CRYSTAL CUTTING METHOD, METHOD OF MANUFACTURING SiC SEMICONDUCTOR DEVICE, AND SiC SEMICONDUCTOR DEVICE

A crystal cutting method includes a step of preparing a crystal structure body constituted of a hexagonal crystal, a first cutting step of cutting the crystal structure body along a [1-100] direction of the hexagonal crystal and forming a first cut portion in the crystal structure body and a second cutting step of cutting the crystal structure body along a [11-20] direction of the hexagonal crystal and forming a second cut portion crossing the first cut portion in the crystal structure body.

TECHNICAL FIELD

The present invention relates to a crystal cutting method, a method for manufacturing an SiC semiconductor device, and an SiC semiconductor device.

BACKGROUND ART

Patent Document 1 discloses a wafer processing method of cutting out a plurality of devices from a single wafer. The wafer is constituted of silicon carbide (SiC), gallium nitride (GaN), lithium tantalate (LT), lithium niobate (LN), etc.

CITATION LIST

Patent Literature

Patent Literature 1: Japanese Patent Application Publication No. 2017-100255

SUMMARY OF INVENTION

Technical Problem

A crystal structure body constituted of a hexagonal crystal has different physical properties according to crystal plane and crystal direction. For example, a crystal structure body constituted of a hexagonal crystal has physical properties of cracking easily along a direction of arrangement of nearest neighboring atoms (hereinafter referred to simply as the “nearest neighbor direction”) and being difficult to crack along an intersecting direction intersecting the nearest neighbor direction (hereinafter referred to simply as the “nearest neighbor direction intersecting direction”).

The present inventors diligently examined steps of cutting a crystal structure body along a nearest neighbor direction and thereafter cutting the crystal structure body along a nearest neighbor direction intersecting direction. As a result, it was discovered that in the second cutting step, a bulging portion bulging along the nearest neighbor direction is formed at a cut portion of the crystal structure body.

In particular, the bulging portion has a tendency of forming with a connection portion of a cut portion formed in the first cutting step and a cut portion formed in the second connection step as a starting point. In the second cutting step, the crystal structure body is cut in a direction in which the atomic arrangement is discontinuous with respect to the nearest neighbor direction. It is therefore considered that a force that holds the atomic arrangement acts in the crystal structure body to form the bulging portion oriented along the nearest neighbor direction at the cut portion.

A preferred embodiment of the present invention provides a crystal cutting method and a method for manufacturing an SiC semiconductor device that enable a crystal structure body constituted of a hexagonal crystal to be cut appropriately from two different directions, and an SiC semiconductor device, manufactured using such a method for manufacturing an SiC semiconductor device.

Solution to Problem

A preferred embodiment of the present invention provides a crystal cutting method including a step of preparing a crystal structure body constituted of a hexagonal crystal, a first cutting step of cutting the crystal structure body along a [1-100] direction of the hexagonal crystal and forming a first cut portion in the crystal structure body and a second cutting step of cutting the crystal structure body along a [11-20] direction of the hexagonal crystal and forming a second cut portion crossing the first cut portion in the crystal structure body.

According to this crystal cutting method, the crystal structure body is cut along the [1-100] direction which is a nearest neighbor direction intersecting direction in the first cutting step. The crystal structure body is cut along the [11-20] direction which is a nearest neighbor direction in the second cutting step.

In the first cutting step, the uncut crystal structure body is cut and therefore stress to the crystal structure body does not become discontinuous. Forming of a bulging portion in the first cut portion can thereby be suppressed. On the other hand, in the second cutting step, stress to the crystal structure body becomes discontinuous because the crystal structure body has been cut in the nearest neighbor direction intersecting direction. However, in the second cutting step, stress is applied to the crystal structure body along the nearest neighbor direction and the crystal structure body is cut along the nearest neighbor direction.

Forming of a bulging portion in the second cut portion can thereby be suppressed and flatness of the first cut portion and the second cut portion can thus be improved. A crystal cutting method that enables a crystal structure body constituted of a hexagonal crystal to be cut appropriately from two different directions can thus be provided.

A preferred embodiment of the present invention provides a crystal cutting method including a step of preparing a SiC crystal structure body constituted of a hexagonal crystal, a first cutting step of cutting the SiC crystal structure body along a [1-100] direction of the hexagonal crystal and forming a first cut portion in the SiC crystal structure body and a second cutting step of cutting the SiC crystal structure body along a [11-20] direction of the hexagonal crystal and forming a second cut portion crossing the first cut portion in the SiC crystal structure body.

According to this crystal cutting method, the SiC crystal structure body is cut along the [1-100] direction which is a nearest neighbor direction intersecting direction in the first cutting step. The SiC crystal structure body is cut along the [11-20] direction which is a nearest neighbor direction in the second cutting step.

In the first cutting step, the uncut SiC crystal structure body is cut and therefore stress to the SiC crystal structure body does not become discontinuous. Forming of a bulging portion in the first cut portion can thereby be suppressed. On the other hand, in the second cutting step, stress to the SiC crystal structure body becomes discontinuous because the SiC crystal structure body has been cut in the nearest neighbor direction intersecting direction. However, in the second cutting step, stress is applied to the SiC crystal structure body along the nearest neighbor direction and the SiC crystal structure body is cut along the nearest neighbor direction.

Forming of a bulging portion in the second cut portion can thereby be suppressed and flatness of the first cut portion and the second cut portion can thus be improved. A crystal cutting method that enables an SiC crystal structure body constituted of a hexagonal crystal to be cut appropriately from two different directions can thus be provided.

A preferred embodiment of the present invention provides a method for manufacturing an SiC semiconductor device comprising, a step of preparing an SiC crystal structure body constituted of a hexagonal crystal, a step of setting a device region of quadrilateral shape having a [1-100] direction side oriented along a [1-100] direction of the hexagonal crystal, and a [11-20] direction side oriented along a [11-20] direction of the hexagonal crystal in the SiC crystal structure body, and forming a functional device in the device region, a first cutting step of cutting the SiC crystal structure body along the [1-100] direction side of the device region and forming a first cut portion in the SiC crystal structure body, and a second cutting step of cutting the SiC crystal structure body along the [11-20] direction side of the device region and forming a second cut portion crossing the first cut portion in the SiC crystal structure body.

According to this method for manufacturing the SiC semiconductor device, the SiC crystal structure body is cut along the [1-100] direction which is a nearest neighbor direction intersecting direction in the first cutting step. The SiC crystal structure body is cut along the [11-20] direction which is a nearest neighbor direction in the second cutting step.

In the first cutting step, the uncut SiC crystal structure body is cut and therefore stress to the SiC crystal structure body does not become discontinuous. Forming of a bulging portion in the first cut portion can thereby be suppressed. On the other hand, in the second cutting step, stress to the SiC crystal structure body becomes discontinuous because the SiC crystal structure body has been cut in the nearest neighbor direction intersecting direction. However, in the second cutting step, stress is applied to the SiC crystal structure body along the nearest neighbor direction and the SiC crystal structure body is cut along the nearest neighbor direction.

Forming of a bulging portion in the second cut portion can thereby be suppressed and flatness of the first cut portion and the second cut portion can thus be improved. A method for manufacturing an SiC semiconductor device that enables an SiC crystal structure body constituted of a hexagonal crystal to be cut appropriately from two different directions can thus be provided.

A preferred embodiment of the present invention provides an SiC semiconductor device including an SiC semiconductor layer that is constituted of a hexagonal crystal and includes a first main surface at one side, a second main surface at another side, a first side surface connecting the first main surface and the second main surface and extending along a [11-20] direction of the hexagonal crystal, and a second side surface connecting the first main surface and the second main surface and extending along a [1-100] direction of the hexagonal crystal, and being not more than 20 μm in an in-plane variation along the [11-20] direction of the hexagonal crystal.

The aforementioned as well as other objects, features, and effects of the present invention will be made clear by the following description of the preferred embodiments, with reference to the accompanying drawings.

DESCRIPTION OF EMBODIMENTS

A crystal structure body constituted of a hexagonal crystal is applied in the preferred embodiments of the present invention. The crystal structure body constituted of the hexagonal crystal may include a material type with a thermal conductivity of not less than 0.35 W/cmK and not more than 25 W/cmK. The crystal structure body constituted of the hexagonal crystal may include a material type with a thermal conductivity exceeding 2.5 W/cmK.

As the crystal structure body constituted of the hexagonal crystal, any of various material types that constitute a hexagonal crystal, such as sapphire (Al2O3), gallium nitride (GaN), silicon carbide (SiC), diamond (C), etc., is applied.

The thermal conductivity increases in the order of sapphire (Al2O3), gallium nitride (GaN), silicon carbide (SiC), and diamond (C). The thermal conductivity of sapphire (Al2O3) is not less than 0.35 W/cmK and not more than 0.45 W/cmK (more specifically, approximately 0.4 W/cmK). That of gallium nitride (GaN) is not less than 1.5 W/cmK and not more than 2.5 W/cmK (more specifically, approximately 2.0 W/cmK).

The thermal conductivity of silicon carbide (SiC) is not less than 4.5 W/cmK and not more than 5.5 W/cmK (more specifically, approximately 4.9 W/cmK). The thermal conductivity of diamond (C) is not less than 10 W/cmK and not more than 25 W/cmK (more specifically, approximately 22 W/cmK).

With the preferred embodiments of the present invention, examples where an SiC crystal structure body constituted of a hexagonal crystal is applied as an example of the crystal structure body constituted of the hexagonal crystal shall be described. The SiC crystal structure body constituted of the hexagonal crystal has a plurality of polytypes including a 2H (hexagonal)-SiC monocrystal, a 4H—SiC monocrystal, and a 6H—SiC monocrystal in accordance with cycle of atomic arrangement. Although, with the preferred embodiments of the present invention, examples where a 4H—SiC monocrystal is applied shall be described, this does not exclude other polytypes and other material types that constitute a hexagonal crystal from the present invention.

The crystal structure body of the 4H—SiC monocrystal shall now be described with reference toFIG.1andFIG.2.FIG.1is a diagram of a unit cell of the 4H—SiC monocrystal applied to the preferred embodiments of the present invention (hereinafter referred to simply as the “unit cell”).FIG.2is a plan view of a silicon plane of the unit cell shown inFIG.1.

Referring toFIG.1andFIG.2, the unit cell includes tetrahedral structures, in each of which four C atoms are bonded to a single Si atom in a tetrahedral arrangement (regular tetrahedral arrangement) relationship. The unit cell has an atomic arrangement in which the tetrahedral structures are layered in a four-layer cycle. The unit cell has a hexagonal prism structure having a regular hexagonal silicon plane, a regular hexagonal carbon plane, and six side planes connecting the silicon plane and the carbon plane.

The silicon plane is an end plane terminated by Si atoms. At the silicon plane, a single Si atom is positioned at each of the six vertices of a regular hexagon and a single Si atom is positioned at a center of the regular hexagon.

The carbon plane is an end plane terminated by C atoms. At the carbon plane, a single C atom is positioned at each of the six vertices of a regular hexagon and a single C atom is positioned at a center of the regular hexagon.

The crystal planes of the unit cell are defined by four coordinate axes (a1, a2, a3, and c) including an a1 axis, an a2 axis, an a3 axis, and a c axis. Of the four coordinate axes, a value of a3 takes on a value of −(a1+a2). The crystal planes of the 4H—SiC monocrystal shall be described below based on the silicon plane as an example of an end plane of a hexagonal crystal.

In a plan view of viewing the silicon plane from the c axis, the a1 axis, the a2 axis, and the a3 axis are respectively set along directions of arrangement of the nearest neighboring Si atoms (hereinafter referred to simply as the “nearest neighbor directions”) based on the Si atom positioned at the center. The a1 axis, the a2 axis, and the a3 axis are set to be shifted by 1200 each in conformance to the arrangement of the Si atoms.

The c axis is set in a direction normal to the silicon plane based on the Si atom positioned at the center. The silicon plane is the (0001) plane. The carbon plane is the (000-1) plane. The side planes of the hexagonal prism include six crystal planes oriented along the nearest neighbor directions in the plan view of viewing the silicon plane from the c axis. More specifically, the side planes of the hexagonal prism include the six crystal planes formed by the nearest neighboring Si atoms.

In the plan view of viewing the silicon plane from the c axis, the side planes of the hexagonal prism include a (10-10) plane, a (01-10) plane, a (−1100) plane, a (−1010) plane, a (0-110) plane, and a (1-100) plane in clockwise order from a tip of the a1 axis.

Diagonals of the hexagonal prism not passing through the center include six crystal planes oriented along intersecting directions intersecting the nearest neighbor directions in the plan view of viewing the silicon plane from the c axis (hereinafter referred to simply as the “nearest neighbor direction intersecting directions”). When viewed on a basis of the Si atom positioned at the center, the nearest neighbor direction intersecting directions are orthogonal directions orthogonal to the nearest neighbor directions. More specifically, the diagonals of the hexagonal prism not passing through the center include the six crystal planes formed by Si atoms that are not nearest neighbors.

In the plan view of viewing the silicon plane from the c axis, the diagonals of the hexagonal prism not passing through the center include a (11-20) plane, a (−2110) plane, a (1-2-10) plane, a (−1-120) plane, a (2-1-10) plane, and a (−12-10) plane.

The crystal directions of the unit cell are defined by directions normal to the crystal planes. A direction normal to the (10-10) plane is a [10-10] direction. A direction normal to the (01-10) plane is a [01-10] direction. A direction normal to the (−1100) plane is a [−1100] direction. A direction normal to the (−1010) plane is a [−1010] direction. A direction normal to the (0-110) plane is a [0-110] direction. A direction normal to the (1-100) plane is a [1-100] direction.

A direction normal to the (11-20) plane is a [11-20] direction. A direction normal to the (−2110) plane is a [−2110] direction. A direction normal to the (1-2-10) plane is a [1-2-10] direction. A direction normal to the (−1-120) plane is a [−1-120] direction. A direction normal to the (2-1-10) plane is a [2-1-10] direction. A direction normal to the (−12-10) plane is a [−12-10] direction.

The hexagonal crystal is six-fold symmetrical and equivalent crystal planes and equivalent crystal directions are present every 60°. For example, the (10-10) plane, the (01-10) plane, the (−1100) plane, the (−1010) plane, the (0-110) plane, and the (1-100) plane form equivalent crystal planes.

Also, the [01-10] direction, the [−1100] direction, the [−1010] direction, the [0-110] direction, the [1-100] direction, and the [10-10] direction form equivalent crystal directions. Also, the [11-20] direction, the [−12-10] direction, the [−2110] direction, the [−1-120] direction, the [1-210] direction, and the [2-1-10] direction form equivalent crystal directions.

The c axis is a [0001] direction ([000-1] direction). The a1 axis is the [2-1-10] direction ([−2110] direction). The a2 axis is the [−12-10] direction ([1-210] direction). The a3 axis is the [−1-120] direction ([11-20] direction).

The [0001] direction and the [000-1] direction are referred to at times simply as the c axis. The (0001) plane and the (000-1) plane are referred to at times simply as c planes. The [11-20] direction and the [−1-120] direction are referred to at times simply as the a axis. The (11-20) plane and the (−1-120) plane are referred to at times simply as a planes. The [1-100] direction and the [−1100] direction are referred to at times simply as the m axis. The (1-100) plane and the (−1100) plane are referred to at times simply as m planes.

FIG.3is a perspective view of a 4H—SiC crystal structure body1that includes a 4H—SiC monocrystal.

In this embodiment, the 4H—SiC crystal structure body1is formed in a plate shape or discoid shape. The 4H—SiC crystal structure body1may be formed in a circular shape (disk shape).

A thickness of the 4H—SiC crystal structure body1may be not less than 1 μm and not more than 1000 μm. The thickness of the 4H—SiC crystal structure body1may be not less than 1 μm and not more than 50 μm, not less than 50 μm and not more than 150 μm, not less than 150 μm and not more than 250 μm, not less than 250 μm and not more than 400 μm, not less than 400 μm and not more than 600 μm, not less than 600 μm and not more than 800 μm, or not less than 800 μm and not more than 1000 μm.

The 4H—SiC crystal structure body1has a first main surface2at one side, a second main surface3at another side, and a side surface4connecting the first main surface2and the second main surface3. The first main surface2and the second main surface3of the 4H—SiC crystal structure body1may have an off angle θ inclined at an angle of not more than 10° in the [11-20] direction with respect to the (0001) plane. The off angle θ is also an angle between a normal direction N of the first main surface2and the second main surface3and the c axis of the 4H—SiC crystal structure body1.

The off angle θ may be not less than 0° and not more than 4°. A state in which the off angle θ is 0° is that in which the normal direction N and the c axis are matched. The off angle θ may exceed 0° and be less than 4°. The off angle θ is typically 2° or 4° and more specifically is set in a range of 2°±10% or a range of 4°±10%.

An orientation flat5which is an example of a marker indicating a crystal orientation is formed on the side surface4of the 4H—SiC crystal structure body1. The orientation flat5is a notched portion formed on the side surface4of the 4H—SiC crystal structure body1. In this embodiment, the orientation flat5extends rectilinearly along the [11-20] direction.

A plurality (for example, two) of orientation flats indicating the crystal orientation may be formed on the side surface4of the 4H—SiC crystal structure body1. In this case, a first orientation flat and a second orientation flat may be formed on the side surface4of the 4H—SiC crystal structure body1. The first orientation flat may be a notched portion extending rectilinearly along the [11-20] direction. The second orientation flat may be a notched portion extending rectilinearly along the [1-100] direction.

An orientation notch constituted of a notched portion recessed toward a central portion of the 4H—SiC crystal structure body1may be formed on the side surface4of the 4H—SiC crystal structure body1in place of the orientation flat5.

The 4H—SiC crystal structure body1includes a first corner portion6connecting the first main surface2and the side surface4, and a second corner portion7connecting the second main surface3and the side surface4. The first corner portion6has a first chamfered portion8that is inclined downward from the first main surface2toward the side surface4. The second corner portion7has a second chamfered portion9that is inclined downward from the second main surface3toward the side surface4.

The first chamfered portion8may be formed in a convexly curved shape. The second chamfered portion9may be formed in a convexly curved shape. The first chamfered portion8and the second chamfered portion9suppress cracking of the 4H—SiC crystal structure body1.

FIG.4is a plan view of a splitting mode of the 4H—SiC crystal structure body1.

The 4H—SiC crystal structure body1has different physical properties according to crystal plane and crystal direction. For example, the 4H—SiC crystal structure body1has physical properties of cracking easily along the nearest neighbor directions and being difficult to crack along the nearest neighbor direction intersecting directions. The nearest neighbor direction intersecting directions are, more specifically, orthogonal directions orthogonal to the nearest neighbor directions.

Referring toFIG.4, when, for example, the 4H—SiC crystal structure body1is split by applying an external force to a center of the 4H—SiC crystal structure body1, the 4H—SiC crystal structure body1is split along six directions based on a center of the first main surface2of the 4H—SiC crystal structure body1.

More specifically, the 4H—SiC crystal structure body1is split along the [11-20] direction, the [−12-10] direction, and the [−2110] direction. The [11-20] direction, the [−12-10] direction, and the [−2110] direction are all nearest neighbor directions.

The 4H—SiC crystal structure body1is difficult to split along a direction orthogonal to the [11-20] direction, a direction orthogonal to the [−12-10] direction, and a direction orthogonal to the [−2110] direction. That is, the 4H—SiC crystal structure body1is difficult to split along the [−1100] direction, the [10-10] direction, and the [01-10]direction. The [−1100] direction, the [10-10] direction, and the [01-10] direction are all nearest neighbor direction intersecting directions.

Processing methods implemented on the 4H—SiC crystal structure body1shall now be described. The following processing methods can also be applied to a method for manufacturing an SiC semiconductor device.

FIG.5AtoFIG.5Dare sectional perspective views of a partial region of the 4H—SiC crystal structure body1shown inFIG.3and are for describing an SiC processing method according to a first preferred embodiment of the present invention.

First, referring toFIG.5A, the 4H—SiC crystal structure body1is prepared as an example of an SiC processing object.

Next, referring toFIG.5B, a processed region10selectively set in the first main surface2of the 4H—SiC crystal structure body1is heated and a modified layer11in which the SiC is modified to a different property is formed. In this step, the modified layer11is formed as a band extending along an arbitrary direction.

The heating of the processed region10may be performed by a method of ablation processing by laser irradiation. In the ablation processing method, an ultraviolet laser may be used. Laser energy, laser pulse duty ratio and laser irradiation speed are respectively set to arbitrary values in accordance with size, shape, thickness, etc., of the modified layer11to be formed.

In the ablation processing method, a depression12recessed from the first main surface2toward the second main surface3is formed in a surface layer portion of the first main surface2. The depression12includes a bottom portion and a side portion. The depression12may be formed in a convergent shape that narrows in opening width from the first main surface2toward the bottom portion. The bottom portion of the depression12may be formed in a shape curved toward the second main surface3.

The depression12includes an opening side corner portion and a bottom portion side corner portion. The opening side corner portion of the depression12connects the first main surface2and the side portion of the depression12. The bottom portion side corner portion of the depression12connects the bottom portion and the side portion of the depression12.

A width W of the depression12may exceed 0 μm and be not more than 10 μm. The width W of the depression12is a width in a direction orthogonal to the direction in which the depression12extends. The width W of the depression12may exceed 0 μm and be not more than 2.5 μm, be not less than 2.5 μm and not more than 5 μm, be not less than 5 μm and not more than 7.5 μm, or be not less than 7.5 μm and not more than 10 μm. If the thickness of the 4H—SiC crystal structure body1is not more than 150 μm, the width W of the depression12preferably exceeds 0 μm and is not more than 5 μm.

A depth D of the depression12may exceed 0 μm and be not more than 30 μm. The depth D of the depression12is a distance in the normal direction N from the first main surface2to a lowermost portion of the depression12. The depth D of the depression12may exceed 0 μm and be not more than 5 μm, be not less than 5 μm and not more than 10 μm, be not less than 10 μm and not more than 15 μm, be not less than 15 μm and not more than 20 μm, be not less than 20 μm and not more than 25 μm, or be not less than 25 μm and not more than 30 μm. If the thickness of the 4H—SiC crystal structure body1is not more than 150 μm, the depth D of the depression12preferably exceeds 0 μm and is not more than 15 μm.

The modified layer11is formed as a film along an inner wall of the depression12. A thickness of a portion of the modified layer11covering a bottom wall of the depression12may be greater than a thickness of portions of the modified layer11covering a side wall of the depression12. The modified layer11may be formed in a uniform thickness along the inner wall of the depression12.

Inside the depression12, the modified layer11defines a recess13. More specifically, the recess13is defined by an outer surface of the modified layer11. The recess13includes a bottom portion and a side portion. The recess13may be formed in a convergent shape that narrows in opening width from the first main surface2toward the bottom portion. The bottom portion of the recess13may be formed in a shape curved toward the second main surface3.

The recess13includes an opening side corner portion and a bottom portion side corner portion. The opening side corner portion of the recess13connects the first main surface2of the 4H—SiC crystal structure body1and the side portion of the recess13. The bottom portion side corner portion of the recess13connects the bottom portion and the side portion of the recess13.

A width WR of the recess13is less than the width W of the depression12. The width WR of the recess13may exceed 0 μm and be less than 10 μm. The width WR of the recess13may exceed 0 μm and be not more than 2.5 μm, be not less than 2.5 μm and not more than 5 μm, be not less than 5 μm and not more than 7.5 μm, or be not less than 7.5 μm and less than 10 μm. If the thickness of the 4H—SiC crystal structure body1is not more than 150 μm, the width WR of the recess13preferably exceeds 0 μm and is less than 5 μm.

A depth DR of the recess13is less than the depth D of the depression12. The depth DR of the recess13may exceed 0 μm and be less than 30 μm. The depth DR of the recess13may exceed 0 μm and be not more than 5 μm, be not less than 5 μm and not more than 10 μm, be not less than 10 μm and not more than 15 μm, be not less than 15 μm and not more than 20 μm, be not less than 20 μm and not more than 25 μm, or be not less than 25 μm and less than 30 μm. If the thickness of the 4H—SiC crystal structure body1is not more than 150 μm, the depth DR of the recess13preferably exceeds 0 μm and is not more than 15 μm.

Next, referring toFIG.5C, corners of the modified layer11are rounded. More specifically, the outer surface of the modified layer11is flattened by removing an unevenness from the outer surface of the modified layer11. A portion of the modified layer11may be removed by an etching method. The etching method may be a dry etching method or may be a wet etching method. Here, a portion of the modified layer11is removed by a plasma etching method as an example of a dry etching method.

The modified layer11has a component differing from that of the 4H—SiC crystal structure body1. An etching rate (etching selectivity) with respect to the modified layer11differs from an etching rate (etching selectivity) with respect to SiC. A portion of the modified layer11can thus be removed appropriately while letting the 4H—SiC crystal structure body1remain. The opening side corner portion of the recess13is thereby rounded to shapes curved toward an inner side of the recess13. Also, the bottom portion side corner portion of the recess13is rounded to shapes curved toward an outer side of the recess13.

By the recess13that is rounded at the opening side corner portion, concentration of stress on the modified layer11can be relaxed at the opening side corner portion. Also, by the recess13that is rounded at the bottom portion side corner portion, concentration of stress on the modified layer11can be relaxed at the bottom portion side corner portion. Undesirable cracks due to stress on the modified layer11can thereby be suppressed.

Next, referring toFIG.5D, the 4H—SiC crystal structure body1may be cleaved with the processed region10as a starting point. More specifically, the 4H—SiC crystal structure body1may be cleaved with the depression12as the starting point. The 4H—SiC crystal structure body1may be cleaved by applying stress to the depression12. In this step, a step of applying thermal stress to the depression12by heating and cooling is performed.

A depression12heating step may be performed by a laser irradiation method. The laser irradiation method may be performed by an infrared laser (for example, a CO2laser). By the depression12heating step, a compressive stress, with the depression12as a starting point, is thermally induced. Laser energy, laser pulse duty ratio and laser irradiation speed are respectively set to arbitrary values in accordance with a magnitude of the stress to be applied to the depression12.

A depression12cooling step may include a step of supplying a cooling fluid to the depression12. The cooling fluid may include water or air or a mixture of water and air (aerosol). By the depression12cooling step, a tensile stress, with the depression12as a starting point, is thermally induced.

The cooling fluid supplying step may include a cooling fluid emission (jetting) step by a coolant jetting method or a cooling gas supplying method. The depression12cooling step may be performed after the depression12heating step or may be performed at the same time as the depression12heating step. The 4H—SiC crystal structure body1is cleaved along the depression12by the compressive stress generated in the depression12heating step and the tensile stress generated in the depression12cooling step.

The cleaved 4H—SiC crystal structure body1has cleavage surfaces14. The cleavage surfaces14are continuous to inclining portions15constituted of residual portions of the depression12. Portions of the modified layer11are exposed at corner portions connecting the first main surface2of the 4H—SiC crystal structure body1and the cleavage surfaces14. The modified layer11is formed along the inclining portions15.

FIG.6is a sectional view of the modified layer11formed in the step ofFIG.5B.FIG.7is a graph of constituents of the modified layer11.FIG.7shows results of examining the components of the 4H—SiC crystal structure body1by a Raman spectroscopy method.

A first region A, a second region B, and a third region C are shown inFIG.6. The first region A represents a surface layer portion of the modified layer11. The surface layer portion of the modified layer11is a region positioned at the first main surface2side of the 4H—SiC crystal structure body1. The second region B represents a bottom portion of the modified layer11. The bottom portion of the modified layer11is a region positioned at the second main surface3side of the 4H—SiC crystal structure body1with respect to the surface layer portion of the modified layer11. The third region C represents a region of the 4H—SiC crystal structure body1outside the modified layer11.

A first curve LA, a second curve LB, and a third curve LC are shown inFIG.7. The first curve LA represents components of the first region A shown inFIG.6. The second curve LB represents components of the second region B shown inFIG.6. The third curve LC represents components of the third region C shown inFIG.6.

The first curve LA has a peak value derived from Si (silicon) in a wavelength range of not less than 500 nm and not more than 550 nm. The second curve LB has a peak value derived from Si (silicon) in the wavelength range of not less than 500 nm and not more than 550 nm and a peak value derived from C (carbon) in a wavelength range of not less than 1300 nm and not more than 1700 nm.

The third curve LC has a peak value derived from SiC (silicon carbide) in a wavelength range of not less than 750 nm and not more than 850 nm. Therefore in the third region C, the modified layer11is not formed and just the 4H—SiC monocrystal is present.

Referring to the first curve LA, a silicon density of the surface layer portion (first region A) of the modified layer11is higher than a carbon density of the surface layer portion of the modified layer11. That is, the surface layer portion of the modified layer11includes an Si modified layer, in which the SiC of the 4H—SiC crystal structure body1is modified to Si. The Si modified layer may include an Si polycrystal. The Si modified layer may include amorphous Si. The Si modified layer may include an Si polycrystal and amorphous Si. The Si modified layer may include an Si amorphous layer as a main constituent.

Referring to the second curve LB, a silicon density of the bottom portion (second region B) of the modified layer11is higher than a carbon density of the bottom portion of the modified layer11. The bottom portion of the modified layer11includes an Si modified layer, in which the SiC of the 4H—SiC crystal structure body1is modified to Si. The Si modified layer may include an Si polycrystal. The Si modified layer may include amorphous Si. The Si modified layer may include an Si polycrystal and amorphous Si. The Si modified layer may include an Si amorphous layer as a main constituent.

Referring to the first curve LA and the second curve LB, the modified layer11has mutually different components in the surface layer portion (first region A) and the bottom portion (second region B). More specifically, the modified layer11has a silicon density that differs along a thickness direction. The silicon density of the bottom portion of the modified layer11is lower than the silicon density of the surface layer portion of the modified layer11. Also, the modified layer11has a carbon density that differs along the thickness direction. The carbon density of the bottom portion of the modified layer11is higher than the carbon density of the surface layer portion of the modified layer11.

From the results of the first curve LA to the third curve LC, it can be understood that the modified layer11forming step includes a step of heating the processed region10to a temperature at which a C atom is eliminated or sublimated from the SiC. The modified layer11is thereby formed in the first main surface2of the 4H—SiC crystal structure body1.

As described above, by the present SiC processing method, an outer surface of the 4H—SiC crystal structure body1can be processed by the modified layer11forming step and the modified layer11removing step. In addition, the 4H—SiC crystal structure body1can also be cleaved using the depression12of the modified layer11.

In particular, by the recess13that is rounded at the opening side corner portion, the concentration of stress on the modified layer11can be relaxed at the opening side corner portion. Also, by the recess13that is rounded at the bottom portion side corner portion, the concentration of stress on the modified layer11can be relaxed at the bottom portion side corner portion. Undesirable cracks due to the stress on the modified layer11can thereby be suppressed.

FIG.8AtoFIG.8Dare sectional perspective views of a partial region of the 4H—SiC crystal structure body1shown inFIG.3and are for describing an SiC processing method according to a second preferred embodiment of the present invention. In the following, description of structures and manufacturing steps corresponding to structures and manufacturing steps described withFIG.5AtoFIG.5Dshall be omitted.

First, referring toFIG.8A, the 4H—SiC crystal structure body1is prepared as an example of the SiC processing object.

Next, referring toFIG.8B, the modified layer11, the depression12and the recess13are formed in the processed region10selectively set in the first main surface2. The modified layer11, the depression12and the recess13are formed through the same step as inFIG.5Bdescribed above.

Next, referring toFIG.8C, an entirety of the modified layer11is removed while letting the 4H—SiC crystal structure body1remain. The modified layer11is removed through the same step as inFIG.5Cdescribed above. The depression12defined by the 4H—SiC crystal structure body1thereby remains in the first main surface2.

In this step, the opening side corner portion of the depression12is rounded to shapes curved toward an inner side of the depression12. Also, the bottom portion side corner portion of the depression12is rounded to shapes curved toward an outer side of the depression12. By the depression12that is rounded at the opening side corner portion, concentration of stress on the depression12can be relaxed at the opening side corner portion. Also, by the depression12that is rounded at the bottom portion side corner portion, concentration of stress on the depression12can be relaxed at the bottom portion side corner portion. Undesirable cracks due to stress on the depression12can thereby be suppressed.

Next, referring toFIG.8D, the 4H—SiC crystal structure body1may be cleaved with the depression12as the starting point. The 4H—SiC crystal structure body1may be cleaved through the same step as inFIG.5Ddescribed above. The cleaved 4H—SiC crystal structure body1has the cleavage surfaces14. The cleavage surfaces14are continuous to the inclining portions15constituted of the residual portions of the depression12.

As described above, by the present SiC processing method, the outer surface of the 4H—SiC crystal structure body1can be processed by the modified layer11forming step and the modified layer11removing step. In addition, the 4H—SiC crystal structure body1can also be cleaved using the depression12formed in the outer surface of the 4H—SiC crystal structure body1through the modified layer11removing step.

In particular, by the depression12that is rounded at the opening side corner portion, the concentration of stress on the depression12can be relaxed at the opening side corner portion. Also, by the depression12that is rounded at the bottom portion side corner portion, the concentration of stress on the depression12can be relaxed at the bottom portion side corner portion. Undesirable cracks due to the stress on the depression12can thereby be suppressed.

FIG.9AtoFIG.9Dare sectional perspective views of a partial region of the 4H—SiC crystal structure body1shown inFIG.3and are for describing an SiC processing method according to a third preferred embodiment of the present invention. In the following, description of structures and manufacturing steps corresponding to structures and manufacturing steps described withFIG.5AtoFIG.5Dshall be omitted.

First, referring toFIG.9A, the 4H—SiC crystal structure body1is prepared as an example of the SiC processing object. In this embodiment, the 4H—SiC crystal structure body1has a laminated structure that includes an SiC semiconductor wafer16and an SiC epitaxial layer17. The SiC epitaxial layer17may have an impurity concentration (for example, an n type impurity concentration) less than an impurity concentration (for example, an n type impurity concentration) of the SiC semiconductor wafer16.

The first main surface2of the 4H—SiC crystal structure body1is formed by the SiC epitaxial layer17. The second main surface3of the 4H—SiC crystal structure body1is formed by the SiC semiconductor wafer16. The side surface4of the 4H—SiC crystal structure body1is formed by the SiC semiconductor wafer16and the SiC epitaxial layer17.

The SiC epitaxial layer17is formed by epitaxially growing SiC from the SiC semiconductor wafer16. A thickness of the SiC epitaxial layer17is less than a thickness of the SiC semiconductor wafer16.

The thickness of the SiC semiconductor wafer16may be not less than 1 μm and less than 1000 μm. The thickness of the SiC semiconductor wafer16may be not less than 1 μm and not more than 50 μm, not less than 50 μm and not more than 150 μm, not less than 150 μm and not more than 250 μm, not less than 250 μm and not more than 400 μm, not less than 400 μm and not more than 600 μm, not less than 600 μm and not more than 800 μm, or not less than 800 μm and not more than 1000 μm.

The thickness of the SiC epitaxial layer17may be not less than 1 μm and not more than 100 μm. The thickness of the SiC epitaxial layer17may be not less than 1 μm and not more than 10 μm, not less than 10 μm and not more than 20 μm, not less than 20 μm and not more than 30 μm, not less than 30 μm and not more than 40 μm, not less than 40 μm and not more than 50 μm, not less than 50 μm and not more than 75 μm, or not less than 75 μm and not more than 100 μm.

Next, referring toFIG.9B, the modified layer11, the depression12and the recess13are formed in the processed region10selectively set in the first main surface2of the 4H—SiC crystal structure body1. The modified layer11, the depression12and the recess13are formed in the SiC epitaxial layer17. The modified layer11, the depression12and the recess13are formed through the same step as inFIG.5Bdescribed above.

Next, referring toFIG.9C, the modified layer11is removed partially and the outer surface of the modified layer11is flattened while letting the 4H—SiC crystal structure body1remain. The modified layer11is removed through the same step as inFIG.5Cdescribed above. The opening side corner portion of the recess13is thereby rounded to shapes curved toward the inner side of the recess13. Also, the bottom portion side corner portion of the recess13is rounded to shapes curved toward the outer side of the recess13.

By the recess13that is rounded at the opening side corner portion, the concentration of stress on the modified layer11can be relaxed at the opening side corner portion. Also, by the recess13that is rounded at the bottom portion side corner portion, the concentration of stress on the modified layer11can be relaxed at the bottom portion side corner portion. Undesirable cracks due to the stress on the modified layer11can thereby be suppressed.

Next, referring toFIG.9D, the 4H—SiC crystal structure body1may be cleaved with the depression12as the starting point. The 4H—SiC crystal structure body1may be cleaved through the same step as inFIG.5Ddescribed above. If the impurity concentration of the SiC semiconductor wafer16is higher than the impurity concentration of the SiC epitaxial layer17, a damping rate of laser light with respect to the SiC semiconductor wafer16is higher than a damping rate of laser light with respect to the SiC epitaxial layer17.

Therefore by irradiating the laser light such that it reaches the SiC semiconductor wafer16, the SiC semiconductor wafer16can be heated efficiently. The compressive stress generated in the depression12heating step and the tensile stress generated in the depression12cooling step can thereby be increased. A cleaving force applied to the 4H—SiC crystal structure body1can thus be increased.

The cleaved 4H—SiC crystal structure body1has the cleavage surfaces14. The cleavage surfaces14are continuous to the inclining portions15constituted of the residual portions of the depression12. Portions of the modified layer11are exposed at the corner portions connecting the first main surface2of the 4H—SiC crystal structure body1and the cleavage surfaces14. The modified layer11is formed along the inclining portions15.

As described above, by the present SiC processing method, an outer surface of the SiC epitaxial layer17can be processed by the modified layer11forming step and the modified layer11removing step. In addition, the 4H—SiC crystal structure body1can also be cleaved using the depression12.

In particular, by the recess13that is rounded at the opening side corner portion, the concentration of stress on the modified layer11can be relaxed at the opening side corner portion. Also, by the recess13that is rounded at the bottom portion side corner portion, the concentration of stress on the modified layer11can be relaxed at the bottom portion side corner portion. Undesirable cracks due to the stress on the modified layer11can thereby be suppressed.

FIG.10AtoFIG.10Dare sectional perspective views of a partial region of the 4H—SiC crystal structure body1shown inFIG.3and are for describing an SiC processing method according to a fourth preferred embodiment of the present invention. In the following, description of structures and manufacturing steps corresponding to structures and manufacturing steps described withFIG.5AtoFIG.5Dshall be omitted.

First, referring toFIG.10A, the 4H—SiC crystal structure body1is prepared as an example of the SiC processing object. In this embodiment, the 4H—SiC crystal structure body1has the laminated structure that includes the SiC semiconductor wafer16and the SiC epitaxial layer17. The SiC epitaxial layer17may have an impurity concentration (for example, an n type impurity concentration) less than the impurity concentration (for example, an n type impurity concentration) of the SiC semiconductor wafer16.

The first main surface2of the 4H—SiC crystal structure body1is formed by the SiC epitaxial layer17. The second main surface3of the 4H—SiC crystal structure body1is formed by the SiC semiconductor wafer16. The side surface4of the 4H—SiC crystal structure body1is formed by the SiC semiconductor wafer16and the SiC epitaxial layer17.

The SiC epitaxial layer17is formed by epitaxially growing SiC from the SiC semiconductor wafer16. The thickness of the SiC epitaxial layer17is less than the thickness of the SiC semiconductor wafer16.

The thickness of the SiC semiconductor wafer16may be not less than 1 μm and less than 1000 μm. The thickness of the SiC semiconductor wafer16may be not less than 1 μm and not more than 50 μm, not less than 50 μm and not more than 150 μm, not less than 150 μm and not more than 250 μm, not less than 250 μm and not more than 400 μm, not less than 400 μm and not more than 600 μm, not less than 600 μm and not more than 800 μm, or not less than 800 μm and not more than 1000 μm.

The thickness of the SiC epitaxial layer17may be not less than 1 μm and not more than 100 μm. The thickness of the SiC epitaxial layer17may be not less than 1 μm and not more than 10 μm, not less than 10 μm and not more than 20 μm, not less than 20 μm and not more than 30 μm, not less than 30 μm and not more than 40 μm, not less than 40 μm and not more than 50 μm, not less than 50 μm and not more than 75 μm, or not less than 75 μm and not more than 100 μm.

Next, referring toFIG.10B, the modified layer11, the depression12and the recess13are formed in the processed region10, selectively set in the first main surface2of the 4H—SiC crystal structure body1. The modified layer11, the depression12and the recess13are formed in the SiC epitaxial layer17. The modified layer11, the depression12and the recess13are formed through the same step as inFIG.5Bdescribed above.

Next, referring toFIG.10C, the entirety of the modified layer11is removed while letting the 4H—SiC crystal structure body1remain. The modified layer11is removed through the same step as inFIG.5Cdescribed above. The depression12, defined by the 4H—SiC crystal structure body1, thereby remains in the first main surface2. In this step, the opening side corner portion of the depression12is rounded to shapes curved toward the inner side of the depression12. Also, the bottom portion side corner portion of the depression12is rounded to shapes curved toward the outer side of the depression12.

By the depression12that is rounded at the opening side corner portion, the concentration of stress on the depression12can be relaxed at the opening side corner portion. Also, by the depression12that is rounded at the bottom portion side corner portion, the concentration of stress on the depression12can be relaxed at the bottom portion side corner portion. Undesirable cracks due to the stress on the depression12can thereby be suppressed.

Next, referring toFIG.10D, the 4H—SiC crystal structure body1may be cleaved with the depression12as the starting point. The 4H—SiC crystal structure body1may be cleaved through the same step as inFIG.5Ddescribed above. If the impurity concentration of the SiC semiconductor wafer16is higher than the impurity concentration of the SiC epitaxial layer17, the damping rate of laser light with respect to the SiC semiconductor wafer16is higher than the damping rate of laser light with respect to the SiC epitaxial layer17.

Therefore by irradiating the laser light such that it reaches the SiC semiconductor wafer16, the SiC semiconductor wafer16can be heated efficiently. The compressive stress generated in the depression12heating step and the tensile stress generated in the depression12cooling step can thereby be increased.

The cleaving force applied to the 4H—SiC crystal structure body1can thus be increased. The cleaved 4H—SiC crystal structure body1has the cleavage surfaces14. The cleavage surfaces14are continuous to the inclining portions15constituted of the residual portions of the depression12.

As described above, by the present SiC processing method, the outer surface of the SiC epitaxial layer17can be processed by the modified layer11forming step and the modified layer11removing step. In addition, the 4H—SiC crystal structure body1can also be cleaved using the depression12.

In particular, by the depression12that is rounded at the opening side corner portion, the concentration of stress on the depression12can be relaxed at the opening side corner portion. Also, by the depression12that is rounded at the bottom portion side corner portion, the concentration of stress on the depression12can be relaxed at the bottom portion side corner portion. Undesirable cracks due to the stress on the depression12can thereby be suppressed.

FIG.11AtoFIG.11Dare sectional perspective views of a partial region of the 4H—SiC crystal structure body1shown inFIG.3and are for describing an SiC processing method according to a fifth preferred embodiment of the present invention. In the following, description of structures and manufacturing steps corresponding to structures and manufacturing steps described withFIG.5AtoFIG.5Dshall be omitted.

First, referring toFIG.11A, the 4H—SiC crystal structure body1is prepared as an example of the SiC processing object. In this embodiment, the 4H—SiC crystal structure body1has the laminated structure that includes the SiC semiconductor wafer16and the SiC epitaxial layer17. The SiC epitaxial layer17may have an impurity concentration (for example, an n type impurity concentration) less than the impurity concentration (for example, an n type impurity concentration) of the SiC semiconductor wafer16.

The first main surface2of the 4H—SiC crystal structure body1is formed by the SiC epitaxial layer17. The second main surface3of the 4H—SiC crystal structure body1is formed by the SiC semiconductor wafer16. The side surface4of the 4H—SiC crystal structure body1is formed by the SiC semiconductor wafer16and the SiC epitaxial layer17.

The SiC epitaxial layer17is formed by epitaxially growing SiC from the SiC semiconductor wafer16. The thickness of the SiC epitaxial layer17is less than the thickness of the SiC semiconductor wafer16.

The thickness of the SiC semiconductor wafer16may be not less than 1 μm and less than 1000 μm. The thickness of the SiC semiconductor wafer16may be not less than 1 μm and not more than 50 μm, not less than 50 μm and not more than 150 μm, not less than 150 μm and not more than 250 μm, not less than 250 μm and not more than 400 μm, not less than 400 μm and not more than 600 μm, not less than 600 μm and not more than 800 μm, or not less than 800 μm and not more than 1000 μm.

The thickness of the SiC epitaxial layer17may be not less than 1 μm and not more than 100 μm. The thickness of the SiC epitaxial layer17may be not less than 1 μm and not more than 10 μm, not less than 10 μm and not more than 20 μm, not less than 20 μm and not more than 30 μm, not less than 30 μm and not more than 40 μm, not less than 40 μm and not more than 50 μm, not less than 50 μm and not more than 75 μm, or not less than 75 μm and not more than 100 μm.

Next, referring toFIG.11B, the modified layer11, the depression12and the recess13are formed in the processed region10, selectively set in the first main surface2of the 4H—SiC crystal structure body1. The modified layer11, the depression12and the recess13are formed through the same step as inFIG.5Bdescribed above.

The modified layer11, the depression12and the recess13are formed in the SiC epitaxial layer17. More specifically, the modified layer11, the depression12and the recess13cross a boundary between the SiC semiconductor wafer16and the SiC epitaxial layer17from the SiC epitaxial layer17and are formed in the SiC semiconductor wafer16as well.

Next, referring toFIG.11C, the modified layer11is removed partially and the outer surface of the modified layer11is flattened while letting the 4H—SiC crystal structure body1remain. The modified layer11is removed through the same step as inFIG.5Cdescribed above. The opening side corner portion of the recess13is thereby rounded to shapes curved toward the inner side of the recess13. Also, the bottom portion side corner portion of the recess13is rounded to shapes curved toward the outer side of the recess13.

By the recess13that is rounded at the opening side corner portion, the concentration of stress on the modified layer11can be relaxed at the opening side corner portion. Also, by the recess13that is rounded at the bottom portion side corner portion, the concentration of stress on the modified layer11can be relaxed at the bottom portion side corner portion. Undesirable cracks due to the stress on the modified layer11can thereby be suppressed.

Next, referring toFIG.11D, the 4H—SiC crystal structure body1may be cleaved with the depression12as the starting point. The 4H—SiC crystal structure body1may be cleaved through the same step as inFIG.5Ddescribed above. If the impurity concentration of the SiC semiconductor wafer16is higher than the impurity concentration of the SiC epitaxial layer17, the damping rate of laser light with respect to the SiC semiconductor wafer16is higher than the damping rate of laser light with respect to the SiC epitaxial layer17.

Therefore by irradiating the laser light such that it reaches the SiC semiconductor wafer16, the SiC semiconductor wafer16can be heated efficiently. In particular in this step, the SiC semiconductor wafer16can be heated via the modified layer11formed inside the SiC semiconductor wafer16.

The compressive stress generated in the depression12heating step and the tensile stress generated in the depression12cooling step can thereby be increased efficiently. The cleaving force applied to the 4H—SiC crystal structure body1can thus be increased efficiently.

The cleaved 4H—SiC crystal structure body1has the cleavage surfaces14. The cleavage surfaces14are continuous to the inclining portions15constituted of the residual portions of the depression12. Portions of the modified layer11are exposed at the corner portions connecting the first main surface2of the 4H—SiC crystal structure body1and the cleavage surfaces14. The modified layer11is formed along the inclining portions15.

As described above, by the present SiC processing method, the outer surface of the SiC epitaxial layer17can be processed by the modified layer11forming step and the modified layer11removing step. In addition, the 4H—SiC crystal structure body1can also be cleaved using the depression12.

In particular, by the recess13that is rounded at the opening side corner portion, the concentration of stress on the modified layer11can be relaxed at the opening side corner portion. Also, by the recess13that is rounded at the bottom portion side corner portion, the concentration of stress on the modified layer11can be relaxed at the bottom portion side corner portion. Undesirable cracks due to the stress on the modified layer11can thereby be suppressed.

FIG.12AtoFIG.12Dare sectional perspective views of a partial region of the 4H—SiC crystal structure body1shown inFIG.3and are for describing an SiC processing method according to a sixth preferred embodiment of the present invention. In the following, description of structures and manufacturing steps corresponding to structures and manufacturing steps described withFIG.5AtoFIG.5Dshall be omitted.

First, referring toFIG.12A, the 4H—SiC crystal structure body1is prepared as an example of the SiC processing object. In this embodiment, the 4H—SiC crystal structure body1has the laminated structure that includes the SiC semiconductor wafer16and the SiC epitaxial layer17. The SiC epitaxial layer17may have an impurity concentration (for example, an n type impurity concentration) less than the impurity concentration (for example, an n type impurity concentration) of the SiC semiconductor wafer16.

The first main surface2of the 4H—SiC crystal structure body1is formed by the SiC epitaxial layer17. The second main surface3of the 4H—SiC crystal structure body1is formed by the SiC semiconductor wafer16. The side surface4of the 4H—SiC crystal structure body1is formed by the SiC semiconductor wafer16and the SiC epitaxial layer17.

The SiC epitaxial layer17is formed by epitaxially growing SiC from the SiC semiconductor wafer16. The thickness of the SiC epitaxial layer17is less than the thickness of the SiC semiconductor wafer16.

The thickness of the SiC semiconductor wafer16may be not less than 1 μm and less than 1000 μm. The thickness of the SiC semiconductor wafer16may be not less than 1 μm and not more than 50 μm, not less than 50 μm and not more than 150 μm, not less than 150 μm and not more than 250 μm, not less than 250 μm and not more than 400 μm, not less than 400 μm and not more than 600 μm, not less than 600 μm and not more than 800 μm, or not less than 800 μm and not more than 1000 μm.

The thickness of the SiC epitaxial layer17may be not less than 1 μm and not more than 100 μm. The thickness of the SiC epitaxial layer17may be not less than 1 μm and not more than 10 μm, not less than 10 μm and not more than 20 μm, not less than 20 μm and not more than 30 μm, not less than 30 μm and not more than 40 μm, not less than 40 μm and not more than 50 μm, not less than 50 μm and not more than 75 μm, or not less than 75 μm and not more than 100 μm.

Next, referring toFIG.12B, the modified layer11, the depression12and the recess13are formed in the processed region10, selectively set in the first main surface2of the 4H—SiC crystal structure body1. The modified layer11, the depression12and the recess13are formed through the same step as inFIG.5Bdescribed above.

The modified layer11, the depression12and the recess13are formed in the SiC epitaxial layer17. More specifically, the modified layer11, the depression12and the recess13cross the boundary between the SiC semiconductor wafer16and the SiC epitaxial layer17from the SiC epitaxial layer17and are formed in the SiC semiconductor wafer16as well.

Next, referring toFIG.12C, the entirety of the modified layer11is removed while letting the 4H—SiC crystal structure body1remain. The modified layer11is removed through the same step as inFIG.5Cdescribed above. The depression12, defined by the SiC semiconductor wafer16and the SiC epitaxial layer17, thereby remains in the first main surface2.

In this step, the opening side corner portion of the depression12is rounded to shapes curved toward the inner side of the depression12. Also, the bottom portion side corner portion of the depression12is rounded to shapes curved toward the outer side of the depression12. By the depression12that is rounded at the opening side corner portion, the concentration of stress on the depression12can be relaxed at the opening side corner portion. Also, by the depression12that is rounded at the bottom portion side corner portion, the concentration of stress on the depression12can be relaxed at the bottom portion side corner portion. Undesirable cracks due to the stress on the depression12can thereby be suppressed.

Next, referring toFIG.12D, the 4H—SiC crystal structure body1may be cleaved with the depression12as the starting point. The 4H—SiC crystal structure body1may be cleaved through the same step as inFIG.5Ddescribed above. If the impurity concentration of the SiC semiconductor wafer16is higher than the impurity concentration of the SiC epitaxial layer17, the damping rate of laser light with respect to the SiC semiconductor wafer16is higher than the damping rate of laser light with respect to the SiC epitaxial layer17.

Therefore by irradiating the laser light such that it reaches the SiC semiconductor wafer16, the SiC semiconductor wafer16can be heated efficiently. In particular in this step, the SiC semiconductor wafer16exposed from the bottom portion of the depression12can be heated directly by the laser light.

The compressive stress generated in the depression12heating step and the tensile stress generated in the depression12cooling step can thereby be increased efficiently. The cleaving force applied to the 4H—SiC crystal structure body1can thus be increased efficiently. The cleaved 4H—SiC crystal structure body1has the cleavage surfaces14. The cleavage surfaces14are continuous to the inclining portions15constituted of the residual portions of the depression12.

As described above, by the present SiC processing method, the outer surface of the SiC epitaxial layer17can be processed by the modified layer11forming step and the modified layer11removing step. In addition, the 4H—SiC crystal structure body1can also be cleaved using the depression12formed in the SiC epitaxial layer17through the modified layer11removing step.

In particular, by the depression12that is rounded at the opening side corner portion, the concentration of stress on the depression12can be relaxed at the opening side corner portion. Also, by the depression12that is rounded at the bottom portion side corner portion, the concentration of stress on the depression12can be relaxed at the bottom portion side corner portion. Undesirable cracks due to the stress on the depression12can thereby be suppressed.

FIG.13AtoFIG.13Dare sectional perspective views of a partial region of the 4H—SiC crystal structure body1shown inFIG.3and are for describing an SiC processing method according to a seventh preferred embodiment of the present invention. In the following, description of structures and manufacturing steps corresponding to structures and manufacturing steps described withFIG.5AtoFIG.5Dshall be omitted.

First, referring toFIG.13A, the 4H—SiC crystal structure body1is prepared as an example of the SiC processing object. In this embodiment, the 4H—SiC crystal structure body1has the laminated structure that includes the SiC semiconductor wafer16and the SiC epitaxial layer17. The SiC epitaxial layer17may have an impurity concentration (for example, an n type impurity concentration) less than the impurity concentration (for example, an n type impurity concentration) of the SiC semiconductor wafer16.

The first main surface2of the 4H—SiC crystal structure body1is formed by the SiC epitaxial layer17. The second main surface3of the 4H—SiC crystal structure body1is formed by the SiC semiconductor wafer16. The side surface4of the 4H—SiC crystal structure body1is formed by the SiC semiconductor wafer16and the SiC epitaxial layer17.

The thickness of the SiC semiconductor wafer16may be not less than 1 μm and less than 1000 μm. The thickness of the SiC semiconductor wafer16may be not less than 1 μm and not more than 50 μm, not less than 50 μm and not more than 150 μm, not less than 150 μm and not more than 250 μm, not less than 250 μm and not more than 400 μm, not less than 400 μm and not more than 600 μm, not less than 600 μm and not more than 800 μm, or not less than 800 μm and not more than 1000 μm.

The thickness of the SiC epitaxial layer17may be not less than 1 μm and not more than 100 μm. The thickness of the SiC epitaxial layer17may be not less than 1 μm and not more than 10 μm, not less than 10 μm and not more than 20 μm, not less than 20 μm and not more than 30 μm, not less than 30 μm and not more than 40 μm, not less than 40 μm and not more than 50 μm, not less than 50 μm and not more than 75 μm, or not less than 75 μm and not more than 100 μm.

Next, referring toFIG.13B, the modified layer11, the depression12and the recess13are formed in the processed region10, selectively set in the second main surface3of the 4H—SiC crystal structure body1instead of the first main surface2of the 4H—SiC crystal structure body1. The modified layer11, the depression12and the recess13are formed in the SiC semiconductor wafer16. The modified layer11, the depression12and the recess13are formed in the second main surface3through the same step as inFIG.5Bdescribed above.

The depression12includes the bottom portion and the side portion. The depression12may be formed in a convergent shape that narrows in opening width from the second main surface3toward the bottom portion. The bottom portion of the depression12may be formed in a shape curved toward the first main surface2. The depression12includes the opening side corner portion and the bottom portion side corner portion. The opening side corner portion of the depression12connects the second main surface3and the side portion of the depression12. The bottom portion side corner portion of the depression12connects the bottom portion and the side portion of the depression12.

The width W of the depression12may exceed 0 μm and be not more than 10 μm. The width W of the depression12is the width in the direction orthogonal to the direction in which the depression12extends. The width W of the depression12may exceed 0 μm and be not more than 2.5 μm, be not less than 2.5 μm and not more than 5 μm, be not less than 5 μm and not more than 7.5 μm, or be not less than 7.5 μm and not more than 10 μm. If the thickness of the 4H—SiC crystal structure body1is not more than 150 μm, the width W of the depression12preferably exceeds 0 μm and is not more than 5 μm.

The depth D of the depression12may exceed 0 μm and be not more than 30 μm. The depth D of the depression12is the distance in the normal direction N from the second main surface3to the lowermost portion of the depression12. The depth D of the depression12may exceed 0 μm and be not more than 5 μm, be not less than 5 μm and not more than 10 μm, be not less than 10 μm and not more than 15 μm, be not less than 15 μm and not more than 20 μm, be not less than 20 μm and not more than 25 μm, or be not less than 25 μm and not more than 30 μm. If the thickness of the 4H—SiC crystal structure body1is not more than 150 μm, the depth D of the depression12preferably exceeds 0 μm and is not more than 15 μm.

The modified layer11is formed as a film along the inner wall of the depression12. The thickness of the portion of the modified layer11covering the bottom wall of the depression12may be greater than the thickness of the portions of the modified layer11covering the side wall of the depression12. The modified layer11may be formed in a uniform thickness along the inner wall of the depression12.

Inside the depression12, the modified layer11defines the recess13. More specifically, the recess13is defined by the outer surface of the modified layer11. The recess13includes the bottom portion and the side portion. The recess13may be formed in a convergent shape that narrows in opening width from the second main surface3toward the first main surface2. The bottom portion of the recess13may be formed in a shape curved toward the first main surface2.

The recess13includes the opening side corner portion and the bottom portion side corner portion. The opening side corner portion of the recess13connects the second main surface3and the side portion of the recess13. The bottom portion side corner portion of the recess13connects the bottom portion and the side portion of the recess13.

The width WR of the recess13is less than the width W of the depression12. The width WR of the recess13may exceed 0 μm and be less than 10 μm. The width WR of the recess13may exceed 0 μm and be not more than 2.5 μm, be not less than 2.5 μm and not more than 5 μm, be not less than 5 μm and not more than 7.5 μm, or be not less than 7.5 μm and less than 10 μm. If the thickness of the 4H—SiC crystal structure body1is not more than 150 μm, the width WR of the recess13preferably exceeds 0 μm and is less than 5 μm.

The depth DR of the recess13is less than the depth D of the depression12. The depth DR of the recess13may exceed 0 μm and be less than 30 μm. The depth DR of the recess13may exceed 0 μm and be not more than 5 μm, be not less than 5 μm and not more than 10 μm, be not less than 10 μm and not more than 15 μm, be not less than 15 μm and not more than 20 μm, be not less than 20 μm and not more than 25 μm, or be not less than 25 μm and less than 30 μm. If the thickness of the 4H—SiC crystal structure body1is not more than 150 μm, the depth DR of the recess13preferably exceeds 0 μm and is not more than 15 μm.

Next, referring toFIG.13C, the modified layer11is removed partially and the outer surface of the modified layer11is flattened while letting the 4H—SiC crystal structure body1remain. The modified layer11is removed through the same step as inFIG.5Cdescribed above. The opening side corner portion of the recess13is thereby rounded to shapes curved toward the inner side of the recess13. Also, the bottom portion side corner portion of the recess13is rounded to shapes curved toward the outer side of the recess13.

By the recess13that is rounded at the opening side corner portion, the concentration of stress on the modified layer11can be relaxed at the opening side corner portion. Also, by the recess13that is rounded at the bottom portion side corner portion, the concentration of stress on the modified layer11can be relaxed at the bottom portion side corner portion. Undesirable cracks due to the stress on the modified layer11can thereby be suppressed.

Next, referring toFIG.13D, the 4H—SiC crystal structure body1may be cleaved with the depression12as the starting point. The 4H—SiC crystal structure body1may be cleaved through the same step as inFIG.5Ddescribed above. If the impurity concentration of the SiC semiconductor wafer16is higher than the impurity concentration of the SiC epitaxial layer17, the damping rate of laser light with respect to the SiC semiconductor wafer16is higher than the damping rate of laser light with respect to the SiC epitaxial layer17.

Therefore by irradiating the laser light such that it reaches the SiC semiconductor wafer16, the SiC semiconductor wafer16can be heated efficiently. In particular in this step, the SiC semiconductor wafer16can be heated by the laser light via the modified layer11. The compressive stress generated in the depression12heating step and the tensile stress generated in the depression12cooling step can thereby be increased efficiently. The cleaving force applied to the 4H—SiC crystal structure body1can thus be increased efficiently.

The cleaved 4H—SiC crystal structure body1has the cleavage surfaces14. The cleavage surfaces14are continuous to the inclining portions15constituted of the residual portions of the depression12. Portions of the modified layer11are exposed at the corner portions connecting the first main surface2of the 4H—SiC crystal structure body1and the cleavage surfaces14. The modified layer11is formed along the inclining portions15.

As described above, by the present SiC processing method, the outer surface of the SiC semiconductor wafer16can be processed by the modified layer11forming step and the modified layer11removing step. In addition, the 4H—SiC crystal structure body1can also be cleaved using the depression12.

In particular, by the recess13that is rounded at the opening side corner portion, the concentration of stress on the modified layer11can be relaxed at the opening side corner portion. Also, by the recess13that is rounded at the bottom portion side corner portion, the concentration of stress on the modified layer11can be relaxed at the bottom portion side corner portion. Undesirable cracks due to the stress on the modified layer11can thereby be suppressed.

FIG.14AtoFIG.14Dare sectional perspective views of a partial region of the 4H—SiC crystal structure body1shown inFIG.3and are for describing an SiC processing method according to an eighth preferred embodiment of the present invention. In the following, description of structures and manufacturing steps corresponding to structures and manufacturing steps described withFIG.5AtoFIG.5Dshall be omitted.

First, referring toFIG.14A, the 4H—SiC crystal structure body1is prepared as an example of the SiC processing object. In this embodiment, the 4H—SiC crystal structure body1has the laminated structure that includes the SiC semiconductor wafer16and the SiC epitaxial layer17. The SiC epitaxial layer17may have an impurity concentration (for example, an n type impurity concentration) less than the impurity concentration (for example, an n type impurity concentration) of the SiC semiconductor wafer16.

The first main surface2of the 4H—SiC crystal structure body1is formed by the SiC epitaxial layer17. The second main surface3of the 4H—SiC crystal structure body1is formed by the SiC semiconductor wafer16. The side surface4of the 4H—SiC crystal structure body1is formed by the SiC semiconductor wafer16and the SiC epitaxial layer17.

The SiC epitaxial layer17is formed by epitaxially growing SiC from the SiC semiconductor wafer16. The thickness of the SiC epitaxial layer17is less than the thickness of the SiC semiconductor wafer16.

The thickness of the SiC semiconductor wafer16may be not less than 1 μm and less than 1000 μm. The thickness of the SiC semiconductor wafer16may be not less than 1 μm and not more than 50 μm, not less than 50 μm and not more than 150 μm, not less than 150 μm and not more than 250 μm, not less than 250 μm and not more than 400 μm, not less than 400 μm and not more than 600 μm, not less than 600 μm and not more than 800 μm, or not less than 800 μm and not more than 1000 μm.

The thickness of the SiC epitaxial layer17may be not less than 1 μm and not more than 100 μm. The thickness of the SiC epitaxial layer17may be not less than 1 μm and not more than 10 μm, not less than 10 μm and not more than 20 μm, not less than 20 μm and not more than 30 μm, not less than 30 μm and not more than 40 μm, not less than 40 μm and not more than 50 μm, not less than 50 μm and not more than 75 μm, or not less than 75 μm and not more than 100 μm.

Next, referring toFIG.14B, the modified layer11, the depression12and the recess13are formed in the processed region10, selectively set in the second main surface3of the 4H—SiC crystal structure body1instead of the first main surface2of the 4H—SiC crystal structure body1. The modified layer11, the depression12and the recess13are formed in the SiC semiconductor wafer16. The modified layer11, the depression12and the recess13are formed in the second main surface3through the same step as inFIG.5Bdescribed above.

The depression12includes the bottom portion and the side portion. The depression12may be formed in a convergent shape that narrows in opening width from the second main surface3toward the bottom portion. The bottom portion of the depression12may be formed in a shape curved toward the first main surface2. The depression12includes the opening side corner portion and the bottom portion side corner portion. The opening side corner portion of the depression12connects the second main surface3and the side portion of the depression12. The bottom portion side corner portion of the depression12connects the bottom portion and the side portion of the depression12.

The width W of the depression12may exceed 0 μm and be not more than 10 μm. The width W of the depression12is the width in the direction orthogonal to the direction in which the depression12extends. The width W of the depression12may exceed 0 μm and be not more than 2.5 μm, be not less than 2.5 μm and not more than 5 μm, be not less than 5 μm and not more than 7.5 μm, or be not less than 7.5 μm and not more than 10 μm. If the thickness of the 4H—SiC crystal structure body1is not more than 150 μm, the width W of the depression12preferably exceeds 0 μm and is not more than 5 μm.

The depth D of the depression12may exceed 0 μm and be not more than 30 μm. The depth D of the depression12is the distance in the normal direction N from the second main surface3to the lowermost portion of the depression12. The depth D of the depression12may exceed 0 μm and be not more than 5 μm, be not less than 5 μm and not more than 10 μm, be not less than 10 μm and not more than 15 μm, be not less than 15 μm and not more than 20 μm, be not less than 20 μm and not more than 25 μm, or be not less than 25 μm and not more than 30 μm. If the thickness of the 4H—SiC crystal structure body1is not more than 150 μm, the depth D of the depression12preferably exceeds 0 μm and is not more than 15 μm.

The modified layer11is formed as a film along the inner wall of the depression12. The thickness of the portion of the modified layer11covering the bottom wall of the depression12may be greater than the thickness of the portions of the modified layer11covering the side wall of the depression12. The modified layer11may be formed in a uniform thickness along the inner wall of the depression12.

Inside the depression12, the modified layer11defines the recess13. More specifically, the recess13is defined by the outer surface of the modified layer11. The recess13includes the bottom portion and the side portion. The recess13may be formed in a convergent shape that narrows in opening width from the second main surface3toward the first main surface2. The bottom portion of the recess13may be formed in a shape curved toward the first main surface2.

The recess13includes the opening side corner portion and the bottom portion side corner portion. The opening side corner portion of the recess13connects the second main surface3and the side portion of the recess13. The bottom portion side corner portion of the recess13connects the bottom portion and the side portion of the recess13.

The width WR of the recess13is less than the width W of the depression12. The width WR of the recess13may exceed 0 μm and be less than 10 μm. The width WR of the recess13may exceed 0 μm and be not more than 2.5 μm, be not less than 2.5 μm and not more than 5 μm, be not less than 5 μm and not more than 7.5 μm, or be not less than 7.5 μm and less than 10 μm. If the thickness of the 4H—SiC crystal structure body1is not more than 150 μm, the width WR of the recess13preferably exceeds 0 μm and is less than 5 μm.

The depth DR of the recess13is less than the depth D of the depression12. The depth DR of the recess13may exceed 0 μm and be less than 30 μm. The depth DR of the recess13may exceed 0 μm and be not more than 5 μm, be not less than 5 μm and not more than 10 μm, be not less than 10 μm and not more than 15 μm, be not less than 15 μm and not more than 20 μm, be not less than 20 μm and not more than 25 μm, or be not less than 25 μm and less than 30 μm. If the thickness of the 4H—SiC crystal structure body1is not more than 150 μm, the depth DR of the recess13preferably exceeds 0 μm and is not more than 15 μm.

Next, referring toFIG.14C, the entirety of the modified layer11is removed while letting the 4H—SiC crystal structure body1remain. The modified layer11is removed through the same step as inFIG.5Cdescribed above. The depression12, defined by the SiC semiconductor wafer16, thereby remains in the second main surface3. In this step, the opening side corner portion of the depression12is rounded to shapes curved toward the inner side of the depression12. Also, the bottom portion side corner portion of the depression12is rounded to shapes curved toward the outer side of the depression12.

By the depression12that is rounded at the opening side corner portion, the concentration of stress on the depression12can be relaxed at the opening side corner portion. Also, by the depression12that is rounded at the bottom portion side corner portion, the concentration of stress on the depression12can be relaxed at the bottom portion side corner portion. Undesirable cracks due to the stress on the depression12can thereby be suppressed.

Next, referring toFIG.14D, the 4H—SiC crystal structure body1may be cleaved with the depression12as the starting point. The 4H—SiC crystal structure body1may be cleaved through the same step as inFIG.5Ddescribed above. If the impurity concentration of the SiC semiconductor wafer16is higher than the impurity concentration of the SiC epitaxial layer17, the damping rate of laser light with respect to the SiC semiconductor wafer16is higher than the damping rate of laser light with respect to the SiC epitaxial layer17.

Therefore by irradiating the laser light such that it reaches the SiC semiconductor wafer16, the SiC semiconductor wafer16can be heated efficiently. In particular in this step, a portion of the SiC semiconductor wafer16exposed from the bottom portion of the depression12can be heated directly by the laser light.

The compressive stress generated in the depression12heating step and the tensile stress generated in the depression12cooling step can thereby be increased efficiently. The cleaving force applied to the 4H—SiC crystal structure body1can thus be increased efficiently. The cleaved 4H—SiC crystal structure body1has the cleavage surfaces14. The cleavage surfaces14are continuous to the inclining portions15constituted of the residual portions of the depression12.

As described above, by the present SiC processing method, the outer surface of the SiC semiconductor wafer16can be processed by the modified layer11forming step and the modified layer11removing step. In addition, the 4H—SiC crystal structure body1can also be cleaved using the depression12.

In particular, by the depression12that is rounded at the opening side corner portion, the concentration of stress on the depression12can be relaxed at the opening side corner portion. Also, by the depression12that is rounded at the bottom portion side corner portion, the concentration of stress on the depression12can be relaxed at the bottom portion side corner portion. Undesirable cracks due to the stress on the depression12can thereby be suppressed.

FIG.15AtoFIG.15Dare sectional perspective views of a partial region of the 4H—SiC crystal structure body1shown inFIG.3and are for describing an SiC processing method according to a ninth preferred embodiment of the present invention. In the following, description of structures and manufacturing steps corresponding to structures and manufacturing steps described withFIG.5AtoFIG.5Dshall be omitted.

First, referring toFIG.15A, the 4H—SiC crystal structure body1is prepared as an example of the SiC processing object. In this embodiment, a covering layer18covering the first main surface2of the 4H—SiC crystal structure body1is formed on the first main surface2. The covering layer18may have a single layer structure constituted of a metal layer or an insulating layer. The covering layer18may have a laminated structure that includes a metal layer and an insulating layer.

As examples of an insulating material of the covering layer18, silicon oxide or silicon nitride can be cited. As examples of a metal material of the covering layer18, aluminum, copper, gold, titanium, titanium nitride, etc., can be cited. The covering layer18may be formed by at least one method among an oxidation processing method, a CVD method, a sputtering method, a vapor deposition method and a plating method.

Next, referring toFIG.15B, the modified layer11, the depression12and the recess13are formed in the processed region10selectively set in the first main surface2of the 4H—SiC crystal structure body1. The modified layer11, the depression12and the recess13are formed in the first main surface2through the same step as inFIG.5Bdescribed above.

In this step, the laser light is irradiated onto the first main surface2via the covering layer18. The covering layer18is melted or sublimated by the irradiation of the laser light. The first main surface2is thereby exposed from the covering layer18. Also, the laser light is continuously irradiated onto a portion of the first main surface2exposed from the covering layer18.

The modified layer11, the depression12and the recess13are thereby formed in the first main surface2. The depression12may be in communication with a portion from which the covering layer18was removed. The modified layer11may cover the covering layer18. The modified layer11may cover the portion from which the covering layer18was removed.

Here, an example where the step of irradiating the laser light onto the 4H—SiC crystal structure body1is performed at the same time as the step of irradiating the laser light onto covering layer18was described. However, the step of irradiating the laser light onto the 4H—SiC crystal structure body1may be performed, upon changing an irradiation condition, etc., after the step of irradiating the laser light onto the covering layer18.

A damping rate of the laser light with respect to the covering layer18is preferably not less than a damping rate of the laser light with respect to the 4H—SiC crystal structure body1. The covering layer18can thereby be melted or sublimated efficiently by the laser energy for the 4H—SiC crystal structure body1.

Next, referring toFIG.15C, the modified layer11is removed partially and the outer surface of the modified layer11is flattened while letting the 4H—SiC crystal structure body1and the covering layer18remain. The modified layer11is removed through the same step as inFIG.5Cdescribed above.

The modified layer11has a component differing from that of the covering layer18. The etching rate (etching selectivity) with respect to the modified layer11differs from an etching rate (etching selectivity) with respect to the covering layer18. A portion of the modified layer11can thus be removed while letting the 4H—SiC crystal structure body1and the covering layer18remain. The opening side corner portion of the recess13is thereby rounded to shapes curved toward the inner side of the recess13. Also, the bottom portion side corner portion of the recess13is rounded to shapes curved toward the outer side of the recess13.

By the recess13that is rounded at the opening side corner portion, the concentration of stress on the modified layer11can be relaxed at the opening side corner portion. Also, by the recess13that is rounded at the bottom portion side corner portion, the concentration of stress on the modified layer11can be relaxed at the bottom portion side corner portion. Undesirable cracks due to the stress on the modified layer11can thereby be suppressed.

Next, referring toFIG.15D, the 4H—SiC crystal structure body1may be cleaved with the depression12as the starting point. The 4H—SiC crystal structure body1may be cleaved through the same step as inFIG.5Ddescribed above. The cleaved 4H—SiC crystal structure body1has the cleavage surfaces14. The cleavage surfaces14are continuous to the inclining portions15constituted of the residual portions of the depression12. Also, the inclining portions15are exposed from the covering layer18.

As described above, by the present SiC processing method, the outer surface of the 4H—SiC crystal structure body1can be processed by the modified layer11forming step and the modified layer11removing step. In addition, the 4H—SiC crystal structure body1can also be cleaved using the depression12formed in the outer surface of the 4H—SiC crystal structure body1through the modified layer11removing step.

In particular, by the recess13that is rounded at the opening side corner portion, the concentration of stress on the modified layer11can be relaxed at the opening side corner portion. Also, by the recess13that is rounded at the bottom portion side corner portion, the concentration of stress on the modified layer11can be relaxed at the bottom portion side corner portion. Undesirable cracks due to the stress on the modified layer11can thereby be suppressed.

With the present preferred embodiment, an example where a portion of the modified layer11is removed from the first main surface2of the 4H—SiC crystal structure body1in the step ofFIG.15Cwas described. However, in the step ofFIG.15C, the entirety of the modified layer11may be removed. The manufacturing method with which the covering layer18is formed is also applicable to the first preferred embodiment to the eighth preferred embodiment described above.

FIG.16AtoFIG.16Dare sectional perspective views of a partial region of the 4H—SiC crystal structure body1shown inFIG.3and are for describing an SiC processing method according to a tenth preferred embodiment of the present invention. In the following, description of structures and manufacturing steps corresponding to structures and manufacturing steps described withFIG.5AtoFIG.5Dshall be omitted.

First, referring toFIG.16A, the 4H—SiC crystal structure body1is prepared as an example of the SiC processing object. In this embodiment, the 4H—SiC crystal structure body1has the laminated structure that includes the SiC semiconductor wafer16and the SiC epitaxial layer17. The SiC epitaxial layer17may have an impurity concentration (for example, an n type impurity concentration) less than the impurity concentration (for example, an n type impurity concentration) of the SiC semiconductor wafer16.

The first main surface2of the 4H—SiC crystal structure body1is formed by the SiC epitaxial layer17. The second main surface3of the 4H—SiC crystal structure body1is formed by the SiC semiconductor wafer16. The side surface4of the 4H—SiC crystal structure body1is formed by the SiC semiconductor wafer16and the SiC epitaxial layer17.

The SiC epitaxial layer17is formed by epitaxially growing SiC from the SiC semiconductor wafer16. The thickness of the SiC epitaxial layer17is less than the thickness of the SiC semiconductor wafer16.

The thickness of the SiC semiconductor wafer16may be not less than 1 μm and less than 1000 μm. The thickness of the SiC semiconductor wafer16may be not less than 1 μm and not more than 50 μm, not less than 50 μm and not more than 150 μm, not less than 150 μm and not more than 250 μm, not less than 250 μm and not more than 400 μm, not less than 400 μm and not more than 600 μm, not less than 600 μm and not more than 800 μm, or not less than 800 μm and not more than 1000 μm.

The thickness of the SiC epitaxial layer17may be not less than 1 μm and not more than 100 μm. The thickness of the SiC epitaxial layer17may be not less than 1 μm and not more than 10 μm, not less than 10 μm and not more than 20 μm, not less than 20 μm and not more than 30 μm, not less than 30 μm and not more than 40 μm, not less than 40 μm and not more than 50 μm, not less than 50 μm and not more than 75 μm, or not less than 75 μm and not more than 100 μm.

In this embodiment, the covering layer18covering the second main surface3of the 4H—SiC crystal structure body1is formed on the second main surface3. The covering layer18may have a single layer structure constituted of a metal layer or an insulating layer. The covering layer18may have a laminated structure that includes a metal layer and an insulating layer.

As examples of the insulating material of the covering layer18, silicon oxide or silicon nitride can be cited. As examples of the metal material of the covering layer18, aluminum, copper, gold, titanium, titanium nitride, etc., can be cited. The covering layer18may be formed by at least one method among the oxidation processing method, the CVD method, the sputtering method, the vapor deposition method, and the plating method.

Next, referring toFIG.16B, the modified layer11, the depression12and the recess13are formed in the processed region10, selectively set in the second main surface3of the 4H—SiC crystal structure body1instead of the first main surface2of the 4H—SiC crystal structure body1. The modified layer11, the depression12and the recess13are formed in the second main surface3through the same step as inFIG.5Bdescribed above.

In this step, the laser light is irradiated onto the second main surface3via the covering layer18. The covering layer18is melted or sublimated by the irradiation of the laser light. The second main surface3is thereby exposed from the covering layer18. Also, the laser light is continuously irradiated onto a portion of the second main surface3exposed from the covering layer18. The modified layer11, the depression12and the recess13are thereby formed in the second main surface3.

Here, an example where the step of irradiating the laser light onto the 4H—SiC crystal structure body1is performed at the same time as the step of irradiating the laser light onto covering layer18was described. However, the step of irradiating the laser light onto the 4H—SiC crystal structure body1may be performed, upon changing an irradiation condition, etc., after the step of irradiating the laser light onto the covering layer18.

The damping rate of the laser light with respect to the covering layer18is preferably not less than the damping rate of the laser light with respect to the 4H—SiC crystal structure body1. The covering layer18can thereby be melted or sublimated efficiently by the laser energy for the 4H—SiC crystal structure body1.

The depression12includes the bottom portion and the side portion. The depression12may be formed in a convergent shape that narrows in opening width from the second main surface3toward the bottom portion. The bottom portion of the depression12may be formed in a shape curved toward the first main surface2. The depression12includes the opening side corner portion and the bottom portion side corner portion. The opening side corner portion of the depression12connects the second main surface3and the side portion of the depression12. The bottom portion side corner portion of the depression12connects the bottom portion and the side portion of the depression12. The depression12may be in communication with the portion from which the covering layer18was removed.

The width W of the depression12may exceed 0 μm and be not more than 10 μm. The width W of the depression12is the width in the direction orthogonal to the direction in which the depression12extends. The width W of the depression12may exceed 0 μm and be not more than 2.5 μm, be not less than 2.5 μm and not more than 5 μm, be not less than 5 μm and not more than 7.5 μm, or be not less than 7.5 μm and not more than 10 μm. If the thickness of the 4H—SiC crystal structure body1is not more than 150 μm, the width W of the depression12preferably exceeds 0 μm and is not more than 5 μm.

The depth D of the depression12may exceed 0 μm and be not more than 30 μm. The depth D of the depression12is the distance in the normal direction N from the second main surface3to the lowermost portion of the depression12. The depth D of the depression12may exceed 0 μm and be not more than 5 μm, be not less than 5 μm and not more than 10 μm, be not less than 10 μm and not more than 15 μm, be not less than 15 μm and not more than 20 μm, be not less than 20 μm and not more than 25 μm, or be not less than 25 μm and not more than 30 μm. If the thickness of the 4H—SiC crystal structure body1is not more than 150 μm, the depth D of the depression12preferably exceeds 0 μm and is not more than 15 μm.

The modified layer11is formed as a film along the inner wall of the depression12. The thickness of a portion of the modified layer11covering a bottom surface of the depression12may be greater than the thickness of the portions of the modified layer11covering the side wall of the depression12. The modified layer11may be formed in a uniform thickness along the inner wall of the depression12. The modified layer11may cover the covering layer18. The modified layer11may cover the portion from which the covering layer18was removed.

Inside the depression12, the modified layer11defines the recess13. More specifically, the recess13is defined by the outer surface of the modified layer11. The recess13includes the bottom portion and the side portion. The recess13may be formed in a convergent shape that narrows in opening width from the second main surface3toward the first main surface2. The bottom portion of the recess13may be formed in a shape curved toward the first main surface2.

The recess13includes the opening side corner portion and the bottom portion side corner portion. The opening side corner portion of the recess13connects the second main surface3and the side portion of the recess13. The bottom portion side corner portion of the recess13connects the bottom portion and the side portion of the recess13.

The width WR of the recess13is less than the width W of the depression12. The width WR of the recess13may exceed 0 μm and be less than 10 μm. The width WR of the recess13may exceed 0 μm and be not more than 2.5 μm, be not less than 2.5 μm and not more than 5 μm, be not less than 5 μm and not more than 7.5 μm, or be not less than 7.5 μm and less than 10 μm. If the thickness of the 4H—SiC crystal structure body1is not more than 150 μm, the width WR of the recess13preferably exceeds 0 μm and is less than 5 μm.

The depth DR of the recess13is less than the depth D of the depression12. The depth DR of the recess13may exceed 0 μm and be less than 30 μm. The depth DR of the recess13may exceed 0 μm and be not more than 5 μm, be not less than 5 μm and not more than 10 μm, be not less than 10 μm and not more than 15 μm, be not less than 15 μm and not more than 20 μm, be not less than 20 μm and not more than 25 μm, or be not less than 25 μm and less than 30 μm. If the thickness of the 4H—SiC crystal structure body1is not more than 150 μm, the depth DR of the recess13preferably exceeds 0 μm and is not more than 15 μm.

Next, referring toFIG.16C, the modified layer11is removed partially and the outer surface of the modified layer11is flattened while letting the 4H—SiC crystal structure body1and the covering layer18remain. The modified layer11is removed through the same step as inFIG.5Cdescribed above.

The modified layer11has a component differing from that of the covering layer18. The etching rate (etching selectivity) with respect to the modified layer11differs from the etching rate (etching selectivity) with respect to the covering layer18. A portion of the modified layer11can thus be removed while letting the 4H—SiC crystal structure body1and the covering layer18remain. The opening side corner portion of the recess13is thereby rounded to shapes curved toward the inner side of the recess13. Also, the bottom portion side corner portion of the recess13is rounded to shapes curved toward the outer side of the recess13.

By the recess13that is rounded at the opening side corner portion, the concentration of stress on the modified layer11can be relaxed at the opening side corner portion. Also, by the recess13that is rounded at the bottom portion side corner portion, the concentration of stress on the modified layer11can be relaxed at the bottom portion side corner portion. Undesirable cracks due to the stress on the modified layer11can thereby be suppressed.

Next, referring toFIG.16D, the 4H—SiC crystal structure body1may be cleaved with the depression12as the starting point. The 4H—SiC crystal structure body1may be cleaved through the same step as inFIG.5Ddescribed above. The cleaved 4H—SiC crystal structure body1has the cleavage surfaces14. The cleavage surfaces14are continuous to the inclining portions15constituted of the residual portions of the depression12. Also, the inclining portions15are exposed from the covering layer18.

As described above, by the present SiC processing method, the outer surface of the 4H—SiC crystal structure body1can be processed by the modified layer11forming step and the modified layer11removing step. In addition, the 4H—SiC crystal structure body1can also be cleaved using the depression12formed in the outer surface of the 4H—SiC crystal structure body1through the modified layer11removing step.

In particular, by the recess13that is rounded at the opening side corner portion, the concentration of stress on the modified layer11can be relaxed at the opening side corner portion. Also, by the recess13that is rounded at the bottom portion side corner portion, the concentration of stress on the modified layer11can be relaxed at the bottom portion side corner portion. Undesirable cracks due to the stress on the modified layer11can thereby be suppressed.

With the present preferred embodiment, an example where a portion of the modified layer11is removed in the step ofFIG.16Cwas described. However, in the step ofFIG.16C, the entirety of the modified layer11may be removed. The manufacturing method with which the covering layer18is formed is also applicable to the first preferred embodiment to the eighth preferred embodiment described above.

FIG.17is a perspective view of the general arrangement of an SiC semiconductor device21according to an eleventh preferred embodiment of the present invention.FIG.18is a plan view of the SiC semiconductor device21shown inFIG.17.FIG.19is a sectional view taken along line XIX-XIX shown inFIG.18.FIG.20is an enlarged view of a region XX shown inFIG.19. The SiC semiconductor device21is a device manufactured using the 4H—SiC crystal structure body1described above.

Referring toFIG.17toFIG.20, the SiC semiconductor device21includes an SiC semiconductor layer22. A thickness of the SiC semiconductor layer22may be not less than 1 μm and less than 1000 μm. The thickness of the SiC semiconductor layer22may be not less than 1 μm and not more than 50 μm, not less than 50 μm and not more than 150 μm, not less than 150 μm and not more than 250 μm, not less than 250 μm and not more than 400 μm, not less than 400 μm and not more than 600 μm, not less than 600 μm and not more than 800 μm, or not less than 800 μm and not more than 1000 μm.

The SiC semiconductor layer22has a first main surface23at one side, a second main surface24at another side, and side surfaces25A,25B,25C and25D connecting the first main surface23and the second main surface24. In this embodiment, the side surfaces25A to25D are all constituted of cut surfaces. More specifically, the side surfaces25A to25D are constituted of cleavage surfaces.

The first main surface23and the second main surface24are formed in quadrilateral shapes (rectangular shapes in this embodiment) in a plan view as viewed in a normal direction N to the surfaces (hereinafter referred to simply as “plan view”). The side surface25A opposes the side surface25C. The side surface25B opposes the side surface25D.

The SiC semiconductor layer22includes a 4H—SiC monocrystal. The first main surface23and the second main surface24face the c planes of the 4H—SiC monocrystal. The first main surface23faces the (0001) plane and the second main surface24faces the (000-1) plane.

The first main surface23and the second main surface24have an off angle θ inclined at an angle of not more than 100 in the [11-20] direction with respect to the (0001) plane. The off angle θ may be not less than 0° and not more than 2°, not less than 2° and not more than 4°, not less than 4° and not more than 6°, not less than 6° and not more than 8°, or not less than 8° and not more than 10°. The off angle θ is preferably not less than 0° and not more than 4°.

A state where the off angle θ is 0° is that in which the normal direction N and the c axis are matched. The off angle θ may exceed 0° and be less than 4°. The off angle θ is typically 2° or 4° and more specifically is set in a range of 2°±10% or a range of 4°±10%.

The side surfaces25A to25D respectively extend as planes along the normal direction N. A length of each of the side surfaces25A to25D may be not less than 1 mm and not more than 10 mm. The length of the side surfaces25A to25D may be not less than 1 mm and not more than 2.5 mm, not less than 2.5 mm and not more than 5 mm, not less than 5 mm and not more than 7.5 mm, or not less than 7.5 mm and not more than 10 mm. The length of the side surfaces25A to25D is preferably not less than 2 mm and not more than 5 mm.

The side surfaces25A to25D extend in a nearest neighbor direction and a nearest neighbor direction intersecting direction. More specifically, the nearest neighbor direction intersecting direction is an orthogonal direction orthogonal to the nearest neighbor direction. In this embodiment, the side surfaces25A to25D extend in the [11-20] direction and the [1-100] direction.

The side surface25A and the side surface25C are formed along the [11-20] direction. The side surface25B and the side surface25D are formed along the [1-100] direction. The side surface25A and the side surface25C may be formed along the [1-100] direction and the side surface25B and the side surface25D may be formed along the [11-20] direction instead.

In-plane variations of the side surfaces25A to25D are not more than 20 μm. The in-plane variations along the [11-20] direction of the side surfaces25B and25D that extend along the [1-100] direction are not more than 20 μm. More specifically the in-plane variations of the side surfaces25B and25D are not more than 10 μm.

The in-plane variations along the [1-100] direction of the side surfaces25A and25C that extend along the [11-20] direction are not more than 20 μm. More specifically, the in-plane variations of the side surfaces25A and25C are not more than 10 μm.

An in-plane variation is defined by a maximum value of distances between a reference virtual line and measurement virtual lines set in one of the side surfaces25A to25D selected from the side surfaces25A to25D. The reference virtual line is a straight line joining two corner portions of the SiC semiconductor22in plan view and is set in the selected one of the side surfaces25A to25D. A measurement virtual line is a straight line extending in parallel to the reference virtual line in plan view and is set to be tangent to a top portion or a base portion of a bulge (tortuosity) present on the selected one of the side surfaces25A to25D.

For example, the distance between the reference virtual line and the measurement virtual line tangent to the top portion of a bulge (tortuosity) and the distance between the reference virtual line and the measurement virtual line tangent to the base portion of the bulge (tortuosity) are measured. The in-plane variation of the selected one of the side surfaces25A to25D is defined by the maximum value of the measured distances between the reference virtual line and the measured virtual lines.

In this embodiment, the SiC semiconductor layer22has a laminated structure that includes an n+type SiC semiconductor substrate31and an n type SiC epitaxial layer32. The second main surface24of the SiC semiconductor layer22is formed by the SiC semiconductor substrate31. The first main surface23of the SiC semiconductor layer22is formed by the SiC epitaxial layer32. The side surfaces25A to25D of the SiC semiconductor layer22are formed by the SiC semiconductor substrate31and the SiC epitaxial layer32.

A thickness of the SiC semiconductor substrate31may be not less than 1 μm and less than 1000 μm. The thickness of the SiC semiconductor substrate31may be not less than 1 μm and not more than 50 μm, not less than 50 μm and not more than 150 μm, not less than 150 μm and not more than 250 μm, not less than 250 μm and not more than 400 μm, not less than 400 μm and not more than 600 μm, not less than 600 μm and not more than 800 μm, or not less than 800 μm and not more than 1000 μm. The thickness of the SiC semiconductor substrate31is preferably not less than 50 μm and not more than 150 μm. By making the thickness of the SiC semiconductor substrate31small, reduction of resistance value can be achieved by shortening of a current path.

The SiC epitaxial layer32has a thickness less than the thickness of the SiC semiconductor substrate31. The thickness of the SiC epitaxial layer32may be not less than 1 μm and not more than 100 μm. The thickness of the SiC epitaxial layer32may be not less than 1 μm and not more than 10 μm, not less than 10 μm and not more than 20 μm, not less than 20 μm and not more than 30 μm, not less than 30 μm and not more than 40 μm, not less than 40 μm and not more than 50 μm, not less than 50 μm and not more than 75 μm, or not less than 75 μm and not more than 100 μm. The thickness of the SiC epitaxial layer32is preferably not less than 5 μm and not more than 20 μm.

An n type impurity concentration of the SiC epitaxial layer32is not more than an n type impurity concentration of the SiC semiconductor substrate31. The n type impurity concentration of the SiC semiconductor substrate31may be not less than 1.0×1018cm−3and not more than 1.0×1021cm−3. The n type impurity concentration of the SiC epitaxial layer32may be not less than 1.0×1015cm−3and not more than 1.0×1018cm−3.

The SiC semiconductor layer22includes an active region33and an outer region34. The active region33includes an impurity region33A having an n type impurity and/or a p type impurity. The active region33is a region in which a semiconductor functional device is formed by the impurity region33A. The semiconductor functional device may include a diode. The semiconductor functional device may include a transistor. The semiconductor functional device may include a field effect transistor.

In plan view, the active region33may be set in a central portion of the SiC semiconductor layer22at intervals toward an inner region from the side surfaces25A to25D. In plan view, the active region33may be set to a quadrilateral shape having four sides parallel to the four side surfaces25A to25D.

The outer region34is a region at an outer side of the active region33. The outer region34may be set in a region between the side surfaces25A to25D and peripheral edges of the active region33. In plan view, the outer region34may be set to an annular shape (for example, an endless shape) surrounding the active region33.

The SiC semiconductor device21includes an insulating layer35formed on the first main surface23. The insulating layer35selectively covers the first main surface23. The insulating layer35may include silicon oxide or silicon nitride. A peripheral edge portion of the insulating layer35is continuous to the side surfaces25A to25D. An opening39selectively exposing the active region33is formed in the insulating layer35.

The SiC semiconductor device21includes a first electrode layer36formed on the first main surface23. More specifically, the first electrode layer36is formed on the insulating layer35. The first electrode layer36may include a conductive polysilicon or a metal. The first electrode layer36enters into the opening39from above the insulating layer35. Inside the opening39, the first electrode layer36is electrically connected to the active region33.

The SiC semiconductor device21includes a resin layer37formed on the first main surface23. More specifically, the resin layer37is formed on the insulating layer35. The resin layer37selectively covers the first electrode layer36. A peripheral edge portion46of the resin layer37described above is formed at intervals toward an inner region from the side surfaces25A to25D. The resin layer37thereby exposes a peripheral edge portion of the SiC semiconductor layer22in plan view.

The resin layer37may include a negative type or positive type photosensitive resin. In this embodiment, the resin layer37includes a polybenzoxazole as an example of a positive type photosensitive resin. The resin layer37may include a polyimide as an example of a negative type photosensitive resin instead. An opening40exposing the first electrode layer36is formed in the resin layer37.

The SiC semiconductor device21includes a second electrode layer38formed on the second main surface24. The second electrode layer38covers the second main surface24. The second electrode layer38is electrically connected to the second main surface24. The second electrode layer38may include a conductive polysilicon or a metal.

An inclining portion41that inclines downwardly from the first main surface23of the SiC semiconductor layer22toward the side surfaces25A to25D is formed at corner portions connecting the first main surface23and the side surfaces25A to25D. The corner portions of the SiC semiconductor layer22include corner portions connecting the first main surface23and the side surfaces25A and25C and extending along the [11-20] direction. The corner portions of the SiC semiconductor layer22include corner portions connecting the first main surface23and the side surfaces25B and25D and extending along the [1-100] direction.

More specifically, the inclining portion41is formed in the SiC epitaxial layer32. The inclining portion41is formed in a region at the first main surface23side with respect to a boundary region between the SiC semiconductor substrate31and the SiC epitaxial layer32. The SiC epitaxial layer32is thus exposed from the inclining portion41.

The inclining portion41is formed by an inner wall of a depression recessed from the first main surface23toward the second main surface24. The inclining portion41has an upper side end portion41aand a lower side end portion41b. The upper side end portion41aof the inclining portion41is positioned at the first main surface23side. The lower side end portion41bof the inclining portion41is positioned at the second main surface24side.

The upper side end portion41aof the inclining portion41extends from the SiC epitaxial layer32toward the insulating layer35and is continuous to the insulating layer35. That is, the SiC epitaxial layer32and the insulating layer35are exposed from the inclining portion41. Also, the peripheral edge portion of the insulating layer35is formed at an inner region of the SiC semiconductor layer22with respect to the side surfaces25A to25D.

The upper side end portion41aof the inclining portion41is connected to an upper surface of the insulating layer35. An upper side connection portion41cof the inclining portion41that connects the upper side end portion41aof the inclining portion41and the upper surface of the insulating layer35may be formed in a shape curved toward an outer side of the SiC semiconductor layer22. The lower side end portion41bof the inclining portion41is connected to the side surfaces25A to25D. The lower side end portion41bof the inclining portion41may be formed in a shape curved toward the second main surface24.

A width WI of the inclining portion41may be not more than the in-plane variations of the side surfaces25A to25D. The width WI of the inclining portion41may be less than the in-plane variations of the side surfaces25A to25D. The width WI of the inclining portion41is a width in a direction orthogonal to a direction in which the inclining portion41extends in plan view.

The width WI of the inclining portion41may exceed 0 μm and be not more than 10 μm. The width WI of the inclining portion41may exceed 0 μm and be not more than 2 μm, be not less than 2 μm and not more than 4 μm, be not less than 4 μm and not more than 6 μm, be not less than 6 μm and not more than 8 μm, or be not less than 8 μm and not more than 10 μm. If the thickness of the SiC semiconductor layer22is not more than 150 μm, the width WI of the inclining portion41preferably exceeds 0 μm and is not more than 5 μm. More preferably, the width WI of the inclining portion41exceeds 0 μm and is not more than 2.5 μm.

A depth D of the inclining portion41may exceed 0 μm and be not more than 30 μm. The depth D of the inclining portion41is a distance in the normal direction N from the first main surface23to the lower side end portion of the inclining portion41. The depth D of the inclining portion41may exceed 0 μm and be not more than 5 μm, be not less than 5 μm and not more than 10 μm, be not less than 10 μm and not more than 15 μm, be not less than 15 μm and not more than 20 μm, be not less than 20 μm and not more than 25 μm, or be not less than 25 μm and not more than 30 μm. If the thickness of the SiC semiconductor layer22is not more than 150 μm, the depth D of the inclining portion41preferably exceeds 0 μm and is not more than 15 μm.

The SiC semiconductor device21includes a modified layer42which is formed in regions of the side surfaces25A to25D at the first main surface23side and in which the SiC is modified to a different property. In this embodiment, the modified layer is formed in the SiC epitaxial layer32. More specifically, the modified layer42is formed in a region at the first main surface23side with respect to the boundary region between the SiC semiconductor substrate31and the SiC epitaxial layer32.

The modified layer42is formed along the corner portions connecting the first main surface23and the side surfaces25A to25D. More specifically, the modified layer42is formed at the corner portions connecting the first main surface23and the side surfaces25A and25C and extending along the [11-20] direction. Also, the modified layer42is formed at the corner portions connecting the first main surface23and the side surfaces25B and25D and extending along the [1-100] direction.

The modified layer42extends as a band on the side surfaces25A to25D along directions parallel to the first main surface23. That is, the modified layer42extends as a band along the [1-100] direction and the [11-20] direction. At the side surfaces25A to25D, the modified layer42is formed in an annular shape (for example, an endless shape) surrounding the active region33.

The modified layer42is formed as a film along the inclining portion41of the SiC semiconductor layer22. A thickness of a portion of the modified layer42covering a bottom wall of the inclining portion41may be greater than a thickness of a portion of the modified layer42covering a side wall of the inclining portion41. The modified layer42may be formed in a uniform thickness along inner wall of the inclining portion41.

The modified layer42includes an upper side covering portion42aand a lower side covering portion42b. The upper side covering portion42aof the modified layer42covers the upper side end portion41aof the inclining portion41. The upper side covering portion42aof the modified layer42covers the SiC epitaxial layer32. The upper side covering portion42aof the modified layer42extends from the SiC epitaxial layer32toward the insulating layer35and covers the insulating layer35. The upper side covering portion42aof the modified layer42may be formed in a shape curved toward the outer side of the SiC semiconductor layer22.

The lower side covering portion42bof the modified layer42covers the lower side end portion41bof the inclining portion41. The lower side covering portion42bof the modified layer42covers the SiC epitaxial layer32. The lower side covering portion42bof the modified layer42includes a connection portion42cconnected to the side surfaces25A to25D. The connection portion42cof the modified layer42may be a cleavage portion of the modified layer42. The connection portion42cof the modified layer42may be formed flush with the side surfaces25A to25D.

The modified layer42is exposed from the peripheral edge portion46of the resin layer37. The peripheral edge portion46of the resin layer37is a portion in which dicing streets were formed in a process of cutting out the SiC semiconductor device21from the 4H—SiC crystal structure body1. By exposing the modified layer42from the resin layer37, it becomes unnecessary to physically cut the resin layer37. The SiC semiconductor device21can thus be cut out smoothly from the 4H—SiC crystal structure body1while achieving appropriate protection of the active region33by the resin layer37.

A width WM of the modified layer42may be not more than the in-plane variations of the side surfaces25A to25D. The width WM of the modified layer42may be less than the in-plane variations of the side surfaces25A to25D. The width WM of the modified layer42is a width in a direction orthogonal to a direction in which the modified layer42extends in plan view.

The width WM of the modified layer42may exceed 0 μm and be not more than 10 μm. The width WM of the modified layer42may exceed 0 μm and be not more than 2 μm, be not less than 2 μm and not more than 4 μm, be not less than 4 μm and not more than 6 μm, be not less than 6 μm and not more than 8 μm, or be not less than 8 μm and not more than 10 μm. If the thickness of the SiC semiconductor layer22is not more than 150 μm, the width WM of the modified layer42preferably exceeds 0 μm and is not more than 5 μm. More preferably, the width WM of the modified layer42exceeds 0 μm and is not more than 2.5 μm.

A thickness T of the modified layer42may exceed 0 μm and be not more than 30 μm. The thickness T of the modified layer42is a thickness of the modified layer42along the normal direction N. The thickness T of the modified layer42may exceed 0 μm and be not more than 5 μm, be not less than 5 μm and not more than 10 μm, be not less than 10 μm and not more than 15 μm, be not less than 15 μm and not more than 20 μm, be not less than 20 μm and not more than 25 μm, or be not less than 25 μm and not more than 30 μm. If the thickness of the SiC semiconductor layer22is not more than 150 μm, the thickness T of the modified layer42preferably exceeds 0 μm and is not more than 15 μm.

FIG.21is an enlarged view of a region XXI shown inFIG.17.FIG.22is a graph of constituents of the modified layer42.FIG.22shows results of examining the components of the SiC semiconductor layer22by the Raman spectroscopy method.

A first region A, a second region B, and a third region C are shown inFIG.21. The first region A represents a surface layer portion of the modified layer42. The surface layer portion of the modified layer42is a region of the modified layer42positioned at the first main surface23side of the SiC semiconductor layer22(here, the upper side covering portion42a).

The second region B represents a bottom portion of the modified layer42. The bottom portion of the modified layer42is a region of the modified layer42positioned at the second main surface24side with respect to the surface layer portion of the modified layer42(here, the lower side covering portion42b). The third region C represents a region of the SiC semiconductor layer22outside the modified layer42(here, the SiC epitaxial layer32).

A first curve LA, a second curve LB, and a third curve LC are shown inFIG.22. The first curve LA represents components of the first region A shown inFIG.21. The second curve LB represents components of the second region B shown inFIG.21. The third curve LC represents components of the third region C shown inFIG.21.

The first curve LA has a peak value derived from Si (silicon) in a wavelength range of not less than 500 nm and not more than 550 nm. The second curve LB has a peak value derived from Si (silicon) in the wavelength range of not less than 500 nm and not more than 550 nm and a peak value derived from C (carbon) in a wavelength range of not less than 1300 nm and not more than 1700 nm.

The third curve LC has a peak value derived from SiC (silicon carbide) in a wavelength range of not less than 750 nm and not more than 850 nm. Therefore in the third region C, the modified layer42is not formed and just the 4H—SiC monocrystal is present.

Referring to the first curve LA, a silicon density of the surface layer portion (first region A) of the modified layer42is higher than a carbon density of the surface layer portion of the modified layer42. That is, the surface layer portion of the modified layer42includes an Si modified layer, in which the SiC of the 4H—SiC crystal structure body1is modified to Si. The Si modified layer may include an Si polycrystal. The Si modified layer may include amorphous Si. The Si modified layer may include an Si polycrystal and amorphous Si. The Si modified layer may include an Si amorphous layer as a main constituent.

Referring to the second curve LB, a silicon density of the bottom portion (second region B) of the modified layer42is higher than a carbon density of the bottom portion of the modified layer42. The bottom portion of the modified layer42includes an Si modified layer, in which the SiC of the 4H—SiC crystal structure body1is modified to Si. The Si modified layer may include an Si polycrystal. The Si modified layer may include amorphous Si. The Si modified layer may include an Si polycrystal and amorphous Si. The Si modified layer may include an Si amorphous layer as a main constituent.

Referring to the first curve LA and the second curve LB, the modified layer42has mutually different components in the surface layer portion (first region A) and the bottom portion (second region B). More specifically, the modified layer42has a silicon density that differs along a thickness direction. The silicon density of the bottom portion of the modified layer42is lower than the silicon density of the surface layer portion of the modified layer42. Also, the modified layer42has a carbon density that differs along the thickness direction. The carbon density of the bottom portion of the modified layer42is higher than the carbon density of the surface layer portion of the modified layer42.

FIG.23is a perspective view of the 4H—SiC crystal structure body1used in manufacturing the SiC semiconductor device21shown inFIG.17.

Referring toFIG.23, in a method for manufacturing the SiC semiconductor device21, the 4H—SiC crystal structure body1that has a laminated structure including an SiC semiconductor wafer51and an SiC epitaxial layer52is used. The SiC semiconductor wafer51is a base of the SiC semiconductor substrate31. The SiC epitaxial layer52is a base of the SiC epitaxial layer32. The SiC epitaxial layer52is formed by epitaxially growing SiC from the SiC semiconductor wafer51.

The first main surface2of the 4H—SiC crystal structure body1is formed by the SiC epitaxial layer52. The second main surface3of the 4H—SiC crystal structure body1is formed by the SiC semiconductor wafer51. The side surface4of the 4H—SiC crystal structure body1is formed by the SiC semiconductor wafer51and the SiC epitaxial layer52.

In the method for manufacturing the SiC semiconductor device21, a plurality of device regions53corresponding to the SiC semiconductor devices21are set in the first main surface2of the 4H—SiC crystal structure body1. The plurality of device regions53are set in a matrix array at intervals in the [1-100] direction and the [11-20] direction. Each of the device regions53has sides oriented along the [1-100] direction and sides oriented along the [11-20] direction.

The plurality of device regions53are defined by lattice-shaped intended cutting lines54extending along the [1-100] direction and the [11-20] direction. More specifically, the intended cutting lines54include a plurality of first intended cutting lines55and a plurality of second intended cutting lines56. The plurality of first intended cutting lines55respectively extend along the [1-100] direction. The plurality of second intended cutting lines56respectively extend along the [11-20] direction.

After predetermined structures are formed in the 4H—SiC crystal structure body1, the plurality of SiC semiconductor devices21are cut out by cutting the 4H—SiC crystal structure body1along the intended cutting lines54.

FIG.24AtoFIG.24Lare sectional perspective views of a partial region of the 4H—SiC crystal structure body1shown inFIG.23and are for describing an example of a method for manufacturing the SiC semiconductor device21shown inFIG.17.

InFIG.24A to24L, four device regions53are indicated as a portion of regions of the 4H—SiC crystal structure body1. Also, an enlarged end face diagram of a partial region of the device regions53as viewed from the [1-100] direction is shown inFIG.24ItoFIG.24K. The technical ideas described withFIG.9AtoFIG.9Dabove are incorporated inFIG.24AtoFIG.24L.

Next, referring toFIG.24B, a plurality of the active regions33are respectively formed in the plurality of device regions53. The plurality of active regions33are respectively formed by introducing a p type impurity and/or an n type impurity into the plurality of device regions53.

Next, referring toFIG.24C, the insulating layer35is formed on the first main surface2of the 4H—SiC crystal structure body1. The insulating layer35includes silicon oxide. The insulating layer35may be formed by a CVD method or a thermal oxidation processing method. In this embodiment, the insulating layer35is formed by thermal oxidation processing of the first main surface2.

Next, referring toFIG.24D, unnecessary portions of the insulating layer35are removed. A plurality of the openings39are thereby formed in the insulating layer35. The respective openings39expose the active regions33of the respective device regions53. The unnecessary portions of the insulating layer35may be removed by an etching method via a mask (not shown).

Next, referring toFIG.24E, the first electrode layer36is formed on the insulating layer35. In the first electrode layer36forming step, first, a conductive material is deposited by a sputtering method or a CVD method on the insulating layer35. Next, unnecessary portions of the conductive material are removed by an etching method via a mask (not shown). The respective first electrode layers36are thereby formed in the respective device regions53.

Next, referring toFIG.24F, a resin is coated onto the insulating layer35to form the resin layer37that covers the first electrode layers36.

Next, referring toFIG.24G, the resin layer37is selectively exposed and thereafter developed. The resin layers37having the openings40that expose the respective first electrode layers36and the peripheral edge portions46that expose the intended cutting lines54are formed on the insulating layer35. The peripheral edge portions46of the resin layer37define the dicing streets.

Next, referring toFIG.24H, the second electrode layer38is formed on the second main surface3of the 4H—SiC crystal structure body1. The second electrode layer38is formed by depositing a conductive material on the second main surface3by a sputtering method or a CVD method.

Next, referring toFIG.24I, the intended cutting lines54are heated to form the modified layers42(first modified layers) in which the SiC is modified to a different property. Here, an example where the first intended cutting lines55along the [1-100] direction is heated first is illustrated.

More specifically, the modified layer42forming step includes a step of heating the intended cutting lines54to a temperature at which a C atom is eliminated or sublimated from the SiC. The modified layers42are thereby formed in the first main surface2of the 4H—SiC crystal structure body1.

The heating of the intended cutting lines54may be performed by the method of ablation processing by laser irradiation. In the ablation processing method, an ultraviolet laser may be used. The laser energy, laser pulse duty ratio and laser irradiation speed are respectively set to arbitrary values in accordance with size, shape, thickness, etc., of the modified layers42to be formed.

In the ablation processing method, the laser light is irradiated onto the first main surface2via the insulating layer35. The insulating layer35is melted or sublimated by the irradiation of the laser light. The first main surface2is thereby exposed from the insulating layer35. Also, the laser light is continuously irradiated onto a portion of the first main surface2exposed from the insulating layer35. The modified layers42are thereby formed in the first main surface2.

Also in this step, depressions57penetrating through the insulating layer35and recessed from the first main surface2toward the second main surface3are formed. Each depression57includes a bottom portion and side portion. The depression57may be formed in a convergent shape that narrows in opening width from the first main surface2toward the bottom portion. The bottom portion of the depression57may be formed in a shape curved toward the second main surface3.

A width W of the depression57may exceed 0 μm and be not more than 10 μm. The width W of the depression57may exceed 0 μm and be not more than 10 μm. The width W of the depression57is a width in a direction orthogonal to the direction in which the depression57extends. The width W of the depression57may exceed 0 μm and be not more than 2.5 μm, be not less than 2.5 μm and not more than 5 μm, be not less than 5 μm and not more than 7.5 μm, or be not less than 7.5 μm and not more than 10 μm. If the thickness of the 4H—SiC crystal structure body1is not more than 150 μm, the width W of the depression57preferably exceeds 0 μm and is not more than 5 μm.

Each modified layer42is formed as a film along inner wall of a depression57. A thickness of a portion of the modified layer42covering a bottom wall of the depression57may be greater than a thickness of portions of the modified layer42covering side wall of the depression57. The modified layer42may be formed in a uniform thickness along the inner wall of the depression57.

Inside the depression57, the modified layer42is formed on the insulating layer35as well. That is, inside the depression57, the modified layer42is formed such as to cover the insulating layer35. Inside the depression57, the modified layer42defines a recess58. More specifically, the recess58is defined by an outer surface of the modified layer42.

The recess58includes a bottom portion and side portion. The recess58may be formed in a convergent shape that narrows in opening width from the first main surface2toward the bottom portion. The bottom portion of the recess58may be formed in a shape curved toward the second main surface3. The recess58includes opening side corner portion and bottom portion side corner portion. The opening side corner portion of the recess58connects the upper surface of the insulating layer35and the side portion of the recess58. The bottom portion side corner portion of the recess58connects the bottom portion of the recess58and the side portion of the recess58.

A width WR of the recess58is less than the width W of the depression57. The width WR of the recess58may exceed 0 μm and be less than 10 μm. The width WR of the recess58may exceed 0 μm and be not more than 2.5 μm, be not less than 2.5 μm and not more than 5 μm, be not less than 5 μm and not more than 7.5 μm, or be not less than 7.5 μm and less than 10 μm. If the thickness of the 4H—SiC crystal structure body1is not more than 150 μm, the width WR of the recess58preferably exceeds 0 μm and is less than 5 μm.

A depth DR of the recess58is less than a depth D of the depression57. The depth DR of the recess58may exceed 0 μm and be less than 30 μm. The depth DR of the recess58may exceed 0 μm and be not more than 5 μm, be not less than 5 μm and not more than 10 μm, be not less than 10 μm and not more than 15 μm, be not less than 15 μm and not more than 20 μm, be not less than 20 μm and not more than 25 μm, or be not less than 25 μm and less than 30 μm. If the thickness of the 4H—SiC crystal structure body1is not more than 150 μm, the depth DR of the recess58preferably exceeds 0 μm and is not more than 15 μm.

Next, referring toFIG.24J, the second intended cutting lines56along the [11-20] direction are heated with the details being the same as inFIG.24I. The modified layers42(second modified layers), the depressions57and the recesses58are thereby formed in the second intended cutting lines56.

The modified layers42, the depressions57and the recesses58along the first intended cutting lines55form first cleavage lines61for cleaving the 4H—SiC crystal structure body1along the [1-100] direction. The modified layers42, the depressions57and the recesses58along the second intended cutting lines56form second cleavage lines62for cleaving the 4H—SiC crystal structure body1along the [11-20] direction.

With this step, a step of forming the first cleavage lines61and thereafter forming the second cleavage lines62was described. However, an order of forming the first cleavage lines61and the second cleavage lines62is arbitrary and is not restricted to the order described above. For example, the first cleavage lines61may be formed after forming the second cleavage lines62. Also, an arbitrary first intended cutting line55and an arbitrary second intended cutting line56may be selected and the first cleavage line61and the second cleavage line62may be formed alternately.

Next, referring toFIG.24K, after the modified layer42forming step, corners of the modified layers42may be rounded. More specifically, an outer surface of each modified layer42may be flattened by removing an unevenness from the outer surface of the modified layer42. The modified layer42may be removed by an etching method. The etching method may be a dry etching method or may be a wet etching method. The modified layer42may be removed by a plasma etching method as an example of a dry etching method.

The modified layer42has a component differing from that of the 4H—SiC crystal structure body1. An etching rate (etching selectivity) with respect to the modified layer42differs from the etching rate (etching selectivity) with respect to SiC. Also, the modified layer42has a component differing from that of the insulating layer35. An etching rate (etching selectivity) with respect to the modified layer42differs from an etching rate (etching selectivity) with respect to the insulating layer35.

A portion of the modified layer42can thus be removed while letting the 4H—SiC crystal structure body1and the insulating layer35remain. The opening side corner portion of each recess58is thereby rounded to shapes curved toward an inner side of the recess58. Also, the bottom portion side corner portion of the recess58is rounded to shapes curved toward an outer side of the recess58.

By the recess58that is rounded at the opening side corner portion, concentration of stress on the modified layer42can be relaxed at the opening side corner portion. Also, by the recess58that is rounded at the bottom portion side corner portion, concentration of stress on the modified layer42can be relaxed at the bottom portion side corner portion. Undesirable cracks due to stress on the modified layer42can thereby be suppressed. The technical ideas ofFIG.8AtoFIG.8Dmay be incorporated in the step ofFIG.24Kand an entirety of the modified layer42may be removed.

Next, referring toFIG.24L, the 4H—SiC crystal structure body1is cleaved along the first cleavage lines61([1-100] direction) and the second cleavage lines62([11-20] direction). A 4H—SiC crystal structure body1cleaving step shall now be described specifically with reference toFIG.25AtoFIG.25D.

FIG.25AtoFIG.25Dare perspective views of the 4H—SiC crystal structure body1shown inFIG.23and are perspective views for describing an example of the cleaving step ofFIG.24L.

Referring toFIG.25A, in this step, first, the 4H—SiC crystal structure body1is cleaved along a nearest neighbor direction intersecting direction. That is, the 4H—SiC crystal structure body1is cleaved along the first cleavage lines61([1-100] direction). More specifically, the 4H—SiC crystal structure body1is cleaved in order along arbitrary first cleavage lines61selected from the plurality of first cleavage lines61.

The 4H—SiC crystal structure body1may be cleaved by applying stress to each first cleavage line61. In this step, a step of applying thermal stress to the first cleavage line61by heating and cooling is performed.

A first cleavage line61heating step may be performed by the laser irradiation method. The laser irradiation method may be performed by an infrared laser (for example, a CO2laser). By the first cleavage line61heating step, a compressive stress with the first cleavage line61as a starting point is thermally induced. The laser energy, laser pulse duty ratio and laser irradiation speed are respectively set to arbitrary values in accordance with a magnitude of the stress to be applied to the first cleavage line61.

A first cleavage line61cooling step may include a step of supplying a cooling fluid to the first cleavage line61. The cooling fluid may include water or air or a mixture of water and air (aerosol). By the first cleavage line61cooling step, a tensile stress with the first cleavage line61as a starting point is thermally induced.

The cooling fluid supplying step may include the cooling fluid emission (jetting) step by the coolant jetting method or the cooling gas supplying method. The first cleavage line61cooling step may be performed after the first cleavage line61heating step. The first cleavage line61cooling step may be performed at the same time as the first cleavage line61heating step.

The 4H—SiC crystal structure body1is cleaved along the first cleavage lines61([1-100] direction) by the compressive stress generated in the first cleavage line61heating step and the tensile stress generated in the first cleavage line61cooling step.

The 4H—SiC crystal structure body1is thereby divided into a plurality of strip portions extending along the [1-100] direction as shown inFIG.25B. Each of the strip portions includes a plurality of device regions53aligned in a single column along the [1-100] direction.

Next, referring toFIG.25C, the 4H—SiC crystal structure body1is cleaved along a nearest neighbor direction. That is, the 4H—SiC crystal structure body1is cleaved along the second cleavage lines62([11-20] direction). More specifically, the 4H—SiC crystal structure body1is cleaved in order along arbitrary second cleavage lines62selected from the plurality of second cleavage lines62.

The 4H—SiC crystal structure body1may be cleaved by applying stress to each second cleavage line62. In this step, a step of applying thermal stress to the second cleavage line62by heating and cooling is performed.

A second cleavage line62heating step may be performed by the laser irradiation method. The laser irradiation method may be performed by an infrared laser (for example, a CO2laser). By the second cleavage line62heating step, a compressive stress with the second cleavage line62as a starting point is thermally induced. The laser energy, laser pulse duty ratio and laser irradiation speed are respectively set to arbitrary values in accordance with a magnitude of the stress to be applied to the second cleavage line62.

A second cleavage line62cooling step may include a step of supplying a cooling fluid to the second cleavage line62. The cooling fluid may include water or air or a mixture of water and air (aerosol). By the second cleavage line62cooling step, a tensile stress with the second cleavage line62as a starting point is thermally induced.

The supplying of the cooling fluid may be performed by emission (jetting) of the cooling fluid by the coolant jetting method or the cooling gas supplying method. The second cleavage line62cooling step may be performed after the second cleavage line62heating step. The second cleavage line62cooling step may be performed at the same time as the second cleavage line62heating step.

The 4H—SiC crystal structure body1is cleaved along the second cleavage lines62([11-20] direction) by the compressive stress generated in the second cleavage line62heating step and the tensile stress generated in the second cleavage line62cooling step.

The plurality of SiC semiconductor devices21are thereby cut out from the plurality of strip portions extending along the [1-100] direction as shown inFIG.25D. The SiC semiconductor devices21are manufactured through steps including the above.

FIG.26is a plan view for describing planar shapes of SiC semiconductor devices71diced through a method for manufacturing the SiC semiconductor devices71according to a reference example.FIG.27is a plan view for describing planar shapes of the SiC semiconductor devices21, shown inFIG.17and diced through the manufacturing method ofFIG.25AtoFIG.25D.

With the method for manufacturing the SiC semiconductor devices71according to the reference example, the 4H—SiC crystal structure body1is cleaved (thermally split) along the second cleavage lines62([11-20] direction) and thereafter the 4H—SiC crystal structure body1is cleaved (thermally split) along the first cleavage lines61([1-100] direction). That is, with the method for manufacturing the SiC semiconductor devices71according to the reference example, a nearest neighbor direction intersecting direction cleaving step is performed after a nearest neighbor direction cleaving step.

Referring toFIG.26, in the SiC semiconductor devices71according to the reference example, the side surfaces25A and25C oriented along the [11-20] direction are formed comparatively flatly. In the [11-20] direction cleaving step, the 4H—SiC crystal structure body1is cleaved along the nearest neighbor direction and, at the same time, the stress (thermal stress) generated in the 4H—SiC crystal structure body1continues continuously. Forming of a bulge at a cleavage portion is thus suppressed.

On the other hand, on the side surfaces25B and25D oriented along the [1-100] direction, tortuosities72that bulge comparatively largely along the [11-20] direction are formed. In particular among the side surfaces25A to25D, the in-plane variations of the side surfaces25B and25D oriented along the [1-100] direction exceed 20 μm.

In the [1-100] direction cleaving step, the 4H—SiC crystal structure body1, that is, the side surfaces25A and25C are cleaved in the nearest neighbor direction intersecting direction. Moreover, the 4H—SiC crystal structure body1is already cleaved along the [11-20] direction and therefore the stress (thermal stress) applied to the 4H—SiC crystal structure body1cannot be made to continue continuously.

Consequently, a force that holds the Si atomic arrangement (a force along the [11-20] direction) acts from the side surfaces25A and25C and the comparatively largely bulging tortuosities72are formed in the side surfaces25B and25D. Such tortuosities72have a tendency of forming from connection points73of the side surfaces25A and25C formed in the first cleaving step and the side surfaces25B and25D formed in the second cleaving step, as starting points in particular. With the SiC semiconductor devices71according to the reference example, the in-plane variations of the side surfaces25B and25D are worsened by the tortuosities72.

The in-plane variation is defined by a maximum value of distances between a reference virtual line74and measurement virtual lines75set in one of the side surfaces25A to25D selected from the side surfaces25A to25D. The reference virtual line74is a straight line joining two corner portions of the SiC semiconductor22in plan view and is set in the selected one of the side surfaces25A to25D. The measurement virtual line75is a straight line extending in parallel to the reference virtual line74in plan view and is set to be tangent to a top portion or a base portion of a bulge (tortuosity72) present on the selected one of the side surfaces25A to25D.

For example, the distance between the reference virtual line74and the measurement virtual line75tangent to the top portion of a bulge (tortuosity72) and the distance between the reference virtual line74and the measurement virtual line tangent75to the base portion of the bulge (tortuosity72) are measured. The in-plane variation of the selected one of the side surfaces25A to25D is defined by the maximum value of the measured distances between the reference virtual line74and the measured virtual lines75.

A distance between the plurality of device regions53that are mutually adjacent in the [11-20] direction and the [1-100] direction is set in consideration of the tortuosities72(in-plane variations). Therefore, if a comparatively large tortuosity72(in-plane variation) is formed, the distance between the plurality of device regions53must be widened to suppress contact of neighboring SiC semiconductor devices71. Therefore, a number of obtained SiC semiconductor devices71that can be acquired from a single 4H—SiC crystal structure body1is restricted by the tortuosities72(in-plane variations).

On the other hand, referring toFIG.27, with the method for manufacturing the SiC semiconductor devices21, the 4H—SiC crystal structure body1is cleaved (thermally split) along the first cleavage lines61([1-100] direction) and thereafter the 4H—SiC crystal structure body1is cleaved (thermally split) along the second cleavage lines61([11-20]direction). That is, with the method for manufacturing the SiC semiconductor devices21, the nearest neighbor direction cleaving step is performed after the nearest neighbor direction intersecting direction cleaving step.

Although in the [1-100] direction cleaving step, the 4H—SiC crystal structure body1is cleaved in the nearest neighbor direction intersecting direction, the stress (thermal stress) applied to the 4H—SiC crystal structure body1continues continuously and therefore the forming of a bulge at a cleavage portion is suppressed.

On the other hand, in the [11-20] direction cleaving step, the 4H—SiC crystal structure body1is already cleaved along the [1-100] direction and therefore the stress (thermal stress) applied to the 4H—SiC crystal structure body1becomes discontinuous. However, in this step, the stress (thermal stress) is applied to the 4H—SiC crystal structure body1along the nearest neighbor direction ([11-20] direction) and the 4H—SiC crystal structure body1is cleaved along the nearest neighbor direction ([11-20] direction). The forming of a bulge at a cleavage portion is thereby suppressed.

Especially according to this order of steps, the forming of tortuosities72having the connection points73of the side surfaces25A and25C and the side surfaces25B and25D as the starting points is suppressed. Consequently, in-plane variations of not more than 20 μm and more specifically not more than 10 μm can be achieved in the side surfaces25A to25D. Also according to this order of steps, in-plane variations of not more than 20 μm and more specifically not more than 10 μm can be achieved in the side surfaces25B and25D oriented along the [1-100] direction. Flatness of all of the side surfaces25A to25D can thus be improved.

Also, the distance between the plurality of device regions53that are mutually adjacent in the [11-20] direction and the [1-100] direction can be narrowed because the tortuosities72can be suppressed. The number of obtained SiC semiconductor devices21that can be acquired from a single 4H—SiC crystal structure body1can thus be increased.

Referring toFIG.26andFIG.27, it can be understood that, regardless of crystal direction, rectilinearity of cleavage is stabilized when the stress (thermal stress) applied to the 4H—SiC crystal structure body1is continuous. On the other hand, it can be understood that when the stress (thermal stress) generated in the 4H—SiC crystal structure body1is discontinuous, the rectilinearity of cleavage in the nearest neighbor direction intersecting direction becomes unstable.

Such a phenomenon is seen prominently in semiconductor materials having a comparatively high thermal conductivity among the various semiconductor materials used in semiconductor devices. In particular, SiC has a comparatively high thermal conductivity with respect to the thermal conductivity of a silicon monocrystal (Si), the thermal conductivity of sapphire (Al2O3), the thermal conductivity of gallium nitride (GaN), etc.

The thermal conductivity of silicon carbide (SiC) is not less than 4.5 W/cmK and not more than 5.5 W/cmK (more specifically, approximately 4.9 W/cmK). The thermal conductivity of Si is approximately 1.5 W/cmK. The thermal conductivity of sapphire (Al2O3) is approximately 0.4 W/cmK. The thermal conductivity of gallium nitride (GaN) is approximately 2.0 W/cmK.

That is, in comparison to the silicon monocrystal (Si), sapphire (Al2O3), gallium nitride (GaN), etc., SiC has a property that stress (thermal stress) due to heat dissipation becomes discontinuous easily. Therefore with SiC, a risk of in-plane variation becomes high in the nearest neighbor direction intersecting direction cleaving step when the stress (thermal stress) is discontinuous. Therefore, the order of performing the nearest neighbor direction cleaving step after the nearest neighbor direction intersecting direction cleaving step is especially effective for SiC which has a comparatively high thermal conductivity.

From a comparison ofFIG.26andFIG.27, a case where the SiC semiconductor layer22has, in plan view, the side surfaces25A and25C that form short sides of a rectangle and the side surfaces25B and25D that form long sides of the rectangle shall now be considered. In this case, the side surfaces25B and25D have areas exceeding the areas of the side surfaces25A and25C.

Therefore, in a case where side surfaces having comparatively large areas are present, it is preferable to set orientations of the plurality of device regions53with respect to crystal directions in advance such that stress (thermal stress) is transmitted continuously in a second cutting step. That is, it is preferable for the side surface25A and the side surface25C that form the short sides of the rectangle to be formed along the [1-100] direction and for the side surface25B and the side surface25D that form the long sides of the rectangle to be formed along the [11-20] direction.

In this case, first, the 4H—SiC crystal structure body1is cut along the [1-100] direction to form the side surface25A and the side surface25C that form the short sides of the rectangle. Thereafter, the 4H—SiC crystal structure body1is cut along the [11-20] direction to form the side surface25B and the side surface25D that form the long sides of the rectangle.

According to this order of steps, the continuity of the stress (thermal stress) can be improved in the second cutting step and therefore the flatness of the side surface25B and the side surface25D that have the comparatively large areas can be improved. Thus in a case of cutting the device regions53of rectangular shape, it is preferable to set the short sides of the device regions53in the [1-100] direction and the long sides of the device regions53in the [11-20] direction.

As described above, according to the present preferred embodiment, a crystal cutting method that enables the 4H—SiC crystal structure body1constituted of a hexagonal crystal to be cut appropriately from two different directions can be provided. Also, according to the present preferred embodiment, a method for manufacturing an SiC semiconductor device using the crystal cutting method can be provided. Also, the SiC semiconductor device21can be manufactured and provided by such a method for manufacturing an SiC semiconductor device.

FIG.28is a sectional view of a region corresponding toFIG.19and is a sectional view of the general arrangement of an SiC semiconductor device91according to a twelfth preferred embodiment of the present invention. In the following, structures corresponding to structures described with the SiC semiconductor device21shall be provided with the same reference symbols and description thereof shall be omitted.

Referring toFIG.28, the SiC semiconductor device91is manufactured by a manufacturing method with which the technical ideas described withFIG.10AtoFIG.10Dabove are incorporated in the steps ofFIG.24AtoFIG.24Ldescribed above. More specifically, the SiC semiconductor device91does not have the modified layer42. With the SiC semiconductor device91, just the inclining portion41is formed at the corner portions of the SiC semiconductor layer22.

Even in the case of manufacturing the SiC semiconductor device91described above, the same effects as the effects described for the eleventh preferred embodiment can be exhibited.

FIG.29is a sectional view of a region corresponding toFIG.19and is a sectional view of the general arrangement of an SiC semiconductor device92according to a thirteenth preferred embodiment of the present invention. In the following, structures corresponding to structures described with the SiC semiconductor device21shall be provided with the same reference symbols and description thereof shall be omitted.

Referring toFIG.29, the SiC semiconductor device92is manufactured by a manufacturing method with which the technical ideas described withFIG.11AtoFIG.11Dabove are incorporated in the steps ofFIG.24AtoFIG.24Ldescribed above. Among the steps ofFIG.24AtoFIG.24L, the step ofFIG.24Kdoes not necessarily have to be performed.

More specifically, the SiC semiconductor device92includes the inclining portion41and the modified layer42that reach the SiC semiconductor substrate31. The inclining portion41reaches the SiC semiconductor substrate31upon crossing the boundary region between the SiC semiconductor substrate31and the SiC epitaxial layer32. The SiC semiconductor substrate31, the SiC epitaxial layer32and the insulating layer35are exposed from the inclining portion41. The lower side end portion41bof the inclining portion41is positioned in the SiC semiconductor substrate31. The lower side end portion41bof the inclining portion41may be formed in a shape curved toward the second main surface24.

The modified layer42is formed as a film along the inclining portion41of the SiC semiconductor layer22. The modified layer42reaches the SiC semiconductor substrate31upon crossing the boundary region between the SiC semiconductor substrate31and the SiC epitaxial layer32. The modified layer42is in contact with the SiC semiconductor substrate31, the SiC epitaxial layer32and the insulating layer35.

The lower side covering portion42bof the modified layer42covers the SiC semiconductor substrate31. The lower side covering portion42bof the modified layer42includes the connection portion42cconnected to the side surfaces25A to25D. The connection portion42cof the modified layer42may be a cleavage portion of the modified layer42. The connection portion42cof the modified layer42may be formed flush with the side surfaces25A to25D.

Even in the case of manufacturing the SiC semiconductor device92described above, the same effects as the effects described for the eleventh preferred embodiment can be exhibited.

FIG.30is a sectional view of a region corresponding toFIG.19and is a sectional view of the general arrangement of an SiC semiconductor device93according to a fourteenth preferred embodiment of the present invention. In the following, structures corresponding to structures described with the SiC semiconductor device21shall be provided with the same reference symbols and description thereof shall be omitted.

Referring toFIG.30, the SiC semiconductor device93is manufactured by a manufacturing method with which the technical ideas described withFIG.12AtoFIG.12Dabove are incorporated in the steps ofFIG.24AtoFIG.24Ldescribed above.

More specifically, the SiC semiconductor device93does not have the modified layer42. With the SiC semiconductor device93, just the inclining portion41is formed at the corner portions of the SiC semiconductor layer22. The inclining portion41reaches the SiC semiconductor substrate31upon crossing the boundary region between the SiC semiconductor substrate31and the SiC epitaxial layer32.

The lower side end portion41bof the inclining portion41is positioned inside the SiC semiconductor substrate31. The lower side end portion41bof the inclining portion41may be formed in a shape curved toward the second main surface24. The SiC semiconductor substrate31, the SiC epitaxial layer32and the insulating layer35are exposed from the inclining portion41.

Even in the case of manufacturing the SiC semiconductor device93described above, the same effects as the effects described for the eleventh preferred embodiment can be exhibited.

FIG.31is a sectional view of a region corresponding toFIG.19and is a sectional view of the general arrangement of an SiC semiconductor device94according to a fifteenth preferred embodiment of the present invention. In the following, structures corresponding to structures described with the SiC semiconductor device21shall be provided with the same reference symbols and description thereof shall be omitted.

Referring toFIG.31, the SiC semiconductor device94does not have the inclining portion41at the corner portions of the SiC semiconductor layer22. The SiC semiconductor device94includes the modified layer42formed in a thickness direction intermediate portion of the SiC semiconductor layer22at the side surfaces25A to25D.

More specifically, the modified layer42is formed in a thickness direction intermediate portion of the SiC epitaxial layer32at the side surfaces25A to25D. The modified layer42is formed in the SiC epitaxial layer32at an interval toward the second main surface24side from the first main surface23. The modified layer42is formed in the SiC epitaxial layer32at an interval toward the first main surface23side from the boundary region between the SiC semiconductor substrate31and the SiC epitaxial layer32.

Such a modified layer42is formed by adjusting a light converging point of the laser light in the steps ofFIG.24JandFIG.24Idescribed above. In this case, the modified layer42is heated and cooled from the second main surface3side of the 4H—SiC crystal structure body1and the 4H—SiC crystal structure body1is cleaved. The step ofFIG.24Kdoes not necessarily have to be performed.

Even in the case of manufacturing the SiC semiconductor device94described above, the same effects as the effects described for the eleventh preferred embodiment can be exhibited.

FIG.32is a sectional view of a region corresponding toFIG.19and is a sectional view of the general arrangement of an SiC semiconductor device95according to a sixteenth preferred embodiment of the present invention. In the following, structures corresponding to structures described with the SiC semiconductor device21shall be provided with the same reference symbols and description thereof shall be omitted.

Referring toFIG.32, the SiC semiconductor device95does not have the inclining portion41at the corner portions of the SiC semiconductor layer22. The SiC semiconductor device95includes the modified layer42formed in a thickness direction intermediate portion of the SiC semiconductor layer22at the side surfaces25A to25D.

The modified layer42has an upper end portion at the first main surface23side and a lower end portion at the second main surface24side. The upper end portion of the modified layer42is formed in the SiC epitaxial layer32at an interval toward the second main surface24side from the first main surface23. The lower end portion of the modified layer42crosses the boundary region between the SiC semiconductor substrate31and the SiC epitaxial layer32and is formed in the SiC semiconductor substrate31.

Such a modified layer42is formed by adjusting the light converging point of the laser light in the steps ofFIG.24JandFIG.24Idescribed above. In this case, the modified layer42is heated and cooled from the second main surface3side of the 4H—SiC crystal structure body1and the 4H—SiC crystal structure body1is cleaved. The step ofFIG.24Kdoes not necessarily have to be performed.

Even in the case of manufacturing the SiC semiconductor device95described above, the same effects as the effects described for the eleventh preferred embodiment can be exhibited.

FIG.33is a sectional view of a region corresponding toFIG.19and is a sectional view of the general arrangement of an SiC semiconductor device96according to a seventeenth preferred embodiment of the present invention. In the following, structures corresponding to structures described with the SiC semiconductor device21shall be provided with the same reference symbols and description thereof shall be omitted.

Referring toFIG.33, the SiC semiconductor device96is manufactured by a manufacturing method with which the technical ideas described withFIG.13AtoFIG.13Dabove are incorporated in the steps ofFIG.24AtoFIG.24Ldescribed above. Among the steps ofFIG.24AtoFIG.24L, the step ofFIG.24Kdoes not necessarily have to be performed.

More specifically, the SiC semiconductor device96includes the inclining portion41and the modified layer42that are formed in regions of the side surfaces25A to25D at the second main surface side24of the SiC semiconductor layer22.

The inclining portion41is formed at corner portions connecting the second main surface24and the side surfaces25A to25D. The corner portions of the SiC semiconductor layer22include corner portions connecting the second main surface24and the side surfaces25A and25C and extending along the [11-20] direction. The corner portions of the SiC semiconductor layer22include corner portions connecting the second main surface24and the side surfaces25B and25D and extending along the [1-100] direction. The inclining portion41is inclined downwardly from the second main surface24toward the side surfaces25A to25D.

The inclining portion41is formed by an inner wall of a depression recessed from the second main surface24toward the first main surface23at the corner portions of the SiC semiconductor layer22. The inclining portion41is formed in the SiC semiconductor substrate31. More specifically, the inclining portion41is formed in a region at the second main surface24side with respect to the boundary region between the SiC semiconductor substrate31and the SiC epitaxial layer32.

The inclining portion41has an upper side end portion41dand a lower side end portion41e. The upper side end portion41dof the inclining portion41is positioned at the first main surface23side of the SiC semiconductor layer22. The upper side end portion41dof the inclining portion41is continuous to the side surfaces25A to25D. The upper side end portion41dof the inclining portion41may be formed in a shape curved toward the first main surface23. The lower side end portion41eof the inclining portion41is positioned at the second main surface24side of the SiC semiconductor layer22. The lower side end portion41eof the inclining portion41is connected to the second main surface24of the SiC semiconductor layer22.

The width WI of the inclining portion41may be not more than the in-plane variations of the side surfaces25A to25D. The width WI of the inclining portion41may be less than the in-plane variations of the side surfaces25A to25D. The width WI of the inclining portion41is the width in the direction orthogonal to the direction in which the inclining portion41extends in plan view.

The width WI of the inclining portion41may exceed 0 μm and be not more than 10 μm. The width WI of the inclining portion41may exceed 0 μm and be not more than 2.5 μm, be not less than 2.5 μm and not more than 5 μm, be not less than 5 μm and not more than 7.5 μm, or be not less than 7.5 μm and not more than 10 μm. If the thickness of the SiC semiconductor layer22is not more than 150 μm, the width WI of the inclining portion41preferably exceeds 0 μm and is not more than 5 μm. More preferably, the width WI of the inclining portion41exceeds 0 μm and is not more than 2.5 μm.

The depth D of the inclining portion41may exceed 0 μm and be not more than 30 μm. The depth D of the inclining portion41is the distance in the normal direction N from the first main surface23to the lower side end portion of the inclining portion41. The depth D of the inclining portion41may exceed 0 μm and be not more than 5 μm, be not less than 5 μm and not more than 10 μm, be not less than 10 μm and not more than 15 μm, be not less than 15 μm and not more than 20 μm, be not less than 20 μm and not more than 25 μm, or be not less than 25 μm and not more than 30 μm. If the thickness of the SiC semiconductor layer22is not more than 150 μm, the depth D of the inclining portion41preferably exceeds 0 μm and is not more than 15 μm.

The modified layer42is formed in the SiC semiconductor substrate31. More specifically, the modified layer42is formed in a region of the SiC semiconductor layer22at the second main surface24side with respect to the boundary region between the SiC semiconductor substrate31and the SiC epitaxial layer32. The modified layer42is formed along the corner portions connecting the second main surface24and the side surfaces25A to25D. The modified layer42is formed at the corner portions connecting the second main surface24and the side surfaces25A and25C and extending along the [11-20] direction. Also, the modified layer42is formed at the corner portions connecting the second main surface24and the side surfaces25B and25D and extending along the [1-100] direction.

In this embodiment, the modified layer42extends as a band on the side surfaces25A to25D along directions parallel to the second main surface24. That is, the modified layer42extends as a band along the [1-100] direction and the [11-20] direction. At the side surfaces25A to25D, the modified layer42is formed in an annular shape (for example, an endless shape) surrounding the active region33.

The modified layer42is formed as a film along the inclining portion41of the SiC semiconductor layer22. The thickness of the portion of the modified layer42covering the bottom wall of the inclining portion41may be greater than the thickness of the portion of the modified layer42covering the side wall of the inclining portion41. The modified layer42may be formed in a uniform thickness along the inner wall of the inclining portion41.

The modified layer42includes an upper side covering portion42dand a lower side covering portion42e. The upper side covering portion42dof the modified layer42covers the upper side end portion41dof the inclining portion41. The lower side covering portion42eof the modified layer42covers the lower side end portion41eof the inclining portion41.

The upper side covering portion42dof the modified layer42includes a connection portion42fconnected to the side surfaces25A to25D. The connection portion42fof the modified layer42may be a cleavage portion of the modified layer42. The connection portion42fof the modified layer42may be formed flush with the side surfaces25A to25D.

The width WM of the modified layer42may be not more than the in-plane variations of the side surfaces25A to25D. The width WM of the modified layer42may be less than the in-plane variations of the side surfaces25A to25D. The width WM of the modified layer42is the width in the direction orthogonal to the direction in which the modified layer42extends in plan view.

The width WM of the modified layer42may exceed 0 μm and be not more than 10 μm. The width WM of the modified layer42may exceed 0 μm and be not more than 2 μm, be not less than 2 μm and not more than 4 μm, be not less than 4 μm and not more than 6 μm, be not less than 6 μm and not more than 8 μm, or be not less than 8 μm and not more than 10 μm. If the thickness of the SiC semiconductor layer22is not more than 150 μm, the width WM of the modified layer42preferably exceeds 0 μm and is not more than 5 μm. More preferably, the width WM of the modified layer42exceeds 0 μm and is not more than 2.5 μm.

The thickness T of the modified layer42may exceed 0 μm and be not more than 30 μm. The thickness T of the modified layer42is the thickness of the modified layer42along the normal direction N. The thickness T of the modified layer42may exceed 0 μm and be not more than 5 μm, be not less than 5 μm and not more than 10 μm, be not less than 10 μm and not more than 15 μm, be not less than 15 μm and not more than 20 μm, be not less than 20 μm and not more than 25 μm, or be not less than 25 μm and not more than 30 μm. If the thickness of the SiC semiconductor layer22is not more than 150 μm, the thickness T of the modified layer42preferably exceeds 0 μm and is not more than 15 μm.

The second electrode layer38exposes the modified layer42at the second main surface24of the SiC semiconductor layer22. That is, a peripheral edge portion of the second electrode layer38is formed at an inner region of the SiC semiconductor layer22with respect to the side surfaces25A to25D. The modified layer42may have a covering portion extending from the inclining portion41toward the second electrode layer38and covering the second electrode layer38.

Even in the case of manufacturing the SiC semiconductor device96described above, the same effects as the effects described for the eleventh preferred embodiment can be exhibited.

FIG.34is a sectional view of a region corresponding toFIG.19and is a sectional view of the general arrangement of an SiC semiconductor device97according to an eighteenth preferred embodiment of the present invention. In the following, structures corresponding to structures described with the SiC semiconductor device21shall be provided with the same reference symbols and description thereof shall be omitted.

Referring toFIG.34, the SiC semiconductor device97is manufactured by a manufacturing method with which the technical ideas described withFIG.14AtoFIG.14Dabove are incorporated in the steps ofFIG.24AtoFIG.24Ldescribed above.

More specifically, the SiC semiconductor device97does not have the modified layer42. The SiC semiconductor device97includes the inclining portion41that is formed in regions of the side surfaces25A to25D at the second main surface side24of the SiC semiconductor layer22.

The inclining portion41is formed at the corner portions connecting the second main surface24and the side surfaces25A to25D. The corner portions of the SiC semiconductor layer22include the corner portions connecting the second main surface24and the side surfaces25A and25C and extending along the [11-20] direction. The corner portions of the SiC semiconductor layer22include the corner portions connecting the second main surface24and the side surfaces25B and25D and extending along the [1-100] direction.

The inclining portion41is inclined downwardly from the second main surface24toward the side surfaces25A to25D. The inclining portion41is formed by an inner wall of a depression recessed from the second main surface24toward the first main surface23at the corner portions of the SiC semiconductor layer22.

The inclining portion41is formed in the SiC semiconductor substrate31. More specifically, the inclining portion41is formed in a region at the second main surface24side with respect to the boundary region between the SiC semiconductor substrate31and the SiC epitaxial layer32.

The inclining portion41has the upper side end portion41dand the lower side end portion41e. The upper side end portion41dof the inclining portion41is positioned at the first main surface23side. The lower side end portion41eof the inclining portion41is positioned at the second main surface24side. The upper side end portion41dof the inclining portion41is continuous to the side surfaces25A to25D. The upper side end portion41dof the inclining portion41may be formed in a shape curved toward the first main surface23. The lower side end portion41eof the inclining portion41is connected to the second main surface24.

The width WI of the inclining portion41may be not more than the in-plane variations of the side surfaces25A to25D. The width WI of the inclining portion41may be less than the in-plane variations of the side surfaces25A to25D. The width WI of the inclining portion41is the width in the direction orthogonal to the direction in which the inclining portion41extends in plan view.

The width WI of the inclining portion41may exceed 0 μm and be not more than 10 μm. The width WI of the inclining portion41may exceed 0 μm and be not more than 2.5 μm, be not less than 2.5 μm and not more than 5 μm, be not less than 5 μm and not more than 7.5 μm, or be not less than 7.5 μm and not more than 10 μm. If the thickness of the SiC semiconductor layer22is not more than 150 μm, the width WI of the inclining portion41preferably exceeds 0 μm and is not more than 5 μm. More preferably, the width WI of the inclining portion41exceeds 0 μm and is not more than 2.5 μm.

The depth D of the inclining portion41may exceed 0 μm and be not more than 30 μm. The depth D of the inclining portion41is the distance in the normal direction N from the first main surface23to the lower side end portion of the inclining portion41. The depth D of the inclining portion41may exceed 0 μm and be not more than 5 μm, be not less than 5 μm and not more than 10 μm, be not less than 10 μm and not more than 15 μm, be not less than 15 μm and not more than 20 μm, be not less than 20 μm and not more than 25 μm, or be not less than 25 μm and not more than 30 μm. If the thickness of the SiC semiconductor layer22is not more than 150 μm, the depth D of the inclining portion41preferably exceeds 0 μm and is not more than 15 μm.

The second electrode layer38exposes the inclining portion41at the second main surface24. That is, the peripheral edge portion of the second electrode layer38is formed at the inner region of the SiC semiconductor layer22with respect to the side surfaces25A to25D.

Even in the case of manufacturing the SiC semiconductor device97described above, the same effects as the effects described for the eleventh preferred embodiment can be exhibited.

FIG.35is a sectional view of a region corresponding toFIG.19and is a sectional view of the general arrangement of an SiC semiconductor device98according to a nineteenth preferred embodiment of the present invention. In the following, structures corresponding to structures described with the SiC semiconductor device21shall be provided with the same reference symbols and description thereof shall be omitted.

Referring toFIG.35, the SiC semiconductor device98does not have the inclining portion41at the corner portions at the first main surface23side and the corner portions at the second main surface24side. The SiC semiconductor device98includes the modified layer42formed in a thickness direction intermediate portion of the SiC semiconductor layer22at the side surfaces25A to25D.

More specifically, the modified layer42is formed in a thickness direction intermediate portion of the SiC semiconductor substrate31. The modified layer42is formed at an interval toward the second main surface24side with respect to the boundary region between the SiC semiconductor substrate31and the SiC epitaxial layer32. Also, the modified layer42is formed at an interval toward the SiC epitaxial layer32side with respect to the second main surface24.

Such a modified layer42is formed by adjusting the light converging point of the laser light when irradiating the laser light onto the second main surface24. In this case, the modified layer42is heated and cooled from the second main surface3side of the 4H—SiC crystal structure body1and the 4H—SiC crystal structure body1is cleaved. The step ofFIG.24Kdoes not necessarily have to be performed.

Even in the case of manufacturing the SiC semiconductor device98described above, the same effects as the effects described for the eleventh preferred embodiment can be exhibited.

FIG.36is a top view of an SiC semiconductor device101according to a twentieth preferred embodiment of the present invention.FIG.37is a top view of the SiC semiconductor device101shown inFIG.36and is a top view with a resin layer116being removed. The SiC semiconductor device101is a device manufactured using the 4H—SiC crystal structure body1described above. The SiC semiconductor device101is also a configuration example that represents a specific structure of the SiC semiconductor device21described above.

Referring toFIG.36andFIG.37, the SiC semiconductor device101includes an SiC semiconductor layer102. A thickness of the SiC semiconductor layer102may be not less than 1 μm and less than 1000 μm. The thickness of the SiC semiconductor layer102may be not less than 1 μm and not more than 50 μm, not less than 50 μm and not more than 150 μm, not less than 150 μm and not more than 250 μm, not less than 250 μm and not more than 400 μm, not less than 400 μm and not more than 600 μm, not less than 600 μm and not more than 800 μm, or not less than 800 μm and not more than 1000 μm.

The SiC semiconductor layer102has a first main surface103at one side, a second main surface104at another side, and side surfaces105A,105B,105C and105D connecting the first main surface103and the second main surface104. In this embodiment, the side surfaces105A to105D are all constituted of cut surfaces. More specifically, the side surfaces105A to105D are constituted of cleavage surfaces.

The first main surface103and the second main surface104are formed in quadrilateral shapes (rectangular shapes in this embodiment) in a plan view as viewed in a normal direction N to the surfaces (hereinafter referred to simply as “plan view”). The side surface105A opposes the side surface105C. The side surface105B opposes the side surface105D.

The SiC semiconductor layer102includes a 4H—SiC monocrystal. The first main surface103and the second main surface104face the c planes of the 4H—SiC monocrystal. The first main surface103faces the (0001) plane and the second main surface104faces the (000-1) plane.

The first main surface103and the second main surface104have an off angle θ inclined at an angle of not more than 10° in the [11-20] direction with respect to the (0001) plane. The off angle θ may be not less than 0° and not more than 2°, not less than 2° and not more than 4°, not less than 4° and not more than 6°, not less than 6° and not more than 8°, or not less than 8° and not more than 100. The off angle θ is preferably not less than 0° and not more than 40.

A state where the off angle θ is 0° is that in which the normal direction N and the c axis are matched. The off angle θ may exceed 0° and be less than 40. The off angle θ is typically 2° or 4° and more specifically is set in a range of 2°±10% or a range of 4°±10%.

The side surfaces105A to105D respectively extend as planes along the normal direction N. A length of each of the side surfaces105A to105D may be not less than 1 mm and not more than 10 mm. The length of the side surfaces105A to105D may be not less than 1 mm and not more than 2.5 mm, not less than 2.5 mm and not more than 5 mm, not less than 5 mm and not more than 7.5 mm, or not less than 7.5 mm and not more than 10 mm. The length of the side surfaces105A to105D is preferably not less than 2 mm and not more than 5 mm.

The side surfaces105A to105D extend in a nearest neighbor direction and a nearest neighbor direction intersecting direction. More specifically, the nearest neighbor direction intersecting direction is an orthogonal direction orthogonal to the nearest neighbor direction. In this embodiment, the side surfaces105A to105D extend in the [11-20] direction and the [1-100] direction.

The side surface105A and the side surface105C that form short sides of a rectangle are formed along the nearest neighbor direction intersecting direction (that is, the [1-100] direction). The side surface105B and the side surface105D that form long sides of the rectangle are formed along the nearest neighbor direction (that is, the [11-20] direction). The side surface105A and the side surface105C may be formed along the [11-20] direction and the side surface105B and the side surface105D may be formed along the [1-100] direction instead.

In-plane variations of the side surfaces105A to105D are not more than 20 μm. The in-plane variations along the [11-20] direction of the side surfaces105A and105C that extend along the [1-100] direction are not more than 20 μm. More specifically, the in-plane variations of the side surfaces105A and105C are not more than 10 μm.

The in-plane variations along the [1-100] direction of the side surfaces105B and105D that extend along the [11-20] direction are not more than 20 μm. More specifically the in-plane variations of the side surfaces105B and105D are not more than 10 μm.

An in-plane variation is defined by a maximum value of distances between a reference virtual line and measurement virtual lines set in one of the side surfaces105A to105D selected from the side surfaces105A to105D. The reference virtual line is a straight line joining two corner portions of the SiC semiconductor102in plan view and is set in the selected one of the side surfaces105A to105D. A measurement virtual line is a straight line extending in parallel to the reference virtual line in plan view and is set to be tangent to a top portion or a base portion of a bulge (tortuosity) present on the selected one of the side surfaces105A to105D.

For example, the distance between the reference virtual line and the measurement virtual line tangent to the top portion of a bulge (tortuosity) and the distance between the reference virtual line and the measurement virtual line tangent to the base portion of the bulge (tortuosity) are measured. The in-plane variation of the selected one of the side surfaces105A to105D is defined by the maximum value of the measured distances between the reference virtual line and the measured virtual lines.

The SiC semiconductor layer102includes an active region106and an outer region107. The active region106is a region in which a vertical MISFET (metal insulator semiconductor field effect transistor) is formed as an example of a field effect transistor. The outer region107is a region at an outer side of the active region106.

The active region106may be set in a central portion of the SiC semiconductor layer102at intervals toward an inner region from the side surfaces105A to105D in plan view. The active region106may be set to a quadrilateral shape (a rectangular shape in this embodiment) having four sides parallel to the four side surfaces105A to105D in plan view.

The outer region107is set in a region between the side surfaces105A to105D and the active region106. The outer region107may be set to an annular shape (for example, an endless shape) surrounding the active region106in plan view.

The SiC semiconductor device101includes a gate terminal electrode layer108and a source terminal electrode layer109that are formed on the first main surface103. In this embodiment, the gate terminal electrode layer108includes a gate pad110and a gate finger111. The gate pad110and the gate finger111are disposed in the active region106.

The gate pad110is formed in a region oriented along the side surface105A in plan view. The gate pad110is formed in a region oriented along a central portion of the side surface105A in plan view. The gate pad110may be formed in a region oriented along a corner portion connecting any two of the side surfaces105A to105D in plan view. The gate pad110is formed in a quadrilateral shape in plan view.

The gate finger111includes an outer gate finger111A and an inner gate finger111B. The outer gate finger111A is led out from the gate pad110and extends as a band along peripheral edges of the active region106. In this embodiment, the outer gate finger111A is formed along the three side surfaces105A,105B and105D and defines an inner region of the active region106from three directions.

The outer gate finger111A has a pair of open end portions112A and112B. The pair of open end portions112A and112B of the outer gate finger111A are formed in a region opposing the gate pad110across the inner region of the active region106. In this embodiment, the pair of open end portions112A and112B of the outer gate finger111A are formed in a region oriented along the side surface105C.

The inner gate finger111B is led out from the gate pad110to the inner region of the active region106. The inner gate finger111B extends as a band in the inner region of the active region106. The inner gate finger111B extends from the side surface105A side toward the side surface105C side.

In this embodiment, the source terminal electrode layer109includes a source pad113, a source routing wiring114and a source connection portion115. The source pad113is formed in the active region106at intervals from the gate pad110and the gate finger111. The source pad113covers a region of C shape (inverted C shape inFIG.36andFIG.37) defined by the gate pad110and the gate finger111. The source pad113is formed in a C shape (an inverted C shape inFIG.36andFIG.37) in plan view.

The source routing wiring114is formed in the outer region107. The source routing wiring114extends as a band along the active region106. In this embodiment, the source routing wiring114is formed in an annular shape (for example, an endless shape) surrounding the active region106in plan view. The source routing wiring114is electrically connected to the SiC semiconductor layer102in the outer region107.

The source connection portion115connects the source pad113and the source routing wiring114. The source connection portion115is formed in a region between the pair of open end portions112A and112B of the outer gate finger111A. The source connection portion115crosses a boundary region between the active region106and the outer region107from the source pad113and is connected to the source routing wiring114.

Due to its structure, the MISFET formed in the active region106includes an npn type parasitic bipolar transistor. When an avalanche current generated in the outer region107flows into the active region106, the parasitic bipolar transistor is switched to an on state. In this case, control of the MISFET may become unstable, for example, due to latchup.

Therefore, with the SiC semiconductor device101, the structure of the source terminal electrode layer109is used to form an avalanche current absorbing structure that absorbs an avalanche current generated in a region outside the active region106.

More specifically, the avalanche current generated in the outer region107is absorbed by the source routing wiring114. The avalanche current is thereby made to reach the source pad113via the source connection portion115. If a lead wire (for example, a bonding wire) for external connection is connected to the source pad113, the avalanche current is taken out by this lead wire.

Switching of the parasitic bipolar transistor to the on state by an undesirable current generated in the outer region107can thereby be suppressed. Latchup can thus be suppressed and therefore stability of control of the MISFET can be improved.

A gate voltage is applied to the gate pad110and the gate finger111. The gate voltage may be not less than 10 V and not more than 50 V (for example, approximately 30 V). A source voltage is applied to the source pad113. The source voltage may be a reference voltage (for example, a GND voltage).

The SiC semiconductor device101includes the resin layer116formed on the first main surface103(more specifically, on an interlayer insulating layer191to be described below). InFIG.36, the resin layer116is shown with hatching for clarity. The resin layer116covers the gate pad110, the gate finger111and the source pad113.

The resin layer116may include a negative type or positive type photosensitive resin. In this embodiment, the resin layer116includes a polybenzoxazole as an example of a positive type photosensitive resin. The resin layer116may include a polyimide as an example of a negative type photosensitive resin instead.

The resin layer116includes a gate pad opening117and a source pad opening118. The gate pad opening117exposes the gate pad110. The source pad opening118exposes the source pad113.

A peripheral edge portion119of the resin layer116is formed at intervals in an inner region from the side surfaces105A to105D. The resin layer116thereby exposes a peripheral edge portion (more specifically, the interlayer insulating layer191to be described below) of the SiC semiconductor layer102.

The peripheral edge portion119of the resin layer116is a portion in which dicing streets were formed in a process of cutting out the SiC semiconductor device101from the 4H—SiC crystal structure body1. By exposing the peripheral edge portion of the SiC semiconductor layer102from the resin layer116, it becomes unnecessary to physically cut the resin layer116. The SiC semiconductor device101can thus be cut out smoothly from the 4H—SiC crystal structure body1.

FIG.38is an enlarged view of a region XXXVIII shown inFIG.37and is a diagram for describing the structure of the first main surface103of the SiC semiconductor layer102.FIG.39is a sectional view taken along line XXXIX-XXXIX shown inFIG.38.FIG.40is a sectional view taken along line XL-XL shown inFIG.38.FIG.41is an enlarged view of a region XLI shown inFIG.39.FIG.42is a sectional view taken along line XLII-XLII shown inFIG.37.FIG.43is an enlarged view of a region XLIII shown inFIG.42.FIG.44is an enlarged view of a region XLIV shown inFIG.42.

Referring toFIG.38toFIG.44, the SiC semiconductor layer102has, in this embodiment, a laminated structure including an n+ type SiC semiconductor substrate121and an n type SiC epitaxial layer122.

The second main surface104of the SiC semiconductor layer102is formed by the SiC semiconductor substrate121. The first main surface103of the SiC semiconductor layer102is formed by the SiC epitaxial layer122. The side surfaces105A to105D of the SiC semiconductor layer102are formed by the SiC semiconductor substrate121and the SiC epitaxial layer122. The second main surface104may be a ground surface having grinding processing marks.

A thickness of the SiC epitaxial layer122is less than a thickness of the SiC semiconductor substrate121. The thickness of the SiC semiconductor substrate121may be not less than 1 μm and less than 1000 μm. The thickness of the SiC semiconductor substrate121may be not less than 1 μm and not more than 50 μm, not less than 50 μm and not more than 150 μm, not less than 150 μm and not more than 250 μm, not less than 250 μm and not more than 400 μm, not less than 400 μm and not more than 600 μm, not less than 600 μm and not more than 800 μm, or not less than 800 μm and not more than 1000 μm.

The thickness of the SiC semiconductor substrate121is preferably not more than 150 μm. By making the thickness of the SiC semiconductor substrate121small, reduction of resistance value can be achieved by shortening of a current path.

The thickness of the SiC epitaxial layer122may be not less than 1 μm and not more than 100 μm. The thickness of the SiC epitaxial layer122may be not less than 1 μm and not more than 10 μm, not less than 10 μm and not more than 20 μm, not less than 20 μm and not more than 30 μm, not less than 30 μm and not more than 40 μm, not less than 40 μm and not more than 50 μm, not less than 50 μm and not more than 75 μm, or not less than 75 μm and not more than 100 μm. The thickness of the SiC epitaxial layer122is preferably not less than 5 μm and not more than 20 μm.

An n type impurity concentration of the SiC epitaxial layer122is not more than an n type impurity concentration of the SiC semiconductor substrate121. The n type impurity concentration of the SiC semiconductor substrate121may be not less than 1.0×1018cm−3and not more than 1.0×1021cm−3. The n type impurity concentration of the SiC epitaxial layer122may be not less than 1.0×1015cm−3and not more than 1.0×1018cm−3.

In this embodiment, the SiC epitaxial layer122has a plurality of regions having different n type impurity concentrations along the normal direction N. More specifically, the SiC epitaxial layer122includes a high concentration region122aof comparatively high n type impurity concentration and a low concentration region122bof lower n type impurity concentration than the high concentration region122a.

The high concentration region122ais formed in a region at the first main surface103side. The low concentration region122bis formed in a region at the second main surface104side with respect to the high concentration region122a. The n type impurity concentration of the high concentration region122amay be not less than 1×1016cm−3and not more than 1×1018cm−3. The n type impurity concentration of the low concentration region122bmay be not less than 1×1015cm−3and not more than 1×1016cm−3.

A thickness of the high concentration region122ais not more than a thickness of the low concentration region122b. More specifically, the thickness of the high concentration region122ais less than the thickness of the low concentration region122b. That is, the thickness of the high concentration region122ais less than half the total thickness of the SiC epitaxial layer122.

The SiC epitaxial layer122is formed, for example, by changing an introduced amount (added amount) of the n type impurity along an SiC growth direction when epitaxially growing SiC from the SiC semiconductor wafer51in the step of preparing the 4H—SiC crystal structure body1(seeFIG.23andFIG.24A).

The SiC semiconductor device101includes a drain pad123connected to the second main surface104of the SiC semiconductor layer102. That is, the SiC semiconductor substrate121is formed as a drain region124of the MISFET. The SiC epitaxial layer122is formed as a drift region125of the MISFET. A maximum voltage that can be applied across the source pad113and the drain pad123in an off state may be not less than 1000 V and not more than 10000 V.

The drain pad123may include at least one layer among an Al layer, a Ti layer, an Ni layer, an Au layer and an Ag layer. The drain pad123may have a laminated structure in which at least two layers among an Al layer, a Ti layer, an Ni layer, an Au layer and an Ag layer are laminated in any mode. The drain pad123may have a single layer structure constituted of an Al layer, a Ti layer, an Ni layer, an Au layer, or an Ag layer. The drain pad123may have a four-layer structure that includes a Ti layer, an Ni layer, an Au layer and an Ag layer that are laminated in that order from the second main surface104.

The SiC semiconductor device101includes a p type body region126formed in a surface layer portion of the first main surface103of the SiC semiconductor layer102in the active region106. A p type impurity concentration of the body region126may be not less than 1×1017cm−3and not more than 1×1020cm−3. The body region126defines the active region106.

The SiC semiconductor device101includes a plurality of gate trenches131in the surface layer portion of the first main surface103in the active region106. The plurality of gate trenches131are formed at intervals along an arbitrary first direction X. The plurality of gate trenches131are formed as bands extending along a second direction Y intersecting the first direction X. The second direction Y is a direction orthogonal to the first direction X. The plurality of gate trenches131are thereby formed as stripes extending along the second direction Y as a whole in plan view.

Preferably, the first direction X is set to the [11-20] direction and the second direction Y is set to the [1-100] direction. That is, the plurality of gate trenches131are preferably formed as bands formed at intervals in the [11-20] direction and extending along the [1-100] direction.

The first direction X may be set to the [1-100] direction and the second direction Y may be set to the [11-20] direction instead. That is, the plurality of gate trenches131may be formed as bands formed at intervals in the [1-100] direction and extending along the [11-20] direction.

Each gate trench131extends as a band from a peripheral edge portion at one side (the side surface105B side) toward a peripheral edge portion at another side (the side surface105D side) of the active region106. Each gate trench131crosses an intermediate portion between the peripheral edge portion at the one side and the peripheral edge portion at the other side of the active region106. One end portion of each gate trench131is positioned at the peripheral edge portion at the one side of the active region106. Another end portion of each gate trench131is positioned at the peripheral edge portion at the other side of the active region106.

Each gate trench131has a length of the millimeter order (a length not less than 1 mm). The length of each gate trench131may be not less than 1 mm and not more than 10 mm. The length of each gate trench131may be not less than 1 mm and not more than 2 mm, not less than 2 mm and not more than 4 mm, not less than 4 mm and not more than 6 mm, not less than 6 mm and not more than 8 mm, or not less than 8 mm and not more than 10 mm. The length of each gate trench131is preferably not less than 2 mm and not more than 5 mm. Also, a total extension of one or a plurality of the gate trenches131per unit area is preferably not less than 0.5 μm/μm2and not more than 0.75 μm/μm2.

Each gate trench131includes an active trench portion131aand a contact trench portion131b. The active trench portion131ais a portion in the active region106along a channel region of the MISFET. The contact trench portion131bis a portion of the gate trench131that mainly serves as a contact with the gate finger111.

The contact trench portion131bis led out from the active trench portion131ato a peripheral edge portion of the active region106. The contact trench portion131bis formed in a region directly below the gate finger111. A lead-out amount of the contact trench portion131bis arbitrary.

Each gate trench131penetrates through the body region126and reaches the SiC epitaxial layer122. A bottom wall of each gate trench131is positioned inside the SiC epitaxial layer122.

More specifically, the bottom wall of each gate trench131is positioned in the high concentration region122aof the SiC epitaxial layer122. The bottom wall of the gate trench131may be formed parallel to the first main surface103. The bottom wall of the gate trench131may be formed in a shape curved toward the second main surface104.

Side wall of the gate trench131may extend along the normal direction N. The side wall of the gate trench131may be formed substantially perpendicular to the first main surface103of the SiC semiconductor layer102. The gate trench131may be formed in a tapered shape with a bottom area being less than an opening area.

A depth of the gate trench131along the normal direction N may be not less than 0.5 μm and not more than 3 μm. The depth of the gate trench131may be not less than 0.5 μm and not more than 1 μm, not less than 1 μm and not more than 1.5 μm, not less than 1.5 μm and not more than 2 μm, not less than 2 μm and not more than 2.5 μm, or not less than 2.5 μm and not more than 3 μm. The depth of the gate trench131is preferably not less than 0.5 μm and not more than 1.0 μm.

A width of the gate trench131along the first direction X may be not less than 0.1 μm and not more than 2 μm. The width of the gate trench131may be not less than 0.1 μm and not more than 0.5 μm, not less than 0.5 μm and not more than 1 μm, not less than 1 μm and not more than 1.5 μm, or not less than 1.5 μm and not more than 2 μm. The width of the gate trench131is preferably not less than 0.1 μm and not more than 0.5 μm.

Referring toFIG.41, an opening edge portion132of each gate trench131includes an inclining portion133that inclines downwardly from the first main surface103toward the gate trench131. The opening edge portion132of the gate trench131is a corner portion connecting the first main surface103and the side wall of the gate trench131.

In this embodiment, the inclining portion133is formed in a curved shape recessed toward the SiC semiconductor layer102. The inclining portion133may instead be formed in a curved shape protruding toward an inner side of the gate trench131. An electric field with respect to the opening edge portion132is relaxed by the inclining portion133.

The SiC semiconductor device101includes a gate insulating layer134and a gate electrode layer135formed inside each gate trench131. InFIG.38, the gate insulating layer134and the gate electrode layer135are shown with hatching.

The gate insulating layer134includes silicon oxide. The gate insulating layer134may include another insulating film of silicon nitride, etc. The gate insulating layer134is formed as a film along inner wall surfaces of the gate trench131. The gate insulating layer134defines a recess space inside the gate trench131.

The gate insulating layer134includes a first region134a, a second region134band a third region134c. The first region134ais formed along the side wall of the gate trench131. The second region134bis formed along the bottom wall of the gate trench131. The third region134cis led out from the first region134aonto the first main surface103and formed on the first main surface103.

A thickness T1of the first region134ais less than a thickness T2of the second region134band a thickness T3of the third region134c. A ratio T2/T1of the thickness T2of the second region134bwith respect to the thickness T1of the first region134amay be not less than 2 and not more than 5. A ratio T3/T1of the thickness T3of the third region134cwith respect to the thickness T1of the first region134amay be not less than 2 and not more than 5.

The thickness T1of the first region134amay be not less than 0.01 μm and not more than 0.2 μm. The thickness T2of the second region134bmay be not less than 0.05 μm and not more than 0.5 μm. The thickness T3of the third region134cmay be not less than 0.05 μm and not more than 0.5 μm.

By thinning of the first region134a, increase in carriers induced in regions of the body region126in vicinities of the side wall of the gate trench131can be suppressed. Increase in channel resistance can thereby be suppressed. By thickening of the second region134b, concentration of electric field with respect to the bottom wall of the gate trench131can be relaxed.

By thickening of the third region134c, a withstand voltage of the gate insulating layer134in a vicinity of the opening edge portion132can be improved. Also, by the thickening of the third region134c, loss of the third region134cdue to an etching method can be suppressed. The first region134acan thereby be protected by the third region134c.

For example, removal of the first region134aby the etching method due to the loss of the third region134ccan be suppressed. The gate electrode layer135can thereby be made to oppose the SiC semiconductor layer102(body region126) appropriately across the gate insulating layer134.

The gate insulating layer134further includes a bulging portion134dwhich bulges toward an interior of the gate trench131at the opening edge portion132. The bulging portion134dis formed at a portion connecting the first region134aand the third region134cof the gate insulating layer134. The bulging portion134dbulges curvingly toward the inner side of the gate trench131. The bulging portion134dnarrows an opening of the gate trench131at the opening edge portion132.

Improvement of the dielectric withstand voltage of the gate insulating layer134at the opening edge portion132is achieved by the bulging portion134d. A gate insulating layer134not having the bulging portion134dmay be formed instead. A gate insulating layer134having a uniform thickness may be formed instead.

The gate electrode layer135is embedded in the gate trench131across the gate insulating layer134. More specifically, the gate electrode layer135is embedded in the recess space defined by the gate insulating layer134. The gate electrode layer135is controlled by the gate voltage.

The gate electrode layer135is formed as a wall extending along the normal direction N in sectional view. The gate electrode layer135has an upper end portion positioned at the opening side of the gate trench131. The upper end portion of the gate electrode layer135is formed in a curved shape recessed toward the bottom wall of the gate trench131. The upper end portion of the gate electrode layer135has a constricted portion that is constricted along the bulging portion134dof the gate insulating layer134.

A cross-sectional area of the gate electrode layer135in a direction (first direction X) orthogonal to the direction in which the gate trench131extends may be not less than 0.05 μm2and not more than 0.5 μm2. The cross-sectional area of the gate electrode layer135is defined as a product of a thickness of the gate electrode layer135along the normal direction N and a width of the gate electrode layer135along the first direction X.

The thickness of the gate electrode layer135is a distance from the upper end portion to a lower end portion of the gate electrode layer135. The width of the gate electrode layer135is a width of the gate electrode layer135at an intermediate position between the upper end portion and the lower end portion of the gate electrode layer135. When the upper end portion is a curved surface (a curved shape recessed toward the lower side in this embodiment), an intermediate position of the upper end portion of the gate electrode layer135is deemed to be the position of the upper end portion of the gate electrode layer135.

The cross-sectional area of the gate electrode layer135may be not less than 0.05 μm2and not more than 0.1 μm2, not less than 0.1 μm2and not more than 0.2 μm2, not less than 0.2 μm2and not more than 0.3 μm2, not less than 0.3 μm2and not more than 0.4 μm2, or not less than 0.4 μm2and not more than 0.5 μm2.

The gate electrode layer135may include at least one type of material among a conductive polysilicon, tungsten, aluminum, copper, an aluminum alloy and a copper alloy. In this embodiment, the gate electrode layer135includes a p type polysilicon doped with a p type impurity. The p type impurity of the gate electrode layer135may include at least one type of material among boron (B), aluminum (Al), indium (In) and gallium (Ga).

A p type impurity concentration of the gate electrode layer135is not less than the p type impurity concentration of the body region126. More specifically, the p type impurity concentration of the gate electrode layer135exceeds the p type impurity concentration of the body region126. The p type impurity concentration of the gate electrode layer135may be not less than 1×1018cm−3and not more than 1×1022cm−3. A sheet resistance of the gate electrode layer135may be not less than 10Ω/□ and not more than 500Ω/□ (approximately 200Ω/□ in this embodiment).

Referring toFIG.38andFIG.40, the SiC semiconductor device101further includes a gate wiring layer136formed in the active region106. InFIG.40, the gate wiring layer136is shown with hatching. The gate wiring layer136electrically connects the gate pad110(gate finger111) and the gate electrode layer135.

In this embodiment, the gate wiring layer136is formed on the first main surface103. More specifically, the gate wiring layer136is formed on the third region134cof the gate insulating layer134.

In this embodiment, the gate wiring layer136is formed along the gate finger111. More specifically, the gate wiring layer136is formed along the three side surfaces105A,105B and105D of the SiC semiconductor layer102and defines the inner region of the active region106from three directions.

The gate wiring layer136is connected to the gate electrode layer135exposed from the contact trench portion131bof each gate trench131. In this embodiment, the gate wiring layer136is formed by lead-out portions of the gate electrode layers135that are led out from the respective gate trenches131onto the first main surface103. An upper end portion of the gate wiring layer136is connected to the upper end portions of the gate electrode layers135.

Referring toFIG.38,FIG.39andFIG.41, the SiC semiconductor device101includes a plurality of source trenches141formed in the first main surface103in the active region106. Each source trench141is formed in a region between two mutually adjacent gate trenches131.

Each source trench141is formed as a band extending along the second direction Y. The plurality of source trenches141are formed as stripes extending along the second direction Y as a whole in plan view. The plurality of gate trenches131and the plurality of source trenches141are thereby formed as stripes formed alternately in the first direction X and extending along the second direction Y.

A pitch between central portions of two mutually adjacent source trenches141that are mutually adjacent in the first direction X may be not less than 1.5 μm and not more than 3 μm. The pitch of the source trenches141may be not less than 1.5 μm and not more than 2 μm, not less than 2 μm and not more than 2.5 μm, or not less than 2.5 μm and not more than 3 μm.

Each source trench141penetrates through the body region126and reaches the SiC epitaxial layer122. A bottom wall of each source trench141is positioned inside the SiC epitaxial layer122. More specifically, the bottom wall of each source trench141is positioned in the high concentration region122a.

In this embodiment, a depth of the source trench141in the normal direction N is not less than the depth of the gate trench131. More specifically, the depth of the source trench141exceeds the depth of the gate trench131. The bottom wall of the source trench141is positioned at the second main surface104side with respect to the bottom wall of the gate trench131.

In the normal direction N, the bottom wall of the source trench141is positioned in a region between the bottom wall of the gate trench131and the low concentration region122b. The bottom wall of the source trench141may be formed parallel to the first main surface103. The bottom wall of the source trench141may be formed in a shape curved toward the second main surface104.

Side wall of the source trench141may extend along the normal direction N. The side wall of the source trench141may be formed substantially perpendicular to the first main surface103. The source trench141may be formed in a tapered shape with a bottom area being less than an opening area.

A ratio of the depth of the source trench141with respect to the depth of the gate trench131may be not less than 1.5. The ratio of the depth of the source trench141with respect to the depth of the gate trench131is preferably not less than 2.

The depth of the source trench141may be not less than 0.5 μm and not more than 10 μm. The depth of the source trench141may be not less than 0.5 μm and not more than 1 μm, not less than 1 μm and not more than 2 μm, not less than 2 μm and not more than 4 μm, not less than 4 μm and not more than 6 μm, not less than 6 μm and not more than 8 μm, or not less than 8 μm and not more than 10 μm. The depth of the source trench141is preferably not less than 1 μm and not more than 6 μm.

A width of the source trench141may be not less than 0.1 μm and not more than 2 μm. The width of the source trench141may be not less than 0.1 μm and not more than 0.5 μm, not less than 0.5 μm and not more than 1 μm, not less than 1 μm and not more than 1.5 μm, or not less than 1.5 μm and not more than 2 μm. The width of the source trench141is preferably not less than 0.1 μm and not more than 0.5 μm. The width of the source trench141along the first direction X may be substantially equal to the width of the gate trench131along the first direction X. The width of the source trench141along the first direction X may be not less than the width of the gate trench131along the first direction X.

The SiC semiconductor device101includes a source insulating layer142and a source electrode layer143formed inside each source trench141. InFIG.38, each source insulating layer142and each source electrode layer143are shown with hatching.

The source insulating layer142may include silicon oxide. The source insulating layer142may include another insulating film of silicon nitride, etc. The source insulating layer142is formed as a film along inner wall surfaces of the source trench141and defines a recess space inside the source trench141.

The source insulating layer142includes a first region142aand a second region142b. The first region142ais formed along the side wall of the source trench141. The second region142bis formed along the bottom wall of the source trench141. A thickness T11of the first region142ais less than a thickness T12of the second region142b.

A ratio T12/T11of the thickness T12of the second region142bwith respect to the thickness T11of the first region142amay be not less than 2 and not more than 5. The thickness T11of the first region142amay be not less than 0.01 μm and not more than 0.2 μm. The thickness T12of the second region142bmay be not less than 0.05 μm and not more than 0.5 μm.

The thickness T11of the first region142amay be substantially equal to the thickness T1of the first region134aof the gate insulating layer134. The thickness T12of the second region142bmay be substantially equal to the thickness T2of the second region134bof the gate insulating layer134. Also, a source insulating layer142having a uniform thickness may be formed.

The source electrode layer143is embedded in the source trench141across the source insulating layer142. More specifically, the source electrode layer143is embedded in the recess space defined by the source insulating layer142. The source electrode layer143is controlled by the source voltage.

The source electrode layer143has an upper end portion positioned at an opening side of the source trench141. The upper end portion of the source electrode layer143is formed at the bottom wall side of the source trench141with respect to the first main surface103. The upper end portion of the source electrode layer143is formed in a curved shape recessed toward the bottom wall of the source trench141. The upper end portion of the source electrode layer143may be formed parallel to the first main surface103.

The upper end portion of the source electrode layer143may be positioned higher than the first main surface103. The upper end portion of the source electrode layer143may project higher than an upper end portion of the source insulating layer142. The upper end portion of the source electrode layer143may be positioned lower than the upper end portion of the source insulating layer142.

A thickness along the normal direction N of the source electrode layer143may be not less than 0.5 μm and not more than 10 μm (for example, approximately 1 μm). The thickness of the source electrode layer143may be not less than 0.5 μm and not more than 1 μm, not less than 1 μm and not more than 2 μm, not less than 2 μm and not more than 4 μm, not less than 4 μm and not more than 6 μm, not less than 6 μm and not more than 8 μm, or not less than 8 μm and not more than 10 μm. The thickness of the source electrode layer143is preferably not less than 1 μm and not more than 6 μm.

The source electrode layer143preferably includes a polysilicon having properties close to SiC in terms of material properties. Stress generated in the SiC semiconductor layer102due to the source electrode layer143can thereby be reduced. The source electrode layer143may preferably include the same conductive material type as the gate electrode layer135.

The source electrode layer143may include a conductive polysilicon. The source electrode layer143may include an n type polysilicon or a p type polysilicon as an example of a conductive polysilicon. In place of a conductive polysilicon, the source electrode layer143may include at least one type of material among tungsten, aluminum, copper, an aluminum alloy and a copper alloy.

If the gate electrode layer135includes a p type polysilicon doped with a p type impurity, the source electrode layer143preferably includes a p type polysilicon doped with a p type impurity. The source electrode layer143can thereby be formed at the same time as the gate electrode layer135.

In this case, the p type impurity of the source electrode layer143may include at least one type of material among boron (B), aluminum (Al), indium (In) and gallium (Ga). A p type impurity concentration of the source electrode layer143is not less than the p type impurity concentration of the body region126. More specifically, the p type impurity concentration of the source electrode layer143exceeds the p type impurity concentration of the body region126.

The p type impurity concentration of the source electrode layer143may be not less than 1×1018cm−3and not more than 1×1022cm−3. A sheet resistance of the source electrode layer143may be not less than 10Ω/□ and not more than 500Ω/□ (approximately 200Ω/□ in this embodiment).

The p type impurity concentration of the source electrode layer143may be substantially equal to the p type impurity concentration of the gate electrode layer135. The sheet resistance of the source electrode layer143may be substantially equal to the sheet resistance of the gate electrode layer135.

The SiC semiconductor device101thus has trench gate structures151and trench source structures152. Each trench gate structure151includes the gate trench131, the gate insulating layer134and the gate electrode layer135. Each trench source structure152includes the source trench141, the source insulating layer142and the source electrode layer143.

The SiC semiconductor device101includes n+type source regions153formed in regions of a surface layer portion of the body region126along the side wall of each gate trench131. An n type impurity concentration of the source regions153may be not less than 1.0×1018cm−3and not more than 1.0×1021cm−3. A plurality of the source regions153are formed along the side wall at one side and the side wall at another side of the gate trenches131in the first direction X.

The plurality of source regions153are respectively formed as bands extending along the second direction Y. The plurality of source regions153are formed as stripes as a whole in plan view. The respective source regions153are exposed from the side wall of the gate trenches131and the side wall of the source trenches141.

The SiC semiconductor device101includes a plurality of p+type contact regions154formed in the surface layer portion of the first main surface103. A p type impurity concentration of the contact regions154is greater than the p type impurity concentration of the body region126. The p type impurity concentration of the contact regions154may be not less than 1.0×1018cm−3and not more than 1.0×1021cm−3.

The plurality of p+type contact regions154are respectively formed along the side wall of the plurality of source trenches141. In this embodiment, a plurality of contact regions154are formed per one source trench141. The plurality of contact regions154are formed at intervals in the second direction Y such as to be oriented along the source trench141for one source trench141.

The plurality of contact regions154are formed at intervals in the first direction X from the gate trenches131. Thereby, each contact region154opposes a gate trench131across a source region153in plan view.

Each contact region154covers the side wall and the bottom wall of a source trench141. A bottom portion of each contact region154may be formed parallel to the bottom wall of a source trench141. More specifically, each contact region154integrally includes a first surface layer region154a, a second surface layer region154band an inner wall region154c.

Each first surface layer region154ais formed along a side wall at one side of a source trench141in the surface layer portion of the first main surface103. The first surface layer region154aextends from the side wall at one side of the source trench141toward the adjacent gate trench131. The first surface layer region154amay extend to an intermediate region between the source trench141and the gate trench131.

The second surface layer region154bis formed along the side wall at the other side of the source trench141in the surface layer portion of the first main surface103. The second surface layer region154bextends from the side surface at the other side of the source trench141toward the adjacent gate trench131. The second surface layer region154bmay extend to an intermediate region between the source trench141and the gate trench131.

The inner wall region154cis formed in a region of the SiC semiconductor layer102along the inner wall of the source trench141. The inner wall region154cis formed along the side wall of the source trench141. The inner wall region154ccovers corner portions connecting the side wall and the bottom wall of the source trench141. The inner wall region154ccovers the bottom wall of the source trench141from the side wall of the source trench141via the corner portions. The bottom portion of each contact region154is formed by the inner wall region154c.

The SiC semiconductor device101includes a plurality of p type deep well regions155formed in the surface layer portion of the first main surface103. The deep well regions155are also referred to as withstand voltage adjusting regions (withstand voltage holding regions) that adjust the withstand voltage of the SiC semiconductor layer102in the active region106.

The plurality of deep well regions155are formed in one-to-one correspondence with the plurality of source trenches141. Each deep well region155covers the inner wall of the corresponding source trench141across the contact region154. The deep well region155is formed as a band extending along the source trench141in plan view. The deep well region155is formed along the side wall of the source trench141.

The deep well region155covers the corner portions connecting the side wall and the bottom wall of the source trench141. The deep well region155covers the bottom wall of the source trench141from the side wall of the source trench141via the corner portions. The deep well region155is continuous to the body region126at the side wall of the source trench141.

The deep well region155is formed in the high concentration region122aof the SiC epitaxial layer122. The deep well region155has a bottom portion positioned at the second main surface104side with respect to the bottom wall of the gate trench131. The bottom portion of the deep well region155may be formed parallel to the bottom wall of the source trench141.

A p type impurity concentration of the deep well region155may be substantially equal to the p type impurity concentration of the body region126. The p type impurity concentration of the deep well region155may exceed the p type impurity concentration of the body region126. The p type impurity concentration of the deep well region155may be less than the p type impurity concentration of the body region126.

The p type impurity concentration of the deep well region155may be not more than the p type impurity concentration of the contact region154. The p type impurity concentration of the deep well region155may be less than the p type impurity concentration of the contact region154. The p type impurity concentration of the deep well region155may be not less than 1.0×1017cm−3and not more than 1.0×1019cm−3.

The deep well regions155form pn junction portions with the SiC semiconductor layer102(high concentration region122aof the SiC epitaxial layer122). Depletion layers spread toward the plurality of gate trenches131from the pn junction portions. The depletion layers spreading from the deep well regions155spread toward regions at the second main surface104side with respect to the bottom walls of the gate trenches131.

The depletion layers spreading from the deep well regions155may overlap with the bottom walls of the gate trenches131. The depletion layers spreading from the bottom portions of the deep well regions155may overlap with the bottom walls of the gate trenches131.

With an SiC semiconductor device that includes just a pn junction diode a problem of concentration of electric field inside the SiC semiconductor layer102does not occur frequently, due to the structure of not including trenches. The deep well regions155make the trench gate type MISFET approach the structure of a pn junction diode.

The electric field inside the SiC semiconductor layer102can thereby be relaxed in the trench gate type MISFET. Narrowing a pitch between the plurality of mutually adjacent deep well regions155is thus effective in terms of relaxing the concentration of electric field. With the deep well regions155having the bottom portions at the second main surface104side with respect to the bottom walls of the gate trenches131, concentration of electric field with respect to the gate trenches131can be relaxed appropriately by the depletion layers.

The bottom portions of the plurality of deep well regions155are preferably formed at a substantially fixed interval from the second main surface104. Occurrence of variation in distance between the bottom portion of each deep well region155and the second main surface104can thereby be suppressed. In this case, the withstand voltage (for example, an electrostatic breakdown strength) of the SiC semiconductor layer102can be suppressed from being restricted by the deep well regions155and therefore improvement of the withstand voltage can be achieved appropriately.

Also in this embodiment, the high concentration region122aof the SiC epitaxial layer122is interposed in the regions between the plurality of mutually adjacent deep well regions155. A JFET (junction field effect transistor) resistance can thereby be reduced in the regions between the plurality of deep well regions155.

Further, in this embodiment, the bottom portions of the deep well regions155are positioned inside the high concentration region122aof the SiC epitaxial layer122. Current paths can thereby be expanded in a lateral direction parallel to the first main surface103by using the high concentration region122apositioned directly below the deep well regions155. Consequently, a current spread resistance can be reduced. The low concentration region122bof the SiC epitaxial layer122increases the withstand voltage of the SiC semiconductor layer102in such a structure.

The deep well regions155are formed using the source trenches141. That is, the deep well regions155are formed conformally to the inner wall of the source trenches141. Occurrence of variation among the depths of the respective deep well regions155can thereby be suppressed appropriately. Also, by using the source trenches141, the deep well regions155can be formed appropriately in comparatively deep regions of the SiC semiconductor layer102.

The SiC semiconductor device101includes a plurality of source sub-trenches156formed in regions of the first main surface103along the upper end portions of the source electrode layers143. The plurality of source sub-trenches156are each in communication with the corresponding source trench141and form a portion of the side wall of the source trench141.

In this embodiment, the source sub-trench156is formed in an annular shape (for example, an endless shape) surrounding the upper end portion of the source electrode layer143in plan view. That is, the source sub-trench156borders the upper end portion of the source electrode layer143.

The source sub-trench156is formed by digging into a portion of the source insulating layer142. More specifically, the source sub-trench156is formed by digging into the upper end portion of the source insulating layer142and the upper end portion of the source electrode layer143from the first main surface103.

The upper end portion of the source electrode layer143has a shape that is constricted with respect to a lower end portion of the source electrode layer143. The lower end portion of the source electrode layer143is a portion of the source electrode layer143that is positioned at the bottom wall side of the source trench141. A width along the first direction X of the upper end portion of the source electrode layer143may be less than a width along the first direction X of the lower end portion of the source electrode layer143.

The source sub-trench156is formed to a convergent shape with a bottom area being less than an opening area in sectional view. A bottom wall of the source sub-trench156may be formed in a shape curved toward the second main surface104.

The source region153, the contact region154, the source insulating region142and the source electrode layer143are exposed from inner wall of the source sub-trench156. At least the first region142aof the source insulating layer142is exposed from the bottom wall of the source sub-trench156. An upper end portion of the first region142aof the source insulating layer142is positioned lower than the first main surface103.

An opening edge portion157of each source trench141includes an inclining portion158that inclines downwardly from the first main surface103toward an inner side of the source trench141. The opening edge portion157of the source trench141is a corner portion connecting the first main surface103and the side wall of the source trench141. The inclining portion158of the source trench141is formed by the source sub-trench156.

In this embodiment, the inclining portion158is formed in a curved shape recessed toward the SiC semiconductor layer102. The inclining portion158may instead be formed in a curved shape protruding toward the source sub-trench156. An electric field with respect to the opening edge portion157is relaxed by the inclining portion156.

The SiC semiconductor device101includes a low resistance electrode layer159formed on the gate electrode layer135. Inside the gate trench131, the low resistance electrode layer159covers the upper end portion of the gate electrode layer135. That is, the trench gate structure151includes the low resistance electrode layer159.

The low resistance electrode layer159includes a conductive material having a sheet resistance less than the sheet resistance of the gate electrode layer135. A sheet resistance of the low resistance electrode layer159may be not less than 0.01Ω/□ and not more than 10Ω/□. The sheet resistance of the low resistance electrode layer159may be not less than 0.01Ω/□ and not more than 0.1Ω/□, not less than 0.1Ω/□ and not more than 1Ω/□, not less than 1Ω/□ and not more than 2Ω/□, not less than 2Ω/□ and not more than 4Ω/□, not less than 4Ω/□ and not more than 6Ω/□, not less than 6Ω/□ and not more than 8Ω/□, or not less than 8Ω/□ and not more than 10Ω/□.

A current supplied into the gate trenches131flows through the low resistance electrode layer159, having the comparatively low sheet resistance, and is transmitted to entireties of the gate electrode layers135. The entireties of the gate electrode layers135can thereby be made to transition rapidly from an on state to an off state and therefore delay of switching response can be suppressed.

In particular, although time is required for transmission of current in a case of gate trenches131having a length of the millimeter order, the delay of the switching response can be suppressed appropriately by the low resistance electrode layer159. That is, the low resistance electrode layer159is formed as a current diffusing electrode layer that diffuses the current into the gate trenches131.

The low resistance electrode layer159is formed as a film. The low resistance electrode layer159has a connection portion159ain contact with the upper end portion of the gate electrode layer135and a non-connection portion159bopposite thereof. The connection portion159aand the non-connection portion159bof the low resistance electrode layer159may be formed in curved shapes conforming to the upper end portion of the gate electrode layer135. The connection portion159aand the non-connection portion159bof the low resistance electrode layer159may take on any of various configurations.

An entirety of the connection portion159aof the low resistance electrode layer159may be positioned higher than the first main surface103. The entirety of the connection portion159aof the low resistance electrode layer159may be positioned lower than the first main surface103.

The connection portion159aof the low resistance electrode layer159may include a portion positioned higher than the first main surface103. The connection portion159aof the low resistance electrode layer159may include a portion positioned lower than the first main surface103. For example, a central portion of the connection portion159aof the low resistance electrode layer159may be positioned lower than the first main surface103and a peripheral edge portion of the connection portion159aof the low resistance electrode layer159may be positioned higher than the first main surface103.

An entirety of the non-connection portion159bof the low resistance electrode layer159may be positioned higher than the first main surface103. The entirety of the non-connection portion159bof the low resistance electrode layer159may be positioned lower than the first main surface103.

The non-connection portion159bof the low resistance electrode layer159may include a portion positioned higher than the first main surface103. The non-connection portion159bof the low resistance electrode layer159may include a portion positioned lower than the first main surface103. For example, a central portion of the non-connection portion159bof the low resistance electrode layer159may be positioned lower than the first main surface103and a peripheral edge portion of the non-connection portion159bof the low resistance electrode layer159may be positioned higher than the first main surface103.

The low resistance electrode layer159has an edge portion159ccontacting the gate insulating layer134. The edge portion159cof the low resistance electrode layer159contacts a corner portion (the bulging portion134din this embodiment) which connects the first region134aand the second region134bat the gate insulating layer134.

The edge portion159cof the low resistance electrode layer159is formed in a region at the first main surface103side with respect to bottom portions of the source regions153. That is, the edge portion159cof the low resistance electrode layer159is formed in a region further to the first main surface103side than boundary regions between the body region126and the source regions153.

The edge portion159cof the low resistance electrode layer159thus opposes the source regions153across the gate insulating layer134. The edge portion159cof the low resistance electrode layer159does not oppose the body region126across the gate insulating layer134. Formation of a leakage current path in a region of the gate insulating layer134between the low resistance electrode layer159and the body region126can thereby be suppressed.

A leakage current path may be formed by undesired diffusion of an electrode material of the low resistance electrode layer159into the gate insulating layer134. Formation of a leakage current path can be suppressed appropriately by connecting the edge portion159cof the low resistance electrode layer159to the comparatively thick third region134c(the bulging portion134d) of the gate insulating layer134.

In regard to the normal direction N, a thickness TR of the low resistance electrode layer159is not more than a thickness TG of the gate electrode layer135(TR≤TG). More specifically, the thickness TR of the low resistance electrode layer159is not more than one-half the thickness TG of the gate electrode layer135(TR≤TG/2).

A ratio TR/TG of the thickness TR of the low resistance electrode layer159with respect to the thickness TG of the gate electrode layer135may be not less than 0.01 and not more than 1. The ratio TR/TG may be not less than 0.01 and not more than 0.1, not less than 0.1 and not more than 0.2, not less than 0.2 and not more than 0.4, not less than 0.4 and not more than 0.6, not less than 0.6 and not more than 0.8, or not less than 0.8 and not more than 1.

The thickness TG of the gate electrode layer135may be not less than 0.5 μm and not more than 3 μm. The thickness TG of the gate electrode layer135may be not less than 0.5 μm and not more than 1 μm, not less than 1 μm and not more than 1.5 μm, not less than 1.5 μm and not more than 2 μm, not less than 2 μm and not more than 2.5 μm, or not less than 2.5 μm and not more than 3 μm.

The thickness TR of the low resistance electrode layer159may be not less than 0.01 μm and not more than 3 μm. The thickness TR of the low resistance electrode layer159may be not less than 0.01 μm and not more than 0.1 μm, not less than 0.1 μm and not more than 0.5 μm, not less than 0.5 μm and not more than 1 μm, not less than 1 μm and not more than 1.5 μm, not less than 1.5 μm and not more than 2 μm, not less than 2 μm and not more than 2.5 μm, or not less than 2.5 μm and not more than 3 μm.

In this embodiment, the low resistance electrode layer159also covers the upper end portion of the gate wiring layer136. A portion of the low resistance electrode layer159that covers the upper end portion of the gate wiring layer136is formed integral to portions of the low resistance electrode layer159covering the upper end portions of the gate electrode layers135. The low resistance electrode layer159thereby covers entire areas of the gate electrode layers135and an entire area of the gate wiring layer136.

A current supplied from the gate pad110(gate finger111) to the gate wiring layer136thus flows through the low resistance electrode layer159of comparatively low sheet resistance and is transmitted to the entireties of the gate electrode layers135and the gate wiring layer136. The entireties of the gate electrode layers135can thereby be made to transition rapidly from the on state to the off state via the gate wiring layer136and therefore the delay of the switching response can be suppressed.

In particular, in the case of the gate trenches131having the length of the millimeter order, the delay of the switching response can be suppressed appropriately by the low resistance electrode layer159covering the upper end portion of the gate wiring layer136.

The low resistance electrode layer159includes a polycide layer. More specifically, the low resistance electrode layer159is constituted of a p type polycide layer that includes the p type impurity doped in the gate electrode layer135(p type polysilicon). The polycide layer is formed by a surface layer portion of the gate electrode layer135, which includes the p type polysilicon, being silicided by a metal material. The siliciding of the p type polysilicon is performed by a heat treatment. The heat treatment may be that by an RTA (rapid thermal annealing) method.

In this embodiment, the low resistance electrode layer159has a specific resistance of not less than 10 μΩ·cm and not more than 110 μΩ·cm. The specific resistance of the low resistance electrode layer159may be not less than 10 μΩ·cm and not more than 20 μΩ·cm, not less than 20 μΩ·cm and not more than 40 μΩ·cm, not less than 40 μΩ·cm and not more than 60 μΩ·cm, not less than 60 μΩ·cm and not more than 80 μΩ·cm, or not less than 80 μΩ·cm and not more than 110 μΩ·cm.

More specifically, the low resistance electrode layer159includes at least one type of material among TiSi, TiSi2, NiSi, CoSi, CoSi2, MoSi2and WSi2as a polycide. Among these types of materials, NiSi, CoSi2and TiSi2are suitable as the polycide layer forming the low resistance electrode layer159due to being comparatively low in specific resistance value and temperature dependence.

A sheet resistance inside the gate trench131embedded with the gate electrode layer135(p type polysilicon) and the low resistance electrode layer159(p type polycide) is not more than a sheet resistance of the gate electrode layer135(p type polysilicon) alone. The sheet resistance inside the gate trench131is preferably not more than a sheet resistance of an n type polysilicon doped with an n type impurity.

The sheet resistance inside the gate trench131is approximated by the sheet resistance of the low resistance electrode layer159. That is, the sheet resistance inside the gate trench131may be not less than 0.01Ω/□ and not more than 10Ω/□. The sheet resistance inside the gate trench131may be not less than 0.01Ω/□ and not more than 0.1Ω/□, not less than 0.1Ω/□ and not more than 1Ω/□, not less than 1Ω/□ and not more than 2Ω/□, not less than 2Ω/□ and not more than 4Ω/□, not less than 4Ω/□ and not more than 6Ω/□, not less than 6Ω/□ and not more than 8Ω/□, or not less than 8Ω/□ and not more than 10Ω/□. The sheet resistance inside the gate trench131is preferably less than 10Ω/□.

Referring toFIG.42andFIG.43, the active region106has an active main surface161forming a portion of the first main surface103. The outer region107has an outer main surface162forming a portion of the first main surface103. The outer main surface162is connected to the side surfaces105A to105D.

The outer main surface162is positioned at the second main surface104side with respect to the active main surface161. In this embodiment, the outer region107is formed by digging into the first main surface103toward the second main surface104side. The outer region107is thus formed in a region that is recessed toward the second main surface104side with respect to the active main surface161.

The outer main surface162may be positioned at the second main surface104side with respect to the bottom walls of the gate trenches131. The outer main surface162may be formed at a depth position substantially equal to the bottom walls of the source trenches141. That is, the outer main surface162may be positioned on substantially the same plane as the bottom walls of the source trenches141. A distance between the outer main surface162and the second main surface104may be substantially equal to a distance between the bottom wall of each source trench141and the second main surface104.

The outer main surface162may be positioned at the second main surface104side with respect to the bottom walls of the source trenches141. The outer main surface162may be positioned in a range of exceeding 0 μm and being not more than 1 μm to the second main surface104side with respect to the bottom walls of the source trenches141.

The SiC epitaxial layer122is exposed from the outer main surface162. More specifically, the high concentration region122aof the SiC epitaxial layer122is exposed from the outer main surface162. The outer main surface162opposes the low concentration region122bof the SiC epitaxial layer122across the high concentration region122aof the SiC epitaxial layer122.

In this embodiment, the active region106is defined as a mesa by the outer region107. That is, the active region106is formed as an active mesa163of mesa shape projecting further upward than the outer region107.

The active mesa163includes active side wall164connecting the active main surface161and the outer main surface162. The first main surface103of the SiC semiconductor layer102is formed by the active main surface161, the outer main surface162and the active side wall164.

In this embodiment, the active side wall164extend in a direction substantially perpendicular to the active main surface161(outer main surface162). The active side wall164may be inclined downward from the active main surface161toward the outer main surface162. The active side wall164defines a boundary region between the active region106and the outer region107.

The SiC epitaxial layer122is exposed from the active side wall164. More specifically, the high concentration region122aof the SiC epitaxial layer122is exposed from the active side wall164. A main structure of the MISFET can thereby be formed appropriately in the high concentration region122adefined by the active mesa163.

At least the body region126is exposed from a region of the active side wall164at the active main surface161side. InFIG.42andFIG.43, a configuration example where the body region126and the source regions153are exposed from the active side wall164is shown.

The SiC semiconductor device101includes a p+type diode region171, a p type outer deep well region172and a p type field limit structure173formed in a surface layer portion of the outer main surface162(first main surface103) in the outer region107.

The diode region171is formed in a region of the outer region107between the active side wall164and the side surfaces105A to105D. The diode region171is formed at intervals from the active side wall164and the side surfaces105A to105D.

The diode region171extends as a band along the active region106in plan view. In this embodiment, the diode region171is formed in an annular shape (for example, an endless shape) surrounding the active region106in plan view.

The diode region171overlaps with the source routing wiring114in plan view. The diode region171is electrically connected to the source routing wiring114. The diode region171forms a portion of the avalanche current absorbing structure.

The diode region171forms a pn junction portion with the SiC semiconductor layer102. More specifically, the diode region171is positioned inside the SiC epitaxial layer122. The diode region171thus forms the pn junction portion with the SiC epitaxial layer122.

Even more specifically, the diode region171is positioned inside the high concentration region122aof the SiC epitaxial layer122. The diode region171thus forms the pn junction portion with the high concentration region122aof the SiC epitaxial layer122. A pn junction diode174having the diode region171as an anode and the SiC semiconductor layer102as a cathode is thereby formed.

An entirety of the diode region171is positioned at the second main surface104side with respect to the bottom walls of the gate trenches131. A bottom portion of the diode region171is positioned at the second main surface104side with respect to the bottom walls of the source trenches141. The bottom portion of the diode region171may be formed at a depth position substantially equal to the bottom portions of the contact regions154. That is, the bottom portion of the diode region171may be positioned on substantially the same plane as the bottom portions of the contact regions154.

A distance between the bottom portion of the diode region171and the second main surface104may be substantially equal to a distance between the bottom portion of each contact region154and the second main surface104. The bottom portion of the diode region171may be positioned at the second main surface104side with respect to the bottom portions of the contact regions154. The bottom portion of the diode region171may be positioned in a range of exceeding 0 μm and being not more than 1 μm to the second main surface104side with respect to the bottom portions of the contact regions154.

A p type impurity concentration of the diode region171is substantially equal to the p type impurity concentration of the contact regions154. The p type impurity concentration of the diode region171exceeds the p type impurity concentration of the body region126. The p type impurity concentration of the diode region171may be not less than 1.0×1018cm−3and not more than 1.0×1021cm−3.

The outer deep well region172is formed in a region between the active side wall164and the diode region171in plan view. In this embodiment, the outer deep well region172is formed at intervals toward the diode region171side from the active side wall164. The outer deep well region172is also referred to as a withstand voltage adjusting region (withstand voltage holding region) that adjusts the withstand voltage of the SiC semiconductor layer102in the outer region107.

The outer deep well region172extends along the active region106in plan view. In this embodiment, the outer deep well region172is formed in an annular shape (for example, an endless shape) surrounding the active region106in plan view.

A bottom portion of the outer deep well region172is positioned at the second main surface104side with respect to the bottom portion of the diode region171. In this embodiment, the outer deep well region172covers the diode region171from the second main surface104side. The outer deep well region172may overlap with the source routing wiring114in plan view.

The outer deep well region172is electrically connected to the source routing wiring114via the diode region171. The outer deep well region172may form a portion of the pn junction diode174. The outer deep well region172may form a portion of the avalanche current absorbing structure.

An entirety of the outer deep well region172is positioned at the second main surface104side with respect to the bottom walls of the gate trenches131. The bottom portion of the outer deep well region172is positioned at the second main surface104side with respect to the bottom walls of the source trenches141.

The bottom portion of the outer deep well region172may be formed at a depth position substantially equal to the bottom portions of the deep well regions155. That is, the bottom portion of the outer deep well region172may be positioned on substantially the same plane as the bottom portions of the deep well regions155. A distance between the bottom portion of the outer deep well region172and the outer main surface162may be substantially equal to a distance between the bottom portion of each deep well region155and the bottom wall of the source trench141.

A distance between the bottom portion of the outer deep well region172and the second main surface104may be substantially equal to a distance between the bottom portion of each deep well region155and the second main surface104. Variation can thereby be suppressed from occurring between the distance between the bottom portion of the outer deep well region172and the second main surface104and the distance between the bottom portion of each deep well region155and the second main surface104.

In this case, the withstand voltage (for example, the electrostatic breakdown strength) of the SiC semiconductor layer102can be suppressed from being restricted by the outer deep well region172and the deep well region155and therefore improvement of the withstand voltage can be achieved appropriately.

The bottom portion of the outer deep well region172may be positioned at the second main surface104side with respect to the bottom portions of the deep well regions155. The bottom portion of the outer deep well region172may be positioned in a range of exceeding 0 μm and being not more than 1 μm to the second main surface104side with respect to the bottom portions of the deep well regions155.

A p type impurity concentration of the outer deep well region172may be not more than the p type impurity concentration of the diode region171. The p type impurity concentration of the outer deep well region172may be less than the p type impurity concentration of the diode region171.

The p type impurity concentration of the outer deep well region172may be substantially equal to the p type impurity concentration of the deep well regions155. The p type impurity concentration of the outer deep well region172may be substantially equal to the p type impurity concentration of the body region126.

The p type impurity concentration of the outer deep well region172may exceed the p type impurity concentration of the body region126. The p type impurity concentration of the outer deep well region172may be less than the p type impurity concentration of the body region126.

The p type impurity concentration of the outer deep well region172may be not more than the p type impurity concentration of the contact regions154. The p type impurity concentration of the outer deep well region172may be less than the p type impurity concentration of the contact regions154. The p type impurity concentration of the outer deep well region172may be not less than 1.0×1017cm−3and not more than 1.0×1019cm−3.

The field limit structure173is formed in a region between the diode region171and the side surfaces105A to105D in plan view. In this embodiment, the field limit structure173is formed at intervals toward the side surfaces105A to105D sides from the diode region171.

The field limit structure173includes one or a plurality of (for example, not less than two and not more than twenty) field limit regions. In this embodiment, the field limit structure173includes a field limit region group having a plurality of (five) field limit regions175A,175B,175C,175D and175E.

The field limit regions175A to175E are formed in that order at intervals along a direction away from the diode region171. The field limit regions175A to175E respectively extend as bands along the peripheral edge of the active region106in plan view.

More specifically, the field limit regions175A to175E are respectively formed as annular shapes (for example, an endless shapes) surrounding the active region106in plan view. Each of the field limit regions175A to175E is also referred to as an FLR (field limiting ring) region.

In this embodiment, bottom portions of the field limit regions175A to175E are positioned at the second main surface104side with respect to the bottom portion of the diode region171. In this embodiment, the field limit region175A at an innermost side among the field limit regions175A to175E covers the diode region171from the second main surface104side.

The field limit region175A may be overlapped in plan view with the source routing wiring114described above. The field limit region175A may be electrically connected to the source routing wiring114via the diode region171. The field limit region175A may form a portion of the pn junction diode174. The field limit region175A may form a portion of the avalanche current absorbing structure.

Entireties of the field limit regions175A to175E are positioned at the second main surface104side with respect to the bottom walls of the gate trenches131. The bottom portions of the field limit regions175A to175E are positioned at the second main surface104side with respect to the bottom walls of the source trenches141.

The field limit regions175A to175E may be formed at a depth position substantially equal to the deep well regions155(outer deep well region172). That is, the bottom portions of the field limit regions175A to175E may be positioned on substantially the same plane as the bottom portions of the deep well regions155(outer deep well region172).

The bottom portions of the field limit regions175A to175E may be positioned at the outer main surface162side with respect to the bottom portions of the deep well regions155(outer deep well region172). The bottom portions of the field limit regions175A to175E may be positioned at the second main surface104side with respect to the bottom portions of the deep well regions155(outer deep well region172).

Widths between mutually adjacent field limit regions175A to175E may differ from each other. The widths between mutually adjacent field limit regions175A to175E may increase in a direction away from the active region106. The widths between mutually adjacent field limit regions175A to175E may decrease in the direction away from the active region106.

Depths of the field limit regions175A to175E may differ from each other. The depths of the field limit regions175A to175E may decrease in the direction away from the active region106. The depths of the field limit regions175A to175E may increase in the direction away from the active region106.

A p type impurity concentration of the field limit regions175A to175E may be not more than the p type impurity concentration of the diode region171. The p type impurity concentration of the field limit regions175A to175E may be less than the p type impurity concentration of the diode region171.

The p type impurity concentration of the field limit regions175A to175E may be not more than the p type impurity concentration of the outer deep well region172. The p type impurity concentration of the field limit regions175A to175E may be less than the p type impurity concentration of the outer deep well region172.

The p type impurity concentration of the field limit regions175A to175E may be not less than the p type impurity concentration of the outer deep well region172. The p type impurity concentration of the field limit regions175A to175E may be greater than the p type impurity concentration of the outer deep well region172.

The p type impurity concentration of the field limit regions175A to175E may be not less than 1.0×1015cm−3and not more than 1.0×1018cm−3. Preferably, the p type impurity concentration of the field limit regions175A to175E< the p type impurity concentration of the outer deep well region172< the p type impurity concentration of the diode region171.

The field limit structure173relaxes concentration of electric field in the outer region107. The number, widths, depths, p type impurity concentration, etc., of the field limit regions may take on any of various values in accordance with the electric field to be relaxed.

The SiC semiconductor device101includes an outer insulating layer181formed on the outer main surface162(first main surface103) in the outer region107. The outer insulating layer181selectively covers the diode region171, the outer deep well region172and the field limit structure173in the outer region107.

The outer insulating layer181is formed as a film along the active side wall164and the outer main surface162. On the active main surface161, the outer insulating layer181is continuous to the gate insulating layer134. More specifically, the outer insulating layer181is continuous to the third region134cof the gate insulating layer134.

The outer insulating layer181may include silicon oxide. The outer insulating layer181may include another insulating film of silicon nitride, etc. In this embodiment, the outer insulating layer181is formed of the same insulating material type as the gate insulating layer134.

The outer insulating layer181includes a first region181aand a second region181b. The first region181aof the outer insulating layer181covers the active side wall164. The second region181bof the outer insulating layer181covers the outer main surface162.

A thickness of the second region181bof the outer insulating layer181may be not more than a thickness of the first region181aof the outer insulating layer181. The thickness of the second region181bof the outer insulating layer181may be less than the thickness of the first region181aof the outer insulating layer181.

The thickness of the first region181aof the outer insulating layer181may be substantially equal to the thickness of the first region134aof the gate insulating layer134. The thickness of the second region181bof the outer insulating layer181may be substantially equal to the thickness of the third region134cof the gate insulating layers134. An outer insulating layer181having a uniform thickness may be formed instead.

Referring toFIG.42andFIG.43, the SiC semiconductor device101further includes a side wall structure182covering the active side wall164. The side wall structure182protects and reinforces the active mesa163from the outer region107side.

The side wall structure182forms a level difference moderating structure that moderates a level difference183formed between the active main surface161and the outer main surface162. If an upper layer structure covering the boundary region between the active region106and the outer region107is formed, the upper layer structure covers the side wall structure182. The side wall structure182improves flatness of the upper layer structure.

The side wall structure182may have an inclining portion184that inclines downwardly from the active main surface161toward the outer main surface162. The level difference183can be moderated appropriately by the inclining portion184. The inclining portion184may be formed in a curved shape recessed toward the SiC semiconductor layer102side. The inclining portion184may be formed in a curved shape protruding outside the SiC semiconductor layer102.

The side wall structure182is formed self-aligningly with respect to the active main surface161. More specifically, the side wall structure182is formed along the active side wall164. In this embodiment, the side wall structure182is formed in an annular shape (for example, an endless shape) surrounding the active region106in plan view.

The side wall structure182may include an insulating material. In this case, an insulating property of the active region106with respect to the outer region107can be improved by the side wall structure182. The side wall structure182may include a conductive material.

The side wall structure182may include the same conductive material type as the gate electrode layers135. The side wall structure182may include the same conductive material type as the source electrode layers143. The side wall structure182can thereby be formed at the same time as the gate electrode layers135and/or the source electrode layers143.

In this embodiment, the side wall structure182includes a polysilicon. The side wall structure182may include an n type polysilicon or a p type polysilicon. If the gate electrode layer135includes a p type polysilicon doped with a p type impurity, the side wall structure182preferably includes a p type polysilicon doped with a p type impurity. The p type impurity of the side wall structure182may include at least one type of material among boron (B), aluminum (Al), indium (In) and gallium (Ga).

A p type impurity concentration of the side wall structure182is not less than the p type impurity concentration of the body region126. More specifically, the p type impurity concentration of the side wall structure182exceeds the p type impurity concentration of the body region126. The p type impurity concentration of the side wall structure182may be substantially equal to the p type impurity concentration of the gate electrode layer135. A sheet resistance of the source electrode layer143may be substantially equal to the sheet resistance of the gate electrode layer135.

The p type impurity concentration of the side wall structure182may be not less than 1×1018cm−3and not more than 1×1022cm−3. The sheet resistance of the side wall structure182may be not less than 10Ω/□ and not more than 500Ω/□ (approximately 200Ω/□ in this embodiment).

Referring toFIG.39toFIG.43, the SiC semiconductor device101includes the interlayer insulating layer191formed on the first main surface103. The interlayer insulating layer191selectively covers the active region106and the outer region107. The interlayer insulating layer191is formed as a film along the active main surface161and the outer main surface162.

In the active region106, the interlayer insulating layer191selectively covers the trench gate structures151, the gate wiring layer136and the trench source structures152. In the outer region107, the interlayer insulating layer191selectively covers the diode region171, the outer deep well region172and the field limit structure173.

In the boundary region between the active region106and the outer region107, the interlayer insulating layer191is formed along an outer surface (inclining portion184) of the side wall structure182. A peripheral edge portion of the interlayer insulating layer191may be formed flush with the side surfaces105A to105D.

The interlayer insulating layer191may include silicon oxide or silicon nitride. The interlayer insulating layer191may include PSG (phosphor silicate glass) and/or BPSG (boron phosphor silicate glass) as an example of silicon oxide.

The interlayer insulating layer191may have a single layer structure constituted of a PSG layer or a BPSG layer. The interlayer insulating layer191may have a laminated structure including a PSG layer or a BPSG layer laminated in that order from the first main surface103side. The interlayer insulating layer191may have a laminated structure including a BPSG layer or a PSG layer laminated in that order from the first main surface103side.

A gate contact hole192, source contact holes193, a diode contact hole194and an anchor hole195are formed in the interlayer insulating layer191. The gate contact hole192exposes the gate wiring layer136in the active region106. The gate contact hole192may be formed as a band oriented along the gate wiring layer136.

An opening edge portion of the gate contact hole192is formed in a shape curved toward an interior of the gate contact hole192. The opening edge portion of the gate contact hole192may be formed in a curved shape recessed toward the interlayer insulating layer191.

The source contact holes193expose the source regions153, the contact regions154and the trench source structures152in the active region106. The source contact holes193may be formed as bands oriented along the trench source structures152, etc.

An opening edge portion of each source contact hole193is formed in a shape curved toward an interior of the source contact hole193. The opening edge portion of the source contact hole193may be formed in a curved shape recessed toward an interior of the interlayer insulating layer191.

The diode contact hole194exposes the diode region171in the outer region107. The diode contact hole194may be formed as a band (more specifically, an endless shape (annular shape)) extending along the diode region171.

The diode contact hole194may expose the outer deep well region172and/or the field limit structure173. An opening edge portion of the diode contact hole194is formed in a shape curved toward an interior of the diode contact hole194. The opening edge portion of the diode contact hole194may be formed in a curved shape recessed toward the interior of the interlayer insulating layer191.

The anchor hole195is formed by digging into the interlayer insulating layer191in the outer region107. The anchor hole195exposes the first main surface103(outer main surface162). The anchor hole195is formed in a region between the field limit structure173and the side surfaces105A to105D in plan view.

Referring toFIG.37, the anchor hole195extends as a band along the active region106in plan view. In this embodiment, the anchor hole195is formed in an annular shape (for example, an endless shape) surrounding the active region106in plan view.

An opening edge portion of the anchor hole195is formed in a shape curved toward an interior of the anchor hole195. The opening edge portion of the anchor hole195may be formed in a curved shape recessed toward an interior of the interlayer insulating layer191.

Referring toFIG.42andFIG.44, an inclining portion196and a modified layer197are formed in the outer region107. The modified layer197is formed by SiC being modified to a different property. The inclining portion196and the modified layer197respectively correspond to the inclining portion41and the modified layer42according to the SiC semiconductor device21described above. The description related to the components of the modified layer42applies to the description of the components of the modified layer197(see alsoFIG.21andFIG.22).

The inclining portion196is formed at corner portions connecting the outer main surface162(first main surface103) and the side surfaces105A to105D. The corner portions of the SiC semiconductor layer102include corner portions connecting the outer main surface162and the side surfaces105A and105C and extending along the [1-100] direction. The corner portions of the SiC semiconductor layer102include corner portions connecting the outer main surface162and the side surfaces105B and105D and extending along the [11-20] direction.

The inclining portion196inclines downwardly from the outer main surface162toward the side surfaces105A to105D. The inclining portion196is formed by an inner wall of a depression recessed from the outer main surface162toward the second main surface104at the corner portions of the SiC semiconductor layer102.

In this embodiment, the inclining portion196is formed in the SiC epitaxial layer122. The inclining portion196is formed in a region at the outer main surface162side with respect to a boundary region between the SiC semiconductor substrate121and the SiC epitaxial layer122. The SiC epitaxial layer122is thus exposed from the inclining portion196.

More specifically, the inclining portion196is formed in a region of the SiC epitaxial layer122at the outer main surface162side with respect to a boundary region between the high concentration region122aand the low concentration region122b. That is, the high concentration region122ais exposed from the inclining portion196.

The inclining portion196has an upper side end portion196aand a lower side end portion196b. The upper side end portion196aof the inclining portion196is positioned at the outer main surface162side. The lower side end portion196bof the inclining portion196is positioned at the second main surface104side.

In this embodiment, the upper side end portion196aof the inclining portion196extends from the SiC epitaxial layer122toward an insulating laminated structure198, which includes the outer insulating layer181and the interlayer insulating layer191, and is continuous to the insulating laminated structure198. That is, the SiC epitaxial layer32and the insulating laminated structure198are exposed from the inclining portion41. A peripheral edge portion of the insulating laminated structure198is formed at an inner region of the SiC semiconductor layer102with respect to the side surfaces105A to105D. The insulating laminated structure198corresponds to the insulating layer35of the SiC semiconductor device21described above.

The upper side end portion196aof the inclining portion196is connected to an upper surface of the interlayer insulating layer191. An upper side connection portion196cof the inclining portion196that connects the upper side end portion196aof the inclining portion196and the upper surface of the insulating laminated structure198may be formed in a shape curved toward an outer side of the SiC semiconductor layer102.

The lower side end portion196bof the inclining portion196exposes the SiC epitaxial layer32. More specifically, the lower side end portion196bof the inclining portion196exposes the high concentration region122aof the SiC epitaxial layer32. The lower side end portion196bof the inclining portion196is connected to the side surfaces105A to105D. The lower side end portion196bof the inclining portion196may be formed in a shape curved toward the second main surface104.

Referring toFIG.44, a width WI of the inclining portion196may be not more than the in-plane variations of the side surfaces105A to105D. The width WI of the inclining portion196may be less than the in-plane variations of the side surfaces105A to105D. The width WI of the inclining portion196is a width in a direction orthogonal to a direction in which the inclining portion196extends in plan view.

The width WI of the inclining portion196may exceed 0 μm and be not more than 10 μm. The width WI of the inclining portion196may exceed 0 μm and be not more than 2 μm, be not less than 2 μm and not more than 4 μm, be not less than 4 μm and not more than 6 μm, be not less than 6 μm and not more than 8 μm, or be not less than 8 μm and not more than 10 μm. If the thickness of the SiC semiconductor layer102is not more than 150 μm, the width WI of the inclining portion196preferably exceeds 0 μm and is not more than 5 μm. More preferably, the width WI of the inclining portion196exceeds 0 μm and is not more than 2.5 μm.

A depth D of the inclining portion196may exceed 0 μm and be not more than 30 μm. The depth D of the inclining portion196is a distance in the normal direction N from the outer main surface162(first main surface103) to the lower side end portion196bof the inclining portion196. The depth D of the inclining portion196may exceed 0 μm and be not more than 5 μm, be not less than 5 μm and not more than 10 μm, be not less than 10 μm and not more than 15 μm, be not less than 15 μm and not more than 20 μm, be not less than 20 μm and not more than 25 μm, or be not less than 25 μm and not more than 30 μm. If the thickness of the SiC semiconductor layer102is not more than 150 μm, the depth D of the inclining portion196preferably exceeds 0 μm and is not more than 15 μm.

The modified layer197is formed in regions of the side surfaces105A to105D at the outer main surface103side. More specifically, the modified layer197is formed along the corner portions connecting the outer main surface162and the side surfaces105A to105D. Even more specifically, the modified layer197is formed at the corner portions connecting the outer main surface162and the side surfaces105A and105C and extending along the [1-100] direction. The modified layer197is formed at the corner portions connecting the outer main surface162and the side surfaces105B and105D and extending along the [11-20] direction.

In this embodiment, the modified layer197is formed in the SiC epitaxial layer122. More specifically, the modified layer197is formed in a region at the outer main surface162side with respect to the boundary region between the SiC semiconductor substrate121and the SiC epitaxial layer122. Even more specifically, the modified layer197is formed in the high concentration region122aof the SiC epitaxial layer122. In this embodiment, the modified layer197is formed in a region at the outer main surface162side with respect to the boundary region between the high concentration region122aand the low concentration region122b.

In this embodiment, the modified layer197extends as a band on the side surfaces105A to105D along directions parallel to the outer main surface162. That is, the modified layer197extends as a band along the [1-100] direction and the [11-20] direction. At the side surfaces105A to105D, the modified layer197is formed in an annular shape (for example, an endless shape) surrounding the outer region107.

Referring toFIG.44, a width WM of the modified layer197may be not more than the in-plane variations of the side surfaces105A to105D. The width WM of the modified layer197may be less than the in-plane variations of the side surfaces105A to105D. The width WM of the modified layer197is a width in a direction orthogonal to a direction in which the modified layer197extends in plan view.

The width WM of the modified layer197may exceed 0 μm and be not more than 10 μm. The width WM of the modified layer197may exceed 0 μm and be not more than 2 μm, be not less than 2 μm and not more than 4 μm, be not less than 4 μm and not more than 6 μm, be not less than 6 μm and not more than 8 μm, or be not less than 8 μm and not more than 10 μm. If the thickness of the SiC semiconductor layer102is not more than 150 μm, the width WM of the modified layer197preferably exceeds 0 μm and is not more than 5 μm. More preferably, the width WM of the modified layer197exceeds 0 μm and is not more than 2.5 μm.

A thickness T of the modified layer197may exceed 0 μm and be not more than 30 μm. The thickness T of the modified layer197is a thickness of the modified layer197along the normal direction N. The thickness T of the modified layer197may exceed 0 μm and be not more than 5 μm, be not less than 5 μm and not more than 10 μm, be not less than 10 μm and not more than 15 μm, be not less than 15 μm and not more than 20 μm, be not less than 20 μm and not more than 25 μm, or be not less than 25 μm and not more than 30 μm. If the thickness of the SiC semiconductor layer102is not more than 150 μm, the thickness T of the modified layer197preferably exceeds 0 μm and is not more than 15 μm.

The modified layer197is formed as a film along the inclining portion196of the SiC semiconductor layer102. A thickness of a portion of the modified layer197covering a bottom wall of the inclining portion196may be greater than a thickness of a portion of the modified layer197covering a side wall of the inclining portion196. The modified layer197may be formed in a uniform thickness along inner wall of the inclining portion196.

The modified layer197includes an upper side covering portion197aand a lower side covering portion197b. The upper side covering portion197aof the modified layer197covers the upper side end portion196aof the inclining portion196. The lower side covering portion197bof the modified layer197covers the lower side end portion196bof the inclining portion196.

The upper side covering portion197aof the modified layer197covers the SiC epitaxial layer122. More specifically, the upper side covering portion197aof the modified layer197covers the high concentration region122a. The modified layer197extends from the SiC epitaxial layer122toward the insulating laminated structure198and covers the insulating laminated structure198. The upper side covering portion197aof the modified layer197may be formed in a shape curved toward the outer side of the SiC semiconductor layer102.

The lower side covering portion197bof the modified layer197covers the SiC epitaxial layer122. More specifically, the lower side covering portion197bof the modified layer197covers the high concentration region122a. The lower side covering portion197bof the modified layer197includes a connection portion197cconnected to the side surfaces105A to105D. The connection portion197cof the modified layer197may be a cleavage portion of the modified layer197. The connection portion197cof the modified layer197may be formed flush with the side surfaces105A to105D.

The gate terminal electrode layer108and the source terminal electrode layer109are formed on the interlayer insulating layer191. Each of the gate terminal electrode layer108and the source terminal electrode layer109has a laminated structure that includes a barrier electrode layer201and a main electrode layer202laminated in that order from the first main surface103side.

The barrier electrode layer201may have a single layer structure constituted of a titanium layer or a titanium nitride layer. The barrier electrode layer201may have a laminated structure including a titanium layer and a titanium nitride layer that are laminated in that order from the first main surface103side.

A thickness of the main electrode layer202exceeds a thickness of the barrier electrode layer201. The main electrode layer202includes a conductive material having a lower resistance value than a resistance value of the barrier electrode layer201. The main electrode layer202may include at least one type of material among aluminum, copper, an aluminum alloy and a copper alloy. The main electrode layer202may include at least one type of material among an aluminum-silicon alloy, an aluminum-silicon-copper alloy and an aluminum-copper alloy. In this embodiment, the main electrode layer202includes an aluminum-silicon-copper alloy.

The gate finger111which is included in the gate terminal electrode layer108enters into the gate contact hole192from above the interlayer insulating layer191. The gate finger111is electrically connected to the gate wiring layer136inside the gate contact hole192. An electrical signal from the gate pad110is thereby transmitted to the gate electrode layer135via the gate finger111.

The source pad113included in the source terminal electrode layer109enters into the source contact holes193and the source sub-trenches156from above the interlayer insulating layer191. The source pad113is electrically connected to the source regions153, the contact regions154and the source electrode layers143inside the source contact holes193and the source sub-trenches156.

The source electrode layers143may be formed using partial regions of the source pad113. That is, the source electrode layers143may be formed by portions of the source pad113entering into the source trenches141.

The source routing wiring114included in the source terminal electrode layer109enters into the diode contact hole194from above the interlayer insulating layer191. The source routing wiring114is electrically connected to the diode region171inside the diode contact hole194.

The source connection portion115included in the source terminal electrode layer109crosses the side wall structure182from the active region106and is led out to the outer region107. The source connection portion115forms a portion of the upper layer structure covering the side wall structure182.

The SiC semiconductor device101includes a passivation layer203formed on the interlayer insulating layer191. The passivation layer203may include silicon oxide and/or silicon nitride. In this embodiment, the passivation layer203has a single layer structure constituted of a silicon nitride layer.

The passivation layer203is formed as a film along the interlayer insulating layer191. The passivation layer203selectively covers the active region106and the outer region107via the interlayer insulating layer191.

The passivation layer203crosses the side wall structure182from the active region106and is led out to the outer region107. The passivation layer203forms a portion of the upper layer structure covering the side wall structure182.

A gate sub-pad opening204and a source sub-pad opening205(see alsoFIG.37) are formed in the passivation layer203. The gate sub-pad opening204exposes the gate pad110. The source sub-pad opening205exposes the source pad113.

Referring toFIG.42, in the outer region107, the passivation layer203enters into the anchor hole195from above the interlayer insulating layer191. Inside the anchor hole195, the passivation layer203is connected to the outer main surface162(first main surface103). A recess, recessed in conformance to the anchor hole195is formed in a region of an outer surface of the passivation layer203positioned above the anchor hole195.

A peripheral edge portion of the passivation layer203may be formed flush with the side surfaces105A to105D. The peripheral edge portion of the passivation layer203may be formed in an inner region across intervals from the side surfaces105A to105D. That is, the peripheral edge portion of the passivation layer203may expose the interlayer insulating layer191.

The peripheral edge portion of the passivation layer203may be portions forming portions of dicing streets in a process of cutting out the SiC semiconductor device101from the 4H—SiC crystal structure body1. By exposing the outer main surface162(first main surface103) from the peripheral edge portion of the passivation layer203, it becomes unnecessary to physically cut the passivation layer203. The semiconductor device101can thus be cut out smoothly from the 4H—SiC crystal structure body1.

The resin layer116described above is formed on the passivation layer203. The resin layer116is formed as a film along the passivation layer203. The resin layer116selectively covers the active region106and the outer region107across the passivation layer203and the interlayer insulating layer191.

The resin layer116crosses the side wall structure182from the active region106and is led out to the outer region107. The resin layer116forms a portion of the upper layer structure covering the side wall structure182.

The gate pad opening117of the resin layer116is in communication with the gate sub-pad opening204of the passivation layer203. In this embodiment, inner wall of the gate pad opening117are positioned at outer sides of inner wall of the gate sub-pad opening204.

The inner wall of the gate pad opening117may be formed flush with the inner wall of the gate sub-pad opening204. The inner wall of the gate pad opening117may be positioned at inner sides of the inner wall of the gate sub-pad opening204. That is, the resin layer116may cover the inner wall of the gate sub-pad opening204.

The source pad opening118of the resin layer116is in communication with the source sub-pad opening205of the passivation layer203. In this embodiment, the inner wall of the source pad opening118are positioned at outer sides of the inner wall of the source sub-pad opening205.

The inner wall of the source pad opening118may be formed flush with the inner wall of the source sub-pad opening205. The inner wall of the source pad opening118may be positioned at inner sides of the inner wall of the source sub-pad opening205. That is, the resin layer116may cover the inner wall of the source sub-pad opening205.

Referring toFIG.42, the resin layer116has an anchor portion entering into the recess of the passivation layer203in the outer region107. An anchor structure, arranged to improve a connection strength of the resin layer116, is thus formed in the outer region107.

The anchor structure includes an uneven structure formed in the first main surface103in the outer region107. More specifically, the uneven structure (anchor structure) includes unevenness formed using the interlayer insulating layer191covering the outer main surface162. Even more specifically, the uneven structure (anchor structure) includes the anchor hole195formed in the interlayer insulating layer191.

The resin layer116is engaged with the anchor hole195. In this embodiment, the resin layer116is engaged with the anchor hole195via the passivation layer203. The connection strength of the resin layer116with respect to the first main surface103can thereby be improved and therefore, peeling of the resin layer116can be suppressed.

Also, the resin layer116exposes the modified layer197. By exposing the modified layer197from the resin layer116, it becomes unnecessary to physically cut the resin layer116. The SiC semiconductor device101can thus be cut out smoothly from the 4H—SiC crystal structure body1while achieving appropriate protection of the active region106and the outer region107by the resin layer116.

Even in the case of manufacturing the SiC semiconductor device101described above, the same effects as the effects described for the eleventh preferred embodiment can be exhibited.

Also, with the SiC semiconductor device101, depletion layers can be spread from boundary regions (pn junction portions) between the SiC semiconductor layer102and the deep well regions155. Consequently, current paths of a short-circuit current flowing between the source pad113and the drain pad123can be narrowed.

Also, a feedback capacitance Crss can be reduced inverse-proportionately by the depletion layers spreading from the boundary regions between the SiC semiconductor layer102and the deep well regions155. The feedback capacitance Crss is a static capacitance across the gate electrode layers135and the drain pad123. The SiC semiconductor device101can thus be provided with which the short-circuit capacity can be improved and the feedback capacitance can be reduced.

Preferably, the depletion layers spreading from the boundary regions (pn junction portions) between the SiC semiconductor layer102and the deep well regions155spread toward regions to the second main surface104side with respect to the bottom walls of the gate trenches131. Regions of the SiC semiconductor layer102occupied by the depletion layers can thereby be increased and the feedback capacitance Crss can thus be reduced appropriately. In this case, the depletion layers spreading from the bottom portions of the deep well regions155may overlap with the bottom walls of the gate trenches131.

Also, with the SiC semiconductor device101, the bottom portions of the plurality of deep well regions155are formed at a substantially fixed interval from the second main surface104. Occurrence of variation in the distance between the bottom portion of each deep well region155and the second main surface104can thereby be suppressed. Consequently, the withstand voltage (for example, the electrostatic breakdown strength) of the SiC semiconductor layer102can be suppressed from being restricted by the deep well regions155and therefore improvement of the withstand voltage can be achieved appropriately.

Also, with the SiC semiconductor device101, the diode region171is formed in the outer region107. The diode region171is electrically connected to the source terminal electrode layer109. An avalanche current generated in the outer region107can thereby be made to flow into the source terminal electrode layer109via the diode region171. Consequently, the avalanche current generated in the outer region107can be absorbed by the diode region171and the source terminal electrode layer109and stability of operation of the MISFET can thus be improved.

Also, with the SiC semiconductor device101, the outer deep well region172is formed in the outer region107. The withstand voltage of the SiC semiconductor layer102can thereby be adjusted in the outer region107.

In this case, the outer deep well region172is preferably formed at substantially the same depth position as the deep well regions155. The bottom portion of the outer deep well region172is preferably positioned on substantially the same plane as the bottom portions of the deep well regions155. The distance between the bottom portion of the outer deep well region172and the second main surface104is preferably substantially equal to the distance between the bottom portion of each deep well regions155and the second main surface104.

With these structures, variation can be suppressed from occurring between the distance between the bottom portion of the outer deep well region172and the second main surface104and the distance between the bottom portion of each deep well region155and the second main surface104. The withstand voltage (for example, the electrostatic breakdown strength) of the SiC semiconductor layer102can thereby be suppressed from being restricted by the outer deep well region172and the deep well regions155. Consequently, improvement of the withstand voltage can be achieved appropriately.

Also, with the SiC semiconductor device101, the outer region107is formed at the second main surface104side with respect to the active region106. The position of the bottom portion of the outer deep well region172can thereby be made to approach the positions of the bottom portions of the deep well regions155appropriately.

That is, by the outer region107positioned at the second main surface104side with respect to the active region106, a need to introduce the p type impurity to a comparatively deep position of the surface layer portion of the first main surface103during the forming of the outer deep well region172is eliminated. The position of the bottom portion of the outer deep well region172can thus be suppressed appropriately from deviating greatly with respect to the positions of the bottom portions of the deep well regions155.

Also, with the SiC semiconductor device101, the outer main surface162of the outer region107is positioned on substantially the same plane as the bottom walls of the source trenches141. Thereby, the deep well regions155and the outer deep well region172can be formed at substantially equal depth positions by introducing the p type impurity into the bottom walls of the source trenches141and the outer main surface162of the outer region107at an equal energy. Consequently, the position of the bottom portion of the outer deep well region172can be suppressed even more appropriately from deviating greatly with respect to the positions of the bottom portions of the deep well regions155.

Also, with the SiC semiconductor device101, the field limit structure173is formed in the outer region107. An electric field relaxation effect by the field limit structure173can thereby be obtained in the outer region107. The electrostatic breakdown strength of the SiC semiconductor layer102can thus be improved appropriately.

Also, with the SiC semiconductor device101, the active region106is formed as the active mesa163of mesa shape. The active mesa163includes the active side wall164connecting the active main surface161of the active region106and the outer main surface162of the outer region107.

The level difference moderating structure that moderates the level difference183between the active main surface161and the outer main surface162is formed in the region between the active main surface161and the outer main surface162. The level difference moderating structure includes the side wall structure182.

The level difference183between the active main surface161and the outer main surface162can thereby be moderated appropriately. The flatness of the upper layer structure formed on the side wall structure182can thus be improved appropriately. With the SiC semiconductor device101, the interlayer insulating layer191, the source terminal electrode layer109, the passivation layer203and the resin layer116are formed as an example of the upper layer structure.

Also, with the SiC semiconductor device101, the anchor structure, arranged to improve the connection strength of the resin layer116is formed in the outer region107. The anchor structure includes the uneven structure formed in the first main surface103of the SiC semiconductor layer102in the outer region107.

More specifically, the uneven structure (anchor structure) includes the unevenness formed using the interlayer insulating layer191formed on the first main surface103in the outer region107. Even more specifically, the uneven structure (anchor structure) includes the anchor hole195formed in the interlayer insulating layer191.

The resin layer116is engaged with the anchor hole195. In this embodiment, the resin layer116is engaged with the anchor hole195via the passivation layer203. The connection strength of the resin layer116with respect to the first main surface103can thereby be improved and therefore, peeling of the resin layer116can be suppressed appropriately.

Also, with the SiC semiconductor device101, the trench gate structures151, with each of which the gate electrode layer135is embedded across the gate insulating layer134in the gate trench131, are formed. With the trench gate structure151, the gate electrode layer135is covered by the low resistance electrode layer159in the limited space of the gate trench151.

The gate electrode layer135includes the p type polysilicon. The gate threshold voltage Vth can thereby be increased (for example, increased by approximately 1V). Also, the low resistance electrode layer159includes the conductive material having the sheet resistance less than the sheet resistance of the p type polysilicon. Reduction of the gate resistance can thereby be achieved. Consequently, a current can be diffused efficiently along the trench gate structures151and reduction of switching delay can thus be achieved.

Especially, with the structure where the gate electrode layer135is covered by the low resistance electrode layer159, the p type impurity concentration of the body region126does not have to be increased. The gate threshold voltage Vth can thus be increased while preventing the increase in channel resistance.

Also, with the SiC semiconductor device101, the gate wiring layer136is covered by the low resistance electrode layer159in the outer region107. Reduction of gate resistance of the gate wiring layer136can also be achieved thereby. Especially, with the structure where the gate electrode layers135and the gate wiring layer136are covered by the low resistance electrode layer159, the current can be diffused efficiently along the trench gate structures151. The reduction of switching delay can thus be achieved appropriately.

Features of the SiC semiconductor devices91to98according to the twelfth to nineteenth preferred embodiments (see alsoFIG.28toFIG.35) may be combined in the SiC semiconductor device101. Configurations in which the features of the SiC semiconductor devices91to98according to the twelfth to nineteenth preferred embodiments are incorporated in the SiC semiconductor device101shall now be described with reference toFIG.45toFIG.54.

FIG.45is an enlarged view of a region corresponding toFIG.44and is an enlarged view of an SiC semiconductor device211according to a twenty-first preferred embodiment of the present invention. In the following, structures corresponding to structures described with the SiC semiconductor device101shall be provided with the same reference symbols and description thereof shall be omitted.

Referring toFIG.45, the SiC semiconductor device211does not have the modified layer197. With the SiC semiconductor device211, just the inclining portion196is formed at the corner portions of the SiC semiconductor layer102.

Even in the case of manufacturing the SiC semiconductor device211described above, the same effects as the effects described for the twentieth preferred embodiment can be exhibited.

FIG.46is an enlarged view of a region corresponding toFIG.44and is an enlarged view of an SiC semiconductor device212according to a twenty-second preferred embodiment of the present invention. In the following, structures corresponding to structures described with the SiC semiconductor device101shall be provided with the same reference symbols and description thereof shall be omitted.

Referring toFIG.46, in this embodiment, the inclining portion196crosses the boundary region between the high concentration region122aand the low concentration region122band reaches the low concentration region122bin the SiC epitaxial layer122. The high concentration region122aand the low concentration region122bare exposed from the inclining portion196.

The lower side end portion196bof the inclining portion196is positioned in the low concentration region122b. In the low concentration region122b, the lower side end portion196bof the inclining portion196is connected to the side surfaces105A to105D. The lower side end portion196bof the inclining portion196may be formed in a shape curved toward the second main surface104.

In this embodiment, the modified layer197crosses the boundary region between the high concentration region122aand the low concentration region122band reaches the low concentration region122bin the SiC epitaxial layer122. The modified layer197covers the high concentration region122aand the low concentration region122b. The upper side covering portion197aof the modified layer197covers the high concentration region122a. The lower side covering portion197bof the modified layer197covers the low concentration region122b.

Even in the case of manufacturing the SiC semiconductor device212described above, the same effects as the effects described for the twentieth preferred embodiment can be exhibited.

FIG.47is an enlarged view of a region corresponding toFIG.44and is an enlarged view of an SiC semiconductor device213according to a twenty-third preferred embodiment of the present invention. In the following, structures corresponding to structures described with the SiC semiconductor device101shall be provided with the same reference symbols and description thereof shall be omitted.

Referring toFIG.47, the SiC semiconductor device213does not have the modified layer197. With the SiC semiconductor device213, just the inclining portion196is formed at the corner portions of the SiC semiconductor layer102.

In this embodiment, the inclining portion196crosses the boundary region between the high concentration region122aand the low concentration region122band reaches the low concentration region122bin the SiC epitaxial layer122. The high concentration region122aand the low concentration region122bare exposed from the inclining portion196.

The lower side end portion196bof the inclining portion196is positioned in the low concentration region122b. In the low concentration region122b, the lower side end portion196bof the inclining portion196is connected to the side surfaces105A to105D. The lower side end portion196bof the inclining portion196may be formed in a shape curved toward the second main surface104.

Even in the case of manufacturing the SiC semiconductor device213described above, the same effects as the effects described for the twentieth preferred embodiment can be exhibited.

FIG.48is an enlarged view of a region corresponding toFIG.44and is an enlarged view of an SiC semiconductor device214according to a twenty-fourth preferred embodiment of the present invention. In the following, structures corresponding to structures described with the SiC semiconductor device101shall be provided with the same reference symbols and description thereof shall be omitted.

Referring toFIG.48, in this embodiment, the inclining portion196crosses the boundary region between the SiC semiconductor substrate121and the SiC epitaxial layer122and reaches the SiC semiconductor substrate121. The SiC semiconductor substrate121and the SiC epitaxial layer122are exposed from the inclining portion196.

The lower side end portion196bof the inclining portion196exposes the SiC semiconductor substrate121. In the SiC semiconductor substrate121, the lower side end portion196bof the inclining portion196is connected to the side surfaces105A to105D. The lower side end portion196bof the inclining portion196may be formed in a shape curved toward the second main surface104.

In this embodiment, the modified layer197crosses the boundary region between the SiC semiconductor substrate121and the SiC epitaxial layer122and reaches the SiC semiconductor substrate121. The modified layer197covers the SiC semiconductor substrate121and the SiC epitaxial layer122. The upper side covering portion197aof the modified layer197covers the SiC epitaxial layer122. The lower side covering portion197bof the modified layer197covers the SiC semiconductor substrate121.

Even in the case of manufacturing the SiC semiconductor device214described above, the same effects as the effects described for the twentieth preferred embodiment can be exhibited.

FIG.49is an enlarged view of a region corresponding toFIG.44and is an enlarged view of an SiC semiconductor device215according to a twenty-fifth preferred embodiment of the present invention. In the following, structures corresponding to structures described with the SiC semiconductor device101shall be provided with the same reference symbols and description thereof shall be omitted.

Referring toFIG.49, the SiC semiconductor device215does not have the modified layer197. With the SiC semiconductor device215, just the inclining portion196is formed at the corner portions of the SiC semiconductor layer102.

In this embodiment, the inclining portion196crosses the boundary region between the SiC semiconductor substrate121and the SiC epitaxial layer122and reaches the SiC semiconductor substrate121. The SiC semiconductor substrate121and the SiC epitaxial layer122are exposed from the inclining portion196.

The lower side end portion196bof the inclining portion196exposes the SiC semiconductor substrate121. In the SiC semiconductor substrate121, the lower side end portion196bof the inclining portion196is connected to the side surfaces105A to105D. The lower side end portion196bof the inclining portion196may be formed in a shape curved toward the second main surface104.

Even in the case of manufacturing the SiC semiconductor device215described above, the same effects as the effects described for the twentieth preferred embodiment can be exhibited.

FIG.50is an enlarged view of a region corresponding toFIG.44and is an enlarged view of an SiC semiconductor device216according to a twenty-sixth preferred embodiment of the present invention. In the following, structures corresponding to structures described with the SiC semiconductor device101shall be provided with the same reference symbols and description thereof shall be omitted.

Referring toFIG.50, the SiC semiconductor device216does not have the inclining portion196at the corner portions of the SiC semiconductor layer102. The SiC semiconductor device216includes the modified layer197formed in thickness direction intermediate portions of the side surfaces105A to105D.

More specifically, the modified layer197is formed in a thickness direction intermediate portion of the SiC epitaxial layer122at the side surfaces105A to105D. The modified layer197is formed in the SiC epitaxial layer122at an interval toward the second main surface104side from the outer main surface162. The modified layer197is formed in the SiC epitaxial layer122at an interval toward the outer main surface162side from the boundary region between the SiC semiconductor substrate121and the SiC epitaxial layer122.

The modified layer197may be positioned in the high concentration region122a. The modified layer197may be positioned in the high concentration region122aat intervals from the outer main surface162and the low concentration region122b. The modified layer197may be positioned in the low concentration region122b. The modified layer197may be positioned in the low concentration region122bat intervals from the SiC semiconductor substrate121and the high concentration region122a.

The modified layer197may be formed in the high concentration region122aand the low concentration region122b. The modified layer197may be formed such as to cross the boundary region between the high concentration region122aand the low concentration region122b.

Even in the case of manufacturing the SiC semiconductor device216described above, the same effects as the effects described for the twentieth preferred embodiment can be exhibited.

FIG.51is an enlarged view of a region corresponding toFIG.44and is an enlarged view of an SiC semiconductor device217according to a twenty-seventh preferred embodiment of the present invention. In the following, structures corresponding to structures described with the SiC semiconductor device101shall be provided with the same reference symbols and description thereof shall be omitted.

Referring toFIG.51, the SiC semiconductor device217does not have the inclining portion196at the corner portions of the SiC semiconductor layer102. The SiC semiconductor device217includes the modified layer197formed in thickness direction intermediate portions of the side surfaces105A to105D.

More specifically, the modified layer197is formed in the SiC semiconductor substrate121and the SiC epitaxial layer122at the side surfaces105A to105D. The modified layer197is formed such as to cross the boundary region between the SiC semiconductor substrate121and the SiC epitaxial layer122.

The modified layer197is formed in the side surfaces105A to105D at intervals to the second main surface104side from the outer main surface162. The modified layer197is formed in the side surfaces105A to105D at intervals to the outer main surface162side from the second main surface104.

The modified layer197has an upper end portion positioned at the outer main surface162side and a lower end portion positioned at the second main surface104side. The upper end portion of the modified layer197is positioned in the SiC epitaxial layer122. The upper end portion of the modified layer197may be positioned in the low concentration region122b. The upper end portion of the modified layer197may cross the boundary region between the high concentration region122aand the low concentration region122band be positioned in the high concentration region122a. The lower end portion of the modified layer197is positioned in the SiC semiconductor substrate121.

Even in the case of manufacturing the SiC semiconductor device217described above, the same effects as the effects described for the twentieth preferred embodiment can be exhibited.

FIG.52is a sectional view of a region corresponding toFIG.44and is a sectional view of an SiC semiconductor device218according to a twenty-eighth preferred embodiment of the present invention. In the following, structures corresponding to structures described with the SiC semiconductor device101shall be provided with the same reference symbols and description thereof shall be omitted.

Referring toFIG.52, the inclining portion196and the modified layer197that are formed in the second main surface104in the outer region107are included.

The inclining portion196is formed at corner portions connecting the second main surface104and the side surfaces105A to105D. The corner portions of the SiC semiconductor layer102include corner portions connecting the second main surface104and the side surfaces105A and105C. Also, the corner portions of the SiC semiconductor layer102include corner portions connecting the second main surface104and the side surfaces105B and105D.

The inclining portion196is inclined downwardly from the second main surface104toward the side surfaces105A to105D. The inclining portion196is formed by an inner wall of a depression recessed from the second main surface104toward the second main surface104at the corner portions of the SiC semiconductor layer102.

The inclining portion196is formed in the SiC semiconductor substrate121. More specifically, the inclining portion196is formed at an interval toward the second main surface104side with respect to the boundary region between the SiC semiconductor substrate121and the SiC epitaxial layer122.

The inclining portion196has an upper side end portion196dand a lower side end portion196e. The upper side end portion196dof the inclining portion196is positioned at the outer main surface162side. The lower side end portion196eof the inclining portion196is positioned at the second main surface104side. The upper side end portion196dof the inclining portion196is continuous to the side surfaces105A to105D. The upper side end portion196dof the inclining portion196may be formed in a shape curved toward the outer main surface162. The lower side end portion196eof the inclining portion196is connected to the second main surface104.

The width WI of the inclining portion196may be not more than the in-plane variations of the side surfaces105A to105D. The width WI of the inclining portion196may be less than the in-plane variations of the side surfaces105A to105D. The width WI of the inclining portion196is the width in the direction orthogonal to the direction in which the inclining portion196extends in plan view.

The width WI of the inclining portion196may exceed 0 μm and be not more than 10 μm. The width WI of the inclining portion196may exceed 0 μm and be not more than 2.5 μm, be not less than 2.5 μm and not more than 5 μm, be not less than 5 μm and not more than 7.5 μm, or be not less than 7.5 μm and not more than 10 μm. If the thickness of the SiC semiconductor layer102is not more than 150 μm, the width WI of the inclining portion196preferably exceeds 0 μm and is not more than 5 μm. More preferably, the width WI of the inclining portion196exceeds 0 μm and is not more than 2.5 μm.

The depth D of the inclining portion196may exceed 0 μm and be not more than 30 μm. The depth D of the inclining portion196is the distance in the normal direction N from the second main surface104to the upper side end portion196dof the inclining portion196. The depth D of the inclining portion196may exceed 0 μm and be not more than 5 μm, be not less than 5 μm and not more than 10 μm, be not less than 10 μm and not more than 15 μm, be not less than 15 μm and not more than 20 μm, be not less than 20 μm and not more than 25 μm, or be not less than 25 μm and not more than 30 μm. If the thickness of the SiC semiconductor layer102is not more than 150 μm, the depth D of the inclining portion196preferably exceeds 0 μm and is not more than 15 μm.

The modified layer197is formed along the corner portions connecting the second main surface104and the side surfaces105A to105D. The modified layer197is formed in the SiC semiconductor substrate121. More specifically, the modified layer197is formed at the second main surface104side with respect to the boundary region between the SiC semiconductor substrate121and the SiC epitaxial layer122.

The modified layer197is formed along the corner portions connecting the second main surface104and the side surfaces105A and105C. The modified layer197is formed along the corner portions connecting the second main surface104and the side surfaces105B and105D. That is, the modified layer197extends as a band along the [1-100] direction and the [11-20] direction.

In this embodiment, the modified layer197extends as a band on the side surfaces105A to105D along directions parallel to the second main surface104. At the side surfaces105A to105D, the modified layer197is formed in an annular shape (for example, an endless shape) surrounding the outer region107.

The width WM of the modified layer197may be not more than the in-plane variations of the side surfaces105A to105D. The width WM of the modified layer197may be less than the in-plane variations of the side surfaces105A to105D. The width WM of the modified layer197is the width in the direction orthogonal to the direction in which the modified layer197extends in plan view.

The width WM of the modified layer197may exceed 0 μm and be not more than 10 μm. The width WM of the modified layer197may exceed 0 μm and be not more than 2 μm, be not less than 2 μm and not more than 4 μm, be not less than 4 μm and not more than 6 μm, be not less than 6 μm and not more than 8 μm, or be not less than 8 μm and not more than 10 μm. If the thickness of the SiC semiconductor layer102is not more than 150 μm, the width WM of the modified layer197preferably exceeds 0 μm and is not more than 5 μm. More preferably, the width WM of the modified layer197exceeds 0 μm and is not more than 2.5 μm.

The thickness T of the modified layer197may exceed 0 μm and be not more than 30 μm. The thickness T of the modified layer197is the thickness of the modified layer197along the normal direction N. The thickness T of the modified layer197may exceed 0 μm and be not more than 5 μm, be not less than 5 μm and not more than 10 μm, be not less than 10 μm and not more than 15 μm, be not less than 15 μm and not more than 20 μm, be not less than 20 μm and not more than 25 μm, or be not less than 25 μm and not more than 30 μm. If the thickness of the SiC semiconductor layer102is not more than 150 μm, the thickness T of the modified layer197preferably exceeds 0 μm and is not more than 15 μm.

The modified layer197is formed as a film along the inclining portion196of the SiC semiconductor layer102. The thickness of the portion of the modified layer197covering the bottom wall of the inclining portion196may be greater than the thickness of the portion of the modified layer197covering the side wall of the inclining portion196. The modified layer197may be formed in a uniform thickness along the inner wall of the inclining portion196.

The modified layer197includes an upper side covering portion197dand a lower side covering portion197e. The upper side covering portion197dof the modified layer197covers the upper side end portion196dof the inclining portion196. The lower side covering portion197eof the modified layer197covers the lower side end portion196eof the inclining portion196.

The upper side covering portion197dof the modified layer197includes a connection portion197fconnected to the side surfaces105A to105D. The connection portion197fof the modified layer197may be a cleavage portion of the modified layer197. The connection portion197fof the modified layer197may be formed flush with the side surfaces105A to105D.

Even in the case of manufacturing the SiC semiconductor device218described above, the same effects as the effects described for the twentieth preferred embodiment can be exhibited.

FIG.53is a sectional view of a region corresponding toFIG.44and is a sectional view of an SiC semiconductor device219according to a twenty-ninth preferred embodiment of the present invention. In the following, structures corresponding to structures described with the SiC semiconductor device101shall be provided with the same reference symbols and description thereof shall be omitted.

The SiC semiconductor device219does not have the modified layer197. The SiC semiconductor device219includes the inclining portion196that is formed in regions of the side surfaces105A to105D at the second main surface104side. The inclining portion196is formed at the corner portions connecting the second main surface104and the side surfaces105A to105D.

The corner portions of the SiC semiconductor layer102include the corner portions connecting the second main surface104and the side surfaces105A and105C. Also, the corner portions of the SiC semiconductor layer102include the corner portions connecting the second main surface104and the side surfaces105B and105D.

The inclining portion196is inclined downwardly from the second main surface104toward the side surfaces105A to105D. The inclining portion196is formed by an inner wall of a depression recessed from the second main surface104toward the second main surface104at the corner portions of the SiC semiconductor layer102.

The inclining portion196is formed in the SiC semiconductor substrate121. More specifically, the inclining portion196is formed at an interval toward the second main surface104side with respect to the boundary region between the SiC semiconductor substrate121and the SiC epitaxial layer122.

The inclining portion196has the upper side end portion196dand the lower side end portion196e. The upper side end portion196dof the inclining portion196is positioned at the outer main surface162side. The lower side end portion196eof the inclining portion196is positioned at the second main surface104side. The upper side end portion196dof the inclining portion196is continuous to the side surfaces105A to105D. The upper side end portion196dof the inclining portion196may be formed in a shape curved toward the outer main surface162. The lower side end portion196eof the inclining portion196is connected to the second main surface104.

The width WI of the inclining portion196may be not more than the in-plane variations of the side surfaces105A to105D. The width WI of the inclining portion196may be less than the in-plane variations of the side surfaces105A to105D. The width WI of the inclining portion196is the width in the direction orthogonal to the direction in which the inclining portion196extends in plan view.

The width WI of the inclining portion196may exceed 0 μm and be not more than 10 μm. The width WI of the inclining portion196may exceed 0 μm and be not more than 2.5 μm, be not less than 2.5 μm and not more than 5 μm, be not less than 5 μm and not more than 7.5 μm, or be not less than 7.5 μm and not more than 10 μm. If the thickness of the SiC semiconductor layer102is not more than 150 μm, the width WI of the inclining portion196preferably exceeds 0 μm and is not more than 5 μm. More preferably, the width WI of the inclining portion196exceeds 0 μm and is not more than 2.5 μm.

The thickness T of the modified layer197may exceed 0 μm and be not more than 30 μm. The thickness T of the modified layer197is the thickness of the modified layer197along the normal direction N. The thickness T of the modified layer197may exceed 0 μm and be not more than 5 μm, be not less than 5 μm and not more than 10 μm, be not less than 10 μm and not more than 15 μm, be not less than 15 μm and not more than 20 μm, be not less than 20 μm and not more than 25 μm, or be not less than 25 μm and not more than 30 μm. If the thickness of the SiC semiconductor layer102is not more than 150 μm, the thickness T of the modified layer197preferably exceeds 0 μm and is not more than 15 μm.

Even in the case of manufacturing the SiC semiconductor device219described above, the same effects as the effects described for the twentieth preferred embodiment can be exhibited.

FIG.54is a sectional view of a region corresponding toFIG.44and is a sectional view of the general arrangement of an SiC semiconductor device220according to a thirtieth preferred embodiment of the present invention. In the following, structures corresponding to structures described with the SiC semiconductor device101shall be provided with the same reference symbols and description thereof shall be omitted.

Referring toFIG.54, the SiC semiconductor device211does not have the inclining portion196at the corner portions at the first main surface103side and the corner portions at the second main surface104side of the SiC semiconductor layer102. The SiC semiconductor device211includes the modified layer197formed in thickness direction intermediate portions of the side surfaces105A to105D.

More specifically, the modified layer197is formed in a thickness direction intermediate portion of the SiC semiconductor substrate121at the side surfaces105A to105D. The modified layer197is formed in the SiC semiconductor substrate121at an interval toward the second main surface104side from the boundary region between the SiC semiconductor substrate121and the SiC epitaxial layer122. Also, the modified layer197is formed at an interval toward the SiC epitaxial layer122side with respect to the second main surface104.

Such a modified layer197is formed by adjusting a light converging point of laser light when irradiating the laser light onto the second main surface3of the 4H—SiC crystal structure body1(second main surface104of the SiC semiconductor layer102). In this case, the modified layer197is heated and cooled from the second main surface3side of the 4H—SiC crystal structure body1and the 4H—SiC crystal structure body1is cleaved. The step ofFIG.24Kdoes not necessarily have to be performed.

Even in the case of manufacturing the SiC semiconductor device220described above, the same effects as the effects described for the twentieth preferred embodiment can be exhibited.

FIG.55is a sectional view of a region corresponding toFIG.42and is a sectional view of an SiC semiconductor device221according to a thirty-first preferred embodiment of the present invention. In the following, structures corresponding to structures described with the SiC semiconductor device101shall be provided with the same reference symbols and description thereof shall be omitted.

Referring toFIG.55, in this embodiment, in the outer region107, a groove222oriented along the active region106is formed in the first main surface103of the SiC semiconductor layer102. The groove222is formed by digging into the first main surface103toward the second main surface104side.

The groove222is formed as a band extending along the active region106in plan view. In this embodiment, the groove222is formed in an annular shape (for example, an endless shape) surrounding the active region106in plan view.

The groove222includes an inner wall223, an outer wall224and a bottom wall225. The inner wall223of the groove222is positioned at the active region106side. The inner wall223of the groove222forms the active side wall164. The outer wall224of the groove222is positioned at the side surface105A to105D sides. The bottom wall225of the groove222connects the inner wall223and the outer wall224.

The bottom wall225of the groove222may be positioned at the second main surface104side with respect to the bottom walls of the gate trenches131. The groove222may be formed at a depth position substantially equal to the source trenches141. That is, the bottom wall225of the groove222may be positioned on substantially the same plane as the bottom walls of the source trenches141.

A distance between the bottom wall225of the groove222and the second main surface104may be substantially equal to the distance between the bottom walls of the source trenches141and the second main surface104. The bottom wall225of the groove222may be positioned at the second main surface104side with respect to the bottom walls of the source trenches141. The bottom wall225of the groove222may be positioned in a range of exceeding 0 μm and being not more than 1 μm to the second main surface104side with respect to the bottom walls of the source trenches141.

The bottom wall225of the groove222exposes the SiC epitaxial layer122. More specifically, the bottom wall225of the groove222exposes the high concentration region122aof the SiC epitaxial layer122. The bottom wall225of the groove222opposes the low concentration region122bacross the high concentration region122a.

The inner wall223of the groove222defines the active mesa163. Together with the side surfaces105A to105D, the outer wall224at the outer region107defines an outer mesa226projecting higher than the bottom wall225of the groove222. In a configuration where the groove222is formed in an annular shape (for example, an endless shape), the outer mesa226is formed in an annular shape (for example, an endless shape) surrounding the groove222in plan view.

The outer mesa226includes a mesa main surface227. The mesa main surface227forms a portion of the first main surface103. The mesa main surface227is positioned on substantially the same plane as the active main surface161of the active region106. The mesa main surface227extends parallel to the bottom wall225of the groove222.

In this embodiment, a p type impurity region228is formed in a surface layer portion of the mesa main surface227of the outer mesa226. The p type impurity region228is formed in an electrically floating state. The p type impurity region228may have a p type impurity concentration substantially equal to the p type impurity concentration of the body region126.

In this embodiment, in the outer mesa226, an n type impurity region229is formed in a surface layer portion of the p type impurity region228. The n type impurity region229is formed in an electrically floating state. The n type impurity region229may have an n type impurity concentration substantially equal to the n type impurity concentration of the source regions153.

With the exception of the point of being formed along the bottom wall225of the groove222, the diode region171, the outer deep well region172and the field limit structure173described above respectively have substantially the same structures as the diode region171, the outer deep well region172and the field limit structure173of the semiconductor device101.

The outer insulating layer181is formed as a film along the inner wall of the groove222and the mesa main surface227of the outer mesa226. In the groove222, an outer wall side wall230is formed in addition to the side wall structure182.

With the exception of the point of covering the outer wall224of the groove222, the outer wall side wall230has substantially the same structure as the side wall structure182. The descriptions of the active side wall164and the side wall structure182apply to the descriptions of the outer wall224of the groove222and the outer wall side wall230.

In this embodiment, the anchor structure arranged to improve the connection strength of the resin layer116is formed in the mesa main surface227. The anchor structure includes an uneven structure formed in a portion of the interlayer insulating layer191covering the mesa main surface227. The uneven structure has the anchor hole195formed in the interlayer insulating layer191. The passivation layer203contacts the mesa main surface227in the anchor hole195.

The resin layer116is engaged with the anchor hole195. In this embodiment, the resin layer116is engaged with the anchor hole195via the passivation layer203. The connection strength of the resin layer116with respect to the first main surface103can thereby be improved and therefore, peeling of the resin layer116can be suppressed appropriately. The anchor structure for the resin layer116may be formed in the bottom wall225of the groove222instead.

In this embodiment, the inclined portion196and the modified layer197are formed along corner portions connecting the side surfaces105A to105D and the mesa main surface227. In regard to the inclined portion196and the modified layer197, at least one configuration among those of the nineteenth to thirtieth preferred embodiments is applied. Specific description of the inclined portion196and the modified layer197shall be omitted.

Even in the case of manufacturing the SiC semiconductor device221described above, the same effects as the effects described for the twentieth preferred embodiment can be exhibited.

FIG.56is a sectional view of a region corresponding toFIG.42and is a sectional view of an SiC semiconductor device241according to a thirty-second preferred embodiment of the present invention. In the following, structures corresponding to structures described with the semiconductor device101shall be provided with the same reference symbols and description thereof shall be omitted.

Referring toFIG.56, in this embodiment, the active main surface161of the active region106and the outer main surface162of the outer region107are formed flush. In this embodiment, the active region106is defined by the body region126.

In this embodiment, a distance between the outer main surface162and the bottom portion of the diode region171is substantially equal to a distance between the bottom walls of the source trenches144and the bottom portions of the contact regions154.

In this embodiment, a distance between the outer main surface162and the bottom portion of the outer deep well region172is substantially equal to a distance between the bottom walls of the source trenches144and the bottom portions of the deep well regions155.

In this embodiment, a distance between the outer main surface162and a bottom portion of the field limit structure173is substantially equal to the distance between the outer main surface162and the bottom portion of the outer deep well region172.

Even in the case of manufacturing the SiC semiconductor device241described above, the same effects as the effects described for the twentieth preferred embodiment can be exhibited.

FIG.57is a sectional view of a region corresponding toFIG.42and is a sectional view of an SiC semiconductor device251according to a thirty-third preferred embodiment of the present invention. In the following, structures corresponding to structures described with the semiconductor device101shall be provided with the same reference symbols and description thereof shall be omitted.

Referring toFIG.57, in this embodiment, the active main surface161of the active region106and the outer main surface162of the outer region107are formed flush. In this embodiment, the active region106is defined by the body region126.

The bottom portion of the diode region171may be formed at substantially the same depth position as the bottom portions of the contact regions154. That is, the bottom portion of the diode region171may be positioned on the same plane as the bottom portions of the contact regions154.

The bottom portion of the outer deep well region172may be formed at substantially the same depth position as the bottom portions of the deep well regions155. That is, the bottom portion of the outer deep well region172may be positioned on the same plane as the bottom portions of the deep well regions155.

The bottom portion of the field limit structure173may be formed at substantially the same depth position as the bottom portion of the outer deep well region172. That is, the bottom portion of the field limit structure173may be positioned on the same plane as the bottom portion of the outer deep well region172.

Even in the case of manufacturing the SiC semiconductor device251described above, the same effects as the effects described for the twentieth preferred embodiment can be exhibited.

FIG.58is an enlarged view of a region corresponding toFIG.38and is an enlarged view of an SiC semiconductor device261according to a thirty-fourth preferred embodiment of the present invention.FIG.59is a sectional view taken along line LIX-LIX shown inFIG.58. In the following, structures corresponding to structures described with the semiconductor device101shall be provided with the same reference symbols and description thereof shall be omitted.

Referring toFIG.58andFIG.59, the semiconductor device261includes an outer gate trench262formed in the first main surface103(active main surface161) in the active region106. The outer gate trench262extends as a band along the peripheral edge portions of the active region106(active side wall164).

The outer gate trench262is formed in a region of the first main surface103of directly below the gate finger111(outer gate finger111A). The outer gate trench262extends along the gate finger111(outer gate finger111A).

More specifically, the outer gate trench262is formed along the three side surfaces105A,105B and105D of the SiC semiconductor layer102and defines the inner region of the active region106from three directions. The outer gate trench262may be formed in an annular shape (for example, an endless shape) that surrounds the inner region of the active region106.

The outer gate trench262is in communication with the contact trench portion131bof each gate trench131. The outer gate trench262and the gate trenches131are thereby formed by a single trench.

The gate wiring layer136is embedded in the outer gate trench262across the gate insulating layer134. The gate wiring layer136is connected to the gate electrode layers135at communication portions of the gate trenches131and the outer gate trench262.

The low resistance electrode layer159, covering the upper surface of the gate wiring layer136, may be formed in the outer gate trench262. In this case, the low resistance electrode layer159covering the gate electrode layers135and the low resistance electrode layer159covering the gate wiring layer136are formed inside a single trench.

Even in the case of manufacturing the SiC semiconductor device261described above, the same effects as the effects described for the twentieth preferred embodiment can be exhibited. Also, with the semiconductor device261, the gate wiring layer136is not required to be led out to above the first main surface103.

The gate wiring layer136can thereby be suppressed from opposing the SiC semiconductor layer102across the gate insulating layer134at the opening edge portions of the gate trenches131and the outer gate trench262. Consequently, the concentration of electric field at the opening edge portions of the gate trenches131can be suppressed.

FIG.60is an enlarged view of a region corresponding toFIG.38and is an enlarged view of an SiC semiconductor device271according to a thirty-fifth preferred embodiment of the present invention. In the following, structures corresponding to structures described with the semiconductor device101shall be provided with the same reference symbols and description thereof shall be omitted.

Referring toFIG.60, in this embodiment, the gate trenches131are formed in a lattice shape that integrally includes a plurality of gate trenches131extending along the first direction X and a plurality of gate trenches131extending along the second direction Y in plan view.

A plurality of cell regions272are defined in a matrix by the gate trenches131in the first main surface103. Each cell region272is formed in a quadrilateral shape in plan view. The source trenches411are formed respectively in the plurality of cell regions272. Each source trench411may be formed in a quadrilateral shape in plan view.

A sectional view taken along line XXXIX-XXXIX ofFIG.60corresponds to the sectional view ofFIG.39. A sectional view taken along line XL-XL ofFIG.60corresponds to the sectional view ofFIG.40.

Even in the case of manufacturing the SiC semiconductor device271described above, the same effects as the effects described for the twentieth preferred embodiment can be exhibited.

Although the preferred embodiments of the present invention have been described above, the present invention may also be implemented in other configurations.

With each of the eleventh to thirty-fifth preferred embodiments described above, an example where the side surfaces25A to25D or105A to105D of the SiC semiconductor layer22or102are formed along the [11-20] direction and the [1-100] direction was described. However, the side surfaces25A to25D or105A to105D may be formed along a crystal direction equivalent to the [11-20] direction and a crystal direction equivalent to the [1-100] direction instead of the [11-20] direction and the [1-100] direction.

That is, the side surfaces25A to25D or105A to105D may be formed along the [−12-10] direction, the [−2110] direction, the [−1-120] direction, the [1-210] direction, or the [2-1-10] direction instead of the [11-20] direction. Also, the side surfaces25A to25D or105A to105D may be formed along the [01-10] direction, the [−1100] direction, the [−1010] direction, the [0-110] direction, or the [10-10] direction instead of the [1-100] direction.

When the SiC semiconductor layer22or102is formed in a rectangular shape in plan view, side surfaces among the side surfaces25A to25D or105A to105D that form the long sides are preferably formed along a nearest neighbor direction.

With each of the twentieth to thirty-fifth preferred embodiments described above, an example where the gate electrode layers135and the gate wiring layer136that include the p type polysilicon doped with the p type impurity are formed was described. However, if increase of the gate threshold voltage Vth is not emphasized, the gate electrode layers135and the gate wiring layer136may include an n type polysilicon doped with an n type impurity instead of the p type polysilicon.

In this case, the low resistance electrode layer159may include an n type polycide, with which the gate electrode layer135(n type polysilicon) is silicided. With such a structure, reduction of gate resistance can be achieved.

With each of the twentieth to thirty-fifth preferred embodiments described above, an example where the SiC semiconductor layer102has the laminated structure that includes the SiC semiconductor substrate121and the SiC epitaxial layer122was described. However, the SiC semiconductor layer102may instead have a single layer structure constituted of the SiC semiconductor substrate121or the SiC epitaxial layer122. An n+type drain region may be formed by implantation of an n type impurity into the second main surface104.

With each of the twentieth to thirty-fifth preferred embodiments described above, an example where the SiC epitaxial layer122, having the high concentration region122aand the low concentration region122bis formed by the epitaxial growth method was described. However, the SiC epitaxial layer122may instead be formed by steps such as the following.

First, the SiC epitaxial layer122, having a comparatively low n type impurity concentration is formed by an epitaxial growth method. Next, the n type impurity is introduced into a surface layer portion of the SiC epitaxial layer122by an ion implantation method. The SiC epitaxial layer112, having the high concentration region122aand the low concentration region122b, is thereby formed.

With each of the twentieth to thirty-fifth preferred embodiments described above, if the source electrode layers143include a polysilicon (n type polysilicon or p type polysilicon), a low resistance electrode layer (159) covering the source electrode layers143inside the source trenches141may be formed.

With each of the twentieth to thirty-fifth preferred embodiments, a p+type SiC semiconductor substrate (121) may be adopted in place of the n+type SiC semiconductor substrate121. With this structure, an IGBT (insulated gate bipolar transistor) can be provided in place of a MISFET.

In this case, the “source” of the MISFET is replaced by an “emitter” of the IGBT. Also, the “drain” of the MISFET is replaced by a “collector” of the IGBT. Even when an IGBT is adopted in place of a MISFET, the same effects as the effects described above for the twentieth to thirty-fifth preferred embodiments can be exhibited.

With each of the preferred embodiments described above, a structure with which the conductivity types of the respective semiconductor portions are inverted may be adopted. That is, a p type portion may be formed to be of an n type and an n type portion may be formed to be of a p type.

With each of the preferred embodiments described above, an example where the 4H—SiC crystal structure body1is cleaved was described. However, the 4H—SiC crystal structure body1may instead be cut by a dicing blade, etc. Even in this case, the 4H—SiC crystal structure body1can be cut appropriately from two different directions. However, in this case, there is concern for wear of the dicing blade and elongation of cutting time and therefore cleaving is more preferable.

The ideas and technical ideas of the respective preferred embodiments described above can also be applied to a semiconductor device besides a SiC semiconductor device. For example, the ideas and technical ideas of the respective preferred embodiments described above can also be applied to a semiconductor laser device that includes a crystal structure body constituted of a hexagonal crystal or to a semiconductor light emitting device that includes a crystal structure body constituted of a hexagonal crystal.

The present specification does not restrict any combined configuration of features illustrated with the first to thirty-fifth preferred embodiments. The first to thirty-fifth preferred embodiments may be combined among each other in any mode or any configuration.

Examples of features extracted from the present specification and drawings are indicated below.

[A1] A crystal cutting method including a step of preparing a crystal structure body constituted of a hexagonal crystal, a first cutting step of cutting the crystal structure body along an intersecting direction intersecting a nearest atom direction of the crystal structure body and forming a first cut portion in the crystal structure body, and a second cutting step of cutting the crystal structure body along the nearest neighbor direction and forming a second cut portion crossing the first cut portion, in the crystal structure body.

According to this crystal cutting method, the crystal structure body is cut along the nearest neighbor direction intersecting direction in the first cutting step. The crystal structure body is cut along the nearest neighbor direction in the second cutting step.

In the first cutting step, the uncut crystal structure body is cut and therefore stress to the crystal structure body does not become discontinuous. Forming of a bulging portion in the first cut portion can thereby be suppressed. On the other hand, in the second cutting step, stress to the crystal structure body becomes discontinuous because the crystal structure body has been cut in the nearest neighbor direction intersecting direction. However, in the second cutting step, stress is applied to the crystal structure body along the nearest neighbor direction and the crystal structure body is cut along the nearest neighbor direction.

Forming of a bulging portion in the second cut portion can thereby be suppressed and flatness of the first cut portion and the second cut portion can thus be improved. A crystal cutting method that enables a crystal structure body constituted of a hexagonal crystal to be cut appropriately from two different directions can thus be provided.

[A2] The crystal cutting method according to A1, wherein the first cutting step includes a first cleaving step of cleaving the crystal structure body along the intersecting direction and the second cutting step includes a second cleaving step of cleaving the crystal structure body along the nearest neighbor direction.

[A3] The crystal cutting method according to A2, further including a step of forming a first cleavage line oriented along the intersecting direction by heating a region of the crystal structure body to be cleaved along the intersecting direction in advance of the first cutting step, and a step of forming a second cleavage line oriented along the nearest neighbor direction by heating a region of the crystal structure body to be cleaved along the nearest neighbor direction in advance of the second cutting step, wherein the first cutting step includes the first cleaving step of cleaving the crystal structure body with the first cleavage line as a starting point and the second cutting step includes the second cleaving step of cleaving the crystal structure body with the second cleavage line as a starting point.

[A4] The crystal cutting method according to A3, wherein the step of forming the first cleavage line includes a step of forming a first modified layer in which a crystal structure is modified to a different property by heating, in the crystal structure body, and the step of forming the second cleavage line includes a step of forming a second modified layer in which a crystal structure is modified to a different property by heating, in the crystal structure body.

[A5] The crystal cutting method according to A3 or A4, wherein the first cleaving step includes a step of cleaving the crystal structure body with the first cleavage line as the starting point by heating and cooling the first cleavage line, and the second cleaving step includes a step of cleaving the crystal structure body with the second cleavage line as the starting point by heating and cooling the second cleavage line.

[A6] The crystal cutting method according to any one of A1 to A5, wherein the nearest neighbor direction is a [11-20] direction, a [−12-10] direction, or a [−2110] direction of the hexagonal crystal.

[A7] The crystal cutting method according to any one of A1 to A6, wherein the crystal structure body is constituted of an SiC crystal structure body having a silicon plane and a carbon plane as crystal planes and the nearest neighbor direction is an arrangement direction of nearest neighboring Si atoms in a plan view viewed from a normal direction of the silicon plane.

[B1] A crystal cutting method including a step of preparing an SiC crystal structure body constituted of a hexagonal crystal having a silicon plane and a carbon plane as crystal planes, a first cleaving step of cleaving the SiC crystal structure body along an intersecting direction intersecting an arrangement direction of nearest neighboring Si atoms in a plan view viewed from a normal direction of the silicon plane and forming a first cleavage portion in the SiC crystal structure body, and a second cleaving step of cleaving the SiC crystal structure body along the arrangement direction and forming a second cleavage portion crossing the first cleavage portion in the SiC crystal structure body.

According to this crystal cutting method, the SiC crystal structure body is cleaved along the nearest neighbor direction intersecting direction in the first cleaving step. The SiC crystal structure body is cleaved along the nearest neighbor direction in the second cleaving step.

In the first cleaving step, the uncut SiC crystal structure body is cleaved and therefore stress to the SiC crystal structure body does not become discontinuous. Forming of a bulging portion in the first cleavage portion can thereby be suppressed. On the other hand, in the second cleaving step, stress to the SiC crystal structure body becomes discontinuous because the SiC crystal structure body has been cleaved in the nearest neighbor direction intersecting direction. However, in the second cleaving step, stress is applied to the SiC crystal structure body along the nearest neighbor direction and the SiC crystal structure body is cleaved along the nearest neighbor direction.

Forming of a bulging portion in the second cleavage portion can thereby be suppressed and flatness of the first cleavage portion and the second cleavage portion can thus be improved. A crystal cutting method that enables an SiC crystal structure body constituted of a hexagonal crystal to be cut appropriately from two different directions can thus be provided.

[B2] The crystal cutting method according to B1, further including a step of forming a first cleavage line oriented along the intersecting direction by heating a region of the SiC crystal structure body to be cleaved along the intersecting direction in advance of the first cleaving step, and a step of forming a second cleavage line oriented along the arrangement direction by heating a region of the SiC crystal structure body to be cleaved along the arrangement direction in advance of the second cleaving step, wherein the first cleaving step includes a step of cleaving the SiC crystal structure body with the first cleavage line as a starting point and the second cleaving step includes a step of cleaving the SiC crystal structure body with the second cleavage line as a starting point.

[B3] The crystal cutting method according to B2, wherein the step of forming the first cleavage line includes a step of forming a first modified layer in which a crystal structure is modified to a different property by heating in the SiC crystal structure body, and the step of forming the second cleavage line includes a step of forming a second modified layer in which a crystal structure is modified to a different property by heating in the SiC crystal structure body.

[B4] The crystal cutting method according to B3, wherein the SiC crystal structure body includes an SiC semiconductor substrate, the first modified layer is formed in an outer surface of the SiC semiconductor substrate in the step of forming the first cleavage line, and the second modified layer is formed in the outer surface of the SiC semiconductor substrate in the step of forming the second cleavage line.

[B5] The crystal cutting method according to B3, wherein the SiC crystal structure body includes an SiC laminated structure that includes an SiC semiconductor substrate and an SiC epitaxial layer, the first modified layer is formed in an outer surface of the SiC epitaxial layer in the step of forming the first cleavage line, and the second modified layer is formed in the outer surface of the SiC epitaxial layer in the step of forming the second cleavage line.

[B6] The crystal cutting method according to B5, wherein the first modified layer is formed to reach a boundary region between the SiC semiconductor substrate and the SiC epitaxial layer in the step of forming the first cleavage line and the second modified layer is formed to reach the boundary region between the SiC semiconductor substrate and the SiC epitaxial layer in the step of forming the second cleavage line.

[B7] The crystal cutting method according to any one of B2 to B6, wherein the first cleaving step includes a step of cleaving the SiC crystal structure body with the first cleavage line as the starting point by heating and cooling the first cleavage line and the second cleaving step includes a step of cleaving the SiC crystal structure body with the second cleavage line as the starting point by heating and cooling the second cleavage line.

[B8] The crystal cutting method according to any one of B1 to B7, wherein the SiC crystal structure body includes 2H—SiC, 4H—SiC, or 6H—SiC.

[B9] The crystal cutting method according to any one of B1 to B8, wherein the arrangement direction is a [11-20] direction, a [−12-10] direction, or a [−2110] direction of the hexagonal crystal.

[C1] A method for manufacturing an SiC semiconductor device including a step of preparing an SiC crystal structure body constituted of a hexagonal crystal having a silicon plane and a carbon plane as crystal planes, a step of setting, in the SiC crystal structure body, a device region of quadrilateral shape having an arrangement direction side oriented along an arrangement direction of nearest neighboring Si atoms in a plan view viewed from a normal direction of the silicon plane and an intersecting direction side oriented along an intersecting direction intersecting the arrangement direction, and forming a functional device in the device region, a first cleaving step of cleaving the SiC crystal structure body along the intersecting direction side of the device region and forming a first cleavage portion in the SiC crystal structure body, and a second cleaving step of cleaving the SiC crystal structure body along the arrangement direction side of the device region and forming a second cleavage portion crossing the first cleavage portion in the SiC crystal structure body.

According to this method for manufacturing the SiC semiconductor device, the SiC crystal structure body is cleaved along the nearest neighbor direction intersecting direction in the first cleaving step. The SiC crystal structure body is cleaved along the nearest neighbor direction in the second cleaving step.

In the first cleaving step, the SiC crystal structure body has not been cleaved and therefore stress to the SiC crystal structure body does not become discontinuous. Forming of a bulging portion in the first cleavage portion can thereby be suppressed. On the other hand, in the second cleaving step, stress to the SiC crystal structure body becomes discontinuous because the SiC crystal structure body has been cleaved in the nearest neighbor direction intersecting direction. However, in the second cleaving step, stress is applied to the SiC crystal structure body along the nearest neighbor direction and the SiC crystal structure body is cleaved along the nearest neighbor direction.

Forming of a bulging portion in the second cleavage portion can thereby be suppressed and flatness of the first cleavage portion and the second cleavage portion can thus be improved. A method for manufacturing an SiC semiconductor device that enables an SiC crystal structure body constituted of a hexagonal crystal to be cut appropriately from two different directions can thus be provided.

[C2] The method for manufacturing the SiC semiconductor device according to C1, wherein the step of forming the functional device includes a step of setting, in the SiC crystal structure body, a plurality of the device regions in a matrix array oriented along the arrangement direction and the intersecting direction and forming the functional devices respectively in the plurality of device regions, the first cleaving step includes a step of cleaving the SiC crystal structure body along the intersecting direction sides of the plurality of device regions, and the second cleaving step includes a step of cleaving the SiC crystal structure body along the arrangement direction sides of the plurality of device regions.

[C3] The method for manufacturing the SiC semiconductor device according to C1 or C2, further including a step of forming a first cleavage line oriented along the intersecting direction side of the device region by heating a region of the SiC crystal structure body oriented along the intersecting direction side of the device region in advance of the first cleaving step, and a step of forming a second cleavage line oriented along the arrangement direction side of the device region by heating a region of the SiC crystal structure body oriented along the arrangement direction side of the device region in advance of the second cleaving step, wherein the first cleaving step includes a step of cleaving the SiC crystal structure body with the first cleavage line as a starting point and the second cleaving step includes a step of cleaving the SiC crystal structure body with the second cleavage line as a starting point.

[C4] The method for manufacturing the SiC semiconductor device according to C3, wherein the step of forming the first cleavage line includes a step of forming, in the SiC crystal structure body, a first modified layer in which a crystal structure is modified to a different property by heating, and the step of forming the second cleavage line includes a step of forming, in the SiC crystal structure body, a second modified layer in which a crystal structure is modified to a different property by heating.

[C5] The method for manufacturing the SiC semiconductor device according to C4, wherein the SiC crystal structure body includes an SiC laminated structure that includes an SiC semiconductor substrate and an SiC epitaxial layer, the device region is set in an outer surface of the SiC epitaxial layer, the first modified layer is formed in the outer surface of the SiC epitaxial layer, and the second modified layer is formed in the outer surface of the SiC epitaxial layer.

[C6] The method for manufacturing the SiC semiconductor device according to C5, wherein the first modified layer is formed to reach a boundary region between the SiC semiconductor substrate and the SiC epitaxial layer, and the second modified layer is formed to reach the boundary region between the SiC semiconductor substrate and the SiC epitaxial layer.

[C7] The method for manufacturing the SiC semiconductor device according to any one of C3 to C6, wherein the first cleaving step includes a step of cleaving the SiC crystal structure body with the first cleavage line as the starting point by heating and cooling the first cleavage line and the second cleaving step includes a step of cleaving the SiC crystal structure body with the second cleavage line as the starting point by heating and cooling the second cleavage line.

[C8] The method for manufacturing the SiC semiconductor device according to any one of C1 to C7, wherein the SiC crystal structure body includes 2H—SiC, 4H—SiC, or 6H—SiC.

[C9] The method for manufacturing the SiC semiconductor device according to any one of C1 to C8, wherein the arrangement direction is a [11-20] direction, a [−12-10] direction, or a [−2110] direction of the hexagonal crystal.

[D1] An SiC semiconductor device including an SiC semiconductor layer that is constituted of a hexagonal crystal, having a silicon plane and a carbon plane as crystal planes, and includes a first main surface at one side, a second main surface at another side, a first side surface connecting the first main surface and the second main surface and extending along an arrangement direction of nearest neighboring Si atoms in a plan view viewed from a normal direction of the silicon plane, and a second side surface connecting the first main surface and the second main surface, extending along an intersecting direction intersecting the arrangement direction in the plan view and being not more than 20 μm in an in-plane variation along the arrangement direction.

[D2] The SiC semiconductor device according to D1, further including a first modified layer which is formed in a region of the first side surface at the first main surface side and in which a crystal structure is modified to a different property, and a second modified layer which is formed in a region of the second side surface at the first main surface side and in which a crystal structure is modified to a different property.

[D3] The SiC semiconductor device according to D2, wherein the first modified layer is exposed from the first main surface and the second modified layer is exposed from the first main surface.

[D4] The SiC semiconductor device according to D2, wherein the first modified layer is formed at an interval toward the second main surface side with respect to the first main surface and the second modified layer is formed at an interval toward the second main surface side with respect to the first main surface.

[D5] The SiC semiconductor device according to D2, wherein the SiC semiconductor layer has an SiC laminated structure that includes an SiC semiconductor substrate and an SiC epitaxial layer, the first main surface of the SiC semiconductor layer is formed by the SiC epitaxial layer, the second main surface of the SiC semiconductor layer is formed by the SiC semiconductor substrate, the first modified layer crosses a boundary region between the SiC semiconductor substrate and the SiC epitaxial layer, and the second modified layer crosses the boundary region between the SiC semiconductor substrate and the SiC epitaxial layer.

[D6] The SiC semiconductor device according to D1, further including a first modified layer which is formed in a region of the first side surface at the second main surface side and in which a crystal structure is modified to a different property, and a second modified layer which is formed in a region of the second side surface at the second main surface side and in which a crystal structure is modified to a different property.

[D7] The SiC semiconductor device according to D6, wherein the first modified layer is exposed from the second main surface and the second modified layer is exposed from the second main surface.

[D8] The SiC semiconductor device according to D6, wherein the first modified layer is formed at an interval toward the first main surface side with respect to the second main surface and the second modified layer is formed at an interval toward the first main surface side with respect to the second main surface.

[D9] The SiC semiconductor device according to any one of D6 to D8, wherein the SiC semiconductor layer has an SiC laminated structure that includes an SiC semiconductor substrate and an SiC epitaxial layer, the first main surface of the SiC semiconductor layer is formed by the SiC epitaxial layer, the second main surface of the SiC semiconductor layer is formed by the SiC semiconductor substrate, the first modified layer is formed in the SiC semiconductor substrate, and the second modified layer is formed in the SiC semiconductor substrate.

[D10] The SiC semiconductor device according to any one of D1 to D9, wherein the arrangement direction is a [11-20] direction, a [−12-10] direction, or a [−2110] direction of the hexagonal crystal.

[E1] An SiC processing method including a step of preparing an SiC processing object that includes SiC, a step of selectively heating an outer surface of the SiC processing object and forming a modified layer in which the SiC is modified to a different property in the outer surface of the SiC processing object, and a step of removing a portion or an entirety of the modified layer while letting the SiC processing object remain.

According to this SiC processing method, the outer surface of the SiC processing object of high hardness can be processed by the modified layer forming step and the modified layer removing step.

[E2] The SiC processing method according to E1, wherein the modified layer has a carbon density that differs along a thickness direction.

[E3] The SiC semiconductor device according to E1 or E2, wherein the modified layer has a silicon density that is higher than a carbon density.

[E4] The SiC processing method according to any one of E1 to E3, wherein the modified layer includes an Si modified layer, in which the SiC of the SiC processing object is modified to Si.

[E5] The SiC processing method according to any one of E1 to E4, wherein the SiC processing object is heated to a temperature at which a C atom is eliminated from the SiC.

[E5] The SiC processing method according to any one of E1 to E5, wherein the SiC processing object is heated to a temperature at which a C atom is sublimated from the SiC.

[E7] The SiC processing method according to any one of E1 to E6, wherein a portion or an entirety of the modified layer is removed by an etching method.

[E8] The SiC processing method according to any one of E1 to E7, wherein the SiC processing object includes an SiC semiconductor substrate and the modified layer is formed in an outer surface of the SiC semiconductor substrate.

[E9] The SiC processing method according to any one of E1 to E7, wherein the SiC processing object includes an SiC laminated structure that includes an SiC semiconductor substrate and an SiC epitaxial layer and the modified layer is formed in an outer surface of the SiC semiconductor layer.

[E10] The SiC processing method according to any one of E1 to E7, wherein the SiC processing object includes an SiC laminated structure that includes an SiC semiconductor substrate and an SiC epitaxial layer and the modified layer is formed in an outer surface of the SiC semiconductor substrate.

[E11] The SiC processing method according to any one of E1 to E10, further including a step of cleaving the SiC processing object with a removed portion of the modified layer as a starting point.

[E12] The SiC processing method according to any one of E1 to E11, wherein the SiC processing object includes an SiC monocrystal constituted of a hexagonal crystal.

[E13] A method for manufacturing an SiC semiconductor device that includes the SiC processing method according to any one of E1 to E12.

[F1] An SiC crystal cutting method including a step of preparing an SiC crystal structure body that includes 4H—SiC, a first cutting step of cutting the SiC crystal structure body along a [1-100] direction of the 4H—SiC and forming a first cut portion in the SiC crystal structure body, and a second cutting step of cutting the crystal structure body along a [11-20] direction of the 4H—SiC and forming a second cut portion crossing the first cut portion in the SiC crystal structure body.

According to this SiC crystal cutting method, the SiC crystal structure body is cut along the [1-100] direction which is a nearest neighbor direction intersecting direction, in the first cutting step. The SiC crystal structure body is cut along the [11-20] direction which is a nearest neighbor direction, in the second cutting step.

In the first cutting step, the uncut SiC crystal structure body is cut and therefore stress to the SiC crystal structure body does not become discontinuous. Forming of a bulging portion in the first cut portion can thereby be suppressed. On the other hand, in the second cutting step, stress to the SiC crystal structure body becomes discontinuous because the SiC crystal structure body has been cut in the nearest neighbor direction intersecting direction. However, in the second cutting step, stress is applied to the SiC crystal structure body along the nearest neighbor direction and the SiC crystal structure body is cut along the nearest neighbor direction.

Forming of a bulging portion in the second cut portion can thereby be suppressed and flatness of the first cut portion and the second cut portion can thus be improved. An SiC crystal cutting method that enables an SiC crystal structure body constituted of a hexagonal crystal to be cut appropriately from two different directions can thus be provided.

[F2] The SiC crystal cutting method according to F1, wherein the first cutting step includes a first cleaving step of cleaving the SiC crystal structure body along the [1-100] direction and the second cutting step includes a second cleaving step of cleaving the SiC crystal structure body along the [11-20] direction.

[F3] The SiC crystal cutting method according to F2, further including a step of forming oriented along the [1-100] direction by heating a region of the SiC crystal structure body to be cleaved along the [1-100] direction in advance of the first cleaving step, a first cleavage line, and a step of forming a second cleavage line oriented along the [11-20] direction by heating a region of the SiC crystal structure body to be cleaved along the [11-20] direction in advance of the second cleaving step, wherein the first cleaving step includes a step of cleaving the SiC crystal structure body along the [1-100] direction with the first cleavage line as a starting point and the second cleaving step includes a step of cleaving the SiC crystal structure body along the [11-20] direction with the second cleavage line as a starting point.

[F4] The SiC crystal cutting method according to F3, wherein the step of forming the first cleavage line includes a step of forming, in the SiC crystal structure body, a first modified layer in which a crystal structure is modified to a different property by heating, and the step of forming the second cleavage line includes a step of forming, in the SiC crystal structure body, a second modified layer in which a crystal structure is modified to a different property by heating.

[F5] The SiC crystal cutting method according to F4, wherein the SiC crystal structure body has an SiC semiconductor substrate that includes 4H—SiC, the first modified layer is formed in an outer surface of the SiC semiconductor substrate in the step of forming the first cleavage line, and the second modified layer is formed in the outer surface of the SiC semiconductor substrate in the step of forming the second cleavage line.

[F6] The SiC crystal cutting method according to F4, wherein the SiC crystal structure body has an SiC laminated structure that includes an SiC semiconductor substrate that includes 4H—SiC and an SiC epitaxial layer that includes 4H—SiC, the first modified layer is formed in an outer surface of the SiC epitaxial layer in the step of forming the first cleavage line, and the second modified layer is formed in the outer surface of the SiC epitaxial layer in the step of forming the second cleavage line.

[F7] The SiC crystal cutting method according to F6, wherein the first modified layer is formed to reach a boundary region between the SiC semiconductor substrate and the SiC epitaxial layer in the step of forming the first cleavage line, and the second modified layer is formed to reach the boundary region between the SiC semiconductor substrate and the SiC epitaxial layer in the step of forming the second cleavage line.

[F8] The SiC crystal cutting method according to any one of F3 to F7, wherein the first cleaving step includes a step of cleaving the SiC crystal structure body along the [1-100] direction with the first cleavage line as the starting point by heating and cooling the first cleavage line and the second cleaving step includes a step of cleaving the SiC crystal structure body along the [11-20] direction with the second cleavage line as the starting point by heating and cooling the second cleavage line.

[F9] The SiC crystal cutting method according to any one of F1 to F8, wherein the SiC crystal structure body is formed in a plate shape or discoid shape.

[G1] A method for manufacturing an SiC semiconductor device including a step of preparing an SiC crystal structure body constituted of a hexagonal crystal, a step of setting, in the SiC crystal structure body, a device region of quadrilateral shape having a [1-100] direction side oriented along a [1-100] direction of the SiC crystal structure body and an [11-20] direction side oriented along an [11-20] direction of the SiC crystal structure body, and forming a functional device in the device region, a first cutting step of cutting the SiC crystal structure body along the [1-100] direction side and forming a first cut portion oriented along the [1-100] direction, and a second cutting step of cutting the SiC crystal structure body along the [11-20] direction side and forming a second cut portion crossing the first cut portion and oriented along the [11-20] direction.

According to this method for manufacturing the SiC semiconductor device, forming of a bulging portion with a connection point connecting the first cut portion and the second portion as a starting point can be suppressed in the second cutting step. Flatness of the first cut portion and the second cut portion can thereby be improved. A method for manufacturing an SiC semiconductor device that enables a crystal structure body constituted of a hexagonal crystal to be cut appropriately from two different directions can thus be provided.

[G2] The method for manufacturing the SiC semiconductor device according to G1, wherein, the first cut portion with which an in-plane variation along the [11-20] direction is not more than 20 μm is formed in the first cutting step.

[G3] The method for manufacturing the SiC semiconductor device according to G1 or G2, wherein the step of forming the functional device includes a step of setting, in the SiC crystal structure body, a plurality of the device regions in a matrix array oriented along the [11-20] direction and the [1-100] direction and forming the functional devices respectively in the plurality of device regions, the first cutting step includes a step of cutting the SiC crystal structure body along the [1-100] direction sides of the plurality of device regions, and the second cutting step includes a step of cutting the SiC crystal structure body along the [11-20] direction sides of the plurality of device regions.

[G4] The method for manufacturing the SiC semiconductor device according to any one of G1 to G3, wherein the first cutting step includes a first cleaving step of cleaving the SiC crystal structure body along the [1-100] direction side and the second cutting step includes a second cleaving step of cleaving the SiC crystal structure body along the [11-20] direction side.

[G5] The method for manufacturing the SiC semiconductor device according to G4, further including a step of forming a first cleavage line oriented along the [1-100] direction side of the device region by heating a region of the SiC crystal structure body oriented along the [1-100] direction side of the device region in advance of the first cleaving step, and a step of forming oriented along the [11-20] direction side of the device region by heating a region of the SiC crystal structure body oriented along the [11-20] direction side of the device region in advance of the second cleaving step, a second cleavage line, wherein the first cleaving step includes a step of cleaving the SiC crystal structure body with the first cleavage line as a starting point and the second cleaving step includes a step of cleaving the SiC crystal structure body with the second cleavage line as a starting point.

[G6] The method for manufacturing the SiC semiconductor device according to G5, wherein the step of forming the first cleavage line includes a step of forming, in the SiC crystal structure body, a first modified layer in which a crystal structure is modified to a different property by heating, and the step of forming the second cleavage line includes a step of forming, in the SiC crystal structure body, a second modified layer in which a crystal structure is modified to a different property by heating.

[G7] The method for manufacturing the SiC semiconductor device according to G6, wherein the SiC crystal structure body includes an SiC laminated structure that includes an SiC semiconductor substrate and an SiC epitaxial layer, the device region is set in an outer surface of the SiC epitaxial layer, the first modified layer is formed in the outer surface of the SiC epitaxial layer, and the second modified layer is formed in the outer surface of the SiC epitaxial layer.

[G8] The method for manufacturing the SiC semiconductor device according to G7, wherein the first modified layer is formed to reach a boundary region between the SiC semiconductor substrate and the SiC epitaxial layer and the second modified layer is formed to reach the boundary region between the SiC semiconductor substrate and the SiC epitaxial layer.

[G9] The method for manufacturing the SiC semiconductor device according to any one of G5 to G8, wherein the first cleaving step includes a step of cleaving the SiC crystal structure body along the [1-100] direction with the first cleavage line as the starting point by heating and cooling the first cleavage line and the second cleaving step includes a step of cleaving the SiC crystal structure body along the [11-20] direction with the second cleavage line as the starting point by heating and cooling the second cleavage line.

[G10] The method for manufacturing the SiC semiconductor device according to any one of G1 to G9, wherein the SiC crystal structure body is formed in a plate shape or discoid shape.

[G11] The method for manufacturing the SiC semiconductor device according to any one of G1 to G10, wherein the SiC crystal structure body includes 2H—SiC, 4H—SiC, or 6H—SiC.

[H1] A semiconductor device including a semiconductor layer that is constituted of a hexagonal crystal and includes a first main surface at one side, a second main surface at another side, a first side surface connecting the first main surface and the second main surface and extending along a nearest neighbor direction of the hexagonal crystal and a second side surface connecting the first main surface and the second main surface, extending along an intersecting direction intersecting the nearest neighbor direction and being not more than 20 μm in an in-plane variation along the nearest neighbor direction.

[H2] The semiconductor device according to H1, further including a first modified layer which is formed in a region of the first side surface at the first main surface side and in which a crystal structure is modified to a different property, and a second modified layer which is formed in a region of the second side surface at the first main surface side and in which a crystal structure is modified to a different property.

[H3] The semiconductor device according to H2, wherein the first modified layer is exposed from the first main surface and the second modified layer is exposed from the first main surface.

[H4] The semiconductor device according to H3, wherein the first modified layer is formed at an interval toward the second main surface side with respect to the first main surface, and the second modified layer is formed at an interval toward the second main surface side with respect to the first main surface.

[H5] The semiconductor device according to H3, wherein the semiconductor layer has a laminated structure that includes a semiconductor substrate and an epitaxial layer, the first main surface of the semiconductor layer is formed by the epitaxial layer, the second main surface of the semiconductor layer is formed by the semiconductor substrate, the first modified layer crosses a boundary region between the semiconductor substrate and the epitaxial layer, and the second modified layer crosses the boundary region between the semiconductor substrate and the epitaxial layer.

[H6] The semiconductor device according to H1, further including a first modified layer which is formed in a region of the first side surface at the second main surface side and in which a crystal structure is modified to a different property, and a second modified layer which is formed in a region of the second side surface at the second main surface side and in which a crystal structure is modified to a different property.

[H7] The semiconductor device according to H6, wherein the first modified layer is exposed from the second main surface, and the second modified layer is exposed from the second main surface.

[H8] The semiconductor device according to H6, wherein the first modified layer is formed at an interval toward the first main surface side with respect to the second main surface, and the second modified layer is formed at an interval toward the first main surface side with respect to the second main surface.

[H9] The semiconductor device according to any one of H6 to H8, wherein the semiconductor layer has a laminated structure that includes a semiconductor substrate and an epitaxial layer, the first main surface of the semiconductor layer is formed by the epitaxial layer, the second main surface of the semiconductor layer is formed by the semiconductor substrate, the first modified layer is formed in the semiconductor substrate, and the second modified layer is formed in the semiconductor substrate.

[H10] The semiconductor device according to any one of H1 to H9, wherein the intersecting direction is a direction orthogonal to the nearest neighbor direction.

[H11] The semiconductor device according to any one of H1 to H10, wherein the nearest neighbor direction is a [11-20] direction, a [−12-10] direction, or a [−2110] direction of the hexagonal crystal.

[H12] The semiconductor device according to any one of H1 to H11, wherein the intersecting direction is a [01-10] direction, a [−1-100] direction, or a [−1010] direction of the hexagonal crystal.

[I1] An SiC semiconductor device including an SiC semiconductor layer that is constituted of a hexagonal crystal having a silicon plane and a carbon plane as crystal planes and includes a first main surface at one side, a second main surface at another side and a side surface connecting the first main surface and the second main surface and extending along an arrangement direction of nearest neighboring Si atoms in a plan view viewed from a normal direction of the silicon plane and an intersecting direction intersecting the arrangement direction, and a modified layer which is formed in the side surface of the SiC semiconductor layer and has a carbon density that differs along a thickness direction of the semiconductor layer and in which a crystal structure is modified to a different property.

[I2] The SiC semiconductor device according to I1, wherein the modified layer has a silicon density that is higher than the carbon density.

[I3] The SiC semiconductor device according to I1 or I2, wherein the modified layer includes an Si modified layer in which SiC of the SiC semiconductor layer is modified to Si.

[I4] The SiC semiconductor device according to any one of I1 or I3, wherein the modified layer includes an Si amorphous layer.

[I5] The SiC semiconductor device according to any one of I1 or I4, wherein the modified layer is formed in a region of the side surface at the first main surface side.

[I6] The SiC semiconductor device according to any one of I1 or I5, wherein the modified layer is exposed from the first main surface.

[I7] The SiC semiconductor device according to any one of I1 to I5, wherein the modified layer is formed at an interval toward the second main surface side with respect to the first main surface.

[I8] The SiC semiconductor device according to any one of I1 to I7, wherein the SiC semiconductor layer has an SiC laminated structure that includes an SiC semiconductor substrate and an SiC epitaxial layer, the first main surface of the SiC semiconductor layer is formed by the SiC epitaxial layer, the second main surface of the SiC semiconductor layer is formed by the SiC semiconductor substrate, and the modified layer crosses a boundary region between the SiC semiconductor substrate and the SiC epitaxial layer.

[I9] The SiC semiconductor device according to any one of I1 to I4, wherein the modified layer is formed in a region of the side surface at the second main surface side.

[I10] The SiC semiconductor device according to I9, wherein the modified layer is exposed from the second main surface.

[I11] The SiC semiconductor device according to I9, wherein the modified layer is formed at an interval toward the first main surface side with respect to the second main surface.

[I12] The SiC semiconductor device according to any one of I9 to I11, wherein the SiC semiconductor layer has an SiC laminated structure that includes an SiC semiconductor substrate and an SiC epitaxial layer, the first main surface of the SiC semiconductor layer is formed by the SiC epitaxial layer, the second main surface of the SiC semiconductor layer is formed by the SiC semiconductor substrate, and the modified layer is formed in the SiC semiconductor substrate.

[I13] The SiC semiconductor device according to any one of I1 to I12, wherein the intersecting direction is a direction orthogonal to the nearest neighbor direction.

[I14] The SiC semiconductor device according to any one of I1 to I13, wherein the arrangement direction is a [11-20] direction, a [−12-10] direction, or a [−2110] direction of the hexagonal crystal.

[I15] The SiC semiconductor device according to any one of I1 to I14, wherein the intersecting direction is a [01-10] direction, a [−1-100] direction, or a [−1010] direction of the hexagonal crystal.

[I16] The SiC semiconductor device according to any one of I1 to I15, wherein an in-plane variation along the arrangement direction of a plane extending along the intersecting direction in the side surface of the SiC semiconductor layer is not more than 20 μm.

The present application corresponds to Japanese Patent Application No. 2018-086472 filed on Apr. 27, 2018 in the Japan Patent Office, and the entire disclosure of this application is incorporated herein by reference.

While preferred embodiments of the present invention have been described in detail, these are merely specific examples used to clarify the technical contents of the present invention and the present invention should not be interpreted as being limited to these specific examples and the scope of the present invention is to be limited only by the appended claims.

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