SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

A semiconductor package includes a first tier and a second tier underlying the first tier and including TIVs and third dies. The first tier includes a first redistribution structure and first and second dies disposed side-by-side and separated by a first insulating encapsulation. A surface of the first insulating encapsulation, surfaces of first die connectors of the first die, and truncated spherical surfaces of second die connectors of the second die are level. The first redistribution structure underlies the surfaces of the first insulating encapsulation and the first die connectors and the truncated spherical surfaces of the second die connectors. The third dies disposed below the first redistribution structure are electrically coupled to the first die through the first redistribution structure and laterally covered by a second insulating encapsulation. The TIVs penetrate through the second insulating encapsulation and are electrically coupled to the second die through the first redistribution structure.

BACKGROUND

The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more of the smaller components to be integrated into a given area. These smaller electronic components also require smaller packages that utilize less area than previous packages. Some smaller types of packages for semiconductor components include quad flat packages (QFP), pin grid array (PGA) packages, ball grid array (BGA) packages, flip chips (FC), three-dimensional integrated circuits (3DICs), wafer level packages (WLPs), package-on-package (PoP) structures, and integrated fan-out (InFO) packages, etc. Although existing semiconductor packages have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.

DETAILED DESCRIPTION

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. In addition, terms, such as “first”, “second”, “third”, “fourth” and the like, may be used herein for ease of description to describe similar or different element(s) or feature(s) as illustrated in the figures, and may be used interchangeably depending on the order of the presence or the contexts of the description.

FIGS.1A-1Fare schematic cross-sectional views illustrating various stages of a manufacturing method of a semiconductor package having a back-to-face configuration, andFIG.1Gis a schematic top view illustrating a configuration of various dies and electrical devices in the semiconductor package ofFIG.1F, in accordance with some embodiments.

Referring toFIG.1A, a first die110and a second die120may be disposed side by side on a temporary carrier51. The temporary carrier51may be made of a material such as silicon, polymer, polymer composite, metal foil, ceramic, glass, glass epoxy, tape, or other suitable material for structural support. In some embodiments, an adhesive layer (not shown) is formed on the temporary carrier51before the placement of the first die110and the second die120. The adhesive layer may be detached from the temporary carrier51by, e.g., shining an ultra-violet (UV) light on the temporary carrier51in a subsequent carrier de-bonding process. For example, the adhesive layer is a light-to-heat-conversion (LTHC) coating layer or the like. In some embodiments, a back surface110bof the first die110and/or a back surface120bof the second die120may be attached to the temporary carrier51through a connecting film DF1(e.g., die attach films or the like). In some embodiments, the connecting film DF1includes a dielectric material having high thermal conductivity. Alternatively, the connecting film(s) DF1may be omitted.

In some embodiments, the first die110and the second die120are of different types of semiconductor dies. The first die110and/or the second die120may be or include a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system-on-a-chip (SoC), an application processor (AP), and a microcontroller); a power management die; a wireless and radio frequency (RF) die; a baseband (BB) die; a sensor die; a micro-electro-mechanical-system (MEMS) die; a signal processing die; a front-end die (e.g., an analog front-end (AFE) die); an application-specific integrated circuit (ASIC) die; a combination thereof; or the like. In alternative embodiments, the first die110and/or the second die120may be or include a memory die (e.g., a dynamic random-access memory (DRAM) die, a static random-access memory (SRAM) die, a resistive random-access memory (RRAM), a magneto-resistive random-access memory (MRAM), a NAND flash memory, a hybrid memory cube (HMC) module, a high bandwidth memory (HBM) module); a combination thereof; or the like. In alternative embodiments, the first die110and/or the second die120may be or include an artificial intelligence (AI) engine; a computing system (e.g., an AI server, a high-performance computing (HPC) system, a high-power computing device, a cloud computing system, a networking system, an edge computing system, a SoIC system, etc.); a combination thereof; or the like.

The first die110and/or the second die120may be cut from a semiconductor wafer (not shown). In some embodiments, the first die110includes a first semiconductor substrate111, a first device layer112formed in/on the first semiconductor substrate111, first die connectors113formed over the first device layer112, and a first protection layer114formed over the first device layer112and covering the first die connectors113. The first semiconductor substrate111may include an elementary semiconductor (e.g., silicon or germanium in a crystalline, a polycrystalline, or an amorphous structure, etc.), a compound semiconductor (e.g., SiC, GaAs, GaP, InP, InAs, and/or InSb, etc.), an alloy semiconductor (e.g., SiGe, GaAsP, AlinAs, AlGaAs, GalnAs, GaInP, etc.), combinations thereof, or other suitable materials. In some embodiments, the first semiconductor substrate111may be a compound semiconductor substrate having a multilayer structure or any suitable substrate. In some embodiments, semiconductor devices are formed in the first device layer112, and may include active devices (e.g., transistors, diodes, etc.) and/or passive devices (e.g., capacitors, resistors, inductors, etc.), or other suitable electrical devices.

In some embodiments, an interconnect structure116including interconnect conductive layers and interconnect dielectric layers are formed between the first device layer112and the first die connectors113to be electrically coupled to the semiconductor devices in the first device layer112and the first die connectors113. The first die connectors113may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the first die connectors113include metal pillars (e.g., a copper pillar) formed by a sputtering, printing, plating, CVD, or the like, with or without a solder cap thereon. The first and second die connectors113and121may be of different materials. In some embodiments, the protection layer114is formed of a polymer, such as polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), and/or other suitable dielectric material(s). At this stage, the first die connectors113may be buried in the protection layer114.

In some embodiments, the second die120may include one or more semiconductor devices, semiconductor dies, bonding wires, conductive pads, an insulating encapsulation, etc., depending on design requirements. For example, the second die120includes second die connectors121′. Examples of the second die connectors121′ may include solder balls, micro-bumps, metal pillars, electroless nickel-electroless palladium-immersion gold (ENEPIG) formed bumps, controlled collapse chip connection (C4) bumps, ball grid array (BGA) bumps, or the like. In some embodiments, the respective second die connector121′ includes a via portion1211, a pillar portion1212overlying the via portion1211, and a cap portion1213′ overlying the pillar portion1212, where the via and pillar portions1211and1212are of the same material (e.g., copper), and the pillar and cap portions1212and1213′ are of different materials. The pillar portion1212may be formed on the top surface of the passivation layer1221, and the via portion1211may penetrate through the passivation layer1221to be in physical and electrical contact with the corresponding contact pad1222. The cap portion1213′ may include solder material and may be a rounded ball with a truncated end landing on the pillar portion1212(e.g., copper pillar).

Referring toFIG.1Band with reference toFIG.1A, a first insulating encapsulation130may be formed over the temporary carrier51to laterally cover the first and second dies110and120and the connecting film DF1. For example, the first insulating encapsulation130extends along the sidewalls110sand120sof the first and second dies110and120. The first insulating encapsulation130may extend to surround the spacing between adjacent second die connectors121. In some embodiments, the first insulating encapsulation130is a molding compound formed by a molding process. For example, the first insulating encapsulation130includes polymers (e.g., epoxy resins, phenolic resins, silicon-containing resins, or other suitable resins), dielectric materials, or other suitable materials. In some embodiments, the first insulating encapsulation130is made of a molding underfill material. In some embodiments, the first insulating encapsulation130includes inorganic fillers which can be added to optimize coefficient of thermal expansion (CTE) of the first insulating encapsulation130. The disclosure is not limited thereto.

In some embodiments, a layer of insulating encapsulation material is formed over the temporary carrier51to encapsulate the first and second dies110and120, and then a planarization process (e.g., chemical mechanical polishing (CMP), mechanical grinding, etching, a combination thereof, etc.) is performed on the insulating encapsulation material until the first die connectors113and the second die connectors121are accessibly exposed. In some embodiments, during the planarization process, an upper portion of the protection layer114of the first die110that covers the top surfaces of the first die connectors113is removed. In some embodiments, during the planarization process, the top of the cap portion1213′ of the respective second die connector121′ is partially removed to impart a truncated spherical shape to the cap portion1213of the respective second die connector121. As shown inFIG.1B, the respective second die connector121may be a rounded ball with two truncated ends. For example, the top surface130aof the first insulating encapsulation130is substantially leveled (or coplanar) with the active surface110aof the first die110and the active surface120aof the second die120, where the active surface110aincludes the exposed surfaces of the first die connectors113, and the active surface120includes the exposed surfaces of the second die connectors121.

Referring toFIG.1Cand with reference toFIG.1B, a first redistribution structure140may be formed on the active surface110aof the first die110, the active surface120aof the second die120, and the top surface130aof the first insulating encapsulation130. The first redistribution structure140may include one or more first patterned conductive layer(s)141formed in one or more first dielectric layer(s)142. In some embodiments, the first dielectric layer142includes a polymer, such as PBO, polyimide, BCB, or the like; a nitride such as silicon nitride; an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), and/or the like. In some embodiments, the first patterned conductive layer141includes conductive lines, conductive vias, and conductive pads, etc., and may be formed of any suitable conductive material(s) such as copper, titanium, tungsten, aluminum, alloys, or the like.

In some embodiments, the bottommost sublayer of the first dielectric layer142is formed and patterned over the first and second dies110and120and the first insulating encapsulation130by using lithography and etching or other suitable processes, and then the bottommost sublayer1413of the first patterned conductive layer141is formed on the top surface of the bottommost sublayer of the first dielectric layer142and in openings of the bottommost sublayer of the first dielectric layer142to be physically and electrically coupled to the first and second die connectors114and121. For example, the conductive vias in the bottommost sublayer1413of the first patterned conductive layer141are tapered toward the corresponding first and second die connectors114and121, where the conductive vias may directly land on the upper truncated end of the cap portion1213.

The topmost sublayer of the first patterned conductive layer141may include first conductive pads1411and second conductive pads1412surrounding the first conductive pads1411, where the first and second conductive pads1411and1412are accessibly exposed from the topmost sublayer of the first dielectric layer142for further electrical connection. The first conductive pads1411may be distributed right over the first die110and/or the second die120. The pitch of the adjacent first conductive pads1411may be less than that of the adjacent second conductive pads1412. The density per unit area of the first conductive pads1411may be denser than that of the second conductive pads1412.

In some embodiments, the steps of forming a sublayer of the first dielectric layer142and forming a sublayer of the first patterned conductive layer141are repeated to form a multi-layered redistribution structure. It is noted that the number of sublayers of the first dielectric layer142and the first patterned conductive layer141in the first redistribution structure140may construe no limitation in the disclosure. Other methods of forming the first redistribution structure140are possible and fully intended to be included within the scope of the disclosure.

With continued reference toFIG.1C, conductive pillars150may be formed on the second conductive pads1412of the first patterned conductive layer141of the first redistribution structure140. The conductive pillars150may be formed by: forming a seed layer; forming a patterned photoresist over the seed layer, where each of the openings in the patterned photoresist corresponds to a location of the respective conductive pillar150to be formed; filling the openings with an electrically conductive material such as copper using, e.g., plating or the like; removing the patterned photoresist using, e.g., an ashing or a stripping process; and removing portions of the seed layer on which the conductive pillars150are not formed. Other methods for forming the conductive pillars150are possible and fully intended to be included within the scope of the disclosure.

Referring toFIG.1D, at least one third dies (e.g.,160_1and160_2) may be mounted on the first conductive pads1411of the first patterned conductive layer141of the first redistribution structure140. In some embodiments, the third dies (160_1and160_2) are of different sizes. For example, the lateral dimension of the third die160_1disposed right over the first die110is less than the lateral dimension of the third die160_2disposed over the first die110, the second die120, and a portion of the first insulating encapsulation130therebetween. Alternatively, the third dies (160_1and160_2) are of the same size. In some embodiments, the thickness of the third dies (160_1and160_2) is less than the thickness of the first die110and/or the second die120. By way of example and not limitation, the thickness110H of the first die110is about 660 μm, while the thickness160H of the third dies (160_1and/or160_2) is about 30 μm. Although other value(s) are fully intended to be included within the scope of the disclosure.

The respective third die (160_1and/or160_2) may include a third semiconductor substrate161having a front surface161aand a back surface161bopposite to each other, a third device layer162formed in/on the front surface161aof the third semiconductor substrate161, through substrate vias (TSVs)163penetrating through the third semiconductor substrate161and electrically coupled to the third device layer162, front-side connectors164disposed over and electrically coupled to the third device layer162, an isolation layer165disposed on the back surface161bof the third semiconductor substrate161and laterally covering the TSVs163, and third die connectors166underlying the isolation layer165and coupled to the TSVs163. The material of the third semiconductor substrate161may be similar to that of the first semiconductor substrate111. Semiconductor devices (e.g., transistors, diodes, capacitors, resistors, inductors, etc.) may be included in the third device layer162. The conductive vias163, the front-side connectors164, and the third die connectors166may include one or more conductive materials (e.g., cobalt, titanium, tungsten, copper, aluminum, tantalum, titanium nitride, tantalum nitride, gold, silver, another metal, a metal alloy, or combinations thereof). The isolation layer165may be made of polyimide or other suitable insulating material(s).

In some embodiments, the respective third die (160_1and/or160_2) may include an interconnect structure168including interconnect conductive layers and interconnect dielectric layers interposed between the third device layer162and the front-side connectors164, where the interconnect conductive layers are electrically coupled to the third device layer162, the front-side connectors164, and the TSVs163. Conductive joints167, such as solder joints, may be formed between the third die connectors166and the underlying first conductive pads1411for coupling the third dies (160_1and160_2) to the first redistribution structure140.

With continued reference toFIG.1D, at least one first electrical device170_1, such as an integrated passive device (IPD), may be mounted on the first conductive pads1411of the first redistribution structure140. Conductive joints172, such as solder joints, may be formed between device connectors171of the first electrical device170_1and the underlying first conductive pads1411. The first electrical device170_1may be electrically coupled to the first die110through the first patterned conductive layer141of the first redistribution structure140. In some embodiments, the first electrical device170_1is disposed right over the first die110and laterally interposed between the third dies (160_1and160_2). In some embodiments, an underfill layer UF1is formed in gaps between the third dies160_1and160_2and the underlying first conductive pads1411and also between the first electrical device170_1and the underlying first conductive pads1411to surround the conductive joints167and172for protection. The underfill layer UF1may also be formed in a gap among the first electrical device170_1and the third dies (160_1and160_2). The underfill layer UF1may partially (or fully) cover the sidewalls of the third dies (160_1and160_2) and/or the sidewall of the first electrical device170_1. Alternatively, the underfill layer UF1is omitted.

Still referring toFIG.1D, a second insulating encapsulation180may be formed on the first redistribution structure140to laterally cover the conductive pillars150, the third dies (160_1and160_2), the first electrical device170_1, and the underfill layer UF1. The material and the forming method of the second insulating encapsulation180may be similar to the first insulating encapsulation130. In some embodiments, the thickness of the second insulating encapsulation180is less than that of the first insulating encapsulation130. In embodiments where the underfill layer UF1is omitted, the second insulating encapsulation180, e.g., molding underfill, is formed in the gaps among the third dies (160_1and160_2), the first electrical device170_1, and the underlying first conductive pads1411. In some embodiments, the first electrical device170_1is surrounded by the underfill layer UF1, and the second insulating encapsulation180is separated from the first electrical device170_1through the underfill layer UF1. In some embodiments, all of the sidewalls of the first electrical device170_1and the third dies (160_1and160_2) are covered by the underfill layer UF1, and the second insulating encapsulation180is separated from the first electrical device170_1and the third dies (160_1and160_2) by the underfill layer UF1.

The conductive pillars150that penetrate through the second insulating encapsulation180may be referred to as through insulation vias (TIVs)150. In some embodiments, after the planarization process (e.g., CMP, mechanical grinding, etching, a combination thereof, etc.) is performed, the top surface180aof the second insulating encapsulation180is substantially leveled (or coplanar) with the top surfaces150aof the TIVs150, the front surfaces160aof the third dies (160_1and160_2), and a back surface170aof the first electrical device170_1, where the respective front surface160amay include the exposed surfaces of the front-side connectors164for further electrical connection. In some embodiments, the active surface110aof the first die110faces the back surfaces160bof the third dies (160_1and160_2), and such configuration may be viewed as a back-to-face configuration.

Referring toFIG.1Eand with reference toFIG.1D, a second redistribution structure190may be formed on the second insulating encapsulation180, the TIVs150, the third dies (160_1and160_2), and the first electrical device170_1. The second redistribution structure190may include one or more second patterned conductive layer(s)191formed in one or more second dielectric layer(s)192. The materials and the forming methods of the second patterned conductive layer191and the second dielectric layer192may be similar to those of the first patterned conductive layer141and the first dielectric layer142, respectively. For example, the bottommost sublayer of the second patterned conductive layer191may be in physical and electrical contact with the top surfaces150aof the TIVs150and the exposed surfaces of the front-side connectors164at the front surfaces160aof the third dies (160_1and160_2). In some embodiments, the topmost sublayer of the second patterned conductive layer191may be or include under bump metallization (UBM) pads for further electrical connection.

In some embodiments, conductive terminals195are formed on the UBM pads of the topmost sublayer of the second patterned conductive layer191. The conductive terminals195may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. The conductive terminals195may be solder balls, metal pillars, a ball grid array (BGA), controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium-immersion gold (ENEPIG) technique formed bumps, combination thereof (e.g., a metal pillar having a solder ball attached thereof), or the like. In some embodiments, the conductive terminals195include an eutectic material and may include a solder bump, a solder ball, or the like. A reflow process may be performed, giving the conductive terminals195a shape of a partial sphere. Alternatively, the conductive terminals195may include non-spherical connectors or have other shape(s).

In some embodiments, at least one second electrical device170_2may be mounted on the UBM pads of the second patterned conductive layer191of the second redistribution structure190through conductive joints (not labeled). The second electrical device170_2may be surrounded by the conductive terminals195. In some embodiments, the electrical device170_2is electrically coupled to the third dies (160_1and/or160_2) through the second patterned conductive layer191of the second redistribution structure190. In some embodiments, the electrical device170_2is electrically coupled to the first die110through the second redistribution structure190, the TIVs150, and the first redistribution structure140. For example, the first and second electrical devices (170_1and170_2) are IPDs. The second electrical device170_2may be electrically coupled to one or more die(s) underlying the second redistribution structure190, depending on the product requirements.

Referring toFIG.1Fand with reference toFIG.1E, the temporary carrier51may be removed by a suitable process, such as etching, grinding, mechanical peeling-off, etc., to accessibly reveal the connecting film DF1(if any) and the back surfaces (120band130b) of the second die120and the first insulating encapsulation130. In an embodiment where an adhesive layer (e.g., a LTHC film) is formed on the temporary carrier51, the temporary carrier51is de-bonded by exposing to a laser or UV light. The laser or UV light breaks the chemical bonds of the adhesive layer that binds to the temporary carrier51, and the temporary carrier51may then be de-bonded. Residues of the adhesive layer, if any, may be removed by a cleaning process performed after the carrier de-bonding process.

In some embodiments, the previous processes are performed at wafer level, and a singulation process may be performed to cut through the first insulating encapsulation130, the first redistribution structure140, the second insulating encapsulation180, and the second redistribution structure190, so as to form a respective semiconductor package10A. In some embodiments, the semiconductor package10A has a coterminous sidewall10sincluding the sidewalls of the first insulating encapsulation130, the first dielectric layer142of the first redistribution structure140, the second insulating encapsulation180, and the second dielectric layer192of the second redistribution structure190.

As shown inFIG.1F, the semiconductor package10A may include a first tier T1_1stacked on a second tier T2_1, where the first tier T1_1includes the first and second dies (110and120), the first insulating encapsulation130, and the first redistribution structure140, and the second tier T2_1includes the third dies (160_1and160_2), the first and second electrical devices (170_1and170_2), the TIVs150, the second insulating encapsulation180, the second redistribution structure190, and the conductive terminals195. In some embodiments, the second die120, such as a memory package component, is disposed in proximity to the first die110(e.g., the SoC die) at the same tier in order to reduce the overall thickness of the semiconductor package10A, as compared to a package structure having the memory package component stacked over the SoC die. In some embodiments, the first die110of the semiconductor package10A has better thermal-dissipating performance due to the connecting film DF1disposed on the back surface110band having high thermal conductivity. In some embodiments, the first electrical device170_1, such as an IPD die, is integrated into the second tier T2_1to reduce the electrical path between the first die110and the electrical device170_1, thereby improving power delivery and electrical performance.

Referring toFIG.1Gand with reference toFIG.1F, in the top view, a plurality of first electrical devices170_1may be arranged in a column between the third dies (160_1and160_2). It should be noted that the number and the arrangement of the first electrical devices170_1are merely an example and construe no limitation in the disclosure. In some embodiments, an orthographic projection area of the column of the first electrical devices170_1is fully within an orthographic projection area of the first die110. In some embodiments, an orthographic projection area of the third die (160_1and/or160_2) at least partially overlaps the orthographic projection area of the first die110. The third dies (160_1and160_2) may have the same orthographic projection area or may have different orthographic projection areas. The boundary of the third die (160_1and/or160_2) may extend beyond the boundary of the first die110, in the top view. In some embodiments, the orthographic projection area of the third die160_2partially (or fully) overlaps an orthographic projection area of the second die120. The orthographic projection area of the first die110may be less than the orthographic projection area of the second die120. It should be noted that the configuration shown inFIG.1Gis merely an example, and the number and the arrangement of these dies and electrical devices can be adjusted depending on product requirements.

FIGS.2A-2Eare schematic cross-sectional views illustrating various stages of a manufacturing method of a semiconductor package having a back-to-face configuration,FIG.2Fis a schematic top view illustrating a configuration of various dies and electrical devices in the semiconductor package ofFIG.2E, in accordance with some embodiments. Unless specified otherwise, the materials and the formation methods of the components in these embodiments are essentially the same as the like components, which are denoted by like reference numerals in the embodiments.

Referring toFIG.2A, a backside redistribution structure210may be formed on the temporary carrier51. The backside redistribution structure210may include one or more backside patterned conductive layer(s)211formed in one or more backside dielectric layer(s)212. The materials and the forming methods of the backside patterned conductive layer211and the backside dielectric layer212may be similar to those of the first patterned conductive layer141and the first dielectric layer142, respectively. In some embodiments, first TIVs252may be formed on the backside redistribution structure210and electrically coupled to the backside patterned conductive layer211. The first TIVs252may be similar to the TIVs150described inFIG.1D.

In some embodiments, the first die110is attached to the backside dielectric layer212of the backside redistribution structure210through the connecting film DF1. The connecting film DF1, such as a die attach film or the like, may be attached to the back surface110bof the first die110. In some embodiments, the first insulating encapsulation130is formed on the backside redistribution structure210to laterally cover the first TIVs252, the first die110, and the connecting film DF1. The first die110and the first insulating encapsulation130may be similar to the first die110and the first insulating encapsulation130described inFIGS.1A-1B. The first die connectors114of the first die110and the first TIVs130may be accessibly revealed for further electrical connection. In some embodiments, the top surface130aof the first insulating encapsulation130is substantially leveled with the top surfaces252aof the first TIVs252, and the active surface110aof the first die110.

Referring toFIG.2Band with reference toFIG.2A, a middle redistribution structure220may be formed on the first insulating encapsulation130, the first TIVs252, and the first die110. The middle redistribution structure220may include one or more middle patterned conductive layer(s)221formed in one or more middle dielectric layer(s)222. The materials and the forming methods of the middle patterned conductive layer211and the middle dielectric layer212may be similar to those of the backside patterned conductive layer211and the backside dielectric layer222, respectively. The middle patterned conductive layer221may be physically and electrically coupled to the top surfaces252aof the first TIVs252, and the first die connectors114of the first die110. In some embodiments, the middle patterned conductive layer211includes conductive vias and conductive pads overlying the conductive vias and is free of conductive lines. The pitch P1of the adjacent conductive pads of the middle patterned conductive layer211may be substantially the same as the pitch of the adjacent first and third die connectors. By way of example and not limitation, the pitch P1is about 25 μm. Alternatively, the middle redistribution structure220is a multi-layered redistribution structure having multiple layers of routing, depending on the circuit design.

In some embodiments, second TIVs254are formed on the middle redistribution structure220and electrically coupled to the middle patterned conductive layer221. The second TIVs254may be similar to the TIVs150described in the preceding paragraphs. In some embodiments, a third die160is mounted on the middle redistribution structure220and electrically coupled to the middle patterned conductive layer221through the conductive joints167. The third die160may be similar to the third dies (160_1and160_2) described inFIG.1D. In some embodiments, the TSVs163of the third die160has a critical dimension less than the pitch P1. For example, the critical dimension of the respective TSV163is in a range of about 2 μm to about 6 μm. The pitch P2of the adjacent TSVs163may be less than the pitch P1. For example, the pitch P2is in a range of about 9 μm to about 24 μm. The back surface160bof the third die160faces the active surface of the first die110, and such configuration may be referred to as the back-to-face configuration.

The first underfill layer UF1is optionally formed in a gap between the back surface160bof the third die160and the middle redistribution structure220to surround the conductive joints167, the third die connectors166, and the corresponding conductive pads of the middle patterned conductive layer221. In some embodiments, the second insulating encapsulation180is formed on the middle redistribution structure220to laterally cover the second TIVs254, the third die160, and the first underfill layer UF1. The second insulating encapsulation180may be similar to the second insulating encapsulation180described inFIG.1D. For example, the top surface180aof the second insulating encapsulation180is substantially leveled (or coplanar) with the top surfaces254aof the second TIVs254and the front surface160aof the third die160, where the front surface160aincludes exposed surfaces of the front-side connectors164for further electrical connection.

Referring toFIG.2Cwith reference toFIG.2B, a front-side redistribution structure230may be formed on the second insulating encapsulation180, the second TIVs254, and the third die160. The front-side redistribution structure230may include one or more front-side patterned conductive layer(s)231formed in one or more front-side dielectric layer(s)232. The materials and the forming methods of the front-side patterned conductive layer231and the front-side dielectric layer232may be respectively similar to those of the second patterned conductive layer191and the second dielectric layer192described inFIG.1E. For example, the bottommost sublayer of the front-side patterned conductive layer231is in physical and electrical contact with the top surfaces254aof the second TIVs254and the exposed surfaces of the front-side connectors164of the third die160. The topmost sublayer of the front-side patterned conductive layer231may include UBM pads for further electrical connection. Subsequently, the conductive terminals195may be formed on a portion of the UBM pads of the front-side patterned conductive layer231. In some embodiments, at least one electrical device170, such as the IPD, is mounted on the other portion of the UBM pads of the front-side patterned conductive layer231and surrounded by the conductive terminals195. The conductive terminals195and the electrical device170may be similar to the conductive terminals195and the second electrical device170_2described inFIG.1E.

Referring toFIG.2Dand with reference toFIG.2C, the structure ofFIG.2Cmay be flipped upside-down, and the conductive terminals195and/or the electrical device170may be disposed on a frame52. The temporary carrier51may be removed to accessibly reveal the backside redistribution structure210by a method similar to the descriptions related toFIG.1F, and thus the detailed descriptions are not repeated. In some embodiments, a patterned dielectric layer213may be formed on the outermost sublayer of the backside dielectric layer212. The patterned dielectric layer213may be or include organic dielectric material, such as a solder resist film, an Ajinomoto Buildup Film (ABF), or the like. In some embodiments, the patterned dielectric layer213is referred to as a patterned resist layer. The patterned dielectric layer213may include openings2130, and at least a portion of the outermost sublayer of the backside patterned conductive layer211may be accessibly revealed by the openings2130for further electrical connection.

Referring toFIG.2Eand with reference toFIG.2D, the second die120, such as the memory package component, may be mounted on the backside redistribution structure210through conductive joints1211, e.g., solder joints. The second die120may be similar to the second die120described inFIG.1A. For example, the second die connectors of the second die120are disposed on the portions of backside patterned conductive layer211exposed by the openings2130, and then a reflow process is performed to form the conductive joints1211coupling the second die120to the backside patterned conductive layer211. In some embodiments, an underfill layer (not shown) is formed in a gap between the second die120and the patterned dielectric layer213to surround the conductive joints1211. In some embodiments, the aforementioned processes are performed at wafer level, and a singulation process is performed to cut through the patterned dielectric layer213, the backside redistribution structure210, the first insulating encapsulation130, the middle redistribution structure220, the second insulating encapsulation180, and the front-side redistribution structure230, so as to form a respective semiconductor package10B.

With continued reference toFIG.2Eand also referring toFIG.1F, the semiconductor package10B is similar to the semiconductor package10A, and thus the detailed descriptions are not repeated. For example, the semiconductor package10B may include a first tier T1_2stacked on a second tier T2_2, and a third tier T3stacked on the first tier T1_2, where the first tier T1_2is free of the second die120, the second die120is included at the third tier T3. The second tier T2_2may (or may not) be free of the electrical device170_1. The first die110at the first tier T1_2and the second die160at the second tier T2_2may be arranged in the back-to-face configuration. The first tier T1_2may include the backside redistribution structure210and the middle redistribution structure220respectively disposed at the backside and the front-side of the first die110, and the middle redistribution structure220and the front-side redistribution structure230respectively disposed at the backside and the front-side of the third die160.

Referring toFIG.2Fand with continued reference toFIG.2E, the lateral dimension of the first die110may be less than that of the third die160. For example, in the top view, the orthographic projection area of the first die110is fully located within the orthographic projection area of the third die160. The lateral dimension of the third die160may be less than that of the second die120. For example, in the top view, the orthographic projection area of the third die160is fully located within the orthographic projection area of the second die120. The boundary of the orthographic projection area of the second die120may (or may not) be coincided with the sidewalls (or boundary)10sof the semiconductor package10B. In some embodiments where the first die110is replaced with a larger first die110′, the lateral dimension of the first die110′ is greater than that of the third die160, and the orthographic projection area of the first die110′ as indicated in the dashed lines encircles the orthographic projection area of the third die160. It should be noted that the configuration shown inFIG.2Fis merely an example, and the number and the sizes of the first, second, and third dies can be adjusted depending on product requirements, thereby increasing the design flexibility.

FIGS.3A-3Eare schematic cross-sectional views illustrating various stages of a manufacturing method of a semiconductor package having a face-to-face configuration, in accordance with some embodiments. Unless specified otherwise, the materials and the formation methods of the components in these embodiments are essentially the same as the like components, which are denoted by like reference numerals in the embodiments.

Referring toFIG.3Aand with reference toFIG.2A, the structure shown inFIG.3Ais similar to the structure described inFIG.2A. The backside redistribution structure210including the backside patterned conductive layer211and the backside dielectric layer212may be formed on the temporary carrier51. The first TIVs252may be formed on the backside redistribution structure210and electrically coupled to the backside patterned conductive layer211. The first die110may be attached to the backside dielectric layer212of the backside redistribution structure210through the connecting film DF1on the back surface110bof the first die110. The first insulating encapsulation130may be formed on the backside redistribution structure210to laterally cover the first TIVs252, the first die110, and the connecting film DF1. The first die connectors114of the first die110and the first TIVs130may be accessibly revealed for further electrical connection. For example, the top surface130aof the first insulating encapsulation130is substantially leveled with the top surfaces252aof the first TIVs252, and the active surface110aof the first die110.

Referring toFIG.3Band with reference toFIG.2B, the structure shown inFIG.3Bis similar to the structure described inFIG.2B, except that the third die160′ and the first die110are arranged in a face-to-face configuration, and the middle redistribution structure220′ includes multiple levels of routing. For example, the middle redistribution structure220including the middle patterned conductive layer221′ and the middle dielectric layer222is first formed on the first insulating encapsulation130, the first TIVs252, and the third die110. Next, the second TIVs254may be formed on the middle redistribution structure220and electrically coupled to the middle patterned conductive layer221. The third die connectors166of the third die160′ may then be mounted on the topmost sublayer of the middle patterned conductive layer221′ through the conductive joints167, where the front surface160aof the third die160′ may face the active surface of the first die110. For example, the third device layer162is in proximity to the first die110, and the isolation layer165laterally covering the TSVs163is distal from the first die110. The third die160′ may be similar to the third die160described inFIG.2B, and it should be noted that not all of the elements in the third die160′ are illustrated herein for simplification.

In some embodiments, the first underfill layer UF1is formed in a gap between the front surface160aof the third die160′ and the middle redistribution structure220′ to surround the conductive joints167, the third die connectors166, and the corresponding conductive pads of the middle patterned conductive layer221′. In some embodiments, the second insulating encapsulation180is formed on the middle redistribution structure220′ to laterally cover the second TIVs254, the third die160′, and the first underfill layer UF1. For example, the top surface180aof the second insulating encapsulation180is substantially leveled (or coplanar) with the top surfaces254aof the second TIVs254and the back surface160bof the third die160′, where the surfaces163aof the TSVs163are accessibly exposed by the isolation layer165and the second insulating encapsulation180for further electrical connection. In some embodiments, the isolation layer165is formed after forming the second insulating encapsulation180. The various formations of the isolation layer165of the third die160′ will be discussed in accompanying withFIGS.4A-4DandFIGS.5A-5C.

Referring toFIG.3Cand with reference toFIG.2C, the structure shown inFIG.3Cis similar to the structure described inFIG.2C. For example, the front-side redistribution structure230including the front-side patterned conductive layer231and the front-side dielectric layer232is formed on the second insulating encapsulation180, the second TIVs254, and the third die160′. For example, the bottommost sublayer of the front-side patterned conductive layer231is in physical and electrical contact with the exposed surfaces of the second TIVs254and the TSVs163of the third die160′. The topmost sublayer of the front-side patterned conductive layer231may include UBM pads, and the conductive terminals195may be formed on a portion of the UBM pads of the front-side patterned conductive layer231. In some embodiments, at least one electrical device170, such as the IPD, is mounted on the other portion of the UBM pads of the front-side patterned conductive layer231and surrounded by the conductive terminals195.

Referring toFIG.3Dand with reference toFIGS.3C and2D, the structure shown inFIG.3Dis similar to the structure described inFIG.2D. For example, the structure ofFIG.3Cmay be flipped upside-down, and the conductive terminals195and/or the electrical device170may be disposed on the frame52. The temporary carrier51may be removed to accessibly reveal the backside redistribution structure210, and then the patterned dielectric layer213having the openings2130may be formed on the outermost sublayer of the backside dielectric layer212.

Referring toFIG.3Eand with reference toFIG.2E, the structure shown inFIG.3Eis similar to the structure described inFIG.2E. For example, the second die120, such as the memory package component, may be mounted on the backside redistribution structure210through the conductive joints1211. An underfill layer (not shown) is optionally formed in a gap between the second die120and the patterned dielectric layer213to surround the conductive joints1211. In some embodiments, a singulation process is performed to cut through the patterned dielectric layer213, the backside redistribution structure210, the first insulating encapsulation130, the middle redistribution structure220′, the second insulating encapsulation180, and the front-side redistribution structure230, so as to form a respective semiconductor packages10C.

The semiconductor package10C, similar to the semiconductor package10B shown inFIG.2E, may include the first tier T1_2stacked on a second tier T2_3, and a third tier T3stacked on the first tier T1_2. The main difference between the semiconductor package10C and the semiconductor package10B lies in that the first die110in the first tier T1_2and the third die160′ in the second tier T2_3are arranged in the face-to-face configuration, where the active surface of the third die160′ at the second tier T2_3faces the active surface of the first die110, and the middle redistribution structure220′ is interposed between and electrically coupled to the active surfaces of the first and third dies110and160. The top view of the semiconductor package10C may be similar to the top view described inFIG.2F, and the first die110may be replaced with a larger first die110′ as described in the preceding paragraphs, and thus the detailed descriptions are not repeated for the sake of brevity.

FIGS.4A-4Dare schematic cross-sectional views illustrating the formation of an isolation layer on a back surface of the third die, in accordance with some embodiments. The steps of forming the isolation layer and the redistribution structure may correspond to the processes described inFIGS.3B-3C. Unless specified otherwise, the materials and the formation methods of the components in these embodiments are essentially the same as the like components, which are denoted by like reference numerals in the embodiments.

Referring toFIG.4A, the second insulating encapsulation180is formed to extend along the sidewall of the third die160′. The interconnect structure168of the third die160′ may be disposed below the third device layer162and the TSV163, and the third device layer162formed in/on the third semiconductor substrate161may be electrically coupled to the TSV163through the interconnect conductive layer1681embedded in the interconnect dielectric layer1682. The TSV163may include a conductive pillar1631lining with a liner1632, where the conductive pillar1631is isolated from the third semiconductor substrate161through the liner1632. By way of example and not limitation, the critical dimension1631D of the conductive pillar1631is about 2 μm, and the thickness of the liner1632is less than the critical dimension1631D, e.g., about 0.15 μm. In some embodiments, after the planarization process is performed on the second insulating encapsulation180, the top surface180ais substantially leveled with the back surface161bof the third semiconductor substrate161and the surface163aof the TSV163.

Referring toFIG.4B, a backside of the third semiconductor substrate161may be thinned down to form a recess on the back surface161b′. For example, an etching process is performed on the backside of the third semiconductor substrate161, while the second insulating encapsulation180is covered by a masking layer (not shown) during the etching. After the etching, an upper portion of the TSV163is exposed and protruded from the back surface161b′ of the third semiconductor substrate161. By way of example and not limitation, the height163H of the exposed portion of the TSV163measured from the surface163ato the back surface161b′ is about 2 μm (or less than 2 μm).

Referring toFIG.4C, the isolation layer165may be formed on the back surface161b′ of the third semiconductor substrate161to laterally cover the exposed portion of the TSV163. In some embodiments, the isolation layer165is a dielectric (e.g., a low temperature polyimide material), and may be formed by coating and curing, etc. Although any other suitable dielectric material and deposition process may also be used to form the isolation layer165. In some embodiments, a planarization process is performed to level the top surface180aof the second insulating encapsulation180, the top surface165aof the isolation layer165, and the surface163aof the TSV163, within process variations. For example, the thickness165H of the isolation layer165is about 1.5 μm to about 2 μm.

Referring toFIG.4D, the bottommost sublayer2321having an opening23210of the front-side dielectric layer232may be formed on the second insulating encapsulation180and the isolation layer165, where the opening23210may accessibly exposed the TSV163. In some embodiments, a portion of the top surface of the isolation layer165surrounding the surface of the TSV163may also be accessibly revealed by the opening23210. The bottommost sublayer2321may include polyimide, and an interface be observed between the bottommost sublayer2321and the underlying isolation layer165. Next, the bottommost sublayer2311of the front-side patterned conductive layer231including the conductive via and the overlying conductive pad may be formed in the opening23210and on the top surface of the bottommost sublayer2321. In some embodiments, the conductive via of the bottommost sublayer2311of the front-side patterned conductive layer231has a tapered profile toward the TSV163, and the narrower end of the conductive via has the lateral dimension2311VD greater than the critical dimension1631D of the underlying TSV163. By way of example and not limitation, the lateral dimension2311VD of the conductive via of the front-side patterned conductive layer231is about 8 μm. In such embodiments, the narrower end of the conductive via is in physical contact with the surface163aof the TSV163and the portion of the top surface of the isolation layer165surrounding the surface163aof the TSV163.

FIGS.5A-5Care schematic cross-sectional views illustrating another formation of an isolation layer on a back surface of the third die, in accordance with some embodiments. The steps ofFIGS.5A-5Cmay be similar to the steps described inFIG.4A-4D, and thus the detailed descriptions are not repeated. The like components are denoted by like reference numerals in the embodiments.

Referring toFIG.5A, after recessing the backside of the third semiconductor substrate161as described inFIG.4B, a first isolation sublayer1651may be formed on the second insulating encapsulation180, the third semiconductor substrate161, and the TSV163. The first isolation sublayer1651may include (or may be) silicon nitride-based material, such as SiN or other suitable dielectric material, and may be deposited at low temperature. The first isolation sublayer1651may be conformally formed on the back surface161b′ of the third semiconductor substrate161, and the sidewalls and the top exposed surface163aof the TSV163. The first isolation sublayer1651may extend to cover the exposed sidewall180sand the top surface180aof the second insulating encapsulation180. In some embodiments, a portion of the first isolation sublayer1651formed on the top surface180aof the second insulating encapsulation180is formed as islands spatially apart from each other, and portions of the top surface180aof the second insulating encapsulation180which are covered by the islands are accessibly exposed. In some embodiments, the thickness1651H of the first isolation sublayer1651is less than about half of the critical dimension1631D. By way of example and not limitation, the thickness1651H of the first isolation sublayer1651is about 0.5 μm.

Referring toFIG.5Band with reference toFIG.5A, a second isolation sublayer1652may be formed on the first isolation sublayer1651. The second isolation sublayer1652may thus be separated from the third semiconductor substrate161and the second insulating encapsulation180by the first isolation sublayer1651. The second isolation sublayer1652and the first isolation sublayer1651may be of different materials and different thicknesses. For example, the second isolation sublayer1652is a dielectric (e.g., a low temperature polyimide material), and may be formed by coating and curing, etc. The second isolation sublayer1652may be thicker than the first isolation sublayer1651. By way of example and not limitation, the thickness1652H of the second isolation sublayer1652is about 1.5 μm to 2 μm. Subsequently, a planarization process (e.g., CMP, mechanical grinding, etching, a combination thereof, etc.) is performed, excess materials of the first and second isolation sublayers1651and1652. For example, after the planarization process, the top surface180aof the second insulating encapsulation180is substantially leveled with the surface163aof the TIV163, the top surface1651aof the first isolation sublayer1651, and the top surface1652aof the second isolation sublayer1652, where the first and second isolation sublayers1651and1652are collectively viewed as the isolation layer165′.

Referring toFIG.5Cand with reference toFIG.5B, the bottommost sublayer2321of the front-side dielectric layer232may be formed on the second insulating encapsulation180and the isolation layer165′, and then the bottommost sublayer2311of the front-side patterned conductive layer231may be formed in/on the bottommost sublayer2321. The forming process may be similar to the process described inFIG.4D. In some embodiments, the narrower end of the conductive via of the bottommost sublayer2311of the front-side patterned conductive layer231is in physical contact with the surface163aof the TSV163and the top surface1651aof the first isolation sublayer1651(and the top surface1652aof the second isolation sublayer1652, in some embodiments).

FIGS.6A-6Dare schematic cross-sectional views illustrating various stages of a manufacturing method of a semiconductor package having a face-to-face configuration, in accordance with some embodiments. Unless specified otherwise, the materials and the formation methods of the components in these embodiments are essentially the same as the like components, which are denoted by like reference numerals in the embodiments.

Referring toFIG.6Aand with reference toFIG.1D, the structure ofFIG.6Ais similar to the structure ofFIG.1D, and thus the detailed formation of each component is not repeated for simplicity. For example, the first and second dies110and120are laterally covered by the first insulating encapsulation130, and the first redistribution structure140including the first patterned conductive layer141and the first dielectric layer142is formed on the first and second dies110and120and the first insulating encapsulation130. Next, the conductive pillars150may be formed on the topmost sublayer of the first patterned conductive layer141.

Subsequently, the third dies (160_3and160_4) may be mounted on the first patterned conductive layer141and surrounded by the conductive pillars150. The third dies (160_3and160_4) may be similar to the third die160′ described inFIG.3B. For example, the first die110and the third dies (160_3and160_4) are arranged in the face-to-face configuration, where the third die connectors166of the third dies (160_3and160_4) are mounted onto the topmost sublayer of the first patterned conductive layer141through the conductive joints167. In some embodiments, the first electrical device170_1is disposed right over the first die110, laterally interposed between the third dies (160_1and160_2), and mounted onto the topmost sublayer of the first patterned conductive layer141through the conductive joints172. An underfill layer UF1is optionally formed in gaps between the third dies160_3and160_4and the underlying first patterned conductive layer141and also between the first electrical device170_1and the first patterned conductive layer141to surround the conductive joints167and172for protection. The underfill layer UF1may partially (or fully) cover the sidewalls of the first electrical device170_1and the third dies (160_3and160_4).

Referring toFIG.6Band with reference toFIG.6A, the second insulating encapsulation180may be formed on the first redistribution structure140to laterally cover the conductive pillars150, the third dies (160_3and160_4), the first electrical device170_1, and the underfill layer UF1. Since the conductive pillars150penetrate through the second insulating encapsulation180, the conductive pillars150are referred to as the TIVs. In some embodiments, a portion of the second insulating encapsulation180is formed on the top surface of the underfill layer UF1to laterally surround the sidewalls of the first electrical device170_1. In alterative embodiments, the first electrical device170_1and the third dies (160_3and160_4) are covered by the underfill layer UF1, and the second insulating encapsulation180is separated from the first electrical device170_1and the third dies (160_3and160_4) by the underfill layer UF1.

In some embodiments, the isolation layer165of the respective third die (160_3and160_4) is formed after forming the second insulating encapsulation180. The formation of the isolation layer165of the third die160′ may refer to the methods discussed in accompanying withFIGS.4A-4DandFIGS.5A-5C. In some embodiments, the second redistribution structure190including the second patterned conductive layer191and the second dielectric layer192is formed on the TIVs150, the second insulating encapsulation180, the third dies (160_3and160_4), and the first electrical device170_1. For example, the second patterned conductive layer191is physically and electrically connected to the TIVs150and the TSVs163of the third dies (160_3and160_4). The materials and the forming methods of the second redistribution structure190may be similar to those of the second redistribution structure190described inFIG.1Eor the backside redistribution structure230described inFIG.3C, and thus the detailed descriptions are not repeated.

Referring toFIG.6C, the conductive terminals195may be formed on a portion of the UBM pads of the topmost sublayer of the second patterned conductive layer191. In some embodiments, at least one second electrical device170_2, such as the IPD, is mounted on the other portion of the UBM pads of the f topmost sublayer of the second patterned conductive layer191and surrounded by the conductive terminals195. The conductive terminals195and the electrical device170_2may be similar to the conductive terminals195and the second electrical device170_2described inFIG.1E.

Subsequently, the structure ofFIG.6Cmay be flipped upside-down and placed on the frame, and then the temporary carrier51may be de-bonded to accessibly reveal the first insulating encapsulation130, the connecting film DF1, and the second die120. A singulation process may be performed to form a respective semiconductor package.

Referring toFIG.6D, the semiconductor package10D may include the first tier T1_1stacked on a second tier T2_4, where the first tier T1_1includes the first and second dies110and120, the first insulating encapsulation130, and the first redistribution structure140, and the second tier T2_4includes the third dies (160_3and160_4), the first and second electrical device170_1and170_2, the TIVs150, the second insulating encapsulation180, the second redistribution structure190, and the conductive terminals195. The third dies (160_3and160_4) and the first die110are arranged in the face-to-face configuration as the first die110and the third die160′ of the semiconductor package10C described inFIG.3E. For example, the front surfaces160aof the third dies (160_3and160_4) face the active surface110aof the first die110and the active surface120aof the second die120. The top view of the semiconductor package10D may be similar to the top view described inFIG.1G, and thus the detailed descriptions are not repeated for the sake of brevity.

FIGS.7A-7Fare schematic cross-sectional views illustrating various stages of a manufacturing method of a semiconductor package having a face-to-back configuration, in accordance with some embodiments. Unless specified otherwise, the materials and the formation methods of the components in these embodiments are essentially the same as the like components, which are denoted by like reference numerals in the embodiments.

Referring toFIG.7A, the front-side redistribution structure330including the front-side patterned conductive layer331and the front-side dielectric layer332may be formed over the temporary carrier51. The front-side redistribution structure330may be similar to the front-side redistribution structure230described in the preceding paragraphs. The bottommost sublayer of the front-side dielectric layer332having openings may be formed over the temporary carrier51, and then the bottommost sublayer of the front-side patterned conductive layer331may be formed in the openings and on the top surface of the bottommost sublayer of the front-side dielectric layer332. The forming steps of the sublayers may repeat several times to form a multi-layered redistribution structure. The topmost sublayer of the front-side patterned conductive layer331may include first pads3311and second pads3312surrounding the first pads3311and formed on the top surface of the topmost sublayer of the front-side dielectric layer332for further electrical connection. The first TIVs354may be formed on the second pads3312of the front-side patterned conductive layer331of the front-side redistribution structure330.

The third die160′ may be mounted on the first pads3311of the front-side patterned conductive layer331of the front-side redistribution structure330through the conductive joints167, where the front surface160aof the third die160′ face the front-side redistribution structure330. In some embodiments, the first underfill layer UF1is formed on the front-side redistribution structure330to surround the conductive joints167for protection. In some embodiments, the second insulating encapsulation180is formed on the front-side redistribution structure330to laterally cover the first TIVs354, the third die160′, and the first underfill layer UF1. For example, the top surface180aof the second insulating encapsulation180is substantially leveled with the top surfaces354aof the first TIVs354, and the back surface160bof the third die160′, where the surfaces of the TSVs163and the isolation layer165are substantially leveled at the back surface160b. The formation of the isolation layer165may be similar to the processes described inFIGS.4A-4DorFIGS.5A-5C.

Referring toFIG.7B, the middle redistribution structure320including the middle patterned conductive layer321and the middle dielectric layer322may be formed on the second insulating encapsulation180, the first TIVs354, and the third die160′. The middle redistribution structure320may be similar to the middle redistribution structure220′ described in the preceding paragraphs. The bottommost sublayer of the middle dielectric layer322having openings may be formed to accessibly expose the first TIVs354and the TSVs163of the third die160′, and then the bottommost sublayer of the middle patterned conductive layer321may be formed in the openings to be in physical and electrical contact with the first TIVs354and the TSVs163. The forming steps of the sublayers may repeat several times to form a multi-layered redistribution structure. The topmost sublayer of the middle patterned conductive layer321may include first pads3211and second pads3212surrounding the first pads3211and formed on the top surface of the topmost sublayer of the middle dielectric layer322for further electrical connection. The second TIVs352may be formed on the second pads3212of the middle patterned conductive layer321of the middle redistribution structure320.

In some embodiments, the first die110′ is mounted onto the first pads3211of the middle patterned conductive layer321of the middle redistribution structure320through conductive joints115, e.g., solder joints. The first die110′ may be similar to the first die110described in the preceding paragraphs. For example, the first device layer112underlies the first semiconductor substrate111, the first die connectors113are disposed below the first device layer112, and the conductive joints115are coupled to the first die connectors113and the first pads3211. The active surface110aof the first die110′ faces the back side of the third die160′, and such configuration may be referred to as the face-to-back configuration. A second underfill layer UF2is optionally formed in a gap between the active surface110aof the first die110′ and the middle redistribution structure320to surround the conductive joints115, the first die connectors113, and the first pads3211.

In some embodiments, a first insulating encapsulation130is formed on the middle redistribution structure320to laterally cover the second TIVs352, the first die110′, and the second underfill layer UF2. A planarization process (e.g., CMP, mechanical grinding, etching, a combination thereof, etc.) may be performed to substantially level the top surface130aof the first insulating encapsulation130, the top surface352aof the second TIVs352, and the back surface110bof the first die110′. In some embodiments, a backside redistribution structure310including the backside patterned conductive layer311and the backside dielectric layer312is formed on the first insulating encapsulation130, the second TIVs352, and the first die110′. The backside redistribution structure310may be similar to the backside redistribution structure210described in the preceding paragraphs. For example, the bottommost sublayer of the backside patterned conductive layer311is physical and electrical contact with the top surface352aof the second TIVs352.

Referring toFIG.7Cand with reference toFIG.7B, the structure ofFIG.7Bmay be flipped upside-down, and the backside redistribution structure310may be disposed over a second temporary carrier53. The first temporary carrier51may then be removed to accessibly reveal the front-side redistribution structure330. The removal of the first temporary carrier51may be similar to the de-bonding process described inFIG.1F, and thus the detailed descriptions are not repeated. In some embodiments, after the removal of the first temporary carrier51, the surfaces331aand332aof the front-side patterned conductive layer331and the front-side dielectric layer332are accessibly revealed.

Referring toFIG.7Dand with reference toFIG.7C, UBM pads333may be formed on the surfaces331aof the front-side patterned conductive layer331. In some embodiments, the conductive terminals195are formed on a portion of the UBM pads333. The electrical device170is optionally formed on the other portion of the UBM pads333and surrounded by the conductive terminals195through the conductive joints172. A third underfill layer UF3is optionally formed in a gap between the electrical device170and the front-side redistribution structure330to surround the conductive joints172. The conductive terminals195and the electrical device170may be similar to the conductive terminals195and the electrical device170described inFIG.2C.

Referring toFIG.7Eand with reference toFIG.7D, the structure of theFIG.7Dmay be flipped upside-down, and the conductive terminals195and/or the electrical device170may be placed on the frame52. The second temporary carrier53may then be removed by the method similar to the removal of the first temporary carrier51to accessibly reveal the backside redistribution structure310. In some embodiments, the patterned dielectric layer213having the openings2130is formed on the outermost sublayer of the backside dielectric layer312, and at least a portion of the outermost sublayer of the backside patterned conductive layer311may be accessibly revealed by the openings2130for further electrical connection. The material and the formation of the patterned dielectric layer213may be similar to the patterned dielectric layer213described inFIG.2D.

Referring toFIG.7Fand with reference toFIG.7E, the second die120, such as the memory package component, may be mounted on the backside redistribution structure310through the conductive joints1211, e.g., solder joints. The mounting process of the second die120may be similar to the process described inFIG.2E. In some embodiments, the aforementioned processes are performed at wafer level, and a singulation process is performed to cut through the patterned dielectric layer213, the backside redistribution structure310, the first insulating encapsulation130, the middle redistribution structure320, the second insulating encapsulation180, and the front-side redistribution structure330, so as to form a respective semiconductor package10E.

With continued reference toFIG.7Fand also referring toFIG.3E, the semiconductor package10E is similar to the semiconductor package10C described inFIG.3E. The difference therebetween includes that the first and third dies (110′ and160′) in the semiconductor package10E are arranged in the face-to-back configuration, while the first and third dies in the semiconductor package10C are arranged in the face-to-face configuration. For example, the first die110′ in the first tier T1_5of the semiconductor package10E is coupled to the middle redistribution structure320through the conductive joints115. The backside of the third die160′ in the second tier T2_5of the semiconductor package10E faces the active surface of the first die110′, and the active surface of the third die160′ is coupled to the front-side redistribution structure330through the conductive joints167.

The difference between the semiconductor package10E and the semiconductor package10C further includes that the conductive vias in the front-side, middle, and backside redistribution structures (330,320, and310) of the semiconductor package10E are tapered toward a same direction from the first tier T1_5toward the second tier T2_5, while the conductive vias in the front-side, middle, and backside redistribution structures (230,220′, and210) of the semiconductor package10C are tapered toward a same direction from the second tier T2_3toward the first tier T1_3. The top view of the semiconductor package10E may be similar to the top view described inFIG.2F, and thus the detailed descriptions are not repeated for the sake of brevity.

FIG.8is a schematic cross-sectional view illustrating a semiconductor package having a face-to-back configuration, in accordance with some embodiments. The formation of the semiconductor package10F having the face-to-back configuration illustrated inFIG.8Amay be similar to the forming methods of the semiconductor package10E described inFIGS.7A-7F, and thus the detailed descriptions are not repeated. The like components are denoted by like reference numerals in the embodiments.

Referring toFIG.8Aand with reference toFIG.7F, the semiconductor package10F may include the first tier T1_6stacked on the second tier T2_6. The first tier T1_6includes the first and second dies110′ and120, the first insulating encapsulation130, and the middle redistribution structure320. For example, more than one first dies110′ are disposed side by side and coupled to the conductive pads of the middle redistribution structure320through the conductive joints115surrounded by the second underfill layer UF2. The second die120may be disposed next to one of the first dies110′, and the second die connectors121of the second die120may be coupled to the conductive pads of the middle redistribution structure320. For example, the second die connectors121′ (as described inFIG.1A) of the second die120are disposed on the conductive pads of the middle redistribution structure320, and then a reflow process is performed on the second die connectors121′ to form the conductive joints121″ (e.g., solder joints) between the pillar portions of the second die connectors and the underlying conductive pads of the middle redistribution structure320.

In some embodiments, a third underfill layer UF3is formed in a gap between the second die120and the middle redistribution structure320to surround the second die connectors121and the underlying conductive pads of the middle redistribution structure320. In some embodiments, the first insulating encapsulation130covers a portion of the sidewalls of the first dies110′ that is not covered by the second underfill layer UF2. In some embodiments, the back surface120bof the second die120is lower than the back surface110bof the respective first die110′, relative the middle redistribution structure320. The first insulating encapsulation130may cover the sidewall and the back surface of the second die120, where the thickness of the respective first die110′ is less than the thickness of the second die120. Alternatively, the back surfaces110bof the first dies110′ are substantially leveled with the back surface120bof the second die120.

The second tier T2_6includes the third dies160′, the TIVs150, the second insulating encapsulation180, the front-side redistribution structure330, the conductive terminals195, and the electrical device170. The third dies160′ and the first die110′ are arranged in the face-to-back configuration as the first die110′ and the third die160′ of the semiconductor package10E described inFIG.7F. In alternative embodiments, the first electrical device, such as the IPD, is embedded in the second insulating encapsulation180and the first underfill layer UF1and is mounted onto the conductive pads of the front-side patterned conductive layer331of the front-side redistribution structure330through the conductive joints (e.g., solder joints). The third die160′ may be disposed right over the one of the first dies110′ and the second die120. In some embodiments, the third die160′ are electrically coupled to the first die(s)110′ and the second die120. In alternative embodiments, the third die160′ is disposed right over adjacent two of the first dies110′ and coupled to the two of the first dies110′.

FIGS.9A,10A, and11Aare schematic cross-sectional views illustrating various semiconductor packages, andFIGS.9B,10B, and11Bare schematic top views illustrating configurations of various dies and electrical devices in the corresponding semiconductor packages ofFIGS.9A,10A, and11A, respectively, in accordance with some embodiments.

Referring toFIG.9A, a semiconductor package10G includes the first tier T1_3stacked over the second tier T2_7, and the third tier T3stacked over the first tier T1_3, where the first tier T1_3and the third tier T3are similar to the first and third tiers T1_3and T3of the semiconductor package10B described inFIG.2E. The second tier T2_7includes the third dies (160_1and160_2) arranged side by side and separated from each other by the second insulating encapsulation180and the second TIVs254, where the third dies (160_1and160_2) may be similar to the third dies (160_1and160_2) of the semiconductor package10A described inFIG.1For the third die160of the semiconductor package10B described inFIG.2E. For example, the third dies (160_1and160_2) in the second tier T2_7and the first die110in first tier T1_3are arranged in the back-to-face configuration.

In some embodiments, the first die110in the first tier T1_3and the third dies in the underlying second tier T2_7are arranged in the face-to-face configuration, where the third dies may be replaced with the third dies (160_3and160_4) of the semiconductor package10D described inFIG.6D. In some embodiments, the first die in the first tier and the third dies in the underlying second tier are arranged in the face-to-back configuration, where the first and third dies may be respectively replaced with the first die110′ and the third dies160′ of the semiconductor package10E described inFIG.7F.

Referring toFIG.9Band with reference toFIG.9A, the lateral dimension of the first die110may be less than that of the second die120. For example, in the top view, the orthographic projection area of the first die120is fully located within the orthographic projection area of the second die120. The lateral dimension of the respective third die (160_1or160_2) may be less than that of the first die110. In some embodiments, the orthographic projection area of one of the third dies (160_1and160_2) overlaps the orthographic projection area of the first die110, and the orthographic projection area of the other one of the third dies (160_1and160_2) overlaps the first and second dies110and120. The third dies (160_1and160_2) may have the same orthographic projection area or may have different orthographic projection areas. The boundary of the third die (160_1and/or160_2) may extend beyond the boundary of the first die110, in the top view. It should be noted that the configuration shown inFIG.9Bis merely an example, and the number and the arrangement of these dies can be adjusted depending on product requirements.

Referring toFIG.10A, a semiconductor package10H includes the first tier T1_8stacked over the second tier T2_8, and the third tier T3stacked over the first tier T1_8. The first tier T1_8includes more than one first dies110arranged side by side and separated from each other by the first insulating encapsulation130. The second tier T2_8includes the third die160surrounded by the second TIVs254, where the third die160may be similar to the third die (160_1or160_2) of the semiconductor package10A described inFIG.1For the third die160of the semiconductor package10B described inFIG.2E. In some embodiments, the third die160is a bridge die in electrical communication with the first dies110. For example, the third die160in the second tier T2_8and the first dies110in the first tier T1_8are arranged in the back-to-face configuration. In some embodiments, the first dies110in the first tier T1_8and the third die160in the underlying second tier T2_8are arranged in the face-to-face configuration, where the third die may be replaced with the third die (160_3or160_4) of the semiconductor package10D described inFIG.6D. In some embodiments, the first dies in the first tier and the third die in the underlying second tier are arranged in the face-to-back configuration, where the first and third dies may be respectively replaced with the first die110′ and the third dies160′ of the semiconductor package10E described inFIG.7F.

Referring toFIG.10Band with reference toFIG.10A, the lateral dimension of each first die110may be less than that of the second die120and may also be less than that of the third die160. The first dies110may have the same orthographic projection area or may have different orthographic projection areas. For example, in the top view, the orthographic projection area of the third die160is fully located within the orthographic projection area of the second die120. In some embodiments, the orthographic projection area of each first die110partially overlaps the orthographic projection area of the third die160. The boundary of the respective first die110may extend beyond the boundary of the third die160, in the top view. It should be noted that the configuration shown inFIG.10Bis merely an example, and the number and the arrangement of these dies can be adjusted depending on product requirements.

Referring toFIG.11Aand with reference toFIG.9A, a semiconductor package10I includes the first tier T1_3stacked over the second tier T2_9, and the third tier T3stacked over the first tier T1_3, where the first tier T1_3is the same as the first tier T1_3of the semiconductor package10G inFIG.9A, and the third dies (160_1and160_2) in the second tier T2_9and the first die110in the first tier T1_3are arranged in the back-to-face configuration. The second tier T2_9is similar to the second tier T2_7, except that the second tier T2_9includes at least one first electrical device170_1interposed between the third dies (160_1and160_2). In some embodiments, first die110in the first tier T1_3and the third dies in the second tier T2_9are arranged in the face-to-face configuration, where the third dies may be replaced with the third die (160_3or160_4) of the semiconductor package10D described inFIG.6D. In some embodiments, the first dies in the first tier and the third die in the underlying second tier are arranged in the face-to-back configuration, where the first and third dies may be respectively replaced with the first die110′ and the third dies160′ of the semiconductor package10E described inFIG.7F.

Referring toFIG.11Band with reference toFIG.11A, in the top view, a plurality of first electrical devices170_1are arranged in a column between the third dies (160_1and160_2). It should be noted that the number and the arrangement of the first electrical devices170_1are merely an example and construe no limitation in the disclosure. The lateral dimension of each first die110may be less than that of the second die120. For example, in the top view, the orthographic projection area of the first die120is fully located within the orthographic projection area of the second die120. The lateral dimension of the respective third die (160_1or160_2) may be less than that of the first die110. For example, the orthographic projection area of the respective third die (160_1and160_2) partially overlaps the orthographic projection area of the first die110, and the column of the first electrical devices170_1is fully located within the orthographic projection area of the first die110. The boundary of the third die (160_1and/or160_2) may extend beyond the boundary of the first die110, in the top view. It should be noted that the configuration shown inFIG.11Bis merely an example, and the number and the arrangement of these dies and electrical devices can be adjusted depending on product requirements.

According to some embodiments, a semiconductor package includes a first tier and a second tier underlying the first tier. The first tier includes a first die and a second die disposed side by side and separated from each other by a first insulating encapsulation, and a first redistribution structure. A surface of the first insulating encapsulation is substantially leveled with surfaces of first die connectors of the first die and truncated spherical surfaces of second die connectors of the second die, and the first redistribution structure underlies the surfaces of the first insulating encapsulation and the first die connectors of the first die and the truncated spherical surfaces of the second die connectors of the second die. The second tier includes third dies disposed below the first redistribution structure, and TIVs. The third dies are electrically coupled to the first die through the first redistribution structure and laterally covered by a second insulating encapsulation. The TIVs penetrate through the second insulating encapsulation and are electrically coupled to the second die through the first redistribution structure.

According to some alternative embodiments, a semiconductor package includes a first tier and a second tier underlying the first tier. The first tier includes at least one first die including first die connectors distributed on a first active surface, a second die laterally separated from the first die by a first insulating encapsulation, and a first redistribution structure underlying the at least one first die, the second die, and the first insulating encapsulation. The second die includes second die connectors distributed on a second active surface, and the second die is coupled to the first redistribution structure through first solder joints. The second tier includes at least one third die disposed below the first redistribution structure and laterally covered by a second insulating encapsulation, TIVs penetrating through the second insulating encapsulation and electrically coupled to the second die through the first redistribution structure, and a second redistribution structure underlying the third die, the second insulating encapsulation, and the TIVs. The third die includes TSVs penetrating through a semiconductor substrate and electrically coupled to the first die, and third die connectors of the third die are coupled to the first redistribution structure or the second redistribution structure through second solder joints.

According to some alternative embodiments, a semiconductor package includes a first tier, a second tier stacked upon the first tier, and a third tier underlying the first tier. The first tier includes at least one first die including an active surface and a back surface opposite to each other, a first insulating encapsulation laterally covering the at least one first die, a first TIV penetrating through the first insulating encapsulation, a backside redistribution structure overlying the first insulating encapsulation, the first TIV, and the back surface of the at least one first die, and a middle redistribution structure underlying the first insulating encapsulation, the first TIV, and the active surface of the at least one first die. The second tier is a second die electrically coupled to the at least one first die through the backside redistribution structure, the first TIV, and the middle redistribution structure. The third die includes at least one third die including an active surface and a back surface opposite to each other, a second insulating encapsulation laterally covering the at least one third die, a second TIV penetrating through the second insulating encapsulation, and a front-side redistribution structure underlying the second insulating encapsulation, the second TIV, and the active surface of the at least one third die. The middle redistribution structure is interposed between the back surface of the at least one third die and the active surface of the at least one first die and is electrically coupled to the at least one first die and the at least one third die.