DISPLAY DEVICE AND DRIVING METHOD THEREOF

A display device includes gate lines which transmits a plurality of gate signals, data lines which transmits a plurality of data signals, and pixels connected to the gate lines and the data lines; a signal controller which generates image data, a data control signal and a gate control signal based on an input video signal and an input control signal; a timing setter including connection pads connected to a voltage of a first level or a voltage of a second level; and a gate driver which generates timing information based on tuning signals transmitted from the timing setter through the connection pads and generates gate signals using the gate control signal and the timing information, where the gate control signal includes a scan start reference signal, which instructs a scan start, and a clock control reference signal, which controls each pulse width of the gate signal.

DETAILED DESCRIPTION

Embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a region illustrated or described as flat may, typically, have rough and/or nonlinear features. Moreover, sharp angles that are illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the claims set forth herein.

Hereinafter, exemplary embodiments of the invention will be described in further detail with reference to the accompanying drawings.

FIG. 1is a block diagram showing an exemplary embodiment of a display device according to the invention.

Referring toFIG. 1, an exemplary embodiment of a display device includes a display panel100, a signal controller200, a gate driver300, a timing setter400and a data driver500. In an exemplary embodiment, the signal controller200, the gate driver300and the data driver500may be integrated in a single chip. In an alternative exemplary embodiment, the signal controller200, the gate driver300and the data driver500may be attached to the display panel100in the form of a tape carrier package (“TCP”) on a flexible printed circuit (“FPC”). In another alternative exemplary embodiment, the signal controller200, the gate driver300and the data driver500may be attached on a separate flexible printed circuit (“FPC”) (or a printed circuit board). In such an embodiment, the display panel100may be one of a liquid crystal display panel and an organic light emitting display panel, for example.

In an exemplary embodiment, the display panel100includes a plurality of gate lines, e.g., first to n-th gate lines S1-Sn, that transmits a plurality of gate signals, e.g., first to n-th gate signals G1-Gn, a plurality of data lines, e.g., first to m-th data lines DL1-DLm, that transmits a plurality of data signals, e.g., first to m-th data signals D1-Dm, and a plurality of pixels PX connected to the gate lines S1-Sn and the data lines D1-Dm. In such an embodiment, each pixel PX may be connected to a corresponding gate line of the gate lines S1-Sn and a corresponding data line of the data lines D1-Dm. Here, each of n and m is a natural number.

The signal controller200receives input video signals R, G and B and input control signals that controls a display of the input video signals R, G and B, for example, a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock signal MCLK and a data enable signal DE. The signal controller200generates image data DATA and a data control signal CONT1based on the input video signals R, G and B, and the input control signals, and transmits the image data DATA to the data driver500along with the data control signal CONT1.

In an exemplary embodiment, the signal controller200generates a gate control signal CONT2based on the input control signal, and transmits the gate control signal CONT2to the gate driver300. In such an embodiment, the gate control signal CONT2may include a scan start reference signal STVS that instructs a scan start, and a clock control reference signal CPVS that controls each pulse width of the gate signals G1-Gn. Each of the scan start reference signal STVS and the clock control reference signal CPVS include a pulse signal that is activated during a frame unit.

In an exemplary embodiment, the gate driver300includes a plurality of input pins, e.g., first to fourth pins1-4, and receives a plurality of predetermined tuning signals, e.g., first to fourth tuning signals T1-T4, from the timing setter400through the input pins1-4. In an exemplary embodiment, the gate driver300may further receive a first power source voltage VDD, a second power source voltage VSS, a ground voltage GND, a gate on voltage VGG and a gate off voltage VEE, for example.

The gate driver300generates timing information corresponding to the tuning signals T1-T4, and generates the gate signals G1-Gn using the gate control signal CONT2and the timing information. In an exemplary embodiment, the gate driver300divides the gate lines S1-Sn into four groups, and the four groups of the gate lines S1-Sn are driven independently of each other by the gate driver300. Hereafter, (4 k+1)-th gate lines of the gate lines S1-Sn are defined as a first group, (4 k+2)-th gate lines of the gate lines S1-Sn are defined as a second group, (4 k+3)-th gate lines are defined as a third group, and (4 k+4)-th gate lines are defined as fourth group. Here, k is an integer equal to or greater than zero (0).

The timing setter400includes a plurality of connection pads, e.g., first to fourth connection pads P1-P4, and each of the connection pads P1-P4may be connected to a voltage of a first level (e.g., the first power source voltage VDD) or a voltage of second level (e.g., first level the ground voltage GND). The connection pads P1-P4are connected to the gate driver300through a plurality of wires, e.g., first to fourth wires301-304.

In an exemplary embodiment, the connection pads P1-P4is disposed on a circuit board disposed outside the gate driver300. In such an embodiment, a connection between the connection pads P1-P4and the first power source voltage VDD or the ground voltage GND is determined by a user, and the connection pads P1-P4and the first power source voltage VDD or the ground voltage GND may be connected after the gate driver300is attached to the circuit board.

In an exemplary embodiment, the tuning signals T1-T4transmitted to the gate driver300through the wires301-304are determined based on the connection between the connection pads P1-P4and the first power source voltage VDD or the ground voltage GND.

The data driver500converts the image data DATA into the data signals D1-Dm based on the data control signal CONT1, and transmits the data signals D1-Dm to the data lines DL1-DLm, respectively.

FIG. 2is a block diagram showing an exemplary embodiment of the gate driver300shown inFIG. 1.

Referring toFIG. 2, an exemplary embodiment of the gate driver300according to the invention includes an input buffer310, an address pointing register320, a timing controller330, a shift register340, a level shifter350and an output buffer360. In such an embodiment, the input buffer310may receive the scan start reference signal STVS and the clock control reference signal CPVS for buffering, and transmits the scan start reference signal STVS and the clock control reference signal CPVS to the timing controller330.

In an exemplary embodiment, the address pointing register320includes the first to fourth input pins1-4connected to the wires301-304, respectively. The address pointing register320receives the tuning signals T1-T4corresponding to the first power source voltage VDD or the ground voltage GND through the first to fourth input pins1-4.

In an exemplary embodiment, the address pointing register320generates the timing information by performing digital signal processing on the tuning signals T1-T4. In such an embodiment, the address pointing register320converts a tuning signal corresponding to the first power source voltage VDD into a ‘1’ digital bit, and converts a tuning signal corresponding to the ground voltage GND into a ‘0’ digital bit to generate the timing information of 4 bit data.

In one exemplary embodiment, for example, where the first and second connection pads P1and P2are connected to the first power source voltage VDD, and the third and fourth connection pads P3and P4are connected to the ground voltage GND, the address pointing register320generates the timing information as ‘1100’.

In an exemplary embodiment, the address pointing register320includes a lookup table LUT, which stores a delay time for the timing information. In such an embodiment, the lookup table LUT may include a first reference delay time corresponding to the scan start reference signal STVS and a second reference delay time corresponding to the clock control reference signal CPVS for each timing information set. The address pointing register320extracts the delay time corresponding to the generated timing information from the lookup table LUT to generate timing data ROUT.

The timing controller330selectively delays the scan start reference signal STVS and the clock control reference signal CPVS output from the input buffer310based on the timing data ROUT to generate first to fourth scan start signals STV1-STV4and first to fourth clock control signals CPV1-CPV4, which correspond to the first to fourth groups of the gate lines S1-Sn, respectively.

In an exemplary embodiment, the shift register340outputs a plurality of pulse signals, e.g., first to n-th pulse signals SS1-SSn, based on the first to fourth scan start signals STV1-STV4and the first to fourth clock control signals CPV1-CPV4. In such an embodiment, a high level of the pulse signals SS1-SSn corresponds to the first power source voltage VDD (shown inFIG. 4) and a low level of the pulse signals SS1-SSn corresponds to the second power source voltage VSS (shown inFIG. 4). The level shifter350converts a voltage level of the pulse signals SS1-SSn into the gate-on voltage VGG (shown inFIG. 4) and the gate-off voltage VEE (shown inFIG. 4) to output a plurality of gate pulse signals, e.g., first to n-th gate pulse signals LSS1-LSSn. The output buffer360buffers the gate pulse signals LSS1-LSSn to output the gate signals G1-Gn.

FIG. 3is a block diagram showing an exemplary embodiment of the timing controller330shown inFIG. 2.

Referring toFIG. 3, an exemplary embodiment of the timing controller330according to the invention includes first to fourth sub-timing controllers TC1-TC4corresponding to the first to fourth groups of the gate lines S1-Sn, respectively.

In an exemplary embodiment, each of the first to fourth sub-timing controllers TC1-TC4receive the scan start reference signal STVS, the clock control reference signal CPVS and the timing data ROUT. Hereinafter, an exemplary embodiment where the timing data ROUT is the delay time corresponding to a unit time td will be described for convenience of description.

The first sub-timing controller TC1delays each of the scan start reference signal STVS and the clock control reference signal CPVS by the unit time td to generate the first scan start signal STV1and the first clock control signal CPV1.

In such an embodiment, the first scan start signal STV1is activated at a second time point t2, and the first clock control signal CPV1is activated at a third time point t3. In such an embodiment, the first sub-timing controller TC1generates the first scan start signal STV1and the first clock control signal CPV1to have a same pulse width, e.g., a pulse width corresponding to two times the unit time td, as shown inFIG. 3.

In such an embodiment, the second sub-timing controller TC2delays each of the scan start reference signal STVS and the clock control reference signal CPVS by two times the unit time td to generate the second scan start signal STV2and the second clock control signal CPV2. In such an embodiment, the second scan start signal STV2is activated at the third time point t3, and the second clock control signal CPV2is activated at a fourth time point t4.

In such an embodiment, the third sub-timing controller TC3respectively delays the scan start reference signal STVS and the clock control reference signal CPVS by three times the unit time td to generate the third scan start signal STV3and the third clock control signal CPV3. In such an embodiment, the third scan start signal STV3is activated at the fourth time point t4, and the third clock control signal CPV3is activated at a fifth time point t5.

In such an embodiment, the fourth sub-timing controller TC4respectively delays the scan start reference signal STVS and the clock control reference signal CPVS by four times the unit time td to generate the fourth scan start signal STV4and the fourth clock control signal CPV4. In such an embodiment, the fourth scan start signal STV4is activated at the fifth time point t5, and the fourth clock control signal CPV4is activated at a sixth time point t6.

FIG. 4is a block diagram showing an exemplary embodiment of the shift register340and the level shifter350shown inFIG. 2.

Referring toFIG. 4, an exemplary embodiment of the shift register340includes the first to fourth shift registers SR1-SR4corresponding to the first to fourth groups of the gate lines S1-Sn, respectively. In such an embodiment, the level shifter350includes the first to fourth level shifters LS1-LS4corresponding to the first to fourth groups of the gate line S1-Sn, respectively. InFIG. 4, only 12 pulse signals SS1-SS12and 12 gate pulse signals LSS1-LSS12are shown for convenience of illustration, and the remaining pulse signals and the remaining gate pulse signals are generated in substantially the same manner as the 12 pulse signals SS1-SS12and the 12 gate pulse signals LSS1-LSS12shown inFIG. 4.

The first shift register SR1is in synchronization with a rising edge of the first clock control signal CPV1during an activation period of the first scan start signal STV1to output the first pulse signal SS1. The first shift register SR1sequentially shifts the first pulse signal SS1by a predetermined time to output the fifth pulse signal SS5and the ninth pulse signal SS9.

The second shift register SR2is in synchronization with a rising edge of the second clock control signal CPV2during the activation period of the second scan start signal STV2to output the second pulse signal SS2. The second shift register SR2sequentially shifts the second pulse signal SS2by the predetermined time to output the sixth pulse signal SS6and the tenth pulse signal SS10.

The third shift register SR3is in synchronization with a rising edge of the third clock control signal CPV3during the activation period of the third scan start signal STV3to output the third pulse signal SS3. The third shift register SR3sequentially shifts the third pulse signal SS3by the predetermined time to output the seventh pulse signal SS7and the eleventh pulse signal SS11.

The fourth shift register SR4is in synchronization with a rising edge of the fourth clock control signal CPV4during the activation period of the fourth scan start signal STV4to output the fourth pulse signal SS4. The fourth shift register SR4sequentially shifts the fourth pulse signal SS4by the predetermined time to output the eighth pulse signal SS8and the twelfth pulse signal SS12.

The first level shifter LS1converts the (4 k+1)-th pulse signal output from the first shift register SR1. In an exemplary embodiment, as shown inFIG. 4, each voltage level of the first, fifth and ninth pulse signals SS1, SS5and SS9is converted into the level of the gate-on voltage VGG and the gate-off voltage VEE. The second level shifter LS2converts the (4 k+2)-th pulse signal output from the second shift register SR2. In such an embodiment, each voltage level of the second, sixth, and tenth pulse signals SS2, SS6and SS10into the level of the gate-on voltage VGG and the gate-off voltage VEE.

In such an embodiment, the third and fourth level shifters LS3and LS4convert each voltage level of the (4 k+3)-th and the (4 k+4)-th pulse signal output from the third and fourth shift registers SR3and SR4into the level of the gate-on voltage VGG and the gate-off voltage VEE.

FIG. 5is a block diagram showing an alternative exemplary embodiment of a timing controller330′ according to the invention.

Referring toFIG. 5, an exemplary embodiment of the timing controller330′ may include a first sub-timing controller TC11and a second sub-timing controller TC12. In such an embodiment, the first sub-timing controller TC11and the second sub-timing controller TC12receive the scan start reference signal STVS, the clock control reference signal CPVS and the timing data ROUT. Hereinafter, an exemplary embodiment where the timing data ROUT is the delay time corresponding to the unit time td will be described for convenience of description.

The first sub-timing controller TC11delays the scan start reference signal STVS by the unit time td to generate a first scan start signal STV11. The first sub-timing controller TC11delays the clock control reference signal CPVS by the unit time td to generate a first clock control signal CPV11, and delays the clock control reference signal CPVS by two times the unit time td to generate a second clock control signal CPV12.

The first sub-timing controller TC11transmits the first scan start signal STV11to the first and second shift registers SR1and SR2, the first clock control signal CPV11to the first shift register SR1, and the second clock control signal CPV12to the second shift register SR2. In an exemplary embodiment, as shown inFIG. 3, the first and second sub-timing controllers TC1and TC2may output the first and second scan start signals STV1and STV2, respectively. In an alternative exemplary embodiment, as shown inFIG. 5, the first scan start signal STV11is simultaneously output the first clock control signal CPV11to the first shift register SR1and the second shift register SR2. In an exemplary embodiment, as shown inFIG. 5, the timing controller330′ includes two sub-timing controllers TC11and TC12. In an alternative exemplary embodiment, the timing controller330′ may include four sub-timing controllers TC1-TC4as shown inFIG. 3, and two sub-timing controllers TC1and TC2among the four sub-timing controllers TC1-TC4may collectively operate as the first sub-timing controller TC11shown inFIG. 5, and remaining two sub-timing controllers TC3and TC4may collectively operate as the second sub-timing controller TC12shown inFIG. 5.

In an exemplary embodiment, as shown inFIG. 5, the first sub-timing controller TC11may generate the pulse width of the first scan start signal STV11to be greater than the pulse width of the first scan start signal STV1shown inFIG. 3. In such an embodiment, two shift registers SR1and SR2are controlled by the first scan start signal STV11, and the activation period of the first scan start signal STV11may be controlled to overlap the rising edge of the first and second clock control signals CPV11and CPV12. In one exemplary embodiment, for example, the first scan start signal STV11may be generated to have a pulse width corresponding to three times the unit time td, and each of the first clock control signal CPV11and the second clock signal CPV12may be generated to have a pulse width corresponding to two times the unit time td.

In such an embodiment, the second sub-timing controller TC12delays the scan start reference signal STVS by three times the unit time td to generate the second scan start signal STV12. The second sub-timing controller TC12delays the clock control reference signal CPVS by three times the unit time td to generate the third clock control signal CPV13and the clock control reference signal CPVS by four times the unit time td to generate the fourth clock control signal CPV14.

FIG. 6is a block diagram showing an alternative exemplary embodiment of an address pointing register320′ according to the invention.

Referring toFIG. 6, an exemplary embodiment of the address pointing register320′ according to the invention is substantially the same as the exemplary embodiment of the address pointing register320shown in inFIGS. 1 and 2, except that the wires301-304are connected to two connection pads P11and P12. In such an embodiment, the four input pins1-4may collectively correspond to the two connection pads P11and P12. In such an embodiment, two connection pads, e.g., first and second connection pads P11and P12, are connected to the first power source voltage VDD and the ground voltage GND, respectively, for example.

FIG. 7is a block diagram showing another alternative exemplary embodiment of an address pointing register320″ according to the invention.

Referring toFIG. 7, an exemplary embodiment of the address pointing register320″ according to of the invention is connected to two connection pads P21and P22, and includes 8 input pins1-8. In an exemplary embodiment, where the address pointing register includes four input pins, the address pointing register may receive 16 timing information sets. In an alternative exemplary embodiment, where the address pointing register includes the 8 input pins is connected to a timing setter400″ via first to eighth wires301-308, as shown inFIG. 7, the address pointing register320″ may receive 256 timing information sets.

FIG. 8andFIG. 9are schematic views showing an input wire of a gate driver300of a comparative embodiment and an exemplary embodiment of the invention, respectively, andFIG. 10andFIG. 11are schematic views showing waveforms of an output signal of a gate driver in a comparative embodiment and an exemplary embodiment of the invention, respectively.

Referring toFIG. 8, the gate driver300of the comparative embodiment is connected to 8 input wires11-18that transmit a plurality of scan start signals, e.g., first to fourth scan start signals STV1-STV4, and a plurality of clock control signals, e.g., first to fourth clock control signals CPV1-CPV4, from the outside. The chip size of the gate driver300of the comparative embodiment is generally substantially limited such that the distance between the 8 input wires11-18may be substantially narrow, and coupling capacitance between the input wires11-18may occur. The coupling capacitance between the input wires11-18is increased as the distance between the wires is decreased. As shown inFIG. 10illustrating a waveform of an output signal (e.g., the first gate signal G1) of the gate driver300including the input wires11-18obtained by a simulation, in which the distance between the input wires11-18is set to be narrower from (a) to (d), the waveform of the gate signal G1is distorted when the distance between the input wires is narrow.

Referring toFIG. 9, an exemplary embodiment of the gate driver300is connected to two input wires21and22that transmit the scan start reference signal STVS and the clock control reference signal CPVS from the outside. As shown inFIG. 11illustrating the waveform of the first gate signal G1obtained by a simulation under the same condition of the simulation ofFIG. 9, the waveform of the gate signal G1is substantially maintained when the distance between the wires is substantially narrow.

As described above, in an exemplary embodiment of the invention, the number of the input wires may be substantially reduced such that a margin of the wire width or the distance between the input wires is obtained, and a defect caused by the coupling capacitance is thereby effectively prevented or substantially reduced.