Video matrix display interface

In a video matrix display interface, an interface includes one or more subsystems to receive information from a plurality of display devices, compile the information from the plurality of display devices, report the compiled information to a graphics processing device, generate a video image using the compiled information, the image to be viewable across the plurality of display devices, splice the video image into portions and transmit the video image portions to the plurality of display devices, thereby creating a continuous image across the plurality of display devices.

BACKGROUND

The present disclosure relates generally to information handling systems (IHSs), and more particularly to a video matrix display interface.

It may be beneficial to have a multi-display device IHS to allow the user to view more information/applications, and/or a larger view of the information/applications. However, multi-display solutions are expensive and thus, not common.

Graphics processor units (GPUs) for an IHS may have two display controllers and associated display outputs (e.g., analog and/or digital) to support two display devices. However, to support more than two display devices for an IHS, there are previously two options, dedicated graphics adapters, and dedicated interfaces. For the first option, dedicated graphics processors with at least two graphics processor units provide up to four display outputs. This may be the only option for some applications where four independent display controllers are required. This option is expensive due to a dual-graphics processor unit approach and associated cost with power/thermal challenges. For the second option, dual graphics configurations where two graphics adapters are linked through a dedicated interface can be provided. This is a more scalable approach, but the system-level cost is very high because the platforms have to support two graphics adapters.

Accordingly, it would be desirable to provide an improved video matrix display interface absent the disadvantages discussed above.

SUMMARY

According to one embodiment, a video matrix display interface includes one or more subsystems to receive information from a plurality of display devices, compile the information from the plurality of display devices, report the compiled information to a graphics processing device, generate a video image using the compiled information, the image to be viewable across the plurality of display devices, splice the video image into portions and transmit the video image portions to the plurality of display devices, thereby creating a continuous image across the plurality of display devices.

DETAILED DESCRIPTION

For purposes of this disclosure, an IHS100includes any instrumentality or aggregate of instrumentalities operable to compute, classify, process, transmit, receive, retrieve, originate, switch, store, display, manifest, detect, record, reproduce, handle, or utilize any form of information, intelligence, or data for business, scientific, control, or other purposes. For example, an IHS100may be a personal computer, a network storage device, or any other suitable device and may vary in size, shape, performance, functionality, and price. The IHS100may include random access memory (RAM), one or more processing resources such as a central processing unit (CPU) or hardware or software control logic, read only memory (ROM), and/or other types of nonvolatile memory. Additional components of the IHS100may include one or more disk drives, one or more network ports for communicating with external devices as well as various input and output (I/O) devices, such as a keyboard, a mouse, and a video display. The IHS100may also include one or more buses operable to transmit communications between the various hardware components.

FIG. 1is a block diagram of one IHS100. The IHS100includes a processor102such as an Intel Pentium™ series processor or any other processor available. A memory I/O hub chipset104(comprising one or more integrated circuits) connects to processor102over a front-side bus106. Memory I/O hub104provides the processor102with access to a variety of resources. Main memory108connects to memory I/O hub104over a memory or data bus. A graphics processor110also connects to memory I/O hub104, allowing the graphics processor to communicate, e.g., with processor102and main memory108. Graphics processor110, in turn, provides display signals to a display device112.

Other resources can also be coupled to the system through the memory I/O hub104using a data bus, including an optical drive114or other removable-media drive, one or more hard disk drives116, one or more network interfaces118, one or more Universal Serial Bus (USB) ports120, and a super I/O controller122to provide access to user input devices124, etc. The IHS100may also include a solid state drive (SSDs)126in place of, or in addition to main memory108, the optical drive114, and/or a hard disk drive116. It is understood that any or all of the drive devices114,116, and126may be located locally with the IHS100, located remotely from the IHS100, and/or they may be virtual with respect to the IHS100.

Not all IHSs100include each of the components shown inFIG. 1, and other components not shown may exist. Furthermore, some components shown as separate may exist in an integrated package or be integrated in a common integrated circuit with other components, for example, the processor102and the memory I/O hub104can be combined together. As can be appreciated, many systems are expandable, and include or can include a variety of components, including redundant or parallel resources.

This disclosure provides a solution to couple 3 or more display devices112A,112B and112C to display contiguous content for situations such as, gaming or panoramic viewing. An embodiment of the solution utilizes the signal bandwidth available using the Video Electronics Standards Association (VESA) DisplayPort™, digital display interface standard. The VESA DisplayPort™ standard, Version 1, Revision 1a, released Jan. 11, 2008 and related DisplayPort™ standards are herein incorporated by reference in their entirety.

In an embodiment, the present disclosure may link up three 22 inch wide display devices112A,112B and112C, each having a viewing area of 1680×1050, to display a continuous image across a viewing area of approximately 5040×1050.

Also shown inFIG. 1is a DisplayPort™ interface connection130coupled with the graphics processor110. As commonly understood by one having ordinary skill in the art, an interface connection130is a source device and includes a transmitter (Tx) and couples to a sink device including a DisplayPort™ receiver (Rx) via a main link, and AUX CH and a hot plug detect (HPD) signal line (not shown). The main link is a uni-directional, high-bandwidth, and low latency channel used for transport of isochronous streams, such as uncompressed video and audio. AUX CH is a half-duplex, bidirectional channel used for link management and device control. The HPD signal serves as an interrupt request by a sink device.

The interface connection130couples to a matrix display interface adapter132. The matrix display interface adapter132may be a separate module from the IHS100or may be part of the IHS100. The matrix display interface adapter132is described below with respect toFIG. 4.

The adapter132may include one or more coupling lines coupling the adapter to one or more display devices112A,112B and112C. In an embodiment, the adapter132couples to a DisplayPort™ receiver113A,113B and113C. The display devices112A,112B and112C may include an extended display identification data (EDID) interface140A,140B and140C. EDID is a data structure provided by an display device112,112A,112B and112C to describe its capabilities to a graphics processor110. For example, the EDID information may include manufacturer name, product type, timings supported by the display, display size, luminance data, pixel mapping data, and/or a variety of other features.

FIG. 2illustrates a block diagram of an embodiment of a video matrix display device interface system. In this embodiment, the interface connection130of the graphics processor110couples with the matrix display interface adapter132to receive single audio/video (A/V) signal via a single A/V cable set, splices the signal and communicates the spliced signal to the plurality of display devices112A,112B and112C. The matrix display device interface adapter132may include one or more DisplayPort™ receiver(s) (Rx)134, a splicing engine136and one or more DisplayPort™ transmitters138A,138B and138C.

FIG. 3illustrates a block diagram of an embodiment of a display device calculating system144. The calculating system144receives the EDID information from the EDID interfaces140A,140B and140C. The EDID information passes to an EDID splicer146, up to an EDID summer148, and then to the graphics processor110via the interface connection130. In an embodiment, the EDID calculator144receives the EDID information from the connected display devices112A,112B and112C, calculates new EDID information and transfers that new calculated EDID information to the IHS100so that the IHS100“thinks” that it is transmitting the A/V signals to a new larger display device112. For example, if each of the display devices112A,112B and112C have a display capability of 1680×1050, the new calculated EDID information would report to the IHS100that the display device is a display device having a capability of 5040×1050. Thus the A/V signal sent from the graphics processor110via the Tx is a signal for a 5040×1050 display device112.

FIG. 4illustrates a block diagram of an embodiment of a video matrix display device interface system132. In an embodiment, the EDID information is received from a plurality of slave receivers113A,113B and113C, compiled to appear as a summation of the plurality of viewing sizes of the display devices112A,112B and112C and communicated to the master receiver134. The master receiver134may then communicate the compiled summed viewing size of the plurality of the display devices112A,112B and112C to the graphics processor110.

The splicing engine136receives A/V signals at the receiver (Rx)134from the graphics processor110. The A/V signal is communicated from the Rx134to the splice engine136. The H line data is received into a buffer154. The buffer154conditions the signal and communicates the A/V signal to a first in first out (FIFO) register158and a multiplexer (MUX) and Tx164. The signal is communicated from the buffer154to the MUX164via a main stream protocol communication link156. The A/V signal is also communicated from the FIFO158to the MUX164and/or a counter162. The communication from the FIFO158to the MUX164may be of H line data without stuffing at160. Additionally, the counter162may communicate with the MUX164to communicate a timing signal to the MUX and Tx164. The MUX164may output a portion of the H line signal via each of the transmitters138A,138B and138C to each of the receivers113A,113B and113C.

In an embodiment, the disclosure uses an adaptor kit132which has a receiver134. The A/V signal packets received are parsed by a splicing engine136which then transmits the video content over 3 transmitters138A,138B and138C to each display device112A,112B and112C.

In an embodiment, a general implementation of this disclosure includes a programmable multi-display device solution with single DisplayPort™ controller, that can support dual (e.g., up to 1920×1200 each), triple (e.g., up to 1680×1050 each) or quad (e.g., up to 1440×900 each) display devices112,112A,112B,112C and112D. When two DisplayPort™ controllers are incorporated, which is possible with next-generation graphics adapters, it has the potential to support quad 1920×1200 or eight 1440×900 through single graphics adapter. Combining with dual a graphics configuration, it could support eight 1920×1200 or sixteen 1440×900 for a cost effective video wall solution.

This disclosure includes an opportunity to lead in the multi-display solutions market, while maintaining a low cost of implementation. Additionally, this is achievable without signal compression and may provide an advantage over USB linked displays, which are becoming increasingly popular. The triple-display device solution is suitable for the high-end gaming space and for bundling with gaming platforms. Its can also be generalized to enable cost-effective video wall or digital signage solution (up to 16 screens).