Display unit, drive circuit, driving method, and electronic apparatus

A display unit includes: a pixel circuit including a display element, a first transistor having a gate and a source, and a capacitor inserted between the gate and the source, the first transistor supplying a current to the display element; and a drive section driving the pixel circuit, through sequentially performing first and second driving operations, the first driving operation allowing the drive section to apply a pixel voltage to a first terminal and allowing a second terminal to be at a first voltage, the pixel voltage determining luminance of the display element, the first and second terminals being one and the other of the gate and the source of the first transistor, respectively, and the second driving operation allowing the second terminal to be at a second voltage, through applying the pixel voltage to the first terminal and allowing a current to flow through the first transistor.

BACKGROUND

The present disclosure relates to a display unit that includes a display element of a current-drive type, to a drive circuit and a driving method that are used in such a display unit, and to an electronic apparatus that includes such a display unit.

Recently, in a field of a display unit that performs image display, a display unit that uses a current-drive-type optical device in which light-emission luminance is varied in accordance with a value of a current flowing therethrough, for example, an organic EL (Electro Luminescence) display unit that uses an organic EL device, has been developed and commercialized. The organic EL device is a self-emitting device unlike a liquid crystal device etc. and it is not necessary to use a light source (backlight) therewith. Therefore, the organic EL display unit has properties such as high image visibility, low electric power consumption, and high device response speed, compared to a liquid crystal display unit in which the light source is necessary.

In such a display unit, a drive transistor in each pixel serves as a current source and supplies current to the display element, and thereby the display element emits light. At that time, image quality may be lowered due to variations in devices such as the drive transistors and the organic EL devices. In order to suppress such lowering in image quality, various techniques have been developed. For example, Japanese Unexamined Patent Application Publication No. 2007-171828 discloses a display unit that performs correcting operation for suppressing influence, on image quality, of the variations in devices such as drive transistors and organic EL devices.

SUMMARY

As described above, it has been demanded to suppress the influence of variations in devices on image quality and to improve image quality in the display unit. Also, it is expected to improve the image quality by simple correcting operation.

It is desirable to provide a display unit, a drive circuit, a driving method, and an electronic apparatus that are capable of improving image quality.

According to an embodiment of the present disclosure, there is provided a display unit including: a pixel circuit including a display element, a first transistor having a gate and a source, and a capacitor inserted between the gate and the source of the first transistor, the first transistor supplying a current to the display element; and a drive section driving the pixel circuit, through performing a first driving operation and performing a second driving operation after the first driving operation, the first driving operation allowing the drive section to apply a pixel voltage to a first terminal and allowing a second terminal to be at a first voltage, the pixel voltage determining luminance of the display element, the first terminal being one of the gate and the source of the first transistor, and the second terminal being the other of the gate and the source of the first transistor, and the second driving operation allowing the second terminal to be at a second voltage, through applying the pixel voltage to the first terminal and allowing a current to flow through the first transistor.

According to an embodiment of the present disclosure, there is provided a drive circuit including a drive section, the drive section performing a first driving operation and performing a second driving operation after the first driving operation, the first driving operation allowing the drive section to apply a pixel voltage to a first terminal and allowing a second terminal to be at a first voltage, the pixel voltage determining luminance of a display element, the first terminal being one of a gate and a source of a first transistor, the second terminal being the other of the gate and the source of the first transistor, the first transistor having the gate and the source between which a capacitor is inserted, and the first transistor supplying a current to the display element, and the second driving operation allowing the second terminal to be at a second voltage, through applying the pixel voltage to the first terminal and allowing a current to flow through the first transistor.

According to an embodiment of the present disclosure, there is provided a driving method including: performing a first driving operation and performing a second driving operation after the first driving operation, the first driving operation allowing a pixel voltage to be applied to a first terminal and allowing a second terminal to be at a first voltage, the pixel voltage determining luminance of a display element, the first terminal being one of a gate and a source of a first transistor, the second terminal being the other of the gate and the source of the first transistor, the first transistor having the gate and the source between which a capacitor is inserted, and the first transistor supplying a current to the display element, and the second driving operation allowing the second terminal to be at a second voltage, through applying the pixel voltage to the first terminal and allowing a current to flow through the first transistor.

According to an embodiment of the present disclosure, there is provided an electronic apparatus with a display unit and a control section controlling operation of the display unit, the display unit including: a pixel circuit including a display element, a first transistor having a gate and a source, and a capacitor inserted between the gate and the source of the first transistor, the first transistor supplying a current to the display element; and a drive section driving the pixel circuit, through performing a first driving operation and performing a second driving operation after the first driving operation, the first driving operation allowing the drive section to apply a pixel voltage to a first terminal and allowing a second terminal to be at a first voltage, the pixel voltage determining luminance of the display element, the first terminal being one of the gate and the source of the first transistor, and the second terminal being the other of the gate and the source of the first transistor, and the second driving operation allowing the second terminal to be at a second voltage, through applying the pixel voltage to the first terminal and allowing a current to flow through the first transistor. Examples of the electronic apparatus of the present disclosure may include televisions, digital cameras, personal computers, video camcorders, and personal digital assistants such as mobile phones.

In the display unit, the drive circuit, the driving method, and the electronic apparatus according to the above embodiments of the present disclosure, the first driving operation and the second driving operation are performed and a current is supplied from the first transistor to the display element. At that time, during the first driving operation, the pixel voltage is applied to one of the gate and the source of the first transistor and the voltage at the other of the gate and the source of the first transistor is allowed to be the first voltage. During the second driving operation, the pixel voltage is applied to one of the gate and the source of the first transistor while a current is supplied to the first transistor, and thereby, the voltage at the other of the gate and the source of the first transistor is varied to the second voltage.

According to the display unit, the drive circuit, the driving method, and the electronic apparatus of the above embodiments of the present disclosure, the pixel voltage is applied to one of the gate and the source of the first transistor and driving operation is performed to allow the voltage of the other of the gate and the source of the first transistor to be the first voltage. Thereafter, the pixel voltage is applied to the one of the gate and the source of the first transistor and a current is supplied to the first transistor, and thereby, the voltage at the other of the gate and the source of the first transistor is varied to the second voltage. Therefore, image quality is improved.

DETAILED DESCRIPTION

Some embodiments of the present disclosure will be described below in detail with reference to the drawings. The description will be given in the following order.

1. First Embodiment (an example of Ids correction)

2. Second Embodiment (an example of Ids correction)

3. Third Embodiment (an example of Ids correction)

8. Eighth Embodiment (an example of Ids correction)

9. Ninth Embodiment (an example of Ids correction)

14. Comparison between Schemes

15. Application Examples

1. First Embodiment

Configuration Example

FIG. 1illustrates a configuration example of a display unit according to a first embodiment. A display unit1is a display unit of an active-matrix type that uses an organic EL device. It is to be noted that, since a drive circuit and a driving method according to embodiments of the present disclosure are embodied by the present embodiment, the drive circuit and the driving method according to embodiments of the present disclosure will be described together herein. The display unit1includes a display section10and a drive section20.

The display section10includes a plurality of pixels Pix that are arranged in a matrix. Each pixel Pix includes sub-pixels11of red, green, and blue. Further, the display section10includes a plurality of scanning lines WSL and a plurality of power lines PL that extend in a row direction, and includes a plurality of data lines DTL that extend in a column direction. One end of each of the scanning lines WSL, the power lines PL, and the data lines DTL is connected to the drive section20. Each of the above-described sub-pixels11is arranged at an intersection of the scanning line WSL and the data line DTL.

FIG. 2illustrates an example of a circuit configuration of the sub-pixel11. The sub-pixel11includes a write transistor WSTr, a drive transistor DRTr, an organic EL device OLED, and a capacitor Cs. In other words, in this example, the sub-pixel11has a so-called “2Tr1C” configuration that includes two transistors (the write transistor WSTr and the drive transistor DRTr) and one capacitor Cs.

The write transistor WSTr and the drive transistor DRTr may be configured, for example, of a TFT (Thin Film Transistor) of an N-channel MOS (Metal Oxide Semiconductor) type. The write transistor WSTr has a gate connected to the scanning line WSL, a source connected to the data line DTL, and a drain connected to a gate of the drive transistor DRTr and to a first end of the capacitor Cs. The drive transistor DRTr has the gate connected to the drain of the write transistor WSTr and to the first end of the capacitor Cs, a drain connected to the power line PL, and a source connected to the second end of the capacitor and to an anode of the organic EL device OLED. It is to be noted that a type of the TFT is not specifically limited, and the TFT may have, for example, an inverted-staggered structure (a so-called bottom gate type) or a staggered structure (a so-called top gate type).

The first end of the capacitor Cs is connected to the gate of the drive transistor DRTr and the like, and the second end of the capacitor Cs is connected to the source of the drive transistor DRTr and the like. The organic EL device OLED is a light emitting device that emits light of a color (red, green, or blue) corresponding to each sub-pixel11. The anode of the organic EL device OLED is connected to the source of the drive transistor DRTr and to the second end of the capacitor Cs. To the cathode of the organic EL device OLED, a cathode voltage Vcath is supplied by the drive section20.

The drive section20drives the display section10based on an image signal Sdisp and a synchronization signal Ssync that are supplied from the outside. The drive section20includes an image signal processing section21, a timing generation section22, a scanning line drive section23, a power line drive section26, and a data line drive section27, as shown inFIG. 1.

The image signal processing section21performs a predetermined signal processing on the image signal Sdisp that is supplied from the outside, thereby generating an image signal Sdisp2. Examples of the predetermined signal processing may include gamma correction, over drive correction, etc.

The timing generation section22is a circuit that supplies a control signal to each of the scanning line drive section23, the power line drive section26, and the data line drive section27based on the synchronization signal Ssync that is supplied from the outside, and thereby controlling these sections to operate in synchronization with each other.

The scanning line drive section23sequentially applies scanning signals WS to the plurality of scanning lines WSL in accordance with the control signal supplied from the timing generation section22, thereby sequentially selecting the sub-pixels11for the respective rows.

The power line drive section26sequentially applies power signals DS2to the plurality of power lines PL in accordance with the control signal supplied from the timing generation section22, thereby controlling light emitting operation and light extinction operation of the sub-pixels11for the respective rows. The power signal DS2is varied between a voltage Vccp and a voltage Vini. As will be described later, the voltage Vini is a voltage for initializing the sub-pixel11, and the voltage Vccp is a voltage for applying a current Ids to the drive transistor DRTr and thereby allowing the organic EL device OLED to emit light.

The data line drive section27generates a signal Sig that includes a pixel voltage Vsig that instructs light-emission luminance of each sub-pixel11based on the image signal Sdisp2supplied from the image signal processing section21and the control signal supplied from the timing generation section22, and applies the generated signal Sig to each data line DTL.

With this configuration, as will be described later, the drive section20writes the pixel voltage Vsig in the sub-pixels11and performs correction (Ids correction) for suppressing the influence, on image quality, of device variations in the drive transistors DRTr in one horizontal period. Subsequently, the organic EL device OLED in the sub-pixel11emits light with luminance in accordance with the written pixel voltage Vsig.

The sub-pixel11corresponds to a specific but not limitative example of “pixel circuit” in one embodiment of the present disclosure. The organic EL device OLED corresponds to a specific but not limitative example of “display element” in one embodiment of the present disclosure. The drive transistor DRTr corresponds to a specific but not limitative example of “first transistor” in one embodiment of the present disclosure. The write transistor WSTr corresponds to a specific but not limitative example of “second transistor” in one embodiment of the present disclosure. Drive in a write period P1corresponds to a specific but not limitative example of “first driving operation” in one embodiment of the present disclosure. Drive in an Ids correction period P2corresponds to specific but not limitative example of “second driving operation” in one embodiment of the present disclosure. The voltage Vini corresponds to a specific but not limitative example of “first voltage” in one embodiment of the present disclosure. The voltage Vcc corresponds to a specific but not limitative example of “third voltage” in one embodiment of the present disclosure.

Description will be given of operation and functions of the display unit1of the present embodiment.

First, outline of general operation of the display unit1will be described referring toFIG. 1. The image signal processing section21performs the predetermined signal processing on the image signal Sdisp supplied from the outside, thereby generating the image signal Sdisp2. The timing generation section22supplies the control signal to each of the scanning line drive section23, the power line drive section26, and the data line drive section27based on the synchronization signal Ssync supplied from the outside, thereby controlling these sections to operate in synchronization with each other. The scanning line drive section23sequentially applies the scanning signals WS to the plurality of scanning lines WSL in accordance with the control signal supplied from the timing generation section22, thereby sequentially selecting the sub-pixels11for the respective rows. The power line drive section26sequentially applies the power signals DS2to the plurality of power lines PL in accordance with the control signal supplied from the timing generation section22, thereby controlling the light emitting operation and the light extinction operation of the sub-pixels11for the respective rows. The data line drive section27generates the signal Sig that includes the pixel voltage Vsig corresponding to luminance of each sub-pixel11in accordance with the image signal Sdisp2supplied from the image signal processing section21and the control signal supplied from the timing generation section22, and applies the generated signal Sig to each data line DTL. The display section10performs display based on the scanning signal WS, the power signal DS2, and the signal Sig that are supplied from the drive section20.

Next, detailed operation of the display unit1will be described.

FIG. 3is a timing chart of display operation in the display unit1. This timing chart illustrates an operation example of display drive with respect to certain one of the sub-pixels11which is focused on. InFIG. 3, Part (A) shows a waveform of the scanning signal WS, Part (B) shows a waveform of the power signal DS2, Part (C) shows a waveform of the signal Sig, Part (D) shows a waveform of a gate voltage Vg of the drive transistor DRTr, and Part (E) shows a waveform of a source voltage Vs of the drive transistor DRTr. In Parts (B) to (E) inFIG. 3, the respective waveforms are shown with the use of the same voltage axis.

The drive section20writes the pixel voltage Vsig in the sub-pixel11and initializes the sub-pixel11(write period P1), and performs the Ids correction for suppressing the influence, on image quality, of the device variations in the drive transistors DRTr (Ids correction period P2) in one horizontal period (1H). Thereafter, the organic EL device OLED in the sub-pixel11emits light with luminance in accordance to the written pixel voltage Vsig (light emission period P3). Details thereof will be described below.

First, the drive section20writes the pixel voltage Vsig in the sub-pixel11and initializes the sub-pixel11in a period (write period P1) from timing t1to timing t2. Specifically, first, at the timing t1, the data line drive section27sets the signal Sig to the pixel voltage Vsig (Part (C) inFIG. 3), and the scanning line drive section23allows a voltage of the scanning signal WS to be varied from a low level to a high level (Part (A) inFIG. 3). Accordingly, the write transistor WSTr is turned on, and the gate voltage Vg of the drive transistor DRTr is set to the pixel voltage Vsig (Part (D) inFIG. 3). It is to be noted that the higher voltage Vsig allows the organic EL device OLED to emit light with higher luminance, and the lower voltage Vsig allows the organic EL device OLED to emit light with lower luminance. Further, at the same time, the power line drive section26allows the power signal DS2to be varied from the voltage Vccp to the voltage Vini (Part (B) inFIG. 3). Accordingly, the drive transistor DRTr is turned on, and the source voltage Vs of the drive transistor DRTr is set to the voltage Vini (Part (E) inFIG. 3). Accordingly, a gate-source voltage Vgs (=Vsig−Vini) between the gate and the source of the drive transistor DRTr is set to a voltage higher than a threshold voltage Vth of the drive transistor DRTr, and the sub-pixel11is initialized.

Next, the drive section20performs the Ids correction on the sub-pixel11in a period (Ids correction period P2) from the timing t2to timing t3. Specifically, at the timing t2, the power line drive section26allows the power signal DS2to be varied from the voltage Vini to the voltage Vccp (Part (B) inFIG. 3). Accordingly, the drive transistor DRTr is allowed to operate in a saturation region, and thereby, the current Ids flows from the drain to the source and the source voltage Vs is increased (Part (E) inFIG. 3). At this time, the source voltage Vs is lower than the voltage Vcath at the cathode of the organic EL device OLED. Therefore, the organic EL device OLED retains a reverse bias state and a current does not flow into the organic EL device OLED. It is to be noted that the state of the organic EL device OLED at this time is not limited to the reverse bias state. Alternatively, for example, a current may be prevented from flowing into the organic EL device OLED by setting an operating point of the organic EL device OLED to be equal to or lower than a threshold voltage Vel. Because the source voltage Vs is thus increased, the gate-source voltage Vgs is decreased, and therefore, the current Ids is decreased. With this negative feedback operation, the source voltage Vs is increased in a slower pace over time. A length of the time period (from the timing t2to the timing t3) for performing the Ids correction is determined in order to suppress variations in the current Ids at the timing t3as will be described later.

Subsequently, the drive section20allows the sub-pixel11to emit light in a period (light emission period P3) that begins from the timing t3. Specifically, at the timing t3, the scanning line drive section23allows the voltage of the scanning signal WS to be varied from the high level to the low level (Part (A) inFIG. 3). Accordingly, the write transistor WSTr is turned off, and the gate of the drive transistor DRTr is placed in a floating state. Therefore, after this, the voltage between the terminals of the capacitor Cs, that is, the gate-source voltage Vgs of the drive transistor DRTr is maintained. Further, as the current Ids flows into the drive transistor DRTr, the source voltage Vs of the drive transistor DRTr is increased (Part (E) inFIG. 3), and the gate voltage Vg of the drive transistor DRTr is increased accordingly (Part (D) inFIG. 3). When the source voltage Vs of the drive transistor DRTr becomes higher than a sum (Vel+Vcath) of the threshold voltage Vel and the voltage Vcath of the organic EL device OLED, a current flows between the anode and the cathode of the organic EL device OLED, which allows the organic EL device OLED to emit light. In other words, the source voltage Vs is increased in accordance with the device variations in the organic EL devices OLED, and the organic EL device OLED emits light.

Subsequently, in the display unit1, the transition is made from the light emission period P3to the write period P1after a predetermined period (one frame period) has passed. The drive section20drives the sub-pixel11so that the above-described series of operation is repeated.

As described above, in the Ids correction period P2, the current Ids is flown from the drain to the source of the drive transistor DRTr, and thereby, the source voltage Vs is increased and the gate-source voltage Vgs is gradually decreased. This operation will be described below in detail.

The current Ids that flows from the drain to the source of the drive transistor DRTr is expressed as the following expression.

Ids⁡(t)=β2⁢(Vgs⁡(t)-Vth)2⁢⁢β≡WL·Cox·μ(1)
In the above-described Expression (1), t represents time when the timing t2(FIG. 3) at which the Ids correction begins is used as a reference. Vth represents the threshold voltage of the drive transistor DRTr. W represents a gate width of the drive transistor DRTr. L represents a gate length thereof. Cox represents oxide film capacitance. μ represents mobility.

The current Ids is supplied to the second end of the capacitor Cs, and thereby, the voltage (=Vgs) between the both ends of the capacitor Cs is varied. This behavior is expressed by the following expression.

With the use of Expressions (1) and (2), the following expression concerning the variation in the gate-source voltage Vgs over time is obtained.

Vgs⁡(t)-Vth=11Vgs⁡(0)-Vth+β2⁢⁢Cs·t(3)
In the above-described Expression (3), Vgs(0) is the gate-source voltage Vgs (=Vsig−Vini) at the timing t2.

As described above, in the Ids correction period P2, the gate-source voltage Vgs is decreased gradually over time as shown in Expression (3). Accordingly, the current Ids that flows from the drain to the source of the drive transistor DRTr is also decreased gradually.

FIG. 4illustrates the variation in the current Ids over time upon application of a certain pixel voltage Vsig.FIG. 4illustrates a simulation result in which a case of manufacturing transistors in a plurality of different process conditions is assumed. As shown inFIG. 4, the current Ids is decreased gradually over time. At that time, the variation in the current Ids over time differs between the transistors depending on the process conditions. Specifically, for example, the current Ids may be decreased faster when a value of the current Ids is large (when the mobility μ is large and the threshold value Vth is small), and the current Ids may be decreased slower when the value of the current Ids is small (when the mobility μ is small and the threshold value Vth is large).

FIG. 5illustrates time dependency of the variations in the current Ids shown inFIG. 4. The characteristics W1indicate a value (σ/ave.) that is obtained by dividing standard deviation by an average value. The characteristics W2indicate a value (Range/ave.) that is obtained by dividing a variation value by the average value. As shown inFIG. 5, the variations in the current Ids have a local minimum value at a certain time t (for example, at time tw in the characteristics W2). Accordingly, the width of variations in the current Ids is minimized when the Ids correction is performed for a time period of tw.

In the display unit1, as described above, the time length (inFIG. 3, from the timing t2to the timing t3) of the Ids correction period P2is set to be the time length (for example, the time period of tw) that allows the variations in the current Ids to be small. Accordingly, the variations in the current Ids at the timing t3are suppressed. Therefore, degradation in image quality is suppressed.

Moreover, in the display unit1, the Ids correction is completed before the current Ids is converged to “0 (zero)”. Therefore, the period (Ids correction period P2) used for the correction operation is allowed to be shorter compared to in a correction method (for example, Vth correction described in a fourth embodiment) which will be described later. Accordingly, design freedom of the display unit1is increased. Specifically, for example, a high-definition display unit may be achieved with the use of the display unit1. In particular, in the high-definition display unit, it is necessary to perform correction operation in a shorter time period since one horizontal period (1H) becomes shorter in accordance with increase in the number of lines. In the display unit1, the correction operation is allowed to be performed in a short time period. Therefore, the high-definition display unit is achievable.

As described above, in the present embodiment, the Ids correction is performed. Therefore, degradation in image quality resulting from the device variations in the drive transistors is suppressed.

Moreover, in the present embodiment, the correction is completed before the current Ids is converged to “0 (zero)” in the Ids correction period. Therefore, the period used for the correction operation is allowed to be short. Accordingly, design freedom is increased. For example, a high-definition display unit may be achievable.

Moreover, in the present embodiment, the source voltage is increased in accordance with the device variations in the organic EL devices. Therefore, degradation in image quality resulting from the device variations in the organic EL device is suppressed.

In the above-described embodiment, the sub-pixel11includes two transistors and one capacitor Cs. However, this is not limitative. Alternatively, for example, the sub-pixel may include three transistors and one capacitor Cs. The present modification will be described below in detail.

FIG. 6illustrates a configuration example of a display unit1A according to the present modification. The display unit1A includes a display section10A and a drive section20A. The display section10A includes a plurality of sub-pixels11A and a plurality of power control lines DSL that extend in the row direction. One end of each of the power control lines DSL is connected to the drive section20A.

FIG. 7illustrates an example of a circuit configuration of the sub-pixel11A. The sub-pixel11A includes a power transistor DSTr. In other words, in this example, the sub-pixel11A has a so-called “3Tr1C” configuration that includes three transistors (the write transistor WSTr, the drive transistor DRTr, and the power transistor DSTr) and one capacitor Cs. The power transistor DSTr is configured of a TFT of a P-channel MOS type. A gate of the power transistor DSTr is connected to the power control line DSL, a source thereof is connected to the power line PL, and a drain thereof is connected to the drain of the drive transistor DRTr.

The power transistor DSTr corresponds to a specific but not limitative example of “third transistor” in one embodiment of the present disclosure.

The drive section20A includes a timing generation section22A, a scanning line drive section23A, a power control line drive section25A, a power line drive section26A, and a data line drive section27A. The timing generation section22A is a circuit that supplies a control signal to each of the scanning line drive section23A, the power control line drive section25A, the power line drive section26A, and the data line drive section27A based on the synchronization signal Ssync that is supplied from the outside, and thereby controlling these sections to operate in synchronization with each other. The power control line drive section25A sequentially applies power control signals DS to the plurality of power control lines DSL in accordance with the control signal supplied from the timing generation section22A, thereby controlling light emitting operation and light extinction operation of the sub-pixels11A for the respective rows. The scanning line drive section23A, the power line drive section26A, and the data line drive section27A have functions similar to those of the scanning line drive section23, the power line drive section26, and the data line drive section27according to the above-described embodiment, respectively.

FIG. 8is a timing chart of display operation in the display unit1A. InFIG. 8, Part (A) shows the waveform of the scanning signal WS, Part (B) shows a waveform of the power control signal DS, Part (C) shows a waveform of the power signal DS2, Part (D) shows the waveform of the signal Sig, Part (E) shows the waveform of the gate voltage Vg of the drive transistor DRTr, and Part (F) shows the waveform of the source voltage Vs of the drive transistor DRTr.

First, the drive section20A writes the pixel voltage Vsig in the sub-pixel11A and initializes the sub-pixel11A in a period (write period P1) from the timing t1to timing t6, as in the above-described embodiment.

Next, at the timing t6, the power control line drive section25A allows the power control signal DS to be varied from a low level to a high level (Part (B) inFIG. 8). Accordingly, the power transistor DSTr is turned off, and supply of the voltage Vini to the source of the drive transistor DRTr is completed. Further, at the timing t2, the power line drive section26A allows the power signal DS2to be varied from the voltage Vini to the voltage Vccp (Part (C) inFIG. 8) as in the above-described embodiment. Thereafter, at timing t7, the power control line drive section25A allows the power control signal DS to be varied from the high level to the low level (Part (B) inFIG. 8). Accordingly, the power transistor DSTr is turned on, and the voltage Vccp is supplied to the drain of the drive transistor DRTr.

Subsequently, the drive section20A performs the Ids correction on the sub-pixel11A in a period (Ids correction period P2) from the timing t7to the timing t3, as in the above-described first embodiment.

Effects similar to those in the above-described embodiment are obtainable also in such a configuration.

In the above-described first embodiment, the sub-pixel11is initialized by supplying the voltage Vini by the power line drive section26. However, this is not limitative. Alternatively, for example, a transistor used only to supply the voltage Vini may be provided. The present modification will be described below in detail.

FIG. 9illustrates a configuration example of a display unit1B according to the present modification. The display unit1B includes a display section10B and a drive section20B. The display section10B includes a plurality of sub-pixels11B and a plurality of control lines AZ1L that extend in the row direction. One end of each of the control lines AZ1L is connected to the drive section20B.

FIG. 10illustrates an example of a circuit configuration of the sub-pixel11B. The sub-pixel11B includes a control transistor AZ1Tr. In other words, in this example, the sub-pixel11B has a so-called “4Tr1C” configuration that includes four transistors (the write transistor WSTr, the drive transistor DRTr, the power transistor DSTr, and the control transistor AZ1Tr) and one capacitor Cs. The control transistor AZ1Tr is configured of a TFT of an N-channel MOS type. A gate of the control transistor AZ1Tr is connected to the control line AZ1L, a drain thereof is connected to the source of the drive transistor DRTr and to the second end of the capacitor Cs, and a source thereof is supplied with the voltage Vini by the drive section20B. Further, the voltage Vccp is supplied to the source of the power transistor DSTr by the drive section20B.

Here, the control transistor AZ1Tr corresponds to a specific but not limitative example of “fourth transistor” in one embodiment of the present disclosure.

The drive section20B includes a timing generation section22B, a scanning line drive section23B, a control line drive section24B, a power control line drive section25B, and a data line drive section27B. The timing generation section22B is a circuit that supplies a control signal to each of the scanning line drive section23B, the control line drive section24B, the power control line drive section25B, and the data line drive section27B based on the synchronization signal Ssync that is supplied from the outside, and thereby controlling these sections to operate in synchronization with each other. The control line drive section24B sequentially applies control signals AZ1to the plurality of control lines AZ1L in accordance with the control signal supplied from the timing generation section22B, thereby controlling initialization operation of the sub-pixels11B for the respective rows. The scanning line drive section23B, the power control line drive section25B, and the data line drive section27B have functions similar to those of the scanning line drive section23, the power control line drive section25A, and the data line drive section27, respectively.

FIG. 11is a timing chart of display operation in the display unit1B. InFIG. 11, Part (A) shows the waveform of the scanning signal WS, Part (B) shows a waveform of the control signal AZ1, Part (C) shows the waveform of the power control signal DS, Part (D) shows the waveform of the signal Sig, Part (E) shows the waveform of the gate voltage Vg of the drive transistor DRTr, and Part (F) shows the waveform of the source voltage Vs of the drive transistor DRTr.

First, at timing t11prior to the write period P1, the power control line drive section25B allows a voltage of the power control signal DS to be varied from a low level to a high level (Part (C) inFIG. 11). Accordingly, the power transistor DSTr is turned off.

Next, the drive section20B writes the pixel voltage Vsig in the sub-pixel11B in a period (write period P1) from timing t12to timing t13, as in the above-described first embodiment. Further, at the timing t12, the control line drive section24B allows a voltage of the control signal AZ1to be varied from a low level to a high level (Part (B) inFIG. 11). Accordingly, the control transistor AZ1Tr is turned on, and the source voltage Vs of the drive transistor DRTr is set to the voltage Vini (Part (F) inFIG. 11). Thus, the sub-pixel11B is initialized.

Subsequently, at the timing t13, the control line drive section24B allows the voltage of the control signal AZ1to be varied from the high level to the low level (Part (B) inFIG. 11). Accordingly, the control transistor AZ1Tr is turned off, and the supply of the voltage Vini to the source of the drive transistor DRTr is completed.

Subsequently, the drive section20B performs the Ids correction on the sub-pixel11B in a period (Ids correction period P2) from timing t14to timing t15. Specifically, at the timing t14, the power control line drive section25B allows the voltage of the power control signal DS to be varied from a high level to a low level (Part (C) inFIG. 11). Accordingly, the power transistor DSTr is turned on, and the Ids correction is performed as in the above-described first embodiment.

Effects similar to those in the above-described embodiment are obtainable also in such a configuration.

In the above-described first embodiment, the sub-pixel11includes two transistors. However, this is not limitative. Alternatively, for example, the sub-pixel may further include other transistors.

For example, a method (FIG. 3) of driving the display section10(FIGS. 1 and 2) that includes the sub-pixel11having the “2Tr1C” configuration may be applied as it is to the display section10A (FIGS. 6 and 7) that includes the sub-pixel11A having the “3Tr1C” configuration. In this case, the same method as the driving method shown inFIG. 3is achievable by allowing the power control signal DS to be mostly at the low level (L) (Part (B) inFIG. 12) and allowing the power transistor DSTr to be mostly ON, as shown inFIG. 12.

Moreover, for example, the method (FIG. 3) of driving the display section10(FIGS. 1 and 2) that includes the sub-pixel11having the “2Tr1C” configuration may be applied as it is to a display section that includes a sub-pixel having the “4Tr1C” configuration. Details thereof will be described below.

FIG. 13illustrates a configuration example of a display unit1C according to the present modification. The display unit1C includes a display section10C and a drive section20C. The display section10C includes a plurality of sub-pixels11C and a plurality of control lines AZ2L that extend in the row direction. One end of each of the control lines AZ2L is connected to the drive section20C.

FIG. 14illustrates an example of a circuit configuration of the sub-pixel11C. The sub-pixel11C includes a control transistor AZ2Tr. In other words, in this example, the sub-pixel11C has the so-called “4Tr1C” configuration that includes four transistors (the write transistor WSTr, the drive transistor DRTr, the power transistor DSTr, and the control transistor AZ2Tr) and one capacitor Cs. The control transistor AZ2Tr is configured of a TFT of an N-channel MOS type. A gate of the control transistor AZ2Tr is connected to the control line AZ2L, a drain thereof is connected to the gate of the drive transistor DRTr and to the first end of the capacitor Cs, and a source thereof is supplied with a voltage Vofs by the drive section20C. Further, the source of the power transistor DSTr is connected to the power line PL.

The drive section20C includes a timing generation section22C, a scanning line drive section23C, a control line drive section24C, a power control line drive section25C, a power line drive section26C, and a data line drive section27C. The timing generation section22C is a circuit that supplies a control signal to each of the scanning line drive section23C, the control line drive section24C, the power control line drive section25C, the power line drive section26C, and the data line drive section27C based on the synchronization signal Ssync that is supplied from the outside, and thereby controlling these sections to operate in synchronization with each other. The control line drive section24C sequentially applies control signals AZ2to the plurality of control lines AZ2L in accordance with the control signal supplied from the timing generation section22C. The scanning line drive section23C, the power control line drive section25C, the power line drive section26C, and the data line drive section27C have functions similar to those of the scanning line drive section23, the power control line drive section25A, the power line drive section26, and the data line drive section27, respectively.

Also in such a configuration, the same method as the driving method shown inFIG. 3is achievable by allowing the control signal AZ2to be mostly at the low level (L) (Part (B) inFIG. 15), allowing the power control signal DS to be mostly at the low level (L) (Part (C) inFIG. 15) and allowing the control transistor AZ2Tr to be mostly OFF, and allowing the power transistor DSTr to be mostly ON, as shown inFIG. 15.

Moreover, for example, the method (FIG. 8) of driving the display section10A (FIGS. 6 and 7) that includes the sub-pixel11A having the “3Tr1C” configuration may be applied as it is to the display section10C (FIGS. 13 and 14) that includes the sub-pixel11C having the “4Tr1C” configuration. In this case, the same method as the driving method shown inFIG. 8is achievable, by allowing the control signal AZ2to be mostly at the low level (L) (Part (B) inFIG. 16) and allowing the control transistor AZ2Tr to be mostly OFF, as shown inFIG. 16.

Moreover, for example, the method (FIG. 11) of driving the display section10B (FIGS. 9 and 10) that includes the sub-pixel11B having the “4Tr1C” configuration may be applied as it is to the display section that includes a sub-pixel having a “5Tr1C” configuration. Details thereof will be described below.

FIG. 17illustrates a configuration example of a display unit1D according to the present modification. The display unit1D includes a display section10D and a drive section20D. The display section10D includes a plurality of sub-pixels11D and the plurality of control lines AZ1L and AZ2L that extend in the row direction. One end of each of the control lines AZ1L and AZ2L is connected to the drive section20D.

FIG. 18illustrates an example of a circuit configuration of the sub-pixel11D. The sub-pixel11D includes the control transistors AZ1Tr and AZ2Tr. In other words, in this example, the sub-pixel11D has the so-called “5Tr1C” configuration that includes five transistors (the write transistor WSTr, the drive transistor DRTr, the power transistor DSTr, and the control transistors AZ1Tr and AZ2Tr) and one capacitor Cs.

The drive section20D includes a timing generation section22D, a scanning line drive section23D, a control line drive section24D, a power control line drive section25D, and a data line drive section27D. The timing generation section22D is a circuit that supplies a control signal to each of the scanning line drive section23D, the control line drive section24D, the power control line drive section25D, and the data line drive section27D based on the synchronization signal Ssync that is supplied from the outside, and thereby controlling these sections to operate in synchronization with each other. The control line drive section24D sequentially applies the control signals AZ1to the plurality of control lines AZ1L, and sequentially applies the control signals AZ2to the plurality of control lines AZ2L, in accordance with the control signal supplied from the timing generation section22D. The scanning line drive section23D, the power control line drive section25D, and the data line drive section27D have functions similar to those of the scanning line drive section23, the power control line drive section25A, and the data line drive section27, respectively.

Also in such a configuration, the same method as the driving method shown inFIG. 11is achievable by allowing the control signal AZ2to be mostly at the low level (L) (Part (C) inFIG. 19), and allowing the control transistor AZ2Tr to be mostly OFF, as shown inFIG. 19.

In the above-described embodiment, the sub-pixels11that are adjacent to each other in the row direction are connected to different data lines DTL. However, this is not limitative. Alternatively, for example, the adjacent sub-pixels11may share one data line DTL. Description will be given below in detail of a display unit1E and a display unit1F according to the present modification.

FIG. 20illustrates a configuration example of a display section10E in the display unit1E. In the display section10E, the sub-pixels11that are adjacent to each other in the row direction are connected to one data line DTL. Moreover, the display section10E includes two scanning lines WSL and two power lines PL for each row.

FIG. 21is a timing chart of display operation in the display unit1E. This timing chart illustrates an operation example of display drive with respect to the two sub-pixels11that are adjacent to each other in the row direction. InFIG. 21, Parts (A) to (E) illustrate operation example of one of the two sub-pixels11, and Parts (F) to (J) illustrate operation example of the other. Parts (A) and (F) each show the waveform of the scanning signal WS, Parts (B) and (G) each show the waveform of the power signal DS2, Parts (C) and (H) each show the waveform of the signal Sig, Parts (D) and (I) each show the waveform of the gate voltage Vg of the drive transistor DRTr, and Parts (E) and (J) each show the waveform of the source voltage Vs of the drive transistor DRTr.

In the display unit1E, the pixel voltage Vsig is written in the two sub-pixels11that are adjacent to each other in the row direction and the Ids correction is performed in one horizontal period (1H). Specifically, the writing operation (write period P1) and the Ids correction operation (Ids correction period P2) are performed on one of the two sub-pixels11in a first half of the one horizontal period (1H), and the writing operation (write period P1) and the Ids correction operation (Ids correction period P2) are performed on the other of the two sub-pixels11in a second half of the horizontal period (1H).

FIG. 22Aillustrates operation of the respective sub-pixels11in the first half of one horizontal period (1H).FIG. 22Billustrates operation of the respective sub-pixels11in the second half of the one horizontal period (1H). InFIGS. 22A and 22B, the hatched sub-pixels11represent the sub-pixels11on which the writing operation and the Ids correction are performed. In this example, the sub-pixels11in every other row are driven in each of the first and second halves of the one horizontal period (1H).

As described above, in the display unit1E, the Ids correction period is short. Therefore, the writing operation and the Ids correction operation are allowed to be performed on the plurality of sub-pixels11in a time-divisional manner in one horizontal period (1H).

In the above-described example, the scanning lines WSL and the power lines PL are connected to the sub-pixels11in the same manner in the respective rows. However, this is not limitative. Alternatively, for example, the scanning lines WSL and the power lines PL may be connected to the sub-pixels11in manners different between the respective rows as shown inFIG. 23. In this case, as shown inFIGS. 24A and 24B, the sub-pixels11are driven in a checkerboard-like pattern in the respective first and second halves of one horizontal period (1H).

Moreover, in the above-described example, two power lines PL are included in each row. However, this is not limitative. Alternatively, for example, as shown inFIG. 25, one power line PL may be included in each row. In this case, as shown inFIG. 26, the two sub-pixels11that are adjacent to each other in the row direction may operate based on the common power signal DS2(Parts (B) and (G) inFIG. 26). The voltage of the power signal DS2becomes the voltage Vini in each of the write period P1of each of the two sub-pixels11in one horizontal period (1H).

2. Second Embodiment

Next, a display unit2according to a second embodiment will be described. In the present embodiment, a voltage of a falling part of the waveform of the scanning signal WS is gradually decreased. It is to be noted that the same numerals are used to designate substantially the same components of the display unit1according to the above-described first embodiment, and the description thereof will be appropriately omitted.

As shown inFIG. 1, the display unit2includes a drive section30. The drive section30includes a scanning line drive section33. The scanning line drive section33sequentially applies the scanning signals WS to the plurality of scanning lines WSL in accordance with the control signal supplied from the timing generation section22, thereby sequentially selecting the sub-pixels11for the respective rows, as with the scanning line drive section23according to the above-described first embodiment. At that time, the scanning line drive section33applies, to the scanning line WSL, the scanning signal WS that has a waveform in which the voltage of the falling part is decreased gradually.

FIG. 27is a timing chart of display operation in the display unit2. InFIG. 27, Part (A) shows the waveform of the scanning signal WS, Part (B) shows the waveform of the power signal DS2, Part (C) shows the waveform of the signal Sig, Part (D) shows the waveform of the gate voltage Vg of the drive transistor DRTr, and Part (E) shows the waveform of the source voltage Vs of the drive transistor DRTr.

First, the drive section30writes the pixel voltage Vsig in the sub-pixel11and initializes the sub-pixel11in the period (write period P1) from the timing t1to the timing t2, as in the above-described first embodiment.

Next, the drive section30performs the Ids correction on the sub-pixel11in a period (Ids correction period P2) from the timing t2to timing t9, as with the drive section20according to the above-described first embodiment. At that time, the scanning line drive section33generates the scanning signal WS that has the waveform in which the voltage of the falling part is decreased gradually (Part (A) inFIG. 27). Thus, the display unit2so operates as to allow the time length (from the timing t2to the timing t9) of the Ids correction period P2to be different depending on the level of the pixel voltage Vsig.

FIG. 28is a timing chart of the Ids correction operation. Part (A) shows the waveform of the scanning signal WS, and Part (B) shows the waveform of the power signal DS2. The write transistor WSTr is turned on when the voltage of the scanning signal WS is higher than (the pixel voltage Vsig+the threshold voltage Vth), and is turned off when the voltage of the scanning signal WS is lower than (the pixel voltage Vsig+the threshold voltage Vth). As shown in Part (A) inFIG. 28, the voltage of the scanning signal WS is decreased gradually upon falling. Therefore, the timing t9at which the write transistor WSTr is switched from the ON state to the OFF state depends on the level of the pixel voltage Vsig. In other words, the time length of the Ids correction period P2depends on the level of the pixel voltage Vsig. Specifically, the time period of the Ids correction period P2becomes shorter as the level of the pixel voltage Vsig is increased, and becomes longer as the level of the pixel voltage Vsig is decreased.

After the Ids correction is completed, the drive section30allows the sub-pixel11to emit light in a period (light emission period P3) that begins from the timing t9, as in the above-described first embodiment.

As described above, in the display unit2is so configured that the voltage of the falling part of the waveform of the scanning signal WS is decreased gradually. Accordingly, image quality is improved as will be described below.

As shown inFIGS. 4 and 5, the variations in the current Ids has the local minimum value at a certain time t (for example, at time tw in the characteristics W2). The time period during which the variations in the current Ids take the local minimum value is varied in accordance with the pixel voltage Vsig.

FIG. 29illustrates a relationship between the pixel voltage Vsig and the time period during which the variations in the current Ids takes the local minimum value. As shown inFIG. 29, the time period during which the variations in the current Ids take the local minimum value is shorter as the pixel voltage Vsig is higher and is longer as the pixel voltage Vsig is lower. Accordingly, when the time period of the Ids correction period P2is reduced as the pixel voltage Vsig is higher and is increased as the pixel voltage Vsig is lower, the variations in the current Ids at the timing t9is suppressed independently of the pixel voltage Vsig.

In the display unit2, the voltage of the falling part of the scanning signal WS is decreased gradually in order to vary the time length of the Ids correction period P2in accordance with the pixel voltage Vsig as described above. Specifically, the waveform of the falling part of the scanning signal WS is generated so that the characteristics shown inFIG. 29are achieved. Accordingly, the variations in the current Ids are suppressed independently of the level of the pixel voltage Vsig, and thereby, degradation in image quality is suppressed.

It is to be noted that a method of generating such a waveform of the scanning signal WS is disclosed, for example, in Japanese Unexamined Patent Application Publication No. 2008-9198.

As described above, in the present embodiment, the voltage of the falling part of the scanning signal is decreased gradually. Therefore, degradation in image quality is suppressed. Other effects are similar to those in the above-described first embodiment.

In the above-described second embodiment, the scanning line drive section33that allows the voltage of the falling part of the scanning signal WS to be decreased gradually is applied to the display unit1according to the first embodiment. However, this is not limitative. Alternatively, for example, the scanning line drive section33may be applied to any of the display units according to Modifications 1-1 to 1-4 of the first embodiment.

Next, a display unit3according to a third embodiment will be described. The present embodiment is different from the display unit1according to the above-described first embodiment and the like in the specific method of the Ids correction. Specifically, in the display unit1, the pixel voltage Vsig is applied to the gate of the drive transistor DRTr, and the source voltage is varied by the Ids correction. On the other hand, in the display unit3according to the present embodiment, the pixel voltage Vsig is applied to the source of the drive transistor, and the gate voltage is varied by the Ids correction. It is to be noted that the same numerals are used to designate substantially the same components of the display unit1according to the above-described first embodiment, and the description thereof will be appropriately omitted.

FIG. 30illustrates a configuration example of the display unit3according to the present embodiment. The display unit3includes a display section40and a drive section50.

The display section40includes a plurality of sub-pixels41, the scanning lines WSL, the power control lines DSL, control lines INISL and AZL, and the data lines DTL. The scanning lines WSL, the power control lines DSL, and the control lines INISL and AZL extend in the row direction. The data lines DTL extend in the column direction. One end of each of the scanning lines WSL, the power control lines DSL, the control lines INISL and AZL, and the data lines DTL is connected to the drive section50.

FIG. 31illustrates an example of a circuit configuration of the sub-pixel41. The sub-pixel41includes a write transistor Tr1, a drive transistor Tr2, control transistors Tr3and Tr4, power transistors Tr5and Tr6, the organic EL device OLED, and the capacitor Cs. In other words, in this example, the sub-pixel41has a so-called “6Tr1C” configuration that includes six transistors (the write transistor Tr1, the drive transistor Tr2, the control transistors Tr3and Tr4, the power transistors Tr5and Tr6) and one capacitor Cs.

The write transistor Tr1, the drive transistor Tr2, the control transistors Tr3and Tr4, and the power transistors Tr5and Tr6may each be configured, for example, of a TFT of a P-channel MOS type. A gate of the write transistor Tr1is connected to the scanning line WSL, a source thereof is connected to the data line DTL, and a drain thereof is connected to a source of the drive transistor Tr2, the first end of the capacitor Cs, and the like. A gate of the drive transistor Tr2is connected to the second end of the capacitor Cs and the like, the source thereof is connected to the drain of the write transistor Tr1, the first end of the capacitor Cs, and the like, and the drain thereof is connected to a drain of the control transistor Tr3and a source of the power transistor Tr5. A gate of the control transistor Tr3is connected to the control line AZL, a source thereof is connected to the second end of the capacitor Cs, the gate of the drive transistor Tr2and the like, and the drain thereof is connected to the drain of the drive transistor Tr2and the source of the power transistor Tr5. A gate of the control transistor Tr4is connected to the control line INISL, a source thereof is connected to the second end of the capacitor Cs, the gate of the drive transistor Tr2, and the like, and a drain thereof is supplied with the voltage Vini by the drive section50. A gate of the power transistor Tr5is connected to the power control line DSL, the source thereof is connected to the drain of the drive transistor Tr2and the drain of the control transistor Tr3, and a drain thereof is connected to the anode of the organic EL device OLED. A gate of the power transistor Tr6is connected to the power control line DSL, a source thereof is supplied with the voltage Vccp by the drive section50, and a drain thereof is connected to the first end of the capacitor Cs, the source of the drive transistor Tr2, and the like.

The first end of the capacitor Cs is connected to the source of the drive transistor Tr2and the like, and the second end thereof is connected to the gate of the drive transistor Tr2and the like. The anode of the organic EL device OLED is connected to the drain of the power transistor Tr5, and the cathode thereof is supplied with the cathode voltage Vcath by the drive section50.

The drive transistor Tr2corresponds to a specific but not limitative example of “first transistor” in one example of the present disclosure. The write transistor Tr1corresponds to a specific but not limitative example of “sixth transistor” in one example of the present disclosure. The control transistor Tr3corresponds to a specific but not limitative example of “seventh transistor” in one example of the present disclosure. The control transistor Tr4corresponds to a specific but not limitative example of “eighth transistor” in one example of the present disclosure. The power transistor Tr5corresponds to a specific but not limitative example of “ninth transistor” in one example of the present disclosure. The power transistor Tr6corresponds to a specific but not limitative example of “tenth transistor” in one example of the present disclosure.

The drive section50drives the display section40based on the image signal Sdisp and the synchronization signal Ssync that are supplied from the outside, as with the drive section20according to the above-described first embodiment. The drive section50includes an image signal processing section51, a timing generation section52, a scanning line drive section53, a control line drive section54, a power control line drive section55, and a data line drive section57. The control line drive section54sequentially applies control signals INIS to the plurality of control lines INISL in accordance with a control signal supplied from the timing generation section52, thereby controlling initialization operation of the sub-pixels41for the respective rows. Also, the control line drive section54sequentially applies control signals AZ to the plurality of control lines AZL in accordance with the control signal supplied from the timing generation section52, thereby controlling the Ids correction operation of the sub-pixels41for the respective rows.

FIG. 32is a timing chart of display operation in the display unit3. InFIG. 32, Part (A) shows a waveform of the control signal INIS, Part (B) shows the waveform of the scanning signal WS, Part (C) shows the waveform of the power control signal DS, Part (D) shows a waveform of the control signal AZ, Part (E) shows the waveform of the signal Sig, Part (F) shows a waveform of a gate voltage Vg of the drive transistor Tr2, and Part (G) shows a waveform of a source voltage Vs of the drive transistor Tr2.

First, the drive section50writes the pixel voltage Vsig in the sub-pixel41and initializes the sub-pixel41in a period (write period P1) from timing t21to timing t22. Specifically, first, at the timing t11, the data line drive section57sets the signal Sig to the pixel voltage Vsig (Part (E) inFIG. 32), and the scanning line drive section53allows the voltage of the scanning signal WS to be varied from a high level to a low level (Part (B) inFIG. 32). Accordingly, the write transistor Tr1is turned on, and the source voltage Vs of the drive transistor Tr2is set to the pixel voltage Vsig (Part (G) inFIG. 32). At the same time, the control line drive section54allows a voltage of the control signal INIS to be varied from a high level to a low level (Part (A) inFIG. 32). Accordingly, the control transistor Tr4is turned on, and the gate voltage Vg of the drive transistor Tr2is set to the voltage Vini (Part (F) inFIG. 32). Thus, the sub-pixel41is initialized.

Next, the drive section50performs the Ids correction on the sub-pixel41in a period (Ids correction period P2) from the timing t22to timing t23. Specifically, first, at the timing t22, the control line drive section54allows the voltage of the control signal INIS to be varied from the low level to the high level (Part (A) inFIG. 32). Accordingly, the control transistor Tr4is turned off. Further, at the same time, the control line drive section54allows the voltage of the control signal AZ to be varied from a high level to a low level (Part (D) inFIG. 32). Accordingly, the control transistor Tr3is turned on. In other words, the drain and the gate of the drive transistor Tr2are connected to each other through the control transistor Tr3(a so-called “diode connection”). Accordingly, a current is flown from the source to the drain of the drive transistor Tr2, and thereby, the gate voltage Vg is increased (Part (F) inFIG. 32). Because the gate voltage Vg is thus increased, a current flown from the source to the drain of the drive transistor Tr2is decreased. With this negative feedback operation, the gate voltage Vg is increased in a slower pace over time. A length of the time period (from the timing t22to the timing t23) for performing this Ids correction is determined in order to suppress variations in the current that flows through the drive transistor Tr2at the timing t23as described in the above first embodiment.

Subsequently, at the timing t23, the control line drive section54allows the voltage of the control signal AZ to be varied from the low level to the high level (Part (D) inFIG. 32). Accordingly, the control transistor Tr3is turned off, and the gate of the drive transistor Tr2is placed in a floating state. Thereafter, the voltage between the terminals of the capacitor Cs, that is, a gate-source voltage Vgs between the gate and the source of the drive transistor Tr2is maintained.

Subsequently, at timing t24, the scanning line drive section53allows the voltage of the scanning signal WS to be varied from the low level to the high level (Part (B) inFIG. 32). Accordingly, the write transistor Tr1is turned off.

Subsequently, the drive section50allows the sub-pixel41to emit light in a period (light emission period P3) that begins from timing t25. Specifically, at the timing t25, the power control line drive section55allows the voltage of the power control signal DS to be varied from a high level to a low level (Part (C) inFIG. 32). Accordingly, the power transistors Tr5and Tr6are turned on, and thereby, the source voltage Vs of the drive transistor Tr2is increased toward the voltage Vccp (Part (G) inFIG. 32) and the gate voltage Vg of the drive transistor Tr2is also increased (Part (F) inFIG. 32). Accordingly, the drive transistor Tr2is allowed to operate in a saturation region, and a current is flown through a path including the power transistor Tr6, the drive transistor Tr2, the power transistor Tr5, and the organic EL device OLED in order. Accordingly, the organic EL device OLED emits light.

Subsequently, in the display unit3, the transition is made from the light emission period P3to the write period P1after a predetermined period (one frame period) has passed. The drive section50drives the sub-pixel41so that the above-described series of operation is repeated.

As described above, effects similar to those in the above-described embodiments and the like are obtainable also when the pixel voltage is applied to the source of the drive transistor and the gate voltage is varied by the Ids correction.

Moreover, in the present embodiment, the display section40is configured only of a PMOS transistor without using an NMOS transistor. Therefore, the display section40may be manufactured, for example, even in a process in which the NMOS transistor is not allowed to be manufactured, such as in an organic TFT (O-TFT) process.

For example, Modification 1-4 according to the first embodiment may be applied to the display unit3according to the above-described third embodiment.

Next, a display unit6according to a fourth embodiment will be described. The present embodiment is different from the display unit1according to the above-described first embodiment and the like in a correction method. It is to be noted that the same numerals are used to designate substantially the same components of the display unit1according to the above-described first embodiment, and the description thereof will be appropriately omitted.

As shown inFIGS. 1 and 2, the display unit6includes the display section10and a drive section60. The display section10includes the sub-pixels11having the “2Tr1C” configuration. The drive section60includes a scanning line drive section63, a power line drive section66, and a data line drive section67.

FIG. 33is a timing chart of display operation in the display unit6. InFIG. 33, Part (A) shows the waveform of the scanning signal WS, Part (B) shows the waveform of the power signal DS2, Part (C) shows the waveform of the signal Sig, Part (D) shows the waveform of the gate voltage Vg of the drive transistor DRTr, and Part (E) shows the waveform of the source voltage Vs of the drive transistor DRTr.

The drive section60initializes the sub-pixel11(initialization period P11), performs Vth correction for suppressing the influence, on image quality, of the device variations in the drive transistors DRTr (Vth correction period P12), writes the pixel voltage Vsig in the sub-pixel11, and performs μ (mobility) correction that is different from the above-described Vth correction (write-μ-correction period P13), in one horizontal period (1H). Thereafter, the organic EL device OLED in the sub-pixel11emits light with luminance in accordance with the written pixel voltage Vsig (light emission period P16). Details thereof will be described below.

First, at timing t31prior to the initialization period P11, the power line drive section66allows the power signal DS2to be varied from the voltage Vccp to the voltage Vini (Part (B) inFIG. 33). Accordingly, the drive transistor DRTr is turned on, and the source voltage Vs of the drive transistor DRTr is set to the voltage Vini (Part (E) inFIG. 33).

Subsequently, the drive section60initializes the sub-pixel11in a period (initialization period P11) from timing t32to timing t33. Specifically, at the timing t32, the data line drive section67sets the signal Sig to the voltage Vofs (Part (C) inFIG. 33), and the scanning line drive section63allows the voltage of the scanning signal WS to be varied from a low level to a high level (Part (A) inFIG. 33). Accordingly, the write transistor WSTr is turned on, and the gate voltage Vg of the drive transistor DRTr is set to the voltage Vofs (Part (D) inFIG. 33). Thus, the gate-source voltage Vgs (=Vofs−Vini) between the gate and the source of the drive transistor DRTr is set to a voltage higher than the threshold voltage Vth of the drive transistor DRTr, and the sub-pixel11is initialized.

Next, the drive section60performs the Vth correction in a period (Vth correction period P12) from the timing t33to timing t34. Specifically, at the timing t33, the power line drive section66allows the power signal DS2to be varied from the voltage Vini to the voltage Vccp (Part (B) inFIG. 33). Accordingly, the drive transistor DRTr is allowed to operate in the saturation region, and thereby, the current Ids flows from the drain to the source and the source voltage Vs is increased (Part (E) inFIG. 33). At that time, the source voltage Vs is lower than the voltage Vcath at the cathode of the organic EL device OLED. Therefore, the organic EL device OLED retains the reverse bias state and a current does not flow into the organic EL device OLED. Because the source voltage Vs is thus increased, the gate-source voltage Vgs is decreased, and therefore, the current Ids is decreased. With this negative feedback operation, the current Ids is converged toward “0 (zero)”. In other words, the gate-source voltage Vgs of the drive transistor DRTr is so converged as to be equal to the threshold voltage Vth of the drive transistor DRTr (Vgs=Vth).

Basic operation in the Vth correction period P12is similar to the operation in the Ids correction period P2according to the above-described first embodiment, and the gate-source voltage Vgs is decreased gradually over time as shown in Expression (3). At that time, in the Vth correction period P12, unlike in the Ids correction period P2according to the above-described first embodiment, the negative feedback operation is performed until the gate-source voltage Vgs is almost converged. In other words, time length of the Vth correction period P12is set to be longer than the time length of the Ids correction period P2.

Subsequently, at the timing t34, the scanning line drive section63allows the voltage of the scanning signal WS to be varied from the high level to the low level (Part (A) inFIG. 33). Accordingly, the write transistor WSTr is turned off. At the timing t35, the data line drive section67sets the signal Sig to the pixel voltage Vsig (Part (C) inFIG. 33).

Subsequently, the drive section60writes the pixel voltage Vsig in the sub-pixel11and performs the μ correction in a period (write-μ-correction period P13) from timing t36to timing t37. Specifically, at the timing t36, the scanning line drive section63allows the voltage of the scanning signal WS to be varied from the low level to the high level (Part (A) inFIG. 33). Accordingly, the write transistor WSTr is turned on, and the gate voltage Vg of the drive transistor DRTr is increased from the voltage Vofs to the pixel voltage Vsig (Part (D) inFIG. 33). At this time, the gate-source voltage Vgs of the drive transistor DRTr becomes higher than the threshold voltage Vth (Vgs>Vth), and the current Ids is flown from the drain to the source. Therefore, the source voltage Vs of the drive transistor DRTr is increased (Part (E) inFIG. 33). With such negative feedback operation, influence of the device variations in the drive transistors DRTr is suppressed (μ correction), and the gate-source voltage Vgs of the drive transistor DRTr is set to a voltage Vemi in accordance with the pixel voltage Vsig.

It is to be noted that such a μ correction method is disclosed, for example, in Japanese Unexamined Patent Publication Application No. 2006-215213.

Subsequently, the drive section60allows the sub-pixel11to emit light in a period (light emission period P16) that begins from timing t37. Specifically, at the timing t37, the scanning line drive section63allows the voltage of the scanning signal WS to be varied from the high level to the low level (Part (A) inFIG. 33). Accordingly, the gate voltage Vg and the source voltage Vs of the drive transistor DRTr are increased (Parts (D) and (E) inFIG. 33) and the organic EL device OLED emits light, as in the light emission period P3according to the above-described first embodiment.

As described above, in the present embodiment, both the Vth correction and the μ correction are performed. Therefore, degradation in image quality resulting from the device variations in the drive transistors is suppressed.

Moreover, in the present embodiment, the source voltage is increased in accordance with the device variations in the organic EL devices in the light emission period. Therefore, degradation in image quality resulting from the device variations in the organic EL devices is suppressed.

In the above-described fourth embodiment, both the Vth correction and the μ correction are performed on the display section10(FIGS. 1 and 2) that includes the sub-pixels11having the “2Tr1C” configuration. However, this is not limitative. Alternatively, both the Vth correction and the μ correction may be performed on the display section10A (FIGS. 6 and 7) that includes the sub-pixels11A having the “3Tr1C” configuration. A display unit6A according to the present modification will be described below in detail.

As shown inFIGS. 6 and 7, the display unit6A includes the display section10A and a drive section60A. The display section10A includes the sub-pixels11A having the “3Tr1C” configuration. The drive section60A includes a scanning line drive section63A, a power control line drive section65A, a power line drive section66A, and a data line drive section67A.

FIG. 34is a timing chart of display operation in the display unit6A. InFIG. 34, Part (A) shows the waveform of the scanning signal WS, Part (B) shows the waveform of the power control signal DS, Part (C) shows the waveform of the power signal DS2, Part (D) shows the waveform of the signal Sig, Part (E) shows the waveform of the gate voltage Vg of the drive transistor DRTr, and Part (F) shows the waveform of the source voltage Vs of the drive transistor DRTr.

First, the drive section60A initializes the sub-pixel11A in a period (initialization period P11) from timing t41to timing t42. Specifically, first, at the timing t41, the data line drive section67A sets the signal Sig to the voltage Vofs (Part (D) inFIG. 34), and the scanning line drive section63A allows the voltage of the scanning signal WS to be varied from a low level to a high level (Part (A) inFIG. 34). At the same time, the power line drive section66A allows the power signal DS2to be varied from the voltage Vccp to the voltage Vini (Part (C) inFIG. 34). Accordingly, the gate voltage Vg of the drive transistor DRTr is set to the voltage Vofs (Part (E) inFIG. 34), and the source voltage Vs of the drive transistor DRTr is set to the voltage Vini (Part (F) inFIG. 34). Thus, the sub-pixel11A is initialized.

Subsequently, the drive section60A performs the Vth correction in a period (Vth correction period P12) from the timing t42to timing t43, as in the above-described fourth embodiment.

Subsequently, at the timing t43, the power control line drive section65A allows the voltage of the power control signal DS to be varied from a low level to a high level (Part (B) inFIG. 34). Accordingly, the power transistor DSTr is turned off.

Subsequently, the drive section60A writes the pixel voltage Vsig in the sub-pixel11A in a period (write period P14) from timing t44to timing t45. Specifically, at the timing t44, the data line drive section67A sets the signal Sig to the pixel voltage Vsig (Part (D) inFIG. 34). Accordingly, the gate voltage Vg of the drive transistor DRTr is increased from the voltage Vofs to the pixel voltage Vsig (Part (E) inFIG. 34). Accordingly, the gate-source voltage Vgs of the drive transistor DRTr becomes higher than the threshold voltage Vth (Vgs>Vth).

Subsequently, the drive section60A performs the μ correction in a period (μ correction period P15) from the timing t45to timing t46. Specifically, at the timing t45, the power control line drive section65A allows the voltage of the power control signal DS to be varied from the high level to the low level (Part (B) inFIG. 34). Accordingly, the power transistor DSTr is turned on, and the current Ids is flown from the drain to the source. Therefore, the source voltage Vs of the drive transistor DRTr is increased (Part (F) inFIG. 34). Through the operation described above, the μ correction is performed.

Effects similar to those in the above-described fourth embodiment are obtainable also in such a configuration.

Moreover, for example, both the Vth correction and the μ correction may be performed on the display section10B (FIGS. 9 and 10) that includes the sub-pixels11B having the “4Tr1C” configuration. A display unit6B according to the present modification will be described below in detail.

As shown inFIGS. 9 and 10, the display unit6B includes the display section10B and a drive section60B. The display section10B includes the sub-pixels11B having the “4Tr1C” configuration. The drive section60B includes a scanning line drive section63B, a control line drive section64B, a power control line drive section65B, and a data line drive section67B.

FIG. 35is a timing chart of display operation in the display unit6B. InFIG. 35, Part (A) shows the waveform of the scanning signal WS, Part (B) shows the waveform of the control signal AZ1, Part (C) shows the waveform of the power control signal DS, Part (D) shows the waveform of the signal Sig, Part (E) shows the waveform of the gate voltage Vg of the drive transistor DRTr, and Part (F) shows the waveform of the source voltage Vs of the drive transistor DRTr.

First, the drive section60B initializes the sub-pixel11B in a period (initialization period P11) from timing t51to timing t52. Specifically, first, at the timing t51, the data line drive section67B sets the signal Sig to the voltage Vofs (Part (D) inFIG. 35), and the scanning line drive section63B allows the voltage of the scanning signal WS to be varied from a low level to a high level (Part (A) inFIG. 35). At the same time, the control line drive section64B allows the voltage of the control signal AZ1to be varied from a low level to a high level (Part (B) inFIG. 35), and the power control line drive section65B allows the voltage of the power control signal DS to be varied from a low level to a high level (Part (C) inFIG. 35). Accordingly, the gate voltage Vg of the drive transistor DRTr is set to the voltage Vofs (Part (E) inFIG. 35), and the source voltage Vs of the drive transistor DRTr is set to the voltage Vini (Part (F) inFIG. 35). Thus, the sub-pixel11B is initialized.

Subsequently, the drive section60B performs the Vth correction in a period (Vth correction period P12) from the timing t52to timing t53. Specifically, the control line drive section64B allows the voltage of the control signal AZ1to be varied from the high level to the low level (Part (B) inFIG. 35), and the power control line drive section65B allows the voltage of the power control signal DS to be varied from the high level to the low level (Part (C) inFIG. 35). Accordingly, the control transistor AZ1is turned off, and the power transistor DSTr is turned on. Thus, the Vth correction is performed as in the above-described fourth embodiment.

Subsequently, at timing t54, the power control line drive section65B allows the voltage of the power control signal DS to be varied from the low level to the high level (Part (C) inFIG. 35). Accordingly, the power transistor DSTr is turned off.

Subsequently, the drive section60B writes the pixel voltage Vsig in the sub-pixel11B in a period (write period P14) from the timing t54to timing t55, and performs the μ correction in a period (μ correction period P15) from the timing t54to the timing t55, as in the above-described Modification 4-1.

Effects similar to those in the above-described fourth embodiment are obtainable also in such a configuration.

Moreover, for example, both the Vth correction and the μ correction may be performed on the display section10C (FIGS. 13 and 14) that includes the sub-pixels11C having the “4Tr1C” configuration. A display unit6C according to the present modification will be described below in detail.

As shown inFIGS. 13 and 14, the display unit6C includes the display section10C and a drive section60C. The display section10C includes the sub-pixels11C having the “4Tr1C” configuration. The drive section60C includes a scanning line drive section63C, a control line drive section64C, a power control line drive section65C, a power line drive section66C, and a data line drive section67C.

FIG. 36is a timing chart of display operation in the display unit6C. InFIG. 36, Part (A) shows the waveform of the scanning signal WS, Part (B) shows the waveform of the control signal AZ2, Part (C) shows the waveform of the power control signal DS, Part (D) shows the waveform of the power signal DS2, Part (E) shows the waveform of the signal Sig, Part (F) shows the waveform of the gate voltage Vg of the drive transistor DRTr, and Part (G) shows the waveform of the source voltage Vs of the drive transistor DRTr.

First, the drive section60C initializes the sub-pixel11C in a period (initialization period P11) from timing t61to timing t62. Specifically, first, at the timing t61, the control line drive section64C allows the voltage of the control signal AZ2to be varied from a low level to a high level (Part (B) inFIG. 36). Accordingly, the control transistor AZ2Tr is turned on, and the gate voltage Vg of the drive transistor DRTr is set to the voltage Vofs (Part (F) inFIG. 36). At the same time, the power line drive section66C allows the power signal DS2to be varied from the voltage Vccp to the voltage Vini (Part (D) inFIG. 36). Accordingly, the drive transistor DRTr is turned on, and the source voltage Vs of the drive transistor DRTr is set to the voltage Vini (Part (G) inFIG. 36). Thus, the sub-pixel11C is initialized.

Subsequently, the drive section60C performs the Vth correction in a period (Vth correction period P12) from the timing t62and timing t63, as in the above-described fourth embodiment.

Subsequently, at the timing t63, the control drive section64C allows the voltage of the control signal AZ2to be varied from the high level to the low level (Part (B) inFIG. 36), and the power control line drive section65C allows the voltage of the power control signal DS to be varied from a low level to a high level (Part (C) inFIG. 36). Accordingly, the control transistor AZ2Tr is turned off, and the power transistor DSTr is turned off.

Subsequently, the drive section60C writes the pixel voltage Vsig in the sub-pixel11C in a period (write period P14) from timing t64to timing t65. Specifically, at the timing t64, the data line drive section67C sets the signal Sig to the pixel voltage Vsig (Part (E) inFIG. 36), and the scanning line drive section63C allows the voltage of the scanning signal WS to be varied from a low level to a high level (Part (A) inFIG. 36). Accordingly, the write transistor WSTr is turned on, and the gate voltage Vg of the drive transistor DRTr is increased from the voltage Vofs to the pixel voltage Vsig (Part (F) inFIG. 36). Accordingly, the gate-source voltage Vgs of the drive transistor DRTr becomes higher than the threshold voltage Vth (Vgs>Vth).

Subsequently, the drive section60C performs the μ correction in a period (μ correction period P15) from the timing t65to timing t66as in the above-described Modification 4-1.

Effects similar to those in the above-described fourth embodiment are obtainable also with such a configuration.

Moreover, for example, both the Vth correction and the μ correction may be performed on the display section10D (FIGS. 17 and 18) that includes the sub-pixels11D having the “5Tr1C” configuration. A display unit6D according to the present modification will be described below in detail.

As shown inFIGS. 17 and 18, the display unit6D includes the display section10D and a drive section60D. The display section10D includes the sub-pixels11D having the “5Tr1C” configuration. The drive section60D includes a scanning line drive section63D, a control line drive section64D, a power control line drive section65D, and a data line drive section67D.

FIG. 37is a timing chart of display operation in the display unit6D. InFIG. 37, Part (A) shows the waveform of the scanning signal WS, Part (B) shows the waveform of the control signal AZ1, Part (C) shows the waveform of the control signal AZ2, Part (D) shows the waveform of the power control signal DS, Part (E) shows the waveform of the signal Sig, Part (F) shows the waveform of the gate voltage Vg of the drive transistor DRTr, and Part (G) shows the waveform of the source voltage Vs of the drive transistor DRTr.

First, at timing t71prior to the initialization period P11, the power control line drive section65D allows the voltage of the power control signal DS to be varied from a low level to a high level (Part (D) inFIG. 37). Accordingly, the power transistor DSTr is turned off.

Subsequently, the drive section60D initializes the sub-pixel11D in a period (initialization period P11) from timing t72to timing t73. Specifically, first, at the timing t72, the control line drive section64D allows the voltage of the control signal AZ1to be varied from a low level to a high level (Part (B) inFIG. 37), and allows the voltage of the control signal AZ2to be varied from a low level to a high level (Part (C) inFIG. 37). Accordingly, the control transistor AZ1Tr is turned on, and the source voltage Vs of the drive transistor DRTr is set to the voltage Vini (Part (G) inFIG. 37). Also, the control transistor AZ2Tr is turned on, and the gate voltage Vg of the drive transistor DRTr is set to the voltage Vofs (Part (F) inFIG. 37). Thus, the sub-pixel11D is initialized.

Subsequently, at the timing t73, the control line drive section64D allows the voltage of the control signal AZ1to be varied from the high level to the low level (Part (B) inFIG. 37). Accordingly, the control transistor AZ1Tr is turned off.

Subsequently, the drive section60D performs the Vth correction in a period (Vth correction period P12) from timing t74to timing t75. Specifically, at the timing t74, the power control line drive section65D allows the voltage of the power control signal DS to be varied from the high level to the low level (Part (D) inFIG. 37). Thus, the Vth correction is performed as in the above-described fourth embodiment.

Subsequently, at the timing t75, the power control line drive section65D allows the voltage of the power control signal DS to be varied from the low level to the high level (Part (D) inFIG. 37). Further, at the timing t76, the control line drive section64D allows the voltage of the control signal AZ2to be varied from the high level to the low level (Part (C) inFIG. 37).

Subsequently, the drive section60D writes the pixel voltage Vsig in the sub-pixel11D in a period (write period P14) from timing t77to timing t78. Specifically, at the timing t77, the data line drive section67D sets the signal Sig to the pixel voltage Vsig (Part (E) inFIG. 37), and the scanning line drive section63D allows the voltage of the scanning signal WS to be varied from a low level to a high level (Part (A) inFIG. 37). Accordingly, the write transistor WSTr is turned on, and the gate voltage Vg of the drive transistor DRTr is increased from the voltage Vofs to the pixel voltage Vsig (Part (F) inFIG. 37). Accordingly, the gate-source voltage Vgs of the drive transistor DRTr becomes higher than the threshold voltage Vth (Vgs>Vth).

Subsequently, the drive section60D performs the μ correction in a period from the timing t78to timing t79(μ correction period P15) as in the above-described Modification 4-1.

Effects similar to those in the above-described fourth embodiment are obtainable also with such a configuration.

Next, a display unit7A according to a fifth embodiment will be described. The present embodiment is a display unit that eliminates the μ correction and performs only the Vth correction in the display unit6according to the above-described fourth embodiment. It is to be noted that the same numerals are used to designate substantially the same components of the display unit6according to the above-described fourth embodiment etc., and the description thereof will be appropriately omitted.

As shown inFIGS. 6 and 7, the display unit7A includes the display section10A and a drive section70A. The display section10A includes sub-pixels11A having the “3Tr1C” configuration. The drive section70A includes a scanning line drive section73A, a power control line drive section75A, a power line drive section76A, and a data line drive section77A.

FIG. 38is a timing chart of display operation in the display unit7A. InFIG. 38, Part (A) shows the waveform of the scanning signal WS, Part (B) shows the waveform of the power signal DS2, Part (C) shows the waveform of the signal Sig, Part (D) shows the waveform of the gate voltage Vg of the drive transistor DRTr, and Part (E) shows the waveform of the source voltage Vs of the drive transistor DRTr.

The drive section70A initializes the sub-pixel11A (initialization period P11), performs the Vth correction for suppressing the influence, on image quality, of the device variations in the drive transistors DRTr (Vth correction period P12), and writes the pixel voltage Vsig in the sub-pixel11A (write period P14), in one horizontal period (1H). Thereafter, the organic EL device OLED in the sub-pixel11A emits light with luminance in accordance with the written pixel voltage Vsig (light emission period P16). Details thereof will be described below.

First, the drive section70A initializes the sub-pixel11A in the period (initialization period P11) from the timing t41to the timing t42, performs the Vth correction in the period (Vth correction period P12) from the timing t42to the timing t43, and writes the pixel voltage Vsig in the sub-pixel11A in the period (write period P14) from the timing t44to the timing t47, as with the drive section60A (FIG. 34) according to the above-described fourth embodiment.

Subsequently, at the timing t47, the scanning line drive section73A allows the scanning signal WS to be varied from a high level to a low level (Part (A) inFIG. 38). Accordingly, the write transistor WSTr is turned off.

Subsequently, the drive section70A allows the sub-pixel11A to emit light in a period (light emission period P16) that begins from the timing t48. Specifically, at the timing t48, the power control line drive section75A allows the power control signal DS to be varied from a high level to a low level (Part (B) inFIG. 38). Accordingly, the gate voltage Vg and the source voltage Vs of the drive transistor DRTr are increased (Parts (E) and (F) inFIG. 38), and the organic EL device OLED emits light, as in the light emission period P16according to the above-described fourth embodiment.

As described above, in the present embodiment, only the Vth correction is performed. Therefore, simpler operation is achieved while degradation in image quality resulting from the device variations in the drive transistors is suppressed.

Moreover, in the present embodiment, the source voltage is increased in accordance with the device variations in the organic EL devices in the light emission period. Therefore, degradation in image quality resulting from the device variations in the organic EL devices is suppressed.

In the above-described fifth embodiment, the Vth correction is performed on the display section10A (FIGS. 6 and 7) that includes the sub-pixels11A having the “3Tr1C” configuration. However, this is not limitative. Alternatively, the Vth correction may be performed on the display section10B (FIGS. 9 and 10) that includes the sub-pixels11B having the “4Tr1C” configuration. A display unit7B according to the present modification will be described below in detail.

As shown inFIGS. 9 and 10, the display unit7B includes the display section10B and a drive section70B. The display section10B includes the sub-pixels11B having the “4Tr1C” configuration. The drive section70B includes a scanning line drive section73B, a control line drive section74B, a power control line drive section75B, and a data line drive section77B.

FIG. 39is a timing chart of display operation in the display unit7B. InFIG. 39, Part (A) shows the waveform of the scanning signal WS, Part (B) shows the waveform of the control signal AZ1, Part (C) shows the waveform of the power control signal DS, Part (D) shows the waveform of the signal Sig, Part (E) shows the waveform of the gate voltage Vg of the drive transistor DRTr, and Part (F) shows the waveform of the source voltage Vs of the drive transistor DRTr.

First, the drive section70B initializes the sub-pixel11B in the period (initialization period P11) from the timing t51to the timing t52, performs the Vth correction in the period (Vth correction period P12) from the timing t52to the timing t53, and writes the pixel voltage Vsig in the sub-pixel11B in the period (write period P14) from the timing t54to the timing t57, as with the drive section60B (FIG. 35) according to the above-described fourth embodiment.

Subsequently, at the timing t57, the scanning line drive section73B allows the scanning signal WS to be varied from a high level to a low level (Part (A) inFIG. 39). Accordingly, the write transistor WSTr is turned off.

Subsequently, the drive section70B allows the sub-pixel11B to emit light in a period (light emission period P16) that begins from timing t58. Specifically, at the timing t58, the power control line drive section75B allows the power control signal DS to be varied from a high level to a low level (Part (C) inFIG. 39). Accordingly, the gate voltage Vg and the source voltage Vs of the drive transistor DRTr are increased (Parts (E) and (F) inFIG. 39), and the organic EL device OLED emits light, as in the light emission period P16according to the above-described fourth embodiment.

Effects similar to those in the above-described fifth embodiment are obtainable also in such a configuration.

Alternatively, for example, the Vth correction may be performed on the display section10C (FIGS. 13 and 14) that includes the sub-pixels11C having the “4Tr1C” configuration. A display unit7C according to the present modification will be described below in detail.

As shown inFIGS. 13 and 14, the display unit7C includes the display section10C and a drive section70C. The display section10C includes the sub-pixels11C having the “4Tr1C” configuration. The drive section70C includes a scanning line drive section73C, a control line drive section74C, a power control line drive section75C, a power line drive section76C, and a data line drive section77C.

FIG. 40is a timing chart of display operation in the display unit7C. InFIG. 40, Part (A) shows the waveform of the scanning signal WS, Part (B) shows the waveform of the control signal AZ2, Part (C) shows the waveform of the power control signal DS, Part (D) shows the waveform of the power signal DS2, Part (E) shows the waveform of the signal Sig, Part (F) shows the waveform of the gate voltage Vg of the drive transistor DRTr, and Part (G) shows the waveform of the source voltage Vs of the drive transistor DRTr.

First, the drive section70C initializes the sub-pixel11C in the period (initialization period P11) from the timing t61to the timing t62, performs the Vth correction in the period (Vth correction period P12) from the timing t62to the timing t63, and writes the pixel voltage Vsig in the sub-pixel11C in the period (write period P14) from the timing t64to the timing t67, as with the drive section60C (FIG. 36) according to the above-described fourth embodiment.

Subsequently, at the timing t67, the scanning line drive section73C allows the scanning signal WS to be varied from a high level to a low level (Part (A) inFIG. 40). Accordingly, the write transistor WSTr is turned off.

Subsequently, the drive section70C allows the sub-pixel11C to emit light in a period (light emission period P16) that begins from timing t68. Specifically, at the timing t68, the power control line drive section75C allows the power control signal DS to be varied from a high level to a low level (Part (C) inFIG. 40). Accordingly, the gate voltage Vg and the source voltage Vs of the drive transistor DRTr are increased (Parts (F) and (G) inFIG. 40), and the organic EL device OLED emits light, as in the light emission period P16according to the above-described fourth embodiment.

Effects similar to those in the above-described fifth embodiment are obtainable also in such a configuration.

Alternatively, for example, the Vth correction may be performed on the display section10D (FIGS. 17 and 18) that includes the sub-pixels11D having the “5Tr1C” configuration. A display unit7D according to the present modification will be described below in detail.

As shown inFIGS. 17 and 18, the display unit7D includes the display section10D and a drive section70D. The display section10D includes the sub-pixels11D having the “5Tr1C” configuration. The drive section70D includes a scanning line drive section73D, a control line drive section74D, a power control line drive section75D, and a data line drive section77D.

FIG. 41is a timing chart of display operation in the display unit7D. InFIG. 41, Part (A) shows the waveform of the scanning signal WS, Part (B) shows the waveform of the control signal AZ1, Part (C) shows the waveform of the control signal AZ2, Part (D) shows the waveform of the power control signal DS, Part (E) shows the waveform of the signal Sig, Part (F) shows the waveform of the gate voltage Vg of the drive transistor DRTr, and Part (G) shows the waveform of the source voltage Vs of the drive transistor DRTr.

First, the drive section70D initializes the sub-pixel11D in the period (initialization period P11) from the timing t72to the timing t73, performs the Vth correction in the period (Vth correction period P12) from the timing t74to the timing t75, and writes the pixel voltage Vsig in the sub-pixel11D in the period (write period P14) from the timing t77to the timing t80, as with the drive section60D (FIG. 37) according to the above-described fourth embodiment.

Subsequently, at the timing t80, the scanning line drive section73D allows the scanning signal WS to be varied from a high level to a low level (Part (A) inFIG. 41). Accordingly, the write transistor WSTr is turned off.

Subsequently, the drive section70D allows the sub-pixel11D to emit light in a period (light emission period P16) that begins from timing t81. Specifically, at the timing t81, the power control line drive section75D allows the power control signal DS to be varied from a high level to a low level (Part (D) inFIG. 41). Accordingly, the gate voltage Vg and the source voltage Vs of the drive transistor DRTr are increased (Parts (F) and (G) inFIG. 41), and the organic EL device OLED emits light, as in the light emission period P16according to the above-described fourth embodiment.

Effects similar to those in the above-described fifth embodiment are obtainable also in such a configuration.

Next, a display unit8according to a sixth embodiment will be described. The present embodiment is a display unit that does not perform correction for suppressing the influence, on image quality, of the device variations in the drive transistors DRTr. It is to be noted that the same numerals are used to designate substantially the same components of the display unit1according to the above-described first embodiment and the like, and the description thereof will be appropriately omitted.

As shown inFIGS. 1 and 2, the display unit8includes the display section10and a drive section80. The display section10includes the sub-pixels11having the “2Tr1C” configuration. The drive section80includes a scanning line drive section83, a power line drive section86, and a data line drive section87.

FIG. 42is a timing chart of display operation in the display unit8. InFIG. 42, Part (A) shows the waveform of the scanning signal WS, Part (B) shows the waveform of the power signal DS2, Part (C) shows the waveform of the signal Sig, Part (D) shows the waveform of the gate voltage Vg of the drive transistor DRTr, and Part (E) shows the waveform of the source voltage Vs of the drive transistor DRTr.

The drive section80writes the pixel voltage Vsig in the sub-pixel11(write period P21) in one horizontal period (1H). Thereafter, the organic EL device OLED in the sub-pixel11emits light with luminance corresponding to the written pixel voltage Vsig (light emission period P22). Details thereof will be described below.

First, the drive section80writes the pixel voltage Vsig in the sub-pixel11in a period (write period P21) from timing t91to timing t92. Specifically, first, at the timing t91, the data line drive section97sets the signal Sig to the pixel voltage Vsig (Part (C) inFIG. 42), and the scanning line drive section83allows the voltage of the scanning signal WS to be varied from a low level to a high level (Part (A) inFIG. 42). Accordingly, the write transistor WSTr is turned on, and the gate voltage Vg of the drive transistor DRTr is set to the pixel voltage Vsig (Part (D) inFIG. 42). At the same time, the power line drive section86allows the power signal DS2to be varied from the voltage Vccp to the voltage Vini (Part (B) inFIG. 42). Accordingly, the drive transistor DRTr is turned on, and the source voltage Vs of the drive transistor DRTr is set to the voltage Vini (Part (E) inFIG. 42).

Subsequently, at the timing t92, the scanning line drive section83allows the voltage of the scanning signal WS to be varied from the high level to the low level (Part (A) inFIG. 42). Accordingly, the write transistor WSTr is turned off, and the gate of the drive transistor DRTr is placed in a floating state. Thereafter, the voltage between the terminals of the capacitor Cs, that is, the gate-source voltage Vgs of the drive transistor DRTr is maintained.

Subsequently, the drive section80allows the sub-pixel11to emit light in a period (light emission period P22) that begins from timing t93. Specifically, at the timing t93, the power line drive section86allows the power signal DS2to be varied from the voltage Vini to the voltage Vccp (Part (B) inFIG. 42). Accordingly, the current Ids is flown into the drive transistor DRTr, and the source voltage Vs of the drive transistor DRTr is increased (Part (E) inFIG. 42). In accordance therewith, the gate voltage Vg of the drive transistor DRTr is increased (Part (D) inFIG. 42). When the source voltage Vs of the drive transistor DRTr becomes higher than a sum (Vel+Vcath) of the threshold voltage Vel and the voltage Vcath of the organic EL device OLED, a current flows between the anode and the cathode of the organic EL device OLED, which allows the organic EL device OLED to emit light. In other words, the source voltage Vs is increased in accordance with the device variations in the organic EL devices OLED, and the organic EL device OLED emits light.

As described above, in the present embodiment, the correction for suppressing the influence, on image quality, of the device variations in the drive transistors is not performed. Therefore, simpler operation is achieved.

Moreover, in the present embodiment, the source voltage is increased in accordance with the device variations in the organic EL devices in the light emission period. Therefore, degradation in image quality resulting from the device variations in the organic EL devices is suppressed.

In the above-described sixth embodiment, the correction for suppressing the influence, on image quality, of the device variations in the drive transistors DRTr is not performed on the display section10(FIGS. 1 and 2) that includes the sub-pixel11having the “2Tr1C” configuration. However, this is not limitative. Alternatively, similar correction may not be performed on the display section10B (FIGS. 9 and 10) that includes the sub-pixel11B having the “4Tr1C” configuration. A display unit8B according to the present modification will be described below in detail.

As shown inFIGS. 9 and 10, the display unit8B includes the display section10B and a drive section80B. The display section10B includes the sub-pixels11B having the “4Tr1C” configuration. The drive section80B includes a scanning line drive section83B, a control line drive section84B, a power control line drive section85B, and a data line drive section87B.

FIG. 43is a timing chart of display operation in the display unit8B. InFIG. 43, Part (A) shows the waveform of the scanning signal WS, Part (B) shows the waveform of the control signal AZ1, Part (C) shows the waveform of the power control signal DS, Part (D) shows the waveform of the signal Sig, Part (E) shows the waveform of the gate voltage Vg of the drive transistor DRTr, and Part (F) shows the waveform of the source voltage Vs of the drive transistor DRTr.

First, at timing t101prior to the write period P21, the power control line drive section85D allows the voltage of the power control signal DS to be varied from a low level to a high level (Part (C) inFIG. 43). Accordingly, the power transistor DSTr is turned off.

Next, the drive section80B writes the pixel voltage Vsig in the sub-pixel11B in a period (write period P21) from timing t102to timing t103, as in the above-described sixth embodiment. Further, at the timing t102, the control line drive section84B allows the voltage of the control signal AZ1to be varied from a low level to a high level (Part (B) inFIG. 43). Accordingly, the control transistor AZ1Tr is turned on, and the source voltage Vs of the drive transistor DRTr is set to the voltage Vini (Part (F) inFIG. 43).

Subsequently, at the timing t103, the scanning line drive section83B allows the voltage of the scanning signal WS to be varied from a high level to a low level (Part (A) inFIG. 43), and the control line drive section84B allows the voltage of the control signal AZ1to be varied from the high level to the low level (Part (B) inFIG. 43). Accordingly, the write transistor WSTr is turned off, and the control transistor AZ1Tr is turned off.

Subsequently, the drive section80B allows the sub-pixel11B to emit light in a period (light emission period P22) that begins from timing t104. Specifically, at the timing t104, the power control line drive section85B allows the power control signal DS to be varied from the high level to the low level (Part (C) inFIG. 43). Accordingly, the organic EL device OLED emits light as in the above-described sixth embodiment.

Effects similar to those in the above-described sixth embodiment are obtainable also in such a configuration.

In the above-described sixth embodiment, the sub-pixel11includes two transistors. However, this is not limitative. Alternatively, for example, the sub-pixel may further include other transistors.

For example, a method (FIG. 42) of driving the display section10(FIGS. 1 and 2) that includes the sub-pixel11having the “2Tr1C” configuration may be applied as it is to the display section10A (FIGS. 6 and 7) that includes the sub-pixel11A having the “3Tr1C” configuration. In this case, the same method as the driving method shown inFIG. 42is achievable by allowing the power control signal DS to be mostly at the low level (L) (Part (B) inFIG. 44) and allowing the power transistor DSTr to be mostly ON, as shown inFIG. 44.

Moreover, for example, the method (FIG. 42) of driving the display section10(FIGS. 1 and 2) that includes the sub-pixel11having the “2Tr1C” configuration may be applied as it is to the display section10C (FIGS. 13 and 14) that includes the sub-pixel11C having the “4Tr1C” configuration. In this case, the same method as the driving method shown inFIG. 42is achievable, by allowing the control signal AZ2to be mostly at the low level (L) (Part (B) inFIG. 45) to allow the control transistor AZ2Tr to be mostly OFF, and allowing the power control signal DS to be mostly at the low level (L) (Part (C) inFIG. 45) to allow the power transistor DSTr to be mostly ON, as shown inFIG. 45.

Moreover, for example, the method (FIG. 43) of driving the display section10B (FIGS. 9 and 10) that includes the sub-pixel11B having the “4Tr1C” configuration may be applied as it is to the display section10D (FIGS. 17 and 18) that includes the sub-pixel11D having the “5Tr1C” configuration. In this case, the same method as the driving method shown inFIG. 43is achievable, by allowing the control signal AZ2to be mostly at the low level (L) (Part (C) inFIG. 46) to allow the control transistor AZ2Tr to be mostly OFF, as shown inFIG. 46.

Next, a display unit9according to a seventh embodiment will be described. The present embodiment is a display unit that is configured to begin light emission of the sub-pixel11upon the operation of writing in the sub-pixel11. It is to be noted that the same numerals are used to designate substantially the same components of the display unit1according to the above-described first embodiment and the like, and the description thereof will be appropriately omitted.

As shown inFIGS. 1 and 2, the display unit9includes the display section10and a drive section90. The display section10includes the sub-pixels11having the “2Tr1C” configuration. The drive section90includes a scanning line drive section93, a power line drive section96, and a data line drive section97.

FIG. 47is a timing chart of display operation in the display unit9. InFIG. 47, Part (A) shows the waveform of the scanning signal WS, Part (B) shows the waveform of the signal Sig, Part (C) shows the waveform of the gate voltage Vg of the drive transistor DRTr, and Part (D) shows the waveform of the source voltage Vs of the drive transistor DRTr.

The drive section90writes the pixel voltage Vsig in the sub-pixel11in a period (write period P31) from timing t111to timing t112. Specifically, first, at the timing t111, the data line drive section97sets the signal Sig to the pixel voltage Vsig (Part (B) inFIG. 47), and the scanning line drive section93allows the voltage of the scanning signal WS to be varied from a low level to a high level (Part (A) inFIG. 47). Accordingly, the write transistor WSTr is turned on, and the gate voltage Vg of the drive transistor DRTr is set to the pixel voltage Vsig (Part (C) inFIG. 47). The current Ids in the drive transistor DRTr is flown into the organic EL device OLED, and the source voltage Vs is determined (Part (D) inFIG. 47). Thus, the organic EL devices OLED emits light in a period (light emission period P32) that begins from the timing t111.

As described above, in the present embodiment, the sub-pixel begins to emit light upon the operation of writing in the sub-pixel. Therefore, simpler operation is achievable.

In the above-described seventh embodiment, the sub-pixel11includes two transistors. However, this is not limitative. Alternatively, for example, the sub-pixel may further include other transistors.

For example, a method (FIG. 47) of driving the display section10(FIGS. 1 and 2) that includes the sub-pixel11having the “2Tr1C” configuration may be applied as it is to the display section10A (FIGS. 6 and 7) that includes the sub-pixel11A having the “3Tr1C” configuration. In this case, the same method as the driving method shown inFIG. 47is achievable by allowing the power control signal DS to be mostly at the low level (L) (Part (B) inFIG. 48) and allowing the power transistor DSTr to be mostly ON, as shown inFIG. 48.

Moreover, for example, the above-described driving method (FIG. 47) may be applied as it is to the display section10B (FIGS. 9 and 10) that includes the sub-pixel11B having the “4Tr1C” configuration. In this case, the same method as the driving method shown inFIG. 47is achievable by allowing the control signal AZ1to be mostly at the low level (L) (Part (B) inFIG. 49) to allow the control transistor AZ1Tr to be mostly OFF, and allowing the power control signal DS to be mostly at the low level (L) (Part (C) inFIG. 49) to allow the power transistor DSTr to be mostly ON as shown inFIG. 49.

Moreover, for example, the above-described driving method (FIG. 47) may be applied as it is to the display section10C (FIGS. 13 and 14) that includes the sub-pixel11C having the “4Tr1C” configuration. In this case, the same method as the driving method shown inFIG. 47is achievable by allowing the control signal AZ2to be mostly at the low level (L) (Part (B) inFIG. 50) to allow the control transistor AZ2Tr to be mostly OFF, and allowing the power control signal DS to be mostly at the low level (L) (Part (C) inFIG. 50) to allow the power transistor DSTr to be mostly ON as shown inFIG. 50.

Moreover, for example, the above-described driving method (FIG. 47) may be applied as it is to the display section10D (FIGS. 17 and 18) that includes the sub-pixels11D having the “5Tr1C” configuration. In this case, the same method as the driving method shown inFIG. 47is achievable by allowing the control signal AZ1to be mostly at the low level (L) (Part (B) inFIG. 51) to allow the control transistor AZ1Tr to be mostly OFF, allowing the control signal AZ2to be mostly at the low level (L) (Part (C) inFIG. 51) to allow the control transistor AZ2Tr to be mostly OFF, and allowing the power control signal DS to be mostly at the low level (L) (Part (D) inFIG. 51) to allow the power transistor DSTr to be mostly ON, as shown inFIG. 51.

Next, a display unit100according to an eighth embodiment will be described. In the present embodiment, the display section in the display unit, in which the pixel voltage Vsig is applied to the gate of the drive transistor DRTr and the source voltage is varied by the Ids correction, is configured using only a PMOS transistor. It is to be noted that the same numerals are used to designate substantially the same components of the display unit1according to the above-described first embodiment, and the description thereof will be appropriately omitted.

FIG. 52illustrates a configuration example of a display unit100according to the present embodiment. The display unit100includes a display section110and a drive section120.

The display section110includes a plurality of sub-pixels111, the plurality of scanning lines WSL, the plurality of power control lines DSL, the plurality of control lines AZ1L, and a plurality of control lines AZ3L. The scanning lines WSL, the power control lines DSL, and the control lines AZ1L and AZ3L extend in the row direction. One end of each of the scanning lines WSL, the power control lines DSL, and the control lines AZ1L and AZ3L is connected to the drive section120.

FIG. 53illustrates an example of a circuit configuration of the sub-pixel111. The sub-pixel111includes the write transistor WSTr, the drive transistor DRTr, the control transistor AZ1Tr, a control transistor AZ3Tr, the power transistor DSTr, and a capacitor Csub.

The write transistor WSTr, the drive transistor DRTr, the control transistors AZ1Tr and AZ3Tr, and the power transistor DSTr may each be configured, for example, of a TFT of a P-channel MOS type. The gate of the write transistor WSTr is connected to the scanning line WSL, the source thereof is connected to the data line DTL, and the drain thereof is connected to the gate of the drive transistor DRTr, the first end of the capacitor Cs, and the like. The gate of the drive transistor DRTr is connected to the drain of the write transistor WSTr, the first end of the capacitor Cs, and the like, the source thereof is connected to the drain of the power transistor DSTr, the second end of the capacitor Cs, and the like, and the drain thereof is connected to the anode of the organic EL device OLED and the like. The gate of the control transistor AZ1Tr is connected to the control line AZ1L, the source thereof is supplied with the voltage Vini by the drive section120, and the drain thereof is connected to the source of the drive transistor DRTr, the second end of the capacitor Cs, and the like. A gate of the control transistor AZ3Tr is connected to the control line AZ3L, one of a source and a drain thereof is connected to the gate of the drive transistor DRTr, the first end of the capacitor Cs, and the like, and the other of the source and the drain thereof is connected to the drain of the drive transistor DRTr and the like. The gate of the power transistor DSTr is connected to the power control line DSL, the source thereof is supplied with the voltage Vccp by the drive section120, and the drain thereof is connected to the source of the drive transistor DRTr, the second end of the capacitor Cs, and the like.

One end of the capacitor Csub is connected to the source of the drive transistor DRTr, the second end of the capacitor Cs, and the like, and the other end of the capacitor Csub is supplied with a voltage V1by the drive section120. The voltage V1may be any direct-current voltage, and may be, for example, any of the voltages Vccp, Vini, Vofs, and Vcath.

The write transistor WSTr corresponds to a specific but not limitative example of “eleventh transistor” in one embodiment of the present disclosure. The control transistor AZ3Tr corresponds to a specific but not limitative example of “twelfth transistor” in one embodiment of the present disclosure.

The drive section120includes a timing generation section122, a scanning line drive section123, a control line drive section124, a power control line drive section125, and a data line drive section127. The timing generation section122is a circuit that supplies a control signal to each of the scanning line drive section123, the control line drive section124, the power control line drive section125, and the data line drive section127based on the synchronization signal Ssync that is supplied from the outside, and thereby controlling these sections to operate in synchronization with each other. The control line drive section124sequentially applies the control signals AZ1to the plurality of control lines AZ1L and sequentially applies the control signals AZ3to the plurality of control lines AZ3L, in accordance with the control signal supplied from the timing generation section122. The scanning line drive section123, the power control line drive section125, and the data line drive section127have functions similar to those of the scanning line drive section23, the power control line drive section25A, and the data line drive section27, respectively.

FIG. 54is a timing chart of display operation in the display unit100. InFIG. 54, Part (A) shows the waveform of the scanning signal WS, Part (B) shows the waveform of the control signal AZ1, Part (C) shows a waveform of the control signal AZ3, Part (D) shows the waveform of the power control signal DS, Part (E) shows the waveform of the signal Sig, Part (F) shows the waveform of the gate voltage Vg of the drive transistor DRTr, and Part (G) shows the waveform of the source voltage Vs of the drive transistor DRTr.

First, the drive section120writes the pixel voltage Vsig in the sub-pixel111and initializes the sub-pixel111in a period (write period P1) from timing t121to timing t122. Specifically, first, at the timing t121, the data line drive section127sets the signal Sig to the pixel voltage Vsig (Part (E) inFIG. 54), and the scanning line drive section123allows the voltage of the scanning signal WS to be varied from a high level to a low level (Part (A) inFIG. 54). Accordingly, the write transistor WSTr is turned on, and the gate voltage Vg of the drive transistor DRTr is set to the pixel voltage Vsig (Part (F) inFIG. 54). At the same time, the control line drive section124allows the voltage of the control signal AZ1to be varied from a high level to a low level (Part (B) inFIG. 54). Accordingly, the control transistor AZ1Tr is turned on, and the source voltage Vs of the drive transistor DRTr is set to the voltage Vini (Part (G) inFIG. 54). Thus, the sub-pixel111is initialized.

Subsequently, at the timing t122, the control line drive section124allows the voltage of the control signal AZ1to be varied from the low level to the high level (Part (B) inFIG. 54). Accordingly, the control transistor AZ1Tr is turned off, and the supply of the voltage Vini to the source of the drive transistor DRTr is stopped.

Subsequently, the drive section120performs the Ids correction on the sub-pixel111in a period (Ids correction period P2) from timing t123to timing t124. Specifically, at the timing t123, the control line drive section124allows a voltage of the control signal AZ3to be varied from a high level to a low level (Part (C) inFIG. 54). Accordingly, the control transistor AZ3Tr is turned on, and the drain and the gate of the drive transistor DRTr are connected to each other through the control transistor AZ3Tr (a so-called “diode connection”). Accordingly, a current is flown from the source to the gate of the drive transistor DRTr through the drain thereof, and the source voltage Vs is decreased (Part (G) inFIG. 54). Because the source voltage Vs is thus decreased, the current flown from the source to the drain of the drive transistor DRTr is decreased. With this negative feedback operation, the source voltage Vs is decreased in a slower pace over time. A length of the time period (from the timing t123to the timing t124) for performing the Ids correction is determined in order to suppress variations in the current that flows through the drive transistor DRTr at the timing t124as described in the above first embodiment.

Subsequently, at the timing t124, the control line drive section124allows the voltage of the control signal AZ3to be varied from the low level to the high level (Part (C) inFIG. 54). Accordingly, the control transistor AZ3Tr is turned off. Therefore, after this, the voltage between the terminals of the capacitor Cs, that is, the gate-source voltage Vgs of the drive transistor DRTr is maintained.

Subsequently, at timing t125, the scanning line drive section123allows the voltage of the scanning signal WS to be varied from the low level to the high level (Part (A) inFIG. 54). Accordingly, the write transistor WSTr is turned off.

Subsequently, the drive section120allows the sub-pixel111to emit light in a period (light emission period P3) that begins from timing t126. Specifically, at the timing t126, the power control line drive section125allows the voltage of the power control signal DS to be varied from a high level to a low level (Part (D) inFIG. 54). Accordingly, the power transistor DSTr is turned on, and the source voltage Vs of the drive transistor DRTr is increased toward the voltage Vccp (Part (G) inFIG. 54). In accordance therewith, the gate voltage Vg of the drive transistor DRTr is also increased (Part (F) inFIG. 54). Accordingly, the drive transistor DRTr is allowed to operate in a saturation region, and a current is flown through a path including the power transistor DSTr, the drive transistor DRTr, and the organic EL device OLED in order. Accordingly, the organic EL device OLED emits light.

Subsequently, in the display unit100, the transition is made from the light emission period P3to the write period P1after a predetermined period (one frame period) has passed. The drive section120drives the sub-pixel111so that the above-described series of operation is repeated.

As described above, in the present embodiment, the display section is configured only of a PMOS transistor without using an NMOS transistor. Therefore, the display section may be manufactured, for example, even in a process in which the NMOS transistor is not allowed to be manufactured, such as in an organic TFT (O-TFT) process.

In the above-described eighth embodiment, the sub-pixel111includes five transistors. However, this is not limitative. Alternatively, for example, the sub-pixel may further include other transistors. An example thereof will be described below.

FIG. 55illustrates a configuration example of a display unit100A according to the present modification. The display unit100A includes a display section110A and a drive section120A. The display section110A includes a plurality of sub-pixels111A and the plurality of control lines AZ2L that extend in the row direction. One end of each of the control lines AZ2L is connected to the drive section120A.

FIG. 56illustrates an example of a circuit configuration of the sub-pixel111A. The sub-pixel111A includes the control transistor AZ2Tr. The control transistor AZ2Tr is configured of a TFT of a P-channel MOS type. The gate of the control transistor AZ2Tr is connected to the control line AZ2L, the source thereof is supplied with the voltage Vofs by the drive section120A, and the drain thereof is connected to the gate of the drive transistor DRTr, the first end of the capacitor Cs, and the like.

Also in such a configuration, the same method as the driving method shown inFIG. 54is achievable by allowing the control signal AZ2to be mostly at the high level (H) (Part (C) inFIG. 57) to allow the control transistor AZ2Tr to be mostly OFF, as shown inFIG. 57.

In the above-described eighth embodiment, the voltage Vini is supplied to the source of the drive transistor DRTr by allowing the control transistor AZ1Tr to be ON in the write period P1. However, this is not limitative. Alternatively, for example, the voltage Vini may be supplied to the source of the drive transistor DRTr by allowing the power transistor DSTr to be ON. The present modification will be described below in detail.

FIG. 58illustrates a configuration example of a display unit100B according to the present modification. The display unit100B includes a display section110B and a drive section120B. The display section110B includes a plurality of sub-pixels111B. The display section110B also includes the plurality of power lines PL and the plurality of control lines AZ3L that extend in the row direction. One end of each of the power lines PL that extend in the row direction and the control lines AZ3L is connected to the drive section120B.

FIG. 59illustrates an example of a circuit configuration of the sub-pixel111B. In the sub-pixel111B, the source of the power transistor DSTr is connected to the power line PL. The power transistor DSTr corresponds to a specific but not limitative example of “thirteenth transistor” in one embodiment of the present disclosure.

The drive section120B includes a timing generation section122B, a scanning line drive section123B, a control line drive section124B, a power control line drive section125B, a power line drive section126B, and a data line drive section127B. The timing generation section122B is a circuit that supplies a control signal to each of the scanning line drive section123B, the control line drive section124B, the power control drive section125B, the power line drive section126B, and the data line drive section127B based on the synchronization signal Ssync that is supplied from the outside, and thereby controlling these sections to operate in synchronization with each other. The control line drive section124B sequentially applies the control signals AZ3to the plurality of control lines AZ3L in accordance with the control signal supplied from the timing generation section122B. The scanning line drive section123B, the power control line drive section125B, the power line drive section126B, and the data line drive section127B have functions similar to those of the scanning line drive section23, the power control line drive section25A, the power line drive section26, and the data line drive section27, respectively.

FIG. 60is a timing chart of display operation in the display unit100B. InFIG. 60, Part (A) shows the waveform of the scanning signal WS, Part (B) shows the waveform of the control signal AZ3, Part (C) shows the waveform of the power control signal DS, Part (D) shows the waveform of the power signal DS2, Part (E) shows the waveform of the signal Sig, Part (F) shows the waveform of the gate voltage Vg of the drive transistor DRTr, and Part (G) shows the waveform of the source voltage Vs of the drive transistor DRTr.

First, at timing t131prior to the write period P1, the power line drive section126B allows the power signal DS2to be varied from the voltage Vccp to the voltage Vini (Part (D) inFIG. 60).

Subsequently, the drive section120B writes the pixel voltage Vsig in the sub-pixel111B in a period (write period P1) from timing t132to timing t133, as in the above-described eighth embodiment. Further, at the timing t132, the power control line drive section125B allows the voltage of the power control signal DS to be varied from a high level to a low level (Part (C) inFIG. 60). Accordingly, the power transistor DSTr is turned on, and the source voltage Vs of the drive transistor DRTr is set to the voltage Vini (Part (G) inFIG. 60). Thus, the sub-pixel111B is initialized.

Subsequently, at the timing t133, the power control line drive section125B allows the voltage of the power control signal DS to be varied from the low level to the high level (Part (C) inFIG. 60). Accordingly, the power transistor DSTr is turned off, and the supply of the voltage Vini to the source of the drive transistor DRTr is stopped.

Subsequently, the drive section120B performs the Ids correction in a period (Ids correction period P2) from timing t134to timing t135as in the above-described eighth embodiment.

At timing t136, the power line drive section126B allows the power signal DS2to be varied from the voltage Vini to the voltage Vccp (Part (D) inFIG. 60).

Effects similar to those in the above-described eighth embodiment are obtainable also in such a configuration.

In the above-described eighth embodiment, the voltage Vini is supplied to the source of the drive transistor DRTr by allowing the control transistor AZ1Tr to be ON in the write period P1. However, this is not limitative. Alternatively, for example, the voltage Vccp may be supplied to the source of the drive transistor DRTr by allowing the power transistor DSTr to be ON. The present modification will be described below in detail.

FIG. 61illustrates a configuration example of a display unit100C according to the present modification. The display unit100C includes a display section110C and a drive section120C. The display section110C includes a plurality of sub-pixels111C. The display section110C also includes a plurality of power control lines DSAL and DSBL that extend in the row direction and the plurality of control lines AZ3L that extend in the row direction. One end of each of the power control lines DSAL and DSBL and the control lines AZ3L is connected to the drive section120C.

FIG. 62illustrates an example of a circuit configuration of the sub-pixel111C. The sub-pixel111C includes power transistors DSATr and DSBTr. The power transistors DSATr and DSBTr are each configured of a TFT of a P-channel MOS type. A gate of the power transistor DSATr is connected to the power control line DSAL, a source thereof is supplied with the voltage Vccp by the drive section120C, and a drain thereof is connected to the source of the drive transistor DRTr, the second end of the capacitor Cs, and the like. A gate of the power transistor DSBTr is connected to the power control line DSBL, a source thereof is connected to the drain of the drive transistor DRTr and the like, and a drain thereof is connected to the anode of the organic EL device OLED. The power transistor DSBTr corresponds to a specific but not limitative example of “fourteenth transistor” in one embodiment of the present disclosure.

The drive section120C includes a timing generation section122C, a scanning line drive section123C, a control line drive section124C, a power control line drive section125C, and a data line drive section127C. The timing generation section122C is a circuit that supplies a control signal to each of the scanning line drive section123C, the control line drive section124C, the power control drive section125C, and the data line drive section127C based on the synchronization signal Ssync that is supplied from the outside, and thereby controlling these sections to operate in synchronization with each other. The power control line drive section125C sequentially applies power control signals DSA to the plurality of power control lines DSAL and sequentially applies power control signals DSB to the plurality of power control lines DSBL, in accordance with the control signal supplied from the timing generation section122C. The scanning drive section123C, the control line drive section124C, and the data line drive section127C have functions similar to those of the scanning line drive section23, the control line drive section124B, and the data line drive section27, respectively.

FIG. 63is a timing chart of display operation in the display unit100C. InFIG. 63, Part (A) shows the waveform of the scanning signal WS, Part (B) shows the waveform of the control signal AZ3, Part (C) shows a waveform of the power control signal DSA, Part (D) shows a waveform of the power control signal DSB, Part (E) shows the waveform of the signal Sig, Part (F) shows the waveform of the gate voltage Vg of the drive transistor DRTr, and Part (G) shows the waveform of the source voltage Vs of the drive transistor DRTr.

First, at timing t141prior to the write period P1, the power control line drive section125C allows a voltage of the power control signal DSB to be varied from a low level to a high level (Part (D) inFIG. 63). Accordingly, the power transistor DSBTr is turned off.

Subsequently, the drive section120C writes the pixel voltage Vsig in the sub-pixel111C in a period (write period P1) from timing t142to timing t143, as in the above-described eighth embodiment. Further, at the timing t142, the power control line drive section125C allows a voltage of the power control signal DSA to be varied from a high level to a low level (Part (C) inFIG. 63). Accordingly, the power transistor DSATr is turned on, and the source voltage Vs of the drive transistor DRTr is set to the voltage Vccp (Part (G) inFIG. 63). At that time, because the power transistor DSBTr is OFF, a current does not flow into the organic EL device OLED. Thus, the sub-pixel111C is initialized.

Subsequently, at the timing t143, the power control line drive section125C allows the voltage of the power control signal DSA to be varied from the low level to the high level (Part (C) inFIG. 63). Accordingly, the power transistor DSATr is turned off, and the supply of the voltage Vccp to the source of the drive transistor DRTr is stopped.

Subsequently, the drive section120C performs the Ids correction in a period (Ids correction period P2) from timing t144to timing t145as in the above-described eighth embodiment.

Subsequently, at timing t146, the scanning line drive section123C allows the voltage of the scanning signal WS to be varied from the low level to the high level (Part (A) inFIG. 63). Accordingly, the write transistor WSTr is turned off.

Subsequently, at timing t147, the power control line drive section125C allows the voltage of the power control signal DSA to be varied from the high level to the low level (Part (C) inFIG. 63). Accordingly, the power transistor DSATr is turned on, and the source voltage Vs of the drive transistor DRTr is increased toward the voltage Vccp (Part (G) inFIG. 63). In accordance therewith, the gate voltage Vg of the drive transistor DRTr is also increased (Part (F) inFIG. 63).

Subsequently, the drive section120C allows the sub-pixel111C to emit light in a period (light emission period P3) that begins from timing t149. Specifically, at the timing t149, the power control line drive section125C allows the voltage of the power control signal DBS to be varied from the high level to the low level (Part (D) inFIG. 63). Accordingly, the power transistor DSBTr is turned on, and a current is flown through a path including the power transistor DSATr, the drive transistor DRTr, the power transistor DSBTr, and the organic EL device OLED in order. Accordingly, the organic EL device OLED emits light.

Effects similar to those in the above-described eighth embodiment are obtainable also in such a configuration.

Moreover, also in the present modification, for example, the sub-pixel may further include other transistors as will be described below.

FIG. 64illustrates a configuration example of a display unit100D according to the present modification. The display unit100D includes a display section110D and a drive section120D. The display section110D includes a plurality of sub-pixels111D and the plurality of control lines AZ2L that extend in the row direction. One end of each of the control lines AZ2L is connected to the drive section120D.

FIG. 65illustrates an example of a circuit configuration of the sub-pixel111D. The sub-pixel111D includes the control transistor AZ2Tr. The gate of the control transistor AZ2Tr is connected to the control line AZ2L, the source thereof is supplied with the voltage Vofs by the drive section120D, and the drain thereof is connected to the gate of the drive transistor DRTr, the first end of the capacitor Cs, and the like.

Also in such a configuration, the same method as the driving method shown inFIG. 63is achievable by allowing the control signal AZ2to be mostly at the high level (H) (Part (B) inFIG. 66) to allow the control transistor AZ2Tr to be mostly OFF, as shown inFIG. 66.

Next, a display unit300according to a ninth embodiment will be described. In the present embodiment, in a case where the drive transistor DRTr is configured of an NMOS transistor, the pixel voltage Vsig is applied to the source of the drive transistor DRTr, and the gate voltage is varied by the Ids correction. It is to be noted that the same numerals are used to designate substantially the same components of the display unit1according to the above-described first embodiment, and the description thereof will be appropriately omitted.

As shown inFIG. 55, the display unit300includes a display section310and a drive section320. The display section310includes sub-pixels311. The drive section320includes a timing generation section322, a scanning line drive section323, a control line drive section324, a power control line drive section325, and a data line drive section327.

FIG. 67illustrates an example of a circuit configuration of the sub-pixel311. The sub-pixel311includes the write transistor WSTr, the drive transistor DRTr, the control transistors AZ1Tr, AZ2Tr, and AZ3Tr, the power transistor DSTr, and the capacitor Csub.

The write transistor WSTr, the drive transistor DRTr, and the control transistors AZ2Tr and AZ3Tr may each be configured, for example, of a TFT of an N-channel MOS type. The control transistor AZ1Tr and the power transistor DSTr may each be configured, for example, of a TFT of a P-channel MOS type. The gate of the write transistor WSTr is connected to the scanning line WSL, the source thereof is connected to the data line DTL, and the drain thereof is connected to the source of the drive transistor DRTr and the first end of the capacitor Cs. The gate of the drive transistor DRTr is connected to the second end of the capacitor Cs and the like, the drain thereof is connected to the drain of the power transistor DSTr and the like, and the source thereof is connected to the drain of the write transistor WSTr, the first end of the capacitor Cs, the anode of the organic EL device OLED, and the like. The gate of the control transistor AZ1Tr is connected to the control line AZ1L, the source thereof is supplied with the voltage Vini by the drive section320, and the drain thereof is connected to the gate of the drive transistor DRTr, the second end of the capacitor Cs, and the like. The gate of the control transistor AZ2Tr is connected to the control line AZ2L, the source thereof is supplied with the voltage Vofs by the drive section320, and the drain thereof is connected to the drain of the write transistor WSTr, the source of the drive transistor DRTr, the first end of the capacitor Cs, and the like. The gate of the control transistor AZ3Tr is connected to the control line AZ3L, one of the source and the drain thereof is connected to the gate of the drive transistor DRTr, the second end of the capacitor Cs, and the like, and the other of the source and the drain thereof is connected to the drain of the drive transistor DRTr, and the like. The gate of the power transistor DSTr is connected to the power control line DSL, the source thereof is supplied with the voltage Vccp by the drive section320, and the drain thereof is connected to the drain of the drive transistor DRTr, and the like.

One end of the capacitor Csub is connected to the source of the drive transistor DRTr, the second end of the capacitor Cs, and the like, and the other end of the capacitor Csub is supplied with the voltage V1by the drive section320. The voltage V1may be any direct-current voltage, and may be, for example, any of the voltages Vccp, Vini, Vofs, and Vcath.

The write transistor WSTr corresponds to a specific but not limitative example of “sixteenth transistor” in one embodiment of the present disclosure. The control transistor AZ3Tr corresponds to a specific but not limitative example of “seventeenth transistor” in one embodiment of the present disclosure.

FIG. 68is a timing chart of display operation in the display unit300. InFIG. 68, Part (A) shows the waveform of the scanning signal WS, Part (B) shows the waveform of the control signal AZ1, Part (C) shows the waveform of the control signal AZ2, Part (D) shows the waveform of the control signal AZ3, Part (E) shows the waveform of the power control signal DS, Part (F) shows the waveform of the signal Sig, Part (G) shows the waveform of the gate voltage Vg of the drive transistor DRTr, and Part (H) shows the waveform of the source voltage Vs of the drive transistor DRTr.

First, the drive section320writes the pixel voltage Vsig in the sub-pixel311and initializes the sub-pixel311in a period (write period P1) from timing t151to timing t152. Specifically, first, at the timing t151, the data line drive section327sets the signal Sig to the pixel voltage Vsig (Part (F) inFIG. 68), and the scanning line drive section323allows the voltage of the scanning signal WS to be varied from a low level to a high level (Part (A) inFIG. 68). Accordingly, the write transistor WSTr is turned on, and the source voltage Vs of the drive transistor DRTr is set to the pixel voltage Vsig (Part (H) inFIG. 68). At the same time, the control line drive section324allows the voltage of the control signal AZ1to be varied from a high level to a low level (Part (B) inFIG. 66). Accordingly, the control transistor AZ1Tr is turned on, and the gate voltage Vg of the drive transistor DRTr is set to the voltage Vini (Part (G) inFIG. 68). Thus, the sub-pixel311is initialized.

Subsequently, at the timing t152, the control line drive section324allows the voltage of the control signal AZ1to be varied from the low level to the high level (Part (B) inFIG. 68). Accordingly, the control transistor AZ1Tr is turned off, and the supply of the voltage Vini to the gate of the drive transistor DRTr is stopped.

Subsequently, the drive section320performs the Ids correction on the sub-pixel311in a period (Ids correction period P2) from timing t153to timing t154. Specifically, at the timing t153, the control line drive section324allows the voltage of the control signal AZ3to be varied from a low level to a high level (Part (D) inFIG. 68). Accordingly, the control transistor AZ3Tr is turned on, and the drain and the gate of the drive transistor DRTr are connected to each other through the control transistor AZ3Tr (a so-called “diode connection”). Accordingly, a current is flown from the gate to the source of the drive transistor DRTr through the drain thereof, and the gate voltage Vg is decreased (Part (G) inFIG. 68). Since the gate voltage Vg is thus decreased, the current flown from the drain to the source of the drive transistor DRTr is decreased. With this negative feedback operation, the gate voltage Vg is decreased in a slower pace over time. A length of the time period (from the timing t153to the timing t154) for performing the Ids correction is determined in order to suppress variations in the current that flows through the drive transistor DRTr at the timing t154as described in the above first embodiment.

Subsequently, at the timing t154, the control line drive section324allows the voltage of the control signal AZ3to be varied from the high level to the low level (Part (D) inFIG. 68). Accordingly, the control transistor AZ3Tr is turned off. Therefore, after this, the voltage between the terminals of the capacitor Cs, that is, the gate-source voltage Vgs of the drive transistor DRTr is maintained.

Subsequently, at timing t155, the scanning line drive section323allows the voltage of the scanning signal WS to be varied from the high level to the low level (Part (A) inFIG. 68). Accordingly, the write transistor WSTr is turned off.

Subsequently, the drive section320allows the sub-pixel311to emit light in a period (light emission period P3) that begins from timing t156. Specifically, at the timing t156, the power control line drive section325allows the voltage of the power control signal DS to be varied from the high level to the low level (Part (D) inFIG. 68). Accordingly, the power transistor DSTr is turned on, the current Ids is flown into the drive transistor DRTr, and the source voltage Vs of the drive transistor DRTr is increased (Part (H) inFIG. 68). In accordance therewith, the gate voltage Vg of the drive transistor DRTr is also increased (Part (G) inFIG. 68). In this example, the source voltage Vs is increased until the source voltage Vs becomes higher than the drain voltage (the voltage Vcath+an on-voltage Von of the organic EL device). When the source voltage Vs of the drive transistor DRTr becomes higher than the sum (Vel+Vcath) of the threshold voltage Vel and the voltage Vcath of the organic EL device OLED, a current flows between the anode and the cathode of the organic EL device OLED, which allows the organic EL device OLED to emit light. In other words, the source voltage Vs is increased in accordance with the device variations in the organic EL devices OLED, and the organic EL device OLED emits light.

Subsequently, in the display unit300, the transition is made from the light emission period P3to the write period P1after a predetermined period (one frame period) has passed. The drive section320so drives the sub-pixel311that the above-described series of operation is repeated.

Effects similar to those in the above-described first embodiment and the like are obtainable also with such a configuration.

In the above-described ninth embodiment, the voltage Vini is supplied to the gate of the drive transistor DRTr by allowing the control transistor AZ1Tr to be ON in the write period P1. However, this is not limitative. Alternatively, for example, the voltage Vccp may be supplied to the gate of the drive transistor DRTr by allowing the control transistor AZ1Tr to be ON as shown inFIGS. 69 and 70.

In the above-described ninth embodiment, the control transistor AZ2Tr is provided in the sub-pixel311. However, this is not limitative. Alternatively, for example, the control transistor AZ2Tr may not be provided.

In the above-described ninth embodiment, the voltage Vini is supplied to the gate of the drive transistor DRTr by allowing the control transistor AZ1Tr to be ON in the write period P1. However, this is not limitative. Alternatively, for example, the voltage Vccp may be supplied to the gate of the drive transistor DRTr by allowing the power transistor DSTr to be ON. The present modification will be described below in detail.

FIG. 71illustrates a configuration example of a display unit300C according to the present modification. The display unit300C includes a display section310C and a drive section320C. The display section310C includes a plurality of sub-pixels311C and the plurality of control lines AZ3L that extend in the row direction. One end of each of the control lines AZ3L is connected to the drive section320C.

FIG. 72illustrates an example of a circuit configuration of the sub-pixel311C. The sub-pixel311C has a configuration in which the control transistors AZ1Tr and AZ2Tr are omitted from the sub-pixel311according to the above-described ninth embodiment. The power transistor DSTr corresponds to a specific but not limitative example of “eighteenth transistor” in one embodiment of the present disclosure.

The drive section320C includes a timing generation section322C, a scanning line drive section323C, a control line drive section324C, a power control line drive section325C, and a data line drive section327C. The timing generation section322C is a circuit that supplies a control signal to each of the scanning line drive section323C, the control line drive section324C, the power control drive section325C, and the data line drive section327C based on the synchronization signal Ssync that is supplied from the outside, and thereby controlling these sections to operate in synchronization with each other. The control line drive section324C sequentially applies control signals AZ3to the plurality of control lines AZ3L in accordance with the control signal supplied from the timing generation section322C. The scanning drive section323C, the power control line drive section325C, and the data line drive section327C have functions similar to those of the scanning line drive section23, the power control line drive section25A, and the data line drive section27, respectively.

FIG. 73is a timing chart of display operation in the display unit300C. InFIG. 73, Part (A) shows the waveform of the scanning signal WS, Part (B) shows the waveform of the control signal AZ3, Part (C) shows the waveform of the power control signal DS, Part (D) shows the waveform of the signal Sig, Part (E) shows the waveform of the gate voltage Vg of the drive transistor DRTr, and Part (F) shows the waveform of the source voltage Vs of the drive transistor DRTr.

First, the drive section320C writes the pixel voltage Vsig in the sub-pixel311C and initializes the sub-pixel311C in a period (write period P1) from timing t161to timing t162. Specifically, first, at the timing t161, the data line drive section327C sets the signal Sig to the pixel voltage Vsig (Part (D) inFIG. 73), and the scanning line drive section323C allows the voltage of the scanning signal WS to be varied from a low level to a high level (Part (A) inFIG. 73). Accordingly, the write transistor WSTr is turned on, and the source voltage Vs of the drive transistor DRTr is set to the pixel voltage Vsig (Part (F) inFIG. 73). At the same time, the control line drive section324C allows the voltage of the control signal AZ3to be varied from a low level to a high level (Part (B) inFIG. 73). Accordingly, the control transistor AZ3Tr is turned on, and the drain and the gate of the drive transistor DRTr are connected to each other through the control transistor AZ3Tr (a so-called “diode connection”). Further, the power control line drive section325C allows the voltage of the power control signal DS to be varied from a high level to a low level (Part (C) inFIG. 73). Accordingly, the power transistor DSTr is turned on, and the gate voltage Vg of the drive transistor DRTr is set to the voltage Vccp (Part (E) inFIG. 73). Thus, the sub-pixel311C is initialized.

Subsequently, the drive section320performs the Ids correction on the sub-pixel311C in a period (Ids correction period P2) from timing t162to timing t163. Specifically, at the timing t162, the power control line drive section325C allows the voltage of the power control signal DS to be varied from the low level to the high level (Part (C) inFIG. 73). Accordingly, the power transistor DRTr is turned off. Consequently, a current is flown from the gate to the source of the drive transistor DRTr through the drain thereof, and the gate voltage Vg is decreased (Part (E) inFIG. 73). Thus, the drive section320C performs the Ids correction as in the above-described ninth embodiment.

Subsequently, at the timing t163, the control line drive section324C allows the voltage of the control signal AZ3to be varied from a high level to a low level (Part (B) inFIG. 73). Accordingly, the control transistor AZ3Tr is turned off.

Subsequently, at timing t164, the scanning line drive section323C allows the voltage of the scanning signal WS to be varied from the high level to the low level (Part (A) inFIG. 73). Accordingly, the write transistor WSTr is turned off.

After the Ids correction is completed, the drive section320C allows the sub-pixel311C to emit light in a period (light emission period P3) that begins from timing t165, as in the above-described ninth embodiment.

Effects similar to those in the above-described ninth embodiment are obtainable also with such a configuration.

Moreover, also in the present modification, for example, the sub-pixel may further include other transistors as will be described below.

FIG. 74illustrates a configuration example of a display unit300D according to the present modification. The display unit300D includes a display section310D and a drive section320D. The display section310D includes a plurality of sub-pixels311D and the plurality of control lines AZ2L that extend in the row direction. One end of each of the control lines AZ2L is connected to the drive section320D.

FIG. 75illustrates an example of a circuit configuration of the sub-pixel311D. The sub-pixel311D includes the control transistor AZ2Tr. The gate of the control transistor AZ2Tr is connected to the control line AZ2L, the source thereof is supplied with the voltage Vofs by the drive section320D, and the drain thereof is connected to the source of the drive transistor DRTr, the first end of the capacitor Cs, and the like.

Also with such a configuration, the same method as the driving method shown inFIG. 73is achievable by allowing the control signal AZ2to be mostly at the low level (L) (Part (B) inFIG. 76) to allow the control transistor AZ2Tr to be mostly OFF, as shown inFIG. 76.

Next, a display unit700A according to a tenth embodiment will be described. In the present embodiment, the Vth correction described in the fifth embodiment is performed with the use of a configuration similar to that of the display unit100according to the above-described eighth embodiment and the like. It is to be noted that the same numerals are used to designate substantially the same components of the display units according to the above-described fifth and eighth embodiments and the like, and the description thereof will be appropriately omitted.

As shown inFIGS. 55 and 56, the display unit700A includes a display section110A and a drive section720A. The display section110A includes the sub-pixels111A. The drive section720A includes a scanning line drive section723A, a control line drive section724A, a power control line drive section725A, and a data line drive section727A.

FIG. 77is a timing chart of display operation in the display unit700A. InFIG. 77, Part (A) shows the waveform of the scanning signal WS, Part (B) shows the waveform of the control signal AZ1, Part (C) shows the waveform of the control signal AZ2, Part (D) shows the waveform of the control signal AZ3, Part (E) shows the waveform of the power control signal DS, Part (F) shows the waveform of the signal Sig, Part (G) shows the waveform of the gate voltage Vg of the drive transistor DRTr, and Part (H) shows the waveform of the source voltage Vs of the drive transistor DRTr.

First, the drive section720A initializes the sub-pixel111A in a period (initialization period P11) from timing t171to timing t172. Specifically, at the timing t171, the control line drive section724A allows the voltage of the control signal AZ1to be varied from a high level to a low level (Part (B) inFIG. 77), and allows the voltage of the control signal AZ2to be varied from a high level to a low level (Part (C) inFIG. 77). Accordingly, the control transistors AZ1Tr and AZ2Tr are turned on. Accordingly, the source voltage Vs of the drive transistor DRTr is set to the voltage Vini (Part (H) inFIG. 77), and the gate voltage Vg is set to the voltage Vofs (Part (G) inFIG. 77). Thus, the sub-pixel111A is initialized.

Subsequently, the control line drive section724A allows the voltage of the control signal AZ1to be varied from the low level to the high level (Part (B) inFIG. 77). Accordingly, the control transistor AZ1Tr is turned off, and the supply of the voltage Vini to the source of the drive transistor DRTr is stopped.

Subsequently, the drive section720A performs the Vth correction in a period (Vth correction period P12) from timing t173to timing t174. Specifically, at the timing t173, the control line drive section724A allows the voltage of the control signal AZ3to be varied from a high level to a low level (Part (D) inFIG. 77). Accordingly, the control transistor AZ3Tr is turned on, and the drain and the gate of the drive transistor DRTr are connected to each other through the control transistor AZ3Tr (a so-called “diode connection”). Accordingly, a current is flown from the source to the gate of the drive transistor DRTr through the drain thereof, and the source voltage Vs is decreased (Part (H) inFIG. 77). Thus, the gate-source voltage Vgs of the drive transistor DRTr is so converged as to be equal to the threshold voltage Vth of the drive transistor DRTr (Vgs=Vth).

Subsequently, the control line drive section724A allows the voltage of the control signal AZ3to be varied from the low level to the high level (Part (D) inFIG. 77). Accordingly, the control transistor AZ3Tr is turned off.

Subsequently, the drive section720A writes the pixel voltage Vsig in the sub-pixel111A in a period (write period P14) from timing t176to timing t177. Specifically, at the timing t176, the scanning line drive section723A allows the voltage of the scanning signal WS to be varied from the high level to the low level (Part (A) inFIG. 77). Accordingly, the write transistor WSTr is turned on, and the gate voltage Vg of the drive transistor DRTr is decreased from the voltage Vofs to the pixel voltage Vsig (Part (G) inFIG. 77).

Subsequently, at the timing t177, the scanning line drive section723A allows the voltage of the scanning signal WS to be varied from the low level to the high level (Part (A) inFIG. 77). Accordingly, the write transistor WSTr is turned off.

Subsequently, the drive section720A allows the sub-pixel111A to emit light in a period (light emission period P16) that begins from timing t178, as with the drive section70A (FIG. 38) according to the above-described fifth embodiment.

Effects similar to those in the above-described fifth embodiment and the like are obtainable also with such a configuration.

In the above-described tenth embodiment, the voltage Vofs is supplied to the gate of the drive transistor DRTr by allowing the control transistor AZ2Tr to be ON in the initialization period P11. However, this is not limitative. Alternatively, for example, the voltage Vofs may be supplied to the gate of the drive transistor DRTr by allowing the write transistor WSTr to be ON. The present modification will be described below in detail.

As shown inFIGS. 52 and 53, a display unit700B according to the present modification includes the display section110and a drive section720B. The display section110includes the sub-pixels111. The drive section720B includes a scanning line drive section723B, a control line drive section724B, a power control line drive section725B, and a data line drive section727B.

FIG. 78is a timing chart of display operation in the display unit700B. InFIG. 78, Part (A) shows the waveform of the scanning signal WS, Part (B) shows the waveform of the control signal AZ1, Part (C) shows the waveform of the control signal AZ3, Part (D) shows the waveform of the power control signal DS, Part (E) shows the waveform of the signal Sig, Part (F) shows the waveform of the gate voltage Vg of the drive transistor DRTr, and Part (G) shows the waveform of the source voltage Vs of the drive transistor DRTr.

First, the drive section720B initializes the sub-pixel111in a period (initialization period P11) from timing t181to timing t182. Specifically, at the timing t181, the data line drive section727B sets the signal Sig to the voltage Vofs (Part (E) inFIG. 78), and the scanning line drive section723B allows the voltage of the scanning line WS to be varied from a high level to a low level (Part (A) inFIG. 78). Accordingly, the write transistor WSTr is turned on, and the gate voltage Vg of the drive transistor DRTr is set to the voltage Vofs (Part (F) inFIG. 78). At the same time, the control line drive section724B allows the voltage of the control signal AZ1to be varied from a high level to a low level (Part (B) inFIG. 78). Accordingly, the control transistor AZ1Tr is turned on, and the source voltage Vs of the drive transistor DRTr is set to the voltage Vini (Part (G) inFIG. 78). Thus, the sub-pixel111is initialized.

Subsequently, at timing t182, the control line drive section724A allows the voltage of the control signal AZ1to be varied from the low level to the high level (Part (B) inFIG. 78). Accordingly, the control transistor AZ1Tr is turned off, and the supply of the voltage Vini to the source of the drive transistor DRTr is stopped.

Subsequently, the drive section720B performs the Vth correction in a period (Vth correction period P12) from timing t183to timing t184as with the drive section720A (FIG. 77) according to the above-described tenth embodiment.

Subsequently, the drive section720B writes the pixel voltage Vsig in the sub-pixel111in a period (write period P14) from timing t185to timing t186. Specifically, at the timing t185, the data line drive section727B allows the signal Sig to be varied from the voltage Vofs to the pixel voltage Vsig (Part (E) inFIG. 78). Accordingly, the gate voltage Vg of the drive transistor DRTr is decreased from the voltage Vofs to the pixel voltage Vsig (Part (F) inFIG. 78).

Subsequently, at the timing t186, the scanning line drive section723B allows the voltage of the scanning signal WS to be varied from the low level to the high level (Part (A) inFIG. 78). Accordingly, the write transistor WSTr is turned off.

Subsequently, the drive section720B allows the sub-pixel111to emit light in a period (light emission period P16) that begins from the timing t187, as with the drive section720(FIG. 77) according to the above-described tenth embodiment.

Effects similar to those in the above-described tenth embodiment are obtainable also with such a configuration.

Moreover, in the display unit700B, the voltage Vini may be supplied to the source of the drive transistor DRTr by allowing the power transistor DSTr to be ON, as will be described below.

As shown inFIGS. 58 and 59, the display unit700C according to the present modification includes the display section110B and a drive section720C. The display section110B includes the sub-pixels111B. The drive section720C includes a scanning line drive section723C, a control line drive section724C, a power control line drive section725C, a power line drive section726C, and a data line drive section727C.

FIG. 79is a timing chart of display operation in the display unit700C. InFIG. 79, Part (A) shows the waveform of the scanning signal WS, Part (B) shows the waveform of the control signal AZ3, Part (C) shows the waveform of the power control signal DS, Part (D) shows the waveform of the power signal DS2, Part (E) shows the waveform of the signal Sig, Part (F) shows the waveform of the gate voltage Vg of the drive transistor DRTr, and Part (G) shows the waveform of the source voltage Vs of the drive transistor DRTr.

First, at timing t191prior to the initialization period P11, the power line drive section726C allows the power signal DS2to be varied from the voltage Vccp to the voltage Vini (Part (D) inFIG. 79).

Subsequently, the drive section720C initializes the sub-pixel111B in a period (initialization period P11) from timing t192to timing t193. Specifically, at the timing t192, the data line drive section727C sets the signal Sig to the voltage Vofs (Part (E) inFIG. 79), and the scanning line drive section723C allows the voltage of the scanning line WS to be varied from a high level to a low level (Part (A) inFIG. 79). Accordingly, the write transistor WSTr is turned on, and the gate voltage Vg of the drive transistor DRTr is set to the voltage Vofs (Part (F) inFIG. 79). At the same time, the power control line drive section725C allows the voltage of the power control signal DS to be varied from a high level to a low level (Part (C) inFIG. 79). Accordingly, the power transistor DSTr is turned on, and the source voltage Vs of the drive transistor DRTr is set to the voltage Vini (Part (G) inFIG. 79). Thus, the sub-pixel111B is initialized.

Subsequently, at the timing t193, the power control line drive section725C allows the voltage of the power control signal DS to be varied from the low level to the high level (Part (C) inFIG. 79). Accordingly, the power transistor DSTr is turned off, and the supply of the voltage Vini to the source of the drive transistor DRTr is stopped.

Subsequently, the drive section720C performs the Vth correction in a period (Vth correction period P12) from timing t194to timing t195as with the drive section720B (FIG. 78) according to the above-described modification.

Subsequently, at the timing t196, the power line drive section726C allows the power signal DS2to be varied from the voltage Vini to the voltage Vccp (Part (D) inFIG. 79).

Further, the drive section720C writes the pixel voltage Vsig in the sub-pixel111B in a period (write period P14) from timing t197to timing t198, and allows the sub-pixel111B to emit light in a period (light emission period P16) that begins from timing t199, as with the drive section720B (FIG. 78) in the above-described modification.

Effects similar to those in the above-described tenth embodiment are obtainable also with such a configuration.

Moreover, in the display unit700B, the voltage Vccp may be supplied to the source of the drive transistor DRTr by allowing the power transistor DSTr to be ON, as will be described below.

As shown inFIGS. 61 and 62, the display unit700D according to the present modification includes the display section110C and a drive section720D. The display section110C includes the sub-pixels111C. The drive section720D includes a scanning line drive section723D, a control line drive section724D, a power control line drive section725D, and a data line drive section727D.

FIG. 80is a timing chart of display operation in the display unit700D. InFIG. 80, Part (A) shows the waveform of the scanning signal WS, Part (B) shows the waveform of the control signal AZ3, Part (C) shows the waveform of the power control signal DSA, Part (D) shows the waveform of the power control signal DSB, Part (E) shows the waveform of the signal Sig, Part (F) shows the waveform of the gate voltage Vg of the drive transistor DRTr, and Part (G) shows the waveform of the source voltage Vs of the drive transistor DRTr.

First, at timing t201prior to the initialization period P11, the power control line drive section725D allows the voltage of the power control signal DSB to be varied from a low level to a high level (Part (D) inFIG. 80). Accordingly, the power transistor DSBTr is turned off.

Subsequently, the drive section720D initializes the sub-pixel111C in a period (initialization period P11) from timing t202to timing t203. Specifically, at the timing t202, the data line drive section727D sets the signal Sig to the voltage Vofs (Part (E) inFIG. 80), and the scanning line drive section723D allows the voltage of the scanning line WS to be varied from a high level to a low level (Part (A) inFIG. 80). Accordingly, the write transistor WSTr is turned on, and the gate voltage Vg of the drive transistor DRTr is set to the voltage Vofs (Part (F) inFIG. 80). At the same time, the power control line drive section725D allows the voltage of the power control signal DSA to be varied from a high level to a low level (Part (C) inFIG. 80). Accordingly, the power transistor DSATr is turned on, and the source voltage Vs of the drive transistor DRTr is set to the voltage Vccp (Part (G) inFIG. 80). Thus, the sub-pixel111C is initialized.

Subsequently, at the timing t203, the power control line drive section725D allows the voltage of the power control signal DSA to be varied from the low level to the high level (Part (C) inFIG. 80). Accordingly, the power transistor DSATr is turned off, and the supply of the voltage Vccp to the source of the drive transistor DRTr is stopped.

Subsequently, the drive section720D performs the Vth correction in a period (Vth correction period P12) from timing t204to timing t205, and writes the pixel voltage Vsig in the sub-pixel111C in a period (write period P14) from timing t206to timing t207, as with the drive section720B (FIG. 78) according to the above-described modification.

Subsequently, at the timing t208, the power control line drive section725D allows the voltage of the power control signal DSA to be varied from the high level to the low level (Part (C) inFIG. 80). Accordingly, the power transistor DSATr is turned on, and the source voltage Vs of the drive transistor DRTr is increased toward the voltage Vccp (Part (G) inFIG. 80). In accordance therewith, the gate voltage Vg of the drive transistor DRTr is also increased (Part (F) inFIG. 80).

Further, the drive section720D allows the sub-pixel111D to emit light in a period (light emission period P16) that begins from timing t210. Specifically, at the timing t210, the power control line drive section725D allows the voltage of the power control signal DSB to be varied from the high level to the low level (Part (D) inFIG. 80). Accordingly, the power transistor DSBTr is turned on, and a current is flown through a path including the power transistor DSATr, the drive transistor DRTr, the power transistor DSBTr, and the organic EL device OLED in order. Accordingly, the organic EL device OLED emits light.

Effects similar to those in the above-described tenth embodiment are obtainable also with such a configuration.

In the above-described tenth embodiment, the voltage Vini is supplied to the source of the drive transistor DRTr by allowing the control transistor AZ1Tr to be ON in the initialization period P11. However, this is not limitative. Alternatively, for example, the voltage Vccp may be supplied to the source of the drive transistor DRTr by allowing the power transistor DSTr to be ON. The present modification will be described below in detail.

As shown inFIGS. 64 and 65, the display unit700E according to the present modification includes the display section110D and a drive section720E. The display section110D includes the sub-pixels111D. The drive section720E includes a scanning line drive section723E, a control line drive section724E, a power control line drive section725E, and a data line drive section727E.

FIG. 81is a timing chart of display operation in the display unit700E. InFIG. 81, Part (A) shows the waveform of the scanning signal WS, Part (B) shows the waveform of the control signal AZ2, Part (C) shows the waveform of the control signal AZ3, Part (D) shows the waveform of the power control signal DSA, Part (E) shows the waveform of the power control signal DSB, Part (F) shows the waveform of the signal Sig, Part (G) shows the waveform of the gate voltage Vg of the drive transistor DRTr, and Part (H) shows the waveform of the source voltage Vs of the drive transistor DRTr.

First, at timing t211prior to the initialization period P11, the power control line drive section725E allows the voltage of the power control signal DSB to be varied from a low level to a high level (Part (E) inFIG. 81). Accordingly, the power transistor DSBTr is turned off.

Subsequently, the drive section720E initializes the sub-pixel111D in a period (initialization period P11) from timing t212to timing t213. Specifically, at the timing t212, the power control line drive section725E allows the voltage of the power control signal DSA to be varied from a high level to a low level (Part (D) inFIG. 81). Accordingly, the power transistor DSATr is turned on, and the source voltage Vs of the drive transistor DRTr is set to the voltage Vccp (Part (H) inFIG. 81). At the same time, the control line drive section724E allows the voltage of the control signal AZ2to be varied from a high level to a low level (Part (B) inFIG. 81). Accordingly, the control transistor AZ2Tr is turned on, and the gate voltage Vg of the drive transistor DRTr is set to the voltage Vofs (Part (G) inFIG. 81). Thus, the sub-pixel111D is initialized.

Subsequently, at the timing t213, the power control line drive section725E allows the voltage of the power control signal DSA to be varied from the low level to the high level (Part (D) inFIG. 81). Accordingly, the power transistor DSATr is turned off, and the supply of the voltage Vccp to the source of the drive transistor DRTr is stopped.

Subsequently, the drive section720E performs the Vth correction in a period (Vth correction period P12) from timing t214to timing t215as with the drive section720A (FIG. 77) according to the above-described tenth embodiment.

Subsequently, at timing t216, the power line drive section724E allows the voltage of the control signal AZ2to be varied from the low level to the high level (Part (B) inFIG. 81). Accordingly, the control transistor AZ2Tr is turned off, and the supply of the voltage Vofs to the gate of the drive transistor DRTr is stopped.

Subsequently, the drive section720E writes the pixel voltage Vsig in the sub-pixel111D in a period (write period P14) from timing t217to timing t218, as with the drive section720A (FIG. 77) according to the above-described tenth embodiment.

Subsequently, at timing t219, the power control line drive section725E allows the voltage of the power control signal DSA to be varied from the high level to the low level (Part (D) inFIG. 81). Accordingly, the power transistor DSATr is turned on, and the source voltage Vs of the drive transistor DRTr is increased toward the voltage Vccp (Part (H) inFIG. 81). In accordance therewith, the gate voltage Vg of the drive transistor DRTr is also increased (Part (G) inFIG. 81).

Further, the drive section720E allows the sub-pixel111E to emit light in a period (light emission period P16) that begins from timing t220. Specifically, at the timing t220, the power control line drive section725E allows the voltage of the power control signal DSB to be varied from the high level to the low level (Part (E) inFIG. 81). Accordingly, the power transistor DSBTr is turned on, and a current is flown through a path including the power transistor DSATr, the drive transistor DRTr, the power transistor DSBTr, and the organic EL device OLED in order. Accordingly, the organic EL device OLED emits light.

Effects similar to those in the above-described tenth embodiment are obtainable also with such a configuration.

Next, a display unit800according to an eleventh embodiment will be described. In the present embodiment, the Vth correction described in the fifth embodiment is performed with the use of a configuration similar to that of the display unit300according to the above-described ninth embodiment. It is to be noted that the same numerals are used to designate substantially the same components of the display units according to the above-described fifth and ninth embodiments and the like, and the description thereof will be appropriately omitted.

As shown inFIGS. 55 and 67, the display unit800includes the display section310and a drive section820. The display section310includes the sub-pixels311. The drive section820includes a scanning line drive section823, a control line drive section824, a power control line drive section825, and a data line drive section827.

FIG. 82is a timing chart of display operation in the display unit800. InFIG. 82, Part (A) shows the waveform of the scanning signal WS, Part (B) shows the waveform of the control signal AZ1, Part (C) shows the waveform of the control signal AZ2, Part (D) shows the waveform of the control signal AZ3, Part (E) shows the waveform of the power control signal DS, Part (F) shows the waveform of the signal Sig, Part (G) shows the waveform of the gate voltage Vg of the drive transistor DRTr, and Part (H) shows the waveform of the source voltage Vs of the drive transistor DRTr.

First, the drive section820initializes the sub-pixel311in a period (initialization period P11) from timing t221to timing t222. Specifically, at the timing t221, the control line drive section824allows the voltage of the control signal AZ1to be varied from a high level to a low level (Part (B) inFIG. 82), and allows the voltage of the control signal AZ2to be varied from a low level to a high level (Part (C) inFIG. 82). Accordingly, the control transistors AZ1Tr and AZ2Tr are turned on. Accordingly, the gate voltage Vg of the drive transistor DRTr is set to the voltage Vini (Part (G) inFIG. 82), and the source voltage Vs is set to the voltage Vofs (Part (H) inFIG. 82). Thus, the sub-pixel311is initialized.

Subsequently, at the timing t222, the control line drive section824allows the voltage of the control signal AZ1to be varied from the low level to the high level (Part (B) inFIG. 82). Accordingly, the control transistor AZ1Tr is turned off, and the supply of the voltage Vini to the gate of the drive transistor DRTr is stopped.

Subsequently, the drive section820performs the Vth correction in a period (Vth correction period P12) from timing t223to timing t224. Specifically, at the timing t223, the control line drive section824allows the voltage of the control signal AZ3to be varied from a low level to a high level (Part (D) inFIG. 82). Accordingly, the control transistor AZ3Tr is turned on, and the drain and the gate of the drive transistor DRTr are connected to each other through the control transistor AZ3Tr (a so-called “diode connection”). Accordingly, a current is flown from the gate to the source of the drive transistor DRTr through the drain thereof, and the gate voltage Vg is decreased (Part (G) inFIG. 82). Thus, the gate-source voltage Vgs of the drive transistor DRTr is so converged as to be equal to the threshold voltage Vth of the drive transistor DRTr (Vgs=Vth).

Subsequently, at the timing t224, the control line drive section824allows the voltage of the control signal AZ3to be varied from the high level to the low level (Part (D) inFIG. 82). Accordingly, the control transistor AZ3Tr is turned off. Further, at timing t225, the control line drive section824allows the voltage of the control signal AZ2to be varied from the high level to the low level (Part (C) inFIG. 82). Accordingly, the control transistor AZ2Tr is turned off, and the supply of the voltage Vofs to the source of the drive transistor DRTr is stopped.

Subsequently, the drive section820writes the pixel voltage Vsig in the sub-pixel311in a period (write period P14) from timing t226to timing t227. Specifically, at the timing t226, the scanning line drive section823allows the voltage of the scanning signal WS to be varied from a low level to a high level (Part (A) inFIG. 82). Accordingly, the write transistor WSTr is turned on, and the source voltage Vs of the drive transistor DRTr is decreased from the voltage Vofs to the pixel voltage Vsig (Part (H) inFIG. 82).

Subsequently, at the timing t227, the scanning line drive section823allows the voltage of the scanning signal WS to be varied from the high level to the low level (Part (A) inFIG. 82). Accordingly, the write transistor WSTr is turned off.

Further, the drive section820allows the sub-pixel311to emit light in a period (light emission period P16) that begins from timing t228as with the drive section70A (FIG. 38) according to the above-described fifth embodiment.

Effects similar to those in the above-described fifth embodiment and the like are obtainable also in such a configuration.

In the above-described eleventh embodiment, the voltage Vini is supplied to the gate of the drive transistor DRTr by allowing the control transistor AZ1Tr to be ON in the initialization period P11. However, this is not limitative. Alternatively, for example, the voltage Vccp may be supplied to the gate of the drive transistor DRTr by allowing the control transistor AZ1Tr to be ON as shown inFIGS. 55, 69, and 83.

In the above-described eleventh embodiment, the voltage Vini is supplied to the gate of the drive transistor DRTr by allowing the control transistor AZ1Tr to be ON in the initialization period P11. However, this is not limitative. Alternatively, for example, the voltage Vccp may be supplied to the gate of the drive transistor DRTr by allowing the power transistor DSTr to be ON. The present modification will be described below in detail.

As shown inFIGS. 74 and 75, a display unit800B according to the present modification includes the display section310D and a drive section820B. The display section310D includes the sub-pixels311D. The drive section820B includes a scanning line drive section823B, a control line drive section824B, a power control line drive section825B, and a data line drive section827B.

FIG. 84is a timing chart of display operation in the display unit800B. InFIG. 84, Part (A) shows the waveform of the scanning signal WS, Part (B) shows the waveform of the control signal AZ2, Part (C) shows the waveform of the control signal AZ3, Part (D) shows the waveform of the power control signal DS, Part (E) shows the waveform of the signal Sig, Part (F) shows the waveform of the gate voltage Vg of the drive transistor DRTr, and Part (G) shows the waveform of the source voltage Vs of the drive transistor DRTr.

First, the drive section820B initializes the sub-pixel311D in a period (initialization period P11) from timing t231to timing t232. Specifically, at the timing t231, the control line drive section824B allows the voltage of the control signal AZ2to be varied from a low level to a high level (Part (B) inFIG. 84). Accordingly, the control transistor AZ2Tr is turned on, and the source voltage Vs of the drive transistor DRTr is set to the voltage Vofs (Part (G) inFIG. 84). At the same time, the control line drive section824B allows the voltage of the control signal AZ3to be varied from a low level to a high level (Part (C) inFIG. 84). Accordingly, the control transistor AZ3Tr is turned on, and the drain and the gate of the drive transistor DRTr are connected to each other through the control transistor AZ3Tr (a so-called “diode connection”). Further, the power control line drive section825B allows the voltage of the power control signal DS to be varied from a high level to a low level (Part (D) inFIG. 84). Accordingly, the power transistor DSTr is turned on, and the gate voltage Vg of the drive transistor DRTr is set to the voltage Vccp (Part (F) inFIG. 84). Thus, the sub-pixel311D is initialized.

Subsequently, the drive section820B performs the Vth correction in a period (Vth correction period P12) from timing t232to timing t233. Specifically, at the timing t232, the power control line drive section825B allows the voltage of the power control signal DS to be varied from the low level to the high level (Part (D) inFIG. 84). Accordingly, the power transistor DSTr is turned off. Accordingly, a current is flown from the gate to the source of the drive transistor DRTr through the drain thereof, and the gate voltage Vg is decreased (Part (F) inFIG. 84). Thus, the gate-source voltage Vgs of the drive transistor DRTr is so converged as to be equal to the threshold voltage Vth of the drive transistor DRTr (Vgs=Vth).

Subsequently, at the timing t233, the control line drive section824B allows the voltage of the control signal AZ3to be varied from the high level to the low level (Part (C) inFIG. 84). Accordingly, the control transistor AZ3Tr is turned off. Subsequently, at timing t234, the control line drive section824B allows the voltage of the control signal AZ2to be varied from the high level to the low level (Part (B) inFIG. 84). Accordingly, the control transistor AZ2Tr is turned off, and the supply of the voltage Vofs to the source of the drive transistor DRTr is stopped.

Subsequently, the drive section820B writes the pixel voltage Vsig in the sub-pixel311D in a period (write period P14) from timing t235to timing t236, and allows the sub-pixel311D to emit light in a period (light emission period P16) that begins from timing t237, as with the drive section820(FIG. 82) according to the above-described eleventh embodiment.

Effects similar to those in the above-described eleventh embodiment are obtainable also with such a configuration.

Moreover, in the display unit800B, the control signal AZ2and the control signal AZ3may be a common signal, as will be described below.

As shown inFIG. 71, the display unit800C according to the present modification includes a display section810C and a drive section820C. The display section810C includes sub-pixels811C. In the display section810C, the control lines AZ2L is eliminated compared to the sub-pixels310D according to the display unit800B. The drive section820C includes a scanning line drive section823C, a control line drive section824C, a power control line drive section825C, and a data line drive section827C.

FIG. 85illustrates an example of a circuit configuration of the sub-pixel811C. The sub-pixel811C has a configuration in which the gate of the control transistor AZ2Tr is connected to the control signal line AZ3L in the sub-pixel311D according to the display unit800B.

FIG. 86is a timing chart of display operation in the display unit800C. InFIG. 86, Part (A) shows the waveform of the scanning signal WS, Part (B) shows the waveform of the control signal AZ3, Part (C) shows the waveform of the power control signal DS, Part (D) shows the waveform of the signal Sig, Part (E) shows the waveform of the gate voltage Vg of the drive transistor DRTr, and Part (F) shows the waveform of the source voltage Vs of the drive transistor DRTr.

After the Vth correction in the Vth correction period P12, at timing t233, the control line drive section824C allows the voltage of the control signal AZ3to be varied from a high level to a low level (Part (B) inFIG. 86). Accordingly, the control transistors AZ2Tr and AZ3Tr are turned off at the same time.

Effects similar to those in the above-described eleventh embodiment are obtainable also with such a configuration.

In the above-described eleventh embodiment, the voltage Vofs is supplied to the source of the drive transistor DRTr by allowing the control transistor AZ2Tr to be ON in the initialization period P11. However, this is not limitative. Alternatively, for example, the voltage Vofs may be supplied to the source of the drive transistor DRTr by allowing the write transistor WSTr to be ON. The present modification will be described below in detail.

As shown inFIGS. 71 and 72, the display unit800D according to the present modification includes the display section310C and a drive section820D. The display section310C includes the sub-pixels311C. The drive section820D includes a scanning line drive section823D, a control line drive section824D, a power control line drive section825D, and a data line drive section827D.

FIG. 87is a timing chart of display operation in the display unit800D. InFIG. 87, Part (A) shows the waveform of the scanning signal WS, Part (B) shows the waveform of the control signal AZ3, Part (C) shows the waveform of the power control signal DS, Part (D) shows the waveform of the signal Sig, Part (E) shows the waveform of the gate voltage Vg of the drive transistor DRTr, and Part (F) shows the waveform of the source voltage Vs of the drive transistor DRTr.

First, the drive section820D initializes the sub-pixel311C in a period (initialization period P11) from timing t241to timing t242. Specifically, at the timing t241, the data line drive section827D sets the signal Sig to the voltage Vofs (Part (D) inFIG. 87), and the scanning line drive section823D allows the voltage of the scanning signal WS to be varied from a low level to a high level (Part (A) inFIG. 87). Accordingly, the write transistor WSTr is turned on, and the source voltage Vs of the drive transistor DRTr is set to the voltage Vofs (Part (F) inFIG. 87). At the same time, the control line drive section824D allows the voltage of the control signal AZ3to be varied from a low level to a high level (Part (B) inFIG. 87). Accordingly, the control transistor AZ3Tr is turned on, and the drain and the gate of the drive transistor DRTr are connected to each other through the control transistor AZ3Tr (a so-called “diode connection”). Further, the power control line drive section825D allows the voltage of the power control signal DS to be varied from a high level to a low level (Part (C) inFIG. 87). Accordingly, the power transistor DSTr is turned on, and the gate voltage Vg of the drive transistor DRTr is set to the voltage Vccp (Part (E) inFIG. 87). Thus, the sub-pixel311C is initialized.

Subsequently, the drive section820D performs the Vth correction in a period (Vth correction period P12) from timing t242to timing t243. Specifically, at the timing t242, the power control line drive section825D allows the voltage of the power control signal DS to be varied from the low level to the high level (Part (C) inFIG. 87). Accordingly, the power transistor DSTr is turned off. Accordingly, a current is flown from the gate to the source of the drive transistor DRTr through the drain thereof, and the gate voltage Vg is decreased (Part (E) inFIG. 87). Thus, the gate-source voltage Vgs of the drive transistor DRTr is so converged as to be equal to the threshold voltage Vth of the drive transistor DRTr (Vgs=Vth).

Subsequently, at the timing t243, the control line drive section824D allows the voltage of the control signal AZ3to be varied from the high level to the low level (Part (B) inFIG. 87). Accordingly, the control transistor AZ3Tr is turned off.

Subsequently, the drive section820D writes the pixel voltage Vsig in the sub-pixel311C in a period (write period P14) from timing t244to timing t245. Specifically, at the timing t244, the data line drive section827D allows the signal Sig to be varied from the voltage Vofs to the pixel voltage Vsig (Part (D) inFIG. 87). Accordingly, the source voltage Vs of the drive transistor DRTr is decreased from the voltage Vofs to the pixel voltage Vsig (Part (F) inFIG. 87).

Subsequently, at the timing t245, the scanning line drive section823D allows the voltage of the scanning WS to be varied from the high level to the low level (Part (A) inFIG. 87). Accordingly, the write transistor WSTr is turned off.

Further, the drive section820D allows the sub-pixel311C to emit light in a period (light emission period P16) that begins from timing t246, as with the drive section800(FIG. 82) according to the above-described eleventh embodiment.

Effects similar to those in the above-described eleventh embodiment are obtainable also with such a configuration.

Next, a display unit400according to a twelfth embodiment will be described. In the present embodiment, the sub-pixel includes three TFTs of a P-channel MOS type and one capacitor Cs. It is to be noted that the same numerals are used to designate substantially the same components of the display unit according to the above-described first embodiment and the like, and the description thereof will be appropriately omitted.

FIG. 88illustrates a configuration example of a display unit400according to the present embodiment. The display unit400includes a display section410and a drive section420.

The display section410includes a plurality of sub-pixels411. The display section410also includes the plurality of scanning lines WSL that extend in the row direction and the plurality of power control lines DSL that extend in the row direction. One end of each of the scanning lines WSL and the power control lines DSL is connected to the drive section420.

FIG. 89illustrates an example of a circuit configuration of the sub-pixel411. The write transistor WSTr, the drive transistor DRTr, and the power transistor DSTr are each configured of a TFT of a P-channel MOS type. The gate of the write transistor WSTr is connected to the scanning line WSL, the source thereof is connected to the data line DTL, and the drain thereof is connected to the gate of the drive transistor DRTr and the first end of the capacitor Cs. The gate of the drive transistor DRTr is connected to the drain of the write transistor WSTr and the first end of the capacitor Cs, the source thereof is connected to the drain of the power transistor DSTr and the second end of the capacitor Cs, and the drain thereof is connected to the anode of the organic EL device OLED. The gate of the power transistor DSTr is connected to the power control line DSL, the source thereof is supplied with the voltage Vccp by the drive section420, and the drain thereof is connected to the source of the drive transistor DRTr and the second end of the capacitor Cs.

The write transistor WSTr corresponds to a specific but not limitative example of “eleventh transistor” in one embodiment of the present disclosure. The power transistor DSTr corresponds to a specific but not limitative example of “fifteenth transistor” in one embodiment of the present disclosure.

The drive section420includes a timing generation section422, a scanning line drive section423, a power control line drive section425, and a data line drive section427. The timing generation section422is a circuit that supplies a control signal to each of the scanning line drive section423, the power control line drive section425, and the data line drive section427based on the synchronization signal Ssync that is supplied from the outside, and thereby controlling these sections to operate in synchronization with each other. The scanning line drive section423, the power control line drive section425, and the data line drive section427have functions similar to those of the scanning line drive section23, the power control line drive section25A, and the data line drive section27, respectively.

FIG. 90is a timing chart of display operation in the display unit400. InFIG. 90, Part (A) shows the waveform of the scanning signal WS, Part (B) shows the waveform of the power control signal DS, Part (C) shows the waveform of the signal Sig, Part (D) shows the waveform of the gate voltage Vg of the drive transistor DRTr, and Part (E) shows the waveform of the source voltage Vs of the drive transistor DRTr.

First, the drive section420writes the pixel voltage Vsig in the sub-pixel411and initializes the sub-pixel411in a period (write period P1) from timing t251to timing t252. Specifically, first, at the timing t251, the data line drive section427sets the signal Sig to the pixel voltage Vsig (Part (C) inFIG. 90), and the scanning line drive section423allows the voltage of the scanning signal WS to be varied from a high level to a low level (Part (A) inFIG. 90). Accordingly, the write transistor WSTr is turned on, and the gate voltage Vg of the drive transistor DRTr is set to the pixel voltage Vsig (Part (D) inFIG. 90). At the same time, the power control line drive section425allows the voltage of the power control signal DS to be varied from a high level to a low level (Part (B) inFIG. 90). Accordingly, the power transistor DSTr is turned on, and the source voltage Vs of the drive transistor DRTr is set to the voltage Vccp (Part (E) inFIG. 90). Thus, the sub-pixel411is initialized.

Subsequently, the drive section420performs the Ids correction on the sub-pixel411in a period (Ids correction period P2) from timing t252to timing t253. Specifically, at the timing t252, the power control line drive section425allows the voltage of the power control signal DS to be varied from the low level to the high level (Part (B) inFIG. 90). Accordingly, the power control transistor DSTr is turned off. Accordingly, a current is flown from the source to the drain of the drive transistor DRTr, and the source voltage Vs is decreased (Part (E) inFIG. 90). Because the source voltage Vs is thus decreased, the current flown from the source to the drain of the drive transistor DRTr is decreased. With this negative feedback operation, the source voltage Vs is decreased in a slower pace over time. A length of the time period (from the timing t252to the timing t253) for performing the Ids correction is determined in order to suppress variations in the current that flows through the drive transistor DRTr at the timing t253as described in the above first embodiment.

It is to be noted that, in the write period P1and the Ids correction period P2(the period from the timing t251to the timing t253), a current corresponding to the pixel voltage Vsig is flown through the organic EL device OLED, and the organic EL device OLED emits light. However, the period is sufficiently short relative to one frame period (1F). Therefore, such light emission does not have large influence on image quality. Moreover, for example, when the sub-pixel411displays black color, the gate-source voltage Vgs is so set that a current is not flown into the drive transistor DRTr at the timing of initialization, and therefore, occurrence of such light emission is prevented. Accordingly, black color is displayed sufficiently, and high contrast is obtained.

Subsequently, at the timing t253, the scanning line drive section423allows the voltage of the scanning signal WS to be varied from a low level to a high level (Part (A) inFIG. 90). Accordingly, the write transistor WSTr is turned off, and the supply of the pixel voltage Vsig to the gate of the drive transistor DRTr is stopped. Therefore, after this, the voltage between the terminals of the capacitor Cs, that is, the gate-source voltage Vgs of the drive transistor DRTr is maintained. Further, because a current is flown from the source to the drain of the drive transistor DRTr, the source voltage Vs of the drive transistor DRTr is decreased (Part (E) inFIG. 90). The source voltage Vs is decreased down to a voltage equivalent to the sum (Vcath+Vel) of the voltage Vcath and the threshold voltage Vel of the organic EL device OLED, and the organic EL device OLED stops emitting light. Further, the gate voltage Vg of the drive transistor DRTr is decreased in accordance with the decrease in the source voltage Vs (Part (D) inFIG. 90).

Subsequently, at timing t255, the power control line drive section425allows the voltage of the power control signal DS to be varied from the high level to the low level (Part (B) inFIG. 90). Accordingly, the power transistor DSTr is turned on, and a current is flown from the source to the drain of the drive transistor DRTr. Further, the source voltage Vs of the drive transistor DRTr is increased (Part (E) inFIG. 90), and the gate voltage Vg of the drive transistor DRTr is also increased accordingly (Part (D) inFIG. 90). Further, the drive transistor DRTr is allowed to operate in a saturation region, and a current is flown between the anode and the cathode of the organic EL device OLED. Accordingly, the organic EL device OLED emits light.

Subsequently, in the display unit400, the transition is made from the light emission period P3to the write period P1after a predetermined period (one frame period) has passed. The drive section420drives the sub-pixel411so that the above-described series of operation is repeated.

As described above, in the present embodiment, the display section is configured only of a PMOS transistor without using an NMOS transistor. Therefore, the display section may be manufactured, for example, even in a process in which the NMOS transistor is not allowed to be manufactured, such as in an organic TFT (O-TFT) process. Other effects are similar to those in the above-described first embodiment.

In the above-described twelfth embodiment, the write transistor WSTr and the power transistor DSTr are each configured of a PMOS transistor. However, this is not limitative. Alternatively, the write transistor WSTr and the power transistor DSTr may each be configured, for example, of an NMOS transistor.

In the above-described twelfth embodiment, the voltage of the scanning signal WS is varied from the low level to the high level in a short time at the timing t253. However, this is not limitative. Alternatively, as shown inFIG. 91, for example, the voltage of the scanning signal WS may be varied gradually from the low level to the high level. Thus, the length of the Ids correction period P2is allowed to be varied in accordance with the pixel voltage Vsig as in the display unit2according to the second embodiment. Therefore, image quality is improved.

Next, a display unit500according to a thirteenth embodiment will be described. In the present embodiment, operation similar to that of the display unit400according to the twelfth embodiment is achieved with the use of the sub-pixel that includes three TFTs of an N-channel MOS type and one capacitor Cs. It is to be noted that the same numerals are used to designate substantially the same components of the display unit according to the above-described twelfth embodiment and the like, and the description thereof will be appropriately omitted.

As shown inFIG. 88, the display unit500includes a display section510and a drive section520. The display section510includes sub-pixels511. The drive section520includes a scanning line drive section523, a power control line drive section525, and a data line drive section527.

FIG. 92illustrates an example of a circuit configuration of the sub-pixel511. The write transistor WSTr, the drive transistor DRTr, and the power transistor DSTr are each configured of a TFT of an N-channel MOS type. The gate of the write transistor WSTr is connected to the scanning line WSL, the source thereof is connected to the data line DTL, and the drain thereof is connected to the gate of the drive transistor DRTr and the first end of the capacitor Cs. The gate of the drive transistor DRTr is connected to the drain of the write transistor WSTr and the first end of the capacitor Cs, the source thereof is connected to the drain of the power transistor DSTr and the second end of the capacitor Cs, and the drain thereof is supplied with the voltage Vccp by the drive section520. The gate of the power transistor DSTr is connected to the power control line DSL, the source thereof is connected to the anode of the organic EL device OLED, and the drain thereof is connected to the source of the drive transistor DRTr and the second end of the capacitor Cs.

The write transistor WSTr corresponds to a specific but not limitative example of “second transistor” in one embodiment of the present disclosure. The power transistor DSTr corresponds to a specific but not limitative example of “fifth transistor” in one embodiment of the present disclosure.

FIG. 93is a timing chart of display operation in the display unit500. InFIG. 93, Part (A) shows the waveform of the scanning signal WS, Part (B) shows the waveform of the power control signal DS, Part (C) shows the waveform of the signal Sig, Part (D) shows the waveform of the gate voltage Vg of the drive transistor DRTr, and Part (E) shows the waveform of the source voltage Vs of the drive transistor DRTr.

First, the drive section520writes the pixel voltage Vsig in the sub-pixel511and initializes the sub-pixel511in a period (write period P1) from timing t261to timing t262. Specifically, first, at the timing t261, the data line drive section527sets the signal Sig to the pixel voltage Vsig (Part (C) inFIG. 93), and the scanning line drive section523allows the voltage of the scanning signal WS to be varied from a low level to a high level (Part (A) inFIG. 93). Accordingly, the write transistor WSTr is turned on, and the gate voltage Vg of the drive transistor DRTr is set to the pixel voltage Vsig (Part (D) inFIG. 93). At the same time, the power control line drive section525allows the voltage of the power control signal DS to be varied from a low level to a high level (Part (B) inFIG. 93). Accordingly, the power transistor DSTr is turned on, and a current is flown from the drive transistor DRTr to the organic EL device OLED through the power transistor DSTr. Accordingly, the source voltage Vs of the drive transistor DRTr is set to a predetermined voltage (the voltage Vcath+the on-voltage Voled1of the organic EL device OLED) (Part (E) inFIG. 93). Thus, the sub-pixel511is initialized. Here, the predetermined voltage corresponds to a specific but not limitative example of “first voltage” in one embodiment of the present disclosure.

It is to be noted that, in the write period P1(the period from the timing t261to the timing t262), a current corresponding to the pixel voltage Vsig is flown through the organic EL device OLED, and the organic EL device OLED emits light. However, the period is sufficiently short relative to one frame period (1F). Also, the current amount is sufficiently small, for example, when the sub-pixel511displays black color. Therefore, it is considered that contrast is hardly degraded.

Subsequently, the drive section520performs the Ids correction on the sub-pixel511in a period (Ids correction period P2) from the timing t262to timing t263. Specifically, at the timing t262, the power control line drive section525allows the voltage of the power control signal DS to be varied from a high level to a low level (Part (B) inFIG. 93). Accordingly, the power control transistor DSTr is turned off, and the organic EL device OLED stops emitting light. Further, a current is flown from the drain to the source of the drive transistor DRTr, and the source voltage Vs is increased (Part (E) inFIG. 93). Because the source voltage Vs is thus increased, a current flown from the drain to the source of the drive transistor DRTr is decreased. With this negative feedback operation, the source voltage Vs is decreased in a slower pace over time. A length of the time period (from the timing t262to the timing t263) for performing the Ids correction is determined in order to suppress variations in the current that is flown through the drive transistor DRTr at the timing t263as described in the above first embodiment.

Subsequently, at the timing t263, the scanning line drive section523allows the voltage of the scanning signal WS to be varied from the high level to the low level (Part (A) inFIG. 93). Accordingly, the write transistor WSTr is turned off, and the supply of the pixel voltage Vsig to the gate of the drive transistor DRTr is stopped. Therefore, after this, the voltage between the terminals of the capacitor Cs, that is, the gate-source voltage Vgs of the drive transistor DRTr is maintained. Further, because a current is flown from the drain to the source of the drive transistor DRTr, the source voltage Vs of the drive transistor DRTr is increased (Part (E) inFIG. 93). The source voltage Vs is increased toward a voltage substantially equivalent to the voltage Vccp that is applied to the drain of the drive transistor DRTr. Also, the gate voltage Vg of the drive transistor DRTr is increased in accordance with the increase in the source voltage Vs (Part (D) inFIG. 93).

Subsequently, at timing t265, the power control line drive section525allows the voltage of the power control signal DS to be varied from the low level to the high level (Power (B) inFIG. 93). Accordingly, the power transistor DSTr is turned on, and the current Ids is flown into the drive transistor DRTr. Also, the source voltage Vs of the drive transistor DRTr is decreased toward a predetermined voltage (the voltage Vcath+an on-voltage Voled2of the organic EL device OLED) (Part (E) inFIG. 93), and the gate voltage Vg of the drive transistor DRTr is also decreased accordingly (Part (D) inFIG. 93). Further, the drive transistor DRTr is allowed to operate in a saturation region, and a current is flown between the anode and the cathode of the organic EL device OLED. Accordingly, the organic EL device OLED emits light.

Subsequently, in the display unit500, the transition is made from the light emission period P3to the write period P1after a predetermined period (one frame period) has passed. The drive section520drives the sub-pixel511so that the above-described series of operation is repeated.

As described above, in the present embodiment, the display section is configured only of an NMOS transistor without using a PMOS transistor. Therefore, the display section may be manufactured, for example, even in a process in which the PMOS transistor is not allowed to be manufactured, such as in an oxide TFT (TOSTFT) process. Other effects are similar to those in the above-described first embodiment.

In the above-described thirteenth embodiment, the write transistor WSTr and the power transistor DSTr are each configured of an NMOS transistor. However, this is not limitative. Alternatively, for example, the write transistor WSTr and the power transistor DSTr may be each configured of a PMOS transistor.

In the above-described thirteenth embodiment, the voltage of the scanning signal WS is varied from the high level to the low level in a short time at the timing t263. However, this is not limitative. Alternatively, as shown inFIG. 94, for example, the voltage of the scanning signal WS may be varied gradually from the high level to the low level. Thus, the length of the Ids correction period P2is allowed to be varied in accordance with the pixel voltage Vsig as in the display unit2according to the second embodiment. Therefore, image quality is improved.

14. Comparison Between Schemes

Next, characteristics are compared taking some of the above-described display units as examples.

FIG. 95Aillustrates pixel voltage Vsig dependency of the current Ids in the display unit6according to the fourth embodiment.FIG. 95Ashows results of simulation that assumes cases in which the transistor is manufactured under a plurality of different process conditions.FIG. 95Billustrates pixel voltage Vsig dependency of the variations in the current Ids shown inFIG. 95A.

FIG. 96Aillustrates pixel voltage Vsig dependency of the current Ids in the display unit2according to the second embodiment.FIG. 96Billustrates pixel voltage Vsig dependency in the variations of the current Ids shown inFIG. 96A.

FIG. 97Aillustrates pixel voltage Vsig dependency of the current Ids in the display unit7according to the fifth embodiment.FIG. 97Billustrates pixel voltage Vsig dependency in the variations of the current Ids shown inFIG. 97A.

FIG. 98illustrates voltage Vgs dependency of the current Ids in the display unit9according to the seventh embodiment.

InFIGS. 95B, 96B, and 97B, the characteristics W3, W5, and W7each indicate a value (σ/ave.) that is obtained by dividing standard deviation by an average value, and the characteristics W4, W6, and W8each indicate a value (Range/ave.) that is obtained by dividing a width of variations by the average value.

As shown in the drawings, in the display unit6(FIGS. 95A and 95B), the display unit2(FIGS. 96A and 96B), and the display unit7(FIGS. 97A and 97B), variations in the current Ids is suppressed compared to the display unit9(FIG. 98) in which the correction for suppressing the influence, on image quality, of the device variations in the drive transistors DRTr is not performed. In particular, the variations in the current Ids are suppressed at the most in the display unit6(FIGS. 95A and 95B), and the variations are suppressed in the display unit2(FIGS. 96A and 96B) in the second place. The variations are also suppressed in the display unit7(FIGS. 97A and 97B).

On the other hand, as described above, the driving method of the display unit9is the simplest, and the driving method is more complex in order of the display units7,2, and6. In terms of robustness, freedom in design, etc., a simpler driving method is more favorable.

Moreover, as shown inFIGS. 95A, 95B, 96A, 96B, 97A, and 97B, the pixel voltage Vsig for obtaining the same current Ids is largest in the display unit6(FIGS. 95A and 95B), and becomes smaller in order of the display unit2(FIGS. 96A and 96B) and the display unit7(FIGS. 97A and 97B). In other words, in the display unit6, a high voltage is necessary for operation, which may lead to high electric power consumption. Further, withstand voltage that is necessary for the transistors configuring the sub-pixel may be increased.

As described above, these display units are, for example, in a trade-off relationship in terms of the variations in the current Ids, simplicity in the driving method, and the operation voltage. Therefore, for example, it may be desirable to select an optimum configuration depending on the device variations that is caused in the manufacturing process. Specifically, when the manufacturing process causing small device variations is used, for example, the display unit, such as the display units9and7, in which a simpler driving method is used may be selected. When the manufacturing process causing large device variations is used, for example, the display unit, such as the display units6and2, in which the variations of the current Ids are further suppressed may be selected.

15. Application Examples

Next, an application example of the display units described above in the embodiments and the modifications will be described.

FIG. 99illustrates an appearance of a television to which any of the display units according to the above-described embodiments and the like is applied. The television may include, for example, an image display screen section510that includes a front panel511and a filter glass512. The television is configured of the display unit according to any of the above-described embodiments or the like.

The display units according to the above-described embodiments and the like are applicable to electronic apparatuses in any fields such as digital cameras, notebook personal computers, mobile information terminals such as mobile phones, portable game players, and video camcorders, in addition to such a television. In other words, the display units according to the above-described embodiments and the like are applicable to electronic apparatuses in any field that display images.

Hereinabove, the present technology has been described referring to some embodiments, modifications, and application examples to electronic units. However, the present technology is not limited to the embodiments and the like, and may be variously modified.

For example, in each of the above-described embodiments and the like, the display unit includes the organic EL display element. However, this is not limitative, and the display unit may be of any kind as long as the display unit includes a current-driven display element.

It is possible to achieve at least the following configurations from the above-described example embodiments and the modifications of the disclosure.

(1) A Display Unit Including:

a pixel circuit including a display element, a first transistor having a gate and a source, and a capacitor inserted between the gate and the source of the first transistor, the first transistor supplying a current to the display element; and

a drive section driving the pixel circuit, through performing a first driving operation and performing a second driving operation after the first driving operation,

the first driving operation allowing the drive section to apply a pixel voltage to a first terminal and allowing a second terminal to be at a first voltage, the pixel voltage determining luminance of the display element, the first terminal being one of the gate and the source of the first transistor, and the second terminal being the other of the gate and the source of the first transistor, and

the second driving operation allowing the second terminal to be at a second voltage, through applying the pixel voltage to the first terminal and allowing a current to flow through the first transistor.

(2) The display unit according to (1), wherein

the display section further performs a third driving operation after the second driving operation, the third driving operation allowing voltages at both of the gate and the source of the first transistor to be varied while maintaining a voltage between the gate and the source of the first transistor at a constant voltage, under a condition of no pixel-voltage applied, and

the display section allows the display element to emit light at a timing after the third driving operation.

(3) The display unit according to (1) or (2), wherein

the pixel circuit further includes a second transistor that allows, through turning on, the pixel voltage to be applied to the gate of the first transistor,

the source of the first transistor is connected to the display element, and

the drive section allows the second transistor to turn on during the first and second driving operations.

(4) The display unit according to (3), wherein the drive section allows an effective on-period of the second transistor to be varied in accordance with a level of the pixel voltage.

(5) The display unit according to (4), wherein

the second transistor has a gate connected to the drive section, and

the drive section applies, to a gate of the second transistor, a gate pulse having a pulse shape where a voltage level in a rear-end section of pulse width gradually varies with time.

(6) The display unit according to any one of (3) to (5), wherein

the first transistor has a drain connected to the drive section,

the drive section applies, during the first driving operation, the first voltage to the source of the first transistor through the drain of the first transistor, and

the drive section applies, during the second driving operation, a third voltage to the drain of the first transistor, thereby allowing a current to flow through the first transistor.

(7) The display unit according to (6), wherein

the pixel circuit further includes a third transistor that allows, through turning on, the drain of the first transistor to be connected to the drive section,

the drive section allows, during the first and second driving operations, the third transistor to turn on, thereby allowing a voltage to be applied to the first transistor through the third transistor, and

during a time period between the first driving operation and the second driving operation, the drive section allows the third transistor to turn off, and allows the voltage applied to the third transistor to be varied from the first voltage to the third voltage.

(8) The display unit according to any one of (3) to (5), wherein

the first transistor has a drain connected to the drive section,

the pixel circuit further includes a third transistor that allows, through turning on, a third voltage to be applied to the drain of the first transistor,

the drive section allows the third transistor to turn off during the first driving operation, and

the drive section allows the third transistor to turn on, thereby allowing a current to flow through the first transistor during the second driving operation.

(9) The display unit according to (8), wherein

the pixel circuit further includes a fourth transistor that allows, through turning on, the first voltage to be applied to the source of the first transistor, and

the drive section allows the fourth transistor to turn on during the first driving operation, and allows the fourth transistor to turn off during the second driving operation.

(10) The display unit according to any one of (3) to (5), wherein

the pixel circuit further includes a fifth transistor that allows, through turning on, the source of the first transistor to be connected to the display element,

the drive section allows, during the first driving operation, the fifth transistor to turn on, thereby allowing a current to flow through the first transistor and allowing the source of the first transistor to be at the first voltage, and

the drive section allows the fifth transistor to turn off during the second driving operation.

(11) The display unit according to (1) or (2), wherein

the pixel circuit further includes a sixth transistor that allows, through turning on, the pixel voltage to be applied to the source of the first transistor,

the first transistor has a drain connected to the display element, and

the drive section allows the sixth transistor to turn on during the first and second driving operations.

(12) The display unit according to (11), wherein

the pixel circuit further includes a seventh transistor that allows, through turning on, the gate of the first transistor to be connected to the drain of the first transistor, and

the drive section allows the seventh transistor to turn off during the first driving operation, and allows the seventh transistor to turn on during the second driving operation.

(13) The display unit according to (11) or (12), wherein

the pixel circuit further includes an eighth transistor that allows, through turning on, the first voltage to be applied to the gate of the first transistor,

the drive section allows the eighth transistor to turn on during the first driving operation, and allows the eighth transistor to turn off during the second drive operation.

(14) The display unit according to any one of (11) to (13), wherein

the pixel circuit further includes

a ninth transistor that allows, through turning on, the drain of the first transistor to be connected to the display element, and

a tenth transistor that allows, through turning on, a third voltage to be applied to the source of the first transistor, and

the drive section allows both the ninth and tenth transistors to turn off during the first and second driving operations.

(15) The display unit according to (1) or (2), wherein

the pixel circuit further includes an eleventh transistor that allows, through turning on, the pixel voltage to be applied to the gate of the first transistor,

the first transistor has a drain connected to the display element, and

the drive section allows the eleventh transistor to turn on during the first and second driving operations.

(16) The display unit according to (15), wherein

the pixel circuit further includes a twelfth transistor that allows, thorough turning on, the gate of the first transistor to be connected to the drain of the first transistor,

during the first driving operation, the drive section applies the first voltage to the source of the first transistor and allows the twelfth transistor to turn off, and

the drive section allows, during the second driving operation, the twelfth transistor to turn on, thereby allowing a current to flow through the first transistor.

(17) The display unit according to (15) or (16), wherein

the pixel circuit further includes a thirteenth transistor that allows, through turning on, the source of the first transistor to be connected to the drive section,

the drive section allowing, during the first driving operation, the thirteenth transistor to turn on, thereby applying the first voltage to the source of the first transistor through the thirteenth transistor, and

after the first driving operation, the drive section allows the thirteenth transistor to turn off and allows a voltage applied to the thirteenth transistor to be varied from the first voltage to a third voltage.

(18) The display unit according to (17), wherein

the pixel circuit further includes a fourteenth transistor that allows, through turning on, the drain of the first transistor to be connected to the display element, and

the drive section allows the fourteenth transistor to turn off during the first and second driving operations.

(19) The display unit according to (15), wherein the drive section allows an effective on-period of the eleventh transistor to be varied in accordance with a level of the pixel voltage.

(20) The display unit according to (15) or (19), wherein

the pixel circuit further includes a fifteenth transistor that allows, through turning on, the first voltage to be applied to the source of the first transistor,

the drive section allows the fifteenth transistor to turn on during the first driving operation, and

the drive section allows the fifteenth transistor to turn off during the second driving operation.

(21) The display unit according to (1) or (2), wherein

the pixel circuit further includes a sixteenth transistor that allows, through turning on, the pixel voltage to be applied to the source of the first transistor,

the source of the first transistor is connected to the display element, and

the drive section allows the sixteenth transistor to turn on during the first and second driving operations.

(22) The display unit according to (21), wherein

the first transistor has a drain connected to the drive section,

the pixel circuit further includes a seventeenth transistor that allows, through turning on, the gate of the first transistor to be connected to the drain of the first transistor,

during the first driving operation, the drive section applies the first voltage to the gate of the first transistor and allows the seventeenth transistor to turn off, and

the drive section allows, during the second driving operation, the seventeenth transistor to turn on, thereby allowing a current to flow through the first transistor.

(23) The display unit according to (22), wherein

the pixel circuit further includes an eighteenth transistor that allows, through turning on, the drain of the first transistor to be connected to the drive section,

the drive section allows, during the first driving operation, the seventeenth and eighteenth transistors to turn on, thereby applying the first voltage to the gate of the first transistor through the seventeenth and eighteenth transistors, and

during the second driving operation, the drive section allows the seventeenth transistor to turn on, and allows the eighteenth transistor to turn off.

(24) The display unit according to any one of (1) to (23), wherein an absolute value of a difference between the pixel voltage and the first voltage is larger than an absolute value of a threshold voltage of the first transistor.

(25) The display unit according to any one of (1) to (24), further including:

a plurality of the pixel circuits, and

a plurality of signal lines transmitting the pixel voltage, wherein

two of the pixel circuits, that are adjacent to each other in a direction intersecting an extending direction of the signal lines, are connected to one of the signal lines.

(26) The display unit according to (25), wherein the drive section time-divisionally drives the two of the pixel circuits in each horizontal period.

(27) A drive circuit including a drive section,

the drive section performing a first driving operation and performing a second driving operation after the first driving operation,

the first driving operation allowing the drive section to apply a pixel voltage to a first terminal and allowing a second terminal to be at a first voltage, the pixel voltage determining luminance of a display element, the first terminal being one of a gate and a source of a first transistor, the second terminal being the other of the gate and the source of the first transistor, the first transistor having the gate and the source between which a capacitor is inserted, and the first transistor supplying a current to the display element, and

the second driving operation allowing the second terminal to be at a second voltage, through applying the pixel voltage to the first terminal and allowing a current to flow through the first transistor.

(28) A driving method including:

performing a first driving operation and performing a second driving operation after the first driving operation,

the first driving operation allowing a pixel voltage to be applied to a first terminal and allowing a second terminal to be at a first voltage, the pixel voltage determining luminance of a display element, the first terminal being one of a gate and a source of a first transistor, the second terminal being the other of the gate and the source of the first transistor, the first transistor having the gate and the source between which a capacitor is inserted, and the first transistor supplying a current to the display element, and

the second driving operation allowing the second terminal to be at a second voltage, through applying the pixel voltage to the first terminal and allowing a current to flow through the first transistor.

(29) An electronic apparatus with a display unit and a control section controlling operation of the display unit, the display unit including:

a pixel circuit including a display element, a first transistor having a gate and a source, and a capacitor inserted between the gate and the source of the first transistor, the first transistor supplying a current to the display element; and

a drive section driving the pixel circuit, through performing a first driving operation and performing a second driving operation after the first driving operation,

the first driving operation allowing the drive section to apply a pixel voltage to a first terminal and allowing a second terminal to be at a first voltage, the pixel voltage determining luminance of the display element, the first terminal being one of the gate and the source of the first transistor, and the second terminal being the other of the gate and the source of the first transistor, and

the second driving operation allowing the second terminal to be at a second voltage, through applying the pixel voltage to the first terminal and allowing a current to flow through the first transistor.

The present application contains subject matter related to that disclosed in Japanese Priority Patent Application JP 2012-170487 filed in the Japan Patent Office on Jul. 31, 2012, Japanese Priority Patent Application JP 2012-202840 filed in the Japan Patent Office on Sep. 14, 2012, and Japanese Priority Patent Application JP 2012-248286 filed in the Japan Patent Office on Nov. 12, 2012, the entire content of each of which is hereby incorporated by reference.