Manufacturing method for semiconductor devices

The reliability of a semiconductor device is enhanced. A first lead frame, a first semiconductor chip, a second lead frame, and a second semiconductor chip are stacked over an assembly jig in this order with solder in between and solder reflow processing is carried out to fabricate their assembly. Thereafter, this assembly is sandwiched between first and second molding dies to form an encapsulation resin portion. The upper surface of the second die is provided with steps. At a molding step, the second lead frame is clamped between the first and second dies at a position higher than the first lead frame; and a third lead frame is clamped between the first and second dies at a higher position. The assembly jig is provided with steps at the same positions as those of the steps in the upper surface of the second die in positions corresponding to those of the same.

CROSS-REFERENCE TO RELATED APPLICATIONS

The disclosure of Japanese Patent Application No. 2009-233125 filed on Oct. 7, 2009 including the specification, drawings and abstract is incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

The present invention relates to manufacturing methods for semiconductor devices and in particular to a technology effectively applicable to a manufacturing method for plastic molded semiconductor package-type semiconductor devices.

Various types of semiconductor packages are used and among them there is a plastic molded semiconductor package in which a semiconductor chip is sealed with an encapsulation resin portion. In plastic molded semiconductor packages, a semiconductor chip is sealed in an encapsulation resin portion; therefore, the reliability of the semiconductor chip can be enhanced. When a terminal is exposed in the back surface of the encapsulation resin portion, the plastic molded semiconductor package can be surface mounted.

Japanese Unexamined Patent Publication No. 2003-188341 (Patent Document 1) describes a technology for implementing the following: a first lead frame and a second lead frame are set in the vertical direction; a first semiconductor chip and a second semiconductor chip are placed over the respective lead frames; and these semiconductor chips are respectively sealed with first encapsulation resin and second encapsulation resin.

Japanese Unexamined Patent Publication No. Sho 61 (1986)-117858 (Patent Document 2) describes a technology related to a semiconductor device in which multiple semiconductor chips are provided in one and the same package in a stacked manner.

Patent Document 1

Patent Document 2

SUMMARY OF THE INVENTION

The investigation by the present inventors has revealed the following:

The present inventors investigated a plastic molded semiconductor package-type semiconductor device. This semiconductor device was configured as follows: a drain terminal is soldered to a drain electrode in the back surface of a semiconductor chip; a source terminal and a gate terminal were respectively soldered to a source electrode and a gate electrode in the front surface of the semiconductor chip; and these elements were sealed with a plastic molding portion. To manufacture this semiconductor device, the following procedure can be taken: first, a lead frame having a drain terminal and a lead frame having a source terminal and a gate terminal are prepared; a semiconductor chip is placed over the drain terminal in one lead frame and then the other lead frame having the source terminal and the gate terminal is placed over this semiconductor chip; and solder reflow processing is carried out to fabricate an assembly of them. Then this assembly is sandwiched between molding dies and plastic molded and the outer lead portion of each terminal protruded from the encapsulation resin portion is separated from the lead frames and bent.

When a semiconductor chip is set between two lead frames to manufacture a semiconductor device as mentioned above, the two lead frames of the assembly are clamped between dies at a molding step. At this time, it is required to clamp the two lead frames at different height positions. When the assembly is fabricated and the spacing between the two lead frames in the assembly is as designed, no problem arises at this molding step. If this spacing is not as designed due to variation in the thickness of the semiconductor chip or variation in the thickness of solder joining together each electrode of the semiconductor chip and each terminal of the lead frames, the following problems can arise. The problems arise when the two lead frames of the assembly are clamped between dies.

If the spacing between the two lead frames of the assembly is excessively smaller than a design value, the following takes place when the two lead frames of the assembly are clamped between molding dies: force is exerted on the lead frames in such directions that the lead frames are stripped from the semiconductor chip. This degrades the reliability of solder joints between the drain terminal and the source terminal and gate terminal and the semiconductor chip, which can lead to the degraded reliability of the manufactured semiconductor device.

Conversely, if the spacing between the two lead frames of the assembly is excessively larger than the design value, a gap is produced between the dies and the lead frames when the two lead frames of the assembly are clamped between molding dies. As a result, when resin material is injected into the cavity in the dies to form an encapsulation resin portion, the resin can flow into this gap and resin leakage can occur. This degrades the fabrication yield of the semiconductor device.

These problems become more noticeable with increase in the number of stacked semiconductor chips and lead frames.

It is an object of the invention to provide a technology with which the reliability of a semiconductor device can be enhanced.

It is another object of the invention to provide a technology with which the fabrication yield of a semiconductor device can be enhanced.

The above and other objects and novel features of the invention will be apparent from the description in this specification and the accompanying drawings.

The following is a brief description of the gist of the typical elements of the invention laid open in this application:

In a manufacturing method for semiconductor devices in a typical embodiment, the following procedure is taken: a first frame having a chip placement portion is set over an assembly jig; a semiconductor chip is set over the chip placement portion of the first frame with first solder in between; a second frame having a first lead terminal portion is set over the assembly jig so that the first lead terminal portion is set over the semiconductor chip with second solder in between; and solder reflow processing is carried out with the first and second frames set over the assembly jig. Thereafter, using a lower die and an upper die, an encapsulation resin portion is formed to seal the first semiconductor chip, the chip placement portion of the first frame, and the first lead terminal portion of the second frame. The lower die includes a first face for setting the chip placement portion of the first frame and a second face for supporting the second frame in a position adjacent to the cavity formed by the lower die and the upper die so that it is protruded from the first face. At an encapsulation resin portion formation step, the chip placement portion of the first frame is set over the first face of the lower die and part of the second frame is sandwiched between the second face of the lower die and the upper die. The assembly jig has a first supporting face over which the chip placement portion of the first frame is set and a second supporting face that is protruded from the first supporting face and is for supporting the second frame set over the assembly jig. The portion of the second frame clamped between the second face of the lower die and the upper die at the encapsulation resin portion formation step is set over the second supporting face of the assembly jig when the second frame is set over the assembly jig. The height of the second face of the lower die relative to the first face and the height of the second supporting face of the assembly jig relative to the first supporting face are identical with each other.

The following is a brief description of the gist of the effect obtained by the typical elements of the invention laid open in this application:

According to a typical embodiment, the characteristics of a semiconductor device can be enhanced.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following description, each embodiment will be divided into multiple sections if necessary for the sake of convenience. Unless explicitly stated otherwise, they are not unrelated to one another and they are in such a relation that one is a modification, details, supplementary explanation, or the like of part or all of the other. When mention is made of any number of elements (including a number of pieces, a numeric value, a quantity, a range, and the like) in the following description of embodiments, the number is not limited to that specific number. Unless explicitly stated otherwise or the number is obviously limited to a specific number in principle, the foregoing applies and the number may be above or below that specific number. In the following description of embodiments, needless to add, their constituent elements (including elemental steps and the like) are not always indispensable unless explicitly stated otherwise or they are obviously indispensable in principle. Similarly, when mention is made of the shape, positional relation, or the like of a constituent element or the like in the following description of embodiments, it includes those substantially approximate or analogous to that shape or the like. This applies unless explicitly stated otherwise or it is apparent in principle that some shape or the like does not include those substantially approximate or analogous to that shape or the like. This is the same with the above-mentioned numeric values and ranges.

Hereafter, detailed description will be given to embodiments of the invention with reference to the drawings. In all the drawings for explaining embodiments, members having the same function will be marked with the same reference numerals and the repetitive description thereof will be omitted. With respect to the following embodiments, description will not be repeated about an identical or similar part unless necessary.

In every drawing used in the description of embodiments, hatching may be omitted to facilitate visualization even though it is a sectional view. Further, hatching may be provided to facilitate visualization even though it is a plan view.

In this application, field effect transistors will be referred to as MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or simply as MOS. Non-oxide films are not excluded from gate insulating films.

First Embodiment

In the description of this embodiment, a case where the invention is applied to a semiconductor device used in a DC-DC converter will be taken as an example.

Description will be given to a semiconductor device in an embodiment of the invention with reference to the drawings.

FIG. 1is a circuit diagram illustrating an example of a DC-DC converter, non-isolated DC-DC converter (DC-DC converter)1in this example, having a semiconductor device (semiconductor package) SM1in an embodiment of the invention; andFIG. 2is a basic operating waveform chart of the non-isolated DC-DC converter1inFIG. 1.

This non-isolated DC-DC converter1is used in the power supply circuit of an electronic device, such as a desk top personal computer, a notebook personal computer, a server, game machine, or the like. It includes the semiconductor device SM1, two driver circuits (drive circuits) DR1, DR2, a control circuit CTC, an input capacitor Cin, an output capacitor Cout, and a coil L. Reference code VIN denotes input power supply; GND denotes reference potential (for example, ground potential of 0 V); Iout denotes output current; and Vout denotes output voltage.

The semiconductor device SM1includes two power MOSFETs (Metal Oxide Semiconductor Field Effect Transistor: hereafter, simply abbreviated as power MOSs) QH1, QL1. These power MOSFETs QH1, QL1are sealed (enclosed) in one semiconductor device SM1.

The driver circuits (drive circuits) DR1, DR2respectively control the potential of the gate terminals of the power MOSs QH1, QL1according to a pulse width modulation (PWM) signal supplied from the control circuit CTC. The driver circuits thereby control the operation of the power MOSs QH1, QL1. The output of one driver circuit DR1is electrically coupled to the gate terminal of the power MOS QH1. The output of the other driver circuit DR2is electrically coupled to the gate terminal of the power MOS QL1. Reference code VDIN denotes the input power supply of each of the driver circuits DR1, DR2.

The power MOSs QH1, QL1are coupled in series between the following terminals of the input power supply VIN: the terminal (first power supply terminal) ET1for supplying high potential (first power supply potential) and the terminal (second power supply terminal) ET2for supplying reference potential (second power supply potential) GND. That is, the power MOS QH1has its source-drain path coupled in series between the terminal ET1for high potential supply of the input power supply VIN and an output node (output terminal) N; and the power MOS QL1has its source-drain path coupled in series between the output node N and the terminal ET2for reference potential GND supply. Reference code Dp1denotes the parasitic diode (internal diode) of the power MOS QH1and Dp2denotes the parasitic diode (internal diode) of the power MOS QL1. Reference code D denotes the drain of each of the power MOSs QH1, QL1and S denotes the source of each of the power MOSs QH1, QL1.

The power MOS (field effect transistor, power transistor) QH1is a field effect transistor for high-side switch (high potential side: first operating voltage; hereafter, simply referred to as high side) and has a switch function for storing energy in the above coil L. The coil L is an element that supplies power to the output of the non-isolated DC-DC converter1(the input of a load LD).

This power MOS QH1for high side is formed in a semiconductor chip (semiconductor chip for high side) CPH. This power MOS QH1is formed of, for example, an n-channel field effect transistor. In this example, a channel of this field effect transistor is formed in the direction of the thickness of the semiconductor chip CPH. In this case, it is possible to increase the channel width per unit area and reduce on-resistance as compared with the following field effect transistors: field effect transistors whose channel is formed along the main surface of the semiconductor chip CPH (surface orthogonal to the direction of the thickness of the semiconductor chip CPH). Therefore, it is possible to reduce the size of each element and miniaturize the semiconductor device SM1.

Meanwhile, the power MOS (field effect transistor, power transistor) QL1is a field effect transistor for low-side switch (low potential side: second operating voltage; hereafter, simply referred to as low side). It has a function of reducing the resistance of the transistor in synchronization with a frequency from the control circuit CTC to carry out rectification. That is, the power MOS QL1is a transistor for rectification of the non-isolated DC-DC converter1.

This power MOS QL1for low side is formed in a semiconductor chip (semiconductor chip for low side) CPL different from the semiconductor chip CPH. The power MOS QL1is formed of, for example, an n-channel power MOS and its channel is formed in the direction of the thickness of the semiconductor chip CPL similarly with the power MOS QH1. The reason why the power MOS whose channel is formed in the direction of the thickness of the semiconductor chip CPL is used is as follows: as indicated by the basic operating waveform of the non-isolated DC-DC converter1inFIG. 2, the on-time (time for which voltage is applied) of the power MOS QL1for low side is longer than the on-time of the power MOS QH1for high side; it seems that loss due to on-resistance is larger than switching loss. For this reason, the channel width per unit area can be made larger in cases where a field effect transistor whose channel is formed in the direction of the thickness of the semiconductor chip CPL is used than in the following cases: cases where a field effect transistor whose channel is formed along the main surface of the semiconductor chip CPL is used. That is, the on-resistance can be reduced by forming the power MOS QL1for low side of a field effect transistor whose channel is formed in the direction of the thickness of the semiconductor chip CPL; therefore, the voltage conversion efficiency can be enhanced even though the current passed through the non-isolated DC-DC converter1is increased. InFIG. 2, reference code Ton denotes the pulse width of the power MOS QH1for high side when it is on; and T denotes its pulse period.

The control circuit CTC is a circuit that controls the operation of the power MOSs QH1, QL1and is comprised of, for example, a PWM (Pulse Width Modulation) circuit. This PWM circuit compares a command signal with the amplitude of a triangular wave and outputs a PWM signal (control signal). The output voltage of the power MOSs QH1, QL1(that is, the width of the voltage switch on (on-time) of the power MOSs QH1, QL1) is controlled by this PWM signal. (That is, the output voltage of the non-isolated DC-DC converter1is controlled by the PWM signal.)

The output of this control circuit CTC is electrically coupled to the input of each of the driver circuits DR1, DR2. The respective outputs of the driver circuits DR1, DR2are respectively electrically coupled to the gate terminal of the power MOS QH1and the gate terminal of the power MOS QL1.

The above input capacitor Cin is a power supply that temporarily stores energy (electric charge) supplied from the input power supply VIN and supplies the stored energy to the main circuit of the non-isolated DC-DC converter1. It is electrically coupled in parallel with the input power supply VIN. The above output capacitor Cout is electrically coupled between output wiring coupling the coil L and the LD and the terminal for supplying reference potential GND.

The wiring of the non-isolated DC-DC converter1coupling the source of the power MOS QH1and the drain of the power MOS QL1is provided with the above output node N that outputs power supply potential for output to the outside. This output node N is electrically coupled with the coil L through the output wiring and is further electrically coupled with the load LD through the output wiring. Examples of this load LD include hard disk drive HDD, ASIC (Application Specific Integrated Circuit), FPGA (Field Programmable Gate Array), expansion card (PCI CARD), memory (DDR memory, DRAM (Dynamic RAM), flash memory, and the like), CPU (Central Processing Unit), and the like.

In this non-isolated DC-DC converter1, power supply voltage is converted by alternately turning on and off the power MOSs QH1, QL1in synchronization with each other. More specific description will be given. When the power MOS QH1for high side is on, a current (first current) I1flows from the terminal ET1to the output node N through the power MOS QH1. Meanwhile, when the power MOS QH1for high side is off, a current I2is passed by the back electromotive voltage of the coil L. Voltage drop can be reduced by turning on the power MOS QL1for low side while this current I2is flowing.

FIG. 3andFIG. 4are perspective views of the semiconductor device SM1in this embodiment;FIG. 5is a top view (plan view) of the semiconductor device SM1;FIG. 6is a bottom view (bottom plan view, back side back view, plan view) of the semiconductor device SM1;FIG. 7toFIG. 12are sectional views (lateral sectional views) of the semiconductor device SM1; andFIG. 13toFIG. 16are planar transparent views of the semiconductor device SM1. Among these drawings,FIG. 3corresponds to a perspective view obtained when the semiconductor device SM1is obliquely viewed from above; andFIG. 4corresponds to a perspective view obtained when the semiconductor device SM1is obliquely viewed from underneath.FIG. 7substantially corresponds to the section taken along line A1-A1ofFIG. 13;FIG. 8substantially corresponds to the section taken along line A2-A2ofFIG. 13;FIG. 9substantially corresponds to the section taken along line B1-B1ofFIG. 13;FIG. 10substantially corresponds to the section taken along line B2-B2ofFIG. 13;FIG. 11substantially corresponds to the section taken along line B3-B3ofFIG. 13; andFIG. 12substantially corresponds to the section taken along line B4-B4ofFIG. 13.FIG. 13illustrates the semiconductor device SM1with an encapsulation resin portion MR seen through;FIG. 14illustrates the semiconductor device SM1inFIG. 13with a gate terminal TGL and a source terminal TSL further removed (seen through);FIG. 15illustrates the semiconductor device SM1inFIG. 14with the semiconductor chip CPL further removed (seen through);FIG. 16illustrates the semiconductor device SM1inFIG. 15with a gate terminal TGH and a source-drain terminal TSD further removed (seen through). InFIG. 13toFIG. 16, the outline of the encapsulation resin portion MR is indicated by alternate long and two short dashes line to facilitate understanding. Code X shown in each plan view indicates a first direction and code Y indicates a second direction orthogonal to (intersecting with) the first direction X. In the following description, the first direction X will be designated as X-direction and the second direction Y will be designated as Y-direction sometimes.

The semiconductor device (semiconductor package) SM1in this embodiment is a plastic molded semiconductor package. That is, the semiconductor device SM1is a plastic molded semiconductor package-type semiconductor device.

In this embodiment, as mentioned above, the following chips are put together (packaged) in one semiconductor package to obtain one semiconductor device SM1: the semiconductor chip CPH in which the power MOS QH1as a field effect transistor for high-side switch is formed; and the semiconductor chip CPL in which the power MOS QL1as a field effect transistor for low-side switch is formed. This makes it possible to achieve miniaturization (area reduction) of the non-isolated DC-DC converter1and, in addition, reduce wiring parasitic inductance; therefore, it is also possible to achieve frequency enhancement and efficiency enhancement.

Concrete description will be given to the structure of the semiconductor device SM1with reference toFIG. 3toFIG. 16.

The semiconductor device SM1in this embodiment illustrated inFIG. 3toFIG. 16includes: the semiconductor chips CPH, CPL; the drain terminal TDH, gate terminals TGL, TGH, source terminal TSL, and source-drain terminal TSD which are lead terminal portions formed of conductor; and the encapsulation resin portion (sealing portion, encapsulation resin) MR sealing them.

The encapsulation resin portion MR is composed of a resin material, such as thermosetting resin material, and the like and may contain filler or the like. For example, epoxy resin containing filler and the like can be used to form the encapsulation resin portion MR. The semiconductor chips CPH, CPL, gate terminals TGL, TGH, source terminal TSL, drain terminal TDH, and source-drain terminal TSD are sealed and protected by the encapsulation resin portion MR.

The encapsulation resin portion MR has two main surfaces MRa, MRb positioned opposite to each other. The main surface MRa of the encapsulation resin portion MR is the upper surface (front surface) of the encapsulation resin portion MR (Refer toFIG. 5); and the main surface MRb of the encapsulation resin portion MR is the back surface (bottom surface, lower surface) of the encapsulation resin portion MR. The main surface MRb of the encapsulation resin portion MR, that is, the back surface (bottom surface, lower surface) of the semiconductor device SM1(Refer toFIG. 6) is the mounting surface of the semiconductor device SM1.

The planar shape of the encapsulation resin portion MR is rectangular (oblong). As illustrated inFIG. 5andFIG. 6, it has the following sides as viewed in a plane (that is, as viewed in a plane parallel to the main surface MRb of the encapsulation resin portion MR): sides SD1, SD3that are parallel to the first direction X and opposed to each other; and sides SD2, SD4that are parallel to the second direction Y orthogonal to the first direction X and opposed to each other.

The semiconductor chips CPL, CPH are obtained by, for example: forming various semiconductor elements or semiconductor integrated circuits in a semiconductor substrate (semiconductor wafer) composed of single crystal silicon or the like; grinding the back surface of the semiconductor substrate as required; and then separating the semiconductor substrate into individual semiconductor chips CPL, CPH by dicing or the like. The semiconductor chip CPL and the semiconductor chip CPH are in rectangular planar shape. The semiconductor chips CPL, CPH are sealed in the encapsulation resin portion MR and neither of them is exposed from the encapsulation resin portion MR.

The semiconductor chip (first semiconductor chip) CPH has two main surfaces positioned opposite to each other: a front surface (main surface on the semiconductor element formation side) and a back surface (main surface on the opposite side to the front surface). The semiconductor chip CPH includes: a source pad electrode (front surface electrode) PDSH and a gate pad electrode (front surface electrode) PDGH formed in the front surface of the semiconductor chip CPH; and a back surface drain electrode (back surface electrode) BEH formed in the entire back surface of the semiconductor chip CPH. (Refer toFIG. 7and the like.) The main surface of the semiconductor chip CPH on the side where the source pad electrode PDSH and the gate pad electrode PDGH are formed will be designated as the front surface of the semiconductor chip CPH; and the main surface of the semiconductor chip CPH on the back surface drain electrode BEH side will be designated as the back surface of the semiconductor chip CPH. The back surface (back surface drain electrode BEH) of the semiconductor chip CPH is opposed to the drain terminal TDH and the front surface of the semiconductor chip CPH is opposed to the gate terminal TGH and the source-drain terminal TSD.

The back surface drain electrode BEH in the back surface of the semiconductor chip CPH is electrically coupled to the drain D of the power MOS QH1for high side formed in the semiconductor chip CPH. That is, the back surface drain electrode BEH of the semiconductor chip CPH corresponds to the drain electrode of the power MOS QH1for high side.

The gate pad electrode (electrode for gate) PDGH in the front surface of the semiconductor chip CPH is electrically coupled to the gate electrode of the power MOS QH1for high side formed in the semiconductor chip CPH. That is, the gate pad electrode PDGH of the semiconductor chip CPH corresponds to a pad (bonding pad, pad electrode) for the gate electrode of the power MOS QH1for high side.

The source pad electrode (electrode for source) PDSH in the front surface of the semiconductor chip CPH is electrically coupled to the source S of the power MOS QH1for high side formed in the semiconductor chip CPH. That is, the source pad electrode PDSH of the semiconductor chip CPH corresponds to a pad (bonding pad, pad electrode) for the source electrode of the power MOS QH1for high side.

The configuration of the semiconductor chip (second semiconductor chip) CPL is substantially the same as the configuration of the semiconductor chip CPH. More specific description will be given. The semiconductor chip CPL has two main surfaces positioned opposite to each other: a front surface (main surface on the semiconductor element formation side) and a back surface (main surface on the opposite side to the front surface). The semiconductor chip CPL includes: a source pad electrode (front surface electrode) PDSL and a gate pad electrode (front surface electrode) PDGL formed in the front surface of the semiconductor chip CPL; and a back surface drain electrode (back surface electrode) BEL formed in the entire back surface of the semiconductor chip CPL. (Refer toFIG. 7and the like.) The main surface of the semiconductor chip CPL on the side where the source pad electrode PDSL and the gate pad electrode PDGL are formed will be designated as the front surface of the semiconductor chip CPL; and the main surface of the semiconductor chip CPL on the back surface drain electrode BEL side will be designated as the back surface of the semiconductor chip CPL. The back surface (back surface drain electrode BEL) of the semiconductor chip CPL is opposed to the source-drain terminal TSD and the front surface of the semiconductor chip CPL is opposed to the source terminal TSL and the gate terminal TGL.

The back surface drain electrode BEL in the back surface of the semiconductor chip CPL is electrically coupled to the drain D of the power MOS QL1for low side formed in the semiconductor chip CPL. That is, the back surface drain electrode BEL of the semiconductor chip CPL corresponds to the drain electrode of the power MOS QL1for low side.

The gate pad electrode (electrode for gate) PDGL in the front surface of the semiconductor chip CPL is electrically coupled to the gate electrode of the power MOS QL1for low side formed in the semiconductor chip CPL. That is, the gate pad electrode PDGL of the semiconductor chip CPL corresponds to a pad (bonding pad, pad electrode) for the gate electrode of the power MOS QL1for low side.

The source pad electrode (electrode for source) PDSL in the front surface of the semiconductor chip CPL is electrically coupled to the source S of the power MOS QL1for low side formed in the semiconductor chip CPL. That is, the source pad electrode PDSL of the semiconductor chip CPL corresponds to a pad (bonding pad, pad electrode) for the source electrode of the power MOS QL1for low side.

The following terminals are composed of conductor, preferably, metal material such as copper (Cu) or copper alloy: the drain terminal (terminal for drain, conductor portion for drain joining, chip placement portion) TDH; gate terminals (terminals for gate, conductor portion for gate joining, lead terminal portions) TGL, TGH; the source terminal (terminal for source, conductor portion for source joining, lead terminal portion) TSL; and the source-drain terminal (terminal for source and drain, conductor portion for source and drain joining, lead terminal portion) TSD.

As seen fromFIG. 7toFIG. 12as well, the semiconductor chip CPH is arranged between the drain terminal TDH positioned under the semiconductor chip CPH and the gate terminal TGH and source-drain terminal TSD positioned above the semiconductor chip CPH. The semiconductor chip CPH is placed so that the front surface side of the semiconductor chip CPH faces upward (toward the gate terminal TGH and the source-drain terminal TSD). The semiconductor chip CPL is positioned between the source-drain terminal TSD positioned under the semiconductor chip CPL and the gate terminal TGL and source terminal TSL positioned above the semiconductor chip CPL. The semiconductor chip CPL is placed so that the front surface of the semiconductor chip CPL faces upward (toward the gate terminal TGL and the source terminal TSL). That is, the semiconductor chip CPH is placed over the drain terminal TDH; the gate terminal TGH and the source-drain terminal TSD are placed over the semiconductor chip CPH; the semiconductor chip CPL is placed over the source-drain terminal TSD; and the gate terminal TGL and the source terminal TSL are placed over the semiconductor chip CPL.

(The upper surface of) the drain terminal TDH is joined (bonded, coupled) and electrically coupled with the back surface drain electrode BEH of the semiconductor chip CPH through solder SLD. (The lower surface of) the gate terminal TGH is joined (bonded, coupled) and electrically coupled with the gate pad electrode PDGH in the front surface of the semiconductor chip CPH through solder SLD; and (the lower surface of) the source-drain terminal TSD is joined (bonded, coupled) and electrically coupled with the source pad electrode PDSH in the front surface of the semiconductor chip CPH through solder SLD. (The upper surface of) the source-drain terminal TSD is joined (bonded, coupled) and electrically coupled with the back surface drain electrode BEL of the semiconductor chip CPL through solder SLD. (The lower surface of) the gate terminal TGL is joined (bonded, coupled) and electrically coupled with the gate pad electrode PDGL in the front surface of the semiconductor chip CPL through solder SLD; and (the lower surface of) the source terminal TSL is joined (bonded, coupled) and electrically coupled with the source pad electrode PDSL in the front surface of the semiconductor chip CPL through solder SLD. For this reason, the source-drain terminal TSD is electrically coupled to the source pad electrode PDSH of the semiconductor chip CPH through solder SLD and is also electrically coupled to the back surface drain electrode BEL of the semiconductor chip CPL through solder SLD.

The semiconductor chip CPH is placed over (die-bonded to) the drain terminal TDH through solder SLD; therefore, the drain terminal TDH can be considered as a chip placement portion (die pad portion). The gate terminals TGL, TGH, source terminal TSL, and source-drain terminal TSD function to draw each electrode of the semiconductor chips CPH, CPL in the encapsulation resin portion MR to outside the encapsulation resin portion MR; therefore, they can be considered as lead terminal portions (lead terminals, lead portions). The semiconductor chip CPL is placed over (die-bonded to) the source-drain terminal TSD through solder SLD; therefore, the source-drain terminal TSD can be considered as what functions both as a chip placement portion and as a lead terminal portion (lead terminal, lead portion).

The drain terminal TDH is not bent (not subjected to bending work) and is flat. The lower surface (main surface) TDHa of the drain terminal TDH is exposed from the main surface MRb of the encapsulation resin portion MR. The drain terminal TDH has two main surfaces positioned opposite to each other. Its main surface on the side where the semiconductor chip CPH is placed (that is, the side opposite to the back surface of the semiconductor chip CPH) will be designated as the upper surface of the drain terminal TDH; and its main surface on the opposite side to this upper surface will be designated as lower surface TDHa.

Parts of the drain terminal TDH (that is, its end portions on the side it is cut off from a lead frame LF1at the Step S11described later) are slightly protruded from the lateral surfaces of the encapsulation resin portion MR corresponding to the sides SD2, SD4. The other lateral surfaces of the drain terminal TDH are covered with and sealed in the encapsulation resin portion MR. Part of the upper surface of the drain terminal TDH is joined to the back surface drain electrode BEH of the semiconductor chip. CPH through solder SLD. The other part of the upper surface of the drain terminal TDH is covered with and sealed in the encapsulation resin portion MR. As illustrated inFIG. 6toFIG. 8andFIG. 12, the drain terminal TDH is provided in its areas other than the area directly under the semiconductor chip CPH with openings (hole portions, through holes) OP1. The openings are extended from the upper surface of the drain terminal TDH to its lower surface TDHa. The drain terminal TDH is made less prone to come off from the encapsulation resin portion MR by filling these openings OP1with the encapsulation resin portion MR.

Part (outer lead portion) of each of the gate terminal TGH, source-drain terminal TSD, gate terminal TGL and source terminal TSL as lead terminals is protruded outward from lateral surfaces of the encapsulation resin portion MR and is bent outside the encapsulation resin portion MR. That is, each of the gate terminal TGH, source-drain terminal TSD, gate terminal TGL, and source terminal TSL is so formed that the following is implemented: its portion positioned in the encapsulation resin portion MR is flat; but it is bent at its portion protruded from a lateral surface of the encapsulation resin portion MR (its portion positioned outside the encapsulation resin portion MR, that is, an outer lead portion). (Refer toFIG. 9,FIG. 12, and the like.)

In each of the gate terminal TGH, source-drain terminal TSD, gate terminal TGL, and source terminal TSL, a portion positioned outside the encapsulation resin portion MR will be designated as outer lead portion; and a portion positioned within the encapsulation resin portion MR will be designated as inner lead portion. In each of the gate terminal TGH, source-drain terminal TSD, gate terminal TGL, and source terminal TSL, the inner lead portion and the outer lead portion are integrally formed. It is the inner lead portion of the source-drain terminal TSD that is joined both to the source pad electrode PDSH of the semiconductor chip CPH and the back surface drain electrode BEL of the semiconductor chip CPL with solder SLD; and it is the inner lead portion of the gate terminal TGH that is joined to the gate pad electrode PDGH of the semiconductor chip CPH with solder SLD. It is the inner lead portion of the source terminal TSL that is joined to the source pad electrode PDSL of the semiconductor chip CPL with solder SLD; and it is the inner lead portion of the gate terminal TGL that is joined to the gate pad electrode PDGL of the semiconductor chip CPL with solder SLD.

The lower surfaces of the following outer lead portions formed by bending are formed substantially flush with the lower surface TDHa of the drain terminal TDH exposed in the main surface MRb of the encapsulation resin portion MR: the lower surface TGHb of the outer lead portion of the gate terminal TGH and the lower surface TSDb of the outer lead portion of the source-drain terminal TSD (Refer toFIG. 12); and the lower surface TGLb of the outer lead portion of the gate terminal TGL and the lower surface TSLb of the outer lead portion of the source terminal TSL (Refer toFIG. 9). These lower surfaces, listed below, located in the same plane become the terminals for external coupling (external terminals) of the semiconductor device SM1: the lower surface TGHb of the outer lead portion of the gate terminal TGH; the lower surface TSDb of the outer lead portion of the source-drain terminal TSD; the lower surface TGLb of the outer lead portion of the gate terminal TGL; the lower surface TSLb of the outer lead portion of the source terminal TSL; and the lower surface TDHa of the drain terminal TDH. For this reason, the semiconductor device SM1can be surface mounted and the back surface of the semiconductor device SM1(the main surface MRb of the encapsulation resin portion MR) is the mounting surface of the semiconductor device SM1.

In the semiconductor device SM1, the source-drain terminal TSD is joined and electrically coupled to both of the following through solder SLD: the source pad electrode PDSH of the semiconductor chip CPH positioned underneath and the back surface drain electrode BEL of the semiconductor chip CPL positioned above. For this reason, the source pad electrode PDSH of the semiconductor chip CPH positioned underneath and the back surface drain electrode BEL of the semiconductor chip CPL positioned above are electrically coupled together through the solder SLD and the source-drain terminal TSD. Therefore, the source-drain terminal TSD functions both as the source terminal of the semiconductor chip CPH positioned underneath and as the drain terminal of the semiconductor chip CPL positioned above. As a result, the source of the power MOS QH1and the drain of the power MOS QL1are electrically coupled together. This makes it possible to couple the power MOS QH1formed in the semiconductor chip CPH positioned underneath and the power MOS QL1formed in the semiconductor chip CPL positioned above in series.

When the terminals and semiconductor chips in the encapsulation resin portion MR of the semiconductor device SM1are considered to be of laminar structure, they are placed as follows: the drain terminal TDH is placed in the first layer as the lowermost layer; the semiconductor chip CPH is placed in the second layer positioned thereabove; the gate terminal TGH and the source-drain terminal TSD are placed in the third layer positioned thereabove; the semiconductor chip CPL is placed in the fourth layer positioned thereabove; and the gate terminal TGL and the source terminal TSL are placed in the fifth layer positioned thereabove. The gate terminal TGL and source terminal TSL placed in the fifth layer are arranged in the same layer (the same height position). (Refer toFIG. 9.) However, they are separated so that they do not planarly overlap with each other and electrically isolated from each other by the encapsulation resin portion MR positioned in between. The gate terminal TGH and source-drain terminal TSD placed in the third layer are arranged in the same layer (the same height position). However, they are separated so that they do not planarly overlap with each other and electrically isolated from each other by the encapsulation resin portion MR positioned in between. (Refer toFIG. 12.)

“As viewed in a plane” cited in this specification means that something is viewed in a plane parallel to the lower surface of the drain terminal TDH. (This plane is also a plane parallel to the main surface MRb of the encapsulation resin portion MR and also corresponds to a plane substantially parallel to the front surfaces and back surfaces of the semiconductor chips CPH, CPL.)

The semiconductor chip CPH is placed (set) over the drain terminal TDH with solder SLD in between and the semiconductor chip CPH is planarly embraced in the drain terminal TDH. The gate terminal TGH and the source-drain terminal TSD are placed (set) over the semiconductor chip CPH with solder SLD in between. Part of the gate terminal TGH and part of the source-drain terminal TSD planarly overlap with the semiconductor chip CPH. More specific description will be given. Part of the gate terminal TGH planarly overlaps with the gate pad electrode PDGH of the semiconductor chip CPH. In this overlap area, the gate terminal TGH and the gate pad electrode PDGH of the semiconductor chip CPH are joined together with solder SLD. Part of the source-drain terminal TSD partly overlaps with the source pad electrode PDSH of the semiconductor chip CPH. In this overlap area, the source-drain terminal TSD and the source pad electrode PDSH of the semiconductor chip CPH are joined together with solder SLD.

The semiconductor chip CPL is placed (set) over the source-drain terminal TSD with solder SLD in between and the semiconductor chip CPL is planarly embraced in the source-drain terminal TSD. The gate terminal TGH does not planarly overlap with the semiconductor chip CPL. (Refer toFIG. 7and the like.) Since the gate terminal TGH does not planarly overlap with the semiconductor chip CPL, the gate terminal TGH is not in contact with the semiconductor chip CPL (especially, the back surface drain electrode BEL). The back surface drain electrode BEL of the semiconductor chip CPL is electrically coupled to the source-drain terminal TSD through solder SLD but it is not electrically coupled with the gate terminal TGH.

The gate terminal TGL and the source terminal TSL are placed (set) over the semiconductor chip CPL with solder SLD in between. Part of the gate terminal TGL and part of the source terminal TSL planarly overlap with the semiconductor chip CPL. (Refer toFIG. 9and the like.) More specific description will be given. Part of the gate terminal TGL is planarly overlaps with the gate pad electrode PDGL of the semiconductor chip CPL. In this overlap area, the gate terminal TGL and the gate pad electrode PDGL of the semiconductor chip CPL are joined together with solder SLD. Part of the source terminal TSL planarly overlaps with the source pad electrode PDSL of the semiconductor chip CPL. In this overlap area, the source terminal TSL and the source pad electrode PDSL of the semiconductor chip CPL are joined together with solder SLD.

The gate terminal TGL is drawn from the lateral surface of the encapsulation resin portion MR corresponding to the side SD1to outside the encapsulation resin portion MR and is bent. The gate terminal TGH is drawn from the lateral surface of the encapsulation resin portion MR corresponding to the side SD3to outside the encapsulation resin portion MR and is bent. The source terminal TSL is drawn from the lateral surface of the encapsulation resin portion MR corresponding to the side SD1and the lateral surface thereof corresponding to the side SD3to outside the encapsulation resin portion MR and is bent. The source-drain terminal TSD is drawn from the lateral surface of the encapsulation resin portion MR corresponding to the side SD1and the lateral surface thereof corresponding to the side SD3to outside the encapsulation resin portion MR and is bent. At the lateral surface of the encapsulation resin portion MR corresponding to the side SD1, the terminal TSL is drawn to outside the encapsulation resin portion MR at two points and is bent. Thus the outer lead portion of the gate terminal TGL is sandwiched between the two drawn parts of the source terminal TSL. At the lateral surface of the encapsulation resin portion MR corresponding to the side SD3, the source-drain terminal TSD is drawn to outside the encapsulation resin portion MR at two points and is bent. Thus the outer lead portion of the gate terminal TGH is sandwiched between the two drawn parts of the source-drain terminal TSD.

The gate terminal TGL and the source terminal TSL are drawn from lateral surfaces of the encapsulation resin portion MR to outside the encapsulation resin portion MR at the same height position. The gate terminal TGH and the source-drain terminal TSD are drawn from lateral surfaces of the encapsulation resin portion MR to outside the encapsulation resin portion MR at the same height position. However, the gate terminal TGL and the source terminal TSL are drawn from a lateral surface of the encapsulation resin portion MR to outside the encapsulation resin portion MR at a height position different from that of the gate terminal TGH and the source-drain terminal TSD. More specific description will be given. The gate terminal TGH and the source-drain terminal TSD are drawn from lateral surfaces of the encapsulation resin portion MR to outside the encapsulation resin portion MR at the following position: at a position lower than the height position at which the gate terminal TGL and the source terminal TSL are drawn to outside the encapsulation resin portion MR. The drain terminal TDH is located at a position lower than the height position at which the gate terminal TGH and the source-drain terminal TSD are drawn to outside the encapsulation resin portion MR.

In the encapsulation resin portion MR, the gate terminal TGL and source terminal TSL in the same layer (at the same height position) do not planarly overlap with each other; and the gate terminal TGH and source-drain terminal TSD in the same layer (at the same height position) do not planarly overlap with each other. This is intended to implement the following in the encapsulation resin portion MR: the gate terminal TGL and source terminal TSL in the same layer are electrically separated from each other and the gate terminal TGH and source-drain terminal TSD in the same layer are electrically separated from each other.

In the encapsulation resin portion MR, part of the source terminal TSL and the gate terminal TGL planarly overlaps with the source-drain terminal TSD positioned thereunder. The reason for this is as follows: to join the entire back surface drain electrode BEL of the semiconductor chip CPL to the source-drain terminal TSD with solder SLD, the semiconductor chip CPL is so arranged that it is planarly embraced in the source-drain terminal TSD; the source terminal TSL is so arranged that it planarly overlaps with the source pad electrode PDSL of the semiconductor chip CPL; and the gate terminal TGL is so arranged that it planarly overlaps with gate pad electrode PDGL of the semiconductor chip CPL. In the encapsulation resin portion MR, for this reason, the source terminal TSL and the gate terminal TGL are opposed to (that is, planarly overlap with) the source-drain terminal TSD with the semiconductor chip CPL in between.

Outside the encapsulation resin portion MR, meanwhile, the source terminal TSL, gate terminal TGL, source-drain terminal TSD, and gate terminal TGH do not planarly overlap with one another. (Refer toFIG. 6and the like.) Short-circuiting between terminals can be easily prevented outside the encapsulation resin portion MR by ensuring that the source terminal TSL, gate terminal TGL, source-drain terminal TSD, and gate terminal TGH do not planarly overlap with one another outside the encapsulation resin portion MR. In addition, the encapsulation resin portion MR can be easily formed at the molding step described later, or Step S8.

In the semiconductor device SM1in this embodiment, the semiconductor chip CPL and the semiconductor chip CPH are vertically stacked. Therefore, the plane area of the semiconductor device SM1in this embodiment can be reduced as compared with cases where the semiconductor chip CPH and the semiconductor chip CPL are laterally arranged and packaged unlike this embodiment. For this reason, it is possible to reduce the mounting area (area required for mounting the semiconductor device SM1) in a mounting board for mounting the semiconductor device SM1. Thus an electronic device (the non-isolated DC-DC converter1) using the semiconductor device SM1can be reduced in size (area). In the semiconductor device SM1in this embodiment, as mentioned above, the semiconductor chip CPL and the semiconductor chip CPH are vertically stacked. Further, the back surface drain electrode BEL of the semiconductor chip CPL and the source pad electrode PDSH of the semiconductor chip CPH are electrically coupled together though the source-drain terminal TSD located between the semiconductor chip CPL and the semiconductor chip CPH. This makes it possible to reduce the wiring parasitic inductance in the semiconductor device SM1. Therefore, it is possible to enhance the performance of the semiconductor device SM1and an electronic device (the non-isolated DC-DC converter1) using it and to achieve frequency enhancement and efficiency enhancement. Consequently, the characteristics of the semiconductor device SM1can be enhanced.

In the semiconductor device SM1in this embodiment, as mentioned above, two semiconductor chips CPH, CPL are vertically laminated. However, the semiconductor chip CPL and the semiconductor chip CPH are so set that the semiconductor chip CPL does not overlap with the area located directly above the gate pad electrode PDGH of the semiconductor chip CPH. (That is, the semiconductor chips are so set that the semiconductor chip CPL does not planarly overlap with the gate pad electrode PDGH of the semiconductor chip CPH.) In other words, the semiconductor chip CPL is prevented from being positioned directly above the gate pad electrode PDGH of the semiconductor chip CPH. (Refer toFIG. 7and the like.) As a result, the gate terminal TGH can be set so that it planarly overlaps with the gate pad electrode PDGH of the semiconductor chip CPH but it does not planarly overlap with the semiconductor chip CPL. Therefore, it is possible to set the gate terminal TGH over the gate pad electrode PDGH of the semiconductor chip CPH so that it is not in contact with the semiconductor chip CPL (especially, the back surface drain electrode BEL). For this reason, it is possible to electrically couple the gate terminal TGH to the gate pad electrode PDGH of the semiconductor chip CPH but not to electrically couple it with the back surface drain electrode BEL of the semiconductor chip CPL.

As mentioned above, the semiconductor chip CPL is so arranged that it does not overlap with the area positioned directly above the gate pad electrode PDGH of the semiconductor chip CPH. (That is, the semiconductor chip CPL is so arranged that it does not exist directly above the gate pad electrode PDGH of the semiconductor chip CPH.) For this purpose, the semiconductor chip CPH and the semiconductor chip CPL are so arranged that their respective centers are displaced from each other. (Refer toFIG. 7,FIG. 8, and the like.)

As mentioned above, the semiconductor chip CPL is so arranged that it does not overlap with the area positioned directly above the gate pad electrode PDGH of the semiconductor chip CPH. However, it is desirable that the semiconductor chip CPL and the semiconductor chip CPH should partly planarly overlap with each other. As a result, the gate terminal TGH can be electrically coupled to the gate pad electrode PDGH of the semiconductor chip CPH without electrically coupling it to the back surface drain electrode BEL of the semiconductor chip CPL. At the same time, the plane area of the semiconductor device SM1can be reduced by an amount equivalent to the overlap between the semiconductor chip CPH and the semiconductor chip CPL. Further, it is possible to electrically couple together the back surface drain electrode BEL of the semiconductor chip CPL and the source pad electrode PDSH of the semiconductor chip CPH using the shortest path through the source-drain terminal TSD sandwiched therebetween. For this reason, the wiring parasitic inductance in the semiconductor device SM1can be further reduced. This is advantageous to the enhancement of the performance, for example, frequency enhancement and efficiency enhancement, of the semiconductor device SM1and an electronic device (non-isolated DC-DC converter1) using it.

It is desirable that the semiconductor chip CPL with the power MOS QL1for low side formed therein and the semiconductor chip CPH with the power MOS QH1for high side formed therein should be made identical in size (dimensions). When the semiconductor chip CPL and the semiconductor chip CPH are made identical in size, a configuration in which a larger semiconductor chip is set over a smaller semiconductor chip is avoided. As a result, the package structure of the semiconductor device SM1is balanced and an assembly step (manufacturing process) for the semiconductor device SM1becomes easy to carry out.

It is more desirable to make the following identical with each other in addition to making the semiconductor chip CPL and the semiconductor chip CPH identical in size (dimensions): the shapes and arrangement of the source pad electrode PDSH and the gate pad electrode PDGH in the semiconductor chip CPH; and the shapes and arrangement of the source pad electrode PDSL and the gate pad electrode PDGL in the semiconductor chip CPL. That is, it is more desirable to use semiconductor chips with the same configuration for the semiconductor chip CPL and the semiconductor chip CPH. This makes it possible to use common semiconductor chips both for the semiconductor chip CPL and for the semiconductor chip CPH and reduce the cost of the semiconductor device SM1. Because of circuitry, a larger current flows in the power MOS QL1for low side than in the power MOS QH1for high side. Therefore, it is desirable to take the following measure: a semiconductor chip in optimal size is prepared for the semiconductor chip CPL in which the power MOS QL1for low side is formed and this semiconductor chip is used not only for the semiconductor chip CPL but also for the semiconductor chip CPH.

When the semiconductor chip CPL and the semiconductor chip CPH are identical in size, the following measure can be taken to prevent the semiconductor chip CPL from overlapping with the area positioned directly above the gate pad electrode PDGH of the semiconductor chip CPH: the semiconductor chip CPH and the semiconductor chip CPL are so arranged that their respective centers are displaced from each other as viewed in a plane. This makes it possible to prevent the semiconductor chip CPL from overlapping with the area positioned directly above the gate pad electrode PDGH of the semiconductor chip CPH. Therefore, it is possible to electrically couple the gate terminal TGH to the gate pad electrode PDGH of the semiconductor chip CPH and prevent it from being electrically coupled to the back surface drain electrode BEL of the semiconductor chip CPL. (Refer toFIG. 7and the like.)

As mentioned above, the semiconductor chip CPL and the semiconductor chip CPH identical in chip size and the shapes and arrangement of the source pad electrode and the gate pad electrode are vertically arranged so that their respective centers are displaced from each other. In this case, as seen from the comparison ofFIG. 14andFIG. 16, it is desirable that the arrangement of the semiconductor chip CPL should correspond to the arrangement obtained by turning the semiconductor chip CPH 180°. That is, it is desirable that the orientation of the semiconductor chip CPL should be made identical with the orientation obtained by turning the semiconductor chip CPH 180°. (Specifically, this orientation is equivalent to the orientation obtained by turning the semiconductor chip CPH 180° in a plane parallel to the front surface or back surface thereof.) In other words, the following measure is taken when two semiconductor chips with the same configuration are used for the semiconductor chip CPL and the semiconductor chip CPH and vertically arranged with their respective centers displaced from each other: the two semiconductor chips are not set in the same orientation but one is set as the semiconductor chip CPH and the other is set as the semiconductor chip CPL in the orientation obtained by turning the one 180°. Thus the semiconductor chip CPH and the semiconductor chip CPL are set in orientations obtained by turning each other 180°. The semiconductor chip CPL and the semiconductor chip CPH are displaced so that the gate pad electrode PDGH of the semiconductor chip CPH and the gate pad electrode PDGL of the semiconductor chip CPL get away from each other unlike the following cases: cases where the center of the semiconductor chip CPH and the center of the semiconductor chip CPL agree with each other. This makes it possible to prevent the semiconductor chip CPL from overlapping with the area positioned directly above the gate pad electrode PDGH of the semiconductor chip CPH even though the displacement between the semiconductor chip CPL and the semiconductor chip CPH is small. (That is, the semiconductor chip CPL can be prevented from overlapping with the area positioned directly above the gate pad electrode PDGH of the semiconductor chip CPH even though the area of overlap between the semiconductor chips CPL, CPH is large.) Therefore, the plane area of the semiconductor device SM1can be further reduced.

It is desirable that the thickness T1of the drain terminal TDH should be larger than the following thicknesses: the thickness T2of the gate terminal TGH, the thickness T3of the source-drain terminal TSD, the thickness T4of the gate terminal TGL, and the thickness T5of the source terminal TSL (That is, T1>T2, T3, T4, T5). The reason for this will be described below. The thicknesses T1to T5are defined inFIG. 7andFIG. 8.

Heat from the semiconductor chips CPH, CPL is radiated mainly from the drain terminal TDH, gate terminal TGH, source-drain terminal TSD, gate terminal TGL, and source terminal TSL to outside the semiconductor device SM1. (The heat is radiated to, for example, the mounting board over which the semiconductor device SM1is mounted.) Of these terminals, the drain terminal TDH exposed in the main surface MRb of the encapsulation resin portion MR contributes most to heat radiation. For this reason, the heat radiation characteristics of the semiconductor device SM1can be enhanced (that is, the thermal resistance of the semiconductor device SM1can be reduced) by increasing the thickness T1of the drain terminal TDH.

Meanwhile, the gate terminal TGH, source-drain terminal TSD, gate terminal TGL, and source terminal TSL are bent outside the encapsulation resin portion MR. If the thicknesses T2, T3, T4, T5are too large, their moldability is degraded and it is difficult to bend them. If the drain terminal TDH, gate terminal TGH, source-drain terminal TSD, gate terminal TGL, and source terminal TSL are all thickened, increase in the size (thickness) of the semiconductor device is incurred.

For this reason, the following can be implemented by making the thickness T2, T3, T4, T5of each of the gate terminal TGH, source-drain terminal TSD, gate terminal TGL, and source terminal TSL smaller than the thickness T1of the drain terminal TDH: it can be made easier to mold (bend) the gate terminal TGH, source-drain terminal TSD, gate terminal TGL, and source terminal TSL. Since the drain terminal TDH is flat and is not bent, no processing problem arises even when it is thicker than the gate terminal TGH, source-drain terminal TSD, gate terminal TGL, and source terminal TSL. As mentioned above, the following can be implemented by making the drain terminal TDH thicker than the gate terminal TGH, source-drain terminal TSD, gate terminal TGL, and source terminal TSL: both enhancement of the heat radiation characteristics of the semiconductor device SM1and ease of terminal processing can be achieved. In addition, the size (thickness) of the semiconductor device SM1can be reduced.

In consideration of ease of processing of a lead frame (corresponding to the lead frames LF1, LF2, LF3described later) for the manufacture of the semiconductor device SM1, it is desirable to take the following measure: the thickness T2of the gate terminal TGH and the thickness T3of the source-drain terminal TSD are made equal to each other (that is, T2=T3). Further, it is desirable that the thickness T4of the gate terminal TGL and the thickness T5of the source terminal TSL should be equal to each other (T4=T5). The thickness T1of the drain terminal TDH is identical with the thickness of the lead frame LF1described later; the respective thicknesses T2, T3of the gate terminal TGH and the source-drain terminal TSD are identical with the thickness of the lead frame LF2described later; and the respective thicknesses T4, T5of the gate terminal TGL and the source terminal TSL are identical with the thickness of the lead frame LF3described later. For the above-mentioned reason, therefore, it is desirable to make the thickness of the lead frame LF1described later larger than the respective thicknesses of the lead frames LF2, LF3described later.

As an example of the thickness T1to T5of each terminal, the following measure can be taken: the thickness T1of the drain terminal TDH (that is, the thickness of the lead frame LF1described later) is set to, for example, 0.4 mm or so; and the thickness T2, T3, T4, T5of each of the gate terminal TGH, source-drain terminal TSD, gate terminal TGL, and source terminal TSL is set to, for example, 0.2 mm or so. (That is, the thickness of each of the lead frames LF2, LF3described later is set to this value.)

In the encapsulation resin portion MR, the source terminal TSL is placed in a layer (height position) different from that of the gate terminal TGH and the source-drain terminal TSD. Therefore, the source terminal TSL could also be provided so that it planarly overlaps with the gate pad electrode PDGH of the semiconductor chip CPH; however, it is desirable that the source terminal TSL should not planarly overlap with the gate pad electrode PDGH of the semiconductor chip CPH. (Refer toFIG. 7,FIG. 13, and the like.) As a result, the following effect can be obtained. The gate terminal TGH is joined to the gate pad electrode PDGH of the semiconductor chip CPH with solder SLD by the solder reflow processing, described later, at Step S7. Until the stage prior to the formation of the encapsulation resin portion MR at the molding step, described later, or Step S8after then, the source terminal TSL does not interfere; and the state of junction between the gate terminal TGH and the gate pad electrode PDGH of the semiconductor chip CPH through solder SLD can be observed (appearance inspection). In addition, the source terminal TSL does not interfere and the state of junction between the source-drain terminal TSD and the source pad electrode PDSH of the semiconductor chip CPH through solder SLD can be observed (appearance inspection). For this reason, the reliability of the semiconductor device SM1can be enhanced.

To facilitate this observation (appearance inspection), it is more desirable that the following state should be established as illustrated inFIG. 13toFIG. 15: part of each of the gate pad electrode PDGH and source pad electrode PDSH of the semiconductor chip CPH does not planarly overlap with the gate terminal TGH, source-drain terminal TSD, source terminal TSL, or gate terminal TGL. That is, it is more desirable that the following state should be established: part (most part) of the gate pad electrode PDGH of the semiconductor chip CPH planarly overlaps with the gate terminal TGH but the remaining part does not planarly overlap with the gate terminal TGH, source-drain terminal TSD, source terminal TSL, or gate terminal TGL. Further, it is more desirable that the following state should be established: part (most part) of the source pad electrode PDSH of the semiconductor chip CPH planarly overlaps with the source-drain terminal TSD but the remaining part does not planarly overlap with the gate terminal TGH, source-drain terminal TSD, source terminal TSL, or gate terminal TGL.

The following widths external to the encapsulation resin portion MR will be set as follows: the widths of the outer lead portions of the source-drain terminal TSD are W1and W2; the widths of the outer lead portions of the source terminal TSL are W3and W4; the width of the outer lead portion of the gate terminal TGH is W5; and the width of the outer lead portion of the gate terminal TGL is W6. At this time, it is desirable that the widths W1, W2, W3, W4should be larger than the widths W5, W6(that is, W1, W2, W3, W4>W5, W6). Each width W1to W6is defined inFIG. 5. As a result, it is possible to reduce the on-resistance of the power MOS QL1for low side and power MOS QH1for high side incorporated in the semiconductor device SM1. Further, it is possible to enhance the heat radiation characteristics of the semiconductor device SM1(that is, reduce the thermal resistance of the semiconductor device SM1).

Description will be given to an example of the configuration of the semiconductor chips CPH, CPL used in the semiconductor device SM1in this embodiment.

The semiconductor chips CPH, CPL used in this embodiment are power MOSFET chips (semiconductor chips in which a power MOSFET is formed) and are specifically semiconductor chips in which a vertical MOSFET is formed. The vertical MOSFET cited here corresponds to MOSFET in which a source-drain current flows in the direction of the thickness of a semiconductor substrate (direction substantially perpendicular to the main surface of the semiconductor substrate). As mentioned above, a semiconductor chip in which a vertical MOSFET is formed is used for the semiconductor chips CPH, CPL. This is also intended to couple the semiconductor chip CPH (power MOS QH1) and the semiconductor chip CPL (power MOS QL1) in series so that the following is implemented: the semiconductor chip CPH is sandwiched between the drain terminal TDH and the source-drain terminal TSD and gate terminal TGH; and the semiconductor chip CPL is sandwiched between the source-drain terminal TSD and the source terminal TSL and gate terminal TGL.

Description will be given to an example of the configuration of the semiconductor chips CPH, CPL with reference toFIG. 17.FIG. 17is a substantial part sectional view illustrating an example of the structure of the semiconductor chips CPH, CPL. The power MOS QH1is formed in the main surface of the semiconductor substrate (hereafter, simply referred to as substrate)21comprising the semiconductor chip CPH; and the power MOS QL1is formed in the main surface of the substrate21comprising the semiconductor chip CPL.

As illustrated inFIG. 17, the substrate21includes: a substrate body (semiconductor substrate, semiconductor wafer)21acomposed of n+-type single crystal silicon or the like doped with, for example, arsenic (As); and an epitaxial layer (semiconductor layer)21bcomposed of, for example, n−-type silicon single crystal formed over the main surface of the substrate body21a. For this reason, the substrate21is a so-called epitaxial wafer. In the main surface of this epitaxial layer21b, there is formed a field insulating film (element isolation region)22composed of, for example, silicon oxide or the like.

In cases where the semiconductor chip illustrated inFIG. 17is the semiconductor chip CPH, multiple unit transistor cells comprising the power MOS QH1are formed in the active region encircled with the field insulating film22and a p-type well PWL1positioned thereunder. The power MOS QH1is formed by coupling these unit transistor cells in parallel. In cases where the semiconductor chip illustrated inFIG. 17is the semiconductor chip CPL, multiple unit transistor cells comprising the power MOS QL1are formed in the active region encircled with the field insulating film22and the p-type well PWL1positioned thereunder. The power MOS QL1is formed by coupling these unit transistor cells in parallel. Each unit transistor cell is formed of an n-channel power MOSFET with, for example, a trench gate structure.

The substrate body21aand the epitaxial layer21bfunction as the drain region of the unit transistor cells.

In cases where the semiconductor chip illustrated inFIG. 17is the semiconductor chip CPH, the back surface drain electrode BEH is formed in the back surface of the substrate21(semiconductor chip CPH). In cases where the semiconductor chip illustrated inFIG. 17is the semiconductor chip CPL, the back surface drain electrode BEL is formed in the back surface of the substrate21(semiconductor chip CPL). The back surface drain electrodes BEH, BEL are formed by, for example, stacking a titanium (Ti) layer, a nickel (Ni) layer, and a gold (Au) layer over the back surface of the substrate21in this order.

A p-type semiconductor region23formed in the epitaxial layer21bfunctions as the channel formation region of the unit transistor cells. A n+-type semiconductor region24formed at the upper part of the p-type semiconductor region23functions as the source region of the unit transistor cells. Therefore, the semiconductor region24is a semiconductor region for source.

In the substrate21, further, there are formed trenches extended form its main surface in the direction of the thickness of the substrate21. The trenches25are so formed that they are extended from the upper surface of the n+-type semiconductor region24, penetrate the n+-type semiconductor region24and the p-type semiconductor region23, and are terminated in the epitaxial layer21bpositioned thereunder. Over the bottom surface and lateral surface of each trench25, there is formed a gate insulating film26composed of, for example, silicon oxide. Each trench25is filled with a gate electrode27with the gate insulating film26in between. The gate electrode27is comprised of, for example, a polycrystalline silicon film added with, for example, an n-type impurity (for example, phosphorus). The gate electrode27functions as the gate electrode of the unit transistor cells. Also over part of the field insulating film22, there is formed a wiring portion27afor gate extraction composed of a conductive film in the same layer as the gate electrode27. The gate electrode27and the wiring portion27afor gate extraction are integrally formed and electrically coupled to each other. In an area not shown in the sectional view inFIG. 17, the gate electrode27and the wiring portion27afor gate extraction are integrally coupled together. The wiring portion27afor gate extraction is electrically coupled with gate wiring30G through a contact hole29aformed in an insulating film28covering it.

Meanwhile, source wiring30S is electrically coupled with the n+-type semiconductor region24for source through contact holes29bformed in the insulating film28. The source wiring30S is electrically coupled to a p+-type semiconductor regions31formed between the n+-type semiconductor regions24at the upper part of the p-type semiconductor region23and electrically coupled with the p-type semiconductor region23for channel formation therethrough. The gate wiring30G and the source wiring30S can be formed by: forming a metal film, for example, an aluminum film (or an aluminum alloy film) over the insulating film28with the contact holes29a,29bformed therein so that the contact holes29a,29bare filled therewith; and patterning this metal film (aluminum film or aluminum alloy film). For this reason, the gate wiring30G and the source wiring30S are comprised of an aluminum film, an aluminum alloy film, or the like.

The gate wiring30G and the source wiring30S are covered with a protective film (insulating film)32composed of polyimide resin or the like. This protective film32is the film (insulating film) in the uppermost layer of the semiconductor chips CPH, CPL.

In part of the protective film32, there is formed an opening33exposing part of the gate wiring30G and source wiring30S positioned thereunder. In case of the semiconductor chip CPH, the portion of the gate wiring30G exposed from the opening33is the gate pad electrode PDGH and the portion of the source wiring30S exposed from the opening33is the source pad electrode PDSH. In case of the semiconductor chip CPL, the portion of the gate wiring30G exposed from the opening33is the gate pad electrode PDGL and the portion of the source wiring30S exposed from the opening33is the source pad electrode PDSL.

A metal layer34may be formed over the front surfaces of the source pad electrodes PDSH, PDSL and gate pad electrodes PDGH, PDGL by planting or the like. (That is, a metal layer34may be formed over the portions of the gate wiring30G and source wiring30S exposed at the bottom of the opening33). This metal layer34is formed of a laminated film of a copper (Cu) film, a nickel (Ni) film, and a gold (Au) film formed from bottom in this order. Or, it is formed of a laminated film of a titanium (Ti) film, a nickel (Ni) film, and a gold (Au) film formed from bottom in this order or the like.

In the thus configured semiconductor chips CPH, CPL, the operating current of each unit transistor of the power MOSs QH1, QL1flows between the epitaxial layer21bfor drain and the n+-type semiconductor region24for source. At this time, it flows in the direction of the thickness of the substrate21along the lateral surface of each gate electrode27(that is, the lateral surface of each trench25). That is, channels are formed along the direction of the thickness of the semiconductor chips CPH, CPL.

<Manufacturing Process for Semiconductor Device>

FIG. 18is a manufacture process flow chart illustrating a manufacturing process (assembly step) for the semiconductor device SM1in this embodiment.FIG. 19is an overall plan view of the lead frame LF1used in the manufacturing process (assembly step) for the semiconductor device SM1in this embodiment; andFIG. 20is a substantial part plan view of the lead frame LF1.FIG. 21is an overall plan view of the lead frame LF2used in the manufacturing process (assembly step) for the semiconductor device SM1in this embodiment andFIG. 22is a substantial part plan view of the lead frame LF2.FIG. 23is an overall plan view of the lead frame LF3used in the manufacturing process (assembly step) for the semiconductor device SM1in this embodiment andFIG. 24is a substantial part plan view of the lead frame LF3. ThoughFIG. 20,FIG. 22, andFIG. 24are plan views, the lead frames LF1, LF2, LF3are hatched to facilitate visualization (to make the shapes of the lead frames LF1, LF2, LF3easily understandable).FIG. 25is an overall plan view (top view) of an assembly jig41used in the manufacturing process (assembly step) for the semiconductor device SM1in this embodiment;FIG. 26is a substantial part plan view (partial enlarged plan view) of the assembly jig41; andFIG. 27toFIG. 31are substantial part sectional views of the assembly jig41. ThoughFIG. 26is a plan view, supporting faces SF1a, SF1b, SF1cand pins42are hatched to facilitate visualization (to make the layout of the supporting faces SF1a, SF1b, SF1cand pins42easily understandable).FIG. 32toFIG. 72are plan views (overall plan views or substantial part plan views) or sectional views (substantial part sectional views) of the semiconductor device SM1in this embodiment in manufacturing process.

In this embodiment, two semiconductor chips CPH, CPL and three lead frames LF1, LF2, LF3are used to manufacture one semiconductor device SM1. As mentioned above, the semiconductor chip CPH has the source pad electrode PDSH and the gate pad electrode PDGH in its front surface and the back surface drain electrode BEH in its entire back surface; and the semiconductor chip CPL has the source pad electrode PDSL and the gate pad electrode PDGL in its front surface and the back surface drain electrode BEL in its entire back surface.

Each lead frame LF1, LF2, LF3is a multiple lead frame (multiple pattern lead frame) in which multiple unit regions (hereafter, referred to as unit regions UT1) are arranged (repeated). One semiconductor device SM1is formed from each unit region.FIG. 19,FIG. 21, andFIG. 23illustrate cases where in each lead frame LF1, LF2, LF3, multiple unit regions UT1, from each of which one semiconductor device SM1is formed, are arranged in one direction (Y-direction in these examples). As an example, these drawings illustrate cases where six unit regions UT1are coupled to form each lead frame LF1, LF2, LF3. However, the number of repeated unit regions UT1is not limited to six. As another embodiment, unit regions UT1may be arranged in a matrix pattern (array pattern) in each lead frame LF1, LF2, LF3.

In the lead frames LF1, LF2, LF3inFIG. 19,FIG. 21, andFIG. 23, unit regions UT1are repeated in the Y-direction.FIG. 20,FIG. 22, andFIG. 24are enlarged views of a unit region UT1aas one of these unit regions. (That is,FIG. 20,FIG. 22, andFIG. 24are respectively enlarged views of the area encircled with a broken line inFIG. 19,FIG. 21, andFIG. 23).

The lead frame (first frame) LF1illustrated inFIG. 19andFIG. 20integrally includes the drain terminal (chip placement portion) TDH in each unit region UT1. The lead frame (second frame) LF2illustrated inFIG. 21andFIG. 22integrally includes the source-drain terminal (first lead terminal portion) TSD and the gate terminal (first lead terminal portion) TGH in each unit region UT1. The lead frame (third frame) LF3illustrated inFIG. 23andFIG. 24integrally includes the source terminal (second lead terminal portion) TSL and the gate terminal (second lead terminal portion) TGL in each unit region UT1. In each lead frame LF1, LF2, LF3, each drain terminal TDH, source-drain terminal TSD, gate terminal TGH, source terminal TSL, and gate terminal TGL are flat and have not been bent yet. Of these terminals, each drain terminal TDH remains flat until each semiconductor device SM1is completed. Meanwhile, each source-drain terminal TSD, gate terminal TGH, source terminal TSL, and gate terminal TGL remain flat until immediately before the bending step described later, or Step S12is carried out but they are bent at the bending step described later, or Step S12.

As illustrated inFIG. 20, each drain terminal TDH is integrally connected (coupled) to the framework LF1aof the lead frame LF1. As illustrated inFIG. 22, each source-drain terminal TSD and each gate terminal TGH are integrally connected (coupled) to the framework LF2aof the lead frame LF2. As illustrated inFIG. 24, each source terminal TSL and each gate terminal TGL are integrally connected (coupled) to the framework LF3aof the lead frame LF3. In the lead frame LF2, as illustrated inFIG. 22, each gate terminal TGH is coupled with each source-drain terminal TSD through a tie bar TB1at its outer lead portion external to the encapsulation resin portion MR to be formed later. In the lead frame LF3, as illustrated inFIG. 24, each gate terminal TGL is coupled with each source terminal TSL through a tie bar TB2at its outer lead portion external to the encapsulation resin portion MR to be formed later.

The lead frames LF1, LF2, LF3are formed of conductive material, preferably, metal material such as copper (Cu) or copper alloy. Each lead frame LF1, LF2, LF3can be fabricated by, for example, processing a metal plate (copper plate or the like) into a predetermined shape by molding (press work), etching, or the like.

It is desirable that the thickness of the lead frame LF1(equal to the thickness T1of the drain terminal TDH) should be larger than the following thicknesses: the thickness of the lead frame LF2(equal to the thickness T2of the gate terminal TGH and the thickness T3of the source-drain terminal TSD); and the thickness of the lead frame LF3(equal to the thickness T4of the gate terminal TGL and the thickness T5of the source terminal TSL). The reason for this is as described with respect to the relation between the thicknesses T1to T5.

As seen with reference toFIG. 20,FIG. 22, andFIG. 24, each lead frame LF1, LF2, LF3is provided with various openings OP. Among these openings OP, aside from the openings OP1, there are the following, for example: those provided in planned cutting positions to make it easy to cut the lead frames LF1, LF2, LF3after the formation of the encapsulation resin portion MR; those provided to make it easier to transport the lead frames LF1, LF2, LF3; those (corresponding to openings OP2) provided for the positioning of the lead frames LF1, LF2, LF3; and the like.

After the preparation of the semiconductor chips CPH, CPL and the lead frames LF1, LF2, LF3, the lead frame LF1is set (placed, mounted) over the assembly jig (support, placement table, stage, mount, seat, jig)41(Step S2inFIG. 18).

The plan view (top view) inFIG. 25shows the entire assembly jig41with the lead frame LF1not set yet; the substantial part plan view (partial enlarged plan view) inFIG. 26is an enlarged view of the area (corresponding to the unit region RG1a) encircled with a broken line inFIG. 25;FIG. 27toFIG. 30are sectional views of the assembly jig41inFIG. 25. The section taken along line C1-C1ofFIG. 26substantially corresponds toFIG. 27; the section taken along line C2-C2ofFIG. 26substantially corresponds toFIG. 28; the section taken along line C3-C3ofFIG. 26substantially corresponds toFIG. 29; the section taken along line C4-C4ofFIG. 26substantially corresponds toFIG. 30; and the section taken along line C5-C5ofFIG. 26substantially corresponds toFIG. 31.FIG. 32is an overall plan view (top view) illustrating the lead frame LF1as is set over the assembly jig41at Step S2; andFIG. 33is a partial enlarged plan view (substantial part plan view) ofFIG. 32, showing an enlarged view of the area (corresponding to the unit regions UT1a, RG1a) encircled with a broken line inFIG. 32.FIG. 34is a sectional view taken along line C1-C1ofFIG. 33;FIG. 35is a sectional view taken along line C2-C2ofFIG. 33;FIG. 36is a sectional view taken along line C3-C3ofFIG. 33;FIG. 37is a sectional view taken along line C4-C4ofFIG. 33; andFIG. 38is a sectional view taken along line C5-C5ofFIG. 33. ThoughFIG. 33is a plan view, the supporting faces SF1b, SF1cand pins42in the upper surface of the assembly jig41and the lead frame LF1are hatched to facilitate visualization (to make the layout of each element easily understandable).

It is desirable that the assembly jig41illustrated inFIG. 25toFIG. 31should be formed of the following material: a material having heat resistance sufficient to prevent thermal deformation against the solder reflow processing, described later, at Step S7with the processing temperature of approximately 300 to 400° C. Typical materials include carbon material. Since the carbon material is also difficult to process and handle, however, SUS material (stainless steel) may be substituted for it. The assembly jig41is so configured that the lead frames LF1, LF2, LF3can be stacked and set on its upper surface (main surface on the side shown inFIG. 25andFIG. 26) and is movable (portable).

The assembly jig41is so configured that multiple unit regions (hereafter, referred to as unit regions RG1) in each of which each unit region UT1of the lead frames LF1, LF2, LF3is set are arranged (repeated). How the unit regions RG1are arranged in the assembly jig41is identical with how the unit regions UT1are arranged in each lead frame LF1, LF2, LF3. More specific description will be given. When multiple unit regions UT1are arranged in the Y-direction in each lead frame LF1, LF2, LF3as illustrated inFIG. 19,FIG. 21, andFIG. 23, the following measure is taken: multiple unit regions RG1are arranged in the Y-direction in the assembly jig41as illustrated inFIG. 25. The number of arranged unit regions UT1in each lead frame LF1, LF2, LF3and the number of arranged unit regions RG1in the assembly jig41are identical with each other. However, the number is not limited to six (in the cases inFIG. 19,FIG. 21,FIG. 23, andFIG. 25). In the assembly jig41inFIG. 25, unit regions RG1are repeated in the Y-direction.FIG. 26is an enlarged view of a unit region RG1aas one of these unit regions. (That is,FIG. 26is an enlarged view of the area encircled with a broken line inFIG. 25.)

The lead frame LF1has two main surfaces positioned on the opposite side to each other. The main surface on the side where the semiconductor chip CPH is placed later will be designated as the upper surface of the lead frame LF1. (That is, this upper surface is the main surface on the side where the lead frame is opposed to the lead frame LF2when the assembly WK described later is formed.) The main surface on the opposite side to this upper surface will be designated as the lower surface of the lead frame LF1. (That is, this lower surface is the main surface on the side where the lead frame is opposed to the assembly jig41or a die MD2at Step S2or S8, described later.) The lead frame LF2has two main surfaces positioned on the opposite side to each other. The main surface on the side where the semiconductor chip CPL is placed later will be designated as the upper surface of the lead frame LF2. (That is, this upper surface is the main surface on the side where the lead frame is opposed to the lead frame LF3when the assembly WK described later is formed). The main surface on the opposite side to this upper surface will be designated as the lower surface of the lead frame LF2. (That is, this lower surface is the main surface on the side where the lead frame is opposed to the lead frame LF1when the assembly WK described later is formed.) The lead frame LF3has two main surfaces positioned on the opposite side to each other. The main surface on the side where the lead frame is opposed to the lead frame LF2(semiconductor chip CPL) when the assembly WK described later is formed will be designated as the lower surface of the lead frame LF3. The main surface on the opposite side to this lower surface will be designated as the upper surface of the lead frame LF3.

In each drain terminal TDH of the lead frame LF1, its main surface corresponding to the upper surface of the lead frame LF1will be designated as the upper surface of the drain terminal TDH; and its main surface corresponding to the lower surface of the lead frame LF1will be designated as the lower surface of the drain terminal TDH. The lower surface of the drain terminal TDH becomes the lower surface TDHa exposed from the encapsulation resin portion MR formed later. In each source-drain terminal TSD and gate terminal TGH of the lead frame LF2, the following designation will be used: their main surfaces corresponding to the upper surface of the lead frame LF2will be designated as the upper surface of the source-drain terminal TSD and the upper surface of the gate terminal TGH; and their main surfaces corresponding to the lower surface of the lead frame LF2will be designated as the lower surface of the source-drain terminal TSD and the lower surface of the gate terminal TGH. In each gate terminal TGL and source terminal TSL of the lead frame LF3, the following designation will be used: their main surfaces corresponding to the upper surface of the lead frame LF3will be designated as the upper surface of the gate terminal TGL and the upper surface of the source terminal TSL; and their main surfaces corresponding to the lower surface of the lead frame LF3will be designated as the lower surface of the gate terminal TGL and the lower surface of the source terminal TSL.

The assembly jig41illustrated inFIG. 25toFIG. 31has the following faces in its upper surface: a supporting face (first supporting face) SF1afor setting (supporting) the lead frame LF1; supporting faces (second supporting faces) SF1bfor setting (supporting) the lead frame LF2, protruded to above the supporting face SF1a; and supporting faces (third supporting faces) SF1cfor supporting (setting) the lead frame LF3, protruded to above the supporting faces SF1a, SF1b. That is, in the upper surface of the assembly jig41, the supporting faces SF1bare higher than the supporting face SF1aand the supporting faces SF1care higher than the supporting faces SF1b. This can be achieved by: providing the upper surface of the assembly jig41with two different kinds of salient (two-level) steps (mount portions, salient portions, protruded portions)43,44different in height; taking the upper surfaces of the lower (lower-level) steps43as the supporting faces SF1b; and taking the upper surfaces of the higher (higher-level) steps44as the supporting faces SF1c. In the assembly jig41, the supporting faces SF1bare identical in height. In the assembly jig41, the supporting faces SF1care identical in height.

The upper surface of the assembly jig41is also provided with positioning pins (first projections, protruded portions, salient portions, columnar portions)42. The pins are projections for determining the planar positions of the lead frames LF1, LF2, LF3. The pins42are portions (projections) locally protruded upward in the upper surface of the assembly jig41and has such a shape that they can be inserted into the openings OP2in the lead frames LF1, LF2, LF3. When the openings OP2are circular in shape, it is desirable that the pins42should be columnar.

At Step S2, as illustrated inFIG. 32toFIG. 38, the lead frame LF1is set over the upper surface of the assembly jig41. At this time, as seen fromFIG. 33andFIG. 38as well, the lead frame LF1is set over the upper surface of the assembly jig41so that the following is implemented: the pins42of the assembly jig41are inserted into the positioning openings (holes, through holes) OP2provided in the lead frame LF1.

At Step S2, the lead frame LF1is set over the upper surface of the assembly jig41so the following is implemented: the upper surface (main surface on the side where the semiconductor chip CPH is placed later) of the lead frame LF1faces upward and the lower surface of the lead frame LF1is opposed to the assembly jig41.

As seen fromFIG. 33and the like as well, the planar shape of each of the lead frames LF1, LF2, LF3and the plane configuration (layout) of the supporting faces SF1a, SF1b, SF1care so designed that the following is implemented: the area of the upper surface of the assembly jig41that planarly overlaps with the lead frame LF1when the lead frame LF1is set at Step S2is taken as the supporting face SF1a; and the supporting faces SF1b, SF1bare arranged in areas where they do not planarly overlap with the lead frame LF1. Further, the planar shape of each of the lead frames LF1, LF2, LF3and the plane configuration (layout) of the supporting faces SF1a, SF1b, SF1care so designed that the following is implemented: in the upper surface of the assembly jig41, the supporting faces SF1cdo not planarly overlap with the lead frame LF1or LF2when the lead frame LF2is set at Step S4described later.

At Step S2, for this reason, the lead frame LF1can be set over the supporting face SF1aof the assembly jig41without the interference of the supporting faces SF1bor SF1c. At Step S4described later, the lead frame LF2can be set over the assembly jig41so that at least part of the lead frame LF2is positioned and supported over the supporting faces SF1bwithout the interference of the supporting faces SF1c. At Step S6described later, the lead frame LF3can be set over the assembly jig41so that at least part of the lead frame LF3is positioned and supported over the supporting faces SF1c.

Therefore, the lead frame LF1set over the assembly jig41at Step S2is set over the supporting face SF1aso that the lower surface of the lead frame LF1is in contact with the supporting face SF1a. Thus the lead frame LF1is supported by the supporting face SF1a. As mentioned above, the lower surface (especially, the lower surface of each drain terminal TDH) of the lead frame LF1is set in contact with the supporting face SF1aof the assembly jig41. As a result, the height position of the lower surface of the lead frame LF1is controlled and made equal to that of the supporting face SF1aof the assembly jig41.

Subsequently, as illustrated inFIG. 39toFIG. 42, solder (solder material) SLDa is set (supplied) onto the upper surface of the drain terminal TDH in each unit region UT1of the lead frame LF1. Thereafter, each semiconductor chip CPH is set (placed) over the upper surface of each drain terminal TDH with the solder SLDa set thereon (Step S3inFIG. 18).

FIG. 39is an overall plan view (top view) obtained when Step S3(semiconductor chip CPH setting step) has been carried out and shows the same area as inFIG. 25andFIG. 32.FIG. 40is a substantial part plan view (partial enlarged plan view) obtained when Step S3(semiconductor chip CPH setting step) has been carried out and shows the same area as inFIG. 26andFIG. 33.FIG. 41is a partial enlarged plan view of the area (that is, the drain terminal TDH and its surrounding area)45encircled with a broken line inFIG. 40.FIG. 41shows what is obtained by turning the area45inFIG. 4090° clockwise and in this drawing the assembly jig41is omitted. ThoughFIG. 42is a sectional view taken along line C6-C6of theFIG. 41, the openings OP1in the lead frame LF1are omitted in the sectional view inFIG. 42to facilitate visualization.

Solder paste may be used as the solder SLDa used at Step S3but use of solder pellets (solder foil) is more desirable. When solder pellets are used as the solder SLDa, it is easy to evenly control the amount of solder SLDa supplied to each drain terminal TDH. Therefore, it is possible to reduce variation in the thickness of the solder SLD joining each drain terminal TDH and each semiconductor chip CPH. When solder pellets are used as the solder SLDa, it is desirable to take the following procedure: flux (flux material) is applied to the upper surface of each drain terminal TDH of the lead frame LF1and then solder pellets are set; and flux (flux material) is further applied to the solder pellets and each semiconductor chip CPH is placed thereover.

As the result of Step S3, each semiconductor chip CPH is set (placed) over the upper surface of each drain terminal TDH of the lead frame LF1with the solder SLDa in between. At Step S3, each semiconductor chip CPH is placed so that its back surface drain electrode BEH is opposed to the upper surface of each drain terminal TDH of the lead frame LF1. When the solder SLDa is solder paste, each semiconductor chip CPH is temporarily fixed by the adhesion (adhesiveness) of the solder paste. When the solder SLDa is solder pellets, it is temporarily fixed by the adhesion (adhesiveness) of flux.

In this embodiment, the following procedure is taken before each semiconductor chip CPH is placed over each drain terminal TDH of the lead frame LF1: solder (solder material, solder layer) SLDb is supplied (formed) over the source pad electrode PDSH and gate pad electrode PDGH in the front surface of each semiconductor chip CPH. Specifically, the following procedure is taken: flux (flux material) is applied to the source pad electrode PDSH and the gate pad electrode PDGH of each semiconductor chip CPH before it is placed over each drain terminal TDH of the lead frame LF1and solder pellets are set; flux (flux material) is further applied to these solder pellets and using a heat block (not shown) or the like, each semiconductor chip CPH is heated to melt and solidify the flux and the solder pellets. As a result, a solder layer (solder SLDb in this example) is formed over the source pad electrode PDSH and gate pad electrode PDGH of each semiconductor chip CPH. Then each semiconductor chip CPH in this state is placed over each drain terminal TDH of the lead frame LF1. As mentioned above, solder pellets are used to form a solder layer (solder SLDb in this example) over the source pad electrode PDSH and gate pad electrode PDGH of each semiconductor chip CPH. Thereafter, this semiconductor chip CPH is placed over each drain terminal TDH of the lead frame LF1. This makes it easier to evenly control the amount of solder SLDb over the source pad electrode PDSH and gate pad electrode PDGH of each semiconductor chip CPH. For this reason, it is possible to reduce variation in the thickness of the solder SLD joining together the source pad electrode PDSH and gate pad electrode PDGH of each semiconductor chip CPH and each source-drain terminal TSD and each gate terminal TGH.

As another embodiment, the following procedure may be taken without previously supplying solder SLDb to the source pad electrode PDSH or gate pad electrode PDGH in the front surface of each semiconductor chip CPH: this semiconductor chip CPH is placed over each drain terminal TDH of the lead frame LF1; and then solder SLDb is supplied (set) over the source pad electrode PDSH and gate pad electrode PDGH in the front surface of the semiconductor chip CPH. In this case, for example, solder pastes or the like can be used as the solder SLDb.

FIG. 43is an overall plan view (top view) obtained when Step S4(lead frame LF2setting step) has been carried out and shows the same area as inFIG. 25,FIG. 32, andFIG. 39.FIG. 44is a substantial part plan view (partial enlarged plan view) obtained when Step S4(lead frame LF2setting step) has been carried out and shows the same area as inFIG. 26,FIG. 33, andFIG. 40.FIG. 45is a sectional view taken along line C1-C1ofFIG. 44;FIG. 46is a sectional view taken along line C2-C2ofFIG. 44;FIG. 47is a sectional view of line C3-C3ofFIG. 44;FIG. 48is a sectional view taken along line C4-C4ofFIG. 44; andFIG. 49is a sectional view taken along line C5-C5ofFIG. 44.FIG. 50is a substantial part plan view (partial enlarged plan view) obtained when Step S4(lead frame LF2setting step) has been carried out and shows the same area as inFIG. 41(equivalent to the area45). ThoughFIG. 51is a sectional view taken along line C6-C6ofFIG. 50, the openings OP1in the lead frame LF1are omitted in the sectional view inFIG. 51to facilitate visualization. ThoughFIG. 44is a plan view, the supporting faces SF1b, SF1cand pins42in the upper surface of the assembly jig41and the lead frame LF2are hatched to facilitate visualization (to make the layout of each element easily understandable).

At Step S4, the lead frame LF2is set over the upper surface of the assembly jig41so that the following is implemented: the pins42of the assembly jig41are inserted into the positioning openings (holes, through holes) OP2provided in the lead frame LF2. The relative positional relation (planar positional relation) between the assembly jig41, lead frame LF1, and lead frame LF2is defined (determined) by the following: the pins42of the assembly jig41, the openings OP2in the lead frame LF1, and the openings OP2in the lead frame LF2.

Thus the lead frame LF2is set over the lead frame LF1and the semiconductor chip CPH so that the following is implemented: each source-drain terminal TSD of the lead frame LF2is set over the source pad electrode PDSH of each semiconductor chip CPH; and each gate terminal TGH of the lead frame LF2is set over the gate pad electrode PDGH of each semiconductor chip CPH. That is, each source-drain terminal TSD of the lead frame LF2is set over the source pad electrode PDSH of each semiconductor chip CPH with solder SLDb in between; at the same time, each gate terminal TGH of the lead frame LF2is set over the gate pad electrode PDGH of each semiconductor chip CPH with solder SLDb in between.

It is more desirable to take the following procedure prior to the step, or Step S4, for setting the lead frame LF2over the assembly jig41: flux (flux material) is applied to the lower surface of each source-drain terminal TSD and gate terminal TGH of the lead frame LF2. (That is, flux is applied to their surfaces on the side where they are opposed to the source pad electrode PDSH and gate pad electrode PDGH of each semiconductor chip CPH.) Thereafter, the lead frame LF2setting step, or Step S4is carried out.

Subsequently, as illustrated inFIG. 52toFIG. 55, solder (solder material) SLDc is set (supplied) to the upper surface of the source-drain terminal TSD in each unit region UT1of the lead frame LF2. Thereafter, each semiconductor chip CPL is set (placed) over the upper surface of each source-drain terminal TSD with the solder SLDc set thereon (Step S5inFIG. 18).

FIG. 52is an overall plan view (top view) obtained when Step S5(semiconductor chip CPL setting step) has been carried out and shows the same area as inFIG. 25,FIG. 32,FIG. 39, andFIG. 43.FIG. 53is a substantial part plan view (partial enlarged plan view) obtained when Step S5(semiconductor chip CPL setting step) has been carried out and shows the same area as inFIG. 26,FIG. 33,FIG. 40, andFIG. 44.FIG. 54is a partial enlarged plan view of the area (that is, the drain terminal TDH and its surrounding area)45encircled with a broken line inFIG. 53.FIG. 54shows what is obtained by turning the area45inFIG. 5390° clockwise and in this drawing the assembly jig41is omitted. ThoughFIG. 55is a sectional view taken along line C6-C6ofFIG. 54, the openings OP1in the lead frame LF1are omitted in the sectional view inFIG. 55to facilitate visualization.

Solder paste may be used as the solder SLDc used at Step S5but use of solder pellets (solder foil) is more desirable. When solder pellets are used as the solder SLDc, it is easy to evenly control the amount of solder SLDc supplied to the upper surface of each source-drain terminal TSD. Therefore, it is possible to reduce variation in the thickness of the solder SLD joining each source-drain terminal TSD and each semiconductor chip CPL. When solder pellets are used as the solder SLDc, it is desirable to take the following procedure: flux (flux material) is applied to the upper surface of each source-drain terminal TSD of the lead frame LF2and then solder pellets are set; and flux (flux material) is further applied to the solder pellets and each semiconductor chip CPL is placed thereover.

As the result of Step S5, each semiconductor chip CPL is set (placed) over the upper surface of each source-drain terminal TSD of the lead frame LF2with the solder SLDc in between. At Step S5, each semiconductor chip CPL is placed so that its back surface drain electrode BEL is opposed to the upper surface of each source-drain terminal TSD of the lead frame LF2. The upper surface of each source-drain terminal TSD of the lead frame LF2is its main surface on the opposite side to the side where it is opposed to each semiconductor chip CPH. When the solder SLDc is solder paste, the semiconductor chip CPL is temporarily fixed by the adhesion (adhesiveness) of the solder paste. When the solder SLDc is solder pellets, it is temporarily fixed by the adhesion (adhesiveness) of flux.

As seen fromFIG. 41,FIG. 42,FIG. 50,FIG. 51,FIG. 54,FIG. 55as well, each source-drain terminal and each semiconductor chip CPL are set as follows: each source-drain terminal TSD of the lead frame LF2is so set that it does not planarly overlap with the gate pad electrode PDGH of each semiconductor chip CPH; and each semiconductor chip CPL is set over each source-drain terminal TSD of the lead frame LF2. For this reason, each semiconductor chip CPL is set in a position displaced from each semiconductor chip CPH as viewed in a plane. Consequently, the back surface drain electrode BEL of each semiconductor chip CPL is not in contact with each gate terminal TGH of the lead frame LF2.

In this embodiment, the following procedure is taken before each semiconductor chip CPL is placed over each source-drain terminal TSD of the lead frame LF2: solder (solder material, solder layer) SLDd is supplied (formed) over the source pad electrode PDSL and gate pad electrode PDGL in the front surface of each semiconductor chip CPL. Specifically, the following procedure is taken: flux (flux material) is applied to the source pad electrode PDSL and gate pad electrode PDGL of each semiconductor chip CPL before it is placed over each source-drain terminal TSD of the lead frame LF2and solder pellets are set; flux is further applied to these solder pellets and using a heat block (not shown) or the like, each semiconductor chip CPL is heated to melt and solidify the flux and the solder pellets. As a result, a solder layer (solder SLDd in this example) is formed over the source pad electrode PDSL and gate pad electrode PDGL of each semiconductor chip CPL. Then each semiconductor chip CPL in this state is placed over the upper surface of each source-drain terminal TSD of the lead frame LF2. As mentioned above, solder pellets are used to form a solder layer (solder SLDd in this example) over the source pad electrode PDSL and gate pad electrode PDGL of each semiconductor chip CPL. Thereafter, this semiconductor chip CPL is placed over each source-drain terminal TSD of the lead frame LF2. This makes it easier to evenly control the amount of solder SLDd over the source pad electrode PDSL and gate pad electrode PDGL of each semiconductor chip CPL. For this reason, it is possible to reduce variation in the thickness of the solder SLD joining together the source pad electrode PDSL and gate pad electrode PDGL of each semiconductor chip CPL and each source terminal TSL and gate terminal TGL.

As another embodiment, the following procedure may be taken without previously supplying solder SLDd to the source pad electrode PDSL or gate pad electrode PDGL in the front surface of each semiconductor chip CPL: this semiconductor chip CPL is placed over each source-drain terminal TSD of the lead frame LF2; and then solder SLDd is supplied (set) over the source pad electrode PDSL and gate pad electrode PDGL in the front surface of each semiconductor chip CPL. In this case, for example, solder pastes or the like can be used as the solder SLDd.

FIG. 56is an overall plan view (top view) obtained when Step S6(lead frame LF3setting step) has been carried out and shows the same area as inFIG. 25,FIG. 32,FIG. 39, andFIG. 43.FIG. 57is a substantial part plan view (partial enlarged plan view) obtained when Step S6(lead frame LF3setting step) has been carried out and shows the same area as inFIG. 26,FIG. 33,FIG. 40, andFIG. 44.FIG. 58is a sectional view taken along line C1-C1ofFIG. 57;FIG. 59is a sectional view taken along line C2-C2ofFIG. 57;FIG. 60is a sectional view taken along line C3-C3ofFIG. 57;FIG. 61is a sectional view taken along line C4-C4ofFIG. 57;FIG. 62is a sectional view taken along line C5-C5ofFIG. 57;FIG. 63is a sectional view taken along line C7-C7ofFIG. 57; andFIG. 64is a sectional view taken along line C8-C8ofFIG. 57.FIG. 65is a partial enlarged plan view of the area (that is, the drain terminal TDH and its surrounding area)45encircled with a broken line inFIG. 57.FIG. 65shows what is obtained by turning the area45inFIG. 5790° clockwise and in this drawing the assembly jig41is omitted. ThoughFIG. 66is a sectional view taken along line C6-C6ofFIG. 65, the openings OP1in the lead frame LF1are omitted in the sectional view inFIG. 66to facilitate visualization. ThoughFIG. 57is a plan view, the supporting faces SF1b, SF1cand the pins42in the upper surface of the assembly jig41and the lead frame LF3are hatched to facilitate visualization (to make the layout of each element easily understandable).

At Step S6, the lead frame LF3is set over the upper surface of the assembly jig41so that the following is implemented: the pins42of the assembly jig41are inserted into the positioning openings (holes, through holes) OP2provided in the lead frame LF3. The relative positional relation (planar positional relation) between the assembly jig41, lead frame LF1, lead frame LF2, and lead frame LF3is defined (determined) by the following: the pin42of the assembly jig41, the openings OP2in the lead frame LF1, the openings OP2in the lead frame LF2, and the openings OP2in the lead frame LF3.

Thus the lead frame LF3is set over the lead frames LF1, LF2and the semiconductor chips CPH, CPL so that the following is implemented: each source terminal TSL of the lead frame LF3is set over the source pad electrode PDSL of each semiconductor chip CPL; and each gate terminal TGL of the lead frame LF3is set over the gate pad electrode PDGL of each semiconductor chip CPL. That is, each source terminal TSL of the lead frame LF3is set over the source pad electrode PDSL of each semiconductor chip CPL with solder SLDd in between; at the same time, each gate terminal TGL of the lead frame LF3is set over the gate pad electrode PDGL of each semiconductor chip CPL with solder SLDd in between.

It is more desirable to take the following procedure prior to the step, or Step S6, for setting the lead frame LF3over the assembly jig41: flux (flux material) is applied to the lower surface of each source terminal TSL and gate terminal TGL of the lead frame LF3. (That is, flux is applied to their surfaces on the side where they are opposed to the source pad electrode PDSL and gate pad electrode PDGL of each semiconductor chip CPL). Thereafter, the lead frame LF3setting step, or Step S6is carried out.

Subsequently, solder reflow processing (heat treatment, solder reflow heat treatment) is carried out (Step S7inFIG. 18).FIG. 67is a substantial part sectional view obtained when Step S7(solder reflow processing) has been carried out and shows the same sectioned area (that is, the section taken along line C6-C6) inFIG. 66.

The solder reflow processing of Step S7is carried out without removing the lead frame LF1, LF2, or LF3from the assembly jig41in a state in which: the lead frames LF1, LF2, LF3are set over the assembly jig41as illustrated inFIG. 56toFIG. 66; and the semiconductor chips CPH, CPL are sandwiched between the lead frames LF1, LF2, LF3. That is, the solder reflow processing of Step S7can be carried out by taking the following procedure to carry out heat treatment: the lead frames LF1, LF2, LF3set over the assembly jig41and the semiconductor chips CPH, CPL sandwiched therebetween are passed through a reflow furnace together with the assembly jig (along with the assembly jig41). As the result of the solder reflow processing of Step S9, the solder SLDa, SLDb, SLDc, SLDd is melt and solidified (re-solidified) and turned into the solder SLD.

The result illustrated inFIG. 67is obtained by carrying out this solder reflow processing of Step S7, that is, solder reflow heat treatment. That is, the back surface drain electrode BEH of each semiconductor chip CPH and each drain terminal TDH of the lead frame LF1are joined and electrically coupled together through solder SLD (obtained by melting and solidifying solder SLDa). The source pad electrode PDSH of each semiconductor chip CPH and each source-drain terminal TSD of the lead frame LF2are joined and electrically coupled together through solder SLD (obtained by melting and solidifying solder SLDb). The gate pad electrode PDGH of each semiconductor chip CPH and each gate terminal TGH of the lead frame LF2are joined and electrically coupled together through solder SLD (obtained by melting and solidifying solder SLDb). The back surface drain electrode BEL of each semiconductor chip CPL and each source-drain terminal TSD of the lead frame LF2are joined and electrically coupled together through solder SLD (obtained by melting and solidifying solder SLDc). The source pad electrode PDSL of each semiconductor chip CPL and each source terminal TSL of the lead frame LF3are joined and electrically coupled together through solder SLD (obtained by melting and solidifying solder SLDd). The gate pad electrode PDGL of each semiconductor chip CPL and each gate terminal TGL of the lead frame LF3are joined and electrically coupled together through solder SLD (obtained by melting and solidifying solder SLDd). As a result, an assembly (work) WK comprised of the lead frames LF1, LF2, LF3and the semiconductor chips CPH, CPL soldered therebetween is obtained. The plan views obtained when the solder reflow processing of Step S7has been carried out to form the solder SLD (the same process step as inFIG. 67) are the same asFIG. 56,FIG. 57, andFIG. 65and the drawings are omitted here.

After the solder reflow processing of Step S7, the assembly WK can be removed from the assembly jig41as illustrated inFIG. 68.FIG. 68is a substantial part sectional view obtained when the assembly WK is removed from the assembly jig41after the solder reflow processing of Step S7. It shows the same sectioned area (that is, the section taken along line C6-C6) as inFIG. 66andFIG. 67. After the solder reflow processing of Step S7, the lead frames LF1, LF2, LF3and the semiconductor chips CPH, CPL are fixed with solder SLD in the assembly WK. Even though the assembly WK is removed from the assembly jig41, therefore, the relative positional relation can be prevented from being broken between the lead frame LF1, lead frame LF2, lead frame LF3, semiconductor chip CPH, and semiconductor chip CPL.

Subsequently, a molding step (resin sealing step, for example, transfer molding step) is carried out to form the encapsulation resin portion MR as illustrated inFIG. 69toFIG. 72. The semiconductor chips CPH, CPL are thereby sealed with the encapsulation resin portion MR (Step S8inFIG. 18).

FIG. 69is an overall plan view (top view) obtained when Step S8(encapsulation resin portion MR formation step) has been carried out and shows the same area as inFIG. 25,FIG. 32,FIG. 39,FIG. 43,FIG. 52, andFIG. 56.FIG. 70is a substantial part plan view (partial enlarged plan view) obtained when Step S8(encapsulation resin portion MR formation step) has been carried out and shows the same area as inFIG. 26,FIG. 33,FIG. 40,FIG. 44,FIG. 53, andFIG. 57.FIG. 71is a substantial part plan view (partial enlarged plan view) obtained when Step S8(encapsulation resin portion MR formation step) has been carried out and shows the same area (equivalent to the area45) as inFIG. 41,FIG. 50,FIG. 54, andFIG. 65. ThoughFIG. 72is a sectional view taken along line C6-C6ofFIG. 71, the openings OP1in the lead frame LF1are omitted in the sectional view inFIG. 72to facilitate visualization.

Description will be given to this molding step, or Step S8with reference toFIG. 73toFIG. 93.

The molding step, or Step S8is carried out using molding dies MD1, MD2. Of these molding dies, the die MD1is an upper die and the die MD2is a lower die.FIG. 73is an overall plan view (top view) of the die (lower die) MD2;FIG. 74is a substantial part plan view (partial enlarged plan view) of the die MD2; andFIG. 75toFIG. 79are substantial part sectional views of the die MD2. The substantial part plan view (partial enlarged plan view) inFIG. 74is an enlarged view of an area (corresponding to a unit region RG2a) encircled with a broken line inFIG. 73. The section taken along line D1-D1ofFIG. 74substantially corresponds toFIG. 75; the section taken along line D2-D2ofFIG. 74substantially corresponds toFIG. 76; the section taken along line D3-D3ofFIG. 74substantially corresponds toFIG. 77; the section taken along line D4-D4ofFIG. 74substantially corresponds toFIG. 78; and the section taken along line D5-D5ofFIG. 74substantially corresponds toFIG. 79. ThoughFIG. 74is a plan view, the supporting faces SF2b, SF2cand pins52in the upper surface of the die MD2are hatched with oblique lines to facilitate visualization (to make the layout of each element easily understandable). The area where a cavity CAV is formed (that is, the area to be the bottom surface of the cavity CAV) is hatched with dots for the same purpose as mentioned above. The position of line D1-D1corresponds to the position of line C1-C1; the position of line D2-D2corresponds to the position of line C2-C2; the position of line D3-D3corresponds to the position of line C3-C3; the position of line D4-D4corresponds to the position of line C4-C4; and the position of line D5-D5corresponds to the position of line C5-C5.

The die MD1illustrated inFIG. 86toFIG. 93and the die MD2illustrated inFIG. 73toFIG. 93are formed of a material having durability (heat resistance) against the molding step, or Step S8, with the processing temperature of approximately 180° C. For example, what is obtained by plating quenched and tempered steel with hard chromium or the like is desirable as the material. The material composing the dies MD1, MD2is different from the material (carbon material or SUS material) composing the assembly jig41. The assembly jig41is used in the solder reflow processing with the processing temperature of approximately 300 to 400° C., which is higher than the processing temperature of approximately 180° C. for the molding step. Deformation in the assembly jig41caused by heat leads to degradation in the accuracy of assembly (combination) of the lead frames LF1, LF2, LF3and the semiconductor chips CPH, CPL sandwiched therebetween. For this reason, if the same material (obtained by plating quenched and tempered steel with hard chromium or the like) as that of the dies MD1MD2is used for the assembly jig41, thermal deformation is caused by heat from solder reflow. To prevent this, a material (carbon material or SUS material) whose heat resistance is higher than that of the material composing the dies MD1, MD2is used for the assembly jig41. The die MD2is so configured that the assembly WK can be set over its upper surface (main surface on the side shown inFIG. 73andFIG. 74).

The die MD2is so configured that multiple unit regions (hereafter, referred to as unit regions RG2), in each of which each unit region UT1of the assembly WK is set, are arranged (repeated). How the unit regions RG2are arranged in the die MD2is identical with how the unit regions UT1are arranged in each lead frame LF1, LF2, LF3. More specific description will be given. When multiple unit regions UT1are arranged in the Y-direction in each lead frame LF1, LF2, LF3as illustrated inFIG. 19,FIG. 21, andFIG. 23, multiple unit regions RG2are arranged in the Y-direction in the die MD2as illustrated inFIG. 73. The number of arranged unit regions UT1in each lead frame LF1, LF2, LF3and the number of arranged unit regions RG2in the die MD2are identical with each other. However, the number is not limited to six (in the cases inFIG. 19,FIG. 21,FIG. 23, andFIG. 73).FIG. 73shows an overall plan view (top view) of the die MD2and multiple unit regions RG2are repeated in the Y-direction in the die MD2inFIG. 73.FIG. 74is an enlarged view of a unit region RG2aas one of these repeated regions. (That is,FIG. 74is an enlarged view of the area encircled with a broken line inFIG. 73.)

The die MD2illustrated inFIG. 73toFIG. 79is so configured that the assembly WK (lead frames LF1, LF2, LF3) can be set over its upper surface. For this purpose, the die MD2has the following faces in its upper surface: a supporting face (first face) SF2afor setting (supporting) the lead frame LF1in the assembly WK; supporting faces (second faces) SF2bfor setting (supporting) the lead frame LF2, protruded to above the supporting face SF2a; and supporting faces (third faces) SF2cfor setting (supporting) the lead frame LF3, protruded to above the supporting faces SF2a, SF2b. That is, in the upper surface of the die MD2, the supporting faces SF2bare higher than the supporting face SF2aand the supporting faces SF2care higher than the supporting faces SF2b. This can be achieved by: providing the upper surface of the die MD2with two different kinds of salient (two-level) steps (mount portions, salient portions, protruded portions)53,54different in height; taking the upper surfaces of the lower (lower-level) steps53as the supporting faces SF2b; and taking the upper surfaces of the higher (higher-level) steps as the supporting faces SF2c. In the die MD2, the supporting faces SF2bare identical in height. In the die MD2, the supporting faces SF2care identical in height. In the upper surface of the die MD2, positioning pins (pin portions, salient portions, projections)52for planarly positioning the assembly WK may be provided in the following positions: positions where the openings OP2in the lead frames LF1, LF2, LF3are positioned when the assembly WK is set. The pins52of the die MD2need not be formed as long as there is no problem in the positioning of the assembly WK without the pins52.

In this embodiment, the following heights (amounts of protrusion) are identical with each other: the height (amount of protrusion) H3of the supporting faces SF2brelative to the supporting face SF2ain the die MD2; and the height (amount of protrusion) H1of the supporting faces SF1brelative to the supporting face SF1ain the assembly jig41(H3=H1). Further, the following heights (amounts of protrusion) are identical with each other: the height (amount of protrusion) H4of the supporting faces SF2crelative to the supporting face SF2ain the die MD2; and the height (amount of protrusion) H2of the supporting faces SF1brelative to the supporting face SF1ain the assembly41(H4=H2).

At the molding step, or Step S8, the assembly WK is set over the die MD2as illustrated inFIG. 80toFIG. 85.

FIG. 80is a substantial part plan view (partial enlarged plan view) of the assembly WK as is set over the die MD2and shows the same area as inFIG. 70andFIG. 74.FIG. 81is a sectional view taken along line D1-D1ofFIG. 80;FIG. 82is a sectional view taken along line D2-D2ofFIG. 80;FIG. 83is a sectional view taken along line D3-D3ofFIG. 80;FIG. 84is a sectional view taken along line D4-D4ofFIG. 80; andFIG. 85is a sectional view taken along line D5-D5ofFIG. 80. ThoughFIG. 80is a plan view, the supporting faces SF2b, SF2cand pins52in the upper surface of the die MD2are hatched to facilitate visualization (to make the layout of each element easily understandable).

When the assembly WK is set over the die MD2, the assembly WK is set over the die MD2so that the following is implemented: the lead frame LF1in the assembly WK comes to the die MD2side (that is, the lower side) and the lead frame LF3in the assembly WK comes to the die MD1side (that is, the upper side). As seen fromFIG. 80andFIG. 85as well, at this time, the assembly WK can be set over the upper surface of the die MD2so that the following is implemented: the positioning pins52provided in the upper surface of the die MD2are inserted into the positioning openings OP2provided in the lead frames LF1, LF2, LF3in the assembly WK.

In the upper surface of the die MD2, the area that planarly overlaps with the lead frame LF1when the assembly WK is set at the molding step, or Step S8is taken as the supporting face SF2a. The planar shapes of the lead frames LF1, LF2, LF3and the plane configuration of the supporting faces SF2a, SF2b, SF2cof the die MD2are so designed that the following is implemented: the supporting faces SF2b, SF2bare set in areas where they do not planarly overlap with the lead frame LF1; and the supporting faces SF2care set in areas where they do not planarly overlap with the lead frame LF1or LF2. At the molding step, or Step S8, for this reason, the assembly WK including the lead frames LF1, LF2, LF3can be set over the die MD2without interference of the supporting faces SF2bor SF2c.

The lead frame LF1in the assembly WK set over the die MD2is set over the supporting face SF2aso that the lower surface of the lead frame LF1is in contact with the supporting face SF2a. Thus the lead frame LF1is supported by the supporting face SF2a. As mentioned above, the lower surface (especially, the lower surface of each drain terminal TDH) of the lead frame LF1in the assembly WK is set in contact with the supporting face SF2aof the die MD2. As a result, the height position of the lower surface of the lead frame LF1is controlled and made equal to that of the supporting face SF2aof the die MD2.

After the assembly WK is set over the die MD2, the die MD1is moved (down) toward the die MD2to sandwich and clamp (fix) the assembly WK between the dies MD1, MD2from above and below.

FIG. 86toFIG. 90are substantial part sectional views illustrating the assembly WK as is sandwiched and fixed (clamped) between the molding dies MD1, MD2at the molding step, or Step S8.FIG. 86shows the section in a position corresponding to line D1-D1ofFIG. 74andFIG. 80(that is, the section corresponding toFIG. 75andFIG. 81).FIG. 87shows the section in a position corresponding to line D2-D2ofFIG. 74andFIG. 80(that is, the section corresponding toFIG. 76andFIG. 82).FIG. 88shows the section in a position corresponding to line D3-D3ofFIG. 74andFIG. 80(that is, the section corresponding toFIG. 77andFIG. 83).FIG. 89shows the section in a position corresponding to line D4-D4ofFIG. 74andFIG. 80(that is, the section corresponding toFIG. 78andFIG. 84).FIG. 90shows the section in a position corresponding to line D5-D5ofFIG. 74andFIG. 80(that is, the section corresponding toFIG. 79andFIG. 85).

When the dies MD1, MD2are clamped, the assembly WK is fixed between the dies MD1, MD2. As a result, each semiconductor chip CPH, CPL sandwiched between the lead frames LF1, LF2, LF3is set in each cavity CAV formed by (the lower surface of) the die MD1and (the upper surface of) the die MD2. That is, the lead frames LF1, LF2, LF3are sandwiched and clamped (fixed) between the dies MD1, MD2so that each semiconductor chip CPH, CPL is set in each cavity CAV formed by the lower surface of the die MD1and the upper surface of the die MD2.

After the assembly WK is fixed and clamped between the dies MD1, MD2as illustrated inFIG. 86toFIG. 90, the following processing is carried out as illustrated inFIG. 91toFIG. 93: encapsulation resin material as the material for the formation of the encapsulation resin portion MR is injected (introduced, filled) in each cavity CAV in the dies MD1, MD2. Then the injected encapsulation resin material is cured to form the encapsulation resin portion MR.

FIG. 91toFIG. 93are substantial part sectional views illustrating the encapsulation resin portion MR formed by injecting the encapsulation resin material into each cavity CAV in the dies MD1, MD2at the molding step, or Step S8.FIG. 91shows the same sectioned area (that is, the section taken along line D2-D2) as inFIG. 87;FIG. 92shows the same sectioned area (that is, the section taken along line D4-D4) as inFIG. 89; andFIG. 93shows the same sectioned area (that is, the section taken along line D5-D5) as inFIG. 90.

The encapsulation resin material for the formation of the encapsulation resin portion MR is composed of resin material or the like, for example, thermosetting resin material or the like and may contain filler or the like. For example, epoxy resin or the like containing filler can be used. When the encapsulation resin material is composed of thermosetting resin material, the encapsulation resin material can be heated and cured (turned into the cured encapsulation resin portion MR) by taking the following procedure: after the injection of the encapsulation resin material into each cavity CAV formed by the dies MD1, MD2, the dies MD1, MD2are heated up to a predetermined temperature. It is desirable to design this encapsulation resin material so that its temperature during curing is less than the melting point of the above solder SLD. This makes it possible to prevent the solder SLD from being melted while the encapsulation resin material is cured. Thus the encapsulation resin portion MR is formed.

Subsequently, the assembly WK (that is, assembly WKa) with the encapsulation resin portion MR formed thereon is released from the dies MD1, MD2and any flash and the like are removed from the encapsulation resin portion MR (Step S9inFIG. 18). Thus the assembly (work) WKa illustrated inFIG. 69toFIG. 72is obtained. The assembly WKa is obtained by forming the encapsulation resin portion MR on the assembly WK.

At the molding step, or Step S8, the encapsulation resin portion MR is formed with the lower surface of each drain terminal TDH of the lead frame LF1in contact with the supporting face SF1aof the die MD2. Therefore, a gap is hardly produced between the lower surface of each drain terminal TDH of the lead frame LF1and the upper surface of the die MD2. As a result, the encapsulation resin portion MR is hardly formed on the lower surface of each drain terminal TDH. For this reason, the following state is established in the assembly WKa: the lower surface (corresponding to the lower surface TDHa) of each drain terminal TDH of the lead frame LF1is exposed from the back surface (corresponding to the main surface MRb) of the encapsulation resin portion MR. Even though any resin flash of the encapsulation resin portion MR is formed on the lower surface of each drain terminal TDH, it can be removed by the def lashing step subsequent to the molding step, or Step S8.

Subsequently, plating is carried out as required to form a plating layer (not shown) over the portions of the lead frames LF1, LF2, LF3exposed from the encapsulation resin portion MR in the assembly WKa (Step S10inFIG. 18). Solder plating can be carried out using, for example, lead-free solder.

Subsequently, the lead frames LF1, LF2, LF3are cut in predetermined positions (Step S11inFIG. 18). That is, the tie bars TB1in the lead frame LF2are cut to separate each gate terminal TGH and each source-drain terminal TSD; and the tie bars TB2in the lead frame LF3are cut to separate each gate terminal TGL and each source terminal TSL. Thereafter, each drain terminal TDH, source-drain terminal TSD, gate terminal TGH, source terminal TSL, and gate terminal TGL are cut off (separated) from (the frameworks LF1a, LF2a, LF3aof) the lead frames LF1, LF2, LF3.

FIG. 94is a substantial part plan view obtained when Step S10(lead frames LF1, LF2, LF3cutting step) has been carried out and shows the area corresponding toFIG. 71.FIG. 94illustrates the drain terminal TDH, source-drain terminal TSD, gate terminal TGH, source terminal TSL, and gate terminal TGL separated from the lead frames LF1, LF2, LF3. When the lead frames LF1, LF2, LF3are cut at Step S10, each drain terminal TDH, source-drain terminal TSD, gate terminal TGH, source terminal TSL, and gate terminal TGL are flat. In addition, the respective outer lead portions of the source-drain terminal TSD, gate terminal TGH, source terminal TSL, and gate terminal TGL are laterally protruded from lateral surfaces of the encapsulation resin portion MR.

Subsequently, the following outer lead portions and terminal protruded outward (laterally) from (lateral surfaces of the encapsulation resin portion MR) are bent (Step S12inFIG. 18): the outer lead portions of the source-drain terminal TSD; the outer lead portion of the gate terminal TGH; the outer lead portions of the source terminal TSL; and the gate terminal TGL. Thus the semiconductor device SM1in this embodiment illustrated inFIG. 3toFIG. 16is manufactured.

FIG. 95andFIG. 96are substantial part sectional views of the semiconductor device SM1in this embodiment as is mounted over a mounting board (wiring board) PCB.FIG. 95shows the section corresponding toFIG. 9andFIG. 96shows the section corresponding toFIG. 12.

As illustrated inFIG. 95andFIG. 96, each semiconductor device SM1is mounted over the mounting board (wiring board) PCB. The step for mounting the semiconductor device SM1over the mounting board PCB can be carried out, for example, as described below. Solder paste (to be the solder SLD2later) is supplied onto terminals TE1, TE2, TE3, TE4, TE5of the mounting board PCB by print processes or the like and then the semiconductor device SM1is set over the mounting board PCB. At this time, the semiconductor device SM1is set so that the following is implemented: (the lower surface TDHa of) the drain terminal TDH of the semiconductor device SM1is opposed to the terminal TE1of the mounting board PCB; and (the lower surfaces of) the respective outer lead portions of the gate terminal TGH, source-drain terminal TSD, gate terminal TGL, and source terminal TSL are respectively opposed to the terminals TE2to TE5of the mounting board PCB. Thereafter, solder reflow processing (heat treatment) is carried out. As a result, (the lower surface TDHa of) the drain terminal TDH exposed in the main surface MRb of the encapsulation resin portion MR is joined and electrically coupled with the terminal TE1of the mounting board PCB through solder SLD2. (The lower surface TGHb of) the outer lead portion of the gate terminal TGH is joined and electrically coupled with the terminal TE2of the mounting board PCB through solder SLD2. (The lower surfaces TSDb of) the outer lead portions of the source-drain terminal TSD are joined and electrically coupled with the terminals TE3of the mounting board PCB through solder SLD2. (The lower surface TGLb of) the outer lead portion of the gate terminal TGL is joined and electrically coupled with the terminal TE4of the mounting board PCB through solder SLD2. (The lower surfaces TSLb of) the outer lead portions of the source terminal TSL are joined and electrically coupled with the terminals TE5of the mounting board PCB through solder SLD2. The back surface side of the semiconductor device SM1(that is, the main surface MRb side of the encapsulation resin portion MR) becomes the mounting surface to the mounting board PCB.

More detailed description will be given to the molding step, or Step S8(that is, the encapsulation resin portion MR formation step).

In the semiconductor device SM1in this embodiment, the lower surface TDHa of the drain terminal TDH is exposed from the encapsulation resin portion MR. To achieve this, the following measure is taken when the assembly WK is clamped between the dies MD1, MD2as illustrated inFIG. 86toFIG. 90at the molding step, or Step S8: the lower surface of each drain terminal TDH of the lead frame LF1is brought into contact with (the supporting faces SF2ain) the upper surface of the die MD2(that is, the main surface of the drain terminal on the opposite side to the side where the semiconductor chip CPH is set is brought into contact with the upper surface of the die MD2); and in this state, the resin material is introduced in each cavity CAV to form the encapsulation resin portion MR.

At the molding step, or Step S8, the following measure is taken with respect to the lead frame LF1in the assembly WK: each drain terminal TDH that should be positioned inside encapsulation resin portion MR is set in each cavity CAV (so that the lower surface of the drain terminal TDH is in contact with the upper surface of the die MD2); and its portion that should be positioned outside the encapsulation resin portion MR is positioned outside each cavity CAV and sandwiched between (the lower surface of) the die MD1and (the supporting face SF2aof) the die MD2. The following measure is taken with respect to each source-drain terminal TSD and gate terminal TGH of the lead frame LF2in the assembly WK1: their portions (inner lead portions) that should be positioned inside the encapsulation resin portion MR are set in each cavity CAV (so that they are not in contact with the die MD1or MD2); and their portions (outer lead portions) that should be positioned outside the encapsulation resin portion MR are sandwiched between (the lower surface of) the die MD1and (the supporting faces SF2bof) the die MD2. The following measure is taken with respect to each source terminal TSL and gate terminal TGL of the lead frame LF3in the assembly WK: their portions that should be positioned inside the encapsulation resin portion MR (portions opposed to each semiconductor chip CPL, inner lead portions) are set in each cavity CAV (so that they are not in contact with the die MD1or MD2); and their portions (outer lead portions) that should be positioned outside the encapsulation resin portion MR are sandwiched between (the lower surface of) the die MD1and (the supporting faces SF2cof) the die MD2. This makes it possible to obtain a structure in which the following is implemented: each semiconductor chip CPH, CPL is sealed with the encapsulation resin portion MR; part of each drain terminal TDH, source-drain terminal TSD, gate terminals TGH, TGL, and source terminal TSL is sealed with the encapsulation resin portion MR and the other part thereof is exposed from the encapsulation resin portion MR.

In the assembly WK, the following portions do not planarly overlap with one another and they do not planarly overlap with the lead frame LF1, either: the outer lead portions of each source-drain terminal TSD, the outer lead portion of each gate terminal TGH, the outer lead portion of each gate terminal TGL, and the outer lead portions of each source terminal TSL. For this reason, the following procedure can be taken in positions adjacent to each cavity CAV when the assembly WK is clamped between the dies MD1, MD2: the outer lead portions of the source-drain terminal TSD and the outer lead portion of the gate terminal TGH are set over the supporting faces SF2bof the die MD2; at the same time, the outer lead portion of the gate terminal TGL and the outer lead portions of the source terminal TSL are set over the supporting faces SF2cof the die MD2. Then these outer lead portions can be sandwiched and clamped between the lower surface of the die MD1and the supporting faces SF2b, SF2cof the die MD2from above and below.

The assembly WK includes multiple (three in this example) lead frames LF1, LF2, LF3and each drain terminal TDH, source-drain terminal TSD, gate terminals TGH, TGL, and source terminal TSL in the lead frames LF1, LF2, LF3are flat. At the molding step, or Step S8, it is required to sandwich and clamp (fix) these (three in this example) lead frames LF1, LF2, LF3between the die MD1and the die MD2. However, the lead frames LF1, LF2, LF3are different from one another in height position.

When height or height position is cited with respect to the assembly WK, it refers to height or height position relative to the lower surface of each drain terminal TDH of the lead frame LF1and in the direction substantially perpendicular thereto. When height or height position is cited with respect to the die MD2, it refers to height or height position relative to the supporting face SF2aand in the direction substantially perpendicular thereto. When height or height position is cited with respect to the assembly jig41, it refers to height or height position relative to the supporting face SF1aand in the direction substantially perpendicular thereto.

For this reason, it is required to change the height position among the following portions in the dies MD1, MD2: their portions that sandwich the lead frame LF1(especially, each drain terminal TDH) from above and below; their portions that sandwich the lead frame LF2(especially, the outer lead portions of each source-drain terminal TSD and gate terminal TGH) from above and below; and their portions that sandwich the lead frame LF3(especially, the outer lead portions of each gate terminal TGL and source terminal TSL) from above and below.

Consequently, the following measure is taken in the upper surface of the die MD2as the lower die: its area that planarly overlaps with the lead frame LF1when the assembly WK is set over the die MD2is taken as the flat supporting face SF2ain advance; and at the molding step, or Step S8, the lead frame LF1is set over the supporting face SF2aof the die MD2.

When the assembly WK is clamped between the dies MD1, MD2, it is desirable that the entire lower surface of each drain terminal TDH of the lead frame LF1should be in contact with the supporting face SF2aof the die MD2. For this reason, in the supporting face SF2aof the die MD2, at least the areas where each drain terminal TDH is set (that is, the areas that planarly overlaps with each drain terminal TDH) must be flat. Therefore, it is desirable that the portions of the supporting face SF2aof the die MD2where the bottom surface of each cavity CAV is formed should be flat.

In the supporting face SF2aof the die MD2, meanwhile, the portions located outside each cavity CAV need not be wholly flat unless they interfere with the setting (flat setting) of the lead frame LF1. For example, a recess (depressed portion) may be partially provided in the portions of the supporting face SF2aof the die MD2located outside each cavity CAV. Further, the above pins52or the like may be provided in areas that do not planarly overlap with the lead frame LF1. Even in such a case, the lower surface of the lead frame LF1is brought into contact with the supporting face SF2aof the die MD1and the lead frame LF1can be set over the supporting face SF2aof the die MD2without inclination.

At the molding step, or Step S8, the lead frame LF1is sandwiched and clamped (fixed) between the lower surface of the die MD1and the supporting face SF2aof the die MD2from above and below in areas adjacent to each cavity CAV.

In the assembly WK, meanwhile, the lead frame LF2is located in a position higher than the lead frame LF1. In the upper surface of the die MD2as the lower die, for this reason, the following areas are taken as the flat supporting faces SF2blocated in a position higher than the supporting face SF2ain advance: the areas where the lead frame LF2is clamped (that is, the areas where the lead frame LF2is sandwiched between the dies MD1, MD2from above and below), especially, the areas where the outer lead portions of each source-drain terminal TSD and gate terminal TGH are set. At the molding step, or Step S8, for this reason, the assembly WK is set over the die MD2so that the lower surface of part of the lead frame LF2is in contact with the supporting faces SF2bof the die MD2. Thus the lead frame LF2is supported (held) by the supporting faces SF2bof the die MD2. As a result, the lower surface of the lead frame LF2becomes higher than the lower surface of the lead frame LF1by an amount equivalent to the difference in height between the supporting faces SF2band the supporting face SF2aof the die MD2. The supporting faces SF2bof the die MD2are provided to make the lead frame LF2higher than the lead frame LF1and clamp the lead frame LF2(especially, the outer lead portions of each source-drain terminal TSD and gate terminal TGH). At the molding step, or Step S8, for this reason, the following takes place in areas adjacent to each cavity CAV: the lead frame LF2(especially, the outer lead portions of each source-drain terminal TSD and gate terminal TGH) is sandwiched and clamped (fixed) between the lower surface of the die MD1and the supporting faces SF2bof the die MD2. Therefore, the supporting faces SF2bare provided in the upper surface of the die MD2in positions adjacent to each cavity CAV.

In the assembly WK, the lead frame LF3is located in a position higher than the lead frame LF2. In the upper surface of the die MD2as the lower die, for this reason, the following areas are taken as the flat supporting faces SF2clocated in a position higher than the supporting faces SF2a, SF2bin advance: the areas where the lead frame LF3is clamped (that is, the areas where the lead frame LF3is sandwiched between the dies MD1, MD2from above and below), especially, the areas where the outer lead portions of each gate terminal TGL and source terminal TSL are set. At the molding step, or Step S8, for this reason, the assembly WK is set over the die MD2so that the lower surface of part of the lead frame LF3is in contact with the supporting faces SF2cof the die MD2. Thus the lead frame LF3is supported (held) by the supporting faces SF2cof the die MD2. As a result, the lower surface of the lead frame LF3becomes higher than the lower surface of the lead frame LF2by an amount equivalent to the difference in height between the supporting faces SF2cand the supporting faces SF2bof the die MD2. The supporting faces SF2cof the die MD2are provided to make the lead frame LF3higher than the lead frames LF1, LF2and clamp the lead frame LF3(especially, the outer lead portions of each gate terminal TGL and source terminal TSL). At the molding step, or Step S8, for this reason, the following takes place in areas adjacent to each cavity CAV: the lead frame LF3(especially, the outer lead portions of each gate terminal TGL and source terminal TSL) is sandwiched and clamped (fixed) between the lower surface of the die MD1and the supporting faces SF2cof the die MD2from above and below. Therefore, the supporting faces SF2care provided in the upper surface of the die MD2in positions adjacent to each cavity CAV.

In the upper surface of the die MD2, as mentioned above, the supporting faces SF2bare higher than the supporting face SF2aand the supporting faces SF2care higher than the supporting faces SF2b. This can be achieved by: providing the upper surface of the die MD2with two salient steps (steps different in height)53,54in positions adjacent to each cavity CAV; taking the upper surfaces of the lower (lower-level) steps53as the supporting faces SF2b; and taking the upper surfaces of the higher (higher-level) steps54as the supporting faces SF2c. In this case, part of the lateral surface of each cavity CAV is formed of the lateral surfaces (lateral surfaces adjacent to each cavity CAV) of the steps53,54. This makes it possible to set the supporting faces SF2b, SF2cin positions adjacent to each cavity CAV. As a result, it is possible to: set the outer lead portions of each source-drain terminal TSD and gate terminal TGH of the lead frame LF2over the supporting faces SF2b; set the outer lead portions of each gate terminal TGL and source terminal TSL of the lead frame LF3over the supporting faces SFc; and clamp these outer lead portions between the dies MD1, MD2.

The lower surface of the die MD1as the upper die is in a shape corresponding to the upper surface of the die MD2as the lower die. More specific description will be given. In the lower surface of the die MD1, the following takes place when the assembly WK is clamped between the dies MD1, MD2: its portions that clamp the lead frame LF2opposite to the supporting faces SF2bof the die MD2are located in positions higher than its portions that clamp the lead frame LF1opposite to the supporting face SF2aof the die MD2. In the lower surface of the die MD1, the following takes place: its portions that clamp the lead frame LF3opposite to the supporting faces SF2cof the die MD2are located in positions higher than its portions that clamp the lead frame LF2opposite to the supporting faces SF2bof the die MD2.

As mentioned above, the portions (SF1a) of the dies MD1, MD2that sandwich the lead frame LF1from above and below is positioned low; the portions (SF1b) of the dies MD1, MD2that sandwich the lead frame LF2from above and below is made higher; and the portions (SF1c) of the dies MD1, MD2that sandwich the lead frame LF3from above and below is made further higher. As a result, the encapsulation resin portion MR can be formed on the assembly WK so structured that the semiconductor chips CPH, CPL are sandwiched between the lead frames LF1, LF2, LF3.

More detailed description will be given to the assembly WK fabrication step.

As mentioned above, the assembly WK is fabricated by carrying out Steps S1to S7. At this time, the assembly jig41is used. The assembly jig41has: a function of supporting (holding) the lead frames LF1, LF2, LF3until the solder reflow processing of Step S7is carried out to finish the assembly WK fixed with solder SLD; and a function of fixing or determining the positional relation between the lead frames LF1, LF2, LF3as well.

More specific description will be given. The planar positions of the lead frames LF1, LF2, LF3are defined by each opening OP2in the lead frames LF1, LF2, LF3and the pins42of the assembly jig41. Meanwhile, the vertical positions (height positions) of the lead frames LF1, LF2, LF3are defined by the supporting faces SF1a, SF1b, SF1cof the assembly jig41.

More specific description will be given. When the lead frame LF1is set over the assembly jig41at Step S2, the lead frame LF1is set over the supporting face SF1aand does not planarly overlap with the supporting faces SF1bor SF1c. The lower surface (especially, the lower surface of each drain terminal TDH) of the lead frame LF1is set in contact with the supporting face SF1aof the assembly jig41. As a result, the height position of the lower surface of the lead frame LF1(especially, each drain terminal TDH) is defined and it is made equal to the height of the supporting face SF1aof the assembly jig41.

When the lead frame LF2is set over the assembly jig41at Step S4, the following takes place: part (especially, the outer lead portions of each source-drain terminal TSD and gate terminal TGH) of the lead frame LF2is positioned over the supporting faces SF1band brought into contact with the supporting faces SF1b. As a result, the lead frame LF2is supported by the supporting faces SF1b. For this reason, the height position of the lower surface of the lead frame LF2(especially, the outer lead portions of each source-drain terminal TSD and gate terminal TGH) is defined; and it is made equal to the height of the supporting faces SF1bof the assembly jig41.

When the lead frame LF3is set over the assembly jig41at Step S6, the following takes place: part (especially, the outer lead portions of each gate terminal TGL and source terminal TSL) of the lead frame LF3is positioned over the supporting faces SF1cand brought into contact with the supporting faces SF1c. As a result, the lead frame LF3is supported by the supporting faces SF1c. For this reason, the height position of the lower surface of the lead frame LF3(especially, the outer lead portions of each gate terminal TGL and source terminal TSL) is defined; and it is made equal to the height of the supporting faces SF1cof the assembly jig41.

The solder reflow step, or Step S7is carried out with the lead frames LF1, LF2, LF3set over the assembly jig41and their planar positions and vertical height positions defined as mentioned above. That is, the solder reflow step, or Step S7is carried out with the lead frames LF1, LF2, LF3remaining set over the assembly jig41. For this reason, in the assembly WK formed by the solder reflow processing of Step S7, the following takes place: the lead frames LF1, LF2, LF3are set over the assembly jig41and their planar positions and vertical height positions are defined; and in this state, the solder SLDa, SLDb, SLDc, SLDd is melted and solidified and the solidified solder SLD is formed. Therefore, the relative position between the lead frames LF1, LF2, LF3is maintained before the solder reflow processing of Step S7, during heat treatment in the solder reflow processing of Step S7, and after the solder reflow processing of Step S7.

Especially, even when the solder SLDa, SLDb, SLDc, SLDd is melted at the solder reflow step, or Step S7, the following is implemented: the lower surface of part (especially, the outer lead portions of each source-drain terminal TSD and gate terminal TGH) of the lead frame LF2is supported by the supporting faces SF1bin contact therewith; and the lower surface of part (especially, the outer lead portions of each gate terminal TGL and source terminal TSL) of the lead frame LF3is supported by the supporting faces SF1cin contact therewith. Even when the solder SLDa, SLDb, SLDc, SLDd is melted, the lower surface of the lead frame LF1(especially, each drain terminal TDH) is supported by the supporting face SF1ain contact therewith. For this reason, the following is implemented when the solder SLDa, SLDb, SLDc, SLDd is solidified and turned into the solder SLD: the height position of the lower surface of the lead frame LF2(especially, the outer lead portions of each source-drain terminal TSD and gate terminal TGH) becomes equal to that of each supporting face SF1b; and the height position of the lower surface of the lead frame LF3(especially, the outer lead portions of each gate terminal TGL and source terminal TSL) becomes equal to that of each supporting face SF1c. The following is implemented when the solder SLDa, SLDb, SLDc, SLDd is solidified and turned into the solder SLD: the height position of the lower surface of the lead frame LF1(especially, each drain terminal TDH) becomes equal to that of the supporting face SF1a. Therefore, the height positions of the lead frames LF1, LF2, LF3in the assembly WK are kept at the height of the supporting faces SF1a, SF1b, SF1cin the assembly jig41.

That is, the following heights are identical with each other: the height H5from the lower surface of the lead frame LF1(especially, each drain terminal TDH) in the assembly WK to the lower surface of the lead frame LF2(especially, the outer lead portions of each source-drain terminal TSD and gate terminal TGH); and the height H1from the supporting face SF1ato the supporting faces SF1bin the assembly jig41(that is, H5=H1). (The height H5is indicated inFIG. 68.) Further, the following heights are identical with each other: the height H6from the lower surface of the lead frame LF1(especially, each drain terminal TDH) in the assembly WK to the lower surface of the lead frame LF3(especially, the outer lead portions of each gate terminal TGL and source terminal TSL); and the height H2from the supporting face SF1ato the supporting faces SF1cin the assembly jig41(that is, H6=H2). (The height H6is indicated inFIG. 68.)

Description will be given to problems that can be solved by in this embodiment.FIG. 97andFIG. 98are explanatory drawings explaining these problems.

FIG. 97is a sectional view with the semiconductor chip CPL and the lead frame LF3omitted, obtained by carrying out Steps S1to S4and then carrying out the solder reflow processing of Step S7without carrying out Step S5or S6to fabricate the assembly WK2. The assembly WK2illustrated inFIG. 97has the same configuration as the assembly WK except there is not the semiconductor chip CPL or the solder SLD on the upper surface side of the lead frame LF3or the lead frame LF2.FIG. 97is a schematic sectional view and depicts each lead frame LF1, LF2like a flat plate to facilitate understanding but in reality each lead frame LF1, LF2has such a structure as illustrated inFIG. 19toFIG. 22. InFIG. 97, the back surface drain electrode BEH, source pad electrode PDSH, and gate pad electrode PDGH of the semiconductor chip CPH are omitted to facilitate understanding.

To clamp the assembly WK2between the molding lower die and upper die to form the encapsulation resin portion MR, it is required to clamp the lead frame LF1and lead frame LF2in the assembly WK2at different height positions. The positions (height positions) where the lead frame LF1and the lead frame LF2are clamped between the lower die and the upper die are determined relative to the following design value: the design value of the spacing between the lead frame LF1and lead frame LF2in the assembly WK2. For this reason, in cases where the spacing T31between the lead frame LF1and lead frame LF2in the assembly WK2is in accordance with the design value when the assembly WK2is fabricated, the following results: no problem arises when the encapsulation resin portion MR is formed on the assembly WK2. In cases where this spacing T31is different from the design value, the following problems can arise when the assembly WK2is clamped between the molding lower die and upper die:

If the spacing T31between the lead frame LF1and lead frame LF2in the assembly WK2is excessively smaller than the design value, the following takes place when the assembly WK2is clamped between the molding lower die and upper die: force in the directions indicated by arrows61a, that is, force in such directions that the lead frames LF1, LF2are stripped from the semiconductor chip CPH is exerted on the lead frames LF1, LF2. This acts to weaken (degrade, disjoin) the following solder joint: the solder joint (joint by solder SLD) between the lead frame LF1and each semiconductor chip CPH; and the solder joint (joint by solder SLD) between the lead frame LF2and each semiconductor chip CPH. Therefore, there is a possibility that the reliability of the solder joint between the lead frames LF1, LF2and each semiconductor chip CPH is degraded and the reliability of each manufactured semiconductor device is degraded.

Conversely, if the spacing T31between the lead frame LF1and lead frame LF2in the assembly WK2is excessively larger than the design value, the following takes place when the assembly WK2is clamped between the molding lower die and upper die: a gap is produced between the dies and the lead frames. As a result, when resin material is injected into the cavity in the dies to form the encapsulation resin portion MR, the resin can flow into this gap and resin leakage can occur. This degrades the fabrication yield of the semiconductor device.

FIG. 98is a sectional view obtained when the assembly WK is fabricated by carrying out Steps S1to S7.FIG. 98is a schematic sectional view and depicts each lead frame LF1, LF2, LF3as a flat plate to facilitate understanding but in reality each lead frame LF1, LF2, LF3has such a structure as illustrated inFIG. 19toFIG. 24. InFIG. 98, the back surface drain electrodes BEH, BEL, source pad electrodes PDSH, PDSL, and gate pad electrodes PDGH, PDGL of the semiconductor chips CPH, CPL are omitted to facilitate understanding.

Also in case of the assembly WK with such a structure that the semiconductor chips CPH, CPL are sandwiched between the lead frames LF1, LF2, LF3, the same problems as described with respect to the assembly WK2can arise.

More specific description will be given. To clamp the assembly WK between the molding lower die and upper die to form the encapsulation resin portion MR, it is required to clamp the lead frame LF1, lead frame LF2, and lead frame LF3in the assembly WK at different height positions. The positions (height positions) where the lead frame LF1, lead frame LF2, and lead frame LF3are clamped between the lower die and the upper die are determined relative to the following design values: the design values of the spacing T31between the lead frames LF1, LF2in the assembly WK and the design value of the spacing T32between the lead frames LF2, LF3. For this reason, in cases where the spacing T31between the lead frames LF1, LF2in the assembly WK and the spacing T32between the lead frames LF2, LF3are in accordance with the design values when the assembly WK is fabricated, the following results: no problem arises when the encapsulation resin portion MR is formed on the assembly WK. In cases where the spacing T31or T32is different from its design value, the following problems can arise when the assembly WK is clamped between the molding lower die and upper die:

If the spacing T31between the lead frames LF1, LF2in the assembly WK or the spacing T32between the lead frames LF2, LF3is excessively smaller than the relevant design value, the following takes place when the assembly WK is clamped between the molding lower die and upper die: force in such directions that the lead frames LF1, LF2, LF3are stripped from the semiconductor chip CPH or the semiconductor chip CPL is exerted on the lead frames LF1, LF2, LF3. This can degrade the reliability of the solder joint (joint by solder SLD) between the lead frames LF1, LF2, LF3and the semiconductor chips CPH, CPL and the reliability of each manufactured semiconductor device can be degraded.

Conversely, if the spacing T31between the lead frames LF1, LF2in the assembly WK or the spacing T32between the lead frames LF2, LF3is excessively larger than the relevant design value, the following takes place: when the assembly WK is clamped between the molding lower die and upper die, a gap is produced between the dies and the lead frames. As a result, when resin material is injected into the cavity in the dies to form the encapsulation resin portion MR, the resin can flow into this gap and resin leakage can occur. This degrades the fabrication yield of the semiconductor device.

For this reason, to enhance the reliability of solder joint to enhance the reliability of the manufactured semiconductor device and prevent resin leakage during the molding step to enhance the fabrication yield of the semiconductor device, it is important to take the following measure: the spacing T31between the lead frames LF1, LF2and the spacing T32between the lead frames LF2, LF3are controlled to predetermined values in the assembly WK, WK2to prevent the above problems from arising during the molding step.

If the assembly jig41is not provided with the supporting faces SF1bor SF1cunlike this embodiment, the lead frames LF2, LF3are not supported by the supporting faces SF1bor SF1c. Therefore, when the solder SLDa, SLDb, SLDc, SLDd is melted at the solder reflow step, or Step S7, the lead frames LF2, LF3are sunk by their own weight and the solder is solidified and the solder SLD is formed in this state. In this case, the amount of sinking of each lead frame LF2, LF3fluctuates from assembly WK (WK2) to assembly WK (WK2). For this reason, the thickness of the solder SLD joining together (each electrode of) the semiconductor chips CPH, CPL and (each terminal of) the lead frames LF1, LF2, LF3fluctuates (varies) from assembly WK (WK2) to assembly WK (WK2). This incurs fluctuation (variation) in the spacing T31between the lead frames LF1, LF2or the spacing T32between the lead frames LF2, LF3in the assembly WK (WK2).

In this embodiment, to cope with this, the assembly jig41is provided with the supporting faces SF1b, SF1cas well as the supporting face SF1a; and some thought is put in the layout (arrangement positions) and heights of the supporting faces SF1a, SF1b, SF1cin the assembly jig41. Then with the lead frames LF1, LF2, LF3set over this assembly jig41, the solder reflow processing of Step S7is carried out.

More specific description will be given. As one of major features of this embodiment, the measures described below are taken. The following heights are made equal to each other: the height H1(shown inFIG. 29andFIG. 30) of the supporting faces SF1brelative to the supporting face SF1ain the assembly jig41; and the height H3(shown inFIG. 77andFIG. 78) of the supporting faces SF2brelative to the supporting face SF2ain the die MD2. (That is, H1=H3.) Further, the following heights are made equal to each other: the height H2(shown inFIG. 27,FIG. 29, andFIG. 31) of the supporting faces SF1crelative to the supporting face SF1ain the assembly jig41; and the height H4(shown inFIG. 75,FIG. 77, andFIG. 79) of the supporting faces SF2crelative to the supporting face SF2ain the die MD2. (That is, H2=H4.)

In this embodiment, the lead frame LF1is set over the supporting face SF1aof the assembly jig41; the lead frame LF2is supported by the supporting faces SF1bof the assembly jig41; and the lead frame LF3is supported by the supporting faces SF1cof the assembly jig41. In this state, the solder reflow processing of Step S7is carried out. In the fabricated assembly WK, for this reason, the following can be implemented. The following heights can be made equal to each other: the height H5from the lower surface of the lead frame LF1to the lower surface of the lead frame LF2(the height H5is indicated inFIG. 68,FIG. 97, andFIG. 98); and the height H1from the supporting face SF1ato the supporting faces SF1bin the assembly jig41(the height H1is indicated inFIG. 27,FIG. 29, andFIG. 30). Further, the following heights can be made equal to each other: the height H6from the lower surface of the lead frame LF1to the lower surface of the lead frame LF3in the assembly WK (the height H6is indicated inFIG. 68,FIG. 97, andFIG. 98); and the height H2from the supporting face SF1ato the supporting faces SF1cin the assembly jig41(the height H2is indicated inFIG. 27,FIG. 29, andFIG. 31). As mentioned above, the heights H1, H2of the supporting faces SF1b, SF1cof the assembly jig41are respectively equal to the heights H3, H4of the supporting faces SF2b, SF2cof the die MD2(that is, H1=H3H2=H4). In this case, the following can be implemented when the assembly WK is set over the die MD2: the height positions of the respective lower surfaces of the lead frames LF1, LF2, LF3of the assembly WK can be respectively made equal to the height positions of the supporting faces SF2a, SF2b, SF2cof the die MD2. Even though the assembly WK is clamped between the dies MD1, MD2, for this reason, the occurrence of the problems described with reference toFIG. 97orFIG. 98can be suppressed or prevented. That is, force in such directions that the lead frames LF1, LF2, LF3are stripped off from the semiconductor chip CPH or the semiconductor chip CPL can be suppressed or prevented from acting on the lead frames LF1, LF2, LF3. Further, a gap can be suppressed or prevented from being produced between the supporting faces SF2b, SF2cof the die MD2and the lower surfaces of the lead frames LF2, LF3. Therefore, it is possible to enhance the reliability of joint by solder SLD (solder joint) to enhance the reliability of the manufactured semiconductor device SM1. Further, it is possible to prevent resin leakage at the molding step, or Step S8to enhance the fabrication yield of the semiconductor device SM1.

In this application, the heights H1, H2of the supporting faces SF1b, SF1cin the assembly jig41are respectively made equal to the heights H3, H4of the supporting faces SF2b, SF2cin the die MD2. (That is, H1=H3, H2=H4.) It is most desirable that “equal” cited here should refer to complete agreement; however, the heights need not completely agree with each other and a difference to the extent that it is inevitable because of processing accuracy is permitted. Specifically, the result of examination by the present inventors revealed the following. A difference of up to 50 μm is permissible between the height H1of the supporting faces SF1bin the assembly jig41and the height H3of the supporting faces SF2bin the die MD2. (This difference is equivalent to the absolute value of the difference between the height H1and the height H3, |H1−H3|.) However, it is desirable that the difference should be 10 μm or less. (That is, it is indispensable that |H1−H3|≦50 μm; however, it is desirable that |H1−H3|≦10 μM.) Further, a difference of up to 50 μm is permissible between the height H2of the supporting faces SF1cin the assembly jig41and the height H4of the supporting faces SF2cin the die MD2. (This difference is equivalent to the absolute value of the difference between the height H2and the height H4, |H2H4|.) However, it is desirable that the difference should be 10 μm or less. (That is, it is indispensable that |H2−H4|≦50 μm; however, it is desirable that |H2−H4|≦10 μm.) This makes it possible to enjoy the above-mentioned effect of making the heights H1, H2of the supporting faces SF1b, SF1cequal to the heights H3, H4of the supporting faces SF2b, SF2c(H1=H3, H2=H4).

In this embodiment, as mentioned above, the heights H1, H2of the supporting faces SF1b, SF1cin the assembly41are respectively made equal to the heights H3, H4of the supporting faces SF2b, SF2cin the die MD2(H1=H3, H2=H4). As another of major features of this embodiment, some thought is put in the layout of the supporting faces SF1a, SF1b, SF1cin the assembly41and the layout of the supporting faces SF2a, SF2b, SF2cin the die MD2. More specific description will be given. The arrangement positions and shapes of the supporting faces SF1bin the assembly jig41are made equal to the arrangement positions and shapes of the supporting faces SF2bin the die MD2; and the arrangement positions and shapes of the supporting faces SF1cin the assembly jig41are made equal to the arrangement positions and shapes of the supporting faces SF2cin the die MD2. In other words, the assembly jig41is so designed that the upper surface of the assembly jig41is basically identical in structure with the upper surface of the die MD2. The reason for this will be described below:

When the assembly WK is fabricated, the height of the portions of the lead frame LF2set over the supporting faces SF1bof the assembly jig41becomes equal to the height H1of the supporting faces SF1b; and the height of the portions of the lead frame LF2set over the supporting faces SF1cof the assembly jig41becomes equal to the height H2of the supporting faces SF1c. However, the following can occur because of inclination, deformation, warp, or the like in the lead frame LF2or LF3: the height of a portion of the lead frame LF2or LF3that is not supported by a supporting face SF1bor SF1cof the assembly jig41can deviate from the height H1or H2of the supporting face SF1bor SF1c.

When the heights H1, H2of the supporting faces SF1b, SF1care made equal to the heights H3, H4of the supporting faces SF2b, SF2c, the following can be implemented: the height of the portions of the lead frames LF2, LF3set and supported over the supporting faces SF1b, SF1cof the assembly jig41can be made identical with the heights H3, H4of the supporting faces SF2b, SF2cof the die MD2. If the positions of the supporting faces SF1b, SF1cin the assembly jig41deviate from the positions of the supporting faces SF2b, SF2cin the die MD2unlike this embodiment, the following portions differ from each other: the portions of the lead frames LF2, LF3set and supported over the supporting faces SF1b, SF1cof the assembly jig41; and the portions thereof sandwiched and clamped between the lower surface of the die MD1and the supporting faces SF2b, SF2cof the die MD2. In this case, there is a possibility that the following can be caused by the above-mentioned inclination, deformation, warp, or the like in the lead frame LF1, LF2, or LF3: the height of a portion of the lead frame LF2or LF3that is sandwiched and clamped between the lower surface of the die MD1and a supporting face SF2bor SF2cof the die MD2can deviate from the following heights: the heights H3, H4of the supporting faces SF2b, SF2cof the die MD2. In this case, the problems described with reference toFIG. 97orFIG. 98can arise.

In this embodiment, as mentioned above, the arrangement positions and shapes of the supporting faces SF1b, SF1cin the assembly jig41are respectively equal to the arrangement positions and shapes of the supporting faces SF2b, SF2cin the die MD2. For this reason, the following portions can be made identical (their positions can be made identical: the portions of the lead frames LF2, LF3set and supported over the supporting faces SF1b, SF1cof the assembly jig41; and the portions thereof sandwiched and clamped between the lower surface of the die MD1and the supporting faces SF2b, SF2cof the die MD2. Therefore, the following heights can be made identical with each other: the heights of the portions of the lead frames LF2, LF3sandwiched and clamped between the lower surface of the die MD1and the supporting faces SF2b, SF2cof the die MD2; and the heights H3, H4of the supporting faces SF2b, SF2cof the die MD2. This makes it possible to appropriately prevent the problems described with reference toFIG. 97orFIG. 98. As a result, it is possible to further enhance the reliability of joint by solder SLD (solder joint) to more appropriately enhance the reliability of the manufactured semiconductor device SM1. Further, it is possible to more appropriately prevent resin leakage during the molding step, or Step S8to more appropriately enhance the fabrication yield of the semiconductor device SM1.

It is most desirable that the following measure should be taken: the assembly jig41is so designed that the upper surface of the assembly jig41is basically identical in structure with the upper surface of the die MD2; and the arrangement positions and shapes of the supporting faces SF1b, SF1cin the assembly jig41and the arrangement positions and shapes of the supporting faces SF2b, SF2cin the die MD2are made identical with each other. However, the effect of this embodiment can be obtained even though the arrangement positions and shapes of the supporting faces SF1b, SF1cin the assembly jig41and the arrangement positions and shapes of the supporting faces SF2b, SF2cof the die MD2are not completely equal to each other. This can be done by designing the arrangement positions and shapes of the supporting faces SF1b, SF1cso that the following conditions are met:

In the die MD2, the area where each drain terminal TDH of the lead frame LF1is to be set is the supporting face SF1a. Therefore, the bottom surface of each cavity CAV is formed by the supporting face SF2a. The supporting faces SF2bare arranged in positions adjacent to each cavity CAV. This is because it is required to: set part of the lead frame LF2, more specifically, the outer lead portions of each source-drain terminal TSD and gate terminal TGH over the supporting faces SF2badjacent to each cavity CAV; and inject resin material into each cavity CAV formed by the dies MD1, MD2with it sandwiched between the supporting faces SF2bof the die MD2and the die MD1to form the encapsulation resin portion MR. The supporting faces SF2care also arranged in positions adjacent to each cavity CAV. This is because it is required to: set part of the lead frame LF3, more specifically, the outer lead portions of each gate terminal TGL and source terminal TSL over the supporting faces SF2cadjacent to each cavity CAV; and inject resin material into each cavity CAV formed by the dies MD1, MD2with it sandwiched between the supporting faces SF2cof the die MD2and the die MD1to form the encapsulation resin portion MR.

In the assembly jig41, meanwhile, the area where each drain terminal TDH of the lead frame LF1is to be set is the supporting face SF1a. Then the arrangement positions and shapes (layout) of the supporting faces SF1bin the assembly jig41are so designed that the following portions are set over the supporting faces SF1bof the assembly jig41at Steps S4to S7: the portions of the lead frame LF2sandwiched between the supporting faces SF2bof the die M2and the die MD1at Step S8(more specifically, the outer lead portions of each source-drain terminal TSD and gate terminal TGH). That is, the layout of the supporting faces SF1bof the assembly jig41may be made different from the layout of the supporting faces SF2bin the die MD2as long as the following is implemented: the portions of the lead frame LF2sandwiched between the supporting faces SF2bof the die M2and the die MD1at Step S8are set over the supporting faces SF1bof the assembly jig41at Steps S4to S7(more specifically, the outer lead portions of each source-drain terminal TSD and gate terminal TGH are set over the supporting faces SF1bof the assembly jig41at Steps S4to S7). Further, the arrangement positions and shapes (layout) of the supporting faces SF1cof the assembly jig41are so designed that the following portions are set over the supporting faces SF1cof the assembly jig41at Steps S4to S7: the portions of the lead frame LF3sandwiched between the supporting faces SF2cof the die M2and the die MD1at Step S8(more specifically, the outer lead portions of each gate terminal TGL and source terminal TSL). That is, the layout of the supporting faces SF1cof the assembly jig41may be made different from the layout of the supporting faces SF2cin the die MD2as long as the following is implemented: the portions of the lead frame LF3sandwiched between the supporting faces SF2cof the die M2and the die MD1at Step S8are set over the supporting faces SF1cof the assembly jig41at Steps S4to S7(more specifically, the outer lead portions of each gate terminal TGL and source terminal TSL are set over the supporting faces SF1cof the assembly jig41at Steps S4to S7). It is required that the heights H1, H2of the supporting faces SF1b, SF1cin the assembly jig41should be respectively made equal to the heights H3, H4of the supporting faces SF2b, SF2cin the die MD2(that is, H1=H3, H2=H4). However, complete agreement is not required and the difference to the above-mentioned extent is permissible. (That is, it is indispensable that the difference between H1and H3and the difference between H2and H4should be respectively 50 μm or less and a difference of 10 μm or less is more desirable.)

Even in this case, the following heights can be made substantially equal to each other in the assembly WK fabricated by Steps S1to S7: the heights of the portions (the outer lead portions of each terminal) sandwiched and clamped between the supporting faces SF2b, SF2cof the die MD2and the die MD1in positions adjacent to each cavity CAV at Step S8; and the heights H3, H4of the supporting faces SF2b, SF2cof the die MD2. This makes it possible to prevent the problems described with reference toFIG. 97orFIG. 98. As a result, it is possible to enhance the reliability of joint by solder SLD (solder joint) to enhance the reliability of the manufactured semiconductor device SM1. Further, it is possible to prevent resin leakage during the molding step, or Step S8to enhance the fabrication yield of the semiconductor device SM1.

In this embodiment, as mentioned above, the lead frames LF1, LF2, LF3are set over the assembly jig41so that the positioning pins42of the assembly jig41are inserted into the openings OP2in the lead frames LF1, LF2, LF3. In each lead frame LF1, LF2, LF3, it is desirable that these openings OP2should be arranged as illustrated inFIG. 19,FIG. 21, andFIG. 23. That is, they should be arranged in proximity to the center in the Y-direction, or the direction of the length of each lead frame LF1, LF2, LF3. The openings OP2are provided to determine the planar position of each lead frame LF1, LF2, LF3. Therefore, the following can be implemented by arranging them in proximity to the center in the Y-direction, or the direction of length: the overall position of each lead frame LF1, LF2, LF3can be more accurately determined than in cases where they are arranged in proximity to the ends of the lead frames LF1, LF2, LF3. When each lead frame LF1, LF2, LF3is a multiple lead frame in which multiple unit regions UT1are arranged as illustrated inFIG. 19,FIG. 21, andFIG. 23, the following can be implemented: in each lead frame LF1, LF2, LF3, the openings OP2have to be provided only in the unit region UT1apositioned in proximity to the center in the Y-direction, or the direction of length and the openings OP2need not be provided in the other unit regions UT1.

The lead frames LF1, LF2, LF3can elongate in the direction of length (Y-direction) during heating in the solder reflow processing of Step S7. The following advantage is obtained by providing the openings OP2only in proximity to the center in the Y-direction, or the direction of length in each lead frame LF1, LF2, LF3: even though a lead frame LF1, LF2, LF3elongates in the direction of length (Y-direction) during heating in the solder reflow processing of Step S7, this elongation is not limited by the pins42. This makes it possible to prevent the lead frames LF1, LF2, LF3from warping and enhance the degree of parallelization between the lead frames LF1, LF2, LF3.

The number of pins42provided in the assembly jig41and the number of openings OP2in each lead frame LF1, LF2, LF3into which they are inserted are equal to each other. The required number of pins42provided in the assembly jig41(that is, the required number of openings OP2provided in each lead frame LF1, LF2, LF3) is at least one but may be more than one. Even in cases where more than one are provided, it is desirable that the multiple openings OP2should be arranged in proximity to the center in the Y-direction, or the direction of length in each lead frame LF1, LF2, LF3as illustrated inFIG. 19,FIG. 21, andFIG. 23. It is desirable that these openings OP2should be set (arranged) in line in the X-direction orthogonal to the Y-direction.

The number of pins42provided in the assembly jig41(that is, the number of openings OP2provided in each lead frame LF1, LF2, LF3) may be made equal to the following number: the total number of the lead frames LF1, LF2, LF3set over the assembly jig41, that is, three. Thus the three pins42(that is, the pins42a,42b,42cshown inFIG. 25andFIG. 26) of the assembly jig41can be used as follows: the lead frame LF1is positioned by the pin42a, the lead frame LF2is positioned by the pin42b, and the lead frame LF3is positioned by the pin42c. That is, different pins42are used as the pin42afor positioning the lead frame LF1, the pin42bfor positioning the lead frame LF2, and the pin42cfor positioning the lead frame LF3. This can be implemented as follows:

In the lead frame LF1, the following measure is taken with respect to the three openings OP2(that is, the openings OP2a, OP2b, OP2cshown inFIG. 19andFIG. 20) into which the pins42a,42b,42cof the assembly jig41are inserted. The size (diameter) of the opening OP2ainto which the pin42ais inserted is substantially matched with the size (diameter) of the pin42a. In the lead frame LF1, the size (diameter) of the opening OP2binto which the pin42bis inserted is made slightly larger than the size (diameter) of the pin42b; and the size (diameter) of the opening OP2cinto which the pin42cis inserted is made slightly larger than the size (diameter) of the pin42c. That is, in the lead frame LF1, the following differences are made larger than the size difference (diameter difference) between the opening OP2aand the pin42ainserted thereinto: the size difference (diameter difference) between the opening OP2band the pin42binserted thereinto; and the size difference (diameter difference) between the opening OP2cand the pin42cinserted thereinto. As a result, when the pin42aof the assembly jig41is inserted into the opening OP2ain the lead frame LF1, the position of the lead frame LF1can be defined and determined by the pin42aof the assembly jig41. At this time, the pins42b,42cof the assembly jig41are respectively inserted into the openings OP2b, OP2cin the lead frame LF1. Since there is an allowance (gap) between the pins42b,42cand the openings OP2b, OP2cin the lead frame LF1, however, the lead frame LF1is substantially positioned by the following: the pin42aof the assembly jig41and the opening OP2ain the lead frame LF1.

In the lead frame LF2, the following measure is taken with respect to the three openings OP2(that is, the openings OP2a, OP2b, OP2cshown inFIG. 21andFIG. 22) into which the pins42a,42b,42cof the assembly jig41are inserted. The size (diameter) of the opening OP2binto which the pin42bis inserted is substantially matched with the size (diameter) of the pin42b. In the lead frame LF2, the size (diameter) of the opening OP2ainto which the pin42ais inserted is made slightly larger than the size (diameter) of the pin42a; and the size (diameter) of the opening OP2cinto which the pin42cis inserted is made slightly larger than the size (diameter) of the pin42c. That is, in the lead frame LF2, the following differences are made larger than the size difference (diameter difference) between the opening OP2band the pin42binserted thereinto: the size difference (diameter difference) between the opening OP2aand the pin42ainserted thereinto; and the size difference (diameter difference) between the opening OP2cand the pin42cinserted thereinto. As a result, when the pin42bof the assembly jig41is inserted into the opening OP2bin the lead frame LF2, the position of the lead frame LF2can be defined and determined by the pin42bof the assembly jig41. At this time, the pins42a,42cof the assembly jig41are respectively inserted into the openings OP2a, OP2cin the lead frame LF2. Since there is an allowance (gap) between the pins42a,42cand the openings OP2a, OP2cin the lead frame LF2, however, the lead frame LF2is substantially positioned by the following: the pin42bof the assembly jig41and the opening OP2bin the lead frame LF2.

In the lead frame LF3, the following measure is taken with respect to the three openings OP2(that is, the openings OP2a, OP2b, OP2cshown inFIG. 23andFIG. 24) into which the pins42a,42b,42cof the assembly jig41are inserted. The size (diameter) of the opening OP2cinto which the pin42cis inserted is substantially matched with the size (diameter) of the pin42c. In the lead frame LF3, the size (diameter) of the opening OP2ainto which the pin42ais inserted is made slightly larger than the size (diameter) of the pin42a; and the size (diameter) of the opening OP2binto which the pin42bis inserted is made slightly larger than the size (diameter) of the pin42b. That is, in the lead frame LF3, the following differences are made larger than the size difference (diameter difference) between the opening OP2cand the pin42cinserted thereinto: the size difference (diameter difference) between the opening OP2aand the pin42ainserted thereinto; and the size difference (diameter difference) between the opening OP2band the pin42binserted thereinto. As a result, when the pin42cof the assembly jig41is inserted into the opening OP2cin the lead frame LF3, the position of the lead frame LF3can be defined and determined by the pin42cof the assembly jig41. At this time, the pins42a,42bof the assembly jig41are respectively inserted into the openings OP2a, OP2bin the lead frame LF3. Since there is an allowance (gap) between the pins42a,42band the openings OP2a, OP2bin the lead frame LF3, however, the lead frame LF3is substantially positioned by the following: the pin42cof the assembly jig41and the opening OP2cin the lead frame LF3.

The processing accuracy of the openings OP2in the lead frames LF1, LF2, LF3can differ from lead frame LF1, LF2, LF3to lead frame LF1, LF2, LF3because of the thickness or the like of each lead frame LF1, LF2, LF3. For this reason, the pins and the openings are differently brought into correspondence with each other. That is, with respect to the lead frame LF1, the positioning pin42aand the opening PO2aare brought into correspondence with each other; with respect to the lead frame LF2, the positioning pin42band the opening OP2bare brought into correspondence with each other; and with respect to the lead frame LF3, the positioning pin42cand the opening OP2care brought into correspondence with each other. This makes it possible to form the positioning openings OP2a, OP2b, OP2cand the pins42a,42b,42cin accordance with the processing accuracy of each lead frame LF1, LF2, LF3. As a result, it is possible to enhance the overall positioning accuracy of the lead frames LF1, LF2, LF3set over the assembly jig41.

As mentioned above, it is desirable that the openings OP2a, OP2b, OP2cshould be set (arranged) as described below in proximity to the center of the direction of the length (Y-direction) of each lead frame LF1, LF2, LF3: they should be set (arranged) in line along the X-direction intersecting with (orthogonal to) the direction of length (Y-direction).

FIG. 99is a plan view (substantial part plan view) illustrating a modification to the assembly jig41and corresponds toFIG. 26.FIG. 100is a plan view (substantial part plan view) illustrating the lead frames LF1, LF2, LF3set over the assembly jig41inFIG. 99(which underwent up to Step S6) and corresponds toFIG. 57.FIG. 101is a sectional view taken along line C9-C9ofFIG. 100andFIG. 102is a sectional view taken along line C2-C2ofFIG. 100(that is, a sectional view corresponding toFIG. 59). ThoughFIG. 99andFIG. 100are plan views, protruded portions71a,71b,72a,72b,72care hatched to facilitate visualization (to make the layout of the protruded portions71a,71b,72a,72b,72cmore understandable).

The assembly jig41illustrated inFIG. 99toFIG. 102has protruded portions in the upper surface of the assembly jig41. The protruded portions (second projections, projections, salient portions, tab portions)71a,71bare for positioning the lead frame LF1in the X-direction and limiting its movement in the X-direction. The protruded portions (second projections, projections, salient portions, tab portions)72a,72b,72care for positioning the lead frames LF2, LF3in the X-direction and limiting their movement in the X-direction. The protruded portions71a,71b,72a,72b,72care locally protruded upward in the upper surface of the assembly jig41. That is, they are projections. It is desirable that the protruded portions71a,71bshould be set in the supporting face SF1aof the assembly jig41and the protruded portions72a,72b,72cshould be set in the supporting faces SF1b, SF1cof the assembly jig41. The configuration of the assembly jig41(41a) inFIG. 99to FIG.102is the same as the assembly jig41illustrated inFIG. 25toFIG. 31except that the protruded portions71a,71b,72a,72b,72care provided. In the following description, the assembly jig41provided with the protruded portions71a,71b,72a,72b,72c, illustrated inFIG. 99toFIG. 102will be designated as assembly jig41a.

The protruded portions71a,71b,72a,72b,72cprovided on the assembly jig41aare positioned in proximity to both ends of each of the lead frames LF1, LF2, LF3set over the assembly jig41ain the Y-direction. They functions to arrest (limit) the movement of the lead frames LF1, LF2, LF3in the direction (more specifically, the X-direction) intersecting with the Y-direction.

More specific description will be given. As illustrated inFIG. 100toFIG. 102, the protruded portions71a,71bof the assembly jig41aare provided in positions where they do not planarly overlap with the lead frame LF1, LF2, or LF3in the supporting face SF1a. At the same time, they are arranged away from each other in the X-direction and protruded upward from the upper surface of the assembly jig41a(more specifically, the supporting face SF1aof the assembly jig41a). When the lead frames LF1, LF2, LF3are set over the assembly jig41a, as illustrated inFIG. 100andFIG. 102, the following is implemented: at least part (the drain terminal TDH in the example inFIG. 100andFIG. 102) of the lead frame LF1is sandwiched between the protruded portion71aand the protruded portion71barranged away from each other in the X-direction; and the movement of the lead frame LF1in the X-direction can be limited (arrested) by the protruded portions71a,71b. However, since at least part of the lead frame LF1is sandwiched between the protruded portions71a,71barranged away from each other in the X-direction, the following results: the movement of the lead frame LF1in the Y-direction is not limited (arrested) by the protruded portion71aor71b. For this reason, the lead frame LF1is positioned by the protruded portions71a,71bin the X-direction but they are not positioned and are free in the Y-direction.

As illustrated inFIG. 100toFIG. 102, the protruded portions72a,72b,72cof the assembly jig41aare provided in positions where they do not planarly overlap with the lead frame LF1, LF2, or LF3in the upper surface of the assembly jig41a. At the same time, they are arranged away from one another in the X-direction and protruded upward from the upper surface of the assembly jig41a(more specifically, the supporting faces SF1b, SF1cof the assembly jig41a). When the lead frames LF1, LF2, LF3are set over the assembly jig41a, as illustrated inFIG. 100andFIG. 101, the following is implemented: at least part of the lead frame LF2is sandwiched between the protruded portion72aand the protruded portion72barranged away from each other in the X-direction; and at least part of the lead frame LF3is sandwiched between the protruded portion72band the protruded portion72carranged away from each other in the X-direction. This makes it possible to limit (arrest) the movement of the lead frame LF2in the X-direction by the protruded portions72a,72band limit (arrest) the movement of the lead frame LF3in the X-direction by the protruded portions72b,72c.

However, since at least part of the lead frame LF2is sandwiched between the protruded portions72a,72barranged away from each other in the X-direction, the following results: the movement of the lead frame LF2in the Y-direction is not limited (arrested) by the protruded portions72aor72b. Further, since at least part of the lead frame LF3is sandwiched between the protruded portions72b,72carranged away from each other in the X-direction, the following results: the movement of the lead frame LF3in the Y-direction is not limited (arrested) by the protruded portion72bor72c. For this reason, the lead frames LF2, LF3are positioned by the protruded portions72a,72b,72cin the X-direction but they are not positioned and are free in the Y-direction.

As mentioned above, the protruded portions71a,71b,72a,72b,72care provided to position the lead frames LF2, LF3in the X-direction. It is unnecessary to provide the protruded portions71a,71b,72a,72b,72cin all the unit regions UT1in each multiple lead frame LF1, LF2, LF3in which multiple unit regions UT1are arranged. However, it is desirable to take the following measure in each multiple lead frame LF1, LF2, LF3in which multiple unit regions UT1are arranged in the Y-direction: the protruded portions71a,71b,72a,72b,72care provided in the unit regions UT positioned at both ends in the Y-direction, or the direction of length. (These unit regions correspond to the unit regions UT1marked with reference numeral UT1binFIG. 19,FIG. 21, andFIG. 23.) More specific description will be given. The assembly jig41illustrated inFIG. 25is so configured that multiple unit regions RG1, in each of which each unit region UT1of the lead frames LF1, LF2, LF3is set, are arranged in the Y-direction. The unit regions RG1positioned at both ends in the Y-direction (corresponding to the unit regions RG1marked with reference code RGlb inFIG. 25) only have to be so configured that the protruded portions71a,71b,72a,72b,72care provided as illustrated inFIG. 99.

The protruded portions71a,71b,72a,72b,72care provided in the unit regions UT at both ends in the direction of the length of each multiple lead frame LF1, LF2, LF3(Y-direction). The lead frames LF1, LF2, LF3are positioned in the X-direction and their movement in the X-direction is limited by the protruded portions71a,71b,72a,72b,72c. As a result, each lead frame LF1, LF2, LF3can be prevented from rotating around a pin42of the assembly jig42. This makes it possible to suppress or prevent change in the relative position between the assembly jig41, lead frame LF1, lead frame LF2, and lead frame LF3during heating in the solder reflow processing of Step S7or on other like occasions.

The multiple lead frames LF1, LF2, LF3are formed of metal material, such as copper or copper alloy; therefore, there is a possibility that they elongate in the direction of length (Y-direction) during heating in the solder reflow processing of Step S7. The protruded portions71a,71b,72a,72b,72cposition the lead frames LF1, LF2, LF3in the X-direction but they do not position the lead frames and keeps them free in the Y-direction. Therefore, even though a lead frame LF1, LF2, LF3elongates in the direction of length (Y-direction) during heating in the solder reflow processing of Step S7, this elongation is not limited by the protruded portion71a,71b,72a,72b, or72c. That is, the protruded portion71a,71b,72a,72b, or72cdoes not arrest (limit) the elongation or contraction of the lead frames LF1, LF2, LF3in the direction of length (Y-direction). This makes it possible to prevent the lead frames LF1, LF2, LF3from warping and enhance the degree of parallelization between the lead frames LF1, LF2, LF3.

After the lead frame LF3is set over the assembly jig41at Step S6, the solder reflow processing (solder reflow heat treatment) of Step S7may be carried out while the lead frame LF3set over the assembly jig41is retained.FIG. 103is an explanatory drawing (sectional view) illustrating an example of how to retain the lead frame LF3and this sectional view corresponds toFIG. 63.

After the steps up to Step S6are carried out to set the lead frames LF1, LF2, LF3over the assembly jig41, the lead frame LF3can be retained from above by a retaining member81as illustrated inFIG. 103. At this time, the following measure is taken: the retaining member81is not set over the areas where the encapsulation resin portion MR is to be formed later or over the supporting faces SF1bor SF1cso that the lead frame LF3is not retained by the retaining member81; and the retaining member81is set over the other areas (especially, the portions of the framework LF3apositioned in boundaries between adjacent unit regions UT1in the lead frame LF3) to retain the lead frame LF3. The reason why the lead frame LF1, LF2, or LF3is not retained over the areas where the encapsulation resin portion MR is to be formed later or over the supporting faces SF1bor SF1cis to prevent deformation in a product portion (an area to be the semiconductor device SM1later).

While the lead frame LF3is retained by the retaining member81or the like, the solder reflow processing of Step S7is carried out. This makes it possible to prevent the lead frame LF2or LF3from lifting during the solder reflow processing of Step S7. Therefore, it is possible to more appropriately fabricate the assembly WK in which the heights H5, H6agree with the heights H1, H2of the supporting faces SF1b, SF1cin the assembly jig41. The retaining member81can be formed of, for example, the same carbon material or SUS material as the material of the assembly jig41.

FIG. 104toFIG. 108are explanatory drawings illustrating a modification to the molding step, or Step S8. In the following description, the modification to the molding step, or Step S8, described with reference toFIG. 104toFIG. 108will be designated as molding step, or Step S8a.FIG. 104andFIG. 105correspond to substantial part plan views illustrating the assembly WK set over the die MD2at the molding step, or Step S8a.FIG. 104shows the area (planar area) corresponding toFIG. 80andFIG. 105shows the area (planar area) substantially corresponding toFIG. 65. InFIG. 104andFIG. 105, the positions (areas) where the outer lead portions of the source-drain terminal TSD and the source terminal TSL are pressed and crushed by projections91of the die MD1are indicated by reference numeral92.FIG. 106andFIG. 107substantially correspond to sectional views at the position of line E1-E1ofFIG. 105andFIG. 108substantially corresponds to a sectional view at the position of line E2-E2ofFIG. 105.FIG. 106illustrates the molding step, or Step S8aafter the assembly WK is set over the die MD2and before the dies MD1, MD2are clamped.FIG. 107andFIG. 108illustrate the molding step, or Step S8awith the die MD1moved down toward the die MD2and the assembly WK sandwiched and clamped between the dies MD1, MD2.

To carry out the molding step, or Step S8a, the projections (third projections)91are provided in advance on the die MD1in positions where it is opposed to the supporting faces S2b, SF2cof the die MD2. At the molding step, Step S8a, the outer lead portions of each source-drain terminal TSD and source terminal TSL of the lead frames LF2, LF3are sandwiched and clamped between the following: the supporting faces SF2b, SF2cof the die MD2and (the lower surface of) the die MD1. At this time, part of the outer lead portions of each source-drain terminal TSD and source terminal TSL is crushed by a projection91of the die MD1.

More specific description will be given. At the molding step, or Step S8a, the following parts are locally crushed by the projections91provided on the lower surface of the die MD1as the upper die when the assembly WK is clamped between the dies MD1, MD2: part of the outer lead portions of each source-drain terminal TSD of the lead frame LF2set over the supporting faces SF2b; and part of the outer lead portions of each source terminal TSL of the lead frame LF3set over the supporting faces SF2c. The height of each projection91of the die MD1is smaller (lower) than the thickness of each of the lead frames LF2, LF3.

The outer lead portions of each source-drain terminal TSD of the lead frame LF2are set over the supporting faces SF2bof the die MD2. In the upper surfaces of these outer lead portions, the positions (areas)92where they are crushed by projections91of the die MD1are in proximity to ends in the X-direction as illustrated inFIG. 104andFIG. 105. The outer lead portions of each source terminal TSL of the lead frame LF3are set over the supporting faces SF2cof the die MD2. In the upper surfaces of these outer lead portions, the positions (areas)92where they are crushed by projections91of the die MD1are in proximity to ends in the X-direction as illustrated inFIG. 104andFIG. 105.

However, it is desirable to take the following measure in the upper surfaces of the outer lead portions of each source-drain terminal TSD of the lead frame LF2: the vicinity of the end on the side where it adjoins to a gate terminal TGH (that is, the end on the side where the tie bar TB1is formed) is prevented from being crushed by a projection91of the die MD1; and the vicinity of the end on the side where it does not adjoin to a gate terminal TGH (that is, the end on the side where the tie bar TB1is not formed) is crushed by a projection91of the die MD1. Similarly, it is desirable to take the following measure in the upper surfaces of the outer lead portions of each source terminal TSL of the lead frame LF3: the vicinity of the end on the side where it adjoins to a gate terminal TGL (that is, the end on the side where the tie bar TB2is formed) is prevented from being crushed by a projection91of the die MD1; and the vicinity of the end on the side where it does not adjoin to a gate terminal TGL (that is, the end on the side where the tie bar TB2is not formed) is crushed by a projection91of the die MD1.

As mentioned above, the outer lead portions of each source-drain terminal TSD and source terminal TSL of the lead frames LF2, LF3are locally crushed by projections91of the die MD1in proximity to ends of the upper surfaces of the outer lead portions. The reason for this is to: spread the outer lead portions in the lateral direction (X-direction in this case); and thereby fill the gap in the lateral direction (X-direction) between the outer lead portions and the lateral surfaces of the dies MD1, MD2(corresponding to the lateral surfaces93illustrated inFIG. 106toFIG. 108).

In areas distant from the positions (areas)92where outer lead portions are crushed by projections91of the die MD1, a little gap94is produced as illustrated inFIG. 108as well. These gaps are produced between the outer lead portions of each source-drain terminal TSD and source terminal TSL and the lateral surfaces (the lateral surfaces93illustrated inFIG. 106toFIG. 108and the like) of the dies MD1, MD2. In consideration of the processing accuracy of the lead frames LF1, LF2, LF3, the assembling accuracy of the assembly WK, and the like, these gaps94are required as margins. However, when resin material is injected into each cavity CAV in the dies MD1, MD2to form the encapsulation resin portion MR, there is a possibility that resin leakage from these gaps94occurs.

At the molding step, or Step S8a, as mentioned above, the projections91are provided on the lower surface of the die MD1and the outer lead portions of each source-drain terminal TSD and source terminal TSL are crushed at the above-mentioned positions92. As illustrated inFIG. 107, as a result, the outer lead portions of each source terminal TSL are locally crushed by projections91of the die MD1in proximity to ends of their upper surfaces and they are spread in the lateral direction (X-direction). This makes it possible to fill the gaps in the lateral direction (X-direction) (equivalent to the gaps94) between the outer lead portions of the source terminal TSL and the lateral surfaces93of the die MD2. Similarly, the outer lead portions of each source-drain terminal TSD are locally crushed by projections91of the die MD1in proximity to ends of their upper surfaces and they are spread in the lateral direction (X-direction). This makes it possible to fill the gaps in the lateral direction (X-direction) (equivalent to the gaps94) between the outer lead portions of the source-drain terminal TSD and the lateral surfaces of the die MD2(or the die MD1). As a result, it is possible to suppress or prevent resin leakage when resin material is injected into each cavity CAV in the dies MD1, MD2to form the encapsulation resin portion MR.

The outer lead portions of the gate terminals TGH, TGL have a source-drain terminal TSD or a source terminal TSL arranged on both adjacent sides and resin leakage can be prevented by the tie bars TB1, TB2. Therefore, it is unnecessary to crush these outer lead portions with projections91of the die MD1.

Up to this point, concrete description has been given to the invention made by the present inventors based on an embodiment thereof. However, the invention is not limited to this embodiment and can be variously modified without departing from the subject matter thereof, needless to add.

In the description of the above embodiment, a case where the semiconductor device SM1so structured that the semiconductor chips CPH, CPL are sandwiched between the three lead frames LF1, LF2, LF3is manufactured has been taken as an example. The invention is also applicable to cases where a semiconductor device so structured that a semiconductor chip CPH is sandwiched between two lead frames LF1, LF2. In this case, the semiconductor chip CPL and the lead frame LF3are omitted and Steps S1to S4are carried out and then Steps S7to S12are carried out without carrying out Step S5or S6. In the assembly jig41and die MD2used at this time, the supporting faces SF1c, SF2care unnecessary. Therefore, the supporting faces SF1c, SF2ccan be formed as faces at the same height as the supporting faces SF1a, SF2aor the supporting faces SF1b, SF2b. The semiconductor device manufactured in this case is equivalent to the semiconductor device SM1so structured that: the semiconductor chip CPL, gate terminal TGL, and source terminal TSL (in addition, the solder SLD in areas where the semiconductor chip CPL and the source-drain terminal TSD are joined together) are omitted. In conjunction with the omission of these elements, the thickness of the encapsulation resin portion MR is reduced. That is, when a semiconductor device so structured that a semiconductor chip CPH is sandwiched between two lead frames LF1, LF2is manufactured, the problem described with reference toFIG. 97can be solved by applying major features described in relation to this embodiment.

The numbers of stacked lead frames and semiconductor chips are larger in cases where a semiconductor device SM1so structured that semiconductor chips CPH, CPL are sandwiched between three lead frames LF1, LF2, LF3as in this embodiment than in the following cases: cases where a semiconductor device so structured that a semiconductor chip CPH is sandwiched between two lead frames LF1, LF2is manufactured. In cases like this embodiment, the spacing between lead frames (equivalent to the spacing T31, T32) is accordingly prone to fluctuate. For this reason, the effect of applying the major features described in relation to this embodiment to manufacture a semiconductor device so structured that semiconductor chips CPH, CPL are sandwiched between three lead frames LF1, LF2, LF3is very great. Thus the major features described in relation to this embodiment brings greater effect in the following structure: a structure in which the numbers of stacked lead frames and semiconductor chips are large and the error in spacing between lead frames becomes large (accumulated) when these elements are stacked.

In the description of the above embodiment, a case where the invention made mainly by the present inventors is applied to a semiconductor device used in a DC-DC converter, which is the field of utilization underlying the invention, has been taken as an example. However, the invention is not limited to this and is applicable to various semiconductor devices manufactured with a semiconductor chip placed between multiple lead frames.

The invention is effectively applicable to a semiconductor device and a manufacturing technology therefor.