Semiconductor device with a line and method of fabrication thereof

A semiconductor device includes an interlayer insulation film, an underlying line provided in the interlayer insulation film, a liner film overlying the interlayer insulation film, an interlayer insulation film overlying the liner film. The underlying line has a lower hole and the liner film and the interlayer insulation film have an upper hole communicating with the lower hole, and the lower hole is larger in diameter than the upper hole. The semiconductor device further includes a conductive film provided at an internal wall surface of the lower hole, a barrier metal provided along an internal wall surface of the upper hole, and a Cu film filling the upper and lower holes. The conductive film contains a substance identical to a substance of the barrier metal. A highly reliable semiconductor device can thus be obtained.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to semiconductor devices and methods of fabrication thereof and particularly to highly reliable semiconductor devices and methods of fabrication thereof

2. Description of the Background Art

As a material for a line for large scale integration circuits (LSIs), aluminum has conventionally been employed. However, as LSIs are increasingly microfabricated and operated more rapidly, aluminum is being replaced with copper (Cu), a material smaller in electrical resistance. Employing Cu as a material for a line for LSIs allows electrical resistance to be reduced and also the line to be microfabricated, and also allows LSIs to operate faster. Cu, however, is diffusible into insulation film. If Cu diffuses into insulation film, the line would be impaired in reliability. Furthermore, Cu reacts with plasma ions very slowly. As such, if etching is employed to form the line, sufficient productivity cannot be achieved.

To address these disadvantages in recent years a Cu line is formed in damascene. If typical damascene is employed to form a Cu line the line is formed as follows:

Initially an underlying line of Cu is covered with a liner film, an interlayer insulation film and an anti-reflection film deposited in layers. Subsequently, resist for forming a via hole is deposited on the anti-reflection film and typical photolithography and etching are employed to provide the interlayer insulation film with the via hole so that the via hole has a bottom has a bottom surface exposing the liner film. The resist for forming the via hole is then removed and thereafter resist for forming a trench is deposited on the anti-reflection film and in the via hole and typical photolithography and etching are employed to provide the interlayer insulation film with a trench. Then the resist for forming the trench and the anti-reflection film are removed and thereafter the liner film exposed at the bottom surface of the via hole is etched to expose the underlying line. Then a Cu oxide film of a surface of the underlying line exposed at the via hole's bottom surface, residue (or polymer) produced in etching the liner film, and the like are removed by performing argon (Ar) sputter etching, annealing in an ambient of hydrogen (H2), a plasma process, wet-etching, or the like. Then, barrier metal is deposited on the via hole and trench's sidewall and bottom surfaces and the interlayer insulation film. Then, a thin Cu film serving as a film that shields plating is deposited on the barrier metal, and plating is employed to deposit a Cu film on the via hole and trench's sidewall and bottom surfaces, and the interlayer insulation film. Then, excessive Cu film and barrier metal on the interlayer insulation film is chemically mechanically polished and thus removed to complete the Cu line.

The Cu line thus obtained, however, is more breakable as voids are caused. More specifically, when high temperature is attained for example in a thermal treatment, an actual environment of use, or the like, thermal stress is caused between the interlayer insulation film and the Cu line. For a conventional Cu line, the underlying line's surface and the via hole's side wall are in contact with each other at a right angle, and a portion at which the underlying line's surface and the Cu line's bottom contact each other tends to experience concentrated thermal stress.

Furthermore in the via hole the Cu line passes a current, which passes through the portion at which the underlying line's surface and the Cu line's bottom contact each other, and flows to the underlying line, which has a larger area in cross section than the via hole. As such, the portion at which the underlying line's surface and the Cu line's bottom contact each other tends to experience a concentrated current.

Thus the portion at which the underlying line's surface and the Cu line's bottom tends to experience concentrated thermal stress and current. As such, the portion provides a point initially causing voids. For a conventional Cu line, the underlying line and the Cu line contact each other in a plane. As such, the lines mutually contact over an insufficient area, and the line is disadvantageously more breakable. Furthermore, between the Cu line and the underlying line there is a disadvantageously large electrical resistance.

To address this, a method of forming a line that allows a Cu line and an underlying line to mutually contact over an increased area is disclosed for example in Japanese Patent Laying-Open No. 2002-064138. As described in the document, the line is formed as follows:

On a first layer line of Cu a copper diffusion preventing insulation film is deposited and thereafter an interlayer insulation film is deposited. Subsequently on the interlayer insulation film a resist film is deposited and used as a mask to expose a surface of the first layer line by anisoptropically etching the interlayer insulation film and the copper diffusion preventing insulation film. Furthermore, the first layer line's exposed surface is further etched to form a contact hole having a bottom deeper than the first layer line's surface. Subsequently a barrier layer is deposited on the interlayer insulation film including the contact hole's interior. Subsequently, a tantalum (Ta) film is deposited on the barrier layer. Subsequently, the Ta film and barrier layer outside the contact hole is chemically mechanically polished and thus removed to form a plug on the first layer line.

In the method disclosed in the publication the interlayer insulation film and the first layer line are etched to form a hole which in turn has a plug introduced therein. As such, the plug has a bottom surface and a partial side surface in contact with the first layer line. More specifically, the plug and the first layer line can mutually contact stereoscopically and hence over an increased area.

Other than the above publication, for example Japanese Patent Laying-Open Nos. 2001-077195, 2000-114261, 07-014836 and 2000-133711 also disclose etching an interlayer insulation film and an underlying line to form a hole which is in turn provided therein with a conductive layer.

As disclosed in Japanese Patent Laying-Open No. 2002-064138, resist remaining in the hole and residue (or polymer) of the copper diffusion preventing insulation film are removed, and this requires that after the interlayer insulation film and the first layer line are etched the hole's interior be washed. However, the hole's interior is washed with a solution having a property dissolving Cu. As such, in the cleaning the hole the first layer liner is wet-etched. This results in the first layer line having a hole larger in diameter than that in the interlayer insulation film. In other words, the first layer line has a hole having an internal wall with a recess. At this recess the barrier layer and the Ta film are hardly deposited (or tend to be discontinuous). As such, the recess provides a point initially causing voids, which tend to increase electrical resistance and render the line more breakable. This results in a semiconductor device impaired in reliability.

SUMMARY OF THE INVENTION

The present invention contemplates a highly reliable semiconductor device and method of publication thereof.

The present semiconductor device includes a first insulation film, a line provided in the first insulation film, a second insulation film provided on the first insulation film, and a third insulation film provided on the second insulation film. The line or the line and the first insulation film has or have a lower hole, and the second insulation film and the third insulation film have an upper hole communicating with the lower hole, and the lower hole is larger in diameter than the upper hole. The semiconductor device further includes a lower conductive film provided at an internal wall surface of the lower hole, an upper conductive film provided along an internal wall surface of the upper hole, and a conductive film containing copper and filling the upper and lower holes. The lower conductive film contains a substance identical to that of the upper conductive film.

The present method of fabricating a semiconductor device includes the steps of: depositing on a first insulation film having a line formed therein a second insulation film and a third insulation film deposited in layers; providing the second and third insulation films with an upper hole reaching the line or the line and the first insulation film; wet-etching an interior of the upper hole to form in the line a lower hole larger in diameter than the upper hole; depositing an upper conductive film covering an inner wall surface of the upper hole and only a bottom of the lower hole; physically etching the upper conductive film present at the bottom of the lower hole to provide a lower conductive film on an inner wall surface of the lower hole; and depositing a conductive film containing copper and filling the upper and lower holes.

In accordance with the present semiconductor device and its fabrication method even if a lower hole is larger in diameter than an upper hole the lower hole can have an internal wall surface with a lower conductive film thereacross. The lower hole can thus be free of significant voids and the semiconductor device can be increased in reliability.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter the present invention's embodiments will be described with reference to the drawings.

First Embodiment

As shown inFIG. 1, the present embodiment provides a semiconductor device mainly including an interlayer insulation film1serving as a first insulation film, an underlying line5serving as a line, a liner film11serving as a second insulation film, and an interlayer insulation film12serving as a third insulation film. Interlayer insulation film1has a groove2formed therein, and along the groove's internal wall surface and bottom surface, barrier metals3and4are deposited in layers, and trench2is filled with underlying line5deposited on barrier metal4. Underlying line5is covered with liner film1land interlayer insulation film12deposited on interlayer insulation film1in layers. Liner film11serves to prevent Cu contained in underlying line5from diffusing into interlayer insulation film12. Furthermore, it also serves as an etching stopper in forming an upper hole10described later.

Interlayer insulation film12has a trench14. Furthermore, through the interlayer insulation film12trench14and liner film11, upper hole10is provided. Furthermore, underlying line5is provided with a lower hole8. Upper hole10and lower hole8communicate with each other. Lower hole8has a hole6and a dug portion7. Hole6has a semi-circular cross section. Hole6in a vicinity of a border between upper and lower holes10and8, i.e., between liner film11and underlying line5, has a diameter d2larger than a diameter d1of upper hole10. Hole6has a bottom with dug portion7forming a portion of lower hole8. Dug portion7has a diameter d3smaller than the hole6diameter d2and the upper hole10diameter d1. Dug portion7has a bottom7ain the form for example of a cone a hemisphere or the like.

Furthermore in the present embodiment the semiconductor device further includes a conductive film15provided across an internal wall surface of lower hole8and serving as a lower conductive film, a barrier metal13provided along an internal wall surface of upper hole10and serving as an upper conductive film, a Cu film19filling upper and lower holes10and8, and a barrier metal17.

Barrier metal13is provided along an internal wall surface of trench14and that of upper hole10. Barrier metal13interrupts at the border between upper and lower holes10and8. In lower hole8, conductive film15is introduced to cover the entire internal wall surface of lower hole8. Conductive film15is not introduced into dug portion7at bottom7a. Conductive film15contains a substance identical to a substance of barrier metal13and underlying line5. Note that while inFIG. 1conductive film15is also provided in trench14and upper hole10on barrier metal13, conductive film15provided at least across the entire internal wall surface of lower hole8suffices. On conductive film15in trench14and upper and lower holes10and8barrier metal17is deposited and thereon Cu film19is deposited to fill trench14and upper and lower holes10and8. Note that in the present semiconductor device upper hole10has an internal wall surface provided with a layer A (inFIG. 1, barrier metal13, conductive film15and barrier metal17), and dug portions7has an internal wall surface provided with a layer B (inFIG. 1, conductive film15and barrier metal17) and bottom7aprovided with a layer C (inFIG. 1, barrier metal17) such that a relationship A≧B≧C is established in thickness or number.

Note that liner film11is formed for example of SiCN, SiCO, SiC, or the like. Interlayer insulation film12is formed for example of tetra ethyl ortho silicate (TEOS), SiO2, SiOC, or the like. Barrier metal3is formed for example of TaN and barrier metal4and17is formed for example of Ta. Underlying line5is formed for example of Cu. Furthermore, barrier metal13is formed of film of at least one type selected from the group consisting of tantalum nitride, tantalum silicide, tantalum carbide, ttitanium nitride, titanium silicide, titanium carbide, tungsten nitride, tungsten silicide, tungsten carbide, ruthenium (Ru), and ruthenium oxide.

In the present embodiment's semiconductor device, underlying line5is etched to form lower hole8, and conductive films such as Cu film19, barrier metal17and conductive film15are provided in lower hole8. Thus lower hole8is internally provided with a conductive film having a bottom surface and a partial side surface in contact with underlying line5. More specifically, lower hole8is internally provided with a conductive film contacting underlying line5stereoscopically and hence over an increased area. This can alleviate thermal stress and a current otherwise concentrated at a portion at which a surface of underlying line5and a bottom of the conductive film in lower hole8contact each other. This can contribute to reduced voids and the line can be less breakable. Furthermore, it can also reduce electrical resistance between Cu film19and underlying line5.

In the present embodiment the semiconductor device is fabricated in a method as will now be described hereinafter.

With reference toFIG. 2, interlayer insulation film1is provided therein with groove2. Then on interlayer insulation film1and in groove2on an internal wall surface and a bottom surface, chemical vapor deposition (CVD), sputtering or the like is employed to deposit barrier metals3and4in layers. Then to fill groove2and cover interlayer insulation film1, CVD, plating or the like is employed to deposit a conductive film which will serve as underling line5. Then, excessive barrier metal3and4on interlayer insulation film1, and excessive conductive film are chemically mechanically polished and thus removed. Thus underlying line5is provided internal to interlayer insulation film1. Then, underlying line5is covered with liner film11deposited on interlayer insulation film1.

With reference toFIG. 3, on liner film11interlayer insulation film12and an anti-reflective layer (ARL)20are deposited in layers. Then, a patterned resist25ais deposited on anti-reflective layer20and used as a mask for etching anti-reflective layer20and interlayer insulation film12to form a hole10a, which is a portion of upper hole10. Hole10ahas a bottom exposing liner film11.

With reference toFIG. 4, resist25ais removed and thereafter a patterned resist25bis provided on interlayer insulation film12and in hole10a. Then, resist25bis used as a mask for etching anti-reflective layer20and interlayer insulation film12to form trench14.

With reference toFIG. 5, resist25band anti-reflective layer20are removed and thereafter liner film11exposed at the bottom of hole10ais etched away to provide interlayer insulation film12and line film11is provided with upper hole10. Note that liner film11may not be completely be removed in forming upper hole10. Furthermore, liner film11is etched such that underlying line5exposed at the bottom of upper hole10is not etched. Upper hole10thus formed has residue of resist25b, that (or polymer) of liner film11remaining therein. To remove the residues, upper hole10then has its interior wet etched. Furthermore, if necessary, in addition to wet etching, sputter-etching using argon (Ar) gas, a helium (He)—Ar gaseous mixture or the like, annealing performed in an ambient containing hydrogen (H2) of several to 100% (for example at 100° C. to 350° C. for 10 to 180 seconds), a (remote) plasma process, or the like may be performed.

Note that wet etching has a nature allowing a substance to be isotropically etched. As such, when upper hole10is internally wet-etched, together with the residues, underlying line5is also etched and hole6having a semi-circular cross section results. Hole6in a vicinity of a border between liner film11and underlying line5has diameter d2larger than diameter d1of upper hole10. In other words, hole6has an internal wall surface removed to be radially outer than that of upper hole10(inFIG. 5, in the lateral direction).

With reference toFIG. 6, for example sputtering, CVD or the like is employed to provide a conductive film13a, which will serve as barrier metal13, to cover an inner wall surface of upper hole10and only a bottom of hole6. As has been described previously, hole6has an inner wall surface removed to be radially outer than that of upper hole10so that the hole has the inner wall surface free of conductive film13a. Conductive film13ais provided for example by the following method:

Initially a wafer is introduced into a load lock chamber in a CVD apparatus, a sputtering apparatus or similar film deposition apparatus and the chamber is vacuumed. Then in the vacuum the wafer is heated to a temperature of at least 100° C. and at most 400° C. to remove water or the like on a surface of the wafer. Then at −50° C. to −300° C. conductive film13ais deposited to have a thickness of approximately 0.5 nm to 50 nm.

With reference toFIG. 7, conductive film13apresent at a bottom of hole6is physically etched and thus scattered to the hole's internal wall surface to deposit a conductive film15aacross the entirety of the surface (FIG. 9). Conductive film15acontains a substance identical to a substance of conductive film13a. Note that conductive film13amay be scattered to the trench14internal wall surface and upper than interlayer insulation film12to provide conductive film15aon the trench's internal wall surface and over interlayer insulation film12.

Conductive film13ais physically etched for example by sputter-etching using Ar, resputtering using sputter particles by bias sputter, or the like. Preferably, conductive film13ais physically etched under such a condition that the hole6bottom is etched at a rate faster than the trench14and hole6internal wall surfaces are etched. Furthermore, sputtering small in vertical component (or directivity) and the above sputter etching may simultaneously be performed.

With reference toFIG. 8, after conductive film13apresent at the bottom of hole6is completely etched, underlying line5present at the bottom of hole6is physically etched and thus partially scattered toward the hole6internal wall surface to form dug portion7at the bottom of hole6. Conductive film15aprovided across the entire internal wall surface of hole6further contains a substance identical to a substance of underlying line5. Note that underlying line5may partially be scattered to the trench14internal wall surface and upper than interlayer insulation film12to provide conductive film15aon the trench14internal wall surface and over interlayer insulation film12. When conductive film15ais provided on the trench14internal wall surface and over interlayer insulation film12, conductive film13aserves as barrier metal and prevents Cu contained in conductive film15afrom diffusing into liner film11and interlayer insulation film12. Preferably, underlying line5existing at the bottom of hole6is etched at least one fourth or 30 nm in thickness.

With reference toFIG. 9, after the etching, hole6having an internal wall surface removed to be radially outer than that of upper hole10has its internal wall surface entirely filled with conductive film15a. Furthermore, as dug portion7is formed by etching through upper hole10, dug portion7has diameter d3smaller than diameter d1of upper hole10and substantially equal to that of upper hole10provided with conductive film13a. Furthermore, between hole6and dug portion7a step results. Note that a portion closer to an internal wall surface of dug portion7is less exposed to ions and thus less etched. Accordingly, dug portion7has bottom7ain the form for example of a cone, a hemisphere, or the like.

With reference toFIG. 10, for example, sputtering, CVD or the like is employed to deposit a conductive film17a, which will serve as barrier metal17, on conductive film15ato have a thickness of 0.5 nm to 50 nm. Note that conductive film17amay be identical in material to conductive film15a. Then, a seed film of Cu (not shown) is deposited on conductive film17aand a Cu film19ais subsequently deposited to fill trench14and upper and lower holes10and8. Cu film19ais deposited for example by CVD, plating or the like.

With reference toFIG. 1, subsequently on interlayer insulation film12excessive conductive films13a,15a,17aand Cu film19aare chemically mechanically polished and thus removed to provide barrier metal13, conductive film15, barrier metal17and CU film19. Thus the present embodiment's semiconductor device completes.

The present embodiment's semiconductor device includes interlayer insulation film1, underlying line5provided in interlayer insulation film1, liner film11overlying interlayer insulation film1, and interlayer insulation film12overlying liner film11. Underlying line5has lower hole8and liner film11and interlayer insulation film12have upper hole10communicating with lower hole8and lower hole8has diameter d2larger than the upper hole's diameter d1. Furthermore, the semiconductor device includes conductive film15provided on an internal wall surface of lower hole8, barrier metal13provided along an internal wall surface of upper hole10, and Cu film19filling upper and lower holes10and8. Conductive film15contains a substance identical to a substance of barrier metal13.

In the present embodiment the semiconductor device is fabricated in a method including the following steps: On interlayer insulation film1having underlying line5therein liner film11and interlayer insulation film12are deposited in layers. Upper hole10reaching underlying line5is provided through liner film11and interlayer insulation film12. Upper hole10is internally wet etched to form in underlying line5hole6having diameter d2larger than diameter d1of upper hole10. Conductive film13ais provided to cover an internal wall surface of upper hole10and only a bottom of hole6. Conductive film13apresent at the bottom of hole6is physically etched to provide conductive film15on an inner wall surface of lower hole8. Upper and lower holes10and8are filled with Cu film19.

In the present embodiment's semiconductor device and its fabrication method conductive film13apresent at the bottom of hole6can physically be etched and thus provided as conductive film15on an inner wall surface of lower hole8. As such, even if lower hole8has diameter d2larger than diameter d1of upper hole10, lower hole8can have reduced voids, and the semiconductor device can be increased in reliability.

In the present embodiment's semiconductor device conductive film15further contains a substance identical to a substance of underlying line5.

In the present embodiment's semiconductor device and its fabrication method conductive film15is provided by physically etching conductive film13aand underlying line5present at a bottom of hole6.

Thus conductive film13aand underlying line5can be scattered to provide conductive film15having a large thickness on an internal wall surface of lower hole8. This ensures that conductive film15is provided on the internal wall surface of lower hole8if underlying line5is significantly wet etched.

In the present embodiment's semiconductor device conductive film15is not provided in lower hole8at bottom7a. Thus at the lower hole8bottom7aCu film19and underlying line5are provided with barrier metal17alone posed therebetween. As such, reduced electrical resistance can be achieved between Cu film19and lower line5.

In the present embodiment's semiconductor device barrier metal13is a film of at least one selected from the group consisting of tantalum nitride, tantalum silicide, tantalum carbide, titanium nitride, titanium silicide, titanium carbide, tungsten nitride, tungsten silicide, tungsten carbide, ruthenium (Ru), and ruthenium oxide.

Thus barrier metal13can effectively prevent Cu contained in conductive film15, CU film19, and the like from diffusing into liner film11and interlayer insulation film12.

While in the present embodiment in physically etching conducting film13aunderlying line5is also etched, the present invention is not limited thereto, and at least physically etching conductive film13asuffices.

Second Embodiment

With reference toFIG. 11, the present embodiment provides a semiconductor device different from that of the first embodiment of the present invention shown inFIG. 1in that lower hole8has dug portion7penetrating underlying line5. Such structure is obtained by performing physical etching in providing conductive film15a, as shown inFIG. 8, until underlying line5is penetrated.

Other than the above, the semiconductor device's structure and its fabrication method are substantially similar to those of the first embodiment of the present invention shown inFIGS. 1–10. Accordingly, identical components are identically denoted and will not be described.

In the present embodiment the semiconductor device has lower hole8penetrating underlying line5.

In the present embodiment's semiconductor device fabrication method, when conductive film15ais provided, physical etching is performed until underlying line5is penetrated.

A portion at which the lower hole8bottom and underlying line5contact each other causes voids more readily than other portions. The present embodiment's semiconductor device and its fabrication method ensure electrical connection between Cu film19and underlying line5at a portion at which an inner wall of lower hole8and underlying line5contact each other. As such, if the portion at which the lower hole8bottom and underlying line5contact each other has voids, the electrical connection between Cu film19and underlying line5is not affected, and the semiconductor device can thus have high reliability.

Third Embodiment

With reference toFIG. 12, the present embodiment provides a semiconductor device different from that in the first embodiment of the present invention shown inFIG. 1in that lower hole8is located in interlayer insulation film1and underlying line5. Such structure can be obtained in forming upper hole10, as shown inFIG. 5, by forming upper hole10reaching interlayer insulation film1and underlying line5.

Other than the above, the semiconductor device's structure and its fabrication method are substantially similar to those of the first embodiment of the present invention shown inFIGS. 1–10. Accordingly, identical members are identically denoted and will not be described.

In the present embodiment's semiconductor device lower hole8is located in interlayer insulation film1and underlying line5.

In the present embodiment's semiconductor fabrication method upper hole10is provided to reach underlying line5and interlayer insulation film1.

In the semiconductor device fabrication process when upper hole10is provided the hole may be displaced from exactly above underlying line5, as shown inFIG. 12, as resist is displaced or the like. In the present embodiment's semiconductor device and its fabrication method if upper hole10is positionally displaced, a portion at which a conductive film provided in lower hole8and underlying line5contact each other can be ensured. As a result, the semiconductor device's reliability can be increased and electrical resistance between Cu film19and underlying line5can be reduced.

While in the first to third embodiments hole6has diameter d2significantly larger than diameter d1of upper hole10, the present semiconductor device may have hole6with diameter d2slightly larger than diameter d1of upper hole10, as shown inFIG. 13.

Fourth Embodiment

With reference toFIG. 14, the present embodiment provides a semiconductor device different from that of the first embodiment, as follows: more specifically, Cu film19is covered with a liner film111deposited on interlayer insulation film12and on liner film111an interlayer insulation film112is deposited. Interlayer insulation film112has an upper portion with a trench114and in trench114and liner film111a hole110is provided to reach an upper surface29of an underlying line5a. A barrier metal113is provided along an internal wall surface and a bottom of trench114and those of hole110. Trench114and hole110are filled with a Cu film119.

Cu film19, barrier metal17, and conductive film15introduced into upper and lower holes10and8form a contact9a, and Cu film19introduced into trench14forms underlying line5a(a second line). Furthermore, Cu film119(a connection layer) filling hole110(a hole for the second line) forms a contact9b, and Cu film119filling trench114forms a line5b. In other words, in the present embodiment, underlying line5followed by line5aand then line5bare sequentially deposited in layers each with insulation film posed therebetween, and underlying line5and line5aare electrically connected by contact9aand lines5aand5bare electrically connected by contact9b.

Note that contacts9aand9bare structurally different. Of upper and lower holes10and8having contact9atherein, lower hole8is located in underlying line5. By contrast, hole110having contact9btherein does not extend into line5aand instead stops at upper surface29of line5a. Furthermore, hole110having contact9btherein has a diameter d101larger than diameter d1of hole10having contact9atherein.

The present embodiment's semiconductor device includes line5a, hole110reaching line5aat the top, and Cu film119filling hole110. Hole110does not extend into line5a.

The present embodiment's semiconductor device is effective as follows: a contact large in diameter contacts an underlying line over a large area. As such, it provides a small current density and hardly provides a point initially causing voids in comparison with other contacts. As such, if the contact large in diameter is modified to have such a simple structure as contact9b, the semiconductor device can still be ensured in reliability. For contact9b, it is unnecessary to etch line5aand form a lower hole communicating with hole110, and the semiconductor device can be fabricated in a simplified process and hence at reduced cost.

Furthermore in the present embodiment's semiconductor device hole110can have diameter d101larger than diameter d1of upper hole10. As such, if contacts9aand9bpass a current of a single magnitude, contact9bproviding a smaller current density can be simplified in structure.

Furthermore in the present embodiment's semiconductor device hole110overlies upper hole10. Normally, an overlying contact provides a smaller current density than an underlying contact, and contact9bprovided in the overlying hole110can be simplified in structure.

Note that the hole may not be filled with Cu layer19and119and instead be filled with a layer of silver (Ag), a layer of an alloy containing Cu and Ag as a main component, or the like.

Fifth Embodiment

With reference toFIG. 15, the present embodiment provides a semiconductor device including a large number of lines35a–35fand contacts39a–39eelectrically connecting lines35a–35fOn line35a, line35bis deposited, followed by line35c,35d,35e,35f, sequentially in layers each with an insulation layer posed therebetween. Lines35aand35bare electrically connected by contact39a. Lines35band35care electrically connected by contact39b. Lines35cand35dare electrically connected by contact39c. Lines35dand35eare electrically connected by contact39d. Line35eand35fare electrically connected by contact39e.

Contacts39a–39eeach have a diameter A or a diameter C. Contacts39a–39ceach have diameter A. Contacts39dand39eeach have diameter C. Diameter C is larger than diameter A.

In the present embodiment, a contact substantially similar in geometry to theFIG. 14contact9aand a contact substantially similar in geometry to theFIG. 14contact9bare mixed together. More specifically, of contacts39a–39e, contacts39a–39chaving diameter A are each substantially similar in geometry to contact9a, and contacts39dand39ehaving diameter C are each substantially similar in geometry to contact9b.

Furthermore, with reference toFIG. 16, contacts39a–39eeach have diameter A, a diameter B, or diameter C. Contacts39aand39beach have diameter A. Contact39chas diameter B. Contacts39dand39each have diameter C. Diameter C is larger than diameter B, and diameter B is larger than diameter A.

In theFIG. 16structure, of contacts39a–39e, contacts39a–39chaving diameters A and B are each substantially similar in geometry to contact9a, and contacts39dand39ehaving diameter C are each substantially similar in geometry to contact9b.

Furthermore, of contacts39a–39e, contacts39aand39bhaving diameter A may each be substantially similar in geometry to contact9a, and contacts39c–39ehaving diameters B and C may each be substantially similar in geometry to contact9b.

Except for the above arrangement, the semiconductor device has a structure substantially similar to that of theFIG. 15semiconductor device. Accordingly, identical members are identically denoted and will not be described.

As provided in the present embodiment's semiconductor device, if a large number of contacts39a–39eare provided, each contact having a relatively small diameter can be formed in a geometry substantially similar to contact9aand each contact having a relatively large diameter can be formed in a geometry substantially similar to contact9bso that as well as in the fifth embodiment, the semiconductor device can be ensured in reliability and also be fabricated at reduced cost.

WhileFIG. 15shows contact39a–39chaving diameter A that have a geometry substantially similar to contact9a, of the contacts having diameter A the lowermost layer's contact39aalone may be formed to have a geometry substantially similar to contact9b.

Furthermore while in the present embodiment a contact having a relatively small diameter underlies that having a relatively large diameter, they may be provided at any position.

Sixth Embodiment

With reference toFIG. 17, contacts39a–39ehave diameter A or C. Contacts39a–39ceach have diameter A and contacts39dand39eeach have diameter C. Diameter C is larger than diameter A.

In the present embodiment contacts39aand39beach passes a current larger in amount than that contact39cdoes. As such, even though contacts39a–39chave the same diameter A, contacts39aand39beach provide a current density larger than contact39c. Similarly, as contact39dpasses a current larger in amount than contact39e, contact39dprovides a current density larger than contact39edespite that contacts39dand39ehave the same diameter C.

Accordingly, of contacts39a–39e, contacts39a,39band39dproviding a relatively large current density are each adapted to be substantially similar in geometry to contact9a, whereas contacts39cand39eproviding a relatively small current density are each adapted to be substantially similar in geometry to contact9b.

Except for the above arrangement, the semiconductor device is substantially similar to that shown inFIG. 15, and identical members are identically denoted and will not be described.

In a semiconductor device having a large number of lines a current density varies for each contact, and for a contact with a large current density voids are caused more readily than for a contact with a small current density. As such, a line readily breaks. As such if the contact with relatively small current density is formed to have such a simple structure as contact9b, the semiconductor device is still ensured in reliability. Thus for the contact with relatively small current density a simplified fabrication process can be adopted, and the semiconductor device can be fabricated at reduced cost.

FIRST EXAMPLE

Hereinafter one example of the present invention will be described.

In the present example, a conventional semiconductor device and the present semiconductor device were compared in reliability. More specifically, a conventional semiconductor device having a via hole formed without etching an underlying line and the present semiconductor device shown inFIG. 1were compared in longevity.FIG. 8shows a result thereof For the conventional semiconductor device, a group of black dots and that of white dots, as shown inFIG. 18, were compared in longevity. A square indicates the present semiconductor device.

As shown inFIG. 18, approximately 50–60% of the entire samples of the conventional semiconductor device had electromigration (EM), stress migration (SM) or similar defect within 10n+1hours, and were found to be defective products. In contrast, it can be seen that the present semiconductor device hardly provided defective product even after 10n+1hours. It can be understood therefrom that the present semiconductor device can alleviate thermal stress and a current otherwise concentrated at a portion at which a surface of underlying line5and a bottom of a conductive film provided in lower hole8contact each other, and that the semiconductor device can be increased in reliability.