Method and circuit for driving a stepping motor

A method and circuit for driving a stepping motor which is driven by a motor clock output having a time variable frequency. So as to generate the time varying frequency, the constant frequency of a basic clock output is divided by constant first factor and is multiplied by a time variable second factor which is in the range between zero and the first factor. A transfer clock sequence is derived from the basic clock output by a division factor. The second factor is changed by a prescribed increment with the frequency of the transfer clock output at the respective clock times and this prescribed increment determines the frequency change of the motor clock output per clock interval. In this manner, the unavoidable frequency discontinuities can be maintained small and constant over the full frequency range of the motor clock output even by when the frequency of the basic clock output is not high whereby a reliable run-up and a reliable braking of the stepping motor are assured without stepping errors.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
This invention relates in general to drive and control technology for 
stepping motors and particularly relates to generating a motor clock 
output with a variable frequency for driving stepping motors during 
individual operating phases. 
2. Description of the Prior Art 
Circuit arrangements for driving stepping motors usually comprise a clock 
generator, a control stage and a motor amplifier. The clock generator 
generates the motor clock output with the desired motor frequency. 
Switching pulses cyclically following one another with the motor frequency 
are derived in the control stage from the motor clock's output. The motor 
amplifier comprises a DC voltage source and switches controlled by the 
switching pulses and these switches are connected to the DC voltage source 
and to the stator windings of the stepping motor. As a result of the 
cyclical supplying by the switches of the motor frequency, the rotary 
field for the rotor of the stepping motor is generated and the speed of 
stepping is dependent on the motor frequency. 
A stepping motor has a limiting frequency dependent upon the coupled load 
at which it no longer starts up without stepping errors on the basis of 
merely switching the motor clock input on and in which it no longer comes 
to a standstill with step precision by switching the motor clock output 
off. So as to avoid stepping errors particularly at high stepping 
frequencies, the stepping motor in a run-up phase having a rising motor 
frequency is thereby pulled up to the desired operating frequency from a 
low starting frequency and is subsequently stopped with step precision in 
a following deceleration phase by lowering the motor frequency. 
The clock generator must therefore supply a motor clock output which has a 
frequency chronologically variable during run-up and during the 
decelerating phases and is constant in the work phase. So as to generate a 
motor clock sequence with a chronologically variable frequency a 
traditional clock generator is formed with, for example, frequency voltage 
transformers wherein the chronological frequency curve is dependent on a 
control voltage. The employment of frequency-to-voltage transformers, 
however, has the disadvantage in that the curve of the control voltage 
must be simulated by timing elements, for example, by charging and 
discharging capacitors and these are used especially when different 
frequency curves must be available. It is also relatively difficult to 
hold the control voltage constant during the work phase and to synchronize 
it with other control parameters during the run-up and decelerating 
phases. 
Another type of apparatus for generating a motor clock output with a 
variable motor frequency is disclosed in German A No. 22 38 613 wherein 
the clock generator is composed of a clock generator that generates a 
basic clock output having a constant basic frequency and also includes a 
following frequency divider stage constructed of individual flipflops in 
which the required motor frequency is acquired from the basic frequency of 
the basic clock output by frequency division. The variable motor frequency 
is generated by means of chronologically varying the division factor for 
example with the assistance of timing elements. 
German C No. 27 21 240 discloses another clock generator comprising a clock 
generator and frequency divider stage. The required division factors are 
prescribed therein as data words which are deposited in a read-only memory 
as a program sequence and are output dependent on the executed steps of 
the stepping motor in order to operate the stepping motor with optimum 
load angle. 
In the known clock generators having traditionally constructed frequency 
divider stages, disturbing frequency discontinuities occur during 
step-by-step switching of the frequency divider stages and these 
discontinuities are especially great and disturbing when small division 
factors are used. There is a risk that the stepping motor will make step 
errors or even fall out of step as a consequence of these frequency 
discontinuities. 
However, small division factors always occur when high motor frequencies 
approaching the constant basic frequency are required. Also, the torque of 
the stepping motor decreases with increasing motor frequency whereby the 
risk of step errors or of falling out of step increases when frequency 
discontinuities occur. For this reason, the division factors for the 
highest motor frequency should be as large as possible so that the 
disturbing frequency discontinuities remain small. In order to meet this 
requirement, a basic clock sequence having an extremely high basic 
frequency must be generated and this is realizable only with high 
technology devices. 
SUMMARY OF THE INVENTION 
It is an object of the present invention to provide a method and circuit 
arrangement for driving a stepping motor in which fundamentally 
unavoidable frequency discontinuities can be kept small over the full 
frequency range of the motor clock output even for not high basic 
frequencies and with which a reliable run-up and a reliable deceleration 
of the stepping motor without step errors is assured. 
It is a feature of the present invention to provide a method for driving a 
stepping motor by a motor clock output having a time variable frequency 
which is obtained by dividing the constant frequency of a basic clock 
output using a time variable factor wherein for generating the time 
variable frequency, the frequency of the basic clock output is divided by 
a constant first factor and is multiplied by a time variable second factor 
and a transfer clock output is derived from the basic clock output by 
dividing the frequency of the basic clock output by a division factor and 
said second factor has the frequency of the transfer clock output and is 
respectively varied by a prescribed increment. 
Other objects, features and advantages of the invention will be readily 
apparent from the following description of certain preferred embodiments 
thereof, taken in conjunction with the accompanying drawings although 
variations and modifications may be effected without departing from the 
spirit and scope of the novel concepts of the disclosure and in which:

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
FIG. 1 is a block schematic diagram of the driving arrangement of a 
stepping motor according to the prior art. A clock generator 1 produces a 
clock output and supplies it to lead 6 which is connected to a frequency 
reduction stage 2. The output of the frequency reduction stage is supplied 
on lead 7 to a motor control stage 3 and the output of the motor control 
stage is connected to a motor amplifier 4 which is connected to the 
stepping motor 5. 
The clock generator 1 produces a basic clock output T.sub.0 having a 
constant basic frequency of f.sub.0 which is supplied to the frequency 
reduction stage through the line 6. In the frequency reduction stage 2, a 
motor clock output T.sub.m having a motor frequency f.sub.m is supplied to 
the motor control stage 3 by way of line 7 and has been formed from the 
basic clock output T.sub.0 with the constant basic frequency f.sub.0 by 
frequency division. By using ring counter cyclically successive switch 
pulses T.sub.s1 through T.sub.s4 are supplied to the motor amplifier 4 
through lines 8 and these are obtained from the motor clock output T.sub.m 
having the motor frequency f.sub.m and are generated in the motor control 
stage 3. The motor amplifier 4 is composed of a connectible and 
disconnectible DC voltage source 9 for generating the motor currents and 
also includes electronic switches 10 and 11 which are actuated by the 
switch pulses T.sub.s1 through T.sub.s4. The stepping motor 5 has a rotor 
12 and a stator which has at its circumference stator windings 13 and 14. 
The rotor 12 is composed of permanent magnets which are fashioned so as to 
form pole pairs. The switches 10 and 11 are connected to the DC voltage 
source 9 as well as to the stator windings 13 and 14 of the stepping motor 
5. The switches 10 and 11 are switched by the switch pulses T.sub.s1 
through T.sub.s4 and are cyclically switched at the motor frequency 
f.sub.m so as to generate the rotary field for the rotor 12. The speed of 
the rotor 12 or of the stepping motor 5 is therefore dependent on the 
motor frequency f.sub.m as well as on the number of pole pairs of the 
stepping motor 5. 
A pair of keys 15a and 15b is connected to the frequency reduction stage 2 
and an operator can by using the keys forward a start command to the 
frequency reduction stage 2 at the beginning of the run-up phase of the 
stepping motor 5 and can also supply a stop command at the beginning of 
the braking phase. Corresponding control commands are generated in the 
frequency reduction stage 2 and these control commands are supplied to the 
motor amplifier 4 by way of lines 16 and correspondingly switch the DC 
voltage source 9 on and off, although this is not shown in greater detail 
since such structure is well known to those skilled in the art. 
For a more detailed structure and the manner of functioning of motor 
control stage 3, motor amplifier 4 and stepping motor 5 reference may be 
made to the article "Positionierungen fur Schrittmotoren" appearing in the 
periodical "Elektronik", Vol. 55, No. 7 of Apr. 5, 1973, pages 18-22 and 
these components are well known to those skilled in the art. 
The subject matter of the invention relates to generating of a motor clock 
output T.sub.m having a time dependent motor frequency f.sub.m (t), also 
referred to as a frequency ramp for the control of the stepping motor 5 in 
the individual operating phases. For this purpose, a rising motor 
frequency is required during the run-up phase, a constant motor frequency 
is required during the work phase and a descending motor frequency is 
required during the braking phase. 
The motor clock sequence T.sub.m having the time dependent motor frequency 
f.sub.m (t) is produced in the frequency reduction stage 2. 
FIG. 2 shows the structure of the frequency reduction stage 2 of the 
invention and which is connected in the circuit of FIG. 1. The frequency 
reduction stage 2 comprises a main frequency divider stage 17 which is 
connected to an accumulator stage 18 and also includes an auxiliary 
frequency divider stage 19 and a further accumulator stage 20 as well as a 
control stage 21. 
The main frequency divider stage 17 is composed of a frequency reducer 22 
which receives an input 23 from the clock generator 6 and produces the 
output T.sub.mi at a frequency of f.sub.m on the lead 7 which is connected 
to the motor control stage 3. A programming input 25 is supplied to the 
frequency reducer 22 from a memory register 26. 
The frequency reducer 22 is constructed according to the invention such 
that the output frequency f.sub.out supplied to the output 24 is formed by 
multiplication of the input frequency f.sub.in supplied to the input 23 by 
a multiplication factor q.sub.m according to equation 1. 
EQU f.sub.out =f.sub.in .multidot.q.sub.m (1) 
The multiplication factor q.sub.m is stored in the memory register 26 and 
is supplied to the programming input 25 of the frequency reducer 22 
through a data bus. The frequency reducer 22 preferably comprises a 
six-bit binary rate multiplier of the types SN7497 available from Texas 
Instruments Company. All of the modules are commercially available and are 
known to a person skilled in the art so a detailed description of their 
structure and function is not required. 
The module type SN7497 additionally has an internal constant division 
factor q.sub.k, so that the relationship of equation (2) is valid between 
the output frequency f.sub.out, and the input frequency f.sub.in, and the 
internal division factor q.sub.k and the multiplication factor q.sub.m 
whereby 0.ltoreq.q.sub.m .ltoreq.q.sub.k. 
EQU f.sub.out =f.sub.in (q.sub.m /q.sub.k) (2) 
The multiplication factor q.sub.m is prescribable as a 6-bit word, so that 
the multiplication factors from 0 to 63 can be realized with a module. So 
as to obtain greater multiplication factors, a corresponding plurality of 
such modules are connected in cascade. Of course, the frequency reducer 22 
can also be comprised of individual commercially available component 
parts. 
The basic clock output T.sub.0 having the basic frequency f.sub.0 is 
supplied to the input 23 of the frequency reducer 22 from the clock 
generator 1 through the line 6 and the motor clock output T.sub.m having a 
motor frequency f.sub.m occurs at the output 24 which is supplied by line 
7 to the motor control stage 3 as shown. 
The frequency level at which the frequency division occurs in the frequency 
reducer 22 between the basic frequency f.sub.0 and the motor frequency 
f.sub.m can be freely selected and can thus be adapted to the requirements 
in that additional frequency dividers 117 are connected between the clock 
generator 1 and the frequency reduction stage 2 and/or between frequency 
reduction stage 2 and the motor control stage 3. 
With f.sub.in =f.sub.0, f.sub.out =f.sub.m (t) and with q.sub.m as a 
time-dependent multiplication factor q.sub.m (t), the equation (3) is 
obtained: 
EQU f.sub.m (t)=(f.sub.0 /q.sub.k).multidot.q.sub.m (t) (3) 
and with f.sub.0 /q.sub.k =f'.sub.0, 
EQU f.sub.m (t)=f'.sub.0 q.sub.m (t) (4) 
According to equation (4), the motor frequency f.sub.m (t) is directly 
proportional to the multiplication factors q.sub.m (t), so the rising 
multiplication factor q.sub.m (t) must be used during the run-up phase and 
a constant multiplication factor q.sub.ma corresponding to the work motor 
frequency must be utilized during the work phase and a descending 
multiplication factor q.sub.m must be utilized during the braking phase. 
The corresponding multiplication factors q.sub.m (t) are generated in the 
accumulator stage 18 and are transferred into the memory register 26 of 
the main frequency divider stage 17 with a data bus 27 and are 
respectively transferred with clock pulses n of a transfer clock sequent 
T.sub.u of the transfer frequency f.sub.u. The transfer clock sequence 
T.sub.u is supplied to the memory register 26 and to the accumulator stage 
18 for synchronization purposes through a line 28. 
The clock times t.sub.n of the transfer clock sequence T.sub.u thus 
determine the time at which the multiplication factor q.sub.m (t) and, 
thus, the motor frequency f.sub.m (t) changes. 
The multiplication factors q.sub.m (t) are formed in the individual 
operating phases of the stepping motor according to Equation 5. 
EQU In the run-up phase: q.sub.m (t)=q.sub.m0 +n.multidot..DELTA.q.sub.m (5a) 
EQU In the work phase: q.sub.m (t)=q.sub.m =const. (5b) 
EQU In the braking phase: q.sub.m (t)=q.sub.ma -n.multidot..DELTA.q.sub.m (5c) 
In equation 5, "q.sub.mo " is a prescribable constant part which as shall 
be later shown determines the starting motor frequency f.sub.mo during the 
run-up phase and "n.DELTA.q.sub.m " is a part dependent on time. 
".DELTA.q.sub.m " represents a prescribable change amount of the 
multiplication factor q.sub.m (t) in the time interval .DELTA..sub.t 
between two successive clock pulses n of the transfer clock sequence 
T.sub.u which as shall be later shown defines the slope of the frequency 
ramp f.sub.m (t). The parameters "q.sub.mo " and ".DELTA.q.sub.m " are 
digitally input into the accumulator stage 18 by coding switches 29 and 30 
while the accumulator stage 18 is switched over with a control line 31 to 
addition (Equation 5a) or subtraction (Equation 5c). A computer can also 
replace the coding switches 29 and 30 for the manual input of the 
parameters and this computer will calculate the required parameters based 
on the required operating conditions for the stepping motor 5. 
The transfer clock sequence T.sub.u is obtained from the basic clock output 
T.sub.0 in the auxiliary frequency reduction stage 19 and is derived by 
means of a traditional frequency division with the division factor 
q.sub.u. 
The auxiliary frequency reduction stage 19 comprises a normal frequency 
divider 32 which may be, for example a type SN7493 and has an input 33 
connected to the output of the clock 1 and produces an output 34 and 
receives a programming input 35 for the division factor q.sub.u from a 
memory register 36 which may be a type SN74174 and which is connected to 
the programming input 35. 
The basic clock output T.sub.0 is supplied to the input 33 of the frequency 
divider 32 from line 6 and the transfer clock output T.sub.u having the 
transfer frequency f.sub.u occurs at the output 34 of frequency divider 32 
wherein the relationship of Equation 6 applies. 
EQU f.sub.u =(f.sub.0 /q.sub.u) (6) 
The transfer frequency f.sub.u can be generated and maintained constant 
where q.sub.u =constant or can be generated so as to ascend or descend as 
a function of time where q.sub.u is time-dependent so as shall be shown 
hereafter to generate different curves for the frequency ramp f.sub.m (t). 
The division factors q.sub.u are formed in the accumulator stage 20 
according to Equation 7. 
For a time-dependent transfer frequency: 
EQU q.sub.u (t)=q.sub.u0 .+-.n.DELTA.q.sub.u (7a) 
For a constant transfer frequency: 
EQU q.sub.u =q.sub.uo =const. (7b) 
The values "q.sub.u0 " and ".DELTA..sub.q u" are supplied to the 
accumulator stage 20 from coding switches 37 and 38 and the instruction 
for addition or for subtraction is input into the accumulator stage from a 
further coding switch 39. However, the accumulator stage 18 can also be 
switched from addition to subtraction or vice versa by corresponding 
control instructions from the control stage 21 through a control line 40 
shown in dashed line in FIG. 2. 
The accumulator stage 20 is synchronized with the transfer clock output 
T.sub.u by a line 41'. The division factors q.sub.u (t) generated in the 
accumulator stage 20 are transferred into the memory register 36 and are 
respectively transferred by the clock of the transfer clock pulses T.sub.u 
supplied on line 41'. In case a constant division factor q.sub.u and, 
thus, a constant transfer frequency f.sub.u are to be generated, the 
accumulator stage is stopped. The accumulator stages 18 and 20 are 
preferably constructed of modules which may be type SN545482. 
The following relationships for the operating phases of the stepping motor 
5 between the motor frequency f.sub.m (t), the multiplication factor 
q.sub.m (t) and the transfer frequency f.sub.u or respectively, the 
division factor q.sub.u are obtained whereby a distinction is made between 
a constant q.sub.u and a time dependent q.sub.u (t). 
For that purpose, FIG. 3 illustrates the typical curve of the motor 
frequency f.sub.m (t) in the individual operation phases of the stepping 
motor 5 whereby a linear frequency change or frequency ramp is assumed. At 
time t.sub.s, the start instruction for run-up of the stepping motor 5 is 
shown. The run-up phase is identified by the time interval t.sub.s through 
t.sub.a in which the motor frequency f.sub.m linearly rises up to the 
working frequency f.sub.ma which corresponds to the desired speed of the 
stepping motor 5. In the working phase of the stepping motor during the 
time interval t.sub.a through t.sub.b the working frequency f.sub.ma 
remains constant. At time t.sub.b, the stop instruction is given. This is 
followed by the braking phase during the time interval t.sub.b through 
t.sub.e during which the stepping motor is decelerated by a linearly 
descending motor frequency f.sub.m down to stop at point t.sub.e. 
Run-up Phase t.sub.s through t.sub.a 
In the run-up phase, the multiplication factor q.sub.m (t) according to 
Equation 5a occurs at the individual clock time t.sub.n of the transfer 
clock sequence T.sub.u as follows: 
##EQU1## 
According to Equation 3, the motor frequency f.sub.mn is generally: 
EQU f.sub.mn =f'.sub.0 (q.sub.m0 +n.DELTA.q.sub.m) (9) 
The starting motor frequency f.sub.ms at time t.sub.s =t.sub.o of the 
beginning of run-up is derived from Equation 4: 
EQU f.sub.ms =f'.sub.0 .multidot.q.sub.m0 (10) 
The starting motor frequency f.sub.ms can thus be prescribed by the term 
"q.sub.m0 " which is set by the coding switch 29. 
At time t.sub.a of the end of run-up, the motor frequency is then equal to 
the working motor frequency f.sub.ma : 
EQU f.sub.ma =f'.sub.0 q.sub.ma with q.sub.ma =q.sub.mo +n.DELTA.q.sub.m (11) 
The curve of the motor frequency f.sub.m (t) between the starting motor 
frequency f.sub.ms and the working motor frequency f.sub.ma can be linear 
or curved. 
Case (a) Linear Frequency Ramp f.sub.m (t) 
The division factor q.sub.u =q.sub.u is constant (n.DELTA.q.sub.u =0) and, 
thus so is the transfer frequency f.sub.u. The clock pulses of the 
transfer clock output T.sub.u are equidistant (.DELTA.t=constant). 
The frequency change f.sub.m between two clocks of the transfer clock 
output T.sub.u during the time interval .DELTA.t is then: 
EQU .DELTA.f.sub.m =f'.sub.0 .DELTA.q.sub.m =constant (12) 
and the slope S or, respectively, the gradient of the frequency change is: 
##EQU2## 
With a constant division factor q.sub.u for the transfer clock sequence 
T.sub.u, thus, a motor frequency f.sub.m rising linearly with time is 
generated whereby the steepness S according to Equation 13 is prescribed 
by the quantity ".DELTA.q.sub.m " which can be set with the coding switch 
30 and/or by variation of the time interval .DELTA.t with the assitance of 
the division factor q.sub.u. 
FIG. 4 is a graphic illustration of the linearly ascending curve of the 
motor frequency f.sub.m (linear frequency ramp) during the run-up phase 
from the starting time t.sub.s up to the time t.sub.a at which the work 
phase begins. 
Case (b) Curved Frequency Ramp f.sub.m (t) 
According to Equation 4, the division fact q.sub.u is time-dependent 
(n.DELTA.q.sub.u .noteq.0) and, thus, so is the transfer frequency 
f.sub.u. 
The clock pulses of the transfer clock output T.sub.u are no longer 
equidistant. 
In this case, the time difference .DELTA.t between two clock pulses of the 
transfer clock output T.sub.u and the steepness S.sub.n of the motor 
frequency change are no longer constant but change with time according to 
Equation 14 and 15. 
##EQU3## 
The deriving from Equation 15, the starting steepness S.sub.1 at time 
t.sub.1 and the final steepness S.sub.n+1 at time S.sub.n+1 : 
##EQU4## 
With the assistance of a time-dependent division factor q.sub.u (t), thus, 
a curved path of the motor frequency f.sub.m (t) or, respectively, a curve 
frequency ramp can be achieved whereby the quantity .DELTA.q.sub.u 
determines the path of the curvature. The curves 5a through 5c show 
various examples. FIG. 5a shows a curved frequency ramp f.sub.m (t) which 
has a steepness which decreases slowly due to the selection of a small 
positive value .DELTA.q.sub.u, whereas the steepness of the frequency ramp 
f.sub.m (t) illustrated in FIG. 5b decreases quickly due to the selection 
of a large positive value .DELTA.q.sub.u. 
When by contrast, a negative value .DELTA.q.sub.u is selected, then, 
according to FIG. 5c a frequency ramp f.sub.m (t) which has a steepness 
that increases with time is generated. 
By means of an expedient selection of the various parameters, the curve of 
the ramp function f.sub.m (t) can be varied within broad limits in this 
manner and, thus, can be optimally matched to the properties of the 
stepping motor and/or of the connected load in an advantageous way. 
Work Phase t.sub.a through t.sub.b 
During the work phase, the working motor frequency f.sub.ma reached at the 
end of the run-up time t.sub.a is held constant up to the beginning of the 
braking at time t.sub.b by means of a constant multiplication factor 
q.sub.ma according to the equations 4 and 5b. 
EQU f.sub.ma =f'.sub.o .multidot.q.sub.ma (18) 
Braking Phase t.sub.b through t.sub.e 
Proceeding from the multiplication factor q.sub.ma, the multiplication 
factor q.sub.m (t) during the braking phase decreases at the individual 
clock time t'.sub.n of the transfer clock T.sub.u according to Equation 5c 
in the following manner: 
##EQU5## 
and the motor frequency f.sub.m (t) then decreases according to Equation 4 
until the stepping motor has come to a standstill at time t.sub.e. 
EQU f.sub.mn =f'.sub.0 (q.sub.ma -n.DELTA.q.sub.m) (20) 
The generating of the motor clock output T.sub.m with variable motor 
frequency f.sub.m has been explained and the control of the stepping motor 
5 in the individual operating phases by the control stage 21 will now be 
set forth in greater detail. 
The control stage 21 includes an AND gate 41 which is connected to lead 41' 
and switching flipflops 42 and 43 are provided which are connected to a 
bidirectional counter 44. The bidirectional counter 44 provides an output 
on bus 54 which is connected to a comparator 45 which is connected to a 
coding switch 46 and an OR gate 47 is connected to the AND gate 41 and has 
input leads 51 and 58. 
Before the stepping motor 5 is placed in operation, the required parameters 
"q.sub.m0 ", ".DELTA.q.sub.m ", "q.sub.u0 " and ".DELTA.q.sub.u " are set 
at the coding switches 29, 30, 37 and 38 and the corresponding operational 
sign is set at the coding switch 39 and are input into the accumulator 
stages 18 and 20. The plurality of clock pulses of the transfer clock 
output T.sub.u required for the run-up of the stepping motor 5 to the 
working motor frequency f.sub.ma is also preset at the coding switch 46 in 
the control stage 21. The plurality n of clock pulses is given by the 
quotient of the difference between the working motor frequency f.sub.ma 
and the starting frequency f.sub.ms and the set frequency change 
.DELTA.f.sub.m per transfer clock whereby n.multidot..DELTA.f.sub.m is a 
measure for the motor frequency reached at the present time. During the 
individual operating phases of the stepping motor 5, the functioning of 
the control stage 21 is as follows according to the graphic illustration 
in FIG. 3. 
Run-Up Phase 
For initiating the run-up, the start key 15a is pressed whereby the Q 
output 49 of the switching flipflop 42 is set to a H level as the control 
instruction "Start of Run-Up". This control instruction "Start of Run-Up" 
triggers various events. Through the control line 31 the accumulator stage 
18 is switched to "run-up", in other words, to addition mode according to 
Equation 5a. Through the control 50, the bidirection counter 44 is 
switched to forward counting mode by the control instruction. 
Simultaneously, the control instruction "Start of Run-Up" is forwarded by 
way of control line 51 and the OR gate 47 to an input 2 of the AND gate 41 
so that the AND gate 41 opens and the transfer clock output T.sub.u is 
connected through. 
Also, the motor control stage 4 illustrated in FIG. 1 is started by way of 
the control line 16. The transfer clock sequence T.sub.u enabled by the 
AND gate 41 now controls the transfer of the division factor q.sub.m 
generated in the accumulator stage according to Equation 5a into the 
memory register 26 of the main frequency divider stage 17. At the same 
time, the enable transfer clock output T.sub.u is counted into the 
bidirectional counter 44 through the clock input 53 and is counted there 
for the identification of the momentarily reached motor frequency 
n.multidot..DELTA.f.sub.m after the starting time t.sub.s. The current 
plurality of clock pulses counted into the bidirectional counter 44 is 
continuously compared to the plurality preset at the coding switch 46 for 
which purpose the comparator 45 is connected to the data outputs 54 of the 
bidirectional counter 44 and to the coding switch 46. Given equality at 
the end of the run-up phase at time t.sub.b at which the working motor 
frequency f.sub.ma is reached, the comparator 45 emits a control 
instruction "end of run-up" at a signal output 55 which resets the 
switching flipflop 42 through line 56. The Q output 49 of the switching 
flipflop 42 assumes the L level and this corresponds to a control 
instruction "end of run-up". This control instruction "end of run-up" 
switches the OR gate 47 and the input 52 of the AND gate 41 off through 
the line 51. As a result, the transfer clock sequence is disconnected and 
the transfer of new multiplication factors q.sub.m into the memory 
register 26 is stopped. Thus, the multiplication factor q.sub.ma according 
to Equation 5b is held constant for the duration of the work phase of the 
stepping motor 5. Due to the disconnect of the transfer clock sequence 
T.sub.u also the counter reading in the bidirectional counter 44 is frozen 
for the duration of the work phase. The control instruction "end of 
run-up" and preparation for the braking phase also switches the 
accumulator stage 18 to the subtraction mode according to Equation 5c 
through line 31 and switches the bidirectional counter over to backward 
counting mode through the line 50. 
Braking Phase 
For the initiation of the braking phase (time t.sub.b) the stop key 15b is 
pressed and the switching flipflop 43 is set. The Q output 57 of the 
switching flipflop 43 assumes the H level in accord with a control 
instruction "start of braking". Through a line 58 and the OR gate 47, the 
control instruction "Start of Braking" proceeds to the switching input 52 
of the AND gate 41. The AND gate 41 is switched and the transfer clock 
sequence T.sub.u is again enabled. According to the set subtraction mode, 
multiplication factors q.sub.m decreasing with time are now generated in 
the accumulator stage 18 according to Equation 5c and are transferred into 
the memory register 26. A frequency ramp having a decreasing motor 
frequency f.sub.m is thereby acquired. Simultaneously, the counter reading 
in the bidirection counter 44 is also deincremented by the enable transfer 
clock sequence T.sub.u until the counter reading becomes zero at the end 
of the braking phase at time t.sub.e and the bidirectional counter 44 
emits a control instruction "end of braking" at its signal output 59. The 
control instruction "end of braking" resets the switching flipflop 43 
through line 41 whereby the AND gate 41 is turned off. At the same time, 
the control instruction "end of braking" also switches the motor stage off 
through line 16. 
In most applications, the frequency ramp of the braking phase will be a 
mirror image of the frequency ramp of the run-up phase, in other words, 
both frequency ramps will, for example, have a linear curve with the same 
slope or gradient so that run-up phase and braking phase are of equal 
length. It is also within the framework of the invention to select 
different curves for the frequency ramps during the run-up phase and the 
braking phase. For example, the two frequency ramps can proceed linearly 
but with different slopes. In this case, respectively, two different 
parameters "q.sub.mo" and "q.sub.m " are input into the accumulator stage 
18 with the use of the coding switches 29 and 30 and switching with the 
control instruction on the line 31 is correspondingly carried out. It is 
just as possible however, that one portion of the frequency ramp can be 
linear and the other portion curved or that the two frequency ramps can 
have different curvatures for which purposes the parameter set in the 
accumulator stage 20 with the coding switches 37, 38 and 39 can be 
switched over with a control instruction on line 40 that can be switced on 
and off using a switch 61. 
It is seen that the invention provides an improved frequency reduction 
stage for a stepping motor control. 
Although the invention has been described with respect to preferred 
embodiments, it is not to be so limited as changes and modifications can 
be made which are within the full intended scope of the invention as 
defined by the appended claims.