Network interface for changing byte alignment transferring on a host bus according to master and slave mode memory and I/O mapping requests

A network interface for a workstation is configured to supply data to a host bus. The network interface includes a buffer memory for storing a data frame received from a network according to a first byte alignment. A bus interface unit is configured to output the data frame onto the host bus according to a second byte alignment based on a master or slave transfer request to access the buffer memory. The slave request to access the buffer memory may be in the form of either an I/O mapped or memory mapped request. A memory management unit includes request logic to receive the master and slave transfer requests and generate a generic request to access the buffer memory. The memory management unit is configured to transfer the data frame from the buffer memory in response to the generic request. The bus interface unit includes a byte packing circuit configured for changing a byte alignment of the data frame prior to its transfer to the host memory. The byte alignment is changed based on information associated with the generic request. Hence, the amount of logic necessary to service the various types of requests is minimized.

BACKGROUND OF THE INVENTION
 1. Technical Field
 The present invention relates to network interfacing and more particularly
 to a network interface for efficiently supplying data from a buffer memory
 to a host bus.
 2. Background Art
 Network interface devices are commonly used to transmit data between a host
 computer and network communication systems, such as a local area network.
 Typical network interface devices include Ethernet-type and IEEE 802.3.
 One of the primary functions of a network interface is to control the
 transfer of data between a buffer and the host bus. The data stored in the
 buffer is retrieved as a result of one of two types of requests, namely
 master and slave.
 In master mode, a transfer is initiated by a master device which must
 arbitrate for use of the host bus with a host CPU prior to retrieving the
 data. In slave mode, the host CPU provides a target device with sufficient
 information to access the buffer and retrieve the data. A slave access can
 be performed using two different types of mapping, namely memory mapping
 and Input/Output (I/O) mapping.
 Transmission of data from the buffer memory to the host bus has
 traditionally been accomplished by providing specific logic for each type
 of request. FIG. 9 is a block diagram illustrating a typical buffer
 architecture 200 for accessing data from buffer memory. An interface unit
 202 receives master and slave requests to access the buffer memory 204.
 The request is directed to a transfer logic 206 that transfers data to or
 from the buffer memory 204. The transfer logic 206 must be capable of
 handling each type of request individually. Thus, the interface unit 202
 transfers the request to a specific logic portion in the transfer logic
 206 based on the nature of the request. For example, the transfer logic
 206 includes a first logic circuit 208 that services a master request, a
 second logic circuit 210 that services an I/O mapped slave request, and a
 third logic circuit 212 that services memory mapped slave requests.
 Hence, a primary disadvantage associated with current methods of
 transferring data is the excessive amount of logic necessary to service
 the different types of requests. Another disadvantage is the increased
 latency encountered during the data transfer process. This latency can be
 defined as the delay between the time when data is retrieved from the
 buffer to the time it is delivered to the host bus. As previously
 mentioned, additional delays are encountered during transfers initiated by
 a master device, because the master device must arbitrate for access to
 the bus with other master devices that also require use of the bus.
 DISCLOSURE OF THE INVENTION
 There is a need for an arrangement for supplying data frames to a host bus
 that minimizes the logic necessary to access a buffer memory using
 different types of requests.
 There is also a need for an arrangement for supplying data frames to a host
 bus that minimizes the latency encountered during the transfer of data
 from a buffer memory.
 There is also a need for an arrangement for supplying data frames to a host
 bus that is capable of maintaining appropriate byte alignment regardless
 of the type of transfer.
 These and other needs are attained by the present invention, where master
 and slave accesses to the buffer are serviced by a single logic circuit
 that eliminates the need for arbitration, reduces the amount of latency
 encountered during the data transfer process, and maintains appropriate
 byte alignment.
 In accordance with one aspect of the present invention, a network interface
 for supplying data frames to a host bus comprises a buffer memory for
 storing a data frame received from a network according to a first byte
 alignment. A memory management unit is configured to transfer the stored
 data frame from the buffer memory in response to the one transfer request.
 The memory management unit includes request logic for generating a generic
 request to access the buffer memory in response to the one transfer
 request. A bus interface unit is configured for outputting the data frame
 onto a host bus according to a second byte alignment based on one of a
 master transfer request and a slave transfer request. The bus interface
 unit also includes a byte packing circuit configured for changing the
 first byte alignment of a portion of the stored data frame to the second
 byte alignment, prior to transfer to the host bus, based on the generic
 request. The generic request is serviced by a single logic circuit,
 eliminating the need for specialized logic to individually service master
 and slave requests. Hence, the network interface can perform master
 transfers or slave transfers with minimal logic. In addition, the byte
 packing circuit maintains the appropriate byte alignment regardless of the
 type of transfer.
 Another aspect of the invention provides a method for accessing a buffer
 memory in a network interface. The method comprises generating a generic
 request in response to the detection of one of a master transfer request
 and a slave transfer request, reading a data frame from the buffer memory
 based on the generic request, determining a byte alignment for
 transmission of the data frame onto a host bus based on the generic
 request, and shifting bytes of the data frame for transfer onto the host
 bus based on the determined byte alignment. Generating a generic request
 enables a single logic circuit to service master and slave requests (both
 I/O and memory mapped) to access the buffer memory. Hence, a data frame
 from a buffer memory can be transferred to a host bus in accordance with a
 prescribed byte alignment for different transfer requests using minimal
 logic.
 Additional objects, advantages, and novel features of the present invention
 will be set forth in part in the description which follows, and in part
 will become apparent to those skilled in the art upon examination of the
 following or may be learned by practice of the invention. The objects and
 advantages of the invention may be realized and attained by means of the
 instrumalities and combinations particularly pointed out in the appended
 claims.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
 The present invention will be described with the example of a network
 interface in a packet switched network, such as an Ethernet (IEEE 802.3)
 network. A description will first be given of a network interface
 architecture, followed by the arrangement for transferring data from a
 buffer memory to a system memory using a single logic circuit configured
 for responding to master and slave requests. It will become apparent,
 however, that the present invention is also applicable to other network
 interface systems.
 Network Interface Architecture
 FIG. 1 is a block diagram of an exemplary network interface 10 that
 accesses the media of an Ethernet (ANSI/IEEE 802.3) network according to
 an embodiment of the present invention.
 The network interface 10, preferably a single-chip, 32-bit Ethernet
 controller, provides an interface between a local bus 12 of a computer,
 for example a peripheral component interconnect (PCI) local bus, and an
 Ethernet-based media 50.
 The interface 10 includes a PCI bus interface unit 16, a buffer memory
 portion 18, and a network interface portion 20. The PCI bus interface unit
 16 includes a PCI slave interface 16a and a direct memory access (DMA)
 interface 16b. The slave interface 16a manages PCI control and status
 information including reading and programming of the PCI status registers,
 but may also be configured for managing slave transfers via the PCI bus
 with a host CPU. The DMA interface 16b manages DMA transfers by the
 network interface 10 to and from system memory. Hence, the PCI bus
 interface unit 16 can be selectively configured for PCI transfers in slave
 and/or master (e.g., DMA) mode.
 The memory portion 18 includes a 32 bit static random access memory (SRAM)
 implemented directly on the network interface chip 10. According to the
 disclosed embodiment, the SRAM 18 may be accessed in a random access
 manner under the control of a memory management unit 22, or may be
 segmented into a receive portion 18a and a transmit portion 18b for
 receive and transmit paths, respectively.
 The network interface 10 also includes a buffer management unit 24
 configured for managing DMA transfers via the DMA interface 16b. The
 buffer management unit 24 manages DMA transfers based on DMA descriptors
 in host memory that specify start address, length, etc. The buffer
 management unit 24 initiates a DMA read from system memory into the
 transmit buffer 18b by issuing an instruction to the DMA interface 16b,
 which translates the instructions into PCI bus cycles. Hence, the buffer
 management unit 24 contains descriptor management for DMA transfers, as
 well as pointers associated with storing and reading data from the memory
 portion 18. Although the buffer management unit 24 and the memory
 management unit 22 are shown as discrete components, the two units may be
 integrated to form a memory management unit (MMU) 52 controlling all
 transfers of data to and from the memory unit 18, as seen with additional
 reference to FIG. 2.
 The network interface 20 includes a media access control (MAC) core 26, a
 general purpose serial interface (GPSI) 28, a media independent interface
 (MII) 30 for connecting to external 10 Mb/s or 100 Mb/s physical (PHY)
 transceivers, an external address detection interface (EADI) 32, an
 attachment unit interface (AUI) 34 having a Manchester encoder and
 decoder, and a 10/100 Mb/s twisted pair transceiver media attachment unit
 (MAU) 36.
 The network interface 10 also includes a network port manager 38 configured
 for performing MII handshaking between two devices on an MII bus via the
 MI port 30. Such MII handshaking may include link information, programming
 information at the MII layer using a management data clock (MDC), and
 management data input/output (MDIO) paths.
 The auto-negotiation portion 40 performs IEEE-compliant negotiation with a
 link partner on the PHY layer to exchange data indicating whether the link
 partner is capable of operating at 10 Mb/s, 100 Mb/s, and whether the link
 should be half-duplex or full-duplex.
 The LED controller 44 selectively controls the generation of LED output
 signals based upon the internal decoding logic and network interface
 status registers (not shown). The network interface 10 also includes an
 IEEE 1149.1-compliant JTAG boundary scan test access port interface 36.
 The EEPROM interface 42 connects to an EEPROM on either a network interface
 adapter card or the motherboard of the host computer via a serial
 interface link. The EEPROM (not shown in FIG. 1) will be programmed with
 configuration information related to the network interface 10, enabling
 the network interface 10 to be configured during initialization via the
 EEPROM interface 42. Once initialized, the network interface 10 stores the
 configuration information in internal registers (not shown), enabling the
 network interface 10 to operate independently of the host computer in the
 event the host computer is powered down. Hence, the network interface 10
 can be configured to operate while the host computer is in a stand-by
 mode, enabling the network interface 10 to output power up information to
 logic within the host computer to enable the host computer to
 automatically turn on in response to data packets received from the
 network and having a specific protocol, described below.
 Memory Management Architecture
 FIG. 2 is a block diagram illustrating the buffer architecture of the
 network interface 10 according to an embodiment of the present invention.
 As shown in FIG. 2, transfer of data frames between the PCI bus interface
 unit 16, also referred to as the bus interface unit (BIU), and the MAC 20
 is controlled by a memory management unit (MMU) 52 including the buffer
 management unit 24 and the SRAM MMU 22 of FIG. 1. The memory management
 unit 52 controls the reading and writing of data to the SRAM 18,
 illustrated in FIG. 2 as a receive SRAM portion 18a and a transmit SRAM
 portion 18b for convenience. It will be recognized in the art that the
 receive SRAM (RX_SRAM) 18a and the transmit SRAM (TX_SRAM) 18b may be
 implemented as a single memory device, or alternatively as two separate
 SRAM devices.
 As shown in FIG. 2, the memory management unit includes the buffer
 management unit 24, also referred to as the descriptor management unit,
 the SRAM MMU 22, and an arbitration unit 54. The arbitration unit 54
 arbitrates DMA requests for data transmission, data reception, descriptor
 lists from the descriptor management block 24, and status.
 The SRAM MMU 22 includes separate controllers for each SRAM 18a and 18b,
 for both read and write operations. According to the disclosed embodiment,
 the network interface 10 operates in two generic clock domains, namely a
 host computer bus clock domain 56a, and a network clock domain 56b. Since
 the network interface 10 needs to send and receive data across two
 independent clock domains 56, divided by the dotted line 58, the SRAM MMU
 22 must be capable of reading and writing data to each SRAM 18a and 18b in
 a manner that tracks memory status independent of the PCI clock in the
 host computer domain and the MAC clock generated from network activity in
 the network domain 56b.
 According to the disclosed embodiment, the SRAM MMU includes a
 transmit-data bus-side memory management unit (XB_MMU) 22a, a
 transmit-data MAC-side memory management unit (XM_MMU) 22b, a receive-data
 bus-side memory management unit (RM_MMU) 22c, a receive-data MAC-side
 memory management unit (RM_MMU) 22d, and a synchronization circuit 60. The
 XB_MMU 22a and the RM_MMU 22d operate as write controllers configured for
 writing frame data into the SRAMs 18b and 18a, respectively. The XB_MMU
 22a and the RB_MMU 22c operate according to the PCI bus clock (CLK). The
 RM_MMU 22d operates according to the receive MAC clock (RX_CLK) received
 by the MAC 20, and the XM_MMU 22b operates under the control of the MAC
 transmit clock (TX_CLK) received by the MAC 20. The XM_MMU 22b and the
 RB_MMU 22c operate as read controllers configured for reading frame data
 from the SRAMs 18b and 18a, respectively. Hence, receive data from the MAC
 20 is written into the RX_SRAM 18a under the control of the write
 controller 22d synchronous to the receive clock (RX_CLK) in the network
 clock domain 56b. Frame data stored in the RX_SRAM 18a is read and output
 to the BIU 16 via data path 62a under the control of the receive-data read
 controller 22c, which reads the frame synchronous to the PCI bus clock
 signal.
 Similarly, transmit data to be output onto the network by the MAC 20 is
 written into the TX_SRAM 18b via data path 62b under the control of the
 transmit-data write controller 22a, configured for writing the frame data
 synchronized to the PCI bus clock (CLK). The stored transmit data is read
 and output from the TX_SRAM 18b to the MAC 20 under the control of the
 transmit-data read controller 22b according to the MAC transmit clock
 (TX_CLK) within the network clock domain 56b.
 The presence of two separate clock domains 56a and 56b in writing and
 reading to a random access memory 18 requires that the write controller
 and read controller devices be coordinated and synchronized to ensure that
 no contention issues arise due to the relative independence of the two
 clock domains 56a and 56b. The SRAM MMU 22 includes a synchronization
 circuit 60 that asynchronously monitors the status of the RX_SRAM 18a and
 18b, enabling the memory controllers to read and write to the memory 18
 between the two clock domains 56a and 56b. Thus, problems that would
 ordinarily arise between the two clock domains in the individual memory
 management units 22a, 22b, 22c and 22d are avoided by use of the
 synchronization circuit 60 according to a prescribed arbitration logic.
 SRAM Data Structure
 FIGS. 3A and 3B illustrate the structure of data frames 70, 70' stored in
 the SRAM 18. Each data frame 70 is 33 bits wide, 1 bit corresponding to an
 ENF parameter 74 and a 32 bit double word (DWORD) corresponding to data or
 control information. The various types of DWORDs in the data frame 70,
 include a frame track 72, frame data 86, an upper status 88, and a lower
 status 90. The frame track 72 functions as a header for the frame 70 and
 includes a FRM parameter 76, a LONG parameter 78, a CNT parameter 80, an
 ENF_ADDR parameter 82, and a BE_L parameter 84. The FRM parameter 76 is a
 1 bit parameter that, when set to 1, indicates the entire received frame
 70 stored in the SRAM 18 is valid. The LONG parameter 78 is a 1 bit
 parameter that, when set to 1, indicates the expected receive frame length
 is greater than a preset length. The CNT 80 parameter is a 14 bit byte
 count that indicates the total number of bytes in the receive frame 70.
 The ENF_ADDR. parameter 82 is a 12 bit parameter that indicates the end
 address of the frame 70. The CNT parameter 80 and the ENF_ADDR parameter
 82 are only valid when the FRM bit 76 is set to 1. The BE_L parameter 84
 is a 4 bit active low parameter used to indicate which bytes are valid in
 the last DWORD (D LAST) of the frame 70. The ENF bit 74 is set to 1 to
 identify the final data segment 86 in the frame 70, and set to 0 for all
 other DWORDs. The upper status and lower status DWORDs 88, 90 provide
 control information, such as the total number of bytes of receive data in
 the frame, necessary to perform slave transactions.
 PCI Bus Data Transfers
 FIG. 4 is a block diagram illustrating a request logic 96 for generating
 generic transfer requests according to an embodiment of the present
 invention. The bus interface unit 16 is configured for outputting
 different types of requests to access the buffer memory 18a through a
 request logic 96 in order to generate a generic request. The requests can
 be in the form of master or slave. In addition, the slave requests can be
 either I/O mapped or memory mapped. As shown in FIG. 4, the request logic
 96 is implemented as an OR gate 98. The OR gate 98 generates the generic
 request which is output to the read controller 22c (RB_MMU) in order to
 access the buffer memory 18a.
 FIG. 5 is a diagram illustrating a logic circuit 100 for transferring data
 from the SRAM 18a to the BIU 16 according to an embodiment of the present
 invention. The logic circuit 100 includes a bus side control block 102 for
 reading stored frame data from the SRAM 18a, and a byte packing circuit
 104 for aligning portions of the frame data prior to transfer to the host
 bus (e.g., the PCI bus 12). The bus side control block 102 includes an
 address register 106, a read line control register 108, an increment
 circuit 110, and an advance signal generator 112. The address register 106
 stores an address pointer value (RB_ADDR) that identifies a memory
 location in the SRAM 18a for reading a corresponding 32-bit double-word
 (DWORD) of frame data. The address register 106 includes a multiplexer
 106a and a delay flip flop 106b. The increment circuit 110 supplies an
 incremented address pointer value (RB_ADDR) which is stored in the address
 register 106. The address register 106 stores the address pointer value in
 response to a bus-side advance signal (RB_ADV) supplied to the selection
 input of multiplexer 106a. The advance signal generator 112 generates the
 bus-side advance signal (RB_ADV) in response to an advance signal (AD_ADV)
 generated by the BIU 16. A read control line register 108, which includes
 a multiplexer 108a and a delay flip-flop 108b, outputs an active-low read
 signal (RB_RD_L) to the RX_SRAM 18a in response to the bus-side advance
 signal (RB_ADV), causing the RX_SRAM 18a to output the stored DWORD from
 the location addressed by the address pointer value (RB_ADDR).
 The byte packing circuit 104 includes a first holding register 114, a
 second holding register 116, and a third holding register 118. As shown in
 FIG. 5, the first holding register 114 includes a multiplexer 114a that
 selectively outputs the output frame data received from the RB_SRAM_DATA.
 signal path based on the bus-side advance signal (RB_ADV), and a delay
 flip flop 114b that latches the frame data at the rising edge of a clock
 signal (BCLK). The second holding register 116 also includes a multiplexer
 116a which selectively outputs frame data received from the RB_DATA signal
 path based on the bus-side advance signal (RB_ADV), and a delay flip flop
 116b. Similarly, the third holding register 118 includes a multiplexer
 118a and a delay flip flop 118b.
 SRAM 18a outputs the 32-bit DWORD of frame data to the first holding
 register 114. A 32-bit multiplexer 120 selectively supplies (on a
 bit-by-bit basis) the outputs of the first holding register 114 (via
 RB_DATA) or the second holding register 116 (via DMA_DFF), in response to
 a 32-bit selection signal from a BIU state machine 122, to the third
 holding register 118 where the data is held until it is ready for transfer
 onto the host bus 12 along the AD signal path. The advance signal (AD_ADV)
 generated by the BIU 16 indicates that frame data has been successfully
 transferred to the host bus 12 and that the BIU 16 is ready to accept new
 frame data. The advance signal (AD_ADV) generated by the BIU 16 drives an
 advance signal generator 112 to produce the bus-side advance signal
 (RB_ADV). The BIU state machine 122 receives various signals from the DMA
 descriptor management block 24, the RB_MMU 22c, and the BIU 16 which are
 used to generate the control signals output to multiplexer 120 and the
 multiplexer 118a. The signals include active low byte enable values for
 master transfers (DMA_BE_L), active low byte enable values for slave
 transfers (SLV_BE_L), and the advance signal (AD_ADV).
 FIG. 6 is a timing diagram illustrating a master (DMA) transfer according
 to an embodiment of the present invention. The bus interface unit (BIU) 16
 and the read controller 22c (RB_MMU) are both inactive at the start of
 clock cycle 1. At the start of clock cycle 2, the DMA descriptor
 management block 24 asserts DMA_REQ to request transfer of data to or from
 a host memory, and outputs a DMA address value (ADDR1) along signal path
 DMA_ADDR. The BIU 16 deasserts a bus request signal (REQ#) on the host bus
 12 and outputs an internal grant signal (DMA_GNT) to the descriptor
 management block 24 during clock cycle 2 and in response to the DMA
 request signal (DMA_REQ). The DMA descriptor management block 24 also
 outputs a DMA count value (DMA_XFR_CNT) to the BIU 16 and the read
 controller 22c (RB_MMU) indicating the number of PCI data transfers to be
 completed during the transaction. As shown in FIG. 6, the DMA address
 (ADDR1) and the number of data transfers (DMA_XFR_CNT) are valid as long
 as the DMA_REQ remains asserted. The DMA descriptor management block 24
 also outputs active low byte enable signals (DMA_BE_L), representing a
 value (BEL1) of valid bytes for the first data block, to the BIU 16 and
 read controller 22c (RB_MMU) during clock cycle 1. The SRAM 18a outputs
 the first block (D1) of data as a 32-bit double word (DWORD) to the first
 holding register 114 via the signal path RB_SRAM_DATA during clock cycle 1
 in response to the corresponding address (RB_ADDR) output by the address
 register 106 and the read signal (RB_RD_L) output by the read control line
 register 108.
 Assertion of DMA_REQ and DMA_GNT cause the BIU 16 to assert an advance
 signal (AD_ADV) during clock cycle 3, indicating that the BIU 16 is ready
 to transfer data. The advance signal (AD_ADV) drives the advance signal
 generator 112 used to produce the bus-side signal RB_ADV. As shown in FIG.
 5, the bus-side advance signal (RB_ADV) controls the address register 106,
 the read control line register 108, the first holding register 114, and
 the second holding register 116. During clock cycle 3, the PCI arbiter
 (e.g. the host CPU) deasserts GNT# in response to REQ#, thus granting
 ownership of the host bus 12 to the network interface 10 at the next
 cycle.
 At the start of clock cycle 4, the network interface 10 asserts FRAME# on
 the host bus 12. The first data block, D1, is also output to the first
 holding register 114 from the SRAM along the RB_SRAM_DATA path at the
 start of clock cycle 4. Deassertion of REQ# and GNT# causes the BIU 16 to
 keep AD_ADV asserted during clock cycle 4. Assertion of AD_ADV causes the
 count (ADV_CNT) to be decremented each clock cycle. In response to AD_ADV
 at clock cycle 4, a byte enable value (BEL2) for the second data block D2
 is output to DMA_BE_L, and the value of read line pointer (RB_ADDR) in the
 address register 106 is incremented to the value A2. The first data block
 D1 is simultaneously transferred from the first holding register 114 to
 the second holding register 116 and to multiplexer 120 along the signal
 path RB_DATA, while the second data block, D2, is loaded into the first
 holding register 114 along the signal path RB_SRAM_DATA during clock cycle
 4.
 The BIU 16 asserts GNT# during clock cycle 5, and the byte enable signal
 (BEL3) for the third data block D3 is output to DMA_BE_L. The third data
 block D3 is also output from the SRAM 18a via the RB_SRAM_DATA path to the
 first holding register 114, and the second data block D2 is output from
 the first holding register 114 to the second holding register 116 via
 signal path RB_DATA. The first data block, D1, is transferred to the third
 holding register 118 as a host bus (e.g., PCI) data block D'1 where it
 will be output to host bus 12 along the AD signal path.
 The data blocks output by the SRAM 18a on the RB_SRAM_DATA path are aligned
 according to a first byte alignment. The PCI data blocks output to the
 host bus 12 by the third holding register 118 are aligned according to a
 second byte alignment. Consequently, the PCI data block D'1 may not be
 identical to the first data block D1 because the first data block, D1,
 must be properly aligned for output to the host bus 12 before it can be
 transferred to the system memory. FIG. 7 illustrates alignment of data
 from the SRAM for a variety of data transfer methods. A sample data frame
 contains six data blocks that must be transferred to the system memory.
 Each data block in the SRAM 18a contains 4 bytes of information, with the
 exception of the last data block, which may contain 1 to 4 bytes of
 information. The data is shifted and moved to the system memory according
 to the second byte alignment, based on the byte enable values. For
 example, the SRAM receive frame shown in FIG. 7 contains a DWORD having a
 first byte alignment "03 02 01 00". The data in the SRAM 18a is contiguous
 except for the last DWORD, which contains only two bytes. However, the
 frame data in the SRAM 18a must be properly shifted, according to the
 second byte alignment, (e.g., "02 01 00 XX") before it can be moved to the
 system memory.
 In order to properly align the data retrieved from the SRAM on the host
 bus, a byte enable value (BEL) is output by the descriptor management
 block 24 to the bus interface unit 16 for each data block. The BIU state
 machine 122 outputs byte selection signals to multiplexer 120 in response
 to byte enable values so that selected bytes (or bits) may be transferred
 to the third holding register 118. The first byte enable value, BEL1,
 specifies the number bytes from the first data block, D1, which may be
 transferred to the third holding register 118 for transfer to the host bus
 12 along signal path AD. The second holding register 116 retains the value
 of the first data block, D1 so that the BIU state machine 122 can control
 the multiplexer 120 may output selected bytes of the first data block, D1,
 or the second data block, D2. Hence, the output of the second holding
 register 116 is shifted by multiplexer 120, so that the PCI data block D'1
 output to the third holding register 118 will be properly aligned on the
 host bus. Accordingly, it should be understood that the BIU state machine
 122 can control the multiplexer 120 for bit-wise or byte-wise manipulation
 of the data blocks. Alternatively, a plurality of 1 bit multiplexers,
 corresponding to the length of the data block in bits, may be substituted.
 The network interface 10 and the target device respectively deassert IRDY#
 and TRDY#, al the start of clock cycle 6, to indicate readiness to
 complete transfer of the first PCI data block, D'1, to the host bus 12.
 Once transfer of the first PCI data block is complete, transfer of a
 second PCI data block D'2 may be initiated. During clock cycle 6, the DMA
 descriptor management block 24 outputs a byte enable value (BEL4) for the
 fourth data block, D4, along the signal path DMA_BE_L to the BIU state
 machine 122. The value for the read pointer (RB_ADDR) stored in the
 address register 106 also is incremented, and the fourth data block, D4,
 is output to the first holding register 114 via the RB_SRAM_DATA signal
 path. The third data block, D3, is output from the second holding register
 116. The second byte enable value (BEL2) is used by the BIU state machine
 122 to control multiplexer 120 for aligning data from the second data
 block, D2, with data from the first data block, D1, which was retained in
 the second holding register 116, and output the second PCI data block,
 D'2, to the host bus 12. The byte alignment process is repeated until all
 the data transfers are complete.
 During clock cycle 6, the BIU 16 asserts an acknowledgement signal
 (BUS_XFR) which is output to the DMA descriptor management block 24 to
 indicate successful transmission of a PCI data block. The acknowledgement
 signal remains asserted throughout the entire data transfer process, clock
 cycle 7 to clock cycle 14. At the start of clock cycle 13, the network
 interface 10 asserts FRAME# to indicate that it is ready to complete the
 data transfer phase and relinquish control of the host bus 12. At the
 start of clock cycle 14, the BIU 16 outputs a termination signal
 (DMA_DONE) to the RB_MMU indicating that the data transfer sequence is
 successfully completed. Similarly, the network interface 10 and the target
 device assert IRDY# and TRDY#, respectfully, to indicate the last
 transaction has occurred.
 FIG. 8 is a timing diagram illustrating a slave transfer according to an
 embodiment of the present invention. The host CPU deasserts FRAME# at
 clock cycle 1 to indicate the start of a transaction, and supplies the
 starting address (ADDR1) and the transaction type (RD) on the AD and CBE#
 paths of the host bus 12, respectively. According to the disclosed
 embodiment, the two least significant bits of the starting address (ADDR1)
 are used to encode byte enable values for the transaction. Since each data
 block is in the form of DWORD, the two least significant bits do not
 effect the data block specified by a particular address location. For
 example, a starting address whose last two hexadecimal digits are 10,
 converts to a binary value of 10000. The two least significant bits. 00,
 represent the encoded byte enable values. Similarly hexadecimal addresses
 whose last two digits are 11, 12, and 13 generate encoded byte enable
 values of 01, 10, and 11, respectively. The least significant bits are
 converted to 4-bit byte enable values (SLV_BE_L) as shown in Table 1:
 TABLE 1
 00 = 0000
 01 = 0001
 10 = 0011
 11 = 0111
 Hence, the same logic may be used to interpret byte enables for master or
 slave requests.
 In response to the signals asserted by the host CPU, the read controller
 22c (RB_MMU) outputs a value (A1) for the read pointer (RB_ADDR) to the
 address register 106. The SRAM 18a outputs a first data block, D1, to the
 first holding register 114 via the signal path RB_SRAM_DATA in response to
 the corresponding address (RB_ADDR) output by the address register 106 and
 the read signal (RB_RD_L) output by the read control line register 108. As
 shown in FIG. 8, the value of the read pointer (RB_ADDR) in the address
 register 106 and the data in the first holding register 114 are valid for
 three clock cycles.
 During clock cycle 2, the host CPU enters a wait state on the address
 signal path (AD), and outputs a byte enable signal along the command
 signal path (C/BE#) having a byte enable value, for example, of zero. The
 host CPU deasserts IRDY# to indicate its readiness to commence the next
 data transfer. The slave device (e.g., the target network interface
 addressed by the host CPU) deasserts DEVSEL# during clock cycle 3 in
 response to the starting address (ADDR1). The BIU 16 asserts an internal
 chip select CS_RB on the read controller 22c (RB_MMU) to indicate a slave
 read access from the SRAM 18a. The BIU 16 decodes the starting address
 (ADDR1) and outputs a byte enable signal (SLV_BE_L) to BIU state machine
 122. The BIU 16 also asserts AD_ADV to indicate that it is ready to accept
 data.
 During clock cycle 4, the second data block, D2, is output by the SRAM 18a
 to the first holding register 114 along the signal path RB_SRAM_DATA, and
 the first data block, D1, is concurrently transferred to the second
 holding register 116 and multiplexer 120 along the signal path RB_DATA in
 response to the advance signal (AD_ADV).
 During clock cycle 5, the slave device deasserts TRDY# on the host bus 12
 to indicate that it is ready to complete the current data phase. The third
 data block, D3, is loaded into the first holding register 114, and the
 second data block, D2, is transferred to the second holding register 116.
 The first data block, D1, is aligned for transfer onto the host bus 12
 according to the byte aligning process previously described with reference
 to the BIU state machine 122.
 During clock cycle 6, the BIU 16 asserts BUS_XFR to indicate successful
 transfer of the first PCI data block D'1, and the SRAM 18a outputs the
 fourth data block, D4, to the first holding register 114. The third data
 block, D3, is transferred from the first holding register 114 to the
 second holding register 116, and a second PCI data block, D'2, is output
 to the host bus 12. The data transfer process continues until clock cycle
 9, at which point the fourth PCI data block D'4 has been output on the
 host bus 12.
 During clock cycle 9, the host CPU asserts IRDY# to halt the current data
 transfer. During clock cycle 10, the host CPU deasserts FRAME# and outputs
 a new starting address (ADDR5) to the address path on the host bus 12 to
 continue the data transfer. The host CPU also outputs a read command (RD)
 along the command signal path (CBE#) of the host bus 12 to indicate a read
 transaction from the SRAM 18a. The BIU deasserts CS_RB and the advance
 signal (AD_ADV). During clock cycle 10, the slave device (e.g., the
 network interface) also continues reading data from the SRAM 18a. During
 clock cycle 11, the host CPU inserts a wait state into the address path of
 the host bus 12, and begins to load a byte enable value on the command
 signal path (CBE#). The host CPU deasserts IRDY# to indicate that it is
 ready to initiate data transfer.
 The BIU 16 deasserts DEVSEL# and CS_RB during clock cycle 12 in response to
 deassertion of IRDY# by the host CPU. The BIU 16 also asserts AD_ADV.
 During clock cycle 13, the sixth address for the read pointer is loaded
 into the address register 106, D5, the sixth data block, D6, is read into
 the first holding register 114, and the fifth data block, D5, is
 transferred to the second holding register 116. During the fourteenth
 clock cycle the slave device deasserts TRDY#, indicating that it is ready
 to receive data. The address for the read pointer (RB_ADDR) in the address
 register 106 is incremented, and the seventh data block D7 is loaded into
 the first holding register 114. The sixth data block, D6, is transferred
 from the first holding register 114 to the second holding register 116.
 The fifth data block, D5, is manipulated and transferred to the host bus
 12 as a fifth PCI data block, D'5, as previously described until the data
 transfer is completed.
 As shown in FIGS. 5 and 8, slave accesses of the SRAM 18a are performed by
 retrieving the address from the AD signal path during the PCI address
 phase, followed by incrementing the read pointer value in the address
 register 106 based on the bus side advance signal (RB_ADV). Hence, the
 disclosed embodiment uses a generic logic configuration that can perform
 slave transfers independent of whether I/O mapped transfers or memory
 mapped transfers are used by the host CPU.
 According to the disclosed embodiment, a generic transfer logic is
 configured for performing data transfers from a buffer memory to a host
 data bus, independent of whether the data transfer is a master access or a
 slave access. In addition, a byte packing circuit ensures that appropriate
 byte alignment is maintained between data output from the receive buffer
 18a and the host bus 12, regardless of whether a master transfer or slave
 transfer is performed.
 While this invention has been described in connection with what is
 presently considered to be the most practical and preferred embodiments,
 it is to be understood that the invention is not limited to the disclosed
 embodiments, but, on the contrary, is intended to cover various
 modifications and equivalent arrangements included within the spirit and
 scope of the appended claims.