Liquid crystal display

A liquid crystal display includes: a first substrate; a gate line disposed on the first substrate; a first data line and a second data line disposed on the first substrate; a first thin film transistor connected to the gate line and to the first data line; a first subpixel electrode connected to the first thin film transistor; a second thin film transistor connected to the gate line and to the second data line; a second subpixel electrode connected to the second thin film transistor; a third thin film transistor connected to the gate line and to the first data line; a fourth thin film transistor connected to the gate line and to the second data line; and a third subpixel electrode connected to the third and fourth thin film transistors.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to, and the benefit of, Korean Patent Application No. 10-2014-0015104 filed in the Korean Intellectual Property Office on Feb. 10, 2014, the entire contents of which are incorporated herein by reference.

BACKGROUND

Field

The present disclosure relates to a liquid crystal display.

Description of the Related Technology

A liquid crystal display is currently one of the most widely used flat panel displays, and includes two display panels on which electric field generating electrodes, such as a pixel electrode and a common electrode, are formed, and a liquid crystal layer interposed between the two display panels.

The liquid crystal display displays an image by generating an electric field on a liquid crystal layer by applying a voltage to the field generating electrodes, determining alignment directions of liquid crystal molecules of the liquid crystal layer through the generated field, and controlling polarization of incident light.

The liquid crystal display typically includes a switching element connected to a pixel electrode and a plurality of signal lines, such as gate lines and data lines, for applying voltages to the pixel electrodes so as to control the switching elements.

Among the liquid crystal displays, a vertically aligned mode liquid crystal display, in which liquid crystal molecules are aligned so that long axes thereof are perpendicular to the upper and lower panels while no electric field is applied, has been in the limelight because its contrast ratio is high and a wide reference viewing angle is easily implemented.

For such a mode liquid crystal display, in order to make side visibility close to front visibility, a method has been proposed in which one pixel is divided into two subpixels of different transmittance by applying different voltages to the two subpixels.

However, when the side visibility becomes similar to the front visibility by dividing one pixel into two subpixels of different transmittance, luminance is increased at a low grayscale or a high grayscale, and thus gray expression at the side is difficult, thereby deteriorating picture quality.

SUMMARY OF CERTAIN INVENTIVE ASPECTS

The present disclosure has been made in an effort to provide a liquid crystal display that is capable of accurately expressing a gray in a low grayscale region while making side visibility similar to front visibility.

A liquid crystal display according to an embodiment includes: a first substrate; a gate line disposed on the first substrate; a first data line and a second data line disposed on the first substrate; a first thin film transistor connected to the gate line and to the first data line; a first subpixel electrode connected to the first thin film transistor; a second thin film transistor connected to the gate line and to the second data line; a second subpixel electrode connected to the second thin film transistor; a third thin film transistor connected to the gate line and to the first data line; a fourth thin film transistor connected to the gate line and to the second data line; and a third subpixel electrode connected to the third and fourth thin film transistors.

The first thin film transistor and the second thin film transistor may be disposed between the first subpixel electrode and the second subpixel electrode, and the third thin film transistor and the fourth thin film transistor may be disposed between the second subpixel electrode and the third subpixel electrode.

The third subpixel electrode may be connected to drain electrodes of the third and fourth thin film transistors, and a ratio of a channel width of the third thin film transistor to a channel length thereof may be substantially equal to or different from the ratio of a channel width of the fourth thin film transistor to a channel length thereof.

A first area H corresponding to the first subpixel electrode, a second area L corresponding to the second subpixel electrode, and a third area M corresponding to the third subpixel electrode may satisfy the equation: H≦M<L.

The first data line may transmit a first data voltage, the second data line may transmit a second data voltage, the first and second data voltages may be obtained from one image signal and may be different from each other, and the third subpixel electrode may be applied with a third voltage between the first and second data voltages.

The gate line may include a first gate line and a second gate line that are connected to each other, the first and second thin film transistors may be connected to the first gate line, and the third and fourth thin film transistors may be connected to the second gate line.

The liquid crystal display may further include an insulating layer disposed on the gate line, the first data line, and the second data line, a first portion of the first subpixel electrode may overlap a first portion of the second subpixel electrode while interposing the insulating layer therebetween, and a first portion of the third subpixel electrode may overlap a second portion of the second subpixel electrode while interposing the insulating layer therebetween.

The first thin film transistor, the second thin film transistor, the third thin film transistor, and the fourth thin film transistor may be disposed between the first subpixel electrode and the third subpixel electrode, and the first thin film transistor, the second thin film transistor, the third thin film transistor, and the fourth thin film transistor may be disposed between the first portion of the second subpixel electrode and the second portion of the second subpixel electrode.

One pixel area of the liquid crystal display may include a first pixel area and a second pixel area, the first portion of the first subpixel electrode, the first portion of the second subpixel electrode, and the second portion of the first subpixel electrode may be disposed in the first pixel area, and the first portion of the third subpixel electrode, the second portion of the second subpixel electrode, the second portion of the third subpixel electrode may be disposed in the second pixel area, and a size of the first pixel area may be substantially equal to or greater than a size of the second pixel area.

The first portion of the first subpixel electrode may be disposed under the insulating layer, the second portion of the first subpixel electrode may be disposed on the insulating layer, and the first and second portions of the first subpixel electrode may be connected to each other through a contact hole that is formed in the insulating layer.

The first portion of the third subpixel electrode may be disposed under the insulating layer, the second portion of the third subpixel electrode may be disposed on the insulating layer, and the first and second portions of the third subpixel may be connected to each other through a contact hole that is formed in the insulating layer.

The first portion of the second subpixel electrode may be disposed on the insulating layer and may have a plurality of minute branch portions, and the first portion of the first subpixel electrode may be disposed under the insulating layer and may have a planar shape. The second portion of the second subpixel electrode may be disposed on the insulating layer and may have a plurality of minute branch portions, and the first portion of the third subpixel electrode may be disposed under the insulating layer and may have a planar shape.

The liquid crystal display according to embodiments is capable of accurately expressing a gray in a low grayscale region while making side visibility similar to front visibility.

DETAILED DESCRIPTION OF CERTAIN INVENTIVE EMBODIMENTS

Embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which certain embodiments are shown.

As those skilled in the art would realize, the described embodiments may be modified in various ways, without departing from the spirit or scope of the present invention.

On the contrary, embodiments introduced herein are provided to make disclosed contents thorough and complete, and to sufficiently transfer the spirit of the present invention to those skilled in the art.

In the drawings, the thickness of layers and regions may be exaggerated for clarity.

It will be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening elements may also be present.

Like reference numerals generally designate like elements throughout the specification.

A pixel of a liquid crystal display according to an embodiment is described with reference toFIG. 1.

FIG. 1is an equivalent circuit diagram of a pixel of the liquid crystal display according to an embodiment.

Referring toFIG. 1, the liquid crystal display according to an embodiment includes signal lines including a gate line121, a first data line171a,and a second data line171b,and a pixel PX connected thereto.

The pixel PX includes a first switching element Qa, a second switching element Qb, a third switching element Qc, a fourth switching element Qd, a first liquid crystal capacitor CLCH, a second liquid crystal capacitor CLCL, and a third liquid crystal capacitor CLCM.

The first switching element Qa, the second switching element Qb, the third switching element Qc, and the fourth switching element Qd are connected to the same gate line121, the first and third switching elements Qa and Qc are connected to the first data line171a,and the second and fourth switching elements Qb and Qd are connected to the second data line171b.

The first switching element Qa, the second switching element Qb, the third switching element Qc, and the fourth switching element Qd are three terminal elements, such as for example thin film transistors, that are disposed on a substrate of the liquid crystal display.

A control terminal of the first switching element Qa is connected to the gate line121, an input terminal thereof is connected to the first data line171a,and an output terminal thereof is connected to the first liquid crystal capacitor CLCH.

A control terminal of the second switching element Qb is connected to the gate line121, an input terminal thereof is connected to the second data line171b,and an output terminal thereof is connected to the second liquid crystal capacitor CLCL.

A control terminal of the third switching element Qc is connected to the gate line121, an input terminal thereof is connected to the first data line171a,and an output terminal thereof is connected to the third liquid crystal capacitor CLCM, while a control terminal of the fourth switching element Qd is connected to the gate line121, an input terminal thereof is connected to the second data line171b,and an output terminal thereof is connected to the third liquid crystal capacitor CLCM.

A first subpixel electrode191a(seeFIG. 2) connected to the first switching element Qa and a common electrode270(seeFIG. 3) overlap each other to form the first liquid crystal capacitor CLCH.

A second subpixel electrode191b(seeFIG. 2) connected to the second switching element Qb and the common electrode270overlap each other to form the second liquid crystal capacitor CLCL.

A third subpixel electrode191c(seeFIG. 2) connected to the third and fourth switching elements Qc and Qd and the common electrode270overlap each other to form the third liquid crystal capacitor CLCM.

The liquid crystal display illustrated inFIG. 1will now be described in detail with reference toFIGS. 2 to 5.

FIG. 2is a layout view of the liquid crystal display according to an embodiment,FIG. 3is a cross-sectional view of the liquid crystal display ofFIG. 2taken along the lineFIG. 4is a cross-sectional view of the liquid crystal display ofFIG. 2taken along the line IV-IV, andFIG. 5is a layout view of a basic electrode of the liquid crystal display according to an embodiment.

Referring toFIGS. 2 to 4, the liquid crystal display according to an embodiment includes a lower display panel100and an upper display panel200that face each other, and a liquid crystal layer3interposed between the two display panels100and200.

The lower panel will be described first.

The gate line121and a storage voltage line131are disposed on a first insulation substrate110. The gate line121includes a first gate line121aand a second gate line121b.

The first and second gate lines121aand121bare connected to each other, and may be applied with the same gate signal.

The first and second gate lines121aand121bmainly extend in a horizontal direction to transmit a gate signal.

The first gate line121aincludes a first gate electrode124aand a second gate electrode124bthat mainly protrude upwards, and the second gate line121bincludes a third gate electrode124cand a fourth gate electrode124dthat mainly protrude downwards.

The storage voltage line131includes storage electrodes132and133.

A gate insulating layer140is disposed on the gate line121including the first and second gate lines121aand121b,and on the storage voltage line131.

A first semiconductor154a,a second semiconductor154b,a third semiconductor154c,and a fourth semiconductor154dare disposed on the gate insulating layer140.

The first semiconductor154a,the second semiconductor154b,the third semiconductor154c,and the fourth semiconductor154dmay contain, for example, amorphous silicon, crystalline silicon, or an oxide semiconductor.

Ohmic contacts163a,165a,163b,165b,163c,165c,163d,and165dare respectively disposed on the first semiconductor154a,the second semiconductor154b,the third semiconductor154c,and the fourth semiconductor154d.

In embodiments where the first semiconductor154a,the second semiconductor154b,the third semiconductor154c,and the fourth semiconductor154dare made of an oxide semiconductor, the ohmic contacts may be omitted.

The first data line171a,the second data line171b,a first drain electrode175a,a second drain electrode175b,a third drain electrode175c,and a fourth drain electrode175dare respectively disposed on the ohmic contacts163a,165a,163b,165b,163c,165c,163d,and165d.

The first and second data lines171aand171btransmit a data signal, and mainly extend in a vertical direction to cross the first and second gate lines121aand121b.

The first data line171aincludes a first source electrode173athat extends toward the first gate electrode124a,and a third source electrode173cthat extends toward the third gate electrode124c.The second data line171bincludes a second source electrode173bthat extends toward the second gate electrode124b,and a fourth source electrode173dthat extends toward the fourth gate electrode124d.

One end portion of the first drain electrode175ais partially enclosed by the first source electrode173a,one end portion of the second drain electrode175bis partially enclosed by the second source electrode173b,one end portion of the third drain electrode175cis partially enclosed by the third source electrode173c,and one end portion of the fourth drain electrode175dis partially enclosed by the fourth source electrode173d.

The third and fourth drain electrodes175cand175dare connected to each other.

The first, second, third, and fourth gate electrodes124a,124b,124c,and124d,the first, second, third, and fourth source electrodes173a,173b,173c,and173d,and the first, second, third, and fourth drain electrodes175a,175b,175c,and175drespectively form the first, second, third, and fourth thin film transistors (TFTs)154a,154b,154c,and154d,which are the first, second, third, and fourth switching elements Qa, Qb, Qc, and Qd, together with the first, second, third, and fourth semiconductors154a,154b,154c,and154d.Channels of the thin film transistors are respectively formed in the first, second, third, and fourth semiconductors154a,154b,154c,and154dbetween the first, second, third, and fourth source electrodes173a,173b,173c,and173dand the first, second, third, and fourth drain electrodes175a,175b,175c,and175d.

Except for the channel regions, the semiconductors154a,154b,154c,and154dhave substantially the same planar shape as the data lines171aand171b,the source electrodes173a,173b,173c,and173d,the drain electrodes175a,175b,175c,and175d,and the ohmic contacts163a,165a,163b,165b,163c,165c,163d,and165d.

A passivation layer180is disposed on exposed portions of the data lines171aand171b,the drain electrodes175a,175b,175c,and175d,and the semiconductors154a,154b,154c,and154d.

A first contact hole185a,a second contact hole185b,and a third contact hole185crespectively exposing a wide end portion of the first drain electrode175a,a wide end portion of the second drain electrode175b,and a wide connection portion that connects the third and fourth drain electrodes175cand175dare formed in the passivation layer180.

A pixel electrode191including the first subpixel electrode191a,the second subpixel electrode191b,and the third subpixel electrode191cis disposed on the passivation layer180. The first thin film transistor Qa and the second thin film transistor Qb are disposed between the first subpixel electrode191aand the second subpixel electrode191b,and the third thin film transistor Qc and the fourth thin film transistor Qd are disposed between the second subpixel electrode191band the third subpixel electrode191c.

When an area formed with the first subpixel electrode191a,an area formed with the second subpixel electrode191b,and an area formed with the third subpixel electrode are respectively represented as a first area H, a second area L, and a third area M, sizes of the first area H, the second area L, and the third area M can be expressed as follows:
H≦M<L

The first subpixel electrode191a,the second subpixel electrode191b,and the third subpixel electrode191crespectively include one or more of a basic electrode199illustrated inFIG. 5or a variant thereof.

The basic electrode199will now be described in detail with reference toFIG. 5.

As shown inFIG. 5, the basic electrode199has a generally quadrangular shape, and includes a cross-shaped stem portion including a horizontal stem portion193and a vertical stem portion192that is perpendicular thereto.

Further, the basic electrode199is divided into a first subregion Da, a second subregion Db, a third subregion Dc, and a fourth subregion Dd by the horizontal and vertical stem portions193and192, and each of the subregions Da to Dd includes a plurality of first to fourth minute branch portions194a,194b,194c,and194d.

The first minute branch portion194aobliquely extends in an upper left direction from the horizontal stem portion193or vertical stem portion192, while the second minute branch portion194bobliquely extends in an upper right direction from the horizontal stem portion193or vertical stem portion192.

In addition, the third minute branch portion194cobliquely extends in a lower left direction from the horizontal stem portion193or vertical stem portion192, while the fourth minute branch portion194dobliquely extends in a lower right direction from the horizontal stem portion193or vertical stem portion192.

The first to fourth minute branch portions194a,194b,194c,and194dform an angle of about 45 or 135 degrees with respect to the gate lines121aand121bor the horizontal stem portion193.

Further, the minute branch portions194a,194b,194c,and194dof two adjacent subregions Da, Db, Dc, and Db may be perpendicular to each other.

The first subpixel electrode191aincludes a first extended portion195a,the first extended portion195ais disposed in the first contact hole185a,and the first subpixel electrode191ais applied with a first data voltage from the first drain electrode175athrough the first contact hole185a.

Similarly, the second subpixel electrode191bincludes a second extended portion195b,the second extended portion195bis disposed in the second contact hole185b,and the second subpixel electrode191bis applied with a second data voltage from the second drain electrode175bthrough the second contact hole185b.

The first and second data voltages are obtained from one image signal, and respectively have different values.

The first data voltage may be greater than the second data voltage.

The third subpixel electrode191cis applied with a third data voltage between the first and second data voltages from the third and fourth drain electrodes175cand175dthrough the third contact hole185c.

As described above, the third and fourth drain electrodes175cand175dare connected to each other, and the third subpixel electrode191cis applied with the third data voltage between the first and second data voltages from the third and fourth drain electrodes175cand175dthrough the third contact hole185c.

If a first channel width CWA and a first channel length CLA of the third thin film transistor Qc connected to the first data line171aare equal to a second channel width CWB and a second channel length CLB of the fourth thin film transistor Qd connected to the second data line171b,the third subpixel electrode191cis applied with the third data voltage having an intermediate value between the first data voltage transmitted through the first data line171aand the second data voltage transmitted through the second data line17lb.

However, if a first ratio (CWA/CLA) of the first channel width CWA of the third thin film transistor Qc to the first channel length CLA thereof is greater than a ratio (CWB/CLB) of the second channel width CWB of the fourth thin film transistor Qd to the second channel length CLB thereof, influence of the first data voltage transmitted through the third thin film transistor Qc is increased such that the third subpixel electrode191cis applied with the third data voltage that has the intermediate value between the first data voltage transmitted through the first data line171aand the second data voltage transmitted through the second data line171bbut is closer to the first data voltage than the second data voltage.

In more detail, if the third and fourth thin film transistors Qc and Qd are respectively seen as a first resistance and a second resistance, an amount of current IAflowing through the third transistor Qc (first resistance) is proportional to the first channel width CWA of the third thin film transistor Qc, and is inversely proportional to the first channel length CLA thereof.

Similarly, an amount of current IBflowing through the fourth transistor Qd (second resistance) is proportional to the second channel width CWB of the fourth thin film transistor Qd, and is inversely proportional to the second channel length CLB thereof.

Accordingly, if the ratio (CWA/CLA) of the first channel width CWA of the third thin film transistor Qc to the first channel length CLA thereof is greater than the ratio (CWB/CLB) of the second channel width CWB of the fourth thin film transistor Qd to the second channel length CLB thereof, the amount of current transmitted through the third thin film transistor Qc is increased such that the third subpixel electrode191cis applied with the third data voltage that has the intermediate value between the first data voltage transmitted through the first data line171aand the second data voltage transmitted through the second data line171bbut is closer to the first data voltage than the second data voltage.

On the contrary, if the ratio (CWA/CLA) of the first channel width CWA of the third thin film transistor Qc to the first channel length CLA thereof is smaller than the ratio (CWB/CLB) of the second channel width CWB of the fourth thin film transistor Qd to the second channel length CLB thereof, influence of the second data voltage is increased such that the third subpixel electrode191cis applied with the third data voltage that has an intermediate value between the first data voltage transmitted through the first data line171aand the second data voltage transmitted through the second data line171bbut is closer to the second data voltage than the first data voltage.

Accordingly, the third data voltage applied to the third subpixel electrode191ccan be controlled by varying the ratio (CW/CL) of the channel widths CW to the channel lengths CL of the third and fourth thin film transistors Qc and Qd.

In the liquid crystal display according to an embodiment, the ratio (CW/CL) of the channel width CW of the third thin film transistor Qc to the channel length CL thereof is substantially equal to or different from the ratio (CW/CL) of the channel width CW of the third thin film transistor Qd to the channel length CL thereof CL.

The first subpixel electrode191a,the second subpixel electrode191b,and the third subpixel electrode191cthat are applied with the data voltages generate an electric field together with the common electrode270of the upper display panel200so as to determine a direction of the liquid crystal molecules of the liquid crystal layer3between the two electrodes191and270.

As described above, luminance of light passing through the liquid crystal layer3is varied depending on the direction of the liquid crystal molecules.

Sides of the first to fourth minute branch portions194a,194b,194c,and194ddistort the electric field to make horizontal components that determine tilt directions of liquid crystal molecules31.

The horizontal components of the electric field are substantially parallel to the sides of the first to fourth minute branch portions194a,194b,194c,and194d.

Thus, as shown inFIG. 5, the liquid crystal molecules31are inclined in a direction parallel to a longitudinal direction of the minute branch portions194a,194b,194c,and194d.

Since one basic electrode199includes the four subregions Da to Dd in which longitudinal directions of the minute branch portions194a,194b,194c,and194dare different from each other, the liquid crystal molecules31are inclined in four different directions to form four domains having different alignment directions of the liquid crystal molecules31in the liquid crystal layer3.

As such, if the liquid crystal molecules are variously inclined, a reference viewing angle of the liquid crystal display becomes wider.

Returning toFIGS. 3 and 4, the upper panel200will now be described.

A light block220is disposed on a second insulation substrate210.

The light block may be a black matrix, and prevents light leakage.

A color filter230is disposed on the second insulation substrate210and the light block220.

The color filter230may be elongated in a vertical direction along the adjacent data lines171aand171b.

Each color filter230may display one of primary colors such as, for example, red, green, and blue.

However, the light block220and the color filter230may be disposed on the lower display panel100rather than the upper panel200.

An overcoat250is disposed on the light block220and the color filter230.

The overcoat250prevents the color filter230and the light block220from being lifted, and suppresses contamination of the liquid crystal layer3by an organic material such as a solvent flowing from the color filter230, thereby preventing defects such as an afterimage generated when a screen is driven.

The common electrode270is disposed on the overcoat250.

Alignment layers (not shown) are formed at inner sides of the display panels100and200, and may be vertical alignment layers.

Polarizers (not shown) are provided at outer sides of the two display panels100and200, transmissive axes of the two polarizers are perpendicular to each other, and one of the transmissive axes thereof may be parallel to the gate line121.

However, the polarizer may be disposed at an outer side of one of the two display panels100and200.

The liquid crystal layer3has negative dielectric anisotropy, and the liquid crystal molecules31of the liquid crystal layer3are aligned such that their long axes are perpendicular with respect to the surfaces of the two display panels100and200when no electric field is applied.

Thus, the incident light does not pass through the crossed polarizers but is blocked when no electric field is applied.

At least one of the liquid crystal layer3and the alignment layer may include a photo-reactive material, such as, for example, a reactive mesogen.

The liquid crystal display according to an embodiment includes the first subpixel electrode191athat is applied with the first data voltage, the second subpixel electrode191bthat is applied with the second data voltage, and the third subpixel electrode191cthat is applied with the third data voltage between the first and second data voltages.

As described above, the first and second data voltages are obtained from one image signal, and respectively have different values.

In addition, the first data voltage may be greater than the second data voltage.

Accordingly, the electric field applied to the liquid crystal layer corresponding to the first subpixel electrode191ais the greatest while the electric field applied to the liquid crystal layer corresponding to the second subpixel electrode191bis smallest, and the electric field applied to the liquid crystal layer corresponding to the third subpixel electrode191cis smaller than the electric field applied to the liquid crystal layer corresponding to the first subpixel electrode191aand greater than the electric field applied to the liquid crystal layer corresponding to the second subpixel electrode19lb.

As described above, the display device according to an embodiment divides one pixel area into a region where the first subpixel electrode191ato which the relatively high first data voltage is applied is disposed, a region where the second subpixel electrode191bto which the relatively low data voltage is applied is disposed, and a region where the third subpixel electrode191cto which the third data voltage between the first and second data voltages is applied is disposed

Accordingly, the electric fields applied to the liquid crystal molecules corresponding to the first subpixel electrode, the second subpixel electrode, and the third subpixel electrode become different and thus inclined angles of the liquid crystal molecules become different. As a result, each region has a different luminance.

As such, when one pixel area is divided into three regions of different luminance, the transmittance is prevented from being abruptly changed at the side even at a low grayscale or a high grayscale by smoothly controlling the transmittance according to grayscale, such that the side visibility can be similar to the front visibility and the accurate gray expression is possible even at the low grayscale or the high grayscale.

In addition, as described above, the third data voltage applied to the third subpixel electrode has the intermediate value between the first data voltage applied to the first subpixel electrode and the second data voltage applied to the second subpixel electrode, and the third data voltage applied to the third subpixel electrode can be adjusted by controlling the ratio (CW/CL) of the channel width CW to the channel length CL of the third thin film transistor connected to the first data line for transmitting the first data voltage and the ratio (CW/CL) of the channel width CW to the channel length CL of the fourth thin film transistor connected to the second data line for transmitting the second data voltage.

An experimental example of will now be described with reference toFIG. 6.

FIG. 6is a graph showing transmittance of the liquid crystal display according to grayscale in the experimental example.

In the experimental example, the transmittance X of the liquid crystal display according to grayscale when viewed from a front side thereof and the transmittances Y1and Y2according to grayscale when viewed from a lateral side thereof are compared with respect to a first case and a second case. The first case is a conventional liquid crystal display in which one pixel area is divided into a region where the first subpixel electrode to which the relatively high first data voltage is applied is disposed, and a region where the second subpixel electrode to which the relatively low data voltage is applied is disposed. The second case is an embodiment in which one pixel area is divided into a region where the first subpixel electrode to which the relatively high first data voltage is applied is disposed, a region where the second subpixel electrode to which the relatively low data voltage is applied is disposed, and a region where the third subpixel electrode to which the third data voltage between the first and second data voltages is applied is disposed.

InFIG. 6, the transmittance of the first case according to grayscale when viewed from the lateral side thereof is represented as Y1, while the transmittance of the second case according to grayscale when viewed from the lateral side thereof is represented as Y2

Referring toFIG. 6, when compared with the transmittance Y1of the first case according to grayscale when viewed from the lateral side thereof, it can be seen that the transmittance Y2of the second case according to grayscale when viewed from the lateral side thereof is closer to the transmittance X of the liquid crystal display according to grayscale when viewed from the front side thereof.

Particularly, similar to the liquid crystal display according to an embodiment, it can be seen that the transmittance is slowly increased throughout the low grayscale and the high grayscale in the second case in which one pixel area is divided into the region where the first subpixel electrode to which the relatively high first data voltage is applied is disposed, the region where the second subpixel electrode to which the relatively low data voltage is applied is disposed, and the region where the third subpixel electrode to which the third data voltage between the first and second data voltages is applied is disposed. The second case is different from the first case in which the transmittance is abruptly increased in the low or middle grayscale or abruptly decreased in the high grayscale.

As described above, in the liquid crystal display according to an embodiment, it can be seen that the transmittance according to grayscale is slowly changed such that accurate gray expression is possible.

Accordingly, the liquid crystal display according to an embodiment may prevent picture quality deterioration that may occur when the gray expression becomes difficult.

A liquid crystal display according to another embodiment will now be described with reference toFIGS. 7 to 10.

FIG. 7is a layout view of the liquid crystal display according to an embodiment,FIG. 8is a cross-sectional view of the liquid crystal display ofFIG. 7taken along the line VIII-VIII,FIG. 9is a cross-sectional view of the liquid crystal display ofFIG. 7taken along the line IX-IX, andFIG. 10is a cross-sectional view of the liquid crystal display ofFIG. 7taken along the line X-X.

Referring toFIGS. 7 to 10, the liquid crystal display according to an embodiment includes a lower display panel100and an upper display panel200that face each other, and a liquid crystal layer3interposed between the two display panels100and200.

The lower panel100will be described first.

A gate line121and a storage voltage line131are disposed on a first insulation substrate110.

The gate line121includes a first gate electrode124a,a second gate electrode124b,a third gate electrode124c,and a fourth gate electrode124d.

The storage voltage line131includes storage electrodes132and133.

A gate insulating layer140is disposed on the gate line121and the storage voltage line131.

A first semiconductor154a,a second semiconductor154b,a third semiconductor154c,and a fourth semiconductor154dare disposed on the gate insulating layer140.

The first semiconductor154a,the second semiconductor154b,the third semiconductor154c,and the fourth semiconductor154dmay contain, for example, amorphous silicon, crystalline silicon, or an oxide semiconductor.

Ohmic contacts163aand165aare disposed on the first semiconductor154a,the second semiconductor154b,the third semiconductor154c,and the fourth semiconductor154d.

In embodiments where the first semiconductor154a,the second semiconductor154b,the third semiconductor154c,and fourth semiconductor154dinclude an oxide semiconductor, the ohmic contacts may be omitted.

A first data line171a,a second data line171b,a first drain electrode175a,a second drain electrode175b,a third drain electrode175c,and a fourth drain electrode175dare disposed on the ohmic contacts163aand165a.

The first and second data lines171aand171btransmit a data signal, and mainly extend in a vertical direction to cross the gate line121.

The first data line171aincludes a first source electrode173athat extends toward the first gate electrode124a,and a third source electrode173cthat extends toward the third gate electrode124c.

The first and third source electrodes173aand173care connected to each other.

The second data line171bincludes a second source electrode173bthat extends toward the second gate electrode124b,and a fourth source electrode173dthat extends toward the fourth gate electrode124d.

The second and fourth source electrodes173band173dare connected to each other.

One end portion of the first drain electrode175ais partially enclosed by the first source electrode173a,one end portion of the second drain electrode175bis partially enclosed by the second source electrode173b,one end portion of the third drain electrode175cis partially enclosed by the third source electrode173c,and one end portion of the fourth drain electrode175dis partially enclosed by the fourth source electrode173d.

The third and fourth drain electrodes175cand175dare connected to each other.

The first through fourth gate electrodes124a,124b,124c,and124d,the first through fourth source electrodes173a,173b,173c,and173d,and the first through fourth drain electrodes175a,175b,175c,and175dform the first through fourth thin film transistors (TFTs)154a,154b,154c,and154d,which are the first through fourth switching elements Qa, Qb, Qc, and Qd, together with the first through fourth semiconductors154a,154b,154c,and154d.Channels of the thin film transistors are respectively formed in the first through fourth semiconductors154a,154b,154c,and154dbetween the first through fourth source electrodes173a,173b,173c,and173dand the first through fourth drain electrodes175a,175b,175c,and175d.

Except for the channel regions, the semiconductors154a,154b,154c,and154dhave substantially the same planar shape as the data lines171aand171b,the source electrodes173a,173b,173c,and173d,the drain electrodes175a,175b,175c,and175d,and the ohmic contacts163aand165a.

A first passivation layer180ais disposed on exposed portions of the data lines171aand171b,the drain electrodes175a,175b,175c,and175d,and exposed portions of the semiconductors154a,154b,154c,and154d.

A first part191a1of a first subpixel electrode191aand a first part191c1of a third subpixel electrode191care disposed on the first passivation layer180a.

The first part191a1of the first subpixel electrode191aand the first part191c1of the third subpixel electrode191care respectively disposed in a first pixel area Ra and a second pixel area Rb.

The first part191a1of the first subpixel electrode191aand the first part191c1of the third subpixel electrode191chave a shape in which four trapezoids are respectively combined to enclose a center part of the first and second pixel areas, the first part191a1of the first subpixel electrode191aincludes a first connection portion96athat is disposed at a center part of the first pixel area Ra, and the first part191c1of the third subpixel electrode191cincludes a second connection portion96bthat has a cross shape and traverses a center part of the second pixel area Rb.

A second passivation layer180bis disposed on the first part191a1of the first subpixel electrode191aand the first part191c1of the third subpixel electrode191c.

The second passivation layer180bis formed with a fourth contact hole186athat exposes the first connection portion96aof the first part191a1of the first subpixel electrode191a,and a fifth contact hole186bthat exposes the second connection portion96bof the first part191c1of the third subpixel electrode191c.

A second part191a2of the first subpixel electrode191a,a first part191b1of the second subpixel electrode191b,a second part191c2of the third subpixel electrode191c,and a second part191b2of the second subpixel electrode191bare disposed on the second passivation layer180b.The first thin film transistor Qa, the second thin film transistor Qb, the third thin film transistor Qc, and the fourth thin film transistor Qd are disposed between the first subpixel electrode191aand the third subpixel electrode191c,and the first thin film transistor, the second thin film transistor, the third thin film transistor, and the fourth thin film transistor are disposed between the a first part191b1of the second subpixel electrode191band second part191b2of the second subpixel electrode191b.

The second part191a2of the first subpixel electrode191aand the first part191b1of the second subpixel electrode191bare disposed in the first pixel area Ra, and the second part191c2of the third subpixel electrode191cand the second part191b2of the second subpixel electrode191bare disposed in the second pixel area Rb.

The second part191a2of the first subpixel electrode191ais disposed in a center portion of the first pixel area Ra that the first part191a1of the first subpixel electrode191aencloses, and is connected to the first part191a1of the first subpixel electrode191athrough the fourth contact hole186a.

The first part191b1of the second subpixel electrode191bis formed at a position to enclose the second part191a2of the first subpixel electrode191a.

The second part191a2of the first subpixel electrode191aand the first part191b1of the second subpixel electrode191bare spaced apart from each other, and similar to the basic electrode199illustrated inFIG. 5, include a plurality of minute branch portions that respectively extend in different directions.

The second part191c2of the third subpixel electrode191cis disposed in a center portion of the second pixel area Rb that the first part191c1of the third subpixel electrode191cencloses, and is connected to the first part191c1of the third subpixel electrode191cthrough the fifth contact hole186b.

The second part191b2of the second subpixel electrode191bis formed at a position to enclose the second part191c2of the third subpixel electrode191c.

The second part191c2of the third subpixel electrode191cand the second part191b2of the second subpixel electrode191bare spaced apart from each other, and similar to the basic electrode199illustrated inFIG. 5, include a plurality of minute branch portions that respectively extend in different directions.

The first part191a1of the first subpixel electrode191aincludes a third extended portion196a,the first and second passivation layers180aand180bare formed with the third extended portion196aof the first part191a1of the first subpixel electrode191aand a seventh contact hole187athat exposes a wide end portion of the first drain electrode175a,and the first connector93ais disposed on the seventh contact hole187a.

The first part191a1of the first subpixel electrode191ais connected to the first drain electrode175athrough the first connector93asuch that it is applied with the first data voltage transmitted through the first data line171a.

The first part191c1of the third subpixel electrode191cincludes a fourth extended portion196b,the first and second passivation layers180aand180bare formed with the fourth extended portion196bof the first part191c1of the third subpixel electrode191cand an eighth contact hole187bexposing a wide connection portion that connects the third drain electrode175cto the fourth drain electrode175d,and the second connector93bis disposed on the eighth contact hole187a.

The first part191c1of the third subpixel electrode191cis connected to the third and fourth drain electrodes175cand175dthrough the second connector93b.

The first and second passivation layers180aand180bare formed with a ninth contact hole187cthat exposes an extended portion of the second drain electrode175b.

The first and second parts191b1and191b2of the second subpixel electrode191bare connected to the second drain electrode175bthrough the ninth contact hole187csuch that it is applied with the second data voltage from the second drain electrode175b.

The first and second data voltages are obtained from one image signal, and respectively have different values.

The first data voltage may be greater than the second data voltage.

The first part191c1of the third subpixel electrode191cis applied with a third data voltage between the first and second data voltages from the third and fourth drain electrodes175cand175d.

The second part191a2of the first subpixel electrode191ais connected to the first connection portion96aof the first part191a1of the first subpixel electrode191athrough the fourth contact hole186asuch that it is applied with the first data voltage.

Similarly, the second part191c2of the third subpixel electrode191cis connected to the second connection portion96bof the first part191c1of the third subpixel electrode191cthrough the fourth contact hole186bsuch that it is applied with the third data voltage.

If a first channel width CWA and a first channel length CLA of the third thin film transistor Qc connected to the first data line171aare equal to a second channel width CWB and a second channel length CLB of the fourth thin film transistor Qd connected to the second data line171b,the third subpixel electrode191cis applied with the third data voltage that has an intermediate value between the first data voltage transmitted through the first data line171aand the second data voltage transmitted through the second data line17lb.

However, if a first ratio (CWA/CLA) of the first channel width CWA of the third thin film transistor Qc to the first channel length CLA thereof is greater than a ratio (CWB/CLB) of the second channel width CWB of the fourth thin film transistor Qd to the second channel length CLB thereof, influence of the first data voltage transmitted through the third thin film transistor Qc is increased such that the third subpixel electrode191cis applied with the third data voltage that has the intermediate value between the first data voltage transmitted through the first data line171aand the second data voltage transmitted through the second data line171bbut is closer to the first data voltage than the second data voltage.

On the contrary, if the ratio (CWA/CLA) of the first channel width CWA of the third thin film transistor Qc to the first channel length CLA thereof is smaller than the ratio (CWB/CLB) of the second channel width CWB of the fourth thin film transistor Qd to the second channel length CLB thereof, influence of the second data voltage is increased such that the third subpixel electrode191cis applied with the third data voltage that has the intermediate value between the first data voltage transmitted through the first data line171aand the second data voltage transmitted through the second data line171bbut is closer to the second data voltage than the first data voltage.

Accordingly, the third data voltage applied to the third subpixel electrode191ccan be controlled by varying the ratios (CW/CL) of the channel widths CW to the channel lengths CL of the third and fourth thin film transistors Qc and Qd.

One pixel area includes the first pixel area Ra and the second pixel area Rb.

A size of the first pixel area Ra may be substantially equal to or larger than that of the second pixel area Rb.

The first part191a1of the first subpixel electrode191a,the second part191a2of the first subpixel electrode191a,and the first part191b1of the second subpixel electrode191bare disposed in the first pixel area Ra.

The first pixel area Ra includes a first region R1in which the second part191a2of the first subpixel electrode191ato which the first data voltage is applied is disposed, a second region R2in which the first part191a1of the first subpixel electrode191ato which the first data voltage is applied partially overlaps the first part191b1of the second subpixel electrode191bto which the second data voltage is applied, and a third region R3ain which a part of the first part191b1of the second subpixel electrode191bto which the second data voltage is applied is disposed.

In the second region R2, together with an electric field formed between the first part191b1of the second subpixel electrode191bto which the second data voltage is applied and the common electrode270, an electric field formed between the first part191a1of the first subpixel electrode191adisposed between the plurality of branch electrodes of the first part191a1of the first subpixel electrode191aand the common electrode270is applied to the liquid crystal layer.

Thus, the electric field applied to the liquid crystal layer of the second region R2is smaller than that applied to the liquid crystal layer of the first region R1, but is greater than that applied to the liquid crystal layer of the third region R3a.

The first part191c1of the third subpixel electrode191c,the second part191c2of the third subpixel electrode191c,and the second part191b2of the second subpixel electrode191bare disposed in the second pixel area Rb.

The second pixel area Rb includes a fourth region R4in which the second part191c2of the third subpixel electrode191cto which the third data voltage is applied is disposed, a fifth region R5in which the first part191c1of the third subpixel electrode191cto which the third data voltage is applied partially overlaps the second part191b2of the second subpixel electrode191bto which the second data voltage is applied, and a sixth region R3bin which a part of the second part191b1of the second subpixel electrode191bto which the second data voltage is applied is disposed.

In the fifth region R5, together with an electric field formed between the first part191c1of the third subpixel electrode191cto which the third data voltage is applied and the common electrode270, an electric field formed between the first part191c1of the third subpixel electrode191cdisposed between a plurality of branch electrodes of the second part191b2of the second subpixel electrode191b2and the common electrode270is applied to the liquid crystal layer.

Thus, the electric field applied to the liquid crystal layer of the fifth region R5is smaller than that applied to the liquid crystal layer of the fourth region R4, but is greater than that applied to the liquid crystal layer of the sixth region R3b.

In addition, the electric field applied to the third region R3ais equal to that applied to the sixth region R3b.

The liquid crystal display according to an embodiment divides one pixel area into the first region R1, the second region R2, the fourth region R4, the fifth region R5, the third region R3a,and the sixth region R3bto which the different electric fields are respectively applied.

As such, by dividing one pixel area into five regions to which the different electric fields are respectively applied, the electric fields are differently applied to the liquid crystal molecules corresponding to the five regions such that the liquid crystal molecules are differently inclined to form the regions of different luminance.

As such, if one pixel area is divided into the five regions of different luminance, the transmittance is prevented from being abruptly changed at the side even at the low grayscale or the high grayscale by smoothly controlling the transmittance according to grayscale, such that the side visibility can be similar to the front visibility and the accurate gray expression is possible even at the low grayscale and the high grayscale.

Another experimental example will now be described with reference toFIG. 11.

FIG. 11is a graph showing transmittance of the liquid crystal display according to grayscale in another experimental example.

In the experimental example, the transmittance X of the liquid crystal display according to grayscale when viewed from a front side thereof and the transmittances Y3and Y4thereof according to grayscale when viewed from the lateral side thereof are compared with respect to a third case and a fourth case. The third case is a conventional liquid crystal display, in which one pixel area is divided into a region where the first subpixel electrode to which the relatively high first data voltage is applied is disposed, and a region where the second subpixel electrode to which the relatively low data voltage is applied is disposed. The fourth case is an embodiment in which one pixel area is divided into the five regions to which the electric fields are differently applied.

InFIG. 11, the transmittance of the third case according to grayscale when viewed from the lateral side thereof is represented as Y3, while the transmittance of the fourth case according to grayscale when viewed from the lateral side thereof is represented as Y4.

Referring toFIG. 11, when compared with the transmittance Y3of the third case according to grayscale when viewed from the lateral side thereof, it can be seen that the transmittance Y4of the fourth case according to grayscale when viewed from the lateral side thereof is closer to the transmittance X according to grayscale when viewed from the lateral side thereof.

While this invention has been described in connection with certain embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.