Light emitting apparatus, driving circuit of light emitting element, and driving method

A light emitting apparatus includes a light emitting element, a driving circuit which has a driving transistor having a gate, a drain, and a source, and a capacitor having one end connected to the gate, a power line, and first and second voltage lines, and, in a period in which the gate and the drain are short-circuited and the drain and the light emitting element are blocked, the source is connected to the first voltage line and the other end of the capacitor is connected to the second voltage line to hold a voltage in the capacitor, and, in a period in which the gate and the drain are disconnected and the drain and the light emitting element are connected, the source is connected to the power line, and the other end of the capacitor is connected to the source to supply a current to the light emitting element.

BACKGROUND OF THE INVENTION

1. Field of the Invention

One disclosed aspect of the embodiments relates to a light emitting apparatus and a driving circuit of a light emitting element and, more particularly, relates to a light emitting apparatus which uses organic electroluminescence device (referred to as an “organic EL element” below) as light emitting elements.

2. Description of the Related Art

An organic EL element is a light emitting element which is formed by sandwiching an organic compound layer between two electrodes, and emits light at brightness matching a current flowing between the electrodes. An application of a light emitting apparatus which uses organic EL elements is a display apparatus in which organic EL elements are arranged in a matrix on a plane. Other applications are an exposure apparatus of an electrophotographic printer in which organic EL elements are provided in a one-dimensional array and a lighting apparatus which emits light of a wide area.

Since a large current flows in an organic EL element upon light emission and a resistance of a conductive line from a power source to a driving circuit of the organic EL element (referred to as a “power line” below) is usually high, a voltage significantly drops along the power line and a voltage applied to the organic EL elements decreases. In a light emitting apparatus in which multiple driving circuits of the organic EL elements are arranged along a power line, the voltage drop results in a difference of a power voltage between an organic EL element close to a power source and an organic EL element far from the power source. This power voltage gradation occurs not only in the power line of an anode side but in a power line of a cathode side of the organic EL element.

Meanwhile, a voltage signal which determines light emission luminance is applied to the driving circuit of the organic EL element through a data line. A current only transiently flows in the data line, and therefore the voltage drops along the data line very little compared to the power line. Hence, the voltage signal is written in the driving circuits irrespectively of the voltage gradation along the power line.

The driving circuit generates a current according to the written signal voltage, and supplies the current to the organic EL element. The current is generated in the driving circuit based on the signal voltage relative to the power voltage. Therefore, even though a signal voltage is uniform, the currents generated in the driving circuits are not uniform due to the gradation of the power voltage.

Japanese Patent Application Laid-Open No. 2006-308845 discloses an embodiment of a driving circuit which first disconnects both ends of a capacitor for holding a signal from the driving circuit, applies a fixed voltage to one end, applies a signal voltage to the other end, and finally connects the capacitor to the driving circuit while maintaining the voltage between both ends of the capacitor. Thus, a current irrespective of the power voltage is generated.

In another embodiment of the patent application, two capacitors are disposed in the driving circuit and a signal voltage is written in a capacitor and a threshold voltage of a driving transistor is held in another capacitor. By connecting the capacitors to the driving circuit, a sum of the signal voltage and the threshold voltage is applied to the driving transistor to generate a current irrespectively of the threshold voltage.

A conventional driving circuit requires two capacitors to cancel variation of the threshold voltage of the driving transistor and cancel influence of variation of the power voltage. Since capacitors occupy a large portion of a pixel area, it is difficult to reduce a pixel size and improve precision of the display.

SUMMARY OF THE INVENTION

One disclosed aspect of the embodiments is to suppress variation of the driving current caused by the power source voltage variation without increasing the number of capacitors in a driving circuit.

A first aspect is a light emitting apparatus comprising:

a light emitting element;

a driving circuit including a driving transistor, a first switch provided between a gate and a drain of the driving transistor, a second switch provided between the drain of the driving transistor and one end of the light emitting element and a capacitor one end of which is connected to the gate of the driving transistor;

a power line configured to supply a power source voltage to the driving circuit, and

a first voltage line and a second voltage line configured to supply a first voltage and a second voltage, respectively, to the driving circuit, wherein

the driving circuit includes a third switch which connects a source of the driving transistor to the power line and the first voltage line alternately, and a fourth switch which connects the other end of the capacitor to the source of the driving transistor and the second voltage line alternately, and

the first to fourth switches are controlled such that,

in a first period in which the first switch is on and the second switch is off, the third switch connects the source of the driving transistor to the first voltage line and the fourth switch connects the other end of the capacitor to the second voltage line, and

in a second period in which the first switch is off and the second switch is on, the third switch connects the source of the driving transistor to the power line and the fourth switch connects the other end of the capacitor to the source of the driving transistor.

A second aspect is

a plurality of driving circuits aligned along a common power line and individually supplying a current to a light emitting element, each of the driving circuits comprising:

a driving transistor;

a capacitor one end of which is connected to a gate of the driving transistor;

a first switch connecting the gate of the driving transistor to a drain of the driving transistor;

a second switch connecting the drain of the driving transistor to the light emitting element;

a third switch connecting a source of the driving transistor to the power line and a first voltage line alternately;

a fourth switch connecting the other end of the capacitor to the source of the driving transistor and the second voltage line alternately; and

at least one control line configured to control the first to fourth switches.

A third aspect is a method of driving a light emitting element using a driving circuit connected to a power line, a first voltage line, and a second voltage line, wherein

the driving circuit includes: a driving transistor; a capacitor one end of which is connected to a gate of the driving transistor; a first switch connecting the gate of the driving transistor to a drain of the driving transistor; a second switch connecting the drain of the driving transistor to the light emitting element; a third switch connecting a source of the driving transistor to the power line and the first voltage line alternately; and a fourth switch connecting the other end of the capacitor to the source of the driving transistor and the second voltage line alternately,

the method comprising:

turning on the first switch, turning off the second switch, connecting the source of the driving transistor to the first voltage line by means of the third switch and connecting the other end of the capacitor to the second voltage line by means of the fourth switch; and

turning off the first switch, turning on the second switch, connecting the source of the driving transistor to the power line by means of the third switch and connecting the other end of the capacitor to the source of the driving transistor by means of the fourth switch.

An embodiment may suppress variation of luminance caused by fluctuation of a power voltage.

DESCRIPTION OF THE EMBODIMENTS

While disconnecting one terminal of a capacitor of a driving circuit and a source terminal of a driving transistor from the driving circuit, a fixed voltage and a signal voltage are applied to these terminals to hold both of a threshold voltage and a signal voltage in the capacitor. By reconnecting these terminals to the driving circuit, a current irrespective of the threshold voltage and the power voltage is generated.

Embodiments of a light emitting apparatus will be described below using drawings. One disclosed feature of the embodiments may be described as a process which is usually depicted as a timing diagram. A timing diagram may illustrate the timing relationships of several entities, such as signals, events, etc. Although a timing diagram may describe the operations as a sequential process, some operations may be performed in parallel or concurrently. In addition, unless specifically stated, the order of the operations or timing instants may be re-arranged. Furthermore, the timing or temporal distances may not be scaled or depict the timing relationships in exact proportions.

FIG. 1is a view illustrating the driving circuit of a light emitting apparatus.

A driving circuit100has a driving transistor M1, a charging element or capacitor C1, and first to fourth switches SW1, SW2, SW3, and SW4.

The driving transistor M1is a P channel type MOS transistor. A source S of the driving transistor M1is connected to one terminal31of a third switch SW3and a second terminal42of a fourth switch SW4. A gate G is connected to one terminal of the capacitor C1and is simultaneously connected to a terminal11of a first switch SW1. A drain D is connected to another terminal12of the first switch SW1and one terminal21of the second switch.

One end of the capacitor C1is connected to a gate of the driving transistor M1, and the other end is connected to a first terminal41of the fourth switch SW4.

An anode of the organic EL element EL is connected to the second terminal22of the second switch SW2, and a cathode is connected to a ground line64.

The first switch SW1and the second switch SW2are two-terminal switches which switch on and off. The third and fourth switches are both three-terminal switches, and enter one of a state in which the first terminal and the second terminal are connected and the first and third terminals are disconnected, and a state in which the first terminal and the second terminal are disconnected and the first and third terminals are connected. The first to fourth switches are connected with control lines which are not illustrated, and connection states are controlled according to a control signal which takes a binary value of H (high) and L (low).

In the driving circuit100, a power line60, a first voltage line61, a second voltage line62and a ground line64are arranged. The power line60applies a power voltage Voled to the second terminal32of the third switch SW3. The first voltage line61applies a voltage V1to the third terminal33of the third switch SW3, and the second voltage line62applies a voltage V2to the third terminal43of the fourth switch SW4. The ground line64applies a common potential Vcom to the cathode of the organic EL element EL.

A signal voltage which determines light emission luminance of the organic EL element is written in the driving circuit as a difference between the voltage V1of the first voltage61and the voltage V2of the second voltage line62.

The driving circuit100extracts a current according to a gate-source voltage from the power line when the source S of the driving transistor M1is connected to the power line60through the third switch SW3. A drain current is supplied to the organic EL element EL when the second switch SW2is on, and flows between an anode A and a cathode K. The organic EL element EL emits light at luminance matching this current.

The first to fourth switches SW1to SW4are applied control signals as indicated by arrows inFIG. 2, and connection states thereof may be switched.

FIG. 2is a timing chart illustrating connection process of the first to fourth switches SW1to SW4, and the gate voltage Vg of the driving transistor.

A time interval between t1and t2is a period in which the voltage is written in the capacitor C1, and the first switch SW1is turned on, the second switch SW2is turned off, the third switch SW3is turned on the third terminal side, that is, the first terminal and the third terminal are connected, and the first and the second terminal are turned off. The fourth switch SW4is also in an on state on the third terminal side. (InFIG. 2, this state is indicated as 1-3on, and an opposite state is indicated as 1-2on.) The source S of the driving transistor M1is connected to the first voltage line61, and receives a supply of the first voltage V1. A terminal of the capacitor C1on an opposite side of the gate G of the driving transistor is connected to the second voltage line62, and receives the second voltage V2.

The voltage of the gate G of the driving transistor M1in this period is indicated as Vg inFIG. 2. A current (drain current) supplied from the first voltage line61and flowing between the source and the drain of the driving transistor M1passes the first switch SW1and flows into the capacitor C1. This current raises the voltage (that is, the gate voltage Vg) of the terminal of the capacitor C1which is connected to the gate of the driving transistor M1. A rise in the gate voltage Vg decreases a voltage between the gate and the source of the driving transistor M1, and, when the voltage becomes close to the threshold voltage Vth of the driving transistor M1, the drain current then also becomes small. In a sufficiently long time, the voltage of the gate G of the driving transistor M1becomes V1−Vth, and both end voltage dV of the capacitor C1is V2−V1+Vth with a gate side as a negative side.

The voltage held in the capacitor C1at a time t2includes the threshold voltage Vth of the driving transistor. This is a result of an operation of charging the capacitor C1by means of a current flowing in the driving transistor M1. This operation enables only one capacitor C1to hold a signal voltage (V2−V1) which specifies luminance and the threshold voltage Vth of the driving transistor.

After the time t2, the first switch SW1is turned off, the second switch SW2is turned on, the third switch SW3is turned on the second terminal side, and the fourth switch SW4is turned on the second terminal side. The source S of the driving transistor M1is connected to the power line60, and the terminal of the capacitor C1on an opposite side of the gate of the driving transistor is connected to the source S of the driving transistor. As a result, the source S of the driving transistor M1is the power voltage Voled, and a voltage dV=V2−V1+Vth held in the capacitor C1is applied between the gate and source of the driving transistor M1. This voltage is a voltage with a source side as a positive side and a gate side as a negative side, and, in a P channel type MOS transistor, by setting V2>V1, the driving transistor M1is turned on and a drain current determined by V2−V1flows. In this case, the current generated by the driving circuit100depends on neither the power voltage Voled nor the threshold voltage Vth.

The drain current is determined by V2−V1when an anode voltage of an organic EL element, that is, a drain voltage of the driving transistor M1is lower than a gate voltage, in other words, the driving transistor M1operates in a saturated region. This is guaranteed by setting sufficiently high Voled.

If there is no third switch SW3and the source of the driving transistor M1is connected to the power line60at all times, the both-end voltage of the capacitor C1at the time t2is V2−Voled+Vth and the drain current subsequent to t2depends on the voltage Voled of the power line60. The power line60is a conductive line which is led from the original power source which generates a power voltage and is laid in the driving circuit100and has a resistance, and the voltage applied to the driving circuit100takes a value which differs depending on a current flowing in the power line. When a power line reaching the driving circuit100from a power source is connected to another same driving circuit, fluctuation of a power voltage also depends on a current to be supplied to this driving circuit.

By contrast with this, during a period in which a voltage is written in the capacitor C1, the driving transistor M1is disconnected from a power line and is connected to another (first) voltage line61, so that the resulting power voltage is not influenced by fluctuation.

During a t1−t2period, a current flowing in a first voltage line is a transient current flowing in the capacitor C1and becomes small as the time passes, and, at the time t2, little current flows. Hence, even if the first voltage line has a high resistance, fluctuation of the voltage V1does not actually a problem. Although the current flowing in the first voltage line61also flows in the second voltage line62through the capacitor C1, the second voltage V2may not fluctuate for the same reason.

A time subsequent to the time t2is a period in which a drain current which is determined by V2−V1flows from the driving transistor M1to an organic EL element EL, and the organic EL element emits light. Light emission started at t2ends at a time t7, and a new signal voltage is written in the same driving circuit100at a time subsequent to t7.

Hereinafter, the t1−t2period is referred to as a “first period” or a “writing period”, and a t2−t7period is referred to as a “second period” or a “light emission period”.

With the circuit inFIG. 1, the driving transistor M1is a P channel type MOS transistor, and, upon V2>V1, a drain flows. Although, generally, a signal voltage Vdata which determines luminance of an organic EL element is applied as V2to the second voltage line62and the voltage V1of the first voltage line is fixed, by contrast with this, the signal voltage Vdata may be applied to the first voltage line61and a fixed voltage may be applied to the second voltage line.

Although, when a writing period is sufficiently long, a current flowing in the capacitor C1from the driving transistor M1through the first switch SW1becomes zero, the writing time is actually finite, and the writing period ends before the current becomes zero. In this case, an influence of the voltage held in the capacitor C1before writing starts (before t1) is left. To prevent this, a period (referred to as a “third period” or an “initialization period”) in which the voltage of the capacitor C1is initialized may be provided prior to t1. The capacitor C1may be initialized by turning the first switch and the second switch on, flowing the current in a state in which the driving transistor M1is provided in diode connection and holding in the capacitor C1a sufficiently high voltage exceeding a threshold voltage of the driving transistor M1. In this case, a stationary current flows in the driving transistor M1, and, preferably, the third and fourth switches are placed in the same state as a state upon light emission and receives a supply of a current from the power line60.

Initialization may be performed by applying the above high voltage to both ends of the capacitor C1. This will be described in detail in the second embodiment.

The third and fourth switches are switched at the same timing at all timings, and may be controlled by one control line. In the embodiments described below, upon initialization, a source of a driving transistor is connected to a first voltage line and a terminal on an opposite side of a gate of a capacitor is connected to a second voltage line, so that the second switch is also switched at the same timing as those of the third and fourth switches and these control lines may be combined as one.

Hereinafter, the embodiments will be described in detail. Although a light emitting apparatus which uses organic EL elements will be described as an example in the following embodiments, the disclosure is applicable to a light emitting apparatus which uses light emitting elements such as inorganic EL elements, field emission elements or LEDs, and a driving circuit of the light emitting apparatus.

FIG. 3illustrates a display apparatus in which a plurality of organic EL elements EL as light emitting apparatuses according to the first apparatus and driving circuits100of the organic EL elements are aligned in a matrix pattern of N rows and M columns. N and M are integers equal to or more than two, and, typically, N=480 and M=640×3 hold.

Three control lines71,72and73are provided per row in a row direction, and are given control signals generated by a scanning circuit SCN.

In a column direction crossing the row direction, power lines60, first voltage lines61, and second voltage lines62are provided. The power lines60are arranged every other column, and supplies a power voltage commonly to two columns of driving circuits on both sides. Between columns in which the power lines60are provided, the first power lines61are arranged every other column, and commonly supplies a first voltage V1to neighboring driving circuits of two columns. One second voltage line62is arranged in each column, and supplies a signal voltage V2=Vdata matching luminance of an organic EL element EL.

The power lines60are combined as one outside a pixel matrix, and are connected to a power source PS0. A wiring to commonly connect the power lines60per column and to a power source has the same resistance as those of the power lines60between columns, and forms part of the power lines. The first voltage lines61are also combined as one outside the pixel matrix, and are connected to a power source PS1of a first voltage V1. The second voltage lines62are connected to a signal voltage generating circuit SIG per column.

FIG. 4is a view illustrating a circuit configuration of each pixel of the display apparatus inFIG. 3. The same portions as those inFIG. 1will be assigned the same reference numerals.

In the present embodiment, first to fourth switches SW1to4include MOS transistors. The third and fourth switches are both three-terminal and are complementary switches which turn a first terminal and a third terminal off when the first terminal and a second terminal are on and turn the first terminal and the third terminal on when the first terminal and the second terminal off, and may be formed using two complementary MOS transistors a gate of which is common.

The first switch SW1includes one N channel type MOS transistor M4, and the gate of the first switch SW1receives a supply of a control signal P1from the first control line71. The second switch SW2includes one P channel type MOS transistor M6, and the gate of the second switch SW2receives a supply of a control signal P2from the second control line72. The third switch includes two transistors of a P channel type MOS transistor M7between the first terminal and the second terminal and an N channel type MOS transistor M5between the first terminal and the third terminal. The common gate receives a supply of a control signal P3from the third control line73. Similar to the third switch SW3, the fourth switch SW4includes a P channel type MOS transistor M8between the first terminal and the second terminal and an N channel type MOS transistor M2between the first terminal and the third terminal, and the common gate receives a supply of the control signal P3from the same third control line73as that of the third switch.

FIG. 5is a timing chart illustrating the control signals P1, P2and P3given to three control lines in each row. Numbers in parentheses after P1, P2and P3represent row numbers. AlthoughFIG. 2illustrates an on/off state of each switch, the control signals P1, P2and P3inFIG. 5are voltage signals, and an upper portion indicates an H (high) level and a lower portion indicates an L (low) level.

A time t0−t1is an initialization period of the driving circuits100in the first row, P1=H, P2=L and P3=L signals are given, and a transistor M4which is the first switch SW1and a transistor M6which is the second switch SW2are turned on. With the third switch SW3and the fourth switch SE4, the transistors M7and M8on the second terminal side of each switch are turned on, and the transistors M5and M2on the third terminal side are off. The gate and the drain of the driving transistor M1are short-circuited and provided in diode connection, an initialization current flows between the source and the drain, and an on voltage exceeding the threshold voltage Vth is produced in the capacitor C1.

At the time t1−t2, P1=H, P2=H and P3=H hold, the transistor M4which is the first switch SW1is kept on and the transistor M6which is the second switch SW2is turned off. With the third switch SW3and the fourth switch SW4, the transistors M5and M2on the third terminal side of each switch are turned on, and the transistors M7and M8on the second terminal side are off.

In this case, the source S of the driving transistor M1is connected to the first voltage line61and given the first voltage V1, and the terminal of the capacitor C1on the opposite side of the gate G is connected to the second voltage line62and is given the second voltage V2. The first voltage V1is a fixed reference voltage Vref, and the second voltage V2is a luminance signal Vdata which determines luminance of an organic EL element.

A current flowing in the source S from the first voltage to the driving transistor M1in a writing period of the time t1−t2is outputted from the drain, passes the transistor M4and flows in one terminal of the capacitor C1. The current flowing from the other terminal of the capacitor C1passes the second voltage line62and flows out. This current produces a voltage Vdata−Vref+Vth at both ends of the capacitor C1(with a gate side as a negative side) at the time t2.

Control voltages are switched at the time t2, and become P1=L, P2=L and P3=L. The transistor M4which is the first switch SW1is turned off, and the transistor M6which is the second switch SW2is turned off. With the third switch SW3and the fourth switch SW4, the second terminal side of each switch is turned on, the terminal on the opposite side of the gate G of the capacitor C1is connected to the source S of the driving transistor M1, and the source of the driving transistor M1is connected again to the power line60.

As a result, a current which is determined according to Vdata−Vref flows from the drain D of the driving transistor M1to an anode of an organic EL element EL. When Vdata is higher, the current is higher, and an organic EL element emits light at higher luminance. When Vdata=Vref is true, the current is zero, and the organic EL element does not emit light.

Although there is a light emission period of organic EL elements in the first row after the time t2, initialization of driving circuits in the second row simultaneously starts. The voltage V2of the second voltage line62switches to a signal which determines luminance of organic EL elements in the second row. The driving circuits are initialized at t2−t3, and writing is performed at t3−t4.

Hereinafter, initialization and writing are sequentially performed per row, and writing in the final N-th row is finished at t7.

After writing in all rows is finished, writing in the first row is performed again. Thus, initialization and writing of a signal voltage are performed per row during light emission periods of other rows, and all rows have the same durations of the light emission periods.

In the present embodiment, the power lines60are provided every other row between columns which are not provided with the first voltage lines61, and driving circuits of two columns share power lines in the column direction. By this means, it is possible to widen wiring widths of the power lines60. When the dimension between columns is sufficiently wide, the power line60and the first voltage line61may be provided one by one in each column.

Signal voltages are written per row, and therefore only one of the driving circuits100aligned in one column enters a writing period, and the rest of (N−1) driving circuits are in light emission periods. Hence, in the writing period of a driving circuit in each row, the current flowing toward organic EL elements in the (N−1)th in the light emission period flows toward power lines, and a voltage drops in the power lines60along the column direction. During the light emission period, a voltage drop due to a current to organic EL elements in this row additionally occurs. However, during the writing period, a signal is written separately from a power line and a current is determined by a written voltage in the light emission period, so that light emission luminance of organic EL elements EL is not influenced by a voltage drop of the power lines60.

Although a current also flows to the power line60at a portion which bundles the power line60of each column and connects to the power source PS0, and then a power voltage of each driving circuit also drops in the row direction, a signal voltage to be written and a current upon light emission are not influenced by any power voltage drop, so that there is no variation of luminance in the row direction.

When the transistor M7which is on the second terminal side of the third switch has on resistance, this transistor M7causes a voltage drop, and the voltage of the source S of the driving transistor M1upon light emission is lower than the voltage Voled of the power line60. However, as in the present embodiment, when the second terminal42of the fourth switch SW4is connected to the first terminal of the third switch SW3, that is, the source S of the driving transistor M1though this means the same, a current which is not influenced even by a voltage drop of the transistor M7is generated.

When on resistance of the transistor M7is low and this voltage drop may be ignored, the second terminal of the fourth switch second terminal may be connected to the second terminal of the third switch, that is, the power line60.

The present example is an example of an exposure apparatus of an electrophotographic printer in which organic EL elements are provided in a one-dimensional array and emitted light irradiates a photosensitive body.

FIG. 6is an entire view of an organic EL exposure head which forms a latent image by irradiating a photosensitive drum with light. The same portions as those inFIG. 3will be assigned the same reference numerals.

On a glass substrate1, organic EL elements EL are arranged in a line pattern, and a driving circuit100is connected to each organic EL element. A power line60, a second voltage line62and a ground line64which uses a cathode of an organic EL element as a ground potential Vcom are commonly provided to all organic EL elements and driving circuits along the line. The total number of organic EL elements is 4800 in case of a printer which forms an image of 600 dpi in a lateral direction of an A4 size sheet.

The driving circuits100are grouped into N blocks as one block of which includes M driving circuits, and the M driving circuits in a single block are controlled by the common control lines71,73and74. The number of control lines71,73and74are N, and the control lines71, and74may control driving circuits per block. N control lines sequentially select each block and give a control signal to each block. N and M only need to be integers equal to or more than two, and are typically 4800 in total when N=64 and M 75 are true.

Meanwhile, the first voltage line61which givens a luminance signal to each driving circuit selects a driving circuit in a block one by one and commonly connects the driving circuit to all blocks.

Although the organic EL elements and the driving circuits inFIG. 6are aligned in a line pattern and provided in parallel to a control line, a power line and first and second voltage lines, circuit connection is equivalent to a matrix arrangement of N rows and M columns illustrated inFIG. 3. Driving circuits in a block correspond to driving circuits in each row in a matrix display apparatus, and are simultaneously selected and writing is performed simultaneously therein. Driving circuits which belong to different blocks and share the first voltage line correspond to driving circuits in each column in the matrix display apparatus. A reference numeral such as (1, 1) assigned to the driving circuit100inFIG. 6indicates a block number and a position in a block, and corresponds to a row and a column of a display apparatus according to the first embodiment.

Although M and N take any numbers as long as M and N are integers equal to or more than two, when M is increased, a block needs to be scanned at a high speed and, when N is increased, the number of first voltage lines increases and an occupied area increases. M and N preferably take about the same values.

Unlike the first embodiment, the second control line and the third control line are shared as a single control line (referred to as a “third control line73”). Further, the third voltage line63and fourth control lines74are provided.

The control lines71,73and74are on the opposite side of the power line60across the driving circuits100, and supply control signals P1(n), P3(n) and P4(n) (n is a block number and n=1, 2, . . . , and N is true) per block. On an outer side of the control lines, a scanning circuit SCN which generates these control signals is provided. The scanning circuit SCN receives an input of a block signal CK, an inverted signal CKB and a scan start signal ST from an outside.

The control signals P1, P3and P4sequentially select blocks from the first block to the N-th block, and write the signal voltage Vdata in the driving circuits100of the selected blocks from the first voltage line61.

Although the signal voltage Vdata of the second voltage line62is inputted from an outside in the present embodiment, a signal voltage generating circuit corresponding to PS3according to the first embodiment may be made using an integrated circuit and implemented on the substrate1according to a COG method.

FIG. 7is a circuit diagram of the driving circuit100. The same portions as those inFIG. 4will be assigned the same reference numeral.

In addition to the driving circuit inFIG. 4, the driving circuit100according to the present embodiment has the transistor M3, the third voltage line63and the fourth control line74, and shares the second control line72and the third control line73as one common control line73. The transistor M5which is the second switch has a gate connected to the third control line73, and is turned on upon P3=L.

The source of the N channel type MOS transistor M3is connected to the gate of the driving transistor M1, and the drain is connected to the third voltage line63. The gate is connected to the fourth control line74, and is turned on when a control signal P4=L is true. The transistor M3is controlled as the fifth switch to close and open independently from the first to fourth switches.

In the present embodiment, the voltage of the first voltage line61is the signal voltage Vdata, and the voltage of the second voltage line62is the fixed voltage Vref. Further, a voltage Vini for initialization is applied to the third voltage line63.

FIG. 8is a timing chart illustrating operation of a driving circuit inFIG. 7.

At a time t0−t1which is an initialization period, control signals of the first block become P1(1)=L, P3(1)=H and P4(1)=H.

P1=L holds, so that the transistor M4which is the first switch SW1becomes off. P3=H holds, so that the transistor M5which is the second switch SW2is turned off, the transistor M5of the third switch SW on the terminal side is turned on and the transistor M2of the fourth switch SW4on the third terminal side is turned on. P4=H holds, so that the transistor M3which is the fifth switch SW5also is turned on.

In this case, supply of a current to organic EL elements EL is stopped, the source of the driving transistor M1is connected to the first voltage line61and one end of the holding capacitor C1is connected to the second voltage line62. V1=Vdata is set to the source S of the driving transistor M1, and Vini is set to the gate G. The voltage between the gate and the source is Vdata−Vini (with a gate side as a negative side). By setting Vdata to a sufficiently low voltage based on Vini, it is possible to place the driving transistor M1in a deep on state.

Unlike the first embodiment, a current does not flow to organic EL elements during an initialization period. An organic EL element the luminance of which is zero is continuously in an extinction state at all times, and therefore contrast of brightness is high.

The time t1−t2is a writing period, and P1(1)=H, P3(1)=H and P4(1)=L hold.

The transistor M4which is the first switch SW1is turned on, the transistor M6which is the second switch SW2is turned off and the transistor M3which is fifth switch SW5is turned off. The same operation as that of the circuit inFIG. 4according to the first embodiment produces a voltage Vref−Vdata+Vth (with the terminal side connected to the gate of the driving transistor M1as a negative side) in the capacitor C1.

In a light emission period of the time t2−t7, P1(1)=L, P3(1)=L and P4(1)=L hold. The transistor M4which is the first switch SW1is turned off, and Vref—Vdata+Vth produced in the writing period is held at both ends of the capacitor C1. Consequently, the signal voltage Vdata is set to a voltage range lower than Vref, and, when a driving transistor is operated in a saturated region, Vref−Vdata is determined, so that it is possible to flow a current to an organic EL element irrespectively of a power voltage and a threshold voltage.

During a light emission period of the first block at the time T2−t7, the second block is initialized during the period of t2−t3, a signal voltage is written during a period of t3−t4and light is emitted after t4. Subsequently, initialization, writing and light emission are sequentially performed up to the N-th block per block.

FIG. 9is the third example and is an example of an exposure apparatus of the same electrophotographic printer as that in the second embodiment. Differences from the second embodiment are that a first voltage line61and a second voltage line62are switched, and the fixed voltage Vref is supplied to the first voltage61and the signal voltage Vdata which determines luminance is applied to the second voltage line62The driving circuit is the same as that inFIG. 7, and timings of control signals P1, P3and P4are the same as those inFIG. 8. Meanwhile, unlikeFIG. 8, the signal voltage Vdata is set to a voltage range higher than the fixed voltage Vref.

FIGS. 10A and 10Bare plan views of an exposure apparatus according to the present embodiment. The exposure apparatus has a plurality of light emitting regions400formed by organic EL elements.FIG. 10Ais an example where the light emitting areas are provided in a zig-zag pattern, andFIG. 10Bis provided in a linear arrangement. When code data Dc is inputted from an external device such as a personal computer to a print controller410inFIGS. 10A and 10B, the code data Dc is converted into image data (dot data) Di. This image data Di is inputted to the exposure apparatus, and each light emitting region400is controlled based on the image data Di.

FIG. 11is a cross-sectional view of an electrophotographic printer which has an exposure apparatus according to the present embodiment. An image forming apparatus represented by an electrophotographic printer has an exposure apparatus and a photosensitive body on a surface of which a latent image is formed by the exposure apparatus. The exposure apparatus adopts a method of scanning a laser beam and fixed exposure method where light emitting elements arranged in an array pattern as in the present embodiment.

An image forming apparatus may selectively execute a color mode of forming a color image by overlaying four color toners of yellow (Y), magenta (M), cyan (C) and black (K), and a monochrome mode of forming a monochrome image using only black (K) toner.

An exposure unit70Y has an exposure apparatus according to the present embodiment, and a lens which collects light emitted from the exposure apparatus and irradiates a surface of a photosensitive drum85Y with exposure light. Further, the exposure unit70Y may have an optical absorption member which prevents a position other than a predetermined position of the surface of the photosensitive drum85Y from being irradiated with light.

In a housing80of the image forming apparatus, in addition to exposure units70Y,70M,70C and70K, a transfer belt81, a feeding unit82, a fusing roller83and a pressure roller84are arranged. Further, in the housing80, photosensitive drums85Y,85M,85C and85K, charging rollers86Y,86M,86C and86K, developer87Y,87M,87C and87K and transfer rollers88Y,88M,88C and88K are arranged. The feeding unit82is formed detachably.

Image forming operation is as follows. In addition, although a case will be described a yellow (Y) image is formed as a latent image, a sheet is conveyed by the transfer belt81, and magenta (M), cyan (C) and black (K) images are sequentially formed in the same way as the way the yellow (Y) image is formed.

First, based on a signal from a print controller, the photosensitive drum85Y which is an electrostatic latent image carrier is rotated clockwise by a motor (not illustrated). Further, following this rotation, a photosensitive surface of the photosensitive drum85Y rotates in response to exposure light. Above the photosensitive drum85Y, the charging roller86Y which charges the surface of the photosensitive drum85Y with a predetermined pattern is provided to abut the surface. Further, the surface of the photosensitive drum85Y uniformly charged by the charging roller86Y is irradiated with exposure light by the exposure unit70Y.

An irradiation position, an irradiation timing, an irradiation time and an irradiation intensity of exposure light emitted from the exposure unit70Y are adjusted based on the image data Di, and an electrostatic image is formed on the surface of the photosensitive drum85Y by exposure light. This electrostatic latent image is developed as a toner image by the developer87Y disposed to abut on the photosensitive drum85Y on a side closer to a downstream of a rotation direction of the photosensitive drum85Y than the irradiation position of exposure light.

The toner image developed by the developer87Y is transferred onto a sheet which is a material to be transferred, by the transfer roller88Y disposed to oppose to the photosensitive drum85Y below the photosensitive drum85Y. Although a sheet is accommodated in a sheet cassette in the feeding unit82, sheets may be fed by a manual tray. At an end of the sheet cassette, feeding rollers are disposed and convey sheets in the sheet cassette to a conveying path.

As described above, a sheet to which a toner image is transferred is conveyed to a fuser by the transfer belt81. The fuser includes a fusing roller83which has a fusing heater (not illustrated) inside and the pressuring roller84which is disposed to pressure against this fusing roller83. A conveyed sheet is pressured and heated by the fusing roller83and the pressuring roller84, so that a toner image is fused on a sheet.

This application claims the benefit of Japanese Patent Application No. 2012-206884, filed 2012Sep. 20, which is hereby incorporated by reference herein in its entirety.