Interconnection resources for programmable logic integrated circuit devices

A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.

BACKGROUND OF THE INVENTION

This invention relates to programmable logic array integrated circuit devices (“programmable logic devices” or “PLDs”), and more particularly to interconnection resources for use on programmable logic devices that increase the speed at which those devices can be made to operate.

Programmable logic devices typically include (1) many regions of programmable logic, and (2) programmable interconnection resources for selectively conveying signals to, from, and/or between those logic regions. Each logic region is programmable to perform any of several different, relatively simple logic functions. The interconnection resources are programmable to allow the logic regions to work together to perform much more complex logic functions than can be performed by any individual logic region. Examples of known PLDs are shown in Wahlstrom U.S. Pat. No. 3,473,160, Freeman U.S. Pat. No. Re. 34,363, Cliff et al. U.S. Pat. No. 5,689,195, Cliff et al. U.S. Pat. No. 5,909,126, and Jefferson et al. U.S. Pat. No. 5,215,326, all which are hereby incorporated by reference herein.

A frequent objective in the design of PLDs is to increase the speed at which the device can be operated. The speeds at which signals can travel through the interconnection resources between logic regions is particularly important to determining device speed. Overall, the interconnection resources must have the general-purpose capability of connecting any logic region to any other logic region. But in addition to this, it can be helpful to find ways to make faster interconnections between nearby logic regions. Many complex logic tasks can be broken down into parts, each of which can be performed by a respective cluster of logic regions. By providing interconnection resources that facilitate the flexible formation of clusters of logic regions with high-speed interconnection capabilities among the logic regions in such clusters, the ability of the PLD to perform various complex logic tasks at high speed in enhanced.

In view of the foregoing, it is an object of this invention to provide improved interconnection resources for programmable logic devices.

It is a more particular object of this invention to provide interconnection resources for programmable logic devices that facilitate the formation of extended clusters of nearby logic modules between which high-speed interconnections can be made.

SUMMARY OF THE INVENTION

These and other objects of the invention are accomplished in accordance with the principles of the invention by providing programmable logic devices with interconnection resources that facilitate the provision of interconnections between logic modules in adjacent rows of logic regions, as well as between nearby logic regions in each row. Typically the logic regions on a PLD are arranged in a two-dimensional array of intersecting rows and columns of such regions. Each logic region may include a plurality of subregions. Local feedback conductors may be provided for facilitating communication among the subregions in a region. In addition, these local feedback conductors may be interleaved between horizontally adjacent regions in a row, thereby facilitating high speed interconnection among the subregions of horizontally adjacent regions. In accordance with this invention such high speed local interconnection is additionally provided between adjacent rows in any of several ways. For example, output signals of subregions in each row may be additionally applied substantially directly (i.e., without making use of the more general-purpose interconnection resources of the device) to programmable logic connectors (e.g., multiplexers) feeding output drivers that are otherwise normally or nominally associated with subregions in an adjacent row. This makes it possible for the subregions in one row to optionally drive interconnection resources that are normally associated with an adjacent row, thereby facilitating clustering of logic regions in adjacent rows. As an alternative or addition to the foregoing, the interconnection resources that bring signals into the regions in each row can be partly shifted or extended relative to the rows so that some signals can be more readily and directly brought into each row from the adjacent rows, again without having to make use of the more general-purpose interconnection resources of the device. This again facilitates forming clusters of logic regions in adjacent rows. As still another alternative, the interconnection resources that bring signals into each row can be substantially directly driven by signals from similar resources in another row, thereby again facilitating the formation of clusters of logic regions in adjacent rows without needing to use the general-purpose interconnection resources.

As an alternative or addition to the foregoing, clustering of logic regions along a row may be facilitated by providing conductors associated with each logic region that extend adjacent a relatively small subplurality of the other adjacent logic regions in that row. For example, one of these conductors associated with each logic region may extend to the left from that logic region adjacent a relatively small number of other logic regions to the left of the associated logic region, and another of these conductors may extend to the right by approximately the same number of other logic regions. The same signal or different signals from the associated logic region can be applied to each of these conductors, and thereby to the other logic regions that these conductors are adjacent to. (The signals on these conductors can alternatively come from other sources.) The relatively short length, light loading, and other similar characteristics of these conductors make them especially suitable for use in providing high-speed interconnections from the associated logic region (or other signal source(s)) to the other logic regions that they are adjacent to, thereby again facilitating flexible clustering of nearby logic regions.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Although the principles of this invention are equally applicable to many different programmable logic device architectures, the invention will be fully understood from the following explanation of its application to programmable logic devices of the type shown in commonly assigned U.S. Pat. No. 6,407,576, which is hereby incorporated by reference herein in its entirety. Because the last-mentioned reference is incorporated by reference herein, it will not be necessary to actually repeat the content of that reference here. Where elements described in that reference are mentioned again here, the same reference numbers will be used here to the greatest extent possible, even though such elements may be here diagrammed more simply or described more briefly.

FIG. 1(similar toFIG. 2in the last-mentioned reference) shows the presently relevant portion of an illustrative programmable logic device10constructed in accordance with this invention. Device10includes several rows of regions20of programmable logic, each of which includes a plurality of subregions30of programmable logic. To avoid over-crowding the drawing, individual subregions30are delineated only in the extreme upper left-hand region20in FIG.1. The rows of logic regions20are interspersed with rows of input/output (“I/O”) circuitry40. At the extreme top and bottom of the circuitry shown inFIG. 1are rows of memory regions50, which the user of device10can use as PAM, ROM, product-term logic, content addressable memory, etc. Regions60include phase-locked loop circuitry, region70includes control logic and pins, region80includes JTAG logic and pins, and region120is part of a secondary signal distribution network. The details of regions40,60,70,80, and120are of little interest in connection with this invention and therefore need not be significantly described herein.

Associated with each row of logic regions20is a plurality of global horizontal interconnection conductors230a/b. (The “a/b” designation is from the last-mentioned reference and refers to “a” conductors having “normal” signal propagation speed characteristics and “b” conductors having higher signal propagation speed characteristics. This feature is at most only tangential to the present invention and therefore need not be further detailed herein.) Also associated with the left and right half of each row of logic regions20is a plurality of so-called direct horizontal interconnection conductors240. Still further associated with subsets of horizontally adjacent regions20in each row are groups of so-called horizontal network of fast line (“HNFL”) interconnection conductors250.

Associated with each column of logic regions20(and extending across I/O regions40and into memory regions50) is a plurality of global vertical interconnection conductors200a/b. (Again, the “a/b” designation is from the last-mentioned reference and refers to some conductors200ahaving normal speed and other conductors200bhaving higher speed.) Associated with the upper and lower half of each column of logic regions20(and the associated I/O and memory circuitry40and50) is a plurality of so-called half vertical interconnection conductors210a/b. (Once again, the “a/b” designation refers to different conductors having different signal propagation speed characteristics.) Associated with vertically adjacent pairs of regions20and50are pluralities of so-called interleaved vertical (“IV”) interconnection conductors220. These conductors220form at least part of a first illustrative embodiment of this invention.

It will be understood thatFIG. 1shows only a few representative ones of each of the various types of interconnection conductors mentioned above.

FIG. 2shows selected circuitry associated with two, representative, horizontally adjacent logic regions20in a typical row of such regions. The circuitry shown inFIG. 2includes selected circuitry for supplying signals to the subregions30in the depicted regions20, and selected circuitry for conveying signals from those subregions. Note that between the depicted regions are a plurality of region-feeding conductors300and a plurality of local feedback conductors310. Signals on the conductors230a/b,240,250, and260associated with the row that includes depicted regions20can be applied to region-feeding conductors300via programmable logic connector (“PLC”) and driver circuitry270/276. Circuitry270/276may be constructed as shown inFIG. 3of the last-mentioned reference (see alsoFIG. 7herein). Local feedback conductors310are supplied with the so-called LOCAL output signals of selected ones of the depicted subregions30. In particular, half of the subregions30in each depicted region20supply their LOCAL output signals to the local feedback conductors310between those regions. (The LOCAL output signals of the other subregions go to local feedback conductors to the left or right of the representative circuitry shown inFIG. 2.) Signals on depicted conductors300/310can be applied to subregion input terminals A-D via PLC circuitry322/328. Circuitry322/328may be constructed as shown inFIG. 4of the last-mentioned reference. Two of the four main data input signals A-D of each of the depicted subregions come from the conductors300/310and circuitry322/328to the right of that subregion, and the other two of those inputs come from the elements300/310/322/328to the left of that subregion. In particular, the B and D inputs to each subregion30come from the right, and the A and C inputs to each subregion30come from the left.

Each subregion30may be constructed as shown inFIGS. 5A and 5Bof the last-mentioned reference. Thus each subregion30may include (among other components) a four-input look-up table or other combinatorial logic circuitry for producing an intermediate signal which is any logical combination of the four main data inputs A-D to the subregion. Each subregion30may further include a register for registering the intermediate signal, and PLC circuitry for outputting either the intermediate signal or the register output signal as any of a LOCAL output signal310, an interleaved vertical (“IV”) output signal220, and/or two more global output signals (not shown inFIG. 2, but shown as OUT0and OUT1in FIG.3. In particular, any of the above-mentioned four outputs of a subregion30can be separately selected to be either the intermediate signal or the register output signal of that subregion.

FIG. 2also shows that the IV outputs220of half the subregions30on the left and half the subregions30on the right extend upwardly (to the row of regions20above the row shown in part in FIG.2), and that the IV outputs220of the other half of the subregions on the left and right extend downwardly (to the row of regions20below the row shown in part in FIG.2). The particular pattern for the IV outputs to go up and down can be different from that shown inFIG. 2if desired. For example, whereasFIG. 2shows that the IV outputs of the upper half of the subregions30go up, and the IV outputs of the lower half of the subregions go down, a different pattern is suggested inFIG. 3, which shows the IV outputs220of vertically alternating subregions30going up and down. The same is true for the left-right patterns of LOCAL outputs shown in FIG.2. That is, a different pattern of LOCAL outputs can be used instead of the pattern shown inFIG. 2in which the upper half of the subregions30in each region20have their LOCAL outputs going to the right and the lower half have their outputs going to the left. An example of a different pattern would be to have vertically alternating subregions going to the left and right in terms of LOCAL output.

FIG. 3shows circuitry500associated with four representative subregions30(two subregions in each of two horizontally adjacent regions20), principally for applying the output signals of those subregions to adjacent horizontal and vertical conductors and for making interconnections between adjacent horizontal and vertical conductors (e.g., so that signals can turn from horizontal to vertical conductors or vice versa).FIG. 3is similar toFIG. 6in the last-mentioned reference. Much of what is shown inFIG. 3is not especially important to the present invention. Those unimportant or relatively unimportant portions ofFIG. 3will therefore not be described in full detail herein, it being appreciated that the last-mentioned reference provides a full discussion (in connection withFIG. 6of the last-mentioned reference) of all portions of this FIG. that are not described here. In addition, operation of portions ofFIG. 3that are not specifically described here can generally be inferred from the portions that are described.

The portions ofFIG. 3that are germane to the present invention are those that are associated with the two conductors220shown in that FIG. Initially it should be said that one of the conductors220shown inFIG. 3comes from the IV output of a subregion30in the row above the row shown in part in that FIG., and the other of those two conductors220comes from the IV output of a subregion30in the row below the row shown in part in FIG.3. (Although the representative circuitry shown inFIG. 3includes four subregions30, producing four IV output signals220, theFIG. 3circuitry only receives two IV input signals220. This does not mean, however, that there is a net excess of IV outputs. The explanation for this is that there is additional similar driver circuitry500to the left/right of what is shown inFIG. 3which utilizes the IV outputs that would appear to be excess if only a vertical slice like what is shown inFIG. 3is considered.)

Both of the IV input signals220to the circuitry shown inFIG. 3are among the inputs to PLC522. One of the IV input signals220to the circuitry shown inFIG. 3is among the inputs to three out of six PLCs502,506,530,540,560, and564. The other IV input signal220toFIG. 3is among the inputs to the other three out of the six just-mentioned PLCs.

Other inputs to PLC522are (1) the signal from an adjacent global vertical conductor200b, (2) the signal from an adjacent half vertical conductor210b, (3) one of the global output signals (“OUT1”) of the upper left-hand subregion30, (4) one of the global output signals (“OUT0)” of the lower right-hand subregion30, (5) one of the global output signals (“OUT1”) of the lower left-hand subregion30, (6) one of the global output signals (“OUT0”) of the upper right-hand subregion30, and (7) the signal from a selected one of four adjacent global vertical conductors200a. (PLC520makes the one-of-four selection referred to at the end of the preceding sentence.)

PLC522is programmable (e.g., by programmable function control elements (“FCEs”) that are not shown inFIG. 3, but that are like FCE526shown inFIG. 3for controlling tri-state driver524) to select any one of its input signals as its output signal. The output signal of PLC522is applied to tri-state driver524. If tri-state driver524is enabled by the associated FCE526, driver524amplifies the signal it receives and applies the resulting amplified signal to one of the adjacent fast or high-speed global horizontal conductors230b. (If tri-state driver524is not thus enabled by the associated FCE526, the driver is off and looks like a high impedance to the associated conductor230b.)

From the foregoing it will be seen that application to PLC522of IV output signals from the row above and the row below allows PLC522and its associated tri-state driver524to be used to apply one of those IV signals from an adjacent row to a global horizontal conductor230bassociated with the row partly shown in FIG.3. In that way a subregion30in the row above or below the partly depicted row can effectively “steal” elements522and524from the partly depicted row and thereby become (for at least the purposes served by elements522and524) like a subregion in the depicted row. Elements220,522, and524therefore allow a subregion30in an adjacent row to provide very direct drive to one of the conductors230bin the partly depicted row. Although other elements in the partly depicted row could be driven by this type of IV signal routing, in the particularly preferred embodiment shown this IV routing is very high-speed by virtue of being through relatively large and strong tri-state driver524to a high-speed conductor230b. From conductor230ba signal can get to any of the regions20in the row served by that conductor.

Other possible routings of the IV signals220provided by theFIG. 3circuitry will now be discussed.

As has been mentioned, one of the two IV signals received by theFIG. 3circuitry from the two adjacent rows is applied to one input terminal of PLC530. PLC530can select this IV signal input in lieu of any of its other inputs for application to buffer532. The output signal of buffer532is applied to PLC534(e.g., a demultiplexer). PLC534is programmable to apply its input signal to any one or more of two of the adjacent normal-speed global horizontal conductors230aand one of the adjacent normal-speed half vertical conductors210a.

The PLC540routing of one of the received IV signals220is similar to that just described for PLC530, except that in the case of routing via elements540,542, and544, one of the possible destinations is one of the adjacent normal-speed global vertical conductors200a.

The PLC502routing of one of the received IV signals220allows that IV signal to be applied to inverting buffer504in lieu of the other inputs to PLC502. The output signal of buffer504is applied to one of the adjacent HNFL conductors250that extends to the left adjacent several other logic regions20from the circuitry shown in FIG.3. The same IV signal220is also applied to one input terminal of PLC560. PLC560can select that signal for application to inverting buffer562and thereby to another adjacent HNFL conductor250that extends to the right adjacent several other logic regions20from the circuitry shown in FIG.3. Thus the IV signal being discussed can be applied to a leftward extending HNFL conductor250, a rightward extending HNFL conductor250, or to both of those conductors. As is described in more detail below in connection withFIG. 6, HNFL conductors250provide relatively high-speed communication—from the associated source logic region(s)20to any of the logic regions20that they pass adjacent to—because of the relatively short length, light loading, etc., of the HNFL conductors.

The PLC506and PLC564IV signal routing is similar to that described for PLCs502and560, except that the other of the two IV signals220received by theFIG. 3circuitry is applied to PLCs506and564, and different HNFL conductors250are driven by inverting buffers508and566.

From the foregoing, it will be seen that the IV connections220between adjacent rows of logic regions20facilitate flexible formation of clusters of logic regions or subregions, as well as relatively high-speed communication within such clusters. For example, using an IV connection220and routing via elements like522and524, a subregion30in one row can be clustered with (i.e., relatively directly coupled to) any of the subregions in one of the adjacent rows. The same is true (albeit using somewhat slower, normal-speed global horizontal conductors230a) via elements530/532/534or540/542/544. As another example, using an IV connection220and routing via elements like502,506,560, and/or564, a subregion30in one row can be clustered with any of the logic regions20in an adjacent row served by the associated HNFL conductors250in the adjacent row. In addition to providing more direct, and therefore higher speed interconnections between adjacent rows, the provision of IV conductors220reduces the need to use longer-haul and more general-purpose vertical conductors200and210for inter-row connections. This helps to reduce the numbers of conductors200and210that must be provided on the device.

It should be noted that the clustering options afforded by the above-described IV circuitry are preferably boundary-less within the array of logic regions20. By this it is meant that any logic region20can serve as a member of a cluster, and the cluster can extend from that logic region in substantially the same way regardless of the logic region that is chosen as the cluster member being considered. Only the physical edges of the logic region array bound the possible clusters.

An alternative embodiment of the invention which facilitates flexible clustering of subregions30in one row with logic regions20(and their subregions30) in another adjacent row is shown in FIG.4. Although for clarityFIGS. 2 and 3show the horizontal interconnection conductors230/240/250/260associated with a typical row laterally displaced from the other circuitry of that row,FIG. 1is somewhat less schematic more physically accurate in that it shows the horizontal conductors and other circuitry of each row super-imposed on or interspersed with one another.FIG. 4shows the horizontal conductors230/240/250/260in the same super-imposed or interspersed way.

InFIG. 4the horizontal conductors230/240/250/260associated with each row are shown subdivided into three laterally spaced subsets, each of which preferably includes some of each type of conductor (especially some of each of conductors230,240, and250).FIG. 4further shows the PLCs270/276nominally associated with each row and each group of logic region feeding conductors300shifted vertically relative to the associated row so that some of the inputs to those PLCs come from the horizontal conductors230/240etc. associated with one of the rows that is adjacent to the row with which the PLCs270/276are nominally associated. Considering, for example, the left-most logic region20shown in row N inFIG. 4, the PLCs270/276that feed the conductors300to the left of that logic region receive their inputs from the lower two subsets of the horizontal conductors230/240etc. associated with row N and from the upper-most subset of the horizontal conductors230/240etc. associated with the row below row N (i.e., row N+1). This arrangement makes it possible to feed signals from row N+1 to any of the subregions30in the exemplary region20being discussed very directly and without having to make use of the vertical interconnection resources (e.g., elements200/210) of the device.

Similarly, the PLCs270/276that feed the conductors300to the right of the left-most logic region20shown in row N inFIG. 4receive their inputs from the upper two subsets of the horizontal conductors230/240etc. associated with row N and from the lower-most subset of the horizontal conductors230/240etc. associated with the row above row N (i.e., row N−1). This makes it possible to feed signals from row N−1 to any of the subregions30in the logic region20being discussed very directly and without having to use the other vertical interconnection resources (e.g., elements200/210) of the device.

It should be noted that because each PLC group270/276is interleaved between two logic regions20(one region to the left and one region to the right) as is described more fully above in connection withFIG. 2, the inputs to each group270/276from the adjacent row are available to both regions20served by that group270/276and its associated conductors300.

A possible alternative to shifting the groups of PLCs270/276as shown inFIG. 4is shown in FIG.5. In theFIG. 5alternative at least some of the region-feeding conductors300interleaved between each horizontally adjacent pair of logic regions20in each row extend into the row above or below that row for programmably selectable connection to the horizontal conductors230/240/250/260associated with that other row. Considering, for example, the conductors300athat serve any two adjacent logic regions20in the upper row (“row N”) inFIG. 5, those conductors300acan receive signals (via PLCs270/276) from both the conductors230/240/250/260associated with row N and the conductors230/240/250/260associated with the row below row N (i.e., “row N+1”). Similarly, the conductors300bthat serve any two adjacent logic regions20in row N+1 inFIG. 5can receive signals (via PLCs270/276) from both the conductors230/240/250/260associated with row N+1 and the conductors230/240/250/260associated with row N. The interconnection arrangement described above for rows N and N+1 can be continued to other adjacent rows (e.g., as shown by the dotted line conductors300cand the dotted extensions of conductors300aextending from row N to row N−1 (not shown), and as shown by the dotted line conductors300dand the dotted extensions of conductors300bextending from row N+1 to row N+2 (not shown).

Like the arrangements shown in earlier FIGS., arrangements of the type shown inFIG. 5facilitate direct clustering of a logic region20in one row with logic regions in an adjacent row without the need to use other vertical interconnection resources such as elements200and210to provide inter-row communication. Also, like the arrangements shown in earlier FIGS., the clustering options afforded byFIG. 5are high-speed and flexible (e.g., they can be essentially boundary-less within the array of logic regions20).

The HNFL conductors250that have already been occasionally mentioned also facilitate flexible clustering of logic regions20without recourse to the general interconnection conductor resource network in accordance with this invention. Accordingly the HNFL conductors will now be considered in more detail in connection withFIGS. 6 and 7.

FIG. 6shows that typical HNFL conductors250originate at a driver block500(FIG. 3) associated with a horizontally adjacent pair of logic regions20and extend, respectively, to the left and right of the source logic regions by a relatively small (but preferably plural) number of other logic regions. For example, each HNFL conductor250may extend four or five logic regions20to the left or right of the source logic regions. The possible sources of the signals on HNFL conductors250have been described above in connection with FIG.3. PLC groups270/276(shown in more detail in FIG.7and described in more detail below in connection with that FIG.), associated with the region-feeding conductors300between at least some of the horizontally adjacent logic regions20that the HNFL conductors250pass, can apply the HNFL conductor signals to those region-feeding conductors for application to the logic regions on either side of those conductors300.FIG. 6shows the PLC groups270/276associated with only every other region-feeding conductor group300being able to make such connections from the HNFL conductors250. This helps reduce the loading on the HNFL conductors, thereby helping to increase the operating speed of those conductors. As an alternative, however, all PLC groups270/276may have the capability of making connections from the HNFL conductors.

As has been mentioned,FIG. 7shows a representative PLC group270/276in more detail.FIG. 7is similar toFIG. 3in the last-mentioned reference. Accordingly, only the portion ofFIG. 7that is particularly pertinent to the present invention will be described in full detail herein.FIG. 7shows that one or more of the HNFL conductors served by a PLC276can be applied to input terminals of that PLC. PLC276is programmable (by FCEs that are not shown but that can be similar to FCEs272) to apply any one of its inputs to inverting buffer278and thereby to a region-feeding conductor300. To increase the speed with which an HNFL conductor signal can reach region-feeding conductor300, the HNFL conductor(s) are connected substantially directly to relatively small, downstream PLC276, thereby effectively bypassing upstream PLCs270(which can select signals from other conductors230,240, and260associated with the row that includes PLCs270/276).

To briefly recapitulate the foregoing discussion of HNFL conductors250, these conductors facilitate flexible high-speed clustering of nearby logic regions due to such characteristics as the following: (1) there is only a single source for the signal on each HNFL conductor (i.e., the driver block500associated with the pair of logic regions20near the midpoint of a left- and right-extending pair of HNFL conductors250), (2) the HNFL conductors are relatively short, (3) the HNFL conductor signals are applied to region-feeding conductors300via downstream PLCs276that bypass other upstream PLCs270, and (4) the PLC groups270/276connect the HNFL conductors to only certain groups of region-feeding conductors300that the HNFL conductors pass.

From FIG.3and the earlier discussion of that FIG. it will be appreciated that each leftwardly extending HNFL conductor250is effectively paired with a rightwardly extending conductor250. Both conductors in each such pair can be driven by the same signal, or different signals can be applied to each conductor in any pair. The sources of the HNFL signals are subregion30output signals, interleaved conductor220signals, and fast vertical interconnection conductor210bsignals.

FIG. 8shows an illustrative embodiment of another type of conductor arrangement that facilitates flexible, close, and direct (i.e., high-speed) association of nearby logic regions20without having to make use of the more general interconnection resources of the device. In this embodiment at least some of the region-feeding conductors300interleaved between each horizontally adjacent pair of logic regions20in the center row have relatively direct programmable connections276ato at least some of the region-feeding conductors300interleaved between the logic regions above and below the first-mentioned logic regions. Similarly, at least some of the local feedback conductors310interleaved between each horizontally adjacent pair of logic regions20in the center row have relatively direct programmable connections276bto at least some of the region-feeding conductors300interleaved between the logic regions above and below the first-mentioned logic regions. Programmable connections276aand276bmay be additional inputs to downstream (and therefore relatively fast) PLCs276in FIG.7. Alternatively, connections276aand276bmay be programmably controlled (e.g., by FCEs) pass gates or transistors between the conductors300/310associated with those connections276a/276b. Such pass gates or transistors are also sometimes referred to herein as PLCs.

Connections276aallow a signal applied to a region-feeding conductor300associated with the center row (e.g., from any of the conductors230/240/250/260associated with the center row) to be applied not only to the center row logic regions20to the left and/or right of that conductor300, but also to the adjacent logic regions20above and/or below those logic regions (i.e., in the adjacent rows above and below the center row). Similarly, connections276ballow a signal applied to a local feedback conductor310associated with the center row (i.e., from the associated subregion30in a region to the left or right of that conductor310) to be applied not only to the center row logic regions to the left and/or right of that conductor310, but also to the adjacent logic regions20above and/or below those logic regions (i.e., in the adjacent rows above and below the center row). Connections276aand276btherefore facilitate rapid and close association of logic regions that are generally vertically adjacent to one another. For example, connections276afacilitate application of the same signals (from the conductors230/240/250/260associated with the center row) to vertically adjacent logic regions20. Connections276bfacilitate application of signals from center row logic regions20to other vertically adjacent logic regions20.

Although both types of connections276aand276bare shown inFIG. 8, it will be understood that only one of these two types of connections may be provided, with the other type being omitted. Similarly, the numbers and patterns of conductors300/310that have connections276aand/or276bmay be varied as desired. WhereasFIG. 8only shows signals flowing from center row conductors300/310to vertically adjacent row conductors300, it will be understood that similar connections can be provided for allowing signal flow in the opposite direction or in other patterns or ways between vertically adjacent rows.

FIG. 9illustrates a programmable logic device10of this invention in a data processing system1002. Data processing system1002may include one or more of the following components: a processor1004; memory1006; I/O circuitry1008; and peripheral devices1010. These components are coupled together by a system bus1020and are populated on a circuit board1030which is contained in an end-user system1040.

System1002can be used in a wide variety of applications, such as computer networking, data networking, instrumentation, video processing, digital signal processing, or any other application where the advantage of using programmable or reprogrammable logic is desirable. Programmable logic device10can be used to perform a variety of different logic functions. For example, programmable logic device10can be configured as a processor or controller that works in cooperation with processor1004. Programmable logic device10may also be used as an arbiter for arbitrating access to a shared resource in system1002. In yet another example, programmable logic device10can be configured as an interface between processor1004and one of the other components in system1002. It should be noted that system1002is only exemplary, and that the true scope and spirit of the invention should be indicated by the following claims.

Various technologies can be used to implement programmable logic devices10having the features of this invention, as well as the various components of those devices (e.g., the above-described PLCs and the FCEs that control the PLCs). For example, each PLC can be a relatively simple programmable connector such as a switch or a plurality of switches for connecting any one of several inputs to an output. Alternatively, each PLC can be a somewhat more complex element which is capable of performing logic (e.g., by logically combining several of its inputs) as well as making a connection. In the latter case, for example, each PLC can be product term logic, implementing functions such as AND, NAND, OR, or NOR. Examples of components suitable for implementing PLCs are EPROMs, EEPROMs, pass transistors, transmission gates, antifuses, laser fuses, metal optional links, etc. As has been mentioned, the various components of PLCs can be controlled by various, programmable, function control elements (“FCEs”). (With certain PLC implementations (e.g., fuses and metal optional links) separate FCE devices are not required.) FCEs can also be implemented in any of several different ways. For example, FCEs can be SRAMs, DRAMs, first-in first-out (“FIFO”) memories, EPROMs, EEPROMs, function control registers (e.g., as in Wahlstrom U.S. Pat. No. 3,473,160), ferro-electric memories, fuses, antifuses, or the like. From the various examples mentioned above it will be seen that this invention is applicable to both one-time-only programmable and reprogrammable devices.

It will be understood that the forgoing is only illustrative of the principles of the invention, and that various modifications can be made by those skilled in the art without departing from the scope and spirit of the invention. For example, the numbers of the various types of resources on device10can be different from the numbers present in the depicted and described illustrative embodiments. This applies to such parameters as the numbers of rows and columns of the various types of circuitry, the number of subregions30in each region20, the numbers of the various types of interconnection conductors, the numbers and sizes of the PLCs provided for making interconnections between various types of interconnection conductors, etc. It will also be understood that various directional and orientational terms such as “vertical” and “horizontal,” “left” and “right,” “above” and “below,” “row” and “column,” and the like are used herein only for convenience, and that no fixed or absolute directional or orientational limitations are intended by the use of these words. For example, the devices of this invention can have any desired orientation. If reoriented, different directional or orientational terms may need to be used in their description, but that will not alter their fundamental nature as within the scope and spirit of this invention. Terms like “region” and “subregion” are also used only as generic, relative terms, and other terms may be used for generally similar circuitry. Indeed, these terms may be used interchangeably herein in contexts in which a region/subregion hierarchy is not important. Alternatively, devices within the scope of this invention may have regions of programmable logic that are not divided into subregions. Although look-up table logic is employed in the illustrative embodiments shown and described herein, it will be understood that other types of logic may be used instead if desired. For example, sum-of-products logic, such as is the primary example considered in references like Pederson et al. U.S. Pat. No. 5,241,224 and Patel et al. U.S. Pat. No. 5,371,422 (both of which are hereby incorporated by reference herein in their entireties), may be used instead of look-up table logic.