Via structure and methods for forming the same

Vias and methods of making the same. The vias including a middle portion located in a via opening in an interconnect-level dielectric layer, a top portion including a top head that extends above the via opening and extends laterally beyond upper edges of the via opening and a bottom portion including a bottom head that extends below the via opening and extends laterally beyond lower edges of the via opening. The via may be formed from a refractory material.

BACKGROUND

Copper is a popular material to use to form interconnect structures such as metal lines and vias in semiconductor devices. However, copper tends to diffuse at typical semiconductor processing temperatures. As a result, copper interconnect structures may form voids during thermal cycling.

In addition, in interconnect structure, it is typically at the junctions where a via joins a metal line structure (e.g., word lines, bit lines, source lines) to form a corner that physical stress tends to concentrate. The combination of high temperature and stress concentration makes the junctions hot spots for void formation. The voids may cause electrical opens within the copper interconnect structures. Such defects adversely impact chip yield in advanced semiconductor devices.

DETAILED DESCRIPTION

The present disclosure is directed semiconductor devices, and specifically to metal interconnect structures including a via made of refractory materials.

Generally, the structures and methods of the present disclosure can be used to form interconnect structures such as vias, metal line structures and integrated via and metal line structures. The interconnect structures electrically connect at least some of the electrical components of an integrated circuit which may include a plurality of electrical components. The interconnect structures of the present disclosure include a via formed using a refractory metal or alloy of refractory metals. In some embodiments, the vias may include a bottom portion. The bottom portion may include a bottom head that that extends below the via opening and extends laterally beyond lower edges of the via opening. The via may further include a middle portion located in a via opening. The via may further include a top portion. The top portion may include a top head that extends above the via opening and extends laterally beyond upper edges of the via opening. The use of refractory metals, which can withstand higher temperatures than copper, reduces diffusion of the via atoms into the interconnect-level dielectric layers, thereby reducing the formation of voids around the vias. Further, the use refractory metal vias with head structures that extend into the metal line structures and extend beyond the edges of the vias further reduce void formation by covering the void formation hot spots with slower diffusing metals.

Referring toFIG.1, a first exemplary structure that may implement the various embodiment interconnect structures101is illustrated. The first exemplary structure includes a substrate8that contains a semiconductor material layer10. The substrate8may include a bulk semiconductor substrate such as a silicon substrate in which the semiconductor material layer continuously extends from a top surface of the substrate8to a bottom surface of the substrate8, or a semiconductor-on-insulator layer including the semiconductor material layer10as a top semiconductor layer overlying a buried insulator layer (such as a silicon oxide layer). The exemplary structure may include various devices regions, which can include a memory array region150in which at least one array of resistive memory elements may be subsequently formed. The exemplary structure may also include a peripheral region250in which electrical connections between each array of resistive memory elements and a peripheral circuit including field effect transistors may be subsequently formed. Areas of the memory array region150and the peripheral region250may be employed to form various elements of the peripheral circuit.

Semiconductor devices such as field effect transistors may be formed on, and/or in, the semiconductor material layer10. For example, shallow trench isolation structures12may be formed in an upper portion of the semiconductor material layer10by forming shallow trenches and subsequently filling the shallow trenches with a dielectric material such as silicon oxide. Other suitable dielectric materials are within the contemplated scope of disclosure. Various doped wells (not expressly shown) may be formed in various regions of the upper portion of the semiconductor material layer10by performing masked ion implantation processes.

Gate structures20may be formed over the top surface of the substrate8by depositing and patterning a gate dielectric layer, a gate electrode layer, and a gate cap dielectric layer. Each gate structure20can include a vertical stack of a gate dielectric22, a gate electrode24, and a gate cap dielectric28, which is herein referred to as a gate stack (22,24,28). Ion implantation processes can be performed to form extension implant regions, which can include source extension regions and drain extension regions. Dielectric gate spacers26may be formed around the gate stacks (22,24,28). Each assembly of a gate stack (22,24,28) and a dielectric gate spacer26may constitute a gate structure20. Additional ion implantation processes may be performed that use the gate structures20as self-aligned implantation masks to form deep active regions. Such deep active regions may include deep source regions and deep drain regions. Upper portions of the deep active regions may overlap with portions of the extension implantation regions. Each combination of an extension implantation region and a deep active region may constitute an active region14, which may be a source region or a drain region depending on electrical biasing. A semiconductor channel15can be formed underneath each gate stack (22,24,28) between a neighboring pair of active regions14. Metal-semiconductor alloy regions18may be formed on the top surface of each active region14. Field effect transistors may be formed on the semiconductor material layer10. Each field effect transistor can include a gate structure20, a semiconductor channel15, a pair of active regions14(one of which functions as a source region and another of which functions as a drain region), and optional metal-semiconductor alloy regions18. A complementary metal-oxide-semiconductor (CMOS) circuit330may be provided on the semiconductor material layer10, which may include a periphery circuit for the array(s) of resistive memory elements to be subsequently formed.

Various interconnect-level structures may be subsequently formed, which are formed prior to formation of an array of resistive memory elements and are herein referred to as lower interconnect-level structures (L0, L1, L2). In case a two-dimensional array of resistive memory elements is to be subsequently formed over two levels of interconnect-level metal lines, the lower interconnect-level structures (L0, L1, L2) may include a contact-level structure L0, a first interconnect-level structure L1, and a second interconnect-level structure L2. The contact-level structure L0may include a planarization dielectric layer31A including a planarizable dielectric material such as silicon oxide and various contact via structures41V contacting a respective one of the active regions14or the gate electrodes24and formed within the planarization dielectric layer31A. The first interconnect-level structure L1includes a first interconnect-level dielectric layer31B and first metal lines41L formed within the first interconnect-level dielectric layer31B. The first interconnect-level dielectric layer31B is also referred to as a first line-level dielectric layer. The first metal lines41L may contact a respective one of the contact via structures41V. The second interconnect-level structure L2includes a second interconnect-level dielectric layer32, which may include a stack of a first via-level dielectric material layer and a second line-level dielectric material layer or a line-and-via-level dielectric material layer. The second interconnect-level dielectric layer32may have formed there within second interconnect-level metal interconnect structures (42V,42L), which includes first metal via structures42V and second metal lines42L. Top surfaces of the second metal lines42L may be coplanar with the top surface of the second interconnect-level dielectric layer32.

In an embodiment, an array95of resistive memory elements may be formed in the memory array region150over the second interconnect-level structure L2. A third interconnect-level dielectric layer33may be formed during formation of the array95of resistive memory elements. The set of all structures formed at the level of the array95of resistive memory elements is herein referred to as a third interconnect-level structure L3.

Third interconnect-level metal interconnect structures (43V,43L) may be formed in the third interconnect-level dielectric layer33. The third interconnect-level metal interconnect structures (43V,43L) may include second metal via structures43V and third metal lines43L. Additional interconnect-level structures may be subsequently formed, which are herein referred to as upper interconnect-level structures (L4, L5, L6, L7). For example, the upper interconnect-level structures (L4, L5, L6, L7) may include a fourth interconnect-level structure L4, a fifth interconnect-level structure L5, a sixth interconnect-level structure L6, and a seventh interconnect-level structure L7. The fourth interconnect-level structure L4may include a fourth interconnect-level dielectric layer34having formed therein fourth interconnect-level metal interconnect structures (44V,44L), which can include third metal via structures44V and fourth metal lines44L. The fifth interconnect-level structure L5may include a fifth interconnect-level dielectric layer35having formed therein fifth interconnect-level metal interconnect structures (45V,45L), which can include fourth metal via structures45V and fifth metal lines45L. The sixth interconnect-level structure L6may include a sixth interconnect-level dielectric layer36having formed therein sixth interconnect-level metal interconnect structures (46V,46L), which can include fifth metal via structures46V and sixth metal lines46L. The seventh interconnect-level structure L7may include a seventh interconnect-level dielectric layer37having formed therein sixth metal via structures47V (which are seventh interconnect-level metal interconnect structures) and metal bonding pads47B. The metal bonding pads47B may be configured for solder bonding (which may employ C4 ball bonding or wire bonding), or may be configured for metal-to-metal bonding (such as copper-to-copper bonding).

Each interconnect-level dielectric layer may be referred to as an interconnect-level dielectric (ILD) layer30. Each interconnect-level metal interconnect structures may be referred to as a metal interconnect structure40. Each contiguous combination of a metal via structure and an overlying metal line located within a same interconnect-level structure (L2-L7) may be formed sequentially as two distinct structures by employing two single damascene processes, or may be simultaneously formed as a unitary structure employing a dual damascene process. Each of the metal interconnect structure40may include a respective metallic liner (such as a layer of TiN, TaN, or WN having a thickness in a range from 2 nm to 20 nm) and a respective metallic fill material. As discussed in further detail below, the metallic fill material may comprise copper. However, other suitable materials may be within the contemplated scope of disclosure. Various etch stop dielectric layers and dielectric capping layers may be inserted between vertically neighboring pairs of ILD layers30, or may be incorporated into one or more of the ILD layers30.

While the exemplary structure is illustrated employing an embodiment in which the array95of resistive memory elements may be formed as a component of a third interconnect-level structure L3, the array95of resistive memory elements may be formed as components of any other interconnect-level structure (e.g., L1-L7). Further, while the exemplary structure is illustrated with a set of eight interconnect-level structures, the exemplary structure may be formed with a different number of interconnect-level structures is employed.

FIGS.2A and2Billustrate a simplified exemplary interconnect structure101according to an embodiment of the present disclosure. The simplified illustrations omit materials such as interconnect-level dielectric layers30shown inFIG.1. Interconnect-level dielectric layers may be referred to as first and second interconnect-level dielectric layers124aand124bas discussed below. First and second interconnect-level dielectric layers124aand124bmay be any adjacent interconnect-level dielectric layers30shown inFIG.1. The exemplary interconnect structure101may include a via100in accordance with various embodiments of the disclosure and at least one line structure102a,102b. The via100may include a top portion100cwhich includes a top head, a middle portion100blocated in a via opening (discussed in more detail below) and a bottom portion100awhich includes a bottom head. The top portion100cextends into a top line structure102b. The top line structure102bmay be a line, such as a word line, bit line or source line. The bottom portion100aextends into a bottom line structure102a. The bottom line structure102amay be a line, such as a word line, bit line or source line. The via100may be formed as any of the metal via structures discussed above with reference toFIG.1. In addition, top line structure102band bottom line structure102amay be formed as any of the metal lines of adjacent interconnect-level dielectric layers30discussed above with reference toFIG.1. For example, top line structure102bmay be formed as fourth metal line44L inFIG.1, via100may be formed as fourth metal via structure44V as shown inFIG.1, and bottom line structure102amay be formed as third metal line43L as shown inFIG.1.

Referring toFIG.2B, the top line structure102band the bottom line structure102amay include a first copper fill layer103and a diffusion barrier layer106over the first copper fill layer103. The diffusion barrier layer106prevents copper atoms from the first copper fill layer103from diffusing out of the first copper fill layer103and into the various electronic devices, such as the field effect transistors discussed above. The presence of a diffusion barrier layer106may be advantageous because copper may damage the electronic devices. Optionally, an adhesion layer108may be provided between the diffusion barrier layer106and the first copper fill layer103. The adhesion layer108improves the adhesion of the first copper fill layer103to the diffusion barrier layer106. As illustrated and discussed in more detail below, the top portion100cand the bottom portion100aeach extend beyond the edges of the via opening, resulting the via having a “dumbbell” shape.

FIG.3illustrates a first step in a method of making an interconnect structure101according to various embodiments. In the first step, a first interconnect-level dielectric layer124amay be provided. While referred to as first interconnect-level dielectric layer124a, such an interconnect-level dielectric layer may represent any of interconnect-level dielectric layers30as shown inFIG.1. A first trench104, such as a trench may be formed in the first interconnect-level dielectric layer124a. The first trench104may be formed by first depositing a photoresist layer (not shown) over the surface of the first interconnect-level dielectric layer124a. The photoresist layer may be photo-lithographically patterned to mask areas of the first interconnect-level dielectric layer124a. Next, the first interconnect-level dielectric layer124amay be etched using the patterned photoresist layer as a mask to form the first trench104. The photoresist may be either a negative or a positive photoresist. The remaining photoresist layer may be removed, for example, by ashing.

Referring toFIG.4, a diffusion barrier layer106may be conformally deposited on the bottom wall and sidewalls of the first trench104. The diffusion barrier layer106may be made of a metal nitride or metal oxide material, such as TaN, TiN, WN, and AlOx. Other suitable materials that may be used to form the diffusion barrier layer106are within the contemplated scope of disclosure. The diffusion barrier layer106may have a thickness in a range from 2 nm to 20 nm. In embodiments, an optional adhesion layer108may be conformally deposited over the diffusion barrier layer106. The adhesion layer108adheres to both the diffusion barrier layer106and the first copper fill layer103that may be subsequently deposited. The adhesion layer108may provide better adhesion to both the first copper fill layer103and diffusion barrier layer106than the first copper fill layer103may have to the diffusion barrier layer106directly. The adhesion layer may be made of Cr, Ti or any other suitable metal or alloy and may have a thickness in a range from 2 nm to 20 nm. A capping layer115may be formed over the first trench104covering the diffusion barrier layer106, the adhesion layer108and the first copper fill layer103. “Selective,” as used herein refers to the ability of one material to be etched at a higher rate than a different material subject to the same etchant. A “non-selective” material etches at substantial the same rate as other materials subjected to the same etchant. However, a non-selective material may be made selective with a suitable pretreatment, use of a particular precursor, use of selected etchants, incubation of the surface or a combination thereof. The capping layer may be made of the same material as the diffusion barrier layer106or any other suitable material. Optionally, one or more etch stop layer116may be deposited over the surface of the first interconnect-level dielectric layer124aand the capping layer115. The etch stop layer(s)116may be formed from metal nitride, a metal carbide or a metal oxide and may be made by any suitable method. Other etch stop layer materials are within the contemplated scope of disclosure. The diffusion barrier layer106, adhesion layer108and first copper fill layer103formed within first trench104in the first interconnect-level dielectric layer124amay comprise the metal line such as bottom line structure102a.

Referring toFIG.5, a second interconnect-level dielectric layer124bmay be formed over the one or more etch stop layers116. The second interconnect-level dielectric layer124bmay be formed by any suitable method such as chemical vapor deposition, plasma enhanced chemical vapor deposition or atomic layer deposition. A second trench105may be formed in the second interconnect-level dielectric layer124b. In an embodiment, the second trench105in the second interconnect-level dielectric layer124bmay be a trench which may aligned in a direction perpendicular to the first trench104in the first interconnect-level dielectric layer124a. Further, as illustrated inFIG.5, a via opening110may be formed in the in the bottom of the second trench105in the second interconnect-level dielectric layer124bextending to the capping layer115. The second trench105and the via opening110may be made with two separate single damascene processes or in the same step by a dual damascene process.

Referring toFIG.6, a barrier layer112may be deposited in the second trench105in the second interconnect-level dielectric layer124b. In embodiments, the barrier layer112may also be deposited on the sidewalls of the via opening110. In embodiments, the barrier layer112may be made of a diffusion barrier material. For example, the barrier layer112may be made of Ta, Co, Ru or alloys thereof. The barrier layer112may be made of the same material as the diffusion barrier layer106or any other suitable material. Further, the barrier layer112, may be deposited by any suitable method such as chemical vapor deposition, plasma enhanced chemical vapor deposition or atomic layer deposition.

Referring toFIG.7, the capping layer115and the first copper fill layer103may be etched to form a cavity113in the first copper fill layer103. In various embodiments, the cavity113includes undercuts111which extend below the via opening110and extend laterally beyond lower edges of the via opening110, i.e. the undercuts111extend below the capping layer115. The resulting cavity113has bottom surface that is substantially concave. The capping layer115may be either dry etched or wet etched. To form the cavity113with the undercuts111in the first copper fill layer103, the first copper fill layer103may first be wet or dry etched. Then, to form the undercuts111, a first portion of the first copper fill layer103may be oxidized to form a second portion comprising copper oxide (not shown) under the capping layer. The copper oxide portion may then be removed by wet etching.

Referring toFIG.8, a first conformal liner114may be formed on the exposed surface of the first copper fill layer103in the cavity113. The first conformal liner114may formed by any suitable method, such as chemical vapor deposition, plasma enhanced chemical vapor deposition or atomic layer deposition. The first conformal liner114may be made of the same material as the capping layer115or any other suitable material, such as Ta, Co, Ru or alloys thereof.

Referring toFIG.9, a refractory material, such as Ni, Co, Ru, Re, Ir, W, Mo, Rh, Fe, Pd, Pt, Os, Nb and alloys thereof, may be deposited in the cavity113in the first copper fill layer103, the via opening110and overflowing into the second trench105in the second interconnect-level dielectric layer124b. Other suitable refractory materials to form the via may be within the contemplated scope of disclosure. In this manner, a via100may be formed that includes a bottom portion100athat includes a bottom head that extends below the via opening110and extends laterally beyond lower edges of the via opening110, a middle portion100bin the via opening110and a top portion100cthat includes a top head that extends above the via opening110and extends laterally beyond upper edges of the via opening110into the second trench105in the second interconnect-level dielectric layer124b. As the refractory materials fill the cavity113, the bottom surface of the resulting bottom portion100aof the via100may have a shape that is substantially convex. The via100may be formed by a selective chemical vapor deposition process, a selective atomic layer deposition process or by an electrolysis plating deposition process.

Referring toFIG.10, a second conformal liner120may be formed over the barrier layer112and the top portion100cof the via100in the second trench105in the second interconnect-level dielectric layer124b. The second conformal liner120may be made of an suitable material, such as Ta, Co, Ru or alloys thereof. In various embodiments, the second conformal liner120is made of a material to improve adhesion of a first copper fill layer103to the barrier layer112. The second conformal liner120made be formed by any suitable method such as chemical vapor deposition, plasma enhanced chemical vapor deposition or atomic layer deposition.

Referring toFIG.11, the second trench105in the second interconnect-level dielectric layer124bmay be filled with a second copper fill layer109. Prior to filling the second trench105with the second copper fill layer109, a diffusion barrier layer106(not shown) may be conformally deposited on the sidewalls of the second trench105. In addition, an optional adhesion layer108may be conformally deposited over the diffusion barrier layer106(both not shown inFIG.11, shown inFIG.12B) prior to second copper fill layer109. After filling the second trench105with the second copper fill layer109, the surface of the second interconnect-level dielectric layer124band the second copper fill layer109may be planarized by chemical mechanical polishing. After planarizing, the surface of the second interconnect-level dielectric layer124band the second copper fill layer109, a second capping layer125may be formed on top of the planarized surface.

FIG.12Ais a vertical cross-sectional view through the line AA′ inFIG.2BwhileFIG.12Bis a vertical cross-sectional view through the line BB′ inFIG.2B. In various embodiments, the interconnect structure101includes a first interconnect-level dielectric layer124a. Located within a first trench104in the first interconnect-level dielectric layer124amay be a diffusion barrier layer106, an optional adhesion layer108and a first copper fill layer103. The bottom head of the bottom portion100aof the via100may be located in a cavity113formed in the first copper fill layer103. In some embodiments, a first conformal liner114may be provided between the first copper fill layer103and a bottom surface of bottom head of the bottom portion100aof the via100. A second interconnect-level dielectric layer124bmay be located above the first interconnect-level dielectric layer124a. In some embodiments, an etch stop layer116may be provided between the first and second interconnect-level dielectric layers124a,124b.

Located within a second trench105(illustrated inFIG.10) in the second interconnect-level dielectric layer124bmay be a diffusion barrier layer106, an adhesion layer108and a second copper fill layer109. The top portion100cthat includes a top head extends above the via opening110and extends laterally beyond upper edges of the via opening110into the second trench105in the second interconnect-level dielectric layer124b. In some embodiments, a barrier layer112may be provided between a portion of the second copper fill layer109and the top head of the top portion100cof the via100. In some embodiments, the barrier layer112may extend into and line the via opening110. The barrier layer112may be made of TaN, TiN, AlOx, a self-assembled monolayer (SAM) or combinations thereof. Other suitable materials for the barrier layer112are within the contemplated scope of disclosure.

A middle portion100bof the via100may be located in the via opening110. As illustrated inFIG.12A, the top head of the top portion100cof the via100and the bottom head of the bottom portion100aof the via100may cover junctions118between the via100and the top and bottom line structures102a,102b. By replacing the conventional copper material that may be conventionally used to form the via100with a slow diffusing refractory metal, the “dumbbell shaped” via100can reduce or eliminate void formation at the junctions118. The refractory metal materials may be more resistant to reflow than conventional copper materials at typical semiconductor processing thermal temperatures.

The top head of the top portion100cof the via100may have a maximum height HTHand the bottom head of the bottom portion100aof the via100may have a maximum height HBHin the range of 1-20 nm, such as 2-15 nm, although greater or lesser heights may be used. The top head of the top portion100cof the via100may extend a length LTHlaterally beyond the upper edges of the via opening110and the bottom head of the bottom portion100aof the via100may extend a length LBHlaterally beyond the lower edges of the via opening110in a range of 1-20 nm, such as 2-15 nm, although greater or lesser lengths may be used.

FIG.13is a vertical cross-sectional view illustrating another interconnect structure101in accordance with another embodiment of the disclosure. This embodiment is similar to embodiment illustrated inFIGS.8-12B, but omits the first conformal liner114located between the first copper fill layer103in the bottom portion100aof the via100that may be formed in the cavity113in the first interconnect-level dielectric layer124a. The present embodiment may be fabricated by following the steps illustrated inFIGS.3-7, but omitting the step illustrated inFIG.8that deposits the first conformal liner114and continuing fabrication with the steps illustrated inFIGS.9-11as discussed above.

FIG.14Ais a vertical cross-sectional view of the second embodiment interconnect structure101shown inFIG.13through the line AA′ inFIG.2B.FIG.14Bis a vertical cross-sectional view of the second embodiment interconnect structure101shown inFIG.13through the line BB′ inFIG.2B.FIGS.14A and14Bare similar toFIGS.12A and12Bdiscussed above in regards to the first embodiment. As illustrated inFIGS.14A and14B, the interconnect structure101includes a via100similar to the first embodiment via100illustrated inFIGS.12A and12B, but omits a first conformal liner114located between the first copper fill layer103and the bottom head of the bottom portion100aof the via100. Similar to the first embodiment, the top head of the top portion100cof the via100may have a maximum height HTHand the bottom head of the bottom portion100aof the via100may have a maximum height HBHin the range of 1-20 nm, such as 2-15 nm, although greater or lesser heights may be used. The top head of the top portion100cof the via100may extend a length LTHlaterally beyond the upper edges of the via opening110and the bottom head of the bottom portion100aof the via100may extend a length LBHlaterally beyond the lower edges of the via opening110in a range of 1-20 nm, such as 2-15 nm, although greater or lesser lengths may be used.

FIGS.15-16illustrate steps in fabrication another embodiment interconnect structure101. The present embodiment may be fabricated by following the steps illustrated inFIGS.3-5, but omitting the step illustrated inFIG.6that deposits a barrier layer112prior to depositing the refractory metal material to form the via100, and continuing fabrication with the steps illustrated inFIGS.7-9as discussed above followed by the steps illustrated inFIGS.15and16.

Referring toFIG.15, a barrier layer112may be conformally deposited over the surface of the second interconnect-level dielectric layer124band the top portion100cof the via100deposited in the second trench105in the second interconnect-level dielectric layer124bto form a conformal barrier layer112C. In this embodiment, the conformal barrier layer112C may be made of a selective material, resulting in a selective barrier layer. Example, selective materials include, but are not limited to, TaN, TiN, AlOx, a self-assembled monolayer (SAM) or combinations thereof. Other suitable selective materials for the conformal barrier layer112C are within the contemplated scope of disclosure.

Next, a second conformal liner120may be deposited over the conformal barrier layer112C. The second conformal liner120may be made of any suitable material and be formed by any suitable method such as chemical vapor deposition, plasma enhanced chemical vapor deposition or atomic layer deposition. The second conformal liner120may act as a copper adhesion layer and may be made of the same material as the adhesion layer108. As illustrated inFIG.17below, sidewalls of the second trench105may be lined with a diffusion barrier layer106and an adhesion layer108. In an embodiment, the conformal barrier layer112C and the diffusion barrier layer106may be made of the same material. In an embodiment the conformal barrier layer112C and the diffusion barrier layer106may be made in the same step and comprise a single continuous layer. In an embodiment, the second conformal liner120and the adhesion layer108may be made of the same material. In an embodiment the second conformal liner120and the adhesion layer108may be made in the same step and comprise a single continuous layer.

Referring toFIG.16, the second trench105in the second interconnect-level dielectric layer124bmay be filled with a second copper fill layer109. After filling the second trench105, the surface of the second interconnect-level dielectric layer124band the second copper fill layer109may be planarized by chemical mechanical polishing. After planarizing, the surface of the second interconnect-level dielectric layer124band the second copper fill layer109, a second capping layer125may be formed on top of the planarized surface.

FIG.17Ais a vertical cross-sectional view of the third embodiment interconnect structure101shown inFIG.16through the line AA′ inFIG.2B.FIG.17Bis a vertical cross-sectional view of the third embodiment interconnect structure101shown inFIG.16through the line BB′ inFIG.2B.FIGS.17A and17Bare similar toFIGS.12A and12Bdiscussed above in regards to the first embodiment. As illustrated inFIGS.17A and17B, the via opening110in the second interconnect-level dielectric layer124bdoes not include a barrier layer112on the sidewalls of the via opening110. However, the copper fill layers103may be isolated from the first and second interconnect-level dielectric layers124a,124bby the diffusion barrier layers106, the conformal barrier layer112C, the first conformal liner114and the capping layer115. Thus, diffusion of copper from copper fill layers103into the first and second interconnect-level dielectric layers may be prevented. Similar to the first and second embodiments, the top head of the top portion100cof the via100may have a maximum height HTHand the bottom head of the bottom portion100aof the via100may have a maximum height HRHin the range of 1-20 nm, such as 2-15 nm, although greater or lesser heights may be used. The top head of the top portion100cof the via100may extend a length LTHlaterally beyond the upper edges of the via opening110and the bottom head of the bottom portion100aof the via100may extend a length LBHlaterally beyond the lower edges of the via opening110in a range of 1-20 nm, such as 2-15 nm, although greater or lesser lengths may be used.

FIGS.18-27illustrate steps in making an interconnect structure101according to a fourth embodiment. Referring toFIG.18, a first trench104may be formed in a first interconnect-level dielectric layer124aas illustrated inFIG.3and described above. A diffusion barrier layer106, an optional adhesion layer108and a first copper fill layer103may be deposited in the first trench104in the first interconnect-level dielectric layer124aas illustrated inFIG.4and discussed above. However, in contrast to the first embodiment illustrated inFIG.4, a capping layer115may be omitted from being deposited over the diffusion barrier layer106, the adhesion layer108and the first copper fill layer103. In addition, the optional etch stop layer illustrated inFIG.4may be omitted.

Referring toFIG.19, a hard mask layer130may be deposited over the surface of the first interconnect-level dielectric layer124a, the diffusion barrier layer106, the adhesion layer108and the first copper fill layer103. The hard mask layer130may be made of a metal oxide or metal nitride. Other suitable hard mask materials may be within the contemplated scope of disclosure.

Referring toFIG.20, the first copper fill layer103may be etched to form a cavity123in the first copper fill layer103. First, a photoresist (not shown) may be deposited over the hard mask layer and photo-lithographically patterned to transfer a pattern to the hard mask layer130. The patterned photoresist layer may be used as a mask to etch the hard mask layer130to form a patterned hard mask layer130. The patterned hard mask layer130may be used as a mask when etching the cavity123in the first copper fill layer103. As illustrated inFIG.20the cavity123may have a substantially rectangular cross section that does not have an undercut portion. Further, the cavity123may have a bottom surface that is substantially planar. As the refractory materials fill the cavity123, the bottom surface of the resulting bottom portion100aof the via100may have a shape that is substantially planar.

Referring toFIG.21, the cavity123in the first copper fill layer103may be filled with a refractory metal to form the bottom portion100aof a via100. The cavity123may be filled prior to removing the hard mask layer130or after removing the hard mask layer130. In this embodiment, the bottom portion100aof the via100may have a substantially rectangular shape matching the shape of the cavity123. Further, the bottom portion100aof the via100may have a bottom surface that is substantially planar. After removing the hard mask layer130, the surface of the first interconnect-level dielectric layer124aand the bottom portion100aof the via100may be planarized, such as with a chemical mechanical polishing process.

Referring toFIG.22, a capping layer115may be deposited over the surface of the adhesion layer108, the first copper fill layer103and the bottom portion100aof the via100. The capping layer115may be made of the same materials and made by the same processes as the capping layer115illustrated in the first embodiment and discussed above.

Referring toFIG.23, an etch stop layer116may be deposited over the surface of the first interconnect-level dielectric layer124a, exposed portions of the diffusion barrier layer106and the capping layer115. The etch stop layer116may be made of the same materials and by the same methods as the etch stop layer illustrated inFIG.4and described above.

Referring toFIG.24A, a second interconnect-level dielectric layer124bmay be deposited over the etch stop layer116. Similarly to the step illustrated inFIG.5and discussed above, a second trench105may be formed in the second interconnect-level dielectric layer124b. Further, as discussed above in regards to the first embodiment, a via opening110may be formed in the in the bottom of the second trench105in the second interconnect-level dielectric layer124bextending to the capping layer115. Next, a barrier layer112may be deposited in the second trench105in the second interconnect-level dielectric layer124b. In embodiments, the barrier layer112may also be deposited on the sidewalls of the via opening110.

As an alternative of the fourth embodiment, a fifth embodiment of an interconnect structure101may now be described with reference toFIG.24B. In the fifth embodiment, the capping layer115may be etched in the step illustrated inFIG.24Aand discussed above. The preceding steps and the remaining steps of the fourth embodiment may be performed as described below with reference toFIGS.25-28B. In the fifth embodiment, the bottom portion100a, middle portion100band tip portion100cform a continuous via100which does not include a capping layer115between the bottom portion100aand the middle portion100b.

Referring toFIG.25, a refractory material, such as a refractory metal or alloy may be deposited in the via opening110and overflowing into the second trench105in the second interconnect-level dielectric layer124b. In this manner, a via100may be formed that includes a bottom portion100athat includes a bottom head that extends below the via opening110and extends laterally beyond lower edges of the via opening110, a middle portion100bin the via opening110and a top portion100cthat includes a top head that extends above the via opening110and extends laterally beyond upper edges of the via opening110. The via100may be formed by a chemical vapor deposition process, an atomic layer deposition process or by an electrolysis plating deposition process.

Referring toFIG.26, a second conformal liner120may be formed over the barrier layer112and the top portion100cof the via100in the second trench105in the second interconnect-level dielectric layer124b. The second conformal liner120may be made of an suitable material. In various embodiments, the second conformal liner120is made of a material to improve adhesion of a second copper fill layer109to the barrier layer112. The second conformal liner120made be formed by any suitable method such as chemical vapor deposition, plasma enhanced chemical vapor deposition or atomic layer deposition.

Referring toFIG.27, the second trench105in the second interconnect-layer dielectric layer124bmay be filled with a second copper fill layer109. After filling the second trench105, the surface of the second interconnect-level dielectric layer124band the second copper fill layer109may be planarized by chemical mechanical polishing. After planarizing, the surface of the second interconnect-level dielectric layer124band the second copper fill layer109, a second capping layer125may be formed on top of the planarized surface.

FIG.28Ais a vertical cross-sectional view of the fourth embodiment interconnect structure101shown inFIG.27through the line AA′ inFIG.2B.FIG.28Bis a vertical cross-sectional view of the fourth embodiment interconnect structure101shown inFIG.27through the line BB′ inFIG.2B.FIGS.28A and28Bare similar toFIGS.12A and12Bdiscussed above in regards to the first embodiment. As in the first embodiment, the via100of the fourth embodiment has a substantially “barbell” shape. However, the bottom portion100amay be square or rectangular in shape. The embodiment illustrated inFIGS.28A and28Bis otherwise the same as the first embodiment. Similar to the first embodiment, the top head of the top portion100cof the via100may have a maximum height HTHand the bottom head of the bottom portion100aof the via100may have a maximum height HBHin the range of 1-20 nm, such as 2-15 nm, although greater or lesser heights may be used. The top head of the top portion100cof the via100may extend a length LTHlaterally beyond the upper edges of the via opening110and the bottom head of the bottom portion100aof the via100may extend a length LBHlaterally beyond the lower edges of the via opening110in a range of 1-20 nm, such as 2-15 nm, although greater or lesser lengths may be used.

FIG.29is a flowchart illustrating a general method200of making a via100according to various embodiments. Referring to step202, a first trench104may be formed in a first interconnect-level dielectric layer124a. Referring to step204, the first trench104may be filled with first copper fill layer103. Referring to step206, a second interconnect-level dielectric layer124bmay be deposited over the first copper fill layer103and the first interconnect-level dielectric layer124a. Referring to step208, the second interconnect-level dielectric layer124bmay be etched to form a second trench105. Referring to step210, the second interconnect-level dielectric layer124bmay be etched to form a via opening110in the second interconnect-level dielectric layer124b, the via opening110extending through the second interconnect-level dielectric layer124band exposing a top surface of the first copper fill layer103in the first trench104. Referring to step212, a portion of the first copper fill layer103in the first trench104may be etched to form a cavity113in the first copper fill layer103in the first trench104, the cavity113including undercuts111under the second interconnect-level dielectric layer124b. Referring to step214, a refractory material may be deposited such that the refractory material: fills the cavity113in the first copper fill layer103, including the undercut111, to form a bottom portion100aof a via100having a bottom head, fills the via opening110in the second interconnect-level dielectric layer124band forms a top portion100chaving a top head in the second trench105that extends above the via opening110and extends laterally beyond upper edges of the via opening110. Referring to step216, a second copper fill layer109may be deposited to fill the second trench105.

FIG.30is a flowchart illustrating a general method300of making a via100according to various embodiments. Referring to step202, a first trench104may be formed in a first interconnect-level dielectric layer124a. Referring to step204, the first trench104may be filled with a first copper fill layer103. Referring to step306, the first copper fill layer103may be etched to form a cavity123. Referring to step308, the cavity113may be filled with a refractory metal to form a bottom portion100aof a via100having a bottom head. Referring to step310, a capping layer115may be deposited over the refractory metal and the first copper fill layer103. Referring to step312, a second interconnect-level dielectric layer124bmay be deposited over the capping layer115and the first interconnect-level dielectric layer124a. Referring to step314, the second interconnect-level dielectric layer124bmay be etched to form a second trench105and a via opening110, the via opening110extending from the second trench105to the capping layer115. Referring to step316, a refractory material may be deposited such that the refractory material fills the via opening110in the second interconnect-level dielectric layer124band forms a top portion100chaving a top head in the second trench105that extends above the via opening110and extends laterally beyond upper edges of the via opening110. Referring to step318, the second trench105may be filled with a second copper fill layer109.

Generally, the structures and methods of the present disclosure can be used to form interconnect structures101such as vias100, metal line structures102a,102band integrated via100and metal line structures102a,102b. The interconnect structures101, may include the vias100, electrically connecting at least some of the electrical components of an integrated circuit which includes a plurality of electrical components. The interconnect structures101of the of the present disclosure include a via100made of a refractory metal or alloy of refractory metals. In embodiments, the vias100include a bottom portion100awhich includes a bottom head that that extends below the via opening110and extends laterally beyond lower edges of the via opening110, a middle portion100blocated in a via opening110and a top portion100cwhich includes a top head that extends above the via opening110and extends laterally beyond upper edges of the via opening110. The use of refractory metals, which can withstand higher temperatures than copper, reduces diffusion of the via atoms into the interconnect-level dielectric layers124a,124b, thereby reducing the formation of voids around the vias100. Further, the use refractory metal vias with head structures that extend into the metal line structures102a,102band extend beyond the edges of the vias100further reduce void formation by covering the void formation hot spots with slower diffusing metals.

Embodiments of the present disclosure include a via100including a middle portion100blocated in a via opening110in a second interconnect-level dielectric layer124b, a top portion100cincluding a top head that extends above the via opening110and extends laterally beyond upper edges of the via opening110and a bottom portion100aincluding a bottom head that extends below the via opening110and extends laterally beyond lower edges of the via opening110in a first interconnect-level dielectric layer124a. The via100may be formed of a refractory material.

Other embodiments are drawn to a method of a method of making an interconnect structure101including forming a first trench104in a first interconnect-level dielectric layer124a, filling the first trench104with a first copper fill layer103, forming a first trench104in a first interconnect-level dielectric layer124aand filling the first trench104with a first copper fill layer103. The method further includes etching the first copper fill layer103to form a cavity123. The method further includes depositing a refractory metal to fill the cavity to form a bottom portion100aof a via100having a bottom head. The method further including depositing a capping layer115over the bottom portion100aof a via100and the first copper fill layer103. The method further including depositing a second interconnect-level dielectric layer124bover the capping layer115and the first interconnect-level dielectric layer124a. The method further includes etching the second interconnect-level dielectric layer124bto form a second trench105and a via opening110in the second interconnect-level dielectric layer124b, the via opening110extending from the second trench105to the capping layer115. The method including depositing a refractory material such that the refractory material fills the via opening110in the second interconnect-level dielectric layer124band forms a top portion100cof a via100having a top head in the second trench105that extends above the via opening110and extends laterally beyond upper edges of the via opening110. The method further includes filling the second trench105with a second copper fill layer109.

In an embodiment, depositing a refractory material such that the refractory material fills the cavity123in the first copper fill layer103to form a bottom portion100aof a via100having a bottom head comprises: forming a hard mask layer130over the first interconnect-level dielectric layer124a, patterning the hard mask layer130to expose a portion of the surface of the first copper fill layer103in the first trench104, using a single damascene process to remove a portion of the first copper fill layer103in the first trench104to form a cavity123in the first copper fill layer103and deposit refractory material to form a bottom head in the cavity123.

Other embodiments are drawn to a method of a method of making an interconnect structure101including forming a first trench104in a first interconnect-level dielectric layer124a, filling the first trench104with a first copper fill layer103, depositing a second interconnect-level dielectric layer124bover the first copper fill layer103and the first interconnect-level dielectric layer124a, and etching the second interconnect-level dielectric layer124bto form a second trench105. The method also includes etching the second interconnect-level dielectric layer124bto form a via opening110in the second interconnect-level dielectric layer124b, the via opening110extending through the second interconnect-level dielectric layer124band exposing a top surface of the first copper fill layer103and etching a portion of the first copper fill layer103in the first trench104to form a cavity113in the first copper fill layer103in the first trench104, the cavity113including an undercut111under the second interconnect-level dielectric layer124b. The method also includes depositing a refractory material such that the refractory material: fills the cavity113in the first copper fill layer103, including the undercut111, to form a bottom portion100aof a via100having a bottom head, fills the via opening110in the second interconnect-level dielectric layer124band forms a top portion100chaving a top head in the second trench105that extends above the via opening110and extends laterally beyond upper edges of the via opening110. The method also includes filling the second trench105with a second copper fill layer109.

In an embodiment, the method further includes forming a first conformal liner114over the first copper fill layer103in the cavity113in the copper fill layer103. In an embodiment, the method further includes depositing a first conformal liner114over the top head prior to filling the second trench105with a second copper fill layer109. In an embodiment, the method further includes depositing a barrier layer112over the top head prior to depositing the first conformal liner114. In an embodiment, etching a portion of the first copper fill layer103in the first trench104includes: wet or dry etching of a first portion of the first copper fill layer103, partially oxidizing a second portion of the first copper fill layer103in the first trench104to form a copper oxide portion, and etching the copper oxide portion.

In an embodiment, depositing the refractory material is performed by selective chemical vapor deposition, selective atomic layer deposition or electrolysis deposition. In an embodiment, etching the second interconnect-level dielectric layer124bto form a second trench105and etching the second interconnect-level dielectric layer124bto form a via opening110in the second interconnect-level dielectric layer124bmay be performed by a single damascene process or dual damascene process. In an embodiment, the method further includes planarizing a top surface of the second interconnect-level dielectric layer124band the second copper fill layer109in the second trench105.