Thin film transistor array substrate for a liquid crystal display

A thin film transistor substrate for a liquid crystal display includes an insulating substrate, and a gate line assembly formed on the substrate. The gate line assembly has a double-layered structure with a lower layer exhibiting good contact characteristics with respect to indium tin oxide, and an upper layer exhibiting low resistance characteristics. A gate insulating layer, a semiconductor layer, a contact layer, and first and second data line layers are sequentially deposited onto the substrate with the gate line assembly. The first and second data line layers are patterned to form a data line assembly, and the contact layer is etched through the pattern of the data line assembly such that the contact layer has the same pattern as the data line assembly. A passivation layer is deposited onto the data line assembly, and a photoresist pattern is formed on the passivation layer by using a mask of different light transmissties mainly at a display area and a peripheral area. The passivation layer and the underlying layers are etched through the photoresist pattern to form a semiconductor pattern and contact windows. A pixel electrode, a supplemental gate pad and a supplemental data pad are then formed of indium tin oxide or indium zinc oxide. The gate and data line assemblies may be formed with a single layered structure. A black matrix and a color filter may be formed at the structured substrate before forming the pixel electrode, and an opening portion may be formed between the pixel electrode and the data line to prevent possible short circuits.

BACKGROUND OF THE INVENTION

(a) Field of the Invention

The present invention relates to a thin film transistor array (TFT) substrate for a liquid crystal display and a method for fabricating the same, and more particularly, to a method for fabricating a TFT array substrate of good performance in processing steps.

(b) Description of the Related Art

Generally, a liquid crystal display (LCD) is formed with two glass substrates, and a liquid crystal layer sandwiched between the substrates.

One of the substrates has a common electrode, a color filter and a black matrix, and the other substrate has pixel electrodes and thin film transistors (TFTs). The former substrate is usually called the “color filter substrate,” and the latter substrate is usually called the “TFT array substrate.”

The TFT array substrate is fabricated by forming a plurality of thin films on a glass substrate, and performing photolithography with respect to the thin films. In photolithography, many masks should be used for uniformly etching the thin films, and this involves complicated processing steps and increased production cost. Therefore, the number of masks becomes a critical factor in the fabrication efficiency of the TFT array substrate.

Furthermore, contact windows tend to be over-etched during the TFT formation, causing contact failure. Thus, it is required that stable and rigid contact between the desired electrodes should be ensured in the device fabrication.

On the other hand, the black matrix provided at the color filter substrate should be formed with a certain width considering the alignment margin for the color filter substrate joining the TFT array substrate. However, the larger black matrix reduces the aperture ratio. Therefore, the opening ratio of the black matrix should be also considered in fabricating the TFT array substrate.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a TFT array substrate for a liquid crystal display of good performance, and a method for fabricating the same with a reduced number of masks.

It is another object of the present invention to provide a method for fabricating a TFT array substrate that ensures suitable contacts between the electrode components.

It is still another object of the present invention to provide a method for fabricating a TFT array substrate with a suitable opening ratio.

These and other objects may be achieved by a TFT array substrate including a gate line assembly with gate lines proceeding in the horizontal direction, gate electrodes branched from the gate lines, and gate pads connected to end portions of the gate lines to receive scanning signals from the outside and transmit them to the gate lines. The gate line assembly may be formed with a single, double or triple layered structure. When the gate line assembly is formed with a double or triple layered structure, one layer is formed with a low resistance material while the other layer is formed with a material having good contact characteristics.

The gate line assembly is overlaid sequentially with a gate insulating layer, semiconductor patterns, and ohmic contact patterns.

A data line assembly is formed on the ohmic contact patterns with data lines proceeding in the vertical direction, data pads connected to end portions of the data lines to receive picture signals from the outside, and source electrodes branched from the data lines. The data line assembly further includes drain electrodes for the TFTs, and conductive patterns for the storage capacitors. The drain electrode is positioned opposite to the source electrode With respect to the gate electrode while being separated from the source electrode. The conductive pattern is positioned above the gate line while overlapping the same. The conductive pattern is connected to a pixel electrode to form a storage capacitor. However, in case the overlapping of the pixel electrode and the gate line can give a sufficient amount of storage capacity, the conductive pattern may be omitted. The data line assembly may have a single, double or triple layered structure.

The semiconductor patterns have a shape similar to that of the data line assembly and the underlying ohmic contact patterns. The semiconductor layer extends to the peripheral portion of the substrate while covering the latter.

A passivation layer covers the data line, the data pad, the source electrode, the drain electrode, the semiconductor pattern, and the overlapping portions between the gate line and the data line.

Contact windows are formed at the passivation layer while exposing the drain electrode and the data pad. The contact window exposing the drain electrode may be extended toward the pixel area such that it can expose the borderline of the drain electrode completely. Another contact window is formed at the passivation layer while passing through the semiconductor pattern and the gate insulating layer to expose the gate pad to the outside.

The pixel electrode is formed on the gate insulating layer at the pixel area defined by the neighboring gate and data lines. The pixel electrode is electro-physically connected to the drain electrode through the contact window such that it receives picture signals from the TFT while making the required electrical field in association with a common electrode. The pixel electrode is extended over the conductive pattern, and electro-physically connected to the latter such that it serves as a storage capacitor together with the conductive pattern and the gate line.

A subsidiary gate pad and a subsidiary data pad are formed on the gate pad and the data pad, respectively. The subsidiary gate and data pads are formed together with the pixel electrode with the same material, and contact the gate and data pads, respectively.

An opening portion may be formed between the pixel electrode and the data line to prevent a possible short circuit thereof.

According to one aspect of the present invention, the steps of fabricating the TFT array substrate may be performed as follows.

A gate line assembly is first formed on a substrate by using a first mask. Then a gate insulating layer, a semiconductor layer, a contact layer, and first and second metal data line layers are deposited onto the substrate with the gate line assembly in a sequential manner. A data line assembly with a predetermined pattern is formed through etching the first and second metal data line layers by using a second mask. The contact layer is etched through the pattern of the data line assembly such that the contact layer has the same pattern as the data line assembly.

A passivation layer is then deposited onto the structured substrate such that the passivation layer covers the semiconductor layer and the data line assembly. A photoresist film is coated onto the passivation layer, and exposed to light by using a third mask. The photoresist film is then developed to thereby form a photoresist pattern partially differentiated in thickness.

A semiconductor pattern is formed by etching the passivation layer and the underling semiconductor layer at the pixel area through the photoresist pattern. First and second contact windows are formed by etching the passivation layer and the underlying second layers of the drain electrode and the data pad. The third contact window is formed by etching the passivation layer and the underlying semiconductor layer and gate insulating layer, and the second layer of the gate pad.

After the photoresist pattern is removed, a pixel electrode is formed by using a fourth mask such that the pixel electrode is connected to the drain electrode through the first contact window.

The second metal gate or data line layer may be formed with aluminum or aluminum alloy, and the first layer with chrome, molybdenum, or molybdenum alloy. Subsidiary gate and data pads may be formed during the step of forming the pixel electrode such that they are connected to the first layers of the gate and data pads through the second and third contact windows. The pixel electrode as well as the subsidiary gate and data pads may be formed with indium tin oxide or indium zinc oxide.

The etching with respect to the second layers of the drain electrode, the gate pad and the data pad may be performed by using a wet-etching technique or a dry-etching technique.

The step of exposing the passivation layer positioned over the drain electrode and at the pixel area may be performed by removing the photoresist film over the passivation layer through oxygen-based ashing.

The third mask for forming the photoresist pattern may be provided with a transparent substrate, a first layer formed on the transparent substrate, and a second layer formed on the transparent substrate while overlapping with the first layer. The first layer has a light transmissivity lower than the transparent substrate, and the second layer has a light transmissivity different from those of the substrate and the first layer. The transparent substrate is established to have a first portion without the first and second layers, a second portion with only the first layer, and a third portion with both the first and second layers.

The transparent substrate has a light transmissivity of 90%, the first layer has a light transmissivity of 20-40%, and the second layer has a light transmissivity of 3% or less. The first and second layers may have a light transmissivity control pattern of slits or mosaics.

According to another aspect of the present invention, a black matrix and a color filter are formed on the structured substrate before the step of forming the pixel electrode.

After the semiconductor layer is etched to form a semiconductor pattern and the remaining photoresist film is removed, an organic black matric layer is deposited onto the substrate, and etched through a fourth mask to thereby form a black matrix pattern. Alternatively, a black photoresist film may be used to form such a black matrix pattern.

A color filter is formed at the pixel area between the neighboring data lines, and at that point the formation of the pixel electrode and subsidiary gate and data pads is complete.

According to still another aspect of the present invention, the formation of the passivation layer is deferred after the formation of the semiconductor pattern.

A gate line assembly is first formed at the substrate by using a first mask. A gate insulating layer, a semiconductor layer, an ohmic contact layer, and a metal data line layer are then sequentially deposited onto the substrate. The metal data line layer, the ohmic contact layer and the semiconductor layer are etched through a second mask to thereby form the desired patterns with similar outlines except that the semiconductor pattern is present at the channel region between the source and drain electrodes.

A passivation layer is deposited onto the substrate10with the data line assembly, and etched through a third mask to thereby form contact windows. An organic black matrix layer is then deposited onto the substrate, and etched through a fourth mask to thereby form a black matrix pattern. Thereafter, a color filter is formed, and the formation of a pixel electrode and subsidiary gate and data pads is complete.

In the above process, the black matrix pattern may perform the function of the passivation layer without forming the latter. Furthermore, it is also possible that the color filter is placed directly over the substrate and the gate line by removing the portion of the gate insulating layer positioned between the neighboring data lines.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of this invention will be explained with reference to the accompanying drawings.

First Preferred Embodiment

FIGS. 1to5illustrate a TFT array substrate according to a first preferred embodiment of the present invention.

A plurality of panel regions for LCDs may be made at one insulating substrate at the same time. For example, as shown inFIG. 1, four panel regions110,120,130and140are made with display areas111,121,131and141, and peripheral areas112,122,132and142. TFTs, lines and pixel electrodes for the main components are repeatedly arranged at the display areas111to141, whereas pads and other static electricity protection circuits for the components connected to the driving circuits are provided at the peripheral areas112to142.

The display areas111to141and the peripheral areas112to142are divided into several regions, and each region is light-exposed by a stepper. A photoresist film coated the substrate is exposed to light using identical or different masks per region. After the exposure, the photoresist film is wholly developed to form a photoresist pattern, and the underlying thin films are etched through the photoresist pattern to form thin film patterns. Such thin film patterns are repeated to form the TFT array substrate.

FIG. 2is a schematic view outlining the TFT array substrate shown inFIG. 1at one panel region where the display area is indicated by the long and short dashed line.

As shown inFIG. 2, a plurality of TFTs3, pixel electrodes82, gate lines22and data lines62electrically connected to the TFTs3are provided at the display area. Gate pads24placed at the end portions of the gate lines22, and data pads64at the end portions of the data lines62are provided at the peripheral area. A gate line shorting bar4and a data line shorting bar5are further provided at the peripheral area to equipotentially interconnect the gate lines22and the data lines62. The neighboring gate and data line shorting bars4and5are electrically connected to each other via a shorting bar connection member6. Completing the device fabrication, the shorting bars4and5are cut away along the dotted line2. Contact windows7interconnect the shorting bar connection member6and the neighboring shorting bars4and5.

FIG. 3is an amplified view of the TFT array substrate shown inFIG. 2at one pixel area, andFIGS. 4 and 5are cross sectional view taken along the IV-IV′ and V-V′ lines, respectively.

First, a gate line assembly is formed on the insulating substrate10. The gate line assembly includes gate lines22proceeding in the horizontal direction, gate electrodes26branched from the gate lines22, and gate pads24connected to end portions of the gate lines22to receive scanning signals from the outside and transmit them to the gate lines22.

The gate line assembly may be formed with a single, double or triple layered structure. When the gate line assembly is formed with a double or triple layered structure, one layer is preferably formed of a low resistance material and the other layer of a material having a good contact characteristic.

In this preferred embodiment, a gate line assembly with a double layered structure will be introduced. That is, the gate line assembly includes lower layers221,241and261, and upper layers222,242and262. The lower layers221to261are formed with a metallic material such as Cr, Mo, or Mo alloy that exhibits a good contact characteristic with respect to indium tin oxide (ITO) or indium zinc oxide (IZO). In contrast, the upper layers222to262are formed with a low resistance metallic material such as Al or Al alloy.

The gate line assembly is overlaid sequentially with a gate insulating layer30, semiconductor patterns42and48, and ohmic contact patterns55,56and58. The gate insulating layer30is formed with silicon nitride (SiNx). The semiconductor patterns42and48are formed of hydrogenated amorphous silicon. The ohmic contact patterns55,56and58are formed with amorphous silicon doped with n-type impurities such as phosphorus (P).

A data line assembly is formed on the ohmic contact patterns55,56and58. The data line assembly includes data lines62proceeding in the vertical direction, data pads64connected to end portions of the data lines62to receive picture signals from the outside, and source electrodes65branched from the data lines62. The data line assembly further includes drain electrodes66for the TFTs, and conductive patterns68for the storage capacitors. The drain electrode66is positioned opposite to the source electrode65with respect to the gate electrode26and separated from the source electrode65. The conductive pattern68is positioned above the gate line22while overlapping the same. The conductive pattern68is connected to a pixel electrode82to form a storage capacitor. However, if the pixel electrode82and the gate line22can generate sufficient storage capacity, the conductive pattern68may be omitted.

In the following description, it is assumed that the conductive pattern68for the storage capacitor is present.

The data line assembly may have a single, double or triple layered structure. In this preferred embodiment, the double, layered structure is used for the data line assembly. That is, the data line assembly includes lower layers621,641,651,661and681, and upper layers622,642,652and662. The lower layers621to681are formed of a metallic material such as Cr, Mo or Mo alloy that exhibits a good contact characteristic with respect to ITO or IZO. The upper layers622to662are formed of a low resistance metallic material such as Al or Al alloy. As shown inFIG. 5, among the components of the data line assembly, only the conductive pattern68has a single layered structure with the lower layer681.

The ohmic contact patterns55,56and58reduce the contact resistance between the semiconductor patterns42and48and the data line assembly, and have the same shape as that of the data line assembly.

The semiconductor patterns42and48have a shape similar to that of the data line assembly and the underlying ohmic contact patterns55,56and58. Specifically, the semiconductor pattern48for the storage capacitor has the same shape as that of the conductive pattern68and the underlying ohmic contact pattern58, while the shape of the semiconductor pattern42for the TFT differs from that of the data line assembly and the underlying ohmic contact patterns55and56. That is, the source electrode65is separated from the drain electrode66at the channel region of the TFT, and the ohmic contact pattern55under the source electrode65is also separated from the ohmic contact pattern56under the drain electrode66. In contrast, the semiconductor pattern42continuously proceeds at the channel region of the TFT. The semiconductor layer extends to the peripheral portion of the substrate10while covering the latter.

A passivation layer70covers the data line62, the data pad64, the source electrode65, the drain electrode66, the semiconductor pattern42, and the overlapping portions between the gate line22and the data line62.

Contact windows71and73are formed at the passivation layer70while exposing the drain electrode66and the data pad64. The contact window71exposing the drain electrode66may be extended toward the pixel area such that it can expose the borderline of the drain electrode66completely. The Al-based upper layers642and662of the data pad64and the drain electrode66are removed such that the Cr-based lower layers641and661thereof are exposed through the contact windows71and73. Another contact window72is formed at the passivation layer70while passing through the semiconductor pattern42and the gate insulating layer30to expose the gate pad24to the outside. The upper layer242of the gate pad24is removed such that the lower layer241thereof is exposed through the contact window72.

The passivation layer70may be formed of an organic insulating material such as silicon nitride and acryl-based materials. The passivation layer70protects the channel portion of the semiconductor pattern42between the source and drain electrodes65and66.

The aforementioned pixel electrode82is formed on the gate insulating layer30at the pixel area enclosed by the neighboring gate and data lines22and62. The pixel electrode82is electro-physically connected to the under-layer661of the drain electrode66through the contact window71such that it receives picture signals from the TFT while making the required electrical field in association with a common electrode. The pixel electrode82is formed of a transparent conductive material such as ITO or IZO. The pixel electrode82is extended over the conductive pattern68, and electro-physically connected to the latter such that it serves as a storage capacitor together with the conductive pattern68and the gate line22.

In the meantime, a supplemental gate pad84and a supplemental data pad86are formed on the gate pad24and the data pad64, respectively. The supplemental gate and data pads84and86are formed together with the pixel electrode82with the same material, and contact the Cr-based lower layers241and641of the gate and data pads24and64, respectively. The supplemental gate and date pads84and86strengthen the adhesion between the gate24and the data pad64and the external circuit devices and protect them. However they may be dispensed with.

The pixel electrode82, the supplemental gate and data pads84and86directly contact the Cr- or Mo-based lower layers661,841and861of the drain electrode66, and the gate and data pads24and64, which results in stable and good contacts between them.

In a reflection-type liquid crystal display, an opaque conductive material may be used for the pixel electrode82instead of ITO or IZO.

A method for fabricating the TFT array substrate according to the first preferred embodiment will be now explained with reference toFIGS. 3to5andFIGS. 6Ato17B.

As shown inFIGS. 6Ato6C, a first metal gate line layer of chrome, molybdenum or molybdenum alloy is deposited onto a substrate10to a thickness of 500-1,500 Å. A second metal gate line layer of aluminum or aluminum alloy is then deposited onto the first gate line layer to a thickness of 1,000-4,000 Å. The first and second metal gate line layers are wet or dry-etched through a first mask so that a double-layered gate line assembly is formed at the substrate10. The gate line assembly includes a gate line22with lower layer221and upper layer222, a gate pad24with lower layers241and upper layer242, and a gate electrode26with lower layer261and upper layer262.

Thereafter, as shown inFIGS. 7Ato7C, a gate insulating layer30having a thickness of 1,500-5,000 Å, a semiconductor layer40having a thickness of 500-1,500 Å, and an ohmic contact layer50having a thickness of 300-600 Å are sequentially deposited onto the substrate10along with the gate line assembly through chemical vapor deposition. The gate insulating layer30is formed of silicon nitride, the semiconductor layer40of amorphous silicon (a-Si), and the ohmic contact layer50of doped amorphous silicon (n+a-Si).

A first metal data line layer of chrome, molybdenum or molybdenum alloy is then deposited onto the ohmic contact layer50to a thickness of 500-1,500 Å. A second metal data line layer of aluminum or aluminum alloy is deposited onto the first data line layer to a thickness of 500-4,000 Å. The first and second data line layers are etched through a second mask together with the underlying ohmic contact layer50to form a double-layered data line assembly. The data line assembly includes a data line62with lower layer621and upper layer622, a data pad64with lower layer641and upper layer642, a source electrode65with lower layer651and upper layer652, a drain electrode66with lower layer661and upper layer662, and a conductive pattern68with lower layer681and upper layer682. At this time, the ohmic contact layer50is also etched to form a first contact pattern55for the data line62, the data pad64and the source electrode65, a second contact pattern56for the drain electrode66, and a third contact pattern58for the conductive pattern68. The conductive pattern68with the third contact pattern58may be omitted.

Thereafter, as shown inFIGS. 8Ato8C, a passivation layer70of silicon nitride is deposited onto the substrate10through chemical vapor deposition to a thickness of 3,000 Å. The passivation layer70is then etched through a third mask together with the underlying semiconductor layer40and gate insulating layer30. As a result, the passivation layer70and the upper layer662are removed from the drain electrode66to form a first contact window71. The passivation layer70, the semiconductor layer40, the gate insulating layer30and the upper layer242are removed from the gate pad24to form a second contact window72. The passivation layer70and the upper layer642are removed from the data pad64to form a third contact window73. The upper layer682is removed from the conductive pattern68. Furthermore, the passivation layer70and the semiconductor layer40at the pixel area between the neighboring data lines62are removed to form the channel region only at the required portion.

The etching process using the third mask will be now described in detail.

A photoresist film PR having a thickness of 5,000-30,000 Å is coated onto the passivation layer70, and exposed to light through the third mask. As shown inFIGS. 9A and 9B, the light exposure at the display area D is different from the light exposure at the peripheral area P. That is, the exposed portion C of the photoresist film PR at the display area D reacts to the light such that the molecules thereof are partially resolved to a predetermined depth from the surface while leaving the molecules thereunder unresolved. In contrast, the exposed portion B of the photoresist film PR at the peripheral area P reacts to the light such that the molecules thereof are completely resolved to the bottom.

In order to perform such a differential light exposure, the light transmissivity of the third mask corresponding to the display area D and the peripheral area P of the photoresist film PR should be controlled appropriately. Three types of techniques will be here introduced.

FIGS. 10Ato12illustrate possible structures of the third mask for etching the passivation layer70along with the underlying layers.

First, separate masks can be used for the third mask to perform the masking operation with respect to the display area D and the peripheral area P of the photoresist film PR, respectively.

As shown inFIGS. 10A and 10B, a mask300for the display area D and a mask400for the peripheral area P are formed with substrates310and410, chrome-based opaque films320and420formed on the substrates310and410, and semitransparent pellicles330and430covering the substrates310and410with the opaque films320and420. It is preferably that the light transmissivity of the opaque films320and420be 3% or less, the light transmissivity of the pellicle430of the mask400for the peripheral area P to be 90% or more, and the pellicle330of the mask300for the display area D to be 20-40% that is in the range of 20-60% of the light transmissivity of the pellicle430for the peripheral area P.

Meanwhile, patterns of slit or lattice with an opening width of about 2.5 μm that is smaller than the resolution capability of the light source for exposure may be formed as a replacement for the semitransparent pellicle330for the display area D.

Alternatively, as shown inFIGS. 11A and 11B, a chrome-based thin film350with a thickness of 100-300 Å covers the entire surface of the mask300for the display area D while being positioned under the opaque film320, whereas such a chrome-based thin film is absent at the mask400for the peripheral area P. In this case, the pellicle340of the mask300for the display area D may have the same light transmissivity as that of the pellicle430of the mask400for the peripheral area P.

Of course, the above two techniques may be used together in a suitable application.

The above two types of masks can be applied for use in partitioned exposure with a stepper, and separately perform the masking operation with respect to the display area D and the peripheral area P. The thickness of the target film can be also controlled by making the light exposure period different depending on the display area D and the peripheral area P.

On the other hand, only one mask can be used for the light exposure with respect to the display and the peripheral areas D and P at the same time while controlling the amount of light applied thereto.FIG. 12illustrates the structure of such a mask500.

As shown inFIG. 12, a light transmissivity control film550is formed on a substrate510for the mask500, and an opaque film520is formed on the light transmissivity control film550. Whereas the light transmissivity control film550for the display area D is formed on the entire surface of the substrate510, the light transmissivity control film550for the peripheral area P is formed only under the opaque film520. That is, two or more patterns with different thickness are formed on the substrate510. Of course, such a light transmissivity control film may be formed on the entire surface of the substrate510both at the display and the peripheral areas D and P. In this case, the light transmissivity of the light transmissivity control film550for the peripheral area P should be established to be higher than that of the light transmissivity control film550for the display area D.

In the fabrication process of the mask500, a light transmissivity control film550, and an opaque film520with an etching ratio different from that of the light transmissivity control film550are sequentially deposited onto the substrate510. A photoresist film is coated on the entire surface of the substrate510with the light transmissivity film550and the opaque film520, exposed to light, and developed to form a photoresist pattern. The opaque layer520is then etched by using the photoresist pattern for the mask. The photoresist pattern is then removed, and a second photoresist pattern is formed while exposing the portions of the light transmissivity film550corresponding to the contact windows at the peripheral area P to the outside. The light transmissivity film550is then etched by using the second photoresist pattern for a mask. A semitransparent pellicle530is finally formed on the substrate510with the patterns of the light transmissivity film550and the opaque layer520.

Meanwhile, the portions of the photoresist film PR with the underlying metal gate or data line assembly may be applied with a larger amount of light due to the light reflected against the metallic component. Therefore, in order to prevent such a problem, a new layer for intercepting the reflected light, for example a colored photoresist film PR, may be introduced.

As shown inFIGS. 13A and 13B, when the photoresist film PR exposed through the third mask is developed, a photoresist pattern PR results. That is, some portions B of the photoresist film at the peripheral area P over the gate and data pads24and64are completely removed, and some portions C of the photoresist film at the display area D over the drain electrode66and the pixel area are partially removed with a resulting small thickness. The remaining portions of the photoresist film at the display and the peripheral areas D and P are left with a relatively large thickness. In this process, as shown inFIG. 13B, the photoresist film having a small thickness may be formed over the conductive pattern68.

The thickness of the thin photoresist film is preferably in the range of 350-10,000 Å that is one fourth to one seventh of the initial thickness, and more preferably in the range of 1,000-6,000 Å. For instance, the initial thickness of the photoresist film may be established to be 25,000-30,000 Å, and the thickness of the thin photoresist film to be 3,000-5,000 Å by controlling the light transmissivity of the mask at the display area D to 30%. However, since the resulting thickness is determined in accordance with the processing conditions, the pellicle of the mask, the thickness of the chrome-based film, and the light transmissivity of the light transmissivity control film, the exposing time should be controlled depending upon such processing conditions.

Alternatively, such a thin photoresist film may be formed by using a common processing technique including the steps of exposing and developing the photoresist film, and then performing the following operation, whereby the photoresist pattern PR and the underlying passivation layer70, semiconductor layer40and gate insulating layer30are etched by using a dry etching technique, passivation

In the etching process, the A portion of the photoresist pattern PR should be partially left, the passivation layer70, semiconductor layer40and gate insulating layer30positioned under the B portion of the photoresist pattern PR should be removed, and the passivation layer70and semiconductor layer40under the C portion of the photoresist pattern PR should be removed, while leaving the gate insulating layer30.

For this purpose, a dry etching technique that is capable of etching the photoresist pattern PR and the underlying layers at the same time may be used.

Alternatively, in order to prevent only partial removal of the semiconductor layer40over the gate insulating layer30due to the non-uniform thickness of the resulting photoresist film, the photoresist pattern PR and the underlying layers can be etched through several etching steps as described below.

As shown inFIGS. 14A and 14B, the passivation layer70at the B portion of the photoresist film over the data pad64is dry-etched while exposing the data pad64. The passivation layer and the underlying semiconductor layer40and gate insulating layer30at the B portion of the photoresist film over the gate pad24is dry-etched while partially leaving the gate insulating layer30. At this time, the gate insulating layer30over the gate pad24may be completely removed while exposing the underlying gate pad24. SF6+N2or SF6+HCL can be used for the dry etching, and the photoresist film PR at the display area D may be partially removed during the dry etching. Therefore, the consumption of the photoresist film PR should be controlled such that the passivation layer70at the display area D is not exposed to the outside. In this process, as shown inFIG. 14B, the thickness of the photoresist film PR over the conductive pattern68becomes reduced by as much as that of the photoresist film PR at the display area D.

Thereafter, as shown inFIGS. 15A and 15B, the C portion of the photoresist film PR over the passivation layer70are removed through oxygen-based ashing. At this time, considering that the C portion of the photoresist film PR may be left with a non-uniform thickness, the ashing should be sufficiently performed by using N6+O2or Ar+O2. In this way, even though the C portion of the photoresist film is non-uniformly formed with a small thickness, it can be completely removed.

Thereafter, as shown inFIGS. 16A and 16B, the passivation layer70over the drain electrode66, the pixel area and the conductive pattern68as well as the gate insulating layer30over the gate pad24are removed by using the photoresist pattern PR for a mask. In order to make etching conditions suitable for the semiconductor layer40and the passivation layer70, the etching gas preferably contains large amount of O2or CF4. SF6+N2, SF6+O2, CF4+O2or CF4+CHF3+O2are preferably used for the dry etching.

As shown inFIGS. 17A and 17B, the semiconductor layer40between the neighboring data lines62is removed by etching, to complete the semiconductor patterns42and48. Cl2+O2or SF6+HCl+O2+Are is preferably used for etching the semiconductor layer40.

Thereafter, as shown inFIGS. 4 and 5, the upper layer242of the gate pad24, the upper layer662of the drain electrode66, the upper layer642of the data pad64, and the upper layer682of the conductive pattern68exposed to the outside are removed through dry-etching or wet-etching, and the remaining photoresist film PR is also removed. An ITO or IZO film is deposited onto the substrate10, and etched through a fourth mask. Consequently, a pixel electrode82, a supplemental gate pad84and a supplemental data pad86are formed while contacting the lower layer661of the drain electrode66, the lower layer241of the gate pad24, and the lower layer641of the data pad64, respectively.

As described above, in this preferred embodiment, the semiconductor patterns42and48together with the contact windows71to73is formed through one masking process and the desired TFT array substrate can be fabricated using only four masks. Furthermore, multiple etching can be uniformly performed on a large target area with different depth. In addition, the data or gate line assembly may have a double-layered structure with a low-resistance aluminum-based layer, eliminating poor contact characteristics of an aluminum-based layer at the pad portions.

In the meantime, when the upper layer662of the drain electrode66, and the upper layer642of the data pad64are etched, over-etching is liable to occur inside of the edge of the passivation layer70. In this case, the ITO or IZO film pattern for the pixel electrode82at the over-etched portion may be broken.

Second Preferred Embodiment

FIGS. 18to23illustrate a method for fabricating a TFT array substrate according to a second preferred embodiment of the present invention. In this preferred embodiment, the processing steps are the same as those related to the first preferred embodiment up to the step of depositing the passivation layer70onto the substrate10.

As shown inFIG. 18, a photoresist film PR is coated onto the passivation layer70. The photoresist film PR is exposed to light through a third mask, and developed to form a photoresist pattern. That is, the portion B of the photoresist film PR over the gate pad24, data pad64and drain electrode66is completely removed. The portion C of the photoresist film PR adjacent to the portion B over the drain electrode66and the data pad64and positioning at the pixel area is partially removed such that it has a small thickness. The remaining portion A of the photoresist film PR is left without being consumed.

Thereafter, as shown inFIG. 19, the passivation layer70, the semiconductor layer40and the gate insulating layer30at the B portion of the photoresist film PR are dry-etched such that the gate pad24, the drain electrode66and the data pad64are exposed to the outside.

In this process, the A portion of the photoresist film PR may be partially removed.

Then, as shown inFIG. 20, the upper layer242of the gate pad24, the upper layer662of the drain electrode66and the upper layer642of the data pad64are dry or wet-etched such that the lower layers241,661and641are exposed. The thin photoresist film PR over the drain electrode66, the pixel area and the data pad64are removed through oxygen-based ashing to expose the underlying passivation layer70.

As shown inFIG. 21, the exposed passivation layer70over the drain electrode66and the data pad64is dry-etched such that the upper layer662of the drain electrode66and the upper layer642of the data pad64are exposed to the outside through the contact windows71and73. At this time, the passivation layer70at the pixel area and the underlying semiconductor layer40are also removed to complete semiconductor patterns42and48.

As shown inFIG. 22, the remaining photoresist film PR is removed to complete the contact windows71,72and73.

As shown inFIG. 23, an ITO or IZO film is deposited onto the entire surface of the substrate10, and etched through a fourth mask. As a result, a subsidiary gate pad84, a pixel electrode82and a subsidiary data pad86are formed while contacting the lower layer241of the gate pad24, the lower layer661of the drain electrode66and the lower layer641of the data pad64, respectively.

As described above, in this preferred embodiment, the semiconductor patterns42and48together with the contact windows71to73is formed through one masking process so that the desired TFT array substrate can be fabricated using only four mask. Furthermore, multiple etching can be uniformly performed on large target areas with different depth. In addition, the data or gate line assembly may have a double-layered structure with a low-resistance aluminum-based layer, not showing poor contact characteristics of an aluminum-based layer at the pad portions.

Furthermore, removing the passivation layer70after removing the upper layer662of the drain electrode66and the upper layer642of the data pad64eliminates the problem of over-etching the upper layers662and642. Therefore, the pixel electrode82and the subsidiary data pad86at the contact windows71and73can be prevented from breaking. In addition, the above structure can mitigate the height differences of the components at the contact windows71to73.

Third Preferred Embodiment

FIGS. 24to29illustrate the steps of fabricating a TFT array substrate according to a third preferred embodiment of the present invention where a photosensitive organic layer is used for the passivation layer. In this preferred embodiment, the processing steps are similar to those related to the first preferred embodiment prior to the step of depositing a passivation layer onto the substrate10.

As shown inFIG. 24, a photosensitive passivation layer80of a photosensitive organic material is deposited onto the substrate10to a thickness of 3,000 Å. The photosensitive passivation layer80is then exposed to light through a third mask, and developed to form a photoresist pattern. That is, the portion B of the photosensitive passivation layer80over the gate pad24, the data pad64and the drain electrode66is completely removed. The portion C of the photosensitive passivation layer80adjacent to the portion B over the drain electrode66and the data pad64and positioned at the pixel area is partially removed such that it has a small thickness. The remaining portion A of the photosensitive passivation layer80is left intact.

Thereafter, as shown inFIG. 25, passivation the semiconductor layer40and the gate insulating layer30are dry-etched through the removed portion B of the photosensitive passivation layer80exposing the gate pad24, the drain electrode66and the data pad64.

Then, as shown inFIG. 26, the upper layer242of the gate pad24, the upper layer662of the drain electrode66and the upper layer642of the data pad64are dry or wet-etched exposing the lower layers241,661and641.

As shown inFIG. 27, the thin photosensitive passivation layer80remaining over the drain electrode66and the data pad64is removed through oxygen-based ashing to expose the upper layer662of the drain electrode66and the upper layer642of the data pad64to the outside through the contact windows71and73. At this time, the thin photosensitive passivation layer80remaining at the pixel area is also removed to expose the underlying semiconductor layer40.

As shown inFIG. 28, the exposed semiconductor layer40is dry-etched to complete semiconductor patterns42and48.

As shown inFIG. 29, an ITO or IZO film is deposited onto the entire surface of the substrate10, and etched through a fourth mask. As a result, a supplemental gate pad84, a pixel electrode82and a subsidiary data pad86are completed while contacting the lower layer241of the gate pad24, the lower layer661of the drain electrode66and the lower layer641of the data pad64, respectively.

This preferred embodiment, in addition to the advantages related to the previous preferred embodiments, simplifies the processing steps because the separate steps of processing a photoresist film after the formation of the passivation layer are not necessary.

Fourth Preferred Embodiment

FIGS. 30Ato37B illustrate the steps of fabricating a TFT array substrate according to a fourth preferred embodiment of the present invention. In this preferred embodiment, other components and structures of the TFT array substrate are similar to those related to the first preferred embodiment except that a single layered structure is used for the gate and data line assemblies, the conductive pattern68for the storage capacitor is eliminated, and an opening portion31is formed between the pixel electrode82and the data line62while exposing the substrate10. The gate and data line assemblies having a single layered structure of a metallic or conductive material such as Al, Al alloy, Mo, Mo—W alloy, Cr, and Ta are formed to a thickness of 1,000-4,000 Å. The opening portion31is to prevent a short circuit between the pixel electrode82and the data line62occurring when the semiconductor pattern42is over-extended toward the periphery of the data line62, and connected to the data line62.

In the method of fabricating the TFT array substrate according to the fourth preferred embodiment, the processing steps are similar as those related to the first preferred embodiment up to the step of depositing the passivation layer onto the substrate except that the gate and data line assemblies are formed with a single layered structure.

As shown inFIG. 30B, a photoresist film PR is coated onto the passivation layer70. The photoresist film PR is exposed to light through a third mask. The light exposure to the photoresist film PR at the display area D is mainly different from that at the peripheral area P. That is, the exposed portions C and E of the photoresist film PR at the display area D over the drain electrode66and the pixel area react to light such that the molecules thereof are partially resolved to a predetermined depth from the surface while leaving the molecules thereunder intact. In contrast, the exposed portion B of the photoresist film PR at the peripheral area P over the gate pad24and the data pad64reacts to the light such that the molecules thereof are completely resolved to the bottom.

The exposed portion B of the photoresist film PR at the display area D between the pixel area and the data line62also reacts to the light such that the molecules thereof are completely resolved to the bottom.

In order to achieve such different light exposures, the light transmission of the third mask at the display area D and the peripheral area P should be controlled appropriately.

As shown inFIG. 31, the third mask for the above etching is formed with a transparent substrate610. The transparent substrate610is sequentially overlaid with a light transmission control film620and an opaque film630. It is preferable that the opaque film630has a light transmissivity of 3%, the light transmission control film620has a light transmissivity of 20-40%, and the transparent substrate610has a light transmissivity of 90% or more. The light transmission control film620and the opaque film630may be formed with materials having different light transmissivities, or with the same material while bearing a thickness different from each other. For instance, in the latter case, a chrome-based film having a thickness of 100-300 Å may be used for the light transmission control film620, and a chrome-based film sufficiently thicker than the light transmission control film620for the opaque film630.

According to the of light transmissivity, the mask can be divided into A, B, C and E portions corresponding to those portions of the photoresist film PR, and an additional F portion. The A portion has a lowest light transmissivity, and the B portion has a highest light transmissivity. The C portion has a light transmissivity between A and B. The E portion has a light transmissivity between B and C. The F portion has a light transmissivity between A and C. The substrate610, the light transmission control film620and the opaque film630are all present at the A portion. Only the substrate610is present at the B portion. The substrate610and the light transmission control film620are present at the C portion. The substrate610and the light transmission control film620are present at the E portion, but the light transmission control film620at the E portion has a plurality of slit patterns. The substrate610, the light transmission control film620and the opaque film630are all present at the F portion, but the opaque film630at the F portion has a plurality of slit patterns.

The slit patterns formed at the light transmission control film620and the opaque film630for the E and F portions have a width narrower than the resolution capability of the light source for the exposure such that the incident light diffracts and partially passes through the slit. Any patterns capable of inducing diffraction of the light may replace the slit patterns. For instance, mosaic patterns may be used for such purpose.

The reason for forming the slit or mosaic patterns at the required portions is to reduce the amount of light applied thereto. That is, when any metal component is present under the photoresist film to be exposed to light, the portion of the photoresist film under the metal component is applied with an increased amount of light due to the light reflected against the metal component so that the relevant portion of the photoresist film has a relatively small thickness compared to other portions. Furthermore, when the photoresist film is coated onto the protruded portion with the metal component, it is planarized to be placed on a plane with the photoresist film at other portions without the metal component so that the portion of the photoresist film over the metal component has a relatively small thickness compared to other portions. For these reasons, slit or mosaic patterns are formed at the mask portions corresponding to those of the photoresist film with the underlying metal layers to reduce the amount of light applied thereto. Alternatively, a colored photoresist film may be used for that purpose.

As shown inFIGS. 32A and 32B, when the photoresist film PR exposed through the third mask is developed, a photoresist pattern PR is formed. That is, the B portion of the photoresist film over the gate and data pads24and64is completely removed, whereas the C portion of the photoresist film over the drain electrode66and the pixel area is partially removed leaving a relatively small thickness. The B portion of the photoresist film between the pixel area and the data line62is completely removed. The remaining A portion of the photoresist film is left with a relatively large thickness.

Thereafter, as shown inFIGS. 33A and 33B, the passivation layer70at the B portion over the data pad64is dry-etched while exposing the data pad64, and the passivation layer70and the underlying semiconductor layer40and gate insulating layer30at the B portion over the gate pad24are dry-etched while partially leaving the gate insulating layer30. At this time, the gate insulating layer30over the gate pad24may be completely removed while exposing the underlying gate pad24. The passivation layer70and the gate insulating layer30at the B portion between the pixel area and the data line62are removed while partially leaving the gate insulating layer30.

Thereafter, as shown inFIGS. 34A and 34B, the C portion of the photoresist film PR over the passivation layer70are removed through oxygen-based ashing.

Then, as shown inFIGS. 35A and 35B, the passivation layer70over the drain electrode66and the pixel area, and the gate insulating layer30remaining over the gate pad24is removed by using the photoresist pattern PR for a mask. At this time, the gate insulating layer30remaining between the pixel area and the data line62is also removed.

As shown inFIGS. 36A and 36B, the semiconductor layer40at the pixel area between the neighboring data lines62is removed by etching, thereby completing the semiconductor patterns42.

Thereafter, as shown inFIGS. 37Ato37B, the remaining photoresist film PR is removed. An ITO or IZO film is deposited onto the substrate10, and etched through a fourth mask. Consequently, a pixel electrode82, a supplemental gate pad84and a supplemental data pad86are formed while contacting the drain electrode66, the gate pad24, and the data pad64, respectively. Furthermore, the section31is opened between the pixel electrode82and the data line62to electrically separate them.

As is in the third preferred embodiment, the passivation layer70may be replaced by a photosensitive organic layer. In this case, the separate steps of processing a photoresist film may be eliminated.

This preferred embodiment, in addition to the advantages related to the previous preferred embodiments, can minutely divide the light transmissivity of the third mask while simplifying the relevant processing steps. Furthermore, the possible short circuit between the pixel electrode82and the data line62can be prevented by forming the opening portion31.

Fifth Preferred Embodiment

FIGS. 38Ato40illustrate the steps of fabricating a TFT array substrate according to a fifth preferred embodiment of the present invention. In this preferred embodiment, other components and structures of the TFT array substrate are similar to those related to the first preferred embodiment except that a single layered structure is used for the gate and data line assemblies, the conductive pattern68for the storage capacitor is eliminated, and a black matrix90and a color filter100are newly introduced.

In the method of fabricating the TFT array substrate according to the fifth preferred embodiment, the processing steps are similar to those related to the first preferred embodiment prior to the step of depositing the ITO or IZO film to form the pixel electrode82.

As shown inFIG. 38B, after the semiconductor layer40is etched to form a semiconductor pattern and the remaining photoresist film PR is removed, an organic black matrix layer is deposited onto the substrate10, and etched through a fourth mask to form a black matrix pattern90. Alternatively, a black photoresist film may be used to form such a black matrix pattern.

Then, as shown inFIG. 39, a color filter100of red, green and blue is formed at the pixel area between the neighboring data lines62. The color filter100formed through screen printing, or photolithography using fifth to seventh masks.

Finally, as shown inFIG. 40, an ITO film having a thickness of 400-500 Å is deposited onto the substrate10, and etched through a fifth or eighth mask. Consequently, a pixel electrode82, a supplemental gate pad84, and a supplemental data pad86are completed.

In the resulting TFT array substrate, the black matrix90formed at the display area is to prevent light leakage due to the electric field present at the periphery of the pixel electrode82. The portion of the black matrix90over the gate line22may be removed. The black matrix90has a narrow contact window for exposing the drain electrode66that is positioned at the center of the contact window71passing through the passivation layer70.

The color filter100formed on the gate insulating layer30between the neighboring data lines62is alternated with the colors of red, green and blue. Such a color filter may be formed per one pixel area or per one longitudinal area defined by the neighboring data lines62. The color filter100may be extended over the contact window71. In this case, the color filter100should also have a separate contact window for interconnecting the drain electrode66and the pixel electrode82. Such a contact window for the color filter100should have a size of at least 4 μ×4 μ because the color filter100is usually formed by using a large size aligner-based light exposure.

The above-mentioned structure can simplify the steps of fabricating the TFT array substrate. Furthermore, the black matrix90and the color filter100formed on the TFT array substrate, the marginal error when combining the TFT array substrate and the color filter substrate need not be considered, and can improve the opening ratio of the device.

Sixth Preferred Embodiment

FIGS. 41A and 41Billustrate the structure of a TFT array substrate according to a sixth preferred embodiment of the present invention. In this preferred embodiment, other components and structures of the TFT array substrate are similar to those related to the fifth preferred embodiment except that the black matrix90is absent. That is, among the processing steps for fabricating the TFT array substrate, the step of forming a black matrix pattern90is eliminated.

In the above structure, the opening ratio of the device is reduced compared to that related to the fifth preferred embodiment, but the black matrix to be formed with a common electrode at the opposite substrate can reduce the resistance of the common electrode.

Seventh Preferred Embodiment

FIGS. 42Ato45illustrate the steps of fabricating a TFT array substrate according to a seventh preferred embodiment of the present invention. In this preferred embodiment, other components and structures of the TFT array substrate are the similar to those related to the sixth preferred embodiment except that the passivation layer70has a new structure. For such a purpose, the passivation layer70is formed after the formation of the semiconductor pattern.

As shown inFIG. 42B, a gate line assembly22,24and26is first formed at the substrate10by using a first mask. A gate insulating layer, a semiconductor layer, an ohmic contact layer, and a metal data line layer are then sequentially deposited onto the substrate10. The metal data line layer, the ohmic contact layer and the semiconductor layer are etched through a second mask to form the desired patterns. The semiconductor pattern40, the ohmic contact pattern50, and the data line assemblies62to66have similar shapes except that the semiconductor pattern40is present at the channel region between the source and drain electrode65and66.

A single mask200is used for the second mask. The mask200has a transparent substrate210overlaid with a light transmission control film220and an opaque film230. As shown inFIG. 43, the portion of the mask corresponding to the data line assemblies62to66is provided with the light transmission control film220and the opaque film230, and the light transmissivity thereof is set to be 3% or less. The portion of the mask corresponding to the semiconductor pattern40between the source and drain electrodes65and66is provided with the light transmission control film220, and the light transmissivity thereof is established to be 20 to 40%. The remaining portion of the mask is provided only with the transparent substrate210, and the light transmissivity thereof is established to be 90% or more.

In the above etching process using the second mask, a photoresist film PR is first coated onto the substrate10, and exposed to light through the second mask. The photoresist film is then developed to thereby form a photoresist pattern.

Thereafter, the metal data line layer exposed through the photoresist pattern is etched while exposing the underlying ohmic contact layer. In this process, either a wet-etching technique or a dry-etching technique can be used, preferably under the condition that only the metal data line layer is etched while leaving the photoresist pattern. However, in the case of the dry etching, since it is difficult to make such a condition, the photoresist pattern may be allowed to be etched altogether.

When the metal data line layer is formed of Cr, wet etching is preferably used, with a solution of CeNHO3. When the metal data line layer is formed of Mo or MoW, dry etching is preferably used, with a mixture of CF4and HCl or CF4and O2.

As a result, the patterns62to66of the data line assembly are formed while exposing the underlying ohmic contact layer, except that the source and drain electrode65and66are not yet separated from each other.

Thereafter, the exposed ohmic contact layer and the underlying semiconductor layer are removed through dry etching. Then, the photoresist film remaining over the channel portion of the metal data line layer between the source and drain electrode portions is removed.

The channel portion of the metal data line layer and the underlying ohmic contact layer are removed through etching. At this time, both the metal data line layer and the ohmic contact layer may be dry etched. Alternatively, dry etching the ohmic contact layer is dry etched and the metal data line layer is wet etched. In the former case, the etching is preferably performed under the condition that the etching selection ratio with respect to the metal layer and the contact layer is high. The reason is that when the etching selection ratio is low, it becomes difficult to find the final etching point and the thickness of the semiconductor pattern to be left at the channel region cannot be controlled in an appropriate manner. In the latter case, the side portions of the metal layer being etched with the wet etching method are etched while leaving those portions of the contact layer being etched by the dry etching, rendering stepped portions. The mixture of CF4and O2is preferably used to form the semiconductor pattern40with a uniform thickness.

In this way, the source electrode65and the drain electrode66are separated from each other, completing the patterns62to66of the data line assembly and the underlying ohmic contact pattern50.

Thereafter, the photoresist film remaining over the data line assembly is removed.

As shown inFIG. 44, a passivation layer70is deposited onto the substrate10with the data line assembly, and etched through a third mask to form contact windows71to73. An organic black matrix layer is then deposited onto the substrate10, and etched through a fourth mask to form a black matrix pattern90.

Finally, as shown inFIG. 45, a color filter100as well as a pixel electrode82, a subsidiary gate pad84and a subsidiary data pad86are formed at the substrate10in the similar way as in the sixth preferred embodiment.

As is in the previous preferred embodiment, the above structure or technique can reduce the number of the processing steps, and enhance the opening ratio of the device.

Eighth Preferred Embodiment

FIGS. 46A and 46Billustrate the structure of a TFT array substrate according to an eighth preferred embodiment of the present invention. In this preferred embodiment, other components and structures of the TFT array substrate are the same as those related to the seventh preferred embodiment except that the passivation layer70is absent. The black matrix pattern90also serves the function of the passivation layer70. The black matrix pattern90is extended over the peripheral portion P. As the extension of the black matrix pattern99over the peripheral portion P may be realized also in the seventh preferred embodiment, only the step of processing the passivation layer70is skipped in this preferred embodiment. In this way, the number of processing steps can be reduced.

Ninth Preferred Embodiment

FIGS. 47A and 47Billustrate the structure of a TFT array substrate according to a ninth preferred embodiment of the present invention. In this preferred embodiment, other components and structures of the TFT array substrate are similar to those related to the fifth preferred embodiment except that the passivation layer70is absent, and the black matrix90serves the function of the passivation layer70. Therefore, the separate step of forming the passivation layer70is eliminated in this preferred embodiment.

The black matrix90is formed with a photosensitive material containing black pigments. In the etching process based on the third mask, the photosensitive matrix layer is itself exposed to light through the third mask without forming the photosensitive film PR, and developed to thereby form the black matrix pattern90. In the subsequent processing steps, the black matrix pattern90severs the function of the photoresist pattern PR.

In the above structure, the number of the processing steps can be reduced.

Tenth Preferred Embodiment

FIGS. 48A and 48Billustrate the structure of a TFT array substrate according to a tenth preferred embodiment of the present invention. In this preferred embodiment, other components and structures of the TFT array substrate are similar to those related to the ninth preferred embodiment except that the gate insulating layer30has a different pattern. That is, the portion of the gate insulating layer at the pixel area between the neighboring data lines is removed such that it has the same shape as that of the semiconductor pattern40. Therefore, the color filter100is positioned directly over the substrate10and the gate line22. The width of the removed portion of the gate insulating layer at the pixel area should be 1 μ or more. That is, the opening width of the semiconductor layer40should reach 1 μ or more. The opening prevents the current from leaking between the neighboring data lines62via the semiconductor layer40.

In the method of fabricating the TFT array substrate according to the tenth preferred embodiment, the processing steps are similar to those related to the ninth preferred embodiment except that a usual mask with only a transparent portion and an opaque portion is used for the third mask. That is, the transparent portion of the mask corresponds to the portion of the target film to be removed, while the opaque portion corresponds to the portion of the target film to remain.

When the photosensitive black matrix pattern90is formed by using the usual mask, and the underlying semiconductor layer and gate insulating layer are etched by using the photosensitive black matrix pattern90as a photoresist pattern PR, exposing the portions of the substrate10and the gate line21between the neighboring data lines62to the outside, and the contact windows71to73are also formed.

Thereafter, a color filter100as well as a pixel electrode82, a supplemental gate pad84and a supplemental data pad86are formed in the similar way as in the ninth preferred embodiment. The color filter100completely covers the exposed portion of the gate line22to insulate the gate line22from the pixel electrode82.

The above mentioned structure can reduce, the number of processing steps even with the usual mask having only transparent and opaque portions.

As described above, the TFT array substrate of the present invention can be fabricated with simplified processing steps while achieving good performance characteristics.