Integrated circuit including load standard cell and method of designing the same

To design an integrated circuit, input data defining an integrated circuit are received, and a plurality of load standard cells having different delay characteristics are provided in a standard cell library. Placement and routing are performed based on the input data and the standard cell library and output data defining the integrated circuit are generated based on a result of the placement and the routing. Design efficiency and performance of the integrated circuit are enhanced by designing the integrated circuit with delay matching and duty ratio adjustment using the load standard cell.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. Non-provisional application claims priority under 35 USC § 119 to Korean Patent Application No. 10-2017-0179484, filed on Dec. 26, 2017, in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated by reference in its entirety herein.

BACKGROUND

Example embodiments relate generally to semiconductor integrated circuits, and more particularly to an integrated circuit including a signal-load cell and a method of designing the integrated circuit.

Standard cells having fixed functions may be used in the design of integrated circuits. The standard cells have predetermined architectures and are stored in cell libraries. When designing integrated circuits, the standard cells are retrieved from the cell libraries and placed into desired locations on an integrated circuit layout. Routing is then performed to connect the standard cells with each other and with other cells. A standard cell has a predetermined (or set) architecture that may include a cell width, a cell height, a power rail width, positions and numbers of pin points, etc. Design efficiency of an integrated circuit may be determined according to configurations of standard cells.

SUMMARY

Some example embodiments may provide an integrated circuit having an efficient signal delay and a method of designing an integrated circuit.

According to some example embodiments, a method of designing an integrated circuit includes, receiving input data defining an integrated circuit, providing, in a standard cell library, a plurality of load standard cells having different delay characteristics, performing placement and routing based on the input data and the standard cell library, and generating output data defining the integrated circuit based on a result of the placement and the routing.

According to some example embodiments, an integrated circuit includes a logic standard cell including a delay node requiring a delay, and a load standard cell including a load node that is connected to the delay node to provide the required delay.

According to some example embodiments, an integrated circuit includes a first logic standard cell including a first delay node, a second logic standard cell including a second delay node, a first load standard cell including a first load node providing a first delay, the first load node being connected to the first delay node and a second load standard cell including a second load node providing a second delay different from the first delay, the second load node connected to the second delay node.

The integrated circuit and the method of designing the integrated circuit according to some example embodiments may enhance design efficiency and performance of the integrated circuit by designing the integrated circuit with delay matching and duty ratio adjustment using the load standard cell.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Various example embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some example embodiments are shown. In the drawings, like numerals refer to like elements throughout. The repeated descriptions may be omitted.

FIG. 1is a diagram illustrating a method of designing and fabricating an integrated circuit according to some example embodiments.

The method ofFIG. 1may include a method of designing a layout of the integrated circuit that is performed by a designing tool. In some example embodiments, the designing tool may include a programming software including a plurality of instructions executable by a processor, that is, software implemented in some form of hardware (e.g. processor, ASIC, etc.)

Referring toFIG. 1, input data defining the integrated circuit may be received (S100). For example, an integrated circuit may be defined by a plurality of cells and the integrated circuit may be designed using a cell library including information of the plurality of cells. Hereinafter, a cell may be a standard cell and a cell library may be a standard cell library.

In some example embodiments, the input data may be data generated from an abstract form with respect to behavior of the integrated circuit. For example, the input data may be defined in a register transfer level (RTL) through synthesis using the standard cell library. For example, the input data may be a bitstream and/or a netlist that is generated by synthesizing the integrated circuit defined by a hardware description language (HDL) such as VHSIC hardware description language (VHDL) or Verilog.

In some example embodiments, the input data may be data for defining the layout of the integrated circuit. For example, the input data may include geometric information for defining a structure implemented as a semiconductor material, a metal, and an insulator. A layout of the integrated circuit indicated by the input data may have a layout of the cells and conducting wires used to connect a cell to other cells, for example.

A plurality of load standard cells having different delay characteristics are provided in a standard cell library (S200). The plurality of load standard cells may be a portion of standard cells included in the standard cell library.

The term “standard cell” may refer to a unit of an integrated circuit in which a size of the layout meets a preset or specified rule. The standard cell may include an input pin and an output pin and may process a signal received through the input pin to output a signal through the output pin. For example, the standard cell may be a basic cell such as an AND logic gate, an OR logic gate, a NOR logic gate, or an inverter, a complex cell such as an OR/AND/INVERTER (OAI) or an AND/OR/INVERTER (AOI), and a storage element such as a master-slave flip flop or a latch. The term “load standard cell” may refer to a unit of an integrated circuit that includes or consists of a capacitor or a plurality of capacitors, each capacitor having a first node connected to, e.g., directly connected to, a standard cell, and having a second node connected to, e.g. directly connected to, a power supply.

The load standard cell may include only one input-output pin corresponding to a load node. According to some example embodiments, a plurality of capacitors having different capacitance values may be provided as the plurality of load standard cells having the different delay characteristics. Some example embodiments of the load standard cell will be described below with reference toFIGS. 12A through 16B.

The standard cell library may include information about a plurality of standard cells. For example, the standard cell library may include a name and a function of a standard cell, as well as timing information, power information, and layout information of the standard cell. The standard cell library may be stored in a storage device and the standard cell library may be provided by accessing the storage device.

Placement and routing are performed based on the input data and the standard cell library (S300) and output data defining the integrated circuit are provided based on a result of the placement and the routing (S400). The integrated circuit may be manufactured, e.g. fabricated, using one or more photomasks generated from the output data (S500).

In some example embodiments, when the received input data are data such as the bitstream or the netlist generated by synthesizing the integrated circuit, the output data may be the bitstream or the netlist. In other example embodiments, when the received input data are data defining the layout of the integrated circuit, for example, the data having a graphic data system II (GDSII) format, a format of the output data may also be data defining the layout of the integrated circuit.

As such, the method of designing the integrated circuit and the integrated circuit by the method according to some example embodiments may enhance design efficiency and performance of the integrated circuit by designing the integrated circuit with delay matching and duty ratio adjustment using the load standard cell.

FIG. 2is a block diagram illustrating a designing system of an integrated circuit according to some example embodiments.

Referring toFIG. 2, a designing system1000may include a storage medium1100, a designing module1400and a processor1500.

The storage medium1100(e.g., a storage device) may store a standard cell library SCLB1110. The standard cell library1110may be provided from the storage medium1100to the designing module1400. The standard cell library1110may include a plurality of standard cells. The plurality of standard cells may include a plurality of load standard cells having different delay characteristics. The standard cell may be a small, e.g., minimum, unit for designing a block, a device and/or a chip.

The storage medium1100may include any computer-readable storage medium used to provide commands and/or data to a computer as a computer-readable storage medium. For example, the computer-readable storage medium1100may include volatile memory such as random access memory (RAM), read only memory (ROM), etc. and nonvolatile memory such as flash memory, magnetoresistive RAM (MRAM), phase-change RAM (PRAM), resistive RAM (RRAM), etc. The computer-readable storage medium1100may be inserted into the computer, may be integrated in the computer, or may be coupled to the computer through a communication medium such as a network and/or a wireless link.

The designing module1400may include a placement module PLMD1200and a routing module RTMD1300.

Herein, the term “module” may indicate, but is not limited to, a software and/or hardware component, such as a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC), which performs certain tasks. A module may be configured to reside in a tangible, addressable storage medium and be configured to execute on one or more processors. For example, a module may include software components, class components, task components, processes, functions, attributes, procedures, subroutines, program code segments, drivers, firmware, micro codes, circuits, data, database, data structures, tables, arrays, parameters, etc. A module may be divided into a plurality of modules performing detailed functions.

The placement module1200may, using the processor1500, arrange standard cells based on input data DI defining the integrated circuit as well as the standard cell library1110. The routing module1300may perform signal routing with respect to cell placement provided from the placement module1200. If the routing is not successful, the placement module1200may modify the previous cell placement and the routing module1300may perform the signal routing with the modified cell placement. When the routing is successfully completed, the routing module1300may provide output data D0defining the integrated circuit.

The placement module1200and the routing module1300may be implemented by a single integrated designing module1400or may be implemented by separate and different modules. The integrated designing module1400including the placement module1200and the routing module1300may perform the placement and the routing such that the delay matching and/or the duty ratio adjustment may be implemented in the integrated circuit using the plurality of load standard cells.

The placement module1200and/or the routing module1300may be implemented in software, but inventive concepts are not limited thereto. If the placement module1200and the routing module1300are implemented in software, they may be stored in the storage medium1100as program codes or in other storage mediums.

The processor1500may be used when the designing module1400performs a computation. InFIG. 2, only one processor1500is illustrated, but inventive concepts are not limited thereto. For example, a plurality of processors may be included in the designing system1000. In addition, the processor1500may include cache memories, which increase computation capacity.

The designing module1400may determine a delay difference between a first signal path and a second signal path of the integrated circuit where delay matching is required or specified between the first signal path and the second signal path. The placement module1200may place a selected load standard cell among the plurality of load standard cells where the selected load standard cell is to provide a delay corresponding to the delay difference through a load node. The routing module1300may route the selected load standard cell such that the load node of the selected load standard cell is connected to one of the first signal path and the second signal path that has a smaller delay.

As such, the integrated circuit and the method of designing the integrated circuit according to some example embodiments may enhance design efficiency and performance of the integrated circuit by designing the integrated circuit with delay matching and duty ratio adjustment using the load standard cell.

FIG. 3is a flow chart illustrating an example operation of the designing system ofFIG. 2.

Referring toFIGS. 2 and 3, the designing module1400may receive the input data DI defining the integrated circuit (S11). The placement module1200may refer to the standard cell library1110so as to extract standard cells corresponding to the input data DI, and may perform cell placement using the extracted standard cells (S12). The routing module1300may perform signal routing with respect to the placed cells (S13). When the signal routing is not successful (S14: NO), the placement module1200may replace at least one standard cell, e.g. may replace at least one standard cell with another standard cell, to modify the placement of the cells. The routing module1300may perform the signal routing again with respect to the modified placement (S13).

As such, the replacement and the routing may be repeated until the signal routing is successfully completed. The success of the placement and the routing may include the success of delay matching and/or duty ratio adjustment. When the signal routing is successfully completed (S14: YES), the designing module1400may generate the output data D0defining the integrated circuit (S16).

Hereinafter, structures of a cell and an integrated circuit including a plurality of cells are described using a first direction X, a second direction Y and a third direction Z in a three-dimensional space. The first direction X may be a row direction, the second direction Y may be a column direction and the third direction Z may be a vertical direction.

FIG. 4is a diagram illustrating a layout of an integrated circuit according to some example embodiments.

An integrated circuit300ofFIG. 4may be an application specific integrated circuit (ASIC). A layout of the integrated circuit300may be determined by performing the above-described placement and routing of standard cells SC1˜SC12. Power may be provided to the standard cells SC1˜SC12through power rails311˜316. The power rails311˜316may include high power rails311,313, and315configured to provide a first power supply voltage VDD and low power rails312,314, and316configured to provide a second power supply voltage VSS that is lower than the first power supply voltage VDD. For example, the first power supply voltage VDD may have a positive voltage level and the second power supply voltage VSS may have a ground level (e.g., 0V) or a negative voltage level.

The high power rails311,313, and315and the low power rails312,314, and316extend in the row direction X and be arranged alternatively one by one in the column direction Y to form boundaries of a plurality of circuit rows CR1˜CR5that is arranged in the column direction Y. The numbers of the power rails and the circuit rows are non-limiting examples and may be determined variously.

According to some example embodiments, power may be distributed to the power rails311˜316through power mesh routes321˜324that extend in the column direction Y. Some power mesh routes322and324may provide the first power supply voltage VDD and other power mesh routes321and323may provide the second power supply voltage VSS. The power mesh routes321˜324may be connected to the power rails311˜316through vertical contacts VC such as via contacts.

In general, each of the circuit rows CR1˜CR5may be connected to two adjacent power rails that are at boundaries thereof so as to be powered. For example, the standard cells SC1, SC2, SC3, and SC4in the first circuit row CR1may be connected to an adjacent and corresponding power rail pair including the high power rail311and the low power rail312.

For example, as illustrated inFIG. 4, an output node of the eighth standard cell SC8and an input node of the ninth standard cell SC9may be connected through wirings331and332. The eighth and ninth standard cells SC8and SC9may be logic standard cells performing each logic operation, and the output node of the eighth standard cell SC8or the input node of the ninth standard cell SC9may be a delay node that requires a certain delay. In this case, the fourth standard cell SC4corresponding to the above-described load standard cell may be connected to the delay node through a wiring333.

FIG. 5is a diagram illustrating a layout of an example standard cell, andFIGS. 6A, 6B and 6Care cross-sectional views of a standard cell that may have the same layout as the standard cell ofFIG. 5.

FIGS. 6A, 6B, and 6Cillustrate a portion of a standard cell SCL that includes a fin field effect transistor (FinFET).FIG. 6Ais a cross-sectional view of the standard cell SCL ofFIG. 5cut along a line A-A′.FIG. 6Bis a cross-sectional view of the standard cell SCL ofFIG. 5cut along a line B-B′.FIG. 6Cis a cross-sectional view of the standard cell SCL ofFIG. 5cut along a line C-C′.

Referring toFIGS. 5, 6A, 6B and 6C, the standard cell SCL may be formed on a substrate110having an upper surface110A that extends in a horizontal direction, e.g., the first direction X and the second direction Y.

In some example embodiments, the substrate110may include a semiconductor such as Si or Ge or a compound semiconductor such as SiGe, SiC, GaAs, InAs, or InP. In some example embodiments, the substrate110may have a silicon on insulator (SOI) structure. The substrate110may include a conductive area such as an impurity-doped well or an impurity-doped structure.

The standard cell SCL includes a first device area RX1, a second device area RX2and an active cut area ACR separating the first and second device areas RX1and RX2. In each of the first and second device areas RX1and RX2, a plurality of fin-type active areas AC protruding from the substrate110may be formed.

The plurality of active areas AC may extend in parallel to one another in the first direction X. A device isolation layer112may be formed between the plurality of active areas AC on the substrate110. The plurality of active areas AC protrude from the device isolation layer112in the form of fins.

A plurality of gate insulation layers118and a plurality of gate lines PC11,12,13,14,15and16may be formed on the substrate110. The gate lines PC11,12,13,14,15and16may extend in the second direction Y crossing the plurality of active areas AC. The plurality of gate insulation layers118and the plurality of gate lines PC11,12,13,14,15and16may extend while covering an upper surface and two sidewalls of each of the active areas AC and an upper surface of the device isolation layer112. A plurality of metal oxide semiconductor (MOS) transistors may be formed along the plurality of gate lines PC11,12,13,14,15and16. The MOS transistors may have a three-dimensional structure in which channels are formed in the upper surface and the two sidewalls of the active areas AC.

The gate insulation layers118may be formed of a silicon oxide layer, a high-k dielectric layer, or a combination thereof. The plurality of gate lines PC11,12,13,14,15and16may extend on the gate insulation layers118across the plurality of active areas AC while covering the upper surface and the two sidewalls of each of the active areas AC.

A mask122may be formed on each of the gate lines PC11,12,13,14,15, and16. Side walls of the insulation layer118, the gate line PC and the mask122may be covered by a spacer124. The gate lines PC11,12,13,14,15and16may have a structure in which a metal nitride layer, a metal layer, a conductive capping layer, and a gap-fill metal layer are sequentially stacked. The metal nitride layer and the metal layer may include Ti, Ta, W, Ru, Nb, Mo, and/or Hf. The metal layer and the metal nitride layer may be formed, for example, by using an atomic layer deposition (ALD) method, a metal organic ALD method, and/or a metal organic chemical vapor deposition (MOCVD) method. The conductive capping layer may function as a protection layer that prevents oxidization of a surface of the metal layer. In addition, the conductive capping layer may function as an adhesive layer (e.g., a wetting layer) that facilitates deposition of another conductive layer on the metal layer. The conductive capping layer may be formed of a metal nitride such as a TiN or TaN or a combination thereof, but inventive concepts are not limited thereto. The gap-fill metal layer may fill spaces between the active areas AC and extend on the conductive capping layer. The gap-fill metal layer may be formed of a W (e.g., tungsten) layer. The gap-fill metal layer may be formed, for example, by using an ALD method, a CVD method, or a physical vapor deposition (PVD) method.

A plurality of conductive contacts CA and CB are formed at a first layer LY1on the active areas AC. The plurality of conductive contacts CA and CB include a plurality of first contacts CA21,22,23,24,25,31,32,33,34and35connected to a source/drain area116of the active areas AC and a plurality of second contacts CB41,42and43connected to the gate lines11,12,13,14,15and16.

The plurality of conductive contacts CA and CB may be insulated from each other by a first interlayer insulation layer132that covers the active areas AC and the gate lines GL. The plurality of conductive contacts CA and CB may have an upper surface that is at substantially the same level as an upper surface of the first interlayer insulation layer132. The first interlayer insulation layer132may be formed of a silicon oxide layer, but inventive concepts are not limited thereto.

A second interlayer insulation layer134and a plurality of lower via contacts V051,52,53,54,55,56,57,58,59,60,61and62that pass through the second interlayer insulation layer134are formed on the first interlayer insulation layer132. The second interlayer insulation layer134may be formed of a silicon oxide layer, but inventive concepts are not limited thereto.

A plurality of wirings M171,72,73,74,75,76,77and78extending in the horizontal direction at a second layer LY2, which is higher than the first layer LY1, are formed on the second interlayer insulation layer134.

Each of the wirings M1may be connected to one of the plurality of conductive contacts CA and CB through one of the plurality of lower via contacts V0formed between the first layer LY1and the second layer LY2. Each of the plurality of lower via contacts V0may be connected to one of the plurality of conductive contacts CA and CB, for example, by passing through the second interlayer insulation layer134. The plurality of lower via contacts V0may be insulated from one another by the second interlayer insulation layer134.

The wirings71˜78may include an internal connection wiring that electrically connects a plurality of areas in the standard cell SCL. For example, the internal connection wiring78may electrically connect the active area AC in the first device area RX1and the active area AC in the second device area RX2through the lower via contacts55and58and the first contacts24and33.

Wirings71and72may correspond to a first power rail and second power rail, respectively. The first power rail71may be connected to the active area AC which is in the first device area RX1, and the second power rail72may be connected to the active area AC which is in the second device area RX2. One of the first and second power rails71and72may be a wiring for supplying a power supply voltage (e.g., the first power supply voltage VDD) and the other of the first and second power rails71and72may be a wiring for supplying a ground voltage (e.g., the second power supply voltage VSS).

The first power rail71and the second power rail72may extend in the first direction X in parallel to one another on the second layer LY2. In some example embodiments, the power rails71and72may be formed at substantially the same time with the other wirings73˜78. The wirings M1may be formed to pass through a third interlayer insulation layer136. The third interlayer insulation layer136may insulate the wirings M1from one another.

A height CH of the standard cell SCL may be defined by the distance along the second direction Y between the first power rail71and the second power rail72. In addition, a width CW of the standard cell SCL may be defined along the first direction X that is parallel to the power rails71and72.

The wirings M1may have to meet limitations due to a minimum spacing rule. For example, the wirings M1may have to meet limitations according to a “tip-to-side” restriction and a “corner rounding” restriction. The size and disposition of the wirings M1may be limited by such restrictions.

The lower via contacts V0and the wirings M1may have a stacked structure of a barrier layer and a wiring conductive layer. The barrier layer may be formed, for example, of TiN, TaN, or a combination thereof. The wiring conductive layer may be formed, for example, of W, Cu, an alloy thereof, or a combination thereof. A CVD method, an ALD method, and/or an electroplating method may be used to form the wirings M1and the lower via contacts V0.

The integrated circuit according to some example embodiments may correspond to a single standard cell that is formed as described above or a combination of various standard cells.

FIG. 7is a diagram illustrating an example integrated circuit, andFIG. 8is a timing diagram illustrating an operation of the integrated circuit ofFIG. 7.

Referring toFIG. 7, an integrated circuit401may include a first NAND gate ND0, a second NAND gate ND1and a third NAND gate ND2. The integrated circuit ofFIG. 7corresponds to a configuration to generate a double data rate (DDR) signal.

The first NAND gate ND0performs a NAND operation on a first data signal D0and an inversion signal Sb of a selection signal SEL to generate a first internal signal d0i. The selection signal SEL may be a clock signal as illustrated inFIG. 8. The second NAND gate ND1performs a NAND operation on a second data signal D1and the selection signal SEL to generate a second internal signal d1i. The third NAND gate ND2performs a NAND operation on the first internal signal d0iand the second internal signal d1ito generate an output signal OUT.

Referring toFIGS. 7 and 8, the integrated circuit401samples the second data signal D1in synchronization with rising edges of the selection signal SEL and samples the first data signal D0in synchronization with falling edges of the selection signal SEL. The sampled data of the second data signal D1included in the output signal OUT has a delay of tND1+tND2, and the sampled data of the first data signal D0included in the output signal OUT has a delay of tINV+tND0+tND2. Here tINV indicates a delay of the inverter INV, tND0indicates a delay of the first NAND gate ND0, tND1indicates a delay of the second NAND gate ND1, and tND2indicates a delay of the third NAND gate ND2.

A delay difference may be caused between the first internal signal d0iand the second internal signal d1idue to a delay of the inversion signal Sb with respect to the selection signal SEL. The delay difference is reflected to the output signal OUT and thus the output signal OUT has propagation delay deviation. For example, the propagation delay deviation is caused between a case of logic low “0” of the selection signal SEL and a case of logic high “1” of the selection signal SEL due the delay of the inverter INV. In this case, as will be described below with reference toFIG. 11, degeneration occurs in an eye pattern of the output signal OUT and a valid window margin may be decreased.

FIG. 9is a diagram illustrating an integrated circuit according to some example embodiments, andFIG. 10is a timing diagram illustrating an operation of the integrated circuit ofFIG. 9.

Referring toFIG. 9, an integrated circuit402may include a first NAND gate ND0, a second NAND gate ND1, a third NAND gate ND2, and a load standard cell LSC. The integrated circuit ofFIG. 9corresponds to a configuration ofFIG. 7to generate a signal, e.g. a DDR signal.

The first NAND gate ND0performs a NAND operation on a first data signal D0and an inversion signal Sb of a selection signal SEL to generate a first internal signal d0i. The selection signal SEL may be a clock signal as illustrated inFIG. 10. The second NAND gate ND1performs a NAND operation on a second data signal D1and the selection signal SEL to generate a second internal signal d1id. The load standard cell LSC is connected to the output node of the second NAND gate ND1to provide an additional delay. The load standard cell LSC may include a first electrode connected to the output node of the second NAND gate ND1and a second electrode connected to a bias voltage VB. The third NAND gate ND2performs a NAND operation on the first internal signal d0iand the second internal signal d1idto generate an output signal OUT.

Referring toFIGS. 9 and 10, the integrated circuit402may sample the second data signal D1in synchronization with rising edges of the selection signal SEL and may sample the first data signal D0in synchronization with falling edges of the selection signal SEL. The sampled data of the second data signal D1included in the output signal OUT has a delay of (tND1+tL)+tND2, and the sampled data of the first data signal D0included in the output signal OUT has a delay of tINV+tND0+tND2. Here tL indicates a delay of the load standard cell LSC, tINV indicates a delay of the inverter INV, tND0indicates a delay of the first NAND gate ND0, tND1indicates a delay of the second NAND gate ND1, and tND2indicates a delay of the third NAND gate ND2. tND0, tND1and tND3may be substantially the same.

Even though a delay difference may be caused between the first internal signal d0iand the second internal signal d1iddue to a delay of the inversion signal Sb with respect to the selection signal SEL, the delay difference may be compensated by the delay tL of the load standard cell LSC. According to some example embodiments, the propagation delay may be controlled by connecting the load standard cell LSC to the output node of the second NAND gate ND1. The delay matching may be performed by selecting an optimum load standard cell among the plurality of load standard cells having different delay characteristics such that the delay difference between tND1+tL and tINV+tND0may be as small as possible. Through such delay matching, a valid window margin of the output signal OUT may be secured.

FIG. 11is a diagram for describing delay matching and duty ratio adjustment in an integrated circuit according to some example embodiments.

An eye pattern corresponding to the integrated circuit401ofFIG. 7is shown in a left portion ofFIG. 11and an eye pattern corresponding to the integrated circuit402ofFIG. 9is shown in a right portion ofFIG. 11

As illustrated inFIG. 11, if the eye pattern of the output signal OUT is measured without delay matching, the valid window margin of the eye pattern is reduced due to propagation delay deviation. The valid window margin may be increased if the delay matching is performed to compensate the propagation delay deviation using the load standard cell LSC.

As such, performance of the integrated circuit may be enhanced by performing delay matching using a plurality of load standard cells having different delay characteristics in layout design based on automatic replacement and routing.

FIGS. 12A through 16Bare diagrams illustrating a load standard cell according to some example embodiments.

FIGS. 12A through 16Billustrate example embodiments of load standard cells having different delay characteristics. The load standard cells compatible with the FinFET process as described with reference toFIGS. 5 through 6Care illustrated inFIGS. 12B, 13B, 14B, 15B and 16B, but inventive concepts are not limited thereto. As described above, inFIGS. 12B, 13B, 14B, 15B and 16B, PC indicates gate lines, CA indicates first contacts, CB indicates second contacts, V0indicates via contacts, M1indicates wirings, CW1and CW2indicate cell widths of load standard cells, CH indicates a cell height of the load standard cells, RX1indicates a first device area, RX2indicates a second device area and ACR indicates an active cut area. The configurations inFIGS. 12B, 13B, 14B, 15B and 16Bmay be understood referring to the descriptions ofFIGS. 5 through 6C, and thus repeated descriptions may be omitted.

FIG. 12Aillustrates a schematic of a load standard cell LSC1including a P-channel metal oxide semiconductor (PMOS) transistor TP and an N-channel metal oxide semiconductor (NMOS) transistor TN. Referring toFIG. 12A, a source electrode and a drain electrode of the PMOS transistor TP may be connected to a power supply voltage VDD, a source electrode and a drain electrode of the NMOS transistor TN may be connected to a ground voltage VSS, and a gate electrode of the PMOS transistor TP and a gate electrode of the NMOS transistor TN may be commonly connected to a load node NL for providing a delay. The PMOS transistor TP and the NMOS transistor TN connected as such may be provided as a single load standard cell LSC1and included in a standard cell library.

FIG. 12Billustrates an example layout corresponding to the schematic of the load standard cell LSC1ofFIG. 12A. Referring toFIGS. 12A and 12B, the PMOS transistor TP is formed in a first device area RX1and the NMOS transistor TN is formed in a second device area RX2. In this case, the power supply voltage VDD may be provided through a first power rail71and the ground voltage VSS may be provided through a second power rail72.

The source electrode and the drain electrode of the PMOS transistor TP may be connected to the power supply voltage VDD through first contacts21and22and via contacts51and52. The source electrode and the drain electrode of the NMOS transistor TN may be connected to the ground voltage VSS through first contacts31and32and via contacts53and54. The common gate line11of the PMOS transistor TP and the NMOS transistor TN may be connected to a wiring75through a via contact61, and the wiring75corresponding to a load node NL may be connected to a delay node of another standard cell.

As such, a load standard cell may be implemented using a metal oxide semiconductor (MOS) capacitor that is formed by connecting a source electrode and a drain electrode of a MOS transistor. A plurality of MOS capacitors may be implemented to have different capacitance values so that a plurality of load standard cells including the MOS capacitors may have different delay characteristics.

In some example embodiments, the MOS capacitor may be designed such that, during fabrication of the integrated circuit, the capacitance of the MOS capacitor is controlled by adjusting a density of impurities that are implanted into a gate electrode of the MOS transistor, that is, the gate line11inFIG. 12B.

In some example embodiments, the capacitance of the MOS capacitor may be controlled by adjusting a size of the MOS capacitor or the MOS transistor. The size of the MOS capacitor may include a size or a relative position of two opposing conductors of the MOS capacitor, etc. For example, the capacitance value of the MOS capacitor may be controlled by adjusting a length of the gate line11.

In some example embodiments, the different delay characteristics may be implemented by controlling the capacitance of the MOS capacitor using a parallel structure ofFIGS. 13A and 13Band/or a serial structure ofFIGS. 14A and 14B.

FIG. 13Aillustrates a schematic of a load standard cell LSC2including a plurality of PMOS transistors TP1and TP2and a plurality of NMOS transistors TN1and TN2.FIG. 13Aillustrates a non-limiting example of two PMOS transistors and two NMOS transistors for convenience of illustration, and the number of the transistors may be changed variously.

Referring toFIG. 13A, a source electrode and a drain electrode of a first PMOS transistor TP1may be connected to a power supply voltage VDD and a source electrode and a drain electrode of a first NMOS transistor TN1are connected to a ground voltage VSS. In the same way, a source electrode and a drain electrode of a second PMOS transistor TP2may be connected to the power supply voltage VDD, and a source electrode and a drain electrode of a second NMOS transistor TN2may be connected to the ground voltage VSS. A gate electrode of the first PMOS transistor TP1, a gate electrode of the second PMOS transistor TP2, a gate electrode of the first NMOS transistor TN1and a gate electrode of the second NMOS transistor TN2may be commonly connected to a load node NL for providing a delay. The PMOS transistors TP1and TP2and the NMOS transistors TN1and TN2connected in parallel as such may be provided as a single load standard cell LSC2and included in a standard cell library.

FIG. 13Billustrates an example layout corresponding to the schematic of the load standard cell LSC2ofFIG. 13A. Referring toFIGS. 13A and 13B, the PMOS transistors TP1and TP2are formed in a first device area RX1and the NMOS transistors TN1TN2are formed in a second device area RX2. In this case, the power supply voltage VDD may be provided through a first power rail71and the ground voltage VSS may be provided through a second power rail72.

The source electrodes and the drain electrodes of the PMOS transistors TP1and TP2may be connected to the power supply voltage VDD through first contacts21,22,23and24and via contacts51,52,53and54. The source electrodes and the drain electrodes of the NMOS transistors TN1and TN2may be connected to the ground voltage VSS through first contacts31,32,33and34and via contacts55,56,57and58.

The common gate line11of the first PMOS transistor TP1and the first NMOS transistor TN1and the common gate line13of the second PMOS transistor TP2and the second NMOS transistor TN2may be connected to a wiring75through via contacts61and62, and the wiring75corresponding to a load node NL may be connected to a delay node of another standard cell. A gate line12is a dummy gate line that is in a floated state.

FIG. 14Aillustrates a schematic of a load standard cell LSC3including a plurality of PMOS transistors TP1and TP2and a plurality of NMOS transistors TN1and TN2.FIG. 14Aillustrates a non-limiting example of two PMOS transistors and two NMOS transistors for convenience of illustration, and the number of the transistors may be changed variously.

Referring toFIG. 14A, a source electrode and a drain electrode of a first PMOS transistor TP1may be connected to a gate electrode of a second PMOS transistor TP2, and a source electrode and a drain electrode of a second PMOS transistor TP2may be connected to a power supply voltage VDD. A source electrode and a drain electrode of a first NMOS transistor TN1may be connected to a gate electrode of the second NMOS transistor TN2and a source electrode and a drain electrode of a second NMOS transistor TN2are connected to a ground voltage VSS. A gate electrode of the first PMOS transistor TP1and a gate electrode of the first NMOS transistor TN1may be commonly connected to a load node NL for providing a delay. The PMOS transistors TP1and TP2and the NMOS transistors TN1and TN2connected in series as such may be provided as a single load standard cell LSC3and included in a standard cell library.

FIG. 14Billustrates an example layout corresponding to the schematic of the load standard cell LSC3ofFIG. 14A. Referring toFIGS. 14A and 14B, the PMOS transistors TP1and TP2are formed in a first device area RX1and the NMOS transistors TN1TN2are formed in a second device area RX2. In this case, the power supply voltage VDD may be provided through a first power rail71and the ground voltage VSS may be provided through a second power rail72.

The source electrodes and the drain electrodes of the first PMOS transistor TP1may be connected to the gate electrode of the second PMOS transistor TP2, that is, a gate line segment13through first contacts21and22, via contacts62,63and64and a wiring76. The source electrode and the drain electrode of the second PMOS transistor TP2may be connected to the power supply voltage VDD through first contacts23and24and via contacts51and52.

The source electrodes and the drain electrodes of the first NMOS transistor TN1may be connected to the gate electrode of the second NMOS transistor TN2, for example, a gate line segment14through first contacts31and32, via contacts65,66and67and a wiring77. The source electrode and the drain electrode of the second NMOS transistor TN2may be connected to the ground voltage VSS through first contacts33and34and via contacts53and54.

The common gate line11of the first PMOS transistor TP1and the first NMOS transistor TN1may be connected to a wiring75through a via contact61, and the wiring75corresponding to a load node NL may be connected to a delay node of another standard cell. A gate line12is a dummy gate line that is in a floated state.

FIG. 15Aillustrates a schematic of a load standard cell LSC4including a PMOS transistor TP. Referring toFIG. 15A, a source electrode and a drain electrode of the PMOS transistor TP may be connected to a power supply voltage VDD, and a gate electrode of the PMOS transistor TP may be connected to a load node NL for providing a delay. The corresponding NMOS transistor according to a complementary MOS (CMOS) fabrication process may be remained in a dummy state, and its illustration is omitted inFIG. 15A. The PMOS transistor TP connected as such may be provided as a single load standard cell LSC4and included in a standard cell library.

FIG. 15Billustrates an example layout corresponding to the schematic of the load standard cell LSC4ofFIG. 15A. Referring toFIGS. 15A and 15B, the PMOS transistor TP is formed in a first device area RX1and the corresponding NMOS transistor in a second device area RX2may be omitted. In this case, the power supply voltage VDD may be provided through a first power rail71and the ground voltage VSS may be provided through a second power rail72.

The source electrode and the drain electrode of the PMOS transistor TP may be connected to the power supply voltage VDD through first contacts21and22and via contacts51and52. The gate line segment12corresponding to the gate electrode of the PMOS transistor TP may be connected to a wiring75through a via contact61and the wiring75corresponding to a load node NL may be connected to a delay node of another standard cell. The other gate line segment11may be a dummy segment that is floated.

FIG. 16Aillustrates a schematic of a load standard cell LSC5including an NMOS transistor TN. Referring toFIG. 16A, a source electrode and a drain electrode of the NMOS transistor TN may be connected to a ground voltage VSS, and a gate electrode of the NMOS transistor TN may be connected to a load node NL for providing a delay. The corresponding PMOS transistor according to a CMOS fabrication process may be remained in a dummy state, and its illustration is omitted inFIG. 16A. The NMOS transistor TN connected as such may be provided as a single load standard cell LSC5and included in a standard cell library.

FIG. 16Billustrates an example layout corresponding to the schematic of the load standard cell LSC5ofFIG. 16A. Referring toFIGS. 16A and 16B, the NMOS transistor TN is formed in a second device area RX2and the corresponding PMOS transistor in a first device area RX1may be omitted. In this case, the power supply voltage VDD may be provided through a first power rail71and the ground voltage VSS may be provided through a second power rail72.

The source electrode and the drain electrode of the NMOS transistor TN may be connected to the ground voltage VSS through first contacts31and32and via contacts51and52. The gate line segment11corresponding to the gate electrode of the NMOS transistor TN may be connected to a wiring75through a via contact61and the wiring75corresponding to a load node NL may be connected to a delay node of another standard cell. The other gate line segment12may be a dummy segment that is floated.

The load standard cell LSC4ofFIG. 15Amay cause a larger delay to a falling edge of a signal than a rising edge of the signal because the power supply voltage VDD is applied to an opposite electrode of the load node NL. In contrast, the load standard cell LSC5ofFIG. 16Amay cause a larger delay to the rising edge of the signal than the falling edge of the signal because the ground voltage VSS is applied to an opposite electrode of the load node NL. A duty ratio of the signal of the integrated circuit may be adjusted using at least one of the load standard cells LSC4and LSC5having different delay characteristics.

FIG. 17is a block diagram illustrating an integrated circuit according to some example embodiments.

Referring toFIG. 17, an integrated circuit403may include a first logic standard cell SC1including a first delay node ND1, a second logic standard cell SC2including a second delay node ND2, a third logic standard cell SC3, a fourth logic standard cell SC4, a first load standard cell LSCa and a second load standard cell LSCb.

The first load standard cell LSCa may include a first load node providing a first delay and the first load node is connected to the first delay node ND1. The second load standard cell LSCb includes a second load node providing a second delay different from the first delay and the second load node is connected to the second delay node ND2. A first bias voltage VB1may be applied to an opposite electrode of the first load node of the first load standard cell LSCa and a second bias voltage VB2may be applied to an opposite electrode of the second load node of the second load standard cell LSCb.

The first logic standard cell SC1may performs a logic operation on a first signal S1to generate a second signal S2, and the third logic standard cell SC3may perform a logic operation on the second signal S2to generate a third signal S3. The second logic standard cell SC2may performs a logic operation on a fourth signal S4to generate a fifth signal S5, and the fourth logic standard cell SC4may perform a logic operation on the fifth signal S5to generate a sixth signal S6.

One of the first bias voltage VB1and the second bias voltage VB2may correspond to the power supply voltage VDD and the other of the first bias voltage VB1and the second bias voltage VB2may correspond to the ground voltage VSS. In this case, as described with reference toFIGS. 15A and 15B, one of the first load standard cell LSCa and the second load standard cell LSCb may provide a larger delay to a rising edge of a signal and the other of the first load standard cell LSCa and the second load standard cell LSCb may provide a larger delay to a falling edge of the signal.

FIGS. 18A and 18Bare timing diagrams illustrating operations of the integrated circuit ofFIG. 17.

Referring toFIGS. 17 and 18A, the first load standard cell LSCa may cause a larger delay to a falling edge of a signal than a rising edge of the signal. According to the delay characteristic of the first load standard cell LSCa, a falling time tF1of the second signal S2may be longer than a rising time tR1of the second signal S2, and thus a delay tDF1of a falling edge of the third signal S3with respect to the first signal S1may be larger than a delay tDR1of a rising edge of the third signal S3with respect to the first signal S1. If the first signal S1has a duty ratio smaller than a value of 0.5, a duty ratio of the third signal S3may be increased to approach the value of 0.5 using the first load standard cell LSCa.

Referring toFIGS. 17 and 18B, the second load standard cell LSCb may cause a larger delay to a rising edge of a signal than a falling edge of the signal. According to the delay characteristic of the second load standard cell LSCb, a rising time tR2of the fifth signal S5may be longer than a falling time tF2of the fifth signal S5, and thus a delay tDR2of a rising edge of the sixth signal S6with respect to the fourth signal S4may be larger than a delay tDF2of a falling edge of the sixth signal S4with respect to the fourth signal S4. If the fourth signal S4has a duty ratio larger than a value of 0.5, a duty ratio of the sixth signal S6may be decreased to approach the value of 0.5 using the second load standard cell LSCb.

As such, a duty ratio of a signal of the integrated circuit may be adjusted using at least one of the first load standard cell LSCa and the second load standard cell LSCb having the different delay characteristics.

FIG. 19is a block diagram illustrating an integrated circuit according to some example embodiments.

FIG. 19illustrates an example embodiment of a digitally-controlled delay line as an example integrated circuit. The digitally-controlled delay line has five stages controlled by five-bit selection signals SEL1˜SEL5is illustrated inFIG. 19for convenience of illustration, but the number of stages in the delay line may be determined variously.

Referring toFIG. 19, an integrated circuit404may include a plurality of input NAND gates GA1˜GA5, a plurality of intermediate NAND gates GB0˜GB4, a plurality of output NAND gates GC0˜GC4, a plurality of intermediate load standard cells LSC12˜LSC15and a plurality of output load standard cells LSC21˜LSC25.

Each of the plurality of input NAND gates GA1˜GA5may perform a NAND operation on each of inversion signals of the selection signals SEL1˜SEL5and may output of the previous input NAND gate. The first input NAND gate GA1receives an input signal IN. Each of the plurality of intermediate NAND gates GB0˜GB4may perform a NAND operation on each of the selection signals SEL1˜SEL5and may output the corresponding input NAND gate. The first intermediate NAND gate GB0receives the input signal IN. Each of the plurality of output NAND gates GC0˜GC4performs a NAND operation on output of the corresponding intermediate NAND gate and output of the previous output NAND gate. The first output NAND gate GC0provides an output signal OUT that is delayed finally.

The selection signals SELL˜SEL5may form a thermometric code. For example, as illustrated inFIG. 19, the first, second and third selection signals SEL1, SEL2and SEL3may have values of “0” and the fourth and fifth selection signals SEL4and SEL5may have values of “1”. In this case, the input signal IN passes through the three input NAND gates GA1, GA2and GA3, the one intermediate NAND gate GB3and the four output NAND gates GC3, GC2, GC1and GC0to provide the finally delayed output signal OUT.

Each output of the input NAND gates GA1˜GA5is provided as inputs of the two NAND gates, that is, the next input NAND gate and the corresponding intermediate NAND gate. In contrast, each output of the intermediate NAND gates GB0˜GA4is provided as an input of the one NAND gate, that is, the corresponding output NAND gate. With such mismatch of the output loads, the delay mismatch may cause degeneration of operational characteristics of the integrated circuit404. According to some example embodiments, the plurality of intermediate load standard cells LSC11˜LSC15may be connected to the output nodes of the plurality of intermediate NAND gates GB0˜GB4to implement delay matching. In the same way, the plurality of output load standard cells LSC21˜LSC25may be connected to the output nodes of the plurality of output NAND gates GC0˜GC4.

FIG. 20is a block diagram illustrating a mobile device according to some example embodiments.

Referring toFIG. 20, a mobile device4000may include at least one application processor4100, a communication module4200, a display/touch module4300, a storage device4400, and a buffer RAM4500.

The application processor4100may control operations of the mobile device4000. The communication module4200is implemented to perform wireless or wire communications with an external device. The display/touch module4300is implemented to display data processed by the application processor4100and/or to receive data through a touch panel. The storage device4400is implemented to store user data. The storage device4400may be or include an embedded multimedia card (eMMC), a solid state drive (SSD, a universal flash storage (UFS) device, etc. The storage device4400may perform caching of the mapping data and the user data as described above.

The buffer RAM4500may temporarily store data used for processing operations of the mobile device4000. For example, the buffer RAM4500may be or include volatile memory such as double data rate (DDR) synchronous dynamic random access memory (SDRAM), low power double data rate (LPDDR) SDRAM, graphics double data rate (GDDR) SDRAM, Rambus dynamic random access memory (RDRAM), etc.

At least one component in the mobile device4000may include at least one load standard cell according to some example embodiments. As described above, a design of the load standard cell may be included in the standard cell library and integrated circuits included in the mobile device4000may be designed through automatic placement and routing by a design tool.

As described above, the integrated circuit and the method of designing the integrated circuit according to some example embodiments may enhance design efficiency and performance of the integrated circuit by designing the integrated circuit with delay matching and duty ratio adjustment using the load standard cell.

Inventive concepts may be applied to any electronic devices and systems. For example, the present inventive concept may be applied to systems such as be a memory card, a solid state drive (SSD), an embedded multimedia card (eMMC), a mobile phone, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a camcorder, personal computer (PC), a server computer, a workstation, a laptop computer, a digital TV, a set-top box, a portable game console, a navigation system, a wearable device, an internet of things (IoT) device, an internet of everything (IoE) device, an e-book, a virtual reality (VR) device, an augmented reality (AR) device, etc.

By designing and/or fabricating an integrated circuit to include load standard cells having different delay characteristics, a design efficiency and performance of the integrated circuit may be enhanced.

Units and/or devices according to one or more example embodiments may be implemented using hardware, a combination of hardware and software, or storage media storing software. Hardware may be implemented using processing circuitry such as, but not limited to, one or more processors, one or more Central Processing Units (CPUs), one or more controllers, one or more arithmetic logic units (ALUs), one or more digital signal processors (DSPs), one or more microcomputers, one or more field programmable gate arrays (FPGAs), one or more System-on-Chips (SoCs), one or more programmable logic units (PLUs), one or more microprocessors, one or more Application Specific Integrated Circuits (ASICs), or any other device or devices capable of responding to and executing instructions in a defined manner.

For example, when a hardware device is a computer processing device (e.g., one or more processors, CPUs, controllers, ALUs, DSPs, microcomputers, microprocessors, etc.), the computer processing device may be configured to carry out program code by performing arithmetical, logical, and input/output operations, according to the program code. Once the program code is loaded into a computer processing device, the computer processing device may be programmed to perform the program code, thereby transforming the computer processing device into a special purpose computer processing device. In a more specific example, when the program code is loaded into a processor, the processor becomes programmed to perform the program code and operations corresponding thereto, thereby transforming the processor into a special purpose processor. In another example, the hardware device may be an integrated circuit customized into special purpose processing circuitry (e.g., an ASIC).

Software and/or data may be embodied permanently or temporarily in any type of storage media including, but not limited to, any machine, component, physical or virtual equipment, or computer storage medium or device, capable of providing instructions or data to, or being interpreted by, a hardware device. The software also may be distributed over network coupled computer systems so that the software is stored and executed in a distributed fashion. In particular, for example, software and data may be stored by one or more computer readable recording mediums, including tangible or non-transitory computer-readable storage media as discussed herein.

The one or more hardware devices, the storage media, the computer programs, program code, instructions, or some combination thereof, may be specially designed and constructed for the purposes of the example embodiments, or they may be known devices that are altered and/or modified for the purposes of example embodiments.

The foregoing is illustrative of some example embodiments and is not to be construed as limiting thereof.