SEMICONDUCTOR DEVICE

A semiconductor device may include a lower substrate; an active region on the lower substrate; a common source plate spaced apart from an upper surface of the lower substrate in a vertical direction, and the common source plate overlapping the upper surface of the lower substrate; a discharge structure directly connecting the common source plate and the active region in the vertical direction, and the discharge structure having a wall shape extending in a first direction parallel to the upper surface of the lower substrate; and a cell array structure on the common source plate. A length of the discharge structure in the first direction may be greater than a width of the discharge structure in a second direction parallel to the upper surface of the lower substrate and perpendicular to the first direction.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 USC § 119 to Korean Patent Application No. 10-2023-0020602, filed on Feb. 16, 2023, in the Korean Intellectual Property Office (KIPO), the contents of which are incorporated by reference herein in their entirety.

BACKGROUND

Various example embodiments relate to semiconductor devices. For example, various example embodiments relate to a vertical memory device.

As information communication devices become multifunctional, memory cells included in a semiconductor device may have a large capacity and may be highly integrated. Alternatively or additionally, a size of each of the memory cells may gradually decrease, and operating circuits and/or wiring structures included in the semiconductor device for operation and/or electrical connection of the semiconductor device may be more complicated. Accordingly, processes for manufacturing the semiconductor device may be complicated, and/or electrical defects may occur during the processes for manufacturing the semiconductor device.

SUMMARY

Various example embodiments provide a semiconductor device having improved or excellent electrical characteristics and/or high reliability.

According to some example embodiments, there is provided a semiconductor device comprising a lower substrate, an active region on the lower substrate, a common source plate spaced apart from an upper surface of the lower substrate in a vertical direction, and the common source plate at least partly overlapping the upper surface of the lower substrate, a discharge structure directly connecting the common source plate and the active region in the vertical direction, the discharge structure having a structure in which a plurality of discharge contact plugs and a plurality of discharge conductive patterns are alternately stacked, and a cell array structure on the common source plate. The discharge contact plugs extend parallel to the upper surface of the lower substrate, and the conductive patterns extend parallel to the upper surface of the lower substrate.

Alternatively or additionally according to some example embodiments, there is provided a semiconductor device comprising a lower substrate, an active region on the lower substrate, a common source plate spaced apart from an upper surface of the lower substrate in a vertical direction, the common source plate at least partly overlapping the upper surface of the lower substrate, a discharge structure directly connecting the common source plate and the active region in the vertical direction, the discharge structure having a wall shape extending in a first direction parallel to the upper surface of the lower substrate, and a cell array structure on the common source plate. A length of the discharge structure in the first direction is greater than a width of the discharge structure in a second direction parallel to the upper surface of the lower substrate and perpendicular to the first direction.

Alternatively or additionally according to some example embodiments, there is provided a semiconductor device comprising a lower substrate, a peripheral circuit including a peripheral circuit pattern and a multilayer wiring structure on the lower substrate, an active region on the lower substrate, the active region including N-type impurities, a common source plate spaced apart from an upper surface of the lower substrate in a vertical direction, the common source plate at least partly overlapping the upper surface of the lower substrate, a discharge structure directly connecting the common source plate and the active region in the vertical direction, the discharge structure including a plurality of discharge contact plugs and a plurality of discharge conductive patterns alternately stacked, a gate stack on the common source plate, the gate stack including a plurality of gate patterns spaced apart from each other in the vertical direction and an insulation layer interposed between the gate patterns, and a channel structure passing through the gate stack in the vertical direction, the channel structure contacting an upper portion of the common source plate. The discharge conductive patterns and the discharge contact plugs extend in a first direction parallel to the upper surface of the lower substrate such that the first direction is a long axis direction of each of discharge conductive patterns and the discharge contact plugs, and a length of each of the discharge contact plugs in the first direction is greater than a width of each of the discharge conductive patterns contacting each discharge contact plugs.

In the vertical memory device according to various example embodiments, the discharge contact plugs and the discharge conductive patterns included in the discharge structure may have a shape extending in the long axis direction, so that a volume of the discharge structure serving as a path for discharging may be increased. As the volume of the path for discharging may be increased, discharging efficiency may be increased. Therefore, the vertical memory device may have a high reliability and/or improved or excellent electrical characteristics.

DETAILED DESCRIPTION

Hereinafter, various example embodiments will be described in detail with reference to the accompanying drawings.

Hereinafter, a direction parallel to a surface of a substrate may be referred to as a first direction X, and a direction parallel to the surface of the substrate and perpendicular to the first direction X may be referred to as a second direction Y. In addition, a direction perpendicular to the surface of the substrate may be referred to as a vertical direction Z.

FIG.1is a block diagram of a semiconductor device according to various example embodiments.FIG.2is an equivalent circuit diagram of a memory cell array in the semiconductor device according to various example embodiments.FIG.3is a schematic perspective view of a vertical memory device having a cell-over-periphery (COP) structure according to various example embodiments.

Referring toFIGS.1to3, a semiconductor device10may include a memory cell array20and a peripheral circuit30. The memory cell array20may include a plurality of memory cell blocks BLK1, BLK2, . . . , BLKn. A plurality of memory cells may be included in each of the plurality of memory cell blocks BLK1, BLK2, . . . , BLKn, for example, the same number of memory cells may be included in each of the plurality of memory cell blocks BLK1, BLK2, . . . , BLKn. The plurality of memory cells may include at least a portion of a bit line BL, at least a portion of a word line WL, at least a portion of a string select line SSL, and at least a portion of ground select line GSL, and the memory cells may be electrically connected to the peripheral circuit30.

The peripheral circuit30may include, e.g. a row decoder32, a page buffer34, a data input/output circuit36, a control logic38and a common source line CSL driver39, etc. Although not shown inFIG.1, the peripheral circuit30may further include various circuits such as a voltage generating circuit for generating various voltages necessary for or used for an operation of the semiconductor device10, an error correcting circuit for correcting errors of read data from the memory cell array20, and input/output interfaces, etc.

The memory cell array20may be connected to a page buffer34through the bit line BL, and may be connected to a row decoder32through the word line WL, the string select line SSL and the ground select line GSL. In the memory cell array20, the plurality of memory cells included in the plurality of memory cell blocks BLK1, BLK2, . . . , BLKn may be or may include memory cells of a NAND flash memory device (however, example embodiments are not necessarily limited thereto). The memory cell array20may be a three-dimensional memory cell array. The three-dimensional memory cell array may include a plurality of memory cell strings, and each of the plurality of memory cell strings may include or be connected to the plurality of memory cells connected to the plurality of word lines WL vertically stacked.

As shown inFIG.2, the memory cell array20may include the plurality of bit lines BL1, BL2, . . . , BLn, the plurality of word lines WL1, WL2, . . . , WLn−1, WLn, at least one string select line SSL, at least one ground select line GSL and a common source line CSL. A plurality of memory cell strings MS may be disposed between the plurality of bit lines BL and a common source line CSL.

In various example embodiments, the number of memory cell blocks may be different from the number of bit lines and/or the number of word lines. In various example embodiments, the number of word lines in each of the memory cell blocks may be the same as or different from the number of bit lines. In various example embodiments, the number of string select lines in each memory cell block may be the same as or different from the number of bit lines in the memory cell block.

FIG.2illustrates a case in which two string selection lines SSL are included in each memory cell string MS. However, a structure of the memory cell structure MS may not be limited thereto. For example, each of memory cell strings MS may include one string select line SSL.

Each of memory cell strings MS may include or be connected to a string select transistor SST, a ground select transistor GST and the plurality of memory cell transistors MC1, MC2, . . . , MCn−1, MCn. A drain region of the string select transistor SST may be connected to the bit line BL, and a source region of the ground select transistor GST may be connected to the common source line CSL. The common source line CSL may be or may correspond to a region where the source regions of the plurality of ground select transistors GST are commonly connected.

The string select transistor SST may be connected to the string select line SSL, and the ground select transistor GST may be connected to the ground select line GSL. The plurality of memory cell transistors MC1, MC2, . . . , MCn−1, and MCn may be connected to the plurality of word lines WL, respectively.

The peripheral circuit30may receive one or more of an address signal ADDR, a command signal CMD, and a control signal CTRL from an outside of the semiconductor device10. The peripheral circuit30may transmit and/or receive data from an external device.

The row decoder32may select at least one of the plurality of memory cell blocks BLK1, BLK2, . . . , BLKn in response to an external address signal ADDR, and then may select the word line WL, the string selection line SSL and the ground selection line GSL in the selected memory cell block. The row decoder32may transmit a voltage for an operation, such as a program operation, an erase operation, or a read operation, of the selected word line WL in the memory cell block.

The page buffer34may be connected to the memory cell array20through the bit line BL. The page buffer34may operate as a write driver during a programming operation, and may apply a voltage according to write data to the bit line BL in the memory cell array20. The page buffer34may operate as a sense amplifier during a read operation, and may sense the data stored in the memory cell array20. The page buffer34may operate according to the control signal PCTL provided from a control logic38.

The data input/output circuit36may be connected to the page buffer34through data lines DLs. The data input/output circuit36may receive data from a memory controller (not shown) during the programming operation, and the data input/output circuit36may transfer a program data based on a column address C_ADDR provided from the control logic38to the page buffer34. The data input/output circuit36may transfer a read data stored in the page buffer based on a column address C_ADDR provided from the control logic38to the memory controller, during a read operation.

The data input/output circuit36may transfer the address signal or the command signal to the control logic38or the row decoder32. The peripheral circuit30may further include an Electro Static Discharge (ESD) circuit and/or a pull-up/pull-down driver (not illustrated).

The control logic38may receive the command signal CMD and the control signal CTRL from the memory controller. The control logic38may provide a row address R_ADDR to the row decoder32and a column address C_ADDR to the data input/output circuit36. The control logic38may generate various internal control signals used in the semiconductor device10in response to the control signal CTRL. For example, the control logic38may adjust voltage levels provided to the word line WL and the bit line BL when a memory operation, such as a program operation and/or an erase operation, is performed.

The common source line driver39may be connected to the memory cell array20through the common source line CSL. The common source line driver39may apply a common source voltage (e.g., a power supply voltage) and/or a ground voltage based on the control of the control logic38to the common source line CSL. In various example embodiments, the common source line driver39may be disposed under the memory cell array20. The common source line driver39may vertically overlap at least a portion of the memory cell array20.

The semiconductor device may further include a discharge structure (refer toFIG.5200) for preventing or reducing the likelihood of and/or impact from arcing due to accumulation of electrical charges by plasma processes in manufacturing the semiconductor device. The semiconductor device may have a COP structure as shown inFIG.3, for high integration; however, example embodiments are not limited thereto.

As shown inFIG.3, the semiconductor device10may include a lower substrate100, a peripheral circuit structure PCS, a common source plate110and a cell array structure CAS.

The peripheral circuit structure PCS may be on and/or at least partly in the lower substrate100. The peripheral circuit structure PCS may include the peripheral circuit30and the discharge structure (refer toFIG.5,200). The common source plate110may be on the peripheral circuit structure PCS, and the cell array structure CAS may be on the common source plate110.

The cell array structure CAS may include the plurality of memory cell blocks BLK1, BLK2, . . . , BLKn. Each of the plurality of memory cell blocks BLK1, BLK2, . . . , BLKn may include three-dimensionally arranged memory cells. The plurality of cell blocks may constitute one mat (MAT).

The discharge structure200may be disposed between the lower substrate100and the common source plate110, and may electrically connect the lower substrate100and the common source plate110to each other.

The discharge structure200may include a metal, and may serve a or be configured for path for moving of charges from the common source plate110to the lower substrate100. Accordingly, charges, such as triboelectric charges and/or charges generated by a plasma process such as a plasma process used in the fabrication of the memory device such as but not limited to chemical vapor deposition (CVD) processes and/or dry etching processes, may be discharged from the common source plate110to the lower substrate100through the discharge structure200. Therefore, the charges may not be accumulated in the common source plate110or may be less likely to be accumulated in the common source plate.

A portion of the lower substrate100contacting the discharge structure200may serve as an impurity region, so that the impurity region may function as and/or operate as a Zener diode.

FIG.4is a plan view illustrating a portion of a vertical memory device according to various example embodiments.FIG.5is a perspective view schematically illustrating a portion of a vertical memory device according to various example embodiments.FIGS.6and7are cross-sectional views of a portion of a vertical memory device according to various example embodiments.FIGS.8and9are a plan view and a perspective view, respectively, illustrating a portion of a vertical memory device according to various example embodiments.FIGS.10and11are a plan view and a perspective view, respectively, illustrating a portion of a vertical memory device according to some example embodiments.

FIG.4is a plan view illustrating a MAT region in the vertical memory device.FIG.6is a cross-sectional view taken along line I-I′ and line III-III′ ofFIG.4.FIG.7is a cross-sectional view taken along line II-II ofFIG.4.FIGS.8and9illustrate discharge structures.FIGS.10and11illustrate discharge structures.FIG.5illustrates channel structures on a common source plate.

Referring toFIGS.4to9, a semiconductor device10may include a peripheral circuit structure on a lower substrate100, a common source plate110on the peripheral circuit structure, and a cell array structure CAS on the common source plate110.

The common source plate110may be spaced apart from an upper surface of the lower substrate100in the vertical direction, and may overlap or at least partly overlap the upper surface of the lower substrate100. A plurality of MAT regions12may be disposed on the common source plate110constituting or included in one semiconductor chip. InFIG.4, only one MAT region may be shown for simplicity. However, in various example embodiments, the plurality of MAT regions12may be arranged in the one memory chip.

The lower substrate100may be or may include a semiconductor substrate. For example, the lower substrate100may include one or more of Si, Ge, or SiGe, and may or may not be doped with impurities such as but not limited to boron.

The peripheral circuit structure may include a peripheral circuit and the discharge structure200. The lower substrate100may include a first region A for forming the peripheral circuit and a second region B for forming the discharge structure200.

An isolation pattern54may be formed on the lower substrate100, and a region where the isolation pattern54is not formed may be defined as an active region. A first active region100amay be positioned on the first region A of the lower substrate100, and a second active region100bmay be positioned on the second region B of the lower substrate100.

A peripheral circuit pattern and a multilayer wiring structure68electrically connected to the peripheral circuit pattern may be disposed on the first region A of the lower substrate100. The discharge structure200may be disposed on the second region B of the lower substrate100.

The peripheral circuit pattern and the multilayer wiring structure68may configure various circuits included in the peripheral circuit30described with reference toFIG.1.

In various example embodiments, the peripheral circuit pattern may include a plurality of passive devices such as but not limited to resistors and/or capacitors and/or inductors, and/or active devices such as but not limited to diodes and/or transistors, constituting or included in the peripheral circuit. Each of the plurality of transistors may include a lower gate50aand second impurity regions58in the first active region100aadjacent to both sides of the lower gate50a. Each of the impurity regions58may serve as a source region or a drain region of the transistor.

Although the plurality of transistors are illustrated as being planar, example embodiments are not limited thereto, and one or more of the plurality of transistors may be three-dimensional. Additionally or alternatively, although the plurality of transistors are illustrated as extending in the X direction, example embodiments are not limited thereto, and one or more of the plurality of transistors may extend in the Y direction.

A lower insulating interlayer70having multi-layers may cover the lower substrate100including the first and second regions A and B and the plurality of transistors.

The multilayer wiring structure68may be disposed in the lower insulating interlayer70on the first region A. The lower insulating interlayer70may cover the multilayer wiring structure68. In various example embodiments, the multilayer wiring structure68may be electrically connected to the plurality of transistors.

The multilayer wiring structure68may include a plurality of lower contact plugs60a,60band60cand a plurality of lower conductive patterns62a,62band62c. Although three wiring levels are illustrated in the multilayer wiring structure68, example embodiments are not limited thereto. Hereinafter, one lower contact plug may be a lower contact plug positioned at one level, and one lower insulating interlayer may be a lower insulating interlayer at one level. In various example embodiments, one lower contact plug may pass through one lower insulating interlayer. The one lower conductive pattern may contact an upper surface of the one lower contact plug. For example, the multilayer wiring structure may include at least the lower contact plug60adisposed at a lowermost level and the lower conductive pattern62cdisposed at an uppermost level.

Each of the lower contact plugs60a,60band60cmay be selectively connected to ones of the plurality of transistors and the plurality of lower conductive patterns62a,62band62c.

The plurality of lower contact plugs60a,60band60cand the plurality of lower conductive patterns62a,62band62cmay include metal. In various example embodiments, the plurality of lower contact plugs60a,60band60cand the plurality of lower conductive patterns62a,62band62cmay independently include tungsten. In some example embodiments, at least one of the plurality of lower contact plugs60a,60band60cand the plurality of lower conductive patterns62a,62band62cmay independently include polysilicon.

In some example embodiments, the plurality of lower contact plugs60a,60band60cand the plurality of lower conductive patterns62a,62band62cmay include the same material. In some example embodiments, the plurality of lower contact plugs60a,60band60cand the plurality of lower conductive patterns62a,62band62cmay include different materials to each other.

Hereinafter, the multilayer wiring structure68including three lower contact plugs60a,60band60cand three lower conductive patterns62a,62band62cmay be described. In addition, the lower insulating interlayers70including first to seventh lower insulating interlayers70a,70b,70c,70d,70e,70fand70gmay be described. The multilayer wiring structure68may include a first lower contact plug60a, a first lower conductive pattern62a, a second lower contact plug60b, a second lower conductive pattern62b, a third lower contact plug60cand a third lower conductive pattern62cstacked. However, the number of patterns and/or the number of contact plugs included in the multilayer wiring structure68may not be limited thereto.

In some example embodiments, the transistors and the multilayer wiring structure68may be configured as the row decoder32, the page buffer34, the data input/output circuit36, the control logic38and common source line driver39, etc.

The discharge structure200may be described with reference toFIGS.6and8to11.

Referring toFIGS.6and8to11, an entire surface of the second region B in the lower substrate100may serve as or correspond to the second active region100b. The second active region100bmay include, e.g., be doped with N-type impurities, and a bulk lower substrate below the second active region100bmay include, e.g., be doped with P-type impurities. Accordingly, the second active region100bmay form or correspond to a P-N junction, so that the second active region100bmay serve as a zener diode D1.

A bottom of the discharge structure200may contact (e.g., directly contact) an upper surface of the second active region100b. An upper surface of the discharge structure200may contact (e.g., directly contact) a lower surface of the common source plate110. The discharge structure200may be directly connected with second active region100band the common source plate110in the vertical direction Z. Accordingly, the discharge structure200may serve as a path for discharging electrical charges, for example generated by an arcing such as arcing from one or more of triboelectricity or plasma processing.

The discharge structure200may be formed in the lower insulating interlayers70on the second region B.

The discharge structure200may have a structure in which the plurality of discharge runners or discharge contact plugs64a,64b,64cand64dand the plurality of discharge conductive patterns66a,66band66care alternately stacked. The discharge structure200may be formed by processes the same as processes used for forming the multilayer wiring structure68together. The discharge structure200may include a number of runners or contact plugs that is one more than the number of contact plugs included in the multilayer wiring structure68. For example, the discharge structure200may include at least a discharge contact plug64apositioned at a lowermost level and a discharge contact plug64dpositioned at an uppermost level.

The discharge conductive patterns66a,66band66cincluded in the discharge structure200may be positioned at the same level as the lower conductive patterns62a,62band62cincluded in the multilayer wiring structure68, respectively. The discharge conductive patterns66a,66band66cincluded in the discharge structure200may include the same material as (e.g., may be formed at the same time as) the lower conductive patterns62a,62band62cincluded in multilayer wiring structure68positioned at the same level, respectively.

Ones of the discharge contact plugs64a,64band64cincluded in the discharge structure200may be positioned at the same level as the lower contact plugs60a,60band60cincluded in the multilayer wiring structure68, respectively. An uppermost discharge contact plug64din the discharge structure200may be positioned higher than a top surface of the multilayer wiring structure68, and may contact a lower surface of the common source plate110.

The discharge contact plugs64a,64band64cincluded in the discharge structure200may include a material that is the same as a material of the lower contact plugs60a,60band60cincluded in the multilayer wiring structure68positioned at the same level, respectively, e.g., may be formed at the same time as respective ones of the low contact plugs60a,60band60c.

The plurality of discharge contact plugs64a,64b,64cand64dand the plurality of discharge conductive patterns66a,66band66cmay include metal. In some example embodiments, the plurality of discharge contact plugs64a,64b,64cand64dand the plurality of discharge conductive patterns66a,66band66cmay include tungsten. Alternatively or additionally in some example embodiments, at least one of the discharge contact plugs64a,64b,64cand64dand the discharge conductive patterns66a,66band66cmay include polysilicon.

For example, as shown inFIGS.6and7, the discharge structure200may include the first discharge contact plug64a, the first discharge conductive pattern66a, the second discharge contact plug64b, the second discharge conductive pattern66b, the third discharge contact plug64c, the third discharge conductive pattern66cand the fourth discharge contact plug64dstacked. An upper surface of the fourth discharge contact plug64dpositioned at the uppermost level may coplanar with an upper surface of an uppermost lower insulating interlayer (i.e., a seventh lower insulating interlayer70g).

In the discharge structure200, the discharge conductive patterns66a,66band66cmay extend in one direction. For example, a long axis direction and a short axis direction in each of the discharge conductive patterns66a,66band66cmay be defined, and each of the discharge conductive patterns66a,66band66cmay extend in the long axis direction (e.g., a length direction). In some example embodiments, the long axis direction of each of the discharge conductive patterns66a,66band66cmay be the same as a long axis direction of the second active region100b.

Hereinafter, the long axis direction may be the second direction Y, and the short axis direction (e.g., a width direction) may be first direction X. However, example embodiments are not limited thereto, in some example embodiments, the long axis direction may be the first direction X, and the short axis direction may be the second direction Y.

Each of the discharge contact plugs64a,64b,64cand64dmay extend in the same direction as the discharge conductive patterns66a,66band66cconnected thereto. For example, each of the discharge contact plugs64a,64b,64cand64dand each of the discharge conductive patterns66a,66band66cmay have the same long axis direction and the same short axis direction. Each of the discharge contact plugs64a,64b,64cand64dand each of the discharge conductive patterns66a,66band66cmay extend in the long axis direction. For example, each of the discharge conductive patterns66a,66band66cand each of the discharge conductive patterns66a,66band66cmay extend in the second direction Y.

A length of each of the discharge contact plugs64a,64b,64cand64din the long axis direction may be greater than a width of each of the discharge conductive patterns66a,66band66ccontacting the discharge contact plugs64a,64b,64cand64d.

Accordingly, a length of the discharge structure200in the second direction Y may be greater than a width of the discharge structure200in the first direction X. In some example embodiments, the length of the discharge structure200in the second direction Y may be twice or more than the width of the discharge structure200in the first direction X.

The discharge structure200may have a wall shape extending in the long axis direction. Since the discharge structure200has the wall shape, the discharge structure200may have a structure connected in the long axis direction without a portion being spaced apart from each other. Accordingly, the discharge structure200may have a junction area with the second active region100bthat is greater than a junction area with a second active region100bin a discharge structure including pillars having a contact plug shape spaced apart from each other. Alternatively or additionally, a volume of the discharge structure200may be increased. For example, an antenna ratio of the discharge structure200may be different than an antenna ratio of a discharge structure including pillars having a contact plug shape spaced apart from each other. Therefore, a volume of the path for discharge in the discharge structure200may increase, so that a discharge efficiency of the discharge structure200may be increased.

In some example embodiments, the discharge conductive patterns66a,66band66cmay overlap or at least partly overlap the discharge contact plugs64a,64b,64cand64dtherebelow, respectively. For example, the discharge conductive patterns66a,66band66cmay completely cover the upper surfaces of the discharge contact plugs64a,64band64ctherebelow, respectively.

In some example embodiments, as shown inFIGS.8and9, each of the discharge conductive patterns66a,66band66cmay have a first width W1in the short axis direction (e.g., the first direction, X). Each of the discharge contact plugs64a,64b,64cand64dmay have the first width W1in the first direction X.

In some example embodiments, as shown inFIGS.10and11, each of the discharge conductive patterns66a,66band66cand each of the discharge contact plugs64a,64b,64cand64dmay have different widths in the first direction X, respectively. For example, each of the discharge conductive patterns66a,66band66cmay have a first width W1in the first direction X, and each of the discharge contact plugs64a,64b,64cand64dmay have a second width W2that is less than the first width in the first direction X. Accordingly, portions of the discharge conductive patterns66a,66band66cmay protrude from sidewalls extending in the long axis direction of the discharge structure200.

In some example embodiments, each of the discharge conductive patterns66a,66band66cmay have a first length in the long axis direction, and each of the discharge contact plugs64a,64b,64cand64dmay have a length of 80% to 100% of the first length in the long axis direction. For example, as shown inFIGS.8and9, each of the discharge contact plugs64a,64b,64cand64dmay have a length substantially the same as a length of each of the discharge conductive patterns66a,66band66c. Alternatively or additionally, as shown inFIGS.10and11, each of the discharge contact plugs64a,64b,64cand64dmay have a length less than a length of each of the discharge conductive patterns66a,66band66c.

In some example embodiments, a plurality of discharge structures200may be disposed on the second active region100b. The plurality of discharge structures200may be spaced apart from each other in a direction perpendicular to the long axis direction.

An uppermost surface of the lower insulating interlayer70and an upper surface of the discharge structure200may be coplanar with each other, and may be substantially flat.

Since the discharge structure200has the wall shape extending in the long axis direction, the lower insulating interlayer70may not be interposed between the discharge contact plugs64a,64b,64cand64dand the discharge conductive patterns66a,66band66cincluded in the discharge structure200. The plurality of discharge structures200may be spaced apart from each other in the first direction. The lower insulating interlayer70may be formed in a space between the plurality of discharge structures200spaced apart from each other in a horizontal direction.

The common source plate110may be formed the uppermost surface of the lower insulating interlayer70and the upper surface of the discharge structure200. The common source plate110may be interposed between the peripheral circuit structure PCS and the cell array structure CAS. The common source plate110may function as a common source line CSL as shown inFIGS.1and2. In some example embodiments, the common source plate110may function as a source region supplying currents to vertical memory cells included in the cell array structure CAS.

In some example embodiments, the common source plate110may include a metal plate110L and a semiconductor plate110U stacked. For example, the metal plate110L may include tungsten (W), and the semiconductor plate110U may include doped polysilicon, but may not be limited thereto. In some example embodiments, the common source plate110may include only the semiconductor plate110U without the metal plate110L.

Meanwhile, a position of the discharge structure200on the lower substrate100may not be limited thereto, and may be disposed anywhere on the upper surface of the lower substrate100. However, the discharge structure200may be formed so as not to be electrically connected to the transistors and multilayer wiring structures68constituting the peripheral circuit on the lower substrate100. Therefore, the discharge structure200may be independently disposed to be spaced from the peripheral circuit. Accordingly, the discharge structure200may be disposed on the lower substrate100on which transistors and multilayer wiring structures68constituting peripheral circuit are not formed.

In some example embodiments, the second region B for forming the discharge structure200may be disposed on the lower substrate100corresponding to an edge of each of MAT region12in the chip region. (refer toFIG.4) In some example embodiments, the second region B for forming the discharge structure200may be disposed on the lower substrate100corresponding to vertex portions of MAT region12in the chip region. (refer toFIG.4)

The cell array structure CAS may be formed on the common source plate110. The cell array structure CAS may include a memory stack disposed on the common source plate110. The memory stack may include a gate stack GS and channel structures168.

The gate stack GS may include a plurality of gate patterns130extending in the horizontal direction and spaced apart in the vertical direction Z. An insulation layer134may be interposed between the common source plate110and a lowermost gate pattern130and between the plurality of gate patterns130.

A plurality of word line cut regions170may be disposed on the common source plate110. The plurality of word line cut regions170may extend in the first direction X, and may across the gate stack GS. A second filling insulation pattern174may fill each of the plurality of word line cut regions170.

A plurality of gate patterns130constituting or included in one gate stack GS may be disposed between two adjacent word line cut regions170on the common source plate110, and the plurality of gate patterns130may be stacked to overlap each other in the vertical direction Z.

Each of the gate stacks GS may extend in the first direction X. An edge in the first direction X of each of the gate stacks GS may have a stepped shape.

The plurality of gate patterns130constituting or included in the gate stack GS may include the ground selection line GSL, the plurality of word lines WL, and the string selection line SSL described with reference toFIG.3. In the gate stack GS, uppermost gate pattern130may be separated in the second direction Y, and a string selection line cut region may be between the uppermost two gate patterns130. Each of the uppermost two gate patterns130may serve as the string selection line SSL described with reference toFIG.3. An upper insulation pattern172may fill the string selection line cut region.

A plurality of channel structures168may pass through the gate stack GS, and may extend to the common source plate110in the vertical direction. A bottom of each of the channel structures168may contact the common source plate110. The plurality of channel structures168may be spaced apart from each other in the first and second directions X and Y. Each of the plurality of channel structures168may include a gate dielectric layer160, a channel pattern162, a filling insulation pattern164and a capping pattern166. The gate dielectric layer160may include a tunnel dielectric layer, a charge storage layer and a blocking dielectric layer sequentially stacked on the channel pattern162. The channel pattern162may have a cylindrical shape or a tapered shape. The filling insulation pattern164may fill an inner space of the channel pattern162. The capping pattern166may include polysilicon such as but not limited to doped polysilicon.

As the number of stacked gate patterns130increases, a height of the channel structure168in the vertical direction Z may increase significantly. In addition, an arrangement density of the channel structure168may be high, and the number of the channel structure168may increase in the MAT region.

In a plasma deposition process and/or a plasma etching process used for forming the channel structures168, electrical charges generated by the plasma may be accumulated in the common source plate110. Therefore, an arcing due to the accumulated charges in common source plate110may occur.

The arcing may be or may include a dielectric breakdown generated an electric arc according to an electric potential generated between conductors separated by an insulator.

In some example embodiments, as the discharge structure200connected to the common source plate110is formed, the accumulated charges may be discharged through a path of the discharge structure200and the lower substrate100. In some example embodiments, the substrate100may be grounded, e.g., may be chucked to a ground, for example during plasma processing, which may lead to a discharge path for accumulated charges. Therefore, the arcing may decrease. In some example embodiments, the discharge structure200may have the wall shape, and may extend in the long axis direction. Therefore, a volume of the path for the discharge may be increased, so that a discharging efficiency may be increased.

A first insulating interlayer144, a second insulating interlayer146, and a third insulating interlayer182may cover the memory stack.

Cell contact plugs184may pass through the first, second, and third insulating interlayers144,146and182, and may contact upper surfaces of edges of the gate patterns130, respectively.

A fourth insulating interlayer190may be on the third insulating interlayer182and the cell contact plug184. A first contact194amay pass through the fourth insulating interlayer190and the third insulating interlayer182, and may contact the capping pattern166of the channel structure168. A bit line196may be on the fourth insulating interlayer190and the first contact194a.

A through via192may pass through the first to third insulating interlayers144,146, and182and a lower filling insulation pattern112, and may be electrically connected to the multilayer wiring structure68included in the peripheral circuit structure. A second contact194bmay pass through the fourth insulating interlayer190, and may contact the through via192. A wiring line198may be on the fourth insulating interlayer190and the second contact194b.

In some example embodiments, the through via192may be spaced apart from the gate stack GS in the horizontal direction. In some example embodiments, the through via192may pass through the gate stack GS without contacting the gate pattern130.

The through via192may be connected to the peripheral circuit through the multilayer wiring structure68.

As described above, the vertical memory device may include the discharge structure200directly connected with the lower substrate100and the common source plate110. The discharge structure200may have the wall shape extending in the long axis direction.

The arrangement and/or the stacking structure of the discharge structure200may be variously modified. Hereinafter, some example embodiments of a semiconductor device including the modified discharge structure200may be described.

FIGS.12and13are a cross-sectional view and a perspective view, respectively, illustrating portion of a vertical memory device according to various example embodiments.

FIGS.12and13illustrate a discharge structure in the vertical memory device.

The vertical memory device may be the same as the semiconductor device described with reference toFIGS.4to9, except for the discharge structure. Therefore, only the discharge structure may be described.

Referring toFIGS.12and13, an entire surface of the second region B in the lower substrate100may serve as the second active region100b.

A discharge structure200amay have a structure in which a plurality of discharge contact plugs64a,64b,64cand64dand a plurality of discharge conductive patterns66a,66band66care alternately stacked. The discharge structure200amay be formed together by processes the same as processes for forming the multilayer wiring structure68.

In some example embodiments, a stacked structure of the plurality of discharge contact plugs64a,64b,64cand64dand the plurality of discharge conductive patterns66a,66band66cincluded in the discharge structure200amay be substantially the same as the stacked structure illustrated inFIG.9. In some example embodiments, a stacked structure of the plurality of discharge contact plugs64a,64b,64cand64dand the plurality of discharge conductive patterns66a,66band66cincluded in the discharge structure may be substantially the same as the stacked structure illustrated inFIG.11

In the discharge structure200a, each of the discharge conductive patterns66a,66band66cmay extend in one direction. For example, a long axis direction and a short axis direction in each of the discharge conductive patterns66a,66band66cmay be defined, and each of the discharge conductive patterns66a,66band66cmay extend in the long axis direction.

Each of the discharge contact plugs64a,64b,64cand64dmay extend in a direction the same as an extension direction of the discharge conductive patterns66a,66band66cconnected thereto. For example, long and short axis directions of each of the discharge contact plugs64a,64b,64cand64dmay be the same as the respective long and short axis directions of each of the discharge conductive patterns66a,66band66c. The discharge contact plugs64a,64b,64cand64dand the discharge conductive patterns66a,66band66cmay extend in the same long axis direction.

In some example embodiments, a plurality of discharge structures200amay be disposed on the second active region100b. The plurality of discharge structures200amay be spaced apart from each other in a direction perpendicular to the long axis direction (e.g., the short axis direction). Alternatively or additionally, the plurality of discharge structures200amay be spaced apart from each other in the long axis direction.

The discharge structure200amay have a wall shape, and may extend in the long axis direction. Therefore, a volume of a path for the discharge may be increased, and a charge discharging efficiency may be increased.

FIG.14is a perspective view illustrating a portion of a semiconductor device according to various example embodiments.

FIG.14illustrates a discharge structure of a vertical memory device.

The vertical memory device may be substantially the same as the vertical memory device described with reference toFIGS.4to9, except for the discharge structure. Therefore, only the discharge structure may be described.

Referring toFIG.14, an entire surface of the second region B in the lower substrate100may serve as the second active region100b.

The discharge structure200bmay have a structure in which a plurality of discharge contact plugs64a,64b,64cand64dand a plurality of discharge conductive patterns66a,66band66care alternately stacked. The discharge structure200bmay be formed together by processes the same as the process for forming the multilayer wiring structure68.

In the discharge structure200b, each of the discharge conductive patterns66a,66band66cmay extend in a long axis direction. At least one discharge conductive pattern among the discharge conductive patterns66a,66band66cmay include a cut portion, and may be spaced apart from each other in the long axis direction.

Each of the discharge contact plugs64a,64b,64cand64dmay extend in a direction the same as an extension direction of the discharge conductive patterns66a,66band66cconnected thereto. At least one of the discharge contact plugs64a,64b,64cand64dmay include a cut portion in a long axis direction, and may be spaced apart from each other in the long axis direction.

In some example embodiments, at least one of the discharge conductive pattern66a,66band66cand the discharge contact plugs64a,64b,64cand64dcontacting the discharge conductive pattern66a,66band66cmay include the cut portion in the long axis direction. The cut portion may serve as a wire passage region80penetrating the discharge structure200bin the first direction X. For example, the discharge structure200bmay have a wall shape extending in the long axis direction (e.g., the second direction), and may further include the wire passage region80passing through the wall of the discharge structure200bin a short axis direction (e.g., the first direction, X).

In the discharge structure200b, a portion where the discharge conductive patterns66a,66band66cand the discharge contact plugs64a,64b,64cand64dare spaced apart in the long axis direction may be the wire passage region80. A lower insulating interlayer70may fill the wire passage region80.

A wiring82may pass through the lower insulating interlayer70in the wire passage region80. The wiring82may be electrically insulated from the discharge structure200b. The wire82may extend in a direction (e.g., the first direction, X) perpendicular to the long axis direction.

FIGS.15and16are a cross-sectional view and a perspective view, respectively, illustrating portions of a vertical memory device according to various example embodiments.

FIGS.15and16illustrate a discharge structure of the vertical memory device.

The vertical memory device may be substantially the same as the vertical memory device described with reference toFIGS.4to9, except for the discharge structure. Therefore, only the discharge structure may be described.

Referring toFIGS.15and16, an entire surface of the lower substrate100of the second region B may serve as the second active region100b.

The discharge structure200cmay have a structure in which a plurality of discharge contact plugs64a,64b,64cand64dand a plurality of discharge conductive patterns66a,66band66care alternately stacked. The discharge structure200cmay be formed together by processes the same as processes for forming the multilayer wiring structure68.

In the plan view, each of the discharge conductive patterns66a,66band66cincluded in the discharge structure200cmay have a mesh shape including portions extending in the first direction X and portions extending in the second direction. For example, each of the discharge conductive patterns66a,66band66cmay include first openings between the portions extending in the first direction X and the portions extending in the second direction Y. The first openings may be spaced apart from each other, and may be arranged in each of the first and second directions X and Y.

Each of the discharge contact plugs64a,64b,64cand64dmay have a shape substantially the same as a shape of the discharge conductive patterns66a,66band66c. Each of the discharge contact plugs64a,64b,64cand64dmay overlap the discharge conductive patterns66a,66band66c. In the plan view, each of the discharge contact plugs64a,64b,64cand64dincluded in the discharge structure200cmay have a mesh shape including portions extending in the first direction X and portions extending in the second direction Y. Each of the discharge contact plugs64a,64b,64cand64dmay include second openings between the portions extending in the first direction X and portions extending in the second direction. The second openings may be spaced apart from each other, and may be arranged in each of the first and second directions X and Y. The second opening and the first opening may communicate with each other in the vertical direction.

FIG.16illustrates that the mesh is a square lattice of square openings; however, example embodiments are not limited thereto. For example, the mesh may be another lattice shape such as but not limited to a triangular lattice shape and/or a rectangular lattice shape. Alternatively or additionally, the openings may have a shape other than a square shape, such as but not limited to a rectangular shape that is not square.

FIGS.17and18are a cross-sectional view and a perspective view illustrating portions of a vertical memory device according to various example embodiments.

FIGS.17and18illustrate a discharge structure in the vertical memory device.

The vertical memory device may be substantially the same as the vertical memory device described with reference toFIGS.4to9, except for the discharge structure. Therefore, only the discharge structure may be described.

Referring toFIGS.17and18, an entire surface of the second region B in the lower substrate100may serve as the second active region100b.

The discharge structure200may have a structure in which a plurality of discharge contact plugs64a,64b,64cand64dand a plurality of discharge conductive patterns66a,66band66care alternately stacked. The discharge structure200cmay be formed together by processes the same as processes for forming the multilayer wiring structure68.

In the discharge structure200c, each of the discharge conductive patterns66a,66band66cmay extend in the first direction X. For example, each of the discharge conductive patterns66a,66band66cmay be disposed such that the first direction X may be the long axis direction. Each of the discharge conductive patterns66a,66band66cmay be spaced apart from each other in the second direction Y.

Each of the discharge contact plugs64a,64b,64cand64dmay extend in the second direction Y. For example, each of the discharge contact plugs64a,64b,64cand64dmay extend in a direction perpendicular to an extension direction of the discharge conductive patterns66a,66band66cconnected thereto. For example, each of the discharge contact plugs64a,64b,64cand64dmay be disposed such that the second direction Y may be a long axis direction. The plurality of discharge contact plugs64a,64b,64cand64dmay be spaced apart from each other in the first direction X.

Accordingly, the discharge contact plugs64a,64b,64cand64dand the plurality of discharge conductive patterns66a,66band66cincluded in the discharge structure200cmay be alternately disposed in the vertical direction to cross each other. In the plan view, the discharge structure200cmay have a mesh shape.

Referring toFIGS.17and18, a line width of the plurality of the discharge contact plugs64a,64b,64cand64dmay be constant or variable, and may be the same as or different from a pitch of neighboring ones of the plurality of discharge conductive patterns66a,66band66c. Alternatively or additionally, a line width of each of the plurality of the discharge contact plugs64a,64b,64cand64dmay be constant or variable and may be the same as or different from a pitch of neighboring ones of the plurality of discharge conductive patterns66a,66band66c. A line width and/or a pitch of plurality of discharge conductive patterns66a,66band66cmay be the same as or different from a respective line width and/or a pitch of the plurality of discharge contact plugs64a,64b,64cand64d.

FIGS.19to30are cross-sectional views illustrating a method of manufacturing a vertical memory device according to various example embodiments.

FIGS.19to23,28and29are cross-sectional views taken along I-I′ and III-III′ lines ofFIG.4.FIGS.24to26are cross-sectional views taken along II-II′ and III-III′ lines ofFIG.4.FIG.27is a cross-sectional view taken along line I-I′ ofFIG.4, andFIG.30is a cross-sectional view taken along line II-II′.

Referring toFIG.19, a shallow trench isolation process such as but not limited to a high-density plasma (HDP) operation may be performed on a lower substrate100to form an isolation pattern54. A region where the isolation pattern54is not formed may serve as an active region. A first active region100amay be formed in a first region A of the lower substrate100, and a second active region100bmay be formed in a second region B of the lower substrate100. The lower substrate100may have a bulk region doped with P-type impurities having low concentration. A first impurity region56may be formed by doping (e.g., implanting and/or implanting and annealing) the second active region100bwith N-type impurities.

A plurality of transistors constituting a peripheral circuit may be formed on the first region A of the lower substrate100. Each of the plurality of transistors may include a lower gate50aand second impurity regions58at the first active region100aadjacent to both sides of the lower gate50a.

A first lower insulating interlayer70amay be formed to cover the lower substrate100and the plurality of transistors on the first and second regions A and B.

The first lower insulating interlayer70aon the first and second regions A and B may be etched to form a first lower contact hole passing through the first lower insulating interlayer70aon the first region A and a first discharge contact hole passing through the first lower insulating interlayer70aon the second region B. In a plan view, the first lower contact hole may have a circular or elliptical shape, and the first discharge contact hole may have a line shape extending in the second direction Y. The second active region100bmay be exposed by a bottom of the first discharge contact hole.

A first conductive layer may be formed on the first lower insulating interlayer70ato fill the first lower contact hole and the first discharge contact hole. The first conductive layer may include a metal material, e.g., tungsten. In some example embodiments, the first conductive layer may include polysilicon.

The first conductive layer may be planarized until an upper surface of the first lower insulating interlayer70amay be exposed to form a first lower contact plug60aon the first region A and a first discharge contact plug64aon the second region B. The first discharge contact plug64amay extend in the second direction Y. That is, the second direction Y may be a long axis direction of the first discharge contact plug64a.

Referring toFIG.20, a second conductive layer may be formed on the first lower insulating interlayer70a, the first lower contact plug60aand the first discharge contact plug64a. The second conductive layer may be patterned to form a first lower conductive pattern62acovering the first lower contact plug60aon the first region A and a first discharge conductive pattern66acovering the first discharge contact64aon the second region B.

In some example embodiments, the first lower conductive pattern62amay have a line shape extending in the first direction X or the second direction Y.

The first discharge conductive pattern66amay extend in the second direction Y to completely cover the first discharge contact plug64a. In some example embodiments, a width of the first discharge conductive pattern66ain the first direction X may be substantially the same as a width of the first discharge contact plug64ain the first direction X. In some exemplary embodiments, a width of the first discharge conductive pattern66ain the first direction X may be greater than a width of the first discharge contact plug64ain the first direction X.

Referring toFIG.21, a second lower insulating interlayer70bmay be formed on the first lower insulating interlayer70ato cover the first discharge conductive pattern66aand the first lower conductive pattern62a. An upper surface of the second lower insulating interlayer70bmay be planarized.

A third lower insulating interlayer70cmay be formed on the first lower conductive pattern62a, the first discharge conductive pattern66a, and the second lower insulating interlayer70b.

The third lower insulating interlayer70cmay be etched to form a second lower contact hole passing through the third lower insulating interlayer70con the first region A and a second discharge contact hole passing through the third lower insulating interlayer70con the second region B.

In a plan view, the second lower contact hole may have a circular or elliptical shape, and the second discharge contact hole may have a line shape extending in the second direction Y. The first discharge conductive pattern66amay be exposed by a bottom of the second discharge contact hole. In some example embodiments, the second discharge contact hole may be disposed to overlap the first discharge contact hole. The first lower conductive pattern62amay be exposed by a bottom of the second lower contact hole.

A third conductive layer may be formed on the third lower insulating interlayer70cto fill the second lower contact hole and the second discharge contact hole. An upper surface of the third conductive layer may be planarized until an upper surface of the third lower insulating interlayer70cmay be exposed to form a second lower contact plug60bon the first region A and a second discharge contact plug64bon the second region B.

Referring toFIG.22, a fourth conductive layer may be formed on the third lower insulating interlayer70c, the second lower contact plug60band the second discharge contact plug64b. The fourth conductive layer may be patterned to form a second lower conductive pattern62bcovering the second lower contact plug60bin the first region A and a second discharge conductive pattern66bcovering the second discharge contact plug64bon the second region B.

The second discharge conductive pattern66bmay extend in the second direction Y to completely cover the second discharge contact plug64b. In some example embodiments, a width of the second discharge conductive pattern66bin the first direction X may be the same as a width of the second discharge contact plug64bin the first direction X. In some example embodiments, a width of the second discharge conductive pattern66bin the first direction X may be greater than a width of the second discharge contact plug64bin the first direction X.

In some example embodiments, the second discharge conductive pattern66bmay be disposed to overlap the first discharge conductive pattern66a.

Referring toFIG.23, a fourth lower insulating interlayer70dmay be formed on the third lower insulating interlayer70cto cover the second discharge conductive pattern66band the second lower conductive pattern62b. An upper surface of the fourth lower insulating interlayer70dmay be planarized.

Thereafter, the processes described with reference toFIGS.19and20may be repeatedly performed on the fourth lower insulating interlayer70d, the second lower conductive pattern62b, and the second discharge conductive pattern66b. Accordingly, the multilayer wiring structure68may be formed on the first region A of the lower substrate100and the discharge conductive structure200may be formed on the second active region100bof the lower substrate100.

According to the above process, the multilayer wiring structure68in which a plurality of lower contact plugs60a,60b, and60cand a plurality of lower conductive patterns62a,62b, and62care alternately stacked may be formed on the first region A of the lower substrate100. Alternatively or additionally, the discharge structure200in which a plurality of discharge contact plugs64a,64b,64cand64dand a plurality of discharge conductive patterns66a,66band66care alternately stacked may be formed on the second active region100bof the lower substrate100. The discharge structure200may include contact plugs one more than the contact plugs included in the multilayer wiring structure68. A plurality of lower insulating interlayers70a,70b,70c,70d,70e,70f, and70gmay be formed to cover the multilayer wiring structure68, and may fill spaces between the discharge structures200. Hereinafter, the plurality of lower insulating interlayers70a,70b,70c,70d,70e,70f, and70gmay be collectively referred to as a lower insulating interlayer70.

For example, as shown inFIG.23, the multilayer wiring structure68may include the first lower contact plug60a, the first lower conductive pattern62a, the second lower contact plug60b, the second lower conductive pattern62b, a third lower contact plug60cand a third lower conductive pattern62cstacked. The discharge structure200may include the first discharge contact plug64a, the first discharge conductive pattern66a, the second discharge contact plug64b, the second discharge conductive pattern66b, a third discharge contact plug64c, a third discharge conductive pattern66cand a fourth discharge contact plug64dstacked. An upper surface of the fourth discharge contact plug64ddisposed on an uppermost portion of the discharge structure200may be coplanar with an upper surface of an uppermost lower insulating interlayer (e.g., a seventh lower insulating interlayer70g).

The discharge structure200may have a wall shape extending in the second direction Y.

Meanwhile, patterning processes for forming the discharge contact plugs64a,64b,64c,64dand the discharge conductive patterns66a,66b,66cmay be controlled, so that a shape of the discharge structure200may be changed.

In some example embodiments, a plurality of discharge structures200extending in the second direction Y and being spaced apart to each other in the first direction X may be formed on the second active region100b.

In some example embodiments, as shown inFIGS.12and13, the plurality of discharge structures200aextending in the second direction Y and being spaced apart to each other in the first direction X and the second direction Y may be formed on the second active region100b.

In some example embodiments, in patterning processes for forming the discharge contact plugs64a,64b,64cand64dand the discharge conductive patterns66a,66band66cmay be formed the wire passage region80(refer toFIG.14) together. Accordingly, the discharge structure200bshown inFIG.14may be formed.

In some example embodiments, the discharge contact plugs64a,64b,64cand64dand the discharge conductive patterns66a,66band66cmay be patterned to have a mesh shape. In this case, the discharge structure200cshown inFIGS.15and16may be formed.

In some example embodiments, the discharge contact plugs64a,64b,64cand64dand the discharge conductive patterns66a,66band66cmay be patterned so that an extension direction (e.g., the long axis direction) of the discharge contact plugs64a,64b,64cand64dand an extension direction of the discharge conductive patterns66a,66band66cmay cross to each other. In this case, the discharge structure200dshown inFIGS.17and18may be formed.

Referring toFIG.24, a common source plate110may be formed on the multilayer wiring structure68, the discharge structure200and the seventh lower insulating interlayer70g. A portion of the common source plate110may be etched to form an opening, and a lower filling insulation pattern112may be formed to fill the opening.

The common source plate110may be disposed to overlap the lower substrate100. In some example embodiments, a horizontal area of the common source plate110may be less than a horizontal area of the lower substrate100. In some example embodiments, a metal plate110L and a semiconductor plate110U may be sequentially stacked on the lower substrate100to form the common source plate110. In some example embodiments, the common source plate110may include only the semiconductor plate110U without the metal plate110L. The semiconductor plate110U may include polysilicon.

A lower portion of the common source plate110may directly contact the discharge structure200. For example, a lower surface of the common source plate110may directly contact the fourth discharge contact plug64ddisposed at the uppermost portion of the discharge structure200.

Referring toFIG.25, a sacrificial layer structure120and a support layer122may be formed on the common source plate110and the lower filling insulation pattern112. Insulation layers134and the sacrificial layers136may be alternately and repeatedly stacked on the support layer122. The insulation layers134may include silicon oxide. The sacrificial layers136may include silicon nitride or silicon carbide. The sacrificial layers136may serve as a space for forming a plurality of gate patterns130by subsequent processes.

Portions of the insulation layers134and the sacrificial layers136A may be repeatedly etched to form a mold structure140. An edge of the mold structure140in the first direction X may have a stepped shape.

A first insulating interlayer144may be formed to cover sidewalls of the mold structure140. A second insulating interlayer146may be formed to cover the mold structure140and the first insulating interlayer144.

FIGS.26and27, portions of the second insulating interlayer146, the first insulating interlayer144, the sacrificial layer structure120, the support layer122, and the mold structure140may be etched to form channel holes150exposing an upper portion of the common source plate110.

An etching process for forming the channel holes150may include a plasma etching process. Due to high integration of the semiconductor device, the number of channel holes150formed by the plasma etching process may increase. Further, an etching depth for forming the channel holes150may increase. When the plasma etching process is performed, a high voltage may be required. Electrical charges may be accumulated in the common source plate110, during the plasma etching process.

If there is no discharge path between the common source plate110and the lower substrate100, an arcing occurs between the common source plate110and the lower substrate100due to the charges accumulated in the common source plate110. An insulation breakdown in the peripheral circuit due to the arcing may occur, and a reliability of the semiconductor device may be decreased.

However, when the plasma etching process is performed, the charges may move through the discharge structure200disposed between the common source plate and the lower substrate100, and the charges may be discharged to the lower substrate100through a zener diode of the second active region100b. Accordingly, the insulation breakdown due to the arcing may be prevented or reduced in likelihood of and/or in impact from occurring.

Referring toFIG.28, a preliminary channel structure may be formed in the channel hole150. The preliminary channel structure may include a preliminary gate dielectric layer, a channel pattern162, a filling insulation pattern164and a capping pattern166.

An upper portion of the mold structure140may be etched to form a string selection line cut region, and then an upper insulation pattern172may be formed to fill the string selection line cut region.

The second insulating interlayer146, the first insulating interlayer144, and the mold structure140may be etched to form a plurality of word line cut regions170. Each of the word line cut regions170may pass through the second insulating interlayer146, the first insulating interlayer144and the mold structure140. An upper portion of the common source plate110may be exposed by bottoms of the word line cut regions170.

The sacrificial layer structure120may be removed using etchant supplying through the word line cut regions170to form a first gap. The preliminary gate dielectric layer exposed by the first gap may be etched to form a gate dielectric layer160. Accordingly, the gate dielectric layer160may be divided into an upper gate dielectric layer and a lower gate dielectric layer. A channel structure168including a gate dielectric layer160, the channel pattern162, the filling insulation pattern164and the capping pattern166may be formed in the channel hole150.

A conductive material may fill the first gap to form a channel connection pattern180. The channel connection pattern180may include, e.g., polysilicon. The channel connection pattern180may connect channel patterns162in adjacent channel structures168to each other, and channel connection pattern180the may connect the channel patterns162and the common source plate110to each other.

Thereafter, the sacrificial layers in the mold structure140may be removed to form second gaps. Gate patterns130may be formed in the second gaps, respectively.

Accordingly, a gate stack GS in which the insulation layers134and the gate patterns130are alternately and repeatedly stacked may be formed on the common source plate110.

Thereafter, a second filling insulation pattern174may be formed to fill the word line cut region170.

Referring toFIGS.29and30, a third insulating interlayer182may be formed on the second insulating interlayer146. Cell contact plugs184may be formed through the third insulating interlayer182, the second insulating interlayer146, and the first insulating interlayer144. The cell contact plugs184may contact step portions of gate patterns130, respectively.

Portions of the third insulating interlayer182, the second insulating interlayer146, the first insulating interlayer144, the lower filling insulation pattern112and the lower insulating interlayer70may be etched to form a through via hole exposing an upper surface of the multilayer wiring structure68. In some example embodiments, an upper surface of an uppermost lower conductive pattern may be exposed by a lower surface of the through via hole.

In some example embodiments, the through via hole may be formed to be spaced apart from the gate stack GS in a horizontal direction. In some example embodiments, some through via holes may be formed to pass through the gate stack GS without contacting the gate patterns130.

Then, a conductive material may fill the through via hole to form a through via192.

A fourth insulating interlayer190may be formed on the third insulating interlayer182, the cell contact plugs184and the through vias192.

A first contact194acontacting the capping pattern166in the channel structure168and a second contact194bcontacting the through via192may be formed through the fourth insulating interlayer190and the third insulating interlayer182. In addition, a bit line196may be formed on the first contact194a. A wiring line198may be formed on the second contact194b.

By performing the above processes, a vertical memory device may be manufactured.

FIG.31is a cross-sectional view of a vertical memory device according to various example embodiments.

FIG.31is a cross-sectional view taken along the line I-I′ and the line III-III′ ofFIG.4.

The semiconductor device may be substantially the same as the semiconductor device described with reference toFIG.6, except for a discharge structure. Therefore, only the discharge structure may be described.

The discharge structure210may include one conductive material extending in the second direction Y. That is, the discharge structure210may have a structure in which a conductive material is filled in a trench202extending in the second direction Y. The discharge structure210may be formed by separate processes, after forming the multilayer wiring structure68.

In some example embodiments, as an arrangement similar to that ofFIG.9, a plurality of discharge structures210extending in the second direction Y and being spaced apart in the first direction X may be formed on the second active region100b. In some example embodiments, as an arrangement similar to that ofFIG.12, a plurality of discharge structures210extending in the second direction may be spaced apart from each other in each of first and second directions X and Y on the second active region100b.

FIGS.32and33are cross-sectional views illustrating a method of manufacturing a vertical memory device according to various example embodiments.

Referring toFIG.32, a first active region100amay be formed on the first region A of the lower substrate100, and a second active region100bmay be formed on the second region B of the lower substrate100.

A plurality of transistors constituting a peripheral circuit may be formed on the first region A of the lower substrate100.

A multilayer wiring structure68may be formed on the first region A of the lower substrate100. In addition, lower insulating interlayers70may be formed to cover the multilayer wiring structure68.

When the multilayer wiring structure68is formed on the first region A of the lower substrate100, the discharge structure may not be formed on the second region B of the lower substrate100. For example, the lower insulating interlayers70may cover the second region B of the lower substrate100.

For example, the multilayer wiring structure68in which a plurality of lower contact plugs60a,60b, and60cand a plurality of lower conductive patterns62a,62b, and62care alternately stacked on the first region A of the lower substrate100. First to seventh lower insulating interlayers70a,70b,70c,70d,70e,70f, and70gmay be formed on the first region A of the lower substrate100to cover the multilayer wiring structure68. The first to seventh lower insulating interlayers70a,70b,70c,70d,70e,70f, and70gmay be formed on the second active region100bof the lower substrate100.

Referring toFIG.33, the first to seventh lower insulating interlayers70a,70b,70c,70d,70e,70f, and70gon the second region B of the lower substrate100may be etched to form a trench202exposing the second active region100b. The trench202may extend in the second direction Y. The trench202may define a region where a discharge structure is formed.

A conductive layer may be formed on the seventh lower insulating interlayer70gto fill the trench202. The conductive layer may be planarized until an upper surface of the seventh lower insulating interlayer70gmay be exposed to form the discharge structure210filling the trench202.

Thereafter, the same processes as described with reference toFIGS.24to30may be performed to manufacture the vertical memory device shown inFIG.31.

FIG.34is a diagram schematically illustrating an electronic system including a semiconductor device according to various example embodiments.

Referring toFIG.34, an electronic system1000may include a semiconductor device1100and a controller1200electrically connected to the semiconductor device1100. The electronic system1000may be a storage device including one or a plurality of semiconductor devices1100or an electronic device including the storage device. For example, the electronic system1000may be a solid state drive (SSD) device including one or a plurality of semiconductor devices1100, a universal serial bus (USB), a computing system, a medical device, or a communication device.

The semiconductor device1100may be a nonvolatile memory device. As described above, the semiconductor device1100may be a vertical memory device including the discharge structure having the wall shape (refer toFIG.5,200). The semiconductor device1100may include a first structure1100F and a second structure1100S on the first structure1100F. The first structure1100F may be a peripheral circuit structure including a decoder circuit1110, a page buffer1120, and a logic circuit1130. The discharge structure may be included in the peripheral circuit structure.

The second structure1100S includes a bit line BL, a common source line CSL, word lines WL, first and second gate upper lines UL1and UL2, and first and second gate lower lines LL1and LL2, and memory cell strings CSTR between the bit line BL and the common source line CSL.

In the second structure1100S, each of the memory cell strings CSTR may include lower transistors LT1and LT2adjacent to the common source line CSL, upper transistors UT1and UT2adjacent to the bit line BL, and a plurality of memory cell transistors MCT between the lower transistors LT1and LT2and the upper transistors UT1and UT2. The number of lower transistors LT1and LT2and the number of upper transistors UT1and UT2may be variously modified.

In some example embodiments, the upper transistors UT1and UT2may include string select transistors, and the lower transistors LT1and LT2may include ground select transistors. The lower gate patterns LL1and LL2may be gate electrodes of the lower transistors LT1and LT2, respectively. The word lines WL may be gate electrodes of the memory cell transistors MCT, and the upper gate patterns UL1and UL2may be gate electrodes of the upper transistors UT1and UT2, respectively.

In some example embodiments, the lower transistors LT1and LT2may include a lower erase control transistor LT1and a ground select transistor LT2connected in series. The upper transistors UT1and UT2may include a string select transistor UT1and an upper erase control transistor UT2connected in series. At least one of the lower erase control transistor LT1and the upper erase control transistor UT1may performs an erase operation of data stored in the memory cell transistors MCT using a gate induce drain leakage (GIDL) phenomenon.

The common source line CSL, the first and second lower gate patterns LL1and LL2, the word lines WL, and the first and second upper gate patterns UL1and UL2may be electrically connected to the decoder circuit through the first connection wirings1115extending from the first structure1100F to the second structure1100S. The bit lines BL may be electrically connected to the page buffer1120through second connection wirings1125extending from the first structure1100F to the second structure1100S.

In the first structure1100F, the decoder circuit1110and the page buffer1120may control at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit1110and the page buffer1120may be controlled by the logic circuit1130. The semiconductor device1100may communicate with the controller1200through the input/output pad1101electrically connected to the logic circuit1130. The input/output pad1101may be electrically connected to the logic circuit1130through an input/output connection wire1135extending from the first structure1100F to the second structure1100S.

The controller1200may include a processor1210, a NAND controller1220, and a host interface1230. In some example embodiments, the electronic system1000may include a plurality of semiconductor devices1100. In this case, the controller1200may control the plurality of semiconductor devices1000.

The processor1210may control overall operations of the electronic system1000including the controller1200. The processor1210may operate according to predetermined firmware and may access the semiconductor device1100by controlling the NAND controller1220. The NAND controller1220may include a NAND interface1221that processes communication with the semiconductor device1100. A control command for controlling the semiconductor device1100, write data in the memory cell transistors MCT of the semiconductor device1100, and read data from the memory cell transistors MCT of the semiconductor device1100may be transmitted by the NAND interface1221.

A host interface1230may provide a communication function between the electronic system1000and an external host. When the control command is received from an external host through the host interface1230, the processor1210may control the semiconductor device1100in response to the control command.

Any of the elements and/or functional blocks disclosed above may include or be implemented in processing circuitry such as hardware including logic circuits; a hardware/software combination such as a processor executing software; or a combination thereof. For example, the processing circuitry more specifically may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc. The processing circuitry may include electrical components such as at least one of transistors, resistors, capacitors, etc. The processing circuitry may include electrical components such as logic gates including at least one of AND gates, OR gates, NAND gates, NOT gates, etc.

While inventive concepts have been shown and described with reference to various example embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made thereto without departing from the spirit and scope of inventive concepts as set forth by the following claims. Furthermore example embodiments are not necessarily mutually exclusive with one another. For example, some example embodiments may include one or more features described with reference to one or more figures, and may also include one or more other features described with reference to one or more other figures.