System clock synchronization circuit

A system clock synchronization circuit according to the present invention includes: a first synchronization and timing delay circuit synchronizing an input clock with a system clock and sending out a first signal which is obtained by delaying the synchronized signal by a first delay amount; an input data latching means for latching input data which changes at a first changing point of the input clock, the latching being in synchronization with a second changing point of the input clock; an input enable signal latching means for latching in synchronization with the input clock an input enable signal which is active when the input data is valid and inactive when the input data is invalid; and a mask signal generation circuit generating in synchronization with the first signal a mask signal which has a prescribed pulse width.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a system clock synchronization circuit, and more particularly, to a system synchronization circuit which, even in the case where noise is superimposed on the clock signal received, is capable of supplying correct input data and a correct input enable signal in synchronization with the system clock, which are to be supplied to circuits downstream of the system clock synchronization circuit comprising a digital broadcast reception device.

2. Description of the Related Art

As illustrated inFIG. 12, a digital broadcast reception device includes: a tuner121which receives a broadcast signal and selects a channel; an A/D converter122A which converts an output signal from the tuner121to a digital signal; a demodulation circuit122B which demodulates a digital signal from the A/D converter122A; an error correction circuit122C which corrects error data created in the transmission paths; buffers123A,123B and123C; a system clock synchronization circuit124; a stream separation circuit125; and an MPEG decoder126.

Here, the A/D converter122A, the demodulation circuit122B and the error correction circuit122C constitute a reception signals preprocessing circuit122, which sends out reception data Sdata′, a reception enable signal Sen′ and reception clock CLK′.

The reception data Sdata′, the reception enable signal Sen′ and the reception clock CLK′ are driven by the buffers123A,123B and123C, which momentarily come to have high impedance on the rising and the falling edges, and enter the system clock synchronization circuit124as input data Sdata, an input enable signal Sen and input clock CLK, respectively.

The system clock synchronization circuit124takes in the input data Sdata, the input enable signal Sen, the input clock CLK and the system clock SCLK, and sends out output data Vdata which is obtained by synchronizing the input data with the system clock SCLK and an output enable signal Ven which is synchronized with the system clock SCLK.

The stream separation circuit125takes in the output data Vdata and the output enable signal Ven and separates multiplex stream data into individual stream data, which is then decoded by the MPEG decoder126according to the MPEG format.

Next, the operation of the system clock synchronization circuit124illustrated inFIG. 12will be described more specifically with reference to a timing chart illustrated in FIG.13.

The reception data Sdata′ and the reception enable signal Sen′ are sent out from the reception signals preprocessing circuit122in such a manner that they are synchronized with the reception clock CLK′ and change on the falling edge of the reception clock CLK′. That is, the reception data Sdata′ and the reception enable signal Sen′ represent data in units of one reception clock CLK′.

The reception data Sdata′ includes valid data which is used by the MPEG decoder126during decoding and invalid data which is on the other hand discarded. InFIG. 13, the invalid data is designated by hatched lines stroked down to the lower left. When the reception enable signal Sen′ becomes active, that is, is set as “1” in the case ofFIG. 13, the valid data is sent out from the reception signals preprocessing circuit122. When the reception enable signal Sen′ becomes inactive, that is, is set as “0” in the case ofFIG. 13, the invalid data is sent out from the reception signals preprocessing circuit122. Hatched lines stroked down to the lower left appearing in the input data Sdata and the output data Vdata also designate invalid data.

InFIG. 13, when the reception enable signal Sen′ synchronizes to the falling edge of the reception clock CLK′ and becomes “1” at time t2, the reception data Sdata′ changes from invalid data to valid data1, and this valid data1is driven by the buffer123A and enters the system clock synchronization circuit124as the input data Sdata. Similarly, the reception enable signal Sen′ which becomes “1” at time t2is driven by the buffer123B and enters the system clock synchronization circuit124as the input enable signal Sen with a delay due to the buffer123B.

Next, at time t3, synchronizing to the rising edge of the input clock CLK, the system clock synchronization circuit124takes in the valid data1. Then at time t4, synchronizing to the system clock SCLK, the system clock synchronization circuit124sends out this data to the stream separation circuit125as the output data Vdata.

The output enable signal Ven which rises to “1” at time t4is generated by the system clock synchronization circuit124as a pulse signal which keeps “1” for one cycle duration of the system clock SCLK and is sent out to the stream data separation circuit125while synchronizing to the system clock SCLK.

Similarly, at time t6, synchronizing to the rising edge of the input clock CLK, the system clock synchronization circuit124takes in valid data2and, synchronizing to the system clock SCLK at time t7, sends out this data to the stream separation circuit125as the output data Vdata.

The output enable signal Ven which rises to “1” at time t7is generated by the system clock synchronization circuit124as a pulse signal which keeps “1” for one cycle duration of the system clock SCLK and sent out to the stream data separation circuit125while synchronizing to the system clock SCLK.

As described above, the input data Sdata, the input enable signal Sen and the input clock CLK are synchronized to the system clock SCLK, and are sent out from the system clock synchronization circuit124to the stream separation circuit125as the output data Vdata and the output enable signal Ven, both of which have been synchronized to the system clock SCLK.

Next, details of the system clock synchronization circuit124will be described with reference to FIG.14.

The system clock synchronization circuit124illustrated inFIG. 14comprises: a flip-flop circuit141which takes in the input enable signal Sen and operates in synchronization with the input clock CLK; a flip-flop circuit142which takes in the input data Sdata and operates in synchronization with the input clock CLK; an OR gate143which takes in the reset signal as one input; a synchronization circuit144which sends out a signal S2which is obtained by synchronizing a signal S1sent out from the flip-flop circuit141with the system clock signal SCLK; a mask signal generation circuit145which takes in the signal S2and generates a mask signal S5having a pulse width of one cycle duration of the system clock SCLK; a flip-flop circuit146which takes in the mask signal S5and sends out the output enable signal Ven while synchronizing to the system clock SCLK; and a write enable flip-flop circuit147which takes in the mask signal S5at the write enable terminal we, takes in the output signal S6from the flip-flop circuit142and sends out the output data Vdata while synchronizing to the system clock SCLK. The mask signal generation circuit145sends out the mask signal S5to the OR gate143and, when the mask signal S5assumes the value “1”, resets the flip-flop circuit141through the OR gate143.

Here, if the mask signal S5is “1”, then the write enable flip-flop circuit147operates as a typical flip-flop circuit, and if “0”, then it does not latch input data but keeps previous data. Moreover, a reset signal Rset becomes active, resetting the whole system, before the start of the reception by a digital broadcast reception device. The reset signal is cancelled later.

Next, an example of the mask signal generation circuit145will be described with reference to FIG.15. Here, the synchronization circuit144ofFIG. 14is constituted of the flip-flop circuit1441illustrated in FIG.15.

The mask signal generation circuit145illustrated inFIG. 15comprises:a flip-flop circuit1451which sends out a signal S3which is obtained by synchronizing the signal S2with system clock SCLK from the flip-flop circuit1441;a flip-flop circuit1452which sends out a signal S4which is obtained by synchronizing, the signal S3with system clock SCLK from the flip-flop circuit1451; an inverter1453; and an AND gate1454.

Here, the flip-flop circuit1452, the inverter1453and the AND gate1454generate a mask signal S5which synchronizes to the rising edge of the signal S3and has a pulse width of one cycle duration of the system clock SCLK.

Next, the normal operation of the system clock synchronization circuit124illustrated inFIGS. 14 and 15will be described with reference to a timing chart shown in FIG.16.

InFIG. 16, the input data Sdata changes from invalid data to valid data1and enters the system clock synchronization circuit124at time t10, and changes from valid data1to valid data2and enters the system clock synchronization circuit124at time t13.

However, as shown inFIG. 12, since the input data Sdata and the input enable signal Sen are those which are driven and generated by the buffers123A and123B which come to have high impedance on the falling edge of the input clock CLK, they become indeterminate data on the falling edge of the input clock CLK.

InFIG. 16, these indeterminate data are designated by hatched lines stroked down to the lower right. As shown in the figure, the input data Sdata first changes from the valid data1to the indeterminate data and then to the valid data2before entering the system clock synchronization circuit124.

Similarly, the input data Sdata first changes from the valid data2to the indeterminate data and then to the valid data3, and enters the system clock synchronization circuit124while synchronizing to the input clock CLK. Similarly, the input enable signal Sen becomes indeterminate at times t10and t13on the falling edge of the input clock CLK as illustrated by the hatched lines stroked down to the lower right.

Next, at time t11, synchronizing to the rising edge of the input clock CLK, the flip-flop circuit142takes in the valid data1, and sends it out as a signal S6to the write enable flip-flop circuit147. Furthermore, the flip-flop circuit141takes in data for which the input enable signal is “1” and sends it out as a signal S1to the flip-flop circuit1441.

Next, at time t12, the flip-flop circuit1451latches the “1” and sends out a signal S3which rises to “1” at time t13, which is one cycle duration later of the system clock SCLK. The circuit which is constituted of the flip-flop circuit1452, the inverter1453and the AND gate1454rises in synchronization with the rising of the signal S3, and sends out the mask signal S5having a pulse width of one cycle duration of the system clock SCLK to the flip-flop circuit146, the write enable terminal we of the write enable flip-flop circuit147and the OR gate143. If the mask signal S5becomes “1”, then the flip-flop circuit141is reset through the OR gate143and fall to “0”.

Moreover, at time t14, the flip-flop circuit146takes in the mask signal S5of “1” level, and sends out the mask signal S5of “0” level after one cycle duration of the system clock SCLK. In other words, the flip-flop circuit146sends out the output enable signal Ven which is obtained by delaying the mask signal S5by one cycle duration of the system clock SCLK.

As described above, the input data Sdata, the input enable signal Sen and the input clock CLK, which enter the system clock synchronization circuit, are synchronized to the system clock SCLK and sent out from the system clock synchronization circuit124to the stream separation circuit125as the output data Vdata and the output enable signal Ven which are in synchronization with the system clock SCLK.

Next, the operation of the system clock synchronization circuit illustrated inFIGS. 14 and 15in the case where noise is superimposed on the falling edge of the input clock CLK will be described with reference to FIG.17.

First, the reason why noise is superimposed on the falling edge of the input clock CLK will be described. Since the input data Sdata and the input enable signal Sen are those which synchronize and change on the falling edge of the input clock CLK, the buffers123A and123B momentarily discharge a large current on the falling edge of the input clock CLK. This large current creates a pulse noise, which superimposes on the falling edge of the input clock CLK via crosstalk capacities between transmission paths for the input data Sdata and the input clock CLK and transmission paths for the input enable signal Sen and the input clock CLK.

When this takes place, the buffer123C which drives the input clock CLK has come to have high impedance and is highly sensitive to a noise, being likely to pick up noises, and the input clock CLK becomes 0 and then jumps to 1 on the falling edge, momentarily exhibiting a pulsed wave shape as illustrated by A and B in FIG.17.

In the system clock synchronization circuit illustrated inFIGS. 14 and 15, the input clock CLK directly enters the flip-flop circuits141and142. Therefore, if a noise whose width is less than one cycle duration of the system clock SCLK is superimposed on the falling edge of the input clock CLK, then the flip-flop circuits141and142wrongly see it as the rising edge of the input clock CLK and latch the input data Sdata and the input enable signal Sen with wrong timing, resulting in the malfunction of the system clock synchronization circuit.

Next, the malfunction of the system clock synchronization circuit due to the noise will be described more specifically with reference toFIGS. 15and17.

At time t21, synchronizing to the input clock CLK, the flip-flop circuit141latches the input enable signal Sen which has become indeterminate and sends it out to the flip-flop circuit1441as the signal S1, and the flip-flop circuit142takes in the input data Sdata which has become indeterminate and sends it out to the write enable flip-flop circuit147as the signal S6.

Next, at time t22, synchronizing to the rising edge of the system clock SCLK, the flip-flop circuit1451latches the indeterminate data of the signal S1and, at time t23which is one cycle duration later of the system clock SCLK, sends it out to the flip-flop circuit1452as the output signal S3.

The circuit which is constituted of the flip-flop circuit1452, the inverter1453and the AND gate1454latches the signal S3and sends out to the flip-flop circuit146the indeterminate data of the mask signal S5which has a pulse width of one cycle duration of the system clock SCLK. And, when the mask signal S5becomes “1”, the flip-flop circuit141is reset through the OR gate143and falls to “0”.

Next, at time t24, synchronizing to the rising edge of the system clock SCLK, the write enable flip-flop circuit147latches indeterminate data of the signal S6and sends it out as the output data Vdata. Moreover, synchronizing to the rising edge of the system clock SCLK, the flip-flop circuit146latches indeterminate data of the signal S5and sends it out as the output enable signal Ven. At time t25, this output enable signal Ven changes to “0” in the flip-flop circuit146, which is the result of latching the mask signal S5of “0” level in synchronization with the rising edge of the system clock SCLK.

As described above, if a noise whose width is smaller than one cycle duration of the system clock SCLK is superimposed on the falling edge of the input clock CLK, then the flip-flop circuits141and142wrongly see it as the rising point of the input clock CLK, latches indeterminate data and sends them out to a next circuit. As a result, these indeterminate data successively transmits through the circuits, and the output data Vdata and the output enable data Ven which have become indeterminate end up being sent out to the stream separation circuit125.

As a result, the stream separation circuit125and the MPEG decoder126which constitute a conventional digital broadcast reception device cannot process a mixture of normal data and indeterminate data, separating one from another, and operate in a wrong manner.

In the above-described conventional system clock synchronization circuit, the noise from onboard buffers is coped with inserting noise filters on board. However, the result of noise simulation to determine what sort of filters be placed where on board is far from representing the actual noise, and the truth is that designing board in a trial-and-error fashion is unavoidable.

For this reason, it would take a long period of time to reduce noise to a satisfactory level. It would also pose a problem with respect to production costs as it becomes necessary to add parts on board designed to reduced noise.

Accordingly, it is an object of the present invention that a system clock synchronization circuit be provided which does not send out wrong output data and a wrong output enable signal but is capable of sending out correct output data and a correct output enable signal in synchronization to the system clock even in the case where noise is superimposed on the input clock CLK.

BRIEF SUMMARY OF THE INVENTION

Objects of the Invention

It is an object of the present invention that a system clock synchronization circuit be provided which does not send out wrong output data and a wrong output enable signal but is capable of sending out correct output data and a correct output enable signal in synchronization to the system clock even in the case where noise is superimposed on the input clock CLK.

SUMMARY OF THE INVENTION

A system clock synchronization circuit according to the present invention includes: a first synchronization and timing delay circuit which synchronizes an input clock with a system clock and sends out the first signal which is obtained by delaying the synchronized signal by the first delay amount; an input data latching means for latching input data which changes at the first changing point of the input clock, the latching being in synchronization with the second changing point of the input clock; an input enable signal latching means for latching in synchronization with the input clock an input enable signal which is active when the input data is valid and inactive when the input data is invalid; a mask signal generation circuit which generates in synchronization with the first signal with a mask signal which has a prescribed pulse width; a second synchronization and timing delay circuit which synchronizes a signal sent out from the input data latching means with the system clock and sends out the second signal which is obtained by delaying the synchronized signal by the second delay amount; a third synchronization and timing delay circuit which synchronizes a signal sent out from the input enable signal latching means with the system clock and sends out the third signal which is obtained by delaying the synchronized signal by the third delay amount; a masking means for taking in the mask signal and the third signal, sending out the third signal when the mask signal is active, and masking the third signal when the mask signal is inactive; a first output latching means for latching in synchronization with the system clock the fourth signal from the masking means and sending out an output enable signal; and a second output latching means for taking in the fourth signal at a write enable terminal and the second signal at a data input terminal, latching in synchronization with the system clock the second signal when the fourth signal is active, and holding and sending out as output data the second signal which is taken immediately before when the fourth signal is inactive.

DETAILED DESCRIPTION OF THE INVENTION

Next, examples of the present invention will be described with reference to the drawings.

FIG. 1is a block diagram illustrating the first example of the system clock synchronization circuit according to the present invention, where the same reference characters and numbers designate the same constituent elements as in FIG.14. Incidentally, a circuit configuration of a digital broadcast reception device mounted with the system clock synchronization circuit of the present invention is the same as that of FIG.12.

The system clock synchronization circuit illustrated inFIG. 1includes: a flip-flop circuit141which takes in the input enable signal Sen and operates in synchronization with the input clock CLK; and a flip-flop circuit142which takes in the input data Sdata and operates in synchronization with the input clock CLK.

Moreover, the system clock synchronization circuit illustrated inFIG. 1further includes: a synchronization and timing delay circuit11which synchronizes the input clock CLK with the system clock SCLK and generates the signal S7which is obtained by delaying this synchronized signal by the first delay amount in synchronization with the system clock SCLK; a synchronization and timing delay circuit12which synchronizes the signal S1sent out from the flip-flop circuit141with the system clock SCLK and generates the signal S9which is obtained by delaying this synchronized signal by the second delay amount in synchronization with the system clock SCLK; and a synchronization and timing delay circuit13which synchronizes the signal S6sent out from the flip-flop circuit142with the system clock SCLK and generates the signal S10which is obtained by delaying this synchronized signal by the third delay amount in synchronization with the system clock SCLK.

Moreover, the system clock synchronization circuit illustrated inFIG. 1further includes: a mask signal generation circuit14which takes in the signal S7and generates a mask signal S8having a pulse width of one cycle duration of the system clock SCLK; an AND gate15which takes in the mask signal S8and the signal S9; a flip-flop circuit146which takes in the signal S11sent out from the AND gate15and sends out in synchronization with the system clock SCLK the output enable signal Ven; and a write enable flip-flop circuit147which takes in the signal S11at the write enable terminal we, takes in the signal S10and sends out in synchronization with the system clock SCLK the output data Vdata.

Next, examples of the synchronization and timing delay circuits11,12and13and the mask signal generation circuit14illustrated inFIG. 1will be described with reference to FIG.2. The synchronization and timing delay circuit11illustrated inFIG. 2includes: a flip-flop circuit111which sends out the signal S111which is obtained by synchronizing the input clock CLK with the system clock SCLK; a flip-flop circuit112which sends out the signal S112which is obtained by synchronizing the signal S111from the flip-flop circuit111with the system clock SCLK; and a flip-flop circuit113which sends out the signal S7which is obtained by synchronizing the signal S112with the system clock SCLK.

Moreover, the synchronization and timing delay circuit12includes: a flip-flop circuit121which sends out the signal S121which is obtained by synchronizing the signal S1sent out from the flip-flop circuit141with the system clock SCLK; and a flip-flop circuit122which sends out the signal S9which is obtained by synchronizing the signal S121sent out from the flip-flop circuit121to the system clock SCLK.

Moreover, the synchronization and timing delay circuit13has a circuit configuration similar to the synchronization and timing delay circuit12, including: a flip-flop circuit131which sends out the signal S131which is obtained by synchronizing the signal S6sent out from the flip-flop circuit142with the system clock SCLK; and a flip-flop circuit132which sends out the signal S10which is obtained by synchronizing the signal S131sent out from the flip-flop circuit131to the system clock SCLK.

Moreover, the mask signal generation circuit14includes: a flip-flop circuit141′ which sends out the signal S141which is obtained by synchronizing the signal S7from the flip-flop circuit113with the system clock SCLK; an inverter142′; and an AND gate143′. Here, the flip-flop circuit141′, the inverter142′ and the AND gate143′ operate together to generate the mask signal S8which synchronizes to the rising edge of the signal S7and has a pulse width of one cycle duration of the system clock SCLK.

Next, the operation of the system clock synchronization circuit illustrated inFIG. 1will be described with reference to FIG.1and the timing chart illustrated in FIG.3. InFIG. 3, hatched lines stroked down to the lower left designate invalid data, and those to the lower right designates indeterminate data as inFIGS. 13,16and17.

At time t31, synchronizing to the rising edge of the input clock CLK, the flip-flop circuit142latches invalid data and sends it out as the signal S6(when this takes place, the input enable signal Sen is “0”). Moreover, synchronizing to the rising edge of the input clock CLK, the flip-flop circuit141latches the input enable signal Sen of “0” level and sends it out as the signal S1.

Next, at time t32, synchronizing to the rising edge of the system clock SCLK, the synchronization and timing delay circuit11latches the input clock CLK and, at time t34which is two cycle duration later of the system clock SCLK, sends it out as the signal S7of “1” level. Similarly, synchronizing to the rising edge of the system clock SCLK, the synchronization and timing delay circuit12latches the signal S1of “0” level and, at time t33which is one cycle duration later of the system clock SCLK, sends it out as the signal S9of “0” level.

Next, at time t33, synchronizing to the rising edge of the system clock SCLK, the synchronization and timing delay circuit11latches the input clock CLK and, at time t35which is two cycle duration later of the system clock SCLK, sends out the signal S7of “1” level.

Then, at time t34, synchronizing to the rising edge of the signal S7, the mask signal generation circuit14sends out the mask signal S8having a pulse width equal to one cycle duration of system clock SCLK to the AND gate15. Taking in this signal S8and the signal S9of “0” level, the AND gate15sends out the “0” level.

Next, at time t35, synchronizing to the rising edge of the system clock SCLK, the synchronization and timing delay circuit11latches the input clock CLK of “0” level and, at time t38which is two cycle duration later of the system clock SCLK, sends it out as the signal S7of “0” level.

Next, at time t36, synchronizing to the rising edge of the input clock CLK, the flip-flop circuit142latches the valid data1and sends it out as the signal S6. Consequently, the signal S6changes from invalid data to valid data1. Similarly, synchronizing to the rising edge of the input clock CLK, the flip-flop circuit141latches the input enable signal Sen of “1” level and sends out to the synchronization and timing delay circuit12the signal S1of “1” level which is to indicate that the signal is valid data.

Moreover, at time t37, synchronizing to the rising edge of the system clock SCLK, the synchronization and timing delay circuit12latches the signal S1of “1” level and, at time t38which is one cycle duration later of the system clock SCLK, sends it out as the signal S9of “1” level. Similarly, synchronizing to the rising edge of the system clock SCLK, the synchronization and timing delay circuit13latches the valid data1and, at time t38which is one cycle duration later of the system clock SCLK, sends it out as the valid data1.

Next, at time t39, the AND gate15takes in the mask signal S8which has risen to “1” level and the signal S9of “1” level and sends out the signal S11to the flip-flop circuit146and the write enable flip-flop circuit147, the signal S11rising to the “1” level simultaneously with the input signal, keeping that level for one cycle duration of the system clock SCLK, and falling to the “0” level at time t40.

Next, at time t40, the write enable flip-flop circuit147takes in the signal S11of “1” level at the write enable terminal we and, synchronizing to the rising edge of the system clock SCLK, latches the valid data1. The latched valid data1is sent out as the output data Vdata.

At the same time, synchronizing to the rising edge of the system clock SCLK, the flip-flop circuit146latches the signal S11of “1” level and sends it out as the output enable signal Ven of “1” level.

And, at time t41, the output enable signal Ven which has risen to the “1” level falls to the “0” level simultaneously with the rising edge of the system clock SCLK and is sent out as the signal which keeps the “1” level for a time period between times t40and t41, i.e., as the signal having a pulse width of one cycle duration of the system clock.

What is described so far is the basic operation of the system clock synchronization circuit according to the present invention: the input clock CLK is synchronized to the system clock SCLK; the signal S7is produced by delaying the synchronized signal by the first delay amount in synchronization with the system clock SCLK; and the mask signal S8which is in synchronization with the signal S7is produced.

On the other hand, the input enable signal Sen is synchronized to the input clock CLK to produce the signal S1, which is then synchronized to the system clock SCLK. And, by delaying this synchronized signal by the second delay amount which is in synchronization with the system clock SCLK, the signal S9is produced. The circuit configuration is such that, if the signal S9is either invalid or indeterminate data, then the mask signal S8becomes “0” to prevent the signal S9which has become invalid or indeterminate data from entering the flip-flop circuit146.

Similarly, the input data Sdata is synchronized to the input clock CLK to produce the signal S6, which is then synchronized to the system clock SCLK. And, by delaying this synchronized signal by the third delay amount which is in synchronization with the system clock SCLK, the signal S10is produced. The circuit configuration is such that, if the signal S10is either invalid or indeterminate data, then the signal S11becomes “0” to prevent the write enable flip-flop circuit147from latching the invalid or indeterminate data.

Moreover, the first, second and third delay amounts for the synchronization and timing delay circuits11,12and13, respectively, are determined in such a manner that the mask signal S8of “0” level enters the AND gate15before the signal S9which becomes invalid or indeterminate data would enter the AND gate15and that the signal S11of “0” level enters the flip-flop circuit147at the write enable terminal we before the signal S10which becomes invalid or indeterminate data would enter the write enable flip-flop circuit147.

Next, the operation of the system clock synchronization circuit illustrated inFIG. 1in the case where the noise is superimposed on the falling edge of the input clock CLK will be described with reference to FIG.4.

At time t41, synchronizing to the falling edge of the input clock CLK, the flip-flop circuit141latches the input enable signal Sen which has become indeterminate, and sends it out as the signal S1to the synchronization and timing delay circuit12. At time t42, synchronizing to the rising edge of the system clock SCLK, the synchronization and timing delay circuit12latches the signal S1which has become indeterminate and, at time t43which is one cycle duration later of the system clock SCLK, sends it out as the signal S9to the AND gate15.

Similarly, at time t41, synchronizing to the falling edge of the input clock CLK, the flip-flop circuit142latches the input data Sdata which has become indeterminate and sends it out as the signal S6to the synchronization and timing delay circuit13. At time t42, synchronizing to the rising edge of the system clock SCLK, the synchronization and timing delay circuit13latches the signal S6which has become indeterminate and, at time t43which is one cycle duration later of the system clock SCLK, sends it out as the signal S10to the write enable flip-flop circuit147.

Moreover, since, at time t42, the flip-flop circuit146latches the “1” level of the signal S11and, at time t43which is one cycle duration later of the system clock SCLK, latches its “0” level, it sends out a signal illustrated as the output enable signal Ven, which rises at time t42and has a pulse width of one cycle duration of the system clock SCLK.

Moreover, since the signal S11is of “1” level at time t42, the write enable flip-flop circuit147latches the signal S10(valid data2), synchronizing to the rising edge of the system clock SCLK.

Next, at time t45, synchronizing to the rising edge of the input clock CLK, the flip-flop circuit141latches the input enable signal Sen of “1” level. As a result, the signal S1changes from indeterminate data to data of “1” level.

Similarly, at time t45, synchronizing to the rising edge of the input clock CLK, the flip-flop circuit142latches the valid data3. As a result, the signal S6changes from indeterminate data to the valid data3.

Next, at time t46, synchronizing to the rising edge of the system clock SCLK, the synchronization and timing delay circuit13latches the valid data3. As a result, the signal S10changes from indeterminate data to the valid data3.

Next, at time t47, synchronizing to the rising edge of the signal S7, the mask signal S8rises and so does the signal S11, producing a pulse signal having a pulse width of one cycle duration of the system clock SCLK.

Moreover, synchronizing to the rising edge of the system clock SCLK, the flip-flop circuit146latches the signal S11of “1” level, and sends out the output enable signal Ven which is a pulse signal having a pulse width of one cycle duration of the system clock SCLK. On the other hand, synchronizing to the rising edge of the system clock SCLK, the write enable flip-flop circuit147latches the signal S10(valid data3) because the signal S11is of “1” level. As a result, the output data Vdata changes from the valid data2to the valid data3.

Next, the operation of the system clock synchronization circuit described above will be summarized.

1) At time t41, synchronizing to the rising edge due to the noise superimposed on the falling edge of the input clock, the signal S1which is an indeterminate signal is sent out from the flip-flop circuit141. This indeterminate data continues until time t45, which is the next rising edge of the input clock CLK.

2) At time t42, synchronizing to the rising edge of the system clock SCLK, the synchronization and timing delay circuit12latches the indeterminate data of 1) above. The latched data changes to the “1” level at time t46, which is about one cycle duration later of the system clock SCLK from the time when the signal S1changes to the “1” level.

3) The mask signal S8continues the “0” level until one cycle duration later of the system clock SCLK from time t46. Therefore, the signal S9which is indeterminate data is masked by the mask signal S8so that the indeterminate data is not sent out from the AND gate15.

4) The signal S11, which rises in synchronization with the rising edge of the system clock SCLK at time t47and indicates that it is valid data, is sent out from the AND gate15and is eventually sent out as the output enable signal Ven which rises at time t48.

11) At time t41, synchronizing to the rising edge due to the noise superimposed on the falling edge of the input clock, the signal S6which is an indeterminate signal is sent out from the flip-flop circuit142. This indeterminate data continues until time t45, which is the next rising edge of the input clock CLK.

12) At time t42, synchronizing to the rising edge of the system clock SCLK, the synchronization and timing delay circuit13latches the indeterminate data of 11) above. This indeterminate data changes to the valid data3at time t46, which is about one cycle duration later of the system clock SCLK from the time when the signal S6changes to the valid data3.

13) The signal S11continues the “0” level until one cycle duration later of the system clock SCLK from time t46. Therefore, the signal S10which is indeterminate data is substantially masked by the signal S11, thereby not being latched by the write enable flip-flop circuit147.

14) At time t48, synchronizing to the rising edge of the system clock SCLK, the write enable flip-flop circuit147latches the signal S10which is the valid data3and sends it out as the output data Vdata.

As described above, even if indeterminate signals occur in the flip-flop circuits141and142, synchronizing to the rising edge due to noise superimposed on the falling edge of the input clock, the indeterminate data does not enter the flip-flop circuit146and the write enable flip-flop circuit147because of the mask signals S8and S11.

It is necessary that the mask signals S8and S11be of “0” level while each of the signal S9and S10is indeterminate data. This timing condition is satisfied by adjusting the first, second and third delay amounts of the synchronization and timing delay circuits11,12and13, respectively.

Next, a case where the clock frequency of the system clock SCLK′ becomes lower than that of the system clock SCLK illustrated inFIG. 4will be described with reference to FIG.5.FIG. 5is the same asFIG. 4with respect to the system clock synchronization circuit, the input clock CLK, the input data Sdata, the input enable signal Sen, and the noise superimposed on the falling edge of the input clock CLK, except for the frequency of the system clock SCLK′ which is lower than that of the system clock SCLK.

The circuit operation in the case ofFIG. 5becomes almost the same as the circuit operation illustrated in FIG.4. However, if the clock frequency of the system clock SCLK′ becomes smaller than that of the input clock CLK by a certain ratio, then the signal S9which has become indeterminate data can no longer be masked by the mask signal S8.

Next, this phenomenon mentioned above will be described.

Time t56at which the signal S9changes from indeterminate data to the “1” level is, in the case ofFIG. 5, when the system clock SCLK rises about one and a half cycle duration later of the system clock SCLK from time t54. If the clock frequency of the system clock SCLK decreases, then time t56shifts in such a direction that time t56moves away from t54.

In order for the mask signal S8to be able to mask the signal S9, the interval between times t56and t58must at least be larger than one cycle duration of the system clock. However, if the clock frequency of the system clock SCLK becomes small, then a mask signal which stretches for one cycle duration of the system clock SCLK cannot be generated between times t56and t58.

Considering the typical timing condition, it is necessary that a time period over which the input clock CLK is “1” level (half the complete cycle of the input clock signal) be latched twice or more at the rising edge of the system clock SCLK. That is to say that the clock frequency of the system clock SCLK needs to be four times or more that of the input clock CLK. The system clock synchronization circuits ofFIGS. 1 and 2were designed such that the clock frequencies were 12.5 MHz for the input clock CLK and 66 to 100 MHz for the system clock SCLK.

Furthermore, in addition to the first constraint described above, the second constraint is necessary that the first delay amount of the synchronization and timing delay circuit11be larger than the second and third delay amounts of the synchronization and timing delay circuits12and13, respectively, as described before. This second constraint means that the number of latching stages in the synchronization and timing delay circuit11by flip-flop circuits, etc. for a period over which the input clock CLK is synchronized to the system clock SCLK and sent out as the signal S7is larger than the number of latching stages in the synchronization and timing delay circuit12by flip-flop circuits, etc. for a period over which the input enable signal Sen synchronized to the input clock signal CLK is synchronized to the system clock SCLK and sent out as the signal S9, and the number of latching stages in the synchronization and timing delay circuit13by flip-flop circuits, etc. for a period over which the input data Sdata synchronized to the input clock signal CLK is synchronized to the system clock SCLK and sent out as the signal S10.

In the example ofFIG. 2, the synchronization and timing delay circuit11has three flip-flop circuits in cascade connection which are synchronized to the system clock SCLK, and the synchronization and timing delay circuits12and13have two flip-flop circuits in cascade connection which are synchronized to the system clock SCLK, thereby satisfying the second constraint mentioned above.

As described above, the first, second and third delay amounts are adjusted by changing the number of cascade connections of the flip-flop circuits which constitute the synchronization and timing delay circuit.

The input enable signal Sen is latched in synchronization with the input clock CLK in the flip-flop circuit141, and the signal S1is latched in synchronization with the system clock SCLK in the synchronization and timing delay circuit12. However, since the input clock CLK and the system clock SCLK are asynchronous, there is a certain delay between the output of the signal S1from the flip-flop circuit141and the latch in the synchronization and timing delay circuit12as illustrated by C1and C2in FIG.6and E1and E2in FIG.7.

In the case of C1and C2, the flip-flop circuit121latches the indeterminate signal S1on the rising edge of the system clock immediately after the rising edge of the noise, but in the case of E1and E2, the flip-flop circuit121latches the indeterminate signal S1on the rising edge of the system clock which is one cycle duration later of the system clock after the rising edge of the noise. Therefore, due to a minute misalignment of rising edges between the noise and the system clock, the timing of the signal S1which is latched in the flip-flop circuit121differs greatly.

Similarly, the input data Sdata is latched in synchronization with the input clock CLK in the flip-flop circuit142, and the signal S6is latched in synchronization with the system clock SCLK in the synchronization and timing delay circuit13. However, due to the slight misalignment of rising edges between the noise and the system clock, the timing of the signal S6which is latched by the flip-flop circuit131differs greatly as illustrated by D1and D2in FIG.6and F1and F2in FIG.7.

However, even in such a case, by providing the first and second constraints, the misalignment of latch timing due to the fact that the input clock CLK and the system clock SCLK are asynchronous can be corrected, thereby sending out only the correct input data Sdata and the correct input enable signal Sen as the output data Vdata and the output enable signal Ven, respectively.

Next, the second example of the system clock synchronization circuit according to the present invention will be described with reference toFIGS. 1 and 8.

FIG. 8is a block diagram illustrating the second example of the system clock synchronization circuit according to the present invention, which corresponds to the circuit configuration ofFIG. 1where the input enable signal Sen is constantly “1”.

If the input enable signal Sen is constantly “1”, then the synchronization and timing delay circuit12constantly sends out “1”, and the AND gate15becomes unnecessary. Therefore, the circuit configuration ofFIG. 1from which the flip-flop circuit141, the synchronization and timing delay circuit12and the AND gate15have been removed corresponds to that of FIG.8. The circuit configuration ofFIG. 8is characterized in that the number of circuit elements is smaller than inFIG. 1where the input terminal of the flip-flop circuit141is constantly pulled up to “1”.

Next, the third example of the system clock synchronization circuit according to the present invention will be described with reference toFIGS. 1 and 9.

FIG. 9is a block diagram illustrating the third example of the system clock synchronization circuit according to the present invention.

InFIG. 1, indeterminate data of the signal S9was masked by sending the mask signal S8generated in the mask signal generation circuit14to one of the terminals of the AND gate15. However, the circuit operation similar to that of the system clock synchronization circuit illustrated inFIG. 1can be realized by: as inFIG. 9, first sending the input clock CLK and the signal S1sent out from the flip-flop circuit141to the AND gate91; sending the signal sent out from this AND gate91to the synchronization and timing delay circuit11; generating a mask signal in the mask signal generation circuit14from the signal sent out from the synchronization and timing delay circuit11; and sending this mask signal to both the input terminal of the flip-flop circuit146and the write enable terminal we of the write enable flip-flop circuit147.

That is, inFIG. 9, instead of taking a logical product of the signal S9and the mask signal S8as inFIG. 1, a logical product of the input clock CLK and the signal S1is taken, and then the signal of this logical product is processed in the downstream of the synchronization and timing delay circuit11in FIG.9.

Next, the fourth example of the system clock synchronization circuit according to the present invention will be described with reference to FIGS.1and10.

FIG. 10is a block diagram illustrating the fourth example of the system clock synchronization circuit according to the present invention. The synchronization and timing delay circuits11,12and13inFIG. 1synchronized the input signal to the system clock SCLK and delayed this synchronized signal by the first, second and third delay amounts, respectively, thereby adjusting the timing among each other. However, the synchronization circuits101,102and103which constitute the system clock synchronization circuits of the present example respectively synchronize the input clock CLK, the input enable signal Sen which is synchronized to the input clock CLK and the input data Sdata which is synchronized to the input clock CLK to the system clock SCLK, and send out these synchronized signals but do not delay the synchronized signals.

The timing adjustment for the entire system clock synchronization circuit is conducted by a timing delay circuit104. This timing delay circuit104is set in such a manner that the delay between the input to the synchronization circuit101and the output from the timing delay circuit104through the mask signal generation circuit14is larger than the delay between the input to and the output from the synchronization circuit102and the delay between the input to and the output from the synchronization circuit103. By providing such a setting, the second constraint described above can be satisfied.

Since the system clock synchronization circuit according to the present example does not include any delay circuits along the transmission path through which the input enable signal Sen and the input data Sdata travel, the input enable signal Sen and the input data Sdata can travel through the transmission path fast. As a result, the speedup of the system clock synchronization circuit can be achieved, and a digital broadcast reception device which processes signals fast can be realized.

Next, the fifth example of the system clock synchronization circuit according to the present invention will be described with reference toFIGS. 1 and 11.

FIG. 11is a block diagram illustrating the fifth example of the system clock synchronization circuit according to the present invention. The system clock synchronization circuits described so far all operated in such a manner that the input data Sdata and the input enable signal Sen changed in synchronization to the falling edge of the input clock CLK and the input data Sdata and the input enable signal Sen were latched in synchronization to the rising edge of the input clock CLK. However, the system clock synchronization circuit according to the present example is for a case where the input data Sdata and the input enable signal Sen change in synchronization to the rising edge of the input clock CLK and the input data Sdata and the input enable signal Sen are latched in synchronization to the falling edge of the input clock CLK.

The system clock synchronization circuit according to the present example is characterized in that an input clock inversion circuit16for inverting the input clock CLK has been added to the system clock synchronization circuit illustrated inFIG. 1, the input clock inversion circuit16sending out the inverted input clock CLK-barred, which is an inversion of the input clock CLK, to the flip-flop circuits141and142and the synchronization and timing delay circuit11.

The circuit operates in a manner similar to the system clock synchronization circuit ofFIG. 1except that the inverted input clock CLK-barred replaces the input clock CLK.

As duly described so far, even in the case where the noise is superimposed on the input clock, the system clock synchronization circuit of the present invention does not send out wrong output data and wrong output enable signal but is capable of sending out correct output data and a correct output enable signal which are synchronized to the system clock.

Moreover, the large misalignment of latch timings when latching the input data and the input enable signal due to the fact that the input clock and the system clock are asynchronous can be corrected, and only correct input data and a correct input enable signal can be sent out as the input data and the input enable signal, respectively.

Moreover, by setting a clock frequency of the system clock over a range greater than a certain ratio to the input clock frequency, depending on the input clock frequency, correct output data and a correct output enable signal which are without any errors due to the input clock superimposed with the noise and synchronized to the system clock can be sent out over a wide range of the input clock frequencies.