SEMICONDUCTOR DEVICE

A semiconductor device for operating an inductive load, including: a switching element having a control terminal, a low potential terminal and a high potential terminal; a drive circuit configured to apply a control voltage to the control terminal of the switching element to switching-drive the switching element, and operate the inductive load connected to the switching element; an extracting circuit configured to extract control terminal charges from the control terminal of the switching element when the switching element makes a transition from an on state to an off state; and a voltage control circuit connected to a connection point between the low potential terminal of the switching element and the inductive load, the voltage control circuit being configured to clamp a drop in a voltage at the connection point to a predetermined voltage while the extracting circuit is extracting the control terminal charges.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2023-112632, filed on Jul. 7, 2023, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The embodiment discussed herein relates to a semiconductor device.

2. Background of the Related Art

Various electronic devices mounted in vehicles include devices which drive a switching element according to a control signal to operate an inductive load. One-chip semiconductor devices are known as such devices. Such a semiconductor device includes an active clamping circuit to prevent destruction of a device in the semiconductor device at the time of clamping operation of an inductive load.

For example, a technique for setting a clamp voltage which depends on an active clamping circuit to a first clamp voltage at the time of a forward voltage change at an output terminal not being detected and for setting a clamp voltage to a second clamp voltage lower than the first clamp voltage at the time of a forward voltage change at the output terminal being detected was proposed as a related art.

SUMMARY OF THE INVENTION

According to an aspect, there is provided a semiconductor device for operating an inductive load, including: a switching element having a control terminal, a low potential terminal and a high potential terminal, the high potential terminal being configured to receive a positive power supply voltage, the switching element being connected to the inductive load, and being configured to operate in an on state and an off state; a drive circuit configured to apply a control voltage to the control terminal of the switching element to switching-drive the switching element, and operate the inductive load connected to the switching element; an extracting circuit configured to extract control terminal charges from the control terminal of the switching element while the switching element makes a transition from the on state to the off state; and a voltage control circuit connected to a connection point between the low potential terminal of the switching element and the inductive load, the voltage control circuit being configured to clamp a drop in a voltage at the connection point to a predetermined voltage while the extracting circuit is extracting the control terminal charges.

DETAILED DESCRIPTION OF THE INVENTION

An embodiment will now be described with reference to the accompanying drawings. Components in the specification and the drawings having virtually the same structure are marked with the same numeral. By doing so, a duplicate description may be omitted.

FIG.1is a view for describing an example of a semiconductor device. A semiconductor device1includes a switching element1a, a drive circuit1b, an extracting circuit1c, and a voltage control circuit1d. Furthermore, the semiconductor device1includes an output terminal OUT, an input terminal IN, and a power supply terminal Vin. An inductive load3is connected to the output terminal OUT. The inductive load3is an inductive load, such as a solenoid valve, widely used in an automobile.

A control section (not illustrated), such as an electronic control unit (ECU), is connected to the input terminal IN. A control signal output from the control section is input to the input terminal IN. A power supply section4which outputs a power supply voltage VCC is connected to the power supply terminal Vin.

The switching element1ais a power semiconductor switching element having a high potential terminal p1, a control terminal p2, and a low potential terminal p3and is a power metal-oxide-semiconductor field-effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), or the like. Furthermore, a positive electrode end of the power supply section4is connected to the high potential terminal p1of the switching element1a. If the switching element1ais a power MOSFET, then the high potential terminal p1, the control terminal p2, and the low potential terminal p3correspond to a drain, a gate, and a source, respectively, in the structure of the semiconductor device1.

On the basis of the control signal input via the input terminal IN, the drive circuit1bapplies a control voltage to the control terminal p2of the switching element1ato switching-drive the switching element1a. Furthermore, the drive circuit1boperates the inductive load3connected via the output terminal OUT to the switching element1a.

If the switching element1amakes the transition from an on state to an off state, then the extracting circuit1cextracts charges from the control terminal p2of the switching element1a. While the extracting circuit1cextracts charges from the control terminal p2, the voltage control circuit1dclamps a drop in voltage at a connection point (corresponding to the output terminal OUT) of the low potential terminal p3of the switching element1aand the inductive load3at a determined voltage.

By adopting the above structure of the semiconductor device1, clamp resistance is improved by decreasing clamp voltage. Furthermore, durability for high voltage application is improved.

Before the details of the present disclosure is described, a semiconductor device including an active clamping circuit will now be described with reference toFIGS.2through5. In the following description, the inductive load3will be referred to as an L load3.

FIG.2illustrates an example of the structure of a semiconductor device including an active clamping circuit. A semiconductor device10aincludes an output terminal OUT, an input terminal IN, and a power supply terminal Vin. The L load3is connected to the output terminal OUT. A control signal output from an ECU or the like is input to the input terminal IN. A power supply section4which outputs, for example, VCC=16 V is connected to the power supply terminal Vin.

The semiconductor device10aincludes a drive circuit11, an active clamping circuit2, resistors R1and R2, an output-stage switch M1, and a gate charge extracting MOS transistor M2. An n-channel MOSFETs (NMOS transistors) are used as the output-stage switch M1and the gate charge extracting MOS transistor M2.

The active clamping circuit2includes diodes D1and D2. The resistor R1has the function of a protection resistor. That is to say, the resistor R1protects the output-stage switch M1connected in series with the resistor R1against surge noise, an input of a current larger than an allowable value, or the like. Furthermore, the resistor R2is a pull-down resistor.

Each element is connected in the following way. The input terminal IN is connected to an input end of the drive circuit11. The power supply terminal Vin is connected to a positive electrode end of the power supply section4, a drain of the output-stage switch M1, a cathode of the diode D1, and one power source terminal of the drive circuit11.

An anode of the diode D1is connected to an anode of the diode D2. A cathode of the diode D2is connected to one end of the resistor R1, one end of the resistor R2, a drain of the gate charge extracting MOS transistor M2, and a signal output end a1of the drive circuit11. The other end of the resistor R1is connected to a gate of the output-stage switch M1. A gate of the gate charge extracting MOS transistor M2is connected to a signal output end a2of the drive circuit11.

The output terminal OUT is connected to one end of the L load3, a source of the output-stage switch M1, the other end of the resistor R2, a source of the gate charge extracting MOS transistor M2, and the other power source terminal of the drive circuit11. The other end of the L load3is connected to a negative electrode end of the power supply section4and ground (GND).

When an H-level control signal is input to the input terminal IN, the drive circuit11outputs an H-level signal from the signal output end a1to the gate of the output-stage switch M1to turn on the output-stage switch M1.

In addition, when an L-level control signal is input to the input terminal IN, the drive circuit11outputs an L-level signal from the signal output end a1to the gate of the output-stage switch M1to turn off the output-stage switch M1. Under the above switching control by the drive circuit11, the output-stage switch M1functions as a switching element for controlling a current flowing through the L load3.

Furthermore, when the drive circuit11turns on the output-stage switch M1, the drive circuit11outputs an L-level signal from the signal output end a2to turn off the gate charge extracting MOS transistor M2. Moreover, if the output-stage switch M1makes a transition to an off state, then the drive circuit11outputs an H-level signal from the signal output end a2to turn on the gate charge extracting MOS transistor M2.

When the gate charge extracting MOS transistor M2is turned on, gate charges corresponding to a control voltage of the output-stage switch M1are extracted via the resistor R1and the gate of the output-stage switch M1becomes an L level. This prompts the output-stage switch M1to turn off.

As stated above, when the output-stage switch M1is turned off, gate charges are extracted by the gate charge extracting MOS transistor M2. As a result, switching time of the output-stage switch M1is made shorter than or equal to a determined time and switching loss is suppressed.

On the other hand, if the output-stage switch M1makes the transition from an on state to an off state, then the active clamping circuit2protects the output-stage switch M1against overvoltage generated due to the inductance of the L load3.

FIG.3illustrates an example of the structure of an active clamping circuit. A diode D1included in the active clamping circuit2may be made up of one or more diffused junction type Zener diodes D1-1, . . . , and D1-n. Furthermore, a diode D2included in the active clamping circuit2may be made up of one or more polycrystalline silicon type Zener diodes D2-1, . . . , and D2-n.

FIG.4illustrates an example of an operational waveform of the semiconductor device.FIG.4illustrates an operational waveform of the above semiconductor device10aobtained at the time of a voltage across the L load3being cramped. A waveform g11is the waveform of a control signal VIN at the input terminal IN.

A waveform g12is the waveform of a voltage VOUT at the output terminal OUT. A waveform g13is the waveform of a current IOUT flowing from the output-stage switch M1, through the output terminal OUT, to the L load3.

(Period t11) When the semiconductor device10ais started, the control signal VIN becomes an L level. At this time, the gate of the output-stage switch M1becomes an L level. Accordingly, the output-stage switch M1turns off. Furthermore, the source of the output-stage switch M1is connected to the output terminal OUT and the output-stage switch M1turns off. As a result, the voltage VOUT is 0 V. In addition, because the output-stage switch M1turns off, the current IOUT does not flow and is 0 A.

(Period t12) The control signal VIN becomes an H level (5 V, for example). At this time, the gate of the output-stage switch M1becomes an H level. Accordingly, the output-stage switch M1turns on. Because the output-stage switch M1turns on, the current IOUT flows from the output terminal OUT to the L load3and increases. In addition, it is assumed that the power supply voltage VCC of the power supply section4is 16 V. Because the output-stage switch M1turns on, the voltage VOUT rises to 16 V.

(Period t13) The control signal VIN becomes an L level. At this time, the gate of the output-stage switch M1becomes an L level and the output-stage switch M1turns off. Accordingly, the current IOUT flowing from the output terminal OUT to the L load3takes a direction in which it is cut off. As a result, the current IOUT decreases.

On the other hand, the L load3is connected to the output terminal OUT. When the output-stage switch M1makes the transition from an on state to an off state to cut off the flow of the current IOUT, a current flowing through the L load3attempts to maintain the flow. As a result, back electromotive force is generated in the L load3in a direction in which the current IOUT flows.

Accordingly, the voltage VOUT drops. For example, if a peak of a potential differential during period t13between the power supply terminal Vin and the output terminal OUT is 50 V and the power supply voltage VCC of the power supply section4is 16 V, then the voltage VOUT drops to −34 V. A voltage between VCC and OUT at this time is a clamp voltage.

When during period t13, the breakdown voltage of the diode D1included in the active clamping circuit2is exceeded and the diode D1breaks down, the current IOUT flows in the reverse direction, that is to say, from the cathode to anode of the diode D1. Furthermore, if at this time, a voltage applied between the gate and the source of the output-stage switch M1becomes higher than or equal to a threshold voltage of the output-stage switch M1, then the output-stage switch M1turns on and the current IOUT flows through the output-stage switch M1to the output terminal OUT.

In addition, a remaining current IOUT which does not flow in the direction of the output-stage switch M1flows through the diode D2and the resistor R2to the output terminal OUT. By exercising the above control, energy stored in the inductance of the L load3at the time of a voltage across the L load3being clamped is handled (surge current at the time of a voltage across the L load3being clamped is handled).

(Period t14) After handling energy stored in the inductance of the L load3ends, the same operation that is performed during period t11is performed.

As has been described, when the control signal VIN becomes an H level, the output-stage switch M1goes into an on state and a current flows through the L load3. When the output-stage switch M1is in an off state, the voltage VOUT drops to a negative value due to back electromotive force generated in the L load3.

When the breakdown voltage of the diode D1inserted between the drain and the gate of the output-stage switch M1is exceeded, a current flows into the gate of the output-stage switch M1and the output-stage switch M1is put into an on state. Furthermore, a current flows through the pull-down resistor R2. As a result, energy stored in the L load3is handled.

FIG.5illustrates the relationship between clamp voltage and clamp resistance. InFIG.5, a vertical axis indicates clamp resistance (mJ) and a horizontal axis indicates clamp voltage (V). Clamp resistance j1at the time of clamp voltage=50 V is lower than clamp resistance j2at the time of clamp voltage=30 V.

If a clamp voltage is 50 V, then time taken to handle energy stored in the L load3is short compared with a case where a clamp voltage is 30 V. However, if energy handling is performed in a short period of time, then the output-stage switch M1generates much heat and clamp resistance is low compared with a case where a clamp voltage is 30 V. As a result, destruction of the element tends to occur.

As stated above, clamp resistance depends on a clamp voltage. Accordingly, if a clamp voltage is made as low as possible, then clamp resistance is improved. On the other hand, if a clamp voltage is made low, it is difficult to form an active clamping circuit which resists high voltage application. The present disclosure has been made in view of this problem. An object of the present disclosure is to provide a semiconductor device in which clamp resistance is improved by decreasing a clamp voltage and in which durability for high voltage application is improved.

A semiconductor device according to an embodiment will now be described in detail.FIG.6illustrates an example of the structure of a semiconductor device. For example, a semiconductor device10according to an embodiment exercises control on a high side in a power module such as an intelligent power switch (IPS). The semiconductor device10includes an output terminal OUT, an input terminal IN, a power supply terminal Vin, and a ground (GND) terminal. An L load3is connected to the output terminal OUT. A control signal is input to the input terminal IN. A power supply section4having, for example, power supply voltage VCC=16 V is connected to the power supply terminal Vin.

The semiconductor device10includes a drive circuit11, a voltage control circuit12, resistors R1and R2, an output-stage switch M1(switching element), a gate charge extracting MOS transistor M2(first MOS transistor), and a ground (GND) resistor R4.

The voltage control circuit12includes a resistor R3and a voltage-controlled MOS transistor M3(second MOS transistor). The voltage-controlled MOS transistor M3has the function of a source follower. That is to say, an output voltage follows up an input voltage. Furthermore, the resistor R3has the function of a protection resistor. That is to say, the resistor R3protects the voltage-controlled MOS transistor M3connected in series with the resistor R3against surge noise, an input of a current larger than an allowable value, or the like.

An NMOS transistor (first NMOS transistor) is used as the gate charge extracting MOS transistor M2and an NMOS transistor (second NMOS transistor) is used as the voltage-controlled MOS transistor M3. The semiconductor device10differs from the semiconductor device10aillustrated inFIG.2in that it does not include the active clamping circuit2and in that it includes the voltage control circuit12.

Each element is connected in the following way. The input terminal IN is connected to an input end of the drive circuit11. The power supply terminal Vin is connected to a positive electrode end of the power supply section4, a drain of the output-stage switch M1, and one power source terminal of the drive circuit11. One end of the resistor R1is connected to one end of the resistor R2, a drain of the gate charge extracting MOS transistor M2, and a signal output end a1of the drive circuit11.

The other end of the resistor R1is connected to a gate of the output-stage switch M1. A gate of the gate charge extracting MOS transistor M2is connected to a drain of the voltage-controlled MOS transistor M3and a signal output end a2of the drive circuit11.

The output terminal OUT is connected to one end of the L load3, a source of the output-stage switch M1, the other end of the resistor R2, a source of the gate charge extracting MOS transistor M2, a source of the voltage-controlled MOS transistor M3, and the other power source terminal of the drive circuit11. One end of the resistor R3is connected to a gate of the voltage-controlled MOS transistor M3. The other end of the resistor R3is connected to one end of the ground resistor R4. The other end of the ground resistor R4is connected to the GND terminal. The GND terminal is connected to the other end of the L load3, a negative electrode end of the power supply section4, and GND (reference potential).

FIG.7illustrates an example of an operational waveform of the semiconductor device.FIG.7illustrates an operational waveform of the above semiconductor device10obtained at the time of a voltage across the L load3being cramped. A waveform g1is the waveform of a control signal VIN at the input terminal IN. A waveform g2is the waveform of a gate voltage VgM1of the output-stage switch M1.

A waveform g3is the waveform of a voltage VOUT at the output terminal OUT. A waveform g4is the waveform of a gate voltage VgM2of the gate charge extracting MOS transistor M2.

A waveform g5is the waveform of a current IM2flowing from the drain to the source of the gate charge extracting MOS transistor M2. A waveform g6is the waveform of a current IM3flowing from the drain to the source of the voltage-controlled MOS transistor M3. A waveform g7is the waveform of a current IOUT flowing from the output-stage switch M1, through the output terminal OUT, to the L load3.

(Period t1) When the semiconductor device10is started, the control signal VIN becomes an L level. At this time, the gate voltage VgM1of the output-stage switch M1becomes an L level. Accordingly, the output-stage switch M1turns off. The source of the output-stage switch M1is connected to the output terminal OUT and the output-stage switch M1turns off. As a result, the voltage VOUT is 0 V.

Furthermore, if the gate voltage VgM1is 0 V, then the gate charge extracting MOS transistor M2turns on.

However, the current IM2does not flow when the semiconductor device10is started. Because the voltage-controlled MOS transistor M3is in an off state, the current IM3does not flow. Because the output-stage switch M1turns off, the current IOUT does not flow and is 0 A.

(Period t2) The control signal VIN becomes an H level (5 V, for example). At this time, the gate voltage VgM1of the output-stage switch M1rises and the output-stage switch M1turns on. Furthermore, it is assumed that the power supply voltage VCC of the power supply section4is 16 V. Because the output-stage switch M1turns on, the voltage VOUT is 16 V.

In addition, if the gate voltage VgM1rises, then the gate voltage VgM2becomes an L level, the gate charge extracting MOS transistor M2turns off, and extracting gate charges of the output-stage switch M1is stopped. Because the voltage-controlled MOS transistor M3is in an off state, the current IM3does not flow. Moreover, because the output-stage switch M1turns on, the current IOUT flows from the output terminal OUT to the L load3and increases.

(Period t3) The control signal VIN becomes an L level. The gate voltage VgM1of the output-stage switch M1drops and the output-stage switch M1begins to turn off. The output-stage switch M1makes the transition from an on state to an off state.

At this time, the gate voltage VgM2becomes an H level, the gate charge extracting MOS transistor M2turns on, and gate charges are extracted via the gate charge extracting MOS transistor M2. As a result, the voltage VOUT drops. Furthermore, because the gate charge extracting MOS transistor M2turns on and extracts gate charges, the current IM2flows. Because the voltage-controlled MOS transistor M3is in an off state, the current IM3does not flow. (Period t4) It is assumed that a threshold voltage of the voltage-controlled MOS transistor M3is Vth. When the voltage VOUT becomes lower than or equal to a voltage differential (GND-Vth) between GND and the threshold voltage Vth in a clamp operation state of a voltage across the L load3, the voltage-controlled MOS transistor M3turns on.

Furthermore, the gate charge extracting MOS transistor M2turns off and extracting gate charges is stopped. Alternatively, an on state of the gate charge extracting MOS transistor M2is slightly maintained and the amount of gate charges extracted is minimized. Because gate charges are extracted via the resistor R2, an extracting speed drops.

In addition, when the voltage-controlled MOS transistor M3turns on, a drop in the voltage VOUT at the output terminal OUT is clamped at the voltage differential (GND-Vth) and stops. That is to say, the voltage VOUT is determined by a source follower of the voltage-controlled MOS transistor M3and is clamped at the voltage differential (GND-Vth). Accordingly, a clamp voltage is −Vth (=GND-Vth) and is −3 V in the example ofFIG.7. After period t4ends, the same operation that is performed during period t1is performed.

FIG.8illustrates the relationship between clamp voltage and clamp resistance. InFIG.8, a vertical axis indicates clamp resistance (mJ) and a horizontal axis indicates clamp voltage (V). From the viewpoint of the absolute value of clamp voltage, clamp voltage drops to 3 V by adopting the structure of the semiconductor device10. Accordingly, clamp resistance j3at the time of clamp voltage=3 V is higher than clamp resistance j1or j2and clamp resistance is improved at a low clamp voltage. Furthermore, clamp voltage is decreased without using the active clamping circuit2. This ensures durability for high voltage application.

As has been described in the foregoing, according to the present disclosure, the voltage-controlled MOS transistor M3is located between the gate and the source of the gate charge extracting MOS transistor M2which extracts gate charges of the output-stage switch M1. The voltage VOUT at the time of a voltage across the L load3being cramped is controlled by switching of the voltage-controlled MOS transistor M3. This improves the clamp resistance of the L load3by decreasing clamp voltage and realizes a circuit which withstands high voltage application.

The embodiment has been taken as an example. The structure of each section indicated in the embodiment may be replaced by another structure having the same function. Furthermore, any other component or process may be added. Moreover, the structures (features) of any two or more of the above embodiment may be combined.

According to an aspect, clamp resistance is improved by decreasing clamp voltage and durability for high voltage application is improved.