Method of manufacturing image pickup device

A method of manufacturing an image pickup device includes a step of forming a filling member such that the filling member covers a light guiding part and a peripheral part provided in a film. The light guiding part is positioned on an image pickup region of the image pickup device and has openings that correspond to respective photoelectric conversion portions. The peripheral part is positioned on a peripheral region of the image pickup device. The filling member fills in the openings. The method includes a step of processing the filling member. The method includes a step of forming light guiding members, which is performed after the step of processing filling member has been performed, by a polishing process performed on the filling member so that the light guiding part is exposed. The light guiding members are part of the filling member and disposed in the openings.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present disclosure relates to a method of manufacturing an image pickup device that has a plurality of light guiding members.

2. Description of the Related Art

It has been proposed that light guiding paths (optical waveguides) that guide light to photoelectric conversion portions are provided in image pickup devices such as complementary metal oxide semiconductor (CMOS) sensors. In an example of known methods, such light guiding paths are formed as follows. That is, a plurality of openings are initially formed in a base film formed of a silicon oxide layer, and then a silicon nitride filling member is formed as a film so as to fill in the plurality of openings. Excessive part of the filling member spread out of the openings is removed by using a chemical mechanical polishing (CMP) method. Thus, silicon nitride light guiding members have been formed.

Japanese Patent Laid-Open No. 2009-164247 discloses an image pickup device that has an effective pixel region, in which photoelectric conversion portions are arranged, and a peripheral region, which surrounds the effective pixel region. In the image pickup device, the level of an upper surface of a filling member is different between the effective pixel region and the peripheral region. Since the level is higher in the peripheral region than in the effective pixel region, in a technology disclosed in Japanese Patent Laid-Open No. 2009-164247, a dummy opening is provided in the peripheral region so as to reduce the difference in level that exists in a boundary portion between the effective pixel region and the peripheral region.

Since circuit wiring is provided in the peripheral region, it may be difficult in some cases to desirably form the dummy opening described in Japanese Patent Laid-Open No. 2009-164247. This limits the reduction of the difference in level of the upper surface of the filling member. Furthermore, such a difference in level causes a problem in particular when the filling member is removed until a base film is exposed, so that a plurality of light guiding members are formed. That is, when not only the excessive part of the filling member spread out of the openings on the image pickup region but also the filling member in the openings and the base film are removed, the length of the light guiding members becomes non-uniform in the image pickup region. Non-uniformity in the length of the light guiding members causes degradation of imaging performance such as variation in the optical interference conditions among the light guiding members.

SUMMARY OF THE INVENTION

In view of such a problem, the present technology provides an image pickup device, with which non-uniformity in the length of a plurality of light guiding members formed of a filling member is reduced and a good image is obtained.

In order to address the above-described problem, a method of manufacturing an image pickup device is proposed. The image pickup device includes a substrate and a plurality of light guiding members. The substrate has an image pickup region and a peripheral region. A plurality of photoelectric conversion portions are arranged in the image pickup region, and the peripheral region surrounds the image pickup region. The plurality of light guiding members are provided so as to correspond to the respective photoelectric conversion portions on the image pickup region. The method includes a step of forming a filling member such that the filling member covers a light guiding part and a peripheral part provided in a film. The light guiding part is positioned on the image pickup region and has a plurality of openings that correspond to the respective photoelectric conversion portions. The peripheral part is positioned on the peripheral region. The filling member fills in the plurality of openings. The method also includes a step of processing the filling member. The method also includes a step of forming the plurality of light guiding members, which is performed after the processing of the filling member has been performed, by a polishing process performed on the filling member so that the light guiding part is exposed. The plurality of light guiding members are part of the filling member and disposed in the plurality of openings. In the method, at a first point of time, which is between the forming of the filling member and the processing of the filling member, and at a second point of time, which is between the processing of the filling member and the forming of the plurality of light guiding members, the filling member has a first part positioned on the light guiding part and separated from the image pickup region by a base distance, a second part positioned on the peripheral part and separated from the peripheral region by the base distance, and a third part that is positioned between the first part and the image pickup region and fills in the plurality of openings. In the method, when S1is an area of the image pickup region, S2is an area of the peripheral region, V1Ais a volume of the first part at the first point of time, V2Ais a volume of the second part at the first point of time, V1Bis a volume of the first part at the second point of time, and V2Bis a volume of the second part at the second point of time, the following relationships, V1A/S1<V2A/S2and V1B/S1≧V2B/S2, are satisfied.

DESCRIPTION OF THE EMBODIMENTS

An embodiment of an image pickup device will be described below with reference to the drawings. In the following description, the same signs will denote the same components or portions throughout the drawings and redundant description thereof will be omitted.

FIG. 1Ais a schematic plan view of an image pickup device1. The image pickup device1has an image pickup region10and a peripheral region20. InFIG. 1A, a region surrounded by the one-dot chain line is the image pickup region10and a region defined between the one-dot chain line and the solid line, which indicates the outline of the image pickup device1, is the peripheral region20. A plurality of pixels11are arranged in a two-dimensional array in the image pickup region10, which is irradiated with light picked up as an image. Although 16 pixels11are arranged in a 4×4 array in the present embodiment, a multi-million or tens of multi-million pixels11may actually be arranged in an array. Signal generating units30generate electrical signals in accordance with signal charges of the pixels11. In the present embodiment, the signal generating units30are disposed in the image pickup region10corresponding to the pixels11.

Referring toFIG. 1A, signal processing units40, output units50, and control units60may be provided in the peripheral region20. The signal processing units40process signals generated by the signal generating units30. The output units50output the signals processed in the signal processing units40to the outside. The control units60control the signal generating units30and the signal processing units40. In the present embodiment, each signal processing unit40includes an amplifying circuit41, a conversion circuit42, and a horizontal scan circuit43. The amplifying circuit41includes a plurality of column amplifiers. The conversion circuit42includes a plurality of column analog to digital (AD) converters. The horizontal scan circuit43selects output from the conversion circuit42and outputs the selected output to the output unit50. Each output unit50includes electrode pads and a protection circuit. Each control unit60includes a vertical scan unit61, a timing generating circuit62, and so forth. Light shielded pixels, which include shielded photoelectric conversion portions, may be provided in the peripheral region20. The structure of the peripheral region20may be appropriately designed. At least part of the signal generating unit30may be provided in the peripheral region20, and at least part of the signal processing unit40may be provided in the image pickup region10.

FIG. 1Bis a schematic plan view of the image pickup region10, illustrating an enlarged view of four pixels in a 2×2 array. The pixel11includes a photoelectric conversion portion101. The signal generating unit30may include, for example, a transfer gate102, a floating diffusion region106, an amplifying transistor103, and a reset transistor104. The signal generating unit30may also include a selection transistor. These transistors may use a metal oxide semiconductor (MOS) transistor, which includes a diffusion region107used as a source, a drain, and a channel, and a polysilicon gate electrode. The signal generating unit30may be shared by a plurality of photoelectric conversion portions101as illustrated inFIG. 1B. Charge coupled devices (CCDs) may be provided in the image pickup region10so as to transfer signal charges to the peripheral region20.

FIG. 1Cis a schematic sectional view of a structure illustrated inFIG. 1Btaken along line IC-IC inFIG. 1B. The photoelectric conversion portion101is formed in a semiconductor substrate100. The photoelectric conversion portion101may be a thin-film semiconductor formed on an insulating substrate. A light guiding structure200that includes a plurality of light guiding members220is provided on a surface of the semiconductor substrate100, which serves as a light receiving surface. Furthermore, a high-refractive-index film240, a second lens250, a color filter270, and a first lens290are provided on the semiconductor substrate100. A first intermediate film230is provided between the light guiding structure200and the high-refractive-index film240. The first intermediate film230has a lower refractive index than that of the light guiding member220. The high-refractive-index film240has a higher refractive index than that of the first intermediate film230. A second intermediate film260is provided between the second lens250and the color filter270. The second lens250has a higher refractive index than that of the second intermediate film260. A third intermediate film280is provided between the color filter270and the first lens290. Each intermediate film may have the function of adjusting the distance between the lenses or the function of planarization.

The light guiding structure200includes a base film210and the light guiding member220surrounded by the base film210. The base film210may be a multilayer film or a single layer film. The base film210of the present embodiment has low-refractive-index layers that have a lower refractive index than that of the light guiding member220. The light guiding structure200guides light to the photoelectric conversion portion101by total reflection occurring at interfaces between the light guiding member220and each low-refractive-index layer. The base film210may include a high-refractive-index layer having a higher refractive index than that of the light guiding member220or an equal-refractive-index layer having a refractive index equal to that of the light guiding member220. However, in order to effectively guide light, the sum of the thicknesses of the low-refractive-index layers included in the base film210can be equal to or greater than a half of the entire thickness of the base film210.

The light guiding principle is not limited to the total reflection at the interface between the light guiding member220and the low-refractive-index layer. For example, light can be guided to the photoelectric conversion portion101by total reflection occurring between the light guiding member220and a low-refractive-index region, which is provided between the base film210and the light guiding member220and has a lower refractive index than the light guiding member220. In this case, the base film210does not necessarily include the low-refractive-index layer having a lower refractive index than that of the light guiding member220. The low-refractive-index region may be formed of a solid, a liquid, a gas, or vacuum.

Furthermore, the light guiding principle is not limited to total reflection. Light may be guided to the photoelectric conversion portion101by metallic reflection caused by a metal film provided between the base film210and the light guiding member220. In this case, the base film210does not necessarily include the low-refractive-index layer having a lower refractive index than that of the light guiding member220. Alternatively, the base film210itself may be formed of a metal film.

An outline of a method of forming the light guiding structure200applied to the manufacture of the image pickup device1is described with reference toFIGS. 2A to 2F.FIGS. 2A to 2Fare schematic sectional views of the image pickup device1during formation of the light guiding structure200.

The semiconductor substrate100that includes the image pickup region10and the peripheral region20is initially prepared. The photoelectric conversion portions101are disposed in the image pickup region10. A region of the semiconductor substrate100other than the image pickup region10is the peripheral region20. When S1is the area of the image pickup region10and S2is the area of the peripheral region20, the present embodiment can satisfy S1<S2. However, the present embodiment may satisfy S1≧S2. The base film210that covers the image pickup region10and the peripheral region20is formed on the semiconductor substrate100(FIG. 2A). As described above, this base film210is a multilayer film or a single layer film. Out of the base film210, a portion of the base film210that covers the image pickup region10is referred to as a light guiding part201and a portion of the base film210that covers the peripheral region20is referred to as a peripheral part202. The thickness of the light guiding part201is denoted by T. The thickness T is the distance from the image pickup region10to an upper surface of the light guiding part201.

Next, a plurality of openings216are formed in at least in the light guiding part201of the base film210(FIG. 2B). Each of the openings216is formed for a corresponding one of the photoelectric conversion portions101. The openings216may be through holes that penetrate through the base film210, and the bottoms of the openings216are defined by the semiconductor substrate100. Alternatively, the openings216may be bottomed holes that do not penetrate through the base film210, and the bottoms thereof are defined by the base film210. Dummy openings (not shown) may be formed in the peripheral part202of the base film210. The dummy openings may also be formed, for example, in the peripheral part202, corresponding to the light shielded pixels in the peripheral region20.

A filling member2201is formed as a film on the base film210(FIG. 2C) so as to fill in the openings216(and the dummy openings). A multilayer formed of the semiconductor substrate100and the base film210functions as a base body that supports the filling member2201. The filling member2201is disposed at positions away from the surface of the semiconductor substrate100by equal to or greater than a datum height HS. The filling member2201has a first part221, which corresponds to the image pickup region10, and a second part222, which corresponds to the peripheral region20. HSrepresents the distance (base distance) between the first part221and the image pickup region10and also represents the distance between the second part222and the peripheral region20. The distance HS, which represents the datum height, is equal to or greater than a distance T, which represents the thickness of the base film210. The first part221covers the light guiding part201, and the second part222covers the peripheral part202. The filling member2201also has a third part223and a fourth part224. The third part223and the fourth part224are disposed on the base film210at positions lower than the datum height HS. The third part223is positioned between the first part221and the image pickup region10, and the fourth part224is positioned between the second part222and the peripheral region20. The third part223covers the light guiding part201, and the fourth part224covers the peripheral part202. At least part of the third part223is positioned in the openings216and fills in the openings216. The entirety of the filling member2201disposed in the openings216is the third part223. The first part221is not disposed in the openings216. Although the datum height HSis set at a position further away from the semiconductor substrate100than the upper surface of the base film210in the present embodiment, the datum height HSmay be set on the upper surface of the base film210. In this case, the third part223is disposed only in the openings216, and the first part221is in contact with the light guiding part201. Also in this case, the fourth part224is not disposed when the dummy opening are not provided, and the fourth part224is disposed only in the dummy opening when the dummy opening is provided.

At a time the formation of the filling member2201as a film is completed as illustrated inFIG. 2C, when V1Ais the volume of the first part221, V2Ais the volume of the second part222, D1A=V1A/S1is defined as an index that represents the amount of the first part221per unit area for the entirety of the image pickup region10. Likewise, D2A=V2A/S2is defined as an index that represents the amount of the second part222per unit area for the entirety of the peripheral region20. The indices D1Aand D2Acorrespond to average heights of the surfaces of the first part221and the second part222from the datum height HS, respectively.

Here, when the filling member is formed as a film by using a typical deposition method, the density per unit area of the filling member on the image pickup region10is the same as that on the peripheral region20. Part of the filling member is positioned in the openings216and the dummy openings. It is impractical to form the dummy openings that have the same depth and diameter as those of the openings216of the light guiding part201and that are spaced at the same interval as that of the openings216over the entirety of the peripheral part202. Thus, the sum of the volumes of the openings216divided by the area S1is typically greater than the sum of the volumes of the dummy openings divided by the area S2. With this taken into consideration, D1A<D2Acan be satisfied. That is, in the filling member2201, with reference to the datum height HS, the average height of the surface of the second part222is higher than the average height the surface of the first part221.

Next, by processing the filling member2201, at least part of the second part222is removed (FIG. 2D). To do this, an etching process can be adopted. Other than the etching process, a polishing process or a reflow process may be adopted for this processing. Although the etching process can be performed while the first part221is protected by a mask, part of the first part221may be removed in the etching process. At the time the etching process for the filling member2201is completed and a resultant filling member2202has been formed as illustrated inFIG. 2D, when V1Bis the volume of the first part221, and the V2Bis the volume of the second part222, D1B=V1B/S1is defined as an index that represents the amount of the first part221per unit area for the entirety of the image pickup region10. Likewise, D1B=V2B/S2is defined as an index that represents the amount of the second part222per unit area for the entirety of the peripheral region20. The indices D1Band D2Bcorrespond to average heights of the surfaces of the first part221and the second part222with respect to the datum height HS, respectively.

The etching process is performed such that, when the relationship D1A<D2Ais satisfied with respect to the filling member2201not having undergone the etching process, the relationship D1B≧D2Bis satisfied with respect to the filling member2202having undergone the etching process. That is, in the filling member2202, with reference to the datum height HS, the average height of the surface of the second part222is equal to or lower than the average height of the surface of the first part221. The relationships D1A≧D1Band D2A>D2Bare naturally satisfied. In the filling member2202having undergone the etching process, the relationship D1B≧D2B≧D1B/2 can be satisfied.

Next, a polishing process is performed on the filling member2202so as to remove the first part221and the second part222(FIG. 2E). The polishing process may be a chemical mechanical polishing process (CMP process). Alternatively, a mechanical polishing process may be used. By removing the first part221from the filling member2202, a filling member2203, the surface of which is positioned at the datum height HS, is obtained. In the present embodiment, at the time the datum height HSis reached, part of the third part223remains at positions outside the openings216. At least part of the fourth part224is also removed. A difference in level HD, which is the difference between the level of the upper surface of the peripheral part202and the level of an upper surface of part of the third part223positioned outside the openings216can be expressed as HS−T. At this time, when D1B>D2B≧D1B/2 is satisfied, the peripheral part202of the base film210can be exposed as illustrated inFIG. 2E. The polishing rate in the polishing process is reduced when the amount of the filling member per unit area is increased. Thus, with regard to the first part221and the second part222, the second part222can be removed earlier.

The polishing process is further performed on the filling member2203, so that part of the third part223is removed. By doing this, the upper surface of the light guiding part201of the base film210is exposed. As described above, in the base film210, both the light guiding part201and the peripheral part202are exposed. Thus, the plurality of light guiding members220, which are independent of one another, can be formed on the image pickup region10(FIG. 2F).

When D1B≧D2Bis satisfied, the peripheral part202tends to be exposed before the light guiding part201is exposed. However, when D1B=D2B, in the base film210, the light guiding part201and the peripheral part202may be simultaneously exposed. Even when D1B>D2B, in the base film210, the light guiding part201and the peripheral part202may be simultaneously exposed. In the base film210, the part of the peripheral part202that is removed in the present embodiment is not necessarily removed.

Referring toFIGS. 3A to 3F, a method of forming the light guiding structure200different from the method illustrated inFIGS. 2A to 2Fis described.FIGS. 3A to 3Fcorrespond toFIGS. 2A to 2F. Since theFIGS. 3A,3B, and3C are respectively the same asFIGS. 2A,2B, and2C, description thereof is omitted.

Referring toFIG. 3D, as is the case withFIG. 2D, the filling member2201is subjected to the etching process, in which at least part of the second part222is removed. However, compared to the case illustrated inFIG. 2D, the amount by which the second part222is removed is reduced in the case illustrated inFIG. 3D. InFIG. 3D, the processed filling member2202satisfies the relationship D1B<D2B<D2A. A polishing process is performed on the filling member2202so as to remove the first part221and the second part222. In the present embodiment, the third part223is removed and, as a result, the light guiding part201is exposed. The polishing rate in the polishing process is reduced when the amount of the filling member per unit area is increased. Thus, with regard to the first part221and the second part222, the first part221can be rapidly removed. This tendency is more clearly observed in the case where S1<S2.

The polishing process is performed on the filling member2203so as to remove the second part222and the fourth part224. At the time the polishing process is performed on the filling member2203, the light guiding part201of the base film210is exposed. Thus, when the second part222and the fourth part224are removed, the third part223in the openings216and the light guiding part201of the base film210are also subjected to the polishing process. This may cause variation in the length of the light guiding members220. Such variation may lead to the difference in the degree of optical interference among the light guiding members220, and accordingly, cause unevenness of color within an image.

As described above, by performing the polishing process in a state in which the index D1Bis greater than the index D2B, variation in the light guiding members220can be reduced. Furthermore, in the base film210, by exposing the light guiding part201at the same time as the peripheral part202or after the peripheral part202has been exposed, variation in the light guiding members220can be reduced. As described above, since it is difficult to satisfy D1B≧D2Bonly with the dummy openings, the etching process can be performed on the second part222.

EXAMPLE

Next, a specific example of a method of manufacturing the image pickup device1will be described with reference toFIGS. 4A to 5F.FIGS. 4A to 4Cand5D to5F are schematic sectional views of the image pickup device1in different steps.

The image pickup device1includes the semiconductor substrate100. Among members of the image pickup device1as a semiconductor device, the semiconductor substrate100serves as a semiconductor portion. The semiconductor substrate100includes, for example, a substrate that has impurity regions formed in a semiconductor wafer by using a known semiconductor manufacturing process. The semiconductor substrate100may use a known semiconductor substrate, examples of which include a silicon substrate such as a silicon-on-insulator (SOI) substrate and a substrate in which an epitaxial layer is formed on a single-crystal body or substrate. A surface1001of the semiconductor substrate100serves as the interface between the semiconductor substrate100and an electrical insulator or conductor. Examples of the electrical insulator include a thermal silicon oxide film or the like that is disposed on and in contact with the semiconductor substrate100.

In the present example, the semiconductor substrate100has p-type semiconductor regions and n-type semiconductor regions. Also in the present example, the surface1001is the interface between the semiconductor substrate100and a thermal silicon oxide film (not shown) stacked on the semiconductor substrate100. The semiconductor substrate100has the image pickup region10and the peripheral region20. The image pickup region10includes a plurality of pixels, and the peripheral region20includes signal processing circuits that process electrical signals from the pixels. In the present example, the area S2of the peripheral region20is equal to or greater than one and a half times the area S1of the image pickup region10.

Step a: In a step a illustrated inFIG. 4A, the base film210is formed on the semiconductor substrate100. The step a is specifically described below.

In the semiconductor substrate100, p-type semiconductor regions and the n-type semiconductor regions are formed. Gate insulating films, gate electrodes, and wiring are formed on the semiconductor substrate100. In the image pickup region10, the photoelectric conversion portions101, the transfer gates102, the floating diffusion regions106, the amplifying transistors103, and the reset transistors (not shown) are formed. The photoelectric conversion portion101uses, for example, a photodiode. The photoelectric conversion portion101includes the n-type semiconductor region disposed in the semiconductor substrate100. Electrons as signal charges generated by photoelectric conversion are collected into the n-type semiconductor region of the photoelectric conversion portion101, in which the electrons are the majority charge carriers. The floating diffusion region106is the n-type semiconductor region. Electrons generated in the photoelectric conversion portion101are transferred to the floating diffusion region106. The floating diffusion region106is electrically connected to an input node of an amplifying unit. In the present example, the floating diffusion region106is electrically connected to the gate electrode of the amplifying transistor103through a plug300. Diffusion regions108for peripheral transistors are formed in the peripheral region20of the semiconductor substrate100. Source and drain regions for the peripheral transistors, which are included in the signal processing circuits, are formed in the diffusion regions108for the peripheral transistors. The semiconductor substrate100may have element isolation regions109. The element isolation regions109electrically isolate individual pixel transistors or the individual peripheral transistors from other elements. The element isolation regions109use shallow trench isolations (STIs). Alternatively, the element isolation regions109may be formed by a local oxidation of silicon (LOCOS) process.

Also in this step, a first protective layer2111and a second protective layer2112are formed on the semiconductor substrate100. For example, the first protective layer2111is a silicon nitride layer and the second protective layer2112is a silicon oxide layer. One or both of a silicon oxide layer and a silicon nitride layer may be additionally provided between the first protective layer2111and the semiconductor substrate100. The first protective layer2111and the second protective layer2112may have a function of reducing damage to the photoelectric conversion portions101caused in a later step. The first protective layer2111and the second protective layer2112may have an antireflective function. The first protective layer2111and the second protective layer2112may have a function of preventing metal from being contaminated in a silicide process. A third protective layer2113is formed on a side of the second protective layer2112opposite to the semiconductor substrate100side. The third protective layer2113is a silicon nitride film formed over the entire surface of the semiconductor substrate100and patterned so as to correspond to the individual photoelectric conversion portions101. The area of a piece of the third protective layer2113can be larger than the area of the base of a corresponding one of the openings216, which will be formed later. At least one of the first protective layer2111, the second protective layer2112, and the third protective layer2113may be omitted. A peripheral protective layer212is formed on the peripheral region20.

Furthermore, a plurality of interlayer insulating layers2131,2132,2133,2134, and2135are formed in order from a layer closer to the semiconductor substrate100. The interlayer insulating layers2131to2135are formed of, for example, silicon oxide. The interlayer insulating layers2131to2135can function as low-refractive-index layers that surround the light guiding members220of the light guiding structure200.

In this process, contact plugs300, a first wiring layer301and a second wiring layer302are formed. The contact plugs300are formed after contact holes are formed in the interlayer insulating layer2131. In the present example, the contact plugs300are formed of tungsten. Next, the interlayer insulating layer2132, the first wiring layer301, the interlayer insulating layer2133, the interlayer insulating layer2134, and the second wiring layer302are formed in this order. In the present example, the first wiring layer301and the second wiring layer302are formed of copper. The first wiring layer301is formed by a single damascene method, and the second wiring layer302is formed by a dual damascene method. Alternatively, when the wiring layers are formed of aluminum, the wiring can be formed by using a known etching process. A plurality of silicon nitride layers214are formed between the interlayer insulating layers2131to2135. Each of the silicon nitride layers214functions as an anti-diffusion layer or a etch stop layer. The silicon nitride layers214have a refractive index equal to or higher than that of the light guiding member220. The silicon nitride layers214are each formed to have a sufficiently small thickness compared to a low-refractive-index layer. The silicon nitride layer serving as an anti-diffusion layer or an etch stop layer may be substituted by a silicon carbide layer. A planarization process is performed on each layer according to need by using the CMP method or the like.

Next, a reference layer215is formed on the interlayer insulating layer2135. The material of the reference layer215can be selected such that, in the polishing process, the polishing rate of the reference layer215is lower than the polishing rate of the filling member for the openings216, which will be disposed in a later step. As such a material of the reference layer215, a carbon-containing silicon oxide or a carbon-containing silicon nitride can be used in the case where the CMP process is performed in the polishing process using silica slurry. A silicon oxide layer, a silicon nitride layer, or a silicon carbide layer can be used as the reference layer215. Thus, the base film210has been formed. The base film210is a multilayer film, the uppermost layer of which is the reference layer215. Although the reference layer215can be the uppermost layer of the multilayer film and serve as the upper surface of the base film210, the reference layer215is not necessarily the uppermost layer. The thickness of the base film210that includes layers from the protective layer2111to the reference layer215is denoted by T.

Step b: In a step b illustrated inFIG. 4B, the plurality of openings216are formed in the light guiding part201of the base film210from the upper surface of the base film210. The openings216are formed at positions superposed with the plurality of photoelectric conversion portions101. An etching mask pattern (not shown) is initially stacked on the base film210on the side of the base film210opposite to the semiconductor substrate100. The etching mask pattern has openings corresponding to the openings216. The etching mask pattern is, for example, a photoresist patterned by photolithography. Next, with the etching mask pattern used as a mask, at least the reference layer215is etched, and furthermore, the plurality of interlayer insulating layers2131to2135and the plurality of anti-diffusion layers214are etched. By doing this, the openings216are formed. The openings216may be formed by a plurality of times of etching performed under different conditions. After the etching has been performed, the etching mask pattern may be removed. In the case where the third protective layer2113is provided, the etching can be performed in the process illustrated inFIG. 4Buntil the third protective layer2113is exposed. The etching rate of the third protective layer2113can be lower than the etching rate of the interlayer insulating layer2131, which is formed on the third protective layer2113. In the case where the interlayer insulating layer2131is a silicon oxide layer, it is sufficient that the third protective layer2113be a silicon nitride layer or a silicon oxynitride layer. The third protective layer2113may be exposed by a plurality of times of etching performed under different conditions.

Regarding the sectional shape of the openings216, the openings216are not necessarily penetrate through all the interlayer insulating layers2131to2135. The interlayer insulating layers2135,2134,2133, and2132may define the side surface of the openings216and the interlayer insulating layer2131may define the bottom surface of the openings216. Regarding the shape of the openings216in plan view, the boundary of each opening216has a closed loop shape such as a circle or a polygon. Alternatively, the openings216may have groove-like shape in plan view that extends along the plurality of photoelectric conversion portions101. That is, the base film210has the opening216when, on a plane parallel to the surface1001, a region in which the base film210is not provided is surrounded by a region or interposed between regions in which the base film210is provided.

Regarding the positions of the openings216in a plane, at least part of each opening216is superposed with a corresponding one of the photoelectric conversion portions101in plan view. That is, when one of the openings216and a corresponding one of the photoelectric conversion portions101are projected onto a single plane, there is a region in which the projection of the opening216and the projection of the photoelectric conversion portion101exist on the single plane. The interval at which the openings216and the photoelectric conversion portions101are arranged is, for example, equal to or smaller than 2 μm.

In the present example, the openings216are formed in regions superposed with the photoelectric conversion portions101. The openings216are not formed in the peripheral region20. However, openings may be formed in the peripheral region20. Such openings are dummy openings because they do not guide light that contributes to imaging. In this case, density of the openings216formed in the light guiding part201may be higher than that of the dummy openings formed in the peripheral part202. The density of the openings can be determined by the number of the openings216or the dummy openings provided per unit area. The density of the openings216can be alternatively determined by the ratio of the area occupied by the openings216.

Step c: In a step c illustrated inFIG. 4C, the filling member2201that fills in the plurality of openings216is formed as a film on the base film210. The filling member2201covers the light guiding part201and the peripheral part202. The filling member2201can be formed by depositing a filling material by using a method such as a chemical vapor deposition (CVD) method or a sputtering method. The filling member2201can also be formed of an organic material by using a coating method such as spin coating. The filling member2201may be formed through a plurality of steps or may be formed of a plurality of materials. For example, when the filling member2201is formed, in a preceding step, either or both of the material and the conditions can be selected so as to improve the adherence of the filling member2201to the underlying material, and either or both of the material and conditions can be selected so as to allow the filling member2201to more easily fill in the openings216in a following step. Also in the step c, in the case where the first interlayer insulating layer2131is etched until the third protective layer2113is exposed, the filling member2201can be in contact with the third protective layer2113.

It is sufficient that the material of the filling member2201have a higher refractive index than those of at least one of the layers of the base film210, for example, the interlayer insulating layers2131to2135. When the interlayer insulating layers2131to2135are formed of a silicon oxide having a refractive index of 1.4 to 1.6, the material of the filling member2201may be a silicon nitride layer having a refractive index of 1.7 to 2.3. The filling member2201is not necessarily formed of an inorganic material. The filling member2201may be formed of an organic material. The filling member2201may be formed of an organic material containing dispersed inorganic particles. The refractive indices of the materials can be appropriately set by adjusting the types, contents, composition ratios, and the film densities of impurities. Also, by increasing the hydrogen content of silicon nitride, dangling bond of a substrate can be terminated due to a hydrogen supply effect. This can reduce noise such as white flaws. The material of the filling member2201can be appropriately selected with consideration of optical characteristics such as the difference in refractive index and ease of manufacture.

Here, the positional relationships among the plurality of interlayer insulating layers2131to2135and the filling member2201disposed in the openings216are described. In a plane, a region where the filling member2201is provided is surrounded by a region or interposed between regions where the plurality of interlayer insulating layers2131to2135are provided. In other words, the first part of the plurality of interlayer insulating layers2131to2135, the second part of the plurality of interlayer insulating layers2131to2135, the second part being different from the first part, and portions of the filling member2201disposed in the openings216are arranged in a direction that intersects a direction in which each photoelectric conversion portion101and the filling member2201disposed in a corresponding one of the openings216are arranged. The direction that intersects the direction in which each photoelectric conversion portion101and the filling member2201disposed in a corresponding one of the openings216are arranged is, for example, a direction parallel to the surface1001of the semiconductor substrate100.

The filling member2201is disposed at positions on the semiconductor substrate100, the positions being superposed with the photoelectric conversion portions101. The filling member2201is surrounded by the plurality of interlayer insulating layers2131to2135. The material of the filling member2201can have a higher refractive index than those of the plurality of interlayer insulating layers2131to2135. With such relationships of the refractive indices, out of light incident upon the filling member2201, the amount of light that leaks to the plurality of interlayer insulating layers2131to2135can be reduced. Accordingly, when at least part of the filling member2201is superposed with the photoelectric conversion portions101, the amount of light incident upon the photoelectric conversion portions101can be increased.

The filling member2201does not necessarily have a higher refractive index than those of the plurality of interlayer insulating layers2131to2135. The filling member2201sufficiently functions as the light guiding member220of the light guiding structure200when the filling member2201has a structure in which light incident upon the filling member2201does not easily leak to the surrounding base film210. For example, light reflecting films may be formed on the side walls of the openings216. Alternatively, low-refractive-index films, which have a lower refractive index than that of the filling member2201, may be formed on the side walls of the openings216, so that light is introduced by total reflection at the interface between the filling member2201and each low-refractive-index film. Alternatively, vacuum spaces or gaps filled with a gas may be formed between the portions of the filling member2201disposed in the openings216and the plurality of interlayer insulating layers2131to2135. The gaps each function as a low-refractive-index region as is the case with the above-described low-refractive-index film. As described above, when total reflection at the interface between the filling member2201and the low-refractive-index layers of the base film210is not utilized, which one of the refractive indices of the material of the filling member2201and the material of the base film210is higher than the other does not matter.

In the present example, the datum height is set in a plane that includes the upper surface of the reference layer215. That is, the datum height HScoincides with the thickness T of the base film210. The filling member2201includes the first part221, the second part222, and the third part223. The first part221is positioned on part of the reference layer215on the light guiding part201. The second part222is positioned on part of the reference layer215on the peripheral part202. The third part223is positioned in the openings216. The first part221is in contact with the reference layer215. The first part221further includes part of the filling member2201positioned on the third part223. In the case where the dummy openings are provided in the peripheral part202, the filling member2201can include the fourth part224illustrated inFIG. 2C.

In the present example, the dummy openings (not shown) having the same shape as that of the openings216are formed in the light shielded pixel portions and are not provided in other peripheral circuit portions. Thus, the filling member2201is formed as a film such that V1A/S1<V2A/S2is satisfied where S1is the total area of the image pickup region10, V1Ais the total volume of the filling member2201disposed above the reference layer215in the image pickup region10, S2is the total area of the peripheral region20, and V2Ais the total volume of the filling member2201disposed above the reference layer215in the peripheral region20.

Examples of the method of measuring the volume of the filling member disposed above the reference layer215are as follows. The section of the first part221is observed so as to analyze the shape of the filling member. The volume of the first part221is calculated in accordance with the analyzed shape. When the shape is analyzed in a plurality of sections, the precision with which the volume of the first part221is calculated can be improved. As for the portion disposed in the peripheral region20, the volume can be calculated by measuring the thickness of the flat portion of the filling member by using spectroscopic ellipsometry. Other than the above-described methods, it is also possible that the difference between the sums of the volumes of the openings216and the dummy openings can be regarded as the difference between the volumes of the first part221and the second part222. The volume of each opening216can be approximated by the product of the diameter and depth of the opening216. The area S2of the peripheral region20is given by S2=S−S1where S is the area of the chip.

Step d: In a step d illustrated inFIG. 5D, a portion of the filling member2201positioned on the peripheral part202is removed by an etching process. Although dry etching such as plasma etching can be used in the etching process, wet etching may instead be used. An etching mask (not shown) is initially stacked on the filling member2201. The etching mask has a pattern, for example, that covers at least part of the first part221and that does not cover at least part of the second part222. Next, with this etching mask, at least part of the second part222of the filling member2201is removed by etching. The part of the filling member2201to be removed is described below when the part of the filling member2201is seen in plan view and in the depth direction.

At least part of the second part222is removed in plan view. The second part222can be subjected to the etching process in a region equal to or greater than a half of the second part222(the area equal to or greater than S2/2 where S2is the area of the peripheral region20). The entirety of the second part222can be subjected to the etching process. In the present example, out of the filling member2201, a portion of the filling member2201disposed in the peripheral region20are entirely etched. In other words, no etching mask is provided over the peripheral region20. As described above, the area subjected to etching can be large. Alternatively, only part of a portion of the filling member2201disposed in the peripheral region20can be etched. Also in this step, part of a portion of the filling member2201disposed in the image pickup region10may be removed.

In the present example, the filling member2202is formed by the etching process such that V1B/S1≧V2B/S2is satisfied where S1is the total area of the image pickup region10, V1Bis the total volume of the filling member2202disposed above the reference layer215in the image pickup region10, S2is the total area of the peripheral region20, and V2Bis the total volume of the filling member2202disposed above the reference layer215in the peripheral region20.

Step e: In a step e illustrated inFIG. 5E, the polishing process is performed on the filling member2202and a portion of the filling member2202positioned on the peripheral part202is removed by the polishing process.FIG. 5Eillustrates an intermediate step of the polishing process after the polishing process has been started with V1B/S1≧V2B/S2satisfied. The peripheral part202is exposed and the filling member2203remains on the light guiding part201. The polishing process is completed in a state in which the light guiding part201is exposed. The polishing process can be completed at the time the reference layer215is exposed or the reference layer215that has been exposed remains. Alternatively, the polishing process may be completed at the time the reference layer215has been removed and the interlayer insulating layer2135is exposed. Thus, the plurality of light guiding members220are arranged on the image pickup region10. The light guiding members220are arranged at an interval of, for example, equal to or smaller than 2 μm.

Step f: In a step f illustrated inFIG. 5F, optical, chemical, mechanical, and electrical structures are appropriately formed on the light guiding structure200. For example, in a step illustrated inFIG. 5F, the first intermediate film230, a third wiring layer303, and the interlayer lenses250are formed. After that, color filters, microlenses, and so forth are formed.

FIG. 6is a graph illustrating the relationship between the removal amount in the etching process and the difference in level in the polishing process. The vertical axis in the graph ofFIG. 6represents the height difference HDbetween the surface of the filling member2203in the image pickup region10and the surface of the base film210(surface of the reference layer215) in the peripheral region20at the time when the reference layer215in the peripheral part202of the base film210is exposed in the step e. In the present example, the height difference is measured by using an atomic force microscope (AFM). Alternatively, the height difference can be measured by, for example, sectional observation with a scanning electron microscope (SEM). The horizontal axis represents the size relationship D2B/D1Bbetween the amount per unit area of the first part221and the amount per unit area of the second part222after the etching process has been performed. A value greater than 0 in the vertical axis indicates that the filling member2203remains above the reference layer215as illustrated in, for example,FIG. 2E. A value smaller than 0 in the vertical axis indicates that the light guiding part201and the light guiding members220are recessed relative to the peripheral part202as illustrated inFIG. 3F. As can be understood fromFIG. 6, the graph illustrates a tendency in which, with the D2B/D1B=1.0 as a boundary, the filling member2203remains on the light guiding part201at the time the peripheral part202is exposed when D2B/D1B<1.0. Since D2B/D1Bis significant to the first decimal place, when D2B/D1Bis equal to or greater than 0.95 and smaller than 1.05, D2Band D1Bcan be regarded as equal to each other. In comparison with damage to the light guiding part201, damage to the peripheral part202is allowable. When D2B/D1B≧0.5, the height difference does not practically cause problems. When the D2B/D1B≧0.7, a very high flatness can be ensured such that unevenness in color or the like does not occur even in consideration of the formation of the color filters and the like to be performed later.

Typically, a plurality of the image pickup devices1are formed on a semiconductor wafer. The peripheral regions20of the image pickup devices1are arranged adjacent to one another with scribe regions therebetween. Referring toFIG. 1A, the peripheral region20is defined by the two-dot chain line. A region between the solid line that indicates the outline of the image pickup device1and the two-dot chain line is a scribe region for obtaining the plurality of image pickup devices1from a semiconductor wafer. By dividing (dicing) the semiconductor wafer along the scribe regions, the plurality of image pickup devices1(chips) can be obtained. The area of each image pickup device1(the area of the chip) is represented by S1+S2. Although there may be a slight difference between central and peripheral portions of the above described semiconductor wafer, the relationship between the image pickup region10and the peripheral region20, and the relationships among the corresponding portions such as the light guiding part201, the peripheral part202, the first part221, and the second part222can be completely established within a region allocated for each image pickup device1.

This application claims the benefit of Japanese Patent Application No. 2012-174844 filed Aug. 7, 2012, which is hereby incorporated by reference herein in its entirety.