Predetermined voltage applications for operation of a flat panel display

A flat panel display comprises: a cathode; an anode having a plurality of associated pixels; and, a control frame. The display has nanotubes disposed thereon; such that when a predetermined voltage is applied to the frame the nanotubes emit electrons that strike the pixels thus increasing the brightness of a displayed image. The display also includes a plurality of TFT circuits, each being associated with a corresponding one of the pixels. Increasing the predetermined voltage, after the threshold has been reached, will increase the quantity of electrons emitted by the nanotubes and increase the brightness of the image displayed. This voltage applied to the frame and associated nanotubes may be a pulsed voltage.

FIELD OF THE INVENTION

This application is generally related to the field of displays and more specifically to the displays using Thin Film Transistor (TFT) technology and nanotubes.

BACKGROUND OF THE INVENTION

Flat panel display (FPD) technology is one of the fastest growing technologies in the world with a potential to surpass and replace Cathode Ray Tubes (CRTs) in the foreseeable future. As a result of this growth, a large variety of FPDs exist, which range from very small virtual reality eye tools to large TV-on-the-wall displays.

Various types of displays exist, such displays utilizing both hot and cold cathodes that produce electrons that activate phosphor. In the prior art, a grid or mesh structure is disposed between the cathode and anode elements. Such structures are depicted in various patents issued by Copytele, Inc., the assignee herein, including, for example, U.S. Pat. Nos. 4,655,897, 4,742,345, 5,053,763, and 5,561,443, the subject matter of these patents is hereby incorporated by reference herein in their entireties.

Display devices that utilize nanotubes, as well as other field emission devices, have an inherent threshold at which emission will commence. For nanotube based display devices, the threshold is a negative voltage which is a function of the spacing between the nanotubes and the electrode upon which the electrons emitted by the nanotube will impinge. Typically, a DC voltage has been applied to generate electron emission from the nanotubes, such that the nanotube-based FED essentially operates as an electron gun of a CRT. Alternative mechanisms for operating a display device are desired.

SUMMARY OF THE INVENTION

According to an embodiment of the invention, a device useful as a flat panel display, includes an electron emission system comprising nanotubes, a pixel control system with each pixel containing phosphor and with pixels having memory. Operating the device by applying a pulsed voltage to the nanotubes in synchronism with a frame pulse for writing information to the pixel causes a desired image to be displayed on the device.

A flat display comprises: a cathode; an anode having a plurality of associated pixels; and, a control frame having nanotubes disposed thereon; and that when a negative voltage pulse is applied to the frame, the nanotubes emit electrons that strike the pixels thus increasing the brightness of a displayed image.

In another embodiment of the invention, a threshold voltage associated with nanotube electron emission is a negative DC voltage the magnitude of which is a function of the spacing between the nanotubes and the anode electrode upon which the electrons emitted by the nanotubes will impinge.

In yet another embodiment of the invention, increasing the negative potential to the nanotubes, after the threshold has been reached, will increase the quantity of electrons emitted by the nanotubes, and therefore, will increase the brightness of the image displayed. In still another embodiment of the invention, a pulsed voltage is applied to the frame and associated nanotubes in order to increase the operational efficiency and the life of the display.

It is to be understood that these drawings are solely for purposes of illustrating the concepts of the invention and are not drawn to scale. The embodiments shown herein and described in the accompanying detailed description are to be used as illustrative embodiments and should not be construed as the only manner of practicing the invention. Also, the same reference numerals, possibly supplemented with reference characters where appropriate, have been used to identify similar elements.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Before embarking on a more detailed discussion, it is noted that passive matrix displays and active matrix displays are FPDs that are used extensively in various display devices, such as laptop and notebook computers, for example. In a passive matrix display, there is a matrix of solid-state elements in which each element or pixel is selected by applying a potential voltage to corresponding row and column lines that collectively form the matrix. In an active matrix display, each pixel is further controlled by at least one transistor and a capacitor that is also selected by applying a corresponding row and column lines.

Referring now toFIGS. 1 and 2, a control frame220(120ofFIG. 1) surrounds each pixel in a matrix display and is disposed in an area between the pixels (e.g., on an insulating substrate over the respective columns and rows). The control frame220includes a plurality of conductors230and240arranged in a matrix having parallel horizontal conductors240and parallel vertical conductors230. Each pixel250is bounded by the intersection of vertical and horizontal conductors such that the conductors surround the corresponding pixels to the right, left, top, and bottom in a matrix fashion. One or more conductive pixel pads are electrically connected to the control frame. The control frame may be fabricated of a metal including, for example, chrome, molybdenum, aluminum, and/or combinations thereof.

The control frame can be formed using standard lithography, deposition and/or etching techniques.

In one exemplary configuration, control frame conductors parallel to columns and rows are electrically connected together, and a voltage is applied thereto (FIG. 2). In another exemplary configuration, conductors parallel to columns are electrically connected together, and have a voltage applied thereto (FIG. 3). Conductors parallel to the rows are also connected together, with a voltage applied thereto. In yet another exemplary configuration, a voltage is only applied to one of the parallel rows or columns of conductors.

Such a control frame can accommodate carbon nanotube electron emission structures, and be suitable for operation at low voltages, such as at a voltage of less than around 40 volts. According to an embodiment of the present invention, the electron emitting structures may take the form of nanostructures, such as carbon nanotubes. The diameter of a nanotube is typically on the order of a few nanometers. According to an embodiment of the present invention, single-wall carbon nanotubes (SWNTs) and/or multiple wall carbon nanotubes (MWNTs) may be used. The nanostructures may be applied to the control frame using any conventional methodology, such as spraying, growth or printing, for example.

FIG. 1illustrates a schematic cross-sectional view of an FPD100useful for implementing the present invention. In the exemplary embodiment, display100is composed of an assembly110that includes an anode. TFT circuitry200, and a control frame structure120disposed on anode passivation layer130. TFT circuitry200may be omitted where FPD100is a passive X-Y matrix-based display. Control frame120substantially surrounds each of a plurality of pixel elements140/180as shown inFIGS. 2 and 3and supports electron emitting nanotubes. In the illustrated embodiment, the pixel metal pads140operate as the anode, which attracts electrons emitted by frame120supported emitters, e.g., carbon nanotubes or other emitters.

Conductive pixel pads140are fabricated in a matrix of substantially parallel rows and columns on a substrate150using conventional fabrication methods. Substrate150may be formed of a transparent material, such as glass, or a flexible material (such as a plastic with no internal outgassing during sealing and vacuumization processing), but may be opaque.

Conductive pixel pads140may be composed of a transparent conductive material, such as ITa (Indium Titanium Oxide) or a non-transparent conductor such as Chrome (Cr), Moly Chrome (MoCr) or aluminum. Deposited on each conductive pixel pad140is a phosphor layer180. Each phosphor layer180is selected from materials that emit light190of a specific color, wavelength, or range of wavelengths. In a conventional RGB display, phosphor layer180is selected from materials that produce red light, green light or blue light when struck by electrons. In the illustrated embodiment, light (i.e., photons) is emitted in the direction of substrate170for viewing. If the pixel metal is of a transparent (or translucent) material (such as ITO) rather than opaque, light emissions190may be transmitted in both the directions of substrates150and170(rather than being reflected via the pixel metal towards substrate170only, for example).

FPD100also includes conductive pixel column and row addressing lines160associated with each of the corresponding conductive pixel pads140. The pixel row and column addressing lines may be substantially perpendicular to one another as shown inFIGS. 2 and 3. Such a matrix organization of conductive pixel pads and phosphor layers allows for X-Y addressing of each of the individual pixel elements in the display as will be understood by those possessing an ordinary skill in the pertinent arts.

Where FPD100takes the form of an active display, associated with each conductive pixel pad140/phosphor layer180pixel is a TFT circuit200that operates to apply an operating voltage to the associated conductive pixel pad140/phosphor layer180pixel element. TFT circuit200operates to apply either a first voltage to bias an associated pixel element to maintain it in an “off” state or a second voltage to bias the associated pixel element to maintain it in an “on” state, or any intermediate state. In this illustrated case, conductive pixel pad140is inhibited from attracting electrons when in an “off” state, and attracts electrons when in an “on” or any intermediate state. In such a case, TFT circuitry200biasing conductive pixel pad140provides for the dual functions of addressing pixel elements and maintaining the pixel elements in a condition to attract electrons for a desired time period, i.e., time-frame or sub-periods of time-frame.

Substrate170, which serves to confine the FPD housing in an evacuated environment may be made of a transparent (or at least translucent) material, such as glass or flexible material, but alternatively may be opaque.

In the illustrated embodiment of the present invention, substrate170supports a conductive layer172. Layer172may be composed of a transparent conductor, such as ITO (Indium Titanium Oxide), or another conductive material, for example. In operation, conductive layer172may be biased to around 15-30 Volts. The layer172can be used for other purposes in an active or passive display.

Referring no also toFIG. 2, there is shown a top plan view of a control frame220suitable for use as control frame120FIG. 1. Control frame220includes a plurality of conductors arranged in a rectangular matrix having parallel vertical conductive lines230and parallel horizontal conductive lines240, respectively. The conductive lines230are sometimes referred to as columns, while lines240are referred to as rows. Each pixel250(e.g. pad140and phosphor180ofFIG. 1) is bounded by vertical and horizontal conductors or lines230,240such that the conductors substantially surround each pixel250to the right, left, top, and bottom. One or more conductive pads260electronically connect conductive frame220to a conventional power source. In the illustrated embodiment ofFIG. 2, four conductive pads260are coupled to the conductive lines230,240of frame220. In an exemplary embodiment, each pad260is around 100×200 micrometers (microns) in size. In the embodiment ofFIG. 2, a first stripe172(FIG. 1) may be substantially aligned with pixels250in “Row1”, a second strip172(FIG. 1) may be substantially aligned with pixels250in “Row2”, and so on. Thus, the conductor (ITO) on substrate170may be a series of row/lines.

FIG. 3shows another exemplary configuration of a control frame structure similar to that ofFIG. 2(wherein like references numerals are used to indicate like parts); but wherein two of the pads250ofFIG. 2are replaced by a single conductive bar or bus260′. The conductive bar260′ is coupled to each of the parallel horizontal conductive lines240a,240b,240c. . .240nat corresponding positions260a,260b,260c. . .260nalong the bar. In the illustrated configuration, the row lines are substantially identical to one another and interconnect to the bar at uniform spacings along the length of the bar. This configuration provides for an equipotential frame configuration with minimal voltage drops as a function of frame position. Again, in the embodiment ofFIG. 3, a first stripe172(FIG. 1) may be substantially aligned with pixels250in “Rox2”, and so on.

In the illustrated embodiments, control frame220(or220′) is formed as a metal layer above the final passivation layer (e.g.130,FIG. 1). Pads260and metal lines that provide the control frame structure220remain free from passivation in the illustrated embodiment. In an exemplary configuration, the control frame metal layer has a thickness of less than about 1 micron (urn), and a width on the order of about 16-19 microns, although other thicknesses and widths may be used depending on particular design criteria.

While the vertical line conductors230and horizontal line conductors240frame each pixel250above the plane of the pixels250in the illustrated embodiment (see, e.g.,FIG. 1), other configurations are contemplated, such as where the conductors are disposed in the same plane as the pixels. Further yet, conductors230,240may be connected in a number of configurations. For example, in one configuration, all horizontal and vertical conductors are joined together as shown inFIG. 2and a voltage is applied to the entire control frame configuration. In another configuration, all horizontal conductors240are joined and separately all vertical conductors230are joined. In this connection configuration the horizontal conductors240and vertical conductors230are not electrically interconnected. Thus, a voltage may be applied to the horizontal conductor array, and a separate voltage may be applied to the vertical conductor array. Other configurations are also contemplated, including for example, a configuration of all horizontal conductors only, or a configuration of all vertical conductors only. For example, the control frame may include only metal lines parallel to the columns or only metal lines parallel to the rows.

Referring toFIG. 1, it is indicated that a voltage equal to γpixel (low)−(γTHN) may be applied to the frame100, where (γTHIN) represents the nanotube183emitting threshold voltage and γpixel (low) represents the minimal pixel voltage. As seen inFIG. 1carbon nanotubes183are positioned on the control frame. They can be positioned on the row conductors at an X-Y intersection or anywhere on the display. This voltage may serve to keep the nanotube structures183to just below the electron emitting threshold when the pixel voltage is in it's “OFF” state. This permits the pixel voltage from the “OFF” state to the “ON” state and all voltages in between to cause changes in brightness. The nanotubes183have an inherent threshold at which electron emission will commence and as that threshold is reached and exceeded electrons travel from their location on the frame200(120ofFIG. 1) (220ofFIG. 2) (220′ ofFIG. 3) towards the anode. A least voltage applied to the control frame100has the effect of causing sufficient electrons to flow from the nanotubes183to the anode phosphor layer180or pixel element to produce a measurable increase in the be of the display. The voltage is essentially above the voltage (γPIXEL (low)−(γTHN)), i.e. the potential difference between the threshold voltage and the pixel voltage. The potential applied to the frame220(FIGS. 2 & 3) is a negative voltage having a magnitude which is a functional of the spacing between the nanotubes183and phosphor layer pixel element180upon which the electrons emitted by the nanotubes183will impinge. It has been found that increasing this negative v potential, after the threshold has been reached, will increase the quantity of electrons emitted by the nanotubes183and in the of the display using phosphor to produce the d increase the brightness of the image displayed.

It has been discovered that a pulsed voltage of the proper polarity applied to the frame120(220ofFIG. 2) (220′ ofFIG. 3) causes the nanotubes183to emit electrons which increases the operational efficiency and the life expectancy of the display. Those skilled in the art of electronic circuit design are familiar with the design, construction and operation of circuits that produced pulsed voltages. For purposes of explanation and not limitation,FIG. 4illustrates a pulse generator205that outputs at output terminal225a rectangular wave that switches between zero (0) and five (5) volts. Level shifters230,240produce the wave shapes illustrated inFIG. 6B, C respectively. The pulse circuit illustrated inFIG. 4thereby supplies to the frame120ofFIG. 1,220of FIGS.2and220′ ofFIG. 3a threshold voltage300as illustrated inFIG. 5having an on/off period or duty cycle that causes the periodic emission of electrons from the nanotubes183disposed on the frame.M8 to travel to the phosphor layer pixel element180.

The flat panel display described herein comprises: the substrate104; substrate106having a plurality of associated phosphor layer pixel elements180; and, control frame220having nanotubes183disposed thereon; such that when a least voltage is applied to the frame220ofFIG. 2the nanotubes183emit electrons that strike the pixels thus increasing the brightness of a displayed image195. Referring toFIG. 8display drivers605apply the desired data information615to each display pixel to produce the desired image within the timing constraints illustrated inFIG. 7. Each phosphor layer pixel element180has memory regarding the last data information supplied by the drivers605, during the preceding scan of the matrix. In synchronism with a frame start pulse as shown inFIG. 7Athe controller (not shown) activates a “display off” signal502(FIG. 7B) to activate the column display drivers605and applies the data information615to the memory630of each pixel650. The display off signal also activates low mode as shown inFIG. 7Cduring a time interval510the voltage applied to the frame220thereby nanotubes183is at a value that causes no emission. After data615has been written to each of the pixel memory630the controller “display off” signal504(FIG. 7B) causes the driver605outputs to go to a low and pulses the frame and associated nanotubes183with a negative voltage during a time interval520(FIG. 7C) to cause the nanotubes to emit electrons. The image is then written in accordance to the data last applied to the pixel memory630. The ratio of nanotube183“on” time to “off” time is determined by the controller to produce the desired image brightness as efficiently as possible. Additionally, the least voltage pulsed rectangular wave has a duty cycle chosen dependent upon producing the desired image brightness as efficiently as possible.

Referring toFIG. 9there is shown a circuit diagram of a PIXEL and FRAME DRIVER. It is noted that thin film transistors (TFTs) are employed but any active device as FET's, MOSFET's and soon can be used. A first TFT (Q1)1310has the gate electrode coupled to γrow, which the voltage is used to select rows of the display. The TFT has output electrodes as a source and drain. In any event these terms can be interchanged. One terminal of TFT1310is connected to a signal designated as γcol. which is the column driver voltage. The output of TFT1310is coupled to the gate electrode of TFT1330(Q2). The drain or output of TFT1330is coupled to an operating potential γanode. A capacitor310(CST) couples the drain of1330to the gate input of TFT1330. The source of TFT1330is connected to pixel1250surrounded by control frame1800. The frame input1810is connected to terminal1820on the junction between outputs of TFT1340(Q3) and TFT1380(Q4). TFT1340has the gate coupled to the output of a delay circuit1381. The gate electrode of TFT1380is coupled to the output of a delay circuit1382. The inputs of delay circuit1381and1382are coupled to a signal input γsync. This is the synchronizing display signal as seen TFT1340and1380are connected in series between a positive voltage +γframe and a negative voltage −γframe. The TFT are of opposite conductivity as one is N-Type and the other is P-Type. The junction1820is the terminal connected to the drain of Q3to the drain of Q4. Thus fromFIG. 9it is seen that when a Row X and a Column Y is selected (X, Y) transistor1310turns on activation transistor1330an applying voltage to pixel1250. The sync signal (FIG. 7A) is applied to the circuit ofFIG. 9and generates the frame signal (FIG. 7C) during internal510(FIG. 7C) Q1and Q2writes the data relative to the image to be displayed and the information is stored in capacitor CST(310) on each pixel. During the internal γframe is positive (510ofFIG. 7C) and the nanotubes do not emit between successive frames γframe is new (520FIG. 7C), the nanotubes emit and the stored data is displayed

While there has been shown, described, and pointed out fundamental novel features of the present invention as applied to preferred embodiments thereof, it will be understood that various omissions and substitutions and changes in the apparatus described, in the form and details of the devices disclosed, and in their operation, may be made by those skilled in the art without departing from the spirit of the present invention. It is expressly intended that all combinations of those elements that perform substantially the same function in substantially the same way to achieve the same results are within the scope of the invention. Substitutions of elements from one described embodiment to another are also fully intended and contemplated.