Transmitting device, receiving device and transmitting/receiving system

A transmitting device has a transmission data generating part and an output buffer part. The transmission data generating part transmits a data and a clock, which are to be transmitted to a receiving device, and outputs them to the output buffer part. The output buffer part includes a data transmitting part and a clock transmitting part. The clock transmitting part generates and transmits a clock intermittently phase-shifted. The data transmitting part transmits the data in sync with the clock transmitted from the clock transmitting part.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a National Stage of International Application No. PCT/JP2011/062717 filed Jun. 2, 2011, claiming priority based on Japanese Patent Application No. 2010-174404 filed Aug. 3, 2010, the contents of all of which are incorporated herein by reference in their entirety.

TECHNICAL FIELD

The present invention relates to a transmitting device, a receiving device and a transmitting/receiving system.

BACKGROUND ART

A clock generating technology according to spread spectrum (SS) is known as a technology of reducing EMI (electro magnetic interference) noise caused by a clock in a transmitting/receiving system that transmits clock and data from a transmitting device to a receiving device. According to the SS technology, by temporally modulating the frequency of the clock transmitted from the transmitting device to the receiving device, a bandwidth of a frequency spectrum of the clock is extended and the peak intensity of the frequency spectrum is reduced, thereby reducing the EMI noise.

The transmitting device employing such SS technology needs to include a spread spectrum clock generator (SSCG) that generates a clock, the frequency of which is temporally modulated. Patent literatures 1 to 11 disclose inventions related to the SS technology and the SSCG.

CITATION LIST

Patent Literature

SUMMARY OF INVENTION

Technical Problem

The transmitting device that employs the conventional SS technology and includes the conventional SSCG has a large circuit size, and the transmitting device formed of a semiconductor integrated circuit has a large semiconductor chip area.

The present invention is made to solve the above-mentioned problems and has an object to provide a transmitting device capable of reducing the EMI noise while suppressing an increase in the circuit size. Another object of the present invention is to provide a receiving device suited to receive a clock and data that are transmitted from such transmitting device and a transmitting/receiving system that includes such transmitting device and receiving device and can transmit/receive data with low noise.

Solution to Problem

A transmitting device according to the present invention includes a clock transmitting part that generates and transmits a clock intermittently phase-shifted, and a data transmitting part that transmits data in sync with the clock transmitted from the clock transmitting part.

The clock transmitting part may generate the phase-shifted clock by switching a clock selected from among multi-phase clocks and transmit the clock. The clock transmitting part may also phase-shift the clock at a transmission timing of a specified piece of data among pieces of data transmitted from the data transmitting part and transmit the clock.

In the transmitting device of the present invention, it is preferred that when the clock transmitted from the clock transmitting part is phase-shifted, the data transmitting part transmits a phase shift announcement command that announces the phase shift timing. It is preferred that immediately before the clock transmitted from the clock transmitting part is phase-shifted, the data transmitting part transmits the phase shift announcement command. Further, it is preferred that the data transmitting part transmits dummy data following the phase shift announcement command.

A receiving device of the present invention, which receives a clock and data transmitted from a transmitting device in sync with each other, includes (1) a clock receiving part that receives the clock, (2) a data receiving part that samples and receives data in sync with the clock received by the clock receiving part, and (3) a data processing part that, when the data received by the data receiving part is a phase shift announcement command that announces a timing when each of the clock received by the clock receiving part and the data received by the data receiving part is phase-shifted, invalidates data reception by the data receiving part at the timing announced by the phase shift announcement command.

A transmitting/receiving system of the present invention includes (1) the transmitting device and the receiving device of the present invention, wherein (2) the clock receiving part of the receiving device receives a clock transmitted from the clock transmitting part of the transmitting device, (3) the data receiving part of the receiving device receives data transmitted from the data transmitting part of the transmitting device, and (4) when the data that is transmitted from the data transmitting part of the transmitting device and received by the data receiving part of the receiving device is the phase shift announcement command, the data processing part of the receiving device invalidates data reception by the data receiving part at a timing announced by the phase shift announcement command.

Advantageous Effects of Invention

According to the present invention, EMI noise can be reduced while suppressing an increase in circuit size.

DESCRIPTION OF EMBODIMENTS

Embodiments for implementing the present invention will be described below in detail with reference to appended figures. In description of figures, the same or similar elements are given the same reference numerals and overlapping description thereof is omitted. First, a comparative example and then, the embodiments will be described.

Comparative Example

FIG. 1is a view showing a configuration of a transmitting device10in the comparative example. The transmitting device10in the comparative example includes a transmission data generating part11and an output buffer part12. The transmission data generating part11generates data1to be transmitted to a receiving device and a clock1, and outputs them to the output buffer part12. The output buffer part12includes a data transmitting part13and a clock transmitting part14.

The data transmitting part13is connected to the receiving device via a high-speed serial data line. The data transmitting part13includes a FIFO (first-in first-out) memory, receives and stores the data1output from the transmission data generating part11in the FIFO memory and outputs data stored in the FIFO memory and dummy data added as needed as data2to the receiving device. A timing when the FIFO memory of the data transmitting part13receives and stores the data1is instructed according to the clock1output from the transmission data generating part11. A timing when the FIFO memory of the data transmitting part13outputs the data2is instructed according to a clock2output from the clock transmitting part14.

The clock transmitting part14is connected to the receiving device via a clock line. The clock transmitting part14includes an SSCG, receives the clock1output from the transmission data generating part11, generates the clock2by temporally modulating (SS application) the frequency of the clock1and outputs the generated clock2. The clock2output from the clock transmitting part14is transmitted to the receiving device as well as being used as a signal instructing output of the data2from the FIFO memory of the data transmitting part13. Thereby, the data transmitting part13can transmit data2in sync with the clock2transmitted from the clock transmitting part14.

FIG. 2is a chart showing temporal change of the frequency of the clock2output from the transmitting device10in the comparative example. In an example of SS application shown in this figure, the clock1before SS application has a constant frequency f0, while the frequency of the clock2after SS application is modulated into the shape of a triangular wave. It is defined that the modulating frequency of the clock2is fmod (modulation cycle is 1/fmod), the central frequency of the clock2is f0and the modulation amplitude of the clock2is Δf.

FIG. 3is a chart showing the frequency spectrum of the clock2output from the transmitting device10in the comparative example. The frequency spectrum of the clock1before SS application concentrates on the frequency f0, while the frequency spectrum of the clock2after SS application as shown inFIG. 2has a band of width2(Δf+fmod) centering on the frequency f0and a reduced peak intensity. This can reduce the EMI noise.

FIG. 4is a chart showing temporal change of the phase of the clock2output from the transmitting device10in the comparative example. The phase of the clock2after SS application is equal to the integral of a frequency f(t) shown inFIG. 2. As apparent from this figure, even when amplitude Δf of frequency modulation is small, the phase as the integral of the frequency greatly changes from a phase ph0 in the case of no SS application.

An amplitude Δph of phase change of the clock2after SS application is expressed in a following formula (1). Using this formula, given that the central frequency f0is 1 GHz, the modulating frequency fmod is 30 kHz and a proportion of the modulation amplitude Δf with respect to the central frequency f0is 3%, the amplitude Δph of phase change becomes 250·2π (rad). That is, as compared to the case of no SS application, a change of the phase of the clock2after SS application is about ±250 cycles at maximum.

The clock transmitting part14of the transmitting device10in the comparative example includes an SSCG to generate and output the clock2after SS application as shown inFIG. 2. The SSCG basically includes a PLL (phase lock loop) circuit configuration, and generates and outputs the clock2, which is frequency-modulated by the PLL circuit. However, the SSCG including such PLL circuit has a large circuit size and is vulnerable to noise.

The data transmitting part13of the transmitting device10in the comparative example receives the data1in sync with the clock1before SS application, and outputs the data2in sync with the clock2after SS application. The output data2has the phase difference Δph with respect to the input data1. In order to prevent an error of data transmission/reception due to the phase difference, the transmitting device10needs to include a FIFO memory. The capacity of the FIFO memory needs to be larger as the amplitude Δph of phase change of clock2after SS application is larger. Accordingly, such FIFO memory also has a large circuit size.

The transmitting device10in the comparative example has a large circuit size as described above, and when the transmitting device10is formed of a semiconductor integrated circuit, an area of the semiconductor chip area is large. On the contrary, in below-mentioned transmitting devices10A to10D in this embodiment, a clock transmitting part generates and transmits a clock intermittently phase-shifted, thereby eliminating the necessity of the SSCG. As a result, EMI noise can be reduced while suppressing an increase in a circuit size.

First Embodiment

FIG. 5is a view showing a configuration of a transmitting device10A in First embodiment. The transmitting device10A in First embodiment includes the transmission data generating part11and an output buffer part12A. The transmission data generating part11generates the data1and the clock1, which are to be transmitted to the receiving device, and outputs them to the output buffer part12A. The output buffer part12A includes the data transmitting part13and a clock transmitting part14A.

The transmitting device10A in First embodiment shown inFIG. 5differs from the transmitting device10in the comparative example shown inFIG. 1in that the output buffer part12A is provided in place of the output buffer part12and the clock transmitting part14A is provided in place of the clock transmitting part14. The clock transmitting part14A includes a PLL15, a counter16and a clock inverting part17, and can generate the clock2intermittently phase-shifted on the basis of the input clock1and transmit the clock2. Given that the amount of phase shift is π (180 degrees), the clock2intermittently phase-shifted is equal to the clock2, voltage amplitude of which is intermittently inverted.

PLL15receives the clock1output from the transmission data generating part11, generates a clock3having a frequency obtained by multiplying the frequency of the input clock1by a certain value and outputs the clock3. The counter16receives the clock3output from the PLL15, counts a pulse of the clock3and outputs a clock inversion control signal having a significant value for a certain period for every certain number of pulses.

The clock inverting part17receives the clock3output from the PLL15as well as the clock inversion control signal output from the counter16, switches between the positive phase and the negative phase of the clock3each time the clock inversion control signal has a significant value and outputs the clock as the clock2. The data transmitting part13transmits the data2in sync with the clock2output from the clock inverting part17of the clock transmitting part14A.

FIG. 6is timing charts of the clock1, the clock2, the clock3and so on in the transmitting device10A in First embodiment. This figure shows, from the top, the clock1input to the PLL15, the clock3output from the PLL15, a signal inverted from the clock3, the clock inversion control signal output from the counter16and the clock2output from the clock inverting part17.

In the figure, the frequency of the clock3output from the PLL15is 21/20 times as high as the frequency of the clock1input to the PLL15. That is, a period of 21 pulses of the clock3is equal to a period of 20 pulses of the clock1. A timing of an edge of a pulse #21of the clock3is the same as that of an edge of a pulse #20of the clock1. The clock inversion control signal output from the counter16is put into High level for a certain period for every 10 pulses of the clock3. Each time the clock inversion control signal is put into High level (that is, every 10 pulses of the clock3), the clock2output from the clock inverting part17has the positive phase and the negative phase switched from those of the clock3and thus, the phase is shifted by7E.

In such operation, in the clock2output from the clock inverting part17, an edge corresponding to an edge of a pulse #11of the clock3output from the PLL15is lost. Accordingly, during a period of 20 pulses of the clock1, 21 pulses of the clock3are generated and 20 pulses of the clock2are generated.

FIGS. 7A and 7Bare timing charts of data and clock, which are output from the transmitting device10A in First embodiment. InFIG. 7A, the clock has no phase shift. InFIG. 7B, the clock is intermittently phase-shifted by π. In both cases, the receiving device that receives the data and clock, which are output from the transmitting device10A, may sample data at an edge of the clock pulse.

FIG. 8is a view showing an example of a frequency spectrum of a clock output from the transmitting device10A in First embodiment. The frequency spectrum of the clock1concentrates on the frequency f0, while the frequency spectrum of the clock2output from the transmitting device10A in First embodiment has no frequency f0component and has peaks at f0±fmod/2, f0±fmod, f0±3fmod/2, . . . , and reduced peak intensity. This can reduce EMI noise. fmod is a frequency at the timing when the clock is phase-shifted.

In the above description, the clock output from the transmitting device10A is phase-shifted for every certain pulses (that is, at the certain frequency fmod). However, the clock2output from the transmitting device10A may be phase-shifted for every N1 pulses and for every N2 pulses. In this case, a frequency division ratio of the PLL15is (N1+N2+1)/(N1+N2), and the counter16may output the clock inversion control signal that has a significant value for a certain period each time the number of pulses N1, N2 of the clock3is counted.

FIG. 9is a view showing another example of the frequency spectrum of the clock output from the transmitting device10A in First embodiment. By changing the fmod and the amount of phase shift, the peak intensity of the spectrum can be further reduced, thereby further reducing EMI noise.

Referring toFIG. 10AtoFIG. 12C, simulation calculation results of the frequency spectrum of the clock will be described.FIGS. 10A and 10Bare views showing waveform and frequency spectrum of the clock without SS application, in whichFIG. 10Ashows the clock waveform, andFIG. 10Bshows the frequency spectrum.FIGS. 11A and 11Bare views showing waveform and frequency spectrum when the clock is phase-shifted by π for every 10 pulses, in whichFIG. 11Ashows the clock waveform, andFIG. 11Bshows the frequency spectrum.FIGS. 12A to 12Care views showing waveform and frequency spectrum when the clock is phase-shifted by π for every 9 pulses and for every 7 pulses in First embodiment, in whichFIG. 12Ashows the waveform of the clock phase-shifted for every 9 pulses,FIG. 12Bshows the waveform of the clock phase-shifted for every 7 pulses, andFIG. 12Cshows the frequency spectrum. As apparent from comparison of these figures, the spectrum peak intensity is reduced when the clock is phase-shifted by π for every 10 pulses (FIGS. 11A and 11B) than when the SS is not applied (FIGS. 10A and 10B), and the spectrum peak intensity is further reduced when the clock is phase-shifted for every 9 pulses and for every 7 pulses (FIGS. 12A to 12C).

Although the transmitting device10in the comparative example requires the SSCG having a large circuit size and the FIFO memory, the transmitting device10A in First embodiment only needs to include the PLL having a fixed frequency division ratio and a FIFO memory having a low capacity value and therefore, EMI noise can be reduced while suppressing an increase in a circuit size, and when the transmitting device is formed of the semiconductor integrated circuit, the area of the semiconductor chip is small.

Second Embodiment

FIG. 13is a view showing a configuration of a transmitting device10B in Second embodiment. The transmitting device10B in Second embodiment includes the transmission data generating part11and an output buffer part12B. The transmission data generating part11generates the data1and the clock1, which are to be transmitted to the receiving device, and outputs them to the output buffer part12B. The output buffer part12B includes the data transmitting part13and a clock transmitting part14B.

The configuration of the transmitting device10B in Second embodiment shown inFIG. 13differs from that of the transmitting device10A in First embodiment shown inFIG. 5in that the output buffer part12B is provided in place of the output buffer part12A and the clock transmitting part14B is provided in place of the clock transmitting part14A. The clock transmitting part14B includes the PLL15, the counter16and a clock selecting part18, and can generate the clock2intermittently phase-shifted on the basis of the input clock1and transmit the clock2.

The PLL15receives the clock1output from the transmission data generating part11, generates a multi-phase clock3having a frequency obtained by multiplying the frequency of the input clock1by a certain value and outputs the multi-phase clock3. The counter16receives any clock of the multi-phase clock3output from the PLL15, counts the input clock pulse and outputs a clock selection control signal for every certain numbers of clocks.

The clock selecting part18receives the multi-phase clock3output from the PLL15as well as the clock selection control signal output from the counter16, selects one clock indicated by the clock selection control signal of the multi-phase clock3and outputs the selected clock as the clock2. The data transmitting part13transmits the data2in sync with the clock2output from the clock selecting part18of the clock transmitting part14B.

In comparison with First embodiment, in Second embodiment, since the phase-shifted clock can be generated by switching a clock selected from among the multi-phase clocks and transmitted, the clock2having a more complicated spectrum can be output. Thus, the spectrum peak intensity can be further reduced, achieving further reduction of EMI noise.

Third Embodiment

In each of First embodiment and Second embodiment described above, the receiving device can receive data transmitted to the receiving device without any loss. In actual some applications, however, data loss may be allowed. For example, data in a blanking period in a video signal may be lost. The blanking period occurs at a certain cycle. In such case, the clock transmitting part does not need to include the PLL. The transmitting device10C in Third embodiment intermittently phase-shifts the clock according to a blanking indicating signal indicating the blanking period.

FIG. 14is a view showing a configuration of a transmitting device10C in Third embodiment. The transmitting device10C in Third embodiment includes the transmission data generating part11and an output buffer part12C. The transmission data generating part11generates the data1and the clock1, which are to be transmitted to the receiving device, and outputs them to the output buffer part12C. The output buffer part12C includes the data transmitting part13and a clock transmitting part14C.

The configuration of the transmitting device10C in Third embodiment shown inFIG. 14differs from that of the transmitting device10A in First embodiment shown inFIG. 5in that the output buffer part12C is provided in place of the output buffer part12A and the clock transmitting part14C is provided in place of the clock transmitting part14A. The clock transmitting part14C includes the counter16and the clock inverting part17, and can generate the clock2intermittently phase-shifted on the basis of the input clock1and transmits the clock2.

The counter16receives the blanking indicating signal indicating the blanking period in a video signal data1, counts an event that the blanking indicating signal has a significant value, and outputs the clock inversion control signal that has the significant value for a certain period for every certain numbers of counts.

The clock inverting part17receives the clock1output from the transmission data generating part11as well as the clock inversion control signal output from the counter16, switches between the positive phase and the negative phase of the clock1each time the clock inversion control signal has the significant value and outputs the clock as the clock2. The data transmitting part13transmits the data2in sync with the clock2output from the clock inverting part17of the clock transmitting part14C.

FIG. 15is timing charts of a clock1, a clock2and so on in the transmitting device10C in Third embodiment. This figure shows, from the top, the clock1input to the clock inverting part17, a signal inverted from the clock1, the blanking indicating signal and the clock2output from the clock inverting part17.

As shown in this figure, in Third embodiment, the clock inverting part17switches between the positive phase and the negative phase of the clock1according to the blanking indicating signal indicating the blanking period and outputs the clock as the clock2. Since a pulse #10is lost in the output clock2, data in sync with a pulse edge is also lost. However, since this loss timing is in the blanking period, no effect is made on video data.

Phase shift may be made each time the blanking indicating signal appears, and in this case, the counter16is unnecessary. However, when phase shift is made once out of several times when the blanking indicating signal appears, the counter16may be provided as shown in the figure. Another specific signal indicating a timing when data loss is allowed may be used in place of the blanking indicating signal.

Fourth Embodiment

In the above description of each embodiment, a delay time difference between data and clock from the transmitting device to the receiving device is not considered. However, actually, it is not limited to a situation in which a data signal line and a clock signal line from the transmitting device10to the receiving device30are equal to each other in length as shown inFIG. 16A, and the clock signal line may be longer than the data signal line as shown inFIG. 16B. As shown inFIG. 16C, a buffer may be inserted in the middle of the clock signal line. Alternatively, when a common clock is transmitted from one transmitting device to a plurality of receiving devices, different number of buffers may be inserted in the middle of the clock signal lines from the transmitting device to the receiving devices. In these cases, the delay time difference between data and clock from the transmitting device to the receiving device occurs.

When the delay time difference exists between data and clock from the transmitting device to the receiving device, if SS application is not performed, the receiving device can receive data output from the transmitting device without any error by compensating the delay time difference. The compensation of the delay time difference may be performed on the side of the transmitting device, on the side of the receiving device or in another device inserted for compensation.

FIGS. 17A to 17Care views illustrating the delay time difference without SS application. A clock shown inFIG. 17Ahas a constant cycle. A clock2shown inFIG. 17Bhas a small delay time difference relative to the clock shown inFIG. 17A. A clock2shown inFIG. 17Chas a delay time difference of one cycle relative to the clock2shown inFIG. 17B. In each case, since the delay time difference is temporally constant, once the delay time difference is compensated, the effect is maintained thereafter.

FIGS. 18A to 18Dare views illustrating the delay time difference with SS application in the comparative example. The cycle of a clock shown inFIG. 18Ais gradually increased. A clock2shown inFIG. 18Bhas a small delay time difference relative to the clock shown inFIG. 18A. A clock2shown inFIG. 18Chas a delay time difference of one cycle relative to the clock2shown inFIG. 18B. A clock2shown inFIG. 18Dhas a delay time difference of one cycle relative to the clock2shown inFIG. 18C.

When the delay time difference is equal to or smaller than one cycle as shown inFIG. 18B, since the delay time difference is temporally constant, once the delay time difference is compensated, the effect is maintained thereafter. However, when the delay time difference is equal to or larger than one cycle as shown inFIG. 18C, since the delay time difference varies with time, even if the delay time difference is compensated at a certain time point, the effect is not maintained and the delay time difference must be compensated at all times. When the delay time difference is further increased as shown inFIG. 18D, the delay time difference greatly changes and adjustment becomes more difficult.

A below-mentioned transmitting/receiving system including a transmitting device and a receiving device in Fourth embodiment is suitable for the case where the delay time difference exists between data and clock from the transmitting device to the receiving device.FIG. 19is a view showing a configuration of the transmitting device10D in Fourth embodiment.FIG. 20is a timing chart of each piece of data in the transmitting device10D in Fourth embodiment. The transmitting device10D in Fourth embodiment includes a transmission data generating part21, an announcement command generating part22and a parallel-serial converting part23.

The transmission data generating part21generates the data1and the clock1, which are to be transmitted to the receiving device, and outputs them to the announcement command generating part22. The transmission data generating part21intermittently inserts dummy data (dummy data) in the middle of pieces of data (Normal Data) to be transmitted to the receiving device. The dummy data is inserted at a timing when the clock is phase-shifted, and occupies at least two decode minimum units of transmission data.

The announcement command generating part22receives the data1output from the transmission data generating part21, detects the dummy data in the data1and replaces a first unit of the dummy data with the phase shift announcement command. The second and subsequent units of the dummy data may be transmitted to the receiving device as they are unless the transmission generates a problem. However, if a trouble occurs on the side of the receiving device when the second and subsequent units of the dummy data may be transmitted to the receiving device as they are, the announcement command generating part22replaces the dummy data with another dummy data (dummy data2) that does not generate a trouble.

The announcement command generating part22outputs the data2after replacement to the parallel-serial converting part23. The announcement command generating part22outputs a phase shift start signal that instructs to phase-shift the clock at a timing of the dummy data (the dummy data or the dummy data2) in the data2to the parallel-serial converting part23.

The parallel-serial converting part23receives the data2and the phase shift start signal, which are output from the announcement command generating part22. Then, like the output buffers14A to14C in First to Third embodiments, the parallel-serial converting part23transmits a clock (serial clock0) phase-shifted at the timing indicated by the phase shift start signal, and transmits serial data (serial data0) converted from the data2in sync with the clock. The serial data (serial data0) contains the phase shift announcement command that announces the timing when the clock (serial clock0) is phase-shifted, and also contains the dummy data (the dummy data or the dummy data2) following the phase shift announcement command.

FIG. 21is a view showing a configuration of the receiving device30in Fourth embodiment.FIG. 22is a timing chart of each piece of data in the receiving device30in Fourth embodiment. The receiving device30in Fourth embodiment includes a serial-parallel converting part31and a data processing part32. The data processing part32includes an announcement command detecting part33, a data switching part34and a decoding part35.

The serial-parallel converting part31receives the serial data (serial data0) and the clock (serial clock0) that are transmitted from the transmitting device10D in sync with each other. The serial-parallel converting part31includes a clock receiving part that receives the clock (serial clock0) and the data receiving part that samples and receives the serial data (serial data0) in sync with this clock. The serial-parallel converting part31also outputs the parallel data1converted from the serial data (serial data0) to the announcement command detecting part33.

The announcement command detecting part33receives the data1output from the serial-parallel converting part31and detects the phase shift announcement command in the data1. Then, when detecting the phase shift announcement command, the announcement command detecting part33outputs an announcement command detecting signal that indicates the detection to the data switching part34. The announcement command detecting part33also outputs the input data1as data2to the data switching part34.

The data switching part34receives the data2and the announcement command detecting signal, which are output from the announcement command detecting part33. Then, the data switching part34recognizes that data following the phase shift announcement command in the data2is the dummy data, that is, invalid data (Invalid data) on the basis of the announcement command detecting signal. Then, the data switching part34outputs a Valid signal as Low level to the decoding part35for an originally unnecessary period of the phase shift announcement command and the invalid data (Invalid data). The Valid signal given from the data switching part34to the decoding part35is put into High level when data3given from the data switching part34to the decoding part35is original data (Normal Data), and is put into Low level when the data3is invalid data. When the phase shift announcement command and the invalid data (Invalid data) cause a trouble in a subsequent stage, the data switching part34replaces the data with a value that generates no trouble (for example, zero) and outputs the data3after replacement to the decoding part35.

The decoding part35receives the data3and the Valid signal output from the data switching part34, performs required processing on the basis of them and outputs data4to a subsequent stage. In this manner, when the received data is the phase shift announcement command, the data processing part32including the announcement command detecting part33, the data switching part34and the decoding part35can invalidate data reception at the timing announced by the phase shift announcement command.

FIG. 23is a timing chart of data and clock in a transmitting/receiving system including the transmitting device10D and the receiving device30in Fourth embodiment. At the time when the transmitting device10D transmits the data1and the clock1, the data1is synchronized with the clock1, and when the clock1is phase-shifted, the data1is also phase-shifted by the same shift amount.

At the time when the receiving device30receives the data1and the clock2, a delay time difference is generated between the data1and the clock2, and in this figure, the delay time difference corresponds to two cycles of the clock. In this case, in the receiving device30, even when the data1is sampled at an edge of a pulse #3immediately before phase shift, the sampling is incorrect.

In Fourth embodiment, the phase shift announcement command that announces the phase shift timing when the clock is phase-shifted is transmitted from the transmitting device10D to the receiving device30. Then, in the receiving device30, when the received data is the phase shift announcement command, data reception at the timing announced by the phase shift announcement command is made invalid. At this time, by setting the data to be made invalid to the dummy data, data transmission can be performed from the transmitting device10D to the receiving device30without any problem.

A specific operational example of a transmitting/receiving system1including the transmitting device10D and the receiving device30in Fourth embodiment will be described with reference toFIG. 24andFIGS. 25A to 25G.FIG. 24is a view showing a configuration example of the transmitting/receiving system1in Fourth embodiment. The transmitting/receiving system1shown in this figure includes a transmitting device10D and receiving devices301to306.

Although the transmitting device10D is substantially similar to the above-mentioned transmitting device10D, the former transmitting device10D transmits a common clock to the six receiving devices301to306, transmits data1to the receiving device301, transmits data2to the receiving device302, transmits data3to the receiving device303, transmits data4to the receiving device304, transmits data5to the receiving device305and transmits data6to the receiving device306.

Although each of the receiving devices301to306is substantially similar to the receiving device30, the receiving devices301to306buffer the input clock and transmits the clock to the receiving device in the next stage. That is, the receiving device301receives the data1and the clock, which are output from the transmitting device10D, buffers the input clock and transmits the clock to the receiving device302in the next stage. The receiving device302receives the data2output from the transmitting device10D and the clock output from the receiving device301in the previous stage, buffers the input clock and transmits the clock to the receiving device303in the next stage.

The receiving device303receives the data3output from the transmitting device10D and the clock output from the receiving device302in the previous stage, buffers the input clock and transmits the clock to the receiving device304in the next stage. The receiving device304receives the data4output from the transmitting device10D and the clock output from the receiving device303in the previous stage, buffers the input clock and transmits the clock to the receiving device305in the next stage.

The receiving device305receives the data5output from the transmitting device10D and the clock output from the receiving device304in the previous stage, buffers the input clock and transmits the clock to the receiving device306in the next stage. The receiving device306receives the data6output from the transmitting device10D and the clock output from the receiving device305in the previous stage.

In the transmitting/receiving system1thus configured, the delay time differences between the data and the clock, which are input to each of the receiving devices301to306are different from one another. That is, the receiving device in the latter stage has a larger delay time difference. Even when no delay time difference exists between the data1and the clock, which are input to the receiving device301in the first stage, a delay time difference exists between the data2and the clock, which are input to the receiving device302in the second stage, and a larger delay time difference exists between the data3and the clock, which are input to the receiving device303in the third stage.

FIGS. 25A to 25Gare time charts of the data and the clock in the transmitting/receiving system1in Fourth embodiment. Here, it is assumed that the transmitting device10D transmits 5 bits of dummy data f to j following 5 bits of phase shift announcement commands a to e. Further, it is assumed that phase shift occurs in the phase shift announcement command e. Each of the receiving devices301to306samples data at timings both at rising and falling of the clock.

FIG. 25Ashows timing in a case of no phase shift and no delay time difference between the data and the clock.FIGS. 25B to 25Gshow timings of the data and the clock, which are input to each receiving device30n, and the data sampled by each receiving device30n, when phase shift is performed.

In an example shown inFIG. 25B, there is no delay time difference between the data1and the clock, which are input to the receiving device301in the first stage. The clock and the data1are phase-shifted at the same timing and a period of the phase shift announcement command e is long. Accordingly, in the receiving device301, since the first received data is the phase shift announcement commands a to e, the following data f to j can be recognized as the dummy data.

In an example shown inFIG. 25C, a delay time difference of a half cycle of the clock (1 bit of data) exists between the data2and the clock, which are input to the receiving device302in the second stage. Also in this case, in the receiving device302, since the first received data is the phase shift announcement commands a to e, the following data f to j can be recognized as the dummy data

In an example shown inFIG. 25D, a delay time difference of one cycle of the clock (2 bits of data) exists between the data3and the clock, which are input to the receiving device303in the third stage. In an example shown inFIG. 25E, a delay time difference of one and a half cycles of the clock (3 bits of data) exists between the data4and the clock, which are input to the receiving device304in the fourth stage. In an example shown inFIG. 25F, a delay time difference of two cycles of the clock (4 bits of data) exists between the data5and the clock, which are input to the receiving device306in the fifth stage. In an example shown inFIG. 25G, a delay time difference of two and a half cycles of the clock (5 bits of data) exists between the data6and the clock, which are input to the receiving device306in the fifth stage.

In examples shown inFIGS. 25D to 25G, although each of the receiving devices303to306receives the phase shift announcement commands a to e, the subsequently received data is not necessarily the dummy data f to j and any dummy data is lost. The dummy data f is lost in the receiving device303, the dummy data g is lost in the receiving device304, the dummy data h is lost in the receiving device305and the dummy data i is lost in the receiving device306.

However, the data e is received immediately after reception of the phase shift announcement commands a to e, and 5 bits of dummy data including the data e is received. Accordingly, in any ofFIGS. 25B to 25G, the 5 bits of data received after reception of the 5 bits of phase shift announcement commands a to e may be recognized as the dummy data.

Although one piece of dummy data after the phase shift announcement command is shown in the above-mentioned example, by providing plural pieces of dummy data, a larger delay time difference between clock and data can be addressed.

The configuration shown inFIG. 24orFIGS. 25A to 25Gmay be used in data transmission between a timing controller and a driver in image display devices such as liquid crystal displays (LCD) and plasma display panels (PDP), and data transmission in a memory system. By adopting such configuration, the number of communication cables in the above-mentioned image display devices and clock lines in the memory system can be reduced, contributing to reduction of costs and EMI.

INDUSTRIAL APPLICABILITY

EMI noise can be reduced while suppressing an increase in a circuit size.

REFERENCE SIGNS LIST