Electrostatic discharge protection device and method of fabricating the same

An electrostatic discharge protection device, and a method of fabricating the same, includes a substrate, an n-well formed in the substrate, a p-well formed on the n-well, an NMOS transistor formed on the p-well, the NMOS transistor including a gate electrode, an n+ source and an n+ drain, and a grounded p+ well pick-up formed in the p-well, wherein the n-well is connected to the n+ drain of the NMOS transistor and the n+ source is grounded. The n+ drain and the n-well are connected to decrease a voltage of a trigger and a current density of a surface of the substrate.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and a method of fabricating the same. More specifically, the present invention relates to an electrostatic discharge protection device and a method of fabricating the same.

2. Description of the Related Art

An integrated circuit (IC) including a MOS field effect transistor (MOSFET) may be easily damaged by an electrostatic discharge (ESD). An ESD may be delivered to an IC from an input/output (I/O) pin, a power pin, or a pad of another IC, and may attack a junction of a transistor, a dielectric and a unit device.

Various structures of an ESD protection circuit have been developed to protect devices from an ESD. An important role of an ESD protection circuit is to guide the ESD current from an easily attackable circuit to a low-impedance path.

Such an ESD protection circuit may be connected between an I/O and power pins and an internal circuit in parallel, and functions to guide the ESD current to an external region by providing a current path at a low power during an ESD. A representative discharge protection circuit may be categorized into a silicon controlled rectifier (SCR) and an npn bipolar transistor. An SCR instantly discharges an ESD current to a node Vss using a parasitic npnp diode. An npn bipolar transistor discharges an ESD current to a node Vss by an operation of a parasitic npn bipolar transistor of a MOS transistor based on a snap-back phenomenon. Such an ESD protection circuit may use a gate grounded NMOS transistor (ggNMOS) for a structure of the npn bipolar transistor.

FIG. 1is a circuit diagram of a conventional ESD protection circuit using a ggNMOS transistor.FIG. 2is a graph illustrating a voltage-current (V-I) characteristic of the ggNMOS transistor ofFIG. 1when an electrostatic current is discharged.

Referring toFIG. 1, an ESD protection circuit5is connected in parallel between a pad1and an internal circuit3. A drain of the ggNMOS transistor is electrically connected to a pad1. A gate, a source and a channel of the transistor are connected to a ground node Vss.

Referring toFIG. 2, when a voltage higher than a trigger voltage Vt is applied to the ggNMOS transistor by an ESD, a break down of the drain junction in the ggNMOS transistor causes a portion of charges to flow in a substrate. The charges make the parasitic npn transistor turned-on to discharge a large amount of ESD current through a low-impedance path to the Vss node instantly. Therefore, the internal circuit3is protected from damage.

Three issues may degrade the robustness of an ESD protection device. These issues are an increase of a surface current density during an ESD, a hot-carrier issue and Joule heating. In an effort to solve this problem, a silicide blocking layer may be formed between the gate and the source/drain contact of the ggNMOS. However, such a structure requires that the silicide be separated at an area where the source/drain contact is connected to a gate. Further, such a structure has a disadvantage of increasing an area of the ESD circuit.

FIG. 3illustrates another conventional semiconductor device for an ESD protection device having an n+ drain surrounded by an n-diffusion layer without increasing a layout area.

Referring toFIG. 3, the ESD protection device is formed at a p-well12of a substrate10and includes NMOS transistors T1and T2connected in series sharing an n+ drain20. Each NMOS transistor T1and T2includes a gate electrode14. Sources16of each of the NMOS transistors T1and T2and a p+ guard ring18are connected to a node Vss. The n+ drain20is electrically connected to a pad24. The device includes an n-diffusion layer22surrounding the n+ drain20to overcome an increase of surface current density and a hot carrier issue. The n− diffusion layer22includes a space under the n+ drain20.

The space under the n+ drain20has a relatively low breakdown voltage. Therefore, the substrate current is generated through the space when an ESD voltage is applied to the n+ drain20and discharged through parasitic npn bipolar transistors Q1and Q2in the NMOS transistor to the node Vss. This structure may improve ESD robustness because a current path is separated from a substrate surface and a transistor channel that are relatively weak. However, such a structure is formed through a complicated process because it requires an additional layer for forming the n-diffusion layer22having the space under the n+ drain20.

SUMMARY OF THE INVENTION

The present invention is therefore directed to an electrostatic discharge protection device and a method of fabricating the same, which substantially overcome one or more of the problems due to the limitations and disadvantages of the related art.

It is a feature of an embodiment of the present invention to provide an ESD protection device, and a method of forming the same, having good ESD robustness.

It is another feature of an embodiment of the present invention to provide an ESD protection device, and a method of forming the same, that has increased robustness without increasing an area of the ESD circuit.

It is still another feature of an embodiment of the present invention to provide an ESD protection device, and a method of forming the same, that is capable of being fabricated without requiring additional complicated processes.

At least one of the above and other features and advantages of the present invention may be realized by providing an electrostatic discharge protection device including a substrate, an n-well formed in the substrate, a p-well formed on the n-well, an NMOS transistor formed on the p-well, the NMOS transistor including a gate electrode, an n+ source and an n+ drain, and a grounded p+ well pick-up formed in the p-well, wherein the n-well is connected to the n+ drain of the NMOS transistor and the n+ source is grounded.

The gate electrode may be grounded. The gate electrode may be electrically connected to the n+ drain.

An impurity concentration of the n+ drain may be higher than that of the n+ source. The n-well may extend vertically under the n+ drain and may contact the n+ drain. The n-well may extend vertically to form a junction with the p-well and a junction of the n-well and the p-well may overlap the n+ drain.

At least one of the above and other features and advantages of the present invention may be realized by providing an electrostatic discharge protection device including a p-well region formed in a substrate, an NMOS transistor formed on the p-well region, the NMOS transistor including a gate electrode and an n+ source that are electrically connected to a ground terminal and an n+ drain electrically connected to a circuit terminal, a p+ well pick-up formed in the p-well region, electrically connected to the ground terminal, and an n-well formed under the p-well region, wherein the n-well extends vertically to contact the n+ drain of the NMOS transistor.

The electrostatic discharge protection device may further include an interconnection connected to the ground terminal, wherein the n+ source, the gate electrode and the p+ well pick-up may be connected to the interconnection in parallel.

At least one of the above and other features and advantages of the present invention may be realized by providing an electrostatic discharge protection device connected to a circuit terminal and a ground terminal including a p-well region formed in a substrate, an NMOS transistor formed on the p-well region, the NMOS transistor including a gate electrode electrically connected to the circuit terminal, an n+ source electrically connected to the ground terminal and an n+ drain electrically connected to the circuit terminal, a p+ well pick-up formed in the p-well region to be electrically connected to the ground terminal, and an n-well formed under the p-well region, wherein the n-well extends vertically to contact the n+ drain of the NMOS transistor.

The electrostatic discharge protection device may further include a first interconnection connected to the ground terminal, wherein the n+ source and the p+ well pick-up are connected to the first interconnection in parallel. The electrostatic discharge protection device may further include a second interconnection for connecting the circuit terminal and the n+ drain, wherein the gate electrode is an extended portion of the second interconnection.

At least one of the above and other features and advantages of the present invention may be realized by providing a method of fabricating the electrostatic discharge protection device including forming a p-well region at an upper portion of a substrate and an n-well region under the p-well region, wherein the n-well region extends vertically along a sidewall of the p-well region to define a junction between the p-well region and the n-well region at a surface of the substrate, forming an n+ source and an n+ drain separated from each other by implanting impurities in the p-well region, wherein the n+ drain is formed to overlap the junction of the p-well region and the n-well region, forming a p+ well pick-up by implanting impurities in the p-well region, and forming an interconnection connected to each of the p+ well pick-up, the n+ source and the n+ drain, wherein the p+ well pick-up and the n+ source are connected to a ground terminal, and the n+ drain is connected to a circuit terminal.

The method may further include forming a device isolation layer in the substrate to define an active region, before forming the n-well region and the p-well region, wherein the active region includes the n-well region and the p-well region, and the n+ source, the p+ well pick-up and the n+ drain are formed in the active region.

The method may further include forming a device isolation layer in the substrate to define an active region, after forming the n-well region and the p-well region, wherein the active region includes the n-well region and the p-well region, and the n+ source, the p+ well pick up and the n+ drain are formed in the active region.

An interconnection connected to the n+ drain may extend over a region between the n+ source and the n+ drain, such that an edge of the interconnection overlaps the n+ source.

At least one of the above and other features and advantages of the present invention may be realized by providing a method of fabricating an electrostatic discharge protection device connected to a circuit terminal and a ground terminal including forming a p-well region at an upper portion of a substrate and an n-well region under the p-well region, wherein the n-well region extends vertically along a sidewall of the p-well region to define a junction of the p-well region and the n-well region at a surface of the substrate, forming a gate electrode on the p-well region, implanting impurities in the substrate at either side of the gate electrode to form an n+ source and an n+ drain, wherein the n+ drain is formed to overlap a junction between the p-well region and the n-well region, implanting impurities in the p-well region to form a p+ well pick-up, and forming an interconnection connecting each of the p+ well pick-up, the gate electrode, the n+ source and the n+ drain, wherein the p+ well pick-up and the n+ source are connected to the ground terminal, and the n+ drain is connected to the circuit terminal.

The method may further include forming a device isolation layer in the substrate to define an active region, before forming the n-well region and the p-well region, wherein the active region includes the n-well region and the p-well region, the gate electrode crosses over the p-well region in the active region, and wherein the active region at one side of the gate electrode includes the p-well region and the active region at the other side of the gate electrode includes the p-well region and the n-well region.

The method may further include forming a device isolation layer in the substrate to define an active region, after forming the n-well region and the p-well region, wherein the active region includes the n-well region and the p-well region, and wherein the gate electrode crosses over the p-well region in the active region, and the active region at one side of the gate electrode is the p-well region and the active region at the other side includes the p-well region and the n-well region.

DETAILED DESCRIPTION OF THE INVENTION

Korean Patent Application 2003-91308, filed on Dec. 15, 2003, in the Korean Intellectual Property Office, and entitled: “Electrostatic Discharge Protection Device and Method of Fabricating the Same,” is incorporated by reference herein in its entirety.

FIG. 4Aillustrates a cross-sectional view of an ESD protection device according to the first embodiment of the present invention.

Referring toFIG. 4A, the ESD protection device includes an n-well52formed in a substrate50and a p-well54formed on the n-well52. The p-well54extends to a surface of the substrate50. The n-well52includes a portion that extends vertically along a sidewall of the p-well54to a surface of the substrate50. A device isolation layer56is formed in the substrate50to define an active region. The active region includes a region where the p-well54is formed (hereinafter, referred to as a ‘p-well region’) and a region where the n-well52is formed (hereinafter, referred to as an ‘n-well region’). A gate electrode58is formed on the active region. The gate electrode58crosses over the active region and, although not illustrated as doing so, may extend over the device isolation layer56. The gate electrode58divides the active region into a first portion of the active at one side of the gate electrode58that includes the p-well region and the n-well region and a second portion of the active region to the other side of the gate electrode58that includes the p-well region. An n+ source64and an n+ drain62are formed in the active regions to either side of the gate electrode58. The gate electrode58, the n+ source64and the n+ drain62compose an NMOS transistor. The n+ source64is formed in the p-well54, and the n+ drain62is formed to overlap the p-well54and the n-well52.

Conventionally, a source and a drain of the NMOS transistor are formed in the p-well or a p-substrate, but the n+ drain62of the NMOS transistor in the ESD protection device according to the present invention overlaps the p-well54and the n-well52and contacts the n-well52. An impurity concentration of the n+ drain62may be higher than that of the n+ source64due to an influence of the n-well52.

A p+ well pick-up66doped with impurities is formed in the p-well region54. The p+ well pick-up66may be separated from the NMOS transistor by the device isolation layer56. The n+ drain62is connected to a circuit terminal60of the integrated circuit. The n+ source64and the p+ well pick-up66are connected to a ground terminal. The circuit terminal60may be an input/output (I/O) pin, a data pin or a power pin, and may be electrically connected to an internal circuit. The gate electrode58functions to separate the n+ source64from the n+ drain62to form a base of a parasitic npn bipolar transistor. However, the gate electrode58may be connected to a ground terminal to prevent the NMOS transistor from operating abnormally due to a voltage drop of the p-well54as a result of an ESD protection current.

The NMOS transistor may adopt a gate electrode in a finger structure to discharge a large amount of current even though a representative singular gate electrode is illustrated inFIG. 4A. In this case, the n-well52vertically extends to connect to the n+ drain62. In addition, the p+ well pick-up66may be formed in the p-well54as a guard ring type that surrounds the ESD protection circuit.

FIG. 4Bis an equivalent circuit diagram of an ESD protection device according to the first embodiment of the present invention.

The ESD protection device operates using a parallel circuit of a parasitic npn bipolar transistor in the NMOS transistor. The n+ source64, the n+ drain62and the p-well54correspond to an emitter, a collector and a base, respectively, of the first npn bipolar transistor Q11. The n+ source64, the n-well52and the p-well54correspond to an emitter, a collector and a base, respectively, of the second npn bipolar transistor Q12.

When an ESD voltage is applied to the n+ drain62to break down a junction among the n+ drain62, the n-well52and the p-well54, the first and second npn bipolar transistors Q11and Q12are triggered. A voltage drop by the parasitic resistors R1and R2of the p-well54drives the first and second npn bipolar transistors Q11and Q12to instantly discharge the ESD current through a ground terminal. The ESD protection device discharges the ESD current by operation of a lateral npn bipolar transistor Q11and a vertical npn bipolar transistor Q12. The lateral npn bipolar transistor Q11includes the n+ source64, the n+ drain62and the p-well54. The vertical npn bipolar transistor Q12includes the n+ source64, the n-well52and the p-well54. Therefore, a discharge current is dispersed to lower a surface current of the substrate and suppress Joule heat generated from a surface of the substrate.

The impurities of the n-well52may raise an impurity concentration of the n+ drain62. Therefore, a junction breakdown voltage between the n+ drain62and the p-well54can be reduced to provide a low trigger voltage for the bipolar transistor. In this case, an impurity concentration of the n+ drain62is highest at a portion where the p-well54, the n-well52and the n+ drain62contact one another. Therefore, this portion breaks down first to lower a current density of the surface at the region adjacent a gate.

FIG. 5Aillustrates a cross-sectional view of an ESD protection device according to the second embodiment of the present invention.

Referring toFIG. 5A, the ESD protection device similarly includes an NMOS transistor having the n+ drain62connected to the n-well52. The n-well52and the p-well54are formed in the substrate50. The p-well54extends to a surface of the substrate50. A portion of the n-well52vertically extends along a sidewall of the p-well54to a surface of the substrate50. The device isolation layer56is formed in the substrate50to define an active region. The active region includes the p-well region and the n-well region. The gate electrode58is formed on the active region. The gate electrode58crosses over the active region and, although not illustrated as doing so, may extend to a surface of the device isolation layer56. The gate electrode58divides the active region into a first portion of the active at one side of the gate electrode58that includes the p-well region and the n-well region and a second portion of the active region to the other side of the gate electrode58that includes only the p-well region. The n+ source64and the n+ drain62are formed in the active regions to either side of the gate electrode58. The gate electrode58, the n+ source64and the n+ drain62compose an NMOS transistor. In the second embodiment of the present invention, a dielectric layer (not shown inFIG. 5A;224ofFIG. 11), which may be thick, is interposed between the gate electrode58and the active region. The n+ source64is formed in the p-well54, and the n+ drain62is formed to overlap the p-well54and the n-well52. Therefore, a drain of the NMOS transistor in the ESD protection device includes a drain62overlapping the p-well54and the n-well52to contact the n-well52. The n+ drain62may have an impurity concentration higher than that of the n+ source64due to an influence of the n-well52.

A p+ well pick-up66doped with impurities is formed in the p-well54. The p+ well pick-up66may be separated from the NMOS transistor by the device isolation layer56. The n+ drain62is connected to a circuit terminal60of the integrated circuit. In the second embodiment of the present invention, the n+ source64and the p+ well pick-up66are connected to a ground terminal, and the gate electrode58and the n+ drain62are connected to the circuit terminal60. A threshold voltage of the NMOS transistor may be high to maintain the NMOS transistor of the ESD protection device at turn-off at a steady state. Therefore, the insulating layer is interposed between the gate electrode58and the active region. The gate electrode58may be an extended portion of an interconnection, which will be described below, connected to the n+ drain62. In this case, the interlayer dielectric layer may correspond to a gate insulation layer.

Although a representative singular gate electrode is illustrated inFIG. 5A, the NMOS transistor may adopt a gate electrode in a finger structure to discharge a large amount of current. In this case, the n-well52vertically extends to connect to the n+ drain62. In addition, the p+ well pick-up66may be formed in the p-well54as a guard ring type surrounding the ESD protection circuit.

FIG. 5Bis an equivalent circuit diagram of the ESD protection device according to the second embodiment of the present invention.

Referring toFIG. 5B, the ESD protection device operates using an NMOS transistor T11and parasitic npn bipolar transistors Q21and Q22in the NMOS transistor T11. The n+ source64, the n+ drain62and the p-well54correspond to an emitter, a collector and a base, respectively, of the first npn bipolar transistor Q21. The n+ source64, the n-well52and the p-well54correspond to an emitter, a collector and a base, respectively, of the second npn bipolar transistor Q22.

When a junction among the n+ drain62, the n-well52and the p-well54breaks down due to application of an ESD voltage to the n+ drain62, the first and second npn bipolar transistors Q21and Q22are triggered. The first and second npn bipolar transistors Q21and Q22are driven by a voltage drop due to parasitic resistances R21and R22of the p-well54, such that an ESD current is instantly discharged to a ground terminal. The ESD protection device discharges ESD current by operation of a lateral npn bipolar transistor Q21, a vertical npn bipolar transistor Q22and the NMOS transistor T11. The lateral npn bipolar transistor Q21includes the n+ source64, the n+ drain62and the p-well54. The vertical npn bipolar transistor Q22includes the n+ source64, the n-well52and the p-well54. That is, the transistors are triggered at the lowest one of a junction breakdown voltage between the n+ drain62and the p-well54, a junction breakdown voltage between the n-well52and the p-well54, and a threshold voltage of the NMOS transistor T11, thereby instantly discharging the ESD current.

FIGS. 6 through 8illustrate cross-sectional views of stages in a method of forming the ESD protection device according to the first embodiment of the present invention.

Referring toFIG. 6, a deep n-well102is formed by implanting impurities in a substrate100. A vertical n-well104is formed by implanting impurities in the substrate100. The deep n-well102is separated a predetermined distance apart from a surface of the substrate. The vertical n-well104is connected to the deep n-well102and extends vertically to the surface of the substrate100.

A CMOS integrated circuit may have various well structures. For example, the integrated circuit may include a p-well where an NMOS transistor is formed, an n-well where a PMOS transistor is formed and a pocket p-well for a well biasing and a well isolation, etc. Therefore, the deep n-well102and the vertical n-well104may be formed without additional processes by changing an existing layout. A device isolation layer108may be formed before forming the wells. A first active region110ais a region where the NMOS transistor of the ESD protection device is to be formed. A second active region110bis a region where a well pick-up is to be formed. In an alternative configuration, the second active region110bmay be omitted and the well pick-up may be formed in the first active region110a. A surface of the first active region110aincludes a p-well region where a p-well106is formed and an n-well region where the vertical n-well104is formed.

Referring toFIG. 7, a gate electrode112is formed on the first active region110a. A gate insulating layer111is interposed between the gate electrode112and the first active region110a. The gate electrode112crosses over the first active region110aextends over the device isolation layer108. The gate electrode112divides the first active region110ainto two portions. The first active region110aat one side of the gate electrode112is a p-well region, and the first active region110aat another side of the gate electrode112includes the p-well region and the n-well region. An n+ source116and an n+ drain114are formed to either side of the gate electrode112by implanting impurities in the first active region110a. The n+ source116is formed in the p-well region, and the n+ drain114is formed to overlap the p-well region and the n-well region. Therefore, the n+ drain114is connected to the vertical n-well104. Impurities are implanted in the p-well region to form a p+ well pick-up118. The p+ well pick-up118is formed in the second active region110b,as described above, the second active region110bis not formed, the p+ well pick-up118may be formed to have a guard ring shape surrounding the ESD protection device. By adopting a guard ring structure, an ESD current flowing through the p-well106is concentrated in one direction, such that an increase of the current density may be prevented.

The p+ well pick-up118, the n+ source116and the n+ drain114may be formed during a formation of a diffusion layer in an internal circuit. Therefore, a formation order may be varied according to an order of forming the internal circuit.

Referring toFIG. 8, an interlayer dielectric layer124is formed on an entire surface of the substrate. The interlayer dielectric layer124is patterned to form contact holes exposing each of the p+ well pick-up118, the n+ source116, the n+ drain114and the gate electrode112. Although not illustrated inFIG. 8, the contact hole exposing the gate electrode112may be placed over the device isolation layer108. That is, the contact hole exposing the gate electrode112may be formed over the portion of gate electrode112extending over the device isolation layer108.

An interconnection, including a first interconnection126and a second interconnection128, is then formed on the interlayer dielectric layer124. The first interconnection126extends through one of the contact holes to contact the n+ source116. The second interconnection128extends through one of the contact holes to contact the n+ drain114. The first interconnection126may extend through another of the contact holes to contact the gate electrode112. In the drawing, the first interconnection126and the second interconnection128are illustrated as a single layer, but the first and second interconnection126and128may have a multi-layered structure. That is, local interconnections may be formed on the interlayer dielectric layer124and then another interlayer dielectric layer may be further formed on the local interconnections, such that global interconnections may be formed to connect the local interconnections. The local interconnections and the global interconnections may be formed using conventional multiple interconnections technology.

A silicide layer122may be further formed on surfaces of the n+ source116, the n+ drain114and the p+ well pick-up118before forming the interlayer dielectric layer124. An additional silicide layer (not shown) may be formed on a top surface of the gate electrode112. The silicide layer122may be formed by applying a conventional self-aligned silicidation process. A spacer pattern120may prevent a short of the silicide layer122and the gate electrode112and also form a ballast resistance between the silicide layer and the junction. Even if the silicide layer122is not formed, the spacer pattern120may be collectively formed in an integrated circuit device to junction engineer the internal circuit.

Although not illustrated in the drawings, the first interconnection126is connected to a ground terminal, and the second interconnection128is connected to a circuit terminal analogous to that shown inFIG. 4A.

FIGS. 9 through 11illustrate cross-sectional views of stages in a method of fabricating an ESD protection device according to the second embodiment of the present invention.

Referring toFIG. 9, a deep n-well202is formed by implanting impurities into a substrate200. A vertical n-well204is formed by implanting impurities in the substrate. The deep n-well202is separated a predetermined distance apart from a surface of the substrate200. The vertical n-well204is connected to the deep n-well202and vertically extends to a surface of the substrate200. The deep n-well202and the vertical n-well204may be formed without an additional process by changing a conventional layout.

A p-well206is formed by implanting impurities in the substrate200on the deep n-well202. A device isolation layer208is formed in the substrate200including the wells to define the first active region210aand the second active region210b. The device isolation layer208may be formed before forming the wells. The second active region210bis a region where the well pick-up is to be formed. If the well pick-up is formed in the first active region210a, the second active region201bmay not be formed. A surface of the first active region210aincludes a p-well region where the p-well206is formed, and an n-well region where the vertical n-well204is formed.

A dummy gate pattern212is formed on the active region210a. The dummy gate pattern212crosses over the first active region210aand a portion thereof extends over the device isolation layer208. A portion of the first active region210aat one side of the dummy gate pattern212is a p-well region, and another portion of the first active region210aat another side of the dummy gate pattern212includes the p-well region and the n-well region. Impurities are implanted in the first active region210asuch that an n+ source216and an n+ drain214are formed to either side of the dummy gate pattern212. The n+ source216is formed in the p-well region, and the n+ drain214is formed overlapping the p-well region and the n-well region. Therefore, the n+ drain214is connected to the vertical n-well204. Impurities are implanted in the p-well region to form a p+ well pick-up218. The p+ well pick-up218is formed in the second active region210b. If the second active region210bis not formed, as described above, the p+ well pick-up218may be formed in the first active region210a. The p+ well pick-up218may be formed to have a guard ring shape surrounding the ESD protection device. By adopting the guard ring structure, ESD current flowing through the p-well206is concentrated in one direction to prevent the current density from increasing.

The p+ well pick-up218, the n+ source216and the n+ drain214may be formed when an impurity diffusion layer of the internal circuit is formed. Thus, an order of forming those elements may be varied according to an order of forming an internal circuit.

Referring toFIG. 10, an interlayer dielectric layer224is formed on an entire surface of the internal circuit. The interlayer dielectric layer224is patterned to form contract holes225exposing each of the p+ well pick-up218, the n+ source216and the n+ drain214. The dummy gate pattern212may be removed before forming the interlayer dielectric layer224. If the dummy gate pattern212is an insulating layer, an interlayer dielectric layer224may be formed on the dummy gate pattern212and then planarized.

Before the interlayer dielectric layer224is formed, a silicide layer222may be further formed on a surface of the n+ source216, the n+ drain214and the p+ well pick-up218. In this case, a silicide layer may not be formed at the region between the n+ source216and the n+ drain214because of the dummy gate pattern212. The dummy gate pattern212may then be removed after the silicide layer222is removed.

Referring toFIG. 11, an interconnection, which includes a first interconnection226and a second interconnection228, is formed on the interlayer dielectric layer224. The first interconnection226extends through the contact holes225to connect to the p+ well218and the n+ source216. The second interconnection228extends through one of the contact holes225to connect to the n+ drain214. The second interconnection228may extend over the region between the n+ source216and the n+ drain214. In this case, one sidewall of the second interconnection228may overlap the n+ source216. If a voltage over a predetermined level is applied to the second interconnection228, a channel may be formed at the first active region210abetween the n+ source216and the n+ drain214. That is, an extended portion G of the second interconnection228, the n+ source216and the n+ drain214may compose a MOS transistor. In this case, the interlayer dielectric layer224between the extended portion G and the first active region210amay correspond to a gate interlayer dielectric layer of the MOS transistor. InFIG. 11, the first and second interconnections226and228are illustrated as a single layer, but each of the first and second interconnections226and228may be formed to have a multi-layered structure. That is, local interconnections may be formed on the interlayer dielectric layer224and then other interlayer dielectric layers may be additionally formed on the local interconnections, thereby forming global interconnections for connecting the local interconnections. The local interconnections and the global interconnections may be formed using a conventional multiple interconnections technology.

Although not illustrated in the drawings, the first interconnection226is connected to a ground terminal, and the second interconnection228is connected to a circuit terminal analogous to that shown inFIG. 5A. When an ESD voltage is applied to the second interconnection228, the ESD protection device operates. If the ESD voltage is higher than a predetermined level, the extended portion G of the second interconnection228may form a channel formed between the n+ source216and the n+ drain214to discharge the ESD current to the ground terminal through the n+ source216.

According to the present invention, an ESD current is discharged through a ground terminal by operation of both a lateral npn bipolar transistor and a vertical npn bipolar transistor, such that a current density of a weak substrate surface can be reduced. Since the current is discharged according to a bulk path of substrate spaced apart from the substrate surface, Joule heating generating from the substrate surface can be suppressed. In addition, an n-well and an n+ drain are connected together such that an impurity concentration of the n+ drain is increased by the impurities of the n-well. If a trigger voltage is low, ESD is effectively prevented and a stress of the ESD protection device can be reduced.

Moreover, the n-well connected to the drain may be formed while forming the well structure of the internal circuit only by changing a typical layout. Therefore, the existing process can be applied as it is because an additional process is not required. In addition, the present invention changes a well structure without increasing lateral dimensions, such that the ESD protection device can have improved intolerance without an increased area.