Built-in self-test arrangement for integrated circuit memory devices

An integrated circuit has a built-in self-test (BIST) arrangement (60). The built-in self-test arrangement includes a read only memory (ROM), (140) that stores test algorithm instructions. A ROM logic circuit (410) receives an instruction read from the read only memory and produces a group of output signals dependent upon the instruction. A BIST register 420 receives and stores the group of output signals from the logic circuit for controlling self-test of the integrated circuit.

This is a Non Provisional application filed under 35 U.S.C. 119(e) and 
claims priority of prior provisional Ser. No. 60/016,516 of inventor Hii 
et al. filed Apr. 30, 1996. 
CROSS REFERENCE TO RELATED APPLICATIONS 
This application is related to Ser. No. 08/840,362 of inventor Hii et al. 
filed on Apr. 29, 1997 which claims priority under 35 USC 119(e) of prior 
provisional 60/016,875 of inventor Hii et al. filed on Apr. 29, 1996. 
FIELD OF THE INVENTION 
This invention, relates to the field of testing an integrated circuit 
device and more particularly to a built-in self-test (BIST) arrangement 
for an integrated circuit device. 
BACKGROUND OF THE INVENTION 
In conventional testing of memory devices, a tester is used to supply the 
control signals such as RAS, CAS and WE, address signals, such as Ao-An, 
and data to the device under test. Outputs from the device under test are 
sampled by the tester to determine whether the device passes or fails. 
Testing of memories requires longer tester times, as device density 
increases. This results in escalating test cost. As the capacity of 
integrated circuit memory devices increases to 256 Mbits and above, 
testing time per device becomes a major component of cost of integrated 
circuit memory devices. 
One way to test integrated circuit memory devices in less time per device 
is to apply a single test data bit to several cells concurrently by 
multiplexing the single bit to the several cells in parallel. Some 
failures, however, cannot be screened unless a single cell is accessed at 
a time. With limited parallelism, i.e., a number of units being tested 
simultaneously, high test time also translates into a long manufacturing 
cycle time. Testing of one batch of memory devices requires most of the 
other devices to be waiting in queue to be tested while some of the memory 
devices are actually undergoing functional test. One solution would be to 
get more testers, but this is not practical as it involves even higher 
cost. The time to deliver a batch of tested memory devices to a customer 
increases as a result. Another solution is to apply the test from the 
testers in parallel to the devices under test. The problem with this 
solution is that the parallel leads occasionally cause good devices to 
fail because of cross talk among the parallel leads. 
Thus there is a problem in finding some way to efficiently test large 
capacity memory devices without requiring an enormous amount of time on a 
tester per memory device. 
SUMMARY OF THE INVENTION 
This problem and others are resolved by an integrated circuit which has a 
built-in self-test (BIST) arrangement. The built-in self-test arrangement 
includes a read only memory that stores test algorithm instructions. A 
logic circuit, receives an instruction read from the read only memory and 
produces a group of output signals dependent upon the instruction. A BIST 
register receives and stores the group of output signals from the logic 
circuit for controlling self-test of the integrated circuit. A pass/fail 
comparator circuit compares expected data bits with data bits written into 
and read from a memory array to determine whether the integrate circuit 
passes or fails the test.

DETAILED DESCRIPTION 
Referring now to FIGS. 1-4, there is shown the block diagram of an 
integrated circuit dynamic random access memory device 50 including a 
built-in self-test (BIST) arrangement 60. The device 50 is designed to 
operate as a synchronous random access memory during normal operation. 
Alternatively the built-in self-test arrangement operates in a distinctive 
self-test mode at times while the device 50 is not operating in the normal 
mode. The built-in self-test arrangement is designed such that all the 
test signals are generated internally to a device, and the arrangement 
only takes a simple setup to get the device into a self-test mode to 
perform a self test. With the simple setup up, the built-in self-test 
arrangement performs a memory self-test in a cost effective procedure. The 
arrangement also allows many devices to be tested in parallel without 
being limited by tester resources. 
While the device 50 operates in the normal mode, it operates like a 
well-known synchronous dynamic random access memory device. Row and column 
addresses produced by a digital processor, such as a microprocessor, are 
time multiplexed by way of the address bus A0-A13 into an address buffer 
100 until control signals RAS.sub.-- and CAS.sub.--, respectively, which 
load them. Thereafter they are decoded either by the row decoder 200 or 
the column decoder 210. The control signals RAS.sub.-- and CAS.sub.-- 
also are produced by the digital processor, which is not shown. 
Depending upon the state of the write enable signal WE.sub.-- from the 
digital processor, data is either written into or read out from storage 
cells located in the banks of the memory array 220. Data, to be written 
into the banks of the memory array 220, is applied to the device 50 by way 
of a data bus DQ0-DQ31. This in-coming data is buffered in a data buffer 
circuit 230 and forwarded by way of an internal data bus 240 to the memory 
array 220 where it is stored until it is written over or until it is no 
longer refreshed at specified intervals. While data is stored in the 
memory array 220, that data can be addressed and read out of the array 220 
through the internal data bus 240 and the data buffer 230 to the data bus 
DQ0-DQ31. This data bus DQ0-DQ31 typically is connected to the data 
receiving and sending terminals of a digital processor, such as a 
microprocessor that is not shown. 
Because the memory device 50 is a synchronous dynamic random access memory, 
a system clock signal CLK is applied to the device from an external source 
for synchronizing its operation with the digital processor, peripheral 
devices, and control circuitry that are connected in a system. The system 
clock is the clock which controls operation of the digital processor. The 
clock signal CLK is applied to a clock buffer 110, which outputs an 
internal clock signal CLK for operating the memory array 220 during normal 
operation. This internal clock signal CLK controls operation of address 
decoding, writing data to the memory array, and reading data out of the 
memory array during such normal synchronous memory operations. 
The control signals RAS.sub.--, CAS.sub.--, and WE.sub.--, which are 
applied to the memory device 50 from the digital processor, are applied to 
a control signal buffer 120. During normal mode operation, these control 
signals pass through the control buffer 120 and a control bus 125 to the 
main control unit 130 of the memory array 220. At the memory array 220 
during normal operation, these control signals RAS.sub.--, CAS.sub.--, and 
WE.sub.-- together with the internal system clock signal CLK control 
operations of the array 220, as previously described. 
Normal mode operation and self-test mode operation are two separate and 
distinct operations of the memory device 50. Those two modes occur 
alternatively. Thus while the device 50 operates in its normal mode it is 
not able to inadvertently go into its self-test mode. Also while it is in 
its active self-test mode, it cannot inadvertently go into its normal 
mode. These are conditions that are imposed upon the operation of the 
device 50 by the built-in self-test arrangement 60 to be described. 
As just mentioned, the self-test mode of operation is different from the 
normal mode of operation. Self-test mode is entered only upon power up of 
the memory device 50. Special signal conditions are applied at that time 
to put the device 50 into the self-test mode. 
In this proposed BIST scheme, only DC signals are needed external to the 
device to enter the self-test mode and to actually proceed through the 
self-test. The following types of external DC signals are supplied: 
a) An overvoltage on one of the multiplexed address pins (e.g., pin A4.) 
b) A switch on CS.sub.-- which allows both a `0` and a `1` to be connected 
to it. 
c) A logic level of `0` or a `1` on the rest of the address pins for tests 
and options selections. 
d) Pass, fail detection on one of the output pins. 
e) An output detector pin to identify completion of the self-test 
operations. 
With the above set up, only DC signals are involved. No complex timing is 
needed. Thus there is no need to be concerned with signal quality. The 
signal quality to the device is always good since the signals are DC. 
Multiple devices can be put on a BIST board and self tested 
simultaneously. Test cycle time can be reduced per device since BIST can 
be applied to all devices on the BIST board in parallel. 
FIG. 6 shows an arrangement for mounting several integrated circuit devices 
which are interconnected in parallel so that they all can be set up at 
once for self-test. Once set up the self-test can be run concurrently on 
some of or all of the devices. 
While in self test operations, BIST circuits take over control of all the 
signals such as CLK, RAS.sub.--, CAS.sub.--, WE.sub.--, the address bits, 
and the data bits. For example, a BIST address bit B.sub.-- Ax is 
generated by the BIST circuits. During a self-test operation, the BIST 
address bits replace the externally generated address bits Ax. The BIST 
address bits B.sub.-- Ax interface with the main circuit right out of the 
address buffer. 
During normal mode operation, the BIST address bits B.sub.-- Ax are not 
generated and are ignored. During power up, if a BIST request is detected, 
the address lines are used to bring in information into the BIST 
arrangement. Referring now to FIG. 7, a test enabled shift register 330 
receives and stores data that determines whether or not specific tests are 
enabled. The data are stored in the shift register at the righthand side 
of FIG. 3. During active self-test mode, BIST generated address signals 
are used for operating the device and externally applied address signals 
Ax are ignored. 
Referring now to FIG. 8 there is a block diagram of a BIST address control 
circuit 65 that controls generation of array addresses during an active 
self-test operation. FIGS. 9, 10, 11 and 12 are logic schematics of 
circuits included within the address control circuit 65 of FIG. 8. 
The BIST signals interface with the main circuit as close to the buffer as 
possible to ensure that they closely simulate conventional test 
conditions. This will allow the BIST circuits to test as much of the 
memory device circuitry as possible. 
FIGS. 13A.sub.-- 13C show the interface between BIST generated signals and 
the main devices. The main function of the BIST generated signals is to 
replace the external signals that the memory device receives. Thus at the 
BIST interface there is a multiplex circuit which chooses between the BIST 
generated signals B-Ax and the external signals Ax from outside. The 
address lines are being used for multiple purposes, besides the above two 
cases, they are also used in power up to bring information into the BIST 
circuit, as illustrated in FIG. 13B. Control signals B.sub.-- PADDIS and 
B.sub.-- IN.sub.-- EN, generated by the self-test arrangement control how 
the multiplexer operates at anytime. 
The address bus A0-A13 of FIG. 1 is used for applying the special signal 
conditions for the self-test mode during and after power up. An 
overvoltage signal is applied by way of one lead of the address bus A0-A13 
to a BIST detector circuit 300, which responds to the overvoltage 
condition by putting itself in a standby self-test condition. In this 
description the address lead A4 is used as an exemplary over voltage lead. 
While the BIST detector circuit 300 remains in its standby condition, it 
allows the built-in self-test arrangement to prepare for testing by 
accumulating information about a specific test to be run. Typically the 
specific test will be selected from a large group of tests which might be 
run. The built-in self-test arrangement will remain in the self-test 
standby condition until another input signal is applied. Meanwhile data 
can be written into or read out of the memory array 220, as if it were in 
the normal mode because the built-in self-test arrangement 60 is in 
standby rather than in active self-test mode. 
The self-test arrangement 60 is put into the active self-test mode from 
standby by applying a high level signal CS.sub.-- by way of a lead 135 to 
the BIST detector circuit 300. The built-in self-test arrangement 60 and 
the memory device 50 will operate in the active self-test mode as long as 
the signal CS.sub.-- remains at the high level and then return to normal 
operation when the signal CS.sub.-- goes to its low level. 
Referring now to FIG. 14, the BIST detector circuit 300 includes input 
terminals 301, 135, and 303 for receiving, respectively, a signal VUPB, an 
over voltage signal A4 from the lead of the address bus A0-A13, and the 
control signal CS.sub.--. An output lead 304 carries a built-in self-test 
enable signal BIST.sub.-- EN that indicates when the device 50 is 
operating in its self-test mode. The BIST detector circuit 300 detects a 
BIST request during power up only. To detect a BIST request requires an 
overvoltage to be detected at power up and the signal CS.sub.-- having a 
value of `0` at that time. When the circuit 300 detects these two 
conditions at power up, the chip goes into a BIST standby mode. While the 
circuit 300 is in BIST standby mode and the signal CS.sub.-- goes high, 
the circuit 300 enters the self-test active mode. 
FIG. 15 presents the timing diagram for the operation of the BIST detector 
circuit 300 of FIG. 14. Several key signals are presented in FIG. 15 
together with their interdependency. It is noted that all of the signals 
applied to the BIST detector circuit 300 are fundamentally voltage levels. 
As will be demonstrated subsequently herein, no external fluctuating 
control signals need to be applied to the memory device 50 during the 
active self-test mode. All signals for performing the repertoire of tests 
are produced by the built-in self-test arrangement 60 on the device 50. 
A more detailed description of the arrangement and operation of the BIST 
detector circuit 300 is presented in a co-pending patent application, Ser. 
No. 08/840,428 (TI-22640) which was filed concurrently herewith. In that 
patent application, the BIST detector circuit 300 is referred to as an 
entry and exit control circuit. The subject matter of that patent 
application is incorporated herein by reference thereto. 
Two signals, A4 and control signal CS.sub.-- are multiplexed for built-in 
self-test entry. The signal A4, or any other address bit, is multiplexed 
as an overvoltage. Control signal CS.sub.-- is used for timing BIST entry 
and EXIT. A BIST request is detected if an overvoltage is detected and the 
control signal CS.sub.-- is low when the device is being powered up. If 
an overvoltage is detected at the falling edge of VUPB, the device will go 
into BIST standby mode. The device will only go into BIST active mode if 
the control signal CS.sub.-- is subsequently pulled high. This will allow 
full control of the time to enter the BIST active mode. During BIST 
operation, if CS.sub.-- is pulled low, the device will exit BIST 
immediately. Normal operation occurs when CS.sub.-- is low. This prevents 
the BIST active mode from occurring during normal mode operation. 
In BIST standby mode, the device can operate as if it were in normal mode. 
Note that the control signal CS.sub.-- behaves normally while the device 
is operating in normal mode. It is only in the BIST mode that the control 
signal CS.sub.-- function differently. Design for test (DFT) modes can be 
executed when device is in BIST standby mode. One of the ways to use DFT 
mode while in BIST standby is to have the address range mode load start 
and stop addresses before the BIST active mode operation. 
Referring now to FIGS. 16-21, there are address range registers for storing 
address information used during self-test operations. When a BIST request 
is detected, an internal signal B.sub.-- SR.sub.-- LOAD is generated to 
load in the information located on the address lines except the address 
for the overvoltage signal on lead A4. The information loaded in contains 
two sets of information. Test selection data on the address leads A0-A3, 
A5-A10 determine whether or not each specific test is to be run in BIST 
active mode. Secondly, BIST operation options such as internal external 
clock option, full/sub array option, enable disable output option. 
In FIG. 3, there is shown a BIST oscillator circuit 310 that includes an 
arrangement for generating a continuously repetitive clock signal B.sub.-- 
CLK which is used to produce a group of specific clock signals for 
controlling different parts of the built-in self-test operation. 
FIG. 22 is a logic schematic of a BIST clock generator circuit 350 of FIG. 
3. It derives BIST clock signals B.sub.-- CLK.sub.-- A, B.sub.-- 
CLK.sub.-- B, and B.sub.-- CLK.sub.-- C. 
Upon entering the active self-test mode, the clock signal B.sub.-- CLK is 
applied to the clock buffer circuit 110 of FIG. 1 for taking over control 
of the clock buffer circuit 110, which thereafter during the active 
self-test mode produces the clock signal B.sub.-- CLK to control access to 
and the operations of the memory array 220, as well as parts of the 
built-in self-test arrangement 60. Initially data from the address buffer 
100 is transferred by way of an internal address bus 140 to an enabled 
tests circuit 330 in FIG. 3. Exemplary circuit 330 is a shift register 
arrangement that stores data identifying a specific test, or a group of 
tests to be run during the relevant active self-test mode. This data may 
be, for example, a high level for each test to be run and a low level for 
each test that is not to be run. Once the selected test data is stored in 
the enabled tests circuit 330, a group of addresses may be stored in the 
address range registers 340. 
Referring now to FIG. 23, there is shown a diagram of the information that 
is stored in the enabled test circuit 330. In FIG. 23, the address bits 
positions A0-A3, respectively, represent the gross test, the pause test, X 
march and Y march. Address bit positions A5-A10, respectively, represent 
short disturb, long disturb, page disturb, burn in, write one row, and 
read one column. Address bit position A11 and bank addresses BA0 and BA1, 
respectively, represent output enable, sub array option, and internal 
clock/external clock selection. 
A clock is needed for the BIST operation. BIST circuit has an internal 
oscillator which provides this clock with a fixed frequency. There is an 
external clock option built in for engineering and debug purposes which 
allows the clock frequency to be varied if needed. The decision to use an 
external or internal clock is loaded in when a BIST request is detected 
during power up. 
The previously mentioned address range registers 340 include a group of 
four registers which receive and store, respectively, row and column 
addresses which determine start and stop addresses in the memory array 220 
where the test or tests should commence and end. Such addresses are used 
at the discretion of the person responsible for testing the device 50. A 
default condition runs the tests throughout the entire memory starting at 
row address 0 and column address 0. Thus the address range registers 340 
are reset to zero when the device 50 is initially put into the active 
self-test mode. Thereafter the range addresses may be stored if desired 
during a DFT mode load operation. 
During prototype debug on any early production chip, it is unlikely that a 
complete array will work correctly. Under such circumstances, the BIST 
test will always fail since there will always be some cells which do not 
work and will cause failure of the BIST tests. This means that the BIST 
logic cannot be completely checked out since there will never be an 
application of BIST which permits the BIST logic to return a "PASS" signal 
until a completely good part is manufactured. A second problem occurs 
during debug of the chip. If the BIST is limited to the complete array 
test, it cannot be used to target a subset of the array as an aid for 
debug. 
Sub array testing permits the starting address to be any location and the 
ending address to be any location and they cna be loaded into the BIST 
address range registers via a DFT mode. The BIST testing is applied 
between the starting and ending locations including one address location 
of the starting address is the same as the ending location. The address 
ranges can be changed each time prior to BIST application thereby 
permitting the BIST to be applied to islands to fault free areas through 
repeated testing. 
Referring now to FIGS. 24 and 25, there is shown a program control circuit 
that includes a program counter 360. The BIST program counter 360 is 
included in the built-in self-test arrangement 60 for controlling test 
sequences. Upon initiation of the active self-test mode, the BIST program 
counter 360 is reset by a signal B.sub.-- RESET to its zero state. This is 
a sequential logic arrangement in which its current state, in combination 
with the state of data furnished by a BIST ROM register determines the 
next state of the BIST program counter 360. The state changes in response 
to a clock signal B.sub.-- CLK.sub.-- B applied from the clock generator 
350. 
FIG. 26 is a logic schematic for a BIST ROM address decoder 370, shown in 
FIG. 3. The state of the BIST program counter 360 is represented by a 
group of binary signals that are applied by way of a bus 361 to the input 
of the BIST ROM address decoder 370. The group of input binary signals are 
decoded into a 1 out of 64 code for selecting a row of data from the BIST 
ROM 400. 
FIG. 27 shows the schemtic layout of an sixty-four word by twelve bit BIST 
ROM 400 of FIG. 4. The BIST ROM 400 is a sixty-four row read only memory 
that stores sequences of instructions for controlling several different 
test routines used to determine the operability of the memory array 220. 
The proposed BIST scheme has ten algorithms stored in a ROM. Each 
algorithm is typically made up of a series of instructions. The ten 
algorithms take up sixty-four ROM words and each Rom word has twelve bits. 
Each row address applied to the BIST ROM 400, accesses a row of data 
stored therein in response to a clock signal B.sub.-- CLK. 
The first instruction in an algorithm is an instruction to determine if 
that test is being enabled. Whether the test is enabled or not is decided 
at power up when test selection information is loaded into the test 
enabled register. All or any subset of tests can be selected. A block of 
test code is skipped if a `0` logical value is loaded in the corresponding 
tests enabled register. 
For most algorithms, the last instruction in an algorithm tests for 
`inverted pattern`. In a typical test, two data patterns (`0` and `1`) 
need to be performed. This means each test is executed twice, once for 
each pattern. This instruction looks at a register to determine if the 
current test is executing the normal pattern (pattern `0`). If it is, then 
the program counter will jump to the start of the test and repeat the test 
with an inverted pattern. If the instruction determines that it is 
executing an inverted pattern, it will simple increment the program 
counter by 1 and move on to the next test since both data patterns have 
already been executed. 
Referring now to FIG. 28, there is shown the table of data stored in the 
BIST ROM 400. In the lefthand column is the list of names of ten 
algorithms which represent the tests which may be selected to be run plus 
an instruction that all tests have been completed. 
The first algorithm GROSS is for running a gross test. There are four rows 
of data, each representing one instruction for the gross test. Addresses 
for the instructions are shown in hexadecimal code in the second column 
from the left. The righthand column presents the mnemonic name for each 
instruction. The main block of the table presents the data which is stored 
in the BIST ROM 400. There are twelve columns of data in the table. In the 
table, there is a bold horizontal line setting off the beginning and 
ending addresses of each algorithm. Thus there is a bold line below the 
address hex 3 which is the fourth instruction in the algorithm GROSS. 
The four instructions in the algorithm GROSS are jump not test enable 
(jnte) to pause, write all cells zero, read all cells with expected data 
zero, and invert data and jump if not previously inverted (divnj). The Z1 
is the label at which to jump. 
Referring now to FIG. 29, there are two major types of instructions. The 
first type is the program control instruction. This type of instruction 
deals with the flow of the program. The program control instruction are 
introduced to control BIST operation. The second type is the array access 
instruction which control how the cells of the array are to be accessed 
and written to and/or read from. They are basically the same type of 
instruction usually found on a tester which are translated into BIST ROM 
format. An instruction that reads back a pattern from the array (220) is 
an example of a array access instruction. 
The instruction is divided into two parts. The first six bits of an 
instruction defines the actions to be taken and the last six bits is the 
data associated with the instruction. 
For an array access instruction such as read whole array, the first six 
bits define the type of array access, whether it is a write or a read or 
both, whether the full array, only the rows, or the columns are accessed. 
To read from the whole array, Read (bit11), X(bit9) and Y(bit8) are set to 
1. The last six bits of the instruction provides information on how the 
whole array is read including the timing sets to be used (Tset0, Tset1), 
the data values (ED) and pattern () and whether the address is to be 
incremented or decremented. 
For a program control instruction such as the `test enable` instruction. 
The four most significant bits are `0`, Bit7 and Bit6 determines the 
program control type. The last six bits provides the address to be jumped 
to if indeed the decision is made to jump. 
There is an unconditional jump instruction. `110011` for the most 
significant 6 bits, and the address to jump to for the 6 least significant 
bits. 
The last instruction in the ROM, see FIG. 28, is an idle instruction to 
signal the end of BIST operation. The last six bits of this instruction 
holds the revision number of the current 256M. 
There are many possible combinations of instructions that can be programmed 
with the current circuits. If a new algorithm is needed for a BIST 
operation. It can be included by simply reprogramming the ROM. 
Combinations of options available to make up an instruction are as 
follows: 
__________________________________________________________________________ 
Timing sets 
Access mode 
Addressing 
Array size 
`0` or `1` 
Data Pattern 
__________________________________________________________________________ 
TSETA READ INC FULLA 
PATTERN0 
CKBD 
TSETB WRITE DEC ROW PATTERN1 
ALTERNATE 
TSETC RMW COL 
__________________________________________________________________________ 
Referring now to FIGS. 30 and 31, there is shown logic schematics for a ROM 
logic circuit 410. As each of the instructions is read out of the BIST ROM 
400, the data is applied to the input of the ROM logic circuit 410, which 
is a combinational logic circuit that decodes the twelve bits of data of 
each instruction word. Output signals from the ROM logic circuit 410 are 
applied to the data inputs of a ROM register circuit 420 where the data 
are stored for the duration required to complete execution of the 
instruction. 
When the built-in self-test arrangement 60 is put into the active self-test 
mode, the BIST program counter 360 is reset. This initial state of the 
program counter 360 is decoded through BIST ROM address decoder 370 to 
produce a row address signal for the BIST ROM 400. After the row address 
is applied and in response to a clock signal, the data from the selected 
row of the BIST ROM 400 is read out. All of the data read out from the 
selected row is applied to the input of the ROM logic circuit 410. 
FIGS. 30 and 31 present an exemplary logic schematic diagram of the ROM 
logic circuit 410 that performs desired combinational logic functions on 
the row of data applied from the selected row of the BIST ROM 400. The 
circuit 410 produces a group of output signals resulting from logical 
processing through the circuit 410. This group of output signals from the 
circuit are applied in parallel to and are stored in the ROM register 420, 
which is arranged to forward them by way of a BIST data bus 421 to the 
pass/fail comparator circuit 430, by way of a group of leads 422 to the 
BIST timing generator 440, and by way of a program counter input bus 423 
to the BIST program counter 360. 
Referring now to FIG. 31, there is shown a logic schematic of an exemplary 
ROM register circuit 420. The data applied onto the program counter input 
bus 423 is accepted by the program counter 360 only when a program control 
instruction is being executed. Data applied to the BIST timing generator 
controls generation of self-test signals, such as B.sub.-- RAS.sub.--, 
B.sub.-- CAS.sub.-- and B.sub.-- WE.sub.--, which perform the functions 
of their similarly named control signals RAS.sub.--, CAS.sub.--, and 
WE.sub.--, used by a microprocessor to access the memory during normal 
operation. Signals, applied by way of the BIST data bus 421 to the 
pass/fail comparator circuit 430, include memory access instructions and a 
data bit. 
FIG. 44 presents the logic schematic diagram of an exemplary pass/fail 
circuit 430 that can be used in the built-in self-test arrangement 60. The 
pass/fail circuit 430 is responsive to control signals and a data bit 
received by way of the BIST data bus 421 from the ROM register 420 to 
produce a sequence of groups of data signals to be written into at least 
one bank of the memory array 220 in response to a write instruction from 
the BIST ROM 400. Pass/fail circuit 430 also receives control signals and 
a data bit by way of the BIST data bus 421 and read out data on a DQ bus 
431 from the memory array 60, in response to a read instruction. In this 
instance, the data bit from the BIST data bus 421 is processed to agree 
with the state of a prior-existing data bit that was written into the 
array location/locations from which the data on the DQ bus 431 is read. 
The processed data bit is referred to as an expected data bit. This 
expected data bit is compared with the data read from the memory array 60 
and the result of the comparison is a Pass signal if the compared data are 
equal and is a Fail signal if the compared data are not equal. The Pass 
signal, indicating that the circuits traversed by the written in and read 
out data and the storage cell are operating correctly, is a low level 
signal. A Fail signal, indicating that some part of the circuits traversed 
by the written in and read out data or the storage cell is malfunctioning, 
is a high level signal. 
A Fail signal is transmitted by way of a lead B.sub.-- Pass/Fail to a PF 
register 432 where it is stored. Subsequently the stored Fail signal can 
be conveyed through a DQ buffer circuit 230 to an external pad of the 
memory device. PF register 432 is reset upon entry of the active self-test 
mode. Pass signals are ignored and in effect discarded because they are a 
low level and the PF register is reset to begin the test operation. An 
assumption is made that the device is operable. So a single test failure 
is the only information of importance to be retained. 
Referring to FIG. 32, a VHDL language description of the Pass/Fail 
comparator is shown. VHDL language is a standard language for describing 
logic circuits used by designers today. Using signal CKBDI for checker 
board data, B.sub.-- ALTERNATE for alternate data, B.sub.-- RDATA for 
expected data (ED) and B.sub.-- WDATA for write data (DAT), the data which 
is expected to write and to compare the read data is calculated. The read 
data is compared to the calculated expected data to determine if the test 
passed or failed. 
Referring to FIG. 33, the functional table is given. The 32 bits of the 
array 220 compressed to 4 data bits using 8 DQ lines. The compression 
table is shown in FIG. 33. B.sub.-- PF.sub.-- results gives the pass or 
fail depending on the corresponding values shown in the table. 
Build In Self Test (BIST) 
10.00 Overview of BIST 
In memory functional testing, various algorithms are used to to test a 
device. Tester are normally used to generate test signals, which represent 
the test algorithms, to the device. The outputs of the device are then 
sampled by the tester to determine pass or fail. For very high density 
memory devices such as 256M SDRAM, test time is expected to be very high 
thus making it not practical or cost efficient to do all functional 
testing on a tester. Build In Self Test (BIST) circuits are designed to 
replace the testers. The role of BIST circuits (FIGS. 51, 52) is to 
generate all the test signals associated with the test algorithms internal 
to the device. Instead of using a tester, a device under test will power 
up in BIST mode, if certain voltage conditions are satisfied, and test 
itself In BIST mode, BIST generated signals takes control of control 
signals such as RAS and CAS as well as all the addresses and data. 
Advantage of BIST: Test Cost savings. 
The build In self circuit is made up of the following (FIG. 60): 
Oscillator with a 50 Mhz frequency 
Overvoltage detector on A4 
64 word X 12 Bit ROM 
6 Bit Program counter 
6 to 64 decoder 
14 bit X register, 9 bit Y register and 14 bit refresh register 
Timing generators 
Address range counters 
Shift register for storage of enabled test algorithms 
Internal pattern data generator 
Pass fail compare circuits 
Output mutiplexer. 
BIST circuit takes up 1.9 mm.sup.2 in silicon area and occupies about 0.5% 
of the total chip area. It is located at the right most end of the chip, 
critical speed interface logic such as the address interface is placed 
near the speed path to avoid slowing down the normal operation. Control 
logic, ROM and various other BIST logic is placed on the end of the chip 
where silicon area is lower priority than in the center or intersection 
areas of the chip (FIG. 61): 
10 algorithms were implemented in the 256M BIST scheme, Summary for them 
are show (FIG. 62) 
Behavior for BIST circuits has been described in VHDL code and simulated 
using QVHDLsim. ALL BIST circuits except for the oscillator, over voltage 
detector and ROM were synthesized using Autologic 2. 
10.01 BIST Entry and Exit 
BIST Entry and Exit scheme is designed to satisfy the following 
requirements. 
1. Simple Entry and Exit sequence with no timing required in order for BIST 
to operate with low cost BIST boards. 
2. No inadvertent BIST entry. 
3. Ability to alternate between Normal and BIST mode for read and write for 
testing BIST circuit operation. 
It is important to have a simple entry and exit sequence so that BIST 
operation can be done on a simple BIST board with very high parallelism 
without having to worry about signal quality. 
BIST Entry: 
To do this, BIST entry is designed such that only DC signal is needed. To 
get into BIST, all that is needed is an overvoltage on A4 and low on CS 
during power up (and high or low on other pins depending the options 
chosen). This will put the device into a BIST standby mode (FIG. 63) 
While in standby mode the device will operate as if it is in normal mode 
and it can perform read, write and regular MRS or even DFT commands. 
A rising edge on the CS pin will start the BIST operation while device is 
in BIST standby mode. 
It is important to have a delay from overvoltage detection to actually 
starting BIST operation because it gives the user the opportunity to start 
the BIST operation at a time suitable to him. 
It allows the user to use a DFT mode to set the address range, for example 
or giving the device enough time to settle down to a steady state before 
BIST operation began. It will also allow the user to write a row in normal 
mode and later enter BIST to read back the data in the array in BIST mode 
(or vice versa) to check BIST circuit functionality. 
BIST Exit: 
A falling edge of CS will exit all BIST operation unconditionally and the 
only way to get back into BIST mode is to power down and then power up 
again with overvoltage. 
It is also imperative to prevent inadvertent BIST entry. To achieve this, 
overvoltage can only be detected at power up at the falling edge of VUPB. 
It cannot be detected at any other time. This and the CS interlock during 
power up gives the device only one chance to go into BIST standby mode. 
This minimizes the chance of inadvertent BIST entry during device 
operation. 
When an overvoltage is detected at A4, it generates a B.sub.-- SR.sub.-- 
LOAD pulse. This pulse loads the information available on the other 13 
addresses into a shift register. These contain the information on which 
tests are to be executed while in BIST as well as information for clock 
option, array size option and output enable option. Details on these can 
be found in B.sub.-- SHIFT block. 
The Entry and Exit timing sequence for BIST operation is summarized here 
(FIG. 64): 
An example of a power up setup is on an example pinout (FIG. 65). 
10.1 BOV 
__________________________________________________________________________ 
INPUTS: B.sub.-- OVDETECT,B.sub.-- DONE,TLBADDRNG,PBCSB.sub.-- BIST,VUPB 
OUTPUTS: 
B.sub.-- SR.sub.-- LOAD,B.sub.-- IN.sub.-- EN,B.sub.-- EXTCLK,B.su 
b.-- PADDIS BIST.sub.-- EN 
BIST.sub.-- MCEN 
# OF CIRCUITS: 
1/chip 
LOCATION: 
right side of chip 
__________________________________________________________________________ 
The function of this circuit is to detect overvoltage during power up. It 
does not detect overvoltage at any other time. 
During power up, at the falling edge of VUPB, a pulse VUPBN which gives 
about 16 ns to charge up B.sub.-- OVERDETECT is generated. The falling 
edge of VUPBN will set the overvoltage latch OVLATCHB to low if B.sub.-- 
OVERDETECT is a high and if PBCSB.sub.-- BIST is low. A low on OVLATCHB 
signals the detection of overvoltage and entry to BIST standby mode. 
During the BIST standby mode, if PBCSB.sub.-- BIST subsequently goes high, 
BIST.sub.-- EN will go high to signal the start of BIST operation. A high 
to low transition of PBCSB.sub.-- BIST will reset the overvoltage latch 
and set OVLATCHB to high. It also brings BIST.sub.-- EN to low signalling 
BIST exit. 
If there is no overvoltage detected during power up, B.sub.-- OVERDETECT 
will be low and it will not get into BIST standby mode. 
If overvoltage is detected at power up and OVLATCHB latch is set at power 
up, B.sub.-- SR.sub.-- LOAD pulse is generated to load the information on 
the address lines into a shift register. This information determines which 
test will be performed in BIST mode. 
B.sub.-- PADDIS and B.sub.-- IN.sub.-- EN are used to control the 
multiplexing of BIST signals and external signals. In normal operation, 
external signals are used. This is the normal mode in which the device 
operates in. 
If overvoltage is detected at power up and the device is ready for BIST 
operation, B.sub.-- IN.sub.-- EN will be set to high to allow address 
signals to get to BIST circuits. In TLBADDRNG DFT mode, where the start 
and stop addresses are loaded into the BIST circuit, B.sub.-- IN.sub.-- EN 
is also high. 
In BIST operation, external signals are ignored and BIST signals (B.sub.-- 
ADDRx) are used. 
B.sub.-- EXTCLK is used to bring in the external clock signal to the BIST 
circuits for two purposes. The external clock is needed for the external 
clock option. It is also needed during the DFT mode to load in the address 
range (TLBADDRNG) 
10.2 BOVBIAS 
______________________________________ 
INPUTS: ESDA4, VUPB 
OUTPUTS: B.sub.-- OVDETECT 
# OF CIRCUITS: 1/chip 
LOCATION: right corner 
______________________________________ 
BOVBIAS is the overvoltage detector. Node OV will be charged up if there is 
an overvoltage condition on ESDA4 after VUPB goes low. This will set 
B.sub.-- OVDETECT to high. A voltage higher than 5.2V on ESDA4 is 
sufficient for an overvoltage to be detected. 
10.3 BIROSC (FIG. 34) 
______________________________________ 
INPUTS: PB.sub.-- CLKBIST,BIST.sub.-- EN,MD.sub.-- SLFR,B.sub.-- 
CLKMUX 
OUTPUTS: B.sub.-- IRCLK,BCLK.sub.-- EN,B.sub.-- CLK 
# OF CIRCUITS: 
1/chip 
LOCATION: right corner of chip 
______________________________________ 
The BIROSC is the primary oscillator that generates the clock signal for 
all BIST operation. It is a dual mode oscillator circuit. In BIST mode 
(when BIST.sub.-- EN is high). It operates in the high frequency mode and 
provides B.sub.-- CLK to the BIST circuit to synchronously control BIST 
operation. In normal mode (when BIST.sub.-- EN) is low, it operates at the 
low frequency mode and produce a low frequency B.sub.-- IRCLK used for 
self refresh mode. It is also a low frequency clock for the VBB circuits 
(FIG. 66). 
This circuit is also used to control internal and external clock for BIST 
operation. 
If the device power up in BIST mode and the internal clock option is 
selected, B.sub.-- CLKMUX will be set to low. This will set BCLK.sub.-- EN 
to high to take over control of the CLK signals going into the device. The 
oscillator will generate 20 ns clock needed for BIST operation. Externally 
CLK needs to be pulled low. If B.sub.-- CLKMUX is high, external clock 
option is chosen, PB.sub.-- CLKBIST will be used as the clock for BIST. 
Nodes BNN and IRNN are used to compensate for process variation to ensure a 
more constant oscillator frequency. 
10.4 BIRBIT (FIG. 33) 
______________________________________ 
INPUTS: CLK 
OUTPUTS: Q 
# OF CIRCUITS: 6/chip 
LOCATION: right corner of chip 
______________________________________ 
This circuit is used to divide the CLK frequency by half Q has half the 
frequency of CLK. 
10.5 BSLFRCLK 
______________________________________ 
INPUTS: B.sub.-- IRCLK,VUPB 
OUTPUTS: SLFR.sub.-- TIME 
# OF CIRCUITS: 1/chip 
LOCATION: right corner of chip 
______________________________________ 
SLFR.sub.-- TIME is the clock used for self refresh and also in VBB pump. 
It oscillates with a period of about 8 US. 
10.9 BTIMEDRV 
______________________________________ 
INPUTS: B.sub.-- PCOUNTER(0) 
OUTPUTS: B.sub.-- PCOUNTERD(9:0),B.sub.-- PCOUNTERDB(9:0) 
# OF CIRCUITS: 
1/chip 
LOCATION: right corner of chip 
______________________________________ 
Generate true and bar signals from the primary counter in the BIST circuit. 
The true and bar signals goes into the B.sub.-- TGEN (FIG. 47) circuit to 
generate the timing sets. 
10.10 BRM (FIG. 27) 
______________________________________ 
INPUTS: B.sub.-- ROM.sub.-- ADDR(63:0) 
OUTPUTS: B.sub.-- WORD(11:0) 
# OF CIRCUITS: 1/chip 
LOCATION: right corner of chip 
______________________________________ 
The BRM has 64 ROM words and each word is 12 bit wide. The decoder in BIST 
circuit decides which ROM word is to be read. 
10.10.1 Gross (Zrom) Algorithm 
1. Write array with selected pattern. 
2. Read array to confirm selected pattern was written. 
Note: 
a) Selected pattern is an all 0's pattern, an all 1's pattern or any 
combination of 0's and 1's. 
10.10.2 Pause Algorithm 
1. Write array with selected pattern. 
2. Wait for specified time to elapse. 
3. Read array to confirm selected pattern written is retained. 
Note: 
a) Selected pattern is an all 0's pattern, an all 1's pattern and/or any 
combination of 0's and 1's. 
10.10.3 Xmarch Algorithm 
1. Write array with background pattern. 
2. For each row read the background pattern and write the inverted pattern 
into each column. 
3. For each row read the inverted pattern and write the original pattern 
into each column. 
4. Read original background pattern to confirm no defect has occurred. 
Notes: 
a) Background pattern is an all 0's pattern, an all 1's pattern or 
combination of 0's and 1's. 
10.10.4 Ymarch Algorithm 
1. Write array with background pattern. 
2. For each column read the background pattern and write the inverted 
pattern into each row. 
3. For each column read the inverted pattern and write the original pattern 
into each row. 
4. Read original background pattern to confirm no defect has occurred. 
Notes: 
a) Background pattern is an all 0's pattern, an all 1's pattern or 
combination of 0's and 1's. 
10.10.5 Sdist Algorithm 
1. Write array with background pattern (optional) 
2. Write target row with disturb pattern repeatedly until specified time 
has elapsed. 
3. Refresh 
4. Read neighboring rows to target row to confirm no disturb type error 
defect has occurred. 
5. Return background pattern to target row. 
6. Repeat by targeting all rows in the chip. 
Notes: 
a) Disturb pattern is an all 1's pattern, an all 0's pattern or any 
combination of 1's and 0's. 
b) Background pattern is an all 0's pattern, an all 1's pattern or 
combination of 0's and 1's. 
c) Steps 4 and 5 can be interchanged. 
10.10.6 Ldist Algorithm 
Algorithm steps are the same as for Sdist Algorithm. The Ldist algorithm 
utilizes a different time set to lengthen the time between a RASB and CASB 
pulses. 
10.10.7 Pdist Algorithm 
Algorithm steps are the same as for Sdist Algorithm. The Pdist algorithm 
writes the disturb pattern in a page mode. In the page mode the row 
remains activated until all columns are written into the row. 
10.10.8 Burnin Algorithm 
1. Continually write array with selected pattern. 
Note: 
a) Selected pattern is an all 0's pattern, an all 1's pattern or any 
combination of 0's and 1's. 
10.10.9 Write 1 Rom Algorithm 
1. Write one row in the array with selected pattern. 
Note: 
a) Selected pattern is an all 0's pattern, an all 1's pattern or any 
combination of 0's and 1's. 
10.10.10 Read 1 Column Algorithm 
1. Read one column in the array. 
Note: 
a) Selected pattern is an all 0's pattern, an all 1's pattern or any 
combination of 0's and 1's. 
10.10.11 Finish Algorithm Set the DONE flag to true and deactivate the 
program counter. 
10.11 to 10.18 BRM0.sub.-- 7 to BRM56.sub.-- 63 
______________________________________ 
INPUTS: B.sub.-- ROM.sub.-- ADDRx where x ranges from 0 to 63 
OUTPUTS: B.sub.-- WORD0 to B.sub.-- WORD11 
# OF CIRCUITS: 
1/chip 
LOCATION: right corner of chip 
______________________________________ 
The BIST ROM circuits is divided into 8 individual circuits with each 
circuit having 8 words. 
10.19 BROMDRV (FIG. 53) 
______________________________________ 
INPUTS: B.sub.-- WORD,B.sub.-- PRECHARGE,B.sub.-- ROM.sub.-- WORD 
OUTPUTS: B.sub.-- WORD0..B.sub.-- WORD11 
# OF CIRCUITS: 
1/chip 
LOCATION: right corner of chip 
______________________________________ 
BROMDRV is a driver circuit for the 12 bits of a ROM word. The 12 bits of 
data line is precharged once every 2 clock cycle during BIST operation 
when the device is not in the array access mode (FIG. 68). 
10.20 BIST (FIGS. 51, 52) 
__________________________________________________________________________ 
INPUTS: BIST.sub.-- EN,B.sub.-- EEPRMOPT,TLBADDRNG,PB.sub.-- CLKBIST,B.sub 
.-- SR.sub.-- LOAD, 
B.sub.-- YSTOPE,B.sub.-- XSTOPE,B.sub.-- YSTARTE,B.sub.-- 
XSTARTE,VUPB,TLBMON3 
TLBMON2,TLBMON1,TLBROMR,B.sub.-- ROM.sub.-- WORD 
B.sub.-- RASA1,B.sub.-- RASB1,B.sub.-- RASC1,B.sub.-- RASA2,B.sub. 
-- RASB2,B.sub.-- RASC2, 
B.sub.-- CASA1,B.sub.-- CASB1,B.sub.-- CASC1,B.sub.-- CASA2,B.sub. 
-- CASB2,B.sub.-- CASC2, 
B.sub.-- OEA1,B.sub.-- OEB1,B.sub.-- OEC1,B.sub.-- OEA2,B.sub.-- 
OEB2,B.sub.-- OEC2, 
B.sub.-- DMUXA1,B.sub.-- DMUXB1,B.sub.-- DMUXC1,B.sub.-- DMUXA1,B. 
sub.-- DMUXB1,B.sub.-- DMUXC1, 
B.sub.-- YMUXA1,B.sub.-- YMUXB1,B.sub.-- YMUXC1,B.sub.-- YMUXA1,B. 
sub.-- YMUXB1,B.sub.-- YMUXC1 
B.sub.-- FIXCOUNTA,B.sub.-- FIXCOUNTB,B.sub.-- FIXCOUNTC 
B.sub.-- PERIODA1,B.sub.-- PERIODB1,B.sub.-- PERIODC1, 
OUTPUTS: 
B.sub.-- DONE,B.sub.-- OUTPUTEN,B.sub.-- CLKMUX,B.sub.-- ROM.sub.- 
- PRECHARGE, 
B.sub.-- DQL(23:18),B.sub.-- RASB,B.sub.-- CASB,B.sub.-- WDATA.sub 
.-- TIMB,B.sub.-- WB, 
B.sub.-- PCOUNTER,B.sub.-- ADDR,B.sub.-- PF.sub.-- RESULTS,B.sub.- 
- ROM.sub.-- ADDR,B.sub.-- DQ 
# OF CIRCUITS: 
1/chip 
LOCATION: 
right corner of chip 
__________________________________________________________________________ 
All circuits in this block is synthesized using Autologic2 after coding in 
VHDL code. It has 8 major blocks: 
1. B.sub.-- CLK.sub.-- GEN (FIG. 22): Generates auxiliary clocks of 
different phases. Also generates the precharge signal for the ROM 
2. B.sub.-- ADDRCTL (FIGS. 8-12): Generates and control the addresses of 
the cells to be accessed 
3. B.sub.-- CROM (FIG. 40): Stores the test conditions in the ROM, holds 
the program counter and decoder 
4. B.sub.-- PG.sub.-- CONTROL (FIG. 24): Controls the flow of test program. 
5. B.sub.-- PASSFAIL: Generates the data pattern to be written to array, 
perform pass fail comparison. 
6. B.sub.-- DQMUX : Control the multiplexing for BIST signals to appear at 
the DQs. 
7. B.sub.-- ADDRNG (FIGS. 16-21): Control the start and stop address of 
BIST operation. 
8. B.sub.-- TGEN (FIGS. 47-50): Control and generates the timing of all the 
Control, Data, and address signals. 
10.21 B.sub.-- CLK.sub.-- GEN 
__________________________________________________________________________ 
INPUTS: B.sub.-- CLK,VUPB,B.sub.-- SR.sub.-- LOAD,B.sub.-- DONE,B.sub.-- 
ROM.sub.-- PRE.sub.-- EN, 
OUTPUTS: 
B.sub.-- CLK.sub.-- B,B.sub.-- RESET,B.sub.-- CLK.sub.-- C,B.sub.- 
- CLK.sub.-- A,B.sub.-- ROM.sub.-- PRECHARGE, 
B.sub.-- CLK.sub.-- AD 
# OF CIRCUITS: 
1/chip 
LOCATION: 
right corner of chip 
__________________________________________________________________________ 
This circuit takes the bist primary clock B.sub.-- CLK and makes 4 other 
clocks out of it in 2 clock cycles. Rising edge of B.sub.-- CLK.sub.-- A 
updates the newest instruction pointed to by the Program counter. Decoding 
of the newest instruction starts at this edge. Rising edge of B.sub.-- 
CLK.sub.-- AD is the clock that executes the newly decoded instruction. At 
the rising edge of B.sub.-- CLK.sub.-- B, a decision is made on the action 
to take with the program counter. B.sub.-- CLK.sub.-- C acts as a reset 
signal. 
It also generates the precharge signal for the ROM (FIG. 69). 
10.22 B.sub.-- CROM (FIG. 40) 
__________________________________________________________________________ 
INPUTS: B.sub.-- CLK.sub.-- A,B.sub.-- CLK.sub.-- C,B.sub.-- ROM.sub.-- 
WORD,TLBROMR,B.sub.-- RESET, 
B.sub.-- INS.sub.-- COMPLETED,B.sub.-- PC.sub.-- LOAD,B.sub.-- 
CLK.sub.-- B,B.sub.-- PC.sub.-- LO.sub.-- ADDR, 
B.sub.-- RPTINV.sub.-- STATE 
OUTPUTS: 
B.sub.-- RPT.sub.-- N.sub.-- INV,B.sub.-- YEN,B.sub.-- DONE,B.sub. 
-- DECR,B.sub.-- ALTERNATE,B.sub.-- INC, 
B.sub.-- XEN,B.sub.-- TIME.sub.-- SET1,B.sub.-- XEN,B.sub.-- 
TIME.sub.-- SET0,B.sub.-- CKBD,B.sub.-- CHK.sub.-- KEY, 
B.sub.-- REN,B.sub.-- READ,B.sub.-- PAUSE,B.sub.-- JUMP,B.sub.-- 
CHK.sub.-- TIMEOUT,B.sub.-- WRITE, 
B.sub.-- JMP.sub.-- ADDR,B.sub.-- ROM.sub.-- ADDR,B.sub.-- 
RDATA,B.sub.-- WDATA 
# OF CIRCUITS: 
1/chip 
LOCATION: 
right corner of chip 
__________________________________________________________________________ 
B.sub.-- CROM controls the operations of the ROM. It is made up of a 
decoder, a program counter and B.sub.-- ROMLOGIC (FIG. 30) which decodes 
what the current instruction. The program counter points to word 0 during 
power up. Subsequently in BIST operation, PC will point to the relevant 
word in the ROM to execute the desired instruction. The decoder decodes 
the 6 bit program counter to point to one of the 64 words in the ROM (FIG. 
70). 
10.23 B.sub.-- DECODER (FIG. 26) 
______________________________________ 
INPUTS: B.sub.-- PC.sub.-- ADDR 
OUTPUTS: B.sub.-- ROM.sub.-- ADDR 
# OF CIRCUITS: 1/chip 
LOCATION: right corner of chip 
______________________________________ 
This is a simple 6 to 64 decoder. 6 bit input address from the program to 
be decoded into 64 words in the ROM 
10.24 B.sub.-- PC (FIG. 25) 
__________________________________________________________________________ 
INPUTS: B.sub.-- PC.sub.-- LOAD,B.sub.-- PC.sub.-- LD.sub.-- ADDR,B.sub.-- 
CLK.sub.-- B,B.sub.-- RESET, 
B.sub.-- INS.sub.-- COMPLETED 
OUTPUTS: 
B.sub.-- PC.sub.-- ADDR, 
# OF CIRCUITS: 
1/chip 
LOCATION: 
right corner of chip 
__________________________________________________________________________ 
The program counter points to an instruction in the ROM to be executed. 
B.sub.-- CLK.sub.-- B is used to change the program counter to its new 
value. 
At the completion of an instruction, program counter can change in 2 ways. 
It can either be incremented by 1 (normal program flow), or it can jump to 
any one of the 64 words of the ROM (conditional or unconditional jump). 
At the rising edge of B.sub.-- CLK.sub.-- B, the circuit will look at two 
signals that comes in: B.sub.-- PC.sub.-- LOAD and B.sub.-- INS.sub.-- 
COMPLETED. 
If B.sub.-- PC.sub.-- LOAD is a high, it will do a jump by loading the PC 
with the address that appears on B.sub.-- PC.sub.-- LD.sub.-- ADDR. If 
B.sub.-- INS.sub.-- COMPLETED is a high, it will increment the PC by 1 and 
proceed to the next instruction. If neither B.sub.-- PC.sub.-- LD.sub.-- 
ADDR nor B.sub.-- INS.sub.-- COMPLETED is high then no action will be 
taken and the PC will remain the same. B.sub.-- PC.sub.-- LOAD and 
B.sub.-- PC.sub.-- LD.sub.-- ADDR cannot be high at the same time (FIG. 
71). 
If one wants to read the content of the ROM and output it to the DQ pins, 
ROM read DFT mode can be used. The device needs to be powered up with 
overvoltage, then perform a DFT entry to TLBROMR while in BIST standby 
mode, then pull CS high to go into BIST mode. 
The external clock is used to move from one ROM word to the next ROM word. 
The PC is incremented every 2 clock cycles, ie on every rising edge of 
B.sub.-- CLK.sub.-- B. This is done by forcing B.sub.-- INS.sub.-- 
COMPLETED to be high all the time during the DFT TLROMR mode. 
10.25 B.sub.-- ROMLOGIC (FIGS. 30, 31) 
__________________________________________________________________________ 
INPUTS: B.sub.-- ROM.sub.-- WORD,TLBROMR,B.sub.-- CLK.sub.-- C,B.sub.-- 
CLK.sub.-- A,B.sub.-- RESET 
OUTPUTS: 
B.sub.-- JMP.sub.-- ADDR,B.sub.-- DONE,B.sub.-- CHK.sub.-- 
TIMEOUT,B.sub.-- RPT.sub.-- N.sub.-- INV, 
B.sub.-- TIMESET1,B.sub.-- TIMESET0,B.sub.-- DECR,B.sub.-- 
XEN,B.sub.-- JUMP,B.sub.-- CHK.sub.-- KEY 
B.sub.-- ALTERNATE,B.sub.-- REN,B.sub.-- WRITE,B.sub.-- PAUSE,B.su 
b.-- READ,B.sub.-- RDATA, 
B.sub.-- WDATA,B.sub.-- CKBD,B.sub.-- INC,B.sub.-- YEN,B.sub.-- 
CLK.sub.-- ARESET 
# OF CIRCUITS: 
1/chip 
LOCATION: 
right corner of chip 
__________________________________________________________________________ 
B.sub.-- ROMLOGIC decodes the 12 bits of data contained in an instruction 
word. There are two major types of instructions. First is the program 
control instruction. This type of instruction deals with the flow of the 
program. They are introduced to control BIST operation. Second is the 
array access instruction and they control how the array is to be tested. 
They are basically the same type of instruction usually found on a tester. 
They are translated into BIST format in this case. 
An instruction is divided into two parts. The first six bits of an 
instruction defines the actions to be taken and the last six bits is the 
data associated with the instruction. 
For an read whole array instruction, Read(bit11),X(bit9) and Y(bit8) are 
set to 1. The last six bits of the instruction provides information on how 
the read whole array is to be achieved, ie timing sets to be used, data 
pattern to be used, etc. 
For a program control instruction, the 4 most significant bits are `0`, Bit 
7 and Bit 6 determines the program control instruction. The last six bits 
provides the address to be jumped to if indeed the decision is made to 
jump. 
There is an unconditional jump instruction. `110011` for the most 
significant 6 bits, and the address to jump to for the 6 least significant 
bits. 
The last instruction in the ROM is an idle instruction to signal the end of 
BIST operation. The last six bits of this instruction holds the revision 
number of the current 256M (FIG. 72). 
The instruction above will perform a read, from the whole array (both X and 
Y enabled), using timing set A, expected data `0`, true internal data 
pattern, and same data among the DQ. 
There are many possible combination of instructions that can be programmed 
with the current circuits. If a new algorithm is need for BIST. It can be 
included by simply reprogramming the ROM. Combinations of options are 
available to make up an instruction (FIG. 73) 
10.26 B.sub.-- TGEN 
__________________________________________________________________________ 
INPUTS: B.sub.-- READ,B.sub.-- RESET,B.sub.-- PAUSE,B.sub.-- YCARRY.sub.-- 
1,B.sub.-- CLK,B.sub.-- WRITE, 
B.sub.-- TIME.sub.-- SET0,B.sub.-- TIME.sub.-- SET1,B.sub.-- 
INS.sub.-- COMPLETED,B.sub.-- REN, 
B.sub.-- OEA1,B.sub.-- OEA2,B,B.sub.-- OEB1,B.sub.-- OEB2,B,B.sub. 
-- OEC1,B.sub.-- OEC2, 
B.sub.-- RASA1,B.sub.-- RASA2,B.sub.-- RASB1,B.sub.-- RASB2,B.sub. 
-- RASC1,B.sub.-- RASC2, 
B.sub.-- CASA1,B.sub.-- CASA2,B.sub.-- CASB1,B.sub.-- CASB2,B.sub. 
-- CASC1,B.sub.-- CASC2, 
B.sub.-- DMUXA1,B.sub.-- DMUXB1,B.sub.-- DMUXC1,B.sub.-- DMUXA1,B. 
sub.-- DMUXB1,B.sub.-- DMUXC1, 
B.sub.-- YMUXA1,B.sub.-- YMUXB1,B.sub.-- YMUXC1,B.sub.-- YMUXA1,B. 
sub.-- YMUXB1,B.sub.-- YMUXC1 
B.sub.-- FIXCOUNTA,B.sub.-- FIXCOUNTB,B.sub.-- FIXCOUNTC 
B.sub.-- PERIODA1,B.sub.-- PERIODB1,B.sub.-- PERIODC1, 
OUTPUTS: 
B.sub.-- YSELB,B.sub.-- RASB,B.sub.-- CASB,B.sub.-- WB,B.sub.-- 
OEB,B.sub.-- PERIODB, 
B.sub.-- ROM.sub.-- PRE.sub.-- EN,B.sub.-- WDATA.sub.-- TIMB,B.sub 
.-- TIMECNT.sub.-- REF,B.sub.-- PCOUNTER 
# OF CIRCUITS: 
1/chip 
LOCATION: 
right corner of chip 
__________________________________________________________________________ 
The timing sets used in BIST tests are generated through the use of the 
primary clock generated in BIROSC (FIG. 34) block. The clock is a 50 MHz 
clock and the resolution of the timing sets is 20 ns. A counter counts the 
number of rising edges of the primary clock. The control timing is set by 
specifying a specific count of the counter. In the example below, Activate 
is specified at count 2 and Deactivate is specified at count 12 (FIG. 74). 
Altogether 3 types of timing sets, namely short, long and page timing set 
were used in the 10 algorithms implemented in BIST (FIG. 75). 
10.27 B.sub.-- COUNTER10B (FIG. 39) 
______________________________________ 
INPUTS: B.sub.-- CNTR10.sub.-- CLK,B.sub.-- CNTR10.sub.-- CLR 
OUTPUTS: B.sub.-- CNTR10 
# OF CIRCUITS: 
1/chip 
LOCATION: right corner of chip 
______________________________________ 
Rising edge of B.sub.-- CNTR10.sub.-- CLK will increment the counter by 1. 
The counter is always enabled. 
10.28 B.sub.-- COUNTER10A (FIG. 38) 
__________________________________________________________________________ 
INPUTS: B.sub.-- CNTR10.sub.-- CLK,B.sub.-- CNTR10.sub.-- EN,B.sub.-- 
CNTR10.sub.-- CLR 
OUTPUTS: 
B.sub.-- CNTR10 
# OF CIRCUITS: 
1/chip 
LOCATION: 
right corner of chip 
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If B.sub.-- CNTR10.sub.-- EN is high, rising edge of B.sub.-- CNTR10.sub.-- 
CLK will increment the counter by 1 
10.29 B.sub.-- ADDRCTL 
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INPUTS: B.sub.-- PAUSE,B.sub.-- PERIODB,B.sub.-- RESET,B.sub.-- CLK.sub.-- 
AD,B.sub.-- YEN,B.sub.-- XEN, 
B.sub.-- REN,B.sub.-- INC,B.sub.-- YSELB,BIST.sub.-- EN,B.sub.-- 
DECR,B.sub.-- SUBARRAY, 
B.sub.-- XADDR.sub.-- STP,B.sub.-- YADDR.sub.-- STP,B.sub.-- 
XADDR.sub.-- STR,B.sub.-- YADDR.sub.-- STR 
OUTPUTS: 
B.sub.-- YCLR,B.sub.-- XCLR,B.sub.-- RCARRY,B.sub.-- YCARRY,B.sub. 
-- XCARRY, 
B.sub.-- YNOCARRYJ,B.sub.-- YCARRY.sub.-- 1,B.sub.-- XNOCARRY,B.su 
b.-- LSB.sub.-- YADDR, 
B.sub.-- LSB.sub.-- XADDR,B.sub.-- ADDR 
# OF CIRCUITS: 
1/chip 
LOCATION: 
right corner of chip 
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B.sub.-- ADDRCTL has two blocks, B.sub.-- ADDR.sub.-- CTR which contains 
all the address counters and B.sub.-- RESET.sub.-- EN which provide 
controls to detect overflows of address counters. 
10.30 B.sub.-- ADDR.sub.-- CTR 
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INPUTS: B.sub.-- SUBARRAY,B.sub.-- INC,B.sub.-- DECR,B.sub.-- ADDRCLK,B.su 
b.-- XCLR,B.sub.-- YCLR, 
B.sub.-- RCLR,B.sub.-- XEN,B.sub.-- YEN,B.sub.-- REN,B.sub.-- 
YSELB,BIST.sub.-- EN, 
B.sub.-- XADDR.sub.-- STP,B.sub.-- YADDR.sub.-- STP,B.sub.-- 
XADDR.sub.-- STR,B.sub.-- YADDR.sub.-- STR 
OUTPUTS: 
B.sub.-- RCARRY,B.sub.-- YCARRY,B.sub.-- XCARRY, 
B.sub.-- YNOCARRYJ,B.sub.-- YCARRY.sub.-- 1,B.sub.-- XNOCARRY,B.su 
b.-- LSB.sub.-- YADDR, 
B.sub.-- LSB.sub.-- XADDR,B.sub.-- ADDR 
# OF CIRCUITS: 
1/chip 
LOCATION: 
right corner of chip 
__________________________________________________________________________ 
B.sub.-- ADDR.sub.-- CTR has 3 counters, the row counter, the column 
counter and the refresh counter. A multiplexer decides which counter value 
is used as the B.sub.-- ADDR signal during BIST operation. In normal 
access, only the X counter and Y counter are used. B.sub.-- YSELB is the 
signal used to choose between the column and row address (FIG. 76). During 
refresh, only the Refresh counter is used. 
The addressing mux sequence and controlled by a combination of B.sub.-- 
ADDRCLK, B.sub.-- INC and B.sub.-- YSELB. B.sub.-- PERIODB pulse generates 
B.sub.-- ADDRCLK which increment the address counter by 1. 
Low on B.sub.-- YSELB indicates selection of column address. High on 
B.sub.-- YSELB indicates selection of row address. B.sub.-- INC will 
increment the enabled address counter by 1 (FIG. 77). 
10.31 B.sub.-- ROW.sub.-- CTR (FIGS. 46, 55) 
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INPUTS: B.sub.-- INC,B.sub.-- DECR,B.sub.-- ADDRCLK,B.sub.-- XCLR,B.sub.-- 
XEN,B.sub.-- XSTART,B.sub.-- XSTOP 
OUTPUTS: 
B.sub.-- CARY,B.sub.-- XCARRY,B.sub.-- XNOCARRYJ,B.sub.-- XADDR 
# OF CIRCUITS: 
1/chip 
LOCATION: 
right corner of chip 
__________________________________________________________________________ 
The X counter is a 14 bit counter and it holds the current row address. It 
can count forward and backward, depending the state of B.sub.-- DECR. A 
low on B.sub.-- DECR means counting forward, ie increment the counter 
value by 1 with every rising edge of the B.sub.-- ADDRCLK. The counter is 
enabled by B.sub.-- XEN. 
If the subarray option is chosen. The counter will be start with the start 
address loaded in earlier. An overflow will be issued once the stop 
address is reached. 
10.32 B.sub.-- COL.sub.-- CTR (FIG. 37) 
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INPUTS: B.sub.-- INC,B.sub.-- DECR,B.sub.-- ADDRCLK,B.sub.-- YCLR,B.sub.-- 
YEN,B.sub.-- YSTART,B.sub.-- YSTOP 
OUTPUTS: 
B.sub.-- CARY,B.sub.-- YCARRY,B.sub.-- YNOCARRYJ,B.sub.-- YADDR 
# OF CIRCUITS: 
1/chip 
LOCATION: 
right corner of chip 
__________________________________________________________________________ 
The Y counter is a 9 bit counter and it holds the current column address. 
It can count forward and backward, depending the state of B.sub.-- DECR. A 
low on B.sub.-- DECR means counting forward, ie increment the counter 
value by 1 with every rising edge of the B.sub.-- ADDRCLK. The counter is 
enabled by B.sub.-- YEN. 
If the subarray option is chosen. The counter will be start with the start 
address loaded in earlier. An overflow will be issued once the stop 
address is reached. 
10.33 B.sub.-- REF.sub.-- CTR (FIG. 45) 
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INPUTS: B.sub.-- ADDRCLK,B.sub.-- RCLR,B.sub.-- REN,B.sub.-- XSTART,B.sub. 
-- XSTOP, 
OUTPUTS: 
B.sub.-- RCARRY,B.sub.-- RADDR 
# OF CIRCUITS: 
1/chip 
LOCATION: 
right corner of chip 
__________________________________________________________________________ 
The refresh counter is a 14 bit counter. It only counts forward. The 
counter value is incremented by 1 with every rising edge of the B.sub.-- 
ADDRCLK if B.sub.-- REN is high. The refresh counter is used in the three 
disturb tests only. During the refresh instruction, a pseudo read is done 
for all the rows that are enabled. This refreshes the array but no 
pass/fail comparison is done. 
10.34 B.sub.-- ADDR.sub.-- RESET.sub.-- EN (FIGS. 35, 36, 54) 
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INPUTS: B.sub.-- INC,B.sub.-- PERIODB,B.sub.-- XEN,B.sub.-- YEN,B.sub.-- 
REN,B.sub.-- RCLR,B.sub.-- REN, 
B.sub.-- X2YLINK 
B.sub.-- RESET,B.sub.-- CLK.sub.-- C,B.sub.-- CLK.sub.-- AD,B.sub. 
-- XCARRY,B.sub.-- YCARRY, 
B.sub.-- RCARRY,B.sub.-- PAUSE 
OUTPUTS: 
B.sub.-- ADDRCLK,B.sub.-- YENABLE,B.sub.-- XRESET,B.sub.-- 
YRESET,B.sub.-- RRESET 
# OF CIRCUITS: 
1/chip 
LOCATION: 
right corner of chip 
__________________________________________________________________________ 
This circuit generates the clock (B.sub.-- ADDRCLK) used to increment or 
decrement the address counters. B.sub.-- ADDRCLK is generated in 2 ways 
namely during an INC instruction or during the end of an array-access 
cycle. The reset signals (XCLR, YCLR and RCLR) are generated at the rising 
edge of B.sub.-- CLK.sub.-- C. These reset the counters to its original 
state when overflows occur. 
B.sub.-- X2YLINK is used to join the X and Y register together for whole 
array tests. The CARRY signal is used to signal the completion of an array 
access instruction. It is sent to the program counter to tell it to move 
on to the next instruction. 
10.35 B.sub.-- PG.sub.-- CONTROL 
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INPUTS: VUPB,B.sub.-- RESET,BIST.sub.-- EN,B.sub.-- DONE,B.sub.-- 
TIMEOUT.sub.-- CHK,B.sub.-- INC, 
B.sub.-- XEN,B.sub.-- XCARRY,B.sub.-- XNOCARRYJ,B.sub.-- XCLR,B.su 
b.-- YEN,B.sub.-- YCARRY, 
B.sub.-- YNOCARRYJ,B.sub.-- YCLR,B.sub.-- REN,B.sub.-- RCARRY,B.su 
b.-- CHK.sub.-- KEY, 
B.sub.-- RPT.sub.-- N.sub.-- INV,B.sub.-- JUMP,B.sub.-- TIMECNT.su 
b.-- REF,B.sub.-- ADDRU,B.sub.-- ADDRL, 
B.sub.-- CLK.sub.-- C,B.sub.-- CLK.sub.-- A,B.sub.-- SR.sub.-- 
LOAD 
OUTPUTS: 
B.sub.-- INS.sub.-- COMPLETED,B.sub.-- PC.sub.-- LOAD,B.sub.-- 
RPTINV.sub.-- STATE,B.sub.-- SUBARRAY 
B.sub.-- CLKMUX,B.sub.-- OUTPUTEN 
# OF CIRCUITS: 
1/chip 
LOCATION: 
right corner of chip 
__________________________________________________________________________ 
This block contains the circuit used for controlling the Program counter. 
It also contain a shift register which holds information on which test to 
perform. 
Upon completion of an instruction, this block will make a decision on 
whether to increment the program counter or to load the program counter 
with a new address. 
10.36 B.sub.-- SHIFT (FIG. 7) 
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INPUTS: VUPB,BIST.sub.-- EN,B.sub.-- DONE,B.sub.-- SR.sub.-- CLK,B.sub.-- 
SR.sub.-- LOAD,B.sub.-- ADDRU, 
B.sub.-- ADDRL 
OUTPUTS: 
B.sub.-- LSB.sub.-- SR,B.sub.-- SUBARRAY,B.sub.-- CLKMUX,B.sub.-- 
OUTPUTEN 
# OF CIRCUITS: 
1/chip 
LOCATION: 
right corner of chip 
__________________________________________________________________________ 
B.sub.-- SHIFT register holds the data latched in during power up. Every 
time the test.sub.-- en instruction is executed once, the shift register 
is shifted right by 1 position. This instruction looks at the last bit to 
see if the test is enabled (FIG. 78). 
10.37 B.sub.-- ECOME10 (FIG. 43) 
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INPUTS: B.sub.-- ECMPR10.sub.-- EN,B.sub.-- AIN9.sub.-- 0,B.sub.-- 
BIN9.sub.-- 0 
OUTPUTS: B.sub.-- ECMPR10.sub.-- RSLT,B.sub.-- ECMPR10.sub.-- RSLTB 
# OF CIRCUITS: 
1/chip 
LOCATION: right corner of chip 
______________________________________ 
This is a simple comparator. If the comparison enable signal is high, then 
B.sub.-- ECMPR10.sub.-- RSLT will be high and the bar signal will be low 
if the 2 10 bit inputs are equal. Alternatively, if the 2 inputs are not 
equal, B.sub.-- ECMPR10.sub.-- RSLT will be low. If the comparison is not 
enabled, then both outputs will be low regardless of the inputs. 
10.38 B.sub.-- PASSFAIL (FIGS. 33, 44) 
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INPUTS: B.sub.-- RESET,B.sub.-- CLK,B.sub.-- RDATA,B.sub.-- WDATA,B.sub.-- 
OEB,B.sub.-- ALTERNATE, 
B.sub.-- CKBD,B.sub.-- WRITE,B.sub.-- LSB.sub.-- XADDR,B.sub.-- 
LSB.sub.-- YADDR,B.sub.-- DQ 
OUTPUTS: 
B.sub.-- WEVNVAL,B.sub.-- WODDVAL,B.sub.-- PF.sub.-- RESULT,B.sub. 
-- DODD,B.sub.-- DEVEN 
# OF CIRCUITS: 
1/chip 
LOCATION: 
right corner of chip 
__________________________________________________________________________ 
This circuit generates internal data pattern to be written to the array. It 
also generates the expected data for pass fail comparison. The timing for 
comparison is controlled by B.sub.-- OEB timing. 
10.39 B.sub.-- DQMUX (FIGS. 41, 42) 
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INPUTS: TLBROMR,TLBMON1,TLBMON2,TLBMON3,B.sub.-- WRITE, 
B.sub.-- WDATA.sub.-- TIMB,B.sub.-- ROM.sub.-- WORD,B.sub.-- 
WEVNVAL,B.sub.-- WODDVAL, 
B.sub.-- RASB,B.sub.-- CASB,B.sub.-- WB,B.sub.-- CLK,B.sub.-- 
DODD,B.sub.-- DEVEN,B.sub.-- OEB, 
B.sub.-- ADDR 
OUTPUTS: 
B.sub.-- DQ,B.sub.-- DQL 
# OF CIRCUITS: 
1/chip 
LOCATION: 
right corner of chip 
__________________________________________________________________________ 
This circuits is a huge multiplexer to multiplex the different signals that 
goes out to the outside world. In the normal mode, only the pass fail 
signals goes to the outside. In the other three monitor modes, different 
control signals are brought to the outside (FIG. 79). 
10.40 B.sub.-- ADDRNG 
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INPUTS: B.sub.-- EEPRMOPT,PB.sub.-- CLKBIST,TLBADDRNG,B.sub.-- ADDR,B.sub. 
-- XSTARTE, 
B.sub.-- XSTOPE,B.sub.-- YSTARTE,B.sub.-- XSTOPE, 
OUTPUTS: 
B.sub.-- XADDR.sub.-- STR,B.sub.-- XADDR.sub.-- STP,B.sub.-- 
YADDR.sub.-- STR,B.sub.-- YADDR.sub.-- STP 
# OF CIRCUITS: 
1/chip 
LOCATION: 
right corner of chip 
__________________________________________________________________________ 
This circuit is used to load start and stop address for sub array BIST 
testing. A DFT mode is used to get into this situation. When this DFT mode 
is entered, the next 4 rising edges of the clock will load in the X and Y 
start and stop address (FIG. 80) . 
10.41 BONEXX 
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INPUTS: IN 
OUTPUTS: OUT 
# OF CIRCUITS: 1/chip 
LOCATION: right corner of chip 
______________________________________ 
This is the `1` bit of the ROM and BONExx represents a high. IN is 
connected to the `wordlines` (B.sub.-- ROM.sub.-- ADDR(x)). OUT is always 
precharged to high and does not get pulled to low whether IN is high or 
not (FIG. 81). 
10.42 BZEROXX 
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INPUTS: IN 
OUTPUTS: OUT 
# OF CIRCUITS: 1/chip 
LOCATION: right corner of chip 
______________________________________ 
This is 0 bit of the ROM and BZEROxx represents a low. IN is connected to 
the `wordlines` (B.sub.-- ROM.sub.-- ADDR(X)). OUT (B.sub.-- WORD(Y)) is 
precharged to high but if this cell is selected and IN goes high, OUT will 
be pulled to low (FIG. 82) 
The foregoing describes the arrangement and operation of an exemplary 
integrated circuit memory device having built-in self-test circuitry. The 
described arrangement and method of and other arrangements made obvious in 
view there of are considered to be within the scope of the appended 
claims.