Semiconductor device and manufacturing method thereof

A semiconductor device includes channel region, first and second two-dimensional metallic contacts, a gate structure, and first and second metal contacts. The channel region includes a two-dimensional semiconductor material. The first two-dimensional metallic contact is disposed at a side of the channel region and includes a two-dimensional metallic material. The second two-dimensional metallic contact is disposed at an opposite side of the channel region and includes the two-dimensional metallic material. The gate structure is disposed on the channel region in between the first and second two-dimensional metallic contacts. The first metal contact is disposed at an opposite side of the first two-dimensional metallic contact with respect to the channel region. The second metal contact is disposed at an opposite side of the second two-dimensional metallic contact with respect to the channel region. The first and second two-dimensional metallic contacts contact sideways the channel region to form lateral semiconductor-metallic junctions.

BACKGROUND

DETAILED DESCRIPTION

FIG.1AtoFIG.1Kare schematic perspective views illustrating structures produced during a manufacturing process of a semiconductor device D10according to some embodiments of the disclosure.FIG.2AtoFIG.2Kare schematic cross-sectional views of the structures respectively illustrated inFIG.1AtoFIG.1K, taken in the XZ plane at the level height of the line I-I′ along the Y direction. The directions X, Y, Z form a set of orthogonal Cartesian coordinates. Referring toFIG.1AandFIG.2A, a substrate100is provided. In some embodiments, the manufacturing process illustrated inFIG.1AtoFIG.1Kmay be a front-end-of-line (FEOL) process, and the substrate100may be a semiconductor substrate, a semiconductor-on-insulator substrate, or the like. For example, the substrate100may include one or more semiconductor materials, which may be elemental semiconductor materials, compound semiconductor materials, or semiconductor alloys. For instance, the elemental semiconductor may include Si or Ge. The compound semiconductor materials and the semiconductor alloys may respectively include SiGe, SiC, SiGeC, a III-V semiconductor, a II-VI semiconductor, or semiconductor oxide materials. The semiconductor oxide materials may be one or more of ternary or higher (e.g., quaternary and so on) semiconductor oxides, such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), or indium tin oxide (ITO). In some embodiments, the substrate100may be a semiconductor-on-insulator, including at least one layer of dielectric material (e.g., an oxide layer) disposed between a pair of semiconductor layers (e.g., silicon layers). The substrate100may include doped regions depending on circuit requirements (e.g., p-type semiconductor substrate or n-type semiconductor substrate). In some embodiments, the doped regions may be doped with p-type or n-type dopants. In some alternative embodiments, the manufacturing process illustrated inFIG.1AtoFIG.1Kmay be a back-end-of-line (BEOL) process, and the substrate100may be, for example, an interlayer dielectric layer formed on conductive patterns and other interlayer dielectric layers of an interconnection structure (not shown), where the interconnection structure is formed on a semiconductor substrate (not shown) including front-end-of-line devices. In such embodiments, the substrate100may include low-k dielectric materials, such as Xerogel, Aerogel, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), flare, hydrogen silsesquioxane (HSQ), fluorinated silicon oxide (SiOF), a combination thereof, or the like.

In some embodiments, a sheet102of two-dimensional semiconductor material is formed on the substrate100. In some embodiments, the sheet102is a monolayer of the two-dimensional semiconductor material. In some embodiments, the sheet102includes one or more monolayers of the two-dimensional semiconductor material stacked on each other along the Z direction. The number of stacked monolayers is not particularly limited, as long as the two-dimensional semiconductor material retains semiconducting properties. In some embodiments, the two-dimensional semiconductor material may include a single type of atoms, or may include different types of atoms. For example, the two-dimensional semiconductor material may be graphene, phosphorene, transition metal chalcogenides (e.g., InSe), transition metal dichalcogenides (e.g., MX2, where M is, for example, Mo, W, Zr, Hf, Sn, V, Pt, or Pd, and X is S, Se, or Te), or the like. Examples of transition metal dichalcogenides include MoS2, MoSe2, MoTe2, WS2, WSe2, WTe2, ZrS2, ZrSe2, HfS2, HfSe2, SnS2, SnSe2, VSe2, VTe2, PtSe2, PtTe2, and PdSe2. In some embodiments, dopants or other defects may be implanted or produced to tune the semiconductor properties of the two-dimensional semiconductor material. In some embodiments, the two-dimensional semiconductor material may be fabricated or provided through any suitable process. For example, the two-dimensional semiconductor material may be grown by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) molecular beam epitaxy (MBE), chemical vapor transport (CVT) or the like. In some embodiments, the deposition temperature may be in the range from 300 to 800° C., and the deposition pressure may be in the range from 1 to 800 torr. In some embodiments, the two-dimensional semiconductor material may be obtained by exfoliation of bulk material, and one or more monolayers may be transferred on the substrate100, for example via sacrificial tapes or supports including polymeric and/or metallic materials. In some alternative embodiments, the monolayer may be produced in situ, for example by reacting a transition metal film disposed on the substrate100with a chalcogen.

Referring toFIG.1BandFIG.2B, in some embodiments, a mask layer104is blanketly formed on the sheet102. In some embodiments, the mask layer104includes an oxide, such as silicon oxide, aluminum oxide, or the like. In some alternative embodiments, the mask layer104includes a nitride, such as silicon nitride, silicon oxynitride, or the like. In some embodiments, the thickness T104of the mask layer104along the Z direction may be selected as a function of the desired thickness of the subsequently formed two-dimensional metallic contacts. In some embodiments, the thickness T104may be in the range from 40 to 60 nm. In some embodiments, the mask layer104is formed through suitable deposition processes, such as plasma-enhanced CVD, PVD, ALD, or the like. In some embodiments, the mask layer104is patterned to form a plurality of mask strips106,108,110, as illustrated, for example, inFIG.1CandFIG.2C. In some embodiments, patterning of the mask layer104may include a lithography process to form a patterned resist mask (not shown) on top of the mask layer104. The pattern of the resist mask may then be transferred to the mask layer104, for example via an etching step. In some embodiments, the etching step is a wet etching step, such as a buffered oxide etching step, in which an etchant such as hydrofluoric acid and a buffering agent, such as ammonium fluoride are employed, optionally in a mixture with other controlling agents. In some embodiments, the mask strips106,108,110run substantially parallel to each other, extending, for example, along the Y direction. Contact trenches112,114extending along the Y direction may separate the mask strips106,108,110from each other along the X direction. For example, the mask strip108may be separated from the mask strip106by the contact trench112on one side, and from the mask strip110by the contact trench114at an opposite side along the X direction. In some embodiments, the contact trenches112,114may independently have widths W112, W114along the X direction in the range from 100 nm to 10 μm. In some embodiments, the widths W112, W114need not be constant proceeding along the Y direction. For example, the contact trenches112,114may present narrower regions and wider regions connected to the narrower regions.

In some embodiments, portions of the sheet102are exposed at the bottom of the contact trenches112,114, while the remaining parts of the sheet102are buried under the mask strips106,108,110. In some embodiments, the exposed portions of the sheet102may be removed, for example via an etching step employing plasma including oxygen or hexafluorosulfide. As illustrated inFIG.1DandFIG.2D, upon removal of the exposed portions of the sheet102, the substrate100may be exposed at the bottom of the contact trenches112,114, and strips116,118,120of two-dimensional semiconductor material may remain below the mask strips106,108,110, respectively. In some embodiments, the strips116,118,120are exposed along the sidewalls of the contact trenches112,114.

In some embodiments, referring toFIG.1D,FIG.1E,FIG.2DandFIG.2E, two-dimensional metallic contacts122,124are formed within the contact tranches112,114. In some embodiments, the two-dimensional metallic contacts122,124respectively include stacked monolayers (which may be collectively referred to as layers)126,128of a two-dimensional metallic material formed within the contact trenches112,114. In some embodiments, the layers126of the two-dimensional metallic material are formed on the substrate100at the bottom of the contact trench112. The bottommost monolayer of the layers126of the two-dimensional metallic material is disposed in between the strips116and118of two-dimensional semiconductor material, while the upper monolayers of the layers126may be disposed in between the mask strips106and108. Similarly, the layers128of the two-dimensional metallic material are formed on the substrate100at the bottom of the contact trench114. The bottommost monolayer of the layers126of the two-dimensional metallic material is disposed in between the strips118and120of the two-dimensional semiconductor material, while the upper monolayers of the layers128may be disposed in between the mask strips108and110. In some embodiments, the two-dimensional metallic contacts122,124are formed by growing the layers126,128of two-dimensional metallic material into the contact trenches112,114. In some embodiments, portions136,138,140of two-dimensional metallic material may be respectively formed on the mask strips106,108,110, while forming the layers126,128of two-dimensional metallic material in the contact trenches112,114. In some embodiments, the two-dimensional metallic material includes a compound having a substantially two-dimensional structure and metallic or semimetallic character. In some embodiments, the two-dimensional metallic material may include transition metal dichalcogenides having metallic or semimetallic character, such as compounds of formula MX2, where M may be V, Nb, Ta, Ti, Hf, Mo, W, Pd, or Pt, and X may be S, Se, or Te. Examples of transition metal dichalcogenides having metallic character include VS2, VSe2, VTe2, NbS2, NbSe2, NbTe2, TaS2, TaSe2, TaTe2, TiS2, TiSe2, HfTe2, MoTe2, WTe2, PtSe2, PdSe2, PtTe2. To grow the two-dimensional metallic material, similar processes as previously described for the two-dimensional semiconductor material may be adopted.

In some embodiments, the strip118of two-dimensional semiconductor material and the adjacent two-dimensional metallic contacts122,124include different materials. In some embodiments, the strip118in between the two-dimensional metallic contacts122,124may act as a channel region130of a transistor, and the two-dimensional metallic contacts122,124may act as source and drain regions of the transistor. In some embodiments, the interfaces between the two-dimensional metallic contact122and the channel region130and the two-dimensional metallic contact124and the channel region130constitute semiconductor-metallic junctions132,134, respectively. In some embodiments, the monolayer(s) forming the strip118or the layers126,128may be considered to extend along an XY plane, so that the semiconductor-metallic junctions132,134extend along the Z direction, for example, in a YZ plane or, more generally, along surfaces extending along the Z direction. Alternatively stated, there is a lateral contact between the channel region130and the two-dimensional metallic contacts122,124, as opposed to a vertical contact with interfaces extending in the XY plane. For example, the two-dimensional metallic material of the layers126,128contacts opposite side surfaces118sof the strip118of two-dimensional semiconductor material, while the top surface118tand the bottom surface118bof the strip118may be in contact with the mask strip108and the substrate100, respectively.

In some embodiments, the mask strips106,108,110with the overlying portions136,138,140of two-dimensional metallic material are removed, for example through one or more etching processes. In some embodiments, the etching process may include a buffered oxide etching step. In some alternative embodiments, a planarization process may be performed to remove the overlying portions136,138,140. Upon removal of the mask strips106,108,110, the strips116,118,120of two-dimensional semiconductor material previously covered are once again exposed, as illustrated inFIG.1FandFIG.2F. The layers126,128of the two-dimensional metallic contacts122,124, also remain in between the strips116,118,120of the two-dimensional semiconductor material. Thereafter, photoresist strips142,144,146are respectively formed on the strips116,118,120, as illustrated inFIG.1GandFIG.2G. In some embodiments, the photoresist strips142,144,146extend along the Y direction as the underlying strips116,118,120of two-dimensional semiconductor material and are separated from each other along the X direction by contact trenches148,150. In some embodiments, the photoresist strip144located on the strip118of two-dimensional semiconductor material in between the two-dimensional metallic contacts122,124fills the gap between the two-dimensional metallic contacts122,124, and extend on at least a portion of the topmost monolayers of the layers126,128. That is, the photoresist strip144may partially extend on top surfaces122t,124tof the two-dimensional metallic contacts122,124. For example, the contact trench148located in between the photoresist strip142and the photoresist strip144exposes at its bottom the strip116of two-dimensional semiconductor material, and, also, an outer sidewall122oand portion of the top surface122tof the two-dimensional metallic contact122. Similarly, the contact trench150separating the photoresist strip144from the photoresist strip146exposes at its bottom the strip120of two-dimensional semiconductor material, as well as an outer sidewall124oand portion of the top surface124tof the two-dimensional metallic contact124. In some embodiments, outer sidewalls122o,124oare the side surfaces of the two-dimensional metallic contact at an opposite side with respect to the channel region130. In some embodiments, the patterned photoresist strips142,144,146are formed through a sequence of deposition, exposure, and development steps.

Referring toFIG.1G,FIG.1H,FIG.2G, andFIG.2H, in some embodiments, metal contacts152,154are formed in the contact trenches148,150, respectively. In some embodiments, the metal contact152is disposed on the strip116of two-dimensional semiconductor material, and contacts at least the outer sidewall122oof the two-dimensional metallic contact122. In some embodiments, the metal contact152may further extend on a portion of the top surface122tof the two-dimensional metallic contact122. Similarly, the metal contact154is disposed on the strip120of the two-dimensional semiconductor material, and contacts at least the outer sidewall124oof the two-dimensional metallic contact124. In some embodiments, the metal contact154may optionally extend on a portion of the top surface124tof the two-dimensional metallic contact124. In some embodiments, the outer sidewalls122o,124omay correspond to metallic-metal junctions156,158between the metal contacts152,154and the two-dimensional metallic contacts122,124, respectively. That is, the contact with the layers126,128of two-dimensional metallic material may happen side-ways, rather than involving the top or bottom surfaces of the layers126,128. In some embodiments, the material of the metal contacts152,154includes cobalt (Co), tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), aluminum (Al), zirconium (Zr), hafnium (Hf), a combination thereof, or other suitable metals or alloys. In some embodiments, the metal contacts152,154may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plating, other deposition techniques, or a combination thereof. In some embodiments, the material of the metal contacts152,154may initially extend on the photoresist strips142,144,146as well, and a planarization process (e.g., a chemical mechanical planarization process or the like) may be performed to remove the material in excess, until the photoresist strips142,144,146are exposed. In some embodiments, the photoresist strips142,144,146are removed, for example via ashing or stripping. Upon removal of the photoresist strips142,144,146, the strip118, the portions of the strips116,120not covered by the metal contacts152,154, and, possibly, portions of the top surfaces122t,124tof the two-dimensional metallic contacts122,124, are once again exposed, as illustrated, for example, inFIG.1IandFIG.2I. In some embodiments, the portions of the strips116,120protruding from below the metal contacts152,154may be removed, for example during an etching step as previously described, leaving the narrower strips160,162of two-dimensional semiconductor material in between the metal contacts152,154and the substrate100. In some embodiments, temporary protective masks (not shown) may be used to protect the strip118of two-dimensional semiconductor material during formation of the strips160,162of two-dimensional semiconductor material. In some embodiments, the footprints of the strips160,162of two-dimensional semiconductor material coincide with the span of the portions of the corresponding metal contacts152,154not stacked on the two-dimensional metallic contacts122,124.

Referring toFIG.1KandFIG.2K, in some embodiments, a gate structure164is formed on the strip118of the channel region130, in between the two-dimensional metallic contacts122,124. In some embodiments, the gate structure164completely covers the strip118. In some embodiments, the gate structure164fills the space in between the two-dimensional metallic contacts122,124. In some embodiments, the gate structure164contacts inner sidewalls122i,124iof the two-dimensional metallic contacts122,124, where the inner sidewalls122i,124iare opposite to the metallic-metal junctions156,158with the metal contacts152,154. In some embodiments, the gate structure164may further extend on the portions of the top surfaces122t,124tleft exposed by the metal contacts152,154. In some embodiments, the gate structure164includes gate dielectric layer166and a gate metal layer168sequentially stacked. In some embodiments, it is the gate dielectric layer166that extends on the strip118of two-dimensional semiconductor material and on the two-dimensional metallic contacts122,124. In some embodiments, the gate dielectric layer166further extends on the top surfaces122t,124tof the two-dimensional metallic contacts122,124up to the metal contacts152,154. For example, the gate dielectric layer166may have a width W166aalong the X direction in between the two-dimensional metallic contacts122,124, and a width W166bgreater than the width W166ain between the metal contacts152,154. In some embodiments, a thickness T166along the Z direction of the gate dielectric layer166is greater than the thicknesses T126, T128of the two-dimensional metallic contacts122,124and is also greater than the thicknesses T152, T154of the metal contacts152,154. In some embodiments, the thicknesses T152, T154, T166may independently be in the range from 30 to 100 nanometers. In some embodiments, a ratio of the thickness T126(or T128) to the thickness T152may be in the range from 0.07 to 0.3. In some embodiments, a ratio of the thickness T126(or T128) to the thickness T166may be in the range from 0.06 to 0.2. In some embodiments, a ratio of the thickness T152to the thickness T166may be in the range from 0.3 to 1.6. In some embodiments, the gate metal layer168may be formed as a strip pattern running on the gate dielectric layer166. The gate dielectric layer166may separate the gate metal layer168from the strip118of two-dimensional semiconductor material, the two-dimensional metallic contacts122,124, and the metal contacts152,154.

In some embodiments, the gate dielectric layer166may be a composite layer, including an interface dielectric layer and a high-k dielectric layer stacked on the interface dielectric layer. In some embodiments, the interface dielectric layer may include a dielectric material such as silicon oxide or silicon oxynitride. In some embodiments, the high-k dielectric layer has a dielectric constant greater than about 4, greater than about 12, greater than about 16, or even greater than about 20. For example, a material of the high-k dielectric layer may include a metal oxide, such as ZrO2, Gd2O3, HfO2, BaTiO3, Al2O3, LaO2, TiO2, Ta2O5, Y2O3, SrTiO3(STO), BaTiO3(BTO), BaZrO, HfZrO, HfLaO, HfTaO, HfiO, a combination thereof, or other suitable materials. The gate metal layer168may include a work function material and a gate electrode material. In some embodiments, the work function material and the gate electrode material are sequentially deposited over the gate dielectric layer166. In some embodiments, the work function material may be selected according to the conductivity type desired for the transistor to adjust a threshold voltage of the transistor. For example, p-type work function materials include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. On the other hand, n-type work function materials include, for example, Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. In some embodiments, the gate electrode material includes titanium (Ti), tantalum (Ta), tungsten (W), aluminum (Al), zirconium (Zr), hafnium (Hf), titanium aluminum (TiAl), tantalum aluminum (TaAl), tungsten aluminum (WAl), zirconium aluminum (ZrAl), hafnium aluminum (HfAl), titanium nitride (TiN), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tungsten silicon nitride (WSiN), titanium carbide (TiC), tantalum carbide (TaC), titanium aluminum carbide (TiAlC), tantalum aluminum carbide (TaAlC), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), any other suitable metal-containing material, or a combination thereof. In some embodiments, the method of providing the work function material and/or the gate electrode material includes performing at least one suitable deposition technique, such as CVD, PECVD, ALD, RPALD, PEALD, MBD, or the like.

FIG.3is a schematic view of the strips118,160,162of two-dimensional semiconductor material and the layers126,128of the two-dimensional metallic contacts122,124. Referring toFIG.1K,FIG.2K, andFIG.3, in the semiconductor device D10, the channel region130of a transistor is formed by the strip118of two-dimensional semiconductor material. At opposite ends of the strip118of two-dimensional semiconductor material are formed the two-dimensional metallic contacts122,124. In some embodiments, the strip118of two-dimensional semiconductor material includes a different material than the layers126,128of the two-dimensional metallic contact. The interfaces between the strip118of two-dimensional semiconductor material and the two-dimensional metallic contacts122,124are semiconductor-metallic junctions132,134. In some embodiments, two-dimensional materials are used for the channel region130and the two-dimensional metallic contacts122,124, and the semiconductor-metallic junctions132,134have a horizontal geometry (e.g., along the X direction), thus lowering the contact resistance due to a van der Waals gap existing when a two-dimensional material is contacted vertically (e.g., along the Z direction). For similar reasons, the later contact between the metal of the metal contacts152,154and the two-dimensional metallic material of the two-dimensional metallic contacts122,124may reduce or even avoid contact resistance at the metallic-metal junctions156,158.

In some embodiments, it is possible that the two-dimensional metallic material of the layers126,128(covalently) bonds at the interface with the two-dimensional semiconductor material of the channel region130. For example, inFIG.3is illustrated the structure in the case in which both the two-dimensional metallic material and the two-dimensional semiconductor material are transition metal dichalcogenides. For example, MoS2may be used as the two-dimensional semiconductor material and PtSe2may be used as the two-dimensional metallic material. In some embodiments, in a monolayer of transition metal dichalcogenide, a layer of atoms of the transition metal may be sandwiched in between layers of chalcogen atoms. In some embodiments, a van der Waals gap separate the monolayer of transition metal dichalcogenide from the overlying element, be it another monolayer of transition metal dichalcogenide, the material of the gate dielectric layer166, or the metal of the metal contacts152,154. In some embodiments, the strips118,160,162of two-dimensional semiconductor material may include a single monolayer of two-dimensional semiconductor material, and such single monolayer may be substantially coplanar along the Z direction (e.g., aligned in the XY plane) with the bottommost monolayers126A,128A of the layers126,128of the two-dimensional metallic contacts122,124. In some embodiments, the bottommost monolayers126A,128A of two-dimensional semiconductor material may be (covalently) bonded to the single monolayer of two-dimensional semiconductor material, while the upper monolayers126B-G,128B-G may be stacked over the respective bottommost monolayer126A or128A. In some embodiments, the number of monolayers126A-G,128A-G of two-dimensional metallic material in a two-dimensional metallic contact122,124is greater than the number of monolayers of two-dimensional semiconductor material in the channel region130. In some embodiments, the number of monolayers126A-G,128A-G in a two-dimensional metallic contact122or124is not particularly limited, and may be selected to tune the properties of the two-dimensional metallic contact122or124.

FIG.4AandFIG.4Bare schematic perspective views of structures formed during manufacturing of a semiconductor device D20according to some embodiments of the disclosure.FIG.5AandFIG.5Bare schematic cross-sectional views of the structures ofFIG.4AandFIG.4B, respectively, taken in an XZ plane at the level height of the line II-II′ along the Y direction. In some embodiments, the structure ofFIG.4Amay be formed following similar processes as previously described with reference toFIG.1AtoFIG.2C,FIG.1E, andFIG.2E. Briefly, on the substrate200, the sheet202of two-dimensional semiconductor material is formed, followed by the mask strips204,206,208, to obtain a structure similar to the one illustrated inFIG.1CandFIG.2C. As previously described, the steps may be performed at the FEOL level or the BEOL level, according to the desired structure. In some embodiments, the sheet202of two-dimensional semiconductor material may include a thickness-modulated switchable material, that is, a material, such as PtSe2, PdSe2, or PtTe2, that switches electronic character according to the number of monolayers stacked. For example, in the case of PtSe2, when one or few monolayers (in some embodiments, about five layers) are stacked on each other, the layer stack has semiconducting properties, while when more monolayers are stacked (in some embodiments, about six layers or more), the layer stack has metallic properties. In some embodiments, one of such thickness-modulated switchable material may be used both as the two-dimensional semiconductor material for the channel region210and as the two-dimensional metallic material of the two-dimensional metallic contacts212,214, adjusting the thickness (e.g., the number of monolayers in the sheet202and in the layers216,218) according to the desired electronic properties. That is, the channel region210and the two-dimensional metallic contacts212,214may include the same material. In some embodiments, the above-mentioned thickness-modulated switchable materials may be conveniently prepared, for example by CVP, PVD, ALD, or MBE, by reaction of a precursor for the transition metal atom and another precursor for the chalcogen atom. As precursors of the transition metal atom, the neat metal (e.g., Pt or Pd), its chlorides (e.g., PtCl2, PtCl4, PdCl2), or its oxides (e.g., PtO2, PdO) may be used. As precursor of the chalcogen atom, the elemental chalcogen (e.g., Se or Te) or the hydrogen chalcogenide (e.g., H2Se, H2Te) may be used. In some embodiments, when chlorides and elemental chalcogens are used as precursors, deposition of the thickness-modulated switchable material may be achieved at temperature below 500° C., for example in the range from 300° C. to 400° C., for example via PVD. In some alternative embodiments, the thickness-modulated switchable material may be deposited using as a source the thickness-modulated switchable material in bulk form.

FIG.6is a schematic view of the sheet202of the channel region210and the layers216,218of the two-dimensional metallic contacts212,214. Referring toFIG.4A,FIG.5A, andFIG.6, in some embodiments, the sheet202of two-dimensional semiconductor material includes the thickness-modulated switchable material, in a number of monolayers such that the thickness-modulated switchable material has semiconducting properties. The monolayers216A-F,218A-F of the two-dimensional metallic material also include the same thickness-modulated switchable material, and are formed on portions of the sheet202exposed by the mask strips204,206,208. Alternatively stated, the portions of the sheet202left exposed by the mask strips204,206,208may be retained on the substrate200to act as bottommost monolayers for the two-dimensional metallic contacts212,214. In such embodiments, different regions of the sheet202may have different electronic character, depending on whether additional layers216,218are formed thereon. For example, the regions of the sheet202underlying the mask strips204,206,208have semiconducting properties, and the regions of the sheet202together with the overlying layers216,218will have metallic properties. At the boundary of such regions, semiconductor-metallic junctions220,222are formed, as indicated between the channel region210and the two-dimensional metallic contact212and between the channel region210and the two-dimensional metallic contact214, respectively. In some embodiments, the semiconductor-metallic junctions220,222have reduced contact resistance because of the horizontal contact geometry between the two-dimensional metallic material and the two-dimensional semiconductor material.

As previously described, during formation of the two-dimensional metallic contacts212,214portions224,226,228of the thickness-modulated switchable material may be respectively formed on the mask strips204,206,208. In some embodiments, forming the semiconductor device D20includes performing process steps similar to the ones previously described with reference toFIG.1FtoFIG.2K. Briefly, referring toFIG.4A,FIG.5A,FIG.4B, andFIG.5B, the mask strips204,206,208with the overlying portions224,226,228of thickness-modulated switchable material are removed, for example via ashing or stripping. Metal contacts230,232are formed on the sheet202beside the two-dimensional metallic contacts212,214, for example by disposing a metal material in trenches defined by photoresist strips (not shown). The sheet202may be trimmed at the sides to remove portions not covered by the metal contacts230,232, thus forming the strip234of thickness-modulated switchable material extending from the metal contact230on one side of the channel region210to the metal contact232at the opposite side of the channel region210. The gate structure236including the gate dielectric layer238and the gate metal layer240is then formed on the channel region210, in between the two-dimensional metallic contacts212,214.

In some embodiments, the metal contacts230,232contact the outer sidewalls212o,214oof the two-dimensional metallic contacts212,214, respectively, thus forming lateral (horizontal) metallic-metal junctions242,244. In some embodiments, the lateral (horizontal) geometry of the metallic-metal junctions242,244results in reduced contact resistance. Without being bound to or limited by any theory, it is possible the reduced contact resistance stems from a lower or absent van der Waals barrier between the two-dimensional metallic material and the metal. In some embodiments, the metal contacts230,232extend also on the top surfaces212t,214tof the two-dimensional metallic contacts212,214. In some embodiments, the metal contacts230,232cover at least a portion of the top surfaces212t,214t. In some embodiments, the gate dielectric layer238extends on the inner sidewalls212i,214iof the two-dimensional metallic contacts. In some embodiments, the gate dielectric layer238further extends on the portions of the top surfaces212t,214tnot covered by the metal contacts230,232. In some embodiments, the gate dielectric layer238separates the gate metal layer240from the metal contacts230,232and the two-dimensional metallic contacts212,214.

FIG.7is a schematic top view of the two-dimensional metallic contacts212,214according to some embodiments of the disclosure. In some embodiments, the two-dimensional metallic contacts212,214may have an elongated shape along the Y direction, with regions of different widths along the X direction. For example, the two-dimensional metallic contacts212,214may present narrower regions of widths W212a, W214aprotruding from wider regions of width W212b, W214b. In some embodiments, the shape of the two-dimensional metallic contacts212,214is determined by the pattern of the mask strips204,206,208. In some embodiments, the shape of the two-dimensional metallic contacts212,214is not particularly limited, and may be selected according to circuit design and/or production requirements.

FIG.8AandFIG.8Bare schematic perspective views of structures formed during a manufacturing process of the semiconductor device D30.FIG.9AandFIG.9Bare schematic cross-sectional views of the structures ofFIG.8AandFIG.8B, respectively, taken at the XZ plane at the level height of the line III-III′ along the Y direction. In some embodiments, the structure ofFIG.8AandFIG.9Amay be formed following similar processes as previously described with reference toFIG.1AtoFIG.2G. As previously described, the steps may be performed at the FEOL level or the BEOL level, according to the desired structure. Briefly, on the substrate300, the strips302,304,306of two-dimensional semiconductor material are formed by patterning a precursor sheet (not shown) of two-dimensional semiconductor material initially formed on the substrate. The strip304of two-dimensional semiconductor material may be configured as a channel region308, and two-dimensional metallic contacts310,312may be formed at opposite ends of the channel region308, by providing the layers314,316of two-dimensional metallic material on the substrate300. The two-dimensional metallic material of the two-dimensional metallic contacts310,312may be different (in terms of chemical composition) from the two-dimensional semiconductor material of the channel region308, and the layers314,316may be formed directly on the substrate, after removal of the two-dimensional semiconductor material of the precursor sheet. In some embodiments, the two-dimensional metallic contacts314,316forms lateral (horizontal) semiconductor-metallic junctions318,320with the two-dimensional semiconductor material of the channel region308, thus lowering the contact resistance at the interface between the two materials. As previously described, in some embodiments, the two-dimensional metallic material of one or more monolayers of the layers314,316may be covalently bonded to the two-dimensional semiconductor material of one or more corresponding monolayers of the strip304in the channel region308. In some embodiments, the photoresist strips322,324,326are formed in a similar manner as previously described with reference toFIG.1G. In some embodiments, the structure ofFIG.8Amay be obtained from the structure ofFIG.1Gby removing the two-dimensional semiconductor material from the bottom of the trenches328,330separating the photoresist strips322,324,326, so that the substrate300may be exposed at the bottom of the trenches328,330.

In some embodiments, forming the semiconductor device D30includes performing process steps similar to the ones previously described with reference toFIG.1HtoFIG.2K. Briefly, referring toFIG.8A,FIG.8B,FIG.9A, andFIG.9B, metal contacts332,334are formed on the substrate300beside the two-dimensional metallic contacts310,312, for example by disposing a metal material in trenches328,330defined by the photoresist strips322,324,326. The photoresist strips322,324,326are removed, for example via ashing or stripping. In some embodiments, the strips302,306of two-dimensional semiconductor material exposed after removal of the photoresist strips322,324,326are removed, so that only the strip304of two-dimensional semiconductor material remains in the channel region308. The metal contacts332,334may be in direct contact with the substrate300. The metal contacts332,334extend on the outer sidewalls310o,312oof the two-dimensional metallic contacts310,312, forming lateral (horizontal) metallic-metal junctions336,338. The horizontal geometry of the metallic-metal junctions336,338may result in lower contact resistance. The gate structure340including the gate dielectric layer342and the gate metal layer344is then formed on the channel region308, in between the two-dimensional metallic contacts310,312. In some embodiments, the metal contacts332,334extend also on the top surfaces310t,312tof the two-dimensional metallic contacts310,312. In some embodiments, the metal contacts332,334cover at least a portion of the top surfaces310t,312t. In some embodiments, the gate dielectric layer342extends on the inner sidewalls310i,312iof the two-dimensional metallic contacts310,312. In some embodiments, the gate dielectric layer342further extends on the portions of the top surfaces310t,312tnot covered by the metal contacts332,334. In some embodiments, the gate dielectric layer342separates the gate metal layer344from the metal contacts332,334and the two-dimensional metallic contacts310,312.

FIG.10AandFIG.10Bare schematic perspective views of structures formed during a manufacturing process of the semiconductor device D40.FIG.11AandFIG.11Bare schematic cross-sectional views of the structures ofFIG.10AandFIG.10B, respectively, taken at the XZ plane at the level height of the line IV-IV′ along the Y direction. In some embodiments, the structure ofFIG.10AandFIG.11Amay be formed from the structure ofFIG.5Afollowing similar processes as previously described. In some embodiments, the steps may be performed at the FEOL level or the BEOL level, according to the desired structure. Briefly, on the substrate400, the strips402,404,406of two-dimensional semiconductor material are formed by removing portions of a precursor sheet (not shown) of two-dimensional semiconductor material initially formed on the substrate. In some embodiments, the strips402,404,406include a thickness-modulated switchable material, similar to what was previously discussed with reference toFIG.4AandFIG.5A. The strip404of two-dimensional semiconductor material may be configured as a channel region408, and two-dimensional metallic contacts410,412may be formed at opposite ends of the channel region408, by providing the additional layers414,416of the thickness-modulated switchable material on the strip404. That is, the metallic character of the two-dimensional metallic contacts410,412may be achieved by stacking a sufficient number of monolayers as the layers414,416on the strip404, where the layers414,416and the strip404include the same thickness-modulated switchable material. In some embodiments, the two-dimensional metallic contacts410,412form lateral (horizontal) semiconductor-metallic junctions418,420with the portion of the strip404in the channel region408, thus lowering the contact resistance between the regions of different electronic character. As previously described, in some embodiments, the strip404may extend from the outer sidewall410oof the two-dimensional metallic contact410to the outer sidewall412oof the two-dimensional metallic contact412. In some embodiments, the photoresist strips422,424,426are formed in a similar manner as previously described with reference toFIG.1G. In some embodiments, the thickness-modulated switchable material is removed from the bottom of the trenches428,430separating the photoresist strips422,424,426, so that the substrate400is exposed at the bottom of the trenches428,430.

In some embodiments, forming the semiconductor device D40includes performing process steps similar to the ones previously described with reference toFIG.1HtoFIG.2K. Briefly, referring toFIG.10A,FIG.10B,FIG.11A, andFIG.11B, metal contacts432,434are formed on the substrate400beside the two-dimensional metallic contacts410,412, for example by disposing a metal material in the trenches428,430defined by the photoresist strips422,424,426. The photoresist strips422,424,426are removed, for example via ashing or stripping. In some embodiments, the strips402,406of two-dimensional semiconductor material exposed after removal of the photoresist strips422,424,426are also removed, so that only the strip404of two-dimensional semiconductor material remains on the substrate400. The metal contacts432,434may be in direct contact with the substrate400. The metal contacts432,434extend on the outer sidewalls410o,412oof the two-dimensional metallic contacts410,412, forming lateral (horizontal) metallic-metal junctions436,438. The horizontal geometry of the metallic-metal junctions436,438may result in lower contact resistance. The gate structure440including the gate dielectric layer442and the gate metal layer444is then formed on the channel region408, in between the two-dimensional metallic contacts410,412. In some embodiments, the metal contacts432,434may further extend on the top surfaces410t,412tof the two-dimensional metallic contacts410,412. In some embodiments, the metal contacts410,412cover at least a portion of the top surfaces410t,412t. In some embodiments, the gate dielectric layer442extends on the inner sidewalls410i,412iof the two-dimensional metallic contacts410,412. In some embodiments, the gate dielectric layer442further extends on the portions of the top surfaces410t,412tnot covered by the metal contacts432,434. In some embodiments, the gate dielectric layer442separates the gate metal layer444from the metal contacts432,434and the two-dimensional metallic contacts410,412.

FIG.12AandFIG.12Bare schematic perspective views of structures formed during manufacturing of the semiconductor device D50according to some embodiments of the disclosure.FIG.13AandFIG.13Bare schematic cross-sectional views of the structures illustrated inFIG.12AandFIG.12B, taken in the XZ plane located at the level height of the line V-V′ along the Y direction.FIG.14is a schematic view of some components of the semiconductor device D50according to some embodiments of the disclosure. Referring toFIG.12AandFIG.13A, in some embodiments, a substrate500is provided. The substrate500may be similar to the substrate100ofFIG.1A. In some embodiments, the sheet502of two-dimensional semiconductor material is formed on the substrate500. In some embodiments, a difference with respect to the structure illustrated inFIG.1Alies in that the sheet502of two-dimensional semiconductor material includes multiple stacked monolayers (e.g., the two monolayers502A,502B) of two-dimensional semiconductor material. Referring toFIG.12AtoFIG.14, in some embodiments, manufacturing the semiconductor device D50includes performing process steps as previously described, for example with reference toFIG.1BtoFIG.2K. Briefly, the sheet502of two-dimensional semiconductor material is patterned to form strips504,506,508of two-dimensional semiconductor material. The strip506may correspond to the channel region510, and two-dimensional metallic contacts512,514may be formed on the substrate500at opposite sides of the strip506, for example by forming the layers516,518of two-dimensional metallic material. In some embodiments, the two-dimensional metallic contacts512,514include a different material than the strip506of two-dimensional semiconductor material. In some alternative embodiments, the two-dimensional metallic contacts512,514and the strip506of two-dimensional semiconductor material may include a different number of monolayers506A,506B,516A-G,518A-G of a same thickness-modulated switchable material. In some embodiments, lateral semiconductor-metallic junctions520,522are formed at the boundary between the channel region510and the two-dimensional metallic contacts512,514. In some embodiments, the monolayers506A,508B,516A-G,518A-G of two-dimensional materials of the channel region510and the two-dimensional metallic contacts512,514may include transition metal dichalcogenides. Within a monolayer506A,506B,516A-G, or518A-G, transition metal atoms are disposed between two levels of chalcogen atoms to which the transition metal is (covalently) bonded, and, upon stacking, chalcogen atoms belonging to different monolayers are separated from each other by a van der Waals gap. In some embodiments, monolayers516A,516B,518A,518B of the two-dimensional metallic contacts512,514may be (covalently) bonded to corresponding monolayers506A,506B of two-dimensional semiconductor material in the channel region510. For example, when the strip506of two-dimensional semiconductor material includes two monolayers506A,506B stacked over each other, the bottommost monolayer506A may be bonded to the bottommost monolayer516A of the two-dimensional metallic contact512and the bottommost monolayer518A of the two-dimensional metallic contact514, and the upper monolayer506B may be bonded to the corresponding monolayers516B and518B of the two-dimensional metallic contacts512,514. The remaining monolayers516C-G,518C-G may be stacked on the upper monolayers516B,518B, respectively. In some embodiments, corresponding bonds may exist between the monolayers516A,516B and the monolayers504A,504B of the strip504, and between the monolayers518A,518B and the monolayers508A,508B of the strip508. The disclosure does not limit the number of monolayers506A,506B,516A-G,518A-G as long as the strip506in the channel region510has semiconductor character, and the two-dimensional metallic contacts512,514have metallic character.

Referring toFIG.12BandFIG.13B, metal contacts524,526are respectively formed on the strips504,508beside the two-dimensional metallic contacts512,514, for example by disposing a metal material in trenches defined by photoresist strips (not shown). In some embodiments, the strips504,508of two-dimensional semiconductor material are trimmed by removing portions of the strips504,508not covered by the metal contacts524,526, so as to expose the substrate500. In some embodiments, the metal contacts524,526extend on the outer sidewalls512o,514oof the two-dimensional metallic contacts512,514, forming lateral (horizontal) metallic-metal junctions528,530. The horizontal geometry of the metallic-metal junctions528,530may result in lower contact resistance. In some embodiments, the gate structure532including the gate dielectric layer534and the gate metal layer536is then formed on the channel region510, in between the two-dimensional metallic contacts512,514. In some embodiments, the metal contacts524,526may further extend on the top surfaces512t,514tof the two-dimensional metallic contacts512,514. In some embodiments, the metal contacts524,526cover at least a portion of the top surfaces512t,514t. In some embodiments, the gate dielectric layer534extends on the inner sidewalls512i,514iof the two-dimensional metallic contacts512,514. In some embodiments, the gate dielectric layer534further extends on the portions of the top surfaces512t,514tnot covered by the metal contacts524,526. In some embodiments, the gate dielectric layer534separates the gate metal layer536from the metal contacts524,526and the two-dimensional metallic contacts512,514.

While some embodiments have been discussed above for illustration purpose, the disclosure is not limited thereto, and features of different embodiments may be combined as required. For example, any one of the strips118ofFIG.1K,234ofFIG.4B,304ofFIG.8B, or404ofFIG.10Bmay include multiple monolayers of two-dimensional semiconductor material, as described for the strip506ofFIG.12B. As another example, the metal contacts524,526ofFIG.12Bmay be formed directly on the substrate500, omitting the strips504and508.

For all the disclosed embodiments, additional process steps and features may also be included. For example, when the described manufacturing process is performed as a front-end-of-line process, active or passive devices (not shown) may be formed on the substrate (e.g., the substrate100) in addition to the described steps, and an interconnection structure (not shown) may integrate such devices into a functional circuit. In some embodiments, an interlayer dielectric (not shown) may be formed on the substrate burying the fabricated transistors, and contact vias (not shown) may be formed through the interlayer dielectric to land on the metal contacts (e.g., the metal contacts152,154ofFIG.1K) or the gate metal layer (e.g., the gate metal layer168ofFIG.1K), to integrate the transistor in larger circuits.

In accordance with some embodiments of the disclosure, a semiconductor device includes a channel region, a first two-dimensional metallic contact, a second two-dimensional metallic contact, a gate structure, a first metal contact, and a second metal contact. The channel region includes a two-dimensional semiconductor material. The first two-dimensional metallic contact is disposed at a side of the channel region and includes a two-dimensional metallic material. The second two-dimensional metallic contact is disposed at an opposite side of the channel region and includes the two-dimensional metallic material. The gate structure is disposed on the channel region in between the first two-dimensional metallic contact and the second two-dimensional metallic contact. The first metal contact is disposed at an opposite side of the first two-dimensional metallic contact with respect to the channel region. The second metal contact is disposed at an opposite side of the second two-dimensional metallic contact with respect to the channel region. The first two-dimensional metallic contact and the second two-dimensional metallic contact contact sideways the channel region to form lateral semiconductor-metallic junctions.

In accordance with some embodiments of the disclosure, a semiconductor device comprises a substrate, a strip of a two-dimensional semiconductor material, layers of a two-dimensional metallic material, metal blocks and a gate structure. The strip of the two-dimensional semiconductor material is disposed on the substrate. The layers of the two-dimensional metallic material are disposed over the substrate in stacks at opposite sides of the strip. The metal blocks extend on outer sidewalls of the stacked layers of the two-dimensional metallic material. The gate structure is disposed on the strip of the two-dimensional semiconductor material in between the stacks of the layers of the two-dimensional metallic material. The strip of two-dimensional semiconductor material extends on the substrate along a first direction and a second direction perpendicular to the first direction. Semiconductor-metallic junctions between the layers of the two-dimensional metallic material and the strip of the two-dimensional semiconductor material extend along at least one direction selected from the first direction and the second direction and along a third direction perpendicular to the first direction and the second direction.

In accordance with some embodiments of the disclosure, a manufacturing method of a semiconductor device includes the following steps. A sheet of a two-dimensional semiconductor material is formed on a substrate. Stacked layers of a two-dimensional metallic material are formed at opposite sides of the two-dimensional semiconductor material. A thickness of the stacked layers of two-dimensional metallic material is greater than a thickness of the sheet of the two-dimensional semiconductor material. Semiconductor-metallic junctions extend parallel to inner sidewalls of the stacked layers of two-dimensional metallic material. The sheet of the two-dimensional semiconductor material is patterned to form a strip of two-dimensional semiconductor material. A metal material is disposed over the substrate. The metal material extends on outer sidewalls of the stacked layers of two-dimensional metallic material. The outer sidewalls are opposite to the inner sidewalls. A gate structure is formed on the strip of the two-dimensional semiconductor material. The gate structure contacts the inner sidewalls of the stacked layers of two-dimensional metallic material.