ELECTRONIC DEVICE PACKAGE AND METHOD OF  MANUFACTURING THE SAME

An electronic device package includes a substrate, at least one first electronic component and at least one electrical element. The substrate includes a first surface. The first surface comprises a plurality of electrical terminals including a first region and a second region, and a pitch of the electrical terminals of the first region is smaller than a pitch of the electrical terminals of the second region. The at least one first electronic component is electrically connected to the substrate and at least over the first region. The at least one electrical element is disposed above the first electronic component and farther from the substrate than the first electronic component. A number of the at least one electrical element under the first region is less than a number of the at least one electrical element under the second region.

TECHNICAL FIELD

The present disclosure generally relates to an electronic device package and method of manufacturing the same, and more particularly to a three-dimensional (3D) stacking electronic device package and method of manufacturing the same.

BACKGROUND

In a 3D stacking electronic device package, electronic components including active electronic components and/or passive electronic components are stacked to increase area utility. For example, a first electronic component may be flip chip bonded to a substrate, and a second electronic component may be vertically overlapping with the first electronic component. The first and second electronic components may be encapsulated by a molding layer. The second electronic component overlapping the first electronic component, however, would impede detection of the molding layer between the substrate and the first electronic component. Therefore, there is a desire for, for example, but not limited to, an electronic device package that would allow a detection of molding layer.

SUMMARY

In some embodiments, an electronic device package includes a substrate, at least one first electronic component and at least one electrical element. The substrate includes a first surface. The first surface comprises a plurality of electrical terminals including a first region and a second region, and a pitch of the electrical terminals of the first region is smaller than a pitch of the electrical terminals of the second region. The at least one first electronic component is electrically connected to the substrate and at least over the first region. The at least one electrical element is disposed above the first electronic component and farther from the substrate than the first electronic component. A number of the at least one electrical element under the first region is less than a number of the at least one electrical element under the second region.

In some embodiments, an electronic device package includes a substrate, at least one first electronic component and at least one electrical element. The substrate includes a first surface. The first surface comprises a plurality of electrical terminals including a first region and a second region, and a pitch of the electrical terminals of the first region is smaller than a pitch of the electrical terminals of the second region. The at least one first electronic component is electrically connected to the substrate and at least over the first region. The at least one electrical element is disposed above the first electronic component and farther from the substrate than the first electronic component. An area of the at least one electrical element under the first region projected on the first surface in a direction substantially perpendicular to the first surface is less than an area of the at least one electrical element under the second region projected on the first surface in the direction.

In some embodiments, an electronic device package includes a substrate, at least one first electronic component and at least one electrical element. The substrate includes a first surface. The first surface comprises a plurality of electrical terminals including a first region and a second region, and a pitch of the electrical terminals of the first region is smaller than a pitch of the electrical terminals of the second region. The at least one first electronic component is electrically connected to the substrate and at least over the first region. The at least one electrical element is disposed above the first electronic component and farther from the substrate than the first electronic component. A defect detectability in and/or under the first region is higher than a defect detectability in and/or under the second region.

DETAILED DESCRIPTION

Some embodiments, or examples, illustrated in the figures are disclosed below using specific language. It will nevertheless be understood that the embodiments and examples are not intended to be limiting. Any alterations and modifications of some of the disclosed embodiments, and any further applications of the principles disclosed in this document, as would normally occur to one of ordinary skill in the pertinent art, fall within the scope of this disclosure.

Further, it is understood that several processing steps (e.g., operations) and/or features of a device may be briefly described. Also, additional processing steps and/or features can be added, and certain of the processing steps and/or features described herein can be removed or changed while implementing the methods described herein or while using the systems and devices described herein. Thus, the following description should be understood to represent examples, and are not intended to suggest that one or more steps or features are required for every implementation. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

FIG. 1is a schematic top view of an electronic device package1in accordance with some embodiments of the present disclosure, andFIG. 1Ais a schematic cross-sectional view of an electronic device package1along a line A-A′ in accordance with some embodiments of the present disclosure. As shown inFIG. 1andFIG. 1A, the electronic device package1includes a substrate10, a first component layer20and a second component layer30. The substrate10includes a first surface101, and a second surface102opposite to the first surface101. The substrate10may include an interposer, a circuit layer such as a redistribution layer (RDL) or another type of substrate that includes embedded circuitry between the first surface101and the second surface102. The first surface101of the substrate10includes a first region10A and a second region10B. The device area density of the first region10A is greater than the device area density of the second region10B. As used herein, the device area density may be referred to a ratio of an area of device(s) disposed in a region of the substrate to an overall area of the region. The device may be referred to an electronic component such as an active electronic device including a semiconductor die, a passive electronic device such as a capacitor, a resistor or an inductor, an electrical terminal such as a pad or a UBM. In some embodiments, the first region10A is adjacent to a corner of the substrate20.

The first surface101may include a plurality of electrical terminals including a first region10A and a second region10B. In some embodiments, the substrate10further comprises a plurality of first electrical terminals10C1in the first region10A, and a plurality of second electrical terminals10C2in the second region10B. The first electrical terminals10C1and the second electrical terminals10C2are electrically connected to the embedded circuitry of the substrate10. By way of example, the first electrical terminals10C1and the second electrical terminals10C2may be pads such as bonding pads disposed in the first region10A and the second region10B, respectively. In some embodiments, an electrical terminal density of the first electrical terminals10C1is greater than an electrical terminal density of the second electrical terminals10C2. As used herein, the electrical terminal density may be referred to a ratio of an area of the electrical terminals disposed in a region of the substrate to an overall area of the region. In this embodiment, the ratio of the area of the first electrical terminals10C1in the first region10A is greater than the ratio of the area of the second electrical terminals10C2in the first region10B. In some embodiments, a pitch P1of the first electrical terminals10C1of the first region10A is smaller than a pitch P2of the second electrical terminals10C2of the second region10B.

The first component layer20is disposed over the first surface101of the substrate10. The first component layer20comprises a first electronic component22electrically connected to the substrate10and at least over the first region10A. In some embodiments, the first electronic component22includes an active electronic device such as a semiconductor die. The first electronic component22may further includes a plurality of conductive structures22C electrically connected to the first electrical terminals10C1of the first region10A. In some embodiments, the first component layer20may further include a second electronic component24over the second region10B. The electrical terminal density of the first electronic component22is greater than the electrical terminal density of the second electronic component24. For example, the second electronic component24includes a passive electronic component such as a resistor, a capacitor, an inductor or a combination thereof. The second electronic component24may further include a plurality of conductive structures24C electrically connected to the second electrical terminals10C2of the second region10B. By way of example, the conductive structures22C and24C may include conductive studs, conductive pillars, solder bumps, solder pastes, solder balls or a combination thereof.

The second component layer30is disposed over the first component layer20and farther from the substrate10than the first component layer20. In other words, the first component layer30is disposed between the substrate10and the second component layer30. The second component layer30includes at least one electrical element32having a plurality of input/output (I/O) terminals32C away from the first component layer20. In some embodiments, the at least one electrical element32may include an active electrical element32A and/or a passive electrical element32B. The at least one electrical element32is without overlapping the first electronic component22in a direction D1substantially perpendicular to the first surface101and under the first surface101. The at least one electrical element32may overlap the second electronic component24in the direction D1. In some embodiments, the second component layer30may include a plurality of electrical elements32, and an electrical element32of the electrical elements32proximal to the first electronic component22is without overlapping the first electronic component22in the direction D1. That is, all electrical elements32are without overlapping the first electronic component22in the direction D1. In some embodiments, a number of the electrical element32under the first region10A is less than a number of the electrical element32under the second region10B. In some embodiments, an area of the electrical element32under the first region10A is less than an area of the at least one electrical element32under the second region10B.

The electronic device package1may further include a first encapsulation layer14over the first region10A and the second region10B and encapsulating the first component layer20and the second component layer30. By way of examples, the first encapsulation layer14encapsulates the first electronic component22and the second electronic component24of the first component layer20, and the at least one electrical element32of the second component layer30. In some embodiments, a surface of the first encapsulation layer14and a surface of the second component layer30are substantially coplanar. The I/O terminals32C of the electrical element32are exposed from the first encapsulation layer14to electrically connect to an external electrical component (not shown) such as a printed circuit board (PCB). The first encapsulation layer14may include molding compound such as epoxy-based material (e.g. FR4), resin-based material (e.g. Bismaleimide-Triazine (BT), Polypropylene (PP)) or other suitable materials.

The electronic device package1may further include a plurality of electrical connection elements36electrically connected to the substrate10, and extending through the first component layer20and the second component layer30. In some embodiments, the electrical connection elements36may include conductive pillars36P such as copper pillars, and electrical terminals36C partially embedded in the first encapsulation layer14and exposed from an outer surface14S of the first encapsulation layer14to electrically connect to the external electrical component. The electrical connection elements36are not disposed over the first region10A. In some embodiments, the electrical connection elements36may be disposed over the second region10B, or over other region of the substrate10. By way of example, the electrical connection elements36are disposed to at least one edge10E of the substrate10.

The defect detectability in and/or under the first region10A is higher than the defect detectability in and/or under the second region10B. As used herein, the defect detectability may be referred to the ability of detecting defect. A higher defect detectability means the defect is easier to be detected, and a lower defect detectability means the defect is more difficult to be detected. By way of example, the defect detectability may include void detectability, i.e., the ability of detecting void defect. In the proximity of the high device density first region10A, defects such as void defects tends to appear, and thus a higher defect detectability is required. In the proximity of the low device density second region10B, defects are less likely to occur, and thus the requirement of defect detectability near the second region10B may not be as important as the requirement of defect detectability near the first region10A.

In some embodiments, the second component layer30defines a clearance region30C over the first region10A. The clearance region30C overlaps the first electronic component22in the direction D1. As used herein, the clearance region30C of the second component layer30may be referred to a region that allows detecting the first encapsulation layer14between the first electronic component22and the first region10A of the substrate10to check if voids defects of the first encapsulation layer14appear. In some embodiments, the first encapsulation layer14is disposed in the clearance region30C, i.e., the clearance region30C may be a portion of the first encapsulation layer14in the absence of other electronic components. In some other embodiments, the clearance region30C of the second component layer30may be a recessed region of the first encapsulation layer14. The clearance region30C allows acoustic wave to pass through such that voids of the first encapsulation layer14in a tiny gap between the substrate10and the first electronic component22can be detected.

In some embodiments, the substrate10may further include a plurality of third electrical terminals10C3exposed from the second surface102, and electrically connected to the embedded circuitry of the substrate10. The electronic device package1may further include at least one third electronic component42disposed over the second surface102of the substrate10, and electrically connected to the substrate10through the third electrical terminals. For example, the at least one third electronic component42includes one or more active electronic components42A such as application specific integrated circuit (ASIC) dies, memory dies or a combination thereof, and one or more passive electronic component42B such as resistors, capacitors, inductors or a combination thereof. The electronic device package1may further include a second encapsulation layer44over the second surface102of the substrate10, and encapsulating the at least one third electronic component42. The second encapsulation layer44may include molding compound such as epoxy-based material (e.g. FR4), resin-based material (e.g. Bismaleimide-Triazine (BT), Polypropylene (PP)) or other suitable materials.

The stack of the first component layer20and the second component layer30increases the device integration of the electronic component device package1. The clearance region30C of the second component layer30allows to perform a detection such as a scan acoustic tomography (SAT) detection to detect mold void in the first encapsulation layer14, particularly in the tiny space between the first electronic component22and the substrate10where mold voids tend to occur. Accordingly, the reliability of the electronic component device package1can be improved.

The electronic device packages and manufacturing methods of the present disclosure are not limited to the above-described embodiments, and may be implemented according to other embodiments. To streamline the description and for the convenience of comparison between various embodiments of the present disclosure, similar components of the following embodiments are marked with same numerals, and may not be redundantly described.

FIG. 2is a schematic top view of an electronic device package2in accordance with some embodiments of the present disclosure, andFIG. 2Ais a schematic cross-sectional view of an electronic device package2along a line B-B′ in accordance with some embodiments of the present disclosure. As shown inFIG. 2andFIG. 2A, in contrast to the electronic device package1, the substrate10includes a plurality of first electrical terminals10C1in the first region10A, and the second region10B is free of electrical terminal. By way of example, the second region10B may be disposed between two first regions10A, or surrounded by a first region10A. The first electronic component22may be disposed over both the first region10A and the second region10B. The first electronic component22further comprises a plurality of conductive structures22C electrically connected to the first electrical terminals10C1of the first region10, and the second region10B is free of conductive structure of the first electronic component22and electrical terminals of the substrate10. The second component layer30defines one or more clearance regions30C over the first region10A. The at least one electrical element32may overlap the first electronic component22in the direction D, but may be without overlapping the clearance regions30C in the direction D. The device area density of the first region10A is greater than the device area density of the second region10B. By way of example, there are the first electrical terminals10C1in the first region10A, and there are no electrical terminals in the second region10B. Accordingly, the electrical terminal density of the first region10A is greater than zero, and the electrical terminal density of the second region10B is zero.

FIG. 3is a schematic top view of an electronic device package3in accordance with some embodiments of the present disclosure, andFIG. 3Ais a schematic cross-sectional view of an electronic device package3along a line C-C′ in accordance with some embodiments of the present disclosure. As shown inFIG. 3andFIG. 3A, in contrast to the electronic device package2, the substrate10includes a plurality of first electrical terminals10C1in the first region10A, and a plurality of second electrical terminals10C2in the second region10B. The first electronic component22may be disposed over both the first region10A and the second region10B. The first electronic component22further includes a plurality of first conductive structures22C1electrically connected to the first electrical terminals10C1of the first region10A, and a plurality of second conductive structures22C2electrically connected to the second electrical terminals10C2of the second region10B. The device area density of the first region10A is greater than the device area density of the second region10B. By way of example, there are the first electrical terminals10C1in the first region10A, and the second electrical terminals10C2in the second region10B. The density of the first electrical terminals10C1is greater than the density of the second electrical terminals10C2. Accordingly, the electrical terminal density of the first region10A is greater than the electrical terminal density of the second region10B.

FIG. 4A,FIG. 4B,FIG. 4C,FIG. 4D,FIG. 4E.FIG. 4F,FIG. 4GandFIG. 4Hillustrate operations of manufacturing an electronic device package in accordance with some embodiments of the present disclosure. As shown inFIG. 4A, a substrate10is provided. The substrate10includes a first surface101, and a second surface102opposite to the first surface101. The first surface101has a first region10A and a second region10B. The device area density of the first region10A is greater than the device area density of the second region10B. In some embodiments, the substrate10comprises a plurality of first electrical terminals10C1in the first region10A, and a plurality of second electrical terminals10C2in the second region10B, and the electrical terminal density of the first electrical terminals10C1is greater than the electrical terminal density of the second electrical terminals10C2. In some other embodiments, the substrate10includes a plurality of first electrical terminals10C1in the first region10A, and the second region10B is free of electrical terminal. In some embodiments, electronic components (also referred to as third electronic components)42may be mounted on the second surface102of the substrate10, and electrically connected to the third electrical terminals10C3of the substrate10.

As shown inFIG. 4B, first electronic component(s)22may be bounded to the first region10A. By way of example, the first electronic component(s)22may be bounded to the first electrical terminals10C1of the substrate10through conductive structures22C. Second electronic component(s)24may be bonded to the second region10B. For example, the second electronic component(s)24may be bonded to the second electrical terminals10C2of the substrate10through conductive structures24C. In some embodiments, a plurality of electrical connection elements36may be mounted on the first surface101of the substrate10.

As shown inFIG. 4C, an electrical element32is suspended over the surface of the substrate without overlapping the first region10A. In some embodiments, the electrical element32is temporarily supported by a carrier60. The carrier60may be temporarily adhered to the electrical connection elements36, and the location of the electrical element32supported by the carrier60is selected such that the electrical element32is without overlapping the first region10A.

As shown inFIG. 4D, a first encapsulation layer14is formed on the first surface101of the substrate10to encapsulate the first electronic component22and the electrical element32. In some embodiments, a second encapsulation layer44is formed on the second surface102of the substrate10to encapsulate the third electronic components42. In some embodiments, the first encapsulation layer14and the second encapsulation layer44may include the same molding compound, and formed by the same molding process. Because the electrical element32suspended over the first surface101of the substrate10is without overlapping the first region10A, a clearance region30C is formed over the first region10A.

As shown inFIG. 4E, the carrier60is released from the first encapsulation layer14and the electrical connection elements36. Subsequently, a singulation process is performed to form a plurality of electronic device packages1,2or3as illustrated inFIG. 1, 2 or 3. As shown inFIG. 4F, a detection is performed through the clearance region30C and the first electronic component22to detect the first encapsulation layer14between the first electronic component22and the first region10A of the substrate10. In some embodiments, the detection comprises an acoustic detection such as a can acoustic tomography (SAT) detection. In the SAT detection, an acoustic detection apparatus80can be used to transmit acoustic wave80W through the clearance region30C and the first electronic component22along a scanning direction D2to detect whether mold voids exist between the tiny space between the first electronic component22and the first region10A. The reflected acoustic wave80W can be sensed and analyzed to confirm whether mold voids exist between the tiny space between the first electronic component22and the first region10A or not. In some embodiments, the clearance region30C may be a portion of the first encapsulation layer14in which electronic component or other structures that impedes traveling of the acoustic wave80W is avoided. Accordingly, the detection can be performed.

As shown inFIG. 4G, the electronic device package may be bonded to an external electrical component62such as a printed circuit board (PCB). The I/O terminals32C of the electrical element32and/or the electrical terminals36C of the electrical connection elements36may be electrically connected to pads62C of the external electrical component62. In some alternative embodiments, the electronic device package may be bonded to the external electrical component62through electrical connectors66such as solder paste, solder paste or the like as illustrated inFIG. 4H. The electrical connectors66may be disposed between the first encapsulation layer14and the external electrical component62, and a space gap may exist therebetween.

FIG. 5is a schematic top view of an electronic device package4in accordance with some embodiments of the present disclosure. As shown inFIG. 5, in contrast to the electronic device package1, the clearance region30C is an empty space defined by the second component layer30. The clearance region30C is a recessed region of the first encapsulation layer14. The clearance region30C allows acoustic wave to pass through such that voids of the first encapsulation layer14in a tiny gap between the substrate10and the first electronic component22can be detected. In some embodiments, other electrical components may be disposed in the clearance region30C after the detection process to increases the device integration of the electronic component device package4.

FIG. 6A,FIG. 6B,FIG. 6CandFIG. 6Dillustrate operations of manufacturing an electronic device package in accordance with some embodiments of the present disclosure. As shown inFIG. 6A, a carrier60including a protrusion portion60P is used to temporarily support the electrical connection elements36. Subsequently, a molding process is performed to form a first encapsulation layer14and the second encapsulation layer44. By virtue of the protrusion portion60P, a clearance region30C formed by a recess of the first encapsulation layer14can be formed subsequent to the carrier60is removed as shown inFIG. 6B.

As shown inFIG. 6C, a detection such as a SAT detection is performed through the clearance region30C and the first electronic component22to detect the first encapsulation layer14between the first electronic component22and the first region10A of the substrate10. In some embodiments, the clearance region30C being a recess portion of the first encapsulation layer14does not impede traveling of the acoustic wave, and accordingly the detection can be performed.

As shown inFIG. 6D, the electrical terminals36C of the electrical connection elements36may be bonded to an external electrical component62such as a printed circuit board (PCB). Electrical components32may be mounded on the external electrical component62in advance. After the electrical terminals36C of the electrical connection elements36is bonded to the external electrical component62, the electrical components32is disposed in the clearance region30C, and the device integration of the electronic component device package4can be improved.

In some embodiments of the present disclosure, the electronic device package is a three-dimensional (3D) stacking electronic device package including a substrate and a plurality of electronic components stacked on the substrate. The 3D stacking electronic device package includes one or more suspended electrical elements that do not overlap a joint region between a high-density electronic component and the substrate, and thus a molding condition in the joint region where mold voids tend to occur can be detected. Accordingly, the reliability of 3D stacking structure can be improved.

In the description of some embodiments, a component provided or disposed “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical or direct contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.