Low voltage drop cascaded synchronous bootstrap supply circuit

A cascaded synchronous bootstrap supply circuit with reduced voltage drop between the cascaded bootstrap capacitors by replacing bootstrap diodes with gallium nitride (GaN) transistors. GaN transistors have a much lower forward voltage drop than diodes, thus providing a cascaded gate driver bootstrap supply circuit with a reduced drop in bootstrap capacitor voltage, which is particularly important as the number of levels increases.

BACKGROUND

Power supplies and power converters are used in a variety of electronic systems. Electrical power is generally transmitted over long distances as an alternating current (AC) signal. The AC signal is divided and metered as desired for each business or home location, and is often converted to direct current (DC) for use with individual electronic devices or components. Modern electronic systems often employ devices or components designed to operate using different DC voltages.

One type of power converter is referred to as a multi-level converter because more than two voltage levels are used to generate an output voltage. As a general rule, multi-level converters step-up to or step-down from a certain voltage using smaller discrete stages. There are numerous multi-level converter topologies, where different topologies vary with regard to efficiency, complexity, and ease of miniaturization (e.g., forming a multi-level converter using integrated circuits). In some examples, a multi-level converter includes a network of switches and capacitors, as well as a control mechanism for the switches. When the switches are power transistors, the control circuit can be referred to as a gate driver circuit, which can be a discrete circuit, a partially integrated circuit, or a fully integrated circuit (IC).

FIG. 1shows a prior art cascaded bootstrap gate driver circuit for a multi-level converter. In the multilevel converter ofFIG. 1, QTN, QT2, QT1, and QLare power transistors; DBN, DB2, DB1are bootstrap diodes; RDBN, RDB2, RDB1are bootstrap resistors; CBN, CB2, CB1are bootstrap capacitors; and VDR is the gate driver power supply voltage (e.g., 5 V inFIG. 1); CD is a decoupling capacitor(s); D1-DNare non-ground referenced gate drivers; DLis a ground referenced gate driver that does not require level shift or bootstrapping; and VBUSis the power supply voltage source.

The operation of the cascaded gate driver circuit ofFIG. 1includes various charging periods represented by dashed loops102,104, and106. In charging period 1, QLis on and CB1is charged by VDRto VCB1≈VDR−VDB1−VRDB1≈4.5 V (assuming VRDBX≈0 V and VDBX≈0.5 V). In charging period 2, QT1is on and CB2is charged by CB1to VCB2≈VCB1−VDB2−VRDB2≈4.0 V. In charging period N, QTN-1is on and CBNis charged by CBN-1to VCBN≈VCBN-1−VDBN−VRDBN≈VDR−N(VRDBN+VDBN). If N=3, VCB3≈3.5 V. If N=4, VCB≈3.0 V. For the gate driver circuit ofFIG. 1, a diode drop occurs during each charging period. Thus, as the number of levels increases, the subsequent bootstrap capacitor voltage in the charging sequence decreases. This drop in voltage in each subsequent stage limits the number of levels that can be supported. Accordingly, a need exists for a cascaded bootstrap supply circuit with a reduced voltage drop between the cascaded bootstrap capacitors.

SUMMARY OF THE INVENTION

The present invention overcomes the above-noted deficiencies of the prior art by providing a cascaded synchronous bootstrap supply circuit with reduced voltage drop between the cascaded bootstrap capacitors by replacing the bootstrap diodes of prior art circuits with gallium nitride (GaN) transistors. GaN transistors have a much lower forward voltage drop than diodes, can be made to support higher voltages, and have no reverse recovery, thus providing a cascaded gate driver bootstrap supply circuit with a reduced drop in bootstrap capacitor voltage, which is particularly important as the number of levels increases.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention is directed to low voltage drop synchronous cascaded bootstrap supply circuits for multi-level DC-DC power converters. The circuit of the present invention comprises a plurality of cascaded gate driver control loops, each loop having a gallium nitride (GaN) transistor, a bootstrap capacitor, and a driver stage configured to selectively couple and decouple an adjacent control loop. In operation, each drive control loop is configured to selectively drive a separate power transistor (e.g., in a multi-level converter or switched-capacitor converter). More specifically, each drive control loop is configured to drive a separate power transistor in a sequence. In at least some embodiments, each drive stage comprises a controller, level shift logic, and complementary switches to follow the desired sequence.

In some embodiments, the GaN transistors used in the drive control loops are enhancement mode transistors. As used herein, “enhancement mode” transistors refer to transistors that are normally “off”, where a positive voltage applied to the transistor gate is used to turn the transistor “on”. In other embodiments, the GaN transistors used for the drive control loops are depletion mode transistors. As used herein, “depletion mode” transistors refer to transistors that are normally “on”, where a negative voltage applied to the transistor gate is used to turn the transistor “off”.

Further, most of the drive control loops are non-ground referenced loops while one drive control loop is a ground referenced loop. Specifically, the cascaded bootstrap supply circuit of the present invention comprises a base drive control loop that is a ground referenced loop, where the base drive control loop comprises a bootstrap capacitor, a diode, a resistor, and a drive stage configured to selectively couple and decouple an adjacent drive control loop.

In different embodiments, various components are included or omitted for one or more of the drive control loops. More specifically, in some embodiments, each bootstrap capacitor is coupled to a current terminal of a respective GaN transistor via a resistor. Also, in some embodiments (e.g., where the GaN transistors are enhancement mode transistors), a bootstrap diode and an auxiliary bootstrap capacitor (e.g., bootstrap FET drive capacitor) are included in each drive control loop and are coupled to a gate terminal of a respective GaN transistor. In other embodiments (e.g., where the GaN transistors are depletion mode transistors), the bootstrap diode and auxiliary bootstrap capacitor for each drive control loop is omitted. In some embodiments (e.g., in designs requiring more accurate control of the bootstrap capacitor voltages), one or more of the drive control loops includes a voltage regulator. The voltage regulator comprises a linear dropout (LDO) regulator or a switched-mode power supply. In some embodiments (e.g., in designs requiring protection and/or more accurate control of the bootstrap capacitor voltages), each drive control loop includes a Zener diode in parallel with a respective bootstrap capacitor.

In different embodiments, the circuit of the present invention comprises discrete components (e.g., components mounted on a printed circuit board (PCB)). Additionally or alternatively, is some embodiments, the circuit comprises integrated circuit components. In one example, the entire circuit is a single integrated circuit. In another example, the circuit is formed of multiple integrated circuits that are coupled together. To provide a better understanding, various circuit details, options, and scenarios are described with reference to the figures as follows.

FIG. 2shows a block diagram of an electrical system200in accordance with the present invention. As shown, the electrical system200comprises a low voltage drop synchronous cascaded bootstrap gate driver circuit202having a plurality of drive control loops204A-204N with respective GaN power transistors206A-206N, bootstrap capacitors208A-208N, and drive stages210A-210N. For each of the drive control loops204A-204N, there is a voltage differential. More specifically, the voltage differential for the drive control loop204A is provided by voltage levels V1+ and GND, the voltage differential for the drive control loop204B is provided by voltage levels V2+ and V2−, and so on. The drive control loop204A is a ground referenced loop, and the other drive control loops204B-204N are non-ground referenced loops (i.e., V2− to VN− are not the same as GND). In different embodiments, each of the drive control loops204A-204N also comprises other component(s)212A, such as a resistor, a bootstrap diode, an auxiliary bootstrap capacitor, a voltage regulator, and/or a Zener diode. In some embodiments, different one of the drive control loops204A-204N vary with regard to at least some of their respective components.

The electrical system200also comprises a voltage converter220coupled to the gate driver circuit202. The converter220may be a multi-level converter or more specifically, a switched-capacitor converter. More specifically, the converter220includes a plurality of switches224A-224N (e.g., power transistors) coupled to a respective drive control loop204A-204N of the gate driver circuit202. The converter220includes capacitor(s)226that is charged or discharged based on the operation of the switches224A-224N. In some embodiments, the number of capacitors226varies relative to the number of switches224A-224N. For example, in some embodiments, different sets of the switches224A-224N provide charge to a given capacitor. Also, in some embodiments, the converter220includes other component(s)228. The output of the converter220is provided to one or more loads230.

In some embodiments, the voltages of the flying capacitors in the multi-level converter220need to be balanced, i.e. maintained within a specified voltage range related to a specific ratio of the main supply voltage. To provide this balance, a controller227may be included in the converter220. With the controller227, voltage balancing for the flying capacitors (e.g., the capacitor(s)226correspond to flying capacitors in some embodiments) is possible. InFIG. 2, the controller227is represented as being part of the multi-level converter200. In other embodiments, the controller227is part of the gate driver circuit202.

FIG. 3shows a synchronous cascaded bootstrap gate driver circuit300in accordance with the present invention. Circuit300is an example of the gate driver circuit202inFIG. 2. As shown, circuit300includes a representation of the drive control loops204A-204N ofFIG. 2with respective GaN power transistors206A-206N (e.g., FETs labeled QBST1-QBSTN), bootstrap capacitors208A-208N (labeled CB1-CBN), and drive stages210A-210N. Each of the drive control loops204A-204N is configured to selectively provide a gate drive signal to a respective switch224A-224N (e.g., power transistors labeled QTLand QT1-QTNinFIG. 3) using the drive stages210A-210N.

FIG. 4shows an example of a drive stage400. The drive stage400ofFIG. 4corresponds to each of the drive stages210B-210N. As shown, the drive stage400comprises a level shift402, an AND gate404, complementary switches406and408, and a controller410. The controller410is a pulse width modulator and/or other logic to provide a drive signal to the level shift402. The output of the level shift402is input to the AND gate404along with a control signal (CSPROT) that provides protection as needed. For example, if there is a system error, CSPROTwill be low and the drive stage400will not provide a signal to the complementary switches406and408. Otherwise, CSPROTwill be high, allowing gate drive operations. The drive stage210A ofFIG. 3includes two sets of the components represented for the drive stage400ofFIG. 4, where one of the sets omits the level shift. Drive stages, such as the drive stage400, can be implemented in numerous variations and thus the drive stage400should not be interpreted as limiting embodiments to a particular drive stage topology.

Returning toFIG. 3, circuit300also includes other components (e.g., corresponding to the other components212A-212N inFIG. 2), such as bootstrap resistors (labeled RDB1-RDBN), bootstrap diodes (labeled DBST1-DBSTN), bootstrap FET drive capacitors (labeled CBST1-CBSTN, and sometimes referred to as auxiliary bootstrap capacitors herein), and a decoupling capacitor (labeled Co). InFIG. 3, the voltage differential for the drive control loop204A is provided by a gate driver power supply, VDR(an example of V1+ inFIG. 2), and GND. Another power supply, VBUS, is a power supply for converter circuit220and is shown as being input to a current terminal of QTN.

Relative to the prior art circuit ofFIG. 1, the circuit300ofFIG. 3uses active GaN transistors (QBST1-QBSTN) instead of bootstrap diodes (DB1-DBN). InFIG. 3, the GaN transistors are enhancement mode transistors, and each GaN transistor forms a network with a respective diode (one of DBST1-DBSTN) and bootstrap FET drive capacitor (one of CBST1-CBSTN). In operation, the drive control loops204A-204N are configured to drive respective switches224A-224N in a sequence. In charging period #1, when QLis on, CB1is charged by VDRto a value VCB1, with this being the drive stage with a ground reference,204A. For example, if VRDBX≈0 V and VBSTX≈0.2 V, then VCB1≈VDR−VBST1−VRDB1≈4.8 V. In charging Period #2 (represented by drive control loop204B), when QT1is on, CB2is charged by CB1to VCB2without a ground reference. For the example values given for charging period #1, VCB2≈VCB1−VBST2−VRDB2≈4.6 V. For cascaded charging Period # N, when QTN-1is on, CBNis charged by CBN-1to VCBN, where VCBN≈VCBN-1−VBSTN−VRDBN≈VDR−N(VRDBN+VDBN). For the example values given herein, if N=3, VCB3≈4.4 V. If N=4, VCB4≈4.2 V, and so on. For the charging sequence, charging begins at the lowest level (CB1is charged first) and moves upward.

More specifically, each of drive control loops204B-204N has an “off” state and an “on” state. For example, for the drive control loop204B, when QTN-1(QT1inFIG. 3) is in the off state, CBN-1(CB1inFIG. 3) will forward bias DBSTN(DBST2inFIG. 3) and charge CBSTN(CBST2inFIG. 3) to VCBN-1−VDBSTN. When QTN-1(QT1inFIG. 3) is in the on state, QBSTN(QBST2inFIG. 3) is driven on by CBSTN(CBST2inFIG. 3) and CBN(CB2inFIG. 3) will be charged by the lower level bootstrap capacitor CBN-1(CB1inFIG. 3). Because of the lower voltage drop on an active GaN power transistor (QBST), the voltage difference between VCBNand VCBN-1will be significantly reduced compared to prior art techniques. This sequence repeats to drive N levels of stacked GaN power transistors.

Relative to the prior art circuit ofFIG. 1, actively controlled low voltage drop cascaded bootstrap devices (QBST1-QBSTN) significantly reduce voltage drop in cascaded bootstrap circuitry. This enables a higher number (N) of levels than the prior art circuit ofFIG. 1without complicated circuitry to account for large voltage drops. Also, the cascaded circuitry provides a minimalistic electrical loop and inductance path for charging the bootstrap capacitor at a desired level (e.g., by using the single power transistor immediately below a given loop). In other words, each bootstrap capacitor (e.g., CBX, where x is 1 to N−1) charges through a power transistor below a given loop (e.g., QT(X-1), where x is 1 to N−1). This ensures that none but the lowest bootstrap capacitor (CB1) charges using GND, resulting in a consistent electrical charging path. The cascaded circuits described herein can be used for any stacked or hybrid stacked topology, since each bootstrap capacitor (e.g., CB1-CBN) only needs the power transistor (e.g., QTL, QT1−QTN-1) immediately below it (in the previous loop) to turn on in order to charge itself.

FIG. 5shows a schematic diagram of a three-level flying capacitor circuit500(the circuit500is an example of the circuit300ofFIG. 3, where N=3) in accordance with the present invention. InFIG. 5, many of the same components described for the circuit300inFIG. 3are represented along with a flying capacitor (labeled CFLY1) that is charged based on the operation of the drive control circuit components inFIG. 5. In some embodiments, a controller (see e.g., controller227inFIG. 2) is included with the circuit500to balance the voltage of the flying capacitor (labeled CFLY1inFIG. 5, and which is an example of the capacitor(s)226inFIG. 2) in the circuit500.

FIG. 6shows a timing diagram600for the three-level flying capacitor circuit500ofFIG. 5in accordance with various embodiments. More specifically, the timing diagram600shows the gate-to-source voltage (VGS) for different transistors as a function of time. As shown, the VGSfor QBST1includes an interval in “high” state and a second interval in a “low” state, repeating every period Ts. Meanwhile, the VGSfor QBST2includes an interval in low state and a second interval in a high state, repeating every period Ts. In the timing diagram600, the VGSwaveforms for QBST1and QBST2are shifted versions of each other, where the low states do not overlap. Meanwhile, the VGSfor QBST3includes an interval in high state and a second interval in a low state repeating every period Ts. As shown, the high states for the VGSof QBST3occur during low states for the VGSof QBST2, with some offset between transitions for the VGSof QBST3and the VGSof QBST2(i.e., the VGSof QBST3is nearly an inverted version of the VGSof QBST2with some offset between their respective transitions). Meanwhile, the VGSfor QT1matches the VGSfor QBST2, the VGSfor QT2matches the VGSfor QBST3, and the VGSfor QTLmatches the VGSfor QBST1. As shown, the high states for the VGSof QT3occur during low states for the VGSof QTLand QBST1with some offset between transitions for the VGSof QT3and transitions for the VGSof QTLor QBST1(i.e., the VGSof QT3is nearly an inverted version of the VGSof QBST1or QBST1with some offset between their respective transitions).

FIGS. 7A and 7Bshow graphs700and710comparing voltage levels for a prior art cascaded bootstrap supply circuit versus the cascaded bootstrap supply circuit of the present invention. For the graph700ofFIG. 7A, various values are assumed for VDR, a switching frequency (fsw), a duty cycle (D), VIN, and IOUT. More specifically, VDR=5 V, fsw=500 kHz, D=20%, VIN=0 V, and IOUT=0 A. As shown, graph700includes a waveform702for Vgs(QTL)(e.g., the gate-to-source voltage for QTLinFIG. 1) that transitions between 0 and approximately 5.0 V, a waveform704for Vgs(QT1)(e.g., the gate-to-source voltage for QT1inFIG. 1) that transitions between 0 and approximately 4.3 V, and a waveform706for Vgs(QT2)(e.g., the gate-to-source voltage for QT2inFIG. 1) that transitions between 0 and approximately 3.51 V. Waveform708for Vgs(QT3)(e.g., the gate-to-source voltage for QT3inFIG. 1) remains at 0 V, this is due to an unsuitably low capacitor voltage on CB3, measured to be approximately 2.8 V, triggering the drive stage,400, protection logic,404, keeping the gate low in an under-voltage lockout (UVLO) protection mode.

For graph710ofFIG. 7B, the same assumed values noted for graph700are used. Again, VDR=5 V, fsw=500 kHz, D=20%, VIN=0 V, and IOUT=0 A. As shown in graph710, a waveform712for Vgs(QTL)(the gate-to-source voltage for QTLinFIG. 5) is represented, where the waveform712transitions between 0 and 5.03 V. Meanwhile, a waveform714for Vgs(QT3)(the gate-to-source voltage for a power transistor QT3inFIG. 5) is represented, where the waveform714transitions between 0 and 4.48 V, allowing safe operation, with an approximately 1.7 V higher capacitor voltage on CB3than in the prior art discussed above. As shown in graphs700and710, the cascaded bootstrap supply circuit of the present invention (e.g., circuit300ofFIG. 3.) can support more stages with a lower voltage drop compared to the prior art circuit ofFIG. 1.

FIG. 8shows a schematic diagram of a four-level flying capacitor circuit800(the circuit800is an example of the circuit300ofFIG. 3, where N=5) in accordance with the present invention. InFIG. 8, many of the same components described for the circuit300inFIG. 8are represented along with two flying capacitors (labeled CFLY1and CFLY1) that are charged based on the operation of the circuit components inFIG. 8. It should be noted that one of benefits of cascaded operations using GaN transistors as described herein (see e.g.,FIGS. 3, 5, and 8) is that higher frequency converters are supported compared to using linear dropout regulators (LDOs) to provide higher voltages.

In some embodiments, a controller (see e.g., the controller227inFIG. 2) is included with the circuit800to balance the voltage of the capacitors in the circuit800. As an example, such a controller may balance the voltage of the flying capacitors (labeled CFLY1and CFLY2inFIG. 8, and which are an example of the capacitor(s)226inFIG. 2) in the circuit800.

FIG. 9shows a timing diagram900for the four-level flying capacitor circuit800ofFIG. 5. More specifically, the timing diagram900shows the VGSfor different transistors as a function of time. As shown, the VGSfor QBST1includes an interval in high state and a second interval in a low state, repeating every period Ts. Meanwhile, the VGSfor QBST2includes an interval in low state and a second interval in a high state, repeating every period Ts. Also, the VGSfor QBST3includes an interval in a high state and a second interval in a low state, repeating every period Ts. Also, the VGSfor QBST4includes an interval in low state and a second interval in a high state, repeating every period Ts. Also, the VGSfor QBST5includes an interval in high state and a second interval in a low state, repeating every period Ts.

In timing diagram900, the VGSwaveforms for QBST1, QBST2, and QBST3are shifted versions of each other, where the low states do not overlap. Meanwhile, the high states for the VGSof QBST4occur during low states for the VGSof QBST3, with some offset between transitions for the VGSof QBST4and transitions for the VGSof QBST3(i.e., the VGSof QBST4is nearly an inverted version of the VGSof QBST3with some offset between their respective transitions). Also, the high states for the VGSof QBST5occur during low states for the VGSof QBST2, with some offset between transitions for the VGSof QBST5and transitions for the VGSof QBST3(i.e., the VGSof QBST5is nearly an inverted version of the VGSof QBST2, with some offset between their respective transitions).

Meanwhile, the VGSfor QT3matches the VGSfor QBST4, and the VGSfor QT2matches the VGSfor QBST3. Also, the VGSfor QT4matches the VGSfor QBST5, and the VGSfor QT1matches the VGSfor QBST2. Also, the VGSfor QTLmatches the VGSfor QBST1. As shown, the high states for the VGSof QT5occur during low states for the VGSof QBST1with some offset between transitions for the VGSof QT5and transitions for the VGSof QBST1(i.e., the VGSof QT5is nearly an inverted version of the VGSof QBST1with some offset between their respective transitions).

FIGS. 10-13shows other cascaded bootstrap supply circuits1000,1100,1200,1300in accordance with various additional embodiments of the present invention. InFIG. 10, the circuit1000includes a plurality of drive control loops1004A-1004N with respective GaN transistors1006A-1006N, where the GaN transistors1006A-1006N are depletion mode transistors. With depletion mode transistors QBST1-QBSTN, various components (e.g., CBST1-CBSTNand DBST1-DBSTN) are not needed as compared to the circuit300ofFIG. 3.

InFIG. 11, circuit1100includes the plurality of drive control loops1004A-1004N with respective GaN transistors1006A-1006N corresponding to depletion mode transistors, where each of the drive control loops1004A-1004N couples to a respective voltage regulator1102A-1102N. Voltage regulators1102A-1002N may be linear dropout (LDO) regulators, or switched-mode power supplies. In operation, the voltage regulators1102A-1102N reduce the voltage variation of the different drive control loops1004A-1004N. Because the voltage variation for the drive control loops1004A-1004N is smaller compared to loops of the prior art circuit ofFIG. 1, the components and operations of circuit1100are simplified and lower circuit losses are achieved as compared to the prior art circuit ofFIG. 1. Voltage regulators1102A-1102N may be integrated with a respective one of the drive stages210A-210N, or provided as discrete components. This embodiment is also possible using normally off enhancement mode GaN transistors with the addition of the bootstrap diodes (DBST1-DBSTN) and the second bootstrap capacitors (CBST1-CBSTN).

InFIG. 12, the circuit1200include the plurality of drive control loops1004A-1004N with respective depletion mode GaN transistors1006A-1006N, where each of the drive control loops1004A-1004N includes a Zener diode1202A-1202N (labeled DZ1-DZN) in parallel with a respective one of the bootstrap capacitors208A-208N (CB1-CBN). In operation, Zener diodes DZ1-DZNreduce voltage variation of the different drive control loops1004A-1004N. Zener diodes DZ1-DZNmay be integrated with the drive stages210A-210N or provided as discrete components. With the significantly reduced bootstrap capacitor voltage variation compared to the prior art circuit ofFIG. 1, the lower overhead voltage regulation will significantly reduce Zener clamp requirements and circuit losses. This embodiment is also possible using normally off enhancement mode GaN transistors with the addition of the bootstrap diodes (DBST1-DBSTN) and the second bootstrap capacitors (CBST1-CBSTN).

InFIG. 13, the circuit1300includes a plurality of drive control loops including base drive control loop1302and upper drive control loops204B-204N. As shown inFIG. 13, the base drive control loop1302employs a bootstrap diode (labeled DB1) instead of a GaN transistor. In circuit1300, the lowest level requiring a bootstrap (in this example CB1for QT1) is charged conventionally through DB1when conduction directly to ground is possible. When a ground path is not possible or practical, the cascaded synchronous bootstrap is employed (CB2to CBNin this example), creating a partial/hybrid cascaded synchronous bootstrap arrangement where part of the bootstrapping is done conventionally and part is done through cascaded synchronous bootstrapping.

In some partial/hybrid cascaded synchronous bootstrap embodiments, the enhancement mode GaN transistors (QBST2-QBSTN) ofFIG. 13are replaced with depletion mode GaN transistors. With depletion mode GaN transistors, the bootstrap diodes (DBST1-DBSTN) and the second bootstrap capacitors (CBST1-CBSTN) used to create positive gate voltage signals in circuit1300are not needed.