Processing system with transport stream aggregation and methods for use therewith

A processing system includes a transport stream aggregator that receives a plurality of transport streams in a transport stream format and that generates an aggregated transport stream in response. The transport stream aggregator processes transport stream packets of the plurality of transport streams and replaces a packet synchronization field with a customized synchronization field. A processing device is configured to generate a processed video signal from the aggregated transport stream.

TECHNICAL FIELD OF THE DISCLOSURE

The present disclosure relates to processing of transport streams such as video transport streams.

DESCRIPTION OF RELATED ART

Video encoding has become an important issue for modern video processing devices. Robust encoding algorithms allow video signals to be transmitted with reduced bandwidth and stored in less memory. However, the accuracy of these encoding methods face the scrutiny of users that are becoming accustomed to greater resolution and higher picture quality. Standards have been promulgated for many encoding methods including the H.264 standard that is also referred to as MPEG-4, part 10 or Advanced Video Coding, (AVC). The video signal encoded by these encoding methods must be similarly decoded for playback on most video display devices. While this standard sets forth many powerful techniques, further improvements are possible to improve the performance and speed of implementation of such methods. Efficient and fast encoding and decoding of video signals is important to the implementation of many video devices, particularly video devices that are destined for home use.

The limitations and disadvantages of conventional and traditional approaches will become apparent to one of ordinary skill in the art through comparison of such systems with the present disclosure.

DETAILED DESCRIPTION

FIG. 1presents a pictorial representation of example devices11-16that can include a processing system100in accordance with an embodiment of the present disclosure. In particular, these example devices include digital video recorder/set top box11, television or monitor12, wireless telephony device13, computers14and15, personal video player16, or other devices that include a processing system100.

Processing system100will be described in greater detail in conjunction withFIGS. 2-14, including several optional functions and features.

FIG. 2presents a block diagram representation of a processing system100in accordance with an embodiment of the present disclosure. In particular, processing system100includes transport stream aggregator150, processing device120, memory device130and slave device140. While a particular architecture is shown, alternative architectures using direct connectivity between one or more modules and/or buses can likewise be implemented in accordance with the present disclosure. In an embodiment of the present disclosure, processing device120is implemented via a system on a chip integrated circuit. Further, processing system100can include one or more additional modules that are not specifically shown such as other slave devices140and/or other devices or modules.

Memory device130stores a plurality of routines to be executed by the processing device120, the TS aggregator150and/or the slave device140. These routines include software such as boot code, an operating system such as a Linux, Mac OS, MS Windows, Solaris or other operating system and/or one or more applications to be executed by the modules of processing system100. The memory device130optionally includes a register space144having a plurality of registers, buffer space and data space for each of the modules of processing system100and storage space for other data files, system data, drivers, utilities and other system programs, and other data. Memory device130may be a single memory device or a plurality of memory devices. Such a memory device can include a hard disk drive or other disk drive, read-only memory, random access memory, volatile memory, non-volatile memory, static memory, dynamic memory, flash memory, cache memory, and/or any device that stores digital information.

The processing device120can be implemented using a single processing device or a plurality of processing devices. Such a processing device may be a microprocessor, co-processors, a micro-controller, digital signal processor, microcomputer, central processing unit, field programmable gate array, programmable logic device, state machine, logic circuitry, analog circuitry, digital circuitry, and/or any device that manipulates signals (analog and/or digital) based on operational instructions that are stored in a memory, such as memory device130. Note that when the processing device120implements one or more of its functions via a state machine, analog circuitry, digital circuitry, and/or logic circuitry, the memory storing the corresponding operational instructions may be embedded within, or external to, the circuitry comprising the state machine, analog circuitry, digital circuitry, and/or logic circuitry.

In operation, the transport stream (TS) aggregator receives a plurality of video signals110as individual transport streams in one or more transport stream formats. TS aggregator150generates an aggregated transport stream in response to the video signals110. The processing device120is configured to generate a processed video signal from the aggregated transport stream.

Video signals110are formatted in accordance with a transport stream format such as H.264, MPEG-4 Part 10 Advanced Video Coding (AVC), high efficiency video coding (HEVC), VC-1 or other digital format such as a Moving Picture Experts Group (MPEG) format (such as MPEG1, MPEG2 or MPEG4), Quicktime format, Real Media format, Windows Media Video (WMV), Audio Video Interleave (AVI), high definition media interface (HDMI) or another digital video format, either standard or proprietary.

Video signals110can be generated in association with a set-top box, television receiver, personal computer, cable television receiver, satellite broadcast receiver, broadband modem, 3G transceiver, a broadcast satellite system, internet protocol (IP) TV system, the Internet, a digital video disc player, a digital video recorder, or other video device. In an embodiment, the video signals110can include a broadcast video signal, such as a television signal, high definition television signal, enhanced high definition television signal or other broadcast video signal that has been transmitted over a wireless medium, either directly or through one or more satellites or other relay stations or through a cable network, optical network or other transmission network. In addition, the video signal110can be generated from a stored video file, played back from a recording medium such as a magnetic tape, magnetic disk or optical disk, and can include a streaming video signal that is transmitted over a public or private network such as a local area network, wide area network, metropolitan area network or the Internet.

The processing device120is operable to decode, transrate, transcrypt, transcale and/or otherwise decode or transcode one or more of the video signals110from the aggregated transport stream. In operation, the processing device120operates in accordance with many of the functions and features of the H.264, MPEG-4 Part 10 Advanced Video Coding (AVC), HEVC, VC-1 or other digital format such as a Moving Picture Experts Group (MPEG) format (such as MPEG1, MPEG2 or MPEG4), VC-1 (SMPTE standard 421M), Quicktime format, Real Media format, Windows Media Video (WMV), Audio Video Interleave (AVI), high definition media interface (HDMI) or another digital video format, either standard or proprietary or other video format, to decode or transcode video signals110to form one or more processed video signals.

While not expressly shown, each of the video signals110can be generated by a separate tuner or demodulator that generates a corresponding transport stream as an output. Consider an example where the processing system100is implemented in a cable card, computer or set top box that supports the contemporaneous reception for two or more video signals. The transport stream aggregator150can generate a single aggregated transport stream232for transfer to the processing device120for either transcoding or decoding. While the processing device may need to re-separate these individual transport streams for processing, the creation of an aggregate transport stream232simplifies the interface between the transport stream aggregator and the processing device.

The slave device140can be an interface module to input the plurality of video signals110and/or output a processed video signal generated by processing device120. In accordance with these embodiments the slave device140can be a wireless transceiver that operates a WLAN, Bluetooth connection, infrared connection, wireless telephony receiver or other wireless data connection, or a wired modem or other network adaptors that uses a wired receiver or other device to receive a signal from a LAN, the Internet, cable network, telephone network or other network or from another device in accordance with an Ethernet protocol, a memory card protocol, USB protocol, Firewire (IEEE 1394) protocol, SCSI protocol, PCMCIA protocol, or other protocol either standard or proprietary. In examples of slave devices include encryption/decryption engines, arithmetic processing devices such as vector processing units or other arithmetic devices, other hardware accelerators or function specific devices, or other slave devices.

As discussed above, the memory device130stores a plurality of routines to be executed by the processing device120, the TS aggregator150and/or the slave device140. During initialization of the processing system100, the processing device120is booted based on a first routine of the plurality of routines. For example, the processing device120is booted by executing a self-initialization and retrieving the first routine from the memory device130. The processing device120further operates as a boot master to boot the transport stream aggregator150based on a second routine of the plurality of routines that includes the boot code for the transport stream aggregator150. In this embodiment, the processing device120boots the transport stream aggregator150by retrieving the second routine from the memory device130and by pushing the second routine to the transport stream aggregator150. The processing device120boots the slave device140by retrieving a third routine from the memory device130that includes the boot code for the slave device and by pushing the third routine to the slave device.

Further details regarding the operation of transport stream aggregator150and processing device120including several optional functions and features are presented in conjunction with examples discussed in association withFIGS. 3-6.

FIG. 3presents a block diagram representation of a transport stream aggregator150in accordance with an embodiment of the present disclosure. In this embodiment, the transport stream aggregator150supports a reduction in the total number of serial transport streams that are input to a transport stream processing device, such as processing device120. In particular, the transport stream aggregator150multiplexes a plurality of serial transport streams down to a single transport stream.

As shown, transport stream aggregator150includes a plurality of parallel processing paths, each corresponding to one of the plurality of transport streams represented by the video signals110. Each processing path includes a sync field substitution module200, a packet identifier (PID) replacement module210and a packet buffer220. In addition, the transport stream aggregator150includes a stream multiplex controller240and a multiplexer230.

In an embodiment, the elements of transport stream aggregator150are implemented via using a single processing device or a plurality of processing devices. Such a processing device may be a microprocessor, co-processors, a micro-controller, digital signal processor, microcomputer, central processing unit, field programmable gate array, programmable logic device, state machine, logic circuitry, analog circuitry, digital circuitry, and/or any device that manipulates signals (analog and/or digital) based on operational instructions that are stored in a memory. Note that when the transport stream aggregator150implements one or more of its functions via a state machine, analog circuitry, digital circuitry, and/or logic circuitry, the memory storing the corresponding operational instructions may be embedded within, or external to, the circuitry comprising the state machine, analog circuitry, digital circuitry, and/or logic circuitry.

In a mode of operation, each of the sync field substitution modules200process the transport stream packets of a corresponding transport stream and replaces a packet synchronization field with a customized synchronization field. In particular, the customized synchronization field includes a stream identifier (SID) that indicates one of the plurality of transport streams. Considering the example where MPEG transport streams are aggregated, the standard transport stream synchronization byte (0x47) is replaced by a unique stream identification byte in order to allow unique identification or SID/PID combinations. A programmable value may be implemented to enable the remapping of the synchronization byte on a stream-by-stream basis. The mapping can implement the following replacement based on functions of the packet ID values of the first packet PID0, and stream identifiers SIDj, where n<m.
{SID0(0x47/PID0)+SID1(0x47/PID0)}−>{SIDj(m/PID0)+SIDj(n/PID0)};
While a particular mapping is illustrated above, other mappings and/or other functions can be used to generate the customized stream identifiers.

PID replacement may be required in order to avoid PID collision/duplication of PID's in the aggregated transport stream232. The PID replacement module210identifies duplicate PIDs and substitutes customized PIDs for duplicate PIDs to allow unique processing of PIDs by the processing device120. The PID replacement modules210each processes the transport stream packets of the corresponding transport streams to replace a packet identifier with a customized packet identifier for selected ones of the transport stream packets of the plurality of transport streams. In particular, the PID replacement modules210each process transport stream packets to determine the selected ones of the transport stream packets based on identifying duplicate packet identifiers from differing ones of the plurality of transport streams. The PID replacement modules210replaces the packet identifier with the customized packet identifier for the selected ones of the transport stream packets to modify the packet identifiers as necessary to avoid duplicate packet identifiers.

The further operation of PID replacement module210can be described in conjunction with the following example that includes several optional functions and features. For example, the PID replacement module210can include a programmable table to implement the remapping of selected PID's on a stream-by-stream basis. Consider the example where m transport streams are aggregated. The programmable table can implement the following replacement based on functions of the packet ID values, PIDi, and stream identifiers SIDj, where 0≦i≦n and where 0≦j≦m.
{SID0(PID0)+SID1(PID0)} is mapped to {SIDx(PID0)+SIDx(PIDn)}
While a particular mapping is illustrated above, other mappings and/or other functions can be used to generate the customized packet identifiers. Also, while the sync field substitution module200and PID replacement module210are presented in a particular order, the order of these modules can be reversed.

In order to transmit the aggregate stream without loss of data, a buffer mechanism is required in order to accommodate the concurrent arrival of multiple stream packets. The packet buffers220buffers the plurality of transport streams. The packet buffers220must be emptied at a rate greater than or equal to the aggregate fill rate of the buffer. In the example shown, a separate packet buffer220is provided for each originating stream. Assuming the input transport streams have the same rate, each packet buffer220can be emptied in a time division multiplexed strategy at equal proportions and periods per buffer. If different transport streams rates are present, the packet buffers220can be emptied in proportion to the corresponding rate.

The multiplexer230multiplexes the plurality of transport streams into the aggregated transport stream232under control of one or more control signals (CS)242. The stream multiplex controller240generates at least one control signal242to control the multiplexing of the plurality of the transport streams into the aggregated transport stream232. In addition, the control signals242can further be used to control the transfer of the aggregated transport stream (ATS)232to the processing device120. In an embodiment, the control signal242includes a gated transport stream clock.

FIG. 4presents a timing diagram representation of a gated transport stream clock260in accordance with a further embodiment of the present disclosure. In an embodiment, in addition to multiplexing a plurality of serial transport streams down to a single transport stream, the transport stream aggregator150further reduces the required pin count on the input interface to processing device120by removal of unnecessary signaling. As discussed in conjunction withFIG. 3, the control signals242can include a gated transport stream clock, an example of which is shown.

Consider the example where the processing device120is an XCODE processor or other processing device that supports gating of the transport stream input clock. In this case, the transport stream aggregator150need not generate a separate control signal242that indicates the presence of valid data on the output. The transport stream aggregator merely toggles the transport stream input clock for periods when a valid bit transmitted, but otherwise keeps the clock in an active low state. In the example shown, the gated transport stream clock260includes clock pulses in periods262and266corresponding to valid data from the transport stream aggregator150and no clock pulses in periods264and268corresponding to no valid data from the transport stream aggregator150—e.g. when the transport stream aggregator150is not ready to transfer the next data element.

In a further embodiment, if the aggregated transport stream232can be guaranteed to contain only valid packets, all of which are equal size, the transport stream aggregator150may not be required to generate a control signal242for synchronization. In an embodiment, the processing device120employs an implicit sync feature, which allows the transport stream input interface to dynamically obtain and retain packet synchronization under the provisions stated above. In this fashion, the interface between transport stream aggregator150and the processing device120may be as simple as two lines—a data line and the gated transport stream clock260.

Note however, that a change in packet size or input of non-packet data during the inter-packet time will force the loss of sync and subsequent loss of packet data during the resynchronization process. Further note that any substitution of the synchronization field described in conjunction withFIG. 3will need to be compatible with the implicit synchronization of processing device120, if implemented.

FIG. 5presents a block diagram representation of an interface architecture in accordance with an embodiment of the present disclosure. In particular, an architecture is shown that includes elements described in conjunction withFIGS. 2-3that are referred to by common reference numerals.

In a system with multiple devices which require persistent storage of software, memory device130is implemented via a single flash memory device in order to reduce memory bandwidth. In order to support this reduction in the total number of storage devices for boot code, the architecture shown is used to boot one or more devices including the transport stream aggregator150and the slave device140as slaves to the processing device120. In the embodiment shown, the transport stream aggregator150and slave device140are coupled to the processing device120via a serial interface270and the memory device130is coupled to the processing device120via serial interface272that is separate from the serial interface270.

In this example, the processing device120operates as a Boot Master and the transport stream aggregator150and slave device140operate as Boot Slaves. The memory device130stores software for both the Boot Master and Boot Slaves. The Boot Master is the first device to boot and will have dedicated control of the Memory device130. The Boot Master is responsible for retrieving its own boot code and completing self-initialization. Subsequently, the Boot Master deasserts, in turn, each slave reset and, in turn, proceeds to push slave boot code and initialization sequence to each Boot Slave using the serial interface270. Each Boot Slave device is under the control of the Boot Master. The size and format of the slave software does not require predefinition. As the processing device120is required to boot, prior to slave initialization and software upload, the specific encoding of the slave software and initialization routine may be embedded in the code of the processing device120.

In an embodiment, the Boot Slaves may be required to support a serial interconnect slave interface which the Boot Master uses to initialize the slave device and upload software. The serial interface270operates in accordance with a first interface protocol and the serial interface272operates in accordance with a second interface protocol that is different from the first interface protocol. Example serial interfaces are SPI or I2C.

In one example, the interface270is an I2C interface and the interface272is an SPI interface. Since each Boot Slave device resides on an I2C bus with other I2C devices. Each Boot Slave device requires a unique address.

FIG. 6presents a block diagram representation of an interface architecture in accordance with an embodiment of the present disclosure. In particular, an architecture is shown that includes elements described in conjunction withFIGS. 2-3that are referred to by common reference numerals.

Like the embodiment shown in conjunction withFIG. 5, memory device130is implemented via a single flash memory device in order to reduce memory bandwidth. In order to support this reduction in the total number of storage devices for boot code, the architecture shown is used to boot one or more devices including the transport stream aggregator150and the slave device140as slaves to the processing device120. In the embodiment shown, the transport stream aggregator150and memory device130are coupled to the processing device120via a serial interface280and the slave device140is coupled to the processing device120via serial interface282that is separate from the serial interface280.

Like the embodiment shown in conjunction withFIG. 5, the processing device120operates as a Boot Master and the transport stream aggregator150and slave device140operate as Boot Slaves. The memory device130stores software for both the Boot Master and Boot Slaves. The Boot Master is the first device to boot and will have dedicated control of the Memory device130. The Boot Master is responsible for retrieving its own boot code and completing self-initialization. Subsequently, the Boot Master deasserts, in turn, each slave reset and, in turn, proceeds to push slave boot code and initialization sequence to each Boot Slave using the serial interfaces280and282. Each Boot Slave device is under the control of the Boot Master. The size and format of the slave software does not require predefinition. As the processing device120is required to boot, prior to slave initialization and software upload, the specific encoding of the slave software and initialization routine may be embedded in the code of the processing device120.

In one example, the interface282is an I2C interface and the interface280is an SPI interface. The transport stream aggregator150operates as an SPI Boot Slave device, residing in a SPI serial topology with tri-state data output and shared data input. In this case, the memory130and transport stream aggregator150are provided a dedicated chip select signal from the Boot Master to enable and disable communications. In operation, the processing device120generates a chip select signal that is coupled to the memory device130and the transport stream aggregator150. The chip select signal indicates one of: communication between the processing device120and the memory device130; and communication between the processing device120and the transport stream aggregator150.

FIG. 7presents a block diagram representation of a video distribution system175in accordance with an embodiment of the present disclosure. In particular, video signals110are transmitted via a transmission path122to a video decoder202. Video decoder202, in turn can operate to decode the video signals110for display on a display device such as television12, computer14or other display device.

The transmission path122can include a wireless path that operates in accordance with a wireless local area network protocol such as an 802.11 protocol, cellular4G or other cellular data protocol, a WIMAX protocol, a Bluetooth protocol, or other wireless protocol. Further, the transmission path can include a wired path that operates in accordance with a wired protocol such as a USB protocol, high-definition multimedia interface (HDMI) protocol an Ethernet protocol or other high speed protocol.

FIG. 8presents a block diagram representation of a video storage system179in accordance with an embodiment of the present disclosure. In particular, device11is a set top box with built-in digital video recorder functionality, a stand alone digital video recorder, a DVD recorder/player or other device that transcodes the video signals110for storage181and/or decodes the video signals110for display on video display device such as television12. Storage181can include a hard disk drive optical disk drive or other disk drive, read-only memory, random access memory, volatile memory, non-volatile memory, static memory, dynamic memory, flash memory, cache memory, and/or any device that stores digital information. Storage181can be integrated in the device11or coupled to the device11via a network, wireline coupling or other connection.

While these particular devices are illustrated, video storage system179can include a hard drive, flash memory device, computer, DVD burner, or any other device that is capable of generating, storing, decoding and/or displaying a video stream in accordance with the methods and systems described in conjunction with the features and functions of the present disclosure as described herein.

FIG. 9presents a flowchart representation of a method in accordance with an embodiment of the present disclosure. In particular a method is presented for use in conjunction with one or more functions and features described in conjunction withFIGS. 1-8. Step400includes receiving a plurality of transport streams in a transport stream format. Step402includes processing transport stream packets of the plurality of transport streams to replace a packet synchronization field with a customized synchronization field. Step404includes generating an aggregated transport stream from the plurality of transport streams. Step406includes transferring the aggregated transport stream to a video processing device.

In an embodiment, the customized synchronization field includes a stream identifier that indicates one of the plurality of transport streams. Step404can include buffering the plurality of transport streams, and multiplexing the plurality of transport streams into the aggregated transport stream, based on at least one control signal. The method can further include generating the at least one control signal to control the multiplexing of the plurality of the transport streams into the aggregated transport stream and the transfer of the aggregated transport stream to the processing device. The at least one control signal can include a gated transport stream clock having clock pulses in a first period corresponding to valid data of the aggregated transport stream and no clock pulses in a second period not corresponding to valid data of the aggregated transport stream.

FIG. 10presents a flowchart representation of a method in accordance with an embodiment of the present disclosure. In particular a method is presented for use in conjunction with one or more functions and features described in conjunction withFIGS. 1-9. Step410includes storing a plurality of routines in a memory device. Step412includes self-booting a processing device based on a first routine of the plurality of routines. Step414includes booting, via the processing device, a transport stream aggregator based on a second routine of the plurality of routines. Step416includes processing a plurality of transport streams in a transport stream format via the transport stream aggregator to generate an aggregated transport stream. Step418includes generating a processed video signal from the aggregated transport stream via the processing device.

In an embodiment, the processing device is self-booted by executing a self-initialization and retrieving the first routine from the memory device. The processing device then boots the transport stream aggregator by retrieving the second routine from the memory device and by pushing the second routine to the transport stream aggregator. The method can further include coupling the transport stream aggregator and the memory device to the processing device via a shared serial interface.

FIG. 11presents a flowchart representation of a method in accordance with an embodiment of the present disclosure. In particular a method is presented for use in conjunction with one or more functions and features described in conjunction withFIGS. 1-10. Step420includes receiving a plurality of transport streams in a transport stream format. Step422includes processing transport stream packets of the plurality of transport streams to replace a packet synchronization field with a customized synchronization field. Step424include processing the transport stream packets of the plurality of transport streams to determine selected ones of the transport stream packets based on identifying duplicate packet identifiers from differing ones of the plurality of transport streams. Step426includes processing the transport stream packets of the plurality of transport streams to replace a packet identifier with a customized packet identifier for selected ones of the transport stream packets of the plurality of transport streams. Step428includes generating an aggregated transport stream from the plurality of transport streams. Step430includes transferring the aggregated transport stream to a video processing device.

FIG. 12presents a flowchart representation of a method in accordance with an embodiment of the present disclosure. In particular a method is presented for use in conjunction with one or more functions and features described in conjunction withFIGS. 1-11. Step430includes generating a chip select signal wherein the chip select signal indicates one of: communication between the processing device and the memory device; and communication between the processing device and the transport stream aggregator. Step432includes coupling the chip select signal to the memory device and the transport stream aggregator.

FIG. 13presents a flowchart representation of a method in accordance with an embodiment of the present disclosure. In particular a method is presented for use in conjunction with one or more functions and features described in conjunction withFIGS. 1-12. Step440includes coupling the transport stream aggregator to the processing device via a first serial interface. Step442includes coupling the memory device to the processing device via second serial interface that is separate from the first serial interface.

In an embodiment, the first serial interface operates in accordance with a first interface protocol and the second serial interface operates in accordance with a second interface protocol that is different from the first interface protocol.

FIG. 14presents a flowchart representation of a method in accordance with an embodiment of the present disclosure. In particular a method is presented for use in conjunction with one or more functions and features described in conjunction withFIGS. 1-13. Step450includes coupling a slave device to the processing device. Step452includes booting, via the processing device, the slave device based on a third routine of the plurality of routines.