System and method for sensor failure detection

A novel image sensor includes a pixel array, a row control circuit, a test signal injection circuit, a sampling circuit, an image processing circuit, a comparison circuit, and a control circuit. In a particular embodiment, the test signal injection circuit injects test signals into the pixel array, the sampling circuit acquires pixel data from the pixel array, and the comparison circuit compares the pixel data with the test signals. If the pixel data does not correspond to the test signals, the comparison circuit outputs an error signal. Additional comparison circuits are provided to detect defects in the control circuitry of an image sensor.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to image sensors, and more particularly to failure detection in image sensors.

2. Description of the Background Art

Electronic image sensors are commonly incorporated into a variety of devices including, for example, cell phones, computers, digital cameras, PDA's, etc. In addition to conventional user-controlled still and video camera applications, more and more image sensor applications are emerging. For example, integral machine vision applications are expanding rapidly in the automotive, manufacturing, medical, security, and defense industries. In such applications, machines typically perform certain operational tasks (e.g. collision prevention tasks) based on information (e.g. position of an object relative another object) captured by the image capture system of the machine. In order for the machine to perform the proper task associated with the particular situation, it is essential for the image sensor to reliably capture, process, and output image data that accurately represents the observed situation.

A Complementary Metal Oxide Semiconductor (CMOS) image sensor typically includes a sensor array, control circuitry, row control circuitry (e.g., row address decoder, pixel drivers, etc.), column sampling circuitry, and image processing circuitry. Image sensors are often used in conjunction with a lens assembly which is aligned with the sensor array so as to focus an image thereon. The sensor array converts incident light into electrical data indicative of the image. The sensor array is made up of a plurality of light sensitive pixels arranged in a plurality of rows and columns. The pixels are electrically coupled to the row control circuitry and the column sampling circuitry via a grid of row and column signal lines, respectively. That is, each individual row of pixels is connected to, and controlled by, the row control circuitry via an associated set of row signal lines including, for example, a transfer line, a reset line, and a row select line. Each individual column of pixels is connected to the column sampling circuitry via a discrete column sampling line. The column sampling circuitry typically includes sampling components such as, for example, amplifiers, analog-to-digital converters, and data storage elements that are coupled to the column sampling lines for digitizing and storing the electrical signals output from the pixels. In image sensors that have a column parallel readout architecture, the column sampling circuitry includes a discrete set of these sampling components for each column sampling line such that an entire row of pixels can be sampled simultaneously. In column-parallel readout architectures, the column sampling circuitry also includes various signal lines that are routed to the various sampling components so as to carry control signals thereto. (Non-column parallel readout architectures also require various horizontal signal lines, although not as many as a column parallel architecture.) The image processing circuitry receives digitized data output from the column sampling circuitry and generates image data in readable format. The interface enables the image sensor to communicate (e.g., output formatted image/video data, receive operating instructions, etc.) with a host system (e.g., cell phone motherboard, vehicle computer system, manufacturing machine computer system, etc.). In general, the control circuitry of the image sensor is connected to the row control circuitry, the column sampling circuitry, the image processing circuitry, and the interface so as to carry out various timing and control operations.

Each pixel includes a photosensitive element (e.g., photodiode, photogate, etc.), a transfer transistor, a floating diffusion region, a reset transistor, a source-follower transistor, and a row-select transistor. The photosensitive element is operative to accumulate a charge proportional to the intensity of incident light to which it is exposed during shutter operations. The transfer transistor connects the photosensitive element to the floating diffusion region and includes a gate that is connected to and, therefore, controlled by a single transfer line dedicated to the entire row of pixels. When a logical high voltage signal is asserted on the transfer line, the charge from the photosensitive element is transferred to the floating diffusion region. The reset transistor connects the floating diffusion region to a voltage source terminal and includes a gate that is connected to and, therefore, controlled by a reset line of the row signal lines. When a logical high voltage signal is asserted on the reset line, the reset transistor connects the floating diffusion region to the voltage source terminal, thus resetting any previously stored charge to a known state. The source-follower transistor connects the voltage source terminal to the row-select transistor and includes a gate that is connected to the floating diffusion region so as to generate an amplified voltage signal indicative of the charge accumulated within the floating diffusion region. The row-select transistor connects the source-follower transistor to the pixel output line of the column lines and includes a gate that is connected to a row-select line of the row lines. When a logical low voltage is asserted on the row-select line the row-select transistor acts as an open switch between the source-follower transistor and the pixel output line. Oppositely, a logical high voltage asserted on the gate of the row-select line causes the row-select transistor to act as a closed switch between the source-follower transistor and the column sampling line such that the state of the floating diffusion can be sampled through the column sampling line.

Although traditional image sensors meet the needs of many image and video capture applications, there are drawbacks to current designs. For example, CMOS pixels are constructed from integrated circuit components (e.g., transistors, diodes, capacitors, etc.) that are prone to failure. As another example, pixel row signal lines (e.g., transfer lines, reset lines, row-select lines, etc.), column sampling lines, and column sampling component control lines (e.g., gain amplifier control lines, analog-to-digital converter control lines, digitized pixel data storage device control lines, etc.) are prone to damage, especially those subjected to large distributed stress-causing loads. As yet another problem, row control circuits are also prone to failure. In the event that any of the aforementioned failures occur in a conventional image sensor, it will generally output erroneous image data to the hosting system. Of course, a hosting system typically does not recognize the difference between erroneous image data and correct image data. This can be particularly problematic in certain applications (i.e. integral machine vision applications) wherein the image data dictates operational tasks performed by the host system. Even when the circuits are not very prone to damage or failure, certain applications (e.g., automotive applications) demand systems with exceptionally high reliability.

What is needed, therefore, is an image sensor design with improved image data output reliability.

SUMMARY

The present invention overcomes the problems associated with the prior art by providing an image sensor with integrated failure detection. Various aspects of the invention detect failures in the photosensing pixels, in the control lines of the pixel array, and in the sample/hold circuitry.

An example image capture device includes a plurality of pixels. Each pixel has a photosensor, a charge storage region, a signal output, and a test signal input. The charge storage region is selectively coupled to receive photocurrent from the photosensor. The signal output is coupled to the charge storage region and outputs a signal indicative of the amount of charge stored in the charge storage region. The test signal input is also coupled to the charge storage region. A test signal injection circuit is coupled to provide test signals to the test signal inputs of the pixels, and a sampling circuit is selectively coupled to receive the output signals from the outputs of the pixels. A comparison circuit compares the test signals provided to the pixels to the output signals received from the pixels, and provides an error signal if the output signals do not correspond to the test signals. Optionally, the test signal injection circuit is coupled to the comparison circuit to directly provide the test signals provided to the pixels to the comparison circuit. Various means are disclosed for comparing the test signals provided to the pixels and the output signals received from the pixels, and for providing an error signal in response to the output signals not corresponding to the test signals.

In a disclosed embodiment, the pixels are arranged in a plurality of columns, and the image capture device includes a plurality charge injection lines. Each charge injection line couples the test signal inputs of the pixels of a respective one of the columns to the test signal injection circuit. The charge storage region of each pixel is coupled to a respective one of the charge injection lines via a capacitor, and there are no switching devices interposed between the charge storage regions of the pixels and the charge injection lines.

In the disclosed embodiment, the test signal injection circuit is capable of providing different test signals on different ones of the charge injection lines, and also capable of providing different test signals on a same one of the charge injection lines at different times.

An example test signal injection circuit includes a plurality of test signal storage elements and a test signal generator. Each of the test signal storage elements is selectively coupled to a respective one of the charge injection lines. The test signal generator is coupled to the test signal storage elements and is operative to generate test signal values and store the test signal values in the storage elements.

In a particular embodiment, the test signal generator is operative to generate digital test signal values, and each of the storage elements is a single-bit storage element. The test signal generator includes a random bit generator. The storage elements are coupled together serially, and bits from the random bit generator are shifted into the storage elements.

The pixels can operate in either image capture mode or test mode. The charge storage region of each the pixel is selectively coupled to the photosensor of each the pixel by a switching device of each the pixel. A controller is coupled to provide transfer signals to the switching devices of the pixels. Responsive to a first value of the transfer signals, the switching devices conduct photocurrent between the photosensors and the charge storage regions to facilitate image capture. Responsive to a second value of the transfer signal, the switching devices block photocurrent between the photosensors and the charge storage regions to facilitate test signal injection. In operation, the image capture device executes a repetitive image capture process over successive frame times to capture frames of image data. The controller asserts the second value of the transfer signal for the duration of an image capture process to facilitate test signal injection every Nth frame time, where N is an integer greater than one.

Means of detecting failures in the control circuitry of an image capture device are also disclosed. In an example image capture device a controller provides a control signal. A driver, responsive to the control signal, is operative to generate a drive signal based on the control signal and to assert the drive signal on a control line of the image capture device. A comparator responsive to a first input based on the control signal and a second input based on the drive signal, generates an error signal if the control signal does not correspond to the asserted drive signal in a predetermined way. In a particular embodiment, the comparator directly compares the control signal to the drive signal to determine whether the drive signal corresponds to the control signal. Various means are disclosed for comparing the first input based on the control signal and the second input based on the drive signal, and for generating an error signal if the control signal does not correspond to the asserted drive signal in a predetermined way.

In one instance, the driver is a row control driver of an image sensor array. In another instance, the driver is a component of an image data sampling circuit, which receives rows of data from the image sensor array.

Various means for comparing control signals and drive signals are disclosed. In one example embodiment, the image capture device additionally includes a second driver coupled to receive the control signal and operative to generate a second drive signal based on the control signal, and the comparator compares the second drive signal to the drive signal.

In another example embodiment, a first encoder is coupled to a plurality of control lines at a first point and generates a first encoded value based on drive signals detected on the control lines. A second encoder is coupled to the plurality of control lines at a second point spaced apart from the first point, and generates a second encoded value based on drive signals detected on the control lines at the second point. The comparator is operative to compare the first encoded value to the second encoded value.

Methods for detecting defects in an image capture device are also disclosed. An example method includes providing an image capture device including a sensor array, causing an image to be focused on the sensor array, and repeatedly capturing frames of image data with the sensor array. The image data is indicative of the image focused on the sensor array. The method additionally includes periodically injecting test data into the sensor array between the repeated captures of the image data, reading the test data from the image capture device, and comparing the read test data to the injected test data. An error signal is generated if the read test data does not correspond to the injected test data.

Another example method includes receiving a control signal, generating a drive signal based on the control signal, and asserting the drive signal on a control line of the image capture device. The method additionally includes comparing the asserted drive signal to the control signal and generating an error signal if the control signal does not correspond to the asserted drive signal in a predetermined way. In a particular method, the step of asserting the drive signal on a control line of the image capture device includes asserting the drive signal on a row control line of an image sensor array. In another particular method, the step of asserting the drive signal on a control line of the image capture device includes asserting the drive signal on a control line of an image data sampling circuit. In yet another particular method, the step of comparing the asserted drive signal to the control signal includes generating a second drive signal based on the control signal and comparing the second drive signal to the drive signal.

In another example method, the step of comparing the asserted drive signal to the control signal includes generating first encoded value based on drive signals being asserted at a first point on a plurality of control lines and generating a second encoded value based on the drive signals at a second point on the plurality of control lines. Then, the first encoded value is compared to the second encoded value.

Additional methods for detecting defects in an image capture device are disclosed. An example method includes receiving a control signal, generating a drive signal based on the control signal, asserting the drive signal on a control line of the image capture device, and comparing the asserted drive signal to the control signal. The method additionally includes generating an error signal if the control signal does not correspond to the asserted drive signal in a predetermined way.

In a particular method, the step of asserting the drive signal on a control line of the image capture device includes asserting the drive signal on a row control line of an image sensor array. In another particular method, the step of asserting the drive signal on a control line of the image capture device includes asserting the drive signal on a control line of an image data sampling circuit.

Optionally, the step of comparing the asserted drive signal to the control signal can include generating a second drive signal based on the control signal and comparing the second drive signal to the drive signal. As another option, the step of comparing the asserted drive signal to the control signal can include generating a first encoded value based on drive signals being asserted at a first point on a plurality of control lines, generating a second encoded value based on the drive signals at a second point on the plurality of control lines, and comparing the first encoded value to the second encoded value.

The various methods can also be used in combination. For example, the methods summarized above can additionally include receiving a second control signal, generating a second drive signal based on the second control signal, asserting the second drive signal on a second control line of the image capture device, and comparing inputs base on the second drive signal and the second control signal. A second error signal is generated if the second control signal does not correspond to the second drive signal in a predetermined way.

In an example method, the image capture device additionally includes an image sensor array and an image data sampling circuit coupled to receive rows of data from the image sensor array. In this example method, the drive signal is a row control drive signal in the image sensor array, and the second drive signal is a drive signal in the image data sampling circuit.

Another example method additionally includes periodically injecting test data into the image sensor array; and comparing the test data injected into the image sensor array with the test data received from the sensor array by the image data sampling circuit. The example method also includes generating a third error signal if the test data injected into the image sensor array does not correspond in a predetermined way with the test data received from the sensor array by the image data sampling circuit.

An example image capture device is also disclosed. The example image capture device includes a controller operative to provide a control signal, a driver and a comparator. The driver is responsive to the control signal and operative to generate a drive signal based on the control signal and to assert the drive signal on a control line of the image capture device. The comparator is responsive to a first input based on the control signal and a second input based on the drive signal. The comparator generates an error signal if the control signal does not correspond to the asserted drive signal in a predetermined way.

Various means are disclosed for comparing the first input based on the control signal and the second input based on the drive signal, and for generating an error signal if the control signal does not correspond to the asserted drive signal in a predetermined way

In a particular example embodiment, the comparator directly compares the control signal to the drive signal to determine whether the drive signal corresponds to the control signal.

In one instance, the image capture device additionally includes an image sensor array, and the driver is a row control driver of the image sensor array. In another instance, the image capture device additionally includes an image data sampling circuit coupled to receive rows of data from the image sensor array, and the driver is a component of the image data sampling circuit.

Multiple means for determining whether the control signal corresponds to the drive signal are disclosed. For example, in an example embodiment, the image capture device additionally includes a second driver coupled to receive the control signal. The second driver is operative to generate a second drive signal based on the control signal, and the comparator is operative to compare the second drive signal to the drive signal.

In another example embodiment, the image capture device additionally includes a plurality of the control lines. A first encoder is coupled to the plurality of control lines at a first point and is operative to generate a first encoded value based on drive signals detected on the control lines. A second encoder is coupled to the plurality of control lines at a second point spaced apart from the first point and is operative to generate a second encoded value based on drive signals detected on the control lines. The comparator then compares the first encoded value to the second encoded value.

Multiple example embodiments of the invention can be implemented in a single image capture device. For example, in addition to the first driver, a disclosed embodiment includes a second driver responsive to a second control signal. The second driver is operative to generate a second drive signal and to assert the second drive signal on a second control line of the image capture device. A second comparator is responsive to a first input based on the second control signal and a second input based on the second drive signal. The second comparator is operative to generate a second error signal if the second control signal does not correspond to the second drive signal in a predetermined way. In addition, the image capture device includes an image sensor array and an image data sampling circuit coupled to receive rows of data from the image sensor array. The driver is a row control driver of the image sensor array, and the second driver is a component of the image data sampling circuit. Furthermore, the example image capture device additionally includes a test data injection circuit operative to periodically inject test data into the image sensor array. A third comparator is operative to compare the test data injected into the image sensor array with the test data received from the sensor array by the image data sampling circuit. The third comparator also generates a third error signal if the test data injected into the image sensor array does not correspond in a predetermined way with the test data received from the sensor array by the image data sampling circuit.

DETAILED DESCRIPTION

The present invention overcomes the problems associated with the prior art, by providing an image sensor that includes malfunction detection circuitry. In the following description, numerous specific details are set forth (e.g., image sensor types, pixel types, transistor types, number of pixels, etc.) in order to provide a thorough understanding of the invention. Those skilled in the art will recognize, however, that the invention may be practiced apart from these specific details. In other instances, details of well-known integrated circuit image sensor manufacturing practices (e.g., transistor forming, color filter forming, wafer singulation, semiconductor doping, etc.) and components have been omitted, so as not to unnecessarily obscure the present invention.

FIG. 1is a perspective view of an image sensor100mounted on a portion of a printed circuit board (PCB)102that represents a PCB of a camera hosting device (e.g., automobile, manufacturing machine, medic device, cell phone, etc.). Image sensor100communicates electronically with other components of the hosting device via a plurality of conductive traces104. In the example embodiment, image sensor100is depicted as being part of a camera module106that further includes an optical assembly108and a housing110. As shown, housing110is mounted to image sensor100and optical assembly108is secured therebetween. Those skilled in the art will recognize that the particular designs and/or presence of PCB102, traces104, optical assembly108, and housing110will depend on the particular application, and are not particularly relevant to the present invention. Therefore, PCB102, traces104, optical assembly108, and housing110are representational in character only.

FIG. 2is a block diagram of image sensor100which, in the example embodiment, is a backside illuminated (BSI) complementary metal oxide semiconductor (CMOS) image sensor system-on-chip (SOC). Image sensor100includes a control circuit200, a pixel array202, a test signal injection circuit204, a first row controller206, a second row controller208, a first comparison circuit210, a sampling circuit212, a second comparison circuit214, an image processor216, and a third comparison circuit218.

Control circuit200provides the primary means for coordinating and controlling the various components of image sensor100. For example, control circuit200is operative to cause test signal injection circuit204to operate in either test mode or image capture mode. As another example, control circuit200is operative to provide both first row controller206and second row controller208with row control signals. As yet another example, control circuit200provides sampling circuit212with sampling control signals.

Pixel array202includes a plurality of pixels220arranged in a plurality of rows222and a plurality of columns224. That is, pixel array202includes M+1 rows222wherein the first is denoted row2220and the last as row222M. Similarly, pixel array202includes N+1 columns224wherein the first is denoted column2240and the last as column224N. Each of pixels220has a unique address i,j wherein i denotes the row of the address and j denotes the column of the address.

Test signal injection circuit204includes N+1 column injection circuits226which are connected to, and denoted in the same fashion as, columns224. Accordingly, the first of column injection circuits is denoted2260and the last as226N. Each of column injection circuits2260through226Nare operative to inject a test signal into a respective one of pixel columns2240through224Nwhen test signal injection circuit204is instructed to do so by control circuit200. When test signal injection circuit204is instructed to operate in image capture mode, all column injection circuits2260through226Ninject the same reference signal into each of respective columns2240through224N.

First row controller206is operative to generate row control signals defined by row control signal instructions output from control circuit200. Furthermore, row controller206is electrically coupled to each of rows222so as to assert the generated row control signals directly thereon. Second row controller208is also operative to generate the same row control signals defined by the same row control signal instructions output from control circuit200. Unlike first row controller206, the row control signals generated by second row controller208are not intended to drive rows222. Rather, they are used by first comparison circuit210to check whether or not the control signals generated by first row controller206have been properly distributed across rows222. That is, first comparison circuit210receives the control signals generated by second row controller208and then compares them with the electrical state of rows222. If the electrical state of rows222do not correspond with the control signals generated by second row controller208, first comparison circuit210outputs an error signal indicating that the control signals generated by first row controller206have not been properly distributed across one or more of rows222.

Sampling circuit212is operative to perform sampling operations according to column sampling instructions from control circuit200. As each row222is sequentially selected by first row controller206, sampling circuit212acquires digital data indicative of the electrical state of each column224. Accordingly, acquiring digital data for every pixel220of pixel array202requires sampling each of the N+1 columns224a total number of M+1 times per frame. Each time sampling circuit212acquires a row sample, it outputs the digital data to image processor216via data line(s)228for further processing.

Second comparison circuit214receives the same column sampling instructions that are provided to sampling circuit212by control circuit200. Second comparison circuit214compares the sampling instructions with actual control signals driving sampling circuit212. If the actual signals driving sampling circuit212do not correspond with the sampling instructions, second comparison outputs an error signal.

Image processor216is operative to convert the digital data acquired by sampling circuit212into readable image data via known image processing techniques.

Third comparison circuit218is operative to compare the test signals injected into columns224via test signal injection circuit204with the resultant digital data acquired by sampling circuit212. If the resultant digital data acquired by sampling circuit212does not properly correspond with the test signals, third comparison circuit218outputs an error signal. Third comparison circuit218can receive the digital data directly from sampling circuit212via data lines228or, optionally, via image processor216and data lines230.

FIG. 3is a schematic of pixel220i,jof pixel array202coupled to a set of row control signal lines300i, a charge injection line302j, and a readout line304j. Row control signal lines300iinclude a row select line306ia reset line308iand a transfer line310i. Row control signal lines300imay extend across the entire row222isuch that first row controller206may provide the same control signal to pixels220i,0through220i,Nof row222i. Likewise, charge injection line302jand readout line304jmay extend along the entire column224j. Charge injection line302jenables test signal injection circuit204to inject test signals into pixels2200,jthrough220M,j. Readout line304jenables sampling circuit212to sample the electrical state of pixels2200,jthrough220M,j.

In the example embodiment, pixel220i,jis a four-transistor (4T) pixel that includes a photosensor312, a charge storage region314, a pixel voltage source terminal (Vdd)316, a reset transistor318, a transfer transistor320, a source-follower transistor322, a row select transistor324, and a coupling capacitor326. Photosensor312is, for example, a photodiode (PD) operative to convert incident light into electrical charge. Charge storage region314is a floating diffusion (FD) element operative to store charge generated by photosensor312. Pixel voltage source terminal316provides a voltage to both reset transistor318and source follower transistor322. Reset transistor318includes a first terminal328coupled to voltage source terminal316, a second terminal330coupled to charge storage region314, and a gate332coupled to reset line308i. When first row controller206asserts a reset signal, in this case a high voltage pulse, on gate332via reset line308itransistor318is temporarily placed into a conducting state wherein charge storage region314is coupled to voltage source terminal316. As a result, the previous charge state of storage region314is returned to a known reference charge state. Once reset line308iis returned to a low voltage state, reset transistor318returns to a non-conducting state wherein charge storage region314is electrically isolated from voltage source terminal316. Transfer transistor320includes a first terminal334coupled to photosensor312, a second terminal336coupled to charge storage region314, and a gate338coupled to transfer line310i. When first row controller206asserts a transfer signal, in this case a high voltage, on gate338via transfer line310itransistor320is placed into a conducting state wherein photosensor312is coupled to charge storage region314. As a result, the charge generated by photosensor312is transferred to charge storage region314. Once transfer line310iis returned to a low voltage state, transfer transistor320returns to a non-conducting state wherein charge storage region314is electrically isolated from photosensor312. Source-follower transistor322includes a first terminal340coupled to voltage source terminal316, a second terminal342coupled to row select transistor324, and a gate344coupled to charge storage region314. Those skilled in the art will recognize that electrical state of terminal342is dictated by the charge state of gate344and, therefore, the charge state of charge storage region314. Accordingly, terminal342may function as the output terminal of pixel220i,j, which is operative output an electrical signal indicative of the charge stored in charge storage region314. Row select transistor324includes a first terminal346coupled to terminal342of source-follower transistor322, a second terminal coupled to readout line304j, and a third terminal350coupled to row select line306i. When first row controller206asserts a row select signal, in this case a high voltage, on row select line306irow select transistor324operates in a conducting state wherein first terminal346and second terminal348are electrically coupled to one another, thus asserting the signal output from terminal342onto readout line304j. Row select transistor324operates in an open state when a row select signal is not being asserted on row select line306ithus disconnecting the output terminal of pixel220i,jfrom readout line304j. Coupling capacitor326includes a first terminal352to charge storage region314and a second terminal354coupled to charge injection line302j. Coupling capacitor326enables test signal injection circuit204(fromFIG. 2) control the charge state of charge storage region314by controlling the voltage asserted on charge injection line302j. When image sensor100operates in image capture mode, the voltage of charge injection lines302are held at a known reference level before and after the charge generated by photosensor312is transferred to charge storage region314. With charge injection line302held at a fixed voltage, the amount of charge generated by photosensor312in a given time frame is measured as difference between the charge state of charge storage region314before and after the charge from photosensor312is transferred thereto.

When image sensor100operates in test mode, test signal injection circuit204transfers a test signal into pixels220by altering the voltage asserted on charge injection line302and, therefore, terminal354of capacitor326. By altering the voltage level, the charge state of charge storage region314is adjusted to a value that simulates a known light intensity. For example, if the same reference voltage that is asserted on charge injection line302during image capture mode is asserted on charge injection line302during test mode, the electrical state of readout line304jwill appear as if photosensor312has generated minimal charge. As will be explained in further detail later, sampling circuit212(fromFIG. 2) samples readout line304jnormally as it would during image capture mode, and third comparison circuit218compares the data sample with the injected test signal and outputs an error signal when they do not agree.

In the example embodiment ofFIG. 3, the test signals are injected into the charge storage region314. However, the test signals can optionally be injected into the photosensor312, for example via reset transistor318and transfer transistor320.

FIG. 4is a schematic of test signal injection circuit204according to one embodiment of the present invention. In addition to column injection circuits2260through226N, test signal injection circuit204includes a random bit generator400, a random bit supply line402, a logical high voltage supply line404, and a logical low voltage supply line406. Furthermore, test signal injection circuit204is coupled to a buffered clock signal line408and a charge injection reset signal line410. Buffered clock signal line408is routed into test signal injection circuit204from control circuit200to supply clock signals to column injection circuits2260through226Nand random bit generator400. Buffer420may be coupled between control circuit200and column injection circuit204to buffer and/or amplify the clock signal from control circuit200.

Charge injection reset line410is routed into test signal injection circuit204from control circuit200to supply reset signals to column injection circuits2260through226N. Random bit generator400includes an input terminal412and an output terminal414coupled to buffered clock signal line408and random bit supply line402, respectively. In one embodiment, random bit generator400may be a Linear Feedback Shift Register (LFSR) that is operative to assert a randomly generated data bit onto random bit supply line402in response to receiving a clock signal from buffered clock signal line408. Random bit supply line402is routed to supply random data bits to column injection circuits2260through226Nand is also routed out of test signal injection circuit204to third comparison circuit218(fromFIG. 2). High voltage supply line404and low voltage supply line406are routed across test signal injection circuit204to column injection circuits2260through226N.

FIG. 5is a schematic of column injection circuit226jand adjacent column injection circuit226j−1. Each column injection circuit226Nthrough2260includes a memory element500, a first switch circuit502, and a second switch circuit504. In the illustrated embodiment, each memory element500is a flip-flop circuit having a clock input terminal506coupled to buffered clock signal line408, a data-bit input terminal508, and a data-bit output terminal510. Data-bit input terminal508of memory element500N(not shown) is coupled to random bit supply line402(fromFIG. 4). With the exception of memory element500N, data-bit input terminal508of subsequent memory elements500N−1through5000are coupled to the output terminals510of the adjacent memory element500. For example, data-bit input terminal508of memory element500jis coupled to data-bit output terminal510of adjacent memory element500j+1. Likewise, data-bit input terminal508of memory element500j−1is coupled to data-bit output terminal510of adjacent memory element500j. Accordingly, memory elements500are flip-flops that are cascaded together to form a single serial-in shift register, wherein data-bits are serially shifted in from random bit generator400via random bit supply line402. Those skilled in the art will recognize that when buffered clock signal line408is clocked, random bit generator400asserts a new data bit on data-bit input terminal508Nthus shifting the data bit that was previously stored in memory element500Ninto 500N−1. Thus, loading a newly generated data-bit into memory5000requires asserting N+1 clock signals on buffered clock signal line408. In the example embodiment ofFIG. 5, memory element500are flip-flops, in other embodiments, memory element500may be pulsed latches or random access memories (RAM).

First switch circuit502includes a control terminal512coupled to charge injection reset signal line410, a first input terminal514coupled to logical high voltage line404, a second input terminal516coupled to second switch circuit504, and an output terminal518coupled to charge injection line302. Under the control of charge injection reset signal line410, first switch circuit502selectively couples charge injection line302to either logical high voltage line404or second switch circuit504. Second switch circuit504includes a control terminal520coupled to input terminal508of memory element500, a first input terminal522coupled to logical high voltage supply line404, a second input terminal524coupled to logical low voltage supply line406, and an output terminal526coupled to second input terminal516of first switch circuit502. Under the control of input terminal508, second switch circuit504selectively couples the second input terminal516of first switch502to either logical high voltage supply line404or logical low voltage supply line406.

FIG. 6is a circuit diagram showing features of pixel array202, first row controller206, second row controller208, and first comparison circuit210. Both first row controller206and second row controller208are coupled to receive row control instructions output from control circuit200in the form of data bits. In the illustrated embodiment, the row control instructions output from control circuit200include row address instructions for controlling row select lines3060through306M, reset line control instructions for controlling reset lines3080through308M, and transfer line control instructions for controlling transfer lines3100through310M. The row address instructions are in the form of data bits that indicate which of row select lines3060through306Mwill be asserted. Each of row select lines3060through306Mincludes a first end600and a second end602coupled to first row controller206and first comparison circuit210, respectively. Each of reset lines3080through308Malso include a first end604and a second end606coupled to first row controller206and first comparison circuit210, respectively. Each of transfer lines3100through310Malso include a first end608and a second end610coupled to first row controller206and first comparison circuit210, respectively.

First row controller206includes a primary row decoder612and a row driver614. Primary row decoder612includes an input terminal616coupled to receive row control signal instructions from control circuit200. Row driver614is coupled to primary row decoder612and is operative to assert row select signals on row select lines3060through306M, reset signals on reset lines3080through308M, and transfer signals on transfer lines3100through310Maccording the row control instructions decoded by primary row decoder612. Row driver614includes a plurality of output terminals6180through618M,6200through620M, and6220through622M. Output terminals6180through618M, are operative to output row select signals associated with respective row select lines3060through306M. First ends6000through600Mare coupled to output terminals6180through618M, respectively. Output terminals6200through620M, are operative to output reset signals associated with respective reset lines3080through308M. First ends6040through604Mare coupled to output terminals6200through620M, respectively. Output terminals6220through622M, are operative to output transfer signals associated with respective transfer lines3100through310M. First ends6080through608Mare coupled to output terminals6220through622M, respectively.

Second row controller208comprises a secondary row decoder624that includes an input terminal626. Second row controller208further includes a plurality of output terminals6280through628M,6300through630M, and6320through632M, collectively output terminals628,630and632respectively. Input terminal626of secondary row decoder624is coupled to receive the same row control signal instructions provided to input primary row decoder612by control circuit200. Accordingly, primary row decoder612and secondary row decoder624simultaneously decode that same row control signal instructions such that the logic states of output terminals6280through628Mmatch the logic states of respective output terminals6180through618M, the logic states of output terminals6300through630Mmatch the logic states of respective output terminals6200through620M, and the logic states of output terminals6320through632Mmatch the logic states of respective output terminals6220through622M. For example, when output terminal6180changes from a low voltage state to a high voltage state, output terminal6280also changes from a low voltage state to a high voltage state at the exact same time.

First comparison circuit210is operative to compare the electrical states of row control signal lines3000through300M, which comprises row select lines3060through306M, reset line3080through308Mand transfer line3100through310M, with control signals output from secondary row decoder624. If the logic state of a particular row control signal for a given row, such as row select line3060do not agree with the logical state of output6280, then, first comparison circuit210outputs an error signal from an error signal output line634.

First comparison circuit210includes a first plurality of input terminals including input terminals6360through636M,6380through638M, and6400through640M. Input terminals6360through636Mare electrically coupled to respective output terminals6280through628M, input terminals6380through638Mare electrically coupled to respective output terminals6300through630M, and input terminals6400through640Mare electrically coupled to respective output terminals6320through632M. First comparison circuit210further includes a second plurality of input terminals including input terminals6420through642M,6440through644M, and6460through646M. Input terminals6420through642Mare electrically coupled to respective second ends6020through602Mof respective row select lines3060through306M. Likewise, input terminals6440through644Mare electrically coupled to respective second ends6060through606Mof respective reset lines3080through308M. Finally, input terminals6460through646Mare electrically coupled to respective second ends6100through610Mof respective transfer lines3100through310M.

During operation, first comparison circuit210determines if the logical state of input terminals6360through636Mhave a predetermined correspondence with those of respective input terminals6420through642M, if the logical state of input terminals6380through638Mcorrespond with those of respective input terminals6440through644M, and if the logical states of input terminals6400through640Mcorrespond with those of respective input terminals6460through646M. If not, error output line634outputs an error signal indicating that image sensor100is malfunctioning.

In the event that one of control signal lines3000through300Mare damaged, it is likely that a row control signal asserted thereon row driver614will not be properly distributed to all of the pixels within the associate row. It is important to understand that simultaneously decoding each set of row control signal instructions via primary row decoder612and secondary row decoder624and then comparing the electrical states of output terminals628,630, and632with respective second ends602,606, and610of control signal lines300, ensures that the row control signals from row driver614are being properly distributed across row control signal lines300. In contrast, prior art image sensors typically have no way of detecting such a malfunction and are, therefore, much more likely to output inaccurate image data to the host device.

FIG. 7is a circuit diagram showing features of first comparison circuit210according to an example embodiment of the invention. First comparison circuit210comprises a plurality of compare circuits and an error signal line706. In the illustrated embodiment, the compare circuits can include XOR gates. In other embodiments of the invention other logic gates such as a NAND or NOR logic gates may be used. If the two inputs to each compare circuit do not have a predetermined relationship (e.g., match), an error signal will be outputted.

In the illustrated embodiment, the sets of compare circuits include compare circuits7000through700M,7020through702M, and7040through704M. Each of compare circuits7000through700Mincludes an associated first input terminal708, second input terminal710, and output terminal712. As shown, each compare circuit700and each associated set of terminals708,710, and712are uniquely denoted with like subscripts. For example, compare circuit70010(not shown) includes first input terminal70810, second input terminal71010, and output terminal71210. First input terminals7080through708Mare electrically coupled to input terminals6360through636M, respectively. Second input terminals7100through710Mare electrically connected to input terminals6420through642M, respectively. Output terminals7120through712Mare all electrically coupled to error signal line706. Each of compare circuits7020through702Mincludes an associated first input terminal714, second input terminal716, and output terminal718.

First input terminals7140through714Mare electrically coupled to input terminals6380through638M, respectively. Second input terminals7160through716Mare electrically coupled to input terminals6440through644M, respectively. Output terminals7180through718Mare all electrically coupled to error signal line706. Each of compare circuits7040through704Mincludes an associated first input terminal720, second input terminal722, and output terminal724. First input terminals7200through720Mare electrically coupled to input terminals6400through640M, respectively. Second input terminals7220through722Mare electrically coupled to input terminals6460through646M. Output terminals7240through724Mare all electrically coupled to error signal line706. It should be recognized that when the first and second input terminals of an associated compare circuit do not correspond, the associated output terminal will output an error signal in the form of a logical high voltage state. With error signal line706being connected to all of output terminals7120through712M,7180through718M, and7240through724M, an error signal is outputted if one or more of them has a logical high voltage state. In other embodiments of the invention, each set of compare circuits may be coupled to their own respective error signal line. For example, first comparison circuit210may comprise three error signal lines, with one error signal line coupled to all of the output terminals of one set of compare circuits, the output terminal of compare circuits7000through700Mmay be coupled to a first error signal line, while compare circuits7020through702Mand7040through704Mmay be coupled to a second and a third error signal line, respectively. In yet other embodiments of the invention, a subset of the compare circuits may be coupled to their own respective error signal line. For example, the output terminal of compare circuits7000through700j,7020through702j,7040through704jmay be coupled to a first error signal line, while the output terminal of the remaining compare circuits may be coupled to a second error signal line. In another embodiment of the invention, a subset of each set of compare circuits may be coupled to their own respective error signal line. For example, the output terminals of compare circuits7000through700M, may be coupled to a first error signal line, while the output terminals of compare circuits702M+1through702jare coupled to a second error signal line. Similarly, a third, fourth, fifth and sixth error signal line may be coupled to the output terminals of compare circuits7040through704M,704M+1through704j,7060through706Mand706M+1through706j.

FIG. 8is a circuit diagram showing control circuit200, pixel array202, sampling circuit212, and second comparison circuit214. Sampling circuit212acquires pixel samples from readout lines3040through304Nof pixel array202and operates according to control signals output from control circuit200. Accordingly, sampling circuit212is coupled to receive control signals from control circuit200. Second comparison circuit214is coupled to both sampling circuit212and control circuit200and is operative to output an error signal when the control signals from sampling circuit212do not correspond with the control signals output from control circuit200.

Sampling circuit212includes a control signal conditioning circuit800, a first control signal line802, a second control signal line804, a third control signal line806, and a plurality of pixel readout circuits8080through808N.

Control signal conditioning circuit800is operative to condition the control signals output from control circuit200before asserting them onto control signal lines802,804, and806. Control signal conditioning circuit800includes a first input terminal810, a second input terminal812, a third input terminal814, a level shifting circuit816, a first buffer circuit818, a second buffer circuit820, a third buffer circuit822, a first output terminal824, a second output terminal826, and a third output terminal828. First input terminal810is coupled to receive amplifier control signals output from control circuit200. Second input terminal812is coupled to receive analog-to-digital converter control signals output from control circuit200. Third input terminal814is coupled to receive memory circuit control signals output from control circuit200. Level shifting circuit816is coupled to input terminals810,812, and814so as to level shift control signals asserted thereon by control circuit200. First buffer circuit818is operative to buffer amplifier control signals asserted on input terminal810after they are level shifted by level shifting circuit816. After being buffered by buffer circuit818, amplifier control signals are asserted on control signal line802from output terminal824. Second buffer circuit820is operative to buffer analog-to-digital converter control signals asserted on input terminal812after they are level shifted by level shifting circuit816. After being buffered by buffer circuit820, analog-to-digital converter control signals are asserted on control signal line804from output terminal826. Third buffer circuit822is operative to buffer memory circuit control signals asserted on input terminal814after they are level shifted by level shifting circuit816. After being buffered by buffer circuit822, memory circuit control signals are asserted on control signal line806from output terminal828.

Control signal line802includes a first end830and a second832, control signal line804includes a first end834and a second end836, and control signal line806includes a first end838and a second end840. Control signal line802is an amplifier control signal line operative to supply amplifier control signals to pixel readout circuits8080through808N. First end830and second end832of control signal line802are coupled to output terminal824of control signal conditioning circuit800and second comparison circuit214, respectively. Control signal line804is an analog-to-digital converter control signal line operative to supply analog-to-digital converter control signals to pixel readout circuits8080through808N. First end834and second end836of control signal line804are coupled to output terminal826of control signal conditioning circuit800and second comparison circuit214, respectively. Control signal line806is a memory circuit control signal line operative to supply memory circuit control signals to pixel readout circuits8080through808N. First end838and second end840of control signal line806are coupled to output terminal828of control signal conditioning circuit800and second comparison circuit214, respectively.

Each of pixel readout circuits8080through808Nis operative to acquire digital data indicative of the electrical state of a respective one of readout lines3040through304N. For example, pixel readout circuit808N−1is operative to acquire digital data indicative of the electrical state of readout line304N−1. Each of pixel readout circuits8080through808Nincludes a capacitor842, an amplifier844, an analog-to-digital converter846, and a memory circuit848. Each of capacitors8420through842Nincludes a first terminal850and a second terminal852coupled to a corresponding readout line304and amplifier844, respectively. Each of amplifiers8440through844Nis operative to amplify the electrical state of corresponding second terminals8520through852N. Each of amplifiers8440through844Nare coupled to control signal line802and, operates according to amplify control signals (e.g. gain control signals) output from terminal824of control signal conditioning circuit800.

Analog-to-digital converters8460through846Nare coupled to respective amplifiers844othrough844Nand are operative to digitize amplified signals output therefrom. For example, analog-to-digital converter846Ngenerates a binary data word indicative of the amplified voltage output from amplifier844N. Each of analog-to-digital converters8460through846Nare coupled to control signal line804and, operates according to analog-to-digital control signals output from terminal826of control signal conditioning circuit800. Memory circuits8480through848Nare coupled to analog-to-digital converters8460through846N, respectively, and are operative to store the binary data words generated therefrom. Memory circuits8480through848Nare coupled to control signal line806and, therefore, operate according to memory circuit control signals output from terminal828of control signal conditioning circuit800. Those skilled in the art will recognize that the number of data bits and, resolution of the binary data words acquired by readout circuits8080through808Nwill depend on the particular application. Accordingly, the resolution (e.g., 8-bit word) is not an essential aspect of the present invention and, therefore, need not be limited to any specific number of data bits or the type of analog-to-digital converter, such as successive approximate register or ramp analog-to-digital conversion.

Second comparison circuit214includes a first input terminal854, a second input terminal856, a third input terminal858, a fourth input terminal860, a fifth input terminal862, a sixth input terminal864. First input terminal854is coupled to receive the same amplifier control signals supplied to input terminal810of control signal conditioning circuit. In the illustrated embodiment, first input terminal854of second comparison circuit214and input terminal810of control signal conditioning circuit800are connected via a transit line866and are, therefore, both coupled to the same node. Second input terminal856is coupled to receive the same analog-to-digital control signals supplied to input terminal812of control signal conditioning circuit800from control circuit200. In the illustrated embodiment, input terminal856of second comparison circuit214and input terminal812of control signal conditioning circuit800are connected via a transit line868and are, therefore, both connected to the same node. Third input terminal858is connected to receive the same memory circuit control signals supplied to input terminal814of control signal conditioning circuit800from control circuit200. In the example embodiment, input terminal858of second comparison circuit214and input terminal814of control signal conditioning circuit800are connected via a transit line870and are, therefore, both connected to the same node.

Fourth input terminal860is coupled to second end832of control signal line802. Fifth input terminal862is coupled to second end836of control signal line804. Sixth input terminal864is connected to second end840of control signal line806. During operation, second comparison circuit214compares the electrical states of input terminals854,856, and858with the electrical states of input terminals860,862, and864, respectively. If the electrical states of input terminals854,856, and858do not correspond to those of respective input terminals860,862, and864, comparison circuit outputs an error signal.

FIG. 9is a circuit diagram showing additional details of second comparison circuit214according to one embodiment of the present invention. Second comparison circuit214comprises a plurality of logic gates and an error signal output terminal908. In the illustrated embodiment, second comparison circuit214comprise a plurality of XOR gates and an OR gate. In other embodiments of the invention, other logic gates such as XNOR or NOR logic gates may be used. With an OR gate, if any of the plurality of input terminals is at a logical high, the output will be a logical high.

Second comparison circuit214comprises a first XOR gate900, a second XOR gate902, a third XOR gate904, an OR gate906, and an error signal output terminal908. First XOR gate900includes a first input terminal910, a second input terminal912, and an output terminal914. Input terminals910and912of XOR gate900are coupled to terminals854and860, respectively. Accordingly, the logic state of output terminal914is low when input terminals910and912are either both logical high or both logical low, thus indicating that the amplifier control signals asserted on control line802are being properly distributed to all of amplifiers8440through844N. If the control signals supplied to input terminal810of control signal conditioning circuit800are not properly distributed across control line802to input terminal860, input terminal910will not have the same logical value as input terminal912thereby causing output terminal914to have a high logic state.

Second XOR gate902includes a first input terminal916, a second input terminal918, and an output terminal920. Input terminals916and918of XOR gate902are coupled to terminals856and862, respectively. The logic state of output terminal920is low when input terminals916and918are either both logical high or both logical low, thus indicating that the analog-to-digital converter control signals asserted on control line804are being properly distributed to all of analog-to-digital converters8460through846N. If the control signals supplied to input terminal812of control signal condition circuit800are not properly distributed across control line804to input terminal862, input terminals918and916will not match, thus causing output terminal920to have a high logic state.

Third XOR gate904includes a first input terminal922, a second input terminal924, and an output terminal926. Input terminals922and924of XOR gate904are coupled to terminals858and864, respectively. The logic state of output terminal926is low when input terminals922and924match, thus indicating that the memory circuit control signals asserted on control line806are being properly distributed to all of memory circuits8480through848N. If the control signals supplied to input terminal814of control signal conditioning circuit800are not properly distributed across control line806to input terminal864, input terminals924and922will not match, thus causing output terminal926to have a high logic state.

OR gate906includes a first input terminal928, a second input terminal930, a third input terminal932, and an output terminal908. Input terminals928,930, and932are coupled to output terminals914,920, and926, respectively. The logic state of output terminal908will be low when the logic state of output terminals914,920, and926are all low. If the logic state of one or more of output terminals914,920, and926are high, output terminal908will have a high logic state indicating that some type of failure has occurred in sampling circuit212.

In the illustrated embodiment, XOR gates are used. In other embodiments of the invention other logic gates such as a NAND or NOR logic gates may be used. With an XOR gate, if the two inputs do not match, a logical high will be outputted.

FIG. 10is a circuit diagram of third comparison circuit218(FIG. 2) according to one embodiment of the present invention. When image sensor100operates in test mode, third comparison circuit218compares the test signals provided by random bit generator400via random bit supply line402(which should also be provided by the column injection circuits2260through226Nto the pixels202and then sampled from the pixels202by sampling circuit212) with the digital data actually acquired by sampling circuit212. In the event that the acquired data does not match the test data, third comparison circuit218outputs an error signal from an error signal output terminal1000. In the illustrated embodiment, third comparison circuit218comprises a first checksum circuit1002, a threshold circuit1004, a second checksum circuit1006, and a comparator1008.

First checksum circuit1002includes a clock input terminal1010, a data-bit input terminal1012, and an output terminal1014. Clock input terminal1010and data-bit input terminal1012are coupled to buffered clock signal line408and random bit supply line402, respectively. Buffer420is coupled between control circuit200and buffered clock signal line408to buffer and/or amplify the clock signal from control circuit200. The clock signals asserted on buffered clock signal line408cause first checksum circuit1002to sequentially read, via input terminal1012, the randomly generated data bits that are sequentially asserted on random bit supply line402by random bit generator400(refer toFIG. 4). As the randomly generated bits are sequentially received by first checksum circuit1002, first checksum circuit1002calculates a checksum value that is output to comparator1008through output terminal1014.

Threshold circuit1004includes a clock input terminal1016, a data input terminal1018, and an output terminal1020. Clock input terminal1016is coupled to a second clock signal line1022to receive clock signals from control circuit200. Data input terminal1018is coupled to data lines228to receive pixel data acquired by sampling circuit212. The pixel data is processed and supplied to terminal1018from image processor216, via data lines228, in the form of binary data words, each word being indicative of the charge state of a particular pixel. Alternatively, the pixel data can be supplied to terminal1018directly from sampling circuit212in the form of binary data words. Each time a data word is loaded into threshold circuit1004, a single data-bit is output from terminal1020. If the binary value of the data word received via terminal1018is below a predetermined threshold value, threshold circuit1004outputs a binary “0” from terminal1020. Threshold circuit1004outputs a binary “1” from output terminal1020if the binary value of the data word received via input terminal1018is greater than, or equal to, the predetermined threshold value. Accordingly, each time clock signal line1022cycles, threshold circuit1004receives another data word and outputs another data bit corresponding thereto.

Second checksum circuit1006includes a clock input terminal1026, a data-bit input terminal1028, and an output terminal1030. Clock input terminal1026and data-bit input terminal1028of second checksum circuit1006are coupled to second clock signal line1022and output terminal1020of threshold circuit1004, respectively. Accordingly, each time clock signal line1022cycles, second checksum circuit1006receives another data bit output from threshold circuit1004. As the randomly generated bits are sequentially received by input terminal1028, first checksum circuit1006calculates a checksum value that is output to comparator1008through output terminal1030.

Comparator1008includes a first input terminal1032, a second input terminal1034, and an output terminal1036. First input terminal1032and second input terminal1034are coupled to receive binary checksum values output from terminals1014and1030, respectively. Output terminal1036of comparator1008is connected to error signal output terminal1000. If the checksum value received by input terminal1034is not equal to the checksum value received by input terminal1032, output terminal1036asserts an error signal onto error signal output terminal1000. The checksums can be calculated for each row or over an entire frame, but checking each row provides the advantage of identifying a particular defective row.

FIG. 11is an example timing diagram1100illustrating the operation of image sensor100while in image capture mode. The following example describes the control and sampling of row222, while image sensor100operates in image capture mode. In addition, the example illustrates the electrical states of various elements of pixel220i,jin response to the control of row222j. Although the operation of only row222iis described in this example, all of rows2220through222Mare controlled and sampled sequentially in the same manner. The operation of image sensor100will be described with reference also toFIGS. 2 through 10.

After acquiring image data for row222i−1, image data for row222iis acquired as follows. Initially, control circuit200outputs a set of row control instructions (e.g., row address for row i) to both row controllers206and208. Responsive to the row control instructions, row controller206asserts a row select signal1102on row select line306ithus causing row select transistor324of pixels220i,0through220i,Nto operate in a conducting state. Once row select transistor324of, for example, pixel220i,jis in a conducting state, the voltage state1104of associated readout line304jcorresponds to the charge state1106of charge storage (FD) region314i,j.

In this example embodiment, voltage supply line404provides the reference voltage (Vhi)1110at which injection lines3020through302Nare held while image sensor100operates in image capture mode. The high voltage state of charge injection reset signal line410causes each of switch circuits5020through502N(FIG. 5) to couple high voltage supply line404to a respective one of charge injection lines302. Thus, all of injection lines3020through302N(i.e., all injection lines to pixels220in row i) are coupled to high voltage supply line404.

At the same time that reset signal1108is asserted on charge injection reset signal line410, a pixel reset signal1112is asserted on reset line308, thus actuating reset transistor318of each associated one of pixels220i,0through220i,N. As previously mentioned, actuating transistor318couples the associated charge storage (FD) region314to voltage source terminal316(Vdd). Reset signal1112remains asserted on reset line308, for a predetermined time duration sufficient to allow any charge previously accumulated in charge storage regions314to return to a known reset state.

After reset signal1112is removed (e.g., goes low) from reset line308i, sampling circuit212simultaneously acquires a voltage sample from each of readout lines3040through304N. The time at which the first voltage samples are acquired is indicated by a dashed line denoted SHR1 (Sample-Hold-Reset 1). Shortly after SHR1, a transfer signal1114is asserted on transfer line310ithus actuating transfer transistor320of each associated one of pixels220i,0through220i,N. The actuation of transfer transistor320results in an electrical coupling and, therefore, a transfer of charge from photosensor312to charge storage (FD) region314. As shown, for example, the initial low charge state1116of photosensor312i,jand the initial high charge state1106of charge storage region314i,jsimultaneously increase and decrease, respectively, upon asserting signal1114on transfer line310i. Transfer signal1114remains asserted on transfer line310ifor a predetermined time duration sufficient to allow any charge generated by photosensor312i,jto transfer to charge storage region314i,j. After transfer signal114is removed from transfer line310i, sampling circuit212simultaneously acquires a second voltage sample from each of readout lines3040through304N. The time at which the second voltage samples are acquired is indicated by a dashed line denoted SHS1 (Sample-Hold-Signal1). Finally, row select signal1102is removed from row select line306, and the aforementioned process is repeated for row222i+1.

FIG. 12is a timing diagram1200illustrating an example of the operation of image sensor100in test mode. In particular, timing diagram1200shows an image capture process (before SHS1) followed by a test process (after SHS1). The following description explains the control and sampling of row222, and illustrates the electrical states of various elements of pixel220i,jin response to the control of row222j. Although the operation of only row222, is described in this example, all of rows222othrough222Mare controlled and sampled sequentially in a similar manner. The following description also referencesFIGS. 2-10.

In effort to convey the novel features of the present invention in a simplified manner, image sensor100is described as having only 24 pixel columns. However, it should be apparent to those skilled in the art that in a typical application image sensor100would likely have a substantially greater number of pixel columns. However, the present invention can be practiced with image sensor100having any practical number of pixel columns and/or rows.

Initially, control circuit200begins asserting a sequence of clock signals1202on clock signal line408. The number of cycles in clock signal1202is equal to the number of pixel columns224of image sensor100. Because this particular example describes image sensor100as having 24 pixel columns224, there are 24 cycles in the illustrated portion of clock signal1202. At each falling edge of clock signal1202, random bit generator400asserts a new randomly generated bit on random bit line402. Thus, random bit generator400asserts a sequence of 24 randomly generated bits on random bit line402. Each time a new randomly generated bit is asserted on random bit line402, the bit previously stored at data input terminal508of memory element500j+1is shifted to data input terminal508of memory element500j. Thus, a sequence of 24 bits1204is shifted into the 24 memory elements5000through50023(only two of the memory elements500are shown). Starting with the 1stand ending with the 24th, the sequence of 24 bits1204shown in this example is 110100101011000101010111.

After the 1stof bits1204is shifted into memory element500j, row select signal1102is asserted on row select signal line306ithus connecting charge storage regions314of pixels220i,0through220i,23to respective readout lines3040through30423. Shortly after row select signal1102is asserted on row select line306ireset signal1108is asserted on charge injection reset signal line410of test signal injection circuit204. The logical high voltage state of charge injection reset signal line410causes each of switch circuits5020through50223to couple terminals5180through51823to terminals5140through51423, respectively. As a result, injection lines3020through30223all couple to high voltage supply line404. At the same time that reset signal1108is asserted on charge injection reset signal line410, pixel reset signal1112is asserted on reset line308, thus coupling charge storage regions314i,0through314i,23to voltage source terminals316in each associated one of pixels220i,0through220i,23. After each of charge storage regions314i,0through314i,23returns to a known reset charge state, reset signal1112is removed (goes low) from reset line308i.

After reset signal1112is removed from reset line308i, sampling circuit212simultaneously acquires a voltage sample from each of readout lines3040through30423. As in image capture mode, the first voltage samples (reset voltage samples) are acquired at SHR1. Shortly after SHR1, transfer signal1114is asserted on transfer line310, thus transferring the charge from photosensors312i,0through312i,23to charge storage regions314i,0through314i,23, respectively. Then, transfer signal1114is removed (goes low) from transfer line310iand sampling circuit212simultaneously acquires the second voltage sample (the image signal) from each of readout lines3040through30423at SHS1. This completes the image capture process.

Shortly after SHS1, reset signal1112is again asserted on reset line308ithus resetting the charge state1106of charge storage regions314i,0through314i,N. After reset signal1112is removed from reset line308, for the second time, sampling circuit212simultaneously acquires a third voltage sample from each of readout lines3040through30423at SHR2. After SHR2, reset signal1108is removed from charge injection reset signal line410thus causing switch circuits5020through502Nto electrically couple terminals5160through516Nwith terminals5180through518N, respectively. As a result, the voltage1110of each test signal injection line3020through302Nis dictated by the logic state of whichever one of bits1204happens to be asserted on respective terminals5200through520N. For example, when the bit1204asserted on terminal508jof memory element500jhappens to be a “0”, switch circuit504jof column injection circuit226jelectrically couples terminals526jand522j. Coupling terminals526jand522jcauses injection line302jto couple to logical high voltage supply line404indirectly through switch circuits502jand504j. On the other hand, when the bit1204asserted on terminal508jof memory element500jhappens to be a “1”, switch circuit504jof column injection circuit226jcouples terminals526jand524j. As a result of coupling terminals526jand524j, injection line302jconnects to logical low voltage line406indirectly through switch circuits502jand504j. In this particular example, however, the 24thbit1204stored in terminal508jis a “1”, thus causing voltage1110of injection line302jto drop down to the logical low voltage of low voltage supply line406when reset signal1108is removed from charge injection reset signal line410. Of course, if the 24thbit1204happened to be a “0” instead of “1”, the voltage1110of injection line302jwould have remained at the level of logical high voltage line404upon removal of reset signal1108from charge injection reset signal line410.

Unlike when image sensor100operates in image capture mode, a second transfer signal1114is not asserted on transfer line310jafter SHR2 when image sensor100operates in test mode. Indeed, the charge states of pixels220i,0through220i,23are not dictated by incident light intensity (i.e., not by photogenerated charge accumulated by photosensors312i,0through312i,N). Rather, the charge states of pixels220i,0through220i,23are dictated by the voltage states of injection lines3020through302j, respectively. Because each of injection lines3020through302jcan have only one of the two possible voltage states (Vhi or Vlo), each of the voltage samples acquired from respective readout lines3040through304jduring SHR2 can have only one of two possible values. In effect, sampling circuit212samples simulated pixel data that is injected into pixels220i,0through220i,Nby replacing the step of transferring photogenerated charge from photosensors312i,0through312i,Ninto respective charge storage regions314i,0through314i,Nwith a step of injecting randomly generated test signals into charge storage regions314i,0through314i,N.

It is not necessary to follow every image capture process with a test process. How often the test process (injected signal sampling) is implemented depends on how fast a sensor failure must be detected. In general, a test process can follow every Nth image capture process, where N is an integer greater than zero. Optionally, only a subset of pixel rows222can be tested during each frame time (i.e., the time for completing an image capture process for every row222in pixel array202).

FIG. 13is a circuit diagram of first comparison circuit210according to an alternate embodiment of the present invention. In this particular embodiment, first comparison circuit210(FIG. 2) is configured to be selectively enabled and disabled according to control signals asserted on an additional input terminal1300thereof. One advantage to selectively enabling and disabling first comparison circuit210is that first comparison circuit210can be disabled when not in use, thus reducing the overall power consumption of image sensor100. In certain applications, it may only be necessary to carry out a comparison routine once per several frames in order to achieve some predetermined image data reliability. In such a case, it might be desirable to disable first comparison circuit210during the frames in which control signals need not be validated.

To implement selective control, first comparison circuit210further includes a plurality of transistors13020through1302M, a second plurality of transistors13040through1304M, a third plurality of transistors13060through1306M, an enable transistor1308, and an inverter1310. Each of transistors13020through1302Mincludes a first terminal1312, a second terminal1314, and a third terminal1316. As shown, each of terminals1312,1314, and1316are denoted with a subscript identifying the associated one of transistors13020through1302Mto which it belongs. Terminals13120through1312Mare connected to terminals7120through712M, respectively. All of terminals13140through1314Mof respective transistors13020through1302Mare connected to a ground terminal1318of first comparison circuit210. All of terminals13160through1316Mof respective transistors13020through1302Mare connected to a common supply line1320of first comparison circuit210.

Each of transistors13040through1304Malso includes a first terminal1322, a second terminal1324, and a third terminal1326. As shown, each of terminals1322,1324, and1326are also denoted with a subscript identifying the associate one of transistors13040through1304Mto which it belongs. Terminals13220through1322Mare connected to terminals7180through718M, respectively. All of terminals13240through1324Mof respective transistors13040through1304Mare connected to ground terminal1318of first comparison circuit210. All of terminals13260through1326Mof respective transistors13040through1304Mare connected to common supply line1320of first comparison circuit210.

Each of transistors13060through1306Nalso includes a first terminal1328, a second terminal1330, and a third terminal1332. As shown, each of terminals1328,1330, and1332are also denoted with a subscript identifying the associate one of transistors13060through1306Mto which it belongs. Terminals13280through1328Mare connected to terminals7240through724M, respectively. All of terminals13300through1330Mof respective transistors13060through1306Mare connected to ground terminal1318of first comparison circuit210. All of terminals13320through1332Mof respective transistors13060through1306Mare connected to common supply line1320of first comparison circuit210.

Transistor1308includes a first terminal1334connected to input terminal1300of first comparison circuit210, a second terminal1336connected to common supply line1320, and a third terminal1338connected to a voltage source1340of first comparison circuit210. Inverter1310includes an input terminal1342connected to common supply line1320and an output terminal1344connected to error signal output line706of first comparison circuit210.

The following example describes the operation of first comparison circuit210according to this alternate embodiment. Initially, terminal1300is at a low voltage state thus actuating transistor1308. When transistor1308is actuated, no voltage drop occurs between terminals1338and1336and, therefore, the voltage state of the node that includes line1320and input terminal1342of inverter1310is equal to the high voltage state of voltage source1340. Of course, with input terminal1342of inverter1310at a high voltage state, output terminal1344is at a low voltage state. To enable first comparison circuit210, an enable signal is asserted on terminal1300in the form of a high voltage state. This causes transistor1308to be in a nonconducting state (“turned off”), thus disconnecting line1320and input terminal1342of inverter1310from voltage source1340. After transistor1308is turned off, the voltage state of line1320and input terminal1342of inverter1310remain precharged to the high voltage state. If any one or more of XOR gates7000through700M,7020through702M, and/or7040through704Mhave noncorresponding input terminals, the associated output terminal will have a high voltage state, thus actuating (place in a conducting state) whichever one of transistors13020through1302M,13040through1304M, or13060through1306Mhas a gate connected thereto. The actuation of any one or more of transistors13020through1302M,13040through1304M, or13060through1306Mwill couple line1320and input terminal1342of inverter1310to ground terminal1318. As a result, input terminal1342of inverter1310causes output terminal1344and, therefore, error output signal line706to have a high voltage state. Of course, the high voltage state of error signal line706is the error signal that indicates one or more control signals have not been properly distributed to control signal lines3000through300M.

FIG. 14is a circuit diagram of an alternate sampling circuit1400and an alternate comparison circuit1402according to another embodiment of the present invention. It should be recognized that many of the features of sampling circuit1400are substantially similar to those of sampling circuit212and are, therefore, denoted by like reference numbers. Those substantially similar elements are not described again in detail to avoid redundancy.

In this particular embodiment, sampling circuit1400includes a first encoder1404and a second encoder1406. First encoder1404is connected to first ends830,834, and838of control signal lines802,804, and806, respectively, and is operative to encode control signals asserted thereon. First encoder1404includes an output terminal1408that is coupled to provide comparison circuit1402with encoded data indicative of control signals asserted on first ends830,834, and838of respective control signal lines802,804, and806. Second encoder1406is connected to second ends832,836, and840of control signal lines802,804, and806, respectively, and is operative to encode control signals asserted thereon. Second encoder1406also includes an output terminal1410that is coupled to provide comparison circuit1402with encoded data indicative of control signals asserted on second ends832,836, and840of respective control signal lines802,804, and806.

Comparison circuit1402includes a first input terminal1412, a second input terminal1414, and an error signal output terminal1416. First input terminal1412is connected to receive encoded data from output terminal1408of first encoder1404. Second input terminal1414is connected to receive encoded data from output terminal1410of second encoder1406.

During operation of sampling circuit1400, first encoder1404and second encoder1406simultaneously encode control signals asserted on control signal lines802,804, and806. More specifically, first encoder1404encodes the control signals from first ends830,834, and838, and second encoder1406encodes the control signals from second ends832,836, and840. Encoders1404and1406also simultaneously output the encoded data from output terminals1408and1410, respectively. Input terminals1412and1414of comparison circuit1402simultaneously receive the encoded data output from terminal1408and1410, respectively. Comparison circuit1402then determines if the encoded data received from input terminal1412corresponds with the encoded data received from input terminal1414. If the encoded data received from input terminal1412does not properly correspond with the encoded data received from input terminal1414, comparison circuit outputs an error signal from terminal1416. The error signal indicates that the control signals asserted on control signal lines802,804, and806are not being properly distributed to all of pixel readout circuits8080through808N.

The term “connected,” as used herein, means a direct electrical connection between the items connected, without any intermediate devices. The term “coupled” means either a direct electrical connection between the items connected or an indirect connection through one or more passive or active intermediary devices. The term “circuit” means either a single component or a multiplicity of components, either active and/or passive, that are coupled together to provide a desired function. The term “signal” means at least one current, voltage, charge, data or other signal.

One or more embodiments include an article of manufacture (e.g., a computer program product) that includes a machine-accessible and/or machine-readable medium. The medium may include a mechanism that provides, for example stores, information in a form that is accessible and/or readable by the machine. The machine-accessible and/or machine-readable medium may provide, or have stored thereon, one or more or a sequence of instructions and/or data structures that if executed by a machine causes or results in the machine performing, and/or causes the machine to perform, one or more or a portion of the operations or methods or the techniques shown in the figures disclosed herein.

In one embodiment, the machine-readable medium may include a tangible nontransitory machine-readable storage media. For example, the tangible non-transitory machine-readable storage media may include a floppy diskette, an optical storage medium, an optical disk, a CD-ROM, a magnetic disk, a magneto-optical disk, a read only memory (ROM), a programmable ROM (PROM), an erasable-and-programmable ROM (EPROM), an electrically-erasable-and-programmable ROM (EEPROM), a random access memory (RAM), a static-RAM (SRAM), a dynamic-RAM (DRAM), aFlash memory, a phase-change memory, or a combinations thereof. The tangible medium may include one or more solid or tangible physical materials, such as, for example, a semiconductor material, a phase change material, a magnetic material, etc. Examples of suitable machines include, but are not limited to, digital cameras, digital video cameras, cellular telephones, computer systems, other electronic devices having pixel arrays, and other electronic devices capable of capturing images. Such electronic devices typically include one or more processors coupled with one or more other components, such as one or more storage devices (non-transitory machine-readable storage media). Thus, the storage device of a given electronic device may stores code and/or data for execution on the one or more processors of that electronic device. Alternatively, one or more parts of an embodiment may be implemented using different combinations of software, firmware, and/or hardware.

The description of particular embodiments of the present invention is now complete. Many of the described features may be substituted, altered or omitted without departing from the scope of the invention. For example, the inventive features can be applied to various image sensor types (e.g., front side illuminated sensors, backside illuminated sensors, etc.). As another example, many of the circuit components and configurations (e.g., logic gates, transistor types, switches, etc.) can be substituted with alternate circuit components and configurations that carry out substantially similar functions. These and other deviations from the particular embodiments shown will be apparent to those skilled in the art, particularly in view of the foregoing disclosure.