Method of implanting during manufacture of ROM device

A ROM device with an array of cells and a method of manufacturing comprises: forming closely spaced conductors in the surface of a semiconductor substrate having a second type of background impurity. Insulation is formed on the substrate. Closely spaced, parallel, conductors on the insulation are arranged orthogonally to the line regions. Glass insulation is formed over the conductors. Reflowing the glass insulation, forming contacts and forming a metal layer on the glass insulation follow. A resist is formed, exposed forming a resist metal pattern, then etching through the resist to pattern metal and removing the resist. Depositing a resist onto the patterned metal, and exposing the second resist with a custom code pattern, developing the resist into a mask follow. Impurity ions are implanted into the substrate adjacent to the conductors through the openings in a second resist layer. The device is passivated followed by activating the implanted impurity ions by annealing the device at a temperature less than or equal to about 520.degree. C. in a forming gas or N.sub.2 atmosphere.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
This invention relates to Read Only Memory (ROM) manufacturing techniques 
and more particularly to code implanting during ROM manufacturing. 
2. Description of Related Art 
ROM devices are standard components of modern computer systems. A ROM 
comprises an array of Metal Oxide Semiconductor Field Effect Transistor 
(MOSFET's) arranged in columns and rows, wherein predetermined MOSFET's 
are either permanently conductive or nonconductive as a function of the 
variety of transistor. The alternative on/off operation of these devices 
states of the MOSFETs is adapted to use for storage of data, which remains 
in the device when the external power supply is off. 
A ROM device includes an array of parallel, closely spaced lines comprising 
regions formed of a heavily doped impurity in a semiconductor substrate 
having an opposite type of background impurity. On the surface of the 
substrate an insulating layer is formed. Another array of closely spaced 
conductive lines formed on the surface of the insulating layer is arranged 
at right angles to the spaced lines in the substrate. Insulating layers 
are formed on the upper array of conductive lines. A metallurgy layer 
connects the two arrays of lines to circuits to address the lines and to 
read the data stored in the RAM, as is well known in the art. 
At the intersection of a conductive line in the upper array which is 
commonly referred to as a "word line" and a pair of adjacent lines in the 
substrate, known as the "bit lines", a MOSFET is formed. The spaced lines 
in the substrate comprise the source and drain for the MOSFET. The 
conductive word line serves as the gate electrode of the MOSFET. Certain 
predetermined MOSFETs can be made permanently conductive by forming a 
region of an impurity of the opposite type from that in the bit lines, 
between adjacent bit lines and beneath the corresponding conductive line. 
This permanently non-conductive region is known as a code implant, and it 
is placed in the substrate to provide specific binary data. Such a ROM is 
constructed of NAND circuits as contrasted with the NOR type circuits 
employed in connection with this invention. 
The conventional manufacturing process is to form the code implant regions 
very early in the ROM fabrication process, since an annealing step is 
required to activate the implanted impurity and also to recrystallize any 
implanted areas of the substrate. The annealing process involves heating 
the substrate above an acceptable temperature, which would damage the 
completed device, since the aluminum metallization conventionally used is 
damaged above a temperature of about 400.degree. C. to about 450.degree. 
C. for more than a minimum time interval, and the maximum possible 
temperature is the melting point of aluminum which is about 660.degree. C. 
FIG. 1A shows an early stage of a prior art process for forming a ROM 
commences with a N- doped semiconductor substrate 10 upon which a P-well 
12 is formed by doping with an opposite (P-) type of dopant followed by 
forming buried N+ bit lines (not shown in FIG. 1A.) Above the P-well 12 is 
formed a silicon dioxide gate oxide layer 14 about 200 .ANG. thick. Above 
the gate oxide layer 14, word lines 15 are formed from a layer of 
polysilicon 16 followed by a layer of a refractory silicide (polycide) 18, 
each about 1,500 .ANG. thick. Adjacent to the word lines 15 are formed 
silicon dioxide spacers 20. The refractory silicide is selected from 
silicides of refractory metals such as Ta, W, Ti and Mo. 
In FIG. 1B, the prior art process continues with application of a layer of 
photoresist 22 which is patterned to form openings 21 therein for 
application of boron B.sup.11 dopant ions 23 to be implanted between 
adjacent buried N+ bit lines (not shown) and beneath the polysilicon word 
lines 15 with an ion implanter operating at an energy level of about 180 
keV. 
In FIG. 1C, the prior art process continues with formation of a layer 24 of 
USG (Undoped Silicon Glass) by APCVD (Atmospheric-Pressure Chemical Vapor 
Deposition) to a thickness of about 1,500 .ANG.. 
In FIG. 1D, the next step of the prior art process is to deposit a BPSG 
layer 26 to a thickness of about 7200 .ANG. with boron (B) about 3.0% and 
phosphorous (P) about 4.6%. The process used in the prior art to deposit 
the BPSG layer 26 also comprises APCVD. 
In FIG. 1E, the prior art device of FIG. 1D has been heated to reflow the 
BPSG layer 26 at a temperature of about 900.degree. C. which reflow the 
BPSG layer 26, thereby planarizing the USG layer 24 and BPSG layer 26 with 
a combined thickness remaining at about 8700 .ANG.. 
In FIG. 1F, after the device of FIG. 1E has been subjected to formation of 
contacts by photolithography and is coated with a metal layer 28. A 
process of photolithography and etching is involved. The metal is 
deposited first by evaporation or preferably by sputtering. Photoresist is 
then applied, masked and developed to form the pattern desired. 
Next in the prior art process, there is passivation and pad etching 
followed by formation of the alloy by annealing at 410.degree. C. in a 
furnace. 
The conventional mask ROM programming methods include: programming by field 
oxide, channel ion implant, etc. It is desirable for a mask ROM that small 
die size, coincides with short turn around time. However, it is difficult 
when a conventional process, such as one of the above mentioned methods, 
is used for the process to achieve a short turn around time. This 
invention uses existing facilities in an industrial laboratory to achieve 
the short turn around time goal in an industrial factory. 
In Hong et al "Very Late Programming Process for Mask ROM" (Ser. No. 
08/044,936) a process of ROM manufacture includes buried bit lines, 
covered by a thin gate oxide layer on which polysilicon word lines are 
formed which are covered with a thick film of BPSG between 3,000 .ANG. A 
and 8,000 .ANG. thick. Metallization is applied formed of aluminum, a 
refractory metal, refractory metal silicide or heavily doped polysilicon. 
The refractory metal or the refractory metal silicide are stated to be 
preferred because they will withstand higher temperatures than aluminum 
and can be annealed at 850.degree. C. for about 15 minutes or 900.degree. 
C. for 5 minutes. A resist layer is applied and patterned to define a code 
implant pattern. The code implantation is performed preferably with boron 
B.sup.11 ions at a power of about 180 keV with an implantation dosage of 
about 1 E 13 to 1 E 14 atoms/cm.sup.2. After implantation of the ions they 
are activated. Preferably, a passivating layer of silicon dioxide or 
silicon nitride in the range of 5,000 .ANG. to 10,000 .ANG. thick is 
deposited by PECVD. When the metallization is aluminum with a thick 
barrier metal layer, the activation of the implanted ions and 
recrystallization "must be done by rapid thermal annealing (RTA). In the 
critical RTA process . . . the device must be heated to a temperature not 
greater than about 650.degree. C., but above a temperature of 550.degree. 
C. and maintained for a time in the range between 3 and 10 minutes. The 
atmosphere of the RTA process may be an inert gas such as nitrogen." 
Applicants find that it is difficult to employ an implant energy of 180 keV 
to implant through a thickness of 3,000 .ANG. or particularly through a 
structure comprising a 9,000 .ANG. thick combination of BPSG and a 
polycide word line. Accordingly an object of this invention is to use a 
thinner layer of BPSG with a thickness less than about 3,000 .ANG.. 
The double charge method has a very low throughput, which is not well 
adapted to mass production. 
The late programming etch back method is not adapted to a practical 
application from the point of end point issues and it is more complicated 
than desired. Accordingly an object of this invention is to avoid the late 
programming etch back method. 
An object of this invention is to employ a lower temperature annealing 
process to achieve a high throughput. 
Another object of this invention is an improved narrow metal pattern 
processing technique. 
A further object of this invention is to employ an improved thinner BPSG 
layer. 
SUMMARY OF THE INVENTION 
In accordance with this invention a Read Only Memory device with an array 
of cells and a method of manufacturing comprises: 
a) forming a plurality of closely spaced line regions with a first impurity 
type in and adjacent to the surface of a semiconductor substrate having a 
background impurity of a second opposite type, 
b) forming a thin insulating layer on the surface of the substrate, 
c) forming a plurality of closely spaced, parallel, electrically conductive 
lines on the thin insulating layer arranged orthogonally relative to the 
line regions, 
d) forming a glass insulating layer over the conductive lines, 
e) reflowing the glass insulating layer, 
f) forming contacts, 
g) forming a metal layer on the glass insulating layer, 
h) depositing a resist layer on the metal layer, 
i) exposing the resist layer with a metal pattern, etching through the 
resist layer to form patterned metal and removing the resist layer, 
j) depositing a second resist layer onto the device, and exposing the 
second resist layer with an ion implantation pattern, 
k) developing the resist layer into a mask, 
l) implanting impurity ions into the substrate adjacent to the conductive 
lines through the openings in the second mask, 
m) removing the second resist layer, 
n) passivating the device, and 
o) activating the implanted impurity ions by annealing the device at a 
temperature less than or equal to about 520.degree. C. in a predetermined 
gas atmosphere, 
whereby the metallurgy and the electrical contacts to the substrate, line 
regions and conductor lines are protected from adverse effect during 
annealing. 
Preferably, the predetermined gas atmosphere comprises N.sub.2 and H.sub.2 
or N.sub.2 only. 
Preferably, the glass insulating layer comprises a sublayer of undoped 
glass and an overlayer of doped glass. Preferably, the overlayer of doped 
glass comprises glass doped with boron and phosphorous. 
Preferably, the overlayer of doped glass comprises glass doped with boron 
within the range from about 2.5 weight percent to about 5 weight percent 
and a concentration of phosphorous within the range from about 3 weight 
percent to about 5.5 weight percent. 
Preferably, the overlayer of doped glass comprises glass doped with about 
3.0 weight percent boron and 5.2 weight percent phosphorous. 
Preferably, the metallization comprises a layer of aluminum having a 
thickness within the range from about 8,000 .ANG. to about 11,000 .ANG., 
and a thin upper layer of titanium nitride having a thickness within the 
range from about 100 .ANG. to about 400 .ANG.. 
Preferably, the aluminum is about 10,000 .ANG. thick and the layer of 
titanium nitride is about 300 .ANG. thick. 
In accordance with this invention a thin BPSG layer is formed with a 
thickness from about 2,000 .ANG. to about 3,000 .ANG., preferably about 
1,000 .ANG. USG and about 2,000 .ANG. BPSG. 
For ultra small dimensions, in accordance with this invention, post metal 
ROM lithography techniques are employed as an antireflection coating. 
In accordance with this invention an antireflection coating is employed 
comprising comprising titanium nitride (TiN), aluminum (Al), titanium 
nitride (TiN) on top of an aluminum layer.

DESCRIPTION OF THE PREFERRED EMBODIMENT 
Referring to FIG. 2, a fragmentary plan view of a ROM in accordance with 
this invention is shown. A pair of word lines 35 are shown extending from 
left to right across the page. A set of buried bit lines 29 in the 
semiconductor are shown extending at right angles to the word lines 35, 
within the semiconductor substrate 30. A metal structure 48 comprises 
TiN/Al/TiN (800 .ANG./10,000 .ANG./300 .ANG.) which serves the purpose of 
providing a main bit line 29 in cooperation with a word line 35 to access 
a specified bit of ROM data. Beneath the metal element 48 is a buried bit 
line 29. Between each buried bit line 29 is the ROM channel and placement 
of metal should be avoided in this region. Element 50 comprises a selector 
(polycide word line) which serves the purpose of selection of one of two 
adjacent cells. 
Element 52 comprises a custom ROM code outside of the cell area which 
serves the purpose of a Mask ROM data storage element. Element 54 
comprises a buried drain which serves the purpose of a main bit line pick 
up for bank cells. A 16, 32 or . . . word line set is employed. Element 56 
comprises a contact which serves the purpose of interconnection between 
the main metal bit line and bank cells. Metal 55 bypasses the cell channel 
area. 
As shown in FIG. 3A an early step in the process of forming a ROM device in 
accordance with this invention commences with a N- doped semiconductor 
substrate 30 upon which a P-well 32 is formed by doping with an opposite 
(P-) type of dopant. Above the P-well 32 is formed a silicon dioxide gate 
oxide layer 34 about 200 .ANG. thick. Above the gate oxide layer 34, word 
lines 35 are formed from a sublayer of polysilicon 36 followed by an 
overlayer of a refractory metal silicide (known as polycide) 38, each 
about 1,500 .ANG. thick. Adjacent to the word lines 35 are formed silicon 
dioxide spacers 40. The refractory metal silicide is preferably tungsten 
silicide, polysilicon, titanium silicide, etc. 
In FIG. 3B, the process of the present invention continues with formation 
of a thin layer 44 of USG (Undoped Silicon Glass, which is sometimes 
referred to as undoped BPSG) by APCVD (Atmospheric-Pressure Chemical Vapor 
Deposition or PECVD (Plasma Enhanced C.V.D.) to a thickness of about 1,000 
.ANG.. 
In FIG. 3C, the next step of the process of the present invention is to 
deposit a BPSG (or BPTEOS) layer 46 to a thickness of preferably about 
2,000 .ANG. (within the range from about 1,000 .ANG. to about 2,000 .ANG.) 
with a preferred concentration of boron (B) of about 3.0 wt. % (preferably 
within the range from about 2.5 wt. % to about 5 wt. %) and with a 
preferred concentration of phosphorous (P) of about 5.2 wt. % (preferably 
within the range from about 3 wt. % to about 5.5 wt. %). The process used 
to deposit the BPSG layer 46 comprises an instrument selected from APCVD, 
PECVD, LPCVD (Low Pressure C.V.D.) which deposits BPSG, BPTEOS, TEOS, etc. 
The typical BPTEOS composition of a boron-phosphorous SiO.sub.2 is boron 4 
wt. %, phosphorous 4 wt. %. The range is the same as above. 
In FIG. 3D, the device of FIG. 3C has been heated to reflow the device of 
FIG. 3C covered with BPSG layer 46 at a temperature of about 900.degree. 
C. which planarizes the combined USG layer 44 and BPSG layer 46. The 
undoped USG layer 44 remains about 1,000 .ANG. thick. The thickness of 
layer 46 is reduced to about 1,500 .ANG. thickness and the combined 
thickness of layers 44 and 46 is reduced to about 2,500 .ANG. in the 
locations above the word line region. The combined word lines 35 (layers 
36 and 38) remain about 3,000 .ANG. thick for a total thickness of about 
5,500 .ANG.. The ranges of thickness of USG after the reflow is about 
1,000 .ANG.. The thickness of the BPSG after the reflow is within the 
range from about 1,000 .ANG. and about 2,000 .ANG.. 
Next a step of formation of contact 56 is performed involving formation of 
a resist mask and etching to form contact 56 as shown in FIG. 2. 
In FIG. 3E, after the device of FIG. 3D has been subjected to formation of 
contacts by photolithography and etching, it is coated with a metal layer 
48, preferably by sputtering. In accordance with this invention, the 
metallization is a first layer of titanium (Ti) about 500 .ANG. thick. 
Then an RTA (Rapid Thermal Anneal) is performed to form TiSi.sub.2. Next, 
aluminum (Al) is deposited preferably about 10,000 .ANG. thick (within the 
range from about 8,000 .ANG. to about 11,000 .ANG.) and a thin upper layer 
of TiN (titanium nitride) preferably about 300 .ANG. thick (within the 
range from about 100 .ANG. to about 400 .ANG..) 
In FIG. 3F, after the metal 48 is deposited, photoresist is then applied, 
masked and developed in the form of the metal pattern desired. The metal 
48 is etched by a metal etching process leaving metal in the area desired 
for the code implant. However, during the etching substantially all of the 
BPSG layer 46 is also removed, leaving behind the layer beneath comprising 
the 1,000 .ANG. thick USG layer 44 (with a range of thicknesses of USG 
layer 44 between about 500 .ANG. and 1,500 .ANG..) Above the channel a 
layer of gate oxide 34 (200 .ANG.), polysilicon layer 36 (1,500 .ANG.), 
polycide 38 (1,500 .ANG.), and USG layer 44 (1,000 .ANG..) 
In FIG. 3G, the process continues with application of a layer of 
photoresist 42 which is patterned for application of ions 43 boron 
B.sup.11 dopant to be implanted adjacent to the spacers 40 with an ion 
implanter operating at an energy level of about 180 keV (which can range 
from about 100 keV to about 200 keV with an implantation dosage 
concentration of about 1 E 14 atoms/cm.sup.2 to about 4 E 15 
atoms/cm.sup.2. 
Following the steps shown in FIG. 3G, the next steps are code etching, 
passivation and pad etching. 
Subsequently, the final step of the process is formation of the alloy by 
annealing at about 450.degree. C. in a furnace. The temperature can range 
from about 400.degree. C. to about 520.degree. C. 
This invention is adapted to be implemented into an industrial standardized 
enhancement code mask ROM process. The very limited cost of employing this 
method is simply the cost of fabrication of a new metal mask. The metal 
pattern of the mask should bypass all the ROM cell channel area inside a 
ROM product, where ROM coding area may be implanted into it, as shown in 
FIG. 3. Thus, the threshold voltage of these ROM cells increases almost an 
order of magnitude from about 0.7 Volts to about 5.5 Volts. The two 
different states of a ROM transistor can be permanently programmed in 
either the "on" or the "off" state during its fabrication process, by 
using a custom designed code mask. 
Details of the process steps of this method as shown in FIGS. 3A to 3G can 
be compared with a traditional method which is shown in FIGS. 1A to 1E. 
The cycle time from the time of receiving a custom designed code to the 
time at which the wafer process is finished is reduced drastically by 
using the method of FIGS. 3A-3G. 
Key features of the process of this invention include: 
a) Excellent planarization of BPSG (Boron Phosphorous Silicate Glass) film 
is achieved by adjusting boron vs. phosphorous ratio. The BPSG film should 
be thin enough for a memory current implanter to implant boron ions 
through the polysilicon gate of ROM cell transistor, directly into the 
channel region. The cross section is flattened. The flatter the BPSG film, 
the greater the accuracy with which the threshold voltage can be 
controlled in the case of coding, because the boron project range is 
located almost a uniform distance beneath the channel region. 
b) A narrow metal pattern is processed by using an anti-reflection coating 
technique. TiN.apprxeq.300 .ANG. The thin TiN film provides an 
anti-reflection advantage by reducing the reflection index very 
substantially as compared with an aluminum film. 
c) Post-metal ROM code lithography technique: The photo-resist should be 
thick enough to avoid the type of thick metal patterns attributable to 
inadequate photoresist coverage. In addition, resolution should be 
maintained as well. (A resist such as Fuji Hunt FH 6400L photoresist is 
particularly helpful in achieving our goals. 
d) A low temperature annealing process is employed in a furnace with 
parameters of 450.degree. C. for 30 minutes in an atmosphere of a 
predetermined gas, e.g. N.sub.2 or forming gas. Forming gas containing H2 
and N2 (a traditional gas for alloying) is used to prevent metal 
oxidation. 
Activation of boron which has been implanted is approximately 45%, as 
compared with 100% activation of B.sup.11 at a temperature of 900.degree. 
C. The B.sup.11 dopant has been increased from the traditional process 
value of 9 E 13/cm.sup.2 to a value of 2 E 14/cm.sup.2. 
e) A zero degree medium current ion implanter performs a low damage ion 
implant process. 
Circuit characterization of a 4 Megabit and an Megabit mask ROM has been 
verified by using the present invention. The resultant product made by 
this invention is successful both in terms of circuit characterization and 
device reliability. 
Advantages of the present invention include as follows: 
1. After the metal is etched it is then programmed by a medium current 
implanter to reach a "short turn around time" and to avoid the damage 
issue which would arise with the use of a high voltage implanter. 
2. The invention can be implemented in a flat cell ROM structure permitting 
a small die size. 
3. The wafer acceptability test can be held before the programming process 
and accordingly a greater yield prediction of 1/2 cell (on cell) can be 
achieved reducing waste. 
4. 0.8 .mu.m NMOS hot carrier stress. Device reliability is not affected by 
this invention. The circuit's ESD (Electro-Static Discharge) technology 
and latch-up even performance are qualified by using the mil-standard at 
the industrial level. 
5. There is no loss of yield from using this process. 
While this invention has been described in terms of the above specific 
embodiment(s), those skilled in the art will recognize that the invention 
can be practiced with modifications within the spirit and scope of the 
appended claims, i.e. that changes can be made in form and detail, without 
departing from the spirit and scope of the invention. Accordingly all such 
changes come within the purview of the present invention and the invention 
encompasses the subject matter of the claims which follow.