Apparatus, method and program for processing information

Apparatus and method for processing information may determine whether a migration condition exists by a source information processing unit executing a program. When a migration condition is determined to exist by the source information processing unit, a destination information processing unit may determine whether an instruction to be executed of the program is a predetermined instruction. The instruction to be executed is converted by an instruction emulator, when a result of a determination by the destination information processing unit is the predetermined instruction.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority from Japanese Patent Application No. JP 2009-125206 filed in the Japanese Patent Office on May 25, 2009, the entire content of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an apparatus, a method, and a program for processing information and, in particular, to an apparatus, a method, and a program for efficiently executing a program subject to migration of the program.

2. Description of the Related Art

Program migration, such as program movement or a program conversion process, is typically used.

Available as a related art technique for executing migration is an emulation method such as QEMU (Registered Trademark of Fabrice Bellard).

Other techniques are also disclosed in Ben Serebrin, “Cross-vendor migration: What do you mean my ISA isn't comptabile?”, Xen Summit, February 2009, and FlexMigration (Intel/DOC-2538, retrieved Apr. 23, 2009 through the Internet).

SUMMARY OF THE INVENTION

The needs described below are not sufficiently satisfied if the above-described related art techniques are merely applied.

There is currently a growing necessity to execute migration of a currently running program between central processing units (CPUs) of different types, for example, a high-end CPU and a low-power consuming CPU. Program migration includes a program movement and a conversion process). Such a need is not sufficiently satisfied.

It is thus desirable to execute efficiently a program prior to and subsequent to the program migration.

In accordance with an aspect of the invention, an apparatus for processing information includes a source information processing unit to determine whether a migration condition exists when executing a program; and a destination information processing unit to determine whether an instruction to be executed of the program is a predetermined instruction, when a migration condition is determined to exist by the source information processing unit.

In accordance with another aspect of the invention, a method for processing information includes determining whether a migration condition exists by a source information processing unit executing a program; and when a migration condition is determined to exist by the source information processing unit, determining by a destination information processing unit whether an instruction to be executed of the program is a predetermined instruction.

In accordance with another aspect of the invention, a system for executing a program includes a source information processing unit having a processing capability to implement a first instruction set and operable to execute the program; and a destination information processing unit having a processing capability to implement a second instruction set. The first instruction set includes at least one instruction common to the second instruction set and at least one instruction not common to the second instruction set. The destination information processing unit is operable to determine whether an instruction to be executed of the program is common or not common to the second instruction set. The instruction to be executed is converted by an instruction emulator only when the instruction to be executed is not common to the second instruction set. The instruction to be executed is executed through a processing capability of the destination information processing unit when the instruction to be executed is common to the second instruction set.

The program is thus efficiently executed subsequent to the migration thereof.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

To help understand the present invention, related art is summarized first. Information processing apparatuses of three embodiments of the present invention (first through third embodiments) are then described.

1. Related Art

The emulation technique is available as a related-art technique for executing program migration as previously described.

With the emulation technique, a program to be executed by a CPU A implementing an instruction set A is executed by a CPU B implementing an instruction set B different from the instruction set A. More specifically, an instruction of the instruction set A is converted into an instruction of the instruction set B. The CPU B can thus execute the program in accordance with an instruction of the converted instruction set B.

The emulation technique has the advantage that the instruction of the instruction set A can be executed by the CPU B implementing the instruction set B completely different from the instruction set A.

The emulation technique takes long process time to convert an instruction of the instruction set A into an instruction of the instruction set B. The conversion process time is as long as or longer than time to execute the converted instruction set B. The migration process based on the emulation technique can substantially slow the execution of a program on the CPU B.

Although the instruction set A and the instruction set B commonly share major instructions, the two instruction sets are still partially different from each other. Even in such a case, the emulation technique converts all the instructions of the instruction set A into instructions of the instruction set B.

If the instruction set A and the instruction set B commonly share major instructions with a partial difference in the other instructions therebetween, the use of the emulation technique is not efficient.

It is also desirable to embody a virtual machine based on virtual technique, and to execute migration of the virtual machine.

The virtual technique refers to a technique of generating a virtual hardware structure using software and running a software application program on the virtual hardware structure.

The virtual machine refers to a set of software and data for causing an operating system (OS) or an application software program to operate like a physical computer. The virtual machine includes a variety of virtual devices having functions equivalent to those of a central processing unit (CPU), a memory, a hard disc drive (HDD), and a network controller.

The virtual machine is created on a physical hardware structure, and controlled by a virtual machine monitor, such as VMware (Registered Trademark of VMware, Inc.) or Xen (Registered Trademark of XenSource, Inc.).

The migration of the virtual machine refers to a movement of the virtual machine from one virtual machine monitor to another virtual machine monitor.

The virtual machine implements the same instruction set as the instruction set of a physical CPU. It is difficult to migrate merely a virtual machine being operated by a CPU A implementing an instruction set A to a CPU B implementing an instruction set B.

Another technique of migrating a program is disclosed in Ben Serebrin, “Cross-vendor migration: What do you mean my ISA isn't comptabile?”, Xen Summit, February 2009. The disclosed technique executes migration between CPUs developed by different vendors. The disclosed technique allows a program to migrate anyway between CPUs commonly sharing a major instruction set but still with a partial instruction difference therebetween in the other instructions. If a system include a high-end CPU and a low-end CPU, an extended instruction present only on the high-end CPU remains unused. Even with the disclosed technique, the high-end CPU has difficulty achieving an originally intended performance.

FlexMigration <URL:http://communities.intel.com/openport/docs/DOC-2538> (retrieved via the Internet, Apr. 23, 2009) discloses a hardware structure called FlexMigration manufactured by Intel Corporation. The hardware permits migration between CPUs of different generations by making a new generation CPU look like an old generation CPU. If an extended instruction causing a new-generation. CPU to perform a high-end operation is added, FlexMigration has difficulty in using the extended instruction. The new-generation CPU fails to achieve an originally intended performance.

AMD has proposed a hardware product called AMD Virtualization as another technique of program migration. As FlexMigration, AMD-V (virtualization) also makes a new-generation CPU look like an old-generation CPU in order to migrate a program between CPUs of different generations.

As with FlexMigration, the new-generation CPU has difficulty in achieving an originally intended performance in AMD-V.

The inventor of this invention has invented a technique that executes, efficiently and with an originally intended performance maintained, program migration between CPUs commonly sharing major instructions but still with a part of the other instructions being different. The CPUs may be different in generation or may be manufactured by different vendors. Information processing apparatuses incorporating such a technique are described below as three embodiments of the present invention.

2. First Embodiment

FIG. 1is a block diagram illustrating an information processing apparatus of a first embodiment of the present invention.

In this specification, the word system refers to a whole system including a plurality of units, and a processing unit. More specifically, the information processing apparatus illustrated inFIG. 1may be constructed of a plurality of units housed in separate cases. In accordance with the first embodiment, however, the information processing apparatus is a single unit housed in a single case.

The information processing apparatus illustrated inFIG. 1includes a CPU11A and a memory12A connected to the CPU11A. The memory12A includes a virtual machine13and a virtual machine monitor14A.

The information processing apparatus illustrated inFIG. 1further includes a CPU11B and a memory12B connected the CPU11B. The memory12B includes a virtual machine monitor14B. The virtual machine monitor14B includes an instruction emulator15.

The CPU11A implements an instruction set A. The CPU11B implements an instruction set B.

The instruction set A and the instruction set B commonly share major instructions. The instruction commonly shared by the instruction set A and the instruction set B is referred to as a common instruction. The instruction set A includes an instruction that is absent in the instruction set B, and that instruction is referred to as an instruction X. The instruction set B includes the common instruction but does not include the instruction X.

The virtual machine13includes a program composed of an instruction of the instruction set A. The program of the virtual machine13is executed through the capability of the CPU11A connected to the memory12A including the virtual machine13.

The virtual machine monitors14A and14B are constructed as a program that provides the virtual machine13with an execution environment not dependent on hardware.

The instruction emulator15is a program having a function of converting the instruction X present in the instruction set A but absent in the instruction set B into an instruction of the instruction set B. The operation of the instruction emulator15is described later with reference toFIG. 2.

Referring toFIG. 1, the virtual machine13under the control of the virtual machine monitor14A operates on the memory12A. The program of the virtual machine13is executed through the capability of the CPU11A implementing the instruction set A.

The structure of the information processing apparatus of the first embodiment has been discussed with reference toFIG. 1. The migration of the virtual machine13is described below with reference toFIG. 2.

Referring toFIG. 2, the virtual machine13may now be migrated from the memory12A to the memory12B.

The virtual machine13moves from the memory12A to the memory12B through the migration process, but the program executed by the virtual machine13is constructed of the instructions of the instruction set A. Through the migration process, however, the virtual machine13is moved to the memory12B connected to the CPU11B implementing the instruction set B.

More specifically, the program of the virtual machine13is executed through the capability of the CPU11B. Although the common instruction can be executed through the capability of the CPU11B as previously discussed, the CPU11B has difficulty in executing the instructions other than the common instruction.

Subsequent to the migration process, the program of the virtual machine13operates as described below in response to the instruction.

The common instruction as a major portion of the program of the virtual machine13is executed through the capability of the CPU11B.

An instruction not carried out through the capability of the CPU11B, i.e., an instruction other than the common instruction, is transferred from the virtual machine13to the virtual machine monitor14B. The instruction emulator15in the virtual machine monitor14B converts the instruction other than the common instruction (not common instruction) into an instruction of the instruction set B. The instruction converted by the instruction emulator15is executed through the capability of the CPU11B in a fashion equivalent to a fashion that the not common instruction is executed through the capability of the CPU11A. The instructions the CPU11B does not execute include an instruction to check the type of a CPU (such as a CPUID instruction of Intel Corporation, hereinafter simply referred to as a CPUID instruction), and the instruction X.

With this arrangement, the information processing apparatus of the first embodiment provides the following advantages.

The CPU11A may be a high-end CPU but with high power consumption. The CPU11B may be a low-end CPU but with lower power consumption.

In such a case, the virtual machine13may be migrated from the memory12A having the high-power consuming CPU11A connected thereto to the memory12B having the low-power consuming CPU11B connected thereto without interrupting the program.

An instruction operating at a high-end throughput is executed through the capability of the CPU11A and an instruction not calling for a high-end throughput is executed through the capability of the CPU11B. With this arrangement, the information processing apparatus of the first embodiment embodies a system that achieves high-end performance and low-power consumption features.

FIG. 3is a flowchart illustrating the migration process of the virtual machine13from the memory12A to the memory12B discussed with reference toFIG. 2.

The CPU11A connected to the memory12A on which the virtual machine13was present prior to the migration is referred to as a migration source CPU11A. The CPU11B connected to the memory12B to which the virtual machine13has moved through the migration process is referred to as a migration destination CPU11B.

In step S1, the virtual machine13executes the program through the capability of the migration source CPU11A.

In step S2, the migration source CPU11A determines whether a migration condition is satisfied. For example, the migration condition is that a user has issued a migration instruction. Also, for example, if a high-end CPU11A is executing a high-end instruction, and a next instruction calls for no high-end throughput, a migration condition may be determined to be satisfied.

If no migration condition is satisfied with no branch followed in step S2, processing returns to step S1to repeat step S1and subsequent steps.

Steps S1and S2are cycled through until the migration condition is satisfied with the program of the migration source CPU11A executed.

If the migration condition is satisfied with yes branch followed in step S2, processing proceeds to step S3.

In step S3, the migration source CPU11A executes a migration process. More specifically, referring toFIG. 2, the virtual machine13is migrated from the memory12A to the memory12B.

In step S4, the virtual machine13executes the program through the capability of the migration destination CPU11B, and the migration process ends. The process of the program execution performed by the virtual machine13through the capability of the migration destination CPU11B is described with reference toFIG. 4.

FIG. 4is a flowchart of the program executed by the virtual machine13through the capability of the migration destination CPU11B in step S4of the migration process ofFIG. 3. The process is hereinafter referred to as an instruction execution process at the migration destination.

In step S11, the migration destination CPU11B determines whether an instruction to be executed is a CPUID instruction or an instruction X. Alternatively, in step11the migration destination CPU11B determines whether an instruction to be executed is a common instruction.

If the instruction to be executed is neither the CPUID instruction nor the instruction X, i.e., the instruction to be executed is a common instruction with no branch followed in step S11. Processing proceeds to step S13.

In step S13, the virtual machine13executes the instruction through the capability of the migration destination CPU11B, and the process ends.

If the instruction to be executed is either the CPUID instruction or the instruction X, yes branch is followed in step S11. Processing proceeds to step S12.

In step S12, the instruction emulator15converts the instruction (the CPUID instruction or the instruction X) into an instruction of the instruction set B. Further in step S12, the virtual machine13executes the instruction converted by the instruction emulator15through the capability of the migration destination CPU11B.

If the instruction is either the CPUID instruction or the instruction X, the instruction emulator15converts the instruction. The virtual machine13executes the converted instruction and the major instructions through the capability of the CPU11B.

In accordance with the first embodiment, the instruction emulator15does not convert all the instructions. The instruction emulator15converts an instruction to be executed only when the instruction to be executed is not common to the instruction set executed through the capability of the migration destination CPU11B (the instruction X or the CPUID instruction). The instruction to be executed converted by the instruction emulator15is executed through the capability of the migration destination CPU11B. The information processing apparatus of the first embodiment shortens time for the emulation process. As a result, the information processing apparatus of the first embodiment executes the virtual machine13efficiently prior to and subsequent to the migration of the virtual machine13.

The first embodiment of the present invention has been discussed with reference toFIGS. 1 through 4. A second embodiment of the present invention is described below with reference toFIG. 5.

3. Second Embodiment

FIG. 5illustrates a functional structure of an information processing apparatus of a second embodiment of the present invention, different from the structure of the information processing apparatus illustrated inFIG. 1.

Referring toFIG. 5, elements identical to those illustrated inFIG. 1are designated with the same reference numerals and the discussion thereof is omitted here as appropriate.

The information processing apparatus illustrated inFIG. 5may be partitioned into a plurality of units housed in separate cases. In accordance with the second embodiment, however, however, the information processing apparatus is a single unit housed in a single case.

The information processing apparatus illustrated inFIG. 5includes CPU11A, CPU11B, memory12A, and HDD16. The memory12A is shared by the CPU11A and the CPU11B. The HDD includes the virtual machine monitor14B having the instruction emulator15. The virtual machine monitors14A and14B can interchangeably be substituted for each other between the memory12A and the HDD16.

The virtual machine13is migrated in this arrangement through the process steps described below.

The virtual machine monitor14A is evacuated into the HDD16other than the memory12A. The virtual machine monitor14B is then moved to the memory12A. The virtual machine13is thus migrated.

In other words, the virtual machine13is migrated by transferring the virtual machine monitor14A to the HDD16, and the virtual machine monitor14B to the memory12A. The program of the virtual machine13is executed through the capability of the CPU11B subsequent to the migration process.

The second embodiment of the present invention has been discussed with reference toFIG. 5.

The first and second embodiments emulate only the instruction X absent on the migration destination CPU11B as described above, thereby executing efficiently the migration of the virtual machine13.

In contrast, in a third embodiment of the present invention, a program including the instruction X is suspended prior to the execution of the migration. In accordance with the third embodiment, only a program including the common instruction is migrated, and a program including the instruction X is not migrated. The program including the instruction X is resumed again by the migration destination CPU11B subsequent to the migration process.

In other words, only the program including the common instruction is migrated and is then continuously executed on the migration destination in the third embodiment. The program including the instruction X is suspended prior to the migration process, and then resumed again on the migration destination.

FIG. 6is a functional block diagram of a structure of the information processing apparatus in accordance with the third embodiment of the present invention, different from the structure illustrated inFIG. 1.

Referring toFIG. 6, elements identical to those illustrated inFIG. 1are designated with the same reference numerals and the discussion thereof is omitted here as appropriate.

The information processing apparatus ofFIG. 6may be constructed of a plurality of units. In accordance with the present embodiment, however, the information processing apparatus is a single unit housed in a single case.

The information processing apparatus ofFIG. 6includes the virtual machine monitor14A including a control panel17A. The virtual machine monitor14B includes a control panel17B.

The virtual machine monitors14A and14B can control the respective virtual machines13thereof. The virtual machine monitors14A and14B, and the virtual machine13are controlled by interfaces of the control panels17A and17B.

The control panels17A and17B are programs implementing functions controlling the virtual machine monitors14A and14B, and the virtual machine13. The control panels17A and17B can communicate with each other via a network or the like.

The virtual machines13can mutually access the control panels17A and17B.

FIGS. 7 and 8illustrate a structure of program21executed by the information processing apparatus of the third embodiment.

FIG. 7illustrates the structure in which an instruction string31composed of an instruction set A and an instruction string32composed of an instruction set B, out of the program21executed by the information processing apparatus of the third embodiment, are simply juxtaposed. An example of the program illustrated inFIG. 7is a universal binary that operates with each of Power PC (Registered Trademark of IBM) and x86 (Registered Trademark of Intel Corporation).

FIG. 8illustrates the program22executed by the information processing apparatus of the third embodiment. The program22illustrated inFIG. 8is a typical program including the instruction set A and the instruction set B sharing major instructions with a part of the other instructions thereof being different.

The program22illustrated inFIG. 8includes an instruction string33as a portion common to both the instruction set A and the instruction set B. Furthermore, the program22illustrated inFIG. 8includes an instruction string34as an extended portion of the instruction set A. The instruction string34as the extended portion of the instruction set A is an instruction string including an instruction that is present in the instruction set A but absent in the instruction set B. The program22illustrated inFIG. 8includes an instruction string35as an extended portion of the instruction set B. The instruction string35as the extended portion of the instruction set B is an instruction string including an instruction that is present in the instruction set B but absent in the instruction set A.

In view of the structure of the program commonly sharing the major instructions with a partially different instruction set, the structure ofFIG. 8is smaller in program size than the structure ofFIG. 7. In the discussion that follows, the third embodiment employs the program having the structure illustrated inFIG. 8.

The program illustrated inFIG. 8includes an instruction x=ASM(“CPUID;”) to check the type of each CPU.

The instruction set different from CPU to CPU is executed in each instruction string branched depending on the value of the results of the CPUID instruction, for example, in the instruction string34as the extended portion of the instruction set A and the instruction string35as the extended portion of the instruction set B.

More specifically, if the type of the CPU is found to be the CPU11A in response to an if instruction (X=CPU for the instruction set A), the instruction of the instruction string34as the extended portion of the instruction set A is executed. If the type of the CPU is found to be the CPU11B in response to an else if instruction (X=CPU for the instruction set B), the instruction of the instruction string as the extended portion of the instruction set B is executed.

The program executed by the information processing apparatus of the third embodiment has been discussed with reference toFIGS. 7 and 8. In accordance with the third embodiment as described above, the program including an instruction that is difficult for the migration destination CPU11B to execute is not migrated. To migrate the virtual machine13, whether the program of the virtual machine13includes an instruction difficult for the migration destination CPU11B to execute is to be determined.

A method of determining whether an instruction difficult for the migration destination CPU11B to execute is present is described below.

Two types of methods, i.e., a static method and a dynamic method are available to determine whether an instruction difficult for the migration destination CPU11B to execute is present.

In the static method, the program is reverse-engineered to determine whether the program includes a CPUID instruction or an X instruction.

In the dynamic method, whether the CPUID instruction or the instruction X has been executed or not is determined.

The determination methods of determining whether the program can be migrated or not include a static method, a dynamic method, and a combination thereof.

The migration is possible prior to the execution of the instruction x=ASM(“CPUID;”) in the program ofFIG. 8. Subsequent to the execution of the instruction x=ASM(“CPUID;”) and prior to the execution of the if sentence, the migration is possible by executing the instruction x=ASM(“CPUID;”) after the migration. However, the migration becomes difficult subsequent to the execution of an instruction in the instruction string of the if sentence (the instruction string as the extended portion of the instruction set A as illustrated inFIG. 8).

In accordance with the third embodiment, the combination of the static method and the dynamic method is adopted as described below. More specifically, for the CPUID instruction, the information processing apparatus determines whether the CPUID instruction has been executed, and for the instruction X, the information processing apparatus reverse-engineers the instruction X.

The program executed by the information processing apparatus ofFIG. 6has been discussed with reference toFIGS. 7 and 8.

FIG. 9illustrates in detail the virtual machine13ofFIG. 6.

The virtual machine13includes a migration manager41, an operating system42, and application programs43-1through43-n.

The migration manager41is a module for controlling the migration process. The migration manager41remains operative. The migration manager41performs a series of control steps for migration. The migration manager41is described in detail later with reference toFIG. 10.

The migration system42runs on the virtual machine13. It is noted that the operating system42is composed of the common instructions.

The application programs43-1through43-n(n is 1 or larger integer) are programs running on the virtual machine13. If it is not necessary to discriminate each of the application programs43-1through43-n, the application programs43-1through43-nare collectively referred to as an application program43. The application program43is executed by the operating system42.

FIG. 10illustrates in detail the structure of the migration manager41, and a database44communicating with the migration manager41.

The migration manager41includes a check target program list51(of programs to be checked), an absent-instruction list52(of instructions absent on a migration destination), a completed program list53(of completed programs), etc. Theses lists are described in detail later.

The migration manager41examines instructions present in all the programs on the virtual machine13. More specifically, the migration manager41reverse-engineers each program prior to the execution of the program, and then produces a list of instructions present in the program.

The lists thus produced are stored on the database as instruction lists61-1through61-n(n is an integer equal to or larger than 1) to be used by the program. The database44may be present on a file system or on a network. It is important that the database44be present at a location which the migration manager41can reference.

The instruction lists61-1through61-nto be used by the programs are produced for the respective programs present on the virtual machine13. More specifically, the number of instruction lists61-1through61-nto be used by the programs is equal to the number of programs present on the virtual machine13. If it is not necessary to discriminate the instruction lists61-1through61-nto be used by the programs (n is an integer equal to or larger than 1), these instruction lists are collectively referred to as an instruction list61to be used by the program.

The instruction list61to be used by the program is produced at any timing regardless of the execution of the migration. The migration manager41can produce the instruction list61to be used by the program, at any appropriate timing prior to the instruction of the execution of the migration. Subsequent to the instruction of the execution of the migration, the migration manager41can produce the instruction list61immediately prior to the execution of the migration.

The migration manager41can reference the database44at any time. By referencing the instruction list61to be used by the program, the migration manager41can quickly learn an instruction used in the program as an execution target.

In the case ofFIG. 10, the instruction list61to be used by the program is stored on the database44. The storage location of the instruction list61to be used by the program is not limited to the location illustrated inFIG. 10. For example, the instruction list61to be used by the program may be encoded and embedded in the header of the program.

Described below are the check target program list51on the migration manager41, the absent-instruction list52of instructions absent on a migration destination, and the completed program list53of completed programs.

The check target program list51includes a listing of information identifying a program having issued a CPUID instruction.

The migration manager41monitors all the programs present on the virtual machine13. More specifically, the migration manager41monitors whether each of the programs has issued the CPUID instruction. If one running program has issued the CPUID instruction, the migration manager41grasps the CPUID instruction, and adds, to the check target program list51, information identifying that program. The check target program list51is updated in this way.

If the execution of the program added to the check target program list51has been completed, the migration manager41deletes that program from the check target program list51.

The instruction list52of instructions absent on the migration destination includes an instruction that the migration manager41finds on the migration source CPU11A but that the migration manager41fails to find on the migration destination CPU11B.

The completed program list53includes a program that the migration manager41completed beforehand prior to the migration. The programs that the migration manager41completed beforehand include a program that is difficult to migrate, i.e., a program that includes an instruction absent on the migration destination. The program listed in the completed program list53is initiated through the capability of the migration destination CPU11B subsequent to the migration process.

The information processing apparatus of the third embodiment thus constructed continues to execute the program having only the common instructions regardless of the migration. The information processing apparatus stops the program having an instruction other than the common instructions prior to the migration, and resumes the program using the common instructions only through the capability of the migration destination CPU11B.

The advantages described below are provided in a system including the CPU11A as a high-end but high-power consuming CPU and the CPU11B as a low-end but low-power consuming CPU.

The information processing apparatus of the third embodiment continues to execute the program composed of the common instructions only regardless of the migration. If the program includes an instruction other than the common instructions, the information processing apparatus re-initiates the program subsequent to the migration. Any instruction other than the common instructions is not executed on the CPU11B. The information processing apparatus of the third embodiment can thus migrate efficiently the virtual machine13from the high-end, high-power consuming CPU to the low-end, low-power consuming CPU.

FIG. 11is a flowchart illustrating a migration process in which the virtual machine13is migrated from the memory12A to the memory12B as previously discussed with reference toFIG. 6.

In step S21, the migration manager41examines the migration destination CPU11B prior to the migration. This process is hereinafter referred to as a CPU information check process of the migration destination. The CPU migration check process of the migration destination is described in detail with reference toFIG. 12.

In step S22, the migration manager41performs a migration pre-process. In the migration pre-process, the migration manager41determines whether a program as a process target is a migratable program or not, and if the process target is an unmigratable program, issues an instruction to quit the unmigratable program. The migration pre-process is described in detail later with reference toFIG. 13.

In step S23, the migration manager41migrates the virtual machine13from the memory12A to the memory12B. Such a process is referred to as a migration execution process. The migration execution process is described later in detail with reference toFIG. 14.

In step S24, the migration manager41starts up all the programs listed in the completed program list53. The migration process of the third embodiment of the present invention is thus complete.

FIG. 12is a flowchart illustrating in detail the CPU information check process of the migration destination in step S21of the migration process ofFIG. 11.

In step S31, the migration manager41inquires of the control panel17B of the virtual machine monitor14B as the migration destination about CPU information of the migration destination via the control panel17A. The CPU information includes information relating to an instruction implemented by the migration destination CPU11B.

In step S32, the migration manager41compares CPU information of the migration source with CPU information of the migration destination. The migration manager41acquires the CPU information of the migration source and the CPU information of the migration destination via the control panels17A and17B.

In step S33, the migration manager41determines whether any instruction absent on the migration destination CPU11B is present.

If no instruction absent on the migration destination CPU11B is present with no branch followed in step S33, the CPU information check process of the migration destination ends.

If any instruction absent on the migration destination CPU11B is present with yes branch followed in step S33, processing proceeds to step S34.

In step S34, the migration manager41adds an instruction absent on the migration destination CPU11B to the absent-instruction list52of instructions absent on the migration destination.

The CPU information check process of the migration destination is thus complete. More specifically, the process step in step S21ofFIG. 11is now complete. The migration pre-process in step S22starts as illustrated inFIG. 13.

FIG. 13is a flowchart illustrating in detail the migration pre-process in step S22of the migration process ofFIG. 11.

In step S41, the migration manager41sets as a process target program one of the programs present in the check target program list51. As previously discussed, the check target program list51includes a listing of information identifying a program having issued the CPUID instruction.

In step S42, the migration manager41determines whether the process target program includes an instruction upresent on the migration destination. More specifically, by referencing the absent-instruction list52of programs absent on the migration destination, the migration manager41determines whether the process target program has an instruction absent on the migration destination.

If the process target program has no instruction absent on the migration destination with no branch followed in step S42, processing proceeds to step S45. Step S45and subsequent steps are described later.

If the process target program includes an instruction absent on the migration destination with yes branch followed in step S42, processing proceeds to step S43.

In step S43, the migration manager41transmits an end signal of the process target program to the migration source CPU11A. More specifically, the migration manager41ends the process target program prior to the migration in a manner such that the process target program including the instruction absent on the migration destination is not migrated.

In step S44, the migration manager41verifies that the process target program has stopped, and adds the process target program onto the completed program list53.

In step S45, the migration manager41determines whether all the programs on the check target program list51have been set as process target programs.

If it is determined that not all the programs on the check target program list51have been set as process target programs with no branch followed in step S45, processing returns to step S41to repeat step S41and subsequent steps.

Steps S41-S44are cycled through until all the programs on the check target program list51have been set as process target programs. In other words, the check target program list51determines whether each of the programs on the check target program list51includes an instruction absent on the migration destination. A program having an instruction absent on the migration destination is added to the completed program list53.

If it is determined that all the programs on the check target program list51have been set as process target programs with yes branch followed in step S45, processing ends.

The migration pre-process thus ends. Step S22illustrated inFIG. 11is thus complete followed by the migration execution process in step S23illustrated inFIG. 14.

FIG. 14is a flowchart illustrating in detail the migration execution process in step S23of the migration process ofFIG. 11.

In step S51, the migration manager41requests the control panel17B of the virtual machine monitor14B of the migration destination to execute the migration.

If the control panel17B is requested to execute the migration, the virtual machine monitor14B migrates the virtual machine13from the memory12A to the memory12B. Subsequent to the completion of the migration, the virtual machine monitor14B notifies the migration manager41of a migration completion notice.

In step S52, the migration manager41determines whether a migration completion notice has been received from the control panel17B of the virtual machine monitor14B as the migration destination.

If the migration manager41has not received a migration completion notice from the control panel17B of the virtual machine monitor14B as the migration destination, no branch is followed in step S52. Processing returns to step S51.

The migration execution process waits on standby until the migration manager41has received a migration completion notice from the control panel173of the virtual machine monitor14B as the migration destination.

If the migration manager41has received a migration completion notice from the control panel17B of the virtual machine monitor14B as the migration destination, yes branch is followed in step S52. Processing thus ends.

The migration execution process is complete in step S23ofFIG. 11, followed by step S24.

The information processing apparatus of the present embodiment provides the advantages described below.

The information processing apparatus of the present embodiment migrates the virtual machine13between the CPUs11A and11B commonly sharing the major instructions thereof but with a part of the instructions different from each other without interrupting the program of the virtual machine13.

For example, the CPU11A is a high-end and high-power consuming CPU, and the CPU11B is a low-end and low-power consuming CPU.

The information processing apparatus of each of the first and second embodiments executes through the capability of the CPU11A an instruction program to be performed at a high throughput, and executes through the capability of the CPU11B an instruction program not calling for a high throughput. With this arrangement, the information processing apparatus of each of the first and second embodiments of the present invention makes a system that provides both the high-performance and low-power consumption features.

The information processing apparatus of the third embodiment executes on the CPU11A a program including an instruction that can be executed by only the CPU11A, and executes a program including only the common instructions through the capability of the CPU11B. With this arrangement, the information processing apparatus of the third embodiment of the present invention makes a system that provides both the high-performance and low-power consumption features.

The information processing apparatus of each of the first through third embodiments allows low-cost hardware to be added to an existing system and migrates the virtual machine13to the resulting hardware.

If high-end hardware is added on an existing system in accordance with the information processing apparatus of each of the first through third embodiments, the migration process is performed on the existing hardware while a high-end function is being used. The existing system is thus effectively used.

The migration is performed within one apparatus in the above-described embodiments. Alternatively, the migration process may be performed between two apparatuses. In the specification, the word system refers to the whole system including a plurality of apparatuses and a controller.

The above-described process steps may be implemented using hardware or software. If the process steps are implemented using software, a program forming the software is installed on a computer. The computers include a computer included in a dedicated hardware system, and a general-purpose personal computer that performs a variety of functions with a variety of programs installed thereon.

FIG. 15is a block diagram illustrating a hardware structure of a computer that performs the above-described process steps.

In the computer, CPUs101and102, read-only memory (ROM)103, random-access memory (RAM)104are interconnected to each other via a bus105.

The bus105is connected to an input-output interface106. Also connected to the input-output interface106are an input unit107, output unit108, storage unit109, communication unit110, and drive111.

The input unit107includes a keyboard, a mouse, a microphone, etc. The output unit108includes a display, a loudspeaker, etc. The storage unit109includes a hard disk, a non-volatile memory, etc. The communication unit110includes a network interface, etc. The drive111drives a removable medium112, such as a magnetic disc, an optical disc, or a semiconductor memory, which may be considered a non-transitory recording medium.

The CPUs101and102in the computer thus constructed perform the above-described series of process steps by loading a program from the storage unit109onto the RAM104via the input-output interface106and the bus105, and then executing the program.

The program to be executed by the CPUs101and102is supplied on the removable medium112as a package medium. The program may also be supplied using wired or wireless transmission media, such as a local-area network (LAN), the Internet, or a digital broadcasting satellite.

The program may be installed onto the storage unit109in the computer through the input-output interface106by loading the removable medium112onto the drive111. The program may be received by the communication unit110via wired or wireless transmission media, and then installed onto the storage unit109. The program may also be pre-installed onto the ROM103or the storage unit109.

The program may be executed by the computer with the process steps in the time-series order previously described or with several process steps in parallel or at an appropriate timing at which a call is made.