Capacitor fabricating method of semiconductor device

A method for fabricating a capacitor of a semiconductor device is provided. In the capacitor fabricating method, the step of forming a lower electrode by using gas including chlorine is included after the step of forming hemispherical grained silicon (HSG&#8212;Si) seeds. Also, after the step of selectively growing only HSG&#8212;Si seeds formed on the lower electrode, the step of removing the HSG&#8212;Si seeds formed on an insulation layer pattern through an etching process using a gas including chlorine is included. Thus, the surface area of the lower electrode is increased, so that capacitance is increased. Also, an electrical short between the lower electrodes of each adjacent capacitor can be prevented without decreasing capacitance.

BACKGROUND OF THE INVENTION

The present invention relates to a capacitor fabricating method of a semiconductor device, and more particularly, to a capacitor fabricating method of a semiconductor device in which a ridge and valley-type lower electrode is formed using a hemispherical grained silicon (HSG Si).

A decrease in cell capacitance according to the decrease of cell memory area is an obstacle to the increase in stability of a dynamic random access memory (DRAM). The decrease in cell capacitance lowers the reading and writting abilities of the memory cell, increases the soft error ratio, and further disturbs the operation of the device at lower voltages. Thus, for high integration of the semiconductor memory device, the decrease in cell capacitance should be overcome.

Generally, in 64Mb DRAMs having a memory cell area of approximately 1.5 m 2 , it is difficult to provide sufficient capacitance even when a dielectric substance such as Ta 2 O 5 is used in a general stacked-type capacitor having a two-dimensional structure. Thus, recently, a capacitor having a three-dimensional structure has been suggested to increase cell capacitance, such as a lower electrode having a fin structure (Fujitsu), a lower electrode having a box structure (Toshiba), a lower electrode having a cylindrical structure (Mitsubishi), etc.

However, in the case of the capacitor having a three-dimensional structure, the fabrication process thereof is complicated and a defect may occur in the fabrication process, thus applying such structure is difficult. Also, research into a high dielectric film has been conducted in order to increase the capacitance of the capacitor, however, the high dielectric film has many problems in application. Thus, research into a method for fabricating a ridge and valley-type lower electrode, in which area is locally increased, has been performed to increase capacitance.

In one method of fabricating the ridge and valley-type lower electrode, multiple bumps of HSG Si are formed on the surface of the lower electrode to form ridges and valleys in the surface thereof, thereby increasing the surface area of the lower electrode.

As a method for forming HSG Si on the surface of the lower electrode, there are following methods: 1) a chemical vapor deposition method in which silicon is deposited at a temperature where phase transformation occurs from amorphous silicon to polysilicon, 2) a method for annealing amorphous silicon without native oxide layer in a vacuum, and 3) a seeding method in which HSG Si seeds are formed by a low pressure chemical deposition (LPCVD) method using SiH 4 or Si 2 H 6 gas, or by irradiating SiH 4 or Si 2 H 6 beam on the amorphous silicon, and then the formed seeds are grown.

It has been reported that the surface area of the lower electrode is effectively increased when the ridge and valley-type silicon lower electrode is formed using the seeding method in an article by H. Watanabe et al., A New Cylindrical Capacitor Using HSG Si for 256 Mb DRAMs, IEDM '92, pp. 259-262.

FIGS. 1 through 3 are cross-sectional diagrams for illustrating a conventional method for fabricating a capacitor of a semiconductor device.

FIG. 1 is a cross-sectional diagram for illustrating the step of forming an insulation layer pattern 20 and a lower electrode 40 . First, an insulation layer such as a silicon oxide layer is formed on a semiconductor substrate 10 and then the insulation layer is patterned by a photolithography process to form the insulation pattern 20 having a contact hole which exposes a predetermined area of the semiconductor substrate 10 .

Subsequently, after an amorphous silicon layer doped with impurity is formed on the entire surface of the substrate having the insulation later pattern 20 to fill the contact hole, the resultant structure is patterned by a general method. As a result, the lower electrode 40 having a cylindrical structure is formed on a predetermined area of the insulation layer pattern 20 , which is connected to the exposed semiconductor substrate via the contact hole.

FIG. 2 is a cross-sectional diagram for illustrating the step of forming HSG Si seeds 50 a and 50 b, wherein the HSG Si seeds are formed on the lower electrode 40 by a low-pressure chemical deposition (LPCVD) method using a silicon source gas. Here, since the HSG Si seeds are formed first at a portion of the lower electrode 40 with high surface energy, the HSG Si seeds are scattered on the surface of the lower electrode 40 . Also, as the silicon source gas, SiH 4 , Si 2 H 6 , Si 3 H 8 , SiH 2 Cl 2 or SiH 2 Cl 2 is used.

Of course, the HSG Si seeds may be formed on the lower electrode 40 by irradiating the silicon source gas as a beam on the entire surface of the substrate having the lower electrode 40 .

Since the selectiveness of the HSG Si seed formation process is very low, the HSG Si seeds are formed on the insulation layer pattern 20 during the step of forming HSG Si seeds on the lower electrode 40 . Hereinafter, HSG Si seeds formed on the lower electrode 40 will be referred to as first HSG Si seeds 50 a, and HSG Si seeds formed on the insulation layer pattern 20 will be referred to as second HSG Si seeds 50 b, respectively.

FIG. 3 is a cross-sectional diagram for illustrating the step of forming HSG Si 50 c. Here, the substrate having the first and second silicon seeds 50 a and 50 b is heated to selectively grow the first HSG Si seeds 50 a, thereby forming the HSG Si 50 c on the lower electrode 40 . As a result, the surface area of the lower electrode 40 is increased. Here, since the first HSG Si seeds 50 a grow by receiving silicon from the lower electrode 40 differently from the second HSG Si seeds 50 b which cannot receive silicon required for growth, only the first HSG Si seeds 50 a are grown.

Here, the second HSG Si seeds 50 b remain on the insulation layer pattern 20 , so that the lower electrode 40 and a lower electrode of a capacitor adjacent thereto are electrically shorted, causing mis-operation of the semiconductor device. Also, since an increase in area at the lower electrode 40 depends only on the growth of the first HSG Si seeds 50 a, it is difficult to obtain sufficient cell capacitance for ensuring reliable operation of the semiconductor device.

Further, a dielectric layer and an upper electrode are formed in sequence on the entire surface of the substrate having the HSG Si 50 c to complete a capacitor, wherein this step is not shown.

As described above, in the conventional method for fabricating a capacitor of a semiconductor device, the second HSG Si seeds 50 b remain on the insulation pattern 20 , so that the lower electrodes of each adjacent capacitors are susceptible to electrical shorts. Also, since the increase in area of the lower electrode 40 depends only on the growth of the first HSG Si seeds 50 a, there are difficulties in the ensuring sufficient cell capacitance. Thus, reliability of the semiconductor device is decreased.

SUMMARY OF THE INVENTION

To overcome the above problems, it is an object of the present invention to provide a method for fabricating a capacitor of a semiconductor device, which can improve reliability of the semiconductor device.

According to the first embodiment for achieving the object, there is provided a method for forming a capacitor of a semiconductor device comprising the steps of: (a) forming an insulation layer pattern on a semiconductor substrate, having a contact hole which exposes a predetermined area of the semiconductor substrate; (b) forming a lower electrode on a predetermined area of the insulation layer pattern, the lower electrode is connected to the exposed semiconductor substrate via the contact hole; (c) forming HSG Si seeds on the surfaces of the lower electrode and the insulation layer pattern; (d) etching the surface of the lower electrode by using the HSG Si seeds formed on the surface of the lower electrode as an etching mask to form a depressed portion on the surface of the lower electrode, resulting in the formation of a modified lower electrode; and (e) growing the HSG Si seeds formed on the surface of the lower electrode to form multiple bumps of HSG Si.

Here, the step (d) of etching the surface of the lower electrode is performed using a gas including chlorine, and the gas including chlorine is one selected from the group consisting of Cl 2 , BCl 3 , ClF 3 and HCl.

Also, preferably, the step (d) of etching the surface of the lower electrode is performed by anisotropically etching while varying the incident angle of etching gas.

Preferably, the step (e) of growing the HSG Si seeds is performed by heating the substrate having the HSG Si seeds, and the heating is performed at 560 630 C.

Also, it is preferably that the method for forming a capacitor of a semiconductor device further comprises the step of removing the HSG Si seeds formed on the surface of the insulation layer pattern by an etching after the step (e). Here, the step of removing HSG Si seeds formed on the surface of the insulation layer pattern by an etching is performed by using the gas including chlorine, and the gas including chlorine is one selected from the group consisting of Cl 2 , BCl 3 , ClF 3 and HCl.

According to the second embodiment for achieving the object, there is provided a method for forming a capacitor of a semiconductor device comprising the steps of: (a) forming an insulation layer pattern on a semiconductor substrate, having a contact hole which exposes a predetermined area of the semiconductor substrate; (b) forming a lower electrode on a predetermined area of the insulation layer pattern, the lower electrode is connected to the exposed semiconductor substrate via the contact hole; (c) forming HSG Si seeds on the surfaces of the lower electrode and the insulation layer pattern; (d) selectively growing the HSG Si seeds formed on the surface of the lower electrode to form multiple bumps of HSG Si on the surface of the lower electrode; (e) removing the HSG Si seeds formed on the surface of the insulation layer pattern through an etching process.

Also, the step (c) of forming the HSG Si seeds is performed by a chemical vapor deposition (CVD) method using a silicon source gas.

It is preferably that the step (d) of forming the HSG Si is performed by heating the substrate having the HSG Si seeds, and the heating is performed at 560 630 C.

In addition, the step of removing the HSG Si seeds formed on the surface of the insulation layer pattern by an etching is performed by using a gas including chlorine, and the gas including chlorine is one selected from the group consisting of Cl 2 , BCl 3 , ClF 3 and HCl.

In the method for fabricating a capacitor of a semiconductor device according to the present invention, the surface area of the lower electrode is increased, so that a high cell capacitance can be ensured compared to that of the conventional device. Also, an electrical short between the lower electrodes of adjacent capacitors can be prevented without decreasing capacitance.

DETAILED DESCRIPTION OF THE INVENTION

The method for fabricating a capacitor of a semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS. 4 through 7 .

FIG. 4 is a cross-sectional diagram for illustrating the step of forming an insulation layer pattern 120 and a lower electrode 140 , and FIG. 5 is a cross-sectional diagram for illustrating the step of forming first and second hemispherical grained silicon (HSG Si) seeds 150 a and 150 b. Here, the insulation pattern 120 , the lower electrode 140 , the first HSG Si seeds 150 a and the second HSG Si seeds 150 b are formed in the same manner as the conventional method described with reference to FIGS. 1 and 2 .

FIG. 6 is a cross-sectional diagram for illustrating the step of forming a modified lower electrode 140 a. Here, the surface of the lower electrode 140 is etched by using the first HSG Si seeds 150 a as an etching mask to form a depressed portion on the surface of the lower electrode 140 , resulting in the formation of a modified lower electrode 140 a. Also, preferably, gas including chlorine such as Cl 2 , BCl 3 , ClF 3 and HCl is used during the etching process.

The HSG Si seeds 150 a and 150 b and the insulation layer pattern 120 are more resistant to etching than the lower electrode 140 with respect to the gas including chlorine, so that the HSG Si seeds 150 a and 150 b, and the insulation layer pattern 120 are etched less than the lower electrode 140 . Here, preferable, anisotropic etching is performed while varying the incident angle, for effectively forming the depressed portion to create a larger surface area.

FIG. 7 is a cross-sectional diagram for illustrating the step of forming HSG Si 150 c, wherein the substrate having the modified lower electrode 140 a is heated at 560 630 C. to selectively grow the first HSG Si seeds 150 a , thereby forming the HSG Si 150 c on the modified lower electrode 140 a. Here, since the first HSG Si seeds 150 a grows by receiving silicon from the modified lower electrode 140 a while the second HSG Si seeds 150 b does not receive silicon required for growth, the first HSG Si seeds 150 a are grown selectively.

According to this preferred embodiment, after forming the HSG Si seeds 150 a and 150 b , the step of etching the lower electrode 140 using gas including chlorine is further performed differently from the conventional method, resulting in a ridge and valley-type lower electrode in which the ridges and valleys is more severe than that of the conventional one. Thus, the surface area of the lower electrode is increased, so that a capacitance can be provided which is greater than that of the conventional method.

FIGS. 8 through 10 are cross-sectional diagrams for illustrating a method for fabricating a capacitor of a semiconductor device according to a second embodiment of the present invention.

FIG. 8 is a cross-sectional diagram for illustrating the step of forming an insulation layer pattern 121 and a lower electrode 141 , and FIG. 9 is a cross-sectional diagram for illustrating the step of forming first and second HSG Si seeds 151 a and 151 b. Here, the insulation layer 121 , the lower electrode 141 , and the first and second HSG Si seeds 151 a and 151 b are formed in the same manner as the conventional method described with reference to FIGS. 1 and 2 .

FIG. 10 is a cross-sectional diagram for illustrating the step of forming HSG Si 151 c. Here, the substrate having first and second HSG Si seeds 151 a and 151 b is heated at 560 630 C. to selectively grow only the first HSG Si seeds 151 a, resulting in the formation of HSG Si 151 c on the lower electrode 141 . Since the first HSG Si seeds 151 a grows by receiving silicon from the lower electrode 141 while the second HSG Si seeds 151 b do not receive silicon required for growth, only the first HSG Si seeds 151 a grow.

FIG. 11 is a cross-sectional diagram for illustrating the step of removing the second HSG Si seeds 151 b, wherein the entire surface of the substrate having the HSG Si 151 c is etched using gas including chlorine such as Cl 2 , BCl 3 , ClF 3 and HCl, thereby removing the second HSG Si seeds 151 b.

Here, the HSG Si 151 c are slightly etched, resulting in the formation of a modified HSG Si 151 d whose size is reduced. Also, when removing the second HSG Si seeds 151 b, the lower electrode 141 is etched for the same reason described with reference FIG. 6 , so that a modified lower electrode 141 a having a depressed portion on the surface thereof is formed. Thus, the surface area of the lower electrode 141 is not changed significantly.

According to this preferred embodiment, after selectively growing only the first HSG Si seeds 151 a, the second HSG Si seeds 151 b are removed through an etching process using a gas including chlorine. As a result, an electrical short between the lower electrodes of each adjacent capacitor can be prevented without a decrease in capacitance.

Also, preferably, the first embodiment of the present invention further includes the step of removing the second HSG Si seeds 150 b of FIG. 7 through the etching process described in FIG. 10 , after the step of forming HSG Si 150 c of FIG 7 .

As described above, in the method of fabricating a capacitor of a semiconductor device according to the present invention, the surface area of the lower electrode is increased, so that a capacitance higher than that of the conventional method can be ensured. Also, the electrical short between the lower electrodes of each adjacent capacitor can be prevented without a decrease in capacitance.

The present invention is not limited to the particular forms illustrated, and further modifications and alterations will be apparent to those skilled in the art within the spirit and scope of this invention.