IMPEDANCE DETECTION CIRCUIT, IMPEDANCE CONTROL CIRCUIT, AND DOHERTY AMPLIFIER CIRCUIT

An impedance detection circuit includes: a first detector that detects a first voltage amplitude at an end of an inverter circuit having the end to which a radio frequency signal is input and having a different end from which a signal is output; a second detector that detects a second voltage amplitude of the different end of the inverter circuit; and a phase difference detector that detects a phase difference between a phase of a voltage across the end of the inverter circuit and a phase of a voltage across the different end of the inverter circuit. An absolute value of a product of diagonal elements of a dependent parameter for the inverter circuit is smaller than an absolute value of a product of off-diagonal elements.

BACKGROUND ART

Technical Field

The present disclosure relates to an impedance detection circuit, an impedance control circuit, and a Doherty amplifier circuit.

Patent Document 1 describes an amplification device that adjusts the phase or the amplitude of a second signal input to a second amplification part, by using the reflection coefficient of each of an output from the first amplification part and an output from the second amplification part.Patent Document 1: Japanese Unexamined Patent Application Publication No. 2017-169146

BRIEF SUMMARY

However, the amplification device described in Patent Document 1 detects the reflection coefficient of each of the output from the first amplification part and the output from the second amplification part and thus requires two directional couplers. Directional couplers are large due to the structure thereof and are not usable for, for example, mobile communication terminals.

The present disclosure prevents a circuit from being upsized and also to detect impedance.

An impedance detection circuit according to an aspect of the present disclosure includes: a first detector that detects a first voltage amplitude at an end of an inverter circuit having the end to which a radio frequency signal is input and having a different end from which a signal is output; a second detector that detects a second voltage amplitude of the different end of the inverter circuit; and a phase difference detector that detects a phase difference between a phase of a voltage across the end of the inverter circuit and a phase of a voltage across the different end of the inverter circuit. An absolute value of a product of diagonal elements of a dependent parameter for the inverter circuit is smaller than an absolute value of a product of off-diagonal elements.

An impedance control circuit according to an aspect of the present disclosure includes: the impedance detection circuit of the present disclosure; and at least one of a first transistor and a second transistor, the first transistor having a base or a gate to which a first signal based on the first voltage amplitude and the second voltage amplitude is input and having a collector from which first current is output to the end of the inverter circuit, a second transistor having a base or a gate to which a second signal based on the first voltage amplitude and the second voltage amplitude is input and having a collector from which second current is output to the different end of the inverter circuit.

A Doherty amplifier circuit according to an aspect of the present disclosure includes: a carrier amplifier that amplifies an input radio frequency signal; a peaking amplifier that amplifies an input radio frequency signal; and the impedance control circuit of the present disclosure. The inverter circuit serves as a Doherty combiner that combines a signal output by the carrier amplifier and a signal output by the peaking amplifier.

According to the present disclosure, the circuit may be prevented from being upsized and may also detect impedance.

DETAILED DESCRIPTION

Hereinafter, embodiments of an impedance detection circuit, an impedance control circuit, and a Doherty amplifier circuit of the present disclosure will be described in detail based on the drawings. The embodiments do not limit the present disclosure. It goes without necessarily saying that each embodiment is exemplification and configurations illustrated in different embodiments can be partially replaced or combined. After a second embodiment, the description of a matter common to that in a first embodiment is omitted, and one or more different points will only be described. In particular, the same advantageous effects and operations of the same configuration are not referred to in each embodiment.

First Embodiment

FIG.1is a diagram illustrating the configuration of an amplifier circuit of a first embodiment.

An amplifier circuit1includes an amplifier2, an inverter circuit3, a 90-degree shift circuit4, and an impedance control circuit10.

The amplifier2amplifies a radio frequency signal RFINand outputs a radio frequency signal RF1to an end3aof the inverter circuit3. The inverter circuit3receives the radio frequency signal RF1at the end3aand outputs a radio frequency signal RF2from a different end3bto a load150.

The amplifier2assumes that impedance ZL′ seen from the output terminal thereof to the load150has a value assumed in designing. A general emitter-grounded or source-grounded single-ended amplifier, a differential amplifier, a Doherty amplifier, an envelope tracking amplifier, and the like are exemplified as the amplifier2; however, the present disclosure is not limited to these.

An output voltage of the amplifier2is a voltage VL′, and output current is current IL′.

The inverter circuit3converts the value of the impedance ZLfor the load150to a reciprocal thereof (admittance). The inverter circuit3is a ¼ wavelength line of characteristic impedance Z0; however, the present disclosure is not limited to this.

A voltage input to the end3aof the inverter circuit3is a voltage VI1, and input current thereof is current II1. A voltage output from the different end3bof the inverter circuit3is a voltage VI2, and output current is current II2.

A voltage input to the load150is a voltage VL, and current input to the load150is current IL.

The impedance control circuit10controls the impedance ZL′. The impedance ZL′ is also the input impedance of the inverter circuit3.

(Configuration of Impedance Control Circuit)

The impedance control circuit10includes transistors Q1and Q2, variable phase control circuits11and15, variable gain control circuits12and16, capacitors13and17, resistors14and18, a control circuit19, and an impedance detection circuit20.

Each transistor is a bipolar transistor in the present disclosure; however, the present disclosure is not limited to this. A heterojunction bipolar transistor (HBT) is exemplified as the bipolar transistor; however, the present disclosure is not limited to this. The transistor may be, for example, a field effect transistor (FET). The transistor may be a multi-finger transistor in which a plurality of unit transistors are electrically connected in parallel. A unit transistor denotes a minimum configuration of a transistor.

If the transistor is a FET, the drain of the FET corresponds to the collector of the bipolar transistor, the gate thereof corresponds to the base, and the source thereof corresponds to the emitter.

The transistor Q1corresponds to an example of “first transistor” of the present disclosure. The transistor Q2corresponds to an example of “second transistor” of the present disclosure. The variable gain control circuit12corresponds to an example of “first variable gain control circuit” of the present disclosure. The variable gain control circuit16corresponds to an example of “second variable gain control circuit” of the present disclosure. The variable phase control circuit11corresponds to an example of “first variable phase control circuit” of the present disclosure. The variable phase control circuit15corresponds to an example of “second variable phase control circuit” of the present disclosure.

The impedance detection circuit20includes detectors21and22and a phase difference detector23.

The detector21corresponds to an example of “first detector” of the present disclosure. The detector22corresponds to an example of “second detector” of the present disclosure.

The detector21detects the voltage VI1across the end3aof the inverter circuit3and outputs a voltage amplitude |VI1| to the control circuit19.

The voltage amplitude |VI1| corresponds to an example of “first voltage amplitude” of the present disclosure.

The detector22detects the voltage VI2across the different end3bof the inverter circuit3and outputs a voltage amplitude |VI2| to the control circuit19.

The voltage amplitude |VI2| corresponds to an example of “second voltage amplitude” of the present disclosure.

The phase difference detector23detects a phase difference (arg(VI1)−arg(VI2)) between the voltage VI1and the voltage VI2and outputs the phase difference (arg(VI1)−arg(VI2)) to the control circuit19.

Based on the voltage amplitudes |VI1| and |VI2| and the phase difference (arg(VI1)−arg(VI2)), the control circuit19outputs a phase control signal S1to the variable phase control circuit11, outputs a gain control signal S2to the variable gain control circuit12, and outputs a bias control signal S3to an end of the resistor14. Alternatively, based on the voltage amplitudes |VI1| and |VI2| and the phase difference (arg(VI1)−arg(VI2)), the control circuit19outputs a phase control signal S4to the variable phase control circuit15, outputs a gain control signal S5to the variable gain control circuit16, and outputs a bias control signal S6to an end of the resistor18.

The variable phase control circuit11changes the phase of the radio frequency signal RFINby a phase θ1based on the phase control signal S1and outputs a radio frequency signal RF11to the variable gain control circuit12.

The variable gain control circuit12changes the amplitude of the radio frequency signal RF11by using a gain G1based on the gain control signal S2and outputs a radio frequency signal RF12via the capacitor13that is a DC blocking capacitor to the base of the transistor Q1.

A different end of the resistor14is electrically connected to the base of the transistor Q1. A bias voltage B1is input from the different end of the resistor14to the base of the transistor Q1.

The emitter of the transistor Q1is electrically connected to the reference potential. A voltage for substrate and source is exemplified as the reference potential; however, the present disclosure is not limited to this. The collector of the transistor Q1is electrically connected to a power supply voltage VCC with a choke coil31interposed therebetween, and power is supplied.

The transistor Q1outputs current Iadd1according to the radio frequency signal RF12and the bias voltage B1from the collector to the end3aof the inverter circuit3. In other words, the transistor Q1outputs a radio frequency signal from the collector to the end3aof the inverter circuit3, the radio frequency signal being obtained by amplifying the radio frequency signal RF12.

The current Iadd1corresponds to an example of “first current” of the present disclosure.

If a reactance component (imaginary component) of the impedance ZL′ is not required to be compensated, the variable phase control circuit11does not have to be provided. That is, the variable gain control circuit12may change the amplitude of the radio frequency signal RFINby using the gain G1based on the gain control signal S2and may output the radio frequency signal RF12to the base of the transistor Q1via the capacitor13that is the DC blocking capacitor.

Both or only one of the variable gain control circuit12and the resistor14may be provided. That is, both or only one of the radio frequency signal RF12and the bias voltage B1may be input to the base of the transistor Q1.

One or both of the radio frequency signal RF12and the bias voltage B1correspond to an example of “first signal” of the present disclosure. Specifically, the radio frequency signal RF12is a signal the phase or the gain of which is controlled in accordance with the phase control signal S1based on the voltage amplitudes |VI1| and |VI2| and the gain control signal S2and is “first signal” based on the voltage amplitudes |VI1| and |VI2|. The bias voltage B1is a signal controlled in accordance with the bias control signal S3based on the voltage amplitudes |VI1| and |VI2| as described above and is “first signal” based on the voltage amplitudes |VI1| and |VI2|.

The 90-degree shift circuit4shifts the phase of the radio frequency signal RFINby 90 degrees and outputs a radio frequency signal RF3to the variable phase control circuit15.

The variable phase control circuit15changes the phase of the radio frequency signal RF3by a phase θ2based on the phase control signal S4and outputs a radio frequency signal RF13to the variable gain control circuit16.

If the control circuit19is designed to add 90-degree offset to the phase control signal S4, the 90-degree shift circuit4does not have to be provided.

The variable gain control circuit16changes the amplitude of the radio frequency signal RF13by using a gain G2based on the gain control signal S5and outputs a radio frequency signal RF14to the base of the transistor Q2via the capacitor17that is the DC blocking capacitor.

A different end of the resistor18is electrically connected to the base of the transistor Q2. A bias voltage B2is input from the different end of the resistor18to the base of the transistor Q2.

The emitter of the transistor Q2is electrically connected to the reference potential. The collector of the transistor Q2is electrically connected to the power supply voltage VCC with a choke coil32interposed therebetween, and power is supplied.

The transistor Q2outputs current Iadd2according to the radio frequency signal RF14and the bias voltage B2from the collector to the different end3bof the inverter circuit3.

The current Iadd2corresponds to an example of “second current” of the present disclosure.

If the reactance component (imaginary component) of the impedance ZL′ is not required to be compensated, the variable phase control circuit15does not have to be provided. That is, the variable gain control circuit16may change the amplitude of the radio frequency signal RF3by using the gain G2based on the gain control signal S5and output the radio frequency signal RF14to the base of the transistor Q2via the capacitor17that is the DC blocking capacitor.

Both or only one of the variable gain control circuit16and the resistor18may be provided. That is, both or only one of the radio frequency signal RF14and the bias voltage B2may be input to the base of the transistor Q2.

One or both of the radio frequency signal RF14and the bias voltage B2correspond to an example of “second signal” of the present disclosure.

(Goal for Control of Impedance Control Circuit)

If the impedance ZL′ deviates from the value assumed in designing in the amplifier2, characteristics are deteriorated on occasions. For example, substantial deviation of the impedance ZL′ from the value assumed in designing in the amplifier2causes substantial distortion in the radio frequency signals RF1and RF2and thus misoperation in communication apparatus nearby in some cases. In particular, the amplifier2that is a Doherty amplifier is typically less resistant to change in the impedance ZL′.

Hence, the impedance control circuit10performs control to cause the impedance ZL′ to have a value close to the value assumed in designing. This enables the impedance control circuit10to prevent the distortion in the radio frequency signals RF1and RF2.

The inverter circuit3has a relationship that the voltage VI2is proportional to the current II1in a carrier frequency. That is, Formula (1) below holds true.

In Formula (1), ZINVis referred to as inverter impedance and is a positive or negative real number. The inverter impedance corresponds to mirror impedance of two-terminal pair network.

The inverter circuit3also has a relationship that the current II2is proportional to the voltage VI1in the carrier frequency. That is, Formula (2) below holds true.

The control circuit19detects the voltage amplitudes |VI1| and |VI2| of the respective voltages VI1and VI2and the phase difference (arg(VI1)−arg(VI2)) between the voltage VI1and the voltage VI2by using Formula (1) and Formula (2) and may thereby calculate the impedance ZINV. Specifically, by using the detectors21and22, the control circuit19detects the voltage amplitudes |VI1| and |VI2| of the respective voltages VI1and VI2derived according to Formula (1) and Formula (2). By using the phase difference detector23, the control circuit19also detects the phase difference (arg(VI1)−arg(VI2)) between the voltage VI1and the voltage VI2derived according to Formula (1) and Formula (2). The control circuit19calculates the impedance ZINVby using the detected voltage amplitudes |VI1| and |VI2| and the phase difference (arg(VI1)−arg(VI2)).

Further, the impedance control circuit10outputs the high frequency current Iadd1or Iadd2to an end portion of the inverter circuit3and may thereby control the impedance ZL′ seen from the amplifier2.

Specifically, if the impedance ZL′ is low, the impedance control circuit10outputs the current Iadd1to the end3aof the inverter circuit3. The current Iadd1flows to the inverter circuit3. Accordingly, the current IL′ is decreased by an amount corresponding to the current Iadd1. That is, the impedance control circuit10may decrease the current IL′ output by the amplifier2. This enables the impedance control circuit10to increase the impedance ZL′ seen from the amplifier2to the load150and prevent the impedance ZL′ from varying.

If the impedance ZL′ is high, the impedance control circuit10outputs the current Iadd2to the different end3bof the inverter circuit3. The current Iadd2flows to the load150. Accordingly, the current II2is decreased by an amount corresponding to the current Iadd2. That is, the impedance control circuit10may decrease the current II2output by the inverter circuit3. The decreased current II2causes the voltage VL′ output by the amplifier2to be low due to the characteristics of the inverter circuit3. The impedance control circuit10may thereby decrease the impedance ZL′ seen from the amplifier2to the load150and prevent the impedance ZL′ from varying.

Further, if the impedance control circuit10includes the variable phase control circuits11and15, the following actions are provided. That is, if the impedance control circuit10controls the phase of the current Iadd1and Iadd2based on the phase difference (arg(VI1)−arg(VI2)), the control of the impedance ZL′ described above may also be act on the reactance component (imaginary component). This enables the impedance control circuit10to further prevent the impedance ZL′ from varying.

InFIG.1, for example, the inverter circuit3has the characteristic impedance Z0and is a line with a ¼ wavelength in a carrier frequency (resonant frequency). However, the inverter circuit3is not limited to this, and it suffices that Formula (1) and Formula (2) described above hold true in the carrier frequency.

As a known circuit for which Formula (1) and (2) hold true, a circuit composed of lumped elements, a circuit obtained by combining a transmission line and lumped elements, a circuit using a transducer are exemplified. These circuits will be described for other embodiments.

According to Formula (1) and (2), the inverter circuit3is a circuit for which Formula (3) below holds true near the carrier frequency.

For example, the amplifier2is designed on the assumption of the impedance ZL′ of 50Ω (ohm) and the characteristic impedance Z0of 50Ω; however, the present disclosure is not limited to these. If the characteristic impedance Z0is different from the assumed impedance (50Ω) of the impedance ZL′, the following processing may be performed in such a manner that the voltage amplitude |VI1| or |VI2| is multiplied by the constant.

First, control performed for lower impedance ZL′ by the impedance control circuit10will be described. If the impedance ZL′ is lower than the assumed impedance (for example, 50Ω), the voltage amplitude |VI1| lower than the voltage amplitude |VI2| is observed.

In this case, the impedance control circuit10outputs the high frequency current Iadd1to the end3aof the inverter circuit3and thereby decreases the current IL′. This enables the impedance control circuit10to increase the impedance ZL′.

For example, the control circuit19controls the gain G1of the variable gain control circuit12by using Formula (4) below. In Formula (4), α1is sensitivity (a coefficient or a constant) for controlling the gain G1and is determined in consideration of the gain of the transistor Q1.

As represented by Formula (4), with the increase of a difference between the voltage amplitude |VI2| and the voltage amplitude |VI1|, the impedance control circuit10increases the amplitude of the radio frequency signal RF12to be input to the base of the transistor Q1and thereby increases the high frequency current Iadd1to be output from the collector of the transistor Q1.

Formula (4) is the simplest expression for the impedance control circuit10to achieve the control goal, and the present disclosure is not limited to this. The impedance control circuit10may use a ratio between the voltage amplitude |VI2| and the voltage amplitude |VI1| instead of the difference between the voltage amplitude |VI2| and the voltage amplitude |VI1|. The impedance control circuit10may also use combination of these or a high-order function such as a quadric.

If the impedance ZL′ seen from the amplifier2is about to be low because the output impedance of the amplifier circuit1deviates from the assumed value, the impedance control circuit10may automatically increase the impedance ZL′ by performing the control represented by Formula (4). The amplifier2thereby exists from the low impedance state.

Further, if a reactance component (imaginary component) is generated in the inverter circuit3, the phase difference (arg(VI1)−arg(VI2)) is shifted from 90 degrees. The control circuit19controls the phase θ1based on a shift amount of the phase difference (arg(VI1)−arg(VI2)) from 90 degrees. This enables the impedance control circuit10to control the phase of the radio frequency signal RF12to be input to the base of the transistor Q1. The impedance control circuit10may thus compensate the reactance component of the impedance ZL′.

For example, the control circuit19controls the phase θ1by using Formula (5) below. In Formula (5), B1is sensitivity (a coefficient or a constant) for controlling the phase.

Control performed for higher impedance ZL′ by the impedance control circuit10will then be described. If the impedance ZL′ is higher than the assumed impedance (for example, 5002), the voltage amplitude |VI1| higher than the voltage amplitude |VI2| is observed.

In this case, the impedance control circuit10outputs the high frequency current Iadd2to the different end3bof the inverter circuit3and thereby decreases the current I12. The decreased current I12causes the voltage VI1to be low due to the characteristics of the inverter circuit3. As the result, the impedance control circuit10may decrease the voltage Vi′ and thus decrease the impedance ZL′.

For example, the control circuit19controls the gain G2of the variable gain control circuit16by using Formula (6) below. In Formula (6), α2is sensitivity (a coefficient or a constant) for controlling the gain G2and is determined in consideration of the gain of the transistor Q2.

As represented by Formula (6), with the increase of a difference between the voltage amplitude |VI1| and the voltage amplitude |VI2|, the impedance control circuit10increases the amplitude of the radio frequency signal RF14to be input to the base of the transistor Q2and thereby increases the high frequency current Iadd2to be output from the collector of the transistor Q2.

Formula (6) is the simplest expression for the impedance control circuit10to achieve the control goal, and the present disclosure is not limited to this. The impedance control circuit10may use a ratio between the voltage amplitude |VI1| and the voltage amplitude |VI2|, instead of the difference between the voltage amplitude |VI1| and the voltage amplitude |VI2|. The impedance control circuit10may also use combination of these or a high-order function such as a quadric.

If the impedance ZL′ seen from the amplifier2is about to be high because the output impedance of the amplifier circuit1deviates from the assumed value, the impedance control circuit10may automatically decrease the impedance ZL′ by performing the control represented by Formula (6). The amplifier2thereby exists from the high impedance state.

Further, if a reactance component (imaginary component) is generated in the inverter circuit3, the phase difference (arg(VI1)−arg(VI2)) is shifted from 90 degrees. The control circuit19controls the phase θ2based on a shift amount of the phase difference (arg(VI1)−arg(VI2)) from 90 degrees. This enables the impedance control circuit10to control the phase of the radio frequency signal RF14to be input to the base of the transistor Q2. The impedance control circuit10may thus compensate the reactance component of the impedance ZL′.

For example, the control circuit19controls the phase θ2by using Formula (7) below. In Formula (7), β2is sensitivity (a coefficient or a constant) for controlling the phase.

(Circuit Simulation Results of Impedance Control Circuit)

FIG.2andFIG.3are charts illustrating circuit simulation results of the amplifier circuit of the first embodiment.

In the circuit simulation inFIG.2andFIG.3, the reflection coefficient of the load150is 0.25 (return loss (R.L.)=−12.0 dB and voltage standing wave ratio (VSWR)=1.67), and the impedance control described above is performed in such a manner that the reflection phase is changed from 0 degrees to 360 degrees.

FIG.2is a Smith chart of the circuit simulation results. InFIG.2, a waveform200represents the impedance ZLof the load150, and a waveform201represents the impedance ZL′ seen from the amplifier2to the load150.

FIG.3is a graph with the horizontal axis representing load phase and the vertical axis representing return loss. InFIG.3, a waveform210represents the return loss of the load150, and a waveform211represents the return loss, of the inverter circuit3, seen from the amplifier2.

The waveform201is inward of the waveform200. The waveform211is downward of the waveform210. That is, it is understood that the return loss is decreased. It is thus understood that the impedance ZL′ approaches the value assumed in designing.

However, a point212and a point213where the load phases are respectively 90 degrees and 270 degrees represent |VI1|=|VI2|, and the gain G1of the variable gain control circuit12and the gain G2of the variable gain control circuit16are each 0. That is, it is not possible for the impedance control circuit10to control the impedance ZL′ sufficiently. However, if the load phase is 90 degrees or 270 degrees, performance is not remarkably deteriorated in the amplifier2on occasions, which is acceptable.

As described above, the impedance detection circuit20detects the voltage amplitudes |VI1| and |VI2| and the phase difference (arg(VI1)−arg(VI2)) and may thereby prevent the circuit from being upsized and also detect the impedance of the inverter circuit3.

If the impedance ZL′ becomes low, the impedance control circuit10may perform control to increase the impedance ZL′ to have the value assumed in designing by outputting the current Iadd1to the end3aof the inverter circuit3.

If the impedance ZL′ becomes high, the impedance control circuit10may perform control to decrease the impedance ZL′ to have the value assumed in designing by outputting the current Iadd2to the different end3bof the inverter circuit3.

As described above, in the amplifier circuit1, the impedance ZL′ seen from the amplifier2to the load150is controlled to have the value assumed in designing, and thus the distortion of the radio frequency signals RF1and RF2may be prevented.

Second Embodiment

Among components in the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

For the first embodiment, the case of controlling all of the gain G1of the path for compensating low impedance and the phase θ1as well as the gain G2of the path for compensating high impedance and the phase θ2has heretofore been described. However, if one or more of these are controlled, a partial effect may be provided.

First Example

If only the impedance ZL′ is required to be compensated, the 90-degree shift circuit4, the transistor Q2, the variable phase control circuit15, the variable gain control circuit16, the capacitor17, and the resistor18may be omitted.

FIG.4is a diagram illustrating the configuration of an amplifier circuit in a first example of the second embodiment.

An amplifier circuit1A does not include the 90-degree shift circuit4, as compared with the amplifier circuit1(seeFIG.1). The amplifier circuit1A includes an impedance control circuit10A instead of the impedance control circuit10, as compared with the amplifier circuit1.

The impedance control circuit10A does not include the transistor Q2, the variable phase control circuit15, the variable gain control circuit16, the capacitor17, and the resistor18, as compared with the impedance control circuit10.

If the impedance ZL′ becomes low, the impedance control circuit10A outputs the current Iadd1to the end3aof the inverter circuit3. The impedance control circuit10A may thereby increase the impedance ZL′ and perform control to have the value assumed in designing.

Second Example

If only a high impedance ZL′ is required to be compensated, the transistor Q1, the variable phase control circuit11, the variable gain control circuit12, the capacitor13, and the resistor14may be omitted.

FIG.5is a diagram illustrating the configuration of an amplifier circuit in a second example of the second embodiment.

An amplifier circuit1B includes an impedance control circuit10B instead of the impedance control circuit10, as compared with the amplifier circuit1(seeFIG.1).

The impedance control circuit10B does not include the transistor Q1, the variable phase control circuit11, the variable gain control circuit12, the capacitor13, and the resistor14, as compared with the impedance control circuit10.

If the impedance ZL′ becomes high, the impedance control circuit10B outputs the current Iadd2to the different end3bof the inverter circuit3. The impedance control circuit10B may thereby decrease the impedance ZL′ and perform control to have the value assumed in designing.

Third Example

FIG.6is a diagram illustrating the configuration of an amplifier circuit in a third example of the second embodiment.

An amplifier circuit1C includes an impedance control circuit10C instead of the impedance control circuit10, as compared with the amplifier circuit1(seeFIG.1). The impedance control circuit10C does not include the variable phase control circuit11and the variable phase control circuit15, as compared with the impedance control circuit10. The impedance control circuit10C includes an impedance detection circuit20C instead of the impedance detection circuit20, as compared with the impedance control circuit10. The impedance detection circuit20C does not include the phase difference detector23, as compared with the impedance detection circuit20.

FIG.7andFIG.8are charts illustrating the circuit simulation results of the amplifier circuit in the third example of the second embodiment.

In the circuit simulation inFIG.7andFIG.8, the reflection coefficient of the load150is 0.25 (return loss (R.L.)=−12.0 dB and voltage standing wave ratio (VSWR)=1.67), and the impedance control is performed in such a manner that the reflection phase is changed from 0 degrees to 360 degrees.

FIG.7is a Smith chart of the circuit simulation results. InFIG.7, the waveform200represents the impedance ZLof the load150, and a waveform221represents the impedance ZL′ seen from the amplifier2to the load150.

FIG.8is a graph with the horizontal axis representing load phase and the vertical axis representing return loss. InFIG.8, the waveform210represents the return loss of the load150, and the waveform211represents the return loss of the inverter circuit3seen from the amplifier2.

The waveform221is inward of the waveform200on the whole. The waveform221is downward of the waveform210on the whole. That is, it is understood that the return loss is decreased. It is thus understood that the impedance ZL′ approaches the value assumed in designing.

However, near a point223and a point224where the load phases are respectively 90 degrees and 270 degrees, impedance mismatching in the real part is not decreased, but impedance mismatching in the imaginary part is increased. As the result, the return loss of the inverter circuit3is higher than the return loss of the load150. However, impedance mismatching in a real axis direction (real part) is sufficiently low, and thus it is understood that it is sufficiently practical.

Third Embodiment

Among components in a third embodiment, the same components as those in any one of the other embodiments are denoted by the same reference numerals, and description thereof is omitted.

In the first and second embodiments, the inverter circuit3is the ¼ wavelength line. However, it suffices that in the inverter circuit3, the diagonal elements of a dependent parameter (see the right side of Formula (3)) is 0 at the operating frequency, and various variations are considered. The diagonal elements is ideally 0 in discussion, and the absolute value of the product of the diagonal elements is only required to be smaller than the absolute value of the product of off-diagonal elements at the used frequency. Circuits having the characteristics as described above will be exemplified and enumerated.

First Example

FIG.9is a diagram illustrating the configuration of an inverter circuit in a first example of the third embodiment.

An inverter circuit3A includes inductors41and42and a capacitor43.

An end of the inductor41is electrically connected to the end3aof the inverter circuit3A. A different end of the inductor41is electrically connected to an end of the inductor42and an end of the capacitor43.

A different end of the capacitor43is electrically connected to the reference potential.

A different end of the inductor42is electrically connected to the different end3bof the inverter circuit3A.

The inverter circuit3A may be considered as a T-type low pass filter.

Second Example

FIG.10is a diagram illustrating the configuration of an inverter circuit in a second example of the third embodiment.

An inverter circuit3B includes an inductor44and capacitors45and46.

An end of the inductor44is electrically connected to the end3aof the inverter circuit3B and an end of the capacitor45. A different end of the inductor44is electrically connected to the different end3bof the inverter circuit3B and an end of the capacitor46.

A different end of the capacitor45and a different end of the capacitor46are electrically connected to the reference potential.

The inverter circuit3B may be considered as a π-type low pass filter.

Third Example

FIG.11is a diagram illustrating the configuration of an inverter circuit in a third example of the third embodiment.

An inverter circuit3C includes capacitors47and48and an inductor49.

An end of the capacitor47is electrically connected to the end3aof the inverter circuit3C. A different end of the capacitor47is electrically connected to an end of the capacitor48and an end of the inductor49.

A different end of the inductor49is electrically connected to the reference potential.

A different end3bof the capacitor48is electrically connected to the different end of the inverter circuit3C.

The inverter circuit3C may be considered as a T-type high pass filter.

Fourth Example

FIG.12is a diagram illustrating the configuration of an inverter circuit in a fourth example of the third embodiment.

An inverter circuit3D includes a capacitor50and inductors51and52.

An end of the capacitor50is electrically connected to the end3aof the inverter circuit3D and an end of the inductor51. A different end of the capacitor50is electrically connected to the different end3bof the inverter circuit3D and an end of the inductor52.

A different end of the inductor51and a different end of the inductor52are electrically connected to the reference potential.

The inverter circuit3D may be considered as a π-type high pass filter.

Fifth Example

FIG.13is a diagram illustrating the configuration of an inverter circuit in a fifth example of the third embodiment.

An inverter circuit3E includes a first winding53, a second winding54, and capacitors55and56.

The first winding53and the second winding54are electromagnetically coupled.

The capacitor55is electrically connected in parallel to the first winding53.

The capacitor56is electrically connected in parallel to the second winding54.

An end of the first winding53and an end of the capacitor55are electrically connected to the end3aof the inverter circuit3E. A different end of the first winding53and a different end of the capacitor55are electrically connected to the reference potential.

An end of the second winding54and an end of the capacitor56are electrically connected to the different end3bof the inverter circuit3E. A different end of the second winding54and a different end of the capacitor56are electrically connected to the reference potential.

The inverter circuit3E may be considered as a transducer.

As described above, the inverter circuit3may be replaced with one of various circuits, and band widening and downsizing are expectable.

Fourth Embodiment

Among components in a fourth embodiment, the same components as those in any one of the other embodiments are denoted by the same reference numerals, and description thereof is omitted.

AS long as an inverter circuit is configured to be used as a balun such as the inverter circuit3E (seeFIG.13), the impedance control may be implemented even if the current IL′ (or a voltage Vadd converted from the current IL′) is injected in series, as illustrated in subsequentFIG.14.

FIG.14is a diagram illustrating the configuration of an amplifier circuit of the fourth embodiment.

An amplifier circuit1D includes the inverter circuit3E instead of the inverter circuit3, as compared with the amplifier circuit1(seeFIG.1). The amplifier circuit1D further includes a scaler circuit5, as compared with the amplifier circuit1.

The end of the first winding53and the end of the capacitor55of the inverter circuit3E are electrically connected to a first terminal3cof the inverter circuit3E. The different end of the first winding53and the different end of the capacitor55are electrically connected to a second terminal3dof the inverter circuit3E.

The end of the second winding54of the inverter circuit3E and the end of the capacitor56are electrically connected to a third terminal3eof the inverter circuit3E. The different end of the second winding54and the different end of the capacitor56are electrically connected to a fourth terminal3fof the inverter circuit3E.

The first terminal3cof the inverter circuit3E is electrically connected to the output terminal of the amplifier2, and the radio frequency signal RF1is input thereto. The second terminal3dof the inverter circuit3E is electrically connected to the load150, and the radio frequency signal RF2is output therefrom.

The third terminal3eof the inverter circuit3E is electrically connected to the reference potential. The fourth terminal3fof the inverter circuit3E is electrically connected to the collector of the transistor Q2, and the current Iadd2is input thereto.

A voltage between the third terminal3eand the fourth terminal3fof the inverter circuit3E is the voltage VI2.

The scaler circuit5includes a first winding61, a second winding62, and capacitors63and64.

An end of the first winding61is electrically connected to a first terminal5aof the scaler circuit5. A different end of the first winding61is electrically connected to an end of the capacitor63serving as a DC blocking capacitor.

A different end of the capacitor63is electrically connected to a second terminal5bof the scaler circuit5.

The end of the second winding62and the end of the capacitor64are electrically connected to a third terminal5cof the scaler circuit5. A different end of the second winding62and a different end of the capacitor64are electrically connected to a fourth terminal5dof the scaler circuit5.

The first terminal5aand the third terminal5cof the scaler circuit5are electrically connected to the reference potential.

The fourth terminal5dof the scaler circuit5is electrically connected to the collector of the transistor Q1, and the current Iadd1is input thereto. The second terminal5bof the scaler circuit5is electrically connected to the output terminal of the amplifier2and the first terminal3cof the inverter circuit3E, and current Iadd1′ is output therefrom.

A voltage between the third terminal5cand the fourth terminal5dof the scaler circuit5is the voltage VI1.

On the contrary to the inverter circuit3E, the scaler circuit5is a circuit having a larger absolute value of the product of the diagonal elements of the dependent parameter than the absolute value of the product of the off-diagonal elements.

The scaler circuit5may be included in the impedance detection circuit20.

If the current Iadd1is not high, the scaler circuit5may output the current Iadd1′ obtained by multiplying the current Iadd1by the constant (for example, once or twice) to the first terminal3cof the inverter circuit3E.

If the current Iadd1is sufficiently high, the scaler circuit5is not required. It suffices that the collector of the transistor Q1is electrically connected to the output terminal of the amplifier2and the first terminal3cof the inverter circuit3E to cause the current Iadd1to be directly output from the collector of the transistor Q1to the first terminal3cof the inverter circuit3E.

If the voltage VL′ is high, the scaler circuit5may decrease the voltage VL′ to one over constant (for example, one second) and output the voltage VL′ to the collector of the transistor Q1and the detector21. The scaler circuit5may thereby prevent the transistor Q1from being damaged and change the detectable range of the detector21.

FIG.15andFIG.16are charts illustrating the circuit simulation results of the amplifier circuit of the fourth embodiment.

In the circuit simulation inFIG.15andFIG.16, the reflection coefficient of the load150is 0.25 (return loss (R.L.)=−12.0 dB and voltage standing wave ratio (VSWR)=1.67), and the impedance control is performed in such a manner that the reflection phase is changed from 0 degrees to 360 degrees.

FIG.15is a Smith chart of the circuit simulation results. InFIG.15, the waveform200represents the impedance ZLof the load150, and a waveform231represents the impedance ZL′ seen from the amplifier2to the load150.

FIG.16is a graph with the horizontal axis representing load phase and the vertical axis representing return loss. InFIG.16, the waveform210represents the return loss of the load150, and a waveform241represents the return loss of the inverter circuit3E seen from the amplifier2.

With the configuration of the amplifier circuit1D, it is possible to freely select whether to inject the current Iadd1and to detect the voltage VI1on the load150side or the amplifier2side with respect to the inverter circuit3E.

Fifth Embodiment

Among components in a fifth embodiment, the same components as those in any one of the other embodiments are denoted by the same reference numerals, and description thereof is omitted.

For the first, second, and fourth embodiments, the case where one of the inverter circuit3to the inverter circuit3E is additionally provided closer to the load150than to the amplifier2has heretofore been described. However, if the amplifier2is a Doherty amplifier, one of the inverter circuit3to the inverter circuit3E is included in the Doherty combiner, and the Doherty combiner may also be used for the impedance control.

FIG.17is a diagram illustrating the configuration of the amplifier circuit of the fifth embodiment. An amplifier circuit1E is a Doherty amplifier circuit.

The amplifier circuit1E includes a carrier amplifier6, a peaking amplifier7, and a Doherty combiner8instead of the amplifier2, as compared with the amplifier circuit1(seeFIG.1).

The Doherty combiner8includes the inverter circuit3.

Each of the carrier amplifier6and the peaking amplifier7has two stages; however, the present disclosure is not limited to this. Each of the carrier amplifier6and the peaking amplifier7may have one stage and may have three or more stages.

The carrier amplifier6amplifies the radio frequency signal RFINand outputs a radio frequency signal RF21to the end3aof the inverter circuit3.

Impedance seen from the carrier amplifier6to the load150is impedance ZC. An output voltage of the carrier amplifier6is a voltage VC, and output current is current IC.

A connection relationship among the carrier amplifier6, the variable phase control circuit11, the variable gain control circuit12, the capacitor13, the resistor14, and the transistor Q1is the same as the connection relationship (seeFIG.1) among the amplifier2, the variable phase control circuit11, the variable gain control circuit12, the capacitor13, the resistor14, and the transistor Q1, and thus description thereof is omitted.

The inverter circuit3receives the radio frequency signal RF21at the end3aand outputs a radio frequency signal RF22from the different end3bto a node N1.

The peaking amplifier7amplifies the radio frequency signal RF3and outputs a radio frequency signal RF23to the node N1.

Impedance seen from the peaking amplifier7to the load150is impedance ZP. An output voltage of the peaking amplifier7is a voltage VP, and output current thereof is current IP.

A connection relationship among the peaking amplifier7, the variable phase control circuit15, the variable gain control circuit16, the capacitor17, the resistor18, and the transistor Q2is the same as the connection relationship (seeFIG.1) among the amplifier2, the variable phase control circuit11, the variable gain control circuit12, the capacitor13, the resistor14, and the transistor Q1, and thus description thereof is omitted.

At the node N1, the radio frequency signal RF22and the radio frequency signal RF23are combined, and a radio frequency signal RF24is generated. The combined radio frequency signal RF24is output to the load150.

The inverter circuit3is used for combining the radio frequency signal RF22and the radio frequency signal RF23and also for controlling impedance, and thereby downsizing may be achieved.

However, in achieving high efficiency, the Doherty amplifier circuit is characterized by variation of the impedance ZCseen from the carrier amplifier6to the load150due to input power (power of the radio frequency signal RFIN). Accordingly, if the technology in the first, second, and fourth embodiments is simply used for the amplifier circuit1E, control is performed to have a constant impedance ZC, and thus the efficiency is likely to be deteriorated.

Hence, the control circuit19may change the control of the gains G1and G2and the control of the bias voltages B1and B2according to input power (power of the radio frequency signal RFINor the radio frequency signal RF3) or output power (power of the radio frequency signals RF21, RF22, or RF24).

Specifically, control as in Formula (8) and Formula (9) below is conceivable as the control of the gains G1and G2

In Formula (8) and (9), Voffset is a parameter varying with the input power or the output power.

The amplifier circuit1E may thereby match the impedance ZCseen from the carrier amplifier6to the load150with different impedance according to the input power or the output power.

Sixth Embodiment

Among components in a sixth embodiment, the same components as those in any one of the other embodiments are denoted by the same reference numerals, and description thereof is omitted.

For the fifth embodiment, the case where each of the carrier amplifier6and the peaking amplifier7has a single-ended output configuration and where the Doherty combiner8combines the radio frequency signal RF21and the radio frequency signal RF23in parallel has heretofore been described. However, the present disclosure is not limited to this. Each of the carrier amplifier and the peaking amplifier may have a differential output configuration, and the Doherty combiner may combine two differential signals in series.

FIG.18is a diagram illustrating the configuration of an amplifier circuit of the sixth embodiment. An amplifier circuit1F is a Doherty amplifier circuit.

The amplifier circuit1F includes carrier amplifiers6-1and6-2instead of the carrier amplifier6, as compared with the amplifier circuit1E (seeFIG.17). The amplifier circuit1F includes peaking amplifiers7-1and7-2instead of the peaking amplifier7, as compared with the amplifier circuit1E. The amplifier circuit1F includes a Doherty combiner8F instead of the Doherty combiner8, as compared with the amplifier circuit1E. The Doherty combiner8F includes the inverter circuit3E and the scaler circuit5. The amplifier circuit1F further includes baluns71and72, as compared with the amplifier circuit1E.

The carrier amplifier6-1and the carrier amplifier6-2form a differential carrier amplifier. The carrier amplifier6-1is a positive polarity carrier amplifier. The carrier amplifier6-2is a negative polarity carrier amplifier.

The peaking amplifier7-1and the peaking amplifier7-2form a differential peaking amplifier7-2. The peaking amplifier7-1is a positive polarity peaking amplifier. The peaking amplifier7-2is a negative polarity peaking amplifier.

Each of the carrier amplifiers6-1and6-2as well as the peaking amplifiers7-1and7-2has two stages; however, the present disclosure is not limited to this. Each of the carrier amplifiers6-1and6-2as well as the peaking amplifiers7-1and7-2may have one stage and may have three or more stages.

The balun71outputs radio frequency signals RF31and RF32constituting a differential signal, based on the radio frequency signal RF3.

The carrier amplifier6-1amplifies the radio frequency signal RF31and outputs a radio frequency signal RF33to the end of the second winding62of the scaler circuit5.

Impedance seen from the carrier amplifier6-1to the load150is the impedance ZC. An output voltage of the carrier amplifier6-1is the voltage VC, and output current thereof is the current IC.

A connection relationship among the carrier amplifier6-1, a variable phase control circuit11-1, a variable gain control circuit12-1, a capacitor13-1, a resistor14-1, and the transistor Q1is the same as the connection relationship (seeFIG.1) among the amplifier2, the variable phase control circuit11, the variable gain control circuit12, the capacitor13, the resistor14, and the transistor Q1, and thus description thereof is omitted.

The carrier amplifier6-2amplifies a radio frequency signal RF32and outputs a radio frequency signal RF34to the different end of the second winding62of the scaler circuit5.

Impedance seen from the carrier amplifier6-2to the load150is impedance ZC′. An output voltage of the carrier amplifier6-2is a voltage VC′, and output current thereof is current IC′.

A connection relationship among the carrier amplifier6-2, a variable phase control circuit11-2, a variable gain control circuit12-2, a capacitor13-2, a resistor14-2, and a transistor Q1′ is the same as the connection relationship (seeFIG.1) among the amplifier2, the variable phase control circuit11, the variable gain control circuit12, the capacitor13, the resistor14, and the transistor Q1, and thus description thereof is omitted.

The balun72outputs radio frequency signals RF35and RF36constituting a differential signal, based on the radio frequency signal RFIN.

The peaking amplifier7-1amplifies the radio frequency signal RF35and outputs a radio frequency signal RF37to the end of the first winding53of the inverter circuit3E.

Impedance seen from the peaking amplifier7-1to the load150is the impedance ZP. An output voltage of the peaking amplifier7-1is the voltage VP, and output current thereof is the current IP.

A connection relationship among the peaking amplifier7-1, a variable phase control circuit15-1, a variable gain control circuit16-1, a capacitor17-1, a resistor18-1, and the transistor Q2is the same as the connection relationship (seeFIG.1) among the amplifier2, the variable phase control circuit11, the variable gain control circuit12, the capacitor13, the resistor14, and the transistor Q1, and thus description thereof is omitted.

The peaking amplifier7-2amplifies the radio frequency signal RF36and outputs a radio frequency signal RF38to the different end of the first winding53of the inverter circuit3E.

Impedance seen from the peaking amplifier7-2to the load150is impedance ZP′. An output voltage of the peaking amplifier7-2is a voltage VP′, and output current thereof is current IP′.

A connection relationship among the peaking amplifier7-2, a variable phase control circuit15-2, a variable gain control circuit16-2, a capacitor17-2, a resistor18-2, and a transistor Q2′ is the same as the connection relationship (seeFIG.1) among the amplifier2, the variable phase control circuit11, the variable gain control circuit12, the capacitor13, the resistor14, and the transistor Q1, and thus description thereof is omitted.

The end of the second winding54of the inverter circuit3E is electrically connected to the reference potential. The different end of the second winding54of the inverter circuit3E is electrically connected to the end of the first winding61of the scaler circuit5. A radio frequency signal RF39obtained by combining the differential signal (radio frequency signals RF33and RF34) and the differential signal (radio frequency signals RF37and RF38) in series is output from the capacitor63of the scaler circuit5to the load150.

In this embodiment, the phase difference detector23detects a phase difference (arg(VC)−arg(VP)) between the radio frequency signal RF33that is an output signal of the positive polarity carrier amplifier6-1and the radio frequency signal RF37that is an output signal of the positive polarity peaking amplifier7-1; however, the present disclosure is not limited to this. The phase difference detector23may detect a phase difference between the radio frequency signal RF34that is an output signal of the negative polarity carrier amplifier6-2and the radio frequency signal RF38that is an output signal of the negative polarity peaking amplifier7-2. The phase difference detector23may also detect a phase difference between the radio frequency signal RF33that is the output signal of the positive polarity carrier amplifier6-1and the radio frequency signal RF38that is the output signal of the negative polarity peaking amplifier7-2. The phase difference detector23may also detect a phase difference between the radio frequency signal RF34that is the output signal of the negative polarity carrier amplifier6-2and the radio frequency signal RF37that is the output signal of the positive polarity peaking amplifier7-1. The phase difference detector23may also average two or more of the phases described above.

Further, the phase difference detector23may calculate a phase difference between the carrier side and the peak side by using the amplitude, the phase, or the like of the differential signal (radio frequency signals RF33and RF34) on the carrier side and the differential signal (radio frequency signals RF37and RF38) on the peak side.

A phase control signal S1-2input to the variable phase control circuit11-2on the negative polarity side, a gain control signal S2-2input to the variable gain control circuit12-2, and a bias control signal S3-2input to the resistor14-2may be respectively same as a phase control signal S1-1input to the variable phase control circuit11-1on the positive polarity side, a gain control signal S2-1input to the variable gain control circuit12-1, and a bias control signal S3-1input to the resistor14-1; however, the present disclosure is not limited to this.

A gain, a phase difference, and a bias point may be controlled by using a result of comparison between the radio frequency signal RF33and the radio frequency signal RF34(for example, comparison between |VC| and |VC′| such as arg(VC)−arg(VC′)). The amplifier circuit1F may thereby reduce an influence on the differential pair caused by the load variation.

A phase control signal S4-2input to the variable phase control circuit15-2, a gain control signal S5-2input to the variable gain control circuit16-2, and a bias control signal S6-2input to the resistor18-2are the same as described above.

Seventh Embodiment

Among components in a seventh embodiment, the same components as those in any one of the other embodiments are denoted by the same reference numerals, and description thereof is omitted.

The load detection technology in the first to sixth embodiments may be combined with another control technology. For example, a case where a target amplifier is a Doherty amplifier will be described. There is typically a possibility that the characteristics of the Doherty amplifier largely vary (performance deterioration) in response to the load variation, as described above. The amplifier circuit1F of the sixth embodiment described above may improve the characteristic variation described above but may improve the characteristic variation described above also in the seventh embodiment.

FIG.19is a diagram illustrating the configuration of an amplifier circuit of the seventh embodiment. An amplifier circuit1G is a Doherty amplifier circuit.

The amplifier circuit1G includes a first bias circuit81, as compared with the amplifier circuit1E (seeFIG.17). The first bias circuit81performs variable control of a bias of the carrier amplifier6. The amplifier circuit1G includes a second bias circuit82, as compared with the amplifier circuit1E. The second bias circuit82performs variable control of a bias of the peaking amplifier7.

Based on the voltage amplitude |VI1| and the voltage amplitude |VI2|, the first bias circuit81outputs a bias signal BCDto the base (or the gate) of a first stage amplifier6aof the carrier amplifier6and outputs a bias signal BCFto the base (or the gate) of a final stage amplifier6b.

Based on the voltage amplitude |VI1| and the voltage amplitude |VI2|, the second bias circuit82outputs a bias signal BPDto the base (or the gate) of a first stage amplifier7aof the peaking amplifier7and outputs a bias signal BPFto the base (or the gate) of a final stage amplifier7b.

Typically, it is known that the characteristic variation in response to the load variation in the Doherty amplifier may be improved by controlling a bias of the base (or the gate) of one or more of amplifiers in respective stages of the carrier amplifier and amplifiers in respective stages of the peaking amplifier. The amplifier circuit1G controls, in accordance with the load condition, a bias of one or more of the first stage amplifier6aand the final stage amplifier6bof the carrier amplifier6and the first stage amplifier7aand the final stage amplifier7bof the peaking amplifier7and thereby may provide a high performance Doherty amplifier even if the load variation occurs.

Hereinafter, control of the amplifier circuit1G, for example, in a case of low impedance will be described. In a case of high impedance, similar effects are provided by performing control for reverse operations.

Low impedance of the load150leads to, for example, |VI2|>|VI1|. In this case, the impedance ZCseen from the carrier amplifier6to the load150becomes high. If the impedance ZCbecomes high, the gain of the carrier amplifier6changes to be higher, and saturation power changes to be lower. The amplifier circuit1G performs control to compensate for this and thereby may prevent the characteristic variation due to the load variation.

Specifically, the first bias circuit81decreases the impedance of the bias signals BCDand BCFto have impedance lower than in the case of the assumed impedance (for example, in the case of |VI2|=|VI1|) and prevents the gain of the carrier amplifier6from increasing. In addition, the second bias circuit82increases the bias signals BPDand BPEto have impedance higher than in the case of the assumed impedance. This causes the peaking amplifier7to start, and thus early saturation in the carrier amplifier6due to low saturation power of the carrier amplifier6may be compensated.

For the seventh embodiment, the case where the amplifier circuit1G combines the radio frequency signal RF21and the radio frequency signal RF23in parallel has heretofore been described; however, the present disclosure is not limited to this. If the amplifier circuit1G combines the radio frequency signal RF21and the radio frequency signal RF23in series, the polarity of a detected voltage and the polarity for bias control are opposite polarities from those in the case of the parallel combination described above.

For a bias point of the peaking amplifier7, control technology in, for example, U.S. Patent Application Publication No. 2021/0036661 Specification and U.S. Patent Application Publication No. 2016/0241209 Specification may be used. A voltage amplitude comparison result or a voltage phase comparison result is reflected on a bias point of the peaking amplifier7, and thereby a Doherty amplifier compensated for the load variation may be provided.

FIG.20is a diagram illustrating the configuration of an equivalent circuit of the amplifier circuit of the seventh embodiment.

An amplifier91inFIG.20corresponds to integration of the capacitor13, the resistor14, and the transistor Q1inFIG.19. An amplifier92corresponds to integration of the capacitor17, the resistor18, and the transistor Q2inFIG.19.

It is understood that the amplifier91for impedance control (transistor Q1) is connected in parallel to the final stage amplifier6bof the carrier amplifier6.

It is understood that the amplifier92for impedance control (transistor Q2) is connected in parallel to the final stage amplifier7bof the peaking amplifier7.

Eighth Embodiment

Among components in an eighth embodiment, the same components as those in any one of the other embodiments are denoted by the same reference numerals, and description thereof is omitted.

FIG.21is a diagram illustrating the configuration of the amplifier circuit of the eighth embodiment. An amplifier circuit1H is a Doherty amplifier circuit.

The amplifier circuit1H includes a variable attenuator101and a detector102instead of the second bias circuit82, as compared with the amplifier circuit1G (seeFIG.19).

The variable attenuator101attenuates the radio frequency signal RF3based on a signal S7and outputs the radio frequency signal RF3to the detector102. The signal S7is a signal representing the drive level of the final stage amplifier6bof the carrier amplifier6, and a saturation signal or a load detection signal is exemplified; however, the present disclosure is not limited to this. The signal S7is also a signal representing the level of the input power (power of the radio frequency signal RFIN). The detector102detects a radio frequency signal attenuated by the variable attenuator101and outputs the bias signals BPDand BPFrespectively to the first stage amplifier7aand the final stage amplifier7b.

Even if input power (power of the radio frequency signal RFIN) is not high, the amplifier circuit1H may perform circuit operations on which the load status is reflected and thus prevent control delay.

FIG.22is a diagram illustrating the configuration of an amplifier circuit of a modification of the eighth embodiment.

An amplifier circuit1I further includes a drive level detector111and an envelope modulation circuit112, as compared with the amplifier circuit1H (seeFIG.21).

The drive level detector111detects the drive level of the final stage amplifier6bof the carrier amplifier6and outputs a signal SDL representing the drive level to the envelope modulation circuit112. In an example, the drive level detector111detects the drive level of the final stage amplifier6bbased on a voltage or current of an amplifying transistor in the final stage amplifier6bor a voltage or current of the transistor in the first bias circuit81; however, the present disclosure is not limited to this. The signal SDL is also a signal representing the level of input power (power of the radio frequency signal RFIN).

The envelope modulation circuit112outputs the signal S7to the variable attenuator101based on the voltage amplitude |VI1|, the voltage amplitude |VI2|, the phase difference (arg(VI1)−arg(VI2)), and the signal SDL.

With the amplifier circuit1I, an adaptive Doherty amplifier capable of impedance control may be achieved.

The embodiments described above have been provided for easier understanding of the present disclosure and are not intended to limit the interpretation of the present disclosure. The present disclosure may be changed/improved without necessarily departing from the spirit thereof and includes its equivalents.

REFERENCE SIGNS LIST