Managing concurrent access to multiple storage bank domains by multiple interfaces

System, methods and apparatus are described that facilitate access to a memory device. A memory space within the memory device is divided into a plurality of storage bank domains. Thereafter, application interface circuits configured to access the memory space are classified into a plurality of interface groups based on one or more application usage requirements. Each interface group of the plurality of interface groups is assigned to a corresponding storage bank domain from the plurality of storage bank domains. Access between each interface group and the corresponding storage bank domain is then provided, wherein a first application interface circuit of a first interface group accesses a first corresponding storage bank domain while a second application interface circuit of a second interface group accesses a second corresponding storage bank domain.

BACKGROUND

Field

The present disclosure relates generally to information storage devices, and more particularly, to facilitating concurrent access to storage domains of the information storage devices by multiple application interface circuits.

Background

Cellular and wireless communication technologies have seen explosive growth over the past several years. Wireless service providers now offer a wide array of features and services, and provide their users with unprecedented levels of access to information, resources and communications. To keep pace with these service enhancements, mobile electronic devices (e.g., cellular phones, tablets, laptops, etc.) have become more feature rich and complex than ever. Mobile electronic devices now commonly include multiple processors, system-on-chips (SoCs), multiple memories, and other resources (e.g., power rails, etc.) that allow mobile device users to execute complex and power intensive software applications (e.g., video streaming, multimedia processing, etc.) on their mobile devices. As mobile devices and related technologies continue to grow in popularity and use, improving the performance capabilities and power consumption characteristics of mobile devices are expected to become important and challenging design criteria for mobile device designers.

SUMMARY

Embodiments disclosed herein provide systems, methods and apparatus for accessing a memory device.

In an aspect of the disclosure, a method for accessing a memory device includes dividing a memory space within the memory device into a plurality of storage bank domains, classifying application interface circuits configured to access the memory space into a plurality of interface groups based on one or more application usage requirements, assigning each interface group of the plurality of interface groups to a corresponding storage bank domain from the plurality of storage bank domains, and providing access between each interface group and the corresponding storage bank domain. A first application interface circuit of a first interface group accesses a first corresponding storage bank domain while a second application interface circuit of a second interface group accesses a second corresponding storage bank domain. The storage bank domains may be separately power-controlled.

The one or more application usage requirements may include at least one of an application storage size requirement, an application interface bandwidth requirement, or an application interface latency requirement. The access may be provided by a plurality of routers managing concurrent data flow between the plurality of interface groups and the storage bank domains. The plurality of routers may be located between the application interface circuits and the plurality of storage bank domains. Each router of the plurality of routers may be located adjacent to a corresponding set of storage banks that includes storage banks of different storage bank domains. According to certain aspects, the method for accessing the memory device may further include sending data having a low-latency requirement from an application interface circuit of an interface group to a storage bank of a corresponding storage bank domain via a router providing lowest-latency access to the storage bank.

In an aspect of the disclosure, an apparatus for accessing a memory device includes means for dividing a memory space within the memory device into a plurality of storage bank domains, means for classifying application interface circuits configured to access the memory space into a plurality of interface groups based on one or more application usage requirements, means for assigning each interface group of the plurality of interface groups to a corresponding storage bank domain from the plurality of storage bank domains, and means for providing access between each interface group and the corresponding storage bank domain. A first application interface circuit of a first interface group accesses a first corresponding storage bank domain while a second application interface circuit of a second interface group accesses a second corresponding storage bank domain. According to certain aspects, the apparatus for accessing the memory device may further include means for sending data having a low-latency requirement from an application interface circuit of an interface group to a storage bank of a corresponding storage bank domain via a router providing lowest-latency access to the storage bank and means for separately power-controlling the storage bank domains.

In an aspect of the disclosure, an apparatus for accessing a memory device includes at least one processor configured to divide a memory space within the memory device into a plurality of storage bank domains, classify application interface circuits configured to access the memory space into a plurality of interface groups based on one or more application usage requirements, assign each interface group of the plurality of interface groups to a corresponding storage bank domain from the plurality of storage bank domains, and provide access between each interface group and the corresponding storage bank domain. A first application interface circuit of a first interface group accesses a first corresponding storage bank domain while a second application interface circuit of a second interface group accesses a second corresponding storage bank domain.

In an aspect of the disclosure, a processor-readable storage medium having one or more instructions which, when executed by at least one processing circuit, cause the at least one processing circuit to divide a memory space within a memory device into a plurality of storage bank domains, classify application interface circuits configured to access the memory space into a plurality of interface groups based on one or more application usage requirements, assign each interface group of the plurality of interface groups to a corresponding storage bank domain from the plurality of storage bank domains, and provide access between each interface group and the corresponding storage bank domain. A first application interface circuit of a first interface group accesses a first corresponding storage bank domain while a second application interface circuit of a second interface group accesses a second corresponding storage bank domain.

DETAILED DESCRIPTION

The terms “computing device” and “mobile device” are used interchangeably herein to refer to any one or all of servers, personal computers, smartphones, cellular telephones, tablet computers, laptop computers, netbooks, ultrabooks, palm-top computers, personal data assistants (PDAs), wireless electronic mail receivers, multimedia Internet enabled cellular telephones, Global Positioning System (GPS) receivers, wireless gaming controllers, and similar personal electronic devices which include a programmable processor. While the various aspects are particularly useful in mobile devices (e.g., smartphones, laptop computers, etc.), which have limited resources (e.g., processing power, battery, etc.), the aspects are generally useful in any computing device that may benefit from improved processor performance and reduced energy consumption.

The term “multicore processor” is used herein to refer to a single integrated circuit (IC) chip or chip package that contains two or more independent processing units or cores (e.g., central processing unit (CPU) cores, etc.) configured to read and execute program instructions. The term “multiprocessor” is used herein to refer to a system or device that includes two or more processing units configured to read and execute program instructions.

The term “system on chip” (SOC) is used herein to refer to a single integrated circuit (IC) chip that contains multiple resources and/or processors integrated on a single substrate. A single SOC may contain circuitry for digital, analog, mixed-signal, and radio-frequency functions. A single SOC may also include any number of general purpose and/or specialized processors (digital signal processors, modem processors, video processors, etc.), memory blocks (e.g., ROM, RAM, Flash, etc.), and resources (e.g., timers, voltage regulators, oscillators, etc.), any or all of which may be included in one or more cores.

A number of different types of memories and memory technologies are available or contemplated in the future, all of which are suitable for use with the various aspects. Such memory technologies/types include phase change random access memory (PRAM), dynamic random access memory (DRAM), static random access memory (SRAM), non-volatile random access memory (NV RAM), pseudostatic random access memory (PSRAM), double data rate (DDR) synchronous dynamic random access memory (SDRAM), and other random access memory (RAM) and read-only memory (ROM) technologies known in the art. A DDR SDRAM memory may be a DDR type 1 SDRAM memory, DDR type2 SDRAM memory, DDR type 3 SDRAM memory, or a DDR type 4 SDRAM memory. Each of the above-mentioned memory technologies include, for example, elements suitable for storing instructions, programs, control signals, and/or data for use in or by a computer or other digital electronic device. Any references to terminology and/or technical details related to an individual type of memory, interface, standard or memory technology are for illustrative purposes only, and not intended to limit the scope of the claims to a particular memory system or technology unless specifically recited in the claim language.

In recent years, mobile computing device architectures have grown in complexity, and now commonly include multiple processor cores, system-on-chips (SOCs), co-processors, functional modules including dedicated processors (e.g., communication modem chips, GPS receivers, etc.), complex memory systems, intricate electrical interconnections (e.g., buses and/or fabrics), and numerous other resources that execute complex and power intensive software applications (e.g., video streaming applications, etc.). With this rise in complexity, new memory management solutions are required to improve the computational and power management performance of mobile devices.

Current devices utilize many different communications protocols (including machine-to-machine and machine-to-human protocols), and therefore need a high degree of parallelism, i.e., the ability for the different communications protocols to concurrently access a memory space via multiple avenues. This requires unblocked interaction and/or data transport between the several communications protocols. A majority of the data is stored in dedicated storage chips (e.g., DRAM, flash, etc.). Due to the nature of separate chips, the data is accessed via interfaces, designed to inter-operate among several functional chips. Due to a high degree of concurrent access requirements, an interface is often bottlenecked, and is constantly revised (e.g., DDR, DDR2, DDR3, DDR4, LP DDR, eMMC, Serial Flash, and RAMBUS).

Certain aspects of the disclosure are directed to storage organization that allows for a high degree of freedom for interfacing and access streamlining multi-protocol communication devices. In an aspect, an interfacing strategy is manipulated to expose an internal multitude of degrees of freedom, inherent in a storage function, beyond an “implementation boundary.” This allows for higher concurrency at lower costs, in terms of power, and aggregated platform implementation. Hence, more functions may be performed for less joules total.

The storage organization may be quantized in three dimensions to serve the needs of communications IC. An aspect may include interface access parallelism per pin, per unit wait time. For example, multiple interfaces may concurrently access portions of a memory (access domains) in parallel. The access may be based on interface usage requirements, such as a memory size requirement, a bandwidth requirement, and/or a latency requirement. Another aspect may include power segmentation. For example, access domains may be separately power-controlled to allow for multiple sub-regulated domains that are dynamically optimized for a prevailing case being used at the moment as dictated by a device application.

The storage organization may further provide for spatially mapped pseudo cache implementations with aggregated storage banks in shared power domains, and interface bundles; routers (micro-routers), which are fast switch networks that allow the isolation necessary to support concurrent memory access and path finding to allow for reach to any word of storage cells, to trade off locality of reference and latency; and multiple interface ports to allow for concurrent and contention free access to in-place computation.

Certain aspects of the invention may be applicable to communications links deployed between electronic components, which may include subcomponents of devices such as telephones, mobile computing devices, appliances, automobile electronics, avionics systems, etc. Referring toFIG. 1, for example, an apparatus100may include a processing circuit102that is configured to control operation of the apparatus100. The processing circuit102may access and execute software applications and control logic circuits and other devices within the apparatus100. In one example, the apparatus100may include a wireless communication device that communicates through a radio frequency (RF) communications transceiver106with a radio access network (RAN), a core access network, the Internet and/or another network. The RF communications transceiver106may be operably coupled to a processing circuit102. The processing circuit102may include one or more IC devices, such as an application specific integrated circuit (ASIC)108. The ASIC108may include one or more processing devices, logic circuits, and so on. The processing circuit102may include and/or be coupled to processor readable storage112that may maintain instructions and data that may be executed by the processing circuit102. The processing circuit102may be controlled by one or more of an operating system and an application programming interface (API)110layer that supports and enables execution of software modules residing in the storage112of the wireless device. The storage112may include read-only memory (ROM) or random access memory (RAM), electrically erasable programmable read-only memory (EEPROM), a flash memory device, or any memory device that can be used in processing systems and computing platforms. The processing circuit102may include and/or access a local database114that can maintain operational parameters and other information used to configure and operate the apparatus100. The local database114may be implemented using one or more of a database module/circuit/processor or server, flash memory, magnetic media, EEPROM, optical media, tape, soft or hard disk, or the like. The processing circuit may also be operably coupled to external devices such as an antenna122, a display124, operator controls, such as a button128and a keypad126, among other components.

FIG. 2is a block schematic illustrating certain aspects of an apparatus200such as a wireless mobile device, a mobile telephone, a mobile computing system, a wireless telephone, a notebook computer, a tablet computing device, a media player, a gaming device, or the like. The apparatus200may include a plurality of IC devices202and230that exchange data and control information through a communications link220. The communications link220may be used to connect the IC devices202and230, which may be located in close proximity to one another or physically located in different parts of the apparatus200. In one example, the communications link220may be provided on a chip carrier, substrate or circuit board that carries the IC devices202and230. In another example, a first IC device202may be located in a keypad section of a flip-phone while a second IC device230may be located in a display section of the flip-phone. A portion of the communications link220may include a cable or an optical connection.

The communications link220may include multiple channels222,224and226. One or more channel226may be bidirectional, and may operate in half-duplex mode and/or full-duplex mode. One or more channels222,224may be unidirectional. The communications link220may be asymmetrical, providing higher bandwidth in one direction. In one example described herein, a first communications channel222may be referred to as a forward link222while a second communications channel224may be referred to as a reverse link224. The first IC device202may be designated as a host, master and/or transmitter, while the second IC device230may be designated as a client, slave and/or receiver, even if both IC devices202and230are configured to transmit and receive on the communications link220. In one example, the forward link222may operate at a higher data rate when communicating data from a first IC device202to a second IC device230, while the reverse link224may operate at a lower data rate when communicating data from the second IC device230to the first IC device202.

The IC devices202and230may each include a processor or other processing and/or computing circuit or device206,236. In one example, the first IC device202may perform core functions of the apparatus200, including maintaining wireless communications through a wireless transceiver204and an antenna214, while the second IC device230may support a user interface that manages or operates a display controller232, and may control operations of a camera or video input device using a camera controller234. Other features supported by one or more of the IC devices202and230may include a keyboard, a voice-recognition component, and other input or output devices. The display controller232may include circuits and software drivers that support a display such as a liquid crystal display (LCD) panel, a touch-screen display, an indicator, and so on. The storage media208and238may include transitory and/or non-transitory storage devices adapted to maintain instructions and data used by the respective processing circuits206and236, and/or other components of the IC devices202and230. Communication between each processing circuit206,236and its corresponding storage media208and238and other modules/processors and circuits may be facilitated by one or more buses212and242, respectively.

The reverse link224may be operated in the same manner as the forward link222. The forward link222and the reverse link224may be capable of transmitting at comparable speeds or at different speeds, where speed may be expressed as a data transfer rate and/or a clocking rate. The forward and reverse data rates may be substantially the same or may differ by orders of magnitude, depending on the application. In some applications a single bidirectional link226may support communications between the first IC device202and the second IC device230. The forward link222and/or the reverse link224may be configurable to operate in a bidirectional mode when, for example, the forward and reverse links222and224share the same physical connections and operate in a half-duplex manner.

In certain examples, the reverse link224derives a clocking signal from the forward link222for synchronization purposes, for control purposes, to facilitate power management and/or for simplicity of design. The clocking signal may have a frequency that is obtained by dividing the frequency of a symbol clock used to transmit signals on the forward link222. The symbol clock may be superimposed or otherwise encoded in symbols transmitted on the forward link222. The use of a clocking signal that is a derivative of the symbol clock allows fast synchronization of transmitters and receivers (transceivers210,240) and enables fast start and stop of data signals without the need for framing to enable training and synchronization.

In certain examples, a single bidirectional link226may support communications between the first processing device (first IC device)202and the second processing device (second IC device)230. In some instances, the first processing device202and the second processing device230provide encoding and decoding of data, address and control signals transmitted between a processing device and memory devices such as dynamic random access memory (DRAM). In one example, one or more of buses212and/or242may provide access to the DRAM using one of various encoding techniques.

FIG. 3illustrates example components and interconnections in a system-on-chip (SOC)300suitable for implementing various aspects of the disclosure. The SOC300may include a number of heterogeneous processors, such as a digital signal processor (DSP)302, a modem processor304, a graphics processor306, and an application processor308. Each processor302,304,306,308, may include one or more cores, and each processor/core may perform operations independent of the other processors/cores. The processors302,304,306,308may be organized in close proximity to one another (e.g., on a single substrate, die, integrated chip, etc.) so that they may operate at a much higher frequency/clock-rate than would be possible if the signals were to travel off-chip. The proximity of the cores may also allow for the sharing of on-chip memory and resources (e.g., voltage rail), as well as for more coordinated cooperation between cores.

The SOC300may include analog circuitry and custom circuitry314for managing sensor data, analog-to-digital conversions, wireless data transmissions, and for performing other specialized operations (e.g., decoding high-definition video, video processing, etc.). The SOC300may further include various system components and resources316, such as voltage regulators, oscillators, phase-locked loops, peripheral bridges, data controllers, system controllers, access ports, timers, and other similar components used to support the processors and software clients running on the computing device. The system components and resources316and custom circuitry314may also include circuitry for interfacing with peripheral devices, such as cameras, electronic displays, wireless communication devices, external memory chips, etc.

The SOC300may further include a universal serial bus (USB) controller324, and one or more memory controllers326. The SOC300may also include an input/output module/circuit/processor (not illustrated) for communicating with resources external to the SOC300, such as a clock318and a voltage regulator320, each of which may be shared by two or more of the internal SOC components.

The processors302,304,306,308may be interconnected to the USB controller324, the memory controller326, system components and resources316, custom circuitry314, and other system components via an interconnection/bus module/circuit/processor330, which may include an array of reconfigurable logic gates and/or implement a bus architecture. In an aspect, the interconnection/bus module/circuit/processor330may be equivalent to the bus212and/or bus242ofFIG. 2. Communications may also be provided by advanced interconnects, such as high performance networks-on chip (NoCs).

The memory controller326may be a specialized hardware module/circuit/processor configured to manage the flow of data to and from memory328. In an aspect, the memory controller326may include logic for interfacing with the memory328, such as selecting a row and column corresponding to a memory location, reading or writing data to the memory location, etc.

In another aspect, routers340may be embedded within the memory328. Via the custom circuitry314, the system components and resources316, and/or the memory controller326, the routers340may manage concurrent access (data flow) between application interface circuits and memory locations (e.g., storage bank domains) of the memory328. For example, the routers340allow for one application interface circuit of a first interface group to access one memory location of the memory328while a different application interface circuit of a second interface group accesses a different memory location of the memory328. In an aspect, each of the routers340may be located adjacent to a corresponding set of memory locations. Accordingly, data having a low-latency requirement may be sent from an application interface circuit of an interface group to a memory location via a router340providing lowest-latency access to the memory location. Each of the routers340may include logic for interfacing with the memory328, such as selecting a row and column corresponding to a memory location, reading or writing data to the memory location, etc.

FIG. 4is a diagram illustrating a functional organization of modules/circuits/processors within a device400. The device400may include an information storage module/circuit/processor402configured to store information. The information storage module/circuit/processor402may, for example, be flash memory, DRAM, DDR memory, etc. The device400may also include a module/circuit/processor404configured to archive and/or retrieve information between the information storage module/circuit/processor402and other modules/circuits/processors of the device400. The device400may also include modules/circuits/processors dedicated to power control/consumption, such as a replenish/regulate module/circuit/processor406and an energy storage/gradient module/circuit/processor408. A multimedia subsystem module/circuit/processor410may operate with a number of different technology components, such as a display module/circuit/processor, a camera module/circuit/processor, a speaker module/circuit/processor, a microphone module/circuit/processor, a haptics module/circuit/processor, and a sensors module/circuit/processor. A communications service subsystem module/circuit/processor420may also operate with a number of different technology components, such as a GPS module/circuit/processor, a near-field communication (NFC) module/circuit/processor, a wireless wide area network (WWAN) module/circuit/processor, a wireless local area network (WLAN) module/circuit/processor, an FM module/circuit/processor, and a Bluetooth module/circuit/processor. Below the multimedia subsystem module/circuit/processor410and the communications service subsystem module/circuit/processor420may lie a transduction module/circuit/processor422and an interaction module/circuit/processor424. Above the multimedia subsystem module/circuit/processor410and the communications service subsystem module/circuit/processor420may lie a heterogeneous compute module/circuit/processor426and a security concerns module/circuit/processor428.

As shown inFIG. 4, multiple technology components (e.g., the display module/circuit/processor, the camera module/circuit/processor, the speaker module/circuit/processor, the microphone module/circuit/processor, the GPS module/circuit/processor, the NFC module/circuit/processor, the WWAN module/circuit/processor, the WLAN module/circuit/processor, and/or the FM module/circuit/processor) may need to access (denoted by dashed arrows) the common information storage module/circuit/processor402in order to store and/or retrieve data/code. However, previous systems allow for the different technology components to access the common information storage module/circuit/processor402at a high cost with a long delay. Accordingly, there is a need for a system that allows multiple technology components to concurrently access a common information storage at a reduced cost and a shorter delay.

FIG. 5is a diagram illustrating an organization of memory storage banks (arrays) in a memory space500. Storage banks may be accessed by different technology components through a common data interface502and a common address interface504. As shown inFIG. 5, the common data interface502and the common address interface504may be used to access all storage banks.

In a parallel system, wherein multiple applications (e.g., multiple technology components) may wish to access the memory at the same time, a bottleneck510occurs due to a single interface (common data interface502/address interface504) being the only avenue available through which the multiple applications can access the memory (referred to as a “single degree of freedom”506inFIG. 5). Thus, an application must wait to access the memory if another application is already accessing the memory via the single interface. Within the memory, “several internal degrees of freedom”508are available in that different storage banks of the memory are capable of being accessed separately. However, even if different applications wish to use the different storage banks, respectively, the different applications are forced to go through the single interface to access the different storage banks. Hence, access is limited by the ability of the single interface to handle the multiple access attempts. To overcome the single interface bottleneck510, a previous solution is to increase the processing speed of the single interface to accommodate for the multiple applications wanting to access the memory. However, the previous solution is problematic because the increase of processing speed comes at the cost of the single interface consuming more power.

To overcome the problems stated above, aspects of the present disclosure provide an alternative scheme for organizing the memory.FIG. 6is a diagram600illustrating an example logical topology for organizing a memory according to the present disclosure. The memory may include a DDR memory including a DDR Bank0602(0), a DDR Bank1602(1), and a DDR Bank2602(3) up to a DDR BankN602(N). The memory may further include a FLASH memory including a FLASH Bank0604(0) and a FLASH Bank1604(1) up to a FLASH BankN604(N). Communications to and from the memory banks may be provided by an advanced interconnect, such as a memory NoC606. A number of interfaces, such as serializer/deserializer (SERDES) interfaces608a,608b,610a, and610bmay operate with the memory NoC606to access one or more of the memory banks. In an example, an application may access one or more of the memory banks via a long reach channel using the SERDES interface608aor608b. In another example, application may access one or more of the memory banks via a short reach channel using the SERDES interface610aor610b. A DDR access channel612may also be provided to operate with the memory NoC606to access one or more of the memory banks.

FIG. 7is a diagram700illustrating an example physical topology for organizing a memory according to the present disclosure. As shown inFIG. 7, a logic die702may lie at a lower end of the topology. A DRAM die704may be located above the logic die702. A FLASH die706may be located above the DRAM die704. Finally, a package encapsulation708may lie above the FLASH die706.

FIG. 8is a diagram illustrating an organization of a memory space800.FIG. 9is a diagram illustrating a router900in accordance with aspects of the present disclosure. The router900may include a number of transistors, for example, a first transistor902, a second transistor904, a third transistor906, a fourth transistor908, a fifth transistor910, a sixth transistor912, a seventh transistor914, and an eighth transistor916. The router900may further include a router control module/circuit/processor918coupled to a router configuration module/circuit/processor920. The router control module/circuit/processor918may be configured to control operations of the router900. The router configuration module/circuit/processor920may be configured to store configuration information related to the routing of data between a storage bank/storage bank domain and an application interface circuit. The router900may also include a first power control module/circuit/processor922and a second power control module/circuit/processor924.

In an aspect, a gate of each of the transistors902to916is coupled to an output of the router control module/circuit/processor918. A drain of each of the first transistor902, the second transistor904, the third transistor906, and the fourth transistor908is coupled to an input of the router control module/circuit/processor918and an input of the second power control module/circuit/processor924. An output of the second power control module/circuit/processor924is coupled to an upstream sense module/circuit/processor (e.g., sense module/circuit/processor804inFIG. 8). The second power control module/circuit/processor924is further coupled to a power switch and a ground node.

A source of each of the fifth transistor910, the sixth transistor912, the seventh transistor914, and the eighth transistor916is coupled to an output of the router configuration module/circuit/processor920and an output of the first power control module/circuit/processor922. An input of the first power control module/circuit/processor922is coupled to an upstream sense module/circuit/processor (e.g., sense module/circuit/processor804). The first power control module/circuit/processor922is further coupled to a power switch and a ground node.

As an example, the router900may be configured to manage concurrent data flow between a number of application interface circuits (e.g., interface circuits812) and four storage bank domains (e.g., four storage bank domains806inFIG. 8). Accordingly, each of the transistors902to916may be connected to storage banks of a particular storage bank domain to facilitate a data flow operation with such storage banks. For example, a source of the first transistor902is coupled to storage bank outputs of a first storage bank domain (bank domain A) and a drain of the fifth transistor910is coupled to storage bank inputs of the bank domain A; a source of the second transistor904is coupled to storage bank outputs of a second storage bank domain (bank domain B) and a drain of the sixth transistor912is coupled to storage bank inputs of the bank domain B; a source of the third transistor906is coupled to storage bank outputs of a third storage bank domain (bank domain C) and a drain of the seventh transistor914is coupled to storage bank inputs of the bank domain C; and a source of the fourth transistor908is coupled to storage bank outputs of a fourth storage bank domain (bank domain D) and a drain of the eighth transistor916is coupled to storage bank inputs of the bank domain D.

FIG. 10is a diagram1000illustrating a physical topology for organizing a memory. As shown inFIG. 10, the topology includes a storage die1002, an interposer1004, an interface (IF)/logic die1006, and a multi-processor modem IC1008. The storage die1002is coupled to the interposer1004by a first set of interconnects1012. The interposer1004is coupled to the IF/logic die1006and the multi-processor modem IC1008by a second set of interconnects1014. A third set of interconnects1016may couple the IF/logic die1006and/or the multi-processor modem IC1008to other dies or a printed circuit board (PCB) (not shown).

Referring toFIGS. 6 to 10, the present disclosure provides for different applications (different technology components) to have individual interfaces for accessing the memory. The different applications accessing the memory may be on the same SOC on which the memory resides (on-chip), or on SOCs different from the SOC on which the memory resides (off-chip). Accordingly, the applications may access desired portions of the memory (storage bank) via their respective interfaces without having to wait for an application to complete an access attempt, such as in the single interface scheme described above.

Referring toFIG. 8, the memory space800provides an organization of power control modules/circuits/processors802, sense modules/circuits/processors804, memory storage bank domains806, memory storage banks808, and routers810that allows for a higher degree of freedom. Surrounding the memory space800are application interface circuits812representing the different applications accessing the memory storage banks808.

As shown inFIG. 8, the storage banks808are grouped into storage bank domains (access domains)806. Traditionally, each of the storage banks808may be identified/organized by row and column. The present disclosure now implements another layer of organization by grouping the storage banks808into the storage bank domains806. A storage bank domain806provides a fast path to an exclusive memory area for accommodating different flows to/from the different application interface circuits812. Each storage bank domain806is connected to a router810that allows fast access to the exclusive memory area. The routers810are embedded in the memory space800and allow for de-coupled operation for all the different flows to/from the different application interface circuits812. Via the routers810, the multiple interface circuits812are provided with a high degree of freedom, i.e., the interface circuits are provided with multiple avenues for accessing the desired memory storage banks808concurrently/simultaneously. Hence, additional buffering is prevented, such as in the single interface scheme described above.

In an aspect, the routers810are configurable elements which can be used to dynamically allocate each of the storage bank domains806to a given application interface circuit812. The proximity of the application interface circuit812to the storage bank domain806may be determined by a number of router hops. The distance from the application interface circuit812to the storage bank domain806determines a total latency.

According to the scheme described with respect toFIG. 8, a small number of transactions from different application interface circuits812have overlapping or shared memory access. Largely, the memory storage banks808are more-or-less exclusive to individual application interface circuits812. Accordingly, throughput may be increased, costs may be lowered, and overall power consumption may be reduced.

According to an aspect of the disclosure, referring again toFIG. 8, a memory space800within a memory device may be divided into a number of storage bank domains (access domains)806. Moreover, application interface circuits812(representing different applications) intending to access the memory space800may be classified into a plurality of interface groups based on one or more application requirements. The one or more application requirements may include an application storage size requirement, an application interface bandwidth requirement, and/or an application interface latency requirement. Each interface group of the plurality of interface groups may be assigned to a corresponding storage bank domain806.

A plurality of routers810(e.g., routers/micro-routers810athrough810f) manage concurrent data flow between the plurality of interface groups and the storage bank domains. As such, the routers810provide access between each interface group and the corresponding storage bank domain806. In particular, the routers810allow for one interface circuit (e.g. interface circuit812a) of one interface group to access its corresponding storage bank domain (e.g., storage bank domain806a) at the same time as (concurrently with) another interface circuit (e.g., interface circuit812b) of another interface group accessing its own corresponding storage bank domain (e.g., storage bank domain806b).

Each router of the plurality of routers810is located adjacent to a corresponding set of storage banks. The corresponding set of storage banks may include storage banks of different storage bank domains. For example, the router810fis located adjacent to a set of storage banks that includes storage banks808from the storage bank domain806band the storage bank domain806c. In an aspect, when data having a low-latency requirement is to be sent from an interface circuit of an interface group to a storage bank of a corresponding storage bank domain, the data may be sent via a router providing lowest-latency access to the storage bank. For example, when data from the interface circuit812ahaving a low-latency requirement is to be sent to a storage bank within the storage bank domain806c, the data may be sent via the router810, which provides the lowest latency access to the storage bank.

In a further aspect, the storage bank domains806are separately power-controlled via power control module/circuit/processor802. This allows for dynamically optimizing each of the storage bank domains806separately according to usage requirements of an interface group corresponding to a particular storage bank domain.

In an aspect, the interface circuits812may be grouped, determine an assigned storage bank domain(s), and learn of which router(s) to access the storage bank domain(s) via a system configuration message. When the application interface circuit812sends information/data to a router810for storing in a particular storage bank808, the application interface circuit812includes an address bit/token in the information/data. The address bit/token may identify the particular storage bank domain806and/or the particular storage bank808the application interface circuit812wishes to access. Once the information/data is received by the router810, the router810may determine via the address bit/token in which storage bank808to store the information/data. If the address bit/token belongs to a storage bank808managed by the router810, the router810will store the information/data in the appropriate storage bank808. If the address bit/token does not belong to a storage bank managed by the router810, the router10will forward the information/data to an appropriate router for further handling.

In an aspect, the application interface circuits812may be configured such that storage bank addresses most frequently used by the application interface circuits may be accessed using one router hop. Storage bank addresses less frequently used by the application interface circuits may be accessed using multiple router hops.

FIG. 11is a flowchart illustrating a method of accessing a memory device (e.g. memory328or memory space800). The method may be performed by an apparatus (e.g., apparatus100or SOC300).

At1102, the apparatus may divide a memory space within the memory device into a plurality of storage bank domains. In an aspect, the apparatus may separately power-control the storage bank domains.

At1104, the apparatus may classify application interface circuits (e.g., interface circuits812) configured to access the memory space into a plurality of interface groups based on one or more application usage requirements. The one or more application usage requirements may include an application storage size requirement, an application interface bandwidth requirement, or an application interface latency requirement.

At1106, the apparatus may assign each interface group of the plurality of interface groups to a corresponding storage bank domain from the plurality of storage bank domains.

At1108, the apparatus may provide access between each interface group and the corresponding storage bank domain. In an aspect, a first application interface circuit of a first interface group accesses a first corresponding storage bank domain while a second application interface circuit of a second interface group accesses a second corresponding storage bank domain. The access may be provided by a plurality of routers (e.g., routers340, routers810, or router900) managing concurrent data flow between the plurality of interface groups and the storage bank domains. The plurality of routers may be located between the application interface circuits and the plurality of storage bank domains.

In an aspect, each router of the plurality of routers is located adjacent to a corresponding set of storage banks, wherein the corresponding set of storage banks includes storage banks of different storage bank domains. Accordingly, at1110, the apparatus may send data having a low-latency requirement from an application interface circuit of an interface group to a storage bank of a corresponding storage bank domain via a router providing lowest-latency access to the storage bank.

FIG. 12is an illustration of an apparatus1200configured to support operations related to accessing a memory device according to one or more aspects of the disclosure (e.g., aspects related to the method ofFIG. 11described above). The apparatus1200includes a communication interface (e.g., at least one transceiver)1202, a storage medium1204, a user interface1206, a memory device1208, and a processing circuit1210.

These components can be coupled to and/or placed in electrical communication with one another via a signaling bus or other suitable component, represented generally by the connection lines inFIG. 12. The signaling bus may include any number of interconnecting buses and bridges depending on the specific application of the processing circuit1210and the overall design constraints. The signaling bus links together various circuits such that each of the communication interface1202, the storage medium1204, the user interface1206, and the memory device1208are coupled to and/or in electrical communication with the processing circuit1210. The signaling bus may also link various other circuits (not shown) such as timing sources, peripherals, voltage regulators, and power management circuits, which are well known in the art, and therefore, will not be described any further.

The communication interface1202may be adapted to facilitate wireless communication of the apparatus1200. For example, the communication interface1202may include circuitry and/or code (e.g., instructions) adapted to facilitate the communication of information bi-directionally with respect to one or more communication devices in a network. The communication interface1202may be coupled to one or more antennas1212for wireless communication within a wireless communication system. The communication interface1202can be configured with one or more standalone receivers and/or transmitters, as well as one or more transceivers. In the illustrated example, the communication interface1202includes a transmitter1214and a receiver1216.

The memory device1208may represent one or more memory devices. As indicated, the memory device1208may maintain network-related information1218along with other information used by the apparatus1200. In some implementations, the memory device1208and the storage medium1204are implemented as a common memory component. The memory device1208may also be used for storing data that is manipulated by the processing circuit1210or some other component of the apparatus1200.

The storage medium1204may represent one or more computer-readable, machine-readable, and/or processor-readable devices for storing code, such as processor executable code or instructions (e.g., software, firmware), electronic data, databases, or other digital information. The storage medium1204may also be used for storing data that is manipulated by the processing circuit1210when executing code. The storage medium1204may be any available media that can be accessed by a general purpose or special purpose processor, including portable or fixed storage devices, optical storage devices, and various other mediums capable of storing, containing or carrying code.

By way of example and not limitation, the storage medium1204may include a magnetic storage device (e.g., hard disk, floppy disk, magnetic strip), an optical disk (e.g., a compact disc (CD) or a digital versatile disc (DVD)), a smart card, a flash memory device (e.g., a card, a stick, or a key drive), a random access memory (RAM), a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), a register, a removable disk, and any other suitable medium for storing code that may be accessed and read by a computer. The storage medium1104may be embodied in an article of manufacture (e.g., a computer program product). By way of example, a computer program product may include a computer-readable medium in packaging materials. In view of the above, in some implementations, the storage medium1204may be a non-transitory (e.g., tangible) storage medium.

The storage medium1204may be coupled to the processing circuit1210such that the processing circuit1210can read information from, and write information to, the storage medium1204. That is, the storage medium1204can be coupled to the processing circuit1210so that the storage medium1204is at least accessible by the processing circuit1210, including examples where at least one storage medium is integral to the processing circuit1210and/or examples where at least one storage medium is separate from the processing circuit1210(e.g., resident in the apparatus1200, external to the apparatus1200, distributed across multiple entities, etc.).

Code and/or instructions stored by the storage medium1204, when executed by the processing circuit1210, causes the processing circuit1210to perform one or more of the various functions and/or process operations described herein. For example, the storage medium1204may include operations configured for regulating operations at one or more hardware blocks of the processing circuit1210, as well as to utilize the communication interface1202for wireless communication utilizing their respective communication protocols.

The processing circuit1210is generally adapted for processing, including the execution of such code/instructions stored on the storage medium1204. As used herein, the term “code” or “instructions” shall be construed broadly to include without limitation programming, instructions, instruction sets, data, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise.

The processing circuit1210is arranged to obtain, process and/or send data, control data access and storage, issue commands, and control other desired operations. The processing circuit1210may include circuitry configured to implement desired code provided by appropriate media in at least one example. For example, the processing circuit1210may be implemented as one or more processors, one or more controllers, and/or other structure configured to execute executable code. Examples of the processing circuit1210may include a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic component, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may include a microprocessor, as well as any conventional processor, controller, microcontroller, or state machine. The processing circuit1210may also be implemented as a combination of computing components, such as a combination of a DSP and a microprocessor, a number of microprocessors, one or more microprocessors in conjunction with a DSP core, an ASIC and a microprocessor, or any other number of varying configurations. These examples of the processing circuit1210are for illustration and other suitable configurations within the scope of the disclosure are also contemplated.

According to one or more aspects of the disclosure, the processing circuit1210may be adapted to perform any or all of the features, processes, functions, operations and/or routines for any or all of the apparatuses described herein. As used herein, the term “adapted” in relation to the processing circuit1210may refer to the processing circuit1210being one or more of configured, employed, implemented, and/or programmed to perform a particular process, function, operation and/or routine according to various features described herein.

According to at least one example of the apparatus1200, the processing circuit1210may include one or more of a memory space dividing circuit/module1220, an application interface/interface group classifying circuit/module1222, an interface group/storage bank domain assigning circuit/module1224, an access providing circuit/module1226, a data sending circuit/module1228, and a power control circuit/module1230.

The memory space dividing circuit/module1220may include circuitry and/or instructions (e.g., memory space dividing instructions1232stored on the storage medium1204) adapted to perform several functions relating to, for example, dividing a memory space within a memory device1208into a plurality of storage bank domains.

The application interface/interface group classifying circuit/module1222may include circuitry and/or instructions (e.g., application interface/interface group classifying instructions1234stored on the storage medium1204) adapted to perform several functions relating to, for example, classifying application interface circuits configured to access the memory space into a plurality of interface groups based on one or more application usage requirements. The one or more application usage requirements may include an application storage size requirement, an application interface bandwidth requirement, and/or an application interface latency requirement.

The interface group/storage bank domain assigning circuit/module1224may include circuitry and/or instructions (e.g., interface group/storage bank domain assigning instructions1236stored on the storage medium1204) adapted to perform several functions relating to, for example, assigning each interface group of the plurality of interface groups to a corresponding storage bank domain from the plurality of storage bank domains.

The access providing circuit/module1226may include circuitry and/or instructions (e.g., access providing instructions1238stored on the storage medium1204) adapted to perform several functions relating to, for example, providing access between each interface group and the corresponding storage bank domain, wherein a first application interface circuit of a first interface group accesses a first corresponding storage bank domain while a second application interface circuit of a second interface group accesses a second corresponding storage bank domain. The access providing circuit/module1226may provide the access via a plurality of routers managing concurrent data flow between the plurality of interface groups and the storage bank domains, wherein the plurality of routers are located between the application interface circuits and the plurality of storage banks.

The data sending circuit/module1228may include circuitry and/or instructions (e.g., data sending instructions1240stored on the storage medium1204) adapted to perform several functions relating to, for example, sending data having a low-latency requirement from an application interface circuit of an interface group to a storage bank of a corresponding storage bank domain via a router providing lowest-latency access to the storage bank.

The power control circuit/module1230may include circuitry and/or instructions (e.g., power control instructions1242stored on the storage medium1204) adapted to perform several functions relating to, for example, separately power-controlling the storage bank domains.

As mentioned above, instructions stored by the storage medium1204, when executed by the processing circuit1210, causes the processing circuit1210to perform one or more of the various functions and/or process operations described herein. For example, the storage medium1204may include one or more of the memory space dividing instructions1232, the application interface/interface group classifying instructions1234, the interface group/storage bank domain assigning instructions1236, the access providing instructions1238, the data sending instructions1240, and the power control instructions1242.

It is understood that the specific order or hierarchy of steps in the processes disclosed is an illustration of exemplary approaches. The specific order or hierarchy of steps in the processes may be rearranged based upon design preferences. The accompanying method claims present elements of the various steps in a sample order, and are not meant to be limited to the specific order or hierarchy presented.