Phase synchronization system

A phase synchronization circuit for processing a received signal, the phase of which is detected by a first reference carrier from a fixed oscillator and a second reference carrier orthogonal to the first reference carrier. Two baseband signals are thus obtained and sampled with a certain period. Converters convert these two signals into digital values. Phase and amplitude values at each sample point are obtained from these digital values orthogonal to each other. The frequency and phase differences between the received signal and each of the first and second reference carriers are estimated by an optimization method by utilization of pluralities of phase and amplitude data obtained with a fixed period of time. The voltage-controlled oscillator and the phase shifter are controlled with the estimated values for generating a recovered carrier of a phase synchronized with the received signal. A circuit is provided in which the hysteresis of frequency and phase differences are stored at the time of current estimation. The stored values and currently-estimated values are compared with each other. On the basis of the results of the comparison of these values, the received signal is analogized. The numbers of data samples for use in the estimation of the frequency and phase differences are made variable according to the result analogy, thereby achieving an optimum phase synchronization in accordance with the state of the received signal.

BACKGROUND OF THE INVENTION 
1. Technical Field of the Invention 
The present invention relates to a phase synchronization system which 
follows the frequency and the phase of an input signal. 
2. Prior Art and Its Problem 
Heretofore a phase synchronization circuit of the PLL (Phase Locked Loop) 
system has widely been used, for example, in a carrier recovery circuit 
for creating a reference carrier necessary for demodulating a 
phase-modulated signal and a frequency tracking circuit for tracking a 
certain electric wave. The frequency and phase pull-in characteristics of 
the phase synchronization circuit of the PLL system depend on an 
equivalent noise band width (a loop band width) which is determined by a 
loop gain and characteristics of a loop filter and a phase comparator. An 
increase in the loop band width will quicken the occurrence of the pull-in 
operation and a decrease in the loop band width will defer the occurrence 
of the pull-in operation. However, when the loop band width is large, an 
output phase jitter in the steady state is large, whereas when the loop 
band width is narrow the jitter is small. 
In general, a phase synchronization circuit is required to have a quick 
pull-in characteristic and to be small in the phase jitter in the steady 
state, but these two requirements are contradictory to each other, as 
mentioned above. 
An example of the prior art for solving this problem has been employed in a 
carrier recovery circuit of the TDMA communication system. Since a TDMA 
signal is composed of a plurality of asynchronous burst signals, its 
demodulation calls for a demodulating operation which takes place while 
generating a reference carrier for each burst signal, and the carrier 
recovery circuit needs to be capable to establishing synchronization in a 
very short period of time. 
Furthermore, since the TDMA signal is generally high in transmission rate, 
it is required that the phase jitter in the steady state be very small. To 
meet this requirement, the carrier recovery circuit is controlled so that 
in the pull-in state it increases the loop gain to widen the loop band to 
quicken the pull-in operation and in the steady state it decreases the 
loop gain to narrow the loop band to reduce the phase jitter. 
FIG. 1 shows an example of the constitution of the above-said prior art. In 
FIG. 1(a) reference numeral 101 indicates a signal input terminal, 102 a 
phase comparator, 103 a VCO (Voltage-Controlled Oscillator), 104 an 
amplifier, 105 a loop filter, 106 a timing signal input terminal, and 107 
an output terminal. FIG. 1(b) shows the phase comparison characteristic of 
the phase comparator 102, the abscissa representing the phase difference 
.theta. between the input signal and the output signal from the VCO 103 
and the ordinate the output voltage. 
The prior art example shown in FIG. 1 operates in the following manner. The 
phase comparator 102 outputs, as a voltage, the difference in phase 
between the input signal and the output signal from the VCO 103. This 
voltage is applied via the amplifier 104 and the loop filter 105 to the 
VCO 103, controlling it so that the frequency and the phase of its 
oscillation signal approach the frequency and the phase of the input 
signal. The amplifier 104 is to adjust the loop gain for changing the loop 
band width, depending on whether the circuit performs the pull-in or 
steady-state operation, as referred to previously. The amplification 
degree of the amplifier is controlled by a timing signal which is 
separately detected and applied to the terminal 106. 
This system has a defect of needing, for changing the loop band width, 
timing information as to when the pull-in operation is to be started and 
when the steady state has been restored. This necessitates the use of a 
circuit for detecting the timing and generating the timing information, 
and hence introduces complexity in the apparatus. 
On the other hand, the phase synchronization circuit of the PLL system 
suffers also the degradation of the phase pull-in characteristic which is 
commonly referred to as a hang-up phenomenon, and difficulty has been 
encountered in employing this circuit in a case where phase 
synchronization must be established in a short period of time. 
The hang-up phenomenon refers to a state in which when the phase difference 
between the input signal 101 and the output signal of the VCO 103 at the 
terminal 107 is .pi., the output of the phase comparator 102 beciomes zero 
and the phase of oscillation of the VCO 103 undergioes no change, with the 
result that the phase difference settles into .pi., making it impossible 
to establish synchronization as will be seen from the phase comparison 
characteristic shown in FIG. 1(b). Moreover, when the phase difference is 
not exactly equal to .pi. but very close to .pi., a phenomenon occurs 
which can be regarded as the hang-up phenomenon; in this case, the output 
of the phase comparator 102 becomes close to zero and much time is needed 
for establishing synchronization. 
A method which prevents this hang-up phenomenon and improves the pull-in 
characteristic is set forth in a literature entitled "Studies of Carrier 
Recovery Circuit for Use in Synchronous Demodulation of TDMA Signal" 
(Journal of Institute of Electronics and Communication Engineers of Japan, 
Vol. 54-B, No. 4, 1971, pp. 160-167). This method is called a kick off 
system, according to which the phase difference is measured at the start 
of synchronization and if the phase difference is close to .pi., the phase 
difference is forcibly shifted by .pi. from a hang-up region (near .pi.) 
to a stable region (near zero). This system also has the drawback that 
information on the starting timing for synchronization operation is needed 
for operation, as is the case with the system which employs different loop 
gains for the pull-in operation and the steady-state operation. Besides, 
according to this system, when the input signal contains noise, there are 
cases where the hang-up phenomenon cannot be detected or the noise is 
detected as the hang-up phenomenon; namely, this system suffers so-called 
nondetection and erroneous detection, and hence cannot yet completely 
eliminate the hang-up phenomenon. 
SUMMARY OF THE INVENTION 
An object of the present invention is to provide a phase synchronization 
system which obviates the above-mentioned defects of the conventional 
phase synchronization systems and which is free from the hang-up 
phenomenon and permits very rapid synchronization of a plurality of a 
synchronous burst signals even if they greatly differ in frequency as in 
the case of the TDMA signal. 
The present invention has its feature in that instead of using c phase 
comparator which causes the hang-up phenomenon, the received signal is 
detected directly by two orthogonal reference carriers, the baseband 
signals thus obtained are digitally processed, and the frequency and phase 
differences between the received signal and each of the reference carriers 
are estimated by use of an optimization method, for performing the phase 
synchronization. 
To enable high-speed, high-stability synchronization, the loop includes a 
memory, by which it is determined whether the circuit is in the pull-in 
operation or steady-state operation. This permits high-speed phase 
synchronization in the pull-in operation and high-stability phase 
synchronization with a small phase jitter in the steady-state operation. 
According to the present invention, no hang-up phenomenon will occur and a 
rapid and highly stable pull-in can be achieved even for TDMA signals with 
large frequency deviations. Furthermore, since the present invention is 
implemented by digital processing, the characteristic of its circuit can 
easily be changed unlike in the case of an analog circuit, and accordingly 
an optimum precision for phase synchronization can easily be set in view 
of the condition of the transmission line.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
With reference to the accompanying drawings embodiments of the present 
invention will hereinafter be described in detail. 
FIG. 2 illustrates a first embodiment of the present invention, which is a 
feedback type circuit. Reference numeral 1 indicates an input signal 
terminal, 2 and 3 multipliers, 4 and 5 low-pass filters (EPFs), 6 and 7 
analog-to-digital converters (A/Ds), 8 a digital calculator, 9 a .pi./2 
phase shifter, 10 a variable phase shifter, 11 a VCO (a Voltage-Controlled 
Oscillator), and 12 a recovered carrier output terminal. Now let it be 
assumed that when an input signal to the input terminal 1 has been 
modulated, it is input after having its modulated component removed. 
Provided that the received signal S(t) is an undemodulated signal, then it 
is expressed, in general, by the following expression: 
##EQU1## 
In expression (1), A represents the amplitude level of the received signal 
and .theta.(t) and n(t) represent a phase component and a noise component 
of the received signal, respectively, which are given by the following 
expressions: 
EQU .theta.(t)=.omega..sub.0 t+.DELTA..omega.t+.theta. (2) 
where .omega..sub.0 represents a reference angular frequency of the 
received signal, .DELTA..omega. an angular frequency deviation of the 
received signal from a reference carrier and .theta. the initial phase of 
the received signal. 
##EQU2## 
where n.sub.1 (t) and n.sub.2 (t) are Gaussian noise components which are 
orthogonal to each other and whose mean value is 0. The circuit depicted 
in FIG. 2 is intended to estimate, with high precision, the phase 
component .theta.(t) from the received signal S(t) and regenerate a signal 
synchronized therewith. 
Now, a description will be given first of the basic operation of this 
circuit and then of synchronization of asynchronous burst signals as of 
the TDMA signal. The received signal S(t) is applied to multipliers 2 and 
3, in which it is multiplied by signals 91 and 101 which are orthogonal to 
each other. The signals 101 and 91 are expressed by the following 
expressions: 
##EQU3## 
where .theta..sub.1 (t) is composed of the angular oscillation frequency 
.omega..sub.0 '[=.omega..sub.0 +.DELTA..omega..sub.0 ] and a phase 
deviation .theta..sub.0 which is controlled by the phase shifter 10, and 
is expressed by the following expression: 
EQU .theta..sub.1 (t)=.omega..sub.0 t+.DELTA..omega..sub.0 t+.theta..sub.0 (6) 
where .DELTA..omega..sub.0 and .theta..sub.0 are frequency and phase 
differences estimated by the digital processor 8. In the following 
description, let it be assumed that these two values start in the initial 
state, that is, they start with zero. 
Output signals 21 and 31 from the multipliers 2 and 3 are applied to the 
LPFs 4 and 5, in which high-frequency components are removed from them. 
Output signals 51 and 41 from the LPFs 5 and 4 are such as expressed by 
the following expressions: 
EQU y.sub.1 (t)=.eta.(t) cos .xi.(t) (7) 
EQU y.sub.2 (t)=.eta.(t) sin .xi.(t) (8) 
where: 
##EQU4## 
The signals expressed by expressions (7) and (8) are sampled with a timing 
period T and are converted by the A/D converters 6 and 7 into digital 
form. Output signals 71 and 61 from the A/D converters 7 and 6 in i-th 
sampling are expressed by the following expressions: 
EQU X.sub.i =.eta..sub.i cos .xi..sub.i (12) 
EQU Y.sub.i =.eta..sub.i sin .xi..sub.i (13) 
where: 
##EQU5## 
The digital processor 8 estimates the phase component .theta.(t) of the 
received signal by performing the following calculations using X.sub.i and 
Y.sub.i. 
At first, calculations of expressions (14) and (15) are performed using 
X.sub.i and Y.sub.i at each input sample point, thereby obtaining 
.eta..sub.i and .xi..sub.i. 
##EQU6## 
.xi..sub.i expressed by expression (15) can be obtained only as the 
principal value in the range -.pi..ltoreq..xi..sub.i .ltoreq..pi.. 
Accordingly, a net amount of angular rotation A.sub.i at each sample point 
is obtained by the following operation: 
##EQU7## 
In this case, the relationship given by the following expression holds 
between A.sub.i and .xi..sub.i. 
EQU A.sub.i (mod2.pi.)=.xi..sub.i (17) 
By using the relationship of expression (17), expressions (12) and (13) 
become as follows: 
EQU X.sub.i =.eta..sub.i cos A.sub.i (18) 
EQU Y.sub.i =.eta..sub.i sin A.sub.i (19) 
Next, a description will be given of a method for estimating the angular 
frequency deviation .DELTA..omega. and the phase component .theta. of the 
received signal by using expressions (18) and (19). For the sake if 
convenience, .DELTA..omega..sub.1 and .theta..sub.1 are set for 
.DELTA..omega. and .theta. to be estimated. Using .DELTA..omega..sub.1 and 
.theta..sub.1, expressions (18) and (19) are transformed as follows: 
EQU X.sub.ei =.eta..sub.i cos (A.sub.i -.DELTA..omega..sub.1 t.sub.i 
-.theta..sub.1) (20) 
EQU Y.sub.ei =.eta..sub.i sin (A.sub.i -.DELTA..omega..sub.1 t.sub.i 
-.theta..sub.1) (21) 
Next, consider the following operation for N samples from t.sub.0 to 
t.sub.N-1. 
##EQU8## 
As will be evident from the relationships of expressions (22) and (23), 
when X.sub.eN assumes a maximum value or when Y.sub.eN assumes a minimum 
value, .DELTA..omega. and .theta. are most accurately estimated in terms 
of .DELTA..omega..sub.1 and .theta..sub.1. 
Accordingly, the estimation of .DELTA..omega. and .theta. comes does to a 
problem of obtaining .DELTA..omega..sub.1 and .theta..sub.1 when X.sub.eN 
becomes maximum (or when Y.sub.eN becomes minimum). 
.DELTA..omega..sub.1 and .theta..sub.1 for maximizing X.sub.eN can be 
obtained as follows, using a calculus of variations which is one iof 
optimization methods. 
At first, expression (22) is partially differentiated as functions of 
.DELTA..omega..sub.1 and .theta..sub.1. 
##EQU9## 
In this case, .DELTA..omega..sub.1 and .theta..sub.1 for maximizing 
X.sub.eN are solutions when expressions (24) and (25) become zero. 
On the other hand, if .DELTA..omega..perspectiveto..DELTA..omega..sub.1 and 
.theta..perspectiveto..theta..sub.1, then the relationship of the 
following expression will hold: 
EQU sin (A.sub.k -.DELTA..omega..sub.1 t.sub.k 
-.theta..sub.1).perspectiveto.A.sub.k -.DELTA..omega..sub.1 t.sub.k 
-.theta..sub.1 (26) 
By solving the simultaneous equations (24) and (25) through use of the 
relationship of Eq. (26), .DELTA..omega..sub.1 and .theta..sub.1 can be 
obtained as follows: 
##EQU10## 
In Eqs. (27) and (28), t.sub.k is the time for the sake of convenience, as 
indicated in Eqs. (20) and (21). Accordingly, consider that t.sub.k =kT. 
Substituting the above-mentioned relations into Eqs. (27) and (28), 
.DELTA..omega..sub.1 and .theta..sub.1 are obtained as follows: 
##EQU11## 
The calculations corresponding to Eqs. (29) and (30) are performed by the 
digital processor 8 shown in FIG. 2. FIG. 3 shows an example of the 
arrangement of the digital processor 8. 
In FIG. 3 the output signals X.sub.i and Y.sub.i for each sample point are 
provided to the terminals 71 and 61. Reference numeral 13 indicates a 
phase calculator, 14 a calculator for calculating a net amount of angular 
rotation, 15 a calculator for calculating the amplitude level of the 
received signal, 16 multipliers, 17 adders, 18 an estimator for 
.DELTA..omega. and .theta., 20 a data sample number counter, and 81 and 82 
output terminals at which .theta. and .DELTA..omega. estimated by the 
estimator 18 are provided. 
In the digital processor 8 depicted in FIG. 3 the phase calculator 13, the 
angular rotation amount calculator 14, the amplitude level calculator 15, 
the multipliers 16 and the adders 17 perform calculations corresponding to 
elements in Eqs. (15), (16), (14), (29) and (30), respectively, and the 
estimator 18 calculates .DELTA..omega. and .theta. corresponding to Eqs. 
(29) and (30) through use of the values of the respective elements derived 
at the output of the adders 17. In this case, .DELTA..omega. and .theta. 
obtained at the output terminals 82 and 81 are used to control the VCO 11 
and the phase shifter 10 in FIG. 2. 
Since the frequency of the VCO 11 is controlled by a voltage value, 
however, let it be assumed that the output .DELTA..omega. from the digital 
processor 8 is converted into a voltage value for yielding a frequency 
having shifted by .DELTA..omega. from the reference carrier .omega..sub.0 
of the VCO 11, which voltage value is provided via the output terminal 82 
to the VCO 11. The phase shifter 11 can be implemented by, for example, a 
delay line circuit corresponding to a phase difference, and the delay of a 
delay line, which forms the variable phase shifter 10, is varied in 
accordance with the output .theta. from the digital processor 8 to the 
output terminal 81. 
By these operations a signal synchronized in phase with the received signal 
1 is provided at the terminal 12. 
The above has described the feedback type phase synchronization circuit. 
Next, a description will be given of a second embodiment of the present 
invention. FIG. 4 illustrates an embodiment of a feedforward type circuit. 
The first embodiment is the feedback type phase synchronization circuit in 
which the frequency difference 82 and the phase difference 81 estimated by 
the digital processor 8 are fed back to the VCO 11 and the phase shifter 
10, respectively, controlling the frequency and the phase of the reference 
signal itself to be synchronized in phase with the received signal. In 
contrast thereto, according to the feedforward type circuit shown in FIG. 
4, the output of a fixed oscillator 19 is used as a reference carrier, 
which has a fixed frequency value at all times. The digital processor 8 
performs the same processing as described previously with respect to first 
embodiment, and provides at its outputs 81 and 82 estimated values of the 
phase and frequency differences between the received signal and the output 
signal of the fixed oscillator, respectively. The variable phase shifter 
10 and the VCO 11 are controlled by the phase difference and the frequency 
difference obtained at the output terminals 81 and 82, respectively, and a 
recovered carrier is obtained at the output terminal 12. 
The operations described above constitute the basis of the present 
invention. Next, this phase synchronization circuit will be described as 
being applied to the case of a TDMA communication in which a plurality of 
asynchronous signals are received in the form of bursts, or the case where 
the received signal varies with time according to the condition of the 
transmission line. 
FIG. 5 shows, by way of example, temporal variations of the angular 
frequency deviation (.DELTA..omega..sub.i) estimated by the digital 
processor 8. The operation of the phase synchronization circuit of the 
present invention shown in FIG. 2 will be described with reference to FIG. 
5. 
The frequency difference .DELTA..omega..sub.1 and the phase difference 
.theta..sub.1 are estimated using N samples from the time t.sub.0 to 
t.sub.N-1. In this instance, the difference E.sub.1 between the estimated 
frequency difference .DELTA..omega..sub.1 and the VCO output frequency 
.DELTA..omega..sub.0 from the time t.sub.0 to t.sub.N-1 is obtained, and 
the difference E.sub.1 is compared with a predetermined threshold value 
E.sub.s. For example, when the difference E.sub.1 is greater than the 
threshold value E.sub.s, it is determined that the variation of the 
received signal is large (corresponding to the pull-in in the case of the 
TDMA signal), and after the time t.sub.N the oscillation frequency of the 
VCO 11 is set to (.omega..sub.0 +.DELTA..omega..sub.1) and the phase of 
the phase shifter 10 is set to .theta..sub.1, as shown in Eq. (2). 
Next, .DELTA..omega..sub.2 and .theta..sub.2 are similarly estimated for N 
samples from the time t.sub.N to t.sub.N-1, and the difference E.sub.2 
between .DELTA..omega..sub.1 and .DELTA..omega..sub.2 is obtained and is 
then compared with the threshold value E.sub.s. 
FIG. 5 shows the case where the difference E.sub.2 is also greater than the 
threshold value E.sub.s and the oscillation frequency of the VCO 11 is 
switched to (.omega..sub.0 +.DELTA..omega..sub.2) at a time t.sub.2N. FIG. 
5 further shows a case where the difference E.sub.3 between 
.DELTA..omega..sub.2 and .DELTA..omega..sub.3 estimated using N samples 
from the time t.sub.2N to t.sub.3N-1 is smaller than the threshold value 
E.sub.s. In this case, it can be judged that the received signal is stable 
(in the steady state in the case of the TDMA signal). 
In this instance, the oscillation frequency of the VCO 11 after a time 
t.sub.3N is held at (.omega..sub.0 +.DELTA..omega..sub.2), N samples are 
taken in after the time t.sub.3N and then 2N samples after the time 
t.sub.2N are used to estimate the angular frequency deviation 
.DELTA..omega. and the initial phase .theta.. Such an increase in the 
number of samples for use in the estimation of the angular frequency 
deviation .DELTA..omega. and the initial phase .theta. corresponds to the 
narrowing of the loop band in the PLL system and permits a phase 
synchronization with a small phase jitter. 
In this case, however, to detect an abrupt change of the received signal in 
the period during which the 2N samples are taken in, .DELTA..omega..sub.31 
and .theta..sub.31 are also estimated using N samples from a time 
t.sub.2N+1 to t.sub.3N as shown in FIG. 5. Similarly, 
.DELTA..omega..sub.32 and .DELTA..omega..sub.33 are sequentially estimated 
using data of N continuous samples as in the periods of time from 
t.sub.2N+2 to t.sub.3N+1 and from t.sub.2N+3 to t.sub.3N+2, in parallel to 
the above-mentioned estimating operation using 2N samples. 
In this case, the differences E.sub.31, E.sub.32, . . . between 
.DELTA..omega..sub.2 and .DELTA..omega..sub.31, .DELTA..omega..sub.32, . . 
. sequentially estimated using the N continuous samples are obtained and 
they are each compared with the threshold value E.sub.s. FIG. 5 shows a 
case where the differences E.sub.31, E.sub.32, . . . , E.sub.3,.sub.N-1 
which are obtained in the time interval of N samples from the time 
t.sub.3N to t.sub.4N-1 are all smaller than the threshold value E.sub.s. 
At a time t.sub.4N, .DELTA..omega..sub.4 and .theta..sub.4 estimated using 
2N samples from the time t.sub.2N to t.sub.4N-1 are used to control the 
VCO 11 and the phase shifter 10. 
If the system is stable after the time t.sub.4N, then the phase 
synchronization takes place every 2N samples through the above-described 
operations. 
For example, an abrupt change of the received signal in case of controlling 
every 2N samples (corresponding to a change of the burst signal in the 
case of the TDMA signal) can be detected because the difference E.sub.42 
between .DELTA..omega..sub.42 estimated using N samples and 
.DELTA..omega..sub.4 becomes greater than the threshold value E.sub.s at 
the time t.sub.4N-2, as shown in the example of FIG. 5. In this instance, 
the VCO 11 and the phase shifter 10 are controlled by 
.DELTA..omega..sub.42 and .theta..sub.42 estimated using N samples from 
the time t.sub.3N+1 to t.sub.4N+2, by which the phase synchronization can 
be achieved following the abrupt change of the received signal. 
As described above, according to the phase synchronization circuit of the 
present invention, it can be determined whether the circuit is in the 
pull-in or stead-state operation, and the pull-in operation can be 
achieved rapidly by decreasing the number of samples for use in the 
estimation of the angular frequency deviation .DELTA..omega. and the 
initial phase .theta., and during the stead-state operation the number of 
samples used is increased, thereby permitting a high quality phase 
synchronization. 
On the other hand, the unit sample number for use in the estimation of the 
angular frequency deviation .DELTA..omega. and the .theta. initial phase 
(N in the above-described embodiments), the unit sample number for use 
during the steady-state operation (2N in the afore-mentioned embodiments), 
and the threshold value E.sub.s of the frequency difference are determined 
in accordance with the state of the transmission line, the accuracy 
required of the phase synchronization circuit in view of the entire 
system, and so forth. These parameters can easily be changed because the 
estimation operation of the frequency difference and the phase difference 
is performed by digital processing. 
As described above in detail, according to the phase synchronization system 
of the present invention, the frequency deviation and the phase error 
between the received signal and the recovered carrier are estimated 
directly through utilization of the optimization method, and even if the 
frequency deviation and the phase error are large, they can be obtained 
accurately. Furthermore, the number of sample data for use in the 
estimation of the frequency deviation and the phase error by use of the 
optimization method can be selected at will in accordance with the state 
of the received signal (during the pull-in or steady state of the TDMA 
signal, for example). This provides, in the pull-in operation, rapid phase 
synchronization through use of a small number of data samples and, in the 
steady-state operation, high-quality phase synchronization through use of 
a larger number of data samples. The determination of the pull-in and the 
steady-state operations is made possible by storing the hysteresis of 
frequency deviations and phase errors estimated in the loop so far. 
Moreover, the parameters such as the number of data samples for the 
estimation can easily be changed from the outside in accordance with the 
state of the transmission line, and an optimum phase synchronization 
system can be provided.