Solder bump with inner core pillar in semiconductor package

An electrical interconnect within a semiconductor device consists of a substrate with a plurality of active devices. A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer, first barrier layer, adhesion layer, and seed layer are formed over the substrate. An inner core pillar including a hollow interior is centered over and formed within a footprint of the contact pad. A second barrier layer and a wetting layer are formed over the single cylindrical inner core pillar and hollow interior. A spherical bump is formed around the second barrier layer, wetting layer, and single cylindrical inner core pillar. A footprint of the spherical bump encompasses the footprint of the contact pad. The spherical bump is electrically connected to the contact pad.

FIELD OF THE INVENTION

The present invention relates in general to semiconductor packaging, and more particularly, to solder bump structures in flip chip packaging of semiconductor devices.

BACKGROUND OF THE INVENTION

Semiconductor devices are found in many products used in modern society. Semiconductors find applications in consumer items such as entertainment, communications, networks, computers, and household items markets. In the industrial or commercial market, semiconductors are found in military, aviation, automotive, industrial controllers, and office equipment.

The manufacture of semiconductor devices involves formation of a wafer having a plurality of die. Each die contains hundreds or thousands of transistors and other active and passive devices performing a variety of electrical functions. For a given wafer, each die from the wafer typically performs the same electrical function. Front-end manufacturing generally refers to formation of the semiconductor devices on the wafer. The finished wafer has an active side containing the transistors and other active and passive components. Back-end manufacturing refers to cutting or singulating the finished wafer into the individual die and then packaging the die for structural support and/or environmental isolation.

One goal of semiconductor manufacturing is to produce a package suitable for faster, reliable, smaller, and higher-density integrated circuits (IC) at lower cost. Flip chip packages or wafer level packages (WLP) are ideally suited for ICs demanding high speed, high density, and greater pin counts. Flip chip style packaging involves mounting the active side of the die facedown toward a chip carrier substrate or printed circuit board (PCB). The electrical and mechanical interconnect between the active devices on the die and conduction tracks on the carrier substrate is achieved through a solder bump structure comprising a large number of conductive solder bumps or balls. The solder bumps are formed by a reflow process applied to contact pads disposed on the semiconductor substrate. The solder bumps are then soldered to the carrier substrate. The flip chip semiconductor package provides a short electrical conduction path from the active devices on the die to the carrier substrate in order to reduce signal propagation, lower capacitance, and achieve overall better circuit performance.

The reliability and integrity of the solder bump is important to testing, manufacturing yield, and longevity of the product while in service. Device reliability is a function of the interconnect material and structural integrity of each solder bump and its effectiveness as an electrical interconnect. Many prior art devices have attempted to modify the basic structure of the solder bump, including encapsulating a first bump within a second bump, as described in U.S. Pat. No. 6,077,765 and US patent application 20040266066. However, these prior art solder bump structures are known to exhibit weak solder joints, particularly with fine pitch applications. In addition, some prior art bump structures continue to have high joint resistance, which increases power consumption and heat dissipation.

A need exists for a solder bump structure with enhanced strength and reliability and lower joint resistance.

SUMMARY OF THE INVENTION

In one embodiment, the present invention is an electrical interconnect within a semiconductor package consisting of a substrate having a plurality of active devices formed thereon, a contact pad formed on the substrate in electrical contact with the plurality of active devices, a first insulation layer formed over the substrate, a second insulation layer formed over the first insulation layer, a first barrier layer formed over the contact pad and the first and second insulation layers, an adhesion layer formed over the first barrier layer, and a seed layer formed over the adhesion layer. The electrical interconnect further consists of a single cylindrical inner core pillar including a hollow interior centered over and formed within a footprint of the contact pad, a second barrier layer and a wetting layer formed over the single cylindrical inner core pillar and hollow interior, and a spherical bump formed around the second barrier layer, wetting layer, and single cylindrical inner core pillar. A footprint of the spherical bump encompasses the footprint of the contact pad, and the spherical bump is electrically connected to the contact pad.

In another embodiment, the present invention is an electrical interconnect within a semiconductor package consisting of a substrate having a plurality of active devices formed thereon, a contact pad formed on the substrate in electrical contact with the plurality of active devices, an insulation layer formed over the substrate, an under bump metallization (UBM) formed over the contact pad and the insulation layer, a cylindrical inner core pillar including a hollow interior centered over and formed within a footprint of the contact pad, a conductive layer formed over the cylindrical inner core pillar and hollow interior, and a spherical bump formed around the conductive layer, cylindrical inner core pillar, and electrically connected to the contact pad.

In another embodiment, the present invention is an electrical interconnect within a semiconductor package consisting essentially of a substrate having a plurality of active devices formed thereon, a contact pad formed on the substrate in electrical contact with the plurality of active devices, an insulation layer formed over the substrate, an UBM formed over the contact pad and the insulation layer, an inner core pillar formed within a footprint of the contact pad, a first barrier layer and a wetting layer formed over the inner core pillar, and a spherical bump formed around the first barrier layer, wetting layer, and inner core pillar. The spherical bump is electrically connected to the contact pad.

In another embodiment, the present invention is an electrical interconnect within a semiconductor package consisting essentially of a substrate having a plurality of active devices formed thereon, a contact pad formed over the substrate in electrical contact with the plurality of active devices, an insulation layer formed over the substrate, a UBM formed over the contact pad and the insulation layer, an inner core pillar formed within a footprint of the contact pad, a conductive layer formed over the inner core pillar, and a rounded bump formed around the conductive layer and inner core pillar. The rounded bump is electrically connected to the contact pad.

DETAILED DESCRIPTION OF THE DRAWINGS

The manufacture of semiconductor devices involves formation of a wafer having a plurality of die. Each die contains hundreds or thousands of transistors and other active and passive devices performing one or more electrical functions. For a given wafer, each die from the wafer typically performs the same electrical function. Front-end manufacturing generally refers to formation of the semiconductor devices on the wafer. The finished wafer has an active side containing the transistors and other active and passive components. Back-end manufacturing refers to cutting or singulating the finished wafer into the individual die and then packaging the die for structural support and/or environmental isolation.

A semiconductor wafer generally includes an active front side surface having semiconductor devices disposed thereon, and a backside surface formed with bulk semiconductor material, e.g., silicon. The active front side surface contains a plurality of semiconductor die. The active surface is formed by a variety of semiconductor processes, including layering, patterning, doping, and heat treatment. In the layering process, semiconductor materials are grown or deposited on the substrate by techniques involving thermal oxidation, nitridation, chemical vapor deposition, evaporation, and sputtering. Patterning involves use of photolithography to mask areas of the surface and etch away undesired material to form specific structures. The doping process injects concentrations of dopant material by thermal diffusion or ion implantation. The active surface is substantially planar and uniform with electrical interconnects, such as bond pads.

Flip chip semiconductor packages and wafer level packages (WLP) are commonly used with integrated circuits (ICs) demanding high speed, high density, and greater pin counts. Flip chip style packaging10involves mounting an active area12of die14facedown toward a chip carrier substrate or printed circuit board (PCB)16, as shown inFIG. 1. Active area12contains active and passive devices, conductive layers, and dielectric layers according to the electrical design of the die. The electrical and mechanical interconnect is achieved through a solder bump structure20comprising a large number of individual conductive solder bumps or balls22. The solder bumps are formed on bump pads24, which are disposed on active area12. In the present example, bump pads24have a fine pitch, e.g., on the order of 150 micrometers (μm). The bump pads24connect to the active circuits by conduction tracks in active area12. The solder bumps22are electrically and mechanically connected to contact pads26on carrier substrate16by a solder reflow process. The flip chip semiconductor package provides a short electrical conduction path from the active devices on die14to conduction tracks on carrier substrate16in order to reduce signal propagation, lower capacitance, and achieve overall better circuit performance.

FIGS. 2a-2dillustrate cross-sectional views of the formation of a support structure for a solder bump. Note that forFIGS. 2-4the wafer is oriented with its active surface facing up. InFIG. 2a, metal contact pad32is formed on silicon substrate34. Contact pad32is made of aluminum (Al), copper (Cu), or aluminum/copper alloys. Contact pad32is electrically connected to active and passive devices through conduction tracks or layers formed on substrate34. A solder bump will later be formed to connect to the metal contact pad. A first passivation layer36is formed over substrate34with an opening to expose metal contact pad32. The opening is realized by removing a portion of passivation layer36through a photoresist mask defined etching process. The first passivation layer36can be made with silicon nitride (SiN), silicon dioxide (SiO2), silicon oxynitride (SiON), polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), or other insulating material. A second passivation layer38is formed over passivation layer36. Passivation layer38can be made using similar material as described for passivation layer36. Again, an opening is formed by removing a portion of passivation layer38to expose metal contact pad32. In another embodiment, passivation layers36-38are formed by repassivation. The UBM uses adhesion layer40, optional barrier layer42, and seed layer44. An adhesion layer40is formed over passivation layer38for bonding to barrier layer42. Adhesion layer40can be titanium (Ti), Al, titanium tungsten (TiW), and chromium (Cr). Barrier layer42inhibits the diffusion of Cu into the active area of the die. Barrier layer42can be made of nickel (Ni), Ni-alloy, platinum (Pt), palladium (Pd), TiW, and chromium copper (CrCu). Seed layer44is formed over barrier layer42. Seed layer44can be made with Cu, Ni, nickel vanadium (NiV), Cu, gold (Au), or Al. Seed layer44follows the contour of passivation layers36-38and contact pad32and acts as an intermediate conductive layer formed between metal contact pad32and the solder bump. Seed layer44electrically connects to contact pad32.

InFIG. 2b, a photoresist layer50is coated, exposed, developed, and etched to form a first opening or column having a width, which is less than that of contact pad32. The first opening is located about central to contact pad32. An inner core pillar52is deposited in the first opening between photoresist layers50by an electroless plating or electrolytic plating process. Core pillar52is made of Cu, Ni, Al, or other suitable metal. By way of example, inner core pillar52can have a rectangular or cylindrical form factor, although other shapes are contemplated as well. The height of inner core pillar52is about two-thirds the thickness of photoresist layer50or, in one embodiment, about 50 μm in height and 50 μm in diameter.

InFIG. 2c, photoresist layer50is exposed, developed, and etched again, without completely stripping the layer away, to form a second opening or column over the first opening. The second opening has a width, which is greater than the width of contact pad32. The distance from the edge of the second opening in photoresist layer50to core pillar52is less than the thickness of photoresist layer50. Barrier layer54is formed over seed layer44and core pillar52for metal (Cu) diffusion isolation. Barrier layer54is made of Ni, Pt, or other suitable metal. Wetting layer56is formed over barrier layer54. Wetting layer56is made of Cu, Au, or Ag. In an alternate embodiment, the sequence can be switched, i.e., barrier layer54can be formed over wetting layer56.

Solder layer58is formed by depositing electrically conductive material through an electrolytic plating or electroless plating process over wetting layer56. The solder material can be any metal, e.g., tin (Sn), lead (Pb), Ni, Au, silver (Ag), Cu, bismuthinite (Bi) and alloys thereof, or mixtures of other conductive materials. In one embodiment, the solder material is 63 percent weight of Sn and 37 percent weight of Pb. The barrier layer and wetting layer between solder layer58and seed layer44enhance reliability of the bump support structure.

InFIG. 2d, any remaining portion of photoresist layer50is stripped away. An etching process removes any portion of seed layer44, barrier layer42, and adhesion layer40outside the region of the solder bump structure, for example in applications where the UBM layers extend continuously between adjacent solder bumps. Solder layer58is reflowed by heating the conductive material above its melting point to form a spherical ball or bump60over semiconductor substrate34. In one embodiment, solder bump60is about 75 μm in height and 80 μm in diameter. Solder bump60electrically contacts core pillar52, seed layer44, and metal contact pad32.

As a feature of the present invention, the solder bump is formed around barrier layer54, wetting layer56, and inner core pillar52by plating solder material and then reflowing the solder material to form the solder bump. In one embodiment, the inner core pillar52extends into the solder bump at least two-thirds a height of the solder bump. The core pillar height is typically less than the pitch between adjacent solder bumps in bump structure20. The core pillar width is typically about 40% to 60% of the bump diameter. The distance from the solder bottom edge to the core pillar edge is about 20% to 30% of the bump diameter. These features reduce solder joint resistance and improve strength and reliability for the bump support structure.

An alternate embodiment of the flip chip package is shown inFIG. 3a. As described above, metal contact pad32is formed on substrate34. Contact pad32is electrically connected to active and passive devices through conduction layers formed on substrate34. Passivation layer(s)36is formed over substrate34with an opening to expose metal contact pad32. An adhesion layer40is formed over passivation layer36for bonding to barrier layer42. Barrier layer42inhibits the diffusion of Cu into the active area of the die. Seed layer44is formed over barrier layer42. Seed layer44is an intermediate conductive layer formed between metal contact pad32and the solder bump. Seed layer44electrically connects to contact pad32.

Photoresist layer50is first coated, exposed, developed, and etched to form a first opening or column, as described inFIG. 2b, having a width which is less than that of contact pad32. The first opening is located about central to contact pad32. An inner core pillar52is deposited in the first opening between photoresist layers50by an electroless plating or electrolytic plating process. The height of inner core pillar52is about two-thirds the thickness of photoresist layer50. Photoresist layer50is again exposed, developed, and etched, without completely stripping the layer away, to form a second opening or column over the first opening. The second opening has a width, which is greater than the width of contact pad32, as shown inFIG. 3a. The distance from the edge of the second opening in photoresist layer50to core pillar52is less than the thickness of photoresist layer50. Barrier layer54is formed over seed layer44and core pillar52for metal (Cu) diffusion isolation. Wetting layer56is formed over barrier layer54.

A solder layer is formed by depositing electrically conductive material through a screen printing process over wetting layer56. The solder material can be any metal, e.g., Sn, Pb, Ni, Au, Ag, Cu, Bi, and alloys thereof, or mixtures of other conductive materials. In one embodiment, the solder material is 63 percent weight of Sn and 37 percent weight of Pb. After plating, the solder layer is reflowed to form ball or bump64between photoresist layers50.

InFIG. 3b, any remaining portion of photoresist layer50is stripped away. An etching process removes any portion of seed layer44, barrier layer42, and adhesion layer40outside the region of the solder bump structure. Solder bump64is reflowed a second time by heating the conductive material above its melting point to form a spherical ball or bump66disposed over semiconductor substrate34. Solder bump66electrically contacts core pillar52, seed layer44, and metal contact pad32.

The process of forming the solder bump around inner core pillar52by plating solder material and then reflowing the solder material twice to form the solder bump reduces solder joint resistance and improves strength and reliability for the bump support structure. The inner core pillar52extends into the solder bump at least two-thirds a height of the solder bump. In addition, barrier layer54and wetting layer56formed over the inner core pillar also enhance strength and reliability for the bump support structure.

Another embodiment of the flip chip package is shown inFIG. 4a. As described above, metal contact pad32is formed on substrate34. Contact pad32is electrically connected to active and passive devices through conduction layers formed on substrate34. Passivation layer(s)36is formed over substrate34with an opening to expose metal contact pad32. An adhesion layer40is formed over passivation layer36for bonding barrier layer42. Barrier layer42inhibits the diffusion of Cu into the active area of the die. Seed layer44is formed over barrier layer42. Seed layer44is an intermediate conductive layer formed between metal contact pad32and the solder bump. Seed layer44electrically connects to contact pad32.

A photoresist layer is first coated, exposed, developed, and etched to form a first opening or column having a width, which is less than that of contact pad32. The first opening in the photoresist layer has the form of a cylinder with its interior containing photoresist material. An inner core pillar70is deposited in the first opening between the photoresist layers by electroless plating or electrolytic plating. Due to the form of the first opening, inner core pillar70has a cylindrical shape with a hollow interior, as seen inFIG. 4bwhich is a top view of bump76and supporting structure at line4b-4b. In another embodiment, the inner core pillar can be toroidal in shape. The height of inner core pillar70is about two-thirds the thickness of the photoresist layer. The photoresist layer is again exposed, developed, and etched, without completely stripping the layer away, to form a second opening or column over the first opening. The second opening has a width, which is greater than the width of contact pad32. The distance from the edge of the second opening in the photoresist layer to core pillar70is less than the thickness of the photoresist layer. Barrier layer72is formed over seed layer44and core pillar70for metal (Cu) diffusion isolation. Wetting layer74is formed over barrier layer72.

A solder layer is formed by depositing electrically conductive material by electroless plating, electrolytic plating, or screen printing over wetting layer72. The solder material can be any metal, e.g., Sn, Pb, Ni, Au, Ag, Cu, Bi, and alloys thereof, or mixtures of other conductive materials. In one embodiment, the solder material is 63 percent weight of Sn and 37 percent weight of Pb.

Any remaining portion of the photoresist layer is stripped away. An etching process removes any portion of seed layer44, barrier layer42, and adhesion layer40outside the region of the solder bump structure. Solder bump64is reflowed by heating the conductive material above its melting point to form a spherical ball or bump76disposed over semiconductor substrate34. Solder bump76electrically contacts core pillar70, seed layer44, and metal contact pad32.

In summary, the process of forming the solder bump around an inner core pillar by plating solder material and then reflowing the solder material once or multiple times to form the solder bump reduce solder joint resistance and improves strength and reliability for the bump support structure. The inner core pillar extends into the solder bump at least two-thirds a height of the solder bump. In addition, the barrier layer and wetting layer formed over the inner core pillar also enhance strength and reliability for the bump support structure.