Array substrate, manufacturing method thereof, display panel, and electronic device

An array substrate, a manufacturing method thereof, a display panel and an electronic device are disclosed. The array substrate includes: a base substrate, a first electrode and a second electrode. The first electrode is disposed on the base substrate; the second electrode is disposed on the first electrode and is at least partly opposite to the first electrode in a direction perpendicular to the base substrate; the first electrode and the second electrode are electrically insulated from each other; a capacitor structure is constituted by a region of the first electrode and a region of the second electrode which are opposite to each other; and the capacitor structure includes a portion which forms at least part of a first recess.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority to Chinese patent application No. 201810240944.4 filed on Mar. 22, 2018 under the title of “ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, DISPLAY PANEL AND ELECTRONIC DEVICE”, the entire disclosure of the above-mentioned Chinese patent application is incorporated herein by reference as part of embodiments of the present disclosure.

TECHNICAL FIELD

Embodiments of the present disclosure relate to an array substrate, a manufacturing method thereof, a display panel and an electronic device.

BACKGROUND

Liquid crystal display panel, organic light-emitting diode display panel and the like have been widely applied in various display devices for characteristics of thinner and lighter design, good shock-resistant property, wide viewing angle, high contrast ratio and the like. For example, a display panel usually includes a plurality of sub-pixels arranged in an array, and each of the sub-pixels, for example, includes structures such as thin film transistor (TFT) and capacitor. For example, with the development of display technologies and customers' demands on display quality of the display panel, a resolution ratio of the display panel is continually improved. Correspondingly, an area occupied by each of the sub-pixels is increasingly smaller, which results in higher requirements in terms of a design of capacitor structure and the like in the display panel.

SUMMARY

At least one embodiment of the present disclosure provides an array substrate, including:

a base substrate;

a first electrode on the base substrate; and

a second electrode at a side of the first electrode facing away from the base substrate, the second electrode being at least partly opposite to the first electrode in a direction perpendicular to the base substrate, wherein

the first electrode and the second electrode are electrically insulated from each other, and a capacitor structure is constituted by a region of the first electrode and a region of the second electrode which are opposite to each other; the capacitor structure includes a portion forming at least part of a first recess.

In one or more embodiments of the present disclosure, the capacitor structure includes a portion forming a plurality of first recesses.

In one or more embodiments of the present disclosure, the array substrate further includes an insulating layer; the insulating layer is located between the base substrate and the first electrode and includes a second recess formed in the insulating layer; the capacitor structure is at least located on a side wall of the second recess.

In one or more embodiments of the present disclosure, the portion of the capacitor structure forming at least part of the first recess is at least partly overlapped with the second recess in the insulating layer, in the direction perpendicular to the base substrate.

In one or more embodiments of the present disclosure, the insulating layer has a stacked structure and includes at least two insulating sub-layers which are stacked sequentially from the base substrate; the second recess penetrates at least one insulating sub-layer at a side of the insulating layer far away from the base substrate.

In one or more embodiments of the present disclosure, at least part of an insulating sub-layer at a side of the insulating layer closest to the base substrate is not penetrated by the second recess.

In one or more embodiments of the present disclosure, the insulating layer includes a plurality of second recesses, the capacitor structure includes a portion forming a plurality of first recesses, the plurality of first recesses and the plurality of second recesses are in one-to-one correspondence, and each of the plurality of first recesses is located inside one of the plurality of second recesses.

In one or more embodiments of the present disclosure, the capacitor structure further includes a dielectric layer located between the first electrode and the second electrode, so that the first electrode and the second electrode are electrically insulated from each other.

In one or more embodiments of the present disclosure, the array substrate further includes a thin film transistor (TFT), the TFT includes an active layer, a gate electrode and a source-drain electrode; the first electrode is located in a same layer with any one of the active layer, the gate electrode and the source-drain electrode; and the second electrode is located in a same layer with one of the other two of the active layer, the gate electrode and the source-drain electrode.

In one or more embodiments of the present disclosure, the array substrate further includes a TFT and a light-emitting element; the TFT includes a drain electrode, the light-emitting element includes a pixel electrode, and the pixel electrode is electrically connected with the drain electrode.

At least one embodiment of the present disclosure further provides a display panel including any array substrate described above.

At least one embodiment of the present disclosure further provides an electronic device including any array substrate described above.

At least one embodiment of the present disclosure further provides a manufacturing method of an array substrate, including:

providing a base substrate;

forming a first electrode on the base substrate;

forming a second electrode on the first electrode, the second electrode being at least partly opposite to the first electrode in a direction perpendicular to the base substrate, wherein

the first electrode and the second electrode are electrically insulated from each other, and a capacitor structure is constituted by a region of the first electrode and a region of the second electrode which are opposite to each other; the capacitor structure includes a portion forming at least part of a first recess.

In one or more embodiments of the present disclosure, the capacitor structure includes a portion forming a plurality of first recesses.

In one or more embodiments of the present disclosure, the manufacturing method further includes:

before forming the first electrode, forming an insulating layer film on the base substrate and etching the insulating layer film to form an insulating layer including a second recess, wherein

the portion of the capacitor structure forming at least part of the first recess is at least partly overlapped with the second recess in the direction perpendicular to the base substrate.

In one or more embodiments of the present disclosure, the capacitor structure is at least formed on a side wall of the second recess.

In one or more embodiments of the present disclosure, the manufacturing method further includes:

forming a gate electrode of a thin film transistor (TFT) in a first patterning process of forming the first electrode; and

forming a source electrode and a drain electrode of the TFT in a second patterning process of forming the second electrode.

At least one embodiment of the present disclosure further provides an array substrate, including:

a base substrate;

an insulating layer located on the base substrate, the insulating layer including a recess, the recess penetrating at least part of the insulating layer from a side of the insulating layer facing away from the base substrate; and

a capacitor structure at least located on a side wall of the recess, the capacitor structure including a first electrode, a second electrode and a dielectric layer located between the first electrode and the second electrode.

In one or more embodiments of the present disclosure, the capacitor structure is also located on a bottom wall of the recess.

At least one embodiment of the present disclosure further provides a manufacturing method of an array substrate, including:

forming an insulating layer on a base substrate;

forming a recess in the insulating layer, the recess penetrating at least part of the insulating layer from a side of the insulating layer facing away from the base substrate; and

forming a capacitor structure at least on a side wall of the recess in a conformal manner, forming the capacitor structure including: forming a first electrode, forming a second electrode and forming a dielectric layer located between the first electrode and the second electrode.

DETAILED DESCRIPTION

In order to make objects, technical details and advantages of the embodiments of the present disclosure apparent, technical solutions according to the embodiments of the present disclosure will be described clearly and completely as below in conjunction with the accompanying drawings of embodiments of the present disclosure. Apparently, the described embodiments are only a part of but not all of exemplary embodiments of the present disclosure. Based on the described embodiments of the present disclosure, various other embodiments can be obtained by those of ordinary skill in the art without creative labor and those embodiments shall fall into the protection scope of the present disclosure.

Unless otherwise defined, the technical terminology or scientific terminology used herein should have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Likewise, terms like “first,” “second,” etc., which are used in the description and the claims of the present application for disclosure, are not intended to indicate any sequence, amount or importance, but distinguish various components. Also, the terms “comprise,” “comprising,” “include,” “including,” etc., are intended to specify that the elements or the objects stated before these terms encompass the elements or the objects and equivalents thereof listed after these terms, but do not preclude the other elements or objects. The phrases “connect”, “connected”, etc., are not intended to define a physical connection or mechanical connection, but may include an electrical connection, directly or indirectly. “On,” “under,” “left,” “right” or the like is only used to describe a relative positional relationship, and when the absolute position of a described object is changed, the relative positional relationship might also be changed accordingly.

With the development of display technologies and the demands on development of society, in order to improve a display quality of a display panel, the display panel has been continuously developed in terms of resolution ratio. The higher the resolution ratio of the display panel is, the smaller the area occupied by each of the sub-pixels in the display panel will be. Correspondingly, an area occupied by a capacitor structure in each of the sub-pixels is increasingly smaller, and a capacitance of the capacitor structure would also be reduced. As a result, ensuring the capacitance of the capacitor structure while improving the resolution ratio of the display panel has become one of research subjects in the field of display.

For example,FIG. 1is a schematic diagram illustrating a sectional structure of an array substrate10. As illustrated inFIG. 1, the array substrate10includes a thin film transistor (TFT)19, a capacitor structure14and other structures. For example, the TFT19includes an active layer15, a gate electrode16, a source electrode17, a drain electrode18and other structures. The capacitor structure14includes a first electrode11, a second electrode12, a dielectric layer13located between the first electrode11and the second electrode12, and other structures. As illustrated inFIG. 1, the first electrode11and the second electrode12of the capacitor structure14both are flat plate-shaped structures. When each of sub-pixels of the array substrate10occupies a relatively smaller area, an area occupied by the capacitor structure14in each of the sub-pixels is also small. Therefore, an area of regions of the first electrode11and the second electrode12opposite to each other is correspondingly small, which may result in that the capacitance of the capacitor structure14is too small to meet the demands of product design.

The capacitance may be expressed as C=K×(A/d), wherein C denotes a capacitance, K denotes a dielectric constant of the dielectric layer, A denotes an area of portions of the two electrodes in the capacitor structure opposite to each other, and d denotes a vertical distance between the two electrodes in the capacitor structure. For example, d usually is a thickness of the dielectric layer, or d is a size of the dielectric layer in a direction perpendicular to the first electrode and/or the second electrode. As it also can be seen from the formula, the capacitance is in direct proportion to the area of the portions of the two electrodes which are right opposite to each other.

In order to improve the resolution ratio of the display panel without reducing the capacitance of the capacitor structure, on one aspect, it can, for example, utilize a dielectric layer material having a great dielectric constant K. For example, the dielectric layer material having a great dielectric constant K includes ZrO2, HfO2or the like. But it usually needs to perform a thin film deposition with the dielectric layer material having a great dielectric constant K under high temperature condition or by using atomic layer deposition (ALD) method. However, the existing manufacturing method of low temperature polysilicon (LTPS) display panel or organic light-emitting diode (OLED) display panel and the like cannot satisfy the high temperature condition required by the deposition of a dielectric film having a great dielectric constant K, and cannot meet the requirements on practical production efficiency because of a poor deposition rate of the ALD method.

On the other aspect, for example, it can increase the capacitance C of the capacitor structure by reducing the thickness d of the dielectric layer. However, in a practical manufacturing process, the dielectric layer in the capacitor structure, for example, can also be used as a gate insulating layer of the TFT in the display panel at the same time, and the decrease of the thickness d of the dielectric layer may result in a driving issue brought by a tunnel effect due to a leakage current generated by the TFT, or may result in a poor image brought by a flicker issue, thereby affecting the display effect of the display panel.

At least one embodiment of the present disclosure provides an array substrate, including: a base substrate, a first electrode and a second electrode. The first electrode is disposed on the base substrate; the second electrode is disposed on the first electrode and is at least partly opposite to the first electrode in a direction perpendicular to the base substrate. The first electrode and the second electrode are electrically insulated from each other; and at least one of the first electrode and the second electrode has a portion forming at least part of a first recess in regions of the first electrode and the second electrode opposite to each other.

At least one embodiment of the present disclosure provides an array substrate, including: a base substrate, an insulating layer and a capacitor structure. The insulating layer is located on the base substrate and includes a recess. The recess penetrates at least part of the insulating layer from a side of the insulating layer facing away from the base substrate. The capacitor structure is at least located on a side wall of the recess; and the capacitor structure includes a first electrode, a second electrode and a dielectric layer located between the first electrode and the second electrode.

For example, in the embodiment of the present disclosure, the first recess is formed by a portion of the first electrode, a portion of the second electrode and/or a portion of the capacitor structure, and is formed by forming a bending portion in the first electrode, the second electrode and/or the capacitor structure. For example, in the embodiment of the present disclosure, at least one of the first electrode, the second electrode and the capacitor structure has substantially the same size everywhere, i.e., having uniform thickness.

In the array substrate provided by at least one embodiment of the present disclosure, by forming at least part of a first recess in a region of the first electrode and/or a region of the second electrode opposite to each other, it can increase a relative area of the first electrode and the second electrode in regions opposite to each other, so as to increase a capacitance of the capacitor structure constituted by the first electrode and the second electrode.

Hereinafter, the present disclosure will be described with reference to several concrete embodiments. In order to make the following description of the embodiments of the present disclosure simple and clear, well-known function(s) and component(s) may be omitted with detailed explanation thereof. When any component of the embodiments of the present disclosure is appeared in more than one figure, it may be denoted by using the same reference sign in each figure.

FIG. 2is a schematic diagram illustrating a sectional structure of an array substrate100provided by an embodiment of the present disclosure.FIG. 2emphasizes on illustrating the capacitor structure of the array substrate provided by the embodiment of the present disclosure. The capacitor structure illustrated inFIG. 2can be used to replace the capacitor structure illustrated inFIG. 1so as to increase the capacitance. For example, the array substrate100may be an array substrate of a display panel of any appropriate type, and the type of the display panel including the array substrate is not particularly limited in the present embodiment. As illustrated inFIG. 2, the array substrate100includes a base substrate101, a first electrode102, a second electrode103and other structures.

As illustrated inFIG. 2, the base substrate101, for example, may be a glass substrate, a quartz substrate, a plastic substrate or a substrate of other suitable materials, without particularly limited in the present embodiment. For example, the base substrate101may be a flexible substrate, and may also be a rigid substrate.

As illustrated inFIG. 2, the first electrode102is disposed on the base substrate101. The second electrode103is disposed on the first electrode102and is at least partly opposite to the first electrode102in a direction perpendicular to the base substrate101. The first electrode102and the second electrode103are electrically insulated from each other, and regions of the first electrode102and the second electrode103that are opposite to each other include a portion forming a first recess104. For example, the number of the first recess104formed by the first electrode102and/or the second electrode103may be one and may also be plural, without particularly limited in the present embodiment. Additionally, the first recess104formed by the first electrode102and/or the second electrode103for example may be in a shape of an integral recess, and can also be at least part of a recess. For example, at least one of the region of the first electrode102and the region of the second electrode103opposite to each other forms a side wall of the recess. The shape of the first recess104formed by the first electrode102and/or the second electrode103is not particularly limited in the present embodiment. The embodiment will be described with reference to the case where each of the first electrode102and the second electrode103includes one first recess104, by way of example.

For example, the first recess104is formed by forming a portion of the first electrode102into a bending structure. For example, the first recess104is formed by forming a portion of the second electrode103into a bending structure. For example, as illustrated inFIG. 2, a region of the first electrode102opposite to the second electrode103includes a portion1042forming a first recess104. For example, as illustrated inFIG. 2, a region of the second electrode103opposite to the first electrode102includes a portion1043forming a first recess104. For example, as illustrated inFIG. 2, the region of the first electrode102and the region of the second electrode103that are opposite to each other constitute a capacitor structure014, and the capacitor structure014includes a portion1040forming at least part of a first recess104. For example, an example of a material of the first electrode102and the second electrode103includes a metallic material, and the metallic material for example includes Ag, Al, Cr, Cu, Mo, Ti, Al—Nd alloy, Cu—Mo alloy, Mo—Ta alloy, Mo—Nd alloy or any combination thereof, without particularly limited in the present embodiment.

For example, as illustrated inFIG. 2, the array substrate100further includes an insulating layer105; the insulating layer105is disposed on the base substrate101and is located between the base substrate101and the first electrode102. The insulating layer105for example includes a second recess106formed therein. As illustrated inFIG. 2, the first recess104of the first electrode102is at least partly overlapped with the second recess106in the insulating layer105in the direction perpendicular to the base substrate101. As illustrated inFIG. 2, a bottom wall and a side wall of the second recess106each are formed with the first electrode102and the second electrode103in a conformal manner. In an example, when the first electrode102includes a portion forming a first recess104, the portion of the first electrode102forming the first recess104is at least partly overlapped with the second recess106in the insulating layer105in the direction perpendicular to the base substrate101. For example, the portion of the first electrode102or the second electrode103forming the first recess104is at least overlapped with the side wall of the second recess106in the insulating layer105in the direction perpendicular to the base substrate101.

For example, as illustrated inFIG. 2, the insulating layer105has a stacked structure, and includes a first insulating sub-layer1051, a second insulating sub-layer1052and a third insulating sub-layer1053which are stacked sequentially from the base substrate101. The second recess106in the insulating layer105penetrates at least one insulating sub-layer at a side of the insulating layer105far away from the base substrate101. For example, a recess may be formed in the third insulating sub-layer1053of the insulating layer105so as to constitute the second recess106; or, a recess may be formed in the third insulating sub-layer1053and the second insulating sub-layer1052of the insulating layer105so as to constitute the second recess106; or, a recess may be formed in the third insulating sub-layer1053, the second insulating sub-layer1052and the first insulating sub-layer1051of the insulating layer105so as to constitute the second recess106. The number of the insulating sub-layer in the insulating layer105penetrated by the second recess106is not particularly limited in the present embodiment. It should be noted that, the number of the insulating sub-layer included in the insulating layer105includes but is not limited to three. For example, depending on the demands of product design, the number of the insulating sub-layer included in the insulating layer105may be one, two, four or more, without particularly limited in the present embodiment. In the embodiment of the present disclosure, the second recess106may also penetrate a part of the insulating sub-layer. For example, in order to facilitate the manufacture of the array substrate and a stable performance, a portion of the insulating sub-layer at a side of the insulating layer105closest to the base substrate101is not penetrated by the second recess106. For example, a thickness of the portion of the insulating sub-layer at the side of the insulating layer105closest to the base substrate101being not etched is about ⅙-⅓ of a thickness of this insulating sub-layer. For example, the thickness of the insulating sub-layer at the side of the insulating layer105closest to the base substrate101is about 6000 Å, and the thickness of the portion of the insulating sub-layer at the side of the insulating layer105closest to the base substrate101being not etched is about 1000-2000 Å.

For example, as illustrated inFIG. 2, in the direction perpendicular to the base substrate101, a sectional area, a sectional shape and the like of a portion of the first electrode102forming the first recess104are correlated with a depth and the like of the second recess106. For example, if a depth of the second recess106in the insulating layer105is increased, a depth of the portion forming the first recess104in the first electrode102formed subsequent to the insulating layer105would also be increased, an area of the first electrode102in per unit area of the base substrate101in the direction perpendicular to the base substrate101would be correspondingly increased, and a relative area of the first electrode102and the second electrode103in regions opposite to each other in per unit area of the base substrate101would also be correspondingly increased. As a result, a capacitance of a capacitor structure constituted by the first electrode102and the second electrode103would be improved. Therefore, during the practical manufacturing process, for example, it may control a thickness of the first insulating sub-layer1051, the second insulating sub-layer1052and the third insulating sub-layer1053so as to control a depth of the second recess106, thereby adjusting a magnitude of capacitance of each of the sub-pixels in the array substrate100, correspondingly.

As illustrated inFIG. 2, the array substrate100further includes a dielectric layer107; the dielectric layer107is disposed between the first electrode102and the second electrode103so that the first electrode102and the second electrode103are electrically insulated from each other. The capacitor structure014includes the first electrode102, the second electrode103, and the dielectric layer107between the first electrode102and the second electrode103. The dielectric layer107includes a portion108forming a first recess; the portion of the second electrode103forming the first recess104is at least partly overlapped with the portion108of the dielectric layer107forming the first recess in the direction perpendicular to the base substrate101. In an example, when the second electrode103includes a portion forming the first recess104, the portion of the second electrode103forming the first recess104is at least partly overlapped with the portion108of the dielectric layer107forming the first recess in the direction perpendicular to the base substrate101. For example, a material used for the dielectric layer107includes silicon oxide, silicon nitride, silicon oxynitride or any other suitable materials such as a high dielectric coefficient material, without particularly limited in the present embodiment.

As illustrated inFIG. 2, in an example, the array substrate100further includes a buffering layer109, a barrier layer110, a second insulating layer111, an interlayered dielectric layer112, a planarization layer113and other structures.

As illustrated inFIG. 2, the buffering layer109is disposed on the base substrate101. The buffering layer109for example can prevent impurity ions and moistures or external air and the like from permeating the array substrate100through the base substrate101, and the buffering layer109can flatten a surface of the base substrate101. The buffering layer109for example can also prevent impurity ions in the array substrate101from diffusing into driving circuit layers formed later, such as the TFT, so as to avoid any influence to the performance of the TFT element such as threshold voltage and leakage current. An example of a material used for the buffering layer109includes SiNx, SiOx or any other suitable materials, without particularly limited in the present embodiment. For example, a thickness of the buffering layer109is about 6000 Å without limited thereto.

For example, the barrier layer110is disposed on the buffering layer109. The barrier layer110of the array substrate100for example can avoid an unexpected leakage current which may be caused by photo-induced carriers generated from an external light irradiation on an active layer formed later in the array substrate. An example of a material used for the barrier layer110includes a metallic material (e.g., Ag, Cr or the like), SiNx, SiOx or any other suitable materials, without particularly limited in the present embodiment.

For example, the second insulating layer111is disposed between the barrier layer110and the insulating layer105. An example of a material of the second insulating layer111includes polyimide or any other suitable materials, without particularly limited in the present embodiment. A distance between a bottom of the second recess106in the insulating layer105and the base substrate101is greater than or equal to a distance between an upper surface of the second insulating layer111and the base substrate101. That is, the second recess106in the insulating layer105would not penetrate the second insulating layer111, so as to avoid a short circuit to be occurred between the first electrode102and the barrier layer110. For example, the interlayered dielectric layer112is disposed on the second electrode103and covers the second electrode103so as to protect the second electrode103. For example, the planarization layer113is disposed on the interlayered dielectric layer112. An example of a material used for the interlayered dielectric layer112and the planarization layer113includes SiNx, SiOx or any other suitable materials, without particularly limited in the present embodiment.

It should be explained that, in order for clarity of illustration, the array substrate100is not illustrated in its entire structure. In order to achieve necessary function(s) of the array substrate, other structure(s) not illustrated may be arranged by those skilled in the art according to particular application scenarios, without particularly limited in the present embodiment.

In the array substrate100provided by at least one embodiment of the present disclosure, in the direction perpendicular to the base substrate101, opposite regions of the first electrode102and the second electrode103include a portion forming the first recess104. As compared to the array substrate constituted by a flat planar electrode, by designing the first electrode102and the second electrode103to include a portion constituting the first recess104, it can increase a relative area of the first electrode102and the second electrode103in regions opposite to each other, and hence improve a capacitance of a capacitor of the array substrate100constituted by the first electrode102and the second electrode103.

FIG. 3is a schematic diagram illustrating a sectional structure of an array substrate200provided by another embodiment of the present disclosure. As illustrated inFIG. 3, in the array substrate200, the number of the first recess104constituted by the first electrode102, the second electrode103and/or the capacitor structure is two. The structure of the array substrate200in this example can be substantially the same with that of the array substrate100described inFIG. 2, except the number of the first recess104in the first electrode102and the second electrode103. It should be explained that, the number of the first recess104in the first electrode102and the second electrode103of the array substrate200may be more than two, instead of being limited to two.

As illustrated inFIG. 3, the first electrode102, the second electrode103and the capacitor structure014of the array substrate200include two first recesses104in regions opposite to each other. For example, the two first recesses104are arranged to be closely adjacent to each other. The insulating layer105is disposed on the base substrate105, and is located between the base substrate101and the first electrode102. The insulating layer105includes two second recesses106formed therein; the two first recesses104constituted by the first electrode102is at least partly overlapped with the two second recesses106in the insulating layer105, respectively, in the direction perpendicular to the base substrate101. For example, the capacitor structure014is formed on the second recess106in a conformal manner. The dielectric layer107is disposed between the first electrode102and the second electrode103so that the first electrode102and the second electrode103are electrically insulated from each other. The dielectric layer107includes portions108forming two first recesses; and portions1043of the second electrode103forming two first recesses104are at least partly overlapped with the portions108of the dialectic layer107forming two first recesses, respectively, in the direction perpendicular to the base substrate101.

For example, when the design of the product satisfies that the array substrate200includes a plurality of first recesses104, e.g., two first recesses104, a relative area of the first electrode102and the second electrode103in regions opposite to each other in per unit area is further increased, so as to further improve the capacitance of the capacitor of the array substrate constituted by the first electrode102and the second electrode103.

FIG. 4is a schematic diagram illustrating a sectional structure of an array substrate300provided by another embodiment of the present disclosure. Referring toFIG. 4, the array substrate300in this example has a structure substantially the same with that of the array substrate100described inFIG. 2, except the shape of the second electrode103. The capacitor structure illustrated inFIG. 4is located on a side wall of the second recess106, and a bottom wall of the second recess106is not provided with the capacitor structure.

As illustrated inFIG. 4, the first electrode102of the array substrate300includes a portion forming a first recess104, the second electrode103of the array substrate300includes a portion forming a part of a first recess104, and the portion of the second electrode103forming the first recess is at least partly overlapped with the portion of the first electrode102forming the first recess104in the direction perpendicular to the base substrate101. The insulating layer105is disposed on the base substrate101and is located between the base substrate101and the first electrode102. The insulating layer105includes a second recess106formed therein, and the portion of the first electrode102forming the first recess104is at least partly overlapped with the second recess106in the insulating layer105in the direction perpendicular to the base substrate101. The dielectric layer107is disposed between the first electrode102and the second electrode103so that the first electrode102and the second electrode103are electrically insulated from each other. The dielectric layer107includes a portion108forming a first recess104, and a portion1043of the second electrode103forming the first recess104is at least partly overlapped with the portion108of the dielectric layer107forming the first recess104in the direction perpendicular to the base substrate101.

In another example, the first electrode102includes a portion forming a first recess104, the second electrode103includes a portion forming a first recess104, and the portion1043of the second electrode103forming the first recess104is at least partly overlapped with the portion1042of the first electrode102forming the first recess104in the direction perpendicular to the base substrate101. Or, it's also possible that each of the first electrode102and the second electrode103includes a portion forming a first recess104in regions of the first electrode102and the second electrode103opposite to each other. The shape of the portion of the first electrode102and/or the second electrode103forming the first recess104is not particularly limited in the present embodiment, as long as the shape of the recess can increase a relative area of the first electrode102and the second electrode103in regions opposite to each other in the direction perpendicular to the base substrate101.

Another embodiment of the present disclosure provides an array substrate400.FIG. 5is a schematic diagram illustrating a sectional structure of the array substrate400provided by the present embodiment. For example, the array substrate400may be used as an array substrate in various, suitable types of display panels.

As illustrated inFIG. 5, the present embodiment will be introduced with reference to the case where the array substrate400is an array substrate of an OLED display device, by way of example. The array substrate400includes a first electrode102, a second electrode103, a driving circuit structure405, a light-emitting element409and other structures. A capacitor structure014includes the first electrode102, the second electrode103and a dielectric layer107. The driving circuit structure405for example may be a transistor. The present embodiment will be introduced with reference to the case where the driving circuit structure405is a TFT (i.e., a driving transistor), by way of example. The TFT405for example may be a top-gate TFT or a bottom-gate TFT, and the type of the TFT405is not particularly limited in the present embodiment. The present embodiment will be introduced with reference to the case where the TFT405is a top-gate TFT, by way of example. As illustrated inFIG. 5, the TFT405includes an active layer401, a gate electrode402, a drain electrode403, a source electrode404and other structures. For example, the dielectric layer107may be used as a gate insulating layer of the TFT405at the same time.

For example, the active layer401may include amorphous silicon material, polycrystalline silicon material, metal oxide semiconductor material (e.g., Indium Gallium Zinc Oxide (IGZO)) or any other suitable materials, without particularly limited in the present embodiment. For example, when the array substrate400is a low temperature polysilicon (LTPS) TFT array substrate or a high temperature polysilicon (HTPS) TFT array substrate, an amorphous silicon active layer101can be crystallized into a polysilicon active layer101by using rapid thermal annealing (RTA) method, solid-phase crystallization (SPC) method, excimer laser annealing (ELA) method, metal induced crystallization (MIC) method, metal induced lateral crystallization (MILC) method, sequential lateral solidification (SLS) method or the like.

As illustrated inFIG. 5, the first electrode102is disposed in a same layer with the gate electrode402of the TFT405; during the manufacturing process, the first electrode102and the gate electrode402may be formed simultaneously by using the same patterning process. The second electrode103is disposed in the same layer with the source electrode404and the drain electrode403of the TFT405; during the manufacturing process, the second electrode103, the source electrode404and the drain electrode403may be formed simultaneously by using the same patterning process. Or, in another example, it's also possible that, the first electrode102is disposed in the same layer with the active layer401of the TFT405, and the second electrode103is disposed in the same layer with the gate electrode402or the drain electrode403/source electrode404of the TFT405. For example, when the TFT405is a bottom-gate TFT, the first electrode102may be disposed in the same layer with the gate electrode402of the TFT405, and the second electrode103may be disposed in the same layer with the active layer401or the drain electrode403/source electrode404of the TFT405.

In an example, the third insulating sub-layer1053may also be used as a gate insulating layer of the TFT405of the array substrate400. An example of a material of the third insulating sub-layer1053includes SiNx, SiOx or any other suitable materials. For example, when the third insulating sub-layer1053is used as the gate insulating layer of the TFT405, because the gate insulting layer has to be used as a mask to perform an ion doping process to the active layer401in the subsequent manufacturing process, a thickness range of the third insulating sub-layer1053may be limited to a certain range. For example, the thickness of the third insulating sub-layer1053may be smaller than 150 nm. For example, when it needs to increase a depth of the second recess106in the insulating layer105so as to correspondingly increase a relative area between the first electrode102and the second electrode103, a thickness of the first insulating sub-layer1051and the second insulating sub-layer1052in the insulating layer105can be increased. A change in thickness parameters of the first insulating sub-layer1051and the second insulating sub-layer1052would not negatively affect the performance of the array substrate400constituted by the first insulating sub-layer1051and the second insulating sub-layer1052. For example, a relationship between the depth of the second recess106in the insulating layer105and the thickness of the first and second insulating sub-layer1051,1052may be obtained through experiments. For example, the thickness of the first insulating sub-layer1051is about 6000 Å. For example, the thickness of the second insulating sub-layer1052is about 4000 Å.

As illustrated inFIG. 5, the light-emitting layer409is an organic light-emitting diode (OLED); the light-emitting layer409for example includes a pixel electrode406, an opposite electrode408, and an organic functional layer407between the pixel electrode406and the opposite electrode408. The pixel electrode406is electrically connected with the source electrode404of the TFT405; of course, the pixel electrode406may also be electrically connected with the drain electrode403of the TFT405, so that the TFT405of each of the sub-pixel units in the array substrate400can be configured to apply a signal to the pixel electrode406. A material of the pixel electrode406includes a transparent conductive material, which, for example, may be Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO) or any other suitable materials. The opposite electrode408may be configured as a common electrode of the array substrate400. For example, the pixel electrode406may be used as an anode of the light-emitting element409, and the opposite electrode408may be used as a cathode of the light-emitting element409. Of course, it's also possible that the pixel electrode406is used as the cathode of the light-emitting element409, and the opposite electrode408is used as the anode of the light-emitting element409.

The organic functional layer407for example includes an organic light-emitting layer, and may further include one or more of a hole transport layer, a hole injection layer, an electron transport layer and an electron injection layer, depending on demands.

It should be explained that, in order for clarity of illustration, the array substrate400is not illustrated in its entire structure. In order to achieve necessary function(s) of the array substrate, other structure(s) not illustrated may be arranged by those skilled in the art according to particular application scenarios, without particularly limited in the present embodiment.

The array substrate400provided by at least one embodiment of the present disclosure includes structures such as the first electrode102, the second electrode103, the TFT405and the light-emitting element409. As compared to the array substrate constituted by a flat planar electrode, by providing the first electrode102and the second electrode103with a bending design, each of the first electrode102and the second electrode103can include a portion forming a first recess104, which increases a relative area of the first electrode102and the second electrode103in regions opposite to each other in per unit area, and improves a capacitance of the array substrate400constituted by the first electrode102and the second electrode103, so as to facilitate the design of the array substrate400in terms of high resolution ratio and improve the display quality.

Other technical effect(s) achieved by the array substrate400provided in the present embodiment may be referred to that of any array substrate described in the embodiments above, without repeating herein.

For example, another embodiment of the present disclosure further provides a display panel including any array substrate described in the embodiments above. The display panel may be, for example, a liquid crystal display panel or an organic light-emitting diode display panel and the like. The technical effect achieved by the display panel may be referred to that of the array substrate described in the embodiments above, without repeating herein.

For example, another embodiment of the present disclosure further provides an electronic device including any array substrate described in the embodiments above. The electronic device for example may be any product or component including the array substrate, such as a display, a television, a digital camera, a mobile phone, a watch, a tablet computer, a notebook computer and a navigation device. The technical effect(s) achieved by the electronic device may be referred to that of the array substrate described in the embodiments above, without repeating herein.

Another embodiment of the present disclosure provides a manufacturing method of an array substrate, including: forming an insulating layer on a base substrate; forming a recess in the insulating layer, the recess penetrating at least part of the insulating layer from a side of the insulating layer facing away from the base substrate; and forming a capacitor structure at least on a side wall of the recess in a conformal manner. Forming the capacitor structure includes: forming a first electrode, forming a second electrode, and forming a dielectric layer located between the first electrode and the second electrode.

Another embodiment of the present disclosure provides a manufacturing method of an array substrate, and the array substrate is any array substrate described in the embodiments above. The present embodiment will be described with reference to the manufacturing method of the array substrate200by way of example.FIGS. 6A-6Gare schematic diagrams illustrating a sectional structure of the array substrate200during the manufacturing method as provided by the present embodiment.

As illustrated inFIG. 6A, first of all, the method includes providing a base substrate101, the base substrate101for example may be a glass substrate, a quartz substrate, a plastic substrate or a substrate of any other suitable materials, without particularly limited in the present embodiment. For example, the base substrate101may also be a flexible substrate of polyimide. When a flexible substrate is adopted, it may be placed on a bearing glass so as to facilitate fabrication of film layers.

As illustrated inFIG. 6A, the method includes depositing a buffering layer109on the base substrate101by using, for example, chemical vapor deposition (CVD) method, physical vapor deposition (PVD) method or the like. The buffering layer109for example can prevent impurity ions and moistures or external air and the like from permeating the array substrate through the base substrate101; at the same time, and the buffering layer109for example can flatten a surface of the base substrate101. The buffering layer109for example can also prevent impurity ions in the array substrate101from diffusing into circuit layer(s) formed later, including TFT and the like, so as to avoid any influence to the performance of the TFT element, such as threshold voltage and leakage current. An example of a material used for the buffering layer109includes SiNx, SiOx or any other suitable materials, without particularly limited in the present embodiment.

As illustrated inFIG. 6A, the method includes depositing a barrier layer110on the buffering layer109by using, for example, CVD method, PVD method or the like. For example, the barrier layer110may be configured to avoid an unexpected leakage current which may be caused by photo-induced carriers generated from an external light irradiation on an active layer formed later in the array substrate. An example of a material used for the barrier layer110includes a metallic material (e.g., Ag, Cr or the like), SiNx, SiOx or any other suitable materials, without particularly limited in the present embodiment.

As illustrated inFIG. 6A, the method includes depositing a second insulating layer111on the barrier layer110by using, for example, CVD method, PVD method or the like. An example of a material of the second insulating layer111includes polyimide or any other suitable materials, without particularly limited in the present embodiment.

As illustrated inFIG. 6B, the method includes depositing a first insulating sub-layer1051, a second insulating sub-layer1052, and a third insulating sub-layer1053, in sequence, on the second insulating layer111by using, for example, CVD method, PVD method or the like, so as to constitute an insulating layer105. For example, according to the requirements of product design, the first insulating sub-layer1051, the second insulating sub-layer1052, and the third insulating sub-layer1053having a required thickness may be obtained, respectively, by controlling parameters such as deposition time and deposition rate. Of course, the number of insulating sub-layer included in the insulating layer105includes but is not limited to three. For example, according to the requirements of product design, the number of insulating sub-layer included in the insulating layer105may be one, two, four or more, without particularly limited in the present embodiment. An example of a material used for the first insulating sub-layer1051, the second insulating sub-layer1052, and the third insulating sub-layer1053includes SiNx, SiOx or any other suitable materials, without particularly limited in the present embodiment.

As illustrated inFIG. 6C, the method includes forming a photoresist layer (not illustrated) on the entire surface of the third insulating sub-layer1053, and patterning the photoresist layer by using a patterning process including steps of exposing and developing so as to form a photoresist pattern with a required shape on the third insulating sub-layer1053; and then simultaneously etching the third insulating sub-layer1053, the second insulating sub-layer1052and the first insulating sub-layer1051by using the photoresist pattern as an etching mask, so as to form two second recesses106in the insulating layer105constituted by the third insulating sub-layer1053, the second insulating sub-layer1052and the first insulating sub-layer1051. For example, the two second recesses106are formed in parallel. The etching method includes, for example, dry etching. By controlling parameters such as etching time and etching rate, a depth of the second recess106can be controlled, so that the second recess106as formed at least can penetrate at least one insulating sub-layer at a side of the insulating layer105far away from the base substrate101and would not penetrate the second insulating layer111. As illustrated inFIG. 6C, the second recess106includes a bottom wall BS and a side wall SS.

As illustrated inFIG. 6D, the method includes depositing a metallic layer on the third insulating sub-layer1053by using, for example, CVD method, PVD method or the like, and then patterning the metallic layer by using photolithographic technology so as to form a first electrode102including two first recesses104on the third insulating sub-layer1053. Portions1042of the first electrode102including two first recesses104are formed along the two second recesses106of the insulating layer105, respectively, in a conformal manner. An example of a material used for the first electrode102includes Ag, Al, Cr, Cu, Mo, Ti, Al—Nd alloy, Cu—Mo alloy, Mo—Ta alloy, Mo—Nd alloy or any combination thereof. For example, as illustrated inFIG. 6D, the first electrode has a portion in a shape as same as that of the second recess106.

For example, in another example, the method includes depositing a metallic layer on the third insulating sub-layer1053by using CVD method, PVD method or the like, and then patterning the metallic layer by using photolithographic technology so as to form a first electrode102on the third insulating sub-layer1053. The first electrode102includes a portion forming a first recess104, and the portion1042of the first electrode102forming the first recess104is formed along at least one second recess106in a conformal manner.

As illustrated inFIG. 6E, after forming the first electrode102having portions forming two first recesses104on the third insulating sub-layer1053, the method includes depositing a dielectric layer film on the first electrode102by using, for example, CVD method, PVD method or the like, and then patterning the dielectric layer film by using photolithographic technology so as to form a dielectric layer107on the second electrode103. The dielectric layer107as formed includes portions108forming two first recesses104, and the portions108forming two first recesses104are formed along portions1042of the first electrode102forming two first recesses104, respectively, in a conformal manner. An example of a material used for the dielectric layer107includes silicon oxide, silicon nitride, silicon oxynitride or any other suitable materials such as a high dielectric coefficient material, without particularly limited in the present embodiment. For example, as illustrated inFIG. 6E, the dielectric layer107has a portion in a shape as same as that of the second recess.

As illustrated inFIG. 6F, the method includes depositing a metallic layer on the dielectric layer107by using CVD method, PVD method or the like, and then patterning the metallic layer by using photolithographic technology so as to form a second electrode103on the dielectric layer107. The second electrode103as formed is at least partly opposite to the first electrode102in the direction perpendicular to the base substrate101, and the second electrode103and the first electrode102are electrically insulted from each other through the dielectric layer107. The second electrode103includes portions1043forming two first recesses104; and the portions1043of the second electrode103forming two first recesses104are formed along the portions108of the dielectric layer107forming two first recesses104, respectively, in a conformal manner. An example of a material used for the second electrode103includes Ag, Al, Cr, Cu, Mo, Ti, Al—Nd alloy, Cu—Mo alloy, Mo—Ta alloy, Mo—Nd alloy or any combination thereof. As illustrated inFIG. 6F, the capacitor structure014has a portion140forming a first recess104.

In another example, the method includes depositing a metallic layer on the dielectric layer107by using CVD method, PVD method or the like, and then patterning the metallic layer by using patterning process so as to form a second electrode103on the dielectric layer107. The second electrode103includes a portion forming a first recess104; and the portion1043of the second electrode103forming the first recess104and the portion108of the dielectric layer107forming at least one first recess are formed in a conformal manner.

As illustrated inFIG. 6Qafter forming the second electrode103including portions1043forming two first recesses104, the method includes depositing an interlayered dielectric film112on the second electrode103by using CVD method, PVD method or the like, and then patterning the interlayered dielectric film by using photolithographic technology so as to form an interlayered dielectric layer112. The interlayered dielectric layer112covers the second electrode103so as to protect the second electrode103; an example of a material used for the interlayered dielectric layer112includes SiNx, SiOx or any other suitable materials, without particularly limited in the present embodiment.

The method further includes depositing a planarization layer film on the interlayered dielectric layer112, and then patterning the planarization layer film by using a patterning process so as to form a planarization layer113. An example of a material used for the planarization layer113includes SiNx, SiOx or any other suitable materials, without particularly limited in the present embodiment.

In the manufacturing method of the array substrate200provided by at least one embodiment of the present disclosure, as compared to the array substrate constituted by a flat planar electrode, in the direction perpendicular to the base substrate101, by designing the first electrode102and the second electrode103to each include portions forming two first recesses104, a relative area of the first electrode102and the second electrode103in regions opposite to each other can be increased, and the capacitance of the array substrate200constituted by the first electrode102and the second electrode103can be improved.

In case of no conflict, the embodiments and the features in the embodiments can be combined with each other to attain additional embodiment(s).

The above are only specific implementations of the present disclosure, without limiting the protection scope of the present disclosure thereto. Any changes or substitutions easily occur to those skilled in the art within the technical scope of the present disclosure should be covered in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.