pBIST read only memory image compression

A programmable Built In Self Test (pBIST) system used to test embedded memories where a plurality of memories requiring different testing conditions are incorporated in an SOC. The pBIST Read Only Memory storing the test setup data is organized to eliminate multiple instances of test setup data for similar embedded memories.

TECHNICAL FIELD OF THE INVENTION

The technical field of this invention is high speed memory testing, and more particularly a built-in self-test (BIST) system for embedded memories.

BACKGROUND OF THE INVENTION

Testing fabricated integrated circuits to determine proper operation has always been a challenging task, particularly with regard to on-board memory functions. There are two major types of device malfunctions caused by design defects. A design defect arises when the integrated circuit was manufactured to a design specification that did not provide proper function for the intended use purpose. Such a defect affects any manufactured integrated circuit until the design defect is corrected. The integrated circuit manufacturer must detect and correct such defects before shipping large number of devices to customers to avoid a costly recall. In contrast to a design defect, a manufacturing defect involves some fault in the manufacture of the integrated circuit. A manufacturing defect will generally affect less than all parts manufactured. Such defects are corrected by identification and correction of the manufacturing fault.

Most integrated circuit manufacturers test integrated circuits for proper operation before shipment to customers. Increasing integrated circuit complexity makes this testing increasingly difficult. Rather than rely on increasingly expensive external testing devices, many manufacturers test integrated circuits using a built-in self-test (BIST). BIST uses circuits on the integrated circuit designed solely to test the integrated circuit. When triggered either automatically in circuit operation or by an external test device, the BIST circuits produce a set of test conditions run on the ordinary circuit hardware. Comparison of the state of the integrated circuit following test to an expected state indicates whether the integrated circuit passed. An example of such a test is writing to a read/write memory and recalling the data written. A match between the data written and the data read passes the test. BIST typically involves other more complex tests.

A subset of BIST is programmable built-in self test (pBIST) that uses a general purpose test engine programmed by a set of instructions. This set of test instructions is typically stored on the integrated circuit in a read only memory (ROM) and includes instructions particularly developed for that integrated circuit. pBIST enables re-use of hardware and test instructions to cover a family of similar but not identical integrated circuits.

U.S. Pat. No. 7,324,392 entitled ROM-Based Memory Testing includes a description of an exemplary set of instructions for use in a pBIST. This patent is incorporated by reference in its entirety.

In conventional VLSI systems memory testing is done in three steps. In the first step hardwired logic (often available through third-party vendors, examples are memBIST (MBIST) use algorithms developed before the device is committed to tape-out. Determining the detailed make-up of hardwired logic is not feasible at this time. It is impossible to predict the appropriate hardware circuits because the necessary information comes from process model drivers during the process qualification window. Secondly, conventional memory testing attempts to close testing gaps using CPU based techniques. These techniques have a number of limitations. A major limitation is the CPU interface with largely inaccessible memory functions. The inability to do back-to-back accesses to all memories is another severe limitation. Thirdly, during memory testing while the device is in wafer form direct memory access (DMA) external memory accesses cannot be accomplished at full processor speed. This may result in a significant number of failures not being observable.

SUMMARY OF THE INVENTION

An SOC (System On Chip) usually contains a plurality of memories. A pBIST (programmable Built In Self Test) module is employed to test the embedded memories.

This invention describes a novel ROM (Read Only Memory) organization within the pBIST that reduces the amount of ROM required to store memory testing and configuration information.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

SRAM/memory structures of different devices vary by technology, design and implementation. To test memories effectively the address access pattern sequence of the memory testing algorithm should follow a particular pattern that sensitizes and tests the electrical structure within the memory.

In a simple memory structure the physical addresses and logical addresses are contiguous and are matched.

Effective testing can be preformed with simple algorithms that linearly increment or decrement addresses. In these memories any possible address scrambling automatically matches the input to the output. Namely bit <0> of the input goes to bit <0> of the output and so on.

The SOC device100includes multiple modules that can be highly complex to test. SOC100includes central processing unit (CPU)110and memories111and112through119coupled by bus120. Other SOC devices may include multiple processors, complex assemblages of memory and cache subsystems, peripheral devices and interfaces, various types of memory storage such as random access memory (RAM), read only memory (ROM) and possibly various types of alterable memory or flash ROM.

The programmable built-in self-test unit pBIST130includes a pBIST controller129, pBIST ROM131, an ID Value interface132, ID Compare unit128and external interface133. pBIST controller129controls SOC tests in much the same fashion as CPU110controls the normal operation of integrated circuit100. pBIST unit130is controlled by test instructions stored in pBIST ROM131. pBIST unit130may couple to circuits outside integrated circuit100via external interface133. Addresses enter and exit pBist unit130via Address I/O134.

pBIST controller129selects a particular pBIST controller within a group of pBIST controllers by using a pBIST ID (identification) value interface132. The pBIST ID value is typically a five-bit value that allows selection of up to thirty-one pBIST controllers.

FIG. 2is a block diagram of functional units included in prior art pBist130. pBIST unit130includes pBIST controller129, registers221through228, dual address register230, match unit232and multiple input signature register (MISR) unit233. Addr[15:0] I/O134allows for input or output of pBist addresses.

Configuration registers221through228are memory mapped within the address space of CPU110. Thus CPU110can read from or write to any register221through228by a memory operation to the corresponding address. Configuration registers221through228control the configuration and the operational mode of pBIST unit130. Data registers222store test data recalled from pBIST ROM131. Program registers223store test program instructions recalled from pBIST ROM131. Other registers224include miscellaneous general-purpose registers. Configuration registers221includes four additional registers algorithm register225, upper RAM information (RINFOL) register226, lower RAM information (RINFOU) register227and pBIST ID register228which will be more fully discussed below.

Algorithm register225is actually an algorithm mask register. Bit [0] of this register indicates whether the first algorithm stored in pBIST ROM131would be executed. Bit [1] indicates whether the second algorithm is executed and so on. A total of 32 algorithms stored in pBist ROM131can be controlled the 32-bit word width of algorithm register225. For an algorithm to be executed, both the corresponding bit of algorithm register225and a valid bit in the previous algorithm header must be set.

RINFOL register226and RINFOU register227are group mask registers similar to algorithm register225. RINFOL register226and RINFOU register227indicate whether a particular RAM group is tested. This capability is provided because not all algorithms can be run on all memories. For a particular RAM group to be tested the corresponding bit in RINFOL register226or RINFOU register227and the valid bit in the previous RAM group header must both be set. RINFOL register226indicates the validity of RAM groups 0 to 31 and RINFOU register227indicates the validity of RAM groups 32 to 63.

pBIST ID register228is a memory mapped register that is loaded with a pBIST ID at the beginning of a programming sequence to specify which of a multiple of pBIST controllers129is being programmed by an external tester or by the local CPU110. Upon being reset, pBIST register assumes a value of 0x0000. Each pBIST controller129is assigned a unique ID value input via ID value interface132when the SOC integrated circuit is designed. This may be embodied by simply tying off the five-bit field to either a high or to a low reference voltage to form a five-bit ID value. Dual Address registers230are used in accessing memory, such as memories111,112, through119.

FIG. 3illustrates memory read portion of a prior art device included here as an example of how address scrambling may be used. In the exampleFIG. 3, the memory has N blocks, each block has M columns and each column has R rows. Output data from two memory blocks (block—0300and block—1301are selected by multiplexers302,303and304. Each of the thirty-two vertical units of block—0300and block—1301contain thirty-two rows of data, each row containing four eight-bit bytes labeled bytes 0 through 3.

Row address <R-1:0> supplies the row address input of block—0300and block—1301and selects one row out of rows 2R−1 to 0 in each block. Data from column 2M−1 to column 0 are output from block—0300to multiplexer302. Column address <M-1:0> supplied to the control input of multiplexer302selects the data for the corresponding column. Similarly, data from column 2M−1 to column 0 are output from block—1301to multiplexer303. Column address <M-1:0> supplied to the control input of multiplexer303selects the data for the corresponding column. The outputs of multiplexers302and303are supplied as inputs to multiplexer304. Block address <N-1:0> supplied to the control input of multiplexer304selects data from the corresponding block for output as data231.

In the memory ofFIG. 3: a column address <(M-1):0> bits wide selects between M columns; a block address <(N-1):0> bits wide selects between N blocks of memory banks; and a row address <(R-1):0> bits wide selects between R rows of logical addresses inside each bank of memory.

FIG. 3illustrates a partitioning of the example memory blocks. The example memory ofFIG. 3requires that the SRAM addresses have two-bit column addresses <0> and <1>, two-bit row A addresses <2> and <3>, a single-bit block address <4> and a three-bit row B address <5>, <6> and <7>. The address supplied to the memory is divided into these three sections. The positions of the above regions may vary from design to design.

The prior pBIST130illustrated inFIGS. 1 and 2is designed for straightforward linear addressing. Row addresses are the address least significant bits (LSBs) <0> through <4>. Column addresses are bits <5> and <6>. The block address is bit <7>. Incrementing through these addresses would fetch data from row 0 through row 31 in sequential order in block—0300and then data from row 32 through 63 in sequential order in block—1301.

The first pass of this linear addressing would address block—0300and proceed through all row addresses sequentially fetching all column 0 data first, and all column 1 data next, followed by column 2 data and finally column 3 data. The second pass of this linear addressing would address block—1301and proceed through all row addresses sequentially fetching all column 0 data first, and all column 1 data next, followed by column 2 data and finally column 3 data.

The architecture demonstrated inFIG. 4consists of a single pBIST, with a Distributed Data Logger system. Each sub chip incorporates a data logger that communicates with the controlling pBIST.

Data is input from the tester (VLCT) to combiner401to format the data, then to pBIST block402, with pBIST memory403. pBIST402communicates with the applicable sub chips via the compressed data bus, and receives fail and log information from each sub chip. The log information is presented in a serial manner to reduce the number of connections.

The sub chips may contain an asynchronous bridge405if they operate in a different voltage and/or clock domain from the pBIST. Asynchronous bridge405connects to distributed data logger406which communicates to control block407. Block407expands the compressed data before writing the test pattern to memory408, and then reads the result from408. The comparison of the expected and actual memory data is performed in DDL406. Since the comparison is done locally in each sub chip, there is no need to return the read data to the pBIST thus reducing the number of connections.

In a pBIST implementation, a plurality of embedded Random Access Memories (RAM) must be tested. Each embedded memory block may need different test algorithms and testing conditions, and the pBIST must be able to set up the testing process depending the actual memory selected. The setup data may be provided by the SOC tester, or it may be stored in the pBIST Read Only Memory (ROM).

In the prior art, the pBIST ROM stored the configuration data separately for each RAM block as shown in Table 1 where the ROM is divided into two sections. The first location stores the pointer to the beginning of the algorithm section (ALGO_PTR), and the second location stores the pointer to the beginning of the RAM Group Section. The algorithm section stores the test algorithm for the selected RAM, and the RAM Group Section stores the constants required for testing the selected RAM block. Table 2 shows the contents of the Ram Group Section.

This ROM structure is repeated for each embedded memory block that may be present.

The current invention eliminates the duplication that may result from storing the setup constants separately for each embedded memory block. As shown in Table 3, a new ROM section called the Data Section is introduced, that will store only the memory type specific information. In each Ram Group Section we only store a pointer to the location where the constant data is stored, allowing the reuse of the data for similar instances of embedded RAM.

Table 4 shows the format of the Ram Group Section in this implementation.