Chip package

A chip package is provided. The chip package includes a chip, having a plurality of conductive pads disposed along a periphery of the chip, wherein the conductive pads have a width. A seal ring includes a plurality of metal strips disposed within a space between the two adjacent conductive pads. Each metal strip is electrically connected to at most one of the two adjacent conductive pads.

CROSS REFERENCE TO RELATED APPLICATIONS

This Application claims priority of Taiwan Patent Application No. 98145253, filed on Dec. 28, 2009, the entirety of which is incorporated by reference herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a chip package, and in particular relates to a sealing ring structure of a chip package.

2. Description of the Related Art

Wafer level packaging technology has been developed for packaging chips. After a wafer level package is completed, a cutting process is performed between each chip to separate the chips from each other. In order to reduce the probability of cracks, produced by the cutting process, extending to the inner side portions of the chip, a sealing ring is disposed between each chip to enhance chip package reliability. However, because the sealing ring occupies an extra area of a wafer, the amount of dies formed on the wafer is reduced.

BRIEF SUMMARY OF THE INVENTION

According to an illustrative embodiment, a chip package is provided. The chip package comprises a chip having a plurality of conductive pads disposed along a periphery of the chip. A seal ring containing a plurality of metal strips is disposed within a space between the two adjacent conductive pads, wherein each metal strip is electrically connected to at most one of the two adjacent conductive pads.

DETAILED DESCRIPTION OF THE INVENTION

The following description is of a mode for carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. Wherever possible, the same reference numbers are used in the drawings and the descriptions to refer the same or like parts. In the drawings, the size of some of the elements may be exaggerated and not drawn to scale for illustrative purposes. The dimensions and the relative dimensions do not correspond to actual dimensions to practice of the invention. Further, parts of the elements in the drawings are illustrated by the following description. Some elements not shown in the drawings are known by one skilled the art.

The embodiments of chip packages of the invention and fabrication methods thereof are illustrated by embodiments of fabricating image sensor packages in the following description. However, it should be appreciated that the invention may also be applied to forming other semiconductor chip packages. Therefore, the packages of the embodiments of the invention may be applied to active or passive components, or electronic components with digital or analog circuits, such as optoelectronic devices, micro electro mechanical systems (MEMS), micro fluidic systems, and physical sensors for detecting heat, light, or pressure. Particularly, a wafer level chip scale packaging (WLCSP) process may be applied to package semiconductor chips, such as image sensors, solar cells, RF circuits, accelerators, gyroscopes, micro actuators, surface acoustic wave devices, pressure sensors, and ink printer heads.

The wafer level chip scale packaging process herein mainly means that after the packaging process is accomplished during a wafer stage, a wafer with chips is cut to obtain separate independent packages. However, in an embodiment of the invention, separate independent chips may be redistributed overlying a supporting wafer and then be packaged, which may also be referred to as a wafer level chip scale packaging process. In addition, the wafer level chip scale packaging process may also be adapted to form chip packages of multi-layered integrated circuit devices by stacking a plurality of wafers having integrated circuits together.

Referring toFIG. 1, a top view of sealing ring structures of chip packages according to an embodiment of the invention is shown. A periphery of each chip30is surrounded by a sealing ring32and a scribe line c is disposed between the two adjacent sealing rings32. Referring toFIG. 2A, an enlarged top view of the dotted line area3B ofFIG. 1is shown. As shown inFIG. 2A, a plurality of conductive pads34is disposed along the periphery of the chip. The sealing ring32includes a plurality of metal strips40disposed between the two adjacent conductive pads34. In an embodiment, all of the metal strips40are disposed within a space between the two adjacent conductive pads34. Thus, the sealing ring structure of the embodiment can be accomplished by using the conductive pads34and the spaces between the two adjacent conductive pads34. In another embodiment, if the width of the sealing ring32is not greater than the width of the two adjacent conductive pads34and the width between the two adjacent sealing rings32is about 80 μm, a required width for the scribe line c is only about 80 μm. Accordingly, for a wafer with a diameter of 8 inches, the amount of area available for dies is increased. Moreover, the sealing ring structure design of the embodiment can be applied to a chip on board (COB) packaging process and a chip scale packaging (CSP) process.

In an embodiment, the conductive pad34may be an extended contact pad, which is electrically connected to a bonding pad on the chip through a connection part36thereof. Thus, a space between the extended contact pad and the bonding pad to dispose an inside sealing ring is not needed, such that the area of chips is decreased.

In an embodiment, the width w of the conductive pad34is for example about 50 μm and the width of the metal strip40is for example about 10 μm. Thus, as shown inFIG. 2A, three parallel metal strips41,43and45can be disposed between the conductive pads34. Moreover, in an embodiment, more than three or less than three metal strips can be disposed between the conductive pads34depending on actual requirements for the chip packages. It is noted that two ends of each metal strip41,43and45are not both electrically connected to two adjacent conductive pads34, i.e. at least one gap is disposed between each metal strip and two adjacent conductive pads to avoid short circuiting. In an embodiment, at least one outside gap is disposed at the outside of the space between the two adjacent conductive pads and at least one inside gap is disposed at the inside of the space between the two adjacent conductive pads. For example, an outside gap41ais disposed between the metal strip41adjacent to the outside of the chip, such as the scribe line c, and the conductive pad34. Meanwhile, an inside gap45ais disposed between the metal strip45adjacent to the inside of the chip and the conductive pad34. In an embodiment, a curved channel C-C is formed from the outside gap41ato the inside gap45aand between the parallel metal trips41,43and45, and a length of the curved channel C-C is greater than a distance d between the outside metal strip41and the inside metal strip45. The curved channel C-C comprises a connection channel D along a space between the two metal strips41and43and another connection channel D along a space between the two metal strips43and45. Accordingly, by forming the metal strips41,43and45, the stress produced from the cutting process for the chip package is passed along to the curved channel C-C between the metal strips41,43and45to enter the chip package. Thus, direct stress passing from the outside gap to the inside gap is prevented, thereby preventing cracks from forming and extending to the inner side of the chip.

Next, referring toFIG. 2B, a three-dimensional view of a portion of the sealing ring structure32according to an embodiment of the invention is shown. In the embodiment, the conductive pad34has three metal layers341,342and343. The connection part36, extending from the conductive pad34to electrically connect to the bonding pad (mot shown), also has three metal layers361,362and363. In this embodiment, the conductive pad is electrically connected to the bonding pad through the three metal layers. However, in other embodiments, the conductive pad can be electrically connected to the bonding pad through one metal layer. For example, the conductive pad can be electrically connected to the bonding pad through the middle metal layer362. In an embodiment, a plurality of vias42is disposed between the three metal layers341,342and343of the conductive pad34for electrically connecting each metal layer. The positions of the vias42are not limited. Meanwhile, the vias42can prevent some cracks from occurring and extending to the inner side of the chip.

In an embodiment, each metal strip41,43and45disposed between the two adjacent conductive pads34can have three metal layers. As shown inFIG. 2B, the metal strip41has three metal layers411,412and413and a plurality vias42is disposed between each metal layer411,412and413for electrically connecting each metal layer. The vias42can be disposed at any position between each metal layer, and is not limited to the positions as shown inFIG. 2B. In an embodiment, the metal layers of the conductive pads can be formed with the metal layers of the metal strips at the same time, thus the amount of the metal layers of the conductive pads can be the same as that of the metal layers of the metal strips. It is noted that, in an embodiment, at least a stress barrier44is disposed between the metal layers411,412and413of the metal strip41. The stress barrier44can strengthen the structure of the sealing ring32and further efficiently prevent cracks from occurring and extending to the inner side of the chip. In an embodiment, at least a stress barrier is disposed between the metal layers of each metal strip41,43and43, i.e. each metal strip41,43and43has a stress barrier. As shown inFIG. 2B, gaps between the stress barriers and the conductive pads can be disposed according to the arrangement of the metal strips and the conductive pads as shown inFIG. 2A. Therefore, the stress produced from the cutting process for the chip package is passed along the extended channel between the two stress barriers to enter the chip package. Thus, direct stress passing from the outside gap to the inside gap is prevented, thereby preventing cracks from forming and extending to the inner side of the chip

In the embodiment of the sealing ring structure, the metal strips40between the conductive pads34can be disposed by various types, wherein one type is shown inFIG. 2A. Meanwhile, two other types are shown inFIGS. 3A and 3B. Referring toFIG. 3A, in one embodiment, two parallel metal strips401and403are disposed between the conductive pads34. One end of the metal strips401and403is connected to one of the conductive pads34and the other end of the metal strips401and403is disposed apart from the other conductive pad with a gap. The gaps between the metal strips401and403and the conductive pads34are staggered, such that the stress produced from the cutting process for the chip package is passed along the extended channel S between the two metal strips401and40to enter the chip package. Thus, preventing cracks from forming and extending to the inner side of the chip.

Next, referring toFIG. 3B, in this embodiment, three metal strips405,407and409are disposed between the conductive pads34, wherein the metal strips405and407are arranged on the same straight line. The direction of the straight line of the arrangement of the metal strips405and407is perpendicular to the conductive pad34. Meanwhile, one end of the metal strips405and407are connected to the conductive pads34and a gap is formed between the metal strips405and407. Another metal strip408is parallel to the metal strips405and407and both of the two ends of the metal strip408are disposed apart from the conductive pads34with a gap. It is noted that, inFIG. 3B, the gaps between the metal strips and the conductive pads are staggered.

The arrangements of the metal strips for the sealing ring structure of the invention are illustrated by several embodiments in the present specification. However, it should be appreciated that the metal strips between the conductive pads may also be arranged in other arrangements. The requirement for arrangement of the metal strips comprises not producing a short circuit between the conductive pads, and staggering the gaps between the metal strips and two adjacent conductive pads or staggering the gaps between each metal strip arranged.

Referring toFIGS. 4A-4F, cross sections illustrating the steps for fabricating a chip package according to an embodiment of the invention are shown. The cross sections ofFIGS. 4A-4Fare taken along the cross section line X-X′ ofFIG. 2A, which are located at the position of the conductive pads34, such that the metal strips40are not shown inFIGS. 4A-4F. Referring toFIG. 4A, firstly, a substrate100, for example a semiconductor wafer, is provided. The semiconductor wafer100has a plurality of chips (not shown), for example image sensor devices, formed thereon and a corresponding micro-lens array100may be disposed over the image sensor devices to be an image sensing surface. A dielectric layer104, for example a silicon oxide layer, is disposed on a substrate of the semiconductor wafer and each chip has corresponding conductive pads102disposed in the dielectric layer104.

Next, a front side of the semiconductor wafer100, i.e. the surface having the chips thereon is bonded to a packaging layer200. The packaging layer is used for a carrier structure of the chip packages, which may be a transparent substrate made of glass, quartz, opal, plastic or other materials that permit light to pass therethrough. Moreover, a filter and/or an anti-reflective layer can be selectively formed on the packaging layer. In an embodiment, a spacer106may be disposed between the packaging layer200and the semiconductor wafer100, such that a cavity107is formed between the packaging layer200and the semiconductor wafer100, wherein the cavity107is surrounded by the spacer106.

The spacer106may be made of epoxy resin, a solder mask or other suitable insulating materials, for example inorganic materials of silicon oxides, silicon nitrides, silicon oxynitrides, metal oxides or combinations thereof, or organic polymer materials of polyimide (PI), butylcyclobutene (BCB), parylene, polynaphthalenes, fluorocarbons, accrylates, etc. The spacer106can be formed by a coating method, such as a spin coating method, a spray coating method, or a curtain coating method, or other suitable deposition methods, such as a liquid phase deposition method, a physical vapor deposition (PVD) method, a chemical vapor deposition (CVD) method, a low pressure chemical vapor deposition (LPCVD) method, a plasma enhanced chemical vapor deposition (PECVD) method, a rapid thermal-CVD (RTCVD) method or an atmospheric pressure chemical vapor deposition (APCVD) method. The spacer106can block environmental contaminants or prevent the chip packages from water vapor permeation.

In an embodiment, the chip packages can be applied to, but are not limited to, image sensor devices, such as complementary metal oxide semiconductor (CMOS) devices or charge-couple devices (CCD). Moreover, the conductive pads102may be extension pads and preferably, formed from copper (Cu), aluminum (Al) or other suitable metal materials.

Next, referring toFIG. 4B, the semiconductor wafer100is thinned from a back side thereof by a thinning process to form a semiconductor wafer100′ with a predetermined thickness. The thinning process may be an etching process, a milling process, a grinding process or a polishing process. Then, notches109are formed on the back side of the thinned semiconductor wafer100′ by a notching process. After forming the notches109, the semiconductor wafer100′ is divided to form a plurality of independent chips.

Referring toFIG. 4C, the dielectric layer104under the bottoms of the notches109is etched to expose a contact surface of the conductive pads102. Then, referring toFIG. 4D, an insulating layer112is formed to cover the sidewalls of the notches109and the back side of the semiconductor wafer100′. In an embodiment, the insulating layer112may be formed from epoxy resin, a solder mask or other suitable insulating materials, for example inorganic materials of silicon oxides, silicon nitrides, silicon oxynitrides, metal oxides or combinations thereof, or organic polymer materials of polyimide (PI), butylcyclobutene (BCB), parylene, polynaphthalenes, fluorocarbons, accrylates, etc. The insulating layer112can be formed by a coating method, such as a spin coating method, a spray coating method, or a curtain coating method, or other suitable deposition methods, such as a liquid phase deposition method, a physical vapor deposition (PVD) method, a chemical vapor deposition (CVD) method, a low pressure chemical vapor deposition (LPCVD) method, a plasma enhanced chemical vapor deposition (PECVD) method, a rapid thermal-CVD (RTCVD) method or an atmospheric pressure chemical vapor deposition (APCVD) method. The insulating layer112can isolate the semiconductor wafer100′ and a subsequently formed conductive trace layer114.

Then, the conductive trace layer114is formed in the notches109and on the back side of the semiconductor wafer100′. The conductive trace layer114can be formed by a physical vapor deposition (PVD) method or a sputtering method for conformally depositing a conductive layer, such as copper (Cu), aluminum (Al), silver (Ag), nickel (Ni) or alloys thereof, in the notches109and on the back side of the semiconductor wafer100′. Then, the conductive layer is patterned by a photolithography and etching process to form the conductive trace layer114. The conductive trace layer114is in contact with the surface of the conductive pad102to form an L-shaped contact and extends to a terminal contact (not shown) on the back side of the semiconductor wafer100′.

Next, referring toFIG. 4E, a passivation layer116is formed on the conductive trace layer114, covering the back side of the semiconductor wafer100′ and the notches. The passivation layer116is for example a solder mask. Then, referring toFIG. 4F, a conductive bump118is formed, passing through the passivation layer116to electrically connect to the conductive trace layer114. In an embodiment, after forming the passivation layer116, the passivation layer116is patterned to form an opening, exposing a portion of the conductive trace layer114. Then, the opening of the passivation layer116is filled with a solder by an electroplating method or a screen printing method and a re-flow process is performed to the solder to form the conductive bump118, such as a solder ball or a solder paste. Next, a wafer level package of the chips is divided along the scribe line to separate each chip to complete the chip packaging process of an embodiment of the invention.

According to one embodiment of the invention, in the method of fabricating the chip package, the conductive pad102is not etched and only a contact surface of the conductive pad102is exposed to be in contact with the conductive trace layer114to form the L-shaped contact. Therefore, during the fabrication processes of the chip package, damage to the sealing ring formed from the conductive pads and the metal strips disposed between the conductive pads are prevented; thereby resulting in an effective sealing ring.

According to the above, embodiments of a sealing ring structure are provided. For example, in an embodiment, the sealing ring is formed from the conductive pads and the spaces between the two adjacent conductive pads. In an embodiment, the width of the sealing ring structure is not greater than the width of the conductive pad. In an embodiment, the sealing ring includes a plurality of metal strips, which are disposed apart from two adjacent conductive pads with at least an outside gap and at least an inside gap. A curved channel formed from the outside gap to the inside gap can reduce the stress placed on the chip packages.