Thin film transistor substrate of liquid crystal display and method of manufacture

The thin film transistor substrate increases an aperture ratio as well as prevents shorts between pixel electrodes by connecting drain electrodes of thin film transistors to storage electrodes to reduce the number of holes contacting the pixel electrodes. In the method of forming the thin film transistor substrate, drain electrode patterns are formed such that drain electrodes included in thin film transistors are electrically connected to storage electrodes included in storage capacitors. Accordingly, the number of holes contacting the pixel electrodes can be reduced so that an aperture ratio can be increased, or shorts between pixel electrodes can be prevented. Also, the drain electrode patterns are formed from the same conductive layer as the data lines supplying data signals to the thin film transistors, and a constant spacing between the two can be obtained to maintain a uniform parasitic capacitance therebetween and prevent deterioration of the data signal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a liquid crystal display, and more particularly to a thin film transistor substrate, which has increased aperture ratio, prevents shorts between pixel electrodes and/or reduces the number of holes for contacting the pixel electrodes, and a method of manufacturing the thin film transistor substrate.

2. Description of the Related Art

Generally, a liquid crystal display (LCD) displays a picture by controlling light transmissivity using an electric field. To this end, the LCD includes a liquid crystal panel having liquid crystal cells arranged in a matrix, and a driving circuit for driving the liquid crystal panel. The liquid crystal panel is provided with pixel electrodes for applying an electric field to each liquid crystal cell with respect to a reference electrode, that is, a common electrode. Typically, the pixel electrodes are provided on a lower substrate for each liquid crystal cell, whereas the common electrode is integrally formed on the entire surface of an upper, opposing substrate. Each of the pixel electrodes is connected to a thin film transistor (TFT) used as a switching device. The pixel electrode drives the liquid crystal cell in accordance with a data signal applied via the TFT.

FIG. 1shows an electrode arrangement of a thin film transistor substrate of a conventional liquid crystal display. InFIG. 1, the LCD includes thin film transistors8positioned at the intersections between data lines4and gate lines2, and pixel electrodes6connected to drain electrodes14of the thin film transistors8. Each of the thin film transistors8includes a gate electrode10protruding from the gate line2, a source electrode12protruding from the data line4, and the drain electrode14connected to the pixel electrode6via a first contact hole20. Further, each thin film transistor8includes a gate-insulating film (not shown) insulating the gate electrode10from a semiconductor layer (not shown), which defines a conductive channel between the source electrode12and the drain electrode14when a large enough gate voltage is applied to the gate electrode10. The thin film transistor8responds to a gate signal from the gate line2to selectively apply a data signal from the data line2to the pixel electrode6.

The pixel electrode6is located at a cell area defined by the data line4and the gate line2and is made from an ITO (indium tin oxide) with a high light transmissivity. The pixel electrode6is formed on a protective film (not shown) coated on the entire surface of the thin film transistor8, and is electrically connected, via the first contact hole20formed in the protective film, to the drain electrode14. The pixel electrode6generates a potential difference with respect to a common transparent electrode (not shown) provided at an upper substrate, opposing the thin film transistor substrate, in response to a data signal applied via the thin film transistor8. By this potential difference, liquid crystal positioned between the thin film transistor substrate and the upper substrate is rotated to allow light, from a light source, to pass therethrough.

As further shown inFIG. 1, storage capacitor18and the prior or pre-stage gate line2are overlapped by a portion of the pixel electrode6. The storage capacitor18prevents a voltage variation in the pixel electrode6by charging to a voltage when a gate high voltage is applied to the pre-stage gate line2and discharging the charge voltage when a data signal is applied to the pixel electrode6. The storage capacitor18must have a large capacitance value so as to maintain a stable pixel voltage. To this end, the storage capacitor18is formed by the pre-stage gate line2, an overlapping storage electrode16, and the gate insulating film (not shown) disposed therebetween. The storage electrode16is electrically connected, via a second contact hole22formed in the protective film (not shown), to the pixel electrode6. The storage electrode16is provided on the gate insulating film at the time of forming the data line4and the source and drain electrodes12and14.

As described above, in the conventional thin film transistor substrate, the overlapping portion of the pixel electrode6and the pre-stage gate line2must be as large as possible so as to provide a storage capacitor with a large capacitance value. As a result, the distance between the pixels6adjacent to each other at the upper and lower portions thereof is reduced, and a short may be generated between them.

Also, inorganic film with a large dielectric constant, such as SiNx, and SiOx, is usually used for the protective film of the thin film transistor substrate. This inorganic protective film typically maintains a constant horizontal interval (e.g., 3 to 5 μm) between the pixel electrode6and the data line4to minimize a coupling effect caused by a parasitic capacitor Cds.

However, during processing, particularly the several light-exposing steps, miss alignment errors can occur between electrodes formed from different layers. As a result, a constant interval may not be maintained between the data line4and the pixel electrode6, and a capacitance of the parasitic capacitor Cds between the data line4and the pixel electrode6becomes non-uniform. A data signal, applied to the data line4and then to the pixel electrode6is deteriorated due to the coupling effect caused by this non-uniform parasitic capacitor Cds, and picture quality thus deteriorates.

Furthermore, in the conventional LCD, an aperture ratio is reduced by as much as the drain electrode14of the thin film transistor8overlaps the pixel electrode6for formation of the contact hole20.

SUMMARY OF THE INVENTION

The thin film transistor substrate according to the present invention includes a plurality of gate lines formed on a substrate and a plurality of data lines insulated from and intersecting the gate lines. The data lines and intersecting gate lines define a plurality of cells. At least one cell includes a pixel electrode, a thin film transistor connected to one of the data lines and one of the gate lines defining the cell, a storage capacitor, and a metallic pattern forming a drain electrode of the thin film transistor and a storage electrode of the storage capacitor.

In one embodiment, the metallic pattern is electrically connected to the pixel electrode at the storage electrode part. Because the storage electrode part is electrically connected to the drain electrode part, no separate connection between the drain electrode and the pixel electrode is required. As a result, the size of the drain electrode is reduced, the effective size of the pixel electrode is increased, and the aperature ratio of the thin film transistor substrate is increased.

In another embodiment, the metallic pattern is electrically connected to the pixel electrode at the drain electrode part. Because the drain electrode part is electrically connected to the storage electrode part, no separate connection between the storage electrode and the pixel electrode is required. As a result, the pixel electrode does not need to overlap the pre-stage gate line, and shorts caused by adjacent pixel electrodes being too closely spaced can be eliminated.

In yet another embodiment, the metallic pattern is electrically connected to the pixel electrode at both the drain and storage electrode parts. Preferably, in this embodiment, the metallic pattern has an annular shape approximating the periphery of the pixel electrode, and therefore, prevents light from leaking from the cell.

Preferably, in each of the embodiments, the data lines and metallic pattern are formed simultaneously from the same conductive material such that a constant predetermined minimum spacing is achieved between the metallic pattern and an adjacent data line. Consequently, a uniform parasitic capacitor, formed by the metallic pattern and the adjacent data line, is obtained, and the deterioration of the data signal is prevented.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring toFIG. 2, there is shown an electrode arrangement of a thin film transistor substrate in a liquid crystal display according to a first embodiment of the present invention. For those elements not specifically mentioned or discussed in detail, it is to be understood that those elements are the same as in the conventional art described with respect to FIG.1.

As shown, the liquid crystal display includes thin film transistors30positioned at intersections between data lines26and gate lines24, and pixel electrodes28connected, via drain electrode patterns36, to the thin film transistors30. Each of the thin film transistors30includes a gate electrode32protruding from the gate line24, a source electrode34protruded from the data line26and the drain electrode pattern36. A gate insulating film (not shown) insulates the gate electrode32from the source and drain electrodes34and36and a semiconductor layer (not shown), which forms a conductive channel between the source electrode34and the drain electrode pattern36when a gate voltage is applied to the gate electrode32.

The drain electrode pattern36is formed such that it overlaps a portion of the periphery of the pixel electrode28. The drain electrode pattern36includes a drain electrode part36A and a storage electrode part36B. The drain electrode part36A forms the drain electrode of the thin film transistor30, and the storage electrode part36B forms a part of a storage capacitor38. A portion of the storage electrode part36B overlaps part of the pre-stage gate line24, is partially overlapped by the pixel electrode28, and is connected, via a contact hole40formed in a protective film (not shown) between the storage electrode part36B and the pixel electrode28, to the pixel electrode28. Accordingly, the contact hole for connecting the pixel electrode28to the drain electrode (i.e., the drain electrode part36A) can be eliminated. This allows for reduction in the size of the drain electrode, and eliminates the need for the pixel electrode28to overlap the drain electrode part36A. As a result, the size of the pixel electrode28is increased, and the aperture ratio of liquid crystal cell is increased.

The storage electrode part36B of the drain electrode pattern36forms the storage capacitor38along with the overlapped pre-stage gate line24and the gate insulating film formed therebetween. Such a drain electrode pattern36has a relatively small width at a portion close to the data line26such that it is not shorted to the data line26. Because the drain electrode pattern36and the data line26are formed from the same conductive layer during processing, (1) a constant separation interval is formed between the drain electrode pattern36and the data line26, and (2) a parasitic capacitor Cds between the data line26and the drain electrode pattern36is consistently or uniformly maintained. As a result, deterioration of the data signal caused by the non-uniformity of the parasitic capacitor Cds is prevented. Also, the storage electrode part36B of the drain electrode pattern36has a large width so as to provide the storage capacitor38with a larger capacitance value.

The thin film transistor30responds to the gate signal from the gate line24to selectively apply the data signal from the data line26to the pixel electrode28. The pixel electrode28, located at a cell area defined by the data line26and the gate line24, is made from an ITO (indium tin oxide) material with a high light transmissivity. The pixel electrode28is formed on a protective film (not shown) coated over an entire surface of the thin film transistor substrate. The pixel electrode28generates a potential difference with respect to a common transparent electrode (not shown) provided at the upper, opposing substrate in response to a data signal applied via the thin film transistor30. By this potential difference, liquid crystal positioned between the thin film transistor substrate and the upper substrate is rotated by its dielectric anisotropy to allow light, to pass therethrough. The storage capacitor38prevents a voltage variation in the pixel electrode28by charging to a voltage when a gate high voltage is applied to the pre-stage gate line24and discharging the charge voltage when a data signal is applied to the pixel electrode28.

A method of fabricating the thin film transistor substrate having the configuration as mentioned above will be described. After a gate metal layer is deposited on a transparent substrate and patterned to form the gate line24and the gate electrode32, a gate insulating film is coated over the substrate. After an amorphous silicon layer is formed on the gate insulating film and patterned to form a semiconductor layer of the thin film transistor30, a source/drain metal layer is deposited and then patterned to form the data line26, the source electrode34and the drain electrode pattern36at the same time. Subsequently, a protective film is coated over the substrate and patterned to form the contact holes40. Finally, a transparent electrode material is coated on the protective film and then patterned to form the pixel electrode28.

Referring toFIG. 3, there is shown an electrode arrangement of a thin film transistor substrate in a liquid crystal display according to a second embodiment of the present invention. When compared with the thin film transistor shown inFIG. 2, the thin film transistor substrate ofFIG. 3has the same constructional elements except that the drain electrode pattern42is electrically connected via a contact hole44to the pixel electrode28at a drain electrode part42A. Accordingly, the contact hole for connecting the pixel electrode28to storage electrode part42B is eliminated to reduce an amount of overlap between the storage electrode part42B and the pixel electrode28. Note also inFIG. 3that pixel electrode28overlaps gate line24, the edge of pixel electrode28designated by reference28A, and contrastFIG. 2in which pixel edge28A overlaps the gate line more than in FIG.3. The contact hole for connecting the pixel electrode28to storage electrode part42B is eliminated in FIG.3.

In this embodiment, because the amount or width of the pixel electrode28overlapping the storage electrode part42B of the drain electrode pattern42is reduced from 15 to 20 μm in the prior art to 2 to 4 μm, a potential snort between the upper and lower pixel electrodes28can be prevented. Also, the drain electrode pattern42and the data line26are formed from the same layer with a uniform interval therebetween to uniformly maintain a parasitic capacitor Cds between the drain electrode26and the drain electrode pattern42. Therefore, a deterioration of the data signal caused by a non-uniformity of the parasitic capacitor Cds is prevented.

The thin film transistor substrate ofFIG. 3is formed by the same method as described with respect toFIG. 2, except that the protective film is patterned to form the contact holes44and the pixel electrodes28are formed to have the shape shown in FIG.3.

Referring toFIG. 4, there is shown an electrode arrangement of a thin film transistor substrate in a liquid crystal display according to a third embodiment of the present invention. When compared with the thin film transistor shown inFIG. 3, the thin film transistor substrate ofFIG. 4has the same constructional elements except that a drain electrode pattern46is formed to have an annular shape along the periphery of the pixel electrode28. In this case, the drain electrode pattern46is formed in an annular shape and overlaps with the bottom periphery of the pixel electrode28; unlike the U-shaped drain electrode patterns36and42in FIG.2andFIG. 3, respectively.

The drain electrode pattern46prevents light from leaking between the pixel electrode28and the gate line24. The drain electrode pattern46is connected, via a contact hole48formed in a protective film on the drain electrode part46A, to the pixel electrode28. Accordingly, the contact hole for connecting the storage electrode part46B to the pixel electrode28can be eliminated to reduce a width or amount by which the pixel electrode28overlaps with the storage electrode part42B. This then prevents a short between the upper and lower pixel electrodes28.

Alternatively, the drain electrode pattern46may be connected to the pixel electrode28by forming a contact hole (not shown) in the protective film on the storage electrode part46B. In this alternative, the contact hole for connecting the drain electrode part46A of the drain electrode pattern46to the pixel electrode28can be eliminated to reduce to the size of the drain electrode part46A, to increase an effective size of the pixel electrode28while reducing an area of the pixel electrode28overlapping the drain electrode part46A, and to thus increase an aperture ratio of liquid crystal cell. The drain electrode pattern46is also uniformly spaced from the data line26to uniformly maintain a parasitic capacitor Cds between the drain electrode26and the drain electrode pattern46. Therefore, a deterioration of the data signal caused by a non-uniformity of the parasitic capacitor Cds is prevented.

The thin film transistor substrate ofFIG. 4is formed by the same method as described with respect toFIG. 2, except for patterning certain layers to achieve the above noted structural differences.

Referring toFIG. 5, there is shown an electrode arrangement of a thin film transistor substrate in a liquid crystal display according to a fourth embodiment of the present invention. When compared with the thin film transistor shown inFIG. 3, the thin film transistor substrate ofFIG. 5has the same constructional elements except that a drain electrode pattern50is electrically connected, via contact holes52and54, to the pixel electrode28at a drain electrode part50A and a storage electrode part50B, respectively. The drain electrode pattern50is electrically connected, via the contact hole52formed in a protective film on the drain electrode part50A, to the pixel electrode28and, at the same time, is electrically connected, via the contact hole54formed in a protective film on the storage electrode part50B, to the pixel electrode28. Also, the drain electrode pattern50and the data line26are formed from the same conductive layer during processing and at a constant separation interval to uniformly maintain a parasitic capacitor Cds between the drain electrode26and the drain electrode pattern50. Therefore, a deterioration of the data signal caused by a non-uniformity of the parasitic capacitor Cds is prevented.

The thin film transistor substrate ofFIG. 5is formed by the same method as described with respect toFIG. 2, except for patterning certain layers to achieve the above noted structural differences.

As described above, according to embodiments of the present invention, the drain electrodes are connected to the storage electrodes in a manner to reduce the number of contact holes, increase an aperture ratio, and prevent shorts between pixel electrodes. Also, a space between the data line and the drain electrode pattern connected to the pixel electrode becomes consistent to maintain a uniform parasitic capacitor Cds and prevent deterioration of the data signal caused by a non-uniformity of the parasitic capacitor Cds.