Time-based wafer de-chucking from an electrostatic chuck having separate RF BIAS and DC chucking electrodes

An electrostatic chuck in a reactor chamber has a cathode electrode insulated from ground, a chucking electrode insulated from the cathode electrode and a dielectric layer overlying the chucking electrode that provides a workpiece support surface. A D.C. chucking voltage supply is coupled to the chucking electrode. An RF power generator is coupled to the cathode electrode. A voltage sensing apparatus is coupled to the chucking electrode and to the cathode electrode to monitor the voltage difference between them during discharge after removal of RF and DC power at the conclusion of processing. The reactor includes a controller programmed to raise the lift pins during electrode discharge as soon as the voltage sensing apparatus detects equal voltages simultaneously on the chucking and cathode electrodes.

BACKGROUND

Electrostatic chucks are used for holding a workpiece in various applications ranging from holding a sheet of paper in a computer graphics blotter to holding a semiconductor wafer within a semiconductor fabrication process system. Although electrostatic chucks vary in design, they all are based on the principle of applying a voltage to one or more electrodes in the chuck so as to induce opposite polarity charges in the workpiece and electrode(s), respectively. The electrostatic attractive force between the opposite charges presses the workpiece against the chuck, thereby retaining the workpiece.

A problem with electrostatic chucks is the difficulty of removing the electric charge from the workpiece and the chuck when it is desired to release the workpiece from the chuck. One conventional solution is to connect both the electrode and the workpiece to ground to drain the charge. However, the charge trapped into the dielectric material cannot be drained freely. Another conventional solution, which purportedly removes the charge more quickly, is to reverse the polarity of D.C. voltage applied to the electrodes.

A shortcoming that has been observed with these conventional approaches to removing the electric charge is that they fail to completely remove the charge, so that some electrostatic force remains between the workpiece and the chuck. This residual electrostatic force necessitates the use of a large mechanical force to separate the workpiece from the chuck. When the workpiece is a semiconductor wafer, the force required for removal sometimes cracks or otherwise damages the wafer. Even when the wafer is not damaged, the difficulty of mechanically overcoming the residual electrostatic force sometimes causes the wafer to pop off the chuck unpredictably into a position from which it is difficult to retrieve by a conventional wafer transport robot. Wafer de-chucking is critical since it can impact particle generation and tool utilization should a wafer be broken or misplaced to the point where it requires that the chamber be opened to retrieve the wafer. These problems may be addressed by applying a de-chucking voltage to the chucking electrode to reduce or remove any residual electrostatic force holding the wafer when de-chucking the wafer. Determining the optimum de-chucking voltage is difficult.

The optimum de-chucking voltage provides for wafer lift-off without popping or significant robot corrections. Typically, an optimum de-chuck voltage is highly dependent upon the wafer characteristics and the plasma process conditions and the temperature of the electrostatic chuck.

The approach of the prior art was to apply a special de-chucking voltage when lifting off the wafer in order to counteract the residual chucking force and thereby avoid wafer breakage.

The foregoing methods are limited because the application and determination of an optimum de-chucking voltage varies among different plasma process conditions and different wafer designs and different electrostatic chuck designs. What is generally desired now is a de-chucking method that minimizes the residual chucking force upon wafer lift-off, regardless of variations in plasma process conditions, wafer characteristics and electrostatic chuck properties.

SUMMARY

A plasma reactor is provided for processing a workpiece. In one aspect, the reactor includes a vacuum chamber including an RF grounded chamber wall and a process gas disperser coupled to the chamber. An electrostatic chuck is disposed in the chamber and includes a cathode electrode insulated from ground. A chucking electrode overlies the cathode electrode and is insulated from the cathode electrode. A dielectric layer overlies the chucking electrode, wherein the dielectric layer has a top surface that can support a workpiece to be processed and lift pins. A D.C. chucking voltage supply is coupled to the chucking electrode. An RF power generator is coupled through the RF impedance match to the cathode electrode. Voltage sensing apparatus is coupled to the chucking electrode and to the cathode electrode to monitor the voltage difference between them during discharge and after removal of RF and DC power at the conclusion of plasma processing. The reactor further includes a controller programmed to raise the lift pins during electrode discharge as soon as the voltage sensing apparatus detects equal voltages simultaneously on the chucking and cathode electrodes.

A first D.C. discharge path having a first resistance is provided through the D.C. chucking voltage supply from the chucking electrode to ground. A second D.C. discharge path having a second resistance is provided through the RF impedance match from the cathode electrode to ground. The first and second resistances provide unequal electrical discharge time constants in the first and second D.C. discharge paths to ensure a crossover of the two electrode voltages during discharge. The chucking electrode typically has the higher initial voltage at the beginning of discharge and therefore its discharge path is provided with the faster (smaller) RF time constant.

To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. The drawings in the figures are all schematic and not to scale.

DETAILED DESCRIPTION

There is data indicating the relationship between the D.C. power supply current spikes observed during chucking or de-chucking and the optimum de-chucking voltage. It is observed that a D.C. current spike is seen at the D.C. chucking supply when the wafer is placed on or removed from the electrostatic chuck. For the spike observed during wafer chucking, it is believed the spike arises from the accumulation of charge in the electrostatic chuck insulator layer separating the wafer from the chucking electrode. When the plasma and D.C. chucking voltage are turned off at the end of wafer processing, this charge remains, and is the likeliest source of a residual chucking force holding the wafer to the chuck.

FIG. 1illustrates an electrostatic chuck (ESC)100for electrostatically clamping in place a workpiece such as a semiconductor wafer during processing in a plasma reactor chamber.FIG. 2depicts the deployment of the ESC100ofFIG. 1in a capacitively coupled plasma reactor chamber andFIG. 3depicts the deployment of the ESC100ofFIG. 1in an inductively coupled plasma reactor chamber. The ESC ofFIG. 1is of the type having an RF-“hot” (floating) cathode105for coupling RF bias power into the chamber and a separate chucking electrode110for coupling a D.C. chucking voltage to the wafer. The chucking electrode110may be a thin conductor or mesh structure. The ESC ofFIG. 1includes an insulating or dielectric base layer115underlying the cathode105. An intermediate dielectric layer120separates and insulates the cathode105and chucking electrode110from one another. A very thin top dielectric layer125overlying the chucking electrode110has a top surface125aon which a workpiece such as a semiconductor wafer130may be held during plasma processing in the chamber. The wafer130is lowered onto the support surface125aand raised from the support surface125aby a set of electrically conductive lift pins135supported on a movable lift spider140, which may also be electrically conductive. A lift servo142raises and lowers the lift spider140under control of a programmable controller144. The controller144also controls the D.C. chucking voltage supply160, so that the controller144can govern the wafer chucking and de-chucking operation. The lift pins135are electrically connected to the floating cathode105(as indicated schematically inFIG. 1by the dashed line wire145). In this way, there is no potential difference between the lift pins135and the cathode105, thereby permitting the lift pins135to be at least partially raised (e.g., to the position depicted inFIG. 1) without risk of arcing between the lift pins135and the cathode105. RF bias power is applied to the cathode105from an RF bias power generator150through an RF impedance match circuit155. The bias power may contribute significantly to ion energy in the plasma sheath, and the RF bias power generator150may have a frequency lying in the LF to HF frequency range, or sufficiently low for ions to follow the oscillations of the bias power.

A D.C. wafer chucking voltage is applied to the chucking electrode110from a D.C. voltage source160to produce a desired electrostatic clamping force on the wafer130. The insulator layer125lying between the chucking electrode110and the wafer130has a limited conductance, e.g., a resistance on the order of 30 megaOhms. This promotes charge mobility in the thin insulator layer125(and a low D.C. current through the insulator layer125) in the manner of a Johnson-Raybeck ESC, so that static charge induced by a D.C. chucking voltage from the D.C. supply160is free to move through the insulator layer125to accumulate at the surface facing the wafer130. The resulting close proximity of the static charge in the insulator layer125to the wafer130greatly increases the electrostatic clamping force for a given D.C. chucking voltage, thereby reducing the chucking voltage required to attain a desired electrostatic clamping force.

In the reactor ofFIG. 2, the ESC100is inside the chamber170of a capacitively coupled plasma reactor, the chamber170defined by a cylindrical side wall175and an overhead ceiling electrode/gas distribution plate180. Optionally, the ESC100is separated from the floor of the chamber enclosure by a layer165which may be a metal or a dielectric material. A process gas supply185provides process gas to the ceiling electrode/gas distribution plate180. An RF plasma source power generator190provides RF plasma source power to the overhead electrode180through an RF impedance match element195. For efficient production of ions, the frequency of the RF plasma source power generator may be a VHF frequency. A vacuum pump192evacuates the chamber170through a pumping annulus194defined between the ESC100and the side wall175.

In the reactor ofFIG. 3, the ESC100is inside the chamber170of an inductively coupled plasma reactor, the chamber170defined by a cylindrical side wall175. A process gas supply185provides process gas for injection into the chamber. An RF plasma source power generator190provides RF plasma source power to an overhead coil antenna200through an RF impedance match element195. For an inductively coupled source, the RF plasma source power generator may be an HF frequency, for example. A vacuum pump192evacuates the chamber170through a pumping annulus194defined between the ESC100and the side wall175.

In the reactor ofFIG. 2and in the reactor ofFIG. 3, the RF source power coupled into the chamber from the source power generator190produces plasma ions. The voltage of the plasma relative to ground follows an RF waveform as depicted inFIG. 4. If only the source power generator190is active, then the waveform of the plasma voltage ofFIG. 4is a sine wave having a frequency equal to that of the source power generator190. If only the bias power generator150is active, then the waveform of the plasma voltage ofFIG. 4is a sine wave having a frequency equal to the frequency of the bias power generator150. If both generators150,190are active, then the plasma voltage may be a composite waveform, depending upon the frequencies of the two RF generators150,190. In the absence of the source power generator190, plasma ions are generated by the RF power applied from the RF generator150to the cathode105. In this case, the plasma voltage relative to ground oscillates with the RF voltage from the RF generator150.

Ions in the plasma, which have a large mass-to-charge ratio, do not easily follow the oscillation of the plasma voltage ofFIG. 4, while the electrons do follow the oscillation. During the least negative portions of the plasma voltage waveform ofFIG. 4, plasma electrons flow from the plasma to the wafer130(and other portions of the chamber) across a sheath or boundary between the plasma and interior surfaces such as the surface of the wafer130. Ion flux across the sheath does not appreciably change over the cycles of the plasma voltage ofFIG. 4. The oscillating plasma voltage waveform ofFIG. 4has a negative D.C. component (referred to as an RF bias voltage) arising from a negative sheath charge on all plasma-exposed surfaces in the chamber, this charge being equivalent to the volume electron charge loss generated in the sheath.

FIG. 5depicts a simplified equivalent circuit or model of the ESC100ofFIG. 1. The RF bias voltage (or D.C. component) of the RF plasma potential ofFIG. 4creates voltage drops across all impedance components between the plasma and ground. In the equivalent circuit ofFIG. 5, these components are modeled as capacitances in series. InFIG. 5, the capacitance across the plasma sheath between the plasma and the wafer130is labeled C1. The capacitance across the insulator layer125is so great (due to the thinness of this layer) that the RF voltage drop across the insulator layer125is negligible, and therefore this capacitance is not modeled in the equivalent circuit ofFIG. 5. The capacitance across the insulator layer120between the chucking electrode110and the cathode105is labeled C2inFIG. 5. The capacitance between the cathode105and ground is labeled C3inFIG. 5.

The RF voltage or electrical potential of the plasma (FIG. 4) produces a voltage on the chucking electrode110and on the wafer130in accordance with RF voltage drops across the capacitances C1, C2, C3in the schematic model ofFIG. 5. The RF voltage of the plasma (FIG. 4) has a D.C. component or bias voltage (labeled as such inFIG. 4) that contributes to the D.C. potentials of the wafer130and chucking electrode110. Because of the negligible RF voltage drop across the thin insulator layer125, the wafer130and chucking electrode110have essentially the same RF bias or D.C. component voltage. The D.C. chucking voltage from the D.C. supply160is superimposed on the bias voltage of the chucking electrode110. The series of capacitances C1, C2, C3act as RF voltage dividers so that a portion of the D.C. bias of the RF plasma voltage appears across the plasma-wafer sheath capacitance C1(placing the chucking electrode110at a first D.C. potential) while another portion of the D.C. bias of the RF plasma voltage appears across the mesh-cathode capacitance C2(placing the cathode105at a second D.C. potential generally closer to ground than the first potential). As a result, the chucking electrode110and the cathode105are at different D.C. bias voltage potentials during the plasma process. Any D.C. voltage applied by the D.C. chucking voltage supply160to the chucking electrode110contributes to this difference.

When the wafer130is to be de-chucked, or lifted off the ESC100, the RF power generators150,190are turned off or disconnected, the D.C. power supply160is turned off (or reduced) and the lift pins135are raised until they contact the wafer130. The lift pins are at the voltage of the cathode105, which is below the voltage of the wafer130/chucking electrode110combination. Therefore, when the lift pins135contact the wafer130, there is a current spike observed at the chucking voltage supply160determined by the cathode-to-mesh voltage difference, the mesh-to-cathode capacitance C2and other factors. The magnitude of this spike is indicative of the residual clamping force existing at the time the RF power and DC voltage are removed.

FIG. 6illustrates contemporaneous waveforms of the chucking electrode voltage and the cathode voltage. The chucking electrode voltage is the sum of the bias or D.C. component of the RF voltage drop at the chucking electrode110(“Vrfbias” inFIG. 6) and the D.C. voltage output by the D.C. chucking voltage supply160(“Vdcsupply” inFIG. 6). Therefore, the voltage difference between the cathode105and chucking electrode110is attributable to both (a) the RF voltage difference between them and (b) the D.C. chucking voltage applied to the chucking electrode110by the D.C. supply160. As depicted in the graph ofFIG. 6, during plasma processing (from time0to time T1), the average or D.C. component of the voltage on the cathode105(“Vdccathode” inFIG. 6), is generally constant during plasma processing. During this same period, the RF bias or D.C. component of the voltage of the chucking electrode110, Vrfbias, is fairly constant but (as indicated inFIG. 6) experiences fluctuations over time due to its closer proximity to the plasma. These fluctuations are relatively small, in that they do not generally cause the chucking electrode voltage to fall below the cathode voltage.

Optionally, for accurate control of the electrostatic clamping force, compensation for such fluctuations may be provided by varying the output of the D.C. supply160during plasma processing in a manner that complements the fluctuations in the D.C. component of the RF voltage on the wafer130or mesh110. For this purpose, a wafer voltage measurement processor300constantly measures the RF bias (D.C. component) voltage on the wafer130(which is essentially the same as that of the chucking electrode110), based upon output signals from a sensor310at the RF impedance match155. Such a measurement may be made in accordance with U.S. patent application Ser. No. 10/440,364 filed May 16, 2003 by Daniel Hoffman entitled PLASMA DENSITY, ENERGY AND ETCH RATE MEASUREMENTS AT BIAS POWER INPUT AND REAL TIME FEEDBACK CONTROL OF PLASMA SOURCE AND BIAS POWER and assigned to the present assignee. A feedback controller320uses the output of the wafer voltage processor300to vary the output level of the D.C. voltage supply160so as to compensate for fluctuations in the RF bias voltage and thereby maintain a more constant chucking electrode voltage. An example of such compensation is depicted in dashed line inFIG. 6. As stated above, the dashed line curve labeled inFIG. 6“Vrfbias” is the D.C. component of the RF voltage on the chucking electrode110(which is about the same as that on the wafer130) as sensed by the measurement processor300. The dashed line curve labeled “Vdcsupply” inFIG. 6is the output of the D.C. supply160. The sum of Vrfbias and Vdcsupply is the D.C. voltage on the chucking electrode110(“Vmesh” ofFIG. 6). Vmesh is constant because of the offsetting variations in Vrfbias and Vdcsupply.

Referring again toFIG. 6, the voltages on the cathode105and chucking electrode110, namely Vcathode and Vmesh, decay after the removal of RF power and removal of the D.C. chucking voltage at time T1. A voltage difference between them possibly can persist for an indefinite period of time, as indicated in the example depicted in the graph ofFIG. 6. This voltage difference produces a residual wafer clamping force that can prevent safe de-chucking or lift-off of the wafer130from the ESC100by the lift pins135. The delay represented by the persistence of this voltage difference impairs throughput and productivity.

An accurate method for de-chucking the wafer130with a minimum (or zero) residual chucking force is provided. One element of this method involves a selection of the D.C. discharge path characteristics (i.e., electrical discharge times) of the two electrodes105,110. This selection is made by providing a selected resistance to ground for the cathode105through the RF impedance match155, and by providing a selected resistance to ground for the chucking electrode110through the D.C. voltage supply160. These resistances are indicated schematically in dashed line inFIG. 1, including a resistance Rcathode through the RF impedance match155and a resistance Rmesh through the D.C. supply160. In addition, the selection of the discharge characteristics of the cathode105and chucking electrode110may further involve a selection of the capacitance of the chucking electrode110and a selection of the capacitance of the cathode105(among other things).

The resistances Rcathode and Rmesh, along with the mesh-to-cathode capacitance C2and the cathode-to-ground capacitance C3, determine the RC decay constants for each of the electrodes105,110(controlling the discharge that occurs after time T1ofFIG. 6) such that their exponentially decaying voltages will cross over one another for a brief instant at some time after T1. The situation is depicted in the graph ofFIG. 7. As shown inFIG. 7, the voltage of the chucking electrode110at time T1starts out higher than the voltage of the cathode105at time T1. Their RC exponential decay time constants, RcathodeC3and RmeshC2, are selected so that the chucking electrode voltage (which is initially the higher of the two) decays faster than the cathode voltage beginning at time T1. This condition enables the two voltages to cross over one another (become equal to one another for a brief instant in time) at time T2. The interval from time T1to time T2is determined by the difference between the RC exponential decay time constants of the cathode105and the chucking electrode110. Specifically, in one implementation, the capacitances C2and C3were not modified, but the discharge path resistances Rcathode, Rmesh through the impedance match155and the D.C. supply160, respectively, were selected so that the discharge resistance for the chucking electrode, Rmesh, was on the order of about 1% of the discharge resistance for the cathode, Rcathode. For example, Rmesh, the D.C. resistance to ground for the chucking electrode110through the D.C. supply160was 1 megOhm, while Rcathode, the D.C. resistance to ground for the cathode105through the impedance match155was 100 megOhms. These choices were realized by adjusting the circuit designs of the D.C. supply160and of the impedance match155using conventional techniques well-known in the art.

The decay and cross-over of the mesh and cathode voltages is depicted in the log scale graph ofFIG. 8. Each of the two electrode voltages V(t) is a function of time starts out at time T1(power off) at an initial voltage V0and decays over time in accordance with the well-known relationship V(t)=V0(1−e−t/RC). In the case of the cathode voltage, V0is the initial cathode voltage at time T1, R is the D.C. resistance to ground through the impedance match and C is the cathode capacitance C3. In the case of the chucking electrode voltage, V0is the initial chucking electrode voltage at time T1, R is the D.C. resistance to ground through the D.C. power supply160and C is the chucking electrode-to-cathode capacitance C2. In the log scale ofFIG. 8, the decay behaviors of the two voltages are straight lines whose slopes are given by (RC)−1.

At the instant in time, T2, when the two electrode voltages cross over one another, the residual electrostatic clamping force on the wafer130is minimum (or possibly zero), and the lift pins135should be moved to lift the wafer130off the ESC100at that instant. Of course, the interval between times T1and T2is generally unknown or can only be predicted with difficulty. Therefore, in one embodiment, means is provided for sensing in real time the occurrence of the crossover between the two decaying electrode voltages ofFIG. 7. For this purpose, a chucking electrode voltage sensor210monitors the mesh voltage after time T1while a cathode voltage sensor220monitors the cathode voltage after time T1. In one embodiment, both sensors210,220measure voltage relative to ground. The output of the two sensors210,220over time corresponds to the two curves in the graph ofFIG. 7. A comparator230constantly compares the outputs of the two sensors210,220, and senses the occurrence of the cross-over at time T2when the outputs are equal. The controller144is programmed to command the lift servo142to lift the wafer130up from the ESC100the instant the comparator230senses an equality between the outputs of the two sensors210,220. For this purpose, and in order to ensure precise timing of the wafer liftoff, before time T2the lift pins135are raised so as to contact the wafer130but not lift it off the ESC100. Then, when the lift pins135are further moved up at time T2, the wafer is lifted off the ESC100at that precise instant, ensuring the minimum residual electrostatic clamping force exists at the time of wafer de-chucking.

The foregoing embodiment is ideal for retrofitting existing plasma reactors, because this embodiment achieves the minimum residual electrostatic clamping force at the time of wafer de-chucking or lift-off without reference to any prior knowledge of characteristics of the ESC or plasma chamber design. What is required is that the D.C. resistances to ground provided through the D.C. voltage supply160and the RF impedance match155be adjusted so that the electrode (e.g., the chucking electrode) having the higher initial voltage at time T1has a faster discharge rate than the electrode (e.g., the cathode) having the lesser initial voltage. This feature can be easily retrofitted into a typical plasma reactor already deployed in commercial use. For a non-typical chamber in which the relationship of the initial electrode voltages is reversed (i.e., the initial cathode voltage at time T1is greater than the chucking electrode voltage at time T1), the discharge characteristics would likewise be reversed. Specifically, the cathode electrode105would have a faster discharge rate (smaller RC constant) than the chucking electrode110.

For greater through-put or better productivity, the interval between time T1(power off) and time T2(wafer liftoff) can be shortened. This is accomplished by programming the controller144to have the D.C. voltage supply160apply a particular constant voltage Vdechuck to the chucking electrode110beginning at time T1. The voltage Vdechuck should be of a polarity opposite to that of the D.C. chucking voltage that was applied during plasma processing, and of a magnitude that is smaller than (e.g., a fraction of) the D.C. chucking voltage. This approach is illustrated in the timing diagram ofFIG. 9, in which a positive D.C. chucking voltage was applied during plasma processing from time T0to time T1. Thereafter, at time T1, a negative voltage Vdechuck is applied that, as can be seen inFIG. 9, moves the initial chucking electrode voltage closer to the initial cathode voltage. This change shortens the interval between times T1and T2. In the example ofFIG. 9, the magnitude of Vdechuck is limited so that the chucking electrode voltage is moved about halfway from its initial value toward the initial cathode voltage. This limitation is important in order to avoid an over-correction at time T1in which the initial mesh voltage is driven below the initial cathode voltage. In one embodiment, the voltage Vdechuck applied by the D.C. voltage supply beginning at time T1to the chucking electrode160is of the opposite polarity and about one half the magnitude of the D.C. chucking voltage applied during plasma processing prior to time T1. Comparing in the qualitative examples ofFIGS. 7 and 9, the delay from time T1(power off) to time T2(wafer dechuck) is greatly reduced. This reduction may be as much as a factor of two, for example.

FIG. 10depicts a method in accordance with one embodiment. The first step is to select a resistance Rmesh of the chucking electrode D.C. discharge path and capacitance C2of the chucking electrode110(block250ofFIG. 10). Also, a selection is made of the resistance Rcathode of the cathode D.C. discharge path and capacitance C3of the cathode105(block255ofFIG. 10). These selections are made to provide a faster RC decay time (smaller value of RC) for the electrode that will have the largest voltage at time T1when RF and D.C. power is turned off. In the embodiments disclosed in this specification it is the chucking electrode110that has the largest initial voltage at power off (time T1) and therefore requires the faster discharge path (smaller value of RC). A wafer is placed on the ESC100and plasma processing is carried out, during which RF power is applied (e.g., to the cathode105) and a D.C. chucking voltage is applied to the chucking electrode110. After completion of plasma processing (at time T1), but before the wafer is lifted from the ESC, the RF power generators150,190are disconnected or turned off and the D.C. supply160is turned off (block260ofFIG. 10). In an alternative embodiment, at this step the output of the D.C. power supply160is switched to an opposite polarity and a smaller magnitude (e.g., a fraction of the chucking voltage applied during plasma processing). Beginning at power-off (time T1), the chucking electrode voltage is monitored (block265ofFIG. 10) and the cathode voltage is monitored (block270ofFIG. 10). When the two voltages being monitored cross over one another (become equal for an instant in time), the lift pins are raised to instantly lift off the wafer from the ESC (block275ofFIG. 10). For this purpose, the lift pin135may have been previously raised into contact with the wafer backside to ensure immediate lift off of the wafer upon lift pin actuation at time T2(cross over of the two electrode voltages).

In one embodiment, the difference between the RC time constants of the cathode105and the chucking electrode110may be sufficiently great to realize crossover of their voltages during the discharge step very quickly, so as to minimize the time delay between T1and T2, to ensure a minimum delay between plasma process complete and wafer dechucking. The difference between the two RC time constants may be such that the delay from time T1(plasma process termination and discharge initiation) to time T2(wafer dechucking) is on the order of minutes or less than a minute, or less than one second or less than a tenth of one second, for example.

In the foregoing examples, the D.C. chucking voltage applied by the D.C. supply160to the chucking electrode110was a positive voltage. However, the chucking voltage may instead be a negative voltage. In such a case, if a dechucking voltage were applied in order to shorten the waiting interval between times T1and T2, then the dechucking voltage would be a positive voltage. Different effects are obtained depending upon the polarity of the chucking voltage. For example, use of a positive D.C. chucking voltage during wafer processing (from time0to time T1) tends to wear or strain grounded conductive elements in the chamber, but puts little wear or strain on floating or RF-hot components, such as the wafer. Use of a negative D.C. chucking voltage during wafer processing tends to strain RF-hot components in the chamber, such as the wafer. The chucking voltage may be a positive or negative voltage between, typically but not necessarily, 300 VDC and 1000 VDC. The de-chucking voltage (if one is employed) may be between zero and 100 volts of a polarity opposite to that of the chucking voltage, and more typically between about 30 and 50 VDC. For retrofitting an existing reactor in the field, it is more simple and reliable to not apply a dechucking voltage.