NRZI processing methods and devices to correct for sync detection failures

New and useful methods and systems for detecting sync signals/patterns in streams of data are disclosed. For example, in an embodiment system for processing data includes a first module having dedicated processing circuitry configured to detect a sync signal embedded in a received stream of data and to produce an output stream of data, and second module that includes a firmware-controlled processor configured to correct sufficient errors within the received stream of data so as to allow the first module to detect the sync signal on a condition when the first module by itself is incapable of resolving the sync signal caused by the errors in the received stream of data.

INCORPORATION BY REFERENCE

This application claims the benefit of U.S. Provisional Application No. 61/540,427 entitled “Firmware processing of nrzi data to handle uncorrectable decoding errors caused by hardware sync detection failure” filed on Sep. 28, 2011, the content of which is incorporated herein by reference in its entirety.

BACKGROUND

Communication and data storage systems rely on any of a variety of encoding systems. For example, optical disc readers use NRZI (non-return to zero, inverted) coding in which 1's are represented by a first type condition, e.g., a change in voltage/state at a clock boundary, and 0's are represented by some other type condition, e.g., no change in voltage/state at a clock boundary. Unfortunately, such systems are susceptible to timing issues. For instance, a sync detection loss of an input stream of data from an optical disc will lead to large numbers of detected errors even though the input data stream actually contains very few actual data errors.

SUMMARY

In an embodiment, a system for processing data includes a first module having dedicated processing circuitry configured to detect a sync signal embedded in a received stream of data and to produce an output stream of data, and a second module that includes a firmware-controlled processor configured to correct sufficient errors within the received stream of data so as to allow the first module to detect the sync signal on a condition when the first module by itself is incapable of resolving the sync signal caused by the errors in the received stream of data.

In another embodiment, a method for processing data is disclosed. The method includes performing first processing using only dedicated processing circuitry configured to detect a sync signal embedded in a received stream of data to produce an output stream of data, and when the first processing is incapable by itself of resolving the sync signal due to errors in the received stream of data, performing second processing using a firmware-controlled processor to correct sufficient errors within the received stream of data so as to allow the first module to detect the sync signal.

DETAILED DESCRIPTION OF EMBODIMENTS

The disclosed methods and systems below may be described generally, as well as in terms of specific examples and/or specific embodiments. For instances where references are made to detailed examples and/or embodiments, it is noted that any of the underlying principles described are not to be limited to a single embodiment, but may be expanded for use with any of the other methods and systems described herein as will be understood by one of ordinary skill in the art unless otherwise stated specifically.

FIG. 1Adepicts an input data stream210provided by a BluRay Disc (BD) and used by the BD storage system100ofFIG. 2as will be explained below. The optical data stream210includes frames of date with each frame including payload data212of 1932 bits and a sync signal214.

For the purpose of this disclosure, the period between sync signals214, i.e., the period between time TAand time TB, is to be considered a “frame” of data. Also for the purpose of this disclosure, a “sync signal” is defined as any pattern of bits that a given system or processing standard uses to determine timing, e.g., frame boundaries.

FIG. 1Bdepicts details of a portion of the periodic sync signals214including a BD sync identification (ID)220having a known and predictable sequence, and a 9T/9T standard sync pattern230having nine NRZI “1's” followed by nine NRZI “0's” noting that the length of payload data and the format of a sync signal can change from example to example depending on the particular data standard employed. For example, an example CD reading system would employ payload data of 588 bits/frame and an 11T/11T sync signal.

In practice, encoded data can be correctly decoded once the location of an embedded sync signal/pattern is identified assuming that the number of errors in the data stream is lower than those that are correctable by an Error Correction Code (ECC) decoder.

However, if the sync signal location is incorrectly identified, then most of the data provided by the ECC decoder will be incorrect and uncorrectable even in situations where the bulk of the NRZI data is error free. If such a scenario is caused by a particular hardware-implemented sync detection, then it is possible to correct for the problem by using a firmware-based solution to flexibly pre-process the NRZI encoded data to remove bit errors before re-processing using the hardware-implemented sync detection. Such a firmware/hardware hybrid system enables flexible error-correction where a hardware-only approach having the same capacity would be too complex and expensive.

The following examples of the disclosed methods and systems are directed to an enhanced BluRay (BD) optical disc reading system employing NRZI encoding. However, it is to be appreciated in light of this disclosure that the following concepts may be applied to a large variety of other systems using NRZI or other encoding techniques, such as Digital Video Disc (DVD) readers, Compact Disc (CD) readers, other optical reading systems, magnetic and other storage systems, communication systems, and any other known or later developed data storage or transfer system capable of using data encoding and sync signals.

FIG. 2is an example of a BD storage system100capable of employing frames of NRZI encoded data and sync signals, such as those data and sync signals described above and depicted inFIGS. 1A and 1B. The storage system100includes a data source110, a data channel120, an enhanced optical disc controller (ODC)130, error correction coding (ECC) circuitry140, and a data sink150. The enhanced optical disc controller130includes a firmware (FW) module132, a hardware (HW) module134, and demodulator (DEMOD) circuitry136.

In operation, the example data source110, which may be a BluRay Disc, provides a stream of input data to the data channel120, which in turn provides the stream of input data to the enhanced ODC130. For the purpose of this example, the input data stream is formatted according to BluRay specifications using non-return to zero, inverted (NRZI) coding having frames of length 1932 bits with 9T/9T sync signals as is shown in greater detail inFIGS. 2A-2Bdiscussed above.

The enhanced ODC130processes the received input data stream using fast (but limited) dedicated/fixed hardware circuitry incorporated in the HW module134and, when necessary, by more versatile (but slower) firmware-based processing using the FW module132to produce a stream of processed data and sync timing signals.

The stream of processed data is then provided to the ECC circuitry140to produce a stream of corrected data, which in turn is provided to the data sink150.

FIG. 3shows details of the example enhanced optical disc controller130ofFIG. 2. Again, the example enhanced optical disc controller130includes a FW module132, and a HW module134and DEMOD circuitry136, as well as disc control circuitry310.

In operation, input/received data, e.g., NRZI encoded data having frames that include payload data of 1932 bits and a sync signal having a sync ID and 9T/9T sync pattern, is provided to the FW module132.

In normal operation, the input/received data will pass through the FW module132to the HW module134unchanged to the HW module134where after the HW module134will process the received data while attempting to detect embedded sync signals.

Should the HW module134successfully detect a sync signal, which includes successfully detecting a correct sync ID followed by a 9T/9T pattern, then the HW module134will provide processed data to the DEMOD circuitry136, while providing a successful SYNC STATUS signal to the disc control circuitry310and to the FW module132.

However, should the HW module134fail to successfully detect a sync signal, then the HW module134will provide an unsuccessful SYNC STATUS signal to the disc control circuitry310and to the FW module132. Such an unsuccessful SYNC SIGNAL can cause the disc control circuitry310to re-read the last frame(s) of data, and cause the FW module132to intercept such re-read frame(s) of data and pre-process such data. In varying examples, such pre-processing by the FW module132can completely correct (or at least compensate for) a given frame of data, or may only partially correct a given frame allowing the HW module134to complete data correction and/or sync detection.

The FW module132is capable of flexibly detecting sync signals in the face of bit errors beyond the capability of the HW module134to resolve, although at a slower rate that makes full-time processing by the FW module132impracticable.

In various examples, the FW module132can perform at least the following non-limiting processes:

(1) Insert or delete bits on short frames assuming that the HW module134cannot correctly process/adjust. For example, should a particular frame of data be three bits too short (i.e., 1929 bits), the FW module132can pad the short frame and pass the padded frame to the HW module134.

(2) Fix erroneous sync IDs assuming that the HW module134cannot correctly identify the proper sync ID by itself.

(3) Insert/delete frames when a write overwrite/gap longer than a “few bits” exists assuming that the actual data inserted is not critical as long as sufficient bits, sync patterns and sync ID are inserted so that the hardware implementation can correctly decode the ECC block/cluster.

Typically, the meaning of a “few bits” can vary depending on the optical standard used. However, for the purpose of this disclosure, a “few bits” can be defined as the maximum number of erroneous bits for which a hardware-based processor can successfully compensate. This, of course, may be a design choice with an observation that the more bits that a hardware-based processor is designed to resolve, the more expensive the hardware-based processor is likely to be. Similarly, the term “sufficient bits” may be defined as the number of bits needed to be added/removed for which a hardware-based processor can then successfully compensate.

(4) Fix erroneous sync patterns assuming that sufficient information is available to pinpoint an exact location of such a pattern, and when not detecting such pattern affects the demodulated data in such a manner that it leads to failures or errors on that frame.

FIG. 4shows details of the example FW module132ofFIG. 3. As shown inFIG. 4, the FW module132includes switch S1and a processor410with firmware memory420enabling flexible, if relatively slow, error correction and/or sync detection.

In operation, the FW module134receives the stream of input data as described above, and provides such stream of received data to switch S1and to the processor410.

Assuming that SYNC STATUS signal indicates that a respective HW module can successfully resolve/detect an embedded sync signal, then the processor410will command switch S1to pass the received stream of data through to the HW module as signal I/C DATA (“Input or Corrected DATA”).

However, should the SYNC STATUS signal indicate that the respective HW module cannot successfully resolve/detect an embedded sync signal, then the processor410will perform the appropriate pre-processing to the input data to produce firmware corrected/compensated data, and command switch S1to pass the firmware corrected data to the HW module as signal I/C DATA.

FIG. 5is a flowchart outlining an example approach for detecting sync errors in a stream of encoded frames of data. The process starts at S502when a received data stream containing a frame of NRZI (or other) encoded data, including payload data and sync signal, is received. Next, at S504, dedicated hardware-based processing is performed to detect the sync signal within the received stream of data.

At S510, a determination is made as to whether the sync signal was correctly detected/resolved at S504. If the sync signal was correctly detected/resolved, then at S550the hardware-processed data produced at S504(with sync timing) is output to an error correction device; otherwise, control continues to S512where a firmware-based processing device is used to pre-process the received data stream of S502so as to correct for errors in the that the hardware-based processing at S504cannot.

At S514, a firmware-corrected stream of data produced at S512is provided to the hardware module so as to allow the hardware module to further process the firmware-corrected stream of data so as to correctly/accurately detect the timing of the embedded sync signal. Then, at S516, dedicated hardware-based processing (similar or identical to that at S504) is performed on the pre-processed data stream to detect the sync signal within the firmware pre-processed data stream. Control then jumps back to S550where the processed data (with sync timing) is output to an error correction device.

While the invention has been described in conjunction with the specific embodiments thereof that are proposed as examples, it is evident that many alternatives, modifications, and variations will be apparent to those skilled in the art. Accordingly, embodiments of the invention as set forth herein are intended to be illustrative, not limiting. There are changes that may be made without departing from the scope of the invention.