Memory array for increased bit density

A memory array having a plurality of resistance variable memory units and method for forming the same are provided. Each memory unit includes a first electrode, a resistance variable material over the first electrode, and a first second-electrode over the resistance variable material. The first second-electrode is associated with the first electrode to define a first memory element. Each memory unit further includes a second second-electrode over the resistance variable material. The second-second electrode is associated with the first electrode to define a second memory element.

FIELD OF THE INVENTION

The invention relates to the field of random access memory (RAM) devices formed using a resistance variable material.

BACKGROUND OF THE INVENTION

Resistance variable memory elements, which include Programmable Conductive Random Access Memory (PCRAM) elements using chalcogenides, have been investigated for suitability as semi-volatile and non-volatile random access memory devices. A typical chalcogenide resistance variable memory element is disclosed in U.S. Pat. No. 6,348,365 to Moore and Gilton.

In a typical chalcogenide resistance variable memory element, a conductive material, for example, silver, tin and copper, is incorporated into a chalcogenide glass. The resistance of the chalcogenide glass can be programmed to stable higher resistance and lower resistance states. An unprogrammed chalcogenide variable resistance element is normally in a higher resistance state. A write operation programs the element to a lower resistance state by applying a voltage potential across the chalcogenide glass and forming a conductive pathway. The element may then be read by applying a voltage pulse of a lesser magnitude than required to program it; the resistance across the memory device is then sensed as higher or lower to define two logic states.

The programmed lower resistance state of a chalcogenide variable resistance element can remain intact for an indefinite period, typically ranging from hours to weeks, after the voltage potentials are removed; however, some refreshing may be useful. The element can be returned to its higher resistance state by applying a reverse voltage potential of about the same order of magnitude as used to write the device to the lower resistance state. Again, the higher resistance state is maintained in a semi- or non-volatile manner once the voltage potential is removed. In this way, such an element can function as a semi- or non-volatile variable resistance memory having at least two resistance states, which can define two respective logic states, i.e., at least a bit of data.

One exemplary chalcogenide resistance variable device uses a germanium selenide (i.e., GexSe100−x) chalcogenide glass as a backbone. The germanium selenide glass has, in the prior art, incorporated silver (Ag) and silver selenide (Ag2+/−xSe) layers in the memory element.FIG. 1depicts an example of a conventional chalcogenide variable resistance element1. A semiconductive substrate10, such as a silicon wafer, supports the memory element1. Over the substrate10is an insulating material11, such as silicon dioxide. A conductive material12, such as tungsten, is formed over insulating material11. Conductive material12functions as a first electrode for the element1. An insulating material,13such as silicon nitride, is formed over conductive material12. A glass material51, such as Ge3Se7, is formed within via22.

A metal material41, such as silver, is formed over glass material51. An irradiation process and/or thermal process are used to cause diffusion of metal ions into the glass material51. A second conductive electrode61is formed over dielectric material13and metal material41.

The element1is programmed by applying a sufficient voltage across the electrodes12,61to cause the formation of a conductive path between the two electrodes12,61, by virtue of a conductor (i.e., such as silver) that is present in metal ion laced glass layer51. In the illustrated example, with the programming voltage applied across the electrodes12,61, the conductive pathway forms from electrode12towards electrode61.

A plurality of resistance variable memory elements can be included in a memory array. In doing so, it is desirable to provide a high density of memory elements.

BRIEF SUMMARY OF THE INVENTION

Exemplary embodiments of the invention provide a memory array having a plurality of resistance variable memory units and methods for forming the same. Each memory unit includes a first electrode, a resistance variable material over the first electrode, and a first second-electrode over the resistance variable material. The first second-electrode is associated with the first electrode to define a first memory element. Each memory unit further includes a second second-electrode over the resistance variable material. The second-second electrode is associated with the first electrode to define a second memory element.

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description, reference is made to various specific embodiments of the invention. These embodiments are described with sufficient detail to enable those skilled in the art to practice the invention. It is to be understood that other embodiments may be employed, and that various structural, logical and electrical changes may be made without departing from the spirit or scope of the invention.

The term “substrate” used in the following description may include any supporting structure including, but not limited to, a semiconductor substrate that has an exposed substrate surface. A semiconductor substrate should be understood to include silicon-on-insulator (SOI), silicon-on-sapphire (SOS), doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. When reference is made to a semiconductor substrate or wafer in the following description, previous process steps may have been utilized to form regions or junctions in or over the base semiconductor or foundation. The substrate need not be semiconductor-based, but may be any support structure suitable for supporting an integrated circuit, including, but not limited to, metals, alloys, glasses, polymers, ceramics, and any other supportive materials as is known in the art.

The term “resistance variable material” is intended to include materials that can change resistance in response to an applied voltage. Such materials include, as non-limiting examples, chalcogenide glasses, chalcogenide glasses comprising a metal, such as silver, tin, copper, among others; a polymer, such as polymethylphenylacetylene, copperphtalocyanine, polyparaphenylene, polyphenylenevinylene, polyaniline, polythiophene and polypyrrole; and amorphous carbon.

The invention is now explained with reference to the figures, which illustrate exemplary embodiments and throughout which like reference numbers indicate like features.FIGS. 2A-2Cdepict a portion of a memory array200according to exemplary embodiments of the invention.FIGS. 2B and 2Care cross-sections illustrating a portion of the memory array200ofFIG. 2Ataken along line2A-2A′ and according to alternate embodiments of the invention.

Referring toFIGS. 2A and 2B, the array200is supported by a substrate210. Over the substrate210, though not necessarily directly so, is a first (e.g., a bottom) electrode212for each memory element201a,201b. This electrode212is preferably tungsten (W), but may be any conductive material, such as aluminum, among others. An insulating layer214is between the first electrodes212and can be, for example, silicon nitride (Si3N4), a low dielectric constant material, an insulating glass, or an insulating polymer, but is not limited to such materials.

A stack240of layers is formed over the first electrodes212. The stack240includes one or more layers of resistance variable material. The stack240can include one or more layers of other materials such as, for example, metal.

In the exemplary embodiments shown inFIGS. 2A-2C, the memory cell stack240includes, for example, a chalcogenide material layer241, a tin-chalcogenide layer242, and an optional metal layer243. The invention, however, is not limited to such embodiments, and the stack240can include additional or fewer layers of other materials suitable for forming a resistance variable memory element. For example, the stack240can include a second chalcogenide material layer (not shown) over the metal layer243. The second chalcogenide layer may be a same material as the chalcogenide layer241or a different material.

In the illustrated embodiments, the chalcogenide material layer241is e.g., germanium selenide (GexSe100−x). The germanium selenide may be within a stoichiometric range of about Ge33Se67to about Ge60Se40. The chalcogenide material layer241may be between about 100 Å and about 1000 Å thick, e.g., about 300 Å thick. Layer241need not be a single layer, but may also be comprised of multiple chalcogenide sub-layers having the same or different stoichiometries. The chalcogenide material layer241is in electrical contact with the underlying electrodes212.

Over the chalcogenide material layer241is an optional layer of metal-chalcogenide242, such as tin-chalcogenide (e.g., tin selenide (Sn1+/−xSe, where x is between about 1 and about 0)), or silver-chalcogenide (e.g., silver selenide). It is also possible that other chalcogenide materials may be substituted for selenium, such as sulfur, oxygen, or tellurium. The layer242in the exemplary embodiment is a layer of tin-chalcogenide layer and may be about 100 Å to about 400 Å thick; however, its thickness depends, in part, on the thickness of the underlying chalcogenide material layer241. The ratio of the thickness of the tin-chalcogenide layer242to that of the underlying chalcogenide material layer241should be between about 5:1 and about 1:3.

An optional metal layer243is provided over the tin-chalcogenide layer242, with silver (Ag) being the exemplary metal. This metal layer243is between about 300 Å and about 500 Å thick. Over the metal layer243are second (e.g., top) electrodes251. The second electrodes251can be made of the same material as the first electrodes212, but are not required to be so formed. In the exemplary embodiment shown inFIGS. 2A and 2B, the second electrodes251are preferably tungsten (W).

In the embodiment ofFIG. 2B, all layers241,242,243of the stack240are blanket layers extending over the array200. In an alternative embodiment shown inFIG. 2C, at least a portion of the stack240is patterned. When one or more top layers of the stack240are conductive, it is desirable to pattern those layers similarly to the second electrodes251to avoid the second electrodes251being shorted together. Specifically, in the embodiment illustrated inFIG. 2C, chalcogenide material layer241is a blanket layer over the memory array and is shared by all memory elements201a,201bof the array200, and optional metal-chalcogenide layer242and optional metal layer243are patterned. Layers242,243are patterned similarly to the second electrodes251, as shown inFIG. 2C. Layers242,243and second electrodes251are patterned to form longitudinally extending element stacks202. WhileFIG. 2Cshows only layers242,243,251as being patterned, it should be appreciated that layer241could also be patterned.

As shown inFIG. 2A, the second electrodes251are formed as lines along the x (first) direction of a memory array. The first electrodes212have a pitch208, which, for example, is the distance in the y direction from about the center of a first electrode212bin row n+4 to about the center of a first electrode212cin row n+5. The second electrodes251have a pitch209, which is approximately the same as the pitch208of the first electrodes212. The second electrodes251are offset by approximately one half pitch208(or209) from the first electrodes212. Accordingly, as shown inFIGS. 2A-2C, each first electrode212underlies a region260between two second electrodes251. In the exemplary embodiment ofFIGS. 2A-2C, each first electrode212underlies a portion of two adjacent second electrodes251. For example, each first electrode212of word row n underlies a portion of the two adjacent second electrodes251(one shown above row n in the y (second) direction and a second one below row n in the y direction).

The array200includes memory elements201a,201b, each for storing at least one bit, i.e., a logic 1 or 0. Since each first electrode212underlies two second electrodes251, each first electrode212is associated with two memory elements201a,201b. Accordingly, the bit density of the array200can be increased over prior art arrays that have a single first electrode associated with a single second electrode and thus, a single memory element. During operation, conductive pathways221a,221bare formed, which causes a detectible resistance change across the memory elements201a,201b, respectively.

FIGS. 3A-3Cdepict a portion of a memory array300according to additional exemplary embodiments of the invention. Specifically,FIG. 3Ashows a portion of a memory array300.FIGS. 3B and 3Cshow a cross-section of the memory array300ofFIG. 3Ataken along the line3A-3A′. The embodiments ofFIGS. 3A-3Care similar to those depicted inFIGS. 2A-2C, except that each first electrode212is associated with three second electrodes351.

As shown inFIG. 3A, the second electrodes351are lines along the x direction. The first electrodes212have a pitch308in the y direction. The second electrodes lines351are arranged on a smaller pitch309than the first electrodes212, such that three or more second electrodes351are associated with each first electrode212. In the illustrated embodiment, three second electrodes351can address each first electrode212, but the array300could be configured such that electrodes351have an even smaller pitch as compared to the pitch308of the first electrodes, such that more than three second electrodes351can address a single first electrode212.

The illustrated array300includes memory elements301a,301b,301c, each for storing at least one bit, i.e., a logic 1 or 0. Since each first electrode212is addressable by three second electrodes351, each first electrode212is associated with three memory elements301a,301b,301c. Accordingly the bit density of the array300can be increased over the embodiment shown inFIGS. 2A-2C.

In the embodiment shown inFIG. 3Ball layers241,242,243of the stack240are blanket layers and are continuously shared by all memory elements301a,301b,301cof the array300. In an alternative embodiment shown inFIG. 3C, at least a portion of the stack240is patterned by etching. Specifically, in the embodiment illustrated inFIG. 3C, chalcogenide material layer241is a blanket layer and is shared by all memory elements301a,301b,301cof the array300, and tin-chalcogenide layer242and metal layer243are patterned. The layers242,243are patterned similarly to the second electrodes351. WhileFIG. 3Cshows only layers242,243as being patterned, it should be appreciated that layer241could also be patterned.

FIGS. 4A-4Bdepict a portion of a memory array400according to another exemplary embodiment of the invention. Specifically,FIG. 4Ashows a portion of a memory array400andFIG. 4Bis an enlarged view of the portion ofFIG. 4A. The embodiment shown inFIGS. 4A-4Bis similar to those depicted inFIGS. 2A-3C, except that each first electrode212is associated with four second electrodes451.

As shown inFIG. 4A, the first electrodes212have a pitch408xin the x direction and408yin the y direction. The second electrodes451are arranged to have approximately the same pitches408x,408y, but are offset from the first electrodes212by about one half pitch. Accordingly, the second electrodes451have a pitch409x,409y. Also, it is preferable that the second electrodes451directly overlie at least a portion of the first electrode212that they address. Specifically, as shown inFIG. 4B, corners418of second electrodes451a,451b,451c,451ddirectly overlie corners of a corresponding first electrode212.

The array400includes memory elements401a,401b,401c,401deach for storing at least one bit, i.e., a logic 1 or 0. Since each first electrode212is addressable by four second electrodes451, each first electrode212is associated with four memory elements401a,401b,401c,401d. Accordingly the bit density of the array400can be increased over the embodiment shown inFIGS. 2A-3C.

A cross-sectional view of the array400along line4A-4A′ would appear similar to the cross-sectional views shown inFIGS. 2B and 2C. Second electrodes451would appear in a same position as the electrodes251shown inFIGS. 2B and 2C. For simplicity, cross-sectional views of the array400are omitted and reference is made toFIGS. 2B and 2C. The array400includes stack240having layers241,242,241, as represented inFIGS. 2B and 2C. Additionally, the layers241,242,243can be blanket layers (as represented inFIG. 2B) or a portion of the stack240, e.g., layer242,243, can be patterned (as represented inFIG. 2C).

FIGS. 5A-5Bdepict a portion of a memory array500according to additional exemplary embodiments of the invention. Specifically,FIG. 5Ashows a portion of a memory array500andFIG. 5Bis an enlarged view of the portion of FIG.5A. The embodiments shown inFIGS. 5A-5Bare similar to those depicted inFIGS. 2A-4D, except that each first electrode212is associated with nine second electrodes551.

As shown inFIG. 5A, the first electrodes212have a pitch508xin the x direction and508yin the y direction. The second electrodes551are arranged on a smaller pitches509xin the x direction and509yin the y direction such that nine second electrodes551can address each first electrode212. In the illustrated embodiment, nine second electrodes551can address each first electrode212, but the array500could be configured such that electrodes551have different pitches as compared to the pitches508x,508yof the first electrodes212, such that greater or fewer than nine second electrodes551can address a single first electrode212.

Also, it is preferable that the second electrodes451directly overlie at least a portion of the first electrode212that they address. Specifically, as shown inFIG. 5B, corners and/or edges518of second electrodes551a,551b,551c,551f,551i,551h,551g,551ddirectly overlie corners of a corresponding first electrode212. The whole of second electrode55ledirectly overlies the first electrode212.

The array500includes memory elements540a,540b,540c,501d,50le,501f,501g,501h,501ieach for storing one bit, i.e., a logic 1 or 0. Since each first electrode212is addressable by nine second electrodes551, each first electrode212is associated with nine memory elements540a,540b,540c,501d,50le,501f,501g,501h,501i. Accordingly the bit density of the array500is increased over the embodiment shown inFIGS. 2A-4B.

A cross-sectional view of the array500taken along line5A-5A′ would appear similar to the cross-sectional views shown inFIGS. 3B and 3C. Second electrodes551would appear in a same position as the electrodes351shown inFIGS. 3B and 3C. For simplicity, cross-sectional views of the array500are omitted and reference is made toFIGS. 3B and 3C. The array500includes stack240having layers241,242,241, as represented inFIGS. 3B and 3C. Additionally, the layers241,242,243can be blanket layers (as represented inFIG. 3B) or a portion of the stack240, e.g., layer242,243, can be patterned (as represented inFIG. 3C).

The formation the memory array200(FIGS. 2A-2C) according to one exemplary embodiment of the invention is now described. No particular order is required for any of the actions described herein, except for those logically requiring the results of prior actions. Accordingly, while the actions below are described as being performed in a general order, the order is exemplary only and can be altered if desired. Although the formation of only a portion of an array200is shown, it should be appreciated that the memory array200can include additional memory elements201a,201b, which can be formed concurrently.

As shown byFIG. 6A, a substrate210is initially provided. As indicated above, the substrate210can be semiconductor-based or another material useful as a supporting structure. An insulating layer214is formed over the substrate210. The insulating layer214can be silicon nitride, a low dielectric constant material, or other insulators known in the art, and may be formed by any known method. Preferably, the insulating layer214(e.g., silicon nitride) does not allow metal ion migration from the optional metal-chalcogenide layer242. An opening214ain the insulating layer214is made, for instance by photolithographic and etching techniques, exposing a portion of the substrate210. A first electrode212is formed within the opening214a, by forming a layer of conductive material over the insulating layer214and in the opening214a. A chemical mechanical polishing (CMP) step is performed to remove the conductive material from over the insulating layer214. Desirably, the first electrode212is formed of tungsten, but may be any conductive material.

At least one layer of a memory stack240is formed over the insulating layer214and first electrodes212, as depicted inFIG. 6B. In the illustrated embodiment, a chalcogenide material layer241is formed over the first electrodes212and insulating layer214. Formation of the chalcogenide material layer241may be accomplished by any suitable method, for example, by sputtering.

When it is desirable to etch one or more layers of the stack240(FIG. 2C), an etch stop layer231is formed over the chalcogenide material layer241. As shown inFIG. 6C, the etch stop layer is patterned to provide openings231aover the layer241offset from the first electrodes212. The etch stop layer231is chosen to have a high selectivity to the etch chemistry used to etch certain layers of the memory cell stack240. Accordingly, the particular etch stop layer may depend on the composition of the memory cell stack240. In the illustrated embodiment, an exemplary etch stop layer is transparent carbon, although other materials can be used.

As shown inFIG. 6D, additional layers of the memory stack240are formed over the etch stop layer and in opening231a. In the illustrated embodiment, an optional metal-chalcogenide layer242(e.g., tin-chalcogenide) is formed over the etch stop layer and in opening231aand in contact with the chalcogenide material layer241. The metal-chalcogenide layer242can be formed by any suitable method, e.g., physical vapor deposition, chemical vapor deposition, co-evaporation, sputtering, among other techniques. An optional metal layer243is formed over the tin-chalcogenide layer242. The metal layer243is preferably silver (Ag), or at contains silver, and is formed to a preferred thickness of about 300 Å to about 500 Å. The metal layer243may be deposited by any technique known in the art.

When the structure ofFIG. 2Bis desired, formation of the etch stop layer231is omitted and the layer242,243are formed on the layer241.

Referring toFIG. 6E, a conductive material is deposited over the metal layer243to form a second electrode251. Similar to the first electrode212, the conductive material for the second electrode251may be any material suitable for a conductive electrode. In one exemplary embodiment the second electrode251is tungsten.

As illustrated inFIG. 6F, a photoresist layer232(or other mask layer) is deposited over the second electrode251layer to define second electrodes251. When the structure ofFIG. 2Bis desired, only the second electrode layer251is etched. When the structure ofFIG. 2Bis desired, second electrode layer251and layers242,243are etched to define stacks202. The etching stops at the etch stop layer231. Desirably, the mask layer232is formed to define stacks202such that the stacks202have a width282, which is larger than the width281of the opening231a. This provides for an alignment margin between the mask layers used to define openings231aand the photoresist layer232.

The photoresist layer232is removed, leaving one of the structures shown inFIG. 2Bor2C.

Additional steps may be performed to complete the memory array200. For example, an insulating layer (not shown) may be formed over the second electrodes251. Also, other processing steps can be conducted to electrically couple the array200to peripheral circuitry (not shown) and to include the array200in an integrated circuit or processor system, e.g., processor system700described below in connection withFIG. 7.

The method described above can be used to form any memory array300(FIGS. 3A-3C),400(FIGS. 4A-4B),500(FIGS. 5A-5B) according to the invention. When forming any of the arrays300,400, and500, the second electrodes351,451,551(and optionally layers242,243), respectively, are patterned to achieve the respective structures described inFIGS. 3A-5B.

FIG. 7illustrates a processor system700which includes a memory circuit748, e.g., a memory device, which employs memory array200constructed according to the invention. The circuit748could instead employ any of memory arrays300(FIGS. 3A-3C),400(FIGS. 4A-4B), or500(FIGS. 5A-5B). The processor system700, which can be, for example, a computer system, generally comprises a central processing unit (CPU)744, such as a microprocessor, a digital signal processor, or other programmable digital logic devices, which communicates with an input/output (I/O) device746over a bus752. The memory circuit448communicates with the CPU744over bus752typically through a memory controller.

In the case of a computer system, the processor system700may include peripheral devices such as a floppy disk drive754and a compact disc (CD) ROM drive756, which also communicate with CPU744over the bus752. Memory circuit748is preferably constructed as an integrated circuit, which includes a memory array200according to the invention. If desired, the memory circuit748may be combined with the processor, for example CPU744, in a single integrated circuit.

The above description and drawings are only to be considered illustrative of exemplary embodiments, which achieve the features and advantages of the present invention. Modification and substitutions to specific process conditions and structures can be made without departing from the spirit and scope of the present invention. Accordingly, the invention is not to be considered as being limited by the foregoing description and drawings, but is only limited by the scope of the appended claims.