Semiconductor device having a die pad with a dam-like configuration

A semiconductor device includes a semiconductor substrate, a power transistor formed in the semiconductor substrate, the power transistor including an active area in which one or more power transistor cells are formed, a first metal pad formed above the semiconductor substrate and covering substantially all of the active area of the power transistor, the first metal pad being electrically connected to a source or emitter region in the active area of the power transistor, the first metal pad including an interior region laterally surrounded by a peripheral region, the peripheral region being thicker than the interior region, and a first interconnect plate or a semiconductor die attached to the interior region of the first metal pad by a die attach material. Corresponding methods of manufacture are also described.

BACKGROUND

Many semiconductor device technologies use metal clips for source/emitter pad interconnections. Cross-contamination between neighboring bond pads is a concern with clip bonding, which utilizes solder paste materials. The undesired distribution or spreading of the solder paste material is typically referred to as ‘flooding’, and can lead to severe die pad corrosion. Cu-based logic die pads are particularly sensitive to solder paste material flooding. For example, typical Cu-to-Cu nail-head bonding processes do not allow any organic foreign material or corrosive byproducts on the Cu die pad surface.

Thus, there is a need for improved semiconductor device interconnect technology.

SUMMARY

According to an embodiment of a semiconductor device, the semiconductor device comprises: a semiconductor substrate; a power transistor formed in the semiconductor substrate, the power transistor including an active area in which one or more power transistor cells are formed; a first metal pad formed above the semiconductor substrate and covering substantially all of the active area of the power transistor, the first metal pad being electrically connected to a source or emitter region in the active area of the power transistor, the first metal pad comprising an interior region laterally surrounded by a peripheral region, the peripheral region being thicker than the interior region; and a first interconnect plate or a semiconductor die attached to the interior region of the first metal pad by a die attach material.

In one embodiment, the interior region of the first metal pad has a thickness in a range of 5 μm to 10 μm and the peripheral region of the first metal pad has a thickness of about 20 μm or greater.

Separately or in combination, the semiconductor substrate may have a thickness of 250 μm or less, e.g. 60 μm or less.

Separately or in combination, the peripheral region of the first metal pad may be thicker than the die attach material.

Separately or in combination, the die attach material may be thicker than the peripheral region of the first metal pad so that a bottom surface of the first interconnect plate or the semiconductor die is disposed above a top surface of the peripheral region of the first metal pad.

Separately or in combination, a bottom surface of the first interconnect plate may have one or more structures laterally disposed inward from the peripheral region of the first metal pad and vertically extending toward the interior region of the first metal pad.

Separately or in combination, the peripheral region of the first metal pad may be divided into a plurality of segments and neighboring ones of the segments may be laterally separated by a gap.

Separately or in combination, the power transistor may comprise a plurality of output channels, each output channel configured to deliver current to a load, the power transistor may comprise an individual active area for each output channel, and the first metal pad may cover substantially a first one of the active areas of the power transistor.

Separately or in combination, the semiconductor device may further comprise: a plurality of additional metal pads formed above the semiconductor substrate, each additional metal pad covering substantially a corresponding one the active areas of the power transistor, each additional metal pad being electrically connected to a source or emitter region in the active area substantially covered by the metal pad, each metal pad comprising an interior region laterally surrounded by a peripheral region, the peripheral region being thicker than the interior region; and a plurality of additional interconnect plates, each additional interconnect plate being attached to the interior region of a corresponding one of the additional metal pads by a die attach material.

Separately or in combination, the semiconductor device may further comprise one or more logic devices integrated in a different region of the semiconductor substrate as the power transistor.

Separately or in combination, the first metal pad may be a Cu pad and the first interconnect plate may be a Cu clip.

According to an embodiment of a method of manufacturing a semiconductor device, the method comprises: forming a power transistor in a semiconductor substrate, the power transistor including an active area in which one or more power transistor cells are formed; forming a first metal pad above the semiconductor substrate and which covers substantially all of the active area of the power transistor, the first metal pad being electrically connected to a source or emitter region in the active area of the power transistor, the first metal pad comprising an interior region laterally surrounded by a peripheral region, the peripheral region being thicker than the interior region; and attaching a first interconnect plate or a semiconductor die to the interior region of the first metal pad by a die attach material.

In one embodiment, forming the first metal pad comprises: depositing a first Cu layer above the semiconductor substrate and which covers substantially all of the active area of the power transistor; forming a mask on a part of the first Cu layer which corresponds to the interior region of the first metal pad, the mask configured to prevent Cu deposition; and depositing a second Cu layer on a part of the first Cu layer unprotected by the mask to form the peripheral region of the first metal pad, the interior region of the first metal pad being formed by the part of the first Cu layer protected by the mask during the depositing of the second Cu layer. The first Cu layer may have a thickness in a range of 5 μm to 10 μm and the second Cu layer may have a thickness in a range of 10 μm to 20 μm.

In another embodiment, forming the first metal pad may comprise: depositing a Cu layer above the semiconductor substrate and which covers substantially all of the active area of the power transistor; forming a mask on a part of the Cu layer which corresponds to the peripheral region of the first metal pad, the mask configured to prevent Cu etching; and etching a part of the Cu layer unprotected by the mask to form the interior region of the first metal pad, the peripheral region of the first metal pad being formed by the part of the Cu layer protected by the mask during the etching of the Cu layer. The thickness of the Cu layer as deposited may be about 20 μm or more and the thickness of the etched part of the Cu layer may be in a range of 5 μm to 10 μm.

Separately or in combination, the peripheral region of the first metal pad may be thicker than the die attach material and wherein attaching the first interconnect plate or the semiconductor die to the interior region of the first metal pad may comprise: depositing the die attach material on the interior region of the first metal pad; and placing the first interconnect plate in contact with the die attach material while using the peripheral region of the first metal pad to align the first interconnect plate with the first metal pad.

Separately or in combination, the die attach material may be thicker than the peripheral region of the first metal pad and wherein attaching the first interconnect plate or the semiconductor die to the interior region of the first metal pad may comprise: depositing the die attach material on the interior region of the first metal pad; and placing the first interconnect plate in contact with the die attach material while using surface tension of the die attach material to align the first interconnect plate with the first metal pad.

Separately or in combination, a bottom surface of the first interconnect plate may have one or more structures laterally disposed inward from the peripheral region of the first metal pad and attaching the first interconnect plate or the semiconductor die to the interior region of the first metal pad may comprise: depositing the die attach material on the interior region of the first metal pad; and placing the first interconnect plate in contact with the die attach material so that the one or more features at the bottom surface of the first interconnect plate vertically extend toward the interior region of the first metal pad and are laterally disposed inward from the peripheral region of the first metal pad, to align the first interconnect plate with the first metal pad.

Separately or in combination, the power transistor may comprise a plurality of output channels, each output channel configured to deliver current to a load, the power transistor may comprise an individual active area for each output channel, the first metal pad may cover substantially a first one of the active areas of the power transistor, and the method may further comprise: forming a plurality of additional metal pads above the semiconductor substrate, each additional metal pad covering substantially a corresponding one the active areas of the power transistor, each additional metal pad being electrically connected to a source or emitter region in the active area substantially covered by the Metal pad, each Metal pad comprising an interior region laterally surrounded by a peripheral region, the peripheral region being thicker than the interior region; and attaching each of a plurality of additional interconnect plates to the interior region of a corresponding one of the additional metal pads by a die attach material.

DETAILED DESCRIPTION

The embodiments described herein provide a metal pad structure for a semiconductor die, and corresponding methods of manufacture. The metal pad has an interior region laterally surrounded by a peripheral region. The peripheral region is thicker than the interior region. The interior region of the metal pad is configured for attachment to an interconnect plate such as a metal clip or metal block, or for attachment to another semiconductor die. The thicker peripheral region of the metal pad forms a dam-like structure for retaining material used to attach the interconnect plate or the other semiconductor die to the metal pad. Also beneficially, the metal pad exerts less mechanical stress on the semiconductor substrate during heating and cooling of the device because the interior region of the metal pad is made thinner.

FIG. 1illustrates a side perspective view of an embodiment of a semiconductor device100having a metal pad102with a dam-like configuration. According to this embodiment, the semiconductor device100includes a semiconductor substrate104and a power transistor such as a power MOSFET (metal-oxide-semiconductor field-effect transistor), IGBT (insulated gate bipolar transistor), HEMT (high-electron mobility transistor), etc. formed in the semiconductor substrate104. One or more logic devices may be integrated in a different region of the semiconductor substrate104as the power transistor, e.g., for controlling the power transistor. For example, a driver circuit and/or controller may be integrated in the semiconductor substrate104for controlling the power transistor.

The semiconductor substrate104may be relatively thick, e.g. greater than 250 μm thick, or relatively thin, e.g., less than 250 μm thick. The semiconductor substrate104may be made of any semiconductor material suitable for manufacturing a power transistor. Examples of such materials include, but are not limited to, elementary semiconductor materials such as silicon (Si) or germanium (Ge), group IV compound semiconductor materials such as silicon carbide (SiC) or silicon germanium (SiGe), binary, ternary or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN) or indium gallium arsenide phosphide (InGaAsP), etc.

The power transistor formed in the semiconductor substrate104includes an active area in which one or more power transistor cells are formed. The active area is covered by the metal pad102with the dam-like configuration and therefore is out of view inFIG. 1. The metal pad102with the dam-like configuration is formed above the semiconductor substrate104and covers substantially all of the active area of the power transistor. The metal pad102is electrically connected to a source or emitter region in the active area of the power transistor. The metal pad102has an interior region106laterally surrounded by a peripheral region108. The peripheral region108is thicker than the interior region106. The thicker peripheral region108of the metal pad102forms a dam-like structure for retaining material used to attach an interconnect plate or another semiconductor die to the metal pad102.FIG. 1does not show an interconnect plate or another semiconductor die attached to the metal pad102with the dam-like configuration so as to provide an unobstructed view of the entire metal pad102.

In one embodiment, the interior region106of the metal pad102with the dam-like configuration has a thickness t1in a range of about 5 μm to about 20 μm and the peripheral region108of the metal pad102has a thickness t2of about 20 μm or greater. Still other thickness ranges for the interior and peripheral regions106,108of the metal pad102are contemplated. In general, the interior and peripheral regions106,108of the metal pad102with the dam-like configuration may have any desired thicknesses so long as the peripheral region108is thicker than the interior region106. Such a metal pad102with a thinner interior region106and a thicker peripheral region108is particularly beneficial for thinner semiconductor dies, e.g., in the case of the semiconductor substrate104having a thickness of 60 μm or less, because the metal pad102exerts less mechanical stress on the semiconductor substrate104during heating and cooling of the device100.

The side of the semiconductor device100with the metal pad102having the dam-like configuration may include additional metal structures such as other metal pads110and/or metal traces112formed in the same metal layers as the metal pad102with the dam-like configuration. For example, the side of the semiconductor device with the metal pad102having the dam-like configuration may also include a gate pad110which is electrically connected to gate electrodes in the active area of the power transistor. The gate pad110may or may not have the same thickness as the peripheral region108of the metal pad102with the dam-like configuration. One or more metal traces112may be formed at the side of the semiconductor device100with the metal pad102having the dam-like configuration. The metal traces112provide signal routing for the power transistor, and may or may not have the same thickness as the interior region106of the metal pad102with the dam-like configuration.

FIG. 2Aillustrates a top plan view of another embodiment of a semiconductor device200having a metal pad102with a dam-like configuration, andFIG. 2Billustrates a sectional view of the semiconductor device200along the line labeled A-A′ inFIG. 2A. The embodiment illustrated inFIGS. 2A and 2Bis similar to the embodiment illustrated inFIG. 1. Different, however, the semiconductor device200includes additional pads202,204at the side of the semiconductor device200with the metal pad102having the thinner interior region106and the thicker peripheral region108. The additional pads202,204may be used to electrically contact different or additional regions of the power transistor formed in the semiconductor substrate104, and/or may be used to bring an electrical contact from the backside of the semiconductor device200to the frontside.

FIG. 2Balso shows the semiconductor device200after an interconnect plate206such as a metal clip or metal block is attached to the interior region106of the metal pad102with a dam-like configuration. The interconnect plate206is attached to the interior region106of the metal pad102by a die attach material208such as solder, electrically conductive glue, electrically conductive tape, etc. The interconnect plate206and the interior region106of the metal pad102to which the interconnect plate206is attached may each have one or more additional layers210,212such as an adhesion promotion layer.

FIG. 2Balso shows the active area214of the power transistor formed in the semiconductor substrate104. The active area214includes one or more power transistor cells. Each power transistor cell includes a gate electrode216insulated from the semiconductor substrate216by a dielectric218, a source or emitter region220of a first conductivity type and a body region222of a second conductivity type which provides a channel controlled by a voltage applied to the gat electrode216. One power transistor cell is shown inFIG. 2Bfor ease of illustration. Each gate electrode216may be disposed in a gate trench224formed in the semiconductor substrate104and which may or may not include a field electrode226below and insulated from the gate electrode216. According to the embodiment illustrated inFIG. 2B, the power transistor is a vertical device with a drift zone228between the body regions222and the backside of the semiconductor substrate104, the backside forming a drain or collector region of the power transistor. A metal body230such as a die paddle of a lead frame, metal block, metallized surface of a substrate, etc. is attached to the backside of the semiconductor substrate104by a die attach material232to form a drain/collector terminal of the semiconductor device200. The source/emitter terminal is at the opposite side of the device200, and is formed in part by the metal pad102with the thinner interior region106and the thicker peripheral region108and the interconnect plate206attached to the thinner region106of the metal pad102. In one embodiment, the metal pad102with the dam-like configuration is a Cu pad and the interconnect plate207is a Cu clip. The power transistor may instead have planar gate electrodes insulated from the frontside of the semiconductor substrate104and/or may be a lateral device instead of a vertical device.

FIG. 2Cillustrates a semiconductor device300similar to the device200shown inFIGS. 2A-2B, but with a semiconductor die302attached to the interior region106of the metal pad102having the dam-like configuration instead of an interconnect plate. The semiconductor die302may have a metallized surface304attached to the interior region106of the metal pad102by the die attach material208, and one or more die pads306at the opposite side of the semiconductor die302. A passivation layer308may be applied to this side of the semiconductor die302, and electrical conductors310may be attached to the die pads306to provide electrical connections to different terminals of the die302. In one embodiment, the lower die104and the upper die302are power transistor dies electrically connected in a half bridge configuration via the metal pad102with the dam-like configuration.

FIGS. 3A through 3Cillustrate an embodiment of forming the metal pad102with the dam-like configuration shown inFIGS. 2A through 2B,

FIG. 3Ashows a first patterned metal layer400formed over a semiconductor substrate104. In one embodiment, the first patterned metal layer400is a Cu layer formed by electrochemical deposition (ECD). The first patterned metal layer400forms metal traces402and metal pad bases404,406,408,410.

FIG. 3Bshows a second patterned metal layer412formed on the first patterned metal layer400. In one embodiment, the second patterned metal layer412is a Cu layer formed by ECD. The second patterned metal layer412is formed where thicker metal is desired. This includes a first metal pad414/102, where the second patterned metal layer412stacked on the first patterned metal layer400forms a thicker peripheral region416of the first metal pad414/102. The first metal pad414/102also has a thinner interior region418which is formed by just the first patterned metal layer400. The second patterned metal layer412may also be used to form other thick metal pads420,422,424. The first and second patterned metal layers400,412may be Cu layers, as explained above, or other types of metal layers such as Al, AlCu, Au, etc. The first and second patterned metal layers400,412may include additional metal layers such as an oxidation prevention layer, adhesion promotion layer, etc. In one embodiment, the exterior lateral edge426of the second patterned metal layer412is spaced inward from the exterior lateral edge428of the first patterned metal layer400by a distance d1along one or more sides of the first metal pad414/102, e.g., by about 5 μm. The exterior lateral edge426of the second patterned metal layer412may instead be vertically aligned with the exterior lateral edge428of the first patterned metal layer400along one or more sides of the first metal pad414/102.

FIG. 3Cshows an interconnect plate430attached to the thinner interior region418of the first metal pad414/102. The interconnect plate430may be attached to the interior region418of the first metal pad414/102by a die attach material (out of view) such as solder, electrically conductive glue, electrically conductive tape, etc., as previously described herein. The interior lateral edge432of the second patterned metal layer412may be spaced apart from the lateral edge434of the interconnect plate430by a distance d2along one or more sides of the first metal pad414/102, e.g., by about 100 μm.

The peripheral region416of the first metal pad414/102has a dam-like shape, as previously described herein. The dam-like shape may be continuous and uninterrupted over the entire periphery of the first metal pad414/102as shown inFIG. 3B. Alternatively, the second patterned metal layer412may be structured such that the peripheral region416of the first metal pad414/102is divided into a plurality of segments with neighboring ones of the segments being laterally separated by a gap. Such gaps are indicted by dashed boxes inFIG. 3B. Accordingly, the dam-like shape of the peripheral region416of the first metal pad414/102may be continuous and uninterrupted along all sides of the first metal pad414/102, along some but not all of the sides of the first metal pad414/102, may have breaks between wall segments, or any other type of desired shape or configuration.

FIG. 4illustrates a side perspective view of an embodiment of the interconnect plate430which is attached to the thinner interior region416of the first metal pad414/102shown inFIGS. 3A through 3C. According to this embodiment, the interconnect plate430is a metal clip such as a Cu clip. The metal clip has a first region436extending along a first level L1, a second region438extending along a second level L2above the first level L1and an intermediary region440connecting the first and second regions436,438and providing a transition between the first and second levels L1, L2. The first region436of the metal clip430is attached to the thinner interior region418of the first metal pad414/102, and the intermediary region440of the metal clip430provides a height transition so that the metal clip430does not contact the peripheral region416of the first metal pad414/102.

FIGS. 5 through 7illustrate respective sectional views of further embodiments of semiconductor devices, each having a different chip pad-to-interconnect interface.

InFIG. 5, the peripheral region108of the metal pad102with the dam-like configuration is thicker than the die attach material208used to attach an interconnect plate206(or other semiconductor die) to the thinner interior region106of the metal pad102. According to the embodiment, the peripheral region108of the metal pad102may be used as a guide when placing the first interconnect plate206(or other semiconductor die), to ensure the interconnect plate206(or other semiconductor die) is properly landed on the thinner interior region106of the metal pad102. For example, after depositing the die attach material208on the interior region106of the metal pad102, the interconnect plate206(or other semiconductor die) may be placed in contact with the die attach material208while using the peripheral region108of the metal pad102to align the interconnect plate206(or other semiconductor die) with the metal pad102.

InFIG. 6, the die attach material208is thicker than the peripheral region108of the metal pad102with the dam-like configuration so that a bottom surface500of the first interconnect plate206(or instead the bottom surface of another semiconductor die) is disposed above a top surface502of the peripheral region108of the metal pad102. According to this embodiment, the properties of the die attach material208allow the interconnect plate206(or other semiconductor die) to auto-center on the thinner interior region106of the metal pad102with the dam-like configuration. For example, after depositing the die attach material208on the interior region206of the metal pad102, the interconnect plate206(or other semiconductor die) may be placed in contact with the die attach material208while using surface tension of the die attach material208to align the interconnect plate206(or other semiconductor die) with the metal pad102. The interconnect plate206(or other semiconductor die) is soft-landed on the thinner interior region106of the metal pad102, meaning that the interconnect plate206(or other semiconductor die) is not pressed into the die attach208, but instead is gently placed on the die attach material208. In the case of glue as the die attach material208, surface tension of the glue centers the interconnect plate206(or other semiconductor die). This approach yields a rough alignment of the interconnect plate206(or other semiconductor die) with respect to the metal pad102having the dam-like configuration.

InFIG. 7, the bottom surface500of the interconnect plate206has one or more structures504laterally disposed inward from the peripheral region108of the metal pad102with the dam-like configuration and vertically extending toward the interior region106of the metal pad102. The one or more structures504may be formed, e.g., by stamping and aid in alignment of the interconnect plate206with the interior region106of the metal pad102during the landing process. For example, after depositing the die attach material208on the interior region106of the metal pad102, the interconnect plate206may be placed in contact with the die attach material208so that the one or more features504at the bottom surface500of the interconnect plate206vertically extend toward the interior region106of the metal pad102and are laterally disposed inward from the peripheral region108of the metal pad102, to align the interconnect plate206with the metal pad102.

The semiconductor device embodiments illustrated inFIGS. 1, 2A-2B, 3A-3C and 5-7show one metal pad having a thinner interior region and a thicker peripheral region and one interconnect plate (or other semiconductor die) attached to the thinner interior region of the metal pad. This is done for ease of illustration only. In general, the power transistor included in the semiconductor devices described herein may have one or more output channels or phases for delivering current to a load. In the case of a single output channel, the semiconductor device is a single-phase device. In the case of multiple (more than one) output channels, the semiconductor device is a multi-phase device such as a multi-phase voltage regulator.

The power transistor included in each semiconductor device described herein has an individual active area for each output channel and a separate dam-like metal pad of the kind described herein for each output channel. In general, for a power transistor with N output channels where N is an integer greater than or equal to 1, the corresponding semiconductor device has N separate active areas and N dam-like metal pads of the kind described herein—one for each output channel/active area of the device. One or more interconnect plates may be attached to each of the N dam-like metal pads. That is, the active area of each channel depends on the Ron (on-state resistance) requirement for that channel. As such, different sized interconnect plates may be used, depending on the active area size per channel. For example, a power transistor may have 1 larger active area and 3 smaller active areas. Smaller interconnect plates may be used for the 3 smaller active areas, and 1 larger interconnect plate or multiple smaller interconnect plates may be used for the larger active area.

FIG. 8illustrates a top plan view of an embodiment of a semiconductor device600with 4 separate active areas and hence 4 output channels. Each active area is substantially covered by a separate dam-like metal pad102of the kind described herein. Each dam-like metal pad102is electrically connected to a source or emitter region in the underlying active area, and has a thinner interior region106laterally surrounded by a thicker peripheral region108. One or more interconnect plates or another semiconductor die is attached to the interior region of106each dam-like metal pad102by a die attach material. The interconnect plates/additional semiconductor dies are not shown inFIG. 8so that the details of the dam-like metal pads102are unobscured.

FIGS. 9A through 9Eillustrate respective sectional views during different stages of manufacturing a semiconductor device having one or more dam-like metal pads of the kind described herein.

FIG. 9Ashows a barrier layer700such as TiW formed over a semiconductor substrate702, and a Cu seed layer704formed on the barrier layer700. The barrier layer700and the Cu seed layer704may be deposited, e.g., by physical vapor deposition (PVD). The barrier layer700and the Cu seed layer704may be relatively thin, e.g., about 300 nm thick each.

FIG. 9Bshows a first Cu layer706formed on the Cu seed layer704. The first Cu layer706may be formed by ECD, using a photoresist mask707to pattern the deposited Cu into a base708for metal pads and into metal traces710for signal routing. In one embodiment, the first Cu layer706has a thickness in a range of about 5 μm to about 20 μm, e.g., about 5 μm to about 10 μm.

FIG. 9Cshows the part of the first Cu layer706which corresponds to the interior region/base708of the dam-like metal pad and of the metal traces710patterned into the first Cu layer706being protected by a mask712, e.g., a resist. The mask712prevents subsequent Cu deposition on the first Cu layer706in the masked regions. A second Cu layer714is then deposited on the part of the first Cu layer706which is unprotected by the mask712to form the peripheral region108of the dam-like metal pad102and to thicken other pads, if desired. The interior region106of the dam-like metal pad102is formed by the part of the first Cu layer706protected by the mask712during deposition of the second Cu layer714. The same mask may be used to form both Cu layers706,714, wherein parts of the mask are removed after deposition of the first Cu layer706to form the second Cu layer714in the desired areas. In one embodiment, the second Cu layer714has a thickness in a range of about 10 μm to about 20 μm, e.g., about 10 μm to about 15 μm.

FIG. 9Dshows the structure after the mask707/712used for Cu deposition is removed, after a new ask716such as an imide mask is formed which covers the metal traces710and part of the periphery of the metal pads708/106, and after a protective layer718such as a passivation is formed on the exposed part of the second Cu layer714. The exposed part of the second Cu layer714is protected by the protective layer718, in case Ag etching is employed.

FIG. 9Eshows the structure after an interconnect plate206such as a metal clip or metal block, or another semiconductor die is attached to the thinner interior region708/106of the dam-like metal pad102, after a conductor720such as a wire stud bump, pillar, vertical (cut) bond wire, etc. is attached to other ones of the bond pads708which do not have a dam-like configuration, and after a metal body230such as a die paddle of a leadframe, metal block, metallized surface of a substrate, etc. is attached to the backside of the semiconductor substrate104. Die attach materials208,232such as solder, electrically conductive glue, electrically conductive tape, etc. may be used to facilitate some or all of the attachments. Additional layers212,304,722such as an adhesion promotion layer may be used in conjunction with the die attach materials208,232.

FIGS. 10A through 10Cillustrate respective sectional views during different stages of manufacturing a semiconductor device having one or more dam-like metal pads of the kind described herein, according to another embodiment.

FIG. 10Ashows a barrier layer800such as TiW formed over a semiconductor substrate802, a Cu layer804formed on the barrier layer800, and an optional silver or aluminium layer806formed on the Cu layer804. In one embodiment, the barrier layer800is relatively thin, e.g., about 300 nm thick, and the Cu layer804is relatively thick, e.g., at least 10 μm or at least 20 μm thick. In the case of a silver or aluminium layer806deposited on the Cu layer804, the optional layer806is thinner than the Cu layer804, e.g., about 200 nm in the case of Ag or about 50 nm in the case of Al.

FIG. 10Bshows the Cu layer804patterned, e.g. by lithography and etching, to form metal pad and metal trace structures808,810,812in the Cu layer804. The patterning process may include Ag or Al etching, e.g., using diluted hydrofluoric acid, followed by Cu etching, e.g. using H3PO4or H2O2, followed by TiW etching, e.g., using H2O2. After the Cu layer patterning process, a mask814such as an imide mask is formed which covers the metal trace structures812, the metal pad structures810which are to have a uniform thickness, and the periphery of the dam-like metal pad structure808. The exposed part of the Cu layer804unprotected by the mask814is then etched, e.g. using H3PO4or H2O2, to form a metal pad102having a dam-like configuration with a thinner interior region106and a thicker peripheral region108. The thickness t_ec of the etched part of the Cu layer804may be in a range of 5 μm to 10 μm. The peripheral region108of the dam-like metal pad102is formed by the part of the Cu layer804protected by the mask814during the etching of the Cu layer804. An interconnect plate such as a metal clip or metal block, or another semiconductor die may then be attached to the thinner interior region106of the dam-like metal pad102, as previously described herein.