Method and apparatus for computing interpolation factors in sample rate conversion systems

The invention allows the interpolation factor, a critical parameter in sample rate conversion systems, to be computed in a real-time system where there is a complex relationship between a DSP clock and the data clocks. Typically, two or three of the clocks in such a system will have simple relationships (such as CLOCK1=2*CLOCK2). This relationship leads to degenerate cases where, in fact, there are only one or two clocks to consider rather than three. Furthermore, the invention allows for input data rates that are higher than the DSP clock rate. The invention also provides for an arbitrary time delay to be applied to the output signal.

FIELD OF THE INVENTION

This invention relates generally to digital signal processing and more particularly to converting a digital signal at a first sampling rate to a representation of the same digital signal at a second sampling rate.

BACKGROUND OF THE INVENTION

In many electronic applications, signals are represented and processed digitally. Digital words, or samples, represent the value of the signal at a regular time interval. This regular interval is often referred to as the sample rate, and is typically expressed in units of Hertz (Hz) representing the reciprocal of the sample interval time period. The signal thus represented can have no energy above half the sample rate; the frequency equal to half the sample rate is called the Nyquist frequency.

Digital sample rate conversion is used in many types of digital systems. For example, audio signals, such as might be generated in making recordings of music, are often processed digitally. The various pieces of equipment used to process and record the signals will not always operate at the same sampling frequency. As a result, it is often necessary that each piece of equipment accept a digital signal sampled at a first rate and then convert it to a digital signal with a second sampling rate before processing it. Of course, the information content of the signal must not be appreciably changed by the sample rate conversion or the sound quality of the signal will be degraded.

A very simple way to accomplish sample rate conversion is to simply drop out samples from the first signal. The output waveform thus has fewer samples per second and therefore has a lower sample rate. Assuming the Nyquist criterion is met in the output signal, it is an accurate representation of the same signal as the input. This process is referred to generally as “decimation.” It is limited, though, to situations in which the sampling rate of the input is an integer multiple of the sampling rate of the output.

A process called interpolation may be used when the sampling rate of the output is intended to be an integer multiple higher than the sampling rate of the input signal. In such an interpolation operation, an intermediate signal can be first produced by filling the time between samples of the input signal with samples which are arbitrarily assigned the value of zero. Such an intermediate signal is called a “zero-stuffed” signal. Because samples are added while the time span is kept the same, the zero-stuffed signal has a higher sampling rate than the input signal. The higher frequency zero-stuffed signal can be filtered in a digital interpolation filter that smoothes out the discontinuities caused by adding the extra samples. The result is a digital signal which has the same shape as the input signal, but contains more samples per second.

The processes of decimation and interpolation may be combined. For example, a circuit could decimate by a factor of D and interpolate by a factor of I. The resulting output would have a sampling rate in a ratio of I/D to the input sampling rate. Such a circuit is, however, limited to scaling the sampling rate by a rational number. More importantly, for a digital system, there are practical limits on the ranges of values for D and I. The decimation factor D can not be so large that the decimated signal no longer satisfies the Nyquist rate. Additionally, the interpolation factor I cannot be made arbitrarily large, because the required complexity of the interpolation filter increases as I gets larger (e.g., more taps). Moreover, it is presumed that at least one of the different clocks is essentially identical to the system clock (i.e., DSP clock), or at least related to it in a straightforward manner, such as by a factor of 2. Maintaining consistency between the different sample rate clocks in such situations places a burden on the accuracy and complexity of the hardware of the timing system.

SUMMARY OF THE INVENTION

An ability to process data accurately in a three clock system allows for simplification of the requirements for real analog clock generation by adding complexity to the digital signal processing. In general, reductions in analog complexity are desirable because they lead to increased system reliability, greater flexibility of functionality, and lower system cost.

Described herein are systems and processes that allow the interpolation factor p, a critical parameter in sample rate conversion systems, to be computed in a real-time system where there is a complex relationship between a DSP clock and the data clocks. Typically, two or three of the clocks in such a system will have simple relationships (such as clock1=2*clock2). This relationship leads to degenerate cases where, in fact, there are only two clocks to consider. Furthermore, the systems and processes described herein allow for such computation of the interpolation factor to occur with input data rates that are higher than the DSP clock rate. In at least some embodiments, an arbitrary time delay can be applied to the output signal.

One embodiment of the invention relates to a process for rate-converting sampled data. Input data sampled according to an input sample clock is received. A value indicative of an output sample clock differing from the input sample clock by a value that need not be an integer is also received. Respective relationships are determined between each of the input and output sample clocks and a processor clock. Each of the input and output clocks are independent from the processor clock. An interpolation factor is determined as a function of the input sample clock, the output sample clock, and the processor clock. Output data is generated as a function of the input data and the interpolation factor, wherein the output data corresponds to the input data sampled according to the output sample clock.

Another embodiment of the invention relates to a system for converting sampled data from a first data rate to a second data rate. This includes a rate converter for receiving input data sampled according to an input sample clock and configured to produce output data indicative of the input data sampled according to an output sample clock. The rate converter operates at a processing clock rate that is independent from either of the input sample clock and the output sample clock. An accumulator receiving the processing clock is configured to monitor a sate of the processor clock and to determine respective relationships of each of the input sample clock and the output sample clock to the processor clock. The system also includes an interpolation factor circuit in communication with the accumulator and the rate converter. The interpolation factor circuit is configured to receive from the accumulator the respective relationships of each of the input sample clock and the output sample clock to the processor clock. The interpolation factor circuit is also configured to calculate an interpolation factor as a function of the input sample clock, the output sample clock, and processor clock. The rate converter is configured to convert the input data to the output data as a function of the interpolation factor.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Systems and processes for converting data at one sample rate to data at a second sample rate are described herein. In the prior art, implementations of sample rate conversion systems employ a digital signal processing clock that is equal to, or directly related to, as in an integer multiple of, the output sample rate. Beneficially, in the system and techniques described herein allow for a system processing clock having non-trivial M/N relationship to the output sample rate. For example, M and N can be very large integers. In at least some embodiments, a programmable time delay (having arbitrary range and resolution) can also be applied to the output signal.

In general, the techniques described herein can be applied to any real-time system having fixed converter frequencies, variable (or even fixed, but different) signal data rates. Use of the term converters, generally includes analog-to-digital converters (ADC) and digital-to-analog converters (DAC), depending upon the particular application. For example, in a source mode, a DAC provides an analog output stimulus signal, obtained from a synthesized digital representation of the stimulus signal. Alternatively, in a detector mode, an ADC converts a received analog response signal, as may be obtained from a device under test, to a digital representation of the received response signal for further processing from a test system. In either instance, a third system clock frequency would likely be employed, for example, controlling the DSP, that need not be related to either of the converter frequency or the signal data rate. Other applications include sample rate conversion systems in which the known converter sample rate is unrelated to the known system or processing clock.

Sample rate conversion techniques as described herein allow users to define baseband waveforms at a rate (i.e., timing) having a wide range and fine resolution relative to a fixed clock rate at which the actual converters operate (e.g., the converter clock rate). This sample rate conversion can be accomplished by determining a non-integer interpolation factor based on relationships among the three different clocks: converter clock; user clock; and system, or DSP clock. The interpolation factor is used by an interpolation filter. Exemplary interpolator filters include a polyphase, finite-impulse-response (FIR) filter and linear interpolator on the source, and a combination of a polyphase FIR filter, linear interpolator, and decimating FIR filters on the digitizer. These filter configurations yield a desired rate conversion within a system running at an unrelated processor or DSP clock rate.

Operation of the re-sampler is essentially transparent to the user so that the re-sampler instrument behaves as if it contained a conventional arbitrary waveform generator and digitizer with the converters operating at one of the input or output clock rates. Thus, the re-sampler knows nothing of special events, such as a start command, user clock reset commands, and the like, sample sizes, or signal content other than bandwidth restrictions. All errors introduced by the re-sampling process will be below the spurious free dynamic range specification. The re-sampler is fairly flexible in terms of input and output frequencies; the re-sampling ratios are driven by an external virtual clock generator which could be customized for different clocking scenarios.

Referring toFIG. 1, a block diagram of an exemplary embodiment of a re-sampler100according to the present invention includes a rate converter102, an accumulator104, and an interpolation factor module106. Also illustrated is an A/D converter108coupled to an input of the re-sampler100. The A/D converter108receives an input analog signal S(t) and samples it according to an input sample rate, or converter clock, referred to herein as a first clock domain. A period of the input sample cycle is illustrated as TRSI. The rate converter102receives the sampled, digital representation of the input signal S(n) in the first converter clock domain and converts it to an output representation of the same input signal, but in a second user clock domain. Generally, the second clock domain has an output sample rate that is different from the first. A period of the output sample cycle is illustrated as TRSO. The two clock domains are, for all practical purposes unrelated. In reality, they may vary by a non-integer ratio of two very large numbers. An important advantage offered by the present invention is that the rate converter102is operating according to yet another process clock, referred to herein as a third clock domain, referred to as a system, or DSP clock domain. A period of the processor sample cycle is illustrated as TDSP.

The accumulator104receives, or is pre-loaded with several values. One such value is representative of the output sample rate. In the example, this value is the period of the output sample rate TRSO. Alternatively or in addition, the accumulator104could have been pre-loaded with the output sample frequency FRSO(i.e., the inverse of TRSO). Another such pre-loaded value is representative of the input sample rate. In the example, this value is the period of the input sample rate TRSI(or input sample frequency, FRSI). Yet another value that can be pre-loaded into the accumulator104is a period of the processor clock, TDSP(or processor clock frequency, FDSP).

The accumulator104processes one or more of the pre-loaded values at the processor clock rate (DSP CLK) to produce several output values. Primarily, the output values include fractional values indicative of a relationship between the different clock domains. One such fractional value FRACRSIis obtained from a relationship of the input sample clock to the processor clock. Another such fractional value FRACRSOis obtained from a relationship of the output sample clock to the processor clock. One or more of the period and frequency of the input and output clocks (TRSI, FRSO, TRSO, FRSO) can also be provided as output values. In the illustrative embodiment, the accumulator provides FRSIand TRSOas output values. In some embodiments, the accumulator104also receives one or more additional inputs, such as an external timing reference TREFand a reset signal TRESET. The accumulator104can periodically update the output values FRACRSI, FRACRSO, FRSI, TRSO. For example, in some embodiments, the output values are updated by the accumulator104during each cycle of the processor clock, TDSP.

The interpolation factor module, or circuit106receives the output values FRACRSI, FRACRSO, FRSI, TRSOfrom the accumulator104and derives an interpolation factor p from one or more of the received values. The interpolation factor module106can also process one or more of the inputs to generate an output according to the processor clock, TDSP. The rate converter102receives the interpolation factor p from the interpolation factor module106and uses this value to accomplish the desired sample rate conversion.

In some embodiments, the interpolation factor module106also receives a delay input value, TDELAY. The delay value can be provided by a user to introduce a skew between the different clock domains. The delay value can also be used to arbitrarily delay the output sampled signal with respect to the input sampled signal. The maximum delay that can be accommodated by a realizable system will depend at least to some extent upon provisions of the particular embodiment. For example, a look-ahead buffer can be included to accommodate such delayed values, as described in more detail below. In such embodiments, the depth of the look-ahead buffer can be determined based on the longest anticipated delay. Longer delays require deeper look-ahead buffers.

Referring toFIG. 2, an exemplary embodiment of an accumulator150according to the present invention, such as the accumulator104shown inFIG. 1, includes an accumulating register152. The accumulating register152stores a value N that is incremented with each processor clock cycle. The value of N can be a binary integer that is incremented by one after each processor clock cycle. The value of N may be reset to zero or another value upon receipt of a reset signal RESET at a reset input. The accumulator150also includes registers for storing various values, such as a processor register154for storing a value indicative of the processor clock period TDSP, an input clock domain register156for storing a value indicative of the input sample period TRSI, and an output clock domain register158for storing a value indicative of the output sample period TRSO. The values of the accumulating register152and the processor clock period TDSPare fed to a multiplier160that multiplies the values together and stores the resulting value TNin a processor time register162. The stored processor time value TNis fed to a first modulo arithmetic processor164atogether with the TRSIvalue stored in the input clock domain register156. The result of the first modulo operation is FRACRSI, a fractional portion of the ratio of the two values: TNand TRSI. The resulting value FRACRSIis stored in an input phase difference register166. Similarly, the stored processor time value TNis also fed to a second modulo arithmetic processor164btogether with the TRSOvalue stored in the output clock domain register158. The result of the second modulo operation is FRACRSO, a fractional portion of the ratio of the two values: TNand TRSO. The resulting value FRACRSOis stored in an output phase difference register168.

In some embodiments, an inverse of the value stored in the input clock domain register156is stored in an input clock domain frequency register170. Similarly, in some embodiments, an inverse value stored in the output clock domain register158is stored in an output clock domain frequency register172. One or more of the stored register values FRACRSI, FRACRSO, FRSI, FRSO, can be forwarded to the interpolation factor module106(FIG. 1). In the illustrative embodiment, four values are forwarded to the interpolation factor module106: FRACRSI, FRACRSO, FRSI, and TRSO.

A timing diagram illustrating an exemplary relationship between different timing signals according to the present invention is illustrated inFIG. 3. The diagram shows a possible relationship between the three clocks of interest (although the process described applies to arbitrary relationships between the clocks). In particular, a portion of a processor clock200, sometimes referred to as a DSP clock, is illustrated having a period TDSP. Just below the DSP clock, an overlapping portion of an input sample clock202, sometimes referred to as a re-sampler in clock, is illustrated having a period TRSI. Finally, an overlapping portion of an output sample clock204, sometimes referred to as a re-sampler out clock, is illustrated at the bottom of the figure having a period TRSO.

The FRAC term is used to describe the time measured from an event to the next clock cycle, as opposed to a “residual,” which by some conventions refers to the time looking forward from a clock cycle to the next event. The FRAC values are provided with respect to the DSP clock obtained from a clock generator section, described in more detail below. Thus, FRACRSIis the time from a re-sampler in clock event looking forward to the next DSP clock event. Similarly, FRACRSOis the time from a re-sampler out clock event looking forward to the next DSP clock event.

In some embodiments, the interpolation factor calculation module106(FIG. 1) calculates the interpolation factor p from the FRACRSIvalue of the converter clock (re-sampler input, TRSI), and the FRACRSOof the user clock (re-sampler output, TRSO). The interpolation factor is defined by
p=Tx/TRSI(1)

Tx is derived from the FRAC values by
Tx=TRSO−(FRACRSO−FRACRSI)  (2)

as can be observed from the relative arrangement of clock signals illustrated inFIG. 3.

The value of p, the interpolation factor, can be derived from the re-sampler input and re-sampler output time accumulator FRACRSIand FRACRSOvalues:

in which TDELAYis an arbitrary delay that may be introduced according to an intended application;
FracRSO=TN⊕TRSO; and  (4)
FRACRSI=TN⊕TRSI.  (5)

The symbol ⊕ refers to the modulo operator. In a sample rate conversion system, the integer portion of p is interpreted as an input data look ahead, and the fractional portion is interpreted as the penetration into the current input clock cycle of the current output clock cycle. An embodiment of an interpolation factor210is illustrated inFIG. 4. The interpolation factor210may include a number of positional digits (e.g., bits for a binary system) arranged to include integer portion212, and a fractional portion214, separated by a radix point215. The fractional portion214of the interpolation factor210is further subdivided into an upper fractional portion216, including the more significant positional digits (e.g., upper bits) of the fractional portion214of the interpolation factor210, and a lower fractional portion218, including the less significant positional digits (lower bits) of the fractional portion214of the interpolation factor210. The particular number of positional digits may vary depending upon an intended application. In some embodiments, such as those not including a look ahead buffer, the integer portion212is not included, as it is not necessary.

In a sample rate conversion system employing a polyphase filter and linear interpolator the interpolation factor210is implemented as a binary number, in which the upper bits216of the fractional portion of p214are interpreted as the polyphase sub-filter number, and the lower bits218of the fractional portion of p214are interpreted as the linear interpolation factor. The integer portion212, when present, can be interpreted as a look ahead value. For an exemplary value of p having 24 bits accuracy, the integer portion212can include 3 bits, the most significant fractional portion216can include 9 bits, and the least significant fractional portion218can include 12 bits.

Referring toFIG. 5, a flow diagram is shown illustrating an exemplary process220for accomplishing sample rate converter according to the present invention. In a first step222, sampled input data at an input sample data rate TRSIis received. In a next step224, a value related to a user output sample rate TRSOis received. In some embodiments, this value can be programmed by a user. At step226, phase relationships are determined between each of the input and output sample rates or domains and a processor clock or domain. These phase relationships can be represented as the fractional values described above with respect toFIG. 3, FRACRSI, FRACRSO. In a subsequent step228, an interpolation factor p is determined from the determined phase relationships FRACRSI, FRACRSOand the input clock domain and output clock domain values TRSI, TRSO. Once obtained, the interpolation factor p can be used in a subsequent step230to generate sampled output data indicative of the input sampled data re-sampled to the output sample data rate.

Referring toFIG. 6, a block diagram of an exemplary circuit240is illustrated for determining an interpolation factor, such as the interpolation factor module106(FIG. 1). The interpolation factor circuit240includes a sign inverter242inverting a sign of a digital input value i_frac_rso, indicative of the FRACRSOvalue. Operation of the sign inverter242would depend upon the nature in which the digital data is stored. The sign-inverted digital input value i_frac_rso (FRACRSO) is then combined with digital input value i_frac_rsi, indicative of FRACRSIand digital input value i_t_rso, indicative of TRSOin a combiner, such as the summer244shown. The output value of the summer244is a digital word indicative of the value Tx (FIG. 3). The interpolation factor circuit240also includes a multiplier246multiplying the digital word indicative of the value Tx with a digital input value i_f_rsi, indicative of FRSI. In some embodiments, the interpolation factor circuit240includes a divider instead of the multiplier246. In those embodiments the i_f_rsi value would be replaced by the value TRSIwhich is the inverse of i_f_rsi as shown inFIG. 10. The value output from the multiplier (divider) is the interpolation factor p.

Illustrated inFIG. 7are schematic representation of exemplary registers used in the interpolation factor circuit ofFIG. 6. In some embodiments, the p ratio calculation has a 40 bit input resulting from the Txcalculation, shown here with 15 integer bits and 25 fractional bits. The p-ratio calculation also has a 40 bit input from the FRSIvalue, of which 2 bits are integer, and 38 bits are fractional. A 25 bit accurate multiplication can be performed from these two 40 bit inputs, as shown. A hardware multiplier block, commercially available from Altera Corp., of San Jose, Calif., provides a 36 bit accurate multiplication, which is sufficient for this purpose.

Referring toFIG. 8, a block diagram of an exemplary embodiment of a rate-converting digitizer300is shown. The rate-converting digitizer300includes a look-ahead buffer302receiving input sampled data, i_converter_data [23:03]. The look ahead buffer302includes one or more outputs coupled to one or more digital filters. For example, the look ahead buffer302includes a first output to a polyphase filter304and a second output to a delta filter306. Each of the filters304,306receives a respective input from the look-ahead buffer302. Filter outputs are input to a linear interpolator308, that provides an output to a decimating finite impulse response (FIR) low-pass filter. In some embodiments, portions of the rate-converting digitizer300are substantially duplicated forming more than one path, such as separate high-frequency and low-frequency paths, each tailored to respective operating parameters. When more than one paths are provided (not shown), a multiplexer or other suitable selection device is used to select among the different paths. In some embodiments, such a selection device can be configured to select a bypass path, substantially bypassing the rate-conversion processing.

Also included is an interpolation factor calculation module312. The interpolation factor calculation module312receives four input digital values from one or more accumulators (not shown), such as: i_frac_rsi [39:0] indicative of FRACRSI; i_fra_rso [32:0], indicative of FRACRSO; i_f_rsi [39:0], indicative of FRSI; and i_t_rso [32:0], indicative of TRSO. The interpolation factor calculation module312provides an interpolation factor p as an output, calculated from the various input values. Any complexity of this function on the rate-converting circuit comes from the fact that the digitizer DSP clock can be different from the converter clock. In some embodiments, at least a portion of the interpolation factor is routed to the look ahead buffer302, the polyphase filter304, the delta filter306, and the linear interpolator308. The interpolation factor p represents the position of the output sample, or user, clock relative to the input sample, or converter (e.g., ADC) clock cycle. The upper bits of the fractional portion of the interpolation factor p can be used to select from among the polyphase and delta filter set304,306. The lower bits of the fractional portion of the interpolation factor p can be used to scale the linear interpolator308. In the rate-converting digitizer300, the integer portion of p is interpreted as data look ahead. Thus, an integer portion of the interpolation factor p is forwarded to the look ahead buffer302, a first fractional portion, the most significant bits, of a fractional portion of the interpolation factor are routed to the polyphase and delta filters304,306, and a second fractional portion, the least significant bits of the fractional portion of the interpolation factor, are routed to the linear interpolator308.

All or at least part of the rate-converting digitizer300can be implemented in a field-programmable gate array (FPGA) using digital signal processing (DSP) techniques known to those skilled in the art. One or more of the polyphase filter304, the delta filter306and any other filters, such as a low-pass, or anti-aliasing filter can be digital filters. As digital filters, they are at least in part defined by filter coefficients. Such filter coefficients can be determined according to standard design practices for designing digital filters. For example, the polyphase filter304has 16 taps and 512 phase sets which results in 8192 coefficients. Local memory318a,318b,318c(generally318) for storing the filter coefficients is provided. The coefficient memory318layout can be optimized to make use of available memory blocks. These memory blocks will be treated in the FPGA design as read-only memory (ROM), so there will be no explicit control circuitry needed to load them.

The rate-converting digitizer300converts data from a fixed sample rate A/D converter by means of a M/N interpolating polyphase filter304, linear interpolator308, and decimating FIR filters. The theory and operation of polyphase filters, linear interpolators, and decimating FIR filters is well know to those skilled in the art. See, for example, Chapt. 10,Introduction to Digital Signal Processing, by J. G. Proakis and D. K. Manolakis, 2nded., 1992, incorporated herein by reference in its entirety.

The look ahead pipeline302, when provided, accommodates interpolation factor values greater than one. In some embodiments, the look ahead pipeline302simply stores one or more extra samples in a polyphase filter input delay line, and thus gives the option of looking into the “future” by one or more samples, when necessary. The integer part of the interpolation factor drives a multiplexer to select the appropriate data set.

The linear interpolator can be implemented by determining (e.g., calculating) the current polyphase filter output, and the output for one coefficient set into the future, and then calculating an average of these two values, weighed by the fine interpolation factor. In order to conserve multiplier resources, this function can be implemented as a delta filter306, as shown. In this implementation the difference between coefficient sets is pre-calculated, resulting in a small difference value that can be handled with a small multiplier rather than a full size multiplier.

In some embodiments, an input analog signal is first band limited by an analog anti-aliasing filter (not shown). A design constraint on the analog filtering stop band is that substantially no A/D alias signals can show up below the highest decimating FIR stop band. In this case that frequency would be exactly A/D Nyquist.

A rate-converting source configuration340is illustrated inFIG. 9. A source configuration refers to sample conversion in which the rate-converting source300takes user data in at an Fuserrate and produces data at a modulation source, or converter rate. The theory and implementation of the source re-sampler are similar to that of the rate-converting digitizer300(FIG. 8), with at least three main differences. First, the number of filter taps may differ; the filter coefficient values may differ; and the fact that the re-sampler output frequency can be an integer sub-multiple of the DSP clock rate (e.g., FDSP=N FRSO). The last difference simplifies the rate-converting source architecture in that the interpolation factor p is a positive value, less than one, i.e., 0≦p<1.

In the exemplary embodiment, digital value i_user_data [23:0] is received, indicative of user data at rate Fuser. The user data may be received in a look ahead pipeline342, as illustrated. The source configuration340also includes a polyphase filter344, a delta filter346, a linear interpolator348, and an interpolation factor calculation module352, similar to the arrangement described above in relation toFIG. 8. Since the interpolation factor is less than one, there is no need to forward any integer portion to the look ahead pipeline342. The upper and lower bits of the interpolation factor are distributed to the filter bank344,346and the linear interpolator348as also described above in relation toFIG. 8. A re-sampled output digital signal is available at an output of the linear interpolator348, referred to herein as o_converter_data [23:0].

A schematic diagram of an exemplary embodiment of a interpolation factor calculation module360is illustrated inFIG. 10. The module360includes input and output accumulators362a,362b, a three-input adder364, and a divider366. The module360receives separate digital input values indicative of the input sample period TRSIand the output sample period TRSO. These sample period values TRSI, TRSOcan be stored in respective registers368a,368b. The module360also receives a digital input indicative of the system (i.e., DSP) clock TDSP. The input sample period TRSIis input as a limit into the input accumulator362a. The accumulator362ais incremented according to the processing clock TDSP. The input accumulator362acomputes a fractional output FRACRSI, providing it as an output to a first input of the adder364. Similarly, the output sample period TRSOis input as a limit into the output accumulator362b. The output accumulator362bis also incremented according to the processing clock TDSP. The output accumulator362bcomputes a fractional output FRACRSO, providing it as an output to a second input of the adder364. The second input of the adder364is sign-invert by techniques known to those skilled in the art, thereby subtracting the FRACRSOvalue from a determined sum. The input value TRSOis input into a third input of the adder364, such that the output of the adder364represents the value Tx (FIG. 3). In some embodiments, the output of the adder364is input into a first, dividend terminal of a divider circuit366. The input value TRSIcan be input into a second divisor input of the divider circuit366, such that an output value of the divider circuit quotient represents the interpolation factor p.

FIG. 11is a schematic diagram illustrating an exemplary embodiment of an accumulator400, suitable for either of the accumulators362a,362bofFIG. 10. A first accumulator400(362a) receives TRSIas a limit value and TDSPas an incrementing value. The input values are processed according to the schematic illustration, yielding the value FRACRSI. Similarly, a second accumulator400(362b) receives TRSOas a limit value and TDSPas an incrementing value. The input values are processed according to the schematic illustration, yielding the value FRACRSO.

TABLE 1SignalDefinitioni_f_rsi(FRSI/Fref)/┌log2(FRSI/Fref)┐i_t_rsoFref/FRSIi_frac_rsiTime from the last RSI clock to the currentDSP clocki_frac_rsoTime from the last RSO clock to the currentDSP clocki_t_skewTskew/Trefi_shift_multiplicand−|log2(TRSO+ TRSI+ Tskew,max)|i_shift_product┌log2FRSI┐ + |log2(TRSO+ TRSI+ Tskew,max)|

The interpolation factor p can be computed to 21 bit accuracy (to the right of the binary point) with a range of 0 to 1.5. The p calculation is:

To avoid a divide operation, the inverse of TRSIcan be pre-calculated.
p=(TRSO−FracRSO+FracRSI)(FRSI)  (7)

In applications where the range of input and output frequencies cover a large range, the interpolation factor calculation accuracy can be preserved by appropriate binary scaling of the interpolation factor factors, as shown inFIG. 13. The

In some embodiments, an integer relationship between the DSP clock and the re-sampler output frequency (FDSP=N FRSO) leads to simplifications to the interpolation factor calculation. For the source, it is assurable that 0≦p<1, thus there is no need for a look ahead pipeline.

In the following example, a user generates a 40 MHz BW signal sampled at 200 MHz. The user data is zero padded to bring the sample rate to 102 GHz (512×200 MHz). The 200 MHz sample rate images are attenuated by the polyphase FIR filter. The signal is applied to the converter which contains an internal four times (4×) interpolation filter. The interpolated signal, now at a 533 MHz sample rate, is converted to analog with a zero order hold (sin x/x) response. Lastly, the analog low pass filter removes the converter rate sampling images.

In reference to the sample rate converter shown inFIG. 8, the linear interpolator308multiplies the output of the delta filter306by the lower bits of the linear interpolation factor (e.g., lower bits218shown inFIG. 4). The exemplary 14-bit linear interpolation factor ranges from [0, 1). In the exemplary embodiment, the output of the linear interpolator308is right shifted (and sign extended) by a number of bits, e.g., 7 bits. This is done to compensate for situations in which the delta filter coefficients were scaled up by the same amount (e.g., by a factor of 27) before being stored in ROM318b. The output data of this block is then added to the output of the main polyphase filter304.

In some embodiments, the sample rate converter includes a bypass mode. When the bypass mode is set, at least a substantial portion of the sample rate converter including polyphase and decimating FIR filters is bypassed. Data enters the re-sampler at the FA/Drate, and then leaves the re-sampler at that same rate without any re-sampler processing. This mode provides user access to the raw ADC samples. Such access would be useful if the user were to perform an FFT on the captured data, the user would see frequency content up to converter Nyquist (FA/D/2). Bypass mode also allows the user to employ the data rate converter in an under sampling manner, provided that the analog front-end allows this situation. A tone at the ADC input greater than converter Nyquist is aliased back into the band between DC and FA/D/2. At this point, the data rate converter in bypass mode will not perform any processing on this captured data.

In some embodiments, the re-sampler low frequency input pipeline, data look ahead, delta filter, linear interpolation, and polyphase filter are implemented with a multi-cycle state machine. For example, one a multi-cycle state machine utilizes one 36×36 bit multiplier through which all of the signals can be processed. Such hardware efficiency is possible because the required output data rate is much slower than the FPGA DSP clock rate.

Referring toFIG. 12, a block diagram illustrating an alternative embodiment of an accumulator and interpolation calculator circuit600. The phase accumulator600keeps track of the state of the real time converter clocks, the virtual user clocks, and the relative phases between these clocks. This state and relative phase information can be used by a sample rate converter300,340(FIG. 8,FIG. 9) to convert the user's signals between the converter clock and user clock domains. The re-sampler300,340consists of an input data pipeline with look ahead302,342, a polyphase FIR filter304,344, and a linear interpolator308,348(FIG. 8,FIG. 9). The re-sampler340on a source channel (e.g.,FIG. 9) takes data in at a virtual user rate and produces data out at a fixed converter rate. The re-sampler300on a capture channel (e.g.,FIG. 8) takes data in at a fixed converter rate from the A/D converter and produces data out at a virtual user rate.

The accumulator can qualify re-sampler input data synchronous with the DSP clock. For example, there can be 0, 1, or 2 input data points qualified for every DSP clock. There can be 0 or 1 output data points qualified for every DSP clock. The accumulator600also tracks the state of the real time converter clocks. For example, the accumulator600tracks the state of each converter clock. A converter clock reset event resets the converter clock accumulators and the converter clocks so that these two are synchronized. This reset event also defines t0. A converter clock reset event typically happens after a power cycle, or other catastrophic event. The phase accumulator must match the converter clock frequencies exactly.

The accumulator600tracks the state of the virtual user clock. The user clock can be reset, corresponding to time t0. A reset of the user clock resets the user clock accumulators so that the exact run to run timing repeatability can be assured. Such user clock reset may occur at natural break points during normal operation, such as at the beginning of a test sequence in tester applications. The user clock can be tracked in terms of the fine resolution, or integer fractions thereof. Preferably, the user clock frequency programmability is binary fraction period based. In an exemplary embodiment, the user clock period has at least 10 ns/244resolution, and the user clock range is 5 kHz to 400 MHz.

In some embodiments, a delay or skew value TDELAYcan be added. Such a delay or skew value will effectively shift the analog waveform in time relative to a digital subsystem reference. Beneficially, such a delay value can be changed without requiring a subsequent reset of either the user clock or the converter clock. In some embodiments, the skew value has a range of 4 ns and a resolution of at least about 10 ns/232(that is, 0.0023 fs). In some embodiments, the value of TDELAYcan be set to zero, or ignored completely. For each re-sampler output data point, compute the re-sampler interpolation factor,
p=(Tx+TDELAY)/TRSI,  (8)
where TRSIis the re-sampler input clock period and Txis the time from the most recent re-sampler input clock that precedes the current DSP clock to the most recent re-sampler output clock in the current DSP clock cycle.

For applications in which tracking of the user clock is required in terms of a fine resolution value, it is necessary to have exact time accumulators operating in an exact underlying clock domain. Thus the user clock will be synthesized with constant period resolution. A method of translating the underlying events to the DSP clock domain is required. One such implementation provides a second set of (exact) phase accumulators602operating in the DSP clock domain that are synchronized to the underlying system clock domain at the coincidence point between the two domains. A second implementation would be to map every three underlying system clock domain user clock states directly into eight DSP domain user clock states.

The complication of having to calculate the interpolation factor from the states of two time accumulators comes from the fact that the DSP clock, re-sampler input, and re-sampler output frequencies are all different. This situation is simplified for embodiments in which the re-sampler output clock is the same as, or some simple multiple of the DSP clock.

The function of the underlying system clock domain user clock time accumulators is to keep track of the state of the user clocks in terms of underlying system clock cycles (t0being defined according to the value of an underlying system clock event plus a precision system clock phase value at the user clock reset event). At any given underlying system clock event the total number of fine resolution counts since t0needs to be known in order to be able to deterministically select a user clock cycle to match to a underlying system clock event. The time relative to the user clock also needs to be known as an input to the re-sampler interpolation factor calculation. For both of these needs, time from t0to the current underlying system clock event is actually measured.
tN=N Tref(9)
where tNis time since t0at the Nthunderlying system clock event, N is the number of underlying system clock cycles since t0, Trefis the period of the system clock, underlying system clock, i.e., 10 ns.

By expressing tNin terms of the user clock period, the fractional value FRAC can determine the time since the last user clock (as opposed to residue, which would be the time to the next user clock). This can be represented mathematically by
Fracuser=tN⊕Tuser,  (10)
in which FRACuseris the time from the last user clock, Tuseris the user clock period, and, ⊕ is the modulo operator. The method of measuring the time from the last user clock is preferable to the residue method for this application, because of the situation in which there are multiple virtual clock events per reference clock. In this case multiple residue values would need to be generated, whereas a single time from the last user clock (i.e., FRAC) value is sufficient.

In general, a user clock synthesized from a reference clock will be a rational fraction of the reference clock, that is,

Fuser=Fref⁢AB,(11)
or in terms of time,

Tuser=Tref⁢BA.(12)
The A term can be fixed so that Trefcan be expressed as A Tresolution, thus combining equations (9), (10), and (12) gives

The function N A⊕B is implemented in hardware as a modulo-B accumulator where the value A=Tref/Tresolutionis pre-calculated and then accumulated on each underlying system clock cycle.

Since the re-sampler operations happen on system, or DSP clock cycles, the underlying system clock domain time accumulator values are mapped to the DSP clock domain. If this mapping is done without long term feedback then any errors introduced will not accumulate; thus the mapping can be approximate. The values shown below are for exemplary clock frequencies of a re-sampler instrument.
Frac′user≈Tresolution(N A′⊕B)  (15)

The converter clock time accumulators are the same as the user clock time accumulators except that the converter clock accumulators are reset by a converter clock reset event, rather than by the user clock reset event. The converter clock frequencies are much more limited than the user clock frequencies so a low resolution accumulator will be acceptable.

The case in which the re-sampler output clock is coincident with the DSP clock is treated as the virtual re-sampler clock occurring “after” the DSP clock, leading to the implication that FRAC values are always greater than zero.

In an exemplary embodiment, a user clock range requirement is 340 MHz down to 5 kHz. The user clock time accumulator must therefore be able to count

1/(5⁢⁢kHz)10⁢⁢ns=20,000<215-1,(18)
thus 14 bits are required to cover this range.

In some embodiments, user clocks are based on integer increments of period. In general one will not be able to achieve coherency between the analog and digital clocks, however one can get close enough for our applications. The areas of concern are (1) FFT outputs will have “leakage,” and therefore give erroneous results, and (2) there will be a slow phase drift between analog and digital signals over time.

The effect of frequency accuracy on sine wave signal to noise ratio, as measured by a rectangular window FFT analysis is known to be approximately. See, for example, “When ‘Almost’ is Good Enough: a Fresh Look at DSP Clock Rates,” Rosenfiled and Max, International Test Conference, 1988, incorporated herein by reference in its entirety.

SNR=T/2(T3/24)⁢(ω1-ω2)2(19)
where T is the duration of the captured and analyzed signal, ω1is the actual sine wave frequency, and ω2is the ideal sine wave frequency, which can be expressed as

SNR=3M2⁢e2⁢π2(20)
where M is the number of sine wave cycles analyzed, and e is the relative frequency error.

Tests conducted using a simulation software application indicated that the correlation is better than 0.1 dB. For a Nyquist frequency, about half of the noise power is concentrated in the M-1 bin, so there is an SFDR limitation of SNR+3 dB. With large FFTs (considering a practical limit of 64 k) and low noise instruments, The SFDR limitation due to non-coherent clocks should be better than 160 dB

A user clock resolution of 10 ns/244(5.6 E−22 seconds) is required to achieve 157 dB SNR. Using the 5.6 E−22 second user clock period resolution requirement, the worst case phase drift will be

The range of p is derived from the extreme values its contributing factors. Ignoring TDELAY, the minimum p value comes from

FRAC values range from (0, T], thus pMINis nearly zero. The maximum value of p follows from the maximum value of Tx, and consequently the minimum value of FRACRSO. Namely,

The minimum value of FRACRSOoccurs when the re-sampler output clock happens immediately before the DSP clock, then FRACRSO=TRSO−TDSP. Thus,

pMAX=TDSP+TRSITRSI.(27)
Note that for the special case shown below in which TRSO=K TDSP. K being an integer, and with the re-sampler input clock TRSOand the DSP clock TDSPaligned in phase, FRACRSOalways equals TRSO. In such a case:

The interpolation factor p represents the relative phase of the re-sampler output clock to the re-sampler input clock. The re-sampler interpolates an output value by applying two of the all pass polyphase sub-filters (with incremental delay values bracketing the ideal relative phase) and then interpolating linearly between the two results. The SNR of such a re-sampler is known to be

SNRfilter≥80⁢Ifilter4ωx4,(29)
in which Ifilteris the number of polyphase sub-filters, and ωxis the relative bandwidth, 2πBWuser/FRSI. See, for example, as described inIntroduction to Digital Signal Processing, by J. G. Proakis and D. K Manolakis, 2nded., 1992. Furthermore, the linear interpolator itself is in fact a polyphase filter with an SNR of

Any automated test equipment, instrumentation, or communications system would benefit from this invention, because it leads to simplifications in the design and implementation of waveform digitizers, arbitrary waveform generators, modulation, and de-modulation systems.

While the preferred embodiment and various alternative embodiments of the invention have been disclosed and described in detail herein, it may be apparent to those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope thereof.

It should be noted that the examples illustrated herein should in no way be interpreted as limited the spirit and scope of the present invention in any way. The specific examples and implementations are shown here for purposes of illustration only. And, while in the preferred embodiment the number of states in the filter may remain unaltered when modified to perform sample rate conversion, in alternative embodiments, additional states may be added without departing from the spirit and scope of the present invention.