MULTI-PATH AMPLIFICATION CIRCUIT FOR OPERATING IN DIFFERENT POWER MODES

Certain aspects of the present disclosure generally relate to an amplification circuit. The amplification circuit generally includes: a first amplification path comprising a first amplification transistor and coupled between an input node of the amplification circuit and an output node of the amplification circuit; and a second amplification path comprising a second amplification transistor and coupled between the input node and the output node, wherein the second amplification path further includes an attenuator coupled between the input node of the amplification circuit and a control input of the second amplification transistor.

FIELD OF THE DISCLOSURE

Certain aspects of the present disclosure generally relate to electronic components and, more particularly, to circuitry for signal amplification.

BACKGROUND

SUMMARY

Certain aspects of the present disclosure are directed towards an amplification circuit. The amplification circuit generally includes: a first amplification path comprising a first amplification transistor and coupled between an input node of the amplification circuit and an output node of the amplification circuit; and a second amplification path coupled between the input node and the output node of the amplification circuit and comprising a second amplification transistor and an attenuator coupled between the input node of the amplification circuit and a control input of the second amplification transistor.

Certain aspects of the present disclosure are directed towards a method for signal amplification. The method generally includes: determining a power mode for an amplification circuit; selecting a first amplification path or a second amplification path based on the determined power mode, wherein the first amplification path includes a first amplification transistor coupled to an output node of the amplification circuit, and wherein the second amplification path includes a second amplification transistor coupled to the output node and an attenuator coupled to a control input of the second amplification transistor; and amplifying an input signal via the first amplification path or the second amplification path based on the selection.

Certain aspects of the present disclosure are directed towards an apparatus for signal amplification. The apparatus generally includes: first means for amplifying an input signal at an input node, the first means for amplifying being coupled between the input node and an output node; means for attenuating the input signal to yield an attenuated signal, the means for attenuating being coupled to the input node; and second means for amplifying the attenuated signal, the second means for amplifying being coupled between the means for attenuating and the output node.

DETAILED DESCRIPTION

Certain aspects of the present disclosure generally relate to techniques and apparatus for signal amplification using different amplification paths allowing for operating in different power modes. For example, certain aspects provide an amplification circuit that may be operable in a low-power mode (LPM) and a high-power mode (HPM). The amplification circuit may include an amplification path for the LPM and an amplification path for the HPM. The amplification path for the LPM may include an attenuator for generating an attenuated signal for amplification when operating in LPM, whereas the amplification path for the HPM may not include such an attenuator. Having separate amplification paths allows an attenuator to be implemented in the amplification for the LPM with little to no impact on the amplification path for the HPM. A first bias circuit may be used to bias the first amplification path, and a second bias circuit may be used to bias the second amplification path. In some aspects, a current source may be selectively coupled to the first bias circuit or the second bias circuit based on whether the amplification circuit is operating in LPM or HPM. In some aspects, an on-die HBT transistor may be used to function as an attenuator. For example, the attenuator may be tunable via a transistor (e.g., a heterojunction bipolar transistor (HBT)) and the transistor may be implemented on the same semiconductor die as a drive amplifier (DA) and/or power amplifier (PA) for the signal amplification.

Example Wireless Communications

FIG.1illustrates a wireless communications system100with access points110and user terminals120, in which aspects of the present disclosure may be practiced. For simplicity, only one access point110is shown inFIG.1. An access point (AP) is generally a fixed station that communicates with the user terminals and may also be referred to as a base station (BS), an evolved Node B (eNB), a next generation Node B (gNB), or some other terminology. A user terminal (UT) may be fixed or mobile and may also be referred to as a mobile station (MS), an access terminal, user equipment (UE), a station (STA), a client, a wireless device, or some other terminology. A user terminal may be a wireless device, such as a cellular phone, a personal digital assistant (PDA), a handheld device, a wireless modem, a laptop computer, a tablet, a personal computer, etc.

Access point110may communicate with one or more user terminals120at any given moment on the downlink and uplink. The downlink (i.e., forward link) is the communication link from the access point to the user terminals, and the uplink (i.e., reverse link) is the communication link from the user terminals to the access point. A user terminal may also communicate peer-to-peer with another user terminal. A system controller130couples to and provides coordination and control for the access points.

Wireless communications system100employs multiple transmit and multiple receive antennas for data transmission on the downlink and uplink. Access point110may be equipped with a number Nap of antennas to achieve transmit diversity for downlink transmissions and/or receive diversity for uplink transmissions. A set Nuof selected user terminals120may receive downlink transmissions and transmit uplink transmissions. Each selected user terminal transmits user-specific data to and/or receives user-specific data from the access point. In general, each selected user terminal may be equipped with one or multiple antennas (i.e., Nut≥1). The Nuselected user terminals can have the same or different number of antennas.

Wireless communications system100may be a time division duplex (TDD) system or a frequency division duplex (FDD) system. For a TDD system, the downlink and uplink share the same frequency band. For an FDD system, the downlink and uplink use different frequency bands. Wireless communications system100may also utilize a single carrier or multiple carriers for transmission. Each user terminal120may be equipped with a single antenna (e.g., to keep costs down) or multiple antennas (e.g., where the additional cost can be supported). In some aspects, the user terminal120or access point110may include an amplifier implemented with multiple amplification paths for operating in different power modes.

On the uplink, at each user terminal120selected for uplink transmission, a TX data processor288receives traffic data from a data source286and control data from a controller280. TX data processor288processes (e.g., encodes, interleaves, and modulates) the traffic data {dup} for the user terminal based on the coding and modulation schemes associated with the rate selected for the user terminal and provides a data symbol stream {sup} for one of the Nut,mantennas. A transceiver front end (TX/RX)254(also known as a radio frequency front end (RFFE)) receives and processes (e.g., converts to analog, amplifies, filters, and frequency upconverts) a respective symbol stream to generate an uplink signal. The transceiver front end254may also route the uplink signal to one of the Nut,mantennas for transmit diversity via an RF switch, for example. The controller280may control the routing within the transceiver front end254. Memory282may store data and program codes for the user terminal120and may interface with the controller280.

A number Nupof user terminals120may be scheduled for simultaneous transmission on the uplink. Each of these user terminals transmits its set of processed symbol streams on the uplink to the access point.

At access point110, Napantennas224athrough224apreceive the uplink signals from all Nupuser terminals transmitting on the uplink. For receive diversity, a transceiver front end222may select signals received from one of the antennas224for processing. The signals received from multiple antennas224may be combined for enhanced receive diversity. The access point's transceiver front end222also performs processing complementary to that performed by the user terminal's transceiver front end254and provides a recovered uplink data symbol stream. The recovered uplink data symbol stream is an estimate of a data symbol stream {sup} transmitted by a user terminal. An RX data processor242processes (e.g., demodulates, deinterleaves, and decodes) the recovered uplink data symbol stream in accordance with the rate used for that stream to obtain decoded data. The decoded data for each user terminal may be provided to a data sink244for storage and/or a controller230for further processing.

On the downlink, at access point110, a TX data processor210receives traffic data from a data source208for Ndnuser terminals scheduled for downlink transmission, control data from a controller230and possibly other data from a scheduler234. The various types of data may be sent on different transport channels. TX data processor210processes (e.g., encodes, interleaves, and modulates) the traffic data for each user terminal based on the rate selected for that user terminal. TX data processor210may provide a downlink data symbol streams for one of more of the Ndnuser terminals to be transmitted from one of the Napantennas. The transceiver front end222receives and processes (e.g., converts to analog, amplifies, filters, and frequency upconverts) the symbol stream to generate a downlink signal. The transceiver front end222may also route the downlink signal to one or more of the Napantennas224for transmit diversity via an RF switch, for example. The controller230may control the routing within the transceiver front end222. Memory232may store data and program codes for the access point110and may interface with the controller230.

At each user terminal120, Nut,mantennas252receive the downlink signals from access point110. For receive diversity at the user terminal120, the transceiver front end254may select signals received from one or more of the antennas252for processing. The signals received from multiple antennas252may be combined for enhanced receive diversity. The user terminal's transceiver front end254also performs processing complementary to that performed by the access point's transceiver front end222and provides a recovered downlink data symbol stream. An RX data processor270processes (e.g., demodulates, deinterleaves, and decodes) the recovered downlink data symbol stream to obtain decoded data for the user terminal. In some aspects, the transceiver front end254or222may include an amplifier implemented with multiple amplification paths for operating in different power modes.

FIG.3is a block diagram of an example transceiver front end300, such as transceiver front ends222,254inFIG.2, in which aspects of the present disclosure may be practiced. The transceiver front end300includes at least one transmit (TX) path302(also known as a “transmit chain”) for transmitting signals via one or more antennas and at least one receive (RX) path304(also known as a “receive chain”) for receiving signals via the antennas. When the TX path302and the RX path304share an antenna303, the paths may be connected with the antenna via an interface306, which may include any of various suitable radio frequency (RF) devices, such as a switch, a duplexer, a diplexer, a multiplexer, and the like.

Receiving in-phase (I) and/or quadrature (Q) baseband analog signals from a digital-to-analog converter (DAC)308, the TX path302may include a baseband filter (BBF)310, a mixer312, a driver amplifier (DA)314, and a power amplifier (PA)316. The BBF310, the mixer312, the DA314, and the PA316may be included in a radio frequency integrated circuit (RFIC). In some cases, the PA316may be external to the RFIC.

The BBF310filters the baseband signals received from the DAC308, and the mixer312mixes the filtered baseband signals with a transmit local oscillator (LO) signal to convert the baseband signal of interest to a different frequency (e.g., upconvert from baseband to RF). This frequency-conversion process produces the sum and difference frequencies between the LO frequency and the frequencies of the baseband signal of interest. The sum and difference frequencies are referred to as the “beat frequencies.” The beat frequencies are typically in the RF range, such that the signals output by the mixer312are typically RF signals, which may be amplified by the DA314and/or by the PA316before transmission by the antenna303. In some aspects, the DA314and/or the PA316may be implemented with multiple amplification paths for operating in different power modes. While one mixer312is illustrated, several mixers may be used to upconvert the filtered baseband signals to one or more intermediate frequencies and to thereafter upconvert the intermediate frequency (IF) signals to a frequency for transmission.

The RX path304includes a low noise amplifier (LNA)322, a mixer324, and a baseband filter (BBF)326. The LNA322, the mixer324, and the BBF326may be included in a radio frequency integrated circuit (RFIC), which may or may not be the same RFIC that includes the TX path components. RF signals received via the antenna303may be amplified by the LNA322, and the mixer324mixes the amplified RF signals with a receive local oscillator (LO) signal to convert the RF signal of interest to a different baseband frequency (i.e., downconvert). The baseband signals output by the mixer324may be filtered by the BBF326before being converted by an analog-to-digital converter (ADC)328to digital I and/or Q signals for digital signal processing.

Certain transceivers may employ frequency synthesizers with a variable-frequency oscillator (e.g., a voltage-controlled oscillator (VCO) or a digitally controlled oscillator (DCO)) to generate a stable, tunable LO with a particular tuning range. Thus, the transmit LO frequency may be produced by a TX frequency synthesizer318, which may be buffered or amplified by amplifier320before being mixed with the baseband signals in the mixer312. Similarly, the receive LO frequency may be produced by an RX frequency synthesizer330, which may be buffered or amplified by amplifier332before being mixed with the RF signals in the mixer324. In some cases, a single frequency synthesizer may be used for both the TX path302and the RX path304.

Example Multi-Path Amplification Circuit

Some wireless devices may use a multi-mode-multi-band (MMMB) power amplifier (PA), such that a single PA can support multiple modes and multiple frequency bands, to save cost and area. A typical MMMB PA shows good performance in high-power mode (HPM) when signal transmission is occurring with high power as the PA may be specifically tuned for HPM. However, in some conditions, the PA may not transmit with high power, and a low-power transmission may be sufficient for a user equipment (UE) to transmit a signal (e.g., to a base station). For a typical PA designed with a 30 dB gain (e.g., implemented by a 2-stage or 3-stage PA) in HPM, in low-power mode (LPM), the PA gain may be high (e.g., even with a lowered rail voltage (Vcc) and reference current (Iref) for the PA), which may cause a problem for meeting a high dynamic range transceiver specification.

Certain aspects of the present disclosure are directed towards an amplifier architecture implemented with an HPM amplification path and an LPM amplification path. With two amplification paths, the HPM performance may be maintained while implementing an attenuator for the LPM. For example, the LPM amplification path may include an attenuator providing tunability for low gain (e.g., with little to no impact on the performance of the HPM amplification path). In other words, if a single amplification path is used for both HPM and LPM and an attenuator is used on the single amplification path, the attenuator may most likely adversely impact the HPM performance. With separate amplification paths (e.g., including separate driver amplifiers (DAs)) for HPM and LPM, the attenuator generates an attenuated signal for the LPM amplification path with a significantly smaller impact on the HPM amplification path, compared to using a single amplification path. While the example attenuation technique described herein is described with respect to multiple amplification paths for driver amplifiers (e.g., referred to as “DA segmentation”), the aspects described herein may additionally or alternatively be implemented with PA segmentation. For example, multiple amplification paths may be used for power amplification with separate bias circuits for the amplification paths, in some aspects.

FIG.4illustrates an example amplification circuit400implemented with multiple amplification paths (e.g., DA paths, for implementing a DA, such as DA314ofFIG.3), in accordance with certain aspects of the present disclosure. As shown, the amplification circuit400may include a PA transistor462(e.g., for implementing the PA, such as PA316ofFIG.3), a DA transistor460(e.g., for implementing a DA for HPM), and a DA transistor486(e.g., for implementing a DA for LPM). One or more of the transistors460,486,462may be implemented as one or more heterojunction bipolar transistors (HBTs). The one or more HBTs may implemented on the same die (e.g., a gallium arsenide (GaAs) die) as the DA transistor460and/or PA transistor462. The DA transistor460may be part of an HPM amplification path490, and the DA transistor486may be part of an LPM amplification path492. The gain associated with each path may be set at least in part using the size of the associated DA transistor. For example, LPM gain may be set using the associated amplification path (e.g., via attenuation) and by configuration of the size of the DA transistor (e.g., transistor486), which may allow for the LPM gain to be reduced (e.g., as compared to the HPM gain).

Each of the amplification paths490,492may receive a bias signal. For example, a transistor434(e.g., also referred to herein as a “bias transistor”) may have an emitter coupled to a base of transistor460through a resistive element444. The collector of transistor434may be coupled to a voltage rail (e.g., coupled to a power source such as a battery providing a battery voltage (Vbatt)). A current source432may source a reference current (IrefDA_HPM) across a resistive element430, diodes438,440, and a resistive element442, generating a voltage at the base of transistor434. Thus, the transistor434may be biased, providing a bias signal (e.g., bias current) for biasing the transistor460.

Similarly, a transistor428may have an emitter coupled to a base of transistor486through a resistive element448. The collector of transistor428may be coupled to the voltage rail (e.g., through a resistive element418). A current source414may source a reference current (IrefDA_LPM) across a resistive element416, diodes422,424, and a resistive element420, generating a voltage at the base of transistor428. Thus, the transistor428may be biased, providing a bias signal (e.g., bias current) for biasing the transistor486.

As shown, the amplification path490may include a ballasting capacitive element446, and the amplification path492may include a ballasting capacitive element450. The collectors of transistors460,486may be coupled to a DA output node498. The DA output node498may be coupled to an input of the PA (e.g., a base of transistor462) through an inter-stage matching circuit456for impedance matching. The collector of transistor462may be coupled to an output node497(e.g., having an output RF signal labeled “Rfout”) of the PA, providing a signal for transmission (e.g., through an output impedance matching circuit499). As shown, a reference current (IrefPA) may be provided for biasing the PA (e.g., transistor462). For example, a transistor472may have an emitter coupled to the base of transistor462through a resistive element458. The collector of transistor472may be coupled to the voltage rail. A current source487may source a reference current (IrefPA) across a resistive element468and diodes464,466, generating a voltage at the base of transistor472. Thus, the transistor472may be biased, providing a bias signal for biasing the transistor462.

In some aspects of the present disclosure, an attenuator may be implemented for the LPM amplification path492. For example, the attenuator may include a resistive element452coupled between an input node451and node453. In some aspects, a resistive element482may be coupled between node453and a collector of a transistor480. The transistor480may be implemented as a HBT (e.g., GaAs transistor). The emitter of transistor480may be coupled to a reference potential node (e.g., electrical ground), as shown. An input impedance matching circuit454(e.g., for impedance matching) may be coupled between the input node451and the resistive element452.

In some aspects, the transistor480may be biased to tune the attenuator. For example, transistor412may have an emitter coupled to a base of transistor480through a resistive element478. In some aspects, a capacitive element484may be coupled between the base and the collector of transistor480. The capacitive element484may be used to tune the attenuator for a specific frequency band. The collector of transistor412may be coupled to the voltage rail, as shown.

A current source402may source a reference current (Irefattn) across a resistive element404, diodes406,408, and a resistive element410, generating a voltage at the base of transistor412. Thus, the transistor412may be biased, providing a bias signal for biasing transistor480to set an attenuation level of the attenuator (e.g., by adjusting the impedance between node453and the reference potential node (e.g., electrical ground)). As described, the attenuator is implemented for the LPM amplification path and provides attenuation for operating in LPM with little to no impact on the HPM amplification path.

FIG.5illustrates an example amplification circuit500with multiple amplification paths and a shared current source502for LPM and HPM, in accordance with certain aspects of the present disclosure. Reference currents for the amplification circuit500may be provided by a residual current device (RCD). By using a same current source502for the LPM and HPM, the cost of the RCD may be reduced (e.g., the RCD may not have to provide separate reference currents for the LPM and HPM). The amplification circuit500may either operate in LPM or HPM. Therefore, the current source502may be selectively coupled (e.g., via switch504) to resistive element416or430for biasing either the transistor428or the transistor434. In other words, when current source502is coupled to resistive element416, a voltage is generated at the base of transistor428, generating a bias signal for the LPM amplification path492, and when current source502is coupled to resistive element430, a voltage is generated at the base of transistor434, generating a bias signal for the HPM amplification path490. By using a common current source502, the number of current sources for implementing the amplification circuit500may be reduced as compared to amplification circuit400, reducing area and power consumption.

In some aspects, the amplification circuit500may be implemented with constant attenuation (e.g., with an attenuator having an attenuation level that is not tunable). For example, the attenuator may include resistive element452in the LPM amplification path492. Implementing the amplification circuit with multiple amplification paths may allow for constant attenuation to be used for LPM (e.g., since amplification path492including the attenuator is designated for only LPM operation as opposed to having to support both LPM and HPM).

Certain aspects of the present disclosure provide a dual amplifier implementation for a MMMB PA with an integrated HBT attenuator design that can maintain HPM performance while providing tunability for lowering the gain for the LPM. Programmable LPM gain may be realized with little to no impact on the HPM path. In addition to the attenuator, attenuation may be configured for the LPM amplification path by setting the HBT emitter length and width (e.g., for transistor428). The dual amplifier implementation described herein can be used to tune the HPM path and the LPM path differently.

FIG.6is a flow diagram depicting example operations600for signal amplification, in accordance with certain aspects of the present disclosure. For example, the operations600may be performed by an electrical device including an amplification circuit, such as the amplification circuit400or amplification circuit500.

The operations600begin, at block602, with the electrical device determining a power mode (e.g., LPM or HPM) for an amplification circuit. At block604, the electrical device selects a first amplification path (e.g., amplification path490) or a second amplification path (e.g., amplification path492) based on the power mode. The first amplification path may include a first amplification transistor (e.g., transistor460) coupled to an output node (e.g., output node498) of the amplification circuit. The second amplification path may include a second amplification transistor (e.g., transistor486) coupled to the output node and an attenuator (e.g., resistive element452) coupled to a control input (e.g., gate) of the second amplification transistor. At block606, the electrical device amplifies an input signal via the first amplification path or the second amplification path based on the selection.

In some aspects, the electrical device attenuates, via the attenuator, the input signal to yield an attenuated signal and amplifies the attenuated signal with the second amplification transistor. The electrical device may determine a level of attenuation associated with the attenuator. The electrical device may generate, via a bias circuit, a bias signal for an attenuation transistor (e.g., transistor480) of the attenuator based on the level of attenuation. For example, the attenuator may include a resistive element (e.g., resistive element452) coupled in series between an input node (e.g., input node451) of the amplification circuit and the control input (e.g., gate) of the second amplification transistor. The attenuation transistor may be coupled between the resistive element and a reference potential node. The electrical device may bias the attenuation transistor with the bias signal. In some aspects, the bias circuit may include a bias transistor (e.g., transistor412) coupled between a voltage rail and a control input of the attenuation transistor. Generating the bias signal may include sourcing, via a current source, a current to a control input (e.g., gate) of the bias transistor.

In some aspects, the electrical device biases, via a first bias circuit (e.g., transistor434), the first amplification transistor based on the power mode being a HPM or biases, via a second bias circuit (e.g., transistor428), the second amplification transistor based on the power mode being a LPM. The first bias circuit may include a first bias transistor (e.g., transistor434) coupled between a voltage rail and a control input of the first amplification transistor, a control input of the first bias transistor being selectively coupled to a current source (e.g. current source502). The second bias circuit may include a second bias transistor (e.g., transistor428) coupled between the voltage rail and a control input of the second amplification transistor, a control input of the second bias transistor being selectively coupled to the current source. In some aspects, the electrical device is configured to selectively couple the current source (e.g., via switch504) to the first bias transistor or the second bias transistor based on the power mode.

Example Aspects

Aspect 1: An amplification circuit, comprising: a first amplification path comprising a first amplification transistor and coupled between an input node of the amplification circuit and an output node of the amplification circuit; and a second amplification path coupled between the input node and the output node of the amplification circuit and comprising a second amplification transistor and an attenuator coupled between the input node of the amplification circuit and a control input of the second amplification transistor.

Aspect 2: The amplification circuit of Aspect 1, wherein the attenuator comprises a first resistive element coupled in series between the input node and the control input of the second amplification transistor.

Aspect 3: The amplification circuit of Aspect 2, wherein the attenuator further comprises an attenuation transistor coupled between the first resistive element and a reference potential node.

Aspect 4: The amplification circuit of Aspect 3, wherein the attenuator further comprises a second resistive element coupled between the first resistive element and the reference potential node.

Aspect 5: The amplification circuit of Aspect 3 or 4, further comprising a bias circuit coupled to a control input of the attenuation transistor.

Aspect 6: The amplification circuit of Aspect 5, wherein the bias circuit comprises a bias transistor coupled between a voltage rail and the control input of the attenuation transistor, a control input of the bias transistor being coupled to a current source.

Aspect 7: The amplification circuit of Aspect 5 or 6, wherein the attenuation transistor includes a heterojunction bipolar transistor (HBT).

Aspect 8: The amplification circuit according to any of Aspects 3-7, wherein the attenuation transistor is on a same semiconductor die as the first amplification transistor, and wherein the attenuation transistor and the first amplification transistor are gallium arsenide (GaAs) transistors.

Aspect 9: The amplification circuit according to any of Aspects 1-8, wherein: the first amplification path includes a first driver amplifier (DA) segment comprising the first amplification transistor; the second amplification path includes a second DA segment comprising the second amplification transistor; and the amplification circuit further comprises a power amplifier (PA) having an input coupled to outputs of the first DA segment and the second DA segment.

Aspect 10: The amplification circuit according to any of Aspects 1-9, further comprising: a first bias circuit coupled to a control input of the first amplification transistor; and a second bias circuit coupled to the control input of the second amplification transistor.

Aspect 11: The amplification circuit of Aspect 10, wherein: the first bias circuit is configured to bias the first amplification transistor based on the amplification circuit operating in a high-power mode (HPM); and the second bias circuit is configured to bias the second amplification transistor based on the amplification circuit operating in a low-power mode (LPM).

Aspect 12: The amplification circuit of Aspect 10 or 11, wherein: the first bias circuit includes a first bias transistor coupled between a voltage rail and a control input of the first amplification transistor, a control input of the first bias transistor being coupled to a first current source; and the second bias circuit includes a second bias transistor coupled between the voltage rail and a control input of the second amplification transistor, a control input of the second bias transistor being coupled to a second current source.

Aspect 13: The amplification circuit of Aspect 12, wherein the first current source and the second current source comprise a same current source selectively coupled to the control input of the first bias transistor or the control input of the second bias transistor.

Aspect 14: The amplification circuit according to any of Aspects 1-13, further comprising: a first capacitive element coupled between the input node and a control input of the first amplification transistor; and a second capacitive element coupled between the input node and the control input of the second amplification transistor.

Aspect 15: A method for signal amplification, comprising: determining a power mode for an amplification circuit; selecting a first amplification path or a second amplification path based on the determined power mode, wherein the first amplification path includes a first amplification transistor coupled to an output node of the amplification circuit, and wherein the second amplification path includes a second amplification transistor coupled to the output node and an attenuator coupled to a control input of the second amplification transistor; and amplifying an input signal via the first amplification path or the second amplification path based on the selection.

Aspect 16: The method of Aspect 15, further comprising: attenuating, via the attenuator, the input signal to yield an attenuated signal; and amplifying the attenuated signal with the second amplification transistor.

Aspect 17: The method of Aspect 16, further comprising: determining a level of attenuation associated with the attenuator; generating, via a bias circuit, a bias signal for an attenuation transistor of the attenuator based on the level of attenuation, wherein the attenuator includes a resistive element coupled in series between an input node of the amplification circuit and the control input of the second amplification transistor, the attenuation transistor being coupled between the resistive element and a reference potential node; and biasing the attenuation transistor with the bias signal.

Aspect 18: The method of Aspect 17, wherein: the bias circuit comprises a bias transistor coupled between a voltage rail and a control input of the attenuation transistor; and generating the bias signal includes sourcing, via a current source, a current to a control input of the bias transistor.

Aspect 19: The method of Aspect 17 or 18, wherein the attenuation transistor includes a heterojunction bipolar transistor (HBT).

Aspect 20: The method according to any of Aspects 15-19, further comprising: biasing, via a first bias circuit, the first amplification transistor based on the determined power mode being a high-power mode (HPM); or biasing, via a second bias circuit, the second amplification transistor based on the determined power mode being a low-power mode (LPM).

Aspect 21: The method of Aspect 20, wherein: the first bias circuit includes a first bias transistor coupled between a voltage rail and a control input of the first amplification transistor, a control input of the first bias transistor being coupled to a current source; the second bias circuit includes a second bias transistor coupled between the voltage rail and a control input of the second amplification transistor, a control input of the second bias transistor being coupled to the current source; and the method further comprises selectively coupling the current source to the first bias transistor or the second bias transistor based on the power mode.

Aspect 22: An apparatus for signal amplification, comprising: first means for amplifying an input signal at an input node, the first means for amplifying being coupled between the input node and an output node; means for attenuating the input signal to yield an attenuated signal, the means for attenuating being coupled to the input node; and second means for amplifying the attenuated signal, the second means for amplifying being coupled between the means for attenuating and the output node.

Aspect 23: The apparatus of Aspect 22, further comprising: means for determining a power mode for the apparatus; and means for selecting the first means for amplifying the input signal or the second means for amplifying the attenuated signal based on the determined power mode.

The apparatus and methods described in the detailed description are illustrated in the accompanying drawings by various blocks, modules, components, circuits, steps, processes, algorithms, etc. (collectively referred to as “elements”). These elements may be implemented using hardware, for example.

One or more of the components, steps, features, and/or functions illustrated herein may be rearranged and/or combined into a single component, step, feature, or function or embodied in several components, steps, or functions. Additional elements, components, steps, and/or functions may also be added without departing from features disclosed herein. The apparatus, devices, and/or components illustrated herein may be configured to perform one or more of the methods, features, or steps described herein.