FET device manufacturing using a modified Ion implantation method

A method for manufacturing a semiconductor device exhibiting improved short channel effects and increased current driving ability is disclosed. The method includes the steps of: providing a substrate of a first conductivity-type, e.g., P-type; forming a gate insulating layer on the substrate; forming a gate electrode on the gate insulating layer; forming a gate cap insulating layer on the gate electrode; introducing inactive ions of the first conductivity-type into the first conductivity-type semiconductor substrate at both sides of the gate electrode, so as to form amorphous regions; forming first impurity regions of the first conductivity-type near the amorphous regions; and forming second impurity regions of a second conductivity-type, e.g., N-type, in the substrate at both sides of the gate electrode. The method also includes forming source and drain regions of the second conductivity-type in the substrate. The amorphous regions are formed by ion implantation of the inactive ions while the first and second impurity regions and the source and drain regions are formed by ion implantation of active ions. Inactive ions are ions which, after implantation into the amorphous regions, assume an atomic or molecular state in which they act neither as acceptors nor donors. Conversely, active ions act as acceptors or donors after implantation.

FIELD OF THE INVENTION

The present invention relates to a method for manufacturing a semiconductor device exhibiting improved short channel effects and increased current driving ability.

BACKGROUND OF THE INVENTION

A conventional method for manufacturing a semiconductor device will be discussed with reference to the attached drawings.

FIGS. 1ato 1dare cross-sectional views showing a conventional method for manufacturing a semiconductor device.

As shown inFIG. 1a, active regions and field regions are defined on a P-type semiconductor substrate1. A field oxide layer2is formed on the field regions. Subsequently, a first oxide layer, a polysilicon layer and a second oxide layer are successively formed on the entire surface. Utilizing a mask, the first oxide layer, the polysilicon layer, and the second oxide layer are patterned to form a gate oxide layer3, a gate electrode4, and a gate cap insulating layer5. P-type impurity ions are implanted at a tilt angle of 7°-20° into the semiconductor substrate1at both sides of the gate electrode4, thus forming first halo regions6.

Referring toFIG. 1b. P-type impurity ions are implanted at a tilt angle of 30°-60° into the substrate1at both sides of the gate electrode4, so as to form second halo regions7. In this case, the second halo regions7extend further underneath the gate electrode4than the first halo regions6, and have a more shallow depth than the first halo regions6.

Referring toFIG. 1c, lightly-doped N-type impurity ions are implanted into the semiconductor substrate1at both sides of the gate electrode4, thus forming a lightly doped drain (LDD) regions8.

Referring toFIG. 1d, utilizing a chemical vapor deposition (CVD) method, an oxide layer is formed on the entire surface and then subjected to etch-back, thus forming insulating sidewalls9on the both sides of the gate electrode4. With the gate electrode4and the gate insulating sidewalls9serving as masks, highly-doped N-type impurity ions are implanted into the semiconductor substrate1. This produces source and drain regions10in the P-type conductivity-type substrate1on both sides of the insulating sidewalls9. In this case, the depth of the first halo regions6is similar to that of the source and drain regions10, and the depth of the second halo regions7is similar to that of the LDD regions8, thereby improving short channel effects. Thus, the conventional manufacturing of a semiconductor device is completed.

Such a conventional method for manufacturing a semiconductor device has problems.

Ion implantation processes are performed twice to form the different halo regions. The halo regions6improve the breakdown voltage characteristics and the halo regions7improve short channel effects and adjust the threshold voltage. Consequently, the first and second halo regions overlap each other.

As channel lengths get shortened in highly integrated devices, increasingly high concentrations in the first halo region6are required to adjust a breakdown voltage. Consequently, the portions where the first and second halo regions overlap have an even higher doping concentration. As a result, it is hard to adjust threshold voltage using the portions having an overlap-increased, high doping concentration, which causes difficulties in carrying out a successful ion implantation process.

SUMMARY OF THE INVENTION

Therefore, the present invention is directed to a manufacturing method of a semiconductor device that substantially obviates one or more of problems due to limitations and disadvantages of the related art.

An object of the invention is to provide a method for manufacturing a semiconductor device exhibiting improved short channel effects, an increased breakdown voltage and improved current driving ability.

To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a method for manufacturing a semiconductor device is provided and includes the steps of: providing a substrate of a first conductivity-type, e.g., P-type; forming a gate insulating layer on the substrate; forming a gate electrode on the gate insulating layer; forming a gate cap insulating layer on the gate electrode; introducing inactive ions into the first conductivity-type semiconductor substrate at both sides of the gate electrode, so as to form amorphous regions; forming first impurity regions of the first conductivity-type near the amorphous regions; and forming second impurity regions of a second conductivity-type, e.g., N-type, in the substrate at both sides of the gate electrode. The method also includes forming source and drain regions of the second conductivity-type in the substrate.

The amorphous regions of the present invention are formed by ion implantation of the inactive ions while the first and second impurity regions and the source and drain regions are formed by ion implantation of active ions. Inactive ions are ions which, after implantation into the first conductivity-type substrate, assume an atomic or molecular state in which they act neither as acceptors nor donors. Conversely, active ions act as acceptors or donors after implantation.

Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring toFIGS. 2ato 2e, there is provided a manufacturing method of a semiconductor device.

Referring toFIG. 2a, field regions and active regions are defined on a semiconductor substrate21, e.g., P-type monocrystalline silicon. Then a field oxide layer22is formed on the field regions.

Subsequently, a first oxide layer, a conductive (e.g., polysilicon) layer, and an insulating layer are successively formed. The insulating layer is an oxide layer, a nitride layer, a doped oxide layer, or double layers of an oxide and a nitride. Utilizing a mask, the first oxide layer, the polysilicon layer, and the insulating layer are patterned to form a gate insulating (e.g., oxide) layer23, a gate electrode24, and a gate cap insulating layer25.

Referring toFIG. 2b, using the gate electrode24as a mask, one or more of the following inactive ions, such as germanium ions, silicon ions, nitrogen ions, fluorine ions, and argon ions are implanted at a tilt angle into the substrate21.

The ions are inactive in the sense that they assume an atomic or molecular states that do not act as either donors or as acceptors in the lattice.

In the exemplary embodiments, the ions extend a predetermined distance under the gate electrode24. Portions of the monocrystalline silicon substrate21become amorphous silicon regions26. In this exemplary embodiment, the tilt angle is 0°-60°, the ion implantation energy is 5-500 KeV and the dosage of the impurity ions is 1×1012ions/cm2-1×1016ions/cm2.

Referring toFIG. 2c, with the gate electrode24serving as a mask, P-type active ions are implanted at a tilt angle of 0°-60° into the substrate21, thus forming halo regions27. The ions are active in the sense that, after they are implanted, the act as either acceptors or donors.

The amorphous silicon regions26act as a gathering center where ions (that alter the substrate21to form the halo regions27) accumulate. Also, the amorphous silicon regions26serve to prevent ions from diffusing as rapidly during annealing as would be the case if the region26were monocrystalline silicon. The doping concentration of the halo regions27is increased, e.g., by a factor or about 1.2 or 1.3, due to the previous formation of the amorphous silicon regions26.

Referring toFIG. 2d, with the gate electrode24serving as a mask, lightly doped N-type ions are implanted into the exposed semiconductor substrate21at both sides of the gate electrode24, thus forming lightly doped drain (LDD) regions28.

Referring toFIG. 2e, an insulating layer is formed, e.g., by a chemical vapor deposition (CVD) method and then is subjected to an etch-back process, thereby forming insulating sidewalls against both sides of the gate electrode24. Next, with the gate electrode24and the insulating sidewalls29serving as masks, highly doped N-type ions are implanted into the P-type semiconductor substrate21, thus forming the source and drain regions30.

Thereafter, the implanted ions are activated by annealing, which causes the halo regions to expand. This expansion is indicated inFIG. 2eby the dashed line27being depicted outside of the amorphous region indicated by the line26. This is in contrast toFIGS. 2c-2d, where the dashed line27is depicted inside the line26.

Then, an interlayer insulating layer is formed, a contact pattern is formed, and a wiring process is performed. This completes the semiconductor device of the invention.

The exemplary embodiments of the present invention can be applied, e.g., to MOS devices and to diodes of different conductivity-types. To explain how to apply the invention to them, one or more ions such as argon ions, germanium ions, silicon ions, fluorine ions, and nitrogen ions (which will be subsequently be inactive, neither acting as acceptors nor as donors) are implanted into a P-type conductivity monocrystalline silicon substrate, thus forming amorphous silicon regions. An ion implantation energy of 5-500 KeV and a dosage of 1×1012ions/cm2-1×1018ions/cm2is used to form the amorphous regions. Then, the P-type ions are implanted at a tilt angle of 0°-60° to form the halo regions. These halo regions are formed near the amorphous regions. The amorphous regions act as ion-gathering centers where ions gather for the formation of the halo regions.

Subsequently, there are formed N-type impurity regions which have a junction with the P-type impurity regions in the halo regions of the substrate. As a result, an N+/P junction is achieved, thereby enabling the characteristics of reverse breakdown voltage, leakage current and forward current to be adjusted.

Alternatively, the substrate can be monocrystalline N-type silicon, the first ion-implantations can use inactive ions, the second ion-implantations can use N-type impurity ions to form the halo regions, the third ion-implantation can use lightly doped P-type impurity ions to form the LDD regions, and the fourth ion-implantation can use highly doped P-type impurity ions to form the source and drain regions.

The manufacturing method of a semiconductor device of the invention has the following advantages. First, amorphous silicon regions act as gathering centers of impurity ions used in the subsequent formation of halo regions. As a result, impurity ions of the halo regions cannot be diffused as rapidly as in a monocrystalline silicon substrate, thereby maintaining a high concentration of impurity ions at the halo regions. Therefore, it is possible to produce a semiconductor device exhibiting improved breakdown voltage characteristics.

Second, since the impurity ions implanted into the semiconductor substrate are diffused only slightly into the channel regions, reverse short channel effects are improved and a threshold voltage is easily adjusted.

Third, since doping concentrations can be kept low in all regions except the halo regions, current driving ability is improved.

It will be apparent to those skilled in the art that various modifications and variations can be made in the manufacturing method of a semiconductor device of the present invention without departing from the spirit or scope of the inventions. Thus, it is intended that the present invention cover the modifications and variations of this invention as would be obvious to one of ordinary skill in the art and that these modifications and variations be included within the scope of the appended claims and their equivalents.