Step voltage identification for multiple inputs

Provided herein are approaches for determining a status of a fuse. In some embodiments, a system may include a first fuse electrically connected to a first node and to a first resistor, and a second fuse electrically connected to a second node and a second resistor, wherein the first and second fuses are in parallel connection to a same port of a multiplexer. The system may further include a controller communicably connected with the multiplexer, the controller operable to read a voltage level of the first and second nodes.

FIELD OF THE DISCLOSURE

The disclosure relates generally to fuses and, more particularly, to systems, circuits, and methods for determining a status of fuses.

BACKGROUND OF THE DISCLOSURE

An increasing number of control modules are needed to monitor voltage levels in today's modern vehicles. One existing design uses one digital input port to detect the voltage of a single node. Increasing the number of ports may thus require the use of one or more multiplexers, resulting in a more difficult layout and increased cost.

SUMMARY

In view of the foregoing, described herein are systems, circuits, and methods for determining a status of fuses. In one approach, a system may include a first fuse electrically connected to a first node and to a first resistor, and a second fuse electrically connected to a second node and a second resistor, wherein the first and second fuses are in parallel connection to a same port of a multiplexer. The system may further include a controller communicably connected with the multiplexer, the controller operable to read a voltage level of the first and second nodes.

In another approach, a circuit may include a first fuse electrically connected between a first node and to a first resistor, and a second fuse electrically connected between a second node and a second resistor, wherein the first and second fuses are in parallel connection to a same port of a multiplexer, and wherein the multiplexer is communicably connected with a controller operable to read a voltage level of the first and second nodes.

In yet another approach, a method for determining a status of a fuse may include electrically connecting a first fuse between a first node and a first resistor, and electrically connecting a second fuse between a second node and a second resistor, wherein the first and second fuses are in parallel connection to a same port of a multiplexer. The method may further include electrically connecting a controller with the multiplexer, and reading, by the controller, a voltage level of the first and second nodes. The method may further include determining whether the first or second fuses are open by comparing the voltage level of the first and second nodes to a predetermined voltage level.

The drawings are not necessarily to scale. The drawings are merely representations, not intended to portray specific parameters of the disclosure. The drawings are intended to depict typical embodiments of the disclosure, and therefore should not be considered as limiting in scope. In the drawings, like numbering represents like elements.

Furthermore, certain elements in some of the figures may be omitted, or illustrated not-to-scale, for illustrative clarity. Furthermore, for clarity, some reference numbers may be omitted in certain drawings.

DETAILED DESCRIPTION

Embodiments in accordance with the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings. The system/circuit and methods may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the system and method to those skilled in the art.

As mentioned above, currently existing voltage monitoring approaches use one digital input port to detect voltage of a single node. A multiplexer may be added, which is a simple way to expand the I/O port of a control unit, but the multiplexer can't reduce the I/O quantity for a COM port to the control unit. Furthermore, one multiplexer can monitor no more than eight nodes. As a result, current art systems may require 6-8 multiplexers for a single control module. However, an excessive number of multiplexers requires too much space on a printed circuit board (PCB), which makes design difficult and expensive.

Embodiments herein advantageously provide step voltage identification using a single port to monitor multiple nodes (e.g., 3 nodes). This approach can effectively identify the status of each node, thereby reducing multiplexer costs and saving space on the PCB.

Referring now toFIG.1, a schematic of a circuit/system (hereinafter “system”)100according to embodiments of the present disclosure will be described. In exemplary embodiments, the system100may include a first fuse102connected between a first node104and a first diode106. Connected in series with the first fuse102and the first diode106is a first resistor110. In some embodiments, the first resistor110has a resistance value of 33K. The system100may further include a second fuse112connected between a second node114and a second diode116. Connected in series with the second fuse112and the second diode116is a second resistor118. In some embodiments, the second resistor118has a resistance value of 47K. The system100may further include a third fuse120connected between a third node122and a third diode124. Connected in series with the third fuse120and the third diode122is a third resistor126. In some embodiments, the third resistor126has a resistance value of 68K. As shown, the first resistor110, the second resistor118, and the third resistor126are electrically connected in parallel to a same port (AO)130of a multiplexer132. Similarly, the first diode106, the second diode116, and the third diode124are electrically connected in parallel.

The multiplexer132may receive a status signal134representing a state of each of the first fuse102, the second fuse112, and the third fuse120. As further shown, the multiplexer132may be connected to a processor or controller138, wherein a fourth resistor140is connected between the multiplexer132and the controller138. Although non-limiting, the fourth resistor140may have a resistance value of 10K.

The controller138may include processing circuitry for storing and processing information, including a microprocessor and memory. It is understood that the processing circuitry may contain additional components, including processors, memories, error and parity/CRC checkers, data encoders, anticollision algorithms, controllers, command decoders, security primitives and tamperproofing hardware, as necessary to perform the functions described herein.

During use, the controller138is operable to read voltage levels of the first node104, the second node114, and the third node122. In some embodiments, the controller138is further operable to determine the AD value, i.e., the value obtained by converting an analog value of the voltage of the nodes into a digital value. Advantageously, the controller138can utilize a single port130of the multiplexer132to monitor all three nodes at same time. Although not specifically shown, the controller138can monitor a total of twenty-four (24) nodes because eight (8) ports (e.g., A0-A7) are present on the multiplexer132.

In one example, the controller138can identify if any of the first, second, or third fuses are open. By setting the resistance values (e.g., R1/R2/R3as 33K/47K/68K), if any fuse is open, the overall resistance at the same port130will be different and the controller138will get a different voltage and/or AD value from predetermined or expected values. So the system100can find which node or nodes are open. Although non-limiting, the resistance values (e.g., 33K/47K/68K) may also be optimized values, causing the system100to have more redundancy for component tolerance and voltage fluctuation. For example, the system100can tolerate +/−3.4% for a given component (e.g., the 33K/47K/68K resistors). With +/−1% component tolerance, the system can also tolerate +/−6% voltage fluctuation. In some embodiments, when the component is a diode, the main tolerance may be the forward voltage drop (Vf) of the diode. When the component is a resistor, the main tolerance may be the resistance. When the component is a multiplexer, the main tolerance is the channel ON-resistance (Ron) when the channel is switched on. When the component is a controller, the main tolerance is the reference voltage used for AD conversion.

Referring now toFIG.2, a schematic of a circuit/system (hereinafter “system”)200according to embodiments of the present disclosure will be described. In exemplary embodiments, the system200may include a first fuse202connected between a first node204and a first resistor210. In some embodiments, the first resistor210has a resistance value of 33K. The system200may further include a second fuse212connected between a second node214and a second resistor218. In some embodiments, the second resistor218has a resistance value of 47K. The system200may further include a third fuse220connected between a third node222and a third resistor226. In some embodiments, the third resistor226has a resistance value of 68K. As shown, the first resistor210, the second resistor218, and the third resistor226are electrically connected in parallel to a same port (AO)230of a multiplexer232.

The system200may further include a first optoisolator240electrically connected to the first resistor210, a second optoisolator242electrically connected to the second resistor218, and a third optoisolator244electrically connected to the third resistor226. The system200may further include a first control and protect circuit250(e.g., a MOSFET and transient voltage suppressor) connected to the first optoisolator240, a second control and protect circuit252connected to the second optoisolator242, and a third control and protect circuit256connected to the third optoisolator244.

As further shown, a fifth resistor260may be positioned between the first fuse202and the first optoisolator240to protect the diode of the first optoisolator240, a sixth resistor262may be positioned between the second fuse212and the second optoisolator242to protect the diode of the second optoisolator242, and a seventh resistor264may be positioned between the third fuse220and the third optoisolator244to protect the diode of the third optoisolator244. A fourth resistor266may be positioned between the multiplexer232and a controller238.

During an example operation of the system200, if the first fuse202, the second fuse212, and the third fuse220are all normal/closed, the first resistor210, the second resistor218, and the third resistor226are in parallel connection with VCC, and the equivalent resistance is smallest. The equivalent resistance is in series with the fourth resistor266, and supply a partial, analog voltage to port230.

If one or more fuses are open, the associated resistor will be open from the port230, so the equivalent resistance will be bigger, and the partial voltage on the port230will be lower. When different fuses open, a different partial voltage is supplied to the port230. The controller238can then identify which fuse is open based on the partial voltage at the port230.

Turning now toFIG.3, a method300for determining a status of a fuse according to exemplary embodiments will be described in greater detail. As shown, at block301, the method300may include electrically connecting a first fuse between a first node and a first resistor. At block303, the method300may include electrically connecting a second fuse between a second node and a second resistor, wherein the first and second fuses are in parallel connection to a same port of a multiplexer. In some embodiments, the method300may include electrically connecting a third fuse between a third node and a third resistor, wherein the third fuse is in parallel connection with the first fuse and the second fuse, and wherein the third fuse is electrically connected to the same port of the multiplexer

At block305, the method300may include electrically connecting a controller with the multiplexer. At block307, the method300may include reading, by the controller, a voltage level of the first and second nodes. At block309, the method300may include determining whether the first or second fuses are open by comparing the voltage level of the first and second nodes to a predetermined voltage level. In some embodiments, the method300may include reading, by the controller, a voltage level of the third node, and determining whether the first fuse, the second fuse, or the third fuse are open by comparing the voltage level of the first, second, and third nodes to the predetermined voltage level. In some embodiments, the first resistor, the second resistor, and the third resistor each have different resistor values.

In some embodiments, the method300may include electrically connecting a first diode between the first fuse and the first resistor, electrically connecting a second diode between the second fuse and the second resistor, and electrically connecting a third diode between the third fuse and the third resistor, wherein the first diode, the second diode, and the third diode are electrically connected in parallel.

In some embodiments, the method300may further include electrically connecting a first optoisolator to the first resistor, a second optoisolator to the second resistor, and a third optoisolator to the third resistor. In some embodiments, the method300may further include electrically connecting a fifth resistor between the first optoisolator and the first fuse, a sixth resistor between the second optoisolator and the second fuse, and a seventh resistor between the third optoisolator and the third fuse.

Although the illustrative method300is described above as a series of acts or events, the present disclosure is not limited by the illustrated ordering of such acts or events unless specifically stated. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein, in accordance with the disclosure. In addition, not all illustrated acts or events may be required to implement a methodology in accordance with the present disclosure.

As used herein, an element or step recited in the singular and proceeded with the word “a” or “an” is understood as not excluding plural elements or steps, unless such exclusion is explicitly recited. Furthermore, references to “one embodiment” of the present disclosure are not intended to be interpreted as excluding the existence of additional embodiments also incorporating the recited features.

The use of “including,” “comprising,” or “having” and variations thereof herein is meant to encompass the items listed thereafter and equivalents thereof as well as additional items. Accordingly, the terms “including,” “comprising,” or “having” and variations thereof are open-ended expressions and can be used interchangeably herein.

Furthermore, identification references (e.g., primary, secondary, first, second, third, fourth, etc.) are not intended to connote importance or priority, and are used to distinguish one feature from another. The drawings are for purposes of illustration, and the dimensions, positions, order and relative sizes reflected in the drawings attached hereto may vary.

Furthermore, the terms “substantial” or “approximately,” as well as the terms “approximate” or “approximately,” can be used interchangeably in some embodiments, and can be described using any relative measures acceptable by one of ordinary skill in the art. For example, these terms can serve as a comparison to a reference parameter, to indicate a deviation capable of providing the intended function. Although non-limiting, the deviation from the reference parameter can be, for example, in an amount of less than 1%, less than 3%, less than 5%, less than 10%, less than 15%, less than 20%, and so on.