CAPACITOR FORMED IN SEMICONDUCTOR

According to an embodiment, a capacitor includes a first electrode, a second electrode and a first via. The first electrode is provided in a first interconnect layer. The second electrode is provided in the first interconnect layer and surrounds a periphery of the first electrode by a closed circuit. The first via is connected to the first electrode and provided to pass through the first interconnect layer.

FIELD

Embodiment described herein relates to a capacitor formed in semiconductor.

BACKGROUND

Various types of capacitors are used in integrated circuits. There is an interconnect capacitor in which part of a pair of interconnects are made to face each other to easily obtain capacitance. In the interconnect capacitor, when micronization advances and a high breakdown voltage process is applied, a situation may occur in which a desired capacitance is difficult to be realized while a breakdown voltage between the wirings is secured.

DETAILED DESCRIPTION

According to an embodiment, a capacitor formed in a semiconductor includes a first electrode, a second electrode and a first via. The first electrode is provided in a first interconnect layer. The second electrode is provided in the first interconnect layer and surrounds a periphery of the first electrode by a closed circuit. The first via is connected to the first electrode and provided to pass through the first interconnect layer.

First Embodiment

FIG. 1Ais a perspective view illustrating a capacitor of a first embodiment.

FIG. 1Bis a plan view illustrating the capacitor of the first embodiment.

FIG. 1Cis a sectional view taken in AA ofFIG. 1B.

As shown inFIG. 1A, a capacitor1of the embodiment includes a first electrode11, a second electrode12and a via24. The first electrode11and the second electrode12are provided on the same plane. The plane is a plane15aof an insulating film15provided on a substrate10as described later. In the following, a description is made under the assumption that the plane15ais a flat surface. The first electrode11and the second electrode12respectively have the same thickness t and are formed on the plane15a. The second electrode12surrounds the periphery of the first electrode11by a closed circuit. The first via24is vertical to the plane15aand extends in a direction opposite to the substrate10. One end of the first via24is connected to the first electrode11. The other end of the first via24is connected to a first interconnect21. In the embodiment, the sectional shape of the first via24is arbitrary. The sectional shape of the first via24on a plane parallel to the plane15amay be circular as in the example, or may be a shape similar to the shape of the first electrode11in plan view. The first electrode11, the second electrode12and the first via24are formed of metal containing high conductivity material such as copper or aluminum.

The first electrode11is connected to the first interconnect21through the first via24. The second electrode12is connected to a second interconnect22provided on the plane15a. The first interconnect21and the second interconnect22are formed of metal containing high conductivity material such as copper or aluminum. That is, the capacitor1is connected to an external circuit through the first interconnect21and the second interconnect22. Incidentally, in the capacitor1, the second interconnect22may be connected to a third interconnect23through a second via25as in the example.

As shown inFIG. 1B, the first electrode11is a rectangle including four sides11ato11din plan view. In the example, lengths “a” of the four sides11ato11dare equal to each other and the first electrode11is square in plan view.

The second electrode12is a rectangular frame body including four outer peripheral sides12ato12dand four inner peripheral sides12eto12h. In the example, lengths b1of the four outer peripheral sides12ato12dare equal to each other, and lengths b2of the four inner peripheral sides12eto12hare equal to each other. The length b1is larger than the length b2. A width d1of a frame of the second electrode12is equal to (b1−b2)/2. That is, both the outer periphery and the inner periphery of the frame body are square.

The side11aof the first electrode11faces the inner peripheral side12eof the second electrode12on the same plane. A shortest distance d2between the side11aand the side12eis equal to (b2−a)/2. Similarly, the side11bof the first electrode11faces the inner peripheral side12fof the second electrode12on the same plane. A shortest distance between the side11band side12fis d2. The side11cof the first electrode11faces the inner peripheral side12gof the second electrode12. A shortest distance between the side11cand the side12is d2. The side11dof the first electrode11faces the inner peripheral side12hof the second electrode12. A shortest distance between the side11dand the side12his d2. That is, the respective facing sides are provided to be parallel to each other, and are disposed so that the center of gravity (center) of the first electrode11in plan view coincides with the center of gravity (center) of the second electrode12in plan view.

As shown inFIG. 1C, the capacitor1of the embodiment is formed in a interconnect layer27. The interconnect layer27includes the first electrode11, the second electrode12, the first via24and an insulating layer26. The first electrode11and the second electrode12are provided on the plane15aof the insulating film15. The plane15ais a plane forming a boundary between the insulating film15and the interconnect layer27. The thicknesses of the first electrode11and the second electrode12are respectively t. That is, the first electrode11is a rectangular parallelepiped having the square section and the height t. The second electrode12is a tubular body having the square section and the height t, and the thickness of the tube is d2. Incidentally, although a layer under the interconnect layer27is the substrate10and the insulating layer15in the example, more generally, the layer may be another interconnect layer.

One end of the first via24is connected to the first electrode11, and the first via24extends vertically toward the opposite side to the substrate10with respect to the plane15a. The other end of the first via24extends until reaching another interconnect layer28. The interconnect layer28is an upper interconnect layer of the interconnect layer27. The other end of the first via24is connected to the first interconnect21in the interconnect layer28.

The insulating layer26is provided between the first electrode11and the interconnect layer28. The insulating layer26is provided between the second electrode12and the interconnect layer28. The insulating layer26is provided also between the first electrode11and the second electrode12. The insulating layer26is formed of, for example, inorganic material such as silicon oxide. The insulating layer26insulates between the first electrode11and the second electrode12, and functions also as a dielectric of the capacitor1.

The first via24and the second via25are respectively formed by filling via holes24aand25aopened in the insulating layer26.

As described above, the capacitor1of the embodiment can be easily manufactured by using an existing multilayer interconnect technique.

The operation of the capacitor1of the embodiment will be described.

In the capacitor1of the embodiment, since the first electrode11is surrounded by the second electrode12, the first electrode11and the first interconnect21are connected through the first via24passing through the insulating layer26. Accordingly, the capacitor1can be freely connected to an external circuit. Incidentally, when the second electrode12is also connected to the second interconnect22through the second via25passing through the insulating layer26, the capacitor1can be connected to an external circuit in the same interconnect layer28.

A capacitance value of the capacitor1of the embodiment is determined as described below.

The capacitance value based on the first electrode11and the second electrode12is obtained in relation to the product of the lengths of the sides11ato11dand12eto12hof the facing electrodes and the thickness t. Besides, the capacitance value based on the first electrode11and the second electrode12is obtained in relation to the distances between the sides11ato11dand the sides12eto12hof the facing electrodes.

Since the first electrode11and the second electrode12are formed simultaneously with the other interconnect formed on the plane15a, the thickness t of the electrodes and the other interconnect is the same. Accordingly, as the lengths of the sides of the facing electrodes become long, the capacitance value based on the first electrode11and the second electrode12becomes large. Besides, as the distance between the sides of the facing electrodes becomes short, the capacitance value becomes larger.

On the other hand, as the distance between the sides11ato11dand the sides12eto12hof the facing electrodes becomes short, electric field intensity becomes high. Thus, the separation distance is set with sufficient margin to prevent breakdown or deterioration in breakdown voltage from occurring according to a voltage used in a circuit.

From the above, the capacitance value based on the first electrode11and the second electrode12can be made large by increasing the length “a” of the side of the first electrode11and by increasing the length b2of the side of the inner periphery of the second electrode12. Incidentally, since the inter-electrode area relative to the first electrode11can be substantially increased also by extending the width d1of the frame part of the second electrode12, this contributes to slightly increasing the capacitance value.

An action effect of the capacitor1of the embodiment will be described.

FIG. 2is a plan view illustrating a capacitor of a comparative example.

FIG. 3Ais a plan view showing sizes of main parts of the capacitor of the first embodiment used for simulating the maximum electric field intensity.FIG. 3Bis a plan view showing sizes of main parts of the capacitor of the comparative example used for simulating the maximum electric field intensity.

As shown inFIG. 2, a technique is known in which a comb-shaped first electrode111and a comb-shaped second electrode112are provided, and a capacitance value is increased by increasing the length of the facing electrodes between the two electrodes.

On the other hand, in the case of a capacitor101using the comb-shaped electrodes111and112, since the shape of the two facing electrodes has a portion protruding as compared with the other portion, electric field concentration occurs at the portion, and breakdown voltage failure may occur. In the example, the protruding portion is tip portions111tand112tof the respective comb-shaped electrodes111and112. Although electric field is uniformly distributed in parallel-disposed portions111pand112pon the side of long sides, electric field distribution becomes irregular in the tip parts111tand112t, and the electric field concentration can occur.

With respect to the capacitor1of the embodiment and the capacitor101of the comparative example, the maximum electric field intensity obtained when the same voltage is applied between the electrodes can be obtained by simulation. InFIG. 3A, the left figure represents the capacitor1of the embodiment. The length of the side of the first electrode11is set to 0.2 μm. The frame width d1of the second electrode12is set to 0.2 μm. All of the shortest separation distances between the sides11ato11dof the first electrode11and the facing sides12eto12hare 0.2 μm.

The figure shown inFIG. 3Brepresents the capacitor101of the comparative example. The size of the capacitor101of the comparative example is set so as to have the same capacitance value as that of the capacitor1of the embodiment. The separation distance between the facing long sides of the first electrode111and the second electrode112is set to 0.2 μm. The shortest separation distance between the tip part111tof the first electrode111and the second electrode112is set to 0.3 μm. Incidentally, the reason why the shortest separation distance between the tip part111tof the first electrode111and the second electrode112is longer than the separation distance between the other portions is that electric field is expected to be concentrated in the portion, and therefore, the separation distance is set to be long in advance.

When a voltage of 40V is applied between the electrodes of the capacitor1of the embodiment and between the electrodes of the capacitor101of the comparative example, the maximum electric field intensity is 2.2 MV/cm in the capacitor1of the embodiment. On the other hand, the maximum electric field intensity is 2.37 MV/cm in the capacitor101of the comparative example. That is, when the same voltage is applied, the electric field intensity is reduced by about 7% in the capacitor1of the embodiment as compared with the capacitor101of the comparative example, and the electric field concentration is relaxed. As stated above, since the separation distance between the tip part111tand the second electrode112is long in the capacitor101of the comparative example, if the separation distance between the tip part111tof the first electrode111and the second electrode112is made short, a further difference appears to occur.

In the capacitor1of the embodiment, the square first electrode11is disposed to be surrounded by the second electrode12including the square inner periphery similar to the first electrode11, and the facing electrodes are disposed to be almost in parallel to each other. Thus, the shortest distance between the facing electrodes becomes almost the same for the respective sides11ato11dand12eto12hof the electrodes. Thus, the electric field distribution becomes almost the same for the respective sides, and the non-uniformity of the electric field intensity is relaxed. In general, an electric field concentration is liable to occur at a corner part of an electrode. However, in the capacitor1of the embodiment, since the separation distance between the corner part of the first electrode11and the corner part of the inner periphery of the second electrode12is longer than the distance between the facing electrodes disposed in parallel, the electric field intensity is reduced. Thus, in the capacitor1, the limit value of the electric field intensity is improved.

The number of the corner parts of each of the electrodes is four in the capacitor1of the embodiment, while the number of the corner parts of the electrode is two in the capacitor101of the comparative example. Thus, in the capacitor1of the embodiment, since sharing is performed by the corner parts the number of which is larger than that of the capacitor101of the comparative example, the electric field concentration can be more relaxed. Accordingly, in the capacitor1of the embodiment, the maximum electric field intensity can be relaxed.

Further, in the capacitor1of the embodiment, since the first electrode11surrounded the periphery can be connected by using the first via24, a desired capacitance value can be obtained without increasing the installation area of the capacitor1.

Second Embodiment

FIG. 4Ais a perspective view illustrating a capacitor of a second embodiment.

FIG. 4Bis a sectional view taken along a plane B ofFIG. 4A.

In the capacitor of the above embodiment, the capacitance value is set by the lengths of two facing electrodes provided on the same plane. The capacitance value can be further increased by extending the two electrodes in the thickness direction.

As shown inFIG. 4A, a capacitor30of the embodiment includes a first electrode41, a second electrode42, a first via54and a second via55. The shapes of the first electrode41and the second electrode42in plan view are similar to those of the first embodiment. That is, the first electrode41is square, and the second electrode42is a square frame body. The second electrode42surrounds the first electrode by a closed circuit. The first electrode41and the second electrode42are provided on the same plane. The same plane is a plane45aof an insulating film45formed on a substrate40and the plane45ais on the opposite side to the substrate40(FIG. 4B).

One end of the first via54is connected to the first electrode41. The other end of the first via54is connected to a first interconnect51. The sectional shape of the first via54on a plane parallel to the plane45aalmost coincides with the shape of the first electrode41in plan view. The first via54is integrated with the first electrode41and forms one electrode of the capacitor30. That is, the first via54has a rectangular column shape vertical to the plane45aand extending toward an opposite side to the substrate40.

One end of the second via55is connected to the second electrode42. The other end of the second via55is connected to a second interconnect52. The sectional shape of the second via55taken along a plane parallel to the plane45aalmost coincides with the shape of the second electrode42in plan view. The second via55is integrated with the second electrode42and forms the other electrode of the capacitor30. The second via55has a square tubular shape vertical to the plane45aand extending toward an opposite side to the substrate40.

Incidentally, the second interconnect52may be connected to a third interconnect53bthrough a third via53aas in the example.

As shown inFIG. 4B, the capacitor30of the embodiment is formed in a interconnect layer58. The interconnect layer58includes the first electrode41, the second electrode42, part of the first via54, the second via55and an insulating layer56. In the capacitor30, the first electrode41is connected to the first interconnect51in a interconnect layer59. The interconnect layer59includes the first interconnect51. In the capacitor30, the second electrode42is connected to the second interconnect52in a interconnect layer60. The interconnect layer60includes the second interconnect52and an insulating layer57. The interconnect layer60is provided between the lower interconnect layer58and the upper interconnect layer59.

The first electrode41and the second electrode42are provided on the plane45a.

The first electrode41is connected through the first via54to the first interconnect51provided in the interconnect layer59above the interconnect layer58including the first electrode41and the second electrode42. The first via54is provided to pass through the interconnect layer58and the interconnect layer60. More specifically, the via54is provided to fill a via hole passing through the insulating layer56of the interconnect layer58and the insulating layer57of the interconnect layer60.

The second electrode42is connected through the second via55to the second interconnect52in the interconnect layer60provided between the interconnect layer58and the upper interconnect layer59. The second via55is provided to pass through the interconnect layer58. The via55is provided to fill a via hole passing through the insulating layer56of the interconnect layer58.

That is, the first electrode41is connected through the first via54to the first interconnect51in the interconnect layer59above the second interconnect52connected to the second electrode42. Besides, the second electrode42is connected to the second interconnect52through the second via55.

The insulating layer56is provided between the first electrode41and the interconnect layer60. The insulating layer56is provided between the second electrode42and the interconnect layer60. The insulating layer56is provided also between the first electrode41and the second electrode42. In the interconnect layer58, the insulating layer56is provided also between the first via54and the second via55. That is, the insulating layer56ensures insulation between the first electrode41and the second electrode42and also functions as a dielectric layer between the electrodes. Simultaneously, the insulating layer56ensures insulation between the first via54and the second via55and functions as a dielectric layer between the vias.

In the interconnect layer60, the insulating layer57is provided between the interconnect layer58and the interconnect layer59and also on the upper surface and the side surface of the second interconnect52.

In the interconnect layer58, the first via54connected to the first electrode41and the second via55connected to the second electrode42are upwardly provided in parallel to each other and vertically to a plane including the plane45a. That is, facing electrodes are formed of the outer peripheral surface of the rectangular column-shaped via54and the inner wall of the tube-shaped via55containing the via54therein, and the facing electrodes constitute a part of the capacitor30.

As stated above, the capacitor30of the embodiment can be easily manufactured by using an existing multi-layer interconnect technique similarly to the other embodiment.

An operation of the capacitor30of the embodiment will be described.

In the capacitor30of the embodiment, since the first electrode41is surrounded by the second electrode42, the first electrode41and the first interconnect51are connected through the first via54passing through the insulating layers56and57. Besides, the second electrode42and the second interconnect52are connected through the second via55passing through the insulating layer56. Accordingly, the capacitor30can be freely connected to an external circuit. Incidentally, when the second electrode42is also connected to the third interconnect53bthrough the third via53apassing through the insulating layer57, the capacitor30can be connected to an external circuit in the same interconnect layer59.

A capacitance value of the capacitor30of the embodiment is determined as described below.

In the capacitor30of the embodiment, the facing electrodes are formed of the surface of the rectangular column-shaped via54and the inner wall of the tube-shaped via55containing the via54therein. When a thickness of the interconnect layer58is tox, the capacitor30of the embodiment has the capacitance value proportional to tox. In the capacitor1of the first embodiment, the area of the facing electrodes is obtained in relation to the thickness t of the first electrode and the second electrode. On the other hand, in the capacitor30of the embodiment, the area of the facing electrodes is obtained in relation to tox sufficiently larger than t. Accordingly, in the capacitor30of the embodiment, the capacitance value tox/t times larger than that of the capacitor1of the first embodiment can be obtained in the same occupied area on the plane45a.

An action effect of the capacitor30of the embodiment will be described.

The capacitor30of the embodiment includes the via54which is the columnar body having the same sectional shape as that of the first electrode41and the via55which is the tubular body having the same sectional shape as that of the second electrode42. Thus, the facing area of the electrodes increases, and the large capacitance value can be obtained.

The capacitance value of the capacitor30of the embodiment can be made a large value proportional to the thickness tox of the insulating layer56in which the surface of the first via54and the inner wall surface of the second via55face each other.

Third Embodiment

FIG. 5Ais a plan view illustrating a capacitor of a third embodiment.

FIG. 5Bis a sectional view taken in CC ofFIG. 5A.

As described above, a first electrode can be connected through a via to a interconnect layer above a interconnect layer in which the first electrode is provided. Thus, when plural first electrodes are provided, each of the electrodes is extracted to another interconnect layer and can be connected. Hereby, the first electrodes and vias can be made one electrode. Besides, also with respect to a second electrode, second electrodes are formed so as to respectively surround the plural first electrodes and the adjacent second electrodes are connected, so that the other electrode can be formed.

As shown inFIG. 5A, a capacitor70of the embodiment includes plural unit capacitors71. Each of the plural unit capacitors71includes a first electrode81and a second electrode82. The second electrode82surrounds the first electrode81by a closed circuit. The shape and the configuration of the first electrode81and the second electrode82are the same as those of the foregoing other embodiments.

In the capacitor70of the embodiment, the unit capacitors71are arranged in a lattice shape on the same plane. In the example, the second electrode82is connected to the adjacent second electrodes82and is integrated.

In the example, the center of gravity (center) of the unit capacitor71is disposed along an X-axis parallel to one side of the unit capacitor71, and the center of gravity (center) of the unit capacitor71is disposed along a Y-axis perpendicular to the X-axis. Incidentally, the disposition on the XY plane is not limited to such lattice shape, and for example, a staggered disposition may be adopted in which the gravity center positions of the unit capacitors disposed alternately in the Y-axis direction are shifted in the X-axis direction.

As shown inFIG. 5B, the capacitor70of the embodiment is formed in a interconnect layer98a. The interconnect layer98aincludes the first electrode81, the second electrode82, part of a first via94, a second via95and an insulating layer96. In the capacitor70, the first electrode81is connected to a first interconnect91in a interconnect layer99. The interconnect layer99includes the first interconnect91. In the capacitor70, the second electrode82is connected to a second interconnect92in a interconnect layer98b. The interconnect layer98bincludes the second interconnect92and the insulating layer97. The interconnect layer98bis provided between the lower interconnect layer98aand the upper interconnect layer99.

The first via94passes through the interconnect layers98aand98band reaches the interconnect layer99. One end of the first via94is connected to the first electrode81, and the other end is connected to the first interconnect91in the upper interconnect layer98. In the interconnect layer98a, the plural respective first electrodes81are connected through the first interconnect91and form one electrode. The second via95passes through the interconnect layer98aand reaches the interconnect layer98b. One end of the second via95is connected to the second electrode82, and the other end is connected to the second interconnect92in the interconnect layer98babove the interconnect layer98a. The second via95and the second interconnect92form the other electrode of the capacitor70in the interconnect layer98b.

The insulating layer96provided between the respective electrodes and between the vias insulates between the respective electrodes and between the vias, and functions also as a dielectric layer of the capacitor70.

An action effect of the capacitor70of the embodiment will be described.

The capacitor70of the embodiment includes the plural unit capacitors71, and the first electrodes81and the second electrodes82of the plural respective unit capacitors71are connected to each other. That is, the capacitor70is configured of the plural parallel-connected unit capacitors71. Accordingly, the capacitance value of the capacitor70can be increased in accordance with the number of the unit capacitors71which are arranged in a lattice shape and are parallel connected. For example, when the n unit capacitors71are arranged in the X-axis direction and the m unit capacitors71are arranged in the Y-axis direction, the capacitance value of the capacitor70is n x m times larger than the capacitance value of the unit capacitor71.

Variations of the Third Embodiment

FIG. 6is a plan view illustrating a capacitor of a variation of the third embodiment.

FIG. 7is a plan view illustrating a capacitor of another variation of the third embodiment.

As described above, in the capacitor, the capacitance value can be increased by increasing the area of the facing electrodes. The lengths of the facing sides of the first electrode and the second electrode are required to be increased in order to increase the facing area of the facing electrodes. On the other hand, when the length of the side of the electrode is increased, the outer peripheral size of the electrode is increased, and the size of the electrode in plan view is required to be increased. In general, since a region and area in which a capacitor can be disposed are often limited in a region on an integrated circuit, it is preferable that a large capacitor can be disposed in the limited region and area. That is, it is desired to decrease the occupied area of the capacitor in the integrated circuit.

Besides, as described above, since an electric field concentration is liable to occur at the corner part of an electrode, the electric field concentration can be relaxed by increasing the number of corner parts. Besides, since the angle of the corner part becomes an obtuse angle by increasing the number of corner parts of the electrode, the electric field concentration can be made hard to occur.

As shown inFIG. 6, in a capacitor70aof the variation, the shape of each of second electrodes82aof plural unit capacitors71ain plan view forms a regular hexagonal frame body. Sides of outer peripheries of the second electrodes82are connected to each other, so that the respective unit capacitors71aare closely arranged. Although the shape of a first electrode81in plan view is circular in the example, the shape may be a hexagonal shape similar to the outer peripheral or inner peripheral shape of the second electrode82.

In the capacitor70aof the variation, the outer peripheral and inner peripheral shapes of the second electrode82aare made regular hexagonal, so that the length of the inner periphery per unit area can be made longer than that of a case of a square. Accordingly, the capacitance value can be increased. The shape of the first electrode81may be circular as in the variation, or may be a regular hexagonal shape similar to the second electrode82.

In the variation ofFIG. 7, a capacitor70bincludes a plural of capacitor elements71b, a first electrode81band a second electrode82bare concentrically provided. The center of a circle of the first electrode81band the centers of an outer circumference and an inner circumference of the second electrode82bare disposed to almost coincide with each other. When the shape is set and disposed in this way, the shortest separation distance between the facing sides can be made identical at any point, and the electric field distribution at voltage application can be made circumferentially uniform. Thus, since the electric field concentration does not occur between any electrodes, the inter-electrode distance can be shortened and the occupied area can be reduced.