Manufacturing method of thin film transistor and display array substrate using same

A manufacturing method of a thin film transistor includes hard-baking and etching processes for a stop layer. Two through holes are exposed and developed in a photoresistor layer, in which a distance between the two through holes is substantially equal to the channel length of the thin film transistor. Further, the etching stop layer is dry-etched to obtain the thin film transistor having an expected channel length.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to Taiwanese Patent Application No. 102130378 filed on Aug. 23, 2013 in the Taiwan Intellectual Property Office, the contents of which are incorporated by reference herein.

FIELD

The disclosure generally relates to thin film transistor manufacture.

BACKGROUND

A channel layer of a thin film transistor can be made of metal oxide semiconductor. An etching stop layer can be arranged on the channel layer to protect the metal oxide semiconductor. A thickness of the etching stop layer is generally greater than 100 nanometers. However, in etching stop (ES) process a resolution of exposing a through hole in the etching stop layer is not high enough to achieve a shorter channel length between a source electrode and a drain electrode of the thin film transistor.

DETAILED DESCRIPTION

Referring toFIG. 1, a display array substrate10can include a plurality of gate lines11and a plurality of data lines12. The gate lines11are parallel to each other. The data lines12are parallel to each other, and each independently intersects with the gate lines11. The data lines12and the gate lines11define multiple intersections where the data lines12cross the gate lines11. A thin film transistor (TFT)100is arranged on each of the multiple intersections. The thin film transistor100can include a gate electrode110, a source electrode120, and a drain electrode130. The gate electrode110is electrically connected to one gate line11to receive a gate signal which is output by a gate driver (not shown). The source electrode120is electrically connected to one data line12to receive a data signal which is output by a data driver (not shown).

When a potential of the gate signal is greater than a threshold potential of the thin film transistor100, a channel layer103(as shown inFIG. 2) is turned on, thus the data signal is output to the drain electrode130via the source electrode120.

Referring also toFIG. 2, the thin film transistor100can further include a gate insulating layer105and an etching stop layer107. The gate electrode110is formed on a substrate101. The source electrode120and the drain electrode130are arranged on the same layer. The channel layer103is coupled between the source electrode120and the drain electrode130. The gate insulating layer105is formed on the same substrate101on which the gate electrode110is formed, and electrically insulates the gate electrode110from the channel layer103. The etching stop layer107is arranged on a surface of the channel layer103to protect the channel layer103.

FIGS. 3-8show sectional views illustrating a manufacturing method of the thin film transistor100.FIG. 9shows a flowchart of the manufacturing method of the thin film transistor100.

At block301, as shown inFIG. 3, the gate electrode110and the gate insulating layer105are formed on the substrate101. In detail, a first metal layer is deposited on the substrate101, and then the first metal layer is patterned to form the gate electrode110. The gate insulating layer105is coated on the gate electrode110. In the embodiment, the first metal layer is etched by photo lithography process. The substrate101can be a glass substrate or a quartz substrate. The first metal layer can include molybdenum (Mo), aluminum (Al), chromium (Cr), copper (Cu), or neodymium (Nd). The gate insulating layer105can include silicon nitride (SiNx) or Silicon oxide (SiOx). In the embodiment, the gate insulating layer105can formed by sputtering, vacuum evaporation, pulsed laser deposition (PLD), or Plasma Enhanced CVD (PECVD) methods.

Referring also toFIG. 3, at block303, the channel layer103is formed on the gate insulating layer105to correspond to the gate electrode110, and the etching stop layer107is coated on the channel layer103. The channel layer103can be metal oxide semiconductor, such as indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium oxide (InO), gallium oxide (GaO), or the like. In the embodiment, a metal oxide semiconductor layer is formed on the gate insulating layer105by sputtering, vacuum evaporation, pulsed laser deposition (PLD), or Plasma Enhanced CVD (PECVD) method, and then the metal semiconductor layer is patterned to form the channel layer103. A material of the etching stop layer107is organic and transparent. In the embodiment, the etching stop layer107is photo-active compound (PAC), and a photosensitivity of the etching stop layer107is not better than a photosensitivity of a photoresistor. The etching stop layer103protects the channel layer103against damage in subsequent processing, and a thickness of the etching stop layer107is generally greater than 100 nanometers up to a few micormeter.

At block305, the etching stop layer107is hard-baked to become flat and solid. The hard-baking process of the etching stop layer107enhances adhesion between the etching stop layer107and the channel layer103. In the embodiment, the etching stop layer107is hard-baked under a temperature between 100° C.-400° C. Residual organic solvents of the etching stop layer107are evaporated in the hard-baking, thus the etching stop layer107becomes solid and the adhesion between the etching stop layer and the channel layer103is enhanced.

At block307, referring toFIG. 4, a photoresistor layer109is coated on the etching stop layer107.

At block309, referring toFIG. 5, the photoresistor layer109is patterned and two through holes, H1 and H2, are defined on the patterned photoresistor layer109. In detail, the photoresistor layer109is photo-exposed and developed to define the two through holes H1 and H2, under a shield of a photomask14. A distance between the two through holes H1 and H2 is equal to a predetermined channel length. In the embodiment, the distance between the two through holes H1 and H2 is 3-5 micrometers. The photomask14can include two transmission portions140and a shading portion141. A distance between the two transmission portions140is defined to be the distance between the two through holes H1 and H2.

At block311, referring toFIG. 6, two contact holes, O1 and O2, are formed by etching the etching stop layer107to the channel layer103using the patterned photoresistor layer109as a mask. The two contact holes O1 and O2 respectively contact the two through holes H1 and H2. In the embodiment, the etching stop layer107is etched by a dry-etching method, such as a plasma etching method or a reactive ion etching (RIE) method. A distance between the two contact holes O1 and O2 is substantially equal to the channel length L1.

At block315, referring toFIG. 8, the source electrode120and the drain electrode130are formed on the etching stop layer107. The source electrode120and the drain electrode130respectively infill the two contact holes O1 and O2 to contact the channel layer103. In detail, a second metal layer is deposited on the etching stop layer107, and then the source electrode120and the drain electrode130are formed in a mask process by patterning the second metal layer. The first metal layer can include molybdenum (Mo), aluminum (Al), chromium (Cr), copper (Cu), or neodymium (Nd).

FIG. 10shows a thin film transistor (thin film transistor200) according to a second embodiment. The thin film transistor200can include a gate electrode210, a channel layer203, and a gate insulating layer210. The gate electrode210is formed on a substrate201. The channel layer203is arranged on the gate insulating layer210to correspond to the gate electrode210. The thin film transistor200can further include an etching stop layer207protectively covering the channel layer203. In one embodiment, the etching stop layer207can include an organic stop layer207aand a hard mask layer207b. The hard mask layer207bis stacked up on the organic stop layer207a. The organic stop layer207acan be a transparent organic material layer after a curing process. The hard mask layer207is arranged on a surface of the organic stop layer207aopposite to the substrate201to enhance a hardness of the organic stop layer207a. In the embodiment, a thickness of the hard mask layer207bis less than a thickness of the organic stop layer207a. Two contact holes O21 and O22 penetrate the etching stop layer207to expose the channel layer207. A distance between the two contact holes O21 and O22 defines a channel length L2. In the embodiment, the distance between the two contact holes O21 and O22 is less than ten micrometers. The preferred distance between the two contact holes O21 and O22 is 3-5 micrometers.

The thin film transistor200can further include a source electrode220and a drain electrode230. The channel layer203is coupled between the source electrode220and the drain electrode230. The source electrode220and the drain electrode230make contact with the channel layer203via the two contact holes O21 and O22.

FIGS. 11-17show sectional views illustrating a manufacturing method of the thin film transistor200.FIG. 18shows a flowchart of the manufacturing method of the thin film transistor200.

At block401, referring toFIG. 11, the gate electrode210and the gate insulating layer205are formed on the substrate201. In detail, a first metal layer is deposited on the substrate201, and then the first metal layer is patterned to form the gate electrode210. The gate insulating layer205is coated on the gate electrode210. In the embodiment, the first metal layer is etched by photo lithography process. The substrate201can be a glass substrate or a quartz substrate. The first metal layer can include molybdenum (Mo), aluminum (Al), chromium (Cr), copper (Cu), or neodymium (Nd). The gate insulating layer205can include silicon nitride (SiNx) or Silicon oxide (SiOx). In the embodiment, the gate insulating layer205can formed by sputtering, vacuum evaporation, pulsed laser deposition (PLD), or Plasma Enhanced CVD (PECVD) process.

At block403, referring also toFIG. 11, the channel layer203is formed on the gate insulating layer205to correspond to the gate electrode210, and the organic stop layer207ais coated on the channel layer203. The channel layer103can be metal oxide semiconductor, such as indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium oxide (InO), gallium oxide (GaO), or the like. In the embodiment, a metal oxide semiconductor layer is formed on the gate insulating layer205by sputtering, vacuum evaporation, pulsed laser deposition (PLD), or Plasma Enhanced CVD (PECVD) process, and then the metal semiconductor layer is patterned to form the channel layer203. A material of the organic stop layer207ais organic and transparent. In the embodiment, a photosensitivity of the organic stop layer207ais not better than a photosensitivity of a photoresistor. The organic stop layer207aprotects the channel layer203against damage of subsequent processes, and a thickness of the organic stop layer207ais one micrometer.

At block405, the organic stop layer207ais hard-baked to be flat and solid. Hard-baking the organic stop layer207aenhances adhesion between the organic stop layer207aand the channel layer203. In the embodiment, the organic stop layer207ais hard-baked between 100° C.-400° C. Residual organic solvents of the organic stop layer207ais evaporated in the hard-baking, thus the organic stop layer207ais solid and the adhesion between the etching stop layer and the channel layer203is enhanced.

At block407, referring toFIG. 12, the hard mask layer207bis formed on the organic stop layer207a. The hard mask layer207bis stacked up with the organic stop layer207ato form the etching stop layer207. In the embodiment, a thickness of the hard mask layer207bis less than a thickness of the organic stop layer207a. The hard mask layer207bcan include silicon nitride (SiNx), Silicon oxide (SiOx), silicon fluorion (SiFx), or silicon nitride oxide (SiNxOy). In one embodiment, the hard mask layer207bis formed by chemical vapor deposition (CVD) or sputtering process.

At block409, referring toFIG. 13, a photoresistor layer209is coated on the etching stop layer207.

At block411, referring toFIG. 14, the photoresistor layer209is patterned and two through holes H21 and H22 are defined on the patterned photoresistor layer209. In detail, the photoresistor layer209is photo-exposed and developed to define the two through holes H21 and H22, under a shield of a photomask24. A distance between the two through holes H21 and H22 is equal to a predetermined channel length. In the embodiment, the distance between the two through holes H21 and H22 is 3-5 micrometers. The photomask24can include two transmission portions240and a shading portion241. A distance between the two transmission portions240defines the distance between the two through holes H21 and H22.

At block413, referring toFIG. 15, two contact holes O21 and O22 are formed by etching the organic stop layer207aand the hard mask layer207bto the channel layer207, with the patterned photoresistor layer209as a mask. The two contact holes O21 and O22 make respective contact with the two through holes H21 and H22. In the embodiment, the organic stop layer207aand the hard mask layer207bare etched by dry-etching method, such as plasma etching or reactive ion etching (RIE). A distance between the two contact holes O21 and O22 is substantially equal to the channel length L2.

At block417, referring toFIG. 17, the source electrode220and the drain electrode230are formed on the hard mask layer207b. The source electrode220and the drain electrode230infill the two contact holes O21 and O22 to make contact with the channel layer203. In detail, a second metal layer is deposited on the hard mask layer207b, and then the source electrode220and the drain electrode230are formed in a mask process by patterning the second metal layer. The first metal layer can include molybdenum (Mo), aluminum (Al), chromium (Cr), copper (Cu), or neodymium (Nd).

When the thin film transistors100and200are applied to a liquid crystal display panel by a subsequent process, a planar layer and pixel structure will be formed.

In summary, a manufacturing method of the thin film transistor includes hard-baking and etching a stop layer, and two through holes are exposed and developed in a photoresistor layer, the distance between the two through holes being substantially equal to the channel length of the thin film transistor. The etching stop layer is dry-etched to obtain the thin film transistor with an expected channel length.