Bipolar transistor structure with emitter/collector contact to doped semiconductor well and related methods

Embodiments of the disclosure provide a lateral bipolar transistor structure with an emitter/collector (E/C) contact to a doped semiconductor well and related methods. A bipolar transistor structure according to the disclosure may include a doped semiconductor well over a semiconductor substrate. An insulative region is on the doped semiconductor well. A base layer is on the insulative region, and an emitter/collector (E/C) layer on the insulative region and adjacent a first sidewall of the base layer. An E/C contact to the doped semiconductor well includes a lower portion adjacent the insulative region and an upper portion adjacent and electrically coupled to the E/C layer.

BACKGROUND

The present disclosure relates to bipolar transistors. Present technology is at atomic level scaling of certain micro-devices such as logic gates, bipolar transistors, field effect transistors (FETs), and capacitors. Circuit chips with millions of such devices are common. The structure of a bipolar transistor defines several of its properties during operation. Conventional integrated circuits may employ vertical bipolar transistors or other types of bipolar transistors, but these types of devices may have higher costs, and/or operational parameters that do not meet certain requirements. Various alternative configurations for bipolar transistors, particularly lateral bipolar transistors, may provide sufficient electrical performance for various operations but at the expense of other physical properties. In some devices or operational settings, certain bipolar transistor structures may impose a risk of exhibiting elevated operating temperatures.

SUMMARY

Embodiments of the disclosure provide a bipolar transistor structure including: a doped semiconductor well over a semiconductor substrate; an insulative region on the doped semiconductor well; a base layer on the insulative region; an emitter/collector (E/C) layer on the insulative region and adjacent a first sidewall of the base layer; and an E/C contact to the doped semiconductor well, the E/C contact including a lower portion adjacent the insulative region and an upper portion adjacent and electrically coupled to the E/C layer.

Other embodiments of the disclosure provide a bipolar transistor structure including: a doped semiconductor well over a semiconductor substrate; a insulative region on the doped semiconductor well; a base layer on the insulative region; a first emitter/collector (E/C) layer on the insulative region and adjacent a first sidewall of the base layer; a first E/C contact to the doped semiconductor well, the first E/C contact including a lower portion adjacent the insulative region and an upper portion adjacent and electrically coupled to the first E/C layer; a second E/C layer on the insulative region and adjacent a second sidewall of the base layer opposite the first sidewall; and a second E/C contact to the second E/C layer, wherein a lower surface of the second E/C contact is on an upper surface of the second E/C layer, and above the insulative region.

Additional embodiments of the disclosure provide a method of forming a bipolar transistor structure, the method including: forming a doped semiconductor well over a semiconductor substrate; forming a base layer on an insulative layer over the doped semiconductor well; forming an emitter/collector (E/C) layer on a insulative region and adjacent a first sidewall of the base layer; and forming an E/C contact to the doped semiconductor well, the E/C contact including a lower portion adjacent the insulative region and an upper portion adjacent and electrically coupled to the E/C layer.

DETAILED DESCRIPTION

Reference in the specification to “one embodiment” or “an embodiment” of the present disclosure, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the phrases “in one embodiment” or “in an embodiment,” as well as any other variations appearing in various places throughout the specification are not necessarily all referring to the same embodiment. It is to be appreciated that the use of any of the following “/,” “and/or,” and “at least one of,” for example, in the cases of “A/B,” “A and/or B” and “at least one of A and B,” is intended to encompass the selection of the first listed option (a) only, or the selection of the second listed option (B) only, or the selection of both options (A and B). As a further example, in the cases of “A, B, and/or C” and “at least one of A, B, and C,” such phrasing is intended to encompass the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B), or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C). This may be extended, as readily apparent by one of ordinary skill in the art, for as many items listed.

Embodiments of the disclosure provide a bipolar transistor structure in which an emitter/collector contact to the emitter or collector terminal of the transistor extends (e.g., through a buried insulator layer) to a doped semiconductor well that is located below the bipolar transistor structure. The doped semiconductor well may be over a semiconductor substrate and may have an insulative region thereover. A base layer may be on the insulative region, e.g., such that the insulative region vertically separates the doped semiconductor well from the base layer. An E/C layer formed of doped semiconductor material also may be on the insulative region, and adjacent a sidewall of the base layer. The bipolar transistor structure includes an E/C contact to the doped semiconductor well, i.e., it may have a lower surface or sidewall that is in thermal communication with the doped semiconductor well. A lower portion of the E/C contact is adjacent the insulative region, and an upper portion of the E/C contact is adjacent and electrically coupled to the E/C layer.

Bipolar junction transistor (BJT) structures, such as those in embodiments of the disclosure, operate using multiple “P-N junctions.” The term “P-N” refers to two adjacent materials having different types of conductivity (i.e., P-type and N-type), which may be induced through dopants within the adjacent material(s). A P-N junction, when formed in a device, may operate as a diode. A diode is a two-terminal element, which behaves differently from conductive or insulative materials between two points of electrical contact. Specifically, a diode provides high conductivity from one contact to the other in one voltage bias direction (i.e., the “forward” direction), but provides little to no conductivity in the opposite direction (i.e., the “reverse” direction). In the case of the P-N junction, the orientation of a diode's forward and reverse directions may be contingent on the type and magnitude of bias applied to the material composition of one or both terminals, which affect the size of the potential barrier. In the case of a junction between two semiconductor materials, the potential barrier will be formed along the interface between the two semiconductor materials.

Referring toFIG.1, a preliminary structure100(simply “structure” hereafter) suitable to form a lateral bipolar transistor structure according to embodiments of the disclosure, is shown. Preliminary structure100may be processed as described herein to yield one or more lateral bipolar transistor structures. However, it is understood that other techniques, ordering of processes, etc., may be implemented to yield the same bipolar transistor structure(s) or similar bipolar transistor structures in further embodiments.FIG.1shows a cross-sectional view of structure100with a substrate102including, e.g., one or more semiconductor materials. Substrate102may include but is not limited to silicon, germanium, silicon germanium (SiGe), silicon carbide, or any other common IC semiconductor substrates. In the case of SiGe, the germanium concentration in substrate102may differ from other SiGe-based structures described herein. A portion or entirety of substrate102may be strained. A doped semiconductor well104may be included on or within substrate102, e.g., to enable electrical biasing of structures or components formed above substrate102. Doped semiconductor well104may have the same dopant type as substrate102(e.g., P type doping), but may have a higher dopant concentration therein.

Preliminary structure100includes embedded elements for electrically separating active materials formed thereon from other regions and/or materials on substrate102. An insulative region106may be formed over substrate102, e.g., by forming one or more insulative materials on doped semiconductor well by deposition and/or by otherwise converting pre-existing semiconductor material into an insulative substance. Insulative region106may extend horizontally over substrate102and doped semiconductor well104, and/or may be located under locations where active materials are formed, examples of which are discussed elsewhere herein. Insulative region106may include oxygen doping to form a dielectric insulator or a buried oxide (“BOX”) layer above substrate102and electrically isolate overlying active semiconductor materials. Insulative region106may include other elements or molecules such as Ge, N, or Si.

Insulative region106may include, e.g., a trench isolation region106aand a buried insulator layer106bthat is adjacent trench isolation region106a. Trench isolation region106amay be included within an intermediate region that is horizontally between distinct electrically active components and may have a relatively larger vertical thickness (e.g., at least approximately six-hundred nanometers (nm)) as compared to other parts of insulative region106. Trench isolation region106amay be embodied as, or may include portions of, a trench isolation (TI) region for horizontally separating distinct regions of active material. Buried insulator layer106bof insulative region106may be sized as narrow as possible to provide better interaction with overlying semiconductor materials, and in various embodiments may have a thickness that is at most approximately five nm to approximately five-hundred nm. In some cases, multiple insulative regions106may be formed over substrate102and/or regions of different vertical thickness may be formed. Each portion106a,106bof insulative region106may be formed of any currently-known or later developed substance for providing electrical insulation, and as examples may include: silicon nitride (Si3N4), silicon oxide (SiO2), fluorinated SiO2(FSG), hydrogenated silicon oxycarbide (SiCOH), porous SiCOH, boro-phospho-silicate glass (BPSG), silsesquioxanes, carbon (C) doped oxides (i.e., organosilicates) that include atoms of silicon (Si), carbon (C), oxygen (O), and/or hydrogen (H), thermosetting polyarylene ethers, a spin-on silicon-carbon containing polymer material, near frictionless carbon (NFC), or layers thereof.

Preliminary structure100may include a base layer110on buried insulator layer106bof insulative region106. Base layer110may include, e.g., SiGe or any other semiconductor material that is doped to have a predetermined polarity. In the case where doped semiconductor well104is doped n-type, base layer110may be doped p-type to form a P-N junction adjacent emitter/collector materials discussed herein. In further examples, base layer110may be a stack of layers of alternating composition (e.g., alternating Si and SiGe layers), in which case the uppermost layer of the stack is highly doped to form an extrinsic base region. It is also understood that base layer110may be doped n-type in alternative embodiments. However embodied, base layer110may extend to a predetermined height over insulative region106, and as discussed herein base layer110may be significantly taller than adjacent emitter or collector materials to be used within a bipolar structure. One or more spacers112may be adjacent base layer110to structurally and electrically separate base layer from adjacent electrically active materials (e.g., emitter and collector layers and/or contacts formed thereto. Spacer(s)112may include a nitride insulative material and/or any other insulative material discussed herein, e.g., regarding buried insulative layer106or other insulating structures. Spacer(s)112be formed, e.g., by depositing a corresponding spacer material such that it covers any exposed surfaces and sidewalls S1, S2of base layer110before other materials are formed over substrate102and adjacent base layer110. In some implementations, spacer(s)112may include a single layer or more than two layers.

Preliminary structure100also may include a set of emitter/collector (E/C) layers120on buried insulator layer106b. One E/C layer120may be adjacent a first sidewall S1of base layer110, while another E/C layer120may be adjacent a second sidewall S2of base layer110. E/C layer(s)120may define all or part of the active bipolar transistor materials for emitter and collector terminals of a bipolar transistor structure. E/C layers120may be formed on respective portions of insulative region106, e.g., by deposition and doping doped semiconductor material. E/C layers120may include the same material composition as base layer110(e.g., doped SiGe), but with an opposite doping type (e.g., they may be doped n-type when first base layer110is doped p-type or vice versa). E/C layers120additionally or alternatively may include other electrically active semiconductor materials. E/C layers120may be formed to a desired thickness above buried insulator layer106b. E/C layers120, however, may have a height above buried insulator layer106bthat is less than the height of base layer110over buried insulator layer106b.

Preliminary structure100may include a set of raised emitter/collector (E/C) layers122on E/C layers120. Raised E/C layers122may be formed by deposition and/or epitaxial growth of silicon and/or other semiconductor materials on E/C layers120and may be of the same doping type as E/C layers120. Raised E/C layers122can be formed for example by selectively growing silicon material on upper surfaces of E/C layers120. Raised E/C layers122, however, may have a higher concentration of dopants than E/C layers120thereunder. The higher doping concentration in raised E/C layers122may increase electrical conductivity between raised E/C layers122and any overlying contacts for transmitting current to the lateral bipolar transistor structure, and/or may facilitate silicide formation in subsequent processing. Due to being formed on E/C layers120, raised E/C layers122may be horizontally adjacent spacer(s)112to physically and electrically isolate raised E/C layers122from base layer110.

Preliminary structure100also may include, e.g., a gate structure130on trench isolation region106aof insulative region106. In this configuration, gate structure130may be horizontally distal to any materials over buried insulator layer106bof insulative region106. That is, gate structure130may be spaced horizontally away from base layer110, E/C layer(s)120, raised E/C layer(s)122, etc., by a predetermined horizontal separation distance. Gate structure130may include any type of semiconductor material (e.g., such as those suitable for substrate102) and/or other types of materials capable of being deposited on insulative region106at selected locations. However, gate structure130may be electrically inactive and thus may be free of p-type or n-type dopants. Gate structure130may be formed through an independent process to form various gate structures for field effect transistors and/or other electrically active components but may not be converted into an electrically active component in subsequent processing. For instance, gate structure130may remain electrically inactive by not being targeted for metal gate replacement. However, as discussed elsewhere herein, conductive contacts to E/C layer(s)120may be formed partially on gate structure130in subsequent processing, and gate structure130may act as a marking structure to help form conductive materials, where desired.

An insulative film140of preliminary structure100may be formed on exposed upper surfaces of insulative region106, base layer110, raised E/C layer(s)122, and gate structure130. Insulative film140can be provided as one or more bodies of insulating material formed on sidewalls of exposed material(s), e.g., by deposition, thermal growth, etc., to electrically and physically insulate materials subsequently formed on the coated material(s) from other components. Portions of insulative film140in some cases may form or define spacers112, but insulative film140may cover spacers112in other implementations. Insulative film140may be formed, e.g., by depositing the corresponding spacer material such that it covers any exposed surfaces and sidewalls of underlying materials in preliminary structure100. In some implementations, insulative film(s)140may include a single layer or more than two layers.

An inter-level dielectric (ILD) layer142may be above insulative film140, and may be formed by deposition or other techniques of forming an insulative material on a structure. ILD layer142may include the same insulating material as insulative region106or may include a different electrically insulative material. After depositing ILD layer142, ILD layer142can be planarized (e.g., using CMP) such that its upper surface is substantially coplanar and above all underlying components of preliminary structure100. Preliminary structure100may include an insulative film144on ILD layer142, e.g., an additional layer of nitride and/or other insulative materials distinct from ILD layer142. Insulative film144may structurally and electrically separate preliminary structure into distinct levels, e.g., to allow overlying metal wires and vias to be formed over insulative film144and ILD layer142in subsequent processing. Where insulative film144is included, an additional ILD layer146(including, e.g., the same material(s) as ILD layer142) may be formed over insulative film144.

Turning toFIG.2, methods according to the disclosure may include forming a first opening150through ILD layers142,146, insulative film144, insulative film140, and further through insulative region106to expose doped semiconductor well104. First opening150may be formed using a mask152at a targeted position to expose additional ILD layer146and any material(s) thereunder. Mask152may include any now known or later developed appropriate masking material, e.g., a nitride hard mask. As shown inFIG.2, any appropriate etching process, e.g., reactive ion etching (RIE), removes layers106,140,142,144,146to expose doped semiconductor well104. The structure of mask152may cause an upper surface and/or sidewall(s) of doped semiconductor layer104to be exposed within first opening150. First opening150also exposes adjacent portions of E/C layer120and raised E/C layer122thereover. First opening150additionally may expose an upper portion and sidewalls of gate structure130therein. In some cases, gate structure130may be formed of detectable materials relative to ILD layer142, e.g., for alignment and positioning of mask152. The forming of first opening150thus can be carried out at any location where conductive material can be formed for coupling to layer(s)120,122.

FIG.2also depicts forming a first silicide layer154on E/C layer(s)120and raised E/C layer(s)122within first opening150. First silicide layer154may be formed to enhance the electrical conductivity between raised E/C layer122and conductors formed thereon. First silicide layer154may be formed by forming a conductive metal (e.g., cobalt, titanium, nickel, platinum, or other materials) on raised E/C layer122, annealing the metal to yield conductive silicide material(s) (e.g., cobalt silicide, titanium silicide, etc.) on exposed surfaces of raised E/C layer122, and removing excess conductive metal. The initially formed metal may be selectively coated on raised E/C layer122, e.g., to prevent first silicide layer154from forming on doped semiconductor well104or on E/C layer120within opening150. First E/C layer122may be formed to allow for stronger electrical coupling to overlying contacts. It is understood that silicide layer154alternatively may be formed in an earlier processing phase. For instance, first silicide layer154may be formed within preliminary structure100(FIG.1) before first opening150is created., e.g., during the forming of preliminary structure100.

FIG.3depicts continued processing, in which mask152(FIG.2) is removed (e.g., by stripping or other mask removal techniques) and replaced with another mask156to cover first opening150while exposing another portion of additional ILD layer146. Mask156may be layer(s) of material that traverses and covers first opening150(e.g., by being supported by additional ILD layer146), but mask156may fill first opening150in other implementations. Using mask156, a second opening158may be formed through layers140,142,144,146to expose raised E/C layer122thereunder. Second opening158may not extend through layers120,122and thus may not expose doped semiconductor well104in the case where thermal coupling thereto is not needed. Second opening158thus may not be as deep as first opening150. In alternative implementations, the depth and shape of second opening158may be similar to first opening150, and thus second opening158optionally may be formed at the same time as first opening150using a single mask. After second opening158, a second silicide layer160may be formed on raised E/C layer122, e.g., by the same processes discussed herein to form first silicide layer154in first opening150. In further embodiments, second silicide layer160may be formed within preliminary structure100(FIG.1) before second opening158is created.

FIG.4depicts the filling of openings150(FIGS.2,3),158(FIG.3) with conductive material. Mask156(FIG.3) may be removed by stripping and/or other mask removal techniques, thereby allowing conductive material to be deposited within each opening150,158. A first E/C contact162may be formed within first opening150, e.g., by conformally depositing a layer of refractory metal lining material on exposed surfaces of first opening150and filling the remaining portions of first opening150with a conductor such as tungsten (W), copper (Cu), cobalt (Co), aluminum (Al), etc., as well as non-metallic conductive materials (e.g., polycrystalline Si). The refractory metal liner materials of first E/C contact162may prevent electromigration degradation, shorting to other components, etc. Due to the shape of first opening150, first E/C contact162may include a lower portion162athat connects to doped semiconductor well104(e.g., by being on an upper surface or adjacent a sidewall thereof) and is adjacent insulative region106. An upper portion162bof first E/C contact162may be on lower portion162aand coupled to raised E/C layer122, e.g., through first silicide layer154. Additionally, upper portion162bof first E/C contact162may be on and adjacent portions of gate structure130in the case where gate structure130is electrically inactive. The coupling of first E/C contact162to gate structure130also may provide additional heat dissipation from electrically active components to gate structure130. As part of the same deposition or in a subsequent operation, a second (alternatively, “additional”) E/C contact164may be formed within second opening158for electrical coupling to second silicide layer160. Due to the differences in size of openings150,158, first E/C contact162may have a largest width W1that is larger than a largest width W2of second E/C contact164. The larger width W1of first E/C contact162may result in, e.g., the larger size of opening150(FIGS.2,3) as compared to second opening152(FIG.3) for placement on doped semiconductor well104.

FIG.5depicts further processes to form a base contact166and third silicide layer168as remaining components of a bipolar transistor structure170according to embodiments of the disclosure. Base contact166may be formed in substantially the same manner as E/C contacts162,164, e.g., by forming a mask over additional ILD layer146and contacts162,164, and removing portions of layers140,142,144,146over base layer110. Third silicide layer168can then be formed on base layer in substantially the same manner as silicide layers154,160or any other currently known or later developed technique to form silicide on a semiconductor material. Conductive material(s) and refractory metal liners then can be formed over third silicide layer168to create base contact166. Thus, contacts162,164,166define conductive pathways to layers110,120,122. First E/C contact162, in addition, may include lower portion162athat is in thermal communication with (e.g., by being on or adjacent) doped semiconductor well104. Although doped semiconductor well104may not include electrically active elements and/or couplings thereto, the coupling from first E/C contact162to doped semiconductor well104may transfer heat from bipolar transistor structure170to doped semiconductor well104and substrate102. First E/C contact162of bipolar transistor structure170thus may dissipate heat to substrate102during operation of bipolar transistor structure170.

FIG.6depicts an alternative implementation of bipolar transistor structure170, e.g., in which first E/C contact162is not formed on any portion of gate structure130. Here, gate structure130may be located at a greater horizontal distance away from E/C layer(s)120than in other implementations, and thus gate structure130may not be practical to use as a marking structure. In this case, first E/C contact162may nevertheless be formed using a differently shaped mask and/or other techniques to locate a suitable coupling to doped semiconductor well104. In other respects, however, bipolar transistor structure170may be substantially identical to other implementations despite the lack of coupling to gate structure130. In addition, first E/C contact162may have largest width W1that is larger than largest width W2of second E/C contact162, e.g., due to the coupling of first E/C contact162to doped semiconductor well104.

Turning toFIGS.5and7, in whichFIG.5depicts a cross-section along line5-5of the plan view inFIG.7, further illustrative structural details of bipolar transistor structure170are discussed. As shown inFIG.7, base layer110may be subdivided into an extrinsic base region110aand an intrinsic base region110bthat is adjacent extrinsic base region110a. Intrinsic base region110bmay be less highly doped than extrinsic base region110a, e.g., to allow a stronger P-N junction to form between base layer110and E/C layer(s)120, while allowing stronger electrical coupling to base layer110through extrinsic base region110b. In addition, intrinsic base region110bmay be horizontally between two E/C layers120, each of which may be adjacent a respective sidewall S1, S2of base layer110. In this configuration, base contacts166may be on extrinsic base region110a, and additionally or alternatively may be on portions of intrinsic base region110b. As discussed elsewhere herein, portions of first E/C contact162may be on E/C layer(s)120,122and gate structure130, while second E/C contact164may overlie only E/C layer(s)120,122.

Embodiments of the disclosure provide various technical and commercial advantages, some of which are discussed herein as examples. Bipolar transistor structures170according to embodiments of the disclosure may provide stronger heat dissipation, and thus lower operating temperatures, than bipolar transistor structures which lack heat dissipation to doped semiconductor well104and/or substrate102through first E/C contact162. Lower operating temperatures, in turn may provide a more robust range of operating frequencies (including maximum and threshold current frequencies) as compared to conventional bipolar transistors. The reduction in operating temperature via bipolar transistor structure170with first E/C contact162to doped semiconductor well104also produces reduced current leakage as compared to conventional bipolar transistors.