Semiconductor device and layout method for the semiconductor device

Provided is a semiconductor device comprising: a plurality of bit line patterns; a plurality of pad patterns that are respectively connected to the plurality of bit line patterns; and at least one contact that is formed on each of the plurality of pad patterns, wherein the pitch of the plurality of pad patterns is greater than the pitch of the plurality of bit line patterns. The bit line patterns may be formed using a double patterning technology (DPT).

REFERENCE TO PRIORITY APPLICATION

This application claims the benefit of Korean Patent Application No. 10-2008-0114030, filed Nov. 17, 2008, the disclosure of which is hereby incorporated herein in its entirety.

BACKGROUND

The inventive concept relates to a semiconductor device and a layout method for the semiconductor device, and more particularly, to a semiconductor device in which bit line patterns and page buffer patterns having a pitch different from that of the bit line patterns can be connected to each other and a layout method for the semiconductor device.

NAND flash memory devices include memory cell array regions and page buffer regions. In this regard, it is important to connect bit line patterns, which belong to the memory cell array region, and page buffer patterns, which belong to the page buffer region.

SUMMARY

The inventive concept provides a semiconductor device in which bit line patterns and page buffer patterns having a pitch different from that of the bit line patterns can be connected to each other and a layout method for the semiconductor device.

According to an aspect of the inventive concept, there is provided a semiconductor device comprising: a plurality of bit line patterns; a plurality of pad patterns that are respectively connected to the plurality of bit line patterns; and at least one contact that is formed on each of the plurality of pad patterns, wherein the pitch of the plurality of pad patterns is greater than the pitch of the plurality of bit line patterns. The bit line patterns may be formed using a double patterning technology (DPT).

The plurality of bit line patterns and the plurality of pad patterns may be formed in a memory cell array region of the semiconductor device. The lengths of the plurality of bit line patterns may be different from each other. Some of the plurality of pad patterns may be respectively connected to ends of some of the plurality of bit line patterns having lengths different from one another, and the remaining pad patterns may be respectively connected to the other ends of the remaining bit line patterns having lengths different from one another.

The semiconductor device may further comprise a plurality of page buffer patterns that are respectively connected to the plurality of bit line patterns or the plurality of pad patterns via the contact, wherein the pitch of the plurality of page buffer patterns are greater than the pitch of the plurality of bit line patterns. The page buffer patterns may be formed on a layer that is different from the layer on which the bit line patterns are formed.

According to another aspect of the inventive concept, there is provided a semiconductor device comprising: a plurality of bit line patterns; and a plurality of page buffer patterns that are respectively connected to the plurality of bit line patterns, wherein the plurality of bit line patterns are connected to the plurality of page buffer patterns in a page buffer region, and the pitch of the plurality of page buffer patterns is greater than the pitch of the plurality of bit line patterns.

The plurality of page buffer patterns may be formed on a layer that is the same as a layer on which the plurality of bit line patterns are formed.

According to another aspect of the inventive concept, there is provided a layout method for a semiconductor device, the method comprising: forming a plurality of bit line patterns on a first layer; forming a plurality of pad patterns on the first layer, wherein the plurality of pad patterns are respectively connected to ends of the plurality of bit line patterns; forming a plurality of page buffer patterns on a second layer that is formed upper than the first layer; forming a plurality of connect patterns on the second layer, wherein the plurality of connect patterns are respectively connected to the plurality of pad patterns; and forming at least one contact that vertically connect the plurality of pad patterns on the first layer and the plurality of connect patterns on the second layer, wherein the pitch of the plurality of pad patterns is greater than the pitch of the plurality of bit line patterns.

According to another aspect of the inventive concept, there is provided a layout method for a semiconductor device, the method comprising: forming a plurality of bit line patterns on a first layer; and forming a plurality of page buffer patterns on the first layer, wherein the plurality of page buffer patterns are respectively connected to the plurality of bit line patterns in a page buffer region, wherein some of the plurality of page buffer patterns are respectively connected to ends of some of the plurality of bit line patterns, and the remaining page buffer patterns are respectively connected to the other ends of the remaining bit line patterns, and the pitch of the plurality of page buffer patterns is greater than the pitch of the plurality of bit line patterns.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The attached drawings for illustrating exemplary embodiments of the inventive concept are referred in order to gain a sufficient understanding of the inventive concept, the merits thereof, and the objectives accomplished by the implementation of the inventive concept.

Hereinafter, the inventive concept will be described in detail by explaining exemplary embodiments of the invention with reference to the attached drawings. Like reference numerals in the drawings denote like elements.

FIG. 1is a schematic diagram of a semiconductor device according to an embodiment of the inventive concept.

Referring toFIG. 1, a main array110is disposed between page buffer regions PBHV1through PBLV8and page buffer regions PBHV9through PBLV16. The page buffer regions PBHV1through PBLV8are sequentially disposed on a side of the main array110, and the page buffer regions PBHV9through PBLV16are sequentially disposed on the other side of the main array110. Page buffer regions PBHV1through PBHV16correspond to a high voltage, and page buffer regions PBLV1through PBLV16correspond to a low voltage. A plurality of bit line patterns are formed on the main array110.

FIG. 2is a schematic diagram of a semiconductor device according to another embodiment of the inventive concept.

Referring toFIG. 2, page buffer regions PBHV1through PBHV16and PBLV1through PBLV16are disposed on both sides of a main array210. The disposition of the page buffer regions PBHV1through PBHV16and PBLV1through PBLV16illustrated inFIG. 2is different from the disposition thereof illustrated inFIG. 1.

InFIG. 2, odd-numbered page buffer regions PBHV1through PBHV15and PBLV1through PBLV15are sequentially disposed on a side of the main array210, and even-numbered page buffer regions PBHV2through PBHV16and PBLV2through PBLV16are sequentially disposed on the other side of the main array210.

FIG. 3is a diagram illustrating a layout of a semiconductor device according to an embodiment of the inventive concept.

Referring toFIG. 3, the semiconductor device according to the present embodiment includes a main array310, a first page buffer330, and a second page buffer340. The main array310may belong to a memory cell array region, and the first and second page buffers330and340may belong to a page buffer region.

A plurality of bit line patterns BLP1and BLP2and a plurality of pad patterns PADP1and PADP2are formed on the memory cell array region to which the main array310belong. The plurality of pad patterns PADP1and PADP2are respectively connected to the plurality of bit line patterns BLP1and BLP2.

In semiconductor manufacturing, the bit line patterns BLP1and BLP2may be formed using a double patterning technology (DPT). In this case, the pitch of the bit line patterns BLP1and BLP2may be decreased. Referring toFIG. 3, the pitch of the bit line patterns BLP1and BLP2is 2 F. Meanwhile, the pitch of the pad patterns PADP1and PADP2is greater than the pitch of the bit line patterns BLP1and BLP2.

Referring toFIG. 3, the lengths of the bit line patterns BLP1and BLP2are different from each other. In this regard, when the pad patterns, e.g, PADP1and PADP2are respective connected to both ends of the bit line pattern BLP1and both ends of the bit line pattern BLP2, a position where the bit line pattern BLP1is connected to the pad pattern PADP1is different from a position where the bit line pattern BLP2is connected to the pad pattern PADP2. Accordingly, the bit line patterns BLP1and BLP2may be connected to the pad patterns PADP1and PADP2having a pitch different from that of the bit line patterns BLP1and BLP2in the memory cell array region.

At least one contact MC1and MC2may be respectively formed on the pad patterns PADP1and PADP2. The contacts MC1and MC2may be formed by metal contact, but may be formed using other various materials. The contacts MC1and MC2are formed in order to connect patterns formed on different layers with each other. The contacts MC1and MC2are vertically perforated to make a predetermined space, and thus there is limitation in decreasing the areas of the contact MC1and MC2. Therefore, it is difficult to directly form the contacts MC1and MC2on the bit line patterns BLP1and BLP2(Take into consideration that since the bit line patterns BLP1and BLP2are formed using the DPT, the pitch thereof is small). To address this problem, the bit line patterns BLP1and BLP2are respectively connected to the pad patterns PADP1and PADP2, and the contacts MC1and MC2are respectively formed on the pad patterns PADP1and PADP2.

The pad pattern PADP1is connected to a connect pattern CONP1via the contact MC1, and the pad pattern PADP2is connected to a connect pattern CONP2via the contact MC2. In the page buffer region to which the first page buffer330and the second page buffer340belong, the connect patterns CONP1and CONP2are respectively connected to page buffer patterns PBP1and PBP2. The connect patterns CONP1and CONP2and the page buffer patterns PBP1and PBP2may be formed on a layer that is upper or lower than the layer on which the bit line patterns BLP1and BLP2and the pad patterns PADP1and PADP2are formed.

As described above, the bit line patterns BLP1and BLP2may be formed using the DPT; however, it is difficult to form the page buffer patterns PBP1and PBP2using the DPT. Thus, when the DPT is used to form the bit line patterns BLP1and BLP2, the pitch thereof is decreased. Accordingly, the pitch of the page buffer patterns PBP1and PBP2is greater than the pitch of the bit line patterns BLP1and BLP2. Referring toFIG. 3, the pitch of the page buffer patterns PBP1and PBP2is 4 F (Compare it with the pitch (2 F) of the bit line patterns BLP1and BLP2illustrated inFIG. 3).

In addition, the connect patterns CONP1and CONP2are connected to the page buffer patterns PBP1and PBP2, and thus the pitch of the connect patterns CONP1and CONP2may be the same as the pitch of the page buffer patterns PBP1and PBP2.

FIG. 4is a diagram illustrating a layout of a semiconductor device according to another embodiment of the inventive concept.

Referring toFIG. 4, the semiconductor device according to the present embodiment includes a main array410, a first page buffer430, a second page buffer4, third page buffer450, and a fourth page buffer460. The main array410may belongs to a memory cell array region, and the first page buffer430, the second page buffer440, the third page buffer450, and the fourth page buffer460may belong to a page buffer region.

A plurality of bit line patterns BLP1through BLP6are formed on the main array410. A plurality of page buffer patterns PBP1through PBP6are formed in the page buffer region.

The bit line patterns BLP1through BLP6connected to the page buffer patterns PBP1through PBP6in the page buffer region. For example, the bit line patterns BLP1and BLP2may be respectively connected to the page buffer patterns PBP1and PBP2in the page buffer region to which the first page buffer430belongs, and the bit line patterns BLP3and BLP4may be respectively connected to the page buffer patterns PBP3and PBP4in the page buffer region to which the third page buffer450belongs. In addition, the page buffer patterns PBP1through PBP6in the page buffer regions to which the first and third page buffers430and450belong may be connected to page buffer patterns PBP7and PBP8in the page buffer regions to which the second and fourth page buffers440and460belong.

The pitch of the page buffer patterns PBP1through PBP8is greater than the pitch of the bit line patterns BLP1through BLP6. Referring toFIG. 4, the pitch of the page buffer patterns PBP1through PBP8is 4 F, and the pitch of the bit line patterns BLP1through BLP6is 2 F. In addition, as illustrated inFIG. 4, the width of the page buffer patterns PBP1through PBP8may be 3 F, and a distance between any two of the page buffer patterns PBP1through PBP8may be 1 F.

The page buffer patterns PBP1through PBP8may be formed on the same layer as that on which the bit line patterns BLP1through BLP6are formed (InFIG. 3, the page buffer patterns are formed on a layer that is different from the layer on which the bit line patterns are formed).

A layout method for a semiconductor device according to an embodiment of the inventive concept will now be described with reference toFIG. 3.

The plurality of bit line patterns BLP1and BLP2are formed on a first layer. The bit line patterns BLP1and BLP2may be formed using a DPT.

Next, the plurality of pad patterns PADP1and PADP2are formed on the first layer and are respectively connected to an end of the bit line pattern BLP1and an end of the bit line pattern BLP2. The pitch (for example, 4 F) of the pad patterns PADP1and PADP2may be greater than the pitch (for example, 2 F) of the bit line patterns BLP1and BLP2. The bit line patterns BLP1and BLP2and the pad patterns PADP1and PADP2are formed in a memory cell array region of the semiconductor device. The pad patterns, e.g., PADP1are connected to both ends of the bit line pattern BLP1, and the pad patterns, e.g., PADP2are connected to both ends of the bit line pattern BLP2.

Subsequently, the plurality of page buffer patterns PBP1and PBP2are formed on a second layer that is formed upper than the first layer. Then, a plurality of connect patterns CONP1and CONP2, which are connected to the pad patterns PADP1and PADP2, are formed on the second layer. The pitch of the connect patterns CONP1and CONP2may be greater than the pitch of the bit line patterns BLP1and BLP2, and may be the same as the pitch of the page buffer patterns PBP1and PBP2.

Lastly, at least one contact MC1is formed so as to vertically connect the pad pattern PADP1on the first layer with the connect pattern CONP1on the second layer, and at least one contact MC2is formed so as to vertically connect the pad pattern PADP2on the first layer with the connect pattern CONP2on the second layer.

A layout method for a semiconductor device according to another embodiment of the inventive concept will now be described with reference toFIG. 4.

The plurality of bit line patterns BLP1through BLP6are formed on a first layer. Then, the plurality of page buffer patterns PBP1through PBP8are formed on the first layer, and the page buffer patterns PBP1through PBP6are respectively connected to the bit line patterns BLP1through BLP6. The page buffer patterns PBP3and PBP4are respectively connected to the bit line patterns BLP3and BLP4in the page buffer region to which the third page buffer450belongs, and the page buffer patterns PBP1, PBP2, PBP5and PBP6are respectively connected to the bit line patterns BLP1, BLP2, BLP5and BLP6in the page buffer region to which the first page buffer430belongs. The pitch of the page buffer patterns PBP1through PBP8is greater than the pitch of the bit line patterns BLP1through BLP6.

As described above, in a semiconductor device according to the inventive concept, bit line patterns and page buffer lines having a pitch different from the pitch of the bit line patterns can be connected to each other.