Method of forming semiconductor cell structure, method of forming semiconductor device including the semiconductor cell structure, and method of forming semiconductor module including the semiconductor device

In a method of forming a semiconductor cell structure, a first insulating layer may be formed on a semiconductor substrate. A connection pattern may be formed in the first insulating layer. Second and third insulating layers may be sequentially formed on the connection pattern. The third insulating layer may be etched at least twice and the second insulating layer may be etched at least once to form a through hole in the second and third insulating layers. The through hole may expose the connection pattern.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2009-0124211, filed on Dec. 14, 2009, the contents of which are hereby incorporated herein by reference in its entirety.

BACKGROUND

Example embodiments relate to a method of forming a semiconductor cell structure, a method of forming a semiconductor device including the semiconductor cell structure, and a method of forming a semiconductor module including the semiconductor device.

2. Description of Related Art

A method of fabricating a semiconductor cell structure on a semiconductor substrate includes reducing a thickness of a stacked layer and a distance between conductive patterns based on shrinkage of a design rule of a semiconductor device. The stacked layer may insulate the conductive layers from each other or support the conductive layers. The conductive patterns may be disposed in the stacked layer to provide a transmission path of an internal or external electrical signal of the semiconductor device. In such a case, the stacked layer may have a lower insulating layer and an upper insulating layer. The lower insulating layer may expose a portion of the conductive patterns and cover the remainder thereof.

The upper insulating layer may be formed on the lower insulating layer and the conductive patterns. The upper insulating layer may have through holes exposing the portion of the conductive patterns. The through holes may be filled with electric nodes. However, diameters of the through holes may shrink according to continuous reduction in the distance between the conductive patterns. The electric nodes may have greater contact resistance with respect to the portion of the conductive patterns through the through holes compared with before the shrink design rule of the semiconductor device. The electric nodes may have a greater internal resistance compared with before the shrink design rule of the semiconductor device.

Furthermore, the through holes may pass the upper insulating layer to extend towards the lower insulating layer. The electric node may be electrically short-circuited with the remainder of the conductive patterns through the through holes. As a result, the semiconductor cell structure may deteriorate electrical characteristics of the semiconductor device compared with before the shrink design rule of the semiconductor device. The semiconductor device may be disposed in a semiconductor module and a processor-based system. The semiconductor module and the processor-based system may have degraded electrical characteristics due to the semiconductor device.

SUMMARY

The present invention provides a method of forming a semiconductor cell structure capable of stably enlarging diameters of through holes disposed on a lower insulating layer and passing an upper insulating layer.

The present invention also provides a method of forming a semiconductor cell structure that does not expose conductive patterns in a lower insulating layer to through holes surrounded by an upper insulating layer.

The present invention provides a method of forming a semiconductor device and a method of forming a semiconductor module, which are capable of improving electrical characteristics by using the semiconductor cell structure. The present invention also provides an etch stopping layer disposed on the lower insulating layer and in the upper insulating layer, and the etch stopping layer having a different etch rate from the lower insulating layer and the remaining upper insulating layer.

According to an example embodiment, a method of forming a semiconductor cell structure may include forming first and second patterns over a semiconductor substrate. Forming each of the first and second patterns may include sequentially stacking a conductive pattern and a mask pattern. A first insulating layer may be formed to surround the first and second patterns. A connection pattern may be formed in the first insulating layer to be located in a region between the first and second patterns. Second and third insulating layers may be sequentially formed on the connection pattern. The third insulating layer may be etched at least twice and the second insulating layer at least once to form a through hole. The through hole may be surrounded by at least one of the second and third insulating layers.

According to an example embodiment, the mask pattern may include silicon and nitrogen. The first insulating layer may include silicon and oxygen. The second insulating layer may include aluminum and nitrogen and be formed to cover the first and second patterns, the connection pattern and the first insulating layer. The third insulating layer may include an insulating material having a concentration gradient of impurity ions along a thickness direction perpendicular to a top surface thereof. The conductive pattern and the connection pattern may include conductive material.

According to an example embodiment, the etching the third insulating layer at least twice and the second insulating layer at least once to form a through hole step may include forming a photoresist layer on the third insulating layer. The photoresist layer may have an opening aligning the connection pattern and exposing the third insulating layer. The third insulating layer may be etched through the opening using the photoresist layer as an etch mask to form a first preliminary through hole in the third insulating layer. The first preliminary through hole may have substantially a same diameter along the thickness direction perpendicular to the top surface of the third insulating layer. The first preliminary through hole may expose the second insulating layer. The photoresist layer may be removed from the semiconductor substrate. A lower portion of the third insulating layer may be etched through the first preliminary through hole using the third insulating layer as an etch mask to form a second preliminary through hole. The second preliminary through hole may have a diameter D2in the lower portion of the third insulating layer, and a diameter D1in an upper portion of the third insulating layer, wherein D2>D1. The second insulating layer may be etched through the second preliminary through hole using the third insulating layer as an etch mask to form the through hole exposing the connection pattern.

According to an example embodiment, the mask pattern may include silicon and nitrogen. The first insulating layer may include silicon and oxygen. The second insulating layer may include aluminum and nitrogen, and be formed to cover the connection pattern. The third insulating layer may include an insulating material having a concentration gradient of impurity ions along a thickness direction perpendicular to a top surface thereof. The conductive pattern and the connection pattern may include conductive material.

According to an example embodiment, the etching the third insulating layer at least twice and the second insulating layer at least once to form a through hole step may include forming a photoresist layer on the third insulating layer. The photoresist layer may have an opening aligning the connection pattern and exposing the third insulating layer. The third insulating layer may be etched through the opening using the photoresist layer as an etch mask to form a first preliminary through hole in the third insulating layer. The first preliminary through hole may have substantially a same diameter along a thickness direction perpendicular to the top surface of the third insulating layer, and the first preliminary through hole may expose the second insulating layer. The photoresist layer may be removed from the semiconductor substrate. A lower portion of the third insulating layer may be etched through the first preliminary through hole using the third insulating layer as an etch mask to form a second preliminary through hole. The second preliminary through hole may have a diameter D2in the lower portion of the third insulating layer, and a diameter D1in an upper portion of the third insulating layer, wherein D2>D1. The second insulating layer may be etched through the second preliminary through hole using the third insulating layer as an etch mask to form the through hole exposing the connection pattern.

According to an example embodiment, a method of forming a semiconductor device may comprise forming an active region in a semiconductor substrate. First and second patterns may be formed over the active region to pass the active region. Forming each of the first and second patterns may include sequentially stacking a conductive pattern and a mask pattern. A first insulating layer may be formed around the first and second patterns to expose the first and second patterns. A connection pattern may be formed in the first insulating layer to be located in a region between the first and second patterns. The connection pattern may be electrically connected to the active region. Second and third insulating layers may be sequentially formed on the connection pattern. The third insulating layer may be etched at least twice and the second insulating layer at least once to form a through hole. The connection pattern may be surrounded by at least one of the second and third insulating layers. The first to third insulating layers may have different etch rates from each other. The second insulating layer may be formed from different material from the mask pattern.

According to an example embodiment, the mask pattern includes one of aluminum and silicon, and nitrogen. The first insulating layer includes silicon and oxygen. The second insulating layer includes one of aluminum and silicon, and nitrogen, and is formed to cover the first and second patterns, the connection pattern and the first insulating layer. The conductive pattern and the connection pattern include conductive material.

According to an example embodiment, The third insulating layer may include one of a first insulating material having a concentration gradient of impurity ions along a thickness direction perpendicular to a top surface thereof, and second insulating materials stacked sequentially toward the top surface thereof, and the third insulating layer may have a greater etch rate at a lower portion of the third insulating layer than an upper portion thereof.

According to an example embodiment, the etching the third insulating layer at least twice sand the second insulating layer at least once to form a through hole step may include forming a photoresist layer on the third insulating layer. The photoresist layer may have an opening aligning the connection pattern and exposing the third insulating layer. The third insulating layer may be etched through the opening using the photoresist layer as an etch mask to form a first preliminary through hole in the third insulating layer. The first preliminary through hole may have substantially a same diameter along a thickness direction perpendicular to the top surface of the third insulating layer, and the first preliminary through hole may expose the second insulating layer. The photoresist layer may be removed from the semiconductor substrate. A lower portion of the third insulating layer may be etched through the first preliminary through hole using the third insulating layer as an etch mask to form a second preliminary through hole. The second preliminary through hole may have a diameter D2in the lower portion of the third insulating layer, and a diameter D1in an upper portion of the third insulating layer, wherein D2>D1. The second insulating layer may be etched through the second preliminary through hole using the third insulating layer as an etch mask to form the through hole exposing the connection pattern.

According to an example embodiment, the first preliminary through hole may be formed by applying a dry etchant to the third insulating layer. The second preliminary through hole may be formed by applying one selected from wet and dry etchants to the third insulating layer. The through hole may be formed by applying one selected from wet and dry etchants to the second insulating layer.

According to an example embodiment, the wet etchant applied to the second insulating layer may include one of H2SO4, H3PO4, and SC-1 or a combination of H2SO4and SC-1. According to an example embodiment, the mask pattern may include one of aluminum and silicon, and nitrogen. The first insulating layer may include silicon and oxygen. The second insulating layer may include one of aluminum and silicon, and nitrogen, and be formed to cover the connection pattern. The conductive pattern and the connection pattern include conductive material.

According to an example embodiment, the third insulating layer may include one of a first insulating material having a concentration gradient of impurity ions along a thickness direction perpendicular to a top surface thereof, and second insulating materials stacked sequentially toward the top surface thereof, and the third insulating layer may have a greater etch rate at a lower portion of the third insulating layer than an upper portion thereof.

According to an example embodiment, the etching the third insulating layer at least twice and the second insulating layer at least once to form a through hole step may include forming a photoresist layer on the third insulating layer. The photoresist layer may have an opening aligning the connection pattern and exposing the third insulating layer. The third insulating layer may be etched through the opening using the photoresist layer as an etch mask to form a first preliminary through hole in the third insulating layer. The first preliminary through hole may have substantially a same diameter along a thickness direction perpendicular to the top surface of the third insulating layer, and the first preliminary through hole may expose the second insulating layer. The photoresist layer may be removed from the semiconductor substrate. A lower portion of the third insulating layer may be etched through the first preliminary through hole using the third insulating layer as an etch mask to form a second preliminary through hole. The second preliminary through hole may have a diameter D2in the lower portion of the third insulating layer, and a diameter D1in an upper portion of the third insulating layer, wherein D2>D1. The second insulating layer may be etched through the second preliminary through hole using the third insulating layer as an etch mask to form the through hole exposing the connection pattern.

According to an example embodiment, the first preliminary through hole may be formed by applying a dry etchant to the third insulating layer. The second preliminary through hole may be formed by applying one selected from wet and dry etchants to the third insulating layer. The through hole may be formed by applying a dry etchant to the second insulating layer including one of H2SO4, H3PO4, and SC-1 or a combination of H2SO4and SC-1.

According to an example embodiment, a method of forming a semiconductor module may comprise preparing a module substrate and at least one semiconductor package structure. The module substrate may be electrically connected to the at least one semiconductor package structure. The at least one semiconductor package structure may have a semiconductor device. The semiconductor device may be formed by using the method of forming a semiconductor cell structure including forming first and second patterns over a semiconductor substrate. Forming each of the first and second patterns may include sequentially stacking a conductive pattern and a mask pattern. A first insulating layer may be formed to surround the first and second patterns. A connection pattern may be formed in the first insulating layer in a region between the first and second patterns. Second and third insulating layers may be sequentially formed on the connection pattern. The third insulating layer may be etched at least twice and the second insulating layer at least once to form a through hole. The through hole may be surrounded by at least one of the second and third insulating layers.

According to an example embodiment, the mask pattern may include silicon and nitrogen. The first insulating layer may include silicon and oxygen. The second insulating layer may include aluminum and nitrogen, and be formed to cover first and second patterns, the connection pattern, and the first insulating layer. The third insulating layer may include an insulating material having a concentration gradient of impurity ions along a thickness direction perpendicular to a top surface thereof. The conductive pattern and the connection pattern may include conductive material.

According to an example embodiment, the etching the third insulating layer at least twice and the second insulating layer at least once to form a through hole step may include forming a photoresist layer on the third insulating layer. The photoresist layer may have an opening aligning the connection pattern and exposing the third insulating layer. The third insulating layer may be etched through the opening using the photoresist layer as an etch mask to form a first preliminary through hole in the third insulating layer. The first preliminary through hole may have substantially a same diameter along a thickness direction perpendicular to the top surface of the third insulating layer, and the first preliminary through hole may expose the second insulating layer. The photoresist layer may be removed from the semiconductor substrate. A lower portion of the third insulating layer may be etched through the first preliminary through hole using the third insulating layer as an etch mask to form a second preliminary through hole. The second preliminary through hole may have a diameter D2in the lower portion of the third insulating layer, and a diameter D1in an upper portion of the third insulating layer, wherein D2>D1. The second insulating layer may be etched through the second preliminary through hole using the third insulating layer as an etch mask to form the through hole exposing the connection pattern.

According to an example embodiment, the mask pattern may include silicon and nitrogen. The first insulating layer may include silicon and oxygen. The second insulating layer may include aluminum and nitrogen, and be formed to cover the connection pattern. The third insulating layer may include an insulating material having a concentration gradient of impurity ions along a thickness direction perpendicular to a top surface thereof. The conductive pattern and the connection pattern may include conductive material.

According to an example embodiment, the etching the third insulating layer at least twice and the second insulating layer at least once to form a through hole step may include forming a photoresist layer on the third insulating layer. The photoresist layer may have an opening aligning the connection pattern and exposing the third insulating layer. The third insulating layer may be etched through the opening using the photoresist layer as an etch mask to form a first preliminary through hole in the third insulating layer. The first preliminary through hole may have substantially a same diameter along a thickness direction perpendicular to the top surface of the third insulating layer, and the first preliminary through hole may expose the second insulating layer. The photoresist layer may be removed from the semiconductor substrate. A lower portion of the third insulating layer may be etched through the first preliminary through hole using the third insulating layer as an etch mask to form a second preliminary through hole. The second preliminary through hole may have a diameter D2in the lower portion of the third insulating layer, and a diameter D1in an upper portion of the third insulating layer, wherein D2>D1. The second insulating layer may be etched through the second preliminary through hole using the third insulating layer as an etch mask to form the through hole exposing the connection pattern.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Various example embodiments will now be described more fully with reference to the accompanying drawings in which some example embodiments are shown. This inventive concept may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure is thorough and complete and fully conveys the scope of the inventive concept to one skilled in the art. In the drawings, the thickness of layers and regions may be exaggerated for clarity. Also, when it is referred that a layer is “on” another layer or a substrate, it may be directly formed on another layer or the substrate or a third layer may be interposed therebetween. Like reference numerals designate like elements throughout the specification.

It will be understood that, although the terms first, second, third, etc., may be used herein to describe various elements, components and/or sections, these elements, components and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component or section from another element, component or section. Thus, a first element, component or section discussed below could be termed a second element, component or section without departing from the teachings of the inventive concepts.

Spatially relative terms, such as “below,” “beneath,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one device or element's relationship to another device(s) or element(s) as illustrated in the drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings.

A method of forming a semiconductor cell structure according to example embodiments will be described below with reference to the accompanying drawings.FIG. 1is a plan view of a semiconductor cell structure according to an example embodiment.

Referring toFIG. 1, a semiconductor cell structure140according to an example embodiment may include first and second patterns15and70. The first patterns15may be disposed to be parallel to each other along one direction in the semiconductor cell structure140. The first patterns15may include a gate pattern or a pattern other than the gate pattern. The second patterns70may be disposed to be parallel to each other along the other direction in the semiconductor cell structure140. The second patterns70may be disposed on the first patterns15to cross the first patterns15.

The second patterns70may include a bit line pattern or a pattern other than the bit line pattern. Active regions9may be disposed between the first and second patterns15and70. The active regions9may be partially exposed between the first and second patterns15and70. The active regions9may cross the first patterns15. Each of the active regions9may be electrically connected (not shown) to one of the adjacent two second patterns70or may not be electrically connected to the adjacent second patterns70. Landing pads30may be disposed on the active regions9.

The landing pads30may be disposed to partially expose the active regions9. Each of the landing pads30may be disposed on an edge of each of the active regions9. Second connection holes80may be disposed on the landing pads30. The second connection holes80may be filled with connection patterns85ofFIG. 4. Through holes129may overlap the second connection holes80. The through holes129may be filled with plugs134ofFIG. 12or electric nodes138ofFIG. 13.

As a variation of example embodiments, the semiconductor cell structure140may not have the first patterns15and the landing pads30on the active regions9. In this case, the connection patterns85may be disposed in predetermined or given regions between the second patterns70to be in direct contact with the active regions9.

FIGS. 2 to 6are cross-sectional views taken along line I-I′ ofFIG. 1, illustrating an intermediate step of a method of forming a semiconductor cell structure. Referring toFIG. 2, a semiconductor substrate3may be prepared according to example embodiments. The semiconductor substrate3may include a non-active region6and active regions9. The non-active region6may be formed in the semiconductor substrate3to define the active regions9. The non-active region6may be filled with a device isolation layer. The device isolation layer may include insulating material. The first patterns15ofFIG. 1may be formed on the non-active regions6and the active regions9. The first patterns15may pass over the active regions9to be formed on the non-active regions6.

A first insulating layer20may be formed on the non-active regions6and the active regions9to cover the first patterns15. The first insulating layer20may include insulating material having the same etch rate as or a different etch rate from the device isolation layer. The first insulating layer20may be formed of silicon and oxygen. Photolithography and etch processes or only an etch process may be performed on the first insulating layer20to form first connection holes25in the first insulating layer20. The first connection holes25may be formed in predetermined or given regions between the first patterns15.

The first connection holes25may penetrate the first insulating layer20to expose the non-active regions6and the active regions9or only the active regions9. Landing pads30may be formed in the first connection holes25to fill the first connection holes25. The landing pads30may be in direct contact with the non-active region6and the active regions9, or only the active regions9. The landing pads30may include doped polysilicon, metal material, metal nitride, or stacked materials thereof. As a variation according to example embodiments, the first patterns15, the first insulating layer20and the landing pads30may not be formed on the non-active regions6and the active regions9.

Referring toFIG. 3, according to example embodiments, a second insulating layer40may be formed on the first insulating layer20and the landing pads30. The second insulating layer40may include insulating material having the same etch rate as or a different etch rate from the first insulating layer20. The second insulating layer40may be formed of silicon and oxygen, e.g., SiO2. A conductive layer50and a mask layer60may be sequentially formed on the second insulating layer40. The conductive layer50may include doped polysilicon, metal material, metal nitride, or stacked materials thereof.

The conductive layer50may be in direct contact with at least one of the active regions9through contact holes (not shown) in the first and second insulating layers20and40or may not be in contact with the active regions9. The mask layer60may include insulating material having the same etch rate as or a different etch rate from the second insulating layer40. The mask layer60may include one of aluminum and silicon, and nitrogen, e.g., aluminum nitride (AlN), silicon nitride (SiN) or silicon oxynitride (SiON).

As a variation of example embodiments, when the first patterns15, the first insulating layer20and the landing pads30are not formed on the non-active regions6and the active regions9, the second insulating layer40may be formed to cover the non-active regions6and the active regions9. The conductive layer50may be in direct contact with at least one of the active regions9through the contact holes in the second insulating layer40or may be not in contact with the active regions9.

Referring toFIG. 4, photolithography and etch processes are performed on the conductive layer50and the mask layer60to form conductive patterns55and mask patterns65on the second insulating layer40. The conductive patterns55and the mask patterns65may form second patterns70. Spacers75may be formed on sidewalls of the second patterns70. The spacers75may include insulating material having the same etch rate as or a different etch rate from the mask patterns65.

The spacers75may include insulating material having the same etch rate as or a different etch rate from the second insulating layer40. A third insulating layer (not shown) may be formed around the second patterns70to expose the second patterns70. The third insulating layer may include insulating material having a different etch rate from the mask patterns65. The third insulating layer may include insulating material having the same etch rate as or a different etch rate from the second insulating layer40. The third insulating layer may be formed of silicon and oxygen, e.g., SiO2.

Second connection holes80may be formed in predetermined or given regions between the second patterns70. The second connection holes80may be formed to expose the landing pads30. The second connection holes80may be surrounded by the second insulating layer40, the third insulating layer and the second patterns70. The second connection holes80may be surrounded by the second insulating layer40and the third insulating layer. Connection patterns85may be formed to fill the second connection holes80. The connection patterns85may include doped polysilicon, metal material, metal nitride, or stacked materials thereof.

The connection patterns85may be in contact with the landing pads30through the second connection holes80. The first insulating layer20, the second insulating layer40, the mask patterns65, the spacers75and the third insulating layer (not shown) may constitute a lower insulating layer. As a variation of example embodiments, when the first patterns15, the first insulating layer20and the landing pads30are not formed on the non-active regions6and the active regions9, the connection patterns85may be in direct contact with the active regions9through the second connection holes80.

Referring toFIG. 5, according to example embodiments, fourth to sixth insulating layers90,100, and110may be sequentially formed on the second patterns70, the spacers75and the connection patterns85. The fourth insulating layer90may include insulating material having a different etch rate from the mask patterns65and the spacers75. The fourth insulating layer90may include insulating material having a different etch rate from the third insulating layer. The fourth insulating layer90may be formed of one of aluminum and silicon, and nitrogen, e.g., AlN, SiN or SiON.

Therefore, when the mask patterns65are formed of SiN or SiON, the fourth insulating layer90may be formed of AlN. When the mask patterns65are formed of AlN, the fourth insulating layer90may be formed of SiN or SiON. The fourth insulating layer90may be used as an etch stopping layer when the fifth and sixth insulating layers100and110are etched.

The fifth insulating layer100may include insulating material having a different etch rate from the fourth insulating layer90. The sixth insulating layer110may include insulating material having a different etch rate from the fifth insulating layer100. The fifth and sixth insulating layers100and110may constitute an upper insulating layer. The fifth and sixth insulating layers100and110may have an external interface A along contacting surfaces with respect to each other.

Referring toFIG. 6, according to example embodiments, a photoresist layer (not shown) may be formed on the sixth insulating layer110. The photoresist layer may have openings aligning the connection patterns85and exposing the sixth insulating layer110. The fifth and sixth insulating layers100and110may be etched through the openings using the photoresist layer as an etch mask.

In this case, the fifth and sixth insulating layers100and110may be etched using a first dry etchant including hexafluorobutyne (C4F6), oxygen (O2), and at least one of octafluorocyclobutane (C4F8), octafluoropropane (C3F8), tetrafluoromethane (CF4) and carbon monoxide (CO).

The first dry etchant may have an etch selectivity with respect to the fourth to sixth insulating layers90to110. After the fifth and sixth insulating layers100and110are etched, the fifth and sixth insulating layers100and110may have first preliminary through holes123aligned with the openings of the photoresist layer. The first preliminary through holes123may have substantially the same first diameters S1along a thickness direction perpendicular to top surfaces of the fifth and sixth insulating layers100and110. In this case, each of the first preliminary through holes123may have substantially the same first sidewalls SW1in the fifth and sixth insulating layers100and110.

The first preliminary through holes123may be formed to expose the fourth insulating layer90. After the first preliminary through holes123are formed in the fifth and sixth insulating layers100and110, the photoresist layer may be removed from the sixth insulating layer110. The fifth insulating layer100may be etched through the first preliminary through holes123using the fifth and sixth insulating layers100and110as an etch mask. The fifth insulating layer100may be etched using a first wet etchant including hydrofluoric acid (HF) or standard cleaning-1 (SC-1).

The first wet etchant may have an etch selectivity with respect to the fourth to sixth insulating layers90to110. The SC-1 may be formed of ammonia water (NH4OH), hydrogen peroxide (H2O2) and deionized water (H2O). The SC-1 may be used at a lower temperature (a temperature ranging from 30 to 50° C.) or higher temperature (a temperature ranging from 50 to 80° C.). In such a case, the first wet etchant may remove a sacrificial region105from the first sidewall SW1of the fifth insulating layer100.

More specifically, the first preliminary through holes123may be formed as second preliminary through holes126Each of the second preliminary through holes126may have a second diameter S2in the fifth insulating layer100, and a first diameter S1in the sixth insulating layer110. The first diameter S1may be smaller than the second diameter S2. Each of the second preliminary through holes126may have a second sidewall SW2in the fifth insulating layer100, and a first sidewall SW1in the sixth insulating layer110.

The second preliminary through holes126may be formed by etching the fifth insulating layer100using a second dry etchant. The second dry etchant may have an etch selectivity with respect to the fourth to sixth insulating layers90to110. Then, the fourth insulating layer90may be etched through the second preliminary through holes126using the fifth and sixth insulating layers100and110as an etch mask. When SiN or SiON corresponds to the mask patterns65, and AlN corresponds to the fourth insulating layer90, the fourth insulating layer90may be etched using a second wet etchant including sulfuric acid (H2SO4) or SC-1.

The second wet etchant may have an etch selectivity with respect to the mask patterns65, the spacers75, the third insulating layer and the fourth to sixth insulating layers90to110. H2SO4may be applied to the fourth insulating layer90at a first step, and SC-1 may be applied to the fourth insulating layer90at a second step to be wet etched.

The SC-1 may be used at a lower temperature (a temperature ranging from 30 to 50° C.). The fourth insulating layer90may be etched using a third dry etchant including chlorine (Cl2), oxygen (O2), hydrogen bromide (HBr) and hydrogen (H2). The third dry etchant may have an etch selectivity with respect to the mask patterns65, the spacers75, the third insulating layer and the fourth to sixth insulating layers90to110.

In contrast, when AlN corresponds to the mask patterns65, and SiN or SiON corresponds to the fourth insulating layer90, the fourth insulating layer90may be etched using a third wet etchant including phosphoric acid (H3PO4). The third wet etchant may have an etch selectivity with respect to the mask patterns65, the spacers75, the third insulating layer and the fourth to sixth insulating layers90to110.

The fourth insulating layer90may be etched using a fourth dry etchant including tetrafluoromethane (CF4), trifluoromethane (CHF3), difluoromethane (CH2F2), fluoromethane (CH3F) and Oxygen (O2). The fourth dry etchant may have an etch selectivity with respect to the mask patterns65, the spacers75, the third insulating layer and the fourth to sixth insulating layers90to110.

The second wet etchant, the third wet etchant, the third dry etchant or the fourth dry etchant may remove a sacrificial region94of the fourth insulating layer90below the second preliminary through holes126. After the fourth insulating layer90is etched by the second wet etchant, the third wet etchant, the third dry etchant or the fourth dry etchant, the fourth insulating layer90may be formed to expose the connection patterns85. As a result, the fourth to sixth insulating layers90to110may have through holes129.

The through holes129may have substantially the same diameters S1and S2as the second preliminary through holes126in the fifth and sixth insulating layers100and110. The through holes129may have the same second diameters S2in the fourth and fifth insulating layers90and100. Therefore, the through holes129may have different diameters S1and S2at a lower part and an upper part with respect to the external interface A between the fifth and sixth insulating layers100and110. The through holes129may fully expose the connection patterns85. As a result, the through holes129may be stably formed to be large through the fourth to sixth insulating layers90to110.

The second wet etchant, the third wet etchant, the third dry etchant or the fourth dry etchant may remove the fourth insulating layer90to a desired extent without causing etch damage to the lower insulating layer. In addition, even when the first preliminary through holes123are misaligned with the connection patterns85, the second wet etchant, the third wet etchant, the third dry etchant or the fourth dry etchant may remove the fourth insulating layer90without causing etch damage to the lower insulating layer.

FIGS. 7 and 8are cross-sectional views taken along line I-I′ ofFIG. 1, illustrating an intermediate step of a method of forming a semiconductor cell structure. InFIGS. 7 and 8, like reference numerals designate like elements inFIGS. 1 to 6.

Referring toFIG. 7, fourth and fifth insulating layers90and100may be sequentially formed on the second patterns70, the third insulating layer, the spacers75and the connection patterns85ofFIG. 4. The thickness of the fifth insulating layer100may be substantially the same as or different from that of the fifth and sixth insulating layers100and110ofFIG. 5. The fifth insulating layer100may include insulating material having a concentration gradient of impurity ions along a thickness direction perpendicular to a top surface.

The concentration gradient of impurity ions may be obtained by performing an ion implantation process on the fifth insulating layer100or a deposition process of the fifth insulating layer100on the fourth insulating layer90. The ion implantation process may be performed on the fifth insulating layer100by adjusting implantation energy of impurity ions. The deposition process may be performed by differentiating concentration of the impurity ions along a deposition time while depositing the fifth insulating layer100on the fourth insulating layer90. The fifth insulating layer100may have an internal interface B connecting inflection points of the concentration gradient of the impurity ions in a parallel manner with respect to a top surface thereof.

Referring toFIG. 8, according to example embodiments, the processes ofFIG. 6may be applied to the fourth and fifth insulating layers90and100in the same manner. For this purpose, the first dry etchant ofFIG. 6may be applied to the fifth insulating layer100. The first dry etchant may have an etch selectivity with respect to the fourth and fifth insulating layers90and100. The first dry etchant may form first preliminary through holes123in the fifth insulating layer100through the openings of the photoresist layer ofFIG. 6. The first preliminary through holes123may have substantially the same diameters S1as those of the first preliminary through holes123ofFIG. 6.

Then, the first wet etchant or the second dry etchant ofFIG. 6may be applied to the fifth insulating layer100. The first wet etchant or the second dry etchant may remove a sacrificial region105of the fifth insulating layer100through the first preliminary through holes123. The fifth insulating layer100may have second preliminary through holes126through the first wet etchant or the second dry etchant. The second preliminary through holes126may have substantially the same diameters S1and S2as the second preliminary through holes126ofFIG. 6.

Afterwards, the second wet etchant, the third wet etchant, the third dry etchant or the fourth dry etchant may be applied to the fourth insulating layer90. The second wet etchant, the third wet etchant, the third dry etchant or the fourth dry etchant may remove a sacrificial region94of the fourth insulating layer90through the second preliminary through holes126. The fourth insulating layer90may be etched using the second wet etchant, the third wet etchant, the third dry etchant or the fourth dry etchant to expose the connection patterns85. As a result, the fourth and fifth insulating layers90and100may have through holes129.

The through holes129may have substantially the same diameters S1and S2as the through holes129ofFIG. 6. In this case, the through holes129may have different diameters S1and S2at a lower part and an upper part with respect to an internal interface B of the fifth insulating layer100. The through holes129may fully expose the connection patterns85.

FIGS. 9 and 10are cross-sectional views taken along line I-I′ ofFIG. 1, illustrating an intermediate step of a method of forming a semiconductor cell structure. InFIGS. 9 and 10, like reference numerals designate like elements inFIGS. 1 to 6.

Referring toFIG. 9, a fourth insulating layer90may be formed on the second patterns70, the third insulating layer, the spacers75and the connection patterns85ofFIG. 4. Photoresist patterns (not shown) may be formed on the fourth insulating layer90. The photoresist patterns may be formed to be aligned with the connection patterns85. An area of each of the photoresist patterns may be the same size as or a different size from that of each of the connection patterns85. The fourth insulating layer90may be etched using the photoresist patterns as an etch mask.

In this case, the fourth insulating layer90may be etched using the third dry etchant or the fourth dry etchant ofFIG. 6. The third dry etchant or the fourth dry etchant may etch the fourth insulating layer90, so that sacrificial patterns98are formed on the connection patterns85. When the photoresist patterns are replaced by hard patterns, the second wet etchant or the third wet etchant ofFIG. 6may be applied to the fourth insulating layer90. The sacrificial patterns98may be formed to expose the second patterns70, the spacers75and the third insulating layer.

The sacrificial patterns98may be formed to expose the second patterns70, the spacers75, the third insulating layer, and the connection patterns85. Afterwards, the photoresist patterns may be removed from the sacrificial patterns98. The fifth and sixth insulating layers100and110may be sequentially formed on the second patterns70, the spacers75, the third insulating layer, and the connection patterns85to cover the sacrificial patterns98. The fifth and sixth insulating layers100and110may have an external interface A along contacting surfaces with respect to each other.

Referring toFIG. 10, according to example embodiments, the processes ofFIG. 6may be applied to the fifth and sixth insulating layers100and110in the same manner. For this purpose, the first dry etchant ofFIG. 6may be applied to the fifth and sixth insulating layers100and110. The first dry etchant may form first preliminary through holes123in the fifth and sixth insulating layers100and110through the openings of the photoresist layer ofFIG. 6. The first preliminary through holes123may have substantially the same diameters S1as the first preliminary through holes123ofFIG. 6.

The first wet etchant or the second dry etchant ofFIG. 6may be applied to the fifth insulating layer100. The first wet etchant or the second dry etchant may remove the sacrificial region105of the fifth insulating layer100through the first preliminary through holes123. The fifth and sixth insulating layers100and110may have second preliminary through holes126through the first wet etchant or the second dry etchant. The second preliminary through hole126may expose the sacrificial patterns98. The second preliminary through holes126may have substantially the same diameters S1and S2as the second preliminary through holes126ofFIG. 6.

Subsequently, a second wet etchant, a third wet etchant, a third dry etchant or a fourth dry etchant may be applied to the sacrificial patterns98. The second wet etchant, the third wet etchant, the third dry etchant or the fourth dry etchant may fully remove the sacrificial patterns98from the semiconductor substrate3through the second preliminary through holes126. In this case, the connection patterns85may be exposed to the fifth and sixth insulating layers100and110. As a result, the fifth and sixth insulating layers100and110may have through holes129.

Alternatively, the second wet etchant, the third wet etchant, the third dry etchant or the fourth dry etchant may partially remove the sacrificial patterns98from the semiconductor substrate3. In such a case, the sacrificial patterns98may partially remain below the fifth insulating layer100. The sacrificial patterns98may be etched by the second wet etchant, the third wet etchant, the third dry etchant or the fourth dry etchant to expose the connection patterns85. As a result, the sacrificial patterns98and the fifth and sixth insulating layers100and110may have through holes129.

The through holes129may have substantially the same diameters S1and S2as the through holes129ofFIG. 6. The through holes129may have different diameters S1and S2at an upper part and a lower part with respect to the external interface A of the fifth and sixth insulating layers100and110. The through holes129may fully expose the connection patterns85. As a result, the through holes129may be stably formed to be large through the fifth and sixth insulating layers100and110.

The second wet etchant, the third wet etchant, the third dry etchant or the fourth dry etchant may sufficiently remove the sacrificial patterns98without causing etch damage to the lower insulating layer. In addition, even when the first preliminary through holes123are misaligned with the connection patterns85, the second wet etchant, the third wet etchant, the third dry etchant or the fourth dry etchant may remove the sacrificial patterns98without causing etch damage to the lower insulating layer.

FIG. 11is a cross-sectional view taken along line I-I′ ofFIG. 1, illustrating an intermediate step of a method of forming a semiconductor cell structure. InFIG. 11, like reference numerals designate like elements inFIGS. 1 to 6.

Referring toFIG. 11, the fourth insulating layer90ofFIG. 9may be formed on the second patterns70, the third insulating layer, the spacers75and the connection patterns85ofFIG. 4. Photoresist patterns (not shown) may be formed on the fourth insulating layer90. The photoresist patterns may be formed to be aligned with the connection patterns85. Area of each of the photoresist patterns may be the same size as or different sizes from that of each of the connection patterns85. The fourth insulating layer90may be etched using the photoresist patterns as an etch mask.

In this case, the fourth insulating layer90may be etched through the third dry etchant or the fourth dry etchant ofFIG. 6. The third dry etchant or the fourth dry etchant may etch the fourth insulating layer90, so that sacrificial patterns98are formed on the connection patterns85. The sacrificial patterns98may be formed to expose the second patterns70, the spacers75and the third insulating layer. The sacrificial patterns98may be formed to expose the second patterns70, the spacers75, the third insulating layer, and the connection patterns85.

The photoresist patterns may be removed from the sacrificial patterns98. The fifth insulating layer100ofFIG. 7may be formed on the second patterns70, the spacers75, the third insulating layer, and the connection patterns85to cover the sacrificial patterns98. The fifth insulating layer100may have an internal interface B connecting inflection points of the concentration gradient of impurity ions in a parallel manner with respect to a top surface thereof. The processes ofFIG. 6may be applied to the sacrificial patterns98and the fifth insulating layer100in the same manner.

For this purpose, the first dry etchant ofFIG. 6may be applied to the fifth insulating layer100. The first dry etchant may form first preliminary through holes123in the fifth insulating layer100through the openings of the photoresist layer ofFIG. 6. The first dry etchant may have an etch selectivity with respect to the sacrificial patterns98and the fifth insulating layer100. The first preliminary through holes123may have substantially the same diameters S1as those of the first preliminary through holes123ofFIG. 6. Afterwards, the first wet etchant or the second dry etchant ofFIG. 6may be applied to the fifth insulating layer100.

The first wet etchant or the second dry etchant may remove the sacrificial region105of the fifth insulating layer100through the first preliminary through holes123. The fifth insulating layer100may have second preliminary through holes126using the first wet etchant or the second dry etchant. The second preliminary through holes126may have substantially the same diameters S1and S2as the second preliminary through holes126ofFIG. 6. Subsequently, the second wet etchant, the third wet etchant, the third dry etchant or the fourth dry etchant may be applied to the sacrificial patterns98.

The second wet etchant, the third wet etchant, the third dry etchant or the fourth dry etchant may fully remove the sacrificial patterns98from the semiconductor substrate3through the second preliminary through holes126. In this case, the connection patterns85may be exposed to the fifth insulating layer100. As a result, the fifth insulating layer100may have through holes129. In contrast, the second wet etchant, the third wet etchant, the third dry etchant or the fourth dry etchant may partially remove the sacrificial patterns98from the semiconductor substrate3.

In such a case, the sacrificial patterns98may partially remain below the fifth insulating layer100. The sacrificial patterns98may expose the connection patterns85using the second wet etchant, the third wet etchant, the third dry etchant or the fourth dry etchant. As a result, the sacrificial patterns98and the fifth insulating layer100may have through holes129. The through holes129may have substantially the same diameters S1and S2as the through holes129ofFIG. 6.

In this case, the through holes129may have different diameters S1and S2at an upper part and a lower part with respect to an internal interface B of the fifth insulating layer100. The through holes129may fully expose the connection patterns85.

FIG. 12is a cross-sectional view taken along line I-I′ ofFIG. 1, illustrating a final step of a method of forming a semiconductor cell structure. Referring toFIG. 12, according to example embodiments, plugs134may be formed in the through holes129ofFIGS. 6,8,10and11. In the through holes129ofFIGS. 6 and 8, the plugs134may be partially surrounded by the fourth insulating layer90. In the through holes129ofFIGS. 6 and 8, the plugs134may not be surrounded by the fourth insulating layer90. The plugs134may be formed to expose a top surface of the fifth or sixth insulating layer100or110and to fill the through holes129.

The plugs134may be molded in the fourth and fifth insulating layers90and100or fourth to sixth insulating layers90to110depending on the shape of the through holes129. The plugs134may include doped polysilicon, metal material, metal nitride or stacked materials thereof. The plugs134may have a desired contact resistance with respect to the connection patterns85through the through holes129compared with the conventional art.

The plugs134may have a smaller internal resistance through the through holes129compared with a conventional art. The plugs134may be electrically insulated from the conductive patterns55through the lower insulating layer compared with the conventional art. As a result, the plugs134together with the first patterns15, the landing pads25, the second patterns70and the connection patterns85may constitute the semiconductor cell structure140according to example embodiments. As a variation of the example embodiments, the semiconductor cell structure140may not have the first patterns15, the first insulating layer20and the landing pads25.

FIG. 13is a cross-sectional view taken along line I-I′ ofFIG. 1, illustrating a final step of a method of forming a semiconductor cell structure. Referring toFIG. 13, according to example embodiments, an electrical node layer and a sacrificial layer (not shown) may be sequentially formed in the through holes129ofFIG. 6,8,10or11. In the through holes129ofFIGS. 6 and 8, the electrical node layer may be partially surrounded by the fourth insulating layer90. The electrical node layer may be formed on the sixth insulating layer110to conformally cover the through holes129of the fourth to sixth insulating layers90to110ofFIG. 6.

The electrical node layer may be formed on the fifth insulating layer100to conformally cover the through holes129of the fourth and fifth insulating layers90and100ofFIG. 8. In the through holes129ofFIGS. 10 and 11, the electrical node layer may not be surrounded by the fourth insulating layer90. The electrical node layer may be formed on the sixth insulating layer110to conformally cover the through holes129of the fifth and sixth insulating layers100and110ofFIG. 10. The electrical node layer may be formed on the fifth insulating layer100to conformally cover the through holes129of the fifth insulating layer100ofFIG. 11. The electrical node layer may include doped polysilicon, metal material, metal nitride or stacked materials thereof.

The sacrificial layer may be formed on the electrical layer to fill the through holes129. The electrical node layer and the sacrificial layer may be etched to expose a top surface of the fifth insulating layer100or the sixth insulating layer110to form electrical nodes138and sacrificially molded patterns. Subsequently, the fifth and sixth insulating layers100and110ofFIG. 6, and the sacrificially molded patterns may be removed from the electrical nodes138. Lower parts of the electrical nodes138may be surrounded by the fourth insulating layer90ofFIG. 6.

The fifth insulating layer100ofFIG. 8and the sacrificially molded patterns may be removed from the electrical nodes138. The lower parts of the electrical nodes138may be surrounded by the fourth insulating layer90ofFIG. 8. The fifth and sixth insulating layers100and110ofFIG. 10, and sacrificially molded patterns may be removed from the electrical nodes138. Sidewalls of the electrical nodes138may be exposed on the connection patterns85as a whole. The fifth insulating layer100ofFIG. 11and the sacrificially molded patterns may be removed from the electrical nodes138. The sidewalls of the electrical nodes138may be exposed on the connection patterns85as a whole.

The electrical nodes138may include a lower electrode of a capacitor. The electrical nodes138may have a desired contact resistance with respect to the connection patterns85through the through holes129compared with the conventional art. The electrical nodes138may have a smaller internal resistance through the through holes129compared with a conventional art. The electrical nodes138may be electrically insulated from the conductive patterns55through the lower insulating layer compared with the conventional art.

The electrical nodes138together with the first patterns15, the landing pads25, the second patterns70and the connection patterns85may constitute the semiconductor cell structure140according to example embodiments. As a variation of the example embodiments, the semiconductor cell structure140may not have the first patterns15, the first insulating layer20and the landing pads25.

A method of forming a semiconductor module and a method of forming a processor-based system according to example embodiments will be described below.FIG. 14is a plan view illustrating a method of forming a semiconductor module160according to example embodiments.

Referring toFIG. 14, according to example embodiments, a module substrate150may be prepared. The module substrate150may include a printed circuit board. The module substrate150may include internal circuits (not shown), electric pads (not shown) and connectors159. The internal circuits may be electrically connected to the electric pads and the connectors159. Semiconductor package structures148and at least one resistor153may be formed on the module substrate150.

The semiconductor package structures148, at least one resistor153and at least one condenser156may be formed on the module substrate150. The semiconductor package structures148, at least one resistor153and at least one condenser156may be electrically connected to the electric pads. Each of the semiconductor package structures148may include at least one semiconductor device144. The semiconductor device144may have a cell array region and a peripheral circuit region.

The cell array region may have the active regions9ofFIG. 1repeatedly and periodically along columns and rows of the semiconductor substrate3ofFIG. 2. Therefore, the first pattern15, the landing pad30, the second connection hole80and the through hole129together with the active region9may be arranged in the cell array region repeatedly and periodically. As a result, the cell array region may have the plurality of semiconductor cell structures ofFIG. 12or13. The peripheral circuit region may surround the cell array region.

The peripheral circuit region may have peripheral circuits to be electrically connected to the cell array region. The peripheral circuits may have semiconductor peripheral structures having a different shape from the semiconductor cell structure140ofFIG. 12or13. A part of the peripheral circuits may have the semiconductor cell structure140ofFIG. 12. Meanwhile, the semiconductor package structures148and at least one resistor153may constitute a semiconductor module160together with the module substrate150.

The semiconductor package structures148, at least one resistor153and at least one condenser156may constitute the semiconductor module160together with the module substrate150. The semiconductor module160may have improved electrical characteristics compared with the conventional art. The semiconductor module160may be electrically connected to the processor-based system190ofFIG. 15through the connectors159of the module substrate150.

FIG. 15is a plan view illustrating a method of forming a processor-based system according to example embodiments. Referring toFIG. 15, according to example embodiments, at least one system board (not shown) may be prepared. The at least one system board may have at least one bus line178. A first module unit may be formed on the at least one bus line178. The first module unit may be electrically connected to at least one bus line178. The first module unit may include a central processing unit (CPU)172, a floppy disk drive174and a compact disk ROM drive176.

Further, a second module device may be formed on the at least one bus line178. The second module device may be electrically connected to at least one bus line178. The second module device may include a first I/O device182, a second I/O device184, a read-only memory (ROM)186and a random access memory (RAM)188.

The RAM188may include the semiconductor cell structure140ofFIG. 13or14. The ROM186may include the semiconductor cell structure140ofFIG. 13. The first and second module units may constitute the processor-based system190according to example embodiments. The processor-based system190may have improved electrical characteristics compared with the conventional art. The processor-based system190may include a computer system, a process control system or other systems.

As described above, in example embodiments, a method of forming a semiconductor cell structure capable of stably forming a larger through hole in an upper insulating layer without exposing a conductive pattern in a lower insulating layer can be provided. For this purpose, the semiconductor cell structure can have different insulating materials with respect to an etching rate in insulating layers surrounding a lower portion of the through hole, and disposed below the through hole.

Also, example embodiments provide a method of forming a semiconductor device and a method of forming a semiconductor module, which are performed to be capable of improving electrical characteristics by using a semiconductor cell structure. For this purpose, the upper insulating layer can be etched using dry etchants or wet etchants having an etch selectivity with respect to the lower and upper insulating layers to have a through hole in the upper insulating layer without causing etch damage to the lower insulating layer, so that leakage current flows through the through hole can be minimized or reduced. The semiconductor device may include a volatile or non-volatile memory device.