Semiconductor light emitting device

According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a p-side electrode, an n-side electrode, an inorganic insulating film, a p-side interconnection portion, an n-side interconnection portion, and an organic insulating film. The organic insulating film is provided on the inorganic insulating film, at least on a portion between the p-side interconnection portion and the n-side interconnection portion. An end portion of the p-side interconnection portion on the n-side interconnection portion side and an end portion of the n-side interconnection portion on the p-side interconnection portion side override the organic insulating film.

FIELD

Embodiments described herein relate generally to a semiconductor light emitting device.

BACKGROUND

In general, a semiconductor light emitting device can provide high brightness by injection of high current. However, injection of high current produces the problem of the decrease of light emission efficiency due to such causes as the temperature increase of the light emitting layer and even the light emitting device itself.

DETAILED DESCRIPTION

According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a p-side electrode, an n-side electrode, an inorganic insulating film, a p-side interconnection portion, an n-side interconnection portion, and an organic insulating film. The semiconductor layer includes a first surface, a second surface opposite to the first surface, and a light emitting layer. The p-side electrode is provided on a region including the light emitting layer on the second surface. The n-side electrode is provided on a region not including the light emitting layer on the second surface. The inorganic insulating film is provided on the second surface side. The inorganic insulating film includes a first via penetrated to the p-side electrode and a second via penetrated to the n-side electrode. The p-side interconnection portion is provided on the inorganic insulating film. The p-side interconnection portion is electrically connected to the p-side electrode through the first via. The n-side interconnection portion is provided on the inorganic insulating film. The n-side interconnection portion is spaced from the p-side interconnection portion. The n-side interconnection portion is electrically connected to the n-side electrode through the second via. The organic insulating film is provided on the inorganic insulating film, at least on a portion between the p-side interconnection portion and the n-side interconnection portion. An end portion of the p-side interconnection portion on the n-side interconnection portion side and an end portion of the n-side interconnection portion on the p-side interconnection portion side override the organic insulating film.

Embodiments will now be described with reference to the drawings. In the drawings, like elements are labeled with like reference numerals.

First Embodiment

FIG. 1Ais a schematic sectional view of a semiconductor light emitting device10of a first embodiment.FIG. 1Bis a schematic diagram of an equivalent circuit superimposed on the cross-sectional structure ofFIG. 1A.

The semiconductor light emitting device10includes a semiconductor layer15. The semiconductor layer15includes a first surface15aand a second surface formed on the opposite side (upper side inFIG. 1A) to the first surface15a. The electrodes and the interconnection layers described later are provided on the second surface side. Light is emitted outside primarily from the first surface15aopposite to the second surface.

The semiconductor layer15includes a first semiconductor layer11and a second semiconductor layer12. The first semiconductor layer11and the second semiconductor layer12are made of a material including e.g. gallium nitride.

The first semiconductor layer11includes e.g. an underlying buffer layer and an n-type layer. The n-type layer functions as a lateral current path. The second semiconductor layer12has a stacked structure in which a light emitting layer (active layer)13is sandwiched between the n-type layer and a p-type layer.

As described later, the semiconductor layer15is formed on a substrate5. In this embodiment, the substrate5is left intact. That is, the substrate5is provided on the first surface15a, which is the main extraction surface of light in the semiconductor layer15. The substrate5is thicker than the semiconductor layer15and provides mechanical strength to the semiconductor light emitting device10.

The substrate5is a transparent body being transparent to the emission light from the light emitting layer13. For instance, the substrate5can be a sapphire substrate. The substrate5has a refractive index between gallium nitride used for the semiconductor layer15and air. This prevents the refractive index of the medium from changing greatly in the direction of light extraction through the first surface15a. Thus, the light extraction efficiency can be increased.

The second surface side of the semiconductor layer15is processed in a protrusion-depression configuration. The protrusion formed on the second surface side includes the light emitting layer13. A p-side electrode16is provided on the surface of the second semiconductor layer12constituting the surface of the protrusion. That is, the p-side electrode16is provided on a region including the light emitting layer13.

A region lacking the second semiconductor layer12including the light emitting layer13is provided beside the protrusion on the second surface side of the semiconductor layer15. An n-side electrode17is provided on the surface of the first semiconductor layer11in that region. That is, the n-side electrode17is provided on the region not including the light emitting layer13.

On the second surface side of the semiconductor layer15, the area of the second semiconductor layer12including the light emitting layer13is larger than the area of the first semiconductor layer11not including the light emitting layer13. Furthermore, the p-side electrode16provided on the region including the light emitting layer13has a larger area than the n-side electrode17provided on the region not including the light emitting layer13. Thus, a large light emitting region is realized.

An insulating film14is provided on the side surface of the second semiconductor layer12including the light emitting layer13, the side surface of the p-side electrode16, and the side surface of the n-side electrode17. The insulating film14covers the side surface of the second semiconductor layer12, the side surface of the p-side electrode16, and the side surface of the n-side electrode17. The insulating film14is an inorganic insulating film such as a silicon oxide film and silicon nitride film. The surface of the p-side electrode16and the surface of the n-side electrode17are exposed from the insulating film14.

An inorganic insulating film18is provided on the insulating film14, the p-side electrode16, and the n-side electrode17. The inorganic insulating film18is e.g. a silicon oxide film or silicon nitride film. The inorganic insulating film18covers the side surface of the insulating film14and the side surface of the first semiconductor layer11.

Furthermore, the inorganic insulating film18covers part of the surface of the p-side electrode16and part of the surface of the n-side electrode17. In the inorganic insulating film18, a first via18apenetrated to the p-side electrode16and a second via18bpenetrated to the n-side electrode17are formed.

An organic insulating film20is selectively formed on the inorganic insulating film18. The organic insulating film20is made of e.g. a resin such as polyimide. The organic insulating film20covers the side surface of the inorganic insulating film18and constitutes the outer surface of the semiconductor light emitting device10in conjunction with the substrate5.

A first p-side interconnection layer21is provided in the first via18aand on the inorganic insulating film18and the organic insulating film20around the first via18a. A metal film19is provided below the first p-side interconnection layer21. The first p-side interconnection layer21is electrically connected to the p-side electrode16through the metal film19provided in the first via18a. A p-side interconnection portion of the embodiment includes the first p-side interconnection layer21and the metal film19below the first p-side interconnection layer21. The metal film19is much thinner than the first p-side interconnection layer21.

A first n-side interconnection layer22is provided in the second via18band on the inorganic insulating film18and the organic insulating film20around the second via18b. A metal film19is provided below the first n-side interconnection layer22. The first n-side interconnection layer22is electrically connected to the n-side electrode17through the metal film19provided in the second via18b. An n-side interconnection portion of the embodiment includes the first n-side interconnection layer22and the metal film19below the first n-side interconnection layer22. The metal film19is much thinner than the first n-side interconnection layer22.

The organic insulating film20is provided on the inorganic insulating film18between the p-side interconnection portion and the n-side interconnection portion. A step is formed between the organic insulating film20and the inorganic insulating film18. The first p-side interconnection layer21is provided via the metal film19so as to cover the step. That is, the end portion21bof the first p-side interconnection layer21on the first n-side interconnection layer22side overrides the organic insulating film20.

Also on the opposite side of the first p-side interconnection layer21from the end portion21b, a step is formed between the organic insulating film20and the inorganic insulating film18. The first n-side interconnection layer22is provided via the metal film19so as to cover the step. That is, the end portion22bof the first n-side interconnection layer22on the first p-side interconnection layer21side overrides the organic insulating film20.

The step between the organic insulating film20and the inorganic insulating film18is provided between the p-side electrode16and the n-side electrode17. However, on the outside of the p-side electrode16(the left side of the first p-side interconnection layer21inFIG. 1A) and the outside of the n-side electrode17(the right side of the first n-side interconnection layer22inFIG. 1A), no step is provided between the organic insulating film20and the inorganic insulating film18.

The end portion21band the end portion22boverriding the organic insulating film20are spaced by a gap from each other.

In the first p-side interconnection layer21, the portion between the end portion21band the portion in the first via18ais provided on the inorganic insulating film18via the metal film19. In the first n-side interconnection layer22, the portion between the end portion22band the portion in the second via18bis provided on the inorganic insulating film18via the metal film19.

In the first p-side interconnection layer21, the other end portion different from the end portion21bon the first n-side interconnection layer22side is provided on the inorganic insulating film18via the organic insulating film20and the metal film19. That is, the organic insulating film20is provided also below the other end portion of the first p-side interconnection layer21different from the end portion21b.

In the first n-side interconnection layer22, the other end portion different from the end portion22bon the first p-side interconnection layer21side is provided on the inorganic insulating film18via the organic insulating film20and the metal film19. That is, the organic insulating film20is provided also below the other end portion of the first n-side interconnection layer22different from the end portion22b.

The first n-side interconnection layer22extends out toward the first p-side interconnection layer21. That is, part of the first n-side interconnection layer22overlaps the inorganic insulating film18on the light emitting region including the light emitting layer13.

Hence, as shown in the equivalent circuit ofFIG. 1B, a capacitor C is formed in parallel to the pn junction in the semiconductor layer15. The inorganic insulating film18functioning as a dielectric film in the capacitor C can be formed by e.g. the sputtering or chemical vapor deposition (CVD) process. Thus, the inorganic insulating film18can be made thinner than an organic film formed by e.g. the coating process. The thin inorganic insulating film18increases the capacitance of the capacitor C. This is advantageous to the improvement in the electrostatic discharge (ESD) resistance of the semiconductor light emitting device10.

The area of the first n-side interconnection layer22is larger than the area of the n-side electrode17. Furthermore, the area of the first n-side interconnection layer22spread on the inorganic insulating film18is larger than the area of the first n-side interconnection layer22connected to the n-side electrode17through the second via18bby the metal film19.

Because the light emitting layer13is formed over a larger region than the n-side electrode17, high optical output can be achieved. The n-side electrode17is provided on a region smaller than the light emitting region and not including the light emitting layer13. However, this embodiment can realize a structure in which the first n-side interconnection layer22having a larger area than the n-side electrode17is arranged on the mounting surface side.

The area of the first p-side interconnection layer21connected to the p-side electrode16through the first via18ais larger than the area of the first n-side interconnection layer22connected to the n-side electrode17through the second via18b. This improves the distribution of current to the light emitting layer13, and can also improve the dissipation of heat generated in the light emitting layer13. Here, the first p-side interconnection layer21may be connected to the p-side electrode16through a plurality of first vias18a.

The first semiconductor layer11is electrically connected to the first n-side interconnection layer22through the n-side electrode17and the metal film19. The second semiconductor layer12including the light emitting layer13is electrically connected to the first p-side interconnection layer21through the p-side electrode16and the metal film19.

The surface of the first p-side interconnection layer21opposite to the semiconductor layer15functions as a p-side external terminal21a. The surface of the first n-side interconnection layer22opposite to the semiconductor layer15functions as an n-side external terminal22a.

FIG. 2shows the state of the semiconductor light emitting device10of the embodiment mounted on a mounting substrate100. InFIG. 2, the semiconductor light emitting device10is shown upside down with respect toFIG. 1A.

The p-side external terminal21aand the n-side external terminal22aare bonded with e.g. solder102to pads101formed on the surface of the mounting substrate100. The mounting substrate100is e.g. a resin substrate or ceramic substrate. Here, instead of the solder102, other metals may be used as a bonding material.

By injection of current into the light emitting layer13, the light emitting layer13emits light, and generates heat. The dissipation of the heat toward the mounting substrate100primarily includes the following paths. One is the path in which the heat of the light emitting layer13is released through the p-side electrode16and the first via18ato the first p-side interconnection layer21. Furthermore, in the portion of the first p-side interconnection layer21overlapping the p-side electrode16across the inorganic insulating film18, the heat of the light emitting layer13can be released through the p-side electrode16and the inorganic insulating film18to the first p-side interconnection layer21. Furthermore, in the portion of the first n-side interconnection layer22overlapping the p-side electrode16across the inorganic insulating film18, the heat of the light emitting layer13can be released through the p-side electrode16and the inorganic insulating film18to the first n-side interconnection layer22.

The heat transferred to the first p-side interconnection layer21and the first n-side interconnection layer22is dissipated through the solder102and the pads101to the mounting substrate100.

In this embodiment, an inorganic insulating film18is used as the insulating film provided between the electrode16,17and the interconnection layer21,22. Inorganic materials have higher thermal conductivity than organic materials (resin materials). Thus, heat dissipation through the inorganic insulating film18to the interconnection layers21,22can be increased. The semiconductor light emitting device having good heat dissipation can suppress the degradation of electrical characteristics and the decrease of light emission efficiency at the time of high current injection into the light emitting layer13. As a result, high brightness can be achieved.

FIG. 9is a schematic sectional view of a semiconductor light emitting device of a comparative example.

The semiconductor light emitting device of the comparative example does not include the organic insulating film20of this embodiment. That is, the first p-side interconnection layer21and the first n-side interconnection layer22are formed on the inorganic insulating film18via the metal film19. The end portion of the first p-side interconnection layer21and the end portion of the first n-side interconnection layer22are also formed on the inorganic insulating film18. Also in this structure, heat of the light emitting layer can be released through the p-side electrode16and the inorganic insulating film18to the first p-side interconnection layer21and the first n-side interconnection layer22.

The inorganic insulating film18has higher thermal conductivity than the organic insulating film. However, the inorganic insulating film18tends to be more brittle and fragile. Furthermore, in the state of the semiconductor light emitting device mounted on the mounting substrate100, a problem arises with the difference in thermal expansion coefficient between the semiconductor layer15and the mounting substrate100. This difference in thermal expansion coefficient generates a stress such that the first p-side interconnection layer21and the first n-side interconnection layer22constrained to the mounting substrate100by the solder102and the pads101are distanced from each other. By this stress, cracks as shown inFIG. 9are likely to occur in the inorganic insulating film18near the end portion of the first p-side interconnection layer21and near the end portion of the first n-side interconnection layer22. The cracks may cause unintentional short circuit between the components.

In contrast, in this embodiment, the end portion21bof the first p-side interconnection layer21on the first n-side interconnection layer22side and the end portion22bof the first n-side interconnection layer22on the first p-side interconnection layer21side are provided on the organic insulating film20softer than the inorganic insulating film18. Thus, the organic insulating film20relaxes the stress near the end portion21band the end portion22b, where the aforementioned stress is more likely to concentrate. This prevents cracks in the inorganic insulating film18and achieves high reliability.

Furthermore, the other end portion of the first p-side interconnection layer21different from the aforementioned end portion21band the other end portion of the first n-side interconnection layer22different from the aforementioned end portion22bare also provided on the organic insulating film20. Thus, the organic insulating film20relaxes the stress near these end portions and achieves higher reliability.

That is, in this embodiment, high current injection is enabled by using high heat dissipation of the inorganic insulating film18. Furthermore, the organic insulating film20softer than the inorganic insulating film18is provided on the portion where the stress is more likely to concentrate. Thus, high reliability is achieved.

Next, a method for manufacturing the semiconductor light emitting device10of the embodiment is described with reference toFIGS. 3A to 5C. In the figures showing the manufacturing process, part of a wafer including a plurality of semiconductor layers15(chips) is shown.

FIG. 3Ashows a stacked body in which a first semiconductor layer11and a second semiconductor layer12are formed on the major surface of a substrate5. The first semiconductor layer11is formed on the major surface of the substrate5, and the second semiconductor layer12including a light emitting layer13is formed on the first semiconductor layer11. The first semiconductor layer11and the second semiconductor layer12including e.g. gallium nitride can be crystal grown on e.g. a sapphire substrate by the metal organic chemical vapor deposition (MOCVD) process.

The first semiconductor layer11includes an underlying buffer layer and an n-type GaN layer. The second semiconductor layer12includes a light emitting layer (active layer)13and a p-type GaN layer. The light emitting layer13can emit e.g. blue, violet, blue-violet, or ultraviolet light. The surface of the first semiconductor layer11in contact with the substrate5constitutes a first surface15aof the semiconductor layer15.

After forming the semiconductor layer15on the substrate5, part of the second semiconductor layer12is removed by e.g. the reactive ion etching (RIE) process using a resist, not shown. Thus, part of the first semiconductor layer11is exposed. The region where the first semiconductor layer11is exposed does not include the light emitting layer13.

Next, as shown inFIG. 3B, a p-side electrode16is formed on the surface of the second semiconductor layer12, and an n-side electrode17is formed on the surface of the first semiconductor layer11. The p-side electrode16and the n-side electrode17are formed by e.g. the sputtering or evaporation process. Either the p-side electrode16or the n-side electrode17may be formed previously, or they may be formed simultaneously from the same material. Activation annealing for forming ohmic contact between each electrode16, and the semiconductor layer11,12is performed as necessary.

An insulating film14is formed on the exposed portion except the surface of the p-side electrode16and the surface of the n-side electrode17. The insulating film14is e.g. a silicon oxide film or silicon nitride film. The insulating film14is provided between the p-side electrode16and the n-side electrode17for insulation between these electrodes. Furthermore, the insulating film14covers and protects the side surface of the second semiconductor layer12including the light emitting layer13.

Next, as shown inFIG. 3C, the insulating film14and the first semiconductor layer11are selectively removed by e.g. the RIE process using a resist51as a mask. Thus, a trench52reaching the substrate5is formed. The trench52is formed in e.g. a lattice-like planar layout on the substrate5in the wafer state. The trench52divides the semiconductor layer15into a plurality of chips.

Here, the step of dividing the semiconductor layer15into a plurality may be performed in the step shown inFIG. 3Abefore forming the electrodes16,17.

Next, after removing the resist51, the entire exposed portion on the substrate5is covered with an inorganic insulating film18as shown inFIG. 4A. That is, the inorganic insulating film18is provided on the p-side electrode16and on the n-side electrode17. Furthermore, the inorganic insulating film18is provided on the inner wall of the trench52and covers the side surface of the first semiconductor layer11.

Next, as shown inFIG. 4B, a first via18aand a second via18bare formed in the inorganic insulating film18by etching using a resist53as a mask. The first via18areaches the p-side electrode16. The second via18breaches the n-side electrode17. Furthermore, the inorganic insulating film18at the bottom of the trench52is removed.

Next, after removing the resist53, as shown inFIG. 4C, an organic insulating film20is selectively formed on the inorganic insulating film18. The organic insulating film20is made of e.g. a photosensitive resin such as polyimide. After forming the organic insulating film20on the entire surface of the inorganic insulating film18, the organic insulating film20is patterned by exposure and development using a mask, not shown. The organic insulating film20is formed also on the sidewall of the inorganic insulating film18in the trench52.

Next, on the exposed portion on the substrate5, a metal film19is formed as shown inFIG. 5A. The metal film19is used as a seed metal for the plating described below. The metal film19is formed also on the surface of the p-side electrode16exposed at the bottom of the first via18aand the surface of the n-side electrode17exposed at the bottom of the second via18b.

The metal film19is formed by e.g. the sputtering process. The metal film19includes e.g. a stacked film of titanium (Ti) and copper (Cu) formed sequentially from bottom.

Next, as shown inFIG. 5B, a resist54is selectively formed on the metal film19, and Cu electrolytic plating is performed with the metal film19used as a current path. Thus, a first p-side interconnection layer21and a first n-side interconnection layer22are selectively formed on the metal film19. The first p-side interconnection layer21and the first n-side interconnection layer22are made of e.g. a copper material formed simultaneously by the plating process.

The first p-side interconnection layer21is formed also in the first via18aand electrically connected to the p-side electrode16through the metal film19. The first n-side interconnection layer22is formed also in the second via18band electrically connected to the n-side electrode17through the metal film19.

The organic insulating film20is formed on the inorganic insulating film18between the first via18aand the second via18b. A step is formed between the organic insulating film20and the inorganic insulating film18. The step is covered with the metal film19functioning as a seed metal. Thus, the plating metal is deposited so as to cover the aforementioned step.

Hence, the end portion21bof the first p-side interconnection layer21on the first n-side interconnection layer22side is provided on the organic insulating film20. The end portion22bof the first n-side interconnection layer22on the first p-side interconnection layer21side is provided on the organic insulating film20.

After forming the first p-side interconnection layer21and the first n-side interconnection layer22, the resist54is removed. Subsequently, the exposed portion of the metal film19not covered with the first p-side interconnection layer21and the first n-side interconnection layer22is removed. Thus, the metal film19connected between the first p-side interconnection layer21and the first n-side interconnection layer22is divided.

Subsequently, the substrate5is cut at the position of the trench52and singulated into a plurality of semiconductor light emitting devices10. For instance, the substrate5is cut using a dicing blade. Alternatively, the substrate5may be cut by laser irradiation. Because the semiconductor layer15is not provided in the trench52, damage to the semiconductor layer15at the time of dicing can be avoided.

The singulated semiconductor light emitting device10may be of a single-chip structure including one semiconductor layer15, or may be of a multi-chip structure including a plurality of semiconductor layers15.

The aforementioned steps until dicing are collectively performed in the wafer state. Hence, there is no need to form interconnection layers and to perform protection with insulating films for each singulated device. This can significantly reduce the production cost. That is, in the singulated state, as shown inFIG. 1A, the side surface of the semiconductor layer15has already been covered and protected with the inorganic insulating film18and the organic insulating film20. As a result, the productivity can be improved, and the price reduction is facilitated.

Second Embodiment

FIG. 6is a schematic sectional view of a semiconductor light emitting device of a second embodiment.

In addition to the semiconductor light emitting device of the above first embodiment, the semiconductor light emitting device of this embodiment further includes a second p-side interconnection layer23, a second n-side interconnection layer24, and a resin layer25.

The second p-side interconnection layer23is provided on the first p-side interconnection layer21. In this embodiment, a p-side interconnection portion includes the metal film19, the first p-side interconnection layer21, and the second p-side interconnection layer23.

The second n-side interconnection layer24is provided on the first n-side interconnection layer22. In this embodiment, an n-side interconnection portion includes the metal film19, the first n-side interconnection layer22, and the second n-side interconnection layer24.

The space between the first p-side interconnection layer21and the first n-side interconnection layer22, and the space between the second p-side interconnection layer23and the second n-side interconnection layer24are filled with the resin layer25as an insulating material. The resin layer25covers each side surface of the first p-side interconnection layer21, the first n-side interconnection layer22, the second p-side interconnection layer23, and the second n-side interconnection layer24.

The surface of the second p-side interconnection layer23opposite to the first p-side interconnection layer21functions as a p-side external terminal23a. The surface of the second n-side interconnection layer24opposite to the first n-side interconnection layer22functions as an n-side external terminal24a.

The p-side external terminal23aand the n-side external terminal24aare exposed from the resin layer25. The p-side external terminal23aand the n-side external terminal24aare bonded with solder102to the aforementioned pads101formed on the mounting substrate100shown inFIG. 2.

The second p-side interconnection layer23is thicker than the first p-side interconnection layer21. The second n-side interconnection layer24is thicker than the first n-side interconnection layer22. The thickness of each of the second p-side interconnection layer23, the second n-side interconnection layer24, and the resin layer25is thicker than that of the semiconductor layer15. The term “thickness” used herein refers to the vertical thickness inFIG. 6.

The thickness of each of the second p-side interconnection layer23and the second n-side interconnection layer24is thicker than the thickness of the stacked body including of the semiconductor layer15, the p-side electrode16, and the n-side electrode17. Here, the aspect ratio (ratio of thickness to planar size) of the second p-side interconnection layer23and the second n-side interconnection layer24is not limited to being one or more, but the ratio may be less than one. That is, the thickness of the second p-side interconnection layer23and the second n-side interconnection layer24may be smaller than the planar size thereof.

The second p-side interconnection layer23, the second n-side interconnection layer24, and the resin layer25for reinforcing them function as a support body for the semiconductor layer15. Hence, even if the substrate5used for forming the semiconductor layer15is removed as described below, the support body including the second p-side interconnection layer23, the second n-side interconnection layer24, and the resin layer25can stably support the semiconductor layer15and increase the mechanical strength of the semiconductor light emitting device.

Furthermore, the second p-side interconnection layer23and the second n-side interconnection layer24shaped like pillars can absorb and relax the stress applied to the semiconductor layer15in the state of the semiconductor light emitting device mounted on a mounting substrate.

The material of the first p-side interconnection layer21, the first n-side interconnection layer22, the second p-side interconnection layer23, and the second n-side interconnection layer24can be copper, gold, nickel, or silver. Among them, copper can provide good thermal conductivity, high migration resistance, and superior adhesion to insulating materials.

The thermal expansion coefficient of the resin layer25may be equal or close to that of the mounting substrate100. Such a resin layer25can be made of e.g. epoxy resin, silicone resin, or fluororesin.

Furthermore, for instance, carbon black may be contained in the resin layer25so that the resin layer25can shield the emission light from the light emitting layer13. Furthermore, powder capable of reflecting the emission light from the light emitting layer13may be contained in the resin layer25.

Also in this embodiment, the end portion of the first p-side interconnection layer21and the end portion of the first n-side interconnection layer22are provided on the organic insulating film20softer than the inorganic insulating film18. Thus, the organic insulating film20can relax the aforementioned stress and prevent cracks in the inorganic insulating film18.

That is, also in this embodiment, high current injection is enabled by using high heat dissipation of the inorganic insulating film18. Simultaneously, the organic insulating film20softer than the inorganic insulating film18is provided on the portion where the stress is likely to concentrate. Thus, high reliability is achieved.

On the first surface15aof the semiconductor layer15, a phosphor layer27is provided as a transparent body being transparent to the emission light of the light emitting layer13. The phosphor layer27includes a transparent resin and phosphor particles dispersed in the transparent resin. The phosphor layer27can absorb the emission light from the light emitting layer13and emit wavelength converted light. Thus, the semiconductor light emitting device of this embodiment can emit mixed light of the light from the light emitting layer13and the wavelength converted light of the phosphor layer27.

The transparent resin in the phosphor layer27has a refractive index between the refractive index of the semiconductor layer15and the refractive index of air. This prevents the refractive index of the medium from changing greatly in the direction of light extraction through the first surface15aand the phosphor layer27. Thus, the light extraction efficiency can be increased.

For instance, the phosphor particles can be yellow phosphor particles emitting yellow light. Then, the blue light from the light emitting layer13made of GaN-based materials and the yellow light of the wavelength converted light of the phosphor layer27can be mixed to obtain white or light bulb color as a mixed color. Here, the phosphor layer27may be configured to include a plurality of kinds of phosphor particles (e.g., red phosphor particles emitting red light and green phosphor particles emitting green light).

The phosphor layer27is formed on the first surface15aafter the substrate5used for growing the semiconductor layer15is removed from the semiconductor layer15. By removing the substrate5from above the first surface15a, the profile of the semiconductor light emitting device can be made lower.

After forming the support body including the second p-side interconnection layer23, the second n-side interconnection layer24, and the resin layer25, the substrate5is removed by e.g. the laser lift-off process in the state of the semiconductor layer15supported by the support body.

Laser light is applied from the rear surface side of the substrate5toward the first semiconductor layer11. The laser light can be transmitted through the substrate5and has a wavelength in the absorption region for the first semiconductor layer11.

When the laser light reaches the interface between the substrate5and the first semiconductor layer11, the first semiconductor layer11near the interface is decomposed by absorbing the energy of the laser light. For instance, the first semiconductor layer11made of GaN-based materials is decomposed into gallium (Ga) and nitrogen gas. By this decomposition reaction, a fine gap is formed between the substrate5and the first semiconductor layer11. Thus, the substrate5and the first semiconductor layer11are separated. Irradiation with the laser light is performed a plurality of times for each specified region throughout the wafer to remove the substrate5.

The semiconductor layer15is supported by the support body thicker than the semiconductor layer15. Hence, even if the substrate5is eliminated, the wafer state can be maintained. Furthermore, both the resin layer25and the metal constituting the second p-side interconnection layer23and the second n-side interconnection layer24are made of softer materials than the semiconductor layer15. Hence, device destruction can be avoided even if the large internal stress generated in the epitaxial growth for forming the semiconductor layer15on the substrate5is released at once in removing the substrate5.

After removing the substrate5, the first surface15ais cleaned and, as necessary, subjected to frost treatment for forming protrusions and depressions. By forming fine protrusions and depressions at the first surface15a, the light extraction efficiency can be increased. Subsequently, the phosphor layer27is formed on the first surface15a. Furthermore, as necessary, a lens is formed on the first surface15aor on the phosphor layer27.

The step of forming the phosphor layer27includes the step of supplying a liquid transparent resin dispersed with phosphor particles onto the first surface15aby a method such as printing, potting, molding, and compression molding, and the step of heat curing it.

The sequence of steps until forming the phosphor layer27is performed in the wafer state. After forming the phosphor layer27, the wafer is cut from the resin layer25to the phosphor layer27at the position of the aforementioned trench52and singulated. At this time, the hard substrate5has already been removed. Hence, there is no need to cut the substrate5. This facilitates singulation.

Third Embodiment

FIG. 7is a schematic sectional view of a semiconductor light emitting device of a third embodiment.

The first p-side interconnection layer21and the first n-side interconnection layer22in this embodiment are provided on the inorganic insulating film18. The end portion of the first p-side interconnection layer21and the end portion of the first n-side interconnection layer22are also formed on the inorganic insulating film18. The organic insulating film20of the above embodiments is not interposed between the end portion of the first p-side interconnection layer21and the inorganic insulating film18, and between the end portion of the first n-side interconnection layer22and the inorganic insulating film18.

A second p-side interconnection layer23is provided on the surface of the first p-side interconnection layer21opposite from the inorganic insulating film18. In this embodiment, a p-side interconnection portion includes the metal film19, the first p-side interconnection layer21, and the second p-side interconnection layer23.

A second n-side interconnection layer24is provided on the surface of the first n-side interconnection layer22opposite from the inorganic insulating film18. In this embodiment, an n-side interconnection portion includes the metal film19, the first n-side interconnection layer22, and the second n-side interconnection layer24.

The planar size of the second p-side interconnection layer is smaller than the planar size of the first p-side interconnection layer21. A step is formed between the side surface of the first p-side interconnection layer21and the side surface of the second p-side interconnection layer23.

Likewise, the planar size of the second n-side interconnection layer24is smaller than the planar size of the first n-side interconnection layer22. A step is formed between the side surface of the first n-side interconnection layer22and the side surface of the second n-side interconnection layer24.

The space between the first p-side interconnection layer21and the first n-side interconnection layer22is not filled with an insulating material such as resin. The first p-side interconnection layer21and the first n-side interconnection layer22are spaced by a gap from each other. The space between the second p-side interconnection layer23and the second n-side interconnection layer24is also not filled with an insulating material such as resin. The second p-side interconnection layer23and the second n-side interconnection layer24are spaced by a gap from each other.

The surface of the second p-side interconnection layer23opposite to the first p-side interconnection layer21functions as a p-side external terminal23a. The surface of the second n-side interconnection layer24opposite to the first n-side interconnection layer22functions as an n-side external terminal24a. The p-side external terminal23aand the n-side external terminal24aexposed at the same surface are bonded with solder102to the pads101formed on the mounting substrate100.

The second p-side interconnection layer23is thicker than the first p-side interconnection layer21. The second n-side interconnection layer24is thicker than the first n-side interconnection layer22. The thickness of each of the second p-side interconnection layer23, the second n-side interconnection layer24, and the resin layer25is thicker than that of the semiconductor layer15.

The distance between the p-side external terminal23aand the n-side external terminal24ais larger than the distance between the first p-side interconnection layer21and the first n-side interconnection layer22on the inorganic insulating film18. That is, the p-side external terminal23aand the n-side external terminal24aare separated by such a distance as to prevent short circuit between the p-side external terminal23aand the n-side external terminal24awith solder102when mounted onto the mounting substrate100.

The first p-side interconnection layer21not functioning as an external terminal can be made close to the first n-side interconnection layer22up to the process limit. Thus, the area of the first p-side interconnection layer21can be enlarged. As a result, the distribution of current to the light emitting layer13and the heat dissipation can be improved.

The planar size of the second p-side interconnection layer23is made smaller than the planar size of the first p-side interconnection layer21. Thus, a step is formed from the side surface of the first p-side interconnection layer21to the side surface of the second p-side interconnection layer23. That is, the p-side interconnection portion including the first p-side interconnection layer21and the second p-side interconnection layer23is slimmer on the mounting substrate100side.

Likewise, the planar size of the second n-side interconnection layer24is made smaller than the planar size of the first n-side interconnection layer22. Thus, a step is formed from the side surface of the first n-side interconnection layer22to the side surface of the second n-side interconnection layer24. That is, the n-side interconnection portion including the first n-side interconnection layer22and the second n-side interconnection layer24is slimmer on the mounting substrate100side.

Thus, the second p-side interconnection layer23and the second n-side interconnection layer24being slimmer absorb and relax the stress applied to the semiconductor light emitting device side in the state of the semiconductor light emitting device mounted on the mounting substrate. This can suppress stress concentration on the end portion of the first p-side interconnection layer21and the end portion of the first n-side interconnection layer22, and prevent cracks in the inorganic insulating film18near the end portions.

Hence, also in this embodiment, high current injection is enabled by using high heat dissipation of the inorganic insulating film18. Simultaneously, cracks in the inorganic insulating film18are prevented to achieve high reliability. Fourth embodiment

FIG. 8is a schematic sectional view of a semiconductor light emitting device of a fourth embodiment.

In this embodiment, as in the first embodiment, the end portion of the first p-side interconnection layer21and the end portion of the first n-side interconnection layer22are provided on the organic insulating film20softer than the inorganic insulating film18. Thus, the organic insulating film20can relax the aforementioned stress and prevent cracks in the inorganic insulating film18.

Furthermore, as in the third embodiment, the planar size of the second p-side interconnection layer23is made smaller than the planar size of the first p-side interconnection layer21.

Thus, a step is formed from the side surface of the first p-side interconnection layer21to the side surface of the second p-side interconnection layer23. That is, the p-side interconnection portion including the first p-side interconnection layer21and the second p-side interconnection layer23is slimmer on the mounting substrate100side.

Likewise, the planar size of the second n-side interconnection layer24is made smaller than the planar size of the first n-side interconnection layer22. Thus, a step is formed from the side surface of the first n-side interconnection layer22to the side surface of the second n-side interconnection layer24. That is, the n-side interconnection portion including the first n-side interconnection layer22and the second n-side interconnection layer24is slimmer on the mounting substrate100side.

Thus, the second p-side interconnection layer23and the second n-side interconnection layer24absorb and relax the stress applied to the semiconductor light emitting device side in the state of the semiconductor light emitting device mounted on the mounting substrate.

That is, also in this embodiment, high current injection is enabled by using high heat dissipation of the inorganic insulating film18. Simultaneously, local stress concentration on the inorganic insulating film18is prevented to achieve high reliability.

In the structures shown inFIGS. 7 and 8, the periphery of the first p-side interconnection layer21, the first n-side interconnection layer22, the second p-side interconnection layer23, and the second n-side interconnection layer24may be filled with a resin layer25as in the structure shown inFIG. 6. By thickening the second p-side interconnection layer23, the second n-side interconnection layer24, and the resin layer25, the thin semiconductor layer15can be stably supported without the substrate5.

In the structures shown inFIGS. 2,7, and8, a phosphor layer27may be provided on the substrate5.

The aforementioned phosphor layer can be a red phosphor layer, yellow phosphor layer, green phosphor layer, or blue phosphor layer illustrated below.

The red phosphor layer can contain e.g. nitride phosphor CaAlSiN3:Eu or SiAlON phosphor.

In the case of using SiAlON phosphor, the phosphor represented by the composition formula
(M1-x,Rx)a1AlSib1Oc1Nd1(1)
(M is at least one metallic element except Si and Al, and notably at least one of Ca and Sr. R is an emission center element, and notably Eu. The quantities x, a1, b1, c1, and d1satisfy the following relations: x is larger than 0 and 1 or less, a1is larger than 0.6 and less than 0.95, b1is larger than 2 and less than 3.9, c1is larger than 0.25 and less than 0.45, and d1is larger than 4 and less than 5.7) can be used.

By using the SiAlON phosphor represented by the composition formula (1), the temperature characteristics of wavelength conversion efficiency are improved. Thus, the efficacy in the high current density region can be further increased.

The yellow phosphor layer can contain e.g. silicate phosphor (Sr,Ca,Ba)2SiO4:Eu.

The green phosphor layer can contain e.g. halophosphate phosphor (Ba,Ca,Mg)10(PO4)6Cl2:Eu or SiAlON phosphor. In the case of using SiAlON phosphor, the phosphor represented by the composition formula
(M1-x,Rx)a2AlSib2Oc2Nd2(2)
(M is at least one metallic element except Si and Al, and notably at least one of Ca and Sr. R is an emission center element, and notably Eu. The quantities x, a2, b2, c2, and d2satisfy the following relations: x is larger than 0 and 1 or less, a2is larger than 0.93 and less than 1.3, b2is larger than 4.0 and less than 5.8, c2is larger than 0.6 and less than 1, and d2is larger than 6 and less than 11) can be used.

By using the SiAlON phosphor represented by the composition formula (2), the temperature characteristics of wavelength conversion efficiency are improved. Thus, the efficacy in the high current density region can be further increased.

The blue phosphor layer can contain e.g. oxide phosphor BaMgAl10O17:Eu.