Level converter circuit for use in CMOS circuit device provided for converting signal level of digital signal to higher level

A level converter circuit is provided for converting an input signal of a digital signal having a first signal level into an output signal having a second signal level higher than the first signal level. An amplifier circuit amplifies the input signal and outputs an amplified output signal, and a current generator circuit generates a control current corresponding to an operating current flowing through the amplifier circuit upon change of the signal level of the input signal. A current detector circuit detects the generated control current, and controls the operating current of the amplifier circuit to correspond to the detected control current. The current generator circuit includes series-connected first and second nMOS transistors as inserted between the current detector circuit and the ground. The first nMOS transistor operates responsive to the input signal, and the second nMOS transistor operates responsive to an inverted signal of the input signal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a level converter circuit for use in a CMOS circuit device, and in particular, to a level converter circuit that converts a signal level of a digital signal from a first voltage level to a second voltage level higher than the first voltage level.

2. Description of the Related Art

As the most effective technique for reducing the power consumption of LSIs, a reduction in the power supply voltage can be enumerated. In particular, a technique for supplying an optimal power supply voltage to each of circuit blocks is adopted for the recent LSIs, and therefore, it is sometimes the case where power supply voltages which are optimum for the circuit blocks differ from one another. Accordingly, a level converter circuit is needed between such circuits of different signal levels. Up to now, a variety of level converter circuits have been reported. The existing circuits generally have level converter circuits based on a latch structure. However, these level converter circuits have such a problem that the driving power of transistors driven by a low power supply voltage becomes extremely small when the difference voltages between the power supply voltages of the circuits are relatively large, and a stable level conversion operation is not guaranteed.

Prior art documents related to the present invention are as follows:

PATENT DOCUMENT

Non-Patent Document 1: S. Henzler, “Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies”, Springer, October 2006;Non-Patent Document 2: Y. Kanno et al., “Level converters with high immunity to power-supply bouncing for high-speed sub-1-V LSIs”, Digest of Technical Papers of 2000 Symposium on VLSI Circuits, pp. 202-203, June 2000;Non-Patent Document 3: I. J. Chang et al., “Robust level converter design for sub-threshold logic”, in Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), pp. 14-19, October 2006;Non-Patent Document 4: O-S. Kwon et al., “Fast-delay and low-power level shifter for low-voltage applications”, IEICE Transactions on Electronics, Volume E90-C, number 7, pp. 1540-1543, July. 2007;Non-Patent Document 5: H. Shao et al., “Low energy level converter design for sub-Vth logics”, in Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 107-108, January 2009;Non-Patent Document 6: Y.-S. Lin et al., “Single stage static level shifter design for subthreshold to I/O Voltage conversion”, in Proceeding of the 13th International Symposium on Low Power Electronics and Design (ISLPED), pp. 197-200, August 2008; andNon-Patent Document 7: F. Ishihara et al., “Level conversion for dual-supply systems”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 12, Issue 2, pp. 185-195, February 2004.

Up to now, the consumption power reductions of CMOS (Complementary Metal Oxide Semiconductor) semiconductor integrated circuits have been achieved by microfabrication of devices and by reduction of the power supply voltage accompanying to this. Since the power consumption of a digital circuit is expressed by the square of the power supply voltage, the reduction of the power supply voltage is an extremely effective technique for reduction of the consumption power. In the recent LSIs, a technique for supplying power supply voltages optimum for circuit blocks is adopted, and therefore, a design of varied power supply voltages for the circuit blocks is performed (See the Non-Patent Document 1). Therefore, a level converter circuit is needed between the circuits of different signal levels.

FIG. 1is a block diagram showing an application example of a prior art level converter circuit100. Referring toFIG. 1, the level converter circuit100converts the signal level of a signal from a low voltage circuit block200to which a low power supply voltage VDDL (e.g., 0.4 V) is supplied, and then, outputs the resulting signal to a high voltage circuit block300to which a high power supply voltage VDDH (e.g., 3 V) is supplied. An input signal IN inputted from the low voltage circuit block200to the level converter circuit100is a binary signal having a high level or a low level. The electrical potential of the high level is the low power supply voltage VDDL, and the electrical potential of the low level is the ground potential. Moreover, an output signal OUT outputted by the level converter circuit100to the high voltage circuit block300is a binary signal having the high level or the low level. The electrical potential of the high level is the high power supply voltage VDDH, and the electrical potential of the low level is the ground potential. Hereinafter, the voltage level of the low power supply voltage VDDL is referred to as a first high level, and the voltage level of the high power supply voltage VDDH is referred to as a second high level. Moreover, a voltage source having the low power supply voltage VDDL is referred to as a low voltage source, and a high voltage source having the high power supply voltage VDDH is referred to as a high voltage source.

Up to now, a variety of level converter circuits have been reported. A larger number of level converter circuits are each configured to include a latch circuit of cross-couple connected p-channel MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) (hereinafter referred to as pMOS transistors) and n-channel MOSFETs (hereinafter referred to as nMOS transistors). However, the nMOS transistors of these level converter circuits are to be driven by a low power supply voltage, and therefore, a circuit design considering driving powers between the pMOS transistors and the nMOS transistors becomes extremely important. In a level converter circuit based on a latch circuit, a positive feedback circuit is configured to include cross-couple connecting pMOS transistors. Therefore, a variety of improving measures, such as a technique for improving the driving power of the nMOS transistors by designing the channel width of the nMOS transistors large to invert the output signal, and a technique for reducing the driving power of the cross-couple connected pMOS transistors have been tried (See the Non-Patent Document 2 to 7 and the Patent Documents 1 to 3). However, when the difference voltage between the power supply voltages are increased as a consequence of the voltage reductions of the power supply voltages, it becomes difficult to guarantee stable level conversion operation by these designing techniques.

First of all, the cross-couple connection type level converter circuit of the prior art level converter circuit will be described, and the problems thereof will be described.

FIG. 2is a circuit diagram showing a configuration of a prior art cross-coupled level converter circuit100. The level converter circuit100is configured to include nMOS transistors (MN101, MN102), to the gates of which a signal IN and an input signal INB are inputted, respectively, and cross-couple connected pMOS transistors (MP101, MP102). In this case, the input signal IN and the input signal INB have a complementary relation. When the input signal IN becomes the first high level, the voltages of the input signal INB and the node N101become the low level. By this operation, the terminal T102is charged via the pMOS transistor MP102, and the level converter circuit100outputs an output signal OUT of the second high level. On the other hand, when the input signal IN becomes the low level, the input signal INB becomes the first high level. The nMOS transistor MN102discharges the terminal T102, and the level converter circuit100outputs an output signal OUT of the low level.

However, the prior art level converter circuit100has such a problem that the prior art level converter circuit100does not normally operate when there is a large difference between a current to charge the terminal T102and a current to discharge the terminal. This becomes especially significant when the difference voltage between power supply voltages (between the high power supply voltage VDDH and the low power supply voltage VDDL) becomes large. For example, when the input signal IN becomes the low level from the first high level, the nMOS transistor MN102is driven by the low power supply voltage VDDL of the low voltage source. In this case, when the current flowing through the pMOS transistor MP102becomes larger than the current flowing through the nMOS transistor MN102, then the logic value (signal level) of the output signal OUT is not inverted, and the second high level is maintained. That is, the output signal OUT remains the second high level regardless of the fact that the input signal IN is the low level, and the level converter circuit100does not normally operate.

In order to guarantee a stable operation in the prior art level converter circuit100, it is required to strike a balance between the amount of the current flowing through the nMOS transistor MN102and the amount of the current flowing through the pMOS transistor MP102. For this purpose, it is required to appropriately set the channel width and the threshold voltage of the nMOS transistor MN102and the pMOS transistor MP102. However, the amplitude of the voltage inputted to the gate of the pMOS transistor MP102has a wide range from the ground voltage to the high power supply voltage VDDH, while the amplitude of the voltage inputted to the gate of the nMOS transistor MN102has a narrow range from the ground voltage to the low power supply voltage VDDL. That is, when the voltage difference between the high power supply voltage VDDH and the low power supply voltage VDDL becomes relatively large, it becomes difficult for the prior art level converter circuit100to strike a balance between the amount of the current flowing through the nMOS transistor MN102and the amount of the current flowing through the pMOS transistor MP102. Further, when the amounts of the currents flowing through the nMOS transistor MN102and the pMOS transistor MP102change due to process variations and temperature changes, the level converter circuit100does not stably operate.

The level converter circuits for ameliorating these problems are proposed (See the Non-Patent Documents 2 to 7 and the Patent Documents 1 to 3). However, many of these level converter circuits, which have circuit configurations based on the cross-couple connection to easily strike a balance between the currents flowing through the nMOS transistor and the pMOS transistor, can not solve the aforementioned problems.

SUMMARY OF THE INVENTION

An object of the present invention is to solve the aforementioned problems and provide a level converter circuit that is able to stably operate even when the difference voltage of the power supply voltages between circuit blocks is relatively large and to operate with low power consumption as compared with the prior art.

In order to achieve the aforementioned objective, according to one aspect of the present invention, a level converter circuit is provided for converting an input signal that is a digital signal having a first signal level into an output signal having a second signal level higher than the first signal level. The level converter circuit includes an amplifier, a current generator circuit, and a current detector circuit. The amplifier circuit that amplifies the input signal and outputs an amplified output signal, and the current generator circuit generates a control current corresponding to an operating current flowing through the amplifier circuit when the signal level of the input signal changes. The current detector circuit that detects the control current generated by the current generator circuit, and controls the operating current of the amplifier circuit to correspond to the detected control current. The current generator circuit includes first and second nMOS transistors that are inserted between the current detector circuit and the ground, and connected in series, and the first nMOS transistor operates in response to the input signal, and the second nMOS transistor operates in response to an inverted signal of the input signal.

The above-mentioned level converter circuit preferably further includes a control circuit that changes a substrate potential of the first and second nMOS transistors so as to increase the control current to be larger than that of a conventional level converter circuit by lowering threshold voltages of the first and second nMOS transistors to be smaller than that of the conventional level converter circuit.

In addition, the above-mentioned level converter circuit preferably further includes a further nMOS transistor that is connected in parallel to each of the first and second nMOS transistors so that the control current is increased so as to be larger than that of a conventional level converter circuit.

Further, in the above-mentioned level converter circuit, the current generator circuit further includes at least one of a rise current generator circuit and a fall current generator circuit. The rise current generator circuit generates the control current for correction so that the output signal becomes a high level when the signal level of the input signal does not change, the input signal has the high level, and the output signal has a low level. The fall current generator circuit generates the control current for correction so that the output signal becomes the low level when the signal level of the input signal does not change, the input signal has the low level, and the output signal has the high level.

Still further, in the above-mentioned level converter circuit, the rise current generator circuit further includes a pMOS transistor, and fourth and fifth nMOS transistors. The pMOS transistor and a third nMOS transistor are inserted between a voltage source and the ground and connected in series via a predetermined node, and the fourth and fifth nMOS transistors are inserted between the current detector circuit and the ground and connected in series. The pMOS transistor operates in response to the output signal, the third nMOS transistor operates in response to the input signal, the fourth nMOS transistor operates in response to the input signal, and the fifth nMOS transistor operates in response to a signal level at the node.

In addition, in the above-mentioned level converter circuit, the fall current generator circuit includes sixth and seventh nMOS transistors that are inserted between the current detector circuit and the ground and connected in series. The sixth nMOS transistor operates in response to the inverted signal of the input signal, and the seventh nMOS transistor operates in response to the output signal.

Further, in the above-mentioned level converter circuit, the amplifier circuit includes a differential amplifier circuit and a source-grounded amplifier circuit.

Still further, in the above-mentioned level converter circuit, the source-grounded amplifier circuit is a push-pull type source-grounded amplifier circuit.

According to the level converter circuit of the present invention, the signal level is converted by applying the current corresponding to the current generated by the current generator circuit to the amplifier circuit. Therefore, even when the difference between the first signal level and the second signal level is large, the level converter circuit stably operates. Moreover, the current generator circuit generates the control current only when the signal level of the input signal changes and does not generate the control current when the signal level of the input signal does not change, and therefore, the level converter circuit operates with low power consumption.

In addition, according to the level converter circuit of the present invention, the control circuit that changes the substrate potential of the first and second nMOS transistors are further provided so that the control current is increased as compared with the conventional level converter circuit by lowering the threshold voltages of the first and second nMOS transistors as compared with the conventional level converter circuit. Therefore, the level converter circuit operates at higher speed than the conventional level converter circuit.

Further, according to the level converter circuit of the present invention, the other nMOS transistors are connected in parallel with the first and second nMOS transistors, respectively, so that the control current is increased as compared with conventional the level converter circuit. Therefore, the level converter circuit operates at higher speed than the conventional level converter circuit.

Still further, according to the level converter circuit of the present invention, the rise current generator circuit or the fall current generator circuit generate the control current even when there is no period or time interval during which both the input signal and the inverted signal of the input signal have the high level, and therefore, the level converter circuit normally operates. Further, the rise current generator circuit or the fall current generator circuit generates the control current even when the signal level of the output signal changes due to disturbances such as external noises, and therefore, the level converter circuit normally operates.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments according to the present invention will be described below with reference to the attached drawings.

First Preferred Embodiment

FIG. 3Ais a block diagram showing an application example of a level converter circuit1according to the first preferred embodiment of the present invention. Referring toFIG. 3A, the level converter circuit1converts the signal level of a signal from a low voltage circuit block200to which the low power supply voltage VDDL (e.g., 0.4 V) is supplied and outputs the resulting signal to a high voltage circuit block300to which the high power supply voltage VDDH (e.g., 3 V) is supplied. An input signal IN inputted from the low voltage circuit block200to the level converter circuit1is a binary signal having the high level or the low level. The electrical potential of the high level is the low power supply voltage VDDL, and the electrical potential of the low level is the ground potential. The output signal OUT outputted to the high voltage circuit block300by the level converter circuit1is a binary signal having the high level or the low level. The electrical potential of the high level is the high power supply voltage VDDH, and the electrical potential of the low level is the ground potential. The voltage level of the low power supply voltage VDDL is hereinafter referred to as a first high level, and the voltage level of the high power supply voltage VDDH is referred to as a second high level. Moreover, a voltage source having the low power supply voltage VDDL is referred to as a low voltage source, and a voltage source having the high power supply voltage VDDH is referred to as a high voltage source.

FIG. 3Bis a block diagram showing a configuration of the level converter circuit1of the first preferred embodiment of the present invention. Referring toFIG. 3B, the level converter circuit1is configured to include a current generator circuit10, a current detector circuit20, a differential amplifier circuit30, a source-grounded amplifier circuit40, a preprocessing circuit50, and terminals T1and T2.

The level converter circuit1of the first preferred embodiment converts the input signal IN of a digital signal having the first high level into the output signal OUT having the second high level higher than the first high level, and the level converter circuit1is characterized in that the level converter circuit1includes the following:

(a) the differential amplifier circuit30and the source-grounded amplifier circuit40for amplifying the input signal IN and outputting the output signal OUT;

(b) the current generator circuit10for generating a control current IA1corresponding to operating currents IA2and IA3flowing through the differential amplifier circuit30and the source-grounded amplifier circuit40, respectively, when the voltage of the input signal IN changes; and

(c) the current detector circuit20for detecting the control current IA1generated by the current generator circuit10and controlling each of the operating currents IA2and IA3of the differential amplifier circuit30and the source-grounded amplifier circuit40so as to corresponds to the control current IA1, and

(d) the current generator circuit10has nMOS transistors MN11and MN12that are inserted between the current detector circuit20and the ground and connected in series and,

(e) the nMOS transistor MN11operates in response to the input signal IN, and the nMOS transistor MN12operates in response to the inverted signal INB of the input signal IN.

The preprocessing circuit50is configured to include a pMOS transistor MP51and an nMOS transistor MN51. The source of the pMOS transistor MP51is connected to a low voltage source. The gate of the pMOS transistor MP51and the gate of the nMOS transistor MN51are connected to a terminal T1, and the input signal IN from the low voltage circuit block200is inputted to its gate. The drain of the pMOS transistor MP51is connected to the drain of the nMOS transistor MN51. The source of the nMOS transistor MN51is grounded. The pMOS transistor MP51and the nMOS transistor MN51are connected in series to constitute an inverter, and the inverter outputs a signal INB (hereinafter referred to as an input signal INB) obtained by inverting the input signal IN to the current generator circuit10and the differential amplifier circuit30.

As described in detail later, the current generator circuit10is connected to the current detector circuit20, the preprocessing circuit50and the terminal T1, and the grounding part of the circuit is grounded.

The current detector circuit20is configured to include a pMOS transistor MP21. The source of the pMOS transistor MP21is connected to a high voltage source, and the gate of the pMOS transistor MP21is connected to the gate of a pMOS transistor MP31and the gate of a pMOS transistor MP41and also connected to the drain of the pMOS transistor MP21. The drain of the pMOS transistor MP21is connected to the current generator circuit10. The pMOS transistors MP21, MP31and MP41constitute a current mirror circuit.

The differential amplifier circuit30is configured to include pMOS transistors MP31, MP32and MP33, and nMOS transistors MN31and MN32. The source of the pMOS transistor MP31is connected to the high voltage source, and the drain of the pMOS transistor MP31is connected to the source of the pMOS transistor MP32and the source of the pMOS transistor MP33. The gate of the pMOS transistor MP32is connected to the preprocessing circuit50, and the input signal INB is inputted to its gate. The drain of the pMOS transistor MP32is connected to the drain of the nMOS transistor MN31. The gate of the pMOS transistor MP33is connected to the terminal T1, and the input signal IN is inputted to its gate. The drain of the pMOS transistor MP33is connected to the drain of the nMOS transistor MN32. The gate of the nMOS transistor MN31is connected to the drain of the nMOS transistor MN31and the gate of the nMOS transistor MN32. The source of the nMOS transistor MN31and the source of the nMOS transistor MN32are grounded.

The source-grounded amplifier circuit40is configured to include a pMOS transistor MP41and an nMOS transistor MN41. The source of the pMOS transistor MP41is connected to the high voltage source, and the drain of the pMOS transistor MP41is connected to the drain of the nMOS transistor MN41. The gate of the nMOS transistor MN41is connected to a connection point of the drain of the pMOS transistor MP33and the drain of the nMOS transistor MN32, and the source of the nMOS transistor MN41is grounded. A connection point of the drain of the pMOS transistor MP41and the drain of the nMOS transistor MN41is connected to a terminal T2. In this case, the differential amplifier circuit30and the source-grounded amplifier circuit40constitute a two-stage amplifier circuit.

In the level converter circuit1, the input signal IN is inputted to the gate of the pMOS transistor MP33, and the input signal INB is inputted to the gate of the pMOS transistor MP32. A feature of the level converter circuit1resides in the current generator circuit10that utilizes the input signal IN and the input signal INB. The current generator circuit10generates the current IA1(also referred to as a control current IA1) only when the signal level of the input signal IN changes. The current detector circuit20detects the current IA1and generates a control voltage Vctrl, then controls the current IA2(also referred to as an operating current IA2) flowing through the differential amplifier circuit30and the current IA3(also referred to as an operating current IA3) flowing through the source-grounded amplifier circuits40, via the current mirror circuit, so that they correspond to the current IA1. When the corresponding currents IA2and IA3are supplied, the differential amplifier circuit30and the source-grounded amplifier circuit40execute level conversion by amplifying the input signal IN of a small amplitude to the output signal OUT of a large amplitude and outputting the resulting signal. The operation of the level converter circuit1will be described in detail below.

The level converter circuit1is configured to include the two-stage amplifier circuit of the differential amplifier circuit30and the source-grounded amplifier circuit40, the current generator circuit10, the current detector circuit20and the preprocessing circuit50. A case where the currents IA2and IA3corresponding to the current IA1generated by the current generator circuit10are supplied to the differential amplifier circuit30and the source-grounded amplifier circuit40, respectively, is considered. When the voltage of the input signal IN is higher than the voltage of the input signal INB, the output signal OUT becomes the second high level. On the other hand, when the voltage of the input signal IN is lower than the voltage of the input signal INB, the output signal OUT become the low level. Since the input signal IN and the input signal INB have a complementary relation of the first high level or the low level, the input signal INB becomes the low level from the first high level, and the output signal OUT rises from the low level to the second high level when the input signal IN becomes the first high level from the low level.

In this case, attention is paid to charging and discharging currents at the terminal T2. The logic value (signal level) of the output signal OUT is determined by charging and discharging the terminal T2with the charging and discharging currents flowing through the pMOS transistor MP41and the nMOS transistor MN41. The gate voltages of the pMOS transistor MP41and the nMOS transistor MN41taking charge of charging and discharging are determined by the current IA1generated by the current generator circuit10. Therefore, it is not necessary to strictly striking a balance of the amounts of currents flowing through the pMOS transistor MP41and the nMOS transistor MN41. That is, the level converter circuit1has tolerances to a voltage difference between the high power supply voltage VDDH and the low power supply voltage VDDL, process variations, and temperature changes as compared with the prior art level converter circuit100shown inFIG. 2.

The differential amplifier circuit30and the source-grounded amplifier circuit40normally operate by utilizing a current generated from a reference current generator circuit. However, it is not preferable that a current regularly flows because it increases power consumption. In general, the level converter circuit1is required to operate at high speed only when the voltage of the input signal IN changes. That is, by generating a current that flows through the differential amplifier circuit30and the source-grounded amplifier circuit40only when the voltage of the input signal IN changes and generating no current when the voltage of the input signal IN does not change, low power consumption of the level converter circuit1can be achieved. Therefore, the current generator circuit10for the above purpose was considered.

FIG. 4is a block diagram showing a configuration of the current generator circuit10ofFIG. 3B. The current generator circuit10is configured to include nMOS transistors MN11and MN12. The drain of the nMOS transistor MN11is connected to the current detector circuit20, and the gate of the nMOS transistor MN11is connected to a terminal T3. The input signal INB is inputted to the terminal T3from the preprocessing circuit50. The source of the nMOS transistor MN11is connected to the drain of the nMOS transistor MN12. The gate of the nMOS transistor MN12is connected to a terminal T4. The terminal T4is connected to the terminal T1, and the input signal IN is inputted to the terminal T4. The source of the nMOS transistor MN12is grounded. It is noted that the current generator circuit10may be configured by inputting the input signal IN to the terminal T3and inputting the signal INB to the terminal T4.

Referring toFIG. 4, the two nMOS transistors MN11and MN12are connected in cascade, the input signal INB is applied to the gate of the nMOS transistor MN11, and the input signal IN is applied to the gate of the nMOS transistor MN12in the current generator circuit10. In this case, since the signal levels of the input signals INB and IN change with a limited delay time, there is a period or time interval during which both the input signals INB and IN have limited voltages. For this period, the nMOS transistor MN11operates in response to the input signal INB, and the nMOS transistor MN12operates in response to the input signal IN, and generates the current IA1.

FIG. 5is a timing chart showing timings between the voltages of the input signal IN and the input signal INB inputted to the current generator circuit10ofFIG. 4and the currents IA1generated by the current generator circuit10.FIG. 5(a) shows the voltages of the input signal IN and the input signal INB, andFIG. 5(b) shows the current IA1. When the voltage of the input signal IN changes, the voltage of the input signal INB is inverted via the preprocessing circuit50. In this case, there is a period or time interval during which both of the voltages of the input signals IN and INB exceed a threshold voltage Vth for the period or time interval during which the signal levels of the input signals IN and INB change. For the period, the nMOS transistors MN11and MN12enter the ON state, and the current IA1is generated until either one of the input signals becomes the low level. The currents IA2and IA3corresponding to the current IA1are applied to the differential amplifier circuit30and the source-grounded amplifier circuit40, executing the level conversion operation. When the voltage of the input signal IN does not change, the level converter circuit1operates only with a leakage current flowing through the nMOS transistors MN11and MN12. Therefore, by utilizing the current generator circuit10, the level converter circuit1can achieve the signal level conversion operation with low power consumption.

The delay time from the change of the input signal IN to the change of the output signal OUT depends on the current IA1generated by the current generator circuit10. Therefore, the delay time can be controlled by adjusting the transistor sizes or the threshold voltages of the two nMOS transistors MN11and MN12connected in cascade or adjusting the current mirror ratios of the differential amplifier circuit30and the source-grounded amplifier circuit40.

As described above, according to the first preferred embodiment, the signal level is converted by applying the currents IA2and IA3corresponding to the current IA1generated by the current generator circuit10to the differential amplifier circuit30and the source-grounded amplifier circuit40, respectively. Therefore, even when the difference voltage between the low power supply voltage VDDL and the high power supply voltage VDDH is large, the level converter circuit1stably operates. Moreover, since the current IA1is generated only when the voltage of input signal IN changes, and the IA1is not generated when the voltage of the input signal IN does not change, the level converter circuit1operates with low power consumption.

FIG. 6is a circuit diagram showing a configuration of a current generator circuit10aaccording to a first modified preferred embodiment of the current generator circuit10ofFIG. 4. The current generator circuit10aofFIG. 6differs from the current generator circuit10ofFIG. 4in that a Vc1generator (voltage generator)501that generates a voltage Vc1, a Vc2generator (voltage generator)502that generates a voltage Vc2, and a controller503are further provided. The substrate potential (well potential) of the nMOS transistor MN11is set to the voltage Vc1generated by the Vc1generator501, and the substrate potential of the nMOS transistor MN12is set to the voltage Vc2generated by the Vc2generator502. The controller503controls the voltages Vc1and Vc2generated by the Vc1generator501and the Vc2generator502so that the threshold voltages of the nMOS transistors MN11and MN12become lower than the threshold voltages of the nMOS transistors MN11and MN12in the current generator circuit10. By this operation, the current IA1generated by the current generator circuit10aincreases more than the current IA1generated by the current generator circuit10, and the level converter circuit1operates at higher speed.

FIG. 7is a circuit diagram showing a configuration of a current generator circuit10baccording to a second modified preferred embodiment of the current generator circuit10ofFIG. 4. The current generator circuit10bofFIG. 7differs from the current generator circuit10ofFIG. 4in that the substrate potential of the nMOS transistor MN11is set to a voltage identical to the voltage of the drain of the nMOS transistor MN11, and the substrate potential of the nMOS transistor MN12is set to a voltage identical to the voltage of the drain of the nMOS transistor MN12. With this arrangement, the threshold voltages of the nMOS transistors MN11and MN12become lower than the threshold voltages of the nMOS transistors MN11and MN12in the current generator circuit10, and the current IA1generated by the current generator circuit10bincreases more than the current IA1generated by the current generator circuit10, so that the level converter circuit1operates at higher speed.

FIG. 8is circuit diagram showing a configuration of a current generator circuit10caccording to a third modified preferred embodiment of the current generator circuit10ofFIG. 4. The current generator circuit10cofFIG. 8differs from the current generator circuit10ofFIG. 4in that the substrate potential of the nMOS transistor MN11is set to a voltage identical to the voltage of the drain of the nMOS transistor MN11, and the substrate potential of the nMOS transistor MN12is set to a voltage identical to the voltage of the source of the nMOS transistor MN12. With this arrangement, the threshold voltage of the nMOS transistor MN11become lower than the threshold voltage of the nMOS transistor MN11in the current generator circuit10, and the current IA1generated by the current generator circuit10cincreases more than the current IA1generated by the current generator circuit10, so that the level converter circuit1operates at higher speed.

FIG. 9is a circuit diagram showing a configuration of a current generator circuit10daccording to a fourth modified preferred embodiment of the current generator circuit10ofFIG. 4. The current generator circuit10dofFIG. 9differs from the current generator circuit10ofFIG. 4in that nMOS transistors MN11aand MN12aare further provided. The drain of the nMOS transistor MN11ais connected to the current detector circuit20, the gate of the nMOS transistor MN11ais connected to the terminal T3, and the input signal INB is inputted to its gate. The source of the nMOS transistor MN11ais connected to the drain of the nMOS transistor MN12a. The gate of the nMOS transistor MN12ais connected to the terminal T4, and the input signal IN is inputted to its gate. The source of the nMOS transistor MN12ais grounded.

Referring toFIG. 9, the nMOS transistors MN11aand MN12aare configured to have connections in a manner similar to those of the nMOS transistors MN11and MN12ofFIG. 4. With this arrangement, a path through which the current flows in the current generator circuit10dincreases more than the current flowing through the current generator circuit10. Therefore, the current IA1generated by the current generator circuit10dincreases more than the current IA1generated by the current generator circuit10, so that the level converter circuit1operates at higher speed.

It is acceptable to increase the gate width, transistor size or channel width of the nMOS transistors MN11and MN12of the current generator circuit10. With this arrangement, the current IA1generated by the current generator circuit10increases, so that the level converter circuit1operates at higher speed.

Second Preferred Embodiment

The operation of the level converter circuit1has such a problem that it strongly depends on the waveform of the input signal IN. Moreover, the level converter circuit1has a problem in the noise immunity in terms of the characteristics of the circuit operation. That is, there are the following two problems.

Problem A: When there is no period during which an overlap between the waveform of the input signal IN and the waveform of the input signal INB, i.e., both the input signal IN and the input signals INB have the first high level, the current generator circuit10does not generate the current IA1.

Problem B: After the logic value of the output signal OUT is established, the current generator circuit10does not operate, and the level converter circuit1operates with a leakage current. Therefore, it is possible that the level converter circuit1has a vulnerability to disturbances such as noises.

The problem A and the problem B will be each described below.

First of all, the problem A will be described.FIG. 10Ais a graph showing ideal waveforms of the input signals IN and INB to the level converter circuit1ofFIG. 3B, andFIG. 10Bis a graph showing non-ideal waveforms of the input signals IN and INB to the level converter circuit1ofFIG. 3B. The level converter circuit1detects a voltage domain in which the logic values of the input signal IN and the input signal INB overlap each other by the nMOS transistors MN11and MN12connected in cascade, and operates by generating the current IA1. As apparent fromFIG. 10A, in the case of the ideal waveforms of the input signals IN and INB, there is a period or time interval during which both the input signals INB and IN have limited voltages, i.e., both of them have the high level for the period or time interval during which the logic values of the input signals INB and IN change. The nMOS transistors MN11and MN12enter the ON state for this period, generating the current IA1for operating the level converter circuit1. On the other hand, in the case of the non-ideal waveforms of the input signals IN and INB shown inFIG. 10B, the waveforms of the input signal IN and the input signal INB overlap each other at the rise of the input signal IN, whereas the waveforms of the input signal IN and the input signal INB do not overlap each other at the fall of the input signal IN. This means that the current generator circuit10cannot generate a sufficient current IA1at the fall of the input signal IN, and this leads to such a problem that it is impossible to guarantee the stable operation of the level converter circuit1.

The problem B will be next described. In the level converter circuit1, the current generator circuit10operates only when the logic value of the output signal OUT changes, generating the current IA1. The differential amplifier circuit30and the source-grounded amplifier circuit40are operated by the currents IA2and IA3corresponding to the current IA1, and achieves the level conversion operation. However, considering time after the change in the logic value of the output signal OUT, the terminal T2enters a floating state, and this leads to a vulnerability to disturbances such as noises. That is, there is such a problem that, even if the output signal OUT falls from the second high level due to influences of noises and the like for the period during which the level converter circuit1should output the output signal OUT of the second high level, this phenomenon cannot be corrected. Moreover, there is such a problem that, even if the output signal OUT rises from the low level due to influences of noises and the like for the period during which the level converter circuit1should output the output signal OUT of the low level, this phenomenon cannot be corrected.

A level converter circuit1A according to the second preferred embodiment solves the aforementioned problems A and B. The level converter circuit1A solves the aforementioned problems A and B by introducing a feedback control system into the fundamental structure of the level converter circuit1.

FIG. 11Ais a block diagram showing an application example of the level converter circuit1A of the second preferred embodiment of the present invention. Referring toFIG. 11A, the level converter circuit1A converts the signal level of a signal from the low voltage circuit block200to which the low power supply voltage VDDL (e.g., 0.4 V) is supplied, and outputs the resulting signal to the high voltage circuit block300to which the high power supply voltage VDDH (e.g., 3 V) is supplied. Hereinafter, the input signals IN and INB, the first high level, the second high level, the low voltage source and the high voltage source are similar to the input signals IN and INB, the first high level, the second high level, the low voltage source and the high voltage source, respectively, described in the first preferred embodiment.

FIG. 11Bis a block diagram showing a configuration of the level converter circuit1A of the second preferred embodiment of the present invention. Referring toFIG. 11B, the level converter circuit1A differs from the level converter circuit1of the first preferred embodiment in that a current generator circuit10A is provided in place of the current generator circuit10, and the other components are similar to those of the level converter circuit1, for which no description is provided. As shown inFIG. 11B, the output signal OUT is inputted to the current generator circuit10A, and the feedback control is executed.

FIG. 12is a circuit diagram showing a configuration of the current generator circuit10A ofFIG. 11B. The current generator circuit10A is configured to include a change current generator circuit11, a rise current generator circuit12, and a fall current generator circuit13.

The change current generator circuit11has a configuration similar to that of the current generator circuit10ofFIG. 4, and operates likewise. The rise current generator circuit12monitors the rise of the input signal IN, and the fall current generator circuit13monitors the fall of the input signal IN. In this case, a current generated by the change current generator circuit11is assumed to be a current IC(also referred to as a control current IC), a current generated by the rise current generator circuit12is assumed to be a current IR(also referred to as a control current IR), and a current generated by the fall current generator circuit13is assumed to be a current IF(also referred to as a control current IF). The rise current generator circuit12and the fall current generator circuit13will be described below.

The rise current generator circuit12is configured to include a pMOS transistor MP11, nMOS transistors MN13, MN14and MN15, and terminals T5, T6and T7. The source of the pMOS transistor MP11is connected to the high voltage source, the gate of the pMOS transistor MP11is connected to the terminal T5, and the output signal OUT is inputted to its gate. The drain of the pMOS transistor MP11is connected to the drain of an nMOS transistor MN13. The gate of the nMOS transistor MN13is connected to the terminal T6, and the input signal IN is inputted to its gate. The source of the nMOS transistor MN13is grounded. Moreover, a connection point of the drain of the pMOS transistor MP11and the drain of the nMOS transistor MN13is referred to as a node N11. The drain of the nMOS transistor MN14is connected to the current detector circuit20, the gate of the nMOS transistor MN14is connected to the terminal T7, and the input signal IN is inputted to its gate. The source of the nMOS transistor MN14is connected to the drain of the nMOS transistor MN15. The gate of the nMOS transistor MN15is connected to the node N11, and the source of the nMOS transistor MN15is grounded. In this case, the terminal T5is connected to the terminal T2, and the terminal T6and the terminal T7are connected to the terminal T1.

The rise current generator circuit12is implemented by a two-stage configuration. In the circuit of the first stage, the pMOS transistor MP11monitors the output signal OUT, and the nMOS transistor MN13monitors the input signal IN. In the circuit of the second stage, the nMOS transistors MN14and MN15are connected in cascade, the nMOS transistor MN15monitors the voltage at the node N11, and the nMOS transistor MN14monitors the input signal IN. With this circuit configuration, the pMOS transistor MP11operates in response to the output signal OUT, the nMOS transistors MN13and MN14operate in response to the input signal IN, and the nMOS transistor MN15operates in response to the voltage at the node N11. Moreover, the rise current generator circuit12operates only when the input signal IN has first high level and the output signal OUT has the low level, and generates the current IRfor correction so that the output signal OUT becomes the second high level.

When the input signal IN has the first high level and the output signal OUT has the second high level, the voltage at the node N11becomes the low level. Therefore, the nMOS transistor MN15enters the OFF state, and the circuit of the second stage does not generate the current IR. When the input signal IN has the first high level and the output signal OUT has the low level, i.e., when the logic values of the input signal IN and the output signal OUT do not coincide with each other, the voltage at the node N11becomes the high level to turn on the nMOS transistor MN15, and the circuit of the second stage generates the current IR. The amount of current of the current IRis defined by the voltage of the input signal IN, i.e., the low power supply voltage VDDL.

The fall current generator circuit13is configured to include nMOS transistors MN16and MN17, and terminals T8and T9. The drain of the nMOS transistor MN16is connected to the current detector circuit20, the gate of the nMOS transistor MN16is connected to the terminal T8, and the input signal INB is inputted to its gate. The source of the nMOS transistor MN16is connected to the drain of the nMOS transistor MN17. The gate of the nMOS transistor MN17is connected to the terminal T9, and the output signal OUT is inputted to its gate. The source of the nMOS transistor MN17is grounded. In this case, the input signal INB is inputted to the terminal T8from the preprocessing circuit50, and the terminal T9is connected to the terminal T2.

The fall current generator circuit13is implemented by a one-stage configuration. The nMOS transistors MN16and MN17are connected in cascade, the nMOS transistor MN17monitors the output signal OUT, and the nMOS transistor MN16monitors the input signal INB. With this circuit configuration, the nMOS transistor MN16operates in response to the input signal INB, and the nMOS transistor MN17operates in response to the output signal OUT. Moreover, when the fall current generator circuit13operates only when the input signal IN has the low level (in this case, the input signal INB has the first high level) and the output signal OUT has the second high level, generating the current IFfor correction so that the output signal OUT becomes the low level.

When the input signal IN has the low level and the output signal OUT has the low level, the fall current generator circuit13does not operate. When the input signal IN has the low level and the output signal OUT has the second high level, i.e., when the logic values of the input signal IN and the output signal OUT do not coincide with each other, the fall current generator circuit13generates the current IF. The amount of current of the current IFis defined by the voltage of the input signal INB, i.e., the low power supply voltage VDDL.

First of all, operation of the current generator circuit10A when the input signal IN has the first high level (the input signal INB has the low level) will be described below. Reference is first made to a case where the output signal OUT has the second high level. In this case, the logic values of the input signal IN and the output signal OUT coincide with each other. Since the nMOS transistor MN11is in the OFF state, the change current generator circuit11does not generate the current IC. Moreover, since the pMOS transistor MP11is in the OFF state and the nMOS transistor MN13is in the ON state, the voltage at the node N11of the rise current generator circuit12is lowered to the ground voltage. The nMOS transistor MN15enters the OFF state in response to the voltage at the node N11. Therefore, the rise current generator circuit12does not generate the current IR. Further, since the nMOS transistor MN16is in the OFF state, the fall current generator circuit13does not generate the current IF. Therefore, when the input signal IN has the first high level and the output signal OUT has the second high level, the current generator circuit10A generates no current.

Reference is next made to a case where the output signal OUT has the low level. In this case, the logic values of the input signal IN and the output signal OUT do not coincide with each other. Since the nMOS transistor MN11is in the OFF state, the change current generator circuit11does not generate the current IC. Moreover, in the rise current generator circuit12, the pMOS transistor MP11enters the ON state, and the voltage at the node N11rises to the high power supply voltage VDDH. The nMOS transistor MN15enters the ON state in response to the voltage at the node N11, thereby generating the current IR. Further, since the nMOS transistor MN16is in the OFF state, the fall current generator circuit13does not generate the current IF. Therefore, when the input signal IN has the first high level and the output signal OUT has the low level, the current generator circuit10A generates the current IR.

Next, operation of the current generator circuit10A when the input signal IN has the low level (the input signal INB has the first high level) will be described below. Reference is first made to a case where the output signal OUT has the low level. In this case, the logic values of the input signal IN and the output signal OUT coincide with each other. Since the nMOS transistor MN12is in the OFF state, the change current generator circuit11does not generate the current IC. Moreover, since the pMOS transistor MP11is in the ON state and the nMOS transistor MN13is in the OFF state in the rise current generator circuit12, the voltage at the node N11rises to the high power supply voltage VDDH. The nMOS transistor MN15is in the ON state in response to the voltage at the node N11, whereas the nMOS transistor MN14is in the OFF state since the input signal IN has the low level. Therefore, the rise current generator circuit12does not generate the current IR. Further, since the nMOS transistor MN17is in the OFF state, the fall current generator circuit13does not generate the current IF. Therefore, when the input signal IN has the low level and the output signal OUT has the low level, the current generator circuit10A generates no current.

Next, reference is made to a case where the output signal OUT has the second high level. In this case, the logic values of the input signal IN and the output signal OUT do not coincide with each other. Since the nMOS transistor MN12is in the OFF state, the change current generator circuit11does not generate the current IC. Moreover, in the rise current generator circuit12, the pMOS transistor MP11enters the OFF state, and the node N11enters the floating state. However, the nMOS transistor MN14enters the OFF state since the input signal IN has the low level, and therefore, the rise current generator circuit12does not generate the current IR. Moreover, since the nMOS transistors MN16and MN17enter the ON state, the fall current generator circuit13generates the current IF. Therefore, when the input signal IN has the low level and the output signal OUT has the second high level, the current generator circuit10A generates the current IF.

Further, the effects of the level converter circuit1A regarding the aforementioned problems A and B of the level converter circuit1are considered.

First of all, the problem A will be described. When there is no period during which both the input signal IN and the input signal INB become the first high level, the current generator circuit10cannot correctly generate a current. In this case, the logic values of the input signal IN and the output signal OUT do not coincide with each other. In contrast to this, the logical inconsistency can be solved by using the current generator circuit10A. That is, when there is a logical inconsistency such that the input signal IN has the first high level and the output signal OUT has the low level, the rise current generator circuit12generates the current IR. Moreover, when there is a logical inconsistency such that the input signal IN has the low level and the output signal OUT has the second high level, the fall current generator circuit13generates the current IF. By this operation, the current generator circuit10A generates a current when there is the logical inconsistency, and it is possible to establish the output of the correct logic values.

This means that the level converter circuit1A can cope with the non-ideal waveforms of the input signals IN and INB shown inFIG. 10B. Moreover, in the case of non-ideal waveforms different fromFIG. 10B, i.e., when the waveforms of the input signal IN and the input signal INB do not overlap at the rise of the input signal IN, and also when the waveforms of the input signal IN and the input signal INB do not overlap at the rise and fall of the input signal IN, the level converter circuit1A normally operates.

Next, the problem B will be described. A case where the logic value of the input signal IN is the first high level, and the logic value of the output signal OUT is the second high level, i.e., the logic values coincide with each other at the high level is considered. In this case, the terminal T2is charged with a leakage current, and the terminal T2enters a high impedance state. In this case, a case where the voltage of the output signal OUT is lowered by the disturbances such as external noises is considered. When the voltage of the output signal OUT is gradually lowered, the pMOS transistor MP11of the rise current generator circuit12that monitors the output signal OUT generates a current corresponding to the lowering of the voltage of the output signal OUT, and the voltage at the node N11gradually rises. In accordance with this, the nMOS transistor MN15that monitors the voltage at the node N11starts generating the current IR. As described above, when the voltage of the output signal OUT is lowered, the current IRis generated by the rise current generator circuit12, and a current is supplied to the differential amplifier circuit30and the source-grounded amplifier circuit40so that the lowering of the voltage of the output signal OUT is avoided.

Next, a case where the logic value of the input signal IN is the low level, and the logic value of the output signal OUT is the low level, i.e., the logic values coincide with each other at the low level is considered. In this case, the terminal T2is discharged with a leakage current, and the terminal T2enters the high impedance state. In this case, a case where the voltage of the output signal OUT is raised by disturbances such as external noises is considered. When the voltage of the output signal OUT gradually rises, the nMOS transistor MN17of the fall current generator circuit13that monitors the output signal OUT generates a current corresponding to a rise in the voltage of the output signal OUT. Moreover, since the input signal INB having the first high level is applied to the gate of the nMOS transistor MN16, the nMOS transistor MN16is in the ON state. As described above, when the voltage of the output signal OUT rises, the current IFis generated by the fall current generator circuit13, and a current is supplied to the differential amplifier circuit30and the source-grounded amplifier circuit40so that a rise in the voltage of the output signal OUT is avoided.

As described above, according to the second preferred embodiment, operative effects similar to those of the first preferred embodiment are produced. Moreover, also when the period during which both the input signal IN and the input signals INB have the first high level does not exist, the rise current generator circuit12generates the current IRor the fall current generator circuit13generates the current IF, and therefore, the level converter circuit1A normally operates. Further, also when the voltage of the output signal OUT changes due to disturbances such as external noises, the rise current generator circuit12generates the current IRor the fall current generator circuit13generates the current IF, and therefore, the level converter circuit1A normally operates.

Although the current generator circuit10A is configured by providing the rise current generator circuit12and the fall current generator circuit13in the second preferred embodiment, the present invention is not limited to this, and it is acceptable to constitute the current generator circuit10A by providing either one of the rise current generator circuit12and the fall current generator circuit13.

Third Preferred Embodiment

FIG. 13Ais a block diagram showing an application example of a level converter circuit1B according to the third preferred embodiment of the present invention. Referring toFIG. 13A, the level converter circuit1B converts the signal level of a signal from the low voltage circuit block200to which the low power supply voltage VDDL (e.g., 0.4 V) is supplied, and outputs the resulting signal to the high voltage circuit block300to which the high power supply voltage VDDH (e.g., 3V) is supplied. Hereinafter, the input signals IN and INB, the first high level, the second high level, the low voltage source and the high voltage source are similar to the input signals IN and INB, the first high level, the second high level, the low voltage source and the high voltage source described in the first preferred embodiment.

FIG. 13Bis a block diagram showing a configuration of the level converter circuit1B of the third preferred embodiment of the present invention. The level converter circuit1A of the second preferred embodiment has had such a problem that the characteristic of the current IFcannot sufficiently be evaluated.

The level converter circuit1B differs from the level converter circuit1A in that a differential amplifier circuit30B is provided in place of the differential amplifier circuit30and a push-pull type source-grounded amplifier circuit40B is provided in place of the source-grounded amplifier circuit40. The other components are similar to those of the level converter circuit1A, and no description is provided therefor.

The differential amplifier circuit30B differs from the differential amplifier circuit30in that a connection point of the drain of the pMOS transistor MP32and the drain of the nMOS transistor MN31is connected to the gate of the nMOS transistor MN42, and a connection point of the drain of the pMOS transistor MP33and the drain of the nMOS transistor MN32is connected to the gate of the nMOS transistor MN43. The other components and operations are similar to those of the differential amplifier circuit30.

The push-pull type source-grounded amplifier circuit40B is configured to include pMOS transistors MP42and MP43, and nMOS transistors MN42and MN43. The source of the pMOS transistor MP42is connected to the high voltage source, and the gate of the pMOS transistor MP42is connected to the drain of the pMOS transistor MP42and the gate of the pMOS transistor MP43. The drain of the pMOS transistor MP42is connected to the drain of the nMOS transistor MN42. The gate of the nMOS transistor MN42is connected to a connection point of the drain of the pMOS transistor MP32and the drain of the nMOS transistor MN31, and the source of the nMOS transistor MN42is grounded. The source of the pMOS transistor MP43is connected to the high voltage source, and the drain of the pMOS transistor MP43is connected to the drain of the nMOS transistor MN43. The gate of the nMOS transistor MN43is connected to a connection point of the drain of the pMOS transistor MP33and the drain of nMOS transistor MN32, and the source of the nMOS transistor MN43is grounded. A connection point of the drain of the pMOS transistor MP43and the drain of the nMOS transistor MN43is connected to the terminal T2. In this case, the differential amplifier circuit303and the push-pull type source-grounded amplifier circuit40B constitute a two-stage amplifier circuit.

The push-pull type source-grounded amplifier circuit40B, which is configured as described above, is able to charge or discharge the terminal T2with a current corresponding to the current generated by the current generator circuit10A both at the rise and the fall of the output signal OUT.

As described above, according to the third preferred embodiment, operative effects similar to those of the second preferred embodiment are produced.

Although the level converter circuit1and the level converter circuit1A have been configured to include the differential amplifier circuit30and the source-grounded amplifier circuit40, respectively, in the first and second preferred embodiments, the present invention is not limited to this, and it is acceptable to constitute the level converter circuit1and the level converter circuit1A of the differential amplifier circuit30B and the push-pull type source-grounded amplifier circuit40B.

First Implemental Example

A simulation evaluation (first implemental example) of the level converter circuit1of the first preferred embodiment will be described below. Results of a SPICE simulation evaluation regarding the level converter circuit1ofFIG. 3Bare shown. In this case, a 0.35-μm CMOS process was used. The low power supply voltage VDDL was set to 0.4 to 0.8 V, and the high power supply voltage VDDH was set to 3 V.

The present inventors conducted a simulation evaluation of the current generator circuit10.FIG. 14is a graph showing dependency of a peak current generated by the current generator circuit10ofFIG. 4on the low power supply voltage VDDL.FIG. 14shows the peak current value of the current IA1generated by the current generator circuit10when the low power supply voltage VDDL is changed from 0.4 V to 0.8 V. It can be confirmed that the peak current exponentially increases in accordance with a rise in the low power supply voltage VDDL. This is because the nMOS transistors MN11and MN12connected in cascade of the current generator circuit10operate in the subthreshold region below the threshold voltage when the low power supply voltage VDDL is a low voltage, and the gate voltages of the nMOS transistors MN11and MN12rise when the low power supply voltage VDDL rises, as a consequence of which the current flowing through the nMOS transistors MN11and MN12exponentially increases.

The current IA1generated by the current generator circuit10is supplied to the differential amplifier circuit30and the source-grounded amplifier circuit40via a current mirror circuit as configured to include the pMOS transistors MP21, MP31and MP41. As shown inFIG. 5, the current IA1generated by the current generator circuit10becomes a pulse current, and this therefore leads to a problem of the current supply accuracy via the current mirror circuit. Accordingly, the frequency characteristics of the current IA2supplied to the differential amplifier circuit30and the current IA3supplied to the source-grounded amplifier circuit40were evaluated.

FIG. 15is a graph showing frequency response characteristics of the currents IA2and IA3ofFIG. 3B. As shown inFIG. 15, it can be understood that the current mirror circuit is able to supply the currents to the differential amplifier circuit30and the source-grounded amplifier circuit40with a constant current gain maintained when the frequency of the current IA1is not higher than about 2 MHz. When the frequency of the current IA1exceeds 2 MHz, the current gain is reduced by the low-pass filter effect of the current mirror circuit. That is, the level converter circuit1has an operation band of several megahertz. In order to improve the operation band of the level converter circuit1, a device to increase the amount of current of the current IA1generated by the current generator circuit10is necessary. By using current generator circuits10a,10b,10cand10daccording to a modified preferred embodiment of the current generator circuit10described above, the amount of current of the current IA1generated by the current generator circuit10can be increased.

The present inventors conducted a simulation evaluation by setting the low power supply voltage VDDL to 0.55 V and setting the frequency of the input signal IN to 10 kHz as one example of the operation of the level converter circuit1.

FIG. 16(a) is a graph showing a waveform of the input signal IN to the level converter circuit1ofFIG. 1, and showing and the waveform of the output signal OUT from the level converter circuit1ofFIG. 1.FIG. 16(b) is a graph showing a waveform of the current IA1generated by the current generator circuit10ofFIG. 2. As shown inFIG. 16(a), the output signal OUT having amplitude of 0 to 3 V is outputted in synchronization with the logic value of the input signal IN. Moreover, as shown inFIG. 16(b), a large current IA1is generated only when the logic value of the input signal IN is inverted.

FIG. 17is a graph showing delay times of the level converter circuit1ofFIG. 3Band the prior art level converter circuit100with respect to the voltage value of the low power supply voltage VDDL. The delay time of the level converter circuit1ofFIG. 3Bis compared with the delay time of the prior art level converter circuit100shown inFIG. 2. The prior art level converter circuit100operates at higher speed than the level converter circuit1when the low power supply voltage VDDL is not lower than 0.7 V. However, the operating delay of the level converter circuit100exponentially increases as the low power supply voltage VDDL is lowered, and the level converter circuit100cannot operate when the low power supply voltage VDDL becomes 0.52 V or less. This is because the current for discharging the terminal T102to lower the voltage of the output signal OUT depends on the voltage of the low power supply voltage VDDL in the prior art level converter circuit100. That is, the current flowing through the nMOS transistor MN102decreases and the delay time exponentially increases as the low power supply voltage VDDL becomes a lower voltage. When the low power supply voltage VDDL becomes 0.52 V or less, the amount of the current flowing through the pMOS transistor MP102becomes larger than the amount of the current flowing through the nMOS transistor MN102, and the logic value of the output signal OUT is not inverted, stopping the operation of the level converter circuit100.

On the other hand, in the level converter circuit1, the delay time is determined by the amount of current of the current IA1generated by the current generator circuit10. In a region in which the low power supply voltage VDDL is lower than about 0.65 V, the nMOS transistors MN11and MN12of the current generator circuit10operate in the subthreshold region. Therefore, as shown inFIG. 14, the amount of current of the current IA1changes exponentially to the low power supply voltage VDDL. As a result, the delay time exponentially decreases in accordance with a rise in the low power supply voltage VDDL. Moreover, in a region in which the low power supply voltage VDDL is higher than about 0.65 V, the delay time becomes almost constant. This is because the current IA1generated by the current generator circuit10increases when the low power supply voltage VDDL becomes higher than about 0.65 V, whereas the capability of supplying the current IA1generated by the low-pass filter effect of the current mirror circuit is reduced as shown inFIG. 15. As a result, neither the current IA2flowing through the differential amplifier circuit30nor the current IA3flowing through the source-grounded amplifier circuit40increases, and the delay time becomes almost constant. This coincides with the result ofFIG. 15also for the reason that the frequency reciprocal of the delay time ofFIG. 17is on several megahertz order. Since the level converter circuit1carries out both charging and discharging of the terminal T2by using a current corresponding to the current IA1generated by the current generator circuit10, such a problem that the prior art level converter circuit100has does not occur, and stable operation is achieved with a low power supply voltage VDDL such that a power supply voltage difference between the low power supply voltage VDDL and the high power supply voltage VDDH becomes large.

FIG. 18is a graph showing a power consumption of the level converter circuit1ofFIG. 3Band the power consumption of the prior art level converter circuit100with respect to the voltage value of the low power supply voltage VDDL. In this case, the frequency of the input signal IN is 1 kHz. Moreover, the power consumption of the level converter circuit1ofFIG. 313is compared with the power consumption of the prior art level converter circuit100shown inFIG. 2. As is apparent fromFIG. 18, the level converter circuit1is operable with low power consumption as compared with the prior art level converter circuit100. The prior art level converter circuit100has high power consumption because a large amount of through current flows from the high voltage source.

Moreover, inFIG. 18, it can be confirmed that the power consumption of the prior art level converter circuit100is exponentially reduced in accordance with a rise in the low power supply voltage VDDL. This is ascribed to the signal waveform of the logic circuit that operates on the low power supply voltage VDDL. In the logic circuit that operates on the low power supply voltage VDDL, the current driving capability of the transistors becomes extremely reduced, and the signal gradually changes. Therefore, the signal transition duration becomes long in the case of a low power supply voltage VDDL of about 0.55 V, and a large amount of through current flows from the high voltage source. On the other hand, the signal steeply changes in accordance with a rise in the low power supply voltage VDDL, and therefore, the through current from the high voltage source decreases.

On the other hand, the power consumption of the level converter circuit1scarcely changes even if the low power supply voltage VDDL changes. This is caused by the following two grounds due to a rise in the low power supply voltage VDDL:

(1) an increase in the current IA1generated by the current generator circuit10; and

(2) an improvement in the signal delay of the logic circuit driven by the low power supply voltage VDDL.

As shown inFIG. 14, the current IA1generated by the current generator circuit10exponentially increases in accordance with a rise in the low power supply voltage VDDL. On the other hand, the delay time of the logic circuit that operates on the low power supply voltage VDDL exponential decreases in accordance with a rise in the low power supply voltage VDDL. Due to these two grounds, the current IA1that momentarily flows exponentially increases, whereas the time duration when the current IA1flows becomes exponentially shorter. Therefore, the total amount of the current IA1that finally flows scarcely changes. Therefore, the power consumption of the level converter circuit1has small dependence on the low power supply voltage VDDL.

Table 1 shows tolerances to the process variations of the level converter circuit1ofFIG. 3Band the prior art level converter circuit100and temperature changes. In Table 1, the low power supply voltage VDDL is 0.6 V. Moreover, FF, FS, TT, SF and SS in Table 1 represent the corner model of an nMOS transistor and a pMOS transistor, P represents a pass state in which the level converter circuit normally operates, and F represents a fail state in which the level converter circuit does not normally operate.

The prior art level converter circuit100does not normally operate when the threshold voltage of the nMOS transistor is raised by the process variations and temperature changes. This is ascribed to the fact that the terminal T102is not discharged because the current flowing through the nMOS transistor MN102becomes smaller than the leakage current flowing through the pMOS transistor MP102in a manner similar to that of the results of the dependence of the delay time on the low power supply voltage VDDL. On the other hand, the level converter circuit1operates stably to the process variations and temperature changes.

The present inventors produced a chip for trial purposes to confirm the effectiveness of the level converter circuit1. The measurement results of the signal waveforms and the power consumption of the prototype chip are shown below. In this case, a 0.35-μm 2P-4M CMOS process was used.FIG. 19shows a photograph of the prototype chip. The circuit area is a small area of 43 μm×43 μm.

FIG. 20is a block diagram showing a measurement environment for measuring the operation of the prototype chip ofFIG. 19. As shown inFIG. 20, measurements were performed by mounting a packaged prototype chip402on a board. The input signal IN of low amplitude is generated by using a function generator401, and the signal is inputted to the level converter circuit (prototype chip402). The input signal IN from the function generator401and the output signal OUT from the level converter circuit were inputted to an oscilloscope403and evaluated. Moreover, the high power supply voltage VDDH is 3 V.

FIG. 21(a) is a graph showing a waveform of the input signal IN to the prototype chip402in the measurement environment ofFIG. 20, andFIG. 21(b) is a graph showing a waveform of the output signal OUT from the prototype chip in the measurement environment ofFIG. 20. Namely,FIG. 21(a) andFIG. 21(b) show the waveform of the input signal IN and the waveform of the output signal OUT when the low power supply voltage VDDL is 0.4 V and the frequency of the input signal IN is 10 kHz. It can be confirmed that the low-amplitude input signal IN having an amplitude of 0.4 V is converted in level into a large-amplitude output signal OUT having an amplitude of 3 V by the level converter circuit1.

Moreover, as apparent from the results ofFIG. 21, it can be understood that the rise time and the fall time from the change in the input signal IN until the change of the output signal OUT differ from each other. As a result, the duty ratio of the output signal OUT became 50% or less. This is attributed to the characteristics of the level converter circuit1. The charging and discharging of the terminal T2of the level converter circuit1shown inFIG. 3Bis performed by the current flowing through the pMOS transistor MP41and the nMOS transistor MN41. In this case, the rise time of the output signal OUT is determined by the current flowing through the pMOS transistor MP41, i.e., a current corresponding to the current IA1generated by the current generator circuit10supplied via the current mirror circuit. On the other hand, the current flowing through the nMOS transistor MN41is determined by the voltage applied to the gate of the nMOS transistor MN41. A time duration when the capacitance of the gate of the nMOS transistor MN41is charged and discharged is also determined by a current corresponding to the current IA1generated by the current generator circuit10supplied via the current mirror circuit. However, due to the characteristics of the circuit configuration of the differential amplifier circuit30, a time duration when the terminal T2is charged by the pMOS transistor MP41and a time duration when the terminal T2is discharged by the nMOS transistor MN41differ from each other. Therefore, the rise time and the fall time of the output signal OUT produce different results. It is required to put the duty ratio close to 50% by constituting a circuit such that the rise time becomes equal to the fall time or taking similar measures.

FIG. 22is a graph showing a Shmoo plot of the prototype chip ofFIG. 19. A frequency band in which the level converter circuit1is operable is plotted with respect to the low power supply voltage VDDL. When the low power supply voltage VDDL is about 0.4 to 0.64 V, the operable maximum frequency exponentially increases. This is because the current IA1generated by the current generator circuit10exponentially increases in accordance with a rise in the low power supply voltage VDDL. When the low power supply voltage VDDL exceeds 0.64 V, the operable frequency becomes almost constant from about 2 MHz. This is because the high frequency components of the current IA1generated by the current generator circuit10are not supplied to the differential amplifier circuit30and the source-grounded amplifier circuit40by the low-pass filter effect of the current mirror circuit, and the current flowing through the differential amplifier circuit30and the source-grounded amplifier circuit40are limited in a manner similar to that of the simulation results shown inFIG. 17.

FIG. 23is a graph showing a power consumption of the prototype chip ofFIG. 19with respect to the voltage value of the low power supply voltage VDDL. In this case, the frequency of the input signal IN is 10 kHz. The power consumption of the prototype chip has small dependence on the low power supply voltage VDDL and decreases with a rise in the low power supply voltage VDDL. This agrees with the simulation results ofFIG. 18.

The level converter circuit1, which operates with lower power consumption than the cross-coupled level converter circuit100and stably operates even if the low power supply voltage VDDL is a low voltage, is useful for low voltage operation LSIs.

In the first preferred embodiment, the level converter circuit1that can stably operate even when the difference voltage between the power supply voltages of the circuit blocks is large is proposed. The level converter circuit1eases the power supply voltage difference dependence of the charging and discharging part, which is the problem of the prior art level converter circuit100, by constituting the circuit based on the two-stage amplifier circuit. Further, the level converter circuit1, which consumes power only when the input signal IN changes, can operate with low power consumption. A chip was produced for trial purposes by using the 0.35-μm standard CMOS process, and the operation was confirmed by measurements. By using the level converter circuit1, the low voltage signal of amplitude of 0.4 V can be converted into the high voltage signal of amplitude of 3 V. The level converter circuit1is useful for low-power-consumption low-voltage-operation LSIs.

Second Implemental Example

A simulation evaluation (second implemental example) of a level converter circuit1A according to the second preferred embodiment will be described. The present inventors conducted a simulation evaluation to confirm the operation of the level converter circuit1A. In this case, the 0.35-μm CMOS process was used.

The present inventors conducted a simulation evaluation of the level converter circuit1A. In this case, the low power supply voltage VDDL is 0.4 V, and the high power supply voltage VDDH is 3.0 V. The simulation results are shown inFIGS. 24 to 27.FIG. 24is a graph showing waveforms of the input signals IN and INB to the level converter circuit1A ofFIG. 11Band the waveform of the output signal OUT from the level converter circuit1A ofFIG. 11B.FIG. 25is a graph showing a waveform of the current ICgenerated by the change current generator circuit11ofFIG. 12.FIG. 26is a graph showing a waveform of the current IFgenerated by the fall current generator circuit13ofFIG. 12.FIG. 27is a graph showing a waveform of the current IRgenerated by the rise current generator circuit12ofFIG. 12.

As shown inFIG. 24, the output signal OUT is converted in level and outputted in conformity to the logic value of the input signal IN. Moreover, the waveforms overlap each other at the rise of the input signal IN and the fall of the input signal INB, whereas the waveforms do not overlap each other at the fall of the input signal IN and the rise of the input signal INB. This means that the current ICis not correctly generated at the fall of the input signal IN.

As shown inFIG. 25, the change current generator circuit11normally generates the current IC(a peak current on the one nano-ampere order) at the rise time of the input signal IN. On the other hand, the change current generator circuit11seems to generate the current IC(a peak current on the two nano-ampere order) at the fall time of the input signal IN. However, since the input signal IN and the input signal INB do not overlap each other at the fall of the input signal IN as described above, it cannot be said that the change current generator circuit11does not normally operate. The current ICis generated by the kickback phenomenon of the output signal OUT, and is not generated by the change current generator circuit11.

However, the level converter circuit1A performs the desired operation (i.e., outputting the low-level output signal OUT). This is because the level conversion operation of the level converter circuit1A depends on the delay time of the rise time and the delay time of the fall time of the output signal OUT in the differential amplifier circuit30and the source-grounded amplifier circuit40and the delay time of the current generator circuit10A. In the differential amplifier circuit30and the source-grounded amplifier circuit40of the level converter circuit1A, the rise delay time of the output signal OUT is determined by the charging current IA3of the pMOS transistor MP41, and the fall time of the output signal OUT is determined by the discharging current IA4of the nMOS transistor MN41. It can be considered that the charging current IA3depends on the current IA1generated by the current generator circuit10A, and the discharging current IA4does not depend on the current generated by the current generator circuit10A.

This is considered in the circuit diagram of the differential amplifier circuit30and the source-grounded amplifier circuit40shown inFIG. 11B. The charging current IA3corresponds to the current IA1generated by the current generator circuit10A supplied via the current mirror circuit as configured to include the pMOS transistors MP21and MP41. On the other hand, the discharge current IA4depends on the gate voltage of the nMOS transistor MN41of the source-grounded amplifier circuit40, i.e., a voltage at the node N31of the differential amplifier circuit30. The voltage at the node N31changes into a voltage close to the first high level from the low level when the input signal IN becomes the low level. Since the voltage at the node N31is applied to the gate of the nMOS transistor MN41, the output signal OUT falls to the low level. The voltage at the node N31does not depend on the current IA1generated by the current generator circuit10A and becomes a voltage close to the first high level to make the output signal OUT fall. That is, in the differential amplifier circuit30and the source-grounded amplifier circuit40, the rise delay time of the output signal OUT is long, and the fall delay time is short. Since the rise delay time is long, a logical inconsistency occurs at the rise of the input signal IN. The rise current generator circuit12of the current generator circuit10A detects the logical inconsistency, and generates the current IRto accelerate the rise of the output signal OUT. On the other hand, since the differential amplifier circuit30and the source-grounded amplifier circuit40of the level converter circuit1A respond quickly at the fall of the output signal OUT, the level converter circuit1A can output the low-level output signal OUT even if the fall current generator circuit13does not operate.

As shown inFIG. 26, it can be confirmed that the current IFis not generated. This is because the output signal OUT falls to the low level before the current generator circuit10A starts operating since the fall delay time of the output signal OUT is short. On the other hand, although the current ICis generated at the rise of the output signal OUT as shown inFIG. 25, it cannot be regarded to be a sufficient amount of current to raise the output signal OUT. The rise current generator circuit12detects the logical inconsistency and generates the current IR. As shown inFIG. 27, it can be confirmed that the current IRis generated at the rise of the output signal OUT.

FIG. 28is a graph showing delay times of the level converter circuit1A ofFIG. 11Band the level converter circuit1ofFIG. 3Bwith respect to the voltage value of the low power supply voltage VDDL. InFIG. 28, the delay time of the level converter circuit1A having the feedback control is indicated by the solid line, and the delay time of the level converter circuit1having no feedback control is indicated by the dashed line. As shown inFIG. 28, it can be confirmed that the delay time of the level converter circuit1A decreases with a rise in the low power supply voltage VDDL. Moreover, it can be confirmed that the level converter circuit1A operates at higher speed than the level converter circuit1. It can be confirmed that the level converter circuit1A operates at a speed several times higher than the level converter circuit1when the low power supply voltage VDDL is a low voltage of not higher than about 0.55 V, and the difference increases as the low power supply voltage VDDL rises. It can be said that the addition of the current IRgenerated by the rise current generator circuit12and the current IFgenerated by the fall current generator circuit13to the operating currents of the differential amplifier circuit30and the source-grounded amplifier circuit40leads to the high-speed operation of the level converter circuit1A.

FIG. 29is a graph showing power consumptions of the level converter circuit1A ofFIG. 11Band the level converter circuit1ofFIG. 3Bwith respect to the voltage value of the low power supply voltage VDDL. Referring toFIG. 29, the power consumption of the level converter circuit1A having feedback control is indicated by the solid line, and the power consumption of the level converter circuit1having no feedback control is indicated by the dashed line. The level converter circuit1A has more power consumption than the level converter circuit1. This is because the current IRgenerated by the rise current generator circuit12and the current IFgenerated by the fall current generator circuit13are added to the operating currents of the differential amplifier circuit30and the source-grounded amplifier circuit40. However, the increased power consumption can be suppressed to a minute power on the nano-watt order.

The present inventors conducted a simulation evaluation for performing the characteristic evaluation of the current generator circuit10A. In this case, the following two simulations were conducted in the current generator circuit10A shown inFIG. 12.

Simulation 1: The current IRgenerated by the rise current generator circuit12and the current IFgenerated by the fall current generator circuit13are measured by fixing the input signal IN to the first high level, fixing the input signal INB to the low level and changing the output signal OUT from 0 V to 3 V.

Simulation 2: The current IRgenerated by the rise current generator circuit12and the current IFgenerated by the fall current generator circuit13are Measured by fixing the input signal IN to the low level, fixing the input signal INB to the first high level and changing the output signal OUT from 0 V to 3 V.

First of all, the results of the Simulation 1 will be described.FIG. 30Ais a graph showing a current IFgenerated when the input signal IN is fixed to the first high level, the input signal INB is fixed to the low level, and the output signal OUT is changed from 0 V to 3 V in the current generator circuit10A ofFIG. 12. Moreover,FIG. 30Bis a graph showing a current IRgenerated when the input signal IN is fixed to the first high level, the input signal INB is fixed to the low level, and the output signal OUT is changed from 0 V to 3 V in the current generator circuit10A ofFIG. 12.

Since the input signal IN has the first high level and the input signal INB has the low level, it is ideal that the output signal OUT has the second high level. As shown inFIG. 30B, it can be confirmed that the current IRis generated when the output signal OUT is a low voltage of not higher than about 2.4 V. The current IRis supplied to the differential amplifier circuit30and the source-grounded amplifier circuit40via the current mirror circuit so that the output signal OUT is raised. On the other hand, it can be confirmed that the current IRis not generated when the output signal OUT is a high voltage, i.e., close to the second high level. Moreover, since the input signal INB has the low level and the output signal OUT is not required to fall in this case, the current IFis not generated as shown inFIG. 30A. The amount of current of the current IR(about 17 nA in the Simulation 1) depends on the value (0.4 V in the Simulation 1) of the low power supply voltage VDDL. The current IRincreases when the low power supply voltage VDDL rises.

Next, the results of the Simulation 2 will be described.FIG. 31Ais a graph showing a current IFgenerated when the input signal IN is fixed to the low level, the input signal INB is fixed to the first high level and the output signal OUT is changed from 0 V to 3 V in the current generator circuit10A ofFIG. 12. Moreover,FIG. 31Bis a graph showing a current IRgenerated when the input signal IN is fixed to the low level, the input signal INB is fixed to the first high level and the output signal OUT is changed from 0 V to 3 V in the current generator circuit10A ofFIG. 12.

Since the input signal IN has the low level and the input signal INB has the first high level, it is ideal that the output signal OUT has the low level. As shown inFIG. 31A, it can be confirmed that the current IFis generated when the output signal OUT is a high voltage of not lower than about 0.3 V. The current IFis supplied to the differential amplifier circuit30and the source-grounded amplifier circuit40via the current mirror circuit so that the output signal OUT is lowered. On the other hand, it can be confirmed that the current IFis not generated when the output signal OUT is a low voltage, i.e., close to the low level. Moreover, since the input signal IN has the low level and the output signal OUT is not required to rise in this case, the current IRis not generated as shown inFIG. 31B. The amount of current of the current IF(about 17 nA in the Simulation 2) depends on the value (0.4 V in the Simulation 2) of the low power supply voltage VDDL. The current IFincreases when the low power supply voltage VDDL rises.

Third Implemental Example

A simulation evaluation (third implemental example) of a level converter circuit1B according to the third preferred embodiment will be described below. The present inventors conducted the simulation evaluation of the level converter circuit1B. The results are shown inFIGS. 32 to 35.FIG. 32is a graph showing waveforms of the input signals IN and INB to the level converter circuit1B ofFIG. 13Band the waveform of the output signal OUT from the level converter circuit1B ofFIG. 13B.FIG. 33is a graph showing a waveform of the current ICgenerated by the change current generator circuit11ofFIG. 12.FIG. 34is a graph showing a waveform of the current IFgenerated by the fall current generator circuit13ofFIG. 12.FIG. 35is a graph showing a waveform of the current IRgenerated by the rise current generator circuit12ofFIG. 12.

As shown inFIG. 32, the output signal OUT is converted in level and outputted in conformity to the logic value of the input signal IN. Moreover, the waveforms overlap each other at the rise of the input signal IN and the fall of the input signal INB, whereas the waveforms do not overlap each other at the fall of the input signal IN and the rise of the input signal INB. Therefore, as shown inFIG. 33, the current ICis generated at the rise of the input signal IN, whereas the current ICis not generated at the fall of the input signal IN. Since the configuration of the two-stage amplifier circuit is changed in the level converter circuit1B as compared with the level converter circuit1A, the output signal OUT does not fall to the low level before the current generator circuit10A starts operating, and the current IFis generated in conformity to the analysis as shown inFIG. 34. Moreover, as shown inFIG. 35, the current IRis generated at the rise of the input signal IN. As described above, it was confirmed that all the circuit blocks (the change current generator circuit11, the rise current generator circuit12and the fall current generator circuit13) of the current generator circuit10A operated in conformity to the analysis.

INDUSTRIAL UTILIZATION APPLICABILITY

As mentioned in detail in the above, according to the level converter circuit of the present invention, the signal level is converted by applying the current corresponding to the current generated by the current generator circuit to the amplifier circuit. Therefore, even when the difference between the first signal level and the second signal level is large, the level converter circuit stably operates. Moreover, the current generator circuit generates the control current only when the signal level of the input signal changes and does not generate the control current when the signal level of the input signal does not change, and therefore, the level converter circuit operates with low power consumption.

In addition, according to the level converter circuit of the present invention, the control circuit that changes the substrate potential of the first and second nMOS transistors are further provided so that the control current is increased as compared with the conventional level converter circuit by lowering the threshold voltages of the first and second nMOS transistors as compared with the conventional level converter circuit. Therefore, the level converter circuit operates at higher speed than the conventional level converter circuit.

Further, according to the level converter circuit of the present invention, the other nMOS transistors are connected in parallel with the first and second nMOS transistors, respectively, so that the control current is increased as compared with conventional the level converter circuit. Therefore, the level converter circuit operates at higher speed than the conventional level converter circuit.

Still further, according to the level converter circuit of the present invention, the rise current generator circuit or the fall current generator circuit generate the control current even when there is no period or time interval during which both the input signal and the inverted signal of the input signal have the high level, and therefore, the level converter circuit normally operates. Further, the rise current generator circuit or the fall current generator circuit generates the control current even when the signal level of the output signal changes due to disturbances such as external noises, and therefore, the level converter circuit normally operates.