Image format conversion system

An image format conversion system includes a horizontal filter to receive an image input signal with a frequency of a first clock signal in order to perform a filtering operation to thereby produce a horizontal filtering image signal; a first FIFO to temporarily store the horizontal filtering image signal; a 2D image interpolator to perform a deinterlacing, a vertical interpolation and a horizontal interpolation operations on the horizontal filtering image signal to further produce a scaled progressive image signal; a second FIFO connected to the 2D image interpolator to temporarily store the scaled progressive image signal; an interpolation clock controller to receive a second clock signal and produce multiple enable signals in order to enable the horizontal filter and the 2D image interpolator, wherein the second clock signal has a frequency independent of the frequency of the first clock signal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the technical field of image processing and, more particularly, to an image format conversion system.

2. Description of Related Art

The resolution of video source in a liquid crystal display television (LCD TV) is typically a constant. Accordingly, for a display on different resolution panels, image of a video source has to be scaled for being properly displayed on the different resolution panels. In this case, U.S. Pat. No. 5,739,867 has disclosed an upscaler for a display with an LCD panel.

FIG. 1is a block diagram of a typical scaler100. As shown inFIG. 1, the typical scaler100essentially replaces frame buffers with line buffers110,120,130. In addition, the operating clocks of deinterlacer140, FIFO150, vertical interpolator160and horizontal interpolator170are generated by applying an image input signal180to a frequency multiplier (not shown).

Since the frame buffers are replaced with the line buffers110,120,130, the die size becomes smaller. In addition, because the operating clock is derived from the frequency of the image input signal180, the phases of the operating clocks of the deinterlacer140, vertical interpolator160and horizontal interpolator170have a better synchronization in comparison with the phase of the image input signal180.

However, due to the line buffers110,120,130used in the typical scaler, the resolution of the image input signal180is limited. Namely, the image input signal180must have a horizontal resolution smaller than the available length of the line buffers110,120and130. Accordingly, the horizontal resolution of the image input signal180is gradually increased as the image format is frequently changed, and such a scaler cannot conform with the requirement of scaling operation on an image input signal with a new format.

Further, for electromagnetic interference (EMI) reduction, the clock signal is typically performed with a spread spectrum operation.FIG. 2is a schematic graph of a typical clock signal spread spectrum. As shown inFIG. 2(A), a clock signal before spreading presents a single-frequency signal in the operating frequency range. As shown inFIG. 2(B), the clock signal after spreading (spreading chips) presents a multi-frequency signal in the operating frequency range, which reduces the amplitude of the clock signal through the spread spectrum technique to thereby reduce the electromagnetic interference. However, owing to the frequency range of the clock signal is widen after spreading, the phase lock loop (PLL) takes more time to lock the frequency of an input signal, and even it cannot lock the frequency of the input signal. In this case, the difficulty in designing the PLL circuitry is thus increased. In addition, when the input signal is unsteady or the frequency range of the clock signal is overlarge after spreading, an abnormal picture possibly occurs.

Therefore, it is desirable to provide an improved image format conversion system to mitigate and/or obviate the aforementioned problems.

SUMMARY OF THE INVENTION

An object of the present invention is to provide an image format conversion system, which can perform a scaling operation on input signals with different image formats to thereby increase the added value on the system. The invention integrates the scaling operation and the deinterlacing operation into a 2D image interpolator to thereby save the memory use and the operational circuitry area.

Another object of the present invention is to provide an image format conversion system, which can overcome the abnormal picture caused by the clock signal spread spectrum in the prior art.

According to a feature of the invention, an image format conversion system is provided. The system includes a horizontal filter, a first first-in-first-out (FIFO), a 2D image interpolator, a second FIFO and an interpolation clock controller. The horizontal filter receives an image input signal with a frequency of a first clock signal in order to perform a filtering operation on the image input signal to thereby produce a horizontal filtering image signal. The first FIFO is connected to the horizontal filter in order to temporarily store the horizontal filtering image signal. The 2D image interpolator is connected to the first FIFO in order to perform a deinterlacing, a vertical interpolation and a horizontal interpolation operations on the horizontal filtering image signal to further produce a scaled progressive image signal. The second FIFO is connected to the 2D image interpolator in order to temporarily store the scaled progressive image signal. The interpolation clock controller is connected to the horizontal filter, the first FIFO, the 2D image interpolator and the second FIFO in order to receive a second clock signal and produce multiple enable signals to thereby enable the horizontal filter and the 2D image interpolator, wherein the second clock signal has a frequency independent of the frequency of the first clock signal.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 3is a block diagram of an image format conversion system300according to the invention. The system300includes a horizontal filter310, a first first-in-first-out (FIFO)320, a 2D image interpolator330, a second FIFO340, an interpolation clock controller350, an image buffer360and a clock synthesizer370.

The horizontal filter310receives an image input signal with a frequency of a first clock signal in order to perform a filtering operation on the image input signal to thereby produce a horizontal filtering image signal. The first FIFO320is connected to the horizontal filter310in order to temporarily store the horizontal filtering image signal.

The image input signal received by the horizontal filter310can be provided by an image data provider390. The image data provider390can be a network device or a storage device. The image data provider390also provides the first clock signal clk1to the horizontal filter310and the first FIFO320with the clock signal at operation.

The 2D image interpolator330is connected to the first FIFO320in order to perform deinterlacing, vertical interpolation and horizontal interpolation operations on the horizontal filtering image signal to thereby produce a scaled progressive image signal.

The second FIFO350is connected to the 2D image interpolator330in order to temporarily store the scaled progressive image signal.

The interpolation clock controller350is connected to the horizontal filter310, the first FIFO320, the 2D image interpolator330and the second FIFO340in order to receive a second clock signal clk2and produce multiple enable signals to thereby enable the horizontal filter310and the 2D image interpolator330. The second clock signal clk2has a frequency independent of the frequency of the first clock signal clk1.

The clock synthesizer370is connected to the first FIFO320, the 2D image interpolator330, the second FIFO340and the interpolation clock controller350. The clock synthesizer370is based on a third clock signal to synthesize the second clock signal clk2. The third clock signal is a system clock signal or a clock signal generated by an oscillator380.

The first FIFO320receives the first clock signal clk1and the second clock signal clk2respectively for providing the different clock domains. Thus, the 2D image interpolator330, the second FIFO340and the interpolation clock controller350can be operated at the frequency of the second clock signal clk2without causing an abnormal picture due to the clock signal is spread in the prior art.

FIG. 4is a block diagram of the horizontal filter310according to the invention. The horizontal filter310includes a pre-filter311, a down-sampler313, a first multiplexer315and a post-filter317.

The pre-filter311performs a pre-filtering operation on the image input signal to thereby produce a pre-filtered image input signal. The pre-filtering operation is executed by, for example, averaging five pixels of a line from the image input signal to thereby produce the pre-filtered image input signal.

The down-sampler313is connected to the pre-filter311in order to perform a downsampling operation on the pre-filtered image input signal to thereby produce a downsampled image input signal. The downsampling operation is executed by, for example, merging two pixels of a line of the pre-filtered image input signal to thereby produce the downsampled image input signal.

The first multiplexer315is connected to the downsampler313and the pre-filter311in order to depend on a first control signal to select the pre-filtered image input signal or the downsampled image input signal as an output of the first multiplexer315. When the downsampling operation is not required, the first control signal indicates that the pre-filtered image input signal is selected as the output of the first multiplexer315. Conversely, when the downsampling operation is required, the first control signal indicates that the downsampled image input signal is selected as the output of the first multiplexer315.

The post-filter317is connected to the first multiplexer315in order to perform a post-filtering operation on the output of the first multiplexer315to thereby produce the horizontal filtering image signal.

FIG. 5is a block diagram of the 2D image interpolator330according to the invention. The 2D image interpolator330includes a deinterlacer331, a vertical interpolator333and a horizontal interpolator335.

The deinterlacer331is connected to the first FIFO320and the image buffer360in order to perform a deinterlacing operation on the horizontal filtering image signal to thereby produce a progressive image signal. The deinterlacing operation can perform an interpolation operation on two lines3311,3313from the horizontal filtering image signal to thereby produce the progressive image signal.

The vertical interpolator333is connected to the deinterlacer331in order to perform a vertical interpolation operation on the progressive image signal to thereby produce a vertical scaling image signal. The vertical interpolation operation can perform an interpolation operation on two or more lines of the progressive image signal to thereby produce the vertical scaling image signal. The vertical interpolator333receives three lines3311,3313,3315provided by the deinterlacer331and produce the lines3317,3319after the interpolation operation to thereby produce the vertical scaling image signal. Alternatively, the vertical interpolator333can perform a vertical downscaling operation by selecting one from two pixels of the lines3311,3313or dividing an average of the pixels of the lines3311,3313by two to thereby produce the vertical scaling image signal.

The horizontal interpolator335is connected to the vertical interpolator333in order to perform a horizontal interpolation operation on the vertical scaling image signal to thereby produce the scaled progressive image signal. The horizontal interpolation operation is executed by, for example, performing an interpolation operation on the pixels of a line of the progressive image signal to thereby produce the scaled progressive image signal. Alternatively, the horizontal interpolator335can perform a horizontal downscaling operation by selecting one from two adjacent pixels of a line or dividing an average of the two adjacent pixels by two to thereby produce the scaled progressive image signal.

FIG. 6is a block diagram of the interpolation clock controller350according to the invention. The interpolation clock controller350includes a horizontal counter351, a vertical counter352, an input synchronization tracer353, a horizontal downsampling rate calculator354, a deinterlacing clock calculator355, a vertical interpolation rate calculator356and a horizontal interpolation rate calculator357.

The horizontal counter351is connected to the clock synthesizer370in order to count the second clock signal clk2to thereby produce a horizontal count signal.

The vertical counter352is connected to the clock synthesizer370in order to count the second clock signal clk2to thereby produce a vertical count signal.

The input synchronization tracer353is connected to the horizontal counter351and the vertical counter352in order to receive an external synchronization reset signal ext_sync_rst to accordingly reset the horizontal counter351and the vertical counter352.

The horizontal downsampling rate calculator354is connected to the horizontal counter351in order to produce a horizontal enable signal HEN1based on the horizontal count signal.

The deinterlacing clock calculator355is connected to the horizontal counter351and the vertical counter352in order to produce a deinterlacing enable signal VEN1based on the horizontal count signal and the vertical count signal.

The vertical interpolation rate calculator356is connected to the horizontal counter351and the vertical counter352in order to produce a vertical interpolation enable signal VEN2based on the horizontal count signal and the vertical count signal.

The horizontal interpolation rate calculator357is connected to the horizontal counter351and the vertical counter352in order to produce a horizontal interpolation enable signal HEN2based on the horizontal count signal and the vertical count signal.

FIG. 7is a schematic diagram of a data control according to the invention. As shown inFIG. 7, the image input signal includes Pixel1to Pixel10. The downsampler313performs a downsampling operation with a ratio of 2:1 on the image input signal. Namely, Pixel1or Pixel2is selected, or the values of Pixel1and Pixel2are averaged and divided by two. When the horizontal enable signal HEN1is at high voltage, the horizontal filter310outputs the horizontal filtering image signal to the first FIFO320.

The vertical interpolator333performs a vertical downscaling operation on Line1and Line2from the image buffer360by selecting Pixel2of Line1or Pixel2of Line2, or dividing a result by two, where the result is obtained by averaging the values of the pixels from Line1and Line2. When the vertical interpolation enable signal VEN2is at high voltage, the image buffer360outputs the scaled progressive image signal to the second FIFO340.

As cited, the scaler in the prior art has an operating clock obtained by passing the frequency of an image input signal through a frequency doubler (not shown), and accordingly it is difficult to determine whether the scaler internally performs a spreading operation on the operating clock or not. Once the frequency of the image input signal is spread and the scaler internally performs the spreading operation again, it makes the spectrum of the operating clock become relatively large, and further the frequency of the input signal is not easily locked by the internal PLL circuit of the scaler, resulting in causing an abnormal picture. Conversely, when the frequency of the image input signal is not spread by the scaler, it is likely to cause the electromagnetic interference (EMI). The invention uses the clock synthesizer370to produce the second clock signal clk2for the 2D image interpolator330, the second FIFO340and the interpolator350, and to perform the spreading operation on the second clock signal clk2. Accordingly, the problems of the EMI and whether or not the spreading operation is performed in the prior art are eliminated.

In addition, the invention uses the image buffer360, and thus the limited resolution of the image input signal that is caused by the line buffers110,120,130of the scaler in the prior art can be improved. The invention uses the first FIFO320and the second FIFO340to separate the operating clock of the image format conversion system300from that of the image data provider390at the front end or that of the panel (not shown) at the rear end to thereby increase the system stability.

For eliminating the cost increase caused by the large sizes of the first FIFO320and the second FIFO340, the invention uses the downsampler313to perform the downsampling operation on an image signal to thereby reduce the sizes of the first FIFO320and the second FIFO340. Further, the scaling operation and the deinterlacing operation are integrated into the 2D image interpolator330to thereby reduce the size of the image buffer360and save the operational circuit area.