Motor driving circuit, cooling apparatus and electronic device using the same

A driving circuit of an electric motor includes: a PWM input pin for externally receiving an input pulse modulation signal with an input duty cycle; a duty cycle to digital converter for receiving and converting the input pulse modulation signal into a first digital value; a slope setting pin for receiving information indicative of a slope of an output duty cycle corresponding to the input duty cycle; a slope acquisition unit for acquiring a second digital value corresponding to the information indicative of the slope; a duty cycle computation unit for generating a linearly increased duty cycle instruction value corresponding to the first digital value by referring to the slope; a digital pulse width modulator for generating a controlling pulse having the output duty cycle corresponding to the duty cycle instruction value; and an output circuit for driving the electric fan motor in accordance with the controlling pulse.

CROSS REFERENCE TO RELATED APPLICATIONS

The present invention claims priority under 35 U.S.C. § 119 to Japanese Application No. 2014-096314, filed May 7, 2014, the entire content of which is incorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates to an electric motor driving device.

BACKGROUND

Present high-speed requirements for personal computers and workstations have forced an increase in operating speed of computational large scale integrated (LSI) circuits, such as central processing units (CPUs) or digital signal processors (DSPs). When the operating speed and the instant clock frequency of an LSI circuit increases, the thermal dissipation of the LSI circuit also increases. Accordingly, the LSI circuit or the peripheral circuits may fail to perform normal operations due to such thermal dissipation. Therefore, providing a proper cooling technique for the thermal dissipation of the LSI circuit is an urgent problem in this field.

An example for cooling an LSI circuit is a ventilation cooling method that implements cooling fans. According to the ventilation cooling method, the cooling fans can be installed on the opposite side of the surface of the LSI circuit, for example, so that the cooling fans can blow the cold air on the surface of the LSI circuit. During the cooling process of the LSI circuit, the ambient air temperature of the LSI circuit is monitored, and the rotating speed of the cooling fan can be adjusted in accordance with the monitored temperature that adjusts the cooling speed.

FIGS. 1A and 1Bare the circuit diagrams illustrating the driving circuit of an electric fan motor and the peripheral circuits in accordance with the present invention. InFIGS. 1A and 1B, the driving integrated circuits (ICs)200have the same configuration but the peripheral circuits of the driving ICs200are different.

A power-supply pin9(i.e. VCC pin) is connected to an input supply voltage VDDvia a diode D1to prevent reverse current. In addition, the VCC pin9is connected to a zener diode ZD1used for overvoltage protection and a capacitor C2used for signal smoothing. A ground pin14is connected to the ground (i.e. GND). An output pin of an H bridge circuit212is connected to an electric fan motor6via a pin6(i.e. OUT2) and a pin8(i.e. OUT1). In addition, the pin on the lower part of the H bridge circuit212is connected to a pin7(i.e. RNF). It is noted that the pin numerals are numbered for the sake of brevity, and is irrelevant to the layout of the pins. A control logic circuit208generates a pulse signal S1, and the pulse signal S1is a pulse width modulated signal. A pre-driving circuit210switches the H bridge212according to the pulse signal S1.

The electric fan motor6is a brushless direct current (DC) electric motor. The driving IC200in combination with the peripheral circuit components are configured as a driving circuit for driving the electric fan motor6in PWM. A Hall sensor8is installed nearby the electric fan motor6for detecting the rotor position.

The Hall biasing circuit204generates a Hall bias voltage VHB, and the Hall bias voltage VHBis supplied to the Hall sensor8via a pin3. Hall signals H− and H+ generated by the Hall sensor8are supplied to a pin2and the pin3of the driving IC200respectively. A Hall comparator202compares the Hall signals H− and H+, and generates a pulse signal S2indicating the rotor position to a control logic circuit208. The control logic circuit208and the pulse signal S2are arranged to synchronously change the driving phases of the H bridge circuit212.

A resistor RNFis connected between the H bridge circuit212and the ground line VSS. In other words, the resistor RNFis connected between pin7and a ground line. A detection voltage proportional to the current flowing to the electric fan motor6is generated across the resistor RNF. A detection voltage VNFis supplied to a pin5via a resistor-capacitor (RC) filter. A current clamping comparator206compares the detection voltage VNFwith a specific voltage Vc1. The voltage Vc1determines the upper bound current flowing through the electric fan motor6. If the output of the current clamp comparator206is determined to be a high voltage level, the control logic circuit208changes the logic value of the pulse signal S1to stop flowing current to the electric fan motor6.

An oscillator220generates a periodic carrier voltage OSC having a specific frequency. The carrier voltage OSC has a sawtooth waveform or a triangle waveform. A PWM comparator216compares a voltage VMINon a pin12(i.e. MIN) with the carrier voltage OSC. The output of the PWM comparator216has a duty cycle corresponding to the voltage VMINon the pin12.

Similarly, a PWM comparator218compares a voltage VTHon a pin11(i.e. TH) with the carrier voltage OSC. The output of the PWM comparator218has a duty cycle corresponding to the voltage VTHon the pin11.

The control logic circuit208combines the output pulses of the PWM comparators216and218in order to generate the pulse signal S1. The larger duty cycle in the output pulses of the PWM comparators216and218becomes the duty cycle of the pulse signal S1. In other words, the voltage on the pin12is used to set the lower bound of the duty cycle (i.e. the minimum duty cycle) of the pulse signal S1.

A reference voltage source214generates a specific reference voltage VREF, and the specific reference voltage VREFis outputted to the external circuit via a pin10(i.e. REF). Resistors R11and R12divide the reference voltage VREFin order to generate a divided voltage on the input to the pin12(i.e. MIN). In other words, the voltage VMINon the pin12can be set by the resistances of the external resistors R11and R12. Thus, the minimum duty cycle of the pulse signal S1can also be set.

The PWM input pin is arranged to input a PWM signal with the duty cycle corresponding to the target rotation number of the electric fan motor6. InFIG. 1A, an input PWM signal is connected to the TH pin via an inverter10.

InFIG. 1B, after an input PWM signal is inverted by an inverter10, the inverted input PWM signal is smoothed by an RC filter12, and is then inputted to the TH pin.

FIGS. 2A and 2Bare timing diagrams illustrating the operating waveforms of the driving IC200inFIGS. 1A and 1Brespectively.

Referring toFIG. 2Ain conjunction withFIG. 1A, the operation of the driving IC200is described as follows.

The TH pin (i.e. pin11) of the driving IC200ofFIG. 1Ais arranged to input the input pulse signal VTH, wherein the input pulse signal VTHcorresponds to the inverted input PWM signal. The high voltage level for the pulse signal VTHis higher than the peak value of the carrier voltage generated by the internal oscillator, and the low voltage level for the pulse signal VTHis lower than the valley value of the carrier voltage generated by the internal oscillator. By comparing the carrier voltage with the pulse voltage VTH, the output pulse signal of the PWM comparator218has the same duty cycle as the duty cycle of the pulse voltage VTH.

FIG. 2Ashows the waveforms of H−>H+, the output OUT1having the first phase is changed, and the output OUT2having the second phase is fixed at the low voltage level. The switching duty cycle of the output OUT1is the same as VTH, and thus the switching duty cycle of the output OUT1is the same as the duty cycle of the original input PWM signal. In addition, as VMINequals to VREFand is higher than the peak value of the carrier voltage in this embodiment, the output of the PWM comparator216does not affect the output OUT1.

Therefore, when the PWM signal has a larger duty cycle, the torque (i.e. the rotation number) of the electric fan motor6is also higher.

In addition, referring toFIG. 2Ain conjunction withFIG. 1B, the operation of the driving IC200is described as follows.

The TH pin (i.e. pin11) of the driving IC200ofFIG. 1Bis arranged to input the DC voltage VTHafter the DC voltage VTHis smoothed by a filter. When the output OUT1equals the lower voltage of VMINand VTH, the output OUT1has the duty cycle corresponds to the comparison result of the carrier voltage.

Therefore, when the PWM signal has a larger duty cycle, the torque (i.e. the rotation number) of the electric fan motor6is also higher. In addition, the smallest torque, i.e. the minimum rotation number, can be set by the voltage VMIN.

Hence, according to the driving IC200inFIG. 1, the TH pin can be inputted by DC voltage, the TH pin can also be inputted by pulse signals. Therefore, the present embodiments provide a high flexibility of circuit components for the designer.

BACKGROUND TECHNICAL LITERATURE

Patent Literatures

BRIEF SUMMARY OF THE INVENTION

Problem to be Solved in the Present Invention

However, the driving IC200has the following problems.

In the platform ofFIG. 1A, there are limitations for the high voltage level and low voltage level of the TH pin. That is, the high voltage level of the TH pin has to be higher than the peak value of the carrier voltage OSC, and the low voltage level has to be lower than the valley value of the carrier voltage OSC. As a result, the amplitude of the input pulse signal of the TH pin has to be carefully designed.

Moreover, the duty cycle (input duty cycle) of the input PWM signal is the same as the duty cycle of the output OUT1(i.e. OUT2). Thus, the relation between input and output is fixed and unchangeable.

In the platform ofFIG. 1B, the relation (i.e. slope) between the input duty cycle and the output duty cycle can be adjusted by using a filter12. However, this will increase the number of components and the cost. Moreover, having a large number of components makes it difficult to minimize the device size.

In addition, the variation range of the DC voltage of the TH pin is the variation range of the output duty cycle. To improve the precision of the output duty cycle with respect to the DC voltage, the difference between the peak value and valley value, i.e., the amplitude, of the carrier voltage OSC should be larger. Therefore, the voltage source VDDis also higher.

Therefore, one of the objectives of the present embodiment is to provide an electric motor driving circuit with low cost, small area, and the relation between the input duty cycle and the output duty cycle is adjustable.

Technical Solution

According to an embodiment of the present invention, a driving circuit of an electric motor is provided. The driving circuit is applicable for driving an electric fan motor by pulse width modulation (PWM). The driving circuit comprises: a PWM input pin for externally receiving an input pulse modulation signal with an input duty cycle; a duty cycle to digital converter for receiving the input pulse modulation signal and converting the input pulse modulation signal into a first digital value corresponding to the input duty cycle; a slope setting pin for receiving information indicative of a slope of an output duty cycle corresponding to the input duty cycle of the electric motor driving circuit; a slope acquisition unit for acquiring a second digital value corresponding to the information indicative of the slope; a duty cycle computation unit for generating a linearly increased duty cycle instruction value corresponding to the first digital value by referring to the slope corresponding to the second digital value; a digital pulse width modulator for generating a controlling pulse having the output duty cycle corresponding to the duty cycle instruction value; and an output circuit for driving the electric fan motor in accordance with the controlling pulse.

According to the embodiment, the input pulse modulation signal is inputted to the PWM input pin via the duty cycle to digital converter. The slope of the output duty cycle in relation to an input duty cycle can be externally set via the slope setting pin and the slope acquisition unit. The arrangement can lower cost and area, and the relation between the input duty cycle and the output duty cycle can also be adjusted.

The slope setting pin receives an analog DC voltage indicative of the slope, and the slope acquisition unit comprises a first A to D converter for converting the analog DC voltage of the slope setting pin into the second digital value.

The slope setting pin receives a serial or parallel digital data indicative of the slope, and the slope acquisition unit comprises: an interface circuit for receiving the digital data; and a storage device for storing the second digital value corresponding to the digital data.

The slope setting pin receives a second digital value indicative of the slope, and the slope acquisition unit also comprises a non-volatile storage device storing the second digital value.

The electric fan motor driving circuit further comprises: a DC input pin, an analog DC input voltage, and a second analog to digital (A/D) converter that converts the DC voltage from the DC input pin to a third digital value. The duty cycle computation unit also clamps the duty cycle instruction value by using the third digital value as a lower bound.

Therefore, the lowest rotation number of the electric fan motor can be arbitrary controlled. Moreover, the electric fan motor driving circuit can also be used in the platform design that controls the rotation number by using an analog input DC voltage.

When setting the output duty cycle as OUTDUTY, setting the input duty cycle as INDUTY, setting the slope as SLP, setting the lower bound of the duty cycle instruction value as MIN, setting a parameter as OFS, and setting a maximal value selection function as max (F), the duty cycle computation unit computes the duty cycle instruction value in accordance with the following equation:
OUTDUTY=SLP×max(INDUTY, MIN)+OFS

When setting the output duty cycle as OUTDUTY, setting the input duty cycle as INDUTY, setting the slope as SLP, sets the lower bound of the duty cycle instruction value as MIN, setting a parameter as OFS, and setting a maximal value selection function as max (F), the duty cycle computation unit computes the duty cycle instruction value in accordance with the following equation:
OUTDUTY=max(SLP×INDUTY+OFS, MIN).

The parameter OFS can be obtained by the constant K in accordance with any of the following equations:
OFS=100×(K−SLP).
OFS=100×K.
OFS=100×(SLP−K).

The constant can also be set as K=1. The constant K can also be set external to the electric motor driving circuit.

The duty cycle to digital converter comprises: a voltage level converting circuit, after a value of the input pulse modulation signal is converted into a binary value comprising 1 and 0, the voltage level converting circuit multiplies the input pulse modulation signal comprised of the binary value by a factor of 2L, where L is a natural number; and a digital low-pass filter, for filtering an output data from the voltage level converting circuit and generating a first digital value.

The digital low-pass filter is a first order IIR (infinite impulse response) filter comprising an adder, a delay circuit, and a factor circuit orderly connected in series. The adder is arranged to add up the output data of the voltage level converting circuit and an output data of the delay circuit, and to subtract an output data of the factor circuit, the delay circuit delays an output data of the adder, and the factor circuit multiplies an output data of the delay circuit by a factor of 2−n, wherein n is a natural number.

The number n is determined by a method such that an amplitude of an output data of the factor circuit is less than 1.

The electric motor driving circuit can also be integrated onto a semiconductor substrate.

The term “integrated” means the required components of the circuit are formed on a semiconductor substrate, or the required components of the circuit are integrated into a single chip. A portion of resistors or capacitors can be installed external to the semiconductor substrate for adjusting the circuit parameters.

By integrating the circuits into a single IC, the size of the circuits can be reduced, and the characteristic of the circuit components can be kept intact.

According to another embodiment of the present invention, a cooling device is provided. The cooling device comprises an electric fan motor and any driving circuit of the above embodiments, for driving the electric fan motor.

According to another embodiment of the present invention, is electronic device. The electronic device comprises a processor and the above cooling device for cooling the processor.

Effects of the Present Invention

In accordance with the embodiment, the cost and chip area are reduced, and the relation between the input duty cycle and the output duty cycle is adjustable.

DETAILED DESCRIPTION

FIG. 3is a diagram illustrating a cooling device2comprising the driving IC100in accordance with an embodiment. The cooling device2may be installed in devices, such as desktop PC, laptop notebook, workstation, gaming console, and audio device, and projecting device and so on, to cool down the CPU (Central Processing Unit), GPU (Graphics Processing Unit), and power supply, etc. The cooling device2comprises: an electric fan motor6installed opposite to the cooling target; and a driving device9for driving the electric fan motor6.

According to the embodiments, the driving device9comprising the driving IC100and the peripheral components. The components of the driving device9are installed on a shared PCB (printed circuit board).FIG. 3only includes a part of the peripheral components required in describing the operation of the driving IC100.

The driving IC100comprising a duty cycle to digital converter102, a slope acquisition unit104, a second analog to digital converter106, a duty computation unit108, a digital pulse width modulator110, an output circuit120, and a reference voltage source214, wherein all the components are integrated in an functional IC on a semiconductor substrate.

The power pin10(also called VCC pin) is inputted by an input supply voltage VDD. The ground pin16(also called GND pin) is inputted by a ground voltage VSS. The reference voltage source214generates a stabilized voltage having a specific voltage level VREF, which is outputted on the reference voltage pin11(also called REF pin). The reference voltage VREFis used in the driving IC100and is also used in the external of the driving IC100. Moreover pins6-9inFIG. 3correspond to pins5-8inFIG. 1respectively.

The duty cycle to digital converter102, the slope acquisition unit104, the second analog to digital converter106, the duty cycle computation unit108, and the digital pulse width modulator110are arranged to receive an input PWM signal SPWMwhich was pulse width modulated externally, and to generate a controlling pulse SCNThaving a duty cycle (i.e. the output duty cycle OUTDUTY) corresponding to the duty cycle (i.e. the input duty cycle INDUTY) of the input PWM signal SPWM.

The output circuit120drives the electric fan motor6in accordance with the controlling pulse SCNT. In general, the present embodiment is arranged to alternatively select the outputs OUT1and OUT2according to the output of the Hall comparator202and to switch the output according to the controlling pulse SCNTat the same time.

The output circuit120comprising the Hall comparator202, a current clamp comparator206, a control logic circuit208, a pre-driving circuit210, an H bridge circuit212, and a reference voltage source214. The connection of the components can be referred toFIG. 1, and the detailed description is omitted here for brevity. Moreover, the implementation of the output circuit120is not limited to the implementation ofFIG. 3, the output circuit120may have other configurations. InFIG. 3, the Hall sensor8is installed externally. However, the Hall sensor8may be installed in the driving IC100.

The generating the controlling pulse SCNTis described as follows.

The PWM input pin5(i.e. the PWM pin) is arranged to externally receive an input pulse modulated signal SPWMhaving an input duty cycle INDUTY. The duty cycle to digital converter102receives the input pulse width modulation signal SPWMand converts the input pulse width modulation signal SPWMinto a first digital value DPWMcorresponding to the input duty cycle INDUTY.

The slope SLP of an output duty cycle OUTDUTY corresponding to the input duty cycle INDUTY of the driving IC100can be externally set. The slope setting pin4(also called SLOPE pin) is arranged to receive the information indicating the slope. The slope acquisition unit104receives the information indicative of the slope SLP and acquires a second digital value (DSLP) corresponding to the slope SLP.

In this embodiment, the SLOPE pin is arranged to receive an analog DC input voltage VSLOPEhaving a voltage level corresponding to the slope SLP. Therefore, the slope acquisition unit104further comprises the first analog to digital converter105used for converting the DC voltage VSLOPEinto a digital value.

For the example of the second analog to digital converter106, when VSLOPE=VREF, then SLP=2, when VSLOPE=VREF/2, then SLP=1, and when VSLOPE=VREF/4, then SLP=1/2.

The duty cycle computation unit108generates a linearly increased duty cycle instruction value DDUTYcorresponding to a first digital value DPWMby referring to the slope SLP corresponding to a second digital value DSLP. The duty cycle instruction value DDUTYis the data indicating the output duty cycle OUTDUTY of the controlling pulse signal SCNT. The digital pulse width modulator110generates the controlling pulse SCNThaving the output duty cycle OUTDUTY corresponding to the duty cycle instruction value DDUTY.

The operation of the duty cycle computation unit108is described as follows. For example the duty cycle computation unit108computes the value (i.e. the output duty cycle OUTDUTY) of the duty cycle instruction value DDUTYin accordance with equation (1):
OUTDUTY=SLP×INDUTY+100×(1−SLP)  (1)

In which, when the value of equation (1) is negative, OUTDUTY=0. It is noted that OUTDUTY≥0. The equation (1) can be calculated under the condition of 100% where INDUTY=100% and OUTDUTY=100%.

The driving IC100can be externally set the lowest rotation number of the electric fan motor6. The DC input pin12(also called MIN pin) is arranged to receive the analog DC input voltage VMIN. The second analog to digital converter106converts the second DC voltage VMINinto a third digital value DMIN. The duty cycle computation unit108clamps the duty cycle instruction value DDUTYby using the third digital value DMINas a lower bound.

In such case, the equation (2) can be obtained by directly amending the equation (1). MIN represents the minimum duty cycle of the digital value DMIN:
OUTDUTY=SLP×max(INDUTY, MIN)+100×(1−SLP)  (2)
Max is a function for selecting the larger value of the INDUTY and MIN.

It is noted that the present invention is not limit to the implementation of the duty cycle computation unit Those skilled in the art are appreciated to understand that the duty cycle computation unit108can be implemented by a combination of product-sum arithmetic unit, multiplier, and adder, etc.

FIG. 4is a diagram illustrating the relationship between the input and the output of the duty cycle computation unit108. The horizontal axis represents the input duty cycle INDUTY, and the vertical axis represents the output duty cycle OUTDUTY. The curve (i) represents the characteristic when SLP=½, the curve (ii) represents the characteristic when SLP=1, and the curve (iii) represents the characteristic when SLP=2.

In addition, the input and output characteristics of the duty cycle computation unit108can be determined under the condition of 0% where INDUTY=0% and OUTDUTY=0%. The input and output characteristics of the duty cycle computation unit108can also be determined under the condition of 50% where INDUTY=50% and OUTDUTY=50%.

FIG. 5is a circuit diagram illustrating a configuration of the duty cycle to digital converter102. The duty cycle to digital converter102comprises a voltage level switching circuit150and a digital filter152.

The high level of the input PWM signal SPWMis set to 1, and the low level is set to 0. Therefore, the input PWM signal SPWMcan be inputted to the input pin of the CMOS (Complementary Metal Oxide Semiconductor). The voltage level switching circuit150multiplies the input PWM signal being converted to 1 and 0 by a factor 2L. When L=7, the values of 1 and 0 of the input PWM signal SPWMare converted to the values of 128 and 0 respectively, and then are transmitted to the subsequent digital filter152.

The digital filter152is a first order IIR (infinite impulse response) low-pass filter comprising an adder153, a delay circuit154, and a factor circuit156orderly connected in series.

The delay circuit154has a bit width of (L+n), the delay circuit154is arranged to synchronously delay the output data of the adder circuit153by a delay time Tclkaccording to the clock signal CLK having a period of Tclk.

The adder153multiplies the output data of the delay circuit154by a factor of 2−n. The constant n is used to determine the frequency response of the low-pass filter. The adder153and the factor circuit156further comprise a bit shifter that shifts the input data to the right by n bits.

The adder153is arranged to add up the output data of the voltage level converting circuit150and an output data of the delay circuit154, and to subtract an output data of the factor circuit156. The computing result is then outputted to the delay circuit154.

FIGS. 6A and 6Bare diagrams illustrating the operation of the PWM duty cycle to digital converter inFIG. 5.FIG. 6Arepresents the first digital value DPWMwhen the input signal PWM has a duty cycle of 50%. The response gain and the amplitude change of the feedback loop can be adjusted by changing the value of n.

The frequency fax of the clock signal CLK is described in this paragraph. When the duty cycle of the input PWM signal SPWMis controlled by L bits, it is better to use the precision level capable of converting the value smaller than ½Lto convert the input PWM signal SPWM. For example, when the duty cycle is converted by L=7 bits (i.e. 0 to 127), the precision level should be under 1/128≈1%. Therefore, when the carrier frequency fPWMof the input PWM signal SPWMis 28 KHz, and the frequency fCLKof the clock signal CLK is 3.6 MHz, i.e. 2L(i.e. 128) times higher than 28 KHz, then no data will be missed. Accordingly, a first digital value DPWMcan be generated in each cycle of the input PWM signal. Therefore, the frequency splitting can be avoided.

The factor n of the filtering process is described in this paragraph.FIG. 6Bis a diagram illustrating the low-pass filtering characteristic of the duty cycle to digital converter102. In order to limit the amplitude of the first digital value DPWMto fall within one pitch, the target gain G should be G= 1/128=−42 dB. When n=12, and when the carrier frequency fPWMof the input signal PWM is 21 KHz, a filtering rate of −38.5 dB can be achieved. If the carrier frequency fPWMis higher, then a filtering rate smaller than −42 dB can be achieved.

The above paragraphs have described the configuration of the driving IC100. The operation of the driving IC100is described in the following paragraphs.

The driving IC100can be used to control a variety of different platforms.FIGS. 7A and 7Bare circuit diagrams illustrating the cooling devices2applied in different platforms respectively. The peripheral circuits of the cooling devices2are different inFIGS. 7A and 7B.

The platform inFIG. 7Ais first described. In the cooling device2aof the first platform, the input PWM signal SPWMgenerated by a CPU or a microprocessor external to the driving IC100is inputted to the PWM pin (i.e. pin5) via the resistor R21.

The VCC pin is connected to the input supply voltage VDDvia a diode D1to prevent reverse current. In addition, the VCC pin is connected to a zener diode ZD1used for overvoltage protection and a capacitor C2used for signal smoothing.

The REF pin (i.e. pin11) is connected to the smoothing capacitor C11. The output reference voltage VREFis generated at the REF pin by the internal reference voltage source214. The resistors R31and R32are arranged to divide the reference voltage VREFon the REF pin to generate the Hall bias voltage VHBof the Hall-effect transducer8.

Resistors R41and R42are arranged to divide the reference voltage VREFto generate a divided voltage to the SLOPE pin (i.e. pin4). Resistors R51and R52are arranged to divide the reference voltage VREFto generate a divided voltage to the MIN pin (i.e. pin12).

The above paragraphs have described the configuration of the cooling device2a.

According to the cooling device2a, the slope of input and output characteristics inFIG. 4can be arbitrarily set by the voltage dividing ratio of the resistors R41and R42. Moreover, the minimum rotation number of the electric fan motor6can be arbitrarily set by the voltage dividing ratio of the resistors R51and R52.

The benefit of the cooling device2abecomes obvious by comparing theFIGS. 1A and 1B. As shown inFIG. 1A, the interface circuit used for receiving the input PWM signal requires an inverter10. As shown inFIG. 1B, the interface circuit used for receiving the input PWM signal requires an inverter10and a low-pass filter12. Furthermore, in the cooling device2aofFIG. 7A, the interface circuit requires only the resistor R21, therefore the required components of the circuit can be reduced significantly.

In the platform ofFIG. 1A, the high voltage level and low voltage level inputted to the TH pin are limited. However, inFIG. 7A, the amplitude of the input PWM signal SPWMis not limited.

In the platform inFIG. 1B, the variation range of the DC voltage on the TH pin corresponds to the variation range of the output duty cycle. To increase the accuracy of the output duty cycle with respect to the DC voltage, the difference between the peak value and the valley value, i.e., the amplitude, of the carrier voltage OSC should be larger. Therefore, the voltage source VDDis also higher

On the other hand, in the platform ofFIG. 7A, the duty cycle INDUTY of the input PWM signal is directly converted into a digital value by the duty cycle to digital converter102, and the pulse width modulated control signal SCNTis generated in the digital domain. Thus, there is no need to increase the power source voltage VDD, and the power consumption can be reduced.

In addition, in the embodiment of the driving IC100, the rotation number corresponding to the analog DC voltage can also be controlled. In the platform ofFIG. 7B, the DC pin is arranged to externally receive the analog input DC voltage VDCindicative of the rotation number of the electric fan motor6.

The input DC voltage VDCis inputted to the MIN pin via the resistor R61. The resistor R62is installed between the REF pin and the DC pin. A diode D2and a resistor R63are serially connected between the REF pin and the DC pin for clamping the voltage on the MIN pin. In this platform, the PWM pin is connected to the ground via the resistor R21.

The above paragraphs describe the configuration of the cooling device2bas shown inFIG. 7B. In the cooling device2b, the PWM pin is connected to the ground. Therefore, the output DPWMof the duty cycle to digital converter102is zero. In addition, the output DMINof the second analog to digital converter106is obtained by converting the input DC voltage VDCto a digital value. Therefore, given that DMIN>DPWM, and MIN>INDUTY in equation (2), the following equation (3) can be obtained:
OUTDUTY=SLP×MIN+100×(1−SLP)  (3)

Accordingly, in the cooling device2binFIG. 7(b), the rotation number of the electric fan motor6can be controlled by the input DC voltage VDC.

Therefore, the driving IC100in the embodiment can be used in a platform that controls the rotation according to the PWM signal, and can be used in a platform that controls the rotation according to the DC voltage. In other words, the driving IC100provides the users with the freedom of selectively controlling different platforms.

The application of the cooling device2is described in the following paragraphs.FIG. 8is a diagram illustrating a sectional view for a PC comprising a cooling device2. The PC500comprises a housing502, a CPU504, a motherboard506, a heat sink508, and a plurality of cooling devices2.

The CPU504is installed on the motherboard506. The heat sink508is securely installed onto the upper surface of the CPU504. A cooling device2-1is installed opposite to the heat sink508and circulates cool air onto the heat sink508. The cooling device2-2is installed on the back side of the housing502, and circulates air to the inside of the housing502from the outside.

In addition to the PC500ofFIG. 8, the cooling device2can also be used in a workstation, a laptop notebook, a TV set, a refrigerator, or other electronic equipment.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should understand the given embodiment is exemplary. Other alternative embodiments can be formed with different combinations of the consisting elements and/or processes. Those alternative embodiments do not depart from the spirit and scope of the present disclosure.

A first alternative embodiment is as follows. The minimum rotation number for an electric fan motor6which is determined by equation (2) has been described in the above embodiment. However, the present invention is not limited to the above embodiment. A more generalized equation (2a) can also be applied as follows:
OUTDUTY=SLP×max(INDUTY, MIN)+OFS(2a)

OFS is a parameter, and the parameter OFS can be determined by a constant K in conjunction with one of the following equations (4a)˜4(c).
OFS=100×(K−SLP)  (4a)
OFS=100×K(4b)
OFS=100×(SLP−K)  (4c)

The constant K can be set by a serial or a parallel interface, or externally set by the input pin of the driving IC100. The constant K can also be a fixed value. In addition, the equation (2) is the same as the equation (4a) under the condition of K=1.

A second alternative embodiment is as follows. The minimum rotation number for an electric fan motor6which is determined by equation (2) has been described in the above embodiment. However, the present invention is not limited to the above embodiment. An equation (5) can also be applied as follows:
OUTDUTY=max(SLP×INDUTY+OFS, MIN)  (5)

OFS can be obtained by one of the above equations (4a)˜4(c). Equation (2) can be understood as clamping the input duty cycle INDUTY by using MIN as the lower bound. Therefore, equation (5) can be understood as clamping the output duty cycle OUTDUTY by using MIN as the lower bound.

A third alternative embodiment is as follows. The driving of the electric fan motor as a single-phase driving electric motor has been described in the above embodiment. However, the present invention is not limited to the above embodiment. The present invention can be applied for driving other type of electric motors.

A fourth alternative embodiment is as follows. The configuration of inputting the analog DC voltage to the SLOPE pin has been described in the above embodiment. However, the present invention is not limited to the above embodiment. The SLOPE pin can also be inputted by a digital data indicative of the information of the slope.FIGS. 9A and 9Bare circuit diagrams illustrating a partial of the driving IC in accordance with the fourth alternative embodiment.

The driving IC100ainFIG. 9Acomprises one of the serial interface, such as an I2C (Inter IC) interface. In such case, the interface pin (I/F, interface), which is connected to the serial bus, is the SLOPE pin. In addition to other input data, the pin is also arranged to receive the serial digital data DSLOPEindicative of the slope SLP. In the driving IC100, the slope acquisition unit104acomprises an interface circuit130and a storage circuit132. The interface circuit130receives the digital data DSLOPEindicative of the slope SLP. The storage circuit132is a buffer device for storing the second digital value DSLPcorresponding to the digital value. It is noted that the serial interface can also be replaced with the parallel interface.

The driving IC100binFIG. 9Bcomprises a non-volatile storage device that can be externally accessed. The SLOPE pin is arranged to receive the digital data DSLOPEindicative of the slope SLP. In such case, the slope acquisition unit104bcan be implemented by the non-volatile storage device134. The non-volatile storage device134is a writable ROM (Read Only Memory) for storing the second digital value DSLPreceived by the SLOPE pin. The non-volatile storage device134can also be an OTP (One Time Programmable) ROM (Read Only Memory) that can be programmed by software, or an EEPROM (Electrically Erasable Programmable Read-Only Memory), etc.

A fifth alternative embodiment is as follows. The components of the driving IC100can be integrated into an integrated circuit, or separated into different integrated circuit blocks. Furthermore, some components of the driving IC100can be discrete circuits. The integration degree of the circuits is depended on the cost, circuit area, or functionality, etc.