System, method, and computer program product for scheduling tasks associated with continuation thread blocks

A system, method, and computer program product for scheduling tasks associated with continuation thread blocks. The method includes the steps of generating a first task metadata data structure in a memory, generating a second task metadata data structure in the memory, executing a first task corresponding to the first task metadata data structure in a processor, generating state information representing a continuation task related to the first task and storing the state information in the second task metadata data structure, executing the continuation task in the processor after the one or more child tasks have finished execution, and indicating that the first task has logically finished execution once the continuation task has finished execution. The second task metadata data structure is related to the first task metadata data structure, and at least one instruction in the first task causes one or more child tasks to be executed by the processor.

FIELD OF THE INVENTION

The present invention relates to task management, and more particularly to hardware and software scheduling mechanisms for tasks associated with continuation thread blocks.

BACKGROUND

Programming tasks are typically implemented by generating a data structure in a memory that includes information associated with instructions and data to be processed by those instructions. Some tasks may be configured to launch child tasks that complete auxiliary work related to the task. The task may be stalled while the child work is completed. The task saves the state related to the task, which may be restored at some point in the future once the child task has completed the auxiliary work.

However, conventional mechanisms associated with related tasks are not efficient at avoiding deadlock conditions. Sometimes, too many child threads may be launched such that resources are starved that don't allow child tasks to finish executing. Too many thread blocks may be active and resident in the processor, causing the active tasks to stall on completion of the child tasks, which in turn cannot be executed because the active tasks have locked all available resources. Thus, there is a need for addressing this issue and/or other issues associated with the prior art.

SUMMARY

A system, method, and computer program product for scheduling tasks associated with continuation thread blocks is described. The method includes the steps of generating a first task metadata data structure in a memory, generating a second task metadata data structure in the memory, executing a first task corresponding to the first task metadata data structure in a processor, generating state information representing a continuation task related to the first task and storing the state information in the second task metadata data structure, executing the continuation task in the processor after the one or more child tasks have finished execution, and indicating that the first task has logically finished execution once the continuation task has finished execution. The second task metadata data structure is related to the first task metadata data structure, and at least one instruction in the first task causes one or more child tasks to be executed by the processor.

DETAILED DESCRIPTION

A hardware scheduling mechanism for a multi-threaded processor is described below. The hardware scheduling mechanism provides a means to implement task scheduling, including out-of-order execution of tasks, prioritization of tasks, and pre-emption of tasks. A task is associated with a task metadata data structure that encapsulates the task state necessary for configuring a processing unit to complete some subset of work (i.e., a program kernel configured to process data). In one embodiment, a central processing unit (CPU) is coupled to a parallel processing unit (PPU) and the PPU is configured to execute one or more tasks. The tasks are written to a memory accessible by the PPU by either a device driver executing on the CPU or predecessor tasks executed on the PPU. In order to launch a task on the PPU, a method call is sent to the PPU that points to a task metadata data structure in the memory. The PPU then loads the task state defined by the task metadata data structure from the memory and launches the task on a processing unit of the PPU.

FIG. 1illustrates a flowchart of a method100for scheduling tasks associated with continuation thread blocks, in accordance with one embodiment. At step102, a first task metadata data structure is generated in a memory. A task data structure comprises a plurality of bits representing one or more fields that encapsulate state information relating to a task. At step104, a second task metadata data structure is generated in the memory. The second task metadata data structure is related to the first task metadata data structure and can store state information for one or more continuation thread blocks associated with a continuation task. A continuation task represents work comprising one or more instructions that are dependent on at least one intermediate value generated by one or more child tasks launched by the first task (i.e., the parent task). At step106, the first task is executed in a processor. The state information utilized to launch the first task is stored in the first task metadata data structure.

At step108, state information representing a continuation task is generated in the memory and stored in the second task metadata data structure. At step110, the continuation task is executed by the processor after the one or more child tasks have finished execution. At step112, once the continuation task has finished executing, state information in the first task metadata data structure is modified to indicate that the first task has logically finished execution.

FIG. 2illustrates a parallel processing unit (PPU)200, according to one embodiment. While a parallel processor is provided herein as an example of the PPU200, it should be strongly noted that such processor is set forth for illustrative purposes only, and any processor may be employed to supplement and/or substitute for the same. In one embodiment, the PPU200is configured to execute a plurality of threads concurrently in two or more streaming multi-processors (SMs)250. A thread (i.e., a thread of execution) is an instantiation of a set of instructions executing within a particular SM250. Each SM250, described below in more detail in conjunction withFIG. 3, may include, but is not limited to, one or more processing cores, one or more load/store units (LSUs), a level-one (L1) cache, shared memory, and the like.

In one embodiment, the PPU200includes an input/output (I/O) unit205configured to transmit and receive communications (i.e., commands, data, etc.) from a central processing unit (CPU) (not shown) over the system bus202. The I/O unit205may implement a Peripheral Component Interconnect Express (PCIe) interface for communications over a PCIe bus. In alternative embodiments, the I/O unit205may implement other types of well-known bus interfaces.

The PPU200also includes a host interface unit210that decodes the commands and transmits the commands to the task management unit215or other units of the PPU200(e.g., memory interface280) as the commands may specify. The host interface unit210is configured to route communications between and among the various logical units of the PPU200.

In one embodiment, a program encoded as a command stream is written to a buffer by the CPU. The buffer is a region in memory, e.g., memory204or system memory, that is accessible (i.e., read/write) by both the CPU and the PPU200. The CPU writes the command stream to the buffer and then transmits a pointer to the start of the command stream to the PPU200. The host interface unit210provides the task management unit (TMU)215with pointers to one or more streams. The TMU215selects one or more streams and is configured to organize the selected streams as a pool of pending grids. The pool of pending grids may include new grids that have not yet been selected for execution and grids that have been partially executed and have been suspended.

A work distribution unit220that is coupled between the TMU215and the SMs250manages a pool of active grids, selecting and dispatching active grids for execution by the SMs250. Pending grids are transferred to the active grid pool by the TMU215when a pending grid is eligible to execute, i.e., has no unresolved data dependencies. An active grid is transferred to the pending pool when execution of the active grid is blocked by a dependency. When execution of a grid is completed, the grid is removed from the active grid pool by the work distribution unit220. In addition to receiving grids from the host interface unit210and the work distribution unit220, the TMU215also receives grids that are dynamically generated by the SMs250during execution of a grid. These dynamically generated grids join the other pending grids in the pending grid pool.

In one embodiment, the CPU executes a driver kernel that implements an application programming interface (API) that enables one or more applications executing on the CPU to schedule operations for execution on the PPU200. An application may include instructions (i.e., API calls) that cause the driver kernel to generate one or more grids for execution. In one embodiment, the PPU200implements a SIMD (Single-Instruction, Multiple-Data) architecture where each thread block (i.e., warp) in a grid is concurrently executed on a different data set by different threads in the thread block. The driver kernel defines thread blocks that are comprised of k related threads, such that threads in the same thread block may exchange data through shared memory. In one embodiment, a thread block comprises 32 related threads and a grid is an array of one or more thread blocks that execute the same stream and the different thread blocks may exchange data through global memory. A thread block may also be referred to as a cooperative thread array (CTA).

In one embodiment, the PPU200comprises X SMs250(X). For example, the PPU200may include 15 distinct SMs250. Each SM250is multi-threaded and configured to execute a plurality of threads (e.g., 32 threads) from a particular thread block concurrently. Each of the SMs250is connected to a level-two (L2) cache265via a crossbar260(or other type of interconnect network). The L2 cache265is connected to one or more memory interfaces280. Memory interfaces280implement 16, 32, 64, 128-bit data buses, or the like, for high-speed data transfer. In one embodiment, the PPU200comprises U memory interfaces280(U), where each memory interface280(U) is connected to a corresponding memory device204(U). For example, PPU200may be connected to up to 6 memory devices204, such as graphics double-data-rate, version 5, synchronous dynamic random access memory (GDDR5 SDRAM).

In one embodiment, the PPU200implements a multi-level memory hierarchy. The memory204is located off-chip in SDRAM coupled to the PPU200. Data from the memory204may be fetched and stored in the L2 cache265, which is located on-chip and is shared between the various SMs250. In one embodiment, each of the SMs250also implements an L1 cache. The L1 cache is private memory that is dedicated to a particular SM250. Each of the L1 caches is coupled to the shared L2 cache265. Data from the L2 cache265may be fetched and stored in each of the L1 caches for processing in the functional units of the SMs250.

In one embodiment, the PPU200comprises a graphics processing unit (GPU). The PPU200is configured to receive commands that specify shader programs for processing graphics data. Graphics data may be defined as a set of primitives such as points, lines, triangles, quads, triangle strips, and the like. Typically, a primitive includes data that specifies a number of vertices for the primitive (e.g., in a model-space coordinate system) as well as attributes associated with each vertex of the primitive. The PPU200can be configured to process the graphics primitives to generate a frame buffer (i.e., pixel data for each of the pixels of the display). The driver kernel implements a graphics processing pipeline, such as the graphics processing pipeline defined by the OpenGL API.

An application writes model data for a scene (i.e., a collection of vertices and attributes) to memory. The model data defines each of the objects that may be visible on a display. The application then makes an API call to the driver kernel that requests the model data to be rendered and displayed. The driver kernel reads the model data and writes commands to the buffer to perform one or more operations to process the model data. The commands may encode different shader programs including one or more of a vertex shader, hull shader, geometry shader, pixel shader, etc. For example, the TMU215may configure one or more SMs250to execute a vertex shader program that processes a number of vertices defined by the model data. In one embodiment, the TMU215may configure different SMs250to execute different shader programs concurrently. For example, a first subset of SMs250may be configured to execute a vertex shader program while a second subset of SMs250may be configured to execute a pixel shader program. The first subset of SMs250processes vertex data to produce processed vertex data and writes the processed vertex data to the L2 cache265and/or the memory204. After the processed vertex data is rasterized (i.e., transformed from three-dimensional data into two-dimensional data in screen space) to produce fragment data, the second subset of SMs250executes a pixel shader to produce processed fragment data, which is then blended with other processed fragment data and written to the frame buffer in memory204. The vertex shader program and pixel shader program may execute concurrently, processing different data from the same scene in a pipelined fashion until all of the model data for the scene has been rendered to the frame buffer. Then, the contents of the frame buffer are transmitted to a display controller for display on a display device.

The PPU200may be included in a desktop computer, a laptop computer, a tablet computer, a smart-phone (e.g., a wireless, hand-held device), personal digital assistant (PDA), a digital camera, a hand-held electronic device, and the like. In one embodiment, the PPU200is embodied on a single semiconductor substrate. In another embodiment, the PPU200is included in a system-on-a-chip (SoC) along with one or more other logic units such as a reduced instruction set computer (RISC) CPU, a memory management unit (MMU), a digital-to-analog converter (DAC), and the like.

In one embodiment, the PPU200may be included on a graphics card that includes one or more memory devices204such as GDDR5 SDRAM. The graphics card may be configured to interface with a PCIe slot on a motherboard of a desktop computer that includes, e.g., a northbridge chipset and a southbridge chipset. In yet another embodiment, the PPU200may be an integrated graphics processing unit (iGPU) included in the chipset (i.e., Northbridge) of the motherboard.

FIG. 3illustrates the streaming multi-processor250ofFIG. 2, according to one embodiment. As shown inFIG. 3, the SM250includes an instruction cache305, one or more scheduler units310, a register file320, one or more processing cores350, one or more double precision units (DPUs)351, one or more special function units (SFUs)352, one or more load/store units (LSUs)353, an interconnect network380, a shared memory/L1 cache370, and one or more texture units390.

As described above, the work distribution unit220dispatches active grids for execution on one or more SMs250of the PPU200. The scheduler unit310receives the grids from the work distribution unit220and manages instruction scheduling for one or more thread blocks of each active grid. The scheduler unit310schedules threads for execution in groups of parallel threads, where each group is called a warp. In one embodiment, each warp includes 32 threads. The scheduler unit310may manage a plurality of different thread blocks, allocating the thread blocks to warps for execution and then scheduling instructions from the plurality of different warps on the various functional units (i.e., cores350, DPUs351, SFUs352, and LSUs353) during each clock cycle.

In one embodiment, each scheduler unit310includes one or more instruction dispatch units315. Each dispatch unit315is configured to transmit instructions to one or more of the functional units. In the embodiment shown inFIG. 3, the scheduler unit310includes two dispatch units315that enable two different instructions from the same warp to be dispatched during each clock cycle. In alternative embodiments, each scheduler unit310may include a single dispatch unit315or additional dispatch units315.

Each SM250includes a register file320that provides a set of registers for the functional units of the SM250. In one embodiment, the register file320is divided between each of the functional units such that each functional unit is allocated a dedicated portion of the register file320. In another embodiment, the register file320is divided between the different warps being executed by the SM250. The register file320provides temporary storage for operands connected to the data paths of the functional units.

Each SM250comprises L processing cores350. In one embodiment, the SM250includes a large number (e.g., 192, etc.) of distinct processing cores350. Each core350is a fully-pipelined, single-precision processing unit that includes a floating point arithmetic logic unit and an integer arithmetic logic unit. In one embodiment, the floating point arithmetic logic units implement the IEEE 754-2008 standard for floating point arithmetic. Each SM250also comprises M DPUs351that implement double-precision floating point arithmetic, N SFUs352that perform special functions (e.g., copy rectangle, pixel blending operations, and the like), and P LSUs353that implement load and store operations between the shared memory/L1 cache370and the register file320. In one embodiment, the SM250includes 64 DPUs351, 32 SFUs352, and 32 LSUs353.

Each SM250includes an interconnect network380that connects each of the functional units to the register file320and the shared memory/L1 cache370. In one embodiment, the interconnect network380is a crossbar that can be configured to connect any of the functional units to any of the registers in the register file320or the memory locations in shared memory/L1 cache370.

In one embodiment, the SM250is implemented within a GPU. In such an embodiment, the SM250comprises J texture units390. The texture units390are configured to load texture maps (i.e., a 2D array of texels) from the memory204and sample the texture maps to produce sampled texture values for use in shader programs. The texture units390implement texture operations such as anti-aliasing operations using mip-maps (i.e., texture maps of varying levels of detail). In one embodiment, the SM250includes 16 texture units390.

The PPU200described above may be configured to perform highly parallel computations much faster than conventional CPUs. Parallel computing has advantages in graphics processing, data compression, biometrics, stream processing algorithms, and the like.

Task Management Unit

FIG. 4illustrates a task metadata (TMD)400data structure, in accordance with one embodiment. The TMD400includes a plurality of fields that encapsulate task state information associated with a task. In one embodiment, the TMD400includes a program offset field410, a grid dimensions field420, a block dimensions field430, a resources field440, a cache control field450, a memory barriers field460, a semaphores field470, a pending counter field480, and an output dependence field490. Although not shown, the TMD400may include other fields in addition to the fields shown inFIG. 4. It will be appreciated that the TMD400shown inFIG. 4is for illustrative purposes only. The particular fields included in the TMD400encapsulate the task state required to configure a processing unit (e.g., the SM250) to execute the task. Consequently, when a TMD400is implemented for different architectures, the corresponding TMD400may include fields in addition to or in lieu of the fields shown inFIG. 4.

In one embodiment, the program offset field410stores a memory offset for the start of program instructions for the task. The grid dimensions field420includes grid dimensions for the grid. A grid is an array of thread blocks generated to implement the program specified by the program offset field410on different sets of input data (e.g., pixel data) corresponding to each thread. The grid may be one-dimensional, two-dimensional, three-dimensional, or n-dimensional. In one embodiment, the grid dimensions field420includes an x-dimension, a y-dimension, and a z-dimension for the size of a three-dimensional grid array. The block dimensions field430stores the dimension for each of the thread blocks and is equal to the number of threads included in each thread block (e.g., 32). The resources field440includes state information related to hardware resources allocated to the task. For example, the resources field440may include a location and size of a circular queue, implemented in a memory, that stores thread blocks to be added to the task. The cache control field450includes data associated with configuring the cache. For example, the cache control field450may include data that specifies what portion of the L1 cache/shared memory270is configured as a cache and what portion is configured as a shared memory. The cache control field450may also specify how much memory is allocated to each thread in a thread block. The memory barriers field460may include counters that are configured to manage task dependency. Similarly, the semaphores field470may include pointers to semaphores that should be released when a task is completed.

The TMD400defines, in the memory204, the encapsulated state information necessary to execute a particular task on a processing unit of the PPU200. In other words, the TMD400may be generated in the memory204and the fields of the TMD400may be filled by software, either a device driver or application executing on the CPU or a different task executing on the PPU200, and then a pointer to the TMD400is passed to the TMU215in the PPU200to indicate that the task is ready to be scheduled. In some system implementations, the TMD400for a task is written into a system memory (i.e., a memory associated with the CPU) and then copied to a video memory (i.e., memory204). One mechanism for copying the task to the video memory involves transmitting packets of data from the system memory to the PPU200via the system bus202. The PPU200then uses various hardware engines to store the data in the video memory. Once the PPU200is ready to schedule the task, the TMD400(or at least portions of the TMD400) is read from the video memory into on-chip memory structures accessible by the TMU215and/or the SMs250.

In one embodiment, the TMD400includes a pending counter field480. The pending counter field480holds an integer value that indicates how many other pending actions must be completed before the task associated with the TMD400is logically complete. In other words, another related task may be executing that prevents the task associated with the TMD400from finishing. When a TMD400is initiated, the pending counter field480may be initially set to one (1) that indicates that the TMD400will be logically complete when the grid of CTAs associated with the task corresponding to the TMD400has finished executing. In modern parallel processing architectures, tasks executing on the processor may be able to spawn one or more child tasks. For example, instructions in a CTA referenced by the TMD400may generate a new TMD corresponding to a child task in the memory204. The child task may generate, e.g., an intermediate value for use by one or more instructions in the CTA referenced by the TMD400. For example, the child task may sample an image to find an average value for the pixel colors in the image. The parent task may use this intermediate value for another calculation. The parent task may execute up to a point where the intermediate value is going to be calculated by a child task. The parent task then generates a TMD400in memory204corresponding to the child task and launches the child task. The parent task may then increment the pending counter field480to indicate that the child task needs to finish as well as the parent task before the parent task is logically complete. The parent task may then be evicted from the processor until the child task has finished executing. Once the child task has finished executing, the pending counter field480of the TMD400is decremented to indicate that the child task has finished and the parent task can then logically finish once any other instructions or child tasks have completed execution. A more detailed explanation of the use of the pending counter field480in relation to generating new tasks is set forth below in conjunction withFIGS. 5A through 5C.

As shown inFIG. 4, the TMD400may also include an output dependence field490. The output dependence field490is a pointer to a TMD400for a different task that is dependent on the completion of the task associated with the TMD400for execution. In one embodiment, the TMU215is configured to decrement a reference counter field (not explicitly shown inFIG. 4) that indicates whether the task corresponding to the TMD400is dependent on the completion of any predecessor tasks before the task may be executed. Once the reference counter field in the TMD400is decremented to zero (0), then the task may be scheduled and launched by the TMU215and the WDU220, respectively.

FIG. 5Aillustrates a technique for scheduling tasks associated with a continuation thread block, in accordance with one embodiment. As shown inFIG. 5A, a task may be initiated by generating a first TMD (GRID_TMD)501in memory204. The first TMD501may initialize the pending counter field480to one to indicate that the work associated with the task has not been completed. The first task corresponds to a grid of CTAs configured to perform a set of work. Again, each CTA is a group of threads configured to perform work on a set of data. At some point within one or more threads in the CTA, the program instructions for the thread may be configured to spawn (i.e., generate) one or more child tasks. The child tasks may perform work that produces an intermediate result that can be used by the threads of the parent task. Once the child tasks have been generated in the memory204, then the threads of the parent task should be stalled while the child tasks are complete. However, when the parent task is stalled, the parent task should be evicted from the SM250such that the newly pending child tasks can be allocated resources, such as a processor (i.e., and SM250) on which to be executed. Otherwise, the PPU200could quickly become deadlocked when all of the SMs250executing stalled tasks are idle and the tasks that the stalled tasks are waiting to complete have no resources on which to be processed.

In one embodiment, the parent task may initialize a continuation task that includes the work from the parent task that is executed after the child tasks have completed execution. As shown inFIG. 5A, the continuation task may be associated with a second TMD (i.e., QUEUE_TMD)511that is similar to the first TMD501. However, unlike the first TMD501, the second TMD511corresponds to a special type of task, which can receive additional CTAs for execution after the task has been launched. In other words, the size or dimensions of the QUEUE_TMD511are not necessarily specified before the task is launched. The special type of task may be referred to herein as a queue task. In addition to the second TMD511, the queue task is also associated with a circular FIFO (i.e., queue)512that is stored in memory204. The queue512holds a plurality of entries that include pointers to CTAs associated with the task. Unlike the first TMD501that includes pointers to a grid of CTAs that are fully defined in the memory204when the parent task is launched, the second TMD511includes a pointer to the queue512that may or may not include pointers to one or more CTAs when the continuation task is launched.

In one embodiment, when a logical task is generated by software, the software generates both a grid TMD501and a queue TMD511in memory204. The grid TMD501may store the state associated with a defined grid of CTAs for the task. The queue TMD511is generated to store continuation work that is to be completed after one or more child tasks have been launched and returned intermediate values to be processed by the parent task. The queue512may also be generated in the memory204which provides a place for the threads in the parent task to insert CTAs that represent the work that needs to be restored when the one or more child tasks have been completed. In another embodiment, the grid TMD501may be initialized and launched and the queue TMD511is only initialized once the task corresponding to the grid TMD501has reached an instruction to spawn a child task.

As the threads of a CTA in the parent task execute, the threads may come to a set of instructions that are configured to generate one or more child tasks to perform some intermediate work. The threads generate the one or more child tasks by initializing additional TMDs (not shown inFIG. 5A) in the memory204. Then, the threads in the CTA in the parent task may generate new CTAs to be added to the queue TMD511. The threads may create a new CTA in memory204and add a pointer to the new CTA to the queue512. The new CTAs represent the work to be restored from the CTAs in the parent task once the child tasks have been executed. In other words, the new CTAs include the instructions from the original CTAs that would be executed after the child tasks have been completed. The pointers are stored in the entries (e.g.,521,522,523) of the queue512. Once the CTA in the parent task has completed these tasks, the parent task may be evicted from the SM250. It will be appreciated that multiple CTAs in the grid of the parent task may spawn different child tasks and may generate associated new CTAs that are added to the queue512.

When each of the CTAs in the grid TMD501have finished executing and have spawned the one or more child tasks, the task associated with the grid TMD501is complete and evicted from the SM250. However, the logical task (i.e., the work encompassing the instructions to be executed after the child tasks have completed execution) is not complete, and therefore the semaphores (i.e., the one or more semaphores referenced by the semaphores field470in the grid TMD501) for the parent task should not be released. In order to prevent the TMU215from releasing the semaphores, the TMU215is configured to clean up the task and release any semaphores only once the pending counter field480for the grid TMD501reaches zero. When the task associated with the grid TMD501is evicted from the SM250, the TMU215decrements the value in the pending counter field480by one. However, when a thread block associated with the parent task generates a continuation thread block that is added to the queue512, the pending counter field480in the grid TMD501is incremented by one. Therefore, the value in the pending counter field480in the grid TMD501is incremented from one to two. Alternatively, the thread block may generate a message that is passed to the TMU215that causes the TMU215to increment the pending counter field480in the grid TMD501by one. Therefore, when the grid TMD501is evicted from the SM250, the TMU215will decrement the pending counter field480to a value that is greater than zero as long as there is still pending work associated with the corresponding queue TMD511waiting on results returned from the one or more child tasks. When the grid TMD501is evicted from the SM250, the value in the pending counter field480in the grid TMD501is decremented from a value of two to one.

FIG. 5Billustrates a set of child tasks launched by the threads of a parent task, in accordance with one embodiment. As shown inFIG. 5B, a parent task is initiated by generating a grid TMD501in the memory204. The pending counter field480is initialized to one at the time when the parent task is launched. As a part of the logical task, a queue TMD511associated with the grid TMD501is also generated in the memory204. One or more CTAs representing work to be completed by the parent task are included in a grid and associated with the grid TMD501. As the CTAs in the grid are executed by an SM250, the instructions may cause one or more child tasks to be launched to perform some intermediate work. As shown inFIG. 5B, each child task may be initiated by generating a grid TMD (e.g.,531,532,541, etc.) in the memory204. A pending counter field480for each child task may also be initialized to one. In one embodiment, for each child task created, the pending counter field480for the grid TMD501is incremented by one. Thus, for the three child tasks generated inFIG. 5B, the pending counter field480of the grid TMD501is incremented from one to four. In addition, the CTA of the parent task may also generate one or more additional CTAs that represent continuation work that is to be performed when all of the child tasks have completed their work. The one or more additional CTAs may be added to the entries of the queue512(e.g., entry521,522,523, etc.) and the pending counter field480of the grid TMD501is incremented accordingly.

In one embodiment, the CTAs associated with the parent task may generate instructions included in the continuation thread blocks that, when executed by the SM250, cause the pending counter field480of the grid TMD501to be decremented by one. Thus, when each continuation thread block is added to the queue512, the pending counter field480of the grid TMD501is incremented, and when each continuation thread block has completed execution within the SM250, the pending counter field480of the grid TMD501is decremented. In another embodiment, the pending counter field480of the grid TMD501is incremented only one time when one or more continuation thread blocks are added to the queue512. The last CTA added to the queue512includes instructions for decrementing the pending counter field480of the grid TMD501. Thus, instead of incrementing the pending counter field480for the grid TMD501once per each continuation thread block and decrementing the pending counter field480for the grid TMD501when each continuation thread block has finished executing, the pending counter field480is only incremented and decremented one time when continuation work is added to the queue512and when all continuation work has finished execution (i.e., when the task associated with the queue TMD511is finished executing).

As also shown inFIG. 5B, one or more of the child tasks may be implemented as part of a stream. A stream is a sequential ordering of dependent tasks. For example, grid TMD531corresponds to a first task in the stream and grid TMD532corresponds to a second task in the stream. The second task is dependent on the first task. In other words, the first task must finish executing before the second task can be launched. In one embodiment, the TMU215manages dependencies between tasks using streams. Each TMD may include an output dependence field490that stores a pointer to a dependent task. Similar to the pending counter field480which prevents a task from logical completion until the pending counter field480reaches zero, each TMD may also include an input dependence field (not explicitly shown) that includes a counter that must be zero before a task can be launched. For example, when a task is created, the input dependence field may be initialized to one to indicate that software is preventing the task from launch until software has finished initializing the state information in the TMD in memory204. The input dependence field can also be incremented one time for each action that must be completed before the task may be launched. For example, the second task in the stream (i.e., the task corresponding to grid TMD532) may include an input dependence field initialized to two—one for a software hold that prevents the task from being launched until software has completely filled out the grid TMD532and one for a hardware hold that prevents the task from being launched until the first task in the stream (i.e., the task corresponding to the grid TMD531) has completed execution. The output dependence field490of the grid TMD531corresponding to the first task in the stream includes a pointer to the grid TMD532corresponding to the second task in the stream that causes the TMU215to decrement the input dependence field of the grid TMD532corresponding to the second task in the stream when the first task in the stream has completed execution. If no other tasks are dependent upon the completion of the execution of a task, then the output dependence field490in the TMD corresponding to the task may include a null pointer.

FIG. 5Cillustrates a mechanism for signaling the completion of all child tasks, in accordance with one embodiment. When child tasks are created, the task associated with the queue TMD511is stalled until all of the child tasks have finished execution. In order to signal that each of the child tasks has completed execution, a special placeholder TMD551is generated, referred to herein as the end-of-child (EOC) TMD551. The EOC TMD551is a placeholder TMD data structure that is executed when all of the child tasks have completed execution. In one embodiment, the task associated with the EOC TMD551is not launched by the TMU215until each of the child tasks have completed execution because the input dependence field is not decremented to zero until every child task has completed execution. The input dependence field (not shown) of the EOC TMD551may be incremented by one each time a TMD for a child task is generated in the memory204. An output dependence field490in the TMD for each of the child tasks may be initialized with a pointer to the EOC TMD551. For example, the output dependence field490of a grid TMD531for a first child task and the output dependence field490of a grid TMD541for a second child task may each contain a pointer to the EOC TMD551. In addition, for each child task, the input dependence field of the EOC TMD551may be incremented by one. As each child task is completed, the TMU215decrements the input dependence field of the EOC TMD551. Thus, when all child tasks have finished execution, the input dependence field of the EOC TMD551stores a value of zero and the task associated with the EOC TMD551may be executed.

In one embodiment, the task associated with the EOC TMD551is launched on an SM250and one or more instructions are executed related to finishing execution of all of the child tasks. For example, the one or more instructions may perform some memory resource cleanup operations, deallocating the memory used for the TMDs corresponding to the child tasks. In another embodiment, the task associated with the EOC TMD551may be completely executed by the TMU215and the task is never launched on an SM250.

As shown inFIG. 5C, when the task associated with the EOC TMD551is finished executing, the TMU215decrements the input dependence field in the TMD pointed to by the pointer in the output dependence field490of the EOC TMD551. The output dependence field490of the EOC TMD551may point to the queue TMD511that represents the continuation thread blocks generated by the thread blocks of the parent task. When the TMU215decrements the input dependence field of the queue TMD511, the value of the input dependence field may go to zero, thereby allowing the TMU215to launch the CTAs in the queue512on the SMs250and completing the execution of the logical task that encompasses both the parent task and the continuation task.

FIGS. 6A and 6Billustrate a flowchart of a method600for scheduling tasks associated with continuation thread blocks, in accordance with another embodiment. The method600begins with steps102,104, and106of method100, set forth above. At step602, one or more child task metadata data structure (e.g., grid TMD531,532,541, etc.) are generated in the memory204. At step604, an input dependence field in the second task metadata data structure is incremented. In one embodiment, the input dependence field is incremented once and represents each of the one or more child tasks as a group. In another embodiment, the input dependence field is incremented once for each child task of the one or more child tasks generated in the memory204. At step606, a third task metadata data structure is generated in the memory204. The third metadata data structure represents the EOC TMD551that indicates when each of the one or more child tasks has finished execution.

At step608, an input dependence field in the third task metadata data structure is incremented for each child task in the one or more child tasks. At step610, an output dependence field in the task metadata data structures for each of the one or more child tasks is modified to include a pointer to the third task metadata data structure. At step612, a pointer to the second task metadata data structure (e.g., queue TMD511) is stored in an output dependence field of the third task metadata data structure (e.g., the EOC TMD551). In addition, an input dependence field in the second task metadata structure is incremented by one. At step614, an input dependence field in the second task metadata data structure (e.g., the queue TMD511) is decremented after the one or more child tasks have finished execution. In other words, when each of the child tasks has finished executing, the task corresponding to the EOC TMD551may be launched, which causes the input dependence field of the queue TMD511to be decremented. As the input dependence field of the queue TMD511reaches zero, the continuation task may be launched at step110, described above. The method then proceeds to step112, as set forth above in conjunction withFIG. 1.

It will be appreciated that the use of incremented and decremented are interchangeable in alternative embodiments. For example, a specific value other than zero may be used to determine when tasks can be launched, such as 1000. Then when child tasks are generated, the value may be decremented (e.g., from 999 to 998). When child tasks complete execution, the value may be incremented (e.g., from 999 to 1000). Thus, incremented, as used herein, may mean adding one to a value or subtracting one from the value and decremented may mean the opposite of incremented (i.e., subtracting one to a value or adding one to the value, respectively).

FIG. 7illustrates an exemplary system700in which the various architecture and/or functionality of the various previous embodiments may be implemented. As shown, a system700is provided including at least one central processor701that is connected to a communication bus702. The communication bus702may be implemented using any suitable protocol, such as PCI (Peripheral Component Interconnect), PCI-Express, AGP (Accelerated Graphics Port), HyperTransport, or any other bus or point-to-point communication protocol(s). The system700also includes a main memory704. Control logic (software) and data are stored in the main memory704which may take the form of random access memory (RAM).

The system700also includes input devices712, a graphics processor706, and a display708, i.e. a conventional CRT (cathode ray tube), LCD (liquid crystal display), LED (light emitting diode), plasma display or the like. User input may be received from the input devices712, e.g., keyboard, mouse, touchpad, microphone, and the like. In one embodiment, the graphics processor706may include a plurality of shader modules, a rasterization module, etc. Each of the foregoing modules may even be situated on a single semiconductor platform to form a graphics processing unit (GPU). Techniques for scheduling continuation thread blocks, described above, may be implemented on the graphics processor706ofFIG. 7.

Computer programs, or computer control logic algorithms, may be stored in the main memory704and/or the secondary storage710. Such computer programs, when executed, enable the system700to perform various functions. The memory704, the storage710, and/or any other storage are possible examples of computer-readable media.

In one embodiment, the architecture and/or functionality of the various previous figures may be implemented in the context of the central processor701, the graphics processor706, an integrated circuit (not shown) that is capable of at least a portion of the capabilities of both the central processor701and the graphics processor706, a chipset (i.e., a group of integrated circuits designed to work and sold as a unit for performing related functions, etc.), and/or any other integrated circuit for that matter.

Further, while not shown, the system700may be coupled to a network (e.g., a telecommunications network, local area network (LAN), wireless network, wide area network (WAN) such as the Internet, peer-to-peer network, cable network, or the like) for communication purposes.