Capacitive digital to analog convertor (CDAC) with capacitive references

Disclosed are circuits and methods for a CDAC with capacitive references. Individual reference capacitors can be implemented to provide the reference voltages for each input capacitor in a CDAC. For example, each input capacitor may be allocated a high-reference capacitor and a low-reference capacitor to provide the reference voltage to the respective input capacitor. Each of these reference capacitors is charged along with the input capacitor when the CDAC is configured into a loading configuration, and then used to convert digital data to an analog signal when the CDAC is configured into a conversion configuration. Accordingly, the reference voltage for each input capacitor is provided by a separate power source. This contrasts with current solutions in which the reference voltages for the input capacitors are provided by either a singular high-reference voltage source or low-reference voltage source.

TECHNICAL FIELD

An embodiment of the present subject matter relates generally to capacitive digital to analog convertors (CDACs), and more specifically, to a CDAC with capacitive references.

BACKGROUND

In electronics, a Digital to Analog Convertor (DAC) is an electronic device that converts a digital signal into an analog signal. For example, a DAC receives digital data (e.g., a binary value) as input and transforms the digital data into a corresponding analog signal. A Capacitive DAC (CDAD) is a type of DAC that uses multiple capacitors of different sizes to convert digital data received as input into an analog signal. The capacitors are arranged in a binary weighted capacitor array where each capacitor corresponds to a different bit of an input binary value. For example, the first capacitor corresponds to the most significant bit, the next capacitor corresponds to the next significant bit, and so on until the least significant bit. During each cycle, the capacitors are initially charged from current drawn from a power source. Once the capacitors are charged, each capacitor is then connected to either a high reference voltage or a low reference voltage based on the value of the bit in the input binary value corresponding to the capacitor. Connecting the capacitors to the high reference voltage or the low reference voltage in this manner results in current to be expelled by the capacitors which cumulatively provide an analog output voltage that corresponding to the input binary value.

CDACs are commonly used in electronic devices and components, such as Successive-Approximation Register (SAR) Analog to Digital Converters (ADCs). One issue with using CDACs is that significant current is needed to charge the capacitors from the reference inputs quickly. Performing these operations quickly is desirable, particularly when using CDACs in asynchronous-timed SAR ADCs. Drawing the significant current needed to accomplish this, however, can cause issues, such as unwanted levels of power dissipation. Accordingly, improvements are needed.

DETAILED DESCRIPTION

In the following description, for purposes of explanation, various details are set forth in order to provide a thorough understanding of some example embodiments. It will be apparent, however, to one skilled in the art, that the present subject matter may be practiced without these specific details, or with slight alterations.

Disclosed are circuits and methods for a CDAC with capacitive references. CDACs are commonly used in electronic devices and component, such as SAR ADCs. CDACS uses multiple capacitors (“input capacitors”) of different sizes to convert digital data received as input into an analog signal. The input capacitors are arranged in a binary weighted capacitor array where each input capacitor corresponds to a different bit of an input binary value. For example, the first input capacitor corresponds to the most significant bit in the input binary value, the next capacitor corresponds to the next significant bit in the input binary value, and so on. During each cycle, the input capacitors are initially charged by an input voltage source to a specified voltage. Once the input capacitors are charged, each input capacitor is then connected to either a high reference voltage or a low reference voltage based on the value of the bit in the input binary value corresponding to the input capacitor. Connecting the input capacitors to the high reference voltage or the low reference voltage in this manner results in current to be expelled by the input capacitors, which cumulatively provide an analog output voltage that corresponding to the input binary value.

As explained earlier, one issue with using CDACs is that significant current is needed to convert digital data to an analog signal, which can cause unwanted levels of power dissipation. To alleviate this issue, individual reference capacitors can be implemented to provide the reference voltages for each input capacitor. For example, each input capacitor may be allocated a high-reference capacitor and a low-reference capacitor to provide the reference voltage to the respective input capacitor. Each of these reference capacitors is charged along with the input capacitor when the CDAC is configured in a loading configuration, and then used to convert digital data to an analog signal when the CDAC is configured into a conversion configuration. Accordingly, the reference voltage for each input capacitor is provided by a separate power source. This contrasts with current solutions in which the reference voltages for the input capacitors are provided by either a singular high-reference voltage source or low-reference voltage source.

A CDAC with capacitive references provides multiple improvements over current solutions. For example, use of capacitive references provides for much faster settling than when using reference buffers. Implementing individual reference capacitors for each input capacitor allows for the use of smaller capacitors than when using global capacitive references to provide the reference voltages. For example, the individual reference capacitors used to provide reference voltage to a single input capacitor may be approximately or even smaller in size to the respective input capacitor. In contrast, a single global capacitive reference used to provide reference voltage to each input capacitor in a CDAC would have to be very large in size, such as over 100 times the combined size of the input capacitors. A CDAC using capacitive references for each input capacitor therefore provides for the use of smaller capacitors, faster settling speeds, and low power dissipation.

FIG. 1is a diagram of a CDAC102with capacitive references, according to certain example embodiments. To avoid obscuring the inventive subject matter with unnecessary detail, various functional components (e.g., modules, mechanisms, devices, nodes, etc.) that are not germane to conveying an understanding of the inventive subject matter have been omitted fromFIG. 1. However, a skilled artisan will readily recognize that various additional functional components may be supported to facilitate additional functionality that is not specifically described herein.

The CDAC102may be implemented in any of a variety of electronic devices. For example, the CDAC102may be implemented in a device including some or all of the features, components, and peripherals of the machine600shown inFIG. 6.

As shown, the CDAC102includes multiple bit-converting components1041,1042,1043, . . .104n(collectively “104”), arranged in an array. Each bit-converting component1041,1042,1043, . . .104ncorresponds to a single bit of an input binary value that is to be converted to an analog signal by the CDAC102. For example, the first bit-converting component1041in the array corresponds to the most significant bit in the input binary value, the second bit-converting component1042in the array corresponds to the next most significant bit in the input binary value (e.g., most significant bit—1), and so on until the last bit-converting component104nin the array, which corresponds to the least significant bit in the input binary value. Accordingly, the number of bit-converting components104included in the CDAC102may vary in implementation based on the desired size of input binary values to be converted by the CDAC102. For example, four bit-converting components104may be included in a CDAC102to convert four-digit binary values (e.g., 0000-1111) to analog. As another example, eight bit-converting components104may be included in a CDAC102to convert eight-digit binary values (e.g., 00000000-1111111) to analog.

Each of the bit-converting components104is connected to an input voltage source106, a high-reference voltage source108, and a low-reference voltage source110. As shown, each of the bit-converting components104includes an input capacitor C1, a high-reference capacitor C2, and a low-reference capacitor C3. The input capacitor C1included in each bit-converting unit104may be sized to create a binary weighted capacitor array in which the size of each sequential input capacitor C1in the binary weighted capacitor array is proportionally sized in relation to the previous and/or next input capacitor C1in the array. For example, the size of each input capacitor C1in the array may be half that of the previous input capacitor C1in array, such that the input capacitor C1included in the first bit-converting component1041may be twice the size of the input capacitor C1included in the second bit-converting component1042, which is twice the size of the input capacitor C3included in third bit-converting component1043, and so on. Accordingly, CDAC102including six input capacitors C1may include input capacitors C1with sizes of 32C, 16C, 8C, 4C, 2C, and 1C.

The high-reference capacitor C2and low-reference capacitor C3included in each bit-converting component104can be approximately the same size as the input capacitor C1included in the bit-converting components104, however larger sizes of capacitors may be used if desired.

To convert binary values to analog signals, the configuration of the CDAC102is shifted between a loading configuration and a conversion configuration. When the CDAC102is configured into the loading configuration, the input capacitors C1, high-reference capacitors C2and low-reference capacitors C3are connected to the input voltage source106, high-reference voltage source108, and low-reference voltage source110respectively, and charged to specified voltages. For example, the input capacitors C1are charged to a specified input voltage provided by the input voltage source106, the high-reference capacitors C2are charged to a specified high-reference voltage provided by the high-reference voltage source108, and the low-reference capacitors C3are charged to a specified low-reference voltage provided by the low-reference voltage source110.

When the CDAC102is configured into the conversion configuration, the connections between the input capacitors C1, high-reference capacitors C2and low-reference capacitors C3and their respective voltage sources are interrupted, and each input capacitor C1is connected to either the high-reference capacitor C2or low-reference capacitor C3based on the value of the bit in the input binary value corresponding to the bit-converting component104. For example, the input capacitor C1is connected to the high-reference capacitor C2when the value of the bit is 1, whereas the input capacitor C1is connected to the low-reference capacitor C3when the value of the bit is 0. Connecting the input capacitors C1to either the high-reference capacitor C2or low-reference capacitor C3in this manner causes the CDAC102provide an output voltage112corresponding to the input binary value.

Various electronic switches are used to modify the configuration of the CDAC102between the loading configuration and the conversion configuration. The electronic switches may be any type of electronic switch that is capable of coupling and decoupling electronic components within a circuit. An electronic switch may be an electronic component configured into various operational states to disconnect or connect a conducting path in an electronic circuit to interrupt or divert electrical current from one conductor to another. For example, an electronic switch may be configured in an open state to interrupt electrical current along a conducting path. Alternately, an electronic switch may be configured in a closed state to allow electrical current to pass from one conductor to another along a conducting path.

The CDAC includes charging switches S1that are coupled between the input capacitors C1, high-reference capacitors C2, and low-reference capacitor C3, and their respective power sources. For example, the charging switches S1includes an electronic switch coupled between the input voltage source106and the input capacitors C1, as well as electronic switches coupled between each high-reference capacitor C2and the high-reference voltage source108, and each low-reference capacitor C3and the low-reference voltage source110. Each bit-converting component104also includes a ground switch S2coupled between the input capacitor C1and ground, a high-reference switch S3coupled between the input capacitor C1and the high-reference capacitor C2, and a low-reference switch S4coupled between the input capacitor C1and the low-reference capacitor C3.

To configure the CDAC102into the loading configuration, the charging switches S1and the ground switches S2are configured into a closed state, and the high-reference and low-reference switches S3, S4are configured into an open state. This allows the input capacitors C1to be charged by the input voltage source106, the high-reference capacitors C2to be charged by the high-reference voltage source108, and the low-reference capacitors C3to be charged by the low-reference voltage source110, while also preventing current to flow from the high-reference capacitors C2or low-reference capacitors C3to the input capacitors C1.

To configure the CDAC102into the conversion configuration, the charging switches S1and the ground switches S2are configured in the open state. Further, in each bit-converting component104, one of either the high-reference switch S3coupled between the input capacitor C1and the high-reference capacitor C2or the low-reference switch S4coupled between the input capacitor C1and the low-reference capacitor C3is configured into the open state, while the other is configured into the closed state. For example, if the bit in the binary input corresponding to the bit-converting component104has a value of 1, the high-reference switch S3coupled between the input capacitor C1and the high-reference capacitor C2is configured into the closed state, while the low-reference switch S4coupled between the input capacitor C1and the low-reference capacitor C3is configured into the open state. In contrast, if the bit in the binary input corresponding to the bit-converting component104has a value of 0, the high-reference switch S3is configured into the open state and the low-reference switch S4coupled into the closed state.

Configuring the CDAC102into the conversion configuration prevents current from flowing from the input voltage source106, the high-reference voltage source108, and the low-reference voltage source110to the input capacitors C1, high-reference capacitors C2, and the to the low-reference capacitors C3, and causes the causes the CDAC102provide an output voltage112corresponding to the input binary value. For example, each of the bit-converting component104provides an output based on the reference voltage and input voltage stored by its respective input capacitor C1and either the high-reference capacitor C2or low-reference capacitor C3that is connected to the input capacitor C1. The cumulative outputs provided by the bit-converting components104result in an output voltage112corresponding to the input binary value that is converted by the CDAC102.

FIGS. 2A-2Dshow a CDAC102with capacitive references configured in various operating configurations, according to certain example embodiments.FIG. 2Ashows the CDAC102configured in a loading configuration. As shown, the charging switches S1and the ground switches S2are configured in a closed state, while the high-reference and low-reference switches S3, S4are configured in an open state. In the loading configuration, each of the input capacitors C1receives an input voltage from the input voltage source106. Similarly, the high-reference capacitors C2receive a high-reference voltage from the high-reference voltage source108, and the low-reference capacitors C3receive a low-reference voltage from the low-reference voltage source110.

FIG. 2Bshows the CDAC102configured in a hold portion of the conversion configuration. As shown inFIG. 2B, the charring switches S1are now configured into the open state, while the ground switches S2remain configured in the closed state, and the high-reference and low-reference switches S3, S4remain configured in the open state. As a result, the input capacitors C1no longer receive input voltage from the input voltage source106, the high-reference capacitors C2no longer receive a high-reference voltage from the high-reference voltage source108, and the low-reference capacitors C3no longer receive a low-reference voltage from the low-reference voltage source110. The input capacitors C1, however, remain connected to ground.

FIG. 2Cshows the CDAC102configured the conversion configuration. As shown, the charging switches S1remain in the open state, however the ground switches S2are now configured to in the open state to disconnect the input capacitors from ground. When the CDAC102is configured into the conversion configuration the input capacitor C1implemented within each bit-converting component104is connected to one of the high-reference capacitor C2or the low reference capacitor C3. For example, as shown inFIG. 2C, the high-reference switch S3is in the closed state to connect the high-reference capacitor C2to the input capacitor C1, while the low-reference switch S4coupled between the low-reference capacitor C3and the input capacitor C1remains in the open state. Accordingly, the high-reference capacitor C2provides its stored reference voltage to the input capacitor C1to generate the output voltage112.

In contrast,FIG. 2Dshows the input capacitor C1connected to the low-reference capacitor C3rather than the high-reference capacitor C2. For example, the low-reference switch S4coupled between the low-reference capacitor C3and the input capacitor C1is in the closed state, while the high-reference switch S3is in the open state. Accordingly, inFIG. 2D, the low-reference capacitor C2, rather than the high-reference capacitor C3, provides its stored reference voltage to the input capacitor C1to generate the output voltage112.

When the CDAC102is configured in the conversion configuration, the input capacitors C1included in each bit-converting component104may be connected to either the high-reference capacitor C2, as shown inFIG. 2C, or the low-reference capacitor C3, as shown inFIG. 2D, based on the input binary value that is being converted by the CDAC102. For example, each bit-converting component104is connected to either the high-reference capacitor C2or the low-reference capacitor C3based on the value of the bit in the input binary value corresponding to the bit-converting component104. Accordingly, when the CDAC102is configured into the conversion configuration, one of the bit-converting components104may include an input capacitor C1coupled to the high-reference capacitor C2, and another input capacitor C1coupled to the low-reference capacitor C3.

FIG. 3is a diagram of a SAR ADC300using a CDAC102with capacitive references, according to certain example embodiments. To avoid obscuring the inventive subject matter with unnecessary detail, various functional components (e.g., modules, mechanisms, devices, nodes, etc.) that are not germane to conveying an understanding of the inventive subject matter have been omitted fromFIG. 3. However, a skilled artisan will readily recognize that various additional functional components may be supported to facilitate additional functionality that is not specifically described herein.

As shown, the SAR ADC300includes a comparator302, a successive approximation register (SAR) and a CDAC. The comparator302compares two input voltages and outputs a digital signal indicating which input voltage is larger. As shown, the comparator302receives an input voltage306to be converted to a digital binary value, and an output voltage308generated by the CDAC102. The comparator302compares the two voltages306,308and provides an output signal310to the SAR304that indicates which of the two voltages306,308is larger. In turn, the SAR304provides a new input binary value312to the CDAC102to be converted to an analog output voltage308. This process results in conversion of the input voltage306to a binary value.

FIG. 4is a flowchart showing a method400for using a CDAC102with capacitive references, according to some example embodiments. The method400is described below by way of example with reference to the CDAC102shown inFIG. 1, however, it shall be appreciated that at least some of the operations of the method400may be deployed on various other hardware and/or software configurations and the method400is not intended to be limited to the CDAC102shown inFIG. 1.

At operation402, a CDAC102is configured into a loading configuration. When the CDAC102is configured into the loading configuration, input capacitors C1, high-reference capacitors C2and low-reference capacitors C3included in the CDAC102are connected to an input voltage source106, high-reference voltage source108, and low-reference voltage source110respectively, and charged to specified voltages. For example, the input capacitors C1are charged to a specified input voltage provided by the input voltage source106, the high-reference capacitors C2are charged to a specified high-reference voltage provided by the high-reference voltage source108, and the low-reference capacitors C3are charged to a specified low-reference voltage provided by the low-reference voltage source110.

To configure the CDAC102into the loading configuration, charging switches S1coupled between the input capacitors C1, high-reference capacitors C2, and low-reference capacitor C3, and their respective power sources are configured into a closed state. Similarly, ground switches S2coupled between the input capacitors C1and ground are also configured into a closed state. In contrast, high-reference switches S3coupled between the input capacitors C1and the high-reference capacitors C2, and low-reference switches S4coupled between the input capacitors C1and the low-reference capacitors C3are configured into an open state. This allows the input capacitors C1to be charged by the input voltage source106, the high-reference capacitors C2to be charged by the high-reference voltage source108, and the low-reference capacitors C3to be charged by the low-reference voltage source110, while also preventing current to flow from the high-reference capacitors C2or low-reference capacitors C3to the input capacitors C1.

At operation404, the CDAC102is configured into a conversion configuration. When the CDAC102is configured into the conversion configuration, the connections between the input capacitors C1, high-reference capacitors C2and low-reference capacitors C3and their respective voltage sources are interrupted, and each input capacitor C1is connected to either the high-reference capacitor C2or low-reference capacitor C3based on the value of the bit in the input binary value corresponding to the bit-converting component104. For example, the input capacitor C1is connected to the high-reference capacitor C2when the value of the bit is 1, whereas the input capacitor C1is connected to the low-reference capacitor C3when the value of the bit is 0. Connecting the input capacitors C1to either the high-reference capacitor C2or low-reference capacitor C3in this manner causes the CDAC102provide an output voltage112corresponding to the input binary value.

To configure the CDAC102into the conversion configuration, the charging switches S1and the ground switches S2are configured in the open state. Further, in each bit-converting component104, one of either the high-reference switch S3or the low-reference switch S4is configured into the open state, while the other is configured into the closed state. For example, if the bit in the binary input corresponding to the bit-converting component104has a value of 1, the high-reference switch S3is configured into the closed state to connect the input capacitor C1to the high-reference capacitor C2, while the low-reference switch S4coupled between the input capacitor C1and the low-reference capacitor C3is configured into the open state. In contrast, if the bit in the binary input corresponding to the bit-converting component104has a value of 0, the high-reference switch S3is configured into the open state and the low-reference switch S4is configured into the closed state to connect the input capacitor C1to the low-reference capacitor C3.

Configuring the CDAC102into the conversion configuration prevents current from flowing from the input voltage source106, the high-reference voltage source108, and the low-reference voltage source110to the input capacitors C1, high-reference capacitors C2, and the to the low-reference capacitors C3, and causes the CDAC102to provide an output voltage112corresponding to the input binary value. For example, each of the bit-converting components104provides an output based on the reference voltage and input voltage stored by its respective input capacitor C1and either the high-reference capacitor C2or low-reference capacitor C3that is connected to the input capacitor C1. The cumulative outputs provided by the bit-converting components104result in an output voltage112corresponding to the input binary value that is converted by the CDAC102.

Software Architecture

FIG. 5is a block diagram illustrating an example software architecture506, which may be used in conjunction with various hardware architectures herein described.FIG. 5is a non-limiting example of a software architecture506and it will be appreciated that many other architectures may be implemented to facilitate the functionality described herein. The software architecture506may execute on hardware such as machine600ofFIG. 6that includes, among other things, processors604, memory614, and (input/output) I/O components618. A representative hardware layer552is illustrated and can represent, for example, the machine600ofFIG. 6. The representative hardware layer552includes a processing unit554having associated executable instructions504. Executable instructions504represent the executable instructions of the software architecture506, including implementation of the methods, components, and so forth described herein. The hardware layer552also includes memory and/or storage modules556, which also have executable instructions504. The hardware layer552may also comprise other hardware558.

In the example architecture ofFIG. 5, the software architecture506may be conceptualized as a stack of layers where each layer provides particular functionality, such as the Open Systems Interconnection model (OSI model). For example, the software architecture506may include layers such as an operating system502, libraries520, frameworks/middleware518, applications516, and a presentation layer514. Operationally, the applications516and/or other components within the layers may invoke application programming interface (API) calls508through the software stack and receive a response such as messages512in response to the API calls508. The layers illustrated are representative in nature and not all software architectures have all layers. For example, some mobile or special purpose operating systems may not provide a frameworks/middleware518, while others may provide such a layer. Other software architectures may include additional or different layers.

The operating system502may manage hardware resources and provide common services. The operating system502may include, for example, a kernel522, services524, and drivers526. The kernel522may act as an abstraction layer between the hardware and the other software layers. For example, the kernel522may be responsible for memory management, processor management (e.g., scheduling), component management, networking, security settings, and so on. The services524may provide other common services for the other software layers. The drivers526are responsible for controlling or interfacing with the underlying hardware. For instance, the drivers526include display drivers, camera drivers, Bluetooth® drivers, flash memory drivers, serial communication drivers (e.g., Universal Serial Bus (USB) drivers), Wi-Fi® drivers, audio drivers, power management drivers, and so forth, depending on the hardware configuration.

The libraries520provide a common infrastructure that is used by the applications516and/or other components and/or layers. The libraries520provide functionality that allows other software components to perform tasks in an easier fashion than to interface directly with the underlying operating system502functionality (e.g., kernel522, services524, and/or drivers526). The libraries520may include system libraries544(e.g., C standard library) that may provide functions such as memory allocation functions, string manipulation functions, mathematical functions, and the like. In addition, the libraries520may include API libraries546such as media libraries (e.g., libraries to support presentation and manipulation of various media format such as MPEG4, H.264, MP3, AAC, AMR, JPG, PNG), graphics libraries (e.g., an OpenGL framework that may be used to render 2D and 3D in a graphic content on a display), database libraries (e.g., SQLite that may provide various relational database functions), web libraries (e.g., WebKit that may provide web browsing functionality), and the like. The libraries520may also include a wide variety of other libraries548to provide many other APIs to the applications516and other software components/modules.

The frameworks/middleware518(also sometimes referred to as middleware) provide a higher-level common infrastructure that may be used by the applications516and/or other software components/modules. For example, the frameworks/middleware518may provide various graphical user interface (GUI) functions, high-level resource management, high-level location services, and so forth. The frameworks/middleware518may provide a broad spectrum of other APIs that may be used by the applications516and/or other software components/modules, some of which may be specific to a particular operating system502or platform.

The applications516include built-in applications538and/or third-party applications540. Examples of representative built-in applications538may include, but are not limited to, a contacts application, a browser application, a book reader application, a location application, a media application, a messaging application, and/or a game application. Third-party applications540may include an application developed using the ANDROID™ or IOS™ software development kit (SDK) by an entity other than the vendor of the particular platform, and may be mobile software running on a mobile operating system such as IOS™, ANDROID™, WINDOWS® Phone, or other mobile operating systems. The third-party applications540may invoke the API calls508provided by the mobile operating system (such as operating system502) to facilitate functionality described herein.

The applications516may use built in operating system functions (e.g., kernel522, services524, and/or drivers526), libraries520, and frameworks/middleware518to create UIs to interact with users of the system. Alternatively, or additionally, in some systems, interactions with a user may occur through a presentation layer, such as presentation layer514. In these systems, the application/component “logic” can be separated from the aspects of the application/component that interact with a user.

FIG. 6is a block diagram illustrating components of a machine600, according to some example embodiments, able to read instructions504from a machine-readable medium (e.g., a machine-readable storage medium) and perform any one or more of the methodologies discussed herein. Specifically,FIG. 6shows a diagrammatic representation of the machine600in the example from of a computer system, within which instructions610(e.g., software, a program, an application, an applet, an app, or other executable code) for causing the machine600to perform any one or more of the methodologies discussed herein may be executed. As such, the instructions610may be used to implement modules or components described herein. The instructions610transform the general, non-programmed machine600into a particular machine600programmed to carry out the described and illustrated functions in the manner described. In alternative embodiments, the machine600operates as a standalone device or may be coupled (e.g., networked) to other machines. In a networked deployment, the machine600may operate in the capacity of a server machine or a client machine in a server-client network environment, or as a peer machine in a peer-to-peer (or distributed) network environment. The machine600may comprise, but not be limited to, a server computer, a client computer, a PC, a tablet computer, a laptop computer, a netbook, a set-top box (STB), a personal digital assistant (PDA), an entertainment media system, a cellular telephone, a smart phone, a mobile device, a wearable device (e.g., a smart watch), a smart home device (e.g., a smart appliance), other smart devices, a web appliance, a network router, a network switch, a network bridge, or any machine600capable of executing the instructions610, sequentially or otherwise, that specify actions to be taken by machine600. Further, while only a single machine600is illustrated, the term “machine” shall also be taken to include a collection of machines that individually or jointly execute the instructions610to perform any one or more of the methodologies discussed herein.

The machine600may include processors604, memory/storage606, and I/O components618, which may be configured to communicate with each other such as via a bus602. The memory/storage606may include a memory614, such as a main memory, or other memory storage, and a storage unit616, both accessible to the processors604such as via the bus602. The storage unit616and memory614store the instructions610embodying any one or more of the methodologies or functions described herein. The instructions610may also reside, completely or partially, within the memory614, within the storage unit616, within at least one of the processors604(e.g., within the processor's cache memory), or any suitable combination thereof, during execution thereof by the machine600. Accordingly, the memory614, the storage unit616, and the memory of processors604are examples of machine-readable media.

The I/O components618may include a wide variety of components to receive input, provide output, produce output, transmit information, exchange information, capture measurements, and so on. The specific I/O components618that are included in a particular machine600will depend on the type of machine. For example, portable machines such as mobile phones will likely include a touch input device or other such input mechanisms, while a headless server machine will likely not include such a touch input device. It will be appreciated that the I/O components618may include many other components that are not shown inFIG. 6. The I/O components618are grouped according to functionality merely for simplifying the following discussion and the grouping is in no way limiting. In various example embodiments, the I/O components618may include output components626and input components628. The output components626may include visual components (e.g., a display such as a plasma display panel (PDP), a light emitting diode (LED) display, a liquid crystal display (LCD), a projector, or a cathode ray tube (CRT)), acoustic components (e.g., speakers), haptic components (e.g., a vibratory motor, resistance mechanisms), other signal generators, and so forth. The input components628may include alphanumeric input components (e.g., a keyboard, a touch screen configured to receive alphanumeric input, a photo-optical keyboard, or other alphanumeric input components), point based input components (e.g., a mouse, a touchpad, a trackball, a joystick, a motion sensor, or other pointing instrument), tactile input components (e.g., a physical button, a touch screen that provides location and/or force of touches or touch gestures, or other tactile input components), audio input components (e.g., a microphone), and the like.

In further example embodiments, the I/O components618may include biometric components630, motion components634, environmental components636, or position components638among a wide array of other components. For example, the biometric components630may include components to detect expressions (e.g., hand expressions, facial expressions, vocal expressions, body gestures, or eye tracking), measure biosignals (e.g., blood pressure, heart rate, body temperature, perspiration, or brain waves), identify a person (e.g., voice identification, retinal identification, facial identification, fingerprint identification, or electroencephalogram based identification), and the like. The motion components634may include acceleration sensor components (e.g., accelerometer), gravitation sensor components, rotation sensor components (e.g., gyroscope), and so forth. The environmental components636may include, for example, illumination sensor components (e.g., photometer), temperature sensor components (e.g., one or more thermometer that detect ambient temperature), humidity sensor components, pressure sensor components (e.g., barometer), acoustic sensor components (e.g., one or more microphones that detect background noise), proximity sensor components (e.g., infrared sensors that detect nearby objects), gas sensors (e.g., gas detection sensors to detect concentrations of hazardous gases for safety or to measure pollutants in the atmosphere), or other components that may provide indications, measurements, or signals corresponding to a surrounding physical environment. The position components638may include location sensor components (e.g., a GPS receiver component), altitude sensor components (e.g., altimeters or barometers that detect air pressure from which altitude may be derived), orientation sensor components (e.g., magnetometers), and the like.

Communication may be implemented using a wide variety of technologies. The I/O components618may include communication components640operable to couple the machine600to a network632or devices620via coupling624and coupling622, respectively. For example, the communication components640may include a network interface component or other suitable device to interface with the network632. In further examples, communication components640may include wired communication components, wireless communication components, cellular communication components, near field communication (NFC) components, Bluetooth® components (e.g., Bluetooth® Low Energy), Wi-Fi® components, and other communication components to provide communication via other modalities. The devices620may be another machine or any of a wide variety of peripheral devices (e.g., a peripheral device coupled via a USB).

GLOSSARY

“CARRIER SIGNAL” in this context refers to any intangible medium that is capable of storing, encoding, or carrying instructions610for execution by the machine600, and includes digital or analog communications signals or other intangible medium to facilitate communication of such instructions610. Instructions610may be transmitted or received over the network632using a transmission medium via a network interface device and using any one of a number of well-known transfer protocols.

“CLIENT DEVICE” in this context refers to any machine600that interfaces to a communications network632to obtain resources from one or more server systems or other client devices. A client device may be, but is not limited to, mobile phones, desktop computers, laptops, PDAs, smart phones, tablets, ultra books, netbooks, laptops, multi-processor systems, microprocessor-based or programmable consumer electronics, game consoles, STBs, or any other communication device that a user may use to access a network632.

“MACHINE-READABLE MEDIUM” in this context refers to a component, device or other tangible media able to store instructions610and data temporarily or permanently and may include, but is not be limited to, random-access memory (RAM), read-only memory (ROM), buffer memory, flash memory, optical media, magnetic media, cache memory, other types of storage (e.g., erasable programmable read-only memory (EEPROM)), and/or any suitable combination thereof. The term “machine-readable medium” should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, or associated caches and servers) able to store instructions610. The term “machine-readable medium” shall also be taken to include any medium, or combination of multiple media, that is capable of storing instructions610(e.g., code) for execution by a machine600, such that the instructions610, when executed by one or more processors604of the machine600, cause the machine600to perform any one or more of the methodologies described herein. Accordingly, a “machine-readable medium” refers to a single storage apparatus or device, as well as “cloud-based” storage systems or storage networks that include multiple storage apparatus or devices. The term “machine-readable medium” excludes signals per se.

“PROCESSOR” in this context refers to any circuit or virtual circuit (a physical circuit emulated by logic executing on an actual processor604) that manipulates data values according to control signals (e.g., “commands,” “op codes,” “machine code,” etc.) and which produces corresponding output signals that are applied to operate a machine600. A processor604may be, for example, a central processing unit (CPU), a reduced instruction set computing (RISC) processor, a complex instruction set computing (CISC) processor, a graphics processing unit (GPU), a digital signal processor (DSP), an ASIC, a radio-frequency integrated circuit (RFIC) or any combination thereof. A processor604may further be a multi-core processor having two or more independent processors604(sometimes referred to as “cores”) that may execute instructions610contemporaneously.