MEMORY OVERLAY USING A HOST MEMORY BUFFER

Two or more overlay sections are copied from a non-volatile memory device of a memory sub-system to a first memory buffer residing on a first volatile memory device of a host system in communication with the memory sub-system. Each overlay section includes a respective set of executable instructions. A first overlay section is copied from the host memory buffer to a second memory buffer residing on a second volatile memory device of the memory sub-system. A first set of executable instructions included in the first overlay section residing in the second memory buffer is executed. A second overlay section is copied from the host memory buffer to the second memory buffer. A second set of executable instructions included in the second overlay section residing in the second memory buffer is executed.

TECHNICAL FIELD

Embodiments of the disclosure relate generally to memory sub-systems, and more specifically, relate to memory overlay using a host memory buffer.

BACKGROUND

DETAILED DESCRIPTION

Aspects of the present disclosure are directed to systems and methods to memory overlay using a host system memory buffer. A memory sub-system can be a storage device, a memory module, or a hybrid of a storage device and memory module. Examples of storage devices and memory modules are described below in conjunction withFIG.1. In general, a host system can utilize a memory sub-system that includes one or more memory components (also hereinafter referred to as “metnory devices”). The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system.

A memory sub-system can include multiple memory devices that are each associated with different memory latencies. A memory access latency refers to an amount of time elapsed for servicing a request for data or code stored at a memory device. In some conventional systems, a memory sub-system controller can copy a first section of code stored at a memory device exhibiting a high access latency, referred to as a high latency memory device, to a memory device associated with a lower access latency, referred to a low latency memory device. For example, a low latency memory device can he a dynamic random access memory (DRAM) device and a high latency memory device can be a non-volatile memory device (e.g., a flash memory device). The memory sub-system controller can execute the first code section residing on the low latency memory device. in some instances, the first code section can include a reference (i.e., a jump instruction) to a second code section stored at the high latency memory device. The memory sub-system controller can remove the first code section from the low latency memory device and copy the second code section from the high latency device to the low latency device. The memory sub-system controller can then execute the second code section residing on the low latency memory device. This technique is referred to memory overlay or memory overlaying.

Memory overlay can be used to reduce an overall mernor sub-system latency. For example, in memory sub-systems including a DRAM device, the memory sub-system controller can overlay code sections stored at a non-volatile memory device (e.g., a NAND flash memory device) to the DRAM device. However, some memory sub-systems do not include a DRAM device and instead include only a static RAM (SRAM) device or a tightly coupled memory (TCM) device. A storage capacity of a SRAM device and/or a TCM device can be significantly smaller than a storage capacity of a non-volatile memory device. Therefore, only a small portion of code stored at the high latency memory device can be copied to the low latency memory device at a given time. The memory sub-system controller performs a significant amount of copying operations to copy code from the high latency memory device to the low latency memory device during operation of the memory sub-system. As a result of the significant amount of copying operations and the high latency associated with the high latency memory device, a reduction in the overall memory sub-system latency is minimal at best.

Aspects of the present disclosure address the above and other deficiencies by having a memory sub-system that uses a memory butler of a host system (referred to herein as a host memory buffer) to facilitate memory overlay during operation of the memory sub-system. A host memory buffer can be part of a memory device that is associated with a latency that is lower than a high latency memory device (e.g., a non-volatile memory device). For example, a host memory buffer can reside on DRAM device of the host system.

The high latency memory device, such as a non-volatile memory device, can store multiple overlay sections each including one or more code sections to be executed during operation of the memory sub-system. EaCh code section can include a set of one or more executable instructions executed by a memory sub-system controller. During initialization of the memory sub-system, the memory sub-system controller can copy at least a portion of overlay sections stored at the high latency memory device to the host memory butler. In response to determining a particular code section is to be executed by the memory sub-system controller, the memory sub-system controller can identify a first overlay section including the particular code section and determine whether the first overlay section is present in the host memory buffer. In response to determining the first overlay section is present in the host memory buffer, the memory sub-system controller can copy the first overlay section to a buffer residing on a low latency memory device (e.g., a SRAM device, a TCM device, etc.) of the memory sub-system (referred to as a memory sub-system buffer). The memory sub-system controller can execute the particular code section included in the first overlay section from the memory sub-system buffer. The memory sub-system controller can determine that another code section is to be executed by the memory sub-system controller. In response to determining a second overlay section including the code section is present in the host memory buffer, the memory sub-system controller can remove the first overlay section from the memory sub-system buffer and copy the second overlay section from the host memory buffer to the memory sub-system buffer. The memory sub-system controller can then execute the code section included in the second overlay section from the memory sub-system buffer.

Advantages of the present disclosure include, but are not limited to, a decrease in an overall system latency of a memory sub-system and an increase in overall memory sub-system performance. Overlay sections stored at a high latency memory device a non-volatile memory device) are copied to the host memory buffer of a low latency memory device (e.g., a DRAM device) during initialization of the memory sub-system. During operation of the memory sub-system, the memory sub-system controller can copy overlay sections to the memory sub-system buffer from the host memory buffer instead of the high latency memory device. By copying data from the host memory buffer instead of the high latency memory device, a number of copying operations between the high latency memory device and the memory sub-system buffer is significantly reduced, thereby reducing overall system latency and increasing overall system performance. Further, as the host memory buffer resides on a low latency memory device (e.g., a DRAM memory device), data stored at the host memory buffer can be accessed and copied to the memory sub-system buffer more quickly than data copied to the memory sub-system buffer from the high latency memory device, thereby further reducing overall system latency and increasing overall system performance.

In some embodiments, a driver of host system120can allocate one or more portions of host system memory to be accessible by memory sub-system controller115(referred to herein as host memory buffers). A host memory buffer can store data. or code associated with operation of memory sub-system110For example, a logical to physical address table (i.e., a L2P table) can be stored at a first portion of a host memory buffer of host system120. Memory sub-system controller115can access the L2P table stored at the host memory buffer to translate a logical address for a portion of data stored at a memory device130,140to a physical address. In some embodiments, one or more portions of the host memory buffer can store sections of executable code copied from a memory device130,140. In such embodiments, the host memory butler can be used to facilitate memory overlay during operation of the memory sub-system110. The host memory buffer can be associated with a latency that is lower than a latency associated with a memory device130,140. For example, the host memory buffer can be a part of a DRAM device and the memory device130can be a non-volatile memory device. In some embodiments, a host memory buffer can store a L2P table and executable code sections copied from a memory device130,140. In other or similar embodiments, the host memory butler can store executable code sections copied from a memory device130,140without storing the L2P table.

In some embodiments, memory sub-system110can include a memory sub-system buffer. In some instances, the memory sub-system buffer can be associated with a latency that is lower than a latency associated with the host memory buffer and a latency associated with a memory device130,140. For example, the memory sub-system buffer can be part of a tightly coupled memory (TCM) device or a static random access memory (SRAM) device, the host memory butler can be part of a DRAM device, and the memory device130can be a non-volatile memory device. In sonie embodiments, a memory sub-system buffer can be a portion of local memory119. In other or similar embodiments, the memory device130can be a first memory device and the memory sub-system buffer can be part of a second memory device (e.g., memory device140).

The memory sub-system110includes a host memory buffer overlay component113(referred to herein as HMB overlay component113) that facilitates memory overlay using the host memory buffer of host system120. In some embodiments, the memory sub-system controller115includes at least a portion of the HMB overlay component113. For example, the memory sub-system controller115can include a processor117(processing device) configured to execute instructions stored in local memory119for performing the operations described herein. In some embodiments, the HMB overlay component113is part of the host system110, an application, or an operating system.

The HMB overlay component113can facilitate code section overlaying in the memory sub-system buffer. In some embodiments, memory device130can store multiple code sections where each code section is included in an overlay section. Each code section can include a set of executable instructions executed by firmware of memory sub-system110. During initialization of the memory sub-system110, the HMB overlay component113can copy at least a portion of the overlay sections stored at the memory device130to the host memory buffer. In response to memory sub-system controller115determining a particular code section is to be executed, HMB overlay component113can identify a first overlay section of the memory device130that includes the particular code section and determine whether the first overlay section is present in the host memory buffer. In response to determining the first overlay section is present in the host memory buffer, the HMB overlay component113can copy the first overlay section from the host memory buffer to the memory sub-system buffer. The memory sub-system controller115can execute the particular code section included in the first overlay section from the memory sub-system buffer. The memory sub-system controller115can determine that another code section is to be executed. In response to determining a second overlay section including the code section is present in the host memory buffer, HMB overlay component113can remove the first overlay section from the memory sub-system buffer and copy the second overlay section from the host memory buffer to the memory sub-system buffer. The memory sub-system controller115can then execute the code section included in the second overlay section from the memory sub-system buffer. Further details with regards to the operations of the HMB overlay component113are described below.

In some embodiments, an overlay section including code associated with executing HMB overlay component113can be copied to the memory sub-system buffer during initialization of memory sub-system110. For example, the overlay section associated with executing HMB overlay component113can be copied from memory device130to the memory sub-system buffer or from the host memory buffer to the memory sub-system buffer, in accordance with embodiments described herein. In some embodiments, the overlay section associated with executing HMB overlay component113can remain in the memory sub-system buffer during operation of memory sub-system110and is not removed from the memory sub-system buffer during performance of memory overlay.

FIG.2illustrates memory overlay using a host memory buffer210, in accordance with some embodiments of the present disclosure. As described previously, memory device130,140can be anon-volatile memory device that stores one or more overlay sections212. Each overlay section212can include a set of executable instructions. During initialization of memory sub-system110, HHB overlay component113can copy one or more overlay sections (e.g., overlay sections1-N) to host memory buffer210. As described previously, host memory buffer210can reside on a memory device exhibiting a lower latency than memory device130,140. For example, host memory buffer210can reside on a DRAM memory device. During operation of memory sub-system110, memory sub-system controller can determine a particular code section stored at the memory device130,140is to be executed. In some embodiments, memory sub-system controller115can determine a particular code section is to be executed in response to receiving a request from firmware of memory sub-system110. HMB overlay component113can identify an overlay section212of memory device130that includes the requested code section and determine whether the identified overlay section212is present in host memory buffer210. In response to determining the overlay section212is present in host memory buffer210, HMB overlay component113can copy the overlay section from host memory buffer210to memory sub-system buffer220. As discussed previously, memory sub-system buffer220can reside on a memory device associated with a lower latency than host memory buffer210and memory device130,140. For example, memory sub-system buffer220can reside on a TCM memory device or a SRAM memory device.

In an illustrative example, memory sub-system controller115can determine a particular code section included in overlay section1is to be executed. In response to determining the particular code section is included in overlay section1. HMB overlay component113can determine whether overlay section1is present in host memory buffer210. In response to determining overlay section1is present in to host memory buffer210, HM111overlay component113can copy overlay section1from host memory buffer210to memory sub-system buffer220. Memory sub-system controller115can execute the code section of overlay section1from memory sub-system buffer220. The memory sub-system controller115can determine another code section included in overlay section2is to be executed. For example, a portion of the code section of overlay section1can include an instruction (i.e., ajump instruction) to execute a portion of the code section of overlay section2. In response to determining overlay section2is present in host memory buffer210, IIMB overlay component113can determine Whether space is available on memory sub-system buffer220for copying of overlay section2. In response to determining that space is not available on memory sub-system buffer220for copying of overlay section2, HAM overlay component113can remove overlay section1from memory sub-system buffer220. HMB overlay component113can then copy overlay section2to memory sub-system buffer220.

At operation310, the processing device copies two or more overlay sections from a non-volatile memory device of the memory sub-system to a first memory buffer (i.e., a host memory buffer) residing on a first volatile memory device of a host system in communication with the memory sub-system. Each overlay section can include sections of code stored at the memory device. Each second of code can include a set of executable instructions, as described previously.FIGS.5A-5Cillustrate memory overlay at memory sub-system H0using a host memory buffer210, in accordance with some embodiments of the present disclosure. As illustrated inFIG.5A, memory device130can be a non-volatile memory device. In some embodiments, the processing device ofFIG.3can include EIMB overlay component113. HMB overlay component113can assign code sections stored at memory device130to be included in particular overlay sections212.

In some embodiments, HMB overlay component113can assign code sections to be included in an overlay section212based on a frequency that instructions included in a particular code section are executed during operation of memory sub-system110(e,g., by firmware of memory sub-system110, etc.). In some embodiments, HMB overlay component113can determine an execution frequency based on an estimated number of instances instructions included in a particular code section are executed during operation of the memory sub-system110. For example, HMB overlay component113can determine the execution frequency for a particular set of instructions based on a measured execution frequency associated with another set of instructions that are similar or related to the particular set of instructions In other or similar embodiments, HMB overlay component113can determine the execution frequency based on a measured execution frequency for the set of instructions. For example, HMB overlay component113can measure an execution frequency for a set of instructions during operation of memory sub-system110. HMB overlay component113can store the measured execution frequency in non-volatile memory (e.g., memory130). During initialization (e.g., power up) of memory sub-system110, HMB overlay component113can determine the execution frequency for a particular set of instructions based on the previously measured execution frequency associated with the particular set of instructions stored in non-volatile memory-. In other or similar embodiments, the execution frequency for a. particular set of instructions can be provided by a programmer or developer of the particular set of instructions.

In some embodiments, HMB overlay component113can identify a first code section and a second code section stored at memory device130. The instructions included in the first code section can be associated with a first execution frequency and the second code section can be associated with a second execution frequency. HMB overlay component113can compare the first execution frequency to the second execution frequency. In response to determining the first execution frequency is lower than the second execution frequency, HMB overlay component113can determine the instructions associated with the first code section are executed less frequently than the instructions associated with the second code section during operation of memory sub-system110. As such, HMB overlay component113can include the first code section in a first overlay section212and the second code section in a second overlay section212.

In some embodiments, memory device130can store code sections that include instructions that are critical to the performance or operation of the memory sub-system110or host system120(e.g., data associated with a handler for a frequently executed command). HMB overlay component113can identify code sections that include critical instructions and include such code sections together in an overlay section212. In some embodiments, HMB overlay component113can determine whether an instruction is a critical instruction based on an indication provided by a programmer or developer of a code section. In other or similar embodiments, HMB overlay component113can determine that an instruction is a critical instruction based on based on a similarity or a relation between a known critical instruction and instructions included in code sections stored at memory device130. Responsive to determining that a code section stored at memory device130includes a critical instruction, HMB overlay component113can include the code section in a particular overlay section212.

In some embodiments, IIMB overlay component can include code sections in an overlay section212that include instructions that reference other instructions of the overlay section212, HMB overlay component113can identify a first code section and a second code section stored at memory device130. HMB overlay component113can determine whether an instruction included in the first code section includes a reference to an instruction included in the second code section. In response to determining that the instruction included in the first code section includes a reference to an instruction included in the second code section, HMB overlay component113can include the first code section and the second code section in a single overlay section212. In response to determining the first code section does not include an instruction that references an instruction in the second code section. HMB overlay component113can include the first code section in a first overlay section212and the second code section in a second overlay section212.

HMB overlay component113can allocate one or more portions of the host memory buffer210for copying of one or more overlay sections212. In some embodiments, HMB overlay component113can transmit a request to host system120to allocate one or more portions of host memory buffer210for overlay sections212of memory device130. In other or similar embodiments, HMB overlay component113can allocate the portions of host memory buffer210without transmitting a request to host system120. HMB overlay component can allocate a particular number of portions and/or a particular amount of space of host memory buffer210for overlay sections212. In some embodiments, HMB overlay component113can include the particular number of portions and/or the particular amount of space in a request transmitted to host system120. Responsive to receiving the request from HMB overlay component113, a driver of host system120can identify one or more available portions of host memory buffer210and allocate the one or more available portions of host memory buffer210for overlay sections212, in accordance with the request. The driver of host system120can transmit an indication of the one or more portions of host memory buffer210reserved for overlay sections212. In some embodiments, the indication can include an amount of space included in the reserved portions of host memory buffer210. In other or similar embodiments, the indication can include a memory address for each allocated portion of host memory buffer210.

As described with respect toFIG.2, HMB overlay component113can copy two or more overlay sections212to the host memory buffer210. As illustrated inFIG.54, host memory buffer210can reside in a volatile memory device, such as volatile memory device510. In some embodiments, HMB overlay component113can copy the two or more overlay sections212during initialization of the memory sub-system110. In some embodiments, HMB overlay component113can copy an overlay section212to a reserved portion of host memory buffer210. HMB overlay component113can determine, based on a size an available portion of the host memory buffer210, a number of overlay sections212to copy to the host memory buffer210. In some embodiments, the size of the available portion of the host memory buffer210may be smaller than a total size or a total number of overlay sections212of memory device130. In such embodiments, HMB overlay component113can copy overlay sections212to the available portion of host memory buffer210until the host memory buffer210is no longer available for copying (i.e., host memory buffer210does not include an available portion). As a result, HMB overlay component113does not copy all overlay sections212to host memory buffer202. For example, as illustrated with respect toFIG.54, HMB overlay component113copies each of overlay section1, overlay section2, and overlay section3to host memory buffer210until host memory buffer210is no longer available for copying (i.e., no additional space is available in any allocated portion of host memory buffer210). As a result, HMB overlay component113does not copy additional overlay sections212stored at memory device130(e.g., overlay section N) to host memory buffer210.

In some embodiments, HMB overlay component113can maintain an overlay data structure configured to track code sections included in overlay sections212and overlay sections212present in host memory buffer210. For example, the overlay data structure can include an entry for each overlay section212of memory device130. Each entry can include one or more memory addresses for each code section included in the overlay section212. In response to copying an overlay section212from memory device130, HMB overlay component113can update an entry for the overlay section212to indicate that the overlay section212is copied at the host memory buffer210. In some embodiments, the overlay data structure entry can further include an indication of the portion of host memory buffer210that includes the copied overlay section212. In other or similar embodiments, HMB overlay component113can track overlay sections212present in host memory buffer210in accordance with other implementations.

Referring back toFIG.3, at operation320, the processing device can copy a first overlay section of the two or more overlay sections from the first memory buffer to a second memory buffer residing on a second volatile memory device of the memory sub-system. In some embodiments, the second volatile memory device can be a local memory device, such as local memory119. In other or similar embodiments, the second memory device can be a memory device of memory sub-system110(e.g., memory device140), as illustrated inFIG.5A, The second memory buffer residing on the second volatile memory device can be memory sub-system buffer220of

In some embodiments, HMB overlay component113can copy a first overlay section to memory sub-system buffer220ofFIG.5Ain response to determining a first code section of the first overlay section212is to be executed.11M13overlay component113can identify a first overlay section212of memory device130that includes the first code section. In some embodiments, HMB overlay component113can identify the first overlay section212of memory device130,140that includes the first code section using an overlay section identification function. For example. HMB overlay component113can provide a memory address for one or more instructions associated with the first code section as a parameter value to the overlay section identification function. HMB overlay component113can receive, as an output of the overlay section identification function, an indication that the one or more instructions are included in the first overlay section212. In other or similar embodiments, HMB overlay component113ofFIG.2can identify a first overlay section212of memory device130that includes the first code section using the overlay data structure, For example, HMB overlay component113can compare a memory device address associated with the first code section with one or more memory device addresses of entries of the overlay data structure. In response to determining the memory device address for the first code section corresponds to a memory device address for an entry of the overlay data structure for the first overlay section212, HMB overlay component113can determine the first code section is included in the first overlay section212.

In response to determining the first code section is included in the first overlay section212, HMB overlay component113can determine whether the first overlay section212is present in the host memory buffer210. In some embodiments, HMB overlay component113can determine whether the first overlay section212is present in the host memory buffer210using the overlay data structure. For example, HMB overlay component113can determine, based on an overlay data structure entry for the first overlay section212, whether the first overlay section212is present in the host memory buffer210. In response to determining the first overlay section212is present in the host memory buffer210, HMB overlay component113can copy the first overlay section to the memory sub-system buffer220. In response to determining the first overlay section212is not present in the host memory buffer210, HMB overlay component113can copy the first overlay section from the memory device130,140to the host memory buffer210, in accordance with embodiments described herein. At operation230, the processing device can execute the first set of executable instructions included in the overlay section residing in the memory sub-system buffer220.

At operation340, the processing device can copy a second overlay section of the two or more overlay sections from the first memory buffer (i.e., the host memory buffer210) to the second memory buffer (i.e., the memory sub-system buffer220). in some embodiments, HMB overlay component113can copy the second overlay section to memory sub-system buffer220ofFIG.54in response to determining a second code section of the second overlay section212is to be executed, in accordance with previously described embodiments. HMB overlay component113can determine whether the second overlay section212resides on the host memory buffer210. In response to determining the second overlay section212resides on the host memory buffer210, HMB overlay component can determine whether a space is available on memory sub-system buffer220for copying the second overlay section212. In some embodiments, HMB overlay component can determine space of memory sub-system buffer220is not available for copying of the second overlay section212. For example, HMB overlay component113can determine space of memory sub-system buffer220is not available for copying of overlay section2because overlay section1resides in memory subs-system buffer220. As illustrated inFIG.5B, HMB overlay component113can remove or erase overlay section2from memory sub-system buffer220and subsequently copy overlay section2from host memory buffer210to memory sub-system buffer220. At operation350, the processing device can execute the second set of executable instructions residing in the second memory buffer, in accordance with previously described embodiments.

At operation410, the processing device can determine that the first set of executable instructions is included in a first overlay section of two or more overlay sections. The processing device (e.g., HMB overlay component113) can determine the first set of executable instructions is included in the first overlay section in accordance with previously described embodimerits.

At operation420, the processing device can determine the first overlay section is not present on the first volatile memory device (i.e., memory sub-system buffer220) on the memory sub-system. In some embodiments, the processing device (e.g., HMB overlay component113) can determine the first overlay section212is not present on the first volatile memory device140using the overlay data structure, as previously described. For example, HMB overlay component113can identify an entry of the overlay data structure corresponding to the first overlay section212. HMB overlay component113can determine whether a memory address of the identified entry associated with the first overlay section212corresponds to a memory address for memory sub-system buffer220. In response to determining the memory address does not correspond to a memory address for memory sub-system buffer220, HMB overlay component113can determine the first overlay section212is not present on the first volatile device140.

In some embodiments, in response to determining the first overlay section212is not present on the first volatile device140, HMB overlay component113can determine whether the first overlay section212is present on a second volatile memory device510of host system120(i.e., in host memory buffer210). HMB overlay component113can determine whether a memory address of the identified overlay data structure entry associated with the first overlay section212corresponds to a memory address for host memory buffer210. In response to determining the memory address does not correspond to a memory address for host memory buffer210, HMB overlay component113can determine the first overlay section212does not reside on volatile memory device510.

In response to determining the first overlay section does not reside on volatile memory device510, HMB overlay component113can copy the first overlay section212from non-volatile memory device130to the host memory buffer210, in accordance with previously described embodiments. HMB overlay component113ofFIG.5Acan copy the first overlay section212from non-volatile memory device130to an available portion of host memory buffer210, in accordance with previously described embodiments, In some embodiments, host memory buffer210does not include any portions that are available for copying of the first overlay section212. In such embodiments, HMB overlay component113can identify a candidate overlay section212present in host memory buffer210to remove or erase from host memory buffer210. In some embodiments, HMB overlay component113can identify the candidate overlay section212for removal based on a frequency that instructions of code sections included in candidate overlay section212are executed by memory sub-system controller114. In response to removing or erasing the candidate overlay section212from host memory buffer210, HMB overlay component113can copy the first overlay section212to the available portion of host memory buffer210.100571In an illustrative example, memory sub-system controller11.5can determine a code section included in overlay section N is to be executed. In response to determining that overlay section N is not present in host memory buffer210, HMB overlay component113can determine whether a portion of host memory buffer210is available for copying of overlay section N, Responsive to determining host memory buffer210does not include an available portion, HMB overlay component113can identify a candidate overlay section212to be removed or erased from host memory butler210(e.g., overlay section3). As illustrated with respect toFIG.5C, HMB overlay component113can remove or erase overlay section3from host memory buffer210and copy overlay section N to the newly available portion of host memory buffer210.

Referring back toFIG.4, at operation430, the processing device can copy, via a host interface, the first overlay section from a second memory buffer (e.g., host memory buffer210) of a second volatile memory device of the host system to the first volatile memory device (e.g., to memory sub-system buffer220). In some embodiments, the host interface can be a peripheral component interconnect express (PCIe) interface, HMB overlay component113can copy the first overlay section212from host memory buffer210to the available portion of memory sub-system buffer220. As illustrated inFIG.5C, HMB overlay component113can copy overlay section N from host memory buffer210to memory sub-system buffer220in response to determining a portion of memory sub-system buffer220is available. In other or similar embodiments, memory sub-system buffer220does not include a portion available for copying an overlay section212. In such embodiments, HMB overlay component113can remove or erase an overlay section212present in memory sub-system buffer220and copy the overlay section212including the requested code sections from host memory buffer210to memory sub-system buffer220, in accordance with previously described embodiments. As illustrated inFIG.5C, in response to receiving a request to access overlay N, HMB overlay component113can determine whether memory sub-system buffer220is available for copying of overlay N. In response to determining that memory sub-system buffer330is not available for copying of overlay N, HMB overlay component113can remove or erase overlay section1from memory sub-system buffer220and copy overlay section N from host memory buffer210to memory sub-system buffer220. Referring back toFIG.4, at operation440, the processing device can execute the first set of executable instructions included in the first overlay section, in accordance with previously described embodiments.

The example computer system600includes a processing device602, a main memory604(e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or RDRAM, etc.), a static memory606(e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system618, whiCh communicate with each other via a bus630.