Providing a via with an increased via contact area

An apparatus and method to provide a via with an increased via contact area. A semiconductor support layer is coupled to a dielectric layer and a contact is coupled to the dielectric layer. A via, having an enlarged end within the semiconductor support layer, passes through the semiconductor support layer and the dielectric layer and connects to the contact. In one embodiment, the formation of the via and the enlarged end in the semiconductor support layer are completed in a single dry etch process.

BACKGROUND

1. Field of Invention

The field of invention relates generally to vias and, more specifically, relates to a method and apparatus to provide a via with an increased via contact area.

2. Background Information

Semiconductor dies are typically encased in a shell or package prior to installation in microelectronic devices. The package makes the die easier to handle and protects the die from dust, dirt, and other contaminants. The package usually has leads or contact pads that are soldered to a printed circuit board (PCB). With its leads attached to the PCB, the package acts as an interface between the die and the PCB.

Generally, a die includes dielectric layers attached to a semiconductor support layer. Attached to the dielectric layers are metal layers. In some dies, a via is formed in the semiconductor support and dielectric layers to connect the metal layers to components outside of the die.

In constructing a die package, the diameter of the vias is usually kept to a minimum in order to help reduce electrical interconnect pitch. Electrical interconnect pitch (e.g., bump pitch) is the distance between the center of two electrical interconnects on a die package. In a die package, a via connects to an electrical interconnect which supplies electrical connection out of the package through bumps, pins, leads or other electrical connective items. Smaller diameter vias allow the vias to be placed closer together, and subsequently, reduce the electrical interconnect pitch. A smaller pitch leads to smaller die packages.

However, difficulties arise when a via with a small diameter is connected to a metal layer of a die. The small diameter of the via creates adhesion problems and may result in de-lamination of the via and the metal layer. Also, a connection with a small diameter via may result in undesired levels of electrical resistance in the connection between the via and the metal layer.

DETAILED DESCRIPTION

Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments. In addition, it is appreciated that the figures provided herewith are for explanation purposes to persons ordinarily skilled in the art and that the drawings are not necessarily drawn to scale.

FIG. 1Aillustrates one embodiment of a via having an increased via contact area.FIG. 1Ashows a die package102coupled to a printed circuit board (PCB)104by a solder ball116. Die package102may be a “spider” type package, a wafer-level package, or the like. The die package102includes a semiconductor support layer106disposed proximate to dielectric layer108. Disposed on dielectric layer108is a contact110. Coupled to the contact110is a solder ball120. Coupled adjacent to the contact110is a device (not shown). Such a device includes, but is not limited to, a transistor, capacitor, a resistor or the like. Package102also includes a contact114. A via118, having an increased via contact area122, couples the contact110to contact114.

FIG. 1Billustrates one embodiment of a multi-layer die having at least one via with an increased via contact area. InFIG. 1B, a multi-layer die130includes contacts132,134, and136, where each contact is part of a different layer of the multi-layer die130. Multi-layer die130also includes a conductive layer144and a semiconductor support layer146. In one embodiment, conductive layer144is electrically coupled to a voltage source to provide power to the multi-layer die130. Contact132,134, and136are each coupled to conductive layer144by vias138,140, and142, respectively. Via142includes an increased via contact area as described herein.

FIG. 1Cillustrates one embodiment of stacking dies packages having at least one via with an increased via contact area. InFIG. 1C, stacking die package150is electrically coupled to stacking die package152. Stacking die package152is electrically coupled to PCB154. In one embodiment, at least one of stacking die packages150and152has a via with an increased via contact area as described herein. In another embodiment, stacking die packages150and152each include multi-layer dies having vias with increased via contact areas.

FIG. 2illustrates one embodiment of a die200with a via210having an increased via contact area. In one embodiment, via210is generally cylindrical in shape. Die200includes a semiconductor support layer202laminated to a dielectric layer204. Semiconductor support layer202includes, but is not limited to, silicon, germanium, selenium, or the like. Dielectric layer204includes, but is not limited to, Silicon Dioxide (SiO2), Silicon Nitride (SiNx), or the like. Attached to the dielectric layer204is a contact206. Contact206includes, but is not limited to, aluminum (Al), chromium (Cr), gold (Au), platinum (Pt), molybdenum (Mo), or the like, or any combination thereof. Adjacent to contact206and attached to the dielectric layer204is insulator208. In one embodiment, the contact206is electrically coupled to a device (not shown) of die200. In another embodiment, the contact206is coupled to a solder ball.

Via210is shown passing through the semiconductor support layer202and the dielectric layer204. The via210is attached to contact206. In one embodiment, via210is a metal-filled via. The portion of via210that passes through the semiconductor support layer202includes a bottom end212, a shaft214, and an enlarged end216. The enlarged end216allows for an increased via contact area218for connection of via210to contact206. The bottom end212may be electrically coupled to a PCB or another die package.

In one embodiment, the diameter of the bottom end212and the shaft214are substantially the same. At the enlarged end216, the via extends outward from the center of the via210to form a semi-cone or bowl shape. In one embodiment, the largest diameter of the via at the enlarged end216is twice the diameter of the bottom end212. In an embodiment, the diameter of the bottom end212is 10 to 60 microns. In yet another embodiment, the diameter of the increased via contact area218is 15 to 100 microns.

The via210passes through the dielectric layer204to connect to the contact206at the increased contact area218of the via210. In one embodiment, the diameter of the via210through the dielectric layer204is similar to the largest diameter of the via210at the enlarged end216. In another embodiment, the semi-cone shape at the enlarged end216continues through the dielectric layer204to the contact206.

It will be understood that the enlarged end216of the via210begins in the semiconductor support layer202and increases in diameter as the via210approaches the dielectric layer204. This enlarged end216tapers outward from the center of the via210to create an increased via contact area218for connection to contact206. An increased via contact area adheres better to the contact and decreases the possibilities of de-lamination of the surrounding layers. Also, the large contact area of the via against the contact decreases the electrical resistance in the connection. Additionally, a narrow via diameter may still by used in the die to keep electrical interconnect pitches small, yet gain the advantages of an increased via contact area at the contact206. The increased via contact area218also ensures connectivity to the contact206. The increased via contact area218provides more surface to create a connection with the contact206.

FIG. 3shows a flowchart300illustrating operations performed in accordance with an embodiment of the present invention. Starting in a block302, a semiconductor support layer is dry etched to a dielectric layer of a die to form a via hole. Generally, the dry etch begins on the backside of the die. In one embodiment, dry etching is a deep reactive ion etching process. In general, this deep reactive ion etching technique involves alternating exposure of a wafer to an etchant plasma and a passivant. The process cycles between etching and deposition steps to create an etch with a vertical shape. In one embodiment, the dry etching tool is aligned with a conductive layer coupled to the dielectric layer before dry etching the semiconductor support layer to form the via hole.

Continuing to a block304, the semiconductor support layer is dry etched to form an enlarged end of the via hole. The enlarged end forms a notch in the semiconductor support layer. The enlarged end will create a via with a large contact area to couple the via to a conductive layer within the die. In one embodiment, the dry etch process from block302is allowed to continue and creates a charge on the dielectric layer that repels the ions laterally forming the enlarged end in the semiconductor support layer. The shape of the enlarged end depends on how long the ions are allowed to etch in the semiconductor support layer. For example, the longer the ions are allowed to etch, the wider the enlarged end will be at the dielectric layer. In one embodiment, an anisotropic dry etch forms the via and the enlarged end in a single dry etch process.

In a block306, the dielectric layer is etched to continue the via hole through the dielectric layer to a conductive layer. In one embodiment, the etch through the dielectric layer is conducted with a wet etch process. In another embodiment, the etch through the dielectric layer is conducted with the same dry etch process as was used to etch the via hole and the enlarged end. In another embodiment, the dielectric layer is etched so that the outward taper of the via hole continues from the semiconductor support layer, continues to taper outward through the dielectric layer, to the conductive layer.

Continuing in a block308, the via hole is filled with a conductive material to create a via. In one embodiment, the via hole is filled with a metallized paste to form a metal-filled via. In another embodiment, a Chemical Vapor Deposition (CVD) process is used to fill the via hole.

In a block310, the via is connected to the conductive layer. In one embodiment, a chemical reflow process is used to couple the enlarged end of the via to the conductive layer. In another embodiment, a thermal reflow process is used to connect the via to the conductive layer.

It will be appreciated that the via hole and the enlarged end in the semiconductor support layer may be completed in a single dry etch process. The diameter of the via is narrow along most of the depth of the via and increased at one end to increase the via contact area with the conductive layer. The etch of the semiconductor support layer, including the via hole and the enlarged end, can be completed in a single dry etch process; the use of build up layers is not required to create the enlarged end of the via. Thus, a large diameter via does not have to extend along the entire depth of the via, but only the diameter of the via at one end is increased to connect with the conductive layer.

FIG. 4is an illustration of one embodiment of an example computer system400that can be implemented in conjunction with an embodiment of the presently claimed invention. Computer system400includes a processor410, a memory420, and an input/output controller430. Bus440is coupled to each of processor410, memory420and input/output controller430. Processor410may be a conventional microprocessor including, but not limited to, an Intel Corporation x86, Pentium, or Itanium family microprocessor, a Motorola family microprocessor, or the like. Memory420includes Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Synchronized Dynamic Random Access Memory (SDRAM), Rambus Dynamic Random Access Memory (RDRAM), or the like. An input/output device (not shown) may be coupled to input/output controller430. Such an input/output device includes, but is not limited to, a keyboard, a disk drive, a printer, a scanner and other input and output devices, including a mouse, trackball, trackpad, joystick, or other pointing device. In computer system400, any one of the processor410, memory420, and input/output controller430may include a die package having a via with an increased via contact area as described herein.

In the foregoing detailed description, the method and apparatus of the present invention have been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present invention. The present specification and figures are accordingly to be regarded as illustrative rather than restrictive.