Fast and accurate sensing amplifier for low voltage semiconductor memory

A memory sensing circuit and method that can achieve both a wide read margin and a fast read time. Roughly described, a target cell draws a target cell current from a first node when selected. The target cell current depends on the charge level stored in the target cell. A reference cell draws a reference cell current from a second node when selected, and a current difference generator generates into a third node a third current flow positively dependent upon the difference between the target cell current and the reference cell current. The current difference generator also generates into a fourth node a fourth current flow negatively dependent upon the difference between the target cell current and the reference cell current. A sense amplifier has its first input connected to the third node and a second input connected to the fourth node.

BACKGROUND

The present invention relates to semiconductor memory devices, and more particularly to sensing schemes for such devices.

Memory devices are known in the art for storing data in a wide variety of electronic devices and applications. A typical memory device comprises a number of memory cells. Often, memory cells are arranged in an array format, where a row of memory cells corresponds to a word line and a column of memory cells corresponds to a bit line, and where each memory cell defines a binary bit, i.e., either a zero (“0”) bit or a one (“1”) bit.

Typically, the state of a memory cell is determined during a read operation by sensing the current drawn by the memory cell. According to one particular embodiment, the current drawn by a particular memory cell is ascertained by connecting the drain terminal of the memory cell to a sensing circuit, where the source terminal of the memory cell is connected to ground, and the gate of the memory cell is selected. The sensing circuit attempts to detect the current drawn by the memory cell, by comparing the sensed memory cell current against a reference current. If the sensed memory cell current exceeds the reference current, the memory cell is considered an erased cell (e.g., corresponding to a “1” bit). If the sensed memory cell current is below the reference current, the memory cell is considered a programmed cell (e.g., corresponding to a “0” bit).

In practice, it is desirable to have the sensed memory cell current be greater than or less than the reference current by a sufficient margin (referred to herein as the “read margin” in the present application) so as to accurately identify the charge level stored by the memory cell. However, when high density memory devices are implemented with a low supply voltage (“VCC”), such as 1.8 volts, for example, the read margin is significantly reduced. When the read margin is significantly reduced, the reliability of sensing the memory cell current also decreases. The reliability and accuracy of the read operation are thus reduced, resulting in poor performance of the memory device.

Accordingly, there is a strong need in the art to overcome deficiencies of known sensing circuits and to provide a fast and accurate sensing circuit and technique for low voltage semiconductor memory devices.

SUMMARY

Roughly described, the invention involves a sensing circuit for a target memory cell, in which the target cell draws a target cell current from a first node in response to selection of the target cell. The target cell current depends on the charge level stored in the target cell. A reference cell draws a reference cell current from a second node in response to selection of the reference cell, and a current difference generator generates into a third node a third current flow positively dependent upon the difference between the target cell current and the reference cell current. The current difference generator also generates into a fourth node a fourth current flow negatively dependent upon the difference between the target cell current and the reference cell current. A sense amplifier has its first input connected to the third node and a second input connected to the fourth node. Embodiments of the invention can thus achieve both a wide read margin and a fast read time.

DETAILED DESCRIPTION

The following detailed description is made with reference to the figures. Preferred embodiments are described to illustrate the present invention, not to limit its scope, which is defined by the claims. Those of ordinary skill in the art will recognize a variety of equivalent variations on the description that follows.

FIG. 1illustrates a conventional sense amplifier arrangement in which the drain terminal of a target nonvolatile memory cell110is cascode-connected through a selection transistor112with a bias transistor114. The current Icell through the cascode combination is converted to a voltage DL at the drain116of the bias transistor114, by PMOS active load transistor118connected between drain116and Vdd. On the reference side, the drain terminal of a reference cell120is cascode-connected through a selection transistor122with a bias transistor124. The current Iref through the cascode combination is converted to a voltage DL at the drain126of the bias transistor124, by a PMOS load transistor128which is connected in a current mirror arrangement with the transistor118on the target side. As long as Icell is stable, the voltage DL will be stable and the voltage DR will depend on the difference between Icell and Iref. The difference between the two voltages DL and DR is amplified by a second stage sense amplifier130, triggered by a sense enable signal132.

In a low supply voltage environment, however, the arrangement ofFIG. 1suffers from the problem that the read margin of the second stage sense amplifier130is reduced because of the need to operate both current mirror transistors118and128in the saturation region. This reduces the available voltage for DL on the higher end of the range, and flash cell drain bias requirements limit the available voltage on the lower end of the range. The narrow voltage swing results in a long waiting time for the sensing signal to build up to a magnitude that is sufficiently reliable to trigger the second stage sense amplifier130.

FIG. 2illustrates a second conventional sense amplifier arrangement that alleviates the narrow voltage swing problem ofFIG. 1. In the arrangement ofFIG. 2, the series connection of transistors on the target side is roughly the same as that inFIG. 1, involving the target memory cell210cascode-connected through a selection transistor212with a bias transistor214. The current Icell through the cascode combination is drawn from the drain216of a PMOS active load transistor218connected between drain216and Vdd. Similarly, the series connection of transistors on the reference side is also roughly the same as that inFIG. 1, involving the target memory cell220cascode-connected through a selection transistor222with a bias transistor224. The current Iref through the cascode combination is drawn from the drain226of a PMOS active load transistor228connected between drain226and Vdd. On the target side, however, node216is not connected directly to the target side of second stage sense amplifier230. Instead the load transistor218is connected in a current mirror arrangement with another transistor240, which outputs a copy of Icell through a load resistance242to ground. The load resistance242converts the current to a voltage SAIN at the source node244of the transistor240, and this is the voltage node that is provided to the target side of second stage sense amplifier230. Similarly, on the reference side, node226is not connected directly to the reference side of second stage sense amplifier230. Instead the load transistor228is connected in a current mirror arrangement with another transistor250, which outputs a copy of Iref through another load resistance252to ground. The load resistance252converts the current to a voltage SREF at the source node254of the transistor250, and this is the voltage node that is provided to the reference side of second stage sense amplifier230. An equalization transistor260is also added, the control gate of which receives an EQ signal262. Equalization transistor260equalizes the SAIN and SREF voltages prior to the start of the reading process.

The arrangement ofFIG. 2alleviates the problem of narrow voltage swing in low voltage environments not because of any increase in the available voltage for SAIN on the higher end of the range of available voltages, but because the flash cell drain bias requirements no longer limit the available voltage on the lower end of the range. The load resistance242also can be made large enough to amplify the voltage swing of SAIN in response to the swing of the current Icell. The same is true on the reference side. The transistors240and250also can be made larger (wider) than the corresponding transistors218and228, so that the mirrored current driven into the resistances242and252are larger than Icell and Iref, respectively.

Although theFIG. 2arrangement can provide increased read margin in the low voltage environment, typically it does so at the expense of a longer waiting time for sensing signal buildup.FIG. 3illustrates the voltage changes over time after the EQ signal turns off and sensing begins. In the example ofFIG. 3, the target cell is in its erased state. Curve310inFIG. 3illustrates the EQ signal262turning off at a time T0. Curve312illustrates the subsequent voltage change for the voltage SAIN, and curve314illustrates the subsequent voltage change for the voltage SREF. Since the target cell210is in its erased state, Icell is larger than Iref, and SAIN moves toward a higher voltage than does SREF. But since both voltages start from an equalized voltage that is lower than the ultimate values of both SAIN and SREF, the trajectories of both voltages are in the same (upward) direction. If the criteria for sensing is for example 100 mV difference between SAIN and SREF, then the device has to wait until time T2before the second stage sense amplifier230can be enabled. The same is true if the target cell is in its programmed state. The only difference would be that SAIN increases more slowly than SREF, toward an ultimate value that is below the ultimate value of SREF. The device still must wait until at least time T2before the difference between the two signals reaches the required 100 mV difference.

FIG. 4is an arrangement that alleviates the narrow voltage swing of theFIG. 1arrangement without incurring the lengthy sensing signal buildup time of theFIG. 2arrangement. InFIG. 4, the source of an N-channel target cell410is connected to ground. The drain412of target cell410is connected, through cell selection circuitry, optional cascode circuitry, as well as perhaps other circuitry, to a node414, such that the cell410is drawing a current Icell from the node414. The value of current Icell depends in the usual manner on the charge stored in the cell410: if the cell is in its erased state, then the current Icell has a larger magnitude than if the cell is in its programmed state.

Similarly on the reference side, the source of an N-channel reference cell420is connected to ground. The drain422of this cell is connected, again through cell selection circuitry, optional cascode circuitry as well as perhaps other circuitry, to a node424, such that the cell420is drawing a current Iref from the node424. The value of the current Iref is, in the usual manner, in between the value drawn by target cell410when it is in the program state and the value drawn by target cell410when it is in the erased state.

The node414is connected to one input442of a current difference generator440, and the node424is connected to a second input444of the current difference generator440. The current difference generator440has an output446which carries a current that is positively dependent on the difference between the current on input terminal442and the current on input terminal444. The current difference generator440also has a second output448, which carries a current that is negatively dependent on the difference between the current on input terminal442and the current on input terminal444. As used herein, an output current is “positively dependent” upon an input current if, throughout its operating range, an increase in the input current yields an increase in the output current; that is, there is no sign change. An output current is “negatively dependent” upon an input current if, throughout its operating range, an increase in the input current yields a decrease in the output current. Preferably in both cases inFIG. 4the dependency is simply a constant of proportionality, and preferably both constants are equal. That is, Iout(446)=K(Icell−Iref), and Iout(448)=K(Iref−Icell). In one embodiment K=1 whereas in another embodiment K>1. A value of K>1 can further improve the reading speed, but it consumes more current from Vdd, requires certain transistors to occupy a larger chip area, and complicates layout matching issues. However, other acceptable types of positive or negative dependencies will be apparent to the reader.

The output terminal446of current difference generator440is connected to an SD node450, which is connected to the inverting input434of a second stage sense amplifier430. Similarly, the output terminal448of the current difference generator440is connected to an SR node452, which is connected to the non-inverting input436of the second stage sense amplifier430. The second stage a sense amplifier430has a high equivalent input impedance on its inverting input434, which effectively converts the current flowing into node450into a voltage. Similarly, the second stage sense amplifier430has a high equivalent input impedance on its non-inverting input436, which effectively converts the current flowing into node452into a voltage. The second stage sense amplifier430also has a sense enable input, in response to which the amplifier430will amplify the difference between the voltages on its two inputs. The circuit ofFIG. 4also includes an equalization transistor460connected between SD node450and SR node452, so as to equalize the voltages on the two nodes, prior to sensing, in response to a signal on its gate terminal462.

Returning toFIG. 3, curve316illustrates the movement of the voltage on SD node450after removal of the equalization signal, in a situation where target cell410is in its erased state. Curve318illustrates the movement of the voltage on SR node452in the same situation. If the target cell410were in its programmed state, and the two curves would be interchanged. It can be seen that because the current flowing into each of the two nodes is the opposite of the current flowing into the other, the two voltages move in opposite directions, one increasing of the other decreasing during sensing signal buildup. Thus if the criteria for sensing is 100 mV, as it was for theFIG. 2arrangement, the difference between the SD and SR voltages reaches this value at a time T1, which is much sooner than T2. The sensing operation can therefore be much quicker in the arrangement ofFIG. 4than in the arrangement ofFIG. 2, all other things being equal. And as mentioned, the sensing operation can be made even quicker by designing a larger value of K, if the downsides mentioned above of the larger value of K can be tolerated.

The current difference generator440can be designed using a variety of different kinds of circuitry, as will be apparent to the reader.FIG. 5illustrates a preferred embodiment of current difference generator440. It includes two P-channel current mirrors510and520and two N-channel current mirrors530and540. Current mirror510has an input512connected to input terminal442of the current difference generator440, and an output514connected to output terminal446of the current difference generator440. Current mirror510also has a second output516that is connected to an input532of N-channel current mirror530. Similarly, current mirror520has an input terminal522connected to input terminal444of the current difference generator440, and an output524connected to output448of current difference generator440. Current mirror520also has a second output526connected to an input542of N-channel current mirror540. N-channel current mirror530further has an output534connected to the output terminal448of the current difference generator440, and the current mirror540further has an output terminal544connected to the output terminal446of the current difference generator440. All the current mirrors are designed to replicate on their outputs the same current magnitude as provided on their inputs. It will be appreciated that in other embodiments, current mirrors can be used that generate output currents which depend by a different relationship on the input current magnitudes. For example, if it is desired to implement K>1, then each of the current mirrors510and520can be designed to drive each of their outputs with K times their respective input current Icell or Iref.

As used herein, a current value can be positive or negative, and depends on an arbitrarily defined current flow “direction”. That is, a positive current flow from a node A toward a node B in a circuit is the same as a negative current flow from node B toward node A. Similarly, when current is said to be “drawn from” a particular node, this language by itself does not require that the current be positive when drawn from the particular node. The current “drawn from” the particular node can be negative, which would be the same as saying that a positive current is flowing into the particular node. In the same way, nor does a current said to be “driven into” a particular node require that the current be positive when driven into the particular node. Finally, the labeling of a current mirror terminal as an “input” or an “output” does not define either its current flow direction or its current flow sign. It merely differentiates between controlling terminals (labeled “inputs”) and controlled terminals (labeled “outputs”).

In operation, N-channel current mirror540draws into its output544current equal to the reference cell current Iref. This current is drawn from the output terminal446of current difference generator440, which also receives a current equal to the target cell current Icell. Thus the current flowing into SD node450(FIG. 4) is equal to the difference between the two current levels, Icell−Iref. Similarly, N-channel current mirror530draws into its output534current equal to the target cell current Icell. This current is drawn from the output terminal448of current difference generator440, which also receives a current equal to the reference cell current Iref. Thus the current flowing into SR node452(FIG. 4) is equal to the difference between the two current levels, Iref−Icell, which is the negative of the current flowing into SD node450.

The P-channel current mirrors510and520can be designed using a variety of different kinds of circuitry, as will be apparent to the reader.FIG. 6illustrates a preferred embodiment of current mirror510. Current mirror520is similar. Referring toFIG. 6, current mirror510includes three P-channel transistors610,612and614. The source terminals of all three transistors are connected together and to the power supply voltage Vdd. The gate terminals of all three transistors are connected together and to the drain terminal of transistor610. The drain terminal of transistor610is also connected to the input terminal512of current mirror510. Similarly, the drain terminals of transistors612and614are connected respectively to the output terminals514and516of current mirror510. The geometries of the three transistors610,612and614are matched so that current flowing into the input terminal512is mirrored on each of the output terminals514and516. Non-unity constants of proportionality (K) can be implemented if desired in a particular embodiment, using well-known variations in the transistor geometries.

The N-channel current mirrors530and540also can be designed using a variety of different kinds of circuitry, as will be apparent to the reader.FIG. 7illustrates a preferred embodiment of current mirror530. Current mirror540is similar. Referring toFIG. 7, current mirror530includes two N-channel transistors710and712. The source terminals of both transistors are connected together and to ground, and the gate terminals of both transistors are connected together and to the drain of transistor710. The drain of transistor710is also connected to input terminal532of the current mirror530, and the drain of transistor712is connected to the output terminal534of current mirror530. The geometries of the two transistors and710and712are matched so that current flowing into the input terminal532is mirrored on the output terminal534. As with the P-channel current mirrors510and520, non-unity constants of proportionality can be implemented if desired in a particular embodiment, using well-known variations in the transistor geometries.

FIG. 8is a circuit diagram of an embodiment of the invention, showing the various components together. It includes a target memory cell810having a drain connected to a node N1through selection circuitry814and bias transistor816. The target memory cell810draws a target memory cell current Icell from node N1when activated during a read operation. A reference memory cell818has its drain connected to a second node N2through another selection circuit822and another bias transistor824. The reference memory cell818draws a reference memory cell current Iref from node N2when activated during the read operation. The circuit includes a current mirror including two transistors Q1and Q2, the target memory cell current Icell flowing separately from drains of these two transistors into respectively the node N1and a node N3. Another current mirror includes transistors Q3and Q4, the target memory cell current Icell flowing separately from the node N3and another node N4to drains of the transistors Q3and Q4. The sources of transistors Q3and Q4are connected to ground. Another current mirror includes transistors Q5and Q6, the reference memory cell current Iref flowing separately from drains of transistors Q5and Q6respectively to the node N2and to another node N5. Another current mirror includes transistors Q7and Q8, the reference memory cell current Iref flowing separately from node N5and another node N6into drains of the transistors Q7and Q8. The sources of the transistors Q7and Q8are both connected to ground. Another transistor Q9and the transistor Q1form yet another current mirror, the target memory cell current Icell flowing from a drain of the transistor Q9to the node N6. Another transistor Q10and the transistor Q5form yet another current mirror, the reference memory cell current Iref flowing from a drain of the transistor Q10to the node N4. The circuit further includes a sense amplifier830having first and second inputs connected respectively to the nodes N6and N4. It can be seen that in the circuit ofFIG. 8, the difference between the target memory cell current Icell and reference memory cell current Iref flows in opposite signs into respectively the first and second inputs of sense amplifier830. In addition, it will be appreciated that a non-unity value of K can be implemented by an appropriate variation in the geometries of transistors Q2and Q9relative to that of transistor Q1, and by an appropriate variation in the geometries of transistors Q6and Q10relative to that of transistor Q5. For example, transistors Q2and Q9can be made with a channel width that is K times that of transistor Q1, and transistors Q6and Q10can be made with a channel width that is K times that of transistor Q5.

As used herein, a given signal, event or value is “responsive” to a predecessor signal, event or value if the predecessor signal, event or value influenced the given signal, event or value. If there is an intervening processing element, step or time period, the given signal, event or value can still be “responsive” to the predecessor signal, event or value. If the intervening processing element or step combines more than one signal, event or value, the signal output of the processing element or step is considered “responsive” to each of the signal, event or value inputs. If the given signal, event or value is the same as the predecessor signal, event or value, this is merely a degenerate case in which the given signal, event or value is still considered to be “responsive” to the predecessor signal, event or value. “Dependency” of a given signal, event or value upon another signal, event or value is defined similarly.

The foregoing description of preferred embodiments of the present invention has been provided for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations will be apparent to practitioners skilled in this art. For example, the invention may also be viewed as a method for sensing a charge level on a target memory cell, by performing the steps that are performed by the circuitry described herein. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the following claims and their equivalents.