Methods for fabricating an integrated circuit

Methods are provided for reducing the aspect ratio of contacts to bit lines in fabricating an IC including logic and memory. The method includes the steps of forming a first group of device regions to be contacted by a first level of metal and a second group of memory bit lines to be contacted by a second level of metal, the first level separated from the second level by at least one layer of dielectric material. Conductive material is plated by electroless plating on the device regions and bit lines and first and second conductive plugs are formed overlying the conductive material. The first conductive plugs are contacted by the first level of metal and the second conductive plugs are contacted by the second level of metal. The thickness of the plated conductive material provides a self aligned process for reducing the aspect ratio of the conductive plugs.

TECHNICAL FIELD

The present invention generally relates to methods for fabricating integrated circuits, and more particularly relates to methods for fabricating integrated circuits having contacts with a reduced aspect ratio.

BACKGROUND

Integrated circuits (ICs) are made up of a plurality of interconnected transistors and other components. Complex ICs require several levels of metallization to properly interconnect all of the devices to power the devices, convey input and output signals, address and timing signals, and the like. The several levels of metallization are separated by layers of dielectric material (inter layer dielectric or ILD). Openings are selectively etched through the various ILD layers and those openings are filled with metal or other conductive material to route the signals between devices as needed to implement the desired circuit function.

As the complexity of ICs increases, the number of devices increases, the number of necessary interconnections increases, and the size of individual devices shrinks. Each generation of integrated circuits is characterized by a minimum feature size; that is the minimum line width or the minimum spacing between lines that is used in designing the individual devices. The reduction in feature size is not generally accompanied by a corresponding reduction in the thickness of layers used to fabricate the IC such as the thickness of metal layers, polycrystalline silicon layers, and ILD layers. Accordingly, the cross sectional area of the openings etched through ILD layers decreases more rapidly than the depth of the opening. The aspect ratio, the ratio of opening width to opening depth, thus increases as the IC size and complexity increases. High aspect ratio openings are difficult to reliably etch and fill with metal or other conductive material, leading to reliability issues and increased manufacturing cost.

Accordingly, it is desirable to provide reliable methods for manufacturing complex integrated circuits. In addition, it is desirable to provide self aligned methods for fabricating ICs with reduced aspect ratio contact openings. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.

BRIEF SUMMARY

Methods are provided for reducing the aspect ratio of contacts to a bit line in fabricating an IC including logic and memory. In accordance with one embodiment of the invention the method includes the steps of forming a first group of device regions to be contacted by a first level of metal and a second group of memory bit lines to be contacted by a second level of metal, the first level separated from the second level by at least one layer of dielectric material. Conductive material is plated by electroless plating in electrical contact with the device regions and the bit lines and first and second conductive plugs are formed overlying the conductive material. The first conductive plugs are contacted by the first level of metal and the second conductive plugs are contacted by the second level of metal. The thickness of the plated conductive material provides a self aligned process for reducing the aspect ratio of the conductive plugs and the conductive openings the plugs fill.

DETAILED DESCRIPTION

FIGS. 1-10illustrate, in cross section, a portion of an integrated circuit (IC)20and method steps for its fabrication in accordance with various embodiments of the invention. For purposes of illustration only, IC20is an MOS integrated circuit, and in particular is a complementary MOS (CMOS) microprocessor integrated circuit including embedded dynamic random access memory (DRAM), although the invention also is applicable to other IC structures. Various steps in the manufacture of MOS circuits are well known and so, in the interest of brevity, many conventional steps will only be mentioned briefly herein or will be omitted entirely without providing the well known process details. Although the acronym “MOS device” properly refers to a device having a metal gate electrode and an oxide gate insulator, that term will be used throughout to refer to any semiconductor device that includes a conductive gate electrode (whether metal or other conductive material) that is positioned over a gate insulator (whether oxide or other insulator) which, in turn, is positioned over a semiconductor substrate.

Only a small portion of exemplary IC20will be described and illustrated in the figures. In a logic portion22of microprocessor IC20only a single MOS transistor24will be illustrated, and in a memory portion25of the IC only a single memory cell26will be illustrated. Memory cell26will be shown to include a word line28, a bit line30and a memory storage capacitor32. Those of skill in the art of fabricating MOS and other types of integrated circuits will understand that an IC such as IC20will include a significant number of transistors24and a significant number of memory cells26. The memory portion of IC20typically includes a plurality of N-channel MOS (NMOS) transistors and the logic portion of the IC typically includes a plurality of NMOS transistors as well as a plurality of P-channel MOS (PMOS) transistors.

As will be explained below, the source and drain regions of logic transistor24as well as the memory storage capacitor may be coupled to one metal interconnect layer and the bit lines of memory cell26may be coupled to another metal interconnect layer with the two metal interconnect layers separated by at least one interlayer dielectric (ILD) layer. In prior art structures and methods the contact openings connecting, for example, the bit lines to an upper layer of metal interconnect have a high aspect ratio and are difficult to etch and to fill with a conductive material in a reliable and easily manufactured manner. In accordance with an embodiment of the invention the aspect ratio of contact openings, especially those previously having a high aspect ratio, is reduced by selectively depositing a conductive material on the contact areas in a self aligned manner to “prefill” the contact openings.

As illustrated in cross section inFIG. 1, the manufacture of CMOS IC20in accordance with an embodiment of the invention begins with providing a semiconductor substrate36in and on which MOS transistor24and memory cell26are fabricated. The initial steps in the fabrication of MOS IC20are conventional and will not be described in detail. The semiconductor substrate is preferably a silicon substrate wherein the term “silicon substrate” is used herein to encompass the relatively pure silicon materials typically used in the semiconductor industry as well as silicon admixed with other elements such as germanium, carbon, conductivity determining dopant impurities, and the like. Semiconductor substrate36will hereinafter be referred to for convenience but without limitation as a silicon substrate although those of skill in the semiconductor art will appreciate that other semiconductor materials such as germanium, gallium arsenide, or other semiconductor material could be used. Silicon substrate36may be a bulk silicon wafer (not illustrated), or may be a thin layer of silicon38on an insulating layer40(commonly know as silicon-on-insulator or SOI) that, in turn, is supported by a carrier wafer42. Thin silicon layer38typically has a thickness of less than about 100 nanometers (nm) depending on the circuit function being implemented, and in certain applications preferably has a thickness of about 50 nm or less. The thin silicon layer preferably has a resistivity of at least about 1-35 Ohms per square. The silicon can be impurity doped either N-type or P-type, but preferably is initially doped P-type. Dielectric insulating layer40, typically silicon dioxide, preferably has a thickness of about 50-200 nm.

Isolation regions48are formed that extend through monocrystalline silicon layer38to dielectric insulating layer40. The isolation regions are preferably formed by well known shallow trench isolation (STI) techniques in which trenches are etched into monocrystalline silicon layer38, the trenches are filled with a dielectric material such as deposited silicon dioxide, and the excess silicon dioxide is removed by chemical mechanical planarization (CMP). STI regions48provide electrical isolation, as needed, between various devices of the CMOS circuit that are to be formed in monocrystalline silicon layer38. As illustrated, the STI provides electrical isolation between what will become logic portion22of the IC and memory portion25. Either before or after fabrication of the STI regions selected portions of silicon layer38can be impurity doped, for example by ion implantation. For example, P-type well50can be impurity doped for the fabrication of NMOS transistors of memory portion25of IC20and N-type well52can be impurity doped N-type for the fabrication of PMOS transistor24of logic portion22. Additional wells (not illustrated) can be doped P-type for the fabrication of NMOS transistors of logic portion22.

A layer of gate insulator54is formed on surface56of silicon layer38. The gate insulator may be thermally grown silicon dioxide formed by heating the silicon substrate in an oxidizing ambient, or may be a deposited insulator such as a silicon oxide, silicon nitride, a high dielectric constant insulator such as HfSiO, or the like. Deposited insulators can be deposited in known manner, for example, by chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), semi-atmospheric chemical vapor deposition (SACVD), or plasma enhanced chemical vapor deposition (PECVD). Gate insulator54is here illustrated as a deposited dielectric material that deposits uniformly on surface56of silicon layer38as well as on the surface of STI region48. The gate insulator material is typically 2-10 nm in thickness. In accordance with one embodiment of the invention a layer of gate electrode forming material58, preferably polycrystalline silicon, is deposited onto the layer of gate insulator. Other electrically conductive gate electrode forming materials such as metals and metal silicides may also be deposited instead of polycrystalline silicon. The gate electrode forming material will hereinafter be referred to as polycrystalline silicon although those of skill in the art will recognize that other materials can also be employed. If the gate electrode material is polycrystalline silicon, that material is typically deposited to a thickness of about 50-200 nm and preferably to a thickness of about 100 nm by LPCVD by the hydrogen reduction of silane. The layer of polycrystalline silicon is preferably deposited as undoped polycrystalline silicon and is subsequently impurity doped by ion implantation. A layer of hard mask material60such as a layer of silicon oxide or silicon nitride is deposited overlying the layer of polycrystalline silicon. The layer of hard mask material can be deposited, for example, by LPCVD or PECVD to a thickness of about 40-50 nm.

As illustrated inFIG. 2, the layer of hard mask material and the layer of polycrystalline silicon gate electrode forming material are patterned and etched to form word lines28in memory portion25of IC20. The word lines are overlaid by the patterned hard mask material. The hard mask material and the polycrystalline silicon can be patterned by conventional photolithographic processing and can be etched by plasma etching. The hard mask material can be etched, for example, by using a using CF4or CHF3chemistry and the polycrystalline silicon can be etched by using a chlorine or HBr/O2chemistry. In a preferred embodiment the hard mask material, polycrystalline silicon layer, and gate insulator are removed from the logic portion of the IC.

The method in accordance with an embodiment of the invention continues, as illustrated inFIG. 3, by again forming a layer62of gate insulating material on surface56of silicon layer38in the logic portion of IC20. Layer62can be thermally grown or can be deposited in the same manner and selected from the same materials as gate insulator layer54. Gate insulator62is here illustrated as a deposited dielectric material that deposits uniformly on surface56as well as on STI region48and word line28. Layer62can be about 1-10 nm in thickness and preferably is thinner than is gate insulator layer54. A layer64of gate electrode forming material such as polycrystalline silicon is deposited over layer62of gate insulator material. The gate electrode forming material can have a thickness of about 50-200 nm and preferably has a thickness of about 100 nm.

As illustrated inFIG. 4, layer64of gate electrode forming material is patterned and etched to form gate electrode66of MOS transistor24in the logic portion of IC20and to remove layer64from the memory portion of the IC. Hard mask layer60protects word line28during the etching of gate electrode forming material layer64. Preferably gate insulator layer54is thicker than gate insulator layer62to minimize the leakage current in the memory portion of the circuit. In addition, the thin gate insulator of MOS transistors24in the logic portion of the IC maximizes the drive current capability and speed of the logic circuitry.

Following the patterning of gate electrodes66a layer of sidewall spacer forming material (not illustrated) is blanket deposited over the structure including over word line28and gate electrodes66. The sidewall spacer forming material can be, for example, silicon dioxide, silicon nitride, silicon oxynitride, or other dielectric material. The sidewall spacer forming material can be deposited, for example, by LPCVD to a thickness of about 40-50 nm. The sidewall spacer forming material is anisotropically etched, for example by reactive ion etching (RIE) using a CHF3, CF4, or SF6chemistry to form sidewall spacers68on the side walls of word lines28and sidewall spacers70on the side walls of gate electrodes66as illustrated inFIG. 5.

Sidewall spacers68, word line28, and STI48are used as an ion implantation mask and N-type conductivity determining ions such as arsenic ions or phosphorous ions are implanted into thin silicon layer38to form a memory storage capacitor contact72and a bit line30as illustrated inFIG. 5. The same ion implantation can be used to form the source and drain regions (not illustrated) of the NMOS transistors of the logic portion of IC20. During the N-type implantation other parts of the IC structure such as the PMOS transistors of the logic portion can be masked with a patterned photoresist layer in conventional manner. The masking photoresist is removed and another layer of photoresist (not illustrated) is applied and patterned to mask the memory cells and the NMOS transistors of logic portion22. Sidewall spacers70, gate electrodes66, and STI48are used as an ion implantation mask and P-type conductivity determining ions such as boron ions are implanted into thin silicon layer38to form source74and drain76regions of PMOS transistor24. As those of skill in the art will understand, the order of the N-type and P-type implantations can be reversed. Although only one set of side wall spacers and one ion implantation have been illustrated for each portion of the IC, those of skill in the art will recognize that additional spacers and implantations can be used to form halo implants and drain extensions, set threshold voltage, and the like. Sidewall spacers68and70can also be used as an etch mask to remove any oxide or other material from and to expose the surface of the source and drain regions, bit lines, and surface portion of the memory storage capacitor contact.

After etching to expose the surface of the source and drain regions, a layer of silicide forming metal (not illustrated) such as cobalt, nickel, rhenium, ruthenium, or palladium, or alloys of those metals, and preferably either cobalt or nickel is blanket deposited over the structure and in contact with the ion implanted areas. The silicide forming metal can be deposited, for example, by sputtering to a thickness of about 5-30 nm. The silicide forming metal is heated, for example by rapid thermal annealing (RTA) to react the silicide forming metal with exposed ion implanted silicon to form metal silicide contacts78on source and drain regions74and76, metal silicide contact80on bit line30, and metal silicide contact82on memory storage capacitor contact72as illustrated inFIG. 6. Metal that is not reacted, for example the metal in contact with the side wall spacers and STI, can be removed by wet etching in a H2O2/H2SO4or HNO3/HCl solution.

In accordance with an embodiment of the invention a layer84,86,88of metal or other conductive material is selectively deposited on the metal silicide contacts78,80,82, respectively, as illustrated inFIG. 7. Preferably the selectively deposited material is a layer of cobalt tungsten deposited by electroless deposition from solution. Phosphorus and/or boron may be added to the deposited cobalt tungsten to aid in selectivity and uniformity of deposition. In a preferred embodiment a thin seed layer90is selectively deposited on the metal silicide layers and thicker layers84,86,88are selectively deposited on the seed layer. Seed layer90can be, for example, a layer of palladium having a thickness of ranging from one monolayer to about 3 nm. The seed layer of palladium is preferably deposited by electroless deposition from a solution of palladium acetate and acetic acid. Thicker layers84,86,88are preferably selectively deposited by electroless deposition from a solution such as a solution of cobalt sulphate heptahydrate, ammonium tungstate, and sodium hypophosphite with the possible addition of buffering agents, complexing agents and pH balancers. Chemicals such as dimethylamine borane can be added as a source of boron. Other electroless deposition solutions for this application, some proprietary, are available from the vendors of electroless deposition equipment. Using such a solution, metal layers84,86,88can be selectively deposited onto seed layer90to a thickness of about 500-800 nm indicated by arrow89with a solution temperature from about 65° C. to about 75° C. Exact deposition times and temperatures depend on the particular deposition solution and the particular deposition equipment that is used. Although in the preferred method seed layer90is preferably palladium deposited by an electroless deposition process and the thicker layers are a metal layer including at least cobalt and tungsten, the inventive method is not limited to these materials or to an electroless deposition process. Other conductive materials and other selective deposition techniques can also be used although for ease of discussion the selectively deposited conductive material will hereinafter be referred to as a metal. For example, the thicker layers can be pure tungsten deposited by a selective CVD technique. Metal silicide contacts78,80,82are self aligned to their respective ion implanted areas; selectively deposited metal layers84,86,88are also self aligned to those ion implanted areas. The selectively deposited conductive material serves to “prefill” contact openings that are subsequently formed as will be explained below.

A dielectric layer92is deposited overlying the selectively deposited conductive material and surface94of the dielectric layer is preferably planarized, for example by CMP as illustrated inFIG. 8. Dielectric layer92is preferably deposited by CVD, LPCVD, SACVD, or PECVD to a thickness greater than the height of the word line structure. Layer92can be, for example, a layer of silicon oxide deposited from a tetraethylorthosilicate (TEOS) source. Contact openings96are etched through dielectric layer92to expose selectively deposited metal84overlying the source74and drain76regions of MOS transistor24and contact opening98is etched through dielectric layer92to expose selectively deposited metal88overlying memory storage capacitor contact72. In accordance with one embodiment of the invention a thin layer of dielectric100is deposited on the portion of selectively deposited metal88to form the capacitor dielectric of the memory storage capacitor. Dielectric100is preferably a layer of high dielectric constant material such as HfSiO2or the like deposited by LPCVD. Dielectric100can be removed from the other contact openings by conventional photoresist patterning and etching.

Electrically conductive plugs102and104are formed in contact openings96and98, respectively, as illustrated inFIG. 9. There are a number of well know methods for forming conductive plugs. In one such method a layer of titanium is deposited, a layer of titanium nitride or other barrier layer is formed over the layer of titanium, and tungsten is deposited to fill the contact opening. The excess titanium, titanium nitride, and tungsten are removed from the surface of dielectric layer92by CMP. Contact plug104forms the top electrode of memory storage capacitor32. The memory storage capacitor includes contact plug104, capacitor dielectric100, and deposited layer88. Deposited layer88is electrically coupled to metal silicide contact82and to ion implanted contact area72. The memory storage capacitor is selectively coupled to bit line30by a channel108in thin silicon layer38beneath and controlled by the potential on word line28. A layer of interconnect metallization110is formed on or embedded in surface94of dielectric layer92. The layer of interconnect metallization is coupled to the source and drain of logic transistor24to convey necessary signals to and from that transistor. The layer of interconnect metallization is also coupled to memory storage capacitor32. The layer of interconnect metallization is typically formed of aluminum or an aluminum alloy or of copper or a copper alloy. Aluminum metallization and copper metallization are patterned by different processes; aluminum metallization is patterned by a subtractive process and copper metallization is patterned by a damascene process. Both processes are well known to those of skill in the art of semiconductor device fabrication and need not be described here.

As illustrated inFIG. 10, the method continues, in accordance with an embodiment of the invention, by depositing another dielectric layer112overlying dielectric layer92and layer of interconnect metallization110. Surface114of the additional dielectric layer is preferably planarized, for example by CMP. The second dielectric layer can be silicon oxide, a low dielectric constant material such as hydrogen, fluorine, carbon or nitrogen-containing silicon oxide, or other dielectric material deposited by CVD, LPCVD, SACVD, PECVD, or a spin on process to a thickness of about 30-100 nm. Contact opening116is etched through dielectric layer112and dielectric layer92to expose a portion of deposited metal layer86that is electrically coupled to bit line30. An electrically conductive plugs118is formed that fills contact opening116and a layer of interconnect metallization120is deposited and patterned at surface114of dielectric layer112. The contact plug can be formed, for example, in the same manner as contact plugs102and104and interconnect metallization118can be formed and patterned in the same manner as interconnect metallization110. Bit line30is thus electrically coupled to interconnect metallization120through electrically conductive plug118, selectively deposited metal layer86and metal silicide contact80. By fabricating IC20in accordance with an embodiment of the invention the length of contact opening116and the height of electrically conductive plug118, as indicated by arrow122, is significantly less than the distance from interconnect metallization120and the corresponding metal silicide contact80as indicated by arrow124. Preferably the thickness of selectively deposited metal layer86as indicated by arrow89is at least one third of the combined height of dielectric layer92and dielectric layer112. The aspect ratio of contact opening thus is significantly reduced, and preferably is reduced by at least one third.

In accordance with another embodiment of the invention, as illustrated inFIG. 11, integrated circuit20is fabricated in a similar manner except that memory storage capacitor dielectric100is deposited on metal silicide contact82before the selective deposition of metal layer88. Memory storage capacitor32thus includes a bottom plate formed by metal silicide contact82and ion implanted memory storage capacitor contact72, capacitor dielectric100and a top plate formed by selectively deposited metal layer88. Capacitor dielectric layer100is deposited directly on metal silicide contact82. A seed layer190of, for example, platinum is deposited onto the dielectric layer, and selectively deposited conductive material88is deposited on the seed layer in the same manner as described above. The remainder of the method is the same as previously described.

Those of skill in the art will understand that many additional layers of interconnect metallization and additional layers of ILD may be required to complete integrated circuit20. Some of those additional layers of interconnect metallization may be positioned between interconnect metallization layers110and120. Additional layers only make the problem of high aspect ratio contacts even more severe and the advantage provided by the current invention more valuable. Although the various embodiments of the invention have been described and illustrated with reference to a combination logic circuit and memory circuit and specifically to a microprocessor that includes embedded DRAM, the invention is also applicable to any circuit having high aspect ratio contacts. The invention is applicable, for example in any circuit in which a contact must extend from an upper layer of interconnect metallization to a device region separated from the interconnect metallization by one or more intervening layers of conductive or insulating material.