WAFER INSPECTION METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

A wafer inspection method includes providing a wafer with at least one position marker; setting a care area around the at least one position marker; detecting a plurality of defects in the wafer by using a surface inspection apparatus identifying the at least one position marker as a defect, the plurality of defects including the defect corresponding to the at least one position marker; and achieving an off-set value of coordinates of the plurality of defects based on the coordinates of the defect corresponding to the at least one position marker and the coordinates of the at least one position marker.

FIELD

Embodiments are generally related to a wafer inspection method for manufacturing a semiconductor device.

BACKGROUND

In-line inspection of wafers in the manufacturing process is essential for improving the manufacturing yield of semiconductor devices. As the integration degree advances in integrated circuits and memory devices, however, it becomes difficult to assign a defect detected by the in-line inspection to a structure element. The major reason of this is in the accuracy of defect position that includes deviations due to the unintentional shift of coordinates and measurement error induced in each inspection and that is relatively lowered as the miniaturization of device structure advances.

DETAILED DESCRIPTION

According to an embodiment, a wafer inspection method includes providing a wafer with at least one position marker; setting a care area around the at least one position marker; detecting a plurality of defects in the wafer by using a surface inspection apparatus identifying the at least one position marker as a defect, the plurality of defects including the defect corresponding to the at least one position marker; and achieving an off-set value of coordinates of the plurality of defects based on the coordinates of the defect corresponding to the at least one position marker and the coordinates of the at least one position marker.

Embodiments will now be described with reference to the drawings. The same portions inside the drawings are marked with the same numerals; a detailed description is omitted as appropriate; and the different portions are described. The drawings are schematic or conceptual; and the relationships between the thicknesses and widths of portions, the proportions of sizes between portions, etc., are not necessarily the same as the actual values thereof. The dimensions and/or the proportions may be illustrated differently between the drawings, even in the case where the same portion is illustrated.

There are cases where the dispositions of the components are described using the directions of XYZ axes shown in the drawings. The X-axis, the Y-axis, and the Z-axis are orthogonal to each other. Hereinbelow, the directions of the X-axis, the Y-axis, and the Z-axis are described as an X-direction, a Y-direction, and a Z-direction. Also, there are cases where the Z-direction is described as upward and the direction opposite to the Z-direction is described as downward.

First Embodiment

FIG. 1is a flow chart showing a wafer inspection method according to a first embodiment. The wafer1used for the inspection includes e.g. chip patterns10and position markers20.FIGS. 2A to 2Care schematic views illustrating the arrangement of the position markers20according to the first embodiment.

The wafer1shown inFIG. 2Aincludes a plurality of position markers20on its surface. The position markers20are recognized as surface defects in e.g. a SEM (scanning electron microscope) or optical wafer inspection apparatus (not shown). The procedure of the wafer inspection is now described with reference toFIG. 1.

Step S01: Setting an inspection recipe. For instance, the controller of the inspection apparatus retrieves the design information of the semiconductor chip from a database, and sets e.g. a wafer size, and a repetition pitch and placement of chip patterns10formed on the wafer.

Step S02: Setting coordinates of position markers20. The position marker20is placed at e.g. coordinates assigning a particular position on the wafer. Alternatively, the position marker20may be placed at coordinates specifying a relative position with respect to the chip pattern10.

For instance, the position markers20are placed on the wafer with a pitch different from that of the chip patterns10. The position marker20is placed in e.g. one of two adjacent chip patterns10. That is, the position marker20is recognized as a surface defect in the surface inspection comparing two adjacent chip patterns10.

Step S03: Setting care areas30(seeFIG. 3) around the position markers20. The care area30is a region to be searched for the presence or absence of defects in e.g. the process for detecting surface defects corresponding to the position markers20. The care area30is set so that the surface defects corresponding to the position markers20are placed inside the care area30in view of the shift amount of coordinates and measurement error in each inspection.

The care area30has preferably a size fitted, for example, to the viewing field of the inspection apparatus. Furthermore, preferably, the care area30does not include all or part of the elements of the chip pattern10. That is, the care area30is set so as not to include the defects other than the surface defects corresponding to the position markers20. This makes it easier to detect the surface defects corresponding to the position markers20.

Step S04: Scanning the surface of the wafer1to detect surface defects. For instance, the SEM images, the bright-field images, or the dark-field images of two adjacent chip patterns10are compared. The presence or absence of defects is determined based on the difference of signal intensity exceeding a preset threshold, and then, the coordinates of the defects (in the inspection coordinate system) are recorded. Here, the inspection coordinates are identified by the inspection apparatus. For instance, the inspection coordinates include off-set of the inspection apparatus or in each inspection.

Step S05: Extracting the off-set value. For instance, the coordinates of the surface defects corresponding to the position markers20(in the inspection coordinate system) are extracted from the inspection data. The distance between the coordinates of the surface defects (in the inspection coordinate system) and the coordinate of the position marker20(in the reference coordinate system) is calculated as the off-set value of the inspection data. The off-set value is calculated as the mean value of the distance between a plurality of position markers20provided on the surface of the wafer1and the corresponding surface defects, or the median or mode value in the distance distribution. Here, the reference coordinate system is, for example, a coordinate assigned on the wafer, or the design coordinate.

Step S06: Correcting the coordinates of the defects. The coordinates of the defects other than the surface defects corresponding to the position markers20are corrected using the off-set value detected in step S05.

In the embodiment, the surface defects corresponding to the position markers20are detected in the process of surface inspection of the wafer. Thus, the off-set value in each inspection can be determined through the process of data processing in the surface inspection apparatus, or data processing using the inspection results stored in a database.

Then, the off-set value is used to correct the coordinates of the defects other than the surface defects corresponding to the position markers20. The accuracy of defect position may be improved through this process.

FIGS. 2B and 2Care schematic views showing another arrangement of position markers20as example.FIG. 2Bshows e.g. the arrangement of chip patterns10in a reticle2used for the photolithography.FIG. 2Cshows chip patterns10with the position markers20placed therein.

As shown inFIG. 2B, the reticle2includes a plurality of chip patterns10, a marker pattern5, and marker patterns7. The marker pattern5includes position markers20in a care area30(seeFIG. 3). The marker pattern7includes no position markers20, but includes a pattern corresponding to the care area30. The reticle2includes e.g. one marker pattern5and a plurality of marker patterns7. The marker patterns5and7are placed respectively at a position close to each chip pattern10, or inside the chip pattern10. For instance, the marker patterns5and7are placed respectively between adjacent chip patterns10.

The marker patterns5and7are placed respectively so that the relative position thereof with respect to each chip pattern10is the same as other chip pattern10. In the case where the marker5or7is placed in the chip pattern10, the marker5or7is placed so that the position of marker5or7in each chip pattern10is the same as that in other chip pattern10. Thus, the surface inspection apparatus may recognize the position marker20as a defect, which is included in the marker pattern5.

As shown inFIG. 2C, a plurality of position markers20may be placed inside the chip pattern10. However, the position marker20is not provided in other chip patterns10adjacent thereto in the X-direction and the Y-direction.

In the example shown inFIG. 2B, the position marker20is placed at a position close to a prescribed chip pattern10. The position thereof is defined as the relative position with respect to the chip pattern10. In the example shown inFIG. 2C, the position marker20is placed in the chip pattern10. The coordinates of the position marker20may be identified by assigning the position of the prescribed chip pattern10, or the position of the chip pattern10including the position marker20, in the plane of the wafer1.

FIG. 3is a schematic view showing marker patterns5according to the first embodiment. Each marker pattern5includes a pattern corresponding to the position marker20. Layers1to15shown inFIG. 3are the names representing mask layers sequentially used for lithography. The marker patterns5are provided in the mask layers respectively. The marker patterns5are provided e.g. in the region corresponding to the position shown inFIGS. 2A to 2Cat which the position marker20is arranged.

In the following description, it is assumed for convenience that the marker pattern5includes at least one position marker20and a care area30therearound. The marker pattern5of Layer1includes one position marker20. The marker patterns5of Layers2-5each include two position markers20. The marker patterns5of Layers6-15each include four position markers20. In the data processing procedure described later, the distance between the position markers20is used, which is defined along a line passing through the geometric barycenter of the four position markers20in each of the layers6to15. Then, a distance between one pair of positon markers20is equal to a distance between the other pair of position markers20.

FIG. 4is a schematic view illustrating an arrangement, as an example, of position markers20in the marker pattern5. The position markers20are disposed respectively in regions divided by a lattice like boundary as shown inFIG. 4. The numeral denoted inFIG. 4corresponds to the name of mask layer. A position marker20of each mask layer is placed in the region denoted with the corresponding numeral.

As shown inFIG. 4, the position markers20are placed so as not to overlap each other in the marker pattern5. This makes it easy to detect surface defects corresponding to the position markers20of each layer.

FIGS. 5A and 5Bare schematic views showing other marker patterns5aand5brespectively according to the first embodiment.

As shown inFIG. 5A, the marker pattern5aincludes a position marker20aand a care area30a.The position marker20ais transparent for exposure light. The care area30ablocks the exposure light. For instance, when forming an opening corresponding to the position marker20in the resist on the wafer, the marker pattern5ais so called a positive pattern.

As shown inFIG. 5B, the marker pattern5bincludes a position marker20band a care area30b.The position marker20bblocks the exposure light. The care area30bis transparent for exposure light. For instance, when the resist corresponding to the position marker20is left on the wafer, the marker pattern5bis so called a negative pattern.

FIG. 6is a table showing an interlayer arrangement of marker patterns5according to the first embodiment. Marker positions (MK positions)1to4shown inFIG. 6represent coordinates different from each other on the surface of the wafer1. “P” inFIG. 6represents the positive pattern. “N” inFIG. 6represents the negative pattern.

As shown inFIG. 6, a marker pattern5placed at the marker position1is of the positive type in all Layers1to15. On the other hand, a marker pattern5placed at the marker position4is of the negative type in all Layers1to15. The marker patterns5of the positive type and the negative type are used alternately in the marker positions2and3.

Thus, position markers20with different structures can be simultaneously formed at the marker positions1to4by appropriately using the positive-type marker pattern or the negative-type marker pattern. It is possible to achieve desired detection sensitivity over the inspection apparatuses of different types. For instance, the desired detection sensitivity may be obtained at the position marker20of each of Layers1-15for at least one of the SEM image, the bright-field image, and the dark-field image.

FIGS. 7A and 7Bare schematic views showing position markers20according to variations of the first embodiment.

As shown inFIG. 7A, the position marker20may include e.g. a plurality of rectangular sub-patterns21. Alternatively, as shown inFIG. 7A, the position marker20may be a cross pattern23. Such a position marker20is suitable e.g. for the process of forming interconnects of the semiconductor device.

As shown inFIG. 7B, the position marker20may include e.g. a plurality of square sub-patterns25. Alternatively, as shown inFIG. 7B, the position marker20may include sub-patterns25arranged in a cross-like shape. Such a position marker20is suitable e.g. for the process of forming a contact holes.

Then, a wafer inspection method according to a variation of the first embodiment is described with reference toFIGS. 8andFIGS. 9A to 11B.FIG. 8is a flow chart showing a method for detecting an off-set value according to the variation of the first embodiment.FIGS. 9A to 11Bare schematic views showing the process for detecting the off-set.

The method for detecting the off-set value is now described with reference to the flow chart shown inFIG. 8.

Step S11: Detecting a defect located in the care area30. For instance,FIG. 9Ais a schematic view showing position markers20and a care area30. In this example, two position markers20are placed in the care area30. The distance between the centers of the position markers20is denoted by Dc. Cp inFIG. 9Ais the geometric barycenter of the position markers20. That is, Cp is the midpoint of the line connecting the centers of the position markers20.

FIG. 9Bis a schematic view illustrating defects located in the care area30. For instance, the defect positions are assigned using the coordinates with reference to the chip pattern10that includes the position markers20or that is adjacent to the position markers20.FIG. 9Bis a schematic view illustrated by superimposing defects located in a plurality of care areas30defined on the wafer.

Step S12: Calculating the distance between a pair of defects for all pairs detected in the care area30. For instance,FIG. 10is a distance map showing distances of all pairs located in the care area30. A distance between a pair of defects is e.g. a distance between one defect coordinates and the other defect coordinates.

Step S13: Selecting pairs of defects having a prescribed distance. For instance, all pairs of defects each having a distance in the range of Dc±Δd are selected. In the example shown inFIG. 10, Dc is equal to 10 micrometers. Thus, all pairs of defects having a distance in the range of 10±0.5 micrometers are selected.

Step S14: Calculating the differences in the X-coordinate and the Y-coordinate respectively between the center coordinates of the selected pair of defects and the coordinates of the center Cp of the position markers20.

Step S15: Plotting the cumulative normal probability distribution of the distance between the center of the pair of defects and Cp. For instance,FIG. 11Ais a graph showing the cumulative normal probability distribution plotted with respect to the difference ΔX in X-coordinate between the center of the pair of defects and Cp.FIG. 11Ashows the cumulative normal probability distributions of four wafers AA, BB, CC, and DD. The horizontal axis represents ΔX. The vertical axis represents the standard deviation σ.

Step S16: Extracting the value of ΔX at the center of the cumulative normal probability distribution as an off-set value of X-coordinate. An off-set value in the Y-direction is similarly extracted from the cumulative normal probability distribution of the difference in the Y-coordinate between the center of the pair of defects and Cp.FIG. 11Bshows a cumulative normal probability distribution after the correction of defect coordinates using the off-set value.

In this example, using the distance Dc between two position markers20, the defect coordinates corresponding to the position marker20are identified, and then, the off-set value of the defect coordinates is obtained. Thus, the off-set value can be achieved even in the case where the care area30includes defects other than the surface defects corresponding to the position markers20. This may improve the positional accuracy of the defects.

Second Embodiment

Then, a wafer inspection method according to a second embodiment is described with reference toFIGS. 12A to 14B.FIGS. 12A to 14Bare schematic views showing a procedure of data processing in the wafer inspection according to the second embodiment.

The embodiment provides e.g. a method for identifying defect coordinates in the chip pattern10without using the position marker20. For instance,FIG. 12Ais an inspection result showing the distribution of defects in a chip pattern of a semiconductor memory device. The vertical axis and the horizontal axis represent the coordinate axes of the chip pattern.FIG. 12Ais the result of the inspections using a plurality of wafers which includes data obtained using a plurality of surface inspection apparatuses.

FIG. 12Bis a histogram showing the distribution of the X-coordinates of the defects shown inFIG. 12A.FIG. 12Bincludes the data of the defects corresponding to memory cell arrays Ar1-Arn arranged in the Y-direction.FIG. 12Bincludes two defect groups DG1and DG2. The peaks of the respective distributions are spaced by a distance Dp.

For instance, the pairs having a distance in the X-direction in the range of Dp±Δd are selected (seeFIG. 10) from all pairs obtained by paring one defect included in the defect group DG1and the other defect included in the defect group DG2. Next, the cumulative normal probability distribution of the difference ΔX between the center of each selected pair and the midpoint of the peak positions of the defect groups DG1and DG2is plotted for each wafer (seeFIG. 11A). Then, the value of ΔX corresponding to the median of the cumulative normal probability distribution of each wafer is used as an off-set value to correct the defect coordinates of the wafer (seeFIG. 11B).

FIG. 13Ais a histogram of the X-coordinates showing the defect distribution after the correction of defect coordinates for each wafer. It is found that the deviation of defect positions is suppressed, and the accuracy of the defect positions is improved. The embodiment is not limited to the example above. For instance, the distance Dp between the peaks of the defect groups DG1and DG2may be replaced by the distance between specific patterns in which the defects are induced. The cumulative normal probability distribution may be plotted based on the difference between the coordinates of the specific pattern and the coordinates of each selected pair.

Furthermore, the cumulative probability distribution is plotted for each chip pattern included in each wafer. The off-set value of X-coordinate in each chip pattern is achieved similarly. Then, the defect coordinate is corrected using each off-set value in each chip pattern.FIG. 13Bis a histogram showing the X-coordinates of the defects after the correction of coordinates for each chip pattern.

Furthermore, the cumulative probability distribution is plotted for each memory cell array included in each chip pattern. Each off-set value of X-coordinate in memory cell arrays

Ar1-Arn is achieved similarly. Then, the defect coordinates is corrected using each off-set value in each memory cell array.FIG. 14Ais a histogram showing the X-coordinates of the defects after the correction of coordinates for each memory cell array.

FIG. 14Bis a schematic view showing the distribution of defects after the aforementioned correction. As shown inFIG. 14B, the accuracy of relative position is significantly improved in the X-coordinates of the defects. Each defect is distributed linearly in the Y-direction. This indicates that each defect corresponds e.g. to a component extending in the Y-direction of the chip pattern. The component corresponding to the defects may be identified based on the distance in the X-direction between the defect groups.

The embodiment has described an example of achieving an off-set value for each wafer, for each chip pattern, and for each memory cell array, and sequentially correcting each defect coordinate. Achieving an off-set value for each wafer enables e.g. the correction of deviation of the coordinate system for each inspection over a plurality of surface inspection apparatuses. Achieving an off-set value for each chip pattern enables the correction of deviation of the coordinate system e.g. for each exposure shot of the stepper.

Furthermore, achieving an off-set value for each memory cell array enables e.g. the correction of measurement errors. For instance, the irradiation position of the electron beam in the SEM type surface inspection apparatus may be varied by electric charging. More specifically, if the components of the chip pattern are unevenly placed, their electric charging generates a potential distribution. This may deflect the electron beam and decrease the accuracy of defect coordinates. In the example shown inFIG. 12A, the defects detected successively in the Y-direction are arranged in a bent curve. In contrast, the corrected defects shown inFIG. 14Bare arranged in a line extending in the Y-direction. This indicates that the positional accuracy of defects is improved.

The embodiment is not limited to the above example. For instance,FIG. 15shows a scan direction at the time of wafer inspection. As shown inFIG. 15, the embodiment may further include the step of achieving an off-set value for each group of chip patterns10arranged in the scan direction (e.g.

X-direction) at the time of wafer inspection.

Third embodiment

FIG. 16is a flow chart showing a wafer inspection method according to a third embodiment. In this example, marker defects are added at prescribed positions in the selected chip patterns10without providing position markers20in the wafer1.FIG. 17is a schematic view showing an example of specifying coordinates MP for providing a marker defect in the chip pattern10.

Step S21: Setting an inspection recipe. For instance, a wafer size, a repetition pitch of chip patterns10formed on a wafer and an arrangement thereof are set in this step.

Step S22: Setting positions (marker points) for adding marker defects. For instance, the chip patterns10for setting marker defects are selected from a plurality of chip patterns10arranged on the wafer. Then, the prescribed coordinates MP in the chip pattern10are assigned as a marker point. The marker point specified in the chip pattern10is preferably a portion that can be identified with high positional accuracy, such as a corner of the pattern as shown inFIG. 17, or a portion having a unique shape.

Step S23: Scanning the surface of the wafer1to detect surface defects. For instance, the SEM images, the bright-field images, or the dark-field images are compared in adjacent chip patterns10. The presence or absence of defects is determined based on the difference of signal intensity exceeding a preset threshold, and the coordinates of each defect are recorded.

Step S24: Adding marker defects to the inspection data. The position corresponding to a marker point of the selected chip pattern10is identified using e.g. the SEM image. A defect serving as a marker (marker defect) is added at the coordinates of the position. In this case, the position of the marker defect is specified in the coordinate system of the inspection apparatus (hereinafter, the inspection coordinate system).

Step S25: Determining an off-set value using the coordinates of the marker defects. For instance, the difference between the coordinate of the marker defect specified by the inspection coordinate system and the coordinate MP of the marker point specified using the coordinate system on the wafer (hereinafter, the reference coordinate system) is achieved as an off-set value. Furthermore, the achieved off-set value is used to correct the coordinates of defects for each wafer. This may improve the accuracy of defect coordinates.

In the examples described above in the first to third embodiments, the positional accuracy of the defect coordinates is improved by the off-set value of defect coordinates which is achieved using the result of wafer inspection. Thus, the failure analysis may be performed using e.g. DBB (design-based binning), and improve the manufacturing yield of semiconductor devices.