Various methods and apparatus for width and burst conversion

Methods and apparatuses are described for a communication system. The communication system may include one or more initiator agents, where each agent couples to its own Intellectual Property core. The communication system may also include two or more target agents, where each agent couples to its own Intellectual Property core. The communication system may also include an interconnect using an end-to-end width conversion mechanism. The conversion mechanism converts data widths between the initiator agent and a first target agent. Two or more branches of pathways in the interconnect exist between the initiator agent and the two or more target agents. The conversion mechanism to use a lookup table that includes data width information of the initiator agent and the two or more branches of pathways to the two or more target agents to concurrently pre-compute width conversion signals for each of the target agent branches.

FIELD OF THE INVENTION

The aspects of embodiments described herein apply to systems, especially Systems on a Chip, where an initiator core, which is sending data, has a different data word width and/or different burst characteristics than a target core, which is receiving the data, such that a conversion of the width and/or burst is required.

BACKGROUND

In computer networks, internetworking, communications, integrated circuits, etc. where there is a need to communicate information, there are often interconnections established to facilitate the transfer of the information. However, not all of the functional blocks connecting to a shared interconnect will have the same data width and burst type support communication capabilities. Some conversions should occur to make communications capable between functional blocks with different communication capabilities.

SUMMARY OF THE INVENTION

Methods and apparatuses are described for a communication system. The communication system may include one or more initiator agents, where each agent couples to its own Intellectual Property core. The communication system may also include one or more target agents, where each agent couples to its own Intellectual Property core. The communication system may also an end-to-end width conversion mechanism. The conversion mechanism converts data widths between the initiator agent and a first target agent. Two or more branches of pathways in the interconnect exist between the initiator agent and the two or more target agents. The conversion mechanism to use a lookup table, or internal logic, that includes data width information of the initiator agent and the two or more branches of pathways to the two or more target agents to concurrently pre-compute width conversion signals for each of the target agent branches.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth, such as examples of specific protocol commands, named components, connections, types of burst capabilities, etc., in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well known components or methods have not been described in detail but rather in a block diagram in order to avoid unnecessarily obscuring the present invention. Thus, the specific details set forth are merely exemplary. The specific details may be varied from and still be contemplated to be within the spirit and scope of the present invention.

An example process of and apparatus to provide Width and Burst Conversion is described. The on-chip interconnect may contain a capability to manage end-to-end width conversion between independent initiator and target data path widths. Logic in an agent may compute target-dependent width support and burst type support information across multiple groups of potential targets at the same time, and then select the correct target-dependent information based upon the address decode result for the target selection. Thus, an initiator agent (hereinafter “IA”) unit may use compiled knowledge of its and the addressed target's data width to pre-compute information to enable later stages (in the IA, target agent (hereinafter “TA”), a width conversion unit, or similar component) to accomplish the actual width conversion via packing, unpacking, padding, stripping, etc. —both for requests and responses. Pre-computing the width conversion information reduces the latency delay seen at each conversion stage in the core of the interconnect. In addition, an optimization can be performed in the IA that permits this pre-computation to be performed in parallel with the target selection (address decode) to further reduce logic delay in the path.

Each agent may also contain one or more burst conversion units. The Intellectual Property cores connected to the on-chip interconnect may have incompatible capabilities with respect to supporting different features and types of burst requests. For example, the supported burst address sequences, burst transaction lengths, and burst alignment restrictions may not match. The on-chip interconnect introduces a mechanism for allowing such cores to communicate, independent of either core needing to adapt its behavior. As with width conversion (discussed above), most of the arithmetic operations to make the different burst features compatible is performed in the IA. The IA compares the initiator burst request with the target burst support capabilities to determine the appropriate conversion action. Also, burst request conversion computations for all of the potential target agents may proceed in parallel with actual target selection (address decode) to further reduce logic delay in the path.

FIG. 1is a block diagram of a complex electronics system100. Shared communications bus112connects sub-systems102,104,106,108, and110. Sub-systems are typically functional blocks including an interface module for interfacing to a shared bus. Sub-systems may themselves include one or more functional blocks and may or may not include an integrated or physically separate interface module. In one embodiment, the sub-systems connected by communications bus112are separate integrated circuit chips. In another embodiment, the sub-systems connected by communications bus112are Intellectual Property cores on a system on a chip.

For example, Sub-system104may be an application specific integrated circuit (hereinafter “ASIC”), which, as is known, is an integrated circuit, designed to perform a particular function. Sub-system106is a dynamic random access memory (hereinafter “DRAM”). Sub-system108is an erasable, programmable, read only memory (hereinafter “EPROM”). Sub-system110is a field programmable gate array (hereinafter “FPGA”). Sub-system102is a fully custom integrated circuit designed specifically to operate in system100. Other embodiments may contain additional sub-systems of the same types as shown or other types not shown. Other embodiments may also include fewer sub-systems than the sub-systems shown in system100. Integrated circuit102includes sub-systems102A,102B,102C,102D and102E. ASIC104include functional blocks101A,104B and104C. FPGA110includes functional blocks110A and110B. A functional block may be a particular block of logic that performs a particular function, a memory component on an integrated circuit, etc.

System100is an example of a system that may consist of one or more integrated circuits, chips, or functional IP cores on a single chip. A functional block may be a logic block on an integrated circuit such as, for example, functional block102E, or a functional block may also be an integrated circuit such as fully custom integrated circuit102that implements a single logic function.

An interconnect such as, a shared communications bus112, provides a shared communications bus between sub-systems of system100. Shared communication bus114provides a shared communications bus between sub-systems or functional blocks on a single integrated circuit. Some of the functional blocks shown are connected to interface modules through which they send and receive signals to and from shared communications bus112or shared communications bus114. Interface interconnects115,116,117, and118are local point-to-point interconnects for connecting interface modules to functional blocks.

Agents, such as interface modules120-128, are connected to various functional blocks as shown. In this embodiment, interface modules120,122,123and124are physically separated from their connected functional block (A, B, C, E and F, respectively). Interface modules121, and125-128are essentially part of their respective functional blocks or sub-systems. Some functional blocks, such as102D, do not require a dedicated interface module. The arrangement of sub-systems, functional blocks and interface modules is flexible and is determined by the system designer.

In one embodiment there are four fundamental types of functional blocks. The four fundamental types are initiator, target, bridge, and snooping blocks. A typical target is a memory device, and a typical initiator is a central processing unit (CPU). However any block may be a target or an initiator. A typical bridge might connect shared communications buses112and114. Functional blocks all communicate with one another via shared communications bus112or shared communications bus114and the protocol of one embodiment. Initiator and target functional blocks may communicate a shared communications bus through interface modules. An initiator functional block may communicate with a shared communications bus through an initiator interface module and a target functional block may communicate with a shared communications bus through a target interface module.

An initiator interface module issues and receives read and write requests to and from functional blocks other than the one with which it is associated. In one embodiment, an initiator interface module is typically connected to a CPU, a digital signal processing (hereinafter “DSP”) core, or a direct memory access (hereinafter “DMA”) engine.

The shared communication bus112may have an end-to-end width conversion mechanism to convert data widths between an initiator interface module and a target interface module. Two or more potential branches of pathways within the shared bus may exist between the initiator agent and the two or more potential target interface modules. The conversion mechanism uses a lookup table that includes data width information of the initiator interface module and the two or more potential branches of pathways to the two or more target interface modules to concurrently pre-compute width conversion signals for each of the target agent branches.

Similarly, the initiator interface module may include an end-to-end burst conversion mechanism to allow the initiator and target functional blocks to communicate, by generating burst conversion signals, independent of the initiator and target functional blocks needing to adapt their burst capabilities.

Note, the interconnect shown inFIG. 1illustrates a bus-based interconnect. However, the interconnect may be implemented in many ways such as point-to-point, switched or routed networks.

FIG. 2illustrates an exemplary group of intellectual property cores, their corresponding agents, an interconnect and its logic core. In system200, there exists two initiator cores (hereinafter “IC”): initiator core205and initiator core210. IC205is coupled to initiator agent (hereinafter “IA”)225via interface communication lines215. IC210is coupled to IA230via interface communication line220. There also exist three target cores (hereinafter “TC”): target core270, target core275and target core280. TC270is coupled to target agent (hereinafter “TA”)240via interface communication line255. TC275is coupled to TA245via interface communication line260. TC280is coupled to TA250via interface communication line265.

Interconnect201comprises a logic core235as well as all the initiator and target agents (e.g., IA225, IA230, TA240, TA245and TA250). IA225is coupled to logic core235via interface communication line232. IA230is coupled to logic core235via interface communication line234. TA240is coupled to logic core235via interface communication line236. TA245is coupled to logic core235via interface communication line237. TA250is coupled to logic core235via interface communication line238.

Both possibilities may exist in communications systems 1) where initiator agents send read requests and target agents correspond by sending data responses; and 2) where initiator agents send write requests with data to a target agent and the target agent sends a response. Thus two possibilities exist for data width conversion: one for writes (where data moves from initiator to target) and one for reads (where data moves from target to initiator). In the read request case, the initiator agent sends a data request based on the width support of the initiator IP core and the target agent sends the data response, which subsequently may need to undergo several width conversions along the interconnect to the initiator agent. In this case, logic in the initiator agent may generate one or more helper signals. A helper signal just accompanies the data request to the target agent and is used with the data response. In the data write case, initiator agents send a request and data to a target agent that subsequently may need to undergo several width conversions along the interconnect to the target agent. The helper signal helps convert width of the data signals from the initiator agent along the way to the target agent.

The case where an initiator sends a write request and data will be used as an example and be described below.

In one embodiment. IC205may need to send data to TC280. IC205sends the data, via interface communication line215to IA225. IA225, which is inside interconnect201, then transmits the data, via interface communication line232, to core logic235. Any processing which may need to take place may occur within core logic235: Next, the data is transmitted, via interface communication line238, to TA250. Lastly, the data reaches TC280, via interface communication line265.

FIG. 3illustrates a close-up view ofFIG. 2, specifically the interface communication lines between an agent and its corresponding core. TA240is coupled to TC270via interface communication line255and IA245is coupled to IC275via interface communication line260. In this embodiment, the width of interface communication line255is 16 bits wide. This is shown by the multiple wires in communication line255. On the other hand, the width of interface communication line260is 32 bits wide. Hence, there are more individual wires in interface communication line260. Depending on characteristics such as data width, burst support, etc., the number of actual wires in a communication line may vary dramatically. Common communication line widths include: 8-bit, 16-bit, 32-bit, 64-bit, 128-bit and 256-bit.

FIG. 4illustrates the process by which data is sent from IC205to TC280. In this embodiment the data width and burst characteristics of each intellectual property core may be different. Therefore width and burst conversion shall be required. An interconnect between IC205and TC280may contain IA225, TA250, and Core logic235. IA225is capable of sending and receiving data to/from IC205via interface communication line215. IA225includes width determination unit (hereinafter “WDU”)415, and burst conversion unit (hereinafter “BCU”)410. IA225is coupled to Core Logic235via interface communication line232. In this embodiment, interface communication line's232data width is 16 bits in width. Core Logic235includes one or more width conversion units such as a first WCU450and a second WCU451.

TA250is capable of sending and receiving data to/from TC280via interface communication line265. TA250comprises burst conversion unit440. TA250is coupled to Core Logic235via interface communication line238. In this embodiment, interface communication line's238data width is 32 bits in width making it twice as wide as interface communication line232.

In this embodiment, IC205wishes to send data to TC280. The data width of the two cores differs. Hence, data width conversion is required. The data420is sent from IC205to IA225via interface communication line215. As stated above, the data is 16-bit. Once data420is received by IA225, WDU415queries data lookup table418to determine the data width of all possible target cores physically coupled to IA225, as well as all the possible pathways between IA225and the possible target cores. With the information provided by data lookup table418, WDU415is able to determine the data width of each possible target core (e.g., any target core that is physically cable of receiving data from IC205.) In another embodiment WDU415may possess internal logic comprising the data width of all possible pathways between IA225and the possible target core, thus eliminating the need for data lookup table418. WDU415generates width conversion signals for all possible target cores and their physical pathways, regardless of which target core is the eventual recipient of the data. The generation of all width conversion signals occurs in parallel (shown further inFIG. 5). As a result, the generation of all width conversion signals shall be completed at substantially the same time.

In one embodiment, the data lookup tables for each instance of an agent include the same data. This data includes the data width capabilities of all the potential target agents in the complete system as well as all the physical pathways to them. Hence every agent would have the identical data lookup table. In another embodiment, every instance of an agent would possess internal logic comprising the data width capabilities of all the potential target agents in the complete system, as well as all the physical pathways to them. Hence, the logic of each initiator agent would contain the same data. In another embodiment, each instance of an agent may include a data lookup table customized to merely contain data about the target agents that may communicate with that initiator agent. In such a scenario, each data lookup table could comprise different data. In another embodiment, each instance of an agent may possess customized internal logic to merely contain data about the target agents that may communicate with that initiator agent. Hence, the logic in each initiator agent could comprise different data.

Further, the generation of the width conversion signals occurs in parallel to the address decoding of the eventual target (described further inFIG. 5). Thus, the generation of all width conversion signals is being computed in parallel to the target address decoding of the signal containing data420. The address decode informs IA225which actual target core requires the data. The parallel processing of the address decode and width conversion signals provides an advantage over the prior art by pre-computing width conversion signals while IA225would otherwise be waiting for the address decode to complete. In a prior art system, the address decode and the width conversion are completed one after the other (e.g., serially). Such an approach is slower than the system illustrated inFIG. 4. Once the address decode is complete, IA225knows that data420is to be transmitted to TC280. Since the width conversion for TA280has already been computed, time is saved over the prior art's serial-based approach.

Initiator agents also comprises logic, along with the help of a width determination unit, to generate a helper signal to direct the conversion of data widths between the initiator agent and a target agent by identifying characteristics of a group of data and how the data may be width converted, to enable subsequent conversion stages to accomplish the width conversion. In this example, WDU415sends helper signal430to WCU450. Helper signal430assists WCU450in the actual width conversion of data420from 16-bit to 32-bit by instructing WCU450in what way data420needs to be converted. WCU450has also received data420from IA225. Hence, WCU450now possesses data420and helper signal430, allowing it to complete the width conversion. Core Logic235also comprises a second WCU451that performs a second width conversion of data420with the assistance of helper signal430. An example of two width conversions has been described but the number of width conversions occurring in Core Logic235should not be so limited. It is possible for numerous width conversions to occur in Core Logic235before data420is passed to TC280. (Note:FIG. 7illustrates a table of helper signal types and the usage of each type.) Under this approach, very little processing is done in Core Logic235. Most of the processing is accomplished on the outside perimeter of interconnect201(e.g., the initiator and target agents). This frees up Core Logic235for other tasks and allows it to be small and fast.

Core Logic235spends a small amount of time performing the actual width conversion of data420from 16-bit to 32-bit, through the assistance of width conversion helper signal430. The converted data435is sent to TA250, in 32-bit form, via 32-bit interface communication line238. Core Logic235also relays helper signal430to TA250. This proves useful in the event that TA250returns data to IA225. TA250will not be required to generate helper signals since they are already available. Lastly, TA250sends the data to TC265via interface communication line265.

In another embodiment, IC205needs to send burst data to TC280. However, IC205has different burst capabilities than TC280. It is possible that one or more potential target cores, coupled to the interconnect, have a burst capability different from the initiator core's burst capability such that a burst conversion unit may generate burst conversion signals for each of the potential target cores. Under such a scenario, an initiator agent compares its supported burst features to the supported burst features of the target agent to determine how to transmit a burst request from the initiator agent to the target agent via the interconnect.FIG. 8illustrates some different types of burst characteristics and the options/choices for each. Further characteristics of burst types can be found in Open Core Protocol Specification Release 2.0 published by the OCP/IP Organization in November, 2003 and is hereby incorporated by reference. In this example, IC205and TC280have different burst length precision and request types. As such, the burst data must be converted to allow TC280to receive it from IC205. (Note:FIG. 9will subsequently describe the different types of burst conversion and how they are performed.)

First, the burst data is received by IA225from IC205via interface communication line215. BCU410is responsible for converting the burst data to characteristics compatible with the target core. BCU410generates burst conversion signals for all possible target cores that could physically receive the burst data. A data lookup table may provide the burst characteristics of each target core.

In one embodiment, the data lookup table may comprise burst data of all the target agents in the entire system, regardless of whether IA225communicates with them. This embodiment would provide for generic burst data lookup tables that are the same for all agents. Under this embodiment the generation of burst conversion signals would result in having conversion signals generated for every possible burst type in the system, regardless of whether an agent with such burst characteristics communicates to IA225. In another embodiment, every agent would possess internal logic comprising the burst capabilities of all the potential target agents in the complete system. Hence, the logic of each initiator agent would contain the same burst data. In another embodiment, the burst data lookup table is customized to merely include burst data for target agents that communicate with IA225. Such an embodiment would allow for different information in each data lookup table. Under this embodiment the generation of burst conversion signals would result in conversion signals merely being generated for the burst characteristics of target agents that can communicate with IA225. In another embodiment, each agent may possess customized internal logic to merely contain burst capabilities of the target agents that may communicate with that initiator agent. Hence, the logic in each initiator agent could comprise different data.

The generation of conversion signals occurs in parallel, allowing the conversion signals to complete at substantially the same time. Further, the address decode must also be processed. The address decode informs IA225which target core requires the burst data. As with width conversion, the address decode processing occurs in parallel to the generation of the burst conversion signals. This offers an advantage of the prior art, which would process the address decode first and then generates the burst conversion signals afterwards. Once the address decode is complete, IA225knows that the burst data is to be transmitted to TC280. Since the burst conversion for TA280has already been computed, time is saved over the prior art's serial approach.

At this point, BCU410transmits the converted burst data425via interface communication line232into Core Logic235. Since the burst conversion has already been completed, Core Logic235is not required to perform any processing. All processing was reserved for the outside perimeter of interconnect201. Since Core Logic235does not need to process any of the burst data425, the data passes directly through Core Logic235(noted by the dotted line) and into TA250via interface communication line238. Lastly, burst data425has some final conversion that occurs in BCU440, before passing to TC280via interface communication line265.

FIG. 5further illustrates the process by which width conversion occurs in parallel to address decoding. IA225comprises WDU415and address decoder525. In this embodiment there are three target agents that could physically receive data from IA225. These include TA240, TA245and TA250. In this example data is passed from IC205(not shown) to IA225via interface communication line215. This data includes address decode information505and510. At this point, address decoder525begins decoding the address of the target core awaiting this data. While the address decoding occurs, WDU415receives information from data lookup table418. This table provides WDU415with a list of all the target agents, and their data width, that could physically receive data from IA225. WDU415uses this information to concurrently generate width conversion signals for all three possible target agents. This can be seen by the three processes running in parallel within WDU415. Process540generates width conversion signals for TA240; Process545generates width conversion signals for TA245; and Process550generates width conversion signals for TA250.

Once address decoder525completes its address decode, it passes the target identity547to WDU415. WDU415now knows that TA245is to receive the data. Hence, the helper signals543generated by process545are passed to width converter logic450within Logic Core235. As noted inFIG. 4, the majority of the processing is accomplished outside Logic Core235and pushed to the outside perimeter of interconnect201. The processing done by Logic Core235is the actual width conversion (through the help of helper signals543). Once the width conversion is complete, the width converted data548passes to TA245.

FIG. 6illustrates different types of width conversions that may take place in the interconnect core. These four types are merely examples and are not meant to be the only types available. WCU610is responsible for using a Strip Technique for converting two words that are 2× wide but merely have data in half the word. For example, the second word contains “B” in the second half of the word, while being padded with meaningless code in the first half of the word. The first word contains “A” in the first half of the word, while being padded with meaningless code in the second half of the word. WCU610converts the 2× wide words to 1× wide by stripping the padded spaces in each word. The result is 2 words that are 1× wide, but still contain the complete data of “A” and “B”.

WCU620is responsible for using an Unpack Technique for converting two words that are 2× wide into four words that are 1× wide. The first word contains “A” and “B” and the second word contain “C” and “D”. WCU620converts the two 2× wide words by unpacking the two parts of each word into individual words that are 1× wide. The result is four words that are 1× wide, where each word contains “A”, “B”, “C”, and “D” consecutively.

WCU630is responsible for using a Pad Technique for converting two words that are 1× wide into two words that are 2× wide. The first word contains “A” and the second word contains “B”. Since the resulting words are twice the width of the starting words WCU630pads each 2× word with a space. The result is a first 2× word that has a space in the first half and “B” in the second half followed by a second 2× word that has a space in the first half and “A” in the second half.

WCU640is responsible for using a Pack Technique for converting four words that are 1× wide into two words that are 2× wide. The four 1× words contain “A”, “B”, “C”, and “D”, consecutively. WCU640packs two of the 1× words into a single 2× word. The result is a first 2× word that has “B” in the first half and “A” in the second half followed by a second 2× word that has “D” in the first half and “C” in the second half.

FIG. 9illustrates a flowchart of different types of burst conversions that may occur by a Burst Conversion Unit within an Initiator Agent sending burst data to a Target Agent. This flowchart provides example embodiments and is no way meant as the only types of burst conversion.FIG. 9describes three types of burst conversion; 1) pass through un-chopped; 2) chop repeatedly; and 3) chop to single transfers. It is desirable to keep the burst length as long as possible, hence chopping to single transfers would be the least preferred conversion, with pass-through un-chopped being the preferred conversion. “Pass through un-chopped” means that no burst conversion is actually required and the data may pass directly through without alteration. This technique would be used if the target supports the incoming burst sequence type and length, and there are no other special chopping conditions. “Chop Repeatedly” means to repeatedly chop the burst data to limit the size of each outgoing interconnect burst. Specifically this means generating additional burst requests with a smaller length associated with the additional burst request and continually subtracting from the initial burst length until it reaches zero. This technique would be used if the target supports the incoming burst sequence type but not the length, and there are no other special chopping conditions. “Chop to Single transfers” means converting the burst into a stream of single initiator transfers, hence removing the burst altogether and converting it into multiple, single transfers. This technique would be used if 1) the target does not support the incoming burst type or has no burst support; or 2) the target merely has precise burst support, but the incoming burst is imprecise; or 3) if the burst is an incrementing address (INCR) burst request AND the target is burst-aligned, but the incoming burst does not follow burst-alignment rules; or 4) if the burst is a burst request (WRAP) burst AND (the target does not support the length of the incoming burst) OR [(the target is wider than the initiator) AND (the starting address is not aligned to a target word)]. Such single transfer requests are treated as precise bursts of a one response solicited per one request.

Certain criteria are used to determine which burst conversion type may be used. At the start of the flow process inFIG. 9, it must be determined whether the target has burst support and if it supports the burst sequence type910. If the answer is “No”, the burst conversion type used is “Chop to Single Transfers”960and the flow ends. If the answer is “Yes” than it must be determined if the target merely has precise burst support and if the burst is imprecise920. If the answer is “Yes”, the burst conversion type used is “Chop to Single Transfers”960and the flow ends. If the answer is “No,” then it should be determined if the burst is an incrementing address (INCR) burst request and if the target is burst-aligned and if the burst does not follow burst-aligned rules930. If the answer is “Yes”, the burst conversion type used is “Chop to Single Transfers”960and the flow ends. If the answer is “No,” then it should be determined if the burst is a wrapping address over two multiple initiator words burst request (WRAP) burst and if the target does not support the burst length OR if the target data width support is wider than the initiator and if the burst starting address is not aligned to the target word940. If the answer is “Yes”, the burst conversion type used is “Chop to Single Transfers”960and the flow ends. If the answer is “No,” then it should be determined if the target supports the burst length950. If the answer is “Yes”, the burst conversion type used is “Pass Through”980and the flow ends. If the answer is “No”, the burst conversion type used is “Chop Repeatedly”970and the flow ends.

As stated above, the three burst conversion techniques described are not conclusive. Other techniques or criteria may be used to alter a burst stream. A person of ordinary skill in the art would be able to implement other burst conversion techniques.

In one embodiment, the software used to facilitate the protocol and algorithms associated with the width and burst conversion can be embodied onto a machine-readable medium. A machine-readable medium includes any mechanism that provides (e.g., stores and/or transmits) information in a form readable by a machine (e.g., a computer). For example, a machine-readable medium includes read only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; DVD's, EPROMs, EEPROMs, FLASH, magnetic or optical cards, or any type of media suitable for storing electronic instructions. The information representing the apparatuses and/or methods stored on the machine-readable medium may be used in the process of creating the apparatuses and/or methods described herein. For example, the information representing the apparatuses and/or methods may be contained in an Instance, soft instructions in an IP generator, or similar machine-readable medium storing this information.

The IP generator may be used for making highly configurable, scalable System On a Chip inter-block communication systems that integrally manages data, control, debug and test flows, as well as other applications. In an embodiment, an example intellectual property generator may comprise the following: a graphic user interface; a common set of processing elements; and a library of files containing design elements such as circuits, control logic, and cell arrays that define the intellectual property generator. In an embodiment, a designer chooses the specifics of the interconnect configuration to produce a set of files defining the requested interconnect instance. An interconnect instance may include front end views and back end files. The front end views support documentation, simulation, debugging, and testing. The back end files, such as a layout, physical LEF, etc are for layout and fabrication.