Conference system

A conference system is disclosed which is capable of freely setting the sound volume level by making the sound volume levels of the input and output of the conference circuit variable for each participant, by pluralities of input and output ROM converters so that the levels of voices of participants of large and small line losses are made as close to each other as possible and that the participant of a large line loss is supplied with a voice of low attenuation.

BACKGROUND OF THE INVENTION 
The present invention relates to a conference system which utilizes a time 
division digital switch. 
Conventionally this kind of system employs a method which subjects 
participant's voices to an N-1 addition while holding their sound levels 
unchanged or after equally attenuating them for preventing singing. On 
this account, for example, in the case of a three-party communication 
involving a CO line A of a large line loss and intercom lines B and C of a 
small line loss, the intercom line B is supplied with the sum of voice (A) 
of the CO line A and voice (C) of the intercom line C, but the volume of 
the voice (A) is small and the volume of the voice (C) is large, so the 
voice of the CO line A is difficult to hear on the intercom line B. 
Furthermore, when the participant's voices are equally attenuated for the 
prevention of singing, the voices that reach the participant of a large 
line loss are appreciably low and difficult to hear, and when a two-party 
communication is switched to a three-party one, sound volume variations 
are caused, creating a sense of incongruity. 
SUMMARY OF THE INVENTION 
It is therefore an object of the present invention to provide a conference 
system which is capable of freely setting the sound volume level by making 
the sound volume levels of the input and output of the conference circuit 
variable, for each participant, by pluralities of input and output ROM 
converters so that the levels of voices of participants of large and small 
line losses are made as close to each other as possible and that the 
participant of a large line loss is supplied with a voice of low 
attenuation.

DETAILED DESCRIPTION 
FIG. 1 shows the concept of the conference system to which the present 
invention is applied. A participant's signal provided on an input highway 
1 is applied into a highway switching circuit 2 and a conference 
communication circuit 4 at the same time. In this instance, output 
switches 21, 22 and 23 of the highway switching circuit 2 are each turned 
OFF and output switches 41, 42 and 43 of the conference circuit 4 are each 
turned ON at the timing of the participants channel of the output highway. 
Furthermore, a signal conference-operated in the conference communication 
circuit 4 is output at the timing of the conferee's channel of the output 
highway. FIG. 1 shows, in the interest of clarity, a case where the number 
of conferees is three and their voice signals are identified by A, B and 
C, respectively, and are each assigned to a particular one of three 
channels of the highway. 
As is evident from FIG. 1, since the participant's signal is not applied to 
the highway switching circuit 2 but is input directly into the conference 
circuit 4, the voice delay is smaller than in the past. 
FIG. 2 represents the concept of the present invention, in which the 
participant's signal provided on the input highway 1 is stored in an input 
memory 11. A signal read out of the input memory 11 is applied to any one 
of table of first ROM converters 12, each determined by a participant, 
wherein it is converted from a PCM code to a linear code and at the same 
time its sound volume is attenuated (or amplified). The ROM converter 
output is provided to an operation circuit 13, wherein it is subjected to 
conference processing. Its output is applied to a second ROM converter 
determined by each participant, wherein it is converted from the linear 
code to the PCM code and at the same time its sound volume is attenuated 
(or amplified), thereafter being stored in an output memory 15. 
Accordingly, sound volume level of a conference signal which is delivered 
from the output memory 15 to the output highway 2 can be freely set in the 
first and second ROM converters 12 and 14 which are determined by each 
participant. 
TABLE 1 
______________________________________ 
Symbol Designation 
______________________________________ 
ADD Adding Register 
BD Bus Driver 
CHG Bit Change Circuit 
CNT Counter 
COMP Comparator 
CON Connection Information Register 
CTM Control Memory 
CTR Control Memory Register 
DEC Decoder 
FA Adder 
HPS Parallel-Serial Converter 
HSP Serial-Parallel Converter 
HWG Highway Gate Flip-Flop 
HWR Highway Register 
INM Input Memory 
LMT .mu.-Law to Linear Code Translation Table 
MLT Linear to .mu.-Law Code Translation Table 
MPX Multiplexer 
NBD Negative Bus Driver 
OTM Output Memory 
PNO Port Number Register 
RHWY Input Highway 
ROM Read-Only Memory 
SPR Speech Register File 
THWY Output Highway 
TKM Trunk Memory 
TNO Trunk Number Register 
______________________________________ 
FIG. 3 illustrates an embodiment of the conference circuit 4 for use in the 
present invention, and designations of symbols used therein are given in 
Table 1. 
The conference circuit 4 depicted in FIG. 3 is used, along with a highway 
switching circuit for controlling eight highways (32 channels/highway), 
and includes eight conference trunks (four participants/trunk). 
The highway is divided into input highways and output highways, and though 
not shown, codecs corresponding to telephone sets or CO lines are each 
assigned the port number (the highway number+the channel number) by a 
fixed time slot system. Each codec performs transmission and reception of 
PCM data between it and the input/output highway at the timing of a 
channel determined by the port number. Further, PCM companding follows the 
.mu.-law. 
A description will be given, with reference to FIG. 3, of the operation of 
the conference circuit. A counter (CNT) operates on external clock timings 
.phi. and frame pulses (FP), and timings T.sub.0 to T.sub.7 and timings 
S.sub.0 to S.sub.3 are created by a decoder (DEC.sub.2). The above timing 
relation is shown in FIG. 4. Data on an input highway (RHWY) from a codec 
of each port is converted by one of serial-parallel converters (HSP.sub.0 
to HSP.sub.7) which operate on clock timings of .phi., and is transferred 
to one of highway registers (HWR.sub.0 to HWR.sub.7) at the timing 
T.sub.0. 
To input memories (INM.sub.0 to INM.sub.7) are supplied addresses from the 
counter (CNT) via a multiplxer (MPX.sub.1) at the timing T.sub.7 and the 
data in the highway registers (HWR.sub.0 to HWR.sub.7) is stored into the 
input memories (INM.sub.0 to INM.sub.7) in such a format as shown in FIG. 
4. Since the counter (CNT) operates as shown in the timing chart of FIG. 
4, data of 32 channels is sequentially loaded into the input memories 
(INM.sub.0 to INM.sub.7) within one frame period 125 .mu.s. Of the data 
stored in the input memories (INM.sub.0 to INM.sub.7), data of 
conference-participating ports is subjected to conference processing 
described later and then stored in output memories (OTM.sub.0 to 
OTM.sub.7) corresponding to the conference-participating ports. The output 
memories (OTM.sub.0 to OTM.sub.7) are each supplied with, as an address, a 
value which is obtained by adding "2" in an adder (FA.sub.0) to a value 
applied thereto from the counter (CNT) via the multiplexer (MPX.sub.1) at 
the timing T.sub.7, and the corresponding data stored in one of the output 
output memories (OTM.sub.0 to OTM.sub.7) is transferred to one of 
parallel-serial converters (HPS.sub.0 to HPS.sub.7). On the other hand, 
when the output memories (OTM.sub.0 to TOM.sub.7) are read out, the same 
address as that applied to the output memories (OTM.sub.0 to OTM.sub.7) is 
also provided via a multiplexer (MPX.sub.3) to a control memory (CTM), at 
the same timing as the readout of the output memories (OTM.sub.0 to 
OTM.sub.7), by which the corresponding data in the control memory (CTM) is 
transferred to highway gate flip-flops (HWG.sub.0 to HWG.sub.7) on a 
bitwise basis. The control memory (CTM) has stored therein bits the number 
of which is equal to (the number of highways).times.(the number of 
channels), as shown in FIG. 8(2). The individual bits are independently 
set by an external processor in a manner described later. Accordingly, the 
highway gate flip-flops (HWG.sub.0 to HWG.sub.7) are set or reset 
according to the contents of the control memory (CTM), and only when they 
are in the set state, the outputs from the parallel-serial converters 
(HPS.sub.0 to HPS.sub.7) are transferred via bus drivers (BD) to output 
highways (THWY). When they are in the reset state, the outputs of the bus 
drivers (BD) are in a high-impedance state, in which they can be 
wired-ORed with the output of a highway switching circuit described later. 
The aforementioned conference processing of one trunk is executed, as 
shown in FIG. 5, in 15.625 .mu.s allocating to four channels which is 
obtained by equally dividing into one-eighth a transmission time 125 .mu.s 
of 32 channels. The process of operation concerning one trunk is shown in 
detail in the timing chart of FIG. 9 and its outline is as follows: 
In a trunk memory (TKM) in FIG. 3, as depicted in FIG. 8(3), four words (15 
bits/word) are assigned to one trunk, and each word has accommodated 
therein port information (the port number+ID) of four participants by a 
method described later. In this case, ID is individual information 
including a port loss of -0, a port loss of -1 and a connection flag, as 
shown in FIG. 8(3). To the trunk memory (TKM) is applied the output of the 
counter (CNT), as an address, via a multipexer (MPX.sub.0) at the timings 
T.sub.0 to T.sub.2 and T.sub.4 to T.sub.6. The address changes for each 
timing and four words of the same trunk are successively read out word by 
word at the timings S.sub.0 and S.sub.1, and at the timings S.sub.2 and 
S.sub.3, four words of the same trunk are read out again in succession. 
Thereafter the same operation is repeated for the next trunk. As a result, 
the above operation takes place for eight trunks in 125 .mu.s. 
Now, when a first word (A) of a certain trunk of the trunk memory (TKM) is 
read out at the timing T.sub.0 to T.sub.2 of S.sub.0, speech data (a) is 
read out from that one of the input memories (INM.sub.0 to INM.sub.7) 
which corresponds to the port number (output at D.sub.0-4 and D.sub.5-7 of 
the trunk memory (TKM)), and is input into a terminal A.sub.0-6 of a 
multiplexer (MPX.sub.4). On the other hand, since the port loss of -1 
(PL1) (derived at D.sub.8-10 of the TKM) included in the individual 
information (ID) of the word (a) is applied to a terminal A.sub.7-9 of the 
multiplexer (MPX.sub.4), the abovementioned speech data (a) is provided to 
that table of a .mu.-law to linear code translation table (MLT) in a 
read-only memory (ROM) which is specified by the port loss of -1, wherein 
it is converted from a PCM code (a) to a linear code (a') attenuated (or 
amplified) as predetermined, thereafter being delivered out from the 
read-only memory (ROM). The output of the read-only memory (ROM) is set in 
an area (ASP) of a speech register file (SPR) at the timing T.sub.2. The 
output of the area (ASP) is applied to an adder (FA.sub.1), wherein it is 
added with the output of an adding register (ADD), and the added output is 
stored in the adding register (ADD) at the timing T.sub.3. 
In a similar manner, processing concerning second, third and fourth words 
in the aforementioned trunk is performed at the timings T.sub.4 to T.sub.7 
of S.sub.0, T.sub.0 to T.sub.3 of S.sub.1 and T.sub.4 to T.sub.7 of 
S.sub.1. Now, let B, C and D stand for the respective words of (b, c and 
d) for speech data corresponding to the port numbers in the words of (B, C 
and D and b', c' and d') for values into which the speech data of (b, c 
and d) are converted by the read-only memory (ROM). At the point of 
completion of the timing T.sub.3 of S.sub.1, the values of (b', c' and d') 
are set in areas BSP, CSP and DSP of the speech register file (SPR), 
respectively, and the adding register (ADD) is cleared to zero at the 
timing T.sub.1 of S.sub.0, so a value of (a'+b'+c'+d') is stored in the 
adding register (ADD). 
After this, the content (a') of the area (ASP) of the speech register file 
(SPR) is subtracted from the adding register (ADD) via the adder 
(FA.sub.1) at the timing T.sub.0 of S.sub.2, and as a result, the output 
(SPX) of the adder (FA.sub.1) goes to a value of (b'+c'+d'), which is 
input into a terminal B.sub.0-12 of the multiplexer (MPX.sub.4). 
On the other hand, the word A is read out again from the trunk memory (TKM) 
at the timing T.sub.0 to T.sub.2 of S.sub.2, and since the port loss of -0 
(PL0) (derived at D.sub.11-13 of the TKM) in the individual information 
(ID) of the word A is applied to B.sub.13-15 of the multiplexer 
(MPX.sub.4), the aforesaid speech data of (b'+c'+d') is provided to that 
table of linear to .mu.-law code translation table (LMT) in the read-only 
memory (ROM) which is specified by the port loss -0 (PL0), wherein it is 
converted from a linear code of (b'+c'+d') to a PCM code (b'+c'+d')' 
attenuated (or amplified) as predetermined, thereafter being output from 
the read-only memory (ROM). The output of the read-only memory (ROM) is 
loaded, at the timing T.sub.2 of S.sub.2, via a negative bus driver (NBA) 
into that one of the output memories (OTM.sub.0 to OTM.sub.7) which is 
specified by the port number in the word A. 
Likewise, processing corresponding to the port numbers in the words B, C 
and D is performed at the timings T.sub.4 to T.sub.6 of S.sub.2, T.sub.0 
to T.sub.2 of S.sub.3 and T.sub.4 to T.sub.6 of S.sub.3. At the end of 
each timing, codes (c'+d'+a')', (d'+a'+b')' and (a'+b'+c')' are stored in 
those of the output memories (OTM.sub.0 to OTM.sub.7) which correspond to 
the respective port numbers, thus completing the process concerning one 
trunk. 
Since a processing time of 15.625 .mu.s is needed for one trunk, processing 
for eight trunks takes a processing time of 125 .mu.s. 
As will be evident from the above, if the kinds of the .mu. law-to linear 
code translation table (MLT) for determining the input level and the 
linear to .mu. law code translation table (LMT) for determining the output 
level for each participant's port are set in the trunk memory in FIG. 3 at 
each time when the conference trunk is used, then the voice level of 
conference communication can suitably be altered according to the kind of 
the participants, such as a long distance line, a short distance CO line, 
and an intercom etc. 
For example, in a memory map of the read-only memory (ROM) shown in FIG. 
8(4), let it be assumed that x.sub.0, x.sub.1, x.sub.2, x.sub.3, x.sub.4, 
x.sub.5, x.sub.6 and x.sub.7 provide attenuations of 0, 1, 2, 3, 4, 5, 6 
and 7 dB, respectively, and y.sub.0, y.sub.1, y.sub.2, y.sub.3, y.sub.4, 
y.sub.5, y.sub.6 and y.sub.7 attenuations of 0, -1, -2, -3, -4, -5, -6 and 
-7 dB (i.e. amplifications of 0, +1, +2, +3, +4, +5, +6 and +7 dB), 
respectively. In the case of three-party communication among a CO line A 
having a line loss of -4 dB and intercom lines B and C having a line loss 
of 0 dB, if different kinds of tables x.sub.0, y.sub.4 and x.sub.4, 
y.sub.0 are provided for the CO line A and the intercom lines B and C, 
respectively, voices of the intercom lines B and C are provided on the CO 
line A at 0 dB without attenuation (received at -4 dB at the far end of 
the CO line A), voices of the CO line A and the intercom line C are both 
provided on the intercom line B at -4 dB, and voices of the CO line A and 
the intercom line B are both provided on the intercom line C at -4 dB. 
Accordingly, volume of the same voice level as in a two-party 
communication between the intercom line B or C and the CO line party A can 
be obtained in the three-party communication, and since no level 
difference exists between the CO line and the intercom lines, voices are 
easy to be hand. On the other hand, volume on the CO line A during the 
three-party communication is also at the same level as in the case where 
the CO line A is in the two-party communication with the intercom line. 
Therefore, switching from the two-party to the three-party communication 
does not create a sense of incongruity. 
While in the above the code translation tables are set so that no 
difference in volume is present between the intercom line B or C and the 
CO line A or the intercom line C or B, it is evident that the code 
translation tables can be set in a manner to provide a difference of 
several dB between them and that voices can be amplified for the CO line 
with a large line loss, and the combination of code translation tables can 
be changed according to a particular purpose. Furthermore, it is also 
possible to employ different levels for two-party, three-party and 
four-party communications, respectively. 
Memory maps of the trunk memory (TKM) and the control memory (CTM) are as 
shown in FIGS. 8(3) and (2), and required data is set in them by an 
external processor using output instructions depicted in FIG. 10. This is 
shown in detail in the timing chart of FIG. 11 (wherein the arrows 
indicate destinations), and its outline is as follows: An output command 
OUT30 sets the number of a conference circuit (an IC number), the trunk 
number in the conference circuit and the position number in the trunk in a 
trunk number register (TNO), an output command OUT31 sets the 
participant's port number in a port number register (PNO) and then an 
output command OUT32 sets a connection flag to a "1" in a connection 
information register (CON). If a comparator (COMP) detects coincidence 
between the IC number set in the trunk number register (TNO) and an 
externally provided IC number, the output of the trunk number register 
(TNO) is applied to the multiplexer (MPX.sub.0) at the timing T.sub.3 or 
T.sub.6 to produce an address of the trunk memory (TKM), and the contents 
of the port number register (PNO) and the connection information register 
(CON) are loaded via a bus driver (BD) into the trunk memory (TKM) at the 
position of a specified trunk number in such a format as shown in the 
memory map in FIG. 8(3). 
On the other hand, the channel number in the output of the port number 
register (PNO) is applied to the multiplexer (MPX.sub.3) to provide an 
address of the control memory (CTM), and data corresponding to a specified 
channel of the control memory (CTM) is set in a control memory register 
(CTR) at the timing T.sub.1. The output of the control memory register 
(CTR) is applied to a bit change circuit (CHG), wherein its only one bit 
specified by the highway number in the output of the port number register 
(PNO) is changed to a "1". The output of the bit change circuit (CHG) is 
stored again via a bus driver (BD) in the control memory (CTM) at the 
aforesaid channel position at the timing T.sub.2 or T.sub.6. 
The above has described the setting of one port in the trunk memory (TKM) 
and the control memory (CTM), and the operation for its resetting is 
identical with the above except in that the connection flag of the output 
command OUT32 is made state of a "0". 
For setting or resetting a plurality of ports, it is necessary only to 
repeatedly execute the output command OUT30, OUT31 and OUT32. 
According to the above embodiment of the conference circuit, a maximum 
eight of such circuits can be connected in parallel, permitting the 
provision of a conference trunk having up to 64 trunks. 
It is apparent that up to 256 trunks can be obtained by a two-bit increase 
in the bit lengths of the trunk number register (TNO) and the output 
instructions OUT30. 
TABLE 2 
______________________________________ 
Symbol Designation 
______________________________________ 
BD Bus Driver 
CNT Counter 
CONM Connection Memory 
DEC Decoder 
FF Flip-Flop 
G Gate 
INR Input Register 
MPX Multiplexer 
OUTR Output Register 
PS Parallel-Serial Converter 
SP Serial-Parallel Converter 
SPM Speech Data Memory 
______________________________________ 
FIG. 6 illustrates an example of the highway switching circuit 2 for use 
with the conference circuit 4 in the present invention. Table 2 shows the 
designations corresponding to symbols of its respective parts. The highway 
switching circuit depicted in FIG. 6 controls eight highways (32 
channels/highway), each divided into input and output highways 1 and 3. 
Codecs corresponding to CO lines or telephone sets, though not shown, are 
each assigned the port number (the highway number+the channel number) 
through the fixed time slot system, and each codec conducts transmission 
and reception of PCM data between it and the input highways and the output 
highways at the timing determined by the port number. 
A description will be given, with reference to FIG. 6, of the operation of 
the highway switching circuit 2. A counter (CNT) operates on an external 
clock timings of .phi..sub.0 and a decoder (DEC) creates timing slot 
T.sub.0 to T.sub.7, S.sub.0, S.sub.1, u.sub.0 to u.sub.7 and FP, as shown 
in FIG. 7. The timing slots T.sub.0 to T.sub.7 are to identify the highway 
numbers, the timing S.sub.0 is assigned to the data input from the input 
highway (RHWY) to a speech data memory (SPM) and the signal S.sub.1 is 
assigned to the data output from the speech data memory (SPM) to the 
output highway (THWY). Data on the input highway (RHWY), which is sent 
from the codec of each port number, is converted by one of serial-parallel 
converters (SP.sub.0 to SP.sub.7) which operate on a clock timings of 
.phi..sub.1, and is transferred to one of input registers (INR.sub.0 to 
INR.sub.7) at the end of the timing u.sub.7 (i.e. at the beginning of the 
timing u.sub.0). To the speech data memory (SPM) is applied an address 
from the counter (CNT) via the multiplexer (MPX.sub.1) at the timing 
S.sub.0. Since this address is updated upon each occurence of the clock 
timings of .phi..sub.0, the data in the input registers (INR.sub.0 to 
INR.sub.7) is sequentially loaded into the speech data memory (SPM) via 
bus drivers (BD.sub.0 to BD.sub.7) selected by the timing slots T.sub.0 to 
T.sub.7, as shown in FIG. 12(1). In FIG. 12(1), reference characters CHm 
and HWn indicate speech data which is input from the port corresponding to 
an mth channel of an nth highway, and each data is composed of a + or - 
sign (S), a chord and a step. On the other hand, a connection memory 
(CONM) is supplied with an address from the counter (CNT) via the 
multiplexer (MPX.sub.0) at the timing S.sub.1. Of the contents of the 
connection memory (CONM) shown in FIG. 12(2) (wherein CHm and HWn 
indicate, respectively, the port number and an output control flag of the 
destination from which the speech data is delivered to the port 
corresponding to the mth channel of the nth highway), read out by the 
above address, the port number of the destination is provided as an 
address via the multiplexer (MPX.sub.1) to the speech data memory (SPM). 
The speech data read out by the address from the speech data memory (SPM) 
is successively loaded into output registers (OUTR.sub.0 to OUTR.sub.7) 
which are each selected by one of the timing signals T.sub.0 to T.sub.7 
upon each occurrence of the clock timings of .phi..sub.0. The contents of 
the output resisters (OUTR.sub.0 to OUTR.sub.7) are stored in 
parallel-serial converters (PS.sub.0 to PS.sub.7) at the end of the timing 
signal u.sub.7 (i.e. at the beginning of the timing signal u.sub.0) Of the 
contents of the connection memory (CONM), the output control flags are 
directly loaded in the output registers (OUTR.sub.0 to OUTR.sub.7) at the 
timings T.sub.0 to T.sub.7 and thence loaded in flip-flops (FF.sub.0 to 
FF.sub.7) at the timing u.sub.0. The parallel-serial converters (PS.sub.0 
to PS.sub.7) operate on the clock timings of .phi..sub.1 and their outputs 
are provided on the output highway (THWY) via gates (G.sub.0 to G.sub.7) 
when the flip-flops FF.sub.0 to FF.sub.7) are in their set state, but when 
the flip-flops (FF.sub.0 to FF.sub.7) are in their reset state, the 
outputs of the gates (G.sub.0 to G.sub.7) are in the high-impedance state, 
permitting the output of the conference circuit 4 to be wired-ORed. 
Incidentally, frame pulses (FP) from a decoder (DEC) are provided to the 
conference circuit 4 for putting the channels of the conference circuit 4 
and the highway switching circuit 2 in phase with each other. A writing 
operation of information in the connection memory (CONM) is effected by an 
external processor via an external interface circuit through the use of an 
output instruction at the timing S.sub.0. This is accomplished by the same 
method as described previously in connection with the conference circuit 
4, and hence will not be described. 
The above is an embodiment of the present invention and should not be 
construed as limiting the invention specifically thereto. For example, the 
number of participants in one trunk may be three or five. The number of 
trunks used may also be determined. Furthermore, the number of highways 
used need not always be limited specifically to eight. While in the 
embodiment the input highways and the output highways are physically 
isolated from each other, it is evident that they can be isolated in terms 
of time but, physically, can be used so as to have both input and output 
highways functions. Moreover, it is also easy to employ, as the PCM code, 
an A-law code in place of the .mu.-law code. 
In short, various modifications may be effected without departing from the 
scope of the gist of the present invention. Hence the invention can be 
applied widely to various communication apparatus. 
As described above, the present invention permits free and dynamic setting 
of the volume level of a conference with very simple control, and hence is 
advantageous in that the volume difference between a CO line and an 
intercom line can be reduced or volume variations can be suppressed when 
switching a two-party communication to a three-party one, i.e. the volume 
level can be varied according to a particular purpose.