System and method for temporal signal measurement of device under test (DUT) and method of forming system

A measurement system of a device under test (DUT) includes a reference clock synthesizer configured to generate a master reference clock signal, a transmitter unit connected to the reference clock synthesizer and configured to connect to the DUT, and a measurement control system connected to the transmitter unit and configured to control the transmitter unit to generate a test signal pattern based on a first reference clock signal derived from the master reference clock signal, and generate a signal for passing through the DUT based on the test signal pattern. A receiver unit connected to the reference clock synthesizer is configured to connect to the DUT and to detect the signal and generate a digital signal based on the signal and a second reference clock signal derived from the master reference clock signal. The measurement control system is configured to provide an output signal based on the digital signal.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of priority of Singapore patent application No. 10201808233T filed on 21 Sep. 2018, the contents of it being hereby incorporated by reference in its entirety for all purposes.

TECHNICAL FIELD

Various aspects of this disclosure relate to a measurement system for temporal signal measurement of a device under test (DUT). Various aspects of this disclosure relate to a method of forming a measurement system for temporal signal measurement of a device under test (DUT). Various aspects of this disclosure relate to a method of measuring temporal signal of a device under test (DUT).

BACKGROUND

As the speed of transmission keeps increasing, it is important to characterize passive communications channels such as a cable to ensure that the distortion caused to the signal due to the channel transmission parameters is within acceptable limit. Typically, bit error ratio (BER) measurement or eye-diagram measurement is used for this assessment. However, BER measurement is time-consuming, whereas eye-diagram measurement can be intuitive and fast, and so it is a widely adopted measurement method. Currently available test setups for eye-diagram measurement employ a plurality of measurement equipment connected for performing the eye-diagram measurement.

SUMMARY

Various embodiments may provide a measurement system for temporal signal measurement of a device under test (DUT). The measurement system may include a reference clock synthesizer configured to generate a master reference clock signal. The measurement system may include a transmitter unit connected to the reference clock synthesizer and configured to connect to a first end of the device under test (DUT). The measurement system may include a measurement control system connected to the transmitter unit, the measurement control system configured to control the transmitter unit to generate a test signal pattern based on a first reference clock signal derived from the master reference clock signal, and to generate a signal for passing through the device under test (DUT) based on the test signal pattern. The measurement system may include a receiver unit connected to the reference clock synthesizer and configured to connect to a second end of the device under test (DUT), and the receiver unit configured to detect the signal that passes through the device under test (DUT) and further configured to generate a digital signal based on the signal detected and a second reference clock signal derived from the master reference clock signal. In various embodiments, the measurement control system may be connected to the receiver unit, wherein the measurement control system may be further configured to provide an output signal including measurement results based on the digital signal.

Various embodiments may provide a method of forming a measurement system for temporal signal measurement of a device under test (DUT). The method may include connecting a reference clock synthesizer to a transmitter unit and to a receiver unit. The method may include connecting a measurement control system to the transmitter unit and to the receiver unit. In various embodiments, the transmitter unit may be configured to connect to a first end of the device under test (DUT) and the receiver unit may be configured to connect to a second end of the device under test (DUT). In various embodiments, the reference clock synthesizer may be configured to generate a master reference clock signal and the measurement control system may be configured to control the transmitter unit to generate a test signal pattern based on a first reference clock signal derived from the master reference clock signal, and to generate a signal for passing through the device under test (DUT) based on the test signal pattern. In various embodiments, the receiver unit may be configured to detect the signal that passes through the device under test (DUT) and may be configured to generate a digital signal based on the signal detected and a second reference clock signal derived from the master reference clock signal. In various embodiments, the measurement control system may be further configured to provide an output signal including measurement results based on the digital signal.

Various embodiments may provide a method of measuring temporal signal of a device under test (DUT). The method may include generating a master reference clock signal using a reference clock synthesizer. The method may include using a measurement control system connected to a transmitter unit to control the transmitter unit to generate a test signal pattern based on a first reference clock signal derived from the master reference clock signal, and to generate a signal for passing through the device under test (DUT) based on the test signal pattern, wherein the transmitter unit connected to the reference clock synthesizer and connected to a first end of the device under test (DUT). The method may include detecting the signal that passes through the device under test (DUT) and generating a digital signal based on the signal detected and a second reference clock signal derived from the master reference clock signal, using a detector unit connected to the measurement control system, the reference clock synthesizer and to a second end of the device under test (DUT). The method may include providing an output signal including measurement results based on the digital signal using the measurement control system.

DETAILED DESCRIPTION

Embodiments described below in the context of the system are analogously valid for the respective methods, and vice versa. Furthermore, it will be understood that the embodiments described below may be combined, for example, a part of one embodiment may be combined with a part of another embodiment.

It should be understood that the terms “on”, “over”, “top”, “bottom”, “down”, “side”, “back”, “left”, “right”, “front”, “lateral”, “side”, “up”, “down” etc., when used in the following description are used for convenience and to aid understanding of relative positions or directions, and not intended to limit the orientation of any system, device, or structure or any part of any system, device or structure.

Various embodiments may provide a measurement system for temporal signal measurement of a device under test (DUT).

FIG. 1is an illustration of a measurement system100for temporal signal measurement of a device under test (DUT)110according to various embodiments.

In various embodiments, the measurement system100may include a reference clock synthesizer120configured to generate a master reference clock signal. The measurement system100may include a transmitter unit130connected to the reference clock synthesizer120and configured to connect to a first end111of the device under test (DUT)110. The measurement system may include a measurement control system140connected to the transmitter unit130, the measurement control system140configured to control the transmitter unit130to generate a test signal pattern based on a first reference clock signal derived from the master reference clock signal, and to generate a signal for passing through the device under test (DUT)110based on the test signal pattern.

In various embodiments, reference clock synthesizer120may be capable of providing a plurality of reference clock signals. In various embodiments, the master reference clock signal may be generated at a specified frequency. In various embodiments, the first reference clock signal may be generated at a specified frequency.

In various embodiments, the test signal pattern may be predetermined. In various embodiments, the test signal pattern may be a pseudo random binary sequence (PRBS). In various embodiments, the test signal pattern may be a square wave sequence. The type of the test signal pattern is not limited thereto, suitable the test signal pattern may be used.

In various embodiments, the transmitter unit130may be an optical transmitter unit. In various embodiments, the signal for passing through the device under test (DUT)110may be an optical signal.

In various embodiments, the first reference clock signal may be an integer or fractional multiple of the master reference clock signal. In various embodiments, the master clock signal and the first reference clock signal may be synchronized. In various embodiments, the first reference clock signal and the master reference clock signal may be phase-locked.

In various embodiments, the measurement system may include a receiver unit150connected to the reference clock synthesizer120and configured to connect to a second end112of the device under test (DUT)110, and the receiver unit150configured to detect the signal that passes through the device under test (DUT)110and further configured to generate a digital signal based on the signal detected and a second reference clock signal derived from the master reference clock signal. In various embodiments, the measurement control system140may be connected to the receiver unit150.

In various embodiments, the receiver unit150may be an optical receiver unit. In various embodiments, the signal that passes through the device under test (DUT)110may be an optical signal.

In various embodiments, the second reference clock signal may be an integer or fractional multiple of the master reference clock signal. In various embodiments, the master clock signal and the second reference clock signal may be synchronized. In various embodiments, the second reference clock signal and the master reference clock signal may be phase-locked.

In various embodiments, the measurement control system140may be further configured to provide an output signal including measurement results based on the digital signal.

In various embodiments, the measurement result may be an eye-diagram measurement. In various embodiments, the measurement result may be in any suitable form.

In various embodiments, the measurement control system140may provide the measurement result to an external device. The external device may be a display monitor or a computer or a storage device. The type of device is not limited thereto, suitable device may be used. In various embodiments, the measurement control system140may provide the measurement result to an inbuilt display device or computer.

In various embodiments, the measurement control system140may be connected to a device via a standard communication interface such as an Ethernet cable or by any other suitable means.

In various embodiments, the device under test (DUT)110may be a cable. The cable may be a copper cable or an optical fiber cable. The optical fiber cable may be a multi-fiber cable. The type of cable is not limited thereto, any suitable cable may be used.

In various embodiments, the device under test (DUT)110may be a semiconductor device or a printed circuit board (PCB). The type of device is not limited thereto, any suitable device may be used.

In various embodiments, the measurement system100for temporal signal measurement of a device under test (DUT)110may be a single test equipment. In various embodiments, in the single test equipment, the transmitter unit130and receiver unit150may use a common clock source.

In various embodiments, a period of a test signal may be spanned by 1,000 samples of sampling frequency.

In various embodiments, the signal for passing through the device under test (DUT)110based on the test signal pattern may be generated by the transmitter unit130at test frequency f_t.

In various embodiments, the signal that passes through the device under test (DUT)110may be sampled by the receiver unit150at a sampling frequency of f_s. The samples may be digitized to produce digitized received test pattern. In various embodiments, the sampling frequency f_s may be a fraction of the test frequency f_t such that some specific number N of consecutive samples may span a full waveform of the test signal.

In various embodiments, the measurement control system140may collect the digitized received test pattern. The measurement control system140may provide an output signal including measurement results. The measurement control system140may present the digitized received test pattern in the form of an eye diagram.

The table below shows an example of possible clock ratios of the test frequency f_t, the sampling frequency f_s and a fractional ratio of the test frequency f_t and the sampling frequency f_s.

FIG. 2shows a flowchart of a method200of forming a measurement system100for temporal signal measurement of a device under test (DUT)110according to various embodiments.

In various embodiments, a first step210of the method200may include connecting a reference clock synthesizer120to a transmitter unit130and to a receiver unit150.

In various embodiments, a second step220of the method200may include connecting a measurement control system140to the transmitter unit130and to the receiver unit150.

In various embodiments, the transmitter unit130may be configured to connect to a first end111of the device under test (DUT)110and the receiver unit150may be configured to connect to a second end112of the device under test (DUT)110.

In various embodiments, the reference clock synthesizer120may be configured to generate a master reference clock signal and the measurement control system140may be configured to control the transmitter unit130to generate a test signal pattern based on a first reference clock signal derived from the master reference clock signal, and may generate a signal for passing through the device under test (DUT)110based on the test signal pattern.

In various embodiments, reference clock synthesizer120may be capable of providing a plurality of reference clock signals. In various embodiments, the master reference clock signal may be generated at a specified frequency. In various embodiments, the first reference clock signal may be generated at a specified frequency.

In various embodiments, the test signal pattern may be predetermined. In various embodiments, the test signal pattern may be a pseudo random binary sequence (PRBS). In various embodiments, the test signal pattern may be a square wave sequence. The type of the test signal pattern is not limited thereto, suitable the test signal pattern may be used.

In various embodiments, the transmitter unit130may be an optical transmitter unit. In various embodiments, the signal for passing through the device under test (DUT)110may be an optical signal.

In various embodiments, the first reference clock signal may be an integer or fractional multiple of the master reference clock signal. In various embodiments, the master clock signal and the first reference clock signal may be synchronized. In various embodiments, the first reference clock signal and the master reference clock signal may be phase-locked.

In various embodiments, the receiver unit150may be configured to detect the signal that passes through the device under test (DUT)110and may be configured to generate a digital signal based on the signal detected and a second reference clock signal derived from the master reference clock signal. In various embodiments, the measurement control system140may be connected to the receiver unit150.

In various embodiments, the receiver unit150may be an optical receiver unit. In various embodiments, the signal that passes through the device under test (DUT)110may be an optical signal.

In various embodiments, the second reference clock signal may be an integer or fractional multiple of the master reference clock signal. In various embodiments, the master clock signal and the second reference clock signal may be synchronized. In various embodiments, the second reference clock signal and the master reference clock signal may be phase-locked.

In various embodiments, the measurement control system140may be further configured to provide an output signal including measurement results based on the digital signal.

In various embodiments, the measurement result may be an eye-diagram measurement. In various embodiments, the measurement result may be in any suitable form.

In various embodiments, the measurement control system140may provide the measurement result to an external device. The external device may be a display monitor or a computer or a storage device. The type of device is not limited thereto, suitable device may be used. In various embodiments, the measurement control system140may provide the measurement result to an inbuilt display device or computer.

In various embodiments, the measurement control system140may be connected to a device via a standard communication interface such as an Ethernet cable or by any other suitable means.

In various embodiments, the device under test (DUT)110may be a cable. The cable may be a copper cable or an optical fiber cable. The optical fiber cable may be a multi-fiber cable. The type of cable is not limited thereto, any suitable cable may be used.

In various embodiments, the device under test (DUT)110may be a semiconductor device or a printed circuit board (PCB). The type of device is not limited thereto, any suitable device may be used.

In various embodiments, the measurement system100for temporal signal measurement of a device under test (DUT)110may be formed as a single test equipment. In various embodiments, in the single test equipment, the transmitter unit130and receiver unit150may use a common clock source.

In various embodiments, the order of the steps of the method200is not limited thereto, any suitable order may be used. Various embodiments may also include methods related to any components included in the transmitter unit130and/or the receiver unit150.

FIG. 3shows a flowchart of a method300of measuring temporal signal of a device under test (DUT)110according to various embodiments.

In various embodiments, the method300may include a first step310of generating a master reference clock signal using a reference clock synthesizer120.

In various embodiments, the method300may include a second step320of generating a test signal pattern based on a first reference clock signal derived from the master reference clock signal using a transmitter unit controlled by a measurement control system, wherein the measurement control system may be connected to the transmitter unit.

In various embodiments, the method300may include a third step330of generating a signal for passing through the device under test (DUT) based on the test signal pattern using the transmitter unit, wherein the transmitter unit may be connected to the reference clock synthesizer and may be connected to a first end of the device under test (DUT).

In various embodiments, reference clock synthesizer120may be capable of providing a plurality of reference clock signals. In various embodiments, the master reference clock signal may be generated at a specified frequency. In various embodiments, the first reference clock signal may be generated at a specified frequency.

In various embodiments, the test signal pattern may be predetermined. In various embodiments, the test signal pattern may be a pseudo random binary sequence (PRBS). In various embodiments, the test signal pattern may be a square wave sequence. The type of the test signal pattern is not limited thereto, suitable the test signal pattern may be used.

In various embodiments, the transmitter unit130may be an optical transmitter unit. In various embodiments, the signal for passing through the device under test (DUT)110may be an optical signal.

In various embodiments, the first reference clock signal may be an integer or fractional multiple of the master reference clock signal. In various embodiments, the master clock signal and the first reference clock signal may be synchronized. In various embodiments, the first reference clock signal and the master reference clock signal may be phase-locked.

In various embodiments, the method300may include a fourth step340of detecting the signal that passes through the device under test (DUT)110and may include generating a digital signal based on the signal detected and a second reference clock signal derived from the master reference clock signal, using the receiver unit150connected to the measurement control system140, the reference clock synthesizer120and to a second end112of the device under test (DUT)110.

In various embodiments, the receiver unit150may be an optical receiver unit. In various embodiments, the signal that passes through the device under test (DUT)110may be an optical signal.

In various embodiments, the second reference clock signal may be an integer or fractional multiple of the master reference clock signal. In various embodiments, the master clock signal and the second reference clock signal may be synchronized. In various embodiments, the second reference clock signal and the master reference clock signal may be phase-locked.

In various embodiments, the method300may include a fifth step350of providing an output signal including measurement results based on the digital signal using the measurement control system140.

In various embodiments, the measurement result may be an eye-diagram measurement. In various embodiments, the measurement result may be in any suitable form.

In various embodiments, the measurement control system140may provide the measurement result to an external device. The external device may be a display monitor or a computer or a storage device. The type of device is not limited thereto, suitable device may be used. In various embodiments, the measurement control system140may provide the measurement result to an inbuilt display device or computer.

In various embodiments, the measurement control system140may be connected to a device via a standard communication interface such as an Ethernet cable or by any other suitable means.

In various embodiments, the device under test (DUT)110may be a cable. The cable may be a copper cable or an optical fiber cable. The optical fiber cable may be a multi-fiber cable. The type of cable is not limited thereto, any suitable cable may be used.

In various embodiments, the device under test (DUT)110may be a semiconductor device or a printed circuit board (PCB). The type of device is not limited thereto, any suitable device may be used.

In various embodiments, the measurement system100for temporal signal measurement of a device under test (DUT)110may be formed as a single test equipment. In various embodiments, in the single test equipment, the transmitter unit130and receiver unit150may use a common clock source.

In various embodiments, the order of the steps in method300is not limited thereto, any suitable order may be used.

FIG. 4is an illustration of a measurement system400for temporal signal measurement of a device under test (DUT)110according to various embodiments.

In various embodiments, a measurement system400may include a reference clock synthesizer120, a transmitter unit130, a measurement control system140and a receiver unit150.

In various embodiments, the transmitter unit130may include a signal generator410and/or a transmitter module420and/or a first switch430.

In various embodiments, the receiver unit150may include a detector module450and/or a track and hold device460and/or a response signal digitizer470and/or a second switch430.

In various embodiments, transmitter unit130may be connected to the reference clock synthesizer120and may be configured to connect to a first end111of a device under test (DUT)110. In various embodiments, the measurement control system140may be connected to the transmitter unit130. In various embodiments, the receiver unit150may be connected to the reference clock synthesizer120and may be configured to connect to a second end112of the device under test (DUT)110. In various embodiments, the reference clock synthesizer120may be connected to the measurement control system140.

In various embodiments, the transmitter unit130may include a signal generator410connected to the reference clock synthesizer120. In various embodiments, the signal generator410may be configured to receive the first reference clock signal. The signal generator410may be configured to generate the test signal pattern based on the first reference clock signal derived from the master reference clock signal. In various embodiments, the signal generator410may be a radio frequency (RF) signal generator. In various embodiments, the signal generator410generates a predetermined test pattern clocked by a multiple of the first reference clock signal.

In various embodiments, reference clock synthesizer120may be capable of providing a plurality of reference clock signals. In various embodiments, the master reference clock signal may be generated at a specified frequency. In various embodiments, the first reference clock signal may be generated at a specified frequency.

In various embodiments, the test signal pattern may be predetermined. In various embodiments, the test signal pattern may be a pseudo random binary sequence (PRBS). In various embodiments, the test signal pattern may be a square wave sequence. The type of the test signal pattern is not limited thereto, suitable the test signal pattern may be used.

In various embodiments, the signal generator410may be connected to the measurement control system140.

In various embodiments, the transmitter unit130may include a transmitter module420connected to the signal generator410, the transmitter module420may be configured to generate the signal for passing through the device under test (DUT)110based on the test signal pattern.

In various embodiments, the transmitter module420may be an optical transmitter module. In various embodiments, the signal for passing through the device under test (DUT)110may be an optical signal.

In various embodiments, the transmitter module420may be connected to the reference clock synthesizer120and the measurement control system140. In various embodiments, the transmitter module420may perform the function of the signal generator410.

In various embodiments, the first reference clock signal may be an integer or fractional multiple of the master reference clock signal. In various embodiments, the master clock signal and the first reference clock signal may be synchronized. In various embodiments, the first reference clock signal and the master reference clock signal may be phase-locked.

In various embodiments, the receiver unit150may include a detector module450which may be configured to detect the signal that passes through the device under test (DUT)110and may be configured to generate a response signal based on the signal detected.

In various embodiments, the signal that passes through the device under test (DUT)110may be an optical signal. The detector module450may be an optical detector module. The detector module450may receive the optical signal from the device under test (DUT)110and may convert it to an electrical signal. In various embodiments, the detector module450may be configured to connect to a second end112of the device under test (DUT)110.

In various embodiments, the receiver unit150may include a track and hold device460connected to the detector module450and the reference clock synthesizer120, the track and hold device460may be configured to generate a sampled response signal based on the response signal and based on a third reference clock signal derived from the master reference clock signal. In various embodiments, the track and hold device460may be capable of tracking the response signal and holding the response signal when a clock edge is received, the output of the track and hold device460being the sampled response signal. The track and hold device460may sample the response signal at the edge of a third reference clock signal. The frequency of the third reference clock signal may be derived using sub-sampling based scheme such that a response to a complete predetermined test pattern may be sampled over a plurality of cycles of the predetermined test pattern.

In various embodiments, the holding of the response signal is not limited to the clock edge, the track and hold device460may track the response signal and hold the response signal at any suitable period.

In various embodiments, the third reference clock signal may be an integer or fractional multiple of the master reference clock signal. In various embodiments, the master clock signal and the third reference clock signal may be synchronized. In various embodiments, the third reference clock signal and the master reference clock signal may be phase-locked.

In various embodiments, the track and hold device460may be configured to connect to a second end112of the device under test (DUT)110. In various embodiments, the track and hold device460may perform the function of the detector module450.

In various embodiments, the receiver unit150may include a response signal digitizer470connected to the track and hold device460and the reference clock synthesizer120, the response signal digitizer470may be configured to generate the digital signal based on the sampled response signal and the second reference clock signal derived from the master reference clock signal.

In various embodiments, the second reference clock signal may be an integer or fractional multiple of the master reference clock signal. In various embodiments, the master clock signal and the second reference clock signal may be synchronized. In various embodiments, the second reference clock signal and the master reference clock signal may be phase-locked.

In various embodiments, the measurement control system may be connected to the reference clock synthesizer120and the response signal digitizer470. In various embodiments, the measurement control system may be configured to provide the output signal including the measurement results based on the digital signal generated by the response signal digitizer470, and a fourth reference clock signal derived from the master reference clock signal.

In various embodiments, the fourth reference clock signal may be an integer or fractional multiple of the master reference clock signal. In various embodiments, the master clock signal and the fourth reference clock signal may be synchronized. In various embodiments, the fourth reference clock signal and the master reference clock signal may be phase-locked.

In various embodiments, the measurement result may be an eye-diagram measurement. In various embodiments, the measurement result may be in any suitable form.

In various embodiments, the measurement control system140may provide the measurement result to an external device. The external device may be a display monitor or a computer or a storage device. The type of device is not limited thereto, suitable device may be used. In various embodiments, the measurement control system140may provide the measurement result to an inbuilt display device or computer.

In various embodiments, the measurement control system140may be connected to a device via a standard communication interface such as an Ethernet cable or by any other suitable means.

In various embodiments, the device under test (DUT)110may be a cable. The cable may be a copper cable or an optical fiber cable. The optical fiber cable may be a multi-fiber cable. The type of cable is not limited thereto, any suitable cable may be used.

In various embodiments, the device under test (DUT)110may be a semiconductor device or a printed circuit board (PCB). The type of device is not limited thereto, any suitable device may be used.

In various embodiments, the measurement system400for temporal signal measurement of a device under test (DUT)110may be a single test equipment. In various embodiments, in the single test equipment, the transmitter unit130and receiver unit150may use a common clock source.

In various embodiments, the first reference clock signal, the second reference clock signal, the third reference clock signal, and the fourth reference clock signal may be an integer or fractional multiple of the master reference clock signal. In various embodiments, the first reference clock signal, the second reference clock signal, the third reference clock signal, and the fourth reference clock signal may be synchronized. In various embodiments, the first reference clock signal, the second reference clock signal, the third reference clock signal, and the fourth reference clock signal may be phase-locked.

In various embodiments, the transmitter unit130may include a first switch430and the signal generated by the transmitter unit130for passing through the device under test (DUT)110may pass to the device under test (DUT)110via the first switch430. In various embodiments, the receiver unit150may include a second switch440and the signal may pass through the device under test (DUT)110to the receiver unit150via the second switch440.

In various embodiments, the first switch430may be connected to transmitter module430. In various embodiments, the second switch440may be connected to the detector module450.

In various embodiments, the first switch430may be outside transmitter unit130. In various embodiments, the second switch440may be outside receiver unit150.

In various embodiments, the device under test (DUT)110is a multi-fiber cable. The multi-fiber cable may include a plurality of fiber cords. The first switch430may be configured to pass the signal from the transmitter unit130to one of the plurality of fiber cords, and the second switch440may be configured to receive the signal from the one of the plurality of fiber cords.

In various embodiments, the measurement control system140may control which fiber cord of the plurality of fiber cords is used to pass the signal.

In various embodiments, the measurement control system140may sequence through each fiber cord of the plurality of fiber cords and may perform measurement by appropriately configuring the first switch430and the second switch440.

In various embodiments, the transmitter module420may be an optical transmitter module420and may accept the predetermined test signal pattern and convert it to an optical predetermined test signal and further transmits the optical predetermined test signal to the first transmitter fiber cord.

In various embodiments, the first switch430may connect a first transmitter fiber cord of the plurality of fiber cords at an input to one of the plurality of fiber cables at an output.

In various embodiments, the output fiber is selected by an control input from the measurement control system140.

FIG. 5shows a flowchart of a method500of forming a measurement system400for temporal signal measurement of a device under test (DUT)110according to various embodiments.

In various embodiments, the method may include a first step502of connecting the signal generator410in the transmitter unit130to the reference clock synthesizer120. The signal generator410may be configured to generate the test signal pattern based on the first reference clock signal derived from the master reference clock signal. In various embodiments, the signal generator410may be a radio frequency (RF) signal generator. In various embodiments, the signal generator410generates a predetermined test pattern clocked by a multiple of the first reference clock signal.

In various embodiments, reference clock synthesizer120may be capable of providing a plurality of reference clock signals. In various embodiments, the master reference clock signal may be generated at a specified frequency. In various embodiments, the first reference clock signal may be generated at a specified frequency.

In various embodiments, the test signal pattern may be predetermined. In various embodiments, the test signal pattern may be a pseudo random binary sequence (PRBS). In various embodiments, the test signal pattern may be a square wave sequence. The type of the test signal pattern is not limited thereto, suitable the test signal pattern may be used.

In various embodiments, the method may include a second step504of connecting the transmitter module420in the transmitter unit130to the signal generator410. The transmitter module420may be configured to generate the signal for passing through the device under test (DUT)110based on the test signal pattern.

In various embodiments, the transmitter module420may be an optical transmitter module. In various embodiments, the signal for passing through the device under test (DUT)110may be an optical signal.

In various embodiments, the transmitter module420may be connected to the reference clock synthesizer120and the measurement control system140. In various embodiments, the transmitter module420may perform the function of the signal generator410.

In various embodiments, the first reference clock signal may be an integer or fractional multiple of the master reference clock signal. In various embodiments, the master clock signal and the first reference clock signal may be synchronized. In various embodiments, the first reference clock signal and the master reference clock signal may be phase-locked.

In various embodiments, the receiver unit150may include a detector module450. The detector module450may be configured to detect the signal that passes through the device under test (DUT)110and may generate a response signal based on the signal detected.

In various embodiments, the signal that passes through the device under test (DUT)110may be an optical signal. The detector module450may be an optical detector module. The detector module450may receive the optical signal from the device under test (DUT)110and may convert it to an electrical signal. In various embodiments, the detector module450may be configured to connect to a second end112of the device under test (DUT)110.

In various embodiments, the method may include a third step506connecting a track and hold device460in the receiver unit150to the detector module450in the receiver unit150and to the reference clock synthesizer120. The track and hold device460may be configured to receive the response signal from the detector module450. The track and hold device460may be configured to generate a sampled response signal based on the response signal and based on a third reference clock signal derived from the master reference clock signal.

The track and hold device460may sample the response signal at the edge of a third reference clock signal. The frequency of the third reference clock signal may be derived using sub-sampling based scheme such that a response to a complete predetermined test pattern may be sampled over a plurality of cycles of the predetermined test pattern.

In various embodiments, the holding of the response signal is not limited to the clock edge, the track and hold device460may track the response signal and hold the response signal at any suitable period.

In various embodiments, the third reference clock signal may be an integer or fractional multiple of the master reference clock signal. In various embodiments, the master clock signal and the third reference clock signal may be synchronized. In various embodiments, the third reference clock signal and the master reference clock signal may be phase-locked.

In various embodiments, the method may include a fourth step508of connecting a response signal digitizer470in the receiver unit150to the track and hold device460and to the reference clock synthesizer120. The response signal digitizer470may be configured to generate the digital signal based on the sampled response signal and the second reference clock signal derived from the master reference clock signal.

In various embodiments, the second reference clock signal may be an integer or fractional multiple of the master reference clock signal. In various embodiments, the master clock signal and the second reference clock signal may be synchronized. In various embodiments, the second reference clock signal and the master reference clock signal may be phase-locked.

In various embodiments, the method may include a fifth step510of connecting the measurement control system to the reference clock synthesizer120and to the response signal digitizer470. The measurement control system may be configured to provide the output signal including the measurement results based on the digital signal and a fourth reference clock signal derived from the master reference clock signal.

In various embodiments, the fourth reference clock signal may be an integer or fractional multiple of the master reference clock signal. In various embodiments, the master clock signal and the fourth reference clock signal may be synchronized. In various embodiments, the fourth reference clock signal and the master reference clock signal may be phase-locked.

In various embodiments, the measurement result may be an eye-diagram measurement. In various embodiments, the measurement result may be in any suitable form.

In various embodiments, the measurement control system140may provide the measurement result to an external device. The external device may be a display monitor or a computer or a storage device. The type of device is not limited thereto, suitable device may be used. In various embodiments, the measurement control system140may provide the measurement result to an inbuilt display device or computer.

In various embodiments, the measurement control system140may be connected to a device via a standard communication interface such as an Ethernet cable or by any other suitable means.

In various embodiments, the device under test (DUT)110may be a cable. The cable may be a copper cable or an optical fiber cable. The optical fiber cable may be a multi-fiber cable. The type of cable is not limited thereto, any suitable cable may be used.

In various embodiments, the device under test (DUT)110may be a semiconductor device or a printed circuit board (PCB). The type of device is not limited thereto, any suitable device may be used.

In various embodiments, the measurement system400for temporal signal measurement of a device under test (DUT)110may be a single test equipment. In various embodiments, in the single test equipment, the transmitter unit130and receiver unit150may use a common clock source.

In various embodiments, the first reference clock signal, the second reference clock signal, the third reference clock signal, and the fourth reference clock signal may be an integer or fractional multiple of the master reference clock signal. In various embodiments, the first reference clock signal, the second reference clock signal, the third reference clock signal, and the fourth reference clock signal may be synchronized. In various embodiments, the first reference clock signal, the second reference clock signal, the third reference clock signal, and the fourth reference clock signal may be phase-locked.

In various embodiments, the transmitter unit130may include a first switch430.

In various embodiments, the receiver unit150may include a second switch440.

In various embodiments, the first switch430may be configured to pass the signal for passing through the device under test (DUT)110from the transmitter unit130to the device under test (DUT)110. In various embodiments, the second switch440may be configured to pass the signal for passing through the device under test (DUT)110from the device under test (DUT)110to the receiver unit150.

In various embodiments, the first switch430may be connected to transmitter module430. In various embodiments, the second switch440may be connected to the detector module450.

In various embodiments, the first switch430may be outside transmitter unit130. In various embodiments, the second switch440may be outside receiver unit150.

In various embodiments, the device under test (DUT)110may be a multi-fiber cable. The multi-fiber cable may include a plurality of fiber cords. In various embodiments, the signal may be passed from the transmitter unit130to one of the plurality of fiber cords using the first switch430. In various embodiments, the signal may be received by the receiver unit150from the one of the plurality of fiber cords using the second switch440.

The order of the steps of method500is not limited thereto, any suitable order of steps may be used. Also, some steps of method500may be omitted.

A system and method of implementing eye-diagram and other temporal signal quality measurement on the device under test (“DUT”) by using a single test equipment with transmit and receive sections using a common clock source may be provided. The temporal response measurement system provided may be suitable for high-speed communications channels.