Methods to enhance doping concentration in near-surface layers of semiconductors and methods of making same

A die includes a semiconductive prominence and a surface-doped structure on the prominence. The surface-doped structure makes contact with contact metallization. The prominence may be a source- or drain contact for a transistor. Processes of making the surface-doped structure include wet-vapor- and implantation techniques, and include annealing techniques to drive in the surface doping to only near-surface depths in the semiconductive prominence.

CROSS-REFERENCE TO RELATED APPLICATION

This patent application is a U.S. National Phase Application under 35 U.S.C. §371 of International Application No. PCT/US2011/067424, filed Dec. 27, 2011, entitled METHODS TO ENHANCE DOPING CONCENTRATION IN NEAR-SURFACE LAYERS OF SEMICONDUCTORS AND METHODS OF MAKING SAME.

TECHNICAL FIELD

Disclosed embodiments relate to contacts in semiconductive devices and methods to reduce contact resistance. Devices such as transistors are formed on a wafer and are connected using front-end metallization layers. The metallization layers include vias and interconnects that function as electrical pathways to interconnect the devices. Contacts connect the vias and interconnects to the devices.

DETAILED DESCRIPTION

Processes are disclosed near-surface layers of contacts for semiconductive devices are doped to reduce contact resistance. Fabrication of contact near-surface layers includes surface or near-surface doping of the contact surfaces. Improved surface area for source- and drain (S/D) contacts results in reduced resistivity for the contacts by preserving electrical current qualities at the contacts.

Disclosed embodiments resist dopant deactivation/depletion in/from near-surface layers of semiconductor source/drains that may occur as a result of native oxide formation, etch- and surface-cleaning treatments, and damage from metal deposition processes. These deactivations/depletions are expected to be exacerbated as devices are further miniaturized. Contact resistance is inversely proportional to near-surface doping concentration. Thus, disclosed embodiments mitigate contact resistance increases due to miniaturization (also referred to as being “scaled”).

As contact areas and device sizes are scaled, two effects are reduced by use of disclosed embodiments. First, the surface-area-to-volume ratio of the source/drain increases, which may cause a greater fraction of dopants to be deactivated/depleted due to effects of native oxide formation, dopant activation anneals, etch and surface cleaning treatments, and damage from metal deposition processes. Second, as the volume of the source/drain reduces, the number of dopant atoms required to cause significant changes in doping concentration will reduce. Disclosed embodiments lessen these two effects to result in sufficient doping density retained in the near-surface layers and greater heterogeneity such as site-to-site variation. Since the doping density in the near-surface layers impacts contact resistance, disclosed embodiments result in decreased contact resistance.

In a process embodiment, a trench is opened to expose a raised S/D contact. Surface doping is carried out on the raised S/D contact and contact metallization is completed. Thereafter, an anneal process is carried out under conditions to cause solid-state, near-surface diffusion of the surface doping such that the electrical current conveying quality at the surface of the raised S/D is preserved and even improved.

In a process embodiment, annealing of the surface doping is carried out before contact metallization is completed.

Reference will now be made to the drawings wherein like structures may be provided with like suffix reference designations. In order to show the structures of various embodiments more clearly, the drawings included herein are diagrammatic representations of integrated circuit chips fabricated with surface-doped or near-surface doped contacts. Thus, the actual appearance of the fabricated chip substrates, alone or in chip packages, for example in a photomicrograph, may appear different while still incorporating the claimed structures of the illustrated embodiments. Moreover, the drawings may only show the structures useful to understand the illustrated embodiments. Additional structures known in the art may not have been included to maintain the clarity of the drawings.

FIG. 1is a cross-section elevation of an active device100that includes a semiconductive prominence112with a surface-enhanced doping concentration114that is a reaction zone according to an example embodiment. A semiconductive substrate110has been processed with a prominence112disposed thereon. In an embodiment, the prominence112is an epitaxial, raised S/D structure. In an embodiment, the prominence112is a raised S/D structure112such as an epitaxial S/D contact area for a transistor. The reaction zone114is seen between the prominence112and a contact116that is filled into a recess of an interlayer dielectric (ILD) layer118. The ILD layer118may be referred to as a gate-level ILD layer118. Where the prominence112is a raised S/D structure112, a gate structure120is disposed adjacent the prominence112. Details of the gate structure120may include a gate dielectric, gate dielectric spacers, a wordline, and agate dielectric cap.

Other structures may also be present. Metallization such as a contact interconnect124is disposed in a first interconnect ILD layer122. Other metallization is represented as a trace126in a second interconnect ILD layer128.

In an embodiment, the semiconductive substrate110is a semiconductor material such as but not limited to silicon (Si), silicon germanium (SiGe), germanium (Ge), or III-V compound semiconductors. The semiconductive substrate110can be monocrystalline, epitaxial crystalline, or polycrystalline. In an embodiment, the semiconductive substrate110is a semiconductor heterostructure such as but not limited to a silicon-on-insulator (SOI) substrate, or a multi-layered substrate comprising silicon, silicon germanium, germanium, III-V compound semiconductors, and any combinations thereof.

Active devices are located at the active surface and they refer to components such as but not limited to gates, transistors, rectifiers, and isolation structures that form parts of integrated circuits. In an embodiment, the semiconductive substrate110is semiconductive portion of a processor die such as that made by Intel Corporation of Santa Clara, Calif.

FIG. 2is a detail section2taken fromFIG. 1at the inset2according to an embodiment. The semiconductive substrate110is seen with the semiconductive prominence112. The reaction zone114is heavy outlined for enhanced clarity. Greater detail of the reaction zone114reveals surface-doping structures. A dopant transition zone134is seen adjacent the dopant-lean zone132. And a dopant-rich zone136is seen adjacent the dopant transition zone134.

In an embodiment, the surface-doping structures are largely homogeneous such as can be achieved by sufficient reaction time with surface dopants. In an embodiment, the reaction zone114is substantially homogeneous and it is retained as a near-surface structure such as required due to length and intensity of anneal processing and due to the amount of surface doping material that was presented onto the surface of the prominence112before annealing.

In an embodiment, the reaction zone114is about 2-10 nanometer (nm) thick (when viewed in the X-direction). The reaction zone114may be quantified as having been superficially diffused into the prominence by this 2-10 nm thickness embodiment. These increasingly small dimensions with respect to electrical current absolute limits of semiconductive atomic sizes (e.g., doped silicon) and semiconductive compound sizes (e.g. III-V materials), process embodiments counteract deactivation or depletion of useful semiconductive materials that can form such as native oxides and damage to the surface areas due to dopant activation anneals, etch- and surface cleaning treatments, and also damage from metal deposition processes.

FIG. 1ais a cross-section elevation of the active device depicted inFIG. 1during processing according to an example embodiment. The active device101includes the semiconductive substrate110and the prominence112disposed thereon. The gate structure120is depicted, but it may be a dummy structure that is sacrificial and will be replaced with a replacement gate during subsequent processing, depending upon a give useful processing scheme.

A recess138has been opened in the gate-level ILD layer118such as by a directional etch. The recess138shows a tapered form factor when viewed in X-Z dimensions. In an embodiment, the recess138is opened by an etch process that is selective to leaving the prominence112such as where the prominence is an epitaxial structure that is differently doped compared to doping of the semiconductive substrate110. Consequently, an etch-selective result may be achieved where the etch is selective to leaving the prominence112and the semiconductive substrate110, but it removes the ILD layer118. Care is taken to etch the recess138to expose the prominence112in a centered exposure to facilitate further surface processing thereof. In an embodiment, the recess138is a contact trench138. In an embodiment, the recess138is a contact via138.

FIG. 1bis a cross-section elevation of the active device depicted inFIG. 1aafter further processing according to an example embodiment. The active device102has been processed by forming a surface-doping precursor structure130over the prominence112.

In an embodiment, a surface-doping precursor structure130is formed by a wet chemical treatment such as by contacting a germanium-containing prominence112with a P-type dopant liquid that adheres to the surface of the prominence112.

In an embodiment, the surface-doping precursor structure130is formed by a vapor-phase treatment. For example a vapor-phase treatment is used to form the surface-doping precursor structure130by an atomic-layer deposition (ALD) treatment. In an example embodiment, a vapor-phase treatment is used to form the surface-doping precursor structure130by a chemical vapor deposition (CVD) treatment. In an example embodiment, a vapor-phase treatment is used to form the surface-doping precursor structure130by a plasma-enhanced chemical vapor deposition (PECVD) treatment. In an example embodiment, a vapor-phase treatment is used to form the surface-doping precursor structure130by a physical vapor deposition (PVD) treatment, which may also be referred to as a sputtering treatment. In an example embodiment, a vapor-phase treatment is used to form the surface-doping precursor structure130by growing an in situ epitaxial film that grows into the surface-doping precursor structure130.

In an example embodiment an ion-implantation process is carried out to surface implant the prominence112under low-energy plasma conditions. “Low-energy plasma” means an electrical bias is applied on the semiconductive device to attract ionized dopant atoms that are accelerated and impact the surface of the prominence112such that the dopant atoms are embedded closer to the surface of the prominence112than to the center of the prominence112.

Thermal processing is done to the surface-doping precursor130in order to drive in dopant materials to the near-surface region of the prominence112and to prevent damage to the dopant-rich zone136that may occur such as native oxide formation during processing conditions.

FIG. 1cis a cross-section elevation of the active device depicted inFIG. 1bafter further processing according to an example embodiment. In an embodiment, the dopant-rich zone136(seeFIG. 2) is not formed until after formation of the contact116. Under such processing embodiment conditions, damage to the surface-doping precursor structure130is of sufficiently low amount that formation of the dopant rich zone136by near-surface anneal may be postponed.

In a process embodiment, a flash lamp is used for annealing the prominence112. The flash lamp uses electromagnetic radiation that is comprised of radiation having wavelengths across some portion of the electromagnetic spectrum. In a process embodiment, the electromagnetic radiation used to expose the prominence112with the precursor130includes radiation having wavelengths corresponding to the ultraviolet region of the electromagnetic spectrum (i.e., 10 to 400 nm). Such electromagnetic radiation may further include the visible light spectrum (i.e., 400 to 750 nm) and even into the infrared spectrum (i.e., 750 nm to 100 μm).

In an embodiment, electromagnetic radiation impinges the prominence112in a range from microseconds to hundreds of milliseconds. For example, one flash annealing process uses intense electromagnetic radiation for less than 10 milliseconds at a power level of at least 0.015 J/cm2(Joule per square centimeter).

FIG. 1dis a cross-section elevation of the active device depicted inFIG. 1bafter further processing according to an example embodiment. In an embodiment, the dopant-rich zone136is pre-processed before the formation of the contact. Under such processing embodiment conditions, damage is avoided to the surface-doping precursor structure130(seeFIG. 1b) in order to obtain a useful surface contact. Processing may be done by a flash anneal according to disclosed embodiments or conventional technique.

FIG. 3is a cross-section elevation of an active device300that includes a semiconductive prominence312with a surface-enhanced doping concentration314and in interlayer392according to an example embodiment. A semiconductive substrate310has been processed with a prominence312disposed thereon. In an embodiment, the prominence312is an epitaxial, raised S/D structure. In an embodiment, the prominence312is a raised S/D structure312such as an epitaxial S/D contact area for a transistor.

FIG. 4is a detail section4taken fromFIG. 3at the inset4according to an embodiment. The semiconductive substrate310is seen with the semiconductive prominence312. The reaction zone314is heavy outlined for enhanced clarity. Greater detail of the reaction zone314reveals surface-doping structures of an interlayer392, a possible transition zone390, and a near-surface area contact layer336.

In an embodiment, the reaction zone311is about 2-10 nm thick (when viewed in the X-direction). These increasingly small dimensions with respect to current absolute limits of semiconductive atomic sizes (e.g., doped silicon) and semiconductive compound sizes (e.g. III-V materials), process embodiments counteract deactivation or depletion of useful semiconductive materials that can form such as native oxides and damage to the surface areas due to dopant activation anneals, etch- and surface cleaning treatments, and also damage from metal deposition processes.

A reaction zone314is seen between the prominence312and a contact316that is filled into a recess of an ILD layer318. Part of the reaction zone314includes the interlayer392that acts as an insulator or semiconductor. For example, solid-state doping includes an interlayer392that is derived from the reaction zone314. During processing, part of the interlayer392is consumed in doping the prominence312to form a near-surface area contact layer336, but sufficient doping material remains to provide a useful Schottky barrier height reduction at the prominence312that is provided by the presence of the interlayer392. A transition zone390may be found between the near-surface area contact layer336and the interlayer392.

In an example embodiment, the prominence312is a material such as Si, SiGe or Ge and it is n-type doped with a material such as As. In an example embodiment, the prominence is a III-V InGaAs material and it is n-type doped with a material such as Si, Ge or Tl. The interlayer392is formed on the prominence312to reduce contact resistance for an NMOS device. In an example embodiment, a InAs interlayer392is formed on the prominence312to reduce contact resistance for an NMOS device.

Consequently, the dopant species is selected based upon the composition of the prominence312. In an example embodiment for a Si- or Ge-based prominence312(Si, SiGe, or Ge) during the anneal, a partial breakdown of the interlayer precursor (such as the interlayer392is formed on the prominence312to reduce contact resistance for an As) causes arsenic to diffuse into the prominence312to enhance doping the near-surface area of the prominence, while a portion of the interlayer precursor remains to provide Schottky barrier-height reduction embodiments.

It may now be understood that processing embodiments of wet chemical treatment by a liquid dopant precursor may be practiced to achieve an interlayer392. Such processing embodiments may be identical or similar to processing depicted inFIGS. 1a, 1b, 1c, and 1d. It may now be understood that processing embodiments of vapor-phase chemical treatment by a vapor deposition dopant precursor may be practiced to achieve an interlayer392. It may now be understood that processing embodiments of implantation chemical treatment by ion implanting of dopant precursor may be practiced to achieve an interlayer392.

The ILD layer318may be referred to as a gate-level ILD layer318. Where the prominence312is a raised S/D structure312, a gate structure320is disposed adjacent the prominence312. Details of the gate structure312may include a gate dielectric, gate dielectric spacers, a wordline, and a gate dielectric cap.

Other structures may also be present. Metallization such as a contact interconnect324is disposed in a first interconnect ILD layer322. Other metallization is represented as a trace326in a second interconnect ILD layer328.

FIG. 5is a process and method flow diagram500according to an example embodiment. Processing is summarized in several stages and is not intended to include exhaustive processing details.

At510, the process includes forming a prominence on a semiconductive substrate of a die.

At520the process includes opening a contact recess in an ILD to expose the prominence.

At530, the process includes surface doping the prominence with a dopant. In an embodiment, surface doping is wet-chemically processed. In an embodiment, surface doping is vapor-phase processed. In an embodiment, surface doping is ion-implanting processed. In a non-limiting example embodiment, surface doping is configured to create both an interlayer392and a dopant-rich zone336such that both contact resistance is lowered and a useful Schottky barrier height reduction is achieved.

At540, processing includes treating the surface dopant to diffuse superficially into the prominence. In a non-limiting example embodiment, thermal treatment includes a flash anneal with a processing time that lasts less than one second.

At550, processing includes treating the surface dopant to diffuse superficially into the prominence. It is observed that processing at550may precede contacting the prominence with a contact metallization, depending upon a useful stage during processing where driving in the dopant will protect the surface of the contact from oxidation and other processing exposures.

At560, a method embodiment includes installing the die into a computer system such as the computer system600depicted inFIG. 6.

FIG. 6is a schematic of a computer system according to an embodiment. The computer system600(also referred to as the electronic system600) as depicted can embody a surface-doped contact according to any of the several disclosed embodiments and their equivalents as set forth in this disclosure. An apparatus that includes a surface-doped contact that is assembled to a computer system.

The computer system600may be a Smartphone. The computer system600may be a tablet computer. The computer system600may be a mobile device such as a netbook computer. The computer system600may be a desktop computer. The computer system600may be integral to an automobile. The computer system600may be integral to a television. The computer system600may be integral to a DVD player. The computer system600may be integral to a digital camcorder.

In an embodiment, the electronic system600is a computer system that includes a system bus620to electrically couple the various components of the electronic system600. The system bus620is a single bus or any combination of busses according to various embodiments. The electronic system600includes a voltage source630that provides power to an integrated circuit610. In some embodiments, the voltage source630supplies current to the integrated circuit610through the system bus620.

The integrated circuit610is electrically coupled to the system bus620and includes any circuit, or combination of circuits according to an embodiment. In an embodiment, the integrated circuit610includes a processor612that can be of any type of an apparatus that includes a surface-doped contact embodiment. As used herein, the processor612may mean any type of circuit such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor, or another processor. In an embodiment, SRAM embodiments are found in memory caches of the processor612. Other types of circuits that can be included in the integrated circuit610are a custom circuit or an application-specific integrated circuit (ASIC), such as a communications circuit614for use in non-equivalent wireless devices such as cellular telephones, Smartphones, pagers, portable computers, two-way radios, and other electronic systems. In an embodiment, the processor610includes on-die memory616such as static random-access memory (SRAM). In an embodiment, the processor610includes embedded on-die memory616such as embedded dynamic random-access memory (eDRAM). Disclosed surface-doped contact embodiments and their art-recognized equivalents are integral memory cells in the eDRAM.

In an embodiment, the integrated circuit610is complemented with a subsequent integrated circuit611such as a graphics processor or a radio-frequency integrated circuit or both as set forth in this disclosure. In an embodiment, the integrated circuit is in a first die and the subsequent integrated circuit is in a second die that is packaged with the first die like a system-on-package (SoP). In an embodiment, the integrated circuit is in a first sector of a die and the subsequent integrated circuit is in a second sector of the die such as a logic-graphics system-on-chip (SoC) die like the Intel code-named SandyBridge™ processor die. In an embodiment, the dual integrated circuit611includes embedded on-die memory617such as eDRAM with any disclosed surface-doped contact memory cell embodiments. The dual integrated circuit611includes an RFIC dual processor613and a dual communications circuit615and dual on-die memory617such as SRAM. In an embodiment, the dual communications circuit615is particularly configured for RF processing.

In an embodiment, at least one passive device680is coupled to the subsequent integrated circuit611such that the integrated circuit611and the at least one passive device are part of the any apparatus embodiment that includes a surface-doped contact that includes the integrated circuit610and the integrated circuit611. In an embodiment, the at least one passive device is a sensor such as an accelerometer for a tablet or Smartphone.

In an embodiment, the electronic system600includes an antenna element682such as any surface-doped contact embodiment set forth in this disclosure. By use of the antenna element682, a remote device684such as a television, may be operated remotely through a wireless link by an apparatus embodiment. For example, an application on a smart telephone that operates through a wireless link broadcasts instructions to a television up to about 30 meters distant such as by Bluetooth® technology. In an embodiment, the remote device(s) includes a global positioning system of satellites for which the antenna element(s) are configured as receivers.

In an embodiment, the electronic system600also includes an external memory640that in turn may include one or more memory elements suitable to the particular application, such as a main memory642in the thrill of RAM, one or more hard drives644, and/or one or more drives that handle removable media646, such as diskettes, compact disks (CDs), digital variable disks (DVDs), flash memory drives, and other removable media known in the art. In an embodiment, the external memory640is embedded memory648such an apparatus that includes a surface-doped contact according to any disclosed embodiment.

In an embodiment, the electronic system600also includes a display device650, and an audio output660. In an embodiment, the electronic system600includes an input device such as a controller670that may be a keyboard, mouse, touch pad, keypad, trackball, game controller, microphone, voice-recognition device, or any other input device that inputs information into the electronic system600. In an embodiment, an input device670includes a camera. In an embodiment, an input device670includes a digital sound recorder. In an embodiment, an input device670includes a camera and a digital sound recorder.

A foundation substrate690may be part of the computing system600. The foundation substrate690is a motherboard that supports an apparatus that includes a die with a surface-doped contact embodiment. In an embodiment, the foundation substrate690is a board that supports an apparatus that includes a die with surface-doped contact embodiment. In an embodiment, the foundation substrate690incorporates at least one of the functionalities encompassed within the dashed line690and is a substrate such as the user shell of a wireless communicator.

As shown herein, the integrated circuit610can be implemented in a number of different embodiments, an apparatus that includes a die with a surface-doped contact according to any of the several disclosed embodiments and their equivalents, an electronic system, a computer system, one or more methods of fabricating an integrated circuit, and one or more methods of fabricating and assembling an apparatus that includes a die with a surface-doped contact according to any of the several disclosed embodiments as set forth herein in the various embodiments and their art-recognized equivalents. The elements, materials, geometries, dimensions, and sequence of operations can all be varied to suit particular I/O coupling requirements including dice with surface-doped contact embodiments and their equivalents.

Although a die may refer to a processor chip, a system-on-chip (SoC), an RF chip, an RFIC chip, or a memory chip may be mentioned in the same sentence, but it should not be construed that they are equivalent structures. Reference throughout this disclosure to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. The appearance of the phrases “in one embodiment” or “in an embodiment” in various places throughout this disclosure are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Terms such as “upper” and “lower” “above” and “below” may be understood by reference to the illustrated X-Z coordinates, and terms such as “adjacent” may be understood by reference to X-Y coordinates or to non-Z coordinates.

It will be readily understood to those skilled in the art that various other changes in the details, material, and arrangements of the parts and method stages which have been described and illustrated in order to explain the nature of this invention may be made without departing from the principles and scope of the invention as expressed in the subjoined claims.