Image processor

Image dividing means of an RPU divides raw image data into divided image data A1 having 2048 horizontal pixels and A2 having 1024 horizontal pixels. The divided image data A1 is continuously processed in single pixel processing means and multiple pixel processing means and thereafter transferred to and stored in a buffer. The divided image data A2 is processed in the single pixel processing means and thereafter transferred to and temporarily stored in another buffer. The multiple pixel processing means reads and processes divided image data A2a stored in this buffer and thereafter transfers and stores the same to and in still another buffer. Image combining means reads divided image data A1b and A2b stored in the buffers and combines the same with each other. Thus, an image processing time and a cost can be reduced even if raw image data having horizontal pixels in a number exceeding the capacity of a line memory is received.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an image processor loaded on a digital camera or the like.

2. Description of the Background Art

FIG. 10is a schematic block diagram of a general digital still camera100. In the digital still camera100, an analog image signal picked up with an image pickup sensor105such as a CCD sensor or a CMOS sensor is converted to a digital signal and thereafter subjected to various image processing such as gamma correction, color space conversion, pixel interpolation and edge enhancement in an image processing part106, as shown in FIG.10. Image data subjected to such image processing is finder-displayed on a liquid crystal monitor109, compression-coded in the JPEG (joint photographic experts group) system or the TIFF (tag image file format) and stored in a storage medium (memory card)110formed by a nonvolatile memory or the like, or output to an external device such as a personal computer or a printer through an interface111. Referring toFIG. 10, numeral101denotes an optical lens, numeral102denotes a color correction filter, numeral103denotes an optical LPF (low-pass filter), numeral104denotes a color filter array, and numeral107denotes a driving part driving/controlling the image pickup sensor105.

In general, image processing in the image processing part106is classified into image processing such as gamma correction or color space conversion in units of single pixels and image processing such as pixel interpolation or edge enhancement in units of multiple pixels. In the image processing in units of multiple pixels, processed data of a specific pixel is created from a plurality of pixel data surrounding the specific pixel, and hence pixel data of a plurality of horizontal lines must be stored in line memories (not shown). Therefore, a plurality of line memories each having capacity at least corresponding to the number of horizontal pixels of the image pickup sensor105are prepared in general. However, the pixel size (pixel number) of the image pickup sensor105is not uniform. When the capacity of the line memories is matched with a popular pixel size, therefore, the image processing in units of multiple pixels cannot be executed on an image sensor having a larger pixel size. When the capacity of the line memories built into an image processing circuit integrated into a chip is increased, power consumption as well as the chip size and the manufacturing cost are disadvantageously increased.

FIG. 11is a schematic block diagram for illustrating an image processing method solving the aforementioned problem. Referring toFIG. 11, it is assumed that raw image data input in the image processing part106has 3072 horizontal pixels exceeding the capacity, corresponding to 2048 horizontal pixels, of line memories (not shown) provided in an RPU (real-time processing unit)106A of the image processing part106. The image processing part106comprises the RPU106A image-processing progressive (sequential scanning) type raw image data in real time. The RPU106A is integrated into a chip, and comprises pixel processing means106Aaperforming image processing such as gamma correction, pixel interpolation and color space conversion on the raw image data transferred from a raw image data buffer108a.

First, raw image data picked up with the image pickup sensor105is temporarily transferred to and stored in the raw image data buffer108aprovided on a memory108(ST100). At subsequent steps ST101and ST102, pixel data are read from the raw image data buffer108aas divided image data A1having 2048 horizontal pixels and divided image data A2having 1024 horizontal pixels and transferred to the RPU106A. At the step ST101, the divided image data A1is read from the raw image data buffer108a,transferred to the pixel processing means106Aaand subjected to image processing in units of single pixels and in units of multiple pixels, and thereafter transferred to and stored in a processed data buffer108b.At the subsequent step ST102, the divided image data A2is read from the raw image data buffer108a,transferred to the pixel processing means106Aaand subjected to image processing, and thereafter transferred to and stored in another processed data buffer108c.

At a subsequent step ST103, divided image data A1aand A2astored in the processed data buffers108band108crespectively are transferred to image combining means106B and thereafter combined with each other into image data of one frame.

A CPU106C compression-codes the image data output from the image combining means106B by the JPEG system or the like (ST104), and stores the same in the storage medium (memory card)110(ST105).

In such image processing, however, the RPU106A must store a plurality of lines of the divided image data A1and A2in the line memory when the pixel processing means106Aaperforms the processing in units of multiple pixels, and temporally independently process the divided image data A1and A2. Thus, the raw image data of one frame is temporarily stored in the raw image data buffer108aso that the divided image data A1and A2are thereafter transferred to the RPU106A, and hence the capacity of the memory108is increased to disadvantageously increase the cost as well as the image processing time. Therefore, the processing time required for ending writing of the compression-coded image in the storage medium110after the operator presses a shutter release button is disadvantageously increased, for example.

SUMMARY OF THE INVENTION

According to a first aspect of the present invention, an image processor comprises an image processing circuit image-processing image data input therein and a main memory receiving and temporarily storing the transferred data processed in the image processing circuit and transferred thereto, while the image processing circuit has a temporary storage area temporarily storing pixel data of a plurality of lines of the image data, image dividing means dividing the image data into divided image data storable in the temporary storage area, single pixel processing means executing image processing on the divided image data in units of single pixels and multiple pixel processing means executing image processing in units of multiple pixels after the temporary storage area stores the divided image data processed in the single pixel processing means, and the main memory has a first buffer area storing first divided image data continuously processed in the single pixel processing means and the multiple pixel processing means among the divided image data, a second buffer area storing second divided image data processed in the single pixel processing means among the divided image data and a third buffer area storing data obtained by processing the second divided image data read from the second buffer area in the multiple pixel processing means. The image processor further comprises image combining means combining the first divided image data stored in the first buffer area and the data stored in the third buffer area with each other.

As hereinabove described, the image processor according to the first aspect requires no step of temporarily storing the image data in the main memory and thereafter transferring the same to the aforementioned image processing circuit dissimilarly to the prior art even if the aforementioned temporary storage area such as a line memory has no capacity for horizontal pixel number of the received raw image data, whereby the image processing speed can be improved and the buffer area on the main memory can be saved for reducing the manufacturing cost.

According to a second aspect of the present invention, a CPU (central processing unit) controls data transfer between the main memory and the image processing circuit.

According to the second aspect, the CPU can execute data transfer between the aforementioned main memory and the aforementioned image processing circuit.

According to a third aspect of the present invention, the image processor further comprises a DMA (direct memory access) controller controlling data transfer between the main memory and the image processing circuit.

According to the third aspect, the load on the CPU is reduced and data transfer between the aforementioned main memory and the aforementioned image processing circuit can be executed at a high speed, whereby the image processing speed can be further improved.

According to a fourth aspect of the present invention, the DMA controller has at least two DMA channels, the first DMA channel is assigned to data transfer from the multiple pixel processing means to the first buffer area and the second DMA channel is assigned to data transfer from the single pixel processing means to the second buffer area.

According to the fourth aspect, the first divided image data processed in the aforementioned multiple pixel processing means can be DMA-transferred to the aforementioned first buffer area and the second divided image data processed in the aforementioned single pixel processing means can be DMA-transferred to the aforementioned second buffer area, whereby image processing is so efficiently executed that the image processing speed can be improved.

According to a fifth aspect of the present invention, the DMA controller has at least two DMA channels, the first DMA channel is assigned to data transfer from the second buffer area to the multiple pixel processing means and the second DMA channel is assigned to data transfer from the multiple pixel processing means to the third buffer area.

According to the fifth aspect, the second divided image data stored in the aforementioned second buffer area can be DMA-transferred to the aforementioned multiple pixel processing means while the data processed in the multiple pixel processing means can be DMA-transferred to the aforementioned third buffer area in parallel therewith, whereby image processing is so efficiently executed that the image processing speed can be improved.

According to a sixth aspect of the present invention, an image processor comprises an image processing circuit image-processing raw image data input therein, a main memory receiving and temporarily storing the data processed in the image processing circuit and transferred thereto and a DMA controller controlling data transfer between the main memory and the image processing circuit, while the image processing circuit has a temporary storage area temporarily storing pixel data of a plurality of lines of the raw image data, image dividing means dividing the raw image data into divided image data storable in the temporary storage area, single pixel processing means executing image processing on the divided image data in units of single pixels and multiple pixel processing means executing image processing in units of multiple pixels after the temporary storage area stores the divided image data processed in the single pixel processing means, the main memory has a first buffer area storing first divided image data continuously processed in the single pixel processing means and the multiple pixel processing means among the divided image data and a second buffer area storing second divided image data processed in the single pixel processing means among the divided image data, the first buffer area also stores data obtained by processing the second divided image data read from the second buffer area in the multiple pixel processing means, and the DMA controller makes addressing when transferring the first and second divided image data to the first buffer area thereby combining the same into a single image and storing the single image.

According to the sixth aspect, the image processor requires no step of temporarily storing the raw image data in the main memory and thereafter transferring the same to the aforementioned image processing circuit dissimilarly to the prior art even if the aforementioned temporary storage area such as a line memory has no capacity for horizontal pixel number of the received raw image data similarly to the first aspect, whereby the image processing speed can be improved and the buffer area on the main memory can be saved for reducing the manufacturing cost. Further, the aforementioned divided image data can be combined in DMA transfer, whereby the divided image data can be combined at a high speed for improving the image processing speed.

According to a seventh aspect of the present invention, the DMA controller comprises a DMA channel generating and outputting an address on the main memory and a memory control circuit executing data transfer between a storage element corresponding to the address output from the DMA channel and the image processing circuit, and the DMA channel comprises an address counter generating and outputting the address by sequentially changing the same from a prescribed start address in the first buffer area up to a prescribed end address in the first buffer area, a local counter performing counting in synchronization with sequential change of the address in the address counter and an adder-subtracter outputting an added/subtracted value obtained by adding/subtracting a prescribed offset value to/from the address output from the address counter when a count output from the local counter reaches a prescribed final value to the address counter thereby making the address counter change the address from the added/subtracted value.

According to the seventh aspect, the aforementioned start address, end address, final value and offset value are properly specified when the first divided image data is DMA-transferred from the multiple pixel processing means to the aforementioned first buffer area and the second divided image data is DMA-transferred from the multiple pixel processing means to the aforementioned first buffer area respectively, whereby the first and second divided image data can be combined into a single image and stored in the first buffer area.

Accordingly, an object of the present invention is to provide an image processor capable of reducing an image processing time as well as a cost also when receiving raw image data having horizontal pixels in a number exceeding the capacity of the aforementioned line memory.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Image processing methods according to various embodiments of the present invention are now described.

FIG. 1is a schematic diagram showing the overall structure of a digital still camera1employed in each embodiment of the present invention. This digital still camera1comprises an optical mechanism11having an AF (auto-focus) function, an automatic exposure control function and the like, and a CCD (charge-coupled device) sensor12picks up an image of an object through the optical mechanism11. At this time, a stroboscope (flash)30may emit light of a controlled quantity in synchronization with the pickup timing for applying the same to the object. An analog signal processing circuit13captures the picked-up analog image data of the object and converts the same to a digital image signal (raw image data). An RPU (real-time processing unit)14performs prescribed image processing such as pixel interpolation, color space conversion, gamma correction, edge enhancement and filtering on the raw image data as real-time processing. The image data subjected to such image processing is displayed on an LCD23functioning as a finder, or subjected to compression coding in the JPEG system or the TIFF by a CPU17and thereafter transferred to a card interface27A and stored in a memory card27through a main bus10or transferred to an external interface (I/F)28and output to an external device such as a personal computer.

A main memory26is interconnected with the analog signal processing circuit13, the RPU14, a DMA controller (data transfer controller)24and a JPEG processing part25through the main bus10. The CPU17or the DMA controller24controls data transfer between the analog signal processing circuit13and the main memory26or between the RPU14and the main memory26.

Referring toFIG. 1, numeral15denotes a CCD driving circuit driving the CCD sensor12, numeral16denotes a timing generator regulating operation timings of the RPU14, the CCD driving circuit15and the like, numeral18denotes a PLL oscillation circuit, numeral19denotes an auxiliary arithmetic unit (coprocessor) for the CPU17, numeral20denotes a display module, numeral21denotes a digital encoder, and numeral22denotes an LCD driving circuit driving the LCD23. A clock generator29divides or multiplies a clock signal supplied from the PLL oscillation circuit18, thereby generating a driving clock signal for all modules such as the RPU14, the timing generator16, the CPU17, the digital encoder21and the like.

FIG. 2is a schematic block diagram for illustrating an image processor according to an embodiment 1 of the present invention. As shown inFIG. 2, the image processor according to the embodiment 1 comprises an RPU (image processing circuit)14integrated into a chip, a main memory26and image combining means31. The RPU14carries a plurality of line memories (not shown) each having a capacity for 2048 horizontal pixels.

The RPU14comprises image dividing means14adividing raw image data having 3072 horizontal pixels input in a progressive system into first divided image data A1having 2048 horizontal pixels and second divided image data A2having 1024 horizontal pixels as well as single pixel processing means14band multiple pixel processing means14cimage-processing the divided image data A1and A2output from the image dividing means14ain units of single pixels and in units of multiple pixels respectively.

Examples of the image processing in units of single pixels are gamma correction for correcting gamma characteristics, color space conversion for converting image data expressed in a three-color system (RGB system) or a four-color system (YMCG system or the like) to other color space components when an original signal is a color image signal, and the like. Examples of a color space coordinate system after color space conversion are a YUV coordinate system, a YIQ coordinate system, a YCbCrcoordinate system etc. employed in the NTSC (national television system committee) system or the like. Examples of the image processing in units of multiple pixels are pixel interpolation, edge enhancement and the like. For example, a Bayer image pickup sensor assigns a monochromatic filter to each pixel, and hence raw image data picked up with this image pickup sensor has only a single color component as to each pixel. In pixel interpolation, pixel data of deficient color components must be interpolated from data of peripheral pixels on three to five horizontal lines including that having the pixel. Therefore, the RPU14has a plurality of line memories (not shown) described above.

An image processing method according to the embodiment 1 is now described in detail. At a step ST1, an image signal output from the aforementioned CCD sensor12driven in the progressive system is converted to a digital signal (raw image data) in the analog signal processing circuit13and thereafter directly input in the image dividing means14aof the aforementioned RPU14without being temporarily transferred to the main memory26. The image dividing means14adivides the received raw image data having 3072 horizontal pixels into the first divided image data A1having 2048 horizontal pixels and the second divided image data A2having 1024 horizontal pixels and outputs the same to the single pixel processing means14b.

At a subsequent step ST2, the single pixel processing means14bperforms real-time processing in units of single pixels on the first divided image data A1and thereafter continuously outputs the same to the multiple pixel processing means14c.At a subsequent step ST3, the multiple pixel processing means14cstores received divided image data A1ain the aforementioned line memories for a plurality of lines, executes real-time processing in units of multiple pixels and thereafter outputs the same. At a step ST4, divided image data A1boutput from the multiple pixel processing means14cis transferred to and stored in a first buffer area26aprovided on the main memory26through the main bus10under control of the CPU17. At a step ST5, the single pixel processing means14bperforms image processing in units of single pixels on the divided image data A2received from the image dividing means14aand outputs divided image data A2a, which in turn is transferred to and stored in a second buffer area26bthrough the main bus10under control of the CPU17at a subsequent step ST6.

In actual division, the aforementioned image dividing means14aidentifies the area of the divided image data A1or A2to which received pixel data belongs, and generates an identification signal therefor to the single pixel processing means14b. The single pixel processing means14bswitches the destination of the processed data in response to the identification signal. In other words, the single pixel processing means14boutputs the processed data A1ato the multiple pixel processing means14c(ST3) when the pixel data belongs to the divided image data A1, while outputting the processed data A2ato the second buffer area26bwhen the pixel data belongs to the divided image data A2(ST6).

After the processing at the aforementioned steps ST1to ST6is ended, the multiple pixel processing means14coutputs divided image data A2bobtained by reading the divided image data A2astored in the second buffer area26band executing real-time processing in units of multiple pixels at a step ST7. At a step ST8, the divided image data A2boutput from the multiple pixel processing means14cis transferred to and stored in a third buffer area26cthrough the main bus10under control of the CPU17in parallel with the aforementioned step ST7.

At a subsequent step ST9, the image combining means31reads the divided image data A1bstored in the first buffer area26aand the divided image data A2bstored in the third buffer area26cfor combining these divided image data A1band A2bwith each other and outputting combined image data to the CPU17. The image combining means31may be built into the RPU14as a hardware structure, or provided in the mode of software executed by the CPU17. The CPU17compression-codes the combined image data received from the image combining means31in the JPEG system or the TIFF by software processing (ST10), and transfers and stores the compression-coded data to and in the memory card27through the aforementioned card interface27A (ST11).

Thus, the image processing according to the embodiment 1 requires no step of temporarily storing the raw image data of the progressive system in the main memory26and thereafter transferring the same to the aforementioned RPU14dissimilarly to the aforementioned prior art, whereby the image processing speed can be improved and the buffer areas provided on the main memory26can be saved for reducing the manufacturing cost.

In order to reduce the load on the CPU17and improve the image processing speed, it is preferable to employ the aforementioned DMA controller24for data transfer between the RPU14and the main memory26.FIG. 3is a schematic block diagram for illustrating an image processor according to an embodiment 2 of the present invention employing a DMA controller24. Referring toFIG. 3, blocks denoted by the same reference numerals as those inFIG. 2are assumed to have functions similar to the above, and redundant description is omitted. This also applies to step numbers shown in FIG.3.

FIG. 4is a block diagram schematically showing the structure of the DMA controller24. This DMA controller24comprises an arbiter (arbitration circuit)32, a memory control circuit MC1and two DMA channels CH0and CH1. The arbiter32and the memory control circuit MC1are connected to a main bus10. DMA transfer processing by this DMA controller24is as follows: When receiving a DMA transfer request from an RPU14, the arbiter32outputs an operating signal ACK to the DMA channel CH0(or CH1) thereby assigning the DMA channel CH0(or CH1) to data transfer between the RPU14and a buffer area provided on the main memory26. When the arbiter32simultaneously receives a plurality of DMA transfer requests or the CPU17accesses the main memory26, the arbiter32decides the priority of the DMA transfer requests according to a predetermined rule and outputs the operating signal ACK along this priority. The DMA channel CH0(or CH1) receiving the operating signal ACK sequentially generates an address on the buffer area and outputs the same to the arbiter32.

The arbiter32outputs a control signal allowing the memory control circuit MC1to use the main bus10and the address received from the DMA channel CH0(or CH1). The memory control circuit MC1acquires the main bus10due to the aforementioned control signal and makes control to DMA-transfer data stored in the address on the buffer area to the RPU14or DMA-transfer data from the RPU14to the address on the buffer area.

According to the embodiment 2, the DMA channel CH0is assigned to data transfer from multiple pixel processing means14cto a first buffer area26aat a step ST4D subsequent to a step similar to the aforementioned step ST3described with reference to the embodiment 1, while the DMA channel CH1is assigned to data transfer from single pixel processing means14bto a second buffer area26dat a step ST6D subsequent to a step similar to the aforementioned step ST5. Thus, divided image data A1boutput from the multiple pixel processing means14ccan be DMA-transferred to and stored in the first buffer area26aat the step ST4D, while divided image data A2aoutput from the single pixel processing means14bcan be DMA-transferred to and stored in the second buffer area26bat the step ST6D.

After the processing at the steps ST4D and ST6D is ended, the DMA channel CH0is assigned to data transfer from the second buffer area26bto the multiple pixel processing means14cat a step ST7D while the DMA channel CH1is assigned to data transfer from the multiple pixel processing means14cto a third buffer area26cat a step ST8D. Thus, divided image data A2astored in the second buffer area26bis DMA-transferred to the multiple pixel processing means14cat the step ST7D, while divided image data A2boutput from the multiple pixel processing means14ccan be DMA-transferred to and stored in the third buffer area26cat the step ST8D in parallel therewith.

Thus, the embodiment 2 switches assignment of the DMA channels CH0and CH1at the steps ST4D and ST6D and the steps ST7D and ST8D for executing DMA transfer, whereby the RPU14can efficiently execute image processing for improving the image processing speed.

An embodiment 3 of the present invention is now described.FIG. 5is a schematic block diagram for illustrating an image processor according to the embodiment 3. Referring toFIG. 5, blocks denoted by the same reference numerals as those inFIG. 3are assumed to have functions similar to the above, and redundant description is omitted. This also applies to step numbers shown in FIG.5.

The feature of the embodiment 3 resides in that a circuit structure shown inFIG. 6is employed for each of DMA channels CH0and CH1of a DMA controller24. A DMA channel CHn (n:0or1) shown inFIG. 6comprises a register SREG1storing a transfer start address as in a buffer area of a main memory26and another register ERGE1storing a transfer end address Ae in the buffer area. The transfer start address As and the transfer end address Ae are transferred from a CPU17and stored in each register.

The DMA channel CHn also comprises an address counter AC1generating/outputting an address on the buffer area by starting from the transfer start address As stored in the register SREG1and sequentially incrementing the same up to the transfer end address Ae. The address output from the address counter AC1is output to an arbiter32, which in turn executes DMA transfer processing with the address. In this specification, the term “increment” stands for an operation of changing a quantity in a positive or negative direction.

A comparator CMP1compares the address transmitted from the address counter AC1with the transfer end address Ae stored in the register EREG1for outputting a high-level comparison signal to an inverter40when the addresses match with each other, i.e., when the address reaches the transfer end address Ae, while outputting a low-level comparison signal to the inverter40when the addresses mismatch with each other. The inverter40outputs an inverted signal obtained by level-inverting the comparison signal to a logical AND element41.

The DMA channel CHn further comprises a local counter LC1executing counting synchronous with the operation of incrementing the address in the address counter AC1. A comparator CMP2compares a count transmitted from the local counter LC1with a final value stored in a register LEREG1, for outputting a high-level comparison signal to a selector SEL1and the address counter AC1when the values match with each other, i.e., when the count reaches the final value, while outputting a low-level comparison signal to the selector SEL1and the address counter AC1when the values mismatch with each other. The final value stored in the register LEREG1is transferred from the CPU17.

The selector SEL1is controlled to select and output zero value when the received comparison signal is low while selecting and outputting an offset value stored in a register OREG1when the comparison signal is high. The offset value stored in the register OREG1is transferred from the CPU17. An adder AD1outputs an added value obtained by adding up the value transmitted from the selector SEL1and the address transmitted from the address counter AC1to the address counter AC1, thereby making the address counter AC1generate an address starting from the added value. While the embodiment 3 employs the adder AD1on the assumption that the address is incremented in the positive direction, the aforementioned adder AD1is replaced with a subtracter when the address is incremented in the negative direction.

Operations of the DMA channel CHn are as follows: First, the CPU17transfers and stores the transfer start address As and the transfer end address Ae in a buffer area Bu of the main memory26shown inFIG. 7to and in the registers SREG1and EREG1respectively. The CPU17also transfers the final value stored in the register LEREGI and the offset value stored in the register OREG1. Then, an operating signal ACK is input from the arbiter32through the logical AND element41, which in turn outputs an enable signal EN obtained by ANDing the operating signal ACK with a high-level signal received from the comparator CMP1to the address counter AC1. The address counter AC1receiving the enable signal EN starts incrementing the address from the transfer start address As.

The local counter LC1outputs a count obtained by count operation in synchronization with the incrementing operation of the address counter AC1to the comparator CMP1, which in turn outputs a high-level comparison signal to the selector SEL1when the count reaches the final value stored in the register LEREG1. At this time, the count of the local counter LC1is reset to zero value. At this time, further, the selector SEL1selects the offset value stored in the register OREG1and outputs the same to the adder D1, while the address counter AC1receiving the comparison signal reads the added value output from the adder AD1and sequentially generates and outputs an address starting from this added value (address skipped (offset) by the offset value). As shown inFIG. 7, the address counter AC1generates an address of an area TR1until the count of the local counter LC1reaches the final value, and generates an address of a subsequent area TR1while skipping an offset area OR1corresponding to the offset value when the count reaches the final value. When the address generated in the address counter AC1finally reaches the transfer end address Ae, the inverter40outputs a low-level signal to the logical AND element41for stopping the transmission of the enable signal EN from the logical AND element41to the address counter AC1, so that the address counter AC1stops the incrementing operation.

Image processing employing the DMA controller24having the DMA channel CHn is now described in detail with reference to FIG.5.

As shown inFIG. 5, the DMA channel CH0having the circuit structure shown inFIG. 6is assigned to data transfer from multiple pixel processing means14cto a first buffer area26aat a step ST40subsequent to a step similar to the aforementioned step ST3. To describe in detail, a head address As of the first buffer area26ais transferred to the aforementioned register SREG1, and a final address Ae of the first buffer area26ais transferred to the aforementioned register EREG1. Further, the final value indicating the length (hereinafter referred to as an address length) of an address area corresponding to 2048 horizontal pixels of divided image data A1is transferred to the aforementioned register LEREG1, while the offset value indicating an address length corresponding to 1024 horizontal pixels of divided image data A2is transferred to and stored in the aforementioned register OREG1.

Thus, the address counter AC1repeats operations of sequentially incrementing the address from the head address As of the first buffer area26aalong arrow50as shown in an exemplary diagram of FIG.8and offsetting the address area corresponding to 1024 horizontal pixels when the address reaches the final value of the address area corresponding to 2048 horizontal pixels. Therefore, a first area26aA of the first buffer area26astores divided image data A1bhaving 2048 horizontal pixels.

At a subsequent step ST41, the DMA channel CH1having the circuit structure shown inFIG. 6is assigned to data transfer from the multiple pixel processing means14cto the first buffer area26a. To describe in detail, the transfer start address As obtained by adding the head address As of the first buffer area26aand the address length corresponding to 2048 horizontal pixels is transferred to the aforementioned register SREG1, while the final address Ae of the first buffer area26ais transferred to the aforementioned register EREG1. Further, the final value indicating the address length corresponding to 1024 horizontal pixels of the divided image data A2is transferred to the aforementioned register LEREG1, while the offset value indicating the address length corresponding to 2048 horizontal pixels of the divided image data A1is transferred to and stored in the aforementioned register OREG1.

Thus, the address counter AC1repeats operations of sequentially incrementing the address from the transfer start address As along arrow51as shown in an explanatory diagram of FIG.9and offsetting the address area corresponding to 2048 horizontal pixels when the address reaches the final value of the address area corresponding to 1024 horizontal pixels. Therefore, a second area26aB of the first buffer area26astores divided image data A2bhaving 1024 horizontal pixels.

Thus, the first buffer area26astores combined image data having 3072 horizontal pixels obtained by combining the divided image data A1band A2bwith each other.

At a subsequent step ST42, the CPU17reads the combined image data stored in the first buffer area26aand compression-codes the same in the JPEG system or the like, so that the compression-coded data is transferred to a card interface27A and stored in a memory card27at a subsequent step ST43.

Thus, the image processing according to the embodiment 3 can combine the divided image data A1and A2divided by image dividing means14aand thereafter processed in the single pixel processing mean14band the multiple pixel processing means14cwith each other into a single image when DMA-transferring the same to the first buffer area26a, whereby no image combining means31is required dissimilarly to the embodiments 1 and 2 and the speed of image processing can be further increased.