Apparatus and method for integral bypass diode in solar cells

A solar cell having a multijunction solar cell structure with a bypass diode is disclosed. The bypass diode provides a reverse bias protection for the multijunction solar cell structure. In one embodiment, the multifunction solar cell structure includes a substrate, a bottom cell, a middle cell, a top cell, a bypass diode, a lateral conduction layer, and a shunt. The lateral conduction layer is deposited over the top cell. The bypass diode is deposited over the lateral conduction layer. One side of the shunt is connected to the substrate and another side of the shunt is connected to the lateral conduction layer. In another embodiment, the bypass diode contains an i-layer to enhance the diode performance.

FIELD OF THE INVENTION

The present invention relates to the field of semiconductor devices. More specifically, the present invention relates to the photovoltaic solar cells.

DESCRIPTION OF THE RELATED ART

Photovoltaic cells, also called solar cells, are one of the most important new energy sources that have become available in the past several years. Considerable effort has gone into solar cell development. As a result, solar cells are currently being used in a number of commercial and consumer-oriented applications. While significant progress has been made in this area, the requirement for solar cells to meet the needs of more sophisticated applications has not kept pace with demand. Applications such as satellites used in mobile and telephone communications have dramatically increased the demand for solar cells with improved power and energy conversion characteristics.

In satellite and other space related applications, the size, mass, and cost of a satellite power system are dependent on the power and energy conversion efficiency of the solar cells used. Putting it another way, the size of the payload and the availability of on-board services are proportional to the amount of power provided. Thus, as the payloads become more sophisticated, solar cells, which act as the power conversion devices for the on-board power systems, become increasingly more important.

Solar cells are often used in arrays, an assembly of solar cells connected together in a series. The shape and structure of an array, as well as the number of cells it contains, are determined in part by the desired output voltage and current.

When solar cells in an array are receiving sunlight or are illuminated, each cell will be forward biased. However, if any of the cells are not illuminated, because of shadowing or damage, those shadowed cells may be forced to become reversed biased in order to carry the current generated by the illuminated cells. This reverse biasing can degrade the cells and can ultimately render the cells inoperable. In order to prevent reverse biasing, a diode structure is often implemented.

The purpose of the bypass diode is to draw the current away from the shadowed or damaged cell. The bypass becomes forward biased when the shadowed cell becomes reverse biased. Rather than forcing current through the shadowed cell, the diode draws the current away from the shadowed cell and maintains the connection to the next cell.

A conventional bypass diode is typically connected to the exterior of a solar cell array. A problem associated with this type of bypass diode is that it is difficult to manufacture and also less reliable because the exterior assembly is performed by the array assemblers rather than the cell manufacturer.

Another conventional method for protecting the solar cell is to place a bypass diode between adjacent cells wherein the anode of the bypass diode is connected to one cell and the cathode of the diode is connected to an adjoining cell. However, a problem associated with this technique is that it complicates the manufacturing process and is more difficult to assemble the solar cell array.

A third technique for protecting the solar cell involves forming a recess on the solar cell structure and placing a bypass diode in the recess. Because of the fragility of the cells this technique is difficult to implement in a manufacturing line. In addition, the adjoining cells need to be connected to the diode by the array assembler.

Thus, what is needed is a mechanism and method to enhance the efficiency and performance of bypass diodes in multifunction solar cell structures.

SUMMARY OF THE INVENTION

A solar device having a multifunction solar cell structure with a bypass diode is disclosed. The bypass diode provides a reverse bias protection for the multijunction solar cell structure. In one embodiment, the multifunction solar cell structure includes a substrate, a bottom cell, a middle cell, a top cell, a bypass diode, a lateral conduction layer, and a shunt. The lateral conduction layer is deposited over the top cell. The bypass diode is deposited over the lateral conduction layer. One side of the shunt is connected to the substrate and another side of the shunt is connected to the lateral conduction layer. In another embodiment, the bypass diode contains an i-layer to enhance the diode performance.

Additional features and benefits of the present invention will become apparent from the detailed description, figures and claims set forth below.

DETAILED DESCRIPTION

A method and an apparatus of solar cell with multijunction solar cell structure having a bypass diode with an i-layer are described.

In the following description, for purposes of explanation, numerous specific details are set forth to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that these specific details may not be required to practice the present invention. In other instances, well-known circuits and devices are shown in block diagram form to avoid obscuring the present invention.

It is understood that the present invention may contain transistor circuits that are readily manufacturable using well-known CMOS (“complementary metal-oxide semiconductor) technology, or other semiconductor manufacturing processes. In addition, the present invention may be implemented with other manufacturing processes for making digital devices.

The present invention relates to a multijunction solar cell with at least one integral monolithic bypass diode. The layers comprising the solar cell are particularly chosen for their combination of efficiency and manufacturability. As discussed below, one embodiment consists of a multijunction structure with at least three junctions, with a unique modified buffer structure.

The process of manufacturing the solar cell with an integral monolithic bypass diode is comprised of five distinct steps, which are described below.

FIG. 1is an illustration of an embodiment of the invention, a monolithic solar cell with an integral bypass diode.FIG. 2is a series of schematic drawings of the two possible current paths through the cell.

FIG. 1shows a multijunction solar cell100with a cell of Indium Gallium Phosphorus (InGaP)101and a cell of Gallium Arsenide (GaAs)102over a GaAs buffer103on top of a Germanium (Ge) substrate104. When the solar cell100is illuminated, both a voltage and a current are generated.FIG. 2Arepresents the solar cell as seen inFIG. 4, without the metalization107and lateral conduction layer113described below. If the solar cell is illuminated, there will be no barrier to the current following the cell path201through the layers of the solar cell: the Ge junction104, the GaAs junction102, and the InGaP junction101.

However, when the solar cell100is not receiving sunlight, whether because of shading by a movement of the satellite, or as a result of damage to the cell, then resistance exists along the cell path201. As solar cells exist in an array, current from illuminated cells must pass through shaded cells. If there were no diode, the current would force its way through the cell path201, reversing the bias of such cells and degrading, if not destroying them.

If the cell contains a diode, however, the current can be offered an alternate, parallel path202, and the shaded cells will be preserved. The problem with this concept has been the difficulty in creating a diode that is relatively easy to manufacture and which uses a very low level of voltage to turn on and operate. The invention described herein solves these problems.

If a cell is shaded or otherwise not receiving sunlight, in order for the current to choose the diode path202, the turn on voltage for the diode path202must be less than the breakdown voltage along the cell path201. The breakdown voltage along the cell path will typically be at least five volts, if not more. The Schottky contact111requires a relatively small amount of voltage to “turn on”-600 milivolts. However, to pass through the Ge junction104, the bias of the Ge junction104must be reversed, requiring a large voltage. Reversing the bias of the Ge junction104requires approximately 9.4 volts, so nearly ten volts are needed for the current to follow the diode path202in FIG.2A. Ten volts used to reverse the bias of the Ge junction is ten volts less than otherwise would be available for other applications. The device illustrated byFIG. 4is therefore a functioning bypass diode, but an inefficient one from a power utilization perspective.

To address this inefficiency, in the metalization process in which the Titanium Gold (TiAu) contacts109,110are added to the solar cell, an additional layer of metal107is added as well. In the embodiment shown inFIG. 1, the metal is TiAu, although practitioners in the art will be well aware that other metals can also be used.

The effect of the metal107is to “short” the Ge junction104to the base of the Ge cell104. Because of the short, a minimal voltage is required to pass current between the layer113and the Ge substrate. No longer is a high voltage required to force the current through the Ge junction104. The current flows easily through the “short path”107.FIG. 2Bprovides a schematic representation. If the solar cell is shaded, no longer is the cell forced into reverse bias to pass the current of the array string. There is a much less resistive path, requiring a much lower voltage drop, for the current to pass through the bypass diode203. With the addition of the metalization107, the Ge cell104is shorted. As a result, rather than a reverse biased diode with a 9.4 turn-on voltage, the current instead encounters an ohmic resistance path represented by the resistor204.

The layer is doped to about 7 to 8 times 1017cm3to do two things. First, it reduces the contact resistance of the metal layer107and second, it provides a low resistance path for the lateral conduction layer. Without the lateral conduction layer, the resistance at the resistor204is approximately 20 ohms. 20 ohms represents a significant drain on the current of the solar cell. To reduce this resistance, a lateral conduction layer113is added to the solar cell.FIG. 2Crepresents the current paths in the solar cell as depicted in FIG.1. When the solar cell is shaded, the current will flow to the resistor204. Because of the presence of the lateral conduction layer113, the resistance at the resistor can be as low as 0.4 ohms.

The manufacturing process for the solar cell100comprises five steps.FIG. 3shows a multijunction solar cell100and the component parts: the multijunction structure301and the buffer structure302. In the illustrated embodiment, a top cell comprised of an n-on-p InGaP2101is grown over a cell of n-on-p GaAs102. A third diffused Ge junction104is formed due to diffusion of As during the growth of buffer layers103.

A buffer exists between the upper junctions in the solar cell and the Ge substrate104, because the upper junctions are fabricated of III-V material, and the entire cell is grown on a Ge substrate104. Ge is a group IV element, so it has different lattice parameters than group III-V elements. Lattice matching is generally accepted among those skilled in the art as a way to increase the efficiency of a solar cell, and it follows that lattice mismatching decreases a cell's overall efficiency. To achieve lattice matching, the buffer layer is inserted in the manufacture process; normally it is a thick layer of GaAs grown over the Ge substrate. An InGaP layer lattice matches with a GaAs layer much better than with a Ge layer.

The buffer structure302is comprised of the following: an InGaP Schottky contact303as the top layer of the buffer structure302. This will later form the Schottky diode. The buffer structure302is also comprised of an additional etch stop304. The etch stop304enables the device to be more easily manufactured. Upon “wet etching” the etch stop creates barriers during processing which facilitate formation of the bypass diode. The lateral conduction layer113exists in this buffer layer, to more efficiently guide the current out of the diode, as discussed above.

As shown onFIG. 4, the first step in the manufacturing process is to make a “wet etch” that comes down into the cell100and terminates at the InGaP layer403.

A TiAu contact110is formed upon the InGaP layer403. A TiAu contact109is formed at the top of the cell to make an ohmic contact with the n+-GaAs layer112. The TiAu contact110on the InGaP layer403makes a Schottky contact, which is non-ohmic. In other words, instead of looking like a resistor, such contact403and the TiAu contact110forms a diode.

The second step in the manufacturing process is demonstrated in FIG.5.FIG. 5shows a “mesa etch”501down to the level of the Ge cell104. The primary purpose of this step is to create a true diode106, electrically isolating the junctions105within the solar cell from the diode106. When the entire solar cell is manufactured and the metal contacts are bound and the cell is packaged, the cell105and the diode106will be parallel, yet electrically separate.

The third step is a “shunt etch”502, which provides a “shelf” on which the metal107in the next step will be laid. To make etches in the middle of manufacturing without etch stops among the layers, one would have to use a “minute etch” which would be extremely difficult to use with any degree of precision in this instance. The etch stop304allows the solar cell to be manufactured more efficiently.

The fourth step is the metalization process. The TiAu contacts109,110are added, and the metal layer107is added. In this embodiment the metal comprising the layer is TiAu. Where the TiAu contact110meets the InGaP layer403, a Schottky contact is created.

At the TiAu contact109on top of the cell, the TiAu makes an ohmic contact to n-type GaAs112. That is an ordinary cell conduction for this type of cell to persons skilled in the art. With the TiAu contact110at the InGaP layer403, a Schottky contact is created. However, because the object is to “short out” the Ge cell104, the contact was made to the highly doped n+-GaAs cell113. Layer113is also a lateral conduction layer. Upon making the contact to the GaAs layer113, a resistor is created. The resistance at the resistor204was approximately 20 ohms, as illustrated inFIG. 2A.20 ohms of power dissipation can make the cell too inefficient from a power utilization perspective.

The etch stop at the GaAs buffer contact304alleviates this problem. The GaAs buffer contact113is n+ doped at the same level as the GaAs buffer contact112at the top of the cell. This creates a cell with the same quality of contact between the TiAu contact109and the GaAs contact layer112at the top of the cell as the metal contact107with the GaAs layer113.

Modifying the thicknesses of the various layers in the diode106is another way to decrease resistance in the diode106.

The lateral conduction layer113also alleviates the resistance through the diode106, from 20 ohms to as low as 0.4 ohms. The current path passes through the diode106, and the thickness of the diode would ordinarily cause some resistance, but the lateral conduction layer113helps the current move to the metal more efficiently. In this embodiment, the lateral conduction layer is made of highly doped n+-GaAs. The shunt layer107can also be made to partially or completely surround the contact110, further lowering the series resistance.

The lateral conduction layer113and the metalization107are the two most important means to lessen the amount of voltage needed to “turn on” the diode and bypass the shaded cell. By reducing the series resistance, the amount of localized I2R heating is also reduced. The process is also unique because the amount of processing steps are reduced, as the bypass diode layers are grown internally to the buffer layers of the cell, rather than as additional layers that have to be grown on top of the cell. The current device provides for a low bypass diode turn on, as well as a low series resistance bypass diode. Completion of the bypass diode circuit requires a soldered or welded interconnect made between contacts109and110. This can be done as part of the usual interconnect weld.

The fifth step in the manufacturing process is to apply the anti-reflective coating and include etches where external contacts will be attached.

As can be seen from the foregoing, the process by which the diode is manufactured is integral to the manufacture of the cell, and does not require additional manufacturing steps or additional layers to be grown on the cell.

The following illustrates another embodiment of the present invention in which a bypass diode is epitaxially disposed over a multijunction solar cell with an i-layer.

FIG. 6is a block diagram600illustrating a schematic sectional view showing a multijunction solar cell structure640having a bypass diode620in accordance with one embodiment of the present invention. Diagram600includes a substrate602, a multijunction solar cell structure640, a bypass diode620, a well650, and a shunt630. In one embodiment, the substrate602is a germanium substrate. The multijunction solar cell structure640further includes a top, middle, and bottom subcells. It should be noted that terms solar cells, cells, and subcells will be used interchangeably herein. The multijunction solar cell structure is divided into two portions642-644, wherein portion642includes solar cell(s) for converting solar power to electrical power and portion644contains a bypass diode620.

Referring toFIG. 6, the multijunction solar cell structure640is a multijunction solar cell structure wherein a bottom solar cell604is deposited over the substrate and a middle solar cell606is deposited over the bottom solar cell604. The top solar cell608of the multijunction solar cell structure is deposited over the middle solar cell606. Each solar cell within the multifunction solar cell structure is designed to convert the solar energy within a range of wavelength λ of the solar spectrum. For example, the top solar cell608of the multijunction solar cell structure is designed to convert the high frequency portion of the solar spectrum into electrical energy. The high frequency portion may include ultraviolet, X-rays, and/or Gamma rays of the solar spectrum. In one embodiment, the high frequency portion covers λ in a range of approximately 700 nm to 100 nm. The middle solar cell606is responsible for converting the solar energy in a range of ultraviolet, visible light, and/or portions of infrared of the solar spectrum, which may be approximately between 90 nm to 1000 nm. The bottom solar cell604is responsible for converting the solar energy in a range of infrared, microwaves, and/or radio waves, which may be approximately between 700 nm and/or greater.

It is known to one skilled in the art that the solar spectrum could be divided into more than three regions and each region has an associated solar cell for capturing photons within the respected region. It should be further noted that the underlying concept of the present invention applies to multijunction solar cell structure640containing more or less than three subcells.

Diagram600further includes a lateral conduction layer610and a stop etch layer612. For one embodiment, the lateral conduction layer610is heavily doped so that it has the property of high electrical conductivity. The stop etch layer612, in one aspect, is needed to create a shunt contact pad652during the etching process.

Referring toFIG. 6, the bypass diode620includes an n-type layer626, i-type layer624, and p-type layer622. For example, n-type layer626could be an n-doped gallium arsenic (“GaAs”) layer and a p-type layer622could be a p-doped GaAs layer. In one embodiment, a bypass diode with p-on-n polarity is formed when a p-type compound layer is deposited over an n-type compound layer. In another embodiment, a bypass diode with n-on-p polarity may be formed when an n-type compound layer is deposited over a p-type compound layer. The i-type layer624is also referred to as an intrinsic layer, lightly doped layer, i-layer and/or non-doping layer. It should be noted that terms i-type layer, intrinsic layer, lightly doped layer, i-layer and undoped layer are interchangeable herein. A function of i-layer624is to reduce defect breakdown such as microplasma breakdown. In other words, i-layer624reduces leakage current when the bypass diode620is in reverse bias mode. As discussed above, the bypass diode620preserves the integrity of the solar cell by preventing the solar cell from entering the reverse bias mode.

In one embodiment, the bypass diode620is epitaxially formed over the multijunction solar cell structure640so that the bypass diode620becomes an integral part of the solar cell structure. In other words, the bypass diode620is part of the monolithic solar cell structure. During the manufacturing process; for instance, once an n-type layer626is deposited over the stop etch layer612, an i-type layer624is deposited over the n-type layer626. A bypass diode is completed after a p-type layer622is deposited over the i-type layer624. An advantage of an integral bypass diode620is to allow the bypass diode to be manufactured at the same time the multijunction solar cell structure640is manufactured. The bypass diode620is electrically isolated from the active portion of the solar cell by well650.

Well650, in one embodiment, is created by an etch process, such as a mesa etch. This generates a physical space or gap between the solar cell and the bypass diode620. In other words, well650provides an electrical separation between the active portion of the solar cell and the bypass diode620. Well650also provides a path allowing a shunt630to access the substrate. In one embodiment, once shunt630is deposited, well650may be filled with non-conductive materials, such as antireflective materials. It should be noted that the width of the gap or space created by the well650between the active portion of the solar cell and bypass diode depends on the semiconductor technology.

Shunt630is deposited via well650wherein one side of the shunt630is in contact with the substrate and another side of the shunt630is in contact with the lateral conduction layer610. In one embodiment, one side of the shunt630is also in contact with a portion of the multijunction solar cell structure640, which contains the bypass diode620. In other words, the shunt630, in this embodiment, shorts a portion of the multijunction solar cell structure that is underneath the bypass diode620. In this embodiment, the shunt630is made of metal to enable it to pass electric current from the substrate to the bypass diode620with minimal current loss. An advantage of using shunt630is that it reduces the need for external welding jumpers or shorts, which affect the reliability of the solar cell.

FIG. 7is a logic diagram700illustrating a triple junction solar cell structure and a bypass diode620in accordance with one embodiment of the present invention. The logic diagram700includes a top cell608, a middle cell606, a bottom cell604, a bypass diode620, a resistance block702, and four paths710-716. In one embodiment, the resistance block702includes resistance from the shorted portion of the multijunction solar cell structure that is situated underneath of the bypass diode620and the resistance from the shunt630.

During normal approach (e.g., solar cells604-608are exposed to sunlight, solar light, light, radiation, and/or photons), the solar cells604-608are in forward biased. They converts solar energy to electrical energy and pass electric current between the neighboring solar cells connected in series. It should be noted that the terms sunlight, solar light, light, radiation, and/or photons may be used interchangeable herein. In this embodiment, solar cells are organized in a series. While solar cells604-608are in forward biased, bypass diode620is reverse biased because bypass diode620has an opposite polarity from solar cells. Thus, when bypass diode620is in reverse bias mode, no electric current passes through the bypass diode620.

When electrical current generated from the neighboring solar cells arrives at solar cells604-608via path710, solar cells604-608pass total electrical current, which includes the current converted by solar cells604-608and the current arriving from neighboring solar cells through path710, to path716via path712. Path716may be connected to another solar cell and/or other electrical devices.

However, during the situation in which the solar cells604-608are in reverse bias mode when, for example, solar cells604-608are shadowed, the bypass diode620becomes forward biased. In this situation, bypass diode620becomes active and passes the current from neighboring solar cells via path710to path716through path714. In other words, when the solar cells604-608are in reverse bias mode, the bypass diode620becomes forward biased and uses path714to pass the current from path710to path716.

It is understood that the underlying concept of the present invention is applicable if additional solar cells and bypass diodes were added in the logic diagram700.

FIG. 8is a block diagram800illustrating a detailed schematic sectional view showing a triple junction solar cell structure640having a bypass diode620in accordance with one embodiment of the present invention. Referring toFIG. 8, the block diagram800includes a substrate602, a triple junction solar cell structure640, a bypass diode620, a well650, and a shunt630. The triple junction solar cell structure640further includes a bottom, middle, and top subcells604-608. The block diagram800also includes contact pads802-806, wherein contact pad806is deposited over a lateral conduction layer610and contact pad804is deposited over the bypass diode620.

In one embodiment, the substrate is a p-type germanium (“Ge”) substrate602, which is formed over a metal contact pad802. The bottom cell604contains a p-type Ge base layer810, a n-type Ge emitter layer812, and a n-type GaAs nucleation layer814. The base layer810is deposited over the substrate602. The nucleation layer814is deposited over the base layer810, which in one embodiment can be formed through diffusion from an emitter layer812. After the bottom cell604is deposited, a p-type and n-type tunneling junction layers816, which are also known form a structure sometimes referred to as tunneling diode, are deposited.

The middle cell606further includes a back surface field (“BSF”) layer820, a p-type GaAs base layer822, an n-type GaAs emitter layer824, and an n-type gallium indium phosphide2(“GaInP2”) window layer826. The base layer822is deposited over the BSF layer820once the BSF layer820is deposited over the tunneling junction layers816. The window layer826is subsequently deposited on the emitter layer824after the emitter layer824is deposited on the base layer822. The BSF layer820is used to reduce the recombination loss in the middle cell606. The BSF layer820drives minority carriers from a highly doped region near the back surface to minimize the effect of recombination loss. In other words, a BSF layer820reduces recombination loss at the backside of the solar cell and thereby reduces the recombination at the emitter region.

The window layer826used in the middle cell606also operates to reduce the recombination loss. The window layer826also improves the passivation of the cell surface of the underlying junctions. It should be apparent to one skilled in the art that additional layer(s) may be added or deleted in block diagram800without departing from the scope of the present invention. Before depositing the top cell608, p-type and n-type tunneling junction layers830are deposited over the middle cell606.

The top cell608, according to this embodiment, includes a p-type indium gallium aluminum phosphide2(“InGaAlP2”) BSF layer840, a p-type GaInP2base layer842, an n-type GaInP2emitter layer844, and an n-type aluminum indium phosphide2(“AlInP2”) window layer846. The base layer842is deposited on the BSF layer840once the BSF layer840is deposited over the tunneling junction layers830. The window layer846is subsequently deposited on the emitter layer844after the emitter layer844is deposited on the base layer842.

According to this embodiment, an n-type GaAs cap layer850is employed for enhancing better contact with metal materials. The cap layer850is deposited over the top cell608. The lateral conduction layer610, formed of n-type GaAs, is deposited over the cap layer850. An n-type GaInP2stop etch layer is deposited over the lateral conduction layer610. After the stop etch layer is deposited, the bypass diode is epitaxially deposited.

The bypass diode620includes an n-type GaAs layer860, an i-type GaAs layer862layer, and a p-type GaAs layer864. The n-type layer860is deposited over the stop etch layer612. The i-type layer862is deposited over the n-type layer860. The p-type layer864is deposited over the i-type layer862. After layer864is deposited, a contact pad804is deposited over the bypass diode620. Once the contact pad804is formed, a p-i-n bypass diode with p-on-n polarity is formed over the solar cell. In another embodiment, an n-i-p bypass with n-on-p polarity bypass diode can be also formed over a solar cell structure using similar process described above. It should be apparent to one skilled in the art that the additional layer(s) may be added or deleted in the bypass diode620without departing from the scope of the present invention.

In one embodiment, a metal shunt630is deposited via well650. One side of the shunt630is connected to the substrate602and another side of the shunt630is connected to the lateral conduction layer610and a portion of the triple junction cell644. An anti-reflection coating808may be deposited over certain parts of the solar cell to enhance solar cell performance.

It should be noted that the multijunction solar cell structure could be formed by any combination of group III to V elements listed in the periodic table, wherein the group III includes boron (B), Aluminum (Al), Gallium (Ga), Indium (In), and thallium (Ti). The group IV includes carbon (C), Silicon (Si), Ge, and Tin (Sn). The group V includes nitrogen (N), phosphorus (P), Arsenic (As), antimony (Sb), and bismuth (Bi).

FIGS. 9A-9Eare block diagrams illustrating a process of manufacturing a multijunction solar cell structure640with a bypass diode620and a shunt630in accordance with one embodiment of the present invention.FIG. 9Aillustrates a triple junction solar cell structure900with an integral bypass diode602epitaxially formed on the triple junction solar cell structure900. The triple junction solar cell900includes a bottom, middle, and top cell604-608.

FIG. 9Billustrates that a portion922of bypass diode602has been etched away.FIG. 9Cillustrates that a well932is created through an etching process, such as a mesa etch method.FIG. 9Dillustrates that a second portion942of the bypass diode620is etched away. The stop etch layer612is, in one embodiment, used to control the etching process to remove the portion942of the bypass diode620to create a shunt contact pad652.FIG. 9Eillustrates the next step of formation of the shunt952. It should be apparent to one skilled in the art that additional layers and steps may be added or deleted without departing from the scope of the present invention.

FIG. 10is a flow chart1000illustrating a method of manufacturing a multijunction solar cell structure with a bypass diode in accordance with one embodiment of the present invention. At block1010, the process deposits a germanium substrate. In one embodiment, the germanium substrate is deposited over a contact layer. Once the substrate is formed, the process moves to block1012.

At block1012, the process deposits a solar cell. In one embodiment, the solar cell is a triple junction solar cell, which includes a bottom, middle, and top subcells. Moreover, the bottom subcell may be a germanium solar subcell and the middle subcell may be a GaAs solar subcell. The top subcell may be a GaInP2 solar subcell. It should be noted that it does not depart from the scope of the present invention if the homojunction subcells are replaced with heterojunction subcells. After the solar cell is formed, the process proceeds to block1014.

At block1014, the process deposits a lateral conduction layer over the solar cell. In one embodiment, the lateral conduction layer is a n-doped GaAs layer, which is used as the shunt contact pad. Once the lateral conduction layer is deposited, the process proceeds to block1016.

At block1016, the process deposits a bypass diode over the lateral conduction layer. In one embodiment, after a stop etch layer is deposited on the lateral conduction layer, an n-type GaAs layer is deposited over the stop etch layer. After an i-type GaAs layer is deposited over the n-type layer, a p-type GaAs layer is deposited over the i-type layer. In one embodiment, the concentration of n dopant in the n-type GaAs layer is between 1017to 1018. Like n-type layer, the concentration of p dopant in the p-type GaAs layer is between 1017to 1018. In contrast, the concentration of dopant for i-tape GaAs layer is less than 1016. Once the bypass diode is formed, the process moves to block1018.

At block1018, a well or gap or space is created to provide electrical separation between the bypass diode and the solar cell. Well also allows the shunt to access the substrate. After the creation of well, the process proceeds to block1020.

At block1020, a shunt is deposited along a portion of the multijunction solar cell structure wherein one side of the shunt is connected to the substrate and another side of the shunt is connected to the shunt contact pad.