Dual spacer formation in flash memory

A method and manufacture for memory device fabrication is provided. In one embodiment, at least one oxide-nitride spacer is formed as follows. An oxide layer is deposited over a flash memory device such that the deposited oxide layer is at least 250 Angstroms thick. The flash memory device includes a substrate and dense array of word line gates with gaps between each of the word lines gate in the dense array. Also, the deposited oxide layer is deposited such that it completely gap-fills the gaps between the word line gates of the dense array of word line gates. Next, a nitride layer is depositing over the oxide layer. Then, the nitride layer is etched until the at least a portion of the oxide layer is exposed. Next, the oxide layer is etched until at least a portion of the substrate is exposed.

TECHNICAL FIELD

The invention is related to computer-readable memory, and in particular, but not exclusively, to a method and manufacture for a creating a dual spacer in flash memory in such a way that the spaces between word line gates in a dense array of word line gates in the flash memory are completely gap-filled.

BACKGROUND

Various types of electronic memory have been developed in recent years. Some exemplary memory types are electrically erasable programmable read only memory (EEPROM) and electrically programmable read only memory (EPROM). EEPROM is easily erasable but lacks density in storage capacity, where as EPROM is inexpensive and denser but is not easily erased. “Flash” EEPROM, or Flash memory, combines the advantages of these two memory types. This type of memory is used in many electronic products, from large electronics like cars, industrial control systems, and etc. to small portable electronics such as laptop computers, portable music players, cell phones, and etc.

Flash memory is generally constructed of many memory cells where a single bit is held within each memory cell. Yet a more recent technology known as MirrorBit™ Flash memory doubles the density of conventional Flash memory by storing two physically distinct bits on opposite sides of a memory cell. The reading or writing of a bit occurs independently of the bit on the opposite side of the cell. A memory cell is constructed of bit lines formed in a semiconductor substrate. An oxide-nitride-oxide (ONO) dielectric layer formed over top of the substrate and bit lines. The nitride serves as the charge storage layer between two insulating layers. Word lines are then formed over top of the ONO layer perpendicular to the bit lines. Applying a voltage to the word line, acting as a control gate, along with an applied voltage to the bit line allows for the reading or writing of data from or to that location in the memory cell array. MirrorBit™ Flash memory may be applied to different types of flash memory, including NOR flash and NAND flash.

DETAILED DESCRIPTION

Throughout the specification and claims, the following terms take at least the meanings explicitly associated herein, unless the context dictates otherwise. The meanings identified below do not necessarily limit the terms, but merely provide illustrative examples for the terms. The meaning of “a,” “an,” and “the” includes plural reference, and the meaning of “in” includes “in” and “on.” The phrase “in one embodiment,” as used herein does not necessarily refer to the same embodiment, although it may. Similarly, the phrase “in some embodiments,” as used herein, when used multiple times, does not necessarily refer to the same embodiments, although it may. As used herein, the term “or” is an inclusive “or” operator, and is equivalent to the term “and/or,” unless the context clearly dictates otherwise. The term “based, in part, on”, “based, at least in part, on”, or “based on” is not exclusive and allows for being based on additional factors not described, unless the context clearly dictates otherwise. The term “coupled” means at least either a direct electrical connection between the items connected, or an indirect connection through one or more passive or active intermediary devices. The term “signal” means at least one current, voltage, charge, temperature, data, or other signal.

Briefly stated, the invention is related to a method and manufacture for memory device fabrication. In one embodiment, at least one oxide-nitride spacer is formed as follows. An oxide layer is deposited over a flash memory device such that the deposited oxide layer is at least 250 Angstroms thick. The flash memory device includes a substrate and dense array of word line gates with gaps between each of the word lines gate in the dense array. Also, the deposited oxide layer is deposited such that it completely gap-fills the gaps between the word line gates of the dense array of word line gates. Next, a nitride layer is depositing over the oxide layer. Then, the nitride layer is etched until the at least a portion of the oxide layer is exposed. Next, the oxide layer is etched until at least a portion of the substrate is exposed.

FIG. 1shows a memory environment in which embodiments of the invention may be employed. Not all the components illustrated in the figures may be required to practice the invention, and variations in the arrangement and type of the components may be made without departing from the spirit or scope of the invention. For example, although primarily described in the context of a NAND-based flash-based memory, the fabrication described herein may be employed in manufacturing other types of devices, such as NOR-based flash-based memory. Similarly, although primarily described in the context of SONOS type flash memory in which a nitride trap layer is employed, the fabrication described herein may be employed in manufacturing other types of flash memory devices.

As shown, memory100includes arrayed memory110and memory controller130. Memory controller130is arranged to communicate addressing data and program data over signal path106. For example, signal path106can provide 8, 16, or more I/O lines of data. Memory controller130is also configured to access arrayed memory110over signal path103. For example, memory controller130can read, write, erase, and perform other operations at portions of arrayed memory110via signal path103. In addition, although shown as single lines, signal path103and/or signal path106may be distributed across a plurality of signal lines and/or bus lines.

Arrayed memory110includes memory sectors120(identified individually as sectors1-i) that can be accessed via memory controller130. Memory sectors120can include, for example, 256, 512, 1024, 2048 or more sectors having memory cells that can be individually or collectively accessed. For example, in a NAND-based architecture, the individual memory cells are accessed collectively. In other examples, the number and/or arrangement of memory sectors can be different. In one embodiment, for example, sectors120can be referred to more generally as memory blocks and/or can be configured to have a configuration that is different than a bit line, word line, and/or sector topology.

Memory controller130includes decoder component132, voltage generator component134, and controller component136. In one embodiment, memory controller130may be located on the same chip as arrayed memory110. In another embodiment, memory controller130may be located on a different chip, or portions of memory controller130may be located on another chip or off chip. For example, decoder component132, controller component134, and voltage generator component136can be located on different chips but co-located on the same circuit board. In other examples, other implementations of memory controller130are possible. For example, memory controller130can include a programmable microcontroller.

Decoder component132is arranged to receive memory addresses via addressing signal path106and to select individual sectors, arrays, or cells according to the architecture of arrayed memory110. In an NAND-based architecture, individual memory cells can be accessed collectively but not individually.

Decoder component132includes, for example, multiplexer circuits, amplifier circuits, combinational logic, or the like for selecting sectors, arrays, and/or cells based on any of a variety of addressing schemes. For example, a portion of a memory address (or a grouping of bits) can identify a sector within arrayed memory110and another portion (or another grouping of bits) can identify a core cell array within a particular sector.

Voltage generator component134is arranged to receive one or more supply voltages (not shown) and to provide a variety of reference voltages required for reading, writing, erasing, pre-programming, soft programming, and/or under-erase verifying operations. For example, voltage generator component134can include one or more cascode circuits, amplifier circuits, regulator circuits, and/or switch circuits that can be controlled by controller component136.

Controller component136is arranged to coordinate reading, writing, erasing, and other operations of memory100. In one embodiment, controller component136is arranged to receive and transmit data from an upstream system controller (not shown). Such a system controller can include, for example, a processor and a static random access memory (SRAM) that can be loaded with executable processor instructions for communicating over signal path106. In another embodiment, controller component136as well as other portions of memory controller130may be embedded or otherwise incorporated into a system controller or a portion of a system controller.

Embodiments of controller component136can include a state machine and/or comparator circuits. State machine and comparator circuits can include any of a variety of circuits for invoking any of a myriad of algorithms for performing reading, writing, erasing, or other operations of memory100. State machines and comparator circuits can also include, for example, comparators, amplifier circuits, sense amplifiers, combinational logic, or the like.

In one embodiment, memory100is a flash-based memory including flash-based memory cells, such as flash-based NAND cells, NOR cells, or hybrids of the two.

FIG. 2shows a partial top plan view of separate sections of a memory. Core section201, for example, may be an embodiment of a portion of sector120ofFIG. 1and may include arrayed core memory cells. Peripheral section202, for example, may be an embodiment of memory controller110ofFIG. 1or a portion of memory controller110ofFIG. 1.

Core section201includes core polysilicon lines241, conductive regions242, and a portion of substrate205. Portions of core polysilicon lines241are coupled to the gates of individual memory cells (not shown inFIG. 2) and can be configured as a word line, a source select gate line, and/or a drain select gate line. Portions of conductive regions242can include, for example, p-type and/or n-type doped regions of substrate205for forming source/drain regions and/or conductive lines. For example, conductive regions242can form portions of bit lines and/or other signal lines. Also, in some embodiments, individual conductive regions242extend at least partially underneath individual core polysilicon lines241.

In one embodiment, core section201is arranged in a NOR topology, and individual memory cells can be individually accessed via individual conductive regions242. In another embodiment, core section201is arranged in a NAND topology, and individual memory cells can be accessed though individual conductive regions242collectively but not individually. In other embodiments, hybrid architectures can be employed. For example, core section201can be configured to have a portion that is NAND-based and another portion that is NOR-based. Also, although not shown ifFIG. 2, core section201may include any of a variety of interconnect and/or passivation layers, such as dielectric, conductive, or other layers. For example, conductive regions242can be positioned beneath a dielectric spacer layer.

Peripheral section202includes peripheral polysilicon lines251, conductive regions252, and interconnects253. Portions of peripheral polysilicon lines251are coupled to individual peripheral devices (not shown inFIG. 2).

Portions of conductive regions252can include, for example, p-type and/or n-type doped regions of substrate205for forming conductive features, such as a source, a drain, or other type of well. Interconnects253can include conductive lines that electrically intercouple portions of peripheral section202and/or electrically couple core section201with peripheral section202. For example, interconnects253can include a combination of metal lines and vias. Also, although not shownFIG. 2, peripheral section202may also include any of a variety of other interconnect and/or passivation layers.

FIG. 3illustrates a block diagram of an embodiment of a NAND memory array (310) that may be employed as an embodiment of memory array110ofFIG. 1. Memory array310includes memory cells340. Each memory cell340stores one or more bits of data. Memory array310can be associated with an X-decoder component304(e.g., word line (WL) decoder) and a Y-decoder component316(e.g., bit line (BL) decoder) that can each respectively decode inputs/outputs during various operations (e.g., programming, reading, verifying, erasing) that can be performed on the memory cells340. The X-decoder component304and Y-decoder component316can each receive address bus information from memory controller130ofFIG. 1, and can utilize such information to facilitate accessing or selecting the desired memory cell(s) (e.g., memory location(s)) associated with the command. The memory cells340can be formed in M rows and N columns. A common WL can be attached to the gate of each memory cell340in a row, such as word-lines WL0, WL1, WL2, through WLM. A common BL is attached collectively to cells340, such as bit-lines BL0, BL1, through BLN as depicted in the respective diagrams. Respective voltages can be applied to one or more cells340through the WLs and BLs to facilitate performing operations, such as program, read, erase, and the like.

In some embodiments, the X-decoder component304is a WL encoder that receives a word line voltage that may be a relatively high boosted voltage. In this case, the X-decoder component304may contains transistors with high-voltage gate oxides. Other transistors in NAND memory array310that do not need such high voltages have low voltage gate oxides. The high voltage gate oxides need to be significantly thicker than the low voltage gate oxides due to the higher voltages that may be applied to the gate.

FIG. 4shows a cross-sectional side view of a memory cell in core section401. In one embodiment, core section401is an embodiment of core section201ofFIG. 2.

Memory cell440includes a portion of substrate405, dielectric spacer layer443, channel region444, source/drain regions442aand442b, and layered stack445, including charge trapping component446and a portion of core polysilicon line441. Substrate405may be an embodiment of substrate205ofFIG. 2. Source/drain regions442aand442bmay be an embodiment of one or more conductive regions242ofFIG. 2. Core polysilicon line441may be an embodiment of an individual core polysilicon line241ofFIG. 2.

In operation, core polysilicon line441and source/drain regions442aand442bare configured to provide electrical potential(s) to memory cell440for trapping charge at charge trapping component446. A bit is “programmed” when it is trapping a charge and “unprogrammed” when it is not trapping charge. To trap charge, charge trapping component446employs tunneling layer447, charge trapping layer448, and dielectric layer449. In general, tunneling layer447provides a tunneling barrier, charge trapping layer448is a layer that is configured to store charge, and dielectric layer449electrically isolates charge trapping layer448from core polysilicon line441. In one embodiment, memory cell440is a one bit memory cell that is configured to store up to two logic states. In another embodiment, memory cell440can store more than two logic (or bit) states.

In some embodiments, charge trapping component446is an oxide-nitride-oxide (ONO) layer in which dielectric layer449is an oxide (such as silicon dioxide), charge trapping layer448is a nitride, and tunneling layer447is an oxide (such as silicon dioxide). In one embodiment in which charge trapping layer448is a nitride, charge trapping layer448may be a silicon-rich nitride (SIRN) such as silicon nitride.

Dielectric spacer layer443is an oxide-nitride spacer. During the fabrication of memory device443, dielectric spacer layer443is fabricated in such a way that the spaces between word line gates in the dense array of word line gates in the flash memory are completely gap-filled.

FIG. 5illustrates a flow chart of an embodiment of a process (580) for dual spacer formation.FIGS. 6A-Eshow an embodiment of flash memory device600undergoing an embodiment of process580. At the start block, an embodiment of flash memory device600is shown inFIG. 6A. Flash memory device600includes one or more periphery gates665, substrate605, and dense array660of word line gates641with gaps661between each of the word lines gates641in dense array660. Dense array660is in the core section of memory device600, and the one or more periphery gates665are in the periphery section of memory device600. Each word line gate641is the polysilicon portion of the gate. In some embodiments, an ONO layer is underneath the polysilicon, as discussed above and shown inFIG. 4for some embodiments.

After a start block, the process proceeds to block581, where an oxide layer671is deposited over flash memory device600such that the deposited oxide layer671is at least 250 Angstroms thick. The preferred oxide thickness is between 300 Angstroms and 500 Angstroms, but the invention is not so limited. Further, the preferred oxide thickness varies according to various factors, as discussed in greater detail below. The deposited oxide layer671is deposited such that it completely gap-fills the gaps661between word line gates641of dense array660of word line gates. In some embodiments, the oxide layer is provided by low-pressure chemical vapor deposition under heating by furnace. For example, in some embodiments, high-temperature oxide deposition (HTO) or tetraethyl orthosilicate (TEOS) may be used for the oxide deposition.FIG. 6Bshows memory device600after this step.

Next, the process advances to block582, where nitride layer672is deposited over the oxide layer671. In some embodiments, the nitride deposition is accomplished by lower-pressure chemical vapor deposition under furnace heating.FIG. 6Cshows memory device600after this step. The process then proceeds to block583, where nitride layer672is etched until the at least a portion of the oxide layer671is exposed. In some embodiments, the etching is accomplished by plasma etching.FIG. 6Dshows memory device600after this step. Next, the process moves to block584, where oxide layer671is etched until at least a portion of substrate605is exposed. In some embodiments, the etching is accomplished by plasma etching.FIG. 6Eshows memory device600after this step. At this point, each periphery gate has two oxide-nitride spacers643. The process then advances to a return block, where other processing is resumed.

Spacers643protect the periphery gates665from diffusion during a subsequent dopant implant step to dope the lightly-doped drains (LDDs) of the cells in the periphery. Spacers643offset the implant during the implant phase to provide this protection. The use of nitride in spacers643minimizes the formation of metallic material forming on the sidewall during a subsequent phase of nickel silicide formation on the top of the gate polysilicon.

Because the gaps661between the word line gates661of the dense array660are completely gap-filled, no spacer nitride gets trapped in the core oxide spacer. If spacer nitride became trapped between word lines and/or between the edge word line and the selective gate, it could trap electrons during erase and cause string current reduction. However, process580ensures that no spacer nitride gets trapped in the core oxide spacer. Previously, the inventors used approximately 100 Angstroms of thickness for the oxide layer, which allowed spacer nitride to be trapped. However, accordingly to aspects of the invention, an oxide layer of sufficient thickness to gap-fill the spaces between the dense array are used so that the spacer nitride does not become trapped. The oxide thickness is accordingly a crucial parameter, but the exact optimal thickness may vary accordingly a number of different factors, including process and the design dimensions used for various portions of the memory device, including the distance between adjacent word lines.

A particular thickness for the dual spacer643may be desired in some embodiments, in order to optimally protects the periphery gate from diffusion by providing the proper amount of offset during the LDD implant, and the optimal thickness of dual spacer643may be expressed as a critical dimension (CD) requirement in some embodiments. For example, in some embodiments, the CD requirement for the LDD spacer thickness is 800 Angstrom. Accordingly, for example, in these embodiments, when the oxide layer671is 300 Angstroms thick, the nitride layer672is 500 Angstroms thick.

Modern semiconductor devices are typically created as integrated circuits manufactured on the surface of a substrate of semiconductor material. The processing begins by growing a wafer, which is typically done using the Czochralski process. Various devices are formed on the wafer using a series of steps that include deposition, removal processes (such as etching), patterning, and doping. Few steps or many hundreds of such steps may be used in various designs. The patterning steps may be performed by photolithography or other lithographic methods. For example, the wafer may be coated with a photoresist, which is exposed with a device that exposes light through photomasking, exposing portions of the wafer not blocked by the photomask to light. The exposed regions are removed so that the photoresist remains only in areas that were not exposed to light. This allows a layer to be etched according to the pattern on the photomask. After the devices have been formed on the wafer, various back-end processing and packaging is performed, including properly interconnecting the devices and bringing metal lines to the chip edge for attachment to wires.

A designer creates the device design in accordance with a set of design rules provided by the fabricator, and creates a series of design files based on the design. Various design tools may be used by the designer in creating the design, simulating the design, and checking the design for layout rules violations. When completed, the design files are provided to the fabricator, which are used to generate photomasks for use in the fabricating the device. The design files may be communicated in different ways, including over a network.

Embodiments of memory device400ofFIG. 4can be incorporated into any of a variety of components and/or systems, including for example, a processor and other components or systems of such components.FIG. 7shows one embodiment of system790, which may incorporate memory720, which is an embodiment of memory device400ofFIG. 4. Memory720can be directly or indirectly connected to any one of processor792, input devices793, and/or output devices794. In one embodiment, memory720may be configured such that it is removable from system790. In another embodiment, memory720may be permanently connected to the components or a portion of the components of system790.

In many embodiments, memory720, processor792, input devices793, and/or output devices794of system790are configured in combination to function as part of a larger system. For example, system790may be incorporated into a cell phone, a handheld device, a laptop computer, a personal computer, and/or a server device. In addition or alternatively, system790can perform any of a variety of processing, controller, and/or data storage functions, such as those associated with sensing, imaging, computing, or other functions. Accordingly, system790can be incorporated into any of a wide variety of devices that may employ such functions (e.g., a digital camera, an MP3 player, a GPS unit, and so on).