Nonvolatile memory device with test mechanism

A nonvolatile semiconductor memory device includes a memory cell having a MIS transistor configured to experience an irreversible change in transistor characteristics thereof to store data as the irreversible change, the MIS transistor having a gate node coupled to a word selecting line and a source/drain node coupled to a bit line, and the MIS transistor becoming conductive in response to a first state of the word selecting line and becoming nonconductive in response to a second state of the word selecting line, and a test circuit coupled to the bit line to sense a current running through the MIS transistor, the test circuit configured to indicate error in response to either a detection of presence of the current when the word selecting line is in the second state or a detection of absence of the current when the word selecting line is in the first state.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to a memory device, and particularly relates to a nonvolatile memory device which is capable of retaining stored data in the absence of a power supply voltage.

2. Description of the Related Art

Nonvolatile semiconductor memory devices, which can retain stored data even when power is turned off, include flash EEPROMs employing a floating gate structure, FeRAMs employing a ferroelectric film, MRAMs employing a ferromagnetic film, etc.

In the case of EEPROMs, there is a need to manufacture a transistor having a special structure comprised of a floating gate. In the case of FeRAMs and MRAMs, which achieve nonvolatile storage by use of a ferroelectric material and a ferromagnetic material, respectively, there is a need to form and process a film made of these respective materials. The need for such transistor having a special structure and the need for such film made of a special material are one of the factors that result in an increase in the manufacturing costs.

PCT/JP2003/016143, which was filed on Dec. 17, 2003, the entire contents of which are hereby incorporated by reference, discloses a nonvolatile memory cell (i.e., a basic unit of data storage) comprised of a pair of MIS (metal-insulating film-semiconductor) transistors that have the same structure as ordinary MIS transistors used for conventional transistor functions (e.g., switching function). Namely, these memory cell transistors use neither a special structure such as a floating gate nor a special material such as a ferroelectric material or a ferromagnetic material. These MIS transistors are configured to experience an irreversible hot-carrier effect on purpose for storage of one-bit data.

The hot-carrier effect leaves an irreversible lingering change in the transistor characteristics such as the threshold or on-resistance of the transistors. Changes in the characteristics of the MIS transistors caused by the hot-carrier effect achieve nonvolatile data retention. Which one of the MIS transistors has a stronger lingering change determines whether the stored data is “0” or “1”.

A latch (flip-flop) circuit may be used together with the pair of MIS transistors for the purpose of reading (sensing) the data stored in the pair of MIS transistors. Such latch circuit may also be used to determine data to be stored in the memory-cell MIS transistors. That is, data to be stored as nonvolatile data may be first set in the latch circuit, and, then, the data stored in the latch circuit may subsequently be stored in the pair of MIS transistors. The latch circuit and the memory-cell MIS transistors together constitute a memory cell (memory circuit).

When a nonvolatile memory device having the nonvolatile memory cells as described above is manufactured, there is a need to conduct a test to ensure that the memory cells perform properly as designed. The latch circuit portion of each memory cell may properly be tested by use of a conventional SRAM test. The nonvolatile memory portion (comprised of a pair of memory-cell MIS transistors) of each memory cell, however, cannot be tested by use of a conventional test technique. This is because the operation of the nonvolatile memory portion is founded on an irreversible change of the transistor characteristics. If a test that creates such an irreversible change is actually performed, the memory circuit may no longer be usable.

Accordingly, there is a need for a nonvolatile memory device provided with a test mechanism that can test the operation of the memory cells without undermining the function of the memory cells where the memory cells include MIS transistors that are designed to experience an irreversible change in their characteristics for the purpose of nonvolatile data retention.

SUMMARY OF THE INVENTION

It is a general object of the present invention to provide a nonvolatile semiconductor memory device that substantially obviates one or more problems caused by the limitations and disadvantages of the related art.

It is another and more specific object of the present invention to provide a nonvolatile memory device provided with a test mechanism that can test the operation of the memory cells without undermining the function of the memory cells where the memory cells include MIS transistors that are designed to experience an irreversible change in their characteristics for the purpose of nonvolatile data retention.

To achieve these and other advantages in accordance with the purpose of the invention, the invention provides a nonvolatile semiconductor memory device, which includes bit lines, word selecting lines, a plurality of memory cells arranged in a matrix, one of the memory cells including a MIS transistor configured to experience an irreversible change in transistor characteristics thereof to store data as the irreversible change, the MIS transistor having a gate node thereof coupled to one of the word selecting lines and a source/drain node thereof coupled to one of the bit lines, and the MIS transistor becoming conductive in response to a first state of the one of the word selecting lines and becoming nonconductive in response to a second state of the one of the word selecting lines, and a test circuit coupled to the one of the bit lines to sense a current running through the MIS transistor, the test circuit configured to indicate error in response to either a detection of presence of the current when the one of the word selecting lines is in the second state or a detection of absence of the current when the one of the word selecting lines is in the first state.

According to at least one embodiment of the present invention, the nonvolatile semiconductor memory device as described above is provided with the test circuit, which tests the conductivity of the MIS transistor by detecting a current flowing through the relevant bit line while the conductivity of the MIS transistor is switched between a conductive state and a nonconductive state. With this provision, it is possible to check the presence/absence of a current running through the MIS transistor designed to experience an irreversible change for nonvolatile data retention. Based on this check, a determination can be made as to whether this MIS transistor properly operates as a transistor and also as to whether circuit connections are properly formed by the manufacturing process.

Further, according to another aspect of the present invention, a method of testing a nonvolatile semiconductor memory device, which includes bit lines and a plurality of memory cells arranged in a matrix, one of the memory cells including a MIS transistor configured to experience an irreversible change in transistor characteristics thereof to store data as the irreversible change, the MIS transistor having a source/drain node thereof coupled to one of the bit lines, includes the steps of placing the MIS transistor in a selected one of a conductive state and a nonconductive state, and checking a current flowing through the one of the bit lines to check a current flowing through the MIS transistor.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1is a block diagram showing the configuration of a nonvolatile semiconductor memory device in which a test mechanism of the present invention is incorporated. A semiconductor memory device10shown inFIG. 1includes an input buffer11, an output buffer12, a column decoder13, a write amplifier14, a sense amplifier & column selector15, a mode selector16, a row decoder17, a row signal driver18, and a memory-cell array19.

The memory cell array19includes a plurality of memory cells arranged in a matrix form, each memory cell having a circuit configuration as will later be described. The memory cells arranged in the same column are connected to the same bit lines, and the memory cells arranged in the same row are connected to the same word line.

The mode selector16receives mode input signals from an exterior of the device, and decodes the mode input signal to determine an operation mode (e.g., a write operation mode, a read operation mode, or a test operation mode). Control signals responsive to the determined operation mode are supplied to the write amplifier14, the sense amplifier & column selector15, the row signal driver18, etc., for control of the individual parts of the semiconductor memory device10.

The column decoder13receives a column address input from the exterior of the device, and decodes the column address input to determine a selected column. The decode signals indicative of the selected column are supplied to the write amplifier14and the sense amplifier & column selector15.

The row decoder17receives a row address input from the exterior of the device, and decodes the row address input to determine a selected row. The decode signals indicative of the selected row are supplied to the row signal driver18.

In response to the control signals from the mode selector16and the decode signals from the row decoder17, the row signal driver18activates a selected word line among the word lines extending from the row signal driver18. As a result of the activation of the selected word line, a volatile memory unit of each memory cell corresponding to the selected word line is coupled to a corresponding bit line pair among a plurality of bit line pairs. Through this coupling, the writing/reading of data to/from the volatile memory portion of each memory cell is performed.

In response to the control signals from the mode selector16and the decode signals from the column decoder13, the sense amplifier & column selector15couples the bit lines corresponding to the selected column to a data bus. Through this coupling, data is transferred between the memory cell array19and the data bus. The sense amplifier & column selector15amplifies the data read from the memory cell array19for provision to the output buffer12. The data is output from the output buffer12to the exterior of the device as output data. Input data supplied to the input buffer11is provided to the write amplifier14. The write amplifier14amplifies the input data to be written to the memory cell array19.

FIG. 2is an illustrative drawing showing the configuration of a memory cell of the nonvolatile memory device shown inFIG. 1.

The memory cell includes NMOS transistors21and22, a PMOS transistor23, NMOS transistors24through26, PMOS transistors27and28, and NMOS transistors29and30. The NMOS transistors24and26and PMOS transistors27and28together constitute a volatile memory unit (latch circuit)31. The NMOS transistors21and22constitute a nonvolatile memory unit32.

The NMOS transistors21and22serving as nonvolatile memory cell transistors have the same structure as the other NMOS transistors including the NMOS transistors24through26used in the volatile memory unit and the NMOS transistors29and30used as a transfer gate between the memory cell and the bit lines.

As shown inFIG. 2, bit lines BL1and /BL1extend from the write amplifier14and the sense amplifier & column selector15, and are coupled to the volatile memory unit31via the NMOS transistors29and30serving as a data transfer unit. A word selecting line WLW extends from the row signal driver18, and is coupled to the gate nodes of the NMOS transistors21and22serving as the nonvolatile memory unit30. A word line WL extends from the row signal driver18to be connected to the gates of the NMOS transistors29and30. Further, a restore line RESTORE, plate line (controlled-power line) PL, and equalize line EQ also extend from the row signal driver18.

It should be noted that the configuration shown inFIG. 2is identical with respect to each and every one of the memory cells provided in the memory cell array19. Namely, multiple sets of the lines RESTORE, PL, WLW, EQ, and WL are provided in one-to-one correspondence to the rows of the memory cell array19.

FIG. 3is a drawing showing the multiple sets of the lines extending from the row signal driver18and their relations with the mode selector16and the row decoder17. In this configuration, store operation (storing data from the volatile memory unit31to the nonvolatile memory unit32) and restore operation (reading data from the nonvolatile memory unit32to the volatile memory unit31) are performed with respect to the entirety of the memory cell array19, rather than performed on a row-address-specific basis. Read/write operations of the volatile memory unit31with respect to the bit lines BL1and /BL1are of course performed on a row-address-specific basis.

As shown inFIG. 3, the mode selector16supplies signals RESTORE, WLW, EQ, WL, and PL to the row signal driver18. The signals RESTORE, WLW, EQ, and PL are coupled to the corresponding lines of each row without any logic operation, and are thus output from the row signal driver18to the memory cell array19as RESTORE1, WLW1, EQ1, and PL1for a row address RA1and RESTOREn, WLWn, EQn, and PLn for a row address RAn, for example. Inverters41and42are used as output buffers for RESTORE, WLW, and EQ. Voltage converters46are used for PL. The voltage converters46serve to covert the voltage of the signal PL to the voltage of the signal PLx (x=1, . . . , n).

The signal WL supplied from the mode selector16and each row address signal (RA1, . . . , RAn) supplied from the row decoder17are combined by a corresponding NAND gate43, an output of which is inverted by the inverter42for provision to the memory cell array19. Thus, only one of the signals WL1through WLn is activated and supplied to the memory cell array19so as to activate a selected row address.

In this configuration, as described above, the store operation and restore operation are performed with respect to the entirety of the memory cell array19. Alternatively, the store operation and restore operation may be performed separately for each row address. In such a case, the signals RESTORE, WLW, EQ, and PL supplied from the mode selector16are combined with each row address signal in the row signal driver18such as to achieve a proper row-address-specific store operation and restore operation.

FIG. 4is a drawing showing the flow of control signals output from the mode selector16. As shown inFIG. 4, the mode selector16receives and decodes the mode input signals, and supplies various control signals to the row signal driver18and the write amplifier14. Specifically, the control signals RESTORE, WLW, EQ, WL, and PL are supplied to the row signal driver18, and a write enable signal WE is supplied to the write amplifier14.

Further, a test enable signal TE and a precharge signal PRC are supplied from the mode selector16to a cell test circuitry, which is provided together with the sense amplifier & column selector15. The mode selector16controls the test enable signal TE and the precharge signal PRC so as to cause the cell test circuitry to perform a test operation when the mode input signals indicate a test operation mode.

Turning toFIG. 2again, the store operation of the nonvolatile memory device10will be briefly described. When the mode input from the exterior of the device indicates a store operation, the control signals PL, RESTORE, WLW, EQ, WL, and WE are set to 1, 1, 1, 0, 0, and 0, respectively. In response to PL being 1, the plate line PL is set to Vpp (=3.3 V), and in response to WLW being 1, the word selecting line WLW is set to Vpp/2.

The potentials of the node C and the node /C are inverse to each other, and the data stored in the latch circuit (NMOS transistors25and26and PMOS transistors27and28) determines which one of the nodes C and /C is HIGH.

For the sake of convenience of explanation, it is assumed that the node /C is HIGH (Vdd=1.8 V), and the node C is LOW (GND: ground). In this case, only the NMOS transistor21experiences a rise in the threshold voltage due to a hot-carrier effect. The NMOS transistor22does not experience a change in the threshold voltage. This achieves the storing of the data of the volatile memory unit31in the nonvolatile memory unit32.

During the store operation as described above, the high potential (3.3 V) is never applied to the latch circuit. This is because the NMOS transistors21and22serve as intervening circuit elements between the plate line PL (Vpp=3.3 V) and the nodes C and /C. Since the word selecting line WLW is set to Vpp/2, and the nodes C and /C are serving as source nodes, the potentials at the nodes C and /C cannot exceed Vpp/2 minus the threshold voltage. In this configuration, therefore, a hot-carrier effect does not happen in the transistors used in the latch circuit (volatile memory unit31).

In the following, the restore operation of the nonvolatile memory device10will be briefly described. When the mode input from the exterior of the device indicates a restore operation, the control signals PL, RESTORE, WLW, EQ, WL, and WE are set to 0, 0-0-1, 0-1-0, 0-1-1, 0, and 0, respectively. Here, 0-1-0, for example, indicates that the signal level is set to 0 at the first phase, 1 at the second phase, and 0 at the third phase.

At the first phase, the signal RESTORE is set to 0, and the signal EQ is set to 0. As a result, the NMOS transistor24inFIG. 2becomes nonconductive to deactivate the volatile memory unit31, and the PMOS transistor23inFIG. 2becomes conductive to equalize the nodes C and /C.

At the second phase, the signal EQ is set to 1, and the word selecting line WLW is set to 1. As a result, the PMOS transistor23is turned off to separate the nodes C and /C from each other, and the NMOS transistors21and22are turned on. Assuming that the store operation as described above has been performed prior to the restore operation, the NMOS transistor21has a higher threshold voltage, and thus has a higher ON resistance. Accordingly, the force that pulls down the node C is weaker than the force that pulls down the node /C, resulting in the nodes C and /C changing to HIGH and LOW, respectively.

At the third phase, the signal RESTORE is set to 1, and the word selecting line WLW is set to 0. As a result, the NMOS transistor24becomes conductive to activate the volatile memory unit31, and the NMOS transistors21and22are turned off. The activated volatile memory unit31amplifies a potential difference appearing between the node C and the node /C, thereby sensing (detecting) the data stored in the nonvolatile memory unit32.

In the configuration described above, a drain node and a source node of the NMOS transistors21and22used to apply a bias for generating the hot-carrier effect are swapped and used as a source node and a drain node, respectively, at the time of reading the data. With the swapping of the source and drain nodes at the time of data read operation relative to the time of data write operation, a change in the transistor characteristics caused by the hot-carrier effect is efficiently used as a means to store data.

It should be noted, however, that the storing and reading (restoring) of data can be performed without such swapping of source and drain nodes, as described in PCT/JP2003/016143, for example. The swapping of drain and source nodes merely serves to utilize asymmetry of a hot-carrier effect. Namely, when the source node and drain node used to apply a bias for generating a hot-carrier effect are swapped and used as a drain node and a source node, respectively, at the time of detecting a drain current, the detected drain current exhibits a larger drop caused by the hot-carrier effect than would be observed when no swapping was performed.

In the following, a first embodiment of a test mechanism provided in the semiconductor memory device10will be described.FIG. 5is an illustrative drawing for explaining a test operation performed in the semiconductor memory device10.

As shown inFIG. 5, in the test operation mode, a current IBLflowing through the NMOS transistor21is detected by the cell test circuitry which is provided together with the write amplifier & sense amplifier & column selector14,15. Please note that, inFIG. 5, the write amplifier14and the sense amplifier & column selector15(and the cell test circuitry) are put together and illustrated as a single unit. It should also be noted that, when the NMOS transistor21is to be tested, the word line WL is activated to turn on the NMOS transistor29.

The current IBLis supposed to flow in sufficient amount when the NMOS transistor21is tuned on and thus conductive. The current IBLis supposed not to flow when the NMOS transistor21is tuned off and thus nonconductive. In this manner, the test operation mode of the present invention detects the presence/absence of a current running through a MIS transistor designed to experience a hot-carrier effect for nonvolatile data retention. Based on this detection, a check can be made as to whether this MIS transistor properly operates as a transistor and also as to whether circuit connections are properly formed by the manufacturing process.

The test operation as described above is performed with respect to each of the MIS transistors21and22of all the memory cells. The write amplifier & sense amplifier & column selector14,15, the cell test circuitry, and the row signal driver18are controlled by the mode selector16to perform such test operation.

FIG. 6is a drawing showing an example of the configuration of the write amplifier & sense amplifier & column selector14,15provided together with the cell test circuitry. As shown inFIG. 6, the write amplifier & sense amplifier & column selector14,15include a column selector51, a sense amplifier52, and a write buffer55, together with which a cell test circuitry56is provided. The cell test circuitry56includes a current sensing circuit53and a current sensing circuit54. The column selector51includes NAND gates61, inverters62, and NMOS transistors63.

The NAND gates61of the column selector51receive column address signals Y0, /Y0, Y1, and /Y1, and output decode results, thereby asserting (turning to LOW) only one of the NAND gate outputs corresponding to the selected column address. When one of the NAND gate outputs is asserted, the NMOS transistors63corresponding to the asserted output are turned on to become conductive, thereby coupling a corresponding pair of bit lines to the sense amplifier52, the current sensing circuit53, the current sensing circuit54, and the write buffer55.

The sense amplifier52is provided for the purpose of reading (sensing) the data appearing on the coupled bit lines. The write buffer55is provided for the purpose of writing (transmitting) write data to the coupled bit lines. The current sensing circuits53and54are provided for the purpose of detecting the current IBLas previously described.

With the configuration as described above, it is possible to suppress an increase in the circuit size caused by providing the current sensing circuits for the test purpose according to the present invention. In the configuration shown inFIG. 6, one of the four bit line pairs is selected and coupled to the current sensing circuits. This is only a non-limiting example, and the number of bit line pairs selected by the column selector51can be any number.

FIG. 7is a circuit diagram showing an example of the configuration of a current sensing circuit. Each of the current sensing circuits53and54shown inFIG. 6may have the same circuit configuration shown inFIG. 7.

The current sensing circuit ofFIG. 7includes NMOS transistors71and72, PMOS transistors73and74, and an inverter75. The PMOS transistors73and74have the same channel width and same channel length, and have the gate nodes thereof coupled to each other, thereby forming a current mirror circuit. A reference current Irefruns through the PMOS transistor73and the NMOS transistor71, and the current IBLruns through the PMOS transistor74and the NMOS transistor72. The current IBLis supplied to the NMOS transistor21, for example, via the NMOS transistor29as shown inFIG. 5.

The NMOS transistors71and72have the gate node thereof to which the test enable signal TE is applied. When the test enable signal TE is set to HIGH, the NMOS transistors71and72are turned on to become conductive.

The NMOS transistors71and72are configured such that the channel width of the NMOS transistor71is much narrower than the channel width of the NMOS transistor72, or the channel length of the NMOS transistor71is much longer than the channel length of the NMOS transistor72. This makes it possible to set Irefto a threshold current amount that discriminates the presence/absence of the current IBL. It should be noted that the channel width of the NMOS transistor72is preferably set wider than the channel width of the NMOS transistor21.

If the current IBLis larger than the reference current Iref, the input node of the inverter75is set to a low potential, resulting in the output TR1of the inverter75being HIGH. If the current IBLis smaller than the reference current Iref, the input node of the inverter75is set to a high potential, resulting in the output TR1of the inverter75being LOW. In this manner, the current sensing circuit detects (senses) the current IBLflowing through an NMOS transistor serving as a nonvolatile memory cell transistor (i.e., the NMOS transistor21shown inFIG. 5). The output TR1of the inverter75serves as a test result signal for the corresponding NMOS transistor21. In the following, a test result signal for the NMOS transistor paired with the NMOS transistor21(i.e., the NMOS transistor22shown inFIG. 5) is designated as /TR1. Further, test result signals for n NMOS transistors are designated as TR1, TR2, TR3, . . . , and TRn, and test result signals for the NMOS transistors paired with these n NMOS transistors are designated as /TR1, /TR2, /TR3, . . . , and /TRn.

FIG. 8is a circuit diagram showing part of the cell test circuitry56. The part of the cell test circuitry56shown inFIG. 8includes an inverter81, an NMOS transistor82, NMOS transistors83-1through83-2n, a PMOS transistor84, and PMOS transistors85-1through85-2n. Here, n is the number of memory cells (memory circuits) that are simultaneously tested by the cell test circuitry56. Since each memory cell has two NMOS transistors21and22(seeFIG. 5), there are 2n test result signals TR1, /TR1, TR2, /TR2, . . . , TRn, and /TRn. These test result signals TR1, /TR1, TR2, /TR2, . . . , TRn, and /TRn are applied to the gates of the NMOS transistors83-1through83-2n, respectively, and are also applied to the gates of the PMOS transistors85-1through85-2n, respectively.

The precharge signal PRC is supplied from the mode selector16. When the precharge signal PRC becomes HIGH, the NMOS transistor82and the PMOS transistor84become conductive. The conductance of the NMOS transistor82and the PMOS transistor84is set much smaller than the conductance of the NMOS transistors83-1through83-2nand the PMOS transistors85-1through85-2n.

If at least one of the test result signals TR1, /TR1, TR2, /TR2, . . . , TRn, and /TRn is HIGH, TON is set to LOW (Gnd). Only when all the test result signals TR1, /TR1, TR2, /TR2, . . . , TRn, and /TRn are LOW, TON is set to HIGH (Vdd). If at least one of the test result signals TR1, /TR1, TR2, /TR2, . . . , TRn, and /TRn is LOW, TOFF is set to HIGH (Vdd). Only when all the test result signals TR1, /TR1, TR2, /TR2, . . . , TRn, and /TRn are HIGH, TON is set to LOW (Vdd).

Accordingly, both TON and TOFF become LOW if all the NMOS transistors tested for their operation properly allow respective currents to flow through (i.e., if TR1, /TR1, TR2, /TR2, . . . , TRn, and /TRn are all HIGH). Both TON and TOFF become HIGH if all the NMOS transistors tested for their operation properly prevent respective currents from flowing through (i.e., if TR1, /TR1, TR2, /TR2, . . . , TRn, and /TRn are all LOW).

FIG. 9is a circuit diagram showing another part of the cell test circuitry56. The part of the cell test circuitry56shown inFIG. 9includes a NAND gate91, a NAND gate92, a NOR gate93, and an exclusive-OR gate94. When the NMOS transistors to be tested are to be tested for their proper conductive state (i.e., currents properly flow through these NMOS transistors), the word selecting line WLW is set to HIGH (seeFIG. 5).

When the test enable signal TE is HIGH and the word selecting line WLW is also HIGH, the NAND gate91produces a LOW output. This LOW output causes the output of the NAND gate92to be fixed to HIGH. Only if both TON and TOFF are set to LOW, indicating that all the NMOS transistors properly allow respective currents to flow through, does the NOR gate93produce a HIGH output, resulting in the output of the exclusive-OR gate94being LOW. Otherwise, the output of the exclusive-OR gate94is set to HIGH.

When the test enable signal TE is HIGH and the word selecting line WLW is LOW, the NAND gate91produces a HIGH output. This HIGH output causes the output of the NOR gate93to be fixed to LOW. Only if both TON and TOFF are set to HIGH, indicating that all the NMOS transistors properly prevent respective currents from flowing through, does the NAND gate92produce a LOW output, resulting in the output of the exclusive-OR gate94being LOW. Otherwise, the output of the exclusive-OR gate94is set to HIGH.

Accordingly, the output of the exclusive-OR gate94serves as a fail signal FAIL, which becomes LOW if the test results indicate no error, and becomes HIGH if any one of the test results indicates an error.

FIG. 10is a signal waveform chart showing signal waveforms that are used when test operations are performed. As shown inFIG. 10, the word selecting line WLW is first set to LOW to check whether all the NMOS transistors to be tested are properly placed in a nonconductive state. The precharge signal PRC and the test enable signal TE are then set to HIGH to check the test results, resulting in TON and TOFF being both HIGH. The fact that both TON and TOFF are HIGH in this case indicates that none of the NMOS transistors exhibits an error. The fail signal FAIL is LOW in this case.

The word selecting line WLW is then set to HIGH to check whether all the NMOS transistors to be tested are properly placed in a conductive state. The precharge signal PRC and the test enable signal TE are then set to HIGH to check the test results, resulting in TON and TOFF being both LOW. The fact that both TON and TOFF are LOW in this case indicates that none of the NMOS transistors exhibits an error. The fail signal FAIL is LOW in this case.

FIG. 11is a table chart showing logic values of some of the relevant signals for test operation. As shown inFIG. 11, when WLW is 0, the fact that TRn (TR1, /TR1, TR2, /TR2, . . . , TRn, and /TRn) are all zero indicates there is no error. If any one of TRn is 1, the fail signal FAIL becomes 1, indicating the presence of an error.

When WLW is 1, on the other hand, the fact that TRn (TR1, /TR1, TR2, /TR2, . . . , TRn, and /TRn) are all “1” indicates there is no error. If any one of TRn is zero, the fail signal FAIL becomes 1, indicating the presence of an error.

In the following, a second embodiment of a test mechanism provided in the semiconductor memory device10will be described.FIG. 12is an illustrative drawing for explaining test operations performed in the semiconductor memory device10.

In the memory cell configuration as shown inFIG. 5, the PMOS transistor23is used for the purpose of equalizing the nodes C and /C. In this configuration, however, the PMOS transistor23cannot be tested with respect to its conductive state and nonconductive state. That is, the PMOS transistor23cannot be tested to see whether the PMOS transistor23properly becomes conductive or nonconductive.

In the memory cell configuration shown inFIG. 12, PMOS transistors33and34are provided in place of the PMOS transistor23shown inFIG. 5. Instead of using the PMOS transistor23to equalize the nodes C and /C, the PMOS transistors33and34are used to set the nodes C and /C to a predetermined potential. Namely, when the equalize line EQ is set to LOW, the PMOS transistors33and34become conductive so as to set the nodes C and /C to the power supply voltage Vdd.

In this configuration, the PMOS transistor33can be tested by checking a current IBL−P that passes through the PMOS transistor33and the NMOS transistor29. It should be noted that the PMOS transistor34can be tested similarly.

The NMOS transistor21can be tested in the same manner as in the first embodiment shown inFIG. 5. Namely, in the test operation mode of the second embodiment, a current IBL−N flowing through the NMOS transistor21is detected by the cell test circuitry provided together with the write amplifier & sense amplifier & column selector14,15.

The current IBL−N flows out of the cell test circuitry provided together with the write amplifier & sense amplifier & column selector14,15. The current IBL−P, on the other hand, flows into the cell test circuitry, so that different current sensing mechanisms may be required separately for the sensing of the current IBL−N and for the sensing of the current IBL−N.

The current IBL−N is supposed to flow in sufficient amount when the NMOS transistor21is tuned on and thus conductive, and is supposed not to flow when the NMOS transistor21is tuned off and thus nonconductive. Further, the current IBL−P is supposed to flow in sufficient amount when the PMOS transistor33is tuned on and thus conductive, and is supposed not to flow when the PMOS transistor33is tuned off and thus nonconductive. It should be noted that, when the NMOS transistor21or PMOS transistor33is to be tested, the word line WL is activated to turn on the NMOS transistor29.

In this manner, the test operation mode of the second embodiment detects the presence/absence of a current running through a transistor to be tested. Based on this detection, a check can be made as to whether this transistor properly operates as a transistor and also as to whether circuit connections are properly formed by the manufacturing process.

The test operation as described above is performed with respect to each of the MIS transistors21,22,33, and34of all the memory cells. The write amplifier & sense amplifier & column selector14,15, the cell test circuitry56, and the row signal driver18are controlled by the mode selector16to perform such test operation.

The configuration of the write amplifier & sense amplifier & column selector14,15and the cell test circuitry56may be the same as those used in the first embodiment. Namely, as shown inFIG. 6, the write amplifier & sense amplifier & column selector14,15include the column selector51, the sense amplifier52, the write buffer55, together with which the cell test circuitry56is provided. The cell test circuitry56includes the current sensing circuit53and the current sensing circuit54. The operations of these circuits are basically the same as were previously described in connection withFIG. 6.

FIG. 13is a circuit diagram showing an example of the configuration of a current sensing circuit according to the second embodiment. In this embodiment, each of the current sensing circuits53and54shown inFIG. 6may have the same circuit configuration shown inFIG. 13.

The current sensing circuit ofFIG. 13includes the NMOS transistors71and72, the PMOS transistors73and74, the inverter75, an inverter100, PMOS transistors101and102, NMOS transistors103and104, and inverters105and106. The same elements as those ofFIG. 7are referred to by the same numerals, and a description thereof may be omitted when unnecessary.

The PMOS transistors73and74have the same channel width and same channel length, and have the gate nodes thereof coupled to each other, thereby forming a current mirror circuit. A reference current Iref−N runs through the PMOS transistor73and the NMOS transistor71, and the current IBL−N runs through the PMOS transistor74and the NMOS transistor72. The current IBL−N is supplied to the NMOS transistor21, for example, via the NMOS transistor29as shown inFIG. 12.

The NMOS transistors103and104have the same channel width and same channel length, and have the gate nodes thereof coupled to each other, thereby forming a current mirror circuit. A reference current Iref−P runs through the PMOS transistor103and the NMOS transistor101, and the current IBL+P runs through the PMOS transistor104and the NMOS transistor102. The current IBL−P is supplied from the power supply potential Vdd through the PMOS transistor33, for example, and the NMOS transistor29as shown inFIG. 12.

The NMOS transistors71and72, the PMOS transistors73and74, and the inverter75constitute a first mirror amplifier to detect (sense) the current IBL−N, which flows out of the current sensing circuit. The inverter100, the PMOS transistors101and102, the NMOS transistors103and104, and the inverters105and106constitute a second mirror amplifier to detect (sense) the current IBL−P, which flows into the current sensing circuit.

The NMOS transistors71and72have the gate node thereof to which a test enable signal TEN is applied. When the test enable signal TEN is set to HIGH, the NMOS transistors71and72are turned on to become conductive. The PMOS transistors101and102have the gate node thereof to which an inverse of a test enable signal TEP is applied. When the test enable signal TEP is set to HIGH, the PMOS transistors101and102are turned on to become conductive.

The channel width conditions and channel length conditions with respect to the NMOS transistors71and72are the same as in the first embodiment. The channel width conditions and channel length conditions with respect to the PMOS transistors101and102are set similarly to the manner the channel width conditions and channel length conditions of the NMOS transistors71and72are set.

If the current IBL−N is larger than the reference current Iref−N, the input node of the inverter75is set to a low potential, resulting in the output TRN1of the inverter75being HIGH. If the current IBL−N is smaller than the reference current Iref−N, the input node of the inverter75is set to a high potential, resulting in the output TRN1of the inverter75being LOW.

By the same token, if the current IBL−P is larger than the reference current Iref−P, the input node of the inverter105is set to a high potential, resulting in the output TRP1of the inverter106being HIGH. If the current IBL−P is smaller than the reference current Iref−P, the input node of the inverter105is set to a low potential, resulting in the output TRP1of the inverter106being LOW.

In this manner, the current sensing circuit53produces the test result signal TRN1for the NMOS transistor21, and produces the test result signal TRP1for the PMOS transistor33. By the same token, the current sensing circuit54produces a test result signal /TRN1for the NMOS transistor22, and produces a test result signal /TRP1for the PMOS transistor34. That is, the test result signals TRN1, /TRN1, TRP1, and /TRP1can be obtained for a single memory cell. For n-th memory cell, test result signals TRNn, /TRNn, TRPn, and /TRPn are obtained in the same manner.

FIG. 14a circuit diagram showing part of the cell test circuitry56of the second embodiment. The circuit shown inFIG. 14includes NAND gates111through113and an inverter114. The output SW of the inverter114becomes LOW if TEN and WLW are both HIGH or if TEP and EQ are both HIGH. Otherwise, the signal SW is set to HIGH. This signal SW serves as a test selecting signal specifying whether transistors to be tested are tested for their proper conductive state or for their proper nonconductive state.

FIG. 15a circuit diagram showing another part of the cell test circuitry56of the second embodiment. The circuit shown inFIG. 15includes NAND gates121through123. The output TRn of the NAND gate123becomes HIGH if TEN and TRNn are both HIGH or if TEP and TRPn are both HIGH. Otherwise, the test result signal TRn is set to LOW. Circuits each having the same configuration as the circuit shown inFIG. 15is provided for the purpose of producing TR1through TRn and /TR1through /TRn, respectively.

The test result signals TR1through TRn and /TR1through /TRn produced in this manner are then used in the same manner as in the first embodiment to produce TON and TOFF by use of the circuit shown inFIG. 8. Both TON and TOFF become LOW if all the transistors tested for their operation properly allow respective currents to flow through. Further, both TON and TOFF become HIGH if all the transistors tested for their operation properly prevent respective currents from flowing through.

FIG. 16is a circuit diagram showing another part of the cell test circuitry56of the second embodiment. The part of the cell test circuitry56shown inFIG. 16includes a NAND gate131, a NAND gate132, and an exclusive-OR gate133. When the transistors to be tested are to be tested for their proper conductive state (i.e., currents properly flow through these transistors), the test selecting signal SW is set to HIGH (seeFIG. 14).

When the test selecting signal SW is LOW, the output of the NAND gate131is fixed to HIGH. Only if both TON and TOFF are set to LOW, indicating that all the tested transistors properly allow respective currents to flow through, does the NOR gate132produce a HIGH output, resulting in the output of the exclusive-OR gate133being LOW. Otherwise, the output of the exclusive-OR gate133is set to HIGH.

When the test selecting signal SW is HIGH, the output of the NOR gate132is fixed to LOW. Only if both TON and TOFF are set to HIGH, indicating that all the tested transistors properly prevent respective currents from flowing through, does the NAND gate132produce a LOW output, resulting in the output of the exclusive-OR gate133being LOW. Otherwise, the output of the exclusive-OR gate133is set to HIGH.

Accordingly, the output of the exclusive-OR gate133serves as a fail signal FAIL, which becomes LOW if the test results indicate no error, and becomes HIGH if any one of the test results indicates an error.

FIG. 17is a signal waveform chart showing signal waveforms that are used when test operations are performed with respect to NMOS transistors (21and22shown inFIG. 12). As shown inFIG. 17, the word selecting line WLW is first set to LOW to check whether all the NMOS transistors to be tested are properly placed in a nonconductive state. The choice of such test is indicated by the HIGH state of the test selecting signal SW. The precharge signal PRC and the test enable signal TEN are then set to HIGH to check the test results, resulting in TON and TOFF being both HIGH. The fact that both TON and TOFF are HIGH in this case indicates that none of the NMOS transistors exhibits an error. The fail signal FAIL is LOW in this case.

The word selecting line WLW is then set to HIGH to check whether all the NMOS transistors to be tested are properly placed in a conductive state. The choice of such test is indicated by the LOW state of the test selecting signal SW. The precharge signal PRC and the test enable signal TEN are then set to HIGH to check the test results, resulting in TON and TOFF being both LOW. The fact that both TON and TOFF are LOW in this case indicates that none of the NMOS transistors exhibits an error. The fail signal FAIL is LOW in this case.

FIG. 18is a table chart showing logic values of some of the relevant signals for the NMOS test operation. As shown inFIG. 18, when WLW is 0, the fact that TRn (TR1, /TR1, TR2, /TR2, . . . , TRn, and /TRn) are all zero indicates there is no error. If any one of TRn is 1, the fail signal FAIL becomes 1, indicating the presence of an error.

When WLW is 1, on the other hand, the fact that TRn (TR1, /TR1, TR2, /TR2, . . . , TRn, and /TRn) are all “1” indicates there is no error. If any one of TRn is zero, the fail signal FAIL becomes 1, indicating the presence of an error.

FIG. 19is a signal waveform chart showing signal waveforms that are used when test operations are performed with respect to PMOS transistors (33and34shown inFIG. 12). As shown inFIG. 19, the equalize line EQ is first set to HIGH to check whether all the PMOS transistors to be tested are properly placed in a nonconductive state. The choice of such test is indicated by the HIGH state of the test selecting signal SW. The precharge signal PRC and the test enable signal TEP are then set to HIGH to check the test results, resulting in TON and TOFF being both HIGH. The fact that both TON and TOFF are HIGH in this case indicates that none of the PMOS transistors exhibits an error. The fail signal FAIL is LOW in this case.

The equalize line EQ is then set to LOW to check whether all the PMOS transistors to be tested are properly placed in a conductive state. The choice of such test is indicated by the LOW state of the test selecting signal SW. The precharge signal PRC and the test enable signal TEP are then set to HIGH to check the test results, resulting in TON and TOFF being both LOW. The fact that both TON and TOFF are LOW in this case indicates that none of the PMOS transistors exhibits an error. The fail signal FAIL is LOW in this case.

FIG. 20is a table chart showing logic values of some of the relevant signals for the PMOS test operation. As shown inFIG. 20, when EQ is 1, the fact that TRn (TR1, /TR1, TR2, /TR2, . . . , TRn, and /TRn) are all zero indicates there is no error. If any one of TRn is 1, the fail signal FAIL becomes 1, indicating the presence of an error.

When EQ is 0, on the other hand, the fact that TRn (TR1, /TR1, TR2, /TR2, . . . , TRn, and /TRn) are all “1” indicates there is no error. If any one of TRn is zero, the fail signal FAIL becomes 1, indicating the presence of an error.

In the embodiments described heretofore, the nonvolatile memory unit is comprised of n-channel silicon MOS transistors. This is a non-limiting example. Other transistors such as p-channel silicon MOS transistors may as well be used to form the nonvolatile memory unit, and the test mechanism of the present invention may as well be properly used.

Further, these embodiments have been described with reference to an example in which a hot-carrier effect is used as a cause of an irreversible change. Other phenomenon such as NBTI (Negative Bias Temperature Instability) or PBTI (Positive Bias Temperature Instability) may be used to cause an irreversible change in place of the hot-carrier effect. Even when such other phenomenon is used for nonvolatile data retention, the test mechanism of the present invention may properly be used.

Further, the present invention is not limited to these embodiments, but various-variations and modifications may be made without departing from the scope of the present invention.