Method for forming inductor in semiconductor device

The present invention relates to a method for manufacturing an inductor being a passive device in RE MEMS, RFCMOS, Bipolor/SiGe and BiCMOS semiconductor devices. According to the present invention, a first negative photoresist layer is covered on a substrate having a lower electrode. A via hole that will become a contact portion of the inductor is then defined by means of an exposure process using a first mask. A second negative photoresist layer is covered on the first negative photoresist layer. Trenches that will become line portions of the inductor are defined by an exposure process using a second mask. A damascene pattern having the via hole and the trenches is formed by means of a developing process and is then buried with copper, thus forming the inductor. Not only a thickness of the trenches in the line portion and a thickness of the via hole in the contact portion can be uniformly controlled, but also their height can be easily controlled. Therefore, that an inductor of a high quality can be manufactured.

BACKGROUND

1. Field of the Invention

The present invention relates to a method for forming an inductor in a semiconductor device, and more specifically, to a method for forming an inductor in a semiconductor device wherein a thickness at the line and contact portions of the inductor being a passive device is made uniform and their height is easily controlled in RE MEMS, RFCMOS, Bipolor/SiGe and BiCMOS semiconductor devices, thus allowing a high Q inductor to be manufactured.

2. Discussion of Related Art

In RE MEMS, RFCMOS, Bipolor/SiGe and BiCMOS semiconductor devices, an inductor being a passive device is formed by means of a damascene process with the device higher integrated, and an inductor of a high quality is required.

FIG. 1AtoFIG. 1Fare cross-sectional views shown to explain a conventional method for forming an inductor in a semiconductor device.

Referring toFIG. 1A, a lower electrode11is formed using a conductive material such as copper on a substrate10in which a predetermined underlying structure constituting a semiconductor device is formed. A positive photoresist layer12is covered on the substrate10including the lower electrode11.

By reference toFIG. 1B, a primary exposure process is performed for some of the positive photoresist layer12up to the lower electrode11using a first mask13. A first exposure region12H is thus formed in a portion in which a contact of an inductor will be formed.

Referring toFIG. 1C, a secondary exposure process is performed for a portion of the positive photoresist layer12in a predetermined thickness using a first mask14. Second exposure regions12T are thus formed in portions in which lines of the inductor will be formed.

By reference toFIG. 1D, the first and second exposure regions12H and12T are developed to form trenches15in which the lines of the inductor is to be formed and a via hole16in which a contact of the inductor is to be formed.

Referring toFIG. 1E, the trenches15and the via hole16are buried with copper, forming the inductor17.

By reference toFIG. 1F, the positive photoresist layer12is stripped to form the inductor17that is spaced apart from the substrate10by a predetermined distance.

In recent years, as semiconductor devices are higher integrated and are multi-functioned, copper (Cu) has been widely used as a material of the inductor in order to implement the inductor of a high quality. In order to facilitate the use of copper, a damascene process is performed at the same time. In order to obtain a desired quality factor of the copper inductor, Cu lines of several μm in thickness are required. In the aforementioned conventional method, the depth of a photoresist layer developed is controlled depending on the time when light is illuminated by means of a positive photoresist layer, thus controlling the line thickness of an inductor that is completed. In this method, however, it is difficult to control the line thickness exactly and uniformly. This is because the amount of a photoresist developed is non-uniform due to various external environments such as the composition of the photoresist when the process is performed, the components or composition of a photoresist developer, a process condition, intensity and time of light illuminated and the like.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a method for forming an inductor in a semiconductor device wherein a thickness at the line and contact portions of the inductor is made uniform and their height is easily controlled, thus allowing a high Q inductor to be manufactured.

In order to accomplish the above object, according to an aspect of the present invention, there is provided a method for forming an inductor in a semiconductor device, comprising the steps of: forming a first negative photoresist layer on a substrate including a lower electrode; performing an exposure process for the first negative photoresist layer to form a first non-exposure region in the lower electrode portion; covering a second negative photoresist layer on the first negative photoresist layer; performing an exposure process for the second negative photoresist layer to form a second non-exposure region including the top of the first non-exposure region; implementing a developing process, whereby a via hole is formed in the first negative photoresist layer and trenches are formed in the second negative photoresist layer; and burying the via hole and the trenches with a conductive material.

In the above, after the first and second negative photoresist layers are covered, a soft bake process is performed, and after performing the exposure process for the first and second negative photoresist layers, a post expose bake process is performed.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Now the preferred embodiments according to the present invention will be described with reference to the accompanying drawings. Since preferred embodiments are provided for the purpose that the ordinary skilled in the art are able to understand the present invention, they may be modified in various manners and the scope of the present invention is not limited by the preferred embodiments described later.

FIG. 2AtoFIG. 2Eare cross-sectional views shown to explain a method for forming an inductor in a semiconductor device according to an embodiment of the present invention.

Referring toFIG. 2A, a lower electrode21is formed on a substrate20in which a predetermined underlying structure constituting a semiconductor device is formed. A first negative photoresist layer22is covered on the substrate20including the lower electrode21. After a soft bake process is performed, a primary exposure process is performed for some of the first negative photoresist layer22up to the substrate20using a first mask23. A first non-exposure region22H is thereby formed in a portion in which a contact of the inductor of the lower electrode21will be formed. A post expose bake process is then carried out.

In the above, the lower electrode21can be formed using a conductive material. In recent years, copper is widely used in order to meet higher-integration and multi-function of semiconductor devices. The thickness of the first negative photoresist layer22is determined considering the height of a contact portion in an inductor to be formed. The first mask23that defines the portion in which the contact of the inductor is to be formed has a mask tone opposite to the existing first mask23corresponding thereto. The first non-exposure region22H becomes the portion in which the contact of the inductor will be formed. As a subject to be exposed is a negative photoresist material, polymerization reaction occurs in a portion to which light of the first negative photoresist layer22is incident. The first non-exposure region22H that is not exposed is stripped in a subsequent developing process.

Referring toFIG. 2B, a second negative photoresist layer24is covered on the first negative photoresist layer22in which the first non-exposure region22H is formed. After a soft bake process is formed, a secondary exposure process is implemented for some of the second negative photoresist layer24up to the first negative photoresist layer22using a second mask25. Thereby, second non-exposure regions24T are formed in regions in which lines of the inductor including the top of the first non-exposure region22H are to be formed. A post expose bake process is then performed.

In the above, the thickness of the second negative photoresist layer24is determined considering the height of line portions of an inductor to be formed. The second mask25that defines the portion in which the lines of the inductor will be formed has a mask tone opposite to the existing second mask24corresponding thereto. The second non-exposure regions24T become the portion in which the lines of the inductor will be formed. As a subject to be exposed is a negative photoresist material, polymerization reaction occurs in a portion to which light of the second negative photoresist layer24is incident. The second non-exposure region24T that is not exposed is stripped in a subsequent developing process.

Meanwhile, polymerization reaction has already occurred in the first negative photoresist layer22beneath the portion to which light is incident during the exposure process of the second negative photoresist layer24since it receives the light in the first exposure process. Nothing effects are given to the first negative photoresist layer22even if light is incident thereto. In order to increase stability in the process, before the second negative photoresist layer24is covered, water-soluble BARC (Bottom Anti-Reflective Coating) can be covered as an anti-exposure and developing film on the first negative photoresist layer22in which the first non-exposure region22H is formed.

Referring toFIG. 2C, the second non-exposure regions24T of the second negative photoresist layer24and the first non-exposure region22H of the first negative photoresist layer22are developed. Therefore, trenches26are formed in a portions from which the second non-exposure regions24T are removed, and a via hole27in which the lower electrode21becomes the bottom is formed in a portion from which the first non-exposure region22H is removed.

By reference toFIG. 2D, the first and second negative photoresist layers22and24in which the trenches26and the via hole27are formed are baked. The trenches26and the via hole27are buried with copper to form an inductor28.

In the above, the burial of copper can be accomplished in such a way that if the lower electrode21is made of copper, the via hole27is buried by means of an electroplating method in which the copper lower electrode21is used as a seed layer, a seed layer is additionally formed on the inside of the trenches26, and an electroplating method is then performed to bury the trenches26, or a seed layer is formed on the inside of the trenches26and the via hole27, and the trenches26and the via hole27are then buried at once by an electroplating method. Copper can be buried by means of a variety of methods other than the above burial method. It has been described in the present invention that the inductor is formed using copper. It is, however, to be noted that the inductor can be formed using other conductive materials.

Referring toFIG. 2E, the first and second positive photoresist layers22and24are removed to complete an inductor28that is spaced apart from the substrate20by a predetermined distance.

In the above embodiment of the present invention, the trenches26in which the lines of the inductor will be formed can be formed in depth as high as the thickness of the second negative photoresist layer24. The via hole27in which the contact of the inductor will be formed can be formed in depth as high as the thickness of the first negative photoresist layer22. By controlling the thickness of the lines and contact of the inductor through the thickness of the first and second negative photoresist layers22and24as such, it is possible to obtain an exact and uniform inductor.

According to the present invention described above, in RE MEMS, RFCMOS, Bipolor/SiGe and BiCMOS semiconductor devices, a thickness of trenches being line portions of an inductor being a passive device and a thickness of a via hole being a contact portion of the inductor can be uniformly controlled and their height can be easily controlled. It is therefore possible to form a high Q inductor having the height of several to several tens of μm uniformly and to realize reliability and higher-integration of a device.