Vertical semiconductor device having a non-conductive substrate and a gallium nitride layer

The present invention discloses a vertical semiconductor device and a manufacturing method thereof. The vertical semiconductor device includes: a substrate having a first surface and a second surface, the substrate including a conductive array formed by multiple conductive plugs through the substrate; a semiconductor layer formed on the first surface, the semiconductor layer having a third surface and a fourth surface, wherein the fourth surface faces the first surface; a first electrode formed on the third surface; and a second electrode formed on the second surface for electrically connecting to the conductive array.

BACKGROUND OF THE INVENTION

1. Field of Invention

The present invention relates to a vertical semiconductor device and a manufacturing method of a vertical semiconductor device; particularly, it relates to such vertical semiconductor device and manufacturing method wherein the current crowding phenomenon of a device is mitigated.

2. Description of Related Art

Conventionally, gallium nitride (GaN) crystal epitaxial growth is performed on a silicon carbide (SiC) substrate or a sapphire substrate. Sapphire is an insulating material, so if a power device is to be manufactured on the sapphire substrate, it has to be formed laterally; that is, the electrodes of the power device are formed on the same side of the substrate. This increases the area of the power device and the manufacturing cost, and also induces the current crowding problem.

To overcome the drawback in the prior art, the present invention proposes a vertical semiconductor device and a manufacturing method thereof which decrease the device area such that the manufacturing cost is decreased, and mitigate the current crowding problem.

SUMMARY OF THE INVENTION

A first objective of the present invention is to provide a vertical semiconductor device.

A second objective of the present invention is to provide a manufacturing method of a vertical semiconductor device.

To achieve the objectives mentioned above, from one perspective, the present invention provides a vertical semiconductor device, including: a substrate having a first surface and a second surface facing opposite directions, the substrate including a conductive array formed by a plurality of conductive plugs through the substrate; a semiconductor layer formed on the first surface, the semiconductor layer having a third surface and a fourth surface facing opposite directions, wherein the fourth surface faces the first surface; a first electrode formed on the third surface; and a second electrode formed on the second surface, for electrically connecting to the conductive array.

From another perspective, the present invention provides a manufacturing method of a vertical semiconductor device, including: providing a substrate, which has a first surface and a second surface facing opposite directions; forming a semiconductor layer on the first surface, which has a third surface and a fourth surface facing opposite directions, wherein the fourth surface faces the first surface; forming a first electrode on the third surface; forming a plurality of holes through the substrate, the holes forming a hole array; forming a plurality of conductive plugs in the holes to form a conductive array; and forming a second electrode on the second surface for electrically connecting to the conductive array.

In one embodiment, the substrate preferably includes a silicon carbide (SiC) substrate or a sapphire substrate.

In the aforementioned embodiment, the semiconductor layer preferably includes a gallium nitride (GaN) layer, and the first electrode, the GaN layer, the conductive array, and the second electrode form a vertical Schottky barrier diode (SBD).

In another embodiment, the semiconductor layer preferably includes: a GaN layer doped with first conductive type impurities; a base region doped with second conductive type impurities, the base region being formed in the GaN layer and electrically connected to the first electrode; and an emitter region doped with first conductive type impurities, the emitter region being formed in the base region and electrically connected to a third electrode which is formed on the third surface; wherein the first electrode, the semiconductor layer, the third electrode, the conductive array, and the second electrode form a vertical bipolar junction transistor (BJT).

In another preferable embodiment, the semiconductor layer includes: a GaN layer doped with first conductive type impurities; a body region doped with second conductive type impurities, the body region being formed in the GaN layer and electrically connected to the first electrode; an emitter region doped with first conductive type impurities, the emitter region being formed in the body region and electrically connected to the first electrode; and an injection region doped with second conductive type impurities, the injection region being formed between the GaN layer and the substrate, and being electrically connected to the second electrode by the conductive array. And, the vertical semiconductor device further includes: a dielectric layer formed on the third surface; and a gate formed on the dielectric layer. Thus, the first electrode, the semiconductor layer, the conductive array, the second electrode, the dielectric layer, and the gate form a vertical insulated gate bipolar transistor (IGBT).

The objectives, technical details, features, and effects of the present invention will be better understood with regard to the detailed description of the embodiments below.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The drawings as referred to throughout the description of the present invention are for illustration only, to show the interrelations between the regions and the process steps, but not drawn according to actual scale.

FIGS. 1A-1Dshow a first embodiment of the present invention.FIGS. 1A-1Dare schematic cross-section diagrams showing a manufacturing flow of a Schottky barrier diode (SBD)100according to this embodiment. As shown inFIG. 1A, first, a substrate11is provided, which has an upper surface111and a lower surface112. The substrate11for example is but not limited to a silicon carbide (SiC) substrate or a sapphire substrate.

Next, referring toFIG. 1B, a semiconductor layer13is formed on the upper surface111. The semiconductor layer13has an upper surface133and a lower surface134, wherein the lower surface134faces the upper surface111. The semiconductor layer13is for example but not limited to a gallium nitride (GaN) layer. Next, an anode14is formed on the upper surface133, wherein a Schottky contact is formed between the anode14and the semiconductor layer13.

Next, as shown inFIG. 1C, multiple holes12aare formed through the substrate11between the upper surface111and the lower surface112, by for example but not limited to a laser etching technology. The multiple holes12aform a hole array12from top view (not shown). A conductive array16through the substrate11is formed by forming multiple conductive plugs16ain the holes12a. Then a cathode15is formed on the lower surface112for electrically connecting to the conductive array16. An Ohmic contact is formed between the conductive array16and the semiconductor layer13. Thus, the anode14, the semiconductor layer13, the conductive array16, and the cathode15form the vertical SBD100.

FIGS. 2A-2Dshow a second embodiment of the present invention.FIGS. 2A-2Dare schematic cross-section diagrams showing a manufacturing flow of a bipolar junction transistor (BJT)200according to this embodiment. As shown inFIG. 2A, similar to the first embodiment, first, a substrate11is provided, which has an upper surface111and a lower surface112. The substrate11for example is but not limited to a silicon carbide (SiC) substrate or a sapphire substrate. Next, a semiconductor layer23is formed on the upper surface111. The semiconductor layer23includes an upper surface233and a lower surface234, and the lower surface234faces the upper surface111. The semiconductor layer23is for example but not limited to a GaN layer. This embodiment is different from the first embodiment in that, the semiconductor layer23is doped with first conductive type impurities. The first conductive type is for example but not limited to N-type.

Next, referring toFIG. 2B, a base region27doped with second conductive type impurities is formed in the semiconductor layer23beneath the upper surface233. The second conductive type is for example but not limited to P-type. Next, a base24is formed on the upper surface233. The base24is electrically connected to the base region27. An emitter region28doped with first conductive type (for example N-type) impurities is formed in the base region27beneath the upper surface233. An emitter29is formed on the upper surface233, which is electrically connected to the emitter region28.

As shown inFIG. 2C, multiple holes12aare formed through the substrate11between the upper surface111and the lower surface112, by for example but not limited to a laser etching technology. The multiple holes12aform a hole array12from top view (not shown).

Next, referring toFIG. 2D, a conductive array16through the substrate11is formed by forming multiple conductive plugs16ain the holes12a. Next, a collector25is formed on the lower surface112, which is electrically connected to the conductive array16. An Ohmic contact is formed between the conductive array16and the semiconductor layer23. Thus, the base region27, the base28, the emitter29, the semiconductor layer23, the conductive array16, and the collector25form the vertical BJT200.

FIG. 3A-3Dshow a third embodiment of the present invention.FIGS. 3A-3Dare schematic cross-section diagrams showing a manufacturing flow of an insulated gate bipolar transistor (IGBT)300according to this embodiment. As shown inFIG. 3A, similar to the second embodiment, first, a substrate11is provided, which has an upper surface111and a lower surface112. The substrate11for example is but not limited to a SiC substrate or a sapphire substrate. Next, semiconductor layers32and33are formed on the upper surface111. The semiconductor layer33includes an upper surface333, and the semiconductor layer32includes a lower surface334, and the lower surface334faces the upper surface111. The semiconductor layers32and33are for example but not limited to GaN layers. This embodiment is different from the second embodiment in that, the semiconductor layer33is doped with first conductive type impurities, and the semiconductor layer32is doped with second conductive type impurities. The first conductive type is for example but not limited to N-type and the second conductive type is for example but not limited to P-type; however, the first conductive type can be P-type and the second conductive type can be N-type.

Next, referring toFIG. 3B, a body region37doped with second conductive type impurities is formed in the semiconductor layer33beneath the surface333. Next, a body electrode34is formed on the upper surface333for electrically connecting to the body region37. An emitter region38doped with first conductive type impurities is formed in the body region37beneath the upper surface33. The emitter region is also electrically connected to the body electrode34. Next, a dielectric layer391is formed on the upper surface333, above portions of the semiconductor layer33, the body region37, and the emitter38. Next, a gate39is formed on the dielectric layer391.

As shown inFIG. 3C, multiple holes12aare formed through the substrate11between the upper surface111and the lower surface112, by for example but not limited to the laser etching technology. The multiple holes12aform a hole array12from top view (not shown).

Next, referring toFIG. 3D, the conductive array16through the substrate11is formed by forming multiple conductive plugs16ain the holes12a. Next, a collector35is formed on the lower surface112, which is electrically connected to the conductive array16. An Ohmic contact is formed between the conductive array16and the semiconductor layer32. Thus, the body electrode34, the semiconductor layers32and33, the gate39, the dielectric layer391, the conductive array16, the body region37, the emitter region38, and the collector35form the vertical IGBT300.

Note that the present invention forms vertical semiconductor devices by the conductive array16through the substrate11. Comparing to the lateral semiconductor device, the vertical semiconductor device not only occupies less area and therefore decreases the manufacturing cost, but also mitigates the current crowding problem because the carriers flow vertically instead of laterally when the vertical semiconductor device operates.

The present invention has been described in considerable detail with reference to certain preferred embodiments thereof. It should be understood that the description is for illustrative purpose, not for limiting the scope of the present invention. Those skilled in this art can readily conceive variations and modifications within the spirit of the present invention. For example, other process steps or structures which do not affect the primary characteristics of the device, such as an aluminum gallium nitride (AlGaN) layer between the semiconductor layer13and the anode14in the vertical SBD100, can be added. For another example, the semiconductor layer13may be P-type or N-type in the SBD100. In view of the foregoing, the spirit of the present invention should cover all such and other modifications and variations, which should be interpreted to fall within the scope of the following claims and their equivalents.