Integrated circuitry, memory circuitry, method used in forming integrated circuitry, and method used in forming memory circuitry

A method used in forming integrated circuitry comprises forming conductive material over a substrate. The conductive material is patterned into a conductive line that is horizontally longitudinally elongated. The conductive material is vertically recessed in longitudinally-spaced first regions of the conductive line to form longitudinally-spaced conductive pillars that individually are in individual longitudinally-spaced second regions that longitudinally-alternate with the longitudinally-spaced first regions along the conductive line. The conductive pillars project vertically relative to the conductive material in the longitudinally-spaced and vertically-recessed first regions of the conductive line. Electronic components are formed directly above the conductive pillars. Individual of the electronic components are directly electrically coupled to individual of the conductive pillars. Additional methods, including structure independent of method, are disclosed.

TECHNICAL FIELD

Embodiments disclosed herein pertain to integrated circuitry, to memory circuitry, to methods used in forming integrated circuitry, and to methods used in forming integrated circuitry.

BACKGROUND

Memory cells may be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for extended periods of time in the absence of power. Non-volatile memory is conventionally specified to be memory having a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed/rewritten to maintain data storage. Volatile memory may have a retention time of milliseconds or less. Regardless, memory cells are configured to retain or store memory in at least two different selectable states. In a binary system, the states are considered as either a “0” or a “1. In other systems, at least some individual memory cells may be configured to store more than two levels or states of information.

A capacitor is one type of electronic component that may be used in a memory cell. A capacitor has two electrical conductors separated by electrically insulating material. Energy as an electric field may be electrostatically stored within such material. Depending on composition of the insulator material, that stored field will be volatile or non-volatile. For example, a capacitor insulator material including only SiO2will be volatile. One type of non-volatile capacitor is a ferroelectric capacitor which has ferroelectric material as at least part of the insulating material. Ferroelectric materials are characterized by having two stable polarized states and thereby can comprise programmable material of a capacitor and/or memory cell. The polarization state of the ferroelectric material can be changed by application of suitable programming voltages and remains after removal of the programming voltage (at least for a time). Each polarization state has a different charge-stored capacitance from the other, and which ideally can be used to write (i.e., store) and read a memory state without reversing the polarization state until such is desired to be reversed. Less desirable, in some memory having ferroelectric capacitors the act of reading the memory state can reverse the polarization. Accordingly, upon determining the polarization state, a re-write of the memory cell is conducted to put the memory cell into the pre-read state immediately after its determination. Regardless, a memory cell incorporating a ferroelectric capacitor ideally is non-volatile due to the bi-stable characteristics of the ferroelectric material that forms a part of the capacitor. Other programmable materials may be used as a capacitor insulator to render capacitors non-volatile.

A field effect transistor is another type of electronic component that may be used in a memory cell. These transistors comprise a pair of conductive source/drain regions having a semiconductive channel region there-between. A conductive gate is adjacent the channel region and separated there-from by a thin gate insulator. Application of a suitable voltage to the gate allows current to flow from one of the source/drain regions to the other through the channel region. When the voltage is removed from the gate, current is largely prevented from flowing through the channel region. Field effect transistors may also include additional structure, for example a reversibly programmable charge-storage region as part of the gate construction between the gate insulator and the conductive gate. Regardless, the gate insulator may be programmable, for example being ferroelectric.

Capacitors and transistors may of course be used in integrated circuitry other than memory circuitry.

Some conductive lines of integrated circuitry, for example digitlines as referred to above, are longitudinally elongated horizontally. Electronic components, for example field effect transistors of memory cells, may be directly electrically coupled longitudinally along a conductive line.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Embodiments of the invention include methods used in forming integrated circuitry, for example memory circuitry, and integrated circuitry independent of method of manufacture. Example method embodiments of forming memory integrated circuitry are initially described with reference toFIGS.1-23.

Referring toFIGS.1-3, such show a portion of a substrate construction10comprising a base substrate11comprising any one or more of conductive/conductor/conducting, semiconductive/semiconductor/semiconducting, and insulative/insulator/insulating (i.e., electrically herein) materials. Various materials may be formed elevationally over and within base substrate11. Materials may be aside, elevationally inward, or elevationally outward of theFIGS.1-3-depicted materials. For example, other partially or wholly fabricated components of integrated circuitry may be provided somewhere above, about, or within base substrate11. With respect to memory circuitry, control and/or other peripheral circuitry for operating components within an array of memory cells may also be fabricated and may or may not be wholly or partially within an array or sub-array. Further, multiple sub-arrays may also be fabricated and operated independently, in tandem, or otherwise relative one another. As used in this document, a “sub-array” may also be considered as an array.

Referring toFIGS.4-6, conductive material36has been patterned into a conductive line38that is horizontally longitudinally elongated. Multiple conductive lines38are shown as having been formed, although method and structure embodiments herein also contemplate a single conductive line, Conductive line(s)38may be patterned using any existing or future-developed techniques, and with or without pitch multiplication. Photolithographic patterning and etch is but one example. Insulator material50when present may also be so-patterned as shown.

Referring toFIGS.7-9, and in one embodiment, space that is laterally-between immediately-adjacent conductive lines38has been filled with insulative material45(e.g., silicon nitride and/or silicon dioxide). By way of example, such may be formed to initially overfill such spaces followed by planarizing insulative material45back at least to a top surface of insulator material50. Insulative material45and insulator material50may be of same composition relative one another (exemplified by dashed interface lines there-between) or may be of different compositions relative one another.

Conductive lines38individually may be considered as comprising longitudinally-spaced first regions40and longitudinally-spaced second regions42that longitudinally-alternate with longitudinally-spaced first regions40along individual conductive lines38. Such regions may not be discernible at this point of processing. Regardless, referring toFIGS.10-12and in one embodiment, patterned masking material55has been formed atop the construction ofFIGS.7-9to mask second regions42and leave first regions40exposed.

Referring toFIGS.13-17, patterned masking material55(not shown) has been used as a mask while conducting, for example, a timed anisotropic etch into conductive material36to vertically recess conductive material36in longitudinally-spaced first regions40to form longitudinally-spaced conductive pillars35that individually are in individual longitudinally-spaced second regions42. Example masking material55(not shown) has been removed during and/or after such example etching. Conductive pillars35project vertically relative to conductive material36in longitudinally-spaced and vertically-recessed first regions40of conductive lines38. In one embodiment where insulator material50is present atop conductive material36and as shown, such has been removed from being atop conductive material36that is in longitudinally-spaced first regions40of the individual conductive lines38before such vertical recessing. Insulator material50(at least some of such) may remain atop conductive pillars35after their formation and, if so, may be in a finished construction of the integrated circuitry, for example as will be apparent in the continuing sequence of drawings in one embodiment. The above-described processing is but one example of vertically recessing conductive material35in longitudinally-spaced first regions40to form longitudinally-spaced conductive pillars35. Any other existing or future-developed methods may be used.

In one embodiment, the vertically recessing forms tops48of conductive material36of conductive lines38in longitudinally-spaced first regions40to be lower than tops49of insulative material45that is laterally-between conductive lines38(FIG.17), and in one embodiment with the space between conductive lines38having insulative material45therein during the forming of conductive pillars35. The vertically recessing has formed void space44above longitudinally-spaced first regions40of conductive lines38longitudinally-between immediately-longitudinally-adjacent conductive pillars35. In one embodiment, conductive material36of conductive pillars35of conductive lines38, conductive material36of conductive lines38below conductive pillars35, and conductive material36of conductive lines38in longitudinally-spaced first regions40are of the same composition relative one another. Such composition, by way of example only, may be homogenous or alternately non-homogenous, for example comprising multiple different composition layers (not shown).

Referring toFIGS.18-22, and in one embodiment, sidewalls of void space44have been lined with first insulating material46that less-than-fills void space44, followed by filling remaining volume of void space44with second insulating material47that is of different composition from that of first insulating material46. Such may be formed, for example, by first depositing a thin conformal layer of first insulating material46, followed by formation of second insulating material47, and followed by planarizing first insulating material46and second insulating material47back at least to a top surface of insulator material50as shown. By way of examples, first insulating material46may be silicon nitride or silicon dioxide and second insulating material47may be the other of silicon nitride or silicon dioxide. One example is first insulating material46being silicon nitride and second insulating material47being silicon dioxide that has been formed with spin-on-dielectric and subsequent densification thereof. Regardless, and in one embodiment as shown, sidewalk of void space44may be considered as comprising sidewalls52of conductive material36and sidewalls54of insulator material50that is atop conductive pillars35(FIG.20). In such example, first insulating material46and second insulating material47are laterally over both of sidewalk52of conductive material36and sidewalk54of insulator material50. Regardless, in one embodiment insulator material50and first insulating material46are of the same composition relative one another.

FIG.23is an enlarged perspective view of a portion of a single conductive line38having two pillars35as a part thereof, with other materials there-about having been removed for clarity. Individual conductive pillars35may be considered as having an uppermost conductive surface56and in one embodiment that is planar. Conductive material36of conductive line38in individual of longitudinally-spaced first regions40may be considered as having an uppermost conductive surface58and in one embodiment that is planar. In one embodiment, pillar-uppermost-conductive surface56and first-region-uppermost surface58are of the same maximum length L relative one another in a straight-line direction60(e.g., the cross-section that isFIG.19or22) that is orthogonal to longitudinal orientation (e.g., that along a longitudinal axis65) of the individual conductive line38.

Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used in the embodiments shown and described with reference to the above embodiments.

An alternate example embodiment is shown and described with reference toFIG.24with respect to a portion of a construction10a. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix “a” or with different numerals or letters. In construction10a, pillar uppermost conductive surface56ahas a maximum length D in straight-line direction60that is shorter than a maximum length Ii of first region uppermost conductive surface58ain straight-line direction60. In one embodiment, straight-line direction60may be considered as first straight-line direction60and construction10acomprises a second straight-line direction62that is orthogonal to first straight-line direction60. Pillar uppermost conductive surface56aof individual conductive pillars35has a maximum length G in second straight-line direction62that is shorter than a maximum length H in second straight-line direction62of uppermost conductive surface58aof conductive material36of conductive line38in individual longitudinally-spaced first regions40. In one embodiment and as shown, conductive lines38individually have a bottom surface64that has a maximum length J in first straight-line direction60that is longer than maximum length E in first straight-line direction60of uppermost conductive surface58aof conductive material36of individual conductive lines38in individual longitudinally-spaced first regions40. The artisan is capable of selecting suitable anisotropic etching conditions that impact whether sidewalls in a subtractive etch, for example, are vertical or whether such taper from vertical. For example, varying one of more of temperature, pressure, or power in a plasma etch can be used to impact such, and which may be different for different chemistries. Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

Electronic components are formed directly above conductive pillars35, with individual of the electronic components being directly electrically coupled to individual of conductive pillars35. In one embodiment, the individual electronic components are directly against an uppermost conductive surface56/56aof the individual conductive pillar to which the respective electronic component is directly electrically coupled. Any existing or future-developed electronic component(s) may be used. In one embodiment, the electronic components individually comprise a vertical transistor.

For example, and referring toFIG.25, such shows an example embodiment wherein vertical transistors18are shown schematically as having been formed directly above and directly electrically coupled to individual conductive pillars35in construction10. Such vertical transistors comprise a top source/drain region32, a bottom source/drain region30, and a channel region15vertically there-between. A conductive gate20and a gate insulator17are operably aside channel region15. Example bottom source/drain region30is directly above and directly against an individual conductive pillar35, for example directly against uppermost conductive surface56. In one embodiment and as shown, for example in a method used in forming memory circuitry, a storage device85has been formed directly above and directly electrically coupled to top source/drain region32, with an example storage device85being schematically depicted as a capacitor85.

FIGS.26and27show, in but one example, more structure associated withFIGS.19and20. For example, vertical transistors18that are referred to above are shown. Such are shown as being laterally separated by dielectric material12(e.g., silicon dioxide). Gates20and gate insulator17as shown are on opposing sides of channel regions15. Gates20may comprise gate lines that interconnect transistors18along a row direction. Regions32,15, and30may be of any one or more suitable horizontal cross-sectional shapes, with square (as shown) or rectangular (not shown) being ideal at least for channel region15towards maximizing lateral overlap of gateline20with channel region15. Capacitors85are shown individually directly electrically coupled to individual top source/drain regions32of individual vertical transistors18. Such, by way of example, are shown as comprising a bottom capacitor electrode/storage node70, a shared top capacitor electrode74, and capacitor insulator72there-between. A single capacitor85and a single vertical transistor18directly there-below may comprise a single memory cell, for example of a one transistor-one capacitor DRAM cell of DRAM integrated circuitry.

Alternate embodiment constructions may result from method embodiments described above, or otherwise. Regardless, embodiments of the invention encompass integrated circuitry independent of method of manufacture. Nevertheless, such integrated circuitry may have any of the attributes as described herein in method embodiments. Likewise, the above-described method embodiments may incorporate, form, and/or have any of the attributes described with respect to device embodiments.

In one embodiment, integrated circuitry comprises a conductive line (e.g.,38) that is horizontally longitudinally elongated. The conductive line comprises longitudinally-spaced first regions (e.g.,40) that alternate with longitudinally-spaced second regions (e.g.,42) along the conductive line. The longitudinally-spaced second regions are characterized by a conductive pillar (e.g.,35) that projects vertically relative to conductive material (e.g.,36) of the conductive line in the longitudinally-spaced first regions. The conductive pillar has an uppermost conductive surface (e.g.,56a) and the conductive material of the conductive line in individual of the longitudinally-spaced first regions has an uppermost conductive surface (e.g.,58a). The uppermost conductive surface of the conductive pillar has a maximum length (e.g., D) in a straight-line direction (e.g.,60) that is orthogonal to longitudinal orientation (e.g.,62/65) of the conductive line that is shorter than a maximum length (e.g., E) of the uppermost conductive surface of the conductive material of the conductive line in the individual longitudinally-spaced first regions in the straight-line direction. Electronic components (e.g.,18) are directly above the conductive pillars. Individual of the electronic components are directly electrically coupled to individual of the conductive pillars. Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

In cine embodiment, memory circuitry comprises multiple conductive lines (e.g.,38) that are horizontally longitudinally elongated and laterally spaced from one another. Individual of the conductive lines comprise longitudinally-spaced first regions (e.g.,40) that alternate with longitudinally-spaced second regions (e.g.,42) along the individual conductive line. The longitudinally-spaced second regions are characterized by a conductive pillar (e.g.,35) that projects vertically relative to conductive material (e.g.,36) of the respective individual conductive line in the longitudinally-spaced first regions. The conductive pillar has an uppermost conductive surface (e.g.,56a) and the conductive material of the conductive line in individual of the longitudinally-spaced first regions has an uppermost conductive surface (e.g.,58a). The uppermost conductive surface of the conductive pillar has a maximum length (e.g., D) in a straight-line direction (e.g.,60) that is orthogonal to longitudinal orientation (e.g.,62/65) of the conductive line that is shorter than a maximum length (e.g., E) of the uppermost conductive surface of the conductive material of the respective conductive line in the individual longitudinally-spaced first regions in the straight-line direction. Vertical transistors (e.g.,18) are directly above the conductive pillars. Individual of the vertical transistors comprise a top source/drain region (e.g.,32), a bottom source/drain region (e.g.,30), and a channel region (e.g.,15) vertically between the top and bottom source/drain regions. The bottom source/drain region is directly above and directly against individual of the conductive pillars. A storage device (e.g.,85) is directly above and directly electrically coupled to the top source/drain region. Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

The above processing(s) or construction(s) may be considered as being relative to an array of components formed as or within a single stack or single deck of such components above or as part of an underlying base substrate (albeit, the single stack/deck may have multiple tiers). Control and/or other peripheral circuitry for operating or accessing such components within an array may also be formed anywhere as part of the finished construction, and in some embodiments may be under the array (e.g., CMOS under-array). Regardless, one or more additional such stack(s)/deck(s) may be provided or fabricated above and/or below that shown in the figures or described above. Further, the array(s) of components may be the same or different relative one another in different stacks/decks and different stacks/decks may be of the same thickness or of different thicknesses relative one another. Intervening structure may be provided between immediately-vertically-adjacent stacks/decks (additional circuitry and/or dielectric layers). Also, different stacks/decks may be electrically coupled relative one another. The multiple stacks/decks may be fabricated separately and sequentially (e.g., one atop another), or two or more stacks/decks may be fabricated at essentially the same time.

The assemblies and structures discussed above may be used in integrated circuits/circuitry and may be incorporated into electronic systems. Such electronic systems may be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. The electronic systems may be any of a broad range of systems, such as, for example, cameras, wireless devices, displays, chip sets, set top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc.

Further, “directly above”, “directly below”, and “directly under” require at least some lateral overlap (i.e., horizontally) of two stated regions/materials/components relative one another. Also, use of “above” not preceded by “directly” only requires that some portion of the stated region/material/component that is above the other be elevationally outward of the other (i.e., independent of whether there is any lateral overlap of the two stated regions/materials/components). Analogously, use of “below” and “under” not preceded by “directly” only requires that some portion of the stated region/material/component that is below/under the other be elevationally inward of the other (i.e., independent of whether there is any lateral overlap of the two stated regions/materials/components).

Any of the materials, regions, and structures described herein may be homogenous or non-homogenous, and regardless may be continuous or discontinuous over any material which such overlie. Where one or more example composition(s) is/are provided for any material, that material may comprise, consist essentially of, or consist of such one or more composition(s). Further, unless otherwise stated, each material may be formed using any suitable existing or future-developed technique, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implanting being examples.

Any use of “row” and “column” in this document is for convenience in distinguishing one series or orientation of features from another series or orientation of features and along which components have been or may be formed. “Row” and “column” are used synonymously with respect to any series of regions, components, and/or features independent of function. Regardless, the rows may be straight and/or curved and/or parallel and/or not parallel relative one another, as may be the columns. Further, the rows and columns may intersect relative one another at 90° or at one or more other angles (i.e., other than the straight angle).

The composition of any of the conductive/conductor/conducting materials herein may be metal material and/or conductively-doped semiconductive/semiconductor/semiconducting material. “Metal material” is any one or combination of an elemental metal, any mixture or alloy of two or more elemental metals, and any one or more conductive metal compound(s).

Herein, any use of “selective” as to etch, etching, removing, removal, depositing, forming, and/or formation is such an act of one stated material relative to another stated material(s) so acted upon at a rate of at least 2:1 by volume. Further, any use of selectively depositing, selectively growing, or selectively forming is depositing, growing, or forming one material relative to another stated material or materials at a rate of at least 2:1 by volume for at least the first 75 Angstroms of depositing, growing, or forming.

Unless otherwise indicated, use of “or” herein encompasses either and both.

CONCLUSION

In some embodiments, a method used in forming integrated circuitry comprises forming conductive material over a substrate. The conductive material is patterned into a conductive line that is horizontally longitudinally elongated. The conductive material is vertically recessed in longitudinally-spaced first regions of the conductive line to form longitudinally-spaced conductive pillars that individually are in individual longitudinally-spaced second regions that longitudinally-alternate with the longitudinally-spaced first regions along the conductive line. The conductive pillars project vertically relative to the conductive material in the longitudinally-spaced and vertically-recessed first regions of the conductive line. Electronic components are formed directly above the conductive pillars. Individual of the electronic components are directly electrically coupled to individual of the conductive pillars.

In some embodiments, a method used in forming memory circuitry comprises forming conductive material over a substrate. The conductive material is patterned into multiple conductive lines that are horizontally longitudinally elongated and laterally spaced from one another. The conductive material is vertically recessed in longitudinally-spaced first regions of individual of the conductive lines to form longitudinally-spaced conductive pillars that individually are in individual longitudinally-spaced second regions that longitudinally-alternate with the longitudinally-spaced first regions along the individual conductive lines. The conductive pillars project vertically relative to the conductive material in the longitudinally-spaced and vertically-recessed first regions of the individual conductive lines. Vertical transistors are formed directly above the conductive pillars. Individual of the vertical transistors comprise a top source/drain region, a bottom source/drain region, and a channel region vertically between the top and bottom source/drain regions. The bottom source/drain region is directly above and directly against individual of the conductive pillars. A storage device is formed directly above and directly electrically coupled to the top source/drain region.

In some embodiments, integrated circuitry comprises a conductive line that is horizontally longitudinally elongated. The conductive line comprises longitudinally-spaced first regions that alternate with longitudinally-spaced second regions along the conductive line. The longitudinally-spaced second regions are characterized by a conductive pillar that projects vertically relative to conductive material of the conductive line in the longitudinally-spaced first regions. The conductive pillar has an uppermost conductive surface and the conductive material of the conductive line in individual of the longitudinally-spaced first regions has an uppermost conductive surface. The uppermost conductive surface of the conductive pillar has a maximum length in a straight-line direction that is orthogonal to longitudinal orientation of the conductive line that is shorter than a maximum length of the uppermost conductive surface of the conductive material of the conductive line in the individual longitudinally-spaced first regions in the straight-line direction. Electronic components are directly above the conductive pillars. Individual of the electronic components are directly electrically coupled to individual of the conductive pillars.

In some embodiments, memory circuitry comprises multiple conductive lines that are horizontally longitudinally elongated and laterally spaced from one another. Individual of the conductive lines comprise longitudinally-spaced first regions that alternate with longitudinally-spaced second regions along the individual conductive line. The longitudinally-spaced second regions are characterized by a conductive pillar that projects vertically relative to conductive material of the respective individual conductive line in the longitudinally-spaced first regions. The conductive pillar has an uppermost conductive surface and the conductive material of the conductive line in individual of the longitudinally-spaced first regions has an uppermost conductive surface. The uppermost conductive surface of the conductive pillar has a maximum length in a straight-line direction that is orthogonal to longitudinal orientation of the conductive line that is shorter than a maximum length of the uppermost conductive surface of the conductive material of the respective conductive line in the individual longitudinally-spaced first regions in the straight-line direction. Vertical transistors are directly above the conductive pillars. Individual of the vertical transistors comprise a top source/drain region, a bottom source/drain region, and a channel region vertically between the top and bottom source/drain regions. The bottom source/drain region is directly above and directly against individual of the conductive pillars. A storage device is directly above and directly electrically coupled to the top source/drain region.