Signal transmission device and power switching element driving device

A signal transmission device relating to a technique disclosed in the specification of the present application includes: an isolation transformer; an input-side circuit connected to an input side of the isolation transformer; and an output-side circuit connected to an output side of the isolation transformer. The output-side circuit includes a first differential circuit having a first input and a second input connected to the first terminal and the second terminal respectively. A reference potential of the first differential circuit is connected to the second terminal.

FIELD OF THE INVENTION

A technique disclosed in the specification of the present application relates to a digital isolator used in the field of communication or in a semiconductor switching element driving device requiring communication between different power supplies, for example.

BACKGROUND ART

For a use involving communication between a circuit configuration on a primary side (input side) and a circuit configuration on a secondary side (output side) of different power supplies, dV/dt noise has conventionally be caused in some cases resulting from dV/dt to vary a reference potential difference between an input side and an output side of an isolation transformer. In response to the dV/dt noise, effort has been made to prevent malfunction due to such noise.

For example, in a circuit illustrated in Japanese Patent Application Laid-Open No. 2016-46723, a differential voltage responsive to a current flowing on an input side of an isolation transformer is induced in a coil on an output side of the isolation transformer. A potential is received by differential input from the output-side coil to remove the dV/dt noise resulting from dV/dt. In this way, malfunction due to the dV/dt noise is prevented.

According to the aforementioned technique, however, if the dV/dt noise is caused to place a signal at the output-side coil at a voltage going out of an operable range of the output-side circuit configuration, this signal cannot be received by the output-side circuit configuration. Hence, the dV/dt noise cannot be removed even in the circuit to receive a potential by differential input.

SUMMARY OF THE INVENTION

The present invention relates to a technique of achieving transmission of a signal, even if dV/dt noise is caused to place the signal at a voltage going out of an operable range of a circuit.

A first aspect of a technique disclosed in the specification of the present application includes: an isolation transformer; an input-side circuit connected to an input side of the isolation transformer; and an output-side circuit connected to an output side of the isolation transformer. The output-side circuit is connected to a first terminal and a second terminal. The first terminal is on the output side of the isolation transformer. The second terminal is on the output side of the isolation transformer and on an opposite side to the first terminal. The output-side circuit includes a first differential circuit having a first input and a second input connected to the first terminal and the second terminal respectively. The first differential circuit outputs a signal responsive to a potential difference between the first input and the second input. A reference potential of the first differential circuit is connected to the second terminal.

A second aspect of the technique disclosed in the specification of the present application includes: the aforementioned signal transmission device; a gate driver connected to the signal transmission device; and a power switching element connected to an output terminal of the gate driver.

According to the first aspect of the technique disclosed in the specification of the present application, even if dV/dt noise is caused to place a signal at a voltage going out of an operable range of a circuit, this signal can still be transmitted

According to the second aspect of the technique disclosed in the specification of the present application, even if the dV/dt noise is caused while the power switching element operates, a signal can still be transmitted.

EMBODIMENT FOR CARRYING OUT THE INVENTION

Preferred embodiments of the present invention will be described below by referring to the accompanying drawings.

The drawings are depicted schematically. For the convenience of illustration, structures are omitted from the drawings or structures in the drawings are simplified, where appropriate. The sizes of images, etc. shown in different drawings and the positions of such images relative to each other in the different drawings are not entirely correct but can be changed, where appropriate.

Comparable components referred to in the following description are identified by the same signs in the drawings. These components will be described as having the same name and the same function. Thus, in some cases, these components will not be described in detail to avoid overlaps.

Ordinal numbers such as a “first” and a “second” given in the following description are for the sake of convenience for facilitating understanding of the preferred embodiments. The present invention is not to be limited to order, etc. that might result from such ordinal numbers.

First Preferred Embodiment

A signal transmission device according to a first preferred embodiment will be described below.

<Configuration of Signal Transmission Device>

FIG. 1schematically illustrates the configuration of the signal transmission device according to the first preferred embodiment.

As illustrated inFIG. 1, the signal transmission device includes an input-side circuit configuration, an output-side circuit configuration, and an isolation transformer between the input-side circuit configuration and the output-side circuit configuration.

The isolation transformer is a structure including an oxide film or an insulating film such as a polyimide film formed between the input-side circuit configuration with respect to the transformer and the output-side circuit configuration with respect to the transformer. With this configuration, electrical isolation can be ensured between the input-side circuit configuration and the output-side circuit configuration. The following description of the preferred embodiments proceeds on the assumption that the isolation transformer is particularly a transformer without a core such as a micro-transformer. However, the isolation transformer may have a core such as an iron core.

The input-side circuit configuration includes a demodulation circuit10and a coil wiring13.

The output-side circuit configuration includes a demodulation circuit20, a coil wiring23, an impedance24, and an impedance25.

The isolation transformer provided between the input-side circuit configuration and the output-side circuit configuration, specifically, the isolation transformer including the coil wiring13and the coil wiring23has a parasitic (stray) capacitance C. An impedance component such as a coil wiring also exists between the input-side circuit configuration and the output-side circuit configuration.

For a use involving communication between the input-side circuit configuration and the output-side circuit configuration of different power supplies, variations are caused in a reference potential difference between the input-side circuit configuration and the output-side circuit configuration across the isolation transformer. In this case, capacitive coupling occurs in the parasitic capacitance C to charge the parasitic capacitance C with a current or the current is discharged from the parasitic capacitance C.

Charging the parasitic capacitance C with a current or discharging the current from the parasitic capacitance C, and the existence of the impedance component such as a coil wiring vary a potential at an output-side isolation transformer terminal. Specifically, dV/dt noise is caused.

At this time, if a potential at the output-side isolation transformer terminal varies to generate a voltage signal going out of an operable range of the output-side circuit configuration, this signal cannot be received properly by the output-side circuit configuration.

FIG. 2is a sequence chart illustrating variations in potentials at isolation transformer terminals in an instance where a reference potential in the output-side circuit configuration varies positively, specifically, during +dV/dt.

FIG. 2illustrates the following in the order named: dV/dt; a potential (IN) of an input signal shown inFIG. 1; a potential (TX1) of an output signal from the demodulation circuit10shown inFIG. 1; a potential (TX2) of an output signal from the demodulation circuit10shown inFIG. 1; a potential (RX1) of a received signal at the demodulation circuit20shown inFIG. 1; a potential (RX2) of a received signal at the demodulation circuit20shown inFIG. 1; and a potential (OUT) of an output signal from the demodulation circuit20shown inFIG. 1.

As illustrated inFIG. 2, in a period +dV/dt, due to the occurrence of the dV/dt noise, potential drop, more specifically, potential drop to a value near a GND potential of the demodulation circuit20is observed at each of RX1and RX2.

In the period +dV/dt, a potential at each of RX1and RX2takes a value smaller than the GND potential of the demodulation circuit20. This makes a signal go out of an operable range of the demodulation circuit20, so that this signal cannot be received properly in the period +dV/dt.

As a result, the potential at each of RX1and RX2is not reflected in OUT in the period +dV/dt.

FIG. 3is a sequence chart illustrating variations in potentials at the isolation transformer terminals in an instance where a reference potential in the output-side circuit configuration varies negatively, specifically, during −dV/dt.

FIG. 3illustrates the following in the order named: dV/dt; a potential (IN) of an input signal shown inFIG. 1; a potential (TX1) of an output signal from the demodulation circuit10shown inFIG. 1; a potential (TX2) of an output signal from the demodulation circuit10shown inFIG. 1; a potential (RX1) of a received signal at the demodulation circuit20shown inFIG. 1; a potential (RX2) of a received signal at the demodulation circuit20shown inFIG. 1; and a potential (OUT) of an output signal from the demodulation circuit20shown inFIG. 1.

As illustrated inFIG. 3, in a period −dV/dt, due to the occurrence of the dV/dt noise, potential increase, more specifically, potential increase to a value near a power supply potential of the demodulation circuit20is observed at each of RX1and RX2.

In the period −dV/dt, a potential at each of RX1and RX2takes a value larger than the power supply potential of the demodulation circuit20. This makes a signal go out of an operable range of the demodulation circuit20, so that this signal cannot be received properly in the period −dV/dt.

As a result, the potential at each of RX1and RX2is not reflected in OUT in the period −dV/dt.

As described above, if the dV/dt noise is caused to make a signal go out of an operable range of the output-side circuit configuration, this signal cannot be transmitted.

Assuming that the value of a current required for charging and discharging the parasitic capacitance C in response to the occurrence of the dV/dt noise is I, the following formula is established:
I=C×dV/dtformula 1

A variation value ΔV of a potential at the output-side isolation transformer terminal is expressed by the following formula:
ΔV=R×I=C×dV/dt×Rformula 2

Assuming that C is 0.300 pF, dV/dt is 100 kV/us, and R is 100Ω, the following formula is established:
ΔV=3 [V]  formula 3

FIG. 4schematically illustrates the configuration of the signal transmission device according to the first preferred embodiment. The signal transmission device illustrated inFIG. 4has a single-ended circuit configuration using two isolation transformers.

The signal transmission device illustrated inFIG. 4includes a modulation circuit31that operates on the ON edge, specifically, rising edge of a signal. The modulation circuit31functions as an input-side modulation circuit that drives an isolation transformer30. The signal transmission device illustrated inFIG. 4includes a modulation circuit33that operates on the OFF edge, specifically, falling edge of a signal. The modulation circuit33functions as an input-side modulation circuit that drives an isolation transformer32.

The modulation circuit31includes a one-shot circuit300that detects an ON edge, and a metal-oxide-semiconductor field-effect transistor (MOSFET)301and a MOSFET302connected in parallel to each other.

The modulation circuit33includes a one-shot circuit303that detects an OFF edge, and a MOSFET304and a MOSFET305connected in parallel to each other.

The signal transmission device illustrated inFIG. 4includes two receiving cores forming an output-side circuit and being provided in correspondence with each isolation transformer.

More specifically, the signal transmission device illustrated inFIG. 4include a receiving core34having an input terminal connected to RX1as an output-side isolation transformer terminal of the isolation transformer30, and a receiving core35having an input terminal connected to RX2as an output-side isolation transformer terminal of the isolation transformer30and on an opposite side to RX1.

The signal transmission device illustrated inFIG. 4further include a receiving core36having an input terminal connected to RX3as an output-side isolation transformer terminal of the isolation transformer32, and a receiving core37having an input terminal connected to RX4as an output-side isolation transformer terminal of the isolation transformer32and on an opposite side to RX3.

A reference potential of one receiving core is fixed to a potential at a terminal on an opposite side to a terminal to which the input terminal of this receiving core is connected. Specifically, a reference potential of a receiving core having an input terminal connected to RX1is fixed to a potential at RX2. A reference potential of a receiving core having an input terminal connected to RX3is fixed to a potential at RX4.

The signal transmission device illustrated inFIG. 4includes a signal conversion circuit38provided in a subsequent stage of the receiving core34and functioning to convert a received signal to a signal based on a GND (AGND) potential. The signal transmission device illustrated inFIG. 4includes a signal conversion circuit40provided in a subsequent stage of the receiving core36and functioning to convert a received signal to a signal based on a GND (AGND) potential.

The signal transmission device illustrated inFIG. 4includes a signal conversion circuit39provided in a subsequent stage of the receiving core35and functioning to convert a received signal to a signal based on a power supply (AVDD) potential. The signal transmission device illustrated inFIG. 4includes a signal conversion circuit41provided in a subsequent stage of the receiving core37and functioning to convert a received signal to a signal based on a power supply (AVDD) potential.

Outputs from the signal conversion circuits in a pair corresponding to one isolation transformer are synthesized by OR logic at a synthesis circuit43. Outputs from the synthesis circuits43, corresponding to demodulated signals obtained from the corresponding isolation transformers, are demodulated to produce a signal at an SR-flip-flop latch circuit42. As a result, an output signal (OUT) is generated.

<Configuration of Receiving Core>

FIG. 5illustrates the internal configuration of the receiving core in detail in the signal transmission device according to the first preferred embodiment.FIG. 5illustrates a circuit configuration connected to the isolation transformer30. A circuit configuration connected to the isolation transformer32is the same as the circuit configuration connected to the isolation transformer30, so that it is not illustrated inFIG. 5.

The receiving core34includes an N-type MOSFET400. The MOSFET400has a gate potential connected to RX2on an opposite side.

The receiving core35includes a P-type MOSFET401. The MOSFET401has a gate potential connected to RX1on an opposite side.

A current responsive to a potential difference between RX1and RX2flows in the MOSFET400. Meanwhile, the gate potential of the MOSFET400is connected to RX2on an opposite side to RX1to which the source potential of the MOSFET400is connected. Thus, a potential difference between the source and the gate of the MOSFET400is equal to a potential difference between RX1and RX2.

As a result, even if the dV/dt noise is caused to make a potential at each of RX1and RX2vary largely, a current output from the MOSFET400is still responsive to a potential difference between RX1and RX2. Specifically, even if the dV/dt noise is caused to make a potential at each of RX1and RX2vary largely, the MOSFET400still functions as a differential circuit that outputs a signal responsive to a potential difference between a source potential and a gate potential.

A current signal from the MOSFET400is output to a current amplifier404and is amplified as a current signal by the current amplifier404. Next, to be extracted as a signal based on a GND (AGND) potential, the amplified current signal is passed through a current-to-voltage conversion circuit405and is then output as a voltage signal.

A current responsive to a potential difference between RX1and RX2further flows in the MOSFET401. Meanwhile, the gate potential of the MOSFET401is connected to RX1on an opposite side to RX2to which the source potential of the MOSFET401is connected. Thus, a potential difference between the source and the gate of the MOSFET401is equal to a potential difference between RX1and RX2.

As a result, even if the dV/dt noise is caused to make a potential at each of RX1and RX2vary largely, a current output from the MOSFET401is also still responsive to a potential difference between RX1and RX2. Specifically, even if the dV/dt noise is caused to make a potential at each of RX1and RX2vary largely, the MOSFET401also still functions as a differential circuit that outputs a signal responsive to a potential difference between a source potential and a gate potential.

A current signal from the MOSFET401is output to a current amplifier407and is amplified as a current signal by the current amplifier407. Next, to be extracted as a signal based on a power supply (AVDD) potential, the amplified current signal is passed through a current-to-voltage conversion circuit408and is then output as a voltage signal.

<Detailed Configuration of Subsequent Stage of Receiving Core>

FIG. 6illustrates the internal configuration of a circuit in detail in a subsequent stage of the receiving core in the signal transmission device according to the first preferred embodiment.FIG. 6illustrates a circuit configuration connected to the isolation transformer30. A circuit configuration connected to the isolation transformer32is the same as the circuit configuration connected to the isolation transformer30, so that it is not illustrated inFIG. 6.

The current amplifier404connected to the receiving core34includes a current mirror circuit that amplifies a current signal output from the MOSFET400in a predetermined instance.

The current amplifier404includes a MOSFET409that flows a constant current420based on a GND potential, and a MOSFET411and a MOSFET412for transmitting a current signal output from the MOSFET400to the current-to-voltage conversion circuit405in a subsequent stage.

Likewise, the current amplifier407connected to the receiving core35is a circuit that amplifies a current signal output from the MOSFET401in a predetermined instance.

The current amplifier407includes a MOSFET410that flows a constant current421based on a power supply potential, and a MOSFET413and a MOSFET414for transmitting a current signal output from the MOSFET401to the current-to-voltage conversion circuit408in a subsequent stage.

First, a current flowing in the MOSFET401in the receiving core35is compared with the constant current421flowing in the MOSFET410.

If a potential difference is not generated between RX1and RX2so no current flows in the MOSFET401, only the constant current421flows in the MOSFET410. The MOSFET410generates a gate potential responsive to the constant current421.

Thus, a gate potential responsive to the constant current421flowing in the MOSFET410, which is about 1.5 V, for example, is applied to the MOSFET413. Then, the MOSFET413flows a current responsive to this gate potential.

A potential only of a value about 0.3 V, for example, is applied to the MOSFET414, so that the gate of the MOSFET414is OFF.

Meanwhile, if a potential difference is generated between RX1and RX2so a current flows in the MOSFET401, the constant current421also flows in the MOSFET410. The value of the current flowing in the MOSFET401is determined by the size of the MOSFET401and the value of a current excited by the isolation transformer.

In this case, a gate potential applied to the MOSFET413changes to about 1.2 V, for example, so as to follow potential change at RX2.

A gate potential responsive to the value of the current flowing in the MOSFET401is applied to the MOSFET414. Thus, a gate potential about 1.5 V, for example, is applied to the MOSFET414and this gate potential is larger than the gate potential applied to the MOSFET413.

As described above, in the presence of a current flowing in the MOSFET401, logic is inverted in the current-to-voltage conversion circuit408in a subsequent stage by the MOSFETs413and414.

A voltage signal is obtained as a result of demodulation by a folded current mirror provided in the current-to-voltage conversion circuit408and by the SR-flip-flop latch circuit42in a subsequent stage.

Likewise, in the presence of a current flowing in the MOSFET400in the receiving core34, logic is inverted in the current-to-voltage conversion circuit405in a subsequent stage by the MOSFETs411and412.

A voltage signal is obtained as a result of demodulation by a folded current mirror in the current-to-voltage conversion circuit405and by the SR-flip-flop latch circuit42in a subsequent stage.

FIG. 7is a sequence chart illustrating variations in potentials at isolation transformer terminals in an instance where a reference potential in the output-side circuit configuration varies positively, specifically, during +dV/dt.

FIG. 7illustrates the following in the order named: dV/dt; a potential (IN) of an input signal shown inFIG. 4; a potential (TX1) of an output signal from the demodulation circuit31shown inFIG. 4; a potential (TX2) of an output signal from the demodulation circuit33shown inFIG. 4; a potential (RX1) of a received signal at the receiving core34shown inFIG. 4; a potential (RX2) of a received signal at the receiving core35shown inFIG. 4; a potential (RX3) of a received signal at the receiving core36shown inFIG. 4; a potential (RX4) of a received signal at the receiving core37shown inFIG. 4; a potential of a output signal from each the receiving cores34and36(first receiving core output) shown inFIG. 4; a potential of an output signal from each of the receiving cores35and37(second receiving core output) shown inFIG. 4; and a potential (OUT) of an output signal from the SR-flip-flop latch circuit42shown inFIG. 4.

As illustrated inFIG. 7, in a period +dV/dt, due to the occurrence of the dV/dt noise, potential drop, more specifically, potential drop to a value near a GND potential of the output-side circuit configuration is observed at each of RX1, RX2, RX3, and RX4. In the period +dV/dt, a potential at each of RX3and RX4takes a value smaller than the GND potential.

Meanwhile, the gate potential of a MOSFET in the receiving core36is connected to RX4. Thus, even if the dV/dt noise is caused to make a potential at each of RX3and RX4vary largely, a current output from the MOSFET in the receiving core36is still responsive to a potential difference between RX3and RX4.

Likewise, the gate potential of a MOSFET in the receiving core37is connected to RX3. Thus, even if the dV/dt noise is caused to make a potential at each of RX3and RX4vary largely, a current output from the MOSFET in the receiving core37is still responsive to a potential difference between RX3and RX4.

Meanwhile, a current amplifier in a subsequent stage of the receiving core36is a circuit that flows a constant current based on a GND potential, so that this current amplifier does not operate in the period +dV/dt.

By obtaining a voltage signal by conversion from the aforementioned current signal, even if the dV/dt noise is caused to place a signal output from the isolation transformer at a voltage going out of an operable range of the circuit configuration, a voltage signal based on a potential difference between output-side terminals of the isolation transformer can still be received.

By using the aforementioned voltage signal, even in the period +dV/dt, a potential at each of RX3and RX4is still reflected in OUT.

FIG. 8is a sequence chart illustrating variations in potentials at the isolation transformer terminals in an instance where a reference potential in the output-side circuit configuration varies negatively, specifically, during −dV/dt.

FIG. 8illustrates the following in the order named: dV/dt; a potential (IN) of an input signal shown inFIG. 4; a potential (TX1) of an output signal from the demodulation circuit31shown inFIG. 4; a potential (TX2) of an output signal from the demodulation circuit33shown inFIG. 4; a potential (RX1) of a received signal at the receiving core34shown inFIG. 4; a potential (RX2) of a received signal at the receiving core35shown inFIG. 4; a potential (RX3) of a received signal at the receiving core36shown inFIG. 4; a potential (RX4) of a received signal at the receiving core37shown inFIG. 4; a potential of an output signal from each of the receiving cores34and36(first receiving core output) shown inFIG. 4; a potential of an output signal from each of the receiving cores35and37(second receiving core output) shown inFIG. 4; and a potential (OUT) of an output signal from the SR-flip-flop latch circuit42shown inFIG. 4.

As illustrated inFIG. 8, in a period −dV/dt, due to the occurrence of the dV/dt noise, potential increase, more specifically, potential increase to a value near a power supply potential of the output-side circuit configuration is observed at each of RX1, RX2, RX3, and RX4. In the period −dV/dt, a potential at each of RX1and RX2takes a value larger than the power supply potential.

Meanwhile, the gate potential of the MOSFET400in the receiving core34is connected to RX2. Thus, even if the dV/dt noise is caused to make a potential at each of RX1and RX2vary largely, a current output from the MOSFET400in the receiving core34is still responsive to a potential difference between RX1and RX2.

Likewise, the gate potential of the MOSFET401in the receiving core35is connected to RX1. Thus, even if the dV/dt noise is caused to make a potential at each of RX1and RX2vary largely, a current output from the MOSFET401in the receiving core35is still responsive to a potential difference between RX1and RX2.

Meanwhile, the current amplifier407in a subsequent stage of the receiving core35is a circuit that flows the constant current42based on a power supply potential, so that the current amplifier407does not operate in the period −dV/dt.

By obtaining a voltage signal by conversion from the aforementioned current signal, even if the dV/dt noise is caused to place a signal output from the isolation transformer at a voltage going out of an operable range of the circuit configuration, a voltage signal based on a potential difference between the output-side terminals of the isolation transformer can still be received.

By using the aforementioned voltage signal, even in the period −dV/dt, a potential at each of RX1and RX2is still reflected in OUT.

In the circuit configuration illustrated inFIGS. 4 to 6, in both the period +dV/dt and the period −dV/dt, at least one circuit operates to achieve signal transmission.

In the circuit configuration illustrated inFIGS. 4 to 6, in both the period +dV/dt and the period −dV/dt, a signal can be transmitted from the output-side circuit to the input-side circuit, specifically, a signal can be transmitted in the reverse direction.

In the circuit configuration illustrated inFIGS. 4 to 6, a pair of receiving cores is provided in correspondence with one isolation transformer. Alternatively, a circuit configuration may also be such that one receiving core is provided in correspondence with one isolation transformer, specifically, one transistor is provided having a source potential and a gate potential connected to one isolation transformer across RX1and RX2. Even with this circuit configuration, the signal transmission device is stilled allowed to operate under a particular situation. This will also apply to preferred embodiments described below.

Second Preferred Embodiment

A signal transmission device according to a second preferred embodiment will be described below. In the following description, structures comparable to those of the above-described preferred embodiment will be given the same signs, and where appropriate, description of such structures will be omitted.

<Configuration of Signal Transmission Device>

FIG. 9schematically illustrates the configuration of the signal transmission device according to the second preferred embodiment. The signal transmission device illustrated inFIG. 9has a double-ended circuit configuration using one transformer. This achieves size reduction in a circuit configuration.

The signal transmission device illustrated inFIG. 9includes a modulation circuit31that operates on an ON edge. The modulation circuit31functions as an input-side modulation circuit connected to a terminal portion of an isolation transformer50. The signal transmission device illustrated inFIG. 9includes a modulation circuit33that operates on an OFF edge. The modulation circuit33functions as an input-side modulation circuit connected to a terminal portion of the isolation transformer50.

The modulation circuits31and33are connected to the opposite terminal portions on the input side of the isolation transformer50.

The modulation circuit31includes a one-shot circuit300, a MOSFET301, and a MOSFET302.

The modulation circuit33includes a one-shot circuit303, a MOSFET304, and a MOSFET305.

The signal transmission device illustrated inFIG. 9includes an N-type MOSFET500and an N-type MOSFET501. The MOSFET500has a gate potential connected to RX1as an output-side isolation transformer terminal of the isolation transformer50. The MOSFET501has a gate potential connected to RX2as an output-side isolation transformer terminal of the isolation transformer50and on an opposite side to RX1.

The MOSFET500has a source potential connected to RX2on an opposite side. Likewise, the MOSFET501has a source potential connected to RX1on an opposite side.

The MOSFET500has a drain terminal connected to a power supply (AVDD) via a load502. In response to a voltage signal generated at the load502, a waveform shaping circuit503outputs a signal.

The MOSFET501has a drain terminal connected to a power supply (AVDD) via a load504. In response to a voltage signal generated at the load504, a waveform shaping circuit505outputs a signal.

The signal output from the waveform shaping circuit503and the signal output from the waveform shaping circuit505are processed by a signal processing logic506and a resultant output is demodulated to produce a signal at an SR-flip-flop latch circuit42. As a result, an output signal (OUT) is generated.

In the signal transmission device illustrated inFIG. 9, a current responsive to a potential difference between RX1and RX2flows in the MOSFET500. Meanwhile, the source potential of the MOSFET500is connected to RX2on an opposite side to RX1to which the gate potential of the MOSFET500is connected. Thus, a potential difference between the source and the gate of the MOSFET500is equal to a potential difference between RX1and RX2.

Likewise, a current responsive to a potential difference between RX1and RX2flows in the MOSFET501. Meanwhile, the source potential of the MOSFET501is connected to RX1on an opposite side to RX2to which the gate potential of the MOSFET501is connected. Thus, a potential difference between the source and the gate of the MOSFET501is equal to a potential difference between RX1and RX2.

As a result, even if dV/dt noise is caused to make a potential at each of RX1and RX2vary largely, a current output from the MOSFET500or501is still responsive to a potential difference between RX1and RX2.

If a potential difference is not generated between RX1and RX2, a gate potential is not applied to either of the MOSFETs500and501. Thus, the gate of each of the MOSFETs500and501is OFF.

Meanwhile, if a potential difference is generated between RX1and RX2to cause a current to flow from RX1to RX2, the gate of the MOSFET500becomes ON. By contrast, a negative bias is applied to the gate of the MOSFET501, so that the gate of the MOSFET501is OFF.

This operation also applies to an instance where the dV/dt noise is caused to make a potential at each of RX1and RX2vary largely.

If a potential difference is generated between RX1and RX2to cause a current to flow from RX2to RX1, the gate of the MOSFET501becomes ON. By contrast, a negative bias is applied to the gate of the MOSFET500, so that the gate of the MOSFET500is OFF.

This operation also applies to an instance where the dV/dt noise is caused to make a potential at each of RX1and RX2vary largely.

Even if a potential at a terminal portion of the isolation transformer50drops in the period +dV/dt, the aforementioned configuration makes it possible to apply a normal gate voltage to each of the MOSFETs500and501. This achieves signal transmission in the period +dV/dt.

FIG. 10schematically illustrates a part of the configuration of the signal transmission device according to the second preferred embodiment.

The signal transmission device illustrated inFIG. 10includes the N-type MOSFET500and the N-type MOSFET501. The MOSFET500has a gate potential connected to RX1on the output side of the isolation transformer50. The MOSFET501has a gate potential connected to RX2on the output side of the isolation transformer50.

The MOSFET500has a drain terminal connected to a power supply (AVDD) via a resistance load507. In response to a voltage signal generated at the resistance load507, the waveform shaping circuit503outputs a signal.

The MOSFET501has a drain terminal connected to a power supply (AVDD) via a resistance load508. In response to a voltage signal generated at the resistance load508, the waveform shaping circuit505outputs a signal.

Providing the resistance loads507and508makes it possible to reduce a circuit scale, while facilitating setting of a load.

FIG. 11schematically illustrates a part of the configuration of the signal transmission device according to the second preferred embodiment.

The signal transmission device illustrated inFIG. 11includes the N-type MOSFET500and the N-type MOSFET501. The MOSFET500has a gate potential connected to RX1on the output side of the isolation transformer50. The MOSFET501has a gate potential connected to RX2on the output side of the isolation transformer50.

The MOSFET500has a drain terminal connected to a power supply (AVDD) via a constant-current load509. In response to a voltage signal generated at the constant-current load509, the waveform shaping circuit503outputs a signal.

The MOSFET501has a drain terminal connected to a power supply (AVDD) via a constant-current load510. In response to a voltage signal generated at the constant-current load510, the waveform shaping circuit505outputs a signal.

Providing the constant-current loads509and510makes it possible to set a load independently of a power supply voltage.

FIG. 12schematically illustrates a part of the configuration of the signal transmission device according to the second preferred embodiment.

The signal transmission device illustrated inFIG. 12includes the N-type MOSFET500and the N-type MOSFET501. The MOSFET500has a gate potential connected to RX1on the output side of the isolation transformer50. The MOSFET501has a gate potential connected to RX2on the output side of the isolation transformer50.

The MOSFET500has a drain terminal connected to a power supply (AVDD) via a P-type MOSFET511. In response to a voltage signal generated at the P-type MOSFET511, the waveform shaping circuit503outputs a signal.

The MOSFET501has a drain terminal connected to a power supply (AVDD) via a P-type MOSFET512. In response to a voltage signal generated at the P-type MOSFET512, the waveform shaping circuit505outputs a signal.

Providing the P-type MOSFET511and the P-type MOSFET512produces a Hi-Z state while the N-type MOSFETs are ON, thereby reducing a load. Further, a load can be increased while the N-type MOSFETs are OFF. In this way, inputs to the waveform shaping circuits in subsequent stages can be given at higher speed.

Third Preferred Embodiment

A signal transmission device according to a third preferred embodiment will be described below. In the following description, structures comparable to those of the above-described preferred embodiments will be given the same signs, and where appropriate, description of such structures will be omitted.

<Configuration of Signal Transmission Device>

FIG. 13schematically illustrates the configuration of the signal transmission device according to the third preferred embodiment. The signal transmission device illustrated inFIG. 13has a double-ended circuit configuration using one transformer. This achieves size reduction in a circuit configuration.

The signal transmission device illustrated inFIG. 13includes a modulation circuit31that operates on an ON edge. The modulation circuit31functions as an input-side modulation circuit connected to a terminal portion of an isolation transformer50. The signal transmission device illustrated inFIG. 13includes a modulation circuit33that operates on an OFF edge. The modulation circuit33functions as an input-side modulation circuit connected to a terminal portion of the isolation transformer50.

The modulation circuits31and33are connected to the opposite terminal portions on the input side of the isolation transformer50.

The modulation circuit31includes a one-shot circuit300, a MOSFET301, and a MOSFET302.

The modulation circuit33includes a one-shot circuit303, a MOSFET304, and a MOSFET305.

The signal transmission device illustrated inFIG. 13includes a P-type MOSFET600and a P-type MOSFET601. The MOSFET600has a gate potential connected to RX1on the output side of the isolation transformer50. The MOSFET601has a gate potential connected to RX2on the output side of the isolation transformer50.

The MOSFET600has a source potential connected to RX2on an opposite side. Likewise, the MOSFET601has a source potential connected to RX1on an opposite side.

The MOSFET600has a drain terminal connected to GND (AGND) via a load602. In response to a voltage signal generated at the load602, a waveform shaping circuit503outputs a signal.

The MOSFET601has a drain terminal connected to GND (AGND) via a load604. In response to a voltage signal generated at the load604, a waveform shaping circuit505outputs a signal.

The signal output from the waveform shaping circuit503and the signal output from the waveform shaping circuit505are processed by a signal processing logic506and a resultant output is demodulated to produce a signal at an SR-flip-flop latch circuit42. As a result, an output signal (OUT) is generated.

In the signal transmission device illustrated inFIG. 13, a current responsive to a potential difference between RX1and RX2flows in the MOSFET600. Meanwhile, the source potential of the MOSFET600is connected to RX2on an opposite side to RX1to which the gate potential of the MOSFET600is connected. Thus, a potential difference between the source and the gate of the MOSFET600is equal to a potential difference between RX1and RX2.

Likewise, a current responsive to a potential difference between RX1and RX2flows in the MOSFET601. Meanwhile, the source potential of the MOSFET601is connected to RX1on an opposite side to RX2to which the gate potential of the MOSFET601is connected. Thus, a potential difference between the source and the gate of the MOSFET601is equal to a potential difference between RX1and RX2.

As a result, even if dV/dt noise is caused to make a potential at each of RX1and RX2vary largely, a current output from the MOSFET600or601is still responsive to a potential difference between RX1and RX2.

Even if a potential at a terminal portion of the isolation transformer50is increased in the period −dV/dt, the aforementioned configuration makes it possible to apply a normal gate voltage to each of the MOSFETs600and601. This achieves signal transmission in the period −dV/dt.

FIG. 14schematically illustrates a part of the configuration of the signal transmission device according to the third preferred embodiment.

The signal transmission device illustrated inFIG. 14includes the P-type MOSFET600and the P-type MOSFET601. The MOSFET600has a gate potential connected to RX1on the output side of the isolation transformer50. The MOSFET601has a gate potential connected to RX2on the output side of the isolation transformer50.

The MOSFET600has a drain terminal connected to GND (AGND) via a resistance load607. In response to a voltage signal generated at the resistance load607, the waveform shaping circuit503outputs a signal.

The MOSFET601has a drain terminal connected to GND (AGND) via a resistance load608. In response to a voltage signal generated at the resistance load608, the waveform shaping circuit505outputs a signal.

Providing the resistance loads607and608makes it possible to reduce a circuit scale, while facilitating setting of a load.

FIG. 15schematically illustrates a part of the configuration of the signal transmission device according to the third preferred embodiment.

The signal transmission device illustrated inFIG. 15includes the P-type MOSFET600and the P-type MOSFET601. The MOSFET600has a gate potential connected to RX1on the output side of the isolation transformer50. The MOSFET601has a gate potential connected to RX2on the output side of the isolation transformer50.

The MOSFET600has a drain terminal connected to GND (AGND) via a constant-current load609. In response to a voltage signal generated at the constant-current load609, the waveform shaping circuit503outputs a signal.

The MOSFET601has a drain terminal connected to GND (AGND) via a constant-current load610. In response to a voltage signal generated at the constant-current load610, the waveform shaping circuit505outputs a signal.

Providing the constant-current loads609and610makes it possible to set a load independently of a power supply voltage.

FIG. 16schematically illustrates a part of the configuration of the signal transmission device according to the third preferred embodiment.

The signal transmission device illustrated inFIG. 16includes the P-type MOSFET600and the P-type MOSFET601. The MOSFET600has a gate potential connected to RX1on the output side of the isolation transformer50. The MOSFET601has a gate potential connected to RX2on the output side of the isolation transformer50.

The MOSFET600has a drain terminal connected to GND (AGND) via an N-type MOSFET611. In response to a voltage signal generated at the N-type MOSFET611, the waveform shaping circuit503outputs a signal.

The MOSFET601has a drain terminal connected to GND (AGND) via an N-type MOSFET612. In response to a voltage signal generated at the N-type MOSFET612, the waveform shaping circuit505outputs a signal.

Providing the N-type MOSFET611and the N-type MOSFET612produces a Hi-Z state while the P-type MOSFETs are ON, thereby reducing a load. Further, a load can be increased while the P-type MOSFETs are OFF. In this way, inputs to the waveform shaping circuits in subsequent stages can be given at higher speed.

Fourth Preferred Embodiment

A signal transmission device and a power switching element driving device according to a fourth preferred embodiment will be described below. In the following description, structures comparable to those of the above-described preferred embodiments will be given the same signs, and where appropriate, description of such structures will be omitted.

FIG. 17illustrates a circuit configuration to which a signal transmission device100according to the above-described preferred embodiments is applied.

As illustrated inFIG. 17, a gate driver101is connected to the signal transmission device100. The gate driver101has an output terminal to which a power switching element1000is connected.

More specifically, the power switching element1000includes an insulated gate bipolar transistor, specifically, an IGBT102, and a free-wheeling diode, specifically, an FWD103.

The IGBT102has a gate potential connected to the output terminal of the gate driver101. The FWD103is connected to the IGBT102across the collector potential and the emitter potential of the IGBT102.

This circuit configuration is usable for high-speed communication required for signal transmission in a P-side element driver circuit section to make signal communication between different power supplies, or required for application to real time control (RTC).

Such high-speed communication is assumed to cause high-speed and large potential variations in an output-side circuit configuration. Hence, the occurrence of dV/dt noise is considered to result in output of a voltage signal going out of an operable range of the output-side circuit configuration. The aforementioned circuit configuration is particularly useful in such an instance.

This circuit configuration is usable as information communication means employing A/D conversion instead of using a pulse width modulation (specifically, a PWM) signal.

Fifth Preferred Embodiment

A signal transmission device and a power switching element driving device according to a fifth preferred embodiment will be described below. In the following description, structures comparable to those of the above-described preferred embodiments will be given the same signs, and where appropriate, description of such structures will be omitted.

FIG. 18illustrates a circuit configuration to which the signal transmission device100according to the above-described preferred embodiments is applied.

As illustrated inFIG. 18, a gate driver101is connected to the signal transmission device100. The gate driver101has an output terminal to which a power switching element1001is connected.

More specifically, the power switching element1001includes an SiC-metal-oxide-semiconductor field-effect transistor (specifically, an SiC-MOSFET)104, and a Schottky barrier diode (specifically, an SBD)105.

The SiC-MOSFET104has a gate potential connected to the output terminal of the gate driver101. The SBD105is connected to the SiC-MOSFET104across the drain potential and the source potential of the SiC-MOSFET104.

This circuit configuration is usable for high-speed communication required for signal transmission in a P-side element driver circuit section to make signal communication between different power supplies, or required for application to RTC. Further, this circuit configuration is usable as information communication means employing A/D conversion instead of using a PWM signal.

Effects achieved by the above-described preferred embodiments will be described next. The effects described below are achieved by the specific structures illustrated in the above-described preferred embodiments. However, as long as comparable effects are to be achieved, these particular structures can be replaced by different particular structures illustrated in the specification of the present application.

This replacement can be made across two or more of the preferred embodiments. Specifically, structures illustrated different preferred embodiments can be combined, as long as such a combination achieves a comparable effect.

According to the above-described preferred embodiments, the signal transmission device includes the isolation transformer30, the input-side circuit connected to the input side of the isolation transformer30, and the output-side circuit connected to the output side of the isolation transformer30. The output-side circuit is connected to a first terminal (RX1) and a second terminal (RX2). The first terminal is on the output side of the isolation transformer30. The second terminal is on the output side of the isolation transformer30and on an opposite side to RX1. The output-side circuit includes a first differential circuit. The first differential circuit corresponds to at least one of the receiving cores34and35, and at least one of the receiving cores36and37, for example. The receiving core34has a first input and a second input connected to RX1and RX2respectively. The receiving core34outputs a signal responsive to a potential difference between the first input and the second input. A reference potential of the receiving core34is connected to RX2.

According to the aforementioned configuration, even if the dV/dt noise is caused to place a signal at a voltage going out of an operable range of the circuit, the signal can still be transmitted. More specifically, as a result of the connection of a reference potential of the receiving core34to RX2, even if the dV/dt noise is caused to make a potential at each of RX1and RX2vary largely, a current responsive to a potential difference between RX1and RX2still flows in the receiving core34. Thus, even if a signal is placed at a voltage going out of an operable range of the circuit in a period when the dV/dt noise is caused, this signal can still be received as a signal at a voltage falling within the operable range of the circuit.

The structures other than the aforementioned structures illustrated in the specification of the present application can be omitted, where appropriate. Specifically, the aforementioned structures can alone achieve the above-described effects.

However, the above-described effects can also be achieved by adding at least one of the other structures illustrated in the specification of the present application to the aforementioned structures appropriately, specifically, by adding the structures except for the aforementioned structures and illustrated in the specification of the present application to the aforementioned structures.

According to the above-described preferred embodiments, the receiving core34is a transistor having a reference potential connected to RX2. With this configuration, the gate potential of the MOSFET400is connected to RX2. Thus, even if the dV/dt noise is caused to make a potential at each of RX1and RX2vary largely, a current responsive to a potential difference between RX1and RX2still flows in the MOSFET400. Thus, even if a signal is placed at a voltage going out of an operable range of the circuit in a period when the dV/dt noise is caused, this signal can still be received as a signal at a voltage falling within the operable range of the circuit.

According to the above-described preferred embodiments, the first differential circuit is the N-type MOSFET501having a source potential connected to RX1and a gate potential connected to RX2. The output-side circuit includes the load504connected between a power supply potential and the drain potential of the MOSFET501. With this configuration, an operable range of the N-type MOSFET is not limited with respect to +dV/dt. Further, a signal can be transmitted in the period +dV/dt.

According to the above-described preferred embodiments, a load is the resistance load508. This configuration facilitates setting of a load. This configuration can also reduce a circuit scale.

According to the above-described preferred embodiments, a load is the constant-current load510. This configuration achieves setting of a load independently of variations in a power supply.

According to the above-described preferred embodiments, a load is the P-type MOSFET512. This configuration produces a high-impedance (Hi-Z) state while the N-type MOSFET is ON, while producing a low-impedance (Lo-Z) state while the N-type MOSFET is OFF. This increases the operating speed of the signal transmission device.

According to the above-described preferred embodiments, the first differential circuit is the P-type MOSFET601having a source potential connected to RX1and a gate potential connected to RX2. The output-side circuit includes the load604connected between a GND potential and the drain potential of the MOSFET601. With this configuration, an operable range of the P-type MOSFET is not limited with respect to −dV/dt. Further, a signal can be transmitted in the period −dV/dt.

According to the above-described preferred embodiments, a load is the resistance load608. This configuration facilitates setting of a load. This configuration can also reduce a circuit scale.

According to the above-described preferred embodiments, a load is the constant-current load610. This configuration achieves setting of a load independently of variations in a power supply.

According to the above-described preferred embodiments, a load is the N-type MOSFET612. This configuration produces a Hi-Z state while the P-type MOSFET is ON, while producing a Lo-Z state while the P-type MOSFET is OFF. This increases the operating speed of the signal transmission device.

According to the above-described preferred embodiments, the output-side circuit includes a first signal conversion circuit. The first signal conversion circuit corresponds to at least one of the signal conversion circuits38and39, and at least one of the signal conversion circuits40and41, for example. The signal conversion circuit38is connected to the receiving core34and converts an output signal from the receiving core34to a voltage signal based on a GND potential. The signal conversion circuit39is connected to the receiving core35and converts an output signal from the receiving core35to a voltage signal based on a power supply potential. With this configuration, a current signal output from the receiving core can be converted to a voltage signal. Even if a potential at each of RX1and RX2increases in the period −dV/dt, converting an output signal to a voltage signal based on a GND potential still makes it possible to transmit a voltage signal responsive to a potential difference between RX1and RX2. Further, even if a potential at each of RX1and RX2drops in the period +dV/dt, converting an output signal to a voltage signal based on a power supply potential still makes it possible to transmit a voltage signal responsive to a potential difference between RX1and RX2.

According to the above-described preferred embodiments, the signal conversion circuit38includes an amplifier circuit and a voltage conversion circuit. The amplifier circuit corresponds to the current amplifier404, for example. The voltage conversion circuit corresponds to the current-to-voltage conversion circuit405, for example. The current amplifier404amplifies an output signal from the receiving core34. The current-to-voltage conversion circuit405converts the amplified output signal from the receiving core34to a voltage signal. With this configuration, if an output signal from the receiving core34is smaller than a predetermined value, this output signal can be amplified and the resultant amplified signal can be converted to a voltage signal.

According to the above-described preferred embodiments, the current amplifier404includes the current mirror circuit. A current can be amplified by such a simple configuration.

According to the above-described preferred embodiments, the current-to-voltage conversion circuit405includes a current mirror latch circuit. A current can be converted to a voltage by such a simple configuration.

According to the above-described preferred embodiments, the output-side circuit includes a second differential circuit. If the first differential circuit is the receiving core34, the second differential circuit corresponds to the receiving core35, for example. If the first differential circuit is the receiving core35, the second differential circuit corresponds to the receiving core34, for example. If the first differential circuit is the receiving core36, the second differential circuit corresponds to the receiving core37, for example. If the first differential circuit is the receiving core37, the second differential circuit corresponds to the receiving core36, for example. The receiving core35has a third input and a fourth input connected to RX2and RX1respectively. The receiving core35outputs a signal responsive to a potential difference between the third input and the fourth input. A reference potential of the receiving core35is connected to RX1. With this configuration, both the differential circuit achieving signal transmission in the period +dV/dt and the differential circuit achieving signal transmission in the period −dV/dt can be provided at the same time. In the double-ended circuit configuration illustrated inFIG. 9using one transformer, for example, both the differential circuit corresponding to a current flow direction from RX1to RX2and the differential circuit corresponding to a current flow direction from RX2to RX1can be provided at the same time. With this configuration, while a signal is to be transmitted from the output-side circuit to the input-side circuit with respect to the isolation transformer, both the differential circuit achieving signal transmission in the period +dV/dt and the differential circuit achieving signal transmission in the period −dV/dt can be provided at the same time.

According to the above-described preferred embodiments, the receiving core35is a transistor having a reference potential connected to RX1. With this configuration, the gate potential of the MOSFET401is connected to RX1. Thus, even if the dV/dt noise is caused to make a potential at each of RX1and RX2vary largely, a current responsive to a potential difference between RX1and RX2still flows in the MOSFET401. Thus, even if a signal is placed at a voltage going out of an operable range of the circuit in a period when the dV/dt noise is caused, this signal can still be received as a signal at a voltage falling within the operable range of the circuit.

According to the above-described preferred embodiments, the output-side circuit includes a second signal conversion circuit. If the first signal conversion circuit is the signal conversion circuit38, the second signal conversion circuit corresponds to the signal conversion circuit39, for example. If the first signal conversion circuit is the signal conversion circuit39, the second signal conversion circuit corresponds to the signal conversion circuit38, for example. If the first signal conversion circuit is the signal conversion circuit40, the second signal conversion circuit corresponds to the signal conversion circuit41, for example. If the first signal conversion circuit is the signal conversion circuit41, the second signal conversion circuit corresponds to the signal conversion circuit40, for example. The signal conversion circuit38is connected to the receiving core34and converts an output signal from the receiving core34to a voltage signal based on a GND potential. The signal conversion circuit39is connected to the receiving core35and converts an output signal from the receiving core35to a voltage signal based on a power supply potential. With this configuration, a current signal output from the receiving core35can be converted to a voltage signal. Even if a potential at each of RX1and RX2increases in the period −dV/dt, converting an output signal to a voltage signal based on a GND potential still makes it possible to transmit a voltage signal responsive to a potential difference between RX1and RX2. Further, even if a potential at each of RX1and RX2drops in the period +dV/dt, converting an output signal to a voltage signal based on a power supply potential still makes it possible to transmit a voltage signal responsive to a potential difference between RX1and RX2.

According to the above-described preferred embodiments, if the signal conversion circuits38and39are circuits that generate voltage signals by conversion based on different potentials, the output-side circuit includes the synthesis circuit43and an output circuit. The output circuit corresponds to the SR-flip-flop latch circuit42, for example. The synthesis circuit43synthesizes an output signal from the receiving core34and an output signal from the receiving core35by OR logic. The SR-flip-flop latch circuit42processes an output from the synthesis circuit43and outputs a result as a set signal or a reset signal. With this configuration, in each of the periods +dV/dt and −dV/dt, a set signal or a reset signal can be output by transmitting a signal via the isolation transformer.

According to the above-described preferred embodiments, the power switching element driving device includes the signal transmission device100, the gate driver101connected to the signal transmission device100, and the power switching element1000connected to the output terminal of the gate driver101. With this configuration, even if the dV/dt noise is caused while a semiconductor switching element operates, a signal can still be transmitted. This configuration can eliminate the need for watchdog in the output-side circuit or need for continuous pulse transmission from the input-side circuit. In this way, a circuit scale can be reduced.

According to the above-described preferred embodiments, the power switching element1000includes the insulated gate bipolar transistor102having a gate potential connected to the output terminal of the gate driver101, and the free-wheeling diode103connected to the insulated gate bipolar transistor102across the collector potential and the emitter potential of the insulated gate bipolar transistor102. With this configuration, even if the dV/dt noise is caused while the semiconductor switching element having an inverter configuration using the IGBT and the FWD operates, a signal can still be transmitted.

According to the above-described preferred embodiments, the power switching element1001includes the SiC-MOSFET104having a gate potential connected to the output terminal of the gate driver101, and the Schottky barrier diode105connected to the SiC-MOSFET104across the drain potential and the source potential of the SiC-MOSFET104. With this configuration, even if the dV/dt noise is caused while the semiconductor switching element having an inverter configuration using the MOSFET and the SBD operates, a signal can still be transmitted.

According to the above-described preferred embodiments, the power switching element1001is formed by using an SiC material. With this configuration, high-speed and high-temperature operation can be achieved by utilizing the characteristics of SiC.

Modifications of Above-Described Preferred Embodiments

In the above-described preferred embodiments, each component may be described in terms of a viewpoint such as properties, material, dimension, shape, arrangement relative to a different component, or a condition for implementation, etc. However, these viewpoints described in the specification of the present application are in all aspects illustrative and not restrictive.

Thus, numerous modifications and equivalents not illustrated are assumed to be included within the technical scope disclosed in the specification of the present application. These modifications and equivalents include modification, addition, or omission of at least one component, and extraction of at least one component from at least one of the preferred embodiments and combination of the extracted component with a component in a different preferred embodiment, for example.

As long as no contradiction is to occur, a component described in a “singular form” in the preferred embodiments may include “one or more” such components.

Each component in the above-described preferred embodiments is a conceptual unit. The technical scope disclosed in the specification of the present application includes an instance where one component is formed of a plurality of structures, an instance where one component corresponds to a part of some structure, and an instance where a plurality of components is provided in one structure.

Each component in the above-described preferred embodiments includes a structure having a different configuration or a different shape, as long as such a component fulfills the same function.

The description given in the specification of the present application should in all aspects be referred to for all purposes relating to the technique disclosed in the specification of the present application and should never be recognized as a background art.

Where the name of a material is given without any particular designation in the above-described preferred embodiments, for example, as long as no contradiction is to occur, this material covers a material with an additive such as an alloy.

Each component in the above-described preferred embodiments is assumed to function both as software or firmware, and as corresponding hardware. Each component falling in both of these concepts is called a “unit” or a “processing circuit,” for example.

The technique disclosed in the specification of the present application can also be implemented if each component in the above-described preferred embodiments is provided in a distributed manner in a plurality of devices. Specifically, the technique disclosed in the specification of the present application can be implemented in a form such as a system.