SEMICONDUCTOR ATTENUATED FINS

A semiconductor device includes a semiconductor substrate and attenuated semiconductor fins (e.g. FinFET fins) that include an outer portion that is a composite of a first material and a second material, an inner portion that is the second material, and an attenuation portion that is an attenuated composite of the first and second materials. The attenuation portion may be formed by diffusing the first material into a plurality of fins made of the second material. The attenuated composite attenuates from a first composite to a second composite, the first composite comprising a majority of the first material, the second composite comprising a majority of the second material. The outer portion may be located on the fin perimeter and the inner portion may be located central to the fin. The first material may be Germanium, the second material may be Silicon, and the attenuated composite may be attenuated Silicon Germanium.

FIELD OF THE INVENTION

Embodiments of invention generally relate to semiconductors and the fabrication of semiconductor device components, such as FinFETs, and more particularly to the formation and structure of attenuated fins.

DESCRIPTION OF THE RELATED ART

While multi-gate, tri-gate architectures, etc., generically known as FinFET technology, deliver superior levels of scalability, semiconductor engineers face challenges in creating devices that optimize the promise of FinFETs.

Design metrics including power, performance, cost, area, and time to market have posed challenges since the inception of the semiconductor integrated circuit industry. However, as process technologies continue to shrink, it becomes increasingly challenging to achieve a similar scaling of certain device parameters, particularly the supply voltage. Additionally, optimizing for one variable such as performance typically results in unwanted compromises in other areas, like power. However, utilizing FinFETs, as compared to planar technology, results in much better performance at the same power budget, or equal performance at a much lower power budget. A particular challenge, as feature size has become smaller, is high leakage current due to short-channel effects and varying dopant levels. Though typical FinFETs generally improve short-channel effects significant challenges exist.

SUMMARY OF THE INVENTION

Embodiments of invention generally relate to semiconductors and the fabrication of semiconductor device components, such as FinFETs, and more particularly to the formation and structure of attenuated fins.

In a first embodiment, a method of fabricating a semiconductor device includes providing a semiconductor substrate and forming attenuated fins upon the substrate. The attenuated fins include an outer portion that is a composite of a first material and a second material, an inner portion that is a second material, and an attenuation portion that is an attenuated composite of the first material and the second material. In certain embodiments, forming attenuated fins upon the substrate further includes depositing the first material onto the substrate surrounding a plurality of fins that are made of the second material and diffusing the first material into the plurality of fins. In certain embodiments, the first material is Germanium (Ge), the second material is Silicon (Si), and the attenuated composite is attenuated SiGe.

In another embodiment, a semiconductor device includes the silicon substrate and the plurality of attenuated fins upon the substrate. In certain embodiments, the attenuated composite attenuates, varies, gradually varies, or otherwise changes from a first composite to a second composite. The first composite includes a majority of the first material and the second composite includes a majority of the second material. The first composite is generally nearest the outer portion and the second composite being nearest the inner portion. In certain embodiments, the outer portion is located on the fin perimeter and the inner portion is located central to the fin.

In another embodiment, a design structure embodied in a machine readable storage medium for designing, manufacturing, or testing an integrated circuit includes the silicon substrate and the plurality of attenuated fins upon the substrate.

These and other features, aspects, and advantages will become better understood with reference to the following description, appended claims, and accompanying drawings.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Detailed embodiments of the claimed structures and methods are disclosed herein; however, it can be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods that may be embodied in various forms. These exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this invention to those skilled in the art. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

Embodiments of invention generally relate to the fabrication of FinFET devices, and more particularly to the formation and structure of attenuated fins. A FinFET device may include a plurality of fins formed in a wafer and a gate covering a portion of the fins. A portion of the fins may be covered by the gate and serves as a channel region of the device. A portion of the fins may extend out from under the gate and may serve as source and drain regions of the device. Typical integrated circuits may be divided into active areas and non-active areas. The active areas may include FinFET devices. Each active area may have a different pattern density, or a different number of FinFET devices.

Specific embodiments described herein relate to SiGe Fins. SiGe fins may be preferable in certain implementation since requisite threshold voltages in systems with SiGe fins may be lower relative to systems with Si Fins. Lower threshold voltages lead to, for example, lower turn on voltage, lower energy consumption. etc. SiGe fins may further be preferable since mobility is higher in systems that utilize SiGe Fins relative to systems that utilize Si Fins.

Referring now to FIGS., exemplary process steps of forming a structure100in accordance with embodiments of the present invention are shown, and will now be described in greater detail below. It should be noted that some of the FIGS. depict a cross section view of structure100having a plurality of fins formed in a semiconductor substrate or bulk. Furthermore, it should be noted that while this description may refer to some components of the structure100in the singular tense, more than one component may be depicted throughout the figures and like components are labeled with like numerals. The particular cross section view orientation and specific number of fins depicted in the figures were chosen for illustrative purposes only.

Referring now toFIG. 1, a cross section view of structure100is shown at an intermediate step during a process flow. At this step of fabrication, structure100may generally include a plurality of fins104etched upon substrate101that has a cap layer106thereon.

The semiconductor substrate101may include a bulk semiconductor or a layered semiconductor such as Si/SiGe, a silicon-on-insulator (SOI), or a SiGe-on-insulator (SGOI). Bulk semiconductor substrate materials may include undoped Si, n-doped Si, p-doped Si, single crystal Si, polycrystalline Si, amorphous Si, Ge, SiGe, SiC, SiGeC, GaAs, InP and all other III/V or II/VI compound semiconductors. In the embodiment shown inFIG. 1a SOI substrate is depicted, however for the purposes of clarity, the various embodiments of the present invention may be applied utilizing a bulk substrate. The SOI substrate may include a base substrate108, a buried dielectric layer102formed on top of the base substrate108, and a SOI layer (not shown) formed on top of the buried dielectric layer102. The buried dielectric layer102may isolate the SOI layer from the base substrate108. The plurality of fins104may be etched from the SOI layer.

The base substrate108may be any of several known semiconductor materials such as, for example, silicon, germanium, silicon-germanium alloy, silicon carbide, silicon-germanium carbide alloy, and compound (e.g. III-V and II-VI) semiconductor materials. Non-limiting examples of compound semiconductor materials include gallium arsenide, indium arsenide, and indium phosphide. Typically the base substrate108may be about, but is not limited to, several hundred microns thick. For example, the base substrate108may have a thickness ranging from 0.5 mm to about 1.5 mm.

The buried dielectric layer102may include any of several dielectric materials, for example, oxides, nitrides and oxynitrides of silicon. The buried dielectric layer102may also include oxides, nitrides and oxynitrides of elements other than silicon. In addition, the buried dielectric layer102may include crystalline or non-crystalline dielectric material. Moreover, the buried dielectric layer102may be formed using any of several known methods, for example, thermal or plasma oxidation or nitridation methods, chemical vapor deposition methods, and physical vapor deposition methods. The buried dielectric layer102may have a thickness ranging from about 5 nm to about 200 nm.

The SOI layer may include any of the several semiconductor materials included in the base substrate108. In general, the base substrate108and the SOI layer may include either identical or different semiconducting materials with respect to chemical composition, dopant concentration and crystallographic orientation. In particular embodiments described herein, the base substrate108and the SOI layer include semiconducting materials that include at least different crystallographic orientations. The SOI layer may include a thickness ranging from about 5 nm to about 100 nm. Methods for forming the SOI layer are well known in the art. Non-limiting examples include SIMOX (Separation by Implantation of Oxygen), wafer bonding, and ELTRAN® (Epitaxial Layer TRANsfer). It may be understood by a person having ordinary skill in the art that the plurality of fins104may be etched from the SOI layer. Because the plurality of fins104may be etched from the SOI layer, they too may include any of the characteristics listed above for the SOI layer.

For clarity, when substrate101is a bulk substrate, the plurality of fins104may formed on the bulk substrate using known processes (e.g. etch fins, oxide fill, recess oxide, etc.).

The cap layer106may include any suitable insulating material such as, for example, silicon nitride. The cap layer106may be formed using known conventional deposition techniques, for example, low-pressure chemical vapor deposition (LPCVD). Cap layer106may be deposited upon the fin layer prior to fin formation as blanket layer. In one embodiment, the cap layer106may have a thickness ranging from about 5 nm to about 100 nm.

Referring now toFIG. 2, a cross section view of structure100is shown at an intermediate step during a process flow. At this step of fabrication, amorphous germanium (α-Ge)120is formed upon structure100, according to various embodiments of the present invention, though polycrystalline Ge (poly-Ge), selective epitaxial Ge, may be also used. Generally, α-Ge120may be formed by process that grows, coats, or otherwise transfers α-Ge120onto semiconductor structure100. For example, α-Ge120may be formed by applicable physical vapor deposition (PVD), CVD, electrochemical deposition (ECD), molecular beam epitaxy (MBE), or (ALD) techniques. At this stage of fabrication, α-Ge120is formed to a thickness to be coplanar with the top of the fins, or alternatively to be coplanar with the top of the upper surface of cap106.

Polycrystalline or epitaxial Ge can be deposited by an epitaxial growth process that are, e.g., rapid thermal chemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD) and molecular beam epitaxy (MBE). The temperature for epitaxial deposition process for forming the germanium layer ranges from 300° C. to 600° C. A polycrystalline or epitaxial germanium layer can be deposited from a germanium gas source that is selected from the group consisting of germane, digermane, halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane and combinations thereof.

Referring now toFIG. 3, a detailed cross section view of structure100is shown at an intermediate step during a process flow. At this step of fabrication, semiconductor structure100is annealed, according to various embodiments of the present invention. More specifically, at this stage of fabrication, known techniques are utilized to force Germanium to diffuse into the Si material of fins104, thereby creating attenuated fins140, accordingly to various embodiments of the present invention. Such known techniques may be heating semiconductor structure100to a exemplary temperature of 950° C., 960° C., etc., melting annealing, furnace annealing, rapid thermal annealing (RTA), Rapid Thermal Processing (RTP), non-melt anneal process completed in Epitaxy tool, etc. Utilizing such processes will typically change α-Ge120to polycrystalline germanium (poly-Ge)130. Generally, other known techniques may be utilized to force the material surrounding fins104to diffuse into the material of fins104.

Referring now toFIG. 4, a partial detailed cross section view of a attenuated fin140is shown, according to various embodiments of the present invention. Generally, attenuated fins140include an outer portion150, inner portion160, and an attenuated portion170.

The outer portion150is the outermost portion of fin140and generally results from the forced diffusion of the material surrounding fins104into fins104. Outer portion150is a compound material has the highest concentration of the material surrounding fins104. For example, outer portion150may be 80% SiGe (i.e. SiGe with 80% Germanium concentration).

Inner portion160is the innermost portion of fin150. Generally, inner portion160is the locations of fin140where the material surrounding fins104did not diffuse. As such, inner portion160generally includes only the original material of fins104. Therefore, for example, inner portion160includes only Silicon.

Attenuated portion170generally includes an attenuated composite of a first material and a second material. The composite of the first material and second material generally results from the diffusion profile of the material surrounding fins104diffusing into fins104. In certain embodiments, the attenuated composite is a graded, variable, or otherwise attenuated composite that is similar to the composition of outer portion150nearest outer portion150and attenuates to the composition of inner portion160nearest the inner portion160. Therefore, for example, an attenuated portion170may be 100% Silicon nearest inner portion160and may be SiGe (80% Ge) nearest outer portion150with an attenuation from SiGe (e.g. 99.9% Si) near inner portion160to SiGe (e.g. 79.9% Ge) near outer portion150there between. In certain embodiments, attenuated portion170includes only the attenuated composition and not the compositions similar to outer portion150and inner portion160. For clarity, it is noted that the outer SiGe concentration may be higher or lower than the exemplary 80% depending on diffusion conditions (e.g. anneal temperature, duration, etc.).

In certain embodiments, attenuated fin140generally includes a vertical outer channel along the perimeter formed by outer portion150and a vertical inner channel in the interior formed by inner portion150. Therefore, the outer portion150, inner portion160, and attenuated portion170may have a substantially vertical orientation (i.e. height is greater than width).

Referring now toFIG. 5, a cross section view of structure100is shown at an intermediate step during a process flow. At this step of fabrication, cap layer106is removed, according to various embodiments of the present invention. Generally, cap layer106may be removed by any known techniques. For example, cap layer106may be removed by an etch processes (wet etch, dry etch, etc.). Other such techniques may be utilized to remove cap layer106without departing from the scope of the embodiments herein claimed.

Referring now toFIG. 6, a cross section view of structure100is shown at an intermediate step during a process flow. At this step of fabrication, poly-Ge130is removed thereby exposing attenuated fins140, according to various embodiments of the present invention. Generally, poly-Ge130may be removed by any known techniques. For example, poly-Ge130may be removed by an etch processes (wet etch, dry etch, etc.). In certain embodiments, poly-Ge130is etched selectively thereby leaving attenuated fins140. Since attenuated fins have outer portion150comprising e.g. SiGe (80% Ge) there is an adequate percentage of non-Ge, that an etchant may selectively remove the surrounding poly-Ge130but leave attenuated fins140. Other such techniques may be utilized to remove poly-Ge130without departing from the scope of the embodiments herein claimed. In certain embodiments, the cap layer106and poly-Ge130may be removed at the same stage of fabrication.

Though no further fabrication stages are depicted, it is to be understood that semiconductor structure100may undergo further fabrication processes to form a semiconductor device. For example, semiconductor structure100may undergo subsequent Front End of the Line stages, Middle of Line stages, and Back of the Line stages, etc.

Referring now toFIG. 7, a cross section view of structure100is shown at an intermediate step during a process flow.FIG. 7depicts structure100at a similar stage of fabrication relative toFIG. 1. However, in the present alternate embodiment, structure100does not include cap layer106. Therefore, for example, structure100may generally include the plurality of fins104etched upon substrate101. As seen in further fabrication stages, the absence of cap layer106generally allows a multi dimensional diffusion profile of the material surrounding fins104diffusing into fins104.

Referring now toFIG. 8, a cross section view of structure100is shown at an intermediate step during a process flow. At this step of fabrication, amorphous germanium (α-Ge)120is formed upon structure100, according to various embodiments of the present invention, though polycrystalline Ge (poly-Ge), selective epitaxial Ge may alternatively be used. Generally, α-Ge120may be formed by process that grows, coats, or otherwise transfers α-Ge120onto semiconductor structure100. For example, α-Ge120may be formed by applicable physical vapor deposition (PVD), CVD, electrochemical deposition (ECD), molecular beam epitaxy (MBE), or (ALD) techniques. At this stage of fabrication, α-Ge120is formed to a thickness greater than the height of fins104.

Polycrystalline or epitaxial Ge can be deposited by an epitaxial growth process apparatuses that are, e.g., rapid thermal chemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD) and molecular beam epitaxy (MBE). The temperature for epitaxial deposition process for forming the germanium layer ranges from 300° C. to 600° C. A polycrystalline or epitaxial germanium layer can be deposited from a germanium gas source that is selected from the group consisting of germane, digermane, halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane and combinations thereof.

Referring now toFIG. 9, a detailed cross section view of structure100is shown at an intermediate step during a process flow. At this step of fabrication, semiconductor structure100may be annealed, according to various embodiments of the present invention. More generally, at this stage of fabrication, known techniques are utilized to force Germanium to diffuse into the Si material of fins104thereby creating multi dimensional attenuated fins200accordingly to various embodiments of the present invention. Such known techniques may be heating semiconductor structure100to a exemplary temperature of 950° C., 950° C., etc., melt annealing, furnace annealing, rapid thermal annealing (RTA), Rapid Thermal Processing (RTP), non-melt anneal process completed in Epitaxy tool, etc. Utilizing such processes will typically change α-Ge120to poly-Ge130. Generally, other known techniques may be utilized to force the material surrounding fins104to diffuse into the material of fins104in order to create multi dimensional attenuated fins200.

Referring now toFIG. 10, a partial detailed cross section view of a multi dimensional attenuated fin200is shown, according to various embodiments of the present invention. Generally, multi dimensional attenuated fin200include a vertical outer portion210, horizontal outer portion215, inner portion220, and an attenuated portion230.

The vertical outer portion210is the sidewall perimeter portion of fin200created by the aforementioned diffusion along the sidewall perimeter of fins104. The horizontal outer portion215is the upper surface portion of fin200also created by the aforementioned diffusion along the top surface of fins104. As such, outer portion150has the highest concentration of the material surrounding fins104. Therefore, for example, vertical outer portion210and horizontal outer portion215may be 80% SiGe (i.e. SiGe with 80% Germanium concentration). The vertical outer portion210has a substantially vertical orientation (i.e. height is greater than width) and the horizontal outer portion215has a horizontal orientation (i.e. width is greater than height).

Inner portion220is the innermost portion of fin200and may be generally located at midpoint of the base of fin200. Generally, inner portion220are the locations of fin200where the material surrounding fins104did not diffuse. As such, inner portion220generally includes only the original material of fins104. Therefore, for example, inner portion220consists of only Silicon.

Attenuated portion230is formed from the multi dimensional diffusion profile of the material surrounding fins104diffusing into fins104. In certain embodiments, the attenuated composite is a graded, variable, or otherwise attenuated material that is similar to the composition of vertical outer portion210and horizontal outer portion215nearest the vertical outer portion210and horizontal outer portion215and attenuates to the composition of inner portion220nearest the inner portion220. Therefore, for example, an attenuated portion230may be 100% Silicon nearest vertical inner portion220and may be SiGe (80% Ge) nearest vertical outer portion210and nearest horizontal outer portion215and attenuates from SiGe (e.g. 99.9% Si) nearest inner portion220to SiGe (e.g. 79.9% Ge) nearest outer portions210,215there between. In certain embodiments, attenuated portion230only includes the attenuated composition and not the compositions similar to vertical outer portion210, horizontal outer portion215, and inner portion220. For clarity, it is noted that the outer SiGe concentration may be higher or lower than the exemplary 80% depending on diffusion conditions (e.g. anneal temperature, duration, etc.).

Referring now toFIG. 11, a cross section view of structure100is shown at an intermediate step during a process flow. At this step of fabrication, poly-Ge130is removed thereby exposing multi dimensional attenuated fins200, according to various embodiments of the present invention. Generally, poly-Ge130may be removed by any known technique. For example, poly-Ge130may be removed by an etch processes (wet etch, dry etch, etc.). In certain embodiments, poly-Ge130is etched selectively thereby leaving multi dimensional attenuated fins200. Since attenuated fins have vertical outer portion210and horizontal outer portion215comprising e.g. SiGe (80% Ge) there is an adequate percentage of non-Ge, that an etchant may selectively remove the surrounding poly-Ge130but leave multi dimensional attenuated fins200. Other such techniques may be utilized to remove poly-Ge130without departing from the scope of the embodiments herein claimed. Though depicted as a final fabrication stage inFIG. 11, it is to be understood that semiconductor structure100may undergo further processes to form a semiconductor device.

Referring now toFIG. 12, a detailed cross section view of structure100is shown at an intermediate step during a process flow. At this step of fabrication, semiconductor structure100may be annealed, according to various embodiments of the present invention. More generally, at this stage of fabrication, known techniques are utilized to force Ge to fully diffuse into the Si material of fins104thereby creating composite fins250accordingly to various embodiments of the present invention. As such,FIG. 12depicts an alternative embodiment to those embodiments shown inFIG. 3and inFIG. 9respectively. The known techniques may be heating semiconductor structure100, furnace annealing, rapid thermal annealing (RTA), Rapid Thermal Processing (RTP), non-melt anneal process completed in Epitaxy tool, etc. Utilizing such processes will change α-Ge120to poly-Ge130and will create a fin250fully comprised of the composite of the material surrounding fins104and the material of fins104. Composite fins250will typically not include a portion made up entirely of the original material of fins104. In certain embodiments, composite fins250may include a first composite portion252that comprises the highest percentage of material previously surrounding fins104. For example, portion252may comprise SiGe (80% Ge). In certain embodiments, composite fins250may include a second composite portion254that comprises the lowest percentage of material previously surrounding fins104. For example, portion254may comprise SiGe (10% Ge). In certain embodiments, composite fins250may also include an attenuated portion that attenuates from a similar composition nearest portion252to a similar composition nearest portion254.

Referring now toFIG. 13, a cross section view of structure100is shown at an intermediate step during a process flow. At this step of fabrication, poly-Ge130is removed, thereby exposing composite fins250, according to various embodiments of the present invention. In certain embodiments, poly-Ge130is etched selectively thereby leaving attenuated fins140. Since attenuated fins have outer portion252comprising e.g. SiGe (80% Ge) there is an adequate percentage of non-Ge, that an etchant may selectively remove the surrounding poly-Ge130but leave composite fins250. Though depicted as a final fabrication stage inFIG. 13, it is to be understood that semiconductor structure100may undergo further processes to form a semiconductor device.

Referring now toFIG. 14, a process300of fabricating a semiconductor device is shown. Process300begins at block302and continues with providing semiconductor substrate101(block304). For example, a semiconductor substrate101may be formed, received, manufactured, etc. Process200continues with forming attenuated fins (e.g. attenuated fins140, multi dimensional attenuated fins200, etc.) upon the semiconductor substrate101(block306). In certain embodiments, the attenuated fins includes an outer portion and/or an upper portion including a composite of a first material and a second material, and inner portion may include only the second material, and an attenuation portion comprising an attenuated composite of the first material and the second material. In certain embodiments, the attenuated composite attenuates from a composite of the first material and the second material nearest the outer portion to a non-composite second material nearest the inner portion. Process300ends at block308.

Referring now toFIG. 15, a process310of forming attenuated fins is shown. Process310begins at block312and continues with forming a cap106upon fins104comprising of the second material (block314). Process310continues with depositing the first material120onto the substrate101surrounding a plurality of fins104(block316). Process310continues with diffusing the first material120into the fins104comprising the second material (block318). For example, the diffusing may be accomplished by annealing the substrate, the plurality of fins, and the first material. In certain embodiments the first material is Germanium (Ge) and the second material is Silicon (Si). Process310continues with exposing the attenuated fins (block320). For example, the material surrounding the attenuated fins and the mask is etched or otherwise removed from the substrate. Process310ends at block322.

Referring now toFIG. 16, a block diagram of an exemplary design flow400used for example, in semiconductor integrated circuit (IC) logic design, simulation, test, layout, and/or manufacture is shown. Design flow400includes processes, machines and/or mechanisms for processing design structures or devices to generate logically or otherwise functionally equivalent representations of the structures and/or devices described above and shown inFIGS. 1-13.

Design flow400may vary depending on the type of representation being designed. For example, a design flow400for building an application specific IC (ASIC) may differ from a design flow400for designing a standard component or from a design flow400for instantiating the design into a programmable array, for example a programmable gate array (PGA) or a field programmable gate array (FPGA) offered by Altera® Inc. or Xilinx® Inc.

FIG. 16illustrates multiple such design structures including an input design structure320that is preferably processed by a design process410. Design structure420may be a logical simulation design structure generated and processed by design process410to produce a logically equivalent functional representation of a hardware device. Design structure420may also or alternatively comprise data and/or program instructions that when processed by design process410, generate a functional representation of the physical structure of a hardware device. Whether representing functional and/or structural design features, design structure420may be generated using electronic computer-aided design (ECAD) such as implemented by a core developer/designer.

When encoded on a machine-readable data transmission, gate array, or storage medium, design structure420may be accessed and processed by one or more hardware and/or software modules within design process410to simulate or otherwise functionally represent an electronic component, circuit, electronic or logic module, apparatus, device, structure, or system such as those shown inFIGS. 1-13. As such, design structure420may comprise files or other data structures including human and/or machine-readable source code, compiled structures, and computer-executable code structures that when processed by a design or simulation data processing system, functionally simulate or otherwise represent circuits or other levels of hardware logic design. Such data structures may include hardware-description language (HDL) design entities or other data structures conforming to and/or compatible with lower-level HDL design languages such as Verilog and VHDL, and/or higher level design languages such as C or C++.

Design process410may include hardware and software modules for processing a variety of input data structure types including Netlist480. Such data structure types may reside, for example, within library elements430and include a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.). The data structure types may further include design specifications440, characterization data450, verification data460, design rules470, and test data files485which may include input test patterns, output test results, and other testing information. Design process410may further include, for example, standard mechanical design processes such as stress analysis, thermal analysis, mechanical event simulation, process simulation for operations such as casting, molding, and die press forming, etc.

One of ordinary skill in the art of mechanical design can appreciate the extent of possible mechanical design tools and applications used in design process410without deviating from the scope and spirit of the invention claimed herein. Design process410may also include modules for performing standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc.

Design process410employs and incorporates logic and physical design tools such as HDL compilers and simulation model build tools to process design structure420together with some or all of the depicted supporting data structures along with any additional mechanical design or data (if applicable), to generate a second design structure490. Design structure490resides on a storage medium or programmable gate array in a data format used for the exchange of data of mechanical devices and structures (e.g. information stored in a IGES, DXF, Parasolid XT, JT, DRG, or any other suitable format for storing or rendering such mechanical design structures).

Similar to design structure420, design structure490preferably comprises one or more files, data structures, or other computer-encoded data or instructions that reside on transmission or data storage media and that when processed by an ECAD system generate a logically or otherwise functionally equivalent form of one or more of the embodiments of the invention shown inFIGS. 1-13. In one embodiment, design structure490may comprise a compiled, executable HDL simulation model that functionally simulates the devices shown inFIGS. 1-13.

Design structure490may also employ a data format used for the exchange of layout data of integrated circuits and/or symbolic data format (e.g. information stored in a GDSII (GDS2), GL1, OASIS, map files, or any other suitable format for storing such design data structures). Design structure490may comprise information such as, for example, symbolic data, map files, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data required by a manufacturer or other designer/developer to produce a device or structure as described above and shown inFIGS. 1-13. Design structure490may then proceed to a stage495where, for example, design structure490: proceeds to tape-out, is released to manufacturing, is released to a mask house, is sent to another design house, is sent back to the customer, etc.

The accompanying figures and this description depicted and described embodiments of the present invention, and features and components thereof. Those skilled in the art will appreciate that any particular nomenclature used in this description was merely for convenience, and thus the invention should not be limited by the specific process identified and/or implied by such nomenclature. Therefore, it is desired that the embodiments described herein be considered in all respects as illustrative, not restrictive, and that reference be made to the appended claims for determining the scope of the invention.

References herein to terms such as “vertical”, “horizontal”, etc. are made by way of example, and not by way of limitation, to establish a frame of reference. The term “horizontal” as used herein is defined as a plane parallel to the conventional plane or surface of the substrate, regardless of the actual spatial orientation of the semiconductor substrate. The term “vertical” refers to a direction perpendicular to the horizontal, as just defined. Terms, such as “on”, “above”, “below”, “side” (as in “sidewall”), “higher”, “lower”, “over”, “beneath” and “under”, are defined with respect to the horizontal plane. It is understood that various other frames of reference may be employed for describing the present invention without departing from the spirit and scope of the present invention.