Double heterojunction inversion base transistor

A bipolar transistor in which the base region includes a heterostructure and a doped layer of semiconductor material with the heterostructure functioning as a two-dimensional hole gas. The doped layer is sufficiently thin to prevent occurrence of a charge-neutral region of holes. In operation the transistor can switch quickly since minority charge storage in the base region does not present a problem. The device lends itself to downscaling in size in a VLSI circuit.

BACKGROUND OF THE INVENTION 
This invention relates generally to transistor structures, and more 
particularly the invention relates to a bipolar transistor having a double 
heterojunction inversion barrier. 
Improved speed and transconductance in transistor devices have been 
achieved by reducing the physical size of the device structures by 
lithography, processing technology and structural design. However, the 
decrease in transistor size leads to problems in both junction and MOS 
transistors, the most serious problem being the punchthrough effect where 
the collector merges with the emitter of a bipolar transistor or where the 
drain and source depletion regions begin to merge in MOS transistors. 
A new device structure has been proposed by Taylor and Simmons in "The 
Bipolar Inversion Channel Field Effect Transistor (BICFET)--A New Field 
Effect Solid State Device: Theory and Structures," IEEE Transactions on 
Electronic Devices November 1985. This device is bipolar in nature and 
relies upon the field effect inducement on an inversion layer that 
corresponds to the conventional neutral base of a bipolar transistor. The 
device utilizes a heterojunction, and does not have a base layer as in the 
conventional bipolar transistor. Yokoyama et al. U.S. Pat. No. 4,617,724 
also discloses a heterojunction bipolar transistor. 
SUMMARY OF THE INVENTION 
An object of the present invention is an improved bipolar transistor 
device. 
Another object of the invention is a bipolar transistor device having 
improved speed and reduced size. 
A feature of the invention is a heterostructure in the base region of a 
bipolar transistor. 
Briefly, a transistor device in accordance with the invention includes an 
emitter, a base, and collector. The base region includes a thin doped 
homogeneous semiconductor layer and an undoped heterostructure which 
functions as a two-dimensional hole gas. In a preferred embodiment, the 
structure comprises single crystalline silicon, with the heterostructure 
comprising a germanium-silicon alloy. Due to the need for abrupt doping 
profile (e.g. 50 Angstrom layers) and the use of a germanium-silicon 
alloy, molecular beam epitaxial processing is preferably employed in 
fabricating the device. Isolation between individual devices can be 
obtained by either selective epitaxy or mesa isolation. 
The invention and objects and features thereof will be more readily 
apparent from the following detailed description and appended claims when 
taken with the drawing.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENT 
Referring now to the drawing, FIG. 1 is a cross-sectional view illustrating 
the layers of a transistor structure in fabricating a bipolar transistor 
in accordance with one embodiment of the invention. The starting material 
is a silicon substrate 10 of (100) single-crystal material. Formed on a 
surface of the substrate 10 is a heavily-doped semiconductor layer 12 of 
approximately 1.2-micron thickness and with a dopant concentration of 
2.times.10.sup.19 atoms/cc of a donor such as antimony. Formed on the 
surface of the buried layer 12 is a layer 14 of silicon having a thickness 
of approximately 2600 Angstroms and a dopant concentration of 
1.times.10.sup.17 atoms/cc of a donor such as antimony. Layers 12 and 14 
comprise the collector region of the transistor structure. 
Formed on the surface of layer 14 is an undoped heterostructure 16 of a 
suitable material such as a germanium-silicon alloy having a thickness on 
the order of 100 Angstroms. Formed on the surface of the heterostructure 
16 is a thin layer 18 (e.g. 50 Angstrom) of single-crystal silicon 
material having a dopant concentration of 1.times.10.sup.19 atoms/cc of an 
acceptor such as boron. The layers 16 and 18 comprise the base region of 
the bipolar transistor with the region 18 contacting a two-dimensional 
hole gas provided by the heterostructure 16. The hole gas can be thought 
of classically as an inversion channel, and is confined by the valence 
band offset between silicon and germanium-silicon. 
Formed on the surface of layer 18 is a layer 20 of silicon having a dopant 
concentration of 1.times.10.sup.18 atoms/cc of a donor with the thickness 
of layer 20 being on the order of 350 Angstroms. Finally, formed on the 
surface of layer 20 is a layer 22 of an n-type silicon having a dopant 
concentration of 3.times.10.sup.19 atoms/cc and a thickness on the order 
of 800 Angstroms. The layers 20 and 22 form the emitter of the finished 
transistor structure. 
Due to the need for abrupt doping profiles and the use of the 
germanium-silicon layer, molecular beam epitaxy (MBE) is preferably 
employed in fabricating the layers. MBE is a well-known technique as 
described in U.S. Pat. No. 4,529,455, for example. 
FIG. 2 is a section view of a completed transistor device using the 
structure of FIG. 1. The layers are suitably etched to form a mesa 
structure and provide isolation between a plurality of transistors formed 
on a single substrate. Since the structure is formed primarily of silicon, 
the sidewalls of the mesa structure can be passivated by either 
low-temperature oxidation of the exposed silicon, or by deposition of 
silicon oxide followed by densification and forming gas anneal. A 
collector contact 24 is formed on the surface of layer 12, with the 
contact 24 connected through a resistor 26 to a +V potential 28. A base 
contact 30 is provided in abutment with the base layers 16, 18 with the 
contact 30 connected to a signal source 32. An emitter contact 34 is 
provided on the surface of layer 22 and is grounded. 
FIG. 3 illustrates the approximate band structure vertically through the 
device of FIG. 2 from emitter to collector, and FIGS. 4A and 4B illustrate 
the operating principle of the structure based on the band structure. The 
transistor is unipolar, doped n-type, except for the region 18 which is 
doped p-type. The p-type region 18 is narrow (approximately 50 Angstrom) 
so that sufficient band bending prevents a charge-neutral region of holes 
from occurring. However, the negative acceptor charge sets up a thermionic 
barrier, thereby preventing electron flow even when a positive bias is 
applied to the collector. 
The negative charge region forms a potential well for holes, which are 
thermally generated or injected into the indicated inversion channel by 
the base diffusion of FIG. 2. This lateral transport of hole charge is 
similar to the operation of a MOSFET or MODFET. If the number of holes 
supplied to the channel approaches the surface charge density of the 
p-doped region, then the electric field lines terminating on the negative 
charge will originate primarily from the mobile holes, which results in a 
lowering of the thermionic barrier. Thus, collector current is controlled 
by the hole quasi-Fermi level of the base region, or equivalently, the 
concentration of holes in the inversion channel. 
The hole and electron current densities are approximately given by the same 
expressions as for the BICFET device described by Taylor and Simmons, 
supra, as follows: 
EQU J.sub.pi =q.nu..sub.p P.sub.o 
e.sup.-q/kT(-V.sbsp.i.sup.+.DELTA.E.sbsp.v.sup./q) (e.sup.qV/kT -1) (1) 
EQU J.sub.ni =q.nu..sub.n N.sub.C 
e.sup.-q/kT(-V.sbsp.i.sup.+.PHI..sbsp.n.sup./q) (e.sup.qV/kT -1) (2) 
where .upsilon. is the effective velocity of the holes or electrons, Po is 
the inversion hole charge density, V.sub.i * is the barrier height, 
.PHI..sub.n is the metal to semi-insulating layer barrier height, and 
.DELTA.E.sub.v is the valence band discontinuity at the heterojunction. 
Current limiting in this analysis due to space charge was ignored, due to 
the assumption of heavy doping of the thermionic barrier layer. Equations 
1 and 2 yield a current gain of 
EQU .beta.=J.sub.ni /J.sub.pi 
.apprxeq.e.sup.(.DELTA.E.sbsp.v.sup.-.PHI..sbsp.n.sup.)/kT (3) 
For .DELTA.E.sub..upsilon. .apprxeq.0.3eV, and .PHI..sub.n .apprxeq.0, 
current gains of 10.sup.5 should be possible. However, quantum mechanical 
corrections result in a lower value of predicted .beta. for the BICFET, 
and even lower values for the double heterojunction transistor, which uses 
a very thin region of narrow gap semiconductor (GeSi). However, the use of 
this narrow region of strained layer semiconductor is what allows 
implementation of the inversion base transistor in silicon. 
This device is easily scaled down in size, since it does not have any 
voltage punchthrough limitations. It switches quickly, since it does not 
have minority charge storage problems as in the base region of a bipolar 
junction transistor. It has a low collector cut-in voltage and no minority 
charge injection into the collector during saturated operation due to the 
presence of a double heterojunction to confine the hole charge. Since the 
device has a very large current drive capability, the transistor excels at 
switching large capacitive loads quickly. 
While the invention has been described with reference to a specific 
embodiment, the description is illustrative of the invention and is not to 
be construed as limiting the invention. For example, other heterostructure 
materials can be employed such as CuCl, ZnS, AlP and GaP, and other 
semiconductor material, layer thicknesses, dopant type and concentration 
levels can be used. 
Thus, various modifications and applications may occur to those skilled in 
the art without departing from the true spirit and scope of the invention 
as defined by the appended claims.