DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF

A display device according to some embodiments includes: a substrate; a plurality of common voltage lines positioned on the substrate; a plurality of connection electrodes positioned on a plurality of common voltage lines; an emission layer positioned on the connection electrode; and a common electrode positioned on the emission layer, wherein the emission layer has a plurality of first openings positioned on at least a portion of a plurality of connection electrodes, the common electrode is electrically connected to the connection electrode through a plurality of first openings, and a pitch of a first direction of a plurality of first openings has a range of about 0.1 mm to about 2.5 mm.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to, and the benefit of, Korean Patent Application No. 10-2021-0141673 filed in the Korean Intellectual Property Office on Oct. 22, 2021, the entire contents of which are incorporated herein by reference.

BACKGROUND

The present disclosure relates to a display device, and to a manufacturing method thereof.

2. Description of the Related Art

A display device includes a display area including a plurality of pixels. Each pixel includes a pixel electrode to which a data signal is applied, a plurality of transistors and at least one capacitor for transmitting a data signal to the pixel electrode, and a common electrode facing the pixel electrode. At least one layer may be positioned between the pixel electrode and the common electrode.

The common electrode may be formed as one electrode over a plurality of pixels to transmit a constant voltage.

SUMMARY

The common electrode formed over a plurality of pixels may be electrically connected to an underlying connection electrode through an opening formed in a layer positioned thereunder.

Embodiments of the present disclosure may reduce contamination due to particles generated when forming the opening where the common electrode is connected to the underlying connection electrode to shorten a manufacturing process time, and may improve uniformity of luminance of the display area to such an extent that a mura is either less visible or not visible.

A display device according to some embodiments includes a substrate common voltage lines on the substrate, connection electrodes on common voltage lines, an emission layer on the connection electrode, and defining first openings on at least a portion of the connection electrode, a pitch of a first direction of the first openings having a range of about 0.1 mm to about 2.5 mm, and a common electrode on the emission layer, and electrically connected to the connection electrode through first openings.

The display device may further include pixels, the pixels including sub-pixels corresponding to different colors and including a transistor and a light emitting diode (LED), the light emitting diode (LED) including a pixel electrode, the emission layer, and the common electrode.

The pitch of the first openings in the first direction may be greater than a pitch of the pixels in the first direction.

The pitch of the first openings in the first direction may be greater than a pitch of the common voltage lines in the first direction.

The pitch of the first openings in the first direction may be greater than a pitch of the connection electrodes in the first direction.

The connection electrodes may be at a same conductive layer as, and may include a same material as, the pixel electrode.

The display device may further include an insulating layer between the pixel electrode and the emission layer, and defining a second opening overlapping one of the first openings.

The one of the first openings may be within an edge of the second opening in a plan view.

An edge of the one of the first openings and an edge of the second opening may be aligned with each other.

A pitch of the first openings in a second direction, which is substantially perpendicular to the first direction, may have a range of about 0.1 mm to about 2.5 mm.

A display device according to some embodiments includes a substrate common voltage lines on the substrate, connection electrodes on common voltage lines, an emission layer on the connection electrodes, defining first openings on at least a portion of connection electrodes, and having an opening formation region defining the first openings and an opening non-formation region not including the first openings, the opening formation region and the opening non-formation region being alternately arranged in a first direction, and a common electrode on the emission layer, and electrically connected to the connection electrodes through the first openings.

The first openings may be arranged in the opening formation region with a constant pitch in a first direction, the pitch being in a range of about 0.1 mm to about 2.5 mm.

A width of the opening non-formation region between the opening formation region and an adjacent opening formation region in the first direction may be greater than a pitch of the first openings, and equal to or less than a value equal to twice the pitch of the first openings added to a width of the opening formation region in the first direction.

A width of the opening formation region in the first direction may be equal to a width of the opening formation region in a second direction that is substantially perpendicular to the first direction.

The width of the opening non-formation region in the first direction may be equal to a width of the opening non-formation region in a second direction that is substantially perpendicular to the first direction.

The display device may further include pixels, the pixels including sub-pixels corresponding to different colors, the sub-pixels including a transistor and a light emitting diode (LED), the light emitting diode (LED) including a pixel electrode, the emission layer, and the common electrode.

The pitch of the first openings in the first direction may be greater than a pitch of the pixels in the first direction.

A pitch of openings in the opening formation region in a second direction that is substantially perpendicular to the first direction may have a range from about 0.1 mm to about 2.5 mm.

A manufacturing method of a display device according to some embodiments includes forming common voltage lines on a substrate, forming connection electrodes on the common voltage lines, stacking and patterning an insulating layer on the connection electrodes to form first openings having a pitch in a first direction in a range of about 0.1 mm to about 2.5 mm, stacking an emission layer on the insulating layer, forming second openings corresponding to the first openings by removing a portion of the emission layer by a laser drilling process, and forming a common electrode on the emission layer, and electrically connected to the connection electrodes through the second openings.

The emission layer may have an opening formation region defining the first openings, and an opening non-formation region not including the first openings, wherein the opening formation region and the opening non-formation region are alternately arranged in the first direction.

According to embodiments, while improving the uniformity of the luminance of the display area to a degree that mura is not recognized, the manufacturing process time may be shortened by reducing contamination by particles that occurs during the formation of the opening where the common electrode is connected to the underlying connection electrode.

DETAILED DESCRIPTION

Aspects of some embodiments of the present disclosure and methods of accomplishing the same may be understood more readily by reference to the detailed description of embodiments and the accompanying drawings. Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings. The described embodiments, however, may have various modifications and may be embodied in various different forms, and should not be construed as being limited to only the illustrated embodiments herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey the aspects of the present disclosure to those skilled in the art, and it should be understood that the present disclosure covers all the modifications, equivalents, and replacements within the idea and technical scope of the present disclosure. Accordingly, processes, elements, and techniques that are not necessary to those having ordinary skill in the art for a complete understanding of the aspects of the present disclosure may not be described.

Unless otherwise noted, like reference numerals, characters, or combinations thereof denote like elements throughout the attached drawings and the written description, and thus, descriptions thereof will not be repeated. Further, parts that are not related to, or that are irrelevant to, the description of the embodiments might not be shown to make the description clear.

Thus, the regions illustrated in the drawings are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to be limiting. Additionally, as those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present disclosure.

It will be understood that when an element, layer, region, or component is referred to as being “formed on,” “on,” “connected to,” or “coupled to” another element, layer, region, or component, it can be directly formed on, on, connected to, or coupled to the other element, layer, region, or component, or indirectly formed on, on, connected to, or coupled to the other element, layer, region, or component such that one or more intervening elements, layers, regions, or components may be present. In addition, this may collectively mean a direct or indirect coupling or connection and an integral or non-integral coupling or connection. For example, when a layer, region, or component is referred to as being “electrically connected” or “electrically coupled” to another layer, region, or component, it can be directly electrically connected or coupled to the other layer, region, and/or component or intervening layers, regions, or components may be present. However, “directly connected/directly coupled,” or “directly on,” refers to one component directly connecting or coupling another component, or being on another component, without an intermediate component. Meanwhile, other expressions describing relationships between components such as “between,” “immediately between” or “adjacent to” and “directly adjacent to” may be construed similarly. In addition, it will also be understood that when an element or layer is referred to as being “between” two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

It will be understood that, although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section described below could be termed a second element, component, region, layer or section, without departing from the spirit and scope of the present disclosure. The description of an element as a “first” element may not require or imply the presence of a second element or other elements. The terms “first”, “second”, etc. may also be used herein to differentiate different categories or sets of elements. For conciseness, the terms “first”, “second”, etc. may represent “first-category (or first-set)”, “second-category (or second-set)”, etc., respectively.

First, a structure of a display device according to some embodiments is described with reference toFIG.1toFIG.5.

FIG.1is a top plan view of one electrode layer and a common voltage line, which are positioned in one pixel of a display area of a display device according to some embodiments, andFIG.2is a top plan view of a plurality of pixels and a plurality of connection electrodes of a display area of a display device according to some embodiments.

Referring toFIG.1andFIG.2, a display device according to some embodiments includes a plurality of pixels PX capable of displaying an image. A plurality of pixels PX, as shown inFIG.2, may be approximately arranged in a matrix form, but are not limited thereto, and may be repeatedly arranged with a certain rule (e.g., according to a corresponding layout scheme).

Referring toFIG.1, each pixel PX may include a plurality of sub-pixels PX1, PX2, and PX3. A plurality of sub-pixels PX1, PX2, and PX3included in each pixel PX may display light of different colors. For example, a plurality of sub-pixels PX1, PX2, and PX3may display primary colors, such as red, green, and blue. A plurality of sub-pixels PX1, PX2, and PX3may display various colors by combining various luminances of different primary colors.

Each of the sub-pixels PX1, PX2, and PX3respectively includes pixel electrodes191a,191b, and191cto which a data signal can be applied, the data signal having luminance information corresponding to light to be displayed, and a plurality of transistors electrically connected thereto. A plurality of pixel electrodes191a,191b, and191cmay be positioned on the same layer, and positioned on a pixel electrode layer including the same material.

Each pixel electrode191a,191b, and191cmay be respectively electrically connected to the transistor, which is formed in each sub-pixel PX1, PX2, and PX3, through an opening1184, which is a hole formed in at least one insulating layer positioned below each pixel electrode191a,191b, and191c.

The display device according to some embodiments includes a plurality of common voltage lines170and a plurality of connection electrodes195for transmitting a common voltage.

The common voltage line170may extend lengthwise (e.g., in the y direction). The common voltage line170may be arranged one by one at least for each pixel PX (e.g., in the x direction).FIG.1andFIG.2shows an example in which one common voltage line170is positioned for every pixel PX in the x direction (e.g., there may be one common voltage line170for multiple pixels PX arranged in the y direction).

For example, there may be at least one connection electrode195for each pixel PX in the x direction or the y direction.FIG.1andFIG.2show an example in which one connection electrode195is formed for each pixel PX in each of the x direction and the y direction.

The connection electrode195may be positioned in a conductive layer that is different from that of the common voltage line170.

At least a portion of each connection electrode195overlaps a corresponding common voltage line170in the z direction that is substantially perpendicular to the x and y directions. The portion of the connection electrode195overlapping the common voltage line170may be electrically connected to the common voltage line170through an opening1182of at least one insulating layer positioned between the common voltage line170and the connection electrode195.

Referring toFIG.2, an emission layer opening1370of an emission layer may be positioned on, or may overlap, a portion of a plurality of connection electrodes195.

The pitch Wa in the x-direction of the emission layer opening1370, that is, the distance between respective emission layer openings1370adjacent in the x-direction, may have a range of about 0.1 mm to about 2.5 mm. Similarly, the pitch Wb in the y direction of the emission layer opening1370, that is, the distance between respective emission layer openings1370adjacent in the y direction, may also have a range of about 0.1 mm to about 2.5 mm. For example, the pitches Wa and Wb of the emission layer openings1370in the x direction and the y direction, which may further increase or maximize aspect of the embodiments, may have a range of about 0.8 mm to about 2.5 mm, respectively. The corresponding aspect due thereto will be described in detail later.

The pitches Wa and Wb of the emission layer openings1370in the x and the y directions are greater than the pitch of the pixels PX in the x and y directions, respectively.

In some embodiments, the pitch Wa in the x direction of the emission layer openings1370may be the same as, or different from, the pitch Wb in the y direction of the emission layer openings1370.

The connection electrode195overlapping the emission layer opening1370is electrically connected to the underlying common voltage line170through the opening1182.

The connection electrode195, which does not overlap with the emission layer opening1370, as shown inFIG.2, may be electrically connected to the common voltage line170through the opening1182. However, according to other embodiments, at least some of the connection electrodes195that do not overlap with the emission layer opening1370also might not overlap with the opening1182.

According to some embodiments, the x-direction pitch Wa of the emission layer opening1370may be greater than the pitch in the x-direction of a plurality of common voltage lines170, and, for example, may be an integer multiple thereof. In addition, the x-direction pitch Wa of the emission layer opening1370may be greater than the pitch of a plurality of connection electrodes195in the x-direction, and, for example, may be an integer multiple thereof.

According to other embodiments, the connection electrode195of a column, in which only ones of the connection electrodes195that do not overlap with the emission layer opening1370are arranged, might not overlap with the common voltage line170. That is, the common voltage line170may be formed to not be in a location corresponding to the column including only the connection electrodes195in which the emission layer opening1370is not formed. Furthermore, the common voltage line170may be formed to have the same pitch as the emission layer openings1370adjacent in the x direction, that is, the pitch Wa in the x direction of the emission layer openings1370.

According to other embodiments, at least some of the connection electrodes195that are not electrically connected to the common voltage line170, or the connection electrode(s)195that do not overlap with the emission layer opening1370, may be omitted.

The connection electrode195may be positioned in a conductive layer that is different from that of the common voltage line170, and may be positioned in the same conductive layer as the pixel electrodes191a,191b, and191c, and may also include the same conductive material, although the present disclosure is not limited thereto.

The planar shape of the emission layer opening1370may vary, such as circular, elliptical, or polygonal. In embodiments in which the emission layer1370is circular will be mainly described. When the emission layer opening1370has a circular planar shape, the common electrode270, which will be described later, may be in more uniform contact with the underlying connection electrode195through the emission layer opening1370.

The detailed structure of the display device according to some embodiments will be described with reference toFIG.3toFIG.5.

FIG.3is a top plan view of a connection electrode of a display device according to some embodiments,FIG.4is a cross-sectional view of a display device shown inFIG.3taken along the line A1-A2, andFIG.5is a cross-sectional view of one pixel of a display device according to some embodiments.

A display device according to some embodiments may include a substrate110including an insulating material, and a buffer layer111, which is an insulating layer, may be positioned on the substrate110.

A first conductive layer including a light blocking pattern177may be positioned between the substrate110and the buffer layer111.

A semiconductor layer including a channel region1132, and conductive regions1131and1133positioned on respective sides of the channel region1132, may be positioned on the buffer layer111. Based on one channel region1132, a conductive region1131positioned on one side may be a source region, and a conductive region1133positioned on the other side may be a drain region, or vice versa.

A first insulating layer120may be positioned on or above the semiconductor layer.

A second conductive layer including a gate electrode1155and a lower electrode1153may be positioned on the first insulating layer120. The gate electrode1155may overlap the channel region1132in the z direction. The gate electrode1155may be electrically connected to the lower electrode1153, and may be formed integrally.

The channel region1132, the conductive regions1131and1133, and the gate electrode1155together may form a single transistor or a section thereof.

A second insulating layer160may be positioned on the gate electrode1155and the lower electrode1153.

A third conductive layer including an upper electrode1154and a common voltage line170may be positioned on the second insulating layer160.

The upper electrode1154may overlap the lower electrode1153with the second insulating layer160interposed therebetween to form a capacitor. The lower electrode1153may also overlap the light blocking pattern177with the first insulating layer120interposed therebetween.

The upper electrode1154may be electrically connected to the conductive region1133of the transistor through the opening165formed in, or defined by, the second insulating layer160and the first insulating layer120.

A third insulating layer180may be positioned on the common voltage line170and the upper electrode1154. The third insulating layer180may include a first protective layer180aand a second protective layer180b.

The third insulating layer180includes or defines a plurality of openings1184and a plurality of openings1182positioned above, or at a layer that is above, the common voltage line170.

At least one of the first conductive layer, the second conductive layer, and the third conductive layer may include at least one of metals including copper (Cu), aluminum (Al), magnesium (Mg), silver (Ag), gold (Au), platinum (Pt), palladium (Pd) , nickel (Ni), neodymium Nd, iridium (lr), molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), tantalum (Ta), and alloys thereof, and metal oxides such as indium tin oxide (ITO) and indium zinc oxide (IZO). Each of the first conductive layer, the second conductive layer, and the third conductive layer may be formed of a single layer or multiple layers. For example, at least one of the first conductive layer, the second conductive layer, and the third conductive layer may have a multilayer structure including a lower layer including titanium, an intermediate layer including copper, and an upper layer including ITO.

At least one of the buffer layer111, the first insulating layer120, the second insulating layer160, and the third insulating layer180may include an inorganic insulating material such as a silicon nitride (SiNx), a silicon oxide (SiOx), a silicon oxynitride (SiON), etc., and/or an organic insulating material such as polyimide, an acryl-based polymer or, a siloxane-based polymer. The first protective layer180aof the third insulating layer180may be made of an inorganic insulating material, and the second protective layer180bmay be made of an organic insulating material.

A fourth conductive layer including a connection electrode195may be positioned on the third insulating layer180. The connection electrode195may be electrically connected to the common voltage line170through the opening1182.

A plurality of pixel electrodes191may be positioned on the third insulating layer180. The pixel electrode191may include the pixel electrodes191a,191b, and191cshown inFIG.1.

According to some embodiments, a plurality of pixel electrodes191may be positioned in the same conductive layer as the connection electrode195, that is, the fourth conductive layer. The pixel electrode191may include the same material as the connection electrode195, and may be formed together in the same process. In this case, the fourth conductive layer may include a transparent metal oxide, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

For example, the fourth conductive layer may be formed of a multilayer such as a triple layer in which a layer including ITO, a layer including silver (Ag), and a layer including ITO are sequentially stacked, or a single layer.

Alternatively, the pixel electrode191and the connection electrode195may be positioned on different conductive layers, and may include different conductive materials.

The pixel electrode191may be electrically connected to the upper electrode1154through the opening1184.

A fourth insulating layer350may be positioned on the connection electrode195and the pixel electrode191. The fourth insulating layer350may include an organic insulating material such as a polyacryl-based resin or a polyimide-based resin.

The fourth insulating layer350has an opening1350that overlaps the connection electrode195in the z direction, and an opening351that overlaps the pixel electrode191. The opening1350may be spaced apart from the opening1182of the third insulating layer180in plan view (e.g., the xy plan view).

The emission layer370may be positioned on the fourth insulating layer350. The emission layer370is positioned entirely over most of the substrate110, but may have an emission layer opening1370overlapping the connection electrode195.

The emission layer opening1370of the emission layer370may overlap at least a portion of the opening1350of the fourth insulating layer350. Referring toFIG.3andFIG.4, the emission layer opening1370of the emission layer370may be positioned within the edge of the opening1350of the fourth insulating layer350(e.g., in a plan view). In this case, a part of the emission layer370may be positioned within the opening1350of the fourth insulating layer350.

Differently fromFIG.3andFIG.4, in some embodiments, a portion of the emission layer opening1370of the emission layer370may overlap a portion of the edge of the opening1350of the fourth insulating layer350.

The emission layer370may include an organic light emitting material or an inorganic light emitting material. The emission layer370may be positioned within the opening351of the fourth insulating layer350to be in contact with the pixel electrode191.

A common electrode270is positioned on the emission layer370. The common electrode270may be positioned entirely on (e.g., over) the substrate110. The common electrode270may be electrically connected to the connection electrode195through the emission layer opening1370of the emission layer370. The common electrode270may be electrically connected to the common voltage line170through the connection electrode195to receive the common voltage.

The common electrode270may include a metal material including silver (Ag) or a transparent metal oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO). The thickness of the common electrode270in the z direction may be about150angstroms or less, but is not limited thereto. The common electrode270may be in contact with the emission layer370.

The pixel electrode191, the emission layer370, and the common electrode270of each sub-pixel PX1, PX2, and PX3together form a light emitting diode (LED) ED. In this case, the pixel electrode191may be an anode, and the common electrode270may be a cathode.

The display device according to some embodiments will be described with reference toFIG.6,FIG.7, andFIG.8.

FIG.6is a top plan view of a connection electrode of a display device according to some embodiments, andFIG.7andFIG.8are cross-sectional views of a display device shown inFIG.6taken along the line A1-A2.

Referring toFIG.6toFIG.8, the display device according to some embodiments is mostly the same as the display device shown inFIG.1toFIG.5, but the edge of the emission layer opening1370of the emission layer370may be substantially aligned with the edge of the opening1350of the fourth insulating layer350. Therefore, unlike previous embodiments, the emission layer370may not be substantially positioned in the opening1350of the fourth insulating layer350.

The side shape of the opening1350of the fourth insulating layer350, as shown inFIG.7, may be made obliquely inclined, and as shown inFIG.8, the side shape of the opening1350of the fourth insulating layer350may form a substantially flat surface with the side of the emission layer opening1370.

A manufacturing method of the display device according to some embodiments will be described with reference toFIG.9andFIG.10along withFIG.3toFIG.8.

FIG.9is a view showing a step of a laser drilling process in a manufacturing method of a display device according to some embodiments, andFIG.10is a view showing a display device after a laser drilling process in a manufacturing method of a display device according to some embodiments.

Referring toFIG.9, after forming a plurality of common voltage lines170and a plurality of connection electrodes195on a substrate110, a fourth insulating layer350is formed and patterned on the connection electrode195to form an opening1350.

Next, an emission layer370is stacked on the fourth insulating layer350.

Next as shown inFIG.10, an emission layer opening1370is formed by removing the emission layer370corresponding to the opening1350of the fourth insulating layer350. As a method of forming the emission layer opening1370, for example, a laser drilling process for forming the emission layer opening1370by irradiating laser, may be used. At this time, particles of the emission layer370that are removed by the laser may be generated.

In the case of the embodiments corresponding toFIG.6toFIG.8, after stacking the fourth insulating layer350, the opening1350is not directly formed, and the emission layer370is stacked on the fourth insulating layer350. Thereafter, the emission layer370and the fourth insulating layer350on the connection electrode195may be removed together using a process such as laser drilling. Accordingly, the emission layer opening1370of the emission layer370and the opening1350of the fourth insulating layer350, which are aligned with each other, may be formed.

After forming the emission layer opening1370, as shown inFIG.4,FIG.5,FIG.7, andFIG.8described above, the common electrode270is formed on the emission layer370.

Now, the emission layer opening1370of the emission layer370of the display device according to some embodiments will be described with reference toFIG.11andFIG.12along withFIG.1toFIG.8described above.

FIG.11andFIG.12are enlarged top plan views of a display area and a part of the display area in a display device according to some embodiments, respectively,

Referring toFIG.11, the display device1000according to some embodiments includes a display area DA capable of displaying an image by including a plurality of pixels. The emission layer positioned in the display area DA has a plurality of emission layer openings1370as described above.

A plurality of emission layer openings1370may be arranged at a constant interval, that is, at a constant pitch, in each of the x direction and the y direction over the entire display area DA.

In the entire display area DA, the x-direction pitch Wa of the emission layer opening1370, that is, the distance between the centers of adjacent emission layer openings1370that are adjacent in the x-direction, may have a range of about 0.1 mm to about 2.5 mm. Similarly, the y-direction pitch Wb of the emission layer opening1370, that is, the distance between the centers of adjacent emission layer openings1370that are adjacent in the y-direction, may also have a range of about 0.1 mm to about 2.5 mm. For example, pitches Wa and Wb of the emission layer opening1370in the x direction and the y direction may have a range of about 0.8 mm to about 2.5 mm, respectively.

The pitch Wa in the x direction of the emission layer opening1370may be the same as, or different from, the pitch Wb in the y direction of the emission layer opening1370.FIG.11shows an example in which the x-direction pitch Wa of the emission layer opening1370is the same as the pitch Wb in the y-direction of the emission layer opening1370.

Referring toFIG.12, the emission layer positioned in the display area DA included in the display device1000aaccording to some embodiments may include an opening formation region LDA where a plurality of emission layer openings1370are arranged with the constant pitch, and an opening non-formation region NLDA without the emission layer opening1370.

UnlikeFIG.11, according to some embodiments, respective intervals at which respective pairs of neighboring emission layer openings1370are spaced apart, of the emission layer openings1370included in the emission layer of the display device1000a, may include different respective intervals for the x direction and the y direction.

For each of the x and y directions, the opening formation region LDA and the opening non-formation region NLDA are positioned alternately. As shown inFIG.12, a plurality of opening formation regions LDA may be spaced apart from each other to be arranged in a matrix form, and the opening non-formation region NLDA may be connected in a square mesh shape.

In each opening formation region LDA, a plurality of emission layer openings1370may be arranged at a constant interval, that is, at a constant pitch, in each of the x and y directions in the opening formation region LDA.

In the opening formation region LDA, the x direction pitch Wa of the emission layer opening1370, that is, the distance between the centers of the emission layer openings1370adjacent in the x direction, may have the range of about 0.1 mm to about 2.5 mm. Similarly, the y-direction pitch Wb of the emission layer opening1370, that is, the distance between the centers of the emission layer openings1370adjacent in the y-direction, may also have the range of about 0.1 mm to about 2.5 mm. For example, the pitches Wa and Wb of the emission layer openings1370in the x direction and the y direction may have the range of about 0.8 mm to about 2.5 mm.

The x-direction width of each opening formation region LDA is substantially the width from the edge of an emission layer opening1370positioned on one edge, to the edge of a corresponding emission layer opening1370positioned on the opposite edge. However, for convenience of illustration and description, the x direction width We of the opening formation region LDA is defined as the distance from the center of the leftmost emission layer opening1370to the center of the rightmost emission layer opening1370as shown. Similarly, the y-direction width Wf of each opening formation region LDA is defined as the distance from the center of an uppermost emission layer opening1370to the center of a lowermost emission layer opening1370as shown.

Similarly, the distance between two adjacent opening formation regions LDA in the x direction, that is, the width in the x direction of the opening non-formation region NLDA positioned between two adjacent opening formation regions LDA, is substantially the width from the right edge of the emission layer opening1370, which is adjacent to the left of one opening non-formation region NLDA, to the left edge of the emission layer opening1370that is adjacent to the right of the corresponding opening non-formation region NLDA. For convenience of illustration and description, as shown, the x-direction width Wc of each opening non-formation region NLDA is defined as the distance from the center of the emission layer opening1370adjacent to the left to the center of the emission layer opening1370adjacent to the right. Similarly, the y-direction width Wd of each opening non-formation region NLDA is defined as the distance from the center of an emission layer opening1370adjacent to the upper side of the non-formation region NLDA to the center of an emission layer opening1370adjacent to the lower side, as shown.

The x-direction width We of each opening formation region LDA may be the same as, or different from, the y-direction width Wf thereof.FIG.12shows an example in which the x-direction width We of each opening formation region LDA) is equal to the y-direction width Wf.

The x-direction pitch Wa of the emission layer opening1370in each opening formation region LDA may be the same as, or different from, the pitch Wb in the y-direction of the emission layer opening1370.FIG.12shows an example where the x-direction pitch Wa of the emission layer opening1370is the same as the pitch Wb in the y-direction of the emission layer opening1370.

FIG.12shows an example in which each opening formation region LDA includes a total of the 36 emission layer openings1370, but is not limited thereto.

The width Wc in the x direction of the opening non-formation region NLDA positioned between two opening formation regions LDA adjacent in the x direction may be larger than the x direction pitch Wa of the emission layer opening1370within one opening formation region LDA, and may be equal to, or smaller than, a value that is twice the x-direction pitch Wa of the emission layer opening1370plus the x-direction width We of one opening formation region LDA.

Similarly, the y-direction width Wd of the opening non-formation region NLDA positioned between two opening formation regions LDA adjacent in the y-direction may be larger than the y-direction pitch Wb of the emission layer opening1370within one opening formation region LDA, and may be equal to or less than the value of which twice of the y-direction pitch (Wb) of the emission layer opening1370is added to the y-direction width Wf of one opening formation region LDA.

FIG.12shows an example of which the width Wc in the x direction of the opening non-formation region NLDA is approximately equal to the distance obtained by adding twice the x direction pitch Wa of the emission layer opening1370to the width We in the x direction of the opening formation region LDA. Also, the y-direction width Wd of the opening non-formation region NLDA is approximately equal to the distance obtained by adding twice the y-direction pitch Wb of the emission layer opening1370to the y-direction width Wf of the opening formation region LDA.

The width Wc in the x direction of the opening non-formation region NLDA may be the same as, or different from, the width Wd in the y direction.FIG.12shows an example in which the width Wc in the x direction and the width Wd in the y direction of the opening non-formation region NLDA are approximately equal to each other.

An aspect according to the display device according to some embodiments will be described with reference toFIG.13toFIG.17along with the above-described drawings.

FIG.13andFIG.14are pictures showing a luminance of a display device according to a comparative example, respectively,FIG.15is a table showing a luminance value of various regions of the display device according to a comparative example as a percentage,FIG.16is a picture showing a luminance of a display device according to some embodiments, andFIG.17is a table showing a luminance value of various regions of the display device according to a comparative example as a percentage.

A display device1000caccording to a comparative example, which is different from embodiments of the present disclosure, includes the same emission layer opening1370as some of the previously described embodiments, but the x-direction pitch and the y-direction pitch of the emission layer opening1370are larger than 2.5 mm, which is different from the range of the previously described embodiments. When the display device1000caccording to the comparative example is displayed as entirely white, according to the voltage drop of the common voltage transmitted by the common electrode, and as shown inFIG.13, the overall luminance is lowered, and a dark region LL1appears as a stain in a wide area.

ReferringFIG.14in which the region LL2with relatively high luminance in the display device ofFIG.13is enlarged, the luminance near the region where the emission layer opening1370is formed is high, and the luminance in the region without the emission layer opening1370is low, so that a mura, which is a localized spot, may be periodically recognized.

FIG.15shows an example of the numerical value of the luminance of the display area of the display device1000caccording to the comparative example shown inFIG.12. When the maximum luminance is 100%, the overall luminance of the display area is not uniform. Also, when about 80% is used as a standard for a luminance failure, the luminance of the center region of the display device1000cmay be about 78.2%, which is below the standard.

On the other hand, referring toFIG.16, it may be confirmed that the display device (1000,1000a) according to some embodiments exhibits uniform and high luminance as a whole when white is displayed like the display device of the comparative example.

FIG.17shows an example of the numerical value of the luminance of the display area of the display devices1000and1000aaccording to some embodiments. When the maximum luminance is 100%, it may be confirmed that the overall luminance of the display area is more than 90% uniform.

FIG.18is a table showing a photograph and a luminance contour diagram showing a luminance of several display devices according to some embodiments and a comparative example.

In the table ofFIG.18, the uppermost display device is a display device according to some embodiments, the pitches Wa and Wb in the x and y directions of the emission layer opening1370are about 1.116 mm, and when being expressed based on the interval of the pixels PX, one emission layer opening1370is formed for every three pixels PX in the x and y directions. If a formation cycle based on these pixels PX is referred to as a pixel interval of the opening, the emission layer opening1370is formed with the pixel interval of 3x3.

In the table ofFIG.18, the middle display device is a display device according to the comparative example, the x-direction and y-direction pitches of the emission layer opening1370are about 6.696 mm, and one emission layer opening1370is formed for each 18 pixels PX in the x-direction and y-direction when being expressed based on the interval of the pixel PX. That is, the emission layer opening1370is formed with the period of the pixel interval of 18x18.

The last display device in Table ofFIG.18is also a display device according to comparative example, the pitches of the emission layer openings1370in the x direction and the y direction are about 8.928 mm, and when the interval of the pixels PX is expressed as a standard, one emission layer opening1370is formed for every 24 pixels PX in the x direction and the y direction. That is, the emission layer opening1370is formed with the pixel interval of 24x24.

Referring to the image (the center column in the table ofFIG.18) and to the graph showing the luminance of light as a contour line (the right column in the table ofFIG.18), when white is displayed on the three display devices shown inFIG.18, in the case of the display device according to some embodiments, the overall luminance is high, and in the case of the display device according to the comparative example, the luminance is significantly low.

FIG.19is a table showing a common voltage drop and a visibility result of several display devices according to some embodiments, and a comparative example.

Referring toFIG.19, no matter what the pixel interval of the emission layer opening1370is (e.g., any interval such as 3x3, 6x6, 18x18, 24x24, etc.), it may be confirmed that whether the mura is recognized depends on the numerical range of the pitch of the x-direction and y-direction of the emission layer opening1370.

In the table ofFIG.19, in the above two cases in which the pitch in the x direction and y direction of the emission layer opening1370are within the range of about 0.1 mm to about 2.5 mm as in some embodiments, although the pixel interval is different as 3x3 and as 6x6, respectively, there is no mura because the difference in luminance according to the non-uniform of the common voltage in the regions with and without the emission layer opening1370is not recognized. However, in the third and fourth cases where the pitches in the x direction and y direction of the emission layer opening1370are respectively about 6.696 mm and about 8.928 mm outside the range of the embodiments, regardless of the pixel spacing (18x18, 24x24), the difference in luminance according to the non-uniformity of the common voltage in the regions with and without the emission layer opening1370is recognized and is shown as mura.

FIG.20is a table showing an example of a pitch of an opening in which mura is not recognized in several display devices according to some embodiments.

Referring toFIG.20, it may be confirmed that the mura does not appear when the pitch of the x-direction and y-direction of the emission layer opening1370is within the numerical range of some embodiments, regardless of the display panel size of the display device. That is, even if the diagonal size of the display panel varies (e.g., 34 inches, 31.5 inches, 65 inches, 55 inches, etc.), and even if the pixel interval of the emission layer opening1370varies (e.g., 5x5, 6x6, 3x3, etc.), when the pitches Wa and Wb respectively in the x direction and y direction of the emission layer opening1370are both within a suitable range (e.g., about 0.1 mm to about 2.5 mm), as in the described embodiments (e.g., about 1.157 mm, about 1.088 mm, about 1.116 mm, about 0.945 mm, etc.), it may be confirmed that the overall luminance deterioration and mura described above are not recognized.

The aspects of embodiments as described above are shown in all of the display devices1000and1000aaccording to embodiments described above. That is, according to some embodiments, the mura according to the non-uniform of the common voltage of the common electrode270is not recognized, and the uniformity of the luminance of the display area may be improved.

A laser processing apparatus used in a laser drilling process of a manufacturing method of a display device according to some embodiments will be described with reference toFIG.21.

FIG.21is a view showing a laser processing apparatus used in a manufacturing method of a display device according to some embodiments.

Referring toFIG.21, a laser processing apparatus used in a manufacturing method of a display device according to some embodiments may include a chamber2000, a protective window2002, a blocking unit (a baffle)2003, an optical unit2004, a scanner2005, and a diffraction optical element2006.

In the chamber2000, the substrate110, which is an object to be processed by a laser (e.g., by laser drilling), may be positioned. At least one layer is formed on the substrate110to form an opening therein by the laser drilling, such as an emission layer370, for example.

A portion of the chamber2000includes a transparent portion2001. The laser may pass through the transparent portion2001into the chamber2000.

The blocking unit2003is positioned between the substrate110and the transparent portion2001. The blocking unit2003has a hole through which the laser passing through the transparent portion2001may pass, so that the laser may be irradiated toward the substrate110.

The transparent protective window2002may be positioned between the blocking unit2003and the transparent portion2001. The protective window2002may be located so as to overlap the aperture of the blocking unit2003and the transparent portion2001.

When the emission layer opening1370is formed by irradiating laser to the emission layer370, particles PTC of the emission layer370that are removed are generated or released, and these particles PTC may be primarily blocked from adhering to the transparent portion2001by the blocking unit2003. However, the particles PTC that are not blocked by the blocking unit2003may be blocked secondarily by the transparent protective window2002overlapping the transparent portion2001, thereby preventing the transparent portion2001from being contaminated by the particles PTC.

The optical unit2004may change the direction of the incident laser. The optical unit2004may include, for example, at least one mirror. The laser irradiated from the laser source outside the chamber2000may be irradiated by changing the direction toward the transparent portion2001of the chamber2000through the optical unit2004.

The scanner2005may be positioned between the optical unit2004and the transparent portion2001of the chamber2000. The scanner2005scans the irradiated laser so as to be irradiated on the substrate110.

The diffraction optical element2006may be positioned between the scanner2005and the transparent portion2001. The diffraction optical element2006may be irradiated toward the transparent portion2001by branching one incident laser beam into a plurality of beams. Accordingly, the emission layer opening1370may be formed in a plurality of positions by using one laser beam. For example, in the display device1000aaccording to the previously described embodiments corresponding toFIG.12, a plurality of emission layer openings1370positioned in one opening formation region LDA may be simultaneously formed using a plurality of beams branched from one laser beam.

The output per unit area of the laser may be, for example, about 200 mJ/cm2or less, to reduce or prevent the likelihood of damage to the connection electrode195, but the present disclosure is not limited thereto. In addition, the laser may use, for example, a UV laser having a wavelength of about 300 nm to about 400 nm, but the present disclosure not limited thereto.

As described above, as the emission layer opening1370is formed on the emission layer370, the generated particles PTC are blocked by the protective window2002, thereby preventing the transparent portion2001of the chamber2000from being contaminated. However, because the protective window2002may be contaminated by particles PTC, replacement of the protective window2002may be suitable depending on the degree of the contamination.

Because the replacement of the protective window2002takes time, and therefore a process time increases accordingly, it may be suitable to reduce the contamination to reduce or minimize the replacement of the protective window2002. According to some embodiments, in the display devices1000and1000a, by making the pitches Wa and Wb in the x-direction or y-direction of the emission layer opening1370larger than the pixel pitch and limiting it to about 0.1 mm or more, the number or the time of the replacements of the protective windows2002may be optimized. In this case, when the length of a diagonal direction (a direction oblique to the x and y directions) of the display area of the display devices (1000,1000a) is about 15 inches to about 100 inches, as the minimum value of the pitches Wa and Wb of the emission layer opening1370may be limited to about 0.1 mm, it is possible to shorten and optimize the manufacturing process of one display panel.

FIG.22is a graph showing a change in a laser output according to a contamination of a protection window of a laser processing apparatus used in a manufacturing method of a display device according to some embodiments.

For example,FIG.22shows the change of the laser output irradiated to the substrate110according to the increase in the number of the display panels of the display devices to be manufactured when the emission layer opening1370is formed using the laser processing apparatus shown inFIG.21for two display devices1000and1000aaccording to embodiments described above.

As previously described, for all of the display device1000aaccording to some embodiments corresponding toFIG.12and of the display device1000according to some embodiments corresponding toFIG.11, the occurrence of the luminance non-uniformity and the mura due to deterioration of the global and local common voltage does not appear, and in the case of the display device1000a, because the number of the emission layer openings1370formed as a whole is smaller than the number of the emission layer openings1370of the display device1000, the amount of the particles PTC generated in the laser drilling process is relatively small in the manufacturing process of the display device1000a. Therefore, when one protective window2002is continuously used to form the emission layer opening1370on several display devices, as compared to the display device1000shown inFIG.11, in the case of the display device1000ashown inFIG.12, the deterioration of the laser output due to the contamination of the particle PTC is relatively quite slow. Therefore, in the manufacturing process of the display device1000ashown inFIG.12, the laser drilling process time may be relatively significantly shortened.

Description of Symbols