Display panel and driving method

A driving method, suitable for a display panel. The display panel includes a first display area, a second display area, a first gate driving circuit and a second gate driving circuit. The second display area comprises an opening. The driving method includes outputting a first gate signal to several first gate lines located at the first display area by the first gate driving circuit; outputting the first gate signal to several second gate lines located at the first display area by the second gate driving circuit, wherein the first gate lines and the second gate lines are arranged in an interlaced manner; outputting the first gate signal and a second gate signal to several third gate lines located at the second display area in the interlaced manner by the first gate driving circuit and the second gate driving circuit.

RELATED APPLICATIONS

This application claims priority to Taiwan Application Serial Number 108104853, filed Feb. 13, 2019, which is herein incorporated by reference.

BACKGROUND

Technical Field

The present disclosure relates to a display panel and a driving method. More particularly, the present disclosure relates to a display panel and a driving method with an opening.

Description of Related Art

At present, smart phone screens are getting bigger and bigger, and without increasing the size of mobile phones, many mobile phone manufacturers use high-resolution display panels with narrow borders or ultra-narrow bezels to increase the proportion of display parts. The display is enlarged. However, limited by the acousto-optic components on the phone (such as lenses, speakers, etc.), the proportion of the rectangular display panel is limited. Thus, a display panel with opening was developed to further increase the display panel's share. However, since the opening part cannot configure the line, the new layout method is proposed to be suitable for the display panel with opening so that the pixels on the display panel can be driven normally.

However, since the display area on both sides of the opening is unilaterally driven, the displayed display pixels are considered to be near-end and the waveforms are close to each other. Because the rest of the display area is single driven in an interlaced manner, the driven pixels are close to each other, and the waveforms will be different, resulting in a boundary phenomenon.

SUMMARY

One aspect of the present disclosure is related to a display panel including a first display area, a second display area, a first gate driving circuit and a second gate driving circuit, several first gate lines, several second gate lines, and several third gate lines. The second display area includes an opening and a first sub-display area, second sub-display area located at two sides of the opening. The first gate driving circuit and a second gate driving circuit are located at two sides of the first display area and the second display area. The several first gate lines are located at the first sub-display area, and the first gate lines are coupled to the first gate driving circuit. The several second gate lines are located at the second sub-display area and are coupled to the second gate driving circuit. The several third gate lines are located at the first display area and are coupled to one of the first gate lines and the second gate lines, and receive a first gate signal from one of the first gate lines and the second gate lines. The first gate driving circuit outputs the first gate signal and a second gate signal to the first gate lines in an interlaced manner. The second gate driving circuit outputs the first gate signal and the second gate signal to the second gate lines in an interlaced manner. A rise time of the second gate signal is longer than a rise time of the first gate signal, and a fall time of the second gate signal is longer than a fall time of the first gate signal.

One aspect of the present disclosure is related to a driving method, suitable for a display panel. The display panel includes a first display area, a second display area, a first gate driving circuit and a second gate driving circuit. The second display area comprises an opening. The driving method includes outputting a first gate signal to several first gate lines located at the first display area by the first gate driving circuit; outputting the first gate signal to several second gate lines located at the first display area by the second gate driving circuit, wherein the first gate lines and the second gate lines are arranged in an interlaced manner; outputting the first gate signal and a second gate signal in an interlaced manner to several third gate lines located at the second display area by the first gate driving circuit and the second gate driving circuit. A rise time of the second gate signal is longer than a rise time of the first gate signal, and a fall time of the second gate signal is longer than a fall time of the first gate signal.

Through the operations of one embodiment described above, by compensating the unilateral driving circuit located at the display area of two sides of the driving opening, so that the unilateral driving waveform is approximated to the near end and far end waveform in an interlaced manner of the one-sided driving circuits located at the display area.

DETAILED DESCRIPTION

It will be understood that, in the description herein and throughout the claims that follow, when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Moreover, “electrically connect” or “connect” can further refer to the interoperation or interaction between two or more elements.

It will be understood that, in the description herein and throughout the claims that follow, although the terms “first,” “second,” etc. may be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the embodiments.

It will be understood that, in the description herein and throughout the claims that follow, the terms “comprise” or “comprising,” “include” or “including,” “have” or “having,” “contain” or “containing” and the like used herein are to be understood to be open-ended, i.e., to mean including but not limited to.

It will be understood that, in the description herein and throughout the claims that follow, the phrase “and/or” includes any and all combinations of one or more of the associated listed items.

It will be understood that, in the description herein and throughout the claims that follow, words indicating direction used in the description of the following embodiments, such as “above,” “below,” “left,” “right,” “front” and “back,” are directions as they relate to the accompanying drawings. Therefore, such words indicating direction are used for illustration and do not limit the present disclosure.

Reference is made toFIG. 1.FIG. 1is a schematic diagram of a display panel100in accordance with some embodiments of the present disclosure. As illustrated inFIG. 1, the display panel100includes a display area AA, a gate driving circuit GD1, GD2. The display area AA includes display areas AA1and AA2. The display area AA1includes an opening OP and the sub-display areas AS1AND AS2located at two sides of the opening OP. The gate driving circuits GD1AND GD2are located at two sides of the display areas AA1and AA2.

The display panel100further includes gate lines F11to F13located at the sub-display area AS1, gate lines F21to F23located at the sub-display area AS2, gate lines F31to F36located at the display area AA2.

In the connection relationship, the gate lines F11to F13are coupled to the gate driving circuit GD1, and the gate lines F11to F13are coupled to the pixel circuit PX located at the sub-display area AS1. The gate lines F21to F23are coupled to the gate driving circuit GD2, and the gate lines F21to F23are coupled to the pixel circuit PX located at the sub-display area AS2. The gate lines F31to F36are coupled to the gate driving circuits GD1, GD2, and the gate lines F31to F36are coupled to the pixel circuit PX located at the display area AA2.

As illustrated inFIG. 1, the gate driving circuit GD1outputs the gate signals GS1, GS2to the gate lines F11to F13in an interlaced manner. The gate driving circuit GD2outputs the gate signals GS1, GS2to the gate lines F21to F23in an interlaced manner. The gate driving circuits GD1, GD2output gate signal GS1to the gate lines F31to F36.

In detail, the gate driving circuit GD1outputs the gate signal GS1to the gate line F11, the gate driving circuit GD1outputs the gate signal GS2to the gate line F12, the gate driving circuit GD1outputs the gate signal GS1to the gate line F13. On the other hand, the gate driving circuit GD2outputs the gate signal GS2to the gate line F21, the gate driving circuit GD2outputs the gate signal GS1to the gate line F22, the gate driving circuit GD2outputs the gate signal GS2to the gate line F23.

In the part of the display area AA2, the gate driving circuit GD2outputs the gate signal GS1to the gate lines F31, F33, F35, the gate driving circuit GD1outputs gate signal GS1to the gate lines F32, F34, F36.

The rise time of the gate signal GS2is longer than the rise time of the gate signal GS1, and the fall time of the gate signal GS2is longer than the fall time of the gate signal GS1.

Since the driving method of the display area AA2is a single drive mode with an interlaced manner. In this situation, the signal received by the near end of the gate lines F31to F36is the gate signal GS1. However, when transmitted to the far end of gate lines F31to F36, the waveform of the gate signal will be distorted, and the signal waveform of the far end of the gate lines F31to F36is the waveform of the gate signal GS2. In the embodiments of the present disclosure, in the area of the display area AA1, gate driving circuit GD1, GD2output gate signals GS1, GS2to the gate lines F11to F13and the gate lines F21to F23in an interlaced manner. In this way, the gate signals on the left and right sides of the display area AA1and AA2can be made uniform. That is, regardless of locating at the display area AA1or AA2, the gate signals received on the left and right sides are gate signals GS1, GS2in an interlaced manner. In this way, the occurrence of crossover phenomenon may be avoided.

In some embodiments, as illustrated inFIG. 1, the gate driving circuit GD1outputs the gate signal GS1to the odd-numbered gate lines of the gate lines F11to F13, the gate driving circuit GD1outputs the gate signal GS2to the even-numbered gate lines of the gate lines F11to F13. On the other hand, the gate driving circuit GD2outputs the gate signal GS1to the even-numbered gate lines of the gate lines F21to F23, the gate driving circuit GD2outputs the gate signal GS2to the odd-numbered gate lines of the gate lines F21to F23.

However, the present disclosure is not limited thereto. In some other embodiments, the gate driving circuit GD1outputs the gate signal GS1to the even-numbered gate lines of the gate lines F11to F13, the gate driving circuit GD1outputs gate signal GS2to the even-numbered gate lines of the gate lines F11to F13. On the other hand, the gate driving circuit GD2outputs the gate signal GS1to the even-numbered gate lines of the gate lines F21to F23, and the gate driving circuit GD2outputs the gate signal GS2to the even-numbered gate lines of the gate lines F21to F23.

In some embodiments, as illustrated inFIG. 1, the gate driving circuit GD1includes several shift registers LSR1to LSR6. The gate driving circuit GD2includes several shift registers RSR1to RSR6. The shift register LSR1outputs the gate signal GS1to the gate line F11, the shift register LSR2outputs the gate signal GS2to the gate line F12, and the shift register LSR3outputs the gate signal GS1to the gate line F13. On the other side, the shift register RSR1outputs the gate signal GS2to the gate line F21, the shift register RSR2outputs the gate signal GS1to the gate line F22, and the shift register RSR3outputs the gate signal GS2to the gate line F23.

That is, in the gate driving circuit GD1, the shift register LSR1, LSR3that outputs the gate signal GS1and the shift register LSR2that outputs the gate signal GS2are arranged in an interlaced manner. Similarly, in the gate driving circuit GD2, the shift register RSR2that outputs the gate signal GS1, and the shift register RSR1, RSR3that outputs the gate signal GS2are arranged in an interlaced manner.

Reference is made toFIG. 2.FIG. 2is a shift register200in accordance with some embodiments of the present disclosure. As illustrated inFIG. 2, the shift register200includes driving transistor G21, the pull-up transistor G22and the pull-down transistor G23, G24. In the connection relationship, the control terminal of the pull-up transistor G22is configured to receive the VGH voltage, a terminal of the pull-up transistor G22and the control terminal of the driving transistor G21are coupled to each other. A terminal of the driving transistor is configured to receive the clock signal CK. Another terminal of the driving transistor, a terminal of the pull-down transistor G23, a terminal of the pull-down transistor G24, and a terminal of the load L1are coupled to the node N21. The node N21is coupled to one of the several gate lines F11to F13, F21to F23, and F31to F36, so as to output the gate signal to the pixel circuit. Furthermore, the node N21is coupled to the next stage of the shift register, so as to output subordinate signal to the shift register which is in a next stage.

The shift register200as illustrated inFIG. 2may be used to represent the shift registers LSR1to LSR6, RSR1to RSR6as illustrated inFIG. 1. It should be noted that, in the shift registers LSR1to LSR6, RSR1to RSR6, the width to length ratio of the channel of the driving transistor G21of the shift register configured to output the gate signal GS1is larger than the width to length ratio of the channel of the driving transistor G21of the shift register configured to output the gate signal GS2. In this way, The rise time of the gate signal GS1output by the shift register is shorter than the rise time of the gate signal GS2output by the shift register, and the fall time of the gate signal GS1output by the shift register is shorter than the fall time of the gate signal GS2of the shift register output. The rise time of the gate signal GS1output by the shift register is shorter than the rise time of the gate signal GS2output by the shift register, and the fall time of the gate signal GS1output by the shift register is shorter than the fall time of the gate signal GS2output by the shift register.

Reference is made toFIG. 3.FIG. 3is a shift register300configured to output a gate signal in accordance with some embodiments of the present disclosure. As illustrated inFIG. 3, the shift register300includes a compensation transistor G31, driving transistor G32, pull-up transistor G33, and the pull-down transistor G34, G35, G36. In the connection relationship, the control terminal of the pull-up transistor G33is coupled to the voltage VGH, a terminal of the pull-up transistor G33is coupled to a control terminal of the compensation transistor G31and the control terminal of the driving transistor G32. That is, the compensation transistor G31and the driving transistor G32are series connected. A terminal of the compensation transistor G31and a terminal of the driving transistor G32are coupled to the clock signal CK. Another terminal of the compensation transistor G31is coupled to a terminal of the pull-down transistor G34. Another terminal of the driving transistor G32is coupled to a terminal of the pull-down transistor G3, a terminal of the pull-down transistor G36and the load L1. Furthermore, another terminal of the compensation transistor G31coupled to the shift register of the next stage, and the compensation transistor G31is configured to output a subordinate signal to the shift register which is in a next stage. Another terminal of the pull-up transistor G32is coupled to one of the several gate lines F11to F13, F21to F23and F31to F36, so as to output the gate signal to the pixel circuit.

In this case, the width to length ratio of the channel of the driving transistor G32, which is configured to output the of the gate signal GS2, of the shift register300is larger than the width to length ratio of the channel of the driving transistor G21, which is configured to output the gate signal GS1, of the shift register200. In this way, the rise time of the gate signal GS1output by the shift register is shorter than the rise time of the gate signal GS2output by the shift register, and the fall time of the gate signal GS1output by the shift register is shorter than the fall time of the gate signal GS2output by the shift register.

In some embodiments, the sum of the width to length ratio of the channel of the compensation transistor G31and the width to length ratio of the channel of the driving transistor G32is equal to the width to length ratio of the channel of the driving transistor G21. In this way, the parasitic capacitance of the shift register300that outputs the gate signal GS2is consistent or similar to the parasitic capacitance of the shift register200for outputting the gate signal GS1.

In some embodiments, as illustrated inFIG. 3, the shift register300further includes load L2. That is, the load on the gate line of the shift register300is larger than the load on the gate line of the shift register200. The shift register300is configured to output the gate signal GS2, and the shift register200is configured to output the gate signal GS1. In this way, it is also possible to make the rise time of the gate signal GS1output by the shift register shorter than the rise time of the gate signal GS2output by the shift register, and it is also possible to make the fall time of the gate signal GS1output by the shift register shorter than the fall time of the gate signal GS2output by the shift register.

Furthermore, inFIG. 3, since the pull-down transistors G34to G36are connected in series, the pull-down efficiency of the shift register300is better than the pull-down efficiency of the shift register200.

In the embodiments ofFIG. 3, by utilizing the feature that the width to length ratio of the channel of the driving transistor G32of the shift register300, configured to output the gate signal GS2, is smaller than the width to length ratio of the channel of the driving transistor G21of the shift register200, configured to output the gate signal GS1, so that the rise time of the gate signal GS1output by the shift register is shorter than the rise time of the gate signal GS2output by the shift register, and the fall time of the gate signal GS1output by the shift register is shorter than the fall time of the gate signal GS2output by the shift register. At the same time, since the reduction of the width to length ratio of the channel of the driving transistor G32may cause waveform distortion, which causes an error in the output of the subordinate signal. Therefore, by setting the compensation transistor G31, the signal with the same or similar waveform as the gate signal GS1is output through one end of the compensation transistor G31to avoid an error in the output of the subordinate signal.

Reference is made toFIG. 4.FIG. 4is a driving method400in accordance with some embodiments of the present disclosure. The driving method includes operations S410to S450. For convenience of illustration and description, reference is made toFIG. 1andFIG. 4.

In operation S410, outputting the first gate signal by the first gate driving circuit to several first gate lines located at the first display. For example, the gate driving circuit GD1as illustrated inFIG. 1outputs gate signal GS1to the gate lines F32, F34, F36located at the display area AA2.

In operation S430, outputting the first gate signal to several second gate lines located at the first display area by the second gate driving circuit, in which several first gate lines are arranged with several second gate lines in an interlaced manner. For example, the gate driving circuit GD2as illustrated inFIG. 1outputs the gate signal GS1to the gate lines F31, F33, F35located at the display area AA2. The gate lines F32, F34, F36and the gate lines F31, F33, F35are arranged in an interlaced manner.

In operation S450, outputting the first gate signal and the second gate signal in an interlaced manner to several third gate lines located at the second display area by the first gate driving circuit and the second gate driving circuit. For example, the gate driving circuit GD1as illustrated inFIG. 1outputs gate signal GS1to the gate line F12, and the gate driving circuit GD1as illustrated inFIG. 1outputs the gate signal GS2to the gate lines F11, F13. The gate driving circuit GD2as illustrated inFIG. 1outputs the gate signal GS1to the gate lines F21, F23, and the gate driving circuit GD2as illustrated inFIG. 1outputs the gate signal GS2to the gate line F22.

The rise time of the gate signal GS2is longer than the rise time of the gate signal GS1, and the fall time of the gate signal GS2is longer than the fall time of the gate signal GS1. In this way, in the area of the display area AA1, the gate driving circuit GD1, GD2output gate signal GS1, GS2to the gate lines F11to F13and the gate lines F21to F23in an interlaced manner. In this way, the gate signals on the left and right sides of the display areas AA1and AA2may be the same. That is, regardless of the display area AA1or AA2, the gate signals received on the left and right sides are gate signals GS1, GS2in an interlaced manner.

In practice, the transistors G21to G24and G31to G36inFIG. 2andFIG. 3may be realized by a P-type low-temperature polycrystalline germanium film transistor, but the embodiments of the present disclosure are not limited thereto. For example, the transistors G21to G24, G31to G36may also be realized with a P-type amorphous silicon thin film transistor. In some embodiments, an N-type thin film transistor may also be used, and the present disclosure does not limit the transistor type employed.

The embodiments of the present disclosure are to provide a display panel and a driving method. By compensating the unilateral driving circuit located at the display area of both sides of the driving opening, the unilateral driving waveform is approximated to the near-end and far-end interleaved waveform of the interleaved single-drive display area to avoid crossover phenomenon.

Although the present invention has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the scope of the appended claims should not be limited to the description of the embodiments contained herein.