Testing system and testing method

A testing system includes a plurality of memory circuits and a testing circuit. The testing circuit is coupled to the memory circuits. The testing circuit is configured to perform a read/write operation on the memory circuits, and each of the memory circuits has a read/write starting time point corresponding to the read/write operation. The testing circuit is further configured to control the read/write starting time points of the memory circuits to be different from each other.

RELATED APPLICATIONS

This application claims priority to Taiwanese Application Serial Number 111101719, filed Jan. 14, 2022, which is herein incorporated by reference.

BACKGROUND

Technical Field

The present disclosure relates to testing technology. More particularly, the present disclosure relates to a testing system and a testing method for testing memory circuits.

Description of Related Art

With developments of technology, there are more and more memories in an electronic device. However, based on the manufacturing process or other factors, the memories may have defects. In some related arts, a testing circuit can be used to test the memories to determine whether the memories have defects.

SUMMARY

Some aspects of the present disclosure are to provide a testing system. The testing system includes a plurality of memory circuits and a testing circuit. The testing circuit is coupled to the memory circuits. The testing circuit is configured to perform a read/write operation on the memory circuits, and each of the memory circuits has a read/write starting time point corresponding to the read/write operation. The testing circuit is further configured to control the read/write starting time points of the memory circuits to be different from each other.

Some aspects of the present disclosure are to provide a testing method. The testing method includes following operations: performing, by a testing circuit, a read/write operation on a plurality of memory circuits, in which each of the memory circuits has a read/write starting time point corresponding to the read/write operation; and controlling, by the testing circuit, the read/write starting time points of the memory circuits to be different from each other.

As described above, the present disclosure uses a single testing circuit to test the multiple memory circuits, and the testing circuit can stagger the read/write starting time points of the memory circuits. Accordingly, the present disclosure can avoid excessive instantaneous voltage drop without increasing (or significantly increasing) the circuit area and without increasing the testing time to ensure that the circuit works correctly.

DETAILED DESCRIPTION

In the present disclosure, “connected” or “coupled” may refer to “electrically connected” or “electrically coupled.” “Connected” or “coupled” may also refer to operations or actions between two or more elements.

Reference is made toFIG.1.FIG.1is a schematic diagram of a testing system100according to some embodiments of the present disclosure.

As illustrated inFIG.1, the testing system100includes memory circuits M1-M3and a testing circuit120. The testing circuit120is coupled to the memory circuits M1-M3. In some embodiments, the testing circuit120is implemented by a memory built-in self test (MBIST) circuit, and the memory circuits M1-M3are integrated on a single chip.

In some embodiments, storage capacities of the memory circuits M1-M3are different from each other. In some other embodiments, the storage capacities of the memory circuits M1-M3are not different from each other.

For better understanding, the storage capacities of the memory circuits M1-M3are different from each other in the following example, but the present disclosure is not limited thereto. As illustrated inFIG.1, the memory circuit M1has Q entries, the memory circuit M2has P entries, and the memory circuit M3has N entries, in which Q, P, N are positive integers, Q is greater than P and P is greater than N. In other words, the storage capacity of the memory circuit M1is greater than the storage capacity of the memory circuit M2, and the storage capacity of the memory circuit M2is greater than the storage capacity of the memory circuit M3.

It is noted that the quantity of the memory circuits inFIG.1is merely for illustration and various suitable quantities are in the contemplated scopes of the present disclosure.

The testing circuit120can be understood as a memory access controller and is used to perform a read/write operation on the memory circuits M1-M3to test them. For the same read/write operation, all entries in the memory circuits M1-M3are read or written. In other words, for the same read/write operation, a total work time interval of the memory circuit M1with the most entries (storage capacity is greatest) is the longest, and a total work time interval of the memory circuit M3with the fewest entries is the shortest.

References are made toFIG.1andFIG.2.FIG.2is a diagram showing operation timeline of the testing system100inFIG.1according to some embodiments of the present disclosure. The testing circuit120can control read/write starting time points ST1-ST3of the memory circuits M1-M3to be different from each other based on a clock signal CLK. As illustrated inFIG.2, for the same read/write operation, the testing circuit120can perform the read/write operation on the memory circuit M1at the read/write starting time point ST1based on the clock signal CLK, perform the read/write operation on the memory circuit M2at the read/write starting time point ST2based on the clock signal CLK, and perform the read/write operation to be performed on the memory circuit M3at the read/write starting time point ST3based on the clock signal CLK.

As illustrated inFIG.1, the testing circuit120includes an enabling signal generator circuit121, an address generator circuit122, an offset circuit123and an offset circuit124.

The enabling signal generator circuit121is used to generate and output enabling signals EN1-EN3. The enabling signals EN1-EN3are mainly used to enable or disable the memory circuits M1-M3. The address generator circuit122is used to generate and output an address signal AD. The address signal AD is mainly used to determine which entries in the memory circuits M1-M3the read/write operation is performed on.

InFIG.1, the enabling signal generator circuit121and the address generator circuit122are coupled to the memory circuit M1. The memory circuit M1can receive the enabling signal EN1from the enabling signal generator circuit121and the address signal AD from the address generator circuit122. Accordingly, when the enabling signal EN1has an enable level at the read/write starting time point ST1, the read/write operation can be performed on the memory circuit M1according to the enabling signal EN1and the address signal AD at the read/write starting time point ST1.

In addition, the enabling signal generator circuit121and the address generator circuit122are coupled to the offset circuit123, and the offset circuit123is coupled to the memory circuit M2. The offset circuit123can receive the enabling signal EN2from the enabling signal generator circuit121and the address signal AD from the address generator circuit122. Then, the offset circuit123can generate an offset signal DS1according to the enabling signal EN2and the address signal AD. The read/write operation can be performed on the memory circuit M2according to the offset signal DS1at the read/write starting time point ST2.

In some embodiments, the offset circuit123can include a comparator. The comparator compares an address value carried in the address signal AD and a first offset value (e.g., 256). The address value carried in the address signal AD can count down from an initial address value (e.g., 0). When the current address value (e.g., 256) carried in the address signal AD is identical to a first shifting value (e.g., the starting time point ST2), the enabling signal EN2has an enable level. Thus, the offset circuit123can generate the offset signal DS1to enable the memory circuit M2at the read/write starting time point ST2and determine which entry (e.g., entry 0) in the memory circuit M2is to be read or written according to a difference value between the current address value and the first shifting value (e.g., 256−256=0).

Similarly, the enabling signal generator circuit121and the address generator circuit122are coupled to the offset circuit124, and the offset circuit124is coupled to the memory circuit M3. The offset circuit124can receive the enabling signal EN3from the enabling signal generator circuit121and the address signal AD from the address generator circuit122. Then, the offset circuit124can generate an offset signal DS2according to the enabling signal EN3and the address signal AD. The read/write operation can be performed on the memory circuit M3according to the offset signal DS2at the read/write starting time point ST3.

Similarly, in some embodiments, the offset circuit124can include a comparator. The comparator compares an address value carried in the address signal AD and a second offset value (e.g., 128). As described above, the address value carried in the address signal AD can count down from an initial address value (e.g., 0). When the current address value (e.g., 128) carried in the address signal AD is identical to a second shifting value (e.g., the starting time point ST3), the enabling signal EN3has an enable level. Thus, the offset circuit124can generate the offset signal DS2to enable the memory circuit M3at the read/write starting time point ST3and determine which entry (e.g., entry 0) in the memory circuit M3is to be read or written according to a difference value between the current address value and the second shifting value (e.g., 128−128=0).

As illustrated inFIG.2, the read/write starting time point ST1is earlier than the read/write starting time point ST3, and the read/write starting time point ST3is earlier than the read/write starting time point ST2. In other words, the read/write starting time point ST1of the memory circuit M1with the greatest storage capacity is the earliest. There is a first delay time interval (marked with dots) between the read/write starting time point ST3and the read/write starting time point ST1, and there is a second delay time interval (marked with dots) between the read/write starting time point ST2and the read/write starting time point ST1, and the second delay time interval is longer than the first delay time interval. It is noted that the read/write starting time point ST3inFIG.2is earlier than the read/write starting time point ST2, but the present disclosure is not limited thereto. In some other embodiments, the read/write starting time point ST3can be later than the read/write starting time point ST2.

The time interval (work time interval) between the read/write starting time point of a memory circuit and read/write ending time point of this memory circuit is positively related to the storage capacity of this memory circuit. As illustrated inFIG.2, since the storage capacity of the memory circuit M1is the greatest, the time interval between the read/write starting time point ST1of the memory circuit M1and a read/write ending time point ET1of the memory circuit M1is the longest. Since the storage capacity of the memory circuit M3is the smallest, the time interval between the read/write starting time point ST3of the memory circuit M3and a read/write ending time point ET3of the memory circuit M3is the shortest.

In some embodiments, the testing circuit120can control a read/write ending time point ET2of the memory circuit M2and the read/write ending time point ET3of the memory circuit M3not later than (aligned with or earlier than) the read/write ending time point ET1of the memory circuit M1with the largest storage capacity. Accordingly, it can avoid extra testing time. In the example inFIG.2, the testing circuit120controls the read/write ending time point ET1of the memory circuit M1, the read/write ending time point ET2of the memory circuit M2, and the read/write ending time point ET3of the memory circuit M3to be different from each other.

In some embodiments, a disable timing point of a memory circuit is the read/write ending time point of this memory circuit. As illustrated inFIG.1andFIG.2, the enabling signal EN1has a disable level at the read/write ending time point ET1to disable the memory circuit M1. The enabling signal EN2has a disable level at the read/write ending time point ET2such that the offset signal DS1can be used to disable the memory circuit M2. The enabling signal EN3has a disable level at the read/write ending time point ET3such that the offset signal DS2can be used to disable the memory circuit M3. Accordingly, it can reduce power consumption.

In some other embodiments, the disable levels of all memory circuits M1-M3are identical to the read/write ending time point of the memory circuit M1with the greatest storage capacity. In other words, all of the enabling signals EN1-EN3has the disable level at the read/write ending time point ET1to disable the memory circuits M1-M3. The time interval between the read/write ending time point ET2of the memory circuit M2and the read/write ending time point ET1of the memory circuit M1is an idle time interval of the memory circuit M2, and the time interval between the read/write ending time point ET3of the memory circuit M3and the read/write ending time point ET1of the memory circuit M1is an idle time interval of the memory circuit M3.

In some related arts, in order to save the circuit area of the testing circuit, a single testing circuit is used to test multiple memory circuits. In these arts, when the testing process starts (from the idle state to the testing state), a large current is generated. The large current can cause insufficient power supply and result in an excessive instantaneous voltage drop and circuit failure.

In some related arts, in order to avoid excessive instantaneous voltage drop, multiple testing circuits are used to test the multiple memory circuits. However, this increases the area of the testing circuit and thus increases the overall chip size. In other related arts, in order to avoid excessive instantaneous voltage drop, the memory circuits are divided into multiple groups and the groups are tested by a time division mechanism. However, this increases testing time.

Compared to the aforementioned related arts, in the present disclosure, the single testing circuit120is used to test the memory circuits M1-M3, and the testing circuit120can stagger the read/write starting time points ST1-ST3of the memory circuits M1-M3. Accordingly, the present disclosure can avoid excessive instantaneous voltage drop caused by the large current without increasing (or significantly increasing) the circuit area and without increasing the testing time to ensure that the circuit works correctly. When the work time intervals of the memory circuits M1-M3overlap less, the effect of avoiding the large current is better.

Reference is made toFIG.3.FIG.3is a schematic diagram of an offset value generator circuit300according to some embodiments of the present disclosure. In some embodiments, the offset circuit123or124inFIG.1further includes the offset value generator circuit300, and the offset value generator circuit300is used to generate the aforementioned first offset value (referenced as OF1inFIG.3) or the aforementioned second offset value (referenced as OF2inFIG.3).

As illustrated inFIG.3, the offset value generator circuit300includes a multiplexer310and a register320. The multiplexer310includes multiple input terminals. One of the input terminals of the multiplexer310is coupled to the register320, and other input terminals of the multiplexer310are used to receive a candidate offset value OFFSET1, a candidate offset value OFFSET2, and a candidate offset value OFFSET3respectively. The register320can generate a candidate offset value OFFSET4based on system requirements or application scenarios and according to a user operation or a command from a control circuit.

The multiplexer310can output one of the candidate offset value OFFSET1, the candidate offset value OFFSET2, the candidate offset value OFFSET3, and the candidate offset value OFFSET4according to a selection signal SS to be the aforementioned first offset value OF1or the aforementioned second offset value OF2. The selection signal SS can be generated based on system requirements or application scenarios and according to a user operation or a command from a control circuit. Then, as described above, the offset circuit123or124can generate the offset signal DS1or DS2according to the first offset value OF1or the second offset value OF2.

Since the candidate offset value OFFSET4or the selection signal SS can be adjusted based on the system requirements or the application scenarios, this architecture has greater flexibility and is applicable to more environments.

It is noted that the quantity of the candidate offset values or the register inFIG.3is merely for illustration and various suitable quantities are in the contemplated scopes of the present disclosure.

Reference is made toFIG.4.FIG.4is a flow diagram of a testing method400according to some embodiments of the present disclosure. As illustrated inFIG.4, the testing method400includes operation S410and operation S420.

In some embodiments, the testing method400can be implemented to the testing system100inFIG.1, but the present disclosure is not limited thereto. However, for better understanding, the testing method400is described with the testing system100inFIG.1.

In operation S410, the testing circuit120performs the read/write operation on the memory circuits M1-M3. Each of the memory circuits M1-M3has one read/write starting time point corresponding to the read/write operation. As illustrated inFIG.2, the memory circuit M1corresponds to the read/write starting time point ST1, the memory circuit M2corresponds to the read/write starting time point ST2, and the memory circuit M3corresponds to the read/write starting time point ST3.

In operation S420, the testing circuit120controls the read/write starting time points ST1-ST3of the memory circuits M1-M3to be different from each other. In some embodiments, the read/write starting time point ST1of the memory circuit M1with the greatest storage capacity is earliest, and the read/write starting time points ST2-ST3of the memory circuit M2-M3are later than the read/write starting time point ST1.

As described above, the present disclosure uses a single testing circuit to test the multiple memory circuits, and the testing circuit can stagger the read/write starting time points of the memory circuits. Accordingly, the present disclosure can avoid excessive instantaneous voltage drop without increasing (or significantly increasing) the circuit area and without increasing the testing time to ensure that the circuit works correctly.