Memory arrays

A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually include a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. At least a portion of the channel region is horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions. The memory cells individually include a capacitor comprising first and second electrodes having a capacitor insulator there-between. The first electrode is electrically coupled to the first source/drain region. The second capacitor electrodes of multiple of the capacitors in the array are electrically coupled with one another. A sense-line structure extends elevationally through the vertically-alternating tiers. Individual of the second source/drain regions of individual of the transistors that are in different memory cell tiers are electrically coupled to the elevationally-extending sense-line structure. Additional embodiments are disclosed.

TECHNICAL FIELD

Embodiments disclosed herein pertain to memory arrays.

BACKGROUND

Memory cells may be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for extended periods of time in the absence of power. Non-volatile memory is conventionally specified to be memory having a retention time of at least about 10 years. Volatile memory dissipates, and is therefore refreshed/rewritten to maintain data storage. Volatile memory may have a retention time of milliseconds or less. Regardless, memory cells are configured to retain or store memory in at least two different selectable states. In a binary system, the states are considered as either a “0” or a “1”. In other systems, at least some individual memory cells may be configured to store more than two levels or states of information.

A capacitor is one type of electronic component that may be used in a memory cell. A capacitor has two electrical conductors separated by electrically insulating material. Energy as an electric field may be electrostatically stored within such material. Depending on composition of the insulator material, that stored field will be volatile or non-volatile. For example, a capacitor insulator material including only SiO2will be volatile. One type of non-volatile capacitor is a ferroelectric capacitor which has ferroelectric material as at least part of the insulating material. Ferroelectric materials are characterized by having two stable polarized states and thereby can comprise programmable material of a capacitor and/or memory cell. The polarization state of the ferroelectric material can be changed by application of suitable programming voltages, and remains after removal of the programming voltage (at least for a time). Each polarization state has a different charge-stored capacitance from the other, and which ideally can be used to write (i.e., store) and read a memory state without reversing the polarization state until such is desired to be reversed. Less desirable, in some memory having ferroelectric capacitors the act of reading the memory state can reverse the polarization. Accordingly, upon determining the polarization state, a re-write of the memory cell is conducted to put the memory cell into the pre-read state immediately after its determination. Regardless, a memory cell incorporating a ferroelectric capacitor ideally is non-volatile due to the bi-stable characteristics of the ferroelectric material that forms a part of the capacitor. Programmable materials other than ferroelectric materials may be used as a capacitor insulator to render capacitors non-volatile.

A field effect transistor is one type of electronic component that may be used in a memory cell. These transistors comprise a pair of conductive source/drain regions having a semiconductive channel region there-between. A conductive gate is adjacent the channel region and separated there-from by a thin gate insulator. Application of a suitable voltage to the gate allows current to flow from one of the source/drain regions to the other through the channel region. When the voltage is removed from the gate, current is largely prevented from flowing through the channel region. Field effect transistors may also include additional structure, for example reversibly programmable charge storage/trap regions as part of the gate construction between the gate insulator and the conductive gate.

One type of transistor is a ferroelectric field effect transistor (FeFET) wherein at least some portion of the gate construction (e.g., the gate insulator) comprises ferroelectric material. The two different polarized states of the ferroelectric material in field effect transistors may be characterized by different threshold voltage (Vt) for the transistor or by different channel conductivity for a selected operating voltage. Again, polarization state of the ferroelectric material can be changed by application of suitable programming voltages, and which results in one of high channel conductance or low channel conductance. The high and low conductance, invoked by the ferroelectric polarization state, remains after removal of the gate programming voltage (at least for a time). The status of the channel can be read by applying a small drain voltage which does not disturb the ferroelectric polarization. Programmable materials other than ferroelectric materials may be used as a gate insulator to render a transistor to be non-volatile.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Embodiments of the invention encompass memory arrays. A first example embodiment is shown in and described with references toFIGS.1-5. Such includes a substrate structure or construction8comprising a memory array10fabricated relative to a base substrate11. Substrate11may comprise any one or more of conductive/conductor/conducting (i.e., electrically herein), semiconductive/semiconductor/semiconducting, and insulative/insulator/insulating (i.e., electrically herein) materials. Various materials have been formed elevationally over base substrate11. Materials may be aside, elevationally inward, or elevationally outward of theFIGS.1-5—depicted materials. For example, other partially or wholly fabricated components of integrated circuitry may be provided somewhere above, about, or within base substrate11. Control and/or other peripheral circuitry for operating components within a memory array may also be fabricated, and may or may not be wholly or partially within a memory array or sub-array. Further, multiple sub-arrays may also be fabricated and operated independently, in tandem, or otherwise relative one another. As used in this document, a “sub-array” may also be considered as an array.

Construction8includes vertically-alternating tiers12and14of insulative material16(e.g., comprising, consisting essentially of, or consisting of carbon-doped silicon nitride [2 to 10 atomic percent carbon], silicon nitride, and/or doped or undoped silicon dioxide deposited to a thickness of 200 Angstroms to 500 Angstroms) and memory cells19, respectively. Only three memory cell outlines19are shown inFIG.1for clarity, although three complete and three partial memory cells are visible inFIG.1. Analogously, only six memory cell outlines19are shown inFIGS.2and3, although more memory cells are visible inFIGS.2and3. Memory cell tiers14may be of the same or different thickness as that of insulative material tiers12, with different and greater thickness being shown (e.g., 500 Angstroms to 2,000 Angstroms). Construction8is shown as having seven vertically-alternating tiers12and14, although fewer or likely many more (e.g., dozens, hundreds, etc.) may be formed. Accordingly, more tiers12and14may be below the depicted tiers and above base substrate11and/or more tiers12and14may be above the depicted tiers.

Memory cells19individually comprise a transistor25and a capacitor34. Transistor25comprises a first source/drain region20and a second source/drain region22(e.g., conductively-doped semiconductor material such as polysilicon for each) having a channel region24there-between (e.g., doped semiconductor material, such as polysilicon, but not to be intrinsically conductive). In some embodiments (but not shown), a conductively-doped semiconductor region and/or or an electrically semiconductive region (e.g., LDD and/or halo regions) may be between channel region24and one or both of source/drain regions20and22.

A gate26or27(e.g., one or more of elemental metal, a mixture or alloy of two or more elementals, conductive metal compounds, and conductively-doped semiconductive materials) is operatively proximate channel region24. Specifically, in the depicted example, a gate insulator material28(e.g., silicon dioxide, silicon nitride, hafnium oxide, other high k insulator material, and/or ferroelectric material) is between gate26/27and channel region24. In one embodiment and as shown, individual memory cell tiers14comprise gate26and another gate27, with one of such gates (e.g., gate26) being directly above the other (e.g., gate27) in that individual memory cell tier14. At least a portion of channel region24is horizontally-oriented for horizontal current flow in the portion between first source/drain region20and second source/drain region22. In the depicted example embodiment, all of channel region24is horizontally-oriented for horizontal current flow there-through. Regardless, when suitable voltage is applied to gate26and/or27, a conductive channel can form within channel region24proximate gate insulator material28such that current is capable of flowing between source/drain regions20and22.

In one embodiment and as shown, channel region24comprises an annulus40in a straight-line horizontal cross-section (e.g., the cross-section shown byFIG.3). In one embodiment and as shown, gate26comprises an annulus44in a straight-line horizontal cross-section. (e.g., the cross-section shown byFIG.2). In one embodiment and as shown, first source/drain region20comprises an annulus41in a straight-line horizontal cross-section (e.g., the cross-section shown byFIG.3). In one embodiment and as shown, second source/drain region22comprises an annulus42in a straight-line horizontal cross-section (e.g., the cross-section shown byFIG.3).

One or both of gates26and27may be part of an access line (e.g., two access lines90x and90y being shown) interconnecting multiple transistors along a row or a column. Regardless, in one embodiment that includes both of gates26and27, such gates are directly electrically coupled to one. As examples, and by way of examples only, one or more staircase regions15(one being shown inFIGS.2,3, and5) may be provided at an end of or as a part of array10. Staircase region15as shown comprises staggered contact openings96individually having a conductive via97(e.g., metal material) therein that directly electrically couples together vertically-stacked gates26and27in individual memory cell tiers14. Conductive vias97may connect with a respective conductive control and/or access line (not shown) to separately access gate line pairs26,27in each memory cell tier14.

Capacitor34comprises a first electrode46and a second electrode48(e.g., conductively-doped semiconductive material and/or metal material for each) having a capacitor insulator50there-between (e.g., silicon dioxide, silicon nitride, hafnium oxide, other high k insulator material, and/or ferroelectric material). Second capacitor electrode material48and capacitor insulator50are not separately distinguishable inFIG.3due to scale. First electrode46is electrically coupled, in one embodiment directly electrically coupled, to first source/drain region20. Second electrodes48of multiple of capacitors34in array10are electrically coupled, in one embodiment are directly electrically coupled, with one another. In one embodiment, all such second electrodes of all capacitors in array10are electrically coupled with one another, and in one embodiment are directly electrically coupled with one another. In one embodiment and as shown, second electrode48is both directly above and directly below first electrode46in a straight-line vertical cross-section (e.g., the cross-section depicted byFIG.1). In one embodiment and as shown, first electrode46comprises an annulus45in a straight-line horizontal cross-section (e.g., the cross-section shown byFIG.3), and in one embodiment second electrode48comprises an annulus53in a straight-line horizontal cross-section (e.g., the cross-section shown byFIG.3). In one embodiment and as shown, one gate26or27(e.g.,26) extends longitudinally directly above capacitor34in a straight-line vertical cross-section (e.g., the cross-section shown byFIG.1), and in one embodiment other gate26or27(e.g.,27) extends longitudinally directly under capacitor34in a straight-line vertical cross-section (e.g., the cross-section shown byFIG.1).

In one embodiment, a capacitor-electrode structure52(e.g., a solid or hollow pillar, a solid or hollow wall, etc.) extends elevationally through vertically-alternating tiers12and14, with individual of second electrodes48of individual capacitors34that are in different memory cell tiers14being electrically coupled, in one embodiment directly electrically coupled, to elevationally-extending capacitor-electrode structure52. Example materials for capacitor-electrode structure52are metal materials and conductively-doped semiconductor material. In one embodiment and as shown, capacitor-electrode structure52extends vertically or within 10° of vertical. In one embodiment and as shown, capacitor-electrode structure52comprises an elevationally-extending wall55that is longitudinally-elongated horizontally and that directly electrically couples the individual second capacitor together. In one embodiment, such, by way of example only, is one example of how second capacitor electrodes48of multiple of capacitors34that are in different memory cell tiers14in the array may be electrically coupled with one another. In one embodiment, capacitor-electrode structure52is directly electrically coupled to a horizontally-elongated capacitor-electrode construction29(e.g., a line or a plate) that is above or below (above being shown) vertically-alternating tiers12and14. Construction(s)29may, in one embodiment, directly electrically couple together all second electrodes48within the array.

A sense line is electrically coupled, in one embodiment directly electrically coupled, to multiple of the second source/drain regions of individual of the transistors that are in different memory cell tiers. In one embodiment and as shown, a sense-line structure56(e.g., a solid or hollow pillar, a solid or hollow wall, etc.) extends elevationally through vertically-alternating tiers12and14, with individual of second source/drain regions22of individual transistors25that are in different memory cell tiers14being electrically coupled, in one embodiment directly electrically coupled, thereto. In one embodiment and as shown, sense-line structure56extends vertically or within 10° of vertical. In one embodiment and as shown, sense-line structure56comprises a pillar59. In one embodiment and as shown, sense-line structure56comprises a peripheral conductively-doped semiconductive material58(e.g., poly silicon) and a central metal material core60(e.g., titanium nitride and/or tungsten). In one embodiment, sense-line structure56is directly electrically coupled to a horizontal longitudinally-elongated sense line57that is above or below (below being shown) vertically-alternating tiers12and14.

Example insulator material47(e.g., silicon nitride) and insulator material49(e.g., silicon dioxide) may be provided as shown for suitable isolation in sub-tiers of memory cell tiers14.

An alternate embodiment construction8a of a memory array10is shown inFIG.6. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix “a”. Only one tier14a and two tiers12are shown for clarity. The channel region of transistor25a comprises two channel-region segments24a that are spaced elevationally apart from one another in a straight-line vertical cross-section (e.g., the cross-section shown byFIG.1). In one such embodiment, such two channel-region segments24a are directly electrically coupled to one another, and in one such embodiment as shown are so coupled by first source/drain region20a. In one embodiment and as shown, second electrode48a of capacitor34a is not both directly above and directly below first electrode46a in any straight-line vertical cross-section. In one embodiment and as shown, first electrode46a is both directly above and directly below second electrode48a in a straight-line vertical cross-section (e.g., the cross-section shown byFIG.1). Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

FIG.7shows another example alternate embodiment construction8b of a memory array10, with individual memory cells comprising a transistor25b and a capacitor34b. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix “b”. Again, only one tier14b and two tiers12are shown. Transistor25b comprises only a single gate26(e.g., no additional gate27) associated with channel region24. Such is shown as being above channel region24, although such may alternately be there-below. Accordingly, capacitor34b may be considered as being single-sided whereas capacitors34and34a may be considered as being at least double-sided (e.g., top and bottom sided with respect to capacitor electrode48,48a). Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

In one embodiment, individual of the memory cell tiers have no two of the memory cells that are directly above and directly below one another in that individual memory cell tier. For example, and by way of example only, the above described embodiments with respect toFIGS.1-7show such example embodiments. Alternately, and by way of example only, individual of the memory cell tiers may comprise two of the memory cells where one of which is directly above the other in that individual tier of memory cells. A first example such embodiment is shown and described with respect toFIG.8and a construction8c of a memory array10. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix “c”. Again, only one tier14c and two tiers12are shown.

Individual memory cells19in a single tier14c are shown as comprising a transistor25c and a capacitor34c. One of memory cells19is above another memory cell19in an individual tier14c as shown in the example embodiment. In one embodiment as shown, each capacitor34c shares a capacitor electrode48c that extends to or is part of capacitor-electrode structure52. Second source/drain regions22of the depicted different transistors25c may be electrically coupled, in one embodiment directly electrically coupled, to one another for example as shown by conductive materials58and60as part of sense-line structure56. First source/drain regions20of each transistor25c are not directly electrically coupled to one another, and are electrically coupled, in one embodiment directly electrically coupled, with respective first capacitor electrodes46c. Thereby, two vertically-stacked memory cells19(one directly above the other) are formed within a single memory cell tier14c. Transistor gates26and27, in one embodiment, are not directly electrically coupled to one another which may enable better separate access/control with respect to different transistors25c that are above and below one another within an individual memory cell tier14c. Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

A second example such embodiment is shown and described with respect toFIG.9and a construction8d of a memory array10. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix “d”. Again, only one tier14d and two tiers12are shown. Example construction8d is very similar to construction8c, with each memory cell19having a transistor25d and capacitor34c. Transistor25d differs from transistor25c in having second source/drain regions22d that integrally connect with one another elevationally along and aside sense-line structure56. Still, individual memory cell tiers14d comprise two of memory cells19where one of such is directly above the other in that individual tier of memory cells.

In one embodiment that includes both of gates26and27, such gates are not directly coupled to one another. For example, such an embodiment is shown and described with respect toFIGS.10-12and a construction8e of a memory array. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix “e”. Staircase region15e comprises staggered contact openings96e individually having a conductive via97e therein that separately extend to different individual gates26and27in individual memory cell tiers14, thereby not directly coupling together gates26and27in individual memory cell tiers14.

The above example structures may be manufactured by any existing or yet-to-be-developed techniques. One example technique of manufacturing the embodiment shown byFIGS.1-5is described with reference toFIGS.13-52. Like numerals from the above-described embodiments have been used for predecessor construction(s), regions, and like/predecessor materials thereof.

FIGS.13and14show an example portion of a predecessor to the construction or stack ofFIGS.1-5. The person of skill in the art may select any suitable different combinations of materials recognizing, in accordance with the continuing description, that certain materials will be etched selectively relative to other materials in the example method. As examples, and consistent with those described above, example material16for insulative-material tiers12is carbon-doped silicon nitride (2 to 10 atomic percent carbon). An example thickness for insulative material16is 200 to 500 Angstroms. Construction8includes a stack of materials or layers26,47,49,47, and27(top-to-bottom), and each of which may be considered as a sub-tier within what will be memory cell tiers14. Example thickness for each of materials26,47, and27is 100 to 400 Angstroms, with example gate materials26and27being n+ conductively-doped polysilicon. An example insulator material47is silicon nitride. Materials26and/or27may be sacrificial and replaced by conductively-doped semiconductive material and/or metal material. An example insulator material49is silicon dioxide, with an example thickness being 300 to 600 Angstroms. Construction8has been patterned to form staircase region15whereby individual gate materials26and27in individual memory cell tiers14form uppermost surfaces of so-called “stairs” that may subsequently be upwardly-exposed as will become apparent from the continuing discussion. Example silicon-dioxide-insulator material49is atop the stairs in staircase region15.

Referring toFIGS.15and16, openings33have been formed in and through the depicted stack of materials in an offset or staggered manner. The centers of example openings33are centered relative to what will be the centers of sense-line structures56(not shown) and annuli40,41,42, and44(not shown).

Referring toFIGS.17and18, substrate construction8ofFIGS.15and16has been subjected to suitable etching whereby material49has been etched laterally/radially selectively relative to the other depicted materials effective to widen openings33within memory cell tiers14. With respect to the above example materials, an example etching chemistry is dilute HF. An example uppermost silicon nitride insulator layer47protects example silicon-dioxide-insulator material49there-under from being etched in staircase region15.

Referring toFIGS.19and20, second capacitor electrode material48(e.g., titanium nitride at 30 to 60 Angstroms), capacitor insulator50/gate insulator28(e.g., silicon dioxide and/or a high k insulator at 30 to 60 Angstroms), and first capacitor electrode material46—first source/drain material20(e.g., conductively-dope polysilicon at 50 to 100 Angstroms) have been deposited as shown. Second capacitor electrode material48and capacitor insulator50/gate insulator28are not separately distinguishable inFIG.19, nor in subsequent corresponding odd-numbered figures, due to scale. Insulator material50/28may be silicon dioxide that is subjected to in situ steam generation immediately after its deposition for densification (e.g., at 650° C. to 1000° C., atmospheric or sub-atmospheric pressure, and in the presence of O2and H2). Material46/20has been deposited sufficient to fill the laterally-widened portions of openings33, but ideally not sufficient to fill the central portion of the narrower part of such openings.

Referring toFIGS.21and22, material46/20has been etched as shown to form finished first capacitor electrode46and first source/drain region20(and corresponding annuli45and41, respectively). An example etching chemistry to conduct the example depicted selective etch for the stated materials is tetra-methylammonium hydroxide (TMAH).

Referring toFIGS.23and24, intrinsic or suitably-doped channel-material silicon24has been deposited and subsequently etched back as-shown to set the channel length (e.g., 200 Angstroms) and define channel annuli40. An example etching chemistry for the stated materials is TMAH.

Referring toFIGS.25and26, more silicon-oxide-insulator material49has been deposited effective to fill the depicted recesses/gaps that were formed by the etching of channel material24shown in inFIGS.23and24, followed by selective etch thereof (e.g., dilute HF) to remove such form the main portion of openings33.

Referring toFIGS.27and28, insulator material50/28has been etched, followed by etching of titanium nitride second capacitor electrode material48, to remove such from being within the main portion of openings33. Example etching chemistries include, respectively, dilute HF and a combination of hydrogen peroxide and sulfuric acid. Thereafter, example silicon nitride insulator material47has been suitably etched (e.g., using hot phosphoric acid) to remove the uppermost layer47and to laterally recess material47within memory cell tiers14as shown. Such also thereby exposes elevationally uppermost and elevationally lowermost surfaces of second capacitor electrode material48where silicon nitride insulator material47has been removed in memory cell tiers14.

Referring toFIG.29, example titanium nitride material48has been subjected to selective etching (e.g., using sulfuric acid and hydrogen peroxide) sufficient to recess it laterally/radially as shown and to form elevational gaps/recesses between insulator material50/28and example silicon nitride47at radially inner ends (relative to openings33) of silicon nitride47.

Referring toFIG.30, insulator material49has been formed within the elevational gaps/recesses that were formed by the etching shown inFIG.29. An example technique for producing theFIG.30construction is a conformal deposition of example silicon-dioxide-insulator material49, followed by etch back (e.g., using dilute HF) to remove such except where received in the depicted gaps/recesses.

Referring toFIGS.31and32, more example n+ conductively-doped polysilicon gate material26,27has been deposited to fill the remaining gaps/recesses shown inFIG.30, followed by selective etching of material26,27(e.g., using TMAH) to laterally recess it as shown.

Referring toFIGS.33and34, example silicon-nitride-insulator material47has been deposited to fill the gaps that were formed by the etching shown inFIGS.31and32, followed by selective etch thereof (e.g., using hot phosphoric acid) to remove such from being within the main portion of openings33.

Referring toFIGS.35and36, example silicon-dioxide-insulator material49that was formed as described above with respect toFIGS.25and26(not shown inFIGS.35and36) has been removed by selective etching (e.g., HF). Suring such etching, some silicon-dioxide-insulator material49in staircase region15may also be etched (not shown). Alternately, uppermost silicon-nitride insulator material47(not shown) shown inFIG.14may initially be sufficiently thick such that all of it is not removed in the processing shown byFIGS.27and28such that some of it remains (not shown) and protects staircase-region-silicon-oxide material49during removal of material49that was formed as shown inFIGS.25and26.

Referring toFIGS.37and38, second source/drain region material22/material58has been deposited as shown sufficient to fill the gaps formed by removing material49as shown inFIGS.35and36. Subsequently, metal material60has been deposited and planarized and/or etched back as-shown to form sense-line structures56. Uppermost portions of materials58and60have been removed as shown and openings formed thereby have been plugged with insulator material49.

Referring toFIGS.39and40, a trench89has been formed (e.g., using lithography and subtractive etch with or without pitch multiplication) as shown. Such effectively enables longitudinal outlines of access lines90x and90y (not shown yet) to be formed, as well as formation of capacitor-electrode structures52(not shown yet) as will be apparent from the continuing discussion.

Referring toFIGS.41and42, example polysilicon material26,27has been selectively etched as-shown (e.g., using TMAH), thereby forming the longitudinal outlines of access lines90x and90y.

Referring toFIGS.43and44, example silicon-nitride-insulator material47has been used to plug the gaps/recesses formed by the etching shown inFIGS.41and42, and then such material47has been removed from the main portion of trenches89.

Referring toFIGS.45and46, example silicon-dioxide-insulator material49has been etched selectively (e.g., using HF) laterally sufficient to expose ends of second capacitor electrode material48as shown.

Referring toFIGS.47and48, additional second capacitor electrode material48has been deposited to fill trenches89and the gaps/recesses formed by the etching shown inFIGS.45and46, thus completing formation of capacitor-electrode structures52. Horizontally-elongated capacitor-electrode construction29may fabricated at this time (e.g., by subtractive patterning of material48of capacitor-electrode structures52).

Referring toFIGS.49and50, contact openings96have been formed in staircase region15to upwardly expose and overlap with conductive gate material26and27within individual memory cell tiers14.

Referring toFIGS.51and52, contact openings96have been filled with conductive material which has then been planarized back to form conductive vias97.

CONCLUSION

In some embodiments, a memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually include a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. At least a portion of the channel region is horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions. The memory cells individually include a capacitor comprising first and second electrodes having a capacitor insulator there-between. The first electrode is electrically coupled to the first source/drain region. The second capacitor electrodes of multiple of the capacitors in the array are electrically coupled with one another. A sense-line structure extends elevationally through the vertically-alternating tiers. Individual of the second source/drain regions of individual of the transistors that are in different memory cell tiers are electrically coupled to the elevationally-extending sense-line structure.

In some embodiments, a memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually include a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. At least a portion of the channel region is horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions. The memory cells individually include a capacitor comprising first and second electrodes having a capacitor insulator there-between. The first electrode is electrically coupled to the first source/drain region. A capacitor-electrode structure extends elevationally through the vertically-alternating tiers. Individual of the second electrodes of individual of the capacitors that are in different memory cell tiers are electrically coupled to the elevationally-extending capacitor-electrode structure. A sense line is electrically coupled to multiple of the second source/drain regions of individual of the transistors.

In some embodiments, a memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually include a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. At least a portion of the channel region is horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions. The memory cells individually include a capacitor comprising first and second electrodes having a capacitor insulator there-between. The first electrode is electrically coupled to the first source/drain region. A sense-line structure extends elevationally through the vertically-alternating tiers. Individual of the second source/drain regions of individual of the transistors that are in different memory cell tiers are electrically coupled to the elevationally-extending sense-line structure. A capacitor-electrode structure extends elevationally through the vertically-alternating tiers. Individual of the second electrodes of individual of the capacitors that are in different memory cell tiers are electrically coupled to the elevationally-extending capacitor-electrode structure.

In some embodiments, a memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually include a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. At least a portion of the channel region is horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions. The memory cells individually include a capacitor comprising first and second electrodes having a capacitor insulator there-between. The first electrode is electrically coupled to the first source/drain region. The second capacitor electrodes of multiple of the capacitors in the array are electrically coupled with one another. A sense line is electrically coupled to multiple of the second source/drain regions of individual of the transistors that are in different memory cell tiers. Individual of the tiers of memory cells comprise two of the memory cells one of which is directly above the other in that individual tier of memory cells.

In some embodiments, a memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually include a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. At least a portion of the channel region is horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions. The memory cells individually include a capacitor comprising first and second electrodes having a capacitor insulator there-between. The first electrode is electrically coupled to the first source/drain region. The second capacitor electrodes of multiple of the capacitors in the array are electrically coupled with one another. A sense line is electrically coupled to multiple of the second source/drain regions of individual of the transistors that are in different memory cell tiers. Individual of the tiers of memory cells comprise the gate and another gate. One of the gate and the another gate is directly above the other in that individual tier of memory cells.