Method and apparatus for synchronous communication of frames of digital information

A method and apparatus for synchronous communication of frames of serial data is provided. A framing pattern and data payloads are communicated over a first communication path. A clock signal is communicated over a second communication path. The clock signal is synchronous to the data to allow easy data recovery at the receiver. The framing pattern is communicated between each data payload. The framing pattern has a length greater than the length of each data payload. The framing pattern includes one or more bits of a first logic level followed contiguously by one or more bits of a second logic level. Since the framing pattern is longer than each data payload, a data payload can never contain sufficient information to mimic a framing pattern. A transmitter and a receiver are provided that avoid the need for complex circuitry while readily identifying any communication path failures so as to prevent propagation of erroneous data.

FIELD OF THE DISCLOSURE

The present invention relates generally to communication of digital information, and more particularly to a method and apparatus for synchronous communication of frames of digital information.

BACKGROUND

It is often desirable to communicate digital information in frames of fixed length. To avoid the need for large numbers of parallel communication paths, information is often transmitted in a serial form, with the several bits of data of a frame communicated in a temporally sequential manner.

It is possible to communicate frames of data over a single communication path, such as a single wire, optical path, or other medium. However, such a one-wire solution requires a complex analog clock recovery circuit. Also, large, complicated state machines are required for framing pattern detection. Additionally, complicated state machines are required to reduce the possibility of false “frame lock” due to a data frame that happens to mimic a framing pattern. Consequently, the complexity and associated expense of a one-wire technique makes it a less than ideal solution.

Another approach involves three parallel communication paths, which one path dedicated to communicating the data, a second path dedicated to communicating a frame pulse, and a third path dedicated to communicating a clock signal. While the separation of the data, frame pulse, and clock signal avoid the need for complex circuits required for the one-wire technique, this separation results in three times as many communication paths needed to communicate the information. Thus, for any given likelihood that a communication path will fail, a three-wire solution has a much greater likelihood of system failure. Proper handling of a communication path failure is also much more complex. For example, if only one or two of the three communication paths were to fail, it could be difficult to detect the exact nature of the communication path failure, and erroneous data may be propagated at the receiver output. Thus, the design of the receiver necessarily becomes complicated if the receiver is required to handle three possible failure modes in a manner such that erroneous data is not propagated. Therefore, a three-wire technique can result in reduced reliability, availability, and serviceability, where availability is defined as the ability to detect a failure quickly and serviceability is defined as the ability to detect which communication path has failed. Consequently, the three-wire technique provides a less than ideal solution.

Thus, a solution is needed that avoids the complex circuitry of the one-wire technique and the reduced reliability, availability, and serviceability of the three-wire technique.

DETAILED DESCRIPTION OF THE FIGURES

A method and apparatus for synchronous communication of frames of serial data is described. A framing pattern and data payloads are communicated over a first communication path. A clock signal is communicated over a second communication path. The clock signal is synchronous to the data to allow easy data recovery at the receiver. The framing pattern is communicated between each data payload. The framing pattern has a length greater than the length of each data payload. The framing pattern includes one or more bits of a first logic level followed contiguously by one or more bits of a second logic level. Since the framing pattern is longer than each data payload, a data payload can never contain sufficient information to mimic a framing pattern. A transmitter and a receiver are provided that avoid the need for complex circuitry while readily identifying any communication path failures so as to prevent propagation of erroneous data. An embodiment of the invention allows communication of frames of time division multiplexed (TDM) data, wherein several frames of data that may belong to several independent data flows may be communicated over a common channel by sequencing the several frames of data in time. In accordance with an embodiment of the invention, demarcation between these several frames of data is efficiently provided.

FIG. 1is a timing diagram illustrating two embodiments of a data stream in accordance with the present invention. The data stream includes frames of information. Each frame includes a framing pattern and a data payload. In the first embodiment, the framing pattern includes bits101through105. In this example, bit101represents a logical zero, while bits102through105represent logical 1's. The data payload includes bits106through109. Bits106through109consist of n bits, and bits102through105of the framing pattern comprise n bits. Since the framing pattern includes bit101in addition to bits102through105, the framing pattern will always be longer than the data payload. Bits101through105of the framing pattern are contiguously sequential. Bits106through109of the data payload are contiguously sequential. The framing pattern is contiguously sequential with the data payload. Bit111represents a bit of a framing pattern of an adjacent frame. Thus, it can be seen that the data payload is contiguously sequential with a framing pattern of an adjacent frame. Bit110represents a bit of a data payload of an adjacent frame. Thus, it can be seen that the framing pattern is contiguously sequential with a data payload of an adjacent frame. Synchronous clock signal112is illustrated in its temporal relationship with the data stream of the first embodiment. As can be seen, if the data stream is sampled on the rising edge of synchronous clock112, the data of the data stream may be synchronously recovered at the receiver.

A second embodiment of a data stream is also illustrated inFIG. 1. In this embodiment, the framing pattern includes bits121through125, and the data payload includes bits126through129. In this example, bit121is of a logic level similar to that of bits102-105in the above example, and bits122through125are of a logic level similar to that of bit101in the above example. Bit130represents a bit of a data payload of an adjacent frame, and bit131represents a bit of a framing pattern of an adjacent frame. As illustrated, bits121through131are contiguously sequential. Thus, it can be seen that the invention is not limited to the use of specific logic levels for bit101and bits102-105or for bit121and bits122-125. Rather, any distinguishable logic levels may be used. Consequently, use of the terms “first logic level” or “first polarity” and “second logic level” or “second polarity” herein should be understood to represent logic levels that may be distinguished from one another, without placing further constraints on either logic level.

The broken lines between bits103and104, between bits107and108, between bits123and124, and between bits127and128illustrated that the framing pattern length and the data payload length may be varied while maintaining the relationship between the framing pattern and the data payload that allows them to be distinguished from one another. Thus, the examples illustrated inFIG. 1are not intended to imply a specific length (or a minimum or maximum length) for the framing pattern or a data payload.

Other variants of a data stream in accordance with an embodiment of the invention include those in which the bits of the framing pattern are temporally reversed with respect to the examples illustrated inFIG. 1. As one example, bits temporally corresponding to bits101-104are of a logic level similar to that of bit101in the above example ofFIG. 1, and a bit temporally corresponding to bit105is of logic level similar to that of bits102-105in the above example ofFIG. 1. In another example, bits temporally corresponding to bits101-104are of a logic level similar to that of bits102-105in the above example ofFIG. 1, and a bit temporally corresponding to bit105is of a logic level similar to that of bit101in the above example ofFIG. 1. Thus, the framing pattern may comprise any of a variety of patterns that allow the framing pattern to be readily distinguished from a data payload.

As another, more general, example, any framing pattern exhibiting only one transition from a given logic level to a different logic level may be used. Such a framing pattern may include a contiguous first number of bits of the given logic level followed by a contiguous second number of bits of the different logic level, wherein the sum of the first number of bits and the second number of bits is greater than the number of bits in the data payload that is transmitted between two instances of the framing pattern. While the framing pattern may remain the same from one instance to the next, by configuring a transmitter to produce framing patterns exhibiting only one transition and configuring a receiver to detect framing patterns based on their single transition, the present invention may be practiced with framing patterns wherein the actual sequence of bits that constitute an instance of the framing pattern may vary from instance to instance.

If the framing pattern is longer than any data payload, no data payload can mimic the framing pattern, and misidentification of bits of the framing pattern and bits of a data payload can be avoided. By using a framing pattern having a contiguously sequential plurality of bits of a similar logic level, with that plurality of bits contiguously sequential with a bit of a different logic level, not only can the framing pattern, as a whole, be distinguished from any data payload, but alignment of the bits of the framing pattern and bits of a data payload can be identified without ambiguity. Therefore, even if, for example, bit106were of a similar logic level to bit105, the demarcation of the framing pattern and the data payload between bit105and bit106can be unambiguously identified.

FIG. 2is a logic diagram illustrating a transmitter in accordance with an embodiment of the present invention. The transmitter includes a payload transmission circuit for accepting a payload of data to be transmitted. The payload includes a plurality of payload bits. The payload transmission circuit causes the payload bits to be transmitted during payload time slots. The transmitter also includes a framing pattern transmission circuit coupled to the payload transmission circuit. The framing pattern transmission circuit causes a framing pattern to be transmitted during framing pattern time slots. The framing pattern has a framing pattern length greater than a payload length of the payload. The transmitter also includes a merging circuit. The merging circuit couples the payload transmission circuit and the framing pattern transmission circuit. The merging circuit merges the payload and the framing pattern to provide a data signal.

The payload transmission circuit includes combinational logic devices, for example, AND gates208-210. The framing pattern transmission circuit includes sequential logic devices, for example, D flip flops204-207. The payload transmission circuit further includes sequential logic devices, for example, D flip flops201-203. The merging circuit includes a combinational logic device, for example, OR gate211.

A shift register comprising D flip flops201through207is provided. The output of D flip flop202is coupled via coupling216to the input of D flip flop201. The output of D flip flop203is coupled via coupling217to the input of D flip flop202. The output of D flip flop204is coupled via coupling218to the input of D flip flop203. The output of D flip flop205is coupled via coupling219to the input of D flip flop204. The output of D flip flop206is coupled via coupling220to the input of D flip flop205. The output of D flip flop207is coupled via coupling221to the input of D flip flop206. The output of D flip flop201is coupled via coupling222to the input of D flip flop207. Thus, the shift register output is coupled to the shift register input, forming a feedback loop around the shift register. Coupling216is also coupled to an input of AND gate210. Coupling217is also coupled to an input of AND gate209. Coupling218is also coupled to an input of AND gate208. Coupling222is also coupled to an input of OR gate211. An input213carrying a first bit of a data payload is coupled to an input of AND gate208. An input214carrying a second bit of a data payload is coupled to an input of AND gate209. An input215carrying an nth bit of a data payload is coupled to an input of AND gate210.

An output223of AND gate208is coupled to an input of OR gate211. An output224of AND gate209is coupled to an input of OR gate211. An output225of AND gate210is coupled to an input of OR gate211. An output226of OR gate211is coupled to an input of D flip flop212. Output227of D flip flop212provides a data stream, for example a data stream such as those illustrated inFIG. 1. WhileFIG. 2illustrates an example for a three-bit data payload, any length of data payload may be accommodated by changing the number of D flip flops in the shift register and the number of AND gates to which they are coupled, as well as the corresponding inputs for the AND gates, as illustrated by ellipses inFIG. 2. The shift register ofFIG. 2is provided with a preload capability allowing specific values to be preloaded into each of the D flip flops201through207. As one example, D flip flops201through206are illustrated as being preloaded with zeros, and D flip flop207is illustrated as being preloaded with a one. D flip flop212is optional and, while preferred, may be omitted.

A common clock signal is preferably used to clock D flip flops201-207and212. This common clock signal is preferably communicated over a clock conductor of a bus between the transmitter and a receiver, while the data stream from the transmitter is communicated over a data conductor of the bus. Thus, communication between the transmitter and a receiver may be provided using only two conductors, for example, two wires.

FIG. 3is a logic diagram illustrating a receiver in accordance with an embodiment of the present invention. The receiver includes a payload reception circuit for receiving a payload of data from a data signal. The payload includes a plurality of payload bits communicated during payload time slots. The receiver also includes a framing pattern reception circuit coupled to the payload reception circuit. The framing pattern reception circuit receives a framing pattern from the data signal during framing pattern time slots. The framing pattern has a framing pattern length greater than a payload length of the payload. The receiver also includes a payload output circuit coupled to the payload reception circuit and to the framing pattern reception circuit. The payload output circuit outputs the payload upon reception of the framing pattern and the payload. The receiver also includes an error detection circuit comprising a too many l's error detector and a too many0's error detector coupled to the payload reception circuit and to the framing pattern reception circuit. The error detection circuit provides the ability to detect error conditions. For example, the error detection circuit can provide a too many ones error indication upon detection of too many logical ones. As another example, the error detection circuit can provide a too many zeros error indication upon detection of too many logical zeros. Of course, these indications can be combined with an OR logic gate to provide a bad frame indication if a simple indication of a faulty frame is desired. The receiver also includes a good frame detector for detecting valid framing of payloads.

The payload reception circuit includes sequential logic devices, for example, D flip flops301-303. The framing pattern reception circuit includes sequential logic devices, for example, D flip flops304-307. The framing pattern reception circuit further includes a combinational logic device, for example, AND gate310. The payload output circuit further includes sequential logic devices, for example, D flip flops311-316.

A data stream is received at input317. Input317is coupled to D flip flop301. D flip flops301through307serve as a shift register. The output of D flip flop301is coupled via coupling318to an input of D flip flop302. The output of D flip flop302is coupled via coupling319to an input of D flip flop303. The output of D flip flop303is coupled via coupling320to an input of D flip flop304. The output of D flip flop304is coupled via coupling321to an input of D flip flop305. The output of D flip flop305is coupled via coupling322to an input of D flip flop306. The output of D flip flop306is coupled via10coupling323to an input of D flip flop307. The output of D flip flop307is coupled via coupling324.

Coupling318is also coupled to an inverting input of AND gate309and to an input of D flip flop311. Coupling319is also coupled to an inverting input of AND gate309and to an input of D flip Flop313. Coupling320is also coupled to an inverting input of AND gate309and to an input of D flip flop315. Coupling321is also coupled to an input of AND gate308, to an inverting input of AND gate309, and to an inverting input of AND gate310. Coupling322is also coupled to an input of AND gate308, to an inverting input of AND gate309, and to an inverting input of AND gate310. Coupling323is also coupled to an input of AND gate308, and inverting input of AND gate309, and an inverting input of AND gate310. Coupling324is coupled to an input of AND gate308, to an inverting input of AND gate309, and to an input of AND gate310.

The too many 1's error detector comprises AND gate308, which provides output325to indicate a too many 1's error. The too many 0's error detector comprises AND gate309, which provides an output326to indicate a too many 0's error. The good frame detector comprises AND gate310, which provides an output327to indicate a good frame. Output327is coupled to a clock enable input of each of D flip flops311through316. The output of D flip flop311is coupled to an input of D flip flop312. The output of D flip flop312is provided at output331, representing the nth bit of the data payload. The output of D flip flop313is coupled via coupling329to an input of D flip flop314. The output of D flip Flop314is provided at output332, representing the second bit of the data payload. The output of D flip flop315is coupled via coupling330to the input of D flip flop316. The output of D flip flop316is provided at output333, representing the first bit of the data payload.

The receiver is preferably coupled to a transmitter by a bus comprising two conductors, for example, two wires. While one conductor is used to communicate a data signal including the framing pattern and the payload, another conductor is used to communicate a clock signal. This clock signal is preferably used to clock D flip flops301-307and311-316. Thus, the transmitter and receiver can operate synchronously using the same clock signal.

WhileFIG. 3illustrates an example for a three-bit data payload, any length of data payload may be accommodated by changing the number of D flip flops in the shift register and the number of D flip flops and AND gate inputs to which they are coupled, as illustrated by ellipses inFIG. 3. Other techniques for identifying too many 1's errors or too many 0's errors may be used. For example, to identify too many 1's errors, an AND gate having more inputs may be used and/or AND gate inputs may be coupled to outputs of different D flip-flops in the shift register.

In the example ofFIG. 3, the too many 1's error detector identifies too many 1's errors that occur when (n+1) or more consecutive 1's are received, a too many 0's error detector identifies too many 0's errors that occur when (2n+1) or more consecutive 0's are received, and the good frame detector identifies when a good frame is received by detecting a consecutive pattern of a 1 followed by n 0's. While, in that example, the too many 1's error detector, the too many 0's error detector, and the good frame detector are described in a manner compatible with a framing pattern having a 1 followed by n 0's, the specific logic circuits used to implement the too many 1's error detector, the too many 0's error detector, and the good frame detector may be configured to accommodate any framing patterns with which the invention may be practiced. As one example, the receiver can accommodate a framing pattern of opposite logic levels if the inputs of AND gates308-310are inverted from the configuration in which they are illustrated inFIG. 3. The receiver can accommodate a framing pattern temporally reversed from that for which the example inFIG. 3is designed simply by inverting the inputs of AND gate310coupled to couplings321and324from the sense in which they are illustrated inFIG. 3. Thus, corresponding to the example illustrated inFIG. 3, the input of AND gate310coupled to coupling321would be changed to a non-inverting input, and the input of AND gate310coupled to coupling324would be changed to an inverting input.

In the example illustrated inFIG. 3, it should be understood that D flip flops312,314, and316maybe considered to be optional. D flip flops312,314, and316ensure that a payload is propagated to their outputs331,332, and333, respectively, only if the framing pattern received following the payload is determined to be valid. D flip flops311,313, and315ensure that the payload is propagated to their outputs328,329, and330, respectively, only if the framing pattern preceding the payload is determined to be valid. By implementing all of D flip-flops311-316, assurance is provided that the payload is only propagated to outputs331,332, and333when the framing patterns surrounding (i.e., before and after) the payload are valid. If D flip flops312,314, and316were omitted, only the framing pattern preceding the payload would be checked for validity before the payload were propagated.

WhileFIGS. 2 and 3provide simple examples of a transmitter and receiver in accordance with an embodiment of the invention, it should be understood that transmitters and receivers in accordance with embodiments of the invention may be implemented in many other ways. In another example, D flip flops201-203are transposed with D flip-flops204-207, and D flip flops301-303are transposed with D flip flops304-307. As noted above, the transmitter and receiver may be readily scaled to accommodate any number of bits in a data payload. While transmitters and receivers in accordance with an embodiment of the invention may be implemented with few logic devices, as illustrated inFIGS. 2 and 3, it should be understood that transmitters and receivers of other levels of complexity, for example, those having more logic devices or other components, may be implemented.

FIG. 4is a flow diagram illustrating a method for transmitting a data signal and a clock signal in accordance with an embodiment of the invention. In step401, a data signal is transmitted. The data signal includes frames. Each frame includes one of a plurality of payloads of data and a framing pattern. The framing pattern has a framing pattern length that is greater than a payload length of each of the plurality of the payloads of the data. In step402, a clock signal is transmitted. The clock signal allows synchronous sampling of the data signal. Since the data signal is synchronous with the clock signal, both steps401and402preferably occur at the same time.

FIG. 5is a flow diagram illustrating a method for transmitting data in accordance with an embodiment of the invention. In step501, a first payload of data having a payload length is transmitted. In step502, a first instance of a framing pattern having a framing pattern length is transmitted. The framing pattern length is greater than the payload length. In step503, a second payload of data having the payload length is transmitted. In step504, a second instance of the framing pattern having the framing pattern length is transmitted.

FIG. 6is a flow diagram illustrating additional steps that may be implemented in the method for transmitting data illustrated inFIG. 5in accordance with an embodiment of the invention. In step601, the first instance of the framing pattern is detected. In step602, the first payload is received upon detecting of the first instance of the framing pattern. In step603, the second instance of the framing pattern is detected. In step604, the second payload is received upon detecting of the second instance of the framing pattern. As an example of a temporal relationship between the steps ofFIGS. 5 and 6, step601may follow step502, step602may follow step501, step603may follow step504, and step604may follow step503.

Accordingly, a method and apparatus for synchronous communication of frames of digital information has been described. It should be understood that the implementation of other variations and modifications of the invention in its various aspects will be apparent to those of ordinary skill in the art, and that the invention is not limited by the specific embodiments described. It is therefore contemplated to cover by the present invention, any and all modifications, variations, or equivalents that fall within the spirit and scope of the basic underlying principles disclosed and claimed herein.