A power-control device for generating and controlling a supply voltage is provided. The power-control device includes a variant delay chain with a delay length, a sampling circuit, a comparison circuit, and a power manager. The variant delay chain receives an initial signal and performs a delay operation on the initial signal according to the delay length to generate a delay signal. The sampling circuit receives the delay signal and performs a sampling operation on the delay signal to generate a sampled signal. The comparison circuit receives the sampled signal and compares the sampled signal with a reference signal to generate a comparison result signal. The power manager receives the comparison result signal and adjusts the supply voltage according to the comparison result signal.

CROSS REFERENCE TO RELATED APPLICATIONS

This Application claims priority of China Patent Application No. 201510557148.X, filed on Sep. 2, 2015, the entirety of which is incorporated by reference herein.

BACKGROUND OF THE INVENTION

Field of the Invention

The invention relates to a power-control device, and more particularly to a power-control device with a performance monitor circuit which is capable of generating a supply voltage to a target processing module to serve as its operation voltage by monitoring the operation state of the target processing module.

Description of the Related Art

Electronic devices consume power when processors perform operations, and so power control is important, especially in mobile devices. When a processor in performs a specific operation, a lower supply voltage is expected, for reducing power consumption. Generally, one dynamic voltage-frequency scaling (DVFS) table consists of a plurality of operation frequencies and a plurality of corresponding operation voltages. For a batch of chips, an operation voltage applied to the batch of chips can be found in one DVFS table on a specific operation frequency. However, among one batch of chips, the chips may have different frequency-voltage characteristics, and even the frequency-voltage characteristic of one chip can vary between different operation states. Thus, when a fixed DVFS table is applied for all of the chips in the same batch, power consumption may not be reduced for the chips that can achieve the same expected operation frequency on lower voltages.

BRIEF SUMMARY OF THE INVENTION

An exemplary embodiment is provided of a power-control device for generating and controlling a supply voltage. The power-control device comprises a variant delay chain with a delay length, a sampling circuit, a comparison circuit, and a power manager. The variant delay chain receives an initial signal and performs a delay operation on the initial signal according to the delay length to generate a delay signal. The sampling circuit receives the delay signal and performs a sampling operation on the delay signal to generate a sampled signal. The comparison circuit receives the sampled signal and compares the sampled signal with a reference signal to generate a comparison result signal. The power manager receives the comparison result signal and adjusts the supply voltage according to the comparison result signal.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1shows an exemplary embodiment of an electronic system. An electronic system1shown inFIG. 1can be a mobile device, such as a smartphone, a tablet PC, or a digital camera. Referring toFIG. 1, the electronic system1comprises a power-control device10, a processing module11, a clock generator12, and a central processing unit (CPU)13. The power-control device10comprises a performance monitor100and a power manager101. The performance monitor100comprises a variant delay chain1000, a sampling circuit1001, a comparison circuit1002, an initial signal generation circuit1003, a reference signal generation circuit1004, and a temperature sensor1005. The power manager101comprises a power management unit (PMU)1010and a power management integrated circuit (PMIC)1011. In the embodiment ofFIG. 1, the power management integrated circuit1011and the power management unit1010are two separate components or devices, and the power management integrated circuit1011is controlled by the power management unit1010. In other embodiments, the power management integrated circuit1011is embodied in the power management unit1010. That is, the power management integrated circuit1011is one portion of the power management unit1010. In these embodiments, the power management unit1010serves as the power manager101.

The power management unit1010comprises a storage unit1012which stores a dynamic voltage-frequency scaling (DVFS) table. The DVFS consists of a plurality of operation frequencies and a plurality of corresponding operation voltages. While the electronic system1operates initially, the central processing unit13controls the power management unit1010to initially select an expected operation frequency and the corresponding operation voltage from the DVFS table according to the expected performance of the processing module11. The power management unit1010generates control signals S101A and S101B to the power management integrated circuit1011and the clock generator12according to the selected operation frequency and the selected operation voltage, respectively. The power management integrated circuit1011initially generates a supply voltage Vsupply with a predetermined level (the predetermined level corresponds to the operation voltage selected by the power management unit1010) according to the control signal S101A. The clock generator12generates a clock signal CLK according to the control signal S101B. In the embodiment, the clock generator12is implemented by a phase-locked loop structure.

The processing module11receives the supply voltage Vsupply to serve as its operation voltage and further receives the clock signal CLK to serve as a clock base of operations. The performance monitor100receives the supply voltage Vsupply to serve as its operation voltage and further receives the clock signal CLK. In other words, the processing module11and the performance monitor100share the supply voltage Vsupply and the clock signal CLK. The performance monitor100operates to monitor the operation performance of the processing module11, and the monitoring result is applied to control the power manager101to adjust or not adjust the supply voltage Vsupply. In the following description, the monitoring operation of the performance monitor100will be illustrated. In the performance monitor100, the initial signal generation circuit1003receives the clock signal CLK and generates an initial signal S1003according to the clock signal CLK. The variant delay chain1000receives the initial signal S1003and performs a delay operation on the initial signal S1003by using the current delay length to generate a delay signal S1000. In the embodiment, the variant delay chain1000is used to imitate a critical path of the processing module11, and the delay length of the variant delay chain1000corresponds to the timing of the critical path. Accordingly, the performance monitor1000can determine the critical path of the processing module11and the timing of the critical path through the variant delay chain1000. In the embodiment, the variant delay chain1000just delays the timing of the initial signal S1003to generate the delay signal S1000, and, however, the variant delay chain1000does not invert the initial signal S1003for output. That is, the level variation of the delay signal S1000is the same as that of the initial signal S1003. The sampling circuit1001receives the delay signal S1000and performs a sampling operation on the delay signal S1000to generate a sampled signal S1001. The reference signal generation circuit1004also receives the initial signal S1003and performs a sampling operation on the initial signal S1003according to the clock signal CLK to generate a reference signal S1004.

The comparison circuit1002receives the sampled signal S1001output from the sampling circuit1001and the reference signal S1004output from the reference signal generation circuit1004. The comparison circuit1002compares the sampled signal S1001and the reference signal S1004and generates a comparison result signal S1002according to the comparison result. The comparison result signal S1002is transmitted to the power management unit1010. In cases where the comparison circuit1002determines that the sampled signal S1001is the same as the reference signal S1004through the comparison operation, the variant delay chain1000operates normally. Since the variant delay chain1000imitates the critical path of the processing module11, in cases where the comparison circuit1002determines that the sampled signal S1001is the same as the reference signal S1004through the comparison operation, the processing module11can operate normally on the current operation voltage (that is, the current supply voltage Vsupply). In such cases, according to the comparison result signal S1002, the power management unit1010determines that the currently generated supply voltage Vsupply is sufficient for the processing module11to operate normally. Thus, the power management unit1010controls the power management integrated circuit1011to lower the supply voltage Vsupply (that is, to lower the voltage level). On the other hand, in cases where the comparison circuit1002determines that the sampled signal S1001is different from the reference signal S1004through the comparison operation, the variant delay chain1000does not operate normally, and the processing module11cannot operate normally on the current operation voltage (that is, the current supply voltage Vsupply). In such cases, according to the comparison result signal S1002, the power management unit1010determines that the currently generated supply voltage Vsupply is not sufficient for the processing module11to operate normally. Thus, the power management unit1010controls the power management integrated circuit1011not to adjust the supply voltage Vsupply (that is, not to adjust the voltage level), so as not to lower the level of the supply voltage Vsupply. In other words, when the power management unit1010determines that continuously lowering the supply voltage Vsupply is not adequate for the processing module11to operate normally, the supply voltage is maintained at the current level or pulled slightly high.

According to the description above, after the power manager101initially generates the supply voltage Vsupply with the initial level based on the DVFS table, the power-control device10imitates the critical path of the processing module11through the variant delay chain1000in the performance monitor100, thereby monitoring the operation performance when the processing module11is operating on the current operation voltage and dynamically adjusting the supply voltage Vsupply in response to the monitoring result. When the performance monitor100determines that the processing module11can operate normally on the current operation voltage, the power manager101lowers the supply voltage Vsupply provided to the processing module11, which can reduce the power consumption of the processing module11. Moreover, according to the embodiment, even if one DVFS table is applied for all of the chips in the same batch, each chip can operate on the operation voltage which better conforms to the frequency-voltage characteristic through the voltage adjustment of the power-control device10. Thus, better performance and low power consumption can be achieved.

FIG. 2shows an exemplary embodiment of the performance monitor100. Referring toFIG. 2, the initial signal generation circuit1003comprises an inverter20and a flip-flop21. An input terminal of the inverter20is coupled to an output terminal Q of the flip-flop21, and an output terminal thereof is coupled to an input terminal D of the flip-flop21. The flip-flop21generates the initial signal S1003at the output terminal Q. The variant delay chain1000receives the initial signal S1003and generates the delay signals S1000. The sampling circuit1001comprises flip-flops22and23. An input terminal D of the flip-flop22receives the delay signal S1000. An input terminal D of the flip-flop23is coupled to an output terminal Q of the flip-flop22. The sampling circuit1001performs the sampling operation on the delay signal S1000through the operations of the flip-flops22and23to generate the sampled signal S1001at an output terminal Q of the flip-flop23. The reference signal generation circuit1004comprises flip-flops24and25. An input terminal D of the flip-flop24receives the initial signal S1003. An input terminal D of the flip-flop25is coupled to an output terminal Q of the flip-flop24. The reference signal generation circuit1004performs the sampling operation on the initial signal S1003through the operations of the flip-flops24and25to generate the reference signal S1004at an output terminal Q of the flip-flop24. The comparison circuit1002comprises an XOR gate26. Two input terminals of the XOR gate26receive the sampled signal S1001and the reference signal S1004respectively. When the sampled signal S1001is the same as the reference signal S1004, the XOR gate26generates the comparison result signal S1002with a low level. At this time, the power management unit1010controls the power management integrated circuit1011to lower the supply voltage Vsupply according to the comparison result signal with the low level. When the sampled signal S1001is different from the reference signal S1004, the XOR gate26generates the comparison result signal S1002with a high level. At this time, the power management unit1010controls the power management integrated circuit1011not to adjust the supply voltage Vsupply according to the comparison result signal with the high level, so as not to lower the level of the supply voltage Vsupply.

FIG. 3shows an exemplary embodiment of the variant delay chain1000. As shown inFIG. 3, the variant delay chain1000comprises a plurality of multiplexers30-0˜30-N coupled in series. Except the multiplexer30-0, one terminal (0) of each one among the multiplexers30-1˜30-N is coupled to the output of the previous multiplexer, and the other input terminal thereof (1) receives the initial signal S1003. The two input terminals of the multiplexer30-0both receive the initial signal S1003. The output terminal of the multiplexer30-N generates the delay signal S1000. In the embodiment, the delay length of the variant delay chain1000is adjustable. Referring toFIGS. 1 and 3, the variant delay chain1000is controlled by the power management unit1010. The power management unit1010generates a plurality of selection signals SEL-1˜SEL-N to the variant delay chain1000to control the multiplexers30-0˜30-N, respectively. The power management unit1010adjusts or changes the delay length of the variant delay chain1000through the selection signal SEL-0˜SEL-N.

In the embodiments inFIGS. 2 and 3, the structures of the variant delay chain1000, the sampling circuit1001, the comparison circuit1002, the initial signal generation circuit1003, and the reference signal generation circuit1004are used as an example. In practice, the above circuits may have different structures according to the system requirements and specifications.

Referring toFIG. 1, in an embodiment, the delay length of the variant delay chain1000can be adjusted or changed according to the ambient temperature of the power-control device10(that is, the ambient temperature of the processing module11). In the following paragraphs, the operation of adjusting the delay length of the variant delay chain1000according to the ambient temperature will be described by referring toFIGS. 1 and 4. The temperature sensor1005of the performance monitor100senses the ambient temperature of the temperature sensor1005to generate a temperature signal S1005(step S40). The temperature sensor1005generates the temperature signal S1005according to the sensed ambient temperature and provides the temperature signal S1005to the power management unit1010. The power management unit1010determines the ambient temperature according to the temperature signal S1005(step S41). The power management unit1010determines whether the sensed ambient temperature reaches an upper threshold (step S42). When the power management unit1010determines that the sensed ambient temperature reaches the upper threshold, the power management unit1010issues an interrupt signal to the central processing unit13. At this time, the central processing unit13transmits an instruction signal to the power management unit1010in response to the interrupt signal, so that the power management unit1010controls the power management integrated circuit1011to lower the supply voltage Vsupply (step S43), thereby preventing the chip of the processing module11from being damaged. In another embodiment of step S43, when the power management unit1010determines that the sensed ambient temperature reaches the upper threshold, the power management unit1010directly controls the power management integrated circuit1011to lower the supply voltage Vsupply. In such cases, the power management unit1010does not issue an interrupt signal to the central processing unit13.

When the power management unit1010determines that the sensed ambient temperature has not reached the upper threshold yet, the power management unit1010issues an interrupt signal to the central processing unit13. At this time, the central processing unit13transmits an instruction signal to the power management unit1010according to the previous and current operation states of the processing module11, so that the power management unit1010can adjust the delay length of the variant delay chain1000if an adjustment of the delay length is required (step S44). According to the description above, the power management unit1010adjusts the delay length of the variant delay chain1000through the selection signals SEL-0˜SEL-N. In another embodiment of the step S44, when the power management unit1010determines that the sensed ambient temperature has not yet reached the upper threshold, the power management unit1010directly adjusts the delay length of the variant delay chain1000through the selection signals SEL-0˜SEL-N. In such cases, the power management unit1010does not issue an interrupt signal to the central processing unit13.

In the above embodiments, the processing module11monitored by the performance monitor100can be a graphics processing unit (GPU), a micro-controller, or a dedicated controller. In some embodiments, as shown inFIG. 5, the processing module50monitored by the performance monitor100can be a central processing unit. In embodiment ofFIG. 5, the central processing unit13may be excluded. In the steps S43and44of the embodiment ofFIG. 4, the power management unit1010issues an interrupt signal to the processing module50, and the processing module50transmits an instruction signal to the power management unit1010in response to the interrupt signal. That is, in the embodiment ofFIG. 5, the operations performed by the central processing unit13shown in the embodiment ofFIG. 1are performed by the processing module50.