Organic light-emitting diode array substrate and manufacturing method thereof

An organic light-emitting diode array substrate and manufacturing method thereof are provided. The manufacturing method includes forming a semiconductor layer, a gate insulating layer, a gate, and a first insulating layer on a substrate; forming a first metal pattern on the first insulating layer, and the first metal pattern connecting to the gate through the through hole; forming a second insulating layer covering the first metal pattern on the first insulating layer; and forming a second metal pattern on the second insulating layer so that the second metal pattern and the first metal pattern overlap each other to form a capacitor.

FIELD OF INVENTION

The present invention relates to a field of display, and more particularly, to an organic light-emitting diode array substrate and a manufacturing method.

BACKGROUND OF INVENTION

Because organic light-emitting diode (OLED) display panels have advantages of self-luminescence, simple structures, wide viewing angles, high color saturation, fast response times, lightness and thinness compared with liquid crystal display (LCD) panels, products with displays are beginning to adopt OLED panels, such as smart phones and wearable devices, etc. With increasing commercial applications of the OLED panels, people have more requirements for OLED performance, such as higher brightness, higher efficiency, lower power consumption, higher stability, and the like.

Based on the above requirements, it is particularly important to improve electrical performance of an OLED array layout. At present, a mainstream OLED array is a pixel circuit using seven thin film transistors and a capacitor (7T1C), as shown inFIG. 1, wherein a gate of a thin film transistor T1serves as a bottom electrode plate of a capacitor C1in the existing technology. The capacitor C1is required to have a greater capacitance value for better electrical performance. The capacitance value of the capacitor C1is proportional to a capacitor area and a dielectric constant, and inversely proportional to a distance between electrode plates. In existing technology, increasing the capacitance value is carried out by the following three approaches: increasing the capacitor area, increasing the dielectric constant, or reducing a distance between the electrode plates. Reducing the distance between the electrode plates leads to a decrease in the thickness of a dielectric layer, and increases a risk of breakdown. The dielectric constant relates to materials, so increasing the capacitor area is the most feasible approach.

However, a low-temperature polysilicon active layer and a gate area of the thin film transistor T1are limited by the demand for high pixel per inch (PPI). If the gate of the thin film transistor T1serves as the bottom electrode plate of the capacitor, the capacitor area is limited by the gate area. Therefore, it is necessary to develop a novel OLED array structure, which can meet a design of high pixel density and provide a larger capacitor area to satisfy more excellent storage capacities.

Therefore, it is necessary to provide an organic light-emitting diode array substrate and a manufacturing method thereof to solve the problems of the prior art.

SUMMARY OF INVENTION

In view of the shortcomings of the existing technology, the major object of the present invention is to provide an organic light-emitting diode array substrate and manufacturing method thereof, which can make the capacitor in the pixel circuit using 7T1C no longer limited by the gate area of the thin film transistor.

In order to achieve the above-mentioned object of the present invention, the technical solutions provided by the present invention are as follows:

The present invention provides a manufacturing method of an organic light-emitting diode array substrate, including steps of: sequentially forming a semiconductor layer, a gate insulating layer, a gate, and a first insulating layer on a substrate, wherein the semiconductor layer includes an active region, a source region, and a drain region; forming a through hole in the first insulating layer to partially expose the gate; forming a first metal pattern on the first insulating layer corresponding to a position of the gate, wherein the first metal pattern is connected to the gate through the through hole; forming a second insulating layer on the first insulating layer to cover the first metal pattern; forming a second metal pattern on the second insulating layer corresponding to a position of the first metal pattern, wherein the second metal pattern and the first metal pattern overlap each other to form a capacitor; forming an interlayer dielectric layer on the second insulating layer to cover the second metal pattern; forming a plurality of first vias passing through the gate insulating layer, the first insulating layer, the second insulating layer, and the interlayer dielectric layer at positions corresponding to the source region and the drain region; forming at least two third metal patterns on the interlayer dielectric layer, wherein the third metal patterns are connected to the source region and the drain region through the first vias, respectively; forming a planarization layer on the interlayer dielectric layer to cover the third metal patterns; and forming an organic light-emitting diode and a pixel definition layer on the planarization layer.

In one embodiment of the present invention, the step of forming an organic light-emitting diode and a pixel definition layer on the planarization layer includes: forming a second via passing through the planarization layer to expose the third metal pattern connecting to the drain region; forming a first electrode of the organic light-emitting diode on the planarization layer, wherein the first electrode is connected to the third metal pattern through the second via; and forming the pixel definition layer on the planarization layer, wherein the pixel definition layer includes an opening exposing the first electrode.

In one embodiment of the present invention, an area of the second metal pattern and an area of the first metal are both larger than an area of the gate.

In one embodiment of the present invention, before the step of sequentially forming a semiconductor layer, a gate insulating layer, a gate, and a first insulating layer on a substrate, further includes following step of: forming a first flexible layer, an inorganic film layer, a second flexible layer, and a buffer layer on the substrate, wherein the semiconductor layer is formed on the buffer layer.

In one embodiment of the present invention, the third metal patterns connecting to the source region and the drain region, the gate, and the semiconductor layer constitute a first transistor.

The present invention further provides a manufacturing method of an organic light-emitting diode array substrate, including steps of: sequentially forming a semiconductor layer, a gate insulating layer, a gate, and a first insulating layer on a substrate, wherein the semiconductor layer includes an active region, a source region, and a drain region; forming a through hole in the first insulating layer to partially expose the gate; forming a first metal pattern on the first insulating layer corresponding to a position of the gate, wherein the first metal pattern is connected to the gate through the through hole; forming a second insulating layer on the first insulating layer to cover the first metal pattern; and forming a second metal pattern on the second insulating layer corresponding to a position of the first metal pattern, wherein the second metal pattern and the first metal pattern overlap each other to form a capacitor.

In one embodiment of the present invention, the manufacturing method further includes following steps of: forming an interlayer dielectric layer on the second insulating layer to cover the second metal pattern; and forming a third metal pattern on the interlayer dielectric layer.

In one embodiment of the present invention, the step of forming a third metal pattern on the interlayer dielectric layer includes: forming a plurality of first vias passing through the gate insulating layer, the first insulating layer, the second insulating layer, and the interlayer dielectric layer at positions corresponding to the source region and the drain region; and forming at least two third metal patterns on the interlayer dielectric layer, wherein each of the third metal patterns are connected to the source region and the drain region through the first vias, respectively.

In one embodiment of the present invention, the manufacturing method further includes following steps of: forming a planarization layer on the interlayer dielectric layer to cover the third metal pattern; and forming an organic light-emitting diode and a pixel definition layer on the planarization layer.

In one embodiment of the present invention, the step of forming an organic light-emitting diode and a pixel definition layer on the planarization layer includes: forming a second via passing through the planarization layer to expose the third metal pattern connecting to the drain region; forming a first electrode of the organic light-emitting diode on the planarization layer, wherein the first electrode is connected to the third metal pattern through the second via; and forming the pixel definition layer on the planarization layer, wherein the pixel definition layer includes an opening exposing the first electrode.

In one embodiment of the present invention, an area of the second metal pattern and an area of the first metal are larger than an area of the gate.

In one embodiment of the present invention, before the step of sequentially forming a semiconductor layer, a gate insulating layer, a gate, and a first insulating layer on a substrate, wherein the semiconductor layer includes an active region, a source region, and a drain region further includes following step of: forming a first flexible layer, an inorganic film layer, a second flexible layer, and a buffer layer on the substrate; wherein the semiconductor layer is formed on the buffer layer.

In one embodiment of the present invention, the third metal patterns connecting to the source region and the drain region, the gate, and the semiconductor layer constitute a first transistor.

The present invention further provides an organic light-emitting diode array substrate, comprising a substrate, a semiconductor layer, a gate insulating layer, a gate, a first insulating layer, a first metal pattern, a second insulating layer, and a second metal pattern; the semiconductor layer disposed on the substrate, and the semiconductor layer comprising an active region, a source region, and a drain region; the gate insulating layer covering the semiconductor layer; the gate disposed on the gate insulating layer and corresponding to the active region of the semiconductor layer; the first insulating layer disposed on the gate and the first insulating layer comprising a through hole, wherein the through hole partially exposes the gate; the first metal pattern disposed on the first insulating layer, wherein the first metal pattern is connected to the gate through the through hole; the second insulating layer disposed on the first insulating layer and covering the first metal pattern; the second metal pattern disposed on the second insulating layer and corresponding to a position of the first metal pattern, wherein the second metal pattern and the first metal pattern overlap each other to form a capacitor.

In one embodiment of the present invention, a pixel unit of the organic light-emitting diode array substrate includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, the capacitor, and an organic light-emitting diode.

The beneficial effect: in the process of forming the organic light-emitting diode array substrate, the two metal pattern layers can be used as a capacitor in the pixel circuit by depositing the two metal pattern layers over the gate of the driving transistor in the pixel circuit. Thus, the area of the two electrode plates constituting the capacitor is no longer limited by the gate area of the driving transistor, which is more advantageous for the improvement of the storage capacitor capability.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top”, “bottom”, “front”, “back”, “left”, “right”, “inside”, “outside”, “side”, etc., is used with reference to the orientation of the figure(s) being described. As such, the directional terminology is used for purposes of illustration and is in no way limiting. Throughout this specification and in the drawings like parts will be referred to by the same reference numerals.

Please refer toFIG. 2andFIGS. 3A to 3C.FIG. 2is a partial cross-sectional view of an organic light-emitting diode array substrate according to an embodiment of the present invention.FIGS. 3A to 3Care schematic diagrams showing manufacturing processes of an organic light-emitting diode array substrate according to an embodiment of the present invention.

A pixel driving circuit using seven thin film transistors and a capacitor (7T1C) is adopted in the organic light-emitting diode array substrate of the present invention, and a pixel unit of the organic light-emitting diode array substrate includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a capacitor, and an organic light-emitting diode, wherein the first transistor serves as a driving transistor for driving the organic light-emitting diode.

The organic light-emitting diode array substrate is mainly improved for the first transistor and the capacitor. Therefore, the partial cross-sectional view of the organic light-emitting diode array substrate shown inFIG. 2mainly shows the structure of the first transistor and the capacitor in one pixel unit, and mainly includes a substrate10, a first transistor T1, and a capacitor.

Specifically, the substrate10may be a glass substrate, a first flexible layer11, an organic film layer12, a second flexible layer13, an M/B layer14, and a buffer layer15can be further disposed on the substrate10, sequentially. The first flexible layer11and the second flexible layer13may be flexible plastic substrates. The inorganic film layer12may be a silicon dioxide film layer. The buffer layer15may be an inorganic material, for example, a combination of one or more of silicon nitride, silicon oxide, silicon oxycarbide, silicon oxynitride, and silicon carbonitride.

Specifically, the first transistor T1includes a semiconductor layer16, a gate insulating layer18, a gate17, a source173, and a drain174. The semiconductor layer16is specifically disposed on the substrate10and may be disposed on the buffer layer15, and the semiconductor layer includes an active region160, a source region161, and a drain region162. The gate insulating layer18is formed on the buffer layer15to cover the semiconductor layer16. The gate17is formed on the gate insulating layer18and corresponding to the active region160of the semiconductor layer16. The source173and the drain174are connected to the source region161and the drain region162of the semiconductor layer16through a through hole200respectively, thereby constituting the first transistor T1.

In the organic light-emitting diode array substrate of the present invention, the capacitor is disposed above the first transistor T1, wherein the capacitor includes a bottom electrode plate171and a top electrode plate172. The bottom electrode plate171is disposed above the gate17of the first transistor T1, and the bottom electrode plate171is connected to the gate17such that the bottom electrode plate171and the gate17are equipotential. The top electrode plate172is disposed in parallel above the bottom electrode plate171. Specifically, a first insulating layer19is first disposed on the gate17and a through hole190is formed to partially expose the gate17. Then, a first metal pattern is formed on the first insulating layer19to serves as a bottom electrode plate171, and the bottom electrode plate17(the first metal pattern) is connected to the gate17through the through hole190. A second insulating layer20is then disposed on the first insulating layer19to cover the bottom electrode plate171(the first metal pattern). A second metal pattern is then formed on the second insulating layer20and corresponds to a position of the bottom electrode plate171(the first metal pattern) to serves as the top electrode plate172. Thereby, the top electrode plate172(the second metal pattern) and the bottom electrode plate171(the first metal pattern) constitute the capacitor.

An area of the bottom electrode plate171and an area of the top electrode plate172may be both larger than an area of the gate.

As can be seen from the above structure, because the bottom electrode plate171constituting the capacitor is additionally deposited over the gate17, the area of the bottom electrode plate171is no longer limited by the gate area of the driving transistor. The bottom electrode plate171can be designed to be larger than the area of the gate17, which is more advantageous for the improvement of the storage capacitor capability.

Please refer toFIGS. 3A to 3CandFIG. 4, in order to provide the organic light-emitting diode array substrate as above-described, a manufacturing method of an organic light-emitting diode array substrate is provided. The manufacturing method mainly includes the following steps S100to S104:

Step S100, sequentially forming a semiconductor layer16, a gate insulating layer18, a gate17, and a first insulating layer19on a substrate10, wherein the semiconductor layer16includes an active region160, a source region161, and a drain region162, as shown inFIG. 3A.

Step S101, forming a through hole190in the first insulating layer19to partially expose the gate17, as shown inFIG. 3B.

Step S102, forming a first metal pattern171on the first insulating layer19corresponding to a position of the gate17, wherein the first metal pattern171is connected to the gate17through the through hole190, as shown inFIG. 3C.

Step S103, forming a second insulating layer20on the first insulating layer19to cover the first metal pattern17, as shown inFIG. 3C.

Step S104, forming a second metal pattern172on the second insulating layer20corresponding to a position of the first metal pattern171, wherein the second metal pattern172and the first metal pattern171overlap each other to form a capacitor, as shown inFIG. 2.

In one embodiment, before the step S100further includes following step of:

Forming a first flexible layer11, an inorganic film layer12, a second flexible layer13, and a buffer layer15on the substrate10, wherein the semiconductor layer16is formed on the buffer layer15.

In one embodiment, the manufacturing method further includes following steps of:

Forming an interlayer dielectric layer21on the second insulating layer20to cover the second metal pattern172.

Forming a third metal pattern (173,174,175) on the interlayer dielectric layer21.

The interlayer dielectric layer21may be an inorganic material, such as silicon oxide (SiOx), silicon nitride (SiNx), or a layered structure (SiOx/SiNx or SiNx/SiOx).

Specifically, the step of forming a third metal pattern (173,174,175) on the interlayer dielectric layer includes:

Forming a plurality of first vias200passing through the gate insulating layer18, the first insulating layer19, the second insulating layer20, and the interlayer dielectric layer21at positions corresponding to the source region161and the drain region162.

Forming at least two third metal patterns (173,174) on the interlayer dielectric layer, wherein each of the third metal patterns (172,174) are connected to the source region161and the drain region162through the first vias200, respectively. The third metal pattern connecting to the source region161and the drain region162forms the source173and the drain174. The source173, the drain174, the gate17, and the semiconductor layer16constitute a first transistor T1.

In one embodiment, the manufacturing method further includes following steps of:

Forming a planarization layer30on the interlayer dielectric layer21to cover the third metal pattern (173,174,175).

Forming an organic light-emitting diode, a pixel definition layer40and a plurality of support elements on the planarization layer30. The planarization layer30may be a single layer structure or a multilayered structure, and material of the planarization layer30may include an inorganic material, an organic material, or other suitable materials. The inorganic material includes, for example, but not limited to, silicon oxide, silicon nitride or silicon oxynitride. The organic material includes, for example, but not limited to, an epoxy resin.

Specifically, the step of forming an organic light-emitting diode, a pixel definition layer40and a plurality of support elements on the planarization layer30include:

Forming a second via300passing through the planarization layer30to expose the third metal pattern174connecting to the drain region162.

Forming a first electrode60of the organic light-emitting diode on the planarization layer30, wherein the first electrode60is connected to the third metal pattern174(i.e., the drain) through the second via300.

Forming the pixel definition layer40on the planarization layer30, wherein the pixel definition layer40comprises an opening400exposing the first electrode60.

After the first electrode60(i.e., an anode) of the organic light-emitting diode is formed, the subsequent manufacturing steps of the organic light-emitting diode are similar to the existing technology, and will not be described herein.

Specifically, the area of the second metal pattern172and of the first metal pattern171may be larger than the area of the gate17to enhance storage capacities.

In summary, compared with the existing technology, the present invention provides two metal layers serving as the top/bottom electrode plate of the capacitor in the pixel circuit using 7T1C by depositing the two metal pattern layers over the gate of the driving transistor in the pixel circuit. Thus, the area of the two electrode plates constituting the capacitor is no longer limited by the gate area of the driving transistor, the area of the storage capacitor is increased, the storage capacity is increased, and the response rate is improved, and the signal transmission is more timely.

In view of the above, although the present invention has been disclosed by way of preferred embodiments, the above preferred embodiments are not intended to limit the present invention, and one of ordinary skill in the art, without departing from the spirit and scope of the invention, the scope of protection of the present invention is defined by the scope of the claims.