Apparatus comprising a differential amplifier

To make it possible to use a transistor with relatively low gate withstand voltage at an output stage in an apparatus including a differential amplifier. An apparatus is provided. The apparatus includes: a differential amplifier having a first current path and a second current path that form a differential pair; a first output-stage transistor that has: a first main terminal connected on a power-supply potential side; a second main terminal connected on a reference-potential side; and a control terminal connected to the second current path; and a first voltage-clamp circuit connected between the control terminal and second main terminal of the first output-stage transistor.

BACKGROUND

1. Technical Field

The present invention relates to an apparatus including a differential amplifier.

2. Related Art

There are conventional known buffer circuits that amplify input signals, and output amplified signals (see Patent Literatures 1 to 3, for example). Patent Literatures 1 and 2 describe buffer circuits that output output voltages corresponding to differential input. Patent Literature 3 describes a buffer circuit that is formed by configuring two current mirror circuits in a complementary circuit, and obtains an output signal.

Patent Literature 1: Japanese Patent Application Publication No. 2018-056750

Patent Literature 2: Japanese Patent Application Publication No. 2008-288900

Patent Literature 3: Japanese Patent Application Publication No. 2001-308695

One form of buffer circuits or the like having differential amplifiers obtains output signals by driving transistors at the output stages by using output from the differential amplifiers. Here, in a buffer circuit or the like operated by using a high power-supply voltage (e.g., 30 V), a transistor at the output stage might receive a high voltage from a differential amplifier, so a transistor with high gate withstand voltage is required inevitably.

SUMMARY

In order to solve the drawbacks mentioned above, a first aspect of the present invention provides an apparatus including: a differential amplifier having a first current path and a second current path that form a differential pair; a first output-stage transistor that has: a first main terminal connected on a power-supply potential side; a second main terminal connected on a reference-potential side; and a control terminal connected to the second current path; and a first voltage-clamp circuit connected between the control terminal and second main terminal of the first output-stage transistor.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

FIG. 1illustrates the configuration of an apparatus100according to the present embodiment. The apparatus100according to the present embodiment is configured to obtain an output signal by driving a transistor (an NMOS transistor HVMN3in the figure) in an output circuit130by using output from a differential amplifier120. With the differential amplifier120having the configuration illustrated inFIG. 1, the apparatus100can lower the gate withstand voltage required of the transistor driven by using output from the differential amplifier120. Here, in order to prevent breakdown of the control terminal of the transistor when a voltage exceeding the gate withstand voltage of the transistor is output due to abnormal operation or the like, the apparatus100is configured to include a first voltage-clamp circuit150provided between the control terminal of the transistor and its main terminal on the reference-potential side. In addition, providing the first voltage-clamp circuit150in the apparatus100might lead to loss of balance between currents to flow through a transistor pair (NMOS transistors MN1and2in the figure) that receives a differential input signal in the differential amplifier120. In order to suppress such loss of balance, the apparatus100may be configured to include a second voltage-clamp circuit160connected in a current path which is in the differential amplifier120, and is opposite to a current path in which the first voltage-clamp circuit150is connected.

The apparatus100is supplied with a power-supply potential VCC and a reference potential VSS, and outputs an output voltage Vout corresponding to an input reference voltage Vref. Here, the reference potential VSS may be ground potential (0 V) of the apparatus100, and the power-supply potential VCC is a potential higher than the reference potential VSS (e.g., 30V). The apparatus100according to the present embodiment for example functions as a voltage regulator that receives the reference voltage Vref which is a predetermined constant voltage, and outputs an output voltage Vout which is a constant voltage corresponding to the reference voltage.

The apparatus100includes a bias-voltage generating circuit110, the differential amplifier120, and the output circuit130. The bias-voltage generating circuit110is connected between the power-supply potential VCC and the reference potential VSS. In the specification of the present application, unless stated specifically, “connections” mean “electrical connections”, and are not limited to ones that are established by components being electrically connected directly. They may be indirect electrical connections between components that are established with other components being connected therebetween.

The bias-voltage generating circuit110generates a reference current Ib0that determines a tail current I0to flow through the differential amplifier120. In addition, the bias-voltage generating circuit110generates a bias voltage to be supplied to the differential amplifier120.

The bias-voltage generating circuit110has a current source Ib0, an NMOS transistor MN4, and an NMOS transistor MN5that are connected in series in this order from the power-supply potential VCC side. Although, in the configuration illustrated in this figure, the power-supply potential VCC, current source Ib0, NMOS transistor MN4, NMOS transistor MN5, and reference potential VSS are directly connected in series, the bias-voltage generating circuit110may instead be configured to include an additional constituting element provided between at least one pair of these constituting elements.

The current source Ib0generates the reference current Ib0, and feeds the reference current Ib0to the NMOS transistor MN4and NMOS transistor MN5. The NMOS transistor MN4has: a first main terminal (drain) connected to the current source Ib0; a second main terminal (source) connected to the NMOS transistor MN5; and a control terminal (gate) connected to the input terminal (Vref) of the apparatus100. The NMOS transistor MN4generates, on the first-main-terminal side, a voltage obtained by adding an offset to the reference voltage Vref received at the input terminal, and supplies the voltage to the differential amplifier120. The NMOS transistor MN5has: a first main terminal connected to the NMOS transistor MN4; a second main terminal connected to the reference potential VSS; and a control terminal connected to the first main terminal. The NMOS transistor MN5constitutes a current mirror circuit along with an NMOS transistor MN3in the differential amplifier120, adjusts a voltage at the control terminal to a voltage that allows flow of the reference current Ib0, and supplies the voltage to the NMOS transistor MN3.

The differential amplifier120is connected between the power-supply potential VCC and the reference potential VSS. The differential amplifier120has: an NMOS transistor MN3; a first current path in which the NMOS transistor MN1, an NMOS transistor HVMN1, a PMOS transistor HVMP1, and a PMOS transistor MP1are connected in series in this order from the NMOS transistor MN3side; and a second current path in which the NMOS transistor MN2, an NMOS transistor HVMN2, a PMOS transistor HVMP2, and a PMOS transistor MP2are connected in series in this order from the NMOS transistor MN3side. The first current path and second current path form a differential pair.

The NMOS transistor MN3has: a first main terminal (drain) connected to the NMOS transistor MN1and NMOS transistor MN2; a second main terminal (source) connected to the reference potential VSS; and a control terminal (gate) connected to the control terminal of the NMOS transistor MN5in the bias-voltage generating circuit110. The NMOS transistor MN3causes the tail current I0to flow, the tail current I0being obtained by multiplying the reference current Ib0flowing through the NMOS transistor MN5by a constant.

The NMOS transistor MN1is an exemplary first differential-input transistor. The NMOS transistor MN1has: a first main terminal (drain) that is provided on the power-supply potential side in the first current path, and is connected to the NMOS transistor HVMN1; a second main terminal that is provided on the reference-potential side in the first current path (source), and is connected to the NMOS transistor MN3; and a control terminal that receives the reference voltage Vref as first differential input. The NMOS transistor MN2is an exemplary second differential-input transistor that forms a pair with the NMOS transistor MN1. The NMOS transistor MN2has: a first main terminal that is provided on the power-supply potential side in the second current path, and is connected to the NMOS transistor HVMN2; a second main terminal that is provided on the reference-potential side in the second current path, and is connected to the NMOS transistor MN3; and a control terminal that receives second differential input. In the present embodiment, the NMOS transistor MN2receives, as the second differential input and at the control terminal, a voltage corresponding to a voltage on the second-main-terminal side (source) of the NMOS transistor HVMN3in the output circuit130. The NMOS transistor MN1and NMOS transistor MN2cause currents I2band I1bto flow, respectively, the currents I2band I1bbeing corresponding to the difference between the first differential input and second differential input. More specifically, if the reference voltage Vref as the first differential input is higher than a comparison target voltage received from the output circuit130as the second differential input, the NMOS transistor MN1and NMOS transistor MN2make the current I2blarger than the current I1b, and if the reference voltage Vref is lower than the comparison target voltage, the NMOS transistor MN1and NMOS transistor MN2make the current I2bsmaller than the current I1b. The total of the current I2band current I1bequals the tail current I0.

The NMOS transistor HVMN1is an exemplary first bias transistor. The NMOS transistor HVMN1has a main-terminal interconnecting portion (between the drain and the source) on the power-supply potential side of the NMOS transistor MN1in the first current path, and receives, at the control terminal (gate), a bias voltage from the bias-voltage generating circuit110. The NMOS transistor HVMN1is turned on if the bias voltage received at the control terminal is higher than a voltage at the second main terminal by an amount corresponding to or larger than a threshold voltage of the NMOS transistor HVMN1. Here, as a bias voltage to be received at the control terminal of the NMOS transistor HVMN1, the bias-voltage generating circuit110generates a voltage that turns on the NMOS transistor HVMN1, but does not cause breakdown of the control terminal even if the NMOS transistor HVMN1has low gate withstand voltage. Thereby, the NMOS transistor HVMN1restricts the voltage at the second main terminal to a voltage obtained by subtracting the gate-source voltage of the NMOS transistor HVMN1from the bias voltage. The NMOS transistor HVMN2is an exemplary second bias transistor that forms a pair with the NMOS transistor HVMN1. The NMOS transistor HVMN2has a main-terminal interconnecting portion (between the drain and the source) on the power-supply potential side of the NMOS transistor MN2in the second current path, and receives, at the control terminal (gate), a bias voltage from the bias-voltage generating circuit110. Similar to the NMOS transistor HVMN1, the NMOS transistor HVMN2restricts the voltage at the second main terminal to a voltage obtained by subtracting the gate-source voltage of the NMOS transistor HVMN2from the bias voltage.

The PMOS transistor HVMP1is an exemplary first power-supply side transistor. The PMOS transistor HVMP1has: a main-terminal interconnecting portion (source-drain) on the power-supply potential side of the NMOS transistor HVMN1in the first current path; and has a control terminal (gate) connected on the power-supply potential side of the NMOS transistor HVMN1. The PMOS transistor HVMP2is an exemplary second power-supply side transistor that forms a pair with the PMOS transistor HVMP1. The PMOS transistor HVMP2has: a main-terminal interconnecting portion on the power-supply potential side of the NMOS transistor HVMN2in the second current path; and a control terminal connected to the control terminal of the PMOS transistor HVMP1. That is, a current mirror connection is established between the PMOS transistor HVMP1and the PMOS transistor HVMP2.

The PMOS transistor MP1has: a main-terminal interconnecting portion (source-drain) on the power-supply potential side of the PMOS transistor HVMP1in the first current path; and has a control terminal (gate) connected on the power-supply potential side of the PMOS transistor HVMP1. The PMOS transistor MP2has: a main-terminal interconnecting portion (source-drain) on the power-supply potential side of the PMOS transistor HVMP2in the second current path; and has a control terminal (gate) connected to the control terminal of the PMOS transistor MP1. That is, a current mirror connection is established between the PMOS transistor MP1and the PMOS transistor MP2. The pair of the PMOS transistor HVMP1and PMOS transistor MP1, and the pair of the PMOS transistor HVMP2and PMOS transistor MP2change a voltage V2abetween the PMOS transistor HVMP1and the NMOS transistor HVMN1, and a voltage V1abetween the PMOS transistor HVMP2and the NMOS transistor HVMN2according to the difference between a current I2aflowing through the PMOS transistor HVMP1and PMOS transistor MP1, and a current I1aflowing through the PMOS transistor HVMP2and PMOS transistor MP2.

With the configuration illustrated above, the differential amplifier120makes the current I2blarger than the current I1bif the reference voltage Vref is higher than the comparison target voltage. Since the total of the current I2band current I1bis restricted by the tail current I0, and so the current I1bdecreases, a voltage drop due to the PMOS transistor MP2and PMOS transistor HVMP2decreases. As a result, the output voltage V1aof the differential amplifier120(a voltage between the PMOS transistor HVMP2and the NMOS transistor HVMN2) increases. Conversely, the differential amplifier120makes the current I2bsmaller than the current I0bif the reference voltage Vref is lower than the comparison target voltage. Since the total of the current I2band current I1bis restricted by the tail current I0, and so the current I1bincreases, a voltage drop due to the PMOS transistor MP2and PMOS transistor HVMP2increases. As a result, the output voltage V1aof the differential amplifier120(a voltage between the PMOS transistor HVMP2and the NMOS transistor HVMN2) decreases.

In the example illustrated above, the NMOS transistor MN1and NMOS transistor MN2, the NMOS transistor HVMN1and NMOS transistor HVMN2, the PMOS transistor HVMP1and PMOS transistor HVMP2, and the PMOS transistor MP1and PMOS transistor MP2, respectively forming pairs, desirably share the same characteristics. In view of this, each pair of transistors mentioned above may be designed and produced to have identical design parameters (channel length, channel width, gate length, etc.).

The output circuit130is connected between the power-supply potential VCC and the reference potential VSS. The output circuit130has the NMOS transistor HVMN3, an NMOS transistor HVMN4, a voltage conversion circuit140, the first voltage-clamp circuit150, a load145, a resistor R4, a PMOS transistor HVMP3, a PMOS transistor MP3, and a PMOS transistor MP4.

The NMOS transistor HVMN3is an exemplary first output-stage transistor. The NMOS transistor HVMN3has: a first main terminal (drain) connected on the power-supply potential side; a second main terminal (source) connected on the reference-potential side; and a control terminal (gate) connected to the second current path. That is, the NMOS transistor HVMN3constitutes a source follower circuit. In the present embodiment, the control terminal of the NMOS transistor HVMN3is connected to the second current path on the power-supply potential side of the NMOS transistor HVMN2, more specifically, between the NMOS transistor HVMN2and the PMOS transistor HVMP2. The NMOS transistor HVMN3has a resistance at the main-terminal interconnecting portion that is controlled according to the output voltage V1aof the differential amplifier120, and outputs, through the second main terminal, an output voltage that changes according to the output voltage V1a.

The NMOS transistor HVMN4is an exemplary second output-stage transistor. The NMOS transistor HVMN4has: a first main terminal (drain) connected on the power-supply potential side; a second main terminal (source) connected on the reference-potential side; and a control terminal (gate) connected to the second current path. That is, the NMOS transistor HVMN4constitutes a source follower circuit. The NMOS transistor HVMN4also has a resistance at the main-terminal interconnecting portion that is controlled according to the output voltage V1aof the differential amplifier120, and outputs, through the second main terminal, an output voltage that changes according to the output voltage V1a. The NMOS transistor HVMN4may output the voltage at the second main terminal as the output voltage Vout to an external instrument or the like to which the apparatus100is connected. In the present embodiment, the NMOS transistor HVMN3and NMOS transistor HVMN4may be designed and produced to have the same potential difference between each pair of their control terminals and second main terminals (the gate-source voltage in this figure) when they are turned on. Thereby, an output voltage output from the second main terminal of the NMOS transistor HVMN3becomes substantially identical to the output voltage Vout output from the second main terminal of the NMOS transistor HVMN4, although there can be a certain degree of error therebetween. In the present specification, it is assumed that the NMOS transistor HVMN3and NMOS transistor HVMN4output the identical output voltages Vout for convenience of explanation.

Note that the apparatus100may not include the NMOS transistor HVMN4, but may be configured to supply the voltage at the second main terminal of the NMOS transistor HVMN3to at least one of the load145, an external instrument, or the like. In addition, the apparatus100may include a plurality of NMOS transistors HVMN4, and may be configured to supply the output voltage Vout to each of a plurality of loads145, a plurality of instruments, or the like.

The voltage conversion circuit140generates a voltage corresponding to the voltage Vout on the second-main-terminal side of the NMOS transistor HVMN3, and inputs the voltage to the control terminal of the NMOS transistor MN2in the differential amplifier120as the comparison target voltage. The voltage conversion circuit140according to the present embodiment is a resistive voltage divider for example, and resistively divides the output voltage Vout at a resistor R2and a resistor R3. Thereby, the NMOS transistor MN2can receive, at the control terminal, a voltage obtained by dividing the voltage on the reference-potential side of the NMOS transistor HVMN3.

As mentioned above, if the reference voltage Vref becomes higher than the comparison target voltage, the output voltage V1aof the differential amplifier120rises. Along with this, the resistance between the drain and source of the NMOS transistor HVMN3decreases, and the output voltage Vout rises. Conversely, if the reference voltage Vref becomes lower than the comparison target voltage, the output voltage V1aof the differential amplifier120falls. Along with this, the resistance between the drain and source of the NMOS transistor HVMN3increases, and the output voltage Vout falls. In this manner, the apparatus100performs feedback operation such that the comparison target voltage becomes equal to the reference voltage Vref. Here, if the voltage conversion circuit140resistively divides the output voltage Vout such that it becomes 1/N, the apparatus100performs operation such that “comparison target voltage 1/N·Vout” becomes equal to the reference voltage Vref. As a result, the apparatus100performs operation such that the output voltage Vout becomes equal to N·Vref. Note that the apparatus100may not have the voltage conversion circuit140, but may supply the output voltage Vout directly to the control terminal of the NMOS transistor MN2. In this case, the apparatus100performs operation such that the output voltage Vout becomes equal to the reference voltage Vref.

The first voltage-clamp circuit150is connected between the control terminal and second main terminal of the NMOS transistor HVMN3, and restricts the potential difference between the voltage at the control terminal of the NMOS transistor HVMN3and the voltage at the second main terminal of the NMOS transistor HVMN3such that it becomes equal to or smaller than a predetermined potential difference. The first voltage-clamp circuit150may have at least one Zener diode ZD1having an anode that is connected on the second-main-terminal side of the NMOS transistor HVMN3, and a cathode that is connected on the control terminal side of the NMOS transistor HVMN3. As necessary, the first voltage-clamp circuit150may be configured to include a plurality of Zener diodes that are provided in parallel if it is necessary to cause a large current to flow at the time of breakdown, and may be configured to include a plurality of Zener diodes that are provided in series if a voltage to be restricted is made high. The first voltage-clamp circuit150may be another known circuit instead of a circuit using Zener diodes, and restrict the voltage of the control terminal using the voltage at the second main terminal of the NMOS transistor HVMN3as a reference voltage. Since the gate-source voltage applied between the gate and source of the NMOS transistor HVMN3can be restricted by providing the first voltage-clamp circuit150, it becomes possible to prevent breakdown of the control terminal of the NMOS transistor HVMN3. Stated differently, it becomes unnecessary to increase the gate withstand voltage of the NMOS transistor HVMN3.

The load145is a circuit that performs operation by receiving the output voltage Vout of the NMOS transistor HVMN4. The load145is provided in an apparatus such as an integrated circuit including the apparatus100, receives the output voltage Vout from the NMOS transistor HVMN4, and performs operation in accordance with the specifications of the apparatus.

The resistor R4, the main-terminal interconnecting portion of the PMOS transistor HVMP3, and the main-terminal interconnecting portion of the PMOS transistor MP3form a constant-current circuit connected in series in this order between the PMOS transistor HVMP3and the power-supply potential VCC. The resistor R4generates a voltage drop having a magnitude corresponding to a current flowing therethrough. The PMOS transistor HVMP3has a control terminal that is connected between the resistor R4, and NMOS transistors HVMN3to4, and receives, at the control terminal, a voltage that has fallen from the voltage at the main terminal on the NMOS transistor HVMN3side due to the resistor R4. The PMOS transistor MP3has a control terminal that is connected between the PMOS transistor HVMP3and the resistor R4, and receives, at the control terminal, a voltage that has fallen from the voltage at the main terminal on the PMOS transistor HVMP3side due to the PMOS transistor HVMP3. Thereby, the PMOS transistor HVMP3and PMOS transistor MP3receive a voltage equal to or higher than a threshold voltage between each pair of their sources and gates, and are turned on. Thus, the resistor R4, the main-terminal interconnecting portion of the PMOS transistor HVMP3, and the main-terminal interconnecting portion of the PMOS transistor MP3cause a constant current that is preset by the resistance of the resistor R4to flow. Accordingly, the NMOS transistor HVMN3at a latter stage causes a current that is determined by the resistors R2and R3inside the voltage conversion circuit140, and the reference voltage Vref to flow through the main-terminal interconnecting portion.

The PMOS transistor MP4has: a main-terminal interconnecting portion that is connected between the power-supply potential VCC and the reference potential VSS; and a control terminal connected to the control terminal of the PMOS transistor MP3. A current mirror connection is established between the PMOS transistor MP4and the PMOS transistor MP3, and the PMOS transistor MP4, along with the PMOS transistor MP3, constitutes a current mirror circuit connected between the power-supply potential VCC and the PMOS transistor HVMP3. With such a configuration, the PMOS transistor MP4can generate a constant current that is obtained by multiplying a constant current flowing though the PMOS transistor MP3by a constant, and provide the constant current to an integrated circuit or the like provided with the apparatus100or an external circuit.

Note that if a constant current is not necessary, the apparatus100may be configured to not include a constant-current circuit and a current mirror circuit that include the resistor R4, PMOS transistor HVMP3, PMOS transistor MP3, and PMOS transistor MP4.

In addition to the configuration mentioned above, the apparatus100may include a resistor R1and a capacitor C1that are connected in series between the control terminal of the NMOS transistor HVMN3and the reference potential VSS. The resistor R1and capacitor C1perform phase compensation for a feedback control loop, and prevent oscillation of the output voltage Vout.

In addition, the apparatus100may further include a second voltage-clamp circuit160connected between the first current path in the differential amplifier120and the reference potential VSS. The second voltage-clamp circuit160may include at least one Zener diode ZD2that has an anode connected to the reference potential VSS, and is connected to the first current path.

The differential amplifier120ideally changes a current that flows through the first current path and a current that flows through the second current path complementarily without causing the currents that flow through the first current path and second current path to flow out of the differential amplifier120, and make the magnitudes of the currents the same when the first differential input and the second differential input are equal to each other. Here, since the NMOS transistor HVMN3having relatively low gate withstand voltage us used, the first voltage-clamp circuit150is provided between the control terminal and second main terminal of the NMOS transistor HVMN3. If a leakage current occurs in the first voltage-clamp circuit150, a current Ileak1inevitably leaks from the second current path due to the first voltage-clamp circuit150, and balance is lost between the current that flows through the first differential-input transistor and the current that flows through the second differential-input transistor, and an error is generated in the output voltage Vout. In view of this, the apparatus100may further include the second voltage-clamp circuit160which makes a current Ileak2leak from the first current path. Since, by using the first voltage-clamp circuit150and second voltage-clamp circuit160having substantially identical characteristics, the current Ileak2becomes substantially identical to the current Ileak1, the apparatus100can make the current I2bthat flows through the first differential-input transistor and the current I1bthat flows through the second differential-input transistor balanced.

In the present embodiment, the second voltage-clamp circuit160is connected to the first current path between the NMOS transistor HVMN1and the NMOS transistor MN1. Thereby, as compared with the case where the second voltage-clamp circuit160is connected on the power-supply potential side of the NMOS transistor HVMN1similar to the first voltage-clamp circuit150, it becomes possible to prevent changes of the voltage V2afrom being inhibited due to breakdown of the second voltage-clamp circuit160.

In the example mentioned above, transistors having relatively low gate withstand voltage and drain-source withstand voltage can be used as the PMOS transistors MP1to3and NMOS transistors MN1to5. In addition, transistors having relatively low gate withstand voltage can be used as the PMOS transistors HVMP1to3and NMOS transistor HVMN1to2, although they are required to have high drain-source withstand voltage. Then, although the NMOS transistor HVMN3is required to have high drain-source withstand voltage, a transistor having relatively low gate withstand voltage can be used as the NMOS transistor HVMN3by providing the first voltage-clamp circuit150between its control terminal and second main terminal. Although the NMOS transistor HVMN4is required to have high drain-source withstand voltage, since it receives, at its control terminal, the same voltage as that of the NMOS transistor HVMN3, and outputs, from the second main terminal, the same output voltage as that of the NMOS transistor HVMN3, a transistor having relatively low gate withstand voltage can be used as the NMOS transistor HVMN4, similar to the NMOS transistor HVMN3. Note that, in this figure, transistors having high drain-source withstand voltage are indicated by symbols including “HV (High Voltage)”.

In this manner, the apparatus100can be configured not to include transistors having high gate withstand voltage. Here, although high drain-source withstand voltage can be realized by increasing the distance between a drain and a source, attaining high gate withstand voltage might require addition or changes in production processes in order to increase the film thicknesses of gate insulators. Thus, the apparatus100configured not to include transistors having high gate withstand voltage can be produced at reduced costs.

FIG. 2illustrates exemplary leakage characteristics of a first voltage-clamp circuit according to the present embodiment. In this figure, the horizontal axis corresponds to temperature, and the vertical axis corresponds to leakage current. In the example illustrated in this figure, the Zener diode ZD1used as the first voltage-clamp circuit150generates leakage current that increases as the temperature rises.

FIG. 3illustrates exemplary output-voltage characteristics of the apparatus100according to the present embodiment. In this figure, the horizontal axis corresponds to temperature, and the vertical axis corresponds to the output voltage Vout of the apparatus100. The output-voltage characteristics curve400indicates output-voltage characteristics of the apparatus100when the first voltage-clamp circuit150is provided, but the second voltage-clamp circuit160is not provided. The output-voltage characteristics curve410indicates the output-voltage characteristics of the apparatus100when the first voltage-clamp circuit150and second voltage-clamp circuit160are provided.

If the apparatus100is not provided with the second voltage-clamp circuit160, the current I2bthat flows through the NMOS transistor MN1in the first current path becomes equal to I2a, and the current I1bthat flows through the NMOS transistor MN2in the second current path becomes equal to I1a−Ileak1. Accordingly, when the state of the differential amplifier120is balanced (I2a=I1a), the current I1bthat flows through the second differential-input transistor MN2becomes equal to I2b−Ileak1, and the voltage at the control terminal of the second differential-input transistor MN2is stabilized at a voltage lower than the reference voltage Vref received at the control terminal of the first differential-input transistor MN1. As a result, in the apparatus100, as the temperature rises and the current Ileak1increases, the control voltage of the NMOS transistor HVMN3lowers, and the output voltage Vout inevitably falls as indicated by the output-voltage characteristics curve400.

In contrast, if the apparatus100is provided with the second voltage-clamp circuit160, the current I2bthat flows through the NMOS transistor MN1in the first current path becomes equal to I1a−Ileak2, and the current I1bthat flows through the NMOS transistor MN2in the second current path becomes equal to I1a−Ileak1. Accordingly, by configuring the first voltage-clamp circuit150and second voltage-clamp circuit160identically such that Ileak2≈Ileak1, if the first differential input and second differential input have the same voltage (I1b=I2b), the currents I1aand I1athat flow through the PMOS transistor MP2and PMOS transistor HVMP2become approximately equal. As a result, the apparatus100can suppress lowering of the output voltage Vout accompanying an increase of the leakage current Ileak1of the first voltage-clamp circuit150as illustrated in the output-voltage characteristics curve410.

FIG. 4illustrates exemplary consumed-current characteristics of the apparatus100according to the present embodiment. In this figure, the horizontal axis corresponds to temperature, and the vertical axis corresponds to consumed current Ivcc of the apparatus100. The consumed-current characteristics curve500indicates consumed-current characteristics of the apparatus100when the first voltage-clamp circuit150is provided, but the second voltage-clamp circuit160is not provided. The consumed-current characteristics curve510indicates consumed-current characteristics of the apparatus100when the first voltage-clamp circuit150and second voltage-clamp circuit160are provided.

If the apparatus100is not provided with the second voltage-clamp circuit160, the consumed current of the apparatus100increases as indicated by the consumed-current characteristics curve500along with a temperature increase, due to the influence of leakage current in first voltage-clamp circuit150. If the apparatus100is provided with the second voltage-clamp circuit160, the consumed current is not different from that in the configuration provided with the second voltage-clamp circuit160until the temperature reaches about 100 degrees. At the temperature of 100 degrees or higher, the consumed current increases by an amount corresponding to addition of the second voltage-clamp circuit160having the leakage characteristics illustrated inFIG. 2, as indicated by the consumed-current characteristics curve510. Although the consumed current increases as illustrated, if the apparatus100might be operated in an environment where an error that cannot be neglected is generated in the output voltage Vout due to the leakage current Ileak1of the first voltage-clamp circuit150or in other cases, the apparatus100may be configured to include the second voltage-clamp circuit160.

In the embodiment mentioned above, the apparatus100is illustrated as a voltage regulator that receives the reference voltage Vref which is a constant voltage, and outputs the output voltage Vout which is a constant voltage. Instead, the apparatus100may be an output buffer apparatus that receives an input signal the voltage value of which is variable as the first differential input, and outputs the output voltage Vout the voltage of which changes corresponding to the input signal. In addition, the apparatus100may be a differential buffer apparatus that receives, instead of a voltage corresponding to the output voltage Vout as the second differential input, a differential signal as the first differential input and second differential input, and outputs an output voltage corresponding to the differential signal.

In addition, in the embodiment mentioned above, the apparatus100illustrated uses P channel type MOS transistors as the PMOS transistors MP1to3and PMOS transistors HVMP1to3, and N channel type MOS transistors as the NMOS transistors HVMN1to4and NMOS transistors MN1to5. Instead, in the apparatus100, at least one P channel type MOS transistor may be replaced with an N channel type MOS transistor, and/or at least one N channel type MOS transistor may be replaced with a P channel type MOS transistor, and surrounding circuits in the apparatus100may be configured differently as appropriate according to such changes.

In addition, in the embodiment mentioned above, the apparatus100illustrated uses MOS transistors each having a control terminal that is called a gate, and two main terminals that are called a drain and a source, as the PMOS transistors MP1to3, PMOS transistors HVMP1to3, NMOS transistors HVMN1to4, and NMOS transistors MN1to5. Instead, the apparatus100may use a bipolar transistor or the like having a control electrode that is called a base, and two main electrodes that are called a collector and an emitter, as at least one of the transistors mentioned above. In addition, the apparatus100may use IGBTs (insulated gate bipolar transistors) each having a control terminal that is called a gate, and two main terminals that are called a collector and an emitter, as the NMOS transistor HVMN3and NMOS transistor HVMN4, if it is to output large current. Part of circuits in the apparatus100may be configured differently as appropriate according to such changes.