Semiconductor device

A semiconductor device includes a semiconductor element including a current mirror circuit, a parasitic resistance formed at the current mirror circuit, and a connection terminal electrically connected to a part of the current mirror circuit via an electric conductor including a bonding wire, the connection terminal being configured to perform input and output relative to an outside of the semiconductor device; wherein a resistance value of the bonding wire is controlled so that a shift of an output electric current of the current mirror circuit based on the parasitic resistance is corrected.

CROSS-REFERENCE TO RELATED APPLICATIONS

This patent application is based upon and claims the benefit of priority of Japanese Patent Application No. 2008-278720 filed on Oct. 29, 2008 the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to semiconductor devices. More specifically, the present invention relates to a semiconductor device including a current mirror circuit.

2. Description of the Related Art

Conventionally, current mirror circuits formed by transistors have been used as parts of various circuits. The current mirror circuit includes two transistors. An electric current having a designated rate flows to each of the transistors. In such a current mirror circuit, if there is unevenness in electric characteristics between the transistors, the electric current having the designated rate cannot flow. Because of this, the current mirror circuit is formed by transistors having equal channel lengths and channel widths so that characteristics of the transistors are the same. See, for example, Japanese Laid-Open Patent Application Publication No. 2007-318094.

However, the electric current having the designated rate may not flow by only making the characteristics of the transistors the same. In other words, in the semiconductor device where the current mirror circuit is formed, due to parasitic resistance of a metal wiring or the like connected to the current mirror circuit, the rate of the electric current flowing to each of the transistors may be shifted from a designated rate.

SUMMARY OF THE INVENTION

Accordingly, embodiments of the present invention may provide a novel and useful semiconductor device solving one or more of the problems discussed above.

More specifically, the embodiments of the present invention may provide a semiconductor device including a current mirror circuit, whereby it is possible to prevent the rate of the electric current flowing to each of the transistors from being shifted from a designated rate.

Another aspect of the present invention may be to provide a semiconductor device, including a semiconductor element including a current mirror circuit; a parasitic resistance formed at the current mirror circuit; and a connection terminal electrically connected to a part of the current mirror circuit via an electric conductor including a bonding wire, the connection terminal being configured to perform input and output relative to an outside of the semiconductor device; wherein a resistance value of the bonding wire is controlled so that a shift of an output electric current of the current mirror circuit based on the parasitic resistance is corrected.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A description is given below, with reference to theFIG. 1throughFIG. 6of embodiments of the present invention.

First Embodiment

FIG. 1is a perspective view of a semiconductor device of a first embodiment of the present invention.FIG. 2is a partial schematic view showing an inside of the semiconductor device of the first embodiment of the present invention. Referring toFIG. 1andFIG. 2, a semiconductor device10includes a lead frame20, a semiconductor element30, bonding wires40athrough40kand a sealing part50.

In the semiconductor device10, the lead frame20includes an island part21and lead parts22athrough22hsituated outside the island part21. The lead frame20is formed by forming a metal layer on a surface of a metal body. The metal body is made of, for example, Cu, Cu alloy, or the like. The metal layer is made of, for example, Au, Sn, Sn—Ag, or the like. The semiconductor element30is adhered on an upper surface of the island part21of the lead frame20by adhesive or the like (not illustrated inFIG. 1).

The semiconductor element30is formed by forming a semiconductor integrated circuit (not illustrated inFIG. 1) including a transistor or the like formed on a semiconductor substrate (not illustrated inFIG. 1). The semiconductor element30includes a current mirror circuit11discussed below. The semiconductor integrated circuit (not illustrated inFIG. 1) includes, for example, a diffusion layer (not illustrated inFIG. 1), an insulation layer (not illustrated inFIG. 1), a via-hole (not illustrated inFIG. 1), a wiring (not illustrated inFIG. 1), and other parts. The semiconductor element30includes plural electrode pads31athrough31kwhich are electrically connected to the semiconductor integrated circuit (not illustrated inFIG. 1). As materials of the electrode pads31athrough31k, for example, Al can be used. However, there is no limitation to the materials of the electrode pads31athrough31k. As the materials of the electrode pads31athrough31k, other materials where an Al layer is formed on a Cu layer may be used.

The bonding wires40athrough40kelectrically connect the electrode pads31athrough31kof the semiconductor element30to corresponding lead parts22athrough22h. As materials of the bonding wires40athrough40k, for example, Au can be used. However, there is no limitation to the materials of the bonding wires40athrough40k. As the materials of the bonding wires40athrough40k, other materials such as an alloy including Au, Al, an alloy including Al, Cu, or an alloy including Cu may be used.

The lead frame20, the semiconductor element30, and the bonding wires40athrough40kare sealed by the sealing part50so that portions of the lead parts22athrough22hof the lead frame20are exposed. Epoxy group thermosetting resin, for example, can be used as a material of the sealing part50. Portions of the lead parts22athrough22hof the lead frame20sealed by the sealing part50may be called inner leads. Portions of the lead parts22athrough22hof the lead frame20which are exposed may be called outer leads. The outer lead functions as an outside connection terminal configured to electrically connect the semiconductor device10to a wiring board or the like situated outside the semiconductor device10. Thus, the lead parts22athrough22hare electrically connected to the semiconductor element30by electric conductors including the bonding wires40athrough40k. The lead parts22athrough22hare connection terminals configured to input or output signals to or from the outside of the semiconductor device10.

FIG. 3is a circuit diagram of a current mirror circuit included in the semiconductor device of the first embodiment of the present invention. Referring toFIG. 3, a current mirror circuit11is included in the semiconductor element30of the semiconductor device10. The current mirror circuit11includes an FET32and FETs33. N (n=natural number) of the FETs33are connected, in parallel, to the FET32; “n” may be, for example, approximately 500. InFIG. 3, “Iref” denotes a reference current and “Io” denotes an output current.

A drain32D of the FET32is connected to the electrode pads31athrough31dvia a metal wiring34such as Al. As shown inFIG. 2, the electrode pads31athrough31dare connected to the lead part22avia the bonding wires40athrough40d. A source32S of the FET32is connected to a source33S of the FET33and further connected to an inside circuit (not illustrated inFIG. 3) via a metal wiring such as Al. A gate32G of the FET32is connected to a drain33D and a gate33G of the FET33and further connected to an inside circuit (not illustrated inFIG. 3) via a metal wiring35such as Al. “Ra” and “Rb” denote parasitic resistances of the metal wirings34and35, respectively, such as Al. “Rc” through “Rf” denote respective resistances of the bonding wires40athrough40d. Although the lead part22aalso has resistance, the resistance of the lead part22ais sufficiently smaller than the parasitic resistances of the metal wirings34and35and the resistances of the bonding wires40athrough40dand therefore can be disregarded.

FIG. 4is a view showing an example of a layout of the current mirror circuit11included in the semiconductor device30of the first embodiment of the present invention. InFIG. 4, only the drain32D of the FET32, the drain33D of the FET33, the metal wirings34and35, the electrode pads31athrough31d, the bonding wires40athrough40dand the lead part22aare illustrated. Illustrations of the source32S of the FET32and other parts are omitted inFIG. 4. Although the drains320of the FET32are laid out at both sides of the drain330of the FET33, the layout is not limited to this example.

It is ideal that, in the current mirror circuit11shown inFIG. 3andFIG. 4, the parasitic resistances of the metal wirings34and35have zero Ω (ohms). A number n (n=natural number) of the FETs33are connected, in parallel, to the FET32. Accordingly, if the parasitic resistances of the metal wirings34and35have zero Q, the following formula 1 holds true.
Io=n×Iref(Numerical Formula 1)
However, actually the parasitic resistances Ra and Rb are not zero Ω, the numerical formula 1 does not hold true and therefore a desirable electric current value Io cannot be obtained.

In order to satisfy the above-mentioned numerical formula 1, it is necessary for the resistance value of the parasitic resistance Ra connected to the drain320of the FET32to be 1/n of the resistance value of the parasitic resistance Rb connected to the drain33D of the FET33. In order to realize this, arrangement of the metal wirings34and35may be controlled. However, since there is limitation of the arrangement of the metal wirings34and35in terms of the layout, it may be difficult to realize this.

Because of this, in the embodiments of the present invention, resistances of not only the metal wirings34and35but also the metal wirings34and35and the bonding wires40a-40dare considered. In other words, by changing the number, the diameter, the length and/or a material of the bonding wires40a-40d, shift of an output electric current Io of the current mirror circuit11due to the parasitic resistances Ra and Rb is corrected. With this structure, even if the parasitic resistances Ra and Rb are not zero Ω, the numerical formula 1 is satisfied so that a desirable electric current value is obtained. In the example shown inFIG. 3andFIG. 4, four electrode pads31athrough31dconnected to the drain32D of the FET32via the metal wiring34are provided. The electrode pads31athrough31dand the lead part22aare connected to each other by the bonding wires40athrough40d. The bonding wires40athrough40dare connected in parallel.

As a result of this, the relationship between the sum of the resistance values of the resistance and the parasitic resistance connected to the drain32D of the FET32, namely “Ra+Rc//Rd//Re//Rf” (parasitic resistance Ra plus the equivalent resistance of parallel resistances Rc, Rd, Re and Rf), and a resistance value “Rb” of the parasitic resistance connected to the drain33D of the FET33can be expressed by the following numerical formula 2.
Ra+Rc//Rd//Re//Rf=1/n×Rb(Numerical Formula 2)
Not only the number of the bonding wires40athrough40kbut also the diameter, length, or material of the bonding wires40athrough40kmay be controlled.

Even if the number of the bonding wires is four (bonding wires40athrough40d), the above-mentioned numerical formula 2 does not always hold true. In this embodiment, by changing the number, diameter, length or material of the bonding wires so that the above-mentioned formula 2 is satisfied, the resistance value of the bonding wires is controlled so as to be a value where the shift of the output electric current Io of the current mirror circuit11due to the parasitic resistances Ra and Rb is corrected. In order to satisfy the numerical formula 2 by controlling the resistances Re through Rf of the bonding wires40athrough40d, the parasitic resistance Ra should be set in advance so as to be sufficiently smaller than the parasitic resistance Rb.

According to the first embodiment of the present invention, in the semiconductor device10including the current mirror circuit11having the FET33and FET32where n (n=natural number) of the FETs33are connected in parallel, by controlling the number, diameter, length or material of the bonding wires40athrough40d, the sum of the resistance values of the resistance and the parasitic resistance connected to the drain32D of the FET32should be 1/n of the resistance value of the parasitic resistance connected to the drain33D of the FET33. As a result of this, it is possible to prevent generation of shift of the electric current value due to the parasitic resistance and therefore the desirable electric current value Io=n×Iref can be obtained.

Second Embodiment

FIG. 5is a circuit diagram of a current mirror circuit included in a semiconductor device of a second embodiment of the present invention.FIG. 6is a view showing an example of a layout of the current mirror circuit included in the semiconductor device of the second embodiment of the present invention. InFIG. 5andFIG. 6, parts that are the same as the parts shown inFIG. 3andFIG. 4are given the same reference numerals, and explanation thereof is omitted.

As shown inFIG. 5andFIG. 6, in a current mirror circuit12included in a semiconductor device10A of the second embodiment of the present invention, the electrode pads31aand31bare connected to the lead part22avia the bonding wires40aand40b. In addition, the electrode pads31cand31dare connected to the lead part22bvia the bonding wires40cand40d. Structures of other parts of the current mirror circuit12included in the semiconductor device10A of the second embodiment of the present invention are the same as those of the current mirror circuit11included in the semiconductor device10of the first embodiment of the present invention. Hence, in the following description, only parts of the current mirror circuit12different from the current mirror circuit11are discussed.

In the current mirror circuit12shown inFIG. 5andFIG. 6, the four electrode pads31athrough31dconnected to the drain32D of the FET32via the metal wiring34are provided. The electrode pads31aand31band the lead part22aare connected to each other by the bonding wires40aand40b. The electrode pads31cand31dand the lead part22bare connected to each other by the bonding wires40cand40d. As discussed above, the parts (outer lead) of the lead parts22athrough22hare exposed from the sealing part50and function as outside connection terminals for electrically connecting to the wiring board or the like provided outside the semiconductor device10A. The current mirror circuit12included in the semiconductor device10A of the second embodiment of the present invention is designed based on the assumption that the lead parts22aand22bexposed from the sealing part50are short-circuited by the wiring pattern of the wiring board or the like when the semiconductor device10A is mounted on the wiring board or the like.

The lead parts22aand22bare short-circuited by the wiring pattern of the wiring board or the like so that the bonding wires40athrough40dare connected in parallel.

As a result of this, the relationship between the sum of the resistance values of the resistance and the parasitic resistance connected to the drain32D of the FET32, namely “Re+Rc//Rd//Re//Rf”, and a resistance value “Rb” of the parasitic resistance connected to the drain33D of the FET33can be expressed by the following numerical formula 2.
Ra+Rc//Rd//Re//Rf=1/n×Rb(Numerical Formula 2)
Not only the number of the bonding wires40athrough40kbut also the diameter, length, or material of the bonding wires40athrough40kmay be controlled.

Even if the number of the bonding wires is four (bonding wires40athrough40d), the above-mentioned numerical formula 2 does not always hold true. In this embodiment, by changing the number, diameter, length or material of the bonding wire so that the above-mentioned formula 2 is satisfied, the resistance value of the bonding wire is controlled so as to be a value where the shift of the output electric current Io of the current mirror circuit11due to the parasitic resistances Ra and Rb is corrected. In order to satisfy the numerical formula 2 by controlling the resistances Rc through Rf of the bonding wires40athrough40d, the parasitic resistance Ra should be set in advance so as to be sufficiently smaller than the parasitic resistance Rb.

According to the second embodiment of the present invention, in the semiconductor device10A including the current mirror circuit12having the FET33and FET32where n (n=natural number) of the FETs33are connected in parallel, the bonding wires40aand40bare connected to the lead part22aand the bonding wires40cand40dare connected to the lead part22bbased on the assumption that the lead parts22aand22bexposed from the sealing part50are short-circuited. In addition, by controlling the number, diameter, length or material of the bonding wires40athrough40d, the sum of the resistance values of the resistance and the parasitic resistance connected to the drain32D of the FET32should be 1/n of the resistance value of the parasitic resistance connected to the drain33D of the FET33. As a result of this, it is possible to prevent generation of a shift of the electric current value due to the parasitic resistance and therefore the desirable electric current value Io=n×Iref can be obtained.

According to the embodiments of the present invention, it is possible to provide a semiconductor device (10), including a semiconductor element (30) including a current mirror circuit (11,12); a parasitic resistance (Re, Rb) formed at the current mirror circuit (11,12); and a connection terminal (20a,20b) electrically connected to a part of the current mirror circuit (11,12) via an electric conductor including a bonding wire (40athrough40d), the connection terminal (20a,20b) being configured to perform input and output relative to an outside the semiconductor device (10); wherein a resistance value (Rc through Rf) of the bonding wire (40athrough40d) is controlled so that a shift of an output electric current (Io) of the current mirror circuit (11,12) based on the parasitic resistance (Ra, Rb) is corrected. It should be noted that the numerical references indicated in the immediately above sentence are indicated just for easy understanding and the present invention is not limited to the examples shown in drawings.

Thus, according to the embodiments of the present invention, it is possible to provide a semiconductor device including a current mirror, whereby it is possible to prevent the rate of the electric current flowing to each of the transistors from being shifted from a designated rate.

For example, in the first embodiment of the present invention, the resistance of the lead part22ais not considered. However, the resistance of the lead part22amay be included in the numerical formula 2 in a case where the resistance of the lead part22ahas a value which cannot be disregarded compared to the parasitic resistances of the metal wirings34and35and the resistances of the bonding wires40athrough40d.

In addition, in the second embodiment of the present invention, two bonding wires are connected to each of the lead parts22aand20b. The number of the electrode pads and the bonding wires may be changed if necessary such that three bonding wires are connected to the lead part22aand four bonding wires are connected to the lead part22b.

Furthermore, in the second embodiment of the present invention, when the semiconductor device10A is mounted on the wiring board or the like, the lead parts22aand20bare short-circuited by the wiring pattern of the wiring board or the like. However, there is no limitation to the lead parts22aand20b. Three or more lead parts may be short-circuited.

In addition, in the first embodiment and the second embodiment of the present invention, the semiconductor device including the current mirror circuit using a P channel FET is discussed. However, the present invention is not limited to this type of the semiconductor device. For example, the present invention can be applied to a semiconductor device including a current mirror circuit using an N channel FET. In addition, for example, the present invention can be applied to a semiconductor device including a current mirror circuit using an NPN type bipolar transistor or a PNP type bipolar transistor.