Print element substrate, printhead, and printing apparatus

This invention provides a print element substrate having a plurality of printing elements. The print element substrate includes a detection circuit configured to detect substrate information of the print element substrate, a shift register configured to serially input print signals for performing driving control of the printing elements, serial-parallel convert the print signals, and parallelly output the print signals, a latch circuit configured to latch the print signals parallelly output from the shift register, and a driving circuit configured to drive the plurality of printing elements based on the print signals latched by the latch circuit. Detection signals based on the substrate information are parallelly input from the detection circuit to the shift register until serial input of next print signals starts after parallelly outputting the print signals from the shift register to the latch circuit.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a print element substrate, printhead, and printing apparatus.

2. Description of the Related Art

There is known a printing apparatus which employs an inkjet printing system. The printing apparatus of this system generally includes a printhead in which a plurality of printing elements are arrayed. The printing apparatus prints an image by scanning the printhead with respect to a printing medium.

Japanese Patent Laid-Open No. 2001-080060 discloses a method of inputting serial data for driving a printing element in a printhead, and serially outputting digital information such as temperature data and head characteristic information.

In this method, the printhead includes an input shift register for inputting serial data for driving a printing element, and an output shift register for digitalizing temperature data in the printhead and serially outputting it.

However, in Japanese Patent Laid-Open No. 2001-080060, two shift registers, that is, an input shift register and output shift register need to be arranged on the same substrate, increasing the circuit scale and substrate size.

In the semiconductor manufacturing process, the substrate size needs to be decreased to increase the number of substrates obtained from a single wafer and reduce the cost. Hence, the increase in substrate size raises the cost.

Recently, printheads (substrates) are increasing the number of printing elements and becoming long for higher resolutions and higher speeds. Achieving high-quality printing requires driving control of printing elements in accordance with the temperature distribution within the substrate. Accordingly, temperature detection at a plurality of portions within the substrate becomes necessary.

When a plurality of temperature detection circuits are arranged in the substrate, wiring lines for outputting detection information also become long along with the elongation of the substrate, increasing the wiring area inside the substrate. This also leads to a large substrate size.

The present invention has been made to solve the above problems, and has as its object to provide a technique for suppressing the circuit scale of a print element substrate for outputting substrate information, and implementing shrinkage of the substrate size.

SUMMARY OF THE INVENTION

For example, a print element substrate, printhead, and printing apparatus according to this invention are capable of providing a technique for suppressing the circuit scale of a print element substrate for outputting substrate information, and implementing shrinkage of the substrate size.

According to one aspect of the present invention, there is provided a print element substrate including a plurality of printing elements, comprising: a detection circuit configured to detect substrate information of the print element substrate; a shift register configured to serially input print signals for performing driving control of the printing elements, serial-parallel convert the print signals, and parallelly output the print signals; a latch circuit configured to latch the print signals parallelly output from the shift register; and a driving circuit configured to drive the plurality of printing elements based on the print signals latched by the latch circuit, wherein detection signals based on the substrate information are parallelly input from the detection circuit to the shift register until serial input of next print signals starts after parallelly outputting the print signals from the shift register to the latch circuit.

According to one aspect of the present invention, there is provided a print element substrate comprising: a printing element; a driving unit configured to drive the printing element based on print data; an obtain unit configured to obtain information of the print element substrate; a transfer unit, including a holding area for holding data, configured to serially receive the print data from outside the print element substrate while serially transmitting information held in the holding area to outside the print element substrate, and store the received print data in the holding area; a latch unit configured to latch the print data held in the holding area; and a storing unit configured to write the information obtained by the obtain unit in the holding area before performing next transmission by the transfer unit after the latch unit latches the print data.

DESCRIPTION OF THE EMBODIMENTS

An exemplary embodiment of the present invention will now be described in detail according to the accompanying drawings. In the following description, a printing apparatus using an inkjet printing system will be exemplified. The printing apparatus may be, for example, a single-function printer having only a printing function, or a multi-function printer having a plurality of functions such as a printing function, FAX function, and scanning function. The printing apparatus may be a manufacturing apparatus for manufacturing, by a predetermined printing method, a color filter, electric device, optical device, micro structure, and the like.

Furthermore, the term “ink” (to be also referred to as a “liquid” hereinafter) should be extensively interpreted similar to the definition of “print” described above. That is, “ink” includes a liquid which, when applied onto a print medium, can form images, figures, patterns, and the like, can process the print medium, and can process ink. The process of ink includes, for example, solidifying or insolubilizing a coloring agent contained in ink applied to the print medium.

Further, the term “printing element” (to be also referred to as a “nozzle”) generically means an ink orifice or a fluid channel communicating with it, and an element which generates energy used to discharge ink, unless otherwise specified.

FIG. 1is a perspective view showing an inkjet printing apparatus (to be referred to as a printing apparatus hereinafter)1according to an embodiment of the present invention.

In the printing apparatus1, an inkjet printhead (to be referred to as a printhead hereinafter)3for discharging ink according to an inkjet method to print is mounted on a carriage2. The carriage2reciprocates in directions (scanning directions) indicated by an arrow A to print. The printing apparatus1feeds a printing medium P via a sheet supply mechanism5, and conveys it to a printing position. At the printing position, the printhead3discharges ink onto the printing medium P, thereby printing.

In addition to the printhead3, for example, ink cartridges6are mounted on the carriage2of the printing apparatus1. Each ink cartridge6stores ink to be supplied to the printhead3. The ink cartridge6is detachable from the carriage2.

The printing apparatus1shown inFIG. 1is capable of color printing. For this purpose, four ink cartridges which contain, for example, magenta (M), cyan (C), yellow (Y), and black (K) inks are mounted on the carriage2. These four ink cartridges are independently detachable.

A print element substrate (to be also simply referred to as a substrate hereinafter)3is arranged on the printhead3. A plurality of nozzle arrays are arranged on the substrate. The printhead3adopts, for example, an inkjet method of discharging ink using thermal energy. The printhead3includes printing elements each formed from a heat generation element (so-called heater) and the like, and a control circuit for performing heater driving control. The heaters are arranged in correspondence with respective nozzles (orifices), and a pulse voltage is applied to a corresponding heater in accordance with a print signal. In the embodiment, discharge of ink using the heat generation element will be explained as an ink discharging type, but the present invention is not limited to this. The present invention may employ various inkjet types such as a type using a piezoelectric element, a type using an electro-static element, and a type using a MEMS element.

A recovery apparatus is arranged outside the reciprocal motion range of the carriage2(outside the printing area) to cancel a discharge failure by the printhead3. The position where the recovery apparatus is arranged is called a home position or the like. While no printing operation is performed, the printhead3stands still at this position.

The arrangement of the printing apparatus1has been exemplified. Note that the arrangement of the printing apparatus1shown inFIG. 1is merely an example, and the printing apparatus1is not limited to this arrangement. For example, in the arrangement ofFIG. 1, the printing medium P is conveyed with respect to the printhead3. However, this arrangement is arbitrary as long as the printhead3and printing medium P move relatively. For example, the printhead3may move with respect to the printing medium P.

FIG. 2is a block diagram exemplifying the functional arrangement of the printing apparatus1shown inFIG. 1.

The printing apparatus1is connected to a host apparatus40. The host apparatus40is implemented as a computer (or an image reader, digital camera, or the like) serving as an image data supply source. The host apparatus40and printing apparatus1exchange image data, commands, and the like via an interface (to be referred to as an I/F hereinafter)11.

A controller20is a so-called control circuit, and includes a CPU (Central Processing Unit)21, ROM (Read Only Memory)22, RAM (Random Access Memory)23, image processing unit24, and printhead control unit25.

The CPU21comprehensively controls processing in the controller20. The ROM22stores programs and various data. The RAM23is used as a work area and temporarily stores various calculation results and the like when the CPU21executes a program.

The image processing unit24performs various image processes for image data received from the host apparatus40via the I/F11.

The printhead control unit25controls the printhead3. The printhead control unit25includes a signal generation unit26. The signal generation unit26generates various signals and transfers the generated signals to the printhead3. The signals transferred to the printhead3are, for example, a serial clock (CLK signal), serial data (DATA signal), latch signal (LT signal), and heat-enable signal (HE signal).

The printhead3discharges ink from each orifice in the printhead3based on a signal transferred from the printhead control unit25. The printhead3includes a print element substrate50on which a plurality of printing elements are arranged, details of which will be described later. The print element substrate50transfers substrate information (for example, temperature data) as a detection signal to the printhead control unit25.

FIG. 3is a block diagram exemplifying the arrangement of the print element substrate50shown inFIG. 2. The print element substrate50includes a plurality of printing elements102. By driving the printing elements based on print data, an image is printed on a printing medium.

The print element substrate50includes the printing elements102, latch circuits105, shift registers106, gate circuits107, a detection circuit108, and a driving circuit109. Note that the driving circuit109includes driving elements103and printing element selection circuits104.

The driving elements (for example, MOS transistors)103and printing element selection circuits104are arranged in correspondence with the respective printing elements102. Each driving element103drives a corresponding printing element based on a driving signal from the printing element selection circuit104, thereby discharging ink from a corresponding nozzle. The printing element selection circuit104receives the heat-enable signal (HE signal), and a print signal (serial data: DATA signal) (from the latch circuit105). The printing element selection circuit104outputs a driving signal to the driving element103based on the logical product of these signals.

A serial data input terminal DATAin, clock input terminal CLK, and serial data output terminal DATAoutare arranged for the shift registers106. The shift registers106serially receive print signals (serial data) in synchronism with the CLK signal, serial-parallel convert them, and output the print signals to the latch circuits105.

An LT signal input terminal LT for inputting the LT signal is arranged for the latch circuits105. The latch circuits105parallelly receive print signals (parallel data) from the shift registers106in synchronism with the LT signal from the terminal LT. The print signals (parallel data) output from the latch circuits105are input to the printing element selection circuits104. Each printing element selection circuit104is connected to a corresponding driving element103, and the driving element103is connected to a corresponding printing element102.

The detection circuit108digitalizes substrate information (for example, temperature data) in the print element substrate50, and outputs it as a detection signal. The output terminal of the detection circuit108is connected to the input terminal of the gate circuit107.

When an output from a gate terminal Gate (for inputting the LT signal) becomes valid, the gate circuit107outputs an output from an output terminal OUT1or OUT2, and the output is set at each bit of the shift register106.

FIG. 4Ais a circuit diagram exemplifying the circuit arrangement of the print element substrate50shown inFIG. 2.FIG. 4Ashows the arrangement of n printing elements and n outputs of the detection circuit. The same reference numerals as those inFIG. 3denote the same parts.

The printing elements102, driving elements103, and printing element selection circuits104are serially connected, and the printing elements102and driving elements103are interposed between power supply lines201. The control terminal (gate) of each driving element103is connected to the printing element selection circuit104, and the input terminal of the printing element selection circuit104is connected to the output terminal of the latch circuit105.

The input terminal of the latch circuit105is connected to the output terminal of the 1-bit shift register106. The shift register106is connected to the output of the gate circuit107. The input of the gate circuit107is connected to the output terminal of the detection circuit108.

The gate circuit107is implemented by, for example, an arrangement shown inFIG. 4B. The gate circuit107receives, at the input terminal IN, a detection signal (substrate information) from the detection circuit108, and outputs an output based on the detection signal from either the output terminal OUT1or OUT2to the shift register106in response to input of the LT signal to the gate terminal Gate.

The operation of the circuit shown in FIG.4A will be explained with reference toFIGS. 5A and 5B.

FIG. 5Ashows the timings of all signals input to the print element substrate50. HE represents the waveform of the HE signal (from the HE signal input terminal) for driving a printing element. The printing element is driven during the “H (High)” period. LT, CLK, DATAin, and DATAoutrepresent the waveforms of signals input from corresponding terminals inFIGS. 1 and 2. In the embodiment, n-bit printing elements are driven.

FIG. 5Bshows the enlarged time ranges of the CLK signal, DATAinsignal, and DATAoutsignal shown inFIG. 5A.

When driving n-bit printing elements by one data transfer, the DATAinsignal is formed from n data for driving n-bit printing elements. The shift registers106sequentially receive print signals from the DATAinterminal at transition (leading edge) timings of the CLK signal. In this case, the shift registers106receive print signals D1to Dn in synchronism with leading edges of the CLK signal. Detection signals S1to Sn input to the shift registers106are sequentially output in synchronism with trailing edges of the CLK signal.

An outline of input and output of the print signal and detection signal will be explained with reference toFIG. 6.

During the print signal serial transfer period, print signals are sequentially input to the shift registers106in synchronism with timings of the CLK signal. At this time, the print signals are sequentially shift and input to the shift registers106of adjacent bits in synchronism with the CLK signal. After inputting n leading edges of the CLK signal, data transfer to the n-bit shift registers106is completed.

Upon completion of transferring the print signals to the shift registers106, the print signals are parallelly output to the latch circuits105at trailing edge timing of the LT signal, and latched by the latch circuits105(latch period). Upon completion of transfer to the latch circuits105, outputs (detection signals) from the detection circuit108are set at the respective bits of the shift registers106.

This operation will be described in detail. A detection signal from the detection circuit108is first input to the gate circuit107. Output of the detection signal input to the gate circuit107is controlled in accordance with input of a signal from the gate terminal of the gate circuit107. In the embodiment, an output from the detection circuit108to the gate circuit107becomes valid in synchronism with the trailing edge of the LT signal.

Each bit of the shift register106includes an S (Set) terminal and R (Reset) terminal (see FIG.4A). When “H (High)” is input to the S terminal, data of the shift register106is set to “H”. When “H” is input to the R terminal, data of the shift register106is set to “L (Low)”.

When “H” is input to the gate terminal of the gate circuit107, “H” is output from either OUT1or OUT2as an output from the gate circuit107, and input to the shift register106via the S or R terminal. In this manner, detection signals parallelly sent from the detection circuit108are set at the respective bits of the shift registers106. That is, temperature data from the detection circuit108are set in the shift registers106.

The number of output bits of the detection circuit108is also n, which is equal to the number of (simultaneously) driven printing elements. Letting S1to Sn be the output bits of the detection circuit108, the detection signals S1to Sn are set at the respective bits of the shift registers106in accordance with trailing edge timings of the LT signal.

As shown inFIG. 6, CLK neither rises nor falls during the period (latch period) of parallel transfer from the shift registers106to the latch circuits105, and the period (detection data store period) during which detection signals are stored. During these periods, no serial transfer occurs in the shift registers106. After outputs from the detection circuit108are set in the shift registers106, a leading edge of the CLK signal is input to the clock input terminal CLK of the shift registers106. In response to this, serial transfer (parallel-serial conversion) of the detection signals by the shift registers106starts.

When n leading edges of the CLK signal are input to the shift registers106, the detection signals S1to Sn are serially output in turn from the DATAoutterminal serving as the output terminal of the shift registers106(to the outside (the controller20)). At the same time, print signals are serially input in turn from the DATAinterminal serving as the input terminal of the shift registers106.

By repeating this operation, output of the bits S1to Sn serving as substrate information and input of driving data D1to Dn for the printing elements102can be continuously performed.

A supplementary explanation ofFIG. 6will be given with reference toFIG. 9.FIG. 9shows a state in which data transfer of 8 bits S1to S8from the gate circuits107to the shift registers106and data transfer of 8 bits D1to D8from the shift registers106to the latch circuits105are performed continuously. The shift registers106transfer data D1to D8to the latch circuits105in synchronism with the leading edge of the LT signal at timing t1. The gate circuits107transfer data S1to S8to the shift registers106in synchronism with the trailing edge of the LT signal at timing t2. Data D1to D8are input bit by bit to the shift registers till timing t1. Data S1to S8are output from the shift registers106, and data D1to D8are input to the shift registers106in the period between timing t2and timing t3.

After the timing when print signals (printing element driving data) serially input to the shift registers106are output to the latch circuits105, detection signals from the detection circuit108are parallelly input to the shift registers106. In the shift register106, the print signal and detection signal do not interfere with each other, and these signals can be interchanged and stored.

As described above, according to the first embodiment, input of a print signal and output of substrate information are performed using a common shift register. The first embodiment can therefore suppress the circuit scale of the print element substrate and implement shrinkage of the substrate size.

According to the first embodiment, the timing to parallelly output, to the latch circuits, print signals serially input to the shift registers, and the timing to parallelly input detection signals from the detection circuit to the shift registers are adjusted based on only the latch signal. Compared to controlling these timings using dedicated signals, the numbers of signal wiring lines and input terminals can be decreased, implementing shrinkage of the substrate size and reduction of the substrate cost.

Further, the input and output timings of the shift register are controlled by one signal. Compared to controlling these timings using two signals, the timing margin for preventing interference between input and output in the shift register can be decreased. As a result, the time taken for transfer can be shortened, increasing the data transfer rate.

FIG. 10shows the first modification of the print element substrate50according to the first embodiment. As shown inFIG. 10, a print element substrate101as the first modification of the print element substrate50includes two types of detection circuits108A and108B, a selector111, and a determination unit110. As described with reference toFIG. 9, each of the detection circuits108A and108B outputs data S1to S8of 8 bits. For example, S1is output from each of the detection circuits108A and108B, and the selector111inFIG. 10receives the 2-bit signal S1. This also applies to S2to S8. The detection circuits108A and108B are, for example, temperature detection circuits.

The selector111receives signals output from the two types of detection circuits108A and108B, and selects a signal to be output to the shift register106from these signals based on a signal generated by the determination unit110. The determination unit110receives data D1from the latch circuit105and generates, based on the value of data D1, a signal for controlling the selector111. For example, if the D1value is 0, the determination unit110outputs a signal to select the detection circuit108A by the selector111. If the D1value is 1, the determination unit110outputs a signal to select the detection circuit108B by the selector111.

FIG. 11shows the second modification of the print element substrate50according to the first embodiment. As shown inFIG. 11, the print element substrate101as the second modification of the print element substrate50includes the detection circuit108, a memory circuit112, the selector111, and the determination unit110. The detection circuit108is, for example, a temperature detection circuit, and outputs data S1to S8of 8 bits, as described with reference toFIG. 9. The memory circuit112holds characteristic data of the print element substrate101.

The selector111receives signals output from the detection circuit108and memory circuit112, and selects a signal to be output to the shift register106from these signals based on a signal generated by the determination unit110. The selector111in FIG.11is identical to the selector111inFIG. 10. Based on the value of data D1output from the latch circuit105, the determination unit110generates a signal for controlling the selector. For example, if the D1value is 0, the determination unit110outputs a signal to select the detection circuit108by the selector111. If the D1value is 1, the determination unit110outputs a signal to select the memory circuit112by the selector111.

The second embodiment will be explained. The circuit arrangement of a print element substrate50according to the second embodiment will be exemplified with reference toFIG. 7.

The second embodiment will explain a case in which m×n printing elements are time-divisionally driven for every m printing elements at n timings. More specifically, m×n printing elements are divided into M groups each formed from n printing elements (groups each containing a predetermined number of printing elements). The time of one sequence is divided at n timings not to simultaneously drive two or more heaters in each group. It is controlled to simultaneously drive m printing elements in accordance with an m-bit print signal within each divided time.

Each printing element102is serially connected to a driving element103, and its driving is controlled based on an input from the gate terminal of the driving element103. The gate terminal of the driving element103receives the output of the logical product of three signals. More specifically, an output from the HE terminal, an output from a decoder110, and an output from a latch circuit105are input. The HE terminal is commonly connected to printing element selection circuits104. The HE signal input to the HE terminal controls the driving timing of the printing element102. The printing element102is driven if an input from another logical product input terminal becomes “H” during the “H” period of the HE signal.

n output signal lines extending from the decoder110are connected to the inputs of the n printing element selection circuits104in each group. To select one printing element102in each group, one of output signals from the output lines extending from the decoder110becomes valid. An output signal from the latch circuit105is commonly supplied to the printing element selection circuits104in each group to select the group.

Note that the interconnections of the latch circuit105, a shift register106, a gate circuit107, and a detection circuit108and the operations of the respective circuits are the same as those in the first embodiment, and a description thereof will not be repeated. The input of the decoder110is connected to the latch circuit105. A signal from the shift register106is output to the decoder110at the “H” timing of the LT signal.

The decoder110validates (“H”) one output from it based on a print signal from the latch circuit105. One wiring line out of n decoder output wiring lines becomes “H”. That is, the basic arrangement in the second embodiment is the same as that in the first embodiment except that the decoder110and the arrangements of the latch circuit105and shift register106connected to it are added to the arrangement in the first embodiment.

FIG. 8is a view exemplifying the layout of the print element substrate50shown inFIG. 7. A print element substrate which adopts a method of heating a printing element (heater) to bubble ink supplied onto the upper surface of the heater, and discharging the ink from a nozzle (not shown) arranged on the upper surface of the substrate will be explained.

An ink supply port704is formed at the center of the substrate50. The ink supply port704is provided to supply ink from the lower surface of the substrate (the reverse of the paper surface) to the upper surface of the substrate (the obverse of the paper surface). The ink is then supplied to each printing element102. The circuit arrangements shown inFIG. 7are symmetrically arranged on the two sides of the ink supply port704.

The printing elements, that is, heaters102are arrayed in line along the ink supply port704. The driving elements103and printing element selection circuits104are arranged in correspondence with the respective heaters102. n heaters102, n driving elements103, and n printing element selection circuits104form one group. The 1-bit shift register106and latch circuit105are arranged for each group. Output wiring lines extending from the decoder110are arranged commonly to the respective groups in the longitudinal direction of the substrate. The detection circuit108and gate circuit107are also arranged in correspondence with each group.

In the layout arrangement shown inFIG. 8, the gate circuit107and detection circuit108are arranged adjacently to the shift register106. Hence, a wiring line which mutually connects the detection circuit108and gate circuit107, and a wiring line which mutually connects the gate circuit107and shift register106can be shortened.

This arrangement can efficiently decrease the area occupied by wiring lines, compared to an arrangement in which detection signals from the detection circuit108are output to wiring lines individually extending to inputs and outputs. Since the line length can be decreased, delays caused by the parasitic resistance and parasitic capacitance of the wiring line can be decreased. Delays from the detection circuit108and gate circuit107can be decreased, increasing the data transfer rate.

For example, in the above-described embodiments, print signals are parallelly output from the shift registers106to the latch circuit105at the leading edge timing of the latch signal, and detection signals are parallelly input to the shift registers at the trailing edge timing of the latch signal. However, the present invention is not limited to this. It suffices to perform these control operations in synchronism with timings when the signal value of the latch signal transits (to the first value and second value). These timings are arbitrarily the leading and trailing edge timings of the latch signal.

Further, the above-described embodiments use the latch signal as a signal which defines these timings, but the present invention is not limited to this. A new signal may be set to perform the above-described processing based on this signal though the number of wiring lines increases.

This application claims the benefit of Japanese Patent Application No. 2012-027722, filed Feb. 10, 2012, which is hereby incorporated by reference herein in its entirety.