Circuit board, semiconductor device, and electronic device

Provided is a circuit board comprising a first conductor periodically arranged with a first periodic width in a first region, a second conductor periodically arranged with a second periodic width in the first region, a third conductor periodically arranged with a third periodic width in a second region, and a fourth conductor periodically arranged with a fourth periodic width in the second region. The first periodic width and the second periodic width, and the third periodic width and the fourth periodic width are in a rational number relationship, the first periodic width and the fourth periodic width are same or substantially same, the first region and the second region have a conductor structure mirror-symmetrical or substantially mirror-symmetrical in a first direction. A first power supply is connected to the first conductor and the third conductor and a second power supply is connected to the second conductor and the fourth conductor.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a U.S. National Phase of International Patent Application No. PCT/JP2020/000381 filed on Jan. 9, 2020, which claims priority benefit of Japanese Patent Application No. JP 2019-008271 filed in the Japan Patent Office on Jan. 22, 2019. Each of the above-referenced applications is hereby incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present technology relates to a circuit board, a semiconductor device, and an electronic device, and more particularly to a circuit board, a semiconductor device, and an electronic device for enabling effective suppression of generation of noise in a signal.

BACKGROUND ART

In a solid-state imaging device represented by a complementary metal oxide semiconductor (CMOS) image sensor, noise may occur in a pixel signal generated by each pixel due to an internal configuration of the solid-state imaging device.

For example, some active elements such as transistors and diodes existing inside a solid-state imaging device generate fine hot carrier light emission. In a case where the hot carrier light emission leaks into a photoelectric conversion unit formed in a pixel, noise occurs in the pixel signal.

As a method of suppressing the noise caused by hot carrier light emission generated from an active element, a technique of providing a light-shielding structure to wiring formed between the active element and a photoelectric conversion unit is known (for example, see Patent Document 1).

Furthermore, for example, noise (inductive noise) may be generated in the pixel signal due to induced electromotive force caused by a magnetic field generated due to the internal configuration of the solid-state imaging device. Specifically, a conductor loop is formed on a pixel array, the conductor loop being formed using a control line for transmitting a control signal for selecting a pixel to read the pixel signal, and a signal line for transmitting the pixel signal read from the selected pixel, when reading the pixel signal from a certain pixel.

In addition, when wiring exists near the conductor loop formed using the control line and the signal line, a magnetic flux passing through the conductor loop may be generated due to a change in current flowing through the wiring, the induced electromotive force may be generated in the conductor loop, accordingly, and the inductive noise may be generated in the pixel signal. Hereinafter, the conductor loop in which a magnetic flux is generated due to a change in current flowing through nearby wiring and the induced electromotive force is generated by the magnetic flux is referred to as Victim conductor loop.

As a method of suppressing inductive noise inside an electronic device, there is a method of canceling a generated magnetic flux by arranging wiring that generates the magnetic flux inside the electronic device as two-layer reticulated wiring (for example, see Patent Document 2).

CITATION LIST

Patent Document

SUMMARY OF THE INVENTION

Problems to be Solved by the Invention

However, the invention described in Patent Document 2 can suppress the inductive noise but having not considered shielding the hot carrier light emission.

The present technology has been made in view of the foregoing, and enables effective suppression of generation of noise in a signal.

Solutions to Problems

A circuit board according to the first aspect of the present technology includes a first conductor periodically arranged with a first periodic width in a first region, a second conductor periodically arranged with a second periodic width in the first region, a third conductor periodically arranged with a third periodic width in a second region different from the first region, and a fourth conductor periodically arranged with a fourth periodic width in the second region, in which the first periodic width and the second periodic width are in a rational number relationship, the third periodic width and the fourth periodic width are in a rational number relationship, the first periodic width and the fourth periodic width are same or substantially same, the first region and the second region have a conductor structure mirror-symmetrical or substantially mirror-symmetrical in a first direction, and a first power supply connected to the first conductor and the third conductor and a second power supply connected to the second conductor and the fourth conductor are power supplies having different voltage values.

A semiconductor device according to the second aspect of the present technology includes a circuit board including: a first conductor periodically arranged with a first periodic width in a first region; a second conductor periodically arranged with a second periodic width in the first region; a third conductor periodically arranged with a third periodic width in a second region different from the first region; and a fourth conductor periodically arranged with a fourth periodic width in the second region, in which the first periodic width and the second periodic width are in a rational number relationship, the third periodic width and the fourth periodic width are in a rational number relationship, the first periodic width and the fourth periodic width are same or substantially same, the first region and the second region have a conductor structure mirror-symmetrical or substantially mirror-symmetrical in a first direction, and a first power supply connected to the first conductor and the third conductor and a second power supply connected to the second conductor and the fourth conductor are power supplies having different voltage values.

An electronic device according to the third aspect of the present technology includes a semiconductor device including a circuit board including: a first conductor periodically arranged with a first periodic width in a first region; a second conductor periodically arranged with a second periodic width in the first region; a third conductor periodically arranged with a third periodic width in a second region different from the first region; and a fourth conductor periodically arranged with a fourth periodic width in the second region, in which the first periodic width and the second periodic width are in a rational number relationship, the third periodic width and the fourth periodic width are in a rational number relationship, the first periodic width and the fourth periodic width are same or substantially same, the first region and the second region have a conductor structure mirror-symmetrical or substantially mirror-symmetrical in a first direction, and a first power supply connected to the first conductor and the third conductor and a second power supply connected to the second conductor and the fourth conductor are power supplies having different voltage values.

In the first to third aspects of the present technology, a first conductor periodically arranged with a first periodic width in a first region, a second conductor periodically arranged with a second periodic width in the first region, a third conductor periodically arranged with a third periodic width in a second region different from the first region, and a fourth conductor periodically arranged with a fourth periodic width in the second region are provided, the first periodic width and the second periodic width are in a rational number relationship, the third periodic width and the fourth periodic width are in a rational number relationship, the first periodic width and the fourth periodic width are same or substantially same, the first region and the second region have a conductor structure mirror-symmetrical or substantially mirror-symmetrical in a first direction, and a first power supply connected to the first conductor and the third conductor and a second power supply connected to the second conductor and the fourth conductor are configured to be power supplies having different voltage values.

The circuit board, the semiconductor device, and the electronic device may be independent devices or may be modules incorporated in other devices.

MODE FOR CARRYING OUT THE INVENTION

Hereinafter, best modes for implementing the present technology (hereinafter referred to as embodiments) will be described in detail with reference to the drawings. Note that the description will be given in the following order.1. Victim Conductor Loop and Magnetic Flux2. Configuration Example of Solid-State Imaging Device (Semiconductor Device) as Embodiment of Present Technology3. Light-shielding Structure for Hot Carrier Light Emission4. Configuration Example of Conductor Layers A and B5. Arrangement Example of Electrodes in Semiconductor Substrate in which Conductor Layers A and B are Formed6. Modification of Configuration Example of Conductor Layers A and B7. Modification of Reticulated Conductor8. Various Effects9. Configuration Example with Different Drawing Portion10. Connection Configuration Example with Pads11. Arrangement Example of Conductive Shield12. Configuration Example of Case Having Three Conductor Layers13. Application14. Shift Configuration Example of Reticulated Conductor15. Configuration Examples of Three-power Supply16. Other Configuration Examples of Case Having Three Conductor Layers17. Configuration Example of Imaging Device18. Application to In-vivo Information Acquisition System19. Application to Endoscopic Surgical System20. Application to Moving Bodies

1. Victim Conductor Loop and Magnetic Flux

For example, in a case where a circuit in which a Victim conductor loop is formed is present near power wiring in a solid-state imaging device (semiconductor device) such as a CMOS image sensor, when a magnetic flux passing through a loop plane of the Victim conductor loop changes, induced electromotive force generated in the Victim conductor loop changes, and noise is sometimes generated in a pixel signal. Note that it is sufficient that the Victim conductor loop includes a conductor at least in part. Furthermore, the Victim conductor loop may be entirely formed using a conductor.

Here, the Victim conductor loop (first conductor loop) refers to a conductor loop on a side affected by a change in magnetic field intensity generated nearby. Meanwhile, a conductor loop on a side that is present near the Victim conductor loop, causes a change in the magnetic field intensity by a change in a flowing current, and affects the Victim conductor loop is referred to as Aggressor conductor loop (second conductor loop).

FIG.1is a diagram for describing a change in induced electromotive force due to a change in the Victim conductor loop. For example, a solid-state imaging device such as a CMOS image sensor illustrated inFIG.1is configured by stacking a pixel board10and a logic board20in that order from the top. In the solid-state imaging device inFIG.1, at least a part of a Victim conductor loop11(11A or11B) is formed in a pixel region of the pixel board10, and power wiring21for supplying a (digital) power supply is formed in a region of the logic board20stacked with the pixel board10, the region being near the Victim conductor loop11.

Then, a magnetic flux due to the power wiring21passes through a loop plane of the Victim conductor loop11on the pixel board10, thereby induced electromotive force is generated in the Victim conductor loop11.

Note that induced electromotive force Vemf generated in the Victim conductor loop11can be calculated by the following equations (1) and (2). Note that Φ represents the magnetic flux, H represents the magnetic field intensity, μ represents magnetic permeability, and S represents the area of the Victim conductor loop11.

A loop path of the Victim conductor loop11formed in the pixel region of the pixel board10changes depending on a position of a pixel selected as a pixel to be read from which a pixel signal is read. In the case of the example inFIG.1, the loop path of the Victim conductor loop11A formed when a pixel A is selected is different from the loop path of the Victim conductor loop11B formed when a pixel B at a different position from the pixel A is selected. In other words, the effective shape of the conductor loop changes depending on the position of the selected pixel.

When the loop path of the Victim conductor loop11changes in this way, the magnetic flux passing through the loop plane of the Victim conductor loop changes, thereby the induced electromotive force generated in the Victim conductor loop sometimes significantly changes. Furthermore, noise (inductive noise) sometimes occurs in the pixel signal read from the pixel due to the change in the induced electromotive force. Then, striped image noise is sometimes generated in a captured image due to the inductive noise. That is, the image quality of the captured image is sometimes reduced.

Therefore, the present disclosure proposes a technique of suppressing generation of the inductive noise in the induced electromotive force in the Victim conductor loop.

2. Configuration Example of Solid-State Imaging Device (Semiconductor Device) as Embodiment of Present Technology

FIG.2is a block diagram illustrating a main configuration example of a solid-state imaging device that is an embodiment of the present technology.

A solid-state imaging device100illustrated inFIG.2is a device that photoelectrically converts light from an object and outputs the photoelectrically converted light as image data. For example, the solid-state imaging device100is configured as a back-illuminated CMOS image sensor using a CMOS, or the like.

As illustrated inFIG.2, the solid-state imaging device100is configured by stacking a first semiconductor substrate101and a second semiconductor substrate102.

A pixel/analog processing unit111including pixels, an analog circuit, and the like is formed on the first semiconductor substrate101. A digital processing unit112including a digital circuit and the like is formed on the second semiconductor substrate102.

The first semiconductor substrate101and the second semiconductor substrate102are superposed in an insulated state from each other. That is, the configuration of the pixel/analog processing unit111and the configuration of the second semiconductor substrate102are basically insulated from each other. Note that although not illustrated, the configuration formed in the pixel/analog processing unit111and the configuration formed in the digital processing unit112are electrically connected with each other as needed (in necessary parts) via, for example, a conductor via (VIA), a through silicon via (TSV), similar metal bonding such as Cu—Cu bonding, Au—Au bonding, or Al—Al bonding, dissimilar metal bonding such as Cu—Au bonding, Cu—Al bonding, or Au—Al bonding, a bonding wire, or the like.

Note that, inFIG.2, the solid-state imaging device100including stacked two-layer substrates has been described as an example. However, the number of stacked substrates constituting the solid-state imaging device100is arbitrary. For example, the solid-state imaging device100may have a single substrate or three or more layers of substrates. Hereinafter, the case where the solid-state imaging device100is configured using two layers of substrates as in the example inFIG.2will be described.

FIG.3is a block diagram illustrating an example of main configuration elements of a pixel/analog processing unit111.

As illustrated inFIG.3, a pixel array121, an A/D conversion unit122, a vertical scanning unit123, and the like are formed in the pixel/analog processing unit111.

In the pixel array121, a plurality of pixels131(FIG.4) each having a photoelectric conversion element such as a photodiode is vertically and horizontally arranged.

The A/D conversion unit122performs A/D conversion for an analog signal or the like read from each pixel131of the pixel array121, and outputs a resultant digital pixel signal.

The vertical scanning unit123controls operation of a transistor (a transfer transistor142or the like inFIG.5) of each pixel131of the pixel array121. That is, a charge accumulated in each pixel131of the pixel array121is controlled and read by the vertical scanning unit123, is supplied as a pixel signal to the A/D conversion unit122via a signal line132(FIG.4) for each column of a unit pixel, and is A/D converted.

The A/D conversion unit122supplies an A/D conversion result (digital pixel signal) to a logic circuit (not illustrated) formed in the digital processing unit112for each column of the pixel131.

FIG.4is a diagram illustrating a detailed configuration example of the pixel array121. Pixels131-11to131-MN are formed in the pixel array121(M and N are arbitrary natural numbers). That is, in the pixel array121, the pixels131of M rows and N columns are arranged in a matrix (array). Hereinafter, the pixels131-11to131-MN are simply referred to as pixel(s)131in a case where there is no need to individually distinguish the pixels131-11to131-MN.

Signal lines132-1to132-N and control lines133-1to133-M are formed on the pixel array121. Hereinafter, the signal lines132-1to132-N are simply referred to as signal line(s)132in a case where there is no need to individually distinguish the signal lines132-1to132-N, and the control lines133-1to133-M are simply referred to as control line(s)133in a case where there is no need to individually distinguish the control lines133-1to133-M.

For each column, the signal line132corresponding to the column is connected to the pixels131. Furthermore, for each row, the control line133corresponding to the row is connected to the pixels131. A control signal from the vertical scanning unit123is transmitted to the pixel131via the control line133.

The analog pixel signal is output from the pixel131to the A/D conversion unit122via the signal line132.

Next,FIG.5is a circuit diagram illustrating a configuration example of the pixel131. The pixel131includes a photodiode141as a photoelectric conversion element, a transfer transistor142, a reset transistor143, an amplification transistor144, and a select transistor145.

The photodiode141photoelectrically converts received light into a photocharge (photoelectrons here) having a charge amount corresponding to a light amount of the received light and accumulates the photocharge. An anode electrode of the photodiode141is connected to GND, and a cathode electrode is connected to floating diffusion (FD) via the transfer transistor142. Of course, the cathode electrode of the photodiode141may be connected to a power supply, the anode electrode may be connected to the floating diffusion via the transfer transistor142, and the photocharge may be read as an optical hole.

The transfer transistor142controls readout of the photocharge from the photodiode141. A drain electrode of the transfer transistor142is connected to the floating diffusion, and a source electrode of the transfer transistor142is connected to the cathode electrode of the photodiode141. Furthermore, a transfer control line for transmitting a transfer control signal TRG supplied from the vertical scanning unit123(FIG.3) is connected to a gate electrode of the transfer transistor142. When the transfer control signal TRG (that is, a gate potential of the transfer transistor142) is in an OFF state, the photocharge is not transferred from the photodiode141(the photocharge is accumulated in the photodiode141). When the transfer control signal TRG (that is, the gate potential of the transfer transistor142) is in an ON state, the photocharge accumulated in the photodiode141is transferred to the floating diffusion.

The reset transistor143resets the potential of the floating diffusion. A drain electrode of the reset transistor143is connected to a power supply potential, and a source electrode of the reset transistor143is connected to the floating diffusion. Furthermore, a reset control line for transmitting a reset control signal RST supplied from the vertical scanning unit123is connected to a gate electrode of the reset transistor143. When the reset control signal RST (that is, a gate potential of the reset transistor143) is in the OFF state, the floating diffusion is disconnected from the power supply potential. When the reset control signal RST (that is, the gate potential of the reset transistor143) is in the ON state, the charge of the floating diffusion is discharged to the power supply potential, and the floating diffusion is reset.

The amplification transistor144outputs an electrical signal (analog signal) corresponding to a voltage of the floating diffusion (causes a current to flow). A gate electrode of the amplification transistor144is connected to the floating diffusion, a drain electrode of the amplification transistor144is connected to a (source-follower) power supply voltage, and a source electrode of the amplification transistor144is connected to a drain electrode of the select transistor145. For example, the amplification transistor144outputs a reset signal (reset level) as an electrical signal according to the voltage of the floating diffusion reset by the reset transistor143to the select transistor145as a pixel signal. Furthermore, the amplification transistor144outputs an optical storage signal (signal level) as an electrical signal according to the voltage of the floating diffusion to which the photocharge has been transferred by the transfer transistor142to the select transistor145as a pixel signal.

The select transistor145controls output of the electrical signal supplied from the amplification transistor144to the signal line (VSL)132(that is, the A/D conversion unit122). The drain electrode of the select transistor145is connected to the source electrode of the amplification transistor144and a source electrode of the select transistor145is connected to the signal line132Furthermore, a select control line for transmitting a select control signal SEL supplied from the vertical scanning unit123is connected to the gate electrode of the select transistor145. When the select control signal SEL (that is, a gate potential of the select transistor145) is in the OFF state, the amplification transistor144and the signal line132are electrically disconnected. Therefore, in this state, the reset signal or the optical storage signal as the pixel signal is not output from the pixel131. When the select control signal SEL (that is, the gate potential of the select transistor145) is in the ON state, the pixel131becomes selected. That is, the amplification transistor144and the signal line132are electrically connected, and the reset signal or the optical storage signal as the pixel signal output from the amplification transistor144is supplied to the A/D conversion unit122via the signal line132. That is, the reset signal or the optical storage signal as the pixel signal is read from the pixel131.

Note that the configuration of the pixel131is arbitrary and is not limited to the example inFIG.5.

In the pixel/analog processing unit111configured as described above, when the pixel131is selected as the target for reading the analog signal as the pixel signal, the control line133for controlling the above-described various transistors, the signal line132, the power wiring (analog power wiring and digital power wiring), and the like form various Victim conductor loops (conductors having a loop shape (annular shape). When the magnetic flux generated from nearby wiring or the like passes through the loop plane of the Victim conductor loop, induced electromotive force is generated.

It is sufficient that the Victim conductor loop includes at least one of the control line133or the signal line132. Furthermore, the Victim conductor loop including a part of the control lines133and the Victim conductor loop including a part of the signal lines132may be present as Victim conductor loops independent of each other. Moreover, a part or the whole of the Victim conductor loop may be included in the second semiconductor substrate102. Moreover, the loop path of the Victim conductor loop may be variable or fixed.

Wiring directions of the control lines133and the signal lines132forming the Victim conductor loop are desirably substantially orthogonal to each other, but may be substantially parallel to each other.

Note that a conductor loop existing near another conductor loop can be the Victim conductor loop. For example, a conductor loop that is not affected even when a change in magnetic field intensity occurs due to a change in a current flowing through a nearby aggressor loop can be the Victim conductor loop.

In the Victim conductor loop, when a high-frequency signal flows through the wiring (Aggressor conductor loop) existing nearby and the magnetic field intensity around the Aggressor conductor loop changes, the induced electromotive force is generated in the Victim conductor loop due to the influence of the change, and noise is sometimes generated in the Victim conductor loop. In particular, in a case where wirings in which the currents flow in the same direction are concentrated near the Victim conductor loop, the change in magnetic field intensity becomes large, and the induced electromotive force (that is, noise) generated in the Victim conductor loop also becomes large.

Therefore, in the present disclosure, the direction of the magnetic flux generated from the loop plane of the Aggressor conductor loop is adjusted so that the magnetic field does not pass through the Aggressor conductor loop.

3. Light-Shielding Structure for Hot Carrier Light Emission

FIG.6is a diagram illustrating an example of a cross-sectional structure of the solid-state imaging device100.

As described above, the solid-state imaging device100is configured by stacking the first semiconductor substrate101and the second semiconductor substrate102.

In the first semiconductor substrate101, for example, a pixel array in which a plurality of pixel units is two-dimensionally arrayed, is formed, each pixel units including the photodiode141serving as a photoelectric conversion unit, and the plurality of pixel transistors (the transfer transistor142to the select transistor145inFIG.5).

The photodiode141has, for example, an n-type semiconductor region and a p-type semiconductor region on a front surface side (lower side in the figure) of the substrate in a well region formed in a semiconductor substrate152. The plurality of pixel transistors (the transfer transistor142to the select transistor145inFIG.5) is formed on the semiconductor substrate152.

A multilayer wiring layer153in which wiring of a plurality of layers is arranged via an interlayer insulating film is formed on the front surface side of the semiconductor substrate152. The wiring is formed using, for example, copper wiring. Wirings in different wiring layers of the pixel transistors, the vertical scanning unit123, and the like are connected to one another at required points by a connecting conductor penetrating the wiring layers. For example, an anti-reflection film, a light-shielding film that blocks a predetermined region, and an optical member155such as a color filter and a microlens provided at positions corresponding to each photodiode141are formed on a back surface (upper side in the figure) of the semiconductor substrate152.

Meanwhile, a logic circuit as the digital processing unit112(FIG.2) is formed in the second semiconductor substrate102. The logic circuit includes, for example, a plurality of MOS transistors164formed in a p-type semiconductor well region of a semiconductor substrate162.

Moreover, a multilayer wiring layer163including a plurality of wiring layers in each of which wiring is arranged via an interlayer insulating film is formed on the semiconductor substrate162.FIG.6illustrates two wiring layers (wiring layers165A and165B) of the plurality of wiring layers forming the multilayer wiring layer163.

In the solid-state imaging device100, a light-shielding structure151is formed by the wiring layer165A and the wiring layer165B.

Here, in the second semiconductor substrate102, a region in which active elements such as the MOS transistors164are formed is referred to as an active element group167. In the second semiconductor substrate102, a circuit for implementing one function by combining active elements such as a plurality of nMOS transistors and pMOS transistors is configured, for example. Then, the region where the active element group167is formed is defined as a circuit block (corresponding to circuit blocks202to204inFIG.7). Note that, as the active element formed on the second semiconductor substrate102, a diode or the like may be present in addition to the MOS transistors164.

Then, in the multilayer wiring layer163of the second semiconductor substrate102, the light-shielding structure151including the wiring layer165A and the wiring layer165B is present between the active element group167and the photodiode141, so that the light-shielding structure151suppresses leakage of hot carrier light emission generated from the active element group167into the photodiode141(details will be described below).

Hereinafter, the wiring layer165A closer to the first semiconductor substrate101on which the photodiode141and the like are formed, between the wiring layer165A and the wiring layer165B forming the light-shielding structure151, will be referred to as a conductor layer A (first conductor layer). Furthermore, the wiring layer165B closer to the active element group167will be referred to as a conductor layer B (second conductor layer).

However, the wiring layer165A closer to the first semiconductor substrate101on which the photodiode141and the like are formed may be referred to as the conductor layer B, and the wiring layer165B closer to the active element group167may be referred to as the conductor layer A. Moreover, any one of an insulating layer, a semiconductor layer, another conductor layer, or the like may be provided between the conductor layers A and B. Furthermore, any one of an insulating layer, a semiconductor layer, another conductor layer, or the like may be provided between layers other than the conductor layers A and B.

The conductor layer A and the conductor layer B are desirably, but are not limited to, the conductor layers in which the current most easily flows among circuit boards, semiconductor substrates, and electronic devices.

One of the conductor layer A or the conductor layer B is desirably, but is not limited to, the conductor layer in which the current most easily flows among circuit boards, semiconductor substrates, and electronic devices, and the other is desirably, but are not limited to, the conductor layer in which the current second-most easily flows among circuit boards, semiconductor substrates, and electronic devices.

One of the conductor layer A or the conductor layer B is desirably, but is not limited to, not a conductor layer in which the current most uneasily flows among circuit boards, semiconductor substrates, and electronic devices. Both of the conductor layer A and the conductor layer B are desirably, but are not limited to, not the conductor layers in which the current most uneasily flows among circuit boards, semiconductor substrates, and electronic devices.

For example, one of the conductor layer A or the conductor layer B may be the conductor layer in which the current most easily flows in the first semiconductor substrate101and the other may be the conductor layer in which the current second-most easily flows in the first semiconductor substrate101.

For example, one of the conductor layer A or the conductor layer B may be the conductor layer in which the current most easily flows in the second semiconductor substrate102and the other may be the conductor layer in which the current second-most easily flows in the second semiconductor substrate102.

For example, one of the conductor layer A or the conductor layer B may be the conductor layer in which the current most easily flows in the first semiconductor substrate101and the other may be the conductor layer in which the current most easily flows in the second semiconductor substrate102.

For example, one of the conductor layer A or the conductor layer B may be the conductor layer in which the current most easily flows in the first semiconductor substrate101and the other may be the conductor layer in which the current second-most easily flows in the second semiconductor substrate102.

For example, one of the conductor layer A or the conductor layer B may be the conductor layer in which the current second-most easily flows in the first semiconductor substrate101and the other may be the conductor layer in which the current most easily flows in the second semiconductor substrate102.

For example, one of the conductor layer A or the conductor layer B may be the conductor layer in which the current second-most easily flows in the first semiconductor substrate101and the other may be the conductor layer in which the current second-most easily flows in the second semiconductor substrate102.

For example, one of the conductor layer A or the conductor layer B may not be the conductor layer in which the current most uneasily flows in the first semiconductor substrate101or the second semiconductor substrate102.

For example, both of the conductor layer A and the conductor layer B may not be the conductor layers in which the current most uneasily flows in the first semiconductor substrate101or the second semiconductor substrate102.

Note that the above-described first can be replaced as third, fourth, or Nth (N is a positive number), and the above-described second can also be replaced as third, fourth, or Nth (N is a positive number).

Note that the above-described conductor layer in which the current easily flows among circuit boards, semiconductor substrates, and electronic devices may be considered to be any of a conductor layer in which the current easily flows among the circuit boards, a conductor layer in which the current easily flows among the semiconductor substrates, or a conductor layer in which the current easily flows among the electronic devices. Note that the above-described conductor layer in which the current less easily flows among circuit boards, semiconductor substrates, and electronic devices may be considered to be any of a conductor layer in which the current less easily flows among the circuit boards, a conductor layer in which the current less easily flows among the semiconductor substrates, or a conductor layer in which the current less easily flows among the electronic devices. Furthermore, even if the conductor layer in which the current easily flows is a conductor layer having a low sheet resistance, and the conductor layer in which the current less easily flows is a conductor layer having a high sheet resistance, thereby can be replaced with each other.

Note that, as the conductor material used for the conductor layers A and B, a metal such as copper, aluminum, tungsten, chromium, nickel, tantalum, molybdenum, titanium, gold, silver, or iron, or a mixture, a compound, or an alloy containing at least one of the aforementioned metals, is mainly used. Furthermore, a semiconductor such as silicon, germanium, a compound semiconductor, or an organic semiconductor may be included. Moreover, an insulator such as cotton, paper, polyethylene, polyvinyl chloride, natural rubber, polyester, epoxy resin, melamine resin, phenol resin, polyurethane, synthetic resin, mica, asbestos, glass fiber, or porcelain may be included.

The conductor layers A and B forming the light-shielding structure151can form an Aggressor conductor loop by a current flowing through the conductor layers A and B.

Next, a region shielded by the light-shielding structure151(light-shielding target region) will be described.

FIG.7is schematic configuration diagrams illustrating plan arrangement examples of circuit blocks including the regions in which the active element groups167are formed in the semiconductor substrate162.

A inFIG.7illustrates an example of a case in which the plurality of circuit blocks202to204is collectively the light-shielding target region by the light-shielding structure151, and a region205including all the circuit blocks202,203, and204serves as the light-shielding target region.

B inFIG.7illustrates an example of a case in which the plurality of circuit blocks202to204is individually the light-shielding target region by the light-shielding structure151. Regions206,207, and208respectively including the circuit blocks202,203, and204individually serve as the light-shielding target regions, and a region209other than the regions206to208serves as a non-light-shielding target region.

In the case of the example illustrated in B inFIG.7, restriction on the degree of freedom in layout of the conductor layers A and B forming the light-shielding structure151can be avoided. However, since the layout of the conductor layers A and B becomes complicated, a great deal of labor is required to design the layout of the conductor layers A and B.

To easily design the layout of the conductor layers A and B forming the light-shielding structure151, it is desirable to adopt the example illustrated in A inFIG.7and collectively set the plurality of circuit blocks as the light-shielding target region.

Therefore, the present disclosure proposes structures of the conductor layers A and B for which the layout can be easily designed while avoiding the restriction on the degree of freedom in layout of the conductor layers A and B.

Note that the light-shielding target region in the present embodiment is provided with a buffer region to serve as a light-shielding target region around the circuit block, in addition to the circuit block representing the region of the active element group167that is a light-emission source of the hot carrier light emission. By providing a buffer region around the circuit block, the hot carrier light emission obliquely emitted from the circuit block can be prevented from leaking into the photodiode141.

FIG.8is a diagram illustrating an example of a positional relationship between the light-shielding target region by the light-shielding structure151, and the region of the active element group and the buffer region.

In the example illustrated inFIG.8, the region in which the active element group167is formed and a buffer region191around the active element group167are a light-shielding target region194, and the light-shielding structure151is formed to face the light-shielding target region194.

Here, the length from the active element group167to the light-shielding structure151is defined as an interlayer distance192. Furthermore, the length from an end of the active element group167to an end of the light-shielding structure151by wiring is defined as a buffer region width193.

The light-shielding structure151is formed so that the buffer region width193is larger than the interlayer distance192. Thereby, oblique components of the hot carrier light emission generated as a point light source can be shielded.

Note that an appropriate value of the buffer region width193changes depending on the interlayer distance192between the light-shielding structure151and the active element group167. For example, in a case where the interlayer distance192is long, the buffer region191needs to be provided in a large manner in order to sufficiently shield the oblique components of the hot carrier light emission from the active element group167. Meanwhile, in a case where the interlayer distance192is short, the hot carrier light emission from the active element group167can be sufficiently shielded even if the buffer region191is not largely provided. Therefore, by forming the light-shielding structure151using the wiring layer close to the active element group167among the plurality of wiring layers constituting the multilayer wiring layer163, the degree of freedom in layout of the conductor layers A and B can be improved. However, it is often difficult to form the light-shielding structure151using the wiring layer close to the active element group167due to layout restrictions of the wiring layer close to the active element group167, for example. In the present technology, a high degree of freedom in layout can be obtained even in a case where the light-shielding structure151is formed using a wiring layer far from the active element group167.

4. Configuration Example of Conductor Layers A and B

Hereinafter, configuration examples of the conductor layer A (wiring layer165A) and the conductor layer B (wiring layer165B) forming the light-shielding structure151, which can be the Aggressor conductor loop in the solid-state imaging device100to which the present technology is applied, will be described. First, a comparative example to be compared with the configuration examples will be described.

First Comparative Example

FIG.9is plan views illustrating a first comparative example of the conductor layers A and B forming the light-shielding structure151, for comparison with a plurality of configuration examples to be described below. Note that A inFIG.9illustrates the conductor layer A, and B inFIG.9illustrates the conductor layer B. In a coordinate system inFIG.9, a horizontal direction is an X axis, a vertical direction is a Y axis, and a direction perpendicular to an XY plane is a Z axis.

In the conductor layer A in the first comparative example, a linear conductor211long in a Y direction is periodically arranged in an X direction with a conductor period FXA. Note that the conductor period FXA=a conductor width WXA in the X direction+a gap width GXA in the X direction. Each linear conductor211is, for example, wiring (Vss wiring) connected to GND or a negative power supply.

In the conductor layer B in the first comparative example, a linear conductor212long in the Y direction is periodically arranged in the X direction with a conductor period FXB. Note that the conductor period FXB=a conductor width WXB in the X direction+a gap width GXB in the X direction. Each linear conductor212is, for example, wiring (Vdd wiring) connected to a positive power supply. Here, the conductor period FXB=the conductor period FXA.

Note that connection destinations of the conductor layers A and B may be exchanged so that each linear conductor211serves as the Vdd wiring and each linear conductor212serves as the Vss wiring.

C inFIG.9illustrates a state of the conductor layers A and B respectively illustrated in A and B inFIG.9, which are viewed from the photodiode141side (back surface side). In the case of the first comparative example, in a case where the linear conductors211constituting the conductor layer A and the linear conductors212constituting the conductor layer B are arranged in an overlapping manner as illustrated in C inFIG.9, the linear conductors211and212are formed to cause overlapping portions where the conductor portions overlap with each other. Therefore, the hot carrier light emission from the active element group167can be sufficiently shielded. Note that the width of the overlapping portion is also referred to as an overlap width.

FIG.10is a diagram illustrating a current condition of a current flowing in the first comparative example (FIG.9).

It is assumed that an AC current evenly flows in ends of the linear conductor211constituting the conductor layer A and the linear conductor212constituting the conductor layer B. However, a current direction changes with time. For example, when the current flows through the linear conductor212that is the Vdd wiring from the upper side to the lower side of the drawing, the current flows through the linear conductor211that is the Vss wiring from the lower side to the upper side of the drawing.

In the first comparative example, in the case where the current flows as illustrated inFIG.10, a magnetic flux in a substantially Z direction is likely to be generated between the linear conductor211as the Vss wiring and the linear conductor212as the Vdd wiring by a conductor loop having a loop plane substantially parallel to an XY plane, the conductor loop being generated including the adjacent linear conductors211and212in the plan view inFIG.10.

Meanwhile, the Victim conductor loop formed using the signal line132and the control line133is formed in the XY plane, as illustrated inFIG.10, in the pixel array121of the first semiconductor substrate101stacked on the second semiconductor substrate102in which the light-shielding structure151formed using the conductor layers A and B is formed. In the Victim conductor loop formed on the XY plane, the induced electromotive force is likely to be generated by the magnetic flux in the Z direction, and an image output from the solid-state imaging device100further deteriorates (the inductive noise increases) as a change in the induced electromotive force is larger.

Moreover, since the induced electromotive force is proportional to dimensions of the Victim conductor loop depending on the configuration of the Aggressor conductor loop, when the effective dimensions of the Victim conductor loop formed using the signal line132and the control line133are changed due to movement of selected pixels in the pixel array121, the change in the induced electromotive force becomes remarkable.

In the case of the first comparative example, since the direction (substantially Z direction) of the magnetic flux generated from the loop plane of the Aggressor conductor loop of the light-shielding structure151formed using the conductor layers A and B and the direction (Z direction) of the magnetic flux that is likely to generate the induced electromotive force in the Victim conductor loop substantially match, deterioration (generation of inductive noise) of an image output from the solid-state imaging device100is expected.

FIG.11illustrates a simulation result of the inductive noise generated in the case where the first comparative example is applied to the solid-state imaging device100.

A inFIG.11illustrates an image in which the inductive noise is generated, the image being output from the solid-state imaging device100. B inFIG.11illustrates a change in a pixel signal in the line segment X1-X2of the image illustrated in A inFIG.11. C inFIG.11illustrates the solid line L1representing the induced electromotive force that generates the inductive noise in the image. The horizontal axis in C inFIG.11represents X-axis coordinates of the image, and the vertical axis represents the magnitude of the induced electromotive force.

Hereinafter, the solid line L1illustrated in C inFIG.11will be used for comparison with the simulation result of the inductive noise generated in a case where the configuration examples of the conductor layers A and B forming the light-shielding structure151are applied to the solid-state imaging device100.

First Configuration Example

FIG.12illustrates a first configuration example of the conductor layers A and B. Note that A inFIG.12illustrates the conductor layer A, and B inFIG.12illustrates the conductor layer B. In the coordinate system inFIG.12, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

The conductor layer A in the first configuration example is configured by a planar conductor213. The planar conductor213is, for example, wiring (Vss wiring) connected to the GND or the negative power supply.

The conductor layer B in the first comparative example is configured by a planar conductor214. The planar conductor214is, for example, wiring (Vdd wiring) connected to the positive power supply.

Note that the connection destinations of the conductor layers A and B may be exchanged so that the planar conductor213serves as the Vdd wiring and the planar conductor214serves as the Vss wiring. The same applies to each configuration example to be described below.

C inFIG.12illustrates a state of the conductor layers A and B respectively illustrated in A and B inFIG.12, which are viewed from the photodiode141side (back surface side). Note that a hatched region215in C inFIG.12where diagonal lines intersect represents a region where the planar conductor213of the conductor layer A and the planar conductor214of the conductor layer B overlap. Therefore, the case of C inFIG.12illustrates that the entire planar conductor213of the conductor layer A and the entire planar conductor214of the conductor layer B overlap. In the case of the first configuration example, the entire planar conductor213of the conductor layer A and the entire planar conductor214of the conductor layer B overlap. Therefore, the hot carrier light emission from the active element group167can be reliably shielded.

FIG.13is a diagram illustrating the current condition of the current flowing in the first configuration example (FIG.12).

It is assumed that AC current evenly flows in ends of the planar conductor213constituting the conductor layer A and the planar conductor214constituting the conductor layer B. However, the current direction changes with time. For example, when the current flows through the planar conductor214that is the Vdd wiring from the upper side to the lower side of the drawing, the current flows through the planar conductor213that is the Vss wiring from the lower side to the upper side of the drawing.

In the first configuration example, in a case where the current flows as illustrated inFIG.13, magnetic fluxes in a substantially X direction and a substantially Y direction are likely to be generated between the planar conductor213that is the Vss wiring and the planar conductor214that is the Vdd wiring by a conductor loop with a loop plane approximately perpendicular to the X axis and a conductor loop with a loop plane approximately perpendicular to the Y axis, the conductor loops being generated including (cross sections of) the planar conductors213and214in a cross section where the planar conductors213and214are arranged.

Meanwhile, the Victim conductor loop formed using the signal line132and the control line133is formed in the XY plane, as illustrated inFIG.13, in the pixel array121of the first semiconductor substrate101stacked on the second semiconductor substrate102in which the light-shielding structure151formed using the conductor layers A and B is formed. In the Victim conductor loop formed on the XY plane, the induced electromotive force is likely to be generated by the magnetic flux in the Z-axis direction, and an image output from the solid-state imaging device100further deteriorates (the inductive noise increases) as a change in the induced electromotive force is larger.

Moreover, when the effective dimensions of the Victim conductor loop formed using the signal line132and the control line133are changed due to movement of selected pixels in the pixel array121, the change in the induced electromotive force becomes remarkable.

In the case of the first configuration example, the direction (approximately X direction or approximately Y direction) of the magnetic flux generated from the loop plane of the Aggressor conductor loop of the light-shielding structure151formed using the conductor layers A and B and the direction (Z direction) of the magnetic flux to generate the induced electromotive force in the Victim conductor loop are substantially orthogonal and differ by approximately 90 degrees. In other words, the direction of the loop plane where the magnetic flux is generated from the Aggressor conductor loop and the direction of the loop plane where the induced electromotive force is generated in the Victim conductor loop differ by approximately 90 degrees. Therefore, it is expected that the deterioration (generation of inductive noise) of the image output from the solid-state imaging device100is less than that in the case of the first comparative example.

FIG.14illustrates a simulation result of the inductive noise generated in the case where the first configuration example (FIG.12) is applied to the solid-state imaging device100.

A inFIG.14illustrates an image in which the inductive noise can be generated, the image being output from the solid-state imaging device100. B inFIG.14illustrates a change in a pixel signal in the line segment X1-X2of the image illustrated in A inFIG.14. C inFIG.14illustrates the solid line L11representing induced electromotive force that generates the inductive noise in the image. The horizontal axis of C inFIG.14represents X-axis coordinates of the image, and the vertical axis represents the magnitude of the induced electromotive force. Note that the dotted line L1in C inFIG.14corresponds to the first comparative example (FIG.9).

As is clear from the comparison between the solid line L11and the dotted line L1illustrated in C inFIG.14, the first configuration example can suppress a change in the induced electromotive force to be generated in the Victim conductor loop as compared with the first comparative example. Therefore, generation of the inductive noise in the image output from the solid-state imaging device100can be suppressed.

Second Configuration Example

FIG.15illustrates a second configuration example of the conductor layers A and B. Note that A inFIG.15illustrates the conductor layer A, and B inFIG.15illustrates the conductor layer B. In the coordinate system inFIG.15, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

The conductor layer A in the second configuration example is configured by a reticulated conductor216. The conductor width in the X direction of the reticulated conductor216is WXA, the gap width is GXA, the conductor period is FXA (=the conductor width WXA+the gap width GXA), and an end width is EXA (=the conductor width WXA/2). Furthermore, the conductor width in the Y direction of the reticulated conductor216is WYA, the gap width is GYA, the conductor period is FYA (=the conductor width WYA+the gap width GYA), and the end width is EYA (=the conductor width WYA/2). The reticulated conductor216is, for example, wiring (Vss wiring) connected to the GND or the negative power supply.

The conductor layer B in the second configuration example is configured by a reticulated conductor217. The conductor width in the X direction of the reticulated conductor217is WXB, the gap width is GXB, the conductor period is FXB (=the conductor width WXB+the gap width GXB), and the end width is EXB (=the conductor width WXB/2). Furthermore, the conductor width in the Y direction of the reticulated conductor217is WYB, the gap width is GYB, the conductor period is FYB (=the conductor width WYB+the gap width GYB), and the end width is EYB (=the conductor width WYB/2). The reticulated conductor217is, for example, wiring (Vdd wiring) connected to the positive power supply.

Note that the reticulated conductor216and the reticulated conductor217desirably satisfy the following relationship.
The conductor widthWXA=the conductor widthWYA=the conductor widthWXB=the conductor widthWYB
The gap widthGXA=the gap widthGYA=the gap widthGXB=the gap widthGYB
The end widthEXA=the end widthEYA=the end widthEXB=the end widthEYB
The conductor periodFXA=the conductor periodFYA=the conductor periodFXB=the conductor periodFYB

C inFIG.15illustrates a state of the conductor layers A and B respectively illustrated in A and B inFIG.15, which are viewed from the photodiode141side (back surface side). Note that a hatched region218in C inFIG.15where diagonal lines intersect represents a region where the reticulated conductor216of the conductor layer A and the reticulated conductor217of the conductor layer B overlap. In the case of the second configuration example, since the gaps of the reticulated conductor216forming the conductor layer A and the gaps of the reticulated conductor217forming the conductor layer B match, the hot carrier light emission from the active element group167cannot be sufficiently shielded. However, as will be described below, generation of the inductive noise can be suppressed.

FIG.16is a diagram illustrating the current condition of the current flowing in the second configuration example (FIG.15).

It is assumed that AC current evenly flows in ends of the reticulated conductor216constituting the conductor layer A and the reticulated conductor217constituting the conductor layer B. However, the current direction changes with time. For example, when the current flows through the reticulated conductor217that is the Vdd wiring from the upper side to the lower side of the drawing, the current flows through the reticulated conductor216that is the Vss wiring from the lower side to the upper side of the drawing.

In the second configuration example, in a case where the current flows as illustrated inFIG.16, the magnetic fluxes in the substantially X direction and the substantially Y direction are likely to be generated between the reticulated conductor216that is the Vss wiring and the reticulated conductor217that is the Vdd wiring by the conductor loop with the loop plane approximately perpendicular to the X axis and the conductor loop with the loop plane approximately perpendicular to the Y axis, the conductor loops being generated including (cross sections of) the reticulated conductors216and217in a cross section where the reticulated conductors216and217are arranged.

Meanwhile, the Victim conductor loop formed using the signal line132and the control line133is formed in the XY plane, as illustrated inFIG.16, in the pixel array121of the first semiconductor substrate101stacked on the second semiconductor substrate102in which the light-shielding structure151formed using the conductor layers A and B is formed. In the Victim conductor loop formed on the XY plane, the induced electromotive force is likely to be generated by the magnetic flux in the Z direction, and an image output from the solid-state imaging device100further deteriorates (the inductive noise increases) as a change in the induced electromotive force is larger.

Moreover, when the effective dimensions of the Victim conductor loop formed using the signal line132and the control line133are changed due to movement of selected pixels in the pixel array121, the change in the induced electromotive force becomes remarkable.

In the case of the second configuration example, the direction (approximately X direction or approximately Y direction) of the magnetic flux generated from the loop plane of the Aggressor conductor loop of the light-shielding structure151formed using the conductor layers A and B and the direction (Z direction) of the magnetic flux to generate the induced electromotive force in the Victim conductor loop are substantially orthogonal and differ by approximately 90 degrees. In other words, the direction of the loop plane where the magnetic flux is generated from the Aggressor conductor loop and the direction of the loop plane where the induced electromotive force is generated in the Victim conductor loop differ by approximately 90 degrees. Therefore, it is expected that the deterioration (generation of inductive noise) of the image output from the solid-state imaging device100is less than that in the first comparative example.

FIG.17illustrates a simulation result of the inductive noise generated in the case where the second configuration example (FIG.15) is applied to the solid-state imaging device100.

A inFIG.17illustrates an image in which the inductive noise can be generated, the image being output from the solid-state imaging device100. B inFIG.17illustrates a change in a pixel signal in the line segment X1-X2of the image illustrated in A inFIG.17. C inFIG.17illustrates the solid line L21representing induced electromotive force that generates the inductive noise in the image. The horizontal axis of C inFIG.17represents X-axis coordinates of the image, and the vertical axis represents the magnitude of the induced electromotive force. Note that the dotted line L1in C inFIG.17corresponds to the first comparative example (FIG.9).

As is clear from the comparison between the solid line L21and the dotted line L1illustrated in C inFIG.17, the second configuration example can suppress a change in the induced electromotive force to be generated in the Victim conductor loop as compared with the first comparative example. Therefore, generation of the inductive noise in the image output from the solid-state imaging device100can be suppressed.

Second Comparative Example

In the second configuration example (FIG.15), as the relationship between the reticulated conductor216forming the conductor layer A and the reticulated conductor217forming the conductor layer B, the conductor period FXA=the conductor period FYA=the conductor period FXB=the conductor period FYB is satisfied.

In this way, when the conductor period FXA in the X direction of the conductor layer A, the conductor period FYA in the Y direction of the conductor layer A, the conductor period FXB in the X direction of the conductor layer B, and the conductor period FYB in the X direction of the conductor layer B are caused to match, generation of the inductive noise can be suppressed.

FIGS.18and19are diagrams for describing that generation of the inductive noise can be suppressed by matching all the conductor periods of the conductor layer A and the conductor layer B.

A inFIG.18illustrates a second comparative example that is a modified second configuration example for comparison with the second configuration example illustrated inFIG.15. In the second comparative example, the gap width GXA in the X direction and the gap width GYA in the Y direction of the reticulated conductor216forming the conductor layer A in the second configuration example are widened, and the conductor period FXA in the X direction and the conductor period FYA in the Y direction are changed by a factor of 5 of the second configuration example. Note that the reticulated conductor217forming the conductor layer B in the second comparative example is the same as that in the second configuration example.

B inFIG.18illustrates the second configuration example illustrated in C inFIG.15by the same magnification as A inFIG.18.

FIG.19illustrates a change in the induced electromotive force that causes the inductive noise in an image, as a simulation result of a case where the second comparative example (A inFIG.18) and the second configuration example (B inFIG.18) are applied to the solid-state imaging device100. Note that the current condition of the current flowing in the second comparative example is similar to that in the case illustrated inFIG.16. The horizontal axis inFIG.19represents X-axis coordinates of the image, and the vertical axis represents the magnitude of the induced electromotive force.

The solid line L21inFIG.19corresponds to the second configuration example, and the dotted line L31corresponds to the second comparative example.

As is clear from the comparison of the solid line L21and the dotted line L31, it can be seen that the second configuration example can suppress the change in the induced electromotive force to be generated in the Victim conductor loop as compared with the second comparative example, and can suppress the inductive noise.

Third Comparative Example

By the way, generation of the inductive noise can also be suppressed even in a case where the conductor width of the reticulated conductor forming the conductor layer A in the second comparative example is expanded.

FIGS.20and21are diagrams for describing that generation of the inductive noise can be suppressed by expanding the conductor width of the reticulated conductor forming the conductor layer A.

A inFIG.20is a re-illustration of the second comparative example illustrated in A inFIG.18.

B inFIG.20illustrates a third comparative example that is a modified second configuration example for comparison with the second comparative example. In the third comparative example, the conductor widths WXA and WYA in the X direction and the Y direction of the reticulated conductor216forming the conductor layer A in the second configuration example are expanded by a factor of 5 of the second configuration example. Note that the reticulated conductor217forming the conductor layer B in the third comparative example is the same as that in the second configuration example.

FIG.21illustrates a change in the induced electromotive force that causes the inductive noise in an image, as a simulation result of a case where the third comparative example and the second comparative example are applied to the solid-state imaging device100. Note that the current condition of the current flowing in the third comparative example is similar to that in the case illustrated inFIG.16. The horizontal axis inFIG.21represents X-axis coordinates of the image, and the vertical axis represents the magnitude of the induced electromotive force.

The solid line L41inFIG.21corresponds to the third comparative example, and the dotted line L31corresponds to the second comparative example.

As is clear from the comparison of the solid line L41and the dotted line L31, it can be seen that the third comparative example can suppress the change in the induced electromotive force to be generated in the Victim conductor loop as compared with the second comparative example, and can suppress the inductive noise.

Third Configuration Example

Next,FIG.22illustrates a third configuration example of the conductor layers A and B. Note that A inFIG.22illustrates the conductor layer A, and B inFIG.22illustrates the conductor layer B. In the coordinate system inFIG.22, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

The conductor layer A in the third configuration example is configured by a planar conductor221. The planar conductor221is, for example, wiring (Vss wiring) connected to the GND or the negative power supply.

The conductor layer B in the third configuration example is configured by a reticulated conductor222. The conductor width in the X direction of the reticulated conductor222is WXB, the gap width is GXB, and the conductor period is FXB (=the conductor width WXB+the gap width GXB). Furthermore, the conductor width in the Y direction of the reticulated conductor222is WYB, the gap width is GYB, the conductor period is FYB (=the conductor width WYB+the gap width GYB), and the end width is EYB. The reticulated conductor222is, for example, wiring (Vdd wiring) connected to the positive power supply.

Note that the reticulated conductor222desirably satisfies the following relationship.
The conductor widthWXB=the conductor widthWYB
The gap widthGXB=the gap widthGYB
The end widthEYB=the conductor widthWYB/2
The conductor periodFXB=the conductor periodFYB

By adjusting the conductor widths, conductor periods, and gap widths in the X direction and the Y direction as described above, wiring resistance and wiring impedance of the reticulated conductor222become uniform in the X direction and the Y direction. Therefore, magnetic field resistance and voltage drop can be made uniform in the X direction and the Y direction.

Furthermore, by setting the end width EYB to ½ of the conductor width WYB, the induced electromotive force generated in the Victim conductor loop by the magnetic field generated around the end of the reticulated conductor222can be suppressed.

C inFIG.22illustrates a state of the conductor layers A and B respectively illustrated in A and B inFIG.22, which are viewed from the photodiode141side (back surface side). Note that a hatched region223where diagonal lines intersect in C inFIG.22represents a region where the planar conductor221of the conductor layer A and the reticulated conductor222of the conductor layer B overlap. In the case of the third configuration example, since the active element group167is covered with at least one of the conductor layer A or the conductor layer B, the hot carrier light emission from the active element group167can be shielded.

FIG.23is a diagram illustrating the current condition of the current flowing in the third configuration example (FIG.22).

It is assumed that AC current evenly flows in ends of the planar conductor221constituting the conductor layer A and the reticulated conductor222constituting the conductor layer B. However, the current direction changes with time. For example, when the current flows through the reticulated conductor222that is the Vdd wiring from the upper side to the lower side of the drawing, the current flows through the planar conductor221that is the Vss wiring from the lower side to the upper side of the drawing.

In the third configuration example, in a case where the current flows as illustrated inFIG.23, the magnetic fluxes in the substantially X direction and the substantially Y direction are likely to be generated between the planar conductor221that is the Vss wiring and the reticulated conductor222that is the Vdd wiring by the conductor loop with the loop plane approximately perpendicular to the X axis and the conductor loop with the loop plane approximately perpendicular to the Y axis, the conductor loops being generated including (cross sections of) the planar conductor221and the reticulated conductor222in a cross section where the planar conductor221and the reticulated conductor222are arranged.

Meanwhile, the Victim conductor loop formed using the signal line132and the control line133is formed in the XY plane in the pixel array121of the first semiconductor substrate101stacked on the second semiconductor substrate102in which the light-shielding structure151formed using the conductor layers A and B is formed. In the Victim conductor loop formed on the XY plane, the induced electromotive force is likely to be generated by the magnetic flux in the Z direction, and an image output from the solid-state imaging device100further deteriorates (the inductive noise increases) as a change in the induced electromotive force is larger.

Moreover, when the effective dimensions of the Victim conductor loop formed using the signal line132and the control line133are changed due to movement of selected pixels in the pixel array121, the change in the induced electromotive force becomes remarkable.

In the case of the third configuration example, the direction (approximately X direction or approximately Y direction) of the magnetic flux generated from the loop plane of the Aggressor conductor loop of the light-shielding structure151formed using the conductor layers A and B and the direction (Z direction) of the magnetic flux to generate the induced electromotive force in the Victim conductor loop are substantially orthogonal and differ by approximately 90 degrees. In other words, the direction of the loop plane where the magnetic flux is generated from the Aggressor conductor loop and the direction of the loop plane where the induced electromotive force is generated in the Victim conductor loop differ by approximately 90 degrees. Therefore, it is expected that the deterioration (generation of inductive noise) of the image output from the solid-state imaging device100is less than that in the first comparative example.

FIG.24illustrates a simulation result of the inductive noise generated in the case where the third configuration example (FIG.22) is applied to the solid-state imaging device100.

A inFIG.24illustrates an image in which the inductive noise can be generated, the image being output from the solid-state imaging device100. B inFIG.24illustrates a change in a pixel signal in the line segment X1-X2of the image illustrated in A inFIG.24. C inFIG.24illustrates the solid line L51representing induced electromotive force that generates the inductive noise in the image. The horizontal axis of C inFIG.24represents X-axis coordinates of the image, and the vertical axis represents the magnitude of the induced electromotive force. Note that the dotted line L1in C inFIG.24corresponds to the first comparative example (FIG.9).

As is clear from the comparison between the solid line L51and the dotted line L1illustrated in C inFIG.24, the third configuration example can suppress a change in the induced electromotive force to be generated in the Victim conductor loop as compared with the first comparative example. Therefore, generation of the inductive noise in the image output from the solid-state imaging device100can be suppressed.

Fourth Configuration Example

Next,FIG.25illustrates a fourth configuration example of the conductor layers A and B. Note that A inFIG.25illustrates the conductor layer A, and B inFIG.25illustrates the conductor layer B. In the coordinate system inFIG.25, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

The conductor layer A in the fourth configuration example is configured by a reticulated conductor231. The conductor width in the X direction of the reticulated conductor231is WXA, the gap width is GXA, the conductor period is FXA (=the conductor width WXA+the gap width GXA), and an end width is EXA (=the conductor width WXA/2). Furthermore, the conductor width in the Y direction of the reticulated conductor231is WYA, the gap width is GYA, and the conductor period is FYA (=the conductor width WYA+the gap width GYA). The reticulated conductor231is, for example, wiring (Vss wiring) connected to the GND or the negative power supply.

The conductor layer B in the fourth configuration example is configured by a reticulated conductor232. The conductor width in the X direction of the reticulated conductor232is WXB, the gap width is GXB, and the conductor period is FXB (=the conductor width WXB+the gap width GXB). Furthermore, the conductor width in the Y direction of the reticulated conductor232is WYB, the gap width is GYB, the conductor period is FYB (=the conductor width WYB+the gap width GYB), and the end width is EYB (=the conductor width WYB/2). The reticulated conductor232is, for example, wiring (Vdd wiring) connected to the positive power supply.

Note that the reticulated conductor231and the reticulated conductor232desirably satisfy the following relationship.
The conductor widthWXA=the conductor widthWYA=the conductor widthWXB=the conductor widthWYB
The gap widthGXA=the gap widthGYA=the gap widthGXB=the gap widthGYB
The end widthEXA=the end widthEYB
The conductor periodFXA=the conductor periodFYA=the conductor periodFXB=the conductor periodFYB
The conductor widthWYA=2×the overlap width+the gap widthGYA, the conductor widthWXA=2×the overlap width+the gap widthGXA
The conductor widthWYB=2×the overlap width+the gap widthGYB, the conductor widthWXB=2×the overlap width+the gap widthGXB

Here, the overlap width is a width of an overlapping portion where the conductor portions overlap in a case where the reticulated conductor231of the conductor layer A and the reticulated conductor232of the conductor layer B are arranged to overlap each other.

As described above, by adjusting all the conductor periods of the reticulated conductor231and the reticulated conductor232in the X direction and the Y direction, a current distribution of the reticulated conductor231and a current distribution of the reticulated conductor232can be made substantially uniform and have opposite characteristics. Therefore, the magnetic field generated by the current distribution of the reticulated conductor231and the magnetic field generated by the current distribution of the reticulated conductor232can be effectively canceled.

Furthermore, by adjusting all the conductor periods, conductor widths, and gap widths of the reticulated conductor231and the reticulated conductor232in the X direction and the Y direction, the wiring resistance and wiring impedance of the reticulated conductor231and the reticulated conductor232become uniform in the X direction and the Y direction. Therefore, magnetic field resistance and voltage drop can be made uniform in the X direction and the Y direction.

Furthermore, by setting the end width EXA of the reticulated conductor231to ½ of the conductor width WXA, the induced electromotive force generated in the Victim conductor loop by the magnetic field generated around the end of the reticulated conductor231can be suppressed. Furthermore, by setting the end width EYB of the reticulated conductor232to ½ of the conductor width WYB, the induced electromotive force generated in the Victim conductor loop by the magnetic field generated around the end of the reticulated conductor231can be suppressed.

Note that instead of providing the end in the X direction of the reticulated conductor231of the conductor layer A, the end in the X direction of the reticulated conductor232of the conductor layer B may be provided. Furthermore, instead of providing the end in the Y direction of the reticulated conductor232of the conductor layer B, the end of the reticulated conductor231of the conductor layer A may be provided in the Y direction.

C inFIG.25illustrates a state of the conductor layers A and B respectively illustrated in A and B inFIG.25, which are viewed from the photodiode141side (back surface side). Note that a hatched region233where diagonal lines intersect in C inFIG.25represents a region where the reticulated conductor231of the conductor layer A and the reticulated conductor232of the conductor layer B overlap. In the case of the fourth configuration example, since the active element group167is covered with at least one of the conductor layer A or the conductor layer B, the hot carrier light emission from the active element group167can be shielded.

Note that to completely shield the hot carrier light emission by the reticulated conductor231of the conductor layer A and the reticulated conductor232of the conductor layer B, the following relationships need to be satisfied.
The conductor widthWYA≥the gap widthGYA
The conductor widthWXA≥the gap widthGXA
The conductor widthWYB≥the gap widthGYB
The conductor widthWXB≥the gap widthGXB

In this case, the following relationships are satisfied.
The conductor widthWYA=2×the overlap width+the gap widthGYA
The conductor widthWXA=2×the overlap width+the gap widthGXA
The conductor widthWYB=2×the overlap width+the gap widthGYB
The conductor widthWXB=2×the overlap width+the gap widthGXB

In the fourth configuration example, in a case where the current flows similarly to the case illustrated inFIG.23, the magnetic fluxes in the substantially X direction and the substantially Y direction are likely to be generated between the reticulated conductor231that is the Vss wiring and the reticulated conductor232that is the Vdd wiring by the conductor loop with the loop plane approximately perpendicular to the X axis and the conductor loop with the loop plane approximately perpendicular to the Y axis, the conductor loops being generated including (cross sections of) the reticulated conductors231and232in a cross section where the reticulated conductors231and232are arranged.

Fifth Configuration Example

Next,FIG.26illustrates a fifth configuration example of the conductor layers A and B. Note that A inFIG.26illustrates the conductor layer A, and B inFIG.26illustrates the conductor layer B. In the coordinate system inFIG.26, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

The conductor layer A in the fifth configuration example is configured by a reticulated conductor241. The reticulated conductor241is obtained by moving the reticulated conductor231forming the conductor layer A in the fourth configuration example (FIG.25) in the Y direction by the conductor period FYA/2. The reticulated conductor241is, for example, wiring (Vss wiring) connected to the GND or the negative power supply.

The conductor layer B in the fifth configuration example is configured by a reticulated conductor242. Since the reticulated conductor242has a similar shape to the reticulated conductor232forming the conductor layer B in the fourth configuration example (FIG.25), the description thereof is omitted. The reticulated conductor242is, for example, wiring (Vdd wiring) connected to the positive power supply.

Note that the reticulated conductor241and the reticulated conductor242desirably satisfy the following relationship.
The conductor widthWXA=the conductor widthWYA=the conductor widthWXB=the conductor widthWYB
The gap widthGXA=the gap widthGYA=the gap widthGXB=the gap widthGYB
The end widthEXA=the end widthEYB
The conductor periodFXA=the conductor periodFYA=the conductor periodFXB=the conductor periodFYB
The conductor widthWYA=2×the overlap width+the gap widthGYA, the conductor widthWXA=2×the overlap width+the gap widthGXA
The conductor widthWYB=2×the overlap width+the gap widthGYB, the conductor widthWXB=2×the overlap width+the gap widthGXB

Here, the overlap width is a width of an overlapping portion where the conductor portions overlap in a case where the reticulated conductor241of the conductor layer A and the reticulated conductor242of the conductor layer B are arranged to overlap each other.

C inFIG.26illustrates a state of the conductor layers A and B respectively illustrated in A and B inFIG.26, which are viewed from the photodiode141side (back surface side). Note that a hatched region243where diagonal lines intersect in C inFIG.26represents a region where the reticulated conductor241of the conductor layer A and the reticulated conductor242of the conductor layer B overlap. In the case of the fifth configuration example, since the active element group167is covered with at least one of the conductor layer A or the conductor layer B, the hot carrier light emission from the active element group167can be shielded.

Furthermore, in the case of the fifth configuration example, the region243where the reticulated conductor241and the reticulated conductor242overlap is continuous in the X direction. In the region243where the reticulated conductor241and the reticulated conductor242overlap, currents having polarities different from each other flow in the reticulated conductor241and the reticulated conductor242, and thus magnetic fields generated from the region243cancel each other. Therefore, generation of the inductive noise near the region243can be suppressed.

In the fifth configuration example, in a case where the current flows similarly to the case illustrated inFIG.23, the magnetic fluxes in the substantially X direction and the substantially Y direction are likely to be generated between the reticulated conductor241that is the Vss wiring and the reticulated conductor242that is the Vdd wiring by the conductor loop with the loop plane approximately perpendicular to the X axis and the conductor loop with the loop plane approximately perpendicular to the Y axis, the conductor loops being generated including (cross sections of) the reticulated conductors241and242in a cross section where the reticulated conductors241and242are arranged.

Sixth Configuration Example

Next,FIG.27illustrates a sixth configuration example of the conductor layers A and B. Note that A inFIG.27illustrates the conductor layer A, and B inFIG.27illustrates the conductor layer B. In the coordinate system inFIG.27, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

The conductor layer A in the sixth configuration example is configured by a reticulated conductor251. Since the reticulated conductor251has a similar shape to the reticulated conductor231forming the conductor layer A in the fourth configuration example (FIG.25), the description thereof is omitted. The reticulated conductor251is, for example, wiring (Vss wiring) connected to the GND or the negative power supply.

The conductor layer B in the sixth configuration example is configured by a reticulated conductor252. The reticulated conductor252is obtained by moving the reticulated conductor232forming the conductor layer B in the fourth configuration example (FIG.25) in the X direction by the conductor period FXB/2. The reticulated conductor252is, for example, wiring (Vdd wiring) connected to the positive power supply.

Note that the reticulated conductor251and the reticulated conductor252desirably satisfy the following relationship.
The conductor widthWXA=the conductor widthWYA=the conductor widthWXB=the conductor widthWYB
The gap widthGXA=the gap widthGYA=the gap widthGXB=the gap widthGYB
The end widthEXA=the end widthEYB
The conductor periodFXA=the conductor periodFYA=the conductor periodFXB=the conductor periodFYB
The conductor widthWYA=2×the overlap width+the gap widthGYA, the conductor widthWXA=2×the overlap width+the gap widthGXA
The conductor widthWYB=2×the overlap width+the gap widthGYB, the conductor widthWXB=2×the overlap width+the gap widthGXB

Here, the overlap width is a width of an overlapping portion where the conductor portions overlap in a case where the reticulated conductor251of the conductor layer A and the reticulated conductor252of the conductor layer B are arranged to overlap each other.

C inFIG.27illustrates a state of the conductor layers A and B respectively illustrated in A and B inFIG.27, which are viewed from the photodiode141side (back surface side). Note that a hatched region253in C inFIG.27where diagonal lines intersect represents a region where the reticulated conductor251of the conductor layer A and the reticulated conductor252of the conductor layer B overlap. In the case of the sixth configuration example, since the active element group167is covered with at least one of the conductor layer A or the conductor layer B, the hot carrier light emission from the active element group167can be shielded.

In the sixth configuration example, in a case where the current flows similarly to the case illustrated inFIG.23, the magnetic fluxes in the substantially X direction and the substantially Y direction are likely to be generated between the reticulated conductor251that is the Vss wiring and the reticulated conductor252that is the Vdd wiring by the conductor loop with the loop plane approximately perpendicular to the X axis and the conductor loop with the loop plane approximately perpendicular to the Y axis, the conductor loops being generated including (cross sections of) the reticulated conductors251and252in a cross section where the reticulated conductors251and252are arranged.

Moreover, in the case of the sixth configuration example, the region253where the reticulated conductor251and the reticulated conductor252overlap is continuous in the Y direction. In the region253where the reticulated conductor251and the reticulated conductor252overlap, currents having polarities different from each other flow in the reticulated conductor251and the reticulated conductor252, and thus magnetic fields generated from the region253cancel each other. Therefore, generation of the inductive noise near the region253can be suppressed.

Simulation Results of Fourth to Sixth Configuration Examples

FIG.28illustrates changes in the induced electromotive force that causes the inductive noise in an image, as simulation results of cases where the fourth to sixth configuration examples (FIGS.25to27) are applied to the solid-state imaging device100. Note that the current conditions of the currents flowing in the fourth to sixth configuration examples are similar to that in the case illustrated inFIG.23. The horizontal axis inFIG.28represents X-axis coordinates of the image, and the vertical axis represents the magnitude of the induced electromotive force.

The solid line L52in A inFIG.28corresponds to the fourth configuration example (FIG.25), and the dotted line L1corresponds to the first comparative example (FIG.9). As is clear from the comparison of the solid line L52and the dotted line L1, it can be seen that the fourth configuration example can suppress the change in the induced electromotive force to be generated in the Victim conductor loop as compared with the first comparative example, and can suppress the inductive noise.

The solid line L53in B inFIG.28corresponds to the fifth configuration example (FIG.26), and the dotted line L1corresponds to the first comparative example (FIG.9). As is clear from the comparison of the solid line L53and the dotted line L1, it can be seen that the fifth configuration example can suppress the change in the induced electromotive force to be generated in the Victim conductor loop as compared with the first comparative example, and can suppress the inductive noise.

The solid line L54in C inFIG.28corresponds to the sixth configuration example (FIG.27), and the dotted line L1corresponds to the first comparative example (FIG.9). As is clear from the comparison of the solid line L54and the dotted line L1, it can be seen that the sixth configuration example can suppress the change in the induced electromotive force to be generated in the Victim conductor loop as compared with the first comparative example, and can suppress the inductive noise.

Furthermore, as is clear from the comparison of the solid lines L52to L54, it can be seen that the sixth configuration example can further suppress the change in the induced electromotive force to be generated in the Victim conductor loop as compared with the fourth and fifth configuration examples, and can further suppress the inductive noise.

Seventh Configuration Example

Next,FIG.29illustrates a seventh configuration example of the conductor layers A and B. Note that A inFIG.29illustrates the conductor layer A, and B inFIG.29illustrates the conductor layer B. In the coordinate system inFIG.29, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

The conductor layer A in the seventh configuration example is configured by a planar conductor261. The planar conductor261is, for example, wiring (Vss wiring) connected to the GND or the negative power supply.

The conductor layer B in the seventh configuration example is configured by a reticulated conductor262and a relay conductor301. Since the reticulated conductor262has a similar shape to the reticulated conductor222of the conductor layer B in the third configuration example (FIG.22), the description thereof is omitted. The reticulated conductor262is, for example, wiring (Vdd wiring) connected to the positive power supply.

The relay conductor (another conductor)301is arranged in a gap region other than the conductor of the reticulated conductor262and is electrically insulated from the reticulated conductor262, and is connected to Vss to which the planar conductor261of the conductor layer A is connected.

The shape of the relay conductor301is arbitrary, and a symmetric circular or polygonal shape such as rotational symmetry or mirror plane symmetry is desirable. The relay conductor301can be arranged in a center of or at any other position of the gap region of the reticulated conductor262. The relay conductor301may be connected to a conductor layer as Vss wiring different from the conductor layer A. The relay conductor301may be connected to a conductor layer as Vss wiring closer to the active element group167than the conductor layer B. The relay conductor301can be connected to a conductor layer different from the conductor layer A or a conductor layer or the like closer to the active element group167than the conductor layer B via the conductor via (VIA) extending in the Z direction.

C inFIG.29illustrates a state of the conductor layers A and B respectively illustrated in A and B inFIG.29, which are viewed from the photodiode141side (back surface side). Note that a hatched region263in C inFIG.29where diagonal lines intersect represents a region where the planar conductor261of the conductor layer A and the reticulated conductor262of the conductor layer B overlap. In the case of the seventh configuration example, since the active element group167is covered with at least one of the conductor layer A or the conductor layer B, the hot carrier light emission from the active element group167can be shielded.

Furthermore, in the case of the seventh configuration example, by providing the relay conductor301, the planar conductor261as Vss wiring can be connected with the active element group167at substantially the shortest distance or a short distance. By connecting the planar conductor261and the active element group167at substantially the shortest distance or a short distance, the voltage drop, energy loss, or inductive noise between the planar conductor261and the active element group167can be reduced.

FIG.30is a diagram illustrating the current condition of the current flowing in the seventh configuration example (FIG.29).

It is assumed that AC current evenly flows in ends of the planar conductor261constituting the conductor layer A and the reticulated conductor262constituting the conductor layer B. However, the current direction changes with time. For example, when the current flows through the reticulated conductor262that is the Vdd wiring from the upper side to the lower side of the drawing, the current flows through the planar conductor261that is the Vss wiring from the lower side to the upper side of the drawing.

In the seventh configuration example, in a case where the current flows as illustrated inFIG.30, the magnetic fluxes in the substantially X direction and the substantially Y direction are likely to be generated between the planar conductor261that is the Vss wiring and the reticulated conductor262that is the Vdd wiring by the conductor loop with the loop plane approximately perpendicular to the X axis and the conductor loop with the loop plane approximately perpendicular to the Y axis, the conductor loops being generated including (cross sections of) the planar conductor261and the reticulated conductor262in a cross section where the planar conductor261and the reticulated conductor262are arranged.

Meanwhile, the Victim conductor loop formed using the signal line132and the control line133is formed in the XY plane in the pixel array121of the first semiconductor substrate101stacked on the second semiconductor substrate102in which the light-shielding structure151formed using the conductor layers A and B is formed. In the Victim conductor loop formed on the XY plane, the induced electromotive force is likely to be generated by the magnetic flux in the Z direction, and an image output from the solid-state imaging device100further deteriorates (the inductive noise increases) as a change in the induced electromotive force is larger.

Moreover, when the effective dimensions of the Victim conductor loop formed using the signal line132and the control line133are changed due to movement of selected pixels in the pixel array121, the change in the induced electromotive force becomes remarkable.

In the case of the seventh configuration example, the direction (approximately X direction or approximately Y direction) of the magnetic flux generated from the loop plane of the Aggressor conductor loop of the light-shielding structure151formed using the conductor layers A and B and the direction (Z direction) of the magnetic flux to generate the induced electromotive force in the Victim conductor loop are substantially orthogonal and differ by approximately 90 degrees. In other words, the direction of the loop plane where the magnetic flux is generated from the Aggressor conductor loop and the direction of the loop plane where the induced electromotive force is generated in the Victim conductor loop differ by approximately 90 degrees. Therefore, it is expected that the deterioration (generation of inductive noise) of the image output from the solid-state imaging device100is less than that in the first comparative example.

FIG.31illustrates a simulation result of the inductive noise generated in the case where the seventh configuration example (FIG.29) is applied to the solid-state imaging device100.

A inFIG.31illustrates an image in which the inductive noise can be generated, the image being output from the solid-state imaging device100. B inFIG.31illustrates a change in a pixel signal in the line segment X1-X2of the image illustrated in A inFIG.31. C inFIG.31illustrates the solid line L61representing induced electromotive force that generates the inductive noise in the image. The horizontal axis of C inFIG.31represents X-axis coordinates of the image, and the vertical axis represents the magnitude of the induced electromotive force. Note that the dotted line L51in C inFIG.31corresponds to the third configuration example (FIG.22).

As is clear from the comparison between the solid line L61and the dotted line L51illustrated in C inFIG.31, it can be seen that the seventh configuration example does not deteriorate the change in the induced electromotive force to be generated in the Victim conductor loop as compared with the third configuration example. That is, even the seventh configuration example in which the relay conductor301is arranged in the gap of the reticulated conductor262of the conductor layer B can suppress the generation of the inductive noise in the image output from the solid-state imaging device100to the same extent as the third configuration example. Note that this simulation result is a simulation result of a case where the planar conductor261is not connected to the active element group167and the reticulated conductor262is not connected to the active element group167. For example, in a case where at least a part of the planar conductor261and a part of the active element group167are connected via a conductor via or the like at substantially the shortest distance or a short distance, or in a case where at least a part of the reticulated conductor262and a part of the active element group167are connected via a conductor via or the like at substantially the shortest distance or a short distance, the amount of current flowing through the planar conductor261and the reticulated conductor262gradually decreases depending on the position. In such a case, there is also a condition that the voltage drop, energy loss, and inductive noise are significantly improved to less than half by providing the relay conductor301.

Eighth Configuration Example

Next,FIG.32illustrates an eighth configuration example of the conductor layers A and B. Note that A inFIG.32illustrates the conductor layer A, and B inFIG.32illustrates the conductor layer B. In the coordinate system inFIG.32, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

The conductor layer A in the eighth configuration example is configured by a reticulated conductor271. Since the reticulated conductor271has a similar shape to the reticulated conductor231of the conductor layer A in the fourth configuration example (FIG.25), the description thereof is omitted. The reticulated conductor271is, for example, wiring (Vss wiring) connected to the GND or the negative power supply.

The conductor layer B in the eighth configuration example is configured by a reticulated conductor272and a relay conductor302. Since the reticulated conductor272has a similar shape to the reticulated conductor232of the conductor layer B in the fourth configuration example (FIG.25), the description thereof is omitted. The reticulated conductor232is, for example, wiring (Vdd wiring) connected to the positive power supply.

The relay conductor (another conductor)302is arranged in a gap region other than the conductor of the reticulated conductor272and is electrically insulated from the reticulated conductor272, and is connected to Vss to which the reticulated conductor271of the conductor layer A is connected.

Note that the shape of the relay conductor302is arbitrary, and a symmetric circular or polygonal shape such as rotational symmetry or mirror plane symmetry is desirable. The relay conductor302can be arranged in a center of or at any other position of the gap region of the reticulated conductor272. The relay conductor302may be connected to a conductor layer as Vss wiring different from the conductor layer A. The relay conductor302may be connected to a conductor layer as Vss wiring closer to the active element group167than the conductor layer B. The relay conductor302can be connected to a conductor layer different from the conductor layer A or to a conductor layer or the like closer to the active element group167than the conductor layer B via the conductor via (VIA) extending in the Z direction.

C inFIG.32illustrates a state of the conductor layers A and B respectively illustrated in A and B inFIG.32, which are viewed from the photodiode141side (back surface side). Note that a hatched region273where diagonal lines intersect in C inFIG.32represents a region where the reticulated conductor271of the conductor layer A and the reticulated conductor272of the conductor layer B overlap. In the case of the eighth configuration example, since the active element group167is covered with at least one of the conductor layer A or the conductor layer B, the hot carrier light emission from the active element group167can be shielded.

In the eighth configuration example, in a case where the current flows similarly to the case illustrated inFIG.30, the magnetic fluxes in the substantially X direction and the substantially Y direction are likely to be generated between the reticulated conductor271that is the Vss wiring and the reticulated conductor272that is the Vdd wiring by the conductor loop with the loop plane approximately perpendicular to the X axis and the conductor loop with the loop plane approximately perpendicular to the Y axis, the conductor loops being generated including (cross sections of) the reticulated conductors271and272in a cross section where the reticulated conductors271and272are arranged.

Furthermore, in the case of the eighth configuration example, by providing the relay conductor302, the reticulated conductor271as Vss wiring can be connected with the active element group167at substantially the shortest distance or a short distance. By connecting the reticulated conductor271and the active element group167at substantially the shortest distance or a short distance, the voltage drop, energy loss, or inductive noise between the reticulated conductor271and the active element group167can be reduced.

Ninth Configuration Example

Next,FIG.33illustrates a ninth configuration example of the conductor layers A and B. Note that A inFIG.33illustrates the conductor layer A, and B inFIG.33illustrates the conductor layer B. In the coordinate system inFIG.33, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

The conductor layer A in the ninth configuration example is configured by a reticulated conductor281. Since the reticulated conductor281has a similar shape to the reticulated conductor241of the conductor layer A in the fifth configuration example (FIG.26), the description thereof is omitted. The reticulated conductor281is, for example, wiring (Vss wiring) connected to the GND or the negative power supply.

The conductor layer B in the ninth configuration example is configured by a reticulated conductor282and a relay conductor303. Since the reticulated conductor282has a similar shape to the reticulated conductor242of the conductor layer B in the fifth configuration example (FIG.26), the description thereof is omitted. The reticulated conductor282is, for example, wiring (Vdd wiring) connected to the positive power supply.

The relay conductor (another conductor)303is arranged in a gap region other than the conductor of the reticulated conductor282and is electrically insulated from the reticulated conductor282, and is connected to Vss to which the reticulated conductor281of the conductor layer A is connected

Note that the shape of the relay conductor303is arbitrary, and a symmetric circular or polygonal shape such as rotational symmetry or mirror plane symmetry is desirable. The relay conductor303can be arranged in a center of or at any other position of the gap region of the reticulated conductor282. The relay conductor303may be connected to a conductor layer as Vss wiring different from the conductor layer A. The relay conductor303may be connected to a conductor layer as Vss wiring closer to the active element group167than the conductor layer B. The relay conductor303can be connected to a conductor layer different from the conductor layer A or to a conductor layer or the like closer to the active element group167than the conductor layer B via the conductor via (VIA) extending in the Z direction.

C inFIG.33illustrates a state of the conductor layers A and B respectively illustrated in A and B inFIG.33, which are viewed from the photodiode141side (back surface side). Note that a hatched region283in C inFIG.33where diagonal lines intersect represents a region where the reticulated conductor281of the conductor layer A and the reticulated conductor282of the conductor layer B overlap. In the case of the ninth configuration example, since the active element group167is covered with at least one of the conductor layer A or the conductor layer B, the hot carrier light emission from the active element group167can be shielded.

In the ninth configuration example, in a case where the current flows similarly to the case illustrated inFIG.30, the magnetic fluxes in the substantially X direction and the substantially Y direction are likely to be generated between the reticulated conductor281that is the Vss wiring and the reticulated conductor282that is the Vdd wiring by the conductor loop with the loop plane approximately perpendicular to the X axis and the conductor loop with the loop plane approximately perpendicular to the Y axis, the conductor loops being generated including (cross sections of) the reticulated conductors281and282in a cross section where the reticulated conductors281and282are arranged.

Furthermore, in the case of the ninth configuration example, by providing the relay conductor303, the reticulated conductor281as Vss wiring can be connected with the active element group167at substantially the shortest distance or a short distance. By connecting the reticulated conductor281and the active element group167at substantially the shortest distance or a short distance, the voltage drop, energy loss, or inductive noise between the reticulated conductor281and the active element group167can be reduced.

Tenth Configuration Example

Next,FIG.34illustrates a tenth configuration example of the conductor layers A and B. Note that A inFIG.34illustrates the conductor layer A, and B inFIG.34illustrates the conductor layer B. In the coordinate system inFIG.34, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

The conductor layer A in the tenth configuration example is configured by a reticulated conductor291. Since the reticulated conductor291has a similar shape to the reticulated conductor251of the conductor layer A in the sixth configuration example (FIG.27), the description thereof is omitted. The reticulated conductor291is, for example, wiring (Vss wiring) connected to the GND or the negative power supply.

The conductor layer B in the tenth configuration example is configured by a reticulated conductor292and a relay conductor304. Since the reticulated conductor292has a similar shape to the reticulated conductor252of the conductor layer B in the sixth configuration example (FIG.27), the description thereof is omitted. The reticulated conductor292is, for example, wiring (Vdd wiring) connected to the positive power supply.

The relay conductor (another conductor)304is arranged in a gap region other than the conductor of the reticulated conductor292and is electrically insulated from the reticulated conductor292, and is connected to Vss to which the reticulated conductor291of the conductor layer A is connected

Note that the shape of the relay conductor304is arbitrary, and a symmetric circular or polygonal shape such as rotational symmetry or mirror plane symmetry is desirable. The relay conductor304can be arranged in a center of or at any other position of the gap region of the reticulated conductor292. The relay conductor304may be connected to a conductor layer as Vss wiring different from the conductor layer A. The relay conductor304may be connected to a conductor layer as Vss wiring closer to the active element group167than the conductor layer B. The relay conductor304can be connected to a conductor layer different from the conductor layer A or to a conductor layer or the like closer to the active element group167than the conductor layer B via the conductor via (VIA) extending in the Z direction.

C inFIG.34illustrates a state of the conductor layers A and B respectively illustrated in A and B inFIG.34, which are viewed from the photodiode141side (back surface side). Note that a hatched region293where diagonal lines intersect in C inFIG.34represents a region where the reticulated conductor291of the conductor layer A and the reticulated conductor292of the conductor layer B overlap. In the case of the tenth configuration example, since the active element group167is covered with at least one of the conductor layer A or the conductor layer B, the hot carrier light emission from the active element group167can be shielded.

In the tenth configuration example, in a case where the current flows similarly to the case illustrated inFIG.30, the magnetic fluxes in the substantially X direction and the substantially Y direction are likely to be generated between the reticulated conductor291that is the Vss wiring and the reticulated conductor292that is the Vdd wiring by the conductor loop with the loop plane approximately perpendicular to the X axis and the conductor loop with the loop plane approximately perpendicular to the Y axis, the conductor loops being generated including (cross sections of) the reticulated conductors291and292in a cross section where the reticulated conductors291and292are arranged.

Furthermore, in the case of the tenth configuration example, by providing the relay conductor304, the reticulated conductor291as Vss wiring can be connected with the active element group167at substantially the shortest distance or a short distance. By connecting the reticulated conductor291and the active element group167at substantially the shortest distance or a short distance, the voltage drop, energy loss, or inductive noise between the reticulated conductor291and the active element group167can be reduced.

Simulation Results of Eighth to Tenth Configuration Examples

FIG.35illustrates changes in the induced electromotive force that causes the inductive noise in an image, as simulation results of cases where the eighth to tenth configuration examples (FIGS.32to34) are applied to the solid-state imaging device100. Note that the current conditions of the currents flowing in the eighth to tenth configuration examples are similar to that in the case illustrated inFIG.30. The horizontal axis inFIG.35represents X-axis coordinates of the image, and the vertical axis represents the magnitude of the induced electromotive force.

The solid line L62in A inFIG.35corresponds to the eighth configuration example (FIG.32), and the dotted line L52corresponds to the fourth configuration example (FIG.25). As is clear from the comparison between the solid line L62and the dotted line L52, it can be seen that the eighth configuration example does not deteriorate the change in the induced electromotive force to be generated in the Victim conductor loop as compared with the fourth configuration example. That is, even the eighth configuration example in which the relay conductor302is arranged in the gap of the reticulated conductor272of the conductor layer B can suppress the generation of the inductive noise in the image output from the solid-state imaging device100to the same extent as the fourth configuration example. Note that this simulation result is a simulation result of a case where the reticulated conductor271is not connected to the active element group167and the reticulated conductor272is not connected to the active element group167. For example, in a case where at least a part of the reticulated conductor271and a part of the active element group167are connected via a conductor via or the like at substantially the shortest distance or a short distance, or in a case where at least a part of the reticulated conductor272and a part of the active element group167are connected via a conductor via or the like at substantially the shortest distance or a short distance, the amount of current flowing through the reticulated conductor271and the reticulated conductor272gradually decreases depending on the position. In such a case, there is also a condition that the voltage drop, energy loss, and inductive noise are significantly improved to less than half by providing the relay conductor302.

The solid line L63in B inFIG.35corresponds to the ninth configuration example (FIG.33), and the dotted line L53corresponds to the fifth configuration example (FIG.26). As is clear from the comparison between the solid line L63and the dotted line L53, it can be seen that the ninth configuration example does not deteriorate the change in the induced electromotive force to be generated in the Victim conductor loop as compared with the fifth configuration example. That is, even the ninth configuration example in which the relay conductor303is arranged in the gap of the reticulated conductor282of the conductor layer B can suppress the generation of the inductive noise in the image output from the solid-state imaging device100to the same extent as the fifth configuration example. Note that this simulation result is a simulation result of a case where the reticulated conductor281is not connected to the active element group167and the reticulated conductor282is not connected to the active element group167. For example, in a case where at least a part of the reticulated conductor281and a part of the active element group167are connected via a conductor via or the like at the at substantially the shortest distance shortest distance or a short distance, or in a case where at least a part of the reticulated conductor282and a part of the active element group167are connected via a conductor via or the like at substantially the shortest distance or a short distance, the amount of current flowing through the reticulated conductor281and the reticulated conductor282gradually decreases depending on the position. In such a case, there is also a condition that the voltage drop, energy loss, and inductive noise are significantly improved to less than half by providing the relay conductor303.

The solid line L64in C inFIG.35corresponds to the tenth configuration example (FIG.34), and the dotted line L54corresponds to the sixth configuration example (FIG.27). As is clear from the comparison between the solid line L64and the dotted line L54, it can be seen that the tenth configuration example does not deteriorate the change in the induced electromotive force to be generated in the Victim conductor loop as compared with the sixth configuration example. That is, even the tenth configuration example in which the relay conductor304is arranged in the gap of the reticulated conductor292of the conductor layer B can suppress the generation of the inductive noise in the image output from the solid-state imaging device100to the same extent as the sixth configuration example. Note that this simulation result is a simulation result of a case where the reticulated conductor291is not connected to the active element group167and the reticulated conductor292is not connected to the active element group167. For example, in a case where at least a part of the reticulated conductor291and a part of the active element group167are connected via a conductor via or the like at substantially the shortest distance or a short distance, or in a case where at least a part of the reticulated conductor292and a part of the active element group167are connected via a conductor via or the like at substantially the shortest distance or a short distance, the amount of current flowing through the reticulated conductor291and the reticulated conductor292gradually decreases depending on the position. In such a case, there is also a condition that the voltage drop, energy loss, and inductive noise are significantly improved to less than half by providing the relay conductor304.

Furthermore, as is clear from the comparison of the solid lines L62to L64, it can be seen that the tenth configuration example can further suppress the change in the induced electromotive force to be generated in the Victim conductor loop as compared with the eighth and ninth configuration examples, and can further suppress the inductive noise.

Eleventh Configuration Example

Next,FIG.36illustrates an eleventh configuration example of the conductor layers A and B. Note that A inFIG.36illustrates the conductor layer A, and B inFIG.36illustrates the conductor layer B. In the coordinate system inFIG.36, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

The conductor layer A in the eleventh configuration example is configured by a reticulated conductor311having a resistance value in the X direction (first direction) and a resistance value in the Y direction (second direction) that are different from each other. The reticulated conductor311is, for example, wiring (Vss wiring) connected to the GND or the negative power supply.

The conductor width in the X direction of the reticulated conductor311is WXA, the gap width is GXA, the conductor period is FXA (=the conductor width WXA+the gap width GXA), and an end width is EXA (=the conductor width WXA/2). Furthermore, the conductor width in the Y direction of the reticulated conductor311is WYA, the gap width is GYA, the conductor period is FYA (=the conductor width WYA+the gap width GYA), and the end width is EYA (=the conductor width WYA/2). In the reticulated conductor311, the gap width GYA>the gap width GXA is satisfied. Therefore, the gap region of the reticulated conductor311has a shape longer in the Y direction than in the X direction, the resistance values differ between the X direction and the Y direction, and the resistance value in the Y direction is smaller than the resistance value in the X direction.

The conductor layer B in the eleventh configuration example is configured by a reticulated conductor312having a resistance value in the X direction and a resistance value in the Y direction that are different from each other. The reticulated conductor312is, for example, wiring (Vdd wiring) connected to the positive power supply.

The conductor width in the X direction of the reticulated conductor312is WXB, the gap width is GXB, and the conductor period is FXB (=the conductor width WXB+the gap width GXB). Furthermore, the conductor width in the Y direction of the reticulated conductor312is WYB, the gap width is GYB, the conductor period is FYB (=the conductor width WYB+the gap width GYB), and the end width is EYB (=the conductor width WYB/2). In the reticulated conductor312, the gap width GYB>the gap width GXB is satisfied. Therefore, the gap region of the reticulated conductor312has a shape longer in the Y direction than in the X direction, the resistance values differ between the X direction and the Y direction, and the resistance value in the Y direction is smaller than the resistance value in the X direction.

Note that, in a case where a sheet resistance value of the reticulated conductor311is larger than a sheet resistance value of the reticulated conductor312, the reticulated conductor311and the reticulated conductor312desirably satisfy the following relationships.
The conductor widthWYA≥the conductor widthWYB
The conductor widthWXA≥the conductor widthWXB
The gap widthGXA≤the gap widthGXB
The gap widthGYA≤the gap widthGYB

On the contrary, in a case where the sheet resistance value of the reticulated conductor311is smaller than the sheet resistance value of the reticulated conductor312, the reticulated conductor311and the reticulated conductor312desirably satisfy the following relationships.
The conductor widthWYA≤the conductor widthWYB
The conductor widthWXA≤the conductor widthWXB
The gap widthGXA≥the gap widthGXB
The gap widthGYA≥the gap widthGYB

Moreover, the sheet resistance values and the conductor widths of the reticulated conductors311and312desirably satisfy the following relationships.
(The sheet resistance value of the reticulated conductor 311)/(the sheet resistance value of the reticulated conductor 312)
≈the conductor widthWYA/the conductor widthWYB(The sheet resistance value of the reticulated conductor 311)/(the sheet resistance value of the reticulated conductor 312)
≈the conductor widthWXA/the conductor widthWXB

The limitations regarding the dimensional relationship disclosed in the present specification are not essential, and the current distribution of the reticulated conductor311and the current distribution of the reticulated conductor312are desirably substantially uniform, substantially the same, or substantially similar, and have opposite characteristics.

For example, it is desirable that a ratio of the wiring resistance in the X direction of the reticulated conductor311and the wiring resistance in the Y direction of the reticulated conductor311, and a ratio of the wiring resistance in the X direction of the reticulated conductor312and the wiring resistance in the Y direction of the reticulated conductor312be substantially the same.

Furthermore, it is desirable that a ratio of wiring inductance in the X direction of the reticulated conductor311and wiring inductance in the Y direction of the reticulated conductor311, and a ratio of wiring inductance in the X direction of the reticulated conductor312and wiring inductance in the Y direction of the reticulated conductor312be substantially the same.

Furthermore, it is desirable that a ratio of wiring capacitance in the X direction of the reticulated conductor311and wiring capacitance in the Y direction of the reticulated conductor311, and a ratio of wiring capacitance in the X direction of the reticulated conductor312and wiring capacitance in the Y direction of the reticulated conductor312be substantially the same.

Furthermore, it is desirable that a ratio of wiring impedance in the X direction of the reticulated conductor311and wiring impedance in the Y direction of the reticulated conductor311, and a ratio of wiring impedance in the X direction of the reticulated conductor312and wiring impedance in the Y direction of the reticulated conductor312be substantially the same.

In other words, it is desirable but is not essential to satisfy any of the following relationships:
(the wiring resistance in theXdirection of the reticulated conductor 311×the wiring resistance in theYdirection of the reticulated conductor 312)≈(the wiring resistance in theXdirection of the reticulated conductor 312×the wiring resistance in theYdirection of the reticulated conductor 311);
(the wiring inductance in theXdirection of the reticulated conductor 311×the wiring inductance in theYdirection of the reticulated conductor 312)≈(the wiring inductance in theXdirection of the reticulated conductor 312×the wiring inductance in theYdirection of the reticulated conductor 311);
(the wiring capacitance in theXdirection of the reticulated conductor 311×the wiring capacitance in theYdirection of the reticulated conductor 312)≈(the wiring capacitance in theXdirection of the reticulated conductor 312×the wiring capacitance in theYdirection of the reticulated conductor 311); and
(the wiring impedance in theXdirection of the reticulated conductor 311×the wiring impedance in theYdirection of the reticulated conductor 312)≈(the wiring impedance in theXdirection of the reticulated conductor 312×the wiring impedance in theYdirection of the reticulated conductor 311).

Note that the above-described wiring resistance, wiring inductance, wiring capacitance, and wiring impedance can be replaced with conductor resistance, conductor inductance, conductor capacitance, and conductor impedance, respectively.

Note that the above-described impedance Z, resistor R, inductance L, and capacitance C have a relationship of Z=R+jωL+1÷(jωC), using an angular frequency ω and an imaginary unit j.

Note that the relationship among these ratios may be satisfied as a whole of the reticulated conductor311and the reticulated conductor312or may be satisfied within a part of the reticulated conductor311and the reticulated conductor312, and it is sufficient that the relationship is satisfied within an arbitrary range.

Moreover, a circuit that adjusts the current distributions to be substantially uniform, substantially the same, or substantially similar, and to have opposite characteristics.

By satisfying the above-described relationships, the current distribution of the reticulated conductor311and the current distribution of the reticulated conductor312can be made substantially uniform and have opposite characteristics. Therefore, the magnetic field generated by the current distribution of the reticulated conductor311and the magnetic field generated by the current distribution of the reticulated conductor312can be effectively canceled.

C inFIG.36illustrates a state of the conductor layers A and B respectively illustrated in A and B inFIG.36, which are viewed from the photodiode141side (back surface side). Note that a hatched region313where diagonal lines intersect in C inFIG.36represents a region where the reticulated conductor311of the conductor layer A and the reticulated conductor312of the conductor layer B overlap. In the case of the eleventh configuration example, since the active element group167is covered with at least one of the conductor layer A or the conductor layer B, the hot carrier light emission from the active element group167can be shielded.

Furthermore, in the case of the eleventh configuration example, the region313where the reticulated conductor311and the reticulated conductor312overlap is continuous in the X direction. In the region313where the reticulated conductor311and the reticulated conductor312overlap, currents having polarities different from each other flow in the reticulated conductor311and the reticulated conductor312, and thus magnetic fields generated from the region313cancel each other. Therefore, generation of the inductive noise near the region313can be suppressed.

Furthermore, in the case of the eleventh configuration example, the gap width GYA in the Y direction and the gap width GXA in the X direction of the reticulated conductor311are formed to be different, and the gap width GYB in the Y direction and the gap width GXB in the X direction of the reticulated conductor312are formed to be different.

By forming the reticulated conductors311and312to have the shapes having a difference in the gap widths in the X direction and the Y direction, restrictions such as dimensions of a wiring region, dimensions of a gap region, and occupancy of the wiring region in each conductor layer in actually designing and manufacturing the conductor layers can be secured, and the degree of freedom in designing wiring layout can be increased. Furthermore, the wiring can be designed in a layout that is advantageous in terms of voltage drop (IR-Drop), inductive noise, and the like, as compared with a case having no difference in the gap widths.

FIG.37is a diagram illustrating the current condition of the current flowing in the eleventh configuration example (FIG.36).

It is assumed that AC current evenly flows in ends of the reticulated conductor311constituting the conductor layer A and the reticulated conductor312constituting the conductor layer B. However, the current direction changes with time. For example, when the current flows through the reticulated conductor312that is the Vdd wiring from the upper side to the lower side of the drawing, the current flows through the reticulated conductor311that is the Vss wiring from the lower side to the upper side of the drawing.

In the eleventh configuration example, in a case where the current flows as illustrated inFIG.37, the magnetic fluxes in the substantially X direction and the substantially Y direction are likely to be generated between the reticulated conductor311that is the Vss wiring and the reticulated conductor312that is the Vdd wiring by the conductor loop with the loop plane approximately perpendicular to the X axis and the conductor loop with the loop plane approximately perpendicular to the Y axis, the conductor loops being generated including (cross sections of) the reticulated conductors311and312in a cross section where the reticulated conductors311and312are arranged.

Meanwhile, the Victim conductor loop formed using the signal line132and the control line133is formed in the XY plane in the pixel array121of the first semiconductor substrate101stacked on the second semiconductor substrate102in which the light-shielding structure151formed using the conductor layers A and B is formed. In the Victim conductor loop formed on the XY plane, the induced electromotive force is likely to be generated by the magnetic flux in the Z direction, and an image output from the solid-state imaging device100further deteriorates (the inductive noise increases) as a change in the induced electromotive force is larger.

Moreover, when the effective dimensions of the Victim conductor loop formed using the signal line132and the control line133are changed due to movement of selected pixels in the pixel array121, the change in the induced electromotive force becomes remarkable.

In the case of the eleventh configuration example, the direction (approximately X direction or approximately Y direction) of the magnetic flux generated from the loop plane of the Aggressor conductor loop of the light-shielding structure151formed using the conductor layers A and B and the direction (Z direction) of the magnetic flux to generate the induced electromotive force in the Victim conductor loop are substantially orthogonal and differ by approximately 90 degrees. In other words, the direction of the loop plane where the magnetic flux is generated from the Aggressor conductor loop and the direction of the loop plane where the induced electromotive force is generated in the Victim conductor loop differ by approximately 90 degrees. Therefore, it is expected that the deterioration (generation of inductive noise) of the image output from the solid-state imaging device100is less than that in the first comparative example.

FIG.38illustrates a simulation result of the inductive noise generated in the case where the eleventh configuration example (FIG.36) is applied to the solid-state imaging device100.

A inFIG.38illustrates an image in which the inductive noise can be generated, the image being output from the solid-state imaging device100. B inFIG.38illustrates a change in a pixel signal in the line segment X1-X2of the image illustrated in A inFIG.38. C inFIG.38illustrates the solid line L71representing induced electromotive force that generates the inductive noise in the image. The horizontal axis of C inFIG.38represents X-axis coordinates of the image, and the vertical axis represents the magnitude of the induced electromotive force. Note that the dotted line L1in C inFIG.38corresponds to the first comparative example (FIG.9).

As is clear from the comparison of the solid line L71and the dotted line L1illustrated in C inFIG.38, it can be seen that the eleventh configuration example can suppress the change in the induced electromotive force to be generated in the Victim conductor loop as compared with the first comparative example, and can suppress the inductive noise.

Note that the eleventh configuration example may be rotated by 90 degrees in an XY plane shape and used. Furthermore, the angle is not limited to 90 degrees and the configuration may be rotated by an arbitrary angle and used. For example, the configuration may be diagonal with respect to the X axis and the Y axis.

Twelfth Configuration Example

Next,FIG.39illustrates a twelfth configuration example of the conductor layers A and B. Note that A inFIG.39illustrates the conductor layer A, and B inFIG.39illustrates the conductor layer B. In the coordinate system inFIG.39, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

The conductor layer A in the twelfth configuration example is configured by a reticulated conductor321. Since the reticulated conductor321has a similar shape to the reticulated conductor311of the conductor layer A in the eleventh configuration example (FIG.36), the description thereof is omitted. The reticulated conductor321is, for example, wiring (Vss wiring) connected to the GND or the negative power supply.

The conductor layer B in the twelfth configuration example is configured by a reticulated conductor322and a relay conductor305. Since the reticulated conductor322has a similar shape to the reticulated conductor312of the conductor layer B in the eleventh configuration example (FIG.36), the description thereof is omitted. The reticulated conductor322is, for example, wiring (Vdd wiring) connected to the positive power supply.

The relay conductor (another conductor)305is arranged in a rectangular gap region long in the Y direction other than the conductor of the reticulated conductor322and is electrically insulated from the reticulated conductor322, and is connected to Vss to which the reticulated conductor321of the conductor layer A is connected

Note that the shape of the relay conductor305is arbitrary, and a symmetric circular or polygonal shape such as rotational symmetry or mirror plane symmetry is desirable. The relay conductor305can be arranged in a center of or at any other position of the gap region of the reticulated conductor322. The relay conductor305may be connected to a conductor layer as Vss wiring different from the conductor layer A. The relay conductor305may be connected to a conductor layer as Vss wiring closer to the active element group167than the conductor layer B. The relay conductor305can be connected to a conductor layer different from the conductor layer A or a conductor layer or the like closer to the active element group167than the conductor layer B via the conductor via (VIA) extending in the Z direction.

C inFIG.39illustrates a state of the conductor layers A and B respectively illustrated in A and B inFIG.39, which are viewed from the photodiode141side (back surface side). Note that a hatched region323in C inFIG.39where diagonal lines intersect represents a region where the reticulated conductor321of the conductor layer A and the reticulated conductor322of the conductor layer B overlap. In the case of the twelfth configuration example, since the active element group167is covered with at least one of the conductor layer A or the conductor layer B, the hot carrier light emission from the active element group167can be shielded.

In the twelfth configuration example, in a case where the current flows similarly to the case illustrated inFIG.37, the magnetic fluxes in the substantially X direction and the substantially Y direction are likely to be generated between the reticulated conductor321that is the Vss wiring and the reticulated conductor322that is the Vdd wiring by the conductor loop with the loop plane approximately perpendicular to the X axis and the conductor loop with the loop plane approximately perpendicular to the Y axis, the conductor loops being generated including (cross sections of) the reticulated conductors321and322in a cross section where the reticulated conductors321and322are arranged.

Moreover, in the case of the twelfth configuration example, the region323where the reticulated conductor321and the reticulated conductor322overlap is continuous in the X direction. In the region323where the reticulated conductor321and the reticulated conductor322overlap, currents having polarities different from each other flow in the reticulated conductor321and the reticulated conductor322, and thus magnetic fields generated from the region323cancel each other. Therefore, generation of the inductive noise near the region323can be suppressed.

Furthermore, in the case of the twelfth configuration example, by providing the relay conductor305, the reticulated conductor321as Vss wiring can be connected with the active element group167at substantially the shortest distance or a short distance. By connecting the reticulated conductor321and the active element group167at substantially the shortest distance or a short distance, the voltage drop, energy loss, or inductive noise between the reticulated conductor321and the active element group167can be reduced.

Note that the twelfth configuration example may be rotated by 90 degrees in an XY plane shape and used. Furthermore, the angle is not limited to 90 degrees and the configuration may be rotated by an arbitrary angle and used. For example, the configuration may be diagonal with respect to the X axis and the Y axis.

Thirteenth Configuration Example

Next,FIG.40illustrates a thirteenth configuration example of the conductor layers A and B. Note that A inFIG.40illustrates the conductor layer A, and B inFIG.40illustrates the conductor layer B. In the coordinate system inFIG.40, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

The conductor layer A in the thirteenth configuration example is configured by a reticulated conductor331. Since the reticulated conductor331has a similar shape to the reticulated conductor311of the conductor layer A in the eleventh configuration example (FIG.36), the description thereof is omitted. The reticulated conductor331is, for example, wiring (Vss wiring) connected to the GND or the negative power supply.

The conductor layer B in the thirteenth configuration example is configured by a reticulated conductor332and a relay conductor306. Since the reticulated conductor332has a similar shape to the reticulated conductor312of the conductor layer B in the eleventh configuration example (FIG.36), the description thereof is omitted. The reticulated conductor332is, for example, wiring (Vdd wiring) connected to the positive power supply.

The relay conductor (another conductor)306is obtained by dividing the relay conductor305in the twelfth configuration example (FIG.39) into a plurality of (10in the case ofFIG.40) parts with a space. The relay conductor306is arranged in a rectangular gap region long in the Y direction of the reticulated conductor332and is electrically insulated from the reticulated conductor332, and is connected to Vss to which the reticulated conductor331of the conductor layer A is connected The number of divisions of the relay conductor and the presence/absence of connection to Vss may be different depending on a region. In this case, the current distribution can be finely adjusted at the time of design, leading to suppression of the inductive noise and reduction of the voltage drop (IR-Drop).

Note that the shape of the relay conductor306is arbitrary, and a symmetric circle or polygon such as rotational symmetry or mirror plane symmetry is desirable. The number of divisions of the relay conductor306can be arbitrarily changed. The relay conductor306can be arranged in a center of or at any other position of the gap region of the reticulated conductor332. The relay conductor306may be connected to a conductor layer as Vss wiring different from the conductor layer A. The relay conductor306may be connected to a conductor layer as Vss wiring closer to the active element group167than the conductor layer B. The relay conductor306can be connected to a conductor layer different from the conductor layer A or to a conductor layer or the like closer to the active element group167than the conductor layer B via the conductor via (VIA) extending in the Z direction.

C inFIG.40illustrates a state of the conductor layers A and B respectively illustrated in A and B inFIG.40, which are viewed from the photodiode141side (back surface side). Note that a hatched region333where diagonal lines intersect in C inFIG.40represents a region where the reticulated conductor331of the conductor layer A and the reticulated conductor332of the conductor layer B overlap. In the case of the thirteenth configuration example, since the active element group167is covered with at least one of the conductor layer A or the conductor layer B, the hot carrier light emission from the active element group167can be shielded.

In the thirteenth configuration example, in a case where the current flows similarly to the case illustrated inFIG.37, the magnetic fluxes in the substantially X direction and the substantially Y direction are likely to be generated between the reticulated conductor331that is the Vss wiring and the reticulated conductor332that is the Vdd wiring by the conductor loop with the loop plane approximately perpendicular to the X axis and the conductor loop with the loop plane approximately perpendicular to the Y axis, the conductor loops being generated including (cross sections of) the reticulated conductors331and332in a cross section where the reticulated conductors331and332are arranged.

Moreover, in the case of the thirteenth configuration example, the region333where the reticulated conductor331and the reticulated conductor332overlap is continuous in the X direction. In the region333, currents having polarities different from each other flow in the reticulated conductor331and the reticulated conductor332, and thus magnetic fields generated from the region333cancel each other. Therefore, generation of the inductive noise near the region333can be suppressed.

Furthermore, in the case of the thirteenth configuration example, by providing the relay conductor306, the reticulated conductor331as Vss wiring can be connected with the active element group167at substantially the shortest distance or a short distance. By connecting the reticulated conductor331and the active element group167at substantially the shortest distance or a short distance, the voltage drop, energy loss, or inductive noise between the reticulated conductor331and the active element group167can be reduced.

Furthermore, in the thirteenth configuration example, the relay conductor306is divided into the plurality of parts, the current distribution in the conductor layer A and the current distribution in the conductor layer B can be made substantially uniform and have opposite polarities. Therefore, the magnetic field generated from the conductor layer A and the magnetic field generated from the conductor layer B can cancel each other. Therefore, in the thirteenth configuration example, it is possible to make it difficult to cause a current distribution difference between the Vdd wiring and the Vss wiring due to an external factor. Therefore, the sixteenth configuration example is suitable for a case where the current distribution of the XY plane is complicated, or a case where the impedances of the conductors connected to the reticulated conductors331and332are different between the Vdd wiring and the Vss wiring.

Note that the thirteenth configuration example may be rotated by 90 degrees in an XY plane shape and used. Furthermore, the angle is not limited to 90 degrees and the configuration may be rotated by an arbitrary angle and used. For example, the configuration may be diagonal with respect to the X axis and the Y axis.

Simulation Results of Twelfth and Thirteenth Configuration Examples

FIG.41illustrates changes in the induced electromotive force that causes the inductive noise in an image, as simulation results of cases where the twelfth (FIG.39) and thirteenth (FIG.40) configuration examples are applied to the solid-state imaging device100. Note that the current conditions of the currents flowing in twelfth and thirteenth configuration examples are similar to that in the case illustrated inFIG.37. The horizontal axis inFIG.41represents X-axis coordinates of the image, and the vertical axis represents the magnitude of the induced electromotive force.

The solid line L72in A inFIG.41corresponds to the twelfth configuration example (FIG.39), and the dotted line L1corresponds to the first comparative example (FIG.9). As is clear from the comparison between the solid line L72and the dotted line L1, it can be seen that the twelfth configuration example does not change the induced electromotive force to be generated in the Victim conductor loop as compared with the first comparative example. Therefore, the twelfth configuration example can suppress the inductive noise in the image output from the solid-state imaging device100as compared with the first comparative example. Note that this simulation result is a simulation result of a case where the reticulated conductor321is not connected to the active element group167and the reticulated conductor322is not connected to the active element group167. For example, in a case where at least a part of the reticulated conductor321and a part of the active element group167are connected via a conductor via or the like at substantially the substantially shortest distance or a short distance, or in a case where at least a part of the reticulated conductor322and a part of the active element group167are connected via a conductor via or the like at substantially the shortest distance or a short distance, the amount of current flowing through the reticulated conductor321and the reticulated conductor322gradually decreases depending on the position. In such a case, there is a condition that the voltage drop, energy loss, and inductive noise are significantly improved to less than half by providing the relay conductor305.

The solid line L73in B inFIG.41corresponds to the thirteenth configuration example (FIG.40), and the dotted line L1corresponds to the first comparative example (FIG.9). As is clear from the comparison between the solid line L73and the dotted line L1, it can be seen that the thirteenth configuration example does not change the induced electromotive force to be generated in the Victim conductor loop as compared with the first comparative example. Therefore, the thirteenth configuration example can suppress the inductive noise in the image output from the solid-state imaging device100as compared with the first comparative example. Note that this simulation result is a simulation result of a case where the reticulated conductor331is not connected to the active element group167and the reticulated conductor332is not connected to the active element group167. For example, in a case where at least a part of the reticulated conductor331and a part of the active element group167are connected via a conductor via or the like at substantially the shortest distance or a short distance, or in a case where at least a part of the reticulated conductor332and a part of the active element group167are connected via a conductor via or the like at substantially the shortest distance or a short distance, the amount of current flowing through the reticulated conductor331and the reticulated conductor332gradually decreases depending on the position. In such a case, there is also a condition that the voltage drop, energy loss, and inductive noise are significantly improved to less than half by providing the relay conductor306.

5. Arrangement Example of Electrodes in Semiconductor Substrate in which Conductor Layers A and B are Formed

Next, arrangement of electrodes in a semiconductor substrate in which conductors having different resistance values in the X direction and the Y direction are formed, as in the eleventh to thirteenth configuration examples of the conductor layers A and B, will be described.

Note that the following description will be given using a case in which the thirteenth configuration example (FIG.40) including the conductor layers A and B including the conductors (the reticulated conductors331and332) in which the resistance value in the Y direction is smaller than the resistance value in the X direction is formed in a semiconductor substrate as an example. Note that, the same applies to cases where the eleventh and twelfth configuration examples of the conductor layers A and B including the conductors in which the resistance value in the Y direction is smaller than the resistance value in the X direction are formed in a semiconductor substrate.

In the thirteenth configuration example of the conductor layers A and B formed in the semiconductor substrate, since the resistance values of the conductors (reticulated conductors331and332) in the Y direction are smaller than the resistance values in the X direction, a current easily flows in the Y direction. Therefore, to make the voltage drop (IR-Drop) in the conductors in the thirteenth configuration example of the conductor layers A and B as small as possible, it is desirable to arrange a plurality of pads (electrodes) to be arranged in the semiconductor substrate more densely in the X direction that is the direction with the large resistance value than in the Y direction that is the direction with the small resistance value. However, the pads may be more densely arranged in the Y direction than in the X direction.

First Arrangement Example of Pads on Semiconductor Substrate

FIG.42is a plan view illustrating a first arrangement example in which the pads are arranged more densely in the X direction than in the Y direction on the semiconductor substrate. Note that, in the coordinate system inFIG.42, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

A inFIG.42illustrates a case of arranging pads on one side of a wiring region400in which a plurality of the thirteenth configuration examples (FIG.40) each including the conductor layers A and B is formed. B inFIG.42illustrates a case of arranging pads on two sides facing each other in the Y direction of the wiring region400in which a plurality of the thirteenth configuration examples (FIG.40) each including the conductor layers A and B is formed. Note that the dotted arrow in the figure illustrates an example of the direction of the current flowing there, and a current loop411by the current illustrated by the dotted arrow is generated. The direction of the current indicated by the dotted arrow changes from moment to moment.

C inFIG.42illustrates a case of arranging pads on three sides of the wiring region400in which a plurality of the thirteenth configuration examples (FIG.40) each including the conductor layers A and B is formed. D inFIG.42illustrates a case of arranging pads on four sides of the wiring region400in which a plurality of the thirteenth configuration examples (FIG.40) each including the conductor layers A and B is formed. E inFIG.42illustrates the orientation of the plurality of thirteenth configuration examples of the conductor layers A and B formed in the wiring region400.

The pad401arranged in the wiring region400is connected to the Vdd wiring, and the pad402is, for example, wiring (Vss wiring) connected to the GND or the negative power supply.

In the case of the first arrangement example illustrated inFIG.42, each of the pads401and402includes one or a plurality (two in the case ofFIG.42) of adjacently arranged pads. The pads401and402are arranged adjacent to each other. The pad401including one pad and the pad402including one pad are arranged adjacent to each other, and the pad401including two pads and the pad402including two pads are arranged adjacent to each other. The polarities of the pads401and402(the connection destination is the Vdd wiring or the Vss wiring) are opposite polarities. The number of pads401and the number of pads402arranged in the wiring region400are substantially the same.

As a result, the current distributions respectively flowing through the conductor layers A and B formed in the wiring region400can be made substantially uniform and have opposite polarities. Therefore, the magnetic fields respectively generated from the conductor layers A and B and the induced electromotive forces based on the magnetic fields can be effectively canceled.

Furthermore, as illustrated in B, C, and D inFIG.42, in a case where the pads are formed on two or more sides of the wiring region400, the polarities of the pads facing each other on the opposite sides are opposite. As a result, as illustrated by the dotted arrows in B inFIG.42, currents in the same direction are likely to be distributed at positions where the X coordinate of the wiring region400is common and the Y coordinates are different.

Second Arrangement Example of Pads on Semiconductor Substrate

Next,FIG.43is a plan view illustrating a second arrangement example in which the pads are arranged more densely in the X direction than in the Y direction on the semiconductor substrate. Note that, in the coordinate system inFIG.43, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

A inFIG.43illustrates a case of arranging pads on two sides facing each other in the Y direction of the wiring region400in which a plurality of the thirteenth configuration examples (FIG.40) each including the conductor layers A and B is formed. Note that the dotted arrow in the figure illustrates the direction of the current flowing there, and a current loop412by the current illustrated by the dotted arrow is generated. The direction of the current indicated by the dotted arrow changes from moment to moment.

B inFIG.43illustrates a case of arranging pads on three sides of the wiring region400in which a plurality of the thirteenth configuration examples (FIG.40) each including the conductor layers A and B is formed. C inFIG.43illustrates a case of arranging pads on four sides of the wiring region400in which a plurality of the thirteenth configuration examples (FIG.40) each including the conductor layers A and B is formed. D inFIG.43illustrates the orientation of the plurality of thirteenth configuration examples of the conductor layers A and B formed in the wiring region400.

The pad401arranged in the wiring region400is connected to the Vdd wiring, and the pad402is, for example, wiring (Vss wiring) connected to the GND or the negative power supply.

In the case of the second arrangement example illustrated inFIG.43, each of the pads401and402includes a plurality (two in the case ofFIG.43) of adjacently arranged pads. The pads401and402are arranged adjacent to each other. The pad401including one pad and the pad402including one pad are arranged adjacent to each other, and the pad401including two pads and the pad402including two pads are arranged adjacent to each other. The polarities of the pads401and402(the connection destination is the Vdd wiring or the Vss wiring) are opposite polarities. The number of pads401and the number of pads402arranged in the wiring region400are substantially the same.

As a result, the current distributions respectively flowing through the conductor layers A and B formed in the wiring region400can be made substantially uniform and have opposite polarities. Therefore, the magnetic fields respectively generated from the conductor layers A and B and the induced electromotive forces based on the magnetic fields can be effectively canceled.

Moreover, in the second arrangement example, the polarities of the pads facing each other on the opposite sides are the same. Note that the polarities of some of the pads facing each other on the opposite sides may be opposite. As a result, a current loop412, which is smaller than the current loop411illustrated in B inFIG.42, is generated in the wiring region400. The size of the current loop affects the distribution range of the magnetic field, and the smaller the electric field loop, the narrower the distribution range of the magnetic field. Therefore, in the second arrangement example, the distribution range of the magnetic field is narrower than that in the first arrangement example. Therefore, in the second arrangement example, the generated induced electromotive force and the inductive noise based on the induced electromotive force can be made smaller than that in the first arrangement example.

Third Arrangement Example of Pads on Semiconductor Substrate

Next,FIG.44is a plan view illustrating a third arrangement example in which the pads are arranged more densely in the X direction than in the Y direction on the semiconductor substrate. Note that, in the coordinate system inFIG.44, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

A inFIG.44illustrates a case of arranging pads on one side of the wiring region400in which a plurality of the thirteenth configuration examples (FIG.40) each including the conductor layers A and B is formed. B inFIG.44illustrates a case of arranging pads on two sides facing each other in the Y direction of the wiring region400in which a plurality of the thirteenth configuration examples (FIG.40) each including the conductor layers A and B is formed. Note that the dotted arrow in the figure illustrates the direction of the current flowing there, and a current loop413by the current illustrated by the dotted arrow is generated.

C inFIG.44illustrates a case of arranging pads on three sides of the wiring region400in which a plurality of the thirteenth configuration examples (FIG.40) each including the conductor layers A and B is formed. D inFIG.44illustrates a case of arranging pads on four sides of the wiring region400in which a plurality of the thirteenth configuration examples (FIG.40) each including the conductor layers A and B is formed. E inFIG.44illustrates the orientation of the plurality of thirteenth configuration examples of the conductor layers A and B formed in the wiring region400.

The pad401arranged in the wiring region400is connected to the Vdd wiring, and the pad402is, for example, wiring (Vss wiring) connected to the GND or the negative power supply.

In the case of the third arrangement example illustrated inFIG.44, the polarities (connection destination is Vdd wiring or Vss wiring) of the pads forming a pad group including a plurality (two in the case ofFIG.44) of adjacently arranged pads are opposite. The number of pads401and the number of pads402arranged on one or all sides of the wiring region400are substantially the same.

Moreover, in the third arrangement example, the polarities of the pads facing each other on the opposite sides are the same. Note that the polarities of some of the pads facing each other on the opposite sides may be opposite.

As a result, the current loop413that is smaller than the current loop412illustrated in A inFIG.43is generated in the wiring region400. Therefore, in the third arrangement example, the distribution range of the magnetic field is narrower than that in the second arrangement example. Therefore, in the third arrangement example, the generated induced electromotive force and the inductive noise based on the induced electromotive force can be made smaller than that in the second arrangement example.

Example of Conductors Having Different Resistance Values in Y Direction and in X Direction

FIG.45is plan views illustrating other examples of the conductors constituting the conductor layers A and B. That is,FIG.45is plan views illustrating examples of conductors having different resistance values in the Y direction and the X direction. Note that A to C inFIG.45illustrate examples in which the resistance value in the Y direction is smaller than the resistance value in the X direction, and D to F inFIG.45illustrate examples in which the resistance value in the X direction smaller than the resistance value in the Y direction.

A inFIG.45illustrates a reticulated conductor in which a conductor width WX in the X direction and a conductor width WY in the Y direction are equal, and a gap width GX in the X direction is narrower than a gap width GY in the Y direction. B inFIG.45illustrates a reticulated conductor in which the conductor width WX in the X direction is wider than the conductor width WY in the Y direction, and the gap width GX in the X direction is narrower than the gap width GY in the Y direction. C inFIG.45illustrates a reticulated conductor in which the conductor width WX in the X direction and the conductor width WY in the Y direction are equal, the gap width GX in the X direction and the gap width GY in the Y direction are equal, and a hole is provided in a region of a portion long in the X direction having the conductor width WY, the region not intersecting with a portion long in the Y direction having the conductor width WX.

D inFIG.45illustrates a reticulated conductor in which the conductor width WX in the X direction and the conductor width WY in the Y direction are equal, and the gap width GX in the X direction is wider than the gap width GY in the Y direction. E inFIG.45illustrates a reticulated conductor in which the conductor width WX in the X direction is narrower than the conductor width WY in the Y direction, and the gap width GX in the X direction is wider than the gap width GY in the Y direction. F inFIG.45illustrates a reticulated conductor in which the conductor width WX in the X direction and the conductor width WY in the Y direction are equal, the gap width GX in the X direction and the gap width GY in the Y direction are equal, and a hole is provided in a region of a portion long in the Y direction having the conductor width WX, the region not intersecting with a portion long in the X direction having the conductor width WY.

In the first to third arrangement examples of the pads in the wiring region400illustrated inFIGS.42to44, the resistance value in the Y direction as illustrated in A to C inFIG.45is smaller than the resistance value in the X direction. In a case where a conductor in which a current easily flows in the Y direction is formed in the wiring region400, it has an effect of suppressing the voltage drop (IR-Drop) in the conductor.

Furthermore, in the first to third arrangement examples of the pads in the wiring region400illustrated inFIGS.42to44, the resistance value in the X direction as illustrated in D to F inFIG.45is smaller than the resistance value in the Y direction, and in a case where a conductor in which a current easily flows in the X direction is formed in the wiring region400, the current is easily diffused in the X direction, and the magnetic field near the pads arranged on the side of the wiring region400is less likely to be concentrated. Therefore, the effect of suppressing generation of the inductive noise can be expected.

6. Modification of Configuration Example of Conductor Layers A and B

Next, modifications of some of the first to thirteenth configuration examples of the conductor layers A and B will be described.

FIG.46is a diagram illustrating a modification in which the conductor period in the X direction of the second configuration example (FIG.15) of the conductor layers A and B is deformed by a factor of ½ and an effect of the modification. Note that A inFIG.46illustrates the second configuration example of the conductor layers A and B, and B inFIG.46illustrates the modification of the second configuration example of the conductor layers A and B.

C inFIG.46illustrates a change in the induced electromotive force that causes the inductive noise in an image, as a simulation result of a case where the modification illustrated in B inFIG.46is applied to the solid-state imaging device100. Note that the current condition of the current flowing in this modification is similar to the case illustrated inFIG.13. The horizontal axis inFIG.46represents X-axis coordinates of the image, and the vertical axis represents the magnitude of the induced electromotive force.

The solid line L81in C inFIG.46corresponds to the modification illustrated in B inFIG.46, and the dotted line L21corresponds to the second configuration example (FIG.15). As is clear from the comparison between the solid line L81and the dotted line L21, this modification has a slightly less change in the induced electromotive force to be generated in the Victim conductor loop than the second configuration example. Therefore, it can be seen that this modification can slightly suppress the inductive noise as compared with the second configuration example.

FIG.47is a diagram illustrating a modification in which the conductor period in the X direction of the fifth configuration example (FIG.26) of the conductor layers A and B is deformed by a factor of ½ and an effect of the modification. Note that A inFIG.47illustrates the fifth configuration example of the conductor layers A and B, and B inFIG.47illustrates the modification of the fifth configuration example of the conductor layers A and B.

C inFIG.47illustrates a change in the induced electromotive force that causes the inductive noise in an image, as a simulation result of a case where the modification illustrated in B inFIG.47is applied to the solid-state imaging device100. Note that the current condition of the current flowing in this modification is similar to the case illustrated inFIG.23. The horizontal axis inFIG.47represents X-axis coordinates of the image, and the vertical axis represents the magnitude of the induced electromotive force.

The solid line L82in C inFIG.47corresponds to the modification illustrated in B inFIG.47, and the dotted line L53corresponds to the fifth configuration example (FIG.26). As is clear from the comparison between the solid line L82and the dotted line L53, this modification has a very little change in the induced electromotive force to be generated in the Victim conductor loop as compared with the fifth configuration example. Therefore, it can be seen that this modification can further suppress the inductive noise as compared with the fifth configuration example.

FIG.48is a diagram illustrating a modification in which the conductor period in the X direction of the sixth configuration example (FIG.27) of the conductor layers A and B is deformed by a factor of ½ and an effect of the modification. Note that A inFIG.48illustrates the sixth configuration example of the conductor layers A and B, and B inFIG.48illustrates the modification of the sixth configuration example of the conductor layers A and B.

C inFIG.48illustrates a change in the induced electromotive force that causes the inductive noise in an image, as a simulation result of a case where the modification illustrated in B inFIG.48is applied to the solid-state imaging device100. Note that the current condition of the current flowing in this modification is similar to the case illustrated inFIG.23. The horizontal axis inFIG.48represents X-axis coordinates of the image, and the vertical axis represents the magnitude of the induced electromotive force.

The solid line L83in C inFIG.48corresponds to the modification illustrated in B inFIG.48, and the dotted line L54corresponds to the sixth configuration example (FIG.27). As is clear by comparing the solid line L83and the dotted line L54, this modification has a smaller change in the induced electromotive force to be generated in the Victim conductor loop than the sixth configuration example. Therefore, it can be seen that this modification can further suppress the inductive noise as compared with the sixth configuration example.

FIG.49is a diagram illustrating a modification in which the conductor period in the Y direction of the second configuration example (FIG.15) of the conductor layers A and B is deformed by a factor of ½ and an effect of the modification. Note that A inFIG.49illustrates the second configuration example of the conductor layers A and B, and B inFIG.49illustrates the modification of the second configuration example of the conductor layers A and B.

C inFIG.49illustrates a change in the induced electromotive force that causes the inductive noise in an image, as a simulation result of a case where the modification illustrated in B inFIG.49is applied to the solid-state imaging device100. Note that the current condition of the current flowing in this modification is similar to the case illustrated inFIG.13. The horizontal axis inFIG.49represents X-axis coordinates of the image, and the vertical axis represents the magnitude of the induced electromotive force.

The solid line L111in C inFIG.49corresponds to the modification illustrated in B inFIG.49, and the dotted line L21corresponds to the second configuration example. As is clear from the comparison between the solid line L111and the dotted line L21, this modification has a slightly less change in the induced electromotive force to be generated in the Victim conductor loop than the second configuration example. Therefore, it can be seen that this modification can slightly suppress the inductive noise as compared with the second configuration example.

FIG.50is a diagram illustrating a modification in which the conductor period in the Y direction of the fifth configuration example (FIG.26) of the conductor layers A and B is deformed by a factor of ½ and an effect of the modification. Note that A inFIG.50illustrates the fifth configuration example of the conductor layers A and B, and B inFIG.50illustrates the modification of the fifth configuration example of the conductor layers A and B.

C inFIG.50illustrates a change in the induced electromotive force that causes the inductive noise in an image, as a simulation result of a case where the modification illustrated in B inFIG.50is applied to the solid-state imaging device100. Note that the current condition of the current flowing in this modification is similar to the case illustrated inFIG.23. The horizontal axis inFIG.50represents X-axis coordinates of the image, and the vertical axis represents the magnitude of the induced electromotive force.

The solid line L112in C inFIG.50corresponds to the modification illustrated in B inFIG.50, and the dotted line L53corresponds to the fifth configuration example. As is clear from the comparison between the solid line L112and the dotted line L53, this modification has a very little change in the induced electromotive force to be generated in the Victim conductor loop as compared with the fifth configuration example. Therefore, it can be seen that this modification can further suppress the inductive noise as compared with the fifth configuration example.

FIG.51is a diagram illustrating a modification in which the conductor period in the Y direction of the sixth configuration example (FIG.27) of the conductor layers A and B is deformed by a factor of ½ and an effect of the modification. Note that A inFIG.51illustrates the sixth configuration example of the conductor layers A and B, and B inFIG.51illustrates the modification of the sixth configuration example of the conductor layers A and B.

C inFIG.51illustrates a change in the induced electromotive force that causes the inductive noise in an image, as a simulation result of a case where the modification illustrated in B inFIG.51is applied to the solid-state imaging device100. Note that the current condition of the current flowing in this modification is similar to the case illustrated inFIG.23. The horizontal axis inFIG.51represents X-axis coordinates of the image, and the vertical axis represents the magnitude of the induced electromotive force.

The solid line L113in C inFIG.51corresponds to the modification illustrated in B inFIG.51, and the dotted line L54corresponds to the sixth configuration example. As is clear by comparing the solid line L113and the dotted line L54, this modification has a smaller change in the induced electromotive force to be generated in the Victim conductor loop than the sixth configuration example. Therefore, it can be seen that this modification can further suppress the inductive noise as compared with the sixth configuration example.

FIG.52is a diagram illustrating a modification in which the conductor width in the X direction of the second configuration example (FIG.15) of the conductor layers A and B is deformed by a factor of 2 and an effect of the modification. Note that A inFIG.52illustrates the second configuration example of the conductor layers A and B, and B inFIG.52illustrates the modification of the second configuration example of the conductor layers A and B.

C inFIG.52illustrates a change in the induced electromotive force that causes the inductive noise in an image, as a simulation result of a case where the modification illustrated in B inFIG.52is applied to the solid-state imaging device100. Note that the current condition of the current flowing in this modification is similar to the case illustrated inFIG.13. The horizontal axis inFIG.52represents X-axis coordinates of the image, and the vertical axis represents the magnitude of the induced electromotive force.

The solid line L121in C inFIG.52corresponds to the modification illustrated in B inFIG.52, and the dotted line L21corresponds to the second configuration example. As is clear from the comparison between the solid line L121and the dotted line L21, this modification has a slightly less change in the induced electromotive force to be generated in the Victim conductor loop than in the second configuration example. Therefore, it can be seen that this modification can slightly suppress the inductive noise as compared with the second configuration example.

FIG.53is a diagram illustrating a modification in which the conductor width in the X direction of the fifth configuration example (FIG.26) of the conductor layers A and B is deformed by a factor of 2 and an effect of the modification. Note that A inFIG.53illustrates the fifth configuration example of the conductor layers A and B, and B inFIG.53illustrates the modification of the fifth configuration example of the conductor layers A and B.

C inFIG.53illustrates a change in the induced electromotive force that causes the inductive noise in an image, as a simulation result of a case where the modification illustrated in B inFIG.53is applied to the solid-state imaging device100. Note that the current condition of the current flowing in this modification is similar to the case illustrated inFIG.23. The horizontal axis inFIG.53represents X-axis coordinates of the image, and the vertical axis represents the magnitude of the induced electromotive force.

The solid line L122in C inFIG.53corresponds to the modification illustrated in B inFIG.53, and the dotted line L53corresponds to the fifth configuration example. As is clear from the comparison between the solid line L122and the dotted line L53, this modification has a very little change in the induced electromotive force to be generated in the Victim conductor loop as compared with the fifth configuration example. Therefore, it can be seen that this modification can further suppress the inductive noise as compared with the fifth configuration example.

FIG.54is a diagram illustrating a modification in which the conductor width in the X direction of the sixth configuration example (FIG.27) of the conductor layers A and B is deformed by a factor of 2 and an effect of the modification. Note that A inFIG.54illustrates the sixth configuration example of the conductor layers A and B, and B inFIG.54illustrates the modification of the sixth configuration example of the conductor layers A and B.

C inFIG.54illustrates a change in the induced electromotive force that causes the inductive noise in an image, as a simulation result of a case where the modification illustrated in B inFIG.54is applied to the solid-state imaging device100. Note that the current condition of the current flowing in this modification is similar to the case illustrated inFIG.23. The horizontal axis inFIG.54represents X-axis coordinates of the image, and the vertical axis represents the magnitude of the induced electromotive force.

The solid line L123in C inFIG.54corresponds to the modification illustrated in B inFIG.54, and the dotted line L54corresponds to the sixth configuration example. As is clear from the comparison between the solid line L123and the dotted line L54, this modification has a smaller change in the induced electromotive force to be generated in the Victim conductor loop than the sixth configuration example. Therefore, it can be seen that this modification can further suppress the inductive noise as compared with the sixth configuration example.

FIG.55is a diagram illustrating a modification in which the conductor width in the Y direction of the second configuration example (FIG.15) of the conductor layers A and B is deformed by a factor of 2 and an effect of the modification. Note that A inFIG.55illustrates the second configuration example of the conductor layers A and B, and B inFIG.55illustrates the modification of the second configuration example of the conductor layers A and B.

C inFIG.55illustrates a change in the induced electromotive force that causes the inductive noise in an image, as a simulation result of a case where the modification illustrated in B inFIG.55is applied to the solid-state imaging device100. Note that the current condition of the current flowing in this modification is similar to the case illustrated inFIG.13. The horizontal axis inFIG.55represents X-axis coordinates of the image, and the vertical axis represents the magnitude of the induced electromotive force.

The solid line L131in C inFIG.55corresponds to the modification illustrated in B inFIG.55, and the dotted line L21corresponds to the second configuration example. As is clear from the comparison between the solid line L131and the dotted line L21, this modification has a slightly less change in the induced electromotive force to be generated in the Victim conductor loop than the second configuration example. Therefore, it can be seen that this modification can slightly suppress the inductive noise as compared with the second configuration example.

FIG.56is a diagram illustrating a modification in which the conductor width in the Y direction of the fifth configuration example (FIG.26) of the conductor layers A and B is deformed by a factor of 2 and an effect of the modification. Note that A inFIG.56illustrates the fifth configuration example of the conductor layers A and B, and B inFIG.56illustrates the modification of the fifth configuration example of the conductor layers A and B.

C inFIG.56illustrates a change in the induced electromotive force that causes the inductive noise in an image, as a simulation result of a case where the modification illustrated in B inFIG.56is applied to the solid-state imaging device100. Note that the current condition of the current flowing in this modification is similar to the case illustrated inFIG.23. The horizontal axis inFIG.56represents X-axis coordinates of the image, and the vertical axis represents the magnitude of the induced electromotive force.

The solid line L132in C inFIG.56corresponds to the modification illustrated in B inFIG.56, and the dotted line L53corresponds to the fifth configuration example. As is clear from the comparison between the solid line L132and the dotted line L53, this modification has a very little change in the induced electromotive force to be generated in the Victim conductor loop as compared with the fifth configuration example. Therefore, it can be seen that this modification can further suppress the inductive noise as compared with the fifth configuration example.

FIG.57is a diagram illustrating a modification in which the conductor width in the Y direction of the sixth configuration example (FIG.27) of the conductor layers A and B is deformed by a factor of 2 and an effect of the modification. Note that A inFIG.57illustrates the sixth configuration example of the conductor layers A and B, and B inFIG.57illustrates the modification of the sixth configuration example of the conductor layers A and B.

C inFIG.57illustrates a change in the induced electromotive force that causes the inductive noise in an image, as a simulation result of a case where the modification illustrated in B inFIG.57is applied to the solid-state imaging device100. Note that the current condition of the current flowing in this modification is similar to the case illustrated inFIG.23. The horizontal axis inFIG.57represents X-axis coordinates of the image, and the vertical axis represents the magnitude of the induced electromotive force.

The solid line L133in C inFIG.57corresponds to the modification illustrated in B inFIG.57, and the dotted line L54corresponds to the sixth configuration example. As is clear from the comparison between the solid line L133and the dotted line L54, this modification has a smaller change in the induced electromotive force to be generated in the Victim conductor loop than the sixth configuration example. Therefore, it can be seen that this modification can further suppress the inductive noise as compared with the sixth configuration example.

7. Modification of Reticulated Conductor

Next,FIG.58is plan views illustrating modifications of the reticulated conductor applicable to each of the above-described configuration examples of the conductor layers A and B.

A inFIG.58is simplified illustration of the shape of the reticulated conductor used in each of the above-described configuration examples of the conductor layers A and B. The reticulated conductor adopted in each of the above-described configuration examples of the conductor layers A and B has a rectangular gap region, and the rectangular gap regions are linearly arranged in the X direction and the Y direction.

B inFIG.58is simplified illustration of a first modification of the reticulated conductor. In the first modification of the reticulated conductor, the gap region is rectangular, and the gap regions are linearly arranged in the X direction and are arranged in the Y direction with a stepwise shift.

C inFIG.58is simplified illustration of a second modification of the reticulated conductor. In the second modification of the reticulated conductor, the gap region is rhombic, and the gap regions are linearly arranged in a diagonal direction.

D inFIG.58is simplified illustration of a third modification of the reticulated conductor. In the third modification of the reticulated conductor, the gap region is circular or polygonal other than rectangular (octagonal in the case of D inFIG.58), and the gap regions are linearly arranged in the X direction and the Y direction.

E inFIG.58is simplified illustration of a fourth modification of the reticulated conductor. In the fourth modification of the reticulated conductor, the gap region is circular or polygonal other than rectangular (octagonal in the case of E inFIG.58), and the gap regions are linearly arranged in the X direction, and are arranged in the Y direction with a stepwise shift.

F inFIG.58is simplified illustration of a fifth modification of the reticulated conductor. In the fifth modification of the reticulated conductor, the gap region is circular or polygonal other than rectangular (octagonal in the case of F inFIG.58), and the gap regions are linearly arranged in the diagonal direction.

Note that the shape of the reticulated conductor applicable to each configuration example of the conductor layers A and B is not limited to the modifications illustrated inFIG.58as long as the shape is reticulated.

8. Various Effects

<Improvement of Degree of Freedom in Layout Design>

As described above, in each of the configuration examples of the conductor layers A and B, the planar conductor or the reticulated conductor is adopted. In general, the reticulated conductor (lattice conductor) has a wiring structure that is periodic in the X direction and the Y direction. Therefore, by designing the reticulated conductor having a basic periodic structure that is a unit of the periodic structure (for one period) and repeatedly arranging the basic periodic structure in the X direction and the Y direction, the wiring layout can be more easily designed than the case of using the linear conductor. In other words, in the case of using the reticulated conductor, the degree of freedom in layout is improved as compared with the case of using the linear conductor. Therefore, the man-hours, time, and cost required for the layout design can be reduced.

FIG.59simulates the design man-hours in the case of using the linear conductor and the case of using the reticulated conductor (lattice conductor) in designing the circuit wiring layout that satisfies a predetermined condition.

In the case ofFIG.59, when the design man-hours in designing the layout using the linear conductor is 100%, the design man-hours in designing the layout using the reticulated conductor (lattice conductor) is about 40%, which can be seen that the man-hours can significantly be reduced.

<Reduction of Voltage Drop (IR-Drop)>

FIG.60is diagrams illustrating a voltage change in a case of causing a DC current to flow in the Y direction under the same condition through conductors of the same material but different shapes arranged on the XY plane.

A inFIG.60corresponds to the linear conductor, B inFIG.60corresponds to the reticulated conductor, and C inFIG.60corresponds to the planar conductor. The shade of color represents the voltage. Comparing A, B, and C inFIG.60, it can be seen that the voltage change is the largest in the linear conductor, followed by the reticulated conductor and the planar conductor in that order.

FIG.61is a diagram illustrating a relative graph of the voltage drops of the linear conductor, the reticulated conductor, and the planar conductor, assuming that the voltage drop of the linear conductor illustrated in A inFIG.60is 100%.

As is clear fromFIG.61, it can be seen that the planar conductor and the reticulated conductor can reduce the voltage drop (IR-Drop), which can be a fatal obstacle to the driving of the semiconductor device, as compared with the linear conductor.

However, it is known that in many cases, the planar conductor cannot be manufactured in the current semiconductor substrate manufacturing process. Therefore, it is realistic to adopt a configuration example using the reticulated conductor for both the conductor layers A and B. However, this does not apply to the case where the semiconductor substrate manufacturing process has been advanced to manufacture the planar conductor. There are some cases where the planar conductor can be manufactured for the uppermost metal or the lowermost metal in metal layers.

The conductor (planar conductor or reticulated conductor) forming the conductor layers A and B may cause not only the inductive noise but also capacitive noise for the Victim conductor loop including the signal line132and the control line133.

Here, the capacitive noise refers to generation of a voltage in the signal line132and the control line133by capacitive coupling between the conductor forming the conductor layers A and B, and the signal line132and the control line133, in a case where a voltage is applied to the conductor, and occurrence of voltage noise in the signal line132or the control line133as the applied voltage changes. This voltage noise becomes noise of the pixel signal.

The magnitude of the capacitive noise is considered to be substantially proportional to the capacitance and voltage between the conductor forming the conductor layers A and B and the wiring of the signal line132, the control line133, and the like. The capacitance is a capacitance C=ε*S/d between two conductors in a case where an overlapping area of the two conductors (one may be a conductor and the other may be wiring) is S, the two conductors are arranged in parallel with a distance d, and a dielectric with a dielectric constant ε is uniformly added between the conductors. Therefore, it can be seen that the larger the overlapping area S of the two conductors, the larger the capacitive noise.

FIG.62is diagrams for describing a difference in capacitance between conductors of the same material but different shapes arranged on the XY plane, and other conductors (wiring).

A inFIG.62corresponds to the linear conductor long in the Y direction and wirings501and502(corresponding to the signal line132and the control line133) linearly formed in the Y direction with a space in the Z direction from the linear conductor. Note that the wiring501as a whole overlaps with the conductor region of the linear conductor, but the wiring502as a whole overlaps with the gap region of the linear conductor and does not have an area overlapping with the conductor region.

B inFIG.62corresponds to the reticulated conductor and wirings501and502linearly formed in the Y direction with a space in the Z direction from the reticulated conductor. Note that the wiring501as a whole overlaps with the conductor region of the reticulated conductor, but substantially half of the wiring502overlaps with the conductor region of the reticulated conductor.

C inFIG.62corresponds to the planar conductor and wirings501and502linearly formed in the Y direction with a space in the Z direction from the planar conductor. Note that the wirings501and502as a whole overlap with the conducting region of the planar conductor.

In a case of comparing the differences between the capacitance of the conductor (linear conductor, reticulated conductor, or planar conductor) and the wiring501, and the capacitance of the conductor (linear conductor, reticulated conductor, or planar conductor) and the wiring502in A, B, and C inFIG.62, the difference is the largest in the linear conductor, followed by the reticulated conductor and the planar conductor.

That is, in the linear conductor, the difference in capacitance between the linear conductor and the wiring is large due to the difference in the XY coordinates of the wiring, and generation of the capacitive noise is also significantly different. Therefore, there is a possibility of noise of a pixel signal having high visibility in an image.

In contrast, in the reticulated conductor and the planar conductor, the difference in capacitance between the conductor and the wiring due to the difference in the XY coordinates of the wiring is smaller than the linear conductor, and thus generation of the capacitive noise can be made smaller. Therefore, the noise of the pixel signal due to the capacitive noise can be suppressed.

As described above, the reticulated conductor is used in the configuration examples of the conductor layers A and B other than the first configuration example. The reticulated conductor can be expected to have an effect of reducing radioactive noise. Here, it is assumed that the radioactive noise includes radioactive noise (unnecessary radiation) from the inside to the outside of the solid-state imaging device100and radioactive noise (transmitted noise) from the outside to the inside of the solid-state imaging device100.

Since the radioactive noise from the outside to the inside of the solid-state imaging device100can generate voltage noise and pixel signal noise in the signal line132and the like, the effect of suppressing the voltage noise and pixel signal noise can be expected in a case of adopting a configuration example using the reticulated conductor for at least one of the conductor layer A or B.

Since the conductor period of the reticulated conductor affects a frequency band of the radioactive noise that can be reduced by the reticulated conductor, the radioactive noise in a broader frequency band can be reduced in a case of using the reticulated conductors having different conductor periods for the conductor layers A and B than a case of using the reticulated conductors having the same conductor frequency for the conductor layers A and B.

Note that the above-described effects are merely examples and are not limited, and other effects may be exhibited.

9. Configuration Example with Different Drawing Portion

By the way, in the case where the wiring layer165A as the conductor layer A or the wiring layer165B as the conductor layer B is connected to the pad401or402, for example, a wiring lead-out portion for being connected to the pad401or402is provided, as illustrated inFIGS.42to44. The wiring lead-out portion is usually formed to have a narrow wiring width according to the size of the pad.

Therefore, consider the case by dividing the wiring layer165A (conductor layer A) into a main conductor portion165Aa and a lead-out conductor portion165Ab as illustrated in A inFIG.63. The main conductor portion165Aa is a portion provided to mainly shield the hot carrier light emission from the active element group167and suppress generation of the inductive noise, and has a larger area than the lead-out conductor portion165Ab. The lead-out conductor portion165Ab is a portion provided to mainly connect the main conductor portion165Aa and the pad402and supply a predetermined voltage such as the GND or the negative power supply (Vss) to the main conductor portion165Aa. The length (width) of at least one of the X direction (first direction) or the Y direction (second direction) of the lead-out conductor portion165Ab is shorter (narrower) than the length (width) of the main conductor portion165Aa. A connecting portion between the main conductor portion165Aa and the lead-out conductor portion165Ab illustrated by the alternate long and short dash line in A inFIG.63is referred to as a joint portion.

Similarly, consider the case by dividing the wiring layer165B (conductor layer B) into a main conductor portion165Ba and a lead-out conductor portion165Bb as illustrated in B inFIG.63. The main conductor portion165Ba is a portion provided to mainly shield the hot carrier light emission from the active element group167and suppress generation of the inductive noise, and has a larger area than the lead-out conductor portion165Bb. The lead-out conductor portion165Bb is a portion provided to mainly connect the main conductor portion165Ba and the pad401and supply a predetermined voltage such as the positive power supply (Vdd) to the main conductor portion165Ba. The length (width) of at least one of the X direction (first direction) or the Y direction (second direction) of the lead-out conductor portion165Bb is shorter (narrower) than the length (width) of the main conductor portion165Ba. A connecting portion between the main conductor portion165Ba and the lead-out conductor portion165Bb illustrated by the alternate long and short dash line in B inFIG.63is referred to as a joint portion.

Note that, in a case of collectively referring to the main conductor portion165Aa and the main conductor portion165Ba and in a case of collectively referring to the lead-out conductor portion165Ab and the lead-out conductor portion165Bb without distinguishing the wiring layer165A (conductor layer A) and the wiring layer165B (conductor layer B), they are respectively referred to as main conductor portion(s)165aand lead-out conductor portion(s)165b.

For facilitating the understanding, inFIG.63, the description has been given on the assumption that the lead-out conductor portion165Ab and the lead-out conductor portion165Bb are connected to the pad401or402. However, the lead-out conductor portion165Ab and the lead-out conductor portion165Bb are not necessarily connected to the pad401or402, and it is sufficient that they are connected to another wiring or electrode.

Furthermore,FIG.63illustrates an example in which the pads401and402have substantially the same shape and are arranged at substantially the same position. However, the configuration is not limited to the example. For example, the pads401and402may have different shapes or may be arranged at different positions. Furthermore, the pads401and402may have smaller dimensions than the example illustrated inFIG.63, may not be in contact with each other in the wiring layer165A, or may not be in contact with each other in the wiring layer165B, or a plurality of the pads401and402may be provided.

Moreover,FIG.63illustrates, but is not limited to, the example in which the end positions in the Y direction substantially match in the main conductor portion165Aa and the lead-out conductor portion165Ab. For example, the main conductor portion165Aa and the lead-out conductor portion165Ab may be configured such that the end positions do not match. Similarly,FIG.63illustrates, but is not limited to, the example in which the end positions in the Y direction substantially match in the main conductor portion165Ba and the lead-out conductor portion165Bb. For example, the main conductor portion165Ba and the lead-out conductor portion165Bb may be configured such that the end positions do not match. The shapes and positions of the main conductor portions165aand the lead-out conductor portions165band the relationship between the pads401and402are similar in the configuration examples to be described below.

In the above-described first to thirteenth configuration examples, for the wiring layer165A, the main conductor portion165Aa and the lead-out conductor portion165Ab are not particularly distinguished, and both the main conductor portion165Aa and the lead-out conductor portion165Ab have been formed using the same wiring pattern such as the planar conductor or the reticulated conductor.

As for the wiring layer165B, the main conductor portion165Ba and the lead-out conductor portion165Bb are not particularly distinguished, and both the main conductor portion165Ba and the lead-out conductor portion165Bb have been formed using the same wiring pattern such as the planar conductor or the reticulated conductor.

FIG.64illustrates examples in which the eleventh configuration example illustrated inFIG.36is applied to the wiring layer165A and the wiring layer165B, using different wiring patterns, as an example of the first to thirteenth configuration examples.

A inFIG.64illustrates the conductor layer A (wiring layer165A) and B inFIG.64illustrates the conductor layer B (wiring layer165B). In the coordinate system inFIG.64, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

In the eleventh configuration example illustrated inFIG.36, the reticulated conductor311of the conductor layer A illustrated in A inFIG.36is an example of the shape in which the conductor width WXA in the X direction is wider than the gap width GXA, whereas a reticulated conductor811of the conductor layer A in A inFIG.64has a shape in which the conductor width WXA in the X direction is narrower than the gap width GXA. Furthermore, in the Y direction, the reticulated conductor311illustrated in A inFIG.36is an example of the shape in which the conductor width WYA is narrower than the gap width GYA, whereas the reticulated conductor811of the conductor layer A in A inFIG.64has a shape in which the conductor width WYA is wider than the gap width GYA. The reticulated conductor311of the conductor layer A illustrated in A inFIG.36is an example of the shape in which the conductor width WYA and the conductor width WXA are substantially the same, whereas the reticulated conductor811of the conductor layer A in A inFIG.64has a shape in which the conductor width WYA is wider than the conductor width WXA. Then, in the reticulated conductor811of the conductor layer A in A inFIG.64, the same pattern is periodically arranged with the conductor period FXA in the X direction, and the same pattern is periodically arranged with the conductor period FYA in the Y direction, both in the main conductor portion165Aa and the lead-out conductor portion165Ab.

The conductor layer B has a shape in which a ratio of the gap width GXB to the conductor width WXB in the X direction (gap width GXB/conductor width WXB) of a reticulated conductor812of the conductor layer B in B inFIG.64is larger than the ratio of the gap width GXB to the conductor width WXB in the X direction (gap width GXB/conductor width WXB) of the reticulated conductor312of the conductor layer B illustrated in B inFIG.36. In other words, the reticulated conductor812of the conductor layer B in B inFIG.64has a larger difference between the conductor width WXB and the gap width GXB than the reticulated conductor312of the conductor layer B illustrated in B inFIG.36. In the Y direction, the ratio of the gap width GYB to the conductor width WYB (gap width GYB/conductor width WYB) of the reticulated conductor812of the conductor layer B in B inFIG.64is smaller than the ratio of the gap width GYB to the conductor width WYB (gap width GYB/conductor width WYB) of the reticulated conductor312of the conductor layer B illustrated in B inFIG.36. The reticulated conductor312of the conductor layer B illustrated in B inFIG.36is an example of the shape in which the conductor width WYB and the conductor width WXB are substantially the same, whereas the reticulated conductor812of the conductor layer B in B inFIG.64has a shape in which the conductor width WYB is wider than the conductor width WXB. Then, in the reticulated conductor812of the conductor layer B in B inFIG.64, the same pattern is periodically arranged with the conductor period FXB in the X direction, and the same pattern is periodically arranged with the conductor period FYB in the Y direction, both in the main conductor portion165Ba and the lead-out conductor portion165Bb.

C inFIG.64illustrates a state of the conductor layers A and B respectively illustrated in A and B inFIG.64, which are viewed from the conductor layer A side (photodiode141side). In C inFIG.64, regions of the conductor layer B, which overlap with and are hidden by the conductor layer A, are not illustrated.

As illustrated in C inFIG.64, in the case of the eleventh configuration example, the active element group167is covered with at least one of the conductor layer A or the conductor layer B, the hot carrier light emission from the active element group167can be shielded, and generation of the inductive noise can be suppressed.

As described above, the first to thirteenth configuration examples are examples in which the main conductor portion165Aa and the lead-out conductor portion165Ab are not particularly distinguished and are formed using the same wiring pattern in the wiring layer165A (conductor layer A), and the main conductor portion165Ba and the lead-out conductor portion165Bb are not particularly distinguished and are formed using the same wiring pattern in the wiring layer165B (conductor layer B).

However, since the lead-out conductor portion165bis formed with a smaller area than the main conductor portion165aand is also a portion where the current is concentrated, it is desirable to have a configuration in which the wiring resistance is small and the current is easily diffused in the main conductor portion165a.

Therefore, hereinafter, a configuration example in which the wiring pattern of the lead-out conductor portion165Ab of the wiring layer165A (conductor layer A) is made different from the wiring pattern of the main conductor portion165Aa, and also the wiring pattern of the lead-out conductor portion165Bb of the wiring layer165B (conductor layer B) is made different from the wiring pattern of the main conductor portion165Ba will be described.

Fourteenth Configuration Example

FIG.65illustrates a fourteenth configuration example of the conductor layers A and B. Note that A inFIG.65illustrates the conductor layer A, and B inFIG.65illustrates the conductor layer B. In the coordinate system inFIG.65, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

The conductor layer A in the fourteenth configuration example includes a reticulated conductor821Aa of the main conductor portion165Aa and a reticulated conductor821Ab of the lead-out conductor portion165Ab, as illustrated in A inFIG.65. The reticulated conductor821Aa and the reticulated conductor821Ab are, for example, wiring (Vss wiring) connected to GND or the negative power supply.

The reticulated conductor821Aa of the main conductor portion165Aa has a conductor width WXAa and a gap width GXAa and is configured such that the same pattern is periodically arranged with a conductor period FXAa in the X direction, and has a conductor width WYAa and a gap width GYAa and is configured such that the same pattern is periodically arranged with a conductor period FYAa in the Y direction. Therefore, the reticulated conductor821Aa has a shape including a repeating pattern in which a predetermined basic pattern is repeatedly arranged with a conductor period in at least one of the X direction or the Y direction.

The reticulated conductor821Ab of the lead-out conductor portion165Ab has a conductor width WXAb and a gap width GXAb and is configured such that the same pattern is periodically arranged with a conductor period FXAb in the X direction, and has a conductor width WYAb and a gap width GYAb in the Y direction. Therefore, the reticulated conductor821Ab has a shape including a repeating pattern in which a predetermined basic pattern is repeatedly arranged with a conductor period in at least one of the X direction or the Y direction.

Furthermore, when comparing the corresponding conductor widths WXA, gap widths GXA, conductor widths WYA, and gap widths GYA of the reticulated conductor821Aa of the main conductor portion165Aa and the reticulated conductor821Ab of the lead-out conductor portion165Ab, at least one widths have different values, and the repeating pattern of the reticulated conductor821Ab of the lead-out conductor portion165Ab is different from the repeating pattern of the reticulated conductor821Aa of the main conductor portion165Aa.

When comparing a total length LAa in the Y direction of the reticulated conductor821Aa of the main conductor portion165Aa with a total length LAb in the Y direction of the reticulated conductor821Ab of the lead-out conductor portion165Ab, the total length LAa of the reticulated conductor821Aa is longer than the total length LAb of the reticulated conductor821Ab. Therefore, the reticulated conductor821Ab of the lead-out conductor portion165Ab has a locally more concentrated current than the reticulated conductor821Aa of the main conductor portion165Aa, and thus has a larger voltage drop (particularly IR-Drop).

Here, the repeating pattern of the reticulated conductor821Ab of the lead-out conductor portion165Ab has a shape in which the current flows at least in a first direction, where the X direction toward the main conductor portion165Aa is the first direction, and the conductor width (wiring width) WYAb in a second direction (Y direction) orthogonal to the first direction is larger than the conductor width (wiring width) WYAa in the second direction of the reticulated conductor821Aa of the main conductor portion165Aa. As a result, the wiring resistance of the reticulated conductor821Ab of the lead-out conductor portion165Ab, which is the current concentration point, can be reduced, so that the voltage drop can be further improved. Note that the example in which the conductor width WYAb is larger than the conductor width WYAa has been described. However, the configuration is not limited to the example, and for example, the conductor width WXAb may be larger than the conductor width WXAa. As a result, the wiring resistance of the reticulated conductor821Ab can be reduced, so that the voltage drop can be further improved.

Furthermore, at least a part of the reticulated conductor821Aa of the main conductor portion165Aa has a pattern (shape) in which the current is more likely to flow in the Y direction (second direction) than in the X direction (first direction). Specifically, the wiring resistance is made smaller in the Y direction than in the X direction as at least one of the wiring widths (conductor width WXAa and conductor width WYAa) or the wiring gaps (gap width GXAa and gap width GYAa) is different. As a result, the current is easily diffused in the Y direction in the main conductor portion165Aa having the total length LAa longer than the total length LAb of the reticulated conductor821Ab, so that the electrodes concentrated around the joint portion between the main conductor portion165Aa and the lead-out conductor portion165Ab can be alleviated, and the inductive noise can be further improved.

The conductor layer B in the fourteenth configuration example includes a reticulated conductor822Ba of the main conductor portion165Ba and a reticulated conductor822Bb of the lead-out conductor portion165Bb, as illustrated in B inFIG.65. The reticulated conductor822Ba and the reticulated conductor822Bb are, for example, wiring (Vdd wiring) connected to the positive power supply.

The reticulated conductor822Ba of the main conductor portion165Ba has a conductor width WXBa and a gap width GXBa and is configured such that the same pattern is periodically arranged with a conductor period FXBa in the X direction, and has a conductor width WYBa and a gap width GYBa and is configured such that the same pattern is periodically arranged with a conductor period FYBa in the Y direction. Therefore, the reticulated conductor822Ba has a shape including a repeating pattern in which a predetermined basic pattern is repeatedly arranged with a conductor period in at least one of the X direction or the Y direction.

The reticulated conductor822Bb of the lead-out conductor portion165Bb has a conductor width WXBb and a gap width GXBb and is configured such that the same pattern is periodically arranged with a conductor period FXBb in the X direction, and has a conductor width WYBb and a gap width GYBb in the Y direction. Therefore, the reticulated conductor822Bb has a shape including a repeating pattern in which a predetermined basic pattern is repeatedly arranged with a conductor period in at least one of the X direction or the Y direction.

Furthermore, when comparing the corresponding conductor widths WXB, gap widths GXB, conductor widths WYB, and gap widths GYB of the reticulated conductor822Ba of the main conductor portion165Ba and the reticulated conductor822Bb of the lead-out conductor portion165Bb, at least one widths have different values, and the repeating pattern of the reticulated conductor822Bb of the lead-out conductor portion165Bb is different from the repeating pattern of the reticulated conductor822Ba of the main conductor portion165Ba.

When comparing a total length LBa in the Y direction of the reticulated conductor822Ba of the main conductor portion165Ba with a total length LBb in the Y direction of the reticulated conductor822Bb of the lead-out conductor portion165Bb, the total length LBa of the reticulated conductor822Ba is longer than the total length LBb of the reticulated conductor822Bb. Therefore, the reticulated conductor822Bb of the lead-out conductor portion165Bb has a locally more concentrated current than the reticulated conductor822Ba of the main conductor portion165Ba, and thus has a larger voltage drop (particularly IR-Drop).

Here, the repeating pattern of the reticulated conductor822Bb of the lead-out conductor portion165Bb has a shape in which the current flows at least in the first direction, where the X direction toward the main conductor portion165Ba is the first direction, and the conductor width (wiring width) WYBb in the second direction (Y direction) orthogonal to the first direction is larger than the conductor width (wiring width) WYBa in the second direction of the reticulated conductor822Ba of the main conductor portion165Ba. As a result, the wiring resistance of the reticulated conductor822Bb of the lead-out conductor portion165Bb, which is the current concentration point, can be reduced, so that the voltage drop can be further improved. Note that the example in which the conductor width WYBb is larger than the conductor width WYBa has been described. However, the configuration is not limited to the example, and for example, the conductor width WXBb may be larger than the conductor width WXBa. As a result, the wiring resistance of the reticulated conductor822Bb can be reduced, so that the voltage drop can be further improved.

Furthermore, at least a part of the reticulated conductor822Ba of the main conductor portion165Ba has a pattern (shape) in which the current is more likely to flow in the Y direction (second direction) than in the X direction (first direction). Specifically, the wiring resistance is made smaller in the Y direction than in the X direction as at least one of the wiring widths (conductor width WXBa and conductor width WYBa) or the wiring gaps (gap width GXBa and gap width GYBa) is different. As a result, the current is easily diffused in the Y direction in the main conductor portion165Ba having the total length LBa longer than the total length LBb of the reticulated conductor822Bb, so that the electrodes concentrated around the joint portion between the main conductor portion165Ba and the lead-out conductor portion165Bb can be alleviated, and the inductive noise can be further improved.

According to the fourteenth configuration example, in the wiring layer165A (conductor layer A), the repeating pattern of the reticulated conductor821Ab of the lead-out conductor portion165Ab is formed to be different from the repeating pattern of the reticulated conductor821Aa of the main conductor portion165Aa, and the main conductor portion165Aa and the lead-out conductor portion165Ab are electrically connected, whereby the wiring resistance of the lead-out conductor portion165Ab can be made small and the voltage drop can be further improved. In the wiring layer165B (conductor layer B), the repeating pattern of the reticulated conductor822Bb of the lead-out conductor portion165Bb is formed to be different from the repeating pattern of the reticulated conductor822Ba of the main conductor portion165Ba, and the main conductor portion165Ba and the lead-out conductor portion165Bb are electrically connected, whereby the wiring resistance of the lead-out conductor portion165Bb can be made small and the voltage drop can be further improved.

Furthermore, as illustrated in C inFIG.65, in the state where the conductor layer A and the conductor layer B are stacked, the active element group167is covered with at least one of the conductor layer A or the conductor layer B. That is, the main conductor portion165Aa of the wiring layer165A and the main conductor portion165Ba of the wiring layer165B form a light-shielding structure, and the lead-out conductor portion165Ab of the wiring layer165A and the lead-out conductor portion165Bb of the wiring layer165B form a light-shielding structure. Thereby, the hot carrier light emission from the active element group167can be shielded in the fourteenth configuration example similarly to the above-described first to thirteenth configuration examples.

Modification of Fourteenth Configuration Example

FIGS.66to68illustrate first to third modifications of the fourteenth configuration example. Note that since A to C inFIGS.66to68correspond to A to C inFIG.65and are given the same reference numerals, description of common parts will be omitted as appropriate, and different parts will be described.

In the fourteenth configuration example illustrated inFIG.65, the joint portion of the main conductor portion165Aa and the lead-out conductor portion165Ab is arranged on a side of a rectangle surrounding an outer periphery of the main conductor portion165Aa in the wiring layer165A (conductor layer A). However, the configuration is not limited thereto.

For example, as illustrated in A inFIG.66, the main conductor portion165Aa and the lead-out conductor portion165Ab may be connected so that the reticulated conductor821Ab of the lead-out conductor portion165Ab enters the inside of the rectangle surrounding the outer periphery of the main conductor portion165Aa.

Furthermore, for example, the main conductor portion165Aa and the lead-out conductor portion165Ab may be connected such that only a part of the plurality of wirings of the conductor width WYAb extending toward the main conductor portion165Aa of the reticulated conductor821Ab of the lead-out conductor portion165Ab enters the inside of the rectangle surrounding the outer periphery of the main conductor portion165Aa, as illustrated in A inFIG.67and in A inFIG.68. In the reticulated conductor821Ab of the lead-out conductor portion165Ab in A inFIG.67, the upper wiring of the two wirings of the conductor width WYAb extends to enter the inside of the rectangle surrounding the outer periphery of the main conductor portion165Aa. In the reticulated conductor821Ab of the lead-out conductor portion165Ab in A inFIG.68, the lower wiring extends to enter the inside of the rectangle surrounding the outer periphery of the main conductor portion165Aa.

The same applies to the wiring layer165B (conductor layer B). That is, in the fourteenth configuration example illustrated inFIG.65, the joint portion of the main conductor portion165Ba and the lead-out conductor portion165Bb is arranged on a side of a rectangle surrounding an outer periphery of the main conductor portion165Ba. However, the configuration is not limited thereto.

For example, as illustrated in B inFIG.66, the main conductor portion165Ba and the lead-out conductor portion165Bb may be connected so that the reticulated conductor822Bb of the lead-out conductor portion165Bb enters the inside of the rectangle surrounding the outer periphery of the main conductor portion165Ba.

Furthermore, for example, the main conductor portion165Ba and the lead-out conductor portion165Bb may be connected such that only a part of the plurality of wirings of the conductor width WYBb extending toward the main conductor portion165Ba of the reticulated conductor822Bb of the lead-out conductor portion165Bb enters the inside of the rectangle surrounding the outer periphery of the main conductor portion165Ba, as illustrated in B inFIG.67and in B inFIG.68. In the reticulated conductor822Bb of the lead-out conductor portion165Bb in B inFIG.67, the upper wiring of the two wirings of the conductor width WYBb extends to enter the inside of the rectangle surrounding the outer periphery of the main conductor portion165Ba. In the reticulated conductor822Bb of the lead-out conductor portion165Bb in B inFIG.68, the lower wiring extends to enter the inside of the rectangle surrounding the outer periphery of the main conductor portion165Ba.

As illustrated inFIGS.66to68, the shape of the portion connecting the main conductor portion165aand the lead-out conductor portion165bmay be complicatedly configured.

In the first to third modifications of the fourteenth configuration example illustrated inFIGS.66to68, the main conductor portion165Aa and the lead-out conductor portion165Ab are connected such that the reticulated conductor821Ab of the lead-out conductor portion165Ab enters the inside of the rectangle surrounding the outer periphery of the main conductor portion165Aa. However, the reticulated conductor821Aa of the main conductor portion165Aa may extend outside the rectangle surrounding the outer periphery of the main conductor portion165Aa and enter the lead-out conductor portion165Ab. Furthermore, the reticulated conductor822Ba of the main conductor portion165Ba may extend outside the rectangle surrounding the outer periphery of the main conductor portion165Ba and enter the lead-out conductor portion165Bb.

Fifteenth Configuration Example

FIG.69illustrates a fifteenth configuration example of the conductor layers A and B. Note that A inFIG.69illustrates the conductor layer A, and B inFIG.69illustrates the conductor layer B. In the coordinate system inFIG.69, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

The conductor layer A in the fifteenth configuration example includes a reticulated conductor831Aa of the main conductor portion165Aa and a reticulated conductor831Ab of the lead-out conductor portion165Ab, as illustrated in A inFIG.69. The reticulated conductor831Aa and the reticulated conductor831Ab are, for example, wiring (Vss wiring) connected to the GND or the negative power supply.

The reticulated conductor831Aa of the main conductor portion165Aa is similar to the reticulated conductor821Aa of the main conductor portion165Aa in the fourteenth configuration example inFIG.65. Meanwhile, the reticulated conductor831Ab of the lead-out conductor portion165Ab is different from the reticulated conductor821Ab of the lead-out conductor portion165Ab in the fourteenth configuration example inFIG.65.

Specifically, the gap width GYAb in the Y direction of the reticulated conductor831Ab of the lead-out conductor portion165Ab is formed to be smaller than the gap width GYAa in the Y direction of the reticulated conductor831Aa of the main conductor portion165Aa. In the fourteenth configuration example illustrated inFIG.65, the gap width GYAb in the Y direction of the reticulated conductor821Ab of the lead-out conductor portion165Ab is the same as the gap width GYAa in the Y direction of the reticulated conductor821Aa of the main conductor portion165Aa.

By forming the gap width GYAb in the Y direction of the reticulated conductor831Ab of the lead-out conductor portion165Ab to be smaller than the gap width GYAa in the Y direction of the reticulated conductor831Aa of the main conductor portion165Aa, the wiring resistance of the reticulated conductor831Ab of the lead-out conductor portion165Ab, which is the current concentration point, can be reduced, so that the voltage drop can be further improved. Note that the description has been given using the example in which the gap width GYAb is smaller than the gap width GYAa. However, the configuration is not limited thereto, and for example, the gap width GXAb may be formed to be smaller than the gap width GXAa. As a result, the wiring resistance of the reticulated conductor831Ab can be reduced, so that the voltage drop can be further improved.

The conductor layer B in the fifteenth configuration example includes a reticulated conductor832Ba of the main conductor portion165Ba and a reticulated conductor832Bb of the lead-out conductor portion165Bb, as illustrated in B inFIG.69. The reticulated conductor832Ba and the reticulated conductor832Bb are, for example, wiring (Vdd wiring) connected to the positive power supply.

The reticulated conductor832Ba of the main conductor portion165Ba is similar to the reticulated conductor822Ba of the main conductor portion165Ba in the fourteenth configuration example inFIG.65. Meanwhile, the reticulated conductor832Bb of the lead-out conductor portion165Bb is different from the reticulated conductor822Bb of the lead-out conductor portion165Bb in the fourteenth configuration example inFIG.65.

Specifically, the gap width GYBb in the Y direction of the reticulated conductor832Bb of the lead-out conductor portion165Bb is formed to be smaller than the gap width GYBa in the Y direction of the reticulated conductor832Ba of the main conductor portion165Ba. In the fourteenth configuration example inFIG.65, the gap width GYBb in the Y direction of the reticulated conductor822Bb of the lead-out conductor portion165Bb is the same as the gap width GYBa in the second direction of the reticulated conductor822Ba of the main conductor portion165Ba.

By forming the gap width GYBb in the Y direction of the reticulated conductor832Bb of the lead-out conductor portion165Bb to be smaller than the gap width GYBa in the Y direction of the reticulated conductor832Ba of the main conductor portion165Ba, the wiring resistance of the reticulated conductor832Bb of the lead-out conductor portion165Bb, which is the current concentration point, can be reduced, so that the voltage drop can be further improved. Note that the description has been given using the example in which the gap width GYBb is smaller than the gap width GYBa. However, the configuration is not limited thereto, and for example, the gap width GXBb may be formed to be smaller than the gap width GXBa. As a result, the wiring resistance of the reticulated conductor832Bb can be reduced, so that the voltage drop can be further improved.

Furthermore, as illustrated in C inFIG.69, in the state where the conductor layer A and the conductor layer B are stacked, the active element group167is covered with at least one of the conductor layer A or the conductor layer B. That is, the main conductor portion165Aa of the wiring layer165A and the main conductor portion165Ba of the wiring layer165B form a light-shielding structure, and the lead-out conductor portion165Ab of the wiring layer165A and the lead-out conductor portion165Bb of the wiring layer165B form a light-shielding structure. Thereby, the hot carrier light emission from the active element group167can also be shielded in the fifteenth configuration example.

First Modification of Fifteenth Configuration Example

FIG.70illustrates a first modification of the fifteenth configuration example. Note that A inFIG.70illustrates the conductor layer A, and B inFIG.70illustrates the conductor layer B. C inFIG.70illustrates a state of the conductor layers A and B respectively illustrated in A and B inFIG.70, which are viewed from the conductor layer A side. In the coordinate system inFIG.70, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

The first modification of the fifteenth configuration example is different from the fifteenth configuration example illustrated inFIG.69in that all the gap widths GYAb in the Y direction of the lead-out conductor portion165Ab of the wiring layer165A are not uniform. Specifically, as illustrated in A inFIG.70, the reticulated conductor831Ab of the lead-out conductor portion165Ab of the wiring layer165A has two types of gap widths GYAb: a small gap width GYAb1 and a large gap width GYAb2.

Furthermore, the first modification of the fifteenth configuration example is different from the fifteenth configuration example illustrated inFIG.69in that all the gap widths GYBb in the Y direction of the lead-out conductor portion165Bb of the wiring layer165B are not uniform. Specifically, as illustrated in B inFIG.70, the reticulated conductor832Bb of the lead-out conductor portion165Bb of the wiring layer165B has two types of gap widths GYBb: a small gap width GYBb1 and a large gap width GYBb2.

Even in the first modification of the fifteenth configuration example, the lead-out conductor portion165Ab of the wiring layer165A and the lead-out conductor portion165Bb of the wiring layer165B form the light-shielding structure in the state where the conductor layer A and the conductor layer B are stacked, as illustrated in C inFIG.70.

Second Modification of Fifteenth Configuration Example

FIG.71illustrates a second modification of the fifteenth configuration example. Note that A inFIG.71illustrates the conductor layer A, and B inFIG.71illustrates the conductor layer B. C inFIG.71illustrates a state of the conductor layers A and B respectively illustrated in A and B inFIG.71, which are viewed from the conductor layer A side. In the coordinate system inFIG.71, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

The second modification of the fifteenth configuration example is different from the fifteenth configuration example illustrated inFIG.69in that all the conductor widths WYAb in the Y direction of the lead-out conductor portion165Ab of the wiring layer165A are not uniform. Specifically, as illustrated in A inFIG.71, the reticulated conductor831Ab of the lead-out conductor portion165Ab of the wiring layer165A has two types of conductor widths WYAb: a small conductor width WYAb1 and a large conductor width WYAb2.

Furthermore, the second modification of the fifteenth configuration example is different from the fifteenth configuration example illustrated inFIG.69in that all the conductor widths WYBb in the Y direction of the lead-out conductor portion165Bb of the wiring layer165B are not uniform. Specifically, as illustrated in B inFIG.71, the reticulated conductor832Bb of the lead-out conductor portion165Bb of the wiring layer165B has two types of conductor widths WYBb: a small conductor width WYBb1 and a large conductor width WYBb2.

Even in the second modification of the fifteenth configuration example, the lead-out conductor portion165Ab of the wiring layer165A and the lead-out conductor portion165Bb of the wiring layer165B form the light-shielding structure in the state where the conductor layer A and the conductor layer B are stacked, as illustrated in C inFIG.71.

As in the first modification and the second modification of the fifteenth configuration example, the gap width GYAb or the conductor width WYAb of the lead-out conductor portion165Ab of the wiring layer165A or the gap width GYBb or the conductor width WYBb of the lead-out conductor portion165Bb of the wiring layer165B is made non-uniform, so that the degree of freedom in wiring can be increased. Each conductor layer generally has a restriction on occupancy of a conductor region. However, since the wiring resistances of the lead-out conductor portions165Ab and165Bb can be minimized within the restriction on the occupancy due to the increase in the degree of freedom in wiring, the voltage drop can be further improved. Note that the description has been given using the example in which all the gap widths GYAb are not uniform, the example in which all the gap widths GYBb are not uniform, the example in which all the conductor widths WYAb are not uniform, and the case in which all the conductor widths WYBb are not uniform. However, the configuration is not limited to the examples. For example, the conductor layers may be configured such that all the gap widths GXAb in the X direction, all the gap widths GXBb in the X direction, all the conductor widths WXAb in the X direction, or all the conductor widths WXBb in the X direction are not uniform. Even in these cases, the degree of freedom in wiring can be increased, so that the voltage drop can be further improved for the similar reason as described above.

Sixteenth Configuration Example

FIG.72illustrates a sixteenth configuration example of the conductor layers A and B. Note that A inFIG.72illustrates the conductor layer A, and B inFIG.72illustrates the conductor layer B. In the coordinate system inFIG.72, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

Since the conductor layer A of the sixteenth configuration example illustrated in A inFIG.72is similar to the conductor layer A of the fourteenth configuration example illustrated inFIG.65, description thereof will be omitted.

The conductor layer B of the sixteenth configuration example illustrated in B inFIG.72has a configuration in which a relay conductor841is further added to the conductor layer B of the fourteenth configuration example illustrated inFIG.65. More specifically, the main conductor portion165Ba includes the reticulated conductor822Ba and a plurality of relay conductors841, and the lead-out conductor portion165Bb includes the reticulated conductor822Bb similar to the fourteenth configuration example.

In the main conductor portion165Ba, the relay conductor841is arranged in a rectangular gap region long in the Y direction other than the reticulated conductor822Ba and is electrically isolated from the reticulated conductor822Ba, and is connected to, for example, Vss wiring to which the reticulated conductor821Aa of the conductor layer A is connected. One or a plurality of relay conductors841is arranged in the gap region of the reticulated conductor822Ba. B inFIG.72illustrates an example in which a total of two relay conductors841are arranged in the gap region of the reticulated conductor822Ba in two-row one-column arrangement.

In B inFIG.72, the relay conductors841are arranged in only some gap regions of the reticulated conductor822Ba in the entire region of the main conductor portion165Ba.

However, the relay conductor841may be arranged in the gap regions of the entire region of the main conductor portion165Ba. Furthermore, in the conductor layer B of the sixteenth configuration example, the relay conductor841is not arranged in the gap region of the reticulated conductor822Bb of the lead-out conductor portion165Bb. However, the relay conductor841may be arranged in the gap region of the reticulated conductor822Bb.

First Modification of Sixteenth Configuration Example

FIG.73illustrates a first modification of the sixteenth configuration example.

In the first modification of the sixteenth configuration example inFIG.73, the relay conductor841is arranged in the gap regions of the entire region of the main conductor portion165Ba of the conductor layer B, and is arranged in the gap regions of the reticulated conductor822Bb of the lead-out conductor portion165Bb. Other configurations in the first modification inFIG.73are similar to those in the sixteenth configuration example illustrated inFIG.72.

Second Modification of Sixteenth Configuration Example

FIG.74illustrates a second modification of the sixteenth configuration example.

The second modification of the sixteenth configuration example inFIG.74is similar to the first modification in that the relay conductor841is arranged in the gap regions of the entire region of the main conductor portion165Ba of the conductor layer B. Meanwhile, the second modification of the sixteenth configuration example is different from the first modification in that a relay conductor842different from the relay conductor841is arranged in the gap regions of the reticulated conductor822Bb of the lead-out conductor portion165Bb. Other configurations in the second modification inFIG.74are similar to those in the sixteenth configuration example illustrated inFIG.72.

As in the second modification, the numbers and shapes of the relay conductors841arranged in the gap regions of the reticulated conductor822Ba of the main conductor portion165Ba and the relay conductors842arranged in the gap regions of the reticulated conductor822Bb of the lead-out conductor portion165Bb, of the conductor layer B may be different.

In the case where the relay conductor841is not arranged in the gap region of the reticulated conductor822Bb of the lead-out conductor portion165Bb, as in the conductor layer B of the sixteenth configuration example inFIG.72, the degree of freedom in wiring (reticulated conductor822Bb) can be increased. Each conductor layer generally has a restriction on occupancy of a conductor region. However, since the wiring resistance of the lead-out conductor portion165Bb can be minimized within the restriction on the occupancy due to the increase in the degree of freedom in wiring, the voltage drop can be further improved.

Meanwhile, in the case where the relay conductor841, the relay conductor842, or the like is arranged in the gap regions of the reticulated conductor822Bb of the lead-out conductor portion165Bb, and in a case where active elements such as MOS transistors and diodes are arranged in the region of the lead-out conductor portion165Bb or in upper and lower layers at the same plane positions as the lead-out conductor portion165Bb, the voltage drop can be further improved.

Furthermore, by making the numbers and shapes different between the relay conductor841arranged in the gap regions of the reticulated conductor822Ba of the main conductor portion165Ba and the relay conductor842arranged in the gap regions of the reticulated conductor822Bb of the lead-out conductor portion165Bb, of the conductor layer B, the occupancy in the conductor regions of each conductor layer can be maximized in the main conductor portion165Ba and the lead-out conductor portion165Bb. Therefore, the voltage drop can be further improved as the wiring resistance is made small.

Note that the shape of the relay conductor841is arbitrary, and a symmetric circle or polygon such as rotational symmetry or mirror plane symmetry is desirable. The relay conductor841can be arranged in a center of or at any other position of the gap region of the reticulated conductor822Ba. The relay conductor841may be connected to a conductor layer as Vss wiring different from the conductor layer A. The relay conductor841may be connected to a conductor layer as Vss wiring closer to the active element group167than the conductor layer B. The relay conductor841can be connected to a conductor layer different from the conductor layer A or to a conductor layer or the like closer to the active element group167than the conductor layer B via the conductor via (VIA) extending in the Z direction. The same applies to the relay conductor842.

The sixteenth configuration example inFIGS.72to74illustrates an example of arranging the relay conductor841or842in the gap regions of the reticulated conductors822Ba and822Bb of the conductor layer B. However, the same or different relay conductors may be arranged in the gap regions of the reticulated conductors821Aa and821Ab of the conductor layer A.

Seventeenth Configuration Example

FIG.75illustrates a seventeenth configuration example of the conductor layers A and B. Note that A inFIG.75illustrates the conductor layer A, and B inFIG.75illustrates the conductor layer B. In the coordinate system inFIG.75, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

When comparing the conductor layer A in the seventeenth configuration example illustrated in A inFIG.75with the conductor layer A of the fourteenth configuration example illustrated in A inFIG.65, the shape of a reticulated conductor851Aa of the main conductor portion165Aa and the shape of a reticulated conductor851Ab of the lead-out conductor portion165Ab are different.

In other words, the gap region of the reticulated conductor821Aa in the fourteenth configuration example in A inFIG.65has the vertically long rectangular shape, whereas the gap region of the reticulated conductor851Aa in the seventeenth configuration example in A inFIG.75has a horizontally long rectangular shape. Furthermore, the gap region of the reticulated conductor821Ab in A inFIG.65has the vertically long rectangular shape, whereas the gap region of the reticulated conductor851Ab in A inFIG.75has a horizontally long rectangular shape.

The reticulated conductor851Ab of the lead-out conductor portion165Ab in A inFIG.75is common to the reticulated conductor821Ab in the fourteenth configuration example in A inFIG.65in that the current more easily flows in the X direction (first direction) toward the main conductor portion165Aa than in the Y direction (second direction) orthogonal to the X direction.

Meanwhile, the reticulated conductor851Aa of the main conductor portion165Aa in A inFIG.75has a shape in which the current more easily flows in the X direction than in the Y direction, whereas the reticulated conductor821Aa of the main conductor portion165Aa in the fourteenth configuration example in A inFIG.65has the shape in which the current more easily flows in the Y direction.

That is, the conductor layer A in the seventeenth configuration example illustrated in A inFIG.75is different from the conductor layer A of the fourteenth configuration example in A inFIG.65in the direction in which the current easily flows in the main conductor portion165Aa.

Furthermore, the main conductor portion165Aa of the conductor layer A in the seventeenth configuration example includes a reinforced conductor853reinforced such that the current more easily flows in the Y direction than in the X direction. A conductor width WXAc of the reinforced conductor853is desirably formed to be larger than one or both of the conductor width WXAa in the X direction and the conductor width WYAa in the Y direction of the reticulated conductor851Aa. The conductor width WXAc of the reinforced conductor853is formed to be larger than the conductor width WXAa in the X direction or the conductor width WYAa in the Y direction of the reticulated conductor851Aa, whichever is smaller. Note that, in the example inFIG.75, the position in the X direction at which the reinforced conductor853is formed is a position closest to the lead-out conductor portion165Ab in the region of the main conductor portion165Aa. However, it is sufficient that the position is a position near the joint portion.

Since the reticulated conductor851Aa of the main conductor portion165Aa can be formed in the shape that allows the current to easily flow in the X direction, the layout can be created with a minimum number of repetitions of the basic pattern, which increases the degree of freedom in designing the wiring layout. Furthermore, the voltage drop can be further improved depending on arrangement of the active elements such as MOS transistors and diodes.

Then, by providing the reinforced conductor853reinforced such that the current can easily flow in the Y direction, the current can be easily diffused in the Y direction in the main conductor portion165Aa, so that the current concentration around the joint portion between the main conductor portion165Aa and the lead-out conductor portion165Ab can be alleviated. In a case where the current is locally concentrated, the inductive noise deteriorates due to the concentrated portion. However, since the current concentration can be reduced, the inductive noise can be further improved.

When comparing the conductor layer B in the seventeenth configuration example illustrated in B inFIG.75with the conductor layer B of the fourteenth configuration example illustrated in B inFIG.65, the shape of a reticulated conductor852Ba of the main conductor portion165Ba and the shape of a reticulated conductor852Bb of the lead-out conductor portion165Bb are different.

In other words, the gap region of the reticulated conductor822Ba in the fourteenth configuration example illustrated in B inFIG.65has the vertically long rectangular shape, whereas the gap region of the reticulated conductor852Ba in the seventeenth configuration example illustrated in B inFIG.75has a horizontally long rectangular shape. Furthermore, the gap region of the reticulated conductor822Bb in B inFIG.65has the vertically long rectangular shape, whereas the gap region of the reticulated conductor852Bb in B inFIG.75has a horizontally long rectangular shape.

The reticulated conductor852Bb of the lead-out conductor portion165Bb in B inFIG.75is common to the reticulated conductor822Bb in the fourteenth configuration example in B inFIG.65in that the current more easily flows in the X direction (first direction) toward the main conductor portion165Ba than in the Y direction (second direction) orthogonal to the X direction.

Meanwhile, the reticulated conductor852Ba of the main conductor portion165Ba in B inFIG.75has a shape in which the current more easily flows in the X direction than in the Y direction, whereas the reticulated conductor822Ba of the main conductor portion165Ba in the fourteenth configuration example in B inFIG.65has the shape in which the current more easily flows in the Y direction.

That is, the conductor layer B in the seventeenth configuration example illustrated in B inFIG.75is different from the conductor layer B of the fourteenth configuration example in B inFIG.65in the direction in which the current easily flows in the main conductor portion165Ba.

Furthermore, the main conductor portion165Ba of the conductor layer B in the seventeenth configuration example includes a reinforced conductor854reinforced such that the current more easily flows in the Y direction than in the X direction. A conductor width WXBc of the reinforced conductor854is desirably formed to be larger than one or both of the conductor width WXBa in the X direction and the conductor width WYBa in the Y direction of the reticulated conductor852Ba. The conductor width WXBc of the reinforced conductor854is formed to be larger than the conductor width WXBa in the X direction or the conductor width WYBa in the Y direction of the reticulated conductor852Ba, whichever is smaller. In the example inFIG.75, the position in the X direction at which the reinforced conductor854is formed is a position closest to the lead-out conductor portion165Bb in the region of the main conductor portion165Ba. However, it is sufficient that the position is a position near the joint portion.

As illustrated in C inFIG.75, the reinforced conductor853of the conductor layer A and the reinforced conductor854of the conductor layer B are formed at overlapping positions. In the state where the conductor layer A and the conductor layer B are stacked, the active element group167is covered with at least one of the conductor layer A or the conductor layer B. Therefore, the hot carrier light emission from the active element group167can be shielded even in the seventeenth configuration example. Note that, for example, in a case where light-shielding is not necessary near the reinforced conductor853or the reinforced conductor854, the reinforced conductor853and the reinforced conductor854may not be formed at overlapping positions. Furthermore, for example, at least one of the reinforced conductor853or the reinforced conductor854may not be provided depending on the current distribution of the main conductor portion165a.

Since the reticulated conductor852Ba of the main conductor portion165Ba can be formed in the shape that allows the current to easily flow in the X direction, the layout can be created with a minimum number of repetitions of the basic pattern, which increases the degree of freedom in designing the wiring layout. Furthermore, the voltage drop can be further improved depending on arrangement of the active elements such as MOS transistors and diodes.

Then, by providing the reinforced conductor854reinforced such that the current easily flows in the Y direction, the current can be easily diffused in the second direction in the main conductor portion165Ba, so that the current concentration around the joint portion between the main conductor portion165Ba and the lead-out conductor portion165Bb can be alleviated. In a case where the current is locally concentrated, the inductive noise deteriorates due to the concentrated portion. However, since the current concentration can be reduced, the inductive noise can be further improved.

Moreover, the conductor layer B in the seventeenth configuration example illustrated in B inFIG.75is different from the conductor layer B of the fourteenth configuration example in B inFIG.65in that a relay conductor855is arranged in at least some gap regions of the reticulated conductor852Ba of the main conductor portion165Ba. The relay conductor855may be or may not be arranged.

First Modification of Seventeenth Configuration Example

FIG.76illustrates a first modification of the seventeenth configuration example.

The first modification of the seventeenth configuration example is different from the conductor layer A of the seventeenth configuration example illustrated in A inFIG.75in that the reinforced conductor853of the conductor layer A illustrated in A inFIG.76is not formed over the entire length in the Y direction of the main conductor portion165Aa but formed in a part in the Y direction. More specifically, in the first modification inFIG.76, the reinforced conductor853of the conductor layer A is formed at a position in the Y direction excluding the position of the joint portion in the Y direction. Other configurations of the conductor layer A in the first modification are similar to those of the conductor layer A in the seventeenth configuration example illustrated in A inFIG.75.

Similarly, the conductor layer B of the first modification of the seventeenth configuration example is different from the conductor layer B of the seventeenth configuration example illustrated in B inFIG.75in that the reinforced conductor854of the conductor layer B illustrated in B inFIG.76is not formed over the entire length in the Y direction of the main conductor portion165Ba but formed in a part in the Y direction. More specifically, in the first modification inFIG.76, the reinforced conductor854of the conductor layer B is formed at a position in the Y direction excluding the position of the joint portion in the Y direction. Other configurations of the conductor layer B in the first modification are similar to those of the conductor layer B in the seventeenth configuration example illustrated in A inFIG.75.

Second Modification of Seventeenth Configuration Example

FIG.77illustrates a second modification of the seventeenth configuration example.

The second modification of the seventeenth configuration example is different from the conductor layer A of the seventeenth configuration example illustrated in A inFIG.75in that the reinforced conductor853of the conductor layer A illustrated in A inFIG.77is not formed over the entire length in the Y direction of the main conductor portion165Aa but formed in a part in the Y direction. More specifically, in the second modification inFIG.77, the reinforced conductor853of the conductor layer A is formed only at the position in the Y direction of the joint portion. Other configurations of the conductor layer A in the second modification are similar to those of the conductor layer A in the seventeenth configuration example illustrated in A inFIG.75.

Similarly, the conductor layer B of the first modification of the seventeenth configuration example is different from the conductor layer B of the seventeenth configuration example illustrated in B inFIG.75in that the reinforced conductor854of the conductor layer B illustrated in B inFIG.77is not formed over the entire length in the Y direction of the main conductor portion165Ba but formed in a part in the Y direction. More specifically, in the second modification inFIG.77, the reinforced conductor854of the conductor layer B is formed only at the position in the Y direction of the joint portion. Other configurations of the conductor layer B in the second modification are similar to those of the conductor layer B in the seventeenth configuration example illustrated in A inFIG.75.

As in the first modification and the second modification of the seventeenth configuration example, the reinforced conductor853of the conductor layer A and the reinforced conductor854of the conductor layer B are not necessarily formed over the entire length in the Y direction of the main conductor portion165Aa, and may be formed in a region in the Y direction of a predetermined part.

Eighteenth Configuration Example

FIG.78illustrates an eighteenth configuration example of the conductor layers A and B. Note that A inFIG.78illustrates the conductor layer A, and B inFIG.78illustrates the conductor layer B. C inFIG.78illustrates a state of the conductor layers A and B respectively illustrated in A and B inFIG.78, which are viewed from the conductor layer A side. In the coordinate system inFIG.78, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

The eighteenth configuration example illustrated inFIG.78has a configuration in which a part of the seventeenth configuration example illustrated inFIG.75is changed. Note that, inFIG.78, a portion corresponding toFIG.75is given the same reference numeral and description thereof is omitted as appropriate.

The conductor layer A of the eighteenth configuration example illustrated in A inFIG.78is common to the seventeenth configuration example illustrated inFIG.75in including the reticulated conductor851Aa having the shape in which the current easily flows in the X direction and the reinforced conductor853reinforced such that the current easily flows in the Y direction.

Meanwhile, the conductor layer A in the eighteenth configuration example is different from that in the seventeenth configuration example illustrated inFIG.75in further including a reinforced conductor856reinforced such that the current more easily flows in the X direction than in the Y direction. A conductor width WYAc of the reinforced conductor856is desirably formed to be larger than one or both of the conductor width WXAa in the X direction and the conductor width WYAa in the Y direction of the reticulated conductor851Aa. The conductor width WYAc of the reinforced conductor856is formed to be larger than the conductor width WXAa in the X direction or the conductor width WYAa in the Y direction of the reticulated conductor851Aa, whichever is smaller. A plurality of the reinforced conductors856may be arranged in a region of the main conductor portion165Aa at predetermined intervals in the Y direction or one reinforced conductor856may be arranged at a predetermined position in the Y direction.

By providing the reinforced conductor856reinforced such that the current can easily flow in the X direction, the current can easily flow not only in the Y direction by the reinforced conductor853but also in the X direction, and the current concentration around the joint portion between the main conductor portion165Aa and the lead-out conductor portion165Ab can be alleviated. In a case where the current is locally concentrated, the inductive noise deteriorates due to the concentrated portion. However, since the current concentration can be reduced, the inductive noise can be further improved.

The conductor layer B of the eighteenth configuration example illustrated in B inFIG.78is common to the seventeenth configuration example illustrated inFIG.75in including the reticulated conductor852Ba having the shape in which the current easily flows in the X direction and the reinforced conductor854reinforced such that the current easily flows in the Y direction.

Meanwhile, the conductor layer B in the eighteenth configuration example is different from that in the seventeenth configuration example illustrated inFIG.75in further including a reinforced conductor857reinforced such that the current more easily flows in the X direction than in the Y direction. A conductor width WYBc of the reinforced conductor857is desirably formed to be larger than one or both of the conductor width WXBa in the X direction and the conductor width WYBa in the Y direction of the reticulated conductor852Ba. The conductor width WYBc of the reinforced conductor857is formed to be larger than the conductor width WXBa in the X direction or the conductor width WYBa in the Y direction of the reticulated conductor852Ba, whichever is smaller. A plurality of the reinforced conductors857may be arranged in a region of the main conductor portion165Ba at predetermined intervals in the Y direction or one reinforced conductor857may be arranged at a predetermined position in the Y direction.

As illustrated in C inFIG.78, the reinforced conductor856of the conductor layer A and the reinforced conductor857of the conductor layer B are formed at overlapping positions. In the state where the conductor layer A and the conductor layer B are stacked, the active element group167is covered with at least one of the conductor layer A or the conductor layer B. Therefore, the hot carrier light emission from the active element group167can be shielded even in the eighteenth configuration example. Note that, for example, in a case where light-shielding is not necessary near the reinforced conductor856or the reinforced conductor857, the reinforced conductor856and the reinforced conductor857may not be formed at overlapping positions. Furthermore, for example, at least one of the reinforced conductor856or the reinforced conductor857may not be provided depending on the current distribution of the main conductor portion165a.

By providing a reinforced conductor857reinforced such that the current can easily flow in the X direction, the current can easily flow not only in the Y direction by the reinforced conductor854but also in the X direction, and the current concentration around the joint portion between the main conductor portion165Ba and the lead-out conductor portion165Bb can be alleviated. In a case where the current is locally concentrated, the inductive noise deteriorates due to the concentrated portion. However, since the current concentration can be reduced, the inductive noise can be further improved.

In the seventeenth configuration example inFIG.75, the configuration including the reinforced conductors853and854reinforced such that the current easily flows in the Y direction has been described. In the eighteenth configuration example inFIG.78, the configuration including the reinforced conductors856and857reinforced such that the current easily flows in the X direction in addition to the reinforced conductors853and854has been described.

Although not illustrated, as a modification of the seventeenth configuration example or the eighteenth configuration example, a configuration in which the conductor layer A does not include the reinforced conductor853and includes the reinforced conductor856, and the conductor layer B does not include the reinforced conductor854and includes the reinforced conductor857may be adopted. In other words, a configuration provided with only the reinforced conductors856and857as the reinforced conductors may be adopted.

By providing the reinforced conductor856reinforced such that the current easily flows in the X direction, the current can be easily diffused in the Y direction depending on the relationship of the wiring resistance even in the case of not including the reinforced conductor853, and the current concentration near the joint portion between the main conductor portion165Aa and the lead-out conductor portion165Ab can be alleviated. In a case where the current is locally concentrated, the inductive noise deteriorates due to the concentrated portion. However, since the current concentration can be reduced, the inductive noise can be further improved.

By providing the reinforced conductor857reinforced such that the current easily flows in the X direction, the current can be easily diffused in the Y direction depending on the relationship of the wiring resistance even in the case of not including the reinforced conductor854, and the current concentration near the joint portion between the main conductor portion165Ba and the lead-out conductor portion165Bb can be alleviated. In a case where the current is locally concentrated, the inductive noise deteriorates due to the concentrated portion. However, since the current concentration can be reduced, the inductive noise can be further improved.

Nineteenth Configuration Example

FIG.79illustrates a nineteenth configuration example of the conductor layers A and B. Note that A inFIG.79illustrates the conductor layer A, and B inFIG.79illustrates the conductor layer B. C inFIG.79illustrates a state of the conductor layers A and B respectively illustrated in A and B inFIG.79, which are viewed from the conductor layer A side. In the coordinate system inFIG.79, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

The nineteenth configuration example illustrated inFIG.79has a configuration in which a part of the seventeenth configuration example illustrated inFIG.75is changed. Note that, inFIG.79, a portion corresponding toFIG.75is given the same reference numeral and description thereof is omitted as appropriate.

The conductor layer A in the nineteenth configuration example illustrated in A inFIG.79is different in that the reinforced conductor853of the seventeenth configuration example illustrated inFIG.75is replaced with a reinforced conductor871and is common in the other points. The reinforced conductor871includes a plurality of wirings extending in the Y direction. The wirings constituting the reinforced conductor871are evenly spaced in the X direction with a gap width GXAd. The gap width GXAd is smaller than the gap width GXAa of the reticulated conductor851Aa of the main conductor portion165Aa.

The conductor layer B in the nineteenth configuration example illustrated in B inFIG.79is different in that the reinforced conductor854of the seventeenth configuration example illustrated inFIG.75is replaced with a reinforced conductor872and is common in the other points. The reinforced conductor872includes a plurality of wirings extending in the Y direction. The wirings constituting the reinforced conductor872are evenly spaced in the X direction with a gap width GXBd. The gap width GXBd is smaller than the gap width GXBa of the reticulated conductor852Ba of the main conductor portion165Ba.

As illustrated in C inFIG.79, the reinforced conductor871of the conductor layer A and the reinforced conductor872of the conductor layer B are formed at overlapping positions. In the state where the conductor layer A and the conductor layer B are stacked, the active element group167is covered with at least one of the conductor layer A or the conductor layer B. Therefore, the hot carrier light emission from the active element group167can be shielded even in the nineteenth configuration example. Note that, for example, in a case where light-shielding is not necessary near the reinforced conductor871or the reinforced conductor872, the reinforced conductor871and the reinforced conductor872may not be formed at overlapping positions. Furthermore, for example, at least one of the reinforced conductor871or the reinforced conductor872may not be provided depending on the current distribution of the main conductor portion165a.

Modifications of Nineteenth Configuration Example

FIG.80illustrates a modification of the nineteenth configuration example.

In the nineteenth configuration example illustrated inFIG.79, the plurality of wirings constituting the reinforced conductor871of the conductor layer A has been evenly spaced in the X direction with the gap width GXAd. A plurality of wirings constituting the reinforced conductor872of the conductor layer B has been evenly spaced in the X direction with the gap width GXAd.

In contrast, inFIG.80as the modification of the nineteenth configuration example, each gap width GXAd of adjacent wirings is different among the plurality of wirings constituting the reinforced conductor871of the conductor layer A. At least one of the gap widths GXAd is smaller than the gap width GXAa of the reticulated conductor851Aa of the main conductor portion165Aa. In the plurality of wirings constituting the reinforced conductor872of the conductor layer B, the gap widths GXBd of adjacent wirings are different. At least one of the gap widths GXBd is smaller than the gap width GXBa of the reticulated conductor852Ba of the main conductor portion165Ba.

Note that, in the example inFIG.80, the plurality of gap widths GXAd and gap widths GXBd is formed to be gradually shortened from the left side. However, the configuration is not limited thereto, and the plurality of gap widths may be formed to be gradually shortened from the right side or may be random widths.

As described above, the modification of the nineteenth configuration example inFIG.80is similar to the nineteenth configuration example illustrated inFIG.79except that the gap widths GXAd and GXBd are not uniform and are modulated.

The reinforced conductor871of the conductor layer A and the reinforced conductor872of the conductor layer B can be configured using a plurality of wirings arranged with the predetermined gap width GXAd or GXBd, as in the nineteenth configuration example and the modification illustrated inFIGS.79and80.

By providing the reinforced conductors871and872reinforced such that the current can easily flow in the Y direction, the current can be easily diffused in the Y direction, so that the current concentration around the joint portion can be alleviated. In a case where the current is locally concentrated, the inductive noise deteriorates due to the concentrated portion. However, since the current concentration can be reduced, the inductive noise can be further improved. In the nineteenth configuration example and its modification illustrated inFIGS.79and80, the configuration including at least the gap width smaller than the gap width GXAa or the gap width GXBa in the X direction, and including the reinforced conductors871and872reinforced such that the current easily flows in the Y direction has been described. However, the configuration is not limited thereto. For example, although not illustrated, a configuration including at least a gap width smaller than the gap width GYAa or the gap width GYBa in the Y direction and including a reinforced conductor reinforced such that the current easily flows in the X direction similarly to the eighteenth configuration example inFIG.78may be adopted. Furthermore, any of the configuration including the reinforced conductor reinforced such that the current easily flows in the X direction, the configuration including the reinforced conductor reinforced such that the current easily flows in the Y direction, or a configuration including both the reinforced conductor reinforced such that the current easily flows in the X direction and the reinforced conductor reinforced such that the current easily flows in the Y direction may be adopted. Even in these cases, the current concentration can be alleviated depending on the relationship of the wiring resistance, so that the inductive noise can be further improved.

Twentieth Configuration Example

FIG.81illustrates a twentieth configuration example of the conductor layers A and B. Note that A inFIG.81illustrates the conductor layer A, and B inFIG.81illustrates the conductor layer B. C inFIG.81illustrates a state of the conductor layers A and B respectively illustrated in A and B inFIG.81, which are viewed from the conductor layer A side. In the coordinate system inFIG.81, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

The twentieth configuration example illustrated inFIG.81has a configuration in which a part of the sixteenth configuration example illustrated inFIG.72is changed. Note that, inFIG.81, a portion corresponding toFIG.72is given the same reference numeral and description thereof is omitted as appropriate.

The conductor layer A of the twentieth configuration example illustrated in A inFIG.81is common to the conductor layer A of the sixteenth configuration example illustrated inFIG.72in that the main conductor portion165Aa includes the reticulated conductor821Aa. Meanwhile, the conductor layer A of the twentieth configuration example is different from the conductor layer A of the sixteenth configuration example illustrated inFIG.72in that the lead-out conductor portion165Ab includes a reticulated conductor881Ab different from the reticulated conductor821Ab.

The conductor layer B of the twentieth configuration example illustrated in B inFIG.81is common to the conductor layer B of the sixteenth configuration example illustrated inFIG.72in that the main conductor portion165Ba includes the reticulated conductor822Ba and the relay conductor841arranged in the gap region. The conductor layer B of the twentieth configuration example is different from the conductor layer B of the sixteenth configuration example illustrated inFIG.72in that the lead-out conductor portion165Bb includes a reticulated conductor882Bb different from the reticulated conductor822Bb.

That is, the twentieth configuration example is different in the shape of the repeating pattern of the lead-out conductor portion165bfrom the sixteenth configuration example illustrated inFIG.72.

As illustrated in C inFIG.81, some regions of the lead-out conductor portion165bare open regions in the state where the conductor layer A and the conductor layer B are stacked.

As described above, it is not necessary to adopt a light-shielding structure in the entire region of the conductor layer A and the conductor layer B, and a region where the active elements such as MOS transistors and diodes are not arranged may not be shielded.

The twentieth configuration example inFIG.81has the configuration in which some regions of the lead-out conductor portions165bof the conductor layer A and the conductor layer B are not shielded. However, a configuration in which some regions of the main conductor portions165aof the conductor layer A and the conductor layer B are not shielded may be adopted. By not adopting the light-shielding structure for the regions where shielding is not required, the degree of freedom in designing the wiring layout further increases, whereby a wiring pattern that further improves the inductive noise and further improves the voltage drop can be adopted.

Twenty-First Configuration Example

The above-described fourteenth to twentieth configuration examples are the examples in which the conductor layers of the lead-out conductor portion165bconnected to the main conductor portion165aare the reticulated conductors.

However, the conductor layer of the lead-out conductor portion165bis not limited to the reticulated conductor, and may be configured by a planar conductor or a linear conductor similarly to the main conductor portion165a.

In the following twenty-first to twenty-fourth configuration examples, configuration examples in which the conductor layer of the lead-out conductor portion165bis formed using a planar conductor or a linear conductor will be described.

FIG.82illustrates a twenty-first configuration example of the conductor layers A and B. Note that A inFIG.82illustrates the conductor layer A, and B inFIG.81illustrates the conductor layer B. C inFIG.82illustrates a state of the conductor layers A and B respectively illustrated in A and B inFIG.82, which are viewed from the conductor layer A side. In the coordinate system inFIG.82, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

The twenty-first configuration example illustrated inFIG.82has a configuration in which the conductor layer of the lead-out conductor portion165bof the sixteenth configuration example illustrated inFIG.72is changed. Note that, inFIG.82, a portion corresponding toFIG.72is given the same reference numeral and description thereof is omitted as appropriate.

A linear conductor891Ab long in the X direction is periodically arranged in the Y direction with a conductor period FYAb instead of the reticulated conductor821Ab of the sixteenth configuration example, in the lead-out conductor portion165Ab of the conductor layer A of the twenty-first configuration example illustrated in A inFIG.82. The conductor period FYAb is equal to the sum of the conductor width WYAb in the Y direction and the gap width GYAb in the Y direction (the conductor period FYAb=the conductor width WYAb in the Y direction+the gap width GYAb in the Y direction).

A linear conductor892Bb long in the X direction is periodically arranged in the Y direction with a conductor period FYBb instead of the reticulated conductor822Bb of the sixteenth configuration example, in the lead-out conductor portion165Bb of the conductor layer B of the twenty-first configuration example illustrated in B inFIG.82. The conductor period FYBb is equal to the sum of the conductor width WYBb in the Y direction and the gap width GYBb in the Y direction (the conductor period FYBb=the conductor width WYBb in the Y direction+the gap width GYBb in the Y direction).

As illustrated in C inFIG.82, in the state where the conductor layer A and the conductor layer B are stacked, the active element group167is covered with at least one of the conductor layer A or the conductor layer B. Therefore, the hot carrier light emission from the active element group167can be shielded even in the twenty-first configuration example.

Twenty-Second Configuration Example

FIG.83illustrates a twenty-second configuration example of the conductor layers A and B. Note that A inFIG.83illustrates the conductor layer A, and B inFIG.83illustrates the conductor layer B. C inFIG.83illustrates a state of the conductor layers A and B respectively illustrated in A and B inFIG.83, which are viewed from the conductor layer A side. In the coordinate system inFIG.83, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

The twenty-second configuration example illustrated inFIG.83has a configuration in which the conductor layer of the lead-out conductor portion165bof the sixteenth configuration example illustrated inFIG.72is changed. Note that, inFIG.83, a portion corresponding toFIG.72is given the same reference numeral and description thereof is omitted as appropriate.

A planar conductor901Ab is arranged instead of the reticulated conductor821Ab of the sixteenth configuration example, in the lead-out conductor portion165Ab of the conductor layer A of the twenty-second configuration example illustrated in A inFIG.83. The planar conductor901Ab has the conductor width WYAb in the Y direction.

A planar conductor902Bb is arranged instead of the reticulated conductor822Bb of the sixteenth configuration example, in the lead-out conductor portion165Bb of the conductor layer B of the twenty-second configuration example illustrated in B inFIG.83. The planar conductor902Bb has the conductor width WYBb in the Y direction.

As illustrated in C inFIG.83, in the state where the conductor layer A and the conductor layer B are stacked, the active element group167is covered with at least one of the conductor layer A or the conductor layer B. Therefore, the hot carrier light emission from the active element group167can be shielded even in the twenty-second configuration example.

Note that, in the twenty-second configuration example, the conductor layer B in A or B inFIG.84may be adopted instead of the conductor layer B illustrated in B inFIG.83.

The conductor layers B illustrated in A and B inFIG.84differ only in the lead-out conductor portion165bfrom the conductor layer B illustrated in B inFIG.83.

A linear conductor903Bb long in the X direction is periodically arranged in the Y direction with the conductor period FYBb instead of the planar conductor901Ab illustrated in B inFIG.83, in the lead-out conductor portion165Bb of the conductor layer B in A inFIG.84. Note that the conductor period FYBb=a conductor width WYBb in the Y direction+a gap width GYBb in the Y direction.

A reticulated conductor904Bb is provided instead of the planar conductor901Ab illustrated in B inFIG.83, in the lead-out conductor portion165Bb of the conductor layer B in B inFIG.84. The reticulated conductor904Bb has a conductor width WXBb and a gap width GXBb and is configured such that the same pattern is periodically arranged with a conductor period FXBb in the X direction, and has a conductor width WYBb and a gap width GYBb and is configured such that the same pattern is periodically arranged with a conductor period FYBb in the Y direction. Therefore, the reticulated conductor904Bb has a shape including a repeating pattern in which a predetermined basic pattern is repeatedly arranged with a conductor period in at least one of the X direction or the Y direction.

A plan view in a state where the conductor layer B in A or B inFIG.84is stacked with the conductor layer A illustrated in A inFIG.83is similar to C inFIG.83.

Twenty-Third Configuration Example

FIG.85illustrates a twenty-third configuration example of the conductor layers A and B. Note that A inFIG.85illustrates the conductor layer A, and B inFIG.85illustrates the conductor layer B. C inFIG.85illustrates a state of the conductor layers A and B respectively illustrated in A and B inFIG.85, which are viewed from the conductor layer A side. In the coordinate system inFIG.85, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

The twenty-third configuration example illustrated inFIG.85has a configuration in which the conductor layer of the lead-out conductor portion165bof the sixteenth configuration example illustrated inFIG.72is changed. Note that, inFIG.85, a portion corresponding toFIG.72is given the same reference numeral and description thereof is omitted as appropriate.

A linear conductor911Ab long in the X direction is periodically arranged in the Y direction with the conductor period FYAb and a linear conductor912Ab long in the X direction is periodically arranged in the Y direction with the conductor period FYAb, instead of the reticulated conductor821Ab of the sixteenth configuration example, in the lead-out conductor portion165Ab of the conductor layer A of the twenty-third configuration example illustrated in A inFIG.85. The linear conductor911Ab is, for example, wiring (Vdd wiring) connected to the positive power supply. The linear conductor912Ab is, for example, wiring (Vss wiring) connected to the GND or the negative power supply. The conductor period FYAb is equal to the sum of the conductor width WYAb in the Y direction and the gap width GYAb in the Y direction (the conductor period FYAb=the conductor width WYAb+the gap width GYAb).

A linear conductor913Bb long in the X direction is periodically arranged in the Y direction with the conductor period FYBb and a linear conductor914Bb long in the X direction is periodically arranged in the Y direction with the conductor period FYBb, instead of the reticulated conductor822Bb of the sixteenth configuration example, in the lead-out conductor portion165Bb of the conductor layer B of the twenty-third configuration example illustrated in B inFIG.85. The linear conductor913Bb is, for example, wiring (Vdd wiring) connected to the positive power supply. The linear conductor914Bb is, for example, wiring (Vss wiring) connected to the GND or the negative power supply. The conductor period FYBb is equal to the sum of the conductor width WYBb in the Y direction and the gap width GYBb in the Y direction (the conductor period FYBb=the conductor width WYBb+the gap width GYBb).

The linear conductor912Ab of the lead-out conductor portion165Ab of the conductor layer A is electrically connected to the reticulated conductor821Aa of the main conductor portion165Aa, and is electrically connected to the linear conductor914Bb of the lead-out conductor portion165Bb of the conductor layer B via the conductor via (VIA) extending in the Z direction, for example.

The linear conductor913Bb of the lead-out conductor portion165Bb of the conductor layer B is electrically connected to the reticulated conductor822Ba of the main conductor portion165Ba, and is electrically connected to the linear conductor911Ab of the lead-out conductor portion165Ab of the conductor layer A via the conductor via (VIA) extending in the Z direction, for example.

As illustrated in C inFIG.85, in the state where the conductor layer A and the conductor layer B are stacked, the active element group167is covered with at least one of the conductor layer A or the conductor layer B. Therefore, the hot carrier light emission from the active element group167can be shielded even in the twenty-first configuration example.

In the above-described fourteenth to twenty-second configuration examples, the Vdd wiring and the Vss wiring having different polarities are arranged to overlap on the same plane region in the lead-out conductor portion165b. However, as in the twenty-third configuration example inFIG.85, the Vdd wiring and the Vss wiring having different polarities may be shifted and arranged on different plane regions, and the GND, the negative power supply, and the positive power supply may be transmitted using both the conductor layer A and the conductor layer B.

Note that the linear conductor911Ab of the lead-out conductor portion165Ab of the conductor layer A may be used as dummy wiring without being electrically connected to the linear conductor913Bb of the lead-out conductor portion165Bb of the conductor layer B. The linear conductor914Bb of the lead-out conductor portion165Bb of the conductor layer B may be used as dummy wiring without being electrically connected to the linear conductor912Ab of the lead-out conductor portion165Ab of the conductor layer A.

Note thatFIG.85illustrates an example in which a group of linear conductors911Ab and a group of linear conductors912Ab are adjacently arranged. However, the configuration is not limited to the example. For example, a plurality of groups of linear conductors911Ab and a plurality of groups of linear conductors912Ab may be provided, and a group of linear conductors911Ab and a group of linear conductors912Ab may be alternately arranged.

Furthermore,FIG.85illustrates an example in which the linear conductor911Ab including a plurality of linear conductors and the linear conductor912Ab including a plurality of linear conductors are adjacently arranged. However, the configuration is not limited to the example. For example, one linear conductor911Ab and one linear conductor912Ab may be alternately arranged.

Furthermore,FIG.85illustrates an example in which a group of linear conductors913Bb and a group of linear conductors914Bb are adjacently arranged. However, the configuration is not limited to the example. For example, a plurality of groups of linear conductors913Bb and a plurality of groups of linear conductors914Bb may be provided, and a group of linear conductors913Bb and a group of linear conductors914Bb may be alternately arranged.

Furthermore,FIG.85illustrates an example in which the linear conductor913Bb including a plurality of linear conductors and the linear conductor914Bb including a plurality of linear conductors are adjacently arranged. However, the configuration is not limited to the example. For example, one linear conductor913Bb and one linear conductor914Bb may be alternately arranged.

Twenty-Fourth Configuration Example

FIG.86illustrates a twenty-fourth configuration example of the conductor layers A and B. Note that A inFIG.86illustrates the conductor layer A, and B inFIG.86illustrates the conductor layer B. C inFIG.86illustrates a state of the conductor layers A and B respectively illustrated in A and B inFIG.86, which are viewed from the conductor layer A side. In the coordinate system inFIG.86, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

The twenty-fourth configuration example illustrated inFIG.86has a configuration in which the conductor layer of the lead-out conductor portion165bof the sixteenth configuration example illustrated inFIG.72is changed. Note that, inFIG.86, a portion corresponding toFIG.72is given the same reference numeral and description thereof is omitted as appropriate.

A linear conductor921Ab long in the Y direction is periodically arranged in the X direction with the conductor period FXAb and a linear conductor922Ab long in the Y direction is periodically arranged in the X direction with the conductor period FXAb, instead of the reticulated conductor821Ab of the sixteenth configuration example, in the lead-out conductor portion165Ab of the conductor layer A of the twenty-fourth configuration example illustrated in A inFIG.86. The linear conductor921Ab is, for example, wiring (Vdd wiring) connected to the positive power supply. The linear conductor922Ab is, for example, wiring (Vss wiring) connected to the GND or the negative power supply. The conductor period FXAb is equal to the sum of the conductor width WXAb in the X direction and the gap width GXAb in the X direction (the conductor period FXAb=the conductor width WXAb+the gap width GXAb).

A linear conductor923Bb long in the Y direction is periodically arranged in the X direction with the conductor period FXBb and a linear conductor924Bb long in the Y direction is periodically arranged in the X direction with the conductor period FXBb, instead of the reticulated conductor822Bb of the sixteenth configuration example, in the lead-out conductor portion165Bb of the conductor layer B of the twenty-fourth configuration example illustrated in B inFIG.86. The linear conductor923Bb is, for example, wiring (Vdd wiring) connected to the positive power supply. The linear conductor924Bb is, for example, wiring (Vss wiring) connected to the GND or the negative power supply. The conductor period FXBb is equal to the sum of the conductor width WXBb in the X direction and the gap width GXBb in the X direction (the conductor period FXBb=the conductor width WXBb+the gap width GXBb).

The linear conductor922Ab of the lead-out conductor portion165Ab of the conductor layer A is electrically connected to the linear conductor924Bb of the lead-out conductor portion165Bb of the conductor layer B via, for example, the conductor via (VIA) extending in the Z direction, and is electrically connected to the reticulated conductor821Aa of the main conductor portion165Aa via the linear conductor924Bb.

That is, for example, the GND or the negative power supply is alternately transmitted in the linear conductor922Ab of the conductor layer A and in the linear conductor924Bb of the conductor layer B in the lead-out conductor portion165b, and reaches the reticulated conductor821Aa of the main conductor portion165Aa.

The linear conductor923Bb of the lead-out conductor portion165Bb of the conductor layer B is electrically connected to the linear conductor921Ab of the lead-out conductor portion165Ab of the conductor layer A via, for example, the conductor via (VIA) extending in the Z direction, and is electrically connected to the reticulated conductor822Ba of the main conductor portion165Ba via the linear conductor921Ab.

That is, for example, the positive power supply is alternately transmitted in the linear conductor921Ab of the conductor layer A and in the linear conductor923Bb of the conductor layer B in the lead-out conductor portion165band reaches the reticulated conductor822Ba of the main conductor portion165Ba.

As illustrated in C inFIG.86, in the state where the conductor layer A and the conductor layer B are stacked, the active element group167is covered with at least one of the conductor layer A or the conductor layer B. Therefore, the hot carrier light emission from the active element group167can be shielded even in the twenty-first configuration example.

In the above-described fourteenth to twenty-second configuration examples, the Vdd wiring and the Vss wiring having different polarities are arranged to overlap on the same plane region in the lead-out conductor portion165b. However, as in the twenty-fourth configuration example inFIG.86, the Vdd wiring and the Vss wiring having different polarities may be shifted and arranged on different plane regions, and the GND, the negative power supply, and the positive power supply may be transmitted using both the conductor layer A and the conductor layer B.

As described above, the conductor layer of the lead-out conductor portion165bis not limited to the reticulated conductor, and may be configured by a planar conductor or a linear conductor, as in the twenty-first to twenty-fourth configuration examples illustrated inFIGS.82to86. Furthermore, not only one layer of the conductor layer A or B but also two layers of the conductor layers A and B may be used.

With such a configuration, any of effects of satisfying the wiring layout restrictions, further improving the degree of freedom in designing the wiring layout, further improving the inductive noise, further improving the voltage drop, or the like can be exhibited.

Twenty-Fifth Configuration Example

FIG.87illustrates a twenty-fifth configuration example of the conductor layers A and B. Note that A inFIG.87illustrates the conductor layer A, and B inFIG.87illustrates the conductor layer B. C inFIG.87illustrates a state of the conductor layers A and B respectively illustrated in A and B inFIG.87, which are viewed from the conductor layer A side. In the coordinate system inFIG.87, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

The twenty-fifth configuration example illustrated inFIG.87has a configuration in which a part is added to the sixteenth configuration example illustrated inFIG.72. Note that, inFIG.86, a portion corresponding toFIG.72is given the same reference numeral and description thereof is omitted as appropriate.

In the conductor layer A of the twenty-fifth configuration example illustrated in A inFIG.87, a conductor941having a shape that optionally contains a repeating pattern different from the reticulated conductor821Aa and the reticulated conductor821Ab is added between the reticulated conductor821Aa of the main conductor portion165Aa and the reticulated conductor821Ab of the lead-out conductor portion165Ab in the sixteenth configuration example illustrated inFIG.72. Note that the conductor941desirably has a shape including the repeating pattern in order to efficiently design the wiring layout, but may have a shape not including the repeating pattern. Since the pattern of the conductor941can take any shape, the conductor941in A inFIG.87is represented by a planar shape without any particular specification. The conductor941is electrically connected to both the reticulated conductor821Aa and the reticulated conductor821Ab. In other words, the reticulated conductor821Aa of the main conductor portion165Aa and the reticulated conductor821Ab of the lead-out conductor portion165Ab are electrically connected via the conductor941.

In the conductor layer B of the twenty-fifth configuration example illustrated in B inFIG.87, a conductor942having a shape that optionally contains a repeating pattern different from the reticulated conductor822Ba and the reticulated conductor822Bb is added between the reticulated conductor822Ba of the main conductor portion165Ba and the reticulated conductor822Bb of the lead-out conductor portion165Bb in the sixteenth configuration example illustrated inFIG.72. Note that the conductor942desirably has a shape including the repeating pattern in order to efficiently design the wiring layout, but may have a shape not including the repeating pattern. Since the pattern of the conductor942can take any shape, the conductor942in B inFIG.87is represented by a planar shape without any particular specification. The conductor942is electrically connected to both the reticulated conductor822Ba and the reticulated conductor822Bb. In other words, the reticulated conductor822Ba of the main conductor portion165Ba and the reticulated conductor822Bb of the lead-out conductor portion165Bb are electrically connected via the conductor942.

According to the twenty-fifth configuration example, the reticulated conductor821Aa of the main conductor portion165Aa and the reticulated conductor821Ab of the lead-out conductor portion165Ab are connected via the predetermined conductor941in the conductor layer A, whereby the degree of freedom in designing the wiring layout can be further improved and the degree of freedom in the vicinity of pads can be particularly improved.

The reticulated conductor822Ba of the main conductor portion165Ba and the reticulated conductor822Bb of the lead-out conductor portion165Bb are connected via the predetermined conductor942in the conductor layer B, whereby the degree of freedom in designing the wiring layout can be further improved and the degree of freedom in the vicinity of pads can be particularly improved.

Twenty-Sixth Configuration Example

FIG.88illustrates a twenty-sixth configuration example of the conductor layers A and B. Note that A inFIG.88illustrates the conductor layer A, and B inFIG.88illustrates the conductor layer B. C inFIG.88illustrates a state of the conductor layers A and B respectively illustrated in A and B inFIG.88, which are viewed from the conductor layer A side. In the coordinate system inFIG.88, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

The twenty-sixth configuration example illustrated inFIG.88has a configuration in which a part of the twenty-fifth configuration example illustrated inFIG.87is changed. Note that, inFIG.86, a portion corresponding toFIG.87is given the same reference numeral and description thereof is omitted as appropriate.

The conductor layer A of the twenty-sixth configuration example illustrated in A inFIG.88includes the reticulated conductor821Aa similar to the twenty-fifth configuration example illustrated inFIG.87, in the main conductor portion165Aa. Furthermore, the conductor layer A of the twenty-sixth configuration example includes a plurality of the reticulated conductors821Ab and the conductors941similar to the twenty-fifth configuration example in the Y direction at predetermined intervals in the lead-out conductor portion165Ab. In other words, the conductor layer A of the twenty-sixth configuration example in A inFIG.88has a configuration in which a plurality of the reticulated conductors821Ab and the conductors941of the lead-out conductor portion165Ab of the twenty-fifth configuration example illustrated inFIG.87is provided in the Y direction at predetermined intervals. Note that all of the plurality of conductors941may be the same or may not be the same.

The conductor layer B of the twenty-sixth configuration example illustrated in B inFIG.88includes the reticulated conductor822Ba similar to the twenty-fifth configuration example illustrated inFIG.87, in the main conductor portion165Ba. Furthermore, the conductor layer B of the twenty-sixth configuration example includes a plurality of the reticulated conductors822Bb and the conductors942similar to the twenty-fifth configuration example in the Y direction at predetermined intervals in the lead-out conductor portion165Bb. In other words, the conductor layer B of the twenty-sixth configuration example in B inFIG.88has a configuration in which a plurality of the reticulated conductors822Bb and the conductors942of the lead-out conductor portion165Bb of the twenty-fifth configuration example illustrated inFIG.87is provided in the Y direction at predetermined intervals. Note that all of the plurality of conductors942may be the same or may not be the same.

With such a configuration, any of effects of satisfying the wiring layout restrictions, further improving the degree of freedom in designing the wiring layout, further improving the inductive noise, further improving the voltage drop, or the like can be exhibited.

Twenty-Seventh Configuration Example

FIG.89illustrates a twenty-seventh configuration example of the conductor layers A and B. Note that A inFIG.89illustrates the conductor layer A, and B inFIG.89illustrates the conductor layer B. C inFIG.89illustrates a state of the conductor layers A and B respectively illustrated in A and B inFIG.89, which are viewed from the conductor layer A side. In the coordinate system inFIG.89, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

The twenty-seventh configuration example illustrated inFIG.89has a configuration in which a part of the twenty-sixth configuration example illustrated inFIG.88is changed. Note that, inFIG.89, a portion corresponding toFIG.88is given the same reference numeral and description thereof is omitted as appropriate.

The main conductor portion165Aa of the conductor layer A of the twenty-seventh configuration example illustrated in A inFIG.89includes the reticulated conductor821Aa similar to the twenty-sixth configuration example illustrated inFIG.88. The lead-out conductor portion165Ab of the conductor layer A of the twenty-seventh configuration example includes a reticulated conductor951Ab and a reticulated conductor952Ab. The shapes of the reticulated conductor951Ab and the reticulated conductor952Ab are each having the conductor width WXAb and the gap width GXAb in the X direction and the conductor width WYAb and the gap width GYAb in the Y direction. Note that the reticulated conductor952Ab is, for example, wiring (Vdd wiring) connected to the positive power supply and the reticulated conductor951Ab is, for example, wiring (Vss wiring) connected to the GND or the negative power supply.

A conductor961having a shape that optionally contains a repeating pattern different from the reticulated conductor821Aa of the main conductor portion165Aa and the reticulated conductor951Ab of the lead-out conductor portion165Ab is arranged between the reticulated conductor821Aa and the reticulated conductor951Ab. A conductor962having a shape that optionally contains a repeating pattern different from the reticulated conductor821Aa of the main conductor portion165Aa and the reticulated conductor952Ab of the lead-out conductor portion165Ab is arranged between the reticulated conductor821Aa and the reticulated conductor952Ab. Note that the conductor961or962desirably has a shape including a repeating pattern in order to efficiently design the wiring layout, but may have a shape not including the repeating pattern. Since the pattern of the conductors961and962can take any shape, the conductors961and962in A inFIG.89are represented by a planar shape without any particular specification.

The main conductor portion165Ba of the conductor layer B of the twenty-seventh configuration example illustrated in B inFIG.89includes the reticulated conductor822Ba similar to the twenty-sixth configuration example illustrated inFIG.88. The lead-out conductor portion165Bb of the conductor layer B of the twenty-seventh configuration example includes a reticulated conductor953Bb and a reticulated conductor954Bb. The shapes of the reticulated conductor953Bb and the reticulated conductor954Bb are each including the conductor width WXBb and the gap width GXBb in the X direction and the conductor width WYBb and the gap width GYBb in the Y direction. Note that the reticulated conductor954Bb is, for example, wiring (Vdd wiring) connected to the positive power supply and the reticulated conductor953Bb is, for example, wiring (Vss wiring) connected to the GND or the negative power supply.

A conductor963having a shape that optionally contains a repeating pattern different from the reticulated conductor822Ba of the main conductor portion165Ba and the reticulated conductor953Bb of the lead-out conductor portion165Bb is arranged between the reticulated conductor822Ba and the reticulated conductor953Bb. A conductor964having a shape that optionally contains a repeating pattern different from the reticulated conductor822Ba of the main conductor portion165Ba and the reticulated conductor954Bb of the lead-out conductor portion165Bb is arranged between the reticulated conductor822Ba and the reticulated conductor954Bb. Note that the conductor963or964desirably has a shape including a repeating pattern in order to efficiently design the wiring layout, but may have a shape not including the repeating pattern. Since the pattern of the conductors963and964can take any shape, the conductors963and964in B inFIG.89are represented by a planar shape without any particular specification.

The conductor961of the conductor layer A is electrically connected to the reticulated conductor821Aa of the main conductor portion165Aa and at least one of the reticulated conductor951Ab or953Bb of the lead-out conductor portion165bdirectly or indirectly via, for example, a conductor that is at least a part of the conductor963. In other words, the reticulated conductor821Aa of the main conductor portion165Aa and at least one of the reticulated conductor951Ab or953Bb of the lead-out conductor portion165bare electrically connected via the conductor961. Furthermore, the reticulated conductor951Ab of the lead-out conductor portion165Ab is electrically connected to the reticulated conductor953Bb of the lead-out conductor portion165Bb of the conductor layer B via, for example, the conductor via (VIA) extending in the Z direction. The conductor961and the conductor963may also be electrically connected via, for example, a conductor via (VIA) extending in the Z direction.

The conductor964of the conductor layer B is electrically connected to the reticulated conductor822Ba of the main conductor portion165Ba and at least one of the reticulated conductor952Ab or954Bb of the lead-out conductor portion165bdirectly or indirectly via, for example, a conductor that is at least a part of the conductor962. In other words, the reticulated conductor822Ba of the main conductor portion165Ba and at least one of the reticulated conductor952Ab or954Bb of the lead-out conductor portion165bare electrically connected via the conductor964. Furthermore, the reticulated conductor952Ab of the lead-out conductor portion165Ab is electrically connected to the reticulated conductor954Bb of the lead-out conductor portion165Bb of the conductor layer B via, for example, the conductor via (VIA) extending in the Z direction. The conductor962and the conductor964may also be electrically connected via, for example, a conductor via (VIA) extending in the Z direction.

For example, in the twenty-sixth configuration example inFIG.88, when looking at the polarities of the conductor layer A and the conductor layer B at the same plane position of the main conductor portion165aand the lead-out conductor portion165b, the main conductor portion165Aa of the conductor layer A and the main conductor portion165Ba of the conductor layer B have different polarities between the Vss wiring and the Vdd wiring, and the lead-out conductor portion165Ab of the conductor layer A and the lead-out conductor portion165Bb of the conductor layer B also have different polarities.

In contrast, in the twenty-seventh configuration example inFIG.89, when looking at the polarities of the conductor layer A and the conductor layer B at the same plane position of the main conductor portion165aand the lead-out conductor portion165b, the main conductor portion165Aa of the conductor layer A and the main conductor portion165Ba of the conductor layer B have different polarities between the Vss wiring and the Vdd wiring, but the lead-out conductor portion165Ab of the conductor layer A and the lead-out conductor portion165Bb of the conductor layer B have the same polarity. With such a polarity arrangement, in the case where the upper and lower conductor layer A and conductor layer B are configured, the lead-out conductor portion165belectrically connected with the upper and lower conductor layer A and conductor layer B can be used as a pad (electrode).

According to the twenty-seventh configuration example, any of effects of satisfying the wiring layout restrictions, further improving the degree of freedom in designing the wiring layout, further improving the inductive noise, further improving the voltage drop, and the like can be exhibited.

Twenty-Eighth Configuration Example

FIG.90illustrates a twenty-eighth configuration example of the conductor layers A and B. Note that A inFIG.90illustrates the conductor layer A, and B inFIG.90illustrates the conductor layer B. C inFIG.90illustrates a state of the conductor layers A and B respectively illustrated in A and B inFIG.90, which are viewed from the conductor layer A side. In the coordinate system inFIG.90, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

The twenty-eighth configuration example illustrated inFIG.90has a configuration in which a part of the twenty-seventh configuration example illustrated inFIG.89is changed. Note that, inFIG.90, a portion corresponding toFIG.89is given the same reference numeral and description thereof is omitted as appropriate.

The twenty-eighth configuration example illustrated inFIG.90is different only in the shape of the lead-out conductor portion165Ab of the conductor layer A from the twenty-seventh configuration example inFIG.89and is common in the other points to the twenty-seventh configuration example inFIG.89.

Specifically, in the lead-out conductor portion165Ab of the conductor layer A in the twenty-seventh configuration example inFIG.89, the reticulated conductor951Ab and the reticulated conductor952Ab having the shapes with the conductor width WXAb and the gap width GXAb in the X direction and the conductor width WYAb and the gap width GYAb in the Y direction are formed.

In contrast, in the lead-out conductor portion165Ab of the conductor layer A in the twenty-eighth configuration example inFIG.90, a planar conductor971Ab and a planar conductor972Ab having shapes with the conductor width WXAb in the X direction and the conductor width WYAb in the Y direction are formed.

In other words, in the twenty-eighth configuration example inFIG.90, the lead-out conductor portion165Ab of the conductor layer A includes the planar conductor971Ab instead of the reticulated conductor951Ab in the twenty-seventh configuration example inFIG.89and the planar conductor972Ab instead of the reticulated conductor952Ab in the twenty-seventh configuration example inFIG.89.

The twenty-seventh configuration example inFIG.89is an example in which the shapes of the lead-out conductor portions165bof the upper and lower conductor layer A and conductor layer B are the same shapes. However, different shapes may be adopted as in the twenty-eighth configuration example inFIG.90.

Moreover, while the shape of the lead-out conductor portion165Ab of the conductor layer A is planar in the twenty-eighth configuration example inFIG.90, a light-shielding structure may be formed using a reticulated conductor973Ab of the conductor layer A in A inFIG.91and the reticulated conductor953Bb of the conductor layer B in B inFIG.90, and a light-shielding structure may be formed using a reticulated conductor974Ab of the conductor layer A in A inFIG.91and the reticulated conductor954Bb of the conductor layer B in B inFIG.90, even if the upper and lower layers have the same reticulated shape like the reticulated conductor973Ab and the reticulated conductor974Ab of the lead-out conductor portion165Ab of the conductor layer A illustrated in A inFIG.91. Moreover, the conductor width WXAb or the gap width GXAb in the X direction and the conductor width WYAb or the gap width GYAb in the Y direction may be substantially the same size as the reticulated conductor953Bb or the reticulated conductor954Bb of the lead-out conductor portion165Bb of the conductor layer B.

Alternatively, as in a reticulated conductor975Ab and a reticulated conductor976Ab of the lead-out conductor portion165Ab of the conductor layer A illustrated in B inFIG.91, the conductor width WXAb or the gap width GXAb in the X direction may be made smaller than the reticulated conductor953Bb or the reticulated conductor954Bb of the lead-out conductor portion165Bb of the conductor layer B in B inFIG.90. Moreover, a light-shielding structure may be formed using the reticulated conductor975Ab of the conductor layer A in B inFIG.91and the reticulated conductor953Bb of the conductor layer B in B inFIG.90, and a light-shielding structure may be formed using the reticulated conductor976Ab of the conductor layer A in B inFIG.91and the reticulated conductor954Bb of the conductor layer B in B inFIG.90. In addition, although not illustrated, the conductor width WYAb or the gap width GYAb in the Y direction of the lead-out conductor portion165Ab of the conductor layer A may be made smaller than the reticulated conductor953Bb or the reticulated conductor954Bb of the lead-out conductor portion165Bb of the conductor layer B, and the conductor width WXAb or the gap width GXAb in the X direction, or the conductor width WYAb or the gap width GYAb in the Y direction, of the lead-out conductor portion165Ab of the conductor layer A, may be made larger than the reticulated conductor953Bb or the reticulated conductor954Bb of the lead-out conductor portion165Bb of the conductor layer B.

A and B inFIG.91illustrate other configuration examples of the conductor layer A in the twenty-eighth configuration example inFIG.90.

Summary of Fourteenth to Twenty-Eighth Configuration Examples

In the fourteenth to twenty-eighth configuration examples illustrated inFIGS.65to90, the repeating patterns of the main conductor portion165aand the lead-out conductor portion165bare different patterns (shapes) both in the conductor layer A and the conductor layer B.

The conductor layer A (first conductor layer) includes the main conductor portion165Aa (first conductor portion) including a conductor having a shape in which a planar, linear, or reticulated repeating pattern (first basic pattern) is repeatedly arranged on the same plane in the X direction or the Y direction, and the lead-out conductor portion165Ab (fourth conductor portion) including a conductor having a shape in which a planar, linear, or reticulated repeating pattern (fourth basic pattern) is repeatedly arranged on the same plane in the X direction or the Y direction. Here, the repeating pattern of the conductor of the main conductor portion165Aa and the repeating pattern of the conductor of the lead-out conductor portion165Ab have different shapes, and a conductor having a pattern different from the above repeating patterns may be present between the conductor of the main conductor portion165Aa and the conductor of the lead-out conductor portion165Ab.

The conductor layer B (second conductor layer) includes the main conductor portion165Ba (second conductor portion) including a conductor having a shape in which a planar, linear, or reticulated repeating pattern (second basic pattern) is repeatedly arranged on the same plane in the X direction or the Y direction, and the lead-out conductor portion165Bb (third conductor portion) including a conductor having a shape in which the planar, linear, or reticulated repeating pattern (third basic pattern) is repeatedly arranged on the same plane in the X direction or the Y direction. Here, the repeating pattern of the conductor of the main conductor portion165Ba and the repeating pattern of the conductor of the lead-out conductor portion165Bb have different shapes, and a conductor having a pattern different from the above repeating patterns may be present between the conductor of the main conductor portion165Ba and the conductor of the lead-out conductor portion165Bb.

In each of the above configuration examples, the conductor described as the wiring (Vss wiring) connected to the GND or the negative power supply, for example, may be the wiring (Vdd wiring) connected to the positive power supply, for example. The conductor described as the wiring (Vdd wiring) connected to the positive power supply, for example, may be the wiring (Vss wiring) connected to the GND or the negative power supply, for example.

In each of the above-described configuration examples, the total length LAa in the Y direction of the conductor of the main conductor portion165Aa has been longer than the total length LAb in the Y direction of the conductor of the lead-out conductor portion165Ab. However, the total length LAa and the total length LAb may be the same or substantially the same, or the total length LAa may be shorter than the total length LAb.

Similarly, the total length LBa in the Y direction of the main conductor portion165Ba has been longer than the total length LBb in the Y direction of the lead-out conductor portion165Bb. However, the total length LBa and the total length LBb may be the same or substantially the same, or the total length LBa may be shorter than the total length LBb.

In each of the above-described configuration examples, as an example of the repeating patterns of the main conductor portion165Aa and the main conductor portion165Ba, a repeating pattern example in which the current easily flows in the X direction may be adopted for the configuration example using the repeating pattern in which the current easily flows in the Y direction than in the X direction, and on the contrary, a repeating pattern example in which the current easily flows in the Y direction may be adopted for the configuration example using the repeating pattern in which the current easily flows in the X direction than in the Y direction. Furthermore, a repeating pattern example in which the current easily flows in the X direction and Y direction to the same extent.

In each of the above-described configuration examples, the conductor patterns of the main conductor portion165Aa of the conductor layer A (wiring layer165A) and the main conductor portion165Ba of the conductor layer B (wiring layer165B) may be any of the patterns described in the first to thirteenth configuration examples. Note that some of the above-described configuration examples have been described using the example in which all the conductor periods, conductor widths, and gap widths are uniform. However, this is not the case. For example, the conductor period, the conductor width, and the gap width may be non-uniform, or the conductor period, the conductor width, and the gap width may be modulated depending on a position. Furthermore, some of the above-described configuration examples have been described using the example in which the conductor periods, conductor widths, gap widths, wiring shapes, wiring positions, the numbers of wirings, and the like are substantially the same in the Vdd wiring and the Vss wiring. However, this is not the case. For example, the Vdd wiring and the Vss wiring may have different conductor periods, different conductor widths, different gap widths, different wiring shapes, or different wiring positions. The wiring position may be shifted or misaligned, and the number of wirings may be different.

10. Connection Configuration Example with Pads

Next, the relationship between the conductor layers A and B and the pads will be described with reference toFIGS.92to108.

FIG.92is plan views illustrating the entire conductor layer A formed on the substrate.

As described above, the conductor layer A (wiring layer165A) includes the main conductor portion165Aa and the lead-out conductor portion165Ab.

In a case where the pads are separately provided from the conductor layer A, the lead-out conductor portion165Ab is provided at a position close to a pad1001, and connects the main conductor portion165Aa and the pad1001, as illustrated in A inFIG.92. Meanwhile, there are some cases where the lead-out conductor portion165Ab configures the pad1001, as illustrated in B inFIG.92.

The main conductor portion165Aa is formed in a main region of a substrate1000, for example, a central region of the substrate, with an area larger than the lead-out conductor portion165Ab, and shields the active elements such as MOMS transistors and diodes formed in a region of the main conductor portion165Aa or in another layer in the Z direction perpendicular to a plane of the region.

Note thatFIG.92illustrates an example of the arrangement and shape of the conductor layer A, and the arrangement and shape of the conductor layer A are not limited to this example. Therefore, the positions and areas in the substrate1000on which the main conductor portion165Aa, the lead-out conductor portion165Ab, and the pad1001are formed are arbitrary, and the active elements may not be formed in a region of the main conductor portion165Aa or the lead-out conductor portion165Ab or in another layer in the Z direction perpendicular to the plane of the region. The lead-out conductor portion165Ab may not be provided at the position near the pad1001. Furthermore, the arrangement of the lead-out conductor portion165Ab and the pad1001with respect to the main conductor portion165Aa may be sides on the Y direction side or may be both sides on the X direction side and the Y direction side, instead of the sides on the X direction side, of the four sides of the main conductor portion165Aa as inFIG.92. Moreover, the number of pads1001may be one or three or more instead of two on each side as inFIG.92.

FIG.92illustrates examples of the conductor layer A (wiring layer165A). However, the same applies to the conductor layer B (wiring layer165B).

With such a configuration, any of effects of satisfying the wiring layout restrictions, further improving the degree of freedom in designing the wiring layout, further improving the inductive noise, further improving the voltage drop, or the like can be exhibited.

InFIG.92, for example, whether the pad1001is an electrode (Vdd electrode) connected to the positive power supply or an electrode (Vss electrode) connected to the GND or the negative power supply has not been particularly distinguished. However, the arrangement of the pad1001when distinguished will be described below.

Fourth Arrangement Example of Pads

FIG.93illustrates a fourth arrangement example of pads.

A inFIG.93is a plan view illustrating an arrangement example of the conductor layer A (wiring layer165A) and pads1001sconnected to the conductor layer A.

B inFIG.93is a plan view illustrating an arrangement example of the conductor layer B (wiring layer165B) and pads1001dconnected to the conductor layer B.

C inFIG.93is a plan view of a state in which the conductor layers A and B and the pads1001sand1001drespectively illustrated in A and B inFIG.93are stacked.

InFIG.93, the pad1001srepresents, for example, the pad1001to which GND or a negative power supply (Vss) is supplied, and the pad1001drepresents, for example, the pad1001to which a positive power supply (Vdd) is supplied.

As illustrated in A inFIG.93, a plurality of the pads1001sis connected to a predetermined side of the rectangular main conductor portion165Aa at predetermined intervals via a conductor1011having a shape optionally including a predetermined repeating pattern. Each pad1001smay be configured by the lead-out conductor portion165Ab, as in the twenty-seventh configuration example illustrated inFIG.89, for example, or the conductor1011may be configured by the lead-out conductor portion165Ab. Furthermore, in the case where the pad1001sis the lead-out conductor portion165Ab, the conductor1011may be omitted or may be present.

As illustrated in B inFIG.93, a plurality of the pads1001dis connected to a predetermined side of the rectangular main conductor portion165Ba and to the same side as the side where the pads1001sare arranged in the conductor layer A at predetermined intervals via the conductor1012having a shape optionally including a predetermined repeating pattern. Each pad1001dmay be configured by the lead-out conductor portion165Bb, as in the twenty-seventh configuration example illustrated inFIG.89, for example, or the conductor1012may be configured by the lead-out conductor portion165Bb. Furthermore, in the case where the pad1001dis the lead-out conductor portion165Bb, the conductor1012may be omitted or may be present.

As illustrated in C inFIG.93, in the state where the conductor layers A and B are stacked, the arrangement of the pads1001sand the pads1001dis an alternate arrangement in which the pad1001sand the pad1001dare alternately arranged in the Y direction. In this case, as described with reference toFIGS.42to44, the magnetic field generated from each of the conductor layers A and B and the induced electromotive force based on the magnetic field can be effectively canceled, so that the inductive noise can be further improved. However, since the arrangement is not symmetrically arranged in the Y direction, in a case where the pads1001are arranged over a wide area, that is, in a case where the main conductor portion165Aa or165Ba, the lead-out conductor portion165Ab or165Bb, or the conductor1011or1012is longer in the arrangement direction of the pads1001(inFIG.93, the Y direction is longer than the X direction), there may be a magnetic field that cannot be canceled, and the induced electromotive force increases as the Victim conductor loop becomes larger and is accumulated, and the inductive noise may deteriorate.

Fifth Arrangement Example of Pads

FIG.94illustrates a fifth arrangement example of pads.

A inFIG.94is a plan view illustrating an arrangement example of the conductor layer A (wiring layer165A) and the pads1001sconnected to the conductor layer A.

B inFIG.94is a plan view illustrating an arrangement example of the conductor layer B (wiring layer165B) and the pads1001dconnected to the conductor layer B.

C inFIG.94is a plan view of a state in which the conductor layers A and B and the pads1001sand1001drespectively illustrated in A and B inFIG.94are stacked.

InFIG.94, the pad1001srepresents, for example, the pad1001to which GND or a negative power supply is supplied, and the pad1001drepresents, for example, the pad1001to which a positive power supply is supplied.

As illustrated in A inFIG.94, a plurality of the pads1001sis connected to a predetermined side of the rectangular main conductor portion165Aa at predetermined intervals via the conductor1011having a shape optionally including a predetermined repeating pattern. Each pad1001smay be configured by the lead-out conductor portion165Ab or the conductor1011may be configured by the lead-out conductor portion165Ab. Furthermore, in the case where the pad1001sis the lead-out conductor portion165Ab, the conductor1011may be omitted or may be present.

As illustrated in B inFIG.94, a plurality of the pads1001dis connected to a predetermined side of the rectangular main conductor portion165Ba and to the same side as the side where the pads1001sare arranged in the conductor layer A at predetermined intervals via the conductor1012having a shape optionally including a predetermined repeating pattern. Each pad1001dmay be configured by the lead-out conductor portion165Bb or the conductor1012may be configured by the lead-out conductor portion165Bb. Furthermore, in the case where the pad1001dis the lead-out conductor portion165Bb, the conductor1012may be omitted or may be present.

As illustrated in C inFIG.94, in the state where the conductor layers A and B are stacked, the arrangement of the pads1001sand1001dis a mirror-symmetrical arrangement in which a set of pads1001is folded back in the Y direction and sequentially arranged, where four consecutive pads1001sand1001din the Y direction are set as one set. In this case, as compared with the alternate arrangement illustrated inFIG.93, the magnetic field generated from each of the conductor layers A and B and the induced electromotive force based on the magnetic field can be more effectively canceled, so that the inductive noise can be further improved depending on the layout other than the pads.

Sixth Arrangement Example of Pads

FIG.95illustrates a sixth arrangement example of pads.

A inFIG.95is a plan view illustrating an arrangement example of the conductor layer A (wiring layer165A) and the pads1001sconnected to the conductor layer A.

B inFIG.95is a plan view illustrating an arrangement example of the conductor layer B (wiring layer165B) and the pads1001dconnected to the conductor layer B.

C inFIG.95is a plan view of a state in which the conductor layers A and B and the pads1001sand1001drespectively illustrated in A and B inFIG.95are stacked.

InFIG.95, the pad1001srepresents, for example, the pad1001to which GND or a negative power supply is supplied, and the pad1001drepresents, for example, the pad1001to which a positive power supply is supplied.

As illustrated in A inFIG.95, a plurality of the pads1001sis connected to a predetermined side of the rectangular main conductor portion165Aa at predetermined intervals via the conductor1011having a shape optionally including a predetermined repeating pattern. Each pad1001smay be configured by the lead-out conductor portion165Ab or the conductor1011may be configured by the lead-out conductor portion165Ab. Furthermore, in the case where the pad1001sis the lead-out conductor portion165Ab, the conductor1011may be omitted or may be present.

As illustrated in B inFIG.95, a plurality of the pads1001dis connected to a predetermined side of the rectangular main conductor portion165Ba and to the same side as the side where the pads1001sare arranged in the conductor layer A at predetermined intervals via the conductor1012having a shape optionally including a predetermined repeating pattern. Each pad1001dmay be configured by the lead-out conductor portion165Bb or the conductor1012may be configured by the lead-out conductor portion165Bb. Furthermore, in the case where the pad1001dis the lead-out conductor portion165Bb, the conductor1012may be omitted or may be present.

As illustrated in C inFIG.95, in the state where the conductor layers A and B are stacked, the arrangement of the pads1001sand1001dis a mirror-symmetrical arrangement in which a set of pads1001is folded back in the Y direction and sequentially arranged, where four consecutive pads1001sand1001din the Y direction are set as one set. Moreover, the four pads1001sand pads1001dthat constitute one set also have a mirror-symmetrical arrangement in which two of the four pads1001are folded back in the Y direction with reference to a center line in the Y direction. In the case of adopting such a two-stage configuration with a mirror arrangement, a range in which a residual magnetic field is accumulated is narrower than that of a one-stage mirror arrangement illustrated inFIG.94, the induced electromotive force is more effectively canceled, and the inductive noise can be further improved depending on the layout other than the pads.

Seventh Arrangement Example of Pads

FIG.96illustrates a seventh arrangement example of pads.

A inFIG.96is a plan view illustrating an arrangement example of the conductor layer A (wiring layer165A) and the pads1001sconnected to the conductor layer A.

B inFIG.96is a plan view illustrating an arrangement example of the conductor layer B (wiring layer165B) and the pads1001dconnected to the conductor layer B.

C inFIG.96is a plan view of a state in which the conductor layers A and B and the pads1001sand1001drespectively illustrated in A and B inFIG.96are stacked.

InFIG.96, the pad1001srepresents, for example, the pad1001to which GND or a negative power supply is supplied, and the pad1001drepresents, for example, the pad1001to which a positive power supply is supplied.

As illustrated in A inFIG.96, a plurality of the lead-out conductor portions165Ab is connected to a predetermined side of the rectangular main conductor portion165Aa, and a plurality of the pads1001sis connected to an outer peripheral portion of each of the lead-out conductor portions165Ab at predetermined intervals via the conductor1011having a shape optionally including a predetermined repeating pattern. The conductor1011may be omitted or may be present. Furthermore, the conductor1011may be located between the main conductor portion165Aa and the lead-out conductor portion165Ab.

As illustrated in B inFIG.96, a plurality of the lead-out conductor portions165Bb is connected to a predetermined side of the rectangular main conductor portion165Ba, and a plurality of the pads1001dis connected to the outer peripheral portion of each of the lead-out conductor portions165Bb at predetermined intervals via the conductor1012having a shape optionally including a predetermined repeating pattern. The conductor1012may be omitted or may be present. Furthermore, the conductor1012may be located between the main conductor portion165Ba and the lead-out conductor portion165Bb.

As illustrated in C inFIG.96, in the state where the conductor layers A and B are stacked, the arrangement of the pads1001sand the pads1001dis an alternate arrangement in which the pad1001sand the pad1001dare alternately arranged in the Y direction. In this case, the magnetic field generated from each of the conductor layers A and B and the induced electromotive force based on the magnetic field can be effectively canceled, so that the inductive noise can be further improved. However, since the arrangement is not symmetrically arranged in the Y direction, in a case where the pads1001are arranged over a wide area, that is, in a case where the main conductor portion165Aa or165Ba, the lead-out conductor portion165Ab or165Bb, or the conductor1011or1012is longer in the arrangement direction of the pads1001(inFIG.96, the Y direction is longer than the X direction), there may be a magnetic field that cannot be canceled, and the induced electromotive force increases as the Victim conductor loop becomes larger and is accumulated, and the inductive noise may deteriorate.

Eighth Arrangement Example of Pads

FIG.97illustrates an eighth arrangement example of pads.

A inFIG.97is a plan view illustrating an arrangement example of the conductor layer A (wiring layer165A) and the pads1001sconnected to the conductor layer A.

B inFIG.97is a plan view illustrating an arrangement example of the conductor layer B (wiring layer165B) and the pads1001dconnected to the conductor layer B.

C inFIG.97is a plan view of a state in which the conductor layers A and B and the pads1001sand1001drespectively illustrated in A and B inFIG.97are stacked.

InFIG.97, the pad1001srepresents, for example, the pad1001to which GND or a negative power supply is supplied, and the pad1001drepresents, for example, the pad1001to which a positive power supply is supplied.

As illustrated in A inFIG.97, a plurality of the lead-out conductor portions165Ab is connected to a predetermined side of the rectangular main conductor portion165Aa, and a plurality of the pads1001sis connected to the outer peripheral portion of each of the lead-out conductor portions165Ab at predetermined intervals via the conductor1011having a shape optionally including a predetermined repeating pattern. The conductor1011may be omitted or may be present. Furthermore, the conductor1011may be located between the main conductor portion165Aa and the lead-out conductor portion165Ab.

As illustrated in B inFIG.97, a plurality of the lead-out conductor portions165Bb is connected to a predetermined side of the rectangular main conductor portion165Ba, and a plurality of the pads1001dis connected to the outer peripheral portion of each of the lead-out conductor portions165Bb at predetermined intervals via the conductor1012having a shape optionally including a predetermined repeating pattern. The conductor1012may be omitted or may be present. Furthermore, the conductor1012may be located between the main conductor portion165Ba and the lead-out conductor portion165Bb.

As illustrated in C inFIG.97, in the state where the conductor layers A and B are stacked, the arrangement of the pads1001sand1001dis a mirror-symmetrical arrangement in which a set of pads1001is folded back in the Y direction and sequentially arranged, where four consecutive pads1001sand1001din the Y direction are set as one set. In this case, as compared with the alternate arrangement illustrated inFIG.96, the magnetic field generated from each of the conductor layers A and B and the induced electromotive force based on the magnetic field can be more effectively canceled, so that the inductive noise can be further improved depending on the layout other than the pads.

Ninth Arrangement Example of Pads

FIG.98illustrates a ninth arrangement example of pads.

A inFIG.98is a plan view illustrating an arrangement example of the conductor layer A (wiring layer165A) and the pads1001sconnected to the conductor layer A.

B inFIG.98is a plan view illustrating an arrangement example of the conductor layer B (wiring layer165B) and the pads1001dconnected to the conductor layer B.

C inFIG.98is a plan view of a state in which the conductor layers A and B and the pads1001sand1001drespectively illustrated in A and B inFIG.98are stacked.

InFIG.98, the pad1001srepresents, for example, the pad1001to which GND or a negative power supply is supplied, and the pad1001drepresents, for example, the pad1001to which a positive power supply is supplied.

As illustrated in A inFIG.98, a plurality of the lead-out conductor portions165Ab is connected to a predetermined side of the rectangular main conductor portion165Aa, and a plurality of the pads1001sis connected to the outer peripheral portion of each of the lead-out conductor portions165Ab at predetermined intervals via the conductor1011having a shape optionally including a predetermined repeating pattern. The conductor1011may be omitted or may be present. Furthermore, the conductor1011may be located between the main conductor portion165Aa and the lead-out conductor portion165Ab.

As illustrated in B inFIG.98, a plurality of the lead-out conductor portions165Bb is connected to a predetermined side of the rectangular main conductor portion165Ba, and a plurality of the pads1001dis connected to the outer peripheral portion of each of the lead-out conductor portions165Bb at predetermined intervals via the conductor1012having a shape optionally including a predetermined repeating pattern. The conductor1012may be omitted or may be present. Furthermore, the conductor1012may be located between the main conductor portion165Ba and the lead-out conductor portion165Bb.

As illustrated in C inFIG.98, in the state where the conductor layers A and B are stacked, the arrangement of the pads1001sand1001dis a mirror-symmetrical arrangement in which a set of pads1001is folded back in the Y direction and sequentially arranged, where four consecutive pads1001sand1001din the Y direction are set as one set. Moreover, the four pads1001sand pads1001dthat constitute one set also have a mirror-symmetrical arrangement in which two of the four pads1001are folded back in the Y direction with reference to a center line in the Y direction. In the case of adopting such a two-stage configuration with a mirror arrangement, a range in which a residual magnetic field is accumulated is narrower than that of a one-stage mirror arrangement illustrated inFIG.97, the induced electromotive force is more effectively canceled, and the inductive noise can be further improved depending on the layout other than the pads.

Tenth Arrangement Example of Pads

FIG.99illustrates a tenth arrangement example of pads.

A inFIG.99is a plan view illustrating an arrangement example of the conductor layer A (wiring layer165A) and the pads1001sconnected to the conductor layer A.

B inFIG.99is a plan view illustrating an arrangement example of the conductor layer B (wiring layer165B) and the pads1001dconnected to the conductor layer B.

C inFIG.99is a plan view of a state in which the conductor layers A and B and the pads1001sand1001drespectively illustrated in A and B inFIG.99are stacked.

InFIG.99, the pad1001srepresents, for example, the pad1001to which GND or a negative power supply is supplied, and the pad1001drepresents, for example, the pad1001to which a positive power supply is supplied.

As illustrated in A inFIG.99, a plurality of the lead-out conductor portions165Ab is connected to a predetermined side of the rectangular main conductor portion165Aa, and one pad1001sis connected to the outer peripheral portion of each of the lead-out conductor portions165Ab via the conductor1011having a shape optionally including a predetermined repeating pattern. The conductor1011may be omitted or may be present. Furthermore, the conductor1011may be located between the main conductor portion165Aa and the lead-out conductor portion165Ab.

As illustrated in B inFIG.99, a plurality of the lead-out conductor portions165Bb is connected to a predetermined side of the rectangular main conductor portion165Ba, and one pad1001dis connected to the outer peripheral portion of each of the lead-out conductor portions165Bb via the conductor1012having a shape optionally including a predetermined repeating pattern. The conductor1012may be omitted or may be present. Furthermore, the conductor1012may be located between the main conductor portion165Ba and the lead-out conductor portion165Bb.

As illustrated in C inFIG.99, in the state where the conductor layers A and B are stacked, the arrangement of the pads1001sand the pads1001dis an alternate arrangement in which the pad1001sand the pad1001dare alternately arranged in the Y direction. In this case, the magnetic field generated from each of the conductor layers A and B and the induced electromotive force based on the magnetic field can be effectively canceled, so that the inductive noise can be further improved. However, since the arrangement is not symmetrically arranged in the Y direction, in a case where the pads1001are arranged over a wide area, that is, in a case where the main conductor portion165Aa or165Ba, the lead-out conductor portion165Ab or165Bb, or the conductor1011or1012is longer in the arrangement direction of the pads1001(inFIG.99, the Y direction is longer than the X direction), there may be a magnetic field that cannot be canceled, and the induced electromotive force increases as the Victim conductor loop becomes larger and is accumulated, and the inductive noise may deteriorate.

Eleventh Arrangement Example of Pads

FIG.100illustrates an eleventh arrangement example of pads.

A inFIG.100is a plan view illustrating an arrangement example of the conductor layer A (wiring layer165A) and the pads1001sconnected to the conductor layer A.

B inFIG.100is a plan view illustrating an arrangement example of the conductor layer B (wiring layer165B) and the pads1001dconnected to the conductor layer B.

C inFIG.100is a plan view of a state in which the conductor layers A and B and the pads1001sand1001drespectively illustrated in A and B inFIG.100are stacked.

InFIG.100, the pad1001srepresents, for example, the pad1001to which GND or a negative power supply is supplied, and the pad1001drepresents, for example, the pad1001to which a positive power supply is supplied.

As illustrated in A inFIG.100, a plurality of the lead-out conductor portions165Ab is connected to a predetermined side of the rectangular main conductor portion165Aa, and one pad1001sis connected to the outer peripheral portion of each of the lead-out conductor portions165Ab via the conductor1011having a shape optionally including a predetermined repeating pattern. The conductor1011may be omitted or may be present. Furthermore, the conductor1011may be located between the main conductor portion165Aa and the lead-out conductor portion165Ab.

As illustrated in B inFIG.100, a plurality of the lead-out conductor portions165Bb is connected to a predetermined side of the rectangular main conductor portion165Ba, and one pad1001dis connected to the outer peripheral portion of each of the lead-out conductor portions165Bb via the conductor1012having a shape optionally including a predetermined repeating pattern. The conductor1012may be omitted or may be present. Furthermore, the conductor1012may be located between the main conductor portion165Ba and the lead-out conductor portion165Bb.

As illustrated in C inFIG.100, in the state where the conductor layers A and B are stacked, the arrangement of the pads1001sand1001dis a mirror-symmetrical arrangement in which a set of pads1001is folded back in the Y direction and sequentially arranged, where four consecutive pads1001sand1001din the Y direction are set as one set. In this case, as compared with the alternate arrangement illustrated inFIG.99, the magnetic field generated from each of the conductor layers A and B and the induced electromotive force based on the magnetic field can be more effectively canceled, so that the inductive noise can be further improved depending on the layout other than the pads.

Twelfth Arrangement Example of Pads

FIG.101illustrates a twelfth arrangement example of pads.

A inFIG.101is a plan view illustrating an arrangement example of the conductor layer A (wiring layer165A) and the pads1001sconnected to the conductor layer A.

B inFIG.101is a plan view illustrating an arrangement example of the conductor layer B (wiring layer165B) and the pads1001dconnected to the conductor layer B.

C inFIG.101is a plan view of a state in which the conductor layers A and B and the pads1001sand1001drespectively illustrated in A and B inFIG.101are stacked.

InFIG.101, the pad1001srepresents, for example, the pad1001to which GND or a negative power supply is supplied, and the pad1001drepresents, for example, the pad1001to which a positive power supply is supplied.

As illustrated in A inFIG.101, a plurality of the lead-out conductor portions165Ab is connected to a predetermined side of the rectangular main conductor portion165Aa, and one pad1001sis connected to the outer peripheral portion of each of the lead-out conductor portions165Ab via the conductor1011having a shape optionally including a predetermined repeating pattern. The conductor1011may be omitted or may be present. Furthermore, the conductor1011may be located between the main conductor portion165Aa and the lead-out conductor portion165Ab.

As illustrated in B inFIG.101, a plurality of the lead-out conductor portions165Bb is connected to a predetermined side of the rectangular main conductor portion165Ba, and one pad1001dis connected to the outer peripheral portion of each of the lead-out conductor portions165Bb via the conductor1012having a shape optionally including a predetermined repeating pattern. The conductor1012may be omitted or may be present. Furthermore, the conductor1012may be located between the main conductor portion165Ba and the lead-out conductor portion165Bb.

As illustrated in C inFIG.101, in the state where the conductor layers A and B are stacked, the arrangement of the pads1001sand1001dis a mirror-symmetrical arrangement in which a set of pads1001is folded back in the Y direction and sequentially arranged, where four consecutive pads1001sand1001din the Y direction are set as one set. Moreover, the four pads1001sand pads1001dthat constitute one set also have a mirror-symmetrical arrangement in which two of the four pads1001are folded back in the Y direction with reference to a center line in the Y direction. In the case of adopting such a two-stage configuration with a mirror arrangement, a range in which a residual magnetic field is accumulated is narrower than that of a one-stage mirror arrangement illustrated inFIG.100, the induced electromotive force is more effectively canceled, and the inductive noise can be further improved depending on the layout other than the pads.

Thirteenth Arrangement Example of Pads

FIG.102illustrates a thirteenth arrangement example of the pad.

A inFIG.102is a plan view illustrating an arrangement example of the conductor layer A (wiring layer165A) and the pads1001sconnected to the conductor layer A.

B inFIG.102is a plan view illustrating an arrangement example of the conductor layer B (wiring layer165B) and the pads1001dconnected to the conductor layer B.

C inFIG.102is a plan view of a state in which the conductor layers A and B and the pads1001sand1001drespectively illustrated in A and B inFIG.102are stacked.

InFIG.102, the pad1001srepresents, for example, the pad1001to which GND or a negative power supply is supplied, and the pad1001drepresents, for example, the pad1001to which a positive power supply is supplied.

As illustrated in A inFIG.102, a plurality of the lead-out conductor portions165Ab is connected to a predetermined side of the rectangular main conductor portion165Aa, and the conductor1011having a shape optionally including a predetermined repeating pattern is connected to the outer peripheral portion of each of the lead-out conductor portions165Ab. Furthermore, one pad1001sis connected to a part of the plurality of lead-out conductor portions165Ab via the conductor1011. The conductor1011may be omitted or may be present. Furthermore, the conductor1011may be located between the main conductor portion165Aa and the lead-out conductor portion165Ab.

As illustrated in B inFIG.102, a plurality of the lead-out conductor portions165Bb is connected to a predetermined side of the rectangular main conductor portion165Ba, and the conductor1012having a shape optionally including a predetermined repeating pattern is connected to the outer peripheral portion of each of the lead-out conductor portions165Bb. Furthermore, one pad1001dis arranged in a part of the plurality of lead-out conductor portions165Bb via the conductor1012. The conductor1012may be omitted or may be present. Furthermore, the conductor1012may be located between the main conductor portion165Ba and the lead-out conductor portion165Bb.

As illustrated in C inFIG.102, in the state where the conductor layers A and B are stacked, the arrangement of the pads1001sand the pads1001dis an alternate arrangement in which the pad1001sand the pad1001dare alternately arranged in the Y direction. In this case, the magnetic field generated from each of the conductor layers A and B and the induced electromotive force based on the magnetic field can be effectively canceled, so that the inductive noise can be further improved. However, since the arrangement is not symmetrically arranged in the Y direction, in a case where the pads1001are arranged over a wide area, that is, in a case where the main conductor portion165Aa or165Ba, the lead-out conductor portion165Ab or165Bb, or the conductor1011or1012is longer in the arrangement direction of the pads1001(inFIG.102, the Y direction is longer than the X direction), there may be a magnetic field that cannot be canceled, and the induced electromotive force increases as the Victim conductor loop becomes larger and is accumulated, and the inductive noise may deteriorate.

Fourteenth Arrangement Example of Pads

FIG.103illustrates a fourteenth arrangement example of pads.

A inFIG.103is a plan view illustrating an arrangement example of the conductor layer A (wiring layer165A) and the pads1001sconnected to the conductor layer A.

B inFIG.103is a plan view illustrating an arrangement example of the conductor layer B (wiring layer165B) and the pads1001dconnected to the conductor layer B.

C inFIG.103is a plan view of a state in which the conductor layers A and B and the pads1001sand1001drespectively illustrated in A and B inFIG.103are stacked.

InFIG.103, the pad1001srepresents, for example, the pad1001to which GND or a negative power supply is supplied, and the pad1001drepresents, for example, the pad1001to which a positive power supply is supplied.

As illustrated in A inFIG.103, a plurality of the lead-out conductor portions165Ab is connected to a predetermined side of the rectangular main conductor portion165Aa, and the conductor1011having a shape optionally including a predetermined repeating pattern is connected to the outer peripheral portion of each of the lead-out conductor portions165Ab. Furthermore, one pad1001sis connected to a part of the plurality of lead-out conductor portions165Ab via the conductor1011. The conductor1011may be omitted or may be present. Furthermore, the conductor1011may be located between the main conductor portion165Aa and the lead-out conductor portion165Ab.

As illustrated in B inFIG.103, a plurality of the lead-out conductor portions165Bb is connected to a predetermined side of the rectangular main conductor portion165Ba, and the conductor1012having a shape optionally including a predetermined repeating pattern is connected to the outer peripheral portion of each of the lead-out conductor portions165Bb. Furthermore, one pad1001dis arranged in a part of the plurality of lead-out conductor portions165Bb via the conductor1012. The conductor1012may be omitted or may be present. Furthermore, the conductor1012may be located between the main conductor portion165Ba and the lead-out conductor portion165Bb.

As illustrated in C inFIG.103, in the state where the conductor layers A and B are stacked, the arrangement of the pads1001sand1001dis a mirror-symmetrical arrangement in which a set of pads1001is folded back in the Y direction and sequentially arranged, where four consecutive pads1001sand1001din the Y direction are set as one set. In this case, as compared with the alternate arrangement illustrated inFIG.102, the magnetic field generated from each of the conductor layers A and B and the induced electromotive force based on the magnetic field can be more effectively canceled, so that the inductive noise can be further improved depending on the layout other than the pads.

Fifteenth Arrangement Example of Pads

FIG.104illustrates a fifteenth arrangement example of pads.

A inFIG.104is a plan view illustrating an arrangement example of the conductor layer A (wiring layer165A) and the pads1001sconnected to the conductor layer A.

B inFIG.104is a plan view illustrating an arrangement example of the conductor layer B (wiring layer165B) and the pads1001dconnected to the conductor layer B.

C inFIG.104is a plan view of a state in which the conductor layers A and B and the pads1001sand1001drespectively illustrated in A and B inFIG.104are stacked.

InFIG.104, the pad1001srepresents, for example, the pad1001to which GND or a negative power supply is supplied, and the pad1001drepresents, for example, the pad1001to which a positive power supply is supplied.

As illustrated in A inFIG.104, a plurality of the lead-out conductor portions165Ab is connected to a predetermined side of the rectangular main conductor portion165Aa, and the conductor1011having a shape optionally including a predetermined repeating pattern is connected to the outer peripheral portion of each of the lead-out conductor portions165Ab. Furthermore, one pad1001sis connected to a part of the plurality of lead-out conductor portions165Ab via the conductor1011. The conductor1011may be omitted or may be present. Furthermore, the conductor1011may be located between the main conductor portion165Aa and the lead-out conductor portion165Ab.

As illustrated in B inFIG.104, a plurality of the lead-out conductor portions165Bb is connected to a predetermined side of the rectangular main conductor portion165Ba, and the conductor1012having a shape optionally including a predetermined repeating pattern is connected to the outer peripheral portion of each of the lead-out conductor portions165Bb. Furthermore, one pad1001dis arranged in a part of the plurality of lead-out conductor portions165Bb via the conductor1012. The conductor1012may be omitted or may be present. Furthermore, the conductor1012may be located between the main conductor portion165Ba and the lead-out conductor portion165Bb.

As illustrated in C inFIG.104, in the state where the conductor layers A and B are stacked, the arrangement of the pads1001sand1001dis a mirror-symmetrical arrangement in which a set of pads1001is folded back in the Y direction and sequentially arranged, where four consecutive pads1001sand1001din the Y direction are set as one set. Moreover, the four pads1001sand pads1001dthat constitute one set also have a mirror-symmetrical arrangement in which two of the four pads1001are folded back in the Y direction with reference to a center line in the Y direction. In the case of adopting such a two-stage configuration with a mirror arrangement, a range in which a residual magnetic field is accumulated is narrower than that of a one-stage mirror arrangement illustrated inFIG.103, the induced electromotive force is more effectively canceled, and the inductive noise can be further improved depending on the layout other than the pads.

In the pad arrangement examples described with reference toFIGS.93to104, the examples in which the total number of pads connected to a predetermined one side of the main conductor portions165aof the conductor layers A and B is eight, and the arrangement of the eight pads1001continuous in the Y direction is the alternate arrangement, one-stage mirror arrangement, and two-stage mirror arrangement have been described. However, a total number of pads other than eight may be arranged in the alternate arrangement, one-stage mirror arrangement, and two-stage mirror arrangement. The number of pads in one set to be arranged in the alternate arrangement or the mirror arrangement is not limited to two or four, and is arbitrary.

Furthermore, the number of pads connected to one lead-out conductor portion165bis not limited to one or two illustrated inFIGS.93to104, and may be three or more.

Moreover,FIGS.93to104illustrate the examples in which the plurality of pads1001is connected to only the predetermined one side of the main conductor portions165aof the rectangular conductor layers A and B have been described for simplicity. However, the pads may be connected to a side other than the side illustrated inFIGS.93to104, or may be any two sides, three sides, or four sides.

The case where the total number of pads is eight has been described as an example, but this is not the case. The number of pads may be increased or the number of pads may be decreased.

The configuration elements illustrated as the examples of pad arrangement may be omitted in part or in whole, the part or the whole may be changed, the part or the whole may be altered, the part or the whole may be replaced with another configuration element, or another configuration element may be added to the part or the whole. Furthermore, a part or the whole of the configuration elements described as examples of pad arrangement may be divided into a plurality of elements, the part or the whole may be separated into a plurality of elements, or at least some of the plurality of divided or separated configuration elements may have different functions or characteristics. Moreover, at least some of the configuration elements illustrated as examples of pad arrangement may be arbitrarily combined to form different pad arrangement. Moreover, at least some of the configuration elements illustrated as examples of pad arrangement may be moved to form different pad arrangement. Moreover, a coupling element or a relay element may be added to a combination of at least some of the configuration elements illustrated as examples of pad arrangement to form different pad arrangement. Moreover, a switching element or a switching function may be added to a combination of at least some of the configuration elements illustrated as examples of pad arrangement to form different pad arrangement.

Sixteenth Arrangement Example of Pads

Next, examples of orthogonal pad arrangement in cases where a plurality of pads1001is arranged on adjacent two sides of the rectangular main conductor portions165aof the conductor layers A and B will be described with reference toFIGS.105to108.

FIG.105illustrates a sixteenth arrangement example of pads.

A inFIG.105is a plan view illustrating an arrangement example of the conductor layer A (wiring layer165A) and the pads1001sconnected to the conductor layer A.

B inFIG.105is a plan view illustrating an arrangement example of the conductor layer B (wiring layer165B) and the pads1001dconnected to the conductor layer B.

C inFIG.105is a plan view of a state in which the conductor layers A and B and the pads1001sand1001drespectively illustrated in A and B inFIG.105are stacked.

InFIG.105, the pad1001srepresents, for example, the pad1001to which GND or a negative power supply is supplied, and the pad1001drepresents, for example, the pad1001to which a positive power supply is supplied.

As illustrated in A inFIG.105, a plurality of the pads1001sis connected to adjacent two sides of the rectangular main conductor portion165Aa at predetermined intervals via the conductor1011having a shape optionally including a predetermined repeating pattern. Each pad1001smay be configured by the lead-out conductor portion165Ab or the conductor1011may be configured by the lead-out conductor portion165Ab. Furthermore, in the case where the pad1001sis the lead-out conductor portion165Ab, the conductor1011may be omitted or may be present.

As illustrated in B inFIG.105, a plurality of the pads1001dis connected to adjacent two sides of the rectangular main conductor portion165Ba at predetermined intervals via the conductor1012having a shape optionally including a predetermined repeating pattern. Each pad1001dmay be configured by the lead-out conductor portion165Bb or the conductor1012may be configured by the lead-out conductor portion165Bb. Furthermore, in the case where the pad1001dis the lead-out conductor portion165Bb, the conductor1012may be omitted or may be present.

As illustrated in C inFIG.105, in the state where the conductor layers A and B are stacked, the arrangement of the pads1001sand the pads1001dis an alternate arrangement in which the pad1001sand the pad1001dare alternately arranged on adjacent two sides of the rectangular main conductor portion165a. Furthermore, among the pads1001sand pads1001dalternately arranged on the two sides, the polarities of the pads1001at the ends of the two sides are both the pads1001sconnected to the GND or the negative power supply. In this way, among the plurality of pads1001on the two sides in which the pads1001sand the pads1001dare alternately arranged, the polarities of the pads1001at the ends closest to a corner of the substrate1000are the same polarity, and the pads1001swith the polarity having higher electrostatic discharge (ESD) resistance are adopted, whereby the ESD resistance can be enhanced.

Note that the polarities of the pads1001at the ends of the two sides where the pad1001sand the pad1001dare alternately arranged are favorably set to the pads1001sconnected to the GND or the negative power supply, for example, in consideration of the ESD resistance. However, the pads1001may be set to the pads1001dconnected to the positive power supply, for example.

Seventeenth Arrangement Example of Pads

FIG.106illustrates a seventeenth arrangement example of pads.

A inFIG.106is a plan view illustrating an arrangement example of the conductor layer A (wiring layer165A) and the pads1001sconnected to the conductor layer A.

B inFIG.106is a plan view illustrating an arrangement example of the conductor layer B (wiring layer165B) and the pads1001dconnected to the conductor layer B.

C inFIG.106is a plan view of a state in which the conductor layers A and B and the pads1001sand1001drespectively illustrated in A and B inFIG.106are stacked.

InFIG.106, the pad1001srepresents, for example, the pad1001to which GND or a negative power supply is supplied, and the pad1001drepresents, for example, the pad1001to which a positive power supply is supplied.

As illustrated in A inFIG.106, a plurality of the pads1001sis connected to adjacent two sides of the rectangular main conductor portion165Aa at predetermined intervals via the conductor1011having a shape optionally including a predetermined repeating pattern. Each pad1001smay be configured by the lead-out conductor portion165Ab or the conductor1011may be configured by the lead-out conductor portion165Ab. Furthermore, in the case where the pad1001sis the lead-out conductor portion165Ab, the conductor1011may be omitted or may be present.

As illustrated in B inFIG.106, a plurality of the pads1001dis connected to adjacent two sides of the rectangular main conductor portion165Ba at predetermined intervals via the conductor1012having a shape optionally including a predetermined repeating pattern. Each pad1001dmay be configured by the lead-out conductor portion165Bb or the conductor1012may be configured by the lead-out conductor portion165Bb. Furthermore, in the case where the pad1001dis the lead-out conductor portion165Bb, the conductor1012may be omitted or may be present.

As illustrated in C inFIG.106, in the state where the conductor layers A and B are stacked, the arrangement of the pads1001sand1001dis a mirror-symmetrical arrangement in which a set of pads1001is folded back in the Y direction and sequentially arranged, where four consecutive pads1001sand1001dare set as one set, as in the pad arrangement example illustrated in C inFIG.95. Furthermore, among the pads1001sand pads1001dmirror-symmetrically arranged on the two sides, the polarities of the pads1001at the ends of the two sides are both the pads1001sconnected to the GND or the negative power supply. In this way, among the plurality of pads1001on the two sides in which the pads1001sand the pads1001dare mirror-symmetrically arranged, the polarities of the pads1001at the ends closest to a corner of the substrate1000are the same polarity, and the pads1001swith the polarity having higher ESD resistance are adopted, whereby the ESD resistance can be enhanced. Furthermore, with the mirror-symmetrical arrangement, the impedance difference between the Vss wiring and the Vdd wiring becomes small and the current difference becomes small, so that the inductive noise can be further improved as compared with the sixteenth arrangement example inFIG.105.

Note that the polarities of the pads1001at the ends of the two sides where the pad1001sand the pad1001dare mirror-symmetrically arranged are favorably set to the pads1001sconnected to the GND or the negative power supply, for example, in consideration of the ESD resistance. However, the pads1001may be set to the pads1001dconnected to the positive power supply, for example.

Eighteenth Arrangement Example of Pads

FIG.107illustrates an eighteenth arrangement example of pads.

A inFIG.107is a plan view illustrating an arrangement example of the conductor layer A (wiring layer165A) and the pads1001sconnected to the conductor layer A.

B inFIG.107is a plan view illustrating an arrangement example of the conductor layer B (wiring layer165B) and the pads1001dconnected to the conductor layer B.

C inFIG.107is a plan view of a state in which the conductor layers A and B and the pads1001sand1001drespectively illustrated in A and B inFIG.107are stacked.

InFIG.107, the pad1001srepresents, for example, the pad1001to which GND or a negative power supply is supplied, and the pad1001drepresents, for example, the pad1001to which a positive power supply is supplied.

As illustrated in A inFIG.107, a plurality of the pads1001sis connected to adjacent two sides of the rectangular main conductor portion165Aa at predetermined intervals via the conductor1011having a shape optionally including a predetermined repeating pattern. Each pad1001smay be configured by the lead-out conductor portion165Ab or the conductor1011may be configured by the lead-out conductor portion165Ab. Furthermore, in the case where the pad1001sis the lead-out conductor portion165Ab, the conductor1011may be omitted or may be present.

As illustrated in B inFIG.107, a plurality of the pads1001dis connected to adjacent two sides of the rectangular main conductor portion165Ba at predetermined intervals via the conductor1012having a shape optionally including a predetermined repeating pattern. Each pad1001dmay be configured by the lead-out conductor portion165Bb or the conductor1012may be configured by the lead-out conductor portion165Bb. Furthermore, in the case where the pad1001dis the lead-out conductor portion165Bb, the conductor1012may be omitted or may be present.

As illustrated in C inFIG.107, in the state where the conductor layers A and B are stacked, the arrangement of the pads1001sand1001dis an alternate arrangement in which the pad1001sand the pad1001dare alternately arranged, similarly to the pad arrangement example illustrated inFIG.105. However, among the pads1001sand the pads1001darranged on the two sides, the polarities of the pads1001at the ends of the two sides are opposite polarities of the pad1001sand the pad1001d, which is different from the pad arrangement example illustrated inFIG.105. By setting the polarities of the pads1001at the ends closest to a corner of the substrate1000to the opposite polarities among the plurality of pads1001on the two sides where the pad1001sand the pad1001dare alternately arranged, the impedance difference between the Vss wiring and the Vdd wiring can be further reduced and the current difference further becomes smaller, whereby the inductive noise can be further improved as compared with the seventeenth arrangement example inFIG.106.

Nineteenth Arrangement Example of Pads

FIG.108illustrates a nineteenth arrangement of pads.

A inFIG.108is a plan view illustrating an arrangement example of the conductor layer A (wiring layer165A) and the pads1001sconnected to the conductor layer A.

B inFIG.108is a plan view illustrating an arrangement example of the conductor layer B (wiring layer165B) and the pads1001dconnected to the conductor layer B.

C inFIG.108is a plan view of a state in which the conductor layers A and B and the pads1001sand1001drespectively illustrated in A and B inFIG.108are stacked.

InFIG.108, the pad1001srepresents, for example, the pad1001to which GND or a negative power supply is supplied, and the pad1001drepresents, for example, the pad1001to which a positive power supply is supplied.

As illustrated in A inFIG.108, a plurality of the pads1001sis connected to adjacent two sides of the rectangular main conductor portion165Aa at predetermined intervals via the conductor1011having a shape optionally including a predetermined repeating pattern. Each pad1001smay be configured by the lead-out conductor portion165Ab or the conductor1011may be configured by the lead-out conductor portion165Ab. Furthermore, in the case where the pad1001sis the lead-out conductor portion165Ab, the conductor1011may be omitted or may be present.

As illustrated in B inFIG.108, a plurality of the pads1001dis connected to adjacent two sides of the rectangular main conductor portion165Ba at predetermined intervals via the conductor1012having a shape optionally including a predetermined repeating pattern. Each pad1001dmay be configured by the lead-out conductor portion165Bb or the conductor1012may be configured by the lead-out conductor portion165Bb. Furthermore, in the case where the pad1001dis the lead-out conductor portion165Bb, the conductor1012may be omitted or may be present.

As illustrated in C inFIG.108, in the state where the conductor layers A and B are stacked, the arrangement of the pads1001sand1001dis a mirror-symmetrical arrangement of the pads1001sand the pads1001d, similarly to the pad arrangement example illustrated inFIG.106. However, among the pads1001sand the pads1001darranged on the two sides, the polarities of the pads1001at the ends of the two sides are opposite polarities of the pad1001sand the pad1001d, which is different from the pad arrangement example illustrated inFIG.106. By setting the polarities of the pads1001at the ends closest to a corner of the substrate1000to the opposite polarities among the plurality of pads1001on the two sides where the pad1001sand the pad1001dare mirror-symmetrically arranged, the impedance difference between the Vss wiring and the Vdd wiring can be further reduced and the current difference further becomes smaller, whereby the inductive noise can be further improved as compared with the seventeenth arrangement example inFIG.106.

In the sixteenth to nineteenth arrangement examples of pads described with reference toFIGS.105to108, the examples in which the plurality of pads1001is arranged on the adjacent two sides of the rectangular main conductor portion165aat predetermined intervals via the conductor1011or1012have been described. However, the sides on which the pads1001are arranged are not limited to two sides and may be three or four sides.

Furthermore, in the sixteenth to nineteenth arrangement examples described with reference toFIGS.105to108, the alternate arrangement inFIG.93and the two-stage mirror arrangement inFIG.95have been adopted as the form of the pads1001arranged on one side. However, a form in which the one-stage mirror arrangement inFIG.94is adopted, and the polarities of the pads1001at the ends closest to a corner are set to the same polarities or opposite polarities may be adopted.

Moreover, in the sixteenth to nineteenth arrangement examples described with reference toFIGS.105to108, the lead-out conductor portion165bhas been omitted. However, a form in which the alternate arrangement inFIG.93, the one-stage mirror arrangement inFIG.94, or the two-stage mirror arrangement inFIG.95is adopted for the configuration provided with the lead-out conductor portion165bon a side of the rectangular main conductor portion165Aa as inFIGS.96to104, and the polarities of the pads1001at the ends closest to a corner are set to the same polarities or opposite polarities may be adopted.

Note that the lead-out conductor portions165Ab and165Bb and the conductors1011and1012are favorably configured such that, but not limited to, the GND or the negative power supply is supplied from the pad1001sto the main conductor portion165Aa, and the positive power supply of the opposite polarity is supplied from the pad1001dto the main conductor portion165Ba. In other words, the lead-out conductor portions165Ab and165Bb and the conductors1011and1012are favorably configured such that, but not limited to, the GND or the negative power supply and the positive power supply of the opposite polarity supplied from the pads1001are not completely short-circuited. Note that at least some ofFIGS.92to108illustrate the example of arranging the plurality of pads1001s, the example of arranging the plurality of pads1001d, the example of arranging the plurality of conductors1011, the example of arranging the plurality of conductors1012, the example of arranging the plurality of lead-out conductor portions165Ab, the example of arranging the plurality of lead-out conductor portions165Bb, and the like. In each drawing, all the pads1001smay be the same, not all the pads1001sneed to be the same, all the pads1001dmay be the same, not all the pads1001dneed to be the same, all the conductors1011may be the same, not all the conductors1011need to be the same, all the conductors1012may be the same, not all the conductors1012need to be the same, all the lead-out conductor portions165Ab may be the same, not all the lead-out conductor portions165Ab need to be the same, all the lead-out conductor portions165Bb may be the same, and not all the lead-out conductor portions165Bb need to be the same. Note that it is desirable but not limited to satisfy at least any one of the following: the total number of pads1001sand the total number of pads1001ddirectly or indirectly connected to the main conductor portion165ain the substrate1000are the same or substantially the same, the total number of pads1001sand the total number of pads1001ddirectly or indirectly connected to the main conductor portion165aon predetermined adjacent two sides of the substrate1000are the same or substantially the same, the total number of pads1001sand the total number of pads1001ddirectly or indirectly connected to the main conductor portion165aon predetermined facing two sides of the substrate1000are the same or substantially the same, the total number of pads1001sand the total number of pads1001ddirectly or indirectly connected to the main conductor portion165aon a predetermined side of the substrate1000are the same or substantially the same, the total number of pads1001sand the total number of pads1001ddirectly or indirectly connected to at least two lead-out conductor portions165bon predetermined adjacent two sides of the substrate1000are the same or substantially the same, the total number of pads1001sand the total number of pads1001ddirectly or indirectly connected to at least two lead-out conductor portions165bon predetermined facing two sides of the substrate1000are the same or substantially the same, the total number of pads1001sand the total number of pads1001ddirectly or indirectly connected to at least one lead-out conductor portion165bon a predetermined side of the substrate1000are the same or substantially the same, the total number of pads1001sand the total number of pads1001ddirectly or indirectly connected to at least two sets of conductors1011and1012on predetermined adjacent two sides of the substrate1000are the same or substantially the same, the total number of pads1001sand the total number of pads1001ddirectly or indirectly connected to at least two sets of conductors1011and1012on predetermined facing two sides of the substrate1000are the same or substantially the same, or the total number of pads1001sand the total number of pads1001ddirectly or indirectly connected to at least one set of conductors1011and1012on a predetermined side of the substrate1000are the same or substantially the same. For example, the total number of pads1001sand the total number of pads1001dmay not be the same, or the total number of pads1001sand the total number of pads1001dmay not be substantially the same.

Substrate Arrangement Example of Victim Conductor Loop and Aggressor Conductor Loop

FIG.109illustrates substrate arrangement examples of the Victim conductor loop and the Aggressor conductor loop.

A inFIG.109is a cross-sectional view schematically illustrating a substrate arrangement example of the Victim conductor loop and the Aggressor conductor loop.

In each of the above-described configuration examples, as illustrated in A inFIG.109, a Victim conductor loop1101being included in the first semiconductor substrate101, Aggressor conductor loops1102A and1102B being included in the second semiconductor substrate102, and the stacked structure of the first semiconductor substrate101and the second semiconductor substrate102have been described.

However, a structure in which the first semiconductor substrate101and the second semiconductor substrate102are not stacked, and the first semiconductor substrate101and the second semiconductor substrate102are arranged adjacent to each other as illustrated in B inFIG.109, or a structure in which the first semiconductor substrate101and the second semiconductor substrate102are arranged on the same plane with a predetermined interval as illustrated in C inFIG.109may be adopted.

Moreover, as the substrate arrangement of the Victim conductor loop and the Aggressor conductor loop, various arrangement configurations as illustrated in A to I inFIG.110can be adopted.

A inFIG.110illustrates a structure in which the Victim conductor loop1101is included in the first semiconductor substrate101, the Aggressor conductor loops1102A and1102B are included in the second semiconductor substrate102, a third semiconductor substrate103is inserted between the first semiconductor substrate101and the second semiconductor substrate102, and the first semiconductor substrate101to the third semiconductor substrate103are stacked.

B inFIG.110illustrates a structure in which the Victim conductor loop1101is included in the first semiconductor substrate101, the Aggressor conductor loop1102A is included in the second semiconductor substrate102, the Aggressor conductor loop1102B is included in the third semiconductor substrate103, and the first semiconductor substrate101to the third semiconductor substrate103are stacked in that order.

C inFIG.110illustrates a structure in which the Victim conductor loop1101is included in the first semiconductor substrate101, the Aggressor conductor loops1102A and1102B are included in the second semiconductor substrate102, a support substrate104is inserted between the first semiconductor substrate101and the second semiconductor substrate102, and the first semiconductor substrate101, the support substrate104, and the second semiconductor substrate102are stacked in this order. The support substrate104may be omitted, and the first semiconductor substrate101and the second semiconductor substrate102may be arranged with a predetermined gap.

D inFIG.110illustrates a structure in which the Victim conductor loop1101is included in the first semiconductor substrate101, the Aggressor conductor loops1102A and1102B are included in the second semiconductor substrate102, and the first semiconductor substrate101and the second semiconductor substrate102are placed on the support substrate104and arranged on the same plane with a predetermined interval. The support substrate104may be omitted, and the first semiconductor substrate101and the second semiconductor substrate102may be supported to be arranged in the same plane at different places.

E inFIG.110illustrates a structure in which the Victim conductor loop1101and Aggressor conductor loop1102A are included in the first semiconductor substrate101, the Aggressor conductor loop1102B is included in the second semiconductor substrate102, and the first semiconductor substrate101and the second semiconductor substrate102are stacked. Here, the region on the XY plane where the Victim conductor loop1101is formed in the first semiconductor substrate101at least partly overlaps with the region on the XY plane where the Aggressor conductor loops1102A and1102B are formed in the second semiconductor substrate102.

F inFIG.110illustrates a structure in which the Victim conductor loop1101is included in the first semiconductor substrate101, the Aggressor conductor loops1102A and1102B are included in the second semiconductor substrate102, and the first semiconductor substrate101and the second semiconductor substrate102are stacked. Here, the region on the XY plane where the Victim conductor loop1101is formed in the first semiconductor substrate101may be completely different from or partly overlap with the region on the XY plane where the Aggressor conductor loops1102A and1102B are formed in the second semiconductor substrate102.

G inFIG.110illustrates a structure in which the Victim conductor loop1101and Aggressor conductor loop1102A are included in the first semiconductor substrate101, the Aggressor conductor loop1102B is included in the second semiconductor substrate102, and the first semiconductor substrate101and the second semiconductor substrate102are stacked. Here, the region on the XY plane where the Victim conductor loop1101is formed in the first semiconductor substrate101is different from the region on the XY plane where the Aggressor conductor loops1102A and1102B are formed.

H inFIG.110illustrates a structure in which the Victim conductor loop1101and the Aggressor conductor loops1102A and1102B are included in one semiconductor substrate105. Note that the region on the XY plane where the Victim conductor loop1101is formed in the one semiconductor substrate105at least partly overlaps with the region on the XY plane where the Aggressor conductor loops1102A and1102B are formed.

I inFIG.110illustrates a structure in which the Victim conductor loop1101and the Aggressor conductor loops1102A and1102B are included in one semiconductor substrate105. Note that the region on the XY plane where the Victim conductor loop1101is formed in the one semiconductor substrate105is different from the region on the XY plane where the Aggressor conductor loops1102A and1102B are formed.

The stacking order of the substrates illustrated in A to I inFIG.110may be inverted, and the positions of the Victim conductor loop1101and the Aggressor conductor loops1102A and1102B may be made upside down.

As described above, the number and arrangement of the semiconductor substrates including the Victim conductor loop1101and the Aggressor conductor loops1102A and1102B, and the presence or absence of the support substrate can have various structures.

The Aggressor conductor loop that generates the magnetic flux passing through the loop plane of the Victim conductor loop may or may not overlap with the Victim conductor loop. Moreover, the Aggressor conductor loop may be formed in a plurality of semiconductor substrates stacked on the semiconductor substrate in which the Victim conductor loop is formed, or may be formed in the same semiconductor substrate as the Victim conductor loop.

Moreover, the Aggressor conductor loop is not a semiconductor substrate, and for example, various substrates such as a printed circuit board, a flexible printed circuit board, an interposer substrate, a package substrate, an inorganic substrate, and an organic substrate are conceivable. However, it is sufficient that any substrate may be used as long as the substrate includes a conductor or can form a conductor, and may exist in a circuit other than the semiconductor substrate such as a package in which the semiconductor substrate is sealed. In general, the distance of the Aggressor conductor loop to the Victim conductor loop becomes shorter in the order of the case where the Aggressor conductor loop is formed in the semiconductor substrate, the case where the Aggressor conductor loop is formed in the package, and the case where the Aggressor conductor loop is formed in the printed circuit board. Since the inductive noise and capacitive noise that can occur in the Victim conductor loop are more likely to increase as the distance of the Aggressor conductor loop to the Victim conductor loop is shorter, the present technology can be more effective as the distance of the Aggressor conductor loop to the Victim conductor loop is shorter. Moreover, application of the present technology is not limited to the substrates. The present technology can be applied to conductors themselves represented by wires and plates, such as bonding wires, lead wires, antenna wires, power wires, GND wires, coaxial wires, dummy wires, and sheet metal.

Next, as illustrated inFIG.111, in a structure in which three types of substrates: a semiconductor substrate1121, a package substrate1122, and a printed circuit board1123are stacked, examples of arranging a conductor1101(hereinafter referred to as Victim conductor loop1101), which is at least a part of the Victim conductor loop, and conductors1102A and1102B that are at least a part of the Aggressor conductor loop (hereinafter referred to as Aggressor conductor loops1102A and1102B) will be described. Note that although not shown, the Victim conductor loop or Aggressor conductor loop may include at least conductors arranged in two or more of the semiconductor substrate1121, the package substrate1122, and the printed circuit board1123. The semiconductor substrate1121can be replaced with any of a package substrate, an interposer substrate, a printed circuit board, a flexible printed circuit board, an inorganic substrate, an organic substrate, a substrate including a conductor, or a substrate capable of forming a conductor. Furthermore, the package substrate1122can be replaced with any of a semiconductor substrate, an interposer substrate, a printed circuit board, a flexible printed circuit board, an inorganic substrate, an organic substrate, a substrate including a conductor, or a substrate capable of forming a conductor. Moreover, the printed circuit board1123can be replaced with any of a semiconductor substrate, a package substrate, an interposer substrate, a flexible printed circuit board, an inorganic substrate, an organic substrate, a substrate including a conductor, or a substrate capable of forming a conductor.

A to R inFIG.112illustrate arrangement examples of the Victim conductor loop and the Aggressor conductor loop in a stacked structure in which the three types of substrates illustrated inFIG.111are stacked.

A inFIG.112illustrates a schematic diagram of a stacked structure in which the Victim conductor loop1101and the Aggressor conductor loops1102A and1102B are all included in the semiconductor substrate1121. The package substrate1122and the printed circuit board1123in which none of the Victim conductor loop1101and the Aggressor conductor loops1102A and1102B are formed may be omitted.

B inFIG.112illustrates a schematic diagram of a stacked structure in which the Victim conductor loop1101and the Aggressor conductor loop1102A are included in the semiconductor substrate1121and the Aggressor conductor loop1102B is included in the package substrate1122. The printed circuit board1123in which none of the Victim conductor loop1101and the Aggressor conductor loops1102A and1102B are formed may be omitted.

C inFIG.112illustrates a schematic diagram of a stacked structure in which the Victim conductor loop1101and the Aggressor conductor loop1102A are included in the semiconductor substrate1121and the Aggressor conductor loop1102B is included in the printed circuit board1123. The package substrate1122in which none of the Victim conductor loop1101and the Aggressor conductor loops1102A and1102B are formed may be omitted.

D inFIG.112illustrates a schematic diagram of a stacked structure in which the Victim conductor loop1101is included in the semiconductor substrate1121and the Aggressor conductor loops1102A and1102B are included in the package substrate1122. The printed circuit board1123in which none of the Victim conductor loop1101and the Aggressor conductor loops1102A and1102B are formed may be omitted.

E inFIG.112illustrates a schematic diagram of a stacked structure in which the Victim conductor loop1101is included in the semiconductor substrate1121, the Aggressor conductor loop1102A is included in the package substrate1122, and the Aggressor conductor loop1102B is included in the printed circuit board1123.

F inFIG.112illustrates a schematic diagram of a stacked structure in which the Victim conductor loop1101is included in the semiconductor substrate1121and the Aggressor conductor loops1102A and1102B are included in the printed circuit board1123. The package substrate1122in which none of the Victim conductor loop1101and the Aggressor conductor loops1102A and1102B are formed may be omitted.

G inFIG.112illustrates a schematic diagram of a stacked structure in which the Aggressor conductor loops1102A and1102B are included in the semiconductor substrate1121and the Victim conductor loop1101is included in the package substrate1122. The printed circuit board1123in which none of the Victim conductor loop1101and the Aggressor conductor loops1102A and1102B are formed may be omitted.

H inFIG.112illustrates a schematic diagram of a stacked structure in which the Aggressor conductor loop1102A is included in the semiconductor substrate1121and the Aggressor conductor loop1102B and the Victim conductor loop1101are included in the package substrate1122. The printed circuit board1123in which none of the Victim conductor loop1101and the Aggressor conductor loops1102A and1102B are formed may be omitted.

I inFIG.112illustrates a schematic diagram of a stacked structure in which the Aggressor conductor loop1102A is included in the semiconductor substrate1121, the Victim conductor loop1101is included in the package substrate1122, and the Aggressor conductor loop1102B is included in the printed circuit board1123.

J inFIG.112illustrates a schematic diagram of a stacked structure in which the Victim conductor loop1101and the Aggressor conductor loops1102A and1102B are all included in the package substrate1122. The semiconductor substrate1121and the printed circuit board1123in which none of the Victim conductor loop1101and the Aggressor conductor loops1102A and1102B are formed may be omitted.

K inFIG.112illustrates a schematic diagram of a stacked structure in which the Victim conductor loop1101and the Aggressor conductor loop1102A are included in the package substrate1122and the Aggressor conductor loop1102B is included in the printed circuit board1123. The semiconductor substrate1121in which none of the Victim conductor loop1101and the Aggressor conductor loops1102A and1102B are formed may be omitted.

L inFIG.112illustrates a schematic diagram of a stacked structure in which the Victim conductor loop1101is included in the package substrate1122and the Aggressor conductor loops1102A and1102B are included in the printed circuit board1123. The semiconductor substrate1121in which none of the Victim conductor loop1101and the Aggressor conductor loops1102A and1102B are formed may be omitted.

M inFIG.112illustrates a schematic diagram of a stacked structure in which the Aggressor conductor loops1102A and1102B are included in the semiconductor substrate1121and the Victim conductor loop1101is included in the printed circuit board1123. The package substrate1122in which none of the Victim conductor loop1101and the Aggressor conductor loops1102A and1102B are formed may be omitted.

N inFIG.112illustrates a schematic diagram of a stacked structure in which the Aggressor conductor loop1102A is included in the semiconductor substrate1121, the Aggressor conductor loop1102B is included in the package substrate1122, and the Victim conductor loop1101is included in the printed circuit board1123.

O inFIG.112illustrates a schematic diagram of a stacked structure in which the Aggressor conductor loop1102A is included in the semiconductor substrate1121and the Aggressor conductor loop1102B and the Victim conductor loop1101are included in the printed circuit board1123. The package substrate1122in which none of the Victim conductor loop1101and the Aggressor conductor loops1102A and1102B are formed may be omitted.

P inFIG.112illustrates a schematic diagram of a stacked structure in which Aggressor conductor loops1102A and1102B are included in the package substrate1122and the Victim conductor loop1101is included in the printed circuit board1123. The semiconductor substrate1121in which none of the Victim conductor loop1101and the Aggressor conductor loops1102A and1102B are formed may be omitted.

Q inFIG.112illustrates a schematic diagram of a stacked structure in which the Aggressor conductor loop1102A is included in the package substrate1122and the Aggressor conductor loop1102B and the Victim conductor loop1101are included in the printed circuit board1123. The semiconductor substrate1121in which none of the Victim conductor loop1101and the Aggressor conductor loops1102A and1102B are formed may be omitted.

R inFIG.112illustrates a schematic diagram of a stacked structure in which the Victim conductor loop1101and the Aggressor conductor loops1102A and1102B are all included in the printed circuit board1123. The semiconductor substrate1121and the package substrate1122in which none of the Victim conductor loop1101and the Aggressor conductor loops1102A and1102B are formed may be omitted.

The stacking order of the substrates illustrated in A to R inFIG.112may be inverted, and the positions of the Victim conductor loop1101and the Aggressor conductor loop1102A or the Aggressor conductor loop1102B may be made upside down.

As described above, the Victim conductor loop1101and the Aggressor conductor loops1102A and1102B can be formed in any region of the semiconductor substrate1121, the package substrate1122, and the printed circuit board1123.

Package Stacking Examples of First Semiconductor Substrate101and Second Semiconductor Substrate102Forming Solid-State Imaging Device100

FIG.113is diagrams illustrating package stacking examples of the first semiconductor substrate101and the second semiconductor substrate102forming the solid-state imaging device100.

The first semiconductor substrate101and the second semiconductor substrate102may be stacked in any manner as a package.

For example, as illustrated in A inFIG.113, the first semiconductor substrate101and the second semiconductor substrate102are individually sealed with a sealing material, and resulting packages601and602may be stacked.

Furthermore, as illustrated in B or C inFIG.113, the first semiconductor substrate101and the second semiconductor substrate102may be stacked and sealed with a sealing material to form a package603. In this case, a bonding wire604may be connected to the second semiconductor substrate102as illustrated in B inFIG.113, or may be connected to the first semiconductor substrate101as illustrated in C inFIG.113.

Moreover, the package may be in any form. For example, the package may be a chip size package (CSP) or a wafer level chip size package (WL-CSP), and an interposer board or a rewiring layer may be used in the package. Furthermore, any form without a package may be adopted. For example, a semiconductor substrate may be mounted as a chip on board (COB). For example, any of the following forms may be adopted: ball grid array BGA), chip on board (COB), chip on tape (COT), chip size package/chip scale package (CSP), dual in-line memory module (DIMM), dual in-line package (DIP), fine-pitch ball grid array (FBGA), fine-pitch land grid array (FLGA), fine-pitch quad flat package (FQFP), single in-line package with heatsink (HSIP), leadless chip carrier (LCC), low profile fine pitch land grid array (LFLGA), land grid array (LGA), low-profile quad flat package (LQFP), multi-chip fine-pitch ball grid array (MC-FBGA), multi-chip module (MCM), multi-chip package (MCP), molded chip size package (M-CSP), mini flat package (MFP), metric quad flat package (MQFP), metal quad (MQUAD), micro small outline package (MSOP), pin grid array (PGA), plastic leaded chip carrier (PLCC), plastic leadless chip carrier (PLCC), quad flat i-leaded package (QFI), quad flat j-leaded package (QFJ), quad flat non-leaded package (QFN), quad flat package (QFP), quad tape carrier package (QTCP), quad in-line package (QUIP), shrink dual in-line package (SDIP), single in-line memory module (SIMM), single in-line package (SIP), stacked multi chip package (S-MCP), small outline non-leaded board (SNB), small outline i-leaded package (SOI), small outline j-leaded package (SOJ), small outline non-leaded package (SON), small outline package (SOP), shrink single in-line package (SSIP), shrink small outline package (SSOP), shrink zigzag in-line package (SZIP), tape-automated bonding (TAB), tape carrier package (TCP), thin quad flat package (TQFP), thin small outline package (TSOP), thin shrink small outline package (TSSOP), ultra chip scale package (UCSP), ultra thin small outline package (UTSOP), very short pitch small outline package (VSO), very small outline package (VSOP), wafer level chip size package (WL-CSP), zigzag in-line package (ZIP), and micro multi-chip package (pMCP).

The present technology can be applied to, for example, any sensor such as charge-coupled device (CCD) image sensor, CCD sensor, CMOS sensor, MOS sensor, infrared (IR) sensor, ultraviolet (UV) sensor, time of flight (ToF) sensor, or distance measurement sensor, a circuit board, a device, or an electronic device.

Furthermore, the present technology is suitable for, but not limited to, sensors, circuit boards, devices, and electronic devices in which some devices such as transistors, diodes, and antennas are arrayed, and is particularly suitable for, but not limited to, sensors, circuit boards, devices, and electronic devices in which some devices are arrayed on substantially the same plane.

The present technology can be applied to, for example, various memory sensors related to memory devices, circuit boards for memory, memory devices, or electronic devices including memories, various CCD sensors related to CCD, circuit boards for CCD, CCD devices, or electronic devices including CCDs, various CMOS sensors related to CMOS, circuit boards for CMOS, CMOS devices, or electronic devices including CMOSs, various MOS sensors related to MOS, circuit boards for MOS, MOS devices, or electronic devices including MOSs, various display sensors related to light emitting devices, circuit boards for display, display devices, or electronic devices including displays, various laser sensors related to light emitting devices, laser circuit boards, laser devices, or electronic devices including lasers, or various antenna sensors related to antenna devices, antenna circuit boards, antenna devices, electronic devices including antennas, or the like. Among them, the present technology can be favorably applied to, but not limited to, sensors including the Victim conductor loop with variable loop paths, sensors including circuit boards, devices, electronic devices, or control lines or signal lines, sensors including circuit boards, devices, electronic devices, or horizontal control lines or vertical signal lines, circuit boards, devices, electronic devices, or the like.

11. Arrangement Example of Conductive Shield

In the above-described configuration examples, the inductive noise being able to be reduced by devising the configurations of the conductor layer A (wiring layer165A) and the conductor layer B (wiring layer165B) has been described. A configuration for further improving the inductive noise by further including a conductive shield will be described.

FIGS.114and115are cross-sectional views illustrating configuration examples in which the conductive shield is provided for the solid-state imaging device100in which the first semiconductor substrate101and the second semiconductor substrate102illustrated inFIG.6are stacked.

Note that, inFIGS.114and115, description of configurations other than the conductive shield is omitted as appropriate as the configurations are similar to the structure illustrated inFIG.6.

A inFIG.114is a cross-sectional view illustrating a first configuration example in which a conductive shield is provided for the solid-state imaging device100illustrated inFIG.6

In A inFIG.114, a conductive shield1151is formed in the multilayer wiring layer153of the first semiconductor substrate101.

B inFIG.114is a cross-sectional view illustrating a second configuration example in which a conductive shield is provided for the solid-state imaging device100illustrated inFIG.6

In B inFIG.114, the conductive shield1151is formed in the multilayer wiring layer163of the second semiconductor substrate102.

C inFIG.114is a cross-sectional view illustrating a third configuration example in which a conductive shield is provided for the solid-state imaging device100illustrated inFIG.6

In C inFIG.114, the conductive shield1151is formed in each of the multilayer wiring layers of the first semiconductor substrate101and the second semiconductor substrate102. More specifically, the conductive shield1151A is formed in the multilayer wiring layer153of the first semiconductor substrate101, and the conductive shield1151B is formed in the multilayer wiring layer163of the second semiconductor substrate102.

A inFIG.115is a cross-sectional view illustrating a fourth configuration example in which a conductive shield is provided for the solid-state imaging device100illustrated inFIG.6

In A inFIG.115, the conductive shield1151is formed in each of the multilayer wiring layers of the first semiconductor substrate101and the second semiconductor substrate102, and the conductive shields1151are bonded. More specifically, a conductive shield1151A is formed on a bonding surface in the multilayer wiring layer153of the first semiconductor substrate101, the bonding surface being for bonding with the multilayer wiring layer163of the second semiconductor substrate102, a conductive shield1151B is formed on a bonding surface in the multilayer wiring layer163of the second semiconductor substrate102, the bonding surface for bonding with the multilayer wiring layer153of the first semiconductor substrate101, and the conductive shields1151A and1151B are bonded by similar metal bonding such as Cu—Cu bonding, Au—Au bonding, or Al—Al bonding, or dissimilar metal bonding such as Cu—Au bonding, Cu—Al bonding, or Au—Al bonding.

Note that C inFIG.114and A inFIG.115are examples in which plane regions of the conductive shields1151A and1151B match, but at least the plane regions overlap and are bonded in part.

B inFIG.115is a cross-sectional view illustrating a fifth configuration example in which a conductive shield is provided for the solid-state imaging device100illustrated inFIG.6

B inFIG.115illustrates a configuration in which the wiring layer165A, which is the conductor layer A, also functions as the conductive shield1151. A part of the wiring layer165A may be the conductive shield1151.

C inFIG.115is a cross-sectional view illustrating a sixth configuration example in which a conductive shield is provided for the solid-state imaging device100illustrated inFIG.6

In the sixth configuration example in C inFIG.115, the conductive shield1151is formed in the multilayer wiring layer153, similarly to the first configuration example illustrated in A inFIG.114, but the plane region in which the conductive shield1151is formed is smaller than the plane region of the wiring layer165A as the conductor layer A and the wiring layer165B as the conductor layer B.

The area of the plane region where the conductive shield1151is formed is favorably equal to or larger than the area of the plane region of the wiring layer165A as the conductor layer A and the wiring layer165B as the conductor layer B, as in the first configuration example in A inFIG.114, but may be smaller, as in B inFIG.115.

The inductive noise can be further improved by providing the conductive shield1151, as in the first to sixth configuration examples inFIGS.114and115.

In the first to sixth configuration examples inFIGS.114and115, the wiring layers shielded by the conductive shield1151are two layers of the wiring layers165A and165B, but one layer may be shielded.

In the first to sixth configuration examples inFIGS.114and115, a magnetic shield may be used instead of the conductive shield1151. The magnetic shield may be conductive or non-conductive. In the case where the magnetic shield is conductive, the inductive noise and the capacitive noise can be further improved.

Next, the arrangement and the planar shape of the conductive shield1151with respect to the signal line132formed in the first semiconductor substrate101will be described with reference toFIGS.116to119.

FIGS.116to119illustrate first to fourth configuration examples of the arrangement and the planar shape of the conductive shield1151with respect to the signal line132. The first to fourth configuration examples inFIGS.116to119have the same configuration other than the planar shape of the conductive shield1151.

A inFIG.116is a cross-sectional view illustrating a positional relationship in the Z direction of the signal line132through which an analog pixel signal is transmitted on the first semiconductor substrate101, the conductive shield1151, and the wiring layer165A. B inFIG.116is a plan view illustrating a planar shape of the conductive shield1151.

As illustrated in A inFIG.116, the conductive shield1151is arranged between the signal line132and the wiring layer165A. As illustrated in B inFIG.116, the planar shape of the conductive shield1151can be formed in a planar shape.

Alternatively, as in the second configuration example in A and B inFIG.117, the planar shape of the conductive shield1151is formed in a linear shape, and each linear region can be formed to correspond to and overlap with the signal line132in a one-to-one manner.

Alternatively, each linear region of the conductive shield1151does not have to correspond one-to-one with the signal line132, as in the second configuration example in A and B inFIG.117. For example, one linear region may be formed to overlap with a plurality of signal lines132, as in the third configuration example in A and B inFIG.118.FIG.118illustrates a planar shape in which one linear region of the conductive shield1151corresponds to two signal lines132. However, a planar shape corresponding to three or more signal lines132may be adopted.

Alternatively, the planar shape of the conductive shield1151may be formed in a reticulated shape, as in the fourth configuration example in A and B inFIG.119, instead of the linear shape. Conductor widths, gap widths, and conductor periods of a vertical conductor extending in the vertical direction (Y direction) of the reticulated conductive shield1151, and of a horizontal conductor extending in the horizontal direction (X direction) may be different or the same.

In the first to fourth configuration examples inFIGS.116to119, the conductive shield1151is placed in one layer but can be placed in two layers, as illustrated in C inFIG.114and in A inFIG.115. Furthermore, the wiring layer165A illustrated inFIGS.116to119is similarly applied to the wiring layer165B.

The conductive shield1151is formed at a position where the conductive shield1151overlaps with the entire region of the signal line132, but may be at a position where the conductive shield1151overlaps with a part of the region or a position where the conductive shield1151does not overlap with the region. Note that since noise is often propagated via a signal line, the conductive shield1151is favorably located at the position where the conductive shield1151overlaps with the signal line132.

Although the forming position of the conductive shield1151with respect to the signal line132through which the analog pixel signal is transmitted in the first semiconductor substrate101has been described, the configuration may be applied to another signal line for signal transmission, control line, wire, conductor, or GND, instead of the signal line132for pixel signal transmission. The conductive shield1151is favorably connected to the GND or the negative power supply to efficiently dissipate noise, but may be connected to another control line, another signal line, another conductor, or another wire. Alternatively, the conductive shield1151may not be connected to another control line, another signal line, another conductor, another wire, or the like.

By providing the conductive shield1151, the inductive noise and the capacitive noise can be further improved.

12. Configuration Example of Case Having Three Conductor Layers

Arrangement Example of Case Having Three Conductor Layers

In each of the above-described configuration examples, the wiring pattern of the two conductor layers: the conductor layer A as the wiring layer165A and the conductor layer B as the wiring layer165B has been described.

However, a third conductor layer is sometimes further arranged near the two conductor layers of the wiring layer165A (conductor layer A) and the wiring layer165B (conductor layer B).

The third conductor layer is used as, for example, wiring for relaying the GND or the negative power supply to the Vss wiring of the conductor layer A as the wiring layer165A, wiring for relaying the positive power supply to the Vdd wiring of the conductor layer B as the wiring layer165B, reinforcing wiring for minimizing the voltage drop (IR-Drop) of the conductor layer A or the conductor layer B, or the like.

When the third conductor layer is referred to as a wiring layer165C or a conductor layer C, corresponding to the names of the wiring layers165A and165B, and the conductor layers A and B in the above-described configuration examples, the wiring layer165C that is the third conductor layer is arranged in any of the positional relationships in A to C inFIG.120with respect to the wiring layers165A and165B.

A to C inFIG.120are schematic cross-sectional views illustrating arrangement examples of the wiring layer165C with respect to the wiring layers165A and165B.

In the first semiconductor substrate101, at least a part of the control lines133for controlling the transistors of the pixels131, or a wiring layer170(fourth conductor layer) containing at least a part of the signal lines132for transmitting the pixel signals is formed. In the second semiconductor substrate102, an active element layer171including active elements such as the MOS transistor164is formed. At least a part of the control lines133or at least a part of the signal lines132may form at least a part of the Victim conductor loop (Victim conductor loop11or Victim conductor loop1101), but this is not the case.

As described with reference toFIG.6and the like, the wiring layer165A is arranged on the wiring layer170side of the first semiconductor substrate101, and the wiring layer165B is arranged on the active element layer171side.

In contrast to the arrangement of the wiring layers165A and165B, the wiring layer165C (conductor layer C) may be arranged between the wiring layer165B and the active element layer171as illustrated in A inFIG.120. In this case, the wiring layers are stacked in the order of the wiring layer170, the wiring layer165A, the wiring layer165B, the wiring layer165C, and the active element layer171from the first semiconductor substrate101side.

Alternatively, the wiring layer165C (conductor layer C) may be arranged between the wiring layer165A and the wiring layer165B, as illustrated in B inFIG.120. In this case, the wiring layers are stacked in the order of the wiring layer170, the wiring layer165A, the wiring layer165C, the wiring layer165B, and the active element layer171from the first semiconductor substrate101side.

Moreover, the wiring layer165C (conductor layer C) may be arranged between the wiring layer170and the wiring layer165A as illustrated in C inFIG.120. In this case, the wiring layers are stacked in the order of the wiring layer170, the wiring layer165C, the wiring layer165A, the wiring layer165B, and the active element layer171from the first semiconductor substrate101side.

Note thatFIG.120is diagrams illustrating the positional relationship among the three conductor layers of the wiring layers165A to165C, and the arrangement of a wiring layer170of the first semiconductor substrate101and an active element layer171of the second semiconductor substrate102may be reversed. Furthermore, the first semiconductor substrate101does not have to include either the signal line132or the control line133, and even in a case where the first semiconductor substrate101includes both the signal line132and the control line133, it is sufficient that at least a part of either the signal line132or the control line133is formed in the wiring layer170. Furthermore, the signal line132or the control line133may be provided in the second semiconductor substrate102instead of the first semiconductor substrate101. Furthermore, at least a part of the signal line132or the control line133may be included in the first semiconductor substrate101and the second semiconductor substrate102, and the signal line132or the control line133may straddle at least the first semiconductor substrate101and the second semiconductor substrate102, for example. Furthermore, at least one of the wiring layer165A, the wiring layer165B, or the wiring layer165C may be provided in the second semiconductor substrate102instead of the first semiconductor substrate101. Furthermore, the arrangement of the wiring layer170of the first semiconductor substrate101and the active element layer171of the second semiconductor substrate102may be omitted. Furthermore, the first semiconductor substrate101and the second semiconductor substrate102may not be separate bodies but may be integrally configured as one semiconductor substrate. Furthermore, the wiring layer170is interpreted as Victim conductor loop1101, the wiring layer165A is interpreted as Aggressor conductor loop1102A, and the wiring layer165B is interpreted as Aggressor conductor loop1102B, and the wiring layer165C may be arranged at an arbitrary position in the substrate arrangement examples illustrated inFIGS.109to112. The positional relationship among the three conductor layers of the wiring layers165A to165C is desirably the positional relationship illustrated inFIG.120but this is not the case.

<Problem of Case Having Three Conductor Layers>

In each of the above-described configuration examples, the wiring layout for shielding the hot carrier light emission from the active element group167and improving at least the inductive noise, the capacitive noise, or the voltage drop in the two conductor layers of the conductor layer A (wiring layer165A) and the conductor layer B (wiring layer165B) has been proposed. However, the inductive noise may further deteriorate depending on the wiring layout of the third conductor layer.

FIG.121is diagrams illustrating examples of wiring patterns of the wiring layer165C.

A inFIG.121illustrates the conductor layer C (wiring layer165C), B inFIG.121illustrates the conductor layer A (wiring layer165A), and C inFIG.121illustrates the conductor layer B (wiring layer165B).

Furthermore, D inFIG.121is a plan view of a stacked state of the conductor layer A and the conductor layer C, E inFIG.121is a plan view of a stacked state of the conductor layer B and the conductor layer C, and F inFIG.121is a plan view of a stacked state of the conductor layer A and the conductor layer B.

In the coordinate system inFIG.121, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

For the conductor layer A (wiring layer165A) and the conductor layer B (wiring layer165B) inFIG.121, the eleventh configuration example described with reference toFIG.36is adopted, which uses the reticulated conductor having the resistance value in the X direction (first direction) and the resistance value in the Y direction (second direction), which are different from each other.

The conductor layer A in B inFIG.121is configured by a reticulated conductor1201. The reticulated conductor1201has the conductor width WXA, the gap width GXA, and the conductor period FXA in the X direction, and the conductor width WYA, the gap width GYA, and the conductor period FYA in the Y direction. The reticulated conductor1201is a conductor having a shape in which basic patterns (first basic pattern) of the conductor period FXA and the conductor period FYA are repeatedly arranged on the same plane. The reticulated conductor1201is, for example, wiring (Vss wiring) connected to the GND or the negative power supply.

In the reticulated conductor1201, the conductor width WXA>the conductor width WYA and the gap width GYA>the gap width GXA. The gap region of the reticulated conductor1201has a shape longer in the Y direction than in the X direction, the resistance values are different between the X direction and the Y direction, and the resistance value in the Y direction is smaller than the resistance value in the X direction. Therefore, in the reticulated conductor1201, the current is more likely to flow in the Y direction than in the X direction.

The conductor layer B in C inFIG.121is configured by a reticulated conductor1202. The reticulated conductor1202has the conductor width WXB, the gap width GXB, and the conductor period FXB in the X direction, and the conductor width WYB, the gap width GYB, and the conductor period FYB in the Y direction. The reticulated conductor1202is a conductor having a shape in which basic patterns (second basic pattern) of the conductor period FXB and the conductor period FYB are repeatedly arranged on the same plane. The reticulated conductor1202is, for example, wiring (Vdd wiring) connected to the positive power supply.

In the reticulated conductor1202, the conductor width WXB>the conductor width WYB and the gap width GYB>the gap width GXB. The gap region of the reticulated conductor1202has a shape longer in the Y direction than in the X direction, the resistance values are different between the X direction and the Y direction, and the resistance value in the Y direction is smaller than the resistance value in the X direction. Therefore, in the reticulated conductor1202, the current is more likely to flow in the Y direction than in the X direction.

The reticulated conductor1201of the conductor layer A and the reticulated conductor1202of the conductor layer B form a differential structure. That is, as described in the eleventh configuration example and the like, the current distribution of the reticulated conductor1201of the conductor layer A and the current distribution of the reticulated conductor1202of the conductor layer B are substantially uniform and have opposite characteristics. Here, the substantially uniform is a difference in a range that can be regarded as uniform, but for example, the difference may be a difference in a range not exceeding at least twice. More specifically, an AC current substantially uniformly flows in ends of the reticulated conductor1201of the conductor layer A and the reticulated conductor1202of the conductor layer B, and current directions are opposite between the reticulated conductor1201and the reticulated conductor1202. As a result, the magnetic field generated by the current distribution of the reticulated conductor1201and the magnetic field generated by the current distribution of the reticulated conductor1202are effectively canceled. As a result, the inductive noise can be suppressed.

Furthermore, as illustrated in F inFIG.121, an opened region is no longer present due to the stacked layer of the conductor layer A and the conductor layer B. Therefore, the hot carrier light emission from the active element group167can be shielded.

Meanwhile, the conductor layer C in A inFIG.121is a conductor layer having a low sheet resistance through which a current easily flows, and a linear conductor1211A long in the X direction and a linear conductor1211B long in the X direction are alternately and periodically arranged in the Y direction. The linear conductor1211A is, for example, wiring (Vss wiring) connected to the GND or the negative power supply. The linear conductor1211B is, for example, wiring (Vdd wiring) connected to the positive power supply. The linear conductor1211A is connected to, for example, a pad (not illustrated) on an outer periphery of the semiconductor substrate, and is electrically connected to the reticulated conductor1201of the conductor layer A. The reticulated conductor1201of the conductor layer A and the linear conductor1211A of the conductor layer C may be electrically connected via, for example, a conductor via (VIA) extending in the Z direction. The linear conductor1211B is connected to, for example, a pad (not illustrated) on an outer periphery of the semiconductor substrate, and is electrically connected to the reticulated conductor1202of the conductor layer B. The reticulated conductor1202of the conductor layer B and the linear conductor1211B of the conductor layer C may be electrically connected via, for example, a conductor via (VIA) extending in the Z direction.

The linear conductor1211A has a conductor width WYCA in the Y direction and the linear conductor1211B has a conductor width WYCB in the Y direction, and the conductor width WYCA of the linear conductor1211A is larger than the conductor width WYCB of the linear conductor1211B (conductor width WYCA>conductor width WYCB). There is a gap with a gap width GYC between the linear conductor1211A and the linear conductor1211B in the Y direction. Then, the one linear conductor1211A and the one linear conductor1211B are periodically arranged in the Y direction with a conductor period FYC (=the conductor width WYCA+the conductor width WYCB+2×the gap width GYC).

When the conductor layer C in which the linear conductor1211A and the linear conductor1211B are periodically arranged in the Y direction in the conductor period FYC is viewed in a predetermined plane range (plane region), the sum of the conductor widths WYCA of a plurality of linear conductors1211A and the sum of the conductor widths WYCB of a plurality of linear conductors1211B in the predetermined plane range are significantly different because the conductor width WYCA of the linear conductor1211A and the conductor width WYCB of the linear conductor1211B are different. In this case, since the current distribution of the linear conductor1211A and the current distribution of the linear conductor1211B are significantly different, generation of the inductive noise cannot be suppressed and the inductive noise is deteriorated. Specifically, since the resistance value in the X direction significantly differs between the linear conductor1211A and the linear conductor1211B, the current distribution significantly differs between the linear conductor1211A and the linear conductor1211B, and the total amount of current flowing through the linear conductor1211A becomes larger than the total amount of current flowing through the linear conductor1211B. Furthermore, the total amount of current flowing through the reticulated conductor1202becomes larger than the total amount of current flowing through the reticulated conductor1201according to the law of current conservation (Kirchhoff's first law). As a result, since the current distribution significantly differs between the reticulated conductor1201and the reticulated conductor1202, generation of the inductive noise cannot be suppressed and the inductive noise is deteriorated.

Therefore, the effect of suppressing the inductive noise in the two conductor layers of the conductor layer A or the conductor layer B is reduced depending on the wiring layout of the conductor layer C.

Therefore, hereinafter, a configuration of effectively reducing the inductive noise in a case of having a stacked structure of the three conductor layers of the wiring layers165A to165C will be described. Note that the configuration examples inFIG.121are not excluded because the configuration examples inFIG.121may be applicable depending on the magnitude of the inductive noise.

First Configuration Example of Three-Layer Conductor Layer

FIG.122illustrates a first configuration example of a three-layer conductor layer.

A inFIG.122illustrates the conductor layer C (wiring layer165C), B inFIG.122illustrates the conductor layer A (wiring layer165A), and C inFIG.122illustrates the conductor layer B (wiring layer165B).

Furthermore, D inFIG.122is a plan view of a stacked state of the conductor layer A and the conductor layer C, E inFIG.122is a plan view of a stacked state of the conductor layer B and the conductor layer C, and F inFIG.122is a plan view of a stacked state of the conductor layer A and the conductor layer B.

The conductor layer A in B inFIG.122is configured by the same reticulated conductor1201as inFIG.121. That is, the reticulated conductor1201has the conductor width WXA, the gap width GXA, and the conductor period FXA in the X direction, and the conductor width WYA, the gap width GYA, and the conductor period FYA in the Y direction. The reticulated conductor1201is a conductor having a shape in which basic patterns (first basic pattern) of the conductor period FXA and the conductor period FYA are repeatedly arranged on the same plane. The reticulated conductor1201is, for example, wiring (Vss wiring) connected to the GND or the negative power supply.

The conductor layer B in C inFIG.122is configured by the same reticulated conductor1202as inFIG.121. That is, the reticulated conductor1202has the conductor width WXB, the gap width GXB, and the conductor period FXB in the X direction, and the conductor width WYB, the gap width GYB, and the conductor period FYB in the Y direction. The reticulated conductor1202is a conductor having a shape in which basic patterns (second basic pattern) of the conductor period FXB and the conductor period FYB are repeatedly arranged on the same plane. The reticulated conductor1202is, for example, wiring (Vdd wiring) connected to the positive power supply. The conductor periods of the reticulated conductor1201and the reticulated conductor1202are the same. That is, the conductor period FXA=the conductor period FXB and the conductor period FYA=the conductor period FYB. In addition, the conductor periods may be substantially the same. Here, the substantially the same is a difference in a range that can be regarded as the same, but for example, the difference may be a difference in a range not exceeding at least twice.

The conductor layer C in A inFIG.122is a conductor layer having a low sheet resistance through which a current easily flows, and a linear conductor1221A (third basic pattern) long in the X direction and a linear conductor1221B (fourth basic pattern) long in the X direction are alternately and periodically arranged in the Y direction.

The linear conductor1221A is, for example, wiring (Vss wiring) connected to the GND or the negative power supply. The linear conductor1221B is, for example, wiring (Vdd wiring) connected to the positive power supply. The linear conductor1221A and the linear conductor1221B are differential conductors (differential structure) having the current directions opposite to each other. The linear conductor1221A is connected to, for example, a pad (not illustrated) on an outer periphery of the semiconductor substrate, and is electrically connected to the reticulated conductor1201of the conductor layer A. The reticulated conductor1201of the conductor layer A and the linear conductor1221A of the conductor layer C may be electrically connected via, for example, a conductor via (VIA) extending in the Z direction. The linear conductor1221B is connected to, for example, a pad (not illustrated) on an outer periphery of the semiconductor substrate, and is electrically connected to the reticulated conductor1202of the conductor layer B. The reticulated conductor1202of the conductor layer B and the linear conductor1221B of the conductor layer C may be electrically connected via, for example, a conductor via (VIA) extending in the Z direction.

The linear conductor1221A has the conductor width WYCA in the Y direction and the linear conductor1221B has the conductor width WYCB in the Y direction, and the conductor width WYCA of the linear conductor1221A is the same as the conductor width WYCB of the linear conductor1221B (conductor width WYCA=conductor width WYCB). Note that the conductor width WYCA and the conductor width WYCB may not be the same or may be substantially the same (the conductor width WYCA z the conductor width WYCB). There is a gap with the gap width GYC between the linear conductor1221A and the linear conductor1221B in the Y direction.

Then, the one linear conductor1221A and the one linear conductor1221B are periodically arranged in the Y direction with the conductor period FYC (=the conductor width WYCA+the conductor width WYCB+2×the gap width GYC). The conductor period FYC of the linear conductor1221A and the conductor period FYC of the linear conductor1221B are the same or substantially the same.

Furthermore, the conductor period FYC that is a repetition period of the linear conductor1221A of the conductor layer C is an integral multiple of the conductor period FYA that is a repetition period in the Y direction of the reticulated conductor1201of the conductor layer A.FIG.122illustrates an example in which the conductor period FYC is twice the conductor period FYA.

The conductor period FYC that is a repetition period of the linear conductor1221B of the conductor layer C is an integral multiple of the conductor period FYB that is a repetition period in the Y direction of the reticulated conductor1202of the conductor layer B.FIG.122illustrates an example in which the conductor period FYC is twice the conductor period FYB.

Note that the conductor width WYCA, the conductor width WYCB, and the gap width GYC can be designed to arbitrary values.

When the conductor layer C in which the linear conductor1221A and the linear conductor1221B are periodically arranged in the Y direction in the conductor period FYC is viewed in a predetermined plane range (plane region), the sum of the conductor widths WYCA of a plurality of linear conductors1221A and the sum of the conductor widths WYCB of a plurality of linear conductors1221B in the predetermined plane range are the same or substantially the same because the conductor width WYCA of the linear conductor1221A and the conductor width WYCB of the linear conductor1221B are the same or substantially the same. As a result, the current distribution of the linear conductor1221A and the current distribution of the linear conductor1221B become the same or substantially the same, so that generation of inductive noise can be suppressed.

Furthermore, in a case where the conductor layer C is arranged near the wiring layer170, as illustrated in C inFIG.120, for example, the capacitive noise due to capacitive coupling between the linear conductor1221A and the linear conductor1221B of the conductor layer C, and the signal line132and the control line133of the wiring layer170can occur. However, since the linear conductor1221A and the linear conductor1221B have the same wiring pattern repeated in the Y direction, the capacitive noise can be completely canceled in the Y direction. The capacitive noise can be significantly improved as the conductor layer C is closer to the wiring layer170.

As illustrated in F inFIG.122, the stacked layer of the conductor layers A and B has a light-shielding structure, and the hot carrier light emission from the active element group167can be shielded. In addition, as illustrated in D and E inFIG.122, the stacked layer of the conductor layers A and C and the stacked layer of the conductor layers B and C have also a light-shielding structure, and the light-shielding property is maintained. Thereby, since the light-shielding restrictions of the conductor layers A and B can be significantly alleviated, the conductive area of the conductor layers A and B can be used to the maximum, the wiring resistance can be lowered, and the voltage drop can be further improved. Furthermore, the degree of freedom in layout of the conductor layers A and B can be improved.

Moreover, in the case where the reticulated conductor1201of the conductor layer A and the linear conductor1221A of the conductor layer C are electrically connected, and the reticulated conductor1202of the conductor layer B and the linear conductor1221B of the conductor layer C are electrically connected, the current amount of the conductor layers A and B can be made small. Therefore, the inductive noise and the voltage drop from the conductor layer A or B can be further improved.

Second Configuration Example of Three-Layer Conductor Layer

FIG.123illustrates a second configuration example of the three-layer conductor layer.

A inFIG.123illustrates the conductor layer C (wiring layer165C), B inFIG.123illustrates the conductor layer A (wiring layer165A), and C inFIG.123illustrates the conductor layer B (wiring layer165B).

Furthermore, D inFIG.123is a plan view of a stacked state of the conductor layer A and the conductor layer C, E inFIG.123is a plan view of a stacked state of the conductor layer B and the conductor layer C, and F inFIG.123is a plan view of a stacked state of the conductor layer A and the conductor layer B.

The conductor layer A in B inFIG.123is a reticulated conductor1201that is the same as the first configuration example inFIG.122, and the conductor layer B in C inFIG.123is a reticulated conductor1202that is the same as the first configuration example inFIG.122. Therefore, description thereof is omitted.

The conductor layer C in A inFIG.123is configured such that two linear conductors1222A long in the X direction and two linear conductors1222B long in the X direction are alternately and periodically arranged in the Y direction.

The linear conductor1222A is, for example, wiring (Vss wiring) connected to the GND or the negative power supply. The linear conductor1222B is, for example, wiring (Vdd wiring) connected to the positive power supply. The linear conductor1222A and the linear conductor1222B are differential conductors whose current directions are opposite to each other. The linear conductor1222A is connected to, for example, a pad (not illustrated) on an outer periphery of the semiconductor substrate, and is electrically connected to the reticulated conductor1201of the conductor layer A. The reticulated conductor1201of the conductor layer A and the linear conductor1222A of the conductor layer C may be electrically connected via, for example, a conductor via (VIA) extending in the Z direction. The linear conductor1222B is connected to, for example, a pad (not illustrated) on an outer periphery of the semiconductor substrate, and is electrically connected to the reticulated conductor1202of the conductor layer B. The reticulated conductor1202of the conductor layer B and the linear conductor1222B of the conductor layer C may be electrically connected via, for example, a conductor via (VIA) extending in the Z direction.

The linear conductor1222A has the conductor width WYCA in the Y direction and the linear conductor1222B has the conductor width WYCB in the Y direction, and the conductor width WYCA of the linear conductor1222A is the same as the conductor width WYCB of the linear conductor1222B (conductor width WYCA=conductor width WYCB). Note that the conductor width WYCA and the conductor width WYCB may not be the same or may be substantially the same (the conductor width WYCA z the conductor width WYCB). There is a gap with the gap width GYC between the linear conductors1222A adjacent in the Y direction, between the linear conductors1222B adjacent in the Y direction, or between the linear conductors1222A and the linear conductors1222B.

Then, the two linear conductors1222A and the two linear conductors1222B are periodically arranged in the Y direction with a conductor period FYC (=2×the conductor width WYCA+2×the conductor width WYCB+4×the gap width GYC). In other words, the conductor period FYC of the two linear conductors1222A and the conductor period FYC of the two linear conductors1222B are the same or substantially the same.

Note that the conductor width WYCA, the conductor width WYCB, and the gap width GYC can be designed to arbitrary values. Furthermore,FIG.123illustrates an example in which the two linear conductors1222A and two linear conductors1222B are periodically arranged. However, the configuration is not limited thereto, and three or more linear conductors may be periodically arranged, for example. Furthermore,FIG.123illustrates an example in which the same numbers of linear conductors1222A and linear conductors1222B are periodically arranged. However, the configuration is not limited thereto, and different numbers of linear conductors1222A and linear conductors1222B may be periodically arranged.

When the conductor layer C in which the linear conductor1222A and the linear conductor1222B are periodically arranged in the Y direction in the conductor period FYC is viewed in a predetermined plane range (plane region), the sum of the conductor widths WYCA of a plurality of linear conductors1222A and the sum of the conductor widths WYCB of a plurality of linear conductors1222B in the predetermined plane range are the same or substantially the same because the conductor width WYCA of the linear conductor1222A and the conductor width WYCB of the linear conductor1222B are the same or substantially the same. As a result, the current distribution of the linear conductor1222A and the current distribution of the linear conductor1222B become the same or substantially the same, so that generation of inductive noise can be suppressed.

Furthermore, in a case where the conductor layer C is arranged near the wiring layer170, as illustrated in C inFIG.120, for example, the capacitive noise due to capacitive coupling between the linear conductor1222A and the linear conductor1222B of the conductor layer C, and the signal line132and the control line133of the wiring layer170can occur. However, since the linear conductor1222A and the linear conductor1222B have the same wiring pattern repeated in the Y direction, the capacitive noise can be completely canceled in the Y direction. The capacitive noise can be significantly improved as the conductor layer C is closer to the wiring layer170.

As illustrated in F inFIG.123, the stacked layer of the conductor layers A and B has a light-shielding structure, and the hot carrier light emission from the active element group167can be shielded, and as illustrated in D and E inFIG.123, the light-shielding property is maintained in a fixed range in the stacked layer of the conductor layers A and C and the stacked layer of the conductor layers B and C. Thereby, since the light-shielding restrictions of the conductor layers A and B can be alleviated, the conductive area of the conductor layers A and B can be used to the maximum, the wiring resistance can be lowered, and the voltage drop can be further improved. Furthermore, the degree of freedom in layout of the conductor layers A and B can be improved.

Moreover, in the case where the reticulated conductor1201of the conductor layer A and the linear conductor1222A of the conductor layer C are electrically connected, and the reticulated conductor1202of the conductor layer B and the linear conductor1222B of the conductor layer C are electrically connected, the current amount of the conductor layers A and B can be made small. Therefore, the inductive noise and the voltage drop from the conductor layer A or B can be further improved.

Modification of Second Configuration Example of Three-Layer Conductor Layer

FIG.124illustrates a first modification of the second configuration example of the three-layer conductor layer.

A to F inFIG.124correspond to A to F inFIG.123, respectively, and description of common parts having the same reference numerals will be omitted as appropriate, and different parts will be described.

In the second configuration example inFIG.123, in the conductor layer C, the conductor widths WYCA in the Y direction of the two linear conductors1222A adjacent in the Y direction are the same. In contrast, in the first modification inFIG.124, the conductor widths of the two linear conductors1222A adjacent in the Y direction are different, which are a conductor width WYCA1 and a conductor width WYCA2 (conductor width WYCA1<conductor width WYCA2). Note that the conductor width WYCA1 and the conductor width WYCA2 can be designed to arbitrary values.

Similarly, in the second configuration example inFIG.123, in the conductor layer C, the conductor widths WYCB in the Y direction of the two linear conductors1222B adjacent in the Y direction are the same. In contrast, in the first modification inFIG.124, the conductor widths of the two linear conductors1222B adjacent in the Y direction are different, which are a conductor width WYCB1 and a conductor width WYCB2 (conductor width WYCB1<conductor width WYCB2). Note that the conductor width WYCB1 and the conductor width WYCB2 can be designed to arbitrary values.

The configuration of the first modification inFIG.124is similar to the second configuration example inFIG.123except for the difference in the conductor widths of the linear conductors1222A and1222B.

FIG.125illustrates a second modification of the second configuration example of the three-layer conductor layer.

A to F inFIG.125correspond to A to F inFIG.123, respectively, and description of common parts having the same reference numerals will be omitted as appropriate, and different parts will be described.

The second modification inFIG.125is different from the second configuration example inFIG.123and is common to the first modification inFIG.124in that the conductor widths of the two linear conductors1222A adjacent in the Y direction are different are different in the conductor layer C. Furthermore, the second modification inFIG.125is different from the second configuration example inFIG.123and is common to the first modification inFIG.124in that the conductor widths of the two linear conductors1222B adjacent in the Y direction are different

Meanwhile, in the first modification inFIG.124, the arrangement of the two linear conductors1222A having different conductor widths is the same as the arrangement of the two linear conductors1222B. Specifically, in a case where the two linear conductors1222A are arranged in the Y direction in the order of the linear conductor1222A with a narrow conductor width (with the conductor width WYCA1) and the linear conductor1222A with a wide conductor width (with the conductor width WYCA2), the two linear conductors1222B are also arranged in the Y direction in the order of the linear conductor1222B with a narrow conductor width (with the conductor width WYCB1) and the linear conductor1222B with a wide conductor width (with the conductor width WYCB2)

In contrast, in the second modification inFIG.125, the arrangement of the two linear conductors1222A having different conductor widths is different from the arrangement of the two linear conductors1222B. Specifically, in a case where the two linear conductors1222A are arranged in the Y direction in the order of the linear conductor1222A with a narrow conductor width (with the conductor width WYCA1) and the linear conductor1222A with a wide conductor width (with the conductor width WYCA2), the two linear conductors1222B are arranged in the Y direction in the order of the linear conductor1222B with a wide conductor width (with the conductor width WYCB1) and the linear conductor1222B with a narrow conductor width (with the conductor width WYCB2) In other words, the two linear conductors1222A and1222B with different conductor widths are arranged mirror-symmetrically in the Y direction.

The configuration of the second modification inFIG.125is similar to the second configuration example inFIG.123except for the difference in the conductor widths of the linear conductors1222A and1222B.

Even in the first modification and the second modification inFIGS.124and125, when the conductor layer C is viewed in a predetermined plane range (plane region), the sum of the conductor widths WYCA1 and WYCA2 of a plurality of linear conductors1222A and the sum of the conductor widths WYCB1 and WYCB2 of a plurality of linear conductors1222B in the predetermined plane range are the same or substantially the same. As a result, the current distribution of the linear conductor1222A and the current distribution of the linear conductor1222B become the same or substantially the same, so that generation of inductive noise can be suppressed.

Even in the first modification and the second modification inFIGS.124and125, the capacitive noise can be significantly improved and the light-shielding restriction of the conductor layers A and B can be alleviated. Furthermore, the wiring resistance can be lowered and the voltage drop can be improved. Moreover, the degree of freedom in layout of the conductor layers A and B can be improved.

Third Configuration Example of Three-Layer Conductor Layer

FIG.126illustrates a third configuration example of the three-layer conductor layer.

A inFIG.126illustrates the conductor layer C (wiring layer165C), B inFIG.126illustrates the conductor layer A (wiring layer165A), and C inFIG.126illustrates the conductor layer B (wiring layer165B).

Furthermore, D inFIG.126is a plan view of a stacked state of the conductor layer A and the conductor layer C, E inFIG.126is a plan view of a stacked state of the conductor layer B and the conductor layer C, and F inFIG.126is a plan view of a stacked state of the conductor layer A and the conductor layer B.

The conductor layer A in B inFIG.126is a reticulated conductor1201that is the same as the first configuration example inFIG.122, and the conductor layer B in C inFIG.126is a reticulated conductor1202that is the same as the first configuration example inFIG.122. Therefore, description thereof is omitted.

The conductor layer C in A inFIG.126is similar to the first configuration example inFIG.122in that a linear conductor1223A long in the X direction and a linear conductor1223B long in the X direction are alternately and periodically arranged in the Y direction. Note that, in the first configuration example inFIG.122, the conductor widths of the linear conductors1221A arranged in order in the Y direction are all the same, which are the conductor width WYCA.

In contrast, in the third configuration example inFIG.126, among the linear conductors1223A and the linear conductors1223B alternately and periodically arranged in the Y direction, for the linear conductors1223A, the linear conductors1223A having the different conductor width WYCA1 and conductor width WYCA2 are alternately arranged in the Y direction, whereas, for the linear conductors1223B, the linear conductors1223A having the same conductor width WYCB are arranged.

The third configuration example inFIG.126is similar to the first configuration example inFIG.122except for the difference in the conductor widths of the linear conductors1223A and1223B.

That is, the linear conductor1223A is, for example, wiring (Vss wiring) connected to the GND or the negative power supply. The linear conductor1223B is, for example, a wiring (Vdd wiring) connected to the positive power supply. The linear conductor1223A and the linear conductor1223B are differential conductors whose current directions are opposite to each other. The linear conductor1223A is connected to, for example, a pad (not illustrated) on an outer periphery of the semiconductor substrate, and is electrically connected to the reticulated conductor1201of the conductor layer A. The reticulated conductor1201of the conductor layer A and the linear conductor1223A of the conductor layer C may be electrically connected via, for example, a conductor via (VIA) extending in the Z direction. The linear conductor1223B is connected to, for example, a pad (not illustrated) on an outer periphery of the semiconductor substrate, and is electrically connected to the reticulated conductor1202of the conductor layer B. The reticulated conductor1202of the conductor layer B and the linear conductor1223B of the conductor layer C may be electrically connected via, for example, a conductor via (VIA) extending in the Z direction.

There is a gap with the gap width GYC between the linear conductor1223A and the linear conductor1223B adjacent in the Y direction. Then, the two linear conductors1223A and the two linear conductors1223B are periodically arranged in the Y direction with the conductor period FYC (=the conductor width WYCA1+the conductor width WYCA2+2×the conductor width WYCB+4×the gap width GYC). Note that the conductor width WYCA1, the conductor width WYCA2, the conductor width WYCB, and the gap width GYC can be designed to any values. Furthermore,FIG.126illustrates an example in which the two linear conductors1223A and two linear conductors1223B are periodically arranged. However, the configuration is not limited thereto, and three or more linear conductors may be periodically arranged, for example. Furthermore,FIG.126illustrates an example in which the same numbers of linear conductors1223A and linear conductors1223B are periodically arranged. However, the configuration is not limited thereto, and different numbers of linear conductors1223A and linear conductors1223B may be periodically arranged.

When the conductor layer C in which the linear conductor1223A and the linear conductor1223B are periodically arranged in the Y direction in the conductor period FYC is viewed in a predetermined plane range (plane region), the sum of the conductor widths WYCA1 and WYCA2 of a plurality of linear conductors1223A and the sum of the conductor widths WYCB of a plurality of linear conductors1223B in the predetermined plane range are the same or substantially the same. As a result, the current distribution of the linear conductor1223A and the current distribution of the linear conductor1223B become the same or substantially the same, so that generation of inductive noise can be suppressed.

Even in the third configuration example inFIG.126, the capacitive noise can be significantly improved and the light-shielding restriction of the conductor layers A and B can be alleviated. Furthermore, the wiring resistance can be lowered and the voltage drop can be improved. Moreover, the degree of freedom in layout of the conductor layers A and B can be improved.

Modification of Third Configuration Example of Three-Layer Conductor Layer

FIG.127illustrates a modification of the third configuration example of the three-layer conductor layer.

A to F inFIG.127correspond to A to F inFIG.126, respectively, and description of common parts having the same reference numerals will be omitted as appropriate, and different parts will be described.

In the third configuration example inFIG.126, there are two types of conductor widths: the conductor width WYCA1 and the conductor width WYCA2 for the conductor widths of the linear conductors1223A, and the linear conductors1223B have the same conductor width WYCB, among the linear conductors1223A and the linear conductors1223B alternately and periodically arranged in the Y direction in the conductor layer C.

In contrast, in the modification of the third configuration example inFIG.127, the linear conductors1223A have the same conductor width WYCA, and there are two types of conductor widths: the conductor width WYCB1 and the conductor width WYCB2 for the conductor widths of the linear conductors1223B, among the linear conductors1223A and the linear conductors1223B alternately and periodically arranged in the Y direction in the conductor layer C. In the modification of the third configuration example inFIG.127, the linear conductors1223B having different conductor width WYCB1 and conductor width WYCB2 are alternately arranged in the Y direction.

The modification of the third configuration example inFIG.127is similar to the third configuration example inFIG.126except for the difference in the conductor widths of the linear conductors1223A and1223B.

When the conductor layer C in which the linear conductor1223A and the linear conductor1223B are periodically arranged in the Y direction in the conductor period FYC is viewed in a predetermined plane range (plane region), the sum of the conductor widths WYCA of a plurality of linear conductors1223A and the sum of the conductor widths WYCB1 and WYCB2 of a plurality of linear conductors1223B in the predetermined plane range are the same or substantially the same. As a result, the current distribution of the linear conductor1223A and the current distribution of the linear conductor1223B become the same or substantially the same, so that generation of inductive noise can be suppressed.

Even in the modification of the third configuration example inFIG.127, the capacitive noise can be significantly improved and the light-shielding restriction of the conductor layers A and B can be alleviated. Furthermore, the wiring resistance can be lowered and the voltage drop can be improved. Moreover, the degree of freedom in layout of the conductor layers A and B can be improved.

Fourth Configuration Example of Three-Layer Conductor Layer

FIG.128illustrates a fourth configuration example of the three-layer conductor layer.

A inFIG.128illustrates the conductor layer C (wiring layer165C), B inFIG.128illustrates the conductor layer A (wiring layer165A), and C inFIG.128illustrates the conductor layer B (wiring layer165B).

Furthermore, D inFIG.128is a plan view of a stacked state of the conductor layer A and the conductor layer C, E inFIG.128is a plan view of a stacked state of the conductor layer B and the conductor layer C, and F inFIG.128is a plan view of a stacked state of the conductor layer A and the conductor layer B.

In the fourth configuration example inFIG.128, a portion corresponding to that in the first configuration example illustrated inFIG.122is given the same reference numeral and description of the portion is omitted as appropriate, and description will be given focusing on different portions.

The conductor layer C in A inFIG.128is similar to the conductor layer C of the first configuration example illustrated inFIG.122. That is, the conductor layer C is configured such that a linear conductor1221A long in the X direction and a linear conductor1221B long in the X direction are alternately and periodically arranged in the Y direction with the conductor period FYC.

The conductor layer A in B inFIG.128has the same reticulated conductor1201as inFIG.121. Furthermore, the conductor layer A includes a relay conductor1241(first relay conductor) inside the gap having the gap width GXA in the X direction and the gap width GYA in the Y direction of the reticulated conductor1201. The relay conductor1241is arranged one-to-one in all the gaps of the reticulated conductor1201. The distance between the relay conductors1241, in other words, the period of the relay conductor1241is also the conductor periods FXA and FYA.

The relay conductor1241is, for example, wiring (Vdd wiring) connected to the positive power supply, and electrically connects the reticulated conductor1202of the conductor layer B and the linear conductor1221B of the conductor layer C via, for example, the conductor via (VIA) extending in the Z direction, in the case of the stacking order illustrated in C inFIG.120. In other words, the reticulated conductor1202of the conductor layer B and the linear conductor1221B of the conductor layer C are electrically connected via the relay conductor1241of the conductor layer A. Furthermore, the relay conductor1241may electrically connect the reticulated conductor1202of the conductor layer B and a conductor of a conductor layer different from the conductor layers A to C via, for example, the conductor via (VIA) extending in the Z direction, in the case of the stacking order illustrated in A inFIG.120. Furthermore, the relay conductor1241may electrically connect the linear conductor1221B of the conductor layer C and a conductor of a conductor layer different from the conductor layers A to C via, for example, the conductor via (VIA) extending in the Z direction, in the case of the stacking order illustrated in B inFIG.120. Furthermore, not all the relay conductors1241may be used for electrical connection, all the relay conductors1241may be used for electrical connection, or some of the relay conductors1241may be used for electrical connection.

By providing the relay conductor1241, it becomes possible to connect the reticulated conductor1202and the linear conductor1221B in the substantially shortest distance or a short distance to draw the power supply, thereby reducing the voltage drop, energy loss, or inductive noise.

The conductor layer B in C inFIG.128has the same reticulated conductor1202as inFIG.121. Furthermore, the conductor layer B includes a relay conductor1242(second relay conductor) inside the gap having the gap width GXB in the X direction and the gap width GYB in the Y direction of the reticulated conductor1202. The relay conductor1242is arranged one-to-one in all the gaps of the reticulated conductor1202. The distance between the relay conductors1242, in other words, the period of the relay conductors1242is also the conductor periods FXB and FYB.

The relay conductor1242is, for example, wiring (Vss wiring) connected to GND or the negative power supply, and electrically connects the reticulated conductor1201of the conductor layer A and the linear conductor1221A of the conductor layer C via, for example, the conductor via (VIA) extending in the Z direction, in the case of the stacking layer illustrated in A inFIG.120. In other words, the reticulated conductor1201of the conductor layer B and the linear conductor1221A of the conductor layer C are electrically connected via the relay conductor1242of the conductor layer B. Furthermore, the relay conductor1242may electrically connect the reticulated conductor1201of the conductor layer A and a conductor of a conductor layer different from the conductor layers A to C via, for example, the conductor via (VIA) extending in the Z direction, in the case of the stacking order illustrated in C inFIG.120. Furthermore, the relay conductor1242may electrically connect the linear conductor1221A of the conductor layer C and a conductor of a conductor layer different from the conductor layers A to C via, for example, the conductor via (VIA) extending in the Z direction, in the case of the stacking order illustrated in B inFIG.120. Furthermore, not all the relay conductors1242may be used for electrical connection, all the relay conductors1242may be used for electrical connection, or some of the relay conductors1242may be used for electrical connection.

By providing the relay conductor1242, it becomes possible to connect the reticulated conductor1201and the linear conductor1221A in the substantially shortest distance or a short distance, thereby reducing the voltage drop, energy loss, or inductive noise.

Furthermore, since the linear conductor1221A and the linear conductor1221B in A inFIG.128are conductors long in the X direction, the direction in which the current easily flows is the X direction. Furthermore, the direction in which the current of the reticulated conductors1201and1202in B and C inFIG.128is likely to flow is the Y direction. Therefore, the direction in which the current of the conductor layer C is likely to flow and the direction in which the current of the conductor layers A and B is likely to flow are substantially orthogonal and differ by approximately 90 degrees. As a result, the current becomes easily diffused (the current is less likely to be concentrated), so that the inductive noise can be further improved.

As illustrated in F inFIG.128, the stacked layer of the conductor layers A and B has a light-shielding structure. Furthermore, as illustrated in D and E inFIG.128, the stacked layer of the conductor layers A and C and the stacked layer of the conductor layers B and C have a light-shielding structure, and the light-shielding property is maintained. As a result, the hot carrier light emission from the active element group167can be shielded. Furthermore, since the light-shielding restrictions of the conductor layers A and B can be significantly alleviated, the conductive area of the conductor layers A and B can be used to the maximum, the wiring resistance can be lowered, and the voltage drop can be further improved. The degree of freedom in layout of the conductor layers A and B can be improved.

Modification of Fourth Configuration Example of Three-Layer Conductor Layer

FIG.129illustrates a first modification of the fourth configuration example of the three-layer conductor layer.

A inFIG.129illustrates the conductor layer C (wiring layer165C), B inFIG.129illustrates the conductor layer A (wiring layer165A), and C inFIG.129illustrates the conductor layer B (wiring layer165B).

Furthermore, D inFIG.129is a plan view of a stacked state of the conductor layer A and the conductor layer C, E inFIG.129is a plan view of a stacked state of the conductor layer B and the conductor layer C, and F inFIG.129is a plan view of a stacked state of the conductor layer A and the conductor layer B.

InFIG.129, a portion corresponding to that in the fourth configuration example illustrated inFIG.128is given the same reference numeral and description of the portion is omitted as appropriate, and description will be given focusing on different portions.

In the first modification of the fourth configuration example, only the configuration of the conductor layer C in A inFIG.129is different from that inFIG.128.

In the conductor layer C in A inFIG.128, the linear conductor1221A long in the X direction and the linear conductor1221B long in the X direction have been alternately and periodically arranged in the Y direction with the conductor period FYC. Furthermore, the direction in which the current of the conductor layer C is likely to flow and the direction in which the current of the conductor layers A and B is likely to flow are substantially orthogonal and differ by approximately 90 degrees.

In contrast, in the conductor layer C in A inFIG.129, a linear conductor1251A long in the Y direction and a linear conductor1251B long in the Y direction are alternately and periodically arranged in the X direction.

Furthermore, since the linear conductor1251A and the linear conductor1251B in A inFIG.129are conductors long in the Y direction, the direction in which the current easily flows is the Y direction. Furthermore, the direction in which the current of the reticulated conductors1201and1202in B and C inFIG.128is likely to flow is the Y direction. Thereby, the direction in which the current of the conductor layer C is likely to flow and the direction in which the current of the conductor layers A and B is likely to flow are the same or substantially the same. In this case, the voltage drop can be further improved depending on the wiring layout. Approximately 90 degrees and substantially the same direction is a difference between two directions being 90 degrees or a range that can be regarded as the same angle. The difference is at least less than 45 degrees with respect to 90 degrees or the same angle.

The linear conductor1251A is, for example, wiring (Vss wiring) connected to the GND or the negative power supply. The linear conductor1251B is, for example, wiring (Vdd wiring) connected to the positive power supply. The linear conductor1251A and the linear conductor1251B are differential conductors whose current directions are opposite to each other. The linear conductor1251A is connected to, for example, a pad (not illustrated) on an outer periphery of the semiconductor substrate, and is electrically connected to the reticulated conductor1201of the conductor layer A. The reticulated conductor1201of the conductor layer A and the linear conductor1251A of the conductor layer C may be electrically connected via, for example, a conductor via (VIA) extending in the Z direction. The linear conductor1251B is connected to, for example, a pad (not illustrated) on an outer periphery of the semiconductor substrate, and is electrically connected to the reticulated conductor1202of the conductor layer B. The reticulated conductor1202of the conductor layer B and the linear conductor1251B of the conductor layer C may be electrically connected via, for example, a conductor via (VIA) extending in the Z direction.

The linear conductor1251A has a conductor width WXCA in the X direction and the linear conductor1251B has a conductor width WXCB in the X direction, and the conductor width WXCA of the linear conductor1251A and the conductor width WXCB of the linear conductor1251B are the same or substantially the same (the conductor width WXCA=the conductor width WXCB or the conductor width WXCA z the conductor width WXCB). There is a gap with a gap width of GXC between the linear conductor1251A and the linear conductor1251B in the Y direction.

Then, the one linear conductor1251A and the one linear conductor1251B are periodically arranged in the X direction with a conductor period FXC (=the conductor width WXCA+the conductor width WXCB+2×the gap width GXC). In other words, the conductor period FXC of the linear conductor1251A and the conductor period FXC of the linear conductor1251B are the same or substantially the same.

Furthermore, the conductor period FXC that is a repetition period of the linear conductor1251A of the conductor layer C is an integral multiple of the conductor period FXA that is a repetition period in the X direction of the reticulated conductor1201of the conductor layer A.FIG.129illustrates an example in which the conductor period FXC is twice the conductor period FYA.

The conductor period FXC that is a repetition period of the linear conductor1251B of the conductor layer C is an integral multiple of the conductor period FXB that is a repetition period in the X direction of the reticulated conductor1202of the conductor layer B.FIG.129illustrates an example in which the conductor period FXC is twice the conductor period FXB.

Note that the conductor width WXCA, the conductor width WXCB, and the gap width GXC can be designed to arbitrary values.

When the conductor layer C in which the linear conductor1251A and the linear conductor1251B are periodically arranged in the X direction in the conductor period FXC is viewed in a predetermined plane range (plane region), the sum of the conductor widths WXCA of a plurality of linear conductors1251A and the sum of the conductor widths WXCB of a plurality of linear conductors1251B in the predetermined plane range are the same or substantially the same because the conductor width WXCA of the linear conductor1251A and the conductor width WXCB of the linear conductor1251B are the same or substantially the same. As a result, the current distribution of the linear conductor1251A and the current distribution of the linear conductor1251B become the same or substantially the same, so that generation of inductive noise can be suppressed.

Furthermore, in a case where the conductor layer C is arranged near the wiring layer170, as illustrated in C inFIG.120, for example, the capacitive noise due to capacitive coupling between the linear conductor1251A and the linear conductor1251B of the conductor layer C, and the signal line132and the control line133of the wiring layer170can occur. However, since the linear conductor1251A and the linear conductor1251B have the same wiring pattern repeated in the X direction, the capacitive noise can be completely canceled in the X direction. The capacitive noise can be significantly improved as the conductor layer C is closer to the wiring layer170.

As illustrated in F inFIG.129, the stacked layer of the conductor layers A and B has a light-shielding structure, and the hot carrier light emission from the active element group167can be shielded. In addition, as illustrated in D inFIG.129, the stacked layer of the conductor layers A and C has also a light-shielding structure, and the light-shielding property is maintained. Thereby, since the light-shielding restrictions of the conductor layers A and B can be significantly alleviated, the conductive area of the conductor layers A and B can be used to the maximum, the wiring resistance can be lowered, and the voltage drop can be further improved. Furthermore, the degree of freedom in layout of the conductor layers A and B can be improved.

Moreover, in the case where the reticulated conductor1201of the conductor layer A and the linear conductor1251A of the conductor layer C are electrically connected, and the reticulated conductor1202of the conductor layer B and the linear conductor1251B of the conductor layer C are electrically connected, the current amount of the conductor layers A and B can be made small. Therefore, the inductive noise and the voltage drop from the conductor layer A or B can be further improved.

FIG.130illustrates a second modification of the fourth configuration example of the three-layer conductor layer.

A to F inFIG.130correspond to A to F inFIG.129, respectively, and description of common parts having the same reference numerals will be omitted as appropriate, and different parts will be described.

In the first modification inFIG.129, when viewing the positions of the gaps in the reticulated conductor1201of the conductor layer A and the reticulated conductor1202of the conductor layer B, the positions in the X direction are different and the positions in the Y direction match.

Meanwhile, in the second modification inFIG.130, when viewing the positions of the gaps in the reticulated conductor1201of the conductor layer A and the reticulated conductor1202of the conductor layer B, the positions in the X direction match and the positions in the Y direction are different.

In other words, when comparing the conductors in the same or substantially the same direction as a direction (Y direction) into which the signal line132of the wiring layer170extends between the reticulated conductor1201of the conductor layer A and the reticulated conductor1202of the conductor layer B, all the conductors overlap as viewed from the stacking direction. The conductor layer A and the conductor layer B having such a configuration correspond to the sixth configuration example of the conductor layers A and B illustrated inFIG.27, and can significantly improve the inductive noise, as illustrated in the simulation result in C inFIG.28.

In the first modification inFIG.129, when comparing the positions between the relay conductor1241of the conductor layer A and the relay conductor1242of the conductor layer B, the positions in the X direction are different and the positions in the Y direction match. Meanwhile, in the second modification inFIG.130, the positions in the X direction match and the positions in the Y direction are different.

In the first modification inFIG.129, the stacked layer of the conductor layers A and B and the stacked layer of the conductor layers A and C have a light-shielding structure, and the light-shielding property is maintained. Meanwhile, in the second modification inFIG.130, the stacked layer of the conductor layers A and C and the stacked layer of the conductor layers B and C have a light-shielding structure, and the light-shielding property is maintained.

The second modification inFIG.130is similar to the first modification inFIG.129except for the above-described points.

Even in the second modification inFIG.130, when the conductor layer C is viewed in a predetermined plane range (plane region), the current distribution of the linear conductor1251A and the current distribution of the linear conductor1251B become the same or substantially the same, so that generation of inductive noise can be suppressed.

Furthermore, since the capacitive noise can be completely canceled in the X direction, the capacitive noise can be significantly improved. Since the stacked layer of the conductor layers A and C and the stacked layer of the conductor layers B and C have the light-shielding structure, the light-shielding restrictions of the conductor layers A and B can be significantly alleviated. Furthermore, the wiring resistance can be lowered and the voltage drop can be improved. Moreover, the degree of freedom in layout of the conductor layers A and B can be improved.

Fifth Configuration Example of Three-Layer Conductor Layer

FIG.131illustrates a fifth configuration example of the three-layer conductor layer.

A inFIG.131illustrates the conductor layer C (wiring layer165C), B inFIG.131illustrates the conductor layer A (wiring layer165A), and C inFIG.131illustrates the conductor layer B (wiring layer165B).

Furthermore, D inFIG.131is a plan view of a stacked state of the conductor layer A and the conductor layer C, E inFIG.131is a plan view of a stacked state of the conductor layer B and the conductor layer C, and F inFIG.131is a plan view of a stacked state of the conductor layer A and the conductor layer B.

In the fifth configuration example inFIG.131, a portion corresponding to that in the fourth configuration example illustrated inFIG.128is given the same reference numeral and description of the portion is omitted as appropriate, and description will be given focusing on different portions.

The conductor layer A in B inFIG.131has a reticulated conductor1261. The difference of the reticulated conductor1261from the reticulated conductor1201of the fourth configuration example illustrated inFIG.128is the ratio of the gap width GXA in the X direction and the gap width GYA in the Y direction. Specifically, the reticulated conductor1201of the conductor layer A of the fourth configuration example illustrated inFIG.128has (the gap width GYA/the gap width GXA)>1, whereas the reticulated conductor1261of the conductor layer A of the fifth configuration example in B inFIG.131has (the gap width GYA/the gap width GXA)<1.

In other words, the reticulated conductor1201of the conductor layer A of the fourth configuration example illustrated inFIG.128has the conductor width WXA>the conductor width WYA and the gap width GYA>the gap width GXA, and is a conductor in which the current easily flows in the Y direction, whereas the reticulated conductor1261of the conductor layer A of the fifth configuration example in B inFIG.131has the conductor width WXA<the conductor width WYA and the gap width GYA<the gap width GXA, and is a conductor in which the current easily flows in the X direction.

Moreover, in other words, the direction in which the current easily flows in the conductor layer C of the fourth configuration example illustrated inFIG.128and the direction in which the current easily flows in the conductor layers A and B are substantially orthogonal and differ by approximately 90 degrees, whereas the direction in which the current easily flows in the conductor layer C of the fifth configuration example in B inFIG.131and the direction in which the current easily flows in the conductor layers A and B are the same or substantially the same. In the case of the fifth configuration example inFIG.131, the voltage drop can be further improved depending on the wiring layout.

In the fourth configuration example illustrated inFIG.128, when comparing the positions of the gaps between the reticulated conductor1201of the conductor layer A and the reticulated conductor1202of the conductor layer B, the positions in the X direction are different and the positions in the Y direction match.

Meanwhile, in the fifth configuration example in B inFIG.131, the positions of the gaps in the X direction match and the positions of the gaps in the Y direction are different in the reticulated conductor1261of the conductor layer A and the reticulated conductor1262of the conductor layer B

In other words, when comparing the conductors in the same or substantially the same direction as a direction (Y direction) into which the signal line132of the wiring layer170extends between the reticulated conductor1261of the conductor layer A and the reticulated conductor1262of the conductor layer B, all the conductors overlap as viewed from the stacking direction. The conductor layer A and the conductor layer B having such a configuration correspond to the sixth configuration example of the conductor layers A and B illustrated inFIG.27, and can significantly improve the inductive noise, as illustrated in the simulation result in C inFIG.28.

The second modification inFIG.130is similar to the fourth configuration example illustrated inFIG.128except for the above-described points.

The conductor layer C in A inFIG.131is the same as the conductor layer C of the fourth configuration example illustrated inFIG.128. Therefore, when the conductor layer C is viewed in a predetermined plane range (plane region), the current distribution of the linear conductor1221A and the current distribution of the linear conductor1221B become the same or substantially the same, so that generation of inductive noise can be suppressed.

Since the linear conductor1221A and the linear conductor1221B have the same wiring pattern repeated in the Y direction, the capacitive noise can be completely canceled in the Y direction. The capacitive noise can be significantly improved as the conductor layer C is closer to the wiring layer170.

As illustrated in F inFIG.131, the stacked layer of the conductor layers A and B has a light-shielding structure, and the hot carrier light emission from the active element group167can be shielded. In addition, as illustrated in D inFIG.131, the stacked layer of the conductor layers A and C has also a light-shielding structure, and the light-shielding property is maintained. Thereby, since the light-shielding restrictions of the conductor layers A and B can be significantly alleviated, the conductive area of the conductor layers A and B can be used to the maximum, the wiring resistance can be lowered, and the voltage drop can be further improved. Furthermore, the degree of freedom in layout of the conductor layers A and B can be improved.

Moreover, in the case where the reticulated conductor1261of the conductor layer A and the linear conductor1221A of the conductor layer C are electrically connected, and the reticulated conductor1262of the conductor layer B and the linear conductor1221B of the conductor layer C are electrically connected, the current amount of the conductor layers A and B can be made small. Therefore, the inductive noise and the voltage drop from the conductor layer A or B can be further improved.

Sixth Configuration Example of Three-Layer Conductor Layer

FIG.132illustrates a sixth configuration example of the three-layer conductor layer.

A inFIG.132illustrates the conductor layer C (wiring layer165C), B inFIG.132illustrates the conductor layer A (wiring layer165A), and C inFIG.132illustrates the conductor layer B (wiring layer165B).

Furthermore, D inFIG.132is a plan view of a stacked state of the conductor layer A and the conductor layer C, E inFIG.132is a plan view of a stacked state of the conductor layer B and the conductor layer C, and F inFIG.132is a plan view of a stacked state of the conductor layer A and the conductor layer B.

In the sixth configuration example inFIG.132, a portion corresponding to that in the fourth configuration example illustrated inFIG.128is given the same reference numeral and description of the portion is omitted as appropriate, and description will be given focusing on different portions.

The sixth configuration example inFIG.132is a configuration in which a part of the relay conductor1241of the conductor layer A is omitted in the fourth configuration example illustrated inFIG.128. Specifically, in the fourth configuration example inFIG.128, the relay conductor1241is formed in all the gaps in a matrix of the reticulated conductor1201, whereas in the sixth configuration example inFIG.132, a row in which the relay conductor1241is formed and a row in which the relay conductor1241is not formed are alternately arranged in the Y direction in units of rows. The relay conductor1241of the conductor layer A is located in the XY plane region of the linear conductor1221B of the conductor layer C.

In this way, the relay conductor1241formed in each gap of the reticulated conductor1201may be thinned out and arranged in a part of the gaps instead of being arranged in all the gaps. The restrictions such as occupancy of the wiring region in the conductor layer A can be secured, and the degree of freedom in designing the wiring layout can be increased.

The sixth configuration example inFIG.132is similar to the fourth configuration example illustrated inFIG.128except for the above-described points.

The conductor layer C in A inFIG.132is the same as the conductor layer C of the fourth configuration example illustrated inFIG.128. Therefore, when the conductor layer C is viewed in a predetermined plane range (plane region), the current distribution of the linear conductor1221A and the current distribution of the linear conductor1221B become the same or substantially the same, so that generation of inductive noise can be suppressed.

Since the linear conductor1221A and the linear conductor1221B have the same wiring pattern repeated in the Y direction, the capacitive noise can be completely canceled in the Y direction. The capacitive noise can be significantly improved as the conductor layer C is closer to the wiring layer170.

As illustrated in F inFIG.132, the stacked layer of the conductor layers A and B has a light-shielding structure, and the hot carrier light emission from the active element group167can be shielded. In addition, as illustrated in D and E inFIG.132, the stacked layer of the conductor layers A and C and the stacked layer of the conductor layers B and C have also a light-shielding structure, and the light-shielding property is maintained. Thereby, since the light-shielding restrictions of the conductor layers A and B can be significantly alleviated, the conductive area of the conductor layers A and B can be used to the maximum, the wiring resistance can be lowered, and the voltage drop can be further improved. Furthermore, the degree of freedom in layout of the conductor layers A and B can be improved.

By providing the relay conductor1241in the conductor layer A, it becomes possible to connect the reticulated conductor1202and the linear conductor1221B in the substantially shortest distance or a short distance to draw the power supply, thereby reducing the voltage drop, energy loss, or inductive noise.

By providing the relay conductor1242in the conductor layer B, it becomes possible to connect the reticulated conductor1201and the linear conductor1221A in the substantially shortest distance or a short distance, thereby reducing the voltage drop, energy loss, or inductive noise.

In the sixth configuration example inFIG.132, the direction in which the current of the conductor layer C is likely to flow and the direction in which the current of the conductor layers A and B is likely to flow are substantially orthogonal and differ by approximately 90 degrees. As a result, the current becomes easily diffused (the current is less likely to be concentrated), so that the inductive noise can be further improved.

Modification of Sixth Configuration Example of Three-Layer Conductor Layer

FIG.133illustrates a modification of the sixth configuration example of the three-layer conductor layer.

A inFIG.133illustrates the conductor layer C (wiring layer165C), B inFIG.133illustrates the conductor layer A (wiring layer165A), and C inFIG.133illustrates the conductor layer B (wiring layer165B).

Furthermore, D inFIG.133is a plan view of a stacked state of the conductor layer A and the conductor layer C, E inFIG.133is a plan view of a stacked state of the conductor layer B and the conductor layer C, and F inFIG.133is a plan view of a stacked state of the conductor layer A and the conductor layer B.

InFIG.133, a portion corresponding to that in the sixth configuration example illustrated inFIG.132is given the same reference numeral and description of the portion is omitted as appropriate, and description will be given focusing on different portions.

In the modification of the sixth configuration example, the configurations of the conductor layer A and the conductor layer C are different from those of the sixth configuration example inFIG.132.

In the conductor layer C in A inFIG.132, the linear conductor1221A long in the X direction and the linear conductor1221B long in the X direction have been alternately and periodically arranged in the Y direction. Thereby, the direction in which the current of the conductor layer C is likely to flow and the direction in which the current of the conductor layers A and B is likely to flow are substantially orthogonal and differ by approximately 90 degrees.

In contrast, in the conductor layer C in A inFIG.133, a linear conductor1251A long in the Y direction and a linear conductor1251B long in the Y direction are alternately and periodically arranged in the X direction. Thereby, the direction in which the current of the conductor layer C is likely to flow and the direction in which the current of the conductor layers A and B is likely to flow are the same or substantially the same. In this case, the voltage drop can be further improved depending on the wiring layout.

Next, in the conductor layer A in B inFIG.132, a row in which the relay conductor1241is formed and a row in which the relay conductor1241is not formed are alternately arranged in the Y direction in units of rows in the gaps in a matrix of the reticulated conductor1201.

In contrast, in the conductor layer A in B inFIG.133, a column in which the relay conductor1241is formed and a column in which the relay conductor1241is not formed are alternately arranged in the X direction in units of columns in the gaps in a matrix of the reticulated conductor1201. The relay conductor1241of the conductor layer A is located in the XY plane region of the linear conductor1251B of the conductor layer C.

The modification of the sixth configuration example inFIG.133is similar to the sixth configuration example illustrated inFIG.132except for the above-described points.

The conductor layer C in A inFIG.133is the same as the conductor layer C of the first modification of the fourth configuration example illustrated inFIG.129. Therefore, the current distribution of the linear conductor1251A and the current distribution of the linear conductor1251B become the same or substantially the same, so that generation of inductive noise can be suppressed.

Since the linear conductor1251A and the linear conductor1251B repeat the same wiring pattern in the X direction, the capacitive noise can be completely canceled in the X direction. The capacitive noise can be significantly improved as the conductor layer C is closer to the wiring layer170.

As illustrated in F inFIG.133, the stacked layer of the conductor layers A and B has a light-shielding structure, and the hot carrier light emission from the active element group167can be shielded. In addition, as illustrated in D inFIG.133, the stacked layer of the conductor layers A and C has also a light-shielding structure, and the light-shielding property is maintained. Thereby, since the light-shielding restrictions of the conductor layers A and B can be significantly alleviated, the conductive area of the conductor layers A and B can be used to the maximum, the wiring resistance can be lowered, and the voltage drop can be further improved. Furthermore, the degree of freedom in layout of the conductor layers A and B can be improved.

Moreover, in the case where the reticulated conductor1201of the conductor layer A and the linear conductor1251A of the conductor layer C are electrically connected, and the reticulated conductor1202of the conductor layer B and the linear conductor1251B of the conductor layer C are electrically connected, the current amount of the conductor layers A and B can be made small. Therefore, the inductive noise and the voltage drop from the conductor layer A or B can be further improved.

Note that, in the modification of the sixth configuration example inFIG.133, the relay conductors1241of the conductor layer A are thinned out, and the relay conductors1242of the conductor layer B are not thinned out. However, a configuration in which the relay conductors1242of the conductor layer B are thinned out and the relay conductors1241of the conductor layer A are not thinned out can also be adopted.

Seventh Configuration Example of Three-Layer Conductor Layer

FIG.134illustrates a seventh configuration example of the three-layer conductor layer.

A inFIG.134illustrates the conductor layer C (wiring layer165C), B inFIG.134illustrates the conductor layer A (wiring layer165A), and C inFIG.134illustrates the conductor layer B (wiring layer165B).

Furthermore, D inFIG.134is a plan view of a stacked state of the conductor layer A and the conductor layer C, E inFIG.134is a plan view of a stacked state of the conductor layer B and the conductor layer C, and F inFIG.134is a plan view of a stacked state of the conductor layer A and the conductor layer B.

In the seventh configuration example inFIG.134, a portion corresponding to that in the fifth configuration example illustrated inFIG.131is given the same reference numeral and description of the portion is omitted as appropriate, and description will be given focusing on different portions.

In the seventh configuration example, only the configuration of the conductor layer A in B inFIG.134is different from that of the fifth configuration example inFIG.131. The conductor layers B and C of the seventh configuration example are similar to the conductor layers B and C of the fifth configuration example inFIG.131.

The conductor layer A in B inFIG.134in the seventh configuration example has a reticulated conductor1271. Furthermore, in the conductor layer A, the relay conductor1241is not formed inside the gap having the gap width GXA in the X direction and the gap width GYA in the Y direction of the reticulated conductor1271.

In other words, the gap width GXA and the gap width GYA of the reticulated conductor1271in B inFIG.134are smaller than the gap width GXA and the gap width GYA of the reticulated conductor1261in B inFIG.131, and the gap is not sufficient to form the relay conductor1241.

The seventh configuration example inFIG.134is similar to the fifth configuration example illustrated inFIG.131except for the above-described points.

The conductor layer C in A inFIG.134is the same as the conductor layer C of the fifth configuration example illustrated inFIG.131. Therefore, when the conductor layer C is viewed in a predetermined plane range (plane region), the current distribution of the linear conductor1221A and the current distribution of the linear conductor1221B become the same or substantially the same, so that generation of inductive noise can be suppressed.

Since the linear conductor1221A and the linear conductor1221B have the same wiring pattern repeated in the Y direction, the capacitive noise can be completely canceled in the Y direction. The capacitive noise can be significantly improved as the conductor layer C is closer to the wiring layer170.

As illustrated in F inFIG.134, the stacked layer of the conductor layers A and B has a light-shielding structure, and the hot carrier light emission from the active element group167can be shielded. In addition, as illustrated in D inFIG.134, the stacked layer of the conductor layers A and C has also a light-shielding structure, and the light-shielding property is maintained. Thereby, since the light-shielding restrictions of the conductor layers A and B can be significantly alleviated, the conductive area of the conductor layers A and B can be used to the maximum, the wiring resistance can be lowered, and the voltage drop can be further improved. Furthermore, the degree of freedom in layout of the conductor layers A and B can be improved.

The seventh configuration example inFIG.134is particularly suitable for the stacking order in which the three conductor layers A to C can be electrically connected, specifically for the stacking order illustrated in B inFIG.120. In the case of the stacking order of the conductor layers A, B, and C illustrated in B inFIG.120, the reticulated conductor1271of the conductor layer A and the linear conductor1221A of the conductor layer C can be connected via the conductor via in the Z direction in a part of a region where plane regions overlap, and the reticulated conductor1262and the relay conductor1242of the conductor layer B can be respectively connected with the linear conductors1221B and1221A of the conductor layer C via the conductor via in the Z direction between the conductors having common current characteristics and in a part of a region where plane regions overlap.

Eighth Configuration Example of Three-Layer Conductor Layer

FIG.135illustrates an eighth configuration example of the three-layer conductor layer.

A inFIG.135illustrates the conductor layer C (wiring layer165C), B inFIG.135illustrates the conductor layer A (wiring layer165A), and C inFIG.135illustrates the conductor layer B (wiring layer165B).

Furthermore, D inFIG.135is a plan view of a stacked state of the conductor layer A and the conductor layer C, E inFIG.135is a plan view of a stacked state of the conductor layer B and the conductor layer C, and F inFIG.135is a plan view of a stacked state of the conductor layer A and the conductor layer B.

The eighth configuration example inFIG.135has a configuration in which a part of the fourth configuration example illustrated inFIG.128is changed. The eighth configuration example inFIG.135will be described while being compared with the fourth configuration example. Note that, inFIG.135, the same reference numerals are given to the portions corresponding to those inFIG.128.

The conductor layer C in A inFIG.135is similar to the conductor layer C of the fourth configuration example illustrated in A inFIG.128. That is, the conductor layer C is configured such that a linear conductor1221A long in the X direction and a linear conductor1221B long in the X direction are alternately and periodically arranged in the Y direction.

The conductor layer A in B inFIG.128has a configuration in which a part of the relay conductor1241of the conductor layer A is omitted in the fourth configuration example illustrated inFIG.128. Specifically, in the fourth configuration example inFIG.128, the relay conductor1241is formed in all the gaps in a matrix of the reticulated conductor1201, whereas in the eighth configuration example inFIG.135, a row in which the relay conductor1241is formed and a row in which the relay conductor1241is not formed are alternately arranged in the Y direction in units of rows.

Similarly, the conductor layer B in C inFIG.128has a configuration in which a part of the relay conductor1242of the conductor layer B is omitted in the fourth configuration example illustrated inFIG.128. Specifically, in the fourth configuration example inFIG.128, the relay conductor1242is formed in all the gaps in a matrix of the reticulated conductor1201, whereas in the eighth configuration example inFIG.135, a row in which the relay conductor1242is formed and a row in which the relay conductor1242is not formed are alternately arranged in the Y direction in units of rows.

Therefore, the eighth configuration example inFIG.135has a configuration in which the relay conductors1241arranged in the gaps in the matrix of the reticulated conductor1201are thinned out every other row in units of rows in the conductor layer A, and the relay conductor1242arranged in the gaps in the matrix of the reticulated conductor1202are thinned out every other row in units of rows in the conductor layer B, from the fourth configuration example inFIG.128.

The eighth configuration example inFIG.135is similar to the fourth configuration example illustrated inFIG.128except for the above-described points.

When the conductor layer C in A inFIG.135is viewed in a predetermined plane range (plane region), the current distribution of the linear conductor1221A and the current distribution of the linear conductor1221B become the same or substantially the same, so that generation of inductive noise can be suppressed.

Since the linear conductor1221A and the linear conductor1221B have the same wiring pattern repeated in the Y direction, the capacitive noise can be completely canceled in the Y direction. The capacitive noise can be significantly improved as the conductor layer C is closer to the wiring layer170.

As illustrated in F inFIG.135, the stacked layer of the conductor layers A and B has a light-shielding structure, and the hot carrier light emission from the active element group167can be shielded. In addition, as illustrated in D and E inFIG.135, the stacked layer of the conductor layers A and C and the stacked layer of the conductor layers B and C have also a light-shielding structure, and the light-shielding property is maintained. Thereby, since the light-shielding restrictions of the conductor layers A and B can be significantly alleviated, the conductive area of the conductor layers A and B can be used to the maximum, the wiring resistance can be lowered, and the voltage drop can be further improved. Furthermore, the degree of freedom in layout of the conductor layers A and B can be improved.

By providing the relay conductor1241in the conductor layer A, it becomes possible to connect the reticulated conductor1202and the linear conductor1221B in the substantially shortest distance or a short distance to draw the power supply, thereby reducing the voltage drop, energy loss, or inductive noise.

By providing the relay conductor1242in the conductor layer B, it becomes possible to connect the reticulated conductor1201and the linear conductor1221A in the substantially shortest distance or a short distance, thereby reducing the voltage drop, energy loss, or inductive noise.

In the eighth configuration example inFIG.135, the direction in which the current of the conductor layer C is likely to flow and the direction in which the current of the conductor layers A and B is likely to flow are substantially orthogonal and differ by approximately 90 degrees. As a result, the current becomes easily diffused (the current is less likely to be concentrated), so that the inductive noise can be further improved.

First Modification of Eighth Configuration Example of Three-Layer Conductor Layer

FIG.136illustrates a first modification of the eighth configuration example of the three-layer conductor layer.

A inFIG.136illustrates the conductor layer C (wiring layer165C), B inFIG.136illustrates the conductor layer A (wiring layer165A), and C inFIG.136illustrates the conductor layer B (wiring layer165B).

Furthermore, D inFIG.136is a plan view of a stacked state of the conductor layer A and the conductor layer C, E inFIG.136is a plan view of a stacked state of the conductor layer B and the conductor layer C, and F inFIG.136is a plan view of a stacked state of the conductor layer A and the conductor layer B.

InFIG.136, a portion corresponding to that in the eighth configuration example illustrated inFIG.135is given the same reference numeral and description of the portion is omitted as appropriate, and description will be given focusing on different portions.

In the first modification of the eighth configuration example, the configurations of the conductor layers A to C are different from those of the eighth configuration example inFIG.135.

In the conductor layer C in A inFIG.135, the linear conductor1221A long in the X direction and the linear conductor1221B long in the X direction have been alternately and periodically arranged in the Y direction. Thereby, the direction in which the current of the conductor layer C is likely to flow and the direction in which the current of the conductor layers A and B is likely to flow are substantially orthogonal and differ by approximately 90 degrees.

In contrast, in the conductor layer C in A inFIG.136, a linear conductor1251A long in the Y direction and a linear conductor1251B long in the Y direction are alternately and periodically arranged in the X direction. Thereby, the direction in which the current of the conductor layer C is likely to flow and the direction in which the current of the conductor layers A and B is likely to flow are the same or substantially the same. In this case, the voltage drop can be further improved depending on the wiring layout.

Next, in the conductor layer A in B inFIG.135, a row in which the relay conductor1241is formed and a row in which the relay conductor1241is not formed are alternately arranged in the Y direction in units of rows in the gaps in a matrix of the reticulated conductor1201.

In contrast, in the conductor layer A in B inFIG.136, a column in which the relay conductor1241is formed and a column in which the relay conductor1241is not formed are alternately arranged in the X direction in units of columns in the gaps in a matrix of the reticulated conductor1201. The relay conductor1241of the conductor layer A is located in the XY plane region of the linear conductor1251B of the conductor layer C.

Furthermore, in the conductor layer B in C inFIG.135, a row in which the relay conductor1242is formed and a row in which the relay conductor1242is not formed are alternately arranged in the Y direction in units of rows in the gaps in a matrix of the reticulated conductor1202.

In contrast, in the conductor layer B in C inFIG.136, a column in which the relay conductor1242is formed and a column in which the relay conductor1242is not formed are alternately arranged in the X direction in units of columns in the gaps in a matrix of the reticulated conductor1202.

The first modification of the eighth configuration example inFIG.136is similar to the eighth configuration example illustrated inFIG.135except for the above-described points.

When the conductor layer C in A inFIG.136is viewed in a predetermined plane range (plane region), the current distribution of the linear conductor1251A and the current distribution of the linear conductor1251B become the same or substantially the same, so that generation of inductive noise can be suppressed.

Since the linear conductor1251A and the linear conductor1251B repeat the same wiring pattern in the X direction, the capacitive noise can be completely canceled in the X direction. The capacitive noise can be significantly improved as the conductor layer C is closer to the wiring layer170.

As illustrated in F inFIG.136, the stacked layer of the conductor layers A and B has a light-shielding structure, and the hot carrier light emission from the active element group167can be shielded. In addition, as illustrated in D inFIG.136, the stacked layer of the conductor layers A and C has also a light-shielding structure, and the light-shielding property is maintained. Thereby, since the light-shielding restrictions of the conductor layers A and B can be significantly alleviated, the conductive area of the conductor layers A and B can be used to the maximum, the wiring resistance can be lowered, and the voltage drop can be further improved. Furthermore, the degree of freedom in layout of the conductor layers A and B can be improved.

Moreover, in the case where the reticulated conductor1201of the conductor layer A and the linear conductor1251A of the conductor layer C are electrically connected, and the reticulated conductor1202of the conductor layer B and the linear conductor1251B of the conductor layer C are electrically connected, the current amount of the conductor layers A and B can be made small. Therefore, the inductive noise and the voltage drop from the conductor layer A or B can be further improved.

By providing the relay conductor1241in the conductor layer A, it becomes possible to connect the reticulated conductor1202and the linear conductor1251B in the substantially shortest distance or a short distance to draw the power supply, thereby reducing the voltage drop, energy loss, or inductive noise.

By providing the relay conductor1242in the conductor layer B, it becomes possible to connect the reticulated conductor1201and the linear conductor1251A in the substantially shortest distance or a short distance, thereby reducing the voltage drop, energy loss, or inductive noise.

Second Modification of Eighth Configuration Example of Three-Layer Conductor Layer

FIG.137illustrates a second modification of the eighth configuration example of the three-layer conductor layer.

A inFIG.137illustrates the conductor layer C (wiring layer165C), B inFIG.137illustrates the conductor layer A (wiring layer165A), and C inFIG.137illustrates the conductor layer B (wiring layer165B).

Furthermore, D inFIG.137is a plan view of a stacked state of the conductor layer A and the conductor layer C, E inFIG.137is a plan view of a stacked state of the conductor layer B and the conductor layer C, and F inFIG.137is a plan view of a stacked state of the conductor layer A and the conductor layer B.

InFIG.137, a portion corresponding to that in the eighth configuration example illustrated inFIG.135is given the same reference numeral and description of the portion is omitted as appropriate, and description will be given focusing on different portions.

In the second modification of the eighth configuration example, the configurations of the conductor layer A and the conductor layer B are different from those of the eighth configuration example inFIG.135.

When comparing the conductor layer A in B inFIG.137with the eighth configuration example illustrated inFIG.135, a reinforced conductor1281having a conductor width WYAd1 in the Y direction is newly added in the gap where the relay conductor1241of the reticulated conductor1201is not formed. The reinforced conductor1281is a linear conductor having the conductor width of the gap width GXA in the X direction and long in the X direction.

When comparing the conductor layer B in C inFIG.137with the eighth configuration example illustrated inFIG.135, a reinforced conductor1282having a conductor width WYBd1 in the Y direction is newly added in the gap where the relay conductor1242of the reticulated conductor1202is not formed. The reinforced conductor1282is a linear conductor having the conductor width of the gap width GXB in the X direction and long in the X direction.

The second modification of the eighth configuration example inFIG.137is similar to the eighth configuration example illustrated inFIG.135except for the above-described points.

When the conductor layer C in A inFIG.137is viewed in a predetermined plane range (plane region), the current distribution of the linear conductor1221A and the current distribution of the linear conductor1221B become the same or substantially the same, so that generation of inductive noise can be suppressed.

Since the linear conductor1221A and the linear conductor1221B have the same wiring pattern repeated in the Y direction, the capacitive noise can be completely canceled in the Y direction. The capacitive noise can be significantly improved as the conductor layer C is closer to the wiring layer170.

As illustrated in F inFIG.137, the stacked layer of the conductor layers A and B has a light-shielding structure, and the hot carrier light emission from the active element group167can be shielded. In addition, as illustrated in D and E inFIG.137, the stacked layer of the conductor layers A and C and the stacked layer of the conductor layers B and C have also a light-shielding structure, and the light-shielding property is maintained. Thereby, since the light-shielding restrictions of the conductor layers A and B can be significantly alleviated, the conductive area of the conductor layers A and B can be used to the maximum, the wiring resistance can be lowered, and the voltage drop can be further improved. Furthermore, the degree of freedom in layout of the conductor layers A and B can be improved.

By providing the relay conductor1241in the conductor layer A, it becomes possible to connect the reticulated conductor1202and the linear conductor1221B in the substantially shortest distance or a short distance to draw the power supply, thereby reducing the voltage drop, energy loss, or inductive noise.

By providing the relay conductor1242in the conductor layer B, it becomes possible to connect the reticulated conductor1201and the linear conductor1221A in the substantially shortest distance or a short distance, thereby reducing the voltage drop, energy loss, or inductive noise.

In the second modification of the eighth configuration example inFIG.137, the direction in which the current of the conductor layer C is likely to flow and the direction in which the current of the conductor layers A and B is likely to flow are substantially orthogonal and differ by approximately 90 degrees. As a result, the current becomes easily diffused (the current is less likely to be concentrated), so that the inductive noise can be further improved.

In the conductor layer A, the reinforced conductor1281long in the X direction is arranged at the position where the relay conductor1241has been thinned out, so that the wiring resistance can be made small, and the voltage drop can be further improved. The inductive noise can also be improved as the voltage drop is improved.

In the conductor layer B, the reinforced conductor1282long in the X direction is arranged at the position where the relay conductor1242has been thinned out, so that the wiring resistance can be made small, and the voltage drop can be further improved. The inductive noise can also be improved as the voltage drop is improved.

Third Modification of Eighth Configuration Example of Three-Layer Conductor Layer

FIG.138illustrates a third modification of the eighth configuration example of the three-layer conductor layer.

A inFIG.138illustrates the conductor layer C (wiring layer165C), B inFIG.138illustrates the conductor layer A (wiring layer165A), and C inFIG.138illustrates the conductor layer B (wiring layer165B).

Furthermore, D inFIG.138is a plan view of a stacked state of the conductor layer A and the conductor layer C, E inFIG.138is a plan view of a stacked state of the conductor layer B and the conductor layer C, and F inFIG.138is a plan view of a stacked state of the conductor layer A and the conductor layer B.

InFIG.138, a portion corresponding to that in the eighth configuration example illustrated inFIG.135is given the same reference numeral and description of the portion is omitted as appropriate, and description will be given focusing on different portions.

In the third modification of the eighth configuration example, the configurations of the conductor layer A and the conductor layer B are different from the eighth configuration example inFIG.135.

First, looking at the conductor layer A, in the eighth configuration example illustrated inFIG.135, the gaps in the matrix of the reticulated conductor1201commonly have the gap width GYA in the Y direction. In other words, the gap width GYA in the Y direction is the same for all the gaps in the matrix of the reticulated conductor1201.

In contrast, in the conductor layer A in B inFIG.138, the gap in which the relay conductor1241is formed has the gap width GYA in the Y direction, and the gap in which the relay conductor1241is not formed has a gap width GYAd1 in the Y direction, which is smaller than the gap width GYA (gap width GYA>gap width GYAd1).

Next, looking at the conductor layer B, in the eighth configuration example illustrated inFIG.135, the gaps in the matrix of the reticulated conductor1202commonly have the gap width GYB in the Y direction. In other words, the gap width GYB in the Y direction is the same for all the gaps in the matrix of the reticulated conductor1202.

In contrast, in the conductor layer A in B inFIG.138, the gap in which the relay conductor1242is formed has the gap width GYB in the Y direction, and the gap in which the relay conductor1242is not formed has a gap width GYBd1 in the Y direction, which is smaller than the gap width GYB (gap width GYB>gap width GYBd1).

The third modification of the eighth configuration example inFIG.138is similar to the eighth configuration example illustrated inFIG.135except for the above-described points.

When the conductor layer C in A inFIG.138is viewed in a predetermined plane range (plane region), the current distribution of the linear conductor1221A and the current distribution of the linear conductor1221B become the same or substantially the same, so that generation of inductive noise can be suppressed.

Since the linear conductor1221A and the linear conductor1221B have the same wiring pattern repeated in the Y direction, the capacitive noise can be completely canceled in the Y direction. The capacitive noise can be significantly improved as the conductor layer C is closer to the wiring layer170.

As illustrated in F inFIG.138, the stacked layer of the conductor layers A and B has a light-shielding structure, and the hot carrier light emission from the active element group167can be shielded. In addition, as illustrated in D and E inFIG.138, the stacked layer of the conductor layers A and C and the stacked layer of the conductor layers B and C have also a light-shielding structure, and the light-shielding property is maintained. Thereby, since the light-shielding restrictions of the conductor layers A and B can be significantly alleviated, the conductive area of the conductor layers A and B can be used to the maximum, the wiring resistance can be lowered, and the voltage drop can be further improved. Furthermore, the degree of freedom in layout of the conductor layers A and B can be improved.

By providing the relay conductor1241in the conductor layer A, it becomes possible to connect the reticulated conductor1202and the linear conductor1221B in the substantially shortest distance or a short distance to draw the power supply, thereby reducing the voltage drop, energy loss, or inductive noise.

By providing the relay conductor1242in the conductor layer B, it becomes possible to connect the reticulated conductor1201and the linear conductor1221A in the substantially shortest distance or a short distance, thereby reducing the voltage drop, energy loss, or inductive noise.

In the third modification of the eighth configuration example inFIG.138, the direction in which the current of the conductor layer C is likely to flow and the direction in which the current of the conductor layers A and B is likely to flow are substantially orthogonal and differ by approximately 90 degrees. As a result, the current becomes easily diffused (the current is less likely to be concentrated), so that the inductive noise can be further improved.

In the conductor layer A, the gap width GYAd1 at the position where the relay conductor1241has been thinned out is made smaller than the gap width GYA at the position where the relay conductor1241is formed, so that the wiring resistance can be made small, and the voltage drop can be further improved. The inductive noise can also be improved as the voltage drop is improved.

In the conductor layer B, the gap width GYBd1 at the position where the relay conductor1242has been thinned out is made smaller than the gap width GYB at the position where the relay conductor1242is formed, so that the wiring resistance can be made small, and the voltage drop can be further improved. The inductive noise can also be improved as the voltage drop is improved.

Note that, in the third modification of the eighth configuration example inFIG.138, the gap width GYAd1 at the position where the relay conductor1241has been thinned out may be made smaller than the gap width GYA at the position where the relay conductor1241is formed by making the conductor width WYA in the Y direction of the reticulated conductor1201of the conductor layer A thicker, or the conductor width WYA in the Y direction may be the same as that of the eighth configuration example inFIG.135. The same applies to the reticulated conductor1202of the conductor layer B.

Fourth Modification of Eighth Configuration Example of Three-Layer Conductor Layer

FIG.139illustrates a fourth modification of the eighth configuration example of the three-layer conductor layer.

A inFIG.139illustrates the conductor layer C (wiring layer165C), B inFIG.139illustrates the conductor layer A (wiring layer165A), and C inFIG.139illustrates the conductor layer B (wiring layer165B).

Furthermore, D inFIG.139is a plan view of a stacked state of the conductor layer A and the conductor layer C, E inFIG.139is a plan view of a stacked state of the conductor layer B and the conductor layer C, and F inFIG.139is a plan view of a stacked state of the conductor layer A and the conductor layer B.

The fourth modification of the eighth configuration example inFIG.139has a configuration in which a part of the first modification of the eighth configuration example inFIG.136is changed. InFIG.139, parts corresponding to those inFIG.136are given the same reference numerals and description of the parts will be omitted as appropriate, and different parts will be described.

In the first modification inFIG.136, when comparing the positions of the gaps between the reticulated conductor1201of the conductor layer A and the reticulated conductor1202of the conductor layer B, the positions in the X direction are different and the positions in the Y direction match.

Meanwhile, in the fourth modification inFIG.139, when comparing the positions of the gaps between the reticulated conductor1201of the conductor layer A and the reticulated conductor1202of the conductor layer B, the positions in the X direction match and the positions in the Y direction are different.

The fourth modification of the eighth configuration example inFIG.139is similar to the first modification inFIG.136except for the above-described points. For example, the point that the column in which the relay conductor1241is formed and the column in which the relay conductor1241is not formed in the gaps in the matrix of the reticulated conductor1201are alternately arranged in the X direction in units of columns in the conductor layer A, and the point that the column in which the relay conductor1242is formed and the column in which the relay conductor1242is not formed in the gaps in the matrix of the reticulated conductor1202are alternately arranged in the X direction in units of columns in the conductor layer B are also similar.

Furthermore, the fourth modification of the eighth configuration example inFIG.139corresponds to a configuration in which the relay conductors1241are thinned out every other column in units of columns in the conductor layer A, and the relay conductors1242are thinned out every other column in units of columns in the conductor layer B from the second modification of the fourth configuration example illustrated inFIG.130.

When the conductor layer C in A inFIG.139is viewed in a predetermined plane range (plane region), the current distribution of the linear conductor1251A and the current distribution of the linear conductor1251B become the same or substantially the same, so that generation of inductive noise can be suppressed.

Since the linear conductor1251A and the linear conductor1251B repeat the same wiring pattern in the X direction, the capacitive noise can be completely canceled in the X direction. The capacitive noise can be significantly improved as the conductor layer C is closer to the wiring layer170.

As illustrated in D and E inFIG.139, the stacked layer of the conductor layers A and C and the stacked layer of the conductor layers B and C have a light-shielding structure, and the light-shielding property is maintained. Thereby, since the light-shielding restrictions of the conductor layers A and B can be significantly alleviated, the conductive area of the conductor layers A and B can be used to the maximum, the wiring resistance can be lowered, and the voltage drop can be further improved. Furthermore, the degree of freedom in layout of the conductor layers A and B can be improved.

Moreover, in the case where the reticulated conductor1201of the conductor layer A and the linear conductor1251A of the conductor layer C are electrically connected, and the reticulated conductor1202of the conductor layer B and the linear conductor1251B of the conductor layer C are electrically connected, the current amount of the conductor layers A and B can be made small. Therefore, the inductive noise and the voltage drop from the conductor layer A or B can be further improved.

In the conductor layer C in A inFIG.139, the direction in which the current of the conductor layer C is likely to flow and the direction in which the current of the conductor layers A and B is likely to flow are the same or substantially the same. In this case, the voltage drop can be further improved depending on the wiring layout.

By providing the relay conductor1241in the conductor layer A, it becomes possible to connect the reticulated conductor1202and the linear conductor1251B in the substantially shortest distance or a short distance to draw the power supply, thereby reducing the voltage drop, energy loss, or inductive noise.

By providing the relay conductor1242in the conductor layer B, it becomes possible to connect the reticulated conductor1201and the linear conductor1251A in the substantially shortest distance or a short distance, thereby reducing the voltage drop, energy loss, or inductive noise.

Fifth Modification of Eighth Configuration Example of Three-Layer Conductor Layer

FIG.140illustrates a fifth modification of the eighth configuration example of the three-layer conductor layer.

A inFIG.140illustrates the conductor layer C (wiring layer165C), B inFIG.140illustrates the conductor layer A (wiring layer165A), and C inFIG.140illustrates the conductor layer B (wiring layer165B).

Furthermore, D inFIG.140is a plan view of a stacked state of the conductor layer A and the conductor layer C, E inFIG.140is a plan view of a stacked state of the conductor layer B and the conductor layer C, and F inFIG.140is a plan view of a stacked state of the conductor layer A and the conductor layer B.

The fifth modification of the eighth configuration example inFIG.140has a configuration in which a part of the first modification of the eighth configuration example illustrated inFIG.136is changed. InFIG.140, parts corresponding to those inFIG.136are given the same reference numerals and description of the parts will be omitted as appropriate, and different parts will be described.

In the fifth modification of the eighth configuration example, only the configuration of the conductor layer B is different from that of the first modification of the eighth configuration example inFIG.136.

In the first modification inFIG.136, a column in which the relay conductor1242is formed and a column in which the relay conductor1242is not formed are alternately arranged in the X direction in units of columns in the gaps in a matrix of the reticulated conductor1202in the conductor layer B. In other words, the relay conductors1241are thinned out every other column in units of columns.

In contrast, in the conductor layer B inFIG.140, a column in which the relay conductor1242is formed and a column in which the relay conductor1242is not formed are alternately arranged in the X direction in units of two columns in the gaps in a matrix of the reticulated conductor1202. In other words, the relay conductors1241are thinned out every two other columns in units of two columns.

The fifth modification of the eighth configuration example inFIG.140is similar to the first modification of the eighth configuration example inFIG.136except for the above-described points.

When the conductor layer C in A inFIG.140is viewed in a predetermined plane range (plane region), the current distribution of the linear conductor1251A and the current distribution of the linear conductor1251B become the same or substantially the same, so that generation of inductive noise can be suppressed.

Since the linear conductor1251A and the linear conductor1251B repeat the same wiring pattern in the X direction, the capacitive noise can be completely canceled in the X direction. The capacitive noise can be significantly improved as the conductor layer C is closer to the wiring layer170.

As illustrated in F inFIG.140, the stacked layer of the conductor layers A and B has a light-shielding structure, and the hot carrier light emission from the active element group167can be shielded. In addition, as illustrated in D inFIG.140, the stacked layer of the conductor layers A and C has also a light-shielding structure, and the light-shielding property is maintained. Thereby, since the light-shielding restrictions of the conductor layers A and B can be significantly alleviated, the conductive area of the conductor layers A and B can be used to the maximum, the wiring resistance can be lowered, and the voltage drop can be further improved. Furthermore, the degree of freedom in layout of the conductor layers A and B can be improved.

Moreover, in the case where the reticulated conductor1201of the conductor layer A and the linear conductor1251A of the conductor layer C are electrically connected, and the reticulated conductor1202of the conductor layer B and the linear conductor1251B of the conductor layer C are electrically connected, the current amount of the conductor layers A and B can be made small. Therefore, the inductive noise and the voltage drop from the conductor layer A or B can be further improved.

In the conductor layer C in A inFIG.140, the direction in which the current of the conductor layer C is likely to flow and the direction in which the current of the conductor layers A and B is likely to flow are the same or substantially the same. In this case, the voltage drop can be further improved depending on the wiring layout.

By providing the relay conductor1241in the conductor layer A, it becomes possible to connect the reticulated conductor1202and the linear conductor1251B in the substantially shortest distance or a short distance to draw the power supply, thereby reducing the voltage drop, energy loss, or inductive noise.

By providing the relay conductor1242in the conductor layer B, it becomes possible to connect the reticulated conductor1201and the linear conductor1251A in the substantially shortest distance or a short distance, thereby reducing the voltage drop, energy loss, or inductive noise.

Ninth Configuration Example of Three-Layer Conductor Layer

FIG.141illustrates a ninth configuration example of the three-layer conductor layer.

A inFIG.141illustrates the conductor layer C (wiring layer165C), B inFIG.141illustrates the conductor layer A (wiring layer165A), and C inFIG.141illustrates the conductor layer B (wiring layer165B).

Furthermore, D inFIG.141is a plan view of a stacked state of the conductor layer A and the conductor layer C, E inFIG.141is a plan view of a stacked state of the conductor layer B and the conductor layer C, and F inFIG.141is a plan view of a stacked state of the conductor layer A and the conductor layer B.

The ninth configuration example inFIG.141has a configuration in which a part of the sixth configuration example inFIG.132is changed. InFIG.141, parts corresponding to those inFIG.132are given the same reference numerals and description of the parts will be omitted as appropriate, and different parts will be described.

In the ninth configuration example, only the configuration of the conductor layer A is different from that of the sixth configuration example inFIG.132.

In the conductor layer A of the sixth configuration example inFIG.132, a row in which the relay conductor1241is formed and a row in which the relay conductor1241is not formed are alternately arranged in the Y direction in units of rows in the gaps in a matrix of the reticulated conductor1201.

The conductor layer A of the ninth configuration example inFIG.141has a configuration in which a relay conductor1243(third relay conductor) is newly provided in the gaps of the row where the relay conductors1241of the conductor layer A of the sixth configuration example ofFIG.132are not formed. The relay conductor1243is, for example, wiring (Vss wiring) connected to the GND or the negative power supply.

That is, the conductor layer A of the ninth configuration example inFIG.141includes the reticulated conductor1201, and has a configuration in which a row in which the relay conductor1241is formed and a column in which a relay conductor1243is formed are alternately arranged in the Y direction in units of rows in the gaps in a matrix of the reticulated conductor1201.

For example, in a case of a stacking order in which the conductor layers A to C of the ninth configuration example inFIG.141are in the order of the conductor layer B, the conductor layer C, and the conductor layer A, and the conductor layer C is arranged in the center, the relay conductor1242of the conductor layer B can be connected to the linear conductor1221A of the conductor layer C via a conductor via in the Z direction, and the reticulated conductor1202of the conductor layer B can be connected to the linear conductor1221B of the conductor layer C via a conductor via in the Z direction. Furthermore, the relay conductor1241of the conductor layer A is connected to the linear conductor1221B of the conductor layer C by a conductor via in the Z direction, and the relay conductor1243is connected to the linear conductor1221A of the conductor layer C by a conductor via in the Z direction. Moreover, the reticulated conductor1201of the conductor layer A can be connected to the linear conductor1221A of the conductor layer C by a conductor via in the Z direction. Furthermore, the relay conductor1243may be connected to a conductor of a conductor layer different from the conductor layers A to C via a conductor via in the Z direction. Furthermore, not all the relay conductors1243may be used for electrical connection, all the relay conductors1243may be used for electrical connection, or some of the relay conductors1243may be used for electrical connection.

By providing the relay conductor1241in the conductor layer A, it becomes possible to connect the linear conductor1221B at substantially the shortest distance or a short distance, thereby reducing the voltage drop, energy loss, or inductive noise.

By providing the relay conductor1243in the conductor layer A, it becomes possible to connect the linear conductor1221A at substantially the shortest distance or a short distance, thereby reducing the voltage drop, energy loss, or inductive noise.

By providing the relay conductor1242in the conductor layer B, it becomes possible to connect the linear conductor1221A at substantially the shortest distance or a short distance, thereby reducing the voltage drop, energy loss, or inductive noise.

The ninth configuration example inFIG.141is similar to the sixth configuration example inFIG.132except for the above-described points.

The conductor layer C in A inFIG.141is the same as the conductor layer C of the sixth configuration example inFIG.132. Therefore, when the conductor layer C is viewed in a predetermined plane range (plane region), the current distribution of the linear conductor1221A and the current distribution of the linear conductor1221B become the same or substantially the same, so that generation of inductive noise can be suppressed.

Since the linear conductor1221A and the linear conductor1221B have the same wiring pattern repeated in the Y direction, the capacitive noise can be completely canceled in the Y direction. The capacitive noise can be significantly improved as the conductor layer C is closer to the wiring layer170.

As illustrated in F inFIG.141, the stacked layer of the conductor layers A and B has a light-shielding structure, and the hot carrier light emission from the active element group167can be shielded. In addition, as illustrated in D and E inFIG.141, the stacked layer of the conductor layers A and C and the stacked layer of the conductor layers B and C have also a light-shielding structure, and the light-shielding property is maintained. Thereby, since the light-shielding restrictions of the conductor layers A and B can be significantly alleviated, the conductive area of the conductor layers A and B can be used to the maximum, the wiring resistance can be lowered, and the voltage drop can be further improved. Furthermore, the degree of freedom in layout of the conductor layers A and B can be improved.

In the ninth configuration example inFIG.141, the direction in which the current of the conductor layer C is likely to flow and the direction in which the current of the conductor layers A and B is likely to flow are substantially orthogonal and differ by approximately 90 degrees. As a result, the current becomes easily diffused (the current is less likely to be concentrated), so that the inductive noise can be further improved.

First Modification of Ninth Configuration Example of Three-Layer Conductor Layer

FIG.142illustrates a first modification of the ninth configuration example of the three-layer conductor layer.

A inFIG.142illustrates the conductor layer C (wiring layer165C), B inFIG.142illustrates the conductor layer A (wiring layer165A), and C inFIG.142illustrates the conductor layer B (wiring layer165B).

Furthermore, D inFIG.142is a plan view of a stacked state of the conductor layer A and the conductor layer C, E inFIG.142is a plan view of a stacked state of the conductor layer B and the conductor layer C, and F inFIG.142is a plan view of a stacked state of the conductor layer A and the conductor layer B.

The first modification of the ninth configuration example has a configuration in which a part of the first modification of the sixth configuration example inFIG.133is changed. InFIG.142, parts corresponding to those inFIG.133are given the same reference numerals and description of the parts will be omitted as appropriate, and different parts will be described.

In the first modification of the ninth configuration example, only the configuration of the conductor layer A is different from that of the first modification of the sixth configuration example inFIG.133.

In the conductor layer A of the first modification of the sixth configuration example inFIG.133, a column in which the relay conductor1241is formed and a column in which the relay conductor1241is not formed are alternately arranged in the Y direction in units of columns in the gaps in a matrix of the reticulated conductor1201.

The conductor layer A of the first modification of the ninth configuration example inFIG.142has a configuration in which the relay conductor1243is newly provided in the gaps of the column where the relay conductors1241of the conductor layer A of the first modification of the sixth configuration example inFIG.133are not formed.

That is, the conductor layer A of the first modification of the ninth configuration example inFIG.142includes the reticulated conductor1201, and has a configuration in which a column in which the relay conductor1241is formed and a column in which a relay conductor1243is formed are alternately arranged in the X direction in units of columns in the gaps in a matrix of the reticulated conductor1201.

For example, in the case of the stacking order in which the conductor layers A to C of the ninth configuration example inFIG.142are in the order of the conductor layer B, the conductor layer C, and the conductor layer A, and the conductor layer C is arranged in the center, the relay conductor1242of the conductor layer B can be connected to the linear conductor1251A of the conductor layer C, and the reticulated conductor1202of the conductor layer B can be connected to the linear conductor1251B of the conductor layer C via a conductor via in the Z direction. Furthermore, the relay conductor1241of the conductor layer A can be connected to the linear conductor1251B of the conductor layer C, and the relay conductor1243can be connected to the linear conductor1251A of the conductor layer C. Moreover, the reticulated conductor1201of the conductor layer A can be connected to the linear conductor1251A of the conductor layer C by a conductor via in the Z direction.

By providing the relay conductor1241in the conductor layer A, it becomes possible to connect the linear conductor1251B at substantially the shortest distance or a short distance, thereby reducing the voltage drop, energy loss, or inductive noise.

By providing the relay conductor1243in the conductor layer A, it becomes possible to connect the linear conductor1251A at substantially the shortest distance or a short distance, thereby reducing the voltage drop, energy loss, or inductive noise.

By providing the relay conductor1242in the conductor layer B, it becomes possible to connect the linear conductor1251A at substantially the shortest distance or a short distance, thereby reducing the voltage drop, energy loss, or inductive noise.

The first modification of the ninth configuration example inFIG.142is similar to the first modification of the sixth configuration example inFIG.133except for the above-described points.

The conductor layer C in A inFIG.142is the same as the conductor layer C of the sixth configuration example inFIG.132. Therefore, when the conductor layer C is viewed in a predetermined plane range (plane region), the current distribution of the linear conductor1251A and the current distribution of the linear conductor1251B become the same or substantially the same, so that generation of inductive noise can be suppressed.

Since the linear conductor1251A and the linear conductor1251B repeat the same wiring pattern in the X direction, the capacitive noise can be completely canceled in the X direction. The capacitive noise can be significantly improved as the conductor layer C is closer to the wiring layer170.

As illustrated in F inFIG.142, the stacked layer of the conductor layers A and B has a light-shielding structure, and the hot carrier light emission from the active element group167can be shielded. In addition, as illustrated in D inFIG.142, the stacked layer of the conductor layers A and C has also a light-shielding structure, and the light-shielding property is maintained. Thereby, since the light-shielding restrictions of the conductor layers A and B can be significantly alleviated, the conductive area of the conductor layers A and B can be used to the maximum, the wiring resistance can be lowered, and the voltage drop can be further improved. Furthermore, the degree of freedom in layout of the conductor layers A and B can be improved.

In the first modification of the ninth configuration example inFIG.142, the direction in which the current of the conductor layer C is likely to flow and the direction in which the current of the conductor layers A and B is likely to flow are the same or substantially the same. In this case, the voltage drop can be further improved depending on the wiring layout.

Second Modification of Ninth Configuration Example of Three-Layer Conductor Layer

FIG.143illustrates a second modification of the ninth configuration example of the three-layer conductor layer.

A inFIG.143illustrates the conductor layer C (wiring layer165C), B inFIG.143illustrates the conductor layer A (wiring layer165A), and C inFIG.143illustrates the conductor layer B (wiring layer165B).

Furthermore, D inFIG.143is a plan view of a stacked state of the conductor layer A and the conductor layer C, E inFIG.143is a plan view of a stacked state of the conductor layer B and the conductor layer C, and F inFIG.143is a plan view of a stacked state of the conductor layer A and the conductor layer B.

The second modification of the ninth configuration example has a configuration in which a part of the ninth configuration example inFIG.141is changed. InFIG.143, parts corresponding to those inFIG.141are given the same reference numerals and description of the parts will be omitted as appropriate, and different parts will be described.

In the second modification of the ninth configuration example, only the configuration of the conductor layer B is different from that of the ninth configuration example inFIG.141.

The conductor layer B of the ninth configuration example inFIG.141has the reticulated conductor1202, and the relay conductor1242is formed in all the gaps in the matrix of the reticulated conductor1202.

In contrast, in the second modification of the ninth configuration example inFIG.143, a row in which the relay conductor1242is formed and a row in which the relay conductor1244(fourth relay conductor) is formed are alternately arranged in the Y direction in units of rows in the gaps of the reticulated conductor1201. The relay conductor1244is, for example, wiring (Vdd wiring) connected to the positive power supply.

For example, in the case of the stacking order in which the conductor layers A to C of the second modification of the ninth configuration example inFIG.143are arranged in the order of the conductor layer B, the conductor layer A, and the conductor layer C, and the conductor layer A is arranged in the center, the relay conductor1242of the conductor layer B is connected to the reticulated conductor1201of the conductor layer A via a conductor via in the Z direction, and the relay conductor1244of the conductor layer B is connected to the reticulated conductor1202of the conductor layer B via a conductor of a conductor layer different from the conductor layers A to C. Furthermore, the reticulated conductor1202of the conductor layer B can be connected to the relay conductor1241of the conductor layer A by a conductor via in the Z direction. The relay conductor1241of the conductor layer A is connected to the linear conductor1221B of the conductor layer C by a conductor via in the Z direction, and the relay conductor1243is connected to the linear conductor1221A of the conductor layer C by a conductor via in the Z direction. Moreover, the reticulated conductor1201of the conductor layer A can be connected to the linear conductor1221A of the conductor layer C by a conductor via in the Z direction. Note that not all the relay conductors1244may be used for electrical connection, all the relay conductors1244may be used for electrical connection, or some of the relay conductors1244may be used for electrical connection. In the second modification of the ninth configuration example inFIG.143, the shape of the Vdd wiring and the shape of the Vss wiring in the conductor layers A and B are the same or substantially the same although there is a positional shift. Therefore, the layout of the conductor layers A to C may be easily designed, and the Vdd wiring and the Vss wiring may be easily made into a suitable current relationship or voltage relationship.

By providing the relay conductor1241in the conductor layer A, it becomes possible to connect the linear conductor1221B at substantially the shortest distance or a short distance, thereby reducing the voltage drop, energy loss, or inductive noise.

By providing the relay conductor1243in the conductor layer A, it becomes possible to connect the linear conductor1221A at substantially the shortest distance or a short distance, thereby reducing the voltage drop, energy loss, or inductive noise.

By providing the relay conductor1242in the conductor layer B, it becomes possible to connect the linear conductor1221A at substantially the shortest distance or a short distance, thereby reducing the voltage drop, energy loss, or inductive noise.

By providing the relay conductor1244in the conductor layer B, it becomes possible to connect the linear conductor1221B at substantially the shortest distance or a short distance, thereby reducing the voltage drop, energy loss, or inductive noise.

The second modification of the ninth configuration example inFIG.143is similar to the ninth configuration example inFIG.141except for the above-described points.

The conductor layer C in A inFIG.143is the same as the conductor layer C of the ninth configuration example inFIG.141. Therefore, when the conductor layer C is viewed in a predetermined plane range (plane region), the current distribution of the linear conductor1221A and the current distribution of the linear conductor1221B become the same or substantially the same, so that generation of inductive noise can be suppressed.

Since the linear conductor1221A and the linear conductor1221B have the same wiring pattern repeated in the Y direction, the capacitive noise can be completely canceled in the Y direction. The capacitive noise can be significantly improved as the conductor layer C is closer to the wiring layer170.

As illustrated in F inFIG.143, the stacked layer of the conductor layers A and B has a light-shielding structure, and the hot carrier light emission from the active element group167can be shielded. In addition, as illustrated in D and E inFIG.143, the stacked layer of the conductor layers A and C and the stacked layer of the conductor layers B and C have also a light-shielding structure, and the light-shielding property is maintained. Thereby, since the light-shielding restrictions of the conductor layers A and B can be significantly alleviated, the conductive area of the conductor layers A and B can be used to the maximum, the wiring resistance can be lowered, and the voltage drop can be further improved. Furthermore, the degree of freedom in layout of the conductor layers A and B can be improved.

In the ninth configuration example inFIG.143, the direction in which the current of the conductor layer C is likely to flow and the direction in which the current of the conductor layers A and B is likely to flow are substantially orthogonal and differ by approximately 90 degrees. As a result, the current becomes easily diffused (the current is less likely to be concentrated), so that the inductive noise can be further improved.

Third Modification of Ninth Configuration Example of Three-Layer Conductor Layer

FIG.144illustrates a third modification of the ninth configuration example of the three-layer conductor layer.

A inFIG.144illustrates the conductor layer C (wiring layer165C), B inFIG.144illustrates the conductor layer A (wiring layer165A), and C inFIG.144illustrates the conductor layer B (wiring layer165B).

Furthermore, D inFIG.144is a plan view of a stacked state of the conductor layer A and the conductor layer C, E inFIG.144is a plan view of a stacked state of the conductor layer B and the conductor layer C, and F inFIG.144is a plan view of a stacked state of the conductor layer A and the conductor layer B.

The third modification of the ninth configuration example has a configuration in which a part of the first modification of the ninth configuration example inFIG.142is changed. InFIG.144, parts corresponding to those inFIG.142are given the same reference numerals and description of the parts will be omitted as appropriate, and different parts will be described.

In the third modification of the ninth configuration example, only the configuration of the conductor layer B is different from the first modification of the ninth configuration example inFIG.142.

The conductor layer B of the first modification of the ninth configuration example inFIG.142has the reticulated conductor1202, and the relay conductor1242is formed in all the gaps in the matrix of the reticulated conductor1202.

In contrast, the conductor layer B of the third modification of the ninth configuration example inFIG.144includes the reticulated conductor1202, and has a configuration in which a column in which the relay conductor1242is formed and a column in which a relay conductor1244is formed are alternately arranged in the X direction in units of columns in the gaps in a matrix of the reticulated conductor1202.

For example, in the case of the stacking order in which the conductor layers A to C of the third modification of the ninth configuration example inFIG.144are arranged in the order of the conductor layer B, the conductor layer A, and the conductor layer C, and the conductor layer A is arranged in the center, the relay conductor1242of the conductor layer B is connected to the reticulated conductor1201of the conductor layer A via a conductor via in the Z direction, and the relay conductor1244of the conductor layer B is connected to the reticulated conductor1202of the conductor layer B via a conductor of a conductor layer different from the conductor layers A to C. Furthermore, the reticulated conductor1202of the conductor layer B can be connected to the relay conductor1241of the conductor layer A by a conductor via in the Z direction. The relay conductor1241of the conductor layer A is connected to the linear conductor1251B of the conductor layer C by a conductor via in the Z direction, and the relay conductor1243is connected to the linear conductor1251A of the conductor layer C by a conductor via in the Z direction. Moreover, the reticulated conductor1201of the conductor layer A can be connected to the linear conductor1251A of the conductor layer C by a conductor via in the Z direction. In the third modification of the ninth configuration example inFIG.144, the shape of the Vdd wiring and the shape of the Vss wiring in the conductor layers A and B are the same or substantially the same although there is a positional shift. Therefore, the layout of the conductor layers A to C may be easily designed, and the Vdd wiring and the Vss wiring may be easily made into a suitable current relationship or voltage relationship.

By providing the relay conductor1241in the conductor layer A, it becomes possible to connect the linear conductor1251B at substantially the shortest distance or a short distance, thereby reducing the voltage drop, energy loss, or inductive noise.

By providing the relay conductor1243in the conductor layer A, it becomes possible to connect the linear conductor1251A at substantially the shortest distance or a short distance, thereby reducing the voltage drop, energy loss, or inductive noise.

By providing the relay conductor1242in the conductor layer B, it becomes possible to connect the linear conductor1251A at substantially the shortest distance or a short distance, thereby reducing the voltage drop, energy loss, or inductive noise.

By providing the relay conductor1244in the conductor layer B, it becomes possible to connect the linear conductor1251B at substantially the shortest distance or a short distance, thereby reducing the voltage drop, energy loss, or inductive noise.

The third modification of the ninth configuration example inFIG.144is similar to the first modification of the ninth configuration example inFIG.142except for the above-described points.

The conductor layer C in A inFIG.144is the same as the conductor layer C of the first modification of the ninth configuration example ofFIG.142. Therefore, when the conductor layer C is viewed in a predetermined plane range (plane region), the current distribution of the linear conductor1251A and the current distribution of the linear conductor1251B become the same or substantially the same, so that generation of inductive noise can be suppressed.

Since the linear conductor1251A and the linear conductor1251B repeat the same wiring pattern in the X direction, the capacitive noise can be completely canceled in the X direction. The capacitive noise can be significantly improved as the conductor layer C is closer to the wiring layer170.

As illustrated in F inFIG.144, the stacked layer of the conductor layers A and B has a light-shielding structure, and the hot carrier light emission from the active element group167can be shielded. In addition, as illustrated in D inFIG.144, the stacked layer of the conductor layers A and C has also a light-shielding structure, and the light-shielding property is maintained. Thereby, since the light-shielding restrictions of the conductor layers A and B can be significantly alleviated, the conductive area of the conductor layers A and B can be used to the maximum, the wiring resistance can be lowered, and the voltage drop can be further improved. Furthermore, the degree of freedom in layout of the conductor layers A and B can be improved.

In the third modification of the ninth configuration example inFIG.144, the direction in which the current of the conductor layer C is likely to flow and the direction in which the current of the conductor layers A and B is likely to flow are the same or substantially the same. In this case, the voltage drop can be further improved depending on the wiring layout.

Fourth Modification of Ninth Configuration Example of Three-Layer Conductor Layer

FIG.145illustrates a fourth modification of the ninth configuration example of the three-layer conductor layer.

A inFIG.145illustrates the conductor layer C (wiring layer165C), B inFIG.145illustrates the conductor layer A (wiring layer165A), and C inFIG.145illustrates the conductor layer B (wiring layer165B).

Furthermore, D inFIG.145is a plan view of a stacked state of the conductor layer A and the conductor layer C, E inFIG.145is a plan view of a stacked state of the conductor layer B and the conductor layer C, and F inFIG.145is a plan view of a stacked state of the conductor layer A and the conductor layer B.

The fourth modification of the ninth configuration example has a configuration in which a part of the third modification of the ninth configuration example inFIG.144is changed. InFIG.145, parts corresponding to those inFIG.144are given the same reference numerals and description of the parts will be omitted as appropriate, and different parts will be described.

In the third modification inFIG.144, when comparing the positions of the gaps between the reticulated conductor1201of the conductor layer A and the reticulated conductor1202of the conductor layer B, the positions in the X direction are different and the positions in the Y direction match.

Meanwhile, in the fourth modification inFIG.145, when comparing the positions of the gaps between the reticulated conductor1201of the conductor layer A and the reticulated conductor1202of the conductor layer B, the positions in the X direction match and the positions in the Y direction are different.

Furthermore, for example, in the third modification inFIG.144, when comparing the positions between the relay conductor1241of the conductor layer A and the relay conductor1244of the conductor layer B, the positions in the X direction are different and the positions in the Y direction match. Meanwhile, in the fourth modification inFIG.145, the positions in the X direction match and the positions in the Y direction are different.

Furthermore, for example, in the third modification inFIG.144, when comparing the positions between the relay conductor1243of the conductor layer A and the relay conductor1242of the conductor layer B, the positions in the X direction are different and the positions in the Y direction match. Meanwhile, in the fourth modification inFIG.145, the positions in the X direction match and the positions in the Y direction are different.

In the third modification inFIG.144, the stacked layer of the conductor layers A and B and the stacked layer of the conductor layers A and C have a light-shielding structure, and the light-shielding property is maintained. Meanwhile, in the fourth modification inFIG.145, the stacked layer of the conductor layers A and C and the stacked layer of the conductor layers B and C have a light-shielding structure, and the light-shielding property is maintained. Thereby, since the light-shielding restrictions of the conductor layers A and B can be significantly alleviated, the conductive area of the conductor layers A and B can be used to the maximum, the wiring resistance can be lowered, and the voltage drop can be further improved. Furthermore, the degree of freedom in layout of the conductor layers A and B can be improved.

Furthermore, for example, in the case of the stacking order in which the conductor layers A to C of the fourth modification of the ninth configuration example inFIG.145are in the order of the conductor layer B, the conductor layer C, and the conductor layer A, and the conductor layer C is arranged in the center, the relay conductor1242of the conductor layer B is connected to the linear conductor1251A of the conductor layer C via a conductor via in the Z direction, and the relay conductor1244of the conductor layer B is connected to the linear conductor1251B of the conductor layer C via a conductor via in the Z direction. Furthermore, the reticulated conductor1202of the conductor layer B can be connected to the linear conductor1251B of the conductor layer C by a conductor via in the Z direction. The relay conductor1241of the conductor layer A is connected to the linear conductor1251B of the conductor layer C by a conductor via in the Z direction, and the relay conductor1243is connected to the linear conductor1251A of the conductor layer C by a conductor via in the Z direction. Moreover, the reticulated conductor1201of the conductor layer A can be connected to the linear conductor1251A of the conductor layer C by a conductor via in the Z direction. Furthermore, the relay conductor1244may be connected to a conductor of a conductor layer different from the conductor layers A to C via a conductor via in the Z direction.

The fourth modification inFIG.145is similar to the third modification inFIG.144except for the above-described points.

When the conductor layer C in A inFIG.145is viewed in a predetermined plane range (plane region), the current distribution of the linear conductor1251A and the current distribution of the linear conductor1251B become the same or substantially the same, so that generation of inductive noise can be suppressed.

Since the linear conductor1251A and the linear conductor1251B repeat the same wiring pattern in the X direction, the capacitive noise can be completely canceled in the X direction. The capacitive noise can be significantly improved as the conductor layer C is closer to the wiring layer170.

In the fourth modification of the ninth configuration example inFIG.145, the direction in which the current of the conductor layer C is likely to flow and the direction in which the current of the conductor layers A and B is likely to flow are the same or substantially the same. In this case, the voltage drop can be further improved depending on the wiring layout.

By providing the relay conductor1241in the conductor layer A, it becomes possible to connect the linear conductor1251B at substantially the shortest distance or a short distance, thereby reducing the voltage drop, energy loss, or inductive noise.

By providing the relay conductor1243in the conductor layer A, it becomes possible to connect the linear conductor1251A at substantially the shortest distance or a short distance, thereby reducing the voltage drop, energy loss, or inductive noise.

By providing the relay conductor1242in the conductor layer B, it becomes possible to connect the linear conductor1251A at substantially the shortest distance or a short distance, thereby reducing the voltage drop, energy loss, or inductive noise.

By providing the relay conductor1244in the conductor layer B, it becomes possible to connect the linear conductor1251B at substantially the shortest distance or a short distance, thereby reducing the voltage drop, energy loss, or inductive noise.

Tenth Configuration Example of Three-Layer Conductor Layer

FIG.146illustrates a tenth configuration example of the three-layer conductor layer.

A inFIG.146illustrates the conductor layer C (wiring layer165C), B inFIG.146illustrates the conductor layer A (wiring layer165A), and C inFIG.146illustrates the conductor layer B (wiring layer165B).

Furthermore, D inFIG.146is a plan view of a stacked state of the conductor layer A and the conductor layer C, E inFIG.146is a plan view of a stacked state of the conductor layer B and the conductor layer C, and F inFIG.146is a plan view of a stacked state of the conductor layer A and the conductor layer B.

The tenth configuration example has a configuration in which a part of the fourth configuration example inFIG.128is changed. InFIG.146, parts corresponding to those inFIG.128are given the same reference numerals and description of the parts will be omitted as appropriate, and different parts will be described.

In the tenth configuration example, only the configuration of the conductor layer C is different from that of the fourth configuration example inFIG.128.

The conductor layer C in A inFIG.146is configured such that a linear conductor1291A long in the X direction and a linear conductor1291B long in the X direction are alternately and periodically arranged in the Y direction. The linear conductor1219A is, for example, wiring (Vss wiring) connected to the GND or the negative power supply. The linear conductor1291B is, for example, wiring (Vdd wiring) connected to the positive power supply.

In the fourth configuration example inFIG.128, the conductor period FYC that is a repetition period of the linear conductor1221A of the conductor layer C in A inFIG.128is twice the conductor period FYA that is a repetition period in the Y direction of the reticulated conductor1201of the conductor layer A in B inFIG.128.

In contrast, the conductor period FYC that is a repetition period of the linear conductor1291A of the conductor layer C in A inFIG.146is one time the conductor period FYA that is a repetition period in the Y direction of the reticulated conductor1201of the conductor layer A in B inFIG.146.

Similarly, in the fourth configuration example inFIG.128, the conductor period FYC of the linear conductor1221B of the conductor layer C in A inFIG.128is twice the conductor period FYB of the reticulated conductor1202of the conductor layer B in C inFIG.128, whereas the conductor period FYC of the linear conductor1291B of the conductor layer C in A inFIG.146is one time the conductor period FYB of the reticulated conductor1202of the conductor layer B in C inFIG.146.

The tenth configuration example inFIG.146is similar to the fourth configuration example inFIG.128except for the above-described points.

When the conductor layer C in A inFIG.146is viewed in a predetermined plane range (plane region), the current distribution of the linear conductor1291A and the current distribution of the linear conductor1291B become the same or substantially the same, so that generation of inductive noise can be suppressed.

Since the linear conductor1291A and the linear conductor1291B repeat the same wiring pattern in the Y direction, the capacitive noise can be completely canceled in the Y direction. The capacitive noise can be significantly improved as the conductor layer C is closer to the wiring layer170.

As illustrated in F inFIG.146, the stacked layer of the conductor layers A and B has a light-shielding structure, and the hot carrier light emission from the active element group167can be shielded. In addition, as illustrated in D and E inFIG.132, the light-shielding property is maintained in a fixed range in the stacked layer of the conductor layers A and C and the stacked layer of the conductor layers B and C. Thereby, since the light-shielding restrictions of the conductor layers A and B can be alleviated, the conductive area of the conductor layers A and B can be used to the maximum, the wiring resistance can be lowered, and the voltage drop can be further improved. Furthermore, the degree of freedom in layout of the conductor layers A and B can be improved.

In the tenth configuration example inFIG.146, the direction in which the current of the conductor layer C is likely to flow and the direction in which the current of the conductor layers A and B is likely to flow are substantially orthogonal and differ by approximately 90 degrees. As a result, the current becomes easily diffused (the current is less likely to be concentrated), so that the inductive noise can be further improved.

By providing the relay conductor1241in the conductor layer A, it becomes possible to connect the linear conductor1291B at substantially the shortest distance or a short distance, thereby reducing the voltage drop, energy loss, or inductive noise.

By providing the relay conductor1242in the conductor layer B, it becomes possible to connect the linear conductor1291A at substantially the shortest distance or a short distance, thereby reducing the voltage drop, energy loss, or inductive noise.

Modification of Tenth Configuration Example of Three-Layer Conductor Layer

FIG.147illustrates a modification of the tenth configuration example of the three-layer conductor layer.

A inFIG.147illustrates the conductor layer C (wiring layer165C), B inFIG.147illustrates the conductor layer A (wiring layer165A), and C inFIG.147illustrates the conductor layer B (wiring layer165B).

Furthermore, D inFIG.147is a plan view of a stacked state of the conductor layer A and the conductor layer C, E inFIG.147is a plan view of a stacked state of the conductor layer B and the conductor layer C, and F inFIG.147is a plan view of a stacked state of the conductor layer A and the conductor layer B.

The modification of the tenth configuration example has a configuration in which a part of the fourth configuration example inFIG.128is changed. InFIG.147, parts corresponding to those inFIG.128are given the same reference numerals and description of the parts will be omitted as appropriate, and different parts will be described.

In the modification of the tenth configuration example, only the configuration of the conductor layer C is different from that of the fourth configuration example inFIG.128.

The conductor layer C in A inFIG.147is configured such that a linear conductor1301A long in the X direction and a linear conductor1301B long in the X direction are alternately and periodically arranged in the Y direction. The linear conductor1301A is, for example, wiring (Vss wiring) connected to the GND or the negative power supply. The linear conductor1301B is, for example, wiring (Vdd wiring) connected to the positive power supply. The distance between the linear conductor1301A and the linear conductor1301B is alternately changed between a gap width GYC1 and a gap width GYC2.

In the fourth configuration example inFIG.128, the conductor period FYC that is a repetition period of the linear conductor1221A of the conductor layer C in A inFIG.128is twice the conductor period FYA that is a repetition period in the Y direction of the reticulated conductor1201of the conductor layer A in B inFIG.128.

In contrast, the conductor period FYC that is a repetition period of the linear conductor1301A of the conductor layer C in A inFIG.147is (1/integer) times the conductor period FYA that is a repetition period in the Y direction of the reticulated conductor1201of the conductor layer A in B inFIG.147.FIG.147illustrates an example in which the conductor period FYC is ½ times the conductor period FYA.

Similarly, in the fourth configuration example inFIG.128, the conductor period FYC of the linear conductor1221B of the conductor layer C in A inFIG.128is twice the conductor period FYB of the reticulated conductor1202of the conductor layer A in C inFIG.128, whereas the conductor period FYC of the linear conductor1301B of the conductor layer C in A inFIG.147is (1/integer) times the conductor period FYB of the reticulated conductor1202of the conductor layer B in C inFIG.147.FIG.147illustrates an example in which the conductor period FYC is ½ times the conductor period FYB.

The modification of the tenth configuration example inFIG.147is similar to the fourth configuration example inFIG.128except for the above-described points.

When the conductor layer C in A inFIG.147is viewed in a predetermined plane range (plane region), the current distribution of the linear conductor1301A and the current distribution of the linear conductor1301B become the same or substantially the same, so that generation of inductive noise can be suppressed.

Since the linear conductor1301A and the linear conductor1301B repeat the same wiring pattern in the Y direction, the capacitive noise can be completely canceled in the Y direction. The capacitive noise can be significantly improved as the conductor layer C is closer to the wiring layer170.

As illustrated in F inFIG.147, the hot carrier light emission from the active element group167can be shielded by the stacked layer of the conductor layers A and B. In addition, as illustrated in D and E inFIG.132, the light-shielding property is maintained in a fixed range in the stacked layer of the conductor layers A and C and the stacked layer of the conductor layers B and C. Thereby, since the light-shielding restrictions of the conductor layers A and B can be alleviated, the conductive area of the conductor layers A and B can be used to the maximum, the wiring resistance can be lowered, and the voltage drop can be further improved. Furthermore, the degree of freedom in layout of the conductor layers A and B can be improved.

In the modification of the tenth configuration example inFIG.147, the direction in which the current of the conductor layer C is likely to flow and the direction in which the current of the conductor layers A and B is likely to flow are substantially orthogonal and differ by approximately 90 degrees. As a result, the current becomes easily diffused (the current is less likely to be concentrated), so that the inductive noise can be further improved.

By providing the relay conductor1241in the conductor layer A, it becomes possible to connect the linear conductor1301B at substantially the shortest distance or a short distance, thereby reducing the voltage drop, energy loss, or inductive noise.

By providing the relay conductor1242in the conductor layer B, it becomes possible to connect the linear conductor1301A at substantially the shortest distance or a short distance, thereby reducing the voltage drop, energy loss, or inductive noise.

Eleventh Configuration Example of Three-Layer Conductor Layer

In the first to tenth configuration examples of the three-layer conductor layer, the description has been made adopting the eleventh configuration example using the reticulated conductor having the resistance value in the X direction and the resistance value in the Y direction, which are different, as the configuration of the conductor layer A and the conductor layer B. In other words, the description has been made adopting the configuration in which the gap width GXA in the X direction and the gap width GYA in the Y direction are different, and the gap width GXB in the X direction and the gap width GYB in the Y direction are different, as in the reticulated conductors1201and1202of the fourth configuration example inFIG.128and the reticulated conductors1261and1602of the fifth configuration example inFIG.131, as the conductor layer A and the conductor layer B.

However, as the conductor layer A and the conductor layer B, any of the first to thirteenth configuration examples of the conductor layers A and B described with reference toFIGS.12to41can be adopted.

In nextFIGS.148to152, a configuration of uniformly adopting the configuration adopted inFIG.122or the like for the conductor layer C (wiring layer165C), and adopting a reticulated conductor having the same resistance value in the X direction and Y directions for the conductor layer A and the conductor layer B will be described.

FIG.148illustrates an eleventh configuration example of the three-layer conductor layer.

A inFIG.148illustrates the conductor layer C (wiring layer165C), B inFIG.148illustrates the conductor layer A (wiring layer165A), and C inFIG.148illustrates the conductor layer B (wiring layer165B).

Furthermore, D inFIG.148is a plan view of a stacked state of the conductor layer A and the conductor layer C, E inFIG.148is a plan view of a stacked state of the conductor layer B and the conductor layer C, and F inFIG.148is a plan view of a stacked state of the conductor layer A and the conductor layer B.

In the eleventh configuration example inFIG.148, a portion corresponding to that in the fourth configuration example illustrated inFIG.128is given the same reference numeral and description of the portion is omitted as appropriate, and description will be given focusing on different portions.

The conductor layer C in A inFIG.148is configured such that the linear conductor1221A long in the X direction and the linear conductor1221B long in the X direction are alternately and periodically arranged in the Y direction with the conductor period FYC.

The conductor layer A in B inFIG.148is configured by a reticulated conductor1311. The reticulated conductor1311has the conductor width WXA, the gap width GXA, and the conductor period FXA in the X direction, and the conductor width WYA, the gap width GYA, and the conductor period FYA in the Y direction. Here, the conductor width WXA=the conductor width WYA, the gap width GXA=the gap width GYA, and the conductor period FXA=the conductor period FYA. Furthermore, the relay conductor1241is arranged in each gap of the reticulated conductor1201. The distance between the relay conductors1241, in other words, the period of the relay conductor1241is also the conductor periods FXA and FYA. The reticulated conductor1311is, for example, wiring (Vss wiring) connected to the GND or the negative power supply.

The conductor layer B in C inFIG.148is configured by a reticulated conductor1312. The reticulated conductor1312has the conductor width WXB, the gap width GXB, and the conductor period FXB in the X direction, and the conductor width WYB, the gap width GYB, and the conductor period FYB in the Y direction. Here, the conductor width WXB=the conductor width WYB, the gap width GXB=the gap width GYB, and the conductor period FXB=the conductor period FYB. Furthermore, the relay conductor1242is arranged in each gap of the reticulated conductor1312. The distance between the relay conductors1242, in other words, the period of the relay conductors1242is also the conductor periods FXB and FYB. The reticulated conductor1312is, for example, wiring (Vdd wiring) connected to the positive power supply.

As illustrated in B and C inFIG.148, the plane position of the relay conductor1241formed in the conductor layer A and the plane position of the relay conductor1242formed in the conductor layer B are the same. In other words, the reticulated conductor1311of the conductor layer A and the reticulated conductor1312of the conductor layer B entirely overlap when viewed from the stacking direction. The conductor layer A and the conductor layer B having such a configuration correspond to the second configuration example of the conductor layers A and B illustrated inFIG.15, and can significantly improve the inductive noise, as illustrated in the simulation result inFIG.17.

Therefore, the configuration is suitable for the stacking order in which the conductor layer C (wiring layer165C) is arranged between the conductor layer A (wiring layer165A) and the conductor layer B (wiring layer165B) as illustrated in B inFIG.120, the reticulated conductor1311of the conductor layer A and the linear conductor1221A of the conductor layer C are connected via the conductor via in the Z direction, and the reticulated conductor1312of the conductor layer B and the linear conductor1221B of the conductor layer C are connected via the conductor via in the Z direction.

When the conductor layer C is viewed in a predetermined plane range (plane region), the current distribution of the linear conductor1221A and the current distribution of the linear conductor1221B become the same or substantially the same, so that generation of inductive noise can be suppressed.

Since the linear conductor1221A and the linear conductor1221B of the conductor layer C repeat the same wiring pattern in the Y direction, the capacitive noise can be completely canceled in the Y direction. The capacitive noise can be significantly improved as the conductor layer C is closer to the wiring layer170.

As illustrated in F inFIG.148, the stacked layer of the conductor layer A and the conductor layer B does not have a light-shielding structure, but as illustrated in D and E inFIG.148, the stacked layer of the conductor layers A and C and the stacked layer of the conductor layers B and C have a light-shielding structure, and the light-shielding property is maintained. As a result, the hot carrier light emission from the active element group167can be shielded. Furthermore, since the light-shielding restrictions of the conductor layers A and B can be significantly alleviated, the conductive area of the conductor layers A and B can be used to the maximum, the wiring resistance can be lowered, and the voltage drop can be further improved. The degree of freedom in layout of the conductor layers A and B can be improved.

Twelfth Configuration Example of Three-Layer Conductor Layer

FIG.149illustrates a twelfth configuration example of the three-layer conductor layer.

A inFIG.149illustrates the conductor layer C (wiring layer165C), B inFIG.149illustrates the conductor layer A (wiring layer165A), and C inFIG.149illustrates the conductor layer B (wiring layer165B).

Furthermore, D inFIG.149is a plan view of a stacked state of the conductor layer A and the conductor layer C, E inFIG.149is a plan view of a stacked state of the conductor layer B and the conductor layer C, and F inFIG.149is a plan view of a stacked state of the conductor layer A and the conductor layer B.

In the twelfth configuration example inFIG.149, a portion corresponding to that in the fourth configuration example illustrated inFIG.128is given the same reference numeral and description of the portion is omitted as appropriate, and description will be given focusing on different portions.

The conductor layer C in A inFIG.149is configured such that the linear conductor1221A long in the X direction and the linear conductor1221B long in the X direction are alternately and periodically arranged in the Y direction with the conductor period FYC.

The conductor layer A in B inFIG.149is configured by a planar conductor1321. The planar conductor1321is, for example, wiring (Vss wiring) connected to the GND or the negative power supply.

The conductor layer B in C inFIG.149is configured by a planar conductor1322. The planar conductor1322is, for example, wiring (Vdd wiring) connected to the positive power supply.

When the conductor layer C is viewed in a predetermined plane range (plane region), the current distribution of the linear conductor1221A and the current distribution of the linear conductor1221B become the same or substantially the same, so that generation of inductive noise can be suppressed.

Since the linear conductor1222A and the linear conductor1222B repeat the same wiring pattern in the Y direction, the capacitive noise can be completely canceled in the Y direction. The capacitive noise can be significantly improved as the conductor layer C is closer to the wiring layer170.

As illustrated in F inFIG.149, the stacked layer of the conductor layers A and B has a light-shielding structure, and the hot carrier light emission from the active element group167can be shielded. In addition, as illustrated in D and E inFIG.149, the stacked layer of the conductor layers A and C and the stacked layer of the conductor layers B and C have also a light-shielding structure, and the light-shielding property is maintained. Thereby, since the light-shielding restrictions of the conductor layers A and B can be significantly alleviated, the conductive area of the conductor layers A and B can be used to the maximum, the wiring resistance can be lowered, and the voltage drop can be further improved. Furthermore, the degree of freedom in layout of the conductor layers A and B can be improved.

Therefore, the twelfth configuration example of the three-layer conductor layer is suitable for the stacking order in which the conductor layer C (wiring layer165C) is arranged between the conductor layer A (wiring layer165A) and the conductor layer B (wiring layer165B), the planar conductor1321of the conductor layer A and the linear conductor1221A of the conductor layer C are connected via the conductor via in the Z direction, and the planar conductor1322of the conductor layer B and the linear conductor1221B of the conductor layer C are connected via the conductor via in the Z direction, as illustrated in B inFIG.120.

Modification of Twelfth Configuration Example of Three-Layer Conductor Layer

FIG.150illustrates a first modification of the twelfth configuration example of the three-layer conductor layer.

A inFIG.150illustrates the conductor layer C (wiring layer165C), B inFIG.150illustrates the conductor layer A (wiring layer165A), and C inFIG.150illustrates the conductor layer B (wiring layer165B).

Furthermore, D inFIG.150is a plan view of a stacked state of the conductor layer A and the conductor layer C, E inFIG.150is a plan view of a stacked state of the conductor layer B and the conductor layer C, and F inFIG.150is a plan view of a stacked state of the conductor layer A and the conductor layer B.

InFIG.150, a portion corresponding to those in the eleventh and twelfth configuration examples illustrated inFIGS.148and149is given the same reference numeral and description of the portion is omitted as appropriate, and description will be given focusing on different portions.

In the first modification of the twelfth configuration example, only the configuration of the conductor layer B in C inFIG.150is different from that inFIG.149.

The conductor layer B in C inFIG.150is configured by a reticulated conductor1312and a relay conductor1242formed in a gap of the reticulated conductor1312.

The twelfth configuration example illustrated inFIG.149is a configuration in which the reticulated conductor1311and the relay conductor1241of the eleventh configuration example of the three-layer conductor layer illustrated inFIG.148are changed to the planar conductor1321in the conductor layer A, and the reticulated conductor1312and the relay conductor1242of the eleventh configuration example of the three-layer conductor layer illustrated inFIG.148are changed to the planar conductor1322in the conductor layer B.

In contrast, the first modification of the twelfth configuration example inFIG.150is a configuration in which the reticulated conductor1311and the relay conductor1241of the eleventh configuration example of the three-layer conductor layer illustrated inFIG.148are changed to the planar conductor1321in the conductor layer A, and the reticulated conductor1312and the relay conductor1242, as in the eleventh configuration example of the three-layer conductor layer illustrated inFIG.148, are used in the conductor layer B.

FIG.151illustrates a second modification of the twelfth configuration example of the three-layer conductor layer.

A inFIG.151illustrates the conductor layer C (wiring layer165C), B inFIG.151illustrates the conductor layer A (wiring layer165A), and C inFIG.151illustrates the conductor layer B (wiring layer165B).

Furthermore, D inFIG.151is a plan view of a stacked state of the conductor layer A and the conductor layer C, E inFIG.151is a plan view of a stacked state of the conductor layer B and the conductor layer C, and F inFIG.151is a plan view of a stacked state of the conductor layer A and the conductor layer B.

InFIG.151, a portion corresponding to those in the eleventh and twelfth configuration examples illustrated inFIGS.148and149is given the same reference numeral and description of the portion is omitted as appropriate, and description will be given focusing on different portions.

In the second modification of the twelfth configuration example, only the configuration of the conductor layer A in B inFIG.151is different from that inFIG.149.

The twelfth configuration example illustrated inFIG.149is a configuration in which the reticulated conductor1311and the relay conductor1241of the eleventh configuration example of the three-layer conductor layer illustrated inFIG.148are changed to the planar conductor1321in the conductor layer A, and the reticulated conductor1312and the relay conductor1242of the eleventh configuration example of the three-layer conductor layer illustrated inFIG.148are changed to the planar conductor1322in the conductor layer B.

In contrast, the second modification of the twelfth configuration example inFIG.151is a configuration in which the reticulated conductor1311and the relay conductor1241, as in the eleventh configuration example of the three-layer conductor layer illustrated inFIG.148, are used in the conductor layer A, and the reticulated conductor1312and the relay conductor1242of the eleventh configuration example of the three-layer conductor layer illustrated inFIG.148are changed to the planar conductor1322in the conductor layer B.

The first modification and the second modification have effects similar to those of the twelfth configuration example illustrated inFIG.149.

That is, when the conductor layer C is viewed in a predetermined plane range (plane region), the current distribution of the linear conductor1221A and the current distribution of the linear conductor1221B become the same or substantially the same, so that generation of inductive noise can be suppressed.

Since the linear conductor1222A and the linear conductor1222B repeat the same wiring pattern in the Y direction, the capacitive noise can be completely canceled in the Y direction. The capacitive noise can be significantly improved as the conductor layer C is closer to the wiring layer170.

The stacked layer of the conductor layers A and B has a light-shielding structure, and the hot carrier light emission from the active element group167can be shielded. In addition, the stacked layer of the conductor layers A and C and the stacked layer of the conductor layers B and C have also a light-shielding structure, and the light-shielding property is maintained. Thereby, since the light-shielding restrictions of the conductor layers A and B can be significantly alleviated, the conductive area of the conductor layers A and B can be used to the maximum, the wiring resistance can be lowered, and the voltage drop can be further improved. Furthermore, the degree of freedom in layout of the conductor layers A and B can be improved.

The first modification inFIG.150is particularly suitable for the stacking order in which the three conductor layers A to C can be electrically connected, specifically for the stacking orders illustrated in A and B inFIG.120. For example, in the case of the stacking order of the conductor layers A, B, and C illustrated in A inFIG.120, the planar conductor1321of the conductor layer A and the relay conductor1242of the conductor layer B can be connected, and the reticulated conductor1312and the relay conductor1242of the conductor layer B can be respectively connected with the linear conductors1221B and1221A of the conductor layer C via the conductor via in the Z direction between the conductors having common current characteristics and in a part of a region where plane regions overlap.

The second modification inFIG.151is particularly suitable for the stacking order in which the three conductor layers A to C can be electrically connected, specifically for the stacking orders illustrated in B and C inFIG.120. For example, in the case of the stacking order of the conductor layers A, B, and C illustrated in B inFIG.120, the reticulated conductor1311and the relay conductor1241of the conductor layer A can be respectively connected with the linear conductors1221A and1221B of the conductor layer C via the conductor via in the Z direction between the conductors having common current characteristics and in a part of a region where plane regions overlap, and the planar conductor1322of the conductor layer B and the linear conductor1221B of the conductor layer C can be connected.

Thirteenth Configuration Example of Three-Layer Conductor Layer

FIG.152illustrates a thirteenth configuration example of the three-layer conductor layer.

A inFIG.152illustrates the conductor layer C (wiring layer165C), B inFIG.152illustrates the conductor layer A (wiring layer165A), and C inFIG.152illustrates the conductor layer B (wiring layer165B).

Furthermore, D inFIG.152is a plan view of a stacked state of the conductor layer A and the conductor layer C, E inFIG.152is a plan view of a stacked state of the conductor layer B and the conductor layer C, and F inFIG.152is a plan view of a stacked state of the conductor layer A and the conductor layer B.

In the twelfth configuration example inFIG.152, a portion corresponding to that in the eleventh configuration example illustrated inFIG.148is given the same reference numeral and description of the portion is omitted as appropriate, and description will be given focusing on different portions.

In the thirteenth configuration example, only the configuration of the conductor layer A in B inFIG.152is different from that inFIG.148.

The conductor layer A in B inFIG.152is configured by a reticulated conductor1331. The reticulated conductor1331is, for example, wiring (Vss wiring) connected to the GND or the negative power supply. The reticulated conductor1331has the conductor width WXA, the gap width GXA, and the conductor period FXA in the X direction, and the conductor width WYA, the gap width GYA, and the conductor period FYA in the Y direction. Here, the conductor width WXA=the conductor width WYA, the gap width GXA=the gap width GYA, and the conductor period FXA=the conductor period FYA. Note that the gap width GXA and the gap width GYA of the gap of the reticulated conductor1331are smaller than the gap width GXB and the gap width GYB of the gap of the reticulated conductor1312of the conductor layer B (the gap width GXA=the gap width GYA<the gap width GXB=the gap width GYB). Furthermore, no relay conductor is formed in the gap of the reticulated conductor1331.

The thirteenth configuration example inFIG.152is similar to the eleventh configuration example inFIG.148except for the above-described points.

When the conductor layer C in A inFIG.152is viewed in a predetermined plane range (plane region), the current distribution of the linear conductor1221A and the current distribution of the linear conductor1221B become the same or substantially the same, so that generation of inductive noise can be suppressed.

Since the linear conductor1221A and the linear conductor1221B have the same wiring pattern repeated in the Y direction, the capacitive noise can be completely canceled in the Y direction. The capacitive noise can be significantly improved as the conductor layer C is closer to the wiring layer170.

As illustrated in D and E inFIG.152, the stacked layer of the conductor layers A and C and the stacked layer of the conductor layers B and C have a light-shielding structure, and the light-shielding property is maintained. Thereby, since the light-shielding restrictions of the conductor layers A and B can be significantly alleviated, the conductive area of the conductor layers A and B can be used to the maximum, the wiring resistance can be lowered, and the voltage drop can be further improved. Furthermore, the degree of freedom in layout of the conductor layers A and B can be improved.

By providing the relay conductor1242in the conductor layer B, it becomes possible to connect the linear conductor1221A at substantially the shortest distance or a short distance, thereby reducing the voltage drop, energy loss, or inductive noise.

The thirteenth configuration example inFIG.152is particularly suitable for the stacking order in which the three layers of the conductor layers A to C can be electrically connected, specifically for the stacking order illustrated in B inFIG.120. For example, in the case of the stacking order of the conductor layers A, B, and C illustrated in B inFIG.120, the reticulated conductor1331of the conductor layer A and the linear conductor1221A of the conductor layer C can be connected via the conductor via in the Z direction, and the reticulated conductor1312and the relay conductor1242of the conductor layer B can be respectively connected with the linear conductors1221B and1221A of the conductor layer C via the conductor via in the Z direction between the conductors having common current characteristics and in a part of a region where plane regions overlap.

Fourteenth Configuration Example of Three-Layer Conductor Layer

The first to thirteenth configuration examples of the three-layer conductor layer have been described adopting the configuration using the linear conductor long in the X direction or the linear conductor long in the Y direction, which is a vertical stripe or horizontal stripe wiring pattern, as the configuration of the conductor layer C.

However, the conductor layer C is not limited to the vertical stripe or horizontal stripe wiring pattern.

In nextFIGS.153to163, a case where the conductor layer C has a configuration other than the vertical stripe or horizontal stripe wiring pattern will be described.

FIG.153illustrates a fourteenth configuration example of the three-layer conductor layer.

A inFIG.153illustrates the conductor layer C (wiring layer165C), B inFIG.153illustrates the conductor layer A (wiring layer165A), and C inFIG.153illustrates the conductor layer B (wiring layer165B).

Furthermore, D inFIG.153is a plan view of a stacked state of the conductor layer A and the conductor layer C, E inFIG.153is a plan view of a stacked state of the conductor layer B and the conductor layer C, and F inFIG.153is a plan view of a stacked state of the conductor layer A and the conductor layer B.

In the fourteenth configuration example inFIG.153, a portion corresponding to that in the eleventh configuration example illustrated inFIG.148is given the same reference numeral and description of the portion is omitted as appropriate, and description will be given focusing on different portions.

In the fourteenth configuration example, only the configuration of the conductor layer C in A inFIG.153is different from that inFIG.148.

The conductor layer C in A inFIG.153is configured by repeatedly arranging pluralities of rectangular conductors1341A and1341B on the same plane with a predetermined repetition period. The rectangular conductor1341A is, for example, wiring (Vss wiring) connected to the GND or the negative power supply. The rectangular conductor1341B is, for example, wiring (Vdd wiring) connected to the positive power supply.

Specifically, a row in which the rectangular conductor1341A is repeatedly arranged with the gap width GXC in the X direction, and a row in which the rectangular conductor1341B is repeatedly arranged with the gap width GXC in the X direction are alternately and periodically arranged in the Y direction. The rectangular conductors1341A and1341B are repeatedly arranged in the X direction with the conductor period FXC, and are repeatedly arranged in the Y direction with the conductor period FYC. There is a gap with the gap width GYC between the rectangular conductor1341A and the rectangular conductor1341B in the Y direction. The rectangular conductor1341A has the conductor width WXCA in the X direction and the conductor width WYCA in the Y direction, and the rectangular conductor1341B has the conductor width WXCB in the X direction and the conductor width WYCB in the Y direction. Here, the conductor widths WXCA, WYCA, WXCB, and WYCB are the same (the conductor width WXCA=the conductor width WYCA=the conductor width WXCB=the conductor width WYCB).

The fourteenth configuration example inFIG.153is similar to the eleventh configuration example inFIG.148except for the above-described points.

When the conductor layer C in A inFIG.153is viewed in a predetermined plane range (plane region), the current distribution of the rectangular conductor1341A and the current distribution of the rectangular conductor1341B become the same or substantially the same, so that generation of inductive noise can be suppressed.

Since the rectangular conductor1341A and the rectangular conductor1341B repeat the same wiring pattern in the Y direction, the capacitive noise can be completely canceled in the Y direction. The capacitive noise can be significantly improved as the conductor layer C is closer to the wiring layer170.

As illustrated in D and E inFIG.153, the stacked layer of the conductor layers A and C and the stacked layer of the conductor layers B and C have a light-shielding structure, and the light-shielding property is maintained. Thereby, since the light-shielding restrictions of the conductor layers A and B can be significantly alleviated, the conductive area of the conductor layers A and B can be used to the maximum, the wiring resistance can be lowered, and the voltage drop can be further improved. Furthermore, the degree of freedom in layout of the conductor layers A and B can be improved.

By providing the relay conductor1241in the conductor layer A, it becomes possible to connect the rectangular conductor1341B at substantially the shortest distance or a short distance, thereby reducing the voltage drop, energy loss, or inductive noise.

By providing the relay conductor1242in the conductor layer B, it becomes possible to connect the rectangular conductor1341A at substantially the shortest distance or a short distance, thereby reducing the voltage drop, energy loss, or inductive noise.

Modification of Fourteenth Configuration Example of Three-Layer Conductor Layer

FIG.154illustrates a first modification of the fourteenth configuration example of the three-layer conductor layer.

A inFIG.154illustrates the conductor layer C (wiring layer165C), B inFIG.154illustrates the conductor layer A (wiring layer165A), and C inFIG.154illustrates the conductor layer B (wiring layer165B).

Furthermore, D inFIG.154is a plan view of a stacked state of the conductor layer A and the conductor layer C, E inFIG.154is a plan view of a stacked state of the conductor layer B and the conductor layer C, and F inFIG.154is a plan view of a stacked state of the conductor layer A and the conductor layer B.

InFIG.154, a portion corresponding to that in the fourteenth configuration example illustrated inFIG.153is given the same reference numeral and description of the portion is omitted as appropriate, and description will be given focusing on different portions.

In the first modification of the fourteenth configuration example, only the configuration of the conductor layer C in A inFIG.154is different from that inFIG.153, and the configurations of the conductor layers A and B are similar to those inFIG.153.

The conductor layer C in A inFIG.154is common to that inFIG.153in that the pluralities of rectangular conductors1341A and1341B are repeatedly arranged on the same plane with a predetermined repetition period, and is different from that inFIG.153in that the arrangement is shifted in adjacent columns by ¼ of the conductor period FYC in the Y direction. The conductor period FXC, which is the repetition period in the X direction, is in units of two columns.

FIG.155illustrates a second modification of the fourteenth configuration example of the three-layer conductor layer.

A inFIG.155illustrates the conductor layer C (wiring layer165C), B inFIG.155illustrates the conductor layer A (wiring layer165A), and C inFIG.155illustrates the conductor layer B (wiring layer165B).

Furthermore, D inFIG.155is a plan view of a stacked state of the conductor layer A and the conductor layer C, E inFIG.155is a plan view of a stacked state of the conductor layer B and the conductor layer C, and F inFIG.155is a plan view of a stacked state of the conductor layer A and the conductor layer B.

InFIG.155, a portion corresponding to that in the fourteenth configuration example illustrated inFIG.153is given the same reference numeral and description of the portion is omitted as appropriate, and description will be given focusing on different portions.

In the second modification of the fourteenth configuration example, only the configuration of the conductor layer C in A inFIG.155is different from that inFIG.149, and the configurations of the conductor layers A and B are similar to those inFIG.149.

The conductor layer C in A inFIG.155is common to that inFIG.149in that the pluralities of rectangular conductors1341A and1341B are repeatedly arranged on the same plane with a predetermined repetition period, and is different from that inFIG.149in that the arrangement is shifted in adjacent columns by ½ of the conductor period FYC in the Y direction. The conductor period FXC, which is the repetition period in the X direction, is in units of two columns. Note that an amount of shift in the Y direction in adjacent columns of the rectangular conductors1341A and1341B can be designed to an arbitrary value.

In the first modification and the second modification of the fourteenth configuration example inFIGS.154and155, when the conductor layer C is viewed in a predetermined plane range (plane region), the current distribution of the rectangular conductor1341A and the current distribution of the rectangular conductor1341B become the same or substantially the same, so that generation of inductive noise can be suppressed.

Furthermore, in the first modification and the second modification of the fourteenth configuration example, the rectangular conductor1341A and the rectangular conductor1341B repeat the same wiring pattern in the Y direction, and therefore the capacitive noise can be completely canceled in the Y direction. The capacitive noise can be significantly improved as the conductor layer C is closer to the wiring layer170.

Moreover, in the second modification of the fourteenth configuration example inFIG.155, the rectangular conductor1341A and the rectangular conductor1341B repeat the same wiring pattern in the X direction, and therefore the capacitive noise can be completely canceled in the X direction. The capacitive noise can be significantly improved as the conductor layer C is closer to the wiring layer170.

In the first modification of the fourteenth configuration example inFIG.154, the light-shielding property is maintained in a fixed range in the stacked layer of the conductor layers A and B, the stacked layer of the conductor layers A and C, and the stacked layer of the conductor layers B and C. Thereby, since the light-shielding restrictions of the conductor layers A and B can be slightly alleviated, the conductive area of the conductor layers A and B can be used to the maximum, the wiring resistance can be lowered, and the voltage drop can be further improved. Furthermore, the degree of freedom in layout of the conductor layers A and B can be improved.

In the second modification of the fourteenth configuration example inFIG.155, the stacked layer of the conductor layers A and C and the stacked layer of the conductor layers B and C have a light-shielding structure, and the light-shielding property is maintained. Thereby, since the light-shielding restrictions of the conductor layers A and B can be significantly alleviated, the conductive area of the conductor layers A and B can be used to the maximum, the wiring resistance can be lowered, and the voltage drop can be further improved. Furthermore, the degree of freedom in layout of the conductor layers A and B can be improved.

By providing the relay conductor1241in the conductor layer A, it becomes possible to connect the rectangular conductor1341B at substantially the shortest distance or a short distance, thereby reducing the voltage drop, energy loss, or inductive noise.

By providing the relay conductor1242in the conductor layer B, it becomes possible to connect the rectangular conductor1341A at substantially the shortest distance or a short distance, thereby reducing the voltage drop, energy loss, or inductive noise.

Other Modifications in Fourteenth Configuration Example of Three-Layer Conductor Layer

Hereinafter, other modifications of the fourteenth configuration example of the three-layer conductor layer illustrated inFIG.153will be described with reference toFIGS.156to163.

Note that, in the modifications of the fourteenth configuration example, only the configuration of the conductor layer C will be illustrated inFIGS.156and163because only the configuration of the conductor layer C is changed similarly to the first and second modifications inFIGS.154and155. Furthermore, inFIGS.156to163, the configuration of the conductor layer C will be described by being compared with the conductor layer C of the fourteenth configuration example illustrated in A inFIG.153.

A inFIG.156illustrates the conductor layer C of a third modification of the fourteenth configuration example of the three-layer conductor layer.

The conductor layer C in A inFIG.156is configured by repeatedly arranging pluralities of rectangular conductors1342A and1342B on the same plane with a predetermined repetition period. The rectangular conductor1342A is, for example, wiring (Vss wiring) connected to the GND or the negative power supply. The rectangular conductor1342B is, for example, a wiring (Vdd wiring) connected to the positive power supply.

The difference of the conductor layer C in A inFIG.156from the conductor layer C in A inFIG.153is the conductor sizes of the rectangular conductors1342A and1342B, that is, the conductor widths WXCA, WYCA, WXCB, and WYCB. Note that the conductor widths WXCA, WYCA, WXCB, and WYCB are the same (the conductor width WXCA=the conductor width WYCA=the conductor width WXCB=the conductor width WYCB).

The capacitive noise can be completely canceled in the Y direction in the conductor layer C in A inFIG.156. The capacitive noise can be significantly improved as the conductor layer C is closer to the wiring layer170.

Furthermore, the wiring resistance can be further reduced by making the conductor sizes of the rectangular conductors1342A and1342B larger than those of the fourteenth configuration example illustrated in A inFIG.153.

B inFIG.156illustrates the conductor layer C of a fourth modification of the fourteenth configuration example of the three-layer conductor layer.

The conductor layer C in B inFIG.156is common to that in A inFIG.156in that the pluralities of rectangular conductors1342A and1342B are repeatedly arranged on the same plane with a predetermined repetition period, and is different from that in A inFIG.156in that the arrangement is shifted in adjacent columns by ¼ of the conductor period FYC in the Y direction. The conductor period FXC, which is the repetition period in the X direction, is in units of two columns.

The capacitive noise can be completely canceled in the Y direction in the conductor layer C in B inFIG.156. The capacitive noise can be significantly improved as the conductor layer C is closer to the wiring layer170.

C inFIG.156illustrates the conductor layer C of a fifth modification of the fourteenth configuration example of the three-layer conductor layer.

The conductor layer C in C inFIG.156is common to that in A inFIG.156in that the pluralities of rectangular conductors1342A and1342B are repeatedly arranged on the same plane with a predetermined repetition period, and is different from that in A inFIG.156in that the arrangement is shifted in adjacent columns by ½ of the conductor period FYC in the Y direction. It can be said that the adjacent rows are shifted in arrangement by ½ of the conductor period FXC in the X direction. The conductor period FXC in the X direction is in units of two columns, and the conductor period FYC in the Y direction is in units of two rows. Note that the amount of shift in the Y direction in adjacent columns of the rectangular conductors1342A and1342B can be designed to an arbitrary value.

The capacitive noise can be completely canceled in the Y direction in the conductor layer C in C inFIG.156. The capacitive noise can be significantly improved as the conductor layer C is closer to the wiring layer170.

Moreover, the capacitive noise can be completely canceled in the X direction in the conductor layer C in C inFIG.156. The capacitive noise can be significantly improved as the conductor layer C is closer to the wiring layer170.

A inFIG.157illustrates the conductor layer C of a sixth modification of the fourteenth configuration example of the three-layer conductor layer.

The conductor layer C in A inFIG.157is configured by repeatedly arranging pluralities of rectangular conductors1343A and1343B on the same plane with a predetermined repetition period. The rectangular conductor1343A is, for example, wiring (Vss wiring) connected to the GND or the negative power supply. The rectangular conductor1343B is, for example, wiring (Vdd wiring) connected to the positive power supply.

The difference of the conductor layer C in A inFIG.157from the conductor layer C in A inFIG.153is the conductor sizes of the rectangular conductors1343A and1343B, specifically, the conductor widths WXCA and WXCB. Note that the rectangular conductors1343A and1343B are rectangular, and the conductor width WXCA>the conductor width WYCA and the conductor width WXCB>the conductor width WYCB. Furthermore, the conductor width WXCA and the conductor width WXCB are the same, and the conductor width WYCA and the conductor width WYCB are the same (the conductor width WXCA=the conductor width WXCB, and the conductor width WYCA=the conductor width WYCB).

The capacitive noise can be completely canceled in the Y direction in the conductor layer C in A inFIG.157. The capacitive noise can be significantly improved as the conductor layer C is closer to the wiring layer170.

B inFIG.157illustrates the conductor layer C of a seventh modification of the fourteenth configuration example of the three-layer conductor layer.

The conductor layer C in B inFIG.157is common to that in A inFIG.157in that the pluralities of rectangular conductors1343A and1343B are repeatedly arranged on the same plane with a predetermined repetition period, and is different from that in A inFIG.157in that the arrangement is shifted in adjacent rows by ½ of the conductor period FXC in the X direction. The conductor period FYC, which is the repetition period in the Y direction, is in units of two rows. Note that an amount of shift in the X direction in adjacent rows of the rectangular conductors1343A and1343B can be designed to an arbitrary value.

In the conductor layer C in B inFIG.157, the rectangular conductor1343A and the rectangular conductor1343B do not have repetition of the same wiring pattern in the Y direction. Therefore, there is an X position in which the capacitive noise cannot be completely canceled in the Y direction.

Therefore, in the case of shifting the rows by ½ of the conductor period FXC in the X direction, the conductor layer C can be configured as in the conductor layer C in C inFIG.157.

C inFIG.157illustrates the conductor layer C of an eighth modification of the fourteenth configuration example of the three-layer conductor layer.

The conductor layer C in C inFIG.157is configured by shifting the rectangular conductors1343A and1343B adjacent in the Y direction by ½ of the conductor period FXC in the X direction in units of two rows, and repeatedly arranging the rectangular conductors1343A and1343B on the same plane with a predetermined repetition period.

The capacitive noise can be completely canceled in the Y direction in the conductor layer C in C inFIG.157. The capacitive noise can be significantly improved as the conductor layer C is closer to the wiring layer170.

Note that the amount of shift in the X direction in units of adjacent two rows of the rectangular conductors1343A and1343B can be designed to an arbitrary value. Furthermore, shift of the rectangular conductors1343A and1343B in the X direction in units of two rows may be performed by shifting two non-adjacent rows of rectangular conductors instead of two adjacent rows of rectangular conductors. Furthermore, the shift of the rectangular conductors1343A and1343B in the X direction in units of two rows need not be performed in units of two rows because the capacitive noise can be completely canceled in the Y direction if the sum of the conductor widths in the Y direction of the rectangular conductors1343A and the sum of the conductor widths in the Y direction of the rectangular conductors1343B in a predetermined plane range (plane region) are the same. In other words, the rectangular conductors1343A and1343B may be shifted in the X direction with an amount of shift designed to an arbitrary value in units of two or more rows regardless of whether the rectangular conductors are adjacent or not, and the shift is suitable but not limited to the case where the sum of the conductor widths in the Y direction of the rectangular conductors1343A and the sum of the conductor widths in the Y direction of the rectangular conductors1343B in a predetermined plane range (plane region) are the same or substantially the same.

A inFIG.158illustrates the conductor layer C of a ninth modification of the fourteenth configuration example of the three-layer conductor layer.

The conductor layer C in A inFIG.158is configured by repeatedly arranging pluralities of rectangular conductors1344A and1344B on the same plane with a predetermined repetition period. The rectangular conductor1344A is, for example, wiring (Vss wiring) connected to the GND or the negative power supply. The rectangular conductor1344B is, for example, a wiring (Vdd wiring) connected to the positive power supply.

The difference of the conductor layer C in A inFIG.158from the conductor layer C in A inFIG.157is the conductor sizes of the rectangular conductors1344A and1344B, specifically, the conductor widths WXCA and WXCB. The conductor widths WXCA and WXCB of the rectangular conductors1344A and1344B in A inFIG.158are larger than the conductor widths WXCA and WXCB of the rectangular conductors1343A and1343B in A inFIG.157.

Note that the rectangular conductors1344A and1344B are rectangular, and the conductor width WXCA>the conductor width WYCA and the conductor width WXCB>the conductor width WYCB. Furthermore, the conductor width WXCA and the conductor width WXCB are the same, and the conductor width WYCA and the conductor width WYCB are the same (the conductor width WXCA=the conductor width WXCB, and the conductor width WYCA=the conductor width WYCB).

The capacitive noise can be completely canceled in the Y direction in the conductor layer C in A inFIG.158. The capacitive noise can be significantly improved as the conductor layer C is closer to the wiring layer170.

B inFIG.158illustrates the conductor layer C of a tenth modification of the fourteenth configuration example of the three-layer conductor layer.

The conductor layer C in B inFIG.158is common to that in A inFIG.158in that the pluralities of rectangular conductors1344A and1344B are repeatedly arranged on the same plane with a predetermined repetition period, and is different from that in A inFIG.158in that the arrangement is shifted in adjacent rows by ⅓ of the conductor period FXC in the X direction. The conductor period FYC, which is the repetition period in the Y direction, is in units of six rows.

The capacitive noise can be completely canceled in the Y direction in the conductor layer C in B inFIG.158. The capacitive noise can be significantly improved as the conductor layer C is closer to the wiring layer170.

C inFIG.158illustrates the conductor layer C of an eleventh modification of the fourteenth configuration example of the three-layer conductor layer.

The conductor layer C in C inFIG.158is configured by shifting the rectangular conductors1344A and1344B adjacent in the Y direction by ⅓ of the conductor period FXC in the X direction in units of two rows, and repeatedly arranging the rectangular conductors1344A and1344B on the same plane with a predetermined repetition period.

The capacitive noise can be completely canceled in the Y direction in the conductor layer C in C inFIG.158. The capacitive noise can be significantly improved as the conductor layer C is closer to the wiring layer170.

A inFIG.159illustrates the conductor layer C of a twelfth modification of the fourteenth configuration example of the three-layer conductor layer.

The conductor layer C in A inFIG.159is configured by repeatedly arranging pluralities of rectangular conductors1341A and1341B on the same plane with a predetermined repetition period.

The difference of the conductor layer C in A inFIG.159from the conductor layer C in A inFIG.153is the arrangement direction of the rectangular conductors1341A and1341B. Specifically, in the conductor layer C in A inFIG.153, the rectangular conductors1341A and1341B are repeatedly arranged in the X direction with the conductor period FXC, and the rectangular conductors1341A and1341B are alternately and periodically arranged in the Y direction. In contrast, in the conductor layer C in A inFIG.159, the rectangular conductors1341A and1341B are repeatedly arranged in the Y direction with the conductor period FYC, and the rectangular conductors1341A and1341B are alternately and periodically arranged in the X direction.

The capacitive noise can be completely canceled in the X direction in the conductor layer C in A inFIG.159. The capacitive noise can be significantly improved as the conductor layer C is closer to the wiring layer170.

B inFIG.159illustrates the conductor layer C of a thirteenth modification of the fourteenth configuration example of the three-layer conductor layer.

The conductor layer C in B inFIG.159is configured by repeatedly arranging pluralities of rectangular conductors1361A and1361B on the same plane with a predetermined repetition period. The rectangular conductor1361A is, for example, wiring (Vss wiring) connected to the GND or the negative power supply. The rectangular conductor1361B is, for example, wiring (Vdd wiring) connected to the positive power supply.

The difference of the conductor layer C in B inFIG.159from the conductor layer C in A inFIG.159is the conductor sizes of the rectangular conductors1361A and1361B, specifically, the conductor widths WYCA and WYCB. Note that the rectangular conductors1361A and1361B are rectangular, and the conductor width WXCA<the conductor width WYCA, and the conductor width WXCB<the conductor width WYCB. Furthermore, the conductor width WXCA and the conductor width WXCB are the same, and the conductor width WYCA and the conductor width WYCB are the same (the conductor width WXCA=the conductor width WXCB, and the conductor width WYCA=the conductor width WYCB).

The capacitive noise can be completely canceled in the X direction in the conductor layer C in B inFIG.159. The capacitive noise can be significantly improved as the conductor layer C is closer to the wiring layer170.

Note that although not illustrated, it is also possible that the rectangular conductors1361A and1361B are shifted by ½ of the conductor period FYC in the Y direction in adjacent columns and repeatedly arranged on the same plane with a predetermined repetition period, or are shifted by ⅓ of the conductor period FYC in the Y direction in adjacent columns. Furthermore, the amount of shift in the Y direction in adjacent columns of the rectangular conductors1361A and1361B can be designed to an arbitrary value. Furthermore, the rectangular conductors1361A and1361B may be shifted in the Y direction with an amount of shift designed to an arbitrary value in units of two or more columns regardless of whether the rectangular conductors are adjacent or not, and the shift is suitable but not limited to the case where the sum of the conductor widths in the X direction of the rectangular conductors1361A and the sum of the conductor widths in the X direction of the rectangular conductors1361B in a predetermined plane range (plane region) are the same or substantially the same.

C inFIG.159illustrates the conductor layer C of a fourteenth modification of the fourteenth configuration example of the three-layer conductor layer.

The conductor layer C in C inFIG.159is configured by shifting the rectangular conductors1361A and1361B adjacent in the X direction by ½ of the conductor period FYC in the Y direction in units of two columns, and repeatedly arranging the rectangular conductors1361A and1361B on the same plane with a predetermined repetition period.

The capacitive noise can be completely canceled in the X direction in the conductor layer C in C inFIG.159. The capacitive noise can be significantly improved as the conductor layer C is closer to the wiring layer170.

A inFIG.160illustrates the conductor layer C of a fifteenth modification of the fourteenth configuration example of the three-layer conductor layer.

The conductor layer C in A inFIG.160is configured by arranging the two rectangular conductors1341A and two rectangular conductors1341B in the X direction and the Y direction on the same plane with a predetermined repetition period. The gap between adjacent rectangular conductors1341A, the gap between adjacent rectangular conductors1341B, and the gap between adjacent rectangular conductors1341A and1341B have the gap width of GXC in the X direction and the gap width GYC in the Y direction. The two rectangular conductors1341A and the two rectangular conductors1341B are repeatedly arranged in the X direction with the conductor period FXC, and are repeatedly arranged in the Y direction with the conductor period FYC.

B inFIG.160illustrates the conductor layer C of a sixteenth modification of the fourteenth configuration example of the three-layer conductor layer.

The conductor layer C in B inFIG.160is common to that in A inFIG.157in that the pluralities of rectangular conductors1343A and1343B are repeatedly arranged on the same plane with a predetermined repetition period, and is different from that in A inFIG.157in that the arrangement is shifted in adjacent columns by ½ of the conductor period FYC in the Y direction. It can be said that the arrangement in the adjacent rows is shifted by ½ of the conductor period FXC in the X direction. The conductor period FXC in the X direction is in units of two columns, and the conductor period FYC in the Y direction is in units of two rows.

C inFIG.160illustrates the conductor layer C of a seventeenth modification of the fourteenth configuration example of the three-layer conductor layer.

The conductor layer C in C inFIG.160is common to that in A inFIG.158in that the pluralities of rectangular conductors1344A and1344B are repeatedly arranged on the same plane with a predetermined repetition period, and is different from that in A inFIG.158in that the arrangement is shifted in adjacent columns by ½ of the conductor period FYC in the Y direction. It can be said that the arrangement in the adjacent rows is shifted by ½ of the conductor period FXC in the X direction. The conductor period FXC in the X direction is in units of two columns, and the conductor period FYC in the Y direction is in units of two rows. The conductor layer C in B inFIG.160and the conductor layer C in C inFIG.160differ only in the conductor widths WXCA and WXCB in the X direction.

In the conductor layers C in A to C inFIG.160, the capacitive noise can be completely canceled both in the X direction and in the Y direction. The capacitive noise can be significantly improved as the conductor layer C is closer to the wiring layer170.

A inFIG.161illustrates the conductor layer C of an eighteenth modification of the fourteenth configuration example of the three-layer conductor layer.

The conductor layer C in A inFIG.161is common to that in A inFIG.156in that the two rectangular conductors1341A and the two rectangular conductors1341B are repeatedly arranged on the same plane in the X direction and the Y direction with a predetermined repetition period, and is different from that in A inFIG.156in that the arrangement is shifted by ¼ of the conductor period FYC in the Y direction in units of two columns.

B inFIG.161illustrates the conductor layer C of a nineteenth modification of the fourteenth configuration example of the three-layer conductor layer.

The conductor layer C in B inFIG.161is common to that in A inFIG.157in that the pluralities of rectangular conductors1343A and1343B are repeatedly arranged on the same plane with a predetermined repetition period, and is different from that in A inFIG.157in that the arrangement is shifted in adjacent columns by ¼ of the conductor period FYC in the Y direction.

C inFIG.161illustrates the conductor layer C of a twentieth modification of the fourteenth configuration example of the three-layer conductor layer.

The conductor layer C in C inFIG.161is configured by arranging conductors1381A and1381B in the Y direction on the same plane with a predetermined repetition period. The conductor1381A is, for example, wiring (Vss wiring) connected to the GND or the negative power supply. The conductor1381B is, for example, wiring (Vdd wiring) connected to the positive power supply.

The conductor1381A has a shape in which all the rectangular conductors1343A arranged in the X direction in B inFIG.161are connected by the shortest path. The conductor1381B has a shape in which all the rectangular conductors1343B arranged in the X direction in B inFIG.161are connected by the shortest path. The gap width GXC and the gap width GYC in C inFIG.161correspond to the minimum widths in the X direction and the Y direction between adjacent conductors. Note that the conductor1381A and the conductor1381B do not need to have the shape connecting all the rectangular conductors arranged in the X direction in B inFIG.161by the shortest path, and may have a meander shape or a meandering shape, for example.

In the conductor layers C in A to C inFIG.161, the capacitive noise can be completely canceled in the Y direction and partially canceled in the X direction. The capacitive noise can be significantly improved as the conductor layer C is closer to the wiring layer170.

A inFIG.162illustrates the conductor layer C of a twenty-first modification of the fourteenth configuration example of the three-layer conductor layer.

The conductor layer C in A inFIG.162is common to that in A inFIG.153in that the pluralities of rectangular conductors1341A and1341B are repeatedly arranged on the same plane with a predetermined repetition period, and is different from that in A inFIG.153in that the arrangement is shifted in adjacent columns by ¼ of the conductor period FYC in the Y direction.

B inFIG.162illustrates the conductor layer C of a twenty-second modification of the fourteenth configuration example of the three-layer conductor layer.

The conductor layer C in B inFIG.162is configured by periodically arranging conductors1382A and1382B on the same plane with the conductor period FXC in the X direction and the conductor period FYC in the Y direction. The conductor1382A is, for example, wiring (Vss wiring) connected to the GND or the negative power supply. The conductor1382B is, for example, wiring (Vdd wiring) connected to the positive power supply. The conductor1382A has the conductor width WXCA in the X direction and the conductor width WYCA in the Y direction, and the conductor1382B has the conductor width WXCB in the X direction and the conductor width WYCB in the Y direction. The gap width GXC and the gap width GYC in B inFIG.162correspond to the minimum widths in the X direction and the Y direction between adjacent conductors.

The conductor1382A has a shape in which two rectangular conductors1341A arranged in the X direction in A inFIG.162are connected by the shortest path. The conductor1382B has a shape in which two rectangular conductors1341B arranged in the X direction in A inFIG.162are connected by the shortest path. Note that the conductor1382A and the conductor1382B do not need to have the shape connected by the shortest path, and may be formed by electrically connecting two or more rectangular conductors arranged in the X direction in A inFIG.162.

C inFIG.162illustrates the conductor layer C of a twenty-third modification of the fourteenth configuration example of the three-layer conductor layer.

The conductor layer C in C inFIG.162is configured by arranging conductors1383A and1383B on the same plane with a predetermined repetition period in the Y direction. The conductor1383A is, for example, wiring (Vss wiring) connected to the GND or the negative power supply. The conductor1383B is, for example, wiring (Vdd wiring) connected to the positive power supply. The conductor1383A has the conductor width WYCA in the Y direction, and the conductor1382B has the conductor width WYCB in the Y direction. The gap width GXC and the gap width GYC in C inFIG.162correspond to the minimum widths in the X direction and the Y direction between adjacent conductors.

The conductor1383A has a shape in which all the rectangular conductors1341A arranged in the X direction in A inFIG.162are connected by the shortest path. The conductor1383B has a shape in which all the rectangular conductors1341B arranged in the X direction in A inFIG.162are connected by the shortest path. Note that the conductors1383A and1383B do not need to have the shape connecting all the rectangular conductors arranged in the X direction in A inFIG.162by the shortest path, and may have a meander shape or a meandering shape, for example.

In the conductor layers C in A to C inFIG.162, the capacitive noise can be completely canceled in the Y direction and partially canceled in the X direction. The capacitive noise can be significantly improved as the conductor layer C is closer to the wiring layer170.

A inFIG.163illustrates the conductor layer C of a twenty-fourth modification of the fourteenth configuration example of the three-layer conductor layer.

The conductor layer C in A inFIG.163is common to that in A inFIG.153in that the rectangular conductors1341A and1341B are repeatedly arranged on the same plane with a predetermined repetition period, and is different from that in A inFIG.153in that a region in which the arrangement is shifted in adjacent columns by ¼ of the conductor period FYC in the Y direction, and a region in which the arrangement is not shifted coexist. The conductor layer C in A inFIG.163has a configuration in which the two rectangular conductors1341A and1341B, which are not shifted in the Y direction, are folded back and repeatedly arranged in the X direction with the conductor period FXC with reference to the center in the X direction.

B inFIG.163illustrates the conductor layer C of a twenty-fifth modification of the fourteenth configuration example of the three-layer conductor layer.

The conductor layer C in B inFIG.163is configured by arranging rectangular conductors1371A and1371B and repeatedly arranging conductors1382A and1382B on the same plane with a predetermined repetition period.

The conductor layer C in B inFIG.163has a configuration in which the conductors1382A and1382B are folded back at the center in the X direction of the rectangular conductors1371A and1371B, and the conductors1382A and1382B are repeatedly arranged in the X direction with the conductor period FXC.

C inFIG.163illustrates the conductor layer C of a twenty-sixth modification of the fourteenth configuration example of the three-layer conductor layer.

The conductor layer C in C inFIG.163is configured by arranging conductors1391A and1391B on the same plane in the Y direction with a predetermined repetition period. The conductor1391A is, for example, wiring (Vss wiring) connected to the GND or the negative power supply. The conductor1391B is, for example, wiring (Vdd wiring) connected to the positive power supply. The conductor1391A has the conductor width WYCA in the Y direction, and the conductor1391B has the conductor width WYCB in the Y direction. The gap width GXC and the gap width GYC in C inFIG.163correspond to the minimum widths in the X direction and the Y direction between adjacent conductors.

The conductor1391A has a shape in which all the rectangular conductors1371A and the conductors1382A arranged in the X direction in B inFIG.163are connected by the shortest path. The conductor1391B has a shape in which all the rectangular conductors1371B and the conductors1382B arranged in the X direction in B inFIG.163are connected by the shortest path. Note that the conductor1391A and the conductor1391B do not need to have the shape connecting all the rectangular conductors arranged in the X direction in B inFIG.163by the shortest path, and may have a meander shape or a meandering shape, for example.

The conductor layer C in C inFIG.163has a configuration in which the conductor1391A and the conductor1391B are folded back and repeatedly arranged in the X direction with the conductor period FXC in the same region units as the conductor layer C in B inFIG.163.

The conductor layers C in A to C inFIG.163have a mirror-symmetrical conductor arrangement in the X direction.

In the conductor layers C in A to C inFIG.163, the capacitive noise can be completely canceled in the Y direction and partially canceled in the X direction. The capacitive noise can be significantly improved as the conductor layer C is closer to the wiring layer170. Although some specific examples have been described, the first to fourteenth configuration examples or the modifications thereof (FIGS.122to163) are particularly suitable for the stacking order in which the three layers of the conductor layers A to C can be electrically connected via the conductor via (VIA) or the like extending in the Z direction. Specifically, the configuration examples and the modifications thereof illustrated inFIGS.122to127,134,148,149, and152to163are suitable for the stacking order illustrated in B inFIG.120. Furthermore, the configuration examples and the modifications thereof illustrated inFIG.150are suitable for the stacking orders illustrated in A and B inFIG.120. Furthermore, the configuration examples and modifications thereof illustrated inFIGS.129,131,133,135to138,140,142to144,146,147, and151are suitable for the stacking orders illustrated in B and C inFIG.120. Furthermore, the configuration examples and modifications thereof illustrated inFIGS.128,130,132,139,141, and145are suitable for the stacking orders illustrated in A to C inFIG.120.

Other Modifications of Three-Layer Conductor Layer

In each of the above configuration examples, the conductor described as the wiring (Vss wiring) connected to the GND or the negative power supply, for example, may be the wiring (Vdd wiring) connected to the positive power supply, for example. The conductor described as the wiring (Vdd wiring) connected to the positive power supply, for example, may be the wiring (Vss wiring) connected to the GND or the negative power supply, for example. The voltage to be Vdd or Vss may be the GND and a power supply, or may be two types of power supplies having different voltages. The voltage to be Vdd or Vss should have two different polarities, but this is not the case. The number and the total area of the conductor vias (VIAs) extending in the Z direction and connecting the conductor layers A, B, and C are desirably the same between Vdd and Vss in a predetermined plane range (plane region), but this is not the case. When thinning out the relay conductors arranged in the gaps, a method other than the above-described method, for example, randomly thinning out the relay conductors may be adopted.

The conductor layer C is a conductor layer having a low sheet resistance in which the current easily flows, but may be a conductor layer having a high sheet resistance in which the current less easily flow. The conductor layer C is desirably, but is not limited to, not the conductor layer in which the current most uneasily flows among circuit boards, semiconductor substrates, and electronic devices. The conductor layer C is desirably, but is not limited to, the conductor layer in which the current most easily flows among circuit boards, semiconductor substrates, and electronic devices. The conductor layer C is desirably, but is not limited to, the conductor layer in which the current more easily flows than at least one of the conductor layer A or the conductor layer B. The conductor layer C is desirably, but is not limited to, the conductor layer in which the current easily flows next to the conductor layer A among circuit boards, semiconductor substrates, and electronic devices. The conductor layer C is desirably, but is not limited to, the conductor layer in which the current easily flows next to the conductor layer B among circuit boards, semiconductor substrates, and electronic devices. For example, the conductor layer C may be the conductor layer in which the current most uneasily flows in the first semiconductor substrate101or the second semiconductor substrate102. For example, the conductor layer C may be the conductor layer in which the current most easily flows in the first semiconductor substrate101or the second semiconductor substrate102. For example, the conductor layer C may be the conductor layer in which the current second-most easily flows in the first semiconductor substrate101or the second semiconductor substrate102. For example, the conductor layer C may be the conductor layer in which the current third most easily flows in the first semiconductor substrate101or the second semiconductor substrate102. For example, the conductor layer C may be the conductor layer in which the current easily flows next to the conductor layer A in the first semiconductor substrate101or the second semiconductor substrate102. For example, the conductor layer C may be the conductor layer in which the current easily flows next to the conductor layer B in the first semiconductor substrate101or the second semiconductor substrate102.

Note that the above-described conductor layer in which the current easily flows among circuit boards, semiconductor substrates, and electronic devices may be considered to be any of a conductor layer in which the current easily flows among the circuit boards, a conductor layer in which the current easily flows among the semiconductor substrates, or a conductor layer in which the current easily flows among the electronic devices. Note that the above-described conductor layer in which the current less easily flows among circuit boards, semiconductor substrates, and electronic devices may be considered to be any of a conductor layer in which the current less easily flows among the circuit boards, a conductor layer in which the current less easily flows among the semiconductor substrates, or a conductor layer in which the current less easily flows among the electronic devices. Furthermore, even if the conductor layer in which the current easily flows is a conductor layer having a low sheet resistance, and the conductor layer in which the current less easily flows is a conductor layer having a high sheet resistance, thereby can be replaced with each other.

As the conductor material used for the conductor layer C, a metal such as copper, aluminum, tungsten, chromium, nickel, tantalum, molybdenum, titanium, gold, silver, or iron, or a mixture, a compound, or an alloy containing at least one of the aforementioned metals, is mainly used. Furthermore, a semiconductor such as silicon, germanium, a compound semiconductor, or an organic semiconductor may be included. Moreover, an insulator such as cotton, paper, polyethylene, polyvinyl chloride, natural rubber, polyester, epoxy resin, melamine resin, phenol resin, polyurethane, synthetic resin, mica, asbestos, glass fiber, or porcelain may be included. Furthermore, the conductor layer C may be an uppermost layer metal or a lowest layer metal, that is, an uppermost layer or a lowest layer conductor layer, or may be a conductor layer used for similar metal bonding such as Cu—Cu bonding, Au—Au bonding, or Al—Al bonding, or dissimilar metal bonding such as Cu—Au bonding, Cu—Al bonding, or Au—Al bonding.

The plane arrangement of each of the conductor layers A to C may be reversed in the X direction or in the Y direction. Furthermore, the plane arrangement may be rotated clockwise by a predetermined angle (for example, 90 degrees) or counterclockwise by a predetermined angle (for example, −90 degrees). Furthermore, some of the above-described configuration examples have been described using the example in which all the conductor periods, conductor widths, and gap widths are uniform. However, this is not the case. For example, the conductor period, the conductor width, and the gap width may be non-uniform, or the conductor period, the conductor width, and the gap width may be modulated depending on a position. Furthermore, some of the above-described configuration examples have been described using the example in which the conductor periods, conductor widths, gap widths, wiring shapes, wiring positions, the numbers of wirings, and the like are substantially the same in the Vdd wiring and the Vss wiring. However, this is not the case. For example, the Vdd wiring and the Vss wiring may have different conductor periods, different conductor widths, different gap widths, different wiring shapes, or different wiring positions. The wiring position may be shifted or misaligned, and the number of wirings may be different.

The technology according to the present disclosure is not limited to the description of the above embodiments and its modifications or applications, and various modifications can be carried out. The above-described embodiments and the modifications or applications thereof may be omitted in part, the part or the whole may be changed, the part or the whole may be altered, the part may be replaced with another configuration element, or another configuration element may be added to the part or the whole. Furthermore, a part or the whole of the configuration elements in the above-described embodiments and the modifications or applications thereof may be divided into a plurality of elements, the part or the whole may be separated into a plurality of elements, or at least some of the plurality of divided or separated configuration elements may have different functions or characteristics. Moreover, at least some of the configuration elements in the above-described embodiments and the modifications or applications thereof may be combined to form a different embodiment. Moreover, at least some of the configuration elements in the above-described embodiments and the modifications or applications thereof may be moved to form a different embodiment. Moreover, a coupling element or a relay element may be added to at least some of the configuration elements in the above-described embodiments and the modifications or applications thereof to form a different embodiment. Moreover, a switching element or a switching function may be added to at least some of the configuration elements in the above-described embodiments and the modifications or applications thereof to form a different embodiment.

In the solid-state imaging device100of the present embodiment, the conductors forming the conductor layers A and B, which can be the Aggressor conductor loops, are the Vdd wiring or the Vss wiring. That is, the currents flow in the directions opposite to each other in at least some regions in the conductor layers A and B. When the current flows downward in the figure in the conductor layer A, the current flows upward in the figure in the conductor layer B. Note that the magnitudes of the currents are desirably the same as each other. Note that the description has been given using the example in which the conductors forming the conductor layers A and B are configured in the second semiconductor substrate, but this is not the case. For example, the conductors may be configured in the first semiconductor substrate, or some or all of the conductors may be configured in somewhere other than the second semiconductor substrate.

As the signal flowing through the conductor layers A and B, any signal other than Vdd and Vss may flow as long as the signal is a differential signal whose current direction changes in the time direction. That is, it is sufficient that a signal with a current I that changes according to a time t (a minute current change in a minute time dt is dI) flows through the conductor layers A and B. Note that even if a DC current is basically flowing through the conductor layers A and B, if there is a rising current, a time transition of the current, a falling current, or the like, the current I changes according to the time t.

For example, the magnitude of the current flowing through the conductor layer A and the magnitude of the current flowing through the conductor layer B do not have to be the same. On the contrary, the magnitude of the current flowing through the conductor layer A and the magnitude of the current flowing through the conductor layer B may be made the same (currents that change with time flow through the conductor layers A and B at substantially the same timing). In general, the magnitude of the induced electromotive force generated in the Victim conductor loop can be more suppressed in the case where the currents that change with time flow through the conductor layers A and B at substantially the same timing than the case where the magnitude of the current flowing through the conductor layer A and the magnitude of the current flowing through the conductor layer B are not the same. Meanwhile, the signals flowing through the conductor layers A and B do not have to be differential signals. For example, both may be Vdd wiring, both Vss wiring, both GND wiring, the same type of signal line, different types of signal lines, or the like. Furthermore, the conductors forming the conductor layers A and B may be conductors that are not connected to a power supply or a signal source. In these cases, the effect of suppressing the inductive noise is reduced, but other effects of the invention can be obtained.

Furthermore, a frequency signal having a predetermined frequency, such as a clock signal, may flow through the conductor layers A and B. Furthermore, for example, an AC power supply current may flow through the conductor layers A and B. Furthermore, for example, the same frequency signal may flow through the conductor layers A and B. Furthermore, signals including a plurality of frequency components may flow through the conductor layers A and B. Meanwhile, a DC signal with the current I that does not change at all may flow according to the time t. In this case, the effect of suppressing the inductive noise cannot be obtained, but other effects of the invention can be obtained. Meanwhile, the signal may be caused not to flow. In this case, the effects of inductive noise suppression, capacitive noise suppression, and voltage drop (IR-Drop) reduction cannot be obtained, but other effects of the invention can be obtained.

14. Shift Configuration Example of Reticulated Conductor

First Shift Configuration Example of Reticulated Conductor

By the way, in the above-described conductor layers A and B, some configuration examples adopting the reticulated conductors have been proposed.

For example, in the second configuration example illustrated inFIG.15, the conductor layer A including the reticulated conductor216and the conductor layer B including the reticulated conductor217have been described. In the fourth configuration example illustrated inFIG.25, the conductor layer A including the reticulated conductor231and the conductor layer B including the reticulated conductor232have been described.

Furthermore, the configuration examples in which the relay conductor is arranged within the gap region of the reticulated conductor have been proposed.

For example, in the eighth configuration example illustrated inFIG.32, the conductor layer A including the reticulated conductor271and the conductor layer B including the reticulated conductor272and the relay conductor302have been described. The relay conductor302is a non-reticulated conductor arranged in the gap region that is not the conductor of the reticulated conductor272. The number of relay conductors arranged in the gap region of the reticulated conductor is not limited to one. For example, a plurality of relay conductors306of the conductor layer B inFIG.40may be arranged.

Moreover, for example, as in the fourth configuration example of the three-layer conductor layer illustrated inFIG.128, each of the conductor layer A and the conductor layer B has the relay conductor.

The wiring pattern in which the reticulated conductor is repeated to the same position in the XY direction has a disadvantage in terms of capacitive noise.

Specifically, for example, as illustrated on the left side inFIG.164, there is a conductor layer1511including a reticulated conductor1501and a relay conductor1502arranged in the gap region of the reticulated conductor1501. The reticulated conductor1501is, for example, wiring (Vss wiring) connected to the GND or the negative power supply. The relay conductor1502is, for example, wiring (Vdd wiring) connected to the positive power supply.

Wiring1512, which constitutes a part of the Victim conductor loop, is arranged in an upper or lower layer of the conductor layer1511including the reticulated conductor1501and the relay conductor1502. The wiring1512corresponds to, for example, the signal line132and the control line133of the solid-state imaging device100.

The signal line132is wired longer in the Y direction than in the X direction, and a plurality of signal lines132is periodically arranged in the pixel array121with a predetermined periodic width (for example, in pixel units). When the signal line132is selected by the select transistor145of each pixel131, a signal is transmitted. The control line133is wired longer in the X direction than in the Y direction, and a plurality of control lines133is periodically arranged in the pixel array121with a predetermined periodic width (for example, in pixel units). When the control line133is selected by the vertical scanning unit123, a signal is transmitted.

When the Vdd wiring and the Vss wiring are integrated with a part where the reticulated conductor1501and the relay conductor1502of the conductor layer1511affect a linear conductor that is long in the Y direction, like the wiring1512, that is, linearly in the Y direction to overlap with the wiring1512, the total charge amount by Vdd and the total charge amount by Vss are significantly different as illustrated on the right side inFIG.164. The difference between the positive capacitance due to the Vdd wiring and the negative capacitance due to the Vss wiring generates the capacitive noise.

The capacitive noise refers to, as described with reference toFIG.62and the like, generation of a voltage in wiring by capacitive coupling between a conductor that forms a conductor layer and wiring in a case where a voltage is applied to the conductor, and occurrence of voltage noise in the wiring as the applied voltage changes. This voltage noise becomes noise of the pixel signal.

To reduce the noise, a conductor layer to which a predetermined amount of shift is set in a direction orthogonal to a longitudinal direction of the wiring1512that constitutes a part of the Victim conductor loop, like the conductor layer1611on the left side inFIG.165, has been conceived by the inventors of the present application.

The conductor layer1611includes a reticulated conductor1601and a relay conductor1602arranged in the gap region of the reticulated conductor1601. The reticulated conductor1601is, for example, wiring (Vss wiring) connected to the GND or the negative power supply. The relay conductor1602is, for example, wiring (Vdd wiring) connected to the positive power supply.

In the case of providing the predetermined amount of shift in the direction orthogonal to the longitudinal direction of the wiring1512in this way, when the Vdd wiring and the Vss wiring are linearly integrated in the Y direction, the total charge amount by Vdd and the total charge amount by Vss can be made substantially the same, as illustrated on the right side inFIG.165. Furthermore, the polarities of the voltages of the reticulated conductor1601and the relay conductor1602are opposite (opposite polarities) between Vdd and Vss. Therefore, according to the conductor layer1611, the capacitive noise in the wiring1512as a Victim conductor can be canceled. In the case where the Vdd wiring and the Vss wiring of Y-direction integration match, the capacitive noise can be completely canceled.

Hereinafter, a configuration example of reducing the capacitive noise, favorably completely canceling the capacitive noise, by providing a predetermined amount of shift in the direction orthogonal to the longitudinal direction of a Victim conductor in a conductor layer of a reticulated conductor, will be described.

First, the conductor widths and gap widths of the reticulated conductor1601and the relay conductor1602constituting the conductor layer1611as a first configuration example of the reticulated conductor provided with an amount of shift (a first shift configuration example of the reticulated conductor) will be described with reference toFIG.166.

The reticulated conductor1601has a conductor width WDX and a gap width GDX in the X direction, and is a repeating pattern of the conductor width WDX and the gap width GDX with a periodic width FDX (=the conductor width WDX+the gap width GDX). Furthermore, in the Y direction, the reticulated conductor1601has a conductor width WDY and a gap width GDY, and is a repeating pattern of the conductor width WDY and the gap width GDY with a periodic width FDY (=the conductor width WDY+the gap width GDY). Note that, in the reticulated conductor1601, the conductor arrangement with the conductor width WDX and the gap width GDX in the X direction is shifted in the X direction by a predetermined amount of shift PDX every time the periodic width FDY in the Y direction is repeated. The amount of shift PDX in the X direction in units of the periodic width FDY is hereinafter also referred to as a periodic shift PDX.

The relay conductor1602is arranged in the gap region with the gap width GDX in the X direction and the gap width GDY in the Y direction of the reticulated conductor1601. The relay conductor1602is a rectangle having a conductor width CDX in the X direction and a conductor width CDY in the Y direction, and is a vertically long rectangle in which the conductor width CDY in the Y direction is larger than the conductor width CDX in the X direction (CDY>CDX).

One end face of the relay conductor1602in the X direction is separated from the reticulated conductor1601by a first gap width GDX1, and the other end face in the X direction is separated from the reticulated conductor1601by a second gap width GDX2. The gap width GDX in the X direction of the reticulated conductor1601is equal to the sum of the conductor width CDX in the X direction of the relay conductor1602, the first gap width GDX1, and the second gap width GDX2. That is, GDX=CDX+GDX1+GDX2.

One end face of the relay conductor1602in the Y direction is separated from the reticulated conductor1601by a first gap width GDY1, and the other end face in the Y direction is separated from the reticulated conductor1601by a second gap width GDY2. The gap width GDY in the Y direction of the reticulated conductor1601is equal to the sum of the conductor width CDY in the Y direction of the relay conductor1602, the first gap width GDY1, and the second gap width GDY2. That is, GDY=CDY+GDY1+GDY2.

Here, the magnitude relationship of the conductor width and the gap width between the reticulated conductor1601and the relay conductor1602is defined as follows.

As illustrated inFIG.166, where A is an arbitrary real number, the conductor width WDX in the X direction and the conductor width WDY in the Y direction of the reticulated conductor1601are widths of 2A. In other words, the real number A is ½ of the conductor width WDX in the X direction and the conductor width WDY in the Y direction of the reticulated conductor1601. Furthermore, the first gap width GDX1 and the second gap width GDX2 in the X direction are also 2A.

The conductor width CDX in the X direction of the relay conductor1602is set to 6A, and the conductor width CDY in the Y direction is set to 7A. The first gap width GDY1 and the second gap width GDY2 in the Y direction are set to 1A.

Therefore, the periodic width FDX (=the conductor width WDX+the gap width GDX) corresponds to 12A and the periodic width FDY (=the conductor width WDY+the gap width GDY) corresponds to 11A when expressed using the arbitrary real number A.

FIGS.167and168are plan views of the conductor layer1611in which the periodic shift PDX is set to various values.

A inFIG.167is a plan view of the conductor layer1611in which the periodic shift PDX is set to zero. Note that the conductor layer1611in which the periodic shift PDX is set to zero corresponds to the reticulated conductor1501inFIG.164.

B inFIG.167is a plan view of the conductor layer1611in which the periodic shift PDX in the X direction is set to 1A, that is, 1/12 of the repetition period (periodic width FDX) in the X direction.

C inFIG.167is a plan view of the conductor layer1611in which the periodic shift PDX is set to 2A, that is, 2/12 of the repetition period (periodic width FDX) in the X direction.

D inFIG.167is a plan view of the conductor layer1611in which the periodic shift PDX is set to 3A, that is, 3/12 of the repetition period (periodic width FDX) in the X direction.

A inFIG.168is a plan view of the conductor layer1611in which the periodic shift PDX is set to 4A, that is, 4/12 of the repetition period (periodic width FDX) in the X direction.

B inFIG.168is a plan view of the conductor layer1611in which the periodic shift PDX is set to 5A, that is, 5/12 of the repetition period (periodic width FDX) in the X direction.

C inFIG.168is a plan view of the conductor layer1611in which the periodic shift PDX is set to 6A, that is, 6/12 of the repetition period (periodic width FDX) in the X direction.

FIG.169is a graph illustrating theoretical values of the capacitive noise of the conductor layer1611in which the periodic shift PDX is set to various values as illustrated inFIGS.167and168.

The horizontal axis ofFIG.169represents coordinates indicating the position of the conductor layer1611in the X direction, and the vertical axis represents the capacitive noise of the Vdd wiring and the Vss wiring at each X position. Note that it is assumed that absolute values of the applied voltage of the Vdd wiring (Vdd applied voltage) and the applied voltage of the Vss wiring (Vss applied voltage) are the same. For example, a case in which the Vdd applied voltage is +1 V and the Vss applied voltage is −1 V is assumed.

As illustrated inFIG.169, in a case where the periodic shift PDX is a predetermined value, the amount of change in the capacitive noise is zero and the absolute value of the capacitive noise is zero. More specifically, in a case where the periodic shift PDX is set to 1/12, 2/12, or 5/12 of the repetition period in the X direction, the amount of change in the capacitive noise is zero and the absolute value of the capacitive noise is zero.

In a case of another periodic shift PDX, specifically, in a case where the periodic shift PDX is 3/12, 4/12, or 6/12 of the repetition period in the X direction, the amount of change in the capacitive noise and the absolute value are not zero, but the change in the amount of change in the capacitive noise can be made smaller than a case where the periodic shift PDX is zero, that is, in a case of no periodic shift.

FIG.170is a graph illustrating theoretical values of the capacitive noise in a case where the periodic shift PDX is set to various values in the conductor layer1611from which the relay conductor1602is omitted. Although illustration of the conductor layer1611from which the relay conductor1602is omitted is omitted, it corresponds to each of the conductor layers1611inFIGS.167and168from which the relay conductor1602is removed.

In the absence of the relay conductor1602, the absolute value of the capacitive noise is not zero, as illustrated inFIG.170, but the amount of change in the capacitive noise is zero in a case where the periodic shift PDX is a predetermined value. The amount of shift at which the amount of change in the capacitive noise becomes zero is the same as the case where the relay conductor1602is present. That is, in a case where the periodic shift PDX is set to 1/12, 2/12, or 5/12 of the repetition period in the X direction, the amount of change in the capacitive noise is zero. In a case of another periodic shift PDX, specifically, in a case where the periodic shift PDX is 3/12, 4/12, or 6/12 of the repetition period in the X direction, the amount of change in the capacitive noise is not zero, but the change in the amount of change in the capacitive noise can be made smaller than a case where the periodic shift PDX is zero, that is, in a case of no periodic shift.

When the following conditions are satisfied, the amount of change in the capacitive noise becomes zero according to the graphs inFIGS.169and170.

First, as a premise, the periodic shift PDX is set to a value different from the periodic width FDX (=12A) in the X direction of the reticulated conductor1601.

In a case where the periodic shift PDX is 2A, that is, the periodic shift PDX is the same as the conductor width WDX in the X direction of the reticulated conductor1601, the amount of change in the capacitive noise becomes zero. Furthermore, the amount of change in the capacitive noise becomes zero in a case where the periodic shift PDX is 1A and in a case where the periodic shift PDX is 5A.

In a case where the periodic shift PDX is 1A or 5A, the amount of change in the capacitive noise becomes zero in units of twelve rows. Meanwhile, in a case where the periodic shift PDX is 2A, the amount of change in the capacitive noise becomes zero in units of six rows. In a case where the periodic shift PDX is equal to the conductor width WDX of the reticulated conductor1601, the amount of change in the capacitive noise can be made zero with a small number of rows. Therefore, the degree of freedom in the wiring layout can be increased.

In a case where the periodic shift PDX is different from the repetition period of 3/12 (=3A) in the X direction of the reticulated conductor1601, in other words, in a case where the periodic shift PDX is not the periodic width FDX (=12A)+4, the amount of change in the capacitive noise becomes zero.

In a case where the periodic shift PDX is different from the repetition period of 4/12 (=4A) in the X direction of the reticulated conductor1601, in other words, in a case where the periodic shift PDX is not the periodic width FDX (=12A)+3, the amount of change in the capacitive noise becomes zero.

In a case where the periodic shift PDX is different from the repetition period of 6/12 (=6A) in the X direction of the reticulated conductor1601, in other words, in a case where the periodic shift PDX is not the periodic width FDX (=12A)+2, the amount of change in the capacitive noise becomes zero.

In the presence of the relay conductor1602, not only the amount of change in the capacitive noise becomes zero but also the absolute value of the capacitive noise can be made zero. In the absence of the relay conductor1602, the amount of change in the capacitive noise is zero, but the absolute value of the capacitive noise is not zero.

Furthermore, the effect of improving the capacitive noise is greater in the presence of the relay conductor1602than the absence of the relay conductor1602.

InFIGS.167to170, the examples in which the periodic shift PDX is shifted in the positive direction of the X axis until the periodic shift PDX becomes 6A, which is half of the periodic width FDX (=12A), have been described. The same applies to a case where the periodic shift PDX is shifted in the negative direction of the X axis. More specifically, the capacitive noise in the case where the periodic shift PDX is shifted in the negative direction of the X axis by 1A, 2A, 3A, 4A, 5A, and 6A is similar to theoretical values of the capacitive noise in the case where the periodic shift PDX is shifted in the positive direction of the X axis by 1A, 2A, 3A, 4A, 5A, and 6A inFIGS.169and170.

Furthermore, the capacitive noise in the case where the periodic shift PDX is shifted in the positive direction of the X axis by 7A, 8A, 9A, 10A, and 11A is similar to theoretical values of the capacitive noise in the case where the periodic shift PDX is shifted in the negative direction of the X axis by 5A, 4A, 3A, 2A, and 1A inFIGS.169and170. In other words, the capacitive noise in the case where the periodic shift PDX is shifted in the positive direction of the X axis by 7A, 8A, 9A, 10A, and 11A is similar to theoretical values of the capacitive noise in the case where the periodic shift PDX is shifted in the positive direction of the X axis by 5A, 4A, 3A, 2A, and 1A.

Furthermore, the capacitive noise in the case where the periodic shift PDX is shifted in the positive direction of the X axis by 13A, 14A, 15A, 16A, 17A, and 18A is similar to theoretical values of the capacitive noise in the case where the periodic shift PDX is shifted in the positive direction of the X axis by 1A, 2A, 3A, 4A, 5A, and 6A inFIGS.169and170. The same applies in the case where the periodic shift PDX is shifted in the negative direction of the X axis by 13A, 14A, 15A, 16A, 17A, and 18A.

According to the conductor layer1611that is the first shift configuration example of the reticulated conductor, the amount of change in the capacitive noise can be made smaller than the case where the periodic shift PDX is zero, that is, in the case of no periodic shift by providing the periodic shift PDX in the X direction. Moreover, in a case where the periodic shift PDX satisfies a predetermined condition, such as a case where the periodic shift PDX is set to be the same as the conductor width WDX in the X direction of the reticulated conductor1601, for example, the amount of change in the capacitive noise can be made zero.

Moreover, in a case where the relay conductor1602is provided in the gap region of the reticulated conductor1601, the absolute value of the capacitive noise can be made zero in the case where the amount of change in the capacitive noise is zero.

In a case where the following three conditions are satisfied, both the amount of change in the capacitive noise and the absolute value can be zero, that is, the capacitive noise can be completely canceled. The following conditions are referred to as first to third conditions of complete offset.
The area of theVddconductor within a predetermined range=the area of theVssconductor within the predetermined range  1.
(The conductor widthCDX)×(the conductor widthCDY)={(the conductor widthCDY)+(the first gap widthGDY1)+(the second gap widthGDY2)}×(the conductor widthWDX)+{(the conductor widthCDX)+(the first gap widthGDX1)+(the second gap widthGDX2)}×(the conductor widthWDY)+(the conductor widthWDX)×(the conductor widthWDY)
(The conductor widthCDY)×{the minimum number of rows−{(the conductor widthWDX)+(the first gap widthGDX1)+(the second gap widthGDX2)}÷the conductor widthWDX}=(the conductor widthWDY)×the minimum number of rows+(the conductor widthCDY)+(the first gap widthGDY1)+(the second gap widthGDY2)  2.
The periodic shiftPDX×the number of offset rows=an integerN×{(the conductor widthWDX)+(the first gap widthGDX1)+(the conductor widthCDX)+(the second gap widthGDX2)}  3.

The first condition of complete offset means that the conductive area of the reticulated conductor1601within the predetermined range match the conductive area of the relay conductor1602within the predetermined range, but the match may not be the exact match and the conductive areas may be substantially the same. Substantially the same means that the conductive areas match within a predetermined range (error) that can be regarded as the same. The minimum number of rows in the second condition represents the minimum number of rows of the reticulated conductor1601in which the capacitive noise can be completely canceled in the case where the periodic shift PDX is the conductor width WDX. With some exceptions, there is a condition in which the capacitive noise can be completely canceled in a case where the number of rows of the reticulated conductor1601is an integral multiple of the minimum number of rows. Since the second condition can be transformed into “the minimum number of rows={(the first gap width GDY1)+(the second gap width GDY2)+(the conductor width CDY)+(the conductor width CDY)×{(the conductor width WDX)+(the first gap width GDX1)+(the second gap width GDX2)}÷the conductor width WDX}÷{(the conductor width CDY)−(the conductor width WDY)}”, the minimum number of rows can be calculated, and since the left side of the formula (the minimum number of rows) is an integer value, the right side of the formula is also an integer value. Note that the second condition is derived from the fact that the complete offset can be performed in the case where the sum of the conductor lengths in the Y direction of the reticulated conductor1601in the predetermined range matches the sum of the conductor lengths in the Y direction of the relay conductor1602within the predetermined range. That is, it is desirable that the sum of the conductor lengths in the Y direction of the reticulated conductor1601in the predetermined range and the sum of the conductor lengths in the Y direction of the relay conductor1602within the predetermined range are the same or substantially the same regardless of the minimum number of rows. The number of offset rows in the third condition represents the number of rows of the reticulated conductor1601in which the capacitive noise can be completely canceled. The integer N in the third condition represents a condition in which the capacitive noise can be completely canceled. With some exceptions, the number of offset rows is an integer, and in the case where “the periodic shift PDX×the number of offset rows” becomes an integral multiple (N times) of “(the conductor width WDX)+(the first gap width GDX1)+(the conductor width CDX)+(the second gap width GDX2), that is, in the case where “the periodic shift PDX×the number of offset rows” becomes an integral multiple (N times) of the periodic width FDX, there is a condition in which the capacitive noise can be completely canceled. In other words, it is desirable that the sum of the periodic shift PDX of the number of offset rows (the periodic shift PDX×the number of offset rows) and the integral multiple (N times) of the periodic width FDX becomes the same or substantially the same. Furthermore, although there may be some exceptions, there is a condition that the capacitive noise can be completely canceled in the case where the number of offset rows becomes an integral multiple of the minimum number of rows. Furthermore, the capacitive noise can be completely offset in a case where the number of rows of the reticulated conductor1601is the number of rows obtained by multiplying the number of offset rows by an integer. Note that it is conceivable that it is necessary to satisfy at least the first condition in order to completely cancel the capacitive noise. However, there are some cases where at least part of the capacitive noise can be canceled in a case where at least one of the second condition or the third condition is satisfied among the first to third conditions. Therefore, at least only part of the first to third conditions may be satisfied. Furthermore, in that case, the minimum number of rows or the number of offset rows may be interpreted as the number of rows of the reticulated conductor1601.

By providing the periodic shift PDX to some extent, the effect of improving the capacitive noise can be increased even in the case where the amount of change in the capacitive noise is not zero.

Note that, in the above-described first shift configuration example, the absolute values of the Vdd applied voltage and the Vss applied voltage are the same, but the absolute values do not necessarily have to be the same. For example, the Vdd applied voltage may be a positive power supply (+1V) and the Vss applied voltage may be the GND (0 V). Even in the case where the absolute values of the Vdd applied voltage and the Vss applied voltage are not the same, at least a part of the capacitive noise is canceled by providing the periodic shift PDX in the X direction, so that the effect of improving the capacitive noise is obtained. Furthermore, even if the Vdd applied voltage and the Vss applied voltage are not the same, the capacitive noise may be completely canceled when, for example, the current direction differs between the Vdd conductor and the Vss conductor (particularly in the opposite direction), and the capacitive noise caused by a change by the voltage drop (IR-Drop) has an opposite polarity between the Vdd conductor and the Vss conductor.

The reticulated conductor1601having the periodic shift PDX in the X direction will be defined with reference toFIG.171.

The reticulated conductor1601can be divided into a plurality of conductors1651wired in the X direction, and a plurality of conductors1652wired in the Y direction between two adjacent conductors1651.

The reticulated conductor1601includes a first conductor group1661including two or more conductors1651having the conductor width WDY (first conductor width) arranged in the Y direction (first direction) with the periodic width FDY (first periodic width) and a second conductor group1662including two or more conductors1652having the conductor width WDX (second conductor width) arranged in the periodic width FDX (second periodic width) in the X direction (second direction) orthogonal to the Y direction.

Moreover, the reticulated conductor1601includes a first moving body group1663arranged at a position obtained by moving at least a part (for example, all) of the second conductor group1662including the two or more conductors1652by a factor of 1 of the periodic width FDY in the Y direction and moving at least the part by a factor of 1 of the periodic shift PDX (third periodic width) in the X direction. Here, the periodic shift PDX and the periodic width FDX are different.

Furthermore, in a case where the reticulated conductor1601further includes an Mth moving body group1663(M=2, 3, 4, 5, . . . , L (L is an integer of 2 or larger)) arranged at a position to which at least a part (for example, all) of the second conductor group1662including two or more conductors1652is moved by a factor of M of the periodic width FDY in the Y direction, and is moved by a factor of M of the periodic shift PDX (third periodic width) in the X direction, the reticulated conductor1601becomes the reticulated conductor illustrated inFIG.172.

Since the reticulated conductor1601has the configuration provided with the periodic shift PDX different from the periodic width FDX, as inFIGS.171and172, the capacitive noise for the wiring (conductor) arranged at the position overlapping with at least a part of the reticulated conductor1601as viewed from the Z direction orthogonal to the X direction and the Y direction can be reduced or favorably completely canceled. Examples of the wiring include the signal lines132and the control lines133of the solid-state imaging device100, as described with reference toFIGS.164and165.

Modification of First Shift Configuration Example of Reticulated Conductor

FIGS.173to181illustrate various modifications of the first shift configuration example of the reticulated conductor.

Note that, inFIGS.173to181, the periodic shift PDX is 2A, that is, the conductor width WDX of the reticulated conductor1601. Furthermore, in the description of the various modifications inFIGS.173to181, for the sake of simplicity, the first shift configuration example of the reticulated conductor illustrated inFIGS.167and168is referred to as a basic configuration example of periodic shift, and only the parts different from the basic configuration example of periodic shift will be described.

A inFIG.173is a plan view illustrating a first modification of the first shift configuration example of the reticulated conductor.

The first modification in A inFIG.173is different from the basic configuration example of periodic shift in that arrangement of the relay conductor1602is changed to left shift in the gap region. In the basic configuration example of periodic shift, (the first gap width GDX1)=(the second gap width GDX2), whereas in the first modification, (the first gap width GDX1)<(the second gap width GDX2).

B inFIG.173is a plan view illustrating a second modification of the first shift configuration example of the reticulated conductor.

The second modification in B inFIG.173is different from the basic configuration example of periodic shift in that arrangement of the relay conductor1602is changed to right shift in the gap region. In the basic configuration example of periodic shift, (the first gap width GDX1)=(the second gap width GDX2), whereas in the second modification, (the first gap width GDX1)>(the second gap width GDX2).

A inFIG.174is a plan view illustrating a third modification of the first shift configuration example of the reticulated conductor.

The third modification in A inFIG.174is different from the basic configuration example of periodic shift in that arrangement of the relay conductor1602is changed to upper shift in the gap region. In the basic configuration example of periodic shift, (the first gap width GDY1)=(the second gap width GDY2), whereas in the third modification, (the first gap width GDY1)<(the second gap width GDY2).

B inFIG.174is a plan view illustrating a fourth modification of the first shift configuration example of the reticulated conductor.

The fourth modification in B inFIG.174is different from the basic configuration example of periodic shift in that arrangement of the relay conductor1602is changed to lower shift in the gap region. In the basic configuration example of periodic shift, (the first gap width GDY1)=(the second gap width GDY2), whereas in the fourth modification, (the first gap width GDY1)>(the second gap width GDY2).

A inFIG.175is a plan view illustrating a fifth modification of the first shift configuration example of the reticulated conductor.

The fifth modification in A inFIG.175is different from the basic configuration example of periodic shift in that arrangement of the relay conductor1602is changed to alternate arrangement of upper shift and lower shift for each column. The magnitude relationship between (the first gap width GDY1) and (the second gap width GDY2) in each of the upper shift and the lower shift is similar to that in the third modification and the fourth modification.

B inFIG.175is a plan view illustrating a sixth modification of the first shift configuration example of the reticulated conductor.

The sixth modification in B inFIG.175is different from the basic configuration example of periodic shift in that arrangement of the relay conductor1602is changed to alternate arrangement of upper shift and lower shift for each row and for each column. The magnitude relationship between (the first gap width GDY1) and (the second gap width GDY2) in each of the upper shift and the lower shift is similar to that in the third modification and the fourth modification.

Although not illustrated, alternate arrangement of right shift and left shift for each column, or alternate arrangement of right shift and left shift for each row and for each column is also similarly possible.

A inFIG.176is a plan view illustrating a seventh modification of the first shift configuration example of the reticulated conductor.

The seventh modification in A inFIG.176is different from the basic configuration example of periodic shift in that the arrangement of the relay conductor1602is changed to arrangement in which two rows forming a pair and in inner shift are repeated in the Y direction. The magnitude relationship between (the first gap width GDY1) and (the second gap width GDY2) in each of the upper shift and the lower shift is similar to that in the third modification and the fourth modification.

B inFIG.176is a plan view illustrating an eighth modification of the first shift configuration example of the reticulated conductor.

The eighth modification in B inFIG.176is different from the basic configuration example of periodic shift in that the arrangement of the relay conductor1602is changed to arrangement in which two rows forming a pair and in inner shift and outer shift for each two columns and for each two rows are repeated in the Y direction. The magnitude relationship between (the first gap width GDY1) and (the second gap width GDY2) in each of the upper shift and the lower shift is similar to that in the third modification and the fourth modification.

A inFIG.177is a plan view illustrating a ninth modification of the first shift configuration example of the reticulated conductor.

The ninth modification in A inFIG.177is different from the basic configuration example of periodic shift in that the relay conductor1602is evenly separated into two parts in a right-left direction. The separated two relay conductors1602are mirror-symmetrically arranged in the separation direction (X direction).

B inFIG.177is a plan view illustrating a tenth modification of the first shift configuration example of the reticulated conductor.

The tenth modification in B inFIG.177is different from the basic configuration example of periodic shift in that the relay conductor1602is separated into two parts in the right-left direction, and arrangements of the two parts in the up-down direction (Y direction) are different.

A inFIG.178is a plan view illustrating an eleventh modification of the first shift configuration example of the reticulated conductor.

The eleventh modification in A inFIG.178is different from the basic configuration example of periodic shift in that the relay conductor1602is unevenly separated into two parts in the right-left direction. In the eleventh modification in A inFIG.178, the left part of the separated two parts is larger than the right part, but a configuration in which the right part is larger than the left part can also be adopted. Furthermore, a configuration in which the relay conductor1602is unevenly separated into two parts in the up-down direction can also be adopted.

B inFIG.178is a plan view illustrating a twelfth modification of the first shift configuration example of the reticulated conductor.

The twelfth modification in B inFIG.178is different from the basic configuration example of periodic shift in that the relay conductor1602is divided into two parts without being separated in the right-left direction, and shifted in the up-down direction In the twelfth modification in B inFIG.178, the left part is shifted upward and the right part is shifted downward, of the right and left two parts shifted in the up-down direction. However, a configuration in which the right part is shifted upward and the left part is shifted downward can also be adopted. Furthermore, a configuration in which the two parts are shifted in the right-left direction from the center in the up-down direction can also be adopted.

A inFIG.179is a plan view illustrating a thirteenth modification of the first shift configuration example of the reticulated conductor.

The thirteenth modification in A inFIG.179is different from the basic configuration example of periodic shift in that the relay conductor1602is evenly separated into three parts in the right-left direction.

Although not illustrated, configurations similar to the two-separation configurations illustrated inFIGS.177and178are also possible in addition to such a three-even separation configuration in the right-left direction. For example, a three-even separation configuration in the up-down direction, a three-uneven separation configuration in the right-left direction, a three-uneven separation configuration in the up-down direction, a configuration of three-even separation in the right-left direction and shifted in the up-down direction, a configuration of three-even separation in the up-down direction and shifted in the right-left direction, a configuration in which three divisions without separation are shifted in the up-down direction, a configuration in which three divisions without separation are shifted in the right-left direction, and the like are also possible.

B inFIG.179is a plan view illustrating a fourteenth modification of the first shift configuration example of the reticulated conductor.

The fourteenth modification in B inFIG.179is different from the basic configuration example of periodic shift in that the relay conductor1602is evenly separated into four parts in the up-down direction and the right-left direction.

Even in the configuration in which the relay conductor1602is separated into four parts, uneven separation, a configuration in which the separated four parts are shifted in at least one of the up-down direction or the right-left direction, and a configuration in which the separated four are shifted without separation can also be adopted, for example.

InFIGS.177to179, examples in which the relay conductor1602is configured by two-separation, three-separation, or four-separation have been described. However, an arbitrary number of separations of five-separation or more is also possible. InFIG.180, examples of five-separation and nine-separation will be described.

A inFIG.180is a plan view illustrating a fifteenth modification of the first shift configuration example of the reticulated conductor.

The fifteenth modification in A inFIG.180is different from the basic configuration example of periodic shift in that the relay conductor1602is separated into five parts. In the example in A inFIG.180, the center region is large among the separated five parts. However, such size relationship and arrangement relationship among the five parts are example, and the configuration is not limited to the example.

B inFIG.180is a plan view illustrating a sixteenth modification of the first shift configuration example of the reticulated conductor.

The sixteenth modification in B inFIG.180is different from the basic configuration example of periodic shift in that the relay conductor1602is separated into nine parts. In the example in B inFIG.180, the center region is large among the separated nine parts. However, such size relationship and arrangement relationship among the nine parts are example, and the configuration is not limited to the example.

A inFIG.181is a plan view illustrating a seventeenth modification of the first shift configuration example of the reticulated conductor.

The seventeenth modification in A inFIG.181is different from the basic configuration example of periodic shift in that the relay conductor1602has one or more gaps (holes) inside. The number, position, and shape of the gaps are not limited to this example.

B inFIG.181is a plan view illustrating an eighteenth modification of the first shift configuration example of the reticulated conductor.

The eighteenth modification in B inFIG.181is different from the basic configuration example of periodic shift in that the relay conductor1602has a configuration in which an outer conductor surrounds an inner conductor. The number, position, and shape of the conductors are not limited to this example.

As described with reference toFIGS.173to181, the relay conductor1602need not be centrally arranged in the gap region of the reticulated conductor1601. For example, the relay conductors1602may be arranged with a bias in the X direction or the Y direction, or a plurality of relay conductors1602may be arranged. Furthermore, the relay conductor1602may have an asymmetric shape in the X direction or the Y direction, a symmetrical shape in the X direction or the Y direction, or a rotationally symmetrical shape. Note that, in the theoretical value of the capacitive noise in each of the modifications inFIGS.173to181, the amount of change in the capacitive noise is zero and the absolute value of the capacitive noise is zero, similarly to the case where the periodic shift PDX is 2A in the first shift configuration example.

Note that regardless of the shape and arrangement of the relay conductor1602, the relay conductor1602is formed to satisfy at least the above-described first condition of complete offset.

In the first to eighteenth modifications illustrated inFIGS.173to181, for example, the degree of freedom in design and the degree of freedom in arranging another conductor, some element or object in the gap region are improved.

Moreover, the relay conductor1602may be a non-reticulated conductor that is a conductor not electrically connecting another conductor layer and another conductor layer, rather than the conductor electrically connecting another conductor layer and another conductor layer. Note that the relay conductor1602is desirably the conductor electrically relaying other conductor layers, rather than the non-reticulated conductor not electrically connecting other conductor layers. In a case where the relay conductor1602is used, the degree of freedom in the wiring layout for drawing in the power supply is improved. Furthermore, the voltage drop can be further improved depending on arrangement of the active elements such as MOS transistors and diodes. Furthermore, the presence of the relay conductor1602may improve the inductive noise, and the presence of a plurality of relay conductors1602(separation arrangement or division arrangement) may further improve the inductive noise.

Second Shift Configuration Example of Reticulated Conductor

FIG.182is a plan view illustrating a second shift configuration example of the reticulated conductor.

In the second shift configuration example of the reticulated conductor, even in a case where some of the dimensions of the reticulated conductor or the relay conductor is changed, the amount of change in the capacitive noise can be made zero.

A conductor layer1711inFIG.182is configured by a reticulated conductor1701and a relay conductor1702.

In the conductor layer1711inFIG.182, the dimensions of the conductor width CDY, the first gap width GDY1, and the second gap width GDY2 in the Y direction of the relay conductor1702are changed to be different from those of the first shift configuration example.

Specifically, as illustrated inFIG.166, in the above-described first shift configuration example, the conductor width CDY in the Y direction of the relay conductor1702is 7A, and the first gap width GDY1 and the second gap width GDY2 are 1A, where ½ of the conductor width WDX in the X direction and the conductor width WDY in the Y direction of the reticulated conductor1601is a real number A.

In contrast, in the second shift configuration example inFIG.182, the conductor width CDY in the Y direction of the relay conductor1702is 8A, and the first gap width GDY1 and the second gap width GDY2 are 2A.

In other words, in the above-described first shift configuration example, the gap width GDY in the Y direction of the reticulated conductor1601is 9A, whereas in the second shift configuration example, the gap width GDY is expanded to 12A.

In the second shift configuration example, the dimensions of the other conductor widths and gap widths are similar to those in the first shift configuration example. The second shift configuration example also satisfies at least the above-described first condition of complete offset.

FIG.183is a graph illustrating theoretical values of the capacitive noise of the conductor layer1711in which the periodic shift PDX is set to various values in the second shift configuration example, as in the first shift configuration example.

Since the horizontal axis and the vertical axis of the graph inFIG.183are similar to those inFIG.169, the description thereof will be omitted. Note that the scale of the graph inFIG.183is also illustrated in accordance withFIG.169.

As illustrated inFIG.183, even in the second shift configuration example, in a case where the periodic shift PDX is a predetermined value, the amount of change in the capacitive noise is zero and the absolute value of the capacitive noise is zero. More specifically, in a case where the periodic shift PDX is set to 1/12, 2/12, or 5/12 of the repetition period in the X direction, the amount of change in the capacitive noise is zero and the absolute value of the capacitive noise is zero.

In a case of another periodic shift PDX, specifically, in a case where the periodic shift PDX is 3/12, 4/12, or 6/12 of the repetition period in the X direction, the amount of change in the capacitive noise and the absolute value are not zero, but the change in the amount of change in the capacitive noise can be made smaller than a case where the periodic shift PDX is zero, that is, in a case of no periodic shift.

In the second shift configuration example in which the dimensions in the Y direction are expanded, the capacitive noise in the case where the periodic shift PDX is zero, that is, in the case of no periodic shift, illustrated by the broken line inFIG.183, is worse than the capacitive noise in the case of no periodic shift in the first shift configuration example. It can be seen that an improvement effect is enhanced by setting the periodic shift PDX.

FIG.184is a graph illustrating theoretical values of the capacitive noise in a case where the relay conductor1702is not present in the second shift configuration example.

Since the horizontal axis and the vertical axis of the graph inFIG.184are similar to those inFIG.169, the description thereof will be omitted. Note that the scale of the graph inFIG.184is also illustrated in accordance withFIG.169.

In the absence of the relay conductor1602, the absolute value of the capacitive noise is not zero, as illustrated inFIG.184, but the amount of change in the capacitive noise is zero in a case where the periodic shift PDX is a predetermined value. The amount of shift at which the amount of change in the capacitive noise becomes zero is the same as the case where the relay conductor1602is present. That is, in a case where the periodic shift PDX is set to 1/12, 2/12, or 5/12 of the repetition period in the X direction, the amount of change in the capacitive noise is zero.

From the graphs inFIGS.183and184, the condition that the amount of change in the capacitive noise becomes zero in the second shift configuration example is similar to the case in the first shift configuration example.

That is, the periodic shift PDX is set to a value different from the periodic width FDX (=12A) in the X direction of the reticulated conductor1701.

In a case where the periodic shift PDX is 2A, that is, the periodic shift PDX is the same as the conductor width WDX in the X direction of the reticulated conductor1701, the amount of change in the capacitive noise becomes zero. Furthermore, the amount of change in the capacitive noise becomes zero in a case where the periodic shift PDX is 1A and in a case where the periodic shift PDX is 5A.

In a case where the periodic shift PDX is 1A or 5A, the amount of change in the capacitive noise becomes zero in units of twelve rows. Meanwhile, in a case where the periodic shift PDX is 2A, the amount of change in the capacitive noise becomes zero in units of six rows. In a case where the periodic shift PDX is equal to the conductor width WDX of the reticulated conductor1701, the amount of change in the capacitive noise can be made zero with a small number of rows. Therefore, the degree of freedom in the wiring layout can be increased.

In a case where the periodic shift PDX is different from the repetition period of 3/12 (=3A) in the X direction of the reticulated conductor1701, in other words, in a case where the periodic shift PDX is not the periodic width FDX (=12A)+4, the amount of change in the capacitive noise becomes zero.

In a case where the periodic shift PDX is different from the repetition period of 4/12 (=4A) in the X direction of the reticulated conductor1701, in other words, in a case where the periodic shift PDX is not the periodic width FDX (=12A)+3, the amount of change in the capacitive noise becomes zero.

In a case where the periodic shift PDX is different from the repetition period of 6/12 (=6A) in the X direction of the reticulated conductor1701, in other words, in a case where the periodic shift PDX is not the periodic width FDX (=12A)+2, the amount of change in the capacitive noise becomes zero.

In the presence of the relay conductor1702, not only the amount of change in the capacitive noise becomes zero but also the absolute value of the capacitive noise can be made zero. In the absence of the relay conductor1702, the amount of change in the capacitive noise is zero, but the absolute value of the capacitive noise is not zero.

Furthermore, the effect of improving the capacitive noise is greater in the presence of the relay conductor1702than the absence of the relay conductor1702.

Third Shift Configuration Example of Reticulated Conductor

In the first and second shift configuration examples, the condition of the periodic shift PDX when the amount of change in the capacitive noise becomes zero is the same between the presence of the relay conductor and the absence of the relay conductor.

Next, an example in which the condition of the periodic shift PDX when the amount of change in the capacitive noise becomes zero is different between the presence of the relay conductor and the absence of the relay conductor will be described as a third shift configuration example.

FIG.185is a plan view for describing a conductor width and a gap width of a conductor layer as a third shift configuration example of the reticulated conductor.

A conductor layer1731inFIG.185is configured by a reticulated conductor1721and a relay conductor1722.

The reticulated conductor1721has the conductor width WDX set to 3A and the conductor width WDY set to 1A, where the arbitrary real number is A. The gap region of the reticulated conductor1721is formed by the gap width GDX set to 6A and the gap width GDY set to 17A.

The relay conductor1722arranged in the gap region of the reticulated conductor1721is a rectangle having the conductor width CDX set to 4A and the conductor width CDY set to 15A, and is a vertically long rectangle in which the conductor width CDY in the Y direction is larger than the conductor width CDX in the X direction (CDY>CDX). Both the first gap width GDX1 and the second gap width GDX2 in the X direction are set to 1A between the reticulated conductor1721and the relay conductor1722. Furthermore, both the first gap width GDY1 and the second gap width GDY2 in the Y direction are set to 1A.

Therefore, the periodic width FDX (=the conductor width WDX+the gap width GDX) corresponds to 9A and the periodic width FDY (=the conductor width WDY+the gap width GDY) corresponds to 18A when expressed using the arbitrary real number A. In the third shift configuration example, the real number A is equal to ⅓ of the conductor width WDX in the X direction of the reticulated conductor1721.

The third shift configuration example also satisfies at least the above-described first condition of complete offset.

FIGS.186and187are plan views in which the periodic shift PDX is set to various values in the conductor layer1731as a third shift configuration example of the reticulated conductor.

A inFIG.186is a plan view of the conductor layer1731in which the periodic shift PDX is set to zero.

B inFIG.186is a plan view of the conductor layer1731in which the periodic shift PDX in the X direction is set to 1A, that is, 1/9 of the repetition period (periodic width FDX) in the X direction.

C inFIG.186is a plan view of the conductor layer1731in which the periodic shift PDX is set to 2A, that is, 2/9 of the repetition period (periodic width FDX) in the X direction.

A inFIG.187is a plan view of the conductor layer1731in which the periodic shift PDX is set to 3A, that is, 3/9 of the repetition period (periodic width FDX) in the X direction.

B inFIG.187is a plan view of the conductor layer1731in which the periodic shift PDX is set to 4A, that is, 4/9 of the repetition period (periodic width FDX) in the X direction.

FIG.188is a graph illustrating theoretical values of the capacitive noise of the conductor layer1731in which the periodic shift PDX is set to various values as illustrated inFIGS.186and187.

Since the horizontal axis and the vertical axis of the graph inFIG.188are similar to those inFIG.169, the description thereof will be omitted. Note that the scale of the graph inFIG.188is also illustrated in accordance withFIG.169. Conditions for the Vdd applied voltage and Vss applied voltage are similar.

As illustrated inFIG.188, in a case where the periodic shift PDX is a predetermined value, the amount of change in the capacitive noise is zero and the absolute value of the capacitive noise is zero. More specifically, in a case where the periodic shift PDX is set to 1/9, 2/9, or 4/9 of the repetition period in the X direction, the amount of change in the capacitive noise is zero and the absolute value of the capacitive noise is zero. In a case where the periodic shift PDX is set to 1/9 (=1A), 2/9 (=2A), or 4/9 (=4A) of the repetition period in the X direction, the amount of change in the capacitive noise becomes zero in units of nine rows.

In a case of another periodic shift PDX, specifically, in a case where the periodic shift PDX is 3/9 of the repetition period in the X direction, the amount of change in the capacitive noise and the absolute value are not zero, but the change in the amount of change in the capacitive noise can be made smaller than a case where the periodic shift PDX is zero, that is, in a case of no periodic shift.

From the above, in the third shift configuration example including the relay conductor1722, the amount of change in the capacitive noise can be made zero under the following conditions.

First, as a premise, the periodic shift PDX is set to a value different from the periodic width FDX (=9A) in the X direction of the reticulated conductor1721.

In a case where the periodic shift PDX is 1A, 2A, or 4A, the amount of change in the capacitive noise becomes zero in units of nine rows. Furthermore, in a case where the periodic shift PDX is different from the repetition period of 3/9 (=3A) in the X direction of the reticulated conductor1721, in other words, in a case where the periodic shift PDX is not the periodic width FDX (=9A)+3, the amount of change in the capacitive noise becomes zero.

FIG.189is a graph illustrating theoretical values of the capacitive noise in a case where the periodic shift PDX is set to various values in the conductor layer1731in which the relay conductor1722is omitted. Although illustration of the conductor layer1731from which the relay conductor1722is omitted is omitted, it corresponds to each of the conductor layers1731inFIGS.186and187from which the relay conductor1722is removed.

In the absence of the relay conductor1722, the absolute value of the capacitive noise is not zero, as illustrated inFIG.189, but the amount of change in the capacitive noise is zero in a case where the periodic shift PDX is a predetermined value. The amount of shift at which the amount of change in the capacitive noise becomes zero is different from the case where the relay conductor1722is present. Specifically, in a case where the periodic shift PDX is set to 1/9, 2/9, 3/9, or 4/9 of the repetition period in the X direction, the amount of change in the capacitive noise is zero. In a case where the periodic shift PDX is set to 1/9 (=1A), 2/9 (=2A), or 4/9 (=4A) of the repetition period in the X direction, the amount of change in the capacitive noise becomes zero in units of nine rows. In a case where the periodic shift PDX is set to 3/9 (=3A) of the repetition period in the X direction, the amount of change in the capacitive noise becomes zero in units of three rows.

From the above, in the third shift configuration example not including the relay conductor1722, the amount of change in the capacitive noise can be made zero under the following conditions.

First, as a premise, the periodic shift PDX is set to a value different from the periodic width FDX (=9A) in the X direction of the reticulated conductor1721.

In a case where the periodic shift PDX is 1A, 2A, or 4A, the amount of change in the capacitive noise becomes zero in units of nine rows. Furthermore, in a case where the periodic shift PDX is the same as 3/9 (=3A) that is the repetition period in the X direction of the reticulated conductor1721, the amount of change in the capacitive noise becomes zero in units of three rows.

Therefore, in the third shift configuration example, in a case where the periodic shift PDX is set to be the same as the conductor width WDX=3A of the reticulated conductor1721, the amount of change in the capacitive noise does not become zero in the presence of the relay conductor1722, but the amount of change in the capacitive noise becomes zero in the absence of the relay conductor1722. That is, in the third shift configuration example, the condition of the periodic shift PDX of when the amount of change in the capacitive noise becomes zero is different between the presence of the relay conductor1722and the absence of the relay conductor1722.

In the case where an integral multiple of the conductor width WDX of the reticulated conductor1721matches the periodic width FDX, and the periodic shift PDX matches the conductor width WDX according to the shape relationship between the conductor part and the gap region of the reticulated conductor1721, the capacitive noise is evenly distributed. Therefore, the amount of change in the capacitive noise can be made zero in the absence of the relay conductor1722.

Fourth Shift Configuration Example of Reticulated Conductor

In the first to third shift configuration examples, examples in which the relay conductor has the vertically long shape longer in the X direction than in the Y direction have been described.

Next, an example where the relay conductor has a horizontally long shape shorter in the Y direction than in the X direction will be described as the fourth shift configuration example.

FIG.190is a plan view for describing a conductor width and a gap width of a conductor layer as a fourth shift configuration example of the reticulated conductor.

The conductor layer1771inFIG.190is configured by a reticulated conductor1761and a relay conductor1762.

The reticulated conductor1761has the conductor width WDX set to 2A and the conductor width WDY set to 2A, where the arbitrary real number is A. The gap region of the reticulated conductor1761is formed by the gap width GDX set to 12A and the gap width GDY set to 10A.

The relay conductor1762arranged in the gap region of the reticulated conductor1761is a rectangle having the conductor width CDX set to 8A and the conductor width CDY set to 6A, and is a horizontally long rectangle in which the conductor width CDX in the X direction is larger than the conductor width CDY in the Y direction (CDX>CDY). Both the first gap width GDX1 and the second gap width GDX2 in the X direction are set to 2A between the reticulated conductor1761and the relay conductor1762. Furthermore, both the first gap width GDY1 and the second gap width GDY2 in the Y direction are set to 2A.

Therefore, the periodic width FDX (=the conductor width WDX+the gap width GDX) corresponds to 14A and the periodic width FDY (=the conductor width WDY+the gap width GDY) corresponds to 12A when expressed using the arbitrary real number A. In the fourth shift configuration example, the real number A is equal to ½ of the conductor width WDX in the X direction of the reticulated conductor1761.

The fourth shift configuration example also satisfies at least the above-described first condition of complete offset.

FIGS.191and192are plan views in which the periodic shift PDX is set to various values in the conductor layer1771as the fourth shift configuration example of the reticulated conductor.

A inFIG.191is a plan view of the conductor layer1771in which the periodic shift PDX is set to zero.

B inFIG.191is a plan view of the conductor layer1771in which the periodic shift PDX in the X direction is set to 1A, that is, 1/14 of the repetition period (periodic width FDX) in the X direction.

C inFIG.191is a plan view of the conductor layer1771in which the periodic shift PDX is set to 2A, that is, 2/14 of the repetition period (periodic width FDX) in the X direction.

D inFIG.191is a plan view of the conductor layer1771in which the periodic shift PDX is set to 3A, that is, 3/14 of the repetition period (periodic width FDX) in the X direction.

A inFIG.192is a plan view of the conductor layer1771in which the periodic shift PDX is set to 4A, that is, 4/14 of the repetition period (periodic width FDX) in the X direction.

B inFIG.192is a plan view of the conductor layer1771in which the periodic shift PDX is set to 5A, that is, 5/14 of the repetition period (periodic width FDX) in the X direction.

C inFIG.192is a plan view of the conductor layer1771in which the periodic shift PDX is set to 6A, that is, 6/14 of the repetition period (periodic width FDX) in the X direction.

D inFIG.192is a plan view of the conductor layer1771in which the periodic shift PDX is set to 7A, that is, 7/14 of the repetition period (periodic width FDX) in the X direction.

FIG.193is a graph illustrating theoretical values of the capacitive noise of the conductor layer1771in which the periodic shift PDX is set to various values as illustrated inFIGS.191and192.

Since the horizontal axis and the vertical axis of the graph inFIG.193are similar to those inFIG.169, the description thereof will be omitted. Note that the scale of the graph inFIG.193is also illustrated in accordance withFIG.169. Conditions for the Vdd applied voltage and Vss applied voltage are similar.

As illustrated inFIG.193, in a case where the periodic shift PDX is a predetermined value, the amount of change in the capacitive noise is zero and the absolute value of the capacitive noise is zero. More specifically, in a case where the periodic shift PDX is 1/14, 2/14, 3/14, 4/14, 5/14, or 6/14 of the repetition period in the X direction, the amount of change in the capacitive noise is zero, and the absolute value of the capacitive noise is zero.

In a case where the periodic shift PDX is 1/14 (=1A), 3/14 (=3A), or 5/14 (=5A) of the repetition period in the X direction, the amount of change in the capacitive noise is zero and is the absolute value of the capacitive noise in units of 14 rows.

In a case where the periodic shift PDX is set to 2/14 (2A), 4/14 (=4A), or 6/14 (=6A) of the repetition period in the X direction, the amount of change in the capacitive noise is zero and is the absolute value of the capacitive noise in units of 7 rows. The amount of change in the capacitive noise is zero and is the absolute value of the capacitive noise with a small number of rows even in the case where the periodic shift PDX is equal to a multiple integral of the conductor width WDX in addition to the case where the periodic shift PDX is equal to the conductor width WDX of the reticulated conductor1721. The amount of change in the capacitive noise is zero and is the absolute value of the capacitive noise with a small number of rows even in a case where the periodic shift PDX is equal to an integral multiple of the conductor width WDX, in the case where the multiple integral of the conductor width WDX does not match the periodic width FDX (=14A)+3 and the periodic width FDX (=14A)+4.

In a case of another periodic shift PDX, specifically, in a case where the periodic shift PDX is 7/14 of the repetition period in the X direction, the amount of change in the capacitive noise and the absolute value are not zero, but the change in the amount of change in the capacitive noise can be made smaller than a case where the periodic shift PDX is zero, that is, in a case of no periodic shift.

From the above, in the fourth shift configuration example including the relay conductor1762, the amount of change in the capacitive noise can be made zero under the following conditions.

First, as a premise, the periodic shift PDX is set to a value different from the periodic width FDX (=14A) in the X direction of the reticulated conductor1761.

In a case where the periodic shift PDX is 2A, that is, the periodic shift PDX is the same as the conductor width WDX in the X direction of the reticulated conductor1761, the amount of change in the capacitive noise and the absolute value become zero. Furthermore, in a case where the periodic shift PDX is 1A, 3A, 4A, 5A, and 6A, the amount of change in the capacitive noise and the absolute value become zero.

Conversely, in a case where the periodic shift PDX is different from the repetition period of 7/14 (=7A) in the X direction of the reticulated conductor1761, in other words, in a case where the periodic shift PDX is not the periodic width FDX (=14A)+2, the amount of change in the capacitive noise and the absolute value become zero.

FIG.194is a graph illustrating theoretical values of the capacitive noise in a case where the periodic shift PDX is set to various values in the conductor layer1771in which the relay conductor1762is omitted. Although illustration of the conductor layer1771from which the relay conductor1762is omitted is omitted, it corresponds to each of the conductor layers1771inFIGS.191and192from which the relay conductor1762is removed.

As illustrated inFIG.194, even in the absence of the relay conductor1762, the amount of shift by which the amount of change in the capacitive noise becomes zero is the same as the presence of the relay conductor1762. Note that the absolute value of the capacitive noise is not zero.

From the above, in the fourth shift configuration example not including the relay conductor1762, the amount of change in the capacitive noise can be made zero under the following conditions.

First, as a premise, the periodic shift PDX is set to a value different from the periodic width FDX (=14A) in the X direction of the reticulated conductor1761.

In a case where the periodic shift PDX is 2A, that is, the periodic shift PDX is the same as the conductor width WDX in the X direction of the reticulated conductor1761, the amount of change in the capacitive noise becomes zero. Furthermore, in a case where the periodic shift PDX is 1A, 3A, 4A, 5A, and 6A, the amount of change in the capacitive noise becomes zero.

Conversely, in a case where the periodic shift PDX is different from the repetition period of 7/14 (=7A) in the X direction of the reticulated conductor1761, in other words, in a case where the periodic shift PDX is not the periodic width FDX (=14A)+2, the amount of change in the capacitive noise becomes zero.

Fifth Shift Configuration Example of Reticulated Conductor

Next, an example in which the conductor width WDX in the X direction of the reticulated conductor is wide will be illustrated as a fifth shift configuration example.

FIG.195is a plan view for describing a conductor width and a gap width of a conductor layer as a fifth shift configuration example of the reticulated conductor.

The conductor layer1791inFIG.195is configured by a reticulated conductor1781and a relay conductor1782.

The reticulated conductor1781has the conductor width WDX set to 4A and the conductor width WDY set to 2A, where the arbitrary real number is A. The gap region of the reticulated conductor1781is formed by the gap width GDX set to 12A and the gap width GDY set to 16A.

The relay conductor1782arranged in the gap region of the reticulated conductor1781is a rectangle having the conductor width CDX set to 8A and the conductor width CDY set to 12A, and is a vertically long rectangle in which the conductor width CDY in the Y direction is larger than the conductor width CDX in the X direction (CDY>CDX). Both the first gap width GDX1 and the second gap width GDX2 in the X direction are set to 2A between the reticulated conductor1781and the relay conductor1782. Furthermore, both the first gap width GDY1 and the second gap width GDY2 in the Y direction are set to 2A.

Therefore, the periodic width FDX (=the conductor width WDX+the gap width GDX) corresponds to 16A and the periodic width FDY (=the conductor width WDY+the gap width GDY) corresponds to 18A when expressed using the arbitrary real number A. In the fifth shift configuration example, the real number A is equal to ¼ of the conductor width WDX in the X direction of the reticulated conductor1781.

The fifth shift configuration example also satisfies at least the above-described first condition of complete offset.

FIGS.196to198are plan views in which the periodic shift PDX is set to various values in the conductor layer1791as the fifth shift configuration example of the reticulated conductor.

A inFIG.196is a plan view of the conductor layer1791in which the periodic shift PDX is set to zero.

B inFIG.196is a plan view of the conductor layer1791in which the periodic shift PDX in the X direction is set to 1A, that is, 1/16 of the repetition period (periodic width FDX) in the X direction.

C inFIG.196is a plan view of the conductor layer1791in which the periodic shift PDX is set to 2A, that is, 2/16 of the repetition period (periodic width FDX) in the X direction.

A inFIG.197is a plan view of the conductor layer1791in which the periodic shift PDX is set to 3A, that is, 3/16 of the repetition period (periodic width FDX) in the X direction.

B inFIG.197is a plan view of the conductor layer1791in which the periodic shift PDX is set to 4A, that is, 4/16 of the repetition period (periodic width FDX) in the X direction.

C inFIG.197is a plan view of the conductor layer1791in which the periodic shift PDX is set to 5A, that is, 5/16 of the repetition period (periodic width FDX) in the X direction.

A inFIG.198is a plan view of the conductor layer1791in which the periodic shift PDX is set to 6A, that is, 6/16 of the repetition period (periodic width FDX) in the X direction.

B inFIG.198is a plan view of the conductor layer1791in which the periodic shift PDX is set to 7A, that is, 7/16 of the repetition period (periodic width FDX) in the X direction.

C inFIG.198is a plan view of the conductor layer1791in which the periodic shift PDX is set to 8A, that is, 8/16 of the repetition period (periodic width FDX) in the X direction.

FIG.199is a graph illustrating theoretical values of the capacitive noise of the conductor layer1771in which the periodic shift PDX is set to various values as illustrated inFIGS.196to198.

Since the horizontal axis and the vertical axis of the graph inFIG.199are similar to those inFIG.169, the description thereof will be omitted. Note that the scale of the graph inFIG.199is also illustrated in accordance withFIG.169. Conditions for the Vdd applied voltage and Vss applied voltage are similar.

As illustrated inFIG.199, in a case where the periodic shift PDX is a predetermined value, the amount of change in the capacitive noise is zero and the absolute value of the capacitive noise is zero. More specifically, in a case where the periodic shift PDX is 1/16 (=1A), 2/16 (=2A), 3/16 (=3A), 4/16 (=4A), 5/16 (=5A), 6/16 (=6A), or 7/16 (=7A) of the repetition period in the X direction, the amount of change in the capacitive noise is zero, and the absolute value of the capacitive noise is zero.

Conversely, in a case where the periodic shift PDX is different from the repetition period of 8/16 (=8A) in the X direction of the reticulated conductor1781, in other words, in a case where the periodic shift PDX is not the periodic width FDX (=16A)+2, the amount of change in the capacitive noise and the absolute value become zero.

In a case where the periodic shift PDX is 1/16 (=1A), 3/16 (=3A), 5/16 (=5A), or 7/16 (=7A) of the repetition period in the X direction, the amount of change in the capacitive noise is zero and is the absolute value of the capacitive noise in units of 16 rows.

In a case where the periodic shift PDX is set to 2/16 (=2A) or 6/16 (=6A) of the repetition period in the X direction, the amount of change in the capacitive noise is zero and is the absolute value of the capacitive noise in units of 8 rows.

In a case where the periodic shift PDX is set to 4/16 (4A) of the repetition period in the X direction, the amount of change in the capacitive noise is zero and is the absolute value of the capacitive noise in units of 4 rows.

In a case of another periodic shift PDX, specifically, in a case where the periodic shift PDX is 8/16 of the repetition period in the X direction, the amount of change in the capacitive noise and the absolute value are not zero, but the change in the amount of change in the capacitive noise can be made smaller than a case where the periodic shift PDX is zero, that is, in a case of no periodic shift.

From the above, in the fifth shift configuration example including the relay conductor1762, the amount of change in the capacitive noise can be made zero under the following conditions.

First, as a premise, the periodic shift PDX is set to a value different from the periodic width FDX (=16A) in the X direction of the reticulated conductor1781.

In a case where the periodic shift PDX is 4A, that is, the periodic shift PDX is the same as the conductor width WDX in the X direction of the reticulated conductor1781, the amount of change in the capacitive noise and the absolute value become zero.

Furthermore, in a case where the periodic shift PDX is 2A and 6A, the amount of change in the capacitive noise and the absolute value become zero. In a case where the periodic shift PDX is 2A, the periodic shift PDX is equal to one time the half of the conductor width WDX. In a case where the periodic shift PDX is 6A, the periodic shift PDX is equal to three times the half of the conductor width WDX. Furthermore, in a case where the periodic shift PDX is 4A, the periodic shift PDX is equal to twice the half of the conductor width WDX.

In the case where the conductor width WDX in the X direction of the reticulated conductor is set to be narrow as in the above-described fourth shift configuration example, the amount of change in the capacitive noise has become zero and been the absolute value of the capacitive noise in the case where the periodic shift PDX is equal to the multiple integral of the conductor width WDX of the reticulated conductor1721.

In contrast, in the case where the conductor width WDX in the X direction of the reticulated conductor is set to be wide, the amount of change in the capacitive noise has become zero and been the absolute value of the capacitive noise in the case where the periodic shift PDX is equal to the multiple integral of half of the conductor width WDX of the reticulated conductor1721.

In this way, in the case where the periodic shift PDX is equal to not only an integral multiple of the conductor width WDX but also an integral multiple of half the conductor width WDX, the amount of change in the capacitive noise and the absolute value may become zero.

FIG.200is a graph illustrating theoretical values of the capacitive noise in a case where the periodic shift PDX is set to various values in the conductor layer1791in which the relay conductor1782is omitted. Although illustration of the conductor layer1791from which the relay conductor1782is omitted is omitted, it corresponds to each of the conductor layers1791inFIGS.196to198from which the relay conductor1782is removed.

As illustrated inFIG.200, even in the absence of the relay conductor1782, the amount of shift by which the amount of change in the capacitive noise becomes zero is the same as the presence of the relay conductor1782. Note that the absolute value of the capacitive noise is not zero.

Sixth Shift Configuration Example of Reticulated Conductor

In the first to fifth shift configuration examples, the examples in which the gap width GDX is larger than the conductor width WDX (the gap width GDX>the conductor width WDX) when focusing on the relationship between the conductor width WDX in the X direction of the reticulated conductor and the gap width GDX have been described.

In the next sixth shift configuration example, an example in which the gap width GDX is smaller than the conductor width WDX (the gap width GDX<the conductor width WDX) will be described.

FIG.201is a plan view for describing a conductor width and a gap width of a conductor layer as a sixth shift configuration example of the reticulated conductor.

The conductor layer1811inFIG.201is configured by a reticulated conductor1801and a relay conductor1802.

The reticulated conductor1801has the conductor width WDX set to 6A and the conductor width WDY set to 6A, where the arbitrary real number is A. The gap region of the reticulated conductor1801is formed by the gap width GDX set to 4A and the gap width GDY set to 4A. Therefore, the conductor width WDX (=6A) is larger than the gap width GDX (=4A).

The relay conductor1802arranged in the gap region of the reticulated conductor1801is a rectangle having the conductor width CDX set to 2A and the conductor width CDY set to 2A, and is a square in which the conductor width CDX in the X direction and the conductor width CDY in the Y direction are the same (CDY=CDX). Both the first gap width GDX1 and the second gap width GDX2 in the X direction are set to 1A between the reticulated conductor1801and the relay conductor1802. Furthermore, both the first gap width GDY1 and the second gap width GDY2 in the Y direction are set to 1A.

Therefore, the periodic width FDX (=the conductor width WDX+the gap width GDX) corresponds to 10A and the periodic width FDY (=the conductor width WDY+the gap width GDY) corresponds to 10A when expressed using the arbitrary real number A.

In the sixth shift configuration example, when comparing the conductive area of the reticulated conductor1801with the conductive area of the relay conductor1802within a predetermined range, the conductive area of the reticulated conductor1801is larger, and the above-described first condition of complete offset is not satisfied.

FIGS.202and203are plan views in which the periodic shift PDX is set to various values in the conductor layer1811as the sixth shift configuration example of the reticulated conductor.

A inFIG.202is a plan view of the conductor layer1811in which the periodic shift PDX is set to zero.

B inFIG.202is a plan view of the conductor layer1811in which the periodic shift PDX in the X direction is set to 1A, that is, 1/10 of the repetition period (periodic width FDX) in the X direction.

C inFIG.202is a plan view of the conductor layer1811in which the periodic shift PDX is set to 2A, that is, 2/10 of the repetition period (periodic width FDX) in the X direction.

A inFIG.203is a plan view of the conductor layer1811in which the periodic shift PDX is set to 3A, that is, 3/10 of the repetition period (periodic width FDX) in the X direction.

B inFIG.203is a plan view of the conductor layer1811in which the periodic shift PDX is set to 4A, that is, 4/10 of the repetition period (periodic width FDX) in the X direction.

C inFIG.203is a plan view of the conductor layer1811in which the periodic shift PDX is set to 5A, that is, 5/10 of the repetition period (periodic width FDX) in the X direction.

FIG.204is a graph illustrating theoretical values of the capacitive noise of the conductor layer1811in which the periodic shift PDX is set to various values as illustrated inFIGS.202and203.

Since the horizontal axis and the vertical axis of the graph inFIG.204are similar to those inFIG.169, the description thereof will be omitted. Note that the scale of the graph inFIG.204is also illustrated in accordance withFIG.169. Conditions for the Vdd applied voltage and Vss applied voltage are similar.

The amount of change in the capacitive noise becomes zero in the case where the periodic shift PDX is a predetermined value, as illustrated inFIG.204. More specifically, in a case where the periodic shift PDX is 1/10 (=1A), 2/10 (=2A), 3/10 (=3A), or 4/10 (=4A) of the repetition period in the X direction, the amount of change in the capacitive noise is zero. Note that the absolute value of the capacitive noise is not zero.

Conversely, in a case where the periodic shift PDX is different from the repetition period of 5/10 (=5A) in the X direction of the reticulated conductor1801, in other words, in a case where the periodic shift PDX is not the periodic width FDX (=10A)+2, the amount of change in the capacitive noise becomes zero.

In a case where the periodic shift PDX is set to 1/10 (1A) or 3/10 (=3A) of the repetition period in the X direction, the amount of change in the capacitive noise becomes zero in units of ten rows.

In a case where the periodic shift PDX is set to 2/10 (2A) or 4/10 (=4A) of the repetition period in the X direction, the amount of change in the capacitive noise becomes zero in units of five rows.

In a case of another periodic shift PDX, specifically, in a case where the periodic shift PDX is 5/10 of the repetition period in the X direction, the amount of change in the capacitive noise is not zero, but the change in the amount of change in the capacitive noise can be made smaller than a case where the periodic shift PDX is zero, that is, in a case of no periodic shift.

From the above, in the sixth shift configuration example including the relay conductor1802, the amount of change in the capacitive noise can be made zero under the following conditions.

First, as a premise, the periodic shift PDX is set to a value different from the periodic width FDX (=10A) in the X direction of the reticulated conductor1801.

In a case where the periodic shift PDX is 4A, that is, the periodic shift PDX is the same as the gap width GDX in the X direction of the reticulated conductor1801, the amount of change in the capacitive noise becomes zero. Furthermore, in a case where the periodic shift PDX is 1A, 2A, and 3A, the amount of change in the capacitive noise becomes zero.

Although not illustrated in the graph inFIG.204, in a case where the periodic shift PDX is 8A, which is twice the gap width GDX (=4A), the periodic width FDX is 10A, and 8/10=(10−2)/10, and thus the case becomes equivalent to the case where the periodic shift PDX is 2A. Therefore, the amount of change in the capacitive noise becomes zero. Furthermore, in a case where the periodic shift PDX is 12A, which is three times the gap width GDX (=4A), the periodic width FDX is 10A, and 12/10=(10+2)/10, and thus the case becomes equivalent to the case where the periodic shift PDX is 2A. Therefore, the amount of change in the capacitive noise becomes zero.

Therefore, in the conductor layer1811having the reticulated conductor1801in which the gap width GDX is larger than the conductor width WDX, the amount of change in the capacitive noise can be made zero in the case of an integral multiple of the gap width GDX. Note that the amount of change in the capacitive noise becomes zero even in the case where the periodic shift PDX is 1A or 3A, so the case is not limited to an integral multiple of the gap width GDX.

FIG.205is a graph illustrating theoretical values of the capacitive noise in a case where the periodic shift PDX is set to various values in the conductor layer1811in which the relay conductor1802is omitted. Although illustration of the conductor layer1811from which the relay conductor1802is omitted is omitted, it corresponds to each of the conductor layers1811inFIGS.202and203from which the relay conductor1802is removed.

As illustrated inFIG.205, even in the absence of the relay conductor1802, the amount of shift by which the amount of change in the capacitive noise becomes zero is the same as the presence of the relay conductor1802. Note that the absolute value of the capacitive noise is not zero.

Seventh Shift Configuration Example of Reticulated Conductor

Next, an example in which the conductor width WDX in the X direction of the reticulated conductor and the gap width GDX are equal (the conductor width WDX=the gap width GDX) will be illustrated as a seventh shift configuration example.

FIG.206is a plan view for describing a conductor width and a gap width of a conductor layer as a seventh shift configuration example of the reticulated conductor.

The conductor layer1831inFIG.206is configured by a reticulated conductor1821and a relay conductor1822.

The reticulated conductor1821has the conductor width WDX set to 6A and the conductor width WDY set to 6A, where the arbitrary real number is A. The gap region of the reticulated conductor1821is formed by the gap width GDX set to 6A and the gap width GDY set to 6A. Therefore, the conductor width WDX (=6A) and the gap width GDX (=6A) are equal.

The relay conductor1822arranged in the gap region of the reticulated conductor1821is a rectangle having the conductor width CDX set to 2A and the conductor width CDY set to 2A, and is a square in which the conductor width CDX in the X direction and the conductor width CDY in the Y direction are the same (CDY=CDX). Both the first gap width GDX1 and the second gap width GDX2 in the X direction are set to 2A between the reticulated conductor1821and the relay conductor1822. Furthermore, both the first gap width GDY1 and the second gap width GDY2 in the Y direction are set to 2A.

Therefore, the periodic width FDX (=the conductor width WDX+the gap width GDX) corresponds to 12A and the periodic width FDY (=the conductor width WDY+the gap width GDY) corresponds to 12A when expressed using the arbitrary real number A.

In the seventh shift configuration example, when comparing the conductive area of the reticulated conductor1801with the conductive area of the relay conductor1802within a predetermined range, the conductive area of the reticulated conductor1801is larger, and the above-described first condition of complete offset is not satisfied.

FIGS.207and208are plan views in which the periodic shift PDX is set to various values in the conductor layer1831as the seventh shift configuration example of the reticulated conductor.

A inFIG.207is a plan view of the conductor layer1831in which the periodic shift PDX is set to zero.

B inFIG.207is a plan view of the conductor layer1831in which the periodic shift PDX in the X direction is set to 1A, that is, 1/12 of the repetition period (periodic width FDX) in the X direction.

C inFIG.207is a plan view of the conductor layer1831in which the periodic shift PDX is set to 2A, that is, 2/12 of the repetition period (periodic width FDX) in the X direction.

D inFIG.207is a plan view of the conductor layer1831in which the periodic shift PDX is set to 3A, that is, 3/12 of the repetition period (periodic width FDX) in the X direction.

A inFIG.208is a plan view of the conductor layer1831in which the periodic shift PDX is set to 4A, that is, 4/12 of the repetition period (periodic width FDX) in the X direction.

B inFIG.208is a plan view of the conductor layer1831in which the periodic shift PDX is set to 5A, that is, 5/12 of the repetition period (periodic width FDX) in the X direction.

C inFIG.208is a plan view of the conductor layer1831in which the periodic shift PDX is set to 6A, that is, 6/12 of the repetition period (periodic width FDX) in the X direction.

FIG.209is a graph illustrating theoretical values of the capacitive noise of the conductor layer1831in which the periodic shift PDX is set to various values as illustrated inFIGS.207and208.

Since the horizontal axis and the vertical axis of the graph inFIG.209are similar to those inFIG.169, the description thereof will be omitted. Note that the scale of the graph inFIG.209is also illustrated in accordance withFIG.169. Conditions for the Vdd applied voltage and Vss applied voltage are similar.

The amount of change in the capacitive noise becomes zero in the case where the periodic shift PDX is a predetermined value, as illustrated inFIG.209. More specifically, in a case where the periodic shift PDX is set to 1/12 (=1A), 2/12 (=2A), or 5/12 (=5A) of the repetition period in the X direction, the amount of change in the capacitive noise becomes zero. Note that the absolute value of the capacitive noise is not zero.

Conversely, in a case where the periodic shift PDX is different from the repetition period of 3/12 (=3A), 4/12 (=4A), and 6/12 (=6A) in the X direction of the reticulated conductor1821, in other words, in a case where the periodic shift PDX is not the periodic width FDX (=12A)+4, the periodic width FDX (=12A)+3, and the periodic width FDX (=12A)+2, the amount of change in the capacitive noise and the absolute value become zero.

In a case where the periodic shift PDX is set to 1/12 (1A) or 5/12 (=5A) of the repetition period in the X direction, the amount of change in the capacitive noise becomes zero in units of twelve rows.

In a case where the periodic shift PDX is set to 2/12 (2A) of the repetition period in the X direction, the amount of change in the capacitive noise becomes zero in units of six rows. In the reticulated conductor1821in which the conductor width WDX in the X direction and the gap width GDX are equal, the amount of change in the capacitive noise can be made zero with a small number of rows in the case where the periodic shift PDX is the same as the conductor width CDX (=2A) in the X direction of the relay conductor1822. In the case where the periodic shift PDX is the same as the conductor width WDX (=6A) in the X direction of the reticulated conductor1821, the amount of change in the capacitive noise does not become zero.

In a case where the periodic shift PDX is set to 3/12 (3A), 4/12 (=4A), or 6/12 (=6A) of the repetition period in the X direction of the reticulated conductor1821, the amount of change in the capacitive noise is not zero, but the change in the amount of change in the capacitive noise can be made smaller than a case where the periodic shift PDX is zero, that is, in a case of no periodic shift.

From the above, in the seventh shift configuration example including the relay conductor1822, the amount of change in the capacitive noise can be made zero under the following conditions.

First, as a premise, the periodic shift PDX is set to a value different from the periodic width FDX (=12A) in the X direction of the reticulated conductor1821.

In the case where the periodic shift PDX is 2A, that is, the periodic shift PDX is the same as the conductor width CDX in the X direction of the relay conductor1822, the amount of change in the capacitive noise becomes zero. Furthermore, in a case where the periodic shift PDX is 1A and 5A, the amount of change in the capacitive noise becomes zero.

In a case where the periodic shift PDX is different from the repetition period of 3/12 (=3A) in the X direction of the reticulated conductor1821, in other words, in a case where the periodic shift PDX is not the periodic width FDX (=12A)+4, the amount of change in the capacitive noise becomes zero.

In a case where the periodic shift PDX is different from the repetition period of 4/12 (=4A) in the X direction of the reticulated conductor1821, in other words, in a case where the periodic shift PDX is not the periodic width FDX (=12A)+3, the amount of change in the capacitive noise becomes zero.

In a case where the periodic shift PDX is different from the repetition period of 6/12 (=6A) in the X direction of the reticulated conductor1821, in other words, in a case where the periodic shift PDX is not the periodic width FDX (=12A)+2, the amount of change in the capacitive noise becomes zero.

FIG.210is a graph illustrating theoretical values of the capacitive noise in a case where the periodic shift PDX is set to various values in the conductor layer1831in which the relay conductor1822is omitted. Although illustration of the conductor layer1831from which the relay conductor1822is omitted is omitted, it corresponds to each of the conductor layers1831inFIGS.207and208from which the relay conductor1822is removed.

Even in the absence of the relay conductor1822, the amount of change in the capacitive noise becomes zero in the case where the periodic shift PDX is a predetermined value, as illustrated inFIG.210. Note that the amount of shift at which the amount of change in the capacitive noise becomes zero is different from the case where the relay conductor1822is present.

Specifically, in a case where the periodic shift PDX is set to 1/12, 2/12, 3/12, 5/12, or 6/12 of the repetition period in the X direction, the amount of change in the capacitive noise is zero.

In a case where the periodic shift PDX is set to 3/12 (3A) of the repetition period in the X direction, the amount of change in the capacitive noise becomes zero in units of four rows. In a case where the periodic shift PDX is set to 2/12 (=2A) of the repetition period in the X direction, the amount of change in the capacitive noise becomes zero in units of six rows.

In a case where the periodic shift PDX is set to 6/12 (6A) of the repetition period in the X direction, the amount of change in the capacitive noise becomes zero in units of two rows.

From the above, in the seventh shift configuration example not including the relay conductor1822, the amount of change in the capacitive noise can be made zero under the following conditions.

First, as a premise, the periodic shift PDX is set to a value different from the periodic width FDX (=12A) in the X direction of the reticulated conductor1821.

In a case where the periodic shift PDX is 1/12 (=1A), 2/12 (=2A), 3/12 (=3A), 5/12 (=5A), or 6/12 (=6A) of the repetition period in the X direction of the reticulated conductor1821, the amount of change in the capacitive noise becomes zero. 1/12 (=1A), 2/12 (=2A), 3/12 (=3A), and 6/12 (=6A) of the repetition period in the X direction of the reticulated conductor1821can be respectively rephrased as the periodic shift PDX being the periodic width FDX (=12A)+12, the periodic width FDX (=12A)+6, the periodic width FDX (=12A)+4, and the periodic width FDX (=12A)+2. Therefore, in a case where the periodic shift PDX is the periodic width FDX an even integer, the amount of change in the capacitive noise becomes zero. In the case where the periodic shift PDX is the periodic width FDX (=12A)+2, which is the case where the periodic shift PDX is 6/12 (=6A) of the repetition period in the X direction, the amount of change in the capacitive noise becomes zero with a smallest number of rows, which is favorable but the configuration is not limited thereto.

Furthermore, in a case where the periodic shift PDX is different from the repetition period of 4/12 (=4A) in the X direction of the reticulated conductor1821, in other words, in a case where the periodic shift PDX is not the periodic width FDX (=12A)+3, the amount of change in the capacitive noise becomes zero.

Therefore, in the seventh shift configuration example, the condition of the periodic shift PDX of when the amount of change in the capacitive noise becomes zero is different between the presence of the relay conductor1822and the absence of the relay conductor1822.

In the case where an even integral multiple of the periodic shift PDX matches the periodic width FDX according to the shape relationship between the conductor part and the gap region of the reticulated conductor1821, the capacitive noise is evenly distributed. Therefore, the amount of change in the capacitive noise can be made zero in the absence of the relay conductor1822.

Modification of Shift Configuration Example of Reticulated Conductor

A configuration in which the following modification is made for at least one of the first to seventh shift configuration examples of the reticulated conductor is also possible.

For example, the conductor width WDY in the Y direction of the reticulated conductor may be made larger than the gap width GDY (the conductor width WDY>the gap width GDY), or the conductor width WDX in the X direction may be made larger than the gap width GDX (the conductor width WDX>the gap width GDX). In this case, it is advantageous in terms of light-shielding property and conductor occupancy.

On the contrary, for example, the conductor width WDY in the Y direction of the reticulated conductor may be made the same as or smaller than the gap width GDY (the conductor width WDY≤the gap width GDY), or the conductor width WDX in the X direction may be made the same or smaller than the gap width GDX (the conductor width WDX≤the gap width GDX). In this case, it is advantageous in terms of offset property the capacitive noise.

In the above-described shift configuration examples of the reticulated conductor, the examples of shifting the reticulated conductor in the positive direction of the X-axis have been described, but the reticulated conductor may be shifted in the negative direction of the X axis. Furthermore, the shift in the positive direction and the shift in the negative direction of the X axis may be combined, such as alternately arranging the shift of one or a plurality of rows in the positive direction of the X axis and the shift of one or a plurality of rows in the negative direction of the X axis.

The conductor layer having the above-described shift configuration of the reticulated conductor is particularly suitable, but not limited, in a case of a conductor layer close to a Victim conductor. The conductor layer having the shift configuration of the reticulated conductor has been described as an example applicable to the reticulated conductor of the conductor layer A (wiring layer165A) or the conductor layer B (wiring layer165B), but is also applicable to a conductor layer other than the conductor layer A or B. For example, the conductor layer may be applied to the conductor layer C (wiring layer165C) or may be applied to any conductor layer in a circuit board, a semiconductor substrate, or an electronic device. Furthermore, two or more conductor layers having the shift configuration of the reticulated conductor may be provided, and in that case, it is desirable that the periodic shift amounts in the respective conductor layers of the two layers are the same or substantially the same from the viewpoint of the inductive noise. However, the periodic shift amounts may be made different from each other. Furthermore, two or more conductor layers having the reticulated conductor are provided, and the periodic shift may be provided in the reticulated conductor of some conductor layers and the periodic shift may not be provided in the reticulated conductor of the other conductor layers. Furthermore, a plurality of reticulated conductors having different periodic shift amounts may be provided in one conductor layer, and both a reticulated conductor having the periodic shift and a reticulated conductor having no periodic shift may be provided.

The wiring period, wiring width, wiring gap width, and wiring periodic shift of the wiring as the reticulated conductor or the relay conductor may have a structure modulated depending on the position. For example, the wiring period, wiring width, gap width, and periodic shift may have a structure that becomes gradually larger according to the distance in the X direction or the Y direction, or may have a structure that becomes gradually smaller according to the distance in the X direction or the Y direction. Furthermore, a structure in which the structure that becomes gradually larger according to the distance in the X direction or the Y direction and the structure that becomes gradually smaller according to the distance in the X direction or the Y direction are combined or alternately arranged.

At least a part of the reticulated conductor or the relay conductor may be separated into a plurality of conductors, or may be a shape in which a plurality of divided but unseparated shapes is coupled, as in B inFIG.178. Furthermore, at least a part of the reticulated conductor may be cut and separated.

In the above-described shift configuration example of the reticulated conductor, the reticulated conductor is the wiring (Vss wiring) connected to the GND or the negative power supply, and the relay conductor is the wiring (Vdd wiring) connected to the positive power supply. Furthermore, an example in which the absolute values of the Vdd applied voltage and the Vss applied voltage are the same has been described.

However, the Vdd applied voltage and the Vss applied voltage may be opposite. That is, the reticulated conductor may be the wiring (Vdd wiring) connected to the positive power supply, and the relay conductor may be the wiring (Vss wiring) connected to the GND or the negative power supply. Furthermore, the absolute values of the Vdd applied voltage and the Vss applied voltage may not be the same. For example, the Vdd applied voltage may be a positive power supply (for example, +1 V) and the Vss applied voltage may be the GND (0 V).

The voltage applied to the reticulated conductor and the voltage applied to the relay conductor are not limited to the above examples, and may be different power sources, and may be any two types of power supplies. In this case, it is desirable, but not limited to, that the polarities of the two types of power supplies are different from each other.

The plane arrangement of the conductor layer having the shift configuration of the reticulated conductor may be reversed in the X direction or in the Y direction. Furthermore, the plane arrangement may be rotated clockwise by a predetermined angle (for example, 90 degrees) or counterclockwise by a predetermined angle (for example, −90 degrees).

In the present disclosure, the effect of improving the capacitive noise by the periodic shift of the reticulated conductor has been illustrated, but the reticulated conductor and the relay conductor not having the periodic shift are not excluded. As described above, the conductor layer having no periodic shift and both the presence and absence of the relay conductor can be applied as a reticulated conductor of the conductor layer A (wiring layer165A) or the conductor layer B (wiring layer165B).

The relay conductor may have any shape such as a circular shape, a polygonal shape, a symmetrical shape, an asymmetrical shape, a star shape, a radial shape, or a complicated shape. Furthermore, in the above-described shift configuration of the reticulated conductor, the conductor used as the relay conductor may be a conductor that does not electrically relay between other conductor layers, and may be non-reticulated conductor arranged in the gap region of the reticulated conductor. The non-reticulated conductor including the relay conductor may be arranged in all of the gap regions of the reticulated conductor, or may be arranged only in a predetermined part of the gap region.

15. Configuration Examples of Three-Power Supply

Next, a configuration example of the conductor layer (wiring layer165) in a case where the solid-state imaging device100has a three-power supply will be described.

In the above-described various configuration examples, in either case of the two layers of the conductor layers A and B (wiring layers165A and165B) or the three layers of the conductor layers A to C (wiring layers165A to165C), the power supply to be supplied to the wiring layer is the two power supplies of Vdd as a positive power supply, for example, and Vss as a GND or a negative power supply, for example.

However, the solid-state imaging device100may be controlled by, for example, a three-power supply of a first power supply Vdd, a second power supply Vss1, and a third power supply Vss2. Note that, hereinafter, in the case of the three-power supply, the power supplies are referred to as the first power supply Vdd, the second power supply Vss1, and the third power supply Vss2, but in the case of a two-power supply, the power supplies are referred to as a first power supply Vdd and a second power supply Vss.

FIG.211is conceptual diagrams in cases where the solid-state imaging device100adopts a two-power supply and a three-power supply.

A ofFIG.211is a conceptual diagram in the case where the solid-state imaging device100described so far is controlled by the two-power supply.

The power supply Vdd is supplied to a circuit block2001included in the solid-state imaging device100via wiring2011, and the power supply Vss is supplied to the circuit block2001via wiring2012. The circuit block2001is a circuit block in which the active element group167is formed, and corresponds to, for example, the circuit blocks202to204inFIG.7. The wiring2011and the wiring2012correspond to the wiring (conductors) included in the conductor layers A and B in the case of two layers and the conductor layers A to C in the case of three layers in the above-described various configuration examples. However, the wiring2011and the wiring2012may include conductors of other conductor layers, and may include conductors having a configuration different from the wiring (conductors) described in the above-described various configuration examples.

B ofFIG.211is a conceptual diagram a first configuration example in the case where the solid-state imaging device100is controlled by the three-power supply.

In the first configuration example controlled by the three-power supply, the first power supply Vdd is supplied to the circuit block2001via wiring2021, the second power supply Vss1is supplied to the circuit block2001via wiring2022, and the third power supply Vss2is supplied to the circuit block2001via wiring2023. The second power supply Vss1and the third power supply Vss2may be configured to be constantly supplied to the circuit block2001via the wiring2022and2023, or the circuit block2001may internally control the connection with the wiring2022and2023and select one of the second power supply Vss1and the third power supply Vss2according to an operation mode or the like.

C ofFIG.211is a conceptual diagram a second configuration example in the case where the solid-state imaging device100is controlled by the three-power supply.

In the second configuration example of controlling the solid-state imaging device100by the three-power supply, a selection unit2002is separately provided from the circuit block2001. The selection unit2002selects at least one of the second power supply Vss1or the third power supply Vss2according to the operation mode or the like under the control of the circuit block2001. In other words, the selection unit2002selects at least one of a first path including the first power supply Vdd, the wiring2021, the circuit block2001, the wiring2022, and the second power supply Vss1, or a second path including the first power supply Vdd, the wiring2021, the circuit block2001, the wiring2023, and the third power supply Vss2.

D ofFIG.211is a conceptual diagram of a third configuration example in the case where the solid-state imaging device100is controlled by the three-power supply.

The third configuration example of controlling the solid-state imaging device100by the three-power supply is a configuration in which a control unit2003for controlling selection of the second power supply Vss1and the third power supply Vss2is separately provided from the circuit block2001. The control unit2003determines the selection of the second power supply Vss1and the third power supply Vss2and instructs the selection unit2002, and the selection unit2002selects at least one of the second power supply Vss1or the third power supply Vss2on the basis of the instruction of the control unit2003.

Each of the configurations of the three-power supply in B to D ofFIG.211is the configuration in which the circuit block2001is electrically connected to the first power supply Vdd via the wiring2021, electrically connected to the second power supply Vss1via the wiring2022, and electrically connected to the third power supply Vss2via the wiring2023.

Note that, in the case of selecting and operating the second power supply Vss1and the third power supply Vss2in each configuration of the three-power supply in B to D ofFIG.211, either one of the second power supply Vss1and the third power supply Vss2may be selectively selected, or the second power supply Vss1and the third power supply Vss2may be selected at the same time.

Regarding the magnitude relationship of power supply voltages of the three-power supply, the first power supply Vdd is larger than the second power supply Vss1, and the first power supply Vdd is larger than the third power supply Vss2. The second power supply Vss1and the third power supply Vss2are the same, or the second power supply Vss1is larger than the third power supply Vss2. That is, the first power supply Vdd>the second power supply Vss1, the first power supply Vdd>the third power supply Vss2, and the second power supply Vss1≥the third power supply Vss2. Total power consumption when the solid-state imaging device100selects the second power supply Vss1is equal to or larger than total power consumption when the solid-state imaging device100selects the third power supply Vss2. Furthermore, a total current amount when the solid-state imaging device100selects the second power supply Vss1is equal to or larger than a total current amount when the solid-state imaging device100selects the third power supply Vss2. In these cases, “a total number of pads (Vdd pads) to which the first power supply Vdd is electrically connected≥a total number of pads (Vss2pads) to which the third power supply Vss2is electrically connected”, and “a total number of pads (Vss1pads) to which the second power supply Vss1is electrically connected≥a total number of pads (Vss2pads) to which the third power supply Vss2is electrically connected” can be obtained. That is, since restrictions due to the total power consumption and the total current amount are small, the total number of pads to which the third power supply Vss2is electrically connected can be made smaller than the total number of pads to which the first power supply Vdd or the second power supply Vss1is electrically connected. Moreover, it may be set that “the total number of pads to which the first power supply Vdd is electrically connected z the total number of pads to which the second power supply Vss1is electrically connected”. Note that as for the pad arrangement in the case of the three-power supply, the pad arrangement example in the above-described case of the two-power supply may be applied, so details are omitted. For example, the Vdd pads, Vss1pads, and Vss2pads may be alternately or mirror-symmetrically arranged, as described above, on any one side, two sides, three sides, or four sides.

The first power supply Vdd is, for example, a power supply of 0 V or higher, and may have a fixed voltage or a variable voltage. The second power supply Vss1and the third power supply Vss2are, for example, a GND or a negative power supply. More specifically, for example, a configuration in which the second power supply Vss1is the GND (grounded) and the third power supply Vss2is a negative power supply, or a configuration in which the second power supply Vss1is a first negative power supply voltage and the third power supply Vss2is a second negative power supply voltage different from the first negative power supply voltage can be adopted. In the present embodiment, the first power supply Vdd, the second power supply Vss1, and the third power supply Vss2distinguish power supply voltage levels supplied to the circuit block2001, and include the GND (ground). Furthermore, the second power supply Vss1and the third power supply Vss2may both be the GND or negative power supplies having the same voltage. In other words, the first power supply Vdd, the second power supply Vss1, and the third power supply Vss2may be a two-system three-power supply in which the second power supply Vss1and the third power supply Vss2are the same power supply voltage, or may be a three-system three-power supply in which the second power supply Vss1and the third power supply Vss2are different power supply voltages.

Note that, hereinafter, the conductor connected to the first power supply Vdd is also referred to as a Vdd conductor, the conductor connected to the second power supply Vss1is also referred to as a Vss1conductor, and the conductor connected to the third power supply Vss2is also referred to as a Vss2conductor.

Furthermore, as a combination of the three-power supply, a configuration in which two power supply voltages of 0 or higher, such as a first power supply Vdd1, a second power supply Vdd2, and a third power supply Vss, can be adopted. The configuration of the first power supply Vdd1, the second power supply Vdd2, and the third power supply Vss is applicable by appropriately replacing the first power supply Vdd, the second power supply Vss1, and the third power supply Vss2to be described below, so description will be omitted. In the case of the configuration of the first power supply Vdd1, the second power supply Vdd2, and the third power supply Vss, the first power supply Vdd1and/or the second power supply Vdd2is selectively selected or are selected at the same time, and the third power supply Vss is a commonly used element.

First Configuration Example of Three-Power Supply

Hereinafter, a configuration example of the wiring layer in the case where the solid-state imaging device100is controlled by the three-power supply will be described. First, a configuration example of arranging the wiring of the three-power supply in the two wiring layers (wiring layers165A and165B) of the plurality of wiring layers forming the multilayer wiring layer163will be described. Next, a configuration example of arranging the wiring of the three-power supply in the three wiring layers (wiring layers165A to165C) will be described. The wiring layer165A will be referred to as the conductor layer A, the wiring layer165B will be referred to as the conductor layer B, and the wiring layer165C will be referred to as the conductor layer C, similarly to the above-described example, and description will be given.

FIGS.212and213illustrate a first configuration example of the three-power supply.

In both the coordinate systems inFIGS.212and213, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

A ofFIG.212is a plan view of the conductor layer A (wiring layer165A), and B ofFIG.212is a plan view of the conductor layer B (wiring layer165B). Note thatFIG.212may be considered as the entire region of each conductor layer or may be considered as a partial region.

The conductor layer A in A inFIG.212is configured by arranging three linear conductors2101to2103, which are long in the Y direction, in the X direction in a predetermined order, and periodically arranging the three linear conductors2101to2103in the X direction.

The linear conductor2101is wiring (Vdd wiring) connected to the first power supply Vdd. The linear conductor2102is wiring (Vss1wiring) connected to the second power supply Vss1. The linear conductor2103is wiring (Vss2wiring) connected to the third power supply Vss2.

Therefore, in A inFIG.212, the three linear conductors2101to2103are arranged in the positive direction of the X-axis in the order of the Vdd wiring, Vss2wiring, and Vss1wiring, but the order of arranging the three linear conductors2101to2103is not limited to this example and can be any order.

The linear conductor2101has a conductor width WXAD in the X direction, the linear conductor2102has a conductor width WXAS1 in the X direction, and the linear conductor2103has a conductor width WXAS2 in the X direction. The conductor width WXAD of the linear conductor2101, the conductor width WXAS1 of the linear conductor2102, and the conductor width WXAS2 of the linear conductor2103are, for example, the same (the conductor width WXAD=the conductor width WXAS1=the conductor width WXAS2). Furthermore, a gap with the gap width GXA is formed between two adjacent linear conductors of the linear conductors2101to2103.

The linear conductor2101is periodically arranged in the X direction with a conductor period FXAD, and the linear conductor2102is periodically arranged in the X direction with a conductor period FXAS1. Similarly, the linear conductor2103is periodically arranged in the X direction with a conductor period FXAS2. The conductor period FXAD, the conductor period FXAS1, and the conductor period FXAS2 are, for example, the same (the conductor period FXAD=the conductor period FXAS1=the conductor period FXAS2).

Therefore, in a rectangular region within a predetermined range of the conductor layer A, the sum of the conductor widths WXAD in the X direction of the linear conductors2101connected to the first power supply Vdd, the sum of the conductor widths WXAS1 in the X direction of the linear conductors2102connected to the second power supply Vss1, and the sum of the conductor widths WXAS2 in the X direction of the linear conductors2103connected to the third power supply Vss2are the same. Furthermore, in a rectangular region within a predetermined range of the conductor layer A, the conductive area of the linear conductor2101connected to the first power supply Vdd, the conductive area of the linear conductor2102connected to the second power supply Vss1, and the conductive area of the linear conductor2103connected to the third power supply Vss2are the same.

The conductor layer B in B inFIG.212is configured by arranging, in the X direction, three linear conductors2111to2113long in the Y direction in a predetermined order, and periodically arranging the three linear conductors2111to2113in the X direction.

The linear conductor2111is wiring (Vdd wiring) connected to the first power supply Vdd. The linear conductor2112is wiring (Vss1wiring) connected to the second power supply Vss1. The linear conductor2113is wiring (Vss2wiring) connected to the third power supply Vss2.

Therefore, in B inFIG.212, the three linear conductors2111to2113are arranged in the positive direction of the X-axis in the order of the Vdd wiring, Vss2wiring, and Vss1wiring, but the order of arranging the three linear conductors2101to2103is not limited to this example and can be any order.

The linear conductor2111has a conductor width WXBD in the X direction, the linear conductor2112has a conductor width WXBS1 in the X direction, and the linear conductor2113has a conductor width WXBS2 in the X direction. The conductor width WXBD of the linear conductor2111, the conductor width WXBS1 of the linear conductor2112, and the conductor width WXBS2 of the linear conductor2113are, for example, the same (the conductor width WXBD=the conductor width WXBS1=the conductor width WXBS2). A gap with the gap width GXB is formed between two adjacent linear conductors of the linear conductors2111to2113.

The, the linear conductor2111is periodically arranged in the X direction with a conductor period FXBD. The linear conductor2112is periodically arranged in the X direction with a conductor period FXBS1, and the linear conductor2113is periodically arranged in the X direction with a conductor period FXBS2. The conductor period FXBD, the conductor period FXBS1, and the conductor period FXBS2 are, for example, the same (the conductor period FXBD=the conductor period FXBS1=the conductor period FXBS2).

Therefore, in a rectangular region within a predetermined range of the conductor layer B, the sum of the conductor widths WXBD in the X direction of the linear conductors2111connected to the first power supply Vdd, the sum of the conductor widths WXBS1 in the X direction of the linear conductors2112connected to the second power supply Vss1, and the sum of the conductor widths WXBS2 in the X direction of the linear conductors2113connected to the third power supply Vss2are the same. Furthermore, in a rectangular region within a predetermined range of the conductor layer B, the conductive area of the linear conductor2111connected to the first power supply Vdd, the conductive area of the linear conductor2112connected to the second power supply Vss1, and the conductive area of the linear conductor2113connected to the third power supply Vss2are the same.

Next, in the conductor layer A and the conductor layer B, comparing the linear conductor2101and the linear conductor2111connected to the same first power supply Vdd, the conductor width WXAD and the conductor width WXBD are the same, and the conductor period FXAD and conductor period FXBD are also the same. Note that the positions of the linear conductor2101and the linear conductor2111in the X direction are different. The amount of shift in the X-direction position between the linear conductor2101and the linear conductor2111is equal to or larger than the gap widths GXA and GXB in the X direction and equal or smaller than the conductor widths WXAD and WXBD in the X direction, and is more favorably larger than the gap widths GXA and GXB in the X direction and smaller than the conductor widths WXAD and WXBD in the X direction.

Furthermore, when comparing the linear conductor2102and the linear conductor2112connected to the second power supply Vss1, the conductor width WXAS1 and the conductor width WXBS1 are the same, and the conductor period FXAS1 and the conductor period FXBS1 are also the same. Note that the positions of the linear conductor2102and the linear conductor2112in the X direction are different. The amount of shift in the X-direction position between the linear conductor2102and the linear conductor2112is equal to or larger than the gap widths GXA and GXB in the X direction and equal or smaller than the conductor widths WXAS1 and WXBS1 in the X direction, and is more favorably larger than the gap widths GXA and GXB in the X direction and smaller than the conductor widths WXAS1 and WXBS1 in the X direction.

Furthermore, comparing the linear conductor2103and the linear conductor2113connected to the third power supply Vss2, the conductor width WXAS2 and the conductor width WXBS2 are the same, and the conductor period FXAS2 and the conductor period FXBS2 are also the same. Note that the positions of the linear conductor2103and the linear conductor2113in the X direction are different. The amount of shift in the X-direction position between the linear conductor2103and the linear conductor2113is equal to or larger than the gap widths GXA and GXB in the X direction and equal or smaller than the conductor widths WXAS2 and WXBS2 in the X direction, and is more favorably larger than the gap widths GXA and GXB in the X direction and smaller than the conductor widths WXAS2 and WXBS2 in the X direction.

FIG.213is a plan view illustrating a stacked state of the conductor layer A in A inFIG.212and the conductor layer B in B inFIG.212.

In the case where the amount of shift in the X-direction position between the linear conductors of the conductor layer A and the conductor layer B, and the conductor widths and the gap widths in the X direction are in the above favorable relationship, the conductor layer A and the conductor layer B can be stacked to form a light-shielding structure, as illustrated inFIG.213, and can shield the hot carrier light emission.

Furthermore, in the case where the amount of shift in the X-direction position between the linear conductors of the conductor layer A and the conductor layer B, and the gap widths and the conductor widths in the X direction are in the above-favorable relationship, the linear conductors connected to the same power supply of the conductor layers A and B may be electrically connected via a conductor via (VIA) extending in the Z direction, in a predetermined partial region where the positions overlap. From the viewpoint of voltage drop (IR-Drop), it is desirable, but not limited to, that the linear conductors connected to the same power supply be electrically connected to each other.

Furthermore, for example, in the case where either the second power supply Vss1or the third power supply Vss2is selected by the selection unit2002or the like inFIG.211, both the conductor layers A and B form a differential structure. Specifically, in the conductor layer A, in the case where the second power supply Vss1is selected, the current distribution of the linear conductor2101connected to the first power supply Vdd and the current distribution of the linear conductor2102connected to the second power supply Vss1are substantially equal and have opposite characteristics, and in the case where the third power supply Vss2is selected, the current distribution of the linear conductor2101connected to the first power supply Vdd and the current distribution of the linear conductor2103connected to the third power supply Vss2are substantially equal and have opposite characteristics. Furthermore, in the conductor layer B, in the case where the second power supply Vss1is selected, the current distribution of the linear conductor2111connected to the first power supply Vdd and the current distribution of the linear conductor2112connected to the second power supply Vss1are substantially equal and have opposite characteristics, and in the case where the third power supply Vss2is selected, the current distribution of the linear conductor2111connected to the first power supply Vdd and the current distribution of the linear conductor2113connected to the third power supply Vss2are substantially equal and have opposite characteristics. Here, the substantially uniform is a difference in a range that can be regarded as uniform, but for example, the difference may be a difference in a range not exceeding at least twice. Thereby, inductive noise can be suppressed as compared with a non-differential structure. Moreover, since the differential structure is a symmetrical structure, noise design is easy.

First Modification of First Configuration Example of Three-Power Supply

FIGS.214and215illustrate a first modification of the first configuration example of the three-power supply.

In both the coordinate systems inFIGS.214and215, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

A ofFIG.214is a plan view of the conductor layer A, and B ofFIG.214is a plan view of the conductor layer B. Note thatFIG.214may be considered as the entire region of each conductor layer or may be considered as a partial region.

Since the conductor layer A in A inFIG.214is the same as the conductor layer A of the first configuration example illustrated in A inFIG.212, description thereof will be omitted.

In the conductor layer B in B inFIG.214, linear conductors2121to2123long in the Y direction are arranged in units of two in a predetermined order in the X direction. Furthermore, the linear conductors2121to2123in units of two are periodically arranged in the X direction.

In other words, the conductor layer B of the second configuration example has a configuration in which linear conductors2111to2113as the Vdd wiring, the Vss2wiring, and the Vss1wiring of the conductor layer B of the first configuration example are respectively replaced with the two linear conductors2121to2123, and the linear conductors2121to2123are periodically arranged in the X direction.

The linear conductor2121is wiring (Vdd wiring) connected to the first power supply Vdd. The linear conductor2122is wiring (Vss1wiring) connected to the second power supply Vss1. The linear conductor2123is wiring (Vss2wiring) connected to the third power supply Vss2.

Therefore, in B inFIG.214, the linear conductors2121to2123in units of two are arranged in the positive direction of the X-axis in the order of the Vdd wiring, Vss2wiring, and Vss1wiring, but the order of arranging the linear conductors2121to2123in units of two is not limited to this example and can be any order.

The linear conductor2121has the conductor width WXBD in the X direction, the linear conductor2122has the conductor width WXBS1 in the X direction, and the linear conductor2123has the conductor width WXBS2 in the X direction. The conductor width WXBD of the linear conductor2121, the conductor width WXBS1 of the linear conductor2122, and the conductor width WXBS2 of the linear conductor2123are, for example, the same (the conductor width WXBD=the conductor width WXBS1=the conductor width WXBS2). A gap with the gap width GXB is formed between two adjacent linear conductors of the linear conductors2121to2123.

Then, the two linear conductors2121are periodically arranged in the X direction with the conductor period FXBD. The two linear conductors2122are periodically arranged in the X direction with the conductor period FXBS1, and the two linear conductors2123are periodically arranged in the X direction with the conductor period FXBS2. The conductor period FXBD, the conductor period FXBS1, and the conductor period FXBS2 are, for example, the same (the conductor period FXBD=the conductor period FXBS1=the conductor period FXBS2).

Therefore, in a rectangular region within a predetermined range of the conductor layer B, the sum of the conductor widths WXBD in the X direction of the linear conductors2121connected to the first power supply Vdd, the sum of the conductor widths WXBS1 in the X direction of the linear conductors2122connected to the second power supply Vss1, and the sum of the conductor widths WXBS2 in the X direction of the linear conductors2123connected to the third power supply Vss2are the same. Furthermore, in a rectangular region within a predetermined range of the conductor layer B, the conductive area of the linear conductor2121connected to the first power supply Vdd, the conductive area of the linear conductor2122connected to the second power supply Vss1, and the conductive area of the linear conductor2123connected to the third power supply Vss2are the same.

In the case where either the second power supply Vss1or the third power supply Vss2is selected in the conductor layer B, the conductor layer B forms a differential structure and thus can suppress the inductive noise more than a non-differential structure, and noise design is easier.

FIG.215is a plan view illustrating a stacked state of the conductor layer A in A inFIG.214and the conductor layer B in B inFIG.214.

By setting the amount of shift in the X-direction position between the linear conductors of the conductor layer A and the conductor layer B, and the conductor widths and the gap widths in the X direction to predetermined conditions, the conductor layer A and the conductor layer B can have a light-shielding structure in a stacked state, as illustrated inFIG.215, and can shield the hot carrier light emission.

The linear conductors connected to the same power supply of the conductor layers A and B may be electrically connected via a conductor via extending in the Z direction, or the like, in a predetermined partial region where the positions overlap. From the viewpoint of voltage drop, it is desirable, but not limited to, that the linear conductors connected to the same power supply be electrically connected to each other.

The first modification of the first configuration example illustrated inFIG.214has a configuration in which the linear conductors2111to2113as the Vdd wiring, the Vss2wiring, and the Vss1wiring of the conductor layer B, of the conductor layers A and B of the first configuration example of the three-power supply illustrated inFIG.212, are respectively replaced with the two linear conductors2121and2123, and the linear conductors2121and2123are periodically arranged in the X direction.

However, a predetermined number of three or more linear conductors may be periodically arranged instead of the periodic arrangement of the linear conductors2121to2123in units of two.

Furthermore, for example, a configuration in which the linear conductors2101to2103as the Vdd wiring, the Vss2wiring, and the Vss1wiring of the conductor layer A, of the conductor layers A and B of the first configuration example of the three-power supply illustrated inFIG.212, can be respectively replaced with the two linear conductors2121and2123, and the linear conductors2121and2123are periodically arranged in the X direction, can also be adopted.

Alternatively, a configuration in which the Vdd wiring, the Vss2wiring, and the Vss1wiring of both the conductor layers A and B are respectively replaced with two or more predetermined number of linear conductors2121to2123, and the linear conductors2121to2123are periodically arranged in the X direction, can also be adopted. In this case, the conductor widths, conductor periods, and gap widths of the linear conductors2121to2123of the conductor layers A and B may be the same or different between the conductor layer A and the conductor layer B. One or two of the conductor widths, the conductor periods, and the gap widths may be the same and the others may be different between the conductor layer A and the conductor layer B.

Second Modification of First Configuration Example of Three-Power Supply

FIGS.216and217illustrate a second modification of the first configuration example of the three-power supply.

In both the coordinate systems inFIGS.216and217, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

A ofFIG.216is a plan view of the conductor layer A, and B ofFIG.216is a plan view of the conductor layer B. Note thatFIG.216may be considered as the entire region of each conductor layer or may be considered as a partial region.

In the conductor layer A of the first configuration example illustrated in A inFIG.212, the three Vdd conductor, Vss1conductor, and Vss2conductor periodically arranged in the X direction have the same conductor width, whereas in the conductor layer A of the second modification in A inFIG.216, the Vdd conductor and the Vss1conductor have the same conductor width but the conductor width of the Vss2conductor is smaller than the conductor width of the Vdd conductor and the Vss1conductor (the conductor width WXAD=the conductor width WXAS1>the conductor width WXAS2).

Specifically, the conductor layer A in A inFIG.216is configured by arranging three linear conductors2131to2133, which are long in the Y direction, in the X direction in a predetermined order, and periodically arranging the three linear conductors2131to2133in the X direction.

The linear conductor2131is wiring (Vdd wiring) connected to the first power supply Vdd. The linear conductor2132is wiring (Vss1wiring) connected to the second power supply Vss1. The linear conductor2133is wiring (Vss2wiring) connected to the third power supply Vss2.

The linear conductor2131has the conductor width WXAD in the X direction, the linear conductor2132has the conductor width WXAS1 in the X direction, and the linear conductor2133has the conductor width WXAS2 in the X direction. The conductor width WXAD of the linear conductor2131and the conductor width WXAS1 of the linear conductor2132are, for example, the same (the conductor width WXAD=the conductor width WXAS1), and the conductor width WXAS2 of the linear conductor2133is smaller than the conductor width WXAD of the linear conductor2131and the conductor width WXAS1 of the linear conductor2132(the conductor width WXAD=the conductor width WXAS1>the conductor width WXAS2). Furthermore, a gap with the gap width GXA is formed between two adjacent linear conductors of the linear conductors2131to2133.

The linear conductor2131is periodically arranged in the X direction with the conductor period FXAD, and the linear conductor2132is periodically arranged in the X direction with the conductor period FXAS1. Similarly, the linear conductors2133are periodically arranged in the X direction with the conductor period FXAS2. The conductor period FXAD, the conductor period FXAS1, and the conductor period FXAS2 are, for example, the same (the conductor period FXAD=the conductor period FXAS1=the conductor period FXAS2).

Therefore, in a rectangular region within a predetermined range of the conductor layer A, the sum of the conductor widths WXAD in the X direction of the linear conductors2131connected to the first power supply Vdd and the sum of the conductor widths WXAS1 in the X direction of the linear conductors2132connected to the second power supply Vss1are the same. Then, the sum of the conductor widths WXAS2 in the X direction of the linear conductor2133connected to the third power supply Vss2is smaller than the sum of the conductor widths WXAS1 in the X direction of the linear conductors2132connected to the second power supply Vss1.

Furthermore, in a rectangular region within a predetermined range of the conductor layer A, the conductive area of the linear conductor2131connected to the first power supply Vdd and the conductive area of the linear conductor2132connected to the second power supply Vss1are the same. Then, the conductive area of the linear conductor2133connected to the third power supply Vss2is smaller than the conductive area of the linear conductor2132connected to the second power supply Vss1.

In the conductor layer B of the second modification in B inFIG.216, the Vdd conductor and the Vss1conductor have the same conductor width, and the conductor width of the Vss2conductor is smaller than the conductor widths of the Vdd conductor and the Vss1conductor, similarly to the conductor layer A of the second modification.

Specifically, the conductor layer B in B inFIG.216is configured by arranging three linear conductors2141to2143, which are long in the Y direction, in the X direction in a predetermined order, and periodically arranging the three linear conductors2141to2143in the X direction.

The linear conductor2141is wiring (Vdd wiring) connected to the first power supply Vdd. The linear conductor2142is wiring (Vss1wiring) connected to the second power supply Vss1. The linear conductor2143is wiring (Vss2wiring) connected to the third power supply Vss2.

The linear conductor2141has the conductor width WXBD in the X direction, the linear conductor2142has the conductor width WXBS1 in the X direction, and the linear conductor2143has the conductor width WXBS2 in the X direction. The conductor width WXBD of the linear conductor2141and the conductor width WXBS1 of the linear conductor2142are, for example, the same (the conductor width WXBD=the conductor width WXBS1), and the conductor width WXBS2 of the linear conductor2143is smaller than the conductor width WXBD of the linear conductor2141and the conductor width WXBS1 of the linear conductor2142(the conductor width WXBD=the conductor width WXBS1>the conductor width WXBS2). Furthermore, a gap with the gap width GXB is formed between two adjacent linear conductors of the linear conductors2141to2143.

The linear conductor2141is periodically arranged in the X direction with the conductor period FXBD, and the linear conductor2142is periodically arranged in the X direction with the conductor period FXBS1. Similarly, the linear conductor2143is periodically arranged in the X direction with the conductor period FXBS2. The conductor period FXBD, the conductor period FXBS1, and the conductor period FXBS2 are, for example, the same (the conductor period FXBD=the conductor period FXBS1=the conductor period FXBS2).

Therefore, in a rectangular region within a predetermined range of the conductor layer B, the sum of the conductor widths WXBD in the X direction of the linear conductors2141connected to the first power supply Vdd and the sum of the conductor widths WXBS1 in the X direction of the linear conductors2142connected to the second power supply Vss1are the same. Then, the sum of the conductor widths WXBS2 in the X direction of the linear conductors2143connected to the third power supply Vss2is smaller than the sum of the conductor widths WXBS1 in the X direction of the linear conductors2142connected to the second power supply Vss1.

Furthermore, in a rectangular region within a predetermined range of the conductor layer B, the conductive area of the linear conductor2141connected to the first power supply Vdd and the conductive area of the linear conductor2142connected to the second power supply Vss1are the same. Then, the conductive area of the linear conductor2143connected to the third power supply Vss2is smaller than the conductive area of the linear conductor2142connected to the second power supply Vss1.

FIG.217is a plan view illustrating a stacked state of the conductor layer A in A inFIG.216and the conductor layer B in B inFIG.216.

By setting the amount of shift in the X-direction position between the linear conductors of the conductor layer A and the conductor layer B, and the conductor widths and the gap widths in the X direction to predetermined conditions, the conductor layer A and the conductor layer B can have a light-shielding structure in a stacked state, as illustrated inFIG.217, and can shield the hot carrier light emission.

The linear conductors connected to the same power supply of the conductor layers A and B may be electrically connected via a conductor via extending in the Z direction, or the like, in a predetermined partial region where the positions overlap. From the viewpoint of voltage drop, it is desirable, but not limited to, that the linear conductors connected to the same power supply be electrically connected to each other.

In the conductor layer A and the conductor layer B of the second modification of the first configuration example of the three-power supply configured as described above, the sum of the conductor widths in the X direction of the Vss2conductors is smaller than the sum of the conductor widths in the X direction of the Vss1conductors, and thus in a case where the total current amount when the third power supply Vss2is selected is smaller than the total current amount when the second power supply Vss1is selected, the total current amount flowing through the Vss2conductor is smaller than the total current amount flowing through the Vss1conductor, and the voltage of the Vss2conductor is less likely to drop than the voltage of the Vss1conductor. Thereby, the conductor resistance of the Vss2conductor can be made larger than that of the Vss1conductor as long as an acceptable level of the voltage drop is satisfied. When the conductor width WXAS2 of the Vss2conductor becomes smaller, the Vdd conductor and the Vss1conductor can be arranged densely, which leads to improvement of the voltage drop of the Vdd conductor and the Vss1conductor when a comparison is performed on the assumption that the wiring regions have the same area. Furthermore, since the area of an Aggressor loop that generates a magnetic field becomes smaller as the conductor period becomes shorter, the inductive noise can be improved as described with reference toFIGS.46to57.

Third Modification of First Configuration Example of Three-Power Supply

FIGS.218and219illustrate a third modification of the first configuration example of the three-power supply.

In both the coordinate systems inFIGS.218and219, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

A ofFIG.218is a plan view of the conductor layer A, and B ofFIG.218is a plan view of the conductor layer B. Note thatFIG.218may be considered as the entire region of each conductor layer or may be considered as a partial region.

In the conductor layer A of the first configuration example illustrated in A inFIG.212, the three Vdd conductor, Vss1conductor, and Vss2conductor periodically arranged in the X direction have the same conductor width, whereas in the conductor layer A of the third modification in A inFIG.218, the conductor width of the Vss1conductor is smaller than the conductor width of the Vdd conductor, and the conductor width of the Vss2conductor is smaller than the conductor width of the Vss1conductor (the conductor width WXAD>the conductor width WXAS1>the conductor width WXAS2).

Specifically, the conductor layer A in A inFIG.218is configured by arranging three linear conductors2151to2153, which are long in the Y direction, in the X direction in a predetermined order, and periodically arranging the three linear conductors2151to2153in the X direction.

The linear conductor2151is wiring (Vdd wiring) connected to the first power supply Vdd. The linear conductor2152is wiring (Vss1wiring) connected to the second power supply Vss1. The linear conductor2153is wiring (Vss2wiring) connected to the third power supply Vss2.

The linear conductor2151has the conductor width WXAD in the X direction, the linear conductor2152has the conductor width WXAS1 in the X direction, and the linear conductor2153has the conductor width WXAS2 in the X direction. The conductor width WXAD of the linear conductor2151is larger than the conductor width WXAS1 of the linear conductor2152(the conductor width WXAD>the conductor width WXAS1), and the conductor width WXAS2 of the linear conductor2153is smaller than the conductor width WXAS1 of the linear conductor2152(the conductor width WXAS1>the conductor width WXAS2). Furthermore, a gap with the gap width GXA is formed between two adjacent linear conductors of the linear conductors2151to2153.

The linear conductor2151is periodically arranged in the X direction with the conductor period FXAD, and the linear conductor2152is periodically arranged in the X direction with the conductor period FXAS1. Similarly, the linear conductor2153is periodically arranged in the X direction with the conductor period FXAS2. The conductor period FXAD, the conductor period FXAS1, and the conductor period FXAS2 are, for example, the same (the conductor period FXAD=the conductor period FXAS1=the conductor period FXAS2).

Therefore, in a rectangular region within a predetermined range of the conductor layer A, the sum of the conductor widths WXAS1 in the X direction of the linear conductors2152connected to the second power supply Vss1is smaller than the sum of the conductor widths WXAD in the X direction of the linear conductors2151connected to the first power supply Vdd. Then, the sum of the conductor widths WXAS2 in the X direction of the linear conductors2153connected to the third power supply Vss2is smaller than the sum of the conductor widths WXAS1 in the X direction of the linear conductors2152connected to the second power supply Vss1.

In a rectangular region within a predetermined range of the conductor layer A, the conductive area of the linear conductor2152connected to the second power supply Vss1is smaller than the conductive area of the linear conductor2151connected to the first power supply Vdd. Then, the conductive area of the linear conductor2153connected to the third power supply Vss2is smaller than the conductive area of the linear conductor2152connected to the second power supply Vss1. That is, the conductive areas of the Vdd conductor, the Vss1conductor, and the Vss2conductor of the conductor layer A are different.

In the conductor layer B of the third modification in B inFIG.218, the conductor width of the Vss1conductor is smaller than the conductor width of the Vdd conductor, and the conductor width of the Vss2conductor is smaller than the conductor width of the Vss1conductor (the conductor width WXBD>the conductor width WXBS1>the conductor width WXBS2), similarly to the conductor layer A of the third modification.

Specifically, the conductor layer B in B inFIG.218is configured by arranging three linear conductors2161to2163, which are long in the Y direction, in the X direction in a predetermined order, and periodically arranging the three linear conductors2161to2163in the X direction.

The linear conductor2161is wiring (Vdd wiring) connected to the first power supply Vdd. The linear conductor2162is wiring (Vss1wiring) connected to the second power supply Vss1. The linear conductor2163is wiring (Vss2wiring) connected to the third power supply Vss2.

The linear conductor2161has the conductor width WXBD in the X direction, the linear conductor2162has the conductor width WXBS1 in the X direction, and the linear conductor2163has a conductor width WXAB2 in the X direction. The conductor width WXBD of the linear conductor2161is larger than the conductor width WXBS1 of the linear conductor2162(the conductor width WXBD>the conductor width WXBS1), and the conductor width WXBS2 of the linear conductor2163is smaller than the conductor width WXBS1 of the linear conductor2162(the conductor width WXBS1>the conductor width WXBS2). Furthermore, a gap with the gap width GXB is formed between two adjacent linear conductors of the linear conductors2161to2163.

The linear conductor2161is periodically arranged in the X direction with the conductor period FXBD, and the linear conductor2162is periodically arranged in the X direction with the conductor period FXBS1. Similarly, the linear conductor2163is periodically arranged in the X direction with the conductor period FXBS2. The conductor period FXBD, the conductor period FXBS1, and the conductor period FXBS2 are, for example, the same (the conductor period FXBD=the conductor period FXBS1=the conductor period FXBS2).

Therefore, in a rectangular region within a predetermined range of the conductor layer B, the sum of the conductor widths WXBS1 in the X direction of the linear conductors2162connected to the second power supply Vss1is smaller than the sum of the conductor widths WXBD in the X direction of the linear conductors2161connected to the first power supply Vdd. Then, the sum of the conductor widths WXBS2 in the X direction of the linear conductors2163connected to the third power supply Vss2is smaller than the sum of the conductor widths WXBS1 in the X direction of the linear conductors2162connected to the second power supply Vss1.

Furthermore, in a rectangular region within a predetermined range of the conductor layer B, the conductive area of the linear conductor2162connected to the second power supply Vss1is smaller than the conductive area of the linear conductor2161connected to the first power supply Vdd. Then, the conductive area of the linear conductor2163connected to the third power supply Vss2is smaller than the conductive area of the linear conductor2162connected to the second power supply Vss1. That is, the conductive areas of the Vdd conductor, the Vss1conductor, and the Vss2conductor of the conductor layer B are different.

FIG.219is a plan view illustrating a stacked state of the conductor layer A in A inFIG.218and the conductor layer B in B inFIG.218.

By setting the amount of shift in the X-direction position between the linear conductors of the conductor layer A and the conductor layer B, and the conductor widths and the gap widths in the X direction to predetermined conditions, the conductor layer A and the conductor layer B can have a light-shielding structure in a stacked state, as illustrated inFIG.219, and can shield the hot carrier light emission.

The linear conductors connected to the same power supply of the conductor layers A and B may be electrically connected via a conductor via extending in the Z direction, or the like, in a predetermined partial region where the positions overlap. From the viewpoint of voltage drop, it is desirable, but not limited to, that the linear conductors connected to the same power supply be electrically connected to each other.

In the conductor layer A and the conductor layer B of the third modification of the first configuration example of the three-power supply configured as described above, the sum of the conductor widths in the X direction of the Vss2conductors is smaller than the sum of the conductor widths in the X direction of the Vss1conductors, and thus in a case where the total current amount when the third power supply Vss2is selected is smaller than the total current amount when the second power supply Vss1is selected, the total current amount flowing through the Vss2conductor is smaller than the total current amount flowing through the Vss1conductor, and the voltage of the Vss2conductor is less likely to drop than the voltage of the Vss1conductor. Thereby, the conductor resistance of the Vss2conductor can be made larger than that of the Vss1conductor as long as an acceptable level of the voltage drop is satisfied.

In the configuration in which the second power supply Vss1and the third power supply Vss2are selectively switched, the Vdd conductor is a commonly used element. By making the commonly used Vdd conductor less likely to have a voltage drop than the Vss1conductor and the Vss2conductor, the voltage drop of both the combination of the Vdd conductor and the Vss1conductor and the combination of the Vdd conductor and the Vss2conductor may be able to be improved. Furthermore, in the third modification, the conductors are arranged more densely than those in the second modification, so that the voltage drop and the inductive noise may be able to be further improved.

Fourth Modification of First Configuration Example of Three-Power Supply

FIGS.220and221illustrate a fourth modification of the first configuration example of the three-power supply.

In both the coordinate systems inFIGS.220and221, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

A ofFIG.220is a plan view of the conductor layer A, and B ofFIG.220is a plan view of the conductor layer B. Note thatFIG.220may be considered as the entire region of each conductor layer or may be considered as a partial region.

In the conductor layer A of the first configuration example illustrated in A inFIG.220, the three Vdd conductor, Vss1conductor, and Vss2conductor periodically arranged in the X direction have the same conductor width, whereas in the conductor layer A of the fourth modification in A inFIG.220, the conductor widths of the Vss1conductor and the Vss2conductor are smaller than the conductor width of the Vdd conductor, and the conductor widths of the Vss1conductor and the Vss2conductor are the same (the conductor width WXAD>the conductor width WXAS1=the conductor width WXAS2).

Specifically, the conductor layer A in A inFIG.220is configured by arranging three linear conductors2171to2173, which are long in the Y direction, in the X direction in a predetermined order, and periodically arranging the three linear conductors2171to2173in the X direction.

The linear conductor2171is wiring (Vdd wiring) connected to the first power supply Vdd. The linear conductor2172is wiring (Vss1wiring) connected to the second power supply Vss1. The linear conductor2173is wiring (Vss2wiring) connected to the third power supply Vss2.

The linear conductor2171has the conductor width WXAD in the X direction, the linear conductor2172has the conductor width WXAS1 in the X direction, and the linear conductor2173has the conductor width WXAS2 in the X direction. The conductor width WXAD of the linear conductor2171is larger than both the conductor width WXAS1 of the linear conductor2172and the conductor width WXAS2 of the linear conductor2173, and the conductor width WXAS1 of the linear conductor2172and the conductor width WXAS2 of the linear conductor2173are, for example, the same (the conductor width WXAD>the conductor width WXAS1=the conductor width WXAS2). Furthermore, a gap with the gap width GXA is formed between two adjacent linear conductors of the linear conductors2171to2173.

The linear conductor2171is periodically arranged in the X direction with the conductor period FXAD, and the linear conductor2172is periodically arranged in the X direction with the conductor period FXAS1. Similarly, the linear conductor2173is periodically arranged in the X direction with the conductor period FXAS2. The conductor period FXAD, the conductor period FXAS1, and the conductor period FXAS2 are, for example, the same (the conductor period FXAD=the conductor period FXAS1=the conductor period FXAS2).

Therefore, in a rectangular region within a predetermined range of the conductor layer A, each of the sum of the conductor widths WXAS1 in the X direction of the linear conductors2172connected to the second power supply Vss1and the sum of the conductor widths WXAS2 in the X direction of the linear conductors2173connected to the third power supply Vss2is smaller than the sum of the conductor widths WXAD in the X direction of the linear conductors2171connected to the first power supply Vdd. Then, the sum of the conductor widths WXAS1 in the X direction of the linear conductors2172connected to the second power supply Vss1and the sum of the conductor widths WXAS2 in the X direction of the linear conductors2173connected to the third power supply Vss2are equal.

Furthermore, in a rectangular region within a predetermined range of the conductor layer A, each of the conductive area of the linear conductor2172connected to the second power supply Vss1and the conductive area of the linear conductor2173connected to the third power supply Vss2is smaller than the conductive area of the linear conductor2171connected to the first power supply Vdd. Then, the conductive area of the linear conductor2172connected to the second power supply Vss1and the conductive area of the linear conductor2173connected to the third power supply Vss2are equal.

In the conductor layer B of the fourth modification in B inFIG.220, the conductor widths of the Vss1conductor and the Vss2conductor are smaller than the conductor width of the Vdd conductor, and the conductor widths of the Vss1conductor and the Vss2conductor are the same (the conductor width WXBD>the conductor width WXBS1=the conductor width WXBS2), similarly to the conductor layer A of the fourth modification.

Specifically, the conductor layer B in B inFIG.220is configured by arranging three linear conductors2181to2183, which are long in the Y direction, in the X direction in a predetermined order, and periodically arranging the three linear conductors2181to2183in the X direction.

The linear conductor2181is wiring (Vdd wiring) connected to the first power supply Vdd. The linear conductor2182is wiring (Vss1wiring) connected to the second power supply Vss1. The linear conductor2183is wiring (Vss2wiring) connected to the third power supply Vss2.

The linear conductor2181has the conductor width WXBD in the X direction, the linear conductor2182has the conductor width WXBS1 in the X direction, and the linear conductor2183has the conductor width WXAB2 in the X direction. The conductor width WXBD of the linear conductor2181is larger than both the conductor width WXBS1 of the linear conductor2182and the conductor width WXBS2 of the linear conductor2183, and the conductor width WXBS1 of the linear conductor2182and the conductor width WXBS2 of the linear conductor2183are, for example, the same (the conductor width WXBD>the conductor width WXBS1=the conductor width WXBS2). Furthermore, a gap with the gap width GXB is formed between two adjacent linear conductors of the linear conductors2181to2183.

The linear conductor2181is periodically arranged in the X direction with the conductor period FXBD, and the linear conductor2182is periodically arranged in the X direction with the conductor period FXBS1. Similarly, the linear conductor2183is periodically arranged in the X direction with the conductor period FXBS2. The conductor period FXBD, the conductor period FXBS1, and the conductor period FXBS2 are the same (the conductor period FXBD=the conductor period FXBS1=the conductor period FXBS2).

Therefore, in a rectangular region within a predetermined range of the conductor layer B, each of the sum of the conductor widths WXBS1 in the X direction of the linear conductors2182connected to the second power supply Vss1and the sum of the conductor widths WXBS2 in the X direction of the linear conductors2183connected to the third power supply Vss2is smaller than the sum of the conductor widths WXBD in the X direction of the linear conductors2181connected to the first power supply Vdd. Then, the sum of the conductor widths WXBS1 in the X direction of the linear conductors2182connected to the second power supply Vss1and the sum of the conductor widths WXBS2 in the X direction of the linear conductors2183connected to the third power supply Vss2are equal.

Furthermore, in a rectangular region within a predetermined range of the conductor layer B, each of the conductive area of the linear conductor2182connected to the second power supply Vss1and the conductive area of the linear conductor2183connected to the third power supply Vss2is smaller than the conductive area of the linear conductor2181connected to the first power supply Vdd. Then, the conductive area of the linear conductor2182connected to the second power supply Vss1and the conductive area of the linear conductor2183connected to the third power supply Vss2are equal.

FIG.221is a plan view illustrating a stacked state of the conductor layer A in A inFIG.220and the conductor layer B in B inFIG.220.

By setting the amount of shift in the X-direction position between the linear conductors of the conductor layer A and the conductor layer B, and the conductor widths and the gap widths in the X direction to predetermined conditions, the conductor layer A and the conductor layer B can have a light-shielding structure in a stacked state, as illustrated inFIG.221, and can shield the hot carrier light emission.

The linear conductors connected to the same power supply of the conductor layers A and B may be electrically connected via a conductor via extending in the Z direction, or the like, in a predetermined partial region where the positions overlap. From the viewpoint of voltage drop, it is desirable, but not limited to, that the linear conductors connected to the same power supply be electrically connected to each other.

In the conductor layer A and the conductor layer B of the fourth modification of the first configuration example of the three-power supply configured as described above, in the configuration in which the second power supply Vss1and the third power supply Vss2are selectively switched, a structural difference between the combination of the Vdd conductor and the Vss1conductor and the combination of the Vdd conductor and the Vss2conductor can be made small. Thereby, for example, in the case where the second power supply Vss1and the third power supply Vss2have the same power supply voltage, the difference in the voltage drop and the difference in the inductive noise can be reduced. Furthermore, in the fourth modification, the conductors are arranged more densely than those in the third modification, so that the voltage drop and the inductive noise may be able to be further improved.

In the first configuration example of the three-power supply and the first to fourth modifications, an example in which the conductor layer A and the conductor layer B form a light-shielding structure has been described, but the conductor layer A and the conductor layer B do not necessarily have the light-shielding structure. For example, a configuration in which the gap width in the X direction is larger than the positional shift in the X direction, the positional shift in the X direction is larger than the conductor width in the X direction, or the positional shift in the X direction is zero or a value close to zero may be adopted. Note that the stacked state of the conductor layer A and the conductor layer B becomes the light-shielding structure even with the configuration in which the positional shift in the X direction is larger than the conductor width in the X direction, depending on the configuration of the linear conductors of the conductor layer A and the conductor layer B. Furthermore, a configuration in which either one of the conductor layer A or the conductor layer B is not provided, or a configuration in which either the conductor layer A or the conductor layer B has a conductor arrangement other than the above-described configuration may be adopted. Even in the case where the stacked state of the conductor layer A and the conductor layer B is not the light-shielding structure, the voltage drop and the inductive noise can be improved.

Second Configuration Example of Three-Power Supply

FIGS.222and223illustrate a second configuration example of the three-power supply.

In both the coordinate systems inFIGS.222and223, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

A ofFIG.222is a plan view of the conductor layer A, and B ofFIG.222is a plan view of the conductor layer B. Note thatFIG.222may be considered as the entire region of each conductor layer or may be considered as a partial region.

In the above-described first configuration example and its modifications, the repeating directions of the linear conductors of the conductor layer A and the conductor layer B are the same X direction, whereas in the second configuration example, the repeating direction of the linear conductor of the conductor layer A and the repeating direction of the linear conductor of the conductor layer B are orthogonal to each other in the X direction and the Y direction.

Since the conductor layer A in A inFIG.222is the same as the conductor layer A of the first configuration example illustrated in A inFIG.212, description thereof will be omitted. The repeating direction of the linear conductors2101to2103long in the Y direction of the conductor layer A is the X direction.

Meanwhile, the repeating direction of the linear conductor of the conductor layer B in B inFIG.222is the Y direction orthogonal to the X direction that is the repeating direction of the conductor layer A.

Specifically, the conductor layer B is configured by arranging three linear conductors2191to2193, which are long in the X direction, in the Y direction in a predetermined order, and periodically arranging the three linear conductors2191to2193in the Y direction.

The linear conductor2191is wiring (Vdd wiring) connected to the first power supply Vdd. The linear conductor2192is wiring (Vss1wiring) connected to the second power supply Vss1. The linear conductor2193is wiring (Vss2wiring) connected to the third power supply Vss2.

Therefore, in B ofFIG.222, the three linear conductors2191to2193are arranged in the positive direction of the Y-axis in the order of the Vdd wiring, Vss2wiring, and Vss1wiring, but the order of arranging the three linear conductors2191to2193is not limited to this example and can be any order.

The linear conductor2191has a conductor width WYBD in the Y direction, the linear conductor2192has a conductor width WYBS1 in the Y direction, and the linear conductor2193has a conductor width WYBS2 in the Y direction. The conductor width WYBD of the linear conductor2191, the conductor width WYBS1 of the linear conductor2192, and the conductor width WYBS2 of the linear conductor2193are, for example, the same (the conductor width WYBD=the conductor width WYBS1=the conductor width WYBS2). A gap with the gap width GYB is formed between two adjacent linear conductors of the linear conductors2191to2193.

Then, the linear conductor2191is periodically arranged in the Y direction with a conductor period FYBD. The linear conductor2192is periodically arranged in the Y direction with a conductor period FYBS1, and the linear conductor2193is periodically arranged in the Y direction with a conductor period FYBS2. The conductor period FYBD, the conductor period FYBS1, and the conductor period FYBS2 are, for example, the same (the conductor period FYBD=the conductor period FYBS1=the conductor period FYBS2).

Therefore, in a rectangular region within a predetermined range of the conductor layer B, the sum of the conductor widths WYBD in the Y direction of the linear conductors2191connected to the first power supply Vdd, the sum of the conductor widths WYBS1 in the Y direction of the linear conductors2192connected to the second power supply Vss1, and the sum of the conductor widths WYBS2 in the Y direction of the linear conductors2193connected to the third power supply Vss2are the same.

Furthermore, in a rectangular region within a predetermined range of the conductor layer B, the conductive area of the linear conductor2191connected to the first power supply Vdd, the conductive area of the linear conductor2192connected to the second power supply Vss1, and the conductive area of the linear conductor2193connected to the third power supply Vss2are the same.

FIG.223is a plan view illustrating a stacked state of the conductor layer A in A inFIG.222and the conductor layer B in B inFIG.222.

As illustrated inFIG.223, the stacked layer of the conductor layer A and the conductor layer B by the second configuration example, that is, the stacked layer of the conductor layer A having a periodic arrangement of the linear conductors2101to2103long in the Y direction and the conductor layer B having a periodic arrangement of the linear conductors2191to2193long in the X direction cannot realize a perfect light-shielding structure but can have a certain degree of light-shielding property.

The linear conductors connected to the same power supply of the conductor layers A and B may be electrically connected via a conductor via extending in the Z direction or the like in a predetermined partial region where the positions overlap. From the viewpoint of voltage drop, it is desirable, but not limited to, that the linear conductors connected to the same power supply be electrically connected to each other.

A ofFIG.224is a plan view illustrating a stacked state of only the linear conductor2101and the linear conductor2191as the Vdd conductors of the conductor layer A and the conductor layer B.

B ofFIG.224is a plan view illustrating a stacked state of only the linear conductor2102and the linear conductor2192as the Vss1conductors of the conductor layer A and the conductor layer B.

FIG.225is a plan view illustrating a stacked state of only the linear conductor2103and the linear conductor2193as the Vss2conductors of the conductor layer A and the conductor layer B.

In the case of electrically connecting the linear conductors connected to the same power supply of the conductor layers A and B via a conductor via in the Z direction or the like, the two layers of the conductor layers A and B can implement a reticulated structure of the three-power supply of the Vdd conductor, the Vss1conductor, and the Vss2conductor, as illustrated inFIGS.224and225. For example, the case of implementing the three-power supply using the conductor layers of the reticulated conductors as in the fourth configuration example of the conductor layers A and B illustrated inFIG.25requires the three layers of conductor layers. Therefore, according to the second configuration example of the three-power supply, the degree of freedom of wiring layout can be increased with a small number of stacked layers.

By implementing the reticulated structure of the three-power supply with the two layers of the conductor layer A and the conductor layer B, the current is easily diffused in the X direction, so that the inductive noise can be improved. Furthermore, the conductor resistance seen from a pad end can be reduced depending on a pad arrangement, so that the voltage drop can be improved.

According to the second configuration example of the three-power supply, comparing the linear conductor2101and the linear conductor2191connected to the same first power supply Vdd in the conductor layer A and the conductor layer B, the conductor width WXAD and the conductor width WYBD are different. However, the conductor width WXAD and the conductor width WYBD may be configured to be the same. Similarly, the conductor period FXAD and the conductor period FYBD are different, but the conductor period FXAD and the conductor period FYBD may be configured to be the same.

First Modification of Second Configuration Example of Three-Power Supply

FIG.226illustrates a first modification of the second configuration example of the three-power supply.

In the coordinate system inFIG.226, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

A ofFIG.226is a plan view of the conductor layer A, and B ofFIG.226is a plan view of the conductor layer B. Note thatFIG.226may be considered as the entire region of each conductor layer or may be considered as a partial region. In the first modification of the second configuration example, the plan view illustrating a stacked state of the conductor layer A and the conductor layer B is omitted.

The conductor layer A in A inFIG.226is the same as the conductor layer A of the second modification of the first configuration example illustrated in A inFIG.216. In other words, in the conductor layer A of the second configuration example illustrated in A inFIG.222, the Vdd conductor, the Vss1conductor, and the Vss2conductor have the same conductor width, whereas in the conductor layer A of the first modification ofFIG.226, the Vdd conductor and the Vss1conductor have the same conductor width, and the conductor width of the Vss2conductor is smaller than the conductor width of the Vdd conductor and the Vss1conductor (the conductor width WXAD=the conductor width WXAS1>the conductor width WXAS2). Thereby, in the first modification, the conductor period FXAD, the conductor period FXAS1, and the conductor period FXAS2 in the X direction are smaller than those in the second configuration example.

Since the conductor layer B in B inFIG.226is the same as the conductor layer B of the second configuration example illustrated in B inFIG.222, description thereof will be omitted.

Second Modification of Second Configuration Example of Three-Power Supply

FIG.227illustrates a second modification of the second configuration example of the three-power supply.

In the coordinate system inFIG.227, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

A ofFIG.227is a plan view of the conductor layer A, and B ofFIG.227is a plan view of the conductor layer B. Note thatFIG.227may be considered as the entire region of each conductor layer or may be considered as a partial region. In the second modification of the second configuration example, the plan view illustrating a stacked state of the conductor layer A and the conductor layer B is omitted.

The conductor layer A in A inFIG.227is the same as the conductor layer A of the first modification of the second configuration example illustrated in A inFIG.226. That is, the conductor layer A has the configuration in which the conductor width of the Vss2conductor is set to be smaller than the conductor width of the Vdd conductor and the Vss1conductor formed with the same conductor width (the conductor width WXAD=the conductor width WXAS1>the conductor width WXAS2).

The conductor layer B in B inFIG.227has a configuration in which the conductor width of the Vss2conductor connected to the third power supply Vss2is smaller than the conductor layer B of the first modification of the second configuration example illustrated in B inFIG.226.

Specifically, the conductor layer B is configured by arranging three linear conductors2201to2203, which are long in the X direction, in the Y direction in a predetermined order, and periodically arranging the three linear conductors2201to2203in the Y direction.

The linear conductor2201is wiring (Vdd wiring) connected to the first power supply Vdd. The linear conductor2202is wiring (Vss1wiring) connected to the second power supply Vss1. The linear conductor2203is wiring (Vss2wiring) connected to the third power supply Vss2.

The linear conductor2201has a conductor width WYBD in the Y direction, the linear conductor2202has a conductor width WYBS1 in the Y direction, and the linear conductor2203has a conductor width WYBS2 in the Y direction. The conductor width WYBD of the linear conductor2201and the conductor width WYBS1 of the linear conductor2202are, for example, the same, and the conductor width WYBS2 of the linear conductor2203is smaller than the conductor width WYBD of the linear conductor2201and the conductor width WYBS1 of the linear conductor2202(the conductor width WYBD=the conductor width WYBS1>the conductor width WYBS2). A gap with the gap width GYB is formed between two adjacent linear conductors of the linear conductors2201to2203.

Then, the linear conductor2201is periodically arranged in the Y direction with a conductor period FYBD. The linear conductor2202is periodically arranged in the Y direction with a conductor period FYBS1, and the linear conductor2203is periodically arranged in the Y direction with a conductor period FYBS2. The conductor period FYBD, the conductor period FYBS1, and the conductor period FYBS2 are, for example, the same (the conductor period FYBD=the conductor period FYBS1=the conductor period FYBS2). In the second modification, the conductor period FYBD, the conductor period FYBS1, and the conductor period FYBS2 in the Y direction are smaller than those of the second configuration example illustrated inFIG.222.

The configuration in which the conductor width WXBS2 of the Vss2conductor of the conductor layer A is made smaller and the conductor periods (the conductor period FXAD, the conductor period FXAS1, and the conductor period FXAS2) in the X direction are made smaller than those of the second configuration example, as in the first modification illustrated inFIG.226, or the configuration in which not only the conductor layer A but also the conductor width WYBS2 of the Vss2conductor of the conductor layer B is made small, and both the conductor period in the X direction of the conductor layer A and the conductor periods (the conductor period FYBD, the conductor period FYBS1, and the conductor period FYBS2) in the Y direction of the conductor layer B are made small, as in the second modification illustrated inFIG.227, can be adopted. By making the conductor period small, the inductive noise can be improved and the voltage drop can also be improved.

In the first modification and the second modification, the conductor width of only the Vss2conductor is made smaller than that of the Vdd conductor in both the conductor layer A and the conductor layer B, but the conductor widths of both the Vss1conductor and the Vss2conductor may be made smaller than that of the Vdd conductor. In that case, the conductor widths of the Vss1conductor and the Vss2conductor may be the same or different.

To make current distributions of the Vdd conductor, the Vss1conductor, and the Vss2conductor the same between the conductor layer A and the conductor layer B, proportions of the conductor widths of the Vdd conductor, the Vss1conductor, and the Vss2conductor are desirably made the same between the conductor layer A and the conductor layer B but the proportions may be made different. For example, a larger discrepancy in the proportions of the conductor widths between the conductor layer A and the conductor layer B can be tolerated as the sheet resistance of the conductor layer B is larger than that of the conductor layer A, such as two times or more, three times or more, four times or more, or the like.

Third Configuration Example of Three-Power Supply

FIGS.228and229illustrate a third configuration example of the three-power supply.

In both the coordinate systems inFIGS.228and229, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

A ofFIG.228is a plan view of the conductor layer A, and B ofFIG.228is a plan view of the conductor layer B. Note thatFIG.228may be considered as the entire region of each conductor layer or may be considered as a partial region.

Regarding the conductor layer A, the first configuration example and the second configuration example have used the linear conductors long in the Y direction connected to the same power supply at the same X position even if the Y positions are different, whereas the conductor A in A inFIG.228is different in that the rectangular Vdd conductor, the rectangular Vss1conductor, and the rectangular Vss2conductor are repeatedly arranged with a predetermined period in the Y direction.

More specifically, a rectangular conductor2211connected to the first power supply Vdd (hereinafter referred to as a rectangular Vdd conductor2211), a rectangle conductor2212connected to the second power supply Vss1(hereinafter referred to as a rectangular Vss1conductor2212), and a rectangular conductor2213connected to the third power supply Vss2(hereinafter referred to as a rectangular Vss2conductor2213) are periodically arranged in the positive direction of the Y axis in that order at a predetermined X position of the conductor layer A. Note that the order of arranging the three rectangular conductors2211to2213is not limited to the example, and may be any order. The rectangular Vdd conductor2211has the conductor width WXAD in the X direction and a conductor width WYAD in the Y direction. The rectangular Vss1conductor2212has the conductor width WXAS1 in the X direction and a conductor width WYAS1 in the Y direction. The rectangular Vss2conductor2213has the conductor width WXAS2 in the X direction and a conductor width WYAS2 in the Y direction. A gap with the gap width GXA in the X direction and the gap width GYB in the Y direction is formed between adjacent rectangular conductors.

A period in the X direction (rectangular conductor period) in which the rectangular conductor, that is one of the rectangular Vdd conductor, the rectangular Vss1conductor, or the rectangular Vss2conductor, is arranged, is the conductor width in the X direction+the gap width in the X direction, and a period in the Y direction (rectangular conductor period) is the conductor width in the Y direction+the gap width in the Y direction.

Furthermore, in the conductor layer A, adjacent three columns each having a set of the rectangular Vdd conductor2211, the rectangular Vss1conductor2212, and the rectangular Vss2conductor2213periodically arranged in the Y direction are formed into one group, and the Y-direction positions of the rectangular conductors are shifted in group units so that regarding gap positions of groups adjacent in the X direction, the gap position of one group comes to a middle in the Y direction of the gap positions of the other adjacent group.

Furthermore, focusing on the arrangement of the rectangular Vdd conductors2211, the rectangular Vss1conductors2212, and the rectangular Vss2conductors2213of the three columns forming one group, the Y-direction positions of the rectangular Vdd conductors, the rectangular Vss1conductors, and the rectangular Vss2conductors are shifted so that the rectangular conductors connected to the same power supply are not arranged at the same Y-direction position of the columns. Meanwhile, looking at the arrangement of the rectangular conductors in the three columns for each connected power supply, for example, the rectangular Vdd conductor2211is arranged at positions of the left column, center column, right column, left column, center column, right column, and the like for every time the rectangular conductor is periodically shifted in the positive direction of the Y axis. The same applies to the arrangement of the rectangular Vss1conductor2212and the rectangular Vss2conductor2213.

With the arrangement of shifting the positions of the rectangular Vdd conductor, the rectangular Vss1conductor, and the rectangular Vss2conductor for each column, the magnetic field is distributed, so that the inductive noise can be reduced. Furthermore, by alternately arranging the Vdd conductor (rectangular Vdd conductor) and the Vss conductors (rectangular Vss1conductor and rectangular Vss2conductor) in one column, the capacitive noise can be reduced. Moreover, by grouping the three columns into one group and shifting the Y-direction positions of the rectangular conductors in group units, the magnetic field is further distributed, and the inductive noise can be further reduced.

Meanwhile, since the conductor layer B in B inFIG.228is the same as the conductor layer B of the second configuration example illustrated in B inFIG.222, description thereof will be omitted.

FIG.229is a plan view illustrating a stacked state of the conductor layer A in A inFIG.228and the conductor layer B in B inFIG.228.

As illustrated inFIG.229, the stacked layer of the conductor layer A and the conductor layer B cannot implement a perfect light-shielding structure but can have a certain degree of light-shielding property, the conductor layer A having three columns in which the Y-direction positions of the rectangular Vdd conductor, the rectangular Vss1conductor, and the rectangular Vss2conductor are shifted for each column as one group, and having the Y-direction positions of the rectangular conductors shifted in group units, and the conductor layer B having the periodic arrangement of the linear conductors2191to2193long in the X direction.

The linear conductors connected to the same power supply of the conductor layers A and B may be electrically connected via a conductor via extending in the Z direction or the like in a predetermined partial region where the positions overlap. From the viewpoint of voltage drop, it is desirable, but not limited to, that the linear conductors connected to the same power supply be electrically connected to each other.

A ofFIG.230is a plan view illustrating a stacked state of only the rectangular Vdd conductor2211and the linear conductor2191as the Vdd conductors of the conductor layer A and the conductor layer B.

B ofFIG.230is a plan view illustrating a stacked state of only the rectangular Vss1conductor2212and the linear conductor2192as the Vss1conductors of the conductor layer A and the conductor layer B.

FIG.231is a plan view illustrating a stacked state of only the rectangular Vss2conductor2213and the linear conductor2193as the Vss2conductors of the conductor layer A and the conductor layer B.

According to the third configuration example of the three-power supply, in the case of electrically connecting the conductors connected to the same power supply of the conductor layers A and B by the configuration of shifting the Y-directional positions of the rectangular conductors in group units, the pseudo reticulated structure can be configured by the two layers of the conductor layers A and B, as illustrated inFIGS.230and231. Therefore, the current can flow in both the X and Y directions, and the degree of freedom of wiring layout can be enhanced. In the case where the conductor layer B is configured by the periodic arrangement of the linear conductors in the X direction or the Y direction, if the periodic shift of the conductor layer A in the Y direction in group units is eliminated, it becomes difficult to cause the current to flow in both the X and Y directions by the two layers of the conductor layer A and the conductor layer B. However, when the conductor layer A is provided with the periodic shift in the Y direction in group units, a pseudo reticulated structure can be implemented, and the degree of freedom of wiring layout can be increased. For example, in a case where the conductor layer B is a diagonal conductor or a stepped conductor extending in an oblique direction in the X direction or the Y direction, the conductor layer A may not be provided with the periodic shift in the Y direction in group units. Of course, the conductor layer A may be provided with the periodic shift in the Y direction in group units.

By implementing the pseudo-reticulated structure of the three-power supply with the two layers of the conductor layer A and the conductor layer B, the current is easily diffused in the X direction, so that the inductive noise can be improved. Furthermore, the conductor resistance seen from a pad end can be reduced depending on a pad arrangement, so that the voltage drop can be improved.

First Modification of Third Configuration Example of Three-Power Supply

FIGS.232and233illustrate a first modification of the third configuration example of the three-power supply.

In both the coordinate systems inFIGS.232and233, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

A ofFIG.232is a plan view of the conductor layer A, and B ofFIG.232is a plan view of the conductor layer B. Note thatFIG.232may be considered as the entire region of each conductor layer or may be considered as a partial region.

Since the conductor layer A in A inFIG.232is the same as the conductor layer A of the third configuration example illustrated in A inFIG.228, description thereof will be omitted.

The conductor layer B in B inFIG.232is different from the conductor layer B of the third configuration example illustrated in B inFIG.228in that the conductor widths of the Vdd conductor, the Vss1conductor, and the Vss2conductor are smaller.

Specifically, the conductor layer B is configured by arranging three linear conductors2221to2223, which are long in the X direction, in the Y direction in a predetermined order, and periodically arranging the three linear conductors2221to2223in the Y direction.

The linear conductor2221is wiring (Vdd wiring) connected to the first power supply Vdd. The linear conductor2222is wiring (Vss1wiring) connected to the second power supply Vss1. The linear conductor2223is wiring (Vss2wiring) connected to the third power supply Vss2.

Therefore, in B inFIG.232, the three linear conductors2221to2223are arranged in the positive direction of the Y axis in the order of the Vdd wiring, Vss2wiring, and Vss1wiring, but the order of arranging the three linear conductors2221to2223is not limited to this example and can be any order.

The linear conductor2221has a conductor width WYBD in the Y direction, the linear conductor2222has a conductor width WYBS1 in the Y direction, and the linear conductor2223has a conductor width WYBS2 in the Y direction. The conductor width WYBD of the linear conductor2221, the conductor width WYBS1 of the linear conductor2222, and the conductor width WYBS2 of the linear conductor2223are, for example, the same (the conductor width WYBD=the conductor width WYBS1=the conductor width WYBS2). A gap with the gap width GYB is formed between two adjacent linear conductors of the linear conductors2221to2223.

The conductor width WYBD of the linear conductor2221, the conductor width WYBS1 of the linear conductor2222, and the conductor width WYBS2 of the linear conductor2223are smaller than the conductor width WYBD of the linear conductor2191, the conductor width WYBS1 of the linear conductor2192, and the conductor width WYBS2 of the linear conductor2193in the third configuration example illustrated in B inFIG.228. For example, the conductor width WYBD, the conductor width WYBS1, and the conductor width WYBS2 have the same width as the gap width GYB in B inFIG.232.

The linear conductor2221is periodically arranged in the Y direction with a conductor period FYBD. The linear conductor2222is periodically arranged in the Y direction with a conductor period FYBS1, and the linear conductor2223is periodically arranged in the Y direction with a conductor period FYBS2. The conductor period FYBD, the conductor period FYBS1, and the conductor period FYBS2 are, for example, the same (the conductor period FYBD=the conductor period FYBS1=the conductor period FYBS2).

Therefore, in a rectangular region within a predetermined range of the conductor layer B, the sum of the conductor widths WYBD in the Y direction of the linear conductors2221connected to the first power supply Vdd, the sum of the conductor widths WYBS1 in the Y direction of the linear conductors2222connected to the second power supply Vss1, and the sum of the conductor widths WYBS2 in the Y direction of the linear conductors2223connected to the third power supply Vss2are the same.

Furthermore, in a rectangular region within a predetermined range of the conductor layer B, the conductive area of the linear conductor2221connected to the first power supply Vdd, the conductive area of the linear conductor2222connected to the second power supply Vss1, and the conductive area of the linear conductor2223connected to the third power supply Vss2are the same.

FIG.233is a plan view illustrating a stacked state of the conductor layer A in A inFIG.232and the conductor layer B in B inFIG.232.

As illustrated inFIG.233, the stacked layer of the conductor layer A and the conductor layer B cannot implement a perfect light-shielding structure but can have a certain degree of light-shielding property, the conductor layer A having the three columns in which the Y-direction positions of the rectangular Vdd conductor, the rectangular Vss1conductor, and the rectangular Vss2conductor are shifted for each column as one group, and having the Y-direction positions of the rectangular conductors shifted in group units, and the conductor layer B having the periodic arrangement of the linear conductors2221to2223long in the X direction.

The linear conductors connected to the same power supply of the conductor layers A and B may be electrically connected via a conductor via extending in the Z direction or the like in a predetermined partial region where the positions overlap. From the viewpoint of voltage drop, it is desirable, but not limited to, that the linear conductors connected to the same power supply be electrically connected to each other.

As in the first modification of the third configuration example, the conductor widths of the linear conductors of the conductor layer B may be made extremely small so that the conductor widths of the conductor layer A and the conductor layer B become different. In this case, the conductor period of the conductor layer B is also smaller than the conductor period of the conductor layer A. Since the area of an Aggressor loop that generates a magnetic field becomes smaller as the conductor period becomes shorter, the inductive noise can be improved.

Second Modification of Third Configuration Example of Three-Power Supply

FIG.234illustrates a second modification of the third configuration example of the three-power supply.

In the coordinate system inFIG.234, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

A ofFIG.234is a plan view of the conductor layer A, and B ofFIG.234is a plan view of the conductor layer B. Note thatFIG.234may be considered as the entire region of each conductor layer or may be considered as a partial region. In the third modification of the second configuration example, the plan view illustrating a stacked state of the conductor layer A and the conductor layer B is omitted.

Comparing the conductor layer A in A inFIG.234with the conductor layer A of the third configuration example illustrated in A inFIG.228, both the conductor layers A satisfy the relationship of “(the conductor width WYAD+the gap width GYA)=(the conductor width WYAS1+the gap width GYA)=(the conductor width WYAS2+the gap width GYA)=(5×the conductor period FYBD)=(5×the conductor period FYBS1)=(5×the conductor period FYBS2)”, but the periodic shift in the Y direction for each group is different.

That is, in the conductor layer A of the third configuration example illustrated in A inFIG.228, the group configured by the adjacent three columns is shifted from another group adjacent on the positive side of the X axis by ½ of the rectangular conductor period in the Y direction so that the gap position comes to the middle in the Y direction of the gap positions of the adjacent group.

In contrast, in the conductor layer A illustrated in A inFIG.234, the gap position of another group adjacent on the positive side of the X axis is shifted by twice the conductor period FYBD (≠½ of the rectangular conductor period in the Y direction) in the positive direction of the Y axis with respect to a predetermined group configured by adjacent three columns. The another group adjacent on the positive side of the X axis is regularly shifted in the positive direction of the Y axis by twice the conductor period FYBD (≠½ of the rectangular conductor period in the Y direction) with respect to the predetermined group that is a reference group. As described above, in the case where the relationship of “(the conductor width WYAD+the gap width GYA)=(the conductor width WYAS1+the gap width GYA)=(the conductor width WYAS2+the gap width GYA)=(an integer N1×the conductor period FYBD)=(an integer N1×the conductor period FYBS1)=(an integer N1×the conductor period FYBS2)” is satisfied and the amount of shift in the positive direction of the Y axis is “an integer N2×the conductor period FYBD”, the number of linear conductors2221connected to the rectangular conductor2211, the number of linear conductors2222connected to the rectangular conductor2212, and the number of linear conductors2223connected to the rectangular conductor2213can be made the same in a rectangular region in a predetermined range. In other words, in a rectangular region within a predetermined range, the sum of the conductive areas of the linear conductors2221connected to the rectangular conductor2211, the sum of the conductive areas of the linear conductors2222connected to the rectangular conductor2212, and the sum of the conductive areas of the linear conductors2223connected to the rectangular conductor2213can be made the same. In such a case, the current distributions of the Vdd conductor, the Vss1conductor, and the Vss2conductor can be brought close to the same current distribution. Therefore, the inductive noise can be improved. Note that, to cause the current to flow in both the X and Y directions without using diagonal conductors or stepped conductors, the condition of “(the conductor width WYAD+the gap width GYA)=(the conductor width WYAS1+the gap width GYA)=(the conductor width WYAS2+the gap width GYA)>(the conductor period FYBD=the conductor period FYBS1=the conductor period FYBS2)” needs to be satisfied. That is, “the integer N1>1” is desirable, but to cause the current to flow in both the X and Y directions, a condition of “the integer N1>the integer N2≥1” needs to be satisfied. Note that these relationships need not be satisfied as long as an acceptable level of the inductive noise is satisfied.

Since the conductor layer B in B inFIG.234is the same as the conductor layer B of the first modification of the third configuration example illustrated in B inFIG.232, description thereof will be omitted.

Third Modification of Third Configuration Example of Three-Power Supply

FIG.235illustrates a third modification of the third configuration example of the three-power supply.

In the coordinate system inFIG.235, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

A ofFIG.235is a plan view of the conductor layer A, and B ofFIG.235is a plan view of the conductor layer B. Note thatFIG.235may be considered as the entire region of each conductor layer or may be considered as a partial region. In the third modification of the third configuration example, the plan view illustrating a stacked state of the conductor layer A and the conductor layer B is omitted.

The conductor layer A in A inFIG.235is different from the conductor layer A of the third configuration example illustrated in A inFIG.228in that the periodic shift in the Y direction in group units is different.

That is, in the conductor layer A of the third configuration example illustrated in A inFIG.228, the group configured by the adjacent three columns is shifted from another group adjacent on the positive side of the X axis by ½ of the rectangular conductor period in the Y direction so that the gap position comes to the middle in the Y direction of the gap positions of the adjacent group.

In contrast, in the conductor layer A illustrated in A inFIG.235, the gap position of another group adjacent on the positive side of the X axis is shifted by twice the conductor period FYBD (≠½ of the rectangular conductor period in the Y direction) with respect to a predetermined group configured by adjacent three columns.

Note that, in the second modification illustrated inFIG.234, the arrangement of shifting another group adjacent on the positive side of the X axis by twice the conductor period FYBD in the positive direction of the Y axis and the arrangement of shifting the another group by twice the conductor period FYBD in the negative direction of the Y axis are alternately arranged with respect to the predetermined reference group, whereas in the third modification inFIG.235, another group adjacent on the positive side of the X axis is always shifted by twice the conductor period FYBD in the positive direction of the Y axis.

Since the conductor layer B in B inFIG.235is the same as the conductor layer B of the first modification of the third configuration example illustrated in B inFIG.232, description thereof will be omitted.

As in the third modification and the fourth modification, the periodic shift in the Y direction in group units may be in the positive direction or the negative direction, or may be any combination of the positive direction and the negative direction. Although a plan view illustrating a stacked state of the conductor layer A and the conductor layer B is omitted, a pseudo-reticulated structure of the three-power supply can be implemented by the two layers of the conductor layer A and the conductor layer B, as inFIGS.230and231, and the current is easily diffused in the X direction, so that the inductive noise can be improved. Furthermore, the degree of freedom of wiring layout can be increased. Moreover, the conductor resistance seen from a pad end can be reduced, so that the voltage drop can be improved, depending on the pad arrangement.

Fourth Modification and Fifth Modification of Third Configuration Example of Three-Power Supply

FIG.236illustrates a fourth modification and a fifth modification of the third configuration example of the three-power supply.

In the coordinate system inFIG.236, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

Both A and B inFIG.236illustrate plan views of the conductor layer A. A ofFIG.236is a plan view of the conductor layer A of the fourth modification of the third configuration example, and B ofFIG.236is a plan view of the conductor layer A of the fifth modification of the third configuration example.

Although plan views of the conductor layer B are omitted, the conductor layer B is, for example, the conductor layer B of the third configuration example illustrated in B inFIG.228or the conductor layer B of the first modification of the third configuration example illustrated in B inFIG.232. A plan view illustrating a stacked state of the conductor layer A and the conductor layer B is also omitted.

The conductor layer A of the fourth modification illustrated in A inFIG.236and the conductor layer A of the fifth modification illustrated in B inFIG.236are common to the conductor layer A of the third modification of the third configuration example illustrated in A inFIG.235in that three columns in each of which the Y-direction positions of the rectangular Vdd conductor, the rectangular Vss1conductor, and the rectangular Vss2conductor are shifted for each column are formed into a group, and the Y-direction positions of the rectangular conductors are shifted in group units.

Meanwhile, in the conductor layer A of the third modification of the third configuration example illustrated in A inFIG.235, the conductor widths in the X direction of the rectangular Vdd conductor, the rectangular Vss1conductor, and the rectangular Vss2conductor are the same. In contrast, in the conductor layer A of the fourth modification in A inFIG.236, the conductor width in the X direction of the rectangular Vss2conductor is smaller than the conductor widths in the X direction of the rectangular Vdd conductor and the rectangular Vss1conductor.

More specifically, a rectangular conductor2251(hereinafter referred to as a rectangular Vdd conductor2251) connected to the first power supply Vdd has the conductor width WXAD in the X direction and the conductor width WYAD in the Y direction. A rectangular conductor2252(hereinafter referred to as a rectangular Vss1conductor2252) connected to the second power supply Vss1has the conductor width WXAS1 in the X direction and the conductor width WYAS1 in the Y direction. A rectangular conductor2253(hereinafter referred to as a rectangular Vss2conductor2253) connected to the third power supply Vss2has the conductor width WXAS2 in the X direction and the conductor width WYAS2 in the Y direction. Then, the conductor width WXAD in the X direction of the rectangular Vdd conductor2251is equal to the conductor width WXAS1 in the X direction of the rectangular Vss1conductor2252, and the conductor width WXAS2 in the X direction of the rectangular Vss2conductor2253is smaller than the conductor width WXAD and the conductor width WXAS1.

Meanwhile, in the conductor layer A of the fifth modification in B inFIG.236, the conductor widths in the X direction of both the rectangular Vss1conductor and the rectangular Vss2conductor are smaller than the conductor width in the X direction of the rectangular Vdd conductor.

More specifically, the conductor width WXAS1 in the X direction of the rectangular Vss1conductor2252and the conductor width WXAS2 in the X direction of the rectangular Vss2conductor2253are equal, and the conductor width WXAS1 and the conductor width WXAS2 are smaller than the conductor width WXAD in the X direction of the rectangular Vdd conductor2251(the conductor width WXAD>the conductor width WXAS1=the conductor width WXAS2).

As described above, the conductor widths in the X direction of the rectangular Vdd conductor, the rectangular Vss1conductor, and the rectangular Vss2conductor may be the same or different. Although not illustrated, the conductor width WXAS1 in the X direction of the rectangular Vss1conductor2252may be smaller than the conductor width WXAD in the X direction of the rectangular Vdd conductor2251, and the conductor width WXAS2 in the X direction of the rectangular Vss2conductor2253may be smaller than the conductor width WXAS1 in the X direction of the rectangular Vss1conductor2252(the conductor width WXAD>the conductor width WXAS1>the conductor width WXAS2).

When the conductor width of the Vss2conductor becomes smaller, the Vdd conductor and the Vss1conductor can be arranged densely, which leads to improvement of the voltage drop of the Vdd conductor and the Vss1conductor when a comparison is performed on the assumption that the wiring regions have the same area. When the conductor widths of both the Vss1conductor and the Vss2conductor in the X direction become small, which leads to improvement of the voltage drop of the Vdd conductor when a comparison is performed on the assumption that the wiring regions have the same area. Furthermore, since the area of an Aggressor loop that generates a magnetic field becomes smaller as the conductor period becomes shorter, the inductive noise can be improved.

Fourth Configuration Example of Three-Power Supply

FIGS.237and238illustrate a fourth configuration example of the three-power supply.

In both the coordinate systems inFIGS.237and238, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

A ofFIG.237is a plan view of the conductor layer A, and B ofFIG.237is a plan view of the conductor layer B. Note thatFIG.237may be considered as the entire region of each conductor layer or may be considered as a partial region.

The conductor layer A is common to the conductor layer A of the third configuration example illustrated in A inFIG.228in that the set of the rectangular Vdd conductor2211, the rectangular Vss1conductor2212, and the rectangular Vss2conductor2213is arrayed in the X direction and in the Y direction, but is different from the conductor layer A of the third configuration example in a rule of the array.

Specifically, the conductor layer A of the fourth configuration example is configured by periodically arranging in the X direction with the rectangular conductor period in the X direction, the column in which the set of the rectangular Vdd conductor2211, the rectangular Vss1conductor2212, and the rectangular Vss2conductor2213is periodically arranged in the Y direction. Comparing the gap positions between a predetermined column of the conductor layer A and another column adjacent on the positive side of the X axis, the gap position of the rectangular conductors is shifted by ½ of the rectangular conductor period in the Y direction so that the gap position of the rectangular conductors comes to the middle in the Y direction of the gap positions of the adjacent column. Thereby, the conductor layer A has a pseudo stepped structure in which the positions in the Y direction of the rectangular Vdd conductor2211, the rectangular Vss1conductor2212, and the rectangular Vss2conductor2213of each column are shifted by ½ of the rectangular conductor period in the Y direction on the positive side of the Y axis as the positions go to the positive side of the X axis. Note that the amount of shift of the rectangular conductor period in the Y direction is not necessarily ½ of the rectangular conductor period in the Y direction, and an integral multiple of the conductor period FYBD is desirable and the amount of shift can be designed to any value.

Meanwhile, since the conductor layer B in B inFIG.237is the same as the conductor layer B of the third configuration example illustrated in B inFIG.228, description thereof will be omitted.

FIG.238is a plan view illustrating a stacked state of the conductor layer A in A inFIG.237and the conductor layer B in B inFIG.237.

As illustrated inFIG.238, the stacked layer of the conductor layer A and the conductor layer B cannot implement a perfect light-shielding structure but can have a certain degree of light-shielding property, the conductor layer A having a column shifted in a pseudo stepwise manner and periodically arranged in the positive direction of the X axis, the column having the set of the rectangular Vdd conductor2211, the rectangular Vss1conductor2212, and the rectangular Vss2conductor2213periodically arranged in the Y direction, and the conductor layer B having the periodic arrangement of the linear conductors2191to2193long in the X direction.

The linear conductors connected to the same power supply of the conductor layers A and B may be electrically connected via a conductor via extending in the Z direction or the like in a predetermined partial region where the positions overlap. From the viewpoint of voltage drop, it is desirable, but not limited to, that the linear conductors connected to the same power supply be electrically connected to each other.

A ofFIG.239is a plan view illustrating a stacked state of only the rectangular Vdd conductor2211and the linear conductor2191as the Vdd conductors of the conductor layer A and the conductor layer B.

B ofFIG.239is a plan view illustrating a stacked state of only the rectangular Vss1conductor2212and the linear conductor2192as the Vss1conductors of the conductor layer A and the conductor layer B.

FIG.240is a plan view illustrating a stacked state of only the rectangular Vss2conductor2213and the linear conductor2193as the Vss2conductors of the conductor layer A and the conductor layer B.

According to the fourth configuration example of the three-power supply, in the case of electrically connecting the conductors connected to the same power supply of the conductor layers A and B by a conductor via in the Z direction or the like by the configuration of shifting the Y-directional positions of the rectangular conductors in column units so that the Y-directional positions of the rectangular conductors connected to the power supplies form a stepped shape, the pseudo reticulated structure can be configured by the two layers of the conductor layers A and B, as illustrated inFIGS.239and240. Therefore, the current can flow in both the X and Y directions, and the degree of freedom of wiring layout can be enhanced.

By implementing the pseudo-reticulated structure of the three-power supply with the two layers of the conductor layer A and the conductor layer B, the current is easily diffused in the X direction, so that the inductive noise can be improved. Furthermore, the conductor resistance seen from a pad end can be reduced depending on a pad arrangement, so that the voltage drop can be improved.

Fifth Configuration Example of Three-Power Supply

FIGS.241and242illustrate a fifth configuration example of the three-power supply.

In both the coordinate systems inFIGS.241and242, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

A ofFIG.241is a plan view of the conductor layer A, and B ofFIG.241is a plan view of the conductor layer B. Note thatFIG.241may be considered as the entire region of each conductor layer or may be considered as a partial region.

The conductor layer A in A inFIG.241is configured such that a group of three columns is periodically arranged in the X direction. The three columns include one column of one linear conductor2271connected to the first power supply Vdd and two columns in which a rectangular conductor2272(hereinafter referred to as a rectangular Vss1conductor2272) connected to the second power supply Vss1and a rectangular conductor2273(hereinafter referred to as a rectangular Vss2conductor2273) connected to the third power supply Vss2are alternately arranged in the Y direction, which are adjacent to the linear conductor2271on both sides.

The linear conductor2171is arranged extending in the Y direction with the conductor width WXAD in the X direction. The rectangular Vss1conductor2272has the conductor width WXAS1 in the X direction and the conductor width WYAS1 in the Y direction. The rectangular Vss2conductor2273has the conductor width WXAS2 in the X direction and the conductor width WYAS2 in the Y direction. The conductor width WXAD, the conductor width WXAS1, and the conductor width WXAS2 in the X direction are, for example, the same (the conductor width WXAD=the conductor width WYAS1=the conductor width WYAS2). A gap with the gap width GXA in the X direction and the gap width GYB in the Y direction is formed between adjacent conductors.

Focusing on the arrangement of the rectangular Vss1conductor2272and the rectangular Vss2conductor2273arranged in the columns on both sides in the three columns forming one group, the rectangular Vss1conductor2272and the rectangular Vss2conductor2273are arranged on both sides of the linear conductor2271at the same Y position such that the rectangular Vss1conductor2272is arranged at a position in one column and the rectangular Vss2conductor2273is arranged at a position corresponding to the position in the other column. Furthermore, the gap positions in the Y direction of the two columns of the rectangular Vss1conductor2272and the rectangular Vss2conductor2273on both sides are the same.

Moreover, focusing on the arrangements of the rectangular Vss1conductors2272and the rectangular Vss2conductors2273of two groups adjacent in the X direction, the Y-direction positions of the rectangular Vss1conductors2272and the rectangular Vss2conductors2273of the adjacent two groups are shifted to each other by ½ of the rectangular conductor period in the Y direction.

Since the conductor layer B in B inFIG.241is the same as the conductor layer B of the third configuration example illustrated in B inFIG.228, description thereof will be omitted.

FIG.242is a plan view illustrating a stacked state of the conductor layer A in A inFIG.241and the conductor layer B in B inFIG.241.

As illustrated inFIG.242, the stacked layer of the conductor layer A and the conductor layer B cannot implement a perfect light-shielding structure but can have a certain degree of light-shielding property, the conductor layer A having the group of three columns periodically arranged in the X direction, the three columns including one column of the linear conductor2271long in the Y direction, and the two columns in which the rectangular Vss1conductor2272and the rectangular Vss2conductor2273are alternately arranged, which are arranged on both sides of the linear conductor2271, and the conductor layer B having the periodic arrangement in the Y direction of the linear conductors2191to2193long in the X direction.

The conductors of the conductor layers A and B connected to the same power supply may be electrically connected to each other via a conductor via in the Z direction or the like in a predetermined partial region where the positions overlap. From the viewpoint of voltage drop, it is desirable, but not limited to, that the conductor layers A and B connected to the same power supply be electrically connected to each other.

A ofFIG.243is a plan view illustrating a stacked state of only the linear conductor2271and the linear conductor2191as the Vdd conductors of the conductor layer A and the conductor layer B.

B ofFIG.243is a plan view illustrating a stacked state of only the rectangular Vss1conductor2272and the linear conductor2192as the Vss1conductors of the conductor layer A and the conductor layer B.

FIG.244is a plan view illustrating a stacked state of only the rectangular Vss2conductor2273and the linear conductor2193as the Vss2conductors of the conductor layer A and the conductor layer B.

According to the fifth configuration example of the three-power supply, in the case of electrically connecting the conductors connected to the same power supply of the conductor layers A and B, the reticulated structure can be configured by the two layers of the conductor layers A and B for the Vdd conductor, and the pseudo reticulated structure can be configured by the two layers of the conductor layers A and B for the Vss1conductor and the Vss2conductor, as illustrated inFIGS.243and244. Therefore, the current can flow in both the X and Y directions, and the degree of freedom of wiring layout can be enhanced. The Vdd conductor, which is commonly used in the configuration where the second power supply Vss1and the third power supply Vss2are selected and switched, has the reticulated structure, and the Vss1conductor and the Vss2conductor have the pseudo-reticulated structure, whereby the commonly used Vdd conductor can have a smaller voltage drop than the Vss1and Vss2conductors. By improving the voltage drop of the Vdd conductor, which is a commonly used element, the voltage drop of the stacked conductor layer as a whole can be improved.

By implementing the pseudo-reticulated structure of the three-power supply with the two layers of the conductor layer A and the conductor layer B, the current is easily diffused in the X direction, so that the inductive noise can be improved. Furthermore, the conductor resistance seen from a pad end can be reduced depending on a pad arrangement, so that the voltage drop can be improved.

First Modification of Fifth Configuration Example of Three-Power Supply

FIGS.245and246illustrate a first modification of the fifth configuration example of the three-power supply.

In both the coordinate systems inFIGS.245and246, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

A ofFIG.245is a plan view of the conductor layer A, and B ofFIG.245is a plan view of the conductor layer B. Note thatFIG.245may be considered as the entire region of each conductor layer or may be considered as a partial region.

The conductor layer A in A inFIG.245is common to the conductor layer A of the fifth configuration example illustrated in A inFIG.241in periodically arranging the group of three columns in the X direction, the three columns including one column of the linear conductor2271long in the Y direction and the two columns in which the rectangular Vss1conductor2272and the rectangular Vss2conductor2273are alternately arranged, which are arranged on both sides of the linear conductor2271.

However, the arrangement of the two columns of the rectangular Vss1conductor2272and the rectangular Vss2conductor2273on both sides of the linear conductor2271long in the Y direction is different from the conductor layer A of the fifth configuration example illustrated in A inFIG.241.

That is, in the conductor layer A of the fifth configuration example illustrated in A inFIG.241, the gap positions in the Y direction of the rectangular Vss1conductor2272and the rectangular Vss2conductor2273arranged on both sides of the linear conductor2271long in the Y direction are the same.

Meanwhile, in the conductor layer A in A inFIG.245, the gap positions in the Y direction of the rectangular Vss1conductor2272and the rectangular Vss2conductor2273arranged on both sides of the linear conductor2271long in the Y direction are different. Specifically, the gap position in the Y direction of the right column and the gap position in the Y direction of the left column are shifted by ½ of the rectangular conductor period in the Y direction. Note that the amount of shift of the rectangular conductor period in the Y direction is not necessarily ½ of the rectangular conductor period in the Y direction, and an integral multiple of the conductor period FYBD is desirable and the amount of shift can be designed to any value.

Furthermore, focusing on the arrangements of the rectangular Vss1conductors2272and the rectangular Vss2conductors2273of two groups adjacent in the X direction, where the linear conductor2271long in the Y direction and the two columns on both sides of the linear conductor2271are formed into one group, the arrangements of the rectangular Vss1conductors2272and the rectangular Vss2conductors2273of the adjacent two groups are opposite.

Since the conductor layer B in B inFIG.245is the same as the conductor layer B of the fifth configuration example illustrated in B inFIG.241, description thereof will be omitted.

FIG.246is a plan view illustrating a stacked state of the conductor layer A in A inFIG.245and the conductor layer B in B inFIG.245.

As illustrated inFIG.246, the stacked layer of the conductor layer A and the conductor layer B cannot implement a perfect light-shielding structure but can have a certain degree of light-shielding property, the conductor layer A having the group of three columns periodically arranged in the X direction, the three columns including one column of the linear conductor2271long in the Y direction, and the two columns in which the rectangular Vss1conductor2272and the rectangular Vss2conductor2273are alternately arranged, which are arranged on both sides of the linear conductor2271, and the conductor layer B having the periodic arrangement of the linear conductors2191to2193long in the X direction.

The conductors of the conductor layers A and B connected to the same power supply may be electrically connected to each other via a conductor via in the Z direction or the like in a predetermined partial region where the positions overlap. From the viewpoint of voltage drop, it is desirable, but not limited to, that the conductor layers A and B connected to the same power supply be electrically connected to each other.

Even in the first modification of the fifth configuration example, in the case of electrically connecting the conductors connected to the same power supply of the conductor layers A and B, the reticulated structure can be configured by the two layers of the conductor layers A and B for the Vdd conductor, and the pseudo reticulated structure can be configured by the two layers of the conductor layers A and B for the Vss1conductor and the Vss2conductor. Therefore, the current can flow in both the X and Y directions, and the degree of freedom of wiring layout can be enhanced. The Vdd conductor, which is commonly used in the configuration where the second power supply Vss1and the third power supply Vss2are selected and switched, has the reticulated structure, and the Vss1conductor and the Vss2conductor have the pseudo-reticulated structure, whereby the commonly used Vdd conductor can have a smaller voltage drop than the Vss1and Vss2conductors. By improving the voltage drop of the Vdd conductor, which is a commonly used element, the voltage drop of the stacked conductor layer as a whole can be improved.

By implementing the pseudo-reticulated structure of the three-power supply with the two layers of the conductor layer A and the conductor layer B, the current is easily diffused in the X direction, so that the inductive noise can be improved. Furthermore, the conductor resistance seen from a pad end can be reduced depending on a pad arrangement, so that the voltage drop can be improved.

Second Modification and Third Modification of Fifth Configuration Example of Three-Power Supply

FIG.247illustrates a second modification and a third modification of the fifth configuration example of the three-power supply.

In the coordinate system inFIG.247, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

Both A and B inFIG.247illustrate plan views of the conductor layer A. A ofFIG.247is a plan view of the conductor layer A of the second modification of the fifth configuration example, and B ofFIG.247is a plan view of the conductor layer A of the third modification of the fifth configuration example.

Although a plan view of the conductor layer B is omitted, the conductor layer B is the same as the conductor layer B of the fifth configuration example illustrated in B inFIG.241, for example. A plan view illustrating a stacked state of the conductor layer A and the conductor layer B is also omitted.

In the conductor layer A of the second modification in A inFIG.247, the conductor widths in the X direction of both the rectangular Vss1conductor and the rectangular Vss2conductor are smaller than the conductor width in the X direction of the rectangular Vdd conductor.

That is, in the conductor layer A of the fifth configuration example illustrated in A inFIG.241, the conductor width WXAD in the X direction of the linear conductor2171, the conductor width WXAS1 in the X direction of the rectangular Vss1conductor2272, and the conductor width WXAS2 in the X direction of the rectangular Vss2conductor2273are the same (the conductor width WXAD=the conductor width WYAS1=the conductor width WYAS2),

In contrast, in the conductor layer A of the second modification in A inFIG.247, the conductor width WXAS1 in the X direction of the rectangular Vss1conductor2272and the conductor width WXAS2 in the X direction of the rectangular Vss2conductor2273are equal, and the conductor width WXAS1 and the conductor width WXAS2 are smaller than the conductor width WXAD in the X direction of the linear conductor2171(the conductor width WXAD>the conductor width WXAS1=the conductor width WXAS2). Other configurations are similar to those of the conductor layer A of the fifth configuration example illustrated in A inFIG.241.

Note that, in the conductor layer A in A inFIG.247, the conductor width WXAS1 in the X direction of the rectangular Vss1conductor2272and the conductor width WXAS2 in the X direction of the rectangular Vss2conductor2273are the same but may be made different. That is, the conductor width WXAS1 in the X direction of the rectangular Vss1conductor2272may be made smaller than the conductor width WXAD in the X direction of the linear conductor2171, and the conductor width WXAS2 in the X direction of the rectangular Vss2conductor2273may be made smaller than the conductor width WXAS1 in the X direction of the rectangular Vss1conductor2272(the conductor width WXAD>the conductor width WXAS1>the conductor width WXAS2).

According to the second modification in A inFIG.247, the Vss1conductor and the Vss2conductor can be densely arranged by reducing the conductor width in the X direction. Therefore, the inductive noise can be improved, and the voltage drop may be able to be improved by reducing the conductor period in the X direction. By making the commonly used Vdd conductor less likely to have a voltage drop, the voltage drop of both the combination of the Vdd conductor and the Vss1conductor and the combination of the Vdd conductor and the Vss2conductor may be able to be improved.

The reticulated structure can be configured by the two layers of the conductor layers A and B for the Vdd conductor, and the pseudo reticulated structure can be configured by the two layers of the conductor layers A and B for the Vss1conductor and the Vss2conductor. Therefore, the current can flow in both the X and Y directions, and the degree of freedom of wiring layout can be enhanced.

Meanwhile, the conductor layer A in B inFIG.247is configured such that a group of three columns is periodically arranged in the X direction. The three columns include one column of one linear conductor2283connected to the third power supply Vss2and two columns in which a rectangular conductor2281(hereinafter referred to as a rectangular Vdd conductor2281) connected to the first power supply Vdd connected to the first power supply Vdd and a rectangular conductor2282(hereinafter referred to as a rectangular Vss1conductor2282) connected to the second power supply Vss1are alternately arranged in the Y direction, which are adjacent to the linear conductor2283on both sides.

Therefore, the conductor layer A of the third modification in B inFIG.247has a configuration in which the arrangement of the Vdd conductor, the Vss1conductor, and the Vss2conductor of the conductor layer A of the fifth configuration example illustrated in A inFIG.241is rearranged, where the middle column of the three columns forming one group is not the Vdd conductor but the Vss2conductor, and the Vdd conductor and the Vss1conductor are arranged on both sides of the Vss2conductor. Since the Vdd conductor and the Vss1conductor are alternately arranged in the Y direction, the capacitive noise can be canceled.

Furthermore, according to the third modification in B inFIG.247, by implementing a pseudo-reticulated structure of three-power supply with the two layers of the conductor layer A and the conductor layer B, the current is easily diffused in the X direction, so that the inductive noise can be improved. Furthermore, the conductor resistance seen from a pad end can be reduced depending on a pad arrangement, so that the voltage drop can be improved.

Sixth Configuration Example of Three-Power Supply

Next, a configuration example in which a three-power supply is implemented using three wiring layers (wiring layers165A to165C) will be described.

FIG.248illustrates a sixth configuration example of the three-power supply.

In the coordinate system inFIG.248, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

A inFIG.248illustrates the conductor layer A (wiring layer165A), B inFIG.248illustrates the conductor layer B (wiring layer165B), and C inFIG.248illustrates the conductor layer C (wiring layer165C).

Furthermore, D inFIG.248is a plan view of a stacked state of the conductor layer A and the conductor layer B, E inFIG.248is a plan view of a stacked state of the conductor layer A and the conductor layer C, and F inFIG.248is a plan view of a stacked state of the conductor layer B and the conductor layer C. Note thatFIG.248may be considered as the entire region of each conductor layer or may be considered as a partial region.

The conductor layer A in A inFIG.248includes a reticulated conductor2301. That is, the reticulated conductor2301has the conductor width WXA, the gap width GXA, and the conductor period FXA in the X direction, and the conductor width WYA, the gap width GYA, and the conductor period FYA in the Y direction. The reticulated conductor2301is a conductor having a shape in which basic patterns of the conductor period FXA and the conductor period FYA are repeatedly arranged on the same plane. The reticulated conductor2301is, for example, wiring (Vss1wiring) connected to the second power supply Vss1.

The conductor layer B in B inFIG.248includes a reticulated conductor2302. That is, the reticulated conductor2302has the conductor width WXB, the gap width GXB, and the conductor period FXB in the X direction, and the conductor width WYB, the gap width GYB, and the conductor period FYB in the Y direction. The reticulated conductor2302is a conductor having a shape in which basic patterns of the conductor period FXB and the conductor period FYB are repeatedly arranged on the same plane. The reticulated conductor2302is, for example, wiring (Vdd wiring) connected to the first power supply Vdd. The conductor periods of the reticulated conductor2301and the reticulated conductor2302are, for example, the same, and the conductor period FXA=the conductor period FXB, and the conductor period FYA=the conductor period FYB.

The conductor layer C in C inFIG.248includes a reticulated conductor2303. That is, the reticulated conductor2303has the conductor width WXC, the gap width GXC, and the conductor period FXC in the X direction, and the conductor width WYC, the gap width GYC, and the conductor period FYC in the Y direction. The reticulated conductor2303is a conductor having a shape in which basic patterns of the conductor period FXC and the conductor period FYC are repeatedly arranged on the same plane. The reticulated conductor2303is, for example, wiring (Vss2wiring) connected to the third power supply Vss2. The conductor periods of the reticulated conductor2301and the reticulated conductor2303are, for example, the same, and the conductor period FXB=the conductor period FXC, and the conductor period FYB=the conductor period FYC.

The conductor layers A to C inFIG.248are stacked in order of the conductor layers A, B, and C so that the conductor layer B is arranged in the center, for example. In this case, both the distance between the Vdd conductor and the Vss1conductor and the distance between the Vdd conductor and the Vss2conductor can be reduced, and the inductive noise can be improved. However, the conductor layer B does not necessarily have to be arranged in the middle.

An example is illustrated in which the shapes of the reticulated conductor2301that is the Vss1conductor, the reticulated conductor2302that is the Vdd conductor, and the reticulated conductor2303that is the Vss2conductor are completely matched, but the shapes may be different in other regions.

First Modification of Sixth Configuration Example of Three-Power Supply

FIGS.249to253illustrate first to fifth modifications of the sixth configuration example illustrated inFIG.248.

InFIGS.249to253, the arrangement of the conductor layer A (wiring layer165A), the conductor layer B (wiring layer165B), the conductor layer C (wiring layer165C), the plan view of the stacked state of the conductor layer A and the conductor layer B, the plan view of the stacked state of the conductor layer A and the conductor layer C, and the plan view of the stacked state of the conductor layer B and the conductor layer C is similar to that inFIG.248. This also similarly applies to the coordinate system.

FIG.249illustrates a first modification of the sixth configuration example of the three-power supply.

In the sixth configuration example illustrated inFIG.248, the conductor layer A has been the Vss1conductor connected to the second power supply Vss1and the conductor layer C has been the Vss2conductor connected to the third power supply Vss2, whereas in the first modification inFIG.249, both the conductor layers A and C are the Vss conductors connected to the same power supply Vss (the second power supply Vss1or the third power supply Vss2).

In the example ofFIG.249, the conductor layer A includes a reticulated conductor2301aand the conductor layer C includes a reticulated conductor2301c, and both the reticulated conductors2301aand2301care the same as the reticulated conductor2301connected to the second power supply Vss1.

The conductor layer B in B inFIG.249includes the reticulated conductor2302, as in the sixth configuration example illustrated inFIG.248.

In the first modification of the sixth configuration example, the Vdd conductor of the conductor layer B is sandwiched between the two layers of Vss conductors, so that further improvement in the inductive noise can be expected, and further improvement in the voltage drop can be expected by using the three-layer stacked structure instead of a two-layer stacked structure. Note that It is favorable that the sheet resistance of the conductor layer B and the sheet resistance of the conductor layer A and the conductor layer B combined are substantially the same, but this is not the case.

Second Modification of Sixth Configuration Example of Three-Power Supply

FIG.250illustrates a second modification of the sixth configuration example of the three-power supply.

The conductor layer A in A inFIG.250includes the reticulated conductor2301connected to the second power supply Vss1and a relay conductor2304. The relay conductor2304is arranged in a gap region that is not the conductor of the reticulated conductor2301and is electrically insulated from the reticulated conductor2301, and is electrically connected to, for example, the reticulated conductor2302of the conductor layer B and another conductor layer.

The conductor layer B in B inFIG.250includes the reticulated conductor2302connected to the first power supply Vdd, as in the sixth configuration example illustrated inFIG.248.

The conductor layer C in C inFIG.250includes the reticulated conductor2303connected to the third power supply Vss2and a relay conductor2305. The relay conductor2305is arranged in a gap region that is not the conductor of the reticulated conductor2303and is electrically insulated from the reticulated conductor2303, and is electrically connected to, for example, the reticulated conductor2302of the conductor layer B and another conductor layer.

In the example ofFIG.250, the planar shape of the relay conductor2304and the relay conductor2305is a rectangular shape having a predetermined conductor width having a gap inside, but the shape is not limited to the case and any shape is adopted as long as the shape can be formed inside the gap region.

Third Modification of Sixth Configuration Example of Three-Power Supply

FIG.251illustrates a third modification of the sixth configuration example of the three-power supply.

In the third modification of the sixth configuration example illustrated inFIG.251, the conductor layer A and the conductor layer C are similarly configured to those in the second modification of the sixth configuration example, and only the conductor layer B has a different configuration from that in the second modification of the sixth configuration example.

Specifically, the conductor layer A in A inFIG.251includes the reticulated conductor2301connected to the second power supply Vss1and the relay conductor2304.

The conductor layer B in B inFIG.251is configured by a reticulated conductor2306having a shape in which a column having a rectangular conductor arranged in the Y direction with a predetermined period with a gap, and a column having a rectangular conductor having a predetermined conductor width with a gap inside arranged in the Y direction with a predetermined period with a gap are alternately arranged in the X direction. The reticulated conductor2306is, for example, wiring (Vdd wiring) connected to the first power supply Vdd.

The conductor layer C in C inFIG.251includes the reticulated conductor2303connected to the third power supply Vss2and the relay conductor2305.

Fourth Modification of Sixth Configuration Example of Three-Power Supply

FIG.252illustrates a fourth modification of the sixth configuration example of the three-power supply.

The fourth modification of the sixth configuration example illustrated inFIG.252is a configuration in which the relay conductors of the conductor layer A and the conductor layer C of the second modification of the sixth configuration example illustrated inFIG.250are replaced.

Specifically, the conductor layer A in A inFIG.252includes the reticulated conductor2301connected to the second power supply Vss1and a relay conductor2311. The relay conductor2304of the conductor layer A of the second modification illustrated inFIG.250has been a rectangular conductor having a predetermined conductor width having a gap inside. In contrast, the relay conductor2311of the fourth modification is rectangular conductors distributed in four places in the gap region of the reticulated conductor2301.

The conductor layer B in B inFIG.252includes the reticulated conductor2302connected to the first power supply Vdd, as in the sixth configuration example illustrated inFIG.248.

The conductor layer C in C inFIG.252includes the reticulated conductor2303connected to the third power supply Vss2and a relay conductor2312. The relay conductor2305of the conductor layer C of the second modification illustrated inFIG.250has been a rectangular conductor having a predetermined conductor width having a gap inside. In contrast, the relay conductor2312of the fourth modification is rectangular conductors distributed in four places in the gap region of the reticulated conductor2303.

Fifth Modification of Sixth Configuration Example of Three-Power Supply

FIG.253illustrates a fifth modification of the sixth configuration example of the three-power supply.

The fifth modification of the sixth configuration example illustrated inFIG.253has a configuration in which the common relay conductor is included and the reticulated conductor is replaced with respect to the fourth modification of the sixth configuration example illustrated inFIG.252.

Specifically, the conductor layer A in A inFIG.253includes the reticulated conductor2321connected to the second power supply Vss1and the relay conductor2311. In the reticulated conductor2321, the conductor width WXA in the X direction and the conductor width WYA in the Y direction are thicker than those of the reticulated conductor2301of the fourth modification illustrated inFIG.252, the gap width GXA in the X direction and the gap width GYA in the Y direction are narrowly formed, and the relay conductors2311are arranged in four corners as non-conductor portions of the gap region.

The conductor layer B in B inFIG.253is configured by a reticulated conductor2322having a shape in which a column having a rectangular conductor arranged in the Y direction with a predetermined period with a gap, and a column having a rectangular shape having a predetermined conductor width with a gap inside arranged in the Y direction with a predetermined period with a gap are alternately arranged in the X direction. The reticulated conductor2322is, for example, wiring (Vdd wiring) connected to the first power supply Vdd.

The conductor layer C in C inFIG.253includes a reticulated conductor2323connected to the third power supply Vss2and the relay conductor2312. In the reticulated conductor2323, the conductor width WXC in the X direction and the conductor width WYC in the Y direction are thicker than those of the reticulated conductor2303of the fourth modification illustrated inFIG.252, the gap width GXC in the X direction and the gap width GYC in the Y direction are narrowly formed, and the relay conductors2312are arranged in four corners as non-conductor portions of the gap region.

In the second modification to the fifth modification inFIGS.250to253, the shapes of the conductor layer A and the conductor layer C completely match, and the shapes of the conductor layer A and the conductor layer B and the shapes of the conductor layer B and the conductor layer C do not match. However, the shapes of which two conductor layers match can be arbitrarily designed. Furthermore, the shapes may match in a part and may not match in another part of the regions of the conductor layers.

Seventh Configuration Example of Three-Power Supply

FIG.254illustrates a seventh configuration example of the three-power supply.

In the coordinate system inFIG.254, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

A inFIG.254illustrates the conductor layer A (wiring layer165A), B inFIG.254illustrates the conductor layer B (wiring layer165B), and C inFIG.254illustrates the conductor layer C (wiring layer165C).

Furthermore, D inFIG.254is a plan view of a stacked state of the conductor layer A and the conductor layer B, E inFIG.254is a plan view of a stacked state of the conductor layer A and the conductor layer C, and F inFIG.254is a plan view of a stacked state of the conductor layer B and the conductor layer C. Note thatFIG.254may be considered as the entire region of each conductor layer or may be considered as a partial region.

The conductor layer A in A inFIG.254includes a reticulated conductor2331. That is, the reticulated conductor2331has the conductor width WXA, the gap width GXA, and the conductor period FXA in the X direction, and the conductor width WYA, the gap width GYA, and the conductor period FYA in the Y direction. The reticulated conductor2331is a conductor having a shape in which basic patterns of the conductor period FXA and the conductor period FYA are repeatedly arranged on the same plane. The reticulated conductor2331is, for example, wiring (Vss1wiring) connected to the second power supply Vss1.

The conductor layer B in B inFIG.254includes a reticulated conductor2332. That is, the reticulated conductor2332has the conductor width WXB, the gap width GXB, and the conductor period FXB in the X direction, and the conductor width WYB, the gap width GYB, and the conductor period FYB in the Y direction. The reticulated conductor2332is a conductor having a shape in which basic patterns of the conductor period FXB and the conductor period FYB are repeatedly arranged on the same plane. The reticulated conductor2332is, for example, wiring (Vdd wiring) connected to the first power supply Vdd. The conductor periods of the reticulated conductor2331and the reticulated conductor2332are, for example, the same, and the conductor period FXA=the conductor period FXB, and the conductor period FYA=the conductor period FYB.

The conductor layer C in C inFIG.254includes a reticulated conductor2333. That is, the reticulated conductor2333has the conductor width WXC, the gap width GXC, and the conductor period FXC in the X direction, and the conductor width WYC, the gap width GYC, and the conductor period FYC in the Y direction. The reticulated conductor2333is a conductor having a shape in which basic patterns of the conductor period FXC and the conductor period FYC are repeatedly arranged on the same plane. The reticulated conductor2333is, for example, wiring (Vss2wiring) connected to the third power supply Vss2. The conductor periods of the reticulated conductor2331and the reticulated conductor2333are the same, and the conductor period FXB=the conductor period FXC, and the conductor period FYB=the conductor period FYC.

The positions of the conductor portions of the reticulated conductor2331of the conductor layer A and the reticulated conductor2333of the conductor layer C overlap in both the X and Y directions, but the positions of the conductor portions of the reticulated conductor2331of the conductor layer A and the reticulated conductor2332of the conductor layer B overlap in the X-direction but are shifted in the Y-direction. In other words, the gap region of the reticulated conductor2331of the conductor layer A is located in the conductor portion of the reticulated conductor2332of the conductor layer B, and the gap region of the reticulated conductor2333of the conductor layer C is located in the conductor portion of the reticulated conductor2332of the conductor layer B. Thereby, as illustrated in D and F inFIG.254, the stacked layer of the conductor layer A and the conductor layer B forms a light-shielding structure, and the stacked layer of the conductor layer B and the conductor layer C forms a light-shielding structure. Thereby, the hot carrier light emission can be shielded.

Modification of Seventh Configuration Example of Three-Power Supply

FIG.255illustrates a modification of the seventh configuration example of the three-power supply.

In the coordinate system inFIG.255, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

A inFIG.255illustrates the conductor layer A (wiring layer165A), B inFIG.255illustrates the conductor layer B (wiring layer165B), and C inFIG.255illustrates the conductor layer C (wiring layer165C).

Furthermore, D inFIG.255is a plan view of a stacked state of the conductor layer A and the conductor layer B, E inFIG.255is a plan view of a stacked state of the conductor layer A and the conductor layer C, and F inFIG.255is a plan view of a stacked state of the conductor layer B and the conductor layer C. Note thatFIG.255may be considered as the entire region of each conductor layer or may be considered as a partial region.

The conductor layer A in A inFIG.255includes the reticulated conductor2331connected to the second power supply Vss1and a rectangular relay conductor2341. In other words, the conductor layer A in A inFIG.255has a configuration in which the relay conductor2341is added to the gap region of the reticulated conductor2331illustrated in A inFIG.254, but the gap region of the reticulated conductor2331is formed larger than the reticulated conductor2331in A inFIG.254for arranging the relay conductor2341. The relay conductor2341is arranged in a gap region that is not the conductor of the reticulated conductor2331and is electrically insulated from the reticulated conductor2331, and is electrically connected to, for example, the reticulated conductor2332of the conductor layer B and another conductor layer.

The conductor layer B in B inFIG.255includes the reticulated conductor2332connected to the first power supply Vdd, as in the seventh configuration example illustrated inFIG.254.

The conductor layer C in C inFIG.255includes the reticulated conductor2333connected to the third power supply Vss2and a rectangular relay conductor2342. In other words, the conductor layer C in C inFIG.255has a configuration in which the relay conductor2342is added to the gap region of the reticulated conductor2333illustrated in C inFIG.254, but the gap region of the reticulated conductor2333is formed larger than the reticulated conductor2333in C inFIG.254for arranging the relay conductor2342. The relay conductor2342is arranged in a gap region that is not the conductor of the reticulated conductor2333and is electrically insulated from the reticulated conductor2333, and is electrically connected to, for example, the reticulated conductor2332of the conductor layer B and another conductor layer.

Even in the modification of the seventh configuration example, the stacked layer of the conductor layer A and the conductor layer B forms a light-shielding structure, and the stacked layer of the conductor layer B and the conductor layer C forms a light-shielding structure, as illustrated in D and F inFIG.255. Thereby, the hot carrier light emission can be shielded.

Note that, in the seventh configuration example and its modifications inFIGS.254and255, the light-shielding structure has been implemented by the stacked layer of the two layers. However, a light-shielding structure may be configured by a stacked layer of three layers although a light-shielding structure is not formed by a stacked layer of two layers.

Eighth Configuration Example of Three-Power Supply

FIG.256illustrates an eighth configuration example of the three-power supply.

In the coordinate system inFIG.256, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

A inFIG.256illustrates the conductor layer A (wiring layer165A), B inFIG.256illustrates the conductor layer B (wiring layer165B), and C inFIG.256illustrates the conductor layer C (wiring layer165C).

Furthermore, D inFIG.256is a plan view of a stacked state of the conductor layer A and the conductor layer B, E inFIG.256is a plan view of a stacked state of the conductor layer A and the conductor layer C, and F inFIG.256is a plan view of a stacked state of the conductor layer B and the conductor layer C. Note thatFIG.256may be considered as the entire region of each conductor layer or may be considered as a partial region.

The conductor layer A in A inFIG.256is configured by the reticulated conductor2331connected to the second power supply Vss1, similarly to the seventh configuration example illustrated inFIG.254.

The conductor layer B in B inFIG.256includes the reticulated conductor2332connected to the first power supply Vdd and a rectangular relay conductor2351. In other words, the conductor layer B in B inFIG.256has a configuration in which the relay conductor2351is added to the gap region of the reticulated conductor2332of the seventh configuration example illustrated in B inFIG.254, but the gap region of the reticulated conductor2332is formed larger than the reticulated conductor2332in B inFIG.254for arranging the relay conductor2351. The relay conductor2351is arranged in a gap region that is not the conductor of the reticulated conductor2332and is electrically insulated from the reticulated conductor2332, and is electrically connected to, for example, the reticulated conductor2331of the conductor layer A and a relay conductor2353of the conductor layer C.

The conductor layer C in C inFIG.256includes the reticulated conductor2333connected to the third power supply Vss2and the rectangular relay conductors2352and2353. In other words, the conductor layer C in C inFIG.256has a configuration in which the relay conductors2352and2353are added to the gap region of the reticulated conductor2333of the seventh configuration example illustrated in C inFIG.254, but the gap region of the reticulated conductor2333is formed larger than the reticulated conductor2333in C inFIG.254for arranging the relay conductors2352and2353. The relay conductor2352is arranged in a gap region that is not the conductor of the reticulated conductor2333and is electrically insulated from the reticulated conductor2333, and is electrically connected to, for example, the reticulated conductor2332of the conductor layer B and another conductor layer. The relay conductor2353is arranged in a gap region that is not the conductor of the reticulated conductor2333and is electrically insulated from the reticulated conductor2333, and is electrically connected to, for example, the relay conductor2351of the conductor layer B and another conductor layer.

The positions of the conductor portions of the reticulated conductor2331of the conductor layer A and the reticulated conductor2332of the conductor layer B partially overlap in the X direction but are shifted in the Y direction. Thereby, the stacked layer of the conductor layer A and the conductor layer B forms a light-shielding structure. Furthermore, the positions of the conductor portions of the reticulated conductor2331of the conductor layer A and the reticulated conductor2333of the conductor layer C are shifted in both the X and Y directions. Thereby, the stacked layer of the conductor layer A and the conductor layer C forms a light-shielding structure. Thereby, the hot carrier light emission can be shielded.

In the eighth configuration example inFIG.256, the X-direction positions of the conductor portions of the reticulated conductors are shifted between the conductor layer B and the conductor layer C, whereby the Vdd conductor and the Vss conductor of the conductor layers A and B can be electrically connected to a lower layer or an upper layer than the conductor layer C via a conductor via extending in the Z direction or the like with a short path.

Note that, in the eighth configuration example inFIG.256, the conductor layer A configured by the reticulated conductor having the largest conductor width is not provided with a relay conductor among the conductor layers A to C but may be provided with a relay conductor.

First Modification of Eighth Configuration Example of Three-Power Supply

FIGS.257to260illustrate first to fourth modifications of the eighth configuration example of the three-power supply.

InFIGS.257to260, the arrangement of the conductor layer A (wiring layer165A), the conductor layer B (wiring layer165B), the conductor layer C (wiring layer165C), the plan view of the stacked state of the conductor layer A and the conductor layer B, the plan view of the stacked state of the conductor layer A and the conductor layer C, and the plan view of the stacked state of the conductor layer B and the conductor layer C is similar to that inFIG.248. This also similarly applies to the coordinate system.

FIG.257illustrates a first modification of the eighth configuration example of the three-power supply.

The conductor layer A in A inFIG.257includes a reticulated conductor2361. That is, the reticulated conductor2361has the conductor width WXA, the gap width GXA, and the conductor period FXA in the X direction, and the conductor width WYA, the gap width GYA, and the conductor period FYA in the Y direction. The reticulated conductor2361is a conductor having a shape in which basic patterns of the conductor period FXA and the conductor period FYA are repeatedly arranged on the same plane. The reticulated conductor2361is, for example, wiring (Vdd wiring) connected to the first power supply Vdd.

The conductor layer B in B inFIG.257includes a reticulated conductor2362connected to the second power supply Vss1and a rectangular relay conductor2363. The relay conductor2363is arranged in a gap region that is not the conductor of the reticulated conductor2362and is electrically insulated from the reticulated conductor2362, and is electrically connected to, for example, the reticulated conductor2361of the conductor layer A and the relay conductor2352of the conductor layer C.

The conductor layer C in C inFIG.257includes the reticulated conductor2333connected to the third power supply Vss2, the rectangular relay conductor2352connected to the first power supply Vdd, and the rectangular relay conductor2353connected to the second power supply Vss1, similarly to the eighth configuration example illustrated inFIG.256.

Therefore, the first modification inFIG.257is a configuration in which the connection destinations of the power supplies in the conductor layer A and the conductor layer B are interchanged with respect to the eighth configuration example inFIG.256. In the first modification inFIG.257, in the case where the conductor layer A is a conductor layer having a sheet resistance smaller than the conductor layer B or the conductor layer C, for example, the conductor layer A having a small sheet resistance is used as a Vdd conductor. In such a case, it is desirable that the conductor layer A is not provided with the relay conductor from the viewpoint of voltage drop. In this way, the conductor layer A having a small sheet resistance can be the conductor layer (Vdd conductor) connected to the power supply commonly used in the configuration of selecting and switching the second power supply Vss1and the third power supply Vss2.

Second Modification of Eighth Configuration Example of Three-Power Supply

FIG.258illustrates a second modification of the eighth configuration example of the three-power supply.

The conductor layer A in A inFIG.258includes the reticulated conductor2361connected to the first power supply Vdd, similarly to the first modification in A inFIG.257.

The conductor layer B in B inFIG.258includes the reticulated conductor2362connected to the second power supply Vss1and rectangular relay conductors2371and2372. The relay conductor2371is arranged in a gap region that is not the conductor of the reticulated conductor2362and is electrically insulated from the reticulated conductor2362, and is electrically connected to, for example, the reticulated conductor2361of the conductor layer A and the relay conductor2352of the conductor layer C. The relay conductor2372is arranged in a gap region that is not the conductor of the reticulated conductor2362and is electrically insulated from the reticulated conductor2362, and is electrically connected to, for example, the reticulated conductor2333of the conductor layer C and another conductor layer.

The conductor layer C in C inFIG.258includes the reticulated conductor2333connected to the third power supply Vss2, the rectangular relay conductor2352connected to the first power supply Vdd, and the rectangular relay conductor2353connected to the second power supply Vss1, similarly to the eighth configuration example illustrated inFIG.256.

Therefore, the second modification inFIG.258has a configuration in which the relay conductor of the conductor layer B is replaced with respect to the first modification inFIG.257.

Third Modification of Eighth Configuration Example of Three-Power Supply

FIG.259illustrates a third modification of the eighth configuration example of the three-power supply.

The conductor layer A in A inFIG.259includes the reticulated conductor2361connected to the first power supply Vdd, similarly to the second modification in A inFIG.258.

The conductor layer B in B inFIG.259includes the reticulated conductor2362connected to the second power supply Vss1, the rectangular relay conductor2371connected to the first power supply Vdd, and the rectangular relay conductor2372connected to the third power supply Vss2, similarly to the second modification in B inFIG.258.

The conductor layer C in C inFIG.259includes the reticulated conductor2333connected to the third power supply Vss2, the rectangular relay conductor2352connected to the first power supply Vdd, and the rectangular relay conductor2353connected to the second power supply Vss1, similarly to the second modification in C inFIG.258.

Therefore, the third modification inFIG.259has the same conductor configuration as the second modification illustrated inFIG.258, but the positional relationship among the conductor layers A to C is different from that of the second modification.

Specifically, comparing the X-direction positions of the conductor layer A and the conductor layer B between the second modification illustrated inFIG.258and the third modification illustrated inFIG.259, in the second modification illustrated inFIG.258, the conductor portion of the reticulated conductor2362of the conductor layer B is arranged at the position of the gap region of the reticulated conductor2361of the conductor layer A, whereas in the third modification ofFIG.259, the conductor portion of the reticulated conductor2362of the conductor layer B is arranged at the position of the conductor portion of the reticulated conductor2361of the conductor layer A. The positional relationship between the conductor layer B and the conductor layer C is the same in the second modification and the third modification.

The stacked states of the two layers of D to F inFIG.259are the same in the second modification and the third modification.

In the second modification illustrated inFIG.258and the third modification illustrated inFIG.259are common in that the conductor layer B and the conductor layer C include the reticulated conductor as the Vss1conductor or the Vss2conductor, and the two rectangular relay conductors are arranged in the gap region. In the configurations of the second modification and the third modification, the shape of the Vss1conductor and the shape of the Vss2conductor are pseudo-identical, so that the combination of the Vdd conductor and the Vss1conductor and the combination of the Vdd conductor and the Vss2conductor can reduce the difference in voltage drop and the difference in inductive noise, which may be favorable. Of course, the shape of the Vss1conductor and the shape of the Vss2conductor can be made not pseudo-identical.

Fourth Modification of Eighth Configuration Example of Three-Power Supply

FIG.260illustrates a fourth modification of the eighth configuration example of the three-power supply.

The conductor layer A in A inFIG.260includes the reticulated conductor2361connected to the first power supply Vdd, similarly to the second modification in A inFIG.258.

The conductor layer B in B inFIG.260includes the reticulated conductor2362connected to the second power supply Vss1and the rectangular relay conductor2363connected to the first power supply Vdd. Therefore, the conductor layer B is common to the conductor layer B of the first modification illustrated in B inFIG.257in including the reticulated conductor2362and the rectangular relay conductor2363but is different from the first modification in the rectangular shape of the relay conductor2363. The rectangular shape of the relay conductor2363has a large difference in the conductor width between the X direction and the Y direction in the first modification, whereas the rectangular shape is close to a square having a small difference in the conductor width between the X direction and the Y direction in the fourth modification.

The conductor layer C in C inFIG.260includes the reticulated conductor2333connected to the third power supply Vss2, the rectangular relay conductor2352connected to the first power supply Vdd, and the rectangular relay conductor2353connected to the second power supply Vss1. Therefore, the conductor layer C is common to the conductor layer C of the first modification illustrated in C inFIG.257in including the reticulated conductor2333, the relay conductor2352, and the relay conductor2353, but is different from the first modification in the conductor width (the conductor width WXB and the conductor width WYB) of the reticulated conductor2333and the gap width (the gap width GXB and the gap width GYB). The conductor width of the fourth modification in C inFIG.260is formed to be extremely narrower than the conductor width of the first modification illustrated in C ofFIG.257. Thereby, the gap region of the reticulated conductor2333is significantly changed. On the other hand, the conductor widths in the X and Y directions of the relay conductors2352and2353in the fourth modification are significantly changed to be larger than those of the relay conductors2352and2353in the first modification.

Therefore, in the fourth modification, the conductor width of the reticulated conductor2333as the Vss2conductor is extremely smaller than the conductor width of the reticulated conductor2361as the Vdd conductor and the conductor width of the reticulated conductor2362as the Vss1conductor. In this way, by securing the conductor widths of the Vdd conductor and the Vss1conductor as large as possible, the Vdd conductor and the Vss1conductor can be prioritized from the viewpoint of voltage drop. Alternatively, the conductor width of the reticulated conductor2362as the Vss1conductor may be also extremely smaller than the conductor width of the reticulated conductor2361as the Vdd conductor, and only the Vdd conductor may be prioritized from the viewpoint of voltage drop. On the contrary, at least one of the Vss1conductor or the Vss2conductor may be prioritized over the Vdd conductor from the viewpoint of voltage drop.

Ninth Configuration Example of Three-Power Supply

FIG.261illustrates a ninth configuration example of the three-power supply.

In the coordinate system inFIG.261, the horizontal direction is the X axis, the vertical direction is the Y axis, and the direction perpendicular to the XY plane is the Z axis.

A inFIG.261illustrates the conductor layer A (wiring layer165A), B inFIG.261illustrates the conductor layer B (wiring layer165B), and C inFIG.261illustrates the conductor layer C (wiring layer165C).

Furthermore, D inFIG.261is a plan view of a stacked state of the conductor layer A and the conductor layer B, E inFIG.261is a plan view of a stacked state of the conductor layer A and the conductor layer C, and F inFIG.261is a plan view of a stacked state of the conductor layer B and the conductor layer C. Note thatFIG.261may be considered as the entire region of each conductor layer or may be considered as a partial region.

The conductor layer A in A inFIG.261is configured such that a linear conductor2411long in the X direction and a linear conductor2412long in the X direction are alternately and periodically arranged in the Y direction.

The linear conductor2411is, for example, wiring (Vdd wiring) connected to the first power supply Vdd. The linear conductor2412is, for example, wiring (Vss1wiring) connected to the second power supply Vss1. The linear conductor2411and the linear conductor2412are differential conductors (differential structure) having the current directions opposite to each other.

The linear conductor2411has the conductor width WYAD in the Y direction and the linear conductor2412has the conductor width WYAS1 in the Y direction, and the conductor width WYAD of the linear conductor2411and the conductor width WYAS1 of the linear conductor2412are, for example, the same (the conductor width WYAD=the conductor width WYAS1). There is a gap with the gap width GYA between the linear conductor2411and the linear conductor2412in the Y direction.

The linear conductor2411long in the X direction is periodically arranged in the Y direction with a conductor period FYAD (=the conductor width WYAD+the conductor width WYAS1+2×the gap width GYA). The linear conductor2412long in the X direction is periodically arranged in the Y direction with a conductor period FYAS1 (=the conductor width WYAD+the conductor width WYAS1+2×the gap width GYA). The conductor period FYAD of the linear conductor2411and the conductor period FYAS1 of the linear conductor2412are, for example, the same (the conductor period FYAD=the conductor period FYAS1).

The conductor layer B in B inFIG.261is configured such that a linear conductor2421long in the Y direction and a linear conductor2422long in the Y direction are alternately and periodically arranged in the X direction.

The linear conductor2421is, for example, wiring (Vdd wiring) connected to the first power supply Vdd. The linear conductor2422is, for example, wiring (Vss1wiring) connected to the second power supply Vss1. The linear conductor2421and the linear conductor2422are differential conductors (differential structure) having the current directions opposite to each other.

The linear conductor2421has a conductor width WXBD in the X direction and the linear conductor2422has a conductor width WXBS1 in the X direction, and the conductor width WXBD of the linear conductor2421and the conductor width WXBS1 of the linear conductor2422are, for example, the same (the conductor width WXBD=the conductor width WXBS1). There is a gap with the gap width GXB between the linear conductor2421and the linear conductor2422in the X direction.

The linear conductor2421long in the Y direction is periodically arranged in the X direction with the conductor period FXBD (=the conductor width WXBD+the conductor width WXBS1+2×the gap width GXB). The linear conductor2422long in the Y direction is periodically arranged in the X direction with the conductor period FXBS1 (=the conductor width WXBD+the conductor width WXBS1+2×the gap width GXB). The conductor period FXBD of the linear conductor2421and the conductor period FXBS1 of the linear conductor2422are, for example, the same (the conductor period FXBD=the conductor period FXBS1).

The conductor layer C in C inFIG.261includes the reticulated conductor2333connected to the third power supply Vss2, the rectangular relay conductor2352connected to the first power supply Vdd, and the rectangular relay conductor2353connected to the second power supply Vss1, similarly to the eighth configuration example illustrated inFIG.256.

As illustrated in D and F inFIG.261, the stacked layer of the conductor layer A and the conductor layer B and the stacked layer of the conductor layer B and the conductor layer C do not form a perfect light-shielding structure, but the stacked layer of the conductor layer A and the conductor layer C forms a light-shielding structure, as illustrated in E inFIG.261.

As illustrated inFIG.261, the ninth configuration example has a configuration in which the conductor layer A has a differential configuration of the Vdd conductor and the Vss1conductor, the conductor layer B has a differential configuration of the Vdd conductor and the Vss1conductor, and the wiring directions are orthogonal to each other between the conductor layer A and the conductor layer B. Then, the conductor layer C includes the reticulated conductor (Vss2conductor) connected to the third power supply Vss2. Furthermore, the conductor layer C is provided with the rectangular relay conductor2352connected to the first power supply Vdd and the rectangular relay conductor2353connected to the second power supply Vss1. One or both of the relay conductor2352and the relay conductor2353may be omitted.

Modification of First to Ninth Configuration Examples of Three-Power Supply

In the linear conductor, the reticulated conductor, or the rectangular conductor of the first to ninth configuration examples provided with the above-described three-power supply, those described as being the same may be substantially the same. For example, the same conductor width, the same conductor period, and the same conductive area may be substantially the same conductor width, substantially the same conductor period, and substantially the same conductive area, respectively. Here, the substantially the same is a difference in a range that can be regarded as the same, but for example, the difference may be a difference in a range not exceeding at least twice.

Any two of the conductor layers A to C can be electrically connected via a conductor via extending in the Z direction or the like, as needed, in the region where the conductors connected to the same power supply overlap.

In the above-described example of the stacked layer of the two layers of the conductor layers A and B or the three layers of the conductor layers A to C, the order of stacking the conductor layers A and B can be arbitrarily determined. Further, in each of the above-described configuration examples, the conductor described as the conductor (Vdd conductor) connected to the first power supply Vdd may be used as the conductor connected to the second power supply Vss1or the third power supply Vss2. The conductor described as the conductor (Vss1conductor) connected to the second power supply Vss1may be used as the conductor connected to the first power supply Vdd or the third power supply Vss2. The conductor described as the conductor (Vss2conductor) connected to the third power supply Vss2may be used as the conductor connected to the first power supply Vdd or the second power supply Vss1. In each of the above-described configuration examples, the description has been made using the examples in which the gap widths GXA, GXB, GYA, and GYB are the same example regardless of their positions, but these gap widths may be different depending on the positions or may be modulated according to the positions. Furthermore, some description has been made using the examples in which the conductor widths WXAD, WXAS1, WXAS2, WXBD, WXBS1, WXBS2, WYAD, WYAS1, WYAS2, WYBD, WYBS1, and WYBS2 are the same regardless of their positions, but these conductor widths may be different depending on the positions or may be modulated according to the positions. Furthermore, it is considered favorable to satisfy “the conductor width WYAD=the conductor width WYAS1=the conductor width WYAS2”, but it may be configured not to satisfy the above. Furthermore, some description has been made using the examples in which the conductor periods FXAD, FXAS1, FXAS2, FXBD, FXBS1, FXBS2, FYAD, FYAS1, FYBD, FYBS1, FYBS2, FXA, FXB, FXC, FYA, FYB, and FYC are the same regardless of their positions, but these conductor periods may be different depending on the positions or may be modulated according to the positions. Furthermore, it is considered favorable to satisfy “the conductor period FXAD=the conductor period FXAS1=the conductor period FXAS2”, “the conductor period FXBD=the conductor period FXBS1=the conductor period FXBS2”, “the conductor period FYAD=the conductor period FYAS1”, “the conductor period FYBD=the conductor period FYBS1=the conductor period FYBS2”, “the conductor period FXA=the conductor period FXB=the conductor period FXC”, or “the conductor period FYA=the conductor period FYB=the conductor period FYC”, but it may be configured not to satisfy the above. Furthermore, at least a part or all of the above-described reticulated conductors may be a planar conductor or a linear conductor. Although the configuration examples and the modifications when the solid-state imaging device adopts the three-power supply have been described, configuration examples and modifications in which the solid-state imaging device can adopt a four-power supply or more are also possible. For example, in the case of the four-power supply, at least one of the first to third power supplies may be replaced with a fourth power supply, and at least one of the first path or the second path may be replaced with a third path connected to the fourth power supply. Furthermore, the fourth power supply may be added to the first to third power supplies, or the third path connected to the fourth power supply may be added to the first path and the second path. The same applies to the case where the solid-state imaging device adopts a five-power supply or more.

16. Other Configuration Examples of Case Having Three Conductor Layers

In the above <12. Configuration Example of Case Having Three Conductor Layers>, the configuration examples of the three-layer conductor layer (the first to fourteenth configuration examples of the three-layer conductor layer) including the conductor layers A to C (the wiring layers165A to165C) have been described with reference toFIGS.122to163. Other configuration examples of the three-layer conductor layer will be further described.

Specifically, an example of a conductor in which the conductor layer C has a diagonal or stepped shape and an example of a conductor having a mirror-symmetrical shape will be described. Hereinafter, the same reference numeral is given to a portion corresponding to the above-described configuration example and description thereof is omitted as appropriate.

Note that, inFIGS.262to283to be described below, the pattern (design) used for the conductor of the wiring (Vss wiring) connected to the GND or the negative power supply (Vss) and the pattern (design) used for the conductor of the wiring (Vdd wiring) connected to the positive power supply (Vdd) are changed from the patterns (design) used in the drawings so far. In the drawings so far, hatching (diagonal line pattern) has been used for the pattern used for the conductor of the Vss wiring and the pattern used for the conductor of the Vdd wiring. This is because if hatching is used for the conductor which has a diagonal or stepped shape, the boundary between the pattern portion (conductor portion) and the gap portion cannot be distinguished.

To reconfirm the above-described configuration of the conductor layer, the wiring layer170(conductor group) and the active element layer171are arranged in the Z-axis direction of the conductor layers A to C as described with reference to FIG.120. An active element such as the MOS transistor164is arranged in the active element layer171. The wiring layer170(conductor group) includes at least a part of the control line133that controls the transistor of the pixel131or at least a part of the signal line132that transmits the pixel signal. For example, the wiring layer170includes the plurality of signal lines132with a predetermined periodic width in the X direction and the plurality of control lines133with a predetermined periodic width in the Y direction. The signal line132is wiring longer in the Y direction than in the X direction, and the control line133is wiring longer in the X direction than in the Y direction. The wiring layer170may be configured by two or more conductor layers, and the plurality of signal lines132and the plurality of control lines133as the wiring layer170may be arranged in the pixel array121. The plurality of signal lines132and control lines133arranged in the pixel array121are selectively switched by the vertical scanning unit123switching a target pixel for exposure and readout of the pixel signal.

Fifteenth Configuration Example of Three-Layer Conductor Layer

FIG.262illustrates a fifteenth configuration example of the three-layer conductor layer.

A inFIG.262illustrates the conductor layer C (wiring layer165C), B inFIG.262illustrates the conductor layer A (wiring layer165A), and C inFIG.262illustrates the conductor layer B (wiring layer165B).

Furthermore, D inFIG.262is a plan view of a stacked state of the conductor layer A and the conductor layer C, E inFIG.262is a plan view of a stacked state of the conductor layer B and the conductor layer C, and F inFIG.262is a plan view of a stacked state of the conductor layer A and the conductor layer B.

The conductor layer A in B inFIG.262includes the same reticulated conductor1201and relay conductor1241as inFIG.128. Note that the reticulated conductor1201is, for example, wiring (Vss wiring) connected to the GND and the negative power supply (Vss), and the relay conductor1241is, for example, wiring (Vdd wiring) connected to the positive power supply (Vdd).

The conductor layer B in C inFIG.262includes the same reticulated conductor1202and relay conductor1242as inFIG.128. The reticulated conductor1202is, for example, wiring (Vdd wiring) connected to the positive power supply, and the relay conductor1242is, for example, wiring (Vss wiring) connected to the GND and the negative power supply.

The conductor layer C in A inFIG.262is a conductor layer having a low sheet resistance through which the current easily flows, and is configured by alternately and periodically arranging a diagonal conductor2501A long in a diagonal direction and a diagonal conductor2501B long in a diagonal direction in a direction orthogonal to an extending direction of the diagonal conductors2501A and2501B (hereinafter referred to as a diagonally extending direction). The diagonally extending direction is the direction of an angle θ (0<θ<90) with respect to the Y axis.

The diagonal conductor2501A is, for example, wiring (Vss wiring) connected to the GND and the negative power supply (Vss). The diagonal conductor2501B is, for example, wiring (Vdd wiring) connected to the positive power supply (Vdd). The diagonal conductor2501A and the diagonal conductor2501B are differential conductors (differential structure) having the current directions opposite to each other. The diagonal conductor2501A is directly or indirectly connected to, for example, a pad (not illustrated) on an outer peripheral portion of the semiconductor substrate, and is electrically connected to the reticulated conductor1201of the conductor layer A. The reticulated conductor1201of the conductor layer A and the diagonal conductor2501A of the conductor layer C may be electrically connected via, for example, a conductor via (VIA) extending in the Z direction. The diagonal conductor2501B is directly or indirectly connected to, for example, a pad (not illustrated) on an outer peripheral portion of the semiconductor substrate, and is electrically connected to the reticulated conductor1202of the conductor layer B. The reticulated conductor1202of the conductor layer B and the diagonal conductor2501B of the conductor layer C may be electrically connected via, for example, a conductor via (VIA) extending in the Z direction.

The diagonal conductor2501A has a conductor width WSCA in the direction orthogonal to the diagonally extending direction, and the diagonal conductor2501B has a conductor width WSCB in the direction orthogonal to the diagonally extending direction. In the fifteenth configuration example inFIG.262, the conductor width WSCA of the diagonal conductor2501A and the conductor width WSCB of the diagonal conductor2501B are the same (the conductor width WSCA=the conductor width WSCB). The conductor width WSCA and the conductor width WSCB may not be the same or may be substantially the same (the conductor width WSCA≈the conductor width WSCB), or may be different conductor widths. There is a gap with a gap width GSC between the diagonal conductor2501A and the diagonal conductor2501B.

The diagonal conductor2501A and the diagonal conductor2501B are periodically arranged in the direction orthogonal to the diagonally extending direction with a conductor period FSC (=the conductor width WSCA+the conductor width WSCB+2×the gap width GSC). A conductor period FSCA of the diagonal conductor2501A and a conductor period FSCB of the diagonal conductor2501B are the same (FSC=FSCA=FSCB) or substantially the same (FSCA z FSCB).

Note that the conductor width WSCA, the conductor width WSCB, and the gap width GSC can be designed to arbitrary values.

When the conductor layer C in which the diagonal conductor2501A and the diagonal conductor2501B are periodically arranged in the diagonally extending direction with the conductor period FSC is viewed in a predetermined plane range (plane region), the sum of the conductor widths WSCA of a plurality of diagonal conductors2501A and the sum of the conductor widths WSCB of a plurality of diagonal conductors2501B in the predetermined plane range are the same or substantially the same because the conductor width WSCA of the diagonal conductor2501A and the conductor width WSCB of the diagonal conductor2501B are the same or substantially the same. As a result, the current distribution of the diagonal conductor2501A and the current distribution of the diagonal conductor2501B become the same or substantially the same, so that generation of inductive noise can be suppressed.

Furthermore, in a case where the conductor layer C is arranged near the wiring layer170, as illustrated in C inFIG.120, for example, the capacitive noise due to capacitive coupling between the diagonal conductor2501A and the diagonal conductor2501B of the conductor layer C, and the signal line132and the control line133of the wiring layer170can occur. However, since the diagonal conductor2501A and the diagonal conductor2501B have the same wiring pattern repeated in the X and Y directions, the capacitive noise generated from the conductors can be completely canceled in both the X and Y directions. The capacitive noise can be significantly improved as the conductor layer C is closer to the wiring layer170.

As illustrated in F inFIG.262, the stacked layer of the conductor layers A and B has a light-shielding structure, and the hot carrier light emission from the active element group167can be shielded. In addition, as illustrated in D and E inFIG.262, the light-shielding property is maintained in a fixed range in the stacked layer of the conductor layers A and C and the stacked layer of the conductor layers B and C. Thereby, since the light-shielding restrictions of the conductor layers A and B can be significantly alleviated, the conductive area of the conductor layers A and B can be used to the maximum, the wiring resistance can be lowered, and the voltage drop can be further improved. Furthermore, the degree of freedom in layout of the conductor layers A and B can be improved.

Moreover, in the case where the reticulated conductor1201of the conductor layer A and the diagonal conductor2501A of the conductor layer C are electrically connected, and the reticulated conductor1202of the conductor layer B and the diagonal conductor2501B of the conductor layer C are electrically connected, the current amount of the conductor layers A and B can be made small. Therefore, the inductive noise and the voltage drop from the conductor layer A or B can be further improved.

Sixteenth Configuration Example of Three-Layer Conductor Layer

FIG.263illustrates a sixteenth configuration example of the three-layer conductor layer.

A inFIG.263illustrates the conductor layer C (wiring layer165C), B inFIG.263illustrates the conductor layer A (wiring layer165A), and C inFIG.263illustrates the conductor layer B (wiring layer165B).

Furthermore, D inFIG.263is a plan view of a stacked state of the conductor layer A and the conductor layer C, E inFIG.263is a plan view of a stacked state of the conductor layer B and the conductor layer C, and F inFIG.263is a plan view of a stacked state of the conductor layer A and the conductor layer B.

In the sixteenth configuration example, only the configuration of the conductor layer C in A inFIG.263is different from that inFIG.262.

In the conductor layer C in A inFIG.262, the diagonal conductors2501A and2501B having a linear shape in the diagonally extending direction have been alternately and periodically arranged with the conductor period FSC.

Meanwhile, in the conductor layer C in A inFIG.263, stepped conductors2511A and2511B having a stepped shape in the diagonally extending direction are alternately and periodically arranged with the conductor period FSC.

The sixteenth configuration example inFIG.263is similar to the fifteenth configuration example inFIG.262except for the above-described points.

When the conductor layer C in which the stepped conductor2511A and the stepped conductor2511B are periodically arranged in the diagonally extending direction with the conductor period FSC is viewed in a predetermined plane range (plane region), the sum of the conductor widths WSCA of a plurality of stepped conductors2511A and the sum of the conductor widths WSCB of a plurality of stepped conductors2511B in the predetermined plane range are the same or substantially the same because the conductor width WSCA of the stepped conductor2511A and the conductor width WSCB of the stepped conductor2511B are the same or substantially the same. As a result, the current distribution of the stepped conductor2511A and the current distribution of the stepped conductor2511B become the same or substantially the same, so that generation of inductive noise can be suppressed.

Furthermore, in a case where the conductor layer C is arranged near the wiring layer170, as illustrated in C inFIG.120, for example, the capacitive noise due to capacitive coupling between the stepped conductor2511A and the stepped conductor2511B of the conductor layer C, and the signal line132and the control line133of the wiring layer170can occur. However, since the stepped conductor2511A and the stepped conductor2511B have the same wiring pattern repeated in the X and Y directions, the capacitive noise generated from the conductors can be completely canceled in both the X and Y directions. The capacitive noise can be significantly improved as the conductor layer C is closer to the wiring layer170.

As illustrated in F ofFIG.263, the stacked layer of the conductor layers A and B has a light-shielding structure, and the hot carrier light emission from the active element group167can be shielded. In addition, as illustrated in D and E inFIG.263, the light-shielding property is maintained in a fixed range in the stacked layer of the conductor layers A and C and the stacked layer of the conductor layers B and C. Thereby, since the light-shielding restrictions of the conductor layers A and B can be significantly alleviated, the conductive area of the conductor layers A and B can be used to the maximum, the wiring resistance can be lowered, and the voltage drop can be further improved. Furthermore, the degree of freedom in layout of the conductor layers A and B can be improved.

Moreover, in the case where the reticulated conductor1201of the conductor layer A and the stepped conductor2511A of the conductor layer C are electrically connected, and the reticulated conductor1202of the conductor layer B and the stepped conductor25111B of the conductor layer C are electrically connected, the current amount of the conductor layers A and B can be made small. Therefore, the inductive noise and the voltage drop from the conductor layer A or B can be further improved.

Note that, in the fifteenth configuration example inFIG.262and the sixteenth configuration example inFIG.263, the configurations of the conductor layers A and B inFIG.128have been adopted as the configurations of the conductor layers A and B, but the configurations of the conductor layers A and B are not limited to the configurations of the conductor layers A and B inFIG.128. Any of the configurations of the conductor layers A and B of the first to fourteenth configuration examples of the three-layer conductor layer can be applied to the conductor layers A and B.

Moreover, the wiring pattern of the diagonal conductor or the stepped conductor of the conductor layer C can be applied to the case where the conductor layers A and B are configured by the wiring connected to the three-power supply such as the first power supply Vdd, the second power supply Vss1, and the third power supply Vss2, as described in <15. Configuration Examples of Three-power Supply> above. In this case, the wiring pattern of the diagonal conductor or the stepped conductor of the conductor layer C can be configured such that diagonal or stepped Vdd wiring, Vss1wiring, and Vss2wiring are periodically arranged in the direction orthogonal to the diagonally extending direction.

Other Modifications in Fifteenth Configuration Example of Three-layer Conductor Layer

Hereinafter, other modifications of the fifteenth configuration example of the three-layer conductor layer illustrated inFIG.262will be described with reference toFIGS.264to273.

Note that, in the modifications of the fifteenth configuration example, only the configuration of the conductor layer C is illustrated inFIGS.264to273because only the configuration of the conductor layer C is changed.

A inFIG.264illustrates the conductor layer C of a first modification of the fifteenth configuration example of the three-layer conductor layer.

The conductor layer C in A inFIG.264is a conductor layer having a low sheet resistance through which a current easily flows, and a diagonal conductor2521A and a diagonal conductor2521B long in the diagonal direction are alternately and periodically arranged. Note that the diagonal conductor2521A is, for example, wiring (Vss wiring) connected to the GND and the negative power supply (Vss), and the diagonal conductor2521B is, for example, wiring (Vdd wiring) connected to the positive power supply (Vdd).

Furthermore, assuming that the conductor layer C is divided into four first region25311to fourth region25314with a center of the entire region in the XY directions as an origin, the diagonal conductors2521A and2521B of the regions2531are mirror-symmetrically arranged in an X-shaped manner with respect to the X and Y directions. Note that the conductor periods, conductor widths, gap widths, and periodic widths of the diagonal conductors2521A and2521B in each region2531are similar to those of the diagonal conductors2501A and2501B in A inFIG.262for the sake of simplicity.

Specifically, the diagonal conductors2521A and the diagonal conductor2521B in the first region25311are periodically formed in the direction of the angle θ (0<θ<90) with respect to the Y axis as the diagonally extending direction, similarly to the diagonal conductors2501A and2501B in A inFIG.262. Then, the diagonal conductor2521A and the diagonal conductor2521B of the second region25312are formed such that the first region25311and the second region25312become mirror-symmetrical with respect to the Y direction. The third region25313is formed such that the second region25312and the third region25313become mirror-symmetrical with respect to the X direction. The fourth region25314is formed such that the first region25311and the fourth region25314become mirror-symmetrical with respect to the X direction.

Therefore, the diagonally extending direction of the diagonal conductor2521A and the diagonal conductor2521B in the first region25311and the third region25313is the direction of the angle θ with respect to the Y axis, and the diagonally extending direction of the diagonal conductor2521A and the diagonal conductor2521B in the second region25312and the fourth region25314is a direction of an angle −θ with respect to the Y axis. Therefore, absolute values of the angle of the diagonally extending direction of the diagonal conductor2521in the first region25311and the third region25313and of the angle of the diagonally extending direction of the diagonal conductor2521in the second region25312and the fourth region25314are the same. The diagonal conductor2521A and the diagonal conductor2521B in each region2531are periodically arranged in the direction orthogonal to the diagonally extending direction with the conductor period FSC.

B inFIG.264illustrates the conductor layer C of a second modification of the fifteenth configuration example of the three-layer conductor layer.

The conductor layer C in B inFIG.264is configured such that the diagonal conductor2521A and the diagonal conductor2521B are alternately and periodically arranged, and the diagonal conductor2521A and the diagonal conductor2521B in the four first region25311to fourth region25314are mirror-symmetrically arranged in an X-shaped manner with respect to the X and Y directions.

The difference between the conductor layer C of the first modification in A inFIG.264and the conductor layer C of the second modification in B inFIG.264is the arrangement of the diagonal conductor2521A and the diagonal conductor2521B. For example, in the first modification in A inFIG.264, the center of the entire region of the conductor layer C in the XY directions is a gap, whereas in the second modification in B inFIG.264, the center of the entire region of the conductor layer C in the XY directions is an intersection of the diagonal conductor2521B. Other configurations are common to the first modification and the second modification.

A inFIG.265illustrates the conductor layer C of a third modification of the fifteenth configuration example of the three-layer conductor layer.

The conductor layer C in A inFIG.265is configured such that the diagonal conductor2521A and the diagonal conductor2521B are alternately and periodically arranged, and the diagonal conductor2521A and the diagonal conductor2521B in the four first region25311to fourth region25314are mirror-symmetrically arranged in a diamond-shaped manner with respect to the X and Y directions.

The difference between the conductor layer C of the first modification in A inFIG.264and the conductor layer C of the third modification in A inFIG.265is the direction (angle) of the diagonally extending direction of the diagonal conductor2521A and the diagonal conductor2521B. The diagonally extending direction of the diagonal conductor2521A and the diagonal conductor2521B in the first region25311and the third region25313is the direction of the angle −θ with respect to the Y axis, and the diagonally extending direction of the diagonal conductor2521A and the diagonal conductor2521B in the second region25312and the fourth region25314is the direction of the angle θ with respect to the Y axis. Other configurations are common to the first modification and the second modification.

B inFIG.265illustrates the conductor layer C of a fourth modification of the fifteenth configuration example of the three-layer conductor layer.

The conductor layer C in B inFIG.265is configured such that the diagonal conductor2521A and the diagonal conductor2521B are alternately and periodically arranged, and the diagonal conductor2521A and the diagonal conductor2521B in the four first region25311to fourth region25314are mirror-symmetrically arranged in a diamond-shaped manner with respect to the X and Y directions.

The difference between the conductor layer C of the third modification in A inFIG.265and the conductor layer C of the fourth modification in B inFIG.265is the arrangement of the diagonal conductor2521A and the diagonal conductor2521B. For example, in the third modification in A inFIG.265, the diagonal conductor2521A and the diagonal conductor2521B are periodically arranged having the diagonal conductor2521A as the center of the entire region of the conductor layer C in the XY directions, whereas in the fourth modification in B inFIG.265, the diagonal conductor2521A and the diagonal conductor2521B are periodically arranged having the diagonal conductor2521B as the center of the entire region of the conductor layer C in the XY directions. Other configurations are common to the third modification and the fourth modification.

In the first to fourth modifications inFIGS.264and265, the diagonal conductor2521A (first conductor) periodically arranged in the first region25311with the conductor period FSCA (first periodic width), the diagonal conductor2521B (second conductor) periodically arranged in the first region25311with the conductor period FSCB (second periodic width), the diagonal conductor2521A (third conductor) periodically arranged in the second region25312different from the first region25311with the conductor period FSCA (third periodic width), and the diagonal conductor2521B (fourth conductor) periodically arranged in the second region25312with the conductor period FSCB (fourth periodic width) are included.

The first region25311and the second region25312have a mirror-symmetrical or substantially mirror-symmetrical conductor structure in the Y direction (first direction), and the first power supply (Vss) connected to the diagonal conductor2521A (first conductor) in the first region25311and the diagonal conductor2521A (third conductor) in the second region25312and the second power supply (Vdd) connected to the diagonal conductor2521B (second conductor) in the first region25311and the diagonal conductor2521B (fourth conductor) in the second region25312have different voltage values.

In the first to fourth modifications, the conductor period FSCA (first periodic width) of the diagonal conductor2521A (first conductor) in the first region25311and the conductor period FSCB (second periodic width) of the diagonal conductor2521B (second conductor width) are the same (FSC=FSCA=FSCB), but do not have to be the same as long as the conductor periods have a rational number relationship. Similarly, the conductor period FSCA (third periodic width) of the diagonal conductor2521A (third conductor) in the second region25312and the conductor period FSCB (fourth periodic width) of the diagonal conductor2521B (fourth conductor) in the second region25312are the same (FSC=FSCA=FSCB), but do not have to be the same as long as the conductor periods have a rational number relationship. The rational number relationship is defined as “A and B are in the rational number relationship” when the relationship of “a real number A×an integer a=a real number B×an integer b” holds.

The conductor period FSCA (first periodic width) of the diagonal conductor2521A (first conductor) in the first region25311and the conductor period FSCB (fourth periodic width) of the diagonal conductor2521B (fourth conductor) in the second region25312are the same or substantially the same.

In this case, the sum of the conductive areas within a predetermined range of the diagonal conductor2521A (first conductor) in the first region25311and the diagonal conductor2521A (third conductor) in the second region25312, and the sum of the conductive areas within the predetermined range of the diagonal conductor2521B (second conductor) in the first region25311and the diagonal conductor2521B (fourth conductor) in the second region25312are the same.

Furthermore, the sum of the conductor widths within a predetermined range of the diagonal conductor2521A (first conductor) in the first region25311and the diagonal conductor2521A (third conductor) in the second region25312, and the sum of the conductor widths within the predetermined range of the diagonal conductor2521B (second conductor) in the first region25311and the diagonal conductor2521B (fourth conductor) of the second region25312are the same.

Furthermore, in the first to fourth modifications of the conductor layer C inFIGS.264and265, the diagonal conductor2521A (fifth conductor) periodically arranged in the third region25313with the conductor period FSC (fifth periodic width), the diagonal conductor2521B (sixth conductor) periodically arranged in the third region25313with the conductor period FSC (sixth periodic width), the diagonal conductor2521A (seventh conductor) periodically arranged in the fourth region25314different from the third region25313with the conductor period FSC (seventh periodic width), and the diagonal conductor2521B (eighth conductor) periodically arranged in the fourth region25314with the conductor period FSC (eighth periodic width) are included.

The third region25313and the fourth region25314have a mirror-symmetrical or substantially mirror-symmetrical conductor structure in the Y direction (first direction), and the first power supply (Vss) connected to the diagonal conductor2521A (fifth conductor) in the third region25313and the diagonal conductor2521A (seventh conductor) in the fourth region25314and the second power supply (Vdd) connected to the diagonal conductor2521B (sixth conductor) in the third region25313and the diagonal conductor2521B (eighth conductor) in the fourth region25314have different voltage values.

In the first to fourth modifications, the conductor period FSCA (fifth periodic width) of the diagonal conductor2521A (fifth conductor) in the third region25313and the conductor period FSCB (sixth period width) of the diagonal conductor2521B (sixth conductor) are the same (FSC=FSCA=FSCB), but do not have to be the same as long as the conductor periods have a rational number relationship. Similarly, the conductor period FSCA (seventh periodic width) of the diagonal conductor2521A (seventh conductor) in the fourth region25314and the conductor period FSCB (eighth period width) of the diagonal conductor2521B (eighth conductor) in the fourth region25314are the same (FSC=FSCA=FSCB), but do not have to be the same as long as the conductor periods have a rational number relationship.

The conductor period FSCA (fifth periodic width) of the diagonal conductor2521A (fifth conductor) in the third region25313and the conductor period FSCB (eighth conductor period) of the diagonal conductor2521B (eighth conductor) in the fourth region25314are the same or substantially the same.

In this case, the sum of the conductive areas within a predetermined range of the diagonal conductor2521A (fifth conductor) in the third region25313and the diagonal conductor2521A (seventh conductor) in the fourth region25314, and the sum of the conductive areas within the predetermined range of the diagonal conductor2521B (sixth conductor) in the third region25313and the diagonal conductor2521B (eighth conductor) in the fourth region25314are the same.

Furthermore, the sum of the conductor widths within a predetermined range of the diagonal conductor2521A (fifth conductor) in the third region25313and the diagonal conductor2521A (seventh conductor) in the fourth region25314, and the sum of the conductor widths within a predetermined range of the diagonal conductor2521B (sixth conductor) in the third region25313and the diagonal conductor2521B (eighth conductor) in the fourth region25314are the same.

Then, the first region25311and the second region25312have a mirror-symmetrical or substantially mirror-symmetrical conductor structure even in the X direction (second direction) orthogonal to the Y direction (first direction). Therefore, the first region25311and the fourth region25314have a mirror-symmetrical or substantially mirror-symmetrical conductor structure in the X direction (second direction), and the second region25312and the third region25313have a mirror-symmetrical or substantially mirror-symmetrical conductor structure in the X direction (second direction).

As described above, in the first to fourth modifications inFIGS.264and265, the diagonal conductors2521A and2521B have a mirror-symmetrical conductor structure in the X and Y directions in units of regions2531. Thereby, the capacitive noise generated from the conductors can be completely canceled in both the X and Y directions.

A inFIG.266illustrates the conductor layer C of a fifth modification of the fifteenth configuration example of the three-layer conductor layer.

The conductor layer C in A inFIG.266is a conductor layer having a low sheet resistance through which a current easily flows, and a linear conductor2631A and a linear conductor2631B long in the Y direction are alternately and periodically arranged in the X direction. The linear conductor2631A is, for example, wiring (Vss wiring) connected to the GND and the negative power supply, and the linear conductor2631B is, for example, wiring (Vdd wiring) connected to the positive power supply.

Furthermore, assuming that the conductor layer C is divided into a first region26321and a second region26322with reference to a center line in the X direction of the entire region, the linear conductors2631A and2531B in the regions2632are mirror-symmetrically arranged with respect to the X direction.

B inFIG.266illustrates the conductor layer C of a sixth modification of the fifteenth configuration example of the three-layer conductor layer.

The conductor layer C in B inFIG.266is configured such that the linear conductor2631A and the linear conductor2631B are alternately and periodically arranged in the X direction, and the linear conductor2631A and the linear conductor2631B in the first region26321and the second region26322are mirror-symmetrically arranged with respect to the X direction.

The difference between the conductor layer C of the fifth modification in A inFIG.266and the conductor layer C of the sixth modification in B inFIG.266is the arrangement of the linear conductor2631A and the linear conductor2631B. For example, in the fifth modification in A inFIG.266, the linear conductor2631A is arranged on the center line in the X direction of the entire region of the conductor layer C, whereas in the sixth modification in B inFIG.266, there is a gap on the center line in the X direction of the entire region of the conductor layer C. Other configurations are common to the fifth modification and the sixth modification.

The fifth modification and the sixth modification can completely cancel the capacitive noise generated from the conductors in the X direction.

A inFIG.267illustrates the conductor layer C of a seventh modification of the fifteenth configuration example of the three-layer conductor layer.

The conductor layer C in A inFIG.267is a conductor layer having a low sheet resistance through which a current easily flows, and a linear conductor2633A and a linear conductor2633B long in the X direction are alternately and periodically arranged in the Y direction. The linear conductor2633A is, for example, wiring (Vss wiring) connected to the GND and the negative power supply, and the linear conductor2633B is, for example, wiring (Vdd wiring) connected to the positive power supply.

Furthermore, assuming that the conductor layer C is divided into a first region26341and a second region26342with reference to a center line in the Y direction of the entire region, the linear conductors2633A and2533B in the regions2634are mirror-symmetrically arranged with respect to the Y direction.

B inFIG.267illustrates the conductor layer C of an eighth modification of the fifteenth configuration example of the three-layer conductor layer.

The conductor layer C in B inFIG.267is configured such that the linear conductor2633A and the linear conductor2633B are alternately and periodically arranged in the Y direction, and the linear conductor2633A and the linear conductor2633B in the first region26341and the second region26342are mirror-symmetrically arranged with respect to the Y direction.

The difference between the conductor layer C of the seventh modification in A inFIG.267and the conductor layer C of the eighth modification in B inFIG.267is the arrangement of the linear conductor2633A and the linear conductor2633B. For example, in the seventh modification in A inFIG.267, the linear conductor2633A is arranged on the center line in the Y direction of the entire region of the conductor layer C, whereas in the eighth modification in B inFIG.267, there is a gap on the center line in the Y direction of the entire region of the conductor layer C. Other configurations are common to the fifth modification and the sixth modification.

The seventh modification and the eighth modification can completely cancel the capacitive noise generated from the conductors in the Y direction.

A inFIG.268illustrates the conductor layer C of a ninth modification of the fifteenth configuration example of the three-layer conductor layer.

The conductor layer C in A inFIG.268is a conductor layer having a low sheet resistance through which an electric current easily flows, and is configured by alternately and periodically arranging the conductors2651A and2651B having a shape of a combination of a linear conductor extending in the Y direction and a diagonal conductor in the diagonal direction. Furthermore, the conductor layer C has a configuration in which the conductors2651A and2651B of each region2531are mirror-symmetrically arranged with respect to the X direction and the Y direction. The conductor2651A is, for example, wiring (Vss wiring) connected to the GND and the negative power supply, and the conductor2651B is, for example, wiring (Vdd wiring) connected to the positive power supply.

The ninth modification can completely cancel the capacitive noise generated from the conductors in the X direction and can partially cancel the capacitive noise in the Y direction.

B inFIG.268illustrates the conductor layer C of a tenth modification of the fifteenth configuration example of the three-layer conductor layer.

The conductor layer C in B inFIG.268is a conductor layer having a low sheet resistance through which an electric current easily flows, and is configured by alternately and periodically arranging the conductors2652A and2652B having a shape of a combination of a linear conductor extending in the Y direction and a diagonal conductor in the diagonal direction. Furthermore, the conductor layer C has a configuration in which the conductors2652A and2652B of each region2531are mirror-symmetrically arranged with respect to the X direction and the Y direction. The conductor2652A is, for example, wiring (Vss wiring) connected to the GND and the negative power supply, and the conductor2652B is, for example, wiring (Vdd wiring) connected to the positive power supply.

The tenth modification can completely cancel the capacitive noise generated from the conductors in the X direction and can partially cancel the capacitive noise in the Y direction.

A inFIG.269illustrates the conductor layer C of an eleventh modification of the fifteenth configuration example of the three-layer conductor layer.

The conductor layer C in A inFIG.269is a conductor layer having a low sheet resistance through which an electric current easily flows, and is configured by alternately and periodically arranging the conductors2653A and2653B having a shape of a combination of a linear conductor extending in the X direction and a diagonal conductor in the diagonal direction. Furthermore, the conductor layer C has a configuration in which the conductors2653A and2653B of each region2531are mirror-symmetrically arranged with respect to the X direction and the Y direction. The conductor2653A is, for example, wiring (Vss wiring) connected to the GND and the negative power supply, and the conductor2653B is, for example, wiring (Vdd wiring) connected to the positive power supply.

The eleventh modification can completely cancel the capacitive noise generated from the conductors in the Y direction and can partially cancel the capacitive noise in the X direction.

B inFIG.269illustrates the conductor layer C of a twelfth modification of the fifteenth configuration example of the three-layer conductor layer.

The conductor layer C in B inFIG.269is a conductor layer having a low sheet resistance through which an electric current easily flows, and is configured by alternately and periodically arranging the conductors2654A and2654B having a shape of a combination of a linear conductor extending in the X direction and a diagonal conductor in the diagonal direction. Furthermore, the conductor layer C has a configuration in which the conductors2654A and2654B of each region2531are mirror-symmetrically arranged with respect to the X direction and the Y direction. The conductor2654A is, for example, wiring (Vss wiring) connected to the GND and the negative power supply, and the conductor2654B is, for example, wiring (Vdd wiring) connected to the positive power supply.

The twelfth modification can completely cancel the capacitive noise generated from the conductors in the Y direction and can partially cancel the capacitive noise in the X direction.

A inFIG.270illustrates the conductor layer C of a thirteenth modification of the fifteenth configuration example of the three-layer conductor layer.

The conductor layer C in A inFIG.270is a conductor layer having a low sheet resistance through which an electric current easily flows, and is configured by alternately and periodically arranging the conductors2655A and2655B having a shape of a combination of a linear conductor extending in the X or Y direction and a diagonal conductor in the diagonal direction. Furthermore, the conductor layer C has a configuration in which the conductors2655A and2655B of each region2531are mirror-symmetrically arranged with respect to the X direction and the Y direction. Conductors2656A and2656B are not arranged in a central region including a mirror-symmetrical reference point. The conductor2655A is, for example, wiring (Vss wiring) connected to the GND and the negative power supply, and the conductor2655B is, for example, wiring (Vdd wiring) connected to the positive power supply.

The thirteenth modification can partially cancel the capacitive noise generated from the conductors in the X direction and can partially cancel the capacitive noise in the Y direction. Note that there are also positions where the capacitive noise generated from the conductor can be completely canceled in the X direction or in the Y direction.

B inFIG.270illustrates the conductor layer C of a fourteenth modification of the fifteenth configuration example of the three-layer conductor layer.

The conductor layer C in B inFIG.270is a conductor layer having a low sheet resistance through which an electric current easily flows, and is configured by alternately and periodically arranging the conductors2656A and2656B having a shape of a combination of a linear conductor extending in the X or Y direction and a diagonal conductor in the diagonal direction. Furthermore, the conductor layer C has a configuration in which the conductors2656A and2656B of each region2531are mirror-symmetrically arranged with respect to the X direction and the Y direction. Conductors2656A and2656B are not arranged in a central region including a mirror-symmetrical reference point. The conductor2656A is, for example, wiring (Vss wiring) connected to the GND and the negative power supply, and the conductor2656B is, for example, wiring (Vdd wiring) connected to the positive power supply.

The fourteenth modification can partially cancel the capacitive noise generated from the conductors in the X direction and can partially cancel the capacitive noise in the Y direction. Note that there are also positions where the capacitive noise generated from the conductor can be completely canceled in the X direction or in the Y direction.

InFIGS.264to270, regarding the conductor layer C divided into the four first region25311to fourth region25314and mirror-symmetrically formed, two regions2531may be omitted, and the remaining two regions2531may be mirror-symmetrical in the X or Y direction.

In the first to fourteenth modifications illustrated inFIGS.264to270, examples of the diagonal conductors have been described, but at least a part or all of the diagonal conductors can be replaced with stepped conductors.

In the fifteenth configuration example inFIGS.262to270, an example in which the diagonal conductor or the stepped conductor is adopted for the conductor layer C in the three-layer stacked structure of the conductor layers A to C has been described. However, the above-described diagonal conductor or stepped conductor may be adopted for the conductor layer A or the conductor layer B. Furthermore, the above-described diagonal conductor or stepped conductor may be adopted for a plurality of layers of the conductor layers A to C. Moreover, the above-described diagonal conductor or stepped conductor may be adopted for a single conductor layer (wiring layer) that is not stacked. In addition, in the fifteenth configuration example inFIGS.262to270, the conductor layer C has been described as a conductor layer having a low sheet resistance in which a current easily flows, but the conductor layer C may be a conductor having a high sheet resistance in which a current does not easily flow.

The effect of the mirror-symmetrical arrangement will be described with reference toFIGS.271and272.

A conductor layer2711in A inFIG.271is configured by alternately and periodically arranging a linear conductor2712A as the Vss wiring and a linear conductor2712B as the Vdd wiring in the X direction.

The conductor layer2711in B inFIG.271is configured by alternately and periodically arranging a linear conductor2713A as the Vss wiring and a linear conductor2713B as the Vdd wiring in the diagonal direction.

Consider a case in which MOS transistors are arranged at positions shifted in the Z direction in a central region2714of the conductor layer2711including the linear conductor2712or the diagonal conductor2713, and the linear conductor2712or the diagonal conductor2713is electrically connected to the MOS transistors.

A pad region2715in which a pad (electrode) that supplies a predetermined power supply voltage to the linear conductor2712or the diagonal conductor2713is arranged is a peripheral portion along the extending direction of the linear conductor2712or the diagonal conductor2713overlapping with the central region2714, as illustrated in A or B inFIG.271.

In a case of adopting the mirror-symmetrical arrangement of the conductor layer C of the first modification of the fifteenth configuration example illustrated in A inFIG.264for the above-described configuration, for example, a pad region2811in which a pad for supplying a predetermined power supply voltage to the diagonal conductor2521is arranged is arranged as in A inFIG.272. The pad region2811in A inFIG.272is wider than pad region2715in A and B inFIG.271. That is, the pad region can be expanded by arranging the diagonal conductor or the stepped conductor in the mirror-symmetrical arrangement. Since the pads can be effectively arranged, the degree of freedom of pad arrangement is improved, and many pads can be arranged. Therefore, IR-Drop (voltage drop) may be able to be improved.

Furthermore, in the case of adopting the mirror-symmetrical arrangement for each of the two conductor layers, for example, in the case of adopting the structure of the first modification of the fifteenth configuration example illustrated in A inFIG.264for the conductor layer A and adopting the structure of the third modification of the fifteenth configuration example illustrated in A inFIG.265for the conductor layer B, the pad region2811can be arranged as illustrated in B inFIG.272, and the pad region can be further expanded. The pad region can be similarly expanded in the case of adopting the structure of the third modification of the fifteenth configuration example illustrated in A inFIG.265for the conductor layer A and adopting the structure of the first modification of the fifteenth configuration example illustrated in A inFIG.264for the conductor layer B.

A inFIG.273is a plan view illustrating a stacked state in the case of adopting the structure of the first modification of the fifteenth configuration example illustrated in A inFIG.264for the conductor layer A and adopting the structure of the second modification of the fifteenth configuration example illustrated in B inFIG.264for the conductor layer B. The stacked structure in the case of adopting the structure of the second modification of the fifteenth configuration example illustrated in B inFIG.264for the conductor layer A and adopting the structure of the first modification of the fifteenth configuration example illustrated in A inFIG.264for the conductor layer B is also similar.

B inFIG.273is a plan view illustrating a stacked state in the case of adopting the structure of the third modification of the fifteenth configuration example illustrated in A inFIG.265for the conductor layer A and adopting the structure of the fourth modification of the fifteenth configuration example illustrated in B inFIG.265for the conductor layer B. The stacked structure in the case of adopting the structure of the fourth modification of the fifteenth configuration example illustrated in B inFIG.265for the conductor layer A and adopting the structure of the third modification of the fifteenth configuration example illustrated in A inFIG.265for the conductor layer B is also similar.

When adopting the stacked layer of the conductor layers having the mirror arrangement structure, the light-shielding structure can be formed.

First Configuration Example of Mirror-Symmetrical Arrangement with Gap

Next, another configuration example of the mirror-symmetrical conductor layers will be described.

In the above-described example, the mirror-symmetrically arranged regions2531are continuously arranged without a gap, whereas a conductor layer2861inFIG.274is an example of a configuration in which the mirror-symmetrically arranged conductor regions are non-continuously arranged with a gap.

FIG.274is a plan view illustrating a first configuration example of a conductor layer (wiring layer) having mirror-symmetrically arranged conductors with a gap.

The conductor layer2861inFIG.274includes a first conductor region2851-1and a second conductor region2851-2and a gap region2852therebetween, and a conductor arranged in at least a part of the first conductor region2851-1and a conductor arranged in at least a part of the second conductor region2851-2are mirror-symmetrically arranged in the Y direction. That is, the first conductor region2851-1and the second conductor region2851-2are symmetrically arranged with respect to a center line L2861in the Y direction of the conductor layer2861.

The conductor layer2861can be applied as at least one of the conductor layers A to C and can also be used as a single-layer conductor layer.

In the conductor layer2861, a pad region2862can be arranged on each side of outer peripheral portions of a region including the first conductor region2851-1, the second conductor region2851-2, and the gap region2852. The pad region2862does not have to be arranged on all the four sides but may be arranged on at least one side. Furthermore, the pads do not have to be arranged in the entire pad region2862, and some pads may be arranged. Another conductor region may be provided between the first conductor region2851-1and the second conductor region2851-2, and the pad region2862.

The timings at which transistors operate may be the same or substantially the same, or different between a transistor group connected to the conductor in the first conductor region2851-1and a transistor group connected to the conductor in the second conductor region2851-2. In the case where the timings at which transistors operate are different between the transistor group in the first conductor region2851-1and the transistor group in the second conductor region2851-2, the capacitive noise in the Y direction generated from the conductors can be reduced.

FIGS.275to277illustrate examples of conductors that can be arranged in the first conductor region2851-1and the second conductor region2851-2that are mirror-symmetrical in the Y direction.

FIG.275illustrates a first conductor example that can be arranged in the first conductor region2851-1and the second conductor region2851-2inFIG.274, which are mirror-symmetrical in the Y direction.

A inFIG.275illustrates conductors arranged in the first conductor region2851-1. In the first conductor region2851-1, a linear conductor2871A as the Vss wiring and a linear conductor2871B as the Vdd wiring are alternately and periodically arranged in the X direction.

B inFIG.275illustrates conductors arranged in the second conductor region2851-2. In the second conductor region2851-2, a linear conductor2872A as the Vss wiring and a linear conductor2872B as the Vdd wiring are alternately and periodically arranged in the X direction.

According to the conductor configuration inFIG.275, the capacitive noise generated from the conductor can be completely canceled in the X direction.

FIG.276illustrates a second conductor example that can be arranged in the first conductor region2851-1and the second conductor region2851-2inFIG.274, which are mirror-symmetrical in the Y direction.

A inFIG.276illustrates conductors arranged in the first conductor region2851-1. In the first conductor region2851-1, a rectangular conductor2881A as the Vss wiring and a rectangular conductor2881B as the Vdd wiring are alternately and periodically arranged in the X and Y directions.

B inFIG.276illustrates conductors arranged in the second conductor region2851-2. In the second conductor region2851-2, a rectangular conductor2882A as the Vss wiring and a rectangular conductor2882B as the Vdd wiring are alternately and periodically arranged in the X and Y directions.

According to the conductor configuration inFIG.276, the capacitive noise generated from the conductors can be completely canceled in the X direction and can be partially canceled in the Y direction.

FIG.277illustrates a third conductor example that can be arranged in the first conductor region2851-1and the second conductor region2851-2inFIG.274, which are mirror-symmetrical in the Y direction.

A inFIG.277illustrates conductors arranged in the first conductor region2851-1. In the first conductor region2851-1, a conductor2883A as the Vss wiring and a conductor2883B as the Vdd wiring are alternately and periodically arranged in the X direction. The conductors2883A and2883B are conductors having a shape of a combination of a linear conductor extending in the Y direction and a diagonal conductor in the diagonal direction.

B inFIG.277illustrates conductors arranged in the second conductor region2851-2. In the second conductor region2851-2, a conductor2884A as the Vss wiring and a conductor2884B as the Vdd wiring are alternately and periodically arranged in the X direction. The conductors2884A and2884B are conductors having a shape of a combination of a linear conductor extending in the Y direction and a diagonal conductor in the diagonal direction.

According to the conductor configuration inFIG.277, the capacitive noise generated from the conductor can be completely canceled in the X direction and can be partially canceled in the Y direction.

Second Configuration Example of Mirror-Symmetrical Arrangement

FIG.278is a plan view illustrating a second configuration example of a conductor layer (wiring layer) having mirror-symmetrically arranged conductors.

A conductor layer2901inFIG.278includes a first conductor region2911-1and a second conductor region2911-2, and a gap region2912therebetween, and a conductor arranged in at least a part of the first conductor region2911-1and a conductor arranged in at least a part of the second conductor region2911-2are mirror-symmetrically arranged in the Y direction. That is, the first conductor region2911-1and the second conductor region2911-2are symmetrically arranged with respect to a center line L2901in the Y direction of the conductor layer2901. Furthermore, the conductor layer2901of the second configuration example is different from the conductor layer2861of the first configuration example illustrated inFIG.274in that a power supply connected to the conductor arranged in the first conductor region2911-1and a power supply connected to the conductor arranged in the second conductor region2911-2are inverted in polarity.

The conductor layer2901can be applied as at least one of the conductor layers A to C and can also be used as a single-layer conductor layer.

In the conductor layer2901, a pad region2902can be arranged on each side of outer peripheral portions of a region including the first conductor region2911-1, the second conductor region2911-2, and the gap region2912. The pad region2902does not have to be arranged on all the four sides but may be arranged on at least one side. Furthermore, the pads do not have to be arranged in the entire pad region2902, and some pads may be arranged. Another conductor region may be provided between the first conductor region2911-1and the second conductor region2911-2, and the pad region2902.

The timings at which transistors operate may be the same or substantially the same, or different between a transistor group connected to the conductor in the first conductor region2911-1and a transistor group connected to the conductor in the second conductor region2911-2. In the case where the timings at which transistors operate are the same or substantially the same between the transistor group in the first conductor region2911-1and the transistor group in the second conductor region2911-2, the capacitive noise in the Y direction generated from the conductors can be completely canceled.

FIG.279illustrates a first conductor example that can be arranged in the first conductor region2911-1and the second conductor region2911-2inFIG.278, which are mirror-symmetrical in the Y direction.

A inFIG.279illustrates conductors arranged in the first conductor region2911-1. In the first conductor region2911-1, a conductor having the same configuration as the conductor arranged in the first conductor region2851-1inFIG.275is arranged.

B inFIG.279illustrates conductors arranged in the second conductor region2911-2. In the second conductor region2911-2, a conductor having a configuration in which the power supply polarity is made opposite to the conductor arranged in the second conductor region2851-2inFIG.275is arranged.

In other words, inFIG.275, the polarities of the power supplies to which the linear conductor2871and the linear conductor2872at the same X position in the first conductor region2851-1and the second conductor region2851-2are respectively connected are the same.

In contrast, inFIG.279, the polarities of the power supplies to which the linear conductor2871and the linear conductor2872at the same X position in the first conductor region2911-1and the second conductor region2911-2are respectively connected are different (opposite).

According to the conductor configuration inFIG.279, the capacitive noise generated from the conductors can be completely canceled in the X and Y directions.

FIG.280illustrates a second conductor example that can be arranged in the first conductor region2911-1and the second conductor region2911-2inFIG.278, which are mirror-symmetrical in the Y direction.

A inFIG.280illustrates conductors arranged in the first conductor region2911-1. In the first conductor region2911-1, a conductor having the same configuration as the conductor arranged in the first conductor region2851-1inFIG.276is arranged.

B inFIG.280illustrates conductors arranged in the second conductor region2911-2. In the second conductor region2911-2, a conductor having a configuration in which the power supply polarity is made opposite to the conductor arranged in the second conductor region2851-2inFIG.276is arranged.

In other words, inFIG.276, the polarities of the power supplies to which the rectangular conductor2881and the rectangular conductor2882at the same X position in the first conductor region2851-1and the second conductor region2851-2and symmetrical in the Y direction are respectively connected are the same.

In contrast, inFIG.280, the polarities of the power supplies to which the rectangular conductor2881and the rectangular conductor2882at the same X position in the first conductor region2911-1and the second conductor region2911-2and symmetrical in the Y direction are respectively connected are different (opposite).

According to the conductor configuration inFIG.280, the capacitive noise generated from the conductors can be completely canceled in the X and Y directions.

FIG.281illustrates a third conductor example that can be arranged in the first conductor region2911-1and the second conductor region2911-2inFIG.278, which are mirror-symmetrical in the Y direction.

A inFIG.281illustrates conductors arranged in the first conductor region2911-1. In the first conductor region2911-1, a conductor having the same configuration as the conductor arranged in the first conductor region2851-1inFIG.277is arranged.

B inFIG.281illustrates conductors arranged in the second conductor region2911-2. In the second conductor region2911-2, a conductor having a configuration in which the power supply polarity is made opposite to the conductor arranged in the second conductor region2851-2inFIG.277is arranged.

In other words, inFIG.277, the polarities of the power supplies to which the conductor2883and the conductor2884at the same X position in the first conductor region2851-1and the second conductor region2851-2and symmetrical in the Y direction are respectively connected are the same.

In contrast, inFIG.281, the polarities of the power supplies to which the conductor2883and the conductor2884at the same X position in the first conductor region2911-1and the second conductor region2911-2and symmetrical in the Y direction are respectively connected are different (opposite).

According to the conductor configuration inFIG.281, the capacitive noise generated from the conductors can be completely canceled in the X and Y directions.

FIG.282illustrates a fourth conductor example that can be arranged in the first conductor region2911-1and the second conductor region2911-2inFIG.278, which are mirror-symmetrical in the Y direction.

A inFIG.282illustrates conductors arranged in the first conductor region2911-1. In the first conductor region2911-1, a reticulated conductor2891as the Vss wiring and a relay conductor2892as the Vdd wiring are arranged. Note that for the sake of simplicity, the conductor widths, gap widths, periods, and the like of the reticulated conductor2891and the relay conductor2892are the same as those of the reticulated conductor1201and the relay conductor1241of the conductor layer A in B inFIG.262.

B inFIG.282illustrates conductors arranged in the second conductor region2911-2. In the second conductor region2911-2, a reticulated conductor2893as the Vss wiring and a relay conductor2894as the Vdd wiring are arranged. Note that or the sake of simplicity, the conductor widths, gap widths, periods, and the like of the reticulated conductor2893and the relay conductor2894are the same as those of the reticulated conductor1202and the relay conductor1242of the conductor layer B in C inFIG.262.

According to the conductor configuration inFIG.282, the capacitive noise generated from the conductor can be completely canceled in the Y direction.

FIG.283illustrates a fifth conductor example that can be arranged in the first conductor region2911-1and the second conductor region2911-2inFIG.274, which are mirror-symmetrical in the Y direction.

The fifth conductor example ofFIG.283is different from the fourth conductor example inFIG.282in that the power supply polarities connected to the reticulated conductor and the relay conductor are inverted.

That is, in the fourth conductor example inFIG.282, the reticulated conductor2891in the first conductor region2911-1has been the Vss wiring and the relay conductor2892has been the Vdd wiring, whereas in the fifth conductor example inFIG.283, the reticulated conductor2895in the first conductor region2911-1is the Vdd wiring and the relay conductor2896is the Vss wiring.

Furthermore, in the fourth conductor example inFIG.282, the reticulated conductor2893in the second conductor region2911-2has been the Vdd wiring and the relay conductor2894has been the Vss wiring, whereas in the fifth conductor example inFIG.283, the reticulated conductor2897in the second conductor region2911-2is the Vss wiring, and the relay conductor2898is the Vdd wiring.

According to the conductor configuration inFIG.283, the capacitive noise generated from the conductor can be completely canceled in the Y direction.

Note that, in the case where the first conductor region2911-1and the second conductor region2911-2include a reticulated conductor as in the conductor configuration inFIGS.282and283, some or all of the relay conductors in the gap may be omitted. In other words, the conductor period of the reticulated conductor and the conductor period of the non-reticulated conductor (relay conductor) can be in a rational number relationship.

Furthermore, the reticulated conductor may be replaced with a planar conductor without providing a gap. Even in this case, the capacitive noise generated from the conductors can be completely canceled in the Y direction.

Furthermore, for example, by inverting the power supply polarities of the first conductor region2911-1and the second conductor region2911-2in the stacked two conductor layers, as in the stacked layer configuration adopting the fourth conductor example inFIG.282for the conductor layer A and the fifth conductor example inFIG.283for the conductor layer B, the direction of the loop plane in which the magnetic flux is generated from the Aggressor conductor loop and the direction of the loop plane that generates the induced electromotive force in the Victim conductor loop are different. Therefore, deterioration of an image output from the solid-state imaging device100(generation of the inductive noise) can be reduced. The stacked layer configuration of inverting the power supply polarities of the first conductor region2911-1and the second conductor region2911-2in the overlapping two conductor layers can be similarly applied to the first conductor example inFIG.279in which the power supply polarities are inverted between the first conductor region2911-1and the second conductor region2911-2in the conductor layer, the second conductor example inFIG.280, and the third conductor example inFIG.281. Furthermore, in the stacked layer configuration adopting the fourth conductor example inFIG.282for the conductor layer A and the fifth conductor example inFIG.283for the conductor layer B, the light-shielding structure can be formed by the stacked layer of the conductor layers A and B, and the hot carrier light emission can be shielded.

To effectively cancel the capacitive noise, the conductor widths in the X direction of the conductor arranged in the first conductor region2911-1and the conductor arranged in the second conductor region2911-2are desirably, but not limited to, the same or substantially the same. For the same reason, the conductor widths in the Y direction are desirably, but not limited to, the same or substantially the same.

Third Configuration Example of Mirror-Symmetrical Arrangement

FIG.284is a plan view illustrating a third configuration example of a conductor layer (wiring layer) having mirror-symmetrically arranged conductors.

InFIG.284, a portion corresponding to the mirror-symmetrical arrangement of the second configuration example illustrated inFIG.278is given the same reference numeral and description thereof is omitted as appropriate.

The third configuration example of the mirror-symmetrical arrangement illustrated inFIG.284is different from the second configuration example of the mirror-symmetrical arrangement illustrated inFIG.278in that a third conductor region2931is additionally provided in the gap region2912of the second configuration example. The gap region2912is formed between the third conductor region2931and the first conductor region2911-1or the second conductor region2911-2. Other points of the third configuration example are common to the second configuration example of the mirror-symmetrical arrangement illustrated inFIG.278.

The first conductor region2911-1and the second conductor region2911-2are symmetrically arranged with respect to a center line L2921in the Y direction of a conductor layer2921, and the polarities of the power supply connected to the conductor arranged in the first conductor region2911-1and the power supply connected to the conductor arranged in the second conductor region2911-2are inverted. Furthermore, the added third conductor region2931is also symmetrically arranged with respect to the center line L2921in the Y direction of the conductor layer2921. Therefore, the conductor layer2921inFIG.284has a mirror-symmetrical arrangement in the Y direction.

The conductor arranged in the third conductor region2931is connected to a power supply different from the power supply connected to the conductor arranged in the first conductor region2911-1and the conductor arranged in the second conductor region2911-2, or the timing is different even if the power supply is the same.

Fourth Configuration Example of Mirror-Symmetrical Arrangement

FIG.285is a plan view illustrating a fourth configuration example of a conductor layer (wiring layer) having mirror-symmetrically arranged conductors.

A conductor layer2941inFIG.285includes a first conductor region2951-1to a fourth conductor region2951-4and a gap region2952therebetween.

The conductor arranged in at least a part of the first conductor region2951-1and the conductor arranged in at least a part of the second conductor region2951-2are symmetrically arranged with respect to a center line L2941in the Y direction. The polarities of the power supply connected to the conductor arranged in the first conductor region2951-1and the power supply connected to the conductor arranged in the second conductor region2951-2are inverted.

The conductor arranged in at least a part of the third conductor region2951-3and the conductor arranged in at least a part of the fourth conductor region2951-4are symmetrically arranged with respect to a center line L2942in the Y direction. The polarities of the power supply connected to the conductor located in the third conductor region2951-3and the power supply connected to the conductor located in the fourth conductor region2951-4are inverted.

Furthermore, the power supply connected to the conductor arranged in the first conductor region2951-1and the power supply connected to the conductor arranged in the third conductor region2951-3are the same, and the power supply connected to the conductor arranged in the second conductor region2951-2and the power supply connected to the conductor arranged in the fourth conductor region2951-4are the same.

As described above, the conductor layer2941is mirror-symmetrically arranged in the Y direction. The conductor layer2941can be applied as at least one of the conductor layers A to C and can also be used as a single-layer conductor layer.

In the conductor layer2941, a pad region2942can be arranged on each side of outer peripheral portions of a region including the first conductor regions2951-1to the fourth conductor region2951-4, and the gap region2952therebetween. The pad region2942does not have to be arranged on all the four sides but may be arranged on at least one side. Furthermore, the pads do not have to be arranged in the entire pad region2942, and some pads may be arranged. Another conductor region may be provided between the first conductor regions2951-1to the fourth conductor region2951-4, and the gap region2952therebetween.

The sum of the conductor width in the Y direction of the conductor arranged in the first conductor region2951-1and the conductor width in the Y direction of the conductor arranged in the third conductor region2951-3(the sum of Y conductor widths of the Vss conductors) and the sum of the conductor width in the Y direction of the conductor arranged in the second conductor region2951-2and the conductor width in the Y direction of the conductor arranged in the fourth conductor region2951-4(the sum of Y conductor widths of the Vdd conductors) are desirably, but not limited to, the same or substantially the same. In the case where the sum of the Y conductor width of the Vss conductor and the sum of the Y conductor width of the Vdd conductor are the same, the capacitive noise in the Y direction generated from the conductors can be completely canceled.

Fifth Configuration Example of Mirror-Symmetrical Arrangement

FIG.286is a plan view illustrating a fifth configuration example of a conductor layer (wiring layer) having mirror-symmetrically arranged conductors.

A conductor layer2961inFIG.286includes a first conductor region2971-1to a fourth conductor region2971-4and a gap region2972therebetween.

The conductor arranged in at least a part of the first conductor region2971-1and the conductor arranged in at least a part of the second conductor region2971-2are symmetrically arranged with respect to a center line L2961in the Y direction. The polarities of the power supply connected to the conductor arranged in the first conductor region2971-1and the power supply connected to the conductor arranged in the second conductor region2971-2are inverted.

The conductor arranged in at least a part of the third conductor region2971-3and the conductor arranged in at least a part of the fourth conductor region2971-4are symmetrically arranged with respect to a center line L2962in the Y direction. The polarities of the power supply connected to the conductor arranged in the third conductor region2971-3and the power supply connected to the conductor arranged in the fourth conductor region2971-4are inverted.

Furthermore, the power supply connected to the conductor arranged in the first conductor region2971-1and the power supply connected to the conductor arranged in the third conductor region2971-3are the same, and the power supply connected to the conductor arranged in the second conductor region2971-2and the power supply connected to the conductor arranged in the fourth conductor region2971-4are the same. In the fifth configuration example inFIG.286, the positions of the third conductor region2971-3and the fourth conductor region2971-4are interchanged as compared with the fourth configuration example inFIG.285.

As described above, the conductor layer2961is mirror-symmetrically arranged in the Y direction. The conductor layer2961can be applied as at least one of the conductor layers A to C and can also be used as a single-layer conductor layer.

In the conductor layer2961, a pad region2962can be arranged on each side of outer peripheral portions of a region including the first conductor regions2971-1to the fourth conductor region2971-4, and the gap region2972therebetween. The pad region2962does not have to be arranged on all the four sides but may be arranged on at least one side. Furthermore, the pads do not have to be arranged in the entire pad region2962, and some pads may be arranged. Another conductor region may be provided between the first conductor regions2971-1to the fourth conductor region2971-4, and the gap region2972therebetween.

The sum of the conductor width in the Y direction of the conductor arranged in the first conductor region2971-1and the conductor width in the Y direction of the conductor arranged in the third conductor region2971-3(the sum of Y conductor widths of the Vss conductors) and the sum of the conductor width in the Y direction of the conductor arranged in the second conductor region2971-2and the conductor width in the Y direction of the conductor arranged in the fourth conductor region2971-4(the sum of Y conductor widths of the Vdd conductors) are desirably, but not limited to, the same or substantially the same. In the case where the sum of the Y conductor width of the Vss conductor and the sum of the Y conductor width of the Vdd conductor are the same, the capacitive noise in the Y direction generated from the conductors can be completely canceled.

Sixth Configuration Example of Mirror-Symmetrical Arrangement

FIG.287is a plan view illustrating a sixth configuration example of a conductor layer (wiring layer) having mirror-symmetrically arranged conductors.

A conductor layer2981inFIG.287includes a first conductor region2991-1to a third conductor region2991-3and a gap region2992therebetween.

The conductor arranged in at least a part of the first conductor region2991-1and the conductor arranged in at least a part of the third conductor region2991-3are symmetrically arranged with respect to a center line L2981in the Y direction. The conductor arranged in at least a part of the second conductor region2991-2is also arranged symmetrically with respect to the center line L2981in the Y direction.

The power supply connected to the conductor arranged in the first conductor region2991-1and the power supply connected to the conductor arranged in the third conductor region2991-3are the same, the polarities of the power supplies are opposite to the polarity of the power supply connected to the conductor arranged in the second conductor region2991-2.

As described above, the conductor layer2981is mirror-symmetrically arranged in the Y direction. The conductor layer2981can be applied as at least one of the conductor layers A to C and can also be used as a single-layer conductor layer.

In the conductor layer2981, a pad region2982can be arranged on each side of outer peripheral portions of a region including the first conductor regions2991-1to the third conductor region2991-3, and the gap region2992therebetween. The pad region2982does not have to be arranged on all the four sides but may be arranged on at least one side. Furthermore, the pads do not have to be arranged in the entire pad region2982, and some pads may be arranged. Another conductor region may be provided between the first conductor regions2991-1to the third conductor region2991-3, and the gap region2992therebetween.

The sum of the conductor width in the Y direction of the conductor arranged in the first conductor region2991-1and the conductor width in the Y direction of the conductor arranged in the third conductor region2991-3(the sum of Y conductor widths of the Vss conductors) and the sum of the conductor widths in the Y direction of the conductors arranged in the second conductor region2991-2(the sum of Y conductor widths of the Vdd conductor) are desirably, but not limited to, the same or substantially the same. In the case where the sum of the Y conductor width of the Vss conductor and the sum of the Y conductor width of the Vdd conductor are the same, the capacitive noise in the Y direction generated from the conductors can be completely canceled.

In the first to sixth configuration examples of the mirror-symmetrical arrangement, the polarity of the power supply to which each conductor is connected may be the opposite of the above-described example. That is, in the above-described first to sixth configuration examples, for example, the wiring connected to the GND or the negative power supply (Vss wiring) may be the wiring connected to the positive power supply (Vdd wiring), and the wiring (Vdd wiring) connected to the positive power supply may be the wiring (Vss wiring) connected to the GND or the negative power supply.

In the first to sixth configuration examples of the mirror-symmetrical arrangement, the dimensional difference and the angular difference described as being the same may be substantially the same. The substantially the same is a difference in a range that can be regarded as the same, but for example, the difference is a difference in a range not exceeding at least twice. The mirror symmetry may also be substantially mirror symmetry. The substantially mirror symmetry is, for example, a difference in a range in which the structural dimensional difference or angular difference do not exceed at least twice.

17. Configuration Example of Imaging Device

For example, the above-described solid-state imaging device100can be applied to a camera system such as a digital camera or a video camera, a mobile phone having an imaging function, another device having an imaging function, or an electronic device including a semiconductor device including a high-sensitivity analog element such as a flash memory.

FIG.288is a block diagram illustrating a configuration example of an imaging device700as an example of the electronic device.

The imaging device700includes a solid-state image sensor701, an optical system702that guides incident light to the solid-state image sensor701, a shutter mechanism703provided between the solid-state image sensor701and the optical system702, and a drive circuit704that drives the solid-state image sensor701. Moreover, the imaging device700includes a signal processing circuit705that processes an output signal of the solid-state image sensor701.

The solid-state image sensor701corresponds to the above-described solid-state imaging device100. The optical system702includes an optical lens group or the like, and causes image light (incident light) from an object to be incident on the solid-state image sensor701. Thereby, a signal charge is accumulated in the solid-state image sensor701for a fixed period. The shutter mechanism703controls a light irradiation period and a light blocking period of the incident light on the solid-state image sensor701.

The drive circuit704supplies a drive signal to the solid-state image sensor701and the shutter mechanism703. Then, the drive circuit704controls a signal output operation of the solid-state image sensor701to the signal processing circuit705and a shutter operation of the shutter mechanism703by the supplied drive signal. That is, in this example, a signal transfer operation from the solid-state image sensor701to the signal processing circuit705is performed by the drive signal (timing signal) supplied from the drive circuit704.

The signal processing circuit705applies various types of signal processing to the signal transferred from the solid-state image sensor701. Then, the signal (video signal) to which the various types of signal processing have been applied is stored in a storage medium (not illustrated) such as a memory, or output to a monitor (not illustrated).

According to the electronic device such as the above-described imaging device700, noise generation due to leakage of light such as hot carrier light emission from an active element such as a MOS transistor or a diode into a light-receiving element during operation in a peripheral circuit can be suppressed in the solid-state image sensor701. Therefore, a high-quality electronic device with improved image quality can be provided.

18. Application to In-Vivo Information Acquisition System

The technology according to the present disclosure (present technology) can be applied to various products. For example, the technology according to the present disclosure may be applied to an in-vivo information acquisition system for patients using a capsule endoscope.

FIG.289is a block diagram illustrating an example of a schematic configuration of an in-vivo information acquisition system for patients using a capsule endoscope, to which the technology according to the present disclosure is applicable.

An in-vivo information acquisition system10001includes a capsule endoscope10100and an external control device10200.

The capsule endoscope10100is swallowed by a patient at the time of examination. The capsule endoscope10100has an imaging function and a wireless communication function, and sequentially captures images of inside of organs (hereinafter also referred to as in-vivo images) at predetermined intervals while moving inside the organs such as stomach and intestine by peristaltic movement or the like until the patient naturally discharges the capsule endoscope10100, and sequentially wirelessly transmits information of the in-vivo images to the external control device10200outside the body.

The external control device10200comprehensively controls the operation of the in-vivo information acquisition system10001. Furthermore, the external control device10200receives information regarding the in-vivo image transmitted from the capsule endoscope10100, and transmits image data for displaying the in-vivo image to the display device (not illustrated) on the basis of the information regarding the received in-vivo image.

As described above, the in-vivo information acquisition system10001can acquire the in-vivo images obtained by imaging the inside of the patient's body from time to time during a period from when the capsule endoscope10100is swallowed to when the capsule endoscope10100is discharged.

The configurations and functions of the capsule endoscope10100and the external control device10200will be described in more detail.

The capsule endoscope10100has a capsule-shaped housing10101, and a light source unit10111, an imaging unit10112, an image processing unit10113, a wireless communication unit10114, a power feed unit10115, a power supply unit10116, and a control unit10117are housed inside the housing10101.

The light source unit10111includes, for example, a light source such as a light emitting diode (LED), and irradiates an imaging field of view of the imaging unit10112with light.

The imaging unit10112includes an optical system including an imaging element and a plurality of lenses provided in front of the imaging element. Reflected light (hereinafter referred to as observation light) of the light radiated on a body tissue that is an observation target is collected by the optical system and enters the imaging element. The imaging unit10112photoelectrically converts the observation light having entered the imaging element to generate an image signal corresponding to the observation light. The image signal generated by the imaging unit10112is provided to the image processing unit10113.

The image processing unit10113includes processors such as a central processing unit (CPU) and a graphics processing unit (GPU), and performs various types of signal processing for the image signal generated by the imaging unit10112. The image processing unit10113provides the image signal to which the signal processing has been applied to the wireless communication unit10114as raw data.

The wireless communication unit10114performs predetermined processing such as modulation processing for the image signal to which the signal processing has been applied by the image processing unit10113and transmits the image signal to the external control device10200via an antenna 10114A. Furthermore, the wireless communication unit10114receives a control signal related to drive control of the capsule endoscope10100from the external control device10200via the antenna 10114A. The wireless communication unit10114provides the control signal received from the external control device10200to the control unit10117.

The power feed unit10115includes an antenna coil for power reception, a power regeneration circuit for regenerating power from a current generated in the antenna coil, a booster circuit, and the like. The power feed unit10115generates power using a principle of so-called non-contact charging.

The power supply unit10116includes a secondary battery, and stores the power generated by the power feed unit10115. InFIG.289, illustration of arrows or the like indicating a supply destination of the power from the power supply unit10116is omitted to avoid complication of the drawing. However, the power stored in the power supply unit10116is supplied to the light source unit10111, the imaging unit10112, the image processing unit10113, the wireless communication unit10114, and the control unit10117, and can be used to drive these units.

The control unit10117includes a processor such as a CPU and appropriately controls drive of the light source unit10111, the imaging unit10112, the image processing unit10113, the wireless communication unit10114, and the power feed unit10115with control signals transmitted from the external control device10200.

The external control device10200includes a processor such as a CPU and a GPU, a microcomputer in which a processor and a memory element such as a memory are mixed, a control board, or the like. The external control device10200controls the operation of the capsule endoscope10100by transmitting a control signal to the control unit10117of the capsule endoscope10100via an antenna 10200A. In the capsule endoscope10100, for example, irradiation conditions of light with respect to the observation target in the light source unit10111can be changed according to the control signal from the external control device10200. Furthermore, imaging conditions (for example, a frame rate in the imaging unit10112, an exposure value, and the like) can be changed according to the control signal from the external control device10200. Furthermore, the content of the processing in the image processing unit10113, and conditions for transmitting the image signal by the wireless communication unit10114(for example, a transmission interval, the number of transmitted images, and the like) may be changed according to the control signal from the external control device10200.

Furthermore, the external control device10200applies various types of image processing to the image signal transmitted from the capsule endoscope10100to generate image data for displaying the captured in-vivo image on the display device. As the image processing, various types of signal processing can be performed, such as development processing (demosaicing processing), high image quality processing (band enhancement processing, super resolution processing, noise reduction (NR) processing, and/or camera shake correction processing, for example), and/or enlargement processing (electronic zoom processing), for example. The external control device10200controls drive of the display device and displays in-vivo images captured on the basis of the generated image data. Alternatively, the external control device10200may cause a recording device (not illustrated) to record the generated image data or cause a printing device (not illustrated) to print out the generated image data.

An example of the in-vivo information acquisition system to which the technology according to the present disclosure is applicable has been described. The technology according to the present disclosure is applicable to the imaging unit10112among the above-described configurations. Specifically, the above-described solid-state imaging device100can be applied as the imaging unit10112. By applying the technology according to the present disclosure to the imaging unit10112, by applying the technology according to the present disclosure to the imaging unit10112, generation of noise is suppressed and a clearer operation portion image can be obtained. Therefore, the accuracy of an examination is improved.

19. Application to Endoscopic Surgical System

The technology according to the present disclosure (present technology) can be applied to various products. For example, the technology according to the present disclosure may be applied to an endoscopic surgical system.

FIG.290is a diagram illustrating an example of a schematic configuration of an endoscopic surgical system to which the technology according to the present disclosure (present technology) is applicable.

FIG.290illustrates a state in which an operator (surgeon)11131is performing surgery for a patient11132on a patient bed11133, using an endoscopic surgical system11000. As illustrated inFIG.213, the endoscopic surgical system11000includes an endoscope11100, other surgical instruments11110such as a pneumoperitoneum tube11111and an energy treatment tool11112, a support arm device11120that supports the endoscope11100, and a cart11200on which various devices for endoscope surgery are mounted.

The endoscope11100includes a lens-barrel11101and a camera head11102. A region having a predetermined length from a distal end of the lens-barrel11101is inserted into a body cavity of the patient11132. The camera head11102is connected to a proximal end of the lens-barrel11101.FIG.213illustrates the endoscope11100configured as so-called a hard endoscope including the hard lens-barrel11101. However, the endoscope11100may be configured as so-called a soft endoscope including a soft lens-barrel.

An opening portion in which an object lens is fit is provided in the distal end of the lens-barrel11101. A light source device11203is connected to the endoscope11100, and light generated by the light source device11203is guided to the distal end of the lens-barrel11101by a light guide extending inside the lens-barrel11101and an observation target in the body cavity of the patient11132is irradiated with the light through the object lens. Note that the endoscope11100may be a forward-viewing endoscope, may be an oblique-viewing endoscope, or may be a side-viewing endoscope.

An optical system and an imaging element are provided inside the camera head11102, and reflected light (observation light) from the observation target is condensed to the imaging element by the optical system. The observation light is photoelectrically converted by the imaging element, and an electrical signal corresponding to the observation light, in other words, an image signal corresponding to an observed image is generated. The image signal is transmitted to a camera control unit (CCU)11201as raw data.

The CCU11201includes a central processing unit (CPU), a graphics processing unit (GPU), and the like, and comprehensively controls an operation of the endoscope11100and a display device11202. Moreover, the CCU11201receives the image signal from the camera head11102, and applies various types of image processing for displaying an image based on the image signal, such as developing processing (demosaicing processing) or the like, to the image signal.

The display device11202displays the image based on the image signal to which the image processing has been applied by the CCU11201, by control of the CCU11201.

The light source device11203includes a light source such as a light emitting diode (LED) for example, and supplies irradiation light to the endoscope11100in capturing an operation portion or the like.

An input device11204is an input interface for the endoscopic surgical system11000. A user can input various types of information and instructions to the endoscopic surgical system11000through the input device11204. For example, the user inputs an instruction to change imaging conditions (a type of irradiation light, a magnification, a focal length, and the like) by the endoscope11100, and the like.

A treatment tool control device11205controls driving of the energy treatment tool11112for cauterization and incision of tissue, sealing of a blood vessel, and the like. A pneumoperitoneum device11206sends a gas into the body cavity of the patient11132through the pneumoperitoneum tube11111to expand the body cavity for the purpose of securing a field of view by the endoscope11100and a work space for the operator. A recorder11207is a device that can record various types of information regarding the surgery. A printer11208is a device that can print the various types of information regarding the surgery in various formats such as a text, an image, and a graph.

Note that the light source device11203that supplies the irradiation light in capturing the operation portion to the endoscope11100can be configured from a white light source configured from an LED, a laser light source, or a combination of the LED and the laser light source, for example. In a case where the white light source is configured from a combination of RGB laser light sources, output intensity and output timing of the respective colors (wavelengths) can be controlled with high accuracy. Therefore, adjustment of white balance of the captured image can be performed in the light source device11203. Furthermore, in this case, the observation target is irradiated with the laser light from each of the RGB laser light sources in a time division manner, and the drive of the imaging element of the camera head11102is controlled in synchronization with the irradiation timing, so that images respectively corresponding to RGB can be captured in a time division manner. According to the method, a color image can be obtained without providing a color filter to the imaging element.

Furthermore, drive of the light source device11203may be controlled to change intensity of light to be output every predetermined time. The drive of the imaging element of the camera head11102is controlled in synchronization with change timing of the intensity of light and images are acquired in a time division manner, and the images are synthesized, so that a high-dynamic range image without so-called clipped blacks and flared highlights can be generated.

Furthermore, the light source device11203may be configured to be able to supply light in a predetermined wavelength band corresponding to special light observation. In the special light observation, for example, so-called narrow band imaging is performed by radiating light in a narrower band than the irradiation light (in other words, white light) at the time of normal observation, using wavelength dependence of absorption of light in a body tissue, to capture a predetermined tissue such as a blood vessel in a mucosal surface layer at high contrast. Alternatively, in the special light observation, fluorescence imaging may be performed to obtain an image by fluorescence generated by radiation of exciting light. In the fluorescence imaging, irradiating the body tissue with exciting light to observe fluorescence from the body tissue (self-fluorescence observation), or injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the body tissue with exciting light corresponding to a fluorescence wavelength of the reagent to obtain a fluorescence image, for example, can be performed. The light source device11203can be configured to be able to supply narrow band light and/or exciting light corresponding to such special light observation.

FIG.291is a block diagram illustrating an example of functional configurations of the camera head11102and the CCU11201illustrated inFIG.290.

The camera head11102includes a lens unit11401, an imaging unit11402, a drive unit11403, a communication unit11404, and a camera head control unit11405. The CCU11201includes a communication unit11411, an image processing unit11412, and a control unit11413. The camera head11102and the CCU11201are communicatively connected with each other by a transmission cable11400.

The lens unit11401is an optical system provided in a connection portion between the camera head11102and the lens-barrel11101. Observation light taken through the distal end of the lens-barrel11101is guided to the camera head11102and enters the lens unit11401. The lens unit11401is configured by a combination of a plurality of lenses including a zoom lens and a focus lens.

The imaging unit11402is configured by an imaging element. The imaging element that configures the imaging unit11402may be one imaging element (so-called single imaging element) or may be a plurality of imaging elements (so-called multiple imaging elements). In a case where the imaging unit11402is configured by multiple imaging elements, for example, a color image may be obtained by generating image signals respectively corresponding to RGB by the imaging elements and synthesizing the image signals. Alternatively, the imaging unit11402may be configured by a pair of imaging elements for respectively obtaining image signals for right eye and for left eye corresponding to three-dimensional (3D) display. With the 3D display, the operator11131can more accurately grasp the depth of a biological tissue in the operation portion. Note that, in a case where the imaging unit11402is configured by the multiple imaging elements, a plurality of systems of the lens units11401may be provided corresponding to the imaging elements.

Furthermore, the imaging unit11402may not be necessarily provided in the camera head11102. For example, the imaging unit11402may be provided immediately after the object lens inside the lens-barrel11101.

The drive unit11403is configured by an actuator, and moves the zoom lens and the focus lens of the lens unit11401by a predetermined distance along an optical axis by control of the camera head control unit11405. With the movement, a magnification and a focal point of a captured image by the imaging unit11402can be appropriately adjusted.

The communication unit11404is configured by a communication device for transmitting or receiving various types of information to or from the CCU11201. The communication unit11404transmits the image signal obtained from the imaging unit11402to the CCU11201through the transmission cable11400as raw data.

Furthermore, the communication unit11404receives a control signal for controlling drive of the camera head11102from the CCU11201and supplies the control signal to the camera head control unit11405. The control signal includes information regarding the imaging conditions such as information for specifying a frame rate of the captured image, information for specifying an exposure value at the time of imaging, and/or information for specifying the magnification and the focal point of the captured image, for example.

Note that the imaging conditions such as the frame rate, the exposure value, the magnification, and the focal point may be appropriately specified by the user or may be automatically set by the control unit11413of the CCU11201on the basis of the acquired image signal. In the latter case, so-called an auto exposure (AE) function, an auto focus (AF) function, and an auto white balance (AWB) function are incorporated in the endoscope11100.

The camera head control unit11405controls drive of the camera head11102on the basis of the control signal received through the communication unit11404from the CCU11201.

The communication unit11411is configured from a communication device for transmitting or receiving various types of information to or from the camera head11102. The communication unit11411receives the image signal transmitted from the camera head11102through the transmission cable11400.

Furthermore, the communication unit11411transmits a control signal for controlling drive of the camera head11102to the camera head11102. The image signal and the control signal can be transmitted through telecommunication, optical communication, or the like.

The image processing unit11412applies various types of image processing to the image signal as raw data transmitted from the camera head11102.

The control unit11413performs various types of control regarding imaging of the operation portion and the like by the endoscope11100and display of the captured image obtained through imaging of the operation portion and the like. For example, the control unit11413generates a control signal for controlling drive of the camera head11102.

Furthermore, the control unit11413displays the captured image of the operation portion or the like in the display device11202on the basis of the image signal to which the image processing has been applied by the image processing unit11412. At this time, the control unit11413may recognize various objects in the captured image, using various image recognition technologies. For example, the control unit11413can recognize a surgical instrument such as forceps, a specific living body portion, blood, mist at the time of use of the energy treatment tool11112, or the like, by detecting a shape of an edge, a color, or the like of an object included in the captured image. The control unit11413may superimpose and display various types of surgery support information on the image of the operation portion using a result of the recognition, in displaying the captured image in the display device11202. The superimposition and display, and presentation of the surgery support information to the operator11131can reduce a burden on the operator11131and enables the operator11131to reliably proceed with the operation.

The transmission cable11400that connects the camera head11102and the CCU11201is an electrical signal cable corresponding to communication of electrical signals, an optical fiber corresponding to optical communication, or a composite cable thereof.

Here, in the illustrated example, the communication has been performed in a wired manner using the transmission cable11400. However, the communication between the camera head11102and the CCU11201may be wirelessly performed.

An example of an endoscopic surgical system to which the technology according to the present disclosure is applicable has been described. The technology according to the present disclosure is applicable to, for example, the imaging unit11402of the camera head11102in the above-described configurations. Specifically, the above-described solid-state imaging device100can be applied as the imaging unit11402. By applying the technology according to the present disclosure to the imaging unit11402, generation of noise is suppressed and a clearer operation portion image can be obtained. Therefore, the operator can reliably confirm the operation portion.

Note that, here, the endoscopic surgical system has been described as an example. However, the technology according to the present disclosure may be applied to microsurgery system or the like, for example.

20. Application to Moving Bodies

Moreover, the technology according to the present disclosure may be implemented as, for example, a device mounted on any type of moving bodies including an automobile, an electric automobile, a hybrid electric automobile, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a ship, a robot, and the like.

FIG.292is a block diagram illustrating a schematic configuration example of a vehicle control system as an example of a moving body control system to which the technology according to the present disclosure is applicable.

A vehicle control system12000includes a plurality of electronic control units connected through a communication network12001. In the example illustrated inFIG.292, the vehicle control system12000includes a drive system control unit12010, a body system control unit12020, a vehicle exterior information detection unit12030, a vehicle interior information detection unit12040, and an integrated control unit12050. Furthermore, as functional configurations of the integrated control unit12050, a microcomputer12051, a sound image output unit12052, and an in-vehicle network interface (I/F)12053are illustrated.

The drive system control unit12010controls operations of devices regarding a drive system of a vehicle according to various programs. For example, the drive system control unit12010functions as a control device of a drive force generation device for generating drive force of a vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting drive force to wheels, a steering mechanism that adjusts a steering angle of a vehicle, a braking device that generates braking force of a vehicle, and the like.

The body system control unit12020controls operations of various devices equipped in a vehicle body according to various programs. For example, the body system control unit12020functions as a control device of a keyless entry system, a smart key system, an automatic window device, and various lamps such as head lamps, back lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a mobile device substituted for a key or signals of various switches can be input to the body system control unit12020. The body system control unit12020receives an input of the radio waves or the signals, and controls a door lock device, the automatic window device, the lamps, and the like of the vehicle.

The vehicle exterior information detection unit12030detects information outside the vehicle that mounts the vehicle control system12000. For example, an imaging unit12031is connected to the vehicle exterior information detection unit12030. The vehicle exterior information detection unit12030causes the imaging unit12031to capture an image outside the vehicle, and receives the captured image. The vehicle exterior information detection unit12030may perform object detection processing or distance detection processing of persons, vehicles, obstacles, signs, letters on a road surface, or the like on the basis of the received image.

The imaging unit12031is an optical sensor that receives light and outputs an electrical signal according to a reception amount of the light. The imaging unit12031can output the electrical signal as an image and can output the electrical signal as information of distance measurement. Furthermore, the light received by the imaging unit12031may be visible light or may be non-visible light such as infrared light.

The vehicle interior information detection unit12040detects information inside the vehicle. A driver state detection unit12041that detects a state of a driver is connected to the vehicle interior information detection unit12040, for example. The driver state detection unit12041includes a camera that captures the driver, for example, and the vehicle interior information detection unit12040may calculate the degree of fatigue or the degree of concentration of the driver, or may determine whether or not the driver falls asleep on the basis of the detection information input from the driver state detection unit12041.

The microcomputer12051calculates a control target value of the drive force generation device, the steering mechanism, or the braking device on the basis of the information outside and inside the vehicle acquired in the vehicle exterior information detection unit12030or the vehicle interior information detection unit12040, and can output a control command to the drive system control unit12010. For example, the microcomputer12051can perform cooperative control for the purpose of realization of an advanced driver assistance system (ADAS) function including collision avoidance or shock mitigation of the vehicle, following travel based on a vehicular gap, vehicle speed maintaining travel, collision warning of the vehicle, lane out warning of the vehicle, and the like.

Furthermore, the microcomputer12051controls the drive force generation device, the steering mechanism, the braking device, or the like on the basis of the information of a vicinity of the vehicle acquired in the vehicle exterior information detection unit12030or the vehicle interior information detection unit12040to perform cooperative control for the purpose of automatic drive of autonomous travel without depending on an operation of the driver or the like.

Furthermore, the microcomputer12051can output a control command to the body system control unit12020on the basis of the information outside the vehicle acquired in the vehicle exterior information detection unit12030. For example, the microcomputer12051can perform cooperative control for the purpose of achievement of non-glare such as by controlling the head lamps according to the position of a leading vehicle or an oncoming vehicle detected in the vehicle exterior information detection unit12030, and switching high beam light to low beam light.

The sound image output unit12052transmits an output signal of at least one of a sound or an image to an output device that can visually and aurally notify a passenger of the vehicle or an outside of the vehicle of information. In the example inFIG.292, as the output device, an audio speaker12061, a display unit12062, and an instrument panel12063are exemplarily illustrated. The display unit12062may include, for example, at least one of an on-board display or a head-up display.

FIG.293is a diagram illustrating an example of an installation position of the imaging unit12031.

InFIG.293, a vehicle12100includes, as the imaging unit12031, imaging units12101,12102,12103,12104, and12105.

The imaging units12101,12102,12103,12104, and12105are provided at positions of a front nose, side mirrors, a rear bumper or a back door, an upper portion of a windshield, and the like in an interior of the vehicle12100, for example. The imaging unit12101provided at the front nose and the imaging unit12105provided at an upper portion of the windshield in an interior of the vehicle mainly acquire images in front of the vehicle12100. The imaging units12102and12103provided at the side mirrors mainly acquire images on sides of the vehicle12100. The imaging unit12104provided at the rear bumper or the back door mainly acquires a rear image of the vehicle12100. The front images acquired in the imaging units12101and12105are mainly used for detection of a leading vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.

Note thatFIG.293illustrates an example of capture ranges of the imaging units12101to12104. An imaging range12111indicates the imaging range of the imaging unit12101provided at the front nose, imaging ranges12112and12113respectively indicate the imaging ranges of the imaging units12102and12103provided at the side mirrors, and an imaging range12114indicates the imaging range of the imaging unit12104provided at the rear bumper or the back door. For example, a bird's-eye view image of the vehicle12100as viewed from above can be obtained by superimposing image data captured by the imaging units12101to12104.

At least one of the imaging units12101to12104may have a function to acquire distance information. For example, at least one of the imaging units12101to12104may be a stereo camera including a plurality of imaging elements or may be an image element having pixels for phase difference detection.

For example, the microcomputer12051obtains distances to three-dimensional objects in the imaging ranges12111to12114and temporal change of the distances (relative speeds to the vehicle12100) on the basis of the distance information obtained from the imaging units12101to12104, thereby to particularly extract a three-dimensional object closest to the vehicle12100on a traveling road and traveling at a predetermined speed (for example, 0 km/h or more) in substantially the same direction as the vehicle12100as a leading vehicle. Moreover, the microcomputer12051can set an inter-vehicle distance to be secured from the leading vehicle in advance and perform automatic braking control (including following stop control) and automatic acceleration control (including following start control), and the like. In this way, the cooperative control for the purpose of automatic driving of autonomous travel without depending on an operation of the driver, and the like can be performed.

For example, the microcomputer12051classifies three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary cars, large vehicles, pedestrians, and other three-dimensional objects such as electric poles to be extracted, on the basis of the distance information obtained from the imaging units12101to12104, and can use the data for automatic avoidance of obstacles. For example, the microcomputer12051discriminates obstacles around the vehicle12100into obstacles visually recognizable by the driver of the vehicle12100and obstacles visually unrecognizable by the driver. The microcomputer12051then determines a collision risk indicating a risk of collision with each of the obstacles, and can perform drive assist for collision avoidance by outputting warning to the driver through the audio speaker12061or the display unit12062, and performing forced deceleration or avoidance steering through the drive system control unit12010, in a case where the collision risk is a set value or more and there is a collision possibility.

At least one of the imaging units12101to12104may be an infrared camera that detects infrared light. For example, the microcomputer12051determines whether or not a pedestrian exists in the captured images of the imaging units12101to12104, thereby to recognize the pedestrian. Such recognition of a pedestrian is performed by a process of extracting characteristic points in the captured images of the imaging units12101to12104, as the infrared camera, for example, and by a process of performing pattern matching processing for the series of characteristic points indicating a contour of an object and determining whether or not the object is a pedestrian. When the microcomputer12051determines that a pedestrian exists in the captured images of the imaging units12101to12104and recognizes the pedestrian, the sound image output unit12052causes the display unit12062to superimpose and display a square contour line for emphasis on the recognized pedestrian. Furthermore, the sound image output unit12052may cause the display unit12062to display an icon or the like representing the pedestrian at a desired position.

An example of a vehicle control system to which the technology according to the present disclosure is applicable has been described. The technology according to the present disclosure is applicable to, for example, the imaging unit12031among the above-described configurations. Specifically, the above-described solid-state imaging device100can be applied as the imaging unit12031. By applying the technology according to the present disclosure to the imaging unit12031, generation of noise can be suppressed, and an easier-to-see captured image can be obtained. Therefore, the driving by the driver can be appropriately assisted.

Embodiments of the present technology are not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present technology.

Note that the effects described in the present specification are merely illustrative and are not restrictive, and effects other than the effects described in the present specification may be exhibited.

Note that the present technology can have the following configurations.

A circuit board including:a first conductor periodically arranged with a first periodic width in a first region;a second conductor periodically arranged with a second periodic width in the first region;a third conductor periodically arranged with a third periodic width in a second region different from the first region; anda fourth conductor periodically arranged with a fourth periodic width in the second region, in whichthe first periodic width and the second periodic width are in a rational number relationship,the third periodic width and the fourth periodic width are in a rational number relationship,the first periodic width and the fourth periodic width are same or substantially same,the first region and the second region have a conductor structure mirror-symmetrical or substantially mirror-symmetrical in a first direction, anda first power supply connected to the first conductor and the third conductor and a second power supply connected to the second conductor and the fourth conductor are power supplies having different voltage values.

The circuit board according to (1), in whicha sum of conductive areas within a predetermined range of the first conductor and the third conductor connected to the first power supply, anda sum of conductive areas within a predetermined range of the second conductor and the fourth conductor connected to the second power supply are same or substantially same.

The circuit board according to (1) or (2), in whicha sum of conductor widths within a predetermined range of the first conductor and the third conductor connected to the first power supply, anda sum of conductor widths within a predetermined range of the second conductor and the fourth conductor connected to the second power supply are same or substantially same.

The circuit board according to any one of (1) to (3), in whichthe first conductor and the second conductor in the first region are diagonal conductors or stepped conductors arranged at a first angle with respect to the first direction,the third conductor and the fourth conductor in the second region are diagonal conductors or stepped conductors arranged at a second angle with respect to the first direction,the first angle is in a relationship of 0°<the first angle <90°,the second angle is in a relationship of −90°<the second angle <0°, andan absolute value of the first angle and an absolute angle of the second angle are same or substantially same.

The circuit board according to (4), in whichthe first conductor is periodically arranged with the first periodic width in a direction orthogonal to the first angle,the second conductor is periodically arranged with the second periodic width in a direction orthogonal to the first angle,the third conductor is periodically arranged with the third periodic width in a direction orthogonal to the second angle, andthe fourth conductor is periodically arranged with the fourth periodic width in a direction orthogonal to the second angle.

The circuit board according to any one of (1) to (5), in whichthe first region and the second region also have a conductor structure mirror-symmetrical or substantially mirror-symmetrical in a second direction orthogonal to the first direction.

The circuit board according to any one of (1) to (6), in whichthe first to fourth conductors are arranged in a same first conductor layer.

The circuit board according to any one of (1) to (7), in whicheach of the first to fourth conductors is at least one of a linear conductor or a rectangular conductor.

The circuit board according to any one of (1) to (7), in whicheach of the first to fourth conductors is at least one of a reticulated conductor or a planar conductor.

The circuit board according to any one of (1) to (7), in whichthe first conductor and the fourth conductor are reticulated conductors, andthe second conductor and the third conductor are non-reticulated conductors.

The circuit board according to any one of (1) to (10), in whichthe first conductor and the third conductor are mirror-symmetrically or substantially mirror-symmetrically arranged in the first direction, andthe second conductor and the fourth conductor are mirror-symmetrically or substantially mirror-symmetrically arranged in the first direction.

The circuit board according to any one of (1) to (10), in whichthe first conductor and the fourth conductor are mirror-symmetrically or substantially mirror-symmetrically arranged in the first direction, andthe second conductor and the third conductor are mirror-symmetrically or substantially mirror-symmetrically arranged in the first direction.

The circuit board according to any one of (1) to (12), in whichthe first region and the second region are continuously arranged without providing a gap between the first region and the second region.

The circuit board according to any one of (1) to (12), in whichthe first region and the second region are discontinuously arranged with providing a gap between the first region and the second region.

The circuit board according to any one of (1) to (14), further including:a conductor group arranged at a position overlapping with at least a part of the first region and at least a part of the second region as viewed from the first direction and a third direction orthogonal to the second direction orthogonal to the first direction.

The circuit board according to (15), in whichthe conductor group is a control line that controls a transistor of a pixel or a signal line that transmits a pixel signal.

The circuit board according to (15) or (16), in whichthe conductor group is configured by periodically arranging two or more conductors longer in the first direction than in the second direction with a fifth periodic width in the second direction.

The circuit board according to (17), further including:a circuit configured to selectively switch one or more conductors from among the two or more conductors configuring the conductor group.

A semiconductor device includinga circuit board including:a first conductor periodically arranged with a first periodic width in a first region;a second conductor periodically arranged with a second periodic width in the first region;a third conductor periodically arranged with a third periodic width in a second region different from the first region; anda fourth conductor periodically arranged with a fourth periodic width in the second region, in whichthe first periodic width and the second periodic width are in a rational number relationship,the third periodic width and the fourth periodic width are in a rational number relationship,the first periodic width and the fourth periodic width are same or substantially same,the first region and the second region have a conductor structure mirror-symmetrical or substantially mirror-symmetrical in a first direction, anda first power supply connected to the first conductor and the third conductor and a second power supply connected to the second conductor and the fourth conductor are power supplies having different voltage values.

An electronic device includinga semiconductor device including a circuit board including:a first conductor periodically arranged with a first periodic width in a first region;a second conductor periodically arranged with a second periodic width in the first region;a third conductor periodically arranged with a third periodic width in a second region different from the first region; anda fourth conductor periodically arranged with a fourth periodic width in the second region, in whichthe first periodic width and the second periodic width are in a rational number relationship,the third periodic width and the fourth periodic width are in a rational number relationship,the first periodic width and the fourth periodic width are same or substantially same,the first region and the second region have a conductor structure mirror-symmetrical or substantially mirror-symmetrical in a first direction, anda first power supply connected to the first conductor and the third conductor and a second power supply connected to the second conductor and the fourth conductor are power supplies having different voltage values.

REFERENCE SIGNS LIST