Wiring substrate and method for manufacturing the same

A wiring substrate includes a first outermost conductor layer, a first outermost insulating layer covering the first conductor layer, a second outermost conductor layer formed on opposite side of the first conductor layer, and a second outermost insulating layer covering the second conductor layer. The first insulating layer has first openings such that the first openings are exposing first conductor pads including portions of the first conductor layer, the second insulating layer has second openings such that the second openings are exposing second conductor pads including portions of the second conductor layer, each of the first conductor pads has a first plating layer recessed with respect to outer surface of the first insulating layer, and each of the second conductor pads has a second plating layer formed flush with outer surface of the second insulating layer or having bump shape protruding from the outer surface of the second insulating layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is based upon and claims the benefit of priority to Japanese Patent Application No. 2014-144674, filed Jul. 15, 2014, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to a wiring substrate in which an opening that exposes a portion of a conductor layer as a conductor pad is formed in a solder resist layer that covers an outer side of the conductor layer, and relates to a method for manufacturing the wiring substrate.

Description of Background Art

In a wiring substrate, an electroless plating layer may be formed on a conductor pad, and a solder bump that protrudes from a solder resist layer to an outer side may be formed on the electroless plating layer (for example, see Re-publication of PCT International Publication No. 2007-129545). The entire contents of this publication are incorporated herein by reference.

SUMMARY OF THE INVENTION

According to one aspect of the present invention, a wiring substrate includes a first outermost conductor layer, a first outermost insulating layer formed on the first outermost conductor layer such that the first outermost insulating layer is covering the first outermost conductor layer, a second outermost conductor layer formed on the opposite side of the first outermost conductor layer, and a second outermost insulating layer formed on the second outermost conductor layer such that the second outermost insulating layer is covering the second outermost conductor layer. The first outermost insulating layer has first openings such that the first openings are exposing first conductor pads including portions of the first outermost conductor layer, respectively, the second outermost insulating layer has second openings such that the second openings are exposing second conductor pads including portions of the second outermost conductor layer, respectively, each of the first conductor pads has a first plating layer recessed with respect to an outer surface of the first outermost insulating layer, and each of the second conductor pads has a second plating layer formed flush with an outer surface of the second outermost insulating layer or having a bump shape protruding from the outer surface of the second outermost insulating layer.

According to one aspect of the present invention, a method for manufacturing a wiring substrate includes forming a first outermost insulating layer on a first outermost conductor layer such that the first outermost insulating layer covers the first outermost conductor layer, forming a second outermost insulating layer on a second outermost conductor layer on the opposite side of the first outermost conductor layer such that the second outermost insulating layer covers the second outermost conductor layer, forming first openings in the first outermost insulating layer such that the first openings expose first conductor pads including portions of the first outermost conductor layer, respectively, forming second openings in the second outermost insulating layer such that the second openings expose second conductor pads including portions of the second outermost conductor layer, respectively, forming a first plating layer on each of the first conductor pads such that the first plating layer is recessed with respect to an outer surface of the first outermost insulating layer, and forming a second plating layer on each of the second conductor pads such that the second plating layer is formed flush with an outer surface of the second outermost insulating layer or has a bump shape protruding from the outer surface of the second outermost insulating layer.

DETAILED DESCRIPTION OF THE EMBODIMENTS

In the following, an embodiment of the present invention is described based onFIG. 1-15. As illustrated inFIG. 1, a wiring substrate100according to the present embodiment is a wiring substrate with a built-in electronic component, having a built-in interposer80as the electronic component. The wiring substrate100has a structure in which an outer side build-up insulating layer21and an outer side build-up conductor layer22are laminated on each of both front and back surfaces of a wiring board10with a cavity (the interposer80being accommodated in the cavity30) (seeFIG. 3), and the outer side build-up conductor layers22are respectively covered by the first solder resist layer (29B) and the second solder resist layer (29F). The first solder resist layer (29B) forms a B surface (100B), which is a back side surface of the wiring substrate100. The second solder resist layer (29F) forms an F surface (100F), which is a back side surface of the wiring substrate100. The solder resist layers (29F,29B) each have a thickness of about 10-20 μm. The outer side build-up insulating layer21has a thickness of about 15 μm. The outer side build-up layer22has a thickness of about 15 μm.

As illustrated inFIG. 3, the wiring board10with the cavity has a multilayer structure in which build-up insulating layers15and build-up conductor layers16are alternately laminated on each of both an F surface (11F), which is a front side surface of a core substrate11, and a B surface (11B), which is a back side surface of the core substrate11.

The core substrate11has a thickness of about 700 μm. A core conductor layer12is formed on each of both the front and back surfaces of the core substrate11. The core conductor layer12has a thickness of about 35 μm. The build-up insulating layers15are each formed of an insulating material and each have a thickness of about 25-30 μm. The build-up conductor layers16are each formed of metal (such as copper) and each have a thickness of about 15 μm.

The front side core conductor layer12and the back side core conductor layer12are connected by a through-hole conductor13that penetrates through the core substrate11. The through-hole conductor13is formed by forming, for example, copper plating on a wall surface of a through hole (13A) that penetrates through the core substrate11.

An innermost build-up conductor layer16, which is closest to the core substrate11, and the core conductor layer12are connected by a via17that penetrates through an innermost build-up insulating layer15. Further, build-up conductor layers (16,16) that are adjacent to each other in a lamination direction are connected by a via18that penetrates through a build-up insulating layer15that is positioned between the build-up conductor layers (16,16).

A conductor circuit layer (31B) and a plane layer (31A) are formed in a second build-up conductor layer (16B) that is among the build-up conductor layers16laminated on the F surface (11F) side of the core substrate11and is positioned second from an outer side. The plane layer (31A) is formed, for example, in a solid shape as an independent conductor layer or as a ground layer that is grounded.

An outer side conductor circuit layer35is formed that is connected via the via18to the conductor circuit layer (31B) in the second build-up conductor layer (16B) that is among the build-up conductor layers16laminated on the F surface (11F) side of the core substrate11and is positioned second from the outer side. Further, a protective layer34is laminated on a second build-up conductor layer (16A). The protective layer34is formed of the same material as the build-up insulating layers15. The protective layer34has a thickness of about 15 μm and is thinner than each of the build-up insulating layers15. The protective layers34respectively form an F surface (10F), which is a front side surface of the wiring board10with the cavity, and a B surface (10B), which is a back side surface of the wiring board10with the cavity.

The cavity30having an opening30A on the F surface (10F) of the wiring board10is formed in the wiring board10with the cavity. The cavity30penetrates through a first build-up insulating layer (15A) positioned on an outermost side and the protective layer34, and exposes the plane layer (31A) as a bottom surface.

As illustrated inFIG. 4, an area of the opening (30A) of the cavity30is smaller than an area of the plane layer (31A), and an outer peripheral portion of the plane layer (31A) protrudes to outer side of the cavity30. In other words, the plane layer (31A) forms the entire bottom surface of the cavity30. Further, a recess32is formed in an outer peripheral portion of the portion of the plane layer (31A) that is exposed as the bottom surface of the cavity30. The recess32has a depth of about 0.5-3 μm. A roughened layer36is formed on a surface of the portion of the plane layer (31A) that is exposed as the bottom surface of the cavity30.

As illustrated inFIG. 1, electronic component mounting regions (R1, R2) for mounting electronic components (90,91) including a semiconductor element and the like are formed on the F surface (100F) of the wiring substrate100. The cavity30is arranged on an inner side of a boundary portion of the electronic component mounting regions (R1, R2). The interposer80that electrically connects the electronic components (90,91) mounted in the electronic component mounting regions (R1, R2) is accommodated in the cavity30. The electronic component90is, for example, an MPU or a CPU, and the electronic component91is, for example, a memory.

Specifically, as illustrated inFIG. 2, a bonding layer33is formed on the plane layer (31A) that is exposed as the bottom surface of the cavity30, and the interposer80is mounted on the bonding layer33. Here, due to the recess32of the plane layer (31A), an anchor effect is exerted on the bonding layer33, and peeling of the bonding layer33from the plane layer (31A) is suppressed. In addition, due to the roughened layer36that is formed on the surface of the plane layer (31A) that is exposed as the bottom surface of the cavity30, peeling of the bonding layer33from the plane layer (31A) is further suppressed.

As illustrated inFIG. 1, first openings28that each expose a portion of the outer side build-up conductor layer22as a first conductor pad24are formed in the first solder resist layer (29B) that forms the B surface (100B) of the wiring substrate100. The first conductor pads24are each connected to the first build-up conductor layer (16A) via a first via26that penetrates through the outer side build-up insulating layer21.

First plating layers42are respectively formed on the first conductor pads24. The first plating layers42are each recessed with respect to an outer surface of the first solder resist layer (29B). As illustrated inFIG. 5B, the first plating layers42are each formed by electroless Ni/Pd/Au metal layers. Of the electroless Ni/Pd/Au metal layers of each of the first plating layers42, the Ni layer (42L) has a thickness of 3-10 μm; the Pd layer (42M) has a thickness of 0-1 μm; and the Au layer (42N) has a thickness of 0.03-0.1 μm. The first plating layers42each have an outer diameter of 80-150 μm. Among the first plating layers42, a distance (pitch) between adjacent first plating layers (42,42) is 150-300 μm. The thickness of the Pd layer (42M) may be 0 μm. In this case, the first plating layers42are each formed by the electroless Ni/Au metal layers.

As illustrated inFIG. 1, second openings27that each expose a portion of the outer side build-up conductor layer22as a second conductor pad23are formed in the second solder resist layer (29F) that forms the F surface (100F) of the wiring substrate100. Specifically, the second openings27include second small-diameter openings (27A) and second large-diameter openings (27B). The second small-diameter openings (27A) each expose a portion of the outer side build-up conductor layer22as a second small-diameter conductor pad (23A). The second large-diameter openings (27B) each expose a portion of the outer side build-up conductor layer22as a second large-diameter conductor pad (23B). As illustrated inFIG. 2, the second large-diameter conductor pad (23B) is connected to the first build-up layer (16A) via a second large-diameter via (25B) that penetrates through the outer side build-up insulating layer21and the bonding layer34. Further, the second small-diameter conductor pad (23A) is connected to the interposer80via a second small-diameter via (25A) that penetrates through the outer side build-up insulating layer21.

Second plating layers41are respectively formed on the second small-diameter conductor pads (23A) and the second large-diameter conductor pads (23B). The second plating layers41each protrude in a bump-like shape to an outer side of the second solder resist layer (29F), and an amount of the protrusion of the second plating layer41from an outer surface of the second solder resist layer (29F) is 0-15 μm. Further, the amount of the protrusion from the outer surface of the second solder resist layer (29F) is substantially the same among the second plating layers41. As illustrated inFIG. 5A, similar to the first plating layers42. the second plating layers41are each formed by electroless Ni/Pd/Au metal layers. Of the electroless Ni/Pd/Au metal layers of each the second plating layers41, the Ni layer (41L) has a thickness of 10-35 μm; the Pd layer (41M) has a thickness of 0.1-1 μm; and the Au layer (41N) has a thickness of 0.03-0.1 μm. The second plating layers41on the second small-diameter conductor pads (25A) respectively penetrate through the second small-diameter openings (27A), and the second plating layers41on the second large-diameter conductor pads (25B) respectively penetrate through the second large-diameter openings (27B). Here, when the second plating layers41that penetrate through the second small-diameter openings (27A) and the second plating layers41that penetrate through the second large-diameter openings (27B) are respectively referred to as second small-diameter plating layers (41A) and second large-diameter plating layers (41B) to be distinguished from each other, the second small-diameter plating layers (41A) each have an outer diameter of 20-30 μm, and a distance (pitch) between adjacent second small-diameter plating layers (41A,41A) among the second small-diameter plating layers (41A) is 40-60 μm. Further, the second large-diameter plating layers (41B) each have an outer diameter of 50-90 μm, and a distance (pitch) between adjacent second large-diameter plating layers (41B,41B) among the second large-diameter plating layers (41B) is 90-180 μm.

In the present embodiment, the first solder resist layer (29B) and the second solder resist layer (29F) respectively correspond to a “first insulating layer” and a “second insulating layer” according to an embodiment of the present invention. Further, the outer side build-up conductor layer22on the B surface (100B) side that is covered by the first solder resist layer (29B) correspond to a “first conductor layer” according to an embodiment of the present invention, and the outer side build-up conductor layer22on the F surface (100F) side that is covered by the second solder resist layer (29F) corresponds to a “second conductor layer” according to an embodiment of the present invention.

The description about the structure of the wiring substrate100is as given above. Next, a method for manufacturing the wiring substrate100is described. Here, since the wiring substrate100is manufactured using the wiring board10with the cavity, in the following, first, a method for manufacturing the wiring board10with the cavity is described.

The wiring board10with the cavity is manufactured as follows.

(1) As illustrated inFIG. 6A, the through hole (13A) is formed in the core substrate11by, for example, drilling or the like. The core substrate11is obtained by laminating a copper foil (not illustrated in the drawings) on each of both an F surface (11F), which is a front side surface of an insulating base material (11K), and a B surface (11B), which is a back side surface of the insulating base material (11K), the insulating base material (11K) being made of epoxy resin or BT (bismaleimide triazine) resin and a reinforcing material such as a glass cloth.

(2) By an electroless plating treatment, a plating resist treatment and an electrolytic plating treatment, the core conductor layer12is formed on each of the F surface (11F) and the B surface (11B) of the core substrate11, and the through-hole conductor13is formed on an inner surface of the through hole (13A) (seeFIG. 6B).

(3) As illustrated inFIG. 7A, a build-up insulating layer15is laminated on the core conductor layer12, and a build-up conductor layer16is laminated on the build-up insulating layer15. Specifically, a prepreg (a resin sheet of a B-stage formed by impregnating a core material with resin) as a build-up insulating layer15and a copper foil (not illustrated in the drawings) are laminated on the core conductor layer12on each of the F surface (11F) side and the B surface (11B) side of the core substrate11. Then, the resulting substrate is hot-pressed. Then, CO2 laser is irradiated to the copper foil, and a via formation hole that penetrates through the copper foil and the build-up insulating layer15is formed. Then, an electroless plating treatment, a plating resist treatment and an electrolytic plating treatment are performed. The via formation hole is filled with electrolytic plating and a via17is formed, and a build-up conductor layer16of a predetermined pattern is formed on the build-up insulating layer15. Instead of the prepreg, it is also possible to use a resin film that does not contain a core material as the build-up insulating layer15. In this case, without laminating a copper foil, a conductor layer can be directly formed on a surface of the resin film using a semi-additive method.

(4) Similar to the process ofFIG. 7A, build-up insulating layers15and build-up conductor layers16are alternately laminated on each of the F surface (11F) side and the B surface (11B) side of the core substrate11(seeFIG. 7B; inFIG. 7B, only the F surface (11F) side is illustrated; this applies also inFIGS. 8A, 8B, 9A and 9Bin the following). In this case, a via18that penetrates through a build-up insulating layer15is formed, and build-up insulating layers16,16that are adjacent to each other in the lamination direction are connected by the via18.

(5) As illustrated inFIG. 8A, a build-up insulating layer15is laminated and a build-up conductor layer16is laminated on the build-up insulating layer15, and the second build-up conductor layer (16B) is formed. In this case, the conductor circuit layer (31B), which is connected to an inner side build-up conductor layer16via a via18, and the solid-shaped plane layer (31A) are formed in the second build-up conductor layer (16B).

(6) As illustrated inFIG. 8B, on the second build-up conductor layer (16B), a build-up insulating layer15and a build-up conductor layer16are laminated, and the first build-up insulating layer (15A) and the first build-up conductor layer (16A) are formed. In this case, on the plane layer (31A), only the first build-up insulating layer (15A) is laminated. Further, in the first build-up conductor layer (16A), the outer side conductor circuit layer35is formed that is connected to the conductor circuit layer (31B) via a via18that penetrates through the first build-up insulating layer (15A).

(7) As illustrated inFIG. 9A, on the build-up conductor layer16, the protective layer34made of the same material as the build-up insulating layer15is laminated. In this case, on the plane layer (31A), the build-up layer15and the protective layer34are laminated.

(8) As illustrated inFIG. 9B, by irradiating, for example, CO2 laser from the F surface (11F) side of the core substrate11, the cavity30is formed that penetrates through the protective layer34and the first build-up insulating layer (15A) to expose the plane layer (31A) as a bottom surface. Here, an area of a range in which laser is irradiated, that is, an opening area of the cavity30, is smaller than an area of the plane layer (31A), so that the entire bottom surface of the cavity30is formed by the plane layer (31A) alone. Further, by strongly irradiating laser to the outer peripheral portion of the cavity30, the recess32is formed in the outer peripheral portion of the portion of the plane layer (31A) that is exposed as the bottom surface of the cavity30.

(9) The plane layer (31A) that is exposed as the bottom surface of the cavity30is subjected to a desmear treatment, and the roughened layer36is formed on the surface of the plane layer (31A) by a roughening treatment. When the desmear treatment is performed, the conductor circuit layer (31B) that is contained in the second build-up conductor layer (16B) is protected by the protective layer34. As a result, the wiring board10with the cavity illustrated inFIG. 3is completed.

The above is the description of the method for manufacturing the wiring board10with the cavity. Next, the method for manufacturing the wiring substrate100using the wiring board10with the cavity is described.

The wiring substrate100is manufactured as follows.

(1) As illustrated inFIG. 10A, the bonding layer33is laminated on the plane layer (31A) that is exposed as the bottom surface of the cavity30, and the interposer80is placed on the bonding layer33, and a thermal curing process and a CZ process are performed.

(2) The outer side build-up insulating layer21made of the same material as the build-up insulating layers15is laminated on each of the F surface (10F) and the B surface (10B) of the wiring board10with the cavity (seeFIG. 10B; inFIG. 10B, only the F surface (10F) side is illustrated; this applies also toFIGS. 11A and 11B).

(3) A second small-diameter via formation hole (45A) and a second large-diameter via formation hole (45B) are formed in the outer side build-up insulating layer21by irradiating laser from the F surface (10F) side of the wiring board10with the cavity (seeFIG. 11A), and a first via formation hole46is formed by irradiating laser from the B surface (10B) side of the wiring board10. In doing so, on the B surface (10B) side, for example, by irradiating infrared laser, the first via formation hole46having a relatively large diameter is formed (seeFIG. 5B). Further, on the F surface (10F) side, for example, by irradiating infrared laser, the second large-diameter via formation hole (45B) having a diameter smaller than that of the first via formation hole46is formed, and, for example, by irradiating visible or ultraviolet laser, the second small-diameter via formation hole (45A) having a diameter smaller than that of the second large-diameter via formation hole (45B) is formed. The first via formation hole46has an opening diameter of about 150 μm; the second large-diameter via formation hole (45B) has an opening diameter of about 50-60 μm; and the second small-diameter via formation hole (45A) has an opening diameter of about 20-30 μm.

(4) An electroless plating treatment, a plating resist treatment and an electrolytic plating treatment are performed. On the F surface (10F) side of the wiring board10with the cavity, the second small-diameter via (25A) and the second large-diameter via (25B) are respectively formed in the second small-diameter via formation hole (45A) and the second large-diameter via formation hole (45B) (seeFIG. 11B); and on the B surface (10B) side of the wiring board10with the cavity, the first via26is formed in the first via formation hole46. Further, the outer side build-up conductor layer22is formed on the outer side build-up insulating layer21.

(5) As illustrated inFIG. 12, the first solder resist layer (29B) and the second solder resist layer (29F) are respectively laminated on the outer side build-up conductors layer22on the F surface (10F) side and the B surface (10B) side of the wiring board10with the cavity; and, by a lithographic treatment, the second large-diameter openings (27B) that each expose a portion of the outer side build-up conductor layer22as a second large-diameter conductor pad (23B) are formed in the second solder resist layer (29F) on the F surface (10F) side of the wiring board10with the cavity, and second openings28that each expose a portion of the outer side build-up conductor layer22as a second conductor pad24are formed in the first solder resist layer (29B) on the B surface (10B) side.

(6) As illustrated inFIG. 13, by irradiating visible or ultraviolet laser from the F surface (10F) side of the wiring board10with the cavity, the second small-diameter openings (27A) that each expose a portion of the outer side build-up conductor layer22as a second small-diameter conductor pad (23A) are formed.

(7) As illustrated inFIG. 14, the second solder resist layer (29F) on the F surface (10F) side of the wiring board10with the cavity is covered by a resin protective film43. Then, the B surface (10B) side of the wiring board10with the cavity is subjected to an electroless plating treatment, and the first plating layers42are respectively formed on the second conductor pads24. Specifically, first, the substrate on which the first solder resist layer (29B) and the second solder resist layer (29F) are formed is immersed in an electroless nickel plating solution for a predetermined period of time, and the Ni layer (42L) is formed. Next, the substrate is immersed in an electroless palladium plating solution for a predetermined period of time, and the Pd layer (42M) is formed. Further, the substrate is immersed in an electroless gold plating solution for a predetermined period of time, and the Au layer (42N) is formed. When the electroless plating treatment is performed, the second small-diameter conductor pads (23A) and the second large-diameter conductor pads (23B) are protected by the resin protective film43.

(8) As illustrated inFIG. 15, the resin protective layer43on the F surface (10F) side of the wiring board10with the cavity is removed, and the first solder resist layer (29B) on the B surface (10B) side of the wiring board10with the cavity is covered by a resin protective film43. Then, similar to the process ofFIG. 14, the F surface (10F) side of the wiring board10with the cavity is subjected to an electroless plating treatment, the second plating layers41are respectively formed on the second small-diameter conductor pads (23A) and the second large-diameter conductor pads (23B). In doing so, the first plating layer42is protected by the resin protective film43.

(9) The resin protective layer43that covers the first solder resist layer (29B) on the B surface (10B) side of the wiring board10is removed, and the wiring board100with the built-in electronic component illustrated inFIG. 1is completed.

The description about the structure and the manufacturing method of the wiring substrate100of the present embodiment is as given above. Next, an operation effect of the wiring substrate100is described.

According to the wiring substrate100of the present embodiment, the second plating layers41that are respectively formed on the second conductor pads23each protrude in a bump-like shape from the outer surface of the second solder resist layer (29F). Therefore, when the surface on the second solder resist layer (29F) is used as a mounting surface of the electronic components (90,91) including a semiconductor element and the like, there is no need to form solder bumps as in a conventional wiring substrate, and improvement in yield can be achieved. Further, the first plating layers42are each recessed from the outer surface of the first solder resist layer (29B). Therefore, by overlaying the wiring substrate100with the surface on the first solder resist layer (29B) side facing downward on a circuit substrate having solder bumps on an upper surface thereof, the wiring substrate100can be mounted on the circuit substrate.

Further, in the wiring substrate100, both the first plating layers42and the second plating layers41are each formed by the electroless Ni/Pd/Au metal layers. Therefore, the first plating layers42and the second plating layers41can be formed by the same electroless plating treatment. Further, the second openings27(the second small-diameter openings (27A) and the second large-diameter openings (27B)) each have an opening diameter smaller than that of the first openings28. Therefore, a time period it takes for the second plating layers41to protrude to the outer side of the second solder resist layer (29F) can be shortened, and it becomes easy for the first plating layers42to be recessed with respect to the outer surface of the first solder resist layer (29B).

Further, in the wiring substrate100of the present embodiment, the second plating layers41are arranged in the electronic component mounting regions (R1, R2) of the F surface (100F). Therefore, due to the second plating layers41, the electronic components (90,91) can be connected to conductor circuit layers in the wiring substrate100. In addition, the wiring substrate100has the built-in interposer80the electrically connects the electronic components (90,91). Therefore, by narrowing spacing between the electronic components (90,91), an electronic circuit apparatus in which the electronic components (90,91) are mounted on the wiring substrate100can be made compact.

Other Embodiments

The present invention is not limited to the above-described embodiment. For example, embodiments described below are also included in the technical scope of the present invention. Further, in addition to the embodiments described below, the present invention can also be embodied in various modified forms within the scope without departing from the spirit of the present invention.

(1) In the above embodiment, the wiring substrate100is a wiring substrate with a built-in electronic component. However, as long as the wiring substrate100has a structure that has openings that expose portions of conductor layers on both front and back surfaces as conductor pads, it is also possible that the wiring substrate100is a wiring substrate that does not have a built-in electronic component.

(2) In the above embodiment, the wiring substrate100may also be a coreless substrate that does not have the core substrate11.

(3) As illustrated inFIG. 16, it is also possible that the second plating layers41are flush with the outer surface of the second solder resist layer (29F).

(4) In the above embodiment, in the second plating layers41, two kinds of the second plating layers41(the second small-diameter plating layer (41A) and the second large-diameter plating layer (41B)) having different sizes (diameters) are provided. However, it is also possible that only one kind of the second plating layers41is provided, or three or more kinds of the second plating layers41having different sizes are provided.

(5) In the above embodiment, it is also possible that the second small-diameter openings (27A) and the second large-diameter openings (27B) have the same size. Further, it is also possible that the second openings27(the second small-diameter openings (27A) and the second large-diameter openings (27B)) and the first openings28have the same size.

In a wiring substrate, there may be a problem that the formation of the solder bump requires time and effort, causing reduction in yield.

A wiring substrate according to an embodiment of the present invention allows yield to be increased, and another embodiment of the present invention is a method for manufacturing such a wiring substrate.

A wiring substrate according to an embodiment of the present invention includes: a first insulating layer that forms one of a front surface and a back surface; a first conductor layer of which an outer side is covered by the first insulating layer; first openings that are formed in the first insulating layer and each expose a portion of the first conductor layer as a first conductor pad; a second insulating layer that forms the other one of the front surface and the back surface; a second conductor layer of which an outer side is covered by the second insulating layer; and second openings that are formed in the second insulating layer and each expose a portion of the second conductor layer as a second conductor pad. A first plating layer that is recessed with respect to an outer surface of the first insulating layer is formed on the first conductor pad, and a second plating layer that is flush with an outer surface of the second insulating layer or protrudes in a bump-like shape from the outer surface of the second insulating layer is formed on the second conductor pad.