Liquid crystal display array and liquid crystal display panel

A liquid crystal display array. The liquid crystal display array has a plurality of gate lines, a plurality of source lines and a plurality of cells. Each gate line comprises a first portion and a second portion extended from the first portion. Each cell corresponds to the interlaced data line and scan line and has a first storage capacitor. A first electrode of the first storage capacitor corresponding to a first gate line of the gate lines is coupled to the first portion or the second portion of any gate line except the first gate line.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a liquid crystal display array in which one electrode of a storage capacitor within each cell is coupled to a first portion or a second portion of one gate line, thus reducing gate line delay time.

2. Description of the Related Art

A conventional thin film transistor liquid crystal display (TFT-LCD) generally comprises driving circuits and an array of cells driven thereby. The driving circuits drive a plurality of gate lines formed in parallel and a plurality of source lines formed orthogonal to the gate lines. Each cell, disposed near an intersection of one of the gate lines and one of the source lines, includes a thin film transistor (TFT) and a storage capacitor. The TFT further includes a gate coupled to a corresponding gate line and a source coupled to a corresponding source line. According to the different structures of storage capacitors, TFT-LCD arrays can be divided into two types, Cs-on-gate type and Cs-on-common type. In a Cs-on-gate array, a storage capacitor is formed between a source of a corresponding TFT and a previous gate line, that is, the reference voltage of the storage capacitor is the potential of the previous gate line. In a Cs-on-common array, a storage capacitor is formed between a source of a corresponding TFT and a common electrode, that is, the reference voltage of the storage capacitor is the potential of the common electrode.

FIG. 1is a schematic diagram of a conventional Cs-on-common array of a TFT-LCD. The array1is formed by a plurality of gate lines G1nto G1n-2and a plurality of source line D1mand D1m-1. The interlaced gate line and source line correspond to one cell, for example, the interlaced gate line G1n-1and source line D1m-1correspond to a cell100. The cell100includes a TFT10, a liquid capacitor Clc10, and a storage capacitor Cs10. Referring toFIG. 1, a gate of the TFT10is coupled to the gate line G1n-1, a source thereof is coupled to a pixel electrode11, and a drain thereof is coupled to the source line D1m-. The storage capacitor Cs10is formed between the pixel electrode11and a common electrode Vcom10. Each storage capacitor within the cells on the same row is coupled between a pixel electrode thereof and the common electrode.

FIG. 2is a schematic diagram of a conventional Cs-on-gate array of a TFT-LCD. The array2is formed by a plurality of gate lines G2nto G2n-2and a plurality of source lines D2mand D2m-1. The interlaced gate line and source line correspond to one cell, for example, the interlaced gate line G2n-1and source line D2m-1correspond to a cell200. The cell200includes a TFT20, a liquid capacitor Clc20, and a storage capacitor Cs20. Referring toFIG. 2, a gate of the TFT10is coupled to the gate line G2n-1, a source thereof is coupled to a pixel electrode21, and a drain thereof is coupled to the source line D2m-1. The storage capacitor Cs20is formed between the pixel electrode21and the gate line G2n-2. In cells on the same row, all the TFTs are coupled to the same gate line, and each storage capacitor is coupled between a pixel electrode thereof and the previous gate line.

As described above, the Cs-on-common array has an extra common electrode line, thus reducing the aperture ratio. Due to low brightness of the TFT-LCD caused by the low aperture ratio, the Cs-on-common type TFT-LCD array is less used. The Cs-on-gate type TFT-LCD array is commonly used instead. When each gate line is coupled to a plurality of storage capacitors in the Cs-on-gate array, RC effect, induced by the gate lines and the storage capacitors, causes increased in gate line delay time and degrades the capability of TFTs to charge the pixel electrodes.

SUMMARY OF THE INVENTION

Accordingly, an object of the present invention is to provide a array for a liquid crystal display panel that ameliorates disadvantages of the related art.

According to the above described object, the present invention provides a liquid crystal display array comprising a plurality of gate lines, a plurality of source lines, and a plurality of cells. Each gate line comprises a first portion and a second portion extended from the first portion. Each cell corresponds to the interlaced gate line and source line and comprises a first storage capacitor. A first electrode of the first storage capacitor corresponding to a first gate line is coupled to the first portion or the second portion of any gate line expect the first gate line.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 3is one array of a TFT-LCD of the present invention. The array3is formed by a plurality of gate lines G3nto G3n-2and a plurality of source lines D3mand D3m-1, which are driven by a gate driver and a source driver (not shown). Sub gate lines G′3nto G′3n-2extend from the gate lines G3nto G3n-2. The interlaced gate line and source line correspond to one cell comprising a TFT, a liquid capacitor, and a storage capacitor. Each gate line and the corresponding sub gate line carry the same signal.

As shown inFIG. 3, the gate line G3nand the source line D3m-1correspond to a cell300. The cell300comprises a TFT30, a crystal capacitor Clc30, and a storage capacitor Cs30. A gate of the TFT30is coupled to the gate line G3n, a drain thereof is coupled to the source line D3m-1. A source of the TFT30, a first electrode of the crystal capacitor Clc30, and a first electrode of the storage capacitor Cs30are coupled to a pixel electrode31. A second electrode of the crystal capacitor Clc30is coupled to a common electrode Vcom30. A second electrode of the storage capacitor Cs30is coupled to the sub gate line G′3n-2.

In the embodiment of the present invention, each gate line comprises one sub gate line. The first electrode of the storage capacitor within any cell is coupled to a pixel electrode thereof, and the second electrode thereof is coupled to the sub gate line of any gate line except the corresponding gate line. That is, each gate line is coupled to the gates of the TFTs within the cells on the corresponding row, and each sub gate line is coupled to the second electrodes of the storage capacitors within the cells on any row. Because the gate lines are not coupled to any storage capacitor, gate line delay time is decreased, and the TFTs are capable of providing increased charge.

FIG. 4is another array of the TFT-LCD of the present invention. The array4is formed by a plurality of gate lines G4nto G4n-2and a plurality of source lines D4mand D4m-1, which are driven by a gate driver and a source driver (not shown). Sub gate lines G′3nto G′3n-2extend from the gate lines G3nto G3n-2. The interlaced gate line and source line correspond to one cell comprising a TFT, a liquid capacitor, and a storage capacitor. Each gate line and the corresponding sub gate line carry the same signal.

As shown inFIG. 4, the gate line G4nand the source line D4m-1correspond to a cell400. The cell400includes a TFT40, a crystal capacitor Clc40, and storage capacitors Cs40and Cs41. A gate of the TFT40is coupled to the gate line G4n, a drain thereof is coupled to the source line D4m-1. A source of the TFT40, a first electrode of the crystal capacitor Clc40, and first electrodes of the storage capacitors Cs40and Cs41are coupled to a pixel electrode41. A second electrode of the crystal capacitor Clc40is coupled to a common electrode Vcom40. A second electrode of the storage capacitor Cs40is coupled to the sub gate line G′4n-2, and a second electrode of the storage capacitor Cs41is coupled to the gate line G4n-1.

According to the array4, RC effect resulting from the gate lines and the storage capacitors degrades, thus reducing gate line delay time increasing ability of TFTs to charge the pixel electrodes. It is assumed that the TFTs within the array2are the same as the TFTs within the array4, and the arrays2and4work at the same operating voltage. The values of the storage capacitors Cs40and Cs41are less than that of the storage capacitors Cs20. Although the second electrode of the storage capacitor Cs41is coupled to the gate line G4n-1, delay time of the gate line G4n-1decreases due to less capacitance induced by the RC effect.

FIG. 5is a operation timing chart of the arrays2and4. It is assumed that all TFTs within the arrays2and4are the same, and total capacitance and resistance of the array2are equal to those of the array4. A level of a signal V(5) on the gate line G4nrises faster than a level of a signal V(4) on the gate line G2n. Thus a level of a voltage signal V(8) of the pixel electrode41rises faster than a level of a voltage signal V(6) of the pixel electrode21. The ability of the TFTs to charge is improved.

In the embodiments of the present invention, any number of storage capacitors can be provided according to requirements, without limitation.

While several embodiments of the invention have been described by way of example, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended that various modifications and similar arrangements (as would be apparent to those skilled in the art) be covered.