Solid state drive

A memory stores data, a memory interface circuit reads the data from the memory, and an arithmetic circuit performs a prescribed arithmetic operation on the data. A host interface circuit outputs an arithmetic request to the arithmetic circuit, and also outputs a reading instruction to the memory via the memory interface circuit, upon receipt of an arithmetic instruction from a host device. The host interface circuit receives, from the arithmetic circuit, an arithmetic result of the prescribed arithmetic operation performed on the data read from the memory via the memory interface circuit, and outputs the arithmetic result to the host device.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2016-133603, filed on Jul. 5, 2016, the entire contents of which are incorporated herein by reference.

FIELD

The embodiments discussed herein are related to a solid state drive (SSD).

BACKGROUND

In recent years, near-data processing has been proposed in which, in an information processing device, an arithmetic circuit is provided near data to perform an arithmetic operation instead of moving data from a storage to a central processing unit (CPU) to perform an arithmetic operation.

FIG. 1Aillustrates an example of an arithmetic operation in a CPU, andFIG. 1Billustrates an example of near-data processing. In a case in which a CPU101performs an arithmetic operation, the CPU101reads data from a storage102, and performs an arithmetic operation by using the read data, as illustrated inFIG. 1A. As the storage102, a storage such as a hard disk drive (HDD) or an SSD is used. The SSD is a storage using a semiconductor memory.

In contrast, in near-data processing, an arithmetic function moves from the CPU101to the storage102, as illustrated inFIG. 1B. In this case, the CPU101outputs an arithmetic instruction to the storage102, and an arithmetic circuit provided in the storage102performs an arithmetic operation on data.

In the near-data processing above, a cost of data movement is reduced, and high-performance power-saving arithmetic processing can be expected. Therefore, the study have become active such that a workshop dedicated to near-data processing is held, for example.

FIG. 2illustrates an exemplary configuration of a conventional SSD that performs near-data processing (see, for example, Non-Patent Document 1). An SSD201ofFIG. 2includes a flash memory controller211, and a flash memory212-1to a flash memory212-4. As the flash memory212-1to the flash memory212-4, a NAND flash memory that is a non-volatile memory is used, for example.

The flash memory controller211includes a host interface circuit (a host IF circuit)221, a dynamic random access memory (DRAM)222, and a processor223. The flash memory controller211further includes a flash memory interface circuit (a flash memory IF circuit)224-1and a flash memory IF circuit224-2. The flash memory IF circuit224-1is connected to the flash memory212-1and the flash memory212-2, and the flash memory IF circuit224-2is connected to the flash memory212-3and the flash memory212-4.

Hereinafter, any of the flash memory212-1to the flash memory212-4may be referred to as a flash memory212. In addition, any of the flash memory IF circuit224-1and the flash memory IF circuit224-2may be referred to as a flash memory IF circuit224. Each of the flash memories212is referred to as a chip, and a transmission line between the flash memory IF circuit224and the flash memory212is referred to as a channel. Accordingly, the number of chips in the SSD201indicates the number of flash memories212, and the number of channels indicates the number of flash memory IF circuits224.

An erasure unit of data in each of the flash memories212is referred to as a block, and a reading/writing unit of data is referred to as a page. The size of one block is, for example, several megabytes, and the size of one page is, for example, several kilobytes to more than ten kilobytes.

The flash memory IF circuit224-1performs error correction on data read from the flash memory212-1and the flash memory212-2. The flash memory IF circuit224-2performs error correction on data read from the flash memory212-3and the flash memory212-4.

The processor223levels the number of times of rewriting by performing wear leveling for exchanging a block for which the number of times of rewriting is large and a block for which the number of times of rewriting is small. In addition, the processor223performs garbage collection for releasing an unneeded page in a block, by using the DRAM222.

In general, physical information, such as the number of chips, the number of channels, the size of a block, or the size of a page, of the SSD201is hidden from a host device such as a CPU.

Upon receipt of an arithmetic instruction from a host device (not illustrated), the host IF circuit221outputs the received arithmetic instruction to the processor223. The processor223reads data from the flash memory212, stores the data in the DRAM222, and performs an arithmetic operation by using the data. The processor223stores an arithmetic result in a main storage (not illustrated) via the host IF circuit221.

A configuration in which data search is performed within a flash memory device is also known (see, for example, Patent Document 1).Patent Document 1: Japanese Laid-open Patent Publication No. 2003-203486Non-Patent Document 1: Jaeyoung Do et al., “Query Processing on Smart SSDs: Opportunities and Challenges,” SIGMOD'13, pages 1221-1230, 2013.

SUMMARY

According to an aspect of the embodiments, a solid state drive includes a memory that stores data, a memory interface circuit that reads the data from the memory, an arithmetic circuit that performs a prescribed arithmetic operation on the data, and a host interface circuit.

The host interface circuit outputs an arithmetic request to the arithmetic circuit, and also outputs a reading instruction to the memory via the memory interface circuit, upon receipt of an arithmetic instruction from a host device. The host interface circuit receives, from the arithmetic circuit, an arithmetic result of the prescribed arithmetic operation performed on the data read from the memory via the memory interface circuit, and outputs the arithmetic result to the host device.

DESCRIPTION OF EMBODIMENTS

Embodiments are described below in detail with reference to the drawings.

In a case in which the SSD201ofFIG. 2is used, a host device indirectly controls the flash memories212via the processor223instead of directly controlling the flash memories212. Therefore, physical information of the SSD201is hidden from the host device, and it is difficult for the host device to optimize data arrangement of the flash memory212-1to the flash memory212-4. Further, in performing near-data processing, the flash memory controller211temporarily stores data read from the flash memory212in the DRAM222, and performs near-data processing. Accordingly, near-data processing is performed at low speed.

The problems above do not arise only in an SSD using a flash memory, but also arise in an SSD using another semiconductor memory.

FIG. 3illustrates an exemplary configuration of a software-defined SSD that can directly control a flash memory by using software. A host device301ofFIG. 3executes an application311or a library312, and an SSD302includes a flash memory controller321and a flash memory322-1to a flash memory322-4. The flash memory controller321includes a host IF circuit331, a flash memory IF circuit332-1, and a flash memory IF circuit332-2.

In this case, the application311or the library312of the host device301manages physical information of the SSD302, and controls wear leveling and garbage collection. Consequently, the host device301can distribute and arrange data to the flash memory322-1to the flash memory322-4, and high-throughput low-latency high-speed reading processing and the like are realized. In addition, a DRAM does not need to be provided in the flash memory controller321, and this enables the circuit scale of the flash memory controller321to be reduced.

However, in the SSD302ofFIG. 3, a processor and a DRAM for wear leveling and garbage collection do not exist, and therefore it is desirable that near-data processing be performed by using another technology.

FIG. 4illustrates an exemplary configuration of an SSD according to the embodiments. An SSD401ofFIG. 4includes a host IF circuit411, an arithmetic circuit412, a memory IF circuit413, and a memory414. The memory414stores data, the memory IF circuit413reads the data from the memory414, and the arithmetic circuit412performs a prescribed arithmetic operation on the data.

Upon receipt of an arithmetic instruction from a host device, the host IF circuit411outputs an arithmetic request to the arithmetic circuit412, and also outputs a reading instruction to the memory414via the memory IF circuit413. The host IF circuit411receives, from the arithmetic circuit412, an arithmetic result of the prescribed arithmetic operation that has been performed on the data read from the memory414via the host IF circuit413, and outputs the arithmetic result to the host device.

By employing the SSD401ofFIG. 4, an arithmetic operation can be performed on data at almost the same speed as the speed of reading data.

FIG. 5illustrates an exemplary configuration of an information processing device using the SSD401ofFIG. 4. An information processing device501ofFIG. 5includes a host device511and an SSD512, and the information processing device501can be applied to various technologies such as big data processing, a database appliance, or a storage system. The host device511includes a control unit521that executes a program such as an application or a library. The control unit521is, for example, a CPU (a processor). The SSD512is a software-defined SSD, and the SSD512includes a flash memory controller531, a flash memory532-1, and a flash memory532-2. The flash memory controller531includes a host IF circuit541, an arithmetic circuit542, and a flash memory IF circuit543.

The host IF circuit541is connected to the control unit521, the arithmetic circuit542, and the flash memory IF circuit543, and the flash memory IF circuit543is connected to the host IF circuit541, the arithmetic circuit542, the flash memory532-1, and the flash memory532-2.

Hereinafter, any of the flash memory532-1and the flash memory532-2may be referred to as a flash memory532. The host IF circuit541, the arithmetic circuit542, the flash memory IF circuit543, and the flash memory532respectively correspond to the host IF circuit411, the arithmetic circuit412, the memory IF circuit413, and the memory414inFIG. 4.

In registering data in the SSD512, the control unit521of the host device511distributes and writes the data to the flash memory532-1and the flash memory532-2, and records a writing address. In using the data registered in the SSD512, the control unit521issues a reading instruction or an arithmetic instruction to the SSD512.

Upon receipt of the reading instruction from the host device511, the host IF circuit541of the flash memory controller531outputs a reading instruction that specifies the host IF circuit541to be a data transfer destination to the flash memory IF circuit543. The flash memory IF circuit543outputs the reading instruction to the flash memory532, and the flash memory532outputs the data to the flash memory IF circuit543. The flash memory IF circuit543outputs the data received from the flash memory532to the host IF circuit541, and the host IF circuit541transfers the data received from the flash memory IF circuit543to the host device511.

In addition, upon receipt of the arithmetic instruction from the host device511, the host IF circuit541outputs an arithmetic request to the arithmetic circuit542, and outputs a reading instruction that specifies the arithmetic circuit542to be a data transfer destination to the flash memory IF circuit543. The flash memory IF circuit543outputs the reading instruction to the flash memory532, and the flash memory532outputs the data to the flash memory IF circuit543.

The flash memory IF circuit543outputs the data received from the flash memory532to the arithmetic circuit542, and the arithmetic circuit542performs an arithmetic operation by using the data received from the flash memory IF circuit543, and outputs an arithmetic result to the host IF circuit541. The host IF circuit541transfers the arithmetic result received from the arithmetic circuit542to the host device511. Examples of the arithmetic operation performed by the arithmetic circuit542include search for data stored in the flash memory532and a statistical operation on data.

FIG. 6is a flowchart illustrating an example of an operation that is performed by the host IF circuit541ofFIG. 5upon receipt of a reading instruction or an arithmetic instruction. Upon receipt of an instruction from the host device511(step601), the host IF circuit541checks whether the received instruction is a reading instruction or an arithmetic instruction (step602).

When the received instruction is an arithmetic instruction (step602, YES), the host IF circuit541outputs an arithmetic request to the arithmetic circuit542(step603). The host IF circuit541generates a reading instruction that specifies the arithmetic circuit542to be a data transfer destination (step604), and the host IF circuit541outputs the generated reading instruction to the flash memory IF circuit543(step605).

When the received instruction is a reading instruction (step602, NO), the host IF circuit541generates a reading instruction that specifies the host IF circuit541to be a data transfer destination (step610). The host IF circuit541outputs the generated reading instruction to the flash memory IF circuit543(step605).

The host IF circuit541checks whether data has been received from the flash memory IF circuit543(step606). When data has not been received from the flash memory IF circuit543(step606, NO), the host IF circuit541receives a completion report from the flash memory IF circuit543(step607). When data has been received from the flash memory IF circuit543(step606, YES), the host IF circuit541transfers the received data to the host device511(step611), and receives a completion report from the flash memory IF circuit543(step607).

The host IF circuit541checks whether an arithmetic result has been received from the arithmetic circuit542(step608). When an arithmetic result has been received from the arithmetic circuit542(step608, YES), the host IF circuit541outputs the received arithmetic result as a response to the arithmetic instruction to the host device511(step609). The host IF circuit541may receive the arithmetic result from the arithmetic circuit542prior to the reception of the completion report of step607.

When an arithmetic result has not been received from the arithmetic circuit542(step608, NO), the host IF circuit541outputs a response to the reading instruction to the host device511(step612). Examples of the response to the reading instruction include normal termination and the number of generated errors.

FIG. 7illustrates an example of an operation sequence in a case in which the host IF circuit541ofFIG. 5receives an arithmetic instruction. First, the host IF circuit541outputs an arithmetic request to the arithmetic circuit542(procedure701), and outputs, to the flash memory IF circuit543, a reading instruction that specifies the arithmetic circuit542to be a data transfer destination (procedure702). The flash memory IF circuit543outputs the reading instruction to the flash memory532(procedure703).

The flash memory532starts data transfer to transfer data in each prescribed unit to the flash memory IF circuit543in accordance with the received reading instruction (procedure704). The flash memory IF circuit543starts data transfer to transfer the data received from the flash memory532in each prescribed unit to the arithmetic circuit542(procedure705). The prescribed unit may be, for example, several tens of bytes.

The arithmetic circuit542performs an arithmetic operation using received data while receiving data from the flash memory IF circuit543, and when data transfer from the flash memory IF circuit543is finished, the arithmetic circuit542outputs an arithmetic result to the host IF circuit541(procedure706).

When the flash memory532finishes data transfer to the flash memory IF circuit543, the flash memory532outputs a completion report to the flash memory IF circuit543. Upon receipt of the completion report from the flash memory532, the flash memory IF circuit543outputs the completion report to the host IF circuit541. The completion report from the flash memory IF circuit543to the host IF circuit541may be output before procedure706, or may be output after procedure706.

By employing the information processing device501ofFIG. 5, the arithmetic circuit542can perform an arithmetic operation while directly receiving data from the flash memory IF circuit543, by outputting, to the flash memory IF circuit543, a reading instruction that specifies the arithmetic circuit542to be a data transfer destination. Therefore, throughput with respect to an arithmetic instruction is almost the same as reading speed.

In addition, latency with respect to an arithmetic instruction increases due to the addition of arithmetic processing, but reading latency is sufficiently large, and therefore, in practice, the latency with respect to the arithmetic instruction is almost the same as the reading latency. As an example, when the arithmetic processing is search processing, the reading latency is about several hundred μs, whereas an increase due to the arithmetic processing is about several hundred ns.

Accordingly, the flash memory controller531can perform arithmetic processing in response to an arithmetic instruction at almost the same speed as the speed of data reading.

In addition, the SSD512ofFIG. 5is a software-defined SSD, and therefore the SSD512can directly control a flash memory by using software, and a DRAM does not need to be provided in the flash memory controller531.

FIG. 8illustrates an exemplary configuration of an arithmetic circuit542that searches for data. The arithmetic circuit542ofFIG. 8includes a keyword register801, a comparison circuit802, and a buffer803. The control unit521of the host device511issues a search instruction including a search target to the SSD512. As the search target, a keyword811is used, for example.

In a case in which the host IF circuit541of the flash memory controller531receives a search instruction including the keyword811, the host IF circuit541outputs a search request including the keyword811to the arithmetic circuit542. The arithmetic circuit542stores the keyword811included in the received search request in the keyword register801, and stores data812of a prescribed unit that has been received from the flash memory IF circuit543in the buffer803.

The comparison circuit802compares the keyword811stored in the keyword register801with the data812stored in the buffer803, and checks whether data that matches the keyword811is included in the data812. Accordingly, every time the data812of a prescribed unit is received from the flash memory IF circuit543, a search process is performed. When the data812includes the keyword811, the comparison circuit802records a position within the flash memory532in which the data that matches the keyword811has been stored.

When data transfer from the flash memory IF circuit543is finished, the comparison circuit802outputs a search result813including HIT or MISS to the host IF circuit541. HIT indicates that the keyword811is included in data within the flash memory532, and MISS indicates that the keyword811is not included in data within the flash memory532. When the keyword811is included in the data, the search result813includes information indicating the position of the data within the flash memory532, together with HIT.

By employing the arithmetic circuit542ofFIG. 8, a search process in response to a search instruction can be performed at almost the same speed as the speed of reading data.

FIG. 9illustrates an exemplary configuration of an arithmetic circuit542that performs a statistical operation on data. The arithmetic circuit542ofFIG. 9includes a statistical arithmetic circuit901, a buffer902, and a result register903. The control unit521of the host device511issues a statistical arithmetic instruction that requests a statistical value to the SSD512. As the statistical value, a total value, a mean value, a median, a maximum value, a minimum value, or the like is used. The statistical value may be the number (a count value) of pieces of data that satisfy a prescribed condition.

As an example, in a case in which the statistical arithmetic instruction is a summation instruction that requests a total value of data, the host IF circuit541of the flash memory controller531outputs a summation request to the arithmetic circuit542. The arithmetic circuit542stores data911of a prescribed unit that has been received from the flash memory IF circuit543in the buffer902. The result register903stores a total value of data, and an initial value of the total value is set to 0.

The statistical arithmetic circuit901calculates a total value of the data911stored in the buffer902, and adds the calculated total value to the total value in the result register903. Accordingly, every time the data812of a prescribed unit is received from the flash memory IF circuit543, a summation process is performed, and the total value in the result register903is updated. When data transfer from the flash memory IF circuit543is finished, the result register903outputs a statistical operation result912including the total value to the host IF circuit541.

Also in a case in which the statistical arithmetic instruction is an instruction that requests another statistical value such as a mean value of data, similarly to the case of the summation instruction, the result register903stores a statistical value of data. Every time the data812of a prescribed unit is received from the flash memory IF circuit543, a statistical process is performed, and the statistical value in the result register903is updated.

By employing the arithmetic circuit542ofFIG. 9, a statistical process in response to a statistical arithmetic instruction can be performed at almost the same speed as the speed of reading data.

FIG. 10illustrates an exemplary configuration of an arithmetic circuit542that performs plural different arithmetic operations. The arithmetic circuit542ofFIG. 10includes an arithmetic circuit1001-1and an arithmetic circuit1001-2. The arithmetic circuit1001-1and the arithmetic circuit1001-2are individual arithmetic circuits that perform different types of arithmetic operations. As an example, the arithmetic circuit1001-1may search for data, and the arithmetic circuit1001-2may perform a statistical operation on data.

In a case in which the host IF circuit541receives an arithmetic instruction from the host device511, the host IF circuit541outputs an arithmetic request to an arithmetic circuit1001-i(i=1, 2) that performs an arithmetic operation that corresponds to the received arithmetic instruction. The host IF circuit541outputs a reading instruction that specifies the arithmetic circuit1001-ito be a data transfer destination to the flash memory IF circuit543.

The flash memory IF circuit543outputs data received from the flash memory532to the arithmetic circuit1001-i, and the arithmetic circuit1001-iperforms an arithmetic operation by using the data received from the flash memory IF circuit543, and outputs an arithmetic result to the host IF circuit541. The host IF circuit541transfers the arithmetic result received from the arithmetic circuit1001-ito the host device511.

In this case, in step603ofFIG. 6, the host IF circuit541outputs an arithmetic request to an arithmetic circuit1001-ithat performs an arithmetic operation that corresponds to the arithmetic instruction from among the arithmetic circuit1001-1and the arithmetic circuit1001-2. In step604, the host IF circuit541generates a reading instruction that specifies the arithmetic circuit1001-ithat is an output destination of the arithmetic request to be a data transfer destination. In addition, in step608, the host IF circuit541checks whether an arithmetic result has been received from the arithmetic circuit1001-ithat is the output destination of the arithmetic request.

By employing the arithmetic circuit542ofFIG. 10, an arithmetic circuit1001-ican be selected according to an arithmetic instruction, and an arithmetic operation that corresponds to the selected arithmetic circuit1001-ican be performed at almost the same speed as the speed of reading data.

FIG. 11illustrates an exemplary configuration of an information processing device that includes plural flash memory IF circuits. An information processing device1101ofFIG. 11includes a host device511and an SSD1111, and the host device511includes a control unit521. The SSD1111is a software-defined SSD, and the SSD1111includes a flash memory controller1121and a flash memory1122-1to a flash memory1122-4. The flash memory controller1121includes a host IF circuit1131, an arithmetic circuit1132-1, an arithmetic circuit1132-2, a flash memory IF circuit1133-1, and a flash memory IF circuit1133-2.

The host IF circuit1131is connected to the control unit521, the arithmetic circuit1132-1, the arithmetic circuit1132-2, the flash memory IF circuit1133-1, and the flash memory IF circuit1133-2. The flash memory IF circuit1133-1is connected to the host IF circuit1131, the arithmetic circuit1132-1, the arithmetic circuit1132-2, the flash memory1122-1, and the flash memory1122-2. The flash memory IF circuit1133-2is connected to the host IF circuit1131, the arithmetic circuit1132-1, the arithmetic circuit1132-2, the flash memory1122-3, and the flash memory1122-4.

Hereinafter, any of the flash memory1122-1to the flash memory1122-4may be referred to as a flash memory1122. In addition, any of the flash memory IF circuit1133-1and the flash memory IF circuit1133-2may be referred to as a flash memory IF circuit1133. Further, any of the arithmetic circuit1132-1and the arithmetic circuit1132-2may be referred to as an arithmetic circuit1132.

The host IF circuit1131, the arithmetic circuit1132, the flash memory IF circuit1133, and the flash memory1122respectively correspond to the host IF circuit411, the arithmetic circuit412, the memory IF circuit413, and the memory414inFIG. 4.

An operation of the control unit521of the host device511is similar to the case ofFIG. 5. In a case in which the host IF circuit1131of the flash memory controller1121receives a reading instruction from the host device511, the host IF circuit1131outputs a reading instruction that specifies the host IF circuit1131to be a data transfer destination to the flash memory IF circuit1133.

The flash memory IF circuit1133outputs the reading instruction to the flash memory1122, and the flash memory1122outputs data to the flash memory IF circuit1133. The flash memory IF circuit1133outputs the data received from the flash memory1122to the host IF circuit1131, and the host IF circuit1131transfers the data received from the flash memory IF circuit1133to the host device511.

In a case in which the host IF circuit1131receives an arithmetic instruction from the host device511, the host IF circuit1131-i(i=1, 2), and outputs a reading instruction that specifies the arithmetic circuit1132-ito be a data transfer destination to a flash memory IF circuit1133-i. The flash memory IF circuit1133-ioutputs the reading instruction to the flash memory1122, and the flash memory1122outputs data to the flash memory IF circuit1133-i.

The flash memory IF circuit1133-ioutputs the data received from the flash memory1122to the arithmetic circuit1132-i, and the arithmetic circuit1132-iperforms an arithmetic operation by using the data received from the flash memory IF circuit1133-i, and outputs an arithmetic result to the host IF circuit1131. The host IF circuit1131transfers the arithmetic result received from the arithmetic circuit1132-ito the host device511.

By employing the information processing device1101ofFIG. 11, arithmetic processing can be performed using a group of flash memories1122connected to each flash memory IF circuit1133as a target, by providing arithmetic circuits1132for the respective flash memory IF circuits1133.

The configurations of the SSD302ofFIG. 3, the SSD401ofFIG. 4, the information processing device501ofFIG. 5, and the information processing device1101ofFIG. 11are examples, and some components may be omitted or changed according to the purposes or conditions of an SSD or an information processing device. As an example, in the SSD302, the information processing device501, or the information processing device1101, data may be stored by using another semiconductor memory such as a random access memory (RAM) instead of a flash memory.

In the SSD302, the information processing device501, or the information processing device1101, the number of flash memories that are connected to each flash memory IF circuit is not limited to 2. The information processing device501may include a single flash memory532, or may include three or more flash memories532. The information processing device1101may include three or more arithmetic circuits1132and three or more flash memory IF circuits1133. In addition, the information processing device1101may include five or more flash memories1122.

The configuration of the arithmetic circuit542ofFIG. 8orFIG. 9is an example, and the configuration of the arithmetic circuit542changes according to the type of an arithmetic operation. An arithmetic operation performed by the arithmetic circuit542may be a process for extracting data that is specified by a prescribed pattern.

The configuration of the arithmetic circuit542ofFIG. 10is an example, and the number of arithmetic circuits changes according to the purposes or conditions of an SSD or an information processing device. The arithmetic circuit542may include three or more arithmetic circuits that respectively perform three or more different arithmetic operations.

The flowchart ofFIG. 6is an example, and some processes may be omitted or changed according to the configuration or conditions of an SSD or an information processing device. The operation sequence ofFIG. 7is an example, and another operation may be performed according to the configuration or conditions of an SSD or an information processing device.