Receiver having clock recovery unit based on delay locked loop

A receiver for receiving an input signal (a clock-embedded data (CED) signal), in which a clock signal is periodically embedded between data signals, includes a clock recovery unit configured to recover and output the clock signal and a serial-to-parallel converter configured to recover and output a data signal. The input signal (the CED signal) comprises a single level signal in which the clock signal is periodically embedded between the data signals at the same level. The clock recovery unit is configured based on a delay locked loop (DLL) without using an internal oscillator for generating a reference clock signal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a receiver of a display driving system, and more particularly, to a receiver having a clock recovery unit based on a delay locked loop, wherein a PLL (phase locked loop) structure is excluded and a clock recovery unit realized using only a DLL (delay locked loop) structure without using a separate oscillator for generating a conventional reference clock signal is employed so that a clock signal embedded between data signals having the same level and amplitude as the data signal can be recovered.

2. Description of the Related Art

In general, display devices include a timing controller which processes image data and generates a timing control signal so as to drive a panel for displaying the image data, and data drivers which drive the panel using the image data and the timing control signal transmitted from the timing controller.

Interfaces for transmitting image data to be displayed, between the timing controller and the data driver, include a multi-drop signaling interface, in which the data drivers share a data signal line and a clock signal line, a PPDS (point-to-point differential signaling) interface, in which data differential signals and clock differential signals are separately supplied to the respective data drivers, and an interface, in which data and clock signals are separated into multiple levels and data differential signals with the clock signals embedded therein are transmitted from the timing controller through independent signal lines to the data drivers.

The present applicant has proposed an interface in Korean Patent Application No. 10-2008-0102492, in which a single level signal with a clock signal embedded between data signals (LVDS data) to the same level is used and data and a clock signal are transmitted together by an independent single signal line so that the data and the clock signal can be recovered by a receiver.

In the interface for transmitting data differential signals with clock signals embedded therein to the data drivers by respective independent signal lines, a transmitter generates a transmission signal that corresponds to respective data bits and transits periodically. The periodic transition can occur by dummy bits that are inserted between data bits of a predetermined number. That is to say, the periodic transition occurs due to the fact that a portion immediately before and after the data bits to be transmitted has a value different from the data bits. In this case, since a receiver provided in the data driver cannot receive a separate clock signal, in order to receive the data differential signals with the embedded clock signals and recover original data, the clock signals embedded between the data signals should be recovered from the received differential signals.

Therefore, the receiver should be provided with a recovery circuit for recovering the clock signals, and it is the norm in the conventional art that such a clock recovery circuit is configured to have a phase locked loop (PLL) structure. That is to say, because a reference clock signal as a clock signal generated by oscillation inside the receiver is needed to recover the received data, it is the norm that the clock signal recovery unit is configured by the phase locked loop (PLL) which has an oscillator for generating the reference clock signal.

As is disclosed in Korean Patent No. 868299, a conventional receiver provided in the data driver includes a clock generation unit which is configured to generate a received clock signal from the periodic transition of a differential signal received through a signal line, and a sampler which is configured to sample the differential signal according to the received clock signal and recover data bits.

The clock generation unit includes a transition detecting circuit configured to output a signal corresponding to a time difference between the periodic transition of the received differential signal and the transition of a feedback clock signal, and an oscillator configured to change the phases of the feedback clock signal and the received clock signal in response to the signal outputted from the transition detecting circuit.

The transition detecting circuit is configured in such a manner that the oscillation frequency of the oscillator is determined by the clock signal inputted upon initial synchronization and the operation of a transition detector is interrupted or restarted in response to an enable signal when data is inputted thereafter. In this case, while the enable signal is generated by the clock signal inputted upon the initial synchronization, since there is no clock edge during a time interval excluding the interval of the enable signal, no influence is exerted on the generation of the received clock signal.

Therefore, the clock generation unit is configured in such a manner that only the rising edge or the falling edge of the received signal composed of the dummy bits is recognized as a transition during an interval in which the enable signal has a high logic level and is not recognized as a transition during an interval in which the enable signal has a low logic level, so that the frequency and the phase of the received clock signal generated by the oscillator deviate from the periodic transition by the dummy bits.

Thus, the conventional clock generation unit is configured based on the phase locked loop (PLL) structure having a characteristic that the feedback signal in the oscillator is inputted again to the oscillator after the initial synchronization to generate the enable signal.

However, the conventional clock generation unit configured based on the phase locked loop (PLL) structure has a problem in that jitter continuously accumulates in the phase lock loop (PLL) as an internal feedback loop.

Also, the conventional clock generation unit may be configured to have not only the characteristic of a delay locked loop (DLL) in that the received signal is directly inputted to the oscillator in the initial synchronization to generate the enable signal but also the characteristic of the phase locked loop (PLL) in that the feedback signal in the oscillator is inputted to the oscillator after the initial synchronization to generate the enable signal.

Nevertheless, the conventional clock generation unit, which is configured to operate by the delay locked loop (DLL) structure in the initial synchronization and by the phase lock loop (PLL) structure after the initial synchronization, has a problem in that the oscillation frequency and the phase are likely to be distorted due to the change of the loop during operation.

Further, since the enable signal is generated by the phase locked loop (PLL) structure after the initial synchronization, a problem is still caused in that jitter continuously accumulates in the phase locked loop (PLL) as an internal feedback loop.

SUMMARY OF THE INVENTION

The technical problem to be solved by the present invention is to provide a receiver having a clock recovery unit based on a delay locked loop that recovers a clock signal periodically embedded between data signals of a clock-embedded data (CED) signal by using only a delay locked loop and prevents jitter from accumulating due to continuous transmission of the clock signal through a feedback loop.

A receiver having a clock recovery unit based on a delay locked loop comprises a clock recovery unit configured to recover and output the clock signal and a serial-to-parallel converter configured to recover and output a data signal, wherein the clock recovery unit is characterized by receiving a clock embedded data signal in which only the clock signal is included during a clock training interval and the clock periodically embedded between the data signals after the clock training interval, generating a first master clock signal from the clock embedded data signal during the clock training interval and generating a second master clock signal from the clock embedded data signal after the clock training interval, after the training interval, generating the second master clock signal by a first delay clock signal that delays the first master clock signal so as to have a phase difference and then generating the second master clock signal by a second delay clock signal that delays the second master clock signal so as to have a phase difference, and providing a recovery clock signal from the second delay clock signals.

EFFECT OF THE INVENTION

The present application has advantages in recovering a clock signal transmitted while being embedded between data signals having the same level and amplitude as the data signal by using a clock recovery unit configured based only on a delay locked loop, preventing jitter from accumulating owing to a feedback loop in a phase locked loop, and preventing disturbance from occurring in an oscillating frequency and a phase due to mixed use of a delay locked loop and a phase locked loop.

THE DESCRIPTION OF REFERENCE NUMERALS

DETAILED DESCRIPTION OF PREFERRED EMBODIMENT

FIG. 1is a block diagram illustrating a receiver for receiving a clock embedded data signal with an embedded clock signal in accordance with an embodiment of the present invention.

Referring toFIG. 1, a receiver for receiving a clock embedded data signal embedded with a clock signal includes a serial-to-parallel converter100configured to receive a clock embedded data (clock embedded data: CED) signal transmitted through a serial signal line from a timing controller, convert clock embedded data signal into parallel data and transmit recovered data to a display panel, and a clock recovery unit200configured to extract a clock signal embedded in the clock embedded data signal (CED), transmit to the serial-to-parallel converter100a sampling clock signal to be used for the recovery of the data signal and output a recovery clock signal to be used for the output of data.

The present invention is for solving the problems caused in a clock recovery unit configured based on a phase locked loop (PLL) due to the fact that jitter continuously accumulates as a clock signal generated in the clock recovery unit passes through an internal feedback loop. The present invention suggests the clock recovery unit200configured only using a delay locked loop (DLL) in which jitter does not continuously accumulate, so that a clock signal embedded in a clock embedded data (CED) signal can be recovered by the receiver without using an oscillator for generating a conventional reference clock signal. In this regard, since the other component parts of the receiver, such as the serial-to-parallel converter100, excluding the clock recovery unit200can be configured similarly to a conventional receiver for receiving a clock embedded data (CED) signal and implementing recovery, the configuration of the clock recovery unit200which is formed based only on the delay locked loop (DLL) will be described below in detail.

The clock embedded data (CED) signal to be received by the receiver is a signal in which a clock signal is embedded between data signals to be transmitted, and is transmitted from the timing controller through the signal line to a data driver. At this time, while it is preferred for the clock embedded data (CED) signal that the clock signal has the same level and amplitude as the data signal and is embedded between the data signals, it is to be understood that the clock signal can be embedded at multiple levels. The clock embedded data (CED) signal as an input signal received by the receiver through the signal line may comprise one differential signal or a single-ended signal.

Also, a clock embedded data (CED) signal may include only a clock signal or it may be a signal embedded in a data signal.

Therefore, in case a clock signal is included in a clock embedded data (CED) signal in the specification of the present invention, it is distinguished as “a first clock embedded data signal” and in case a clock signal is embedded in a data signal, it is distinguished as “a second clock embedded data (CED) signal.” And, in case there is no need to distinguish signals, it is collectively referred to as “a clock embedded data (CED) signal.”

FIG. 2is of exemplary views showing transmission data composed of clock embedded data (CED) signals with embedded clock signals in accordance with the embodiment of the present invention.

Referring toFIG. 2, the clock embedded (CED) signal periodically inserts clock signals of the same level between data bits and inserts a dummy bit between data signals and clock signals to so as to represent the rising edge or the falling edge of the inserted clock signals. At this time, it is of course possible to increase the width of the dummy signals and the clock signals so as to ease circuit design.

The timing controller transmits clock embedded data (CED) signal comprising only the clock signal before transmitting data signal, thereby starting clock training. The data driver generates a first master clock signal to be used for a recovery of embedded clock signals in response to a first clock embedded data (CED) signal transmitted during a clock training interval. LOCK signals LOCK1˜LOCKNis transited to an “H” state when a first master clock signal (MCLK) is stabilized.

The timing controller ends the clock training after the lapse of a predetermined time and starts the transmission of a second clock embedded data (CED) signal including data signals and clock signals. If the LOCK signal is transited to an “L” state (a low logic state) during the transmission of the data, the timing controller immediately restarts the clock training and maintains the clock training for a preset time.

FIG. 3is a configurational view of a clock recovery unit in accordance with the embodiment of the present invention.

Referring toFIG. 3, the clock recovery unit200is configured based on the delay locked loop (DLL) and is configured based on the delay locked loop (DLL) that provides delay clock signals to recover the clock signal from the clock embedded data (CED) signal transmitted from a transmitter, and to generate at least one sampling clock signal and the recovery clock signal to be used for the detection of data signal.

A clock recovery unit200is configured to include a clock generator210configured to generate a master clock signal (MCLK) from the clock embedded data (CED) signal, a delay line220configured to delay the master clock signal MCLK generated in the clock generator210and output delay clock signals having various phases depending upon delay amounts; a phase difference detector230configured to compare the delay clock signals from the delay line220and detect phase differences or time differences; and a low pass filter240configured to generate a delay controlled signal VCTRL depending upon a comparison result from the phase difference detector230and supply the delayed signal to the delay line220.

The clock generator210is configured to generate a mask signal MASK, a pull-up signal PU or a pull-down signal PD in response to at least one signal among various delayed clock signals outputted from the delay line220and recover the clock signal embedded between the data signals. Therefore, the clock generator receives as an input the delayed clock signals CK1, CK2. . . CK2N+1outputted from the delay line220, and generates a first master clock signal MCLK by the clock embedded data (CED) signal inputted during the clock training interval before the delayed clock signals CK1, CK2. . . CK2N+1are generated. At this time, the number of the delayed clock signals should be at least equal to or greater than 2N+1, where N is a natural number that indicates the number of data bits existing between clock bits that are periodically embedded.

In the embodiment of the present invention, the master clock signal (MCLK) generated during the clock training interval is described as a first master clock signal (MCLK), a master clock signal (MCLK) generated after the clock training interval is described as a second master clock signal (MCLK), and in case of collectively referring to them, they are described as a master clock signal (MCLK).

Also, in the embodiment of the present invention, delayed clock signals CK1, CK2. . . CK2N+1outputted by a first master clock signal (MCLK) from the delay line220are described as a first delay clock signal, delayed clock signals CK1, CK2. . . CK2N+1outputted by a second master clock signal (MCLK) from the delay line220are described as a second delay clock signal, and in case of collectively referring them, they are described as delay clock signals.

FIG. 4is a configurational view of a clock generator in accordance with the embodiment of the present invention.

Referring toFIG. 4, the clock generator210includes a mask signal generator211configured to receive the delayed clock signals and generate a mask signal MASK; a pass switch212configured to switch a cutoff switch in response to the mask signal MASK and control the transmitting state of the clock embedded data (CED) signal; a cutoff switch213configured to cutoff direct transmission of the clock embedded data (CED) signal in response to the LOCK signal transmitted from the timing controller and the mask signal MASK; a pull-up section214and a pull-down section215configured to complementarily operate with respect to each other in response to at least one signal of the delayed clock signals CK1, CK2. . . CK2N+1when the cutoff switch213is turned off and generate and output the master clock signal MCLK; and a first switch216configured to connect one end of the pull-up section214to a power supply voltage VDD and a second switch217configured to connect one end of the pull-down section215to a ground voltage GND. At this time, the LOCK signal is a signal that informs the ending of the clock training interval, and indicates that the operation of the delay locked loop is stabilized or an external input signal is stabilized.

The mask signal generator211comprises a masking circuit which receives the delayed clock signals CK1, CK2. . . CK2N+1) outputted after being delayed through a plurality of inverters in the delay line220so as to recover clock signals embedded with the clock embedded data (CED) signal and detects the rising edges or the falling edges of the clock signals.

The pass switch212is switched in response to the LOCK signal and controls the operation of the cutoff switch213so that the mask signal MASK for detecting the edges of the clock signals embedded in the clock embedded data (CED) signal can be transmitted. The pass switch212has one end which is connected to the mask signal generator211and the other end which is connected to the cutoff switch213for cutting off the transmission of the clock embedded data (CED) signal as the output of the clock generator210.

At this time, the pass switch212is configured in such a manner that the mask signal MASK is connected to the cutoff switch213in response to the LOCK signal or the logic value of “1”, that is, a value indicating a logic high state is connected to the cutoff switch213. In other words, in the case where the LOCK signal is in a logic high state, the cutoff switch213operates by the mask signal MASK, and in the case where the LOCK signal is in a logic low state, the first clock embedded data (CED) signal is outputted as a first master clock signal MCLK.

Also, the cutoff switch213has one end which is connected to a signal line connected to the receiver and the other end which is connected to the delay line220. The cutoff switch213is configured to control the direct transmission of the a first clock embedded data (CED) signal as a first master clock signal MCLK to the delay line220and receive the mask signal MASK for detecting edges of a clock signal embedded in a second clock embedded data (CED) signal, from the pass switch212.

The other end of the cutoff switch213is connected as well to the connection node of the pull-up section214and the pull-down section215which is connected to the delay line220, and cuts off the output of a second clock embedded data (CED) signal and outputs a second master clock signal (MCLK) recovered by pull-up or pull-down operation.

Hence, the cutoff switch213is configured to operate by the mask signal MASK transmitted from the pass switch212and be controlled to detect the rising edge or the falling edge of the clock signal embedded in the second clock embedded data (CED) signal when the LOCK signal is in a logic high state, and operate by the logic value “1” and allow the first clock embedded data (CED) signal to be outputted as a first master clock signal MCLK when the LOCK signal is in a logic low state.

Since the state in which the LOCK signal is in the logic low (L) state corresponds to the clock training interval, the pass switch212is connected to the logic value of “1”, and the cutoff switch213transmits the first clock embedded data (CED) signal as a first master clock signal MCLK irrespective of the logic state of the mask signal MASK. Thus, the clock signal of a first clock embedded data (CED) signal transmitted from the clock generator210during the clock training interval is transferred to the delay line220as a first master clock signal (MCLK).

Namely, while a signal having a period corresponding to the period of the clock signal inserted between the data signals when the timing controller transmits the signal is needed to recover the edges of the clock signal embedded in a second clock embedded data (CED) signal, the signal can be obtained, without using a separate oscillator for generating a reference clock signal, by outputting, as it is, a first clock embedded data (CED) transmitted during the clock training interval, from the clock generator210. A signal obtained at this time is a first master clock signal (MCLK). A first master clock signal (MCLK) is transferred to the delay line220comprising a voltage-controlled delay line (VCDL) or a current-controlled delay line (CCDL).

However, in the case where the LOCK signal is in a logic high (H) state, the transmission of the clock embedded data (CED) signal is controlled by the mask signal MASK which is generated by the mask signal generator211, the rising edge or the falling edge of the clock signal embedded in the clock embedded data (CED) signal is detected. That is to say, during the interval in which the mask signal MASK is in the logic high (H) state, the edge of the clock signal embedded in clock embedded data (CED) signal is transferred while being detected. However, during the interval in which the mask signal MASK in the logic low (L) state, the cutoff switch213is operated such that the clock embedded data (CED) signal from being transferred as it is, is prevented and the remaining portion of excluding the edge of the clock signal embedded in the clock embedded data (CED) signal is recovered through the operation of the pull-up section214or the pull-down section215using at least one delayed clock signal.

The pull-up section214and the pull-down section215generate the pull-up signal PU or the pull-down signal PD by using or combining at least one signal of the delayed clock signals CK2, CK2. . . CK2N+1when the LOCK signal is in the logic high state and the mask signal MASK is in the logic low state, thereby implementing the pull-up and pull-down operations and recovering the remaining portion excluding the edge of the clock signal embedded in the clock embedded data (CED) signal.

The pull-up section214is connected at one end thereof to the power supply voltage VDD through the first switch216, and the pull-down section215is connected to the ground voltage GND through the second switch217. The first switch216and the second switch217are controlled by the LOCK signal such that they are turned off when the LOCK signal is in the logic low (L) state and are turned on when the LOCK signal is in the logic high (H) state.

Accordingly, when the LOCK signal is in the logic low state, the first switch216prevents the pull-up section214from being connected to the power supply voltage VDD and the second switch217prevents the pull-down section215from being connected to the ground voltage GND. Also, when the LOCK signal is in the logic high state, the first switch216connects the pull-up section214to the power supply voltage VDD, and the second switch217connects the pull-down section215to the ground voltage GND.

In this way, due to the fact that the operations of the first switch216and the second switch217are controlled by the LOCK signal, when the LOCK signal of the delay locked loop (DLL) is in the logic low (L) state, it is possible to prevent the master clock signal MCLK from being erroneously generated due to the mis-operation of the pull-up section214and the pull-down section215.

Hence, the pull-down signal PD outputs as an output the voltage value of the ground voltage GND when an input corresponds to a logic low output since the pull-up section214is turned off and a path is not formed between the power supply voltage VDD and the ground voltage GND, and the pull-up signal PU outputs as an output the voltage value of the power supply voltage VDD when an input corresponds to a logic high output since the potential of the output node thereof is raised to the power supply voltage, the pull-down section215is turned off and a path is not formed from the power supply voltage VDD to the ground voltage GND. A value determined by the switching operations of the pull-up section214and the pull-down section215is outputted as a second master clock signal MCLK and is transferred to the delay line220.

The delay line220may comprise a voltage-controlled delay line (VCDL) or a current-controlled delay line (CCDL). The delay line220is configured based on the delay locked loop (DLL) in such a manner that they do not have a feedback loop by which the delayed clock signals outputted are inputted again, and have a plurality of delay means capable of receiving, delaying and then outputting the master clock signal MCLK outputted from the clock generator210.

Hereafter, the delay line will be stated as, but not limited to, the voltage-controlled delay line220. Also, while it is illustrated inFIG. 3that the delay means comprise inverters, it is to be noted that the delay means are not limited to the inverters but may comprise other delay cells or delay elements.

The delay line220generates a first delay clock signal by delaying a first master clock signal MCLK outputted from the clock generator210during the clock training interval. Further, the delay line (220), after the clock training period ends, generates a second delay clock signal by receiving and delaying the signal obtained by recovering the remaining portion excluding the edges of the clock signal included in the second clock embedded data (CED) signal through the operations of the pull-up section and the pull-down section using the master clock signal MCLK.

The plurality of inverters provided to the delay line220have a delay unit that is composed of a pair of inverters, and generate and output the delayed clock signals CK1, CK2, CK3, . . . CK2N+1through pairs of inverters.

At this time, as the delayed clock signals outputted from the delay line220are transmitted to the clock generator210, the remaining portion of the clock signal excluding the portion inserted between the data can be recovered. That is to say, the delayed clock signals comprise a clock signal that is delayed while passing through the pair of inverters, and optional clock signals selected among delay clock signals are inputted to the clock generator210, such that, when the LOCK signal is in the logic high state and the mask signal MASK is in the logic low state, the remaining portion of the clock signal excluding the edge of the clock signal embedded in the clock embedded data (CED) signal can be recovered by operating the pull-up section214or the pull-down section215.

Optional two clock signals among the master clock signal (MCLK) as an input signal of the delay line220and the delay clock signals delayed by the delay line220are transmitted to the phase difference detector230such that the delay amounts of the clock signals delayed while passing through the inverters can be compared.

The phase difference detector230has as its inputs optional two clock signals among the master clock signal (MCLK) as an input signal of the delay line (220) and the clock signals delayed by delay line (220) and is configured to generate the up/down signal UP/DN as a delay amount control signal corresponding to the time difference between the two clock signals and output the up/down signal UP/DN to the low pass filter240.

At this time, when the LOCK signal is in the logic high state and the delay locked loop (DLL) is locked, the phase difference detector230has, as its inputs being comparison targets, two optional signals among the master clock signal MCLK outputted from the clock generator210and the delayed clock signals CK1, CK2, CK3, . . . , CK2N+1of which time difference is the same as the period at which the clock bits are inserted. While it is illustrated inFIG. 4that the phase difference detector230has as its two inputs a first delayed clock signal CK1delayed first and a 2N+1stdelayed clock signal CK2N+1delayed while passing through all of the plurality of pairs of inverters provided in the delay line and is configured to generate the up/down signals depending upon the time difference between these two input clock signals, it is to be appreciated that the two delayed clock signals selected as the inputs to the phase difference detector230are not limited to these two clock signals.

Namely, when the time difference between the first delayed clock signal CK1and the 2N+1stdelayed clock signal CK2N+1corresponds to the up signal UP as a positive signal, a low pass filter240as a charge pump charges electric charges, and when the time difference corresponds to the down signal DN as a negative signal, the low pass filter240as the charge pump discharges electric charges, thereby controlling the delay amount in the delay line220.

The low pass filter240supplies a signal capable of adjusting a delay amount of the delay line by removing or reducing the high frequency component of the up/down signal UP/DN. While it is illustrated in the embodiment that the low pass filter240comprises the charge pump, it is to be appreciated that the low pass filter240is not limited to such and may comprise various loop filters.

InFIG. 3, in order for the low pass filter240to receive the up/down signal UP/DN and output the voltage control signal VCTRL for adjusting the delay amount of the delay line220, the output terminal of the low pass filter240is connected to the inverters provided to the delay line220. Accordingly, the low pass filter240removes or reduces the high frequency component of the up/down signal generated by the time difference between the two clock signals in the phase difference detector230, and outputs the voltage control signal VCTRL.

FIG. 5is a timing diagram illustrating the operation of the clock recovery unit in accordance with the embodiment of the present invention.

Referring toFIG. 5, in order to recover the rising edge or falling edge of the clock signal inserted between the clock embedded data (CED), a first clock embedded data (CED) signal including a clock signal that has a period corresponding to the period of a clock signal to be recovered, when initially recovering, is needed. Therefore, during the clock training interval in which the LOCK signal is in a logic low state, the first clock embedded data (CED) signal transmitted from the transmitter is outputted as it is as a first master clock signal MCLK from the clock generator210, and is transferred to the voltage-controlled delay line220. During the clock training interval, the LOCK signal is changed from the logic low (L) state to the logic high (H) state. Even though a separate oscillator is not provided, a first master clock signal (MCLK) to be used for the recovery of the clock signal can be generated during the clock training interval.

In order to recover the clock signal embedded in the clock embedded data (CED) signal, using at least one delay clock signal delayed by the delay line220, the mask signal MASK for detecting the rising edge or the falling edge of the clock embedded data (CED) signal, and the pull-up signal PU and the pull-down signal PD for driving the pull-up section214and the pull-down section215to generate the remaining portion of the clock signal excluding the portion detected by the mask signal MASK are generated.

As shown inFIG. 5, if the delayed clock signal is delayed little by little by an amount delayed in the respective delay means and the transition timings of the first delayed clock signal CK1and the 2N+1stdelayed clock signal CK2N+1correspond to each other, the up/down signal is not needed and a current state can be maintained. However, if the transition timings of the two signals do not correspond to each other and a phase difference occurs between the two signals, a delay amount is adjusted by the voltage control signal VCTRL that is generated through charge and discharge in the loss pass filter240.

FIG. 5illustrates that a mask signal (MASK) is generated by being synchronized and combined with a rising edge of a 2N−1stdelayed clock signal CK2n−1and a 2N+1stdelayed clock signal CK2n+1. That is to say,FIG. 5illustrates a mask signal (MASK) generated by selecting two delay clock signals that an edge of a clock signal is located within a phase difference of two signals among delay clock signals CK1, CK2, CK3. . . CK2N+1.

Also,FIG. 5illustrates that a pull-up signal PU is generated by being synchronized with a rising edge of a 2N+1stdelayed clock signal CK2n+1and a pull-down signal PD is generated by being synchronized with a rising edge of a 2N−1stdelayed clock signal CK2n−1. That is to say,FIG. 5illustrates a pull-up signal PU for generating a signal after an edge using a 2N+1stdelayed clock signal CK2n+1having a rising edge which is the same as the end timing of a mask signal (MASK) and illustrates a pull-down signal PD for finishing a recovery of a clock signal using a 2N−1stdelayed clock signal CK2n−1having a rising edge which is the same as the end timing of a 2N+1stdelayed clock signal CK2n+1used as a pull-up signal PU.

Only when both the LOCK signal and the mask signal MASK generated in the mask signal generator211are in the logic high state, the edge of the clock signal embedded in clock embedded data (CED) signal is detected, and if the mask signal MASK is in the logic low state, the remaining portion of the clock signal excluding the edges is recovered by the pull-up signal PU and the pull-down signal PD for operating the pull-up section214and the pull-down section215.

Hence, it is possible that an embedded clock signal is recovered in the clock embedded data (CED) signal having the same level and amplitude as the data signal while preventing jitter from accumulating through nonuse of a separate phase fixed loop and not using a separate internal oscillator and recovery clock signal can be outputted.

FIG. 6is a timing diagram illustrating another operation of the clock recovery unit in accordance with the embodiment of the present invention.

Referring toFIG. 6, in order to recover the clock signal embedded in the clock embedded data (CED) signal as described above, the mask signal MASK for detecting the rising edge or falling edge of the clock signal embedded in the clock embedded data (CED) signal using at least one first delay clock signal generated through delaying and outputting the input signal (the CED signal) during the clock training interval by the delay line220, and the pull-up signal PU and the pull-down signal PD for generating the remaining portion excluding the portion detected by the mask signal MASK are generated.

The clock embedded data (CED) signal shown inFIG. 6is illustrated having a dummy bits preceding the clock signal. When both the LOCK signal and the mask signal MASK are in the logic high state, the transition of the clock signal embedded after the dummy bit is perceived, so that the rising edge or falling edge of the clock signal embedded in the clock embedded data (CED) signal is detected. At this time, depending upon whether the rising edge or the falling edge of the clock embedded data (CED) signal is detected, the sequence of the pull-up signal PU and the pull-down signal PD for driving the pull-up section214and the pull-down section215can be changed.

In these ways, in the present invention, the receiver generates the initial master clock signal to be used in the receiver, using the first clock embedded data (CED) signal transmitted during the clock training interval, detects the edge of the clock signal embedded between data signals to the same level, using the mask signal generated by the initial first master, generates a second master clock signal by recovering the remaining portion of the clock signal excluding the portion detected in this manner, and selects a second delay clock signal that a second master clock signal is delayed to output the recovery clock signal. As a consequence, the clock signal can be outputted from the output signal, that is to say, delay clock signals of the voltage-controlled delay line220based on the delay locked loop (DLL) without using the phase locked loop (PLL) for generating the internally oscillating clock signal.