STACKED ELECTRONIC DEVICES HAVING INDEPENDENT GATES

Embodiments of the invention are directed to an integrated circuit (IC) that includes a stacked device configuration having a top electronic device positioned over a bottom electronic device, along with an isolation region operable to electrically isolate at least a gate region of the top electronic device from a gate region of the bottom electronic device. The gate region of the top electronic device includes a first conductive material, and the gate region of the bottom electronic device includes a second conductive material that is different from the first conductive material.

BACKGROUND

The present invention relates in general to fabrication methods and resulting structures for semiconductor devices. More specifically, the present invention relates to fabrication methods and resulting structures for forming stacked electronic devices having independent gate regions.

In contemporary semiconductor device fabrication processes, a large number of metal oxide semiconductor field effect transistors (MOSFETs), such as n-type field effect transistors (nFETs) and p-type field effect transistors (pFETs), are fabricated on a single wafer. Non-planar MOSFET architectures (e.g., fin-type FETs (FinFETs) and nanosheet FETs) can provide increased device density and increased performance over planar MOSFETs. For example, nanosheet FETs, in contrast to conventional planar MOSFETs, include a gate stack that wraps around the full perimeter of multiple stacked and spaced-apart nanosheet channel regions for a reduced device footprint and improved control of channel current flow.

To further improve wafer density, complimentary FET (CFET) architectures have been developed. In CFET architectures, transistor devices are stacked on top of each other, allowing further maximization of the effective channel width and further reducing device footprint. Fabricating CFETs presents a number of challenges, including, for example, the types of devices that can be stacked, making effective electrical contact to the active components of the stacked devices, and providing the necessary electrical isolation for the stacked devices.

SUMMARY

Embodiments of the invention are directed to an integrated circuit (IC) that includes a stacked device configuration having a top electronic device positioned over a bottom electronic device, along with an isolation region operable to electrically isolate at least a gate region of the top electronic device from a gate region of the bottom electronic device. The gate region of the top electronic device includes a first conductive material, and the gate region of the bottom electronic device includes a second conductive material that is different from the first conductive material.

The above-described embodiments of the invention provide technical benefits and technical effects. For example, because the first conductive material is different from the second conductive material, the gate region of the top electronic device can be provided with different characteristics than the gate region of the bottom electronic device. Additionally, because the gate region of the top electronic device can be provided with different characteristics than the gate region of the bottom electronic device, the top electronic device can be a first type of electronic device, and the bottom electronic device can be a second type of electronic device that is different from the first type of electronic device. The ability to mix and match different types of electronic devices in the stacked device configuration provides improved flexibility in generating the design and floorplan of the IC.

In addition to one or more of the features described above, or as an alternative to any of the foregoing embodiments of the invention, a work function of the first conductive material is different from a work function of the second conductive material.

The above-described embodiments of the invention provide technical benefits and technical effects. For example, because the first conductive material is different from the second conductive material, the work function of the first conductive material can be different from the work function of the second conductive material, which enables the implementation of a type of the top electronic device that requires a different work function than is required for the type of the bottom electronic device. The ability to mix and match different types of electronic devices in the stacked device configuration provides improved flexibility in generating the design and floorplan of the IC.

In addition to one or more of the features described above, or as an alternative to any of the foregoing embodiments of the invention, the top electronic device includes a p-type transistor, and the bottom electronic device includes an n-type transistor. Alternatively, the top electronic device can include an n-type transistor, and the bottom electronic device can include a p-type transistor.

The above-described embodiments of the invention provide technical benefits and technical effects. For example, because the top electronic device can be a first type of electronic device, and the bottom electronic device can be a second type of electronic device that is different from the first type of electronic device, this feature facilitates providing the first type of electronic device as a p-type transistor and providing the second type of electronic device as an n-type transistor. Alternatively, this feature also facilitates providing the first type of electronic device as an n-type transistor and providing the second type of electronic device as a p-type transistor. The ability to mix and match different types of electronic devices in the stacked device configuration provides improved flexibility in generating the design and floorplan of the IC.

In addition to one or more of the features described above, or as an alternative to any of the foregoing embodiments, the top electronic device includes a memory device operable to perform storage operations; and the bottom electronic device includes a transistor operable to perform logic operations.

The above-described embodiments of the invention provide technical benefits and technical effects. For example, because the top electronic device can be a first type of electronic device, and the bottom electronic device can be a second type of electronic device that is different from the first type of electronic device, this feature facilitates providing the first type of electronic device as a memory device operable to perform storage operations, and providing the second type of electronic device as transistor operable to perform logic operations. The ability to mix and match different types of electronic devices in the stacked device configuration provides improved flexibility in generating the design and floorplan of the IC.

In addition to one or more of the features described above, or as an alternative to any of the foregoing embodiments, a portion of the first gate contact structure is electrically coupled to the gate region of the top electronic device through a sidewall of the gate region of the top electronic device.

The above-described embodiments of the invention provide technical benefits and technical effects. For example, providing an electronic connection through a sidewall of the gate region of the top electronic device to a portion of the first gate contact structure provides a relatively large interface between the sidewall of the gate region of the top electronic device and the portion of the first gate contact structure, thereby providing decreased contact resistance.

In addition to one or more of the features described above, or as an alternative to any of the foregoing embodiments, the first gate contact structure is electronically isolated except for the portion of the first gate contact structure that is electrically coupled through the sidewall of the gate region of the top electronic device.

The above-described embodiments of the invention provide technical benefits and technical effects. For example, isolation of the first gate contact structure ensure that the only path for current to flow from the first gate contact structure is through the portion of the portion of the first gate structure that is electrically connected to the sidewall of the gate region of the top electronic device, thereby further providing decreased contact resistance.

Embodiments of the invention also include fabrication methods having substantially the same features, functions, technical benefits, and technical effects of the above-described IC structure.

Additional features and advantages are realized through techniques described herein. Other embodiments and aspects are described in detail herein. For a better understanding, refer to the description and to the drawings.

DETAILED DESCRIPTION

Turning now to a description of technologies that are more specifically relevant to aspects of the present invention, semiconductor devices (e.g., FETs) are formed using active regions of a wafer. The active regions are defined by isolation regions used to separate and electrically isolate adjacent semiconductor devices. For example, in an IC having a plurality of MOSFETs, each MOSFET has a source and a drain that are formed in an active region of a semiconductor layer by implanting n-type or p-type impurities in the layer of semiconductor material. Disposed between the source and the drain is a channel (or body) region. Disposed above the body region is a gate electrode. The gate electrode and the body are spaced apart by a gate dielectric layer.

MOSFET-based ICs are fabricated using so-called complementary metal oxide semiconductor (CMOS) fabrication technologies. In general, CMOS is a technology that uses complementary and symmetrical pairs of p-type and n-type MOSFETs to implement logic functions. The channel region connects the source and the drain, and electrical current flows through the channel region from the source to the drain. The electrical current flow is induced in the channel region by a voltage applied at the gate electrode.

The wafer footprint of an FET is related to the electrical conductivity of the channel material. If the channel material has a relatively high conductivity, the FET can be made with a correspondingly smaller wafer footprint. A known method of increasing channel conductivity and decreasing FET size is to form the channel as a nanostructure. For example, a so-called gate-all-around (GAA) nanosheet FET is a known architecture for providing a relatively small FET footprint by forming the channel region as a series of thin nanosheets (e.g., about 3 nm to about 8 nm thick). In a known GAA configuration, a nanosheet-based FET includes a source region, a drain region and stacked, spaced-apart nanosheet channels between the source and drain regions. A gate surrounds the stacked, spaced-apart nanosheet channels and regulates electron flow through the nanosheet channels between the source and drain regions.

GAA nanosheet FETs are fabricated by forming alternating layers of non-sacrificial nanosheets and sacrificial nanosheets. The sacrificial nanosheets are released from the non-sacrificial nanosheets before the FET device is finalized. For n-type FETs, the non-sacrificial nanosheets are typically silicon (Si) and the sacrificial nanosheets are typically silicon germanium (SiGe). For p-type FETs, the non-sacrificial nanosheets can be SiGe and the sacrificial nanosheets can be Si. In some implementations, the non-sacrificial nanosheet of a p-type FET can be SiGe or Si, and the sacrificial nanosheets can be Si or SiGe. Forming the GAA nanosheets from alternating layers of non-sacrificial nanosheets formed from a first type of semiconductor material (e.g., Si for n-type FETs, and SiGe for p-type FETs) and sacrificial nanosheets formed from a second type of semiconductor material (e.g., SiGe for n-type FETs, and Si for p-type FETs) provides superior non-sacrificial electrostatics control, which is necessary for continuously scaling gate lengths down to seven (7) nanometer CMOS technology and below. The use of multiple layered SiGe/Si sacrificial/non-sacrificial nanosheets (or Si/SiGe sacrificial/non-sacrificial nanosheets) to form the channel regions in GAA FET semiconductor devices provides desirable device characteristics, including the introduction of strain at the interface between SiGe and Si.

To further improve wafer density, complimentary FET (CFET) architectures have been developed. In CFET architectures, transistor devices (e.g., GAA nanosheet FETs) are stacked on top of each other, allowing further maximization of the effective channel width and further reducing device footprint. Fabricating CFETs presents a number of challenges, including, for example, the types of devices that can be stacked, making effective electrical contact to the active components of the stacked devices, and providing the necessary electrical isolation for the stacked devices.

Turning now to an overview of aspects of the invention, embodiments of the invention provide a novel stacked device configuration having a CFET architecture in which independent gates are provided for the stacked device configuration. A configuration of dielectric regions is provided that electrically isolates the bottom electronic device from the top electronic device. Thus, each independent gate can be fabricated from different materials than the other independent gate. For example, the top electronic device can be provided with a gate material having a first work function, and the bottom electronic device can be provided with a gate material having a second work function that is different than the first work function. Additionally, fabrication methods are provided for forming gate contacts for the top electronic device and the bottom electronic device configured and arranged to extend through the top gate structures without increasing the footprint of the CFET architecture. The fabrication methods disclosed herein are sufficiently flexible to enable the fabrication of a variety different device types to be combined into a CFET architecture. For example, a bottom electronic device in the CFET architecture can be a switching device (e.g., a transistor) operable to perform logic-based switching operations, and the top electronic device in the CFET architecture can be a storage device (e.g., a memory element), operable to perform storage-based operations.

Although embodiments of the invention described herein focus on electronic devices having GAA nanosheet architectures, the various aspects of the invention described herein can be applied to electronic devices having other FET architectures, including, for example FinFET architectures. Additionally, although embodiments of the invention described herein depict two (2) electronic devices in the stacked electronic device configuration, any number of electronic device can be provided in the stacked electronic device configuration, and each electronic device can be electronically isolated from the others such that different electronic devices having different architectures and functions can be provided in the stacked electronic device configuration.

Turning now to a more detailed description of embodiments of the invention,FIG.1depicts a two-dimensional top-down view of a simplified nanosheet-based reference structure101having a nanosheet stack (NS) and a gate (Gate). The nanosheet-based reference structure101provides a reference point for the various cross-sectional views (X-view, Y-view) shown inFIGS.2-16. More specifically, the X-view is a side view taken along the NS of the reference structure101, and the Y-view is an end view taken along the active Gate of the reference structure101. Although the cross-sectional diagrams depicted inFIGS.2-16are two-dimensional, the diagrams depicted inFIGS.2-16represent three-dimensional structures. Thus, to assist with visualizing the three-dimensional structures, the top-down view of the nanosheet-based reference structure101provides a reference point for the various cross-sectional views (the X-view and the Y-view) shown inFIGS.2-16.

FIG.2depicts cross-sectional views (an X-view and a Y-view) of a novel stacked device configuration202having a CFET architecture and embodying aspects of the invention. The stacked device configuration202defines a top electronic device250positioned over a bottom electronic device260. The bottom electronic device260is a nanosheet-based n-type transistor having stacked and spaced-apart channel nanosheets412surrounded by a high-k metal gate (HKMG) structure identified inFIG.2as HKMG1, along with a high-k dielectric1402. Although it is conventional to represent the high-k dielectric as incorporated within the illustrated representation of the HKMG, for ease of illustration and description, in this detailed description, the HKMG and its associated high-k dielectric are shown separately as a primary metal region represented by HKMB1), and as a gate dielectric region represented by the high-k dielectric1402. In some embodiments of the invention, the high-k dielectric1402associated with HKMG1is a different material than the high-k dielectric1402associated with the HKMG2. The channel nanosheets412are coupled to n-type doped source or drain (S/D) regions1010. The top electronic device250is a nanosheet-based p-type transistor having stacked and spaced-apart channel nanosheets422surrounded by an HKMG structure identified as HKMG2, along with the high-k gate dielectric1402. The channel nanosheets422are coupled to p-type doped S/D regions1012. A configuration of electrical isolation regions are defined that include a dielectric isolation region (or dielectric isolation layer)602, a lower spacer region902, replacement dielectric isolation regions602A, vertical isolation regions1302,1304, and isolation liners320. The configuration of electrical isolation regions enable, inter alia, the materials of the HKMG2and the high-k dielectric1402(specifically the WFM) to be different from the HKMG1and the high-k dielectric1402. Accordingly, the bottom electronic device260with the HKMG1and the high-k dielectric1402can be a first type of electronic device (e.g., an n-type transistor), and the top electronic device250with the HKMG2and the high-k dielectric1402can be a second type of electronic device (e.g., a p-type transistor, or a memory element) that is different from the first type of electronic device. The gate contact CB1extends vertically through the HKMG2and allows convenient contact through a sidewall of the HKMG2, and the gate contact CB2also extends vertically through the HKMG2but is electrically isolated from the HKMG2while allowing convenient contact to the HKMG1through a top surface of the HKMG1. Additional details of how the top electronic device250and the bottom electronic device260can be fabricated are provided subsequently herein in connection with the description of the fabrication operations depicted inFIG.4-16.

FIG.3Adepicts cross-sectional views (an X-view and a Y-view) of a novel stacked device configuration302having a CFET architecture and embodying aspects of the invention. The stacked device configuration302defines a top electronic device350positioned over a bottom electronic device360. The bottom electronic device360is a nanosheet-based n-type transistor having stacked and spaced-apart channel nanosheets412surrounded by a HKMG structure identified as HKMG1and the high-k dielectric1402. The channel nanosheets412are coupled to n-type doped S/D regions1010. The top electronic device350includes nanosheet-based MOSFET memory devices310each having one of the Si channel nanosheets422surrounded by a HKMG structure identified as TANOS (Tantalum-Alumina-Nitride-Oxide-Silicon), along with a relatively thick gate dielectric304. The relatively thick gate dielectric304can be implemented as a so-called extended-gate (EG) dielectric304, which is configured to tolerate larger gate threshold voltages (e.g., larger than required for transistor switching operations) that are required by electronic devices such as MOSFETs that function as memory cells. In embodiments of the invention, the EG dielectric304is relatively thick (e.g., from about 1 nm to about 10 nm). The thickness of the EG dielectric304is selected to increase the threshold voltage VTthat can be tolerated by memory device310. The EG dielectric304can be deposited conformally using any suitable conformal deposition process (e.g., atomic layer depositions (ALD)), and can include interfacial layers (IL) and high-k dielectric layers. In some embodiments of the invention, the high-k dielectric layers can modify the work function of the TANOS control gate370. The high-k dielectric layer can be made of, for example, silicon oxide, silicon nitride, silicon oxynitride, boron nitride, high-k materials, or any combination of these materials. Examples of other high-k materials include but are not limited to metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. The high-k materials can further include dopants such as lanthanum and aluminum.

In the top electronic device350, the channel nanosheets422are coupled to p-type doped S/D regions306. A configuration of electrical isolation regions are defined by a dielectric isolation region602, a lower spacer region902, a replacement dielectric isolation region602A, vertical isolation regions1302,1304, and isolation liners320. The configuration of electrical isolation regions enable, inter alia, the materials of the TANOS and the relatively thick gate dielectric layer304(specifically the WFM) to be different from the HKMG1and the high-k dielectric1402. Accordingly, the bottom electronic device360with the HKMG1and the high-k dielectric1402can be a first type of electronic device (e.g., an n-type transistor or a p-type transistor), and the top electronic device350with the TANOS and the relatively thick gate dielectric304can be a second type of electronic device (e.g., a memory element310) that is different from the first type of electronic device. The gate contact CB1extends vertically through the TANOS and allows convenient contact through a sidewall of the TANOS, and the gate contact CB2also extends vertically through the TANOS but is electrically isolated from the TANOS while allowing convenient contact to the HKMG1through a top surface of the HKMG1. Additional details of how the top electronic device350and the bottom electronic device360can be fabricated are provided subsequently herein in connection with the description of the fabrication operations depicted inFIG.4-16.

FIG.3Bdepicts a cross-sectional view of an example of how the memory element310shown inFIG.3Acan be implemented as a memory element310A. As shown the memory element310A can be an embedded NOR Flash memory device having the Si nanosheet channel422surrounded by a multilayer gate element having the TANOS functioning as a control gate metal370, a blocking layer372(e.g., SiO2), a trap layer374(e.g., SiN), and a tunnel layer376(e.g., SiO2), configured and arranged as shown. Flash memory is an electronic non-volatile computer memory storage medium that can be electrically erased and reprogrammed. The two main types of flash memory, NOR flash and NAND flash, are named for the NOR and NAND logic gates. Both use the same cell design, which can be a floating gate MOSFET. They differ at the circuit level depending on whether the state of the bit line or word lines is pulled high or low. In NAND flash memory, the relationship between the bit line and the word lines resembles a NAND gate, and in NOR flash memory, the relationship between the bit line and the word lines resembles a NOR gate.

FIGS.4-16depict multiple cross-sectional views (i.e., an X-view and a Y-view) of a stacked nanosheet-based structure400after various fabrication operations for forming the stacked device configuration202(shown inFIG.2) having a CFET architecture, along with independent and electrically-isolated gate regions HKMG1(with the high-k dielectric1402) and HKMG2(with the high-k dielectric1402) (shown inFIG.2) in accordance with aspects of the invention. AlthoughFIGS.4-16focus on forming the stacked device configuration202, virtually all of the operations depicted inFIGS.4-16can also be used to fabricate the stacked device configuration302(shown inFIG.3A), the memory element310(shown inFIG.3A), and the example memory element310A (shown inFIG.3B).

Turning initially toFIG.4, there are depicted cross-sectional views of the stacked nanosheet-based structure400after initial fabrication operations in accordance with aspects of the present invention. As shown inFIG.4, an initial wafer is formed that includes a substrate402and a buried insulator (BOX) layer404over the substrate402. A bottom nanosheet stack430is over the BOX layer404; a relatively thicker SiGe sacrificial nanosheet layer418is over the bottom nanosheet stack430; and a top nanosheet stack440is formed over the relatively thicker SiGe sacrificial layer418.

In embodiments of the invention, the substrate402can be a bulk configuration. The substrate402can be formed from silicon or it can be formed from materials other than silicon, e.g., silicon-germanium, a III-V compound semiconductor material, and the like. The BOX layer404can be an oxide such as SiO2. The initial semiconductor layer above the BOX layer404can be a thin SiGe layer (not shown separately) or a Si layer that is later converted to a SiGe layer (e.g., SiGe layer410) by SiGe epitaxy growth and SiGe condensation The terms “substrate” or “semiconductor substrate” should be understood to cover all semiconducting materials and all forms of such materials. Although the stacked nanosheet-based structure400illustrates an SOI (silicon on insulator) configuration (BOX layer404plus the substrate402), embodiments of the inventions apply to any suitable starting substrate/wafer, such as bulk Si wafers, III-V wafers, and the like.

The bottom nanosheet stack430and the top nanosheet stack440each includes an alternating series of SiGe sacrificial nanosheet layers410,420and Si nanosheet layers412,422. In accordance with aspects of the invention, the alternating nanosheet layers410,412,420,422of the bottom and top nanosheet stacks430,440are formed by epitaxially growing one nanosheet layer then the next until the desired number and desired thicknesses of the nanosheet layers are achieved. A hard mask layer (not shown) is deposited over the stacked nanosheet-based structure400. The hard mask layer is patterned to define an elongated fin-shape profile for the stacked nanosheet-based structure400(best shown in the Y-view). The hard mask layer and the stacked nanosheet-based structure400are etched to define the elongated fin-shaped profile for the hard mask (HM)428(best shown in the Y-view), the bottom nanosheet stack430(best shown in the Y-view), the relatively thicker SiGe sacrificial nanosheet layer418, and the top nanosheet stack440(best shown in the Y-view). In accordance with aspects of the invention, the width dimension (W) shown in the Y-view is greater than what is required by the IC design for the final stacked device configuration202(shown inFIG.2). The hard mask layer and the resulting HM428can be formed from any suitable dielectric, including but not limited to SiN.

In embodiments of the invention, each of the nanosheet layers410,412,420,422can have a vertical direction thickness in the range from about 5 nm to about 20 nm, in the range from about 10 nm to about 15 nm, or about 10 nm. Other vertical direction thicknesses are contemplated. Although fifteen (15) instances of the alternating nanosheet layers410,412,418,420,422are depicted in the figures, any number of alternating nanosheet layers can be provided.

As noted, epitaxial growth techniques can be used to form the alternating nanosheet layers410,412,418,420,422shown inFIG.4. Epitaxial materials can be grown from gaseous or liquid precursors using, for example, vapor-phase epitaxy (VPE), molecular-beam epitaxy (MBE), liquid-phase epitaxy (LPE), or other suitable process. Epitaxial silicon, silicon germanium, and/or carbon doped silicon (Si:C) silicon can be doped during deposition (in-situ doped) by adding dopants, n-type dopants (e.g., phosphorus or arsenic) or p-type dopants (e.g., boron or gallium), depending on the type of transistor.

In some embodiments of the invention, the gas source for the deposition of epitaxial semiconductor material include a silicon containing gas source, a germanium containing gas source, or a combination thereof. For example, an epitaxial Si layer can be deposited from a silicon gas source that is selected from the group consisting of silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, methylsilane, dimethylsilane, ethylsilane, methyldisilane, dimethyldisilane, hexamethyldisilane and combinations thereof. An epitaxial germanium layer can be deposited from a germanium gas source that is selected from the group consisting of germane, digermane, halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane and combinations thereof. While an epitaxial silicon germanium alloy layer can be formed utilizing a combination of such gas sources. Carrier gases like hydrogen, nitrogen, helium and argon can be used.

In some embodiments of the invention, the SiGe sacrificial nanosheet layers410,420can be about SiGe 25% or 30%. The notation “SiGe 25%” is used to indicate that 25% of the SiGe material is Ge and 75% of the SiGe material is Si. In some embodiments of the invention, the Ge percentage in the SiGe sacrificial nanosheet layers410,420can be any value, including, for example a value within the range from about 20% to about 45%.

In accordance with aspects of the invention, the relatively thicker SiGe sacrificial nanosheet layer418that separates the bottom nanosheet stack430from the top nanosheet stack440can be about SiGe 60%. In embodiments of the invention, the relatively thicker SiGe sacrificial nanosheet layer418has a Ge percentage that is sufficiently greater than the Ge percentage in the SiGe sacrificial nanosheet layers410,420to provide etch selectivity between the relatively thicker SiGe sacrificial nanosheet layer418and the remaining portions of the stacked nanosheet-based structure400, including specifically the SiGe sacrificial nanosheet layers410,420. In some aspects of the invention, the Ge percentage in the relatively thicker SiGe sacrificial nanosheet layer418is above about 55%. In some aspects of the invention, the SiGe sacrificial nanosheet layers410,420can be SiGe 25%, and the relatively thicker SiGe sacrificial nanosheet layer418can be at or above about SiGe 55% (e.g., about SiGe 60%).

FIG.5depicts cross-sectional views of the stacked nanosheet-based structure400after known fabrication operations have been applied according to embodiments of the invention. A sacrificial anchoring layer502(best shown in the Y-view) is formed on the stacked nanosheet-based structure400and patterned to expose one side of the stacked nanosheet-based structure400. The sacrificial anchoring layer502operates to secure the bottom nanosheet stack430and the top nanosheet stack440after the relatively thicker SiGe sacrificial nanosheet layer418(shown inFIG.4) has been removed. The sacrificial anchoring layer502can be formed of titanium oxide (TiOx). In embodiments of the invention, other example materials of the sacrificial anchoring layer502can include AlOx, TiN, and the like. Subsequent to forming the sacrificial anchoring layer502, a selective etch is performed to remove the relatively thicker SiGe sacrificial nanosheet layer418(shown inFIG.4), thereby forming a cavity504. An isotropic etch can be performed that is selective to remove the relatively thicker SiGe sacrificial nanosheet layer418while not removing the remaining portions of the stacked nanosheet-based structure400, including specifically the SiGe sacrificial nanosheet layers410,420. An example etchant that selectively etches the relatively thicker SiGe sacrificial nanosheet layer418can include a vapor phase hydrogen chloride (HCl) at a suitable temperature and pressure.

FIG.6depicts cross-sectional views of the stacked nanosheet-based structure400after known fabrication operations have been applied according to embodiments of the invention. A dielectric isolation layer602is formed to fill the cavity504(shown inFIG.5). The dielectric isolation layer602provides dielectric isolation between the bottom nanosheet stack430and the top nanosheet stack440. The dielectric isolation layer602can be deposited using ALD, CVD, or any other suitable deposition technique. Example materials of the dielectric isolation layer602can include silicon carbide (SiC), silicon carbon oxygen (SiCO), SiOCN, SiBCN, and the like. Any excess material of the dielectric isolation layer602can be removed by a suitable selective isotropic etching process.

FIG.7depicts cross-sectional views of the stacked nanosheet-based structure400after known fabrication operations have been applied according to embodiments of the invention. More specifically, known fabrication operations (e.g., a wet or dry etch) has been used to remove the sacrificial anchoring layer502(shown inFIG.5). Subsequently, the bottom nanosheet stack430and the top nanosheet stack440are each trimmed using a wet or dry etch to a new width dimension W1. For example, an isotropic etch can be used to selectively etch semiconductor material layers410,412,420,422while not etching dielectric isolation layer602. This results in dielectric isolation layer602have a greater width than semiconductor material layers410,412,420,422in the Y-view. An example process that selectively etches semiconductor material layers410,412,420,422can include a cyclic wet TMAH (tetramethylammonium hydroxide) and dry HCl etch process.

FIG.8depicts cross-sectional views of the stacked nanosheet-based structure400after known fabrication operations have been applied according to embodiments of the invention. More specifically, a conformal deposition of SiGe has been performed followed by an anisotropic reactive ion etch (RIE) to selectively remove any excess SiGe material not covered by the HM428. This results in additional SiGe semiconductor material806formed from substantially vertical SiGe sacrificial layers802,804formed on the sides of the substantially horizontal SiGe sacrificial nanosheets410,420. The deposited SiGe semiconductor material806is the same as the substantially horizontal SiGe sacrificial nanosheets410,420such that the materials410,420,802,804,806can be etched selectively.

FIG.9depicts cross-sectional views of the stacked nanosheet-based structure400after known fabrication operations have been applied according to embodiments of the invention. More specifically, lithography processes are performed to form a lower spacer902on the sides of the substantially vertical SiGe sacrificial layers802,804and the dielectric isolation layer602. To form the lower spacer902, a conformal layer deposition of spacer material is formed on the nanosheet-based structure400and an anisotropic etch (e.g., RIE) is performed to recess the spacer material resulting in the lower spacer902. In aspects of the invention, the lower spacer902is recessed to a height above the dielectric isolation layer602. Subsequently, a mask (e.g., an organic patterning layer (OPL), not shown) is formed and patterned on one side of bottom and top nanosheet stacks430,440while the side of the bottom and top nanosheet stacks430,440where lower spacer902is formed remains covered by the mask, which allows the exposed lower spacer to be selectively removed by wet or dry etch process, leaving the lower spacer902. The lower spacer902can be formed from a suitable dielectric such as SiN, SiBCN, SiC, SiOC, and the like.

FIG.10depicts cross-sectional views of the stacked nanosheet-based structure400after known fabrication operations have been applied according to embodiments of the invention. More specifically, the HM428has been stripped away, and multiple known fabrication operations have been used to form sacrificial gates1002, gate spacers1004, inner spacers1006, n-type doped S/D regions1010, replacement dielectric isolation regions602A, p-type doped S/D regions1012, and interlayer dielectric (ILD) regions1014, configured and arranged as shown. A variety of techniques are available to form these structures, and such techniques are well-known to those skilled in the relevant arts. Accordingly, specific illustrations and detailed descriptions of examples of such fabrication techniques have not been provided in the interest of brevity, and instead, the following summary descriptions of the structures formed inFIG.10is provided.

Referring still toFIG.10, known fabrication operations have been used to, prior to formation of the sacrificial gates1002, deposit a thin layer of gate oxide (not shown separately) over the bottom and top nanosheet stacks430,440. As shown inFIG.10, the sacrificial gates1002represent the combination of the thin layer of gate oxide (e.g., SiO2) and a material (e.g., amorphous silicon (a-Si)) from which the sacrificial gates1002are formed. Known fabrication operations (e.g., an RIE) can be used to form the sacrificial gates1002. In embodiments of the invention, the sacrificial gates1002can be formed by depositing and planarizing a layer of sacrificial gate material (not shown) over the gate oxide (not shown separately from the topmost SiGe sacrificial nanosheet420). In some embodiments of the invention, the sacrificial gate material can be polycrystalline Si. In some embodiments of the invention, the sacrificial gate material can be amorphous Si (a-Si).

Referring still toFIG.10, known fabrication operations have been used to deposit and etch dielectric material to form offset gate spacers1004on sidewalls of the sacrificial gates1002. In embodiments of the invention, the offset gate spacers1004can be formed from any suitable dielectric material including, for example, silicon oxide, silicon nitride, silicon oxynitride, SiBCN, SiOCN, SiOC, or any suitable combination of those materials. In some embodiments of the invention, the offset gate spacers1004can be a low-k dielectric material.

Referring still toFIG.10, the portions of the bottom and top nanosheet stacks430,440that are not covered by the offset gate spacers1004and the sacrificial gates1002are etched, thereby forming two (2) trenches that each extends through the top nanosheet stack440, the dielectric isolation602, and the bottom nanosheet stack430, and further forming multiple instances of the bottom and top nanosheet stacks430,440. The trenches provide access to end regions of the Si nanosheets412,422. The right-most and left-most instances of the bottom and top nanosheet stacks430,440can each be part of an active or inactive electronic device (e.g., a transistor) depending on the requirements of the IC design in which the stacked nanosheet-based structure400will be incorporated. Where the right-most and/or left-most instances of the bottom and top nanosheet stacks430,440is part of an active transistor, the active transistor formed from right-most and/or left-most bottom and top nanosheet stacks430,440will be in series with the transistor formed from the center instances of the bottom and top nanosheet stacks430,440and will share a S/D drain region with the transistor formed from the center instances of the bottom and top nanosheet stacks430,440. Whether or not the transistors formed from the right-most and left-most instances of the top and bottom nanosheet stacks430,440are active, the right-most and left-most instances of the bottom and top nanosheet stacks430,440define portions of the previously described trenches in which the n-type doped S/D regions1010, the replacement dielectric isolation regions602A, the p-type doped S/D regions1012, and the ILD regions1014will be formed.

Referring still toFIG.10, subsequent to forming the above-described trenches, but prior to forming the n-type doped S/D regions1010, the replacement dielectric isolation regions602A, the p-type doped S/D regions1012, and the ILD regions1014, known semiconductor fabrication processes are used to partially remove end regions of the SiGe sacrificial nanosheets410,420to form end region or inner spacer cavities in which the inner spacers1006are formed. The inner spacers1006can be silicon nitride, silicoboron carbonitride, silicon carbonitride, silicon carbon oxynitride, or any other type of dielectric material (e.g., a dielectric material having a dielectric constant k of less than about 5). Subsequent to forming the inner spacers1006, known fabrication operations are used to form the n-type doped S/D regions1010in the previously-described trenches. In embodiments of the invention, an epitaxial growth process can be used to grow the n-type doped S/D regions1010from exposed ends of the Si nanosheets412. In embodiments of the invention, the n-type doped S/D regions1010can be epitaxially grown from gaseous or liquid precursors using, for example, vapor-phase epitaxy (VPE), molecular-beam epitaxy (MBE), liquid-phase epitaxy (LPE), or other suitable process. In embodiments of the invention, the n-type doped S/D regions1010can be doped during deposition (e.g., in-situ doped) by adding dopants such as n-type dopants (e.g., phosphorus or arsenic) during the above-described methods of forming the n-type doped S/D regions1010.

Referring still toFIG.10, subsequent to forming the n-type doped S/D regions1010, the replacement dielectric isolation region602A is formed to replace the portions of the dielectric isolation region602that was removed during formation of the previously-described trenches. Example materials of the replacement dielectric isolation regions602A can include silicon carbide (SiC), silicon carbon oxygen (SiCO), SiOCN, SiBCN, and the like. In embodiments of the invention, the dielectric isolation region602and the replacement dielectric isolation regions602A can be the same or different material. Subsequent to formation of the replacement dielectric regions602A, known fabrication operations are used to form the p-type doped S/D regions1012in the previously-described trenches. In embodiments of the invention, an epitaxial growth process can be used to grow the p-type doped S/D regions1012from exposed ends of the Si nanosheets422. In embodiments of the invention, the p-type doped S/D regions1012can be epitaxially grown from gaseous or liquid precursors using, for example, vapor-phase epitaxy (VPE), molecular-beam epitaxy (MBE), liquid-phase epitaxy (LPE), or other suitable process. In embodiments of the invention, the p-type doped S/D regions1012can be doped during deposition (e.g., in-situ doped) by adding dopants such as p-type dopants (e.g., Ga, B, BF2, or Al) during the above-described methods of forming the p-type doped S/D regions1012. Subsequent to forming the p-type doped S/D regions1012, known semiconductor device fabrication processes are used to deposit ILD regions1014to fill in remaining open spaces of the previously-described trenches and stabilize the stacked nanosheet-based structure400. In aspects of the invention, the ILD regions1014can be formed from a low-k dielectric (e.g., k less than about 4) and/or an ultra-low-k (ULK) dielectric (e.g., k less than about 2.5). The nanosheet-based structure400is then planarized to a predetermined level to prepare the nanosheet-based structure400for downstream processing.

FIG.11depicts cross-sectional views of the stacked nanosheet-based structure400after known fabrication operations have been applied according to embodiments of the invention. More specifically, etching is applied to the sacrificial gates1002to form a full height cut in the sacrificial gate structures1002resulting in gate cut opening1102. The gate cut openings1102extend through the full or entire height of sacrificial gate structures1002, thereby exposing a top surface of the BOX layer404underneath.

FIG.12depicts cross-sectional views of the stacked nanosheet-based structure400after known fabrication operations have been applied according to embodiments of the invention. More specifically, etching is performed to form a less than full height cut in the sacrificial gate structures1002resulting in gate cut opening1102. The gate cut opening1102cuts through part (e.g., at least about half) of the sacrificial gate structures1002, thereby exposing an end surface of the dielectric isolation layer602.

FIG.13depicts cross-sectional views of the stacked nanosheet-based structure400after known fabrication operations have been applied according to embodiments of the invention. More specifically, dielectric material is deposited to fill the gate cut openings1102,1202(shown inFIG.12) then recessed (e.g., using CMP) to the level shown inFIG.13to form the full height vertical dielectric layers1302and the top vertical dielectric layer1304. A bottom surface of full height vertical dielectric layers1302abuts the BOX layer404underneath. A side surface of the top vertical dielectric layer1304abuts the end surface of dielectric isolation layer602. Example dielectric materials for the full height vertical dielectric layers1302and the top vertical dielectric layer1304include SiN, SiBCN, SiOCN, SiOC, SiC, and the like. In embodiments of the invention, different dielectric materials can be utilized for full height vertical dielectric layers1302and top vertical dielectric layer1304.

FIG.14depicts cross-sectional views of the stacked nanosheet-based structure400after known fabrication operations have been applied according to embodiments of the invention. More specifically, known semiconductor fabrication operations have been used to remove the SiGe sacrificial nanosheets410,420(shown inFIG.13) and the sacrificial gates1002(shown inFIG.13). The sacrificial gates1002and the gate dielectric (not shown) can be removed by suitable known etching processes, e.g., RIE or wet removal processes. Known semiconductor fabrication operations can be used to remove the SiGe sacrificial nanosheets410,420selective to the Si nanosheets412,422. In embodiments of the invention, because the SiGe sacrificial nanosheets410,420are formed from SiGe, they can be selectively etched with respect to the Si nanosheets412,422using, for example, a vapor phase HCL gas isotropic etch process. After the fabrication operations depicted inFIG.14, the bottom nanosheet stack430(shown inFIG.9) no longer includes the SiGe sacrificial nanosheets410and the substantially vertical SiGe sacrificial layers802; and the top nanosheet stack440(shown inFIG.9) no longer includes the SiGe sacrificial nanosheets420and the substantially vertical SiGe sacrificial layers804.

Referring still toFIG.14, the spaces that were occupied by the SiGe sacrificial nanosheets410,420(shown inFIG.13) and the sacrificial gates1002(shown inFIG.13) are filled by a multi-segmented HKMG gate stack structure identified inFIG.14as HKMG1, along with a high-k dielectric1402. The HKMG1can include a primary metal region having a work function metal (WFM) (not shown separately), and the high-k dielectric1402can be a relatively thin (e.g., from about 0.7 nm to about 3 nm) high-k gate dielectric (e.g., hafnium oxide) (not shown separately). The HKMG1and the high-k dielectric1402extend into open regions around the bottom nanosheet stacks430and the top nanosheet stacks440to surround the Si nanosheets412,422. The portion of the HKMG1and the high-k dielectric1402around the bottom nanosheet stacks430is considered non-sacrificial, and the portion of the HKMG1and the high-k dielectric1402around the top nanosheet stacks440is considered sacrificial and will be replaced in subsequent fabrication operations in accordance with aspects of the invention to provide independent and electrically isolated gate regions for the bottom nanosheet stack430and the top nanosheet stack440, respectively. The portion of the HKMG1and the high-k dielectric1402that is around the bottom nanosheet stack430will be part of the final regulates electron flow through the Si nanosheets412.

Referring still toFIG.14, the primary metal region of the HKMG1can be formed of any suitable conducting material, including but not limited to, doped polycrystalline or amorphous silicon, germanium, silicon germanium, a metal (e.g., tungsten, titanium, tantalum, ruthenium, zirconium, cobalt, copper, aluminum, lead, platinum, tin, silver, gold), a conducting metallic compound material (e.g., tantalum nitride, titanium nitride, tantalum carbide, titanium carbide, titanium aluminum carbide, tungsten silicide, tungsten nitride, ruthenium oxide, cobalt silicide, nickel silicide), carbon nanotube, conductive carbon, graphene, or any suitable combination of these materials. The primary metal region can further include dopants that are incorporated during or after deposition.

Examples of suitable materials for the high-k dielectric1402associated with the HKMG1include but are not limited to metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. The high-k dielectric1402can further include dopants such as lanthanum, aluminum, magnesium. In some embodiments of the invention, the high-k dielectric1402can further include silicon oxide, silicon nitride, silicon oxynitride, or any suitable combination of those materials with high-k dielectric material. In embodiments of the invention, a function performed by the high-k dielectric1402between the Si nanosheets412,422and the primary gate metal region of the HKMG1is to prevent shorting.

In embodiments of the invention, the WFM layers of the primary metal region of the HKMG1can be a nitride, including but not limited to titanium nitride (TiN), titanium aluminum nitride (TiAlN), hafnium nitride (HfN), hafnium silicon nitride (HfSiN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tungsten nitride (WN), molybdenum nitride (MoN), niobium nitride (NbN); a carbide, including but not limited to titanium carbide (TiC) titanium aluminum carbide (TiAlC), tantalum carbide (TaC), hafnium carbide (HfC), and combinations thereof (e.g., titanium nitride, titanium aluminum nitride, titanium aluminum carbide, titanium aluminum carbon nitride, and tantalum nitride) and other appropriate metals and conducting metal layers (e.g., tungsten, cobalt, tantalum, aluminum, ruthenium, copper, metal carbides, and metal nitrides).

FIG.15depicts cross-sectional views of the stacked nanosheet-based structure400after known fabrication operations have been applied according to embodiments of the invention. More specifically, known semiconductor fabrication operations have been used to recess and/or remove the HKMG1and the high-k dielectric1402from the upper regions of the nanosheet-based structure400, and more particularly from regions around the top nanosheet stack440.

FIG.16depicts cross-sectional views of the stacked nanosheet-based structure400after known fabrication operations have been applied according to embodiments of the invention. More specifically, the spaces that were occupied by the recessed and removed portions of the HKMG1and the high-k dielectric1402have been filled by a multi-segmented HKMG gate stack structure identified inFIG.16as HKMG2, along with the high-k dielectric1402. The HKMG2can include a primary metal region and a work function metal (WFM) (not shown separately), and the high-k dielectric1402includes a relatively thin (e.g., from about 0.7 nm to about 3 nm) high-k gate dielectric material (e.g., hafnium oxide). The HKMG2and the high-k dielectric liner1402include substantially the same general features and functionality previously described for the HKMG1and the high-k dielectric1402, except the materials of the HKMG2and the high-k dielectric liner1202(specifically the WFM) can be different from the HKMG1and the high-k dielectric1402. Accordingly, the combination of the bottom nanosheet stack430(after release of the SiGe sacrificial nanosheets410) with the HKMG1and the high-k dielectric1402can be a first type of electronic device (e.g., an n-type transistor), and the combination of the top nanosheet stack440(after release of the SiGe sacrificial nanosheets420) with the HKMG2and the high-k dielectric1402can be a second type of electronic device (e.g., a p-type transistor, or a memory element) that is different from the first type of electronic device.

Subsequent to the fabrication operations depicted inFIG.16, known semiconductor operations are used to form the final stacked device configuration202shown inFIG.2. More specifically, known semiconductor operations have been used to deposit a layer of ILD210over the nanosheet-based structure400. Subsequently, known semiconductor fabrication operations are used to form a first contact trench extending through the ILD210, the HKMG2, and a portion of the high-k dielectric1402, thereby exposing a top surface of the lower spacer902. The configuration of the gate contact CB1provides one path for current flow through the contact CB1, which is at the interface between the gate contact CB1and a sidewall surface that extends along a height dimension of the HKMG2. Similarly, known semiconductor fabrication operations are used to form a second contact trench extending through the ILD210, the HKMG2, and a portion of the high-k dielectric1402, thereby exposing a top surface of the HKMG1. A gate contact isolation liner320, which can be formed from a dielectric material (e.g., SiO2, high K, SiN), is deposited on sidewalls of the second contact trench, and a gate contact CB2is formed in the remaining volume of the second contact trench such that a bottom surface of the gate contact CB2lands on the exposed top surface of the HKMG1. The configuration of the gate contact CB2provides one path for current flow through the contact CB2, where the one path is at the interface between the gate contact CB2and the top surface of the HKMG1. Accordingly, CB1provides the gate contact to the HKMG2, and CB2provides the gate contact to the HKMG1.

In addition to the gate contacts CB1/CB2, S/D contacts (also known as CA contacts) are provided for the n-type doped S/D regions1010, as well as the p-type doped S/D regions1012. The S/D contacts for the n-type doped S/D regions1010and the p-type doped S/D regions1012can be formed in substantially the same way. However, for ease of illustration and explanation, only the S/D contacts220for the p-type doped S/D regions1012are depicted inFIG.2. The S/D contacts220can be formed by forming trenches extending through the ILD210and the ILD1014, where each trench is sized such that sidewalls of the trenches are ILD material and top surfaces of the p-type doped S/D regions1012are exposed. The remaining volume of the trenches is filled with the S/D contacts220such that bottom surfaces of the S/D contacts220land on the exposed top surfaces of the p-type doped S/D regions1012. In some embodiments of the invention, the S/D contacts220can be formed from conductive material (e.g., a trench silicide), and the material that forms the S/D contacts220can be deposited using, for example, a chemical/electroplating process. In some embodiments of the invention, the S/D contacts220include a liner/barrier (not shown separately) deposited on sidewalls of the trenches prior to deposition of the conductive material of the S/D contacts220.

In embodiments of the invention, the fabrication operations depicted inFIGS.4through16can be used as a base process for fabricating a variety of devices that can be formed through using the bottom nanosheet stack430and the top nanosheet stack440as the base platform for the devices. As an example, substantially the same fabrication operations shown inFIGS.4-16can be used to form the bottom nanosheet stack430into a switching-based electronic device (e.g., a p-type or n-type transistor operable to perform logic operations), and to form the top nanosheet stack440into a storage-based device (e.g., a memory device operable to perm storage operations). A non-limiting example is the final stacked device configuration302shown inFIG.3A, along with the example memory elements310,310A shown inFIGS.3A,3B, both of which are previously described herein.

Accordingly, it can be seen from the foregoing detailed description that embodiments of the invention provide technical benefits and technical effects. For example, embodiments of the invention provide an IC that includes a stacked device configuration having a top electronic device positioned over a bottom electronic device, along with an isolation region operable to electrically isolate at least a gate region of the top electronic device from at least a gate region of the bottom electronic device. The gate region of the top electronic device includes a first conductive material, and the gate region of the bottom electronic device includes a second conductive material that is different from the first conductive material.

The above-described embodiments of the invention provide technical benefits and technical effects. For example, because the first conductive material is different from the second conductive material, the gate region of the top electronic device can be provided with different characteristics than the gate region of the bottom electronic device. Additionally, because the gate region of the top electronic device can be provided with different characteristics than the gate region of the bottom electronic device, the top electronic device can be a first type of electronic device, and the bottom electronic device can be a second type of electronic device that is different from the first type of electronic device. The ability to mix and match different types of electronic devices in the stacked device configuration provides improved flexibility in generating the design and floorplan of the IC.

In addition to one or more of the features described above, or as an alternative to any of the foregoing embodiments, a work function of the first conductive material is different from a work function of the second conductive material.

The above-described embodiments of the invention provide technical benefits and technical effects. For example, because the first conductive material is different from the second conductive material, the work function of the first conductive material can be different from the work function of the second conductive material, which enables the implementation of a type of the top electronic device that requires a different work function than the type of the bottom electronic device. The ability to mix and match different types of electronic devices in the stacked device configuration provides improved flexibility in generating the design and floorplan of the IC.

In addition to one or more of the features described above, or as an alternative to any of the foregoing embodiments of the invention, the top electronic device includes a p-type transistor, and the bottom electronic device includes an n-type transistor. Alternatively, the top electronic device includes an n-type transistor, and the bottom electronic device includes a p-type transistor.

The above-described embodiments of the invention provide technical benefits and technical effects. For example, because the top electronic device can be a first type of electronic device, and the bottom electronic device can be a second type of electronic device that is different from the first type of electronic device, this feature facilitates providing the first type of electronic device as a p-type transistor and providing the second type of electronic device as an n-type transistor. Alternatively, this feature also facilitates providing the first type of electronic device as an n-type transistor and providing the second type of electronic device as a p-type transistor. The ability to mix and match different types of electronic devices in the stacked device configuration provides improved flexibility in generating the design and floorplan of the IC.

In addition to one or more of the features described above, or as an alternative to any of the foregoing embodiments, the top electronic device includes a memory device operable to perform storage operations; and the bottom electronic device includes a transistor operable to perform logic operations.

The above-described embodiments of the invention provide technical benefits and technical effects. For example, because the top electronic device can be a first type of electronic device, and the bottom electronic device can be a second type of electronic device that is different from the first type of electronic device, this feature facilitates providing the first type of electronic device as a memory device operable to perform storage operations, and providing the second type of electronic device as transistor operable to perform logic operations. The ability to mix and match different types of electronic devices in the stacked device configuration provides improved flexibility in generating the design and floorplan of the IC.

In addition to one or more of the features described above, or as an alternative to any of the foregoing embodiments, a portion of the first gate contact structure is electrically coupled to the gate region of the top electronic device through a sidewall of the gate region of the top electronic device.

The above-described embodiments of the invention provide technical benefits and technical effects. For example, providing an electronic connection through a sidewall of the gate region of the top electronic device to a portion of the first gate contact structure provides a relatively large interface between the sidewall of the gate region of the top electronic device and the portion of the first gate contact structure, thereby providing decreased contact resistance.

In addition to one or more of the features described above, or as an alternative to any of the foregoing embodiments, the first gate contact structure is electronically isolated except for the portion of the first gate contact structure that is electrically coupled through the sidewall of the gate region of the top electronic device.

The above-described embodiments of the invention provide technical benefits and technical effects. For example, isolation of the first gate contact structure ensure that the only path for current to flow from the first gate contact structure is through the portion of the portion of the first gate structure that is electrically connected to the sidewall of the gate region of the top electronic device, thereby further providing decreased contact resistance.

The term “conformal” (e.g., a conformal layer) means that the thickness of the layer is substantially the same on all surfaces, or that the thickness variation is less than 15% of the nominal thickness of the layer.

References in the specification to terms such as “vertical,” “horizontal,” “lateral,” etc. are made by way of example, and not by way of limitation, to establish a frame of reference. Terms such as “horizontal” and “lateral” refer to a direction in a plane parallel to a top surface of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. Terms such as “vertical” and “normal” refer to a direction perpendicular to the “horizontal” and “lateral” direction.