A method and system for performing a leading 0/1 anticipation (LZA) in parallel with the floating-point addition of two operands (A and B) in a computer to significantly reduce the Addition-Normalization time. A combinational network is used to process appropriate XOR (P), AND (G) and NOR (Z) state signals resulting from the comparison of the bits in corresponding bit positions of the operands (A and B), starting with the most significant bit (MSB) side of the addition. The state of the initial state signal is detected and shift amount signals are produced and counted for each successive state signal detected, as long as the state remains TRUE. When the state becomes NOT TRUE, adjustments are made depending on the initial state and the successive state, and production of the shift amount signals is halted and an adjustment signal is produced. To determine the exponent of the sum of the floating-point addition, the shift amount count is summed with the adjustment signal. The latter sum will be the exponent of the sum of the operands thus providing a normalized result. The adjustment signal may be based on the CARRY at the NOT TRUE bit position, and the state at the NOT TRUE position may be used to determine whether the result of the addition is positive or negative. In addition to a serial network, an implementing network of a parallel form which accepts appropriate state inputs as blocks of n bits in length, is disclosed, along with certain special implementations.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The present invention involves a method and system for reducing the time 
needed to complete an Addition-Normalization operation in a computer and 
more particularly for normalizing the result of a floating point addition 
in a computer by carrying out leading zero processing in parallel with the 
addition of the operands. 
2. Prior Art 
In electronic computations normalization is used as a means for referencing 
a number to a fixed radix point. Normalization strips out all leading sign 
bits such that the two bits immediately adjacent to the radix point are of 
opposite polarity. Table I exemplifies a 32-bit register containing 
certain floating point numbers. When the Normalize command is applied, the 
bits in the unnormalized numbers will be shifted toward the most 
significant bit (MSB) of the register until the bits on either side of the 
radix point are of opposite value. The numbers are then considered to be 
normalized as indicated in the Table. It will be seen that a negative 
number is normalized in the same manner as a positive number and after the 
illustrated operations it is necessary that the exponent of the 
floating-point numbers be adjusted according to the shift amount. 
TABLE I 
______________________________________ 
Radix Point 
______________________________________ 
Unnormalized Positive 
0'0000001011110001101100111000100 
Number MSB LSB 
After Normalization 
0'1011110001101100111000100000000 
MSB LSB 
Unnormalized Negative 
1'1111110100001110010011000111011 
Number MSB LSB 
After Normalization 
1'0100001110010011000111011000000 
MSB LSB 
______________________________________ 
Heretofore in order to normalize a floating point addition, typically the 
following three steps were performed: 
1. The two terms or operands A and B were added (a process requiring a 
minimum of log(N) time); 
2. The result was searched for the leading 0/1 (depending upon the sign of 
the result), that is, the "leading zero" was detected (LZD); and 
3. The result of the addition was shifted by an appropriate amount. 
Examples of various embodiments of prior art systems utilizing this LZD 
approach are found in U.S. Pat. No. 4,631,696 to Sakamoto, U.S. Pat. No. 
4,644,490 to Kobayashi et al, U.S. Pat. No. 4,649,508 to Kanuma, and Jap. 
Pat. No. 57-196351 of Sakamoto. While some forecasting during the adding 
is found in these teachings, notably in the Japanese patent wherein 
generation of the carry is forecast, still it is generally necessary to 
wait for the completion of the addition function before beginning the 
operation to normalize the result, so that this activity in the prior art 
is compatively time consuming. Consequently, in order to reduce the time 
needed to complete the Addition-Normalization operation, the present 
invention provides a method and system in which the leading 1/0 detection 
may be performed at the same time as the addition (subject only to a 
single bit correction). 
SUMMARY OF THE INVENTION 
In contrast to the prior art leading 0/1 detection (LZD), which, as noted 
above, is carried out after the completion of the addition of the two 
operands A and B in a computerized floating-point addition, the present 
invention performs a leading 0/1 anticipation (LZA) in parallel with the 
addition operation. As a result, the Addition-Normalization time required 
in electronic processing equipment may be significantly reduced. 
The improved operation is accomplished using a combinational network which 
processes appropriate XOR (Propagate), AND (Generate), and NOR (Zero) 
state signals resulting from the comparison of the bits in corresponding 
bit positions of the operands (A and B), starting with the most 
significant bit (MSB) side of the addition. The state of the initial state 
signal is detected and, if the state is G or Z, a signal is produced 
indicating a shift amount, which amount is counted for each successive 
state signal detected, as long as the state remains TRUE. When the state 
becomes NOT TRUE, production of the shift amount signals is halted and an 
adjustment signal is produced. To determine the exponent of the sum of the 
floating point addition, the shift amount count is summed with the 
adjustment signal. The latter sum will be the exponent of the sum of the 
operands thus providing a normalized result. The adjustment signal may be 
based on the CARRY at the NOT TRUE bit position, and the state at the NOT 
TRUE position may be used to determine whether the result of the addition 
is positive or negative. 
When the initial state is P, halting of the shift amount signals becomes 
dependent upon the state of the state signal for the bit position 
following the NOT TRUE bit position. If the second state (G or Z) at the 
NOT TRUE position is followed by a state signal of the third state, then 
production of the shift amount signals is continued until the third state 
becomes NOT TRUE. Otherwise, the shift signals are halted one bit position 
following the NOT TRUE position. In these cases the adjustment signal may 
be based on the CARRY at the bit position at which the shift signals are 
halted, and the state at that position may be used to determine whether 
the result of the addition is positive or negative. 
In addition to a serial network, an implementing network may be of a 
parallel form which accepts appropriate state inputs as blocks of n bits 
in length, comprising Z.sub.1 to Z.sub.n, P.sub.1 to P.sub.n, and G.sub.1 
to G.sub.n state signals resulting from the comparing of the bits in 
corresponding bit positions, and in response produces intermediate state 
outputs comprising ZZ, PP, PZ, PG, and GG signals. By ORing these 
intermediate state outputs, signals indicative of a shift count and an 
adjustment signal may be created based on the bit position at the end of 
the shift count. Summing the shift count with the adjustment signal may 
then be used to determine the exponent of the sum of the floating point 
addition of the operands (A and B). Modifications and simplifications of 
the basic implementing network are possible for special cases.

DETAILED DESCRIPTION OF THE INVENTION 
The present invention is directed to performing a leading 0/1 anticipation 
(LZA) in parallel with the addition of the two operands A and B in a 
computerized floating-point addition, so that the Addition-Normalization 
time may be significantly reduced. By way of brief explanation, in the 
prior art, as illustrated in FIG. 1, generally the result of an addition 
of operands A and B in a floating-point adder 10 is communicated to both a 
shifter 20 and a leading-zero-detection (LZD) logic unit 30. The output of 
the LZD unit 30, when the leading-zero is detected, is used to operate the 
shifter 20 to then produce an output indicative of the normalized result. 
In contrast, as shown in FIG. 2, a leading-zero-anticipation (LZA) logic 
unit 40 in accordance with the present invention receives the operands A 
and B in parallel with the adder 10 and provides its output to the shifter 
20 substantially coincidentally with the receipt of the result of the 
addition so that the normalized result is produced more quickly thus 
increasing the speed of the floating-point-addition operation. 
More specifically, in order to provide an implementing system for 
accomplishing this end an iterative combinational network is disclosed 
with operations and combinations of components as will be understood from 
the following detailed description. 
To begin with, suppose that one of the unnormalized floating point numbers 
depicted in TABLE I above is the result of a floating point addition 
(A+B). This addition for all values of A and B has essentially four 
possible cases: 
EQU 1. A&gt;0, B&gt;0, A+B&gt;0 (Unnormalized Positive Number) 
EQU 2. A&lt;0, B&lt;0, A+B&lt;0 (Unnormalized Negative Number) 
EQU 3. A&gt;0, B&lt;0, A+B&gt;0 (Unnormalized Positive Number) 
EQU 4. A&gt;0, B&lt;0, A+B&lt;0 (Unnormalized Negative Number) 
Since (A&lt;0, B&gt;0) turns out to be case (3) or case (4), it can be handled by 
simply interchanging the register names A and B. 
Now it is possible to define three auxiliary equations which describe the 
Bit-to-Bit relations of the two operands A and B. These logical 
expressions are: 
EQU Z.sub.i =NOR (a.sub.i, b.sub.i) (II.1) 
EQU P.sub.i =XOR (a.sub.i, b.sub.i) (II.2) 
EQU G.sub.i =AND (a.sub.i, b.sub.i) (II.3) 
It will be seen that the logical functions defined above are very similar 
to those used in a Carry-Lookahead Adder (CLA) found in general purpose 
computers, such as an IBM 370 or the like. In fact, P, G, and Z signals 
may be generated in such computers without the use of any additional 
circuitry since they already are required for the CLA function so that the 
invention may be readily carried out on these computers. Accordingly, the 
inputs for the purposes of the invention will be these P, G, Z signals, 
one of which can be TRUE (1) at each bit position. 
Now considering all possible cases in detail, the finite-state 
representation of a leading 0/1 anticipator (LZA) in accordance with the 
present invention may be constructed. 
EQU Case 1: A&gt;0, B&gt;0, A+B&gt;0 
As is well known, there are numerous combinations of A and B resulting in a 
given number. Two interesting combinations of A and B which yield the same 
result are given in TABLE II as follows: 
TABLE II 
______________________________________ 
(a) A 0 0000001000100001001000101000000 
B 0 0000000011010000100100010000100 
Z ZZZZZZPZPPPPZZZPPZPPZZPPPZZZPZZ 
CARRY=0 
(b) A 0 0000000100100001001000101000000 
B 0 0000000111010000100100010000100 
Z ZZZZZZZGPPPPZZZPPZPPZZPPPZZZPZZ 
CARRY=1 
MSB LSB 
______________________________________ 
The state description for the LZA can be obtained from considering the 
examples in Table II. First of all, leading 0/1 anticipation should be 
carried out starting from the Most Significant Bit (MSB) side of the 
addition. Other statements can be summarized as follows: 
1.1- If the MSB is a Z-signal then the LZA enters into a Z-state and 
remains unchanged as long as the Z-signal is TRUE, i.e. (1). 
1.2- For each Z-input, the LZA generates a LEFT-SHIFT signal (SHL). 
1.3- The leading 0/1 anticipation is finished when the kth Z-input is NOT 
TRUE, namely (0). Subsequently, the LZA takes the CARRY into the kth 
Z-position into account and creates an ADJUSTMENT signal (AD) according to 
EQU AD=CARRY (II.4) 
The AD-output is a single RIGHT-SHIFT signal resulting in a total shift: 
EQU SH=SHL-AD (II.5) 
The total shift amount (SH) is important for changing the exponent of the 
floating-point number. 
It will be seen that a simple `NOR` of the bits produces a result which 
differs from the final normalization by less than the CARRY output. 
Referring to the example in TABLE II, the total shift amounts are given by: 
EQU (a) SHL=6, AD=0, SH=6. 
EQU (b) SHL=7, AD=1, SH=6. 
The state diagram obtained by the above discussion is shown in FIG. 3. 
EQU Case 2: A&lt;0, B&lt;0, A+B&lt;0 
As can be seen, this case corresponds to an addition of two negative 
numbers. 
TABLE III 
______________________________________ 
(a) A 1 1111111000000100010000000101001 
B 1 1111111100001010000011000010010 
G GGGGGGGPZZZZPPPZZPZZPPZZZPPPZPP 
CARRY=0 
(b) A 1 1111110110000100010000000101001 
B 1 1111111110001010000011000010010 
G GGGGGGPGGZZZPPPZZPZZPPZZZPPPZPP 
CARRY=1 
MSB LSB 
______________________________________ 
Starting from the examples presented in TABLE III, 
2.1- If the MSB is a G-signal then the LZA enters into the G-state and 
remains unchanged as long as the G-signal is TRUE, i.e. (1). 
2.2- For each G-input, the LZA generates a LEFT-SHIFT signal (SHL). 
2.3- The leading 0/1 anticipation is finished when the kth G-input is NOT 
TRUE, namely (0). Subsequently, the LZA takes the CARRY into the kth 
G-position into account and creates an ADJUSTMENT signal (AD) according to 
EQU AD=INV(CARRY) (II.6) 
which means, if CARRY=0 then AD=1, and if CARRY=1 then AD=0. 
Contrary to the previous case, the LZA for (A&lt;0, B&lt;0) continues as long as 
the bit comparison on the MSB side of both operands is TRUE. This duality 
originates from binary complementing the operands in order to obtain the 
negative numbers. Performing the LZA for 
##STR1## 
will yield the same shift amounts. 
Finally, the state diagram can be extended as shown in FIG. 4. 
EQU Case 3: A&gt;0, B&lt;0, A+B&gt;0 
This case corresponds to a substraction resulting in a positive number. 
TABLE IV 
______________________________________ 
(a) A 0 0000001100100001001000101000000 
B 1 1111111111010000100100010000100 
P PPPPPPGGPPPPZZZPPZPPZZPPPZZZPZZ 
CARRY=1 
(b) A 0 0000001011111001001000101000000 
B 1 1111111111111000100100010000100 
P PPPPPPGPGGGGGZZPPZPPZZPPPZZZPZZ 
CARRY=1 
(c) A 0 0010000011111001001000101000000 
B 1 1110000111111000100100010000100 
P PPGZZZZPGGGGGZZPPZPPZZPPPZZZPZZ 
CARRY=1 
(d) A 0 0010000010100001001000101000000 
B 1 1110001001010000100100010000100 
P PPGZZZPZPPPPZZZPPZPPZZPPPZZZPZZ 
CARRY=0 
MSB LSB 
______________________________________ 
Now extending the statements given in the previous case using the above 
examples: 
3.1- If the MSB is a P-signal then the LZA enters into a P-state and 
remains unchanged as long as the P-signal is TRUE, i.e. (1). 
3.2- For each P-input, the LZA generates a LEFT-SHIFT signal (SHL). 
3.3- If the jth input signal is a G-signal then the new state will be the 
Z-state which has been presented in the previous case. The LZA will create 
a LEFT-SHIFT output and go to statement (1.2). 
Referring to the example in TABLE IV, the total shift amounts are given by: 
EQU (a) SHL=7, AD=1, SH=6. 
EQU (b) SHL=7, AD=1, SH=6. 
EQU (c) SHL=7, AD=1, SH=6. 
EQU (d) SHL=6, AD=0, SH=6. 
The state diagram presented in the previous case can be extended by 
including the new statements 3.1-3.3 as shown in FIG. 5. 
EQU Case 4: A&gt;0, B&lt;0, A+B&lt;0 
Based on the above discussion, this case can easily be included into the 
finite-state machine which has been conveniently denoted by LZA. 
TABLE V 
______________________________________ 
(a) A 0 0000000001000100010000000101001 
B 1 1111110011001010000011000010010 
P PPPPPPZZPGZZPPPZZPZZPPZZZPPPZPP 
CARRY=0 
(b) A 0 0000000000000100010000000101001 
B 1 1111110100001010000011000010010 
P PPPPPPZPZZZZPPPZZPZZPPZZZPPPZPP 
CARRY=0 
(c) A 0 0001111000000100010000000101001 
B 1 1101111100001010000011000010010 
P PPZGGGGPZZZZPPPZZPZZPPZZZPPPZPP 
CARRY=0 
(d) A 0 0001111110000100010000000101001 
B 1 1101110110001010000011000010010 
P PPZGGGPGGZZZPPPZZPZZPPZZZPPPZPP 
CARRY=1 
MSB LSB 
______________________________________ 
As can be seen from each individual example given in Table V, this case 
also begins with the P-state. Therefore, the conditions (3.1-3.2) 
described above will also be valid here. The next input entered after the 
P-state, however, is not a G- but a Z-input. Consequently, the new state 
of the LZA has to be different and it is designated by the G-state. The 
state conditions can now be extended as follows: 
4.1-4.2 are the same as given in 3.1-3.2. 
4.3- If the mth input is a Z-signal then create a LEFT-SHIFT output and go 
to the statement (2.2). 
The total shift amounts are given by: 
EQU (a) SHL=7, AD=1, SH=6. 
EQU (b) SHL=7, AD=1, SH=6. 
EQU (c) SHL=7, AD=1, SH=6. 
EQU (d) SHL=6, AD=0, SH=6. 
The general state diagram can then be obtained as shown in FIG. 6. 
Apart from the CARRY dependent ADJUSTMENT, the logical descriptions of the 
finite-state machine representation can be obtained as follows: 
##EQU1## 
As seen, the Z-state can occur either for the string of (k) Z-inputs or 
(i) P-inputs followed by a single G and the string of (k-i-1) Z-inputs. 
Similar statements can be made for the G-state. 
Besides the total shift amount, the sequential model of the LZA also points 
out whether the final result of the addition is to be positive or negative 
depending on the previous state before finishing leading 0/1 anticipation. 
If the previous state is the Z-state then the final result is positive, 
otherwise it is negative since, as depicted in FIG. 6, the P-state always 
leads to the Z- or G-state. 
Logarithmic Leading 0/1 Anticipator (LZA) 
The finite-state model of the LZA allows entry of a string of serial inputs 
which, depending on the bit-length (N), may not always be as fast as a 
Carry-Lookahead Adder. It is therefore desirable to process the string of 
P-, G-, Z-inputs using a parallel algorithm similar to the Lookahead 
structure. The final construction, which first processes the input data in 
distinctly chosen blocks of block-length D, can be interpreted as a 
parallel implementation of the foregoing finite-state machine considering 
its combinational equivalents for different state and input combinations. 
Accordingly, the leading 0/1 anticipation may be carried out digitwise, 
that is, using a block-length of 4-Bits, although the results can easily 
be extended to arbitrary block-lengths. Assuming that the beginning of a 
block is on the kth bit position, the possible input combinations at this 
position are given by: 
##STR2## 
According to the string between the kth and (k-3)th bit positions, the 
state outputs of the LZA are defined as follows: 
##EQU2## 
It will be noted that the names of the intermediate state outputs 
correspond to their beginning and finishing states. For a block-length D 
(3.sup.D possible input combinations), the number of the input 
combinations resulting in an intermediate LZA block output is given by 
(2D+3). As shown in the following example, the 2D combinations occur for 
PZ-and PG-states. 
______________________________________ 
PZ PG 
1 2 . . . . D 1 2 . . . . D 
______________________________________ 
1 G Z Z . . Z Z 
1 Z G G . . G G 
2 P G Z . . . Z 
2 P Z G . . . G 
. P P G . . . . 
. P P Z . . . . 
. . . . G . . . 
. . . . Z . . . 
. . . . . G . Z 
. . . . . Z . G 
. P . . . . G Z 
. P . . . . Z G 
D P P . . P P G 
D P P . . P P Z 
______________________________________ 
Three additional combinations are due to the ZZ, PP-, and GG-states. This 
is important to ascertain the correctness of the logical equations in the 
general case and to compare the design complexity for different 
block-lengths. 
Looking back to the finite-state machine (FIG. 6), the new set of state 
equations designated in terms of the beginning and final inputs, is 
slightly different. Two new terms 
EQU (G.sub.k Z.sub.(k-1) Z.sub.(k-2) Z.sub.(k-3)) (III.6) 
and 
EQU (Z.sub.k G.sub.(k-1) G.sub.(k-2) G.sub.(k-3)) (III.7) 
are presented in the PZ- and PG-states that, in essence, would not occur in 
the LZA model given in FIG. 6. These expansions are due to the fact that 
each block handles the data without being informed about the results of 
the adjacent one. Hence, if the output state of the previous block is PP, 
then the consecutive state should be a PZ- or PG-output. The resulting 
basic building block of the LZA is shown in FIG. 7A and a suitable logic 
diagram for its implementation is given in FIG. 7B. 
This circuit is a combinational network since its outputs are fully 
determined by the inputs. Thus the implementation of the sequential 
network is converted into the problem of propagating the different state 
outputs for the iterative combinational network. A preferred anticipation 
scheme for the state iteration is depicted in FIG. 8A and a suitable logic 
diagram for its implementation is given in FIG. 8B. 
The logical equations necessary for the state iteration can be obtained by 
considering the input strings of the serial LZA for all possible cases. 
##STR3## 
where 
(j=1, 2, . . . , (J-1) ) and [m=(i.sup.(j-1) +1), . . . , M]; 
M=N/D, J=log.sub.i M, (J, M integers, i : Lookahead distance); 
N: Total bit-length of the LZA; 
D: Block-length; and 
J: The number of the LZA stages necessary. 
Although the equations for the state iteration are expressed in terms of 
the state outputs of the two adjacent blocks, they can be extended to 
arbitrary lookahead distances. 
At any stage, an anticipated state can be generated by implementing the 
above equations and using auxiliary functions ZZ.sub.1k, PP.sub.1k, 
PZ.sub.1k, PG.sub.1k, and GG.sub.1k. Each cell at the following iteration 
stages will have the intermediate ZZ-, PP, PZ-, PG-, GG-signals as inputs 
(to receive the information from its neighbors on the left and the top) 
and as outputs (to supply the anticipated states to its neighbors on the 
right and the bottom as well as to the network outputs). It is interesting 
to note that either (1) only one of these states can be TRUE (1), or (2) 
all of them are NOT TRUE (0), if no leading 0/1 has been detected. The 
LEFT-SHIFT signal can therefore be defined by: 
EQU SHL.sub.jm =OR (ZZ.sub.jm, PP.sub.jm, PZ.sub.jm, PG.sub.jm, 
GG.sub.jm)(III.13) 
A logic diagram for this function is shown in FIG. 9. 
At this point in the description, an example may be helpful in 
understanding the calculation of the SHL signals. Consider now the 
following input string: 
##STR4## 
It will be seen that the LZA will give m LEFT-SHIFT signals beginning from 
the MSB side of the addition. It is then necessary to determine the 
ADJUSTMENT at the mth digit-position. A single signal is needed which 
points out that the CARRY input to the mth digit is to be taken into 
account in order to generate a RIGHT-SHIFT signal. This 
ADJUSTMENT-POSITION output can be created using the string of the SHL 
signals. 
EQU ADP.sub.m =SH.sub.im INV(SH.sub.i(m+1))=SH.sub.im 
XOR(SH.sub.i(m+1))(III.14) 
The logic diagram for this function in FIG. 10 illustrates that ADP.sub.m 
will be TRUE if, and only if, the two SH-signals are different. As pointed 
out above, the SH-signals consist of a TRUE bit-string followed by the NOT 
TRUE one. Therefore, ADP.sub.m will be TRUE at the transition digit. Again 
considering the example: 
##STR5## 
The ADJUSTMENT in that case becomes: 
EQU AD.sub.m =ADP.sub.m CARRY (III.15) 
or 
EQU AD.sub.m =ADP.sub.m INV(CARRY) (III.16) 
depending upon the state in which the leading 0/1 anticipation has been 
finished. Interestingly, if the finishing state is PP, then 
EQU AD.sub.m =0, (III.17) 
since both cases, CARRY=1 and CARRY=0, would only determine whether the 
result is positive or negative but would not change the shift amount. 
Based on the above discussion, it will be seen that the LZA would 
preferably include a (N/4) LEFT- (1) RIGHT-SHIFTER, where N is the 
Bit-length of the leading 0/1 anticipation. 
Processing the shift signals depends on the realization of a suitable 
shifter. Accordingly, a simple approach will now be presented in order to 
demonstrate some interesting features of the output signals of the LZA as 
well as how the SHIFT operation can be carried out effectively. For large 
Bit-lengths, performing the SHIFT operation in a single level would 
require a large number (maximum) of subcycles. In such cases, this 
operation could be carried out in different SHIFT levels. For example, 
m=14 can be split up by: 
EQU 3 times 4-Digit LEFT-SHIFT 
EQU 2 times 1-Digit LEFT-SHIFT 
The multilevel SHIFT signals can be generated in the same manner as 
ADP.sub.m, e.g., by connecting the SHL-signals at appropriate distances. 
An n-Digit LEFT-SHIFT is defined by: 
EQU NSH.sub.m =SH.sub.m INV(SH.sub.m+n) (III.18) 
Referring back to the previous example, a 4-Digit LEFT-SHIFT can be created 
as follows: 
______________________________________ 
Digits 4 8 12 16 . . . 
SHL 1111 1111 1111 1100 . . . 
0 0 1 1 . . . 
4SH 0 0 1 0 . . . 3 .times. 4-Digit 
1SH 000 000 000 010 . . . 2 .times. 1-Digit 
______________________________________ 
Note that generating the ADP signal already provided the number of the 
1-Digit LEFT-SHIFT because this case corresponds to (n=1). 
IMPLEMENTATION OF THE BITWISE NORMALIZATION 
Using the above implementation, the leading 0/1 anticipation can be 
performed with a 3-bit accuracy in the worst case. In order to obtain the 
exact shift amount, this network can easily be extended to a bitwise 
normalization; however, this would require some supplementary logic to 
determine the exact shift position. In any event, after finishing the 
blockwise leading 0/1 anticipation, the ADJUSTMENT-POSITION signal points 
out in which block the exact shift position is to be found. Defining 
EQU ZZ.sub.1k =Z.sub.k, PP.sub.1k =P.sub.k, GG.sub.1k =G.sub.k (IV. 1) 
the consecutive states can be described by applying the logical expressions 
given in Eqs. (III.1-5) to the actual case. The SHIFT signals, stripping 
out the appropriate bit amount (k=1, 2, 3), are obtained in the same 
manner as the preceding discussion. 
SPECIAL REALIZATIONS 
A special implementation of the LZA is obtained when one of the operands in 
the floating point addition is assumed to be always positive resulting in: 
EQU G.sub.11 =0 (V.1) 
This supposition also simplifies other consecutive state anticipations. At 
the end, it can readily be shown that the LEFT-SHIFT signals are defined 
by: 
EQU SHL.sub.jk =OR(ZZ.sub.jk, PP.sub.jk, PZ.sub.jk, PG.sub.jk) (V.2) 
Note that the intermediate state GG.sub.jk (j&gt;1) may still be other than 
zero. 
Another interesting constraint is that, in addition to the previous 
assumption, the register lengths of the two operands may not be equal. 
This is commonly encountered during a floating point addition to achieve 
equal exponents for both operands. For example, let the bit-lengths of A 
and B be m and n, respectively, where m&lt;n. The first (n-m) bits of the 
operand A can be interpreted to be zero. Therefore, the general basic 
building block of FIG. 7A can be simplified as shown in FIG. 11. 
Note that, only the PP, ZZ, or PG states can occur in the first (n-m) bit 
positions. If the state PG occurs in the kth bit position (k&lt;n-m) then 
leading 0/1 anticipation will be finished since the subsequent state input 
can only be P or Z but not G. The LEFT-SHIFT signals can be created using: 
EQU SHL.sub.jk =OR (ZZ.sub.jk, PP.sub.jk, PG.sub.jk) for (k&lt;n-m)(V.3) 
The leading 0/1 anticipation can continue if, and only if, and only if, the 
PG-state occurs for k=n-m in which there are two possible implementations. 
If j is defined 
EQU j=mod.sub.D (n-m) (V.4) 
For j=0, the entire LZA can be implemented using the building blocks 
depicted in FIGS. 7A and 11. 
The construction for D=4 is shown in FIG. 12. 
For j&gt;0, a new transition block is to be realized by reducing the 
appropriate state expressions in eqs. (III.1-5) according to the value 
(j). When 
j=1, PZ and GG are to be simplified; and, when 
j&gt;1, PZ, PG, and GG are to be simplified. 
This special realization is shown in FIG. 13. 
It will be appreciated that starting the LZA with a reduced set of state 
equations simplifies the entire implementation. 
In summary, FIG. 14 is a flow diagram generally illustrating the operation 
of the elements of the LZA component 40 indicated in FIG. 2. Briefly, the 
operands A and B are received in registers 50a and 50b, respectively, and 
their most significant bits (MSB) are successively compared in comparator 
51 which outputs P, G, or Z state signals, as appropriate. The state of 
the initial state signal I is compared with the state of each of the 
subsequently-produced state signals n to determine whether the result is 
TRUE or NOT TRUE. If TRUE, a shift signal is produced causing shifter 52 
to shift the operands in registers 50a and 50b to continue the state 
comparisons. Each shift signal output by shifter 52 is also counted by a 
counter 53. When the comparison becomes NOT TRUE, it is determined whether 
the initial state I is either G or Z. If it is either, shifting ceases and 
a signal is output to cause adjuster 54 to produce an adjustment signal 
that is input to the counter 53. If the initial state is P rather than G 
or Z, then the state of signal n is compared with that of signal n+1. If 
the comparison is TRUE, a signal is sent to shifter 52 to continue the 
shifting operation on the operands A and B. If the comparison is NOT TRUE, 
then a signal is output to the shifter 52 to produce one more shift and a 
subsequent signal is output to adjuster 54 to send an adjustment signal to 
the counter 53. Following the receipt of an adjustment signal, the counter 
53 outputs a signal, indicative of the sum of the counts and the 
adjustment signal, to the shifter 20 which then proceeds to normalize the 
sum of the operands A and B, all in a manner as has been described in 
detail above. 
It will accordingly be seen that a system and method have been disclosed to 
facilitate a computerized floating-point addition by performing a leading 
0/1 anticipation (LZA) in parallel with the addition operation, so that 
the Addition-Normalization time may be significantly reduced. The 
invention may be incorporated in various electronic processing equipment 
components, e.g., either CPUs or peripherals. Also, modifications and 
simplifications of the basic implementing network have been described 
generally and particularly for special cases in a manner that will permit 
those skilled in the art to fully utilize the teachings in ways not 
specifically described.