Primitive cell method for front end physical design

A method for forming an integrated circuit (280) comprises accessing (282) a library of primitive cells and edge codes in the formation of an integrated circuit layout. At least one edge code of at least one previously placed primitive cell (284) of the integrated circuit layout is used. A primitive cell is selected (286) from the library that is compatible with the at least one previously placed primitive cell and the selected primitive cell is placed into the integrated circuit layout adjacent the at least one previously placed primitive cell. The integrated circuit is manufactured (290) using the integrated circuit layout.

BACKGROUND

The present disclosures relate to integrated circuit manufacturing, and more particularly, to a primitive cell method for front end physical design for integrated circuit manufacturing.

Problems exist in the current designing and building of electronic systems in integrated circuits. These problems include, but are not limited to, (1)complex front-end design rules, (2) complexity and inaccuracy of translating written design rules into Design Rule Check (DRC) code, (3) difficulty or impossibility to achieve one hundred percent (100%) coverage with DRC Quality Assurance (QA) cells, (4) an inability of layout designers to comprehend written rules, wherein a corresponding layout is performed by trial-and-error, and layout checking is performed with (imperfect) DRC decks that correspond to machine readable code of the design rules, (5) an inaccuracy of front-end device models with respect to silicon due to small layout variations, (6) transistor variability on chip due to randomness in physical design, (7) 65 nm and beyond process requires post-layout extraction to comprehend non-local effects (stressors, etc.) on front-end device models, and (8) irregular front-end layout practices complicate the generation of derived layers (e.g., stressor films), and create unexpected flaws such as slivers/gaps.

With current layout design proposals, variations in layout style increase variability in device electrical behavior. Neighboring structures within the layout have an increasing effect on electrical behavior and complicates modeling. Current methods to comprehend these effects require the use of very complex post-layout extraction to back annotate models for simulation. Even with the post layout extraction, the ability of the models to accurately represent the electrical behavior of all devices is poor. Furthermore, design rules are increasing in complexity so rapidly that existing paradigms cannot continue to handle them.

Accordingly, there is a need for an improved method and apparatus for overcoming the problems in the art as discussed above.

DETAILED DESCRIPTION

FIG. 1is a schematic expanded layout view10of primitive cells of a portion of a physical design layout, the primitive cells having a same size dimension (i.e., length and width) and including partial-layout features according to one embodiment of the present disclosure. InFIG. 1, the primitive cells are generally indicated by reference numerals12,14,16and18. Primitive cell12includes four side edges20,22,24, and26. Each side edge of the primitive cell is characterized by a predetermined edge code, to be discussed further herein. Primitive cell12further includes partial-layout features28,30,32, and34. Furthermore, a portion of primitive cell12includes a region or feature other than partial-layout features, generally indicated by reference numeral36.

As discussed herein, the partial-layout features are representative of one or more portions of a semiconductor device of an integrated circuit. In other words, a partial-layout feature by itself would not suffice as a functional portion of a semiconductor device of an integrated circuit. InFIG. 1, the primitive cell12is representative of a portion of a transistor layout, wherein partial-layout feature28is representative of a portion of a gate electrode. The gate electrode comprises any suitable electrode material or stack of materials selected according to the requirements of a given transistor device application. For example, the gate electrode may comprise polysilicon.

The partial-layout feature30is representative of a portion of a gate electrode contact. The gate electrode contact comprises any suitable contact material or materials selected according to the requirements of a given transistor device application. For example, the gate electrode contact may comprise tungsten. The partial-layout feature32is representative of a portion of an active region of the transistor device, in particular, a source/drain region. The active region comprises any suitable semiconductor material or materials selected according to the requirements of a given transistor device application. For example, the active region may comprise silicon, germanium, gallium arsenide, combinations thereof, and/or strained versions of the same, etc.

The partial-layout feature34is representative of a portion of an active area contact. The active area contact comprises any suitable contact material or materials selected according to the requirements of a given device application. For example, the active area contact may comprise tungsten. The portion of primitive cell12indicated by reference numeral36is representative of a portion of an isolation region, which is a region or feature other than a partial-layout feature. The isolation region comprises any suitable isolation material or materials selected according to the requirements of a given transistor device application. For example, the isolation region may comprise an oxide.

Further with respect to primitive cell12ofFIG. 1, several dimensions are illustrated by reference numerals38,40and42. Dimension38is representative of a partial gate length of a gate electrode. Dimension40is representative of a length of a source/drain extension, beyond the gate electrode. Dimension42is representative of a portion of an isolation region36within primitive cell12. In particular, dimension42comprises a dimension that is defined according to a design rule regarding the spacing between adjacent active regions. Accordingly, when primitive cell12is coupled to another cell at edge20, there is provided an appropriate isolation between adjacent active regions according to the design rules for the given technology.

Further with respect toFIG. 1, primitive cell14includes four side edges50,52,54, and56. Each side edge of the primitive cell is characterized by a predetermined edge code, as will be discussed further herein. Primitive cell14further includes partial-layout features58,60, and62. Furthermore, a portion of primitive cell14includes a region or feature other than partial-layout features, generally indicated by reference numeral64.

The primitive cell14is representative of another portion of a transistor layout, wherein partial-layout feature58is representative of a portion of a gate electrode. As discussed above, the gate electrode comprises any suitable electrode material or stack of materials selected according to the requirements of a given transistor device application. The partial-layout feature60is representative of a portion of an active region of the transistor device, in particular, a source/drain region. As discussed above, the active region comprises any suitable semiconductor material or materials selected according to the requirements of a given transistor device application. The partial-layout feature62is representative of a portion of an active area contact. As discussed above, the active area contact comprises any suitable contact material or materials selected according to the requirements of a given transistor device application. Furthermore, the portion of primitive cell14indicated by reference numeral64is representative of a portion of an isolation region, which is a region or feature other than a partial-layout feature. As discussed above, the isolation region comprises any suitable isolation material or materials selected according to the requirements of a given device application.

Further with respect to primitive cell14ofFIG. 1, several dimensions are illustrated by reference numerals66,68and70. Dimension66is representative of a partial gate length of a gate electrode. Dimension68is representative of a length of a source/drain extension, beyond the gate electrode. Dimension70is representative of a portion of an isolation region64within primitive cell14. In particular, dimension70comprises a dimension that is defined according to a design rule regarding the spacing between adjacent active regions. Accordingly, when primitive cell14is coupled to another cell at edge50, there is provided an appropriate isolation between adjacent active regions according to the design rules for the given technology.

Primitive cell16is similar to primitive cell12, for example, primitive cell16includes four side edges80,82,84, and86. Each side edge of the primitive cell is characterized by a predetermined edge code, as will be discussed further herein. Primitive cell16further includes partial-layout features88,90,92, and94. Furthermore, a portion of primitive cell16includes a region or feature other than a partial-layout feature, generally indicated by reference numeral96. Primitive cell16is representative of another portion of a transistor layout, wherein partial-layout feature90is representative of a portion of a gate electrode. The gate electrode comprises any suitable electrode material or stack of materials selected according to the requirements of a given transistor device application.

The partial-layout feature88is representative of a portion of a gate electrode contact. The gate electrode contact comprises any suitable contact material or materials selected according to the requirements of a given device application. The partial-layout feature92is representative of a portion of an active region of the transistor device, in particular, a source/drain region. The active region comprises any suitable semiconductor material or materials selected according to the requirements of a given transistor device application. The partial-layout feature94is representative of a portion of an active area contact. The active area contact comprises any suitable contact material or materials selected according to the requirements of a given transistor device application. The portion of primitive cell16indicated by reference numeral96is representative of a portion of an isolation region, which is a region or feature other than a partial-layout feature. The isolation region comprises any suitable isolation material or materials selected according to the requirements of a given transistor device application.

Further with respect to primitive cell16ofFIG. 1, several dimensions are illustrated by reference numerals98,100and102. Dimension98is representative of a partial gate length of a gate electrode. Dimension100is representative of a length of a source/drain extension, beyond the gate electrode. Dimension102is representative of a portion of an isolation region96within primitive cell16. In particular, dimension102comprises a dimension that is defined according to a design rule regarding the spacing between adjacent active regions. Accordingly, when primitive cell16is coupled to another cell at edge84, there is provided an appropriate isolation between adjacent active regions according to the design rules for the given technology.

Primitive cell18is similar to primitive cell14, for example, primitive cell18includes four side edges110,112,114, and116. Each side edge of the primitive cell is characterized by a predetermined edge code, as will be discussed further herein. Primitive cell18further includes partial-layout features118,120, and122. Furthermore, a portion of primitive cell18includes a region or feature other than a partial-layout feature, generally indicated by reference numeral124.

The primitive cell18is representative of another portion of a transistor layout, wherein partial-layout feature118is representative of a portion of a gate electrode. As discussed above, the gate electrode comprises any suitable electrode material or stack of materials selected according to the requirements of a given device application. The partial-layout feature120is representative of a portion of an active region of the transistor device, in particular, a source/drain region. As discussed above, the active region comprises any suitable semiconductor material or materials selected according to the requirements of a given transistor device application. The partial-layout feature122is representative of a portion of an active area contact. In addition, as discussed above, the active area contact comprises any suitable contact material or materials selected according to the requirements of a given transistor device application. Furthermore, the portion of primitive cell18indicated by reference numeral124is representative of a portion of an isolation region, which is a region or feature other than a partial-layout feature. Moreover, as discussed above, the isolation region comprises any suitable isolation material or materials selected according to the requirements of a given transistor device application.

Further with respect to primitive cell18ofFIG. 1, several dimensions are illustrated by reference numerals126,128and130. Dimension126is representative of a partial gate length of a gate electrode. Dimension128is representative of a length of a source/drain extension, beyond the gate electrode. Dimension130is representative of a portion of an isolation region124within primitive cell18. In particular, dimension130comprises a dimension that is defined according to a design rule regarding the spacing between adjacent active regions. Accordingly, when primitive cell18is coupled to another cell at edge114, there is provided an appropriate isolation between adjacent active regions according to the design rules for the given technology.

As discussed above with respect to the primitive cells ofFIG. 1, each edge is characterized by a predetermined edge code. In one embodiment, the edge code for a corresponding edge comprises computer readable code that provides compatibility information with respect to that edge of the primitive cell. Compatibility information comprises information for identification of edges of other primitive cells that the instant cell can be adjacent to in a layout, thus insuring the generation of an error free layout. For illustration purposes, edge codes are represented various letters/numerals A1, B1, C1, D1, E1, F1, G1, and H1are shown inFIG. 1.

According to one embodiment, primitive front-end layout elements (also referred to as primitive cells) are provided, which can constitute, for example, portions of transistors or other devices (e.g., passive or active). The primitive cells have edges that are coded in a manner such that only the intended abutment possibilities are allowed. The allowed abutments are designed as a function of or based upon the intended process technology capability, such that correct placement/abutment of the primitive cells guarantees a design rule clean layout.

FIG. 2is a schematic layout view of the primitive cells of the physical design layout ofFIG. 1coupled together based upon edge code compatibility, according to one embodiment of the present disclosure. In particular, in response to a determination of an edge code compatibility, side edge22of primitive cell12couples with side edge56of primitive cell14. Side edge54of primitive cell14couples with side edge110of primitive cell18. Side edge116of primitive cell18couples with side edge82of primitive cell16. In addition, side edge80of primitive cell16couples with side edge24of primitive cell12. As a result of the coupling together based upon edge code compatibility, partial-layout features34and62together form a full-layout active area contact feature. Partial-layout features32and60together form a full-layout active region feature, such as a source/drain region. Partial-layout features94and122together form another full-layout active area contact feature. In addition, partial-layout features92and120together form another full-layout active region feature, such as a source/drain region. Furthermore, partial-layout features28,58,90and118together form a substantially complete full-layout gate electrode feature, wherein the gate electrode feature has a width dimension which is the sum of dimensions38and98(or66and126). Still further, partial-layout features30and88together form a partially complete full-layout gate electrode contact feature.

FIG. 3is a schematic expanded layout view140of primitive cells of another physical design layout, the primitive cells each having a same size and including partial-layout features as well as full-layout features according to another embodiment of the present disclosure. The layout view ofFIG. 3is similar to that ofFIG. 1, with the following differences. InFIG. 3, the primitive cells are generally indicated by reference numerals142,144,16and18. Primitive cell142includes four side edges20,22,24, and26. Each side edge of the primitive cell is characterized by a predetermined edge code, for example, represented by B1, F3, A1and E1. Primitive cell142further includes both partial-layout features (28,30and32) and a full-layout feature (146). Furthermore, a portion of primitive cell142includes a region or feature other than partial-layout features, generally indicated by reference numeral36.

As discussed herein, the partial-layout features are representative of one or more portions of a semiconductor device of an integrated circuit. In other words, a partial-layout feature by itself would be insufficient to suffice as a functional portion of a semiconductor device of an integrated circuit. In addition, a full-layout feature is representative of a functional portion of a semiconductor device. InFIG. 3, the primitive cell142is representative of a portion of a transistor layout, wherein partial-layout feature28is representative of a portion of a gate electrode, partial layout feature30is representative of a portion of a gate electrode contact, and partial-layout feature32is representative of a portion of an active region of the transistor device, in particular, a source/drain region. The full-layout feature146is representative of an active area contact. The active area contact comprises any suitable contact material or materials selected according to the requirements of a given device application. For example, the active area contact may comprise tungsten.

Further with respect toFIG. 3, primitive cell144includes four side edges50,52,54, and56. Each side edge of the primitive cell is characterized by a predetermined edge code, for example, represented by D1, G1, C1and F3. Primitive cell144further includes both partial-layout features (58and60) and a full-layout feature (148). Furthermore, a portion of primitive cell144includes a region or feature other than partial-layout features, generally indicated by reference numeral64.

The primitive cell144is representative of another portion of a transistor layout, wherein partial-layout feature58is representative of a portion of a gate electrode, and the partial-layout feature60is representative of a portion of an active region of the transistor device, in particular, a source/drain region. The full-layout feature148is representative of an active area contact. As discussed above, the active area contact comprises any suitable contact material or materials selected according to the requirements of a given transistor device application. In addition, primitive cells16and18are as discussed herein above with respect toFIG. 1.

As discussed above with respect to the primitive cells ofFIG. 1, each edge is characterized by a predetermined edge code. In one embodiment, the edge code for a corresponding edge comprises computer readable code that provides compatibility information with respect to that edge of the primitive cell. Compatibility information comprises information for identification of edges of other primitive cells that the instant cell can be adjacent to in a layout, thus insuring the generation of an error free layout. For illustration purposes, edge codes are represented various letters/numerals A1, B1, C1, D1, E1, F1, G1, and H1are shown inFIG. 1.

FIG. 4is a schematic expanded layout view150of primitive cells of yet another physical design layout, the primitive cells comprising one or more different sizes and including one or more (i) partial-layout features and/or (ii) full-layout features, according to yet another embodiment of the present disclosure. The layout view150ofFIG. 4is similar to those ofFIGS. 1 and 3, with various differences as explained in the following. InFIG. 4, the primitive cells are generally indicated by reference numerals152,154,156,158,160,162,164and166. Each primitive cell includes four side edges, wherein each side edge of the primitive cell is characterized by a predetermined edge code. Edge codes are illustrated inFIG. 4, for example, represented by B1, F3, A1, E1, D1, G1, C1, I4, A4, E4, G4, C4, H4, E4, G4and F4.

Primitive cell152includes both partial-layout features (174,176and178) and a full-layout feature (180). Furthermore, a portion of primitive cell152includes a region or feature other than partial-layout or full-layout features, generally indicated by reference numeral182. InFIG. 4, the primitive cell152is representative of a portion of a transistor layout, wherein partial-layout feature176is representative of a portion of a gate electrode, partial layout feature174is representative of a portion of a gate electrode contact, and partial-layout layout feature178is representative of a portion of an active the transistor device, in particular, a source/drain region. The full-layout feature180is representative of an active area contact. Region182is representative of an isolation region.

Primitive cell154includes both partial-layout features (184and188) and a full-layout feature (186). Furthermore, a portion of primitive cell154includes a region or feature other than partial-layout or full-layout features, generally indicated by reference numeral190. InFIG. 4, the primitive cell154is representative of a portion of a transistor layout, wherein partial-layout feature184is representative of a portion of a gate electrode and partial-layout feature188is representative of a portion of an active region of the transistor device. The full-layout feature186is representative of an active area contact. Region190is representative of an isolation region.

Primitive cell156includes partial-layout features (192,194and196). In addition, a portion of primitive cell156includes a region or feature other than partial-layout or full-layout features, generally indicated by reference numeral198. InFIG. 4, the primitive cell156is representative of a portion of a transistor layout, wherein partial-layout feature192is representative of a portion of a gate electrode, partial-layout feature194is representative of a portion of an active region of the transistor device, and partial-layout feature196is representative of a portion of an active area contact. Region198is representative of an isolation region. Primitive cell158is similar to primitive cell156. In particular, partial-layout features (204,202and200) of primitive cell158are similar to partial-layout features (192,194and196) of primitive cell156, respectively. In addition, region206of primitive cell158is similar to region198of primitive cell156.

Primitive cell160is similar to primitive cell154. In particular, the partial-layout features (208and212) and full-layout feature (210) of primitive cell160are similar to the partial-layout features (184and188) and full-layout feature (186) of primitive cell154, respectively. In addition, region214of primitive cell160is similar to region190of primitive cell154.

Primitive cell162is similar to primitive cell152. In particular, the partial-layout features (216,218and222) and full-layout feature (220) of primitive cell162are similar to the partial-layout features (174,176and178) and full-layout feature (180) of primitive cell152, respectively. In addition, region224of primitive cell162is similar to region182of primitive cell152.

Primitive cell164includes partial-layout features (226,228,230and232). In addition, a portion of primitive cell164includes a region or feature other than partial-layout or full-layout features, generally indicated by reference numeral234. InFIG. 4, the primitive cell164is representative of a portion of a transistor layout, wherein partial-layout feature226is representative of a portion of a gate electrode contact, partial-layout feature228is representative of a portion of a gate electrode, partial-layout feature230is representative of a portion of an active region of the transistor device, and partial-layout feature232is representative of a portion of an active area contact. Region234is representative of an isolation region. Primitive cell166is similar to primitive cell164. In particular, partial-layout features (242,240,238and236) of primitive cell166are similar to partial-layout features (226,228,230and232) of primitive cell164, respectively. In addition, region244of primitive cell166is similar to region234of primitive cell164.

Further with respect toFIG. 4, primitive cell152has length and width dimensions that are indicated by reference numerals170and172, respectively. In one embodiment, the length and width dimensions of a given primitive cell are not equal. In another embodiment, the length and width dimension of a given primitive cell are equal. Further as illustrated inFIG. 4, a length dimension250of primitive cell166is equal to the length dimension170of primitive cell152. Further as shown inFIG. 4, the layout150includes primitive cells of differing dimensions.

FIG. 5is a flowchart view260of a method of creating primitive cells, generating edge codes, and generating a library of primitive cells with edge codes according to one embodiment of the present disclosure. To begin, step262includes obtaining technology specification and design rules for a given semiconductor technology. In step264, the method includes creating primitive cells. In step266, the method includes generating edge codes as a function of primitive cells per technology specifications and design rules. In step268, the method includes a query of whether the primitive cells provide a desired coverage. If not, then the method returns to step264and continues with creation of an additional one or more primitive cells. If in step268, the created primitive cells provide the desired coverage, then the process proceeds to step270. In step270, the method includes generating a library of primitive cells with edge codes and then ends.

FIG. 6is a flowchart view280of a method of generating an integrated circuit layout using primitive cells with edge codes in the manufacturing of an integrated circuit according to another embodiment of the present disclosure. To begin, step282includes accessing a library of primitive cells with edge codes. In step284, the method includes selecting and placing a first primitive cell from the library in the formation of an integrated circuit layout. In step286, the method includes selecting and placing a subsequent primitive cell from the library that is compatible with one or more previously placed cells based on edge codes in the formation of the integrated circuit layout. In step288, the method includes a query of whether the integrated circuit layout is complete. If not, then the method returns to step286and continues with selecting and placing a subsequent primitive cell from the library. If in step288, the integrated circuit layout is complete, then the process proceeds to step290. In step290, the method includes manufacturing the integrated circuit per the integrated circuit layout and then ends.

As disclosed herein, in one embodiment a method for forming an integrated circuit comprises accessing a library of primitive cells and edge codes in the formation of an integrated circuit layout. Using at least one edge code of at least one previously placed primitive cell of the integrated circuit layout, the method includes selecting a primitive cell from the library that is compatible with the at least one previously placed primitive cell and placing the selected primitive cell into the integrated circuit layout adjacent the at least one previously placed primitive cell. The integrated circuit is subsequently manufactured according to or with use of the integrated circuit layout. In one embodiment, the edge codes provide compatibility information with respect to edges of the primitive cells. In another embodiment, prior to manufacturing the integrated circuit, the method further comprises repeating the selecting and placing. Furthermore, in another embodiment, for a given integrated circuit layout, edge codes of abutting edges of previously placed primitive cells indicate that the abutting edges are compatible. Still further, at least a subset of the primitive cells in the library includes a partial layout feature which is representative of a portion of a semiconductor device of the integrated circuit.

According to another embodiment, a method for forming an integrated circuit comprises selecting a first primitive cell from a library having a plurality of primitive cells, each of the plurality of primitive cells having at least one corresponding edge code. The first primitive cell is placed in the formation of an integrated circuit layout. A second primitive cell is selected from the library. The second primitive cell is placed adjacent the first primitive cell in the integrated circuit layout, wherein at least one edge code of the first primitive cell is compatible with at least one edge code of the second primitive cell. The integrated circuit is subsequently manufactured using the integrated circuit layout. In addition, the at least one edge code corresponding to each of the plurality of primitive cells provides compatibility information with respect to at least one edge of the each of the plurality of primitive cells.

In another embodiment, the first primitive cell has a first edge and a corresponding first edge code and the second primitive cell has a first edge and a corresponding first edge code. Placing the second primitive cell adjacent the first primitive cell comprises placing the first edge of the first primitive cell adjacent the first edge of the second primitive cell, wherein the first edge code of the first primitive cell is compatible with the first edge code of the second primitive cell. In another embodiment, each of the plurality of primitive cells in the library comprises a plurality of edges, wherein each of the plurality of edges have an edge code associated therewith which provides edge compatibility information.

In yet another embodiment, the method of forming an integrated circuit, prior to manufacturing the integrated circuit, further comprises using at least one edge code of at least one of the first primitive cell or the second primitive cell to select a third primitive cell from the library and placing the third primitive cell adjacent the at least one of the first primitive cell or the second primitive cell in the integrated circuit layout. At least one edge code of the third primitive cell is compatible with at least one edge code of the at least one of the first primitive cell or the second primitive cell. In addition, each of the plurality of primitive cells can comprise at least one partial layout feature corresponding to a portion of a semiconductor device of the integrated circuit.

The first primitive cell can comprise a first partial layout feature corresponding to a first portion of a semiconductor device of the integrated circuit, and the second primitive cell can comprise a second partial layout feature corresponding to a second portion of the semiconductor device of the integrated circuit. In one embodiment, the first portion and the second portion of the semiconductor device do not complete the semiconductor device. In another embodiment, each of the plurality of primitive cells has a same height and each of the plurality of cells has a same width. In a further embodiment, selecting the second primitive cell comprises using the at least one edge code of the first primitive cell to select the second primitive cell.

According to yet another embodiment, a method for forming an integrated circuit comprises selecting a first primitive cell from a library having a plurality of primitive cells. The first primitive cell can include a partial layout feature representative of a first portion of a semiconductor device of the integrated circuit, and a plurality of edges, each edge of the plurality of edges having a corresponding edge code. The method further includes placing the first primitive cell in the formation of an integrated circuit layout. A second primitive cell is selected from the library, the second primitive cell including a partial layout feature representative of a second portion of the semiconductor device of the integrated circuit, and a plurality of edges, each edge of the plurality of edges having a corresponding edge code. The second primitive cell is placed in the integrated circuit layout, wherein a first edge of the second primitive cell is adjacent a first edge of the first primitive cell, and a first edge code of the first edge of the second primitive cell is compatible with a first edge code of the first edge of the first primitive cell. Subsequently, the integrated circuit is manufactured according to or using the integrated circuit layout.

According to further embodiments, selecting the second primitive cell can comprise using the first edge code of the first edge of the first primitive cell to select the second primitive cell. In another embodiment, the first portion and the second portion complete the semiconductor device. In another embodiment, the first portion and the second portion do not complete the semiconductor device, wherein additional portions are needed to complete the semiconductor device. In a further embodiment, the first primitive cell has a same height as a height of the second primitive cell and a same width as a width of the second primitive cell.

The method according to the embodiments of the present disclosure improves a speed of physical design. For example, place-and-route tools could be used at the primitive level, since Design-for-manufacturability practices would be designed into the primitives. In another example, if higher level cells or a custom layout is done, then manual CAD tools could be configured to do real time abutment check. The relative simplicity of abutment rules, compared to layer-by-layer layout rules, enables such real-time checking during manual layout. Furthermore, the primitive cells and their abutment rules constrain the spectrum of pitches and spaces to discrete values. These discrete values would be reflected in the front-end models, and would obviate the need for post-layout extraction for the front-end simulation models to comprehend proximity effects of stressors, etc.

The primitive cell design according to the embodiments of the present disclosure addresses and resolves various process related issues. For example, in the present art, design rules are written, however complex, and then translated into a CAD tool language for automated checking. Besides the requirement for a design to not violate design rules, the layout has tended to be irregular. Current methods for simulating front-end devices with arbitrary (albeit, design rule clean) layouts is to extract the physical spaces and pitches, and feed the extracted values back into the simulation environment. In contrast, the embodiments of the present disclosure restrict the physical layout to discrete values, and more particularly, provide exact physical layout primitives or primitive cells. As a result, the predictability and accuracy of simulated design performance is improved. Furthermore, the embodiments of the present disclosure can be used to provide a front-end physical design (layout) for any technology.

The embodiments of the present disclosure thus address the problems of the prior art variations on a wafer due to layout, and overcome difficulties in modeling the electrical behavior due to layout variations. In addition, the embodiments of the present disclosure relate to primitive cells, compared with other types of cells that are at a minimum, a complete device or set of interconnected devices.

The embodiments of the present disclosure can be useful for anyone who manufactures or designs semiconductor products, as well as those who provide CAD tools and associated libraries. In addition, the embodiments of the present disclosure can be implemented as a new level of library cells. Furthermore, the embodiments of the present disclosure enable physical layout itself to be a quicker process and one that is less prone to error than prior known layout techniques.

Still further, the embodiments of the present disclosure relate to non-functional primitive cells that are technology independent and that solve the problems in the art as listed herein. The embodiments include a method wherein a front-end integrated circuit or semiconductor device layout can be done using pre-defined primitive elements, which can constitute, for example, small portions of transistors. The primitive cells include edge tagged cells, such that only the intended abutment possibilities are allowed. The allowed abutments are based on a process capability such that correct placement/abutment of the primitive cells guarantees a manufacture-able layout by construction. In addition, place-and-route tools could be used for the manufacturing of an integrated circuit according to the embodiments of the present disclosure, since best design-for-manufacturability practices would be built into the primitive cells. For higher level standard cells or custom layout, manual CAD tools could be configured to do real-time check of the relatively simple abutment rules. Furthermore, the primitive cells and their corresponding abutment rules would constrain all pitches and spaces. The small number of configurations would be captured in the front end models, and would obviate the need for post-layout extraction for the front end models to comprehend proximity effects of stressors, etc.

The embodiments of the present disclosure include front end physical design (layout) primitive cells assembled into a library. The primitive cell edges are tagged with allowed abutments and, when joined, form complete functional devices such as transistors. The primitive cells can be pieced together either through automated place and route, or manually, to achieve the final physical design. In response to being placed consistently with the edge tagging, the layout is guaranteed by construction to meet all design rules. As described herein, the primitive elements by themselves are not electrically functional. The embodiments discussed herein enable physical designs that minimize variation and enables accurate modeling. This is accomplished by encoding the edges of primitive cells with allowed abutment or placement information. Primitive layout elements which can be assembled to form electrically functional circuit elements (e.g., transistors) include layout elements having edges that are coded with allowed or forbidden placement information, and which ensure the resulting layout is design rule compliant. The embodiments of the present disclosure enable more manufacturable designs to be generated that are more likely to behave electrically as they do in design (i.e., via simulation).