Lead-free alloys for column/ball grid arrays, organic interposers and passive component assembly

A lead free solder hierarchy structure for electronic packaging that includes organic interposers. The assembly may also contain passive components as well as underfill material. The lead free solder hierarchy also provides a lead free solder solution for the attachment of a heat sink to the circuit chip with a suitable lead free solder alloy.

BACKGROUND OF INVENTION

The present invention is directed to electronic packaging and, more particularly, is directed to a lead free solder composition for the assembly of passive components and organic substrates with conventional ceramic packages.

A chip carrier may be attached to a circuit board by a ball grid array (BGA) or column grid array (CGA) comprising solder alloys. Such solder alloys have typically comprised an eutectic alloy composition of Pb/Sn. The chip carrier is typically a ceramic substrate carrying semiconductor chips. The BGA consists of an array of solder balls which are soldered to connecting pads on both the circuit board and the substrate.

U.S. Pat. No. 6,333,563 (Jackson et al.), the disclosure of which is incorporated herein by reference, teaches an organic interposer attached to a ceramic module using a high modulus underfill material. The organic interposer is then joined to an organic board. This assembly increases the fatigue life of the BGA electrical interconnection. The assembly uses standard Pb/Sn solders well known in the art.

For various reasons, however, the Industry is moving to a lead free solder strategy for component assembly. Any lead free interconnect structure will need to accommodate the various solder joint hierarchy temperatures involved. This will include not only conventional chip join and ball grid array to card assembly, but also organic interposer and passive component assembly as well.

Another problem addressed by the present invention relates to cooling the circuit chips. A current thermal solution for cooling circuit chips is to solder a heat sink to the chip. The preferred solder is eutectic PbSn or some combination of Pb and Sn depending on the temperature requirements of the various module interconnect components. As the industry migrates to lead free solder, this soldered chip/heat sink interface is an important consideration in solder hierarchy structure because the heat sink is typically attached to the chip prior to second level module to card assembly.

Accordingly, it is a purpose of the present invention to provide a lead free solder hierarchy structure for electronic packaging that includes organic interposers.

It is another purpose of the present invention to provide a lead free solder hierarchy structure for electronic packaging that includes passive components such as capacitors and resistors.

It is another purpose of the present invention to provide a lead free solder solution for the attachment of a heat sink to the circuit chip.

These and other purposes of the present invention will become more apparent after referring to the following description considered in conjunction with the accompanying drawings.

SUMMARY OF INVENTION

The features of the invention believed to be novel and the elements characteristic of the invention are set forth with particularity in the appended claims. The Figures are for illustration purposes only and are not drawn to scale. The invention itself, however, both as to organization and method of operation, may best be understood by reference to the detailed description which follows taken in conjunction with the accompanying drawings.

According to a first aspect of the invention there is provided a solder interconnect structure for electronic package interconnections comprising:

at least one electronic circuit chip attached to a top surface of a chip carrier with a first array of solder connections, the first array of solder connections having a first lead free off-eutectic solder composition;

a second array of solder connections attached to a bottom surface of the chip carrier, the second array of solder connections having a second lead free off-eutectic solder composition, the second lead free off-eutectic solder composition having a lower liquidus temperature than the first lead free off-eutectic solder composition;

an organic interposer having a top surface attached to the second array of solder connections;

a third array of solder connections attached to a bottom surface of the organic interposer, the third array of solder connections having a third lead free off-eutectic solder composition, the third lead free off-eutectic solder composition having a lower liquidus temperature than the second lead free off-eutectic solder composition; and

a circuit board having a top side attached to the third array of solder connections to create a solder interconnect structure.

The organic interposer to circuit board solder connection may alternatively be an approximately eutectic Sn/Pb solder composition. The structure may also contain passive components and underfill material at the chip to chip carrier and chip carrier to interposer interfaces.

According to another aspect of the invention, there is provided a solder interconnect structure for electronic package interconnections comprising: at least one electronic circuit chip attached to a top side of a chip carrier with a first array of solder connections, the first array of solder connections having a first lead free off-eutectic solder composition;

a second array of solder connections having a first end attached to a bottom surface of the chip carrier with a second lead free off-eutectic solder composition, the second lead free off-eutectic solder composition having a lower liquidus temperature than the first lead free off-eutectic solder composition;

an organic interposer having a top surface attached to a second side of the second array of solder connections by a third lead free off-eutectic solder composition, the third lead free off-eutectic solder composition having a lower liquidus temperature than the second lead free off-eutectic solder composition;

a third array of solder connections attached to a bottom surface of the organic interposer, the third array of solder connections having a fourth lead free off-eutectic solder composition, the fourth lead free off-eutectic solder composition having a lower liquidus temperature than the third lead free off-eutectic solder composition;

and a circuit board having a top surface attached to the third array of solder connections to create a solder interconnect structure.

The organic interposer to circuit board solder connection may alternatively be an approximately eutectic Sn/Pb solder composition.

According to another aspect of the invention, there is provided a solder hierarchy structure for electronic package interconnections comprising:

an electronic module;

an array of solder columns having a first end attached to a bottom side of the module with a lead free solder composition; and

a circuit board having a top side attached to a second end of the array of solder columns by a Sn/Pb solder composition.

According to another aspect of the invention, there is provided a lead free solder structure for attaching a heat sink to a circuit chip comprising:

a circuit chip;

metallized layers on the chip;

a heat sink;

metallized layers on the heat sink; and

a lead free solder connecting the heat sink to the chip.

DETAILED DESCRIPTION

The purposes of the present invention have been achieved by providing, according to the present invention, a variety of solder interconnect structures employing a lead free solder temperature hierarchy which enables lead free solder solutions to be applied to complex module assemblies including organic interposers, heat sinks, and passive components.

The present invention employs the use of lead free solder alloys. In one embodiment an off-eutectic solder composition of between 90.0-99.0 weight % Sn, between 10.0-1.0 weight % Cu, and having inter-metallics with a melting temperature above 280° C. Preferred embodiments are 93Sn/7Cu and 97Sn/3Cu, both compositions having dispersed grains of SnCu inter-metallic phase structure.

In another embodiment an off-eutectic solder composition of between 70.0-96.0 weight % Sn, between 30.0-4.0 weight % Ag, and having inter-metallics with a melting temperature above 280° C. Preferred embodiments are 72Sn/28Ag, 78Sn/22Ag and 82Sn/18Ag, all compositions having dispersed grains of SnAg inter-metallic phase structure.

A first embodiment of the present invention will be discussed with reference to FIG.1. At least one circuit chip10is attached to a top surface of a chip carrier20with a first array of solder connections30. In this embodiment the first array of solder connections30are comprised of a lead free off-eutectic solder composition. In a preferred embodiment the first array of solder connections30are a composition of about 72.0 weight % Sn and 28.0 weight % Ag, having dispersed grains of SnAg inter-metallic phase structure and a liquidus temperature of approximately 400° C.

A second array of solder connections40is used to attach the chip carrier20to an organic interposer50. In this embodiment the second array of solder connections40are comprised of a lead free off-eutectic solder composition having a lower liquidus temperature than the first array of solder connections30. In a preferred embodiment the second array of solder connections40are a composition of about 78.0 weight % Sn and 22.0 weight % Ag, having dispersed grains of SnAg Inter-metallic phase structure and a liquidus temperature of approximately 375° C.

A third array of solder connections60is used to attach the organic interposer50to a printed circuit board70. In this embodiment the third array of solder connections60are comprised of a lead free off-eutectic solder composition having a lower liquidus temperature than the second array of solder connections40. In a preferred embodiment the third array of solder connections60are a composition of about 95.5 weight % Sn and about 3.8 weight % Ag and about 0.7 weight % Cu and has a liquidus temperature of approximately 217° C. The organic interposer50is preferably fabricated from a material which has an expansion coefficient similar to the circuit board70. For example, the organic interposer50, or the circuit board70, could consist of FR4, FR4 with surface laminate circuits, or organic carriers with at least one metal and at least one polyimide layer.

In a preferred embodiment, the solder interconnect structure may also have a first underfill encapsulation material80surrounding the first array of solder connections30. Additionally, the solder interconnect structure may have a second underfill encapsulation material90surrounding the second array of solder connections40. The underfill material80,90is preferably a high modulus material which couples the chip10to the chip carrier20or the organic interposer50to the chip carrier20and limits the ability to expand freely. Examples of commercially available underfill material are Hysol 4526 from Dexter and 8800 series underfill from Johnson Mathey.

The solder interconnect structure may also consist of passive components100attached to the chip carrier20. Typical passive components include capacitors, resistors and thermistors. In this embodiment the passive components100are attached to the chip carrier20with a lead free off-eutectic solder composition110having a liquidus temperature lower than the first array of solder connections30. In a preferred embodiment, the solder composition110is about 78.0 weight % Sn and 22.0 weight % Ag, and has dispersed grains of SnAg inter-metallic phase structure and a liquidus temperature of approximately 375° C. In another preferred embodiment the solder composition110is 78Sn/22Ag but the second array of solder connections40are comprised of a lead free off-eutectic solder composition of about 82.0 weight % Sn and 18.0 weight % Ag, having dispersed grains of SnAg inter-metallic phase structure and a liquidus temperature of approximately 355° C.

The solder connections30,40and60shown inFIG. 1are solder balls. However the present invention is not limited to solder balls and it will be appreciated by those skilled in the art that these solder connections may also be “columns”, “springs”. “s-connectors”, “c-connectors”, “cantilever beams” or any solder joint assembly.

The solder interconnect structure shown inFIG. 1is not limited to an all lead free off-eutectic solder assembly. For example, the passive components100may be attached to the chip carrier20with a Sn/Pb solder composition having a liquidus temperature lower than the liquidus temperature of the first array of solder connections30. Alternatively, either a Sn/Bi or a Sn/In solder composition having a liquidus temperature lower than the liquidus temperature of the first array of solder connections30may also be used. In addition, the third array of solder connections60may consist of a eutectic Sn/Pb solder composition61. In a preferred embodiment the Sn/Pb solder composition is a eutectic composition of approximately 63.0 weight % Sn and 37.0 weight % Pb. However a slightly off-eutectic Sn/Pb solder composition in the range of approximately 58 to 70 weight % Sn and approximately 42 to 30 weight % Pb may be used as well.

Referring now toFIG. 2there is shown a solder interconnect structure, including passive components, but without an organic interposer, according to another embodiment of the present invention. At least one circuit chip10is attached to a top surface of a chip carrier20with a first array of solder connections30. As in the previous embodiment, the first array of solder connections30are comprised of a lead free off-eutectic solder composition, preferably about 72.0 weight % Sn and 28.0 weight % Ag, having dispersed grains of SnAg inter-metallic phase structure and a liquidus temperature of approximately 400° C.

At least one passive component100is attached to the chip carrier20with a lead free off-eutectic solder composition110having a liquidus temperature lower than the first array of solder connections30. In a preferred embodiment, the solder composition110is about 78.0 weight % Sn and 22.0 weight % Ag, and has dispersed grains of SnAg inter-metallic phase structure and a liquidus temperature of approximately 375° C. In another preferred embodiment the solder composition110is a lead free off-eutectic solder composition of about 82.0 weight % Sn and 18.0 weight % Ag, having dispersed grains of SnAg inter-metallic phase structure and a liquidus temperature of approximately 355° C.

A second array of solder connections41is used to attach the chip carrier20to a circuit board70. In this embodiment the second array of solder connections41are comprised of a lead free off-eutectic solder composition having a lower liquidus temperature than the first array of solder connections30. In a preferred embodiment the second array of solder connections41have a composition of about 95.5 weight % Sn and about 3.8 weight % Ag and about 0.7 weight % Cu and have a liquidus temperature of approximately 217° C.

The solder interconnect structure shown inFIG. 2is also not limited to an all lead free off-eutectic solder assembly. For example, the passive components100may be attached to the chip carrier20with a Sn/Pb solder composition having a liquidus temperature lower than the liquidus temperature of the first array of solder connections30. Alternatively, either a Sn/Bi or a Sn/In solder composition having a liquidus temperature lower than the liquidus temperature of the first array of solder connections30may also be used. In addition, the second array of solder connections41may consist of a eutectic Sn/Pb solder composition42. In a preferred embodiment the Sn/Pb solder composition is a eutectic composition of approximately 63.0 weight % Sn and 37.0 weight % Pb. However a slightly off-eutectic Sn/Pb solder composition in the range of approximately 58 to 70 weight % Sn and approximately 42 to 30 weight % Pb may be used as well.

Another embodiment of the present invention will be discussed with reference to FIG.3. At least one circuit chip10is attached to a top surface of a chip carrier20with a first array of solder connections30. In this embodiment the first array of solder connections30are comprised of a lead free off-eutectic solder composition. In a preferred embodiment the first array of solder connections30are a composition of about 72.0 weight % Sn and 28.0 weight % Ag, having dispersed grains of SnAg inter-metallic phase structure and a liquidus temperature of approximately 400° C.

A second array of solder connections43is used to attach the chip carrier20to an organic interposer50. A first end of the solder connection43is attached to the bottom of the chip carrier20with a second lead free off-eutectic solder composition44having a lower liquidus temperature than the first array of solder connections30. In a preferred embodiment the second lead free off-eutectic solder composition44is about 78.0 weight % Sn and 22.0 weight % Ag, having dispersed grains of SnAg inter-metallic phase structure and a liquidus temperature of approximately 375° C. A second end of the solder connection43is attached to the organic interposer50with a third lead free off-eutectic solder composition45having a lower liquidus temperature than the second lead free off-eutectic solder composition44. In a preferred embodiment the third lead free off-eutectic solder composition45is about 82.0 weight % Sn and 18.0 weight % Ag, having dispersed grains of SnAg inter-metallic phase structure and a liquidus temperature of approximately 355° C.

A third array of solder connections62is used to attach the organic interposer50to a printed circuit board70. In this embodiment the third array of solder connections62are comprised of a fourth lead free off-eutectic solder composition having a lower liquidus temperature than the third lead free off-eutectic solder composition45. In a preferred embodiment the third array of solder connections62are a composition of about 95.5 weight % Sn and about 3.8 weight % Ag and about 0.7 weight % Cu and has a liquidus temperature of approximately 217° C.

The solder interconnect structure shown inFIG. 3may also contain passive components100attached to the chip carrier20. In this embodiment the passive components100are attached to the chip carrier20with a fifth lead free off-eutectic solder composition112having a liquidus temperature lower than the first array of solder connections30. In a preferred embodiment, the fifth lead free off-eutectic solder composition112is about 78.0 weight % Sn and 22.0 weight % Ag, and has dispersed grains of SnAg inter-metallic phase structure and a liquidus temperature of approximately 375° C. In another preferred embodiment the fifth lead free off-eutectic solder composition112is 78Sn/22Ag but the second lead free off-eutectic solder composition44is about 82.0 weight % Sn and 18.0 weight % Ag, having dispersed grains of SnAg inter-metallic phase structure and a liquidus temperature of approximately 355° C.

The solder interconnect structure shown inFIG. 3is not limited to an all lead free off-eutectic solder assembly. For example, the passive components100may be attached to the chip carrier20with a Sn/Pb solder composition having a liquidus temperature lower than the liquidus temperature of the first array of solder connections30. Alternatively, either a Sn/Bi or a Sn/In solder composition having a liquidus temperature lower than the liquidus temperature of the first array of solder connections30may also be used. In addition, the third array of solder connections62may consist of a eutectic Sn/Pb solder composition63. In a preferred embodiment the Sn/Pb solder composition is a eutectic composition of approximately 63.0 weight % Sn and 37.0 weight % Pb. However a slightly off-eutectic Sn/Pb solder composition in the range of approximately 58 to 70 weight % Sn and approximately 42 to 30 weight % Pb may be used as well.

Referring now toFIG. 4there is shown a solder interconnect structure, including passive components, but without an organic interposer, according to another embodiment of the present invention. At least one circuit chip10is attached to a top surface of a chip carrier20with a first array of solder connections30. The first array of solder connections30are comprised of a first lead free off-eutectic solder composition, preferably about 72.0 weight % Sn and 28.0 weight % Ag, having dispersed grains of SnAg inter-metallic phase structure and a liquidus temperature of approximately 400° C.

At least one passive component100is attached to the chip carrier20with a second lead free off-eutectic solder composition111having a liquidus temperature lower than the first array of solder connections30. In a preferred embodiment, the second lead free off-eutectic solder composition117is about 78.0 weight % Sn and 22.0 weight % Ag, and has dispersed grains of SnAg inter-metallic phase structure and a liquidus temperature of approximately 375° C.

A second array of solder connections43is used to attach the chip carrier20to a circuit board70. A first end of the solder connection43is attached to the bottom of the chip carrier20with a third lead free off-eutectic solder composition44having a lower liquidus temperature than the second lead free off-eutectic solder composition111. In a preferred embodiment the third lead free off-eutectic solder composition44is about 82.0 weight % Sn and 18.0 weight % Ag, having dispersed grains of SnAg inter-metallic phase structure and a liquidus temperature of approximately 355° C. A second end of the solder connection43is attached to the circuit board70with a fourth lead free off-eutectic solder composition45having a lower liquidus temperature than the third lead free off-eutectic solder composition44. In a preferred embodiment the fourth lead free off-eutectic solder composition45is about 95.5 weight % Sn and about 3.8 weight % Ag and about 0.7 weight % Cu and has a liquidus temperature of approximately 217° C.

In an alternative to the above embodiment, both the second lead free off-eutectic solder composition111and the third lead free off-eutectic solder composition44may both be about 82.0 weight % Sn and 18.0 weight % Ag. Additionally, the solder interconnect structure shown inFIG. 4is not limited to an all lead free off-eutectic solder assembly. For example, the passive components100may be attached to the chip carrier20with a Sn/Pb solder composition having a liquidus temperature lower than the liquidus temperature of the first array of solder connections30. Alternatively, either a Sn/Bi or a Sn/In solder composition having a liquidus temperature lower than the liquidus temperature of the first array of solder connections30may also be used. In addition, the second array of solder connections43may be attached to the circuit board70with a eutectic Sn/Pb solder composition46. In a preferred embodiment the Sn/Pb solder composition46is a eutectic composition of approximately 63.0 weight % Sn and 37.0 weight % Pb. However a slightly off-eutectic Sn/Pb solder composition in the range of approximately 58 to 70 weight % Sn and approximately 42 to 30 weight % Pb may be used as well.

Referring toFIG. 5there is shown another embodiment of the present invention. A solder hierarchy structure for electronic package interconnections is comprised of an electronic module65which is attached to a circuit board70with an array of solder columns66. The electronic module65may be any conventional ceramic or organic chip carrier with or without passive components. A first end of the columns66are attached to the bottom side of the module65with a lead free solder composition67. The top surface of the circuit board70is attached to the second end of the array of solder columns66by a eutectic or near eutectic Sn/Pb solder composition68. In a preferred embodiment the Sn/Pb solder composition is a eutectic composition of approximately 63.0 weight % Sn and 37.0 weight % Pb. However a slightly off-eutectic Sn/Pb solder composition in the range of approximately 58 to 70 weight % Sn and approximately 42 to 30 weight % Pb may be used as well.

In one preferred embodiment the lead free solder composition67is a Sn/Ag solder composition. Preferred compositions include approximately 78 weight % Sn and 22 weight % Ag, approximately 82 weight % Sn and 18 weight % Ag, approximately 72 weight % Sn and 28 weight % Ag and approximately 96.5 weight % Sn and 3.5 weight % Ag.

In another preferred embodiment the lead free solder composition67is a Sn/Cu solder composition. Preferred compositions include approximately 93 weight % Sn and 7 weight % Cu, approximately 97 weight % Sn and 3 weight % Cu and approximately 99.3 weight % Sn and 0.7 weight % Cu.

In another embodiment of the present invention there is shown inFIG. 6a lead free solder structure for attaching a heat sink75to a circuit chip10with a lead free solder76. The mating surface of the chip10and heat sink75are metallized with a suitable wettable surface (not shown), such as Nickel or Gold, and which are well known in the art. In one embodiment the lead free solder76is a Sn/Ag solder composition comprised of approximately 72 to 96.5 weight % Sn and 28 to 3.5 weight % Ag. In another embodiment the lead free solder76is a Sn/Cu solder composition comprised of approximately 93 to 99.3 weight % Sn and 7 to 0.7 weight % Cu.

In another embodiment the lead free solder structure76is a layered solder preform of Sn/Ag/Sn. In a preferred embodiment the lead free layered solder preform comprises a first layer of Sn approximately 10 mils thick; a layer of Ag approximately 5 mils thick, the layer of Ag contiguous with the first layer of Sn; and a second layer of Sn approximately 10 mil thick, the second layer of Sn contiguous with the layer of Ag.

In this embodiment the layers of 10 mil thickness (0.01 inch) Tin, 5 mil thickness (0.005 inch) Silver and 10 mil thickness (0.01 inch) Tin would result in an off-eutectic SnAg alloy of approximately 80Sn/20Ag vol % once reflowed. The reflow temperature would be approximately 235° C. but the resulting off-eutectic heat sink/chip solder thermal interface would remain stable at temperatures up to 300° C.

In a preferred method commercially available Tin and Silver ribbon is cut roughly to the same planar area size as the chip. The Sn/Ag/Sn layered sandwich structure described above is placed on the metallized (Nickel/Gold etc.) back of the chip and held in place with a solder flux. The heat sink, also metallized, is then placed on the layered Sn/Ag/Sn solder structure on the chip. The assembly is then furnace reflowed to melt the solder structure. The top and bottom layers of Tin readily react with the metallized layers on the chip and heat sink forming a good bond. The remaining solder forms uniform areas of off-eutectic SnAg during reflow.

Once the preform is melted or reflowed it will result in a Sn/Ag off-eutectic soldered thermal interface with the appropriate temperature hierarchy to remain stable during subsequent module/card join assembly. The thickness of each layer would be determined to provide provide a specific solder structure during the heat sink to chip attach reflow.