Fault detection and automatic recovery apparatus or write-read pointers in First-In First-Out

The present invention relates to a fault detection and automatic recovery apparatus of write-read pointers in FIFO. While storing effective data in a register in writing performance, the apparatus does not unconditionally enable a FULL.sub.-- FLAG signal allotted to the register but confirms the relation of write-read pointers at that time and the EMPTY.sub.-- FLAG signal of a register at which the read pointer is situated and detects the error of FIFO. By selectively enabling the FULL.sub.-- FLAG signal of the register according to the result of detection, it automatically restores the FIFO functions without unnecessary re-initialization or the discontinuation of data transmission attributable thereto.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The present invention relates to a FIFO (First-In First-Out) memory which 
is used to prevent a loss of data caused by asynchronism in data 
transmission between two systems operating at different frequencies. More 
particularly, this invention relates to a fault detection and automatic 
recovery apparatus of write-read pointers in FIFO memories. 
2. Description of the Prior Art 
Generally speaking, the FIFO is a kind of memory which is frequently used 
in data communication. Such a FIFO memory performs read or write 
sequentially along the previously fixed addresses unlike a memory element 
which can perform random access. In other words, it stores effective data 
in an optional register and then moves a write pointer to the previously 
fixed next address. In like manner, it also moves a read pointer to the 
previously fixed next address after the read pointer has read the 
effective data. 
Since the FIFO can read after storing effective data in an empty space 
(register or memory cell), it characterizes that the read pointer follows 
the write pointer. 
In the FIFO which accesses the previously fixed addresses sequentially, if 
and when effective data is stored in an optional register, other data 
cannot be overwritten before the effective data is accessed by reading, 
thus rendering initialization of read/write pointers to be very important. 
If the FIFO operates when the positions of initial read/write pointers are 
not the same like an instance where the read pointer precedes the write 
pointer or the write pointer precedes the read pointer owing to a failure 
in initialization, there is a serious data error. In other words, the data 
which is output through the FIFO is not kept in the order of the input 
data. Consequently, it loses the function of FIFO. 
For example, as illustrated in FIG. 1, when all initial registers are 
empty, the read pointer is situated in the register at the address 1 due 
to a failure in initialization and the write pointer is normally situated 
in the register at the address 0 in the structure of FIFO in which 4 data 
can be stored, its performance will be observed. To help understand the 
performance, it is supposed that reading performance will begin after data 
is completely stored in all registers (4 registers). 
Writing performance stores first data in the register at the address 0 
according to the order of registers, then enables a FULL.sub.-- 
FLAG.sub.-- O signal allotted to the address 0 and confirms the condition 
of the register at the address 1 which is the next address. Since no 
effective data has yet been stored in the register at the address 1, it 
stores second data therein. When the effective data is stored in 4 
registers by repetitional writing performance, there exist no more empty 
registers, and so writing performance comes to a stop. 
Regarding reading performance, the initial read pointer was situated at the 
address 1, so that the data of the register at the address 0 input firstly 
cannot be accessed first of all and the data will be accessed in the order 
of addresses 1, 2, 3 and 0. Consequently, the data which is output becomes 
different from the order of input data and the FIFO loses its function. 
In this case, the FIFO is unable to return to normal conditions only with 
its existing structure. More particularly, if the read/write pointers are 
in such an abnormal condition in the UTOPIA interface which takes charge 
of interface between the physical layer of ATM, an applied field of the 
FIFO which processes frame-structured data, and ATM layer, it is next to 
impossible to expect normal data transmission. If necessary, the whole 
system must be initialized again and it is very inefficient. 
Now, the distinction between the prior patent ("Apparatus for and a method 
of detecting a malfunction of a FIFO memory", U.S. Pat. No. 5,404,332) and 
the present invention will be clarified. 
In the method of detecting a malfunction of a FIFO memory and restoring it 
to normalcy, the conventional parity check method cannot accurately detect 
an error when the error is not in the data but in the FIFO memory itself. 
Therefore, the prior patent realized the FIFO by means of a write address 
counter, a read address counter and a control counter to supplement its 
detection. The control counter used therein is to count the depth of a 
register containing effective data. Every time the write address counter 
changes, it is counted up. Conversely, it is counted down every time the 
read address counter changes. Therefore, when the FIFO is normal, the 
value of the control counter amounts to the number of registers containing 
the effective data. 
So, in the prior patent, the error of the FIFO is detected in the condition 
where "write address count value-read address count value=control count 
value". In the present invention, however, the error of the FIFO is 
detected by confirming if the read pointer is at the "write pointer+1" 
address and the FULL.sub.-- FLAG signal is at the "write pointer+1" 
address. 
Moreover, in the prior patent, each counter is reset to restore the FIFO to 
normal conditions when an error is made. In the present invention, 
however, the FULL.sub.-- FLAG signal of a corresponding register is 
selectively enabled according to the results of an error detector. 
SUMMARY OF THE INVENTION 
The object of the present invention is to provide a fault detection and 
automatic recovery apparatus of write-read pointers in FIFO memories which 
detect abnormal performance between a read pointer and a write pointer 
which may be caused by electrical noise and asynchronous initialization, 
and automatically restores its function without reinitialization. 
In the FIFO memory which temporally stores data which is input when 
synchronized with a write clock and outputs the data in the order input by 
synchronizing it again with a read clock, a fault detection and automatic 
recovery apparatus of write-read pointers comprises: a write controller 
which selectively outputs a write control signal by receiving input of a 
write performance enable signal of FIFO input from the outside and an 
effective state signal of the present register of a write pointer; a first 
counter which outputs a carry signal which indicates that one cell is 
produced and a write low-ranking data pointer which is synchronized with 
the write clock and counts frame-structured low-ranking data when the 
write control signal output from the write controller is enabled; a second 
counter which is connected in series with the first counter and outputs a 
write cell pointer by counting the carry signal corresponding to one cell 
output from the first counter by being synchronized with the write clock 
only when the write control signal of the write controller is enabled; a 
write flag generator which disables an effective state signal of the 
present register of the write pointer corresponding to an enabled address 
among the read empty flag signals of each register group input from an 
outside reading processor and, upon receiving input of a signal resulting 
from a comparison made between the write-read pointers, outputs a state 
signal of the register corresponding to the write cell pointer output from 
the second counter by synchronizing it with the carry signal of the first 
counter and then enables it selectively; a first multiplexer, upon 
receiving input of the state signal of the register output from the write 
flag generator, selects and outputs only the state signal of the register 
corresponding to the write cell pointer; a second multiplexer which, upon 
receiving input of the state signal of the register output from the write 
flag generator, selects and outputs only the state signal of the register 
corresponding to the next address of the present write cell pointer output 
from the second counter; an analyzer of the write-read pointers which, 
upon receiving input of the read pointer input from the outside upon 
reading processor, the write cell pointer output from the second counter 
and the state signal of the register output from the second multiplexer, 
analyzes the relationship between the write-read pointers and outputs a 
signal resulting from a comparison made between the write-read pointers; a 
first decoder which decodes the signal of the write cell pointer output 
from the second counter according to the write control signal of the write 
controller and a second decoder which decodes the signal of the write 
low-ranking data pointer output from the first counter according to the 
write control signal of the write controller. 
Additionally, the analyzer of write-read pointers determines the relation 
of read-write pointers to be abnormal when the read pointer input from the 
outside is situated at the next address register of the present write 
pointer and its register is in an empty condition. 
Such an analyzer of write-read pointers comprises a third decoder which 
decodes the read cell pointer information input from the outside reading 
processor; a synchronizer which synchronizes the output of the third 
decoder with the write clock; a third multiplexer which receives input of 
the write cell pointer from the second counter and selects the output of 
the third decoder corresponding to the next address of the write pointer 
and a signal controller which receives input of the output from the third 
multiplexer and the output from the second multiplexer and controls a 
write requiring pointer signal. 
The write flag generator enables a signal which shows that there is 
effective data in the register corresponding to the write cell pointer 
when the signal output from the analyzer of write-read pointers is normal. 
At the same time, the write flag generator disables the signal which shows 
that there is effective data in the register corresponding to the write 
cell pointer to restore normal FIFO functions if it stored the effective 
data in the register when the signal output from the analyzer of 
write-read pointers is abnormal. 
In the present invention, a judgment of whether the relation between a 
write pointer and a read pointer is normal or abnormal can be formed by 
confirming the address of a register at which the write pointer and the 
read pointer are situated and a FULL.sub.-- FLAG signal of the register. 
In other words, write performance in a general FIFO memory stores effective 
data in the present register in which the write pointer is situated and 
then declares a FULL.sub.-- FLAG signal allotted thereto. And, to 
ascertain if it can store data in a register at the next address, it 
confirms the state of that register. When the register is empty at this 
time, it stores new data therein but, when the effective data which is not 
yet read is contained therein, it is suspended to protect the existing 
data. 
Therefore, when the write pointer and the read pointer are not situated in 
the same register and no effective data is contained in the register of 
the read pointer, the relation between the write-read pointers within the 
FIFO can be judged to be abnormal.

DESCRIPTION OF PREFERRED EMBODIMENTS 
FIG. 2 is a schematic diagram of an apparatus which detects the abnormal 
relation of write-read pointers and automatically recovers FIFO functions. 
The fault detection and automatic recovery apparatus of write-read pointers 
in FIFO comprises a write controller (10), a first counter (20), a second 
counter (30), a write flag generator (40), a first multiplexer (50), a 
second multiplexer (60), an analyzer (70) of write-read pointers, a first 
decoder (80) and a second decoder (90). 
The write controller (10) receives input of a WRITE.sub.-- ENABLE signal 
(111) which controls the write performance of the FIFO and is input from 
the outside and an effective state signal (W.sub.-- FULL.sub.-- FLAG) (50) 
of the present register of the write pointer which is output from the 
first multiplexer (50), and outputs a write control signal (W.sub.-- 
EN.sub.-- INT) (11) selectively according to the input conditions of the 
two signals. 
The first counter (W.sub.-- UNIT.sub.-- PTR.sub.-- COUNTER) (20) is driven 
by being synchronized with a write clock (W.sub.-- CLK) (222) when the 
write control signal (W.sub.-- EN.sub.-- INT) (11) output from the write 
controller (10) is enabled. The first counter (20) has a frame size (for 
example, in the case of ATM cell which is a basic cell for SDH 
transmission system, it is formed of 53 bytes, and so the size of a frame 
is "53".) when the data which is input to the FIFO has a frame structure. 
According thereto, the first counter (20) outputs a carry signal (W.sub.-- 
UNIT.sub.-- CARRY) (21) which indicates that one cell is produced and a 
write low-ranking data pointer (W.sub.-- UNIT.sub.-- PRTm:1!) (22) by 
being synchronized with the above write clock (222) and counting the 
frame-structured 53 bytes (forms one cell) sequentially. 
The second counter (W.sub.-- CELL.sub.-- PTR.sub.-- COUNTER) (30) is 
connected in series to the first counter (W.sub.-- UNIT.sub.-- PTR.sub.-- 
COUNTER) (20). The second counter outputs a write cell pointer (W.sub.-- 
CELL.sub.-- PRTn:1!) (31) by being synchronized with the write clock 
(W.sub.-- CLK) (222) and counts the carry signal (W.sub.-- UNIT CARRY) 
(21) which indicates that one cell output from the above first counter 
(20) is produced only when the write signal (W.sub.-- EN.sub.-- INT) (11) 
output from the above write controller (10) is enabled. Such second 
counter (30) is related to the register depth of the FIFO. 
The write flag (W.sub.-- FULL.sub.-- FLAG) generator (40) receives input of 
read empty flag (R.sub.-- EMPTY.sub.-- FLAG) signals 2.sup.n ! (333) 
which show if each register group reads its registers from the outside 
reading processor. The write flag generator (40) disables an effective 
state (W.sub.-- FULL.sub.-- FLAG) signal of the present register of the 
write pointer corresponding to an enabled address among the input R.sub.-- 
EMPTY.sub.-- FLAG signals. Moreover, the write flag generator (40) 
synchronizes the state (W.sub.-- FULL.sub.-- FLAG) signal (41) of a 
register corresponding to the write cell pointer (W.sub.-- CELL.sub.-- 
PTRn:1!) (31) output from the above second counter (W.sub.-- CELL.sub.-- 
PTR.sub.-- COUNTER) (30) with the W.sub.-- UNIT.sub.-- CARRY signal (21) 
output from the above first counter (20) and selectively enables it and 
then outputs it according to the state of a signal resulting from a 
comparison made between write-read pointers (WR.sub.-- EQ.sub.-- PTR) (71) 
output from the analyzer (70) of write-read pointers (WR.sub.-- PTR) which 
will be described hereinafter. Such a write flag generator (40) enables 
and outputs the W.sub.-- FULL.sub.-- FLAG signal which shows that an 
effective data is contained only when the relation between write-read 
pointers is proved to be normal if it stored all data of one frame as a 
group of registers. 
The first multiplexer (W.sub.-- FULL.sub.-- FLAG) (50) receives input of 
the state signal (W.sub.-- FULL.sub.-- FLAG) 2.sup.n ! (41) of the 
register output from the above write flag generator (40) and selects only 
the state signal (W.sub.-- FULL-FLAG) of the register corresponding to the 
write cell pointer (W.sub.-- CELL.sub.-- PTRn:1! (31) output from the 
above second counter (W.sub.-- CELL.sub.-- PTR.sub.-- COUNTER) (30) and 
outputs it. 
The second multiplexer (W.sub.-- FULL.sub.-- FLAG.sub.-- NEXT) (60) 
receives input of the state signal (W.sub.-- FULL.sub.-- FLAG) 2.sup.n ! 
(41) of the register output from the above write flag generator (40) and 
selects only the state (W.sub.-- FULL.sub.-- FLAG.sub.-- NEXT) signal (61) 
of the register corresponding to the next address of the present write 
cell pointer (W.sub.-- CELL.sub.-- PTRn:1! (31) output from the above 
second counter (30) and outputs it. 
The analyzer (70) of write-read pointers (WR.sub.-- PTR) receives input of 
the read pointer information (R.sub.-- CELL.sub.-- PTRn:1!) (444) output 
from the outside reading processor, input of the write cell pointer 
(W.sub.-- CELL.sub.-- PTRn:1! (31) output from the second counter 
(W.sub.--CELL.sub.-- PTR.sub.-- COUNTER) (30) and input of the state 
signal (W.sub.-- FULL.sub.-- FLAG.sub.-- NEXT) (61) and analyzes the 
relation between write-read pointers and outputs a signal resulting from a 
comparison made between the write-read pointers (WR.sub.-- EQ.sub.-- PTR) 
(71). 
The first decoder (W.sub.-- CELL.sub.-- PTR) (80) receives input of the 
write cell pointer (W.sub.-- CELL.sub.-- PTRn:1! signal (31) output from 
the above second counter (W.sub.-- CELL.sub.-- PTR.sub.-- COUNTER) (30), 
and decodes it only when the write control signal (W.sub.-- EN.sub.-- INT) 
(11) is enabled and then outputs (W.sub.-- CELL.sub.-- PTR.sub.-- DEC) 
2.sup.n ! (81) it. 
The second decoder (W.sub.-- UNIT.sub.-- PTR) (90) recovers input of the 
signal of the write low-ranking data pointer (W.sub.-- UNIT.sub.-- 
PTRm:1!) (22) output from the above first counter (W.sub.-- UNIT.sub.-- 
PTR.sub.-- COUNTER) (20) and decodes it only when the write control signal 
(W.sub.-- EN.sub.-- INT) (11) output from the above write controller (10) 
is enabled and then outputs (W.sub.-- UNIT.sub.-- PTR.sub.-- DEC) 2.sup.n 
! (91) it. 
Performance and effectiveness of the fault detection and automatic recovery 
apparatus of write-read pointers in FIFO formed in such a manner will now 
be described. 
The write controller (10) is formed so as to limit writing performance in 
order to protect the existing effective data contained in FIFO even if 
writing performance is enabled from the outside. 
In other words, if and when an effective data which has not yet been read 
is contained in a register at which the write pointer is located, the 
write controller (10) disables the W.sub.-- EN.sub.-- INT (11) signal to 
protect the existing effective data contained in the register even if the 
input WRITE.sub.-- ENABLE (111) signal is enabled. Whether effective data 
is contained or not can be judged by confirming the W.sub.-- FULL.sub.-- 
FLAG signal of the register at which the write pointer is situated. The 
first multiplexer (W.sub.-- FULL.sub.-- FLAG) (50) selects and provides 
the W.sub.-- FULL.sub.-- FLAG signal of the register at which the write 
pointer is situated. 
A FIFO according to the present invention has two counters for generation 
of pointers to process frame-structured data. 
One is a counter which has the size of a frame to process frame-structured 
low-ranking data. 
The other is a counter which shows the number of frames the FIFO can 
accommodate. 
As illustrated in FIG. 2, the first counter (W.sub.-- UNIT.sub.-- 
PTR.sub.-- COUNTER) (20) is a device to process low-ranking data in frame 
structure and the second counter (W.sub.-- CELL.sub.-- PTR.sub.-- COUNTER) 
(30) is a device to show the number of frames the FIFO can accommodate. 
The second counter (30) and the first counter (20) operate by being 
connected in series. 
In other words, the second counter (30) which shows the number of frames 
the FIFO can accommodate receives input of the carry signal (W.sub.-- 
UNIT.sub.-- CARRY) (21) from the first counter (20) and operates only when 
the write control signal (W.sub.-- EN.sub.-- INT) (11) is enabled. 
The number of write flags which shows the state of FIFO depends on the 
second counter (W.sub.-- CELL.sub.-- PTR.sub.-- COUNTER)(30). That is, the 
write flag (W.sub.-- FULL.sub.-- FLAG) is not allotted to every 
low-ranking data included in the frame. It is allotted to the frame as a 
unit. 
The write flag generator (40) is a device which generates a signal which 
indicates that effective data is contained in the register of FIFO. When 
the write control signal (W.sub.-- EN.sub.-- INT) (11) is enabled, it 
begins to write data in the register group indicated by the write cell 
pointer (W.sub.-- CELL.sub.-- PTRn:1!) and writes the last data included 
in the frame. At the same time, it selectively enables the write flag 
(W.sub.-- FULL.sub.-- FLAG) signal indicated by the write cell pointer 
(W.sub.-- CELL.sub.-- PTR n:1!) according to the output (WR.sub.-- 
EQ.sub.-- PTR)(71) value of the analyzer (70) of write-read pointers 
(WR.sub.-- PTR). 
In other words, even if the write flag generator stored all data of one 
frame in the register group, it enables the write flag (W.sub.-- 
FULL.sub.-- FLAG) signal which shows that an effective data is contained 
only when the relation of write-read pointers at that time is proved to be 
normal. 
The write flag generator (40) receives input of R.sub.-- EMPTY.sub.-- FLAG 
signals (333) which indicate if each register group reads its registers 
from the outside reading processor (not illustrated) and disables the 
write flag (W.sub.-- FULL.sub.-- FLAG) signal of a corresponding register 
group by synchronizing it with the W.sub.-- CLR (222). 
The analyzer of write-read pointers (WR.sub.-- PTR)(70) is a device which 
analyzes the present relation between write-read pointers. 
As illustrated in FIG. 3, the present invention comprises a third decoder 
(75) which receives a read pointer (R.sub.-- CELL.sub.-- PTRn:1!) (444) 
from the reading processor (not illustrated) and decodes it; a 
synchronizer (76) which synchronizes output of the above third decoder 
(75); a third multiplexer (77) which receives input of the write cell 
pointer (W.sub.-- CELL.sub.-- PTR.sub.-- COUNTER)(30) and selects output 
of the third decoder (75) corresponding to the next address of write 
pointer and a signal controller (78) which controls a value resulting from 
a comparison made between write-read pointers (WR.sub.-- EQ.sub.-- 
PTR)(71) with output of the above third multiplexer (77) and a W.sub.-- 
FULL.sub.-- FLAG.sub.-- NEXT (61) signal output from the second 
multiplexer as input. 
Thus, the analyzer (70) of write-read pointers (WR.sub.-- PTR) receives 
input of read pointer information (R.sub.-- CELL.sub.-- PTR n:1!) (444) 
from the reading processor (not illustrated) and judges if the read 
pointer is situated at the next address of the write pointer. It also 
receives input of the information (W.sub.-- FULL.sub.-- FLAG.sub.-- NEXT) 
(61) which shows the state of a register at the next address of the write 
pointer from the second multiplexer (W.sub.-- FULL.sub.-- FLAG.sub.-- 
NEXT) (60) and judges the relation between the write-read pointers. In 
other words, it judges the relation between the write-read pointers to be 
abnormal only when the read pointer is situated at the next address of the 
present write pointer and its register is empty, and enables the result of 
a comparison made between the write-read pointers (WR.sub.-- EQ.sub.-- 
PTR)(71). 
According thereto, the above write flag (W.sub.-- FULL.sub.-- FLAG) 
generator (40) disables the write flag state (W.sub.-- .sub.-- FULL.sub.-- 
FLAG) even if it stored effective data in the present register group, if 
its WR.sub.-- EQ.sub.-- PTR (71) signal is enabled. So, the effective data 
of one frame is lost but it is restored to normal FIFO functions in the 
final analysis. 
On the contrary, when the existing FIFO finishes storing effective data in 
a register or a register group, it unconditionally enables the W.sub.-- 
FULL.sub.-- FLAG, which is information that the effective data is 
contained, without confirming the position of a read pointer and the state 
of a corresponding register. So, if the write-read pointers of FIFO 
operated in an abnormal condition, first-in first-out functions will be 
lost, as described hereinabove. 
However, the FIFO according to the present invention enables the W.sub.-- 
FULL.sub.-- FLAG signal selectively by analyzing the position of read 
pointer and the state of a corresponding register while storing the 
effective data in the corresponding register. 
In other words, if and when the FIFO confirms that the relation between the 
write-read pointers is normal, it enables the W.sub.-- FULL.sub.-- FLAG 
signal, but it does not enable the W.sub.-- FULL.sub.-- FLAG signal to 
restore normal functions even if it stored effective data in a register, 
if it confirms that the relation between the write-read pointers is 
abnormal. 
Consequently, this register is overwritten by the next writing performance 
and data is lost, but it will restore normal first-in first-out functions 
in the final analysis. 
One embodiment of the present invention will now be described on the basis 
of a FIFO comprised of 4registers. 
Looking at the state of the initial write-read pointers in FIG. 1, the 
write pointer is situated at the address 0, the read pointer is situated 
at the address 1 corresponding to the next address of the write pointer 
and the FULL.sub.-- FLAG signal of each register in the initial stage is 
disabled, so that the analyzer (70) of the write-read pointers (WR.sub.-- 
PTR) judges that the relation between the present write-read pointers is 
abnormal and enables the WR.sub.-- EQ.sub.-- PTR (71) signal. So, it 
stores a first input data in the register at the address 0 by writing 
performance but disables the FULL.sub.-- FLAG.sub.-- 0. 
Looking at the relation between the write-read pointers at this time, the 
read pointer moves to the next address and then indicates the address 1 
and the read pointer indicates the address 1 as it is without a change, 
and so it is not in the abnormal state of write-read pointers. 
Accordingly, the analyzer (70) of write-read pointers disables the 
WR.sub.-- EQ.sub.-- PTR (71) signal, and stores a second input data in the 
register at the address 1 by performing writing and enables a FULL.sub.-- 
FLAG.sub.-- 1 signal. 
By repeated writing performance, the analyzer (70) stores input data in 
those registers at the addresses 2 and 3 and enables a FULL.sub.-- 
FLAG.sub.-- 2 signal and a FULL.sub.-- FLAG.sub.-- 3 signal. 
Finishing off storing input data in the register at the address 3, the 
analyzer (70) confirms a FULL.sub.-- FLAG.sub.-- 0 of the register at the 
address 0. Though the first input effective data is actually stored in the 
register at the address 0, FIFO is operated in the abnormal state of 
write-read pointers, so that the FULL.sub.-- FLAG.sub.-- 0 signal has been 
disabled. So, the register at the address 0 is overwritten by newly input 
data and there are no more empty registers. For this reason, writing 
performance is discontinued. 
On the other hand, the analyzer (70) reads data stored in the registers by 
reading performance beginning with the register at the address 1. 
Consequently, as shown in FIG. 1, when accessing of 4 registers is 
finished, the abnormal state of write-read pointers in the initial stage 
is restored to the normal state. 
FIG. 4 relates to a performance of a FIFO comprised of 4 registers 
according to the invention. It illustrates the relation between the state 
signal and the input/output data of each register. 
As described hereinabove, the present invention is formed so as to analyze 
the position of a read pointer and the state of a corresponding register 
and enable a FULL.sub.-- FLAG signal selectively according to the result 
thereof. Therefore, even when the FIFO operates in the abnormal state of 
write-read pointers due to failure in initialization or owing to an 
electric shock, it recovers normal functions in the final analysis without 
discontinuation of data transmission caused by unnecessary 
re-initialization, though a small loss is inflicted on data in the initial 
stage. 
Many different embodiments of the present invention may be constructed 
without departing from the spirit and scope of the invention. It should be 
understood that the present invention is not limited to the specific 
embodiments described in this specification. To the contrary, the present 
invention is intended to cover various modifications and equivalent 
arrangements included within the spirit and scope of the claims.