SELF-ALIGNED, SYMMETRIC PHASE CHANGE MEMORY ELEMENT

A phase change memory element including at least one phase change material layer, and a heater conductor, wherein at least a portion of the heater conductor is circumferentially surrounded by the at least one phase change material layer. The phase change memory element is symmetrical. The phase change memory element can include a top electrode circumferentially surrounding and connected to the at least one phase change material layer, and a bottom electrode in contact with the heater conductor. The phase change memory element can include at least one resistive liner in contact with the at least one phase change material layer.

BACKGROUND

The present disclosure relates to non-volatile, high density, integrated circuit memory devices, and more particularly to such memory devices based upon phase change material, and methods of fabricating the same.

Phase change memory (PCM) is an emerging non-volatile (NV) random-access memory (RAM) that can store information based on a resistance state of a memory element of a memory cell. The memory element includes material that can change between different phases (e.g., crystalline and amorphous phases) when programmed. Different phases of the material can cause the memory cell to have different resistance states with different resistance values. The different resistance states of the memory element can represent different values of the information stored in memory.

One issue with use of PCM is called “resistive drift.” Resistive drift is an undesired changing of resistance after a PCM has been programmed, which relates to the amorphous phase, and corresponds to a high resistance state (HRS) of the memory cell.

SUMMARY

According to some embodiments of the disclosure, there is provided a phase change memory element. The phase change element includes at least one phase change material layer; and a heater conductor, wherein at least a portion of the heater conductor is circumferentially surrounded by the at least one phase change material layer.

According to some embodiments of the disclosure, there is provided a method for forming a phase change memory element. The method includes providing a substrate, depositing a dielectric layer on the substrate, and depositing a phase change material layer on the dielectric layer. The method further includes forming a via through the dielectric layer, and the phase change material layer, forming a heater conductor within the via wherein at least a portion of the heater conductor is circumferentially surrounded by the phase change material layer, patterning the phase change material layer, and forming a top electrode circumferentially surrounding and connected to the phase change material layer.

According to some embodiments of the disclosure, there is provided a method for forming a phase change memory element. The method includes providing a substrate, depositing a dielectric layer on the substrate, depositing at least one phase change material layer on the dielectric layer, and depositing at least one resistive liner on the at least one phase change material layer. The method further includes forming a via through the dielectric layer, the at least one phase change material layer, and the at least one resistive liner, forming a heater conductor within the via, wherein at least a portion of the heater conductor is circumferentially surrounded by the at least one phase change material layer and the at least one resistive liner, patterning the at least one phase change material layer and the at least one resistive liner, and forming a top electrode circumferentially surrounding and connected to the at least one phase change material layer and the at least one resistive liner.

DETAILED DESCRIPTION

Aspects of the present disclosure relate to non-volatile, high density, integrated circuit (IC) memory devices, and more particularly to such memory devices based upon PCM, and methods of fabricating the same. While the present disclosure is not necessarily limited to such applications, various aspects of the disclosure may be appreciated through a discussion of various examples using this context.

A memory element100in accordance with an embodiment of the present disclosure is shown inFIG.1. It will be understood thatFIG.1presents, in schematic form, only a portion of a memory cell as finally fabricated and placed in use. Circuit elements are formed both above and below the portion shown in the figure. Memory element100can be fabricated using method operations described herein below. The features of memory element100are also described in detail below.

It is useful to clarify several matters of terminology. First, it should be noted that the term “memory element” refers to the devices required to provide a location for storing one or more bits of information. A “memory cell” is a combination of a memory element and an element of an access circuit which conventionally consists of a transistor having a gate coupled to a word line, a drain coupled to a contact for connection to the memory element, and a source coupled to a reference line or ground, or consists of a diode having one terminal coupled to a word line or a reference line. The access circuits operate in conjunction with parallel arrays of bit lines and word lines to route signals to appropriate individual memory elements. Other structures can be used for providing access to memory elements, as can be selected by those skilled in the art. Here, the access circuits are preferably located at a level below that of memory element100, and they are not shown.

FIGS.2A and2Bare schematic, cross-sectional views taken at line2-2inFIG.1at two different phases of memory element100, for example.FIG.2Ashows the memory element100while a phase change material layer112is in a crystalline state.FIG.2Bshows the memory element while in a partial amorphous state, with a portion of the phase change material layer112being amorphous, and indicated as112′. The amorphous portion112′ is surrounding and adjacent a heater conductor122of memory element100, and can be amorphous while electricity is conducted through heater conductor122, for example. The features shown inFIGS.2A and2Bwill be discussed in detail herein below with regard to fabrication of the memory element100.

For the sake of brevity, conventional techniques related to semiconductor device or IC chip fabrication may or may not be described in detail herein. Moreover, the various tasks and process operations described herein can be incorporated into a more comprehensive procedure or process having additional operations or functionality not described in detail herein. In particular, various operations in the manufacture of semiconductor devices or ICs are well known and so, in the interest of brevity, many conventional operations will only be mentioned briefly herein or will be omitted entirely without providing the well-known process details.

Example methods of fabricating the memory element100are shown in cross-sectional views at fabrication stages starting inFIG.3. Starting withFIG.3, a substrate102is provided as shown. The substrate102can be any semiconductor substrate, which can comprise other devices such as transistors, isolation structures, contacts, etc. A bottom electrode104is formed on a portion of an upper surface of the substrate102in a center area of the substrate102. The bottom electrode104is surrounded by a first dielectric layer106. The bottom electrode104can be formed, for example, by a conventional complementary metal-oxide semiconductor (CMOS) back end-of-line (BEOL) damascene process (e.g., tungsten, cobalt, or copper surrounded by low-k dielectric), for example. Other suitable processes and materials may be used, however, for the bottom electrode104. The first dielectric layer106can include one or more dielectric materials, including but not limited to, silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), carbon-doped silicon oxide (SiOC), carbon doped silicon oxide (SiO:C), fluorine-doped silicon oxide (SiO:F), silicon-carbon-nitride (SiCN), boron nitride (BN), silicon boron nitride (SiBN), silicoboron carbonitride (SiBCN), silicon oxycarbonitride (SiOCN), silicon oxide (SiO), boron carbon nitride (BCN), hydrogen silsesquioxane polymer (HSQ), methyl silsesquioxane polymer (MSQ), methyl doped silica (SiO:(CH3)), organosilicate glass (SiCOH), porous SiCOH, and any suitable combinations thereof. The first dielectric layer106can be formed by any suitable deposition technique, including but not limited to, chemical vapor deposition (CVD), spin-on, atomic layer deposition (ALD), etc.

FIG.4shows the structure after deposition of four additional layers, which would be deposited one at a time in successive operations, atop the bottom electrode104and first dielectric layer106. The first of the four layers deposited is a second dielectric layer108that is above and in electrical contact with a top surface of the bottom electrode104and a top surface of the first dielectric layer106. An example material for the second dielectric layer108is SiN, although other materials are also contemplated. The second dielectric layer108can be applied using CVD, ALD, and physical vapor deposition (PVD), although other processes are contemplated.

The second of the four layers deposited above the second dielectric layer108is a resistive liner110. The resistive liner110material can be, for example, aluminum nitride (AlN), BN, aluminum oxide (AlO), tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), cobalt tungsten (CoW), nickel tungsten (NiW), or yttrium oxide (YO). The resistance of resistive liner110is substantially greater than the resistance of heater conductor122(e.g., five to fifty times higher, or about twenty times higher). Furthermore, the resistance of resistive liner110is substantially greater than the resistance of phase change material layer112in a low resistance, polycrystalline state (e.g., ten to forty times higher, or about twenty times higher) and substantially lower than the resistance of phase change material layer112in high resistance, amorphous state (e.g., five to fifty times lower, or about ten times lower). The resistivity of resistive liner110can be, for example, in the range of 0.1 ohm micrometers (Ωμm) to 1 kiloohm micrometers (kΩμm). The resistive liner110can be deposited by any suitable technique, including but not limited to ALD, PVD, CVD, etc.

The resistive liner110, for example, can migrate resistance drift. Such a resistive liner, in general, can migrate resistive drift in a confined PCM cell. In a confined PCM cell, a resistive liner is formed in parallel with the PCM in a vertical via. The resistance of such a resistive liner is higher than that of PCM in a low resistance state (LRS) but lower than that of PCM in a HRS. The resistance drift is migrated by the resistive liner as the resistive liner shunts read current in the amorphous PCM. Embodiments described herein adopt a resistive liner in order to migrate resistance drift.

The third of the four layers deposited, as shown inFIG.4, and which is applied above the resistive liner110, is the layer of phase change material112. One example alloy material that can be used for the phase change material layer112is germanium-antimony-tellurium (Ge/Sb/Te) (otherwise known as “GST”). However, the phase change material layer112can be fabricated from a number of different phase change materials, including but not limited to, Si—Sb—Te (silicon-antimony-tellurium) alloys, Ga—Sb—Te (gallium-antimony-tellurium) alloys, Ge—Bi—Te (germanium-bismuth-tellurium) alloys, In—Te (indium-tellurium) alloys, As—Sb—Te (arsenic-antimony-tellurium) alloys, Ag—In—Sb—Te (silver-indium-antimony-tellurium) alloys, Ge—In—Sb—Te alloys, Ge—Sb alloys, Sb—Te alloys, Si—Sb alloys, and combinations thereof. In some embodiments, the phase change material can further include nitrogen, carbon, and/or oxygen. In some embodiments, the phase change material can be doped with dielectric materials including but not limited to Al2O3, SiO, Ta2O5, HfO2, zirconium oxide (ZrO2), cerium oxide (CeO2), SiN, SiON, etc.

Phase change alloys are capable of being switched between a first structural state in which the material is in a generally amorphous solid phase, and a second structural state in which the material is in a generally crystalline solid phase in its local order in the active channel region of the cell. These alloys are at least bistable. The term “amorphous” is used to refer to a relatively less ordered structure, more disordered than a single crystal, which has the detectable characteristics such as higher electrical resistivity than the crystalline phase. The term “crystalline” is used to refer to a relatively more ordered structure, more ordered than in an amorphous structure, which has detectable characteristics such as lower electrical resistivity than the amorphous phase. Typically, phase change materials can be electrically switched between different detectable states of local order across the spectrum between completely amorphous and completely crystalline states. An example method for forming chalcogenide material uses PVD, sputtering, magnetron-sputtering, CVD, or ALD.

Next, inFIG.4, a third dielectric layer114is shown deposited atop the phase change material layer112. An example material for the third dielectric layer114is SiN, although other materials are contemplated. The third dielectric layer114can include one or more dielectric materials, including but not limited to, SiN, SiC, SiON, SiOC, SiO:C, SiO:F, SiCN, BN, SiBN, SiBCN, SiOCN, SiO, BCN, HSQ, MSQ, SiO:(CH3), SiCOH, porous SiCOH, and any suitable combinations thereof. The third dielectric layer114can be formed by any suitable deposition technique, including but not limited to, CVD, spin-on, ALD, etc.

Also inFIG.4, a sacrificial layer116is shown deposited on top of the third dielectric layer114. An example material for the sacrificial layer116is silicon dioxide (SiO2), although other materials are contemplated. The sacrificial layer116can be deposited by CVD, although other deposition techniques such as spin-on and PVD are contemplated. Above the sacrificial layer, a block mask layer118can be deposited (shown inFIG.5). The block mask layer can be a softmask layer such as optical planarization layer (OPL), anti-reflection layer, and photoresist. Alternatively, the block mask layer118can be a hardmask layer such as amorphous silicon or amorphous silicon germanium. The block mask layer118can be deposited by, for example, spin-on, PVD, or CVD, although other deposition techniques are contemplated.

FIG.5illustrates the structure fromFIG.4, including the block mask layer118, after patterning to form a via120reaching the bottom electrode104. The via120is located at or near the center of the structure and extends vertically (i.e., along y-axis) from the top of the structure, through some of the layers of the structure, and down to the bottom electrode104. Patterning the via can be performed using a directional etching process (e.g., reactive ion etch (RIE)) or other suitable processes.FIG.6shows the structure after the next operation, which is after removal of the block mask layer118. The block mask layer can be removed by, for example, ashing or any other suitable technique.

FIG.7is an alternative, resultant structure to that ofFIG.6and after the patterning process is performed to form a via in the structure, subsequent toFIG.5. The layers inFIG.7are labelled with a “2” as their first number rather than a “1” as inFIG.6, and are corresponding layers to those in the embodiment ofFIG.6. The discussion of the materials and methods of forming the layers herein with regard to the embodiment ofFIGS.1,3-6,8,10,12,14,16,18and20also applies to the embodiment ofFIGS.7,9,11,13,15,17,19,21and22. The difference betweenFIG.6andFIG.7is a presence of etched portions221of phase change material layer212that are located within and/or adjacent via220. During the patterning process (e.g., isotropic etching process) used to form the via220, the sidewalls of the phase change material layer212can be damaged. The damaged portions can be removed using, e.g., lateral etching. Lateral etching of the phase change material layer212can expose tips of resistive liner210.

Following the patterning process used to form vias120,220, next, a preclean process can be used to access or clean the tips of the resistive layer212and bottom electrodes104,204(used for bottom electrodes in both embodiments ofFIGS.6and7) prior to a next operation in the fabrication process described below. Such a process includes deposition of heater conductor material to form a heater conductor122,222. An example preclean process is an argon sputtering/hydrogen plasma process, which can be in situ or ex situ in order to clean the surface of the resistive liner210and bottom electrodes104,204.

FIGS.8and9illustrate the next operation in the fabrication process, which is addition of heater conductor122,222. The heater conductor122,222can be formed in the corresponding via120,220using conformal deposition, for example, although other suitable processes are contemplated. The heater conductor122,222can be made of a single material (e.g., TiN) or multiple-layered materials (e.g., TaN/TiN/TaN). Other suitable, conductive materials are also contemplated. Other heater conductor materials include: hafnium nitride (HfN), niobium nitride (NbN), WN, tungsten carbon nitride (WCN), or combinations thereof. The heater conductor122,222can be deposited in the trench(es) by ALD, CVD, metal organic CVD (MOCVOD), plasma-enhanced CVD (PECVD), or combinations thereof. As shown inFIG.9, after the metal fill is deposited in the embodiment including etched portions221(seeFIG.7) to form the heater conductor222, a void223(or seam) is formed at or near the middle of the heater conductor222in the area of the etched portions221.

FIGS.10and11show the next operation of the process, which is removal of sacrificial layer116,216to expose a portion of the heater conductor122,222. The sacrificial layer116,216can be removed by any suitable dry etch (e.g., plasma etching) or wet etching, selective to heater conductor. Portions of the heater conductor122,222then extends upward above the third dielectric layer114,214.

FIGS.12and13show a following operation, in which a spacer124,224is added surrounding the portion of the heater conductor122,222that extends above the third dielectric layer114,214as in the previous operation (seeFIGS.10and11). The spacer124,224, can be formed in two operations by depositing a material (e.g., SiN) around heater conductor122,222, and following material deposition (e.g., by CVD) by a directional etch (e.g., reactive-ion etching (RIE)). Other suitable materials (e.g., SiON, SiCN, SiOCN, SiBCN, SiOC) and methods for forming a spacer are also contemplated.

FIGS.14and15show resultant structures after the next operation, which is to use a combination of the heater conductor122,222and the spacer124,224as a mask to pattern the three layers below the spacer124,224. The three layers that are patterned are the third dielectric layer114,214, the phase change material layer112,212, and the resistive liner110,210. The patterning process involves directive ion etch (RIE) and/or ion beam etching. The spacer124,224has a uniform lateral thickness, which allows the patterning process to result in a symmetric phase change material layer112,212and symmetric resistive liner110,210that are self-aligned with the heater conductor122,222. The symmetrical feature of the phase change material layer112,212and the resistive liner110,210is an advantage to the resultant memory cell because it enables the same distance from the edge of the heater conductor122,222to the edge of the later formed on top electrode (128,228, discussed below). In other words, the lateral dimension of the phase change material layer112,212between the heater conductor122,222and the later formed on top electrode128,228is substantially the same as it is defined by the spacer124,224thickness. The uniform dimension of phase change material layer112,212between heater conductor122,222and top electrode128,228reduces the variation of phase change memory cell.

FIGS.16and17show the next resultant structures, which is after a portion of the heater conductor122,222is recessed by etching, for example, plasma etching or wet etching. Void223is still present, as shown inFIG.17.

Next,FIGS.18and19show a dielectric cap material layer125,225deposited over the top of the structures and into the vias120,220where the heater conductors122,222were recessed in the earlier operation of the method (seeFIGS.16and17). Conformal dielectric deposition, such as ALD and CVD, can be used to apply the dielectric cap material layer125,225. The thickness of the dielectric cap material layer125,225can be more than half of the diameter of the heater conductor122,222opening in order to pinch off the top of the heater conductor122,222. The dielectric cap material layer125,225may comprise any suitable dielectric material, such as, e.g., SiN, SiON, SiOC, or SiOCN.

FIGS.20and21show the next operation in which the dielectric cap material layers125,225(fromFIGS.18and19) are etched back to form dielectric caps126,226located above the heater conductors122,222within vias120,220. Isotropic dielectric etching may be used to form the dielectric cap126,226on top of heater conductor122,222. As an alternative, the etching process may etch away slightly more than the deposited dielectric thickness to result in an over-etch, resulting in the dielectric cap being slightly recessed within the via (not shown).

FIGS.1and22show the result of the next operation in which a top electrode128,228is formed on the memory elements100,200. The top electrode128,228can be formed by deposition of the electrode material followed by patterning. The top electrode128,228material can be tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), nickel (Ni), titanium (Ti), ruthenium (Ru), molybdenum (Mo), or any other suitable conductive material. The metal contact can further include a barrier layer. The barrier layer can be TiN, TaN, HfN, NbN, WN, WCN, or combinations thereof. In various embodiments, the barrier layer can be deposited in the trench(es) by ALD, CVD, MOCVD, PECVD, or combinations thereof. In various embodiments, the top electrodes can be formed by ALD, CVD, PVD, and/or plating. Patterning the top electrodes can be done, for example, by RIE. Alternatively, the top electrodes can be formed by damascene process, i.e., depositing a dielectric material (not shown), forming a trench/via in the dielectric material, and filling the trench/via with a conducting material. Top electrodes128,228circumferentially surround, and are connected to peripheral portions of, the phase change material layers112,212and resistive liners110,210.

FIGS.1and22show the finished phase change memory elements100,200fabricated using the method operations as described above. Memory elements100,200have at least one phase change material layer112,212, and heater conductor122,22, wherein at least a portion of the heater conductor122,222is circumferentially surrounded by the at least one phase change material layer112,212. The phase change material layer112,212has a donut-shape.FIGS.2A and2Bshow the donut-shape. One feature and advantage of the donut-shape of the phase change material layer112,212is that the heater conductor122,222is located along an inner surface of the phase change material layer112,212and is surrounded by the phase change material layer112,212. The heater conductor122,222is configured to heat a portion of the at least one phase change material layer112,212and change the portion of the phase change material layer112,212from a crystalline phase to an amorphous phase. The configuration of the phase change material layer112,212, surrounding the heater conductor122,222results in a reduction in contact area compared to previous designs that had a heater conductor located underneath (and in parallel with) a phase change material layer, for example. The reduction in contact area results in a corresponding reduction in reset current. Memory elements100,200, also have top electrode128,228circumferentially surrounding and connected to the at least one phase change material layer112,212, and bottom electrode104,204in contact with the heater conductor122,222.

Memory elements100,200are self-aligned as a result of the method of fabrication, and have a symmetrical arrangement. An advantage of the self-aligned, symmetrical structure is a reduction in variability of characteristics of phase change memory devices such as resistance.FIGS.2A and2Bshow the symmetrical arrangement.

Memory elements100,200have at least one resistive liner110,210in contact with the at least one phase change material layer112,212. In alternative embodiments, the resistive liners110,210can be left out of memory elements100,200. The advantage of the symmetrical nature of the phase change memory layer112,212is still present in such alternative embodiments even without the resistive liners110,210. The advantage of the symmetrical feature is reduction in variability. However, if the resistive liners110,210are included in the memory elements100,200, an additional advantage of reduction of resistive drift is possible.

It will be understood thatFIG.22presents, in schematic form, only a portion of a memory cell as finally fabricated and placed in use. Circuit elements are formed both above and below the portion shown in the figure.

Another embodiment of the disclosure is an alternative memory element300, and a method of fabricating the memory element300. The layers inFIG.23are labelled with a “3” as their first number rather than a “1” or “2” in the earlier described embodiments, and correspond to the layers in those earlier described embodiments. The discussion of the materials and methods of forming the corresponding layers also applies to the layers in memory element300, with the exception of the methods of forming phase change material layer312(i.e.,312-1,312-2,312-3) and resistive liner310(i.e.,310-1,310-2). Instead, as shown inFIG.23, a first phase change material layer312-1is deposited, followed by a first resistive liner310-1, followed by a second phase change material layer312-1, a second resistive liner310-2, and a third phase change material layer312-3. The advantage of the multiple layers of phase change material and resistive liner, in an alternating fashion, is that it enables multiple states of the phase change memory as well as fine-tuning of the material property of each layer to improve device characteristics.

It will be understood thatFIG.23presents, in schematic form, only a portion of a memory cell as finally fabricated and placed in use. Circuit elements are formed both above and below the portion shown in the figure.