Multi-mode voltage pump and control

A multi-mode voltage pump may be configured to select an operational mode based on a temperature of a semiconductor device. The selected mode for a range of temperature values may be determined based on process variations and operational differences caused by temperature changes. The different selected modes of operation of the multi-mode voltage pump may provide pumped voltage having different voltage magnitudes. For example, the multi-mode voltage pump may operate in a first mode that uses two stages to provide a first VPP voltage, a second mode that uses a single stage to provide a second VPP voltage, or a third mode that uses a mixture of a single stage and two stages to provide a third VPP voltage. The third VPP voltage may be between the first and second VPP voltages, with the first VPP voltage having the greatest magnitude. Control signal timing of circuitry of the multi-mode voltage pump may be based on an oscillator signal.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a 35 U.S.C. § 371 National Stage Application of PCT Application No. PCT/CN2018/119102, filed Dec. 4, 2018, the entire contents of which are hereby incorporated by reference, in their entirety, for any purposes.

BACKGROUND

High data reliability, high speed of memory access, low power, and reduced chip size are features that are demanded from semiconductor memory. In some applications, circuits may use supply voltages having potential greater than that provided by an external voltage source. For example, some memory circuits may use higher internal voltages to activate access lines during a memory access operation. Voltage pump circuits may be included to generate the higher internal voltages. A difference between external voltage supply magnitudes and the higher internal voltage magnitudes used during operation may vary from application to application. In addition, efficiency of a voltage pump circuit may vary based on process and temperature differences. Thus, voltage pump circuits may be designed to provide sufficient margin to account for process, voltage, and temperature variation in order to meet operational voltage requirements. However, designing voltage pump circuits to operate assuming worst case scenarios may result in wasted power consumption in some applications.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Various embodiments of the present disclosure will be explained below in detail with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings that show, by way of illustration, specific aspects and embodiments of the disclosure. The detailed description includes sufficient detail to enable those skilled in the art to practice the embodiments of the disclosure. Other embodiments may be utilized, and structural, logical and electrical changes may be made without departing from the scope of the present disclosure. The various embodiments disclosed herein are not necessary mutually exclusive, as some disclosed embodiments can be combined with one or more other disclosed embodiments to form new embodiments.

FIG. 1is a schematic block diagram of a semiconductor device100as a memory device, in accordance with an embodiment of the present disclosure. The semiconductor device100may include a clock input circuit105, an internal clock generator107, an address command input circuit115, an address decoder120, a command decoder125, a plurality of row (e.g., first access line) decoders130, a memory cell array145including sense amplifiers150and transfer gates195, a plurality of column (e.g., second access line) decoders140, a plurality of read/write amplifiers165, an input/output (I/O) circuit170, and a voltage generator circuit190. The semiconductor device100may include a plurality of external terminals including address and command terminals coupled to command/address bus (C/A)110, clock terminals CK and/CK, data terminals DQ, DQS, and DM, and power supply terminals VDD, VSS, VDDQ, and VSSQ. The terminals and signal lines associated with the command/address bus110may include a first set of terminals and signal lines that are configured to receive the command signals and a separate, second set of terminals and signal lines that configured to receive the address signals, in some examples. In other examples, the terminals and signal lines associated with the command and address bus110may include common terminals and signal lines that are configured to receive both command signal and address signals. The semiconductor device may be mounted on a substrate, for example, a memory module substrate, a motherboard or the like.

The memory cell array145includes a plurality of banks BANK0-N, where N is a positive integer, such as 3, 7, 15, 31, etc. Each bank BANK0-N may include a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC arranged at intersections of the plurality of word lines WL and the plurality of bit lines BL. The selection of the word line WL for each bank BANK0-N is performed by a corresponding row decoder130and the selection of the bit line BL is performed by a corresponding column decoder140. The plurality of sense amplifiers150may be located for their corresponding bit lines BL and coupled to respective local I/O line pairs (LIOT/B) further coupled to respective main I/O line pairs (MIOT/B), via transfer gates TG195, which function as switches. The sense amplifiers150and transfer gates TG195may be operated based on control signals from decoder circuitry, which may include the command decoder125, the row decoders130, the column decoders140, any control circuitry of the memory cell array145of the banks BANK0-N, or any combination thereof.

The address/command input circuit115may receive an address signal and a bank address signal from outside at the command/address terminals via the command/address bus110and transmit the address signal and the bank address signal to the address decoder120. The address decoder120may decode the address signal received from the address/command input circuit115and provide a row address signal XADD to the row decoder130, and a column address signal YADD to the column decoder140. The address decoder120may also receive the bank address signal and provide the bank address signal BADD to the row decoder130and the column decoder140.

The address/command input circuit115may receive a command signal from outside, such as, for example, a memory controller, at the command/address terminals via the command/address bus110and provide the command signal to the command decoder125. The command decoder125may decode the command signal and generate various internal command signals. For example, the internal command signals may include a row command signal to select a word line, or a column command signal, such as a read command or a write command, to select a bit line.

Accordingly, when a read command is issued and a row address and a column address are timely supplied with the read command, read data is read from a memory cell in the memory cell array145designated by the row address and the column address. The read/write amplifiers165may receive the read data DQ and provide the read data DQ to the IO circuit170. The IO circuit170may provide the read data DQ to outside via the data terminals DQ together with a read data strobe signal at DQS. Similarly, when the write command is issued and a row address and a column address are timely supplied with the write command, and then the input/output circuit170may receive write data at the data terminals DQ together with a write data strobe signal at DQS and a data mask signal at DM and provide the write data via the read/write amplifiers165to the memory cell array145. Thus, the write data may be written in the memory cell designated by the row address and the column address.

Turning to the explanation of the external terminals included in the semiconductor device100, the clock terminals CK and /CK may receive an external clock signal and a complementary external clock signal, respectively. The external clock signals (including complementary external clock signal) may be supplied to a clock input circuit105. The clock input circuit105may receive the external clock signals and generate an internal clock signal ICLK. The clock input circuit105may provide the internal clock signal ICLK to an internal clock generator107. The internal clock generator107may generate a phase controlled internal clock signal LCLK based on the received internal clock signal ICLK and a clock enable signal CKE from the address/command input circuit115. Although not limited thereto, a DLL circuit may be used as the internal clock generator107. The internal clock generator107may provide the phase controlled internal clock signal LCLK to the IO circuit170. The IO circuit170may use the phase controller internal clock signal LCLK as a timing signal for determining an output timing of read data. In addition to the phase controller internal clock signal LCLK, the internal clock generator may generate various internal clock signals for memory operations.

The power supply terminals may receive power supply voltages VDD and VSS. These power supply voltages VDD and VSS may be supplied to a voltage generator circuit190. The voltage generator circuit190may generate various internal voltages, VPP, VOD, VARY, VPERI, and the like based on the power supply voltages VDD and VSS. The internal voltage VPP is mainly used in the row decoder130, the internal voltages VOD and VARY are mainly used in the sense amplifiers150included in the memory cell array145, and the internal voltage VPERI is used in many other circuit blocks. The IO circuit170may receive the power supply voltages VDDQ and VSSQ. For example, the power supply voltages VDDQ and VSSQ may be the same voltages as the power supply voltages VDD and VSS, respectively. However, the dedicated power supply voltages VDDQ and VSSQ may be used for the IO circuit170.

In some examples, the voltage generator circuit190includes a multi-mode voltage pump192that is configured to provide the VPP voltage. The VPP may be a pumped voltage that is greater than the external supply voltage VDD. The multi-mode voltage pump192may be a multi-stage voltage pump circuit that is configured to operate in different modes based on a temperature. In some examples, the multi-mode voltage pump192may be capable of operating in one of at least three different modes, including a single stage mode, a two stage mode, and a mixed stage mode. The multi-mode voltage pump192may be configured to select an operational mode based on a temperature of the semiconductor device received via a temperature signal Temp. In some embodiments, the temp signal may indicate a temperature measurement. In other examples, the temp signal may indicate a temperature range (e.g., high, medium, low, etc.). The selected mode for a range of temperature values may be determined during production, as each semiconductor device may experience differences in the VDD voltage magnitude and the VPP voltage requirements, as well as process variations during fabrication and operational differences caused by temperature changes. Thus, the temperature range to selected mode programming may be determined during production testing of the semiconductor device. The temperature range to selected mode programming may be programmed in a programmable element bank (e.g., fuse or anti-fuse bank circuit), in some examples. In some examples, a mode may be programmed for each temperature range. For example, a first selected mode may be programmed for a first temperature range (e.g., low), a second selected mode may be programmed for a second temperature range (e.g., medium), a third selected mode may be programmed for a third temperature range (e.g., high). Additional temperature ranges may be defined without departing from the scope of the disclosure. In some examples, a same mode may be programmed for more than one temperature range, or for all temperature ranges. The different selected modes of operation of the multi-mode voltage pump192may provide a VPP voltage having different voltage magnitudes. For example, the multi-mode voltage pump192may operate in a first mode that uses two stages to provide a first VPP voltage, the multi-mode voltage pump192may operate in a second mode that uses a single stage to provide a second VPP voltage, and the multi-mode voltage pump192may operate in a third mode that uses a mixture of a single stage and two stages to provide a third VPP voltage. The third VPP voltage may be between the first and second VPP voltages, with the first VPP voltage having the greatest magnitude. Control signal timing of circuitry of the multi-mode voltage pump192may be based on an oscillator signal OSC (e.g., provided from an oscillator circuit, such as an oscillator circuit included in the clock input circuit105).

FIG. 2is a block diagram of a multi-mode voltage pump292in accordance with an embodiment of the present disclosure. The multi-mode voltage pump292may include a mode control circuit202, a multi-mode control circuit204, and a multi-mode pump circuit206. The multi-mode voltage pump292may be included in the multi-mode voltage pump192ofFIG. 1, in some examples.

The mode control circuit202may be configured to receive a temperature signal Temp and to provide a mode control signal Mode to the multi-mode control circuit204. In some embodiments, the temp signal may indicate a temperature measurement. In this example, the mode control circuit202may include logic to convert the temp signal value to a range value that indicates one of a predefined set of temperature ranges (e.g., low, medium, high). For example, if the temperature is less than or equal to a first (e.g., low) temperature threshold, the mode control circuit202set the range value to “low”. If the temperature is greater than the first (e.g., low) temperature threshold and less than or equal to a second (e.g., high) temperature threshold, the mode control circuit202set the range value to “medium”. If the temperature is greater than the second (e.g., high) temperature threshold, the mode control circuit202set the range value to “high”. More or fewer than three predefined ranges may be implemented without departing from the scope of the disclosure. In other examples, the temp signal may provide the range value (e.g., low, medium, high, etc.) directly. The mode control circuit202may include logic that provides the mode selection signal having a value based on the range value. For example, the logic of the mode control circuit202may look up a selected mode based on the range value. In some examples, the mode control circuit202may include programmable elements (e.g., fuses or anti-fuses) that provide temperature range to selected mode programming. For example, based on a value read from the programmable elements, the mode control circuit202may read the programmable elements to select a first mode in response the range value having a first value, a second mode in response the range value having a second value, and a third mode in response the range value having a third value. In other examples, based on a value read from the programmable elements, the mode control circuit202may select a same mode for more than one or all of the range values. The value programmed into the programmable elements may be based on a VDD voltage magnitude, the VPP voltage requirements, process variations of a semiconductor device (e.g., the semiconductor device100ofFIG. 1) that includes the multi-mode voltage pump292, and operational differences caused by temperature changes.

The multi-mode control circuit204may receive the selected mode from the mode control circuit202via the Mode signal and an oscillator signal OSC. The multi-mode control circuit204may include logic to provide control signals to the multi-mode pump circuit206in response to timing of the OSC signal and based on the selected mode. The control signal transitions may cause circuitry of the multi-mode pump circuit206to operate according to the selecting mode. The multi-mode pump circuit206may include multiple stages and may be designed to operate in one of multiple modes. The selected mode may be controlled based on the control signals from the multi-mode control circuit204. In some examples, the modes may include two stages, a single stage, and a mixed stage mode (e.g., combination of two stages and a single stage).

FIGS. 3A-3Care block diagrams of mode control circuitry in accordance with an embodiment of the present disclosure. The mode control circuitry ofFIGS. 3A-3Cmay be included in the multi-mode voltage pump192ofFIG. 1and/or the multi-mode control circuit204ofFIG. 2, in some examples.FIG. 3Aincludes a clock signal logic circuit300that is configured to receive oscillator signals (e.g., OSC, OSCF, OSC90, and OSC90F) and to provide clock signals (e.g., PU, PUF, PU2, and PU2F). The value of the OSCF signal is complementary to the value of the OSC signal. The value of the OSC90F signal is complementary to the value of the OSC90signal. The value of the OSC90signal is 90 degrees out of phase from the value of the OSC signal. The clock signal logic circuit300includes a NAND gate301that is configured to provide the PU2signal based on values of the OSC and OSC90F signals using NAND logic. The clock signal logic circuit300further includes a NAND gate302that is configured to provide the PU2F signal based on values of the OSCF and OSC90signals using NAND logic. The clock signal logic circuit300further includes a NAND gate303that is configured to provide the PU signal based on values of the OSC and OSC90signals using NAND logic. The clock signal logic circuit300further includes a NAND gate304that is configured to provide the PUF signal based on values of the OSCF and OSC90F signals using NAND logic.

FIG. 3Bincludes a first stage control logic circuit1310, a first stage control logic circuit2330, and a latch circuit305. The latch circuit305may be a latch circuit having outputs controlled based on input signals received from the first stage control logic circuit1310and the first stage control logic circuit2330. The circuitry ofFIG. 3Bis configured to provide control signals PHN0, PHN0F, PHP0, and PHP0F based on values of the PU2and PU2F signals provided from the clock signal logic circuit300ofFIG. 3A. The PHN0, PHN0F, PHP0, and PHP0F control signals may be provided to a multi-mode pump circuit, such as the multi-mode pump circuit206ofFIG. 2. The first stage control logic circuit1310includes first serially-coupled logic circuitry (e.g., a NAND gate311, an inverter312, an inverter313, a NOR gate314, and an inverter315), second serially-coupled logic circuitry (e.g., an inverter316, an inverter317, and an inverter318), and third serially-coupled logic circuitry (e.g., an inverter319and an inverter320). The first serially-coupled logic circuitry may be configured to provide the PHN0F signal from the inverter315based on the PU2signal and a first drive signal DRVNAF (e.g., from an output of an inverter333of the first stage control logic circuit2330) received at an input of the NAND gate311, and a signal received at the NOR gate314from an output of the inverter317. The second serially-coupled logic circuitry may be configured to provide the PHP0signal from the inverter318based on a first output of the latch circuit305received at the inverter316. The third serially-coupled logic circuitry may be configured to control a first input of the latch circuit305based on the PU2signal received at the inverter319. The first serially-coupled logic circuitry may be further configured to provide a second drive signal DRVNBF at an output of the inverter313.

The first stage control logic circuit2330includes fourth serially-coupled logic circuitry (e.g., a NAND gate331, an inverter332, an inverter333, a NOR gate334, and an inverter335), fifth serially-coupled logic circuitry (e.g., an inverter336, an inverter337, and an inverter338), and sixth serially-coupled logic circuitry (e.g., an inverter339and an inverter340). The fourth serially-coupled logic circuitry may be configured to provide the PHN0signal from the inverter335based on the PU2F signal and the DRVNBF signal (e.g., from the output of the inverter313of the first stage control logic circuit1310) received at an input of the NAND gate331, and a signal received at the NOR gate334from an output of the inverter337. The fifth serially-coupled logic circuitry may be configured to provide the PHP0F signal from the inverter338based on a second output of the latch circuit305received at the inverter336. The sixth serially-coupled logic circuitry may be configured to control a second input of the latch circuit305based on the PU2F signal received at the329. The fourth serially-coupled logic circuitry may be further configured to provide the DRVNAF signal at an output of the inverter333.

FIG. 3Cincludes a second stage control logic circuit1350, a second stage control logic circuit2370, and a latch circuit306. The latch circuit306may be a latch circuit having outputs controlled based on input signals received from the second stage control logic circuit1350and the second stage control logic circuit2370. The circuitry ofFIG. 3Cis configured to provide control signals PHP, PHPF, PHN, PHNF, PHP2, PHP2F, PHN2, and PHN2F based on values of the PU and PUF signals provided from the clock signal logic circuit300ofFIG. 3A. The PHP, PHPF, PHN, PHNF, PHP2, PHP2F, PHN2, and PHN2F control signals may be provided to a multi-mode pump circuit, such as the multi-mode pump circuit206ofFIG. 2. The second stage control logic circuit1350includes first serially-coupled logic circuitry (e.g., a NAND gate351an inverter352, an inverter353, a NOR gate354, and an inverter355), second serially-coupled logic circuitry (e.g., a NAND gate356, an inverter357, an inverter358, a NOR gate359, and an inverter360), third serially-coupled logic circuitry (e.g., an inverter363, an inverter364, and an inverter365), and fourth serially-coupled logic circuitry (e.g., an inverter361and an inverter362). The first serially-coupled logic circuitry may be configured to provide an output signal from the inverter355to an XOR gate390and a multiplexer391based on the PU2signal inverted via an inverter366and a VDD1voltage received at an input of the NAND gate351, and a signal received at the NOR gate354from an output of the inverter364. The second serially-coupled logic circuitry may be configured to provide an output signal from the inverter360to the XOR gate390and a multiplexer392based on the PU, PUF, and second output LOUT2of the latch circuit306signals received at the NAND gate356and a signal received at the NOR gate359from an output of the NOR gate354. The output of the XOR gate390may be provided to the multiplexer391and the multiplexer392having a value based on the output signal from the inverter355and the output signal from the inverter360. In response to a value of the MODE signal, the multiplexer391may be configured to provide one of the output signal from the inverter355(e.g., mixed stage mode), the output of the XOR gate390(e.g., single stage mode), or a float signal (e.g., two stage mode) at an output as the PHN2F signal. In response to a value of the MODE signal, the multiplexer392may be configured to provide one of the output signal from the inverter360(e.g., mixed stage mode), the output of the XOR gate390(e.g., two stage mode), or a float signal (e.g., single stage mode) at an output as the PHNF signal. The third serially-coupled logic circuitry may be configured to provide the PHP signal based on a first output signal LOUT1of the latch circuit306received at the inverter363. The fourth serially-coupled logic circuitry may be configured to control a first input of the latch circuit306based on the PUF signal received at the inverter361.

The second stage control logic circuit2370includes fifth serially-coupled logic circuitry (e.g., a NAND gate371an inverter372, an inverter373, a NOR gate374, and an inverter375), sixth serially-coupled logic circuitry (e.g., a NAND gate376, an inverter377, an inverter378, a NOR gate379, and an inverter380), seventh serially-coupled logic circuitry (e.g., an inverter383, an inverter384, and an inverter385), and eighth serially-coupled logic circuitry (e.g., an inverter381and an inverter382). The fifth serially-coupled logic circuitry may be configured to provide an output signal from the inverter375to an XOR gate393and a multiplexer396based on the PUF signal inverted via an inverter386and a VDD1voltage received at an input of the NAND gate371, and a signal received at the NOR gate374from an output of the inverter384. The sixth serially-coupled logic circuitry may be configured to provide an output signal from the inverter380to an XOR gate393and a multiplexer395based on the PU, PUF, and LOUT1signals received at the NAND gate376and a signal received at the NOR gate379from an output of the NOR gate374. The inverted (e.g., via the inverter394) output of the XOR gate393may be provided to the multiplexer395and the multiplexer396having a value based on the output signal from the inverter375and the output signal from the inverter380. In response to a value of the MODE signal, the multiplexer395may be configured to provide one of the output signal from the inverter380(e.g., mixed stage mode), the inverted output of the XOR gate393(e.g., two stage mode), or a float signal (e.g., single stage mode) at an output as the PHN signal. In response to a value of the MODE signal, the multiplexer396may be configured to provide one of the output signal from the inverter375(e.g., mixed stage mode), the inverted output of the XOR gate393(e.g., single stage mode), or a float signal (e.g., two stage mode) at an output as the PHN2signal. The seventh serially-coupled logic circuitry may be configured to provide the PHPF signal based on the LOUT2signal received at the inverter383. The eighth serially-coupled logic circuitry may be configured to control a second input of the latch circuit306based on the PU signal received at the inverter381.

FIG. 4is a schematic diagram of a multi-mode pump circuit400in accordance with an embodiment of the present disclosure. The multi-mode pump circuit400may be included in the multi-mode voltage pump192ofFIG. 1and/or the multi-mode pump circuit206ofFIG. 2, in some examples. The multi-mode pump circuit400may be configured to receive the PHP0, PHP0F, PHN0, PHN0F, PHP, PHPF, PHN, PHNF, PHP2, PHP2F, PHN2, and PHN2F control signals from the logic circuits ofFIGS. 3B and 3C.

The multi-mode pump circuit400may include multiple stages, including a first stage410and a second stage440. The first stage410may include an upper portion412and a lower portion414. Based on a VDD2voltage, the upper portion412and the lower portion414may be configured to alternatively provide a first precharge voltage from output node428and a second precharge voltage from output node438, respectively, in response to the PHN0and PHP0signals and the PHN0F and the PHP0F signals. The upper portion412may include first precharge circuitry (e.g., an inverter421, a capacitor422, an n-type transistor425, and an n-type transistor426) that is configured to control a precharge of a first boost node in response to the PHN0signal. The upper portion412may further include first boost circuitry (e.g., an inverter423and a capacitor424) that is configured to control a pump voltage provided to the first boost node in response to the PHP0signal and a p-type transistor427that is configured to couple the first boost node to the output node428. The lower portion414may include second precharge circuitry (e.g., an inverter431, a capacitor432, an n-type transistor435, and an n-type transistor436) that is configured to control a precharge of a second boost node in response to the PHN0F signal. The lower portion414may further include second boost circuitry (e.g., an inverter433, a capacitor434) that is configured to control a pump voltage provided to the second boost node in response to the PHP0F signal and a p-type transistor437that is configured to couple the second boost node to the output node438.

The second stage440may include a first circuitry442and a second circuitry444. An upper portion446may include a first portion of the first circuitry442and a first portion of the second circuitry444. A lower portion448may include a second portion of the first circuitry442and a second portion of the second circuitry444. In a first mode that uses the first circuitry442and a portion of the second circuitry444(e.g., via the PHN2, PHN2F, PHP, and PHPF signals), based on the VDD1voltage, the upper portion446and the lower portion448may be configured to alternatively provide a first pumped voltage from output node462and a second pumped voltage from output node482, respectively, having a value equal to twice the VDD1voltage in response to the PHN2F and PHPF signals and the PHN2and the PHP signals. In a second mode that uses the first stage410and the second circuitry444(e.g., via the PHN0, PHN0F, PHP0, PHP0F, PHN, PHNF, PHP, and PHPF signals), based on the precharge voltages from the output nodes428and438, the upper portion446and the lower portion448may be configured to alternatively provide the first pumped voltage from output node462and a second pumped voltage from output node482, respectively, having a value equal to twice the VDD1voltage plus the VDD2voltage in response to the PHN0, PHP0, PHNF and PHPF signals and the PHN0F, PHP0F, PHN, and the PHP signals.

Within the upper portion446, the first circuitry442may include an inverter451, a capacitor452, a n-type transistor453, and a n-type transistor454that are configured to control a precharge of a third boost node in response to the PHN2F signal based on the VDD1voltage. Within the upper portion446, the second circuitry444may include first precharge circuitry (e.g., an inverter455, a capacitor456, a n-type transistor459, and a n-type transistor460) that is configured to control a precharge of the third boost node in response to the PHNF signal based on the precharge voltage from the output node428. Within the upper portion446, the second circuitry444may further include first boost circuitry (e.g., an inverter457and a capacitor458) that is configured to control a pump voltage provided to the third boost node in response to the PHPF signal and a p-type transistor461that is configured to couple the third boost node to the output node462. The lower portion414may include an inverter431, a capacitor432, an n-type transistor435, and an n-type transistor436that are configured to control a precharge of a second boost node in response to the PHN0F signal.

Within the lower portion448, the first circuitry442may include an inverter471, a capacitor472, a n-type transistor473, and a n-type transistor474that are configured to control a precharge of a fourth boost node in response to the PHN2signal based on the VDD1voltage. Within the lower portion448, the second circuitry444may include second precharge circuitry (e.g., an inverter475, a capacitor476, a n-type transistor479, and a n-type transistor480) that is configured to control a precharge of the fourth boost node in response to the PHN signal based on the precharge voltage from the output node438. Within the lower portion448, the second circuitry444may further include second boost circuitry (e.g., an inverter477and a capacitor478) that is configured to control a pump voltage provided to the fourth boost node in response to the PHP signal and a p-type transistor481that is configured to couple the fourth boost node to the output node482.

In operation, the circuitry ofFIGS. 3A-3Cmay provide the control signals (e.g., the PHN0, PHN0F, PHP0, PHP0F, PHN, PHNF, PHN2, PHN2F, PHP, and PHPF signals) according to a selected mode of operation for the multi-mode pump circuit multi-mode pump circuit400. The multi-mode pump circuit400may be configured to operate in the selected mode of operation in response to the control signals. In a first (e.g., single stage) mode, the first pumped voltage from the output node462and the second pumped voltage from the output node482may be controlled using the first circuitry442to precharge the third and fourth boost nodes and the first and second boost circuitry of the second circuitry444to boost the third and fourth boost nodes (e.g., excludes the first stage410and the first and second precharge circuitry of the second circuitry444). The first pumped voltage from the output node462and the second pumped voltage from the output node482may have a magnitude that is the VDD1+VDD1voltage while operating in the first mode. In some examples, the VDD1voltage is 1.8 volts.

In a second (e.g., two stage) mode, the first pumped voltage from the output node462and the second pumped voltage from the output node482may be controlled using the first stage410and the first and second precharge circuitry of the second circuitry444to precharge the third and fourth boost nodes and the first and second boost circuitry of the second circuitry444to boost the third and fourth boost nodes (e.g., excludes the first circuitry442). The precharge voltage provided from the first stage410at the output nodes428and438may have a magnitude that is the VDD1voltage added to the VDD2voltage. The first pumped voltage from the output node462and the second pumped voltage from the output node482may have a magnitude that is the VDD1+VDD1voltage plus the VDD2voltage while operating in the first mode. In some examples, the VDD2voltage is 1 volt.

In a third (e.g., mixed stage) mode, the first pumped voltage from the output node462and the second pumped voltage from the output node482may be controlled using a combination of 1) the first circuitry442and2) the first stage410and the first and second precharge circuitry of the second circuitry444to precharge the third and fourth boost nodes, and the first and second boost circuitry of the second circuitry444to boost the third and fourth boost nodes, respectively. For example, during the precharge phase in the second stage440, the third and fourth boost nodes may be initially precharged via the first circuitry442(e.g., for one-quarter of a clock cycle) based on the VDD1voltage, and then may subsequently precharged via the first and second precharge circuitry of the second circuitry444(e.g., for one-quarter of a clock cycle) based on the precharge voltage (e.g., VDD1+VDD2) from the first stage410. The first pumped voltage from the output node462and the second pumped voltage from the output node482may have a magnitude that is between the voltage provided in the first mode and the voltage provided while in the second mode.

FIGS. 5A-5Care illustrations of exemplary timing diagrams500,501, and502, respectively, depicting control signal transition to control a voltage pump in various modes of operation for a multi-mode pump circuit in accordance with embodiments of the present disclosure. The timing diagrams500,501, and502may illustrate operation of a multi-mode controller and a multi-mode voltage pump, such as the multi-mode voltage pump192ofFIG. 1, the multi-mode control circuit204and the multi-mode pump circuit206, respectively, ofFIG. 2, the circuitry ofFIGS. 3A-3Band the multi-mode pump circuit400ofFIG. 4, respectively, or combinations thereof. The OSC and OSC90signals may correspond to the OSC and OSC90signals ofFIG. 3A, respectively. The PU, PUF, PU2, and PU2F signals may correspond to the PU, PUF, PU2, and PU2F signals ofFIGS. 3A-3C, respectively. The PHN0, PHP0, PHN2, PHN, and PHP signals may correspond to the PHN0, PHP0, PHN2, PHN, and PHP signals forFIGS. 3B, 3C, and 4, respectively. The Stg1Boost Node and Stg Boost node signals may correspond to voltages of the Boost Node1or Boost Node2and Boost Node3or Boost Node4, respectively, ofFIG. 4. For clarity, the following discussion of the timing diagrams500,501, and502may refer to circuitry ofFIGS. 3A-3B, andFIG. 4. Specifically, the PU, PUF, PU2, and PU2F signals depicting in the timing diagram500may be generated via the clock signal logic circuit300ofFIG. 3Abased on the OSC and OSC90(e.g., and complement) signals. The PHN0and PHP0signals depicted in the timing diagrams500,501, and502may be generated via the first stage control logic circuit1310, the latch circuit305, and the first stage control logic circuit2330ofFIG. 3B. The PHN2, PHN, and PHP signals depicted in the timing diagrams500,501, and502may be generated via the second stage control logic circuit1350, the latch circuit306, and the second stage control logic circuit2370ofFIG. 3C.

The timing diagram500ofFIG. 5Adepicts control signal transition to control a voltage pump in a mixed stage mode of operation for the multi-mode pump circuit. At time T1, the first stage (e.g., the first stage410) of the multi-mode pump circuit (e.g., the multi-mode pump circuit400) may begin a precharge operation in response to the PHN0signal (e.g., controlling the inverter421and the capacitor422, respectively) transitioning to a low logic level. Transition of the PHN0signal may be based on the clock signal logic circuit300ofFIG. 3. The precharge operation may include precharging voltage of the Stg1boost node (e.g., of the first stage410) to a VDD2voltage via the capacitor424.

At time T2, the first stage of the multi-mode pump circuit may begin a boost operation in response to the PHP0signal transitioning to a high logic level. The boost operation may include charging the voltage of the Stg1Boost Node to a VDD1+VDD2voltage via the capacitor424.

At time T3, a second stage (e.g., the second stage440) of the multi-mode pump circuit (e.g., the multi-mode pump circuit400) may begin a first part of a precharge operation in response to the PHN2signal (e.g., controlling the inverter471) transitioning to a low logic level. The first part of the precharge operation may include precharging a voltage of the Stg2Boost Node toward a VDD1voltage via the capacitor478.

At time T4, the second stage of the multi-mode pump circuit may begin a second part of a precharge operation in response to the PHN2signal transitioning to a high logic level and the PHN signal (e.g., controlling the inverter475) transitioning to a low logic level. The second part of the precharge operation may include precharging the voltage of the Stg2Boost Node toward the Stg1Boost Node voltage (e.g., the VDD1+VDD2voltage from the output nodes428or438) via the capacitor478. Each of the first and second parts of the second stage precharge operation may have a duration of one-quarter of a clock cycle of the OSC signal. A final precharge voltage may be between the VDD1voltage and the VDD1+VDD2voltage from the first stage.

At time T5, the second stage of the multi-mode pump circuit may begin a boost operation in response to the PHP signal (e.g., controlling the inverter477) transitioning to a high logic level. The boost operation may include charging the voltage of the Stg2Boost Node to voltage between the VDD1+VDD1voltage and the VDD1+VDD1+VDD2voltage via the capacitor478.

The timing diagram501ofFIG. 5Bdepicts control signal transition to control a voltage pump in a two-stage mode of operation for the multi-mode pump circuit (e.g., the multi-mode pump circuit400). While in a two-stage mode, a first precharge circuit (e.g., the first circuitry442) of a second stage (e.g., the second stage440) may be disabled by disabling the PHN2signal. At time T1, the first stage (e.g., the first stage410) of the multi-mode pump circuit may begin a precharge operation in response to the PHN0signal (e.g., controlling the inverter421) transitioning to a low logic level. The precharge operation may include precharging the Stg1Boost Node to a VDD2voltage via the capacitor424.

At time T2, the first stage of the multi-mode pump circuit may begin a boost operation in response to the PHP0signal transitioning to a high logic level. The boost operation may include charging the voltage of the Stg1Boost Node to a VDD1+VDD2voltage via the capacitor424.

At time T3, a second stage (e.g., the second stage440) of the multi-mode pump circuit may begin a precharge operation in response to the PHN signal (e.g., controlling the inverter475) transitioning to a low logic level. The precharge operation may include precharging the Stg1Boost Node voltage (e.g., the VDD1+VDD2voltage from the output nodes428or438) via the capacitor478.

At time T4, the second stage of the multi-mode pump circuit may begin a boost operation in response to the PHP signal (e.g., controlling the inverter477) transitioning to a high logic level. The boost operation may include charging the voltage of the Stg2Boost Node to the VDD1+VDD1+VDD2voltage via the capacitor478.

The timing diagram502ofFIG. 5Cdepicts control signal transition to control a voltage pump in a single-stage mode of operation for the multi-mode pump circuit (e.g., the multi-mode pump circuit400). While in single-stage mode, the first and second precharge circuitry of a second precharge circuit (e.g., the second circuitry444) of a second stage (e.g., the second stage440) may be disabled by disabling the PHN signal. In the single-stage mode, the first stage (e.g., the first stage410) is also not used. In some examples, the PHN0and PHP0signals may also be disabled while in the single-stage mode to reduce power consumption within the multi-mode pump circuit.

At time T1, a second stage (e.g., the second stage440) of the multi-mode pump circuit may begin a precharge operation in response to the PHN2signal (e.g., controlling the inverter471) transitioning to a low logic level. The first part of the precharge operation may include precharging a voltage of the Stg2Boost Node toward a VDD1voltage via the capacitor478.

At time T2, the second stage of the multi-mode pump circuit may begin a boost operation in response to the PHP signal (e.g., controlling the inverter477) transitioning to a high logic level. The boost operation may include charging the voltage of the Stg2Boost Node to the VDD1+VDD1voltage via the capacitor478.

The timing diagrams500,501, and502ofFIGS. 5A-5Care exemplary for illustrating operation of various described embodiments. Although the timing diagrams500,501, and502depict a particular arrangement of signal transitions of the included signals, one of skill in the art will appreciate that additional or different transitions may be included in different scenarios without departing from the scope of the disclosure. Further, the depiction of a magnitude of the signals represented in the timing diagrams500,501, and502are not intended to be to scale, and the representative timing is an illustrative example of a timing characteristics.

Although this invention has been disclosed in the context of certain preferred embodiments and examples, it will be understood by those skilled in the art that the inventions extend beyond the specifically disclosed embodiments to other alternative embodiments and/or uses of the inventions and obvious modifications and equivalents thereof. In addition, other modifications which are within the scope of this invention will be readily apparent to those of skill in the art based on this disclosure. It is also contemplated that various combination or sub-combination of the specific features and aspects of the embodiments may be made and still fall within the scope of the inventions. It should be understood that various features and aspects of the disclosed embodiments can be combined with or substituted for one another in order to form varying mode of the disclosed invention. Thus, it is intended that the scope of at least some of the present invention herein disclosed should not be limited by the particular disclosed embodiments described above.