MRAM device structure employing thermally-assisted write operations and thermally-unassisted self-referencing operations

A thermally-assisted MRAM structure which is programmable at a writing mode operating temperature is presented and includes an anti-ferromagnet, an artificial anti-ferromagnet, a barrier layer, and a free magnetic layer. The anti-ferromagnet is composed of a material having a blocking temperature Tb which is lower than the writing mode operating temperature of the magnetic random access memory structure. The artificial anti-ferromagnet is magnetically coupled to the anti-ferromagnet, and includes first and second magnetic layers, and a coupling layer interposed therebetween, the first and second magnetic layers having different Curie point temperatures. The barrier layer is positioned to be between the second magnetic layer and the free magnetic layer.

TECHNICAL FIELD

The present invention relates to magnetic random access memory (MRAM) cells, and more particularly to thermally-assisted MRAM cells employing thermally-unassisted self-referencing operations, methods of operation, and manufacture.

BACKGROUND

Magnetic random access memory (MRAM) devices are emerging as possible replacements for conventional RAM memory structures such as dynamic and static RAM structures. MRAM devices exhibit fast access speeds and greater immunity to radiation compared to conventional DRAM and SRAM structures, and do not require applied power to retain their logical state.

Thermally-assisted writing represents a conventional MRAM programming technique in which a heating current is supplied across the MRAM's barrier layer, the resistance of which causes the storage layer to heat to a predefined temperature. The free magnetic layer or the MRAM cell is preferably constructed from a material which exhibits a decreasing magnetic coercivity with increasing temperature, such that when the storage layer is sufficiently heated, lower magnitude writing currents can be used to re-orient the existing magnetic polarization of the storage layer.

Self-referencing is a technique also used in optimizing the performance of an MRAM device, and particularly, reading accuracy. In this technique, an MRAM cell undergoes operations in which the cell resistance is compared to resistances of the same or a similar cell when in a logical 1 and/or a logical 0 state. In a typical operation, the resistance corresponding to an initial state of the MRAM is stored, and subsequently a logical 1 is written to the cell and the resulting resistance stored. Similarly, a logical 0 may be written to the cell, and the result stored. The resistance corresponding to the MRAM's original state is subsequently compared against the resistance corresponding to the logical 1 or 0 self-reference measurements, and the logical state corresponding to the resistance having the closest correlation thereto is deemed to be the logical state of the MRAM cell.

As self-referencing operations include a programming phase in which logical 0 and/or 1 states are written to the MRAM cell, the aforementioned thermal-assist process is conventionally used to write the 0 and 1 logical states during this process. Thermally-assisted self-referencing presents difficulties, as it requires heating the MRAM cell to write either a 0 or 1 to the MRAM cell, waiting a predefined period to allow the cell to cool, and reading the cell. The process can be shortened if the MRAM cell is formed (e.g., with a heat sink) such that the cooling process occurs faster. In such an arrangement, however, the aforementioned thermally-assisted writing process is negatively impacted, as heating during the programming process will occur more slowly and require more energy in order to heat the MRAM cell to the required temperature.

SUMMARY OF THE INVENTION

In a representative embodiment of the invention, a thermally-assisted MRAM structure which is programmable at a writing mode operating temperature is presented and includes an anti-ferromagnet, an artificial anti-ferromagnet, a barrier layer, and a free magnetic layer. The anti-ferromagnet includes a material having a blocking temperature Tbwhich is lower than the writing mode operating temperature of the magnetic random access memory structure. The artificial anti-ferromagnet is magnetically coupled to the anti-ferromagnet, and includes first and second magnetic layers, and a coupling layer interposed therebetween, the first and second magnetic layers having different Curie point temperatures. The barrier layer is positioned to be adjacent to the second magnetic layer, and the free magnetic layer is positioned to be adjacent to the barrier layer.

These and other features of the invention will be better understood in view of the following drawings and detailed description.

For clarity, previously identified features retain their reference indicia in subsequent drawings.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

Various embodiments of the present invention provide a thermally-assisted MRAM structure that enables device self-reference without thermal heating. Thermal-assisted writing permits lower writing current, and accordingly, implementation of smaller current handling transistors and higher density MRAM memory devices and arrays. A greater degree of thermal insulation can be provided to the MRAM structure, since thermal heating is not required during self-referencing. Greater MRAM thermal insulation may permit the MRAM device to heat more quickly and efficiently during thermally-assisted write operations, thereby increasing programming speed and reducing power consumption.

Exemplary MRAM Device Structure

FIG. 1illustrates an exemplary embodiment of a MRAM device structure in accordance with the present invention. As shown, the MRAM structure100includes an anti-ferromagnet110(AFM), an artificial anti-ferromagnet120(AAF) magnetically coupled to the anti-ferromagnet110, a barrier layer130adjacent to the artificial anti-ferromagnet; and a free magnetic layer140adjacent to the barrier layer130. It will be understood that the order of layers of the MRAM structure100may be reversed in some embodiments. The MRAM structure100is preferably formed as a part of a monolithic integrated circuit process, for example, as further described below. As used herein, the term “magnetically coupled” refers to the orientation of particular components in a manner such that a magnetic field can be coupled (e.g., ferromagnetically, anti-ferromagnetically) between the described components. Such an orientation includes components/layers which directly contact each other, as well as those components/layers which are spaced apart, perhaps by intervening structures, but which still are operable to provide magnetic coupling therebetween.

In a particular embodiment, the AFM110is formed from a material having a blocking temperature (Tb) which is lower than the intended writing mode operating temperature (Twrite) of the magnetic random access memory structure100. As known in the art, a material's blocking temperature is the temperature above which the material exhibits a sufficiently low magnetic coercivity so that the material's magnetic polarization is readily re-oriented in the presence of a magnetizing field. The description “writing mode operating temperature” (Twrite) refers to the intended temperature at which the MRAM structure100operates during a thermally-assisted write operation. In a particular embodiment, Twriteranges from 150-300° C., for example, 250° C. Further particularly, exemplary AFM materials exhibiting a blocking temperature below these temperatures include anti-ferromagnetic materials such as manganese alloys (e.g., iridium manganese (IrMn), iron manganese (FeMn), rhodium manganese (RhMn), platinum manganese (PtMn), platinum palladium manganese (PtPdMn), nickel manganese (NiMn), NixFeyIrzMn, and the like. Those skilled in the art will appreciate that other programming mode operating temperatures and AFM materials may be used in alternative embodiments of the present invention.

Magnetically coupled to the AFM110, the artificial anti-ferromagnet (AAF)120includes a first magnetic layer122, a second magnetic layer124, and a coupling layer126interposed therebetween. The AAF may include or be composed of a Co/non-magnetic metal/Co system, or other suitable materials. For example, the first and second magnetic layers122and124may include materials such as nickel (Ni), iron (Fe), or cobalt (Co), or combinations thereof (e.g., nickel iron (NiFe), cobalt iron (CoFe) and nickel iron cobalt (NiFeCo), and the coupling layer126may be formed from ruthenium (Ru), osmium (Os), rhenium (Re), chromium (Cr), rhodium (Rh), or copper (Cu), or combinations thereof. Those skilled in the art will appreciate that other materials may be used in alternative embodiment of the present invention.

In some embodiments, the first and second magnetic layers122and124may include materials having different Curie point temperatures (TC). In some embodiments, the Curie point temperature of either the first or second magnetic layers122or124may be below the intended write mode operating temperature of the structure100, the other magnetic layer122or124having a Curie point temperature above the programming mode operating temperature. As an example, the first magnetic layer122may include NiFe, or CoFeB, and exhibit a TCabove Twrite, and the second magnetic layer124may include Co alloys, such as CoFeSiMoB, CoV, CoCr, and exhibit a TC(e.g., 200-230° C.) below Twrite. In another example, the first magnetic layer122may include a material having a TCbelow Twrite, and the second magnetic layer124may include a material having a TCabove Twrite. In some embodiments of this later instance in which the Curie point temperature of the first magnetic layer122is below the writing mode operating temperature (i.e., Twrite>TC≧Tb), the blocking temperature of the AFM110is lower than or equal to the Curie point temperature of the first magnetic layer122. This arrangement ensures that the AFM110does not pin the first magnetic layer122during the write mode.

Completing the MRAM structure100, the barrier layer130is adjacent to the second magnetic layer124, and a free magnetic layer140is adjacent to the barrier layer130, to form a tunneling magnetoresistive (TMR) element. The barrier layer130provides the magnetic tunneling junction, the electrical resistance across which determines the logical state of the structure100. The electrical resistance may be determined by the relative orientations of the magnetic fields between the second magnetic layer124and the free magnetic layer140. Embodiments of the barrier layer130include silicon dioxide (SiO2), aluminum oxide (Al2O3), magnesium oxide (MgO), hafnium oxide (HfO2), boron oxide (B2O3), tantalum oxide (Ta2O5), zinc oxide (ZnO2) and other oxides, nitrides, or other suitable dielectrics, and the like. Exemplary embodiments of the free magnetic layer140may include nickel (Ni), iron (Fe), or cobalt (Co), or combinations thereof. In other embodiments, the free magnetic layer140may include Co alloys, such as CoFeSiMoB, CoV, CoCr which exhibit a TCbelow Twrite. Depending upon the construction of the MRAM structure100, interconnects150aand150bmay be used to provide contact to the bit line structures, and, via a selection transistor or other selection device (not shown), to the word line structures (not shown). In some embodiments, interconnects150aand150bmay be composed of a TaN material, although other materials may be used in accordance with various embodiments of the present invention. Furthermore, the MRAM structure100may be implemented in an array to provide a memory device of any particular size, for example, 1 GB or more of storage capacity. In such an application, interface contacts150aand150bmay be connected (directly or indirectly, such as through a selection transistor) to bit and word lines which interconnect a multiplicity of MRAM structures100therealong.

Exemplary Methods for Thermally-Assisted Writing and Thermally-Unassisted Self-Referencing

FIGS. 2A and 2Billustrate exemplary methods for performing thermally-assisted writing and thermally-unassisted self-referencing operations, respectively, in an MRAM device in accordance with an embodiment of the present invention. Each of the methods may occur at different times; for example, cell writing operations described inFIG. 2Amay occur before or after cell self-referencing operations described inFIG. 2B, or visa versa.

Referring toFIG. 2A, a cell writing operation is initiated at212by supplying a heating current (in the form of a pulse of a predefined duration in one embodiment of the invention) to the MRAM device structure100, the heating current operable to heat the structure100to the desired writing mode operating temperature Twrite. Once the structure100has been heated to the predefined temperature Twrite, the magnetic moments of the free magnetic layer140and one of the first or second magnetic layers having a low TC(e.g., the second layer124) may be substantially reduced or eliminated, as Twrite>low TC. In addition, the AFM110will lose its pinning ability, permitting the first magnetic layer122to be switched by an applied magnetic field. Accordingly, the AAF120may become unbalanced at the elevated writing mode operating temperature. Further, because the free magnetic layer140and the first magnetic layer122have a TCbelow Twrite, they do not generate a magnetic field, which would interfere with and require a stronger applied magnetic field.

At214, a magnetic field is applied to the MRAM structure100(e.g., by supplying current in a particular direction to or proximate to the MRAM structure100), the applied magnetic field operable to re-orient the magnetic polarization of the first (i.e., higher TC) magnetic layer122.

At216, the MRAM structure100is cooled below Twrite, and the orientation of the first magnetic layer122determines the orientation of the AFM110(in parallel therewith), and the second magnetic layer124(in anti-parallel therewith). In this manner, the AAF120returns to a balanced state.

In some embodiments, heating and writing currents are applied at different times, the timing of each of which is controlled to allow sufficient heating of the MRAM structure prior to application of the programming magnetic field. Such timing, of course, will depend upon the particular construction of the MRAM structure100, but in an exemplary embodiment the writing/field pulse is delayed approximately 0 to 5 ns behind the heating pulse.

FIG. 2Billustrates an exemplary method for performing a thermally-unassisted self-referencing operation in the MRAM device ofFIG. 1in accordance with an embodiment of the present invention. At222, a self-referencing operation is initiated, whereby the MRAM structure's initial data (e.g., cell resistivity) is read and stored. Cell reading may occur, for example, by supplying a current to the word or bit line, and measuring the resultant voltage thereacross to determine the cell's resistivity, or alternatively, applying a predefined voltage across the structure and measuring the current supplied therethrough.

Next at224, the selected structure/cell is programmed without additional thermal heating, the selected structure operating at a self-referencing mode operating temperature TSRwhich is below the writing mode operating temperature Twrite. The term “self-referencing mode operating temperature” refers to an operating temperature of the selected MRAM structure100when not supplied a heating current or signal, as is done during the writing mode. The self-referencing temperature TSRmay be the ambient operating temperature of the MRAM device, which may range, for example, from 0° to 100° C., and in some embodiments may be between 10° and 50° C.

In some embodiments, at224, the selected cell is programmed with a logical 0 or 1 by exposing the free magnetic layer140to a magnetic field of a particular orientation. The free magnetic layer140can be switched at an unheated temperature by the supplied magnetic field, as the first and second magnetic layers122and124are balanced at the self-reference mode operating temperature, as this temperature is lower than the writing temperature. Because the AAF120is balanced at the self-referencing operating temperature TSR, the magnetic polarization of the free magnetic layer140may be easily re-oriented by the applied magnetic field without heating the MRAM structure100.

At226, the content (i.e., the resistivity) of the structure is read and stored as a first reference value. At228, a determination is made as to whether a second reference value has been programmed into the cell, and if so, the process returns to224where the MRAM structure/cell is programmed (without applied heating) with a second logical value in the same manner as described above, that content being subsequently read and stored as a second reference in a second iteration of224. At230, the original content of the memory structure is compared with each of the first and second reference values, the value of the original content being assigned the logical value corresponding to the reference value which most closely correlates therewith. In this manner, the structure100can undergo the conventional self-referencing operations: write 1 (no heat)/read, write 0 (no heat)/read to accurately determine the existing state of the selected MRAM cell without the heating the cell.

Exemplary Method of Manufacture

FIG. 3illustrates an exemplary method for constructing the MRAM device structure ofFIG. 1in accordance with an embodiment of the present invention. No particular order is indicated in the following process operations, as any of the following processes may occur before, after, or concurrently with other of the described operations in accordance with known fabrication processes. For example, the operations may generally be performed in an order that is the reverse of the order shown in the figure or described below, or in any other suitable order. The following operations may be employed as a part of a semiconductor fabrication process in which a plurality of device structures is monolithically formed on an integrated substrate.

Referring toFIG. 3, at322an anti-ferromagnet (AFM)110is formed having a blocking temperature Tbwhich is below the writing mode operating temperature of the MRAM structure. In some embodiments, the anti-ferromagnet includes IrMn, which is deposited at a thickness of 20 to 80 Å. Depending upon construction of the MRAM structure, the AFM110may be deposited on interconnect150b, which may include, e.g., TaN deposited at 5-100 nm in thickness, and which provides interconnectivity between the MRAM structure100and a select transistor or other selection structure connected directly or indirectly to bit and/or word line structures.

At324, an artificial anti-ferromagnet (AAF)120is formed so as to be magnetically coupled to the AFM110, the AAF120formed so as to include two magnetic layers having different Curie point temperatures. In some embodiments of this process, one of the magnetic layers is formed from a material having a Curie point temperature below the writing mode operation temperature of the MRAM structure100, and a second of the magnetic layers is constructed from a material having a Curie point temperature higher than the writing mode operating temperature. In such an embodiment, the first magnetic layer122may include materials such as CoFe, CoFeB, NiFeCo, or multiple sub-layers of such materials, such as CoFe/CoFeB sub-layers. Such materials or sets of sub-layers have a TCabove typical thermally-assisted temperatures of 250° C., and are deposited at a thickness of approximately 1-5 nm. The second of the magnetic layers124may be composed of Co alloys, such as CoFeSiMoB, CoV, CoCr, or multiple sub-layers. These materials and/or sub-layers have a TCbelow 250° C. and are deposited at a thickness of approximately 1-5 nm. The coupling layer126, in one embodiment, includes or is composed of 0.5-1.5 nm thick Ru. Other materials and deposition dimensions will be apparent to those skilled in the art.

In another embodiment of324, the first magnetic layer122includes or is composed of a low TC(i.e., <Twrite) material, and the second magnetic layer124includes or is composed of a high TC(i.e., >Twrite) material. In such an embodiment, the first magnetic layer122has a TCgreater or equal to the blocking temperature Tbof the AFM110, and lower than the writing mode operating temperature, i.e., Twrite>TC≧Tb. In this embodiment, the first magnetic layer122includes or is composed of the aforementioned low TCCo alloys deposited at a thickness of 1-20 nm, and the second magnetic layer124includes or is composed of the aforementioned high TCmaterials, such as CoFe, CoFeB, NiFeCo, or other suitable materials, deposited at a thickness of 0.5-1.5 nm.

At326, a barrier layer130is formed adjacent to the AAF120, the barrier layer130being formed from materials such silicon dioxide (SiO2) aluminum oxide (Al2O3), magnesium oxide (MgO), haffiium oxide (HfO2), boron oxide (B2O3), tantalum oxide (Ta2O5), zinc oxide (ZnO2) and other oxides, nitrides, and the like. In some embodiments, the barrier layer130is formed from MgO at a thickness of 0.5-2 nm.

At328, a free magnetic layer140is formed adjacent to the barrier layer130. In some embodiments, the free magnetic layer140includes a low Curie temperature material, such as the aforementioned Co alloys of the second magnetic layer124, and is deposited at a thickness of 1-20 nm. In other embodiments of the invention in which the free magnetic layer includes or is composed of a high TCmaterial (i.e., TC>Twrite), it may be composed of CoFe, CoFeB, CoFeNi, or other suitable materials, and is deposited at a thickness of 1-5 nm.

Although not shown, the process may further include the deposition of the interconnect material (e.g., TaN)150aand150bto facilitate interconnection to the MRAM structure. Exemplary thicknesses of the interconnecting material would be in the range of 5-100 nm.

The described processes may be implemented in hardware, software, firmware or a combination of these implementations as appropriate. In addition, some or all of the described processes may be implemented as computer readable instruction code resident on a computer readable medium (removable disk, volatile or non-volatile memory, embedded processors, etc.), the instruction code operable to program a computer or other such programmable device to carry out the intended functions.