Semiconductor growth substrates and associated systems and methods for die singulation

Semiconductor growth substrates and associated systems and methods for die singulation are disclosed. A representative method for manufacturing semiconductor devices includes forming spaced-apart structures at a dicing street located between neighboring device growth regions of a substrate material. The method can further include epitaxially growing a semiconductor material by adding a first portion of semiconductor material to the device growth regions and adding a second portion of semiconductor material to the structures. The method can still further include forming semiconductor devices at the device growth regions, and separating the semiconductor devices from each other at the dicing street by removing the spaced-apart structures and the underlying substrate material at the dicing street.

TECHNICAL FIELD

The present technology is directed generally to semiconductor growth substrates and associated systems and methods for die singulation.

BACKGROUND

Solid state transducer (“SST”) devices are used in a wide variety of products and applications. For example, mobile phones, personal digital assistants (“PDAs”), digital cameras, MP3 players, and other portable electronic devices utilize SST devices for backlighting. SST devices are also used for signage, indoor lighting, outdoor lighting, and other types of general illumination. SST devices generally use light emitting diodes (“LEDs”), organic light emitting diodes (“OLEDs”), and/or polymer light emitting diodes (“PLEDs”) as sources of illumination, rather than electrical filaments, plasma, or gas.FIG. 1Ais a cross-sectional view of a conventional SST device10awith lateral contacts. As shown inFIG. 1A, the SST device10aincludes a substrate20carrying an LED structure11having an active region14, e.g., containing gallium nitride/indium gallium nitride (GaN/InGaN) multiple quantum wells (“MQWs”), positioned between N-type GaN15and P-type GaN16. The SST device10aalso includes a first contact17on the P-type GaN16and a second contact19on the N-type GaN15. The first contact17typically includes a transparent and conductive material (e.g., indium tin oxide (“ITO”)) to allow light to escape from the LED structure11. In operation, electrical power is provided to the SST device10avia the contacts17,19, causing the active region14to emit light.

FIG. 1Bis a cross-sectional view of another conventional LED device10bin which the first and second contacts17and19are opposite each other, e.g., in a vertical rather than lateral configuration. During formation of the LED device10b, a growth substrate (not shown), similar to the substrate20shown inFIG. 1A, initially carries an N-type GaN15, an active region14and a P-type GaN16. The first contact17is disposed on the P-type GaN16, and a carrier21is attached to the first contact17. The growth substrate is removed, allowing the second contact19to be disposed on the N-type GaN15. The structure is then inverted to produce the orientation shown inFIG. 1B. In the LED device10b, the first contact17typically includes a reflective and conductive material (e.g., silver or aluminum) to direct light toward the N-type GaN15. An optional converter material and an encapsulant can then be positioned over one another on the LED structure11. In operation, the LED structure11can emit energy at a first wavelength (e.g., blue light) that stimulates the converter material (e.g., phosphor) to emit energy at a second wavelength (e.g., yellow light). Energy at the first and second wavelengths is combined to generate a desired color of light (e.g., white light).

One drawback associated with the foregoing techniques is that growing semiconductor materials to produce the LED structure11can be difficult to perform in a uniform fashion. For example, at least some conventional techniques tend to produce an uneven distribution of semiconductor material on the growth substrate. This in turn can cause non-uniformities in the subsequent manufacturing steps used to produce the SST devices, and/or non-uniformities in the light production and/or other characteristics of the SST devices. Accordingly, there remains a need for improved SST device manufacturing techniques.

DETAILED DESCRIPTION

Specific details of several semiconductor growth substrates and associated systems and methods for die singulation are described below. In particular embodiments, the die singulation techniques described below are performed on solid state transducer (SST) dies and devices. The term “SST” generally refers to solid state transducers or other devices that include a semiconductor material as the active medium to convert between electrical energy and electromagnetic radiation in the visible, ultraviolet, infrared, and/or other spectra. For example, SST devices include solid state light emitters (e.g., LEDs, laser diodes, etc.) and/or other sources of emission other than electrical filaments, plasmas, or gasses. The term SST can also include solid state devices that convert electromagnetic radiation into electricity. Additionally, depending upon the context in which it is used, the term “substrate” can refer to a wafer-level substrate or to a singulated device-level substrate. A person skilled in the relevant art will also understand that the technology may have additional embodiments, and that the technology may be practiced without several of the details of the embodiments described below with reference toFIGS. 2A-5.

FIG. 2Ais a partially schematic, cross-sectional illustration of a growth substrate220suitable for epitaxially growing materials used to form SST devices and/or other semiconductor devices. The techniques for growing materials can include selective area epitaxial growth (SAG), epitaxial lateral overgrowth (ELOG), lateral epitaxial overgrowth (LEO), and pendeo-epitaxy. These techniques are typically used to form thin films from elements in Groups III and V of the periodic table. The growth substrate220can have the form of a wafer and can include multiple device growth regions230at which the semiconductor devices are formed. Street regions240are positioned between neighboring device growth regions230. The street regions240provide spaces between the neighboring device growth regions230that accommodate the tools and processes used to separate the SST devices formed at these regions. Aspects of the present technology are directed to forming spaced-apart structures, e.g., “dummy” or sacrificial structures, at the street regions240to improve the uniformity with which materials are grown or otherwise formed at the device growth regions230, as will be described in further detail below.

In a particular embodiment, the growth substrate220can include silicon or another substrate material (e.g., an engineered substrate) suitable for growing gallium nitride and/or gallium nitride compounds that are typically used to form SST devices. In other embodiments, the growth substrate220can include other suitable materials depending upon the nature of the materials grown on it. In general, the growth substrate220is itself crystalline and supports the growth of a crystalline material. In many instances, the lattice structure and/or coefficient of thermal expansion (CTE) of the growth substrate220is different than that of the material formed on it. Either or both of these differences can create stresses in the materials formed on the growth substrate220and can adversely affect the resulting dies and/or the processes for forming the dies. For example, the stresses can cause substrate wafers to “bow,” which interferes with subsequent process steps and/or with the uniformity of the resulting devices. Accordingly, in addition to or in lieu of improving the uniformity with which growth materials are formed on the growth substrate220, the dummy structures described below can reduce stress build-up in such materials by interrupting an otherwise continuous material layer.

FIG. 2Bis an enlarged, partially schematic, cross-sectional illustration of a portion of the growth substrate220shown inFIG. 2A. InFIG. 2B, a mask221has been applied to the illustrated street regions240(one of which is visible inFIG. 2B). The mask221can include apertures222at which dummy structures will be formed during subsequent processing steps.

FIG. 2Cillustrates an embodiment of the growth substrate220described above with reference toFIG. 2Bafter a seed material223has been disposed on it. The seed material223can include first portions223aat the device growth regions230, and second portions223bat the street region240. At the street region240, the second portions223bof the seed material223are disposed in the apertures222of the mask221. Accordingly, the second portions223bcan support additional materials that together form dummy structures241at the street region240. In a particular embodiment, the seed material223includes aluminum nitride, and in other embodiments, the seed material223can include other suitable elements or compounds. The seed material223can be deposited and/or processed to be co-planar with the adjacent mask221, as shown inFIG. 26, or it can be recessed below or extend above the mask221.

InFIG. 2D, a first semiconductor material224has been disposed on the growth substrate220. Accordingly, the first semiconductor material224can include first portions224aat the device growth regions240, and one or more second portions224bat the street region240. In one aspect of this embodiment, the mask221can remain in place during this process (and ensuing processes), and in other embodiments, the mask221can be removed, e.g., if doing so does not cause bridging between adjacent dummy structures during subsequent processing steps. In any of these embodiments, the first semiconductor material224is disposed on the first portion223aof the seed material223at the device growth regions230, and on the second portions223bof the seed material223and the street region240. The first semiconductor material223can include an undoped or unintentionally doped gallium nitride material (u-GaN) and/or another material suitable for growing additional material volumes used to form the resulting SST or other device. In other embodiments, the first semiconductor material224can be eliminated, and other suitable materials (e.g., the second semiconductor material described further below) can be disposed directly on the seed material223. In still further embodiments, the seed material223can be eliminated and an appropriate semiconductor material can be disposed directly on the growth substrate220. In any of these embodiments, the first semiconductor material224and/or other materials carried by the growth substrate220can be disposed using any of a variety of suitable techniques, including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD) and atomic layer deposition (ALD). In any of these embodiments, the first portions224acan form or define first exposed surfaces at the device growth regions240, and the second portions224bcan form or define second exposed surfaces at the spaced-apart structures241. The spaced-apart structures241can accordingly attract material that would otherwise be disposed at the growth regions240.

InFIG. 2E, a second semiconductor material225has been disposed on the growth substrate220. In particular, first portions225aof the second semiconductor material225have been disposed at the device growth regions230, and second portions225bof the second semiconductor material225have been disposed at the street region240. In particular embodiments, the second semiconductor material225can include silicon gallium nitride (Si—GaN) or another N-type GaN material. In other embodiments, the second semiconductor material225can include other elements or compounds.

As shown inFIG. 2E, the second portion225aof the second semiconductor material225can have a generally uniform thickness, e.g., the same or generally the same thickness at both an edge region231(adjacent to the street region240) and at positions spaced further away from the street region240. This is unlike existing processes which generally form edge structures232(shown in dotted lines) projecting away from the growth substrate220at the edge regions231. These conventional processes include depositing a dielectric material at the street region240to prevent the first semiconductor material224and/or the second semiconductor material225from growing or otherwise forming at the street regions240. This conventional step is taken to prevent the first and/or second semiconductor materials224,225from forming layers that extend laterally (left/right and into/out of the plane ofFIG. 2E) over long uninterrupted distances. Formation of the first or second semiconductor materials over an uninterrupted distance can increase stress on the growth substrate and may result in wafer bowing or other types of deformation than are layers having smaller lateral extents. In a conventional arrangement, the dielectric material at the street regions240inhibits the semiconductor materials from nucleating there and accordingly interrupts the lateral extension of these materials. However, as a result of preventing the first and/or semiconductor materials224,225from forming at the street regions240, conventional techniques can force the material that would otherwise nucleate in the street regions240to form the edge structures232at the edge regions231of the device growth regions230. Instead of forming such edge structures232, embodiments of the present technology include the dummy structures241positioned at the street region240to attract at least some of the second semiconductor material225(e.g., atoms or molecules) that would otherwise be disposed at the edge region231. Accordingly, the exposed surfaces of the dummy structures241can have the same composition as the exposed surfaces at the device growth regions230. The dummy structures241can accordingly prevent the edge structures232from forming and can therefore improve the uniformity with which the second semiconductor material225and materials supported and/or carried by the second semiconductor material225are formed.

The dummy structures241can be sized, shaped and spaced to attract growth materials in the manner described above. For example, the dummy structures241closest to the device growth region230can be spaced apart from the device growth regions230by an offset distance D having a value of from about 5 microns to about 15 microns. In other embodiments, the offset distance D can have other values that produce dummy structures that are also (a) close enough to the device growth regions230to attract material that might otherwise form the edge structures232, yet (b) far enough from the device growth regions230to avoid coalescing with these regions. Individual dummy structures241can be separated from each other by a separation distance S having a similar value to avoid coalescing. The selected values for the offset distance D and/or the separation distance S can depend upon the type of device being formed. For example, devices with a vertical configuration (generally shown inFIG. 1B) may not require values as large as those for devices with a lateral configuration (generally shown inFIG. 1A).

InFIG. 2F, additional materials have been disposed at the growth regions230to form corresponding dies251. In particular embodiments, the additional materials can include an active region material226(e.g., a gallium nitride and a gallium nitride compound for example, indium gallium nitride) that form multiple quantum wells suitable for generating light. A third semiconductor material227(e.g., a P-type GaN material) is positioned adjacent the active region material226to form an electrical path through the active region material226. Accordingly, the resulting dies251can be used to form LEDs or other SST devices. The additional materials226,227are also disposed at the street region240.

In particular embodiments, other processes may be performed on the dies251before they are singulated. Such processes can include forming interconnect structures, lenses, coatings, and/or other elements. In any of these embodiments, the dies251can then be separated using a singulation device250, shown inFIG. 2G. The singulation device250can include a saw blade252that separates the dies251at the street regions240, thus damaging, destroying, and/or otherwise modifying (e.g., in an irreversible manner) the dummy structures241(FIG. 2F) and other features formed at the street regions240. Accordingly, the dummy structures can be sacrificial elements with no further purpose once the dies251have been singulated. In other embodiments, other techniques can be used to singulate the dies251. Suitable techniques include laser dicing, cleave-and-break separation techniques, and/or others, which also typically damage or destroy the dummy structures. In any of these embodiments, the singulated dies can be further processed to form packages and/or other structures suitable for end users after the singulation operation has been performed.

FIG. 3is a partially schematic, cross-sectional view of a growth substrate220supporting dummy structures341formed at a street region240in accordance with another embodiment of the present technology. In one aspect of this embodiment, the mask221includes a single aperture222in which the second portion223bof the seed material223is disposed. The second material224can be disposed in a generally similar manner, forming a second portion224bat the street region240. The second portion224bcan be further processed (e.g., using a separate mask and etch process) to form recesses in the second portion224bwhich then support multiple second portions225bof the second material225. The second portions225bof the second material225form the corresponding dummy structures341. Accordingly, a combination of additive and subtractive processes can be used to form the dummy structures341. Once the dummy structures341are formed, the growth substrate220can be further processed, e.g., using the techniques described above with reference toFIG. 2F.

FIGS. 4A and 4Billustrate an arrangement in accordance with still another embodiment in which a subtractive process is used to form corresponding dummy structures441. Beginning withFIG. 4A, the seed material223can be disposed in a generally continuous manner over both the device growth regions230and the street region240, so that the first and second portions223a,223bare generally continuous. A mask321has been applied to the seed material223and includes apertures322in between dummy structure sites. A subtractive process (e.g., an etch process) is used to remove sections of the second portion223bof the seed material223, as shown inFIG. 4B. The remaining second portions223bform the dummy structures441. The remaining sections of the mask321(FIG. 4A) are removed to facilitate adding to the growth substrate220the additional materials described above with reference toFIGS. 2D-2F. In another embodiment, the masking process described above can operate in reverse. For example, the initially continuous mask321can be processed to have openings where mask material is shown inFIG. 4A, and mask material where openings are shown inFIG. 4A. Subsequently disposed materials will then form at the unmasked regions, producing growth at the growth regions230and producing spaced-apart dummy structures in the street region240. In this embodiment, the seed material can include AlN, AlGaN, GaN and/or another suitable material, and the mask221can include SiNx, SiO2or another suitable dielectric.

One feature of the foregoing embodiments is that the sacrificial, dummy structures can reduce or prevent epitaxially grown materials from over-accumulating at the edges of targeted growth regions. An advantage of this arrangement is that it can reduce or eliminate the extent to which such over-accumulations interfere with subsequent processes. Such processes can include photolithographic processes and subsequent growth processes, both of which benefit from and in many cases require very flat, uniform underlying layers. At the same time, the foregoing techniques do not require additional semiconductor “real estate” because the dummy structures can be formed within the confines of existing street widths.

FIG. 5is a partially schematic plan view of a portion of a wafer500having representative dies551separated by dummy structures that, in addition to attracting material that would otherwise accumulate at the corresponding growth regions, form test structures542. For purposes of illustration, multiple test structures542having different arrangements (e.g., first test structures542a, second test structures542b, and third test structures542c) are illustrated as being carried by the same wafer500. During typical processing steps, not all such test structures need be included in a single wafer or other growth substrate.

The test structures542can be used to conduct any of a number of pre-dicing diagnostic tasks, including, without limitation, testing electrical characteristics (e.g., impedance) and/or material doping levels. The first test structure542acan include first dummy structures541athat form spaced-apart transmission line elements suitable for transmission line measurement (TLM) techniques used to identify the electrical characteristics of the materials forming both the first dummy structures541aand the corresponding structures at the dies551. The first test structure542acan include evenly spaced dummy structures541a.The second test structure542bcan include corresponding dummy structures541bthat are spaced apart by different amounts. In still a further embodiment, a third test structure542ccan include dummy structures541cthat are arranged in concentric rings, e.g., to determine contact or sheet resistance.

In any of the foregoing embodiments, the results obtained from the test structures542can be used to influence downstream processes (prior to dicing). Accordingly, the dummy structures541can improve yield by improving the uniformity with which materials are grown on the growth substrate, and facilitating processes for correcting non-uniformities or other defects or anomalies.

From the foregoing, it will be appreciated that specific embodiments of the disclosed technology have been described herein for purposes of illustration, but that various modifications may be made without deviating from the technology. For example, the foregoing techniques can be used to form SST devices (e.g., LEDs) or other devices that make use of crystalline materials grown on substrates having different lattice and/or CTE characteristics. Such devices can include power devices. Depending upon the embodiment, the dummy structures can have forms and shapes other than those described above. For example, the dummy structures can have the form of intermittent, spaced-apart line segments, or spaced-apart pillars. In other embodiments, the foregoing techniques can be applied to devices with Group II-IV or VI layers, or layers formed from other elements or compounds. The overall epitaxial growth techniques, e.g., SAG techniques, can be applied at the die level as discussed above and/or at scales larger or smaller than die scale.

Certain aspects of the technology described in the context of particular embodiments may be combined or eliminated in other embodiments. For example, the test structures shown inFIG. 5can be formed using any of the techniques described above with reference toFIGS. 2A-4B. Further, while advantages associated with certain embodiments have been described in the context of those embodiments, other embodiments may also exhibit such advantages, and not all embodiments need necessarily exhibit such advantages to fall within the scope of the present technology. Accordingly, the present disclosure and associated technology can encompass other embodiments not expressly described or shown herein.