Synchronous bus type semiconductor circuit wherein two control signals share common terminal

A semiconductor IC device of an asynchronous bus type which is in a selected state when a chip select signal applied to it is at a "H" level, comprises an external control signal line through which an external control signal is input, and a first and a second internal control signal lines for transfer of a first and a second control signals each of which is not activated when the other is activated. The first control signal is allocated to either the "H" level or the "L" level of the external control signal, and the second control signal is activated when the external control line is at the second level which is the inverse of the first level for the first control signal. An inhibit circuit is provided to prevent the second control signal from being erroneously activated while the first control signal is to be activated and when the first level of the external control signal begins after or terminates before the chip select signal.

BACKGROUND OF THE INVENTION 
The present invention relates to a semiconductor IC (integrated circuit) 
device of an asynchronous bus type and particularly to an improvement for 
reducing the number of terminals by use of an arrangement in which a 
terminal is shared by two types of control signals. 
When it is desired that two types of control signals are allotted to or 
transmitted by a common terminal or pin, a circuit as shown in FIG. 1 may 
be contemplated. As illustrated, the contemplated circuit comprises AND 
gates 7 and 8 and an inverter 10, to which a chip select signal CS and a 
control signal A/B which represents a combination of control signals A and 
B, are supplied. 
FIG. 2 shows operation of the circuit of FIG. 1. An internal control signal 
A' on an internal control signal line 4 can be activated if a chip select 
terminal 1 and a control terminal 2 are both at "H". But if the chip 
select signal CS on the chip select terminal 1 is longer that the period 
t1 of the combined control signal A/B on the control terminal 2, there 
occurs an error (undesirable "H" level) in an internal control signal B' 
on an internal control signal line 3, for the periods t2 and t3. This 
error is fatal in that the internal control signal B' is made at "H" when 
it is attempted that only the internal control signal A' be made at "H". 
Because of such a problem, it has been impossible to allocate two control 
signals to a common terminal in a semiconductor IC device of the 
asynchronous bus type. 
SUMMARY OF THE INVENTION 
An object of the invention is to enable reduction of the number of 
terminals of a semiconductor IC device of the asynchronous bus type. 
According to the invention, there is provided a semiconductor IC device of 
an asynchronous bus type which is in a selected state when a chip select 
signal applied to it is at "H" level, and which comprises 
an external control signal line through which an external control signal is 
input, and 
a first and a second internal control signal lines for transfer of a first 
and a second control signals each of which is not activated when the other 
is activated, 
wherein said first control signal is allocated to a first one of the "H" 
level and the "L" level of the external control signal, and said second 
control signal is activated when the external control line is at the 
second level which is the inverse of the first level for said first 
control signal, 
said semiconductor IC device further comprising an inhibit circuit for 
preventing said second control signal from being erroneously activated 
while said first control signal is to be activated, and when the first 
level of said external control signal begins after or terminates before 
said chip select signal.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
An embodiment shown in FIG. 3 includes an arrangement for preventing an 
erroneous operation at the period t3 in FIG. 2, that is at the termination 
of the chip select signal CS. 
The semiconductor IC device comprises a control terminal 2 through which a 
control signal A/B is input. The control signal A/B represents a 
combination of a control signal A and an inversion of a control signal B. 
Application of "H" at the terminal 2 means input of the control signal A, 
while application of "L" at the terminal 2 means input of the control 
signal B. 
The semiconductor IC device further comprises AND gates 7 and 8 whose 
output lines constitute control signal lines 4 and 3 on which internal 
control signals A' and B' are produced. The AND gate 8 receives the chip 
select signal CS and the control signal A/B, so the signal A' is a logical 
product of the signal A/B and the chip select signal CS. 
The semiconductor IC device further comprises an inhibit circuit 20 which 
comprises a delay circuit 5 receiving the control signal A/B and a NOR 
gate 6 receiving the output a of the delay circuit 5 and the control 
signal A/B. 
The AND gate 7 receives the chip select signal CS and the output of the NOR 
gate 6. 
The operation of the device will be described with reference to FIG. 4. 
When there is a difference in the timing between the chip select signal CS 
and the control signal A/B, an error may occur. But according to the 
illustrated embodiment, the signal A/B is passed through the delay circuit 
5, and the output a of the delay circuit 5 and the signal A/B (without the 
delay) are input to the NOR gate 6, whose output b is then input to the 
AND gate 7 together with the chip select signal CS. The erroneous pulse at 
t3 in FIG. 2 is thereby rejected or eliminated. The delay time of the 
delay circuit can be determined on consideration of the maximum difference 
which can occur in the chip select signal CS of the system and the pulse 
width of the control signal A/B. 
FIG. 5 shows another embodiment of the invention. This embodiment includes 
an arrangement for preventing an erroneous operation at the periods t2 and 
t3, that is at the beginning and the termination of the chip select signal 
CS. 
The circuitry includes a portion identical to that of FIG. 1. But the 
output of the AND gate 7 is denoted by Ba, rather than B'. In addition, 
there are provided a delay circuit 11 receiving the signal Ba and an AND 
gate 12 receiving an output Bb of the delay circuit 11 and the output Ba 
of the AND gate 7. The output of the AND gate 7 constitutes the second 
control signal B'. In this embodiment, the delay circuit 11 and the AND 
gate 12 forms an inhibit circuit 21 which rejects a control signal of a 
pulsewidth smaller than a predetermined time length. 
FIG. 6 shows operation of the circuit of FIG. 5. The signals A/B, CS and A' 
are identical to those of the same notations in FIG. 2. The signal Ba is 
identical to the signal B' in FIG. 2. The signal Bb is delayed by the 
delay time Td of the delay circuit 11 with respect to the signal Ba. The 
signal B' is the logical product of Ba and Bb. It is seen that pulses P1 
and P2 at the output of the AND gate 7, having a pulsewidth smaller than 
Td are removed or rejected, and do not appear at the output of the AND 
gate 12. 
The delay time Td of the delay circuit 11 is so determined as to be larger 
than the deviation in the timing of the leading and trailing edges of the 
chip select signal CS which must be allowed. 
As has been described, according to the present invention, the number of 
pins of a semiconductor IC device of the asynchronous bus type can be 
reduced and the production cost can therefore be reduced. Alternatively, 
the pin that has been saved can be used for other purposes. This will 
increase the performance of the semiconductor IC device.