Apparatus with multi-wafer based device comprising embedded active and/or passive devices and method for forming such

An apparatus is provided which comprises: a substrate; a first active device adjacent to the substrate; a first set of one or more layers to interconnect with the first active device; a second set of one or more layers; a second active and/or passive device coupled to the second set of one or more layers; and a layer adjacent to one of the layers of the first and second sets, wherein the layer is to bond the one of the layers of the first and second sets.

CLAIM OF PRIORITY

This Application is a National Stage Entry of, and claims priority to, PCT Application No. PCT/US2017/025177, filed on Mar. 30, 2017 and titled “APPARATUS WITH MULTI-WAFER BASED DEVICE COMPRISING EMBEDDED ACTIVE AND/OR PASSIVE DEVICES AND METHOD FOR FORMING SUCH,” which is incorporated by reference in its entirety for all purposes.

BACKGROUND

Today, manufacturing of semiconductor device starts with a silicon (Si) substrate and progresses with front-end (FE) processes followed by back-end (BE) processes, and finally end-of-life or end-of-line (EOL) processes. Current BE processes are developed such that there is no negative impact on the FE structures (e.g., transistors formed on a substrate). Recent semiconductor device manufacturing processes may also not allow embedding other active devices near the FE structures. For example, high temperature processing of forming active devices near the FE structures may adversely impact the integrity of the FE structures. Further, as the complexity in device manufacturing is increasing, higher throughput/cycle time in manufacturing has become a challenge.

DETAILED DESCRIPTION

Competitiveness in throughput and cycle time is a concern as it takes a long time from start to end in device manufacturing and hence impacts product to market times in addition to having high development cost. Another constraint with current manufacturing processes is the limitation in BE processes. Current BE processes are developed such that there is no negative impact on the integrity FE structures underneath.

Here, the terms “FE” or “front-end process” refer to a manufacturing process that is used for forming one or more active devices over a substrate. Here, the terms “BE” or “back-end process” refer to a manufacturing process that is used for forming one or more interconnects (e.g., metal layers) to couple the active devices.

Various embodiments describe a chip which is formed by splitting device processing on two substrates (e.g., on two separate wafers). In some embodiments, one substrate of a first wafer can be used for fabricating one or more active devices (e.g., FE process+Mx, where ‘M’ is a metal layer, and ‘x’ is a number) and the other substrate of a second wafer can be used for the remaining part of the process (EOL+Mx+1) and other one or more active and/or passive devices. Here, the terms “EOL” or “end-of-life” or “end-of-line” process refer to a manufacturing process that is used for coupling one or more interconnects to pads that then are coupled to package interconnects (e.g., solder bumps).

In some embodiments, the active and/or passive devices are formed on a substrate before the EOL processing. These active and/or passive devices include one of: high power transistor, photonic laser, sensor (e.g., a bio sensor, temperature sensor, etc.) inductor, or capacitor. In some embodiments, the two substrates are bonded together and a post bond process is performed to expose the EOL metal interconnect layer/pads and the active and/or passive devices to produce the full device for packaging, in according to some embodiments. In some embodiments, as part of the BE process, active devices are also formed. These active devices are also referred to as embedded active devices because when the two processed wafers are bonded, these active devices are in a region between opposite sides of the bonded wafers. These embedded active devices may include non-volatile memory, volatile memory, voltage regulators, DC-DC converters, clock buffers, signal buffers, etc. In some embodiments, the embedded active devices are adjacent to the layer used for bonding the two wafers.

In some embodiments, an apparatus is provided which comprises: a substrate (e.g., Si); a first active device (e.g., a transistor) adjacent to the substrate; a first set of one or more layers (e.g., metal0(M0), metal1(M1), metal2(M2), etc.) to interconnect with the first active device; a second set of one or more layers (e.g., metal3(M3), metal4(M4), metal5(M5), etc.); a second active and or passive device (e.g., high power transistor, photonic laser, sensor (e.g., a bio sensor, temperature sensor, etc.) inductor, or capacitor etc.) coupled to the second set of one or more layers; and a layer adjacent to one of the layers of the first and second sets, wherein the layer is to bond the one of the layers of the first and second sets. In some embodiments, another set of active devices (e.g., embedded devices) is formed on a substrate which is coupled to one of the layers of the second set of one or more layers such that these active devices are separated from the second active and/or passive devices by BE and EOL processing features. These embedded devices include a transistor for a memory, voltage regulator, DC-DC converter, signal buffer, clock buffer, power gate, etc.

Here, the substrate, the first active device, and the first set of one of more layers are formed on a first wafer, and the second set of one or more layers and the second active and/or passive device are formed on a second wafer. In some embodiments, the layer to bond includes at least one of a dielectric or a metal. In some embodiments, the dielectric includes one of: oxygen, carbon-doped oxide, polymer, or glue. In some embodiments, the metal includes one of: Cu, Ni, Co, Al, or W.

Current known solutions have several disadvantages such as high throughput time, high development time and cost, and BE process constraints to minimize impacts to underneath FE processes. Current known solutions also uses gas anneal that may destroy active devices such as memory transistors.

The method of forming the device (or apparatus) of various embodiments can use high temperature materials for BE process because the BE process is applied on a different wafer. For example, wafer2processing may not impact processing of wafer1. The manufacturing process of various embodiments have manufacturability advantage and significant throughput advantage. For example, wafer1and wafer2can be processed in parallel resulting in yield benefits and shorter development time. In some examples, wafer2may not need to be high quality silicon because it is used for providing the structure formed during the BE process. Separating the manufacturing processes on to two different wafers, and then joining or bonding those wafers in a specific manner is referred to here as the split and join process. The split and join process to manufacture a first device on a first wafer and a second device on a second wafer provides integrated cost of ownership benefit by having a segmented process (e.g., separate process for wafer1and wafer2).

After the two wafers are joined, the second device (active and/or passive) allows the joined wafers to become a more complete system on chip (SOC). For example, active devices on wafer1may include digital signal processing logic while the devices formed near the top of the joined stack are optical transceivers to send and receive optical signals. As such, the joined wafers can provide a fully integrated solution. In some embodiments, active devices are also embedded between the two wafers. For example, during processing of wafer2, active devices are fabricated in wafer2, and these devices become embedded devices that reside between the first device and the EOL pad connections. Other technical effects will be evident from the various embodiments and figures.

For the purposes of the present disclosure, phrases “A and/or B” and “A or B” mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C). The terms “left,” “right,” “front,” “back,” “top,” “bottom,” “over,” “under,” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions.

FIG. 1illustrates a cross-section of apparatus100formed by joining or bonding of two wafers comprising active and/or passive devices formed after EOL process, according to some embodiments of the disclosure.

In some embodiments, two processed wafers101and121are joined and then packaged. In some embodiments, wafer101comprises substrate102, active devices103(e.g., transistors), oxide region104, vias105, metal layers106(e.g., metal0(M0)),107(e.g., metal1(M1)),108(e.g., metal2(M2)), and wafer connection vias (or regular vias)110. In some embodiments, substrate102includes bulk silicon or silicon-on-insulator (SOI). In some embodiments, the bulk silicon includes device quality Epi.

In some embodiments, wafer121comprises wafer connection vias (or regular vias)120, oxide region124, vias125, metal layers126(e.g., metal3(M3)),127(e.g., metal4(M4)),128(e.g., metal5(M5)), and129(e.g., metal6(M6)) which include EOL pads130, and one or more active and/or passive devices140. In some embodiments, active and/or passive devices140include one of: high power transistor, photonic laser, sensors (e.g., bio sensors), inductor, capacitor, MEMs (micro-electro-mechanical-system), or any other device which is expected to be close to a package assembly. While layer140is shown to cover the entire length of wafer2, some EOL pads130can be exposed and directly connected to a package assembly (e.g., solder bumps), in accordance with some embodiments.

The various number of metal layers, active devices, and vias in each wafer are shown as an example. Any number of metal layers, active devices, and vias can be used in accordance with some embodiments. In this cross-section, the substrate of wafer121is not shown because it is grinded out as discussed with reference toFIGS. 3A-D.

Referring back toFIG. 1, in some embodiments, processing of wafer101is performed separate and independent of processing of wafer121. In some embodiments, the processing or fabricating technology used to process wafer101and wafer121is the same. For example, both wafers101and121are processed using10nanometer (nm) CMOS process technology. In some embodiments, the processing or fabricating technology used to process wafer101and wafer121is different. For example, a newer and more advanced process node technology may be used for processing wafer101to produce state of the art transistors and other active devices, while a less expensive process node technology (e.g., a previous generation process technology node technology) may be used for producing wafer121which may not have active devices. In some embodiments, depending on the kind of active and/or passive devices140, a process technology suited for those devices may be used for wafer121.

For example, wafer121may be fabricated using a process technology node suited for RF (radio frequency) circuits while wafer101may be fabricated using a process technology node suited for regular digital circuits. In another example, wafer121may be fabricated using a MEMs process technology while wafer101may be fabricated using a process technology node suited for regular digital circuits. Various embodiments allow mixing of circuits from different process technologies without having to develop one process technology that offers benefits of those different process technologies.

In some embodiments, wafer101and wafer121are bonded or fused together by applying a bonding material111such that wafer connection vias110and120electrical connect with one another. Any suitable apparatus can be used for bonding wafer101and wafer121. In some embodiments, bonding material111or layer111includes at least one of a dielectric or a metal. In some embodiments, the dielectric includes one of: oxygen, carbon-doped oxide, polymer, or glue. In some embodiments, the metal includes one of: Cu, Ni, Co, Al, or W.

In various embodiments, the processing operation to wafer1are FE processing which includes forming active devices on substrate102and metal layers closer to active devices (e.g., M0-M2). In some embodiments, the processing operation to wafer2are BE and EOL processing which include forming metal layers (e.g., M3-M6) and their associated vias that continue above the metal layers processed or fabricated on wafer1and all the way to layers used to connect to package bumps.

While the various embodiments show the bonding of two wafers, a number of wafers can be bonded on top of one another such that each wafer (or at least one of them) is fabricated or formed in parallel or independent from the other wafer. As such, as stack of processed wafers can be bonded forming an apparatus or integrated chip in much shorter time resulting in high fabrication throughput.

FIG. 2illustrates a cross-section of apparatus200formed by joining or bonding of two wafers comprising embedded active and/or passive devices along with active and/or passive devices formed after EOL process, according to some embodiments of the disclosure. It is pointed out that those elements ofFIG. 2having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. Apparatus200is similar to apparatus100except that active devices230are also formed on the other side of wafer221(same as wafer121but for additional active devices). For example, active device230are formed on a side opposite to the side of active/passive devices140. The active device230are also referred to as embedded devices because they are positioned between one end of wafer221and another end of wafer101. These embedded active devices230may include non-volatile memory, volatile memory, voltage regulators, DC-DC converters, clock buffers, signal buffers, power gates, etc.

FIGS. 3A-Fillustrate cross-sections300,320,330,340, and350, respectively, of various phases of manufacturing the apparatus ofFIGS. 1-2, according to some embodiments of the disclosure. It is pointed out that those elements ofFIGS. 3A-Fhaving the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

In some embodiments, cross-section300illustrates a portion of wafer101after active devices103are formed on substrate102, and including layers that are part of FE processing (e.g., initial metal layers that are closer in proximity to the active device103than to the package bumps).

In some embodiments, cross-section320illustrates a portion of wafer121after layers that are part of BE processing and EOL processing are added on substrate122(e.g., Si, bulk silicon with device quality Epi, or SOI). In some embodiments, after substrate122is prepared for further processing, active and/or passive devices140are fabricated over substrate122. In some embodiments, active and/or passive devices140include one or more of: high power transistor, photonic laser, sensors (e.g., bio sensors), inductor, capacitor, MEMs (micro-electro-mechanical-system), or any other device which is expected to be close to a package assembly. In some embodiments, after active and/or passive devices140are fabricated on substrate122, metal layer that is used in the EOL processing is first deposited and then patterned according to pitch requirements of package bumps. This patterned metal layer (e.g.,129) which is directly adjacent to substrate122is used for connecting the bonded apparatus100to a package assembly, in accordance with some embodiments.

In some embodiments, cross-section330illustrates a portion of wafer221after active device(s)230are formed. In some embodiments, after the metal layer is patterned to form connecting vias120, active devices230(also referred to as embedded devices) are formed. For example, a layer of silicon to behave as a substrate (not shown) is deposited and then transistors are fabricated over that substrate. These transistors or active devices can be for any kind of circuit. For example, the active devices may be part of a memory array (volatile or non-volatile), power gates, clock buffers, voltage regulators, low dropout (LDO) circuits, DC-DC converters, etc.

In some embodiments, the deposition and processing of layers is reversed compared to traditional wafer processing. For example, EOL processing steps are performed first after a substrate is made ready and then BE processing is performed such that the top layer (here, the layer forming connecting vias120) is fabricated. In some embodiments, the layer forming the top layer120may be part of a FE processing operation.

In some embodiments, cross-section340illustrates a portion of wafer101after bonding layer111is applied. However, the application of bonding layer is not limited to wafer101. In some embodiments, bonding layer111may be applied to wafer101and/or wafer121/221. In some embodiments, before bonding layer111is applied, the surface of the wafers121/221and101are prepared for receiving bonding material forming bonding layer111. For example, the surfaces of wafers121/221and101are grinded, etched, and/or polished before bonding material forming bonding layer111is deposited.

In some embodiments, cross-section350illustrates a portion of a process after wafer101and wafer121are fused or bonded together such that substrates102and122are along opposite ends or sides of the stack of layers. In some embodiments, after wafer101and wafer121are bonded, substrate122of wafer121is removed to expose the EOL pad structures and the active/passive devices140. For example, substrate122is grinded, chemical mechanical planarization (CMP) is applied, and/or dry etching process is applied to expose the EOL patterned metal and active/passive devices140that were deposited on substrate122. Cross-section100describes the apparatus or portion of the process after substrate122is removed, in accordance with some embodiments.

In some embodiments, cross-section360illustrates a portion of a process after wafer101and wafer221are fused or bonded together such that substrates102and122are along opposite ends or sides of the stack of layers. In some embodiments, after wafer101and wafer221are bonded, substrate122of wafer221is removed to expose the EOL pad structures and the active/passive devices140. For example, substrate122is grinded, CMP is applied, and/or dry etching process is applied to expose the EOL patterned metal and active/passive devices140that were deposited on substrate122. Cross-section200describes the apparatus or portion of the process after substrate122is removed, in accordance with some embodiments.

FIG. 4illustrates flowchart400of a method to form the apparatus ofFIGS. 1-2, according to some embodiments of the disclosure. It is pointed out that those elements ofFIG. 3having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

Although the blocks in the flowchart with reference toFIG. 4are shown in a particular order, the order of the actions can be modified. Thus, the illustrated embodiments can be performed in a different order, and some actions/blocks may be performed in parallel. Some of the blocks and/or operations listed inFIG. 4are optional in accordance with certain embodiments. The numbering of the blocks presented is for the sake of clarity and is not intended to prescribe an order of operations in which the various blocks must occur. Additionally, operations from the various flows may be utilized in a variety of combinations.

At block401, FE process operation is applied to wafer1(e.g., wafer101) to from active device(s)103on substrate102. The FE process also forms metal layers and vias to interconnect the active devices103and other nodes. For example, FE process forms a stack of layers up to Mx, where ‘M’ stands for metal and ‘x’ stands for the associated layer number.

At block402a, active and/or passive devices140are also formed on a substrate region122of wafer2(e.g., wafer121/221). In some embodiments, active and/or passive devices140include one of: high power transistor, photonic laser, sensors (e.g., bio sensors), inductor, capacitor, MEMs (micro-electro-mechanical-system), or any other device which is expected to be close to a package assembly.

In some embodiments, at block402b, EOL process operations are applied to wafer2to form EOL pads over active and/or passive devices140such that active and/or passive devices140and/or metal layers126-129are electrically coupled. At block402c, BE process operation are applied to wafer2from EOL processing end to metal layers My, where ‘y’ is an integer. The BE process forms metal layers and vias to interconnect various nodes and to the active devices140. For example, BE process forms a stack of layers starting from Mx and up to My=Mx+n, where ‘M’ stands for metal and ‘x’ stands for the associated layer number, and ‘n’ is a number. As such, wafer2includes layers which are EOL layers minus Mx+1, where “Mx” is the last layer formed on wafer1.

In some embodiments, at block402d, another set of active devices230may be formed over a substrate region, where these set of active devices (also referred to as embedded devices) are coupled to one of the Mx layers (e.g., layer128). These active devices230may be part of a memory array (volatile or non-volatile), power gates, clock buffers, voltage regulators, low dropout (LDO) circuits, DC-DC converters, etc.

In some embodiments, blocks402a/b/c/dare performed separate from block401. For example, blocks401band402cmay be performed simultaneously and independently of block401.

At block403, bonding material is deposited on either or both of polished/cleaned surfaces of wafer1and wafer2. The wafers101and121/221are then bonded such that their vias110and120electrically connect with one another. As such, vias110and120connect without causing unintended shorts with other contacts.

At block404, substrate122is removed (e.g., by dry etch or CMP process) to expose the EOL pads of wafer2121/221and active/passive devices140. At block405, a package is assembled around apparatus100/200and package bumps are electrically coupled to the EOL pads of wafer2.

FIG. 5illustrates cross-section500of a package assembly having a processor formed by joining or bonding of two wafers comprising embedded active and/or passive devices along with active and/or passive devices formed after EOL process, according to some embodiments of the disclosure. It is pointed out that those elements ofFIG. 5having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

In some embodiments, IC package assembly may include First die501, package substrate504(or interposer), and circuit board522(which may be a substrate). IC package assembly of cross-sectional view500is one example of a stacked die configuration in which First die501is coupled to package substrate504, and Second die502is coupled with First die501, in accordance with some embodiments. In some embodiments, both or at least one of First die501or Second die502is formed by the split and join process of FIGS.3A-F where at least two wafers are separately processed and then joined together to form a single IC structure having embedded active devices.

In some embodiments, First die501may have a first side S1and a second side S2opposite to the first side S1. TSVs may also exist in First and Second dies (501and502, respectively) as illustrated by vias525, in accordance with some embodiments. In some embodiments, first side S1may be the side of the die commonly referred to as the “inactive” or “back” side of the die. For example, first side S1may refer to the side that exposes the EOL pads and active/passive devices140after substrate122is removed.

In some embodiments, second side S2may include one or more transistors, and may be the side of the die commonly referred to as the “active” or “front” side of the die. For example, second side S2is the side of substrate102which is opposite to the side having active devices103. In some embodiments, second side S2of First die501may include one or more electrical routing features506. In some embodiments, Second die502may include an “active” or “front” side with one or more electrical routing features506. In some embodiments, electrical routing features506may be bond pads (e.g., formed from a combination of metal bumps and solder balls).

In some embodiments, Second die502may be coupled to First die501in a front-to-back configuration (e.g., the “front” or “active” side of Second die502is coupled to the “back” or “inactive” side S1of First die501) via interconnect507(e.g., vias, bumps, solder balls, etc.). In some embodiments, dies may be coupled with one another in a front-to-front, back-to-back, or side-to-side arrangement. In some embodiments, one or more additional dies may be coupled with First die501, Second die502, and/or with package substrate interposer504. Other embodiments may lack Second die502. In some embodiments, First die501may include one or more TSVs.

In some embodiments, Second die502is coupled to First die501by die interconnects formed from a combination of bumps and solder balls. In some embodiments, inter-die interconnects may be solder bumps, copper pillars, or other electrically conductive features. In some embodiments, copper pillars507are formed to attach to the solder balls and thus couple First die501with Second die502. In some embodiments, an interface layer524may be provided between First die501and Second die502. In some embodiments, interface layer524is a solder based interconnect layer. For example, bumps coupled to First die501couple to solder balls which couple to bumps coupled to Second die502. In some embodiments, interface layer524may be, or may include, a layer of under-fill, adhesive, dielectric, or other material. In some embodiments, interface layer524may serve various functions, such as providing mechanical strength, conductivity, heat dissipation, or adhesion.

In some embodiments, First die501and Second die502may be single dies formed by the split and join process ofFIGS. 3A-E. In other embodiments, First die501and/or Second die502may each include two or more dies where at least one die is formed by the split and join process ofFIGS. 3A-E. In some embodiments, First die501and/or Second die502includes two or more dies embedded in an encapsulant. In some embodiments, the two or more dies are arranged side-by-side, vertically stacked, or positioned in any other suitable arrangement. In some embodiments, the IC package assembly may include, for example, combinations of flip-chip and wire-bonding techniques, interposers, multi-chip package configurations including system-on-chip (SoC) and/or package-on-package (PoP) configurations to route electrical signals.

In some embodiments, First die501and/or Second die502may be a primary logic die. In some embodiments, First die501and/or Second die502may be configured to function as memory, an application specific circuit (ASIC), a processor, an RF IC, a baseband processor, or some combination of such functions. For example, First die501may include a processor and active/passive devices140and Second die502may include memory and active/passive devices140. In some embodiments, one or both of First die501and Second die502may be embedded in encapsulant508. In some embodiments, encapsulant508can be any suitable material, such as epoxy-based build-up substrate, other dielectric/organic materials, resins, epoxies, polymer adhesives, silicones, acrylics, polyimides, cyanate esters, thermoplastics, and/or thermosets.

In some embodiments, First die501may be coupled to package substrate interposer504. In some embodiments, package substrate interposer504may be a cureless substrate interposer. For example, package substrate interposer504may be a bumpless build-up layer (BBUL) assembly that includes a plurality of “bumpless” build-up layers. Here, the term “bumpless build-up layers” generally refers to layers of substrate and components embedded therein without the use of solder or other attaching means that may be considered “bumps.” However, the various embodiments are not limited to BBUL type connections between die and substrate interposer, but can be used for any suitable flip chip substrates.

In some embodiments, the one or more build-up layers may have material properties that may be altered and/or optimized for reliability, warpage reduction, etc. In some embodiments, package substrate interposer504may be composed of a polymer, ceramic, glass, or semiconductor material.

In some embodiments, layer522may be a Printed Circuit Board (PCB) composed of an electrically insulative material such as an epoxy laminate. For example, layer522may include electrically insulating layers composed of materials such as, phenolic cotton paper materials (e.g., FR-1), cotton paper and epoxy materials (e.g., FR-3), woven glass materials that are laminated together using an epoxy resin (FR-4), glass/paper with epoxy resin (e.g., CEM-1), glass composite with epoxy resin, woven glass cloth with polytetrafluoroethylene (e.g., PTFE CCL), or other polytetratluoroethylene-based prepreg material.

Structures such as traces, trenches, and vias (which are not shown here) may be formed through the electrically insulating layers to route the electrical signals of First die501through the layer522. Layer522may be composed of other suitable materials in other embodiments. In some embodiments, layer522may include other electrical devices coupled to the circuit board that are configured to route electrical signals to or from First die501through layer522. In some embodiments, layer522may be a motherboard.

In some embodiments, a first side of package substrate interposer504is coupled to second surface S2and/or electrical routing features506of First die501. In some embodiments, a second opposite side of package substrate interposer504is coupled to layer522by package interconnects512. In some embodiments, package interconnects512may couple electrical routing features510disposed on the second side of package substrate interposer504to corresponding electrical routing features516on layer522. In some embodiments, non-circle TSV landing pads510are for landing one or more TSVs511and coupling them to solder bumps512.

In some embodiments, package substrate interposer504may have electrical routing features formed therein to route electrical signals between First die501(and/or the Second die502) and layer522and/or other electrical components external to the IC package assembly. In some embodiments, package interconnects512and die interconnects406include any of a wide variety of suitable structures and/or materials including, for example, bumps, pillars or balls formed using metals, alloys, solderable material, or their combinations. In some embodiments, electrical routing features510may be arranged in a ball grid array (“BGA”) or other configuration.

FIG. 6illustrates a smart device or a computer system or a SoC (System-on-Chip) formed by joining of at least two wafers, according to some embodiments. It is pointed out that those elements ofFIG. 6having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

FIG. 6illustrates a block diagram of an embodiment of a mobile device in which flat surface interface connectors could be used. In some embodiments, computing device1600represents a mobile computing device, such as a computing tablet, a mobile phone or smart-phone, a wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device1600.

In some embodiments, computing device1600includes first processor1610and network interface within1670such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant. In some embodiments, at least one or all blocks of device1600are formed by the split or join process.

In some embodiments, computing device1600includes audio subsystem1620, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device1600, or connected to the computing device1600. In one embodiment, a user interacts with the computing device1600by providing audio commands that are received and processed by processor1610.

In some embodiments, computing device1600comprises display subsystem1630. Display subsystem1630represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device1600. Display subsystem1630includes display interface1632, which includes the particular screen or hardware device used to provide a display to a user. In one embodiment, display interface1632includes logic separate from processor1610to perform at least some processing related to the display. In one embodiment, display subsystem1630includes a touch screen (or touch pad) device that provides both output and input to a user.

In some embodiments, computing device1600comprises I/O controller1640. I/O controller1640represents hardware devices and software components related to interaction with a user. I/O controller1640is operable to manage hardware that is part of audio subsystem1620and/or display subsystem1630. Additionally, I/O controller1640illustrates a connection point for additional devices that connect to computing device1600through which a user might interact with the system. For example, devices that can be attached to the computing device1600might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.

As mentioned above, I/O controller1640can interact with audio subsystem1620and/or display subsystem1630. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device1600. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem1630includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller1640. There can also be additional buttons or switches on the computing device1600to provide I/O functions managed by I/O controller1640.

In some embodiments, computing device1600includes power management1650that manages battery power usage, charging of the battery, and features related to power saving operation. Memory subsystem1660includes memory devices for storing information in computing device1600. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem1660can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device1600. In some embodiments, Memory subsystem1660includes the scheme of analog in-memory pattern matching with the use of resistive memory elements. In some embodiments, memory subsystem includes a 4-state spin Hall memory, according to some embodiments

In some embodiments, computing device1600comprises connectivity1670. Connectivity1670includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device1600to communicate with external devices. The computing device1600could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.

Connectivity1670can include multiple different types of connectivity. To generalize, the computing device1600is illustrated with cellular connectivity1672and wireless connectivity1674. Cellular connectivity1672refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface)1674refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication.

In some embodiments, computing device1600comprises peripheral connections1680. Peripheral connections1680include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device1600could both be a peripheral device (“to”1682) to other computing devices, as well as have peripheral devices (“from”1684) connected to it. The computing device1600commonly has a “docking” connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device1600. Additionally, a docking connector can allow computing device1600to connect to certain peripherals that allow the computing device1600to control content output, for example, to audiovisual or other systems.

In some embodiments, some components may be formed on wafer1while other components may be formed on wafer2, and then the two wafers can be joined or bonded together as described with reference to various embodiments. In some embodiments, all active devices are formed in wafer1while wafer2has most of the EOL layers and active/passive devices140.

The following examples pertain to further embodiments. Specifics in the examples may be used anywhere in one or more embodiments. All optional features of the apparatus described herein may also be implemented with respect to a method or process. Various embodiments here can be can be combined with any of the other embodiments thereby allowing various combinations.

Example 1 is an apparatus which comprises: a substrate; a first active device adjacent to the substrate; a first set of one or more layers to interconnect with the first active device; a second set of one or more layers; a second active and/or passive device coupled to the second set of one or more layers; and a layer adjacent to one of the layers of the first and second sets, wherein the layer is to bond the one of the layers of the first and second sets.

Example 2 includes all features of example 1, wherein the substrate, the first active device, and the first set of one of more layers are formed on a first wafer, and wherein the second set of one or more layers and the second active device are formed on a second wafer.

Example 3 according to any of examples 1 or 2, wherein the substrate includes bulk silicon or silicon-on-insulator (SOI).

Example 4 includes all features of example 3, wherein the bulk silicon includes device quality Epi.

Example 5 according to any of examples 1 or 2, wherein the layer to bond includes at least one of a dielectric or a metal.

Example 6 includes all features of example 5, wherein the dielectric includes one of: oxygen, carbon-doped oxide, polymer, or glue, and wherein the metal includes one of: Cu, Ni, or Co.

Example 7 according to any of examples 1 or 2, wherein the second active and/or passive device includes one of: high power transistor, photonic laser, inductor, or capacitor.

Example 8 according to any of examples 1 or 2, wherein the second set of one or more layers includes a layer which is to couple to a package solder bump, and wherein the layer of the second set is coupled to the second active and/or passive device.

Example 9 is a method which comprises: forming a substrate; fabricating a first active device adjacent to the substrate; forming a first set of one or more layers to interconnect with the first active device; forming a second set of one or more layers; fabricating a second active and/or passive device adjacent to the second set of one or more layers; and forming a layer adjacent to one of the layers of the first and second sets, wherein the layer is to bond the one of the layers of the first and second sets.

Example 10 includes all features of example 9, wherein the substrate includes bulk silicon or silicon-on-insulator (SOI).

Example 11 includes all features of example 10, wherein the bulk silicon includes device quality Epi.

Example 12 according to any of examples 9 or 10, wherein the layer to bond includes at least one of a dielectric or a metal.

Example 13 includes all features of example 12, wherein the dielectric includes one of: oxygen, carbon-doped oxide, polymer, or glue, and wherein the metal includes one of: Cu, Ni, Co, Al, or W.

Example 14, includes all features of example 9, wherein the substrate, the first active device, and the first set of one of more layers are formed on a first wafer, and wherein the second set of one or more layers and the second active and/or passive device are formed on a second wafer.

Example 15 according to any of examples 9 or 10 comprising: dry etching a surface of the second wafer such that pads are exposed; and forming solder bump on the exposed pads.

Example 16 according to any of examples 9 or 10, wherein the second active and/or passive device includes one of: high power transistor, photonic laser, inductor, or capacitor.

Example 17 is a method which comprises: forming, on a first wafer, one or more transistors adjacent to a substrate; forming a first set of one or more layers to interconnect the one or more transistors; forming, on a second wafer, a second set of one or more layers and an active and/or passive device adjacent to one of the layers of the second set; and bonding the first wafer with the second wafer such that one of the layers of the first and second sets couple with one another.

Example 18 includes all features of example 17, wherein the method of example 18 comprises: dry etching a surface of the second wafer such that pads are exposed.

Example 19 according to any of examples 17 or 18, wherein bonding the first wafer with the second wafer comprises applying a layer which includes at least one of a dielectric or a metal.

Example 20 includes all features of example 19, wherein the dielectric includes one of: oxygen, carbon-doped oxide, polymer, or glue, and wherein the metal includes one of: Cu, Ni, Co, Al, or W.

Example 21 according to any of examples 17 or 18, wherein the active and/or passive device includes one of: high power transistor, photonic laser, inductor, or capacitor.

Example 22 is an apparatus which comprises: one or more transistors adjacent to a substrate of a first wafer; a first set of one or more layers to interconnect the one or more transistors, wherein the first set of one or more layers are part of the first wafer; a second set of one or more layers of a second wafer; an active and/or a passive device adjacent to one of the layers of the second set; and a layer adjacent to one of the layers of the first and second sets, wherein the layer is to bond the one of the layers of the first and second sets, respectively.

Example 23 includes all features of example 22, wherein the substrate includes bulk silicon or silicon-on-insulator (SOI), and wherein the bulk silicon includes device quality Epi.

Example 24 includes all features of example 22, wherein the layer to bond includes at least one of a dielectric or a metal.

Example 25 includes all features of example 24, wherein the dielectric includes one of: oxygen, carbon-doped oxide, polymer, or glue, and wherein the metal includes one of: Cu, Ni, Co, Al, or W.

Example 26 according to any of examples 22 to 24, wherein the active and/or passive device includes one of: high power transistor, photonic laser, inductor, or capacitor.

Example 27 is a system which comprises: a memory; a processor coupled to the memory, the processor having an apparatus according to any one of apparatus examples 1 to 8 or apparatus examples 22 to 26; and a wireless interface to allow the processor to communicate with another device.

Example 28 is an apparatus which comprises: a substrate; a first active device adjacent to the substrate; means for interconnecting a first set of one or more layers with the first active device; a second set of one or more layers; means for coupling a second active and/or passive device to the second set of one or more layers; and means for bonding bond the one of the layers of the first and second sets.

Example 29 includes all features of example 28, wherein the substrate, the first active device, and the first set of one of more layers are formed on a first wafer, and wherein the second set of one or more layers and the second active device are formed on a second wafer.

Example 30 according to any of examples 28 or 29, wherein the substrate includes bulk silicon or silicon-on-insulator (SOI).

Example 31 includes all features of claim30, wherein the bulk silicon includes device quality Epi.

Example 32 according to any of examples 28 or 29, wherein the means for bonding includes at least one of a dielectric or a metal.

Example 33 includes all features of example 32, wherein the dielectric includes one of: oxygen, carbon-doped oxide, polymer, or glue, and wherein the metal includes one of: Cu, Ni, or Co.

Example 34 according to any of examples 28 or 29, wherein the second active and/or passive device includes one of: high power transistor, photonic laser, inductor, or capacitor.