Method and apparatus for a multiplexed address line driver

A method and apparatus for multiplexing various voltage magnitudes onto the address line of a memory cell. An address line voltage generator applies complex analog voltage magnitudes to a memory cell address line during Power On Reset (POR) to insure proper memory cell initialization during power up. Once initialized, read and write address select signals are level shifted to be equal to or greater than the read and write voltage magnitudes applied to the memory cell address line to ensure proper operation.

FIELD OF THE INVENTION

The present invention generally relates to memory cell addressing schemes, and more particularly to a voltage multiplexing architecture used in conjunction with the memory cell addressing and power up schemes of a Programmable Logic Device (PLD).

BACKGROUND OF THE INVENTION

PLDs are a well-known type of integrated circuit that may be programmed to perform specified logic functions. One type of PLD, the Field Programmable Gate Array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, Input/Output Blocks (IOBs), Configurable Logic Blocks (CLBs), dedicated Random Access Memory Blocks (BRAM), multipliers, Digital Signal Processing blocks (DSPs), processors, clock managers, Delay Lock Loops (DLLs), and so forth.

Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by Programmable Interconnect Points (PIPs). The programmable logic implements the logic of a user design using programmable elements that may include, for example, function generators, registers, arithmetic logic, and so forth.

The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data may be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.

Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to Input/Output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In some CPLDs, configuration data is stored on-chip in non-volatile memory. In other CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.

Part of the FPGA design methodology is to allocate one or more power supplies within the FPGA depending upon the requirements of the particular functional blocks that are incorporated within the FPGA. Some FPGA blocks, such as the BRAMs, are designed with transistors having relatively thin gate oxide layers for operation at a relatively low voltage level to minimize power consumption. In the I/O portions of the FPGA, on the other hand, a higher operational voltage is required because communication with devices external to the FPGA necessitates an extended dynamic range. Still other portions of the FPGA are designed for operation using multiple power supply magnitudes, thus requiring transistors exhibiting varying oxide thicknesses, depending upon voltage level.

A programmable interconnect tile is then used to interconnect the various blocks of the FPGA. N-type Metal Oxide Semiconductor (NMOS) transistors, for example, are typically used as passgates, whereby higher level signals incident at the gate terminal of the passgates cause relatively lower level signals to propagate from the drain to source, or from the source to drain, terminals.

In the prior art, the disparity between the VGGlevel signals and the VDDlevel signals is minimal, being separated, for example, by approximately 50 millivolts (mV). Allowing for a greater differential to exist between VGGand VDDwould provide several advantages not currently realized by the prior art. Among these advantages includes, providing for an extended differential between the VGGand VDDvoltage levels to allow for an improved propagation time through the interconnect tile.

Such a voltage differential, however, is generally not supported by the prior art and hence cannot support an improved propagation time. Large voltage differentials were supported in the early version PLDs, however, such a voltage differential cannot be supported by the modern deep sub-micron and sub-100 nanometer (nm) memory cell designs.

SUMMARY OF THE INVENTION

To overcome limitations in the prior art, and to overcome other limitations that will become apparent upon reading and understanding the present specification, the present invention discloses an apparatus and method for multiplexing analog voltages onto an address line of a memory cell. The multiplexing occurs in a manner that is consistent with an operational state of the memory cell.

In accordance with one embodiment of the invention, a method of controlling a signal level of a memory cell address line comprises detecting an operational state of a memory cell, selecting one of a plurality of multiplexed signal levels onto the memory cell address line in response to the operational state, and level shifting a first logic level of a memory cell address select line to be at least equal to the selected signal level.

In accordance with another embodiment of the invention, a memory cell address line generator comprises an analog driver that is adapted to generate a first signal having first and second amplitudes. The memory cell address line generator further comprises an address line generator that is coupled to the analog driver and is adapted to provide the first signal to a memory cell address line during first and second modes of operation and is further adapted to apply a second signal having a plurality of amplitudes to the memory cell address line during a third mode of operation. The memory cell address line generator further comprises a level shifter that is coupled to the analog driver and is adapted to increase a level of a received memory cell address select signal to be at least equal to the first and second amplitudes of the first signal.

In accordance with another embodiment of the invention, a system of addressing a memory cell within a Field Programmable Gate Array (FPGA) comprises means for applying a plurality of voltage signal levels to an address line of a memory cell during a power up sequence, means for applying a read voltage signal level to the address line during a read sequence, means for applying a write voltage signal level to the address line during a write sequence, and means for shifting an amplitude of an address select signal associated with the memory cell to be at least equal to the read and write voltage signal levels during the respective read and write sequences.

DETAILED DESCRIPTION OF THE DRAWINGS

The various embodiments of the present invention may be applied to the field of PLDs, which utilize a plurality of operational voltage levels during operation. The present invention contemplates a scheme to selectively drive the address line of a memory cell array to any one of these operational voltage magnitudes as needed. The operational voltage magnitudes may be directly connected to power supplies, or may be optionally derived from the power supplies via, e.g., voltage regulators.

Any combination of memory cells may be supported, to include so-called heterogeneous columns containing a mix of memory cells operating from different operational voltage levels. In one embodiment according to the present invention, for example, a complex multiplexer receives operational voltages from an analog voltage generator and in response to operational logic, applies the correct operational voltage to the memory cell address lines. As such, the correct voltage magnitude is applied to the memory cell address lines depending upon the corresponding operational state, e.g., memory cell read, memory cell write, or memory cell power-up.

It should be noted that while only three memory cell operational states are discussed herein, any number of operational states, N, may be supported by an embodiment of the present invention to generate, VN, address line voltage magnitudes. As such, VNvoltage magnitudes may be multiplexed onto the address lines of the memory cells as required by the particular application.

As noted above, advanced FPGAs can include several different types of programmable logic blocks in the array. For example,FIG. 1illustrates an FPGA architecture100that includes a large number of different programmable tiles including Multi-Gigabit Transceivers (MGTs)101, CLBs102, BRAMs103, IOBs104, configuration and clocking logic CONFIG/CLOCKS105, DSPs106, specialized I/O107, including configuration ports and clock ports, and other programmable logic108, such as digital clock managers, analog-to-digital converters, system monitoring logic, and so forth. Some FPGAs also include dedicated processor blocks PROC110.

In some FPGAs, each programmable tile includes programmable interconnect element INT111having standardized connections to and from a corresponding interconnect element in each adjacent tile. Therefore, the programmable interconnect elements taken together implement the programmable interconnect structure for the illustrated FPGA. INT111also includes the connections to and from the programmable logic element within the same tile, as shown by the examples of blocks102,103or106, and104.

For example, a CLB102may include a Configurable Logic Element CLE112that may be programmed to implement user logic plus a single programmable interconnect element INT111. A BRAM103may include a BRAM logic element BRL213in addition to one or more programmable interconnect elements. Typically, the number of interconnect elements included in a tile depends on the height of the tile (as measured from right to left ofFIG. 1). In the pictured embodiment, for example, a BRAM tile has the same height as four CLBs, but other multiples (e.g., five) may also be used. A DSP tile106may include a DSP logic element DSPL114in addition to an appropriate number of programmable interconnect elements. An IOB104may include, for example, two instances of an input/output logic element IOL115in addition to one instance of the programmable interconnect element INT111. As will be clear to those of skill in the art, the actual I/O pads connected, for example, to the I/O logic element115are manufactured using metal layers above the various illustrated logic blocks, and typically are not confined to the area of the input/output logic element115.

The programmable functional elements, e.g., CLBs and IOBs, and the programmable interconnect elements are programmed or configured using, in one embodiment, static random access memory cells. These memory cells are configured as described in co-pending, commonly assigned U.S. patent application Ser. No. 10/796,750 filed Mar. 8, 2004 entitled “Segmented Dataline Scheme in a Memory with Enhanced Full Fault Coverage Memory Cell Testability,” by Vasisht M. Vadi, et al., which is herein incorporated by reference and in concurrently filed U.S patent application, entitled “A METHOD AND SYSTEM FOR CONFIGURING AN INTEGRATED CIRCUIT”, by Vasisht M. Vadi, et al., which is herein incorporated by reference.

In the pictured embodiment, a columnar area near the center of the die (shown shaded inFIG. 1) is used for configuration, clock, and other control logic. Horizontal areas109extending from this column are used to distribute the clocks and configuration signals across the breadth of the FPGA.

Some FPGAs utilizing the architecture illustrated inFIG. 1include additional logic blocks that disrupt the regular columnar structure making up a large part of the FPGA. The additional logic blocks can be programmable blocks and/or dedicated logic. For example, the processor block PROC110shown inFIG. 1spans several columns of CLBs and BRAMs.

Note thatFIG. 1is intended to illustrate only an example FPGA architecture. The number of logic blocks in a column, the relative width of the columns, the number and order of columns, the type of logic blocks included in the columns, the relative size of the logic blocks, and the interconnect/logic implementations102,103or106, and104are examples. For example, in an actual FPGA more than one adjacent column of CLBs is typically included wherever the CLBs appear, to facilitate the efficient implementation of user logic.

As discussed above, memory cells existent within, for example, INT111operate at a higher operating voltage as compared to memory cells existent within an FPGA core, for example, CLE112. In particular, memory cells within INT111operate at a power supply level of VGG, whereas memory cells within the FPGA core operate at the lower voltage of VDD. In addition, the voltage level present at each of the address lines of the respective VGGor VDDmemory cells must be set in accordance with the particular operation being conducted, e.g., write, read, or power-up.

During power-up of FPGA100, for example, several phases of voltage control are performed in accordance with an embodiment of the present invention in order to avoid power supply contention and high current paths that may develop during such power supply contention. In order to initiate the first phase of power-up, a Power-On Reset (POR) signal is asserted, which is effective to disable a major portion of FPGA100to allow a smooth ramp up of the operational voltages, denoted hereinafter as VCCAUXand VDDvoltages, as well as other auxiliary voltages associated with FPGA100, denoted hereinafter as VCCO. In addition during phase1, all generated analog voltages, e.g., VGG, and memory cell address lines are held at a logic low level. Once each of the power supplies has achieved a minimum voltage magnitude, e.g., a magnitude equivalent to at least 50% of their nominal value, then signal POR is de-asserted to begin phase2.

During phase2, a disable VGGpull-down signal remains asserted to continue to require that the VGGnet, or grid, is held to a 0 volt potential for a pre-determined amount of time after the POR signal is deasserted. Once the disable VGGpull-down signal is deasserted, the VGGgrid is released from the 0 volt requirement and is allowed to slowly ramp up. In addition, each of the address line drivers for the VGGmemory cells are expected to weakly drive the address lines of all the VGGmemory cells during phase2. In this way, the VGGpower supply and the address lines of the VGGmemory cells ramp up at substantially the same rate, thus allowing a known configuration state to be achieved for each VGGmemory cell, e.g., output Q=0; outputQ=1.

Once the VGGaddress lines have achieved a voltage magnitude of at least a transistor threshold voltage, Vt, the initialization of the VGGmemory cells completes to mark the end of phase2. Phase3allows the VGGpower supply to attain its final value after the VGGmemory cells have been correctly initialized, while the VGGaddress line voltage level is held to a logic low value. Completion of phase3marks the end of power up operation.

In one embodiment according to the present invention, therefore, a VGGaddress line generator is contemplated, which supports the complex power-up sequence as discussed above in relations to phases1–3.

In addition to the complex power-up sequence, the VGGaddress line generator also supports the write and read sequences pertaining to the VGGmemory cell as required. Turning toFIG. 2, an example VGGaddress line generator200in accordance with an embodiment of the present invention is now discussed. Generally speaking, VGGaddress line generator200generates any address line voltage that may be required by the particular memory cell address line224being addressed.

That is to say, that address line voltage224may take on substantially any voltage value during the power-up, write, or read sequences as required by the memory cell being addressed, to insure proper operation through all sequences. While VGGaddress line generation for VGGmemory cells is discussed in relation toFIG. 2, it should be noted that the operation ofFIG. 2is applicable to any other memory cell address line generation that may be required within the PLD.

Logic block216in conjunction with address line voltage generator218controls the voltage magnitude present at address line224through the entire power-up sequence, as well as through the subsequent read and write sequences required during operation of the PLD. It should be noted also, thatFIG. 2represents a single address line voltage generator that is used by one of the many address lines that may be required in the PLD.

Address line voltage generator218accepts power supply inputs VDDand VCCAUX, as well as the regenerated analog voltage, ADRVR_VGG, from analog driver202and logic signals from logic block216to determine the magnitude of the address line voltage224. The regenerated analog voltage, ADRVR_VGG, may represent a magnitude that is substantially equal to 80% of the magnitude of generated voltage, VGG, due to transistor mismatch.

During the first phase of power-up as discussed above, address line voltage generator218determines if power supply VDDobtains its operational voltage magnitude sooner than power supply VCCAUX. If so, address line224is forced to a logic zero value, e.g., ground potential, until such time as the VCCAUXpower supply has reached its operational voltage level.

During the initial portion of the second phase of power-up, address line224continues to be held at a logic zero value through operation of address line voltage generator218, in response to the disable VGGpull-down signal that is received from logic block216as discussed above. After a pre-determined amount of time has passed, the disable VGGpull-down signal is deasserted and in response, address line voltage generator218weakly drives address line224to slowly bring it to a voltage level of at least a transistor threshold voltage, Vt. The slow ramp up of voltage on address line224is effective to properly initialize the memory cell (not shown) that is attached to address line224.

Address line voltage generator218is also effective to provide the proper voltage level to address line224depending upon whether the column of a particular memory cell, as illustrated inFIG. 1, of the PLD has been activated for use. If, for example, the memory cell's column is selected for writing, then its corresponding address line224is driven to a voltage level substantially equal to 80% of the voltage generated by VGGgenerator206. If, on the other hand, the memory cell's column is deselected for writing, then its corresponding address line224is driven to a voltage level substantially equal to VDD.

Thus, in a write state, address line voltage generator218selects the maximum voltage that is obtainable for application to address line224, e.g., from VGGgenerator206. If, on the other hand, the column is deselected for a write state or is otherwise not in use, then address line voltage generator218selects VDDfor application to address line224. Likewise, analog driver202disables buffer204and VGGgenerator206and selects voltage supply VDDvia multiplexer210to be routed to the ADRVR_VGGterminal.

VGGof a PLD is generally a regulated power supply and as such is a very stable reference voltage. The VGGpower grid, however, is generally unable to source a large amount of current due to the current limitations of its associated voltage regulator. Thus, buffer204and VGGgenerator206combine to regenerate VGGfrom VCCAUXat the ADRVR_VGGterminal, whereby the regenerated VGGexhibits an increased current sourcing capability from power supply VCCAUX, while at the same time exhibiting a voltage magnitude that may only be substantially equal to 80% of VGG. Turning toFIG. 3, an example schematic of analog driver202is illustrated.

In operation, analog driver202generates an analog potential substantially equal to the magnitude of the regulated VGGpower supply plus a transistor threshold voltage, Vt, as can be verified at node328. In particular, buffer204receives a control voltage, e.g., the regulated VGGvoltage, at the control terminal of transistor312. Once the gate-to-source potential, VGS, of transistor312has exceeded its threshold voltage, Vt, transistor312is rendered conductive to sink the current provided by transistor302from power supply VCCAUX.

Transistor306shares its gate connection with transistor304, such that the VGSof transistor306is substantially equivalent to the VGSof transistor304. Thus, the current conducted by transistor304is mirrored by the current conducted by transistor306in ratio proportion to the respective geometries of transistor306to304. Given that transistors304and306each exhibit substantially identical geometry, for example, the current conducted by transistor306is substantially equal to the current conducted by transistor304. Diode connected transistors308,310and314also provide a Vtvoltage drop across their respective drain-source terminals.

Buffer204thus translates the voltage at the control terminal of transistor312, e.g., the regulated VGGvoltage, to a voltage that is higher in magnitude by one transistor threshold voltage, Vt, at node328. The increased voltage magnitude at node328is then applied to the control terminal of transistor318of VGGgenerator206, which renders transistor318conductive to sink the current provided by transistor316from power supply VCCAUX. Once conductive, the VGSof transistor318is substantially equal to a transistor threshold voltage, Vt, and as such, is effective to provide a voltage magnitude that is approximately equal to 80% (more or less) of the regulated voltage VGGat terminal ADRVR_VGG.

In order to insure the Vtvoltage drop across transistor318, a “leaker” current source is implemented using transistor322, and is configured as a very small, e.g., microamp (μL), current source. Through operation of transistor322, therefore, a very small amount of current on the order of microamps is guaranteed to flow through transistor318, thus insuring the Vtvoltage drop across transistor318.

The source terminals of transistors324and326share a common connection at terminal ADRVR_VGGand as such, represent a multiplexing operation. That is to say, that either the voltage at the source terminal of transistor326, or the voltage at the source terminal of transistor324is applied to terminal ADRVR_VGGdepending upon the logic state of signal WRITE. Given that the logic state of signal WRITE is a logic high value, for example, then the set output, S, of SR latch208is asserted, which then renders VGGgenerator206active to effectively apply the source voltage of transistor326to terminal ADRVR_VGG. Conversely, if the logic state of signal WRITE is a logic low value, then the reset output, R, of SR latch208is asserted, which then renders VDDblock212active to effectively apply the source voltage of transistor324to terminal ADRVR_VGG. In this instance, transistor320is conductive to conduct current from power supply VDDto terminal ADRVR_VGG.

Thus, in a write phase of operation (i.e., signal WRITE is asserted), an analog voltage approximately equal to VGGis regenerated at terminal ADRVR_VGG, which exhibits an augmented current sourcing capability through the use of the VCCAUXpower supply. Conversely, during a non-write phase of operation (i.e., signal WRITE is deasserted), power supply approximately equal to VDDis applied to terminal ADRVR_VGG, as discussed above. It should be noted, that the regenerated VGGat node ADRVR_VGGmay not be precisely regenerated at the same magnitude as supplied by the regulated VGG, due to the Vtmismatch that may exist between the transistors of buffer204and VGGgenerator206. However, through the use of proper design procedures and Monte Carlo simulation sweeps, the effects of any Vtmismatch may be substantially eliminated.

Turning toFIG. 4, an example schematic diagram of address line voltage generator218ofFIG. 2is now discussed. As exemplified inFIG. 2, address line voltage generator218provides the top rail power supply, V226, for inverter222. Thus, the logic high potential that is applied to address line224by inverter222is governed through the operation of address line voltage generator218in conjunction with logic216and analog driver202.

The operation of address line voltage generator218may be explained in relation to each phase of operation that is associated with address line224. In particular, during the first phase of POR, inverter416and transistor418combine to detect a condition whereby power supply VDDhas reached its nominal operational voltage magnitude, but power supply VCCAUXhas not. In such an instance, the output of inverter416is at a logic high value that renders transistor418into its conductive state, which in turn forces node420, i.e., the voltage at terminal226, to be substantially equal to ground potential.

During a second phase of POR, POR logic412renders transistor414into a conductive state in order to hold node424, i.e., the voltage at terminal226, to a 0 volt potential for a pre-determined amount of time as determined by programmable delay410. After the pre-determined amount of time has expired, POR logic412renders transistor414into its non-conductive state, while transistor408is rendered into its conductive state. In this way, address line voltage generator218applies the regenerated VGGvoltage to terminal ADRVR_VGG, so that ADRVR_VGGand address line224are allowed to ramp up at substantially the same rate, thus allowing a known configuration state to be achieved for the corresponding memory cell (not shown), e.g., output Q=0 and outputQ=1.

Once initialized, the memory cell (not shown) is configured to be in a “write” state via mode sequence logic402and multiplexer404, by applying the re-generated VGGvoltage to terminal226. Conversely, when the column in which the memory cell resides is disabled, or is otherwise in a non-write state, mode sequence logic402and multiplexer404apply the lower voltage, VDD, to node426. In addition, buffer204is disabled to reduce the quiescent current drain of analog driver202when the column is disabled.

During a read operation, buffer204is also disabled to reduce its quiescent current drain. In addition, read block406is operative to gently apply VDDto terminal226once signal READ ENABLE is asserted by mode sequence logic402. In particular, transistor434is configured as a current source to supply current to transistor428once transistor428is rendered conductive by signal READ ENABLE.

The voltage drop across the drain and source terminals of transistor428is guaranteed by leaker current source432. Thus, the voltage applied to node422, e.g., the voltage at terminal226, via transistor430during the read mode is substantially equal to 80% of VDD. In addition, leaker current source432is effective to control the rate at which terminal226achieves the “read” voltage as well as to control the maximum voltage obtained at terminal226. The reduced ramp rate and maximum voltage obtained helps to prevent a disturbance to the memory cell during the read process and minimizes any bump in the memory cell during the read operation.

Turning back toFIG. 2, it can be seen that the top rail power supply of level shifter220and inverter222may be at two different voltage magnitudes. As discussed above, the voltage at terminal ADRVR_VGGmay be equal to either the regenerated VGGpotential or VDD, depending upon the particular phase of operation. The voltage at terminal226, on the other hand, may essentially take on any number of voltage magnitudes, depending upon the memory cell being addressed and its operational state.

As such, without the operation of level shifter220, a possibility exists such that a logic high level presented at the input to inverter222by logic216may not achieve a voltage magnitude that is equal to or greater than the top rail power supply voltage magnitude at terminal226. Such a condition causes sub-threshold current to be conducted by the P-type transistor228of inverter222when a logic low level is desired at address line224. In such an instance, P-type transistor228is not completely turned off.

Thus, in accordance with an embodiment of the present invention, level shifter220shifts the voltage magnitude of the logic high signals transmitted by VDDlogic216to be substantially equal to either VDDor the regenerated VGGpotential, whichever is present at terminal ADRVR_VGG. In this way, the logic high potential presented to the input of inverter222by level shifter220is guaranteed to be equal to or greater than the top rail power supply level presented at terminal226. As such, irrespective of the particular voltage that is generated by address line voltage generator218at node226, P-type transistor228of inverter222is rendered non-conductive when a logic low level is desired on address line224.

It can be seen, therefore, that level shifter220effectively shifts the logic high signal levels transmitted from logic block216up to the voltage existing at terminal ADRVR_VGG. Since the voltage at terminal ADRVR_VGGis guaranteed to be at a higher magnitude than the top rail voltage magnitude of node226, the VGSof P-type transistor228within inverter222is guaranteed to be equal to or greater than its threshold voltage, Vt. Thus, transistor228is rendered fully non-conductive under all phases of operation where a logic low level is desired on address line224.

Turning now toFIG. 5, flow diagram500is presented to illustrate an example method of controlling the address line voltage applied to a memory cell in accordance with an embodiment of the present invention. In state502, all power supplies are in a power off condition, i.e., at 0 volt output potential, the POR signal is asserted as in step504, and all power supplies are activated and allowed to achieve at least 50% of their nominal operational voltage magnitudes as in step506.

Once all power supplies have reached their 50% operational voltage magnitude, a timer programmed with a predetermined amount of time, e.g., N clock cycles, is started as in step514, while steps508–512progress. In particular, the generated VGGgrid is released from ground potential and is allowed to slowly rise in potential as in step508. Each of the address line voltage generators218within the FPGA are expected to weakly drive their respective address lines up to a potential that is substantially equivalent to a transistor threshold voltage, Vt. In so doing, the generated VGGgrid and the address lines each ramp up in voltage at substantially the same rate to initialize the memory cells as in step510. In step512, the generated VGGvoltage is allowed to ramp up to its nominal operational level. Once the timer of step514has expired, signal POR is released as in step516.

Once POR has completed, determination of the memory cell's action is made in steps518and520. If the memory cell is to be written as in step520, then the address of the memory cell is referenced to the appropriate write voltage, e.g., VGG, as in step522and the address select logic is shifted up in magnitude to be equal to or greater than the magnitude of the address line write voltage as in step524. The magnitude of the power supplies continues to be monitored, as denoted by step526, and the POR state is re-entered if it is determined that the power supplies have fallen below 50% of their nominal operational values.

If, on the other hand, the memory cell is to be read as determined in step518, then the address of the memory cell is referenced to the appropriate read voltage, e.g., VDD, as in step528and the address select logic is shifted up in magnitude to be equal to or greater than the magnitude of the address line read voltage as in step530. The magnitude of the power supplies continues to be monitored, as denoted by step532, and the POR state is re-entered if it is determined that the power supplies have fallen below 50% of their nominal operational values.

Embodiments of the present invention are believed to be applicable in a variety of memory cell applications. In particular, although the address line driver circuits disclosed herein have been discussed in relation to IC applications using MOS processes, one of ordinary skill in the art will recognize relevant application to bipolar IC processes, and discrete applications as well. Other aspects and embodiments of the present invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and illustrated embodiments be considered as examples only, with a true scope and spirit of the invention being indicated by the following claims.