Electrostatic discharge (ESD) protection device with simultaneous and distributed self-biasing for multi-finger turn-on

An ESD protection circuit for a semiconductor integrated circuit (IC) having protected circuitry, includes an SCR having at least one finger. Each finger includes a PNP transistor and an NPN transistor, where an emitter of the PNP and NPN transistors is respectively coupled between an I/O pad of the IC and ground, a base of the PNP transistor being coupled to a collector of the NPN transistor, and a base of the NPN transistor being coupled to a collector of the PNP transistor. The NPN transistor of each finger further includes a first gate for triggering said finger. A PMOS transistor includes a source and a drain respectively coupled to the I/O pad of the IC and the first gate of the NPN transistor. Further, a gate of the PMOS transistor is coupled to a supply voltage of the IC.

FIELD OF THE INVENTION

This invention generally relates to the field of electrostatic discharge (ESD) protection circuitry, and more specifically, improvements for multi-fingered MOS protection circuitry of an integrated circuit (IC).

BACKGROUND OF THE INVENTION

Robust NMOS and other ESD protection are crucial to obtain high levels of ESD robustness in CMOS technologies. In processes with the option of local blocking of silicide, ballasting resistance is introduced to ensure equal current spreading and uniform multi-finger triggering.

In order to achieve adequate ESD protection levels with high failure thresholds and good clamping capabilities, sufficient device width must be provided. Therefore, multi-finger MOS structures have been implemented for ESD protection. Furthermore, advanced CMOS technologies require high numbers of fingers, since decreasing pad pitch and minimum active area width might be largely restricted by design limitations.

A major concern with regard to multi-finger devices under ESD stress is the possibility of non-uniform triggering of the fingers. In order to ensure uniform turn-on of multi-finger structures, the voltage value at the second finger breakdown Vt2must exceed the triggering voltage Vt1of the parasitic BJT transistor, i.e. the voltage at the onset of snapback. In order to avoid damaging an initially triggered finger from a high current load, the adjacent fingers must also be switched on into the low resistive ESD conduction state (i.e. snapback). To achieve a homogeneity condition Vt1<Vt2, either the initial triggering voltage Vt1must be reduced or the second breakdown voltage Vt2must be increased.

Complications arise, for example, in standard I/O library cells, where the multi-finger MOS device is formed as a split device. In particular, the multi-finger device is formed as a split device where a first portion of the fingers is actively used by circuitry of an integrated circuit (IC) for functional purposes (i.e., the driver), and a second portion of the fingers is utilized only for ESD protection (i.e., the dummy ESD fingers). The multi-finger device can be configured for several drive strengths by including or excluding a particular number of fingers from being driven at their respective gates by a pre-driver. That is, during normal circuit operation the active fingers are controlled by the pre-driver, while the non-active dummy ESD fingers are not utilized. In this latter instance, the gates of the unused driver fingers are typically grounded, either directly or indirectly, through a resistance.

During an ESD event, trigger competition between the actively used (driver fingers) and unused fingers (dummy ESD fingers) may cause non-uniform turn-on of the normally active and non-active fingers. Specifically, the driver fingers may trigger prior to the dummy ESD fingers (i.e., non-uniform turn-on of all the fingers), which may result in failure of the MOS device and damage of the IC. As such, only a part of the total device carries ESD current, while the remainder of the device does not contribute to the current flow and remains unused.

Further problems arise for drivers or other I/O circuitry, which are configured to be over-voltage tolerant (OVT). That is, the voltage that is applied to the I/O circuitry may be higher than the supply voltage (e.g. VDD). In many over-voltage cases, a single NMOS driver may be susceptible to hot carrier injection because the applied voltage exceeds the normally specified maximum voltage between drain and gate. One method to overcome hot carrier injection concerns is to use a cascoded output driver. That is, two NMOS devices (transistors) are connected in series between an I/O pad of the IC and ground. The serially connected cascoded NMOS transistors form the output driver. The gates of the active cascoded NMOS transistor fingers, whose source is coupled to ground, are driven by the pre-driver. Alternately, the gates of the non-active (dummy ESD fingers) cascoded NMOS transistor fingers are tied to ground. Furthermore, the gates of the active and non-active NMOS transistor fingers are tied to a supply line (e.g., VDD) in a normally turned on condition, while drains are coupled to the I/O pad. In this manner, neither of the cascoded NMOS transistor's drain-gate potential can increase enough to cause a hot-carrier concern.

However, during an ESD event, the cascoded devices are difficult to trigger due to the longer base length of the parasitic NPN transistor. As such, the Vt1value increases, while the Vt2value remains substantially constant, thereby causing additional non-uniform triggering problems of the cascoded NMOS driver. Again, the issue of trigger competition may cause only a part of the transistor fingers to trigger, thereby causing premature failure. As such, there is a need in the art to provide an ESD protection device with simultaneous and distributed self-biasing for multi-finger turn-on.

SUMMARY OF THE INVENTION

The disadvantages heretofore associated with the prior art are overcome by various embodiments of an electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC) having protected circuitry. The ESD protection circuit has a simultaneous and distributed self-biased multi-finger turn-on MOS device. In one embodiment, each finger of a plurality of fingers comprise a P-well, a plurality of N+ drain regions interspersed in the P-well, where the N+ drain regions are coupled to a high potential.

Each finger of the plurality of fingers also include a plurality of N+ source regions interspersed in the P-well and substantially parallel with the plurality of interspersed N+ drain regions, where the N+ source regions are coupled to ground. A gate region is disposed between the plurality of interspersed N+ drain regions and the plurality of interspersed N+ source regions and over the P-well region.

Additionally, a first plurality of P+ local substrate tie regions are interspersed between and electrically isolated from the plurality of interspersed N+ drain regions, and a second plurality of P+ local substrate tie regions are interspersed between and electrically isolated from the plurality of interspersed N+ source regions. Furthermore, at least one of the first and/or second plurality of P+ substrate tie regions of at least two fingers are electrically connected, and the gate region of each finger is coupled to any one element comprising a pre-driver circuit, ground, and the first and second plurality of P+ local substrate tie regions.

In a second embodiment, an ESD protection circuit includes a simultaneously biased multi-finger turn-on MOS device for a semiconductor integrated circuit (IC) having protected circuitry. The ESD protection circuit includes a multi-fingered NMOS transistor, where each finger has a drain and source for respectively coupling between an I/O pad of the IC and ground, as well as a gate for biasing the finger.

Additionally, an ESD detector includes a PMOS transistor having a source coupled to the I/O pad of the IC, as well as a gate for coupling to a supply voltage of the IC. A parasitic capacitance is formed between the supply line of the IC and ground. A transfer circuit having a first diode is coupled between the drain of the PMOS transistor and the gate of each finger of the NMOS transistor.

DETAILED DESCRIPTION OF THE INVENTION

The present invention is described with reference to CMOS devices. However, those of ordinary skill in the art will appreciate that selecting different dopant types and adjusting concentrations allows the invention to be applied to other devices that are susceptible to damage caused by ESD. The present invention includes various illustrative embodiments utilizing a multi-fingered NMOS device, which may provide dual functions as a driver during normal operation (powered state) of the IC, and as an ESD protection device when the IC is in a non-powered state.

FIG. 1depicts a top view layout of a multi-finger turn-on NMOS ESD/driver device100of the present invention.FIGS. 2A-2Cdepict cross-sectional view layouts of the NMOS ESD/driver device ofFIG. 1, along respective lines a-a′, b-b′, and c-c′, and should be viewed along with FIG.1. The illustrative embodiment inFIGS. 1 and 2Athrough2C provide a layout for providing simultaneous triggering of the multiple fingers of the NMOS ESD/driver device. The illustrative layout advantageously affords greater circuit design versatility. For example, the fingers of the NMOS device may be split into a first group of fingers actively used during normal IC operation, and a second group of fingers, which are passive and used as passive (dummy) fingers during non-powered IC conditions for ESD events. Both, the active fingers and the passive fingers are required together to achieve a total device size that is sufficient to safely shunt a certain amount of ESD current to ground.

The layout also provides for nearly simultaneous turn-on of all the fingers (i.e., both active and passive finger groups) by various alternate techniques including (optional) external gate biasing of the fingers, or external substrate biasing or self-biasing of the substrate (i.e., P-substrate) formed under the well and doped regions of the fingers. The NMOS device100is fully driver compatible, meaning that the active driver fingers also contribute during ESD protection during non-powered IC conditions, while acting as active transistor and not interfering with normal circuit operation during powered-on IC conditions. These advantages are discussed in greater detail with regard to the layout views of FIGS.1and2A-2C, as well as in the context of the multi-finger NMOS device used in various circuits, as shown and discussed with regards toFIGS. 3-13.

Referring toFIG. 1, a plurality of fingers1101through110fis formed substantially parallel in a P-well104(see FIGS.2A-2C). Each finger110comprises a drain finger region112, a source finger region114, and a gate finger region116.FIG. 1illustratively depicts drain finger regions1121through112f, source finger regions1141through114f, and gate finger regions1161through116f, where the first drain, gate and source regions1121,1141, and1161form a first finger1101.

Referring toFIG. 2A, the drain and source finger regions112and114are formed from a highly doped N+ material, which are disposed in the lower doped P-well104substantially parallel to each other. The gate finger region116(e.g., a polysilicon gate region) is disposed between the drain and source finger regions112and114over the P-well104, as well as over a thin gate dielectric layer (i.e., the gate oxide). As such, a portion of the P-well between the source and drain finger regions112and114, and under the gate regions116, forms a channel region127(e.g., channel regions12716and127f6shown inFIG. 2A) of the NMOS transistor.

Each drain finger region112further comprises a first plurality of P+ doped regions120Dinterspersed in the P-well104, where each P+ region120Dforms a local substrate tie. For example, drain finger region1121comprises P+ regions120D11through120D1m. Shallow trench isolation (STI)118is provided around each substrate tie120Dfm, thereby segmenting each drain finger112into a plurality of drain segments1221through122q, which are all coupled together near the gate region116. In other words, each drain finger region112is formed by a plurality of drain segments122qthat are connected together, and where a respective P+ local tie120Dmis disposed between each drain segment122q. For example, drain finger region1121comprises drain segments12211through1221qhaving the P+ local substrate tie regions120D11through120D1minterspersed therebetween. For purposes of clarity, it is noted that the subscript “D” and “S” respectively refer to the drain and source regions of the transistor, and the subscript references “f, m, and q” represent integers greater than one.

Likewise, each source finger region114further comprises a first plurality of P+ doped regions120Sinterspersed in the P-well104, where each P+ region120Sforms a local substrate tie. For example, source finger region1141comprises P+ regions120S11through120S1m. Shallow trench isolation (STI)118is provided around each substrate tie120Sfm, thereby segmenting each source finger114into a plurality of source segments1241through124q, which are all coupled together near the gate region116. In other words, each source finger region114is formed by a plurality of source segments124qthat are connected together, and where a respective P+ local substrate tie120Smis disposed between each source segment124q. For example, source finger region1141comprises source segments12411through1241qhaving the P+ local substrate tie regions120S11through120S1minterspersed therebetween.

Accordingly, a plurality of diodes125are formed between each N+ drain segment122and P+ local substrate tie region120, as well as between each N+ source segment124and P+ local substrate tie region120.FIG. 2Billustratively depicts diodes1251,6,12526,125f-1,6and125f,6formed by P+ regions120Dand drain regions122.

It is noted that each gate finger region116is formed between the drain and source finger regions112and114, and parallel to each other. It is further noted that a source and drain finger region112and114may be shared by two adjacent gate finger regions. For example, the source finger region1141is shared between adjacent gate finger regions1161and1162.

Recall, to ensure uniform turn-on of multi-finger structures, the voltage value at the second finger breakdown Vt2must exceed the triggering voltage Vt1of the parasitic BJT transistor. One common technique to increase the trigger voltage Vt2is by adding ballasting resistance, e.g., by increasing of the drain contact to gate spacing and/or the source contact to gate spacing in conjunction with silicide blocking. However, the additional process steps for the local silicide blocking are costly and known for yield losses. An efficient technique of introducing micro-ballasting resistances RDand/or RSto each drain region122and/or source region124of each finger110may be accomplished by so-called active area ballasting of the N+ drain122and/or source regions124and/or by back-end implementation of resistive ballasting elements (from the silicon contacts up). Where the active area ballasting is provided, the ESD current is confined in parallel resistive channels each being fed by a limited number of silicon contacts. The N+ drain and source regions may alternately be fully silicided, thereby avoiding the costly silicide-blocking steps.

Referring toFIG. 1, preferably, micro-ballasting resistors Rdand Rsare provided in both the drain and source segments122and124of each finger110. For example, the drain segments12211through1221qof the first drain finger1121respectively comprise ballasting resistors RD11through RD1q. Similarly, the source segments12411through1241qof the first source finger1141respectively comprise ballasting resistors Rs11through RSiq. The illustrative technique of providing sufficient ballast resistance helps to fulfill uniform current spreading within one finger. For a detailed description of providing ballasting resistance, the reader is directed to U.S. patent application Ser. No. 09/583,141, filed May 30, 2000, which is incorporated by reference herein, in its entirety. One skilled in the art will recognize that other techniques to enhance ESD robustness of the NMOS devices include silicide blocking or a fully silicided NMOS transistor device.

The drain segments1221through122qof each respective drain finger region112are coupled via an external metallic connection, such as metallic connection130D1through130Df. The metallic connection130D1through130Dfare coupled to each drain segment122via contacts (e.g., contact141D11) affixed to each drain segment122. Likewise, the source segments1241through124qof each respective source finger region114are coupled via a metallic connection, such as metallic connection130S1through130Sf. The metallic connection130S1through130Sfare coupled to each source segment122via contacts (e.g., contact141S11) affixed to each source segment124. In one embodiment, the metallic connections130D1through130Dfof the drain regions112, as well as130S1through130Sfof the source regions114are respectively coupled to the I/O pad20and to ground15, as further discussed in the embodiments ofFIGS. 3,6, and8.

Similarly, the interspersed P+ doped regions forming the local ties120Dfmof the drain finger regions112and120Sfmof the source finger regions114, are coupled via external coupling such as metallic connections132. In one embodiment, the external metallic connections132are coupled to at least two P+ doped regions120via contacts142. In a second embodiment (as shown in FIG.1), the external metallic connections132are coupled to each P+ doped region120via contacts142(e.g., contacts142D11and142S11affixed to each P+ doped region120). In this second embodiment, the external metallic connections132form a metal grid to connect all the local substrate ties120of the drain and source fingers112and114together.FIGS. 2B and 2Cillustratively show the metal grid132coupled to each substrate tie120.

It is noted that the P+ local substrate ties120provide a mechanism to enable self-biasing of the entire multi-finger NMOS device100. That is, the local substrate ties120, which are connected together by metal grid132, will distribute the local substrate potential increase resulting from a local drain-to-substrate junction breakdown. The increased substrate potential distributed around the structure will lower the triggering voltage of the other fingers110to provide a simultaneous substrate self-biasing, and therefore ensure uniform turn-on of the fingers110of the NMOS device100. Moreover, the substrate ties120(via the metal grid132) may be further coupled to a substrate bias generator, which will bias and simultaneously trigger the fingers110of the NMOS device100.

Where self-biasing via the substrate-ties120is utilized, the gates116of each finger110may be grounded (for dummy ESD fingers) or connected (for a active driver fingers) to a pre-driver (not shown). Alternately, the gates116of the dummy ESD fingers may be connected to the grid132of local substrate ties120for further enhanced reduction in the trigger voltage. The external connections to the drain, source, and gate regions112,114, and116of each finger110are described in further detail below with regard toFIGS. 3,6, and8.

The number of fingers in the entire multi-finger NMOS device100may typically range from 10 to 30 fingers. In one embodiment, the multiple fingers110of the illustrative NMOS device100are apportioned (split) into groups of active and dummy fingers. In a second embodiment, the multiple fingers of the NMOS device may all be dedicated as active fingers, while in a third embodiment, the multiple fingers of the NMOS device100may all be dedicated as dummy fingers. Apportioning the fingers of the NMOS device100is application specific, where the number of active and dummy fingers varies from application to application. That is, the type and use of the IC circuitry dictates the apportionment requirements (active and/or dummy fingers) of the fingers of the NMOS protection device100. For example, an NMOS device100of the present invention may illustratively have twenty fingers110, where 2 are dedicated as active driver fingers coupled to a pre-driver, and the remaining 18 passive fingers serve as dummy ESD fingers.

It is also noted that the size (i.e., width) of the fingers110may also vary within a single NMOS device100(e.g., 20-50 micrometers). One skilled in the art will recognize that the number of fingers110, groupings of fingers as being active and/or passive, and their size are a matter of design specification. That is, the total active finger width depends on the required functional drive strength, while the total device width depends on the required ESD strength.

FIG. 3depicts a schematic block diagram of a portion of an integrated circuit (IC)10having a multi-finger MOS device100and ESD control circuit300of the present invention. The present invention utilizes available components of the IC10for normal circuit operation, as well as additional ESD protection circuitry150during non-powered IC conditions. In particular, components of the IC10used during normal operation include an I/O pad20, a pre-driver600, at least one supply line (e.g., VDD90and VDDx91, where x is an integer greater than one), and respective parasitic capacitors CDD900and CDDx901. It is noted that parasitic capacitors CDD900and CDDx901are illustratively formed and coupled respectively between the supply line90and ground15, and supply line91and ground15. The pre-driver600and an optional PMOS driver700are also considered part of the normal IC operation circuitry.

The ESD protection circuitry includes an ESD-hardened multi-finger NMOS device100(with active and/or dummy fingers), and an ESD control circuit300. The ESD control circuit300comprises an ESD detector310, an optional transfer circuit320, an optional voltage limiter330, an optional pre-driver control circuit500, and optional grounding resistors800and801.

Referring toFIG. 3, the NMOS device100is coupled between the pad20and ground15. An optional multi-finger PMOS driver700(drawn in phantom) is coupled between the supply line VDD90and the pad10. The ESD detector310is coupled to the pad20and either voltage supply line VDD90or VDDx91. The ESD detector310is further coupled (via line30) to the ground resistor800, which is further coupled to ground15. In an embodiment where a dummy pre-driver (not shown) is utilized for ESD dummy fingers of the NMOS device100, the ESD detector310is further coupled (via line31) to a second ground resistor801, which is also coupled to ground15.

The ground resistors800and801guarantee that other components (i.e., transfer circuit320and voltage limiter330) remain off during normal circuit operation. Furthermore, during a non-powered IC state and ESD event at the pad20, the ground resistors800and801provide the necessary biasing for the voltage limiter330and pre-driver control. Additionally, one skilled in the art will recognize that in an embodiment utilizing the optional PMOS driver700, a corresponding pre-driver (not shown) is coupled to the gates of the multi-finger PMOS device700in a similar manner as shown for the pre-driver600and the NMOS transistor device100.

Optionally, the transfer circuit320is coupled between the ESD detector310and ground15. The optional transfer circuit320is further coupled to the NMOS device100via line40for the active fingers153and via line41for the dummy ESD fingers151. In an embodiment where the NMOS device100comprises cascoded transistors (see FIG.7), the optional transfer circuit30is coupled to the upper NMOS transistor of the cascoded transistors via line44. In an alternate embodiment, the optional voltage limiter330may also be provided between the transfer circuit320and ground15. That is, the transfer circuit320is coupled to the voltage limiter330via lines20,21, and45, thereby limiting the voltage for the respective connections40,41,44to the NMOS device100, and the voltage limiter330is further coupled to ground15.

The pre-driver600is coupled to the supply voltage VDDx91and the gates of the active fingers of the NMOS device100via line40. Where the optional transfer circuit320and/or voltage limiter330are provided, the pre-driver600is also coupled to a node312between the transfer circuit320and voltage limiter330. Where a dummy pre-driver (part of the normal pre-driver600inFIG. 3) is utilized for the passive fingers of the NMOS device100, the dummy pre-driver is coupled, via line41, to node313between the transfer circuit320and voltage limiter330. The optional pre-driver control500is coupled to the pre-driver600and ground15. If the optional voltage limiter330is provided, the pre-driver control500is also coupled to the voltage limiter330via lines50(for normal pre-driver600) and51(for dummy pre-driver600). Furthermore, the pre-driver600has an input line60coupled to further functional parts of the circuit (not shown) as required to fulfill its regular functionality. For the dummy pre-driver600, a similar connection61is provided.

The configuration and connectivity between the above-mentioned components of the IC10and ESD control device300of the present invention (as illustrated by the blocks ofFIG. 3) are defined in various embodiments inFIGS. 4-13, and are discussed in further detail below. Circuit analysis is provided for normal circuit operation of the IC10, and during a non-powered state of the IC10, when an ESD event occurs at the illustrative pad20of the IC10. The following embodiments of the multi-finger NMOS ESD protection device100must protect the circuitry of the IC10during an ESD event under non-powered conditions. Moreover, during normal operation of the IC10(i.e., the IC is powered on), the multi-finger NMOS device100and the ESD control circuitry150must not interfere with the operation of the circuitry of the IC10.

The operation of the circuit shown inFIG. 3is discussed generally in terms of normal powered-on IC operation and non-powered IC operation during an ESD event. Detailed circuit analysis is shown below with regard toFIGS. 4-13for each embodiment of the invention.

The ESD detector310is used to derive a bias signal and providing a multi-finger turn-on for the entire NMOS device100. The ESD detector310senses the occurrence of an ESD event to the pad20. Generally, during normal circuit operation, the IC10is powered and the parasitic capacitor of the supply lines CDD900and CDDx901(e.g., approximately 10 pico Farads to 10 nano Farads) are charged such that the supply lines VDD90and VDDX91remain at the supply line potential, which is above ground15. As such, the ESD detector310is pulled to a high state for normal circuit operation and in one embodiment, the ESD detector310is turned off. When the ESD detector310is in a high state and is turned off, the pad20is decoupled from the transfer circuit320. Moreover, the transfer circuit320decouples the pre-driver600from the ESD detector310. Accordingly, the ESD protection circuit150and the active, as well as the dummy ESD fingers of the NMOS device100will not interfere with the normal operation of the IC10. Furthermore, large active circuitry (not shown inFIG. 3) is typically connected between the supply lines VDD90and VDDX91and ground15, and in parallel to the parasitic capacitors900and901.

During an ESD event when the IC10is not powered on, the parasitic capacitors CDD900and CDDx901are not charged, which couples supply lines VDD90and VDDX91to ground15. As such, the ESD detector310is pulled to a low state, and in one embodiment, the ESD detector310is turned on. Additionally, the active circuitry may draw some leakage current that is strongly depended on the applied voltage at the lines VDD90and VDDx91(the higher the applied voltage the stronger such current). The leakage paths from such active circuitry provide additional current flow to ground and are supportive to the parasitic capacitors in their function of keeping the supply lines90and91below the pad voltage during an ESD event to a non-powered IC.

When the ESD detector310is in a low state and turned on, the pad20is coupled to the transfer circuit320. The transfer circuit320will transfer a portion of the ESD voltage at the pad20from the ESD detector310to the multi-finger NMOS device100via the bias lines40,41, and44. The bias line40and the optional bias lines41and44enable all of the fingers110(active and dummy ESD fingers) of the NMOS device100to turn-on simultaneously. It is noted that the layout ofFIG. 1is preferably used in conjunction with the entire ESD protection circuit150.

The voltage limiter330serves to limit the voltage at node312during an ESD event. As will be discussed in further detail below with regard toFIGS. 4-12, the voltage limiter330protects the NMOS device100by limiting the biasing voltage to the gate fingers (active and dummy ESD fingers) of the NMOS device, and thereby reduces the risk of hot carrier degradation of the thin gate oxides.

FIG. 4depicts a schematic diagram of a first embodiment of the multi-finger NMOS device100and ESD control circuit300ofFIG. 3, including active and dummy fingers153and151of the NMOS device100. For a better understanding of the embodiment,FIGS. 3 and 4should be viewed together. Additionally, for purposes of clarity, the active and dummy (i.e., passive) fingers153and151of the NMOS device100are each shown as a single transistor device, however, one skilled in the art will understand that the single shown active and passive fingers153and151may each represent multiple fingers.

The multi-finger NMOS transistor device100is illustratively shown having ballasting resistor RDand RSby active area segmentation or back-end ballasting at the respective drain and source of the NMOS device100. Recall that inFIG. 1, the ballasted resistors RDand RSwere formed in each drain segment122and source segment124of each finger110. Furthermore,FIG. 1illustratively shows that the drain finger regions112are coupled to the I/O pad20, the source finger regions114are coupled to ground, and the gate regions116may be coupled to either ground15, a pre-driver600, a local substrate pick-up, or a bias generator, as is discussed in further detail below with regard to each of the embodiments. For purposes of consistency and clarity, the NMOS device100is shown in all of the figures having ballasting resistors RDand RS. However, one skilled in the art will recognize that the invention will work with either back end ballasting resistors or active area segmentation ballasting resistors, or with standard transistor design.

Depending on the type and use of the IC10, the NMOS device100may comprise either active and/or passive fingers. The NMOS device100accommodates normal circuit operation via the active fingers153, while ignoring the passive ESD fingers151of the multi-finger NMOS transistor100. During an ESD event under a non-powered IC state, circuit operation includes both the active and dummy ESD fingers153and151of the multi-finger NMOS transistor100, as discussed in detail further below.

Referring toFIGS. 3 and 4together, the drain and source of each finger110of the NMOS device100is respectively coupled between the pad20and ground15. Optionally, a PMOS driver700(drawn in phantom) may be provided between the supply line VDD90and the pad20.

The ESD detector310comprises a back-end ballasted resistance PMOS transistor311, having the source coupled to the pad20and the drain of the multi-finger NMOS device100. In one alternate embodiment, the PMOS transistor310may be silicide blocked to increase its intrinsic ESD robustness. In a second alternate embodiment, the PMOS transistor310may be fully silicided to provide ESD hardness, although at a typically lower level of intrinsic ESD hardness with respect to the silicide blocking embodiment.

The gate of the PMOS ESD detector311is coupled to the supply line VDD90, and the source of the PMOS ESD detector311is coupled to the pad20. The drain of the PMOS ESD detector311is coupled to the gates of the multi-finger NMOS transistor device100via the optional transfer circuit320. The PMOS ESD detector311is used to derive a bias signal and provide a multi-finger turn-on for the entire NMOS device100. The PMOS ESD detector311senses the occurrence of an ESD event to the pad20.

As illustratively shown inFIG. 4, the transfer circuit320comprises a first diode321and a second diode322. The first diode321has the anode and cathode respectively coupled to node318and to node312, which is further coupled to the gates of the active fingers153of the NMOS device100. In an instance where all of the fingers of the NMOS device100are active, then the transfer circuit may be replaced by a short from the PMOS ESD detector drain to node312. The pre-driver600is also coupled to node312to provide the functional gate signal to the gate regions116of each active finger153of the NMOS device100. Furthermore, the second diode322is coupled has the anode and cathode respectively coupled to node318and to node314, which is further coupled to the gates of the passive dummy ESD fingers151of the NMOS device100.

It is noted that regarding the biasing of the dummy ESD fingers151, the ground (Shunt) resistor R801(e.g., approximately 1 to 100 Kohm) is coupled between the cathode of the second diode322and ground15. The shunt resistor801is used to couple the passive dummy ESD fingers151to ground15during normal circuit operation and to generate a voltage drop (at node314) for the gate bias of the dummy ESD fingers151during an ESD event.

During normal circuit operation, the capacitor CDD900is charged, thereby holding the gate of the PMOS detector high (i.e., at the potential of VDD), which is greater than or equal to the potential of the drain and source of the PMOS ESD detector311. The PMOS transistor ESD detector311is turned off, which decouples the ESD detector310and diode transfer circuit321and322from nodes312and314. As such, there is no conductive path between the I/O pad20and the gates of the NMOS device100. Additionally, the pre-driver600provides the signaling voltages to the active fingers153of the NMOS transistor device100, as required under normal circuit operation. Recall that the dummy ESD fingers151of the NMOS transistor device100are decoupled by the diodes321and322of the transfer circuit320from the pre-driver600, and will not turn on except under non-powered IC and ESD conditions. Thus, the ESD detector310(PMOS transistor311) prevents interference between the ESD protection circuitry150and the functional purpose of the IC10during normal circuit operation.

During a non-powered IC state, the IC10is off and supply line VDD90is coupled to ground15via parasitic capacitor CDD900. That is, the gate of the PMOS transistor ESD detector311is pulled low to approximately ground potential. Once an ESD event occurs at the pad20, the source of the PMOS is at a higher potential than the gate of the PMOS transistor ESD detector311, and the PMOS transistor ESD detector311is turned on. The PMOS transistor ESD detector311conducts a portion of the ESD current to the gates of both the active and passive fingers of the NMOS transistor device100via the transfer circuit (i.e., the first and second diode321and322)

The transfer circuit320ofFIG. 4includes the first and second diodes321and322respectively coupled to the active and passive fingers153and151. During a non-powered IC state and an ESD event at the pad20, the transfer circuit320allows both the active and passive fingers153and151to be externally biased and simultaneously turned on (i.e., triggered). As such, the non-uniform triggering of the all the fingers151and153of the NMOS device100, as discussed above with regard to the prior art, is alleviated. Furthermore, the passive fingers151do not interfere with normal IC operation when the IC10is powered on. It is noted that the transfer circuit320is optional if the NMOS device100has only active or only passive fingers, but the transfer circuit is mandatory if the NMOS device has both types of fingers (i.e., split driver).

The optional PMOS transistor driver700(drawn in phantom), which is coupled between the supply voltage VDD90and the pad20, may be a part of the functional circuitry of the IC10. When utilized, the PMOS driver700acts during ESD as a forward biased diode between the drain terminal and the N-well terminal to shunt a portion of the ESD current to ground15, via the supply line VDD90and the capacitor CDD900. Therefore, during the charging of the capacitor CDD900during the ESD pulse, the VDD line will be at a potential that is approximately a diode voltage below the voltage at the pad20. The PMOS ESD detector311remains on because the voltage between its gate and source is the same as the diode drop across the PMOS700, which is typically above the PMOS threshold voltage.

Once the capacitor CDD900charges up and the voltage difference between source and gate of the PMOS detector transistor311falls below the threshold voltage, the PMOS transistor311is turned off. However, the time delay for the capacitor CDDto charge up until PMOS311turns off is usually long enough so that the NMOS transistor110is fully turned on. Moreover, and alternatively, the supply line VDDx for the pre-driver may be utilized for the PMOS detector transistor311as shown on FIG.3. In particular, the VDDx supply line is not directly charged by the PMOS transistor700, and therefore keeps the VDDx line capacitively on ground15ensuring the PMOS detector transistor311stays turned on.

FIG. 5depicts a schematic diagram of a second embodiment of the multi-finger NMOS device100and ESD control circuit300ofFIG. 3, including a controlled gate-voltage limiter330and a pre-driver control500.FIG. 5should be viewed in conjunction withFIGS. 3 and 4. In particular, the second embodiment ofFIG. 5is the same as shown inFIG. 4, except that a pre-driver control500has been added, and the transfer circuit320and voltage limiter330have been modified. It is noted that circuit analysis will be discussed under normal powered IC conditions and non-powered ESD conditions.

In particular, the voltage limiter330comprises a pair of cascoded NMOS transistors333and334serially coupled between the bias line40and ground15. Specifically, a first NMOS transistor333has the source coupled to ground15and the drain coupled to the source of a second NMOS transistor334. The drain of the second NMOS transistor334is coupled to the bias line40. The gate of the first NMOS transistor333is coupled to a higher potential than the source, such as the drain of the first NMOS transistor333. The gate of the second NMOS transistor334is coupled to node316.

In this second embodiment, the first and second diode321and322of the transfer circuit320are required, as discussed in the first embodiment of FIG.4. The first diode321is required for coupling a signal to the active fingers153of the NMOS transistor device100, while the second diode322enables grounding of the passive fingers151during normal operation, and biases the passive fingers151during an ESD event. That is, the gates of the passive fingers151of the NMOS device100are coupled to node314, which is formed by the second diode322and the ground resistor801, which is further coupled to ground15. Furthermore, the drain of the PMOS ESD detector311is additionally connected to node316to provide a bias for the controlled gate voltage limiter330during an ESD event, as is discussed in detail below.

A third NMOS transistor501forms the functional pre-driver control500. In particular, the drain and source of the third NMOS transistor501are respectively coupled to the input60of the pre-driver600and ground15. The gate of the third NMOS transistor501is coupled to node316. It is noted that the pre-driver600is an inverting circuit, such as an inverter comprising serially coupled NMOS and PMOS transistors (not shown), or any other logic circuit with an inverting function (NAND, NOR, among others).

During normal IC operation, the first transistor333of the cascoded transistors is turned on, while the second transistor334of the cascoded transistors of the voltage limiter330is turned off. The first transistor333is pulled high by hard wiring, while the second transistor334is pulled low to ground15via a shunt resistor R800, which is coupled to ground15. As such, the voltage limiter330does not interfere with normal operation of the IC. That is, since the second NMOS transistor334is off, the drive current from the pre-driver600flows entirely to the active fingers153of the multi-finger NMOS device100instead of flowing to ground15via the voltage limiter320.

Regarding the pre-driver control NMOS transistor501, during normal operation, the gate at node316is pulled low via the shunt resistor800, which turns the pre-driver control NMOS transistor501off. Therefore, the pre-driver control NMOS transistor501has no effect on the input60to the pre-driver inverter600. As such, the pre-driver600provides drive current, as required, to the active fingers153of the multi-finger NMOS device100during normal IC operation.

During an ESD event, the IC is in a non-powered state, and the PMOS ESD detector320is turned on, which pulls nodes318and316high. A voltage drop is formed across shunt resistor800to ground15, which biases the gate and turns on the second transistor334. As such, both first and second transistors333and334are turned on, which limits the voltage that is applied to the active fingers153of the multi-finger NMOS device100. Therefore, the voltage limiter320is activated only during a non-powered IC ESD event. It is noted that both of the cascoded transistors333and334of the voltage limiter330together provide a voltage drop having a value approximately twice the threshold voltage VTHof the individual transistor333and334.

The high potential at node316also turns the pre-driver control NMOS transistor501on. Turning the pre-driver control NMOS transistor501on, pulls the input of the input to the pre-driver inverter600to ground15, which produces a high output at the pre-driver inverter600, thereby further providing drive current and gate bias to the active fingers153of the multi-finger NMOS device100via the biasing line40.

The passive fingers151of the NMOS transistor100are connected in parallel to the active fingers153as shown in FIG.5. The gates of the passive fingers151are pulled low during normal circuit operation via the resistor801, as discussed with regard to FIG.4. Furthermore, it is noted that parts of the ESD control circuit300are provided in an identical version (not shown onFIG. 5) to ensure the same biasing for the dummy ESD fingers151as for the active fingers153. In particular, the ESD control circuit300comprises a controlled gate voltage limiter330and an optional pre-driver control501used in conjunction with a dummy pre-driver600all together, thereby ensuring the same gate biasing conditions for the dummy fingers151as for the active fingers153.

As such, during an ESD event, the active fingers153participate in shunting the ESD current from the pad20along with the passive fingers151. Moreover, both the passive and active fingers151and153are externally biased at their respective gates and all of the fingers are simultaneously turned on.

FIG. 6depicts a schematic diagram of a third embodiment of the multi-finger NMOS device100and ESD protection circuit300ofFIG. 3having a substrate pump340. In particular, the circuit is the same as shown and discussed with regard toFIG. 4, except that the transfer circuit is not needed. A substrate pump is used to bias the local substrate of the passive dummy ESD fingers151together with the active fingers153of the NMOS transistor device100.

In particular, during normal IC operation, where the IC100is powered on, the parasitic capacitor CDD900is charged such that the supply line VDD90remains above ground15at the supply potential. As such, the PMOS ESD detector311is turned off, the pad20is decoupled from the ESD control circuit300, and the substrate ties120in all the fingers110are grounded via the shunt resistor800. Moreover, the pre-driver600will provide drive current to the active fingers153of the NMOS device100, as required, and the ESD control circuit300(and the dummy ESD fingers151of the NMOS device100) will not interfere with the normal operation of the IC10.

During an ESD event when the IC is in a non-powered state, the gate of the PMOS ESD detector311is pulled to a low state, and is turned on. The ESD detector is then coupled to node316, which is further coupled to ground via the shunt resistor800.

A substrate pump340is formed between the node316and the local substrate ties120of the dummy ESD fingers151and the active fingers153. Referring toFIG. 1, recall that the plurality of P+ regions (local substrate ties)120interspersed between the drain and source segments122and124were interconnected via a metal grid132. The metal grid132is further coupled to node316, such that the metal grid132and interspersed P+ doped regions120form the substrate pump340.

Once the ESD event occurs, a voltage at node316(formed by a voltage drop across the shunt resistor800) causes the biasing to be distributed across all of the active and passive fingers153and151. That is, the substrate pump340provides distributed biasing such that the P+ region local substrate ties120act as trigger taps to all the fingers110. Therefore, the active and passive fingers153and151will simultaneously turn on to shunt the ESD current to ground15.

It is noted that this third embodiment does not require a transfer circuit component to turn on the dummy ESD fingers151and the active fingers153of the NMOS device100. Rather, the distributed P+ local substrate ties120, forming the substrate pump340, simultaneously trigger both the active and passive fingers153and151of the NMOS device100. It is further noted that a substrate ring may alternately be used instead of the distributed P+ regions120to provide distributed biasing of the active and passive fingers153and151of the NMOS device100.

It is also noted in the embodiment shown, the gate of the optional PMOS driver700is coupled to the pre-driver600and gate of the active fingers153of the NMOS device. Alternately, a separate pre-driver (not shown) may be coupled to the gate of the optional PMOS device700.

In the embodiments shown inFIGS. 4-6, the voltage potential at the I/O pad20during normal circuit operation was below the voltage potential at the supply line VDD90. In alternate embodiments of the multi-finger NMOS transistor device100and ESD circuitry, an over-voltage condition may exist, where the voltage potential at the I/O pad20is above the voltage potential at the supply line VDD90. The over-voltage condition usually occurs at the pad20from external sources (circuitry) to the IC10, rather than from the IC10itself. In this alternate embodiment, the I/O circuitry of the IC10may be said to be “over-voltage tolerant (OVT)”, and may be used in an over-voltage condition without circuit malfunction or device degradation during normal IC operation.

FIG. 7depicts a schematic diagram of a fourth embodiment of the multi-finger NMOS device100and ESD control circuit300of FIG.3. In particular, the inventive circuit comprises a cascoded NMOS transistor device100, an ESD detector310, a transfer circuit320., a controlled gate-voltage limiter330, a pre-driver control500, and a pre-driver600, which are configured according to the block diagram of FIG.3. More specifically, block components ofFIG. 7are configured similar to the schematic diagram ofFIG. 5, except for the notable differences as described hereafter.

The NMOS transistor device100illustratively comprises passive fingers1051and active fingers1053. Each finger comprises two cascoded NMOS transistors (i.e., first and second cascoded transistors1012and1014) coupled in series between the pad20and ground15. For example, passive finger1051comprises first and second cascoded transistors1012pand1014p, while active finger1053comprises first and second cascoded transistors1012aand1014a. For purposes of clarity, it is noted that the subscripts “a” and “p” respectively identify the cascoded transistors as being active and passive transistors.

In one embodiment, each NMOS transistor1012and1014has a similar layout structure as shown and discussed with regard to FIGS.1and2A-2C. It is further noted that the ballasted drain and source resistances RDand RSare utilized to enhance ESD robustness of the NMOS. Alternately, silicide blocking or a fully silicided NMOS transistor device100may be utilized. The NMOS transistor is typically cascoded to limit the drain-gate voltage at each stage and prevent damage to the gate oxides.

The circuit ofFIG. 7is termed an open-drain NMOS device, since the pad20is only coupled to the drain (of the first transistor1012) of the cascoded NMOS device100, as opposed to additionally having a PMOS driver700coupled between the supply line VDD90and the pad20, as illustratively shown in FIG.9. The circuit ofFIG. 7is used where the PMOS driver700is not required for IC functionality.

ESD detector310comprises the PMOS transistor311and a plurality of diodes372. In particular, the source of the PMOS transistor is coupled to the pad20, while the drain is coupled to the transfer circuit320. The gate of the PMOS transistor is coupled to the plurality of diodes372, which are coupled to the supply line VDD90with the cathodes directed towards the VDD line and the anodes directed towards the gate and N-well tie377of the PMOS311.

During normal circuit operation where the IC10is powered on, if the voltage at the pad20exceeds the supply line voltage VDD90, then the plurality of diodes372plus a source-Nwell diode371formed in the PMOS ESD detector transistor311form a diode chain373from the pad20to the supply line VDD90. The voltage drop across the plurality of diodes372is used to ensure that the PMOS detector transistor311is not turned on during an over-voltage condition under normal circuit operations conditions. Typical over-voltage conditions range up to 3 volts above the potential of the supply line VDD90. During an ESD event, a similar but distinctively higher over-voltage condition will exist, while the supply line VDD90is capacitively coupled to ground. There will be current flow through the diode chain373to the capacitively grounded VDD line90, and the voltage drop across the source/Nwell diode371will provide the necessary source-gate voltage to turn-on the PMOS detector transistor311.

During an over-voltage condition under normal operation, all of the diodes in the diode chain373operate in slight forward biased mode but practically in a non-conductive state, such that a voltage of 0.2-0.4 volts forms across each diode. InFIG. 7, the plurality of diodes illustratively comprises four diodes, and the PMOS transistor311forms a fifth diode in the diode chain373, such that a voltage drop between 1.0 and 2.0 volts can appear between the pad20and supply line VDD90without any significant current from the pad to the VDD line. The number of diodes in the diode chain373is a design consideration dependent on the external over-voltage applied to the IC10and the threshold voltage of the PMOS detector transistor311, which must not be exceeded by the voltage drop of the diode371of the PMOS311.

For example, if an over-voltage condition will arise where the pad20has a potential of 5.0 volts and the supply line VDD90is 3.3 volts, then the over-voltage is 1.7 volts. That is, each of the five diodes of the diode chain373(i.e., four diodes forming the plurality of diodes372plus diode371) will have a voltage drop of 0.34 volts. Moreover, the PMOS detector transistor311is assumed to have a threshold voltage of 0.5V in this example. As such, a diode chain373comprising 5 diodes (as shown inFIG. 7) is sufficient to equalize the potential between the pad20and the supply line VDD90without any significant current flow, while also maintaining the PMOS detector transistor311in off state.

As such, the ESD detector embodiment ofFIG. 7is compatible with the over-voltage tolerant condition under normal IC operation because the diode chain373of the ESD detector310prevents any current from flowing from the pad20to the supply line VDD90. The ESD detector310senses whether the IC is operating under normal powered-on IC conditions (including the over-voltage condition) or non-powered (over-voltage) ESD conditions.

The pre-driver600is coupled to the gates of the second cascoded transistors1014aof the active fingers1053of the NMOS device100, while in one embodiment, the gates of the first cascoded transistors1012aof the active fingers1053are coupled through a resistor1020to the supply line VDD90. Resistor1020may be any resistive element (typically above 1 kOhm) and is required to avoid loss of the gate bias during ESD to the capacitively grounded supply line90, while during normal operation conditions, the gate is biased to VDD as required for the operation of the cascoded NMOS transistor100.

The controlled voltage limiting circuit330comprises the shunt resistor800coupled between node316and ground15. Furthermore, the cascoded first and second voltage-limiting NMOS transistors333and334are coupled between biasing line40at node312and ground15, as discussed above with regard to FIG.5. That is, the cascoded first and second voltage-limiting NMOS transistors333and334are coupled between the gate of the second NMOS transistor1014aof the active fingers1053and ground15.

A third and a fourth voltage-limiting NMOS transistor335and336are also each coupled serially (cascoded) with the first voltage-limiting NMOS transistor333. Specifically, the NMOS transistor335has the drain coupled to the node315(i.e., gates of the first cascoded active as well as dummy ESD NMOS transistor1012of the NMOS device100). The NMOS transistor336has the drain coupled to the gate of the second transistor1014pof the dummy ESD fingers. The sources of the third and fourth voltage-limiting NMOS transistors335and366are coupled to the source of the second voltage-limiting NMOS transistor334as well as to the drain of the first voltage limiting NMOS transistor333. The gates of the second through fourth voltage-limiting NMOS transistors334-336are coupled to the node316.

During normal IC operation, the first transistors1012aand1012pof the active fingers1053and dummy ESD fingers1051are turned on, the second transistor1014aof the active fingers1053provides the switching action for the signal and as discussed with regard to the embodiments ofFIGS. 3-6. The second transistor1014pof the ESD dummy fingers1051is off because its gate is pulled to ground15via a resistor801, such that the ESD dummy fingers1051are not utilized during normal IC operation. The PMOS ESD detector311is off, which decouples the transfer circuit320and voltage limiter330from the NMOS device100.

Furthermore, during normal IC operation, the first transistor333of the voltage limiting transistors is turned on, while the second through fourth voltage-limiting transistors334through336of the voltage limiter330are turned off. In particular, the gate of the first voltage-limiting transistor333is pulled high by hard wiring, while the gates of the second through fourth voltage-limiting transistors334through336are pulled low to ground15via the shunt resistor R800. As such, the voltage limiter330does not interfere with normal operation of the IC. Since the second voltage limiting NMOS transistor334is off, the drive current from the pre-driver600flows entirely to the active fingers153of the multi-finger NMOS device100, instead of flowing to ground15via the voltage limiter320(i.e., flowing through voltage limiting NMOS transistors333, and334). Where the pre-driver600comprises an inverter circuit, the optional pre-driver controller500may be utilized to provide additional bias to the second transistor1014aof the active fingers of the NMOS device100as discussed in regard toFIGS. 5 and 7.

During non-powered ESD conditions, the IC10is turned off. When an ESD event occurs at the pad20, the gate of the PMOS transistor ESD detector311is pulled low to ground15, via parasitic capacitor900, which turns the ESD detector310on. The ESD detector310passes part of the ESD current to the transfer circuit320(via diodes321,322, and325), which turns on both the active and passive dummy ESD cascoded fingers1053and1051of the NMOS device100.

Regarding the biasing and turn-on of the transistors1012and1014of the active fingers1053and dummy ESD fingers1051, the transfer circuit320comprises diodes321,322, and325. Diode321has the anode and cathode respectively coupled to node318and to node312, which is coupled to the gate of the second cascoded NMOS transistor1014aof the active finger1053of the NMOS device100. Diode322has the anode and cathode respectively coupled to node318and to node314, which is coupled to the gate of the second cascoded NMOS transistor1014pof the dummy ESD fingers1051.

Diode325has the anode and the cathode respectively coupled to node318and to the gate of the first NMOS transistor1012. In particular, diode325is coupled at node315formed between the resistor1020and the gate of the first NMOS transistor1012of the NMOS device100. During an ESD event the supply line VDD90is capacitively coupled to ground15. The resistor1020prevents the current to flow from node318, through diode325, to ground15via supply line VDD90. As such, the resistor1020ensures biasing of the gates of the first transistors1012aand1012p.

Furthermore, during an ESD event, all transistors333through336of the voltage limiting circuit330are turned on. In particular, the gate of the first voltage-limiting transistor333is pulled high by hard wiring, while the gates of the second through fourth voltage-limiting transistors334through336are pulled high at their respective gates at node316. As such, the voltage limiter330is only active during ESD and does not interfere with normal operation of the IC. When the second through fourth voltage-limiting transistors334through336are turned on, the gate biasing at the first and second cascoded NMOS transistors1012and1014of the active fingers1053and the dummy ESD fingers1051is limited but sufficiently high to ensure uniform turn-on of all fingers of the cascoded NMOS transistor100.

It is noted that instead of the previously discussed gate-biasing method, the substrate biasing method, as discussed with regard toFIG. 6, is also a possible embodiment for uniform turn-on of the cascoded NMOS transistors1012and1014. Again, as already mentioned in the context of FIG.6, the illustrative layout as shown in FIGS.1and2A-2C provides distributed biasing of the substrate and simultaneous turn-on of all the cascoded transistors1012pand1014pof the passive fingers1051, as well as the cascoded transistors1012aand1014aof the active fingers1053. Essentially, the same biasing scheme as inFIG. 6is utilized and no interference with the pre-driver will take place.

FIG. 8depicts a schematic diagram of a fifth embodiment of the multi-finger NMOS device and ESD protection circuit ofFIG. 3having a substrate pump. In particular,FIG. 8is similar to the circuit shown inFIG. 6having a substrate pump340biasing both the active in passive fingers153and151of the NMOS device100. Furthermore,FIG. 8is the same as the embodiment ofFIG. 7, except that the transfer circuit320, voltage limiter330, pre-driver control500, and ground resistor801are not provided.

Referring toFIG. 8, the first cascoded transistors1012of the active and passive fingers1053and1051are coupled to the supply line VDD90via resistor1020. A diode321has its anode and cathode respectively coupled to the drain of the PMOS ESD detector transistor311and to the gates of the first cascoded transistors1012aand1012p, as discussed above with regard to FIG.7. The gates of the second cascoded NMOS transistor1014aof the active fingers1053are coupled to the pre-driver600, as also discussed with regard to FIG.7. The gates of the second cascoded NMOS transistor1014pof the passive fingers1051are coupled to ground15.

Moreover, the local substrates of both cascoded transistors1012and1014of the active and passive fingers1053and1051are coupled, via the substrate pump340, to node316, which is formed between the drain of the PMOS ESD transistor311and the ground resistor800. During an ESD event when the IC10is non-powered, the substrate pump340simultaneously self-biases the active and passive fingers1053and1051, in a similar manner as discussed with regard to FIG.6. That is, the distributed P+ substrate ties120that are electrically connected (FIG.1), simultaneously turns on the active and passive fingers1053and1051of the NMOS device100. AlthoughFIG. 1, depicts a single MOS multi-finger layout, it is understood by those skilled in the art that a cascoded MOS multi-finger layout comprises two gates having an additional N+ region disposed therebetween, where the P+ substrate tie regions120are interspersed in a similar manner as shown in FIG.1.

FIG. 9depicts a schematic diagram of a sixth embodiment of the multi-finger NMOS device and ESD protection circuit of FIG.3. The schematic diagram is the same as shown and described with regard toFIG. 7, except for the notable distinctions discussed below.

The I/O pad20is capable of outputting signals to other circuitry from the IC10, as well as receiving input signals from other circuitry (not shown) to the IC10. When the I/O pad20receives an input signal, the signal may be higher that the supply line VDD90, such that an over-voltage condition exists between the pad20.and supply line VDD90. If an over-voltage condition arises, then precautions must be taken to prevent malfunctioning of the output circuit, such as sinking of the input signal into to the VDD line. Where there is no PMOS drive700present, then one solution is provided as discussed above with regard to FIG.7.

Where the PMOS driver700is utilized for functional aspects of the IC10, then an N-well bias generator (well-pump)338is also included to avoid sinking of the over-voltage signal from the pad20into the supply line VDD90, which is at a lower potential than the pad20. The well-pump338is coupled to the N-well at node336of the PMOS ESD detector311. The well-pump338tracks the voltage potential at the I/O pad20and senses an over-voltage condition. It is noted that one skilled in the art will understand how to configure the circuitry of the well-pump338.

In particular, the PMOS transistor ESD detector311has a source to N-well diode371formed between the source and N-well of the PMOS ESD detector transistor311. During normal IC operation, and when the I/O pad20is functioning as a pad for receiving an input signal, an over-voltage condition will forward bias the source-N-well diode and conduct the input signal to the supply line VDD90, rather than to the circuitry of the IC that is supposed to receive such input signal.

To alleviate this problem, the circuitry of the well-pump338senses the voltage applied to the I/O pad, and couples the N-well of the PMOS ESD detector transistor311to the input pad20during an over-voltage condition at the pad20. Conversely, when there is no over-voltage condition during normal circuit operation, the well-pump338couples the N-well of the PMOS ESD detector transistor311to the supply line VDD90.

Another problem may arise where, during an ESD event, the N-well and the gate of the PMOS ESD detector transistor311follow the voltage potential at the pad20too quickly, because of the presence of the well-pump338. The PMOS ESD detector311may not be able to determine if an over-voltage condition or an actual ESD event is occurring at the pad20. As such, the PMOS ESD detector311may properly stay off during normal operation. However, the PMOS ESD detector transistor311may also improperly stay off while sensing an ESD event, when in actuality, a similar over-voltage condition exists at the pad20that is typically larger than under normal operating conditions.

To alleviate this problem, in one embodiment, a voltage-limiting resistor375is coupled at node336of the N-well and to the gate of the PMOS ESD detector311. The voltage-limiting resistor375has a resistance value in the range of 1 to 100 Kohms, and is used to provide gate biasing of the PMOS ESD detector transistor311. That is, during normal IC operation, an over-voltage condition at the pad20produces only a small voltage drop across the voltage-limiting resistor375, and which is below the threshold voltage of the PMOS311, thereby keeping the PMOS ESD detector transistor311off.

In particular, during an ESD event at the pad20when the IC10is non-powered, the gate must be lower than the source of the PMOS transistor311in order for the PMOS transistor311to turn on. However, the well-pump338will sense the ESD event at the pad20as an over-voltage condition, and will attempt to couple the N-well and the gate of the PMOS ESD detector transistor311to the pad20, thereby turning the PMOS ESD detector transistor311off. Turning the PMOS ESD detector transistor311off during an ESD event at the pad20is detrimental to the circuitry of the IC10.

To solve this problem, in one embodiment, the voltage-limiting resistor375between the N-well and gate of the PMOS ESD detector transistor311, limits the current of the well-pump338to the diode chain372. During an ESD event, the over voltage condition is stronger and the current in the resistor375, such that the diode chain372to the VDD line is now highly supported by some portion of the ESD current. As such, a voltage drop is generated across the resistor375, which is above the PMOS threshold voltage, thereby turning on the PMOS detector transistor311.

FIG. 10depicts a schematic diagram of a seventh embodiment of the multi-finger NMOS device and ESD protection circuit of FIG.3.FIG. 10depicts a second embodiment for solving the problem of the well-pump338improperly turning the PMOS ESD detector transistor311off during a non-powered IC condition and ESD event at the pad20. The circuit shown inFIG. 10is the same as shown and described inFIG. 9, except for the notable aspects described below.

In particular, an N-well pull-down loop1400is added to the circuit shown in FIG.9. Although not shown inFIG. 10, a person skilled in the art will recognize that the voltage limiter circuitry330of the ESD protection circuit300may be included in the present embodiment of the invention. The N-well pull-down loop1400comprises two cascoded NMOS transistors1461and1462and the ground resistor800. The first cascoded NMOS transistor1461has the source coupled to ground15and the gate coupled to node316of the voltage limiter circuit330. The drain of the first cascoded NMOS transistor1461is coupled to the source of the second cascoded NMOS transistor1462. The gate is coupled to the drain, and the drain of the second cascoded NMOS transistor1462is coupled to the node336at the PMOS ESD detector transistor311.

In an alternative embodiment, a breakdown device399is provided between the N-well tie377of the PMOS ESD detector transistor311and ground15. The breakdown device399may be provided either in conjunction with or in the alternative to the pull-down loop1400, and may comprise a Zener diode, a regular junction diode, and a grounded gate NMOS device, among others. In particular, the cathode of the breakdown device399is coupled to the N-well tie377of PMOS ESD detector transistor311and the anode is coupled to ground. The breakdown voltage of the breakdown device399is above any supply voltage and signal level, but is below any critical oxide breakdown voltage.

During normal IC operation, the PMOS ESD detector transistor311and N-well pull-down loop1400are off because the gate of the first transistor1461is pulled low via the resistor800. The breakdown device399is not conducting any current besides its intrinsic leakage current. The PMOS ESD detector transistor311, as well as the N-well pull-down loop1400do not contribute to the normal circuit operation, except during an over-voltage condition as discussed with regard to FIG.7.

During a non-powered IC state and ESD event at the pad20, both the PMOS ESD detector transistor311and N-well pull-down loop1400must be considered. In particular, once the PMOS ESD detector transistor311turns on, the voltage potential at node316increases, thereby turning on the first cascoded NMOS transistor1461. The second cascoded NMOS transistor1462is normally on, since the gate is coupled to the higher potential at the drain. The purpose of the second NMOS transistor1462is to comply with the maximum voltage limitation across a gate oxide.

The N-well of the PMOS ESD detector transistor311(i.e., node336) is pulled low via the N-well pull-down loop1400, and the output current of the well pump338is largely shunted to ground. Consequently, a voltage drop across the source-Nwell diode371is generated, while a voltage drop across the resistor375is prevented. As such, the gate of the PMOS ESD detector transistor311is held below the source and will turn on the PMOS ESD detector transistor311even stronger to allow more current to flow. The pull down loop1400enhances this effect by positive feedback and maintains the PMOS ESD detector transistor311in an on state. As such, the N-well pull-down loop1400counteracts the tendencies of the well-pump338to couple the gate and the N-well of the PMOS ESD detector transistor311to the pad20, which would thereby keep the PMOS ESD detector transistor311in an off state.

If the alternative breakdown device399is used, the current flowing during an ESD event through the device399prevents again the potential of the N-well to follow the voltage at the pad20and keeps the N-well voltage below the pad voltage. Like the pull-down loop1400, the breakdown device399counteracts the tendencies of the well-pump338.

In contrast to the pull-down loop1400, the breakdown device399does not need an initial slight conduction in the PMOS detector311to become active. As such, the breakdown device399is able, during an ESD event, to keep the N-well and the gate of the PMOS detector311below the pad voltage, and thereby turns the PMOS detector on. This means that the diode chain372is no longer needed and the resistor375, between well-pump338and the gate of PMOS detector, can be replaced by a short. The important advantage for circuit applications is that the ESD protection circuit150is now compliant with the so-called Fail-Safe requirement. In particular, the supply lines VDD90and VDDX91can be hard-grounded during normal circuit operation, while the voltage at the pad20can still be above the regular VDD level, and no malfunction occurs.

The embodiments shown and described above with regard toFIGS. 1-10provide various techniques to simultaneously turn on multiple fingers of an NMOS transistor device, which is used as an output driver and/or ESD protection device. The circuits used to describe the invention are defined as blocks or “modules”, as shown inFIG. 3, to provide better understanding of the invention. One skilled in the art will recognize that alternate embodiments of the circuits in each of the blocks ofFIG. 3are also possible.

In the case where a library I/O cell has unused driver fingers, typically a second set of components including a second pre-driver control500, transfer circuit320, and voltage limiter310are further required. The second set of components is necessary to ensure that during an ESD event at the pad20, all the driver gates of the NMOS device100are biased together, rather than having the gates of the unused driver fingers held at ground, such that the unused driver fingers have difficulties to trigger and are prone to not contribute to the ESD protection.

FIGS. 11 and 12Athrough12D below provides additional embodiments for various portions (i.e., blocks) of the invention. The additional embodiments illustratively include noteworthy complementary components that are useful for a library I/O cells.

FIG. 11depicts a schematic diagram of a dummy ESD pre-driver601and pre-driver control501coupled to the NMOS device100and ESD control circuit300of FIG.3. In particular, a dummy pre-driver601is shown as an inverting circuit, having the output line41(see alsoFIG. 3) coupled to the dummy ESD fingers151of the NMOS device100. The NMOS transistor501of the pre-driver control500is coupled with the drain to the input line61of the dummy pre-driver601and with the source to ground15. The gate of the pre-driver control NMOS transistor501is coupled to the ESD detector310to switch the pre-driver control NMOS transistor501on and off, as discussed above with regard toFIG. 5. Apull-up device503, such as a resistor, is coupled to a voltage potential above ground15, (e.g., supply lines VDD90or VDDx91) and the input line61of the dummy pre-driver601.

The dummy pre-driver601and pre-driver control circuitry501and503similarly provide gate biasing to the dummy fingers151of the multi-finger NMOS transistor device100, as discussed with regard to the pre-driver600and pre-driver control500of FIG.5. That is, the dummy pre-driver601is used for the dummy driver fingers151in split function drivers, and is designed to make the regular pre-driver600match the biasing requirements for the active driver fingers153of the NMOS transistor device100.

FIGS. 12A through 12Ddepict schematic diagrams of various embodiments of the dummy ESD pre-driver601, pre-driver600, and pre-driver control500of FIG.3.FIG. 12Ais a schematic diagram utilized in conjunction with the dummy ESD pre-driver601of FIG.11. The dummy ESD driver601is formed by an inverter circuit comprising serially coupled PMOS and NMOS transistors612and614, where the source of the PMOS transistor612is coupled to a supply line (e.g., VDDx91) and the drain of the PMOS transistor612is coupled to the drain of the NMOS transistor614forming the output of the inverter. The gates of transistors612and614are coupled together forming the input of the inverter and coupled to the supply line VDDx91via a pull-up device616, such as a resistor.

The pre-driver control501comprises NMOS transistors513and514, PMOS transistor516, and a pull-up device515. The NMOS transistor514is coupled from the source of the NMOS transistor614of the pre-driver601to ground15. PMOS transistor516is coupled from the supply line VDDx91to the drains of the inverter transistors612and614, as well as to the gates of the dummy ESD fingers151of the NMOS transistor device100via line41. The gate of the PMOS transistor516is also coupled to the supply line VDDx91via pull-up device (e.g. a resistor)515. NMOS transistor513is coupled from the pull-up device515and the gate of NMOS transistor514to ground15. The gate of the NMOS transistor513is biased by ESD detector310via line30.

Referring toFIG. 12B, it is noted that the configuration is the same as shown inFIG. 12A, except that the inverter pre-driver600is alternately coupled to the gates of the active fingers153of the multi-finger NMOS transistor device100via line40and that the input60of the inverter pre-driver receives a signal from some pre-driver logic. For either embodiment inFIGS. 12A and 12B, during an ESD event, transistor513is turned on by the PMOS ESD detector310, which pulls the gates of transistors514and.516low. The PMOS transistor516is turned on, thereby coupling the lines40and/or41to supply line VDDx91, which biases the gates of the unused passive fingers151(dummy ESD fingers) and the gates of the active fingers153of the NMOS device100. Furthermore, the transistor514is turned off, thereby preventing the inverter device601from pulling either lines40or41low, which would act in opposition to the gate biasing transistor516.

FIG. 12Cillustrates alternate dummy pre-driver601and pre-driver control501circuits, which may be used with the multi-finger NMOS device100. In particular, the dummy ESD driver601is formed by an inverter circuit comprising serially coupled PMOS and NMOS transistors612and614, where the source of the NMOS transistor614is coupled to ground15and the drains of the NMOS and PMOS transistors614and612are serially coupled.

The pre-driver control501comprises a PMOS transistor531serially coupled to the source of the PMOS transistor612of the inverter601, and the supply line VDDx91. The gates of the pre-driver transistors612and614are coupled to a pull-down NMOS transistor532, which is further coupled to ground15. The gates of the pre-driver transistors612and614are also coupled to a pull-up device515(e.g., resistor), which is coupled to the supply line VDDx91. The ESD detector310is coupled to the gates of the pre-driver control transistors531and532to control the turn-on of the pre-driver601. The output of the dummy pre-driver601is connected to the gates of the dummy ESD fingers151of the multi-finger NMOS transistor100.

Referring toFIG. 12D, the configuration is the same as shown inFIG.12C, except that the output of the inverter pre-driver600is alternately coupled to the gates of the active fingers153of the multi-finger NMOS transistor device100and that the input60of the inverter pre-driver receives a signal from some pre-driver logic. For either embodiment inFIGS. 12C and 12D, during an ESD event, transistor531is turned off and transistor532is turned on. The inputs of the inverters601and600are pulled low to ground15. NMOS transistor614is turned off and PMOS transistor612is turned on. As such, the entire structure enters into a tri-state high impedance condition at lines40or41, thereby preventing the pre-driver601(or600) from influencing the effects of the transfer circuit320.

It is further noted that the pre-driver600and dummy pre-driver601configurations (as shown inFIGS. 12A-12B) depending on their power supply and pre-logic connections may also act as transfer circuits320. That is, because they also transfer some of the ESD voltage to the gate of the NMOS transistor100. One difference with respect to the regular ESD transfer circuit320ofFIGS. 4-10is that the ESD voltage does not come via the ESD detector310. Rather, the ESD voltage is provided via the charged VDD line and the pre-driver600or dummy pre-driver601. As such, the pre-driver600or dummy pre-driver601are supportive to the ESD biasing of the ESD detector310and transfer circuit320. If the existing pre-drivers600and601configurations cannot be guaranteed to act as the transfer circuit to properly bias the output driver100, for ESD purposes, the pre-driver control500should be added to achieve the desired effect to force the pre-drivers600and601to provide a bias during ESD. Alternately, a different pre-driver control500may be used to prevent the pre-driver from influencing the function of the transfer circuit320, as discussed above forFIGS. 12C-12Dwith regard to FIG.5.

It is also noted that the pre-drivers600and dummy pre-drivers601are utilized to provide biasing conditions that are symmetrical as possible, as between the active and the dummy transistor parts, for most uniform turn-on of the NMOS transistor100. Such symmetrical conditions are best achieved if both the pre-driver600and dummy pre-driver601either provide the supportive bias from the supply line VDDx91(FIGS.12A and12B), or if they are both turned off during the ESD event (FIGS.12C and12D).

FIG. 13depicts a schematic diagram of a silicon controlled rectifier (SCR) and PMOS ESD detector310of the present invention. The circuit comprises an SCR1300, an ESD detector310, a grounding resistor800, and a parasitic capacitor CDD900. In particular, the SCR1300is utilized to shunt ESD current from the I/O pad20to ground15, rather than the multi-finger NMOS transistor device100ofFIGS. 1-12. As is well known by persons in the art, an SCR1300may be represented by a PNP transistor1301and an NPN transistor1302. The emitter of the PNP transistor1301is coupled to the pad20and the emitter of the NPN transistor1302is coupled to ground. Although only a single SCR1300is illustratively, shown, one skilled in the art will understand that the single SCR1300may alternately comprise multiple SCR fingers. For a detailed understanding of the manufacture and operation of an SCR ESD protection device, the reader is directed to U.S. patent application Ser. No. 10/007,833, filed Nov. 5, 2001, by common assignee Sarnoff Corporation of Princeton, N.J., which is incorporated by reference herein, in it's entirety.

The configuration of the circuit ofFIG. 13is similar to that described with regard to FIG.4. In particular, the ESD detector310comprises a PMOS transistor311having the source coupled to the pad20and to the emitter of the PNP transistor1301of the SCR1300. The gate of the PMOS transistor311is coupled to the supply line VDD60, and the drain of the PMOS transistor311is coupled to ground15, via grounding resistor800. A first gate G11306is coupled to the grounding resistor and drain of the PMOS ESD transistor311at node I304. Specifically, the first gate G11306of each SCR finger is biased via a substrate pump1340, which is fabricated using a plurality of interspersed local substrate ties (trigger taps) coupled together, as illustratively shown with regard to the NMOS device100ofFIG. 1, or as specifically described for an SCR in U.S. patent application Ser. No. 10/007,833 mentioned above.

During an ESD event, when the IC10is in a non-powered state, the PMOS ESD detector311turns on and provides a gate biasing signal to the first gate G11306of the SCR1300in a similar manner as described with regard to the NMOS transistor100of FIGS.4. One advantage of using the SCR1300is that the SCR may be used in conjunction with the NMOS transistor100, such that the SCR1300replaces the passive dummy ESD fingers151of the NMOS transistor100. The SCR1300is a low voltage-clamping device that forms in conjunction with the ESD control circuit300also a low voltage triggering device, and is used only for ESD protection.