SEMICONDUCTOR STRUCTURE INCLUDING DIFFERENT DEVICES AND METHODS FOR MANUFACTURING THE SAME

A semiconductor structure includes a substrate, a first device unit and a second device unit. The substrate includes a first region and a second region. The first device unit is disposed on the first region, and includes a plurality of first channel portions and two first source/drain portions. The second device unit is disposed on the second region, and includes a lower device and an upper device. The lower device is disposed on the second region, and includes at least one lower channel portion and two lower source/drain portions. The upper device is disposed above and spaced apart from the lower device, and includes at least one upper channel portion and two upper source/drain portions. A number of the first channel portions is greater than a number of the at least one lower channel portion and greater than a number of the at least one upper channel portion.

BACKGROUND

Complementary field-effect transistors (CFETs) can be formed by stacking the transistors in a top and bottom manner, so as to achieve a relatively higher transistor density. As such, CFETs are promising candidates in the manufacture of semiconductor devices with improved performance.

DETAILED DESCRIPTION

The term “source/drain portion(s)” may refer to a source or a drain, individually or collectively dependent upon the context.

Critical dimension (CD) of transistors continues to shrink and various three-dimensional (3D) transistor structures (e.g., a gate-all-around field-effect transistor (GAAFET) structure, a forksheet field-effect transistor structure, a complementary field-effect transistor (CFET) structure including stacked transistors, etc.) are developed for manufacturing integrated circuit (IC) with a high integration density, and the CFET structure is a promising candidate in advanced logic IC technology among the 3D transistor structures as mentioned above. This is because, for some logic cells which are designed to have a plurality of devices with different conductivity types, a high integration density can be achieved by stacking an array of top devices on an array of bottom devices which have conductivity type different from that of the top devices. In practice, for some peripheral logic cells (for example, but not limited to, power switch, header switch, footer switch, etc.) which are designed to have a plurality of devices (or unipolar devices) with a single conductivity type, the CFET structure may be less attractive for such peripheral logic cells, because one or more additional photolithography processes may be required to be performed such that the top and bottom devices have the same conductivity type.

Therefore, the present disclosure is directed to a semiconductor structure including a CFET region for forming stacked devices thereon and a unipolar region for forming non-stacked devices (or unipolar devices) thereon, and streamlined approaches for manufacturing the same. The semiconductor structure may be applied to fin-type FETs (FinFETs), multi-gate FETs (e.g., GAAFETs), multi-bridge channel FETs (MBCFETs), fork-sheet FETs, etc.), memory cells, inverters, or other suitable devices or applications. In some embodiments, the semiconductor structure may be exemplified as a semiconductor structure70(seeFIG.24) which includes a first device unit71formed on a first region (e.g., a unipolar region)1, and a second device unit72formed on a second region (e.g., a CFET region)2. The first and second device units71,72formed on the same substrate (e.g., the same wafer) and have different configurations. In some embodiments, the first device unit71has a GAAFET structure and the second device unit72is a CFET structure. The first device unit71includes two first source/drain portions310and first channel portions122B,124,121B at the unipolar region1. The second device unit72includes a lower device721and an upper device722which is separated from the lower device721through isolation features410and a middle isolation portion125. The lower device721includes two lower source/drain portions321and a lower channel portion121B at the CFET region2. The upper device722includes two upper source/drain portions322and an upper channel portion122B at the CFET region2.

FIG.1is a flow diagram illustrating a method10for manufacturing the semiconductor structure (for example, the semiconductor structure70shown inFIG.24) in accordance with some embodiments.FIGS.2to26illustrate schematic views of intermediate stages of the method10in accordance with some embodiments. Some repeating structures are omitted inFIGS.2to26for the sake of brevity.

Referring toFIG.1and the example illustrated inFIG.2, the method10begins at step S11, where a laminated structure110is formed on a starting substrate100.

In some embodiments, the starting substrate100may be made of elemental semiconductor materials, such as crystalline silicon, diamond, or germanium; compound semiconductor materials, such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide; or alloy semiconductor materials, such as silicon germanium, silicon germanium carbide, gallium arsenide phosphide, or gallium indium phosphide. In addition, the starting substrate100may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate. Other suitable materials for the starting substrate100are within the contemplated scope of the present disclosure. In some embodiments, the starting substrate100includes a first region (e.g., a unipolar region)1and a second region (e.g., a CFET region)2which is displaced from the unipolar region1.FIGS.3to5are each a schematic top view of the structure shown inFIG.2in accordance with different embodiments, in which the unipolar and CFET regions1,2of the starting substrate100are shown and other elements are omitted. In some embodiments, the unipolar and CFET regions1,2are displaced from each other in an X direction and/or a Y direction which is transverse to the X direction. In the following embodiments exemplified byFIGS.6to26, the first device unit71at the unipolar region1and the second device unit72at the CFET region2are formed on a single fin structure using the method10, whilst in some other embodiments not shown, the first device unit71at the unipolar region1and the second device unit72at the CFET region2may be formed on different fin structures using the method10.

In some embodiments, the laminated structure110is formed to cover the unipolar and CFET regions1,2of the starting substrate100. The laminated structure110includes a first set of layers120and a second set of layers130. The first set of layers120include at least one lower channel layer121, at least one upper channel layer122, and a preformed layer123which is disposed between and spaced apart from the at least one lower channel layer121and the at least one upper channel layer122. The second set of layers130include at least three sacrificial layers131, and are disposed to alternate with the first set of layers120(i.e., the layers121,122,123) in a Z direction which is transverse to both the X and Y directions. A bottommost one of the at least three sacrificial layers131is disposed on the starting substrate100. In some embodiments, the X, Y and Z directions are perpendicular to one another. As shown inFIG.2, each of a number (N1) of the at least one lower channel layer121and a number (N2) of the at least one upper channel layer122is one, and a number (N3) of the at least three sacrificial layers131is three. The number (N3) may vary according to the numbers (N2, N3) (i.e., a sum number (N1+N2+1) of the layers121,122,123in the first set of layers120is equal to the number (N3) of the layers131in the second set of layers130). It is noted that each of the numbers (N1. N2, N3) is not limited to the number shown in the drawings, and may vary according to practical applications. For example, in some not shown embodiments, each of the numbers (N1, N2) may be designed to be two, three or four, independently.

In some embodiments, the laminated structure110is a stack of semiconductor materials. Semiconductor materials suitable for forming the layers121,122,123,131are similar to those for the starting substrate100, and thus details thereof are omitted for the sake of brevity. In some embodiments, the laminated structure110may be formed on the starting substrate100by chemical vapor deposition (CVD), atomic layer deposition (ALD), an epitaxial growth process (such as molecular-beam epitaxy (MBE), selective area epitaxy (SEG), etc.), or other suitable deposition techniques.

In some embodiments, the lower and upper channel layers121,122are made of a first semiconductor material, the sacrificial layers131are made of a second semiconductor material, and the preformed layer123is made of a third semiconductor material. It is noted that the first, second and third semiconductor materials have different chemical compositions from one another, and thus the first, second and third semiconductor materials have different etching selectivity ratios from one another. Thus, by selecting a suitable etchant, any one of the third semiconductor material of the preformed layer123and the second semiconductor material of the sacrificial layers131can be selectively removed with respect to the semiconductor materials of the other layers in subsequent processes. In some embodiments, the lower channel layer121may be made of a semiconductor material the same as or different from that of the upper channel layer122, and hence the transport behavior of major carriers (i.e., holes or electrons) therein may be further adjusted. In some embodiments, each of the semiconductor materials of the lower and upper channel layers121,122may be the same as or different from that of the starting substrate100.

In certain embodiments, each of the starting substrate100and the lower and upper channel layers121,122is made of silicon. Each of the preformed layer123and the sacrificial layers131is made of silicon germanium, while the preformed layer123has an atomic percentage of germanium different from (e.g., greater than) an atomic percentage of germanium in each of the sacrificial layers131. In some embodiments, the atomic percentage of germanium in each of the sacrificial layers131ranges from about 10% to about 30%. In some embodiments, the atomic percentage of germanium in the preformed layer123ranges from about 20% to about 60%. Other materials and combinations thereof suitable for the laminated structure110are within the contemplated scope of the present disclosure.

In some embodiments, the lower and upper channel layers121,122may have the same or different thicknesses in the Z direction. In some embodiments, the sacrificial layers131may have the same as or different thicknesses in the Z direction. In some embodiments, as shown inFIG.2, a thickness of the preformed layer123is substantially equal to that of at least one of the lower and upper channel layers121,122. In some embodiments, the thickness of each of the lower and upper channel layers121,122may range from about 3 nm to about 8 nm. In some embodiments, the thickness of each of the sacrificial layers131may range from about 5 nm to about 23 nm. In some embodiments, the thickness of the preformed layer123may range from about 3 nm to about 8 nm. It is noted that, in some other embodiments, the thickness of the preformed layer123may be greater than that of each of the lower and upper channel layers121,122, and will be detailed described inFIGS.27to46.

Referring toFIG.1and the examples illustrated inFIGS.8and9, the method10proceeds to step S12, where a patterned structure60is formed from the structure shown inFIG.2.FIG.8is a schematic cross-sectional view of the patterned structure60taken in the X direction in accordance with some embodiments.FIG.9is a schematic cross-sectional view of the patterned structure60taken along line A1-A1′ or line A2-A2′ ofFIG.8in accordance with some embodiments. It is noted that, in some embodiments,FIG.9may present the patterned structure60at the unipolar region1or the CFET region2since the patterned structure60at the unipolar and CFET regions1,2may have substantially the same cross-section in the Y direction.

The patterned structure60is formed from patterning the laminated structure110and the starting substrate100shown inFIG.2, and includes a semiconductor substrate103, at least one first fin portion101, at least one second fin portion102, at least one first stack unit111B, and at least one second stack unit112B.

After step S12, the stating substrate100is patterned into the semiconductor substrate103and the first and second fin portions101,102. The semiconductor substrate103includes a unipolar region1and a CFET region2which are respectively corresponding to the unipolar region1and the CFET region2of the starting substrate100, and which are thus respectively denoted by the same numerals for the sake of brevity. The first and second fin portions101,102are respectively formed on the unipolar region1and the CFET region2. In some embodiments, as exemplified byFIG.8, the first and second fin portions101,102may be formed on a single fin structure and are displaced from each other in the X direction (i.e., the unipolar region1and the CFET region2are displaced from each other in the X direction, see alsoFIG.3or5). In some other embodiments not shown, the first and second fin portions101,102are formed at two different fin structures and are spaced apart from each other in the Y direction (i.e., the unipolar and CFET regions1,2are displaced from each other in the Y direction, seeFIG.4), In this case, the first fin portion101in one of the fin structures may be formed over the unipolar region1, and the second fin portion102in the other one of the fin structures may be formed over the CFET region2.

After step S12, the laminated structure110is patterned into the at least one first stack unit111B and the at least one second stack unit112B are respectively disposed on the first and second fin portions101,102. In some embodiments, as shown inFIGS.8and9, three of the first stack units111B are displaced from each other in the X direction and disposed on the first fin portion101at the unipolar region1, and three of the second stack units112B are displaced from each other in the X direction and disposed on the second fin portion102at the CFET region2. It is noted that the number of each of the elements101,102,111B,112B is not limited to the number shown in the drawings, and may vary according to practical applications. In the following, for the sake of brevity, each of the elements101,102,111B,112B is described in a singular form, the first stack unit111B refers to a middle one of those shown inFIG.8, and the second stack unit112B refers to a middle one of those shown inFIG.8.

Each of the first and second stack units111B,112B includes a first set of portions120B and a second set of portions130B. The first set of portions120B include a lower channel portion121B, an upper channel portion122B and a preformed portion123B which are respectively patterned from the lower channel layer121, the upper channel layer122and the preformed layer123. The preformed portion123B is disposed between and spaced apart from the lower and upper channel portions121B,122B. The second set of portions130B include three of sacrificial portions131B which are respectively patterned from the sacrificial layers131. The sacrificial portions131B are disposed to alternative with the first set of portions120B (i.e., the portions121B,122B,123B). A bottommost one of the sacrificial portions131B is disposed on a corresponding one of the first and second fin portions101,102. In some embodiments, as shown inFIG.9, the lower and upper channel portions121B,122B in the first stack unit111B has a first width (W1) in the Y direction, and the lower and upper channel portions121B,122B in the second stack unit111B has a second width (W2) in the Y direction. The first width (W1) may be the same as or different from the second width (W2). In some embodiments, each of the first width (W1) and the second width (W2) may independently range from about 5 nm to about 80 nm.

In some embodiments, the patterned structure60further includes multiple pairs of isolation regions180(a pair of the isolation regions180are shown inFIG.9), a plurality of dummy gate portions190, multiple pairs of dummy gate spacers220, and multiple pairs of source/drain recesses210. In the following, for sake of brevity, the dummy gate portions190refer to a middle one of the dummy gate portions190at the unipolar region1and a middle one of the dummy gate portions190at the CFET region2(seeFIG.8), and the multiple pairs of the dummy gate spacers220refer to a middle pair of the dummy gate spacers220at the unipolar region1and a middle pair of the dummy gate spacers220at the CFET region2.

The isolation regions180are disposed at two opposite sides of a corresponding one of the first and second fin portions101,102(seeFIG.9). In some embodiments, the isolation regions180are provided for isolating the first fin portion101or the second fin portion102from the structure adjacent thereto. The isolation regions180may each be a portion of a shallow trench isolation (STI), a deep trench isolation (DTI), or other suitable structures, and may be made of a dielectric material, such as an oxide material (for example, silicon oxide), a nitride material (for example, silicon nitride), or a combination thereof. Other suitable materials and/or configurations for the isolation regions180are within the contemplated scope of the present disclosure.

In some embodiments, the dummy gate portions190are each elongated in the Y direction, and disposed over the first and second stack unit111B,112B, respectively. In some embodiments, each of the dummy gate portions190may include a dummy gate dielectric layer191, a dummy gate electrode layer192and a hard mask layer193sequentially formed over a corresponding one of the first and second stack units111B,112B in such order. In some embodiments, the hard mask layer193may include silicon nitride, silicon oxide, silicon oxynitride, other suitable dielectric materials, or combinations thereof, the dummy gate electrode layer192may include polycrystalline silicon, single crystalline silicon, amorphous silicon, or combinations thereof, and the dummy gate dielectric layer191may include silicon oxide, silicon nitride, silicon oxynitride, high dielectric constant (k) materials, other suitable dielectric materials, or combinations thereof. Other suitable materials for the dummy gate portions190are within the contemplated scope of the present disclosure. In some embodiments, each of the dummy gate portions190is further formed over the corresponding isolation regions180.

Each pair of the gate spacers220are respectively formed at two opposite sides of a corresponding one of the dummy gate portions190in the X direction. In some embodiments, the gate spacers220may be made of a dielectric material. The dielectric material for forming the gate spacers220may include a nitride-based material, such as silicon nitride, silicon oxynitride, silicon carbon nitride, silicon oxycarbonnitride, but is not limited thereto. Other materials suitable for forming the gate spacers220are within the contemplated scope of the present disclosure.

Each pair of the source/drain recesses210are disposed at two opposite sides of a corresponding one of the first and second stack units111B,112B (or a corresponding one of the dummy gate portions190) in the X direction, such that two opposite end surfaces of the corresponding one of the first and second stack units111B,112B are exposed therefrom. In some embodiments, each of the source/drain recesses210may extend into an upper part of a corresponding one of the first and second fin portions101,102.

FIGS.6and7are views respectively similar to those ofFIGS.8and9, but illustrating the structures in an intermediate stage of step S12. In some embodiments, step S12for forming the patterned structure60shown inFIGS.8and9may be formed by following sub-steps (i) to (v). In sub-step (i) of step S12, the starting substrate100is patterned into the semiconductor substrate103and the first and second fin portions101,102, and the laminated structure110is patterned into a first stack portion111A and a second stack portion112A (seeFIGS.6and7) respectively disposed on the first and second fin portions101,102, Each of the first and second stack portions111A,112A includes a first set of films120A which are patterned from the first set of layers120and a second set of films130A which are patterned from the second set of layers130, and which are disposed to alternate with the first set of films120A. In sub-step (ii) of step S12, the isolation regions180are formed respectively at the two opposite sides of the corresponding one of the first and second fin portions101,102(seeFIG.7). In sub-step (iii) of step S12, the dummy gate portions190are respectively over the first and second stack portions111A,112A (seeFIG.6). In sub-step (iv) of step S12, each pair of the dummy gate spacers220are respectively formed at the two opposite sides of the corresponding one of the dummy gate portions190(seeFIG.8). In sub-step (v) of step S12, the first and second stack portions111A,112A are patterned to form the source/drain recesses210(seeFIG.8) such that the first and second stack portions111A,112A (seeFIG.6) are respectively formed into the first and second stack units111B.112B and such that each pair of the source/drain recesses210are respectively disposed at the two opposite sides of the corresponding one of the first and second stack units111B,112B. That is, the first and second stack units111B,112B may be patterned from the laminated structure110through two of the patterning processes (i.e., sub-steps (i) and (v) of step S12) in accordance with some embodiments as described above, but is not limited thereto. Other suitable process flows for forming the patterned structure60are within the contemplated scope of the present disclosure.

Referring toFIG.1and the examples illustrated inFIG.18, the method10proceeds to step S13, where the preformed portions123B in the first and second stack units111B,112B (seeFIG.8) are respectively replaced with a middle channel portion124and a middle isolation portion125.FIG.18is a view subsequent toFIG.8for illustrating the structure after step S13.

In some embodiments, step S13may include sub-steps (i) to (iv), where the replacement process of the preformed portion123B in the first stack unit111B is performed after the replacement process of the preformed portion123B in the second stack unit112B. In some alternative embodiments, the replacement process of the preformed portion123B in the first stack unit111B may be performed before the replacement process of the preformed portion123B in the second stack unit112B.

FIG.10is a view subsequent toFIG.8for illustrating the structure after sub-step (i) of S13.FIGS.11and12are views subsequent toFIG.9and respectively illustrate the structures at the unipolar region1and the CFET region2after sub-step (i) of S13. In sub-step (i) of step S13, a patterned mask91(seeFIGS.10and11) is formed to cover the structure at the unipolar region1obtained after step S12using CVD, ALD, or other suitable deposition techniques, followed by a photolithography process, and then the preformed portion123B in the second stack unit112B (seeFIGS.8and9) is removed to form a first gap200(seeFIGS.10and12) by a selective etching process with the use of etchant(s) having high etching selectivity to the preformed portion123B and thus the other layers121B,122B,131B in the second stack unit112B are substantially intact. In some embodiments, the selective etching process may include dry etching, wet etching, other suitable etching techniques, or combinations thereof. In some embodiments, the etchant(s) may be gas-phase, liquid-phase, or other suitable states.

In some embodiments, the patterned mask91may include an oxide, a nitride, a carbide, an oxynitride, an oxycarbide, a carbonitride, an oxycarbonitride, or combinations thereof. In some embodiments, the patterned mask91may be made of silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, titanium nitride, but is not limited thereto. Other dielectric materials suitable for forming the patterned mask91are within the contemplated scope of the present disclosure. In some embodiments, the dielectric material(s) of the patterned mask91may be different from the dielectric material(s) of the elements193,220, and may be different from dielectric material(s) of the middle isolation portion125to be formed subsequently.

FIGS.13and14are views respectively subsequent toFIGS.10and12for illustrating the structure after sub-step (ii) of S13. In sub-step (ii) of step S13, the middle isolation portion125is formed in the first gap200(seeFIGS.10and12), and then the patterned mask91(seeFIGS.10and11) is removed.

In some embodiments, the middle isolation portion125may include dielectric material(s), such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride, silicon oxycarbonitride, silicon oxycarbide, silicon carbide, aluminum oxide, hafnium oxide, zirconium oxide, or combinations thereof. In some embodiments, the middle isolation portion125may be formed as a single layer structure, a bi-layered structure or a multi-layered structure. Other dielectric materials and configurations suitable for the middle isolation portion125are within the contemplated scope of the present disclosure. In some embodiments, sub-step (ii) of S13may include (a) depositing the dielectric material(s) (not shown) for forming the middle isolation portion125on the structures obtained after sub-step (i) of S13(seeFIGS.10to12) to fill the first gap200by CVD, ALD, or other suitable deposition techniques, (b) removing excess portions of the dielectric material(s) for forming the middle isolation portion125by a suitable etching process, so as to form the middle isolation portion125in the first gap200(seeFIGS.13and14), and (c) removing the patterned mask91(seeFIGS.10and11) by a suitable etching process.

FIGS.15,16and17are views respectively subsequent toFIGS.13,11and14for illustrating the structures after sub-step (iii) of step S13. In sub-step (iii) of step S13, as shown inFIGS.15and17, a patterned mask92is formed to cover the previous obtained structure at the CFET region2(seeFIGS.15and17), and then the preformed portion123B in the first stack unit111B (seeFIG.13) is removed to form a second gap230(seeFIGS.15and16).

In some embodiments, the suitable materials and processes for forming the patterned mask92are similar to those for the patterned mask91, and thus details thereof are omitted for the sake of brevity. In addition, since processes for forming the second gap230are similar to those for forming the first gap200, details thereof are omitted for the sake of brevity.

FIGS.18and19are views respectively subsequent toFIGS.15and16for illustrating the structures after sub-step (iv) of step S13. In sub-step (iv) of step S13, the middle channel portion124(seeFIGS.18and19) is formed in the second gap230(seeFIGS.15and16), and then the patterned mask92(seeFIGS.15and17) is removed.

In some embodiments, the middle channel portion124(seeFIGS.18and19) may be made of a semiconductor material the same as that of each of the lower and upper channel portions121B,122B in the first stack unit111B (seeFIG.13). In some embodiments, sub-step (iv) of step S13may include (a) epitaxial growing the semiconductor material for forming the middle channel portion124on the structure obtained after sub-step (iii) of step S13(seeFIGS.15to17) to fill the second gap230by an epitaxial growth process including CVD, MBE, an epitaxial deposition/partial etch process, such as a cyclic deposition-etch (CDE) process and/or a SEG process, or other suitable deposition techniques, (b) removing excess portions of the semiconductor material for forming the middle channel portion124in the source/drain recesses210by a suitable etching process so as to form the middle channel portion124in the second gap230, and (c) removing the patterned mask92(seeFIGS.15and17) by a suitable etching process. In some embodiments, as shown inFIG.19, the middle channel portion124has a third width (W3) in the Y direction which may be the same as or slightly different from the first width (W1, seeFIG.9). In some embodiments, the third width (W3) may range from about 5 nm to about 80 nm. In some embodiments, a thickness of the middle channel portion124in the Z direction is mainly affected by a gap size of the second gap230(seeFIGS.15and16) in the Z direction, so the thickness of the middle channel portion124may the same as or slightly different from the thickness of the preformed layer123(seeFIG.2). In some embodiments, the thickness of the middle channel portion124may the same as or different from the thickness of each of the lower and upper channel layers121,122(seeFIG.2).

After step S13, the preformed portion123B of the first stack unit111B (seeFIGS.8and9) is replaced with the middle channel portion124to obtain a first stack unit111C (seeFIGS.18and19), and the preformed portion123B of the second stack unit112B (seeFIGS.8and9) is replaced with the middle isolation portion125to obtain a second stack unit112C (seeFIGS.14and18). After step S13, the structures taken in the Y direction at the unipolar region1and the CFET region2may be presented byFIGS.19and14, respectively.

Referring toFIG.1and the example illustrated inFIG.23, the method10proceeds to step S14, where a plurality pairs of inner spacers240, two first source/drain portions310, two lower source/drain portions321and two upper source/drain portions322are formed. After step S14, the first device unit71and the second device unit72are obtained.FIG.23is a view subsequent toFIG.18for illustrating the structure after step S14. In some embodiments, step S14include sub-steps (i) to (vi).

In sub-step (i) of step S14, the pairs of the inner spacers240are formed by (a) recessing two opposite ends of the sacrificial portions131B in the first and second stack unit111C,112C (seeFIG.18) through the source/drain recesses210to form lateral recesses (not shown) by a suitable etching process (e.g., an isotropic etching process), and (b) forming the inner spacers240(seeFIG.20) respectively in the lateral recesses in a manner similar to that for forming the middle isolation portion125as describe in sub-step (ii) of step S13. In some embodiments, the inner spacers240may include a low-k dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, silicon carbide, and so on. Other low-k dielectric materials suitable for the inner spacers240are within the contemplated scope of the present disclosure.

After sub-step (i) of step S14, the first and second stack units111C and112C shown inFIG.18are respectively formed into first and second stack units111D and112D (seeFIG.20). In addition, the recessed sacrificial portions in each of the first and second stack units111D,112D are denoted by131C.

FIG.21is a view subsequent toFIG.18for illustrating the structure after sub-step (ii) of step S14. In sub-step (ii) of step S14, blocking films94A are formed to at least cover the end surfaces of the upper channel portions122B in the second stack unit112D, while the end surfaces of the lower channel portion121B in the second stack unit112D and the end surfaces of the lower, middle and upper channel portions121B,124,122B in the first stack unit111D are accessible through the source/drain recesses210.

In some embodiments, the blocking films94A may be formed by (a) forming a plurality of dielectric portions93respectively in the source/drain recesses210at the unipolar and CFET regions1,2(seeFIG.20) using CVD, ALD or other suitable processes, followed by a suitable etching back process, such that the dielectric portions93cover the end surfaces of the lower channel portions121B in the first and second stack units111D,112D. (b) conformally forming a blocking layer94(seeFIG.20) using CVD, ALD or other suitable processes, (c) performing an anisotropic etching process to form the blocking layer94into the blocking films94A (seeFIG.21) which are respectively and partially formed on inner surfaces of the source/drain recesses210at the CFET region2and additional blocking films (not shown) which are respectively and partially formed on inner surfaces of the source/drain recesses210at the unipolar region1, (d) removing the dielectric portions93(seeFIG.20) by a suitable etching process, (e) covering the blocking layer94at the CFET region2using a protective mask (not shown, which may be a patterned photoresist or other suitable masks), (f) removing the additional blocking films using a suitable etching process through the protective mask, and (g) removing the protective mask.

In some embodiments, the dielectric portions93may be made of a dielectric material, such as the examples of the inner spacers240as described in sub-step (i) of step S14. In some embodiments, the blocking films94A may be made of a dielectric material, such as the examples for the patterned mask91as described with reference toFIGS.10and11. In some embodiments, the dielectric portions93are made of a dielectric material which is different from those of the elements94A,193,220,240, so that the dielectric portions93may be selectively removed relative to the elements94A,193,220,240. Other dielectric materials suitable for the dielectric portions93and the blocking films94A are within the contemplated scope of the present disclosure

In sub-step (iii) of step S14, the first source/drain portions310and the lower source/drain portions321(seeFIG.22) are formed by an epitaxial growth process (such as the examples described in the preceding paragraph) and then the blocking films94A shown inFIG.21are removed. The first source/drain portions310are respectively formed in the source/drain recesses210at the unipolar region1(seeFIGS.21and22) and spaced apart from each other such that each of the lower, middle and upper channel portions121B,124,122B in the first stack unit111D extends between the first source/drain portions310. The lower source/drain portions321are respectively formed in the source/drain recesses210at the CFET region2(seeFIGS.21and22) and spaced apart from each other such that the lower channel portion121B in the second stack unit112D extends between the lower source/drain portions321. The lower source/drain portions321have a conductivity type the same as that of the first source/drain portions310. In some embodiments, each of the first source/drain portions310may be doped with n-type impurities or p-type impurities, and may be formed as a single layer structure or a multi-layered structure having several sub-layers with different doping concentration. In some embodiments, the first source/drain portions310have a p-type conductivity, and include single crystalline or polycrystalline silicon, single crystalline or polycrystalline silicon germanium, or other suitable materials doped with p-type impurities so as to function as a source/drain of a p-FET. The p-type impurities may be, for example, but not limited to, boron (B), aluminum (Al), gallium (Ga), indium (In), other suitable materials, or combinations thereof. In some embodiments, the first source/drain portions310have an n-type conductivity, and include single crystalline silicon, polycrystalline silicon or other suitable materials doped with n-type impurities so as to function as a source/drain of an n-FET. The n-type impurities may be, for example, but not limited to, nitrogen (N), phosphorous (P), arsenic (As), antimony (Sb), other suitable materials, or combinations thereof. In some embodiments, carbon (C) may be selected to be doped in the first source/drain portions310. The impurities in the first source/drain portions310and the lower source/drain portions321may be in-situ doped during the epitaxial growth process for forming the same, or post doped after the epitaxial growth process for forming the same.

In sub-step (iv) of step S14, first isolation features410are formed to respectively cover the lower source/drain portions321(seeFIG.22). In some embodiments, the first isolation features410is configured as a bi-layered structure, and includes a first dielectric layer401and a second dielectric layer402formed on the first dielectric layer401. In some embodiments, sub-step (iv) of step S14includes (a) sequentially depositing first material layers401A,402A respectively for forming the first and second dielectric layers401,402on the previously obtained structure to fill the remaining source/drain recesses210using CVD, ALD or other suitable processes, (b) performing a planarization process, for example, but not limited to, chemical mechanical polishing (CMP) to partially expose the first material layer402A, and (c) forming a patterned mask (which may be a patterned photoresist and/or a patterned hard mask)95which covers a first part of the first material layers401A,402A at the unipolar region1, (d) etching back a second part of the first material layers401A,402A at the CFET region2through the patterned mask95using a suitable etching process so as to form the second part of the first material layers401A,402A at the CFET region2into the first isolation features410respectively on the lower source/drain portions321. After sub-step (iv) of step S14, the first part of the first material layers401A,402A remains at the unipolar region1. As shown inFIG.22, the end surfaces of the upper channel portions122B in the second stack unit112D are exposed from the first isolation features410. In some embodiments, the first dielectric layer401may include silicon nitride, carbon-doped silicon nitride, other suitable materials, or combinations thereof. In some embodiments, the second dielectric layer402may include a low-k dielectric material (such as the examples described in the preceding paragraph) which is different from that of the first dielectric layer401. Other suitable materials and/or configurations for the first isolation features410are within the contemplated scope of the present disclosure.

After sub-step (iv) of step14, the patterned mask95may be removed, and the remaining source/drain recesses at the CFET region2are denoted by210A.

In sub-step (v) of step S14, the upper source/drain portions322(seeFIG.23) are respectively formed in the source/drain recesses210A (seeFIG.22) by an epitaxial growth process (such as the examples described in the preceding paragraph). Since suitable materials for the upper source/drain portions322are similar to those for the first source/drain portions310, details thereof are omitted for the sake of brevity. As shown inFIG.23, the upper source/drain portions322are respectively formed above and spaced apart from the lower source/drain portions321by the first isolation features410, and the upper channel portion122B in the second stack unit112D extends between the upper source/drain portions322. The upper source/drain portions322may have a conductivity type which is the same as or different from that of the lower source/drain portions321. In the case that the second device unit72has a CFET structure, the upper source/drain portions322have a conductivity type opposite to that of the lower source/drain portions321. For example, the lower source/drain portions321have a p-type conductivity, while the upper source/drain portions322have an n-type conductivity, and vice versa. The impurities in the upper source/drain portions322may be in-situ doped during the epitaxial growth process for forming the same, or post doped after the epitaxial growth process for forming the same. As shown inFIG.23, each of the first isolation features410is formed to separate one of the lower source/drain portions321from a corresponding one of the upper source/drain portions322.

In sub-step (vi) of step S14, as shown inFIG.23, second isolation features420are formed to respectively cover the upper source/drain portions322, and third isolation features430are formed to respectively cover the first source/drain portions310. Each of the second and third isolation features420,430includes a first dielectric layer401and a second dielectric layer402which may be made of materials substantially the same as those of the first isolation features410. In some embodiments, sub-step (vi) of step S14includes (a) sequentially depositing second material layers (not shown) respectively for forming the first and second dielectric layers401,402of the second isolation features420on the previously obtained structure to fill the remaining source/drain recesses (not shown) at the CFET region2using CVD, ALD or other suitable processes, and (b) performing a planarization process, for example, but not limited to, CMP, to expose the dummy gate electrode layers192of the dummy gate portions190on the first and second stack units111D,112D (seeFIG.22). As such, the first part of the first material layers401A,402A at the unipolar region1(seeFIG.22) is formed into the third isolation features430(seeFIG.23) and the second material layers are formed into the second isolation features420. At this stage, the first device unit71is formed at the unipolar region1, and the second device unit72is formed at the CFET region2and includes the lower device721and the upper device722.

After sub-step (vi) of step S14, each of the remaining dummy gate portions on the first and second stack units111D,112D is denoted by190A, and includes the remaining dummy gate electrode layer192A and the dummy gate dielectric layer191. As such, compared to the structure shown inFIGS.19and14(obtained in step S13), after step14, the structure may have a reduced height in the Z direction (i.e., the hard mask layer193and a portion of the dummy gate electrode layer192shown inFIGS.19and14are removed in step S14).

The first device unit71includes the lower, middle and upper channel portions121B,124,122B of the first stack unit111D (hereinafter referred to as first channel portions) which are spaced apart from each other in the Z direction, and the two first source/drain portions310which are spaced apart from each other in the X direction such that each of the first channel portions121B,124,122B extends between the first source/drain portions310.

The lower device721in the second device unit72is disposed at the CFET region2, and includes the lower channel portion121B of the second stack unit112D and the two lower source/drain portions321which are spaced apart from each other in the X direction such that the lower channel portion121B of the second stack unit112D extends between the lower source/drain portions321.

The upper device722is disposed above and spaced apart from the lower device721, and includes the upper channel portion122B of the second stack unit112D and the two upper source/drain portions322which are spaced apart from each other in the X direction such that the upper channel portion122B of the second stack unit112D extends between the upper source/drain portions322.

In some embodiments, as shown inFIG.23, an uppermost one of the first channel portions121B,124,122B in the first device unit71has an upper surface which is substantially flush with an upper surface of the upper channel portion122B of the upper device721.

In some embodiments, as shown inFIG.23, the second device unit72further includes the middle isolation portion125which is disposed between and spaced apart from the lower and upper channel portions121B,122B of the second stack unit112D. In some embodiments, the middle isolation portion125has a length in the X direction which is the same as that of each of the lower and upper channel portions121B,122B of the second stack unit112D. In some embodiments, the middle isolation portion125has a thickness in the Z direction which is substantially the same as that of each of the first channel portions121B,124,122B of the first device unit71, and which is substantially the same as that of each of the lower and upper channel portions121B,122B of the second stack unit112D.

In some embodiments, as shown inFIG.23, the second device unit72further includes the first isolation features410, each of which is disposed between one of the lower source/drain portions321and a corresponding one of the upper source/drain portions322. In some embodiments, the middle isolation portion125extends between the two isolation features410, such that the middle isolation portion125and the first isolation features410together isolate the lower and upper devices721,722.

It is worth noting that a number of the first channel portions121B,124,122B in the first device unit71is greater than a number of the lower channel portion121B in the lower device721and greater than a number of the upper channel portion122B in the upper device722. Therefore, the first device unit71may function to have a higher speed performance with respect to the lower and upper devices721,722. Relatively, the second device unit72, which includes the lower and upper devices721,722stacked on each other, may have a higher device density with respect to the first device unit71. In some embodiments, since the second device unit72has a stack of the devices721,722which have opposite types of conductivity, the second device unit72may be referred to as a CFET structure. In some embodiments, since the first device unit71has a single type of conductivity, the first device unit71may be referred to as a unipolar transistor. Notably, the CFET and the unipolar transistor can be formed on the same wafer by the method of this disclosure.

Referring toFIG.1and the examples illustrated inFIGS.24to26, the method10proceeds to step S15, where a replacement gate process is performed, thereby obtaining the semiconductor structure70.FIGS.24to26are views respectively subsequent toFIGS.23,19and14for illustrating the structures after step S15.

In a first sub-step of step S15, the remaining dummy gate portions190A and the sacrificial portions131C (seeFIG.23) are removed using one or more suitable etching processes to form a first cavity (not shown) at the unipolar region1and a second cavity (not shown) at the CFET region2. The first channel portions121B,124,122B remaining in the first stack unit111D and exposed from the first cavity are together referred to as a first stack11R, and the lower and upper channel portions121B.122B, and the middle isolation portion125remaining in the second stack unit112D and exposed from the second cavity are together referred to as a second stack12R. Afterwards, as shown inFIG.24, in a second sub-step of step S15, materials for forming a first gate dielectric511and a first gate electrode512are sequentially formed in the first cavity using one or more suitable deposition processes (such as CVD, ALD, etc.), and materials for forming a second gate dielectric521and a second gate electrode522are sequentially formed in the second cavity using one or more suitable deposition processes (such as CVD, ALD, etc.), followed by one or more planarization processes (such as, CMP, or other suitable processes) to remove an excess of the above materials, thereby obtain the first and second gate dielectrics511,521and the first and second gate electrodes512,522.

In some embodiments, the first gate dielectric511is disposed around each of the first channel portions121B,124,122B in the first stack11R. The first gate electrode512is disposed on the first gate dielectric511such that each of the first channel portions121B,124,122B is separated from the first gate electrode512by the first gate dielectric511.

The second gate dielectric521is disposed around each of the lower and upper channel portions121B,122B and the middle isolation portion125in the second stack12R. The second gate electrode522is disposed on the second gate dielectric521such that each of the lower and upper channel portions121B,122B and the middle isolation portion125in the second stack12R is separated from the second gate electrode522by the second gate dielectric521.

In some embodiments, each of the first and second gate dielectrics511,521may independently include silicon oxide, silicon nitride, silicon oxynitride, a suitable high-k material (such as hafnium oxide, zirconium oxide, zirconium aluminum oxide, hafnium aluminum oxide, hafnium silicon oxide, aluminum oxide, and so on), other suitable materials, or combinations thereof. Other suitable materials for the first and second gate dielectrics512,522are within the contemplated scope of the present disclosure. In some embodiments, any one of the first and second gate electrodes512,522may be configured as a multi-layered structure including at least one work function metal which is provided for adjusting threshold voltage of an n-FET or an p-FET, an electrically conductive material having a low resistance which is provided for reducing electrical resistance of the one of the first and second gate electrodes512,522, other suitable materials, or combinations thereof. In some embodiments, the work function metal of one of the first and second gate electrodes512,522for forming an n-FET may be different from that for forming a p-FET so as to permit the n-FET and the p-FET to have different threshold voltages. Other suitable methods for adjusting the threshold voltages are within the contemplated scope of the present disclosure. In some embodiments, each of the first and second gate electrodes512,522may independently include a metal material (e.g., tungsten (W), titanium (Ti), tantalum (Ta), aluminum (Al), or ruthenium (Ru)), metal-containing nitrides (e.g., titanium nitride (TiN), or tantalum nitride (TaN)), metal-containing silicides (e.g., nickel silicide (NiSi)), metal-containing carbides (e.g., tantalum carbide (TaC)), or combinations thereof. Other suitable materials for the first and second gate electrodes512,522are within the contemplated scope of the present disclosure.

In some embodiments, some steps in the method10may be modified, replaced, or eliminated without departure from the spirit and scope of the present disclosure. For example, in some embodiments exemplified byFIGS.20to24, the first source/drain portions71are formed together with the lower source/drain portions321to have the same conductivity type as that of the lower source/drain portions321. In other embodiments, the first source/drain portions71are formed together with the upper source/drain portions322to have the same conductivity type as that of the upper source/drain portions322. Furthermore, the semiconductor structure70may further include additional features, and/or some features present in the semiconductor structure70may be modified, replaced, or eliminated without departure from the spirit and scope of the present disclosure.

In some embodiments, as shown inFIG.24, the semiconductor structure70may further include a plurality of interfacial layers524each of which is interposed between one of the channel portions in the first and second stacks11R.12R and a corresponding one of the first and second gate dielectrics511,521.

In some embodiments, as shown inFIG.24, in some embodiments, the semiconductor structure70may further include a plurality of front-side contact features531which are respective formed in the second and third isolation features420,430such that each of the front-side contact features531is coupled to a corresponding one of the first source/drain portions310of the first device unit71and the upper source/drain portions322of the upper device722. In some embodiments, the semiconductor structure70may further include a plurality of metal silicide features534each of which is disposed between one of the contact features531and a corresponding one of the source/drain portions310,322for reducing a contact resistance (Rcsd) therebetween. In some embodiments, the semiconductor structure70may further include a plurality of front-side interconnect layers540each including a plurality of inter-metal dielectric (IMD) features (not shown) in which front-side electrically conductive elements (not shown, for example, metal contacts, metal lines and/or metal vias) are formed so as to permit the first device unit71and/or the upper device722to be electrically connected to external circuits through the front-side electrically conductive elements. In some embodiments, each of the interconnect layers540may be formed by a dual damascene process, a single damascene process, or other suitable back-end-of-line (BEOL) techniques.

In the method10, since the middle channel portion124and the middle isolation portion125(seeFIG.24) are respectively formed by replacing the preformed portion123B in the first stack unit111B and the preformed portion123B in the second stack unit112B (seeFIG.10), the middle isolation portion125has a thickness substantially the same as that of the middle channel portion124. In the following, another semiconductor structure80shown inFIGS.45and46are formed in accordance with some other embodiments. It is noted that similar numerals from the above-mentioned embodiments are used where appropriate, with some construction differences being indicated with different numerals.

The semiconductor structure80shown inFIGS.45and46has a structure similar to the semiconductor structure70shown inFIG.24, but include a middle isolation portion127which has a thickness greater than that of each of the middle channel portion124and the middle isolation portion125shown inFIG.24. The semiconductor structure80is advantageous for the case that the second gate electrode522have two gate parts5221,5222(seeFIG.44) stacked on and spaced apart from each other, because the middle isolation portion127may cooperate with other dielectric portions440to together provide good isolation between the two gate parts5221,5222, and provide a wider process window (or a higher process tolerance) for a process of forming the isolation between the two gate parts5221,5222.

FIG.27is a flow diagram illustrating a method20for manufacturing a semiconductor structure (for example, the semiconductor structure80shown inFIGS.44to46) in accordance with some embodiments.FIGS.28to46illustrate schematic views of intermediate stages of the method20in accordance with some embodiments. Some repeating structures are omitted inFIGS.28to46for the sake of brevity.

Referring toFIG.27and the example illustrated inFIG.31, the method20begins at step S21, where a first laminated structure81and a second laminated structure82are respectively formed on the unipolar region1and the CFET region2of the starting substrate100. The first laminated structure81has an upper surface substantially flush with an upper surface of the second laminated structure82.

The first laminated structure81includes a plurality of first channel layers80E and a plurality of first sacrificial layers80F disposed to alternate with the first channel layers80E. A bottommost one of the first sacrificial layers80F is disposed on the unipolar region1of the starting substrate100. In some embodiments, as shown inFIG.31, an uppermost one of the first channel layers80E has the upper surface of the first laminated structure81. In some other not shown embodiments, an uppermost one of the first sacrificial layers80F may have the upper surface of the first laminated structure81. In some embodiments, the first laminated structure81is a stack of semiconductor materials. Semiconductor materials suitable for forming the layers80E,80F are similar to those for the starting substrate100as described above with reference toFIG.2, and thus details thereof are omitted for the sake of brevity. It is noted that the first channel layers80E are made of a semiconductor material different from that of the first sacrificial layers80F, so that the first sacrificial layers80E can be selectively removed with respect to the first channel layers80E in subsequent processes due to different etching selectivity ratios.

The second laminated structure82includes a first set of layers821and a second set of layers822. The first set of layers821include at least one lower channel layer80A, at least one upper channel layer80B and a preformed layer80C which is disposed between and spaced apart from the at least one lower channel layer80A and the at least one upper channel layer80B in the Z direction. The second set of layers822include at least three second sacrificial layers80D, and are disposed to alternate with the layers80A,80B,80C of the first set of layers821. A bottommost one of the at least three second sacrificial layers80D is disposed on the CFET region2of the starting substrate100. In some embodiments, as shown inFIG.31, an uppermost one of the at least one upper channel layers80B has the upper surface of the second laminated structure82. In some other not shown embodiments, an uppermost one of the second sacrificial layers80D may have the upper surface of the second laminated structure82.

In some embodiments, the second laminated structure82has a configuration similar to that the laminated structure110shown inFIG.2, but the preformed layer80C in the second laminated structure82has a thickness greater than that of each of the lower and upper channel layers80A,80B. In some embodiments, the preformed layer80C has a thickness greater than that of each of the first channel layers80E. The thickness ranges for the lower and upper channel layers80A,80B and the second sacrificial layers80D are respectively similar to those for the lower and upper channel layers121,122and the sacrificial layers131as described above with reference toFIG.2. In some embodiments, the preformed layer80C may have a thickness ranging from about 5 nm to about 30 nm. The materials for the lower and upper channel layers80A,80B, the preformed layer80C and the second sacrificial layers80D are respectively similar to those of the lower and upper channel layers121,122, the preformed layer123and the sacrificial layers131as described above reference toFIG.2, and thus details thereof are omitted for the sake of brevity.

It is noted that a number of the first channel layers80E is designed to be greater than a number of the at least one lower channel layer80A, and greater than a number of the at least one upper channel layer80B. In some embodiments, as shown inFIG.44, a number of the first channel layers80E is three, but is not limited thereto, and may vary according to practical applications. In some other not shown embodiments, the number of the first channel layers80E may be two to four.

Since the first and second laminated structures81,82are formed on the unipolar region1and the CFET region2, respectively using two different deposition processes, a total number of the layers80E,80F in the first laminated structure81may be the same as or different from a total number of the layers80A,80B,80C,80D in the second laminated structure82. Furthermore, each of the first channel layers80E may have a thickness which is the same as or different from that of each of the lower and upper channel layers80A,80B, and each of the first sacrificial layers80F may have a thickness which is the same as or different from that of each of the second sacrificial layers80D.

In some embodiments, step S21may include sub-steps illustrated inFIGS.28to31in accordance with some embodiments, where the first laminated structure81is formed after formation of the second laminated structure82. In some not shown embodiments, the first laminated structure81may be formed before formation of the second laminated structure82.

Referring toFIG.28, a first stack structure800A is formed to cover the unipolar region1and the CFET region2of the starting substrate100, and includes a stack of semiconductor material layers801,802,803,804respectively for forming the layers80A,80B.80C,80D, using a manner similar to that for forming the laminated structure110as described above with reference toFIG.2.

Referring toFIG.29, a patterned mask96is formed to cover the first stack structure800A (seeFIG.28) at the CFET region2, followed by removing a portion of the first stack structure800A at the unipolar region1exposed from the patterned mask96. As such, a remaining portion of the first stack structure800A serves as the second laminated structure82.

Referring toFIG.30, a second stack structure800B, which includes a stack of semiconductor material layers805,806respectively for forming the layers80E,80F, is formed on the unipolar region1of the starting substrate100using a manner similar to that for forming the laminated structure110as described above with reference toFIG.2.

Referring toFIG.31, a planarization process, for example, but not limited to, CMP, is performed to remove the patterned mask96and to expose the second laminated structure82, thereby obtaining the first laminated structure81.

Referring toFIG.27and the examples illustrated inFIG.32, the method20proceeds to step S22, where the first laminated structure81is patterned into a first stack portion113A disposed on a first fin portion102, and the second laminated structure82is patterned into a second stack portion114A disposed on a second fin portion103. The first stack portion113A including a plurality of first channel films81E which are patterned from the first channel layers80E and a plurality of first sacrificial films81F which are patterned from the first sacrificial layers80F. The second stack portion114A includes a lower channel film82A which is patterned from the lower channel layer80A, an upper channel film82B which is patterned from the upper channel layer80B, a preformed film82C which is patterned from the preformed layer80C, and a plurality of second sacrificial films82D which are patterned from the second sacrificial layers80D. In some embodiments, as shown inFIG.32, the first and second fin portions101,102respectively at the unipolar and CFET regions1,2are spaced apart from each other in the Y direction and are formed at two different fin structures using the method20. In some other embodiments not shown, the first and second fin portions101,102respectively at the unipolar and CFET regions1,2may be formed in two parts of a single fin structure using the method20and are displaced from each other in the X direction.FIGS.33and34are schematic cross-sectional view taken along lines B-B′ and C-C′ ofFIG.32, respectively.

Furthermore, step22may further include forming the isolation regions180(seeFIG.32) at two opposite sides of each of the first and second fin portions101,102.

Referring toFIG.27and the examples illustrated inFIGS.35to37, the method20proceeds to step S23, where a patterned structure60A is formed.FIGS.35to37are views respectively subsequent toFIGS.32to34for illustrating the structure after step S23.

The patterned structure60A, which is formed from the first stack portion113A and the second stack portion114A, has a structure similar to that of the patterned structure60shown inFIGS.8and9, but has the differences as described in the following. In some embodiments, step S23includes sub-steps (i) and (ii). In sub-step (i) of step S23, the dummy gate portions190(seeFIGS.35to37) are formed over the first and second stack portions113A,114A (seeFIGS.32to34), followed by forming the multiple pairs of the gate spacers220. In sub-step (ii) of step S23, the first and second stack portions113A,114A (seeFIGS.32to34) are patterned to form the source/drain recesses210(see FIGS.36and37) and are respectively formed into the first and second stack units113B,114B shown inFIGS.35to37. Each pair of the source/drain recesses210are respectively disposed at the two opposite sides of the corresponding one of the first and second stack units113B,114B. In details, in sub-step (ii) of step S23, the first channel films81E (seeFIGS.32and33) are patterned into first channel portions (i.e., the lower, middle and upper channel portions121B,124,122B in the first stack unit113B, seeFIGS.35and36); the first sacrificial films81F (seeFIGS.32and33) are patterned into first sacrificial portions (i.e., the sacrificial portions131B in the first stack unit113B, seeFIGS.35and36); the lower channel film82A, the preformed film82C and the upper channel film82B (seeFIGS.32and34) are respectively patterned into the lower channel portion121B, the preformed portion126, and the upper channel portion122B in the second stack unit114B (seeFIGS.35and37); and the second sacrificial films82D (seeFIGS.32and34) are patterned into second sacrificial portions (i.e., the sacrificial portions131B in the second stack unit114B, seeFIGS.35and37).

Referring toFIG.27and the examples illustrated inFIGS.38to40, the method20proceeds to step S24, where the preformed portion126in the second stack unit114B (seeFIGS.35and37) is replaced with a middle isolation portion127to obtain a second stack unit114C.FIGS.38to40are views respectively subsequent toFIGS.35to37for illustrating the structures after step S24. Since the preformed portion126has a thickness greater than that of each of the lower and upper channel portions121B,122B, the middle isolation portion127has a thickness greater than that of each of the lower and upper channel portions121B,122B. In some embodiments, the preformed portion126is replaced in a manner similar to the process for replacing the preformed portion123B in the second stack unit112B (seeFIG.8) with the middle isolation portion125(seeFIG.13) and thus details thereof are omitted for the sake of brevity.

Referring toFIG.27and the examples illustrated inFIGS.41to43, the method20proceeds to step S25, where the inner spacers240, the first source/drain portions310, and the lower and upper source/drain portions321,322are formed. Since step S25may be performed in a manner similar to step14, thus details thereof are omitted for the sake of brevity. After formation of the inner spacers240is formed, the first and second stack units113B,114C (seeFIGS.38to40) are respectively formed into first and second stack units113C,114D (seeFIGS.41to43), and the first and second sacrificial portions131B (respectively at the unipolar and CFET regions1,2, seeFIGS.38to40) are recessed and formed into first and second sacrificial portions131C (seeFIGS.42and43).

Referring toFIG.27and the examples illustrated inFIGS.44to46, the method20proceeds to step S26, where a replacement gate process is performed, thereby obtaining the semiconductor structure80.FIGS.44to46are views respectively subsequent toFIGS.41to43for illustrating the structures after step S26.

The semiconductor structure80has a structure similar to that of the semiconductor structure70shown inFIGS.24to26, but has the differences as described in the following.

In step S26, the remaining dummy gate portion190A (seeFIGS.41and43) on the second stack unit114D and the sacrificial portions131C in the second stack unit114D are removed to form a third cavity (not shown). The lower and upper channel portions121B.122B, and the middle isolation portion127remaining in the second stack unit114D and exposed from the third cavity are together referred to as a second stack12S (seeFIGS.44and46). Afterwards, the second gate dielectric521and the second gate electrode522are sequentially formed in the third cavity.

It is noted that, in some embodiments, as shown inFIGS.44and46, the second gate electrode522may include a lower gate part5221and an upper gate part5222spaced apart from each other in the Z direction. The lower gate part5221is disposed around the lower channel portion121B in the second stack12S such that the lower channel portion121B is separated from the lower gate part5221by the second gate dielectric521. The upper gate part5222is disposed above the lower gate part5221, and is disposed around the upper channel portion122B in the second stack12S such that the upper channel portion122B is separated from the upper gate part5222by the second gate dielectric521. In some embodiments, as shown inFIG.56, the semiconductor structure80further includes two isolation features440, each of which is formed between the lower and upper gate parts5221,5222for isolation. In some embodiments, the isolation features440may be made of a low-k dielectric material (such as the examples described in the preceding paragraph). Each of the isolation features440may be configured as a single layer structure or a multi-layered structure. Other suitable materials and/or configurations for the isolation features440are within the contemplated scope of the present disclosure. It is noted that, the middle isolation portion127, which is surrounded by a portion of the second gate dielectric521, extends between the two isolation features440, and thus the middle isolation portion127, the portion of the second gate dielectric521and the isolation features440may together isolate the lower gate part5221from the upper gate part5222. Since the middle isolation portion127has a relatively great thickness, the isolation features440are liable to be formed on the lower gate part5221and at two opposite sides of the middle isolation portion127, using a suitable deposition processes (for example, but not limited to, CVD, or ALD), followed by a suitable etching back process.

In some embodiments, some steps in the method20may be modified, replaced, or eliminated without departure from the spirit and scope of the present disclosure. In some alternative embodiments, the semiconductor structure80may further include additional features, and/or some features present in the semiconductor structure80may be modified, replaced, or eliminated without departure from the spirit and scope of the present disclosure. For example, in some embodiments, the semiconductor structure80may further include the interfacial layers524, the front-side contact features531, the metal silicide features534, and the front-side interconnect layers540as described above with reference toFIGS.24to26, and details thereof are omitted for the sake of brevity.

In this disclosure, the semiconductor structure is provided to integrate two types of device (i.e., the first device unit which includes a non-stacked device, and the second device unit which has a CFET structure and which includes a stack of the lower and upper devices) on the same wafer. In addition to achievement of high integration density of the second device unit, it is worth noting that the non-stacked device has a number of channels which is not limited to be equal to a number of channel(s) in each of the lower and upper devices, and which can even be greater than the number of channel(s) in each of the lower and upper devices, such that the non-stacked device, which may be used as a power switch, may have an improved switching performance (e.g., switching frequency, etc.). Furthermore, the middle isolation portion for isolating the lower and upper devices in the second device unit can be formed with a thickness equal to or greater than that of the channel(s) in each of the lower device, the upper device and the first device unit. Therefore, the methods for making the semiconductor structure provided in this disclosure enable implementation of various circuit design.

In accordance with some embodiments of the present disclosure, a semiconductor structure includes a substrate, a first device unit, and a second device unit. The substrate includes a first region and a second region which is displaced from the first region. The first device unit is disposed on the first region, and includes a plurality of first channel portions spaced apart from each other, and two first source/drain portions spaced apart from each other such that each of the first channel portions extends between the first source/drain portions. The second device unit is disposed on the second region, and includes a lower device and an upper device. The lower device is disposed on the second region and includes at least one lower channel portion and two lower source/drain portions spaced apart from each other such that the at least one lower channel portion extends between the lower source/drain portions. The upper device is disposed above and spaced apart from the lower device, and includes at least one upper channel portion and two upper source/drain portions spaced apart from each other such that the at least one upper channel portion extends between the upper source/drain portions. A number of the first channel portions in the first device unit is greater than a number of the at least one lower channel portion in the lower device and greater than a number of the at least one upper channel portion in the upper device.

In accordance with some embodiments of the present disclosure, the second device unit further includes a middle isolation portion which is disposed between and spaced apart from the at least one lower channel portion and the at least one upper channel portion.

In accordance with some embodiments of the present disclosure, the middle isolation portion has a length in an X direction which is the same as that of each of the at least one lower channel portion and the at least one upper channel portion.

In accordance with some embodiments of the present disclosure, the middle isolation portion has a thickness in a Z direction transverse to the X direction which is the same as that of each of the first channel portions, and which is the same as that of each of the at least one lower channel portion and the at least one upper channel portion.

In accordance with some embodiments of the present disclosure, the middle isolation portion has a thickness in the Z direction which is greater than that of each of the first channel portions, and which is greater than that of each of the at least one lower channel portion and the at least one upper channel portion.

In accordance with some embodiments of the present disclosure, an uppermost one of the first channel portions has an upper surface which is flush with an upper surface of an uppermost one of the at least one upper channel portion.

In accordance with some embodiments of the present disclosure, the second device unit further includes two isolation features, each of which is disposed between one of the lower source/drain portions and a corresponding one of the upper source/drain portions.

In accordance with some embodiments of the present disclosure, the middle isolation portion extends between the two isolation features, such that the middle isolation portion and the isolation features together isolate the lower and upper devices.

In accordance with some embodiments of the present disclosure, the semiconductor structure further includes a first gate dielectric, a first gate electrode, a second gate dielectric, and a second gate electrode. The first gate dielectric is disposed around each of the first channel portions. The first gate electrode is disposed on the first gate dielectric such that each of the first channel portions is separated from the first gate electrode by the first gate dielectric. The second gate dielectric is disposed around each of the at least one lower channel portion, the at least one upper channel portion and the middle isolation portion. The second gate electrode is disposed on the second gate dielectric such that each of the at least one lower channel portion, the at least one upper channel portion, and the middle isolation portion is separated from the second gate electrode by the second gate dielectric.

In accordance with some embodiments of the present disclosure, the semiconductor structure further includes a first gate dielectric, a first gate electrode, a second gate dielectric, and a second gate electrode. The first gate dielectric is disposed around each of the first channel portions. The first gate electrode is disposed on the first gate dielectric such that each of the first channel portions is separated from the first gate electrode by the first gate dielectric. The second gate dielectric is disposed around each of the at least one lower channel portion, the at least one upper channel portion and the middle isolation portion. The second gate electrode includes a lower gate part and an upper gate part. The lower gate part is disposed around the at least one lower channel portion such that the at least one lower channel portion is separated from the lower gate part by the second gate dielectric. The upper gate part is disposed above and spaced apart from the lower gate part, and is disposed around the at least one upper channel portion such that the at least one upper channel portion is separated from the upper gate part by the second gate dielectric.

In accordance with some embodiments of the present disclosure, the semiconductor structure further includes an isolation feature disposed between the lower gate part and the upper gate part.

In accordance with some embodiments of the present disclosure, a method for manufacturing a semiconductor structure, includes: forming a first fin portion and a second fin portion on a semiconductor substrate, the first and second fin portions being displaced from each other; forming a first stack on the first fin portion, the first stack including at least one lower channel portion, at least one upper channel portion, and a middle channel portion which is formed between and spaced apart from the at least one lower channel portion and the at least one upper channel portion; forming a second stack on the second fin portion, the second stack including at least one lower channel portion, at least one upper channel portion, and a middle isolation portion which is formed between and spaced apart from the at least one lower channel portion and the at least one upper channel portion; forming two first source/drain portions on the first fin portion, the first source/drain portions being spaced apart from each other such that each of the at least one lower channel portion, the at least one upper channel portion and the middle channel portion in the first stack extends between the first source/drain portions; forming two lower source/drain portions on the second fin portion, the lower source/drain portions being spaced apart from each other such that the at least one lower channel portion in the second stack extends between the lower source/drain portions; and forming two upper source/drain portions which are respectively above and spaced apart from the lower source/drain portions such that the at least one upper channel portion in the second stack extends between the upper source/drain portions. A first sum of a number of the at least one lower channel portion, a number of the at least one upper channel portion and a number of the middle channel portion in the first stack is greater than a number of the at least one lower channel portion in the second stack and greater than a number of the at least one upper channel portion in the second stack.

In accordance with some embodiments of the present disclosure, formation of the first and second stacks includes: forming a first stack unit and a second stack unit respectively on the first fin portion and the second fin portion, each of the first and second stack units including a first set of portions which include the at least one lower channel portion, the at least one upper channel portion and a preformed portion that is disposed between and spaced apart from the at least one lower channel portion and the at least one upper channel portion, and a second set of portions which include at least three sacrificial portions, and which are disposed to alternate with the first set of portions, a bottommost one of the at least three sacrificial portions being disposed on a corresponding one of the first and second fin portions; replacing the preformed portion in the first stack unit with the middle channel portion; removing the at least three sacrificial portions in the first stack unit, thereby obtaining the first stack on the first fin portion; replacing the preformed portion in the second stack unit with the middle isolation portion; and removing the at least three sacrificial portions in the second stack unit, thereby obtaining the second stack on the second fin portion.

In accordance with some embodiments of the present disclosure, the at least one lower channel portion, the at least one upper channel portion and the middle channel portion are made of a first semiconductor material. The at least three sacrificial portions are made of a second semiconductor material. The preformed portion is made of a third semiconductor material. The first, second and third semiconductor materials have different chemical compositions from one another such that the first, second and third semiconductor materials have different etching selectivity ratios from one another.

In accordance with some embodiments of the present disclosure, formation of the first and second stack units includes: forming a laminated structure on a starting substrate, the laminated structure including a first set of layers which include at least one lower channel layer, at least one upper channel layer and a preformed layer that is disposed between and spaced apart from the at least one lower channel layer and the at least one upper channel layer, and a second set of layers which include at least three sacrificial layers, and which are disposed to alternate with the first set of layers, a bottommost one of the at least three sacrificial layers being disposed on the starting substrate; and performing a patterning process such that the starting substrate is patterned into the semiconductor substrate and the first and second fin portions which are formed on the semiconductor substrate, the at least one lower channel layer, the at least one upper channel layer and the preformed layer are respectively patterned into the at least one lower channel portion, the at least one upper channel portion and the preformed portion in each of the first and second stack units, and the at least three sacrificial layers are respectively patterned into the at least three sacrificial portions in each of the first and second stack units.

In accordance with some embodiments of the present disclosure, formation of the first and second stacks includes: forming a first laminated structure on a first region of a starting substrate, the first laminated structure including at least three first channel layers and at least three first sacrificial layers disposed to alternate with the at least three first channel layers, a bottommost one of the at least three first sacrificial layers being disposed on the first region of the starting substrate; forming a second laminated structure on a second region of the starting substrate, the first and second regions being displaced from each other, the second laminated structure including a first set of layers which include at least one lower channel layer, at least one upper channel layer and a preformed layer that is disposed between and spaced apart from the at least one lower channel layer and the at least one upper channel layer, and a second set of layers which include at least three second sacrificial layers, and which are disposed to alternate with the first set of layers, a bottommost one of the at least three second sacrificial layers being disposed on the second region of the starting substrate; performing a patterning process such that the starting substrate is patterned into the semiconductor substrate and the first and second fin portions, the at least three first channel layers are respectively patterned into the at least one lower channel portion, the at least one upper channel portion and the middle channel portion in the first stack, the at least three first sacrificial layers are respectively patterned into at least three first sacrificial portions, the at least one lower channel layer and the at least one upper channel layer are respectively patterned into the at least one lower channel portion and the at least one upper channel portion in the second stack, the preformed layer is patterned into a preformed portion, and the at least three second sacrificial layers are respectively patterned into at least three second sacrificial portions; replacing the preformed portion with the middle isolation portion; and removing the at least three first sacrificial portions and the at least three second sacrificial portions.

In accordance with some embodiments of the present disclosure, a method for manufacturing a semiconductor structure includes: forming a first fin portion and a second fin portion on a semiconductor substrate, the first and second fin portions being displaced from each other; forming a first stack on the first fin portion, the first stack including a plurality of first channel portions spaced apart from each other; forming a second stack on the second fin portion, the second stack including at least one lower channel portion, at least one upper channel portion and a middle isolation portion which is formed between and spaced apart from the at least one lower channel portion and the at least one upper channel portion; forming two first source/drain portions on the first fin portion, the first source/drain portions being spaced apart from each other such that each of the first channel portions extends between the first source/drain portions; forming two lower source/drain portions on the second fin portion, the lower source/drain portions being spaced apart from each other such that the at least one lower channel portion extends between the lower source/drain portions; forming two upper source/drain portions which are respectively above and spaced apart from the lower source/drain portions such that the at least one upper channel portion extends between the upper source/drain portions; and forming two isolation features each of which is formed between one of the lower source/drain portions and a corresponding one of the upper source/drain portions. A number of the first channel portions is greater than a number of the at least one lower channel portion and greater than a number of the at least one upper channel portion.

In accordance with some embodiments of the present disclosure, formation of the first and second stacks includes: forming a first laminated structure on a first region of a starting substrate, the first laminated structure including a plurality of first channel layers and a plurality of first sacrificial layer formed to alternate with the first channel layers, a bottommost one of the first sacrificial layers being formed on the first region of the starting substrate; forming a second laminated structure on a second region of the starting substrate, the second laminated structure including a first set of layers which include at least one lower channel layer, at least one upper channel layer and a preformed layer that is disposed between and spaced apart from the at least one lower channel layer and the at least one upper channel layer, and a second set of layers which include at least three second sacrificial layers and which are disposed to alternate with the first set of layers, a bottommost one of the at least three second sacrificial layers being disposed on the second region of the starting substrate; performing a patterning process, such that the starting substrate is patterned into the semiconductor substrate and the first and second fin portions, the first channel layers are respectively patterned into the first channel portions, the first sacrificial layers are respectively patterned into a plurality of first sacrificial portions, the at least one lower channel layer and the at least one upper channel layer are respectively patterned into the at least one lower channel portion and the at least one upper channel portion, the preformed layer is patterned into a preformed portion, and the at least three second sacrificial layers are respectively patterned into at least three second sacrificial portions; replacing the preformed portion with the middle isolation portion; and removing the first sacrificial portions and the at least three second sacrificial portions.

In accordance with some embodiments of the present disclosure, the preformed layer has a thickness greater than that of each of the first channel layers.

In accordance with some embodiments of the present disclosure, the first laminated structure is formed before or after forming the second laminated structure.