Nonvolatile memory with program while program verify

A page mode program sequence is described that includes first and second bias applying cycles. In the first cycle, a program bias is applied to a first part of a page of memory cells, while a program verify bias is applied to, and data is sensed from, a second part of the page. In this manner, a first part of the page is programmed, while a second part of the page is verified. This operation is followed by a second bias applying cycle, in which a program bias is applied to the second part of the page, while a program verify bias is applied to, and data is sensed from, the first part of the page.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to nonvolatile memory devices, including flash memory and page mode flash memory, which include program and program verify operations.

2. Description of Related Art

Nonvolatile memory devices typically include a memory array comprising memory cells that maintain their data even when electrical power has been removed from the device. There are a variety of types of nonvolatile memory devices. One type includes so-called “read-only memory,” like mask ROM in which the data is stored in the memory cell by implanting impurities in the channel region of MOS transistors. The data stored in mask ROM devices, and other nonvolatile read-only memory devices, cannot be changed in the field. Another type of nonvolatile memory device includes electrically erasable and programmable memory cells, such as flash memory. The data stored in flash memory cells, and other nonvolatile electrically erasable and programmable memory cells, can be changed in the field using electronic programming and erasing procedures. Representative flash memory technologies include floating gate memory cells and charge trapping memory cells such as SONOS, NROM, PHINES and the like.

There are a variety of biasing procedures that are used for programming and erasing memory cells in flash memory. The biasing procedures for floating gate memory cells and charge trapping memory cells cause tunneling of electrons and/or holes into and out of the floating gates or charge trapping structures. The concentration of charge held in the floating gates or the charge trapping structures has an effect on the threshold voltage of the memory cell. Thus, by controlling the amount of charge held in the floating gates, or in the charge trapping structures, the threshold voltage of the memory cell can be set, and data stored.

Due to demand for faster access times combined with large, high-density arrays for flash memory, page read and burst read flash memories have been developed. In normal flash memory, the read operation is executed word by word so that within a specified time, such as time after address transition (TAA of for example 100 ns to 70 ns or less) or time after a chip enable signal (TCE), only one 16-bit word is addressed, its contents sensed, and its data output. In page mode devices, the input and output structures for the array may include a fast access buffer storing a page including for example, 1024 bits or 2048 bits, on the chip. The programming and reading procedures use the page buffer to improve throughput, and in some cases are set up to provide for addressing more than one word at a time, such as four words (64 bits) or more, during programming to and reading from the page buffer. Data stored in the page buffer can be read out in burst mode or otherwise with very short cycle times.

According to a typical process, to program a page in the array, a page buffer is loaded with data to be programmed, which is then transferred in chunks to bit latches associated with a set of sense amplifiers, including for example 32 or 64 sense amplifiers, coupled via decoding circuits to columns in the array, and programming the chunks of the page in parallel, with the program bias for each bit line being controlled by the data in the corresponding bit latch. A verify procedure for page mode programming can include automatically clearing the bits in the page buffer which correspond to cells that are successfully programmed. The data stored in the page buffer is then read to confirm that all bits have been cleared to indicate a successful page program operation.

As mentioned above, the operation to program the cells in a flash memory device typically involves a procedure that causes injection or ejection of charge into a charge storage structure that affects the threshold of the cell. The charge injection or ejection procedure must be tightly controlled for modern, high density operations. For multiple bit per cell embodiments, even greater control of the charge injection or ejection operation is required.

Because of the need for precise control of cell thresholds in memory devices along with variations in memory cell characteristics, variations in voltages applied, and variations in other parameters across an array, the biasing procedures used for programming and erasing operations in flash memory can result in non-uniform levels of charge stored in the cells distributed across the array. Therefore, the biasing procedures applied in many devices include a sequence of programming with verify operations between each pulse, or between each set of pulses. A typical verify process includes driving word line voltages to program verify levels, which are changed slightly from the standard read level in order to provide program or erase margin. Then, data is sensed from the memory cells to determine whether each cell has been successfully programmed or erased. If the verify process fails, then retry program pulses, followed by verify operations, are applied iteratively until a successful verify is achieved, or a maximum number of retries is reached.

For precise control of the threshold, memory devices are designed so that several iterations of the program and verify procedure may be required, that cause small increments in change of the threshold voltages for convergence on a target threshold level in a given cell on the device. The time required for a program operation therefore includes a plurality of cycles including both the program pulse and the program verify interval. See, U.S. Pat. No. 6,714,457 by Hsu et al.; U.S. Pat. No. 5,835,414 by Hung et al.; U.S. Pat. No. 5,748,535 by Lin et al.; U.S. Pat. No. 5,751,637 by Chen et al.; U.S. Pat. No. 5,787,039 by Chen et al.; U.S. Pat. No. 5,638,326 by Hollmer et al.; and U.S. Pat. No. 6,141,253 by Lin.

It is desirable to provide an architecture for nonvolatile memory and program and program verify procedures for such memory, that reduces the time required for the program operation while supporting precise control over memory cell threshold voltages.

SUMMARY OF THE INVENTION

The present invention provides a method for programming a nonvolatile memory device with input data in memory cells identified by respective memory cell addresses. The method includes loading a set of data to be stored in a set of memory cells in buffer circuitry, where the set of memory cells consists of memory cells that have identical higher order address bits, such as memory cells in a single page. A program sequence is executed that includes first and second bias applying cycles. In the first cycle, a program bias is applied to a first part of the set of memory cells, while a program verify bias is applied to, and data is sensed from, a second part of the set of memory cells. In this manner, a first part of the set of memory cells is programmed, while a second part of the set of memory cells is verified. This operation is followed by a second bias applying cycle, in which a program bias is applied to the second part of the set of memory cells, while a program verify bias is applied to, and data is sensed from, the first part of the set of memory cells. These two bias applying cycles result in a program pulse being applied to both the first and second parts of the set of memory cells. In an embodiment, the program sequence includes updating the set of data to be programmed in response to the sensing operation during the first and second bias applying cycles. If the updated set of data does not indicate success of the programming sequence, then the program sequence is retried using the updated set of data. This sequence of two bias applying cycles is repeated until both parts of the set of memory cells are successfully programmed. In this manner, the time required for verifying the programming of data in the set of memory cells is hidden within the time used for programming, saving substantial time in the overall program operation. The technology is suitable for devices in which when multiple program pulses are required to achieve tight control over the threshold voltages of the cells being programmed.

The nonvolatile memory device includes structures that support the program-while-verify bias cycles. For example, in one embodiment, the set of memory cells comprises cells in a row of cells in a memory array. The first part of the set of memory cells is coupled to a first word line along the row, and the second part of the set of memory cells is coupled to a second word line along the row. Thus, the array is split along the row, and each of the two word lines along the row has an independent word line driver activated in response to the same higher order address bits.

In one embodiment, the memory cells along the row are accessed by a page address, where a page includes a large number of cells such as 1024 or 2048 cells. The set of memory cells subject of the first and second bias applying cycles may comprise in this example 64 memory cells or 128 memory cells of the page. The first part of the set of memory cells may comprise a chunk of 16, 32 or 64 memory cells coupled to one of the word lines, while the second part of the set of memory cells may comprise a chunk of 16, 32 or 64 memory cells coupled to the second word line along the row. In another embodiment, the set of memory cells subject of the programming sequence comprises cells in a first row of memory cells in a first sector of the array coupled to a first word line and cells in a second row of memory cells in a second sector in the array coupled to a second word line. The first word line and the second word line are driven by independent word line drivers activated in response to the same higher order address bits, such that a page includes memory cells along a row in the first sector and memory cells along another row in the second sector.

An embodiment of the method includes storing a page of data in a buffer on the memory device, which is to be stored in a corresponding page of memory cells identified by a set of higher order address bits. Chunks of data from the buffer are loaded in bit latches coupled to the decoding circuitry. The program sequence comprising the first and second bias applying cycles is executed on a first chunk in the first part of the split page and a second chunk in the second part of the split page, repeatedly until the pair of chunks is successfully programmed, and then the next pair of chunks is loaded from the buffer to the bit latches, and programmed until all the data of the page is successfully programmed.

An integrated circuit is described supporting the program-while-verify method described above. The integrated circuit includes an array of memory cells including a plurality of bit lines and a plurality of word lines. Decoder circuitry is coupled to the plurality of bit lines and the plurality of word lines that is responsive to addresses to access memory cells in the array, and to selectively apply a program bias and a program verify bias to first and second word lines having common higher order address bits, such as a page address. Sense circuitry is coupled to the array, and arranged to sense data in a plurality of memory cells, such as a chunk of memory cells as discussed above, in parallel. Buffer circuitry is coupled to the array to support the program operations. In addition, a state machine or other circuitry is coupled to the array, decoder circuitry and buffer circuitry to control execution of program operations. The program operations include the methods described above.

In embodiments of the invention, the buffer circuitry comprises a page buffer which stores a page of data to be stored in a corresponding page of memory cells. In another embodiment, the buffer circuitry comprises a plurality of latches coupled with the decoder circuitry and associated with the sense amplifiers. The plurality of latches store a chunk of data from the page to be stored which indicates whether the memory cell on a corresponding bit line in the array needs programming during a particular bias applying cycle. In yet another embodiment, the buffer circuitry includes both a page buffer, and a plurality of latches as discussed above.

Technology described herein includes an integrated circuit memory architecture having a split page organization, where a program bias can be applied to a first part of the split page, while a program verify bias is applied to a second part of the split page. High speed page mode operations are supported, achieving improved control over threshold voltages achieved during programming, and reduced times required for programming because all or part of the time needed for program verify is hidden within the time needed for applying programming pulses.

DETAILED DESCRIPTION

A detailed description of embodiments of the present invention is provided with reference to theFIGS. 1–7.

FIG. 1is a simplified block diagram of a single chip, integrated circuit memory device9supporting page mode operations and program-while-verify operations. The memory device9includes a flash memory array10that includes an array of memory cells typically organized into a plurality of sectors, and accessible using a plurality of bit lines, a plurality of word lines and a plurality of sector select lines. A row decoder11is used for accessing selected word lines and sectors. The plurality of word lines include pairs of word lines that are accessed in response to identical higher order address bits, as explained below. A Y-select column decoder12is used for accessing selected bit lines. A plurality of sense amplifiers13, or other sensing circuitry, is coupled to data lines from the output of the column decoder12, and arranged to sense two chunks of data in parallel, where each chunk includes for example 32 bits.

In the illustrated example, a page of data includes 1024 bits. The two chunks together amount to 64 bits in this example, which can be read in parallel through 64 sense amplifiers coupled to the column decoder12. The 64 bits correspond to four words, each of which includes two bytes that are 8 bits wide. Other embodiments include a greater number of bits per page, including for example 2048 bits per page or more, and larger or smaller chunks. The sense amplifiers13, with associated bit latches used during program operations, are coupled to column decoder12. The sense amplifiers13and bit latches are coupled to a page buffer15, so that data can be moved from the sense amplifiers13to the page buffer15and from the page buffer15to the bit latches in support of read, erase and program operations.

Addressing circuits20are included on the memory device shown inFIG. 1. The addressing circuits20provide addresses to the row decoder11, the column decoder12, and to the page buffer15. An I/O bus19is coupled to the page buffer15.

A state machine21for page mode read, erase and program operations, including program-while-verify operations, is included on the integrated circuit. In support of the operations of the state machine, read, erase and program supply voltages are generated and controlled by circuitry22on the circuit. The state machine21comprises a processor executing instructions, programmable logic structures, dedicated logic, or various combinations thereof.

The array10is configured so that the set of cells arranged to store a page of data identified by identical higher order address bits comprises a first part that is coupled to a first word line, and a second part that is coupled to a second word line. The state machine21and decoders11and12are configured so that a program bias can be applied to bit lines and word lines coupled to cells storing a chunk of data in the first part of the page, while a program verify bias is applied to bit lines and word lines coupled to cells storing another chunk of data in the second part of the page. In a ping-pong type operation, the program-while-verify operation includes a sequence that programs cells in the first part of the page while verifying cells in the second part of the page, then programs cells in the second part of the page while verifying cells in the first part of the page. Thus, the time required for programming data in the first part of the page substantially overlaps with the time required for verifying data in the second part of the page. Where each part of the page requires multiple program and program verify steps to achieve precise control over cell threshold voltages, the program operation can be achieved by applying technology described herein with little or no additional time being allotted for verify operations.

FIG. 2is a simplified diagram of an array structure having split pages. As shown, the array is organized into a left bank50and a right bank51. X-decoder52and X-decoder53are coupled to the left bank and the right bank respectively. Word lines54in the left bank and55in the right bank are arranged along a row of memory cells in the array. Word line drivers58and59drive the word line54and word line55respectively in response to the X-decoders52,53based on a page address, which includes higher order bits of an address for a memory cell. During a program operation, the bias voltages applied by the word line drivers58and59can be separately controlled as described below. Word line drivers60and61drive word lines56and57in response to X-decoders52and53in a similar manner. Y-decoder64is coupled to the bit lines in the array, and is operable in response to addresses to select a first chunk of bit lines for a left set66of n sense amplifiers SA[0:(n−1)] and a second chunk of bit lines for a right set67of n sense amplifiers SA[n:(2n−1)]. During a program operation, the left set66and the right set67can be selectively operated for applying a program bias or for sensing data, as described below. The sets66,67of sense amplifiers are coupled via bus68to the page buffer implemented using static random access memory SRAM or other read/write storage technology. The page buffer includes a left bank70storing a plurality of n-bit chunks of data (M×n bits) and a right bank71storing a plurality of n-bit chunks of data (M×n bits). The page buffer can be logically or physically separated into left and right banks in various embodiments. Conceptually, a program operation includes the data flow represented by arrows (a)–(d) inFIG. 2. The data flow arrow (a) represents loading a chunk of data from the page buffer to bit latches associated with the left set66of sense amplifiers and applying program bias for programming of the left bank50. The data flow arrow (b) represents applying verify bias, sensing data from the cell and updating of the data in the page buffer in response to a verify operation on the right bank51, and can be accomplished while the operation represented by data flow arrow (a) is accomplished. The data flow arrow (c) represents loading a chunk of data from the page buffer to bit latches associated with the right set67of sense amplifiers and applying program bias for programming of the right bank51. The data flow arrow (d) represents applying verify bias, sensing data from the cell and updating of the data in the page buffer in response to a verify operation on the left bank50, and can be accomplished while the operation represented by data flow arrow (c) is accomplished. Thus a first part of the page of data that is stored in cells coupled to the word lines54and55is programmed while a second part of the page of data that is stored in cells coupled to word lines54and55is verified using separate data paths and bias voltages.

FIG. 3is a simplified diagram of an alternative array structure having split pages. As shown the array is organized into a top sector80and a bottom sector81, including word line82arranged along a row of cells in the top sector80and word line83arranged along a row of cells in the bottom sector81. An X-decoder (not shown) selects word line drivers84and85, which drive word lines82and83respectively, in response to an identical page address.

The top sector80includes a left bank in which global bit lines, such as bit line86, are connected and disconnected to local bit lines coupled to the cells in corresponding columns using a top select structure SELT(n) and a bottom select structure SELB(n). The top select structure SELT(n) and bottom select structure SELB(n) are controlled by the sector select lines SECn, that are in turn generated by a sector decoder. In addition, the top sector80includes a right bank in which global bit lines, such as bit line87, are connected and disconnected to local bit lines coupled to the cells in corresponding columns using a top select structure SELT(n−1) and a bottom select structure SELB(n−1), which are controlled by the sector select lines SECn−1.

The bottom sector81includes a left bank in which global bit lines, such as bit line86, are connected and disconnected to local bit lines coupled to the cells in corresponding columns using a top select structure SELT(n−1) and a bottom select structure SELB(n−1). The top select structure SELT(n−1) and bottom select structure SELB(n−1) are controlled by the sector select lines SECn-1, that are in turn generated by a sector decoder. In addition, the bottom sector81includes a right bank in which global bit lines, such as bit line87, are connected and disconnected to local bit lines coupled to the cells in corresponding columns using a top select structure SELT(n) and a bottom select structure SELB(n), which are controlled by the sector select lines SECn.

Also shown inFIG. 3are the column decoding, sense amplifier and page buffer structures, described above with reference toFIG. 2, which are given like reference numerals.

Accordingly, the array shown inFIG. 3is arranged so that a first part of the page of data is stored in memory cells, such as cell A, in the left bank of the top sector80, and a second part of the page of data is stored in memory cells, such as cell B, in the right bank of the bottom sector81. In this manner, bias voltages applied to the word line82and delivered to cell A can be different from the bias voltages applied to word line83and delivered to cell B during a program operation.

FIG. 4illustrates the current flow paths for a program-while-verify operation in an embodiment of the memory device having split pages, such as described with reference toFIG. 2. Basically, the program operation for cell A in a first part of the page is executed along current flow paths100and101, while the verify operation for cell B in a second part of the page is executed along current flow paths102and103. As illustrated, cell A is situated in a row of memory cells coupled to word line WL0A, while cell B is situated in a row of memory cells coupled to word line WL0B. The word line WL0A is controlled by word line driver104, while the word line WL0B is controlled by word line driver105in the illustrated embodiment. The word line drivers104and105can be operated selectively during a program-while-verify operation to apply different bias voltages, using structures such as those described below with reference toFIG. 5.

Cell A, and other cells in the left bank of the array, are coupled via local bit lines to a top select structure including the top block transistor107controlled by signal BLB(n), and a bottom select structure including the bottom block transistor106controlled by signal BLT(n). From the top block transistor107, the current flow proceeds to a global bit line through Y-pass transistors110which are part of the column decoder circuitry, to a selector112controlled by the signal SELECTBL1. The selector112is controlled during a program operation to direct a current flow to a bit latch116, referred to as a “need pgm?” latch. The bit latch116is powered by a voltage regulator118, which delivers the program bias voltage under the control of the control state machine on the device. The voltage regulator118is driven by on-chip charge pumps and off-chip power supplies in various embodiments of the described technology.

In a representative embodiment, the memory cells comprise nitride charge trapping cells or floating gate cells, programmed by channel hot electron injection which is induced by applying a high positive voltage on a bit line with a positive voltage on the word line, and ground on the source. The selector112is controlled during a verify operation, or during a read operation, to direct current flow through the load114. The voltage applied to the bit line during a sensing operation is also a positive voltage delivered through the load114. Sense amplifier SAO is coupled to the load114, and generates sensed output data DO0.

Cell B, and other cells in the right bank of the array, are coupled via local bit lines to a top select structure including the top block transistor109, controlled by signal BLB(n), and a bottom select structure including the bottom block transistor108controlled by signal BLT(n). From the top block transistor109, the current flow proceeds to a global bit line through Y-pass transistors111which are part of the column decoder circuitry, to a selector113controlled by the signal SELECTBL2. The selector113is controlled during a read or verfiy operation to direct a current flow through the load115. Sense amplifier SA63is coupled to the load115, and generates sensed output data DO63. During a verify operation, the sensed output data DO63is compared with data in the bit latch117, or data in a page buffer corresponding to the memory cell, to determine whether a program pulse needs to be applied to the cell in a following program operation. The selector112is controlled during a program operation to direct current flow to a bit latch117, referred to as a “need pgm?” latch. The bit latch117is powered by a voltage regulator118, which delivers the program bias voltage under the control of the control state machine on the device.

FIG. 5illustrates structures and word line drivers used for applying different bias voltages to word line WL0A and word line WL0B, during a program-while-verify operation. The structures include a regulator circuit150which delivers a program level voltage on line151and a program verify level voltage on line152. In the example applying channel hot electron injection, as mentioned above, the program bias and the program verify bias are both positive voltages that can be applied at the same time to the array. The regulator circuit150is driven by on-chip charge pumps and off-chip power supplies in various embodiments of the described technology. The voltages on lines151and152are applied to a first selector154that is controlled by the signal SELECTWL1and to a second selector153that is controlled by the signal SELECTWL2.

During an operation applying a program bias to word line WL0A, selector154is operated to apply the program level voltage on the global word line GWL1, at for example about 10 V in one embodiment. The global word line GWL1is applied to word line drivers in the left bank of the array, including the driver coupled to the word line WL0A, comprising transistors156,158and160. Transistor156is a p-channel transistor formed in a well that is coupled to its drain. Transistors158and160are n-channel transistors, each having its well coupled to the bias line WLDRVSS, which is typically ground, or another reference level, like a program inhibit voltage, applied to the word line drivers. When the word line WL0A is selected, the decoder circuitry will apply a ground signal to the gates of transistor156and160, and a supply potential to the gate of transistor158. The program voltage from the global word line GWL1flows through the transistors156and158to the word line WL0A.

During an operation applying a program verify bias to word line WL0B, selector153is operated to apply the program verify level voltage on the global word line GWL2, at for example about 5 V in one embodiment. The global word line GWL2is applied to word line drivers in the right bank of the array, including the driver coupled to the word line WL0B, comprising transistors157,159and161. Transistor159is a p-channel transistor formed in a well that is coupled to its drain. Transistors157and161are n-channel transistors, each having its well coupled to the bias line WLDRVSS, which is typically ground or another reference level, like a program inhibit voltage, applied to the word line drivers. When the word line WL0B is selected, the decoder circuitry will apply a ground signal to the gates of transistor159and161, and a supply potential to the gate of transistor157. The program verify voltage from the global word line GWL2flows through the transistors157and159to the word line WL0B.

Thus, the structures shown inFIG. 4andFIG. 5are representative of circuitry on an integrated circuit that supports applying a program bias voltage to memory cells storing data from a page in the left bank of an array, while applying a program verify bias voltage to memory cells storing data from the same page in the right bank of the array, and vice versa.

FIGS. 6A–6Care simplified diagrams used for the purpose of the explanation of a program-while-verify sequence. As shown inFIG. 6A, components of the integrated circuit include an array200, a first set201of sense amplifiers SA[0:31] and a second set202of sense amplifiers SA[32:63]. A data bus203is coupled between the first and second sets201,202of sense amplifiers and a page buffer204implemented as an SRAM. In the illustrated example, a chunk of data comprises 32 bits and can be sensed and programmed in parallel using the data structures of a split page device, such as the structures described above with reference toFIGS. 4 and 5.

Three steps of a program-while-verify operation are illustrated inFIG. 6A. In the first step (step1), a page of data is loaded in the page buffer204. The page consists of a plurality of 64 bit wide sets of data, each 64 bit wide set including a left chunk consisting of bits0–31, and a right chunk consisting of bits and32–34. In the second step (step2), 64 bits of data are loaded on the bus203, including the left chunk of data and thirty two 1's in the position of the right chunk of data. In the third step (step3), data is transferred from the data bus to the bit latches associated with the sense amplifiers. The bit latches associated with sense amplifiers SA[0:31] are loaded with the left chunk of data, while the bit latches associated with sense amplifiers SA[32:63] are loaded with all 1's, where a 1 stored in the bit latch corresponds with a “do-not-program state.” After transferring the data out of the SRAM into the bit latches, the process is ready for applying the bias voltages to the array.

FIG. 6Billustrates steps4a,4b,4cand4d, of the simplified flow, which are executed in parallel so they overlap at least partially in time. In particular, the data from the bit latches associated with sense amplifiers SA[0:31] is programmed into corresponding cells in the left bank of the array200(step4a), while data in cells in the right bank of the array is sensed (step4b), and then loaded on the bus203(step4c). Meanwhile the first chunk of data is copied back to the bus (step4d). Steps4a–4dresult in data on the bus that includes the first chunk of data to be programmed unmodified, and the second chunk of data equal to data sensed from corresponding cells in the array prior to programming.

FIG. 6Cillustrates the last step in the process, in which the page buffer is updated in response to the program-while-verify sequence. In particular, the data from the bus is compared with the data stored in the page buffer. If the corresponding bit in the page buffer matches the data on the bus, then the value of the bit in the page buffer is updated to “1” indicating a “do-not-program” state because the cycle has verified that the memory cell already stores the correct data. Because of an erase cycle prior to programming as applied in flash memory technologies known in the art, there should not be any cells in the right bank in a programmed state during the first cycle. Therefore, any mismatches of the data sensed from the array with data stored in the page buffer will correspond to bit positions selected for programming.

FIGS. 6A–6Cillustrate programming a chunk of data in the left bank while verifying a chunk of data in the right bank. The operation is executed again, with step2inverted so that all 1's indicating the “do-not-program” state are loaded into the bit latches associated with sense amplifiers SA[0:31], and steps4a–4dexecuted on the opposite side of the array to program bits32–63while verifying bits0–31. During this second cycle, the only cells in the left bank (bits0–31) in a program state will be those programmed during the previous program-while-verify cycle. Therefore, any mismatches of data sensed from the array with data stored in the page buffer will correspond to bit positions selected for programming, that did not successfully pass program verify. The sequence is repeated on the left and right sides of the array until all the bits in the two chunks of data are successfully programmed. Then, the next two chunks of data are programmed iteratively until the entire page is done.

FIG. 7is a flow chart illustrating a page program operation in a program-while-verify device based on split pages. The algorithm starts a page program command (block300). A page of data is then loaded into the page buffer, where the page comprises an even number N of chunks, and an index n for the algorithm is set to zero (block301). Next, steps302and303are executed in parallel, programming chunk(n) in the left half page, and verifying chunk (n+1) in the right half page, applying the procedures such as described above with reference toFIGS. 6A–6C. Next, the page buffer SRAM is updated based on the results of the verify operations (block304). Next, steps305and306are executed in parallel, verifying chunk(n) in the left half page, and programming chunk (n+1) in the right half page. Then, the page buffer SRAM is updated again based on the results of the verify operations (block307). At this point, both chunks (n) and (n+1) have been subjected to one program pulse each. The updated page buffer is checked to determine whether both chunks have passed the verify operation (block308). If not, the algorithm branches to block309determine whether a retry limit has been reached. If the retry limit has not been reached, then the algorithm loops back to steps302and303to retry the program-while-verify sequence for chunks (n) and (n+1). If at block309, the retry limit had been reached, then the procedure has failed (block310).

If at block308, both chunks (n) and (n+1) pass verify, then the index is tested to determine whether all the chunks in the page have been programmed, by determining whether n+1 is equal to N−1. If all chunks have not been programmed, then the index n is incremented by 2 at block312. Then the process loops back to steps302and303to execute the program-while-verify sequence for the next pair of chunks. If at block311, it is determined that all the chunks in the page have been successfully programmed and verified, then the page program process ends (block313).

Embodiments of the technology can be applied to memory cells storing multiple bits per cell that require multiple threshold levels to be programmable in a single cell, or one bit per cell as suits the need for a particular application.

The technology described is suitable for use in a wide variety of flash memory architectures, including NOR flash arrays, NAND flash arrays, virtual ground arrays, or other array configurations. The technology described is also suitable for arrays implemented using floating gate memory cells, arrays implemented using nitride charge trapping memory cells, and arrays implemented using other types of memory cells.

Technology described herein provides an integrated circuit memory device including nonvolatile memory where program and program verify processes can be executed at the same time in a split page architecture. Using a split page architecture, the left side and right side of the array can be provided different bias conditions supporting programming and program verifying at the same time. In this manner, the time required for the verify process in one part of the page can be hidden partially or completely during the time required for a program operation on a different part of the page.