Randomized clock cycle lengths for boot sequences

In general, this disclosure describes techniques for using a random number generator to affect the lengths of clock cycles in a clock waveform that drives the timing of operations performed by processing circuitry. In one example, the processing circuitry includes a central processing unit and a clock generator. The clock generator is configured, upon receiving an indication of a boot command for the processing circuitry, generate a random number using a true random number generator and generate, based at least in part on the random number, an output clock waveform indicating at least a length of a clock cycle for the central processing unit. The central processing unit is configured to execute a boot sequence for at least the processing circuitry using the output clock waveform.

TECHNICAL FIELD

This disclosure generally relates to processor clocks and, more specifically, to processor clocks for secure boot sequences.

BACKGROUND

Many computing systems, including those that receive content over networks, incorporate content protection or digital rights management technology that includes data decryption and encryption hardware and software. This encryption protects secure data, which is potentially sensitive, private, and/or right-managed and is stored or used on the system, from unauthorized access and exploitation.

SUMMARY

In general, this disclosure describes techniques for using a random number generator to affect the lengths of clock cycles in a clock waveform that drives the timing of operations performed by processing circuitry. These techniques may be applied to reduce a likelihood of a successful compromise of secure boot sequences being executed by computing systems, including AR/VR computing systems, among other applications to improve the security of computing systems and of encryption operations generally.

For example, a randomized clock generator that generates an output clock waveform may use a random number generator to affect the length of clock cycles within the output clock waveform. The random number generator repeatedly outputs random binary sequences that are applied to a clock waveform to vary the length of clock cycles within the clock waveform to produce the output clock waveform. The randomized clock generator may apply different random binary sequences to one or more clock cycles to cause the one or more clock cycles in the output waveform to vary in length. To apply a random binary sequence, the randomized clock generator may use a programmable clock divider to frequency divide the length of the one or more clock cycles by a value that is based on the random binary sequence.

The random number generator may include a pseudo-random number generator (PRNG). To increase the non-determinism of the random binary sequences, the PRNG may be seeded with seed information from a true random number generator (TRNG). This seeding may occur at the start of each secure boot sequence or periodically, for instance. To further increase the randomness of the output clock waveform from the random clock generator, a ring oscillator may generate the clock waveform that is modified using the random binary sequences. An external oscillator or phase-locked loop (PLL), for example, may alternatively be used to generate the clock waveform.

The output clock waveform generated by the randomized clock generator may be used to frustrate replay attacks or other attacks on a computing system and thereby increase the trustworthiness of the computing system. A replay attack exploits the predictable timing of operations executed by a computing device, such as during a secure boot sequence. By driving the timing of the operations using a clock waveform having randomly-generated cycle lengths, the timing of operations is no longer predictable and this reduces the likelihood that a replay attack will succeed. The output clock waveform as generated herein may also frustrate other types of attacks, such as channel analysis, reset glitching, laser pulsing, and so forth.

In one example of the techniques described herein, an artificial reality system includes a clock generator configured to generate, using one or more random binary sequences generated by a random number generator, an output clock waveform having one or more clock cycles of randomized lengths. The artificial reality system also includes processing logic configured to execute instructions according to the output clock waveform.

In another example of the techniques described herein, a method includes generating, by a processing circuit, using one or more random binary sequences generated by a random number generator, an output clock waveform having one or more clock cycles of randomized lengths. The method also includes executing, by the processing circuit, instructions according to the output clock waveform.

In another example of the techniques described herein, a computing device includes a clock generator configured to generate, using one or more random binary sequences generated by a random number generator, an output clock waveform having one or more clock cycles of randomized lengths. The computing device also includes a secure boot sequence for an operating system of the computing device, the secure boot sequence comprising executable instructions. The computing device further includes processing circuitry configured to execute the instructions according to the output clock waveform.

Like reference characters denote like elements throughout the figures and text.

DETAILED DESCRIPTION

FIG. 1Ais an illustration depicting an example artificial reality system10that implements a boot sequence with randomized clock cycle lengths in accordance with aspects of this disclosure. In the example ofFIG. 1A, artificial reality system10includes head mounted device (HMD)112, console106and, in some examples, one or more external sensors90. As shown, HMD112is typically worn by user110and includes an electronic display and optical assembly for presenting artificial reality content122to user110. In addition, HMD112includes one or more sensors (e.g., accelerometers) for tracking motion of HMD112. HMD112may include one or more image capture devices134, e.g., cameras, line scanners, and the like. Image capture devices134may be configured for capturing image data of the surrounding physical environment. In this example, console106is shown as a single computing device, such as a gaming console, workstation, a desktop computer, or a laptop.

In other examples, console106may be distributed across a plurality of computing devices, such as a distributed computing network, a data center, or a cloud computing system. Console106, HMD112, and sensors90may, as shown in this example, be communicatively coupled via network104, which may be a wired or wireless network, such as a WiFi® or 5G® based network, an Ethernet® network, a mesh network or a short-range wireless (e.g., Bluetooth®) communication medium. Although HMD112is shown in this example as being in communication with (e.g., tethered to or in wireless communication with) console106, in some implementations HMD112operates as a standalone, mobile artificial reality system. During operation, the artificial reality application constructs artificial reality content122for display to user110by tracking and computing pose information for a frame of reference, typically a viewing perspective of HMD112. Artificial reality system10may use external sensors90, external cameras102, etc. to capture 3D information within the real world, physical environment.

In general, this disclosure describes a secure boot sequence that initializes a secure execution environment for accessing and using secure data by authenticating the required set of software components so as to prevent malicious code from being loaded and executed. Some examples of these computing systems include artificial reality systems. Artificial reality systems are becoming increasingly ubiquitous with applications in many fields such as computer gaming, health and safety, industrial, and education. As a few examples, artificial reality systems are being incorporated into mobile devices, gaming consoles, personal computers, movie theaters, and theme parks. In general, artificial reality is a form of reality that has been adjusted in some manner before presentation to a user, which may include, e.g., a virtual reality (VR), an augmented reality (AR), a mixed reality (MR), a hybrid reality, or some combination and/or derivatives thereof.

Typical artificial reality systems include one or more devices for rendering and displaying content to users. As one example, an artificial reality system may incorporate a head-mounted display (HMD) worn by a user and configured to output artificial reality content to the user. The artificial reality content may include completely-generated content or generated content combined with captured content (e.g., real-world video and/or images).

In accordance with the techniques described herein, non-predictable clock generator132generates a processor clock having randomized clock cycle lengths. In some cases, non-predictable clock generator132may be a clock generator separate from the main processor clock for HMD112. In some cases, non-predictable clock generator132may be a configurable clock generator having a fixed mode and a non-predictable mode, where fixed mode produces an output waveform having cycles of default or near-constant (i.e., within the normal oscillator jitter tolerances) lengths while non-predictable mode produces an output waveform having cycles of randomized lengths. Non-predictable clock generator132may be even further configurable to, when in non-predictable mode, produce an output waveform having a uniform randomized length or to produce an output waveform where different portions of the output waveform have different randomized lengths. HMD112may specify the mode for the non-predictable clock generator132for different operations. For example, HMD112may signal the non-predictable clock generator132into non-predictable mode for a secure boot sequence of HMD112(or a component thereof).

Non-predictable clock generator132uses random numbers to generate an output clock waveform having one or more clock cycles with randomized lengths. The output clock waveform is input as the computing clock for a central processing unit (CPU) or other processing circuitry of HMD112that executes instructions according to clock cycles of an oscillating signal. While the output clock waveform may define a single randomized length for every clock cycle of the processing circuitry during a boot sequence, non-predictable clock generator132may modify the lengths for the output clock waveform cycles over time, such as throughout a secure boot sequence. As such, a clock cycle of the output clock waveform may have a different length than an immediately subsequent clock cycle of the output clock waveform. The length of a clock cycle of a processor clock is the time it takes for the processor clock signal to oscillate a full oscillation. In addition, the difference in length due to modification is greater than the normal jitter of the processor clock caused by, e.g., environmental conditions. In some cases, each clock cycle may be varied. In this way, non-predictable clock generator132may increase the randomness of the timing of the boot sequence operations, thereby increasing the trustworthiness of HMD112by frustrating replay attacks and/or other attacks on HMD112. Non-predictable clock generator132may produce the output clock waveform having randomized clock cycle lengths in response to receiving an indication of an upcoming secure boot sequence for HMD112or a component thereof.

While shown inFIG. 1Aand described above as being included in HMD112, non-predictable clock generator132may be included in console106in some examples. In these examples, console106may invoke non-predictable clock generator132when console106receives in indication to execute a boot command for one or more components of console106. In such examples, non-predictable clock generator132may then randomize the lengths of clock cycles for processing circuitry implemented in console106during a boot sequence of console106or components thereof. In other examples, a non-predictable clock generator132may be included in a peripheral device, such as a smartphone, tablet computer, personal data assistant (PDA), or other hand-held device that provides processing for HMD112. The non-predictable clock generator132may randomize the lengths of clock cycles for processing circuitry implemented in the peripheral device during a boot sequence of the peripheral device. In some examples, peripheral device may be a smartwatch, smartring, or other wearable device. The peripheral device may also be part of kiosk or other stationary or mobile system. The peripheral device may be in communication with HMD112, in any form factor included herein, and/or console106using one or more wired or wireless communications links (e.g., Wi-Fi, near-field communication of short-range wireless communication such as Bluetooth).

FIG. 1Bis an illustration depicting another example artificial reality system20that implements a boot sequence with randomized clock cycle lengths in accordance with aspects of this disclosure. Similar to artificial reality system10ofFIG. 1A, non-predictable clock generator132ofFIG. 1Bgenerates an output clock waveform with randomized clock cycle lengths to increase the resistance of the system to various attacks that are designed to access and/or manipulate sensitive data, e.g., during the boot sequence of system20.

In the example ofFIG. 1B, artificial reality system20includes external cameras102A and102B (collectively, “external cameras102”), HMDs112A-112C (collectively, “HMDs112”), console106, and sensors90. As shown inFIG. 1B, artificial reality system20represents a multi-user environment in which an artificial reality application executing on console106and/or HMDs112presents artificial reality content to each of users110A-110C (collectively, “users110”) based on a current viewing perspective of a corresponding frame of reference for the respective user110. That is, in this example, the artificial reality application constructs artificial content by tracking and computing pose information for a frame of reference for each of HMDs112. Artificial reality system20uses data received from cameras102and HMDs112to capture 3D information within the real-world environment, such as motion by users110and/or tracking information with respect to users110, for use in computing updated pose information for a corresponding frame of reference of HMDs112.

Each of HMDs112concurrently operates within artificial reality system20. In the example ofFIG. 1B, each of users110may be a “player” or “participant” in the artificial reality application, and any of users110may be a “spectator” or “observer” in the artificial reality application. HMD112C may each operate substantially similar to HMD112ofFIG. 1A. HMD112A may also operate substantially similar to HMD112ofFIG. 1Aand receive user inputs by tracking movements of hands132A,132B of user110A. HMD112B may operate similarly.

While shown inFIG. 1Band described above as being included in HMD112C, non-predictable clock generator132may be included in console106in some examples. In these examples, console106invokes non-predictable clock generator132to perform randomization of clock cycle lengths described herein. A content provider may implement randomization techniques of this disclosure that are generally reciprocal to the randomization of clock cycle lengths described above with respect to non-predictable clock generator132.

FIG. 2Ais an illustration depicting an example HMD configured to randomize clock cycle lengths during a boot sequence in accordance with the techniques of the disclosure. HMD112ofFIG. 2Amay be an example of any of HMDs112ofFIGS. 1A and 1B. HMD112may be part of an artificial reality system, such as artificial reality systems10,20ofFIGS. 1A, 1B, or may operate as a stand-alone, mobile artificial realty system configured to implement the techniques described herein. In the example ofFIG. 2A, HMD112takes the general form factor of a headset.

In this example, HMD112includes a front rigid body and a band to secure HMD112to a user. In addition, HMD112includes an interior-facing electronic display203configured to present artificial reality content to the user. Electronic display203may include, be, or be part of any suitable display technology, such as liquid crystal displays (LCD), quantum dot display, dot matrix displays, light emitting diode (LED) displays, organic light-emitting diode (OLED) displays, cathode ray tube (CRT) displays, e-ink, or monochrome, color, or any other type of display capable of generating visual output. In some examples, the electronic display is a stereoscopic display for providing separate images to each eye of the user. In some examples, the known orientation and position of display203relative to the front rigid body of HMD112is used as a frame of reference, also referred to as a local origin, when tracking the position and orientation of HMD112for rendering artificial reality content according to a current viewing perspective of HMD112and the user.

As further shown inFIG. 2A, in this example, HMD112further includes one or more motion sensors206, such as one or more accelerometers (also referred to as inertial measurement units or “IMUs”) that output data indicative of current acceleration of HMD112, GPS sensors that output data indicative of a location of HMD112, radar, or sonar that output data indicative of distances of HMD112from various objects, or other sensors that provide indications of a location or orientation of HMD112or other objects within a physical environment. Moreover, HMD112may include integrated image capture devices134A and134B (collectively, “image capture devices134”), such as video cameras, laser scanners, Doppler® radar scanners, depth scanners, or the like, configured to output image data representative of the physical environment.

FIG. 2Bis an illustration depicting another example of an HMD configured to randomize clock cycle lengths during a boot sequence in accordance with the techniques of the disclosure. HMD112ofFIG. 2Bmay be an example of any of HMDs112ofFIGS. 1A and 1B. HMD112may be part of an artificial reality system, such as artificial reality systems10,20ofFIGS. 1A, 1B, or may operate as a stand-alone, mobile artificial realty system configured to implement the techniques described herein. In the example ofFIG. 2B, HMD112takes the general form factor of glasses.

In this example, HMD112includes a front rigid body and two stems to secure HMD112to a user, e.g., by resting over the user's ears. In addition, HMD112includes an interior-facing electronic display203configured to present artificial reality content to the user. Electronic display203may include, be, or be part of any suitable display technology, such as liquid crystal displays (LCD), quantum dot display, dot matrix displays, light emitting diode (LED) displays, organic light-emitting diode (OLED) displays, cathode ray tube (CRT) displays, e-ink, or monochrome, color, or any other type of display capable of generating visual output. In some examples, the electronic display is a stereoscopic display for providing separate images to each eye of the user. In some examples, the known orientation and position of display203relative to the front rigid body of HMD112is used as a frame of reference, also referred to as a local origin, when tracking the position and orientation of HMD112for rendering artificial reality content according to a current viewing perspective of HMD112and the user.

Electronic display203may be split into multiple segments, such as into two segments, each segment corresponding to a separate lens disposed on the rigid front body of HMD112in the example ofFIG. 2B. In other examples, electronic display203may form a contiguous surface that spans both lenses and the lens-connecting bridge (i.e., the over-the-nose portion) of the rigid front body of HMD112in the example ofFIG. 2B. In some examples, electronic display203may also encompass portions of HMD112that connect the lenses of the front rigid body to the stems, or optionally, portions of the stems themselves, in the example form factor illustrated inFIG. 2B. These various designs of electronic display203in the context of the form factor of HMD112shown inFIG. 2Bimprove accessibility for users having different visual capabilities, eye movement idiosyncrasies, etc. Elements ofFIG. 2Bthat share reference numerals with elements ofFIG. 2Aperform like-functionalities, and are not described separately with respect toFIG. 2Bfor the sake of brevity.

In the examples illustrated inFIGS. 2A & 2B, control unit210of HMD112includes non-predictable clock generator132illustrated inFIGS. 1A & 1B. Control unit210may, for example, comprise any combination of one or more processors, one or more field programmable gate arrays (FPGAs), one or more application specific integrated circuits (ASICs), and one or more application specific standard products (ASSPs). Control unit210may also comprise memory, both static (e.g., hard drives or magnetic drives, optical drives, FLASH memory, EPROM, EEPROM, etc.) and dynamic (e.g., RAM, DRAM, SRAM, etc.), or any other non-transitory computer readable storage medium capable of storing instructions that cause the one or more processors to control non-predictable clock generator132(e.g., by controlling timing or other operational parameters) to perform the clock cycle length randomization techniques described in this disclosure. Thus, control unit210may represent hardware or a combination of hardware and software to support the below described components (e.g., non-predictable clock generator132), modules, elements, or operations.

FIG. 2Cis an illustration depicting an example of a console configured to randomize clock cycle lengths during a boot sequence in accordance with the techniques of the disclosure. In the example illustrated inFIG. 2C, non-predictable clock generator132is part of console106, instead of being implemented in HMD112as in the examples ofFIGS. 2A & 2B. Non-predictable clock generator132may implement the clock cycle length randomization operations described above with respect toFIGS. 2A & 2B, but in the context of console106, in the example ofFIG. 2C. As such, whether implemented within HMD112or within console106that provides decrypted content to HMD112or within another console, computing device, or peripheral device, non-predictable clock generator132may implement the clock cycle length randomization operations of this disclosure to increase the randomization of the timing of instruction execution, such as a boot sequence for whichever device includes non-predictable clock generator132. In this way, non-predictable clock generator132implements the techniques of this disclosure to, for instance, improve data security in a variety of configurations with which artificial reality systems10and20are compatible.

In the examples ofFIGS. 2A-2C, as described above with respect toFIGS. 1A & 1B, non-predictable clock generator132may be configured in accordance with aspects of this disclosure to use a random number generator to affect the lengths of clock cycles in a clock waveform that drives the timing of operations performed by processing circuitry of HMD112ofFIGS. 2A and 2Bor console106ofFIG. 2C. These techniques may be applied to reduce a likelihood of a successful compromise of secure boot sequences being executed by computing systems, including AR/VR computing systems, among other applications to improve the security of computing systems and of encryption operations generally.

A non-predictable clock generator132may be applied to drive operations within a co-processor or peripheral device for an HMD112, other artificial reality system, or other computing system. The co-processor or peripheral device may include an encryption engine having application-specific or other specialized logic for encryption operations. The co-processor or peripheral device may include a System-on-Chip (SoC) having an integrated hardware environment that executes an operating system and applications and include an instance of non-predictable clock generator132.

FIG. 3is a block diagram showing example implementations of a console and an HMD of the artificial reality systems ofFIGS. 1A & 1B. In this example, HMD112includes one or more processors302and memory304that, in some examples, provide a computer platform for executing an operating system305, which may be an embedded, real-time multitasking operating system, for instance, or other type of operating system. In turn, operating system305provides a multitasking operating environment for executing one or more software components307, including application engine340. As discussed with respect to the examples ofFIGS. 2A & 2B, processors302are coupled to electronic display203, motion sensors206and image capture devices134. In some examples, processors302and memory304may be separate, discrete components. In other examples, memory304may be on-chip memory collocated with processors302within a single integrated circuit.

In general, console106is a computing device that processes image and tracking information received from cameras102(FIG. 1B) and/or HMD112to perform motion detection, user interface generation, and various other artificial reality-related functionalities for HMD112. In some examples, console106is a single computing device, such as a workstation, a desktop computer, a laptop, or gaming system. In some examples, at least a portion of console106, such as processors312and/or memory314, may be distributed across a cloud computing system, a data center, or across a network, such as the Internet, another public or private communications network, for instance, broadband, cellular, WiFi®, and/or other types of communication networks for transmitting data between computing systems, servers, and computing devices.

In the example ofFIG. 3, console106includes one or more processors312and memory314that, in some examples, provide a computer platform for executing an operating system316, which may be an embedded, real-time multitasking operating system, for instance, or other type of operating system. In turn, operating system316provides a multitasking operating environment for executing one or more software components317. Processors312are coupled to one or more I/O interfaces315, which provides one or more I/O interfaces for communicating with external devices, such as a keyboard, game controllers, display devices, image capture devices, HMDs, and the like. Moreover, the one or more I/O interfaces315may include one or more wired or wireless network interface controllers (NICs) for communicating with a network, such as network104. Each of processors302,312may comprise any one or more of a multi-core processor, a controller, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), processing circuitry (e.g., fixed function circuitry or programmable circuitry or any combination thereof) or equivalent discrete or integrated logic circuitry. Memory304,314may comprise any form of memory for storing data and executable software instructions, such as random-access memory (RAM), read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electronically erasable programmable read only memory (EEPROM), and flash memory.

Software applications317of console106operate to provide an overall artificial reality application. In this example, software applications317include application engine320, rendering engine322, and pose tracker326. In general, application engine320includes functionality to provide and present an artificial reality application, e.g., a teleconference application, a gaming application, a navigation application, an educational application, training or simulation applications, and the like. Application engine320may include, for example, one or more software packages, software libraries, hardware drivers, and/or Application Program Interfaces (APIs) for implementing an artificial reality application on console106. Responsive to control by application engine320, rendering engine322generates 3D artificial reality content for display to the user by application engine340of HMD112.

Application engine320and rendering engine322construct the artificial content for display to user110in accordance with current pose information for a frame of reference, typically a viewing perspective of HMD112, as determined by pose tracker326. Based on the current viewing perspective, rendering engine322constructs the 3D, artificial reality content which may in some cases be overlaid, at least in part, upon the real-world 3D environment of user110. During this process, pose tracker326operates on sensed data received from HMD112, such as movement information and user commands, and, in some examples, data from any external sensors90(shown inFIGS. 1A & 1B), such as external cameras, to capture 3D information within the real-world environment, such as motion by user110and/or feature tracking information with respect to user110. Based on the sensed data, pose tracker326determines a current pose for the frame of reference of HMD112and, in accordance with the current pose, constructs the artificial reality content for communication, via the one or more I/O interfaces315, to HMD112for display to user110.

In the example ofFIG. 3, console106includes non-predictable clock generator132, which is described above with respect toFIGS. 1A-2B. For example, console106may receive an indication of a boot command. Non-predictable clock generator132may generate, using one or more random binary sequences generated by a random number generator, an output clock waveform having one or more clock cycles of randomized lengths. Processors312may then execute instructions according to the output clock waveform.

While defined as randomized, the output waveform may have the lengths of the one or more clock cycles with randomized lengths be bound by hardware constraints of processor312. For instance, if processor312is a 2 gigahertz (GHz) processor, then non-predictable clock generator132may bound the randomized adjustments to the clock cycle lengths such that the clock cycle length is not less than 0.5 nanoseconds (ns). Processor312may execute a boot sequence for operating system316of console106or other software operations using the output waveform generated by the clock randomization techniques described herein.

In one example implementation, a pseudo-random number generator (PRNG) may repeatedly output random binary sequences that are applied by non-predictable clock generator132to a clock waveform generated by a clock device to vary the length of clock cycles within the clock waveform to produce an output waveform. These clock waveforms may be produced by any of a number of devices, including a ring oscillator, an external oscillator, or a phase-locked loop (PLL). The clock waveform may have a fixed length clock cycle throughout the waveform. Non-predictable clock generator132may apply different random binary sequences to one or more clock cycles of the clock waveform to cause the one or more clock cycles in the output waveform to vary in length. To apply a random binary sequence, non-predictable clock generator132may frequency divide the frequency of different portions of the clock waveform by a value that is based on the random binary sequence to generate a corresponding portion of the output waveform, for instance. In general, a frequency divider takes an input signal of a frequency, fin, and generates an output signal of a frequency fout=fin,/n, wherein n is an integer.

As in this example implementation, to increase the non-determinism of the random binary sequences, the PRNG of non-predictable clock generator132is optionally seeded with seed information from a true random number generator (TRNG). The TRNG may be a local component to non-predictable clock generator132or a remote service, for instance. This seeding may occur at the start of each secure boot sequence or periodically, for instance.

In any of these examples, non-predictable clock generator132may alter the clock waveform such that the entirety of the output waveform has a uniform, albeit randomized, clock cycle length throughout the output waveform. In other instances, non-predictable clock generator132may alter different portions of the clock waveform with different parts of the random binary sequence such that different portions of the output waveform have different randomized lengths.

FIG. 4is a block diagram depicting an example implementation of an HMD of the artificial reality systems ofFIGS. 1A & 1B. In this example, as in the example ofFIG. 3, HMD112includes one or more processors302and memory304that, in some examples, provide a computer platform for executing an operating system305, which may be an embedded, real-time multitasking operating system, for instance, or other type of operating system. In turn, operating system305provides a multitasking operating environment for executing one or more software components417. Moreover, processor(s)302are coupled to electronic display203, motion sensors206, and image capture devices134. Operating system305may boot, at least in part, from boot ROM412.

In the example ofFIG. 4, software components417operate to provide an overall artificial reality application. In this example, software applications417include application engine440, rendering engine422, and pose tracker426. In various examples, software components417operate similar to the counterpart components of console106ofFIG. 3(e.g., application engine320, rendering engine322, and pose tracker326) to construct the artificial content for display to user110. In some examples, rendering engine422constructs the 3D, artificial reality content which may be overlaid, at least in part, upon the real-world, physical environment of user110.

In the example ofFIG. 4, HMD112includes non-predictable clock generator132, which is described above with respect toFIGS. 1A-3and generates, using one or more random binary sequences generated by a random number generator, an output clock waveform having one or more clock cycles of randomized lengths. Processors302may then execute the boot sequence by executing instructions according to the output clock waveform generated by the non-predictable clock generator132, which may increase the resilience of HMD112to attack.

While defined as randomized, the output waveform may have the lengths of the one or more clock cycles with randomized lengths be bound by hardware constraints of processors302. For instance, if processors302includes an 8 gigahertz (GHz) processor, then non-predictable clock generator132may bound the randomized adjustments to the clock cycle lengths such that the clock cycle length is not less than 0.125 nanoseconds (ns). Processor312may execute boot ROM412for operating system305of HMD112or other software operations using the output waveform generated by the clock randomization techniques described herein.

In one example implementation, a pseudo-random number generator (PRNG) may repeatedly output random binary sequences that are applied by non-predictable clock generator132to a clock waveform generated by a clock device to vary the length of clock cycles within the clock waveform to produce an output waveform. These clock waveforms may be produced by any of a number of devices, including a ring oscillator, an external oscillator, or a phase-locked loop (PLL). The clock waveform may have a fixed length clock cycle throughout the waveform. Non-predictable clock generator132may apply different random binary sequences to one or more clock cycles of the clock waveform to cause the one or more clock cycles in the output waveform to vary in length. To apply a random binary sequence, non-predictable clock generator132may frequency divide the frequency of different portions of the clock waveform by a value that is based on the random binary sequence to generate a corresponding portion of the output waveform, for instance. In general, a frequency divider takes an input signal of a frequency, fin, and generates an output signal of a frequency fout=fin,/n, wherein n is an integer.

As in this example implementation, to increase the non-determinism of the random binary sequences, the PRNG of non-predictable clock generator132is optionally seeded with seed information from a true random number generator (TRNG). The TRNG may be a local component to non-predictable clock generator132or a remote service, for instance. This seeding may occur at the start of each secure boot sequence or periodically, for instance.

In any of these examples, non-predictable clock generator132may alter the clock waveform such that the entirety of the output waveform has a uniform, albeit randomized, clock cycle length throughout the output waveform. In other instances, non-predictable clock generator132may alter different portions of the clock waveform with different parts of the random binary sequence such that different portions of the output waveform have different randomized lengths.

FIG. 5is a conceptual diagram illustrating an example implementation of a non-predictable clock generator132that randomizes one or more lengths of clock cycles for a output waveform509, in accordance with the techniques of the disclosure. Output waveform509is shown as an input clock waveform for secure logic510, which includes processing logic in the form of secure CPU512and encryption engines514. These techniques may be applied to reduce a likelihood of a successful compromise of the secure logic510, such as during secure boot sequence, where non-predictable clock generator132and secure logic510may be included in AR/VR computing systems, among other applications, to improve the security of computing systems and of encryption operations generally.

In the example ofFIG. 5, non-predictable clock generator132may obtain a random number as one or more random binary sequences generated using true random number generator (TRNG)502and generate, based at least in part on the random number, output waveform509having one or more clock cycles of randomized lengths. TRNG502may be a local component or a remote service, for instance. While defined as randomized, output waveform509may have the lengths of the one or more clock cycles with randomized lengths be bound by hardware constraints of secure CPU512. For instance, if secure CPU512is a 4 gigahertz (GHz) processor, then non-predictable clock generator132may bound the randomized adjustments to the clock cycle lengths such that the clock cycle length is not less than 0.25 nanoseconds (ns). Non-predictable clock generator132may also determine whether any artificial limits are placed on secure CPU512in the system's basic input/output system (BIOS), such as an underclocking or overclocking limit different from the manufacturer's recommended settings. If such an artificial limit exists in the system BIOS, non-predictable clock generator132may use the artificial limit in determining the bounds for the randomized clock cycle lengths.

Secure logic510includes one or more of secure CPU512and encryption engines514. Secure CPU512may execute a boot sequence for an operating system of the device that includes secure CPU512or other software operations using the output waveform509. Secure logic510may be part of a secure boot component for a computing system. Encryption engines514encrypt and decrypt data.

In this example implementation, pseudo-random number generator (PRNG)504repeatedly outputs random binary sequences that are applied by programmable clock divider508to a clock waveform507, generated by ring oscillator506, to vary the length of clock cycles within the clock waveform507to produce output waveform509. Clock waveform507may have a fixed length clock cycle throughout the waveform. Programmable clock divider508may apply different random binary sequences to one or more clock cycles of clock waveform507to cause the one or more clock cycles in the output waveform509to vary in length. To apply a random binary sequence, programmable clock divider508may frequency divide the frequency of different portions of clock waveform507by a value that is based on the random binary sequence to generate a corresponding portion of output waveform509, for instance. In general, a frequency divider takes an input signal of a frequency, fin, and generates an output signal of a frequency fout=fin,/n, wherein n is an integer.

As in this example implementation, to increase the non-determinism of the random binary sequences, PRNG504is optionally seeded with seed information from a true random number generator (TRNG). TRNG502may be a local component or a remote service, for instance. This seeding may occur at the start of each secure boot sequence or periodically, for instance. For example, a computing device may request seed information from a TRNG service and use the seed information to seed the PRNG504.

To further increase the randomness of the output clock waveform from the random clock generator, a ring oscillator506may generate the clock waveform507that is modified using the random binary sequences from PRNG504. An external oscillator or phase-locked loop (PLL), for example, may alternatively be used to generate the clock waveform507. In any of these examples, non-predictable clock generator132may alter clock waveform507such that the entirety of output waveform509has a uniform randomized clock cycle length throughout output waveform509. In other instances, non-predictable clock generator132may alter different portions of clock waveform507with different parts of the random binary sequence such that different portions of output waveform509have different randomized lengths.

The predictable nature of boot sequences makes computing systems vulnerable to malicious attacks, such as replay attacks, channel analysis, reset glitching, and laser pulsing when executing the boot sequences. In particular, replay attacks during the boot sequence rely on the predictability of the boot sequence process and clock timing during the boot sequence, enabling attackers to inject packets into the boot sequence at different times, representing different steps in the boot sequence, to instigate some sort of desired response. However, for replay attacks to be successful, the injections must occur at very specific times, or else the desired response will not be produced.

The output clock waveform generated by non-predictable clock generator132may be used to frustrate replay attacks or other attacks on a computing system and thereby increase the trustworthiness of the computing system. A replay attack exploits the predictable timing of operations executed by a computing device, such as during a secure boot sequence. By driving the timing of the operations using a clock waveform having randomly-generated cycle lengths, the timing of operations is no longer predictable and this reduces the likelihood that a replay attack will succeed. The output clock waveform as generated herein may also frustrate other types of attacks, such as channel analysis, reset glitching, laser pulsing, and so forth.

When a chip having logic driven by an output waveform from non-predictable clock generator132boots, each operation performed by the chip now occurs at a time that is no longer predictable, which brings at least two benefits. First, the number of repetitions that the attacker must run increases by orders of magnitude, because the knowledge that the attack failed at a certain point in time does not give any additional information. In other words, the next time the sequence restarts, the chip will be doing a completely different operation at the same point in time. The variability increases as the length of the operation that needs to be protected increases. Second, even if the attacker were to be able to execute the attack successfully once, the attacker would not be able to replay the attack because the attacker would not be able to predict when the same operation will happen at the next execution.

The randomized clock cycle length techniques described herein may present advantages over other techniques for modifying clock cycle lengths. For example, spread spectrum clocking techniques modulate the clock frequency to address electromagnetic interference. However, spread spectrum clock frequency modulation may still leave the system vulnerable to attack during the secure boot sequence. The techniques described herein, in contrast to spread spectrum clocking, offer a technical improvement of randomizing the clock cycle lengths using a random number generator that, at least in some cases, does not output values that conform to a known distribution and are therefore more truly random. In some cases, because the techniques rely on clock division, the time taken to perform the boot sequence may be increased, but this increase provides the practical application of improving the overall security of the boot sequence.

FIGS. 6A and 6Bare conceptual diagrams of example output waveforms that have randomized clock cycle lengths in accordance with the techniques of the disclosure. In the examples ofFIGS. 6A and 6B, non-predictable clock generator132may be similar to non-predictable clock generator132as described in any ofFIGS. 1A-5, and may perform the clock cycle length randomization described throughout this disclosure. Similarly, central processing unit (CPU)604may be similar to processors302,312, and512ofFIGS. 3-5, respectively, and may execute instructions in accordance with an output waveform generated by non-predictable clock generator132where the output waveform has one or more randomized frequencies that affect the clock cycle length of CPU604.

In the examples ofFIGS. 6A and 6B, the output waveforms generated by non-predictable clock generator132are represented by waveforms606and608A-608E (collectively, waveform608). Waveforms606and608drive execution of machine instructions by CPU604. The machine instructions may form at least part of a sequence of operations (e.g., the boot sequence). For instance, at each initial spike in clock waveforms606and608, upon receipt of that portion of waveforms606and608, CPU604may execute the next instruction in the sequence of operations. In instances where CPU604may execute multiple instructions in parallel, CPU604may execute the next group of instructions at the receipt of each initial spike in clock waveforms606and608.

In the example ofFIG. 6A, non-predictable clock generator132alters a default clock waveform to produce waveform606that has a random, but uniform, frequency throughout the transmission of waveform606. For instance, initially, a default clock waveform may have a particular clock cycle length, potentially similar to the recommended limit for the particular model of CPU604. Non-predictable clock generator132may use the random binary sequence to alter the default clock waveform to generate output waveform606. The default clock waveform may be input to non-predictable clock generator132or generated by non-predictable clock generator132. In the example ofFIG. 6A, the default clock waveform may have clock cycle lengths of 0.5 ns that cause CPU604to execute instructions at a corresponding rate. Non-predictable clock generator132may randomly alter the default clock waveform to be output waveform606, which may have clock cycle lengths of 0.63 ns and cause CPU604to execute an instruction at a slower pace than would the default waveform would.

In the example ofFIG. 6B, non-predictable clock generator132alters different portions of a default clock waveform to produce waveform608that has multiple different, random frequencies at different points along waveform608. For instance, initially, a default clock waveform may have a particular clock cycle length, potentially similar to the recommended limit for the particular model of CPU604, such as 0.25 ns. Non-predictable clock generator132may use the random binary sequence to alter the default clock waveform at different times using different binary sequences to arrive at output waveform608.

For instance, non-predictable clock generator132may use a first segment of the random binary sequence to alter the length of the clock cycles for a first segment of the default clock waveform to produce first segment608A of output waveform608. If the minimum clock cycle length of CPU604, as defined by the manufacturer's recommended clock length, is 0.25 ns, first segment608A may have a smaller frequency, such as 0.5 ns. Each segment of the random binary sequence may be an n-bit values used by a clock divider to divide the default clock waveform, meaning that each segment may have a length that is some integer multiple of the manufacturer's recommended clock length.

Non-predictable clock generator132may repeat this process for a second, third, fourth, and fifth segment of the random binary sequence, altering different segments of the default clock waveform to produce segments608B,608C,608D, and608E. As such, when CPU604is executing instructions in a sequence of operations, such as a boot sequence, the clock cycles of CPU604may have different lengths throughout the sequence. For instance, if segment608A has a clock cycle length of 0.5 ns, segment608B may increase the timing even further, such as to 0.6 ns. When CPU604receives segment608C of the output waveform, CPU604may decrease the time for the clock cycles to 0.25 ns. CPU604may then significantly increase the time length for the clock cycles upon receiving segment608D, such as to 3.75 ns. Finally, CPU604may decrease the time length for the clock cycles upon receiving segment608E, such as to 1 ns. Non-predictable clock generator132may apply modifications to the output clock waveform out of step with the frequency of the output clock waveform. Non-predicable clock generator132may alter the frequency of output clock waveform periodically or at semi-random times.

The predictable nature of boot sequences makes computing systems vulnerable to malicious attacks, such as replay attacks, channel analysis, reset glitching, and laser pulsing when executing the boot sequences. In particular, replay attacks during the boot sequence rely on the predictability of the boot sequence process and clock timing during the boot sequence, enabling attackers to inject packets into the boot sequence at different times, representing different steps in the boot sequence, to instigate some sort of desired response. However, for replay attacks to be successful, the injections must occur at very specific times, or else the desired response will not be produced.

The output clock waveform generated by non-predictable clock generator132may be used to frustrate replay attacks or other attacks on a computing system and thereby increase the trustworthiness of the computing system. A replay attack exploits the predictable timing of operations executed by a computing device, such as during a secure boot sequence. By driving the timing of the operations using a clock waveform having randomly-generated cycle lengths, the timing of operations is no longer predictable and this reduces the likelihood that a replay attack will succeed. The output clock waveform as generated herein may also frustrate other types of attacks, such as channel analysis, reset glitching, laser pulsing, and so forth.

When a chip having logic driven by an output waveform from non-predictable clock generator132boots, each operation performed by the chip now occurs at a time that is no longer predictable, which brings at least two benefits. First, the number of repetitions that the attacker must run increases by orders of magnitude, because the knowledge that the attack failed at a certain point in time does not give any additional information. In other words, the next time the sequence restarts, the chip will be doing a completely different operation at the same point in time. The variability increases as the length of the operation that needs to be protected increases. Second, even if the attacker were to be able to execute the attack successfully once, the attacker would not be able to replay the attack because the attacker would not be able to predict when the same operation will happen at the next execution.

FIG. 7is a flowchart illustrating an example process by which artificial reality systems10&20utilize non-predictable clock generator132to decrypt and render encrypted artificial reality content. The process is described herein as being performed by artificial reality system10and components thereof, such as HMD112as an example, although it will be appreciated that other systems and components of this disclosure may perform the process as well, in accordance with aspects of this disclosure. According to the process ofFIG. 7, non-predictable clock generator132receives an indication of a boot command (702). Non-predictable clock generator132generates a random number using a true random number generator (704). Non-predictable clock generator132generates, based at least in part on the random number, an output clock waveform having at least a length of a clock cycle for a processor of HMD112(706). Non-predictable clock generator132continues generating the output clock waveform based on the random number (706) until the non-predicable clock generator132generators a new random number (704) and generates the output clock waveform based on the new random number (706). The processor of HMD112executes a boot sequence for at least a component of HMD112using the output clock waveform (708).