User device having a host flash translation layer (FTL), a method for transferring an erase count thereof, a method for transferring reprogram information thereof, and a method for transferring a page offset of an open block thereof

A user device includes a storage device including a flash memory; and a host connected to the storage device via an interface and adapted to transmit data to the storage device. The host provides the storage device with erase count information of the flash memory using a host flash translation layer (FTL), provides the storage device with reprogram information when the flash memory uses a reprogram method, or provides the storage device with page offset information of an open block of the flash memory.

TECHNICAL FIELD

The inventive concept described herein relates to a user device, and more particularly, to an erase count transferring method, a reprogram information transferring method, and a method of transferring a page offset of an open block, in a user device having a host flash translation layer.

DISCUSSION OF RELATED ART

A storage system may consist of a host and a storage device. The host and the storage device may be connected through various standardized interfaces such as a serial advanced technology attachment (SATA), universal flash storage (UFS), a small computer system interface (SCSI), a serial attached SCSI (SAS), an embedded multi-media card (eMMC), and so on.

The storage device may include nonvolatile memories such as flash memory, magnetoresistive random access memory (MRAM), phase-change RAM (PRAM), ferroelectric RAM (FeRAM), and so on. A flash memory-based storage device may use a flash translation layer (FTL).

As a characteristic is lowered due to shrinkage of the storage device, a variety of schemes have been developed to ensure the reliability of the storage device. In particular, a user device in which a host manages the FTL has been used to provide the storage device with information necessary to improve its performance and ensure its reliability.

SUMMARY

An exemplary embodiment of the inventive concept provides a user device which comprises a storage device including a flash memory; and a host connected to the storage device via an interface and adapted to transmit data to the storage device. The host provides the storage device with erase count information of the flash memory using a host flash translation layer (FTL), provides the storage device with reprogram information when the flash memory uses a reprogram method, or provides the storage device with page offset information of an open block of the flash memory.

In an exemplary embodiment of the inventive concept, the flash memory includes a plurality of memory blocks, and the erase count information is a max erase count of erase counts of the memory blocks. The host provides the storage device with the erase count information of the flash memory periodically. The host provides the storage device with the erase count information of the flash memory when the storage device is booted up.

In an exemplary embodiment of the inventive concept, the storage device adjusts a read level of the flash memory using the erase count information. The flash memory includes a plurality of block types, and wherein the erase count information is a max erase count of each block type.

In an exemplary embodiment of the inventive concept, the host provides the storage device with the reprogram information using a program command field format. The program command field format includes a storage address format. The reprogram information is included in the storage address format.

In an exemplary embodiment of the inventive concept, the host provides the storage device with the page offset information of the open block when a specific condition is satisfied.

In an exemplary embodiment of the inventive concept, the specific condition includes a condition in which a read-target block is an open block and a read operation is first performed after the user device is initialized, a condition in which a read-target block is an open block and a memory block is changed in the same concurrently addressable unit (CAU), or a condition in which a read-target block is an open block and a page offset of the read-target block is changed.

In an exemplary embodiment of the inventive concept, a memory cell array of the flash memory has a three-dimensional structure in which cell strings are formed in a direction perpendicular to a substrate.

An exemplary embodiment of the inventive concept provides an erase count transferring method of a user device which includes a storage device including a flash memory; and a host connected to the storage device via an interface and adapted to drive a host FTL, the erase count transferring method comprising transferring, from the host, a setting command mark to setup the storage device for a transfer of an erase count; sending, from the host, a setting erase count corresponding to a storage address format; transmitting, from the storage device, erase count data including an erase count of the flash memory; and sending, from the host, a setting command end mark for ending a command setting.

In an exemplary embodiment of the inventive concept, the erase count is a max erase count of erase counts of memory blocks in the flash memory. The host provides the erase count of the flash memory periodically or when the storage device is booted up. The storage device adjusts a read level of the flash memory using the erase count. The flash memory includes a plurality of block types, and wherein the erase count is a max erase count of each block type.

An exemplary embodiment of the inventive concept provides a reprogram information transferring method of a user device which includes a storage device including a flash memory; and a host connected to the storage device via an interface and adapted to drive a host FTL. The reprogram information transferring method including transferring, from the host, a program mark for indicating a transfer of information for a write operation; sending, from the host, a storage address format for designating a storage location of program data in the flash memory; and transmitting, from the host, a program end mark for reporting a program end. The host provides reprogram information to the storage device when the flash memory uses a reprogram method.

In an exemplary embodiment of the inventive concept, the host provides the storage device with the reprogram information using a program hint command field format. The program hint command field format includes a storage address format. The reprogram information is included in the storage address format.

The program hint command field format is provided to the storage device prior to a transfer of a program command. The program hint command field format is formed of a program hint mark, a storage address format, and a program hint end mark. The program hint command field format does not include program data.

An exemplary embodiment of the inventive concept provides a method of transferring a page offset of an open block in a user device which includes a storage device including a flash memory; and a host connected to the storage device via an interface. The method includes providing, from the host, page offset information of an open block when a specific condition is satisfied; and providing, from the host, a read command to the storage device after the page offset information of the open block is provided.

In an exemplary embodiment of the inventive concept, the specific condition includes a condition in which a read-target block is an open block and a read operation is first performed after the user device is initialized, a condition in which a read-target block is an open block and a memory block is changed in the same CAU, or a condition in which a read-target block is an open block and a page offset of the read-target block is changed.

In an exemplary embodiment of the inventive concept, a page offset command field format of the open block includes a read command mark, a storage address format, and a read command end mark. The storage address format includes a read hint area and a page offset area, and the page offset command field format and a read command field format are determined by the read hint area. The host includes a buffer random access memory (RAM) for driving a host FTL.

In an exemplary embodiment of the inventive concept, there is provided a device including a host including a translation layer; and a storage device including a nonvolatile memory. The host provides erase count information of a memory block in the nonvolatile memory to the storage device, reprogram information to the storage device, or information about available space in the nonvolatile memory to the storage device.

The reprogram information is included in a storage address format area of a command field.

The information about available space in the nonvolatile memory is included in a storage address format area of a command field.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. The inventive concept, however, may be embodied in various different forms, and should not be construed as being limited only to the illustrated embodiments. Unless otherwise noted, like reference numerals denote like elements throughout the attached drawings and written description, and thus descriptions will not be repeated. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity.

It will be understood that when an element or layer is referred to as being “on”, “connected to”, “coupled to”, or “adjacent to” another element or layer, it can be directly on, connected, coupled, or adjacent to the other element or layer, or intervening elements or layers may be present.FIG. 1is a block diagram illustrating a user device according to an exemplary embodiment of the inventive concept. Referring toFIG. 1, a user device1000may comprise a host1100and a storage device1200. The host1100and the storage device1200may be connected through a variety of standardized interfaces such as a serial advanced technology attachment (SATA), universal flash storage (UFS), a small computer system interface (SCSI), a serial attached SCSI (SAS), an embedded multi-media card (eMMC), and so on.

As illustrated inFIG. 1, a host interface1101and a device interface1201may be connected through data lines DIN and DOUT for exchanging data or signals and a power line PWR for providing a power. The host1100may include an application1110, a device driver1120, a host controller1130, and a buffer memory1140.

The application1110may be various application programs to be executed by the host1100. The device driver1120may drive peripheral devices that are used through connection with the host1100, and it may drive the storage device1200, for example. The application1110or the device driver1120may be implemented by software or firmware. The host controller1130may exchange data with the storage device1200through the host interface1101.

The buffer memory1140may be used as a main memory or a cache memory of the host1100. In addition, the buffer memory1140may be used as a driving memory for driving software, such as the application1110or the device driver1120, or firmware such as a host flash translation layer (FTL).

The storage device1200may be connected to the host1100through the device interface1201. The storage device1200may include a nonvolatile memory1210, a device controller1230, and a buffer memory1240. The nonvolatile memory1210may include, but is not limited to, flash memory, magnetoresistive random access memory (MRAM), phase-change RAM (PRAM), ferroelectric (FeRAM), and so on. The device controller1230may control an overall operation of the nonvolatile memory1210including a write operation, a read operation, an erase operation, and so on. The device controller1230may exchange data with the nonvolatile memory1210or the buffer memory1240through an address or data bus,

The buffer memory1240may be used to temporarily store data read from the nonvolatile memory1210or data to be written to the nonvolatile memory1210. The buffer memory1240may be implemented with a volatile memory or a nonvolatile memory. The buffer memory1240may be used as a main memory or a cache memory of the storage device1200.

In addition, the buffer memory1240may be used as a driving memory for driving software or firmware such as a command manager, a flash manager, an error fix manager, and so on.

FIG. 2is a block diagram illustrating a flash memory-based user device according to an exemplary embodiment of the inventive concept. A user device2000shown inFIG. 2may be a mobile device, such as a smart phone, a tablet personal computer (PC), an e-book, a mobile phone, and so on. Referring toFIG. 2, the user device2000includes a host2100and a storage device2200.

The host2100may include an application2110, a device driver2120, a host controller2130, and a buffer RAM2140, The host controller2130may include a command queue2131, a host direct memory access (DMA)2132, and a power manager2133.

A command (e.g., a write command) generated by the application2110and the device driver2120in the host2100may be provided to the command queue2131of the host controller2130. The command queue2131may sequentially store commands to be provided to the storage device2200. The commands stored in the command queue2131may be provided to the host DMA2132. The host DMA2132may send the commands to the storage device2200through a host interface2101. The host interface2101may include a physical layer and a link layer.

The storage device2200may include a flash memory2210, a device controller2230, and a buffer RAM2240. The device controller2230may include a central processing unit (CPU)2231, a device DMA2232, a flash DMA2233, a command manager2234, a buffer manager2235, an error fix manager2236, and a flash manager2237.

A command transferred from the host2100to the storage device2200may be provided to the device DMA2232through a device interface2201. The device interface2201may include a physical layer and a link layer. The device DMA2232transfers the input command to the command manager2234. The command manager2234is a module that analyzes a command received from the host2100and converts the command to be suitable for transmission to the flash memory2210. In addition, the command manager2234allocates the buffer RAM2240to receive data through the buffer manager2235. If there is ready to transfer data, the command manager2234may send a transmission ready complete signal READY_TO_TRANSFER to the host2100.

The host2100may send data to the storage device2200in response to the transmission ready complete signal READY_TO_TRANSFER. The data may be sent to the storage device2200through the host DMA2132and the host interface2101. The storage device2200may store the received data in the buffer RAM2240through the device DMA2232and the buffer manager2235. The data stored in the buffer RAM2240may be provided to the flash manger2237through the flash DMA2233. The flash manager2237may store data at an address of the flash memory2210.

If a data transfer operation and a program operation associated with a command are completed, the storage device2200may send a response signal to the host2100through an interface and may inform the host2100that the operations associated with the command are completed. Based on the response signal, the host2100may inform the device driver2120and the application2110whether the operations associated with the command are completed and terminate any operations remaining for that command.

FIG. 3is a block diagram illustrating a flash memory device shown inFIG. 2, according to an exemplary embodiment of the inventive concept. Referring toFIG. 3, a flash memory2210includes a memory cell array110, a data input/output circuit120, an address decoder130, and control logic140.

The memory cell array110contains a plurality of memory blocks BLK1to BLKn, each of which is formed of a plurality of pages. Each page may be formed of a plurality of memory cells. The flash memory2210performs an erase operation by the memory block and a write or a read operation by the page.

Each memory cell that stores one data bit may be named a single level cell or a single bit cell. Each memory cell that stores two or more data bits may be named a multi-level cell or a multi-bit cell.

The single level cell may have an erase state or a program state based on its threshold voltage. The multi-level cell may have one of an erase state and a plurality of program states based on its threshold voltage. The flash memory2210may include both the single level cells and multi-level cells.

The data input/output circuit120is connected with the memory cell array110through a plurality of bit lines BLs. The data input/output circuit120receives data DATA from an external device and transfers program data to a selected page111. At a read operation, the data input/output circuit120reads data from the selected page111to output it to the external device.

The address decoder130is connected with the memory cell array110through a plurality of word lines WLs, a string selection line SSL and a ground selection line GSL. The address decoder130selects a memory block or a page in response to an address ADDR. Here, an address for selecting a memory block may be named a block address, and an address for selecting a page may be named a page address. Below, it is assumed that one page111of a first memory block BLK1is selected.

The control logic140may control programming, erasing, and reading of the flash memory1000. For example, at programming, the control logic140may control the address decoder130such that a program voltage is supplied to a selected word line and the data input/output circuit120such that data is programmed at the selected page111. The control logic140controls programming, erasing, and reading of the flash memory1000based on a control signal CTRL from the device controller2230(refer toFIG. 2). The control logic140may receive a corresponding command CMD from the device controller2230(refer toFIG. 2).

FIG. 4is a circuit diagram illustrating a memory block shown inFIG. 3, according to an exemplary embodiment of the inventive concept. Referring toFIG. 4, a memory block BLK1may be of a cell string structure. A cell string includes a string selection transistor connected to a string selection line SSL, memory cells connected to word lines WL1to WLn, and a ground selection transistor connected to a ground selection line GSL. The string selection transistors are connected to bit lines BL1to BLm, and the ground selection transistors are connected to a common source line CSL.

InFIG. 4, a selected page111may experience simultaneous programming. A page may be divided into a main area for storing main data and a spare area for storing additional data such as parity bits.

FIG. 5is a diagram illustrating a threshold voltage distribution of memory cells shown inFIG. 4, according to an exemplary embodiment of the inventive concept.FIG. 5shows a threshold voltage distribution of memory cells each of which stores 2-bit data. InFIG. 5, the abscissa represents a threshold voltage Vth, and the ordinate represents the number of memory cells. A memory cell may have one of four states E, P1, P2, and P3according to its threshold voltage. InFIG. 5, “E” represents an erase state, and “P1”, “P2”, and “P3” represent program states.

FIG. 6is a diagram illustrating a command field format of a user device shown inFIG. 2, according to an exemplary embodiment of the inventive concept. A command field format is an interfacing standard that allows information to be exchanged between a host interface2101of a host2100and a device interface2201of a storage device2200.

InFIG. 6, there are illustrated a program command field format for writing data at the storage device2200and a read command field format for reading data from the storage device2200.

Referring toFIG. 6, the host2100sends the storage device2200a program mark indicating a transfer of information for writing. After sending the program mark, the host2100sends a storage address format for designating a storage location of program data. The host2100transfers a program end mark indicating a program end after transmitting the program data. The storage device2200performs a program operation during a wait busy period.

As illustrated inFIG. 6, host2100sends the storage device2200a read command mark indicating a transfer of information for reading. After sending the read command mark, the host2100sends a storage address format for designating a storage location of data and a read command end mark indicating a program end after transmitting the program data.

After the read command end mark is sent, the storage device2200performs a read operation during a wait busy period. If the read operation ends, the host2100transfers a data out mark and the storage device2200outputs data to the host2100.

Returning to FIG,2, in the user device2000according to an exemplary embodiment of the inventive concept, the storage device2200contains the error fix manager2236, and an FTL is driven on the buffer RAM2140of the host2100. Since the user device2000shown inFIG. 2drives the FTL on the host2100, the storage device2200is provided with a variety of information that influences performance of the flash memory2210.

If a flash memory-based storage device does not have erase count information about memory blocks, it may operate under a condition that a characteristic of the storage device is worse case.

Thus, in an exemplary embodiment of the inventive concept, erase count information of a memory block may be sent from the host2100to the storage device2200, thereby improving performance of the storage device2200and ensuring reliability.

FIGS. 7 and 8are detailed diagrams of a read command field format and a program command field format shown inFIG. 6, according to an exemplary embodiment of the inventive concept. Referring toFIGS. 7 and 8, a storage address format may be formed of, for example, 32 bits.

An unused area of the storage address format may be formed of “X” bits. A cell type area of the storage address format may be used to indicate whether a read or a write operation is performed with any cell type (e.g., a single level cell (SLC) or a multilevel cell (MLC)) and may be formed of “A” bits. A concurrently addressable unit (CAU) area of the storage address format may be used to designate a data storage location of an upper level such as a chip, a die, or a plane and may be formed of “B” bits. A block area of the storage address format may be used to designate a block number in a CAU and may be formed of “C” bits. A page area of the storage address format may be used to designate a page number in a block and may be formed of “D” bits. In the above-described example, the storage address format may be formed of 32 bits corresponding to a sum of “X” bits and “A” to “C” bits.

FIG. 9is a block diagram illustrating a memory cell array of a flash memory shown inFIG. 3, according to an exemplary embodiment of the inventive concept. Referring toFIG. 9, the memory cell array may include a plurality of block types. In the example ofFIG. 9, a first block type may be a tri-level cell (TLC) block that stores 3 bits per memory cell, and a second block type may be an SLC block that stores one bit per memory cell.

Data that is to be programmed at a memory block with the first block type (e.g., TLC block) may be stored in a memory block with the second block type (e.g., SLC block). Next, there may be performed an operation of moving data from the second block type to the first block type. This operation may be referred to as an on-chip buffered program operation.

Referring to FIG,9, the second block type includes first to fourth memory blocks BLK1to BLK4, and the first block type includes fifth to eighth memory blocks BLK5to BLK8. Each memory block may have an erase count EC.

For example, erase counts of the first to fourth memory blocks BLK1to BLK4may be80,60,100, and90, respectively. A max erase count of an SLC block may be an erase count of the third memory block BLK3:100. Erase counts of the fifth to eighth memory blocks BLK5to BLK8may be450,521,510, and490, respectively. A max erase count of a TLC block may be an erase count of the sixth memory block BLK6:521.

When the flash memory2210(refer toFIG. 3) iterates a program-erase operation, a characteristic of a threshold voltage distribution may get worse due to deterioration of memory cells. For example, a read fail may arise when a threshold voltage distribution of the memory cells varies. For this reason, a permissible limit of a program-erase (PIE) operation for the flash memory2210may be determined. This may be referred to as P/E cycle endurance, The P/E cycle endurance may vary with the number of data bits stored in a memory cell. In general, as the number of data bits stored in a memory cell decreases, the more the P/E cycle endurance increases.

The user device2000(refer toFIG. 2) may manage erase counts of memory blocks using the host FTL2140of the host2100(refer toFIG. 2). The user device2000may provide erase count information of each memory block to the storage device2200from the host2100, thereby improving performance of the storage device2200and elongating its lifetime.

For example, the storage device2200may adjust a read voltage level of the flash memory2210based on erase count information received from the host2100. The storage device2200may cope with a variation in a threshold voltage due to the deterioration of its memory cells by adjusting a read voltage level of the flash memory2210according to an erase count. In other words, using the erase count, the storage device2200may reduce a read fail of the flash memory2210and elongate the lifetime of the flash memory2210.

FIG. 10is a diagram for describing a method for transferring an erase count of a user device according to an exemplary embodiment of the inventive concept. InFIG. 10, there is illustrated an erase count command field format that allows a host2100to transfer an erase count to a storage device2200. Information is exchanged between a host interface2101of the host2100and a device interface2201of the storage device2200.

Here, the host2100transfers the storage device2200a setting command mark indicating it is time to set the storage device2200to receive an erase count. A setting erase count corresponding to a storage address format is send following a transfer of the setting command mark. Following a transfer of the setting erase count, a max erase count is transmitted which includes max erase counts of first and second block types (refer toFIG. 9). Then, there is sent a setting command end mark representing that command setting is terminated.

As illustrated inFIG. 10, erase count data may contain first to fourth data W1to W4including the max erase count of the first block type and fifth to eighth data W5to W8including the max erase count of the second block type. Here, the first block type may mean a TLC block, and the second block type may mean an SLC block.

FIG. 11is a diagram for describing an erase count transferring method shown inFIG. 10, according to an exemplary embodiment of the inventive concept. Sending a setting erase count corresponding to a storage address format after a transfer of a setting command mark, the host2100may transmit max erase counts corresponding to two block types. InFIG. 11, a max erase count for a TLC block is 521, and a max erase count for an SLC block is 100.

The host2100sends a device status check command mark for checking a status of the storage device2200after sending a setting command end mark. Then, the host2100checks completion of an erase count transfer operation.

In the user device2000according to an exemplary embodiment of the inventive concept, the host2100sends a max erase count to the storage device2200. An erase count may be iteratively transmitted with a constant period (e.g., 100 times). For example, the host2100may transmit a max erase count to the storage device2200when a max erase count of the SLC block reaches 200 or a max erase count of the TLC block reaches621. An erase count may be transmitted when the storage device2200is booted up.

In the user device2000according to an exemplary embodiment of the inventive concept, the host2100manages the FTL and sends an erase count to the storage device2200according to a specific condition (e.g., a constant period or boot-up). The erase count may be a max erase count of a memory block. In addition, in the case a plurality of block types are provided, the erase count may include max erase counts of respective block types. The storage device2200may improve program/read performance of the flash memory2210using an erase count transferred from the host2100.

In an exemplary embodiment of the inventive concept, reprogram information may be sent from a host to a storage device, thereby improving performance of the storage device and ensuring reliability.

FIGS. 12 and 13are diagrams illustrating a program method of a flash memory, according to an exemplary embodiment of the inventive concept.FIG. 12shows program states of a flash memory in which 3-bit data is stored in a memory cell. A flash memory may have eight threshold voltage distributions by performing program operations three times.

A program method shown inFIG. 12may be a shadow program method that requires a program operation to be performed on a page once, and a program method shown inFIG. 13may be a reprogram method that requires a program operation to be performed on a page in plural. InFIGS. 12 and 13, the half ovals correspond to threshold voltage distributions.

Referring toFIG. 12, in the shadow program method, a first program state may be achieved from an erase state via a first program operation, and a characteristic of data corresponding to the first program state may be ensured, When a second program state is achieved from the first program state via a second program operation, a characteristic of data corresponding to the second program state may also be ensured. A third program state may be obtained via a third program operation. At this time, eight threshold voltage distributions may be formed.

Referring toFIG. 13, in the reprogram method, characteristics of data corresponding to first and second program states may not be ensured. This can be gleaned from the overlapping threshold voltage distributions in the second program state, for example. In other words, the flash memory2210(refer toFIG. 2) using the reprogram method has to perform a plurality of program operations on a page to ensure a characteristic of data. Since a program operation on the same page is iterated in the reprogram method, the storage device2200(refer toFIG. 2) manages the number of program operations executed.

In the user device2000(refer toFIG. 2) according to an exemplary embodiment of the inventive concept, the host2100(refer toFIG. 2) may provide the storage device2200with reprogram information when the flash memory2210is programmed using the reprogram method.

FIG. 14is a detailed diagram of a storage address format of a program command field format shown inFIGS. 6 and 8, according to an exemplary embodiment of the inventive concept.

Referring toFIG. 8, a storage address format may be formed of, for example, 32 bits.

An unused area of the storage address format may be formed of “X” bits. A cell type area of the storage address format may be used to indicate whether a read or a write operation is performed with any cell type (e.g., SLC or MLC) and may be formed of “A” bits. A CAU area of the storage address format may be used to designate a data storage location of an upper level such as a chip, a die, or a plane and may be formed of “B” bits. A block area of the storage address format may be used to designate a block number in a CAU and may be formed of “C” bits. A page area of the storage address format may be used to designate a page number in a block and may be formed of “D” bits. In the above-described example, the storage address format may be formed of 32 bits corresponding to a sum of “X” bits and “A” to “C” bits.

Referring toFIG. 14, the user device2000(refer toFIG. 2) transfers reprogram information using a program command field format shown inFIG. 8. A program command field format for transmitting reprogram information is illustrated inFIG. 14. The reprogram information may be included in a storage address format. In other words, the storage address format may contain a reprogram information area as a separate area for transferring reprogram information.

Referring toFIG. 14, the reprogram information area of the storage address format may use “Y” bits of the “X” bits of the unused area of the storage address format. In this case, the unused area of the storage address format may be formed of (X−Y) bits, and the reprogram information area of the storage address format may be formed of “Y” bits. A cell type area of the storage address format may be formed of “A” bits, a CAU area of the storage address format may be formed of “B” bits, a block area of the storage address format may be formed of “C” bits, and a page area of the storage address format may be formed of “D” bits.

FIGS. 15 and 16are diagrams for describing a reprogram information transferring method shown inFIG. 14, according to an exemplary embodiment of the inventive concept. The host2100sends a program command field format in which a reprogram information area of a storage address format is set with “Y” bits.

Referring toFIG. 15, a first program (1stPGM) operation may be performed when the reprogram information area is set to “00h”, a second program operation (2ndPGM) may be performed when the reprogram information area is set to “04h”, and a third program operation (3rdPGM) may be performed when the reprogram information area is set to “08h”.

FIG. 16shows a table of page addresses and program orders. Referring toFIGS. 15 and 16, a first program operation (program order 3 inFIG. 16) about WL2may be performed. The word line WL2may have page addresses of 06h, 07h, and 08h as illustrated inFIGS. 15 and 16. After the first program operation about WL2is performed, a second program operation (program order4inFIG. 16) about WL1may be performed. The word line WL1may have page addresses of 03h, 04h, and 05h as illustrated inFIGS. 15 and 16. After the second program operation about WL1is performed, a third program operation (program order 5 inFIG. 16) about WL0may be performed. The word line WL0may have page addresses of 00h, 01h, and 02h as illustrated inFIGS. 15 and 16. LSB, CSB and MSB inFIG. 16correspond to least significant bit, center significant bit and most significant bit, respectively.

FIG. 17is a diagram illustrating a reprogram information transferring method of a user device, according to an exemplary embodiment of the inventive concept. The user device2000(refer toFIG. 2) may send reprogram information using a program hint command field format.

Prior to a transfer of a program command, the user device2000sends a program hint command to transmit a program address from a host2100to a storage device2200. The program hint command may enable the storage device2200to grasp program information prior to the transference of the program command, thereby improving program performance. Information is exchanged between a host interface2101of the host2100and a device interface2201of the storage device2200.

A program hint command field format for transferring reprogram information is illustrated inFIG. 17. Referring toFIG. 17, the program hint command field format contains a program hint mark, a storage address format, and a program hint end mark. The program hint command field format does not include program data.

The reprogram information may be included in the storage address format. A first program operation may be carried out when a reprogram information area of the storage address format is set to 00h, a second program operation may be carried out when the reprogram information area of the storage address format is set to 04h, and a third program operation may be carried out when the reprogram information area of the storage address format is set to 08h. As illustrated inFIG. 15, a program order is: WL2→WL1→WL0. A word line WL2has page addresses of 06h, 07h, and 08h, a word line WL1has page addresses of 03h, 04h, and 05h, and a word line WL0has page addresses of 00h, 01h, and 02h.

When the user device2000according to an exemplary embodiment of the inventive concept manages an FTL on the host2100and uses a reprogram method, reprogram information may be transferred from the host2100to the storage device2200. The reprogram information may be included in a program command field format or in a storage address format of a program command field format. The storage device2200may improve performance of a program operation using reprogram information from the host2100.

In an exemplary embodiment of the inventive concept, a page offset of an open block may be transferred from a host to a storage device, thereby improving performance of the storage device and ensuring reliability.

FIG. 18is a diagram for describing an open block of a flash memory shown inFIG. 3, according to an exemplary embodiment of the inventive concept. A program operation of a memory block may be ended before its storage space is fully filled with data. This memory block may be referred to as an open block. An empty storage space of the memory block may be programmed with data later.

Referring toFIG. 18, a memory block is formed of 64 pages. 1stto 5thpages are pages that are programmed, and 6thto 64thpages are pages that are not programmed. The 5thpage may be a page that is last programmed. A page offset may mean a number of the last programmed page. InFIG. 18, the page offset may be the 5thpage.

FIG. 19is a diagram for describing a method of transferring a page offset of an open block in a user device, according to an exemplary embodiment of the inventive concept. A page offset command field format for transferring a page offset of an open block is illustrated inFIG. 19.

A host2100transfers a page offset of an open block to a storage device2200using a host FTL. Using the page offset of the open block, the storage device2200improves program/read performance and ensures reliability of data. Information is exchanged between a host interface2101of the host2100and a device interface2201of the storage device2200.

Prior to a transfer of a command field format for a read, the host2100sends read hint information to the storage device2200using a page offset command field format. The read hint information may contain page offset information about a memory block to be read. The page offset command field format need not be provided when a read operation is requested. For example, the page offset command field format may be provided only at a read operation on an open block.

Referring toFIG. 19, the page offset command field format may be used in a manner similar to a read command field format. In other words, the page offset command field format may use a read command mark, a storage address format, and a read command end mark of the read command field format. The page offset command field format may have a format in which data is not output after the read command end mark.

In this case, the host2100transmits the storage device2200a read command mark representing a transfer of read information to the storage device2200. After sending the read command mark, the host2100transmits a storage address format for reporting a data storage location information and a read command end mark.

InFIG. 19, the storage address format is formed of 32 bits and includes a read hint area and a page offset area.

The read hint area of the storage address format may use one bit of “X” bits of an unused area of the storage address format. In this case, the unused area of the storage address format is formed of (X−1) bits, and the read hint area of the storage address format is formed of one bit. A cell type area of the storage address format is formed of “A” bits, a CAU area of the storage address format is formed of “B” bits, and a block area of the storage address format is formed of “C” bits. A page area shown inFIG. 18is used as a page offset area of the storage address format and is formed of “D” bits.

FIG. 20is a diagram for describing a page offset transferring method shown inFIG. 19, according to an exemplary embodiment of the inventive concept. In the case a specific condition is satisfied prior to transferring a read command, the host2100transmits a page offset command field format in which a read hint area of a storage address format is set to “1”.

A condition by which a read hint command bit ofFIG. 19is set to “1” may be expressed by the following equation (1).
A& (B∥C∥D)   (1)

In the equation (1), “&” represents an AND operation, and “∥” represents an OR operation.

Here, a condition A represents the case that a block to be read is an open block. A condition B means a first read operation after a user device is initialized. For example, the condition B represents the case that a power is turned on/off while a read operation is performed after a transfer of a page offset command field format. A condition C represents the case that a memory block is changed in the same CAU. In other words, the condition C represents the case that a read-target block is changed in the same chip or die. A condition D represents the case that a page offset of a read-target block is changed. For example, the condition D represents the case that a read operation is performed after a transfer of a page offset command field format and a last program page offset is changed due to programming a corresponding memory block.

Referring toFIG. 20, “04h” of a storage address format includes a read hint command bit, and “05h” includes a last programmed page offset bit. InFIG. 20, a page offset of an open block may be a fifth page. If a condition expressed by the equation (1) is satisfied, the user device2000(refer toFIG. 2) according to an exemplary embodiment of the inventive concept may set a read hint command bit to “1” and a page offset to a fifth page. Afterwards, the user device2000sends a page offset command field format to the storage device2200.

FIG. 21is a diagram illustrating a normal read operation performed when a read hint area is set to 0, according to an exemplary embodiment of the inventive concept. If a condition expressed by the equation (1) is not satisfied, the host2100sets a read hint area ofFIGS. 19to “0” and performs a normal read operation.

Referring toFIG. 21, “00h” of a storage address format includes a read command bit, and “03h” of the storage address format includes a page number of a read target. InFIG. 21, a page corresponding to a read target may be a third page. If the condition expressed by the equation (1) is not satisfied, the host2100sets a read command bit to “0” and a read-target page to a third page and sends a read command field format to the storage device2200.

The user device2000according to an exemplary embodiment of the inventive concept manages a FTL on the host2100, and if a specific condition is satisfied, the user device2000sends a read hint command to the storage device2200prior to a transfer of a read command. The read hint command may include page offset information of an open block. The read hint command has a page offset command field format similar to a read command field format, thereby preventing a drop off in performance. The storage device2200may improve program/read performance using page offset information from the host2100.

Not only is a user device according to an exemplary embodiment of the inventive concept applicable to a two-dimensional flash memory, but it is also applicable to a three-dimensional (3D) flash memory.

FIG. 22is a block diagram illustrating a flash memory used in an exemplary embodiment of the inventive concept. Referring toFIG. 22, a flash memory2210may include a 3D cell array210, a data input/output circuit220, an address decoder230, and control logic240.

The data input/output circuit220is connected with the 3D cell array210via a plurality of bit lines BLs. The data input/output circuit220receives data DATA from an external device or outputs data read from the 3D cell array210to the external device. The address decoder230is connected with the 3D cell array210via a plurality of word lines WLs and selection lines GSL and SSL. The address decoder230selects a word line in response to an address ADDR.

The control logic240controls operations of the flash memory2210including a read operation, a program operation, an erase operation, and so on. For example, at a program operation, the control logic240controls the address decoder230such that a program voltage is supplied to a selected word line and the data input/output circuit220such that data is programmed. The control logic240controls programming, erasing, and reading of the flash memory2210based on a control signal CTRL from the device controller2230(refer toFIG. 2). The control logic240may receive a corresponding command CMD from the device controller2230(refer toFIG. 2).

FIG. 23is a perspective view illustrating a 3D structure of a memory block illustrated inFIG. 22, according to an exemplary embodiment of the inventive concept. Referring toFIG. 23, a memory block BLK1is formed in a direction perpendicular to a substrate SUB. An n+ doping region is formed in the substrate SUB. A gate electrode layer and an insulation layer are repeatedly deposited above the substrate SUB. An information storage layer is formed between the gate electrode layers and the insulation layers.

V-shaped pillars are formed when the gate electrode layer and the insulation layer are patterned in a vertical direction. The pillars are in contact with the substrate SUB via the gate electrode layers and the insulation layers. In each pillar, an outer portion may be a vertical active pattern and be formed of a channel semiconductor and an inner portion may be a filling dielectric pattern and be formed of an insulation material such as silicon oxide.

The gate electrode layers of the memory block BLK1may be connected with a ground selection line GSL, a plurality of word lines WL1to WL8, and a string selection line SSL. The pillars of the memory block BLK1are connected with a plurality of bit lines BL1to BL3. InFIG. 23, one memory block BLK1is illustrated as having two selection lines SSL and GSL, eight word lines WL1to WL8, and three bit lines BL1to BL3. However, the inventive concept is not limited thereto.

FIG. 24is a circuit diagram illustrating an equivalent circuit of a memory block BLK1illustrated inFIG. 23, according to an exemplary embodiment of the inventive concept. Referring toFIG. 24, cell strings CS11to CS33are connected between bit lines BL1to BL3and a common source line CSL. Each cell string (e.g., CS11) includes a string selection transistor SST, a plurality of memory cells MC1to MC8, and a ground selection transistor GST.

The string selection transistors SST are connected with string selection lines SSL1to SSL3. The memory cells MC1to MC8are connected with corresponding word lines WL1to WL8, respectively. The ground selection transistors GST are connected with a ground selection line GSL. In each cell string, the string selection transistor SST is connected with a bit line, and the ground selection transistor GST is connected with the common source line CSL.

Memory cells MC1to MC8are connected to corresponding word lines WL1to WL8, and a group of memory cells that are connected to a word line and are simultaneously programmed and are named a page. The memory block BLK1is constituted by a plurality of pages. In addition, a word line is connected with a plurality of pages. Referring toFIG. 24, a word line (e.g., WL4) with the same distance from the common source line CSL may be connected in common to three pages.

A user device according to an exemplary embodiment of the inventive concept may be applied to or used in various products. The user device according to an exemplary embodiment of the inventive concept may be implemented in electronic devices, such as, but not limited to, a PC, a digital camera, a camcorder, a handheld phone, an MP3 player, a portable media player (PMP), a playstation portable (PSP), a personal digital assistant (PDA), and so on. A storage medium of the user device may be implemented with storage devices, such as, but not limited to, a memory card, a universal serial bus (USB) memory, a solid state drive (SSD), and so on.

FIG. 25is a block diagram illustrating a memory card to which a storage device of a user device according to an exemplary embodiment of the inventive concept is applied. A memory card system3000includes a host3100and a memory card3200. The host3100contains a host controller3110and a host connection unit3120. The memory card3200includes a card connection unit3210, a card controller3220, and a flash memory3230.

The host3100writes data at the memory card3200and reads data from the memory card3200. The host controller3110sends a command (e.g., a write command), a clock signal CLK generated from a clock generator (not shown) in the host3100, and data to the memory card3200through the host connection unit3120.

The card controller3220stores data at the flash memory3230in response to a command input through the card connection unit3210. The data is stored in synchronization with a clock signal generated from a clock generator (not shown) in the card controller3220. The flash memory3230stores data transferred from the host3100. For example, in a case where the host3100is a digital camera, the memory card3200may store image data.

FIG. 26is a block diagram illustrating an SSD to which a storage device according to an exemplary embodiment of the inventive concept is applied. Referring toFIG. 26, an SSD system4000includes a host4100and an SSD4200.

The SSD4200exchanges signals SGL with the host4100through a signal connector4211and is supplied with a power PWR through a power connector4221. The SSD4200includes a plurality of flash memories4201to420n, an SSD controller4210, and an auxiliary power supply4220.

The plurality of flash memories4201to420nmay be used as a storage medium of the SSD4200. Not only may the SSD4200employ the flash memory, but it may employ other nonvolatile memory devices. The flash memories4201to420nare connected with the SSD controller4210through a plurality of channels CH1to CHn. One channel is connected with one or more flash memories. Flash memories connected with one channel may be connected with the same data bus.

The SSD controller4210exchanges the signals SGL with the host4100through the signal connector4211. The signals SGL may include a command, an address, data, and so on. The SSD controller4210is adapted to write or read out data to or from a corresponding flash memory according to a command of the host4100. The SSD controller4210will be more fully described with reference toFIG. 27.

The auxiliary power supply4220is connected with the host4100through the power connector4221. The auxiliary power supply4220is charged by the power PWR from the host4100. The auxiliary power supply4220may be placed inside or outside the SSD4200. For example, the auxiliary power supply4220may be put on a main board to supply an auxiliary power to the SSD4200.

FIG. 27is a block diagram illustrating an SSD controller shown inFIG. 26, according to an exemplary embodiment of the inventive concept. Referring toFIG. 27, an SSD controller4210includes a nonvolatile memory (NVM) interface4211, a host interface4212, an error correction code (ECC) circuit4213, a CPU4214, and a buffer memory4215.

The NVM interface4211may spread data transferred from the buffer memory4215into channels CH1to CHn. The NVM interface4211transmits data read from flash memories4201to420nto the buffer memory4215. The NVM interface4211may use a flash memory interface method, for example. In other words, the SSD controller4210may perform a read, a write, and an erase operation according to the flash memory interface method.

The host interface4212may provide an interface with the SSD4200according to the protocol of the host4100. The host interface4212may communicate with the host4100using USB, SCSI, peripheral component interconnect (PCI) express, ATA, Parallel ATA (PATA), Serial ATA (SATA), SAS, or the like. The host interface4212may also perform a disk emulation function which enables the host4100to recognize the SSD4200as a hard disk drive (HDD).

The ECC circuit4213may generate an ECC using data transferred to the flash memories4201to420n. The ECC thus generated may be stored at a spare area of the flash memories4201to420n. The ECC circuit4213may detect an error of data read from the flash memories4201to420n. If the detected error is correctable, the ECC circuit4213may correct the detected error.

The CPU4214may analyze and process signals received from the host4100. The CPU4214may control the host4100through the host interface4212or the flash memories4201to420nthrough the NVM interface4211. The CPU4214may control the flash memories4201to420naccording to firmware for driving the SSD4200.

The buffer memory4215may temporarily store write data provided from the host4100or data read from a flash memory. In addition, the buffer memory4215may store metadata to be stored in the flash memories4201to420nor cache data. At a sudden power-off operation, metadata or cache data stored at the buffer memory4215may be stored in the flash memories4201to420n. The buffer memory4215may be implemented with a dynamic RAM (DRAM), a static RAM (SRAM), and so on.

FIG. 28is a block diagram illustrating an electronic device including a storage device according to an exemplary embodiment of the inventive concept. An electronic device5000may be implemented with handheld electronic devices, such as a PC or a handheld electronic device, such as a notebook computer, a cellular phone, a PDA, a camera, and so on.

Referring toFIG. 28, the electronic device5000includes a memory system5100, a power supply5200, an auxiliary power supply5250, a CPU5300, a RAM5400, and a user interface5500. The memory system5100contains a flash memory5110and a memory controller5120.

While the inventive concept has been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present inventive concept as defined by the claims.