Word line driver for negative voltage

A word line driver includes multiple current paths for driving a word line of a memory device to a negative voltage and a positive voltage. When driving the word line from the negative voltage to the positive voltage, the word line driver uses a first current path to drive the word line to the positive voltage in one stage. When driving the word line from the positive voltage to the negative voltage, the word line driver drives the word line from the positive voltage to ground using the first current path in a first stage. In a second stage, the word driver further drives the word line from ground to the negative voltage in using a second current path.

FIELD

The present invention relates generally to semiconductor devices, and in particular to drivers for word lines in memory devices.

BACKGROUND

Memory devices often reside in computers and electronic products to store data. A memory device has many memory cells, each holding an electrical charge that represents a bit of data. External data is stored in the memory cells during a write operation. The stored data is retrieved from the memory cells during a read operation. The write and read operations are memory access operations.

A typical memory device has a number of control lines, each connecting to one or more corresponding memory cells. During a memory access operation, the memory device controls a voltage on each control line to access the memory cells to either store data or retrieve data. Control lines of these types are usually called word lines.

A typical memory device has a number of word line drivers. Each word line driver drives a corresponding word line to various voltages. For example, some memory devices have word line drivers that drive the corresponding word lines to a positive voltage during a memory access operation. After the memory access operation, the word line drivers drive the corresponding word lines to a negative voltage.

Some memory devices have word line drivers that drive the corresponding word lines from a positive voltage to a negative voltage using one discharge path. In some of these memory devices, driving the word lines from a positive voltage to a negative voltage using one discharge path generates excessive noise, causing the memory device to perform inefficiently.

SUMMARY OF THE INVENTION

The present invention provides circuits and methods for driving word lines of memory devices to a negative voltage without generating excessive noise.

In one aspect, a memory device includes a memory cell connected to a word line. A word line driver drives the word line to various voltages. The word line driver has multiple paths: a first path and a second path, each connecting to the word line. The first path serves as both a charging path and a discharging path. The second path serves as another discharging path. During a first state of a control signal, the first path charges the word line to a positive voltage. During a second state of the control signal, the first path discharges the word line to ground. The second path further discharges the word line from ground to a negative voltage during the second state of the control signal.

Another aspect offers a method that includes driving a word line connected to a memory cell to a first voltage via a first path to access the memory cell. After the memory is accessed, the method drives the word line to a second voltage via the first path. The method further drives the word line from the second voltage to a third voltage via a second path. The first voltage, the second voltage, and the third voltage are unequal.

DESCRIPTION OF EMBODIMENTS

The following description and the drawings illustrate specific embodiments of the invention sufficiently to enable those skilled in the art to practice it. Other embodiments may incorporate structural, logical, electrical, process, and other changes. In the drawings, like numerals describe substantially similar components throughout the several views. Examples merely typify possible variations. Portions and features of some embodiments may be included in or substituted for those of others. The scope of the invention encompasses the full ambit of the claims and all available equivalents.

FIG. 1shows a memory device having a word line driver circuit according to an embodiment of the invention. Memory device100includes a main memory112having a plurality of memory cells113arranged in rows and columns along with word lines (WL0-WLN) and bit lines (BL0-BLM). Row decoder104and column decoder106decode address signals A0-AX on address lines (or address bus)108to access memory cells113. A data input path114and a data output path116transfer data between memory cells113and data lines (or data bus)110. Data lines110carry data signals DQ0through DQN. A memory controller118controls the modes of operations of memory device100based on control signals on control lines120. Examples of control signals include a row access strobe signal RAS*, a column access strobe CAS* signal, a write enable signal WE*, and a clock signal CLK.

Memory device100further includes a word line driver circuit150and a driver control circuit160for activating memory cells113during an access mode based on address signals decoded by decoders104and106to transfer data between memory cells113and data lines110. During a standby mode, word line driver circuit150and a driver control circuit160deactivate memory cells113. Memory controller118initiates the access and standby modes.

Memory device100also includes a supply line170for receiving a supply voltage Vcc. A pump circuit172pumps Vcc to a pumped voltage Vp higher than Vcc. In some embodiments, memory device100uses Vp to activate memory cells113during the access mode. Memory device100further includes a negative voltage generator174for generating a negative voltage VNat node176. In some embodiments, memory device100uses VNto deactivate memory cells113during the standby mode.

In some embodiments, memory device100is a dynamic random access memory (DRAM) device. In other embodiments, memory device100is a static random access memory (SRAM) device, or a flash memory. Some examples of DRAM devices include synchronous DRAM, commonly referred to as SDRAM (synchronous dynamic random access memory), SDRAM II, SGRAM (synchronous graphics random access memory), DDR SDRAM (double data rate SDRAM), DDR II SDRAM, and Synchlink or Rambus DRAM. Those skilled in the art recognize that memory device100includes other elements which are not shown for clarity.

FIG. 2shows more detail of a portion of the memory device of FIG.1. Memory cells113are arranged in rows (Row0-RowN) and columns (Col0-ColM). Memory cells connect to a plurality of word lines115.0-115.N and a plurality of bit lines125.0-125.M. Word lines115.0-115.N have word line signals WL0-WLN connects to memory cells113. Bit lines125.0-125.N have bit line signals BL0-BLM. The memory cells in the same row connect to one corresponding word line. The memory cells in the same column connect to one corresponding bit line. The voltage level on a word line activates the memory cells in the corresponding rows so that data can be read from or written to the memory cells via the corresponding bit line. The voltage signal of the bit line represents the data.

Word line driver circuit150(FIG. 1) includes multiple word line drivers250.0-250.N, each connecting to a corresponding word line. Driver control circuit160(FIG. 1) includes a plurality of driver controllers260.0-260.N, each connecting to a corresponding word line driver. A plurality of select lines210.0-210.N connects between row decoder104and driver controllers260.0-260.N. Select lines210.0-210.N have select signals SEL0-SELN. Driver controllers260.0-260.N, word line drivers250.0-250.N, word lines115.0-115.N form a plurality of word line driving paths270.0-270.N between row decoder104and memory cells113.

When a select line is selected, its corresponding select signal is activated. Each of the select lines210.0-210.N corresponds to one of the word lines115.0-115.N. When a select line is selected, the corresponding word line is also selected and its corresponding word line signal is activated. Each of the word line signals WL0-WLN has a signal level corresponding to an access voltage when the word line is activated. Each of the word line signals WL0-WLN also has a signal level corresponding to a standby voltage when the word line is deactivated (not activated). In embodiments represented byFIG. 2, each of the word line signals WL0-WLN has a signal level corresponding to a positive voltage when the word line is activated and a signal level corresponding to a negative voltage when the word line is deactivated.

During a memory access operation, decoder104decodes address signals A0-AX to select one of the select lines210.0-210.N as a selected select line. The driver controller corresponding to the selected select line applies appropriate drive control signals to a corresponding selected word line driver. Based on the drive control signals, the selected word line driver drives the corresponding word line to various voltages to activate (open) the corresponding memory cells. After the corresponding memory cells are activated, one or more of these memory cells are accessed to either read data from or write data to the activated memory cells.

FIG. 3is an exemplary timing diagram forFIG. 2. Astandby mode occurs before time T0and after time T1. An access mode occurs between times T0and T1. In some embodiments, the standby mode occurs when address decoder104selects none of the select lines210.0-210.N (FIG.2). And the access mode occurs when address decoder104selects at least one of the select lines210.0-210.N. Thus, in these embodiments, none of the SEL0-SELN signals is activated in the standby mode and at least one of the SEL0-SELN signals is activated the access mode.

Each of the SEL0-SELN signals has one signal level in the standby mode and another signal level in the access mode. In some embodiments, in the standby mode, none of the signals SEL0-SELN is activated and they all have a low signal level. And in the access mode, at least one of the SEL0-SELN signals is activated to a high signal level. InFIG. 3, for example, when the SEL0signal is activated between times T0and T1while all other select signals are not activated, the SEL0signal has a high signal level, all other select signals remain at the low signal level.

The corresponding word line signal WL0is also activated between time T0and T1when the SEL0signal is activated. In the above, word line driver250.0is the selected word line driver, which drives the WL0signal to various voltages between the standby mode and the access mode. As shown inFIG. 3, between the standby and the access mode, word line driver250.0drives the WL0signal between Va and Vs where Va is greater than zero and Vs is less than zero. In some embodiments, Va corresponds to Vp (FIG. 1) and Vs corresponds to VN. Thus, in these embodiments, the WL0signal has a signal level corresponding a positive voltage and a signal level corresponding to a negative voltage.

In embodiments represented byFIG. 3, none of WL0-WLN signals is activated in the standby mode and no data is read from or written to memory cells113. And in the access mode, at least one of the WL0-WLN signals is activated and data is read from or written to at least one of the memory cells113. Further in the standby mode memory cells113are idle. Thus, the standby mode is also an idle mode.

In some embodiments, at least one of the WL0-WLN signals is still activated in the standby mode but no data is read from or written to memory cells113.

FIG. 4shows a word line driving path according to an embodiment of the invention. Word line driving path400has a word line driver401which drives word line410to activate a memory cell420, which connects to a bit line440. A driver controller430controls word line driver401based on a select signal SEL on select line432. Bit line440corresponds to one of the bit lines125.0-125.M (FIG.2). Word line driving path400corresponds to one of the word line driving paths270.0-270.N (FIG.2).

Word line driver401has a first current path451and a second current path452. Via current paths451and452, word line driver410drives word line410to various voltages between the access mode and the standby mode. In some embodiments, the access mode occurs when data is transferred between memory cell420and bit line440. The standby mode occurs when no data is transferred between memory cell420and bit line440; memory cell420is idle in the standby mode.

In the access mode, word line driver401drives word line410to an access voltage. In the standby mode, word line driver401drives word line410to standby voltage. The access voltage and the standby voltage are unequal. In embodiments represented byFIG. 4, word line driver401drives word line410to an access voltage equal to positive voltage and to a standby voltage equal to a negative voltage. The signal level of the WL signal indicates the voltage level of word line410.

From the standby mode to the access mode, word line driver401drives word line410having the negative voltage to the positive voltage in one stage via current path451.

From the access mode to the standby mode, word line driver401drives word line410having the positive voltage to the negative voltage in two separate stages via both current paths451and452. In a first stage, word line driver401drives word line410having the positive voltage to ground via first current path451. In a second operating stage, word line driver401further drives word line410from ground to the negative voltage via second current path452.

Thus, current path451of word line driver401has two functions. A first function drives word line410from the negative voltage to the positive voltage during the access mode. A second function drives word line410from the positive voltage to ground during the standby mode. Current path452has a function of driving word line from ground to the negative voltage.

Current path451has a driving unit461connected between node471and word line410. Node471receives a charge signal P. Current path452has a driving unit462connected between node472and word line410. Node472receives a charge signal N. Driving unit461receives a drive control signal CP. Driving unit462receives a drive control signal CN.

FIG. 5is a timing diagram for FIG.4. The SEL signal is activated to a high signal level during the access mode between times T2and T3. The P signal at node471varies between voltages V2and V3. Thus, node471has a variable voltage (not fixed). The WL signal on word line410varies between voltages V1and V3. The N signal is fixed at voltage V1. V1is a negative voltage, V2corresponds to ground (zero volt), and V3is a positive voltage. In some embodiments, V1corresponds to VNand V3corresponds to Vp of FIG.1.

As shown inFIG. 5, in the stand by mode, the WL signal has signal level corresponding to a negative voltage V1while the P signal has signal level corresponding to ground (V2). In the access mode, the WL signal has signal level corresponding to a positive voltage V3, which is the same as the signal level of the P signal.

Referring toFIGS. 4 and 5, when path400switches from the standby node (before time T2) to the access mode (at time T2), driving unit462isolates node472from word line410in response to the CN signal. Driver controller430activates the P signal to a signal level corresponding V3. Thus, the voltage at node471is V3. Between time T2and T3, driving unit461charges word line410to V3via current path451in response to the CP signal.

When path400switches from the access mode (at time T3) to the standby mode, driver controller430deactivates the P signal to a signal level corresponding to V2(ground). Thus, node471is ground. Driving unit461discharges word line410from V3to ground in response to the CP signal. After word line410is at ground, driving unit462connects word line to node472in response to the CN signal to further discharge word line410from ground to the negative voltage V1.

FIG. 6shows another word line driving path according to another embodiment of the invention. Path600has a word line driver601which drives word line610to activate a memory cell620via current paths651and652. Memory cell620connects to a bit line644. Word line610has word line signal WL. A driver controller630controls word line driver601based on a select signal SEL signal on select line632. Bit line644corresponds to one of the bit lines125.0-125.M (FIG.2). Word line driving path600corresponds to one of the word line driving paths270.0-270.N (FIG.2).

Current path651has a driving unit661connected between node671and word line610. Node671receives a charge signal P. Current path652has a driving unit662connected between node672and word line610. Node672receives a charge signal N. Driving units651and652receive a drive control signal DR on node664. Node671has a variable voltage. Node672has a negative voltage.

Driving unit661includes a driving transistor682having a source connected to node671, a drain connected to word line610, and a gate connected to node666. An isolation transistor684has a source connected to node664, a drain connected to node666, and a gate connected to a voltage V4. During the access mode, transistor682changes the voltage of word line610from a negative voltage to a positive voltage. During the standby mode transistor682changes the voltage of word line610from a positive voltage to ground.

Driving unit662includes a pulldown transistor692having a source connected to node672, a drain connected to word line610, and a gate connected to node664. During the standby mode, transistor692changes the voltage of word line610from ground to a negative voltage.

FIG. 7is a timing diagram for FIG.6. The P signal at node671varies between ground (GND) and V6. The N signal is fixed at voltage V5. The WL signal on word line410varies between voltages V5and V6. V5is a negative voltage and V6is a positive voltage. In some embodiments, VS corresponds to VNand V6corresponds to Vp of FIG.1.

Referring toFIGS. 6 and 7, in the standby mode, the DR signal has a high signal level. This turns on transistor692, connecting word line610to node672. Since node672has a voltage V5, word line610also has a voltage of V5. InFIG. 6, V4is equal to or less than zero. Thus, transistor684turns on, connecting node666to node664. Since node664has a high signal level, node666also has a high signal level. This turns off transistor682, disconnecting word line610from node671. Thus, word line610remains at V5. In the standby mode node671is ground.

When the access mode is initiated at time T4, the DR signal switches to low, causing the voltage at node664low. Transistor692turns off, disconnecting word line610from node672. Transistor682turns on connecting word line610to node671. The P signal switches to V6, forcing the voltage of node666low and turning on transistor682. This allows word line610to charge from V5to V6via current path651.

When the standby mode is initiated at time T5, the P signal switches to ground. The voltage of node666goes even lower than ground. This allows word line610to quickly discharge from V6to ground via current path651. After word line610reaches ground, the DR signal switches to high, causing the voltage at node664high. Transistor692turns on, allowing word line610to further discharges from ground to V5via current path652.

FIG. 8shows a word line driver according to another embodiment of the invention. Word line driver801drives word line810to a positive voltage when word line801is selected and to a negative voltage when word line810is deselected (not selected). Word line driver801can substitute one of the word line drivers250.0-250.N ofFIG. 2. Acontrol circuit similar to memory controller118ofFIG. 1can select and deselect word line810in different operating modes.

Word line driver801includes transistors882,884, and892connected in a similar fashion as that of word line driver601(FIG.6). Transistor882connects between word line810and node871. Transistor892connects between word line810and node872. Transistor884connects between the gates of transistors882and892. Node871has a charge signal P. Node872has a charge signal N. The P signal has signal levels representing a variable voltage. The N signal has a signal level fixed at a voltage.

Word line driver801further includes switches850and860. Drive control signal PCTL controls switch850. In some embodiments, the PCTL signal switches between ground and Vp. Drive control signals NCTL1and NCTL2control switch860. The PCTL, NCTL1, and NCTL2are generated by a driver controller similar to one of the driver controllers260.0-260.N (FIG. 2) and driver controller630(FIG.6). In some embodiments, switches850and860are part of the driver controller.

Switch850includes a transistor854connected between node871and a supply node856and a transistor858connected between node871and ground. Node856has a voltage Vp. Switch850controls the signal P based on the signal levels of the PCTL. The P signal varies between ground and Vp. Switch850, and transistors882and884form a driving unit861similar to driving unit461(FIG.4).

Switch860includes a transistor863connected between node864and a supply node866and a transistor868connected between node864and a path to ground circuit888. When transistor868turns on, path to ground circuit888provides a ground potential to node864. In some embodiments, path to ground circuit888connects node864directly to ground when transistor868turns on. Node866has a voltage V8. In some embodiments, V8equals Vp. Switch860controls a signal NSW at node864based on the signal levels of the NCTL1and NCTL2signals. The NSW signal varies between ground (or a negative voltage) and V8. Switch860and transistor892form a driving unit862similar to driving unit462(FIG.4).

Word line810has a negative and a positive voltage. When word line810is selected, driving unit861drives word line810from a negative voltage to a positive voltage via current path851. When word line810is not selected, driving unit861drives word line810from the positive voltage to the negative voltage in two stages. In one stage, driving unit861drives word line810from the positive voltage to ground via current path851. In another stage, after word line810reaches ground, driving unit862further drives word line810from ground to the negative via current path852.

FIG. 9is a timing diagram for FIG.8. The P signal varies between ground (GND) and Vp. The N signal is fixed at VN. The WL signal varies between voltages Vp and VN.

Referring toFIGS. 8 and 9, when word line810is not selected, the NCTL1and NCLT2signals have a low signal level. Transistor868turns off. Transistor863turns on, connecting node864to V8(high). When node864is high, transistor892turns on, connecting word line810to node872. Since node872has a voltage VN, the WL signal on word line810also has a voltage of VN. InFIG. 8, V7is equal to or less than zero. Thus, transistor884turns on, connecting node877to node864. Since node864has a high signal level, node877also has a high signal level. When node877is high enough compared with node871, transistor882turns off, disconnecting word line810from node871. Thus, the WL signal remains at VN. When word line810is not selected, the PCTL signal has a high signal level.

When word line810is selected at time T7, the NCTL1and NCTL2signals switch to high, transistor863turns off. Transistor868turns on, connecting node864to ground (low). When node864is low, transistor892turns off, disconnecting word line810from node872. Transistor882turns on connecting word line810to node871. The PCTL signal switches to low, transistor858turns off, transistor854turns on connecting node871to node856, which has the voltage Vp. Thus, the P signal on node871switches to Vp and forces the voltage of node877low (or V7plus the absolute value of Vtp, where Vtp is the threshold voltage of transistor884). This allows transistor882to remain conductive, allowing word line810to charge from VNto Vp via current path851.

When word line810is not selected at time T8, the PCTL signal switches to high (or Vp). Transistor854turns off. Transistor858turns on, connecting node871to ground. The voltage of node877goes even lower than ground. This allows word line810to quickly discharge from Vp to ground via current path851. Node877is “boosted” to V7minus the absolute value of Vtp by capacitor coupling. After word line810reaches ground, the NCTL1and NCTL2signals switch to low. Transistor868turns off. Transistor863turns on. This connects node864to V8to turn off transistor882on current path851. The high signal level on node864turns on transistor892, allowing word line810to further discharge from ground to VNvia current path852.

FIG. 10shows another word line driver according to an alternative embodiment of the invention. Word line driver1001drives word line1010to a positive voltage when it is selected in the access mode and to a negative voltage when it is deselected in the standby mode. Word line driver1001can substitute one of the word line drivers250.0-250.N ofFIG. 2. Acontrol circuit similar to memory controller118ofFIG. 1initiates the access and standby modes.

Word line driver1001includes current paths1051and1052. A combination of branched current paths1051aand1051bforms current path1051. Current path1051a includes a current path between word line1010and node1071through a first driving transistor1082. Current path1051bincludes a current path between word line1010and node1071through a second driving transistor1083.

A combination of branched current paths1052aand1052bforms current path1052. Current path1052aincludes a current path between word line1010and node1072through series connected pulldown transistors1092and1093. Current path1052bincludes a current path between word line1010and node1072through a pulldown transistor1095.

Transistors1082and1083and an isolation transistor1084form a driving unit1061. Transistors1020,1021,1092,1093, and1095form another driving unit1062. Driving unit1061drives word line1010from a negative voltage to a positive voltage during the access mode and drives word line1010from a positive voltage to ground during the standby mode. Driving unit1062drives word line1010from ground the standby mode to a negative voltage.

Node1071receive a charge signal P that switches between different signal levels representing different voltages. Node1072receives a charge signal N that remains at a fixed level representing a fixed voltage. Node1064receives drive control signal DR. Node1097receives another drive control signal DEC. The P, DR, and DEC signals are generated by a drive controller similar to one of the drive controllers260.0-260.N (FIG. 2) and driver controller630(FIG.6).

FIG. 11is a timing diagram for FIG.10. The P signal at node1071varies between ground (GND) and Vp. The N signal is fixed at VN. The WL signal varies between voltages Vp and VN.

Referring toFIGS. 10 and 11, when word line1010is not selected, the DR and DEC signals are high. When these signals are high, transistors1092,1093, and1095turn on, connecting word line1010to node1072. The Since node1072has a voltage VN, word line1010also has a voltage of VN. InFIG. 10, V8is equal to or less than zero. Thus, transistor1084turns on, connecting node1077to node1064. Since node1064has a high signal level, node1077also has a high signal level. When node1077is high enough, transistor1082turns off. Transistor1083also turns off because node1064has a high signal level. When transistors1082and1083turn off, word line1010is disconnected from node1071. Thus, the signal level of the WL signal remains at VN. When word line1010is not selected, the P signal is has a low signal level.

When word line1010is selected at time T9, the DR (node1064) and DEC signals switch to low signal levels. When these signals are low, transistors1092,1093, and1095turn off, disconnecting word line1010from node1072. When node1064is low, node1077is also low. When these nodes are low, both transistors1082and1083turn on. When transistors1082and1083turn on, word line1010connects to node1071. The P signal on node1071switches to Vp. Thus, the WL signal switches to Vp via current path1051(1051aand1051b).

When word line1010is not selected at time T10, the P signal switches to ground. Word line1010discharges from Vp to ground via current path1051. After word line1010reaches ground, the DR signal switches to high to turn off both transistors1082and1083on current path1051. The DEC signal also switches to high. When both of the DR and DEC signals are high, transistors1092,1093, and1095turn on, allowing word line1010to further discharge from ground to VNvia current path1052(1052aand1052b).

In alternative embodiments of the invention, transistor1083(FIG.10), or transistor1095, or both can be omitted without departing from the scope of the invention.

FIG. 12shows a system according to an embodiment of the invention. System1200includes a first integrated circuit (IC)1202and a second IC1204. ICs1202and1204can include processors, controllers, memory devices, application specific integrated circuits, and other types of integrated circuits. In embodiments represented byFIG. 12, for example, IC1202represents a processor, and IC1204represents a memory device. Processor1202and memory device1204communicate using address signals on lines1208, data signals on lines1210, and control signals on lines1220.

Memory device1204corresponds to memory device100of FIG.1. Thus, memory device1204has elements similar to the elements of memory device100. Further, memory device1204also includes word line drivers similar to word line drivers described in the specification.

CONCLUSION

Various embodiments of the invention describe circuits and methods for driving word lines of memory devices to a negative voltage without generating excessive noise or with reducing high negative current. Although specific embodiments are described herein, those skilled in the art recognize that other embodiments may be substituted for the specific embodiments shown to achieve the same purpose. This application covers any adaptations or variations of the present invention. Therefore, the present invention is limited only by the claims and all available equivalents.