Method and device for metal gate stacks

A method for manufacturing a semiconductor device includes providing a substrate structure including a substrate, a high-k dielectric layer on the substrate, a capping layer on the high-k dielectric layer, forming a first N-type work function metal layer on the capping layer, forming a second N-type work function metal layer on the first N-type work function metal layer, and forming a metal electrode layer on the second N-type work function metal layer. The second N-type work function metal layer has a Ti/Al atomic ratio greater than the Ti/Al atomic ratio of the first N-type work function metal layer. The second work function metal layer having a higher Ti/Al atomic ratio will not absorb appreciable oxygen from the atmosphere, so that oxygen will not be available to the first work function metal layer, thereby reducing the oxidation level of the first work function metal layer.

CROSS-REFERENCES TO RELATED APPLICATIONS

The present application claims priority to Chinese patent application No. 201510674607.2, filed with the State Intellectual Property Office of People's Republic of China on Oct. 19, 2015, the content of which is incorporated herein by reference in its entirety.

FIELD OF THE INVENTION

The present invention relates to integrated semiconductor devices, and more particularly to gate stack structures, a semiconductor device having the gate stack structures, and methods for manufacturing the same.

BACKGROUND OF THE INVENTION

As the critical dimension of metal oxide semiconductor field effect transistor (MOSFET) devices continues to shrink, the short channel effect becomes a critical issue. Fin field effect transistor (FinFET) devices have a good gate control capability to effectively suppress the short channel effect. FinFET devices also reduce random dopant fluctuation to improve the stability of the devices. Thus, FinFET devices are generally used in the design of small-sized semiconductor elements.

The work function plays an important role in the regulation of the threshold voltage of a FinFET device. In high-k dielectric layer and metal gate (HKMG) gate-last processes of FinFET devices, a compound containing aluminum (Al) is generally used as an N-type work function metal layer, however, the present inventor has discovered that N-type work function metal layers can be easily oxidized, resulting in the change of the work function of an NMOS device, thereby affecting its threshold voltage.

Therefore, there is a need for an improved gate stack structure and manufacturing methods thereof to stabilize the work function of an NMOS device.

BRIEF SUMMARY OF THE INVENTION

Embodiments of the present invention provide a method for manufacturing a semiconductor device. The method includes providing a substrate structure comprising a substrate, a high-k dielectric layer on the substrate, a capping layer on the high-k dielectric layer, forming a first N-type work function metal layer on the capping layer, forming a second N-type work function metal layer on the first N-type work function metal layer, and forming a metal electrode layer on the second N-type work function metal layer. The second N-type work function metal layer has a Ti/Al atomic ratio greater than a Ti/Al atomic ratio of the first N-type work function metal layer.

In one embodiment, forming the substrate structure includes providing the substrate, sequentially forming the high-k dielectric layer, the capping layer, a barrier layer, and a P-type work function metal layer on the substrate, and removing the P-type work function metal layer and the barrier layer.

In one embodiment, providing the substrate structure may include providing the substrate, sequentially forming the high-k dielectric layer, the capping layer, a barrier layer, and a P-type work function metal layer on the substrate, removing the P-type work function metal layer, the barrier layer, and the capping layer, and forming a new capping layer on the high-k dielectric layer. The new capping layer and the first N-type work function metal layer are formed in a same station.

In one embodiment, the substrate further comprises a first trench in an NMOS region and a second trench in a PMOS region, wherein the high-k dielectric layer and the capping layer are sequentially formed on a bottom and sidewalls of the first trench, wherein the high-k dielectric layer, the capping layer, a barrier layer, and a P-type work function metal layer are sequentially formed on a bottom and sidewalls of the second trench.

In one embodiment, the first N-type work function metal layer is formed on the capping layer in the first trench and on the P-type work function metal layer in the second trench.

In one embodiment, the first trench comprises a first fin and the second trench comprises a second fin; the high-k dielectric layer and the capping layer are sequentially formed on a top surface and side surfaces of the first fin; and the high-k dielectric layer, the capping layer, the barrier layer, and the P-type work function metal layer are sequentially formed on a top surface and side surfaces of the second fin.

In one embodiment, the capping layer may include TiN or TiSiN. The first N-type work function metal layer may include TiAl, TiCAl, TiNAl, or TiSiAl. The second N-type work function metal layer may include TixAly, TixCzAly, TixNzAly, or TixSizAly, x represents a ratio of atoms of Ti, y represents a ratio of atoms of Al, z represents a ratio of atoms of the corresponding C, N, and Si, and x is greater than y.

In one embodiment, the substrate structure further includes an interface layer disposed between the substrate and the high-k dielectric layer.

In one embodiment, the method may further include, prior to forming the metal electrode layer, forming an adhesion layer on the second N-type work function metal layer.

Embodiments of the present invention also provide a semiconductor device. The semiconductor device includes a substrate, a high-k dielectric layer on the substrate, a first capping layer on the high-k dielectric layer, a first N-type work function metal layer on the first capping layer, a second N-type work function metal layer on the first N-type work function metal layer, and a metal electrode layer on the second N-type work function metal layer. The second N-type work function metal layer has a Ti/Al atomic ratio greater than the Ti/Al atomic ratio of the first N-type work function metal layer.

In one embodiment, the first capping layer includes TiN or TiSiN. The first N-type work function metal layer includes TiAl, TiCAl, TiNAl, or TiSiAl. The second N-type work function metal layer includes TixAly, TixCzAly, TixNzAly, or TixSizAly, x represents a ratio of atoms of Ti, y represents a ratio of atoms of Al, z represents a ratio of atoms of the corresponding C, N, and Si, and x is greater than y.

In one embodiment, the semiconductor device may further include an interface layer disposed between the substrate and the high-k dielectric layer.

In one embodiment, the semiconductor device may further include an adhesion layer disposed between the second N-type work function metal layer and the metal electrode layer.

In one embodiment, the semiconductor device also includes a first trench and a second trench separated from each other by an interlayer dielectric layer. The first trench includes the high-k dielectric layer on a surface of the substrate, the first capping layer on the high-k dielectric layer, the first N-type work function metal layer on the capping layer, the second N-type work function metal layer on the first N-type work function metal layer, and the metal electrode layer on the second N-type work function metal layer. The second trench includes the high-k dielectric layer on a surface of the substrate, a second capping layer on the high-k dielectric layer, a barrier layer on the capping layer, a P-type work function metal layer on the barrier layer, the first capping layer on the P-type work function metal layer, the first N-type work function metal layer on the first capping layer, the second N-type work function metal layer on the first N-type work function metal layer, and the metal electrode layer on the second N-type work function metal layer.

In one embodiment, the first trench is disposed in an NMOS region, and the second trench is disposed in a PMOS region.

Embodiments of the present invention also provide a method for manufacturing a semiconductor device. The method includes providing a substrate including an NMOS region and a PMOS region, sequentially forming on the substrate a high-k dielectric layer, a capping layer, a barrier layer, and a P-type work function metal layer, removing a portion of the P-type work function metal layer, a portion of the barrier layer, and a portion of the capping layer in the NMOS region, forming a new capping layer on the high-k dielectric layer in the NMOS region and on the P-type work function metal layer in the PMOS region, forming an N-type work function metal layer on the new capping layer, and forming a metal electrode layer on the N-type work function metal layer. The new capping layer and the N-type work function metal layer are formed in a same station.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention now will be described more fully hereinafter with reference to the accompanying drawings. The invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The features may not be drawn to scale, some details may be exaggerated relative to other elements for clarity. Like numbers refer to like elements throughout.

The inventor of the present invention has done deep and systematic research on the N-type work function metal layer containing aluminum and discovered the causes of susceptibility of the N-type work function metal layer to oxidation: (a) The N-type work function layer can absorb oxygen from the environment, and (b) The capping layer disposed below the N-type work function layer can absorb oxygen, resulting in the oxidation of the N-type work function layer. The present disclosure proposes solutions corresponding to these problems.

FIG. 1is a simplified flowchart of a method10for manufacturing a semiconductor device according to an embodiment of the present invention. The method10may include the following process steps:

At102: providing a substrate structure including a substrate, a high-k dielectric layer on the substrate, and a capping layer on the high-k dielectric layer.

The capping layer may be of TiN or TiSiN. The capping layer is configured to prevent the diffusion of an aluminum element of a subsequently formed N-type work function layer into the high-k dielectric layer, thus eliminating any adverse effect on the stability and other properties of the semiconductor device.

At104: forming a first N-type work function metal layer on the capping layer.

At106: forming a second N-type work function metal layer on the first N-type work function metal layer. The ratio between the number of Ti atoms and Al atoms (Ti/Al atomic ratio) in the second work function metal layer is greater than the ratio between the number of Ti atoms and Al atoms in the first work function metal layer.

That is, relative to the first work function metal layer, the second work function metal layer is richer in Ti atoms (Ti-rich), the Ti-rich second work function metal layer does not easily absorb oxygen from the atmosphere and blocks the oxygen absorption by the first work function metal layer, thereby reducing the level of oxidation of the first work function metal layer without affecting the device performance.

In a specific embodiment, the first N-type work function metal layer may include TiAl, TiCAl, TiNAl, TiSiAl, or combinations thereof. Correspondingly, the second N-type work function metal layer may include TixAly, TixCzAly, TixNzAly, TixSizAly, or combinations thereof, where x represents the ratio of atoms of Ti, y represents the ratio of atoms of Al, z represents the ratio of atoms of corresponding C, N, and Si, and x is greater than y. It should be understood that the above-described materials of the first and second N-type work function metal layers are preferred materials, and are not limited thereto. As will be appreciated by those of skill in the art, the oxidation level of the first N-type work function metal layer will be reduced as long as the ratio of the Ti and Al atoms of second N-type work function metal layer is greater than the ratio of the Ti and Al atoms of first N-type work function metal layer. Thus, those of skill in the art may select other suitable materials for the first N-type work function metal layer and the second N-type work function metal layer.

At108: forming a metal electrode layer on the second N-type work function metal layer. For example, the metal electrode layer may include W, Al, or other metal materials.

In the embodiment, in forming the gate stack structure, the N-type work function metal layer may be deposited in two steps, and the ratio of the Ti and Al atoms of the second N-type work function metal layer is greater than the ratio of the Ti and Al atoms of the first N-type work function metal layer, as to block the oxygen absorption in the atmosphere by the first N-type work function metal layer, thereby reducing the oxidation level of the N-type work function metal layer without affecting the device performance.

The substrate structure in the above step102may be provided by a variety of processes, which will be described in detail below. The process of forming the substrate structure will now be described with reference toFIG. 2throughFIG. 4.

Referring toFIG. 2, a substrate201is provided. An interface layer202is formed on the substrate201, a high-k dielectric layer203is formed on the interface layer202, a capping layer204is formed on the high-k dielectric layer203, a barrier layer205is formed on the capping layer204, and a P-type work function metal layer206is formed on the barrier layer205.

In an exemplary embodiment, referring toFIG. 3, the P-type work function metal layer206and the barrier layer205may be removed to form a substrate structure.FIG. 3is a cross-sectional view illustrating a substrate structure30according to an embodiment of the present invention. As shown inFIG. 3, the substrate structure30includes a substrate201, an interface layer202on the substrate201, a high-k dielectric layer203on the interface layer202, and a capping layer204on the high-k dielectric layer203. It is to be understood that, although an interface layer is shown between the substrate and the high-k dielectric layer, the interface layer is optional.

In another exemplary embodiment, referring toFIG. 4, in addition to removing the P-type work function metal layer206and the barrier layer205, the capping layer204may also be removed. Thereafter, a new capping layer204may be formed anew on the high-k dielectric layer203to form a substrate structure shown inFIG. 3. The new capping layer can be formed in the same station as the deposition process of the first N-type work function metal layer. In this case, since the capping layer204is first removed, and the new capping layer204is then formed in the same station as the deposition process of the first N-type work function metal layer, this process can prevent the capping layer204from absorbing oxygen from the environment, resulting in the oxidation of the N-type work function metal layer. Removing the capping layer, then forming a new capping layer in the same station as the deposition of the N-type work function metal layer can further reduce the oxidation of the N-type work function metal layer without affecting the device performance.

In accordance with the present invention, the method for manufacturing a semiconductor device is suitable for planar devices as well as FinFET devices.

FIG. 5throughFIG. 11are cross-sectional views of intermediate stages of a method for manufacturing a semiconductor device according to embodiments of the present invention. It is noted that certain parts (e.g., source, drain, fin, etc.) are omitted to more clearly show the details of the gate stack structure.

According to exemplary embodiments of the present invention, a method for manufacturing a semiconductor device will hereinafter be described in detail with reference toFIG. 5throughFIG. 11.

Referring toFIG. 5, a substrate structure50is provided. The substrate structure50includes an NMOS region having a first trench5011and a PMOS region having a second trench5012. The substrate structure50may also include a shallow trench isolation (STI) structure (not shown).

For a FinFET device, the first trench may include a first fin configured to be a channel region of an NMOS device, the second trench may include a second fin configured to be a channel region of a PMOS device.

The first and second trenches5011,5012may be formed by the following process steps: forming a dummy gate structure including dummy gates and a dummy gate oxide layer in an interlayer dielectric layer502disposed on a substrate501. Next, a planarization process is performed to expose the dummy gates disposed in the first trench5011and the second trench5012. Thereafter, the dummy gates and the dummy gate oxide layer are removed to form the first gate trench5011and the second gate trench5012. Spacer503is formed on sidewalls of the first and second trenches. The spacer503may be, for example, silicon oxide, silicon nitride, silicon oxynitride, and the like. Furthermore, source and drain regions of an NMOS device and a PMOS device may be formed on opposite sides of the first trench5011and the second trench5012. In the NMOS region, the source and drain regions may be formed from an epitaxially grown SiC layer, the epitaxially grown SiC creates a tensile stress in the channel region of the NMOS device. In the PMOS region, the source and drain regions may be formed from an epitaxially grown SiGe layer, the epitaxially grown SiGe creates a compression stress in the channel region of the PMOS device.

Referring toFIG. 6, a high-k dielectric layer601is deposited on the bottom and sidewalls of the first trench5011and the second trench5012, a capping layer602is deposited on the high-k dielectric layer601, a barrier layer603is deposited on the capping layer602, and a P-type work function metal layer604is deposited on the barrier layer603. For a planar device, the bottom of the first and second trenches is the substrate. For a FinFET device, the bottom of the first and second trenches includes the surface and side surfaces of the fin. For example, a high-k dielectric layer601, a capping layer602, a barrier layer603, and a P-type work function layer604may be sequentially deposited in the first and second trenches5011,5012by atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD) process. In a specific embodiment, an interface layer may be formed on the bottom and sidewalls of the first and second trenches5011,5012prior to depositing the high-k dielectric layer601. The interface layer may be a thermal oxide layer to improve the interface properties between the high-k dielectric layer and the substrate. The high-k dielectric layer may include, but not limited to, hafnium oxide, aluminum oxide, tantalum oxide, titanium oxide, zirconium oxide, or the like.

Referring toFIG. 7, a portion of the P-type work function metal layer604, a portion of the barrier layer603, and a portion of the capping layer602are removed from the bottom and sidewalls of the first trench5011.

For example, a patterned photo resist is formed on the P-type work function metal layer604covering the PMOS region while exposing the NMOS region. A dry or wet etching process is performed to remove a portion of the P-type work function metal layer disposed in the NMOS region using the patterned photo resist as a mask and the barrier layer603as an etch stop layer. Thereafter, the portion of the barrier layer603and the portion of the capping layer602disposed in the NMOS region are removed.

Referring toFIG. 8, a new capping layer602′ is deposited on the high-k dielectric layer of the first trench5011and on the P-type work function metal layer604of the second trench5012.

Referring toFIG. 9, a first N-type work function metal layer901is deposited on the new capping layer602′, and a second N-type work function metal layer902is deposited on the first N-type work function metal layer901. The second N-type work function metal layer902has a ratio of the Ti and Al atoms (alternatively referred to as Ti/Al atomic ratio) greater than the ratio of the Ti and Al atoms of the first N-type work function metal layer901.

It should be noted that the N-type work function metal layer(s) in the PMOS region may also be removed by additional process steps.

Referring toFIG. 10, a metal electrode layer1001is deposited on the second N-type work function metal layer902, the metal electrode layer1001may be, for example, W, Al or other metal material. In an alternative embodiment, prior to depositing the metal electrode layer1001, an adhesion layer (glue layer), e.g., TiN, Ti or a stacked structure including a combination of TiN and Ti may be deposited on the second N-type work function metal layer902to increase the bonding between the metal electrode layer and the second N-type work function metal layer.

Thereafter, referring toFIG. 11, a planarization process is performed on the metal electrode layer to expose a surface of the interlayer dielectric layer502, thereby forming a metal gate1011in the NMOS region and a metal gate1021in the PMOS region.

The above-described process steps provide a method for manufacturing a gate stack structure, an NMOS device including the gate stack structure, a PMOS device, and a semiconductor device including the gate stack structure. The semiconductor device includes an NMOS device and a PMOS device.

FIG. 11is a cross-sectional view illustrating gate stack structures11nand11pand a semiconductor device11including the gate stack structures according to some embodiments of the present invention. Referring toFIG. 11, the gate stack structure11nin the NMOS region includes a substrate501, a high-k dielectric layer601on the substrate501, a capping layer602′ on the high-k dielectric layer, a first N-type work function metal layer901on the capping layer602′, a second N-type work function metal layer902on the first N-type work function metal layer901, and a metal electrode layer1011on the second N-type work function metal layer902. The Ti/Al atomic ratio of the second N-type work function metal layer902is greater than the Ti/Al atomic ratio of the first N-type work function metal layer901.

Referring still toFIG. 11, the gate stack structure11pin the PMOS region includes the substrate501, the high-k dielectric layer601on the substrate501, a capping layer602on the high-k dielectric layer601, a barrier layer603on the capping layer602, a P-type work function layer604on the barrier layer603, the capping layer602′ on the P-type work function layer604, the first N-type work function metal layer901on the capping layer602′, the second N-type work function metal layer902on the first N-type work function metal layer901, and the metal electrode layer1011on the second N-type work function metal layer902. The Ti/Al atomic ratio of the second N-type work function metal layer902is greater than the Ti/Al atomic ratio of the first N-type work function metal layer901.

In some embodiments, the gate stack structure may also include an interface layer disposed between the substrate501and the high-k dielectric layer604, such as a thermal oxide layer. In other embodiments, the gate stack structure may also include an adhesion layer disposed between the second N-type work function metal layer902and the metal electrode layer1011, such as TiN, Ti, or a stacked structure including a combination of TiN and Ti.

In a specific embodiment, the capping layer602′ may include TiN or TiSiN. The first N-type work function metal layer901may include TiAl, TiCAl, TiNAl, TiSiAl, or any combinations thereof. The second N-type work function metal layer902may include TixAly, TixCzAly, TixNzAly, TixSizAly, or any combinations thereof, where x represents the ratio of atoms of Ti, y represents the ratio of atoms of Al, and x is greater than y.

In a specific embodiment, the capping layer602′ and the first N-type work function metal layer901are formed in the same station.

Embodiments of the present invention also provide an NMOS device that include the above-described gate stack structure11n, a source, a drain, and others.

Embodiments of the present invention also provide a semiconductor device including the above-described NMOS device having the above-described gate stack structure11nand a PMOS device having the above-described gate stack structure11p, a source, a drain, and others. Referring toFIG. 7andFIG. 11, the gate stack structures11nand11pmay be formed in respective first and second trenches5011and5012. The first and second trenches5011and5012may include respective first and second fins (not shown). The gate stacks11nand11pmay be formed on a top surface and side surfaces of the fins.

FIG. 12is a simplified flowchart of a method120for manufacturing a semiconductor device according to an embodiment of the present invention. The method120may include the following process steps:

At1202: providing a substrate including an NMOS region and a PMOS region.

At1204: sequentially forming on the substrate a high-k dielectric layer, a capping layer, a barrier layer, and a P-type work function metal layer on the substrate.

At1206: removing a portion of the P-type work function metal layer, a portion of the barrier layer, and a portion of the capping layer in the NMOS region.

At1208: forming a new capping layer on a portion of the high-k dielectric layer over the NMOS region.

At1210: forming an N-type work function metal layer on the new capping layer and on the P-type work function metal layer on the PMOS region.

At1212: forming a metal electrode layer on the N-type work function metal layer. The process of forming the new capping layer and the process of forming the N-type work function metal layer are performed in the same station.

The materials for each layers have been described in the sections above and will not be repeated herein for the sake of brevity.

In the embodiment, the capping layer is first removed, a new capping layer is then formed in the same station used for forming the first N-type work function metal layer, so that the oxygen absorption by the capping layer can be minimized or avoided, that will reduce or prevent, in turn, the oxidation of the N-type work function metal layer. The thus formed NMOS device has a stable work function and a threshold voltage.