Wiring substrate

A wiring substrate includes: a wiring member that includes a first surface and a second surface, the wiring member including a plurality of wiring layers between the first surface and the second surface; and a carrier that is bonded to the first surface via an adhesive and that includes a plurality of layers whose coefficients of thermal expansion are different from each other. A pitch of wires included in the plurality of wiring layers is narrower on the second surface side than on the first surface side. When being heated, a direction in which the wiring member tends to warp and a direction in which the carrier tends to warp are opposite.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims priority to Japanese Patent Application No. 2018-109772, filed on Jun. 7, 2018, the entire contents of which are incorporated herein by reference.

FIELD

The embodiments discussed herein relate to a wiring substrate.

BACKGROUND

As one type of wiring substrates used for semiconductor packages, coreless substrates that do not include core substrates are known. Coreless substrates are suitable for reducing the thickness of the wiring substrates. Conversely, because a coreless substrate more easily deflects than a wiring substrate including a core substrate and does not easily maintain its shape, the coreless substrate is not easily handled. Accordingly, a coreless substrate may be bonded to a stiff carrier and then a semiconductor chip may be mounted. Adhesion to the carrier enhances handling of the core substrate.

Patent Documents

However, when a semiconductor chip is mounted, warpage may occur on a wiring substrate configured by adhering a coreless substrate to a carrier. Such warpage of a wiring substrate leads to a decrease in alignment accuracy with a semiconductor chip.

SUMMARY

According to one aspect, a wiring substrate includes: a wiring member that includes a first surface and a second surface, the wiring member including a plurality of wiring layers between the first surface and the second surface; and a carrier that is bonded to the first surface via an adhesive and that includes a plurality of layers whose coefficients of thermal expansion are different from each other. A pitch of wires included in the plurality of wiring layers is narrower on the second surface side than on the first surface side. When being heated, a direction in which the wiring member tends to warp and a direction in which the carrier tends to warp are opposite.

DESCRIPTION OF EMBODIMENTS

The inventors of the present invention have conducted an earnest investigation to find the cause of warpage that occurs on a wiring substrate when mounting a semiconductor chip. Then, as a result of the detailed analysis by the inventors of the present invention, it has been found that a carrier itself does not easily warp even when the temperature changes during conveyance or reflow, and a wiring substrate including wiring layers and insulating layers cannot be sufficiently prevented from warping. That is, because of a high symmetry of the internal structure of the carrier, the carrier thermally expands or thermally shrinks simply isotropically but does not easily warp. Here, this new finding will be described with reference to a reference example.

FIGS. 1A to 1Care cross-sectional views illustrating a reference example of a method of manufacturing wiring substrates.FIGS. 2A to 2Care cross-sectional views illustrating the reference example of a method of manufacturing a semiconductor package using a wiring substrate.

In this reference example, as illustrated inFIG. 1A, wiring members20are formed on both main surfaces of a support10by a build-up method. A plurality of wiring layers and insulating layers are included in the wiring members20but are not illustrated here. Then, carriers30are bonded to the wiring members20via adhesives40, as illustrated inFIG. 1B. Thereafter, as illustrated inFIG. 1C, the wiring members20are separated from the support10. In this manner, structures including the wiring members20and the carriers30are obtained. Then, by cutting such a structure into a plurality of pieces by a slicer or the like, a plurality of wiring substrates9are manufactured. Note thatFIGS. 1A to 1Cillustrate only an area that becomes the wiring substrates9after being cut.

In a case where a semiconductor package is manufactured using a wiring substrate9, as illustrated inFIG. 2A, a semiconductor chip50is mounted on the wiring substrate9via bumps51, and reflow is performed. Then, as illustrated inFIG. 2B, a resin sealing process using a thermosetting sealing resin52is performed. Thereafter, as illustrated inFIG. 2C, the carrier30and the adhesive40are peeled off to form bumps53on the surface opposite the surface of the wiring member20on which the semiconductor chip50is mounted.

In this manner, a semiconductor package can be manufactured.

In this reference example, as illustrated inFIG. 3A, the wiring member20is thermally defamed into a concave shape (downwardly protruding shape) during being heated, and, as illustrated inFIG. 3B, the carrier30is uniformly thermally expanded during being heated. In this case, the warpage of the wiring substrate9is smaller than the warpage of the wiring member20as illustrated inFIG. 3C, but is not eliminated. Accordingly, the wiring member20warps to a similar extent. In a case where the wiring member20is thermally deformed into a convex shape (upwardly protruding shape) during being heated, similarly, the warpage of the wiring substrate9and the wiring member20is not eliminated.

Focusing on the method of manufacturing a semiconductor package, the warpage of the wiring substrate9may be noticeable during reflow and a positional deviation may occur between the bumps51and the wiring member20. Also, due to the warpage of the wiring member20, a wiring layer inside the wiring member20may be damaged or broken. Further, in a case where the wiring member20is conveyed at a high temperature before the semiconductor chip50is mounted, there is a possibility that, during being conveyed, the wiring member20warps, swings in a conveyance rack, and falls from the conveyance rack. Also, even in a case where the semiconductor chip50is properly mounted, the appearance may be poor due to the warpage.

Although it is considered to use a thick carrier in order to suppress the warpage of the wiring member20, the use of a thick carrier may significantly increase a cost. In addition, the stiffness of the carrier itself may be excessively high, and deformation of the wiring member may occur when the carrier is peeled off.

At least, these phenomena have not been elucidated with respect to a wiring substrate on which a carrier is bonded to the opposite side from a wiring member with respect to a support, and no measures for these have been taken. In such a situation, as a result of earnest investigation by the inventors of the present invention, it was found that the use of a carrier with an appropriate coefficient of thermal expansion in accordance with a manner of thermal deformation of a wiring member can sufficiently suppress warpage of a wiring substrate when mounting a semiconductor chip.

The following embodiments based on these new findings of the inventors of the present invention will be described. In the following, the embodiments will be described with reference to the accompanying drawings. Note that in the specification and the drawings, substantially same constituent elements may be referred to by the same reference numerals, and duplicate descriptions may be omitted as appropriate.

First Embodiment

A first embodiment will be described. The first embodiment relates to a wiring substrate.

First, a structure of a wiring substrate1will be described.FIG. 4is a plan view illustrating the structure of the wiring substrate1according to the first embodiment, andFIG. 5is a cross-sectional view illustrating the structure of the wiring substrate1according to the first embodiment.FIG. 5corresponds to a cross-sectional view taken along the line I-I inFIG. 4.

As illustrated inFIG. 4, the wiring substrate1according to the first embodiment is a sheet-shaped wiring substrate having a plurality of areas surrounded by double-dot chain lines C. The wiring substrate1is subjected to processes such as mounting semiconductor chips and forming sealing resins. Then, the support is removed. Finally, the wiring substrate1is cut along the double-dot chain lines C to be a plurality of separated semiconductor packages. Note that in the example illustrated inFIG. 4, the wiring substrate1has eighteen areas surrounded by the double-dot chain lines C, but the number of areas is not limited to eighteen.

As illustrated inFIG. 5, the wiring substrate1includes a wiring member200and a carrier300. The wiring member200includes a first surface200A and a second surface200B, and the carrier300is bonded to the first surface200A via an adhesive400.

The wiring member200includes a wiring layer201, an insulating layer202, a wiring layer204, an insulating layer205, and a wiring layer207. The wiring layer204is located between the wiring layer201and the wiring layer207, the wiring layer201is located on the second surface200B side of the wiring layer204, and the wiring layer207is located on the first surface200A side of the wiring layer204. Via holes203are formed on the insulating layer202and parts of the wiring layer204are connected to the wiring layer201through the via holes203. Also, via holes206are formed on the insulating layer205and parts of the wiring layer207are connected to the wiring layer204through the via holes206. The pitch of wires included in the wiring layer201is narrower than the pitch of wires included in the wiring layer204, and the pitch of wires included in the wiring layer204is narrower than the pitch of wires included in the wiring layer207.

For example, copper (Cu) or a copper alloy can be used as a material of the wiring layers201,204, and207. As a material of the insulating layers202and205, for example, an insulating resin such as an epoxy resin or a polyimide resin, or a resin material obtained by mixing a filler such as silica or alumina into such an insulating resin can be used. Also, as a material of the insulating layers202and205, for example, an insulating resin including a reinforced material obtained by impregnating the reinforced material such as a woven fabric such as glass, aramid, or a Liquid Crystal Polymer (LCP) fiber or a non-woven fabric with a thermosetting resin mainly composed of an epoxy resin or a polyimide resin may be used. Note that an insulating resin having a thermosetting property or an insulating resin having a photosensitive property can be used as a material of the insulating layers202and205.

The second surface200B side of the insulating layer202is covered by a solder resist layer210, and opening portions211, which expose parts of the wiring layer201, are formed on the solder resist layer210. The first surface200A side of the insulating layer205is covered by a solder resist layer208, and opening portions209, which expose parts of the wiring layer207, are formed on the solder resist layer208.

As a material of the solder resist layers208and210, for example, a photosensitive dry film resist or a liquid photoresist (for example, a dry film resist such as an novolac resin or an acrylic resin or a liquid resist) is used. Note that the solder resist layer210may not be formed.

In the present embodiment, when the wiring member200is heated, the second surface200B is thermally expanded larger than the first surface200A. That is, by being heated, the wiring member200is thermally deformed into a convex shape on the carrier300. The manner of thermal deformation of the wiring member200depends on the materials and the thicknesses of the wiring layers201,204and207, and the materials and the thicknesses of the insulating layers202and205, and the like.

The carrier300includes a first layer301, a second layer302above the first layer301, and a third layer303above the second layer302. The first layer301and the second layer302are bonded to each other by an adhesive311, and the second layer302and the third layer303are bonded to each other by an adhesive312. The coefficient of thermal expansion of the second layer302is lower than the coefficient of thermal expansion of the first layer301, and the coefficient of thermal expansion of the third layer303is lower than the coefficient of thermal expansion of the second layer302. For example, the coefficient of thermal expansion of the first layer301is in a range of from 24 ppm/° C. to 29 ppm/° C., the coefficient of thermal expansion of the second layer302is in a range of from 20 ppm/° C. to 23 ppm/° C., and the coefficient of thermal expansion of the third layer303is in a range of from 15 ppm/° C. to 19 ppm/° C.

For example, a polyimide film can be used as the first layer301, the second layer302, and the third layer303. Also, as the first layer301, the second layer302, and the third layer303, a copper plate or copper foil may be used, and an aluminum plate or aluminum foil may be used. As a material of the adhesives311and312, for example, a material whose adhesion is decreased by ultraviolet radiation can be used. Also, as a material of the adhesives311and312, for example, an adhesive that hardens at an ambient temperature or a cold temperature or a thermosetting adhesive can be used.

In the wiring substrate1, the third layer303is bonded to the first surface200A by an adhesive400. As a material of the adhesive400, for example, a material whose adhesion is decreased by ultraviolet radiation can be used. Also, as a material of the adhesive400, for example, an adhesive that hardens at an ambient temperature or a cold temperature or a thermosetting adhesive can be used.

In a case where a material whose adhesion is decreased by ultraviolet radiation is used as each of the adhesive311, the adhesive312, and the adhesive400, the sensitivity to ultraviolet light of the adhesive312may be lower for than that of the adhesive311and the sensitivity to ultraviolet light of the adhesive400may be lower than that of the adhesive312. In other words, the adhesive312is less easily peeled off due to ultraviolet than the adhesive311, and the adhesive400is less easily peeled off due to ultraviolet radiation than the adhesive312.

Also, in a case where an adhesive that hardens at an ambient temperature or a cold temperature or a thermosetting adhesive is used as each of the adhesive311, the adhesive312, and the adhesive400, the strength of adhesion of the adhesive312may be lower than that of the adhesive400, and the strength of adhesion of the adhesive311may be lower than that of the adhesive312. In other words, the adhesive312is less easily peeled off due to ultraviolet than the adhesive311, and the adhesive400is less easily peeled off due to ultraviolet radiation than the adhesive312.

In this manner, by changing the sensitivities and/or the strengths of the adhesive311, the adhesive312, and the adhesive400in a stepwise manner, the warpage of the carrier300with respect to the warpage of the wiring member200can be easily adjusted.

Next, thermal deformation of the wiring substrate1according to the first embodiment will be described.FIGS. 6A to 6Care schematic views illustrating an example of thermal deformation of the wiring substrate1according to the first embodiment.

In the present embodiment, as illustrated inFIG. 6A, upon being heated, the wiring member200tends to be thermally deformed into a convex shape. With respect to the carrier300, the thermal expansion coefficient of the second layer302is lower than the thermal expansion coefficient of the first layer301, and the thermal expansion coefficient of the third layer303is lower than the thermal expansion coefficient of the second layer302. Accordingly, as illustrated inFIG. 6B, upon being heated, the carrier300tends to be thermally deformed into a concave shape. That is, when being heated, the direction in which the wiring member200tends to warp and the direction in which the carrier300tends to warp are opposite. Also, the wiring member200is bonded to the carrier300by the adhesive400. Therefore, thermal deformation of the wiring member200and thermal deformation of the carrier300are restrained each other, the warpage of the wiring member200and the warpage of the carrier300are canceled out each other, and the warpage of the wiring substrate1is significantly suppressed, as illustrated inFIG. 6C. Because the warpage of the wiring substrate1is suppressed, the warpage of the wiring member200is also suppressed.

In this manner, according to the present embodiment, the warpage of the wiring member200due to being heated can be remarkably suppressed. Accordingly, as will be described below, semiconductor chips can be precisely aligned during a process of manufacturing semiconductor packages. Also, it is possible to reduce or prevent conveyance failure and appearance failure due to warpage of the wiring substrate1.

Also, in the present embodiment, the pitch of the wires included in the wiring layer201is narrower than the pitch of the wires included in the wiring layer207. Accordingly, the present embodiment can be used to mount semiconductor chips having a narrow pitch of pads (external terminals).

Note that it is preferable that the stiffness of the first layer301, the second layer302, and the third layer303is lower than the stiffness of the wiring member200. This is because if the stiffness of the first layer301, the second layer302, and the third layer303is excessively high, there is a possibility that the wiring member200is deformed when the carrier300is peeled off from the wiring member200in the manufacturing process of semiconductor packages.

[Method of Manufacturing Wiring Substrates]

Next, a method of manufacturing wiring substrates1will be described.FIGS. 7 to 12are diagrams illustrating a method of manufacturing wiring substrates according to the first embodiment.

First, a support100is provided as illustrated inFIGS. 7A and 7B.FIG. 7Ais a plan view, andFIG. 7Bis a cross-sectional view taken along the line I-I inFIG. 7A. The support100includes a support substrate101, adhesive layers102, and metal layers103. The adhesive layers102and the metal layers103are provided on both surfaces of the support substrate101.

As the support substrate101, for example, a material obtained by impregnating a woven fabric such as a glass fiber or an aramid fiber or a non-woven fabric (not illustrated) with an insulating resin such as an epoxy-based resin can be used. As the adhesion layers102, for example, metal foil such as copper foil, aluminum foil, nickel foil, or zinc foil, a ceramic plate, a resin sheet mainly composed of an acrylic resin or a polyimide resin, or the like can be used. For example, copper foil or the like may be used as the metal layers103.

InFIG. 7A, respective areas surrounded by the double-dot chain lines D indicate areas that becomes sheet-shaped wiring substrates1. That is, the respective areas surrounded by the double-dot chain lines D are cut along the double-dot chain lines D to be the plurality of separated sheet-shaped wiring substrates1(seeFIG. 4andFIG. 5). The respective areas surrounded by the double-dot chain lines D are arranged inside areas with respect to the outer edge of the support100in a plan view. Note that althoughFIG. 7Aillustrate eight areas surrounded by the double-dot chain lines D, the number of areas is not limited to eight.

Note that in the following, processes will be described with reference to a cross-sectional view of an area (corresponding to an area surrounded by the double-dot chain lines C inFIG. 4) to be a semiconductor package by being separated finally within an area to be one wiring substrate1surrounded by the double-dot chain lines D inFIG. 7A. Also, in the following description, the term “on” or “above” may refer to a direction away from the support100with respect to support100.

After preparation of the support100, the wiring layers201are formed on the metal layers103with respect to both sides of the support100, as illustrated inFIG. 8A. The wiring layers201can be formed, for example, by a semi-active method. For example, resist layers having openings at desired locations are formed on the surfaces of the metal layers103. The openings are formed so as to expose portions of the metal layers103corresponding to the wiring layers201. As a material of the resist layers, a material such as a photosensitive dry film resist or a liquid photoresist (for example, a dry film resist such as an novolac resin or an acrylic resin or a liquid resist) can be used. Subsequently, using the resist layers as plating masks, to the surfaces of the metal layers103, electrolytic plating (electrolytic copper plating) using the metal layers103as plating feeder layers is applied to form the wiring layers201. The resist layers are then removed, for example, with an alkaline peeling liquid.

Then, as illustrated inFIG. 8B, the insulating layers202that cover the wiring layers201are formed on the metal layers103with respect to both sides of the support100. In forming the insulating layers202, for example, an uncured resin film is applied, heat treated, and cured. The insulating layers202are formed of an insulating resin such as, for example, an epoxy resin or a polyimide resin. The insulating layers202may be formed by applying a liquid resin.

Thereafter, with respect to both sides of the support100, the via holes203that penetrate the insulating layers202and that expose parts of the wiring layers201are formed on the insulating layers202. The via holes203can be foamed, for example, by laser processing using a CO2laser or the like. A desmear process may be performed as needed.

Subsequently, with respect to both sides of the support100, the wiring layers204, which are connected to the wiring layers201through the via holes203, are formed on the insulating layers202. The wiring layers204can be formed, for example, by a semi-active method. For example, first, seed layers are formed on the upper surfaces of the insulating layers202by an electroless plating method. Resist layers having opening portions at predetermined locations are formed on the seed layers. As a material of the resist layers, a material such as a photosensitive dry film resist or a liquid photoresist (for example, a dry film resist such as an novolac resin or an acrylic resin or a liquid resist) can be used. Subsequently, using the resist layers as plating masks, electrolytic plating (electrolytic copper plating) using the seed layers as plating feeder layers is applied to form electrolytic plating layers. Then, the resist layers are removed by an alkaline peeling liquid, and the unnecessary seed layers are removed using the electrolytic plating layers as etching masks. Thereby, the wiring layers204are formed.

After forming the wiring layers204, as illustrated inFIG. 9A, the insulating layers205that cover the wiring layers204are formed on the insulating layers202with respect to both sides of the support100. The insulating layers205can be formed by a method similar to the method of forming the insulating layers202. Thereafter, the via holes206that penetrate the insulating layers205and that expose parts of the wiring layers204are formed on the insulating layers205. The via holes206can be formed by a method similar to the method of forming the via holes203. Subsequently, the wiring layers207, which are connected to the wiring layers204through the via holes206, are formed on the insulating layers205. The wiring layers207can be formed by a method similar to the method of forming the wiring layers204.

Then, as illustrated inFIG. 9B, with respect to both sides of the support100, the solder resist layers208having the opening portions209are formed on the insulating layers205. The solder resist layers208can be obtained, for example, by laminating a photosensitive resin film or by applying a liquid resin or a paste resin and exposing and developing the resin by photolithography to pattern it into a desired shape. Through the opening portions209, parts of the upper surfaces of the wiring layers207are exposed as external connection terminals. In this manner, the wiring members200are obtained on both sides of the support100.

Thereafter, as illustrated inFIG. 10, with respect to both sides of the support100, the carriers300, which are prepared in advance, are bonded to the first surfaces200A of the wiring members200by the adhesives400so as to cover the entire surfaces of the solder resist layers208. At this time, the carriers300adhere to the first surfaces200A of the wiring members200such that the third layers303are in contact with the adhesives400.

Then, the wiring members200are separated from both sides of the support100as illustrated inFIG. 11.

Subsequently, as illustrated inFIG. 12, the solder resist layer210having the opening portions211is formed on the insulating layer202. The solder resist layer210can be formed by a method similar to the method of forming the solder resist layers208. Note thatFIG. 12illustrates only one of the wiring members200.

Subsequently, the structure illustrated inFIG. 12is cut by a slicer or the like along the double-dot chains lines D inFIG. 7. Thus, the structure illustrated inFIG. 12is separated into pieces, and a plurality of wiring substrates1according to the first embodiment are obtained. In this manner, the wiring substrates1according to the first embodiment can be manufactured.

According to such a method, because the wiring layers201with a narrow pitch of wires are formed on the support100side prior to the wiring layers207with a wide pitch of wires, wiring substrates1suitable for mounting semiconductor chips with a narrow pitch of pads can be easily manufactured.

Note that it is preferable that the materials and the thicknesses of the first layer301, the second layer302, and the third layer303are selected as appropriate so as to prevent warpage of the wiring member200, for example, through a simulation using a finite element method. Also, after the selection through the simulation, it is preferable to actually manufacture semiconductor packages by a method that will be described below, to feedback the results, and to use more suitable materials and thicknesses, and the like.

Second Embodiment

Next, a second embodiment will be described. The second embodiment relates to a method of manufacturing semiconductor packages using a wiring substrate1according to the first embodiment.FIG. 13toFIG. 16are diagrams illustrating the method of manufacturing the semiconductor packages according to the second embodiment.

In the second embodiment, semiconductor chips500are first flip-chip mounted on the wiring substrate1via bumps501, as illustrated inFIG. 13. Specifically, by reflow, the wiring layer207exposed from the opening portions211of the wiring substrate1and pads (not illustrated) of the semiconductor chips500are joined through the bumps501. For example, a solder ball or the like may be used as the bumps501. As a material of the solder ball, for example, an alloy such as an alloy containing Pb, an alloy of Sn and Cu, an alloy of Sn and Sb, an alloy of Sn and Ag, an alloy of Sn and Ag, or an alloy of Ag and Cu may be used. Note that a gap between the semiconductor chips500and the wiring member200may be filled with an underfill resin. The temperature of the reflow is, for example, in a range of from 200° C. to 250° C. As the temperature rises during reflow, the wiring member200tends to warp in a convex shape and the carrier300tends to warp in a concave shape. Because the directions in which warpage tends to occur are opposite the warpage of the entire substrate1is suppressed. Also, as the temperature drops after the reflow, the wiring member200and the carrier300tend to return to a flat shape. At this time, because the direction in which the wiring member200tends to warp and the direction in which the carrier300tends to warp are also opposite, the warpage of the entire wiring substrate1is suppressed. Accordingly, thermal deformation of the wiring substrate1during the reflow process is suppressed.

Thereafter, similarly to the second embodiment, as illustrated inFIG. 14, sealing resins502that seal the semiconductor chips500and the bumps501are formed by a transfer mold method using a sealing mold or the like. As the sealing resins502, an insulating resin (which may be referred to as a mold resin) such as a thermosetting epoxy resin containing a filler, for example, can be used. The sealing resins502are then heated to harden. The heating temperature at this time is, for example, between 130° C. and 170° C. During this heating, as the temperature rises, the wiring member200tends to warp in a convex shape and the carrier300tends to warp in a concave shape. Thus, because the directions in which warpage tends to occur are opposite, the warpage of the entire wiring substrate1is suppressed. Also, as the temperature drops after the heating, the wiring member200and the carrier300tend to return to a flat shape. At this time also, because the direction in which the wiring member200tends to warp and the direction in which the carrier300tends to warp are also opposite, the warpage of the entire wiring substrate1is suppressed. Accordingly, thermal deformation of the wiring substrate1during the sealing resin formation process is suppressed.

Thereafter, as illustrated inFIG. 15, the carrier300is peeled off from the wiring member200. Subsequently, bumps503are formed on the lower surface of the wiring layer207. For example, a solder ball or the like may be used as the bumps503. As a material of the solder ball, for example, an alloy such as an alloy containing Pb, an alloy of Sn and Cu, an alloy of Sn and Sb, an alloy of Sn and Ag, an alloy of Sn and Ag, or an alloy of Ag and Cu may be used.

Subsequently, as illustrated inFIG. 16, the structure illustrated inFIG. 15is cut by a slicer or the like along the double-dot chains lines C. Thus, the structure illustrated inFIG. 15is separated into pieces, and a plurality of semiconductor packages5are obtained. In this manner, the semiconductor packages5can be manufactured.

Third Embodiment

Next, a third embodiment will be described. The third embodiment relates to a method of manufacturing semiconductor packages using a wiring substrate1according to the first embodiment.FIG. 17toFIG. 20are diagrams illustrating the method of manufacturing the semiconductor packages according to the third embodiment.

In the third embodiment, similarly to the second embodiment, the semiconductor chips500are first flip-chip mounted on the wiring substrate1via the bumps501, as illustrated inFIG. 17. Specifically, by reflow, the wiring layer207exposed from the opening portions211of the wiring substrate1and pads (not illustrated) of the semiconductor chips500are joined through the bumps501. Similarly to the second embodiment, thermal deformation of the wiring substrate1during the reflow process is suppressed.

The first layer301is then peeled off from the second layer302together with the adhesive311, as illustrated inFIG. 18.

Thereafter, similarly to the second embodiment, as illustrated inFIG. 19, the sealing resins502that seal the semiconductor chips500and the bumps501are formed by a transfer mold method using a sealing mold or the like. As the sealing resins502, an insulating resin (which may be referred to as a mold resin) such as a thermosetting epoxy resin containing a filler, for example, can be used. The sealing resins502are then heated to harden. The heating temperature at this time is, for example, between 130° C. and 170° C.

Thereafter, as illustrated inFIG. 20, the carrier300is peeled off from the wiring member200. Subsequently, the bumps503are formed on the lower surface of the wiring layer207. The structure illustrated inFIG. 20is cut by a slicer or the like along the double-dot chains lines C. Thus, the structure illustrated inFIG. 20is separated into pieces, and a plurality of semiconductor packages5are obtained. In this manner, the semiconductor packages5can be manufactured.

After mounting the semiconductor chips500, thermal deformation of the wiring member200may be restrained by the semiconductor chips500. Accordingly, depending on the restraint strength from the semiconductor chips500, the thermal deformation of the first layer301may be excessive with respect to the restraint of the thermal deformation of the wiring member200. In the present embodiment, because the first layer301is peeled off prior to a heating process to harden the sealing resins502, the thermal deformation of the wiring member200can be suppressed in an appropriate balance. Note that depending on the restraint strength from the semiconductor chips500, not only the first layer301but also the second layer302may be peeled off.

Fourth Embodiment

Next, a fourth embodiment will be described. The fourth embodiment relates to a wiring substrate.

First, a structure of a wiring substrate2will be described.FIG. 21is a cross-sectional view illustrating the structure of the wiring substrate2according to the fourth embodiment.

With respect to the wiring substrate2according to the fourth embodiment, when the wiring member200is heated, the first surface200A is thermally expanded larger than the second surface200B. That is, by being heated, the wiring member200is thermally deformed into a concave shape. The manner of thermal deformation of the wiring member200depends on elements such as the materials and the thicknesses of the wiring layers201,204and207and the materials and the thicknesses of the insulating layers202and205, and, for example, differs from the first embodiment in at least one of these elements.

Also, as illustrated inFIG. 21, the configuration of the carrier300itself is similar to that of the first embodiment, but in the wiring substrate2, the first layer301is bonded to the first surface200A by the adhesive400. That is, assuming that the wiring member200is above the carrier300, the carrier300includes the third layer303, the second layer302above the third layer303, and the first layer301above the second layer302. The first layer301and the second layer302are bonded to each other by the adhesive311, and the second layer302and the third layer303are bonded to each other by the adhesive312. The coefficient of thermal expansion of the second layer302is lower than the coefficient of thermal expansion of the first layer301, and the coefficient of thermal expansion of the third layer303is lower than the coefficient of thermal expansion of the second layer302. For example, the coefficient of thermal expansion of the first layer301is in a range of from 24 ppm/° C. to 29 ppm/° C., the coefficient of thermal expansion of the second layer302is in a range of from 20 ppm/° C. to 23 ppm/° C., and the coefficient of thermal expansion of the third layer303is in a range of from 15 ppm/° C. to 19 ppm/° C.

Other configurations of the fourth embodiment are similar to those of the first embodiment.

Next, thermal deformation of the wiring substrate2according to the fourth embodiment will be described.FIGS. 22A to 22Care schematic views illustrating an example of thermal deformation of the wiring substrate2according to the fourth embodiment.

In the present embodiment, as illustrated inFIG. 22A, upon being heated, the wiring member200tends to be thermally deformed into a concave shape. Accordingly, as illustrated inFIG. 22B, upon being heated, the carrier300tends to be thermally deformed into a convex shape. That is, when being heated, the direction in which the wiring member200tends to warp and the direction in which the carrier300tends to warp are opposite. Also, the wiring member200is bonded to the carrier300by the adhesive400. Therefore, thermal deformation of the wiring member200and thermal deformation of the carrier300are restrained each other, the warpage of the wiring member200and the warpage of the carrier300are canceled out each other, and the warpage of the wiring substrate2is significantly suppressed, as illustrated inFIG. 22C. Because the warpage of the wiring substrate2is suppressed, the warpage of the wiring member200is also suppressed. Also, as the temperature drops after the heating, the wiring member200and the carrier300tend to return to a flat shape. At this time, because the direction in which the wiring member200tends to warp and the direction in which the carrier300tends to warp are also opposite, the warpage of the entire wiring substrate2is suppressed.

In this manner, according to the present embodiment, the warpage of the wiring member200due to heat can be remarkably suppressed. Accordingly, similarly to the first embodiment, semiconductor chips can be precisely aligned during a process of manufacturing semiconductor packages. Also, it is possible to reduce or prevent conveyance failure and appearance failure due to warpage of the wiring substrate2.

[Method of Manufacturing Wiring Substrates]

Next, a method of manufacturing wiring substrates2will be described.FIG. 23toFIG. 25are diagrams illustrating the method of manufacturing the wiring substrates2according to the fourth embodiment.

First, similarly to the first embodiment, the support100is provided, and the wiring members200are formed on both sides of the support100(seeFIG. 9B). Thereafter, as illustrated inFIG. 23, with respect to both sides of the support100, the carriers300, which are prepared in advance, are bonded to the first surfaces200A of the wiring members200by the adhesives400so as to cover the entire surfaces of the solder resist layers208. At this time, the carriers300adhere to the first surfaces200A of the wiring members200such that the third layers303are in contact with the adhesives400.

Thereafter, as illustrated inFIG. 24, the wiring members200are separated from both sides of the support100.

Subsequently, as illustrated inFIG. 25, the solder resist layer210having the opening portions211is formed on the insulating layer202. The solder resist layer210can be foamed by a method similar to the method of forming the solder resist layers208. Note thatFIG. 25illustrates only one of the wiring members200.

Subsequently, the structure illustrated inFIG. 25is cut by a slicer or the like along the double-dot chains lines D inFIG. 7. Thus, the structure illustrated inFIG. 25is separated into pieces, and a plurality of wiring substrates2according to the fourth embodiment are obtained. In this manner, the wiring substrates2according to the fourth embodiment can be manufactured.

According to such a method, because the wiring layers201with a narrow pitch of wires are formed on the support100side prior to the wiring layers207with a wide pitch of wires, wiring substrates2suitable for mounting semiconductor chips with a narrow pitch of pads can be easily manufactured.

By a method similar to that of the second or third embodiment, semiconductor packages can be manufactured by using the wiring substrate2. In this case, warpage can also be suppressed.

Note that the number of layers included in a carrier is not limited to three, and may be two or four or more. In a case where the number of layers included in a carrier is three or more, it is preferable that in accordance with the direction in which a wiring member tends to warp, the coefficient of thermal expansion decreases or increases with decreasing distance to the wiring member.

Also, in these embodiments, a flat wiring substrate is obtained by the warpage of a wiring member and the warpage of a carriers being canceled out each other. Therefore, for the carrier, delicate control of the coefficient of thermal expansion is needed. If the number of layers contained in the carrier is one or two, the amount of warping is required to be adjusted by adjusting the material and the thickness of each layer, and it is difficult to control to cancel the warpage of a wiring member. However, in a case where the number of layers contained in the carrier is three or more, because the coefficient of thermal expansion (material) and the thickness of the intermediate layer can be adjusted, the coefficient of thermal expansion can be delicately controlled to cancel out the warpage of the wiring member.

Various aspects of the subject-matter described herein may be set out non-exhaustively in the following numbered clauses:

1. A method of manufacturing a wiring substrate, the method comprising:

forming, on a support, a wiring member including a first surface and a second surface such that the second surface is toward the support, the wiring member including a plurality of wiring layers between the first surface and the second surface;

bonding a carrier to the first surface via an adhesive, the carrier including a plurality of layers whose coefficients of thermal expansion are different from each other; and

separating the wiring member from the support;

wherein a pitch of wires included in the plurality of wiring layers is narrower on the second side than on the first side, and

wherein, when being heated, a direction in which the wiring member tends to warp and a direction in which the carrier tends to warp are opposite.

2. The method of clause1, further comprising:

mounting a semiconductor chip on the wiring member;

sealing the semiconductor chip; and

peeling off the carrier from the wiring member after sealing the semiconductor chip.

3. The method of clause2, further comprising:

between the mounting the semiconductor chip and the sealing the semiconductor chip, peeling off part of the layers included in the carrier.

Although the preferred embodiments and the like have been described above in detail, the present invention is not limited to the embodiments and the like described above, and various variations and substitutions may be made for the embodiments and the like described above without departing from the scope of the present invention.