Emulation of static random access memory (SRAM) by magnetic random access memory (MRAM)

A magnetic memory system includes a magnetic random access memory (MRAM) including a plurality of magnetic memory banks and operative to store data during a write operation initiated by a write command. The magnetic memory system further includes a first-in-first-out (FIFO) interface device coupled to the MRAM and including a plurality of FIFOs Each of the magnetic memory banks is coupled to a respective one of the plurality of FIFOs, the FIFO being operative to queue write commands on a per magnetic memory bank basis and further operative to issue the queued write commands at a time when the MRAM is not in use, wherein concurrent write operations are performed to at least two of the plurality of magnetic memory banks.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to magnetic memory devices including magnetic random access memory (MRAM) elements for data storage and particularly to magnetic memory devices used to emulate static random access memories (SRAMs).

2. Description of the Prior Art

Static random access memory (SRAM) has been used prevalently throughout the recent decades for storage of binary information or data in applications such as computers, handheld devices among many other electronics applications. SRAMs have fast read and write access times making them excellent candidates for applications in need of such requirements. For example, as central processing units (CPUs) have acquired increased speeds, faster memory has been required to keep up with them—SRAMs fit this bill. Similarly, as electronic devices have decreased in size, so have size requirements of SRAMs.

However, due to manufacturing constraints, limitations of manufacturing SRAMs in terms of size and speed have been anticipated and are now being experienced. Thus, devices replacing SRAMs are highly sought-after devices. One such candidate is magnetic random access memory (MRAM). MRAMs have the advantage of being smaller in size, and being non-volatile where data or information stored therein is retained even after power is disconnected. Also, MRAM's read access time is comparable to that of SRAMs. But when it comes to writing/programming/storing of data, MRAM suffers from slower than that of SRAM. It is well known that the write access time of an MRAM is generally longer than its read access time. Thus, while MRAMs hold their own against SRAMs in terms of read access times, they cannot do the same in terms of write access times.

In an effort to compensate for MRAMs' longer write access time, current memory designs employ “burst” operations by increasing the number of data units written to memory. “Burst” refers to writing a number of data units during a write access operation or before the completion of a write operation. However, burst operations require data units to be sequential and because not all data or even most data is sequential, and additionally large bust sizes are not practical.

Thus, the need arises for a non-volatile memory device such as MRAM with comparable system performance to SRAM.

SUMMARY OF THE INVENTION

To overcome the limitations in the prior art described above, and to overcome other limitations that will become apparent upon reading and understanding the present specification, the present invention discloses a method and a corresponding structure for a magnetic memory system including magnetic tunnel junctions (MTJs) and structures and methods for causing such systems to replace SRAMs.

Briefly, an embodiment of the invention includes magnetic memory system comprises a magnetic random access memory (MRAM) including a plurality of magnetic memory banks and operative to store data during a write operation initiated by a write command. The magnetic memory system further includes a first-in-first-out (FIFO) interface device coupled to the MRAM and including a plurality of FIFOs Each of the magnetic memory banks is coupled to a respective one of the plurality of FIFOs, the FIFO being operative to queue write commands on a per magnetic memory bank basis and further operative to issue the queued write commands at a time when the MRAM is not in use, wherein concurrent write operations are performed to at least two of the plurality of magnetic memory banks.

These and other objects and advantages of the present invention will no doubt become apparent to those skilled in the art after having read the following detailed description of the preferred embodiments illustrated in the several figures of the drawing.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following description of the embodiments, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration of the specific embodiments in which the invention may be practiced. It is to be understood that other embodiments may be utilized because structural changes may be made without departing from the scope of the present invention. It should be noted that the figures discussed herein are not drawn to scale and thicknesses of lines are not indicative of actual sizes.

FIG. 1shows a magnetic memory system10in accordance with an embodiment of the invention. The system10is shown to include a magnetic random access memory (MRAM)12coupled to a first-in-first-out (FIFO) interface device14through a memory bus18(sometimes referred to herein as “datain”18). The device14is shown to receive Data_in16as input and generates a FIFO output coupled onto the bus18for storage in the MRAM12. The MRAM12generates the output mDO126for use by the device14, at times, device14couples the same onto Data_out20of the magnetic memory system10. At other times, the device14generates the output of the magnetic memory system10and couples the same onto Data_out20. The Data_out20serves as output of the system10, whereas the mDO126remains internal to the system10. While the general operation of the system10is described below relative toFIG. 1, it is described in further detail relative to subsequent figures.

The MRAM12typically includes many magnetic memory elements with each element including at least one magnetic tunnel junction (MTJ). An MTJ, as well known, typically is made of a free layer, separated by from a fixed layer by a barrier (or “tunnel”) layer. The fixed layer has a magnetic orientation that is fixed or permanent in a particular direction and while the free layer also has a magnetic orientation, its orientation switches relative to that of the fixed layer, when suitable electrical current flows through the MTJ. The switching of the free layer results in the MTJ storing different states, i.e. data.

A magnetic memory element is typically accessed through an access transistor, which together with the magnetic memory element is referred to as a magnetic memory cell. The magnetic memory cells comprise the MRAM12along with other non-magnetic circuitry used for reading and writing to the magnetic memory elements thereof.

Magnetic memory elements can be of a variety of types, such as but not limited to, spin-transfer torque, spin valve and other known magnetic memory.

It is well known that the time required to read information stored in a MRAM is fast and generally comparable to read a static random access memory (SRAM). It is equally well known that the time required to write information to MRAM is longer than that which is required for writing to a SRAM. For example, the time required to write to (write time) a SRAM is 1-10 nano seconds (ns) while the write time of a MRAM is 3-30 ns. In accordance with the various embodiments and methods of the invention, a user of the system10enjoys the use of MRAM with the benefits of comparable system performance of write operations. That is, memory performance of the system10is comparable to a system using SRAM, for example, by the system10effectively performing concurrent non-sequential write operations.

As will be shown in subsequent figures, the device14includes a FIFO, well known by those skilled in the art, and a FIFO logic block. The FIFO serves as a temporary location to load address and data from the outside (or by a user) and intended for storage in the MRAM12. The FIFO within the device14writes (or “stores”) and retrieves information in a certain order (for write to MRAM12). That is, data that is first input is output first such that any data that is saved after the first input is necessarily retrieved after the first data. By way of example, if data0is saved first followed by data1being saved and followed by data2being saved, the order in which this data is retrieved is the same in that first, data0is retrieved and then data1is retrieved and next data2is retrieved. In some embodiments, concurrent write operations are performed to multiple MRAM sub-arrays (or “banks”) comprising the MRAM12resulting in increased system performance. Further, write operations are queued per MRAM bank and queued write commands are issued by the FIFO at a later time, allowing multiple write operations to be performed without the requirement for sequential data. Data coherency is checked to return data from the queue of the device14rather than the MRAM12if the queue has the latest content at the accessed address (prior to writing to MRAM12). “Return” as used herein refers to outputting data.

It is contemplated that any device that achieves the function of device14may be used in place of device14.

The FIFO logic block within the device14serves to mediate the address and data that is loaded into the FIFO at a clock rate, “clks”, and also serves to send data out to the MRAM12for writing at another rate, “clkm”, in conjunction with a memory busy signal, in one embodiment of the present invention. In this case, the “clks” and the “clkm” need be synchronized in manners known to those in the art. Alternatively, a single clock is used by the FIFO logic block and the MRAM12, in conjunction with a memory busy signal, to send data out from the FIFO to the MRAM. To speed up the write operation, data is first stored or saved in the device14through the coupling of the incoming data onto the Data_in16and then saved into MRAM12in the order described above. This allows an overall faster write operation time of the magnetic memory system10because since writing is being accomplished through the device14, data can be read from the Data_out20with the net effect of the write operations of the system10being comparable to that of a system using SRAM. In accordance therewith, at times, such as when data has not had a chance to make it from the device14into the MRAM12before it is accessed by a user of the system10, it may be retrieved directly from the device14, as will become further evident below.

Accordingly, the magnetic memory system10generally functions as or emulates an SRAM or its variants, such as pseudo SRAMs, synchronous SRAMs, and double data rate synchronous static random access memory (DDR SRAM) with comparable system performance.

FIG. 2shows a block diagram of a portion of the system10, in accordance with an embodiment of the invention. The system10is shown to include a magnetic memory bank100having a magnetic random access memory (MRAM) sub-array (or “bank”)102and a portion of the interface14, bank interface104, coupled to the bank102through the memory bus18. The bank102is one of many MRAM banks in the MRAM12ofFIG. 1. The bank interface104, shown inFIG. 2, is responsive to interface signals112, which is a part of the Data_in16and the Data_out20ofFIG. 1. The signals112are shown to include an address114, an input data (Di)116, output data (Do)118, chip enable (CE*)120, write enable (WE*)122and busy (bsy*)124. Clock (CLK)110is shown provided, as input, to the bank interface104shown inFIG. 2. The interface104is shown to include FIFO106and in some embodiments, optionally includes pending read register108.

As will be appreciated by the discussion below, the FIFO106generally functions as a queue and in some embodiments, functions as a write queue for queuing commands and data during write operations.

The interface104is shown to be coupled to the bank102through a number of signals, which are a part of the bus18, namely, the memory Data out (mDo)126, the memory address (mA)128, the memory Data in (mDi)130, the memory chip enable (mCE*)132and the memory write enable (mWE*)134signals.

The address114is an address provided by the user of the system10and identifies a location in the system10where data is either retrieved or read. Di116is the data that is written or saved in the system10by a user of thereof and the Do118is data that is retrieved from the system10by the user. CE*120enables reading and/or writing to the system10and WE*122signals a write operation to the system10. The bsy*124signals to the user whether or not the system10is in use. In this embodiment CE*120and WE*122are synchronous to clk110.

The mDO126is data that is retrieved from the bank102, the mA128is the address that is provided to the bank102for identifying a location therein, the mDi130is the memory input data or data that is provide to the bank102to be saved therein. The mCE*132is the memory chip enable that enables use of the bank102and the mWE*134is the memory write enable signal that indicates whether or not a write operation to the bank102is taking place. In this embodiment mCE*132and WE*134are synchronous to clk110.

The mbsy*135signal is generated by the interface104and used internally to indicate whether the access time of the bank102is greater than one cycle, and a WAIT cycle need to be inserted to allow for proper completion of the write cycle. Accordingly, mbsy*135is asserted (or become active) on the first cycle of the write operation and is deasserted at the last cycle of the write operation.

The register108, which is optionally used in some embodiments, saves the incoming command during a read operation, when the memory102is busy, that is read command becomes pending and not yet complete, as further discussed below.

The operation of the signals and structures shown inFIG. 2is perhaps better understood relative to timing diagrams presented in subsequent figures and discussed later.

In one embodiment of the invention, the FIFO106stores units of data in fixed bursts of 1, 2 or 4 units of data, as an example.

In the case of a single MRAM bank operation, using the block diagram ofFIG. 2, various scenarios are presented and explained as follows. The following scenarios assume that a write operation to the MRAM12is longer or requires more clock cycles than that which is required for read operations. “Cycle”, as used herein, refers to a clock cycle, as readily known to those in the art.

One scenario is if the incoming command is a read command and a pending write operation (as indicated by the mCE*, mWE* and mbsy*135signals) is not in progress and the bank102is not being accessed, a read operation of the bank102is performed and the FIFO106is checked for an address match. An example of an address match is presented and discussed relative toFIG. 4. If there is a match, i.e. the pending write command in the FIFO106is to the same address as the one being read, the data in the FIFO106is returned (or coupled onto the Do118, otherwise, the data in the bank102is returned. This scenario is shown, in part, and discussed accordingly relative toFIG. 5, at reference number300.

Another scenario is if the incoming command is a read command and a pending write operation is in progress, the bsy*124is asserted and the read command is saved and becomes a pending read command (stored in the register108) because the bank102is not idle (or it is busy). The pending read command is executed after the completion of the pending write operation that is in progress. This scenario is shown, in part, and discussed accordingly relative toFIG. 5, at reference number324. Alternatively the FIFO106is checked for an address match, if there is a match the data in the FIFO106is returned else the bsy* is asserted, and the read command is saved and becomes a pending read command, which is executed after the completion of the pending write operation that is in progress.

Yet another scenario is if the incoming command is a read command and a pending write operation is in progress, the pending write operation is aborted and a read operation is preformed in the same cycle as the reception of the read command without asserting the bsy*124signal (or without waiting, i.e. no wait cycle required), and the FIFO is checked for an address match, as discussed above. That is, a match is detected if a pending write operation in the FIFO is taking place with the same address as that used in the read command, in which case, the data in the FIFO106is returned (or read), otherwise, the data in the bank102is returned. In the foregoing embodiment, register108is not required. Alternatively the FIFO106is checked for an address match, if there is a match the data in the FIFO106is returned and pending write in progress is not affected, else the pending write operation is aborted, and a read operation is preformed in the same cycle as the reception of the read command without asserting the bsy*124signal.

In yet another scenario, if an incoming command is a write command and the bank102is idle (or no pending commands are in progress) and the FIFO106is empty (no valid data is in the FIFO), the incoming command is saved in the FIFO106and optionally sent to the bank102to perform a write operation thereto. In the event this option is not taken, the current cycle is unused or wasted. This scenario is shown, in part, and discussed accordingly relative toFIG. 5, at reference number302.

In another scenario, if the incoming command is a write operation and the bank102is idle (no pending commands are in progress) and the FIFO106is not empty, the incoming command is saved in the FIFO106and a pending command in the FIFO106(from the top of the FIFO) is sent to the bank102to perform a write operation thereto.

In yet another scenario, if an incoming command is a write command and the FIFO106is near full, the incoming command is saved in the FIFO106and the bsy*124is asserted and a pending command in the FIFO106(top of the FIFO) is sent to the bank102to perform a write operation thereto. Near full conditions are readily known to those in the art to be a predefined threshold at or above which the FIFO is considered or declared to be full. Generally, the function of a near full condition is to allow queuing of at least one more command to the FIFO. This scenario is shown, in part, and discussed accordingly relative toFIG. 6.

In yet another scenario, if the incoming command is a no operation (or “NOP” CE* not asserted), and the bank102is idle and the FIFO106is not empty, a pending command in the FIFO (top of the FIFO) is sent to the bank102to perform a write operation thereto.

When a pending write operation is written to the bank102, it is removed from the pending commands in FIFO106and if bsy*124is asserted and the FIFO102is not in near full condition, the bsy*124is deasserted in the last cycle of the write operation.

In one embodiment, the bsy*124is asserted after edge of the clk110, registering a command. In some embodiments, the rising edge of the clk110is used and in other embodiments, the falling edge of the clk110is used. If the bsy*124is asserted at the rising of the clk100, then the cycle is a “wait” cycle and no command is registered (state of CE*120is ignored).

In another embodiment bsy*124is asserted before edge of clock registering command (in this case rising edge) and is valid at the said edge. In this embodiment if bsy*124is asserted at rising edge of the clk110, the command is registered and the following cycle becomes the “wait” cycle.

FIG. 3shows a block diagram of additional MRAM banks in the system10ofFIG. 1. Namely, magnetic memory banks152-158are shown and coupled to respective bank selects192,194,196, and198. Each of the banks152-158is analogous to the bank102ofFIG. 2and includes a FIFO interface device14labeled FIFO interface device168,170,172and174. It is appreciated that while four banks are shown inFIG. 3, other number of banks are contemplated.

Each of the bank selects192-198receives as input a bank select signal,206-200, respectively, and CE*120. The bank select signals200-206are generated by the address decoder190, which is responsive to the address114and uses the same to generate the signals200-206. Accordingly, the address decoder190serves to select a bank to be accessed by activating one of the signals200-206. It is appreciated that using more than four banks likely requires additional bank select signals to be generated by the decoder190. Each of the selects192-198, upon the activation of the signals, CE*120and a corresponding bank select signal, activates CE*120, which is internal to the corresponding interface, among the interfaces152-158. Alternatively, banks152-158receive an input that is used for assigning a number to each bank. For example, each bank has an additional two-digit binary input that can be used to assign an integer number (0, 1, 2 or 3) to each of the banks by permanently coupling the input to a logical value of “0” or “1”. The address bits defining the banks are compared with the bank value and if matched and CE*120is asserted, the addressed bank is enabled.

The busy signal generator208receives the bsy* signals from each of the interfaces152-158and uses them to generate the bsy*124. That is, in the case where any of the interfaces152-158are busy, the bsy*124is activated, otherwise, if none of the interfaces152-158are busy, the bsy*124is not activated. The notation “*”, as used herein, generally refers to the negative polarity of a corresponding signal being the active state of the signal, however, it is noted that this is merely a design choice and the opposite polarity may be employed without departing from the spirit and scope of the invention.

The data output generator210selects between the data from each of the interfaces152-158to send to the user via the DO118. This selection is based on which bank is being accessed.

Multiple MRAM banks of the system10allows for concurrency of data storage thereby increasing performance thereof, which is particularly noteworthy during write operations because in this respect, the performance of the MRAM of system10is comparable to the performance of a system utilizing SRAM.

FIG. 4shows a block diagram of further details of the FIFO106ofFIG. 2and its interface with other blocks in FIFO interface14. The FIFO106is coupled to FIFO memory interface control268and a memory address selector211. The FIFO106is operative to FIFO write294and FIFO read296generated by memory interface control268, and provides FIFO empty status296and FIFO near full status298to the FIFO memory interface control268. The FIFO106provides address253to memory address selector211.

The FIFO106is shown to include a FIFO write control250, a FIFO memory interface control268, FIFO entries251_0through251—n(where n is an integer), and the data output selector210. For the sake of simplicity only two FIFO entries, FIFO entries251_0and FIFO entry251—nare shown inFIG. 4, it is understood that additional ones are identical in structure and function. The FIFO control250is coupled to FIFO entries251_0through251—n, FIFO memory interface control268, and the data output selector210. The data output selector210, couples either the mDO126or internal bus170onto DO118depending on select signal292from FIFO control250.

The FIFO entry251_0comprises an address register252_0, comparators256_0, data registers260_0, data selects264_0, data selects266_0. FIFO control250is shown coupled to the address registers252_0, data blocks260_0, comparator256_0, data select264_0, and data select266_0. The address register252_0receives input272_0from the FIFO write control250to load the address114in the register. The data registers260_0receives input274_0from the FIFO write control250to load the input Di116in the register. The comparators256_0receive address114as input and also receive as input the contents of address register252_0, along with compare enable257_0; indicating that the entry is a valid entry, from FIFO control250. The comparator256_0output; compare276_0, is input to the FIFO control250. The output of the data registers260_0is provided as input to a data selects,264_0and266_0. Data select264_0couples the output of data register260_0to mDi130, when enable290_0from FIFO control250is asserted. Similarly data select266_0couples the output of data register260_0to internal bus170, when enable266_0from FIFO control250is asserted. The output of the address registers252_0is provided as input to a select263_0that couples the output of address register252_0to address253, when enable290_0from FIFO control250is asserted. As mentioned earlier FIFO entries251_0and FIFO entry251—nshown inFIG. 4are identical in structure and function.

In operation, when the FIFO memory interface control detects a write command, it will save the command (address and data) in a FIFO entry (address register and data register of the entry) by asserting a FIFO write297, the FIFO write pointer will advance to next entry at next cycle and make the current entry valid.

In operation, when the FIFO memory interface control detects an idle cycle or a write command, and FIFO not empty, and MRAM idle it will issue a pending write (from top of FIFO) and upon completion of write it will assert a FIFO read296to advance top of FIFO to next entry in FIFO and make the current entry invalid.

The FIFO106ofFIG. 4checks data coherency, and returns data from FIFO if the FIFO interface device14holds the most recent data that is being accessed by the user of the system10. In operation the FIFO control250provides a compare enable257-0through257—nto the comparator within each entry251_0through251—nto enable comparison of address stored in address registers252_0through252—nwith incoming address114. When compare enable257-0through257—nis asserted it indicates the entry is valid and comparison is enabled, The output of comparators276_0through276—nis provided to FIFO control250, if any of the comparator outputs is asserted it indicates the latest data is in FIFO and FIFO control250asserts the select292of the data output selector210to couple data bus267from FIFO to data out118, else memory data output126is coupled on the data out118. In this respect, data coherency is performed to return data if the device14holds the most recent data that is being accessed, otherwise the data in the MRAM12is output.

FIG. 5shows a timing diagram of the behavior of some of the signals shown in previous figures during a number of the scenarios discussed hereinabove. More specifically, the clk110, CE*120, WE*122, mCE*132, mWE*134, mbsy*135, bsy*124signal, DO118, and DI116, are shown. In all the timing diagram figures herein MRAM read operation takes one cycle of clk110, and MRAM write requires two cycles of clk110. A clk110cycle is shown by the reference number326. In the scenarios discussed, which, as appreciated, are some of many other scenarios, including but not limited to memory cycles being more than or less than two clock cycles.

At300, the first scenario presented above, where a read operation takes place. At300, CE*120is active, WE*122is inactive, mCE*132is active, mWE*134is inactive, mbsy* is inactive, and bsy*124is inactive. In this scenario, the incoming command is a read command and a pending write operation (as indicated by the mCE* and the mWE* signals) is not in progress and the MRAM12is not being accessed, a read operation of the MRAM12is performed and the FIFO106is checked for an address match. In this case, there is a match, (what in the timing diagram indicates that? Additionally below on line16you say fifo is empty, to be consistent you can say we assume the fifo empty and the memory data is returned) i.e. the pending write command in the FIFO106is to the same address as the one being read, the data in the FIFO106is returned (or coupled onto the DO118).

At302, the WE*122is at a state signifying a write operation and was inactivated at308. Accordingly, in this scenario, the incoming command is a write command and the MRAM12is idle (or no pending commands are in progress) and the FIFO106is empty (no valid data is in the FIFO), the incoming command is saved in the FIFO106followed by sending the incoming command to the MRAM12to perform a write operation thereto, at304. Thus, at310, the mWE*134is activated and at312, the mbsy* is activated resulting in an additional clk110cycle being needed to account for the added time needed to complete writing to the MRAM12. However note that bsy* is not asserted and the user can continue using the memory system10.

During306, the mbsy*135is asserted, indicating a MRAM wait cycle (MRAM is busy) the state of mCE*132is ignored. During306, the incoming command is a write command (CE*120and WE*122asserted and bsy*124deasserted) and a pending write operation is in progress (mbsy*135asserted), the incoming command is saved in FIFO. Note that since FIFO is not near full condition bsy* remains deassered and the user can continue using the memory system10. During cycle306at314the mbsy*135changes state to indicate that the MRAM12will not be busy in the next cycle and a command can be issued to MRAM in cycle307. During307, the incoming command is a write command (CE*120and WE*122asserted and bsy*124deasserted) and a pending write operation is started (mbsy*135asserted at318), the incoming command is saved in FIFO. Note that since FIFO is not near full condition bsy* remains deassered and the user can continue using the memory system10. During cycle307at318the mbsy*135is asserted to indicate that the MRAM12will be busy in the next cycle308and a command can not be issued to MRAM in cycle308.

During308, the incoming command is a read command (CE*120is asserted and WE*122is deasserted and bsy*124deasserted) and a pending write operation is in progress (mbsy*135asserted), the incoming command is a read command and the FIFO106is checked for an address match, the timing diagram assumes that at cycle308a match did not occur as indicated at330by the bsy*124being asserted and the read command is saved and becomes a pending read command (stored in the register108) because the MRAM12is not idle (or it is busy). The pending read command is executed immediately after the completion of the pending write operation that is in progress in cycle324. Subsequently, at324, a “wait” cycle takes place allowing time for the completion of the read operation with DO118being output accordingly.

FIG. 6shows a timing diagram of the behavior of some of the signals shown inFIG. 5and particularly when the FIFO106is near full during a write operation. More specifically,FIG. 6, during340, shows the incoming command being a write command (shown at344with the WE*122being asserted) and a memory operation started (at346, with the mWE*134being asserted) and the FIFO106being near full (shown at342with the bsy*124being activated), the incoming command is saved in the FIFO106and, as stated above, the bsy*124is asserted and a pending command in the FIFO106(top of the FIFO) is sent to the bank102to perform a write operation thereto.

It is understood that the foregoing timing diagrams are merely exemplary and other timing behavior and/or signals are contemplated. Additionally, the polarity of the signals shown and discussed herein are exemplary and opposite polarities may be employed.

FIG. 7shows a block diagram of an apparatus70incorporating the magnetic memory system71, which is analogous to the system10. The apparatus70, which is understood as being an exemplary application with many others being contemplated, is shown to include a digital circuitry78(comprising a micro processor) coupled to the magnetic memory system71and a ROM72and an analog circuitry76(comprising power on reset generator, low power voltage detect, voltage regulator and a NOR/NAND memory80. The NOR/NAND memory80is another form of memory used to store data. Additionally the analog circuitry76transmits and receives analog data72and converts the analog data to digital form for use by the digital circuitry78through the digital data78. The ROM72is yet another form of memory used to store data during manufacturing of the apparatus70and whose contents are read through the signals80. The system71communicates data through the signals82to and from the digital circuitry78. The apparatus70transmits and receives information through the interface74, and the analog data72. In some embodiments, the digital circuitry78is a microprocessor although other digital circuitry in addition thereto or in replacement thereof is contemplated.