Compiler based cache allocation

Techniques a generally described for creating a compiler determined map for the allocation of memory space within a cache. An example computing system is disclosed having a multicore processor with a plurality of processor cores. At least one cache may be accessible to at least two of the plurality of processor cores. A compiler determined map may separately allocate a memory space to threads of execution processed by the processor cores.

BACKGROUND

Multicore processors have emerged as a mainstream computing platform in major market segments, including personal computer (PC), server, and embedded domains. As the number of processor cores on a given chip increase, so too does the potential demand on that chip's local memory. When the processor executes an instruction, for example, the processor first looks at its on-chip cache to find the data associated with that instruction to avoid performing a more time-consuming search for the data elsewhere (e.g., off-chip or on a main memory chip). Commercial multicore processors often use cache designs from uni-processors. Thus, multicore processors may share a single cache. With multiple cores, multiple incoming application streams may interfere with each other while seeking shared cache space, and as a result, may cause a shared cache and, thus, the processor to operate inefficiently. Other factors relating to multiple cores may also reduce processor efficiency.

Not all applications, however, benefit from the availability of cache resources. One example may be a streaming application, where data may be fetched into the cache, processed, and then may be unlikely to be reused. Thus, different types of applications sharing cache space with similar or equal priority may result in sub-optimal allocation of cache resources. Conflict among processor cores for the use of a shared cache may be expensive in terms of both latency and power as a result of additional requests to off-chip memory.

DETAILED DESCRIPTION

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof. In the drawings, similar symbols typically identify similar components, unless context dictates otherwise. The illustrative examples described in the detailed description, drawings, and claims are not meant to be limiting. Other examples may be utilized, and other changes may be made, without departing from the spirit or scope of the subject matter presented herein. It will be readily understood that the aspects of the present disclosure, as generally described herein, and illustrated in the Figures, may be arranged, substituted, combined, separated, and designed in a wide variety of different configurations, all of which are explicitly contemplated herein.

This disclosure is drawn, inter alia, to methods, apparatus, systems and computer program products related to creating a compiler determined map for the allocation of memory space within a cache. In a multicore processor system, several applications may be running in parallel on separate cores, each with its own memory requirements. Memory space, however, may be finite. Depending on the design of the chip, individual processor cores may have to share local memory space with one or more other cores. This local memory may include, for example, the L2 or L3 caches.

The execution characteristics of some running applications may differ from the execution characteristics of other running applications. These execution characteristics may also change over time. One such execution characteristic may be the amount of local memory utilized to achieve adequate processing performance. For example, one application may operate more efficiently when a large amount of cache space is available, while another application may operate efficiently with any amount of cache space available. Thus, on a chip with limited cache space, the benefit to each application of obtaining additional cache resources may vary.

As is described herein, various examples for efficient use of shared cache resources in a multicore computing environment are disclosed. As a compiler compiles a program, it may simultaneously create a map for the partitioning of a shared cache such that conflict among the processor cores, which may process various threads of execution in parallel, may be reduced or minimized. Furthermore, as application execution characteristics change over time, cache allocation may change dynamically. Thus, by reducing the interference resulting from competition for cache space amongst the cores, overall system performance may be improved.

FIG. 1shows an illustrative multicore processor100, including a single integrated circuit having a processing core array102. In other examples a multicore processor may include processors on separate integrated chips. The processing core array102may include some number (N) of processing cores104(1)-104(N). Any suitable number of processing cores104may be provided. Individual processor cores104may generally be of any desired configuration including but not limited to a microprocessor (μP), a microcontroller (μC), a digital signal processor (DSP), or any combination thereof. Thus, individual processor cores104may include logic for executing program instructions as well as other functional blocks such as an arithmetic logic unit (ALU), a floating point unit (FPU), a digital signal processing (DSP) core, registers, accumulators, etc.

The multicore processor100may include any combination of dedicated or shared resources. A dedicated resource may be a resource106dedicated to a single processing core104, such as a dedicated level one cache, or may be a resource108dedicated to any subset of the processing cores104. A shared resource may be a resource110shared by some or all of the cores104, such as a shared level two cache or a shared external bus112. Such a shared external bus112may support an interface between the multicore processor100and another component114. Such components114may include, but are not limited to, input-output (I/O) devices, external sensors, or the like, or may be a resource shared by any subset of the processing cores104. A shared resource may also include main memory120, which may be any suitable form of memory including, but not limited to, volatile memory such as random access memory (RAM), non-volatile memory such as read only memory (ROM) and flash memory storage, data storage devices such as magnetic disk storage (e.g., hard disk drive or HDD), tape storage, optical storage (e.g., compact disk or CD, digital versatile disk or DVD), or other machine-readable storage mediums that may be removable, non-removable, volatile or non-volatile.

As stated above, multicore processor100may have any suitable number of processing cores104. For example, multicore processor100may have two (2) cores, four (4) cores, tens of cores, and even hundreds or more of processing cores. Some multicore processors may be homogenous, such that individual processing cores use a single core design. Other multicore processors may be heterogeneous, such that one or more of the processing cores may be different from one or more of other processing cores, and individual processor cores or subset of processor cores may be designed for a different role in the multicore processor100.

The multicore processor100may include a core controller, or core interface116. Core controller116may determine which processing tasks are to be processed by individual processing cores104. One or more switches118may be provided. In one example, processing tasks may be routed to selected processing cores using switches118.

FIG. 1is an illustrative schematic of a multicore processor and does not illustrate physical location of the components illustrated therein. It is appreciated that the multicore processor100described herein is illustrative and that examples and modifications are possible. Design choices may be driven by, for example, considerations of hardware size and complexity versus performance, thermal energy and heat dissipation, processor speed, overall throughput, etc.

As may be appreciated by one skilled in the art, the multicore processor100may be provided in a suitable computing environment, such as a personal computer (PC). A computing environment may include the multicore processor100, system memory, one or more buses, and one or more I/O devices, such as a keyboard, mouse, touch screen, display device, such as a CRT or LCD based monitor, universal serial bus (USB) or other port connections, CD drives, DVD drives, and the like. Bus connections among the various components may be implemented using bus protocols such as Peripheral Component Interconnect (PCI), PCI Express, Accelerated Graphics Port (AGP), HyperTransport, or any other suitable bus protocol, and connections between different devices may use different protocols. A PC may operate in a networked environment using logical connections to one or more remote computers. Such remote computers may be, for example, other PCs, servers, routers, network PCs, peer devices, or other common network nodes, and may include many or all of the elements described above relative to multicore processor100. Logical connections may comprise, for example, a local-area network (LAN) or a wide-area network (WAN), intranets and the Internet.

In one example,FIG. 2illustrates a plurality of processor cores201-204, suitable for use in a multicore processor system. Individual processor cores201-204may have differing performance characteristics, as represented by the varying sizes of cores201-204. For example, the larger cores201and203may be of higher performance, suitable for more complex software applications, as compared to the smaller cores202and204, which may be suitable for processing software applications of less complexity. It is to be appreciated that more or fewer cores may be provided, that the cores may be of uniform or varying size, and that specific descriptions of the cores herein are not intended to be limiting.

A suitable shared cache300is depicted inFIG. 2for use with the plurality of processor cores201-204. Individual cores201-204may transfer data to and from shared cache300. Shared cache300may be partitioned such that individual cores201-204may only have access to certain areas within the cache.

FIG. 3ais an illustrative schematic of the partitioning of a shared cache300suitable for use with any of the examples disclosed herein. The rows inFIG. 3arepresent the 1 through m lines in shared cache300. The columns inFIG. 3arepresent the 1 through n ways into shared cache300. Thus, block401inFIG. 3arepresents way “1” into cache line “1” in shared cache300. Similarly, block408represents way “n” into cache line “2” in shared cache300.FIG. 3adepicts one possible partitioning of shared cache300. A first processor core “A” is depicted as having been allocated ways “1” and “2” into cache line “1”. A second processor core “B” is depicted as having been allocated ways “3” through “n” into cache line “1”. Thus, in the example shown, provided that n is larger than 2, processor core “B” has been allocated a larger portion of shared cache300than processor core “A”. Furthermore, a processor core “C” is depicted as having been allocated all the ways “1” through “n” into cache line “2”. Thus, processor core “C” has been allocated a larger portion of shared cache300that either processor cores “A” or “B”. It is to be appreciated that processor cores200may be partitioned shared cache300space in any combination of cache lines and ways, and that some processor cores200may share any combination of lines and ways. The specific partitioning of shared cache300inFIG. 3ais not in any way intended to be limiting.

In yet other examples, cache partitioning may be accomplished by reference to a compiler determined cache allocation map. A compiler is a computer software application that translates text from a high-level programming language into a lower level language such as machine language or assembly language.FIG. 4illustrates a flowchart diagram of a suitable process by which cache partitioning based at least in part on compiler mapping may be accomplished. As depicted inFIG. 4, a computer software application510containing a plurality of threads of execution501-502in a computing environment500may be compiled by a compiler800. Because the compiler800has direct access to the software code, the compiler800may be able to determine the execution characteristics of the computer software application510, such as, whether a particular thread501-502, when executed, may utilize a large or small cache300space for adequate performance. Then, based at least in part on these characteristics of the computer software application510, or the individual threads501-502thereof, as determined by the compiler800, a cache allocation map may be created [block900]. For example, the compiler800may allocate a larger cache300area when the compiler800determines that a thread501-502, which the compiler800has compiled, may utilize a larger cache300area. Alternatively, the compiler800may allocate a smaller cache300area when the compiler800determines that a thread501-502, which the compiler800has compiled, may utilize only a smaller cache300area.

In some examples, the compiler800may analyze profile information of the software application. Using a profiler, for example, the compiler800may analyze the behavior of a program as it executes, which may include the frequency and duration of function calls or other subroutines within the program. Profile information may also be analyzed using sampling techniques, wherein a sampling profiler may probe the target application's program counter at regular intervals using operating system interrupts. Then, using any of this profile information, the compiler800may create a cache allocation map.

In other examples, the compiler800may make a dynamic assessment of data locality of reference (locality) for shifting allocation. Locality refers to the frequency with which data is accessed. As that locality increases, the allocation may shift to give more space for that data. Data that is assessed as having more locality (where there is more frequent return to the data) may be given more access. Data that is assessed as having less locality may be given limited access. Alternatively, this assessment may be static and made at the beginning of execution based at least in part on an initial review of the data or may be dynamic as the compiler determines that the data has more locality than expected. From this locality information, the compiler800may then create a cache allocation map.

The cache allocation map may then be translated to the cache300by the compiler800. This action may be accomplished by, for example, re-indexing the address bits in the cache300, or any other suitable means, as will be apparent to those skilled in the art. Thus, the location where data is stored in a shared cache may be determined at the software level, prior to processing by a processor core, rather than at the hardware level.FIG. 3bis a schematic illustration of a cache that has been re-indexed. In block701, the cache memory index “0” corresponds with main memory index “2”, as marked by the tag “2”. After re-indexing, in block702, cache memory index “1” is now associated with main memory index “2”, as marked by the tag “2”. Cache index “0” has been changed to correspond with main memory index “0”.

In alternative examples, mapping may be done on hardware, prior to being translated to the chip. For example, within the processing system architecture may be embedded hardware configured for mapping a cache. The compiler may dictate the map to the hardware, based at least in part on the information it has gathered, and then the hardware may create the map for the cache. This alternative example is depicted inFIG. 4, wherein shared cache allocation map900may be directed to hardware950, and then translated to shared cache300.

It is to be appreciated that software application execution characteristics may change dynamically. Thus, in any of the examples disclosed herein, cache partitioning may be configured to change over time in a dynamic manner. Furthermore, in examples that use compiler mapping, Bloom filters, reference counts based at least in part on thread identification (thread ID) using a performance counter, or any other suitable means may be used to determine when to re-map the cache.

In one particular example, as shown inFIG. 5a, a computer system600may include a processor601configured for performing an example of a method for partitioning a shared cache. In other examples, various actions or portions of various actions of the method may be performed outside of the processor601. In action602, the method may include creating a map of memory space within the cache using a compiler for allocating memory space within the cache to one or more processor cores. In action604, the method may include partitioning the shared cache in accordance with the compiler determined map. As disclosed above, the mapping may be done by the compiler re-indexing the address bits in the cache, by hardware placed in front of the cache, or by any suitable means as will be appreciated by those in the art.

In another example, as shown inFIG. 5b, a computer accessible medium600having stored thereon computer accessible instructions601for performing a procedure for allocating a cache space within a multicore processor computing system. In action602, the procedure may include creating a map of memory space within the cache using a compiler for allocating memory space within the cache to one or more processor cores. In action604, the procedure may include partitioning the shared cache in accordance with the compiler determined map. As disclosed above, the mapping may be done by the compiler re-indexing the address bits in the cache, by hardware placed in front of the cache, or by any suitable means as will be appreciated by those in the art.

The foregoing describes various examples of compiler based cache allocation. Following are specific examples of methods and systems of compiler based cache allocation. These are for illustration only and are not intended to be limiting.

Disclosed in some examples is a computing system comprising a multicore processor, at least one cache that is shared among the processor cores, and a compiler capable of creating a map for the partitioning of memory space within the shared cache. In further examples, the compiler may create the map for the partitioning of memory space within the shared cache based at least in part on the execution characteristics of the threads of execution. In some of these examples, the map for the partitioning of memory space within the shared cache may be translated from the compiler to the shared cache by re-indexing address bits in the shared cache. In other examples, memory space within the cache may be partitioned by restricting the number of ways the processor cores have access into the cache. In these examples, the ways into the cache may be partitioned separately at each cache line. In still other examples, Bloom filters may be used to determine when to initiate a re-mapping of the shared cache. Alternatively, reference counts based at least in part on thread identification, collected by means of a performance counter, may be used to determine when to initiate a re-mapping of the shared cache.

In other examples, a method is disclosed for partitioning the cache in accordance with a compiler determined map. In this example, a compiler may create a map for the allocation of memory space within the shared cache based at least in part on characteristics of one or more software applications, the threads of execution of which are to be processed on one or more processor cores within the multicore processor computing system. In some further examples, the map for the allocation of memory space within the cache may be created within a hardware located in front of the cache, based at least in part on information which has been determined by the compiler and sent to the hardware. In other examples, the map for the allocation of memory space within the cache may be translated from the compiler to the cache by re-indexing address bits in the cache. Additionally, the map for the allocation of memory space within the cache may restrict a number of ways the plurality processor cores have access into the cache. In yet other examples, the map for the allocation of memory space within the cache is reconfigured dynamically over the course of the execution of the one or more software applications.

In other example, a computer accessible medium is disclosed, having stored thereon computer executable instructions for performing a procedure for allocating a cache space within a multicore processor computing system, the procedure comprising creating a compiler determined map for the allocation of memory space within the cache partitioning the cache in accordance with the compiler determined map. In some further examples, a compiler creates the map for the allocation of memory space within the shared cache based at least in part on characteristics of one or more software applications, threads of execution of which are to be processed on one or more processor cores within the multicore processor computing system.

Claimed subject matter is not limited in scope to the particular implementations described herein. For example, some implementations may be in hardware, such as employed to operate on a device or combination of devices, for example, whereas other implementations may be in software and/or firmware. Likewise, although claimed subject matter is not limited in scope in this respect, some implementations may include one or more articles, such as a storage medium or storage media. This storage media, such as CD-ROMs, computer disks, flash memory, or the like, for example, may have instructions stored thereon, that, when executed by a system, such as a computer system, computing platform, or other system, for example, may result in execution of a processor in accordance with claimed subject matter, such as one of the implementations previously described, for example. As one possibility, a computing platform may include one or more processing units or processors, one or more input/output devices, such as a display, a keyboard and/or a mouse, and one or more memories, such as static random access memory, dynamic random access memory, flash memory, and/or a hard drive.

Reference in the specification to “an implementation,” “one implementation,” “some implementations,” or “other implementations” may mean that a particular feature, structure, or characteristic described in connection with one or more implementations may be included in at least some implementations, but not necessarily in all implementations. The various appearances of “an implementation,” “one implementation,” or “some implementations” in the preceding description are not necessarily all referring to the same implementations. Moreover, when terms or phrases such as “coupled” or “responsive” or “in response to” or “in communication with”, etc. are used herein or in the claims that follow, these terms should be interpreted broadly. For example, the phrase “coupled to” may refer to being communicatively, electrically and/or operatively coupled as appropriate for the context in which the phrase is used.

In the preceding description, various aspects of claimed subject matter have been described. For purposes of explanation, specific numbers, systems and/or configurations were set forth to provide a thorough understanding of claimed subject matter. However, it should be apparent to one skilled in the art and having the benefit of this disclosure that claimed subject matter may be practiced without the specific details. In other instances, well-known features were omitted and/or simplified so as not to obscure claimed subject matter. While certain features have been illustrated and/or described herein, many modifications, substitutions, changes and/or equivalents will now, or in the future, occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and/or changes as fall within the true spirit of claimed subject matter.

While various aspects and examples have been disclosed herein, other aspects and examples will be apparent to those skilled in the art. The various aspects and examples disclosed herein are for purposes of illustration and are not intended to be limiting, with the true scope and spirit being indicated by the following claims.