Integrated circuit package and method

In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially encapsulating the integrated circuit die; a redistribution structure on the encapsulant, the redistribution structure being electrically connect to the integrated circuit die, the redistribution structure including a pad; a passive device including a conductive connector physically and electrically connected to the pad; and a protective structure disposed between the passive device and the redistribution structure, the protective structure surrounding the conductive connector, the protective structure including an epoxy flux, the protective structure having a void disposed therein.

BACKGROUND

The semiconductor industry has experienced rapid growth due to ongoing improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, improvement in integration density has resulted from iterative reduction of minimum feature size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices has grown, a need for smaller and more creative packaging techniques of semiconductor dies has emerged. An example of such packaging systems is Package-on-Package (PoP) technology. In a PoP device, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration and component density. PoP technology generally enables production of semiconductor devices with enhanced functionalities and small footprints on a printed circuit board (PCB).

DETAILED DESCRIPTION

In accordance with some embodiments, a redistribution structure is formed, and a protective structure is prefilled on a surface of the redistribution structure. The protective structure is formed of an epoxy flux, is directly printed on contact pads of the redistribution structure, and is not cured immediately after printing. A surface-mounted device (SMD), such as a passive device, is pressed into the uncured protective structure to physically and electrically couple the contact pads of the redistribution structure. External connectors, such as solder connectors, are also formed on pads of the redistribution structure. A single thermal processing step is performed to simultaneously cure the protective structure and reflow the external connectors and passive device contacts. By delaying the curing and performing the curing concurrently with the reflowing, one or more thermal processing steps may be omitted, thereby decreasing wafer processing time and manufacturing costs.

FIG. 1illustrates a cross-sectional view of an integrated circuit die50, in accordance with some embodiments. The integrated circuit die50will be packaged in subsequent processing to form an integrated circuit package. The integrated circuit die50may be a logic die (e.g., central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC), application processor (AP), microcontroller, etc.), a memory die (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), a power management die (e.g., power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., digital signal processing (DSP) die), a front-end die (e.g., analog front-end (AFE) dies), the like, or combinations thereof.

The integrated circuit die50may be formed in a wafer, which may include different device regions that are singulated in subsequent steps to form a plurality of integrated circuit dies. The integrated circuit die50may be processed according to applicable manufacturing processes to form integrated circuits. For example, the integrated circuit die50includes a semiconductor substrate52, such as silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate52may include other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, and/or GaInAsP; or combinations thereof. Other substrates, such as multi-layered or gradient substrates, may also be used. The semiconductor substrate52has an active surface (e.g., the surface facing upwards inFIG. 1), sometimes called a front side, and an inactive surface (e.g., the surface facing downwards inFIG. 1), sometimes called a back side.

Devices54may be formed at the front surface of the semiconductor substrate52. The devices54may be active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc. An inter-layer dielectric (ILD)56is over the front surface of the semiconductor substrate52. The ILD56surrounds and may cover the devices54. The ILD56may include one or more dielectric layers formed of materials such as Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), Boron-Doped Phospho-Silicate Glass (BPSG), undoped Silicate Glass (USG), or the like.

Conductive plugs58extend through the ILD56to electrically and physically couple the devices54. For example, when the devices54are transistors, the conductive plugs58may couple the gates and source/drain regions of the transistors. The conductive plugs58may be formed of tungsten, cobalt, nickel, copper, silver, gold, aluminum, the like, or combinations thereof. An interconnect structure60is over the ILD56and conductive plugs58. The interconnect structure60interconnects the devices54to form an integrated circuit. The interconnect structure60may be formed by, for example, metallization patterns in dielectric layers on the ILD56. The metallization patterns include metal lines and vias formed in one or more low-k dielectric layers. The metallization patterns of the interconnect structure60are electrically coupled to the devices54by the conductive plugs58.

The integrated circuit die50further includes pads62, such as aluminum pads, to which external connections are made. The pads62are on the active side of the integrated circuit die50, such as in and/or on the interconnect structure60. One or more passivation films64are on the integrated circuit die50, such as on portions of the interconnect structure60and pads62. Openings extend through the passivation films64to the pads62. Die connectors66, such as conductive pillars (for example, formed of a metal such as copper), extend through the openings in the passivation films64and are physically and electrically coupled to respective ones of the pads62. The die connectors66may be formed by, for example, plating, or the like. The die connectors66electrically couple the respective integrated circuits of the integrated circuit die50.

Optionally, solder regions (e.g., solder balls or solder bumps) may be disposed on the pads62. The solder balls may be used to perform chip probe (CP) testing on the integrated circuit die50. CP testing may be performed on the integrated circuit die50to ascertain whether the integrated circuit die50is a known good die (KGD). Thus, only integrated circuit dies50, which are KGDs, undergo subsequent processing are packaged, and dies, which fail the CP testing, are not packaged. After testing, the solder regions may be removed in subsequent processing steps.

A dielectric layer68may (or may not) be on the active side of the integrated circuit die50, such as on the passivation films64and the die connectors66. The dielectric layer68laterally encapsulates the die connectors66, and the dielectric layer68is laterally coterminous with the integrated circuit die50. Initially, the dielectric layer68may bury the die connectors66, such that the topmost surface of the dielectric layer68is above the topmost surfaces of the die connectors66. In some embodiments where solder regions are disposed on the die connectors66, the dielectric layer68may bury the solder regions as well. Alternatively, the solder regions may be removed prior to forming the dielectric layer68.

The dielectric layer68may be a polymer such as PBO, polyimide, BCB, or the like; a nitride such as silicon nitride or the like; an oxide such as silicon oxide, PSG, BSG, BPSG, or the like; the like, or a combination thereof. The dielectric layer68may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), or the like. In some embodiments, the die connectors66are exposed through the dielectric layer68during formation of the integrated circuit die50. In some embodiments, the die connectors66remain buried and are exposed during a subsequent process for packaging the integrated circuit die50. Exposing the die connectors66may remove any solder regions that may be present on the die connectors66.

In some embodiments, the integrated circuit die50is a stacked device that include multiple semiconductor substrates52. For example, the integrated circuit die50may be a memory device such as a hybrid memory cube (HMC) module, a high bandwidth memory (HBM) module, or the like that includes multiple memory dies. In such embodiments, the integrated circuit die50includes multiple semiconductor substrates52interconnected by through-substrate vias (TSVs). Each of the semiconductor substrates52may (or may not) have an interconnect structure60.

FIGS. 2 through 21illustrate cross-sectional views of intermediate steps during a process for forming a first package component100, in accordance with some embodiments. A first package region100A and a second package region100B are illustrated, and one or more of the integrated circuit dies50are packaged to form an integrated circuit package in each of the package regions100A and100B. The integrated circuit packages may also be referred to as integrated fan-out (InFO) packages.

InFIG. 2, a carrier substrate102is provided, and a release layer104is formed on the carrier substrate102. The carrier substrate102may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate102may be a wafer, such that multiple packages can be formed on the carrier substrate102simultaneously. The release layer104may be formed of a polymer-based material, which may be removed along with the carrier substrate102from the overlying structures that will be formed in subsequent steps. In some embodiments, the release layer104is an epoxy-based thermal-release material, which loses its adhesive property when heated, such as a light-to-heat-conversion (LTHC) release coating. In other embodiments, the release layer104may be an ultra-violet (UV) glue, which loses its adhesive property when exposed to UV lights. The release layer104may be dispensed as a liquid and cured, may be a laminate film laminated onto the carrier substrate102, or may be the like. The top surface of the release layer104may be leveled and may have a high degree of planarity.

InFIG. 3, a back-side redistribution structure106may be formed on the release layer104. In the embodiment shown, the back-side redistribution structure106includes a dielectric layer108, a metallization pattern110(sometimes referred to as redistribution layers or redistribution lines), and a dielectric layer112. The back-side redistribution structure106is optional. In some embodiments, a dielectric layer without metallization patterns is formed on the release layer104in lieu of the back-side redistribution structure106.

The dielectric layer108may be formed on the release layer104. The bottom surface of the dielectric layer108may be in contact with the top surface of the release layer104. In some embodiments, the dielectric layer108is formed of a polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. In other embodiments, the dielectric layer108is formed of a nitride such as silicon nitride; an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like; or the like. The dielectric layer108may be formed by any acceptable deposition process, such as spin coating, CVD, laminating, the like, or a combination thereof.

The dielectric layer112may be formed on the metallization pattern110and the dielectric layer108. In some embodiments, the dielectric layer112is formed of a polymer, which may be a photo-sensitive material such as PBO, polyimide, BCB, or the like, that may be patterned using a lithography mask. In other embodiments, the dielectric layer112is formed of a nitride such as silicon nitride; an oxide such as silicon oxide, PSG, BSG, BPSG; or the like. The dielectric layer112may be formed by spin coating, lamination, CVD, the like, or a combination thereof. The dielectric layer112is then patterned to form openings114exposing portions of the metallization pattern110. The patterning may be formed by an acceptable process, such as by exposing the dielectric layer112to light when the dielectric layer112is a photo-sensitive material or by etching using, for example, an anisotropic etch. If the dielectric layer112is a photo-sensitive material, the dielectric layer112can be developed after the exposure.

It should be appreciated that the back-side redistribution structure106may include any number of dielectric layers and metallization patterns. If more dielectric layers and metallization patterns are to be formed, steps and processes discussed above may be repeated. The metallization patterns may include conductive lines and conductive vias. The conductive vias may be formed during the formation of the metallization pattern by forming the seed layer and conductive material of the metallization pattern in the opening of the underlying dielectric layer. The conductive vias may therefore interconnect and electrically couple the various conductive lines.

InFIG. 5, integrated circuit dies50are adhered to the dielectric layer112by an adhesive118. A desired type and quantity of integrated circuit dies50are adhered in each of the package regions100A and100B. In the embodiment shown, multiple integrated circuit dies50are adhered adjacent one another, including a first integrated circuit die50A and a second integrated circuit die50B. The first integrated circuit die50A may be a logic device, such as a central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC), microcontroller, or the like. The second integrated circuit die50B may be a memory device, such as a dynamic random access memory (DRAM) die, static random access memory (SRAM) die, hybrid memory cube (HMC) module, a high bandwidth memory (HBM) module, or the like. In some embodiments, the integrated circuit dies50A and50B may be the same type of dies, such as SoC dies. The first integrated circuit die50A and second integrated circuit die50B may be formed in processes of a same technology node, or may be formed in processes of different technology nodes. For example, the first integrated circuit die50A may be of a more advanced process node than the second integrated circuit die50B. The integrated circuit dies50A and50B may have different sizes (e.g., different heights and/or surface areas), or may have the same size (e.g., same heights and/or surface areas). The space available for the through vias116in the package regions100A and100B may be limited, particularly when the integrated circuit dies50A and50B include devices with a large footprint, such as SoCs. Use of the back-side redistribution structure106allows for an improved interconnect arrangement when the package regions100A and100B have limited space available for the through vias116.

The adhesive118is on back-sides of the integrated circuit dies50A and50B and adheres the integrated circuit dies50A and50B to the back-side redistribution structure106, such as to the dielectric layer112. The adhesive118may be any suitable adhesive, epoxy, die attach film (DAF), or the like. The adhesive118may be applied to back-sides of the integrated circuit dies50A and50B or may be applied over the surface of the carrier substrate102. For example, the adhesive118may be applied to the back-sides of the integrated circuit dies50A and50B before singulating to separate the integrated circuit dies50A and50B.

InFIG. 6, an encapsulant120is formed on and around the various components. After formation, the encapsulant120encapsulates the through vias116and integrated circuit dies50. The encapsulant120may be a molding compound, epoxy, or the like. The encapsulant120may be applied by compression molding, transfer molding, or the like, and may be formed over the carrier substrate102such that the through vias116and/or the integrated circuit dies50are buried or covered. The encapsulant120is further formed in gap regions between the integrated circuit dies50, if present. The encapsulant120may be applied in liquid or semi-liquid form and then subsequently cured.

InFIG. 7, a planarization process is performed on the encapsulant120to expose the through vias116and the die connectors66. The planarization process may also remove material of the through vias116, dielectric layer68, and/or die connectors66until the die connectors66and through vias116are exposed. Top surfaces of the through vias116, die connectors66, dielectric layer68, and encapsulant120are coplanar after the planarization process. The planarization process may be, for example, a chemical-mechanical polish (CMP), a grinding process, or the like. In some embodiments, the planarization may be omitted, for example, if the through vias116and/or die connectors66are already exposed.

InFIGS. 8 through 12, a front-side redistribution structure122(seeFIG. 11) is formed over the encapsulant120, through vias116, and integrated circuit dies50. The front-side redistribution structure122includes dielectric layers124,128,132, and136; metallization patterns126,130, and134; and pads138A and138B. The metallization patterns may also be referred to as redistribution layers or redistribution lines. The front-side redistribution structure122is shown as an example having three layers of metallization patterns. More or fewer dielectric layers and metallization patterns may be formed in the front-side redistribution structure122. If fewer dielectric layers and metallization patterns are to be formed, steps and process discussed below may be omitted. If more dielectric layers and metallization patterns are to be formed, steps and processes discussed below may be repeated.

InFIG. 8, the dielectric layer124is deposited on the encapsulant120, through vias116, and die connectors66. In some embodiments, the dielectric layer124is formed of a photo-sensitive material such as PBO, polyimide, BCB, or the like, which may be patterned using a lithography mask. The dielectric layer124may be formed by spin coating, lamination, CVD, the like, or a combination thereof. The dielectric layer124is then patterned. The patterning forms openings exposing portions of the through vias116and the die connectors66. The patterning may be by an acceptable process, such as by exposing the dielectric layer124to light when the dielectric layer124is a photo-sensitive material or by etching using, for example, an anisotropic etch. If the dielectric layer124is a photo-sensitive material, the dielectric layer124can be developed after the exposure.

InFIG. 9, the dielectric layer128is deposited on the metallization pattern126and dielectric layer124. The dielectric layer128may be formed in a manner similar to the dielectric layer124, and may be formed of a similar material as the dielectric layer124.

The metallization pattern130is then formed. The metallization pattern130includes line portions on and extending along the major surface of the dielectric layer128. The metallization pattern130further includes via portions extending through the dielectric layer128to physically and electrically couple the metallization pattern126. The metallization pattern130may be formed in a similar manner and of a similar material as the metallization pattern126. In some embodiments, the metallization pattern130has a different size than the metallization pattern126. For example, the conductive lines and/or vias of the metallization pattern130may be wider or thicker than the conductive lines and/or vias of the metallization pattern126. Further, the metallization pattern130may be formed to a greater pitch than the metallization pattern126.

The metallization pattern134is then formed. The metallization pattern134includes line portions on and extending along the major surface of the dielectric layer132. The metallization pattern134further includes via portions extending through the dielectric layer132to physically and electrically couple the metallization pattern130. The metallization pattern134may be formed in a similar manner and of a similar material as the metallization pattern126. The metallization pattern134is the topmost metallization pattern of the front-side redistribution structure122. As such, all of the intermediate metallization patterns of the front-side redistribution structure122(e.g., the metallization patterns126and130) are disposed between the metallization pattern134and the integrated circuit dies50. In some embodiments, the metallization pattern134has a different size than the metallization patterns126and130. For example, the conductive lines and/or vias of the metallization pattern134may be wider or thicker than the conductive lines and/or vias of the metallization patterns126and130. Further, the metallization pattern134may be formed to a greater pitch than the metallization pattern130.

InFIG. 11, the dielectric layer136is deposited on the metallization pattern134and dielectric layer132. The dielectric layer136may be formed in a manner similar to the dielectric layer124, and may be formed of the same material as the dielectric layer124. The dielectric layer136is the topmost dielectric layer of the front-side redistribution structure122. As such, all of the metallization patterns of the front-side redistribution structure122(e.g., the metallization patterns126,130, and134) are disposed between the dielectric layer136and the integrated circuit dies50. Further, all of the intermediate dielectric layers of the front-side redistribution structure122(e.g., the dielectric layers124,128,132) are disposed between the dielectric layer136and the integrated circuit dies50.

InFIG. 12, the pads138A and138B are formed on and extending through the dielectric layer136. As an example to form the pads138A and138B, the dielectric layer136may be patterned to form openings exposing portions of the metallization pattern134. The patterning may be by an acceptable process, such as by exposing the dielectric layer136to light when the dielectric layer136is a photo-sensitive material or by etching using, for example, an anisotropic etch. If the dielectric layer136is a photo-sensitive material, the dielectric layer136can be developed after the exposure. The openings for the pads138A and138B may be wider than the openings for the conductive via portions of the metallization patterns126,130, and134. A seed layer is formed over the dielectric layer136and in the openings. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the pads138A and138B. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may comprise a metal, like copper, titanium, tungsten, aluminum, or the like. Then, the photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and conductive material form the pads138A and138B. In embodiments where the pads138A and138B are formed differently, more photoresist and patterning steps may be utilized.

In the embodiment shown, the pads138A are larger than the pads138B. For example, the pads138A can have a width in range of 30 about μm to about 1000 μm, and the pads138B can have a width in range of 100 about μm to about 760 μm. In another embodiment, the pads138A can be smaller than the pads138B. The pads138A may be used to couple to surface-mounted passive devices146(seeFIG. 14), and the pads138B may be used to couple to conductive connectors164(seeFIG. 17). It should be appreciated that the pads138A and138B could be a variety of connection types and sizes. Further, the pads138A and138B could be the same size. In some embodiments, the pads138A are micro bumps and the pads138B are under bump metallurgies (UBMs). The pads138A and138B may be formed in different processes. For example, a first photoresist may be formed having a pattern for the pads138A, a first plating process may be performed in the pattern of the first photoresist, and the first photoresist may be removed. A second photoresist may then be formed having a pattern for the pads138B, a second plating process may be performed in the pattern of the second photoresist, and the second photoresist may be removed.

InFIG. 13, protective structures140are formed on and around the pads138A. In the embodiment shown, the protective structures140are each a single continuous material, and are formed from an epoxy flux. In another embodiment, the protective structures140can comprise multiple layers of material. An epoxy flux is a polymeric material that includes a flux for forming conductive connectors, and also includes a resin for encapsulating and protecting the conductive connectors after formation. The resin may be an epoxy-based resin, a phenol-based resin, or the like. The flux may be hydrochloric acid, phosphoric acid, citric acid, hydrobromic acid, a carboxylic acid, an amino acid, a salt of a mineral acid with amines, or the like. Forming the protective structures140from an epoxy flux obviates the use of a flux when devices are subsequently attached to the pads138A. The protective structures140may be formed by printing, jetting, or dispensing the epoxy flux on the pads138A with (or without) a stencil142. The stencil142has openings144corresponding to target regions where the epoxy flux will be dispensed. The use of preformed protective structures140also obviates the need for molding an underfill beneath subsequently attached devices. The protective structures140may be printed with the stencil142quicker than a capillary flow process for forming an underfill. Processing time for forming the first package component100may thus be reduced. Further, the epoxy flux is not cured immediately after being dispensed. Rather, the curing process is delayed and is performed concurrently with a reflow process for subsequently formed reflowable materials. One or more thermal processing steps may thus be omitted, and the uncured protective structures140are viscous such that they may be easily molded and used as an adhesive during processing.

InFIG. 14, passive devices146are attached to the pads138A.FIGS. 15A through 15Dare detailed views of a region10of the first package component100, in accordance with various embodiments.FIGS. 15A through 15Dillustrate additional details of the passive devices146, and are described in conjunction withFIG. 14. The passive devices146include one or more passive devices in a main structure of the passive devices146. The main structure could include a substrate and/or encapsulant. In the embodiments including a substrate, the substrate could be a semiconductor substrate, such as silicon, doped or undoped, or an active layer of a SOI substrate. The semiconductor substrate may include other semiconductor material, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, and/or GaInAsP; or combinations thereof. Other substrates, such as multi-layered or gradient substrates, may also be used. The passive devices may include a capacitor, resistor, inductor, the like, or a combination thereof. The passive devices may be formed in and/or on the semiconductor substrate and/or within the encapsulant and may be interconnected by interconnect structures formed by, for example, metallization patterns in one or more dielectric layers on the main structure to form the passive devices146. The passive devices146may be surface mount devices (SMDs), 2-terminal integrated passive devices (IPDs), multi-terminal IPDs, or other types of passive devices. Pads148are formed on and coupled to the passive devices146, to which external connections are made. The pads148may be, e.g., micro bumps. Conductive connectors150are formed on ends of the pads148and comprise, e.g., a reflowable material. The conductive connectors150may also be referred to as reflowable connectors.

The passive devices146may be attached to the front-side redistribution structure122using, for example, a pick-and-place tool. The pads138A and148are aligned during placement. The passive devices146are pressed in the uncured protective structures140, such that the pads148and conductive connectors150extend into and are surrounded by the uncured protective structures140. The uncured protective structures140adhere the passive devices146to the front-side redistribution structure122. The uncured protective structures140may not extend along sidewalls146S of the passive devices146, e.g., the sidewalls146S of the passive devices146may be free from the material of the uncured protective structures140. The protective structures140have a main body140B and fillets140F. As noted above, the curing process for the protective structures140is delayed and combined with a subsequent reflow step. By omitting a thermal processing step at this stage of processing, the fillets140F of the protective structures140may be shortened. In some embodiments, the fillets140F have a length L1in the range from about 1 μm to about 200 μm. By reducing the length L1of the fillets140F, the minimum spacing between adjacent passive devices146(or adjacent pads138B) may be reduced by up to 200 μm. In some embodiments, the spacing between adjacent passive devices146(or adjacent pads138B) is in the range from about 100 μm to about 600 μm, such as about 150 μm. The overall footprint of the passive devices146may thus be reduced, thereby improving the circuit routing of the front-side redistribution structure122.

The viscous material of the uncured protective structures140has a high surface tension, and as such, voids152may be formed between adjacent ones of the conductive connectors150during placement. In some embodiments (e.g.,FIG. 15A), the protective structures140separate the voids152from the passive devices146, the dielectric layer136, the conductive connectors150, and the pads138A and148. In some embodiments (e.g.,FIG. 15B), the protective structures140separate the voids152from the passive devices146and the dielectric layer136, and the voids152expose surfaces of the conductive connectors150and the pads138A and148. In some embodiments (e.g.,FIG. 15C), the protective structures140separate the voids152from the conductive connectors150and the pads138A and148, and the voids152expose surfaces of the passive devices146and the dielectric layer136. In some embodiments (e.g.,FIG. 15D), the voids152expose surfaces of the passive devices146, the dielectric layer136, the conductive connectors150, and the pads138A and148.

AlthoughFIGS. 15A through 15Dillustrate the protective structures140as each having a single void152, it should be appreciated that the protective structures140may each have multiple voids152. Further, althoughFIGS. 15A through 15Dillustrate the single void152as being in the center of each protective structure140, it should be appreciated that the voids152may be disposed in other locations. For example, the voids152may be disposed in the centers of the protective structures140, or along edges of the protective structures140.

InFIG. 16, flux154is formed on the pads138B. The flux154is formed during a cleaning process for deoxidizing surfaces of the pads138B. The flux154is different from the epoxy flux of the protective structures140. For example, the flux154may be a non-epoxy flux. In some embodiments, the flux154is water, hydrochloric acid, phosphoric acid, citric acid, hydrobromic acid, a carboxylic acid, an amino acid, a salt of a mineral acid with amines, or the like. The flux154may be dispensed on the pads138B with a stencil156. The stencil156has openings158corresponding to target regions where the flux154will be dispensed (e.g., corresponding to the pattern of the pads138B). The stencil156also has recesses160corresponding to the passive devices146. The recesses160of the stencil156cover the passive devices146during the cleaning process, such that the passive devices146are disposed in the recesses160and protected (e.g., not contacted by the flux154) during the flux dispensing process.

InFIG. 17, reflowable material162is formed on the flux154. The reflowable material162may include solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the reflowable material162is solder, which may be formed by methods such as evaporation, electroplating, printing, solder transfer, ball placement, or the like. In some embodiments, a repair process is performed after the reflowable material162is formed. During the repair process, defective or missing reflowable material162is identified and replaced. The reflowable material162may also be referred to as reflowable connectors.

InFIG. 18, conductive connectors164are formed on the pads138B by reflowing the reflowable material162. The resulting conductive connectors164may be ball grid array (BGA) connectors, solder balls, or the like. In some embodiments, a single thermal processing step is performed to simultaneously cure the protective structures140, reflow the conductive connectors150, and reflow the reflowable material162. Details about the thermal processing step are discussed further below with respect toFIG. 19. After the thermal processing step, the conductive connectors150physically and electrically couple the passive devices146to the front-side redistribution structure122. Further, the reflowable material162is shaped into desired bump shapes by the thermal processing step, thus forming the conductive connectors164. The flux154may be burned and/or evaporated during the thermal processing step, thereby removing the flux154. Finally, the protective structures140are cured by the thermal processing step, allowing separate curing processes (e.g., subsequent to the reflow) to be omitted. The cured protective structures140protect the conductive connectors150and the pads138A and148, obviating the need for forming an underfill beneath the passive devices146. A molding step for the underfill and a curing step for the underfill may thus be eliminated, thereby reducing processing time for forming the first package component100. Manufacturing costs may thus be reduced.

FIG. 19is a graph illustrating the temperature and duration of the thermal processing step, in accordance with some embodiments. The thermal processing step is performed at several different temperatures. First, the temperature is increased from an initial temperature T0(e.g., room temperature) to a first temperature T1of about 150° C. The temperature is then increased to a second temperature T2of about 200° C., over a time period t1of from about 30 seconds to about 180 seconds. The increase from T1to T2can be non-linear. The temperature is then further increased to a temperature T3of about 217° C., and even further increased to a temperature T4of about 260° C. Reflow of the reflowable material162occurs between 217° C. and 260° C. and curing of the protective structures140occurs during the reflow process. The temperature is maintained above the minimum reflow temperature T3for a total time period t2of from about 30 seconds to about 150 seconds, with the temperature being maintained at the maximum reflow temperature T4for a maximum time period t3of from about 20 seconds to about 100 seconds. The temperature is then decreased back to the initial temperature T0as the reflowable material162cools. The rate of increase from the minimum reflow temperature T3to the maximum reflow temperature T4can be up to about 3° C./second, and the rate of decrease from the maximum reflow temperature T4to the minimum reflow temperature T3can be up to about 6° C./second. The total amount of elapsed time between the initial temperature and the maximum reflow temperature T4can be up to about 8 minutes.

InFIG. 20, a carrier substrate de-bonding is performed to detach (or “de-bond”) the carrier substrate102from the back-side redistribution structure106, e.g., the dielectric layer108. In accordance with some embodiments, the de-bonding includes projecting a light such as a laser light or an UV light on the release layer104so that the release layer104decomposes under the heat of the light and the carrier substrate102can be removed. The structure is then flipped over and placed on a tape.

InFIG. 21, conductive connectors166are formed extending through the dielectric layer108to contact the metallization pattern110. Openings are formed through the dielectric layer108to expose portions of the metallization pattern110. The openings may be formed, for example, using laser drilling, etching, or the like. The conductive connectors166are formed in the openings. In some embodiments, the conductive connectors166comprise flux and are formed in a flux dipping process. In some embodiments, the conductive connectors166comprise a conductive paste such as solder paste, silver paste, or the like, and are dispensed in a printing process. In some embodiments, the conductive connectors166are formed in a manner similar to the conductive connectors164, and may be formed of the same material as the conductive connectors164.

FIGS. 22 and 23illustrate formation and implementation of device stacks, in accordance with some embodiments. The device stacks are formed from the integrated circuit packages formed in the first package component100. The device stacks may also be referred to as package-on-package (PoP) structures.

InFIG. 22, second package components200are coupled to the first package component100. One of the second package components200are coupled in each of the package regions100A and100B to form an integrated circuit device stack in each region of the first package component100.

The second package components200include a substrate202and one or more dies coupled to the substrate202. In the illustrated embodiment, the dies include stacked dies210A and210B. In some embodiments, the dies (or die stacks) may be disposed side-by-side coupled to a same surface of the substrate202. The substrate202may be made of a semiconductor material such as silicon, germanium, diamond, or the like. In some embodiments, compound materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations of these, and the like, may also be used. Additionally, the substrate202may be a silicon-on-insulator (SOI) substrate. Generally, an SOI substrate includes a layer of a semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof. The substrate202is, in one alternative embodiment, based on an insulating core such as a fiberglass reinforced resin core. One example core material is fiberglass resin such as FR4. Alternatives for the core material include bismaleimide-triazine (BT) resin, or alternatively, other printed circuit board (PCB) materials or films. Build up films such as Ajinomoto build-up film (ABF) or other laminates may be used for substrate202.

The substrate202may include active and passive devices (not shown). A wide variety of devices such as transistors, capacitors, resistors, combinations of these, and the like may be used to generate the structural and functional requirements of the design for the second package components200. The devices may be formed using any suitable methods.

The substrate202may also include metallization layers (not shown) and conductive vias208. The metallization layers may be formed over the active and passive devices and are designed to connect the various devices to form functional circuitry. The metallization layers may be formed of alternating layers of dielectric (e.g., low-k dielectric material) and conductive material (e.g., copper) with vias interconnecting the layers of conductive material and may be formed through any suitable process (such as deposition, damascene, dual damascene, or the like). In some embodiments, the substrate202is substantially free of active and passive devices.

The substrate202may have bond pads204on a first side of the substrate202to couple to the stacked dies210A and210B, and bond pads206on a second side of the substrate202, the second side being opposite the first side of the substrate202, to couple to the conductive connectors166. In some embodiments, the bond pads204and206are formed by forming recesses into dielectric layers (not shown) on the first and second sides of the substrate202. The recesses may be formed to allow the bond pads204and206to be embedded into the dielectric layers. In other embodiments, the recesses are omitted as the bond pads204and206may be formed on the dielectric layer. In some embodiments, the bond pads204and206include a thin seed layer made of copper, titanium, nickel, gold, palladium, the like, or a combination thereof. The conductive material of the bond pads204and206may be deposited over the thin seed layer. The conductive material may be formed by an electro-chemical plating process, an electroless plating process, CVD, atomic layer deposition (ALD), PVD, the like, or a combination thereof. In an embodiment, the conductive material of the bond pads204and206is copper, tungsten, aluminum, silver, gold, the like, or a combination thereof.

In an embodiment, the bond pads204and bond pads206are UBMs that include three layers of conductive materials, such as a layer of titanium, a layer of copper, and a layer of nickel. Other arrangements of materials and layers, such as an arrangement of chrome/chrome-copper alloy/copper/gold, an arrangement of titanium/titanium tungsten/copper, or an arrangement of copper/nickel/gold, may be utilized for the formation of the bond pads204and206. Any suitable materials or layers of material that may be used for the bond pads204and206are fully intended to be included within the scope of the current application. In some embodiments, the conductive vias208extend through the substrate202and couple at least one of the bond pads204to at least one of the bond pads206.

In the illustrated embodiment, the stacked dies210A and210B are coupled to the substrate202by wire bonds212, although other connections may be used, such as conductive bumps. In an embodiment, the stacked dies210A and210B are stacked memory dies. For example, the stacked dies210A and210B may be memory dies such as low-power (LP) double data rate (DDR) memory modules, such as LPDDR1, LPDDR2, LPDDR3, LPDDR4, or the like memory modules.

The stacked dies210A and210B and the wire bonds212may be encapsulated by a molding material214. The molding material214may be molded on the wire bonds212and the stacked dies210A and210B, for example, using compression molding. In some embodiments, the molding material214is a molding compound, a polymer, an epoxy, silicon oxide filler material, the like, or a combination thereof. A curing process may be performed to cure the molding material214; the curing process may be a thermal curing, a UV curing, the like, or a combination thereof.

In some embodiments, the wire bonds212and the stacked dies210A and210B are buried in the molding material214, and after the curing of the molding material214, a planarization step, such as a grinding, is performed to remove excess portions of the molding material214and provide a substantially planar surface for the second package components200.

After the second package components200are formed, the second package components200are mechanically and electrically bonded to the first package component100by way of the conductive connectors166, the bond pads206, and the back-side redistribution structure106. In some embodiments, the stacked dies210A and210B may be coupled to the integrated circuit dies50through the wire bonds212, the bond pads204and206, conductive vias208, the conductive connectors166, the back-side redistribution structure106, the through vias116, and the front-side redistribution structure122.

In some embodiments, a solder resist is formed on the side of the substrate202opposing the stacked dies210A and210B. The conductive connectors166may be disposed in openings in the solder resist to be electrically and mechanically coupled to conductive features (e.g., the bond pads206) in the substrate202. The solder resist may be used to protect areas of the substrate202from external damage.

In some embodiments, the conductive connectors166have an epoxy flux formed thereon before they are reflowed with at least some of the epoxy portion of the epoxy flux remaining after the second package components200are attached to the first package component100.

In some embodiments, an underfill is formed between the first package component100and the second package components200, surrounding the conductive connectors166. The underfill may reduce stress and protect the joints resulting from the reflowing of the conductive connectors166. The underfill may be formed by a capillary flow process after the second package components200are attached, or may be formed by a suitable deposition method before the second package components200are attached. In embodiments where the epoxy flux is formed, it may act as the underfill.

InFIG. 23, a singulation process is performed by sawing along scribe line regions, e.g., between the first package region100A and the second package region100B. The sawing singulates the first package region100A from the second package region100B. The resulting, singulated device stack is from one of the first package region100A or the second package region100B. In some embodiments, the singulation process is performed after the second package components200are coupled to the first package component100. In other embodiments, the singulation process is performed before the second package components200are coupled to the first package component100, such as after the carrier substrate102is de-bonded and the conductive connectors166are formed.

Each singulated first package component100is then mounted to a package substrate300using the conductive connectors164. The package substrate300includes a substrate core302and bond pads304over the substrate core302. The substrate core302may be made of a semiconductor material such as silicon, germanium, diamond, or the like. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations of these, and the like, may also be used. Additionally, the substrate core302may be a SOI substrate. Generally, an SOI substrate includes a layer of a semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or combinations thereof. The substrate core302is, in one alternative embodiment, based on an insulating core such as a fiberglass reinforced resin core. One example core material is fiberglass resin such as FR4. Alternatives for the core material include bismaleimide-triazine BT resin, or alternatively, other PCB materials or films. Build up films such as ABF or other laminates may be used for substrate core302.

The substrate core302may include active and passive devices (not shown). As one of ordinary skill in the art will recognize, a wide variety of devices such as transistors, capacitors, resistors, combinations of these, and the like may be used to generate the structural and functional requirements of the design for the device stack. The devices may be formed using any suitable methods.

The substrate core302may also include metallization layers and vias (not shown), with the bond pads304being physically and/or electrically coupled to the metallization layers and vias. The metallization layers may be formed over the active and passive devices and are designed to connect the various devices to form functional circuitry. The metallization layers may be formed of alternating layers of dielectric (e.g., low-k dielectric material) and conductive material (e.g., copper) with vias interconnecting the layers of conductive material and may be formed through any suitable process (such as deposition, damascene, dual damascene, or the like). In some embodiments, the substrate core302is substantially free of active and passive devices.

In some embodiments, the conductive connectors164are reflowed to attach the first package component100to the bond pads304. The conductive connectors164electrically and/or physically couple the package substrate300, including metallization layers in the substrate core302, to the first package component100. In some embodiments, a solder resist is formed on the substrate core302. The conductive connectors164may be disposed in openings in the solder resist to be electrically and mechanically coupled to the bond pads304. The solder resist may be used to protect areas of the substrate202from external damage.

The conductive connectors164may have an epoxy flux formed thereon before they are reflowed with at least some of the epoxy portion of the epoxy flux remaining after the first package component100is attached to the package substrate300. This remaining epoxy portion may act as an underfill to reduce stress and protect the joints resulting from the reflowing the conductive connectors164. In some embodiments, an underfill306may be formed between the first package component100and the package substrate300and surrounding the conductive connectors164. The underfill306may be formed by a capillary flow process after the first package component100is attached or may be formed by a suitable deposition method before the first package component100is attached. The underfill306contacts surfaces of the surface-mounted passive devices146and protective structures140.

In some embodiments, passive devices (e.g., surface mount devices (SMDs), not illustrated) may also be attached to the package substrate300(e.g., to the bond pads304). For example, the passive devices may be bonded to a same surface of the first package component100or the package substrate300as the conductive connectors164. The passive devices may be attached to the package component100prior to mounting the first package component100on the package substrate300, or may be attached to the package substrate300prior to or after mounting the first package component100on the package substrate300.

It should be appreciated that the first package component100may be implement in other device stacks. For example, a PoP structure is shown, but the first package component100may also be implemented in a Flip Chip Ball Grid Array (FCBGA) package. In such embodiments, the first package component100is mounted to a substrate such as the package substrate300, but the second package component200is omitted. Instead, a lid or heat spreader may be attached to the first package component100. When the second package component200is omitted, the back-side redistribution structure106and through vias116may also be omitted.

Embodiments may achieve advantages. Dispensing the protective structures140before attachment of the passive devices146may obviate the need for an underfill, reducing the overall footprint of the passive devices146. By curing the protective structures140and reflowing the reflowable material162in a same thermal processing step, one or more thermal processing steps may be omitted, thereby decreasing wafer processing time and manufacturing costs.

In an embodiment, a method includes: encapsulating an integrated circuit die with an encapsulant; forming a redistribution structure on the encapsulant, the redistribution structure being electrically connected to the integrated circuit die, the redistribution structure including a first pad and a second pad; dispensing an epoxy flux on the first pad to form a protective structure; prior to curing the epoxy flux, pressing a passive device into the protective structure to physically couple the passive device to the first pad; forming a first conductive connector on the second pad; and performing a single thermal process to simultaneously cure the protective structure and reflow the first conductive connector, the first conductive connector physically and electrically coupling the passive device to the first pad after the single thermal process.

In some embodiments, the method further includes: placing the integrated circuit die adjacent to a conductive via, the redistribution structure being electrically connected to the conductive via; and encapsulating the conductive via with the encapsulant. In some embodiments of the method, the passive device includes a second conductive connector, the passive device being pressed into the protective structure until the second conductive connector contacts the first pad, the second conductive connector including a reflowable material. In some embodiments of the method, performing the single thermal process reflows the second conductive connector. In some embodiments of the method, the protective structure has a void disposed between the passive device and the redistribution structure. In some embodiments of the method, the protective structure separates the void from the passive device, the redistribution structure, the second conductive connector, and the first pad. In some embodiments of the method, the protective structure separates the void from the passive device and the redistribution structure, and the void exposes surfaces of the second conductive connector and the first pad. In some embodiments of the method, the protective structure separates the void from the second conductive connector and the first pad, and the void exposes surfaces of the passive device and the redistribution structure. In some embodiments of the method, the void exposes surfaces of the second conductive connector, the first pad, the passive device, and the redistribution structure.

In an embodiment, a method includes: encapsulating an integrated circuit die with an encapsulant; depositing a first dielectric layer over the encapsulant and the integrated circuit die; forming a first metallization pattern extending along and through the first dielectric layer, the first metallization pattern electrically coupling the integrated circuit die; depositing a second dielectric layer over the first metallization pattern; forming a first pad and a second pad through the second dielectric layer, the first pad and the second pad electrically coupling the first metallization pattern; adhering a passive device to the first pad and the second dielectric layer with an epoxy flux, the passive device including a first reflowable connector, the first reflowable connector being physically and electrically coupled to the first pad after adhering the passive device; forming first flux on the second pad, the first flux being different from the epoxy flux; forming a second reflowable connector on the first flux; and performing a single thermal process to simultaneously cure the epoxy flux, remove the first flux, reflow the first reflowable connector, and reflow the second reflowable connector.

In some embodiments, the method further includes: printing the epoxy flux on the first pad with a first stencil, the first stencil having a first opening exposing the first pad. In some embodiments of the method, forming the first flux on the second pad includes: printing the first flux on the second pad with a second stencil, the second stencil having a second opening exposing the second pad, the second stencil having a recess covering the passive device. In some embodiments of the method, after adhering the passive device, the epoxy flux has a main body disposed between the passive device and the second dielectric layer and a fillet extending along the second dielectric layer away from the main body, the main body having a void disposed therein. In some embodiments of the method, the fillet of the epoxy flux extends away from the main body by a first distance, the first distance being from 1 μm to 200 μm. In some embodiments, the method further includes: attaching a package substrate to the second pad with the second reflowable connector; and forming an underfill between the package substrate and the second dielectric layer, the underfill contacting sides of the epoxy flux and the passive device.

In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially encapsulating the integrated circuit die; a redistribution structure on the encapsulant, the redistribution structure being electrically connect to the integrated circuit die, the redistribution structure including a pad; a passive device including a conductive connector physically and electrically connected to the pad; and a protective structure disposed between the passive device and the redistribution structure, the protective structure surrounding the conductive connector, the protective structure including an epoxy flux, the protective structure having a void disposed therein.

In some embodiments of the device, the protective structure separates the void from the passive device, the redistribution structure, the conductive connector, and the pad. In some embodiments of the device, the protective structure separates the void from the passive device and the redistribution structure, and the void exposes surfaces of the conductive connector and the pad. In some embodiments of the device, the protective structure separates the void from the conductive connector and the pad, and the void exposes surfaces of the passive device and the redistribution structure. In some embodiments of the device, the void exposes surfaces of the conductive connector, the pad, the passive device, and the redistribution structure.