Interpolator linearity testing system

According to some embodiments, an interpolated clock signal having a first frequency is received, and the interpolated clock signal is periodically sampled based on a reference clock signal to generate periodically-sampled values, the reference clock signal having substantially the first frequency. A phase of the interpolated clock signal may be set to a phase degree at which the periodically-sampled values resolve to more than one value, and the phase of the interpolated clock signal may be incrementally changed until the periodically-sampled values resolve to one value. A non-linearity of the interpolated clock signal may be determined based on the number of incremental changes.

BACKGROUND

An interpolator may be used to mix two or more different input signals to provide an output signal. In a transceiver, an interpolator may generate an interpolated clock signal having a desired phase by mixing two or more out-of-phase clock signals. Such an interpolator may be used in conjunction with a tracking loop to extract clock information from a data stream received by the transceiver.

Some interpolators may be controlled to provide an output signal having any one of a linear sequence of phase degrees. For example, an interpolator having thirty-two modes of operation may provide output signals having thirty-two different phase degrees, spaced every 360/32=11.5 degrees. An interpolator exhibiting such linear behavior may be desired in some circumstances. It is currently difficult to efficiently detect non-linear behavior in some types of interpolators.

DETAILED DESCRIPTION

FIG. 1is a circuit diagram of interpolator10according to some embodiments. Interpolator10includes pairs21,22,23and24of n-channel metal oxide semiconductor field effect transistors (nMOSFETs) and barrel-shift register30. Interpolator10may operate to receive at least two clock signals having different clock phases and to provide an output clock signal (CLKOUT) having an output clock phase that is based on the at least two received clock signals.

First input terminals of pairs21,22,23and24receive input clock signals with phases 0°, 90°, 180° and 270°, respectively. Second input terminals of pairs21,22,23and24receive input clock signals that are 180° out of phase with the input clock signal received by a respective first input terminal. According to the illustrated example, second input terminals of pairs21,22,23and24receive input clock signals with phases 180°, 270°, 0° and 90°, respectively.

Barrel-shift register30comprises thirty-two individual registers. Eight individual registers32are coupled to pair21. Accordingly, eight individual circuits are coupled to pair21, each of the circuits including a register. Each of these eight circuits shall be referred to herein as an interpolator leg. Similarly, eight interpolator legs comprising registers34,36and38are coupled to pairs22,23, and24, respectively.

During some conventional interpolator operation, eight legs of interpolator10are activated to determine two input clock phases that will be mixed by interpolator10.FIG. 1illustrates the activation of six legs associated with pair21and two legs associated with pair22. As shown, a leg may be activated by asserting a bit of a register associated with the leg. In the illustrated example, output clock signal CLKOUT has an output clock phase that is a weighted mix of 0° and 90°. The output clock phase will be closer to 0° than to 90° since more of the activated legs are associated with pair21than with pair22.

The output clock phase may be changed by barrel-shifting the eight asserted bits through register30. In the illustrated embodiment, each shift of the eight asserted bits should advance a phase of the output clock signal by a step size of 11.5°. However, implementation errors and/or manufacturing defects may result in unequal step sizes as the bits are shifted through register30.

FIG. 2is a block diagram of a testing system according to some embodiments. Testing system40may be used to evaluate the linearity of interpolator10. Testing system includes interpolator10, flip-flop50and testing state machine60.

Generally, flip-flop50receives an interpolated clock signal from interpolator10at its “D” input terminal. Flip-flop50also receives a reference clock signal at its clock terminal. The reference clock signal may have substantially the same frequency as the interpolated clock signal. Flip-flop50therefore periodically samples the interpolated clock signal based on the reference clock signal. Although flip-flop50is illustrated as a D flip-flop, any other suitable flip-flop or latch may be used in conjunction with some embodiments. Flip-flop50transmits the periodically-sampled values to testing state machine60.

Based on the periodically-sampled values, testing state machine60sets a phase of the interpolated clock signal to a phase degree at which the periodically-sampled values resolve to more than one value. The phase degree may be one that causes flip-flop50to sample the values in a metastable manner.

FIG. 3includes timing diagrams for illustrating metastable operation of flip-flop50according to some embodiments. Diagram a) illustrates the reference clock signal as well as setup and hold times associated with flip-flop50. A setup time is a time period prior to the leading edge of the sampling (reference) clock during which data at the D terminal must be valid to assure valid data at the Q output of flip-flop50. A hold time is a time period after the leading edge of the sampling (reference) clock during which data at the D terminal must be valid to assure valid data at the Q output.

Together, the setup and hold times represent an aperture window surrounding the leading edge of the sampling (reference) clock. Data that changes at the D input of flip-flop50during this window violates either the setup time or the hold time constraint of flip-flop50. Accordingly, the data is sampled in a metastable manner. As a result, a corresponding sampled value output by flip-flop50is either a 1 or a 0, and does not reliably indicate the data present at the D input at the time of sampling.

Diagram b) illustrates a scenario in which a phase of the interpolated clock signal, which is received at the D terminal of flip-flop50, is closely aligned with a phase of the reference clock. As shown, the interpolated clock signal transitions from 0 to 1 during the aperture window of flip-flop50. The periodically-sampled values output by flip-flop50will comprise a mix of binary 1's and 0's because the sampling is metastable. Therefore, by setting a phase of the interpolated clock signal to a phase degree that results in periodically-sampled values including a mix of binary 1's and 0's, testing state machine60may assure metastable operation of flip-flop50.

After setting the phase as described above, testing state machine60incrementally changes the phase of the interpolated clock signal until the periodically-sampled values resolve to one value. Diagrams c) and d) ofFIG. 3illustrate two scenarios in which the periodically-sampled values output by flip-flop50will resolve to one value. In diagram c), a phase degree of the interpolated clock signal leads a phase degree of the reference clock signal to an extent that no transitions of the interpolated clock signal (terminal D of flip-flop50) occur during the aperture window of flip-flop50. The interpolated clock signal is a binary 1 during the aperture window, so each periodically-sampled value in the illustrated scenario is a binary 1.

Diagram d) shows a phase degree of the interpolated clock signal lagging a phase degree of the reference clock signal to an extent that no transitions of the interpolated clock signal occur during the aperture window. The interpolated clock signal is a binary 0 during the aperture window, so each periodically-sampled value in diagram d) scenario is a binary 0.

Testing state machine60may set and change the phase of the interpolated clock signal as described above by instructing shift register30of interpolator10to barrel-shift its asserted bits. Testing state machine60may then determine a number of incremental changes made to the phase of the interpolated signal until the periodically-sampled values resolved to one value. The number may be stored within testing state machine60or in a register (not shown) separate from testing state machine60. The above process may be repeated for at least one other phase degree of the reference clock signal. Next, non-linearity of interpolator10may be determined based on the number of incremental changes determined for the first reference clock phase degree and the number of changes determined for the other (at least one) reference clock phase degree. This determination will be described in detail below.

In some embodiments, system40resides on a single integrated circuit. Interpolator10may comprise an element of a transceiver on such an integrated circuit. One or more elements of testing system40may be physically separate from other elements. According to some embodiments, interpolator10is an element of an integrated circuit package (e.g., a microprocessor) to be tested, and elements50and60may comprise hardware and/or software disposed within an external testing device. The external testing device may interface with interpolator10through test pins and/or dedicated pins of the integrated circuit package.

FIGS. 4A and 4Bcomprise a flow diagram of testing method100according to some embodiments. Method100may be performed by any suitable combination of hardware and software, and some of method100may be performed manually. Method100may be used to test interpolator functionality in a high volume manufacturing environment.

The reference clock signal and the interpolated clock signal are initialized at101. Initialization may comprise procedures used to begin transmission of each signal at substantially identical frequencies. Relative phase degrees of each signal need not be established at101, although they may be in some embodiments. Initialization of the two clock signals begins periodic sampling of the interpolated clock signal based on the reference clock signal.

Referring to system40, some embodiments of101may comprise asserting particular bits of register30and applying bias voltages/currents to other elements of interpolator10so as to generate output clock signal CLKOUT. Corresponding procedures may be used to begin generation of the reference clock signal. Some systems for generating the reference clock signal will be described below with respect toFIGS. 7 through 9. After101, flip-flop50of system40therefore begins to periodically sample the interpolated clock signal based on the reference clock signal to generate periodically-sampled values.

According to some embodiments of101, a phase of the reference clock signal is set to a reference phase degree, and a phase of the interpolated clock signal is set to a phase degree different from the reference phase degree. It is then determined that the periodically-sampled values resolve to one value. Such a scenario may be illustrated by diagram c) and diagram d) ofFIG. 3. In other words, the phase degree of the interpolated clock signal either leads or lags the reference phase degree by an amount sufficient to comply with the aperture window of flip-flop50.

FIG. 5is a diagram to further illustrate a relationship between the phase difference of the two clock signals and the periodically-sampled values according to some embodiments. Arrow200represents a phase degree of the interpolated clock signal and arrow210represents a phase degree of the reference clock signal after101. Arrow200leads arrow210and therefore, as shown in diagram c) ofFIG. 3, the periodically-sampled values resolve to the value directly beneath arrow200, binary 1.

At102, it is determined if the periodically-sampled values are mixed, i.e., resolve to more than one value. Such a determination would indicate that flip-flop50is operating in a metastable state. If the periodically-sampled values are not mixed, the phase of the interpolated clock signal is incrementally changed at103.

Continuing with the above example, the periodically-sampled values initially resolve to only one value. Therefore, testing state machine60incrementally changes the phase of the interpolated clock signal by instructing interpolator10to barrel-shift the bits of register30. In response, arrow200ofFIG. 5moves toward the right.

Flow then returns to102and continues until it is determined that the periodically-sampled values resolve to more than one value. As shown inFIG. 5, the phase of the interpolated clock signal will be changed several times at103until arrow200reaches point A. Point A represents a phase degree at which the interpolated clock signal violates the aperture window of flip-flop50. Accordingly, the periodically-sampled values resolve to more than one value when the phase degree of the interpolated clock signal reaches point A.

Flow continues to104if the determination at102is positive. Point A is stored at104. According to some embodiments of104, testing state machine60stores point A at104by resetting a counter to 0. The phase degree of the interpolated clock signal is then changed again at105. This change may be effected as described above, and graphically, may continue to move arrow200to the right of point A.

Next, at106, it is determined if the periodically-sampled values resolve to one value. If not, flow returns to105to again change the phase degree of the interpolated clock signal. The above-mentioned counter may be incremented by one each time flow returns to105. Flow cycles between105and106until it is determined that the periodically-sampled values resolve to one value.

Returning to the example ofFIG. 5, the phase degree of the interpolated clock signal is changed nine times at105until the periodically-sampled values resolve to one value, binary 0. The phase degree at this point is indicated by point B ofFIG. 5. As shown, point B represents a phase degree at which the interpolated clock signal input to terminal D of flip-flop50no longer violates the aperture window of flip-flop50.

Point B is stored at107. Next, at108, a number of incremental changes made to the phase of the interpolated clock signal between point A and point B is determined and stored. This number, or count, reflects a number of incremental changes made to the phase until the periodically-sampled values resolved to one value. The count may be considered as representing the aperture window of the flip-flop50, expressed in interpolator steps. The count may be stored in association with the current phase degree of the reference clock signal.

FIG. 6Ais a tabular representation of a portion of a register used to store the count. Register300may comprise an element of testing state machine60and/or may be integrated into a same integrated circuit die as system40. In some embodiments, the count may be written to a memory device such as hard disk. Column310includes indices to particular reference clock phase degrees, and column320specifies counts that are stored at108for each phase degree.

After the count is stored, it is determined at109whether all reference clock phase degrees have been tested. The determination of109depends on the number of available reference clock phase degrees and the number of available phase degrees that are to be tested. Assuming additional phase degrees remain to be tested, flow returns to101and continues as described above.

Therefore, a count is stored at108for each tested phase degree of the reference clock signal. Register300illustrates the storage of eight counts, each associated with a different reference clock phase degree. The data of register300is plotted inFIG. 6B. Flow continues from109to110after all reference clock phase degrees have been tested. Then, at110, non-linearity of interpolator10is determined based on the stored counts.

The aperture window of flip-flop50remains substantially constant for a particular set of environmental conditions, including but not limited to manufacturing process, voltage and temperature. Accordingly, the non-linearity of interpolator10may be determined by comparing the counts stored in register300. For example, each stored count Cnwould be equal if interpolator10exhibited perfect phase step size with zero non-linearity. Conversely, variations in the measured Cnshould be interpreted as a measure of non-linearity in the phase step size of interpolator10. The maximum non-linearity for interpolator10of the present example is bounded by n=3 where four incremental changes are equivalent to the seven incremental changes of at n=6.

To obtain an absolute number (in time units) for the non-linearity, some embodiments store the actual phase degree of the interpolated clock at point A, and the actual phase degree of the interpolated clock at point B ofFIG. 5. The real-time distance between the two phase degrees is substantially equally to the aperture window of flip-flop50. The measured aperture window may be divided by the count Cnto determine the average interpolator step size for iteration n.

For example, if the measured aperture window is 40 ps then the phase step size for n=3 is 10 ps and the phase step size for n=6 is 5.7 ps. Hence it can be inferred that the phase step size non-linearity is 10−5.7=4.3 ps. Measurement of the absolute aperture window is not needed for every interpolator under test. A few exemplary samples can be characterized to estimate an empirical threshold level in a high volume manufacturing environment.

Regardless of how the non-linearity is determined at110, the non-linearity is deemed acceptable or unacceptable at111. For example, the non-linearity may be compared against a threshold level of non-linearity. Interpolator10is failed at112if its non-linearity is unacceptable, and passed at113if its non-linearity is acceptable.

FIG. 7is a block diagram of testing system400according to some embodiments. Testing system400includes interpolator10, flip-flop50, testing state machine60, and second interpolator410. Testing system400may operate to determine the non-linearity of interpolator10, using method100or any other suitable method.

Interpolator10, flip-flop50, testing state machine60may operate and be embodied as described above with respect toFIG. 2and method100. During normal (non-test) operation, second interpolator410is “in quadrature” with interpolator10. In other words, a phase of signal CLKOUT from second interpolator410lags a phase of signal CLKOUT from interpolator10by 90°. This relationship may be changed during testing as described above. Two thusly-related interpolators may be used in a transceiver that extracts embedded clock information from data streams. Accordingly, testing system400may be integrated into a single integrated circuit die.

Second interpolator410provides the reference clock signal as described above. Testing state machine60is coupled to second interpolator410. In some embodiments, testing state machine60instructs second interpolator410to change the phase degree of the reference clock signal at101of method100. Such an arrangement may provide testing of interpolator10using existing circuitry to generate the multiple reference clock phase degrees.

FIG. 8is a block diagram of testing system500according to some embodiments. Testing system500includes interpolator10, flip-flop50, testing state machine60, and multiplexer510. Testing system500may operate to determine the non-linearity of interpolator10, using method100or any other suitable method.

Interpolator10, flip-flop50, testing state machine60may operate and be embodied as described above with respect toFIG. 2and method100. Multiplexer510receives two or more clock signals and provides one of the clock signals to flip-flop50as the reference clock signal. Multiplexer510includes input520by which testing state machine60may select the one of the two or more clock signals that will be provided as the reference clock. In this regard, testing state machine60may select a new clock signal at101of method100. Multiplexer510may be located on a same integrated circuit die as the other elements of system500.

FIG. 9is a block diagram of testing system600according to some embodiments. Testing system600includes interpolator10, flip-flop50, testing state machine60, serially-coupled buffers610, and multiplexer620. Testing system600may operate to determine the non-linearity of interpolator10, using method100or any other suitable method.

Again, interpolator10, flip-flop50, testing state machine60may operate and be embodied as described above with respect toFIG. 2and method100. Buffers610and multiplexer620may combine to provide a reference clock signal to flip-flop50. In some embodiments, buffers610and multiplexer620each receive reference clock signal X, and multiplexer620also receives an output signal from each of buffers610. The clock phase of a signal output by a particular buffer may differ from the clock phase of a signal output by each other buffer. In some embodiments, each of buffers610provides a substantially equal signal propagation delay. Therefore, increments between the different clock phases may be substantially equal.

Multiplexer620includes input630by which testing state machine60may select which of the received clock signals will be provided to flip-flop50as the reference clock. Testing state machine60may select a new clock signal at101of method100. Buffers610and multiplexer620may be located on a same integrated circuit die as the other elements of system600.

FIG. 10is a block diagram of system700according to some embodiments. System700may comprise a motherboard. System700includes integrated circuit710, which may comprise a microprocessor. Microprocessor710is coupled to memory720, which may comprise any type of memory for storing data, such as a Single Data Rate Random Access Memory, a Double Data Rate Random Access Memory, a fully buffered Dual In-line Memory Module, or a Programmable Read Only Memory.

Microprocessor710includes transceiver730having interpolators732and734. Transceiver730may provide serial I/O functions, including but not limited to direct memory access. Interpolators732and734of transceiver730may be in quadrature with one another. Testing unit740may be used to determine the non-linearity of interpolators732and734as described herein. Accordingly, testing unit740comprises flip-flop742and testing state machine744. Microprocessor710also includes core750for providing primary functions of microprocessor710.

The several embodiments described herein are solely for the purpose of illustration. Some embodiments may incorporate, in part or in whole, any currently or hereafter-known interpolators, flip-flops, state machines, and other elements. Therefore, persons in the art will recognize from this description that other embodiments may be practiced with various modifications and alterations.