Variable amplitude delay equalizer

A variable amplitude delay equalizer network comprising generally a 90.degree. hybrid matrix consisting of toroidal transformer and two capacitors and having an input, an output and two reference ports. A reactive network at the first reference port forms a network which allows input energy to be shifted in phase and returned to the hybrid, thus providing envelope delay correction. An amplitude corrective network at the second port permits adjustment of the amplitude response essentially independent of envelope delay adjustment.

BACKGROUND OF THE INVENTION 
This invention relates to an electronic network utilized to compensate for 
nonlinear phase distortion created by other networks and circuitry. Such 
nonlinear phase distortion is typically created by networks such as 
filters, amplifiers, amplitude equalizers, FM modulators, FM demodulators 
and other analog and digital broadband communications devices. 
Envelope delay distortion or group delay distortion has previously been 
corrected utilizing various networks such as different bridge T 
configurations derived from an allpass lattice structure. Reflective type 
equalizers, such as 90.degree. hybrids and 180.degree. hybrids have also 
been utilized. However, conventional equalizer networks have shared a 
common disadvantage: as the shape factor increases (greater envelope delay 
correction per unit of frequency bandwidth), the networks exhibit greater 
amplitude distortion due to the finite Q of the reactive elements used in 
implementation of the networks. Thus, while correcting for envelope delay 
distortion, a second distortion is introduced, which is amplitude 
distortion versus frequency. 
Methods for measuring envelope delay are disclosed in U.S. Pat. No. 
3,400,329 to Cannon together with amplitude and delay distortion 
correcting networks comprising cascaded frequency selective active 
corrective networks which separately correct a portion of the frequency 
band to be corrected. U.S. Pat. No. 4,258,340 to Ryu discloses an 
amplitude equalizer intended to have flat delay distortion characteristics 
comprising a pair of amplitude equalizers having complimentary, and thus 
cancelling, delay distortion characteristics. Such equalizers include 
delay circuits and/or phase shifters but do not teach or suggest 
correction of envelope delay distortion while avoiding amplitude 
distortion. 
U.S. Pat. No. 4,333,063 to Ryu et al. discloses another amplitude equalizer 
for use within a predetermined frequency band, which equalizer is intended 
to exhibit no delay distortion. It utilizes combinations of signal 
splitters, delay circuitry and polarity and gain adjusting means. 
Additionally, U.S. Pat. No. 4,352,190 to Hullwegen discloses an automatic 
equalizer for data transmission and suggests a delay equalizer which 
includes an output amplitude stabilizer utilizing active network elements. 
None of this art, however, or other art known to applicant discloses the 
simple and effective variable amplitude delay equalizer of the present 
invention. 
SUMMARY OF THE INVENTION 
The present invention corrects nonlinear phase distortion, also known as 
envelope delay distortion and normally referred to as 
Td=d.theta./d.omega., while maintaining a flat or corrective amplitude 
response. 
The circuit of the present invention comprises generally a 90.degree. 
hybrid matrix consisting of a toroidal transformer and two capacitors and 
having an input, an output and two reference ports, c and d. Reactive 
components at reference port c form a network which allows input energy to 
be shifted in phase and returned to the hybrid, thus forming an envelope 
delay corrective network. An amplitude corrective network comprising three 
resistors and a capacitor is connected to port d to permit adjustment of 
the amplitude response essentially independent of the envelope delay 
adjustment. 
The present invention will achieve at least five times the envelope delay 
correction as conventional approaches without introducing amplitude 
distortion and can provide simultaneous envelope delay correction and 
amplitude correction.

DETAILED DESCRIPTION OF THE DRAWINGS 
FIG. 1 shows the preferred embodiment of the present invention comprising a 
90.degree. hybrid matrix formed by a toroidal transformer 10 having 
connections a and c to a first winding 12 and connections b and d to a 
second winding 14. A capacitor 16 is connected between toroidal 
transformer 10 connections c and b, and a capacitor 18 is connected 
between transformer 10 connections a and d. The hybrid matrix formed by 
transformer 10 and capacitors 16 and 18 has an input 20 at connection a 
and an output 22 at connection b. Connections c and d serve as reference 
ports. 
A reactive network is connected to reference port c to allow energy from 
the input 20 to enter and return shifted in phase, thereby providing an 
envelope delay corrective network. The reference port c reactive network 
comprises a pair of capacitors 24 and 26 connected to reference port c, 
each of which connects in series to variable inductors 21 and 30, 
respectively, which inductors 21 and 30 connect to "ground" or a "common" 
connection 31. 
An amplitude corrective network, which provides for amplitude 
distortionless envelope delay equalization in accordance with the present 
invention, comprises 3 resistors, 32, 34 and 36 and one variable capacitor 
38. Variable resistor 36 is connected between transformer 10 connections a 
and b. Resistor 36 can be adjusted to vary the amplitude response, 
essentially independent of the delay adjustment achieved with the delay 
corrective network. Resistor 32 connects between reference port d and 
ground 31, and resistor 34 and variable capacitor 38 are in series between 
reference port d and ground 31. Centering of the amplitude peak or dip may 
be adjusted by variable capacitor 38. 
The transformer 10 should be one with a low insertion loss, and at 
appropriate frequencies, such as in a network for use at 70 MHz, may be a 
bifilar wound toroid. 
As will be appreciated by one skilled in the art, component values for the 
circuit of FIG. 1 may be chosen in accordance with conventional network 
design techniques for the desired frequency and other operating 
parameters. 
FIG. 2 is a graphic presentation of the envelope delay correction 40 which 
may be achieved by the present invention. The amplitude response 
adjustable by resistor 36 is indicated by broken line 42, and centering of 
the amplitude peak adjustable by capacitor 38 is indicated by broken line 
44. 
The foregoing description of the present invention is for purposes of 
explanation and illustration. The invention is not intended to be limited 
to the details of the embodiment or components described, but includes 
numerous modifications and changes, which will be apparent to those 
skilled in the relevant art, while still falling within the scope and 
spirit of the preceding description.