Processor having Switch Instruction Circuit

In one implementation a processor has an instruction fetch circuit fetching instructions, the instruction fetch circuit having an input and an output and a decode circuit to decode the fetched instructions, the decode circuit having a first and second input, and an output, wherein the decode circuit first input is coupled to the instruction fetch circuit output receiving the fetched instructions, and an execution circuit executing the decoded fetched instructions, the execution circuit having an input coupled to the decode circuit output to receive the decoded fetched instructions, and a switch instruction circuit (SIC) to detect and execute switch instructions of the fetched instructions, the SIC having an input and an output, wherein the SIC input is coupled to the instruction fetch circuit output to receive the fetched instructions, wherein the SIC output is coupled to the decode circuit second input and the instruction fetch circuit input.

BACKGROUND

Processors generally work on machine code instructions, also known as opcodes, which are difficult to decipher. The machine code instructions reflect what the respective processor is electrically arranged to implement. One level above machine code is assembler code, which is basically a more readable version of the opcode. A machine code instruction, and the respective assembler code instruction, may be called a processor instruction, in that the instruction is handled “as is” by the processor. Higher level programming languages exist, with associated respective compilers, which convert instructions in the higher level language into a string of machine code instructions for the respective processor. Higher level programming languages often have “switch” instructions, which is a type of selection control mechanism used to allow the value of a variable or expression to change the control flow of program execution via search and map. For example, C++ and C# have the “switch” instruction and Visual Basic has the “select” instruction. Compilers reduce these to machine-code instructions that perform a series of conditional jumps to finally arrive at the address of the instructions for each case identified by the switch statement. The compiler can be very clever and creative in the structure of this series of jumps that reduce the number of jump instructions that need to be executed by the processor. However, for some specialized processors, a compiler may not yet exist. Programming is then done via assembly language that can be easily converted into the machine code. But the writing of a switch, or switch-like, instruction in assembly language for present processors is cumbersome, awkward to use, difficult to optimize, and yields difficult to read assembler code that is hard to visually ensure is correct.

There is a need for a switch instruction in assembler code, with a respective processor arranged to handle the associated opcode.

This presents a technical problem for which a technical solution is needed using a technical means.

BRIEF SUMMARY

In one implementation a processor has an instruction fetch circuit fetching instructions, the instruction fetch circuit having an input and an output and a decode circuit to decode the fetched instructions, the decode circuit having a first and second input, and an output, wherein the decode circuit first input is coupled to the instruction fetch circuit output receiving the fetched instructions, and an execution circuit executing the decoded fetched instructions, the execution circuit having an input coupled to the decode circuit output to receive the decoded fetched instructions, and a switch instruction circuit (SIC) to detect and execute switch instructions of the fetched instructions, the SIC having an input and an output, wherein the SIC input is coupled to the instruction fetch circuit output to receive the fetched instructions, wherein the SIC output is coupled to the decode circuit second input and the instruction fetch circuit input.

A method is disclosed that includes in one implementation a processor fetching an opcode instruction through an input of the processor and then determining whether the fetched opcode instruction is a switch instruction, and when the opcode instruction is determined to be a switch instruction performs the switch instruction at a switch instruction circuit of the processor, and when the opcode instruction is determined not to be a switch instruction then decoding the opcode instruction to obtain a decoded instruction and performing the decoded instruction at an execution circuit of the processor.

DETAILED DESCRIPTION

A processor switch instruction and a processor responsive to such a processor switch instruction is disclosed.

For illustrative purposes only the discussion below will limit the number of cases in the processor switch instruction to a small number to illustrate the techniques disclosed. The methods and techniques disclosed are not so limited.

The processor switch instruction disclosed has, as an example, the following form:

switch instruction (some_variable) {case 0: <code for when some_variable is 0>case 1: <code for when some_variable is 1>case 2: <code for when some_variable is 2>default: <code for when some_variable is 3 or more>}
[The code illustrated immediately above from the beginning of the “switch instruction (some_variable) {” to the ending “}” is being denoted as Example Code 1 for purposes of discussion. Other notations will simply refer to “Example Code N” where N is replaced by a positive integer greater than 1.]

Example Code 1 above illustrates a 4 entry processor switch instruction having switch instruction table entry points for case 0:, case 1:, case 2:, and default:. The size of the switch instruction table is from the 1stinstruction at case 0: to the last instruction of the default:.

The technique disclosed addresses similar constructs by a processor switch instruction, which may be simply called a SWITCH Instruction (aka switch instruction), that jumps to the code indicated by the value of some variable (denoted as some_variable). This is made possible by a predetermined allocated code-space for each of the case statements. If this predetermined allocated code-space is insufficient for the case, a jump (JUMP) or subroutine call (CALL) instruction as part of the switch instruction table can handle the excess code. The SWITCH instruction automatically handles each case having a first instruction of CALL in the switch instruction table by returning to the instruction that follows the SWITCH instruction. This yields improved readability in the assembly language. The use of a predetermined allocated code-space yields execution that ensures that one case statement does not run into the next and cause some other instruction to be executed.

In one illustrative implementation, the actions required by each switch instruction case can be reduced to either a JUMP or CALL instruction to jump to the instructions that implements the action.

In one illustrative implementation the SWITCH instruction is implemented as a 16-bit instruction with fields for: opcode, register, and size. The opcode (which may be 8 bits) identifies the SWITCH instruction. The register (which may be 4 bits) identifies a register that contains the value that determines which case in the switch instruction table is to be executed. The size (which may be 4 bits) identifies the size of the switch instruction table. The switch instruction table size is the combined size of all of the predetermined allocated code-spaces. The field “size” identifies the largest allowed value in the register, which value in the register may be considered an index to the switch instruction table. The indices to the switch instruction table are zero-based (i.e. starting the count at 0, rather than one-based starting the count at 1), 0-15 in the case of size being 4 bits. The number of cases is therefore the value of size+1.

In one illustrative implementation the predetermined allocated code-space for each of the case statements is 4 bytes, which is the size of the JUMP and CALL instructions for the particular processor of the example. In an example where the switch instruction table comprise only JUMP or CALL instructions, then the SWITCH instruction will jump to the appropriate JUMP or CALL. It is not a limitation to require only JUMP or CALL instructions in each of the cases, but a simplification that was made for sake of illustration.

In one illustrative implementation of a processor102, an instruction fetch circuit104, a decode circuit106and a switch instruction circuit110of the processor102operate thusly, and with reference toFIG.1.

When the instruction fetch circuit104fetches an instruction, instruction fetch circuit104outputs the fetched instruction to decode circuit106and to switch instruction circuit110. Switch instruction circuit110is illustrated as a separate circuit from both instruction fetch circuit104and decode circuit106, however this is not meant to be limiting in any way. In one example, switch instruction circuit110is part of decode circuit106. In one example, switch instruction circuit110may be at least partially integrated with instruction fetch circuit104. Switch instruction circuit may also be partially integrated within execution circuit108. Instruction fetch circuit is illustrated as having a single output coupled to both decode circuit106and switch instruction circuit110, however this is not meant to be limiting in any way. In another example, multiple outputs are provided for fetch instruction circuit104, fetch instruction circuit104identifies a SWITCH instruction and outputs the SWITCH instruction to switch instruction circuit110. The switch instruction circuit110identifies a SWITCH instruction output by instruction fetch circuit104and operates thusly:

1. Switch instruction circuit110determines the address of the first instruction following the switch instruction table of the SWITCH instruction. It determines this from the instruction address of the SWITCH instruction, the length of the SWITCH instruction (2 bytes), and the number of bytes or words in the switch table, as indicated in the switch instruction, which number of bytes or words is the number of cases it has multiplied by the size pre-allocated to each case, 4 bytes in this example. The number of cases in the switch table is in the size field of the SWITCH instruction plus 1, since a size of 0 means 1 case. In other words, the address of the first instruction following the switch instruction table=current address+size of switch instruction+ (size*predetermined allocated code-space for each of the case statements).

2. Switch instruction circuit110determines the instruction address of the switch instruction table entry to execute. It determines this by adding an offset to the current SWITCH instruction address. The offset is calculated from the value in the register specified by SWITCH instruction. The calculation is: instruction address of SWITCH instruction+size of SWITCH instruction (2 bytes)+ (pre-allocated size (4 bytes)*value in register). However, if value in the register specified by the SWITCH instruction exceeds the size of the table, the size of the table is used instead which means the final table entry is the execution point when the register equals or exceeds the size of the table.

1. Instruction fetch circuit104discards any prefetched instructions to ensure they do not execute. (See further explanation below at Nota bene.)

2. The instruction at the address given by the switch instruction circuit110, i.e. instruction at the address of the switch instruction table entry to execute, is fetched.

3. The fetched instruction may be executed by instruction fetch circuit104instead of the decode circuit106. Since this is a specialized case, the instruction fetch circuit104can execute the instruction faster than handing it off to the decode circuit106and waiting. This execution is simplified when the instruction is limited to, for example, a JUMP or CALL, where instruction fetch circuit104already has most of the necessary circuits to carry out this instruction, and thus addition of certain circuitry enables instruction fetch circuit104to execute the fetched instruction. However, the invention is not so limited and for implementations that allow more complex operations in the switch instruction table, it may be preferred to allow the execution circuit108to execute the instruction or instruction sequence.

4. If the instruction is not a JUMP or CALL or any other instruction that a particular implementation does not support within a SWITCH instruction, a processor fault is declared and program execution of the switch instruction terminates.

5. The address specified by the fetched JUMP or CALL is used by instruction fetch circuit104to retrieve the instruction pointed to by the JUMP or CALL.

6. If the instruction is a JUMP, instruction fetch circuit104passes the retrieved target of the JUMP to decode circuit106for decoding and transfer to execution circuit108for execution, and continues fetching instructions as per normal.

7. If the instruction is a CALL, the same action as a JUMP is performed however, in addition, the address of the first instruction following the switch instruction table (received from decode circuit106) is pushed onto a subroutine return stack by instruction fetch circuit104. This ensures that when the subroutine completes, the subroutine will return to the first instruction following the switch instruction table instead of the instruction that follows the CALL.

Nota bene: Above, instruction fetch circuit104executes a switch instruction operation as follows: 1. It discards any prefetched instructions to ensure they do not execute.” Please note that one of skill in the art is aware that modern processors predictively fetch instructions before it's known whether they should execute or not. If it's determined at a later point they should not execute, they are discarded from the queue of instructions to be executed. The techniques disclosed herein adds a new case of this discard operation. Furthermore, modern processors also speculatively execute instructions before it's known whether they should execute or not. In this case the processor also includes a sequence of instructions to undo any processor state that the speculatively executed instructions have modified. This sequence of instructions is enacted when the processor has determined the speculatively executed instructions should not have executed and need to be discarded and any modified state undone. The techniques disclosed herein adds a new case of this discard operation. That is, one of skill in the art is aware that many modern processors for the sake of speedup do speculative processing, go down instruction paths that later will be determined to be wrong, and this is handled by discarding or tossing results later to be determined to be incorrect in the originally executing instruction stream. This is called “prefetch discard” or “discarding”, or “discarding instructions” or similar terms.

For illustrative purposes what follows is a comparison between the technique presented and a traditional SWITCH statement such as the SWITCH statement defined by the C programming language for conventional processors, which has been reduced to the assembly code by the C compiler.

SWITCH Instruction Example

Example Code 2

Without SWITCH Instruction, Example Assembly Code

Example Code 3

This Example Code 3 is done via a binary search, which is logarithmically faster than a linear search.

For the 2 examples illustrated above [Example Code 2] and [Example Code 3] if we make these assumptions: for all cases that the JUMPs and CALLs are unpredicted branches and require 3 cycles to complete, and CMP requires 3 cycles to complete due to pipeline register access cycles then we get this type of performance improvement.

The SWITCH instruction is not only more readable code, it is much smaller code, far simpler to write, and substantially faster.

In one implementation, for example, the size of the switch instruction table for this code:

Example Code 4

is largely the number of lines between the SWITCH instruction and endswitch.

In the following illustrative example the hex addresses are just for illustration.

Predetermined allocated code-space being for example:

address0x1000 <code for when some_variable is 0>0x2000 <code for when some_variable is 1>0x3000 <code for when some_variable is 2>0x4000 <code for when some_variable is 3 or more>

Example Code 5

Example Code 6

Here the hex addresses shown (0x1000, 0x2000, 0x3000, 0x4000) are the instruction addresses of the code shown to the left of the addresses. These addresses are generated by an assembler when assembling the SWITCH instruction.

In the above pseudo code “SWITCH instruction (some_variable)” the term some_variable was used to indicate the case statement that was to be executed. At the machine code level as indicated earlier the instruction is opcode, register, size. In the examples below we use “[reg]” to indicate the content of the register called reg. For example, in one implementation, reg may be r0, r1, . . . , r15 or k0, k1, . . . , k15.

Likewise, the addresses following a JUMP or CALL may also be generated by an assembler and the code itself may use symbolic names. For example, the code may be:

SWITCH instruction [reg]JUMP abcCALL defJUMP ghiJUMP jklENDSWITCH...@abc // The first JUMP will jump to the code that follows this label - the assembler willresolve the address of the code at this location...@ghi...@jkl...subroutine def // The CALL will execute the subroutine contained herein...Endsubroutine

Example Code 7

In this example the SWITCH instruction only refers to a register [reg] and does not refer to a size. In this example, when written in assembly language, the assembler can determine the “size” value itself and doesn't need the programmer to specify it, and the assembler provides the size for the processor switch instruction.

Note that in [Example Code 6] a Call will return to 0x0105, while a Jump does not as it changes the instruction stream. That is, a CALL returns but JUMP does not return, as JUMP passes execution control to some other address and the instructions from that address onward are executed. But a CALL has a RETURN instruction that returns execution to, in the case of this implementation, the address of the instruction that follows the ENDSWITCH (as seen in [Example Code 7]).

Illustrated below is an example of the handling of nested CALLs.

CALLs are often nested. If you CALL a subroutine from within the SWITCH instruction, the RETURN for that subroutine will return to the instruction that follows the SWITCH instruction. If a subroutine called from within the SWITCH instruction does a CALL to something else, the RETURN in that something else returns to the instruction that follows the corresponding CALL. The RETURN in the subroutine called from within the SWITCH instruction still returns to the instruction following the ENDSWITCH—it is therefore not affected by nested CALLS.

Furthermore, the nested CALLs may have SWITCH instructions. For example

SWITCH Instruction [reg]CALL abc...ENDSWITCH// *1: this is where the RETURN from subroutine abc will return tosubroutine abcSWITCH instruction [reg]CALL def...ENDSWITCH// *2: this is where the RETURN from subroutine def will return toRETURN // this will return to *1endsubroutinesubroutine defSWITCH instruction [reg]CALL def...ENDSWITCHRETURN // this will return to *2Endsubroutine

Example Code 8

In some of the code illustrations above there is an ENDSWITCH and in others there is not. Rather than pre-specifying the size to figure out the return address for a CALL instruction, which is one past the end of the predetermined allocated code-spaces, the assembler can figure out the return address for a CALL instruction if ENDSWITCH is used. That is, size can be determined by the assembler, which makes it easier for a programmer, however it means the assembler may need the ENDSWITCH so it can work out the size or some similar mechanism that heralds the end of the switch block. This ENDSWITCH indicator is used by the assembler and need not generate any machine code.

In some implementations, the SWITCH instruction case range may be limited. For example, if the case range is 0 to 15, that is 16 cases, then if more cases are needed in one example then multiple SWITCH instruction instances may be provided, which the assembler can handle. For example, if the need is for a 0-63 case range, that is, 64 cases then the following SWITCH instruction illustrative machine instructions cover that range: SWITCH00-15 instruction, SWITCH16-31 instruction, SWITCH32-47 instruction, SWITCH48-63 instruction. Thus multiple processor switch instructions instances may be provided to handle a larger range than the range of a single switch instruction.

In such an example, when the assembler encounters a SWITCH instruction, it may count how many cases are in it, and it may then generate the appropriate machine code for the SWITCH instruction accordingly. In the case of 18 cases, the assembler will generate machine code for the respective instance of SWITCH instructions, i.e. a SWITCH16-31 instruction with the 4-bit size set to 2. SWITCH16-31 instruction means the number of cases determined by the assembler is between 16 and 31, in this case 18. But there are 18 cases that can be executed, depending on the value of the register (as noted above denoted as [reg]).

The 4-bit size indicates if the table size is x+4-bit size+1. The +1 is because a 4-bit size of 0 means 1 entry. The value of x is determined from the machine code. The machine code for SWITCH00-15 instruction means x is 0, the machine code for SWITCH16-31 instruction means x is 16, the machine code for SWITCH32-47 instruction means x is 32, and the machine code for SWITCH48-63 instruction means x is 48.

When, for example, the assembler encounters the SWITCH instruction and the assembler determines the number of switch cases is in the range 16 to 31 and it's specifically 16 plus 4-bit size. If 4-bit size is 2, for example, the SWITCH16-31 instruction is specifying a switch table size of 16+2=18. Therefore, value 0-17 in the register will execute their corresponding case and values greater than 17 will go to case 17.

That is, the SWITCH16-31 machine instruction handles cases when the switch table has at least 16 cases but no more than 31. If the register specified by the switch instruction has a value 0-31, it will cause the corresponding case, 0, 1, 2, . . . or 31, to be executed next. If the register value exceeds 31, case 31 will be executed.

If the switch instruction table had 40 cases, then the assembler generates a SWITCH32-48 instruction with a 4-bit size equal to 8, since 32+8 is 40. The register values 0-39 result in the corresponding case 0, 1, 2, . . . , 39 to be executed and all other register values result in case 39 being executed.

Thus with a 4-bit size, a single SWITCH instruction can support a table size up to 16 (0-15). But a different processor SWITCH instruction can support a table size of up to 32 and a yet different processor SWITCH instruction can support a table size of up to 48, without limitation.

What has been illustrated is a 4 bit value for size, however, the implementations are not so limited and using multiple instructions and registers it is possible to have a size of any value.

FIG.1illustrates, generally at100, a block diagram for one example of the techniques disclosed, and operates as described above. At102is a processor which has within it an Instruction Fetch Circuit104, a Decode Circuit106a Switch Instruction Circuit (SIC)110, and an Execution Circuit108. Instruction Fetch Circuit104is in communication with Decode Circuit106and SIC110. SIC110is in communication with Decode Circuit106, and Decode Circuit106is in communication with Execution Circuit108. Particularly, Decode Circuit106and SIC110are responsive to respective outputs of Instruction Fetch Circuit104, and Decode Circuit106and Instruction Fetch Circuit104are responsive to respective outputs of SIC110. Execution circuit108is responsive to an output of decode circuit106.

In one example, instruction fetch circuit (104) is to fetch instructions, the instruction fetch circuit (104) having an input and an output. The instruction fetch circuit104fetches instructions from outside the processor102, from for example, memory. This connection to memory outside the processor102is not shown inFIG.1so as not to obscure the implementation. Once the instruction fetch circuit104has fetched an instruction it outputs this on the instruction fetch circuit104output which is connected to both the decode circuit106and the switch instruction circuit (SIC)110. The instruction fetch circuit (104) input (not the hidden one to memory) is connected to the switch instruction circuit (SIC)110output.

The processor102also has a decode circuit106to decode the fetched instructions it receives from the instruction fetch circuit104, the decode circuit having a first input which is coupled to the instruction fetch circuit104output, a second input which is coupled to the switch instruction circuit (SIC)110output to receive the fetched instructions, and an output which is coupled to the execution circuit108.

The processor102also has an execution circuit108to execute the decoded fetched instructions (from instruction fetch circuit104as processed by decode circuit106), the execution circuit108having an input to receive the decode circuit106output, wherein the execution circuit108input is coupled to the decode circuit106output to receive the decoded fetched instructions (from instruction fetch circuit104as processed by decode circuit106).

The switch instruction circuit (SIC)110is to detect and execute switch instructions of the fetched instructions, the SIC110having an input and an output, wherein the SIC110input is coupled to the instruction fetch circuit104output to receive the fetched instructions, wherein the SIC110output is coupled to the decode circuit106second input and the instruction fetch circuit104input.

FIG.2illustrates, generally at200, details of an example SIC202. SIC202has within it a Switch Instruction Check Circuit (SICC)206, a Switch First Address Determination Circuit (SFADC)208, and a Switch Address Execute Determination Circuit (SAEDC)210. Instruction Fetch Circuit204, which may be an example of instruction fetch circuit104, is in communication with SICC206, i.e. SICC206is responsive to an output of instruction fetch circuit204. SICC206is in communication with Switch First Address Determination Circuit (SFADC)208and Switch Address Execute Determination Circuit (SAEDC)210, i.e. SFADC208and SAEDC210are responsive to respective outputs of SICC206.

SICC206is a circuit to check for a SWITCH instruction output by instruction fetch circuit204, SFADC208is a circuit to determine a first address of a SWITCH instruction and SAEDC210is a circuit to determine an execution address of a SWITCH instruction.

In one example, the SIC202which may be an example of SIC110, includes the switch instruction check circuit (SICC)206having an input connected to the output of instruction fetch circuit204which may be an example of instruction fetch circuit104and an output connected to the input of switch first address determination circuit (SFADC)208and to the input of switch address execute determination circuit SAEDC210, the SICC206to determine when the fetched instruction as received from the instruction fetch circuit204is the SWITCH instruction, the SICC206input coupled to the instruction fetch circuit204output. When the SICC206determines the fetched instruction as received from the instruction fetch circuit204is the SWITCH instruction, then in response the SICC206places the SWITCH instruction on the SICC206output. The SIC202also has switch first address determination circuit (SFADC)208having an input which is connected to the output of the SICC206, the SFADC208to determine a first instruction address following a switch table, the SFADC208input coupled to the SICC206output. The SIC202also has a switch address execute determination circuit (SAEDC)210having an input which is connected to the SICC206output, the SAEDC210to determine an instruction address of an entry in the switch table to execute, the SAEDC210input coupled to the SICC206output. SIC202checks to see if an instruction received from the instruction fetch circuit204is a SWITCH instruction at SICC206and if it is a switch instruction then at SFADC208a switch first address is determined, and at SAEDC210a switch address to execute is determined.

FIG.3illustrates, generally at300, details of an example SIC302. SIC302has within it a Switch Address Execute Determination Circuit (SAEDC)304, a Switch Address Size Check Circuit (SASCC)306and a Switch Change Address Circuit (SCAC)308. SAEDC304is in communication with SASCC306, which SASCC306is responsive to an output of SAEDC304. SASCC306is in communication with SCAC308, which SCAC308is responsive to an output of SASCC306.

SAEDC304is a circuit to determine an execution address of a switch instruction, SASCC306is a circuit to check the switch address size and SCAC308is a circuit to change the switch address.

In one example, SIC302which may be an example of switch instruction circuit SIC110includes: switch address size check circuit (SASCC)306having an input and an output, the SASCC306input coupled to the SAEDC304output, the SASCC306to determine if the instruction address of the entry in the switch table to execute exceeds a size of the switch table, the SASCC306input coupled to an output of the SAEDC304. SIC302includes switch change address circuit (SCAC)308having an input which is coupled to the SASCC306output, the SCAC308to change the instruction address of the entry in the switch table to execute that exceeds the size of the switch table to a last case address in the switch table, the SCAC308input coupled to the SASCC306output. The SASCC306checks the switch address size and SCAC308changes that address if needed.

FIG.4illustrates, generally at400, details of an example SIC402. SIC402has within it a Switch Change Address Circuit (SCAC)404having an output that goes to an example Instruction Fetch Circuit410which has within it a Switch Discard Instruction(s) Circuit (SDIC)406and a Switch Instruction Fetch Circuit (SIFC)408. SCAC404is in communication with SDIC406which SDIC406is responsive to an output of SCAC404. SDIC406is in communication with SIFC408, which is responsive to an output of SDIC406.

SCAC404is a circuit to change the switch address, SDIC406is a circuit to discard switch instruction(s) and SIFC408is a circuit to fetch a switch instruction. In some examples, as indicated above, SDIC406and SIFC408may be integrated as part of instruction fetch circuit104. In some examples one or more of SDIC406and SIFC408may be integrated as part of SIC402.

In one example, the instruction fetch circuit104ofFIG.1is to pre-fetch instructions and comprises switch discard instruction(s) circuit (SDIC)406having an input which is connected to the SCAC404output, and an output which is connected to the SIFC408input, the SDIC406to discard any pre-fetched instructions, the SDIC406input coupled to the SCAC404output; and the SIC402, which may be an example of SIC110, includes the SCAC404. . . . Switch instruction fetch circuit (SIFC)408has an input which is connected to the SDIC406output, the SIFC408to fetch a switch target instruction at the instruction address of the entry in the switch table entry to execute, the SIFC408input coupled to the SIDC406output. The SDIC406discards switch instructions if needed, and SIFC408fetches a switch instruction. SIFC408may fetch the plurality of instructions machine code lines that form the switch instruction.

FIG.5illustrates, generally at500, details of an example SIC502. SIC502, which may be an example of SIC510, has within it a Switch Instruction Inspection Circuit (SIIC)506and a Switch Instruction Error Fault Circuit (SIEFC)508. SIIC506receives from an example Instruction Fetch Circuit510which has within it a Switch Instruction Fetch Circuit (SIFC)504, which may be an example of SIFC408and is in communication with SIIC506, which SIIC506is responsive to an output of SIFC504. SIIC506is in communication with SIEFC508, which SIEFC is responsive to an output of SIIC506.

SIFC504is a circuit to fetch a switch instruction, SIIC506is a circuit to inspect a switch instruction and SIEFC508is a circuit to detect an error fault in a switch instruction. In some examples, as indicated above, SIFC504may be integrated as part of instruction fetch circuit104.

In one example, the SIC502includes: SIIC506having an input which is connected to the SIFC output, and an error output which is connected to the SIEFC508input, the SIIC506to determine when the instruction at the instruction address of the entry in the switch table to execute is not a jump (JUMP instruction) and not a call (CALL instruction) and generate an error signal on the error output which is connected to the SIEFC508input when it is determined that the instruction at the instruction address of the entry in the switch table to execute is not the jump (JUMP instruction) and not the call (CALL instruction). The SIEFC508has an input which is connected to the SIIC506error output, the SIEFC508to halt execution of the fetched switch target instruction when the error signal is received on the input from the SIIC506error output, the SIEFC508input coupled to the SIIC506error output. The SIIC506receives on its input from SIFC504an switch instruction and inspects it. If the switch instruction is found to be in error then SIIC506communicates an error condition via its error output (the only output shown inFIG.5) to SIEFC508. The above is described in an example wherein only a JUMP or a CALL instruction is supported by the SWITCH instruction, however this is not meant to be limiting in any way. In another example, other instructions may be supported, and in such an example, SIIC506to determine when the instruction at the instruction address of the entry in the switch table to execute is not a supported instruction, and generates an error signal on the error output which is connected to the SIEFC508input when it is determined that the instruction at the instruction address of the entry in the switch table to execute is not a supported instruction.

FIG.6illustrates, generally at600, details of an example SIC602. SIC602, which may be an example of SIC110, has within it a Switch Instruction Inspection Circuit (SIIC)604, a Switch Instruction Determination Circuit (SIDC)606, a Switch Instruction Return Stack Circuit (SIRSC)608and a Switch First Address Determination Circuit (SFADC)610. SIIC604is in communication with SIDC606, which SIDC606is responsive to an output of SIIC664. SIDC606is in communication SIRSC608, which SIRSC608is responsive to an output of SIDC606. SFADC610is in communication with SIRSC608, which SIRSC608is responsive to an output of SFADC610.

SIIC604is a circuit to inspect a switch instruction, SIDC606is a circuit to determine a switch instruction, SIRSC608is a circuit for the switch instruction return stack and SFADC610is a circuit to determine the switch instruction first address.

In one example, the SIC602includes: the SIIC604having an output which is connected to the SIDC606input, the SIIC604to determine when the instruction at the instruction address of the entry in the switch table to execute is a jump (JUMP instruction) or a call (CALL instruction) and place the switch target instruction on the output of the SIIC604when it is determined that the instruction at the instruction address of the entry in the switch table to execute is the jump (JUMP instruction) or the call (CALL instruction). The SFADC610has an output which is connected to the second input of the SIRSC and is to place on the output of SFADC610the first instruction address following the switch table.

The SIDC606has an input which is connected to the SIIC604output, and an output which is connected to the first input of the SIRSC608, the SIDC606input coupled to the SIIC604output, the SIDC606to determine if the fetched switch target instruction is the CALL instruction and if the fetched switch target instruction is the CALL instruction place the CALL instruction on the output of the SIDC606which is connected to the first input of SIRSC608.

The SIRSC608has a first input which is connected to the output of the SIDC606, and a second input which is connected to the second input of the SIRSC608, the first input coupled to the SIDC606output, the second input coupled to the SFADC610output, the SIRSC608to put on a return stack the first instruction address following the switch table when the output of the SIDC606is the CALL instruction. The SFADC610determines the first instruction address following the switch table and presents it to SIRSC608which places it on a return stack only if SIDC606determines the fetched switch target instruction is the CALL instruction.

FIG.7illustrates, generally at700, details of an example SIC702and communications with an Instruction Fetch Circuit708, and a Decode Circuit710. SIC702may be an example of SIC110. Within the SIC702is Switch Instruction Determination Circuit (SIDC)704in communication with Switch Instruction Target Determination Circuit (SITDC)706, which SITDC706is responsive to an output of SIDC704. SITDC706communicates outside of the SIC702with the Instruction Fetch Circuit708and the Decode Circuit710, which instruction fetch circuit708and decode circuit710are responsive to respective outputs of SITDC706.

SIDC704is a circuit to determine a switch instruction, SITDC706is a circuit to determine a switch instruction target and Instruction Fetch Circuit708is a circuit to fetch an instruction. Instruction fetch circuit708may be an example of instruction fetch circuit104. Decode circuit710may be an example of decode circuit106. Decode Circuit710is a circuit to decode the determined target on the SITDC706output.

In one example, the SIC702includes: the SIDC704having a second output which is connected to the SITDC706input, the SIDC704second output set to the fetched switch target instruction; the SITDC706has an input which is coupled to the SIDC second output, and an output which is connected to the Instruction Fetch Circuit708and the Decode Circuit710, the SITDC706input coupled to the SIDC704second output, the SITDC706to determine a target of the JUMP instruction or the CALL instruction and place the determined target on the SITDC706output; and wherein the SITDC706output is coupled to the instruction fetch circuit708input, and is coupled to the decode circuit710second input.

The SITDC706output goes to the instruction fetch circuit708, to fetch the determined target on the SITDC706output and as indicated above, goes to the decode circuit710, and thus can affect their operation.

FIG.8illustrates, generally at800, details of an example Switch Instruction Circuit (SIC)802and communications with a Switch Instruction Return Stack Circuit (SIRSC)808. SIC802may be an example of SIC110. Within the SIC802is a Switch Instruction Inspection Circuit (SIIC)804, a Switch Instruction Determination Circuit (SIDC)806and a Switch First Address Determination Circuit (SFADC)810. SIIC804is in communication with SIDC806, which SIDC806is responsive to an output of SIIC804. SIRSC808is responsive to an output of SIDC806and to an output of SFADC810.

SIIC804is a circuit to inspect a switch instruction, SIDC806is a circuit to determine a switch instruction, SFADC810is a circuit to determine the switch instruction first address and SIRSC808is a circuit for a return stack of the switch instruction.

In one example, the SIRSC808is a same stack used by processor102when not executing the switch instruction, i.e. SIRSC808is used by the processor when not executing a switch instruction, that is, for example, the processor's stack for regular operations. In this example it is shown that the switch instruction can use the processor's stack used for regular operations versus in another example is shown a dedicated switch instruction stack distinct from the processor's stack used for regular operations.

FIG.9illustrates, generally at900, a flow chart beginning with a fetch. At902an opcode instruction is fetched through an input of a processor, then proceed to904. At904, it is determined at the processor whether the fetched opcode instruction is a switch instruction, and when the opcode instruction is determined to be a switch instruction the switch instruction is performed at a switch instruction circuit of the processor, then proceed to906. At906, when the opcode instruction is determined not to be a switch instruction, the fetched opcode instruction is decoded to obtain a decoded instruction and the decoded instruction is performed at an execution circuit of the processor. This may generate an output at an output of the processor.

In one example, the flow chart beginning with a fetch may be an example of a method which method includes: fetching an opcode instruction through an input of a processor, for example, as shown inFIG.1the instruction fetch circuit104fetches instructions from outside the processor102, from for example, memory. This connection to memory outside the processor102is not shown inFIG.1so as not to obscure the implementation. The method may include determining at the processor, for exampleFIG.1at102, whether the fetched opcode instruction is a switch instruction, for exampleFIG.2at SICC206, and when the opcode instruction is determined to be a switch instruction performing the switch instruction at a switch instruction circuit, for exampleFIG.1at SIC110of the processor, for exampleFIG.1at102. When the opcode instruction is determined not to be the switch instruction, the method may include decoding the opcode instruction to obtain a decoded instruction, for exampleFIG.1at106, and performing the decoded instruction at an execution circuit, for exampleFIG.1at108of the processor102. This may generate an output at an output of the processor.

FIG.10illustrates, generally at1000, wherein the switch instruction circuit, for example SIC110, executes a first instruction located in a switch table at a switch table entry address1002, as part of the method, for example as fetched by SIFC408inFIG.4.

FIG.11illustrates, generally at1100, wherein the switch instruction includes a size for one or more fixed sized instruction blocks in a switch table, and a pointer address to a first instruction in the one or more fixed sized instruction blocks in the switch table to execute1102.

In one example, the method includes wherein the switch instruction, for example as fetched by Instruction Fetch Circuit104inFIG.1, includes a size for one or more fixed sized instruction blocks, for example as checked by SASCC306inFIG.3, in a switch table, and a pointer address to a first instruction in the one or more fixed sized instruction blocks in the switch table to execute, for example as determined by SAEDC210inFIG.2.

FIG.12illustrates, generally at1200, when the pointer address to the first instruction in the one or more fixed sized instruction blocks in the switch table to execute exceeds an address of a combined sizes of the one or more fixed sized instruction blocks in the switch table the pointer address of the first instruction to execute is adjusted to an address of a last of the one or more fixed sized instruction blocks in the switch table1202.

In one example, the method thus included when the pointer address to the first instruction in the one or more fixed sized instruction blocks in the switch table to execute exceeds an address of a combined sizes of the one or more fixed sized instruction blocks in the switch table, for example as checked at SASCC306inFIG.3, the pointer address of the first instruction to execute is adjusted, for example as changed at SCAC308inFIG.3, to an address of a last of the one or more fixed sized instruction blocks in the switch table.

FIG.13illustrates, generally at1300, when the one or more fixed sized instruction blocks that is called has a first instruction of a jump (JUMP instruction) nothing is pushed onto a stack as a result of the first instruction being the JUMP instruction1302.

In one example, the method thus includes wherein when the one or more fixed sized instruction blocks that is called has a first instruction of a jump (JUMP instruction), as determined by SIDC606inFIG.6, nothing is pushed onto a stack as a result of the first instruction being the JUMP instruction. For example, inFIG.6SFADC610determines the first instruction address following the switch table and presents it to SIRSC608which places it on a return stack only if SIDC606determines the fetched switch target instruction is the CALL instruction, so when, for example, the instruction is a JUMP instruction, which is not a CALL instruction, nothing is pushed onto the stack as represented by, for example, SIRSC608inFIG.6.

FIG.14illustrates, generally at1400, when the one or more fixed sized instruction blocks that is called has a first instruction of a call (CALL instruction) an address past the end of a combined sizes of the one or more fixed sized instruction blocks is pushed onto a stack regardless of which of the one or more fixed sized instruction blocks are called as a result of the first instruction being the CALL instruction1402.

In one example, the method thus includes wherein when the one or more fixed sized instruction blocks that is called has a first instruction of a call (CALL instruction), for example as determined by SIDC606inFIG.6, an address past the end of a combined sizes of the one or more fixed sized instruction blocks, for example as determined by SFADC610inFIG.6, is pushed onto a stack regardless of which of the one or more fixed sized instruction blocks are called as a result of the first instruction being the CALL instruction. For example, inFIG.6, SFADC610determines the first instruction address following the switch table and presents it to SIRSC608which places it on a return stack if SIDC606determines the fetched switch target instruction is the CALL instruction.

FIG.15illustrates, generally at1500, wherein a circuit calculates an instruction address of a first instruction following the switch table1502.

In one example, the method thus includes, wherein a circuit, for example SFADC810inFIG.8, calculates an instruction address of a first instruction following the switch table.

FIG.16illustrates, generally at1600, wherein the switch instruction provides an instruction address of a switch table entry to execute1602.

In one example, the method thus includes, wherein the switch instruction provides an instruction address of a switch table entry to execute, for example SIDC806inFIG.8.

FIG.17illustrates, generally at1700, when the calculated instruction address of the switch table entry to execute is beyond an address that is a sum of a starting address of a switch table and the combined sizes of the one or more fixed sized instruction blocks switch table entries then the calculated instruction address is set to a last switch table entry1702.

In one example, the method thus includes wherein when the calculated instruction address of the switch table entry to execute is beyond an address that is a sum of a starting address of a switch table and the combined sizes of the one or more fixed sized instruction blocks switch table entries, for example as determined at SASCC306in

FIG.3, then the calculated instruction address is set to a last switch table entry, for example as changed in SCAC308FIG.3.

Thus a processor switch instruction and a processor responsive to such a processor switch instruction has been described.

For purposes of discussing and understanding the examples, it is to be understood that various terms are used by those knowledgeable in the art to describe techniques and approaches. Furthermore, in the description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the examples. It will be evident, however, to one of ordinary skill in the art that the examples may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the examples. These examples are described in sufficient detail to enable those of ordinary skill in the art to practice the examples, and it is to be understood that other examples may be utilized and that logical, mechanical, and other changes may be made without departing from the scope of the examples.

As used in this description, “one example” or “an example” or similar phrases means that the feature(s) being described are included in at least one example. References to “one example” in this description do not necessarily refer to the same example; however, neither are such examples mutually exclusive. Nor does “one example” imply that there is but a single example. For example, a feature, structure, act, etc. described in “one example” may also be included in other examples. Thus, the invention may include a variety of combinations and/or integrations of the examples described herein.

As used in this description, “substantially” or “substantially equal” or similar phrases are used to indicate that the items are very close or similar. Since two physical entities can never be exactly equal, a phrase such as “substantially equal” is used to indicate that they are for all practical purposes equal.

It is to be understood that in any one or more examples where alternative approaches or techniques are discussed that any and all such combinations as may be possible are hereby disclosed. For example, if there are five techniques discussed that are all possible, then denoting each technique as follows: A, B, C, D, E, each technique may be either present or not present with every other technique, thus yielding 2{circumflex over ( )}5 or 32 combinations, in binary order ranging from not A and not B and not C and not D and not E to A and B and C and D and E. Applicant(s) hereby claims all such possible combinations. Applicant(s) hereby submit that the foregoing combinations comply with applicable EP (European Patent) standards. No preference is given any combination.