Conductive spacer for field emission displays and method

Methods of operating field emission displays are disclosed. In one embodiment, a method for operating a field emission display includes applying a voltage to an extraction grid with respect to an emitter in proximity to the extraction grid to extract electrons from the emitter, regulating a supply of electrons from the emitter in response to a control signal, and accelerating the electrons from the emitter towards a faceplate with an accelerating voltage that also reverse biases a semiconductor diode extending from a baseplate that includes the extraction grid and the emitter to the faceplate.

TECHNICAL FIELD

This invention relates in general to visual displays for electronic devices and in particular to improved spacers for field emission displays.

BACKGROUND OF THE INVENTION

FIG. 1is a simplified side cross-sectional view of a portion of a field emission display10including a faceplate18and a baseplate20in accordance with the prior art.FIG. 1is not drawn to scale. The faceplate18includes a transparent viewing screen22, an antireflective layer23, a transparent conductive layer24and a cathodoluminescent layer26. The transparent viewing screen22supports the layers23,24and26, acts as a viewing surface and as a wall for a hermetically sealed package formed between the viewing screen22and the baseplate20. The viewing screen22may be formed from glass. The antireflective layer23may be formed from Si3N4having a thickness of 900 Angstroms. The transparent conductive layer24may be formed from indium tin oxide. The cathodoluminescent layer26may be segmented into localized portions that are separated from each other within openings in a grille28of light-absorbing, opaque material formed on the antireflective layer23. The light absorption and opacity of the grille28increases the contrast of the faceplate18. The grille28is formed by conventional patterning of a layer of material such as silicon, cobalt oxide, manganese oxide or chromium oxide.

In a conventional monochrome display10, each localized portion of the cathodoluminescent layer26forms one pixel of the display10. Also, in a conventional color display10, each localized portion of the cathodoluminescent layer26forms a primary color such as a green, red or blue sub-pixel of the display10. Materials useful as cathodoluminescent materials in the cathodoluminescent layer26include Y2O3:Eu (red, phosphor P-56), Y3(Al, Ga)5O12:Tb (green, phosphor P-53) and Y2(SiO5):Ce (blue, phosphor P-47) available from Osram Sylvania of Towanda Pa. or from Nichia of Japan.

The baseplate20includes emitters30formed on a planar surface of a substrate32, which may be formed from glass having a layer of silicon formed on it. The baseplate20is coated with a dielectric layer34. In one embodiment, this is effected by deposition of silicon dioxide via a conventional TEOS process. The dielectric layer34is formed to have a thickness that is approximately equal to or just less than a height of the emitters30. This thickness is on the order of 0.4 microns, although greater or lesser thicknesses may be employed. A conductive extraction grid38is formed on the dielectric layer34. The extraction grid38may be formed, for example, as a thin layer of polysilicon. The radius of an opening40created in the extraction grid38, which is also approximately the separation of the extraction grid38from the tip of the emitter30, is about 0.4 microns, although larger or smaller openings40may also be employed.

In operation, the extraction grid38is biased to a voltage on the order of 100 volts, although higher or lower voltages may be used, while the baseplate32is maintained at a voltage of about zero volts. Signals coupled to the emitter30allow electrons to flow to the emitter30. Intense electrical fields between the emitter30and the extraction grid38cause field emission of electrons from the emitter30in response to the signals impressed on the emitter30.

An anode voltage VA, ranging up to as much as 5,000 volts or more but often 2,500 volts or less, is applied to the faceplate18via the transparent conductive layer24. The electrons emitted from the emitter30are accelerated to the faceplate18by the anode voltage VAand strike the cathodoluminescent layer26. The electron bombardment causes light emission in selected areas, i.e., those areas adjacent to where the emitters30are emitting, and forms luminous images such as text, pictures and the like.

A gap separating the faceplate18and the baseplate20of the conventional field emission display10is relatively small, on the order of one thousandth of an inch or twenty-five microns per 100 volts of anode voltage VA. Too large a gap leads to spreading of the emitted electrons and thus to defocusing or blurring of luminous images formed on the faceplate18. Too small a gap leads to catastrophic failure of the display10due to arcing between the faceplate18and the baseplate20. The gap must be evacuated in order for electrons to travel from the emitters30to the faceplate18. As a result, atmospheric pressure is exerted on the faceplate18and the baseplate20that forces the baseplate20and the faceplate18toward each other.

In relatively small displays10, such as those having a diagonal measurement of an inch or less, the pressure on the faceplate18does not cause significant bowing of the faceplate18. In larger displays10, however, the faceplate18tends to bow towards the baseplate20, and the baseplate20also bows towards the faceplate18. In a display10having a diagonal measurement of thirty inches, the force compressing the baseplate20and the faceplate18together is several tons. The bowing is exaggerated because of need to keep the faceplate18and the baseplate20light and thus to make them as thin as is practicable. Bowing leads to non-uniform spacing between the faceplate18and the baseplate20, causing focusing and intensity variations and thereby degrading images formed on the faceplate18. As a result, spacers62are incorporated between the faceplate18and the baseplate20.

The spacers62typically are formed from glass and have a width of 25 to 250 micrometers. The spacers62typically extend from the baseplate20to the faceplate18and thus have a height that is similar to the spacing separating the faceplate18from the baseplate20, in the range of 0.2 to 1 mm. In relatively small displays10, the transparent viewing screen22may be formed from glass having a thickness of about 1.1 mm. In such displays10, spacers62are needed about every fifteen mm. in order to provide adequate support for the faceplate18, but the spacers62may be separated by smaller distances. The spacers62typically are positioned to contact the faceplate18in areas that are opaque due to the grille28in order to avoid interfering with images formed on the display10.

Spacers62tend to be made from insulating materials because the large voltage applied to the transparent conductive layer24otherwise causes arcing between the baseplate20and the faceplate18. Additionally, other techniques that might be tried are either impractical or unworkable for a variety of reasons. For example, forming reverse-biased diodes (not illustrated) on the baseplate32and placing conductive spacers32on the reverse-biased diodes is impractical, because the materials requirements for such diodes are not compatible with other requirements for the baseplate32.

Typically, the spacers62are made from glass or ceramic. As described in U.S. Pat. No. 5,717,287, entitled “Spacers For A Flat Panel Display And Method,” issued to Amrine et al., the spacers62can cause problems in the display10. When the spacers62are affixed to the faceplate18using organic glue, the glue can chemically decompose, causing contamination of the evacuated interior of the display10. Alternatively, the glue can exhibit mechanical failure, causing the spacers62to become detached and misplaced in the interior of the display10. Affixation of glass spacers62to the faceplate18using glass frit results in a brittle bond that is subject to mechanical failure and that may cause particulate contamination within the display10. Additionally, use of a jig to facilitate correct placement of the spacers62on the faceplate18is laborious and may be unreliable.

What is needed is a way to simplify formation and accurate placement of spacers in field emission displays and to provide more robust spacers for use in field emission displays.

SUMMARY OF THE INVENTION

In accordance with one aspect of the invention, a field emission display includes a spacer formed from silicon that prevents significant faceplate or baseplate bowing. In one aspect, the spacer is formed in situ on the faceplate after deposition of other faceplate components by anodic bonding of a silicon wafer to a glass layer that has been formed on the faceplate. Portions of the silicon wafer that are not needed for the spacer are removed by directional etching processes. In one aspect, the spacer also forms a diode that is reverse biased by voltages applied to the faceplate to accelerate electrons towards the faceplate.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 2is a simplified side cross-sectional view of a portion of a field emission display10′ including a spacer62′, in accordance with an embodiment of the present invention.FIG. 2is not drawn to scale. Many of the components used in the field emission display10′ shown inFIG. 2are identical to components used in the field emission display10of FIG.1. Therefore, in the interest of brevity, these components have been provided with the same reference numerals, and an explanation of them will not be repeated.

In the embodiment ofFIG. 2, the spacer62′ may be formed from silicon. In one embodiment, an insulating layer64positioned at the end of the spacer62′ is formed from spin-on glass. In one embodiment, the insulating layer64has a thickness in excess of two microns. A layer66may be included between the insulating layer64and the transparent conductive layer24. In one embodiment, the layer66is formed from conventional polycrystalline silicon. In another embodiment, a conventional layer of metal, such as aluminum, nickel or other metal, forms the layer66. The layer66is used to protect the transparent conductive layer24from chemical attack at a later stage in fabrication when the insulating layer64is etched. In one embodiment, the spacer62may be conductive and attached to the insulating layer64through a process of anodic bonding, as described below.

FIG. 3is a simplified side cross-sectional view of a portion of a faceplate at one stage in fabrication, according to an embodiment of the present invention. The grille28has previously been fabricated on the transparent viewing screen22using conventional photolithography and deposition techniques. The transparent conductive layer24has previously been fabricated on the transparent viewing screen22and the grille28using conventional deposition techniques.

The layer66has previously been fabricated of polycrystalline silicon or metal using conventional deposition techniques. The insulating layer64may be formed using spin-on-glass (e.g., TEOS and a sodium or potassium salt dissolved in ethanol), as described in “Silicon-Silicon Anodic-Bonding With Intermediate Glass Layers Using Spin-On Glasses,” by H. J. Quenzer et al. (Proc. Ninth Annual Int. Workshop on Micro Electro Mech. Sys., IEEE Cat. No. 96CH35856 (Feb. 11-15, 1996), pp. 272-267.). Alternatively, the insulating layer64may be formed by sputtering, as described in “Field-Assisted Bonding Below 200° C. Using Metal And Glass Thin-Film Interlayers,” by W. Y. Lee et al. (App. Phys. Lett., Vol. 59, No. 9 (1987), pp. 522-524.). In another embodiment, the insulating layer64may be formed using other conventional processes, such as electron beam evaporation. In one embodiment, the insulating layer64may be planarized and smoothed using conventional chemical-mechanical polishing.

FIG. 4is a simplified side cross-sectional view of the faceplate ofFIG. 3at a later stage in fabrication, according to an embodiment of the present invention. A silicon wafer67having one metallized surface68is placed to have another surface70in intimate contact with the insulating layer64to form a composite assembly72. A voltage source74has a negative lead coupled to the transparent conductive layer24and to the layer66. A positive lead of the voltage source74is coupled to the metallized surface68. In one embodiment, the metallized surface68forms an ohmic contact with the silicon wafer67. In another embodiment, the metallized surface forms a Schottky contact with n-type silicon forming the silicon wafer67. The composite assembly72is heated and a voltage of several hundred volts is supplied by the voltage source74to anodically bond the silicon wafer67to the insulating layer64.

Anodic bonding is described in U.S. Pat. No. 3,397,278, entitled “Anodic Bonding,” issued to D. I. Pomerantz, and in “Field Assisted Glass-Metal Sealing,” by G. Wallis et al. (Jour. App. Phys., Vol. 40, No. 10 (September 1969), pp. 3946-3949.). Anodic bonding of silicon to an insulating layer is described in “Anodic Bonding Technique For Silicon-to-ITO Coated Glass Bonding,” by W. B. Choi et al. (Proc. Soc. Phot. Opt. Inst. Eng., Vol. 3046 (1997), pp. 336-341.). Selection of glass composition for the insulating layer64to provide temperature coefficient of expansion matching to the silicon wafer67and to allow room-temperature anodic bonding is discussed in “Low-Temperature Silicon-to-Silicon Anodic Bonding With Intermediate Low Melting Point Glass,” by M. Esashi et al. (Sensors and Actuators, A21-A23 (1990), pp. 931-934.). Significantly, anodic bonding provides bonds having superior mechanical strength and does not introduce additional materials that can result in contamination of the interior of the field emission display10′.

FIG. 5is a simplified side cross-sectional view of the faceplate ofFIG. 4at a later stage in fabrication, according to an embodiment of the present invention. The metallization on the surface68(FIG. 4) has been stripped using conventional etching techniques and a hard mask76is formed from a material such as SiO2deposited by conventional TEOS or Si3N4deposited by conventional PECVD. The hard mask76is patterned using conventional photolithographic techniques.

FIG. 6is a simplified side cross-sectional view of the faceplate ofFIG. 5at a later stage in fabrication, according to an embodiment of the present invention. Reactive ion etching is used to anisotropically etch the silicon wafer67(FIGS.4and5), leaving the spacers62′. Anisotropic etching is discussed in “Reactive Ion Etching For High Aspect Ratio Silicon Micromachining,” by I. W. Rangelow (Surf. and Coatings Tech. 97 (1997), pp. 140-150.). Reactive ion etchers capable of etching >300 microns of silicon at an etch rate of 3 microns a minute using positive photoresist or a hard mask are available from Surface Technology Systems USA, Inc., 611 Veterans Boulevard, Suite 107, Redwood City, Calif. 94063.

In one embodiment, the spacers62′ are formed from silicon having a dopant concentration of about 2×1014/cm3or less to realize an avalanche breakdown voltage of in excess of 1,000 volts, and in any case a dopant concentration of 7×1014/cm3or less to realize an avalanche breakdown voltage of in excess of 400 volts. In one embodiment, a cathode of the spacer62′ is coupled to the faceplate18′. In one embodiment, the cathode is formed as a Schottky contact with the faceplate18′. In one embodiment, an anode is formed by doping the portion of the spacer62′ that will contact the baseplate20with acceptors. In one embodiment, the spacer62′ is formed from intrinsic silicon in order to realize a high resistivity. Gold doping may be used to reduce mobile charge carrier concentrations in the spacer62′. In one embodiment, the spacer62′ is formed from polycrystalline silicon. In one embodiment, the spacer62′ is formed as a diode having a carrier concentration such that a depletion region in the diode extends along most of the length of the spacer from the faceplate18′ to the baseplate20when the anode voltage VAis applied to the faceplate18′.

It will be appreciated that spacers62′ that include diodes may be formed in a variety of different ways, and may have a p-n junction that may be placed anywhere along the height of the spacer62′ by suitable choice of doping levels and other conventional diode parameters. It will also be appreciated that a Schottky junction may be formed at either end of the spacer62′ by appropriate choice of conductivity type for the spacer62′. In one embodiment, the spacer62′ is coated with a conventional passivation layer (not shown). In one embodiment, respective ends of the spacer62′ are coupled to conventional conductors (not shown) formed on the faceplate18′ and on the baseplate20. In one embodiment, ends of the spacers62′ corresponding to the anodes shown inFIG. 6couple to bumps of soft conductive material (not shown) formed on the baseplate20.

FIG. 7is a simplified plan view of a portion of the faceplate ofFIG. 6including spacers62′ of arbitrary geometry, according to an embodiment of the present invention. In one embodiment, a faceplate for a display10′ having XGA resolution includes an array of approximately 1024 by 768 pixels formed from cathodoluminescent layers26. In this type of display10′, each pixel is about 60 microns by 180 microns, providing a faceplate having a display area of 9.65 inches by 7.28 inches. The cathodoluminescent layer26may be formed using a resist formed from polyvinyl alcohol and an ammonium dichromate sensitizer. The resist may be deposited and patterned after the spacers62′ are formed. The insulating layer64may then be etched, for example with a buffered oxide etch containing hydrofluoric acid. The layer66may be etched using conventional etching processes. Isopropyl alcohol may be used as a carrier medium to selectively deposit the cathodoluminescent layer26, using the transparent conductive layer24as one electrode in a conventional electrophoretic deposition process. Fabrication of the field emission display10′ is subsequently completed via conventional fabrication steps.

FIG. 8is a simplified plan view of a portion of a faceplate18′ including spacers62′ and an insulating layer64surrounding an area where the spacer62′ contacts the faceplate18′, in accordance with an embodiment of the present invention. The insulating layer64is formed to have a thickness sufficient to withstand the anode voltage VA, and is patterned to provide an area surrounding the spacer62′ that is wide enough to prevent arcing from the spacer62′ to the transparent conductive layer24, i.e., having a width comparable to the height of the spacer62′. For example, for a glass having a breakdown field strength of 1.4×105volts/cm. to withstand an anode voltage VAof 500 volts, an insulating layer64having a thickness of about forty microns is required.

In one embodiment, the pixels26are formed of cathodoluminescent materials chosen to emit different colors of light when bombarded by electrons. For example, the lower left and upper right pixels26may include phosphor P-56 and emit red light. The upper left pixel26may include phosphor P-53 and emit green light, and the lower right pixel26may include phosphor P-47 and emit blue light.

FIG. 9is a simplified block diagram of a portion of a computer100including the field emission display10′ having the spacer62′ as described with reference toFIGS. 2 through 8and associated text. The computer100includes a central processing unit102coupled via a bus104to a memory106, function circuitry108, a user input interface110and the field emission display10′ including the spacer62′, according to the embodiments of the present invention. The memory106may or may not include a memory management module (not illustrated) and does include ROM for storing instructions providing an operating system and a read-write memory for temporary storage of data. The processor102operates on data from the memory106in response to input data from the user input interface110and displays results on the field emission display10′. The processor102also stores data in the read-write portion of the memory106. Examples of systems where the computer100or the display10′ finds application include personal/portable computers, camcorders, televisions, automobile electronic systems, microwave ovens and other home and industrial appliances.

Field emission displays10′ for such applications provide significant advantages over other types of displays, including reduced power consumption, improved range of viewing angles, better performance over a wider range of ambient lighting conditions and temperatures and higher speed with which the display can respond. Field emission displays find application in most devices where, for example, liquid crystal displays find application.

Although the present invention has been described with reference to various embodiments, the invention is not limited to these embodiments. Rather, the invention is limited only by the appended claims, which include within their scope all equivalent devices or methods which operate according to the principles of the invention as described.