Memory transaction management

A device includes a processor coupled to a memory. The processor is configured to assign distinct domain identifiers to each of multiple software threads. The processor is also configured to control operation of one or more components of the processor based on a number of memory transactions associated with a domain identifier.

The present disclosure is generally related to management of memory transactions.

II. DESCRIPTION OF RELATED ART

Advances in technology have resulted in smaller and more powerful computing devices. For example, there currently exist a variety of portable personal computing devices, including wireless telephones such as mobile and smart phones, tablets and laptop computers that are small, lightweight, and easily carried by users. These devices can communicate voice and data packets over wireless networks. Further, many such devices incorporate additional functionality such as a digital still camera, a digital video camera, a digital recorder, and an audio file player. Also, such devices can process executable instructions, including software applications, such as a web browser application, that can be used to access the Internet. As such, these devices can include significant computing capabilities.

Such computing devices incorporate functionality to support memory transactions, such as reads from memory and writes to memory. Data that is read from memory or is to be written to memory is often temporarily stored in a buffer. Buffer resources are consumed as software threads make memory requests. Software threads stall when no buffer resources are available for a memory transaction. Some data may stay longer in the buffer for a software thread that takes longer to consume or process the data. Slower traffic can congest the system and block memory requests from other software threads, resulting in delays and reduced quality of service.

According to one implementation of the present disclosure, a device includes a memory and a processor. The processor is coupled to the memory and is configured to assign distinct domain identifiers to each of multiple software threads. The processor is also configured to control operation of one or more components of the processor based on a number of memory transactions associated with a domain identifier.

According to another implementation of the present disclosure, a computer-implemented method includes assigning, at a device, distinct domain identifiers to each of multiple software threads. The method also includes controlling, at the device, operation of one or more components of a processor based on a number of memory transactions associated with a domain identifier.

According to another implementation of the present disclosure, a non-transitory computer-readable medium stores instructions that, when executed by a processor, cause the processor to assign distinct domain identifiers to each of multiple software threads. The instructions, when executed by the processor, also cause the processor to control operation of one or more components of the processor based on a number of memory transactions associated with a domain identifier.

According to another implementation of the present disclosure, an apparatus includes means for assigning distinct domain identifiers to each of multiple software threads. The apparatus also includes means for controlling operation of one or more components of a processor based on a number of memory transactions associated with a domain identifier.

V. DETAILED DESCRIPTION

Data read from memory or to be written to memory can be stored in a buffer. Buffer resources are consumed as software threads make memory requests. Software threads stall when no buffer resources are available for a memory transaction. Some data may stay longer in the buffer for a software thread that takes longer to consume or process the data. Slower traffic can congest the system and block memory requests from other software threads, resulting in delays and reduced quality of service.

Synchronization operations can be used to enforce ordering. When a typical synchronization operation is performed, all pending transactions have to be completed before any subsequent data access operations can be performed. This can lead to software threads being stalled for long periods.

System and methods of memory transaction management are disclosed. For example, a memory manager assigns domain identifiers to software threads. A domain identifier is assigned to a software thread based on a thread type of the software thread. The thread type can be based on an application, an application type, a device, a device type, a traffic type, or a combination thereof, associated with the thread. As an illustrative example, the memory manager assigns a first domain identifier to a first software thread based on a thread type of the first software thread, and a second domain identifier to a second software thread based on a thread type of the second software thread. The memory manager tracks a number (e.g., count) of memory transactions associated with each of the first domain identifier and the second domain identifier. The memory manager controls operation of one or more components of a processor based on the number of memory transactions associated with a domain identifier.

In some implementations, a synchronization instruction is used to enforce consistency (e.g., ordering of data access) for a software thread. As an illustrative example, the first domain identifier assigned to the first software thread includes a first consistency domain identifier, and the second domain identifier assigned to the second software thread includes a second consistency domain identifier. In response to receiving a synchronization instruction of the first software thread, any pending store operations associated with the first consistency domain identifier are completed prior to performing any subsequent data access instruction associated with the first consistency domain identifier, thereby enforcing consistency for the first software thread. For example, assigning the first consistency domain identifier to a software thread of a first application enables enforcing consistency for the software thread of the first application independently of software threads of other applications.

In some examples, some consistency domain identifiers (e.g., sub-domain identifiers) that are not the same as the first consistency domain identifier can match the first consistency domain identifier. In these examples, responsive to the synchronization instruction, any pending store operations associated with the first consistency domain identifier or the second consistency domain identifier are completed prior to performing any subsequent data access instruction associated with the first consistency domain identifier or the second consistency domain identifier if the second consistency domain identifier matches the first consistency domain identifier.

Data access instructions associated with consistency domain identifiers that do not match the first consistency domain identifier are not affected (e.g., not delayed) by the synchronization instruction associated with the first software thread. To illustrate, data access instructions associated with the second software thread are not delayed by the synchronization instruction if the second consistency domain identifier does not match the first consistency domain identifier.

Controlling the operation of one or more components of the processor includes, in response to receiving the synchronization instruction, completing any pending store operations associated with any consistency domain identifier that matches the first consistency domain identifier prior to performing any subsequent data access instruction associated with any consistency domain identifier that matches the first consistency domain. Any subsequent data access instruction associated with any consistency domain identifier that matches the first consistency domain is thus performed after a number of prior pending memory transactions associated with any consistency domain identifier that matches the first consistency domain identifier is zero, while subsequent data access instructions associated with consistency domain identifiers that do not match the first consistency domain identifier are not similarly delayed.

In some implementations, up to a threshold count of memory access instructions associated with a domain identifier can be pending at any time so that some resources can be available for memory access instructions associated with other domain identifiers. As an illustrative example, the first domain identifier assigned to the first software thread includes a first capacity domain identifier, and the second domain identifier assigned to the second software thread includes a second capacity domain identifier. The first capacity domain identifier is associated with a first threshold count. A memory access instruction from the first software thread is selectively enabled in response to determining that a count of pending memory access instructions associated with the first capacity domain identifier is less than the first threshold count. In these implementations, controlling the operation of one or more components of the processor includes selectively enabling the memory access instruction based on capacity limits. Limiting the count of pending memory access instructions associated with a capacity domain identifier can enable resources to be available for memory access instructions associated with other non-matching capacity domain identifiers. For example, assigning the first capacity domain identifier to a software thread of a first application enables enforcing resource limitations for the first application independently of resource limits for other applications.

Particular aspects of the present disclosure are described below with reference to the drawings. In the description, common features are designated by common reference numbers. As used herein, various terminology is used for the purpose of describing particular implementations only and is not intended to be limiting of implementations. For example, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Further, some features described herein are singular in some implementations and plural in other implementations. To illustrate,FIG.1depicts a device102including one or more processors (“processor(s)”190ofFIG.1), which indicates that in some implementations the device102includes a single processor190and in other implementations the device102includes multiple processors190.

In some drawings, multiple instances of a particular type of feature are used. Although these features are physically and/or logically distinct, the same reference number is used for each, and the different instances are distinguished by addition of a letter to the reference number. When the features as a group or a type are referred to herein, e.g., when no particular one of the features is being referenced, the reference number is used without a distinguishing letter. However, when one particular feature of multiple features of the same type is referred to herein, the reference number is used with the distinguishing letter. For example, referring toFIG.1, multiple cache control registers (CCRs) are illustrated and associated with reference numbers154A and154B. When referring to a particular one of these cache control registers, such as a cache control register (CCR)154A, the distinguishing letter “A” is used. However, when referring to any arbitrary one of these cache control registers or to these cache control registers as a group, the reference number154is used without a distinguishing letter.

As used herein, the terms “comprise,” “comprises,” and “comprising” may be used interchangeably with “include,” “includes,” or “including.” Additionally, the term “wherein” may be used interchangeably with “where.” As used herein, “exemplary” indicates an example, an implementation, and/or an aspect, and should not be construed as limiting or as indicating a preference or a preferred implementation. As used herein, an ordinal term (e.g., “first,” “second,” “third,” etc.) used to modify an element, such as a structure, a component, an operation, etc., does not by itself indicate any priority or order of the element with respect to another element, but rather merely distinguishes the element from another element having a same name (but for use of the ordinal term). As used herein, the term “set” refers to one or more of a particular element, and the term “plurality” refers to multiple (e.g., two or more) of a particular element.

As used herein, “coupled” may include “communicatively coupled,” “electrically coupled,” or “physically coupled,” and may also (or alternatively) include any combinations thereof. Two devices (or components) may be coupled (e.g., communicatively coupled, electrically coupled, or physically coupled) directly or indirectly via one or more other devices, components, wires, buses, networks (e.g., a wired network, a wireless network, or a combination thereof), etc. Two devices (or components) that are electrically coupled may be included in the same device or in different devices and may be connected via electronics, one or more connectors, or inductive coupling, as illustrative, non-limiting examples. In some implementations, two devices (or components) that are communicatively coupled, such as in electrical communication, may send and receive signals (e.g., digital signals or analog signals) directly or indirectly, via one or more wires, buses, networks, etc. As used herein, “directly coupled” may include two devices that are coupled (e.g., communicatively coupled, electrically coupled, or physically coupled) without intervening components.

In the present disclosure, terms such as “determining,” “calculating,” “estimating,” “shifting,” “adjusting,” etc. may be used to describe how one or more operations are performed. It should be noted that such terms are not to be construed as limiting and other techniques may be utilized to perform similar operations. Additionally, as referred to herein, “generating,” “calculating,” “estimating,” “using,” “selecting,” “accessing,” and “determining” may be used interchangeably. For example, “generating,” “calculating,” “estimating,” or “determining” a parameter (or a signal) may refer to actively generating, estimating, calculating, or determining the parameter (or the signal) or may refer to using, selecting, or accessing the parameter (or signal) that is already generated, such as by another component or device.

Referring toFIG.1, a particular illustrative aspect of a system100configured to manage memory transactions is disclosed. The system100includes a device102that is configured to manage memory transactions using a memory manager140.

The device102includes one or more processors190coupled to a memory120. In a particular aspect, the memory120includes data storage, a memory controller, or both. In some aspects, a cache172(e.g., a memory buffer) is coupled via an interface174to the memory120. The one or more processors190include the memory manager140and one or more components170. In some aspects, the one or more components170include one or more of the cache172, the interface174, the memory120, a data bus, a modem, an antenna, an instruction buffer, or a coprocessor (e.g., a graphics processing unit (GPU), a digital signal processor (DSP), or another type of processor). The memory manager140has access to configuration data146, domain identifier data150, a transaction tracker160, or a combination thereof. The memory manager140includes a consistency domain manager142, a capacity domain manager144, or both.

The transaction tracker160is configured to track consistency domain number of transactions data162, capacity domain number of transactions data164, or both. In a particular aspect, the consistency domain number of transactions data162indicates numbers (e.g., counts) of transactions associated with each of one or more consistency domain identifiers156. In a particular aspect, the capacity domain number of transactions data164indicates numbers (e.g., counts) of transactions associated with each of one or more capacity domain identifiers158.

The memory manager140is configured to assign distinct domain identifiers (e.g., a consistency domain identifier156, a capacity domain identifier158, or both) to each of a plurality of software threads152. In some aspects, a process (e.g., an application) executing at the one or more processors190initializes a software thread152. In some aspects, the software thread152corresponds to a database worker thread. For example, the software thread152receives data access requests from another process or device, and services the data access requests by sending memory access instructions to the memory manager140.

The memory manager140is configured to manage memory transactions of the one or more software threads152based on the domain identifiers. For example, the consistency domain manager142is configured to manage memory transactions based on the consistency domain number of transactions data162. As another example, the capacity domain manager144is configured to manage memory transactions based on the capacity domain number of transactions data164. In some examples, the memory transactions include one or more of reading data from the memory120via the interface174to the cache172, providing data from the cache172to a software thread152, updating data in the cache172based on data received from the software thread152, or writing updated data from the cache172via the interface174to the memory120. In some aspects, controlling operation of the one or more components170includes, or corresponds to, performing the memory transactions.

In some implementations, the device102corresponds to or is included in one of various types of devices. In an illustrative example, the one or more processors190are integrated in a headset device, such as described further with reference toFIG.19. In other examples, the one or more processors190are integrated in at least one of a mobile phone or a tablet computer device, as described with reference toFIG.18, a wearable electronic device, as described with reference toFIG.20, a voice-controlled speaker system, as described with reference toFIG.21, a camera device, as described with reference toFIG.22, or a virtual reality, mixed reality, or augmented reality headset, as described with reference toFIG.23. In another illustrative example, the one or more processors190are integrated into a vehicle, such as described further with reference toFIG.24andFIG.25.

During operation, the memory manager140assigns distinct domain identifiers to each of one or more software threads152based on corresponding thread types. For example, a software thread of a first thread type is assigned a domain identifier having a particular prefix (e.g., “00”), and a software thread of a second thread type is assigned a domain identifier having another prefix (e.g., “01”). A thread type of a software thread can be based on an application, an application type, a device, a device type, a traffic type, or a combination thereof, associated with the software thread.

In some implementations, a cache control register154associated with a software thread152indicates a consistency domain identifier156, a capacity domain identifier158, or both, assigned to the software thread152. For example, during initialization of a software thread152A, the consistency domain manager142updates a cache control register154A associated with the software thread152A to indicate that a consistency domain identifier156A is assigned to the software thread152A. In some aspects, the capacity domain manager144, during initialization of the software thread152A, updates the cache control register154A to indicate that a capacity domain identifier158A is assigned to the software thread152A.

Similarly, during initialization of a software thread152B, the consistency domain manager142updates a cache control register154B associated with the software thread152B to indicate that the consistency domain identifier156B is assigned to the software thread152B. The consistency domain identifier156A is distinct from the consistency domain identifier156B. In some aspects, the capacity domain manager144, during initialization of the software thread152B, updates the cache control register154B to indicate that a capacity domain identifier158B is assigned to the software thread152B. The capacity domain identifier158A is distinct from the capacity domain identifier158B.

In a particular aspect, the domain identifier data150ofFIG.1represents the cache control register154A indicating that the consistency domain identifier156A, the capacity domain identifier158A, or both, are assigned to the software thread152A. In a particular aspect, the domain identifier data150ofFIG.1represents the cache control register154B indicating that the consistency domain identifier156B, the capacity domain identifier158B, or both, are assigned to the software thread152B.

The memory manager140manages memory transactions based at least in part on whether the software thread152A and the software thread152B have matching domain identifiers, as further described with reference toFIGS.2-15. For example, the consistency domain manager142manages memory transactions based at least in part on whether the consistency domain identifier156A matches the consistency domain identifier156B, as further described with reference toFIGS.2and4-15. To illustrate, the consistency domain manager142, in response to a store associated with the software thread152A being committed, updates (e.g., increments) the consistency domain number of transactions data162to indicate a pending store operation associated with the consistency domain identifier156A, as further described with reference toFIG.5. The consistency domain manager142, in response to receiving a synchronization instruction of the software thread152A and determining that the consistency domain number of transactions data162indicates at least one pending store operation that matches the consistency domain identifier156A, refrains from performing any subsequent memory access instructions that match the consistency domain identifier156A, as further described with reference toFIGS.6-7. The consistency domain manager142determines that a pending store operation “matches” the consistency domain identifier156A in response to determining that the pending store operation is associated with a consistency domain identifier (e.g., the consistency domain identifier156A or another consistency domain identifier) that matches the consistency domain identifier156A, as further described with reference toFIG.2. The consistency domain manager142updates (e.g., decrements) the consistency domain number of transactions data162in response to receiving an acknowledgement from the memory120that the pending store operation has been completed, as further described with reference toFIG.8.

In some aspects, the consistency domain manager142, in response to determining that there are no pending store operations that match the consistency domain identifier156A subsequent to receiving the synchronization instruction of the software thread152A, enables subsequent memory access operations associated with any consistency domain identifiers (e.g., the consistency domain identifier156A or another consistency domain identifier) that match the consistency domain identifier156A to be performed.

In some examples, the capacity domain manager144manages memory transactions associated with the software thread152A and the software thread152B based at least in part on whether the capacity domain identifier158A matches the capacity domain identifier158B, as further described with reference toFIGS.3and16-17. To illustrate, the capacity domain number of transactions data164indicates a count of pending memory accesses that match the capacity domain identifier158A. In some aspects, a pending memory access “matches” the capacity domain identifier158A when the pending memory access is associated with a capacity domain identifier (e.g., the capacity domain identifier158A or another capacity domain identifier) that matches the capacity domain identifier158A. The capacity domain manager144, in response to receiving a memory access instruction from the software thread152A, determines whether the count of pending memory accesses is greater than or equal to a threshold count, as further described with reference toFIGS.16-17. The capacity domain manager144, in response to determining that the count of pending memory accesses is less than the threshold count, initiates a memory access associated with the memory access instruction and updates (e.g., increments) the count of memory accesses indicated by the capacity domain number of transactions data164. Alternatively, the capacity domain manager144, in response to determining that the count of pending memory accesses is greater than or equal to the threshold count, refrains from performing the memory access. The capacity domain manager144updates (e.g., decrements) the capacity domain number of transactions data164in response to receiving an acknowledgement that a pending memory access is complete, as further described with reference toFIGS.16-17.

The capacity domain manager144limits a count of pending memory accesses that match a capacity domain identifier to enable resources to be available for memory accesses associated with other non-matching capacity domain identifiers. The consistency domain manager142ensures that a synchronization instruction associated with a particular consistency domain identifier does not affect (e.g., delay) memory access instructions associated with other consistency domain identifiers that do not match the particular consistency domain identifier.

The memory manager140is described as managing memory transactions for the memory120that is included in the device102as an illustrative example. In other examples, the memory manager140can perform similar operations, based on domain identifiers, to manage transactions for another component of the device102or to manage transactions for another device. In an illustrative example, the memory manager140manages data transactions with (e.g., data storage to or retrieval from) an external device based on the consistency domain identifiers156, the capacity domain identifiers158, or a combination thereof.

Referring toFIG.2, an example of consistency domain configuration data202is shown, along with multiple sets of consistency domain identifiers222-228based on the consistency domain configuration data202. In a particular aspect, the consistency domain configuration data202is included in the configuration data146ofFIG.1. The consistency domain configuration data202can be implemented as a collection of bits (e.g., a bitmask) in which “1” values designate which bits are compared when determining whether two or more consistency domain identifiers156“match” each other, as described further below.

Each cache control register154includes a first count of bits (e.g., 32 bits) from a least significant bit (e.g., bit0) to a most significant bit (e.g., bit31). In some aspects, a first set of bits (e.g., bit8to bit15) of a cache control register154associated with a software thread152can be used to indicate a consistency domain identifier156assigned to the software thread152.

In some implementations, the first set of bits (e.g., bit8to bit15) of cache control registers154indicates multiple sets of consistency domain identifiers that can be used to define domains or sub-domains of consistency domain identifiers. The consistency domain configuration data202indicates bits of the cache control registers154that are implemented for indicating sets of consistency domain identifiers. To illustrate, the consistency domain configuration data202indicates that a first subset (e.g., bit14to bit15) of the first set of bits (e.g., bit8to bit15) of cache control registers154is implemented for indicating sets of consistency domain identifiers. For example, the first subset (e.g., bit14to bit15) of bits of a particular consistency domain identifier156indicates a set of consistency domain identifiers that includes that particular consistency domain identifier156.

In a particular aspect, a count of bits (e.g., 2) of the first subset indicates a count of sets of consistency domain identifiers (e.g., 2(count of bits)or 4 sets) that are supported. For example, bit values212of the first subset (e.g., a value of 0 for each of bit15and bit14) indicate a set of consistency domain identifiers222(e.g., binary 00000000 to 00111111 or decimal 0 to 63). Bit values214of the first subset (e.g., a value of 0 for bit15and a value of 1 for bit14) indicate a set of consistency domain identifiers224(e.g., binary 01000000 to 01111111 or decimal 64 to 127). Bit values216of the first subset (e.g., a value of 1 for bit15and a value of 0 for bit14) indicate a set of consistency domain identifiers226(e.g., binary 10000000 to 10111111 or decimal 128 to 195). Bit values218of the first subset (e.g., a value of 1 for each of bit15and bit14) indicate a set of consistency domain identifiers228(e.g., binary 11000000 to 11111111 or decimal 196 to 255). In the illustrated example, the first subset includes 2 bits that can support four sets of consistency domain identifiers. However, in other examples, the first subset can include any count of bits that support a corresponding count of sets of consistency domain identifiers (e.g., the first subset including 3 bits can support8sets of consistency domain identifiers, etc.).

In some implementations, each set of consistency domain identifiers corresponds to a respective consistency domain. In these implementations, two or more consistency domain identifiers “match” each other if they have the same bit values for the first subset (e.g., bit14to bit15). For example, the consistency domain identifier156A matches the consistency domain identifier156B if each of the consistency domain identifier156A and the consistency domain identifier156B has the same bit values of the first subset (e.g., bit14to bit15). To illustrate, the consistency domain identifier156A matches the consistency domain identifier156B if both of the consistency domain identifier156A and the consistency domain identifier156B are included in the same one of the set of consistency domain identifiers222(e.g., decimal 0 to 63), the set of consistency domain identifiers224(e.g., decimal 64 to 127), the set of consistency domain identifiers226(e.g., decimal 128 to 195), or the set of consistency domain identifiers228(e.g., decimal 196 to 255).

In an example in which the consistency domain identifier156A has a first value “4” and the consistency domain identifier156B has a second value “6,” the consistency domain identifier156A having the first value (e.g., decimal 4) included in the set of consistency domain identifiers222(e.g., decimal 0 to 63) matches the consistency domain identifier156B having the second value (e.g., decimal 6) that is also included in the set of consistency domain identifiers222. In an example in which the consistency domain identifier156A has a first value “4” and the consistency domain identifier156B has a second value “125,” the consistency domain identifier156A having the first value (e.g., decimal 4) included in the set of consistency domain identifiers222(e.g., decimal 0 to 63) does not match the consistency domain identifier156B having the second value (e.g., decimal 125) that is not included in the set of consistency domain identifiers222.

In some implementations, one or more of the consistency domains can include multiple sets of consistency domain identifiers. For example, a first consistency domain includes the set of consistency domain identifiers222(e.g., decimal 0 to 63) and the set of consistency domain identifiers224(e.g., decimal 64 to 127). A second consistency domain includes the set of consistency domain identifiers226(e.g., decimal 128 to 195) and the set of consistency domain identifiers228(e.g., decimal 196 to 255). In this example, the first consistency domain corresponds to a value of 0 for bit15, and the second consistency domain corresponds to a value of 1 for bit15. In some implementations, a consistency domain identifier156A (e.g., decimal 3) included in the first consistency domain (e.g., decimal 0 to 127) matches a consistency domain identifier156B (e.g., decimal 70) included in the first consistency domain. However, a consistency domain identifier156A (e.g., decimal 3) included in the first consistency domain (e.g., decimal 0 to 127) does not match a consistency domain identifier156B (e.g., decimal 129) that is not included in the first consistency domain.

In some aspects, the consistency domain manager142assigns domain identifiers from the first consistency domain (e.g., decimal 0 to 127) to software threads152associated with a first thread type, and assigns domain identifiers from the second consistency domain (e.g., decimal 128 to 255) to software threads152associated with a second thread type. A thread type of a software thread152can be based on an application, an application type, a device, a device type, a traffic type, or a combination thereof, associated with the software thread152. In a particular aspect, traffic type can include communication traffic type, such as cellular traffic, wireless local-area network (WLAN) traffic, Bluetooth® (a registered trademark of BLUETOOTH SIG, INC., Washington) traffic, fifth generation (5G) cellular digital network, Institute of Electrical and Electronic Engineers (IEEE) 802.11-type network (e.g., WiFi) traffic, or other types of communication traffic. As an example, the first thread type is associated with cellular modem traffic and the second thread type is associated with WLAN traffic. Assigning consistency domain identifiers from the first consistency domain (e.g., decimal 0 to 127) to software threads152associated with cellular modem traffic, and assigning consistency domain identifiers from the second consistency domain (e.g., decimal 128 to 255) to software threads152associated with the WLAN traffic enables segregation of cellular modem traffic and WLAN traffic. For example, cellular modem memory transactions are not blocked by synchronization operations associated with WLAN memory transactions, and vice versa.

In some implementations, a consistency domain can be divided into sub-domains. For example, the first consistency domain can include a first sub-domain including the set of consistency domain identifiers222(e.g., decimal 0 to 63) and a second sub-domain including the set of consistency domain identifiers224(e.g., decimal 64 to 127). In some aspects, the second consistency domain includes the set of consistency domain identifiers226(e.g., 128 to 195) and the set of consistency domain identifiers228(e.g., 196 to 255) that are not divided into sub-domains.

In some implementations, a consistency domain identifier156A (e.g., decimal 3) included in the first sub-domain (e.g., decimal 0 to 63) matches a consistency domain identifier156B (e.g., decimal 62) included in the first sub-domain. However, a consistency domain identifier156A (e.g., decimal 3) included in the first sub-domain (e.g., decimal 0 to 63) does not match a consistency domain identifier156B (e.g., decimal 70) that is not included in the first sub-domain. For example, a consistency domain identifier156A included in the first sub-domain (e.g., decimal 0 to 63) of the first consistency domain does not match a consistency domain identifier156B included in a second sub-domain (e.g., decimal 64 to 127) of the first consistency domain.

In some aspects, the consistency domain manager142assigns consistency domain identifiers156from the first sub-domain (e.g., decimal 0 to 63) to software threads152associated with a first thread sub-type of the first thread type, and assigns consistency domain identifiers156from the second sub-domain (e.g., decimal 64 to 127) to software threads152associated with a second thread sub-type of the first thread type. A thread sub-type of a software thread152can be based on an application, an application type, a device, a device type, a traffic type, or a combination thereof, associated with the software thread152. For example, the first thread sub-type is associated with cellular modem traffic from the device102to a first device, and the second thread sub-type is associated with cellular modem traffic from the device102to a second device.

Assigning consistency domain identifiers156from the first sub-domain (e.g., decimal 0 to 63) to software threads152associated with the cellular modem traffic to the first device, and assigning consistency domain identifiers from the second sub-domain (e.g., decimal 64 to 127) to software threads152associated with cellular modem traffic to the second device enables segregation between cellular modem traffic to the first device and cellular modem traffic to the second device. For example, cellular modem memory transactions associated with the first device are not blocked by synchronization operations associated with cellular modem memory transactions associated with the second device, and vice versa. Thus, in some implementations, matching is determined at the sub-domain level rather than at the domain level.

In some implementation, matching can be determined at the domain level or at the sub-domain level. For example, a particular value (e.g., 0) of a consistency domain identifier156A can be used to indicate that a synchronization operation is associated with an entire domain as compared to one of the sub-domains. In some aspects, the particular value (e.g., 0) is reserved to indicate the entire domain and is not included in any sub-domain. In a particular example, a consistency domain identifier156A (e.g., decimal 0) is used to indicate a first consistency domain that includes a first sub-domain (e.g., decimal 1 to 63) and a second sub-domain (e.g., decimal 64 to 127). For example, a consistency domain identifier156B (e.g., decimal 1 to 63 of the first sub-domain) matches the consistency domain identifier156A (e.g., decimal 0 indicating the first consistency domain) to block cellular modem memory transactions of the first sub-domain during a synchronization operation associated with the consistency domain identifier156A. As another example, a consistency domain identifier156B (e.g., decimal 64 to 127 of the second sub-domain) also matches the consistency domain identifier156A (e.g., decimal 0 indicating the first consistency domain) to block cellular modem memory transactions of the second sub-domain during a synchronization operation associated with the consistency domain identifier156A.

Subsequent cellular modem memory transactions associated with both the first device and the second device are blocked by a synchronization operation associated with the consistency domain identifier156A indicating the first consistency domain. When memory transactions of a sub-domain are to be blocked, a synchronization operation associated with a consistency domain identifier indicating the sub-domain (and not the entire domain) can be used. For example, a synchronization operation associated with a consistency domain identifier156A (e.g., decimal 1 to 63) corresponding to the first sub-domain blocks subsequent memory transactions of the first sub-domain while not blocking memory transactions of the second sub-domain. As another example, a synchronization operation associated with a consistency domain identifier156A (e.g., decimal 64 to 127) corresponding to the second sub-domain blocks subsequent memory transactions of the second sub-domain while not blocking memory transactions of the first sub-domain.

Referring toFIG.3, an example of capacity domain configuration data302is shown, along with multiple sets of capacity domain identifiers322-328based on the capacity domain configuration data302. In a particular aspect, the capacity domain configuration data302is included in the configuration data146ofFIG.1. The capacity domain configuration data302can be implemented as a collection of bits (e.g., a bitmask) in which “1” values designate which bits are compared when determining whether two or more capacity domain identifiers158“match” each other, as described further below.

In some aspects, a second set of bits (e.g., bit0to bit5) of the cache control register154can be used to indicate a capacity domain identifier158assigned to the software thread152. In some implementations, the second set of bits (e.g., bit0to bit5) of cache control registers154indicate multiple sets of capacity domain identifiers that can be used to define domains or sub-domains of capacity domain identifiers. The capacity domain configuration data302indicates bits of the cache control registers154that are implemented for indicating sets of capacity domain identifiers. To illustrate, capacity domain configuration data302indicates that a second subset (e.g., bit4to bit5) of the second set of bits (e.g., bit0to bit5) of cache control registers154is implemented for indicating sets of capacity domain identifiers. For example, the second subset (e.g., bit4to bit5) of a capacity domain identifier158indicates a set of capacity domain identifiers that includes the capacity domain identifier158.

In a particular aspect, a count of bits (e.g., 2) of the second subset indicates a count of sets of capacity domain identifiers (e.g., 2(count of bits)or 4 sets) that are supported. For example, bit values312of the second subset (e.g., a value of 0 for each of bit5and bit4) indicate a set of capacity domain identifiers322(e.g., binary 000000 to 001111 or decimal 0 to 15). Bit values314of the second subset (e.g., a value of 0 for bit5and a value of 1 for bit4) indicate a set of capacity domain identifiers324(e.g., binary 010000 to 011111 or decimal 16 to 31). Bit values316of the second subset (e.g., a value of 1 for bit5and a value of 0 for bit4) indicate a set of capacity domain identifiers326(e.g., binary 100000 to 101111 or decimal 32 to 47). Bit values318of the second subset (e.g., a value of 1 for each of bit5and bit4) indicate a set of capacity domain identifiers328(e.g., binary 110000 to 111111 or decimal 48 to 63). The second subset including 2 bits that can support four sets of capacity domain identifiers is provided as an illustrative example. In other examples, the second subset can include any count of bits that support a corresponding count of sets of capacity domain identifiers. The second subset (e.g., bit4to bit5) of a capacity domain identifier158including the same count (e.g.,2) of bits as included in the first subset (e.g., bit14to bit15) of a consistency domain identifier156is provided as an illustrative example. In other examples, the second subset can include fewer or more bits than included in the first subset. The capacity domain identifiers are used to enforce resource utilization limits, whereas the consistency domain identifiers are used to enforce synchronization.

In some implementations, each set of capacity domain identifiers corresponds to a respective capacity domain. In these implementations, two or more capacity domain identifiers “match” each other if they have the same bit values for the second subset (e.g., bit4to bit5). For example, the capacity domain identifier158A matches the capacity domain identifier158B if each of the capacity domain identifier158A and the capacity domain identifier158B has the same bit values of the second subset (e.g., bit4to bit5). To illustrate, the capacity domain identifier158A matches the capacity domain identifier158B if both of the capacity domain identifier158A and the capacity domain identifier158B are included in the same one of the set of capacity domain identifiers322(e.g., decimal 0 to 15), the set of capacity domain identifiers324(e.g., decimal 16 to 31), the set of capacity domain identifiers326(e.g., decimal 32 to 47), or the set of capacity domain identifiers328(e.g., decimal 48 to 63).

In an example in which the capacity domain identifier158A has a first value “4” and the capacity domain identifier158B has a second value “6,” the capacity domain identifier158A having the first value (e.g., decimal 4) included in the set of capacity domain identifiers322(e.g., decimal 0 to 15) matches the capacity domain identifier158B having the second value (e.g., decimal 6) that is also included in the set of capacity domain identifiers322. In an example in which the capacity domain identifier158A has a first value “4” and the capacity domain identifier158B has a second value “18,” the capacity domain identifier158A having the first value (e.g., decimal 4) included in the set of capacity domain identifiers322(e.g., decimal 0 to 15) does not match the capacity domain identifier158B having the second value (e.g., decimal 18) that is not included in the set of capacity domain identifiers322.

In some implementations, one or more of the capacity domains can include multiple sets of domain identifiers. For example, a first capacity domain includes the set of capacity domain identifiers322(e.g., decimal 0 to 15) and the set of capacity domain identifiers324(e.g., decimal 16 to 31). A second capacity domain includes the set of capacity domain identifiers326(e.g., decimal 32 to 47) and the set of capacity domain identifiers328(e.g., decimal 48 to 63). In this example, the first capacity domain corresponds to a value of 0 for bit5, and the second capacity domain corresponds to a value of 1 for bit5. In some implementations, a capacity domain identifier158A (e.g., decimal 3) included in the first capacity domain (e.g., decimal 0 to 31) matches a capacity domain identifier158B (e.g., decimal 17) included in the first capacity domain. However, a capacity domain identifier158A (e.g., decimal 3) included in the first capacity domain (e.g., decimal 0 to 31) does not match a capacity domain identifier158B (e.g.,41) that is not included in the first capacity domain.

In some aspects, the capacity domain manager144assigns capacity domain identifiers from the first capacity domain (e.g., decimal 0 to 31) to software threads152associated with a first thread type, and assigns domain identifiers from the second capacity domain (e.g., decimal 32 to 63) to software threads152associated with a second thread type. For example, the first thread type is associated with cellular modem traffic and the second thread type is associated with wireless local-area network (WLAN) traffic. Assigning capacity domain identifiers from the first capacity domain (e.g., decimal 0 to 31) to software threads152associated with cellular modem traffic, and assigning capacity domain identifiers from the second capacity domain (e.g., decimal 32 to 63) to software threads152associated with the WLAN traffic enables separate capacity limits for cellular modem traffic and WLAN traffic. For example, cellular modem memory transactions are not blocked by too many WLAN memory transactions, and vice versa.

In some implementations, a capacity domain can be divided into sub-domains. For example, the first capacity domain can include a first sub-domain including the set of capacity domain identifiers322(e.g., decimal 0 to 15) and a second sub-domain including the set of capacity domain identifiers324(e.g., decimal 16 to 31). In some aspects, the second capacity domain includes the set of capacity domain identifiers326(e.g., 32 to 47) and the set of capacity domain identifiers328(e.g., 48 to 63) that are not divided into sub-domains.

In some implementations, a capacity domain identifier158A (e.g., decimal 3) included in the first sub-domain (e.g., decimal 0 to 15) matches a capacity domain identifier158B (e.g., decimal 6) included in the first sub-domain. However, a capacity domain identifier158A (e.g., decimal 3) included in the first sub-domain (e.g., decimal 0 to 15) does not match a capacity domain identifier158B (e.g., decimal 17) that is not included in the first sub-domain. For example, a capacity domain identifier158A included in the first sub-domain (e.g., decimal 0 to 15) of the first capacity domain does not match a capacity domain identifier158B included in a second sub-domain (e.g., decimal 16 to 31) of the first capacity domain.

In some aspects, the capacity domain manager144assigns capacity domain identifiers158from the first sub-domain (e.g., decimal 0 to 15) to software threads152associated with a first thread sub-type of the first thread type, and assigns capacity domain identifiers158from the second sub-domain (e.g., decimal 16 to 31) to software threads152associated with a second thread sub-type of the first thread type. For example, the first thread sub-type is associated with cellular modem traffic of a first device, and the second thread sub-type is associated with cellular modem traffic of a second device.

Assigning capacity domain identifiers158from the first sub-domain (e.g., decimal 0 to 15) to software threads152associated with the cellular modem traffic of the first device, and assigning capacity domain identifiers from the second sub-domain (e.g., decimal 16 to 31) to software threads152associated with cellular modem traffic of the second device enables separate capacity limits for cellular modem traffic of the first device and cellular modem traffic of the second device. For example, cellular modem memory transactions of the first device are not blocked by too many cellular modem memory transactions of the second device, and vice versa. Thus, in some implementations, matching is determined at the sub-domain level rather than at the domain level.

In some implementation, matching can be determined at the domain level or at the sub-domain level. For example, a particular value (e.g., 0) of a capacity domain identifier158A can be used to indicate an entire domain as compared to one of the sub-domains. In some aspects, the particular value (e.g., 0) is reserved to indicate the entire domain and is not included in any sub-domain. In a particular example, a capacity domain identifier158A (e.g., decimal 0) is used to indicate a first capacity domain that includes a first sub-domain (e.g., decimal 1 to 15) and a second sub-domain (e.g., decimal 16 to 31). For example, a capacity domain identifier158B (e.g., decimal 1 to 15 of the first sub-domain) matches the capacity domain identifier158A (e.g., decimal 0 indicating the first capacity domain). As another example, a capacity domain identifier158B (e.g., decimal 16 to 31 of the second sub-domain) also matches the capacity domain identifier158A (e.g., decimal 0 indicating the first capacity domain).

In some examples, the first capacity domain is associated with a domain threshold count (e.g., 8), the first sub-domain is associated with a first sub-domain threshold count (e.g., 5), and the second sub-domain is associated with a second sub-domain threshold count (e.g., 5). For example, the first sub-domain traffic is limited if either the capacity limit of the first sub-domain is reach or the capacity limit of the first capacity domain is reached. To illustrate, the first sub-domain traffic can be limited when a count of pending memory accesses associated with the first capacity domain (e.g., 3 first sub-domain pending memory accesses and 5 second sub-domain memory accesses) is equal to the domain threshold count (e.g., 8) although a count (e.g., 3) of pending memory accesses associated with the first sub-domain is less than the first sub-domain threshold count (e.g., 5). In some implementations, when a domain threshold count is different from a sum of sub-domain threshold counts, a sub-domain threshold corresponds to a maximum capacity limit for the sub-domain instead of a guaranteed capacity limit.

FIGS.4A-4Cillustrate examples of updating the cache172responsive to a write instruction from a software thread152A.FIG.5illustrates an example of updating the transaction tracker160to indicate a pending store associated with a consistency domain identifier156A of the software thread152A. For example, the pending store ofFIG.5can be associated with data in the cache172that is updated responsive to the write instruction in the examples ofFIGS.4A-4C.

Referring toFIG.4A, in an example400, a software thread152A sends a write instruction440indicating an opcode442, an address444, and data446. The opcode442(e.g., an identifier) indicates that the write instruction440corresponds to a memory write instruction.

The write instruction440indicates that the data446is to be written to the address444of the memory120. The memory manager140ofFIG.1, in response to receiving the write instruction440indicating the address444and determining that data associated with the address444is not available in the cache172, initiates a load452of data from the address444of the memory120. In some aspects, the memory manager140initiates the load452in response to determining that the consistency domain manager142indicates that the consistency domain identifier156A does not match any consistency domain identifier associated with a pending synchronization operation, as further described with reference toFIGS.5-8, and that the capacity domain manager144indicates that the capacity domain identifier158A does not match any capacity domain identifier that has a count of pending memory accesses that have reached a corresponding threshold count, as further described with reference toFIGS.16-17.

In an example490ofFIG.4B, data448stored at the address444is received via the interface174from the memory120and stored in a portion460of the cache172. For example, the memory manager140receives the data448and stores the data448in the portion460.

In some implementations, the memory manager140also updates metadata of the portion460to indicate the software thread152A and the address444. For example, the metadata indicates that the portion460includes data associated with the address444and is associated with a memory access of the software thread152A. In some implementations, the metadata includes a dirty bit, and the memory manager140updates the metadata to set the dirty bit to a first value (e.g., 0) to indicate that the portion460includes data read from the memory120that has not been updated in the cache172.

In an example492ofFIG.4C, the memory manager140replaces (e.g., overwrites) the data448with the data446of the write instruction440. In some implementations, the memory manager140updates the dirty bit to a second value (e.g., 1) to indicate that the portion460includes data that has been updated in the cache172.

The write instruction440is provided as an example of a memory access instruction of the software thread152A. A read instruction can be another example of a memory access instruction of the software thread152A. The read instruction can include an opcode and an address. The memory manager140, in response to receiving the read instruction of the software thread152A, loads the data from the address of the memory120to a portion of the cache172and sets a dirty bit (e.g., metadata) of the portion to a first value (e.g., 0) to indicate that the portion stores data that is retrieved from the memory120and that has not been updated in the cache172.

Referring toFIG.5, a system500operable to manage memory transactions is disclosed. In a particular aspect, the system100ofFIG.1may include one or more components of the system500.

The transaction tracker160includes a transaction tracking scoreboard562that is configured to track one or more pending stores associated with the one or more consistency domain identifiers156. The transaction tracking scoreboard562includes a plurality of entries564, such as an entry564A, one or more additional entries, an entry564N, or a combination thereof. Each of the plurality of entries564includes a tag field572, a valid indicator field574, an eviction indicator field576, a domain identifier field578, and an address field580.

The tag field572of an entry564indicates an identifier of the entry564. For example, a tag field572A of the entry564A includes an identifier (e.g., A) of the entry564A. As another example, a tag field572N of the entry564N includes an identifier (e.g., N) of the entry564N.

The eviction indicator field576of an entry564is used to indicate a pending eviction to an address indicated by the address field580. For example, a first value (e.g., 0) of the eviction indicator field576indicates no pending eviction, whereas a second value (e.g., 1) of the eviction indicator field576indicates a pending eviction.

The domain identifier field578of an entry564is used to indicate one or more consistency domain identifiers156associated with the entry564. In some aspects, the consistency domain number of transactions data162corresponds to a count of pending transactions associated with a consistency domain identifier156. The count of pending transactions can be determined based on a count of entries564including valid data (e.g., as indicated by the valid indicator field574) that are associated with the consistency domain identifier156(e.g., as indicated by the domain identifier field578).

The software thread152A issues a commit542subsequent to the write instruction440of the example400ofFIG.4A. In a particular aspect, the consistency domain manager142, in response to determining that the portion460of the cache172includes data associated with the software thread152A (e.g., as indicated by metadata) and that the portion460includes updated data (e.g., as indicated by a dirty bit), determines that a store corresponding to the software thread152A and associated with the portion460is being committed. Alternatively, if a second portion of the cache172includes data associated with the software thread152A that has not been updated in the cache172(e.g., as indicated by the dirty bit), the consistency domain manager142determines that no store associated with the second portion (e.g., corresponding to a read instruction) is being committed.

The consistency domain manager142, in response to a store corresponding to the software thread152A and associated with the portion460being committed, updates an entry564A to indicate a pending store operation associated with the portion460. For example, the consistency domain manager142updates the address field580A to indicate the address444associated with the portion460. The consistency domain manager142updates the domain identifier field578A to indicate the consistency domain identifier156A (e.g., 0) assigned to the software thread152A that is associated with the portion460. The consistency domain manager142sets the eviction indicator field576A to a first value (e.g., 0) to indicate no pending eviction. The consistency domain manager142updates the valid indicator field574A to a second value (e.g., 1) to indicate that the entry564A includes valid data.

The consistency domain manager142, subsequent to updating the entry564A, initiates a store of the data446to the address444. For example, the consistency domain manager142causes the data446to be provided via the interface174to the memory120for storage at the address444.

The transaction tracking scoreboard562indicates the consistency domain number of transactions data162. For example, the consistency domain number of transactions data162indicates counts584of pending stores associated with consistency domain identifiers156. In some implementations, the consistency domain manager142increments (e.g., by 1) a count584A of pending stores associated with the consistency domain identifier156A concurrently with updating the entry564A, initiating the store of the data446, or both. In some implementations, the count584A is indicated by a count of valid entries (e.g., as indicated by the valid indicator field574) of the transaction tracking scoreboard562that are associated with the consistency domain identifier156A (e.g., as indicated by the domain identifier field578).

Operations that may be performed in the event of a synchronization operation are described with reference to a system600ofFIG.6, a system700ofFIG.7, and a system800ofFIG.8. Each of the system600, the system700, and the system800is operable to manage memory transactions and may include one or more components that are included in the system100ofFIG.1. In particular,FIG.6illustrates an example of initiation of a synchronization operation of the software thread152A,FIG.7illustrates examples of receiving access instructions during the synchronization operation, andFIG.8illustrates an example of completing the pending store and the synchronization operation.

InFIG.6, the consistency domain manager142includes or has access to synchronization data650indicating whether a synchronization operation associated with the one or more consistency domain identifiers156is pending. For example, the synchronization data650includes a synchronization indicator654for each of the one or more consistency domain identifiers156. To illustrate, the synchronization data650includes a synchronization indicator654A and a synchronization indicator654B for the consistency domain identifier156A and the consistency domain identifier156B, respectively. Each of the one or more synchronization indicators654is initialized to a first value (e.g., 0) to indicate that no pending synchronization operation is associated with the corresponding consistency domain identifier156.

The software thread152A initiates a synchronization operation by issuing a synchronization instruction644. In some implementations, the synchronization instruction644corresponds to a barrier instruction or a store-release load-acquire instruction. The consistency domain manager142, in response to receiving the synchronization instruction644of the software thread152A and determining that domain identifier data150indicates that the software thread152A is assigned to the consistency domain identifier156A, updates a synchronization indicator654A associated with the consistency domain identifier156A to a second value (e.g., 1) to indicate a pending synchronization operation associated with the consistency domain identifier156A.

In some implementations, the consistency domain manager142selectively updates the synchronization indicator654A based on a count of pending stores that match the consistency domain identifier156A. For example, the count of pending stores that match the consistency domain identifier156A corresponds to a count of valid entries, such as the entry564A, of the transaction tracking scoreboard562having a domain identifier field578indicating one or more consistency domain identifiers156that match the consistency domain identifier156A. To illustrate, the consistency domain identifier156A matches itself and the count of pending stores is based on the count584A associated with the consistency domain identifier156A. In an example, another consistency domain identifier (e.g., the consistency domain identifier156B) also matches the consistency domain identifier156A, as described with reference toFIG.2, and the count of pending stores that match the consistency domain identifier156A is also based on a count584B of pending stores associated with the consistency domain identifier156B. In this example, the count of pending stores that match the consistency domain identifier156A is based on a sum of the count584A and the count584B.

In some implementations, the consistency domain manager142, in response to determining that the count of pending stores that match the consistency domain identifier156A is greater than zero, updates a synchronization indicator654A associated with the consistency domain identifier156A to a second value (e.g., 1) to indicate a pending synchronization operation associated with the consistency domain identifier156A. The synchronization indicator654A is thus set based on the consistency domain number of transactions data162to control operation of the one or more components170, as further described with reference toFIGS.7-8.

InFIG.7, the consistency domain manager142receives an access instruction744(e.g., a read instruction or a write instruction) of the software thread152A. The consistency domain manager142, in response to determining that the software thread152A is assigned the consistency domain identifier156A (e.g., as indicated by the domain identifier data150) and that the synchronization data650indicates that a pending synchronization operation is associated with the consistency domain identifier156A, refrains from performing the access instruction744. Controlling operation of the one or more components170includes refraining from performing the access instruction744. In some aspects, refraining from performing the access instruction744includes adding the access instruction744of the software thread152A to an instruction buffer750with a corresponding ready flag set to a first value (e.g., 0) to indicate that the access instruction744is not ready to be performed.

In a particular example, the consistency domain manager142receives an access instruction746from the software thread152B, and determines that the consistency domain identifier156B is assigned to the software thread152B (e.g., as indicated by the domain identifier data150). The consistency domain manager142, in response to determining that the synchronization data650indicates that the consistency domain identifier156A has a pending synchronization operation, determines whether the consistency domain identifier156B matches the consistency domain identifier156A, as described with reference toFIG.2.

The consistency domain manager142, in response to determining that the consistency domain identifier156B matches the consistency domain identifier156A, refrains from performing the access instruction746. Controlling operation of the one or more components170includes refraining from performing the access instruction746. In some aspects, refraining from performing the access instruction746includes adding the access instruction746of the software thread152B to the instruction buffer750with a corresponding ready flag set to a first value (e.g., 0) to indicate that the access instruction746is not ready to be performed. Alternatively, the consistency domain manager142, in response to determining that the consistency domain identifier156B does not match any consistency domain identifier associated with a pending synchronization operation, initiates performance of the access instruction746or adds the access instruction746to the instruction buffer750with a corresponding ready flag set to a second value (e.g., 1) indicating that the access instruction746is ready to be performed.

The consistency domain manager142thus refrains from performing access instructions associated with consistency domain identifiers that match the consistency domain identifier156A during a synchronization operation of the consistency domain identifier156A. However, performance of access instructions associated with consistency domain identifiers that do not match the consistency domain identifier156A is not blocked by the synchronization operation of the software thread152A.

InFIG.8, the memory120issues an acknowledgement (ack.)844indicating that storage of data to the address444is complete. The consistency domain manager142, in response to receiving the acknowledgement844, determines a consistency domain identifier associated with the address444and updates the transaction tracking scoreboard562to indicate that there is no pending store associated with the address444. For example, the consistency domain manager142determines that the entry564A is valid (e.g., as indicated by the valid indicator field574A) and indicates that the address444(e.g., as indicated by the address field580A) is associated with the consistency domain identifier156A (e.g., as indicated by the domain identifier field578A). The consistency domain manager142updates the valid indicator field574A of the entry564A to a first value (e.g., 0) to indicate that the entry564A is invalid and that there is no pending store associated with the address444. In some implementations, the consistency domain manager142decrements (e.g., by 1) the count584A corresponding to the consistency domain identifier156A that is associated with the address444.

The consistency domain manager142, in response to determining that the synchronization data650indicates a pending synchronization operation associated with the consistency domain identifier156A (e.g., corresponding to the address444indicated by the acknowledgement844), determines whether the transaction tracking scoreboard562indicates any remaining pending store operations that match the consistency domain identifier156A. For example, the consistency domain manager142determines the count of pending stores that match the consistency domain identifier156A based on the count584A associated with the consistency domain identifier156A. In some examples, another consistency domain identifier (e.g., the consistency domain identifier156B) matches the consistency domain identifier156A. In these examples, the consistency domain manager142determines the count of pending stores that match the consistency domain identifier156A also based on the count584B. For example, the count of pending stores that match the consistency domain identifier156A is based on a sum of counts associated with consistency domain identifiers that match the consistency domain identifier156A. The consistency domain manager142, in response to determining that the count of pending stores that match the consistency domain identifier156A is zero, updates the synchronization indicator654A to a first value (e.g., 0) to indicate that the synchronization operation associated with the consistency domain identifier156A is complete.

In a particular aspect, the consistency domain manager142, in response to determining that the synchronization operation associated with the consistency domain identifier156A is complete, designates one or more instructions in the instruction buffer750as ready to be performed. For example, the consistency domain manager142determines that the access instruction744included in the instruction buffer750is designated as not ready to be performed (e.g., as indicated by a ready flag). The consistency domain manager142determines that the access instruction744is associated with the software thread152A that is assigned the consistency domain identifier156A (e.g., as indicated by the domain identifier data150). The consistency domain manager142, in response to determining that the consistency domain identifier156A does not match any consistency domain identifiers associated with a pending synchronization operation (e.g., as indicated by the synchronization data650), designates the access instruction744as ready to be performed by setting the ready flag to a second value (e.g., 1). Similarly, in another example, the consistency domain manager142designates the access instruction746as ready to perform in response to determining that the consistency domain identifier156B does not match any consistency domain identifiers associated with a pending synchronization operation.

The consistency domain manager142, in response to receiving the synchronization instruction644of the software thread152A, controls operation of the one or more components170ofFIG.1based on the number (e.g., count) of pending stores that match the consistency domain identifier156A. Controlling operation of the one or more components170includes completing any pending stores that match the consistency domain identifier156A prior to performing any subsequent data access instruction associated with any consistency domain identifier that matches the consistency domain identifier156A.

Operations that may be performed in the event of a capacity eviction are described with reference to a system900ofFIG.9, an example1000ofFIG.10A, an example1090ofFIG.10B, and a system1100ofFIG.11. Each of the system900and the system1100is operable to manage memory transactions and may include one or more components that are included in the system100ofFIG.1. In particular,FIG.9illustrates an example of initiation of a capacity eviction of updated data from a portion of the cache172in response to a second memory access instruction,FIGS.10A and10Billustrate loading data corresponding to the second memory access instruction to the portion of the cache, andFIG.11illustrates an example of completing the capacity eviction in response to an acknowledgement that a store of the updated data is completed.

InFIG.9, the portion460of the cache172includes the data446of the software thread152A that is updated in the cache172(e.g., as indicated by a dirty bit) and is associated with the address444, as described with reference toFIG.4C. The software thread152B issues an access instruction946(e.g., a memory read instruction or a memory write instruction) indicating at least an opcode942and an address944. For example, the opcode942includes an identifier of the access instruction946. In a particular aspect, the access instruction946corresponds to a memory write instruction and also indicates data to be written to the address944.

The consistency domain manager142, in response to receiving the access instruction946, determining that data corresponding to the address944is not available in the cache172, and determining that the cache172is full, uses various cache eviction strategies (e.g., least recently accessed) to select the portion460of the cache172to store data corresponding to the address944. If the selected portion (e.g., the portion460) includes data that has not been updated in the cache172(e.g., as indicated by the dirty bit), the selected portion can be overwritten without an eviction. Alternatively, the consistency domain manager142, in response to determining that the selected portion (e.g., the portion460) includes data that has been updated in the cache172(e.g., as indicated by the dirty bit), initiates an eviction of the data446stored in the portion460.

Initiating the eviction of the data446associated with the address444includes updating an available entry564(e.g., an invalid entry as indicated by the valid indicator field574) of the transaction tracking scoreboard562and initiating a store of the data446to the address444of the memory120. For example, the consistency domain manager142sets the address field580A of the entry564A to indicate the address444associated with the portion460. The consistency domain manager142sets the eviction indicator field576A to a second value (e.g., 1) to indicate a pending eviction. The consistency domain manager142sets the domain identifier field578A of the entry564A to indicate the consistency domain identifier156A assigned to the software thread152A that is associated with the portion460. In some implementations, a pending eviction corresponds to a pending store associated with the consistency domain identifier156A for a synchronization operation. For example, in some implementations, the consistency domain manager142updates (e.g., increments by 1) the count584A corresponding to the consistency domain identifier156A assigned to the software thread152A. The consistency domain manager142sets the valid indicator field574A to a second value (e.g., 1) to indicate that the entry564A corresponds to a valid entry.

The consistency domain manager142initiates a store of the data446by causing the data446to be sent via the interface174to be written to the address444of the memory120. The data from the address944is loaded to the portion460subsequent to the initiation of the store of the data446. In the example1000ofFIG.10A, the consistency domain manager142initiates a load1042of data from the address944of the memory120.

In the example1090ofFIG.10B, data1048stored at the address944is received via the interface174from the memory120and stored in the portion460of the cache172. For example, the consistency domain manager142receives a notification that the data1048is stored in the portion460.

In some implementations, the consistency domain manager142also updates metadata of the portion460to indicate the software thread152B (associated with the access instruction946) and the address944. For example, the metadata indicates that the portion460includes data associated with the address944and is associated with a memory access of the software thread152B. In some implementations, the metadata includes a dirty bit, and the memory manager140updates the metadata to set the dirty bit to a first value (e.g., 0) to indicate that the portion460includes data read from the memory120that has not been updated in the cache172.

If the access instruction946corresponds to a write instruction and indicates updated data to be written to the address944, the data1048is replaced (e.g., overwritten) with the updated data, and the metadata is updated to set the dirty bit to a second value (e.g., 1) to indicate that the portion460includes data that has been updated in the cache172.

InFIG.11, the memory120issues an acknowledgement (ack.)1144indicating that storage of data to the address444is complete. The consistency domain manager142, in response to receiving the acknowledgement1144, determining that the entry564A is valid (e.g., as indicated by the valid indicator field574A), and determining that the entry564A is associated with the address444(e.g., as indicated by the address field580A), updates the valid indicator field574A to a first value (e.g., 0) to indicate that the entry564A is invalid and that the pending eviction is completed. In some implementations, the consistency domain manager142, in response to receiving the acknowledgement1144and prior to setting the valid indicator field574A to the first value (e.g., 0), updates (e.g., decrements by 1) the count584A corresponding to the consistency domain identifier156A associated with the address444(e.g., as indicated by the domain identifier field578A).

Operations that may be performed in the event of a cache operation hit are described with reference to a system1200ofFIG.12and a system1300ofFIG.13. Each of the system1200and the system1300is operable to manage memory transactions and may include one or more components that are included in the system100ofFIG.1. In particular,FIG.12andFIG.13illustrate an example of initiation of a cache operation that corresponds to a hit in the cache172and an example of completing the cache operation, respectively.

InFIG.12, the portion460of the cache172includes the data446of the software thread152A that is updated in the cache172(e.g., as indicated by a dirty bit) and is associated with the address444, as described with reference toFIG.4C. The software thread152B initiates a cache operation1246(e.g., a clean cache line operation or a clean and invalidate cache line operation) indicating an opcode1242and the address444. For example, the opcode1242includes an identifier of the cache operation1246. The cache operation1246is associated with the consistency domain identifier156B assigned to the software thread152B (e.g., as indicated by the domain identifier data150).

The consistency domain manager142detects a cache hit in response to determining that the portion460of the cache172includes the data446associated with the address444indicated by the cache operation1246. The consistency domain manager142, in response to detecting the cache hit, initiates an eviction of the data446and updates the cache172to indicate that the portion460of the cache172is available (e.g., includes invalid data).

Initiating the eviction of the data446associated with the address444includes performing one or more operations described with reference toFIG.9. For example, the consistency domain manager142updates an available entry564(e.g., an invalid entry) of the transaction tracking scoreboard562and initiates a store of the data446to the address444of the memory120. To illustrate, the consistency domain manager142sets the address field580A of the entry564A to indicate the address444associated with the portion460. The consistency domain manager142sets the eviction indicator field576A to a second value (e.g., 1) to indicate a pending eviction. The consistency domain manager142sets the domain identifier field578A of the entry564A to indicate the consistency domain identifier156A (e.g., 0) assigned to the software thread152A that is associated with the portion460.

In some implementations, initiating the eviction of the data446includes setting the domain identifier field578A to also indicate the consistency domain identifier156B (e.g., 1) assigned to the software thread152B associated with the cache operation1246(illustrated as the domain identifier field578A including a 0 value representing the consistency domain identifier156A assigned to the software thread152A and also including a 1 value representing the consistency domain identifier156B assigned to the software thread152B).

In some aspects, a pending eviction due to a cache hit operation corresponds to a pending store operation associated with the consistency domain identifier156A and with the consistency domain identifier156B. For example, in some implementations, the consistency domain manager142updates (e.g., increments by 1) the count584A corresponding to the consistency domain identifier156A and the count584B corresponding to the consistency domain identifier156B. The consistency domain manager142sets the valid indicator field574A to a second value (e.g., 1) to indicate that the entry564A corresponds to a valid entry. The consistency domain manager142initiates a store of the data446by sending the data446via the interface174to be written to the address444of the memory120.

InFIG.13, the memory120issues an acknowledgement (ack.)1344indicating that storage of data to the address444is complete. The consistency domain manager142, in response to receiving the acknowledgement1344, determining that the entry564A is valid (e.g., as indicated by the valid indicator field574A), and determining that the entry564A is associated with the address444(e.g., as indicated by the address field580A), updates the valid indicator field574A to a first value (e.g., 0) to indicate that the entry564A is invalid and that the pending eviction is completed.

In some implementations, the consistency domain manager142, in response to receiving the acknowledgement1344and prior to setting the valid indicator field574A to the first value (e.g., 0), updates (e.g., decrements by 1) the count584A and the count584B corresponding to the consistency domain identifier156A and the consistency domain identifier156B, respectively, that are associated with the address444(e.g., as indicated by the domain identifier field578A).

Operations that may be performed in the event of a cache operation miss are described with reference to a system1400ofFIG.14and a system1500ofFIG.15. Each of the system1400and the system1500is operable to manage memory transactions and may include one or more components that are included in the system100ofFIG.1. In particular,FIG.14illustrates an example of initiation of a cache operation that corresponds to a miss in the cache172, andFIG.15illustrates an example of completing the cache operation.

InFIG.14, the entry564A of the transaction tracking scoreboard562indicates a pending eviction associated with the address444. In a particular aspect, the pending eviction corresponds to a capacity eviction, as described with reference toFIG.9. In another aspect, the pending eviction corresponds to a cache operation hit, as described with reference toFIG.12.

The software thread152B initiates the cache operation1246(e.g., a clean cache line operation or a clean and invalidate cache line operation) indicating the opcode1242and the address444. The cache operation1246is associated with the consistency domain identifier156B assigned to the software thread152B (e.g., as indicated by the domain identifier data150).

The consistency domain manager142detects a cache miss in response to determining that no valid data associated with the address444is stored in the cache172. The consistency domain manager142, in response to detecting the cache miss, assigns the consistency domain identifier156B associated with the cache operation1246to any pending evictions associated with the address444. For example, the consistency domain manager142, in response to determining that the entry564A is valid (e.g., as indicated by the valid indicator field574A) and corresponds to a pending eviction (e.g., as indicated by the eviction indicator field576A) associated with the address444(e.g., as indicated by the address field580A), updates the domain identifier field578A of the entry564A to also indicate the consistency domain identifier156B.

In a particular aspect, the pending eviction indicated by the entry564A corresponds to a pending store operation associated with the consistency domain identifier156B in addition to any other consistency domain identifiers indicated by the domain identifier field578A. For example, in some implementations, the consistency domain manager142updates (e.g., increments by 1) the count584A corresponding to the consistency domain identifier156A and another count (e.g., the count584B) corresponding to another consistency domain identifier (e.g., the consistency domain identifier156B) indicated by the domain identifier field578A.

InFIG.15, the memory120issues an acknowledgement (ack.)1544indicating that storage of data to the address444is complete. The consistency domain manager142, in response to receiving the acknowledgement1544, determining that the entry564A is valid (e.g., as indicated by the valid indicator field574A), and determining that the entry564A is associated with the address444(e.g., as indicated by the address field580A), updates the valid indicator field574A to a first value (e.g., 0) to indicate that the entry564A is invalid and that the pending eviction is completed.

In some implementations, the consistency domain manager142, in response to receiving the acknowledgement1544and prior to setting the valid indicator field574A to the first value (e.g., 0), updates (e.g., decrements by 1) the count584A corresponding to the consistency domain identifier156A that is associated with the address444(e.g., as indicated by the domain identifier field578A). In addition, the consistency domain manager142, in response to receiving the acknowledgement1544and prior to setting the valid indicator field574A to the first value (e.g., 0), also updates (e.g., decrements by 1) the count (e.g., the count584B) corresponding to any other consistency domain identifier (e.g., the consistency domain identifier156B) that is associated with the address444(e.g., as indicated by the domain identifier field578A).

Operations that may be performed that account for capacity domains are described with reference to a system1600ofFIG.16and a system1700ofFIG.17. Each of the system1600and the system1700is operable to manage memory transactions and may include one or more components that are included in the system100ofFIG.1. In particular,FIG.16illustrates an example of updating a count of pending memory access instructions corresponding to a capacity domain identifier responsive to a read instruction, andFIG.17illustrates an example of updating a count of pending memory access instructions corresponding to a capacity domain identifier responsive to a write instruction.

InFIG.16, the transaction tracker160includes the capacity domain number of transactions data164that indicates capacity thresholds1676associated with the capacity domain identifiers158. For example, the capacity domain number of transactions data164indicates that the capacity domain identifier158A is associated with a capacity threshold1676A, the capacity domain identifier158B is associated with a capacity threshold1676B, and so on. The capacity threshold1676B may be the same as or distinct from the capacity threshold1676A. In a particular aspect, the capacity thresholds1676are based on a configuration setting, user input, default data, or a combination thereof.

The capacity domain manager144is configured to use the capacity domain number of transactions data164to track counts1674of pending memory access instructions associated with the capacity domain identifiers158. The software thread152A issues a read instruction1640. The capacity domain manager144selectively enables the read instruction1640based on the counts1674. In some aspects, the capacity domain manager144determines whether a capacity limit associated with any capacity domain identifier that matches the capacity domain identifier158A (that is assigned to the software thread152A) has been reached. For example, the capacity domain identifier158A is a match for itself and the capacity domain manager144, in response to determining that the count1674A associated with the capacity domain identifier158A is greater than or equal to the capacity threshold1676A associated with the capacity domain identifier158A, determines that a capacity limit associated with the capacity domain identifier158A has been reached. In some examples, another capacity domain identifier (e.g., the capacity domain identifier158B) that is not the same as the capacity domain identifier158A can also match the capacity domain identifier158A, as described with reference toFIG.3. The capacity domain manager144, in response to determining that the count1674B associated with the capacity domain identifier158B is greater than or equal to the capacity threshold1676B associated with the capacity domain identifier158B, determines that a capacity limit associated with the capacity domain identifier158B has been reached.

The capacity domain manager144disables the read instruction1640in response to determining that a capacity limit has been reached for at least one capacity domain identifier that matches the capacity domain identifier158A. In some implementations, disabling the read instruction1640includes discarding the read instruction1640. In other implementations, disabling the read instruction1640includes adding the read instruction1640to an instruction buffer to be performed when capacity is available (e.g., capacity limit has not been reached) for all capacity domain identifiers that match the capacity domain identifier158A.

The capacity domain manager144, in response to determining that capacity is available for all capacity domain identifiers that match the capacity domain identifier158A, enables the read instruction1640and updates (e.g., increments by 1) the count1674A. In some aspects, data associated with an address indicated by the read instruction1640is available in the cache172. In these aspects, enabling the read instruction1640includes providing the data from the cache172to the software thread152A.

In some aspects, data associated with the address indicated by the read instruction1640is not available in the cache172. In these aspects, enabling the read instruction1640includes initiating a memory access associated with the read instruction1640. For example, the capacity domain manager144initiates a load1642of the data from the memory120. The capacity domain manager144receives data1648(e.g., stored at the address indicated by the read instruction1640) via the interface174from the memory120. The capacity domain manager144stores the data1648in the cache172and provides the data1648from the cache172to the software thread152A.

When the software thread152A is done reading the data1648from the cache172, the software thread152A issues an acknowledgement1650indicating that the memory access associated with the read instruction1640is complete. The capacity domain manager144, in response to receiving the acknowledgement1650, updates (e.g., decrements by 1) the count1674A.

InFIG.17, the software thread152A issues a write instruction1740. The capacity domain manager144selectively enables the write instruction1740based on the counts1674. The capacity domain manager144determines whether a capacity limit associated with any capacity domain identifier that matches the capacity domain identifier158A (that is assigned to the software thread152A) has been reached, as described with reference toFIG.16.

The capacity domain manager144disables the write instruction1740in response to determining that a capacity limit has been reached for at least one capacity domain identifier that matches the capacity domain identifier158A. In some implementations, disabling the write instruction1740includes discarding the write instruction1740. In other implementations, disabling the write instruction1740includes adding the write instruction1740to an instruction buffer to be performed when capacity is available (e.g., capacity limit has not been reached) for all capacity domain identifiers that match the capacity domain identifier158A.

The capacity domain manager144, in response to determining that capacity is available for all capacity domain identifiers that match the capacity domain identifier158A, enables the write instruction1740and updates (e.g., increments by 1) the count1674A. Enabling the write instruction1740includes initiating a memory access associated with the write instruction1740. In some aspects, initiating the memory access includes initiating a store operation of data1748indicated by the write instruction1740to an address indicated by the write instruction1740. To illustrate, the capacity domain manager144provides the data1748via the interface174to the memory120. The memory120provides an acknowledgement1750indicating that the memory access (e.g., the store operation) associated with the write instruction1740is complete.

In some aspects, initiating the memory access includes storing the data1748in the cache172. In these aspects, the software thread152A may provide the acknowledgement1750indicating that the memory access (e.g., the store to the cache172) associated with the write instruction1740is complete.

The capacity domain manager144, in response to receiving the acknowledgement1750, updates (e.g., decrements by 1) the count1674A. In some implementations, the capacity domain manager144, subsequent to decrementing the count1674A, determines whether a memory access instruction stored in an instruction buffer is a candidate for enabling. For example, the capacity domain manager144, in response to determining that capacity is available for all capacity domain identifiers that match a capacity domain identifier associated with the memory access instruction, enables the memory access instruction, removes the memory access instruction from the instruction buffer, and updates (e.g., increments) a count associated with the capacity domain identifier.

The memory manager140is illustrated as not including the consistency domain manager142in addition to the capacity domain manager144inFIGS.17-18for ease of description. In some implementations, the memory manager140can include the consistency domain manager142and the capacity domain manager144. For example, the consistency domain manager142updates the transaction tracking scoreboard562concurrently with initiating the write of the data1748to the memory120and updates the transaction tracking scoreboard562in response to receiving the acknowledgement1750, as described with reference toFIGS.5-8.

It should be noted that various functions performed by the one or more processors190are described as being performed by certain components or modules. However, this division of components and modules is for illustration only. In an alternate aspect, a function described herein as performed by a particular component or module is divided amongst multiple components or modules. Moreover, in an alternate aspect, two or more components or modules of the one or more processors190are integrated into a single component or module. In a particular aspect, one or more functions described herein as performed by the device102are divided amongst multiple devices (e.g., the device102, a central server, a distributed system, or any combination thereof).

FIG.18depicts an implementation1800in which the device102includes a mobile device1802, such as a phone or tablet, as illustrative, non-limiting examples. The mobile device1802includes a display screen1804. Components of the one or more processors190, including the memory manager140, are integrated in the mobile device1802and are illustrated using dashed lines to indicate internal components that are not generally visible to a user of the mobile device1802. In a particular example, the memory manager140operates to access a memory of the mobile device1802to perform one or more operations at the mobile device1802, such as to launch a graphical user interface or otherwise display other information at the display screen1804(e.g., via an integrated “smart assistant” application).

In some aspects, the memory manager140enables memory access transactions for a consistency domain identifier to remain unaffected by synchronization operations of a non-matching consistency domain identifier. For example, memory accesses of a first application (e.g., video playback) associated with a first consistency domain identifier are not blocked by a synchronization operation of a second application (e.g., a social networking application) associated with a second consistency domain identifier that does not match the first consistency domain identifier. In some aspects, the memory manager140segregates capacity limits based on capacity domain identifiers. For example, memory accesses of the second application (e.g., the social networking application) are not blocked by too many memory accesses of the first application (e.g., video playback).

FIG.19depicts an implementation1900in which the device102includes a headset device1902. Components of the one or more processors190, including the memory manager140, are integrated in the headset device1902. In a particular example, the memory manager140operates to access a memory of the headset device1902to perform one or more operations at the headset device1902.

FIG.20depicts an implementation2000in which the device102includes a wearable electronic device2002, illustrated as a “smart watch.” The memory manager140is integrated into the wearable electronic device2002. In a particular example, the memory manager140operates to access a memory of the wearable electronic device2002to perform one or more operations at the wearable electronic device2002, such as to launch a graphical user interface or otherwise display other information associated with user's speech at a display screen2004of the wearable electronic device2002. To illustrate, the wearable electronic device2002may include a display screen that is configured to display a notification based on user speech detected by the wearable electronic device2002. In a particular example, the wearable electronic device2002includes a haptic device that provides a haptic notification (e.g., vibrates) in response to detection of user voice activity. For example, the haptic notification can cause a user to look at the wearable electronic device2002to see a displayed notification indicating detection of a keyword spoken by the user.

FIG.21is an implementation2100in which the device102includes a wireless speaker and voice activated device2102. The wireless speaker and voice activated device2102can have wireless network connectivity and is configured to execute an assistant operation. The one or more processors190including the memory manager140are included in the wireless speaker and voice activated device2102. The wireless speaker and voice activated device2102also includes a speaker2104. During operation, the memory manager140operates to access a memory of the wireless speaker and voice activated device2102to execute assistant operations, such as via execution of a voice activation system (e.g., an integrated assistant application). The assistant operations can include adjusting a temperature, playing music, turning on lights, etc. For example, the assistant operations are performed responsive to receiving a command after a keyword or key phrase (e.g., “hello assistant”).

FIG.22depicts an implementation2200in which the device102includes a portable electronic device that corresponds to a camera device2202. The memory manager140is included in the camera device2202. During operation, the memory manager140accesses a memory of the camera device2202to execute operations responsive to spoken user commands, such as to adjust image or video capture settings, image or video playback settings, or image or video capture instructions, as illustrative examples.

FIG.23depicts an implementation2300in which the device102includes a portable electronic device that corresponds to a virtual reality, mixed reality, or augmented reality headset2302. The memory manager140is integrated into the headset2302. The memory manager140operates to access a memory of the headset2302to execute operations at the headset2302. In a particular aspect, user voice activity detection can be performed based on audio signals received from one or more microphones of the headset2302. A visual interface device is positioned in front of the user's eyes to enable display of augmented reality, mixed reality, or virtual reality images or scenes to the user while the headset2302is worn. In a particular example, the visual interface device is configured to display a notification indicating user speech detected in the audio signals.

FIG.24depicts an implementation2400in which the device102corresponds to, or is integrated within, a vehicle2402, illustrated as a manned or unmanned aerial device (e.g., a package delivery drone). The memory manager140is integrated into the vehicle2402. The memory manager140operates to access a memory of the vehicle2402to execute operations at the vehicle2402. User voice activity detection can be performed based on audio signals received from the one or more microphones of the vehicle2402, such as for delivery instructions from an authorized user of the vehicle2402.

FIG.25depicts another implementation2500in which the device102corresponds to, or is integrated within, a vehicle2502, illustrated as a car. The vehicle2502includes the one or more processors190including the memory manager140. The memory manager140operates to access a memory of the vehicle2502to execute operations at the vehicle2502. User voice activity detection can be performed based on audio signals received from one or more microphones of the vehicle2502. In some implementations, user voice activity detection can be performed based on an audio signal received from interior microphones, such as for a voice command from an authorized passenger. For example, the user voice activity detection can be used to detect a voice command from an operator of the vehicle2502. In some implementations, user voice activity detection can be performed based on an audio signal received from external microphones, such as an authorized user of the vehicle. In a particular implementation, in response to receiving a verbal command identified as user speech, a voice activation system initiates one or more operations of the vehicle2502based on one or more keywords (e.g., “unlock,” “start engine,” “play music,” “display weather forecast,” or another voice command) detected in an input signal, such as by providing feedback or information via a display2520or one or more speakers.

Referring toFIG.26, a particular implementation of a method2600of memory transaction management is shown. In a particular aspect, one or more operations of the method2600are performed by at least one of the memory manager140, the one or more processors190, the device102, the system100ofFIG.1, or a combination thereof. In a particular aspect, the method2600is computer-implemented.

The method2600includes assigning distinct domain identifiers to each of multiple software threads, at2602. For example, the consistency domain manager142assigns the consistency domain identifiers156to each of the multiple software threads152, as described with reference toFIG.1. As another example, the capacity domain manager144assigns capacity domain identifiers158to each of the multiple software threads152, as described with reference toFIG.1.

The method2600also includes controlling operation of one or more components of the processor based on a number of memory transactions associated with a domain identifier, at2604. For example, the consistency domain manager142controls operations of the one or more components170of the one or more processors190based on the consistency domain number of transactions data162, as described with reference toFIG.1. As another example, the capacity domain manager144controls operations of the one or more components170of the one or more processors190based on the capacity domain number of transactions data164, as described with reference toFIG.1.

In implementations in which the domain identifiers correspond to capacity domain identifiers, the method2600can limit a count of pending memory accesses that can be associated with a capacity domain identifier to enable resources to be available for memory accesses associated with other capacity domain identifiers. To illustrate, the software thread152A is associated with a capacity domain identifier158A, as described with reference toFIG.16. Controlling the operations of the one or more components170includes refraining from initiating a memory access of the software thread152A in response to determining that a count of pending memory accesses associated with any capacity domain identifier (e.g., a capacity domain identifier158B) that matches the capacity domain identifier158A is equal to a corresponding threshold count, as described with reference toFIGS.16-17. Memory accesses associated with other capacity domain identifiers that do not match the capacity domain identifier158A are not affected by the count of pending memory accesses associated with the capacity domain identifier158A.

Alternatively, or in addition, in implementations in which the domain identifiers correspond to consistency domain identifiers, the method2600can ensure that a synchronization instruction associated with a particular consistency domain identifier does not affect (e.g., delay) memory access instructions associated with other consistency domain identifiers that do not match the particular consistency domain identifier. To illustrate, a synchronization instruction644is associated with a consistency domain identifier156A, as described with reference toFIG.6. Controlling the operations of the one or more components170includes enabling pending memory access instructions associated with any consistency domain identifier (e.g., a consistency domain identifier156B) that matches the consistency domain identifier156A to be performed (e.g., count of pending memory access instructions=0) prior to performing any subsequent memory access instructions associated with the matching consistency domain identifier (e.g., the consistency domain identifier156B), as described with reference toFIGS.6-8. The synchronization instruction644does not affect (e.g., delay) memory access instructions associated with other consistency domain identifiers that do not match the consistency domain identifier156A.

The method2600ofFIG.26may be implemented by a field-programmable gate array (FPGA) device, an application-specific integrated circuit (ASIC), a processing unit such as a central processing unit (CPU), a DSP, a GPU, a controller, another hardware device, firmware device, or any combination thereof. As an example, the method2600ofFIG.26may be performed by a processor that executes instructions, such as described with reference toFIG.27.

Referring toFIG.27, a block diagram of a particular illustrative implementation of a device2700is depicted. In various implementations, the device2700may have more or fewer components than illustrated inFIG.27. In an illustrative implementation, the device2700may correspond to the device102. In an illustrative implementation, the device2700may perform one or more operations described with reference toFIGS.1-26.

In a particular implementation, the device2700includes a processor2706(e.g., a CPU). The device2700may include one or more additional processors2710(e.g., one or more DSPs, one or more GPUs, or a combination thereof). In a particular aspect, the one or more processors190ofFIG.1corresponds to the processor2706, the processors2710, or a combination thereof. The processors2710may include a speech and music coder-decoder (CODEC)2708that includes a voice coder (“vocoder”) encoder2736, a vocoder decoder2738, or both. The processors2710may include the one or more components170, the memory manager140, the transaction tracker160, the configuration data146, the domain identifier data150, or a combination thereof.

The device2700may include a memory2786and a CODEC2734. In some implementations, the memory2786includes the memory120ofFIG.1. In other implementations, the memory120is distinct from the memory2786. The memory2786may include instructions2756, that are executable by the one or more additional processors2710(or the processor2706) to implement the functionality described with reference to the memory manager140. The device2700may include one or more modems2770coupled, via one or more transceivers2750, to one or more antennas2752.

In some aspects, the processors2710(or the processor2706) are configured to communicate via the one or more modems2770and the one or more transceivers2750with a device2780, a device2782, or both. In a particular example, the device2700exchanges traffic2781(e.g., cellular modem traffic) with the device2780, exchanges traffic2783(e.g., WLAN traffic) with the device2782, or both. For example, the traffic2781is exchanged along a data path via at least one (e.g., a cellular modem) of the one or more modems2770, at least one of the one or more transceivers2750, and at least one of the one or more antennas2752to the device2780. Similarly, the traffic2783is exchanged along a data path via at least one (e.g., a WLAN modem) of the one or more modems2770, at least one of the one or more transceivers2750, and at least one of the one or more antennas2752to the device2782.

In a particular implementation, the consistency domain manager142of the memory manager140enforces synchronization of the traffic2781(e.g., cellular modem traffic) independently of the traffic2783(e.g., WLAN traffic). For example, the consistency domain manager142ensures that a synchronization operation associated with the cellular modem memory transactions does not block subsequent WLAN memory transactions, and vice versa. In a particular aspect, the capacity domain manager144of the memory manager140enforces resource utilization of the traffic2781(e.g., cellular modem traffic) independently of the traffic2783(e.g., WLAN traffic). For example, the capacity domain manager144ensures that cellular modem memory transactions are not blocked by WLAN memory transactions, and vice versa.

The device2700may include a display2728coupled to a display controller2726. One or more speakers2792, one or more microphones2790, or a combination thereof, may be coupled to the CODEC2734. The CODEC2734may include a digital-to-analog converter (DAC)2702, an analog-to-digital converter (ADC)2704, or both. In a particular implementation, the CODEC2734may receive analog signals from the one or more microphones2790, convert the analog signals to digital signals using the analog-to-digital converter2704, and provide the digital signals to the speech and music codec2708. The speech and music codec2708may process the digital signals. In a particular implementation, the speech and music codec2708may provide digital signals to the CODEC2734. The CODEC2734may convert the digital signals to analog signals using the digital-to-analog converter2702and may provide the analog signals to the one or more speakers2792.

In a particular implementation, the device2700may be included in a system-in-package or system-on-chip device2722. In a particular implementation, the memory2786, the processor2706, the processors2710, the display controller2726, the CODEC2734, and the one or more modems2770are included in the system-in-package or system-on-chip device2722. In a particular implementation, an input device2730and a power supply2744are coupled to the system-in-package or the system-on-chip device2722. Moreover, in a particular implementation, as illustrated inFIG.27, the display2728, the input device2730, the one or more speakers2792, the one or more microphones2790, the one or more antennas2752, and the power supply2744are external to the system-in-package or the system-on-chip device2722. In a particular implementation, each of the display2728, the input device2730, the one or more speakers2792, the one or more microphones2790, the one or more antennas2752, and the power supply2744may be coupled to a component of the system-in-package or the system-on-chip device2722, such as an interface or a controller.

The device2700may include a smart speaker, a speaker bar, a mobile communication device, a smart phone, a cellular phone, a laptop computer, a computer, a tablet, a personal digital assistant, a display device, a television, a gaming console, a music player, a radio, a digital video player, a digital video disc (DVD) player, a tuner, a camera, a navigation device, a vehicle, a headset, an augmented reality headset, a mixed reality headset, a virtual reality headset, an aerial vehicle, a home automation system, a voice-activated device, a wireless speaker and voice activated device, a portable electronic device, a car, a computing device, a communication device, an internet-of-things (IoT) device, a virtual reality (VR) device, a base station, a mobile device, or any combination thereof.

In conjunction with the described implementations, an apparatus includes means for assigning distinct domain identifiers to each of multiple software threads. For example, the means for assigning distinct domain identifiers can correspond to the consistency domain manager142, the capacity domain manager144, the memory manager140, the one or more processors190, the device102, the system100ofFIG.1, the processor2706, the one or more processors2710, the device2700, one or more other circuits or components configured to assign distinct domain identifiers to each of multiple software threads, or any combination thereof.

The apparatus also includes means for controlling operation of one or more components of a processor based on a number of memory transactions associated with a domain identifier. For example, the means for controlling operation can correspond to the consistency domain manager142, the capacity domain manager144, the memory manager140, the one or more processors190, the device102, the system100ofFIG.1, the processor2706, the one or more processors2710, the device2700, one or more other circuits or components configured to assign distinct domain identifiers to each of multiple software threads, or any combination thereof.

In some implementations, a non-transitory computer-readable medium (e.g., a computer-readable storage device, such as the memory2786) includes instructions (e.g., the instructions2756) that, when executed by one or more processors (e.g., the one or more processors2710or the processor2706), cause the one or more processors to assign distinct domain identifiers (e.g., the consistency domain identifiers156, the capacity domain identifiers158, or both) to each of multiple software threads. The instructions, when executed by the one or more processors, also cause the one or more processors to control operation of one or more components (e.g., the one or more components170) of the processor based on a number of memory transactions associated with a domain identifier (e.g., the consistency domain number of transactions data162, the capacity domain number of transactions data164, or both).

Particular aspects of the disclosure are described below in sets of interrelated clauses:According to Clause 1, a device includes: a memory; and a processor coupled to the memory and configured to: assign distinct domain identifiers to each of multiple software threads; and control operation of one or more components of the processor based on a number of memory transactions associated with a domain identifier.Clause 2 includes the device of Clause 1, further including a cache control register associated with a first software thread, and wherein assigning a first domain identifier to the first software thread includes updating the cache control register to indicate the first domain identifier.Clause 3 includes the device of Clause 1 or Clause 2, wherein the processor is configured to receive a synchronization instruction of a first software thread, the first software thread assigned a first consistency domain identifier, and wherein controlling the operation includes, in response to receiving the synchronization instruction, completing any pending store operations associated with the first consistency domain identifier prior to performing any subsequent data access instruction associated with the first consistency domain identifier.Clause 4 includes the device of Clause 3, wherein the processor is configured to, in response to receiving a synchronization instruction associated with a second consistency domain identifier that matches the first consistency domain identifier, complete any pending store operations associated with the first consistency domain identifier prior to performing any subsequent data access instruction associated with the second consistency domain identifier.Clause 5 includes the device of Clause 4, wherein the second consistency domain identifier indicates a sub-domain of a consistency domain that is indicated by the first consistency domain identifier.Clause 6 includes the device of Clause 4, wherein the first consistency domain identifier is the same as the second consistency domain identifier.Clause 7 includes the device of any of Clause 3 to Clause 6, wherein the synchronization instruction includes a barrier instruction or a store-release load-acquire instruction.Clause 8 includes the device of any of Clause 1 to Clause 7, further including: a cache configured to store data of the memory; and a transaction tracking scoreboard configured to track one or more pending stores associated with one or more consistency domain identifiers, wherein the processor is configured to, in response to receiving a write instruction of a first software thread indicating a first memory location and determining that data associated with the first memory location is not available in the cache: load first data from the first memory location to a first portion of the cache; and update the first data in the cache.Clause 9 includes the device of Clause 8, wherein the processor is configured to, in response to a store associated with the first software thread being committed, update an entry of the transaction tracking scoreboard to indicate a pending store operation of the updated first data to the first memory location, the entry updated to indicate the first memory location and a first consistency domain identifier of the first software thread.Clause 10 includes the device of Clause 9, wherein the processor is further configured to: receive an acknowledgement indicating that storage of the updated first data to the first memory location is complete; and in response to receiving the acknowledgement, update the transaction tracking scoreboard to indicate that the entry of the transaction tracking scoreboard is invalid.Clause 11 includes the device of any of Clause 8 to Clause 10, wherein the processor is configured to, in response to receiving a memory access instruction of a second software thread indicating a second memory location when data corresponding to the second memory location is not available in the cache and the cache is full: initiate an eviction of the updated first data from the cache; and load second data from the second memory location to the first portion of the cache.Clause 12 includes the device of Clause 11, wherein initiating the eviction of the updated first data includes updating an entry of the transaction tracking scoreboard to indicate a pending eviction of the updated first data corresponding to the first memory location.Clause 13 includes the device of Clause 12, wherein the processor is further configured to: receive an acknowledgement indicating that storage of the updated first data to the first memory location is complete; and in response to receiving the acknowledgement, update the transaction tracking scoreboard to indicate that the entry of the transaction tracking scoreboard is invalid.Clause 14 includes the device of any of Clause 8 to Clause 13, wherein the processor is configured to, in response to determining that a cache operation having a second consistency domain identifier is associated with the first memory location corresponding to the updated first data stored in the first portion of the cache: initiate an eviction of the updated first data from the cache; and update the cache to indicate that the first portion of the cache is available.Clause 15 includes the device of Clause 14, wherein initiating the eviction of the updated first data includes updating an entry of the transaction tracking scoreboard to indicate a pending eviction of the updated first data and to indicate a pending store operation associated with the second consistency domain identifier.Clause 16 includes the device of Clause 15, wherein the processor is further configured to: receive an acknowledgement indicating that storage of the updated first data to the first memory location is complete; and in response to receiving the acknowledgement, update the transaction tracking scoreboard to indicate that the entry of the transaction tracking scoreboard is invalid.Clause 17 includes the device of any of Clause 1 to Clause 16, further including a cache configured to store data of the memory, wherein the processor is configured to, in response to determining that a cache operation is associated with a second memory location and that no valid data associated with the second memory location is stored in the cache, assign a second consistency domain identifier of the cache operation to any pending evictions associated with the second memory location.Clause 18 includes the device of any of Clause 1 to Clause 17, further including: a cache configured to store data of the memory; and a transaction tracking scoreboard, wherein the processor is configured to, in response to determining that a cache operation is associated with a second memory location, that no valid data associated with the second memory location is stored in the cache, and that an entry of the transaction tracking scoreboard corresponds to a pending eviction associated with the second memory location, update the entry of the transaction tracking scoreboard to indicate a second consistency domain identifier of the cache operation.Clause 19 includes the device of Clause 18, wherein the processor is further configured to: receive an acknowledgement indicating that a store associated with the entry of the transaction tracking scoreboard is complete; and in response to receiving the acknowledgement, update the transaction tracking scoreboard to indicate that the entry of the transaction tracking scoreboard is invalid.Clause 20 includes the device of any of Clause 1 to Clause 19, wherein the processor is configured to receive a memory access instruction from a first software thread, the first software thread assigned a first capacity domain identifier, and wherein controlling the operation includes selectively enabling the memory access instruction based on a count of pending memory access instructions associated with the first capacity domain identifier.Clause 21 includes the device of Clause 20, wherein the processor is configured to, based on determining that the count of pending memory access instructions is less than a threshold count corresponding to the first capacity domain identifier: initiate a memory access associated with the memory access instruction; and increment the count of pending memory access instructions associated with the first capacity domain identifier.Clause 22 includes the device of Clause 21, wherein the processor is configured to: receive an acknowledgement indicating that the memory access is complete; and in response to receiving the acknowledgement, decrement the count of pending memory access instructions associated with the first capacity domain identifier.Clause 23 includes the device of any of Clause 1 to Clause 22, wherein a first domain identifier is assigned to the first software thread based at least in part on a communication type associated with the first software thread, and wherein the communication type includes cellular modem traffic or wireless local-area network (WLAN) traffic.According to Clause 24, a computer-implemented method includes: assigning, at a device, distinct domain identifiers to each of multiple software threads; and controlling, at the device, operation of one or more components of a processor based on a number of memory transactions associated with a domain identifier.Clause 25 includes the computer-implemented method of Clause 24, wherein a cache control register is associated with a first software thread, and wherein assigning a first domain identifier to the first software thread includes updating the cache control register to indicate the first domain identifier.Clause 26 includes the computer-implemented method of Clause 24 or Clause 25, further including receiving a synchronization instruction of a first software thread, the first software thread assigned a first consistency domain identifier, wherein controlling the operation includes, in response to receiving the synchronization instruction, completing any pending store operations associated with the first consistency domain identifier prior to performing any subsequent data access instruction associated with the first consistency domain identifier.Clause 27 includes the computer-implemented method of Clause 26, further including, in response to receiving a synchronization instruction associated with a second consistency domain identifier that matches the first consistency domain identifier, completing any pending store operations associated with the first consistency domain identifier prior to performing any subsequent data access instruction associated with the second consistency domain identifier.Clause 28 includes the computer-implemented method of Clause 27, wherein the second consistency domain identifier indicates a sub-domain of a consistency domain that is indicated by the first consistency domain identifier.Clause 29 includes the computer-implemented method of Clause 27, wherein the first consistency domain identifier is the same as the second consistency domain identifier.Clause 30 includes the computer-implemented method of any of Clause 26 to Clause 29, wherein the synchronization instruction includes a barrier instruction or a store-release load-acquire instruction.Clause 31 includes the computer-implemented method of Clause 24 to Clause 30, further including, in response to receiving a write instruction of a first software thread indicating a first memory location and determining that data associated with the first memory location is not available in a cache: loading first data from the first memory location to a first portion of the cache; and updating the first data in the cache.Clause 32 includes the computer-implemented method of Clause 31, further including, in response to a store associated with the first software thread being committed, updating an entry of a transaction tracking scoreboard to indicate a pending store operation of the updated first data to the first memory location, the entry updated to indicate the first memory location and a first consistency domain identifier of the first software thread.Clause 33 includes the computer-implemented method of Clause 32, further including: receiving an acknowledgement indicating that storage of the updated first data to the first memory location is complete; and in response to receiving the acknowledgement, updating the transaction tracking scoreboard to indicate that the entry of the transaction tracking scoreboard is invalid.Clause 34 includes the computer-implemented method of any of Clause 31 to Clause 33, further including, in response to receiving a memory access instruction of a second software thread indicating a second memory location when data corresponding to the second memory location is not available in the cache and the cache is full: initiating an eviction of the updated first data from the cache; and loading second data from the second memory location to the first portion of the cache.Clause 35 includes the computer-implemented method of Clause 34, wherein initiating the eviction of the updated first data includes updating an entry of the transaction tracking scoreboard to indicate a pending eviction of the updated first data corresponding to the first memory location.Clause 36 includes the computer-implemented method of Clause 35, further including: receiving an acknowledgement indicating that storage of the updated first data to the first memory location is complete; and in response to receiving the acknowledgement, updating the transaction tracking scoreboard to indicate that the entry of the transaction tracking scoreboard is invalid.Clause 37 includes the computer-implemented method of any of Clause 31 to Clause 36, wherein the processor is configured to, in response to determining that a cache operation having a second consistency domain identifier is associated with the first memory location corresponding to the updated first data stored in the first portion of the cache: initiating an eviction of the updated first data from the cache; and updating the cache to indicate that the first portion of the cache is available.Clause 38 includes the computer-implemented method of Clause 37, wherein initiating the eviction of the updated first data includes updating an entry of the transaction tracking scoreboard to indicate a pending eviction of the updated first data and to indicate a pending store operation associated with the second consistency domain identifier.Clause 39 includes the computer-implemented method of Clause 38, further including: receiving an acknowledgement indicating that storage of the updated first data to the first memory location is complete; and in response to receiving the acknowledgement, updating the transaction tracking scoreboard to indicate that the entry of the transaction tracking scoreboard is invalid.Clause 40 includes the computer-implemented method of any of Clause 24 to Clause 39, further including, in response to determining that a cache operation is associated with a second memory location and that no valid data associated with the second memory location is stored in a cache, assign a second consistency domain identifier of the cache operation to any pending evictions associated with the second memory location.Clause 41 includes the computer-implemented method of any of Clause 24 to Clause 40, further including, in response to determining that a cache operation is associated with a second memory location, that no valid data associated with the second memory location is stored in a cache, and that an entry of a transaction tracking scoreboard corresponds to a pending eviction associated with the second memory location, updating the entry of the transaction tracking scoreboard to indicate a second consistency domain identifier of the cache operation.Clause 42 includes the computer-implemented method of Clause 41, further including: receiving an acknowledgement indicating that a store associated with the entry of the transaction tracking scoreboard is complete; and in response to receiving the acknowledgement, updating the transaction tracking scoreboard to indicate that the entry of the transaction tracking scoreboard is invalid.Clause 43 includes the computer-implemented method of any of Clause 24 to Clause 42, further including receiving a memory access instruction from a first software thread, the first software thread assigned a first capacity domain identifier, wherein controlling the operation includes selectively enabling the memory access instruction based on a count of pending memory access instructions associated with the first capacity domain identifier.Clause 44 includes the computer-implemented method of Clause 43, further including, based on determining that the count of pending memory access instructions is less than a threshold count corresponding to the first capacity domain identifier: initiating a memory access associated with the memory access instruction; and incrementing the count of pending memory access instructions associated with the first capacity domain identifier.Clause 45 includes the computer-implemented method of Clause 44, further including: receiving an acknowledgement indicating that the memory access is complete; and in response to receiving the acknowledgement, decrementing the count of pending memory access instructions associated with the first capacity domain identifier.Clause 46 includes the computer-implemented method of any of Clause 24 to Clause 45, wherein a first domain identifier is assigned to the first software thread based at least in part on a communication type associated with the first software thread, and wherein the communication type includes cellular modem traffic or wireless local-area network (WLAN) traffic.According to Clause 47, a device includes: a memory configured to store instructions; and a processor configured to execute the instructions to perform the method of any of Clause 24 to Clause 46.According to Clause 48, a non-transitory computer-readable medium stores instructions that, when executed by a processor, cause the processor to perform the method of any of Clause 24 to Clause 46.According to Clause 49, an apparatus includes means for carrying out the method of any of Clause 24 to Clause 46.According to Clause 50, a non-transitory computer-readable medium stores instructions that, when executed by a processor, cause the processor to: assign distinct domain identifiers to each of multiple software threads; and control operation of one or more components of the processor based on a number of memory transactions associated with a domain identifier.Clause 51 includes the non-transitory computer-readable medium of Clause 50, wherein the instructions, when executed by the processor, cause the processor to receive a synchronization instruction of a first software thread, the first software thread assigned a first consistency domain identifier, wherein controlling the operation includes, in response to receiving the synchronization instruction, completing any pending store operations associated with the first consistency domain identifier prior to performing any subsequent data access instruction associated with the first consistency domain identifier.According to Clause 52, an apparatus includes: means for assigning distinct domain identifiers to each of multiple software threads; and means for controlling operation of one or more components of a processor based on a number of memory transactions associated with a domain identifier.Clause 53 includes the apparatus of Clause 52, wherein the means for assigning and the means for controlling are integrated into at least one of a smart speaker, a speaker bar, a display device, a television, a gaming console, a music player, a camera, a navigation device, a vehicle, a headset, an augmented reality headset, a mixed reality headset, a virtual reality headset, an aerial vehicle, a home automation system, a voice-activated device, a wireless speaker and voice activated device, a computing device, a communication device, an internet-of-things (IoT) device, a virtual reality (VR) device, a base station, or a mobile device.

The previous description of the disclosed aspects is provided to enable a person skilled in the art to make or use the disclosed aspects. Various modifications to these aspects will be readily apparent to those skilled in the art, and the principles defined herein may be applied to other aspects without departing from the scope of the disclosure. Thus, the present disclosure is not intended to be limited to the aspects shown herein but is to be accorded the widest scope possible consistent with the principles and novel features as defined by the following claims.