Negative gate stress operation in multi-pass programming and memory device thereof

A memory device is provided. The memory device includes an array of memory cells arranged in a plurality of rows, a plurality of word lines respectively coupled to the plurality of rows of the memory cells; and a peripheral circuit coupled to the word lines and configured to perform multi-pass programming on a selected row of memory cells coupled to a selected word line of the word lines. The multi-pass programming includes a plurality of programming passes, each of the programming passes having a programming operation and a verify operation. To perform the multi-pass programming, the peripheral circuit is configured to, in a non-last programming pass, perform a negative gate stress (NGS) operation on each memory cell in the selected row of memory cells between the programming operation and the verify operation.

BACKGROUND

The present disclosure relates to memory devices and operations thereof.

Flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR Flash memory and NAND Flash memory. Various operations can be performed by Flash memory, such as read, program (write), and erase, to change the threshold voltage of each memory cell to a desired level. For NAND Flash memory, an erase operation can be performed at the block level, a program operation can be performed at the page level, and a read operation can be performed at the cell level.

SUMMARY

In one aspect, a memory device includes an array of memory cells arranged in a plurality of rows, a plurality of word lines respectively coupled to the plurality of rows of the memory cells, and a peripheral circuit coupled to the word lines and configured to perform multi-pass programming on a selected row of memory cells coupled to a selected word line of the word lines. The multi-pass programming includes a plurality of programming passes. Each of the programming passes includes a programming operation and a verify operation. To perform the multi-pass programming, the peripheral circuit is configured to, in a non-last programming pass, perform a NGS operation on each memory cell in the selected row of memory cells between the programming operation and the verify operation.

In another aspect, a method for operating a memory device is provided. The memory device has an array of memory cells arranged in a plurality of rows and a plurality of word lines respectively coupled to the plurality of rows of the memory cells. The method includes performing multi-pass programming on a selected row of memory cells, the multi-pass programming comprising a plurality of programming passes. Each of the programming passes includes a programming operation and a verify operation. Performing the multi-pass programming includes, in a non-last programming pass, performing a NGS operation on each memory cell in the selected row of memory cells between the programming operation and the verify operation.

In still another aspect, a system includes a memory device configured to store data and a memory controller coupled to the memory device and configured to control the memory device. The memory device includes an array of memory cells arranged in a plurality of rows, a plurality of word lines respectively coupled to the plurality of rows of the memory cells, and a peripheral circuit coupled to the word lines and configured to perform multi-pass programming on a selected row of memory cells coupled to a selected word line of the word lines. The multi-pass programming includes a plurality of programming passes. Each of the programming passes includes a programming operation and a verify operation. To perform the multi-pass programming, the peripheral circuit is configured to, in a non-last programming pass, perform a NGS operation on each memory cell in the selected row of memory cells between the programming operation and the verify operation.

Aspects of the present disclosure will be described with reference to the accompanying drawings.

DETAILED DESCRIPTION

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. As such, other configurations and arrangements can be used without departing from the scope of the present disclosure. Also, the present disclosure can also be employed in a variety of other applications. Functional and structural features as described in the present disclosures can be combined, adjusted, and modified with one another and in ways not specifically depicted in the drawings, such that these combinations, adjustments, and modifications are within the scope of the present discloses.

Charge-trapping material has been used for retention of data in a NAND Flash memory. For example, a charge-trapping material can be used in a charge-trapping layer in a NAND memory string (e.g., memory channel. However, a charge-trapping device, e.g., a memory device having a charge-trapping layer for data retention, can have reliability issues due to the nature of the charge-trapping material.

A common issue of a charge-trapping device is known as a fast initial charge loss (or early retention) issue, which is a fast relaxation behavior in which charges escape from the charge-trapping layer shortly after a programming operation. This behavior is believed to cause by the shallowly-trapped charges and can result in a threshold voltage of a memory cell to drift. The drifting of the threshold voltage can lead to degraded programming distributions.

In a NAND Flash memory, the intersections of word lines and strings form a plurality of memory cells. The block includes a plurality of fingers, and each finger includes a pair of fingers. Each string is coupled to a bit line. Strings in a finger are coupled to a drain select gate (DSG). A memory cell stores data in the form of a threshold voltage, which represents the lowest voltage at which the memory cell can be switched on. For example, the threshold voltage range of a 2-bit multi-level cell (MLC) NAND Flash memory cell is divided into four regions. The region in which the threshold voltage of a memory cell falls represents the memory cell's current state, which can be an erased (or ER) state and three higher data states. A programming pass may use a set of increasing program voltages/pulses which are applied on the word line coupled to a memory cell to program the memory cell by setting the threshold voltage of the memory cell to the desired states. Each program voltage/pulse is applied in a programming operation and is followed by a verify operation, which employs one or more verify voltages to determine whether the memory cell has completed programming. After all the memory cells are programmed, the data in the memory cells can be read back in a read operation.

Multi-pass programming can be used in programming memory cells. In multi-pass programming, multiple programming passes are employed consecutively. Multi-pass programming can reduce neighboring word line interference (NWI), which refers to an increase in the threshold voltage of a memory cell connected to one word line when the neighboring (adjacent) memory cells (e.g., in the same string and coupled to other word lines) are programmed. Multi-pass programming can reduce the NWI by programming the memory cells to intermediate threshold voltage distributions in non-last programming pass(es), and programming the memory cells to the final threshold voltage distribution in the last programming pass.

As mentioned above, shallowly-trapped charges may cause programming distribution to degrade. To solve the issue of degraded programming distribution, a negative gate stress (NGS) operation has been used in the multi-pass programming to remove at least some shallowly-trapped charges and tighten the threshold voltage distribution. However, a NGS operation may decrease a read window budget (RWB), i.e., a threshold voltage window between erased and higher data states needed for reading operation of a memory cell, and is thus not suitable to be enabled on a memory cell after the memory cell already passes a verify operation. In a NGS operation, memory cells passed the verify operation immediately prior to the NGS operation, and memory cells not passed the verify operation immediately prior to the NGS operation are applied with different combinations of voltages such that the memory cells passed the verify operation would not undergo the NGS operation and only the memory cells not passed the verify operation would undergo the NGS operation. For example, when programming memory cells row by row, different voltages are applied on the DSGs and bit lines coupled to memory cells (e.g., in the same row) passed and not passed the verify operation, respectively, such that only the memory cells not passed the verify operation undergo NGS operations. The operation of the NAND memory can be complex, and the power consumption of the operation can be undesirably high. Sometimes, the distributions of the threshold voltage of memory cells that have already undergone a NGS operation are not desirably narrow, impacting the reading operation.

The present disclosure provides a novel NGS scheme for multi-pass programming in a memory device, the memory device, and a system thereof. The NGS scheme is enabled in at least one non-last programming pass of the multi-pass programming to remove shallowly-trapped charges in memory cells passed and not passed a respective verify operation immediately-prior to the NGS operation. Different from the known NGS scheme, which is only enabled on memory cells not passed a respective verify operation, the novel NGS scheme is enabled on all memory cells in a selected row that are being programmed. That is, memory cells, passed and not passed the respective verify operation, may each undergo a respective NGS operation. The NGS operations can further remove the shallowly-trapped charges in the memory cells that have already passed the respective verify operation, and further narrow the distributions of threshold voltage, increasing the RWB. In the last programming pass of the multi-pass programming, when a selected row of memory cells are being programmed, NGS operations are only enabled on memory cells not passed a respective verify operation immediately prior to the NGS operation or not enabled on any memory cells. The RWB of a memory cell thus would not be decreased by NGS operations.

To enable NGS operations on each memory cells in a selected row that is being programmed, a same low voltage may be applied on the DSGs of all the strings in which all the memory cells in the selected row are located. The DSGs of these strings are thus turned off. Meanwhile, source-select gates (SSGs) of all these strings are also turned off. A relatively high positive voltage, e.g., higher than VDD, is applied on word lines above and below the word line coupled to the memory cells in the selected row, boosting the voltage potential of the strings. The strings are thus each in a floating state, and the potential in the string increases. A low voltage is applied on the word line coupled to the selected row of memory cells such that a NGS operation can be enabled in each of the memory cells in the row. This can enable “an erase” of the shallowly-trapped charges such that each memory cell in the selected row can have the shallowly-trapped charges further removed. To avoid the decrease of RWB of the memory cells, the novel NGS scheme is enabled in a non-last programming pass. In some implementations, because a low voltage, e.g., ground or a negative voltage, is applied on the DSGs of all the strings being programmed, the power consumption can be reduced.

FIG.1Aillustrates a block diagram of an exemplary system100having a memory device, according to some aspects of the present disclosure. System100can be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an argument reality (AR) device, or any other suitable electronic devices having storage therein. As shown inFIG.1A, system100can include a host108and a memory system102having one or more memory devices104and a memory controller106. Host108can be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). Host108can be configured to send or receive the data to or from memory devices104.

Memory device104can be any memory devices disclosed herein, such as a NAND Flash memory device. Consistent with the scope of the present disclosure, memory controller106may control the multi-pass programming on memory device104such that a NGS operation is enabled on all memory cells, even those passed the respective verify operations, in a non-last programming pass of the multi-pass programming. The peripheral circuits, such as the word line drivers, may apply a low voltage, e.g., ground (GND) voltage, on the DSGs of each memory string coupled to the selected word line, and may apply a low or negative voltage on the selected word line to enable a NGS operation on all memory cells coupled to the selected word line during a non-last programming pass.

Memory controller106is coupled to memory device104and host108and is configured to control memory device104, according to some implementations. Memory controller106can manage the data stored in memory device104and communicate with host108. In some implementations, memory controller106is designed for operating in a low duty-cycle environment like secure digital (SD) cards, compact Flash (CF) cards, universal serial bus (USB) Flash drives, or other media for use in electronic devices, such as personal computers, digital cameras, mobile phones, etc. In some implementations, memory controller106is designed for operating in a high duty-cycle environment SSDs or embedded multi-media-cards (eMMCs) used as data storage for mobile devices, such as smartphones, tablets, laptop computers, etc., and enterprise storage arrays. Memory controller106can be configured to control operations of memory device104, such as read, erase, and program operations. Memory controller106can also be configured to manage various functions with respect to the data stored or to be stored in memory device104including, but not limited to bad-block management, garbage collection, logical-to-physical address conversion, wear leveling, etc. In some implementations, memory controller106is further configured to process error correction codes (ECCs) with respect to the data read from or written to memory device104. Any other suitable functions may be performed by memory controller106as well, for example, programming memory device104. Memory controller106can communicate with an external device (e.g., host108) according to a particular communication protocol. For example, memory controller106may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial-ATA protocol, a parallel-ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

Memory controller106and one or more memory devices104can be integrated into various types of storage devices, for example, be included in the same package, such as a universal Flash storage (UFS) package or an eMMC package. That is, memory system102can be implemented and packaged into different types of end electronic products. In one example as shown inFIG.1B, memory controller106and a single memory device104may be integrated into a memory card112. Memory card112can include a PC card (PCMCIA, personal computer memory card international association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. Memory card112can further include a memory card connector114coupling memory card112with a host (e.g., host108inFIG.1A). In another example as shown inFIG.1C, memory controller106and multiple memory devices104may be integrated into an SSD116. SSD116can further include an SSD connector118coupling SSD116with a host (e.g., host108inFIG.1A). In some implementations, the storage capacity and/or the operation speed of SSD116is greater than those of memory card112.

FIG.2illustrates a diagram of an exemplary memory device104, e.g., a NAND Flash memory, having a memory cell array202and peripheral circuits including a page buffer204, a column decoder/bit line driver206, a row decoder/word line driver208, a voltage generator210, control logic212, registers214, and an interface216.FIG.3illustrates a schematic circuit diagram of an exemplary memory device104including a memory cell array202and peripheral circuits302coupled to memory cell array202. For ease of illustration, some components inFIGS.2and3are described together. Peripheral circuits302can include page buffer204, column decoder/bit line driver206, row decoder/word line driver208, voltage generator210, control logic212, registers214, and interface216inFIG.2. It is understood that in some examples, additional peripheral circuits may be included as well.

As shown inFIG.3, memory cell array202can be a NAND Flash memory cell array in which memory cells306are provided in the form of an array of NAND memory strings308each extending vertically above a substrate (not shown). In some implementations, each NAND memory string308includes a plurality of memory cells306coupled in series and stacked vertically. Each memory cell306can hold a continuous, analog value, such as an electrical voltage or charge, that depends on the number of electrons trapped within a region of memory cell306. Each memory cell306can be either a floating gate type of memory cell including a floating-gate transistor or a charge trap type of memory cell including a charge-trap transistor.

In some implementations, each memory cell306is a single-level cell (SLC) that has two possible memory states and thus, can store one bit of data. For example, the first memory state “0” can correspond to a first range of voltages, and the second memory state “1” can correspond to a second range of voltages. In some implementations, each memory cell306is a multi-level cell (MLC) that is capable of storing more than a single bit of data in more than four memory states. For example, the MLC can store two bits per cell, three bits per cell (also known as triple-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to assume a range of possible nominal storage values. In one example, if each MLC stores two bits of data, then the MLC can be programmed to assume one of three possible programming levels from an erased state by writing one of three possible nominal storage values to the cell. A fourth nominal storage value can be used for the erased state.

As shown inFIG.3, each NAND memory string308can include an SSG310at its source end and a DSG312at its drain end. SSG310and DSG312are respective the gate electrodes of an SSG transistor and a DSG transistor and can be configured to activate selected NAND memory strings308(columns of the array) during read and program operations. In some implementations, SSGs310of NAND memory strings308in the same block304are coupled through a same source line (SL)314, e.g., a common SL, for example, to the ground. DSG312of each NAND memory string308is coupled to a respective bit line316from which data can be read via an output bus (not shown), according to some implementations. In some implementations, each NAND memory string308is configured to be selected or deselected by applying a select voltage (e.g., above the threshold voltage of the transistor having DSG312) or a deselect voltage (e.g., 0 V) to respective DSG312through one or more DSG lines313and/or by applying a select voltage (e.g., above the threshold voltage of the transistor having SSG310) or a deselect voltage (e.g., 0 V) to respective SSG310through one or more SSG lines315.

As shown inFIG.3, NAND memory strings308can be organized into multiple blocks304, each of which can have a common source line314. In some implementations, each block304is the basic data unit for erase operations, i.e., all memory cells306on the same block304are erased at the same time. Memory cells306of adjacent NAND memory strings308can be coupled through word lines318that select which row of memory cells306is affected by read and program operations. In some implementations, each word line318is coupled to a page320of memory cells306, which is the basic data unit for program operations. The size of one page320in bits can correspond to the number of NAND memory strings308coupled by word line318in one block304. Each word line318can include a plurality of control gates (gate electrodes) at each memory cell306in respective page320and a gate line coupling the control gates.

Peripheral circuits302can be coupled to memory cell array202through bit lines316, word lines318, source lines314, SSG lines315, and DSG lines313. Peripheral circuits302may apply voltages on bit lines316, word lines318, source lines314, SSG lines315, and DSG lines313to perform multi-pass programming including the proposed NGS scheme in a non-last programming pass. As described above, peripheral circuits302can include any suitable circuits for facilitating the operations of memory cell array202by applying and sensing voltage signals and/or current signals through bit lines316to and from each target memory cell306through word lines318, source lines314, SSG lines315, and DSG lines313. Peripheral circuits302can include various types of peripheral circuits formed using MOS technologies.

FIG.4Aillustrates a cross-section of an exemplary memory cell array202, according to some aspects of the present disclosure. As shown inFIG.4A, memory cell array202includes a NAND memory string410, which can be an example of a NAND memory string308inFIG.3, extending vertically above a substrate402. Substrate402can include silicon (e.g., single crystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable materials. It is noted that x, y, and z axes are included inFIG.4Ato further illustrate the spatial relationship of the components in memory cell array202. Substrate402includes two lateral surfaces (e.g., a top surface and a bottom surface) extending laterally in the x-direction (i.e., the lateral direction). As used herein, whether one component is “on,” “above,” or “below” another component of a semiconductor structure (e.g., memory cell array202) is determined relative to the substrate of the semiconductor structure (e.g., substrate402) in the z-direction (i.e., the vertical direction or depth direction) when the substrate is positioned in the lowest plane of the semiconductor structure in the z-direction. The same notion for describing the spatial relationship is applied throughout the present disclosure.

As shown inFIG.4A, NAND memory string410extends vertically through a memory stack404having interleaved gate conductive layers406and gate-to-gate dielectric layers408above substrate402. Gate conductive layers406and gate-to-gate dielectric layers408in memory stack404can alternate in the vertical direction. Each gate conductive layer406can include conductive materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. In some implementations, each gate conductive layer406includes a metal layer, such as a tungsten layer. In some implementations, each gate conductive layer406includes a doped polysilicon layer. Each gate conductive layer406can include control gates surrounding the memory cells (e.g., memory cells306inFIG.3), a DSG (e.g., DSG312inFIG.3), or an SSG (e.g., SSG310inFIG.3), and can extend laterally as a DSG line (e.g., DSG line313inFIG.3) at the top of memory stack404, an SSG line (e.g., SSG line315inFIG.3) at the bottom of memory stack404, or a word line between the DSG line and the SSG line (e.g., word lines318inFIG.3).

As shown inFIG.4A, NAND memory string410includes a channel structure412extending vertically through memory stack404. In some implementations, channel structure412includes a channel hole filled with semiconductor material(s) (e.g., as a semiconductor channel420) and dielectric material(s) (e.g., as a memory film418). In some implementations, semiconductor channel420includes silicon, such as amorphous silicon, polysilicon, or single crystalline silicon. In some implementations, memory film418is a composite dielectric layer including a tunneling layer426, a storage layer424(also known as a “charge trap/storage layer”), and a blocking layer422. Channel structure412can have a cylinder shape (e.g., a pillar shape). Semiconductor channel420, tunneling layer426, storage layer424, blocking layer422are arranged radially from the center toward the outer surface of the pillar in this order, according to some implementations. Tunneling layer426can include silicon oxide, silicon oxynitride, or any combination thereof. Storage layer424can include silicon nitride, silicon oxynitride, silicon, or any combination thereof. Blocking layer422can include silicon oxide, silicon oxynitride, high dielectric constant (high-k) dielectrics, or any combination thereof. In one example, memory film418can include a composite layer of silicon oxide/silicon oxynitride/silicon oxide (ONO).

In some implementations, NAND memory string410further includes a semiconductor plug414in the lower portion (e.g., at the lower end) of NAND memory string410. Semiconductor plug414can include a semiconductor material, such as single-crystal silicon, which is epitaxially grown from substrate402in any suitable direction. Semiconductor plug414can function as part of the channel of a source-select transistor (e.g., the source-select transistor having SSG310inFIG.3) of NAND memory string410. In some implementations, NAND memory string410further includes a channel plug416in the upper portion (e.g., at the upper end) of NAND memory string410. In some implementations, channel plug416can function as the channel of a drain select transistor (e.g., the drain select transistor having DSG312inFIG.3) of NAND memory string410. As used herein, the upper end of a component (e.g., channel structure412) is the end farther away from substrate402in the z-direction, and the lower end of the component (e.g., channel structure412) is the end closer to substrate402in the z-direction when substrate402is positioned in the lowest plane of memory cell array202.

FIG.4Billustrates a top view of part of memory cell array202, which includes a block434in which a plurality of NAND memory strings410are located, according to some implementations. Multi-pass programming may be performed to program the threshold voltages of memory cells in block434to higher data states. Block434may be an example of block304in memory cell array202illustrated inFIG.3. As shown inFIG.4B, in the x-y plane, block434is located between a pair of gate-line slits (GLSs)432in memory cell array202. One or more (e.g., a pair of) GLSs432may further divide block434into a plurality of fingers436A and436B. A source contact (not shown) structure may be located in each GLS432and electrically coupled to source line314. A DSG cut428may be located in the upper portion of block434and divide block434into a pair of fingers436A and436B. Each finger436A/436B may include a plurality of NAND memory strings410arranged in the x-direction and the y-direction. In some implementations, the source contact structure each includes an insulating spacer and a conductive material in the insulating spacer. The insulating spacer may include a suitable dielectric material such as silicon oxide, and the conductive material may include W, Co, Al, Cu, polysilicon, silicides, etc. In some implementations, DSG cut428extends in the x-direction and includes a suitable dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

In some implementations, the same voltage is applied via a DSG line (e.g., DSG line313) onto DSGs (e.g., DSGs312) of NAND memory strings410in the same finger. In some implementations, the DSGs of NAND memory strings410in each finger can be separately controlled by applying a respective voltage via the respective DSG line. In a programming pass, memory cells (e.g., memory cells306) coupled to the same word line (e.g., word line318) in block434may the applied with the same programming voltage/pulse and verify voltages at the same time. In some implementations, the same voltage is applied via an SSG line (e.g., SSG line315) onto SSGs (e.g., SSGs310) of NAND memory strings410in block434. In some implementations, each NAND memory string410is applied with a respective voltage via the respective bit line (e.g., bit line316). To perform the multi-pass programming on NAND memory strings410in block434, control logic212may control each peripheral circuit302to apply respective voltages. The details are illustrated as follows.

Referring back toFIG.2, page buffer204can be configured to read and program data from and to memory cell array202according to the control of control logic212. In one example, page buffer204may store one page of program data (write data) to be programmed into one page320of memory cell array202. In another example, page buffer204also performs verify operations to ensure that the data has been properly programmed into memory cells306coupled to selected word lines318.

Row decoder/word line driver208can be configured to be controlled by control logic212. Row decoder/word line driver208may select/deselect a block304of memory cell array202and a word line318(page320) of the selected block304. Row decoder/word line driver208can be further configured to drive selected word line318using a word line voltage generated from voltage generator210. Row decoder/word line driver208can also be configured to select a finger of block304. Voltage generator210can be configured to be controlled by control logic212and generate the word line voltages (e.g., read voltage, program voltage, pass voltage, local voltage, and verification voltage) to be supplied to memory cell array202. Column decoder/bit line driver206can be configured to be controlled by control logic212and select one or more NAND memory strings308by applying bit line voltages generated from voltage generator210. For example, column decoder/bit line driver206may apply column signals for selecting a set of N bits of data from page buffer204to be outputted in a read operation.

Control logic212can be coupled to or deposed in each peripheral circuit302and configured to control operations of peripheral circuits302. For example, control logic212may control peripheral circuits302to perform multi-pass programming, which includes the disclosed NGS scheme in a non-last programming pass. Registers214can be coupled to control logic212and include status registers, command registers, and address registers for storing status information, command operation codes (OP codes), and command addresses for controlling the operations of each peripheral circuit302. Interface216can be coupled to control logic212and act as a control buffer to buffer and relay control commands received from a host (not shown) to control logic212and status information received from control logic212to the host. Interface216can also be coupled to memory controller106and act as an I/O interface and a data buffer to buffer and relay the program data received from memory controller106to control logic212.

FIG.5Aillustrates an exemplary multi-pass programming500applied on a selected word line (e.g., word line318) of block304(or block434), according to some implementations.FIG.5Billustrates an exemplary program loop506including a NGS operation in a non-last programming pass502in multi-pass programming500, according to some implementations.FIG.5Cillustrates an exemplary program loop508without a NGS operation in a last programming pass504in multi-pass programming500according to some implementations.

FIG.5Aillustrates an example of the voltages applied on memory cells coupled to a selected word line in multi-pass programming500via the selected word line, according to implementations of the present disclosure. Multi-pass programming500may include one or more non-last programming pass502and a last programming pass504. For example, multi-pass programming500may be two-pass programming that includes a first programming/non-last pass502and a second/last programming pass504. Each programming pass may include one or more program loops. For example, non-last programming pass502may include a plurality of program loops506, and last programming pass504may include a plurality of program loops508. Each program loop506/508may include a programming voltage/pulse applied by a programming operation and one or more verify voltages applied by a verify operation. The programming operation may apply programming voltage on the selected word line to program the memory cells in the selected word line into a data state. In some implementations, programming voltage increases stepwise in an amplitude in one or more program loops of a programming pass using a fixed or varying step size. In some implementations, an incremental step pulse programming (ISPP), in which programming voltage starts at an initial level and increases in a step in each successive program loop until a programming pass is completed. The verify operation may apply one or more verify voltages on the selected word line to test if the threshold voltages of the memory cells in the selected word lines have been programmed into the desired data states. It should be noted that the actual amplitudes of programming voltages and verify voltages are not limited by the implementations of the present disclosure. Although programming voltages in programming pass504are shown to be higher than programming voltages in programming pass502inFIG.5A, depending on the operation, programming voltages in programming pass504may also be lower than or equal to programming voltages in programming pass502.

FIG.5Billustrates an example of voltages applied on the selected word line in program loop506, according to implementations of the present disclosure. In some implementations, program loop506includes a programming operation510, a NGS operation512following programming operation510, and a verify operation514following NGS operation512. In programming operation510, a programming voltage VPGM1may be applied on the selected word line to cause the threshold voltages of the memory cells coupled to the selected word line to be assigned to the higher data states. NGS operation512may be subsequently enabled on all the memory cells coupled to the selected word line by applying a low voltage VLon the selected word line. Details of NGS operation512is described as follows inFIGS.6A and6B. In some implementations, verify operation514is performed after NGS operation512to test if the threshold voltages of the memory cells assigned to the higher data state reach verify voltages VR1(e.g., intermediate verify voltages) as shown inFIG.5B.

FIG.5Cillustrates an example of voltages applied on the selected word line in program loop508, according to implementations of the present disclosure. In some implementations, program loop508includes a programming operation520and a verify operation524following programming operation520. No NGS operation is performed in any program loop508according to some implementations. In some embodiments, NGS operation is inhibited on all memory cells in program loop508, as shown inFIG.5C. In programming operation520, a programming voltage VPGM2may be applied on the selected word line to cause the threshold voltages of the memory cells coupled to the selected word line to be assigned to the higher data states and/or have narrower distributions. In some implementations, verify operation524is performed after programming operation520to test if the threshold voltages of the memory cells assigned to the higher data state reach verify voltages VR2(e.g., final verify voltages) as shown inFIG.5C. In some embodiments, although not shown, NGS operation is selectively enabled only on memory cells coupled to the selected word line and did not pass the respective verify operation immediately prior to the NGS operation.

Non-last programming pass502may or may not be the first programming pass in multi-pass programming500. If non-last programming pass502is not the first programming pass, memory cells coupled to the selected word line may include memory cells passed the respective verify operations prior to non-last programming pass502and memory cells did not pass the respective verify operations prior to non-last programming pass502. If non-last programming pass502is the first programming pass, all memory cells coupled to the selected word line may be treated as not passing the respective verify operations prior to non-last programming pass502. According to the present disclosure, all memory cells coupled to the selected word line may undergo a NGS operation in non-last programming pass502. However, in known multi-pass programming, in non-last programming pass502, only memory cells that did not pass the respective verify operations prior to non-last programming pass502are selected to undergo respective NGS operations, while the NGS operations are inhibited in memory cells that passed the respective verify operations prior to non-last programming pass502.

FIG.6Aillustrates a memory string600in an exemplary NGS operation, according to some implementations of the present disclosure.FIG.6Billustrates an example of voltages applied on a selected word line in a program loop506, according to some implementations of the present disclosure. For ease of illustration,FIGS.6A and6Bare described together.

As shown inFIG.6A, memory string600may include a plurality of memory cells arranged at respective cell depths, e.g., in the z-direction. Each of the memory cells may be coupled to a respective word line. For ease of illustration, a memory cell602is coupled to a selected word line610, and memory cells608are each coupled to an unselected word line612. Memory string600may also include a DSG transistor604at the upper end and an SSG transistor606at the lower end. DSG transistor604has a DSG (e.g.,312) that is coupled to a DSG line614, and SSG transistor606has an SSG (e.g.,310) that is coupled to an SSG line616. The DSG, the SSG, selected word line610, DSG line614, and SSG line616may be respective examples of DSG312, SSG310, selected word line318, DSG line313, and SSG line315illustrated inFIG.3.

For each programming pass,502and504, word lines612and610in the same block (e.g., block304) may be sequentially applied with respective voltages from bottom to top or from top to bottom in the z-direction, e.g., in a direction from SSG transistor606to DSG transistor604or vice versa. When program loop506is performed on word line610, programming operation510may include the word line driver (e.g.,208inFIG.2) applying programming voltage VPGM1on word line610, i.e., the selected word line. Threshold voltages of memory cells coupled to word line610(e.g., memory cell602) may be programmed to higher data states. After programming operation510, NGS operation512may be enabled on all memory cells coupled to word line610(e.g., memory cell602). NGS operation512may include the word line driver applying low voltage VLon word line610and applying a high voltage VPon word lines612. Low voltage VLmay be VSS/GND or a negative voltage applied on memory cells coupled to word line610(e.g., memory cell602). High voltage VPmay be a sufficiently high positive voltage that keeps memory cells608on during NGS operation512. In some implementations, VPis higher than VDD. After NGS operation512, verify operation514may be performed on memory cells coupled to word line610(e.g., memory cell602). Verify operation514may include the word line driver applying verify voltages VR1on word line610to test if threshold voltages of any memory cells coupled to word line610have been successfully programmed into the higher data states.

NGS operation512may function as a “shallow etch” to remove at least some shallowly-trapped charges in all memory cells coupled to word line610(e.g., memory cell602). Specifically, to enable NGS operation512on memory cell602, memory string600, which memory cell602is located, is configured to be at a “floating” state and undergoes a potential boost, in which the potential of memory string600increases. In the present disclosure, to set memory string600to the “floating” state, DSG transistor604and SSG transistor606are both turned off. Specifically, the value of VLis sufficiently low to ensure the value of the voltage on DSG line614minus the voltage on the bit line (e.g.,316) is below the threshold voltage of DSG transistor604. DSG transistor604is thus turned off for both memory cells passed and did not pass the verify operations. As such, the NGS operation can be enabled on both memory cells passed and did not pass the verify operations. Different from a known NGS operation, which is only enabled on memory cells that coupled to a selected word line and did not pass respective verify operations, NGS operation512is enabled on all memory cells coupled to a selected word line, e.g., word line610, when the word line610is being programmed in program loop506.

Referring back toFIG.4B, as an example, memory string600may be located in finger436A. Memory cell602may or may not pass a respective verify operation immediately prior to the NGS operation512. If memory cell602passed the verify operation, in some implementations, to enable NGS operation512on memory cell602, memory string600is set to be “floating” by applying a turn-off voltage on DSG transistor604via DSG line614of the respective finger, applying a turn-off voltage on SSG transistor606via SSG line616of the respective finger, and applying a low voltage on the bit line (not shown) coupled to memory string600. If memory cell602did not pass the verify operation, in some implementations, to enable NGS operation512on memory cell602, memory string600is set to be “floating” by applying a turn-off voltage on DSG transistor604via DSG line614of the respective finger, applying a turn-off voltage on SSG transistor606via SSG line616of the respective finger, and applying a high voltage on the bit line (not shown) coupled to memory string600. That is, even if finger436A includes memory cells coupled to word line610and did not pass a respective verify operation immediately prior to the NGS operation512when word line610is selected for programming, DSG transistors604of all the memory strings in the finger are turned off to enable NGS operations512in all memory cells coupled to word line610(e.g., including memory cell602). In some implementations, a turn-off voltage includes a low voltage or a negative voltage, and a turn-on voltage includes a positive voltage. In some implementations, the turn-off voltage is VSS/GND, and the turn-on voltage is VDD. Meanwhile, low voltage VLmay be applied on memory cell602via word line610, and high voltage VPmay be applied on memory cells608via word lines612. In some implementations, low voltage VLincludes one of VSSand a negative voltage, and high voltage VPincludes a positive voltage higher than VDD.

FIG.7Aillustrates exemplary waveforms of voltages applied on certain elements of memory string600in NGS operation512in program loop506, according to some implementations.FIG.7Billustrates waveforms of voltages applied on certain elements of memory string600in a NGS operation in program loop508, according to some implementations. In various implementations, voltages shown inFIG.7Aare applied in a non-last programming pass, and voltages shown inFIG.7Bcan be applied in a non-last programming pass or the last programming pass. In some implementations, NGS operations are inhibited in program loop508, as referring back toFIG.5Cand related description.

As shown inFIGS.7A and7B, waveforms of voltages applied on DSG line614and word lines610and612are illustrated. The NGS operations may be enabled at phases700and701, respectively. In some implementations, DSG line614and word lines610and612are ramped up from initial voltages to respective voltages in phase700/701such that the NGS operations can be enabled. WLn represents the selected word line that is being programmed. WLn+1 represents the word line immediately above WLn in the z-direction. WL(above) represents all other word lines above WLn+1. WLn−1 represents the word line immediately below WLn in the z-direction. WL(below) represents all other word lines below WLn+1. DSG (sel) represents the waveform of voltages applied on DSG of a finger having memory cells coupled to WLn and not passed a respective verify operation immediately prior to the NGS operation. DSG (unsel) represents the waveform of voltages applied on DSG of a finger having memory cells coupled to WLn and all passed a respective verify operation immediately prior to the NGS operation.

As shown inFIG.7A, in phase700, WLn (e.g.,610) is being programmed and is applied with a low voltage. DSG line614may be applied with a low voltage such that DSG transistors of all memory strings in a finger WLn extends laterally may be turned off. In some implementations, the low voltage is VSS/GND. In the meantime, other word lines612above and below WLn (e.g., WLn−1, WL(above), WLn+1, WL(below)) are each applied with a high voltage. In some embodiments, other word lines are applied with a positive voltage of VP. In some implementations, VPis higher than VDD.

Different from NGS operation512, the NGS operation illustrated inFIG.7Bmay be enabled only on memory cells coupled to WLn and did not pass the respective verify operations immediately prior to the NGS operation. For example, if memory cell602did not pass the verify operation, DSG line614may be applied with a voltage of VDSG_P_L; and if memory cell602passed the verify operation, DSG line614may be applied with a voltage of VDSG_P_H. In some embodiments, VDSG_P_Land VDSG_P_Hare each a positive voltage, and VDSG_P_His higher than VDSG_P_L. As described above, in the NGS operation, the bit line of the memory string having memory cells coupled with WLn and did not pass the verify operation may be applied with a high voltage, e.g., VDD; and the bit line of the memory string having memory cells in the selected word line and all passed the verify operation may be applied with a low voltage, e.g., VSS. The value of VDSG_P_Lminus VDDis lower than the threshold voltage of the DSG transistor such that the DSG transistor is turned off, enabling the NGS operation on memory cells coupled with word line610and did not pass the respective verify operations. The value of VDSG_P_Hminus VDDis higher than the threshold voltage of the DSG transistor such that the DSG transistor is turned on, inhibiting the NGS operation on memory cells coupled with word line610and passed the respective verify operations.

FIG.8is a flowchart of an exemplary method800for operating a memory device, according to some implementations of the present disclosure. Examples of the memory device depicted inFIG.8include memory devices104depicted inFIG.1A. For ease of illustration,FIG.8may be described in view of operations illustrated inFIGS.3,5A-5C,6A,6B,7A, and7B. It is understood that the operations shown in method800are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown inFIG.8. In some implementations, method800is performed by peripheral circuits302. Specifically, the word line driver (e.g.,208) may be configured to apply voltages on the word lines, the DSG line, and the SSG line, and bit line driver (e.g.,206) may be configured to apply voltages on the bit lines.

Referring toFIG.8, method800starts at operation802, in which a non-last programming pass is performed on a selected word line. The non-last programming pass includes one or more program loops. At least one of the program loops includes a programming operation, a NGS operation after the programming operation, and a verify operation after the NGS operation.

Referring back toFIGS.5A-5C,6A,6B,7A, and7B, a non-last programming pass, e.g.,502, may be performed on a selected word line, e.g.,610/WLn. The non-last programming pass may include one or more program loops, e.g.,506. At least one of the program loops includes a programming operation (e.g.,510), a NGS operation (e.g.,512) after the programming operation, and a verify operation (e.g.,514) after the NGS operation. The programming operation is first performed by applying a program voltage/pulse (e.g., VPGM1) on the selected word line. The NGS operation may be enabled in one or more program loops506(e.g., each program loop506). To enable the NGS operation, DSGs (e.g.,614) in fingers that include the memory cells coupled to the selected word line are each applied with a low voltage, e.g., VSS, as illustrated inFIG.7A. Bit lines of memory strings having memory cells not passed the verify operation and passed the verify operation are respectively applied with a high voltage (e.g., VDD) and a low voltage (VSS). The SSGs (e.g.,616) in the fingers are applied with a low voltage, e.g., VSS. The DSG transistors and the SSG transistors in the fingers may both be turned off. In the meantime, a low voltage, GND or negative voltage, is applied on the selected word line, and a positive voltage is applied on the word lines above and below the selected word line, as illustrated inFIGS.6B and7A. In some implementations, all memory cells coupled with the selected word line each undergoes a respective NGS operation. The verify operation may be performed on the memory cells coupled to the selected word line after the NGS operation by applying one or more verify voltages (e.g., VR1) on the selected word line.

In some implementations, the NGS operation is enabled in each program loop in the non-last programming pass. In some implementations, if the program loop is the first program loop, e.g., before any verify operations is performed, each memory cells coupled to the selected word line is treated as a memory cell that did not pass a respective verify operation prior to the NGS operation.

Referring back toFIG.8, method800proceeds to operation804, in which a last programming pass is performed on the selected word line. The last programming pass includes one or more program loops. The program loops may not include any NGS operations or include NGS operations enabled only on memory cells that did not pass respective verify operations immediately prior to the NGS operations.

Referring back toFIGS.5A-5C,6A,6B,7A, and7B, a last programming pass, e.g.,504, may be performed on the selected word line, e.g.,610/WLn. The last programming pass may include one or more program loops, e.g.,508. Different from the program loop in the non-last programming pass, the programming loop may not include any NGS operations on any memory cells or may include NGS operations enabled only on memory cells that did not pass respective verify operations immediately prior to the NGS operations. In some implementations, the NGS operations are not enabled on memory cells that passed the verify operations. In some implementations, NGS operation is inhibited between the programming operation (e.g.,520) and the following verify operation (524), as shown inFIG.5C. In some implementations, a NGS operation is enabled between the programming operation and the following verify operation, only on memory cells coupled to the selected word line and did not pass respective verify operations immediately prior to the NGS operations. The NGS operation may be enabled in one or more program loops508. The programming operations and the verify operation may be referred to the description ofFIG.5Cand the detailed descriptions are not repeated herein. To inhibit the NGS operation on the memory cells coupled to the selected word line and passed the verify operations, DSGs (e.g.,614) in fingers that include these memory cells are each applied with a low positive voltage (e.g., VDSG_P_L), as illustrated inFIG.7B. To enable the NGS operation on the memory cells coupled to the selected word line and did not pass the verify operations, DSGs (e.g.,614) in fingers that include these memory cells are each applied with a high positive voltage (e.g., VDSG_P_H), as illustrated inFIG.7B. Bit lines of memory strings having memory cells not passed the verify operation and passed the verify operation are respectively applied with a high voltage (e.g., VDD) and a low voltage (e.g., VSS). The SSGs (e.g.,616) in the fingers are applied with a low voltage and are turned off. In the meantime, a low voltage, e.g., negative or GND voltage, is applied on the selected word line, and a positive voltage is applied on the word lines above and below the selected word line, as illustrated inFIGS.6B and7A. The verify operation may be performed on the memory cells coupled to the selected word line after the NGS operation by applying one or more verify voltages (e.g., VR2) on the selected word line. In some implementations, operation804is performed by peripheral circuits302. It should be noted that, in various implementations, the verify operations (e.g.,514and/or524) may not be performed in all program loops.

Implementations of the present disclosure provide a memory device. The memory device includes an array of memory cells arranged in a plurality of rows, a plurality of word lines respectively coupled to the plurality of rows of the memory cells, and a peripheral circuit coupled to the word lines and configured to perform multi-pass programming on a selected row of memory cells coupled to a selected word line of the word lines. The multi-pass programming includes a plurality of programming passes. Each of the programming passes includes a programming operation and a verify operation. To perform the multi-pass programming, the peripheral circuit is configured to, in a non-last programming pass, perform a NGS operation on each memory cell in the selected row of memory cells between the programming operation and the verify operation.

In some implementations, the peripheral circuit includes a word line driver coupled to the plurality of word lines. In some implementations, to perform the NGS operation on the selected row of memory cells, the word line driver is configured to apply one of a negative voltage or GND voltage on the selected word line.

In some implementations, to perform the NGS operation on the selected row of memory cells, the word line driver is further configured to apply a positive voltage on a rest of the word lines.

In some implementations, the memory device further includes a plurality of bit lines. The array of memory cells includes a plurality of strings coupled to the plurality of bit lines, the strings each comprising a DSG transistor and a SSG transistor. The memory cells in the selected row are in a plurality of strings, respectively. To perform the NGS operation on the selected row of memory cells, the peripheral circuit is further configured to turn off the DSG transistor and the SSG transistor of each of the strings.

In some implementations, the peripheral circuit includes a bit line driver coupled to the plurality of bit lines and the word line driver is coupled to the DSG transistor via a DSG line. To turn off the DSG transistor of each of the strings, the bit line driver is configured to apply, of each of the strings, a bit line voltage on the respective bit line; and the word line driver is configured to apply, of each of the strings, a DSG voltage on the DSG transistor via the DSG line. A value of the DSG voltage minus the bit line voltage is lower than a threshold voltage of the DSG transistor.

In some implementations, the DSG voltage is a GND voltage.

In some implementations, in response to the row of memory cells having a memory cell not passing a respective verify operation immediately prior to the NGS operation, the bit line voltage is a positive voltage.

In some implementations, in response to the row of memory cells having a memory cell passing a respective verify operation immediately prior to the NGS operation, the bit line voltage is a GND voltage.

In some implementations, the peripheral circuit includes an SSG line coupled to the SSG transistor of each of the strings and a source driver coupled to the SSG line. The source driver is configured to apply a GND voltage on the SSG line.

In some implementations, to perform the multi-pass programming, the peripheral circuit is configured to, in a last programming pass, in response to one of the memory cells in the selected row passing a respective verify operation immediately prior to the last programming pass, inhibit a respective NGS operation on the one of the memory cells. In response to another one of the memory cells in the selected row not passing a respective verify operation immediately prior to the last programming pass, the peripheral circuit is configured to, in a last programming pass, perform a respective NGS operation on the other one of the memory cells.

In some implementations, to perform the multi-pass programming, the peripheral circuit is configured to, in the last programming pass, inhibit a respective NGS on each of the memory cells in the selected row of memory cells.

In some implementations, the NGS operation is performed between a respective programming operation and a respective verify operation.

In some implementations, the non-last programming pass includes a plurality of programming operations and a plurality of verify operations, and the NGS operation is performed after each of the programming operations and before a respective verify operation.

In some implementations, the memory device is a three-dimensional NAND Flash memory device.

Implementations of the present disclosure provide a method for operating a memory device comprising an array of memory cells arranged in a plurality of rows and a plurality of word lines respectively coupled to the plurality of rows of the memory cells. The method includes performing multi-pass programming on a selected row of memory cells, the multi-pass programming comprising a plurality of programming passes. Each of the programming passes includes a programming operation and a verify operation. Performing the multi-pass programming includes, in a non-last programming pass, performing a NGS operation on each memory cell in the selected row of memory cells between the programming operation and the verify operation.

In some implementations, performing the NGS operation on the selected row of memory cells includes applying one of a negative voltage or a GND voltage on a selected word line coupled to the selected row of memory cells.

In some implementations, performing the NGS operation on the selected row of memory cells includes applying a positive voltage on a rest of the word lines.

In some implementations, the memory device includes a plurality of bit lines, the array of memory cells comprising a plurality of strings coupled to the plurality of bit lines, the strings each comprising a DSG transistor and a SSG transistor. The memory cells in the selected row are in a plurality of strings, respectively. The method includes turning off the DSG transistor and the SSG transistor of each of the strings.

In some implementations, the method further includes applying a bit line voltage on the respective bit line; and applying a DSG voltage on the DSG transistor via a DSG line. A value of the DSG voltage minus the bit line voltage is lower than a threshold voltage of the DSG transistor.

In some implementations, the DSG voltage is a GND voltage.

In some implementations, the method further includes, in response to the row of memory cells comprising a memory cell not passing a respective verify operation immediately prior to the NGS operation, applying a positive voltage as the bit line voltage.

In some implementations, the method further includes, in response to the row of memory cells comprising a memory cell passing a respective verify operation immediately prior to the NGS operation, applying a GND voltage as the bit line voltage.

In some implementations, the method further includes applying a GND voltage on the SSG transistor.

In some implementations, the method further includes, in a last programming pass, in response to one of the memory cells in the selected row passing a respective verify operation immediately prior to the last programming pass, inhibiting a respective NGS operation on the one of the memory cells. In some implementations, the method further includes, in a last programming pass, in response to another one of the memory cells in the selected row not passing a respective verify operation immediately prior to the last programming pass, performing a respective NGS operation on the other one of the memory cells.

In some implementations, the method further includes, in the last programming pass, inhibiting a respective NGS on each of the memory cells in the selected row of memory cells.

In some implementations, the method includes performing the NGS operation between a respective programming operation and a respective verify operation.

In some implementations, the non-last programming pass includes a plurality of programming operations and a plurality of verify operations, and the method includes performing NGS operation after each of the programming operations and before a respective verify operation.

Implementations of the present disclosure provide a system. The system includes a memory device configured to store data and a memory controller coupled to the memory device and configured to control the memory device. The memory device includes an array of memory cells arranged in a plurality of rows, a plurality of word lines respectively coupled to the plurality of rows of the memory cells, and a peripheral circuit coupled to the word lines and configured to perform multi-pass programming on a selected row of memory cells coupled to a selected word line of the word lines. The multi-pass programming includes a plurality of programming passes. Each of the programming passes includes a programming operation and a verify operation. To perform the multi-pass programming, the peripheral circuit is configured to, in a non-last programming pass, perform a NGS operation on each memory cell in the selected row of memory cells between the programming operation and the verify operation.

In some implementations, the system further includes a host coupled to the memory controller.

In some implementations, the peripheral circuit includes a word line driver coupled to the plurality of word lines. To perform the NGS operation on the selected row of memory cells, the word line driver is configured to apply one of a negative voltage or a GND voltage on the selected word line.

In some implementations, to perform the NGS operation on the selected row of memory cells, the word line driver is further configured to apply a positive voltage on a rest of the word lines.

In some implementations, the memory device further includes a plurality of bit lines. The array of memory cells includes a plurality of strings coupled to the plurality of bit lines, and the strings each includes a DSG transistor and a SSG transistor. The memory cells in the selected row are in a plurality of strings, respectively. To perform the NGS operation on the selected row of memory cells, the peripheral circuit is further configured to turn off the DSG transistor and the SSG transistor of each of the strings.

In some implementations, the peripheral circuit includes a bit line driver coupled to the plurality of bit lines and the word line driver is coupled to the DSG transistor via a DSG line. To turn off the DSG transistor of each of the strings, the bit line driver is configured to apply, of each of the strings, a bit line voltage on the respective bit line. The word line driver is configured to apply, of each of the strings, a DSG voltage on the DSG transistor via the DSG line, a value of the DSG voltage minus the bit line voltage being lower than a threshold voltage of the DSG transistor.

In some implementations, the DSG voltage is a GND voltage.

In some implementations, in response to the row of memory cells having a memory cell not passing a respective verify operation immediately prior to the NGS operation, the bit line voltage is a positive voltage.

In some implementations, in response to the row of memory cells having a memory cell passing a respective verify operation immediately prior to the NGS operation, the bit line voltage is a GND voltage.

In some implementations, the peripheral circuit includes an SSG line coupled to the SSG transistor of each of the strings and a source driver coupled to the SSG line. The source driver is configured to apply a GND voltage on the SSG line.

In some implementations, to perform the multi-pass programming, the peripheral circuit is configured to, in a last programming pass, in response to one of the memory cells in the selected row passing a respective verify operation immediately prior to the last programming pass, inhibit a respective NGS operation on the one of the memory cells. In some implementations, to perform the multi-pass programming, the peripheral circuit is configured to, in response to another one of the memory cells in the selected row not passing a respective verify operation immediately prior to the last programming pass, perform a respective NGS operation on the other one of the memory cells.

In some implementations, to perform the multi-pass programming, the peripheral circuit is configured to, in the last programming pass, inhibit a respective NGS on each of the memory cells in the selected row of memory cells.

In some implementations, the NGS operation is performed between a respective programming operation and a respective verify operation.

In some implementations, the non-last programming pass includes a plurality of programming operations and a plurality of verify operations, and the NGS operation is performed after each of the programming operations and before a respective verify operation.

In some implementations, the memory device is a three-dimensional NAND Flash memory device.