Gate driver circuit for a half bridge or full bridge output driver stage and corresponding method for driving a half bridge or full bridge output driver stage

A gate driver circuit for a half bridge or full bridge output driver stage having a high side branch connected to one or more high side transistors and a low side branch connected to one or more low side transistors. A high side gate driver and a low side gate driver receive input signals at a low voltage level and output signals at a high voltage level as gate driving signals for the high side transistors and low side transistors. Each of the high side and the low side branches of the gate driver includes a set-reset latch having a signal output that is fed as a gate signal to the corresponding transistor of the half bridge or full bridge driver. A differential capacitive level shifter circuit receives the input signals at a low voltage level and outputs high voltage signals to drive the set and reset inputs of the set-reset latch.

BACKGROUND

Technical Field

The present description relates generally to gate driver circuits for a half bridge or full bridge output driver stage.

Description of the Related Art

Recently in the market of integrated high voltage drivers the need for high frequency signals is growing. In order to reach high performance, high slew rate and low latency in the chip between the low voltage input and the high voltage output have to be addressed.

In DC-DC Converters applications high slew rate edges help to obtain higher efficiency because they lower commutation losses, hence they reduce the power consumption and increase the performance of systems that use those circuits. Moreover, a higher frequency allows smaller inductances to be chosen, this meaning higher efficiency and system lower costs.

In Envelope Tracking applications, high frequency signals allow having a proper supply voltage envelope. In these systems, the supply voltage has to be continuously adapted to the load request, in order to allow having maximum efficiency of the system. This is particularly suitable for digital communication base-stations (mobile phones and also digital television are the main examples). Moreover, as long as fast reaction to the output level has to be addressed, also a low latency from digital low voltage input signal to analog high voltage output signals across the power stage has to be obtained.

In electromedical applications and in particular in ecographic machines, high voltage half bridges are required to drive the piezoelectric element to obtain an ultrasound wave. High current peaks are required.

All these characteristics have usually to be reached through dedicated design solutions.

InFIG. 1, in order to better understand the problems of half bridges or full bridges driver output stages operating with a high slew rate signal, it is shown a half bridge driver11comprising a high side, i.e., the side connected to the power supply voltage, branch and a low side, i.e., the side connected to the lower reference voltage, in particular ground, branch. The half bridge11includes a high side output transistor, in particular a high voltage pMOS or pMOSFET Mp, and a low side output transistor, in particular a nMOS or nMOSFET Mn, which are controlled through respective gate drivers10pand10n, which drive gate signals Gp and Gn applied to their respective gate electrodes. Each of the gate drivers10pand10nreceives as input a respective low level signal pLVor nLV, which is however referred to a high voltage ground, i.e., it is a shifted low level signal, inFIG. 1being shown only a waveform LSC schematizing the transient oscillation causing a logic state change in the input low signal pLVon the high side gate driver10p. Each of the gate drivers10pand10nis connected to a respective high voltage supply VPP for the high side or VNN for the low side and receives also a respective reference ground voltage referred to the respective high voltage supply voltage, VPP_RIF=VPP−VDD voltage or VNN_RIF=VNN−VDD voltage, VDD being the digital supply voltage, in particular the low level supply voltage.

With the reference12is indicated a parasitic inductance of a bonding wire, connecting the chip with a package pad13, between the half bridge11and the high side high voltage supply VPP, and it is also indicated a voltage generator14associated to the package pad13. With15is indicated a parasitic capacitance of the high side power MOSFET Mp, while with16are indicated capacitors representing capacitances existing between the supply line and the signal lines and between signal line and fixed voltages in the chip, and between the referred ground voltage VPP_RIF and fixed voltages in the chip. As already mentioned, for simplicity's sake, only parasitic elements corresponding to the high side are shown inFIG. 1, although dual parasitic elements are present in the low side.

With OLV is then indicated the overvoltage on the low voltage components relative to supply voltages VPP and reference ground voltage VPP_RIF, OV indicates a overvoltage on the signal on the gate of the high side MOSFET transistor Mp, UV a corresponding undervoltage, while OHV indicates a total overvoltage on the high voltage components at the output of the half-bridge11. I indicates the spike of the current flowing in the high side MOSFET Mp, causing the VPP oscillations.

The parasitic elements15and16determine several effects in presence of high slew rate signals.

In the first place, high slopes on the output of a half-bridge driver cause the current spike I profile to have huge peaks. This current spikes, flowing through any metal path presenting parasitic inductance15, such as bonding wires12and other bonding wires in the package, cause high oscillation on the supply voltages, which could:damage the related power-stage MOSFET Mp or Mn with exceeding gate source voltage Vgs when the MOSFET is in the ON state, with exceeding drain source voltage Vds when the MOSFET is OFF state,damage the low voltage logiccause spurious turning-on or turning-off of the power device,
because of a logic state change such as the one shown in signal LV at the gate driver11p. This could cause damage of the power stage due to cross conduction (high Side and low Side simultaneously ON) and could cause the half bridge to be in a high impedance state.

Several approaches have been taken in order to avoid the above indicated negative effects.

For instance, in order to obtain a low latency it is known to use a capacitive gate driver. This solution per se however determines sensitivity to high voltage supply oscillations. To avoid this latter problem it is known to reduce the parasitic inductances in the path, from the circuit to the filtering capacitance, for example by substituting bonding wires with bump bonding, although the results are usually not sufficient.

Also filtering the supply voltage with capacitance in the package or at a very small distance from the silicon usually turns out to be not sufficient. Further passive components in the package mean increased costs.

It is also known to split the supply path to the filtering passive components and to the generator. However, the bumps number and external passive components number increase, while a low area efficiency is obtained (bump-Limited silicon area and production costs)

Of course, also a slow turn-on and turn-off can be attempted with a lower working frequency and slew rate, but this determines limited functionalities, i.e., high propagation delay in the chip.

With regard to the problem of the spurious turn-on and turn-off, it is known to use a resistive level shifter which however is not always effective and causes high power consumption and slow commutations. A mask circuit instead is not applicable when several half bridges share the same power supply.

BRIEF SUMMARY

Various embodiments of the present disclosure may apply, e.g., to envelop tracking for 4G, 5G, mobile base stations, digital stations, digital television, DC-DC converters, ultrasound pulsers.

One or more embodiments provide a gate driver circuit for a half bridge or full bridge output driver stage, operating with high slew rate, which solves the drawbacks of the prior art.

The claims form an integral part of the technical teaching provided herein in relation to the various embodiments.

According to the solutions described herein, a circuit includes high side and the low side branches each including a set-reset latch with a signal output fed as a gate signal to the corresponding transistor of the half bridge or full bridge driver, a differential capacitive level shifter circuit receiving said input signals at a low voltage level and outputting high voltage signals to drive the set and reset inputs of the set-reset latch.

In variant embodiments, the circuit includes that said differential capacitive level shifter circuit includes a capacitive level shifter circuit portion receiving said input signals at a low voltage level and shifting said input signals at a low voltage level to a high voltage level and supplying them to a differential circuit with outputs feeding respectively the set and reset inputs of the set-reset latch.

In variant embodiments, the circuit includes that the set-reset latch feeds its output to the transistor through a drive chain comprising a plurality of inverting buffers defining taps, the differential circuit includes two feedback circuit modules configured to, when enabled, feed an additional current to the two outputs of the differential circuit, said circuit modules being enabled by respective feedback signals obtained from taps of said delay line, in particular the first feedback signal corresponding to a tap supplying the inverted output of the set-reset latch and the second feedback signal being obtained at the following tap.

In variant embodiments, the circuit includes a low level signal generator receiving as input a PWM signal and outputting said low level signals, configured to generate a delayed input signal delaying the input PWM signal of a given time delay, obtaining a low side signal to drive the low side transistor performing an OR Boolean operation on the delayed input signal and input PWM signal, and an obtaining a high side signal to drive the high side transistors, performing a AND Boolean operation on the delayed input signal and input PWM signal.

In variant embodiments, the circuit includes the generator that is further configured to obtain from the low side signal a low side low level on signal having an on trigger pulse of given length starting in correspondence of the rising edge of the low side signal and a low side low level off signal having an off trigger pulse of given length starting with the falling edge of the low side signal and a high side low level on signal and a high side low level off signal having trigger pulses and starting in correspondence of the rising edge and of the falling edge of the high side signal.

In variant embodiments, the circuit includes an additional synchronicity loop, which produces a synchronism PWM delayed signal which is synchronized and delayed with respect to the PWM signal, said additional synchronicity loop having as inputs from taps of the high side and low side delay lines a low side delayed signal and a high side delayed signal, said additional synchronicity loop being configured to obtain from said input signals set and reset signals of a second set-reset latch which outputs the synchronism PWM delayed signal.

In various embodiments, the solution described herein is also directed to a method for driving a half bridge or full bridge output driver stage using the gate driver circuit and performing the operations of the gate driver circuit in one of the above embodiments.

DETAILED DESCRIPTION

The ensuing description illustrates various specific details aimed at an in-depth understanding of the described embodiments. The embodiments may be implemented without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that various aspects of the embodiments will not be obscured.

The references used herein are intended merely for convenience and hence do not define the sphere of protection or the scope of the embodiments.

InFIG. 2it is shown a half bridge output driver stage11which is driven by a structure of gate driver21comprising a high side gate driver21pand a low side gate driver21n.

The structure of gate driver21receives two low level signals, a high side low level on signal pONLVand a high side low level off signal pOFFLVat respective low voltage drivers22poand22pf, which are connected to the digital voltage supply VDD and the corresponding ground GND. Low voltage high side drivers22poand22pfalong with corresponding low voltage low side voltage drivers22noand22nfare comprised in low level driving stage22.

Such signals are preferably generated by a signal generator30, which receives an input PWM signal PWM_in, shown in the timing diagram ofFIG. 7A, and generates the high side low level on signal pONLVand the high side low level signal pOFFLV. The signal generator30in general controls all the high side and low side signals. InFIG. 7Atiming diagrams of other signals generated by the signal generator30are shown. In particular the signal generator30generates a delayed input signal PWM_in_delayed, delaying the input PWM signal PWM_in, for instance by means of a delay line, of a given time delay Δ. Then the signal generator circuit30performs an OR on the delayed input signal PWM_in_delayed and input PWM signal PWM_in, obtaining a low side signal nLVto drive the low side MOSFET and an OR on the delayed input signal PWM_in_delayed and input PWM signal PWM_in, obtaining a high side signal nLVto drive the high side MOSFET, the latter having the rising edge delayed of time delay Δ and the falling edge anticipated of the time delay Δ in order to avoid having both the MOSFET of the half bridge11conducting at the same time. InFIG. 7Awith nOFF is indicated the transition corresponding to the nMOS Mn going in the off state, while nON indicates the on state. In the same way pOFF is indicated the transition corresponding to the power pMOS Mp going in the off state, while pON indicates the on state.

From the low side signal nLV, as shown inFIG. 7B, the generator30can obtain a low side low level off signal nOFFLVhaving a trigger pulse Hnf, of given length from high state to low state starting in correspondence of the off state nOFF of the nMOS Mn, at the rising edge of the low side signal nLV, and a low side low level on signal nONLVhaving a trigger pulse Hno of given length starting with the falling edge (state nON) of the nLVlow side signal. The same can be done with respect to the high side signal pLVobtaining a high side low level on signal pONLVand a high side low level off signal pOFFLVhaving trigger pulses Hpo and Hpf from the high to the low logic state starting in correspondence of the rising edge and of the falling edge of the high side signal pLV.

According to an aspect of the solution here described,

the low side low level signals pOFFLV, pONLVat the output of each such low level high side drivers22poand22pfare to be fed as set and reset signal to the set S and reset R inputs of a high side set-reset latch24prespectively, while the high side low level signals nOFFLV, nONLVat the output of each such low level low side drivers22noand22nfare to be fed to the set S and reset R inputs of a low side set-reset latch24n. The high side output Qp of the high side latch24pdrives the high side pMOS transistor Mp and the low side output Qn of the low side latch24ndrives the highs side nMOS transistor Mn.

However according to a further relevant aspect of the solution here described, in order to avoid spurious SET/RESET due to supply voltage oscillations, a high side differential capacitive level shifter circuit23pis interposed between the high side low level signals pOFFLV, pONLVand the high side set-reset latch24pand a high side differential capacitive level shifter circuit23nis interposed between the low side low level signals nOFFLV, nONLVand the low side set-reset latch24n.

Now, the high side differential capacitive level shifter circuit23ponly will be described, since the low side differential capacitive level shifter circuit23nhas the same structure, taken in account that is on the low side of the half bridge and pertains to a nMOS instead of a pMOS transistor.

Thus, in particular, the output of the two high side low level drivers22poand22pnis connected to one end of respective high voltage capacitors C1pand C2p, included the high side differential capacitive level shifter circuit23p. The other end of the high voltage capacitors C1pand C2pis the input of a differential circuit27p. Such differential circuit27poutputs a high voltage on signal pONHVand a high voltage off signal pOFFHV, which, as mentioned, are brought respectively to the set and reset inputs of the set-reset latch24p. The output Qp of the set-reset latch24pis supplied to a drive chain25p, comprising a plurality of inverting buffers26pwith increasing current capacity. In particular are shown five inverters26p, at each output of which a tap is defined at which a version the output Qp of the latch, alternatively inverted, i.e., negated, or not with respect to the output Qp of the latch can be drawn. At the end of the drive chain25pthe gate signal Gp is obtained which is applied to the gate of the high side MOSFET Mp. At the output of the first inverter26pof the drive chain25pan inverted signal Qinvis taken, which is fed back as on feedback signal GpONto a feedback input of the differential circuit27p. At the output of the second inverter26of the drive chain25pa buffered signal Qbuffis drawn, which is fed back as off feedback signal GpOFFto another feedback input of the differential circuit27p.

With reference toFIG. 2it has to be underlined that, although not shown in the drawing, from the low side drive chain25na on feedback signal GnONto a feedback input of the low side differential circuit27nand an off feedback signal GpOFFto another feedback input of the differential circuit27nare fed back, these feedback signals generated in the same manner described for the high side.

InFIG. 3Ait is shown a time diagram indicating the main signals of the circuit shown inFIG. 2. Such signals are of the type already discussed with reference toFIGS. 7A and 7B, i.e., the low level signals inputting the differential circuit have pulses Hpo, Hpf.

As shown, when the high side low level on signal pONLVgoes from high to low logic level for the duration of a trigger pulse Hpn, the output Qp of the high side set-reset latch24pgoes to high logic level, and the high gate signal Gp goes to low logic level. When the low side low level on signal pOFFLVgoes from high to low logic level for the duration of a pulse Hpo, the output Qp of the set-reset latch24pgoes to low level, and the high side gate signal Gp goes high.

InFIG. 3B, on the other hand, it is shown a high side low level off signal POFFLVand a high side low level on signal PONLVwhich can be used as input of the gate driver21, which are simply a copy of the PWM input signal PWM_in and of its negated signal, specifically of the OR-ed and AND-ed signal shown inFIG. 7A. The gate driver21however is able in the same way to switch the output Qp of high the set-reset latch24pon the falling edge of the high side low level on signal PONLV, such output Qp of the set-reset latch going to high level, while the high gate signal Gp goes low. This means that through the gate driver21is obtained that the half bridge switches when the input signals go to the low level, while it is insensitive to the high level of a triggering pulse Hpo, Hno like inFIG. 3A.

InFIG. 4it is detailed one of the differential circuits, the high side differential capacitive level shifter23p.

Circuit23pincludes a differential circuit27, in particular a differential amplifier, comprising four low voltage MOSFET, M1, M2, M3, M4. Two hysteresis circuit modules272oand272freceive respectively the on feedback signal GPONand the off feedback signal GPOFF, their outputs being connected to the outputs of the differential circuit27p, where high voltage on signal pONHVand high voltage off signal pOFFHV, which are the outputs of a differential circuit having the low voltage on signal pONIVand low voltage off signal pOFFLVas input. In other words, the differential circuit27phas a differential input, represented by the low voltage on signal pONIVand low voltage off signal pOFFLV. The differential circuit27penables the high voltage on signal pONHVand high voltage off signal pOFFHV.

InFIG. 4are also shown the low voltage drivers22, which are supplied with low voltage VDD supply, referred to the digital ground GND. Digital low level input signals are pONLVand pOFFLV. The output of each driver, as already indicated with reference toFIG. 2, is a low level signal lvs1, lvs2on an end or terminal of the high voltage capacitance C1por C2p, on the low voltage side of a level shifter222prepresented by the two capacitors. The high voltage capacitance C1por C2pconnect the low voltage portion, i.e., drivers22, of the circuitry with the high voltage portion represented by the differential amplifier27pand the hysteresis circuit modules272.

The differential amplifier27pis supplied with the high voltage supply VPP and the ground voltage VPP_RIF referred to the high voltage supply VPP (VPP_RIF=VPP−VDD). The input signals, hvs1and hvs2for the differential circuit are taken from the high voltage terminal of the high voltage capacitances C1por C2pof the level shifter222.

The input high voltage signal hvs1is connected to the gate and drain terminals of a pMOS M1, which is in trans diode configuration, and to the gate of a pMOS M4, which is source connected to the high voltage supply VPP. The other input high voltage signal hvs2is connected to the gate and drain terminals of the pMOS M2, in trans diode configuration and to the gate of the pMOS M3, source connected to the high voltage supply VPP. The drain of the pMOS M3is connected to the source of the pMOS M1, while drain of pMOS M4is connected to the source of pMOS M1. Drain of pMOS M1is connected to ground voltage VPP_RIF through a polarization current generator I4, while drain of pMOS M2is connected to ground voltage VPP_RIF through a polarization current generator I5. A polarization current generator I6, connected to the high voltage supply VPP, forces a current in the drain of pMOS M3, while in the same way a polarization current generator I7, connected to the high voltage supply VPP, forces a current in the drain of pMOS M4. Such drain of pMOS M3and M4are the output of the differential circuit231, on which high voltage signals pONHVand pOFFHVare formed.

The differential circuit27basically operates as follows. In static condition the low level signals lvs1and lvs2are at supply voltage VDD, the high level signals hvs1and hvs2are at the high voltage supply VPP for the high side. The capacitance C1p, C2pis charged and a voltage drop of (VPP−VDD) is present between its terminals (so that the capacitance might be a high voltage component if voltage VPP is a high voltage power supply).

The active signal that can be transmitted through the high voltage capacitance C1pand C2pis a negative edge. A negative edge of amplitude of the digital supply voltage VDD (signal from VDD to GND) on the low level signal lvs terminal of the capacitance causes a negative edge on the high level signal hvs terminal. It is to be noted that in practice, due the to the parasitic capacitances which operate a charge sharing with high voltage capacitances C1por C2p, the charge on the high voltage capacitances is slightly reduced during the signal edge with respect to the nominal value VPP−VDD. Therefore the amplitude of the edge at the terminals of high level signals hvs1e hvs2is slightly lower than VDD.

If a negative edge occurs, for example at the terminal on which the low level signal lvs1is (and at the input hvs1of the differential circuit), this negative level on signal hvs1, equal to the level on the gate of MOSFET M1, causes the source of MOSFET M1, which corresponds to the output on which is formed the high voltage on signal pONHVof the differential circuit, to follow and have a negative edge.

At the same time, the high level signal hvs1is also the gate of MOSFET M4, so that a negative edge on the high level signal hvs1causes also the drain of MOSFET M4, which corresponds to the output on which is formed the high voltage off signal pOFFHVof the differential circuit, to have a rising edge.

If a common mode input (i.e., negative edges at both the inputs) occurs at the gate of MOSFETs M1and M2, each effect on the output of the differential circuit, i.e., the drains of MOSFETs M1and M2, that would both have negative edges accordingly to the output, is cancelled by the effect of the same common mode input on MOSFETS M3and M4, that, in correspondence of the same negative edges on their gate, are causing positive edges on their drain. A common mode input as here described is usually the result of a disturbance.

Hysteresis circuit modules272add a hysteresis to the differential circuit27pand to the whole circuit23p. Each hysteresis circuit module272includes a respective pMOS, M5, M6, source connected to the high voltage supply VPP and drain connected with such drain of pMOS M3and M4which are the outputs of the differential circuit231. Their gates are respectively controlled by the on feedback signal GpONand the off feedback signal GpOFF, so that such pMOS M5and M6add an extra-current to the polarization current coming from current generators I6and I7. In other words, the inputs of the hysteresis circuits272are the on feedback signal GpONand the off feedback signal GpOFFrepresentative of the state of the high side gate signal Gp.

Thus, if the power pMOS Mp of the half bridge11is in OFF state:Gp=VPPGPOFF=VPPGPON=VPP_RIF

The extra current of pMOS M5is flowing to the output node on which is formed the high voltage on signal pONHV, so that a current greater than the sum of the current in pMOS M5and current generator I6have to be sinked from the pON_HVsignal node in order to have a voltage drop on it, and cause a Set S event in the set-reset latch24p, thus causing a logic state change.

If the power pMOS Mp of the half bridge11is ON:Gp=VPP_RIFGpOFF=VPP_RIFGpON=VPP

The extra current of pMOS M6is flowing to the output node on which is formed the high voltage off signal pOFFHV, so that a current greater than the sum of the current in pMOS M6and polarization current generator I7has to be sinked from node of signal POFFHVin order to have a voltage drop on it, and cause a reset R event in the set-reset latch24p, thus causing a logic state change.

The added current therefore makes it difficult to turn off the power pMOS when it is ON, (and vice versa), so that only a driving signal coming from the drivers22through the capacitive level shifter222is strong enough to cause a logic state change, while a differential interference from the high voltage supplies oscillation is not strong enough.

The hysteresis function implemented by the circuits272o,272fadds, in other words, a sort of inertia to the state change of the power MOSFET Mp and Mn, so that the state is changed only when commanded by a signal coming from the control logic, and not by disturbances. While the differential circuits prevents the action of common mode disturbances, the hysteresis circuits strengthen the gate driver with respects to possible asymmetries between the high and low branch of the circuit, due for instance to the technological aspects of the production process, favoring a transition between the logical levels with respect to the other.

Only if the power pMOS output transistor Mp on the high side is on, the MOSFET M6of the hysteresis circuit272fis on. When a negative edge occurs on the other input high voltage signal hvs2, which should make the high side power pMOS to go off, with the lowering of the voltage on the gate of MOSFET M2, also the voltage source of MOSFET M2attempts to decrease, however the hysteresis circuit272foperates against such decrease through the increase of the current in MOSFET M6, which is caused by the increase of its drain-source voltage VDS. It is noted that since it is driven the drain of MOSFET M6, not the gate, it is accepted a second order effect on the current value.

To obtain the hysteresis function it is more in general needed that the differential circuit23p,23nincludes two feedback hysteresis circuit modules,272o,272f, configured to, when enabled, feed an additional current to the two outputs of the differential circuit23p,23n, said circuit modules being enabled by respective feedback signals which logic state correspond to the logic state at the input of the output transistor of the driver stage11of the corresponding branch and its negated. With reference toFIG. 2, where only feedback signals GpONand GpOFFare shown for simplicity, the feedback hysteresis circuit modules272oand272freceive as input the signal at the gate of the high side output MOS Mp (high or low logic level of its gate) and its negated.

This can be obtained for instance, alternatively:using as feedback signal, i.e., GpONand GpOFF, the sole gate signal and performing the negation operation locally, in the hysteresis circuit272;using set-reset latches as latch24having both the Q output and the negated output Qn as feedback signals i.e., GpONand GpOFFbrought as input to the hysteresis circuit;exploiting the drive chain25p,25n, which includes a chain of inverting buffer26having size, i.e., current available at their output, but also input capacitance, which increase along the chain, and taking two consecutive output signals of two consecutive inverting buffers26, which are one the negated of the other. This is the solution shown inFIG. 2.

InFIG. 5it is shown an implementation of the circuit ofFIG. 4, in particular an implementation of the current generator I4, I5, I6, I7. As shown, generator I4is obtained by a current mirror formed by a nMOS MOSFET M00and MOSFET M04, while a nMOS MOSFET M05forms with nMOS MOSFET M00a second current mirror in parallel, which corresponds to current generator I5. As shown, such nMOS M00, M04and M05have their source connected to the high reference ground VPP_RIF, while the drain of M04is connected to the drain of pMOS M1and the drain of M05is connected to the drain of M2.

In the same way, generator I6is obtained by a current mirror formed by a pMOS MOSFET M03and pMOS MOSFET M06, while a pMOS MOSFET M07forms with pMOS MOSFET M03a second current mirror in parallel, which corresponds to current generator I7. As shown, such nMOS M03, M06and M07have their source connected to the high voltage supply VPP, while the drain of M06is connected to the source of pMOS M1and the drain of M07is connected to the source of M2. A first polarization nMOS M01is placed with the drain connected to the drain of M00and the gate and it is in trans diode configuration, with the gate short-circuited to the drain. A second polarization nMOS M02in trans diode configuration is connected with the drain to the source of M01and with the source to the drain of M03. This first and second polarization nMOS M01and M02are sized to set the working point of the current generators.

InFIG. 6it is shown a gate driver21associated to an additional synchronicity loop40, which produces a synchronism PWM delayed signal PWM_delay. InFIG. 6it is also shown the low level generator30already mentioned before with reference to the low level signals ofFIG. 2. As discussed, a PWM signal PWM_in enters the generator30, while the additional synchronicity loop40derives from the drive chains25pand25n, a low side delayed signal Qn_delay, after the third low side inverter26n, and a high side delayed signal Qp_delay, after the fourth high side inverter26p, which are the inputs of the loop40.

The synchronicity loop40includes a low voltage capacitor Cp an Cn on each of the high and low side inputs, connected at the input of a driver42por42n. The input is connected to the low voltage ground by a resistor Rp (Rn), so that low voltage capacitor Cp (Cn) brings a low level voltage delayed signal GpLV (GnLV) on the input of the driver42p(42n). The output of the high side driver42pis, after performing an OR with the PWM input signal PWM_in in a logic OR gate43p, fed to a set input of a set-reset latch44. In a dual manner, the output of the low side driver42nis, after performing an OR with the negated PWM input signal PWM_n signal in a logic OR gate43p, a fed to a reset input of a set-reset latch44, which outputs then the synchronism PWM delayed signal PWM_delay.

The corresponding signals are shown in the timing diagram ofFIGS. 8A and 8B.

InFIG. 8Awithin ellipses RE are indicated the rising edges of the input signal PWM_in. Such rising edge RE propagates through the various signals of gate driver21and synchronization loop40to produce the delayed rising edge of the PWM delayed signal PWM_delay. Ellipses FE indicate in the same way the falling edges, in particular of the input signal PWM_in and of the PWM delayed signal PWM_delay. InFIG. 8Ait is depicted the case corresponding toFIG. 3Bin which the circuit21switches on the rising edges of the PWM signal, but no pulses Hpo, Hpf, are generated for the low level driving signals.

The gate driver circuit just described obtains several advantages.

The gate driver circuit described performs level shifting from a low voltage digital input to the gates of the half-bridge with a fast level shifting, low power consumption by a capacitive level shifter

The gate driver circuit described in particular takes advantage of a differential topology to avoid logic state changes due to common mode supply voltage oscillations. The use of hysteresis increases margins in case of mismatch between the two branches of capacitive level shifter.

Of course, without prejudice to the principle of the embodiments, the details of construction and the embodiments may vary widely with respect to what has been described and illustrated herein purely by way of example, without thereby departing from the scope of the present embodiments, as defined the ensuing claims.

It should be noted that the bridge MOSFETs are preferably high voltage MOSFETs, however the gate driver circuit here described can be used with low voltage bridge MOSFETs, the high voltage being applied to their gate, while the power supply of the bridge is low, for example, the digital voltage supply.

Of course, the high voltage supply VPP for the high side and/or VNN for the low side can also be negative, and to the person skilled in the art it is apparent the dual structure of the gate driver that should be used in that case, which falls within the scope of protection of the gate drivers here described.