Method of manufacturing thin-film transistor, thin-film transistor substrate, and flat panel display apparatus

A method of manufacturing a thin-film transistor includes forming an oxide semiconductor on a substrate, stacking an insulating layer and a metal layer on the substrate to cover the oxide semiconductor, forming a photosensitive pattern on the metal layer, forming a gate electrode by etching the metal layer using the photosensitive pattern as a mask, where a part of the gate electrode overlaps a first oxide semiconductor region of the oxide semiconductor, forming a gate insulating film by partially etching the insulating layer using the photosensitive pattern as a mask, where the gate insulating film includes a first insulating region with a first thickness under the photosensitive pattern and a second insulating region with a second thickness less than the first thickness, and performing plasma processing on the gate insulating film so that a second oxide semiconductor region of the oxide semiconductor under the second insulating region becomes conductive.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. § 119 from, and the benefit of, Korean Patent Application No. 10-2015-0182791, filed on Dec. 21, 2015 in the Korean Intellectual Property Office, the contents of which are herein incorporated by reference in their entirety.

BACKGROUND

One or more embodiments are directed to a method of manufacturing a thin-film transistor (TFT), a TFT substrate, and a flat panel display apparatus, and more particularly, to a method of manufacturing a TFT using an oxide semiconductor, and a TFT substrate and a flat panel display apparatus that include a TFT manufactured using the method.

2. Description of the Related Art

A flat panel display apparatus such as an organic light-emitting diode display apparatus or a liquid-crystal display (LCD) apparatus includes at least one thin-film transistor (TFT), a capacitor, and a wiring line that connects the at least one TFT and the capacitor to each other. Each of the at least one TFT includes an active layer that includes a channel region, a source region, and a drain region, and a gate electrode on the channel region that is electrically insulated from the active layer by a gate insulating layer.

The active layer of the TFT is generally formed of a semiconductor material such as amorphous silicon or poly-silicon. When the active layer is formed of amorphous silicon, a mobility of the TFT is low, and thus a driving circuit may not operate at a high speed. When the active layer is formed of poly-silicon, although a mobility of the TFT is high, a threshold voltage is non-uniform and an additional compensation circuit is required. In addition, since a conventional method of manufacturing a TFT using low temperature poly-silicon (LTPS) uses an expensive laser heat treatment, investment and equipment management costs are high, particularly for large-sized substrates.

SUMMARY

According to one or more embodiments, a method of manufacturing a thin-film transistor (TFT) includes: forming an oxide semiconductor pattern on a substrate; sequentially stacking an insulating material layer and a metal layer on the substrate that covers the oxide semiconductor pattern; forming a photosensitive pattern on the metal layer; forming a gate electrode by etching the metal layer using the photosensitive pattern as a mask, where at least one part of the gate electrode overlaps a first oxide semiconductor region of the oxide semiconductor pattern; forming a gate insulating film by partially etching the insulating material layer using the photosensitive pattern as a mask, where the gate insulating film includes a first insulating region with a first thickness under the photosensitive pattern and a second insulating region with a second thickness less than the first thickness; and performing plasma processing on the gate insulating film where a second oxide semiconductor region of the oxide semiconductor pattern under the second insulating region becomes conductive.

The plasma processing uses a hydrogen-containing gas.

The second thickness may range from about 500 Å to about 1000 Å.

The method may further include: removing the photosensitive pattern; forming an interlayer insulating film on the gate electrode and the gate insulating film; forming a contact hole through which a part of the second oxide semiconductor region is exposed, by etching the gate insulating film and the interlayer insulating film; and forming an electrode through the contact hole that is electrically connected to the exposed part of the second oxide semiconductor region.

Forming the gate electrode may include wet etching the metal layer using the photosensitive pattern as a mask, where a side surface of the gate electrode is disposed inward from a side surface of the photosensitive pattern.

Forming the gate insulating film may include partially dry etching the insulating material layer by using the photosensitive pattern as a mask, where an edge of the photosensitive pattern corresponds to a boundary between the first and second insulating regions.

The first insulating region may include a central portion covered by the gate electrode and an edge portion not covered by the gate electrode.

Performing the plasma processing may include: removing the photosensitive pattern; and performing plasma processing using the gate electrode as a mask to form the oxide semiconductor pattern, including the first oxide semiconductor region under the central portion of the first insulating region, a third oxide semiconductor region under the edge portion of the first insulating region, and the conductive second oxide semiconductor region under the second insulating region, wherein the third semiconductor region has a resistance less than a resistance of the first oxide semiconductor region and greater than a resistance of the second oxide semiconductor region.

According to one or more embodiments, a thin-film transistor (TFT) substrate includes: a substrate; an oxide semiconductor pattern disposed on the substrate and that includes a semiconducting first oxide semiconductor region and a conductive second oxide semiconductor region; a gate insulating film disposed on the substrate that covers the oxide semiconductor pattern and that includes a first insulating region with a first thickness and a second insulating region with a second thickness less than the first thickness; a gate electrode disposed on the first insulating region, where at least a part of the gate electrode overlaps the first oxide semiconductor region; and an interlayer insulating film disposed on the gate insulating film that cover the gate electrode, where the second oxide semiconductor region became conductive from a hydrogen gas based plasma process performed on the gate electrode and gate insulating film

The TFT substrate may further include an electrode disposed on the interlayer insulating film that is electrically connected to the second oxide semiconductor region through a contact plug that penetrates the interlayer insulating film and the gate insulating film.

The second thickness may range from about 500 Å to about 1000 Å.

The first insulating region may include a central portion covered by the gate electrode and an edge portion not covered by the gate electrode.

The oxide semiconductor pattern may include a third oxide semiconductor region disposed between the first and second oxide semiconductor regions and that has a resistance less than a resistance of the first oxide semiconductor region and greater than a resistance of the second oxide semiconductor region.

According to one or more embodiments, a flat panel display apparatus includes: a substrate; an oxide semiconductor pattern disposed on the substrate and that includes a semiconducting first oxide semiconductor region and a conductive second oxide semiconductor region; a gate insulating film disposed on the substrate that covers the oxide semiconductor pattern and that includes a first insulating region with a first thickness and a second insulating region with a second thickness less than the first thickness; a gate electrode disposed on the first insulating region, where at least a part of the gate electrode overlaps the first oxide semiconductor region; an interlayer insulating film disposed on the gate insulating film that covers the gate electrode; and an electrode disposed in the interlayer insulating film that is electrically connected to the second oxide semiconductor region through a contact plug that penetrates the interlayer insulating film and the gate insulating film.

The second oxide semiconductor region may become conductive from a hydrogen gas based plasma process performed on the gate electrode and gate insulating film.

The second thickness may range from about 500 Å to about 1000 Å.

The first insulating region may include a central portion covered by the gate electrode and an edge portion not covered by the gate electrode.

The oxide semiconductor pattern may include a third oxide semiconductor region disposed between the first and second oxide semiconductor regions and that has a resistance less than a resistance of the first oxide semiconductor region and greater than a resistance of the second oxide semiconductor region.

The flat panel display apparatus may further include: a pixel electrode electrically connected to the electrode; a counter electrode that faces the pixel electrode; and an organic emission layer disposed between the pixel electrode and the counter electrode.

The flat panel display apparatus may further include: a pixel electrode electrically connected to the electrode; a counter electrode that faces the pixel electrode; and a liquid crystal layer disposed between the pixel electrode and the counter electrode.

DETAILED DESCRIPTION

Embodiments of the inventive concept may include various embodiments and modifications, and embodiments thereof will be illustrated in the drawings and will be described herein in detail. The features of the inventive concept and methods of achieving the features will be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the inventive concept are shown. The inventive concept may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein.

It will be understood that when a layer, region, or element is referred to as being “formed on”, another layer, region, or element, it can be directly or indirectly formed on the other layer, region, or element.

Sizes of elements may be exaggerated for convenience of explanation.

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. In the drawings, the same elements may be denoted by the same reference numerals, and a repeated explanation thereof will not be given.

FIG. 1is a cross-sectional view of a thin-film transistor (TFT) substrate100according to an embodiment.

Referring toFIG. 1, a TFT substrate100includes a substrate110, an oxide semiconductor pattern115, a gate insulating film120, a gate electrode125, an interlayer insulating film130, and an electrode135. The oxide semiconductor pattern115is disposed on the substrate110, and includes a first oxide semiconductor region115awith semiconducting properties and a second oxide semiconductor region115bwith conductive properties. The gate insulating film120is disposed on the substrate110to cover the oxide semiconductor pattern115. The gate insulating film120includes a first insulating region120awith a first thickness da and a second insulating region120bwith a second thickness db that is less than the first thickness da. The gate electrode125is disposed on the first insulating region120a, and at least a part of the gate electrode125overlaps the first oxide semiconductor region115a. The interlayer insulating film130is disposed on the gate insulating film120to cover the gate electrode125. The electrode135is disposed on the interlayer insulating film130and is electrically connected to the second oxide semiconductor region115bthrough a contact plug CP that penetrates the interlayer insulating film130. The oxide semiconductor pattern115and the gate electrode125may constitute a top gate-type TFT.

The TFT substrate100is part of an apparatus that includes at least one TFT on the substrate110. The TFT substrate100may be a flat panel display apparatus in which pixels that include TFTs are arranged in a matrix. For example, the TFT substrate100may be an organic light-emitting diode display apparatus or a liquid crystal display (LCD) apparatus.

The substrate110supports the entire TFT substrate100and maintains the stiffness of the TFT substrate100. The substrate110may have a flat top surface and may be formed of a transparent insulating material. For example, the substrate110can be formed of glass. However, embodiments of the inventive concept are not limited thereto, and the substrate110may be formed of a plastic material such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyimide (PI), polyethersulfone (PES), or polyacrylate (PAR). The substrate110may be formed of an opaque material such as a metal or a carbon fiber, and to realize a flexible display apparatus, the substrate110may be formed of a flexible plastic material such as a PI film.

In addition, an auxiliary film, such as a barrier film, a blocking film, and/or a buffer film may be disposed on the substrate110. The auxiliary film planarizes a top surface of the substrate110and prevents the penetration of impurities. The auxiliary film may be formed of an inorganic insulating material, and may have a single-layer structure or a multi-layer structure. The auxiliary film may prevent the oxide semiconductor pattern115that is to be subsequently stacked from being contaminated with impurities from the substrate110, thereby protecting the oxide semiconductor pattern115and improving interfacial properties.

The oxide semiconductor pattern115is disposed on the substrate110, and includes the first oxide semiconductor region115aand the second oxide semiconductor region115b.

The first oxide semiconductor region115ahas semiconducting properties, and corresponds to a channel region of each TFT. The first oxide semiconductor region115aoverlaps the gate electrode125.

The second oxide semiconductor region115bhas conductive properties, and is disposed both sides of the first oxide semiconductor region115a. The second oxide semiconductor regions115bcorrespond to a source region and a drain region of the TFT. The second oxide semiconductor region115bmay also function as a wiring line for electrically connecting the TFT to another TFT or another element. The second oxide semiconductor region115bmay obtain its conductive properties from a plasma process that uses a hydrogen-containing gas.

According to an embodiment, oxide semiconductor pattern115includes an oxide semiconductor material. The oxide semiconductor material may include an oxide of at least one of indium (In), gallium (Ga), stannum (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). For example, the oxide semiconductor material may include at least one of zinc oxide (ZnO), zinc-tin oxide (ZTO), zinc-indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium-gallium-zinc oxide (IGZO), and indium-zinc-tin oxide (IZTO).

Since a TFT using an oxide semiconductor as an active layer has a higher mobility than a TFT using silicon (Si) as an active layer, additional ion doping for increasing mobility is not required. In addition, since a TFT that includes an oxide semiconductor has a polycrystalline and amorphous structure even at room temperature, an additional annealing process is not needed and a TFT that includes an oxide semiconductor material can be formed using a low-temperature process. In addition, since the active layer can be formed using sputtering, etc., a TFT that includes an oxide semiconductor material can be used to manufacture a large-sized substrate, as material costs may be low.

The gate insulating film120is disposed on the substrate110to cover the oxide semiconductor pattern115. The gate insulating film120includes the first insulating region120awith the first thickness da and the second insulating region120bwith the second thickness db less than the first thickness da.

According to an embodiment, the first insulating region120acorresponds to the first oxide semiconductor region115a, and the gate electrode125is disposed on the first insulating region120a. A part, of the first insulating region120a, such as a central portion, is covered by the gate electrode125, and a remaining part of the first insulating region120a, such as an edge portion, is not covered by the gate electrode125.

According to an embodiment, the second insulating region120bhas the second thickness db and covers the second oxide semiconductor region115band a portion of the substrate110not covered by the oxide semiconductor pattern115.

According to an embodiment, the gate insulating film120is formed of a silicon oxide (SiO2). In this case, the second thickness db of the second insulating region120bmay range from about 500 Å to about 1000 Å. However, embodiments of the inventive concept are not limited thereto, and the gate insulating film120may be formed of an insulating material other than SiO2, and may have a single-layer structure or a multi-layer structure.

According to an embodiment, the gate insulating film120can improve the interfacial properties of the oxide semiconductor pattern115and can prevent impurities from penetrating into the oxide semiconductor pattern115.

According to an embodiment, the gate electrode125is disposed on the first insulating region120aof the gate insulating film120, and at least a part of the gate electrode125overlaps the first oxide semiconductor region115a. The gate electrode125may be formed of a metal and may have a single-layer structure or a multi-layer structure. The gate electrode125may be formed by stacking, for example, a copper (Cu) film and titanium (Ti) layer.

According to an embodiment, the interlayer insulating film130is formed of an inorganic insulating material and has a single-layer structure or a multi-layer structure. Alternatively, the interlayer insulating film130may be formed of an organic insulating material using spin coating, etc. In addition, the interlayer insulating film130may have a multi-layer structure in which an organic insulating material and an inorganic insulating material are alternately disposed.

According to an embodiment, the interlayer insulating film130and the gate insulating film120have a contact hole CH through which a portion of the second oxide semiconductor region115bof the oxide semiconductor pattern115is exposed.

According to an embodiment, the electrode135is disposed on the interlayer insulating film130and is electrically connected to the second oxide semiconductor region115bthrough the contact plug CP in the contact hole CH in the interlayer insulating film130and the gate insulating film120. The electrode135includes a source electrode135aand a drain electrode135b.

According to an embodiment, the electrode135is formed of, for example, a metal, and may have a single-layer structure or a multi-layer structure.

According to a present embodiment, the gate insulating film120includes the first insulating region120awith the first thickness da and the second insulating region120bwith the second thickness db less than the first thickness da. The gate insulating film120is entirely disposed between the gate electrode125and the second oxide semiconductor region115b.

In a conventional method of making the second oxide semiconductor region115bof the oxide semiconductor pattern115conductive, a part of a gate insulating film120is removed to expose the second oxide semiconductor region115b. In this case, the gate insulating film is disposed only between the gate electrode125and the first oxide semiconductor region115a, and an interlayer insulating film covers the second oxide semiconductor region115b. In this case, an interface between the gate insulating film and the interlayer insulating film, which is matched to a boundary between the first and second oxide semiconductor regions115aand115b, is formed. In this structure, if a high voltage is applied between the gate electrode125and the second oxide semiconductor region115b, current can leak along the interface between the gate insulating film and the interlayer insulating film between the gate electrode125and the second oxide semiconductor region115b. In addition, since the interface between the gate insulating film and the interlayer insulating film is structurally weaker than a continuous insulating film, if a high voltage is applied to the gate electrode125, the interface between the gate insulating film and the interlayer insulating film may be destroyed, thereby causing the TFT to break down.

According to embodiments, however, since the gate insulating film120covers the entire oxide semiconductor pattern115, current leakage between the gate electrode125and the second oxide semiconductor region115bcan be prevented. In addition, since the continuously formed gate insulating film120is structurally stronger than an interface between the gate insulating film120and the interlayer insulating film130, the gate insulating film120is not easily destroyed, thereby reducing the risk of a TFT breakdown.

In addition, since the second oxide semiconductor region115bis made conductive using plasma processing with a hydrogen-containing gas, the second oxide semiconductor region115bdoes not need to be exposed. For hydrogen to penetrate into the second oxide semiconductor region115bthrough plasma processing, the second thickness db of the second insulating region120bon the second oxide semiconductor region115bis less than the first thickness da of the first insulating region120a. Such a structure can be formed without an additional mask.

FIGS. 2A through 2Hare cross-sectional views that sequentially illustrate a method of manufacturing a TFT, according to an embodiment.

Referring toFIG. 2A, a first oxide semiconductor pattern115′ is formed on the substrate110.

The substrate110has a flat top surface and may be formed of a transparent insulating material, such as glass. Alternatively, the substrate110may be formed of a flexible plastic material such as a PI film to realize a flexible display apparatus. Alternatively, the substrate110may be formed of an opaque material such as a metal or a carbon fiber.

According to an embodiment, to prevent impurities from penetrating from the substrate110into the first oxide semiconductor pattern115′ that is to be subsequently stacked, and thus to protect the first oxide semiconductor pattern115′ and improve its interfacial properties, an auxiliary film, such as a barrier film, a blocking film, and/or a buffer film, may be disposed on the substrate110. The auxiliary film may be formed of an insulating oxide such as silicon oxide (SiOx), silicon nitride (SiNx), aluminum oxide (Al2O3), hafnium oxide (HfO3), or yttrium oxide (Y2O3) to have a multi-layer structure or a single-layer structure. The auxiliary film may be formed by any appropriate deposition method, such as plasma-enhanced chemical vapor deposition (PECVD), atmospheric pressure CVD (APCVD), or low-pressure CVD (LPCVD).

According to an embodiment, the first oxide semiconductor pattern115′ is formed on the substrate110. An oxide semiconductor layer115′ is formed on the substrate110, after which the first oxide semiconductor pattern115′ is formed using photolithography and etching, as shown inFIG. 2A.

The oxide semiconductor material may include an oxide of at least one of In, Ga, Sn, Zr, V, Hf, Cd, Ge, Cr, Ti, and Zn. For example, the oxide semiconductor material may include at least one of ZnO, ZTO, ZIO, InO, TiO, IGZO, and IZTO. For example, the oxide semiconductor material may include In, Ga, and Zn in an atomic ratio of 2:2:1.

However, embodiments of the inventive concept are not limited thereto, and the oxide semiconductor material may include a quaternary metal oxide such as a In—Sn—Ga—Zn—O-based material, a ternary metal oxide such as a In—Ga—Zn—O-based material, a In—Sn—Zn—O-based material, a In—Al—Zn—O-based material, a Sn—Ga—Zn—O-based material, a Al—Ga—Zn—O-based material, a Sn—Al—Zn—O-based material, or a Cd—Sn—O-based material, a binary metal oxide such as a In—Zn—O-based material, a Sn—Zn—O-based material, a Al—Zn—O-based material, a Zn—Mg—O-based material, a Sn—Mg—O-based material, or a In—Mg—O-based material, or a unary metal oxide such as a In—O-based material, a Sn—O-based material, a Zn—O-based material, a Ti—O-based material, or a Cd—O-based material. A In—Ga—Zn—O-based oxide semiconductor may include at least In, Ga, and Zn, irrespective of the composition ratio, and may also include one or more elements other than In, G, and Zn.

Referring toFIG. 2B, according to an embodiment, a first insulating layer120′ and a first metal layer125′ are sequentially stacked on the substrate110to cover the first oxide semiconductor pattern115′.

According to an embodiment, the first insulating material layer120′ is deposited on the substrate110on which the first oxide semiconductor pattern115′ is formed. The first insulating material layer120′ may be formed of SiO2. However, embodiments of the inventive concept are not limited thereto, and the first insulating material layer120′ may be formed of an inorganic insulating material such as silicon nitride (SiNO, aluminum oxide (Al2O3), copper oxide (CuOx), terbium oxide (Tb4O7), yttrium oxide (Y2O3), niobium oxide (Nb2O5), or praseodymium oxide (Pr2O3) in a single-layer structure or a multi-layer structure. The first insulating material layer120′ may be formed by any appropriate deposition method, such as PECVD, APCVD, or LPCVD.

According to an embodiment, the first metal material layer125′ is deposited on the first insulating material layer120′. The first metal material layer125′ is formed of at least one metal material selected from silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). The first metal material layer125′ can be formed by stacking, for example, a Cu film and a Ti film.

Referring toFIG. 2C, according to an embodiment, a photosensitive pattern PR is formed on the first metal material layer125′.

According to an embodiment, a photosensitive organic material layer is stacked on the first metal material layer125′, after which the photosensitive pattern PR can be formed by exposure or development using a photomask, as shown inFIG. 2C.

Examples of a photosensitive organic material include an olefin-based organic material, an acryl-based organic material, and an imide-based organic material. For example, the photosensitive organic material may include PI. The photosensitive organic material may be a positive photosensitive material of which an exposed portion is removed, or a negative photosensitive material of which an exposed portion is hardened.

Referring toFIG. 2D, according to an embodiment, the first metal material layer125′ is etched using the photosensitive pattern PR as a mask. The first metal layer125′ can be isotropically wet etched using an etchant. As a result, the gate electrode125corresponding to the photosensitive pattern PR can be formed as shown inFIG. 2D. At least a part of the gate electrode125overlaps the first oxide semiconductor region115aof the oxide semiconductor pattern115ofFIG. 1.

According to an embodiment, the first metal material layer125′ is etched more than the mask during the wet etching. As a result, a side surface of the gate electrode125is disposed inward from a side surface of the photosensitive pattern PR.

Referring toFIG. 2E, according to an embodiment, the first insulating material layer120′ is partially etched using the photosensitive pattern PR as a mask. A portion of the first insulating material layer120′ disposed under the photosensitive pattern PR is not etched, and a portion of the first insulating material layer120′ not covered by the photosensitive pattern PR is slightly etched. As a result, the first insulating region120aof the gate insulating film120with the first thickness da is formed under the photosensitive pattern PR along with the second insulating region120bwith the second thickness db less than the first thickness da.

When the gate insulating film120is formed of SiO2, the second thickness db of the second insulating region120branges from about 500 Å to about 1000 Å. When the second thickness db is less than or equal to 500 Å, the first oxide semiconductor region115aof the oxide semiconductor pattern115may become conductive during a subsequent hydrogen gas plasma process. In addition, when the second thickness db is greater than or equal to 1000 Å, the second oxide semiconductor region115bof the oxide semiconductor pattern115may not become conductive from the subsequent hydrogen gas plasma process.

According to an embodiment, isotropic dry etching is performed on the first insulating material layer120′ using the photosensitive pattern PR as a mask. Due to the isotropic dry etching, a boundary between the first insulating region120aand the second insulating region120bmay correspond to an edge of the photosensitive pattern PR. Accordingly, the gate electrode125is disposed on a part, that is, a central portion, of the first insulating region120aand a remaining part, that is, an edge portion, of the first insulating region120awill be exposed.

Referring toFIG. 2F, according to an embodiment, plasma processing is performed on the structure ofFIG. 2Eon the substrate110. The plasma processing may be performed using a hydrogen-containing gas.

As a result, the oxide semiconductor pattern115that includes a semiconducting first oxide semiconductor region115aand a conductive second oxide semiconductor region115bis formed.

According to an embodiment, the second oxide semiconductor region115bof the oxide semiconductor pattern115becomes conductive due to the hydrogen plasma. The oxide semiconductor material of the second oxide semiconductor region115bbecomes conductive by being reduced due to the hydrogen plasma. In this case, since the photosensitive pattern PR functions as a mask, the first oxide semiconductor region115adisposed under the first insulating region120adoes not become conductive due to the plasma.

The second insulating region120bhaving the relatively small second thickness db is disposed on the second oxide semiconductor region115b, Accordingly, hydrogen can diffuse through the second insulating region120bduring plasma processing into the second oxide semiconductor region115b, and the oxide semiconductor material of the second oxide semiconductor region115bis reduced by reacting with the hydrogen. For the oxide semiconductor material to become conductive using plasma processing, the second thickness db should be less than or equal 1000 Å.

If the second thickness db is less than 500 Å, the first oxide semiconductor region115aof the oxide semiconductor pattern115awill also become conductive during the hydrogen plasma processing. As a result, the entire oxide semiconductor pattern115can be made conductive, thereby causing the TFT to fail to function.

Plasma processing is a process of modifying chemical or physical properties of a material's surface allowing high energy plasma particles to collide with the material's surface. According to an embodiment of the inventive concept, a hydrogen-containing gas can be used for plasma processing. The gas may further contain at least one of argon, helium, xenon, nitrogen, nitric oxide, and oxygen, in addition to hydrogen.

Since an oxide semiconductor is reduced by having plasma processing performed thereon, an oxygen vacancy in the oxide semiconductor is induced and increased. The increased oxygen vacancy increases a carrier concentration of the oxide semiconductor material. As a result, the oxide semiconductor material becomes conductive and easily conducts electricity therethrough.

Referring toFIG. 2G, according to an embodiment, the photosensitive pattern PR is removed from the gate electrode125. The photosensitive pattern PR may be removed by ashing.

Next, according to an embodiment, a second insulating material layer is stacked on the gate insulating film120and the gate electrode125. The second insulating material layer may include an inorganic insulating material such as SiO2, SiNx, Al2O3, CuOx, Tb4O7, Y2O3, Nb2O5, or Pr2O3. The second insulating material may have a single-layer structure or a multi-layer structure. The second insulating material layer may be formed using any appropriate deposition method, such as PECVD, APCVD, or LPCVD.

Alternatively, the second insulating material layer may be formed of at least one organic insulating material selected from polyimide, polyimide, acrylic resin, benzocyclobutene, and phenolic resin using spin coating, etc. In addition, the second insulating material layer may have a multi-layer structure in which an organic insulating material and an inorganic insulating material are alternately disposed.

Next, according to an embodiment, photolithography and etching are performed on the the second insulating material layer and gate insulating film120, and the interlayer insulating film130is formed with the contact hole CH through which a part of the second oxide semiconductor region115bis exposed.

Referring toFIG. 2H, according to an embodiment, a second metal layer135′, including the contact plug CP that fills the contact hole CH in the gate insulating film120and the interlayer insulating film130is stacked on the interlayer insulating film130. The contact plug CP is electrically connected to the second oxide semiconductor region115b.

The second metal material layer135′ may be formed of at least one of Ag, Mg, Al, Pt, Pb, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, and Cu. The second metal material layer135′ may have a single-layer structure or a multi-layer structure.

Referring toFIG. 1, the electrode135is formed that is electrically connected to the second oxide semiconductor region115bthrough the contact plug CP in the contact hole CH, by performing photolithography and etching on the second metal material layer135′. The electrode135includes the source electrode135aand the drain electrode135b.

FIG. 3is a cross-sectional view of a TFT substrate100aaccording to another embodiment.

Referring toFIG. 3, a TFT substrate100aincludes the substrate110, an oxide semiconductor pattern116, the gate insulating film120, the gate electrode125, the interlayer insulating film130, and the electrode135.

The TFT substrate100ais substantially the same as the TFT substrate100ofFIG. 1except for the oxide semiconductor pattern116. A repeated explanation of the same elements as those inFIG. 1will not be given.

The oxide semiconductor pattern116includes a first oxide semiconductor region116a, second oxide semiconductor regions116b, and third oxide semiconductor regions116c. The first oxide semiconductor region116ais disposed between the second oxide semiconductor regions116b. Each third oxide semiconductor region116cis disposed between the first oxide semiconductor region116aand one of the second oxide semiconductor regions116b.

According to an embodiment, resistance of the third oxide semiconductor region116cis less than a resistance of the first oxide semiconductor region116aand greater than a resistance of the second oxide semiconductor region116b. Since the second oxide semiconductor region116bis conductive, the second oxide semiconductor region116bhas a very low resistance. Since the first oxide semiconductor region116ais a semiconductor, the first oxide semiconductor region116ahas a resistance between that of a conductor and an insulator. Since the third oxide semiconductor region116chas a resistance that is less than that of the first oxide semiconductor region116aand greater than that of the second oxide semiconductor region116b, a strong electric field may be prevented from forming between the first oxide semiconductor region116aand the second oxide semiconductor region116b. Accordingly, the possibility that characteristics of the TFT, such as a threshold voltage of the TFT, change due to a strong electric field can be reduced, thereby improving reliability.

As described above, the gate insulating film120includes the first insulating region120awith the first thickness da and the second insulating region120bwith the second thickness db less than the first thickness da. The gate electrode125is disposed on a part of the first insulating region120a. The first insulating region120aincludes a central portion covered by the gate electrode125and an edge portion not covered by the gate electrode125.

According to an embodiment, the first oxide semiconductor region116ais disposed under the central portion of the first insulating region120acovered by the gate electrode125. That is, a boundary between the first oxide semiconductor region116aand the third oxide semiconductor region116ccan be defined by the edge of the gate electrode125.

According to an embodiment, the third oxide semiconductor region116cis disposed under the edge portion of the first insulating region120anot covered by the gate electrode125. That is, a boundary between the third oxide semiconductor region116cand the second oxide semiconductor region116bcan be defined by a stepped portion of the gate insulating film120, that is, a boundary between the first insulating region120aand the second insulating region120b.

According to an embodiment, the second oxide semiconductor region116bis disposed under the second insulating region120b.

FIG. 4is a cross-sectional view that illustrates a method of manufacturing a TFT ofFIG. 3.

The TFT of the TFT substrate100acan be formed using processes of a method described with reference toFIGS. 2A through 2E. Next, a process ofFIG. 4can be performed. Next, processes of the method described with reference toFIGS. 2G through 2Hcan be performed.

First, referring toFIG. 2E, the gate insulating film120is formed that includes the first insulating region120aand the second insulating region120b, by partially etching the first insulating material layer120′ using the photosensitive pattern PR as a mask.

Referring toFIG. 4, according to an embodiment, the photosensitive pattern PR is removed from the gate electrode125. The photosensitive pattern PR can be removed by ashing.

According to an embodiment, plasma processing is performed on a structure formed on the substrate110. The plasma processing can be performed using a hydrogen-containing gas. As a result, the oxide semiconductor pattern116is formed, including the first oxide semiconductor region116aunder a central portion of the first insulating region120acovered by the gate electrode125, the third oxide semiconductor region116cunder an edge portion of the first insulating region120anot covered by the gate electrode125, and the conducting second oxide semiconductor region116cunder the second insulating region120b.

According to an embodiment, the third oxide semiconductor region116ccorresponds to the edge portion of the first insulating region120aand is disposed between the first oxide semiconductor region116aand the second oxide semiconductor region116b.

According to an embodiment, the second oxide semiconductor region116band the third oxide semiconductor region116cof the oxide semiconductor pattern116become conductive due to a hydrogen-based plasma. Oxide semiconductor materials of the second oxide semiconductor region116band the third oxide semiconductor region116cbecome conducting by being reduced by the hydrogen-based plasma. In this case, since the gate electrode125functions as a mask, the first oxide semiconductor region116adisposed under the central portion of the first insulating region120aunaffected by the plasma.

The second insulating region120b, which as a relatively small second thickness db, is disposed on the second oxide semiconductor region116b. Accordingly, hydrogen can diffuse through the second insulating region120bduring plasma processing into the second oxide semiconductor region116b, and the hydrogen reacts with and reduces the oxide semiconductor material of the second oxide semiconductor region116b.

The first insulating region120a, which has a relatively greater first thickness da, is disposed on the third oxide semiconductor region116c. Accordingly, less hydrogen can diffuse through the first insulating region120athan that through the second insulating region120b. A smaller amount of hydrogen can diffuse into the third oxide semiconductor region116cthan into the second oxide semiconductor region116b. Accordingly, although the third oxide semiconductor region116calso becomes conductive, since the third oxide semiconductor region116cis less conductive than the second oxide semiconductor region116b, the third oxide semiconductor region116chas a resistance greater than that of the second oxide semiconductor region116b.

Referring back toFIG. 2G, according to an embodiment, the interlayer insulating film130, which has the contact hole CH through which a part of the second oxide semiconductor region116bis exposed, is formed on the gate insulating film120and the gate electrode125.

FIG. 5is a cross-sectional view of an organic light-emitting diode display apparatus200according to an embodiment.

Referring toFIG. 5, an organic light-emitting diode display apparatus200includes a substrate210, an oxide semiconductor pattern215, a gate insulating film220, a gate electrode225, an interlayer insulating film230, an electrode235, a pixel electrode245, a pixel defining film250, an organic emission layer255, and a counter electrode260.

The oxide semiconductor pattern215is disposed on the substrate210, includes a semiconducting first oxide semiconductor region215aand a conductive second oxide semiconductor region215b, and corresponds to the oxide semiconductor pattern115ofFIG. 1. The oxide semiconductor pattern215may be replaced with the oxide semiconductor pattern116ofFIG. 3. The gate insulating film220is disposed on the substrate210to cover the oxide semiconductor pattern215, includes a first insulating region220awith a first thickness da and a second insulating region220bwith a second thickness db less than the first thickness da, and corresponds to the gate insulating film120ofFIG. 1.

The gate electrode225is disposed on the first insulating region220a, has at least a part that overlaps the first oxide semiconductor region215a, and corresponds to the gate electrode125ofFIG. 1. The interlayer insulating film230is disposed on the gate insulating film220to cover the gate electrode225and corresponds to the interlayer insulating film130ofFIG. 1. The electrode235is disposed on the interlayer insulating film230, is electrically connected to the second oxide semiconductor region220bthrough a contact plug CP that penetrates the interlayer insulating film230and the gate insulating film220, and corresponds to the electrode135ofFIG. 1. The electrode235includes a source electrode235aand a drain electrode235b.

The substrate210, the oxide semiconductor pattern215, the gate insulating film220, the gate electrode225, the interlayer insulating film230, and the electrode235respectively correspond to the substrate110, the oxide semiconductor pattern115, the gate insulating film120, the gate electrode125, the interlayer insulating film130, and the electrode135ofFIGS. 1 and 3, and thus a repeated explanation thereof will not be given.

According to an embodiment, the organic light-emitting display apparatus200includes a protective layer240that covers the interlayer insulating film230and the electrode235. The protective layer240has a via-hole VH through which a part of the electrode235is exposed. The via-hole VH can be formed using photolithography and etching.

The protective layer240may be formed of an organic insulating material selected from polyimide, polyamide, acrylic resin, benzocyclobutene, and phenolic resin using spin coating, etc. According to an embodiment, the protective layer240has a flat top surface, which can prevent defects of a subsequently formed organic light-emitting diode device.

According to an embodiment, the organic light-emitting diode display apparatus200includes the pixel electrode245formed on the protective layer240, the counter electrode260, and the organic emission layer255. The pixel electrode245can be used as an anode of an OLED and the counter electrode260can be used as a cathode of an OLED. However, embodiments of the inventive concept are not limited thereto, and the pixel electrode245and the counter electrode260may be respectively a cathode and an anode.

The OLED can emit light at a luminance corresponding to a driving current received from the TFT.

According to an embodiment, the pixel electrode245is formed on the protective layer240and is electrically connected to the TFT, for example, the source electrode235a, through the via-hole VH in the protective layer240. The pixel electrode245may be formed of any material suitable for an emission type organic light-emitting display apparatus200. For example, when the organic light-emitting display apparatus200is a bottom-emission display apparatus in which an image is displayed in a direction toward the substrate210or a dual-emission display apparatus in which an image is displayed in both directions, the pixel electrode245can be formed of a transparent metal oxide. The pixel electrode245may include at least one material selected from transparent conductive oxides such as ITO, IZO, ZnO, and In2O3. When the organic light-emitting display apparatus200is a top-emission display apparatus in which an image is displayed in a direction away from the substrate210, the pixel electrode245further includes a reflective electrode formed of a light-reflecting material. Although the pixel electrode245and the electrode235are separate elements inFIG. 5, according to an embodiment, the pixel electrode245and the electrode235may be integrally formed with each other.

According to an embodiment, the organic light-emitting display apparatus200includes a pixel-defining film250that defines a light-emitting portion by exposing a part of the pixel electrode245on the protective layer240.

According to an embodiment, the organic emission layer255is disposed on the part of the pixel electrode245exposed by the pixel-defining film250. The organic emission layer255is disposed between the pixel electrode245and the counter electrode260. At least one functional layer, such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (HTL), and an electron injection layer (EIL), in addition to the organic emission layer255, may be disposed on the pixel electrode245and may have a single-layer structure or a multi-layer structure.

According to an embodiment, the counter electrode260faces the pixel electrode245. The counter electrode260can be formed as a common electrode by being entirely deposited on the substrate210. The counter electrode260may be formed by thinly depositing one of Ag, Mg, Al, Pt, Pb, Au, Ni, Nd, Ir, Cr, Li, Ca, lithium fluoride (LiF), and/or a compound thereof. The counter electrode260may include a reflective electrode and/or a semi-transparent electrode, based on a light emitting direction.

According to an embodiment, the organic light-emitting display apparatus200further includes a capping layer disposed on the counter electrode260that includes an inorganic material to protect the counter electrode260. The organic light-emitting display apparatus200includes an encapsulation substrate270that faces the substrate210and encapsulates the substrate210using an encapsulating member, to prevent oxygen and moisture from being externally introduced. Alternatively, the organic light-emitting display apparatus200may include a thin film encapsulation layer formed by alternately stacking at least one organic film and at least one inorganic film, instead of the encapsulation substrate270.

FIG. 6is a cross-sectional view of an LCD apparatus300according to an embodiment.

Referring toFIG. 6, an LCD apparatus300includes a substrate310, an oxide semiconductor pattern315, a gate insulating film320, a gate electrode325, an interlayer insulating film330, an electrode335, a protective layer340, a pixel electrode345, a liquid crystal layer350, and a counter electrode355.

The oxide semiconductor pattern315is disposed on the substrate310, includes a semiconducting first oxide semiconductor region315aand a conducting second oxide semiconductor region315b, and corresponds to the oxide semiconductor pattern115ofFIG. 1. The oxide semiconductor pattern315may be replaced with the oxide semiconductor pattern116ofFIG. 3. The gate insulating film320is disposed on the substrate310to cover the oxide semiconductor pattern315, includes a first insulating region320awith a first thickness da and a second insulating region320bwith a second thickness db less than the first thickness da, and corresponds to the gate insulating film120ofFIG. 1.

The gate electrode325is disposed on the first insulating region320a, has at least a part that overlaps the first oxide semiconductor region315a, and corresponds to the gate electrode125ofFIG. 1. The interlayer insulating film330is disposed on the gate insulating film330to cover the gate electrode325and corresponds to the interlayer insulating film130ofFIG. 1. The electrode335is disposed on the interlayer insulating film330, is electrically connected to the second oxide semiconductor region320bthrough a contact plug CP that penetrates the interlayer insulating film330and the gate insulating film320, and corresponds to the electrode135ofFIG. 1. The electrode335includes a source electrode335aand a drain electrode335b.

The substrate310, the oxide semiconductor pattern315, the gate insulating film320, the gate electrode325, the interlayer insulating film330, and the electrode335respectively correspond to the substrate110, the oxide semiconductor pattern115, the gate insulating film120, the gate electrode125, the interlayer insulating film130, and the electrode135ofFIGS. 1 and 3, and thus a repeated explanation thereof will not be given.

According to an embodiment, the LCD apparatus300further includes the protective layer340, the pixel electrode345, the liquid crystal layer350, the counter electrode355, a planarization layer360, a color filter365, a black matrix370, and a counter substrate380.

According to an embodiment, the protective layer340covers the interlayer insulating film330and the electrode335, and has a via-hole VH through which a part of the electrode335is exposed. The protective layer240can be formed of an organic insulating material using spin coating, etc., and has a flat top surface.

According to an embodiment, the liquid crystal layer350is disposed between the substrate310on which a TFT is formed and the counter substrate380on which the counter electrode355and the color filter365are formed.

According to an embodiment, the black matrix370, the color filter365, the planarization layer360, and the counter electrode355are sequentially formed on the counter substrate380.

According to an embodiment, the black matrix370blocks light that is unnecessary to form an image. The black matrix370can block light leakage of light caused by abnormal liquid crystal molecule behaviors along a pixel edge or mixed colors along a color filter365edge.

According to an embodiment, the color filter365imparts color to light that propagates through a pixel. The color filter365can be one of a red filter, a green filter, and a blue filter.

According to an embodiment, the planarization layer360covers the black matrix370and the color filter365. The planarization layer360can be formed of an organic insulating material using spin coating, etc., and has a flat top surface.

According to an embodiment, the counter electrode355is formed of a transparent conductive material, and may be referred to as a common electrode. For example, the counter electrode355may be formed of a transparent conductive metal oxide such as ITO, IZO, or ITZO.

According to an embodiment, the pixel electrode345receives a pixel signal from the source electrode335aof the TFT and a potential difference is formed between the pixel electrode345and the counter electrode355. Once the potential difference is formed, the molecules of the liquid crystal layer350rotate due to dielectric anisotropy, which controls the amount of light than can propagate through the liquid crystal layer350. Light is incident to the the liquid crystal layer350from a light source. Thus the amount of light emitted from the liquid crystal layer350can be adjusted by adjusting the potential difference between the pixel electrode345and the counter electrode355, thereby enabling light with a desired luminance and a desired color to be emitted.

According to a method of manufacturing the TFT according to one or more embodiments, since a gate insulating film having thicknesses that differ according to regions entirely covers an oxide semiconductor pattern, current may be prevented from leaking between a gate and a drain, which can reduce the risk of a breakdown of the TFT. Since no mask is added, manufacturing costs can be decreased. Accordingly, the TFT can reliably operate with a long lifespan.