Structure to monitor arcing in the processing steps of metal layer build on silicon-on-insulator semiconductors

The present invention addresses detection of charge-induced defects through test structures that can be easily incorporated on a wafer to detect charge-induced damage in the back-end-of-line processing of a semiconductor processing line. A test macro is designed to induce an arc from a charge accumulating antenna structure to another charge accumulating antenna structure across parallel plate electrodes. When an arc of a predetermined sufficient strength is present, the macro will experience a voltage breakdown that is measurable as a short. The parallel plate electrodes may both be at the floating potential of the microchip to monitor CMP-induced or lithographic-induced charge failure mechanisms, or have one electrode electrically connected to a ground potential structure to capture charge induced damage, hence having the capability to differentiate between the two.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The field of the invention relates to semiconductor technology, and specifically to structure to monitor arcing between metal layers. More specifically, the present invention addresses charge-induced defects through adequate test structures that can be easily implemented in back-end-of-line processing.

2. Description of Related Art

Integrated circuit chips are exposed to various potential differences during processing making them vulnerable to charge induced damage. For example, silicon-on-insulator (SOI) technology in 300 mm semiconductor fabrication is prone to arcing damage and shorting. The primary problem from this phenomenon is defects caused by sprays of foreign material (debris) and the discharge damage itself. Damage to gates within the chip may also cause the chip to be nonfunctional. One of the mechanism by which charge accumulated on the wafer in the SOI technologies are discharged is generally through a guard ring, which is connected to the substrate and thus ground via the body (BI) contact through the buried oxide layer. The potential difference created by both the floating circuit net and the crack stop, which is connected to the substrate through the BI contact, increases as thicker dielectric stacks are fabricated through back-end-of-line (BEOL) processing. The greater potential build-up causes arcing or dielectric breakdown between the layers that typically results in electrical shorting and damage.

The primary method of detecting this type of charge damage has been historically through expensive and time-consuming optical inspection techniques. Since the defect normally manifests itself as an intermittent problem, it is difficult without testing to diagnosis a large sample size of components. Furthermore, the defect is generally detectable with optical inspection only if a large discharge is generated. More subtle problems will often remain undetected. Consequently, there remains a need in the industry to provide a test structure that allows the discharge to be detected more readily through standard in-line test methods.

Charge damage has been a key yield detractor in 90 nm technology. The absence of a suitable structure for monitoring this yield-detracting mechanism through electrical test prevents a manufacturer from employing an early detection scheme. As such, the manufacture is often unaware of the problem until a significant amount of hardware has been impacted by this failure mode. The present invention attempts to address charge-induced defects through adequate test structures that can be easily implemented.

SUMMARY OF THE INVENTION

Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a test structure macro to initiate arcing-induced failures and allow for measurements thereof.

It is another object of the present invention to provide a test structure macro to monitor charge-induced arcing and shorting from the microcircuit chip to the guard ring.

A further object of the invention is to provide a test structure macro to monitor charge-induced arcing and shorting across different segments of a floating microcircuit chip so that one can differentiate between a charge-damage induced shorting and shorting induced due to other reasons.

The above and other objects, which will be apparent to those skilled in the art, are achieved in the present invention, which is directed to a test structure for monitoring discharges during semiconductor wafer processing comprising: a parallel plate electrode having a first electrode plate electrically connected on one end to a first metal structure, and a second electrode plate adjacent the first electrode plate, connected on one end to a second metal structure; a first metal probe pad electrically connected to the first metal structure; a second metal probe pad electrically connected to the second metal structure; such that charge is accumulated on the metal structures and a conductive circuit is established between the probe pads after arcing occurs across the parallel plate electrode. The test structure further comprises electrically connecting an opposite end of the second metal probe pad to a ground potential structure. The ground potential structure may include a guard ring. The test structure may also include a dielectric between the parallel plate electrodes. Spacing between the parallel plate electrode plates is selected to adjust for arcing.

In a second aspect, the present invention is directed to a test structure for monitoring discharges during semiconductor wafer processing comprising: a first metal probe pad having an electrical connection to a first metal antenna structure on the semiconductor wafer; and a second metal probe pad having an electrical connection on the semiconductor wafer to a second metal antenna structure: a first parallel plate electrode having an electrical connection to the first metal antenna structure, and a second parallel plate electrode having an electrical connection to the second metal antenna structure, the second parallel plate electrode adjacent the first parallel plate electrode, such that the parallel plate electrodes form a conductive path between the first and second metal probe pads when charge accumulates on the metal antenna structures and an arc occurs. The test structure may further include the first and second metal probe pads and the first and second metal antenna structures fabricated using techniques from the semiconductor wafer processing and capable of being electrically monitored during and after the processing The metal antenna structures may be fabricated on the wafer and held at a floating voltage potential.

In a third aspect, the present invention is directed to a test structure for monitoring discharges during semiconductor wafer processing comprising: a first parallel plate electrode electrically connected on one end to a first metal plate antenna; and a second parallel plate electrode electrically connected on one end to a second plate antenna; a first metal probe pad connected to the first metal plate antenna; and a second metal probe pad connected to the second metal plate antenna; the parallel plate electrodes adjacent one another forming a path for arcing therebetween.

DESCRIPTION OF THE PREFERRED EMBODIMENT(S)

Charge-induced damage is a common phenomenon in the back-end-of-line processing steps in a semiconductor processing line. Charging mechanisms in silicon-on-insulator (SOI) wafers are different from those on bulk wafers since in SOI wafers there are many circuits where the body of transistors, such as MOSFETs, are generally at a floating potential. Different types of back-end-of-line charging damage have been observed during the manufacture of SOI wafers. One such type is charge damage near the guard ring of the product. This damage is generally observed by inspection, and is usually later confirmed by Transfer Electron Microscope (TEM), a high resolution, time consuming, expensive microscopy. The confirmation, however, cannot be performed in-situ, and is an inefficient way to verify the failure. In many instances, multiple failures are manifested within a production lot before charge-induced failures can be identified and corrected. Charge-induced damage is of particular interest since the guard ring is one of the largest metal layers connected to the SOI wafer through the body (BI) contact. The observed failure mechanism is an arcing between the guard ring and the other metal layers of the chip, ultimately causing a conductive carbon trace, which in turn forms an electrical short. This finding indicates that it is more probable for the body of the SOI wafer to contact the large metal layers than other floating body structures, making the device more susceptible to arcing and charging.

Test macros are monitor structure designed to detect failure mechanisms of the product chip before the actual chip is fully built. These usually happen to be much smaller in size and much more simple in design, but are designed in a way so that their design is sensitive to particular types of failure mechanisms. These special designs for test macros make it easy to detect particular types of failure mechanisms, whereas, the product chip may lack similar diagnostic features for narrowing down to a particular failure mechanism for chip failures.

FIG. 1Adepicts an SOI wafer2having multiple layers and a plurality of gate structures4.FIG. 1Bdepicts a magnification of gate structure4of the SOI wafer ofFIG. 1Aafter arcing-induced damage. As shown, the top portion of gate structure4is obliterated by the arc. Arrow A correlates the gate structure4ofFIG. 1Ato the same damaged gate structure depicted inFIG. 1B.

Since most test macros in SOI technology are floating-body macros, they will generally not exhibit an electrical signature of this failure mechanism. As a result, any arc-induced short to ground would go undetected during macro testing. Therefore, it is necessary to induce this failure mode by designing a macro that is sensitive to arcing to understand and address the root cause. The present invention proposes a macro particularly designed to induce an arc to ground. In this manner, if an arc of a predetermined strength is present, the macro will experience a voltage breakdown that is measurable as a short. The test circuit is easily adapted to measure this short. By regulating the dimensions and characteristics of the test circuit and calculating the total number or percentage of these fails, a determination may then be made regarding the presence of an arc of sufficient strength to damage the circuit.

FIG. 2depicts an arc-inducing macro5of the present invention. A top view of wafer10is shown with metal plates12on top surface14. These metal plates act as an “antenna” and provide a large area for charge to accumulate before it can discharge through the thin metal lines forming parallel plate electrodes18for causing an arc. Two metal probe pads1,2are connected to metal plates12. Metal probe pad2is electrically connected to the BI (not shown) located underneath top surface14. Preferably, the electrical connection is made by constructing an array of vias16within probe pad2to the guard ring. The two parallel plate electrodes18separate the two large metal plates12, and act as “arcing electrodes”. The gap distance20and type of dielectric between parallel plates18are predetermined such that arcs of certain strength (voltage) will breakdown and cause a short between the plates, while arcs of less strength will not breakdown. The predetermined breakdown voltage is calculated to be capable of registering a short across parallel plates18if an arc occurs, and correspondingly sufficient to damage circuitry on the chip. Test circuitry is designed to contact and measure the resistance of probe pad1with respect to probe pad2. If an arc of sufficient strength has exceeded the breakdown voltage of gap20, a short will occur within the dielectric. The continuity between probe pad1and newly shorted probe pad2is measurable, making the arc damage detectable.

The proposed macro is accomplished by having one metal plate connected to the SOI wafer body through the body (BI) contact while holding a second plate at a floating potential. Any shorting due to arcing between the plates will be empirically measured by electrically testing the structure for a short. This scheme represents a much more powerful detection scheme than PLY testing since the proposed test may be performed on every lot and over many sites, while PLY tests can only be performed on a limited number of wafers. Additionally, PLY tests are much less cost efficient. The proposed scheme is more likely to observe subtle defects that a PLY inspection would generally miss.

To distinguish an arcing-induced short from a chemical-mechanical-polishing (CMP)-induced or lithographic-induced short, the present invention employs a second test structure macro30, preferably fabricated in close proximity to the first macro test structure.FIG. 3depicts second test structure macro30for measuring CMP-induced and/or lithographic-induced shorts. In second test structure macro30, both metal probe pads21,22are held at a floating potential on wafer32. Once again, a parallel plate electrode24is configured between metal plates12. The parallel plates24are separated by gap26at a predetermined distance, having a known dielectric therebetween, such that an arc of sufficient strength will breakdown and cause a short. However, because the probe pads are floating, any arcing or shorting must mimic an arc formed on the chip surface between chip circuitry held at a floating potential, and not between the chip circuitry and the guard ring or ground.

Both of the test macro structures5,30are prone to the same CMP-induced or lithographic-induced shorting mechanism; however, test structure macro5having one end of its parallel plates connected to the guard ring will be more prone to arcing-induced shorting. The yield delta between these two test schemes provides information of the extent of the arcing-induced or charging-induced shorts.

In the second test structure macro30, metal probe pad22is not connected to the substrate. However, the two metallic plates12could still be shorted out due to a non-arcing related failure mechanism. This ultimately creates a shorting mechanism between the pads. This could happen in macro5as well, even in the absence of any arcing damage. If that indeed happens then the difference in the percentage or number of fails between macros30and5will give information regarding the damage done solely due to arcing and charge damage related failure mechanism, since macro5is prone to both arching-related and litho- and CMP-related failure mechanism, but macro30is prone to CMP- and litho-related failure mechanisms only.

FIG. 4depicts a cross-sectional view of the first test structure macro5on layered wafer10. A top metal wire surface layer40is shown with a gap42therebetween. An insulator layer44supports metal wire surface layer40and resides underneath it. The insulating material fills gap42and provides the requisite dielectric breakdown characteristic for the gap. One segment of metal wire surface layer40is held at the same potential as the chip (not shown) on the wafer, while another segment of metal wire surface layer40connects to the body (BI) silicon layer46through via48. This connection represents the grounding of one side of the parallel plate capacitor to ground potential, which is equivalent of that of the guard ring. An SOI layer50is located between silicon layer52and silicon layer46.

FIG. 5depicts a cross-sectional view of the second test structure macro30on layered wafer32. Top metal wire surface60is shown with a gap62therebetween. As similarly depicted in the first test structure macro, an insulating layer64supports the metal wire surface60. However, in this macro, there is no via to electrically connect on segment of metal wire surface60to the body silicon layer66, which would otherwise depict an electrical connection to ground potential and is equivalent to the potential of the guard ring. In this embodiment, each segment of top metal wire surface60is floating with respect to silicon layer66or SOI layer68. In this manner, CMP-induced or lithographic-induced failure mechanisms are modeled and detected by the parallel plate macro with its floating electrodes.

The dual test structure macros may be used collectively as a vehicle to develop a new BEOL process and to define various ground rules of a new technology, as well as an excellent in-line monitor for the production of wafers.