Semiconductor memory device and method of manufacturing the same

A semiconductor memory device and manufacturing method, including a bit line connector and a lower electrode connector that respectively connect a bit line and a capacitor lower electrode of the device to active areas of a semiconductor substrate. The connectors are formed using a line-type self-aligned photoresist mask pattern positioned on an interlevel dielectric layer formed on the substrate, which exposes only a portion of the dielectric layer corresponding to a source region and which extends in a direction which a gate electrode extends, to provide a misalignment margin. The bit line connector and the lower electrode connector are respectively formed by one-time mask processes. A contact hole for the bit line connector in a cell area, and a contact hole for a metal wiring plug in a peripheral area are simultaneously formed, alleviating etching burden during subsequent forming of a metal wiring pad.

BACKGROUND OF THE INVENTION

The present application claims priority under 35 U.S.C. § 119 to Korean Application No. 2000-55208 filed on Sep. 20, 2000, which is hereby incorporated by reference in its entirety for all purposes.

1. Field of the Invention

The present invention relates to a semiconductor memory device and manufacturing method thereof, and more particularly, to a dynamic random access memory device having a capacitor-over-bit line (COB) structure capable of forming a connector for connecting a bit line or a lower electrode of a capacitor with a semiconductor substrate by a one-time mask process, while providing a misalignment margin during the connector formation process, and a manufacturing method thereof.

2. Description of the Related Art

As the integration density of semiconductor devices such as dynamic RAMs (DRAMs) continues to increase, a bit line is formed under a capacitor. In association therewith, a lower electrode connector for connecting a lower electrode of a capacitor with an active area (e.g., a source region of a transistor) of a semiconductor substrate on which a DRAM is formed, and a bit line connector for connecting a bit line and another active area are formed by a two-time mask process, respectively. In this case., the lower electrode connector and the bit line connector, respectively, include a contact plug directly contacting an active area of a semiconductor substrate, and a contact pad disposed between the contact plug and the lower electrode or the bit line.

Since the contact pad and the contact plug forms a contact surface, the overall resistance of the lower electrode connector and the bit line connector increases, which in turn degrades the operating speed of a semiconductor memory device. Furthermore, to form the lower electrode connector and the bit line connector, the step of manufacturing and removing a photo mask is repeatedly performed three or four times, thereby complicating the overall process and increasing the possibility that a semiconductor substrate will suffer damage due to the repeatedly performed mask removing step. Furthermore, as the integration density of a semiconductor memory device continues to increase, there is a limit to securing a misalignment margin when forming contact holes for the contact pad and contact plug described above.

The above problems will now be described with reference toFIGS. 1–8. A semiconductor memory device shown inFIGS. 1,2,3,6and8is divided into a cell area C and a peripheral circuit area P, while only the cell area C of the semiconductor memory device is shown inFIGS. 4,5and7. Hereinafter, a bit line contact plug and a lower electrode contact plug denote a portion directly connected with an active area of a substrate and a gate electrode, respectively, and a bit line contact pad and lower electrode contact pad denote a portion connecting the bit line contact plug with a bit line formed on the substrate and a portion connecting the lower electrode contact plug with a lower electrode, respectively. Either the bit line contact plug (or lower electrode contact plug) or the bit line contact pad (or lower electrode contact pad), or if there are the contact pad and the contact plug, the combination thereof is defined as a bit line contact connector (or lower electrode contact connector).

InFIG. 1, an active area of a semiconductor substrate100is defined by isolation regions102. The isolation regions may be formed by shallow trench isolation (STI) or local oxidation of silicon (LOCOS) technique, and in the case of a highly integrated semiconductor memory device, a STI technique is preferably used. Next, an insulating layer, a polysilicon layer, a metal layer or a metal silicide layer, and a capping layer are formed over the entire surface of the semiconductor substrate100on a cell area C and a peripheral circuit area P and patterned to form the gate electrodes G1, G2, G3, G4, G5, G6, G7, and G8and capping patterns111. Each gate electrode G1, G2, G3, G4, G5, G6, G7, or G8is composed of a gate electrode insulating pattern104, a polysilicon pattern108, and a metal pattern or a metal silicide pattern110. Then, using each gate electrode G1, G2, G3, G4, G5, G6, G7, or G8as a mask, ions having the opposite conductive type to the semiconductor substrate100are implanted into the semiconductor substrate100to form drain and source regions103and105.

The capping layer or the capping pattern111may be composed of a material having high selectivity with respect to an interlevel dielectric layer112which will later be formed, such as for example a silicon nitride layer, an aluminum oxide layer, or a tantalum oxide layer. Subsequently, an insulating layer is formed over the entire surface of the semiconductor substrate100on which the gate electrodes G1, G2, G3, G4, G5, G6, G7, or G8been formed, and etched back to form a spacer106along the sidewall of the gate electrodes G1, G2, G3, G4, G5, G6, G7, or G8and capping pattern111. The spacer106may be composed of a material having high selectivity with respect to the interlevel dielectric layer112. Here, the structures comprised of the gate electrodes G1, G2, G3, G4, G5, G6, G7, or G8, the capping pattern111, and the spacers106are referred to as gate electrode structures.

Meanwhile, after having formed the spacer106, impurity ions of high concentration are implanted into the semiconductor substrate100to form the drain and source regions103and105having a lightly doped drain and source (LDD) structure, thereby completing first through eighth transistors T1, T2, T3, T4, T5, T6, T7, and T8. The first through fifth transistors T1, T2, T3, T4, and T5are formed on the cell area C, while the sixth through the eight transistors T6, T7, and T8are formed on the peripheral circuit area P. Hereinafter, the drain and source regions having a LDD structure are referred to as drain and source regions.

InFIG. 1, the transistors T1, T2, T3, and T4, or T6and T7between the isolation regions102have channels of the same conductive type. The source region105of the second transistor T2is in common with that of the first transistor T1, and the drain region103of the second transistor T2is in common with that of the third transistor T3. Meanwhile, the fifth transistor T5may have the same or opposite conductive type of channel. To have a channel of the opposite conductive type to a substrate, a well (not shown) of the opposite conductive type to the substrate is formed within the substrate to form source and drain regions of an adjacent transistor.

A planarized first interlevel dielectric layer112is formed over the entire surface of the semiconductor substrate100on the cell area C and the peripheral circuit area P on which the spacer106has been formed. Subsequently, the first interlevel dielectric layer112on the cell area C is etched to form first contact holes exposing the drain and source regions103and105of the transistors T1, T2, T3, and T4. At this point, if the capping patterns111and the spacers106are composed of materials having high selectivity to the first interlevel dielectric layer112, the first contact holes are formed using a self-aligned etching by the capping patterns111and the spacers106. Next, a polysilicon layer114formed of a conductive material is formed on the first interlevel dielectric layer112including the first contact holes.

Referring toFIG. 2, chemical mechanical polishing (CMP) or etchback is performed on the polysilicon layer114until the top surface of the first interlevel dielectric layer112is substantially exposed to form a bit line contact plug114band lower electrode bit line contact plugs114aand114cconnected to the drain region103and the source region on the cell area C of the semiconductor substrate100, respectively. Next, a planarized second interlevel dielectric layer116is formed over the entire surface of the semiconductor substrate100including the peripheral circuit area P and bit line contact plug114band the lower electrode bit line contact plugs114aand114con the cell area C. Then, the second interlevel dielectric layer116overlying the bit line contact plug114bis etched to form a second contact hole. At the same time that the second contact hole is formed, the second interlevel dielectric layer116and the first interlevel dielectric layer112formed at the different positions are etched to form a third contact hole exposing an active area of the transistor T5disposed on the cell area C, such as the drain region103. Meanwhile, a process of forming a fourth contact hole exposing the metal or metal silicide pattern110of the gate electrode G6on the peripheral circuit area P includes a step of etching the second interlevel dielectric layer116to expose the capping pattern111of the sixth transistor T6, which is similar to an initial step in the process of forming the third contact hole, and a subsequent step of removing the capping pattern111to expose the metal layer or the metal silicide pattern110. After having formed the second through the fourth contact holes in this way, a polysilicon layer118, which is a conductive material, is formed on the second interlevel dielectric layer116to thereby fill the second through the fourth contact holes.

InFIG. 3, CMP or etchback is performed on the polysilicon layer118until the top surface of the second interlevel dielectric layer116is exposed to form a bit line contact pad118aand bit line contact plugs118band118c. The bit line contact plugs118band118cmay be also called bit line contact pads, but in this specification bit line contact plug is used. A bit line connector for connecting the active area103between the transistors T2and T3and a bit line120is comprised of the bit line contact plug114band the bit line contact pad118a. A bit line connector connecting the transistor T5and the bit line120is the bit line contact plug118b, while a bit line connector connecting the transistor T6to the bit line120is the bit line contact plug118c.

Next, a metal anti-diffusion layer and a metal layer are provided over the semiconductor substrate100including the bit line contact pad118aand the bit line contact plugs118band118cand patterned to form a bit line120. Titanium nitride (TiN) or titanium tungsten (TiW) is used as the metal anti-diffusion layer, while Ti, W or Al is used as the metal layer.

To protect the bit line from a subsequent integration process, an insulating layer is formed over the entire surface of the semiconductor substrate including the bit line120and is subjected to etchback to form a capping pattern122including a spacer. The insulating layer formed on the cell area C and the peripheral circuit area P is removed except for a portion in which the bit line120is formed, thereby shielding only the bit line120on the peripheral circuit area P.

Subsequently, a planarized third interlevel dielectric layer124is formed over the entire surface of the semiconductor substrate100on which the capping pattern122has been formed. Using a contact-type photoresist mask pattern (160ofFIG. 5), the third interlevel dielectric layer124and the underlying second interlevel dielectric layer116are etched to form a fifth contact hole125exposing the lower electrode contact plugs114aand114cof a capacitor.

Meanwhile, a plan view in which the contact-type photoresist mask pattern (160ofFIG. 5) used in forming the fifth contact hole125is disposed is shown inFIG. 4. Only a portion denoted by reference numeral150inFIG. 4is exposed by the contacttype photoresist mask pattern (160ofFIG. 5), which corresponds to the underlying third interlevel dielectric layer124.

More specifically, inFIG. 4, the first through fourth gate electrodes G1, G2, G3and G4extending in the Y-axis direction are disposed in parallel with respect to each other along the X-axis direction, and the bit lines120are disposed interposing the second interlevel dielectric layer116on the first through fourth gate electrodes G1, G2, G3, and G4so that both meet at right angles. The lower electrode contact plugs114aand114care positioned between the gate electrodes G1and G2, and between the gate electrodes G3and G4, respectively. The bit line contact plug114bis positioned between the second and third gate electrodes G2and G3in a direction in which the gate electrodes G2and G3extend. The bit line capping pattern122and the overlying third dielectric layer124are not shown inFIG. 4.

In a cross-sectional view (not shown) taken along line VI—VI ofFIG. 4, if an etching process for forming the fifth contact hole125is performed, the second and third interlevel dielectric layer116and124between the second and third gate electrodes G2and G3are not etched, while the second and third interlevel dielectric layer116and124between the first and second gate electrodes G1and G2, and between the third and fourth gate electrodes G3and G4are removed to form the fifth contact holes125as shown inFIG. 3.

On the other hand, referring toFIG. 5, which is a cross sectional view taken along line V—V ofFIG. 4, the lower electrode contact plug114aself-aligned between the first and second gate electrodes extends along the gate electrodes on the semiconductor substrate100. The second interlevel dielectric layer116is formed perpendicularly to the gate electrode on the lower electrode contact plug114a. The bit lines120covered with the capping pattern122are formed on top of the second interlevel dielectric layer116, each of which is separated in the Y direction in which the gate electrode extends. Next, the third interlevel dielectric layer124is disposed on the second interlevel dielectric layer116including the capping pattern122, on top of which the contact-type self-aligned photoresist mask pattern160is positioned for forming the fifth contact hole125by etching the second and third interlevel dielectric layers116and124between the capping patterns122.

Subsequently, as shown inFIG. 7, using the mask pattern160as an etch mask, the third and second interlevel dielectric layers124and116are etched to form the fifth contact hole125, and then the contact-type self-aligned photoresist mask pattern160is removed. Next, the polysilicon layer126is formed over the entire surface of the semiconductor substrate100and subjected to etchback or CMP until the top surface of the third dielectric layer124is exposed.

Specifically,FIG. 6shows a cross sectional view of a semiconductor memory device including the cell area C on which etchback or CMP has been performed on the polysilicon layer126, taken along line VI—VI of the X-axis direction ofFIG. 4, whileFIG. 7shows a cross-sectional view of the cell area C taken along line V—V of the Y-axis direction. That is, inFIGS. 6 and 7, the polysilicon layer126undergoes CMP to form capacitor lower electrode contact pads126aand126b.

Subsequently, as shown inFIG. 6, an etching stop layer128provided with an opening is formed on the third interlevel dielectric layer124on the cell area C on which the lower electrode contact pads126aand126bhave been formed, on top of which a lower electrode130, a dielectric layer132, and an upper electrode134constituting a capacitor are formed.

InFIG. 8, a planarized fourth interlevel dielectric layer136is formed over the entire surface of the semiconductor substrate100on the cell area C on which the capacitor has been formed, and on the peripheral circuit area P. A predetermined portion of the fourth interlevel dielectric layer136is etched to form a sixth contact hole exposing a portion of the upper electrode134on the cell area C. After having formed the sixth contact hole, predetermined portions of the third interlevel dielectric layer124, the capping patterns122and111, and the first and second interlevel dielectric layers112and116are etched to form seventh, eighth, and ninth contact holes. Here, the seventh, eighth, and ninth contact holes expose the bit line120on the peripheral circuit area P, the active area103of the semiconductor substrate100on the peripheral circuit area P, and the metal or metal silicide pattern110of the gate electrode G8, respectively. A metal layer (not shown) is formed on the fourth interlevel dielectric layer136in which the sixth through ninth contact holes have been formed in such a way as to fill the sixth through ninth contact hole, and then CMP or etchback is performed on the metal layer to form metal wiring contact plugs138a,138b,138c, and138d. In a subsequent process, a metal layer (not shown) is formed on the fourth interlevel dielectric layer136and patterned to form metal wiring contact pads140a,140b,140c, and140d.

While the bit line contact plugs and the lower electrode contact plugs are simultaneously formed using one mask, a three-time mask process is required in order to connect the bit line120and the lower electrode130to the active areas103and105of the semiconductor substrate100. That is, to form the bit line connector, a first mask for the bit line contact plug114bformed simultaneously with the lower electrode contact plugs114aand114c, and a second mask for forming the bit line contact pad118aare required. To form the lower electrode connector, a first mask and a third mask for forming the lower electrode contact pads126aand126bare required. Thus, a process for forming the bit line connector and the lower electrode connector is complicated.

Meanwhile, the bit line120is connected to the area103of the semiconductor substrate100through the bit line contact plug114band the bit line contact pad118a, while the lower electrode130is connected to the active area105of the semiconductor substrate100through the lower electrode contact plugs114aand114cand the lower electrode contact pads126aand126b. Thus, the bit line connector and the lower electrode connector have contact surfaces within them, which increases the overall resistance due to occurrences of contact resistance. The increased resistance, in turn, degrades the operating speed of transistors and capacitors.

Furthermore, since the fifth contact holes125for forming the lower electrode contact plug126aand126bare separated by 1 feature size (F) and 3 F in the Y-and X-axis directions, respectively, an alignment margin for the photoresist mask pattern160is not sufficient. That is, if the photoresist mask pattern160is misaligned in the Y-axis direction, the adjacent bit lines120are connected to each other to cause a bridge. Furthermore, if the third interlevel dielectric layer124for the fifth contact hole125is overetched, the capping pattern122is removed to expose the bit line120. As a result, an electrical short occurs between the bit line120and the lower electrode130.

Thus, to provide for a misalignment margin, the thickness of the capping pattern122, which is a hard mask formed on the bit line120, needs to increase. However, an increase in the thickness of capping pattern122makes it difficult to fill the space between the bit line structures120and122with a material of the third interlevel dielectric layer124where the fifth contact hole125will be formed without a void forming.

To fill the space between the bit line structures120and122without forming a void, liquid spin-on glass (SOG) and borophosphosilicate glass (BPSG) may be used. However, oxygen contained in the SOG or BPSG penetrates under the bit line120to oxidize the bit line120, thereby causing the problem of lifting the bit line120.

Furthermore, if the mask pattern160is misaligned in the X- and/or Y-axis directions, an overlay margin with the gate electrodes G1, G2, G3, and G4and the hard mask122formed on the bit line120becomes smaller, thereby offering low selectivity during a self-aligned contact (SAC) etching process.

Meanwhile, when forming the fifth contact hole125using the contact-type self-aligned mask pattern160, since the mask pattern160does not have high selectivity with respect to the third interlevel dielectric layer124, a portion of the underlying third interlevel dielectric layer124is removed, and a bridge defect occurs between the adjacent bit lines120.

To form the metal wiring contact plugs138b,138c, and138don the peripheral circuit area P, thick third and fourth interlevel dielectric layers124and136, and the first and second interlevel dielectric layers112and116must be etched. This imposes a burden on an etching process for forming the fifth contact hole125.

SUMMARY OF THE INVENTION

The present invention is therefore directed to a semiconductor memory device, and a method of forming a semiconductor memory device, which substantially overcome one or more of the problems due to the limitations and disadvantages of the related art.

To solve the above problems, it is an objective of the present invention to provide a semiconductor memory device for reducing the number of masks used in forming a lower electrode connector and a bit line connector while suppressing an increase of resistance thereof, and a manufacturing method thereof.

It is another objective of the present invention to provide a semiconductor memory device for providing a misalignment margin in forming the lower electrode connector and the bit line connector, and a manufacturing method thereof.

It is still another objective of the present invention to provide a semiconductor memory device capable of reducing a burden on an etching process for forming a metal wiring contact plug formed on a peripheral circuit area of the semiconductor memory device, and a manufacturing method thereof.

It is yet still another objective of the present invention to provide a semiconductor memory device for preventing a bit line from lifting off of a cell area, and a manufacturing method thereof.

The present invention provides a semiconductor memory device for reducing the number of masks used in forming a lower electrode connector and a bit line connector and suppressing an increase of resistance thereof, while providing a misalignment margin in forming the lower electrode connector. The semiconductor memory device according to the present invention includes transistors having gate electrode structures and source and drain regions and the interlevel dielectric layer. The gate electrode structure is formed on the substrate, and includes a gate electrode structure including a gate electrode, a gate electrode capping pattern formed on top of the gate electrode, and sidewall spacers formed on the sidewalls of the gate electrode and the gate electrode capping pattern. The interlevel dielectric layer is formed over the substrate on which the transistors have been formed, and includes a bit line contact hole and a lower electrode contact hole. The interlevel dielectric layer is formed of a material having high selectivity with respect to the gate electrode capping pattern and the sidewall spacers. A conductive bit line connector is formed within the bit line contact hole of the interlevel dielectric layer and is connected to the drain region. A bit line is formed on the interlevel dielectric layer in which the bit line connector has been formed and electrically connected to the bit line connector. The bit line is covered by a bit line capping pattern. A capacitor lower electrode connector is formed within the lower electrode contact hole of the interlevel dielectric layer and extends to be the same level as the top surface of the bit line capping pattern. Then, a capacitor including a lower electrode, a dielectric layer, and an upper electrode is formed on the capacitor lower electrode connector.

Here, the interlevel dielectric layer is a silicon oxide layer, a silicon nitride layer, a borosilicate glass (BSG) layer, a borophospho-silicate glass (BPSG) layer, a tetraethylorthosilicate (TEOS) layer, an ozone-TEOS layer, a plasma enhanced-TEOS (PE-TEOS) layer, an undoped silicate glass (USG) layer, or a combination thereof, and the gate electrode capping pattern, the bit line capping pattern and the sidewall spacers are formed of different materials from the interlevel dielectric layer, such as a silicon nitride layer, an aluminum oxide layer, a tantalum oxide layer, a silicon carbide layer or a combination thereof.

To prevent oxidation of the bit line, an anti-oxidation layer such as a silicon nitride layer or a silicon oxynitride layer is further interposed between the interlevel dielectric layer and the bit line.

The present invention also provides a semiconductor memory device for reducing a burden on an etching process for forming a metal wiring contact plug formed in a peripheral circuit area. The semiconductor memory device includes a first transistor including a first gate electrode, a first source region, and a first drain region, which is formed on the substrate, and a first interlevel dielectric layer formed over the substrate including the first transistor and having a bit line contact hole and a lower electrode contact hole formed in the cell area and a metal wiring contact hole formed in the peripheral circuit area. Furthermore, the semiconductor memory device further includes a bit line connector, a bit line capping pattern covering the bit line, a capacitor lower electrode connector, a capacitor, and a lower metal wiring contact plug. The bit line connector is formed within the bit line contact hole of the first interlevel dielectric layer and electrically connected to the drain region, and the bit line is formed on the interlevel dielectric layer in which the bit line connector has been formed and electrically connected to the bit line connector. The capacitor lower electrode connector is formed within the lower electrode contact hole of the interlevel dielectric layer and extends to be the same level as the bit line capping pattern. The capacitor including a lower electrode, a dielectric layer, and an upper electrode is formed on the capacitor lower electrode connector, and the lower metal wiring contact plug is formed within the metal wiring contact hole and connected to the drain region or the gate electrode positioned on the peripheral circuit area.

To form the bit line contact hole and the lower electrode contact hole using a self-aligned etching, the transistor further includes a gate electrode capping pattern formed on top of the gate electrode and sidewall spacers formed at the sidewalls of the gate electrode. In this case, the gate electrode capping pattern, the sidewall spacers, and the bit line capping pattern are formed of materials having high selectivity to the first interlevel dielectric layer.

The semiconductor memory device further includes a planarized second interlevel dielectric layer, which overlies the capacitor and is formed over the entire surface of the substrate including the cell area and the peripheral circuit area, and which includes a metal wiring contact hole provided in the peripheral circuit area. The metal wiring contact hole is filled with a conductive material to form an upper metal contact plug electrically connected to the lower metal contact plug.

Meanwhile, the bit line capping pattern is disposed on the bit line and the first interlevel dielectric layer, thereby alleviating a burden on etching when forming the metal wiring contact hole formed in the second interlevel dielectric layer.

The present invention also provides a method of manufacturing a semiconductor memory device which reduces the number of masks used in forming a lower electrode connector and a bit line connector and suppresses an increase of resistance thereof while providing a misalignment margin in forming the lower electrode connector. According to the manufacturing method, transistors are formed on the substrate, wherein each transistor includes a gate electrode structure having a gate electrode, a gate electrode capping pattern formed on top of the gate electrode, and gate electrode sidewall spacers formed on the sidewalls of the gate electrode and the gate electrode capping pattern, a source region, and a drain region. A first interlevel dielectric layer including a bit line contact hole is formed of a material having high selectivity with respect to the gate electrode capping pattern and the sidewall spacers over the entire surface of the substrate including the transistors. A bit line connector electrically connected to the drain region is formed by filling the bit line contact hole with a conductive material. Then, a bit line is formed on the first interlevel dielectric layer including the bit line connector, and then a bit line capping pattern covering the bit line is formed. A second interlevel dielectric layer is formed of a material having high selectivity with respect to the gate electrode capping pattern and the gate electrode sidewall spacers over the entire surface of the first interlevel dielectric layer on which the bit line capping pattern has been formed. A mask pattern exposing a portion of the second interlevel dielectric layer which corresponds to the source region in the second interlevel dielectric layer and extends along the direction of bit line arrangement is formed on the second interlevel dielectric layer. The first and second interlevel dielectric layers are etched using the mask pattern to form a capacitor lower electrode contact hole exposing the source region. The lower electrode contact hole is filled with the conductive material from the bottom thereof up to the top surface of the bit line capping pattern to form a capacitor lower electrode connector positioned at the same level as the bit line capping pattern. Then, a capacitor including a lower electrode, a dielectric layer, and an upper electrode is formed on top of the capacitor lower electrode connector.

More specifically, to form the lower electrode contact hole, the entire exposed portion of the second interlevel dielectric layer is removed and the first interlevel dielectric layer is etched using the bit line capping pattern. Then, to form the capacitor lower electrode connector, after forming a conductive material layer over the entire surface of the substrate including the lower electrode contact hole, chemical mechanical polishing (CMP) or etchback is performed on the entire surface of the substrate on which the conductive material layer has been formed until the top surface of the bit line capping layer is substantially exposed.

To prevent lifting due to oxidation of the bit line, a material layer for preventing oxidation of the bit line is formed between the steps of forming the first interlevel dielectric layer and forming the bit line contact hole, the bit line anti-oxidation material layer is etched to form an opening for opening the bit line contact hole, and the opening is filled with a conductive material up to the top thereof.

To reduce a burden on an etching process for forming a metal wiring contact plug formed in a peripheral circuit area of the semiconductor memory device, after preparing a substrate of the semiconductor memory device including a cell area and a peripheral circuit area, transistors are formed on the substrate including the cell area and the peripheral circuit area, wherein each transistor includes a gate electrode structure having a gate electrode, a gate electrode capping pattern formed on top of the gate electrode, and sidewall spacers formed at the sidewalls of the gate electrode and the gate electrode capping pattern, a source region, and a drain region. Then, a first interlevel dielectric layer is formed over the entire surface of the substrate including the transistors, and the first interlevel dielectric layer is etched to form a bit line contact hole on the cell area and a metal wiring contact hole on the peripheral circuit area at the same time. The bit line contact hole and the metal wiring contact hole are filled with a conductive material to form a bit line connector connected to the drain region formed in the cell area and a metal contact connector connected to the drain region or the gate electrode formed in the peripheral circuit area at the same time.

Here, to form the bit line connector and the metal contact connector, a conductive layer of a conductive material such a polysilicon or metal, or a combination thereof, is formed on the first interlevel dielectric layer in which the bit line contact hole and the metal wiring contact hole have been formed. CMP or etchback is performed on the conductive layer until the top surface of the first interlevel dielectric layer is substantially exposed.

Furthermore, after the step of forming the bit line connector and the metal contact connector, a bit line is formed on a predetermined portion of the first interlevel dielectric layer in which the bit line connector and the metal contact connector have been formed and connected to the bit line connector. Continuously, a bit line capping pattern covering the bit line is formed, wherein the bit line capping pattern positioned on the cell area covers only the bit line on the cell area and the bit line capping pattern positioned on the peripheral circuit area covers the bit line and the top surfaces of the first interlevel dielectric layer and the metal contact connector on the peripheral circuit area. Here, the bit line capping pattern positioned on the peripheral circuit area is used as an etch stop layer during dry etching for etching the interlevel dielectric layer overlying the capacitor to form the metal wiring contact hole.

After forming the bit line capping pattern, the manufacturing method further includes the steps of: forming a second interlevel dielectric layer over the entire surface of the substrate on which the bit line capping pattern has been formed; forming a mask pattern on the second interlevel dielectric layer, the mask pattern exposing a portion of the second interlevel dielectric layer which corresponds to the source region on the second interlevel dielectric layer and extends along the direction of bit line arrangement; etching the first and second interlevel dielectric layers using the mask pattern and forming a capacitor lower electrode contact hole exposing the source region; filling the lower electrode contact hole with the conductive material from the bottom thereof up to the top surface of the bit line capping pattern to form a capacitor lower electrode connector positioned at the same level as the bit line capping pattern; and forming a capacitor including a lower electrode, a dielectric layer, and an upper electrode on top of the capacitor lower electrode connector.

Furthermore, prior to the step of forming the bit line, a bit line anti-oxidation material layer having an opening for opening the bit line connector is formed of a silicon nitride layer or a silicon oxynitride layer on the first interlevel dielectric layer and the opening of the bit line anti-oxidation material layer is filled with a conductive material up to the top thereof, thereby preventing the oxidation of the bit line.

More specifically, to form the lower electrode contact hole, the exposed portion of the second interlevel dielectric layer is removed and the first interlevel dielectric layer is removed using the bit line capping pattern.

Specifically, to form the lower electrode connector, a conductive material layer is formed over the entire surface of the substrate including the lower electrode contact hole and CMP or etchback is performed over the entire surface of the substrate on which the conductive material layer has been formed until the top surface of the bit line capping pattern is substantially exposed.

Furthermore, to form the bit line capping pattern, a bit line capping layer is formed over the entire surface of the semiconductor substrate including the cell area and the peripheral circuit area, and then a mask pattern exposing the cell area is formed on the bit line capping layer. Then, the bit line capping layer positioned on the cell area is etched back using the mask pattern to form the bit line capping pattern, and the mask pattern is removed. Thus, since only the bit line capping layer positioned on the cell area is etched, a burden on the etching process can be alleviated. Furthermore, the bit line capping pattern on the peripheral circuit area can be used as an etch stop layer in forming the metal wiring contact hole.

DETAILED DESCRIPTION OF THE INVENTION

Semiconductor memory devices shown inFIGS. 9,10,18and19are divided into a cell area C and a peripheral circuit area C, while only cell areas C of semiconductor memory devices are shown inFIGS. 11–17. InFIG. 9, an active area of a semiconductor substrate200is defined by isolation regions202. The isolation regions202may be formed using shallow trench isolation (STI) or local oxidation of silicon (LOCOS) technique, and in the case of a highly integrated semiconductor memory device, a STI technique is preferably used.

Next, an insulating layer, a polysilicon layer, a metal layer or a metal silicide layer, and a capping layer are formed over the entire surface of the semiconductor substrate200on a cell area C and a peripheral circuit area P, and are patterned to sequentially form the gate electrodes G11, G12, G13, G14, G15, G16, G17, and G18and capping patterns211. Each of the gate electrodes G11, G12, G13, G14, G15, G16, G17and G18includes a gate insulating pattern204, a polysilicon pattern208, and metal or metal silicide pattern210. Then, ions having opposite conductive type to the semiconductor substrate200are implanted into the semiconductor substrate200to form drain and source regions203and205. The source region205of a transistor including the gate electrode G12is in common with that of a transistor including the gate electrode G11, while the drain region203of a transistor including the gate electrode G12is in common with that of a transistor including the gate electrode G13.

The gate electrode capping pattern211may be formed of a material having high selectivity with respect to an interlevel dielectric layer212which will later be formed, such as for example a silicon nitride layer, an aluminum oxide layer, a silicon carbide layer or a tantalum oxide layer. Subsequently, an insulating layer is formed over the entire surface of the semiconductor substrate200on which the gate electrodes G11, G12, G13, G14, G15, G16, G17, and G18have been formed, and is etched back to form spacers206along the sidewalls of the gate electrodes G11, G12, G13, G14, G15, G16, G17, and G18and to form capping patterns211. The spacers206may be composed of a material having high selectivity with respect to the interlevel dielectric layer212that will later be formed. Here, structures comprised of the gate electrodes G11, G12, G13, G14, G15, G16, G17, and G18, the capping pattern211and the spacer206are referred to as gate electrode structures.

Meanwhile, after having formed the gate electrode structures including the spacers206, impurity ions of high concentration are implanted into the semiconductor substrate200to form the drain and source regions203and205having a lightly doped drain and source (LDD) structure, thereby completing transistors T11, T12, T13, T14, T15, T16, T17, and T18. The drain and source regions203and205shown inFIGS. 9,10, and12–19have a LDD structure. Hereinafter, source and drain regions having the LDD structure are referred to as source and drain regions.

A planarized first interlevel dielectric layer212and a bit line anti-oxidation layer214are formed over the entire surface of the semiconductor substrate100in the cell area C and the peripheral circuit area P on which the spacers206have been formed. Subsequently, predetermined portions of the first interlevel dielectric layer212and the bit line anti-oxidation layer214are etched using a mask (not shown) to form first contact holes exposing the drain regions203of the transistors T12, T13, and T15in the cell area C, and second and third contact holes exposing the metal or metal silicide patterns210of the transistors T16and T18and the drain region203of the transistor T17, respectively, in the peripheral circuit area P. In particular, the second and third contact holes formed in the peripheral circuit area P serves to alleviate a burden on etching during a process of forming a metal wiring contact hole.

Meanwhile, if the gate electrode capping patterns211and the spacers206are composed of a material having high selectivity with respect to the first interlevel dielectric layer212, the first through third contact holes are etched by the gate electrode capping pattern211and the spacer206in a self-aligned manner. Here, the first interlevel dielectric layer212may be formed of a silicon nitride layer, a silicon oxide layer, a phosphosilicate glass (PSG) layer, a borosilicate glass (BSG) layer, a borophospho-silicate glass (BPSG) layer, a tetraethylorthosilicate (TEOS) layer, an ozone-TEOS layer, a plasma enhanced-TEOS (PE-TEOS) layer or an undoped silicate glass (USG) layer, or a combination thereof. The gate electrode capping patterns211and the spacers206may be composed of a different material from the first interlevel dielectric layer212, such as a silicon nitride layer, an aluminum oxide layer, a tantalum oxide layer or a silicon carbide layer, or a combination thereof.

Next, a conductive polysilicon layer216is formed over the entire surface of the semiconductor substrate200to fill the first through third contact holes. InFIG. 10, the polysilicon layer216is subjected to etchback or chemical mechanical polishing (CMP) until the top surface of the bit line anti-oxidation layer214is substantially exposed to form first bit line contact connectors216aand216bconnected to the drain regions203of the transistors T12and T15through the first contact holes in the cell area C. Second bit line contact connectors216cand216econnected to the top surfaces of the gate electrodes G16and G18of the transistors T16and T18through the second contact holes, and a third bit line contact connector216dconnected to the drain region203of the transistor T17through the third contact hole are formed in the peripheral circuit region P. Here, the top surface of the bit line anti-oxidation layer214being “substantially” exposed means both the case in which the top surface of the bit line anti-oxidation layer214is ideally exposed without etching and the case in which a portion thereof is actually etched.

Next, a metal anti-diffusion layer and a metal layer are formed over the semiconductor substrate200including the first through third bit line connectors216a,216b,216c,216d, and216eand patterned to form a bit line218in the cell area C and the peripheral circuit area P. The metal anti-diffusion layer may be formed of titanium nitride (TiN) or titanium tungsten (TiW), while the metal layer may be formed of Ti, W or Al. Meanwhile, the metal anti-diffusion layer and the metal layer may be used instead of the polysilcon layer216to fill the first through third contact holes.

After forming a capping layer (not shown) for protecting bit line218over the entire surface of the semiconductor substrate200on which the bit line218has been formed, using a mask (not shown) for masking the peripheral circuit area P, etchback is performed to form a bit line capping pattern220a. The bit line capping layer220formed in the peripheral circuit area P is not removed, but is formed on the bit line218, the second and third bit line contact connectors216dand216e, and the bit line anti-oxidation layer214. After having performed the etchback process, the bit line capping pattern220ais formed on the cell area C, while the bit line capping pattern220is formed on the peripheral circuit area P.

Next, a second interlevel dielectric layer222formed of the same or equivalent material as the first interlevel dielectric layer212is formed over the entire surface of the semiconductor substrate200, and then a line-type self-aligned mask (270ofFIG. 12) exposing only a portion denoted by reference numeral250as shown inFIG. 11is positioned on the second interlevel dielectric layer222.

FIG. 12is a cross-sectional view of the cell area C of a semiconductor memory device taken along line XII—XII ofFIG. 11, on which the line-type self-aligned mask270has been formed on the second interlevel dielectric layer222. InFIG. 11, the bit lines218extend in the X-axis direction and are arranged parallel to each other with respect to the Y-axis direction, while the gate electrodes G11, G12, G13, and G14extend in the Y-axis direction and are arranged parallel to each other with respect to the X-axis direction. The first interlevel dielectric layer212and the bit line anti-oxidation layer214disposed between the gate electrodes G11, G12, G13, G14, and G15and the bit line218, and the bit line capping pattern220afor covering the bit line218, are not shown inFIG. 11. Furthermore, a portion denoted by reference numeral260inFIG. 11represents a portion where a lower electrode contact hole will later be formed.

Meanwhile, as shown inFIG. 12, bit line connector216aas formed within the first contact hole in a self-aligned manner by the spacer206of the gate electrode G12and the spacer206of the gate electrode G13as previously described with respect toFIG. 9, connects the drain region203of the transistors T12and T13and the bit line218. The bit line capping pattern220aand the second interlevel dielectric layer222are sequentially formed on the bit line218. The line-type self-aligned photoresist mask pattern270is formed on the second interlevel dielectric layer222. The line-type self-aligned mask270exposes the second interlevel dielectric layer222at the source region205of the transistors T11and T12and the source region205of the transistors T13and T14.

FIG. 13is a cross-sectional view of the cell area C of a semiconductor memory device taken along line XIII—XIII ofFIG. 11, on which the first interlevel dielectric layer212has been formed on the semiconductor substrate200. The bit line anti-oxidation layer214, the bit line218, and the bit line capping pattern220aare sequentially formed on the first interlevel dielectric layer212. Next, the second interlevel dielectric layer222is formed over the entire surface of the semiconductor substrate200including the bit line capping pattern220a. The line-type self-aligned photoresist mask pattern270is not formed on the second interlevel dielectric layer222in this view, which means that the photoresist mask pattern270is not formed on the bit line218.

Next, using the line-type self-aligned mask270an etching process for forming a lower electrode contact hole is performed.FIGS. 14 and 15show subsequent manufacture states ofFIG. 12which is a cross-sectional view taken along line XII—XII ofFIG. 11, andFIG. 13which is a cross-sectional view taken along line XIII—XIII ofFIG. 11, respectively.

Referring toFIG. 14, the second interlevel dielectric layer222corresponding to portions260between bit lines218exposed by the line-type self-aligned photoresist mask pattern270and the underlying first interlevel dielectric layer are etched to form a recess223and a projection225. A plurality of grooves224etched in a self-aligned manner by the bit line capping pattern220aare separately disposed within the recess223between the bit lines218, as shown inFIG. 15. Then, following removal of the line-type self-aligned photoresist mask270, a polysilicon layer226is formed of polysilicon, which is a conductive material, over the entire surface of the semiconductor substrate200on which the recess223, the projection225, and the grooves224have been formed. InFIG. 14, the grooves having polysilicon therein and being between bit lines218as corresponding to portions260, are shown by dashed lines.

Next, when etchback or CMP is performed over the entire surface of the semiconductor substrate until the top surface of the bit line capping pattern220ais substantially exposed, as shown inFIGS. 16 and 17, a plurality of lower electrode connectors228aand228b(shown by dashed lines inFIG. 16), which are separated in the X- and Y-axis directions, respectively, are formed. That is, the top surface of the lower electrode connector228ais on a level with the top surface of the bit line capping pattern220a. Here, the top surface of the bit line capping pattern220abeing “substantially” exposed means both the case in which the top surface of the bit line capping pattern220ais exposed without etching and the case in which a portion thereof is etched.

For a subsequent process for forming a capacitor, as shown inFIG. 18, a planarized third interlevel dielectric layer230having a fifth contact hole for forming a capacitor lower electrode and an etching stop layer234are formed over the semiconductor substrate200including the lower electrode connectors228aand228b. After plugs232aand232bare formed by filling the fifth contact hole with a conductive material, a lower electrode236of a capacitor is formed. Then, a dielectric layer238and an upper electrode240are sequentially formed on the lower electrode236.

InFIG. 19, a planarized fourth interlevel dielectric layer242is formed over the entire surface of the semiconductor substrate200on which the capacitor has been formed. Subsequently, the fourth interlevel dielectric layer242is etched to form a sixth contact hole exposing a portion of the upper electrode240on the cell area. After forming the sixth contact hole, the fourth interlevel dielectric layer242, the third interlevel dielectric layer230and the bit line capping pattern220on the peripheral circuit area P are removed to form seventh through ninth contact holes exposing the top surface of the bit line218overlying the second bit line connector216c, third bit line connector216dand second bit line connector216e, respectively.

After a polysilicon layer (not shown) or a metal layer (not shown) are formed on the fourth interlevel dielectric layer242on which the sixth through ninth contact holes have been formed, etchback or CMP is performed to form metal wiring contact plugs244a,244b,244c, and244dfor filling the sixth through ninth contact holes. Subsequently, after forming a metal layer (not shown), the metal layer is patterned to form metal wiring contact pads246a,246b,246cand246d.

The chief advantages of the present invention are as follows. First, considering that one mask is used to form the bit line connector216ain the cell area C, and one mask is used to form the lower electrode connectors228aand228b, respectively, the number of masks is reduced compared to conventional processes. Thus, a fabrication process attendant on the manufacture and removal of masks is simplified.

Second, since the bit line connector216aand the lower electrode connectors228aand228bare formed by one-time etching process and one-time conductive material filling process (SeeFIG. 9), they have no contact surfaces within them, thereby suppressing an increase in resistance. In particular, since the lower electrode connectors228aand228bare simply slightly longer (higher) than the bit line connector216a, resistance can decrease by reducing the length of the lower electrode connectors228aand228b.

Third, when forming a bit line contact hole on the cell area C, (lower) metal wiring contact holes are formed on the peripheral circuit area P. Thus, a burden on an etching process is reduced compared to the case in which all interlevel dielectric layers including the fourth interlevel dielectric layer242overlying the capacitor are etched to form metal wiring plugs.

Fourth, by the line-type self-aligned mask270, a photoresist is not formed on the bit line218, positioned on the source region205, which is peripheral to the direction in which the gate electrodes extend. Thus, a bridge defect between the lower electrode connectors due to low selectivity between the photoresist and the underlying interlevel dielectric layer222does not occur.

Fifth, since a lower electrode contact hole is formed in a self-aligned manner using the line-type photoresist mask pattern270, a bridge defect between the lower electrode contact plugs does not occur although misalignment occurs in the direction of bit line arrangement.

Sixth, the bit line anti-oxidation layer214formed simultaneously on the cell area C and the peripheral circuit area P is used to prevent oxidation of the bit line218on the cell area, while it is used as an etching stop layer on the peripheral circuit area P during a subsequent process of forming (upper) metal wiring contact holes.

Furthermore, during a process of forming a bit line capping pattern220a, etchback is performed only over the cell area C, thereby reducing a burden on the etchback process. In addition, the bit line capping pattern220acan serve as an etching stop layer on the peripheral circuit area P during a process of forming the upper metal wiring contact holes.