Display panel and bi-directional shift register circuit

A display panel includes shift registers coupled in serial. At least one of the shift registers includes an input circuit, an output circuit and a control circuit. The input circuit is coupled to a first input terminal and a second input terminal for respectively receiving a first input signal and a second input signal. The output circuit is coupled to a first clock input terminal for receiving a first clock signal and outputting a pulse signal at an output terminal according to the first clock signal. The control circuit is coupled to the output circuit via a first control node, a second control node and a third control node and controls voltages at the first control node, the second control node and the third control node according to the first input signal or the second input signal, and further controls operations of the output circuit.

CROSS REFERENCE TO RELATED APPLICATIONS

This Application claims priority of Taiwan Patent Application No. 103135166, filed on Oct. 9, 2014, the entirety of which is incorporated by reference herein.

BACKGROUND OF THE INVENTION

Field of the Invention

The invention relates to bi-directional shift registers, and more particularly to bi-directional shift registers capable of reducing the falling time of an output pulse and reducing the power consumption.

Description of the Related Art

Shift registers have been widely used in data driving circuits and gate driving circuits used in display devices to control timing when receiving a data signal in each data line, as well as to generate a scanning signal for each gate line. In a data driving circuit, the shift register outputs a selection signal to each data line, so as to write the image data into each data line. In a gate driving circuit, the shift register outputs a scanning signal to each gate line, so as to write the image signal provided to each data line in the pixels of a pixel array.

A conventional shift register generates the selection signal or scanning signal in only a single direction. However, a single scanning direction does not satisfy the entire requirements of LCD products. For example, some displays of digital cameras are rotated according to the placement angle of the camera. In addition, some LCD monitors comprise the function of rotating the monitor. Therefore, novel bi-directional shift registers capable of outputting signals in a forward direction and a reverse direction, and further reducing the falling time of an output pulse and reducing the power consumption, are highly desired.

BRIEF SUMMARY OF THE INVENTION

A display panel and a bi-directional shift register circuit are provided. An exemplary embodiment of the display panel comprises a gate driving circuit. The gate driving circuit comprises a plurality of shift registers coupled in serial. At least one of the shift registers comprises an input circuit, an output circuit, and a control circuit. The input circuit is coupled to a first input terminal and a second input terminal for respectively receiving a first input signal and a second input signal. The output circuit is coupled to a first clock input terminal for receiving a first clock signal and outputting a pulse signal at an output terminal according to the first clock signal. The control circuit is coupled to the output circuit via a first control node, a second control node and a third control node and controls voltages at the first control node, the second control node and the third control node according to the first input signal or the second input signal, and further controls operations of the output circuit.

An exemplary embodiment of a bi-directional shift register circuit generates a plurality of gate driving signals and comprises a plurality of shift registers. At least one shift register comprises an input circuit, an output circuit, a control circuit, a second clock input terminal and a third clock input signal. The input circuit is coupled to a first input terminal and a second input terminal for respectively receiving a first input signal and a second input signal. The output circuit is coupled to a first clock input terminal for receiving a first clock signal and outputs a pulse signal at an output terminal according to the first clock signal. The control circuit is coupled to the output circuit via a first control node, a second control node and a third control node and controls voltages at the first control node, the second control node and the third control node according to the first input signal or the second input signal, and further controls operations of the output circuit. The second clock input terminal receives a second clock signal. The third clock input signal receives a third clock signal. When the shift register operates in a forward scan, the falling edge of the first clock signal is close to the rising edge of the second clock signal, and when the shift register operates in a reverse scan, the falling of the first clock signal is close to the rising edge of the third clock signal.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1is a block diagram of a display device according to an embodiment of the invention. As shown inFIG. 1, the display device100may comprise a display panel101, a data driving circuit120and a controller chip140. The display panel101may comprise a gate driving circuit110and a pixel array130. The gate driving circuit110generates a plurality of gate driving signals to drive a plurality of pixels in the pixel array130. The data driving circuit120generates a plurality of data driving signals to provide image data to the pixels of the pixel array130. The controller chip140generates a plurality of timing signals, comprising clock signals, reset signals and start pulses.

In addition, the display device100may further comprise an input unit102. The input unit102receives image signals and controls the display panel101to display images. According to an embodiment of the invention, the display device100may further be comprised in an electronic device. The electronic device may be implemented as various devices, comprising: a mobile phone, a digital camera, a personal digital assistant (PDA), a lap-top computer, a personal computer, a television, an in-vehicle display, a portable DVD player, or any apparatus with image display functionality.

According to an embodiment of the invention, the gate driving circuit110may be designed as a unilateral gate driving circuit and disposed at one side of the pixel array130, or may be designed as a bilateral gate driving circuit and disposed at two sides of the pixel array, and the invention should not be limited to either implementation method.

In addition, according to an embodiment of the invention, according to the unilateral or bilateral design, the gate driving circuit may comprise one or more shift register circuits. The shift register circuit may be a bi-directional shift register circuit for supporting the operations of two different scan directions (the forward scan and reverse scan). In the embodiments of the invention, the bi-directional shift register circuit may comprise a plurality of shift registers SR coupled in serial. Each shift register may sequentially generate a gate driving signal to one gate line for driving the pixels on each gate line. For example, when the bi-directional shift register circuit operates in the forward scan, the shift registers sequentially output the corresponding gate driving signals in a first order, such as SR(1)˜SR(M), where M is the number of shift registers, and when the bi-directional shift register circuit operate in the reverse scan, the shift registers sequentially output the corresponding gate driving signals in a second order, such as SR(M)˜SR(1).

Generally, when the resolution of the display panel increases, the number of shift register increases, accordingly. However, once the number of shift register increases, the loading of the clock signals provided to the shift register circuit increases, causing a distortion problem in the clock signals received by the shift register in the far end.

FIG. 2shows an exemplary waveform of a clock signal. The waveform201represents the clock signal received by a near end shift register and the waveform202represents the clock signal received by a far end shift register. Here, the near end and far end represents the relative distance between the shift register and the controller chip providing the clock signals. As shown inFIG. 2, the falling time Tf2of the clock pulse received by the far end shift register is longer than the falling time Tf1of the clock pulse received by the near end shift register. However, the falling edge of the clock pulse is an important timing for reading the image data, especially when the clock signal is designed to have a pulse width of multiple horizontal times. Therefore, the falling time of the clock pulse is as short as possible.

In this manner, the size of the transistor (for example, the transistor M1in the embodiment as shown inFIGS. 4 and 7) outputting one pulse of the clock signal as the gate pulse in conventional design cannot be reduced, so as to prevent extending the falling time of the gate pulse. However, the big size transistor M1increases the circuit area and consumes more power. To solve this problem, a bi-directional shift registers capable of reducing power consumption and the falling time of the gate pulse and are proposed. The proposed bi-directional shift registers are further discussed in the following paragraphs.

FIG. 3shows a block diagram of a bi-directional shift register circuit according to an embodiment of the invention. As shown inFIG. 3, the bi-directional shift register circuit300may comprise a plurality of shift registers SR(1)˜SR(M) coupled in serial. Each shift register may at least comprise a first input terminal IN1, a second input terminal IN2, an output terminal OUT, a first clock input terminal C1, a second clock input terminal C2, a third clock input terminal C3and a fourth clock input terminal. The first stage shift register SR(1) receives the start pulse STV at the first input terminal IN1as the first input signal, and the remaining stage shift registers SR(2)˜SR(M) respectively receive the gate pulse output by a previous stage shift register SR(1)˜SR(M−1) at the first input terminal IN1as the first input signal. The last stage shift register SR(M) receives the start pulse STV at the second input terminal IN2as the second input signal, and the remaining stage shift registers SR(M−1)˜SR(1) respectively receive the gate pulse output by a following stage shift register SR(M)—SR(2) at the second input terminal IN2as the second input signal.

In addition, according to an embodiment of the invention, each shift register may receive at least four clock signals. For example, the clock signals CKV1, CKV2, CKV3and CKV4as shown. As shown inFIG. 3, each shift register may receive the clock signal at each clock input terminals according to a predetermined rule. In the embodiments of the invention, the rising edge of a clock signal is close to the falling edge of the next clock signal. In addition, in a forward scan, the pulse of the clock signals CKV1˜CKV4are sequentially generated in a cyclic manner and in a reverse scan, the pulse of the clock signals CKV4˜CKV1are sequentially generated in a cyclic manner. As shown inFIG. 5andFIG. 8, in a forward scan, the rising edge of the clock signal CKV1is close to the falling edge of the clock signal CKV4, the rising edge of the clock signal CKV2is close to the falling edge of the clock signal CKV1, and so on, and the pulse of the clock signals CKV1˜CKV4are sequentially generated in a cyclic manner. In addition, as shown inFIG. 6andFIG. 9, in reverse scan, the rising edge of the clock signal CKV4is close to the falling edge of the clock signal CKV1, the rising edge of the clock signal CKV3is close to the falling edge of the clock signal CKV4, and so on, and the pulse of the clock signals CKV4˜CKV1are sequentially generated in a cyclic manner.

In addition, according to an embodiment of the invention, in the forward scan, each shift register is activated in response to the first input signal received at the first input terminal IN1, and is deactivated in response to the clock signal received at the fourth clock input terminal C4. In the reverse scan, operation of each shift register is activated in response to the second input signal received at the second input terminal IN2, and is deactivated in response to the clock signal received at the fourth clock input terminal C4. Multiple shift register circuits are discussed in detail in the following paragraphs.

FIG. 4shows a circuit diagram of a shift register circuit according to a first embodiment of the invention. The shift register400may be either one of the shift registers SR(1)˜SR(M) shown inFIG. 3, and may comprise an input circuit410, a control circuit420, an output circuit430and a switch circuit440. For the convenience of illustration, the shift register400is regarded as the first stage shift register SR(1).

The input circuit410is coupled to a first input terminal IN1and a second input terminal IN2for respectively receiving the input signal STV and G(2) (that is, the gate driving signal output by a following stage shift register SR(2)). The output circuit430is coupled to the first clock input terminal C1for receiving the clock signal CKV1and outputs a pulse signal (that is, the gate pulse of the gate driving signal G(1)) at the output terminal OUT according the clock signal CKV1. The control circuit420is coupled to the output circuit430through the first control node N1, the second control node N2and the third control node N3, controls the voltages at the first control node N1, the second control node N2and the third control node N3according to the input signal STV or G(2), and further controls the operation of the output circuit430. The switch circuit440is coupled to the second clock input terminal C2and the third clock input terminal C3for receiving the clock signals CKV2and CKV4.

In this embodiment, the input circuit410and the switch circuit440further receive two control signals CSV and BCSV. The control signals CSV and BCSV are utilized to define the scan direction. For example, when operating in the forward scan, the control signal CSV has a first voltage level and the control signal BCSV has a second voltage level. Meanwhile, the input circuit410only transmits the input signal STV to the control circuit420and the switch circuit440only transmits the clock signal CKV2to the control circuit420. When operating in the reverse scan, the control signal has the second voltage level and the control signal BCSV has the first voltage level. Therefore, the input circuit410only transmits the input signal G(2) to the control circuit420and the switch circuit440only transmits the clock signal CKV4to the control circuit420.

According to an embodiment of the invention, the output circuit430may comprise transistors M1, M2and a capacitor C. The transistor M1is coupled between the first clock input terminal C1and the output terminal OUT and comprises a control electrode coupled to the first control node N1. The transistor M2is coupled between the output terminal OUT and the low operation voltage VL and comprises a control electrode coupled to the second control node N2. The transistor M1is turned on or off according to a voltage at the first control node N1and the transistor M2is turned on or off according to a voltage at the second control node N2.

The control circuit420may comprise transistors M3˜M8. The transistor M3is coupled between the high operation voltage VH and the first control node N1and comprises a control electrode coupled to the fourth control node N4. The transistor M3is turned on or off according to a voltage at the fourth control node N4for controlling the voltage at the first control node N1. The transistor M4is coupled between the high operation voltage VH and the second control node N2and comprises a control electrode coupled to the fifth control node N5. The transistor M4is turned on or off according to a voltage at the fifth control node N5for controlling the voltage at the second control node N2. The transistor M5is coupled between the high operation voltage VH and the third control node N3and comprises a control electrode coupled to the fourth clock input terminal C4. The transistor M5is turned on or off according to a voltage of the clock signal CKV3for controlling the voltage at the third control node N3.

The transistor M6is coupled between the first control node N1and the low operation voltage VL and comprises a control electrode coupled to the third control node N3. The transistor M6is turned on or off according to the voltage at the third control node N3for controlling the voltage at the first control node N1. The transistor M7is coupled between the second control node N2and the low operation voltage VL and comprises a control electrode coupled to the fourth control node N4. The transistor M7is turned on or off according to a voltage at the fourth control node N4for controlling the voltage at the second control node N2. The transistor M8is coupled between the third control node N3and the low operation voltage VL and comprises a control electrode coupled to the fourth control node N4. The transistor M8is turned on or off according to a voltage at the fourth control node N4for controlling the voltage at the third control node N3.

The input circuit410may comprise transistors M9and M10. The transistor M9is coupled between the first input terminal IN1and the fourth control node N4and comprises a control electrode receiving the control signal CSV. The transistor M10is coupled between the second input terminal IN2and the fourth control node N4and comprises a control electrode receiving the control signal BCSV. The transistors M9and M10are respectively turned on or off according to the control signals CSV and BCSV for selectively transmitting the input signal STV or G(2) to the control circuit420.

The switch circuit440may comprise transistors M11and M12. The transistor M11is coupled between the second clock input terminal C2and the fifth control node N5and comprises a control electrode receiving the control signal CSV. The transistor M12is coupled between the third clock input terminal C3and the fifth control node N5and comprises a control electrode receiving the control signal BCSV. The transistors M11and M12are respectively turned on or off according to the control signals CSV and BCSV for selectively transmitting the clock signals CKV2or CKV4to the control circuit420.

FIG. 5shows the waveforms of the corresponding signals and nodes of a shift register in the forward scan according to the first embodiment of the invention. Similarly, for convenience of illustration, the waveforms as shown are the waveforms of the first stage shift register SR(1). Based on the waveforms shown inFIG. 5, operations in the forward scan of the shift register in the first embodiment of the invention are illustrated in the following paragraphs.

In the forward scan, the transistors M9and M11are turned on in response to the voltage level of the control signal CSV. When the start pulse STV arrives, the fourth control node N4is charged to a high voltage approaching the high operation voltage VH, thereby turning on the transistors M3, M7and M8. When the transistor M3is turned on, the first control node N1is charged to a high voltage VH1approaching the high operation voltage VH, thereby turning on the transistor M1. When the transistors M7and M8are turned on, the second control node N2and the third control node N3are discharged to have a voltage level that is the same as the low operation voltage VL.

When a pulse of the clock signal CKV1arrives, the first control node N1is further charged to another high voltage VH2that is higher than the high voltage VH1. Meanwhile, a pulse signal (that is, the gate pulse of the gate driving signal G(1)) is output at the output terminal OUT in response to the pulse of the clock signal CKV1. In addition, since the pulse of the start pulse STV is ended, the fourth control node N4is discharged to the low operation voltage VL, thereby turning off the transistors M3, M7and M8.

When the pulse of the clock signal CKV2arrives, the fifth control node N5is charged to a high voltage approaching the high operation voltage, thereby turning on the transistor M4. When the transistor M4is turned on, the second control node N2is charged to a high voltage VH3approaching the high operation voltage, thereby turning on the transistor M2. Meanwhile, since the transistors M1and M2are turned on, the voltage at the output terminal OUT is discharged through both the transistors M1and M2at the same time. Therefore, the falling time Tfof the gate pulse of the gate driving signal G(1) is greatly reduced.

When the pulse of the clock signal CKV3arrives, the transistor M5is turned on, and the third control node N3is charged to the high voltage VH4approaching the high operation voltage VH, thereby turning on the transistor M6. When the transistor M6is turned on, the first control node N1is discharged to the low operation voltage VL, thereby turning off the transistor M1.

Note that in the embodiment of the invention, the voltage levels of the high voltages VH1, VH3and VH4may be equal to or a little bit lower than that of the high operation voltage VH. The voltage level of another high voltage VH2is higher than that of the high operation voltage VH, such that the voltage level of the gate pulse output by the shift register will not have “threshold loss” caused by the threshold voltage of the transistor M1.

Since the shift register400generates pulse signal according to the received clock signal only when the transistor M1is turned on, the high voltage region of the first control node N1capable of turning on the transistor M1may be regarded as the voltage region in which the shift register400is activated. In other words, in the forward scan, the operation of each shift register is activated in response to the first input signal received at the first input terminal IN1, and is deactivated in response to the clock signal received at the fourth clock input terminal C4. In addition, in this embodiment, when the pulse of the clock signal CKV4received at the third clock input terminal C3arrives, the shift register does not respond to it since the transistors M10and M12are not turned on at this time.

FIG. 6shows the waveforms of the corresponding signals and nodes of a shift register in the reverse scan according to the first embodiment of the invention. The waveforms shown inFIG. 6are the waveforms of the last stage shift register SR(M). Operation of the shift register in the reverse scan is similar to that in the forward scan, and the difference is only in that the pulses of the clock signals CKV4˜CKV1are sequentially generated in a cyclic manner. Those who are skilled in this technology can easily derive the operation of the shift register in the reverse scan according to that in the forward scan as illustrated above, and the related illustration are omitted here for brevity.

FIG. 7shows a circuit diagram of a shift register circuit according to a second embodiment of the invention. The shift register700may be either one of the shift registers SR(1)˜SR(M) shown inFIG. 3, and may comprise an input circuit710, a control circuit720and an output circuit730. For the convenience of illustration, the shift register700is regarded as the first stage shift register SR(1).

The input circuit710is coupled to a first input terminal IN1and a second input terminal IN2for respectively receiving the input signal STV and G(2) (that is, the gate driving signal output by a following stage shift register SR(2)). The output circuit730is coupled to the first clock input terminal C1for receiving the clock signal CKV1and outputs a pulse signal (that is, the gate pulse of the gate driving signal G(1)) at the output terminal OUT according the clock signal CKV1. The control circuit720is coupled to the output circuit730through the first control node N1, the second control node N2and the third control node N3, controls the voltages at the first control node N1, the second control node N2and the third control node N3according to the input signal STV or G(2), and further controls the operation of the output circuit730.

According to an embodiment of the invention, the output circuit730may comprise transistors M1, M2and a capacitor C. The transistor M1is coupled between the first clock input terminal C1and the output terminal OUT and comprises a control electrode coupled to the first control node N1. The transistor M2is coupled between the output terminal OUT and the low operation voltage VL and comprises a control electrode coupled to the second control node N2. The transistor M1is turned on or off according to a voltage at the first control node N1, and the transistor M2is turned on or off according to a voltage at the second control node N2.

The input circuit710may comprise transistors M23and M29. The transistor M23is coupled between the high operation voltage VH and the first control node N1and comprises a control electrode coupled to the first input terminal IN1. The transistor M23is turned on or off according to the voltage of the input signal received at the first input terminal IN1for controlling the voltage at the first control node N1in the forward scan. The transistor M29is coupled between the high operation voltage VH and the first control node N1and comprises a control electrode coupled to the second input terminal IN2. The transistor M29is turned on or off according to the voltage of the input signal received at the second input terminal IN2for controlling the voltage at the first control node N1in the reverse scan.

The control circuit720may comprise transistors M24, M25, M26, M27, M28and M30. The transistor M24is coupled between the high operation voltage VH and the second control node N2and comprises a control electrode coupled to the second clock input terminal C2. The transistor M24is turned on or off according to the voltage of the clock signal received at the second clock input terminal C2for controlling the voltage at the second control node N2in the forward scan. The transistor M30is coupled between the high operation voltage VH and the second control node N2and comprises a control electrode coupled to the third clock input terminal C3. The transistor M30is turned on or off according to the voltage of the clock signal received at the third clock input terminal C3for controlling the voltage at the second control node N2in the reverse scan.

The transistor M25is coupled between the high operation voltage VH and the third control node N3and comprises a control electrode coupled to the fourth clock input terminal C4. The transistor M25is turned on or off according to the voltage of the clock signal received at the fourth clock input terminal C4for controlling the voltage at the third control node N3. The transistor M26is coupled between the second control node N2and the third control node N3and comprises a control electrode coupled to the first clock input terminal C1. The transistor M26is turned on or off according to the voltage of the clock signal received at the first clock input terminal C1for controlling the voltage at the second control node N2.

The transistor M27is coupled between the first control node N1and the low operation voltage VL and comprises a control electrode coupled to the third control node N3. The transistor M27is turned on or off according to the voltage at the third control node N3for controlling the voltage at the first control node N1. The transistor M28is coupled between the third control node N3and the low operation voltage VL and comprises a control electrode coupled to the first control node N1. The transistor M28is turned on or off according to the voltage at the first control node N1for controlling the voltage at the third control node N3.

FIG. 8shows the waveforms of the corresponding signals and nodes of a shift register in the forward scan according to the second embodiment of the invention. Similarly, for the convenience of illustration, the waveforms as shown inFIG. 8are the waveforms of the first stage shift register SR(1). Based on the waveforms shown inFIG. 8, operations in the forward scan of the shift register in the second embodiment of the invention are illustrated in the following paragraphs.

When the start pulse STV arrives, the transistor M23is turned on and the first control node N1is charged to a high voltage VH1′ approaching the high operation voltage VH, thereby turning on the transistors M11and M28. When the transistor M28is turned on, the third control node N3is discharged to have a voltage level that is the same as the low operation voltage VL.

When a pulse of the clock signal CKV1arrives, the first control node N1is further charged to another high voltage VH2′ that is higher than the high voltage VH1′. Meanwhile, a pulse signal (that is, the gate pulse of the gate driving signal G(1)) is output at the output terminal OUT in response to the pulse of the clock signal CKV1. In addition, the transistor M26is turned on in response to the pulse of the clock signal CKV1for discharging the voltage at the second control node N2to the low operation voltage VL according to the voltage at the third control node N3. In addition, since the pulse of the start pulse STV is ended, the transistor M23is turned off.

When the pulse of the clock signal CKV2arrives, the transistor M24is turned on and the second control node N2is charged to a high voltage VH3′ approaching the high operation voltage, thereby turning on the transistor M2. Meanwhile, since the transistors M1and M2are turned on, the voltage at the output terminal OUT is discharged through both the transistors M1and M2at the same time. Therefore, the falling time Tfof the gate pulse of the gate driving signal G(1) is greatly reduced.

When the pulse of the clock signal CKV3arrives, the transistor M25is turned on, and the third control node N3is charged to the high voltage VH4′ approaching the high operation voltage VH, thereby turning on the transistor M27. When the transistor M27is turned on, the first control node N1is discharged to the low operation voltage VL, thereby turning off the transistor M1.

Note that in the embodiment of the invention, the voltage levels of the high voltages VH1′, VH3′ and VH4′ may be equal to or a little bit lower than that of the high operation voltage VH. The voltage level of another high voltage VH2′ is higher than that of the high operation voltage VH, such that the voltage level of the gate pulse output by the shift register will not have “threshold loss” caused by the threshold voltage of the transistor M1.

In addition, when the gate pulse of the gate driving signal G(2) of the following stage shift register SR(2) arrives, the transistor M29is turned on. However, the shift register does not respond to the gate pulse of the gate driving signal G(2) since the first control node N1still has a high voltage level.

Since the shift register700generates the pulse signal according to the received clock signal only when the transistor M1is turned on, the high voltage region of the first control node N1capable of turning on the transistor M1may be regarded as the voltage region in which the shift register700is activated. In other words, in the forward scan, the operation of each shift register is activated in response to the first input signal received at the first input terminal IN1, and is deactivated in response to the clock signal received at the fourth clock input terminal C4. In addition, when the pulse of the clock signal CKV4received at the third clock input terminal C3arrives, since the shift register is deactivated at this time, the shift register does not respond to it. In this manner, compared to the structure in the first embodiment, in the second embodiment, there is no need to use the control signals CSV and BCSV to define the scan direction and the scan direction can be naturally defined according to the sequence of generating the clock signals CKV1˜CKV4.

FIG. 9shows the waveforms of the corresponding signals and nodes of a shift register in the reverse scan according to the second embodiment of the invention. The waveforms shown inFIG. 9are the waveforms of the last stage shift register SR(M). Operation of the shift register in the reverse scan is similar to that in the forward scan, and the difference is only in that the pulses of the clock signals CKV4˜CKV1are sequentially generated in a cyclic manner. Those who are skilled in this technology can easily derive the operation of the shift register in the reverse scan according to that in the forward scan as illustrated above, and the related illustrations are omitted here for brevity.

As discussed above, in the embodiments of the invention, since the voltage at the output terminal OUT is discharged through both the transistors M1and M2at the same time, the falling time Tfof the gate pulse of the gate driving signal G(1) is greatly reduced. In addition, compared to the conventional design in which the size of the transistor M1cannot be reduced since the voltage at the output terminal is discharged only through the transistor M1, in the embodiment of the invention, the size of the transistor M1can be reduced since the voltage at the output terminal OUT is discharged through both the transistors M1and M2at the same time.

Moreover, unlike the conventional design, in which the size (that is, the width-to-length ratio W/L, or the width when the length of the transistors is fixed) of the transistor M1must be greater than that of the transistor M2, in the embodiments of the invention, the size (that is, the W/L or width) of the transistor M1can be smaller than that of the transistor M2. In addition, in the embodiments of the invention, the sizes of both the transistors M1and M2can be smaller than that of the transistors M1and M2of a conventional design. In this manner, the circuit area of the shift register can be greatly reduced, and the power consumption of the shift register can also be greatly reduced.