Over-current detection for a power field-effect transistor (FET)

A system and method is provided for detecting an over-current condition in a power field-effect transistor (FET). In one embodiment, an over-current detection circuit for detecting an over-current condition in a power FET comprises a current generator circuit operative to generate a reference current and a plurality of matched FETs operative to receive the reference current and provide a reference voltage, the matched FETs being matched to each other and to the power FET. The over-current detection circuit also comprises a comparator operative to measure a drain-to-source voltage of the power FET and to provide an output that indicates that the drain-to-source voltage of the power FET has exceeded the reference voltage.

TECHNICAL FIELD

This invention relates to electronic circuits, and more specifically to over-current detection for a power-field effect transistor (FET).

BACKGROUND

In the field of electronic design, amplifier circuits, such as a class-D amplifier, are commonly used to convert a given input signal to a similar signal of a greater magnitude. Amplifier circuits can typically only operate within a given input signal magnitude range, beyond which the amplifier circuit, or other associated circuitry, can be damaged by an over-current condition. Circuit designers of amplifier circuits often design safeguards or limitations into the amplifier circuits, thus providing warnings or otherwise preventing the occurrence of over-current conditions.

To detect an over-current condition in an amplifier circuit, circuit designers often generate a reference voltage to compare with the output voltage of the amplifier circuit. The reference voltage that is compared with the output voltage of the amplifier is derived from circuitry that is separate from the amplifier circuit. However, this reference voltage does not take into account process variations that may result in the manufacture of a power field-effect transistor (FET) of the amplifier circuit, such as variations in temperature or the drain-to-source resistance RDSonof the power FET. These manufacturing variations may result in inaccurate detection of an over-current condition. This reference voltage is also a static specification dictated by the manufacturer, and is not subject to change to suit the needs of the end-user of the amplifier circuit. Additionally, voltage spikes that result from inrush current at activation and deactivation of the power FET may cause false over-current detection, thus undesirably shutting off the amplifier circuit at inappropriate times.

SUMMARY

In one embodiment of the present invention, an over-current detection circuit for detecting an over-current condition in a power field-effect transistor (FET) comprises a current generator circuit operative to generate a reference current and a plurality of matched FETs operative to receive the reference current and provide a reference voltage, the matched FETs being matched to each other and to the power FET. The over-current detection circuit also comprises a comparator operative to measure a drain-to-source voltage of the power FET and to provide an output that indicates that the drain-to-source voltage of the power FET has exceeded the reference voltage.

In another embodiment of the present invention, an over-current detection circuit for detecting an over-current condition in a power FET comprising a plurality of current-mirror stages operative to generate a reference current and a switch operative to deactivate at least one of the plurality of current-mirror stages, the reference current comprising a sum of current values supplied from each of the plurality of current-mirror stages. The over-current detection circuit also comprises a resistor having a resistance value, the current values supplied from each of the plurality of current-mirror stages being determined by the resistance value of the resistor, and the switch deactivating the at least one of the plurality of current-mirror stages upon the resistance value of the resistor being below a predetermined magnitude. The over-current detection further comprises a comparator operative to measure a drain-to-source voltage of the power FET and to provide an output that indicates that the drain-to-source voltage of the power FET has exceeded a reference voltage determined by the reference current.

In another embodiment of the present invention, an over-current detection circuit for detecting an over-current condition in a power FET comprising a comparator operative to measure a drain-to-source voltage of the power FET and to provide an output that indicates that the drain-to-source voltage of the power FET has exceeded a reference voltage, and a blanking control circuit operative to at least one of activate and deactivate the over-current detection circuit at predetermined times that correspond to activation and deactivation of the power FET.

In another embodiment of the present invention, a method for detecting an over-current condition in a power FET comprising summing current values from each of a plurality of current mirror stages to generate a reference current, the magnitude of the current values from each of the plurality of current mirror stages being determined by a resistance value of an external resistor and generating a reference voltage by passing a reference current through a plurality of matched FETs, the matched FETs being matched to each other and to the power FET. The method also comprises comparing a drain-to-source voltage of the power FET to the reference voltage at predetermined times corresponding to at least one of activation and deactivation of the power FET, and generating an over-current output signal upon the drain-to-source voltage of the power FET exceeding the reference voltage.

In another embodiment of the present invention, an over-current detection circuit for detecting an over-current condition in a power FET comprising means for generating a reference current based on a resistance value of an external resistor, and means for generating a reference voltage based on the reference current, the reference voltage and a drain-to-source voltage of the power FET being measurable relative to each other independent of manufacturing process variables. The over-current detection circuit also comprises means for activating and deactivating the over-current detection circuit at predetermined times based on activation and deactivation of the power FET, and means for generating an output upon a drain-to-source voltage of the power FET exceeding the reference voltage.

DETAILED DESCRIPTION

The present invention relates to electronic circuits, and more specifically to over-current detection for a power-field effect transistor (FET), such as could be used in a class-D amplifier or switching power supply. In one aspect of the invention, an over-current detection circuit with an external resistor is used to compare an output voltage of the power FET to a reference voltage. The external resistor has a resistance value that determines the value of a reference current. The reference current is received by a plurality of matched FETs (e.g., FETs manufactured from the same substrate and having similar design characteristics) to provide a reference voltage. The output voltage of the power FET is compared to the reference voltage to determine the presence of an over-current condition. The external resistor thus allows an end-user the ability to adjust the magnitude of the reference voltage, and thus an allowable output current of the power FET, to properly suit the application. The plurality of matched FETs are also matched to the power FET, thus compensating for process variables such as temperature and resistance to allow more accurate comparison of the reference voltage to the output voltage of the power FET in a variety of different operating conditions. In one aspect of the invention, false comparisons of the reference voltage to the output voltage of the power FET resulting from output voltage spikes at activation and deactivation of the power FET are reduced by adding a blanking control circuit. The blanking control circuit deactivates the over-current detection circuit during switching of the power FET to mitigate false over-current detection.

FIG. 1illustrates an example of an amplifier circuit10, such as a class-D amplifier, in accordance with an aspect of the invention. The amplifier circuit10includes a high-side, represented by a high-side amplifier circuit12, and a low-side, represented by a low-side amplifier circuit14. The high-side amplifier circuit12receives an input, denoted HIGH-SIDE INPUT and provides an output signal, denoted as HIGH-SIDE OUTPUT. The low-side amplifier circuit14receives an input, denoted LOW-SIDE INPUT and provides an output signal, denoted as LOW-SIDE OUTPUT. An over-current detection circuit16is coupled to the outputs of each of the high-side amplifier circuit12and the low-side amplifier circuit14. The over-current detection circuit16thus receives inputs corresponding to the output voltages of each of the high-side amplifier circuit12and the low-side amplifier circuit14. The over-current detection circuit16includes an external resistor18coupled to ground, and provides an output signal OC SENSE OUT. It is to be understood that, although the example ofFIG. 1demonstrates an amplifier circuit, any other type of circuit that includes a power FET, such as a switching power supply, can utilize the over-current detection circuit16in accordance with an aspect of the invention.

The over-current detection circuit16measures the output voltages of the high-side amplifier circuit12and the low-side amplifier circuit14. If either of the output voltages of the high-side amplifier circuit12and the low-side amplifier circuit14are greater than a reference voltage, the over-current detection circuit16outputs the signal OC SENSE OUT. The over-current detection circuit16thus indicates that an over-current condition has occurred at either the high-side amplifier circuit12or the low-side amplifier circuit14. The reference voltage is determined by a resistance value of the external resistor18, such that different resistance values of the external resistor18can result in different reference voltage values.

It is to be understood that, although the example ofFIG. 1demonstrates an amplifier circuit10with both a high-side and a low-side, the over-current detection circuit16could work in accordance with an aspect of the invention with just one of either a high-side or a low-side. Additionally, in accordance with an aspect of the invention, the amplifier circuit10could include two separate over-current detection circuits16, one for each of the high-side and the low-side, and each including a separate external resistor18for determining independent reference voltages for outputting separate OC SENSE OUT signals.

FIG. 2illustrates a circuit50including a switching driver circuit52and an over-current detection circuit54in accordance with an aspect of the invention. The switching driver circuit52, which could be a low-side of an amplifier circuit, includes a gate drive circuit56and a power FET58. The gate drive circuit56receives power from a positive supply voltage VDDand controls a gate terminal of the power FET58. The over-current detection circuit54includes a resistor60coupled between a drain terminal and a source terminal of the power FET58, such that the voltage measured by the over-current detection circuit54is a drain-to-source voltage VDSof the power FET58. The voltage VDSis buffered by a gain amplifier62, which could be a unity gain amplifier, and is input to a positive terminal of a comparator64.

The over-current detection circuit54also includes a reference current generator circuit66that outputs a reference current IREF. An external resistor68is coupled between the reference current generator circuit66and ground. The external resistor68has a resistance value REXTthat determines the magnitude of the reference current IREF. The over-current detection circuit54includes three matched N-type FETs70,72, and74arranged in series, drain-to-source, interconnected between the output of the reference current generator circuit66and ground. It is to be understood that the matched FETs are matched to each other, such that they are manufactured from the same substrate with proportional and similar design characteristics, and thus have substantially the same operating characteristics. Each of the matched FETs70,72, and74has a gate terminal that is connected to the positive supply voltage VDD, such that all three of the matched FETs70,72, and74are activated. Because the three matched FETs70,72, and74are all activated with the same positive supply voltage VDD, each of them has a drain-to-source resistance RDSonthat is substantially equal. The reference current IREF, after being output from the reference current generator circuit66, flows through the matched FETs70,72, and74to ground. This current flow through the matched FETs70,72, and74generates a reference voltage VREFthat is input to a negative terminal of the comparator64, such that VREF=IREF*(3*RDSon). It is to be understood that, although the example ofFIG. 2demonstrates three matched FETs70,72, and74, more or less than three matched FETs can be utilized to generate the reference voltage VREFin accordance with an aspect of the invention.

The comparator64compares the output voltage VDSof the power FET58to the reference voltage VREF. If the voltage VDSis greater than the reference voltage VREF, the comparator64outputs a signal OC SENSE OUT, which corresponds to an over-current condition such that excessive current is flowing through the power FET58. The signal OC SENSE OUT can then be used for any purpose that the end-user of the amplifier sees fit, such as, for example, an alarm or a shut-off.

In addition to being matched to each other, the three matched FETs70,72, and74are also matched to the power FET58. Because the three matched FETs70,72, and74are also matched to the power FET58, and because the three matched FETs70,72, and74and the power FET58are all gate driven from the same positive supply voltage VDD, the comparator64can compare the reference voltage VREFto the voltage VDSindependent of process and temperature variables. This substantially increases over-current sensing accuracy in the over-current detection circuit54. In addition, because the resistance value REXTof the external resistor68determines the magnitude of the reference current IREF, the end-user of the circuit50can set the resistance value REXTof the external resistor68to generate a reference voltage VREFthat best suits the application to which the circuit50is applied.

It is to be understood that, although the circuit50includes only one switching driver circuit52(e.g., a low-side of an amplifier circuit), it could also be implemented for a high-side driver of an amplifier circuit. For example, in a high-side driver circuit, a bootstrap architecture could be implemented. One such architecture could include a diode interconnected between the positive supply voltage VDDand the gate drive circuit56, with a cathode at the gate drive circuit56, and a capacitor interconnected between the cathode and the source terminal of the power FET58. As another example, the over-current detection circuit54could include additional switching driver circuits, such as depicted in the example ofFIG. 1, in accordance with an aspect of the invention. For example, the over-current detection circuit54could include additional comparators64, one for each additional switching driver circuit, such that each additional comparator could compare a voltage VDSof a power FET from the corresponding additional switching driver circuit to the reference voltage VREF. Alternatively, each additional switching driver circuit could have a separate corresponding over-current detection circuit, such that each additional switching driver circuit could compare a voltage VDSof its corresponding power FET to an independent reference voltage VREF, for individual control of the over-current detection of each of the additional switching driver circuits.

FIG. 3illustrates an example of a reference current generator circuit100operative to generate the reference current IREF, in accordance with an aspect of the invention. An external resistor102is interconnected between ground and a node104. As described above regardingFIG. 2, the reference current generator circuit100generates the reference current IREFbased on a resistance value REXTof the external resistor102. An internal resistor106having a resistance value of R1is interconnected between the node104and a node108. The node108is connected to a negative input to an op-amp110and a source terminal of an N-type FET112. The op-amp110receives a band-gap voltage VBGat a positive input, and has an output connected to a gate terminal of the FET112, such that the FET112is always activated and the op-amp110is arranged as a feedback buffer.

The band-gap voltage VBGcan be independent of process and temperature variables. As an example, the band-gap voltage VBGcould be approximately 1.2V-1.3V, but it is to be understood that any suitable value for the band-gap voltage VBGcan be utilized in accordance with an aspect of the invention. Because the op-amp110is arranged as a feedback buffer, the voltage at the node108is also fixed approximately equal to the band-gap voltage VBG. Accordingly, a current IAflows through the resistors106and102, such that IA=VBG/(R1+REXT).

The reference current generator circuit100includes a P-type FET114with a source terminal connected to a positive supply voltage VDD, and with a gate and a drain terminal that are both connected to a node116, such that the FET114is diode connected and thus always activated. Because the node108is fixed at approximately VBG, the current flow through the FET114is approximately equal to the current IA. The reference current generator circuit100also includes three output P-type FETs118,120, and122, each with a gate terminal connected to the node116, such that the output FETs118,120, and122are arranged as current-mirror stages. Accordingly, the current IAthrough the FET114is mirrored proportionally as a current IBthrough the output FET118, as a current ICthrough the output FET120, and as a current IDthrough the output FET122. The currents IB, IC, and IDare all added together at an output of the reference current generator circuit100as the reference current IREF.

It is to be understood that, although there are three current-mirror stages of output FETs118,120, and122in the example ofFIG. 3, there can be more or less current-mirror stages in accordance with an aspect of the invention. In addition, the relationships between the values of the currents IA, IB, IC, and IDis a matter of preference depending on the desired magnitude of the reference current IREF, and can be modified by varying the channel widths of the output FETs. As an example, the substantial majority of the reference current IREFcan be supplied by the current IDby making the channel width of the output FET122significantly larger than the channel widths of the other output FETs, such that IB=IA, IC=IA, and ID=(8*IA). As an alternative, FETs of the same channel width can be chosen for the FETs114,118,120, and122(e.g., IA=IB=IC=ID), or the channel widths of the output FETs could double from one current-mirror stage to the next (e.g., IB=(2*IA), IC=(4*IA), ID=(8*IA)).

As the resistance value REXTof the external resistor102changes, the value of the current IAchanges as well. More specifically, as demonstrated above, the current IAand the resistance value REXTof the external resistor102have an inversely proportional relationship, such that the current IAdecreases as the resistance value REXTof the external resistor102increases. The magnitudes of the currents IB, IC, and IDare proportional to the magnitude of the current IAand have a sum that equals the reference current IREF. Therefore, the resistance value REXTof the external resistor102determines the value of the reference current IREF. As described above regardingFIG. 2, the reference current IREFgenerates the reference voltage VREFto detect an over-current condition for a power FET used, for example, in a class-D amplifier. An end-user of an over-current detection circuit, such as the over-current detection circuit54in the example ofFIG. 2, can thus set a resistance value REXTthat corresponds to a desired reference voltage VREF.

As stated above, it is important to prevent over-current conditions in amplifiers to prevent damage to the circuit components of the amplifier. Because the resistance value REXTof the external resistor102determines the reference voltage VREF, an end-user of an amplifier with an over-current detection circuit in accordance with an aspect of the invention could attempt to push the reference voltage VREFto a value that is beyond an acceptable range of safe operation for the amplifier circuit. The end-user could attempt this by setting the resistance value REXTof the external resistor102to a very low magnitude, such as very close to or equal to zero (e.g., short-circuiting the node104to ground). However, the reference current generator circuit100includes two safeguards to prevent the reference current IREFfrom becoming too large, thus preventing unsafe values of the reference voltage VREF. The first such safeguard for preventing unsafe values of the reference voltage VREFis the inclusion of the internal resistor106. Without the internal resistor106, a resistance value REXT=0 of the external resistor102would cause a short circuit of the voltage VBGto ground, forcing the current IAto approach an infinite magnitude. The second such safeguard, in accordance with an aspect of the invention, is a sub-circuit124that also operates to prevent the reference current IREF, and thus the reference voltage VREF, from reaching an unsafe value.

The sub-circuit124includes a comparator126that has a positive input terminal that is connected to a preset voltage VPS. The preset voltage VPScan be small, such as, for example, approximately 0.2V. The sub-circuit124also includes a resistor128and an N-type FET130interconnected between a negative input terminal of the comparator126, a negative supply voltage VSS, and the node104. The resistor128and the FET130act as an RC filter, such that the negative input terminal of the comparator126can receive a steady measurement of a voltage VXat the node104. The sub-circuit124also includes a P-type FET132that acts as a switch and has a gate terminal connected to an output of the comparator126. The switch132is interconnected at a source terminal to the output FET122and at a drain terminal to the output of the reference current generator circuit100.

As described above, the node108has a voltage that is fixed at approximately VBG. Therefore, the voltage VXat the node104changes with different resistance values REXTof the external resistor102. Accordingly, the comparator126compares the voltage VXat the node104with the preset voltage VPS. If the voltage VXis greater than the preset voltage VPS, then the resistance value REXTof the external resistor102, as chosen by the end-user, is acceptable for normal operation of the amplifier circuit. The comparator126responds by outputting a low (e.g., logic 0) signal to the gate terminal of the switch132, which activates (closes) the switch132. When closed, the switch132conducts the current IDfrom its source terminal to its drain terminal, thus adding the current IDto the reference current IREF. If the voltage VXis less than the preset voltage VPS, then the resistance value REXTof the external resistor102, as chosen by the end-user, is too small for normal operation of the amplifier circuit. The comparator126responds by outputting a high (e.g., logic 1) signal, which deactivates (opens) the switch132. When open, the switch132prevents conduction of the current ID, such that the current-mirror stage that conducts the current IDis not added to the reference current IREF. Therefore, the sub-circuit124can limit the amount of the reference current IREF. An end-user can thus be prevented from pushing the reference voltage VREFto a value that is beyond an acceptable range of safe operation for the amplifier circuit, such as by setting the resistance value REXTof the external resistor102to a very low magnitude (e.g., very close to or equal to zero). It is to be understood that, in accordance with an aspect of the invention, the sub-circuit124need not be limited to activating/deactivating only one of the current-mirror stages. Additional current-mirror stages can also be activated/deactivated to better control the amount of the reference current IREFbased on the resistance value REXTof the external resistor102.

FIG. 4, in continuance of the discussion ofFIG. 3, illustrates a graph150of the resistance value REXTversus the reference current IREF. Accordingly, the graph150demonstrates the variations of the reference current IREFas a result of changes in the resistance value REXTof the external resistor102, in accordance with an aspect of the invention.

At a resistance value REXT=0Ω, the reference current IREFis equal to I1. As described above with regard toFIG. 3, the reference current generator circuit100prevents the reference current IREFfrom attaining a magnitude that would cause the reference voltage VREFto reach a value that is beyond an acceptable range of safe operation for the amplifier circuit by the inclusion of the internal resistor106and the sub-circuit124in accordance with an aspect of the invention. Such an unacceptable range of safe operation for the amplifier circuit of the reference voltage VREFcould result from an end-user setting the resistance value REXTof the external resistor102to a very low magnitude (e.g., very close to or equal to zero). Therefore, at REXTbeing equal to 0Ω, as described above with regard toFIG. 3, the voltage VXat the node104is less than the preset voltage VPS, such that the comparator126has opened the switch132, preventing the current IDfrom being added to the reference current IREF. As the resistance REXTincreases from zero, the magnitude of the reference current IREFdecreases as there is less current IAflowing through the external resistor102.

At a resistance value REXT=RX, the reference current IREFincreases substantially to IMAX. It is at the point upon REXTapproximately equal to RXthat the voltage VXat the node104becomes greater than the preset voltage VPS, such that the comparator126has activated the switch132, and thus adding the current IDto the reference current IREF. As the resistance REXTincreases from RX, the magnitude of the reference current IREFdecreases as there is less current IAflowing through the external resistor102.

It is to be understood that, in the example ofFIG. 4, the relationship between the magnitudes of the reference current IREFat IREF=I1and IREF=IMAXneed not be as depicted in the graph150. For example, I1could be equal to or even greater than IMAX. The relationship between I1and IMAXdepends on a number of factors, such as the channel width of the output transistor122, the resistance value REXTof the external resistor102at REXT=RX, the magnitude of the preset voltage VPS, etc. The graph150is merely intended to demonstrate an example of the relative changes in the value of the reference current IREFas the resistance REXTincreases, in accordance with an aspect of the invention.

FIG. 5illustrates another example of a circuit200including a switching driver circuit202and an over-current detection circuit204in accordance with an aspect of the invention. The switching driver circuit202, which could be a low-side of an amplifier circuit, includes a gate drive circuit206and a power FET208. The gate drive circuit206receives power from a positive supply voltage VDDand controls a gate terminal of the power FET208. The over-current detection circuit204includes a resistor210and an N-type FET211coupled between a drain terminal and a source terminal of the power FET208. The FET211acts as a switch, such that, when the switch211is closed, the voltage measured by the over-current detection circuit204is approximately a drain-to-source voltage VDSof the power FET208. It is to be understood that the switch211need not be a FET, but could be any other type of switch known in the art. The voltage VDSis buffered by a gain amplifier212, which could be a unity gain amplifier, and is input to a positive terminal of a comparator214.

The over-current detection circuit204also includes a reference current generator circuit216that outputs a reference current IREF. An external resistor218is coupled between the reference current generator circuit216and ground. The external resistor218has a resistance value that determines the magnitude of the reference current IREF. The over-current detection circuit204includes three matched N-type FETs220,222, and224arranged in series, drain-to-source, interconnected between the output of the reference current generator circuit216and ground. Each of the matched FETs220,222, and224has a gate terminal that is connected to the positive supply voltage VDD, such that all three of the matched FETs220,222, and224are activated. Because the three matched FETs220,222, and224are all activated with the same positive supply voltage VDD, each of them has a drain-to-source resistance RDSonthat is substantially equal. The reference current IREF, after being output from the reference current generator circuit216, flows through the matched FETs220,222, and224to ground. This current flow through the matched FETs220,222, and224generates a reference voltage VREFthat is input to a negative terminal of the comparator214, such that VREF=IREF*(3*RDSon).

It is to be understood that, although the example ofFIG. 5demonstrates three matched FETs220,222, and224, more or less than three matched FETs can be utilized to generate the reference voltage VREFin accordance with an aspect of the invention. It is to be further understood that, as described above regardingFIG. 2, the three matched FETs220,222, and224may also be matched to the power FET208, as well as driven from the same positive supply voltage VDD. The comparator214can therefore compare the reference voltage VREFto the voltage VDSindependent of process and temperature variables, such that over-current sensing accuracy in the over-current detection circuit204is greatly increased. Additionally, because the resistance value of the external resistor218determines the magnitude of the reference current IREF, the end-user of the circuit200can set the resistance value of the external resistor218to generate a reference voltage VREFthat best suits the application to which the circuit200is applied.

The comparator214compares the output voltage VDSof the power FET208to the reference voltage VREF. If the voltage VDSis greater than the reference voltage VREF, the comparator214outputs a signal OC SENSE OUT, which corresponds to an over-current condition such that excessive current is flowing through the power FET208. The signal OC SENSE OUT can then be used for any purpose that the end-user of the amplifier sees fit, such as, for example, an alarm or a shut-off.

The over-current detection circuit204ofFIG. 5also includes a blanking control circuit226interconnected between the output of the gate drive circuit206and a gate terminal of the switch211. The blanking control circuit226operates to control the switch211, such that the drain-to-source voltage VDSof the power FET208can be measured by the comparator214only at certain times. For example, when the gate drive circuit206initially drives the gate terminal of the power FET208, the drain-to-source voltage VDSof the power FET208will spike due to the excessive inrush current upon activation. Such a voltage spike, if measured by the comparator214, would most likely cause a false over-current measurement, resulting in the comparator214outputting the OC SENSE OUT signal at an undesired time. The blanking control circuit226therefore activates the switch211only when the drain-to-source voltage VDSwould yield appropriate measurements for the purpose of determining the existence of an over-current condition in the power FET208. For example, the blanking control circuit226could wait for a predetermined time after the gate drive circuit206drives the power FET208before activating the switch211, such that a false over-current measurement due to inrush current can be avoided. A similar scenario may exist at deactivation of the power FET208, such that the blanking control circuit226could deactivate the switch211for a predetermined time before and after deactivation of the power FET208, such that a false over-current measurement due to a shut-off voltage spike can be avoided.

In view of the foregoing structural and functional features described above, certain methods will be better appreciated with reference toFIG. 6. It is to be understood and appreciated that the illustrated actions, in other embodiments, may occur in different orders and/or concurrently with other actions. Moreover, not all illustrated features may be required to implement a method.

FIG. 6demonstrates a method250for detecting an over-current flow through a power FET, such as could be used in a class-D amplifier, in accordance with an aspect of the invention. At252, the method250sets a resistance value REXTof an external resistor to provide a reference current IREF. The external resistor could be provided by an end-user, and the resistance value REXTof the external resistor determines the magnitude of the reference current IREF. At254, the method250generates a reference voltage VREFby passing the reference current IREFthrough a plurality of matched FETs. The plurality of matched FETs could also be matched to the power FET, and could be provided with a gate voltage that is the same as the power FET, such that the reference voltage VREFis generated independent of process variables and thermal conditions relative to the output voltage of the power FET. Also, since the resistance value REXTof the external resistor sets the reference current IREF, which is used to generate the reference voltage VREF, the end-user can set the resistance value REXTof the external resistor to best suite the end-user's application.

At256, the method250measures the output voltage of the power FET, which could be a drain-to-source voltage VDS, at certain predetermined times. The timing of the measurement of the output voltage of the power FET could be performed by a blanking control circuit. The predetermined times could be for a predetermined time before and after activation of the power FET and/or for a predetermined time before and after deactivation of the power FET. At258, the method250compares the output voltage VDSof the power FET with the reference voltage VREF. This comparison could be performed by a comparator. At260, the method250provides an output upon an over-current condition resulting from an over-current flow through the power FET. The output could be provided by the comparator upon the comparator measuring that the output voltage VDSof the power FET is greater than the reference voltage VREF. The output could be used to shut off the class-D amplifier for which the power FET is used, or to provide an over-current alarm, or for any other reason that an end-user of the class-D amplifier determines is necessary.