Current mirror amplifier

A current mirror amplifier in which the potentials appearing across the principal conduction paths of its master and slave transistors are maintained substantially the same. This is done by a differential-input, single-ended output amplifier, which is connected as a non-inverting amplifier in the direct-coupled feedback connection that conditions the master transistor to conduct applied input current via its principal conduction path.

The present invention relates to transistor amplifiers and more 
particularly to current mirror amplifiers. 
A current mirror amplifier is defined in connection with the present 
invention as an amplifier having a current gain substantially equal to the 
transconductance of a slave transistor divided by the transconductance of 
a master transistor. Each transistor has first and second electrodes and a 
principal conduction path therebetween and has a control electrode, with 
the conductances of the principal conduction path controlled in response 
to potential applied between the first and control electrodes. The master 
transistor has an input current applied to its principal conduction path 
and is provided with direct-coupled feedback between its second and 
control electrodes to apply a potential between its first and control 
electrodes that conditions its principal conduction path to conduct all or 
substantially all the input current. The potential between the first and 
control electrodes of the master transistor is applied between the first 
and control electrodes of the slave transistor to condition its principal 
conduction path to conduct the desired level of output current. 
A basic reason for using a current mirror amplifier is that its current 
gain being determined by the ratio between the transconductances of its 
slave and master transistors, and the transconductances of transistor 
devices relying directly on certain physical dimensions that are readily 
proportioned as between transistors, the current gain of the current 
mirror amplifier can be accurately predicted despite shared variations in 
the transistors. Ideally, this current gain is constant despite expected 
changes in input and output current, potential levels and shared 
temperature variations. 
Field effect transistors (FET's) can be used as the master and slave 
transistors. The first and second electrodes of an FET correspond to its 
source and drain electrodes; its principal conduction path is its channel; 
and its control electrode is its gate electrode. However, the 
transconductance of a FET changes, not only as a function of its physical 
dimensions, but also as a function of its source-to-drain potential. This 
dependence of FET transconductance upon source-to-drain potential is a 
substantially stronger second order effect than the dependence of the 
transconductance of a bipolar transistor on its emitter-to-collector 
potential; both effects are often referred to as "Early effect." Current 
mirror amplifier configurations in which the potentials appearing across 
the principal conduction paths of the master and slave transistors are not 
constrained to be equal, have undesirable inaccuracies in current gain 
when these transistors are FET's. 
The present invention is embodied in a current mirror amplifier in which 
the potentials appearing across the principal conduction paths of its 
master and slave transistors are maintained substantailly the same by a 
differential-input single-ended-output amplifier, which is connected as a 
non-inverting amplifier in the direct-coupled feedback connection of the 
master transistor.

FIG. 1 shows a long-tailed pair configuration comprising transistors 
Q.sub.1 and Q.sub.2 and a constant current generator S.sub.1 that demands 
a current I.sub.1 + I.sub.2. Q.sub.1 and Q.sub.2 supply drain currents 
I.sub.1 and I.sub.2 that exhibit variations that are balanced with respect 
to each other, responsive to differential-mode potential applied between 
the non-inverting and inverting input terminals T.sub.1 and T.sub.2 
connected to their respective gate electrodes. A current mirror amplifier 
CMA has an input terminal T.sub.3 connected to the drain electrode of 
Q.sub.1, has an output terminal T.sub.4 connected to the source node N as 
the drain electrode of Q.sub.2, and has a common terminal T.sub.5. Current 
mirror amplifier CMA functions as a balanced-to-single-ended signal 
converter, inverting the differential-mode signal variations in the drain 
current I.sub.1 of Q.sub.1 for application to node N where they combine 
constructively with the different-mode signal variations in the drain 
current I.sub.2 of Q.sub.2. To satisfy Kirchoff's Law of Currents, the 
combined differential-mode current components flow through output load OL, 
developing a signal voltage thereacross in accordance with Ohm's Law. 
Common-mode direct current components of the drain current of Q.sub.2 and 
the output current of CMA combine destructively at node N, satifying 
Kirchoff's Law of Currents, so that no direct current responsive to these 
common-mode components flows through output load OL connected between node 
N and the positive terminal of voltage supply S.sub.2. So the direct 
component of potential at node N -- that is, the quiescent potential -- is 
the same as that at the positive terminal of supply S.sub.2, connected at 
its negative terminal to reference ground, assuming that the direct 
component present in the applied signal is zero. 
A further voltage supply S.sub.3 is connected at its negative terminal to 
the positive terminal of voltage source S.sub.2, and the positive terminal 
of S.sub.3 has the common terminal T.sub.5 of current mirror amplifier CMA 
connected to it. 
Q.sub.3 and Q.sub.4 are the master and slave transistors, respectively, in 
the CMA. The drain electrodes of Q.sub.3 and Q.sub.4 are connected to the 
input terminal T.sub.3 of CMA and to the output terminal T.sub.4 of CMA, 
respectively, and their source electrodes are connected to the common 
terminal T.sub.5 of the CMA. Direct-coupled drain-to-gate feedback is 
applied to Q.sub.3 by a differential-input, single-ended-output amplifier 
DA. Gate-to-gate connection provides Q.sub.3 and Q.sub.4 with like gate 
potentials. As with any feedback system, some capacitance such as C shown 
in dotted outline may be needed to augment the stray capacitance inherent 
in the current mirror amplifier CMA, to assure stability against 
self-oscillatory tendencies. 
DA comprises: (a) FET's Q.sub.5 and Q.sub.6 connected in long-tailed pair 
configuration with constant current generator S.sub.4, which demands a 
current I.sub.5 + I.sub.6 ; (b) FET's Q.sub.7 and Q.sub.8 connected in a 
subsidiary current mirror amplifier configuration SCMA; and (c) connection 
to the subsidiary current mirror amplifier SCMA as a 
balanced-to-single-ended signal converter to convert the balanced 
collector currents I.sub.5 and I.sub.6 and Q.sub.5 and Q.sub.6 to 
single-ended form for application to the gate electrode of Q.sub.3. More 
particularly, the current mirror amplifier SCMA has an input connection at 
the interconnected drain electrode of Q.sub.7 and gate electrodes of 
Q.sub.7 and Q.sub.8, an output connection at the drain electrode of 
Q.sub.8, and a common connection at the interconnection of the source 
electrodes of Q.sub.7 and Q.sub.8 . 
A current I.sub.1 is withdrawn from input terminal T.sub.3 of current 
mirror amplifier CMA. If I.sub.1 exceeds the drain current I.sub.3 of 
Q.sub.3 there is a tendency for the gate electrode of Q.sub.5 to be drawn 
to a potential less positive than the potential at the gate of Q.sub.6. 
This reduces the conduction of Q.sub.5 vis-a-vis Q.sub.6 in their 
long-tailed pair connection, causing the portions of the current demand 
imposed by constant current generator S.sub.4 that are satisfied by the 
source currents of Q.sub.5 and Q.sub.6 to be respectively relatively small 
and relatively large. This cuases the drain current I.sub.5 of Q.sub.5 to 
be correspondingly small, which current is demanded from the input 
connection of subsidiary current mirror amplifier SCMA to cause a 
correspondingly small drain current to be supplied by Q.sub.8. The drain 
current I.sub.6 demanded by Q.sub.6 being of the same amplitude as the 
source current of Q.sub.6 is relatively large compared to the drain 
current supplied by Q.sub.8. So the potential at the gate electrodes of 
Q.sub.3 and Q.sub.4, to which the drain electrodes of Q.sub.6 and Q.sub.8 
connect, is drawn to a less positive potential. This increases the 
amplitude of the source-to-gate potentials of Q.sub.3 and Q.sub.4, 
increasing the conduction of Q.sub.3 and Q.sub.4 to adjust the drain 
current I.sub.3 of Q.sub.3 to equal I.sub.1. 
On the other hand, if the I.sub.3 exceeds I.sub. 1, there is a tendency for 
the gate electrode of Q.sub.5 to be drawn to a potential more positive 
than the potential at the gate electrode of Q.sub.6. This increases the 
conduction of Q.sub.5 vis-a-vis Q.sub.6, causing I.sub.5 to be relatively 
large compared to I.sub.6. The relatively large I.sub.5 withdrawn from the 
input connection of SCMA causes the collector current of Q.sub.8 to be 
correspondingly large such that it exceeds I.sub.6 in amplitude to draw 
the potential at the gate electrodes of Q.sub.3 and Q.sub.4 to more 
positive value. This reduces the amplitude of the source-to-gate 
potentials (V.sub.GS 's) of Q.sub.3 and Q.sub.4, reducing the conduction 
of Q.sub.3 and Q.sub.4 to adjust I.sub.3 to equal I.sub.1. 
If the transconductance of the amplifier DA is made sufficiently large, 
only a very small difference between the gate potentials of Q.sub.5 and 
Q.sub.6 will be required to adjust the conduction of Q.sub.3 to make 
I.sub.3 equal to I.sub.1. Ideally, of course, zero difference will be 
required. But in actuality, if Q.sub.3 and Q.sub.4 have appreciable 
gate-to-drain potentials, there will be some difference required to 
compensate for the mismatch in the transconductances (g.sub. m 's) of 
Q.sub.7 and Q.sub.8 caused by their source-to-drain potentials (V.sub.DS 
's) differing somewhat. The V.sub.DS of Q.sub.7 will be its own V.sub.GS. 
This error can be reduced at lower V.sub.DS 's for Q.sub.3 and Q.sub.4, 
where a difference in their V.sub.DS 's would cause the most difference 
between their g.sub. m 's, by choosing I.sub.5 + I.sub.6 equal to I.sub.1 
+ I.sub.2 times the ratio of the g.sub. m 's of Q.sub.5 and Q.sub.6 to the 
g.sub. m 's of Q.sub.3 and Q.sub.4. At larger V.sub.DS 's for Q.sub.3 and 
Q.sub.4 the small difference between their V.sub.DS 's due to offset 
between the V.sub.GS 's of Q.sub.5 and Q.sub.6 does not affect their 
relative g.sub. m 's very much. 
Since the g.sub. m 's of Q.sub.3 and Q.sub.4 match well over the entire 
range, owing to amplifier DA maintaining their V.sub.DS 's substantially 
equal, their similar V.sub.GS 's will cause their source-to-drain currents 
to be in constant proportion. This is a 1:1 proportion where Q.sub.3 and 
Q.sub.4 are devices with matching dimensions, as would be used in a 
current mirror amplifier such as CMA used for balanced-to-single-ended 
conversion. 
Modifications of the CMA where Q.sub.3 and Q.sub.4 have transconductances 
that are in ratio other than 1:1 are possible. Assuming Q.sub.3 and 
Q.sub.4 to be monolithic FET's, one can scale their g.sub. m 's by making 
them with channels having differing width-to-length ratios, as is well 
known. Q.sub.7 and Q.sub.8 have g.sub. m 's in the same ratio as those of 
Q.sub.5 Q.sub.6. 
FIG. 2 shows a modification CMA' of the FIG. 1 current mirror amplifier CMA 
suitable for use in a monolithic integrated circuit technology in which 
NPN bipolar transistors and P-channel FET's are available. FET's Q.sub.5 
and Q.sub.6 are replaced by the relatively high transconductance bipolar 
transistors. Only a few millivolts difference will appear between the base 
potentials of Q.sub.5 ' and Q.sub.6 ' despite one being substantially more 
conductive than the other. So error in the current gain of CMA' due to 
mismatch of the V.sub.DS 's of Q.sub.3 and Q.sub.4 will be virtually 
non-existant. Some error due to the base currents of Q.sub.5 and Q.sub.6 
will appear in the current gain of CMA', but it will be small so long as 
the current I.sub.5 + I.sub.6 is chosen so as not to be much larger than 
I.sub.1 + I.sub.2. 
A number of modifications of the FIG. 1 and FIG. 2 will, in light of this 
application, suggest themselves to one skilled in the art of integrated 
circuit design. For example, one may alternatively replace Q.sub.5 and 
Q.sub.6 with FET devices having their transconductances multiplied by 
bipolar transistors. Q.sub.3 and Q.sub.4 may be provided with source 
degeneration resistors. Current generators S.sub.1 and S.sub.4 may be 
provided by simple resistive connections or from the collector or drain 
electrodes of fixed-bias transistors. A current mirror amplifier 
configuration according to the present invention is useful when all the 
transistors are of bipolar type, including Q.sub.3 and Q.sub.4, although 
the need for avoiding Early effect is less acute with bipolar transistors. 
Diodes may be introduced into the amplifier DA to adjust the V.sub.DS 's 
of Q.sub.7 and Q.sub.8 to more equal value, if the conditions under which 
the current mirror amplifier is to operate are well defined. All such 
modifications which are in the spirit of the invention are to be 
considered within the scope of the following claims. 
In the following claims a "transistor" is any current amplifying 
arrangement having input, common and output electrodes. The term "input" 
electrode is generic to the base electrode of a bipolar transistor and to 
the gate electrode of an FET; "common" electrode, to the emitter electrode 
of a bipolar transistor and to the source electrode of an FET; and 
"output" electrode to the collector electrode of a bipolar transistor and 
to the drain electrode of an FET, for example.