Liquid crystal display

An exemplary embodiment of the present invention relates to a liquid crystal display having a display area and a non-display area which includes a first substrate and a second substrate facing the first substrate, a layer having a first opening, a spacer disposed in the first opening, and a first light blocking member disposed in the non-display area. The spacer is disposed in the first opening to maintain an interval between the first substrate and the second substrate. The spacer and the first light blocking member include the same material.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority from and the benefit of Korean Patent Application No. 10-2009-0113477, filed on Nov. 23, 2009, which is hereby incorporated by reference for all purposes as if fully set forth herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a liquid crystal display.

2. Discussion of the Background

A liquid crystal display (LCD) is one of the most widely used flat panel displays (FPD), and is composed of two display panels on which electrodes are formed, and a liquid crystal layer interposed between the two display panels. A voltage is applied to the electrodes to generate an electric field on the liquid crystal layer, and the orientation of liquid crystal molecules in the liquid crystal layer is determined and the polarization of incident light is controlled through the generated electric field to display an image.

A widely used LCD has a structure in which field generating electrodes are respectively formed on two display panels. Among the two display panels, a plurality of pixel electrodes and thin film transistors are arranged in a matrix format on one display panel (hereafter referred to as a “thin film array panel”), color filters of red, green, and blue and a light blocking member are formed on the other display panel (hereafter referred to as a “common electrode panel”), and one common electrode covers the entire surface of the other display panel.

However, when the pixel electrodes and the color filters are formed on different display panels, it may be difficult to correctly align the pixel electrodes and the color filters, which may cause an alignment error. To solve this problem, a color filter on array (COA) structure may be used in which the pixel electrodes and the color filters may be formed on the same display panel.

Also, when considering a combination margin of the thin film transistor array panel and the common electrode panel, a light blocking member such as a black matrix may be formed with a larger than predetermined size. However, the aperture ratio may be decreased by the size of the black matrix so that the black matrix may alternatively be formed in the thin film transistor array panel.

An interval of the liquid crystal layer between two display panels is referred to as a cell gap, and the cell gap influences general operation characteristics of the LCD such as response speed, contrast ratio, viewing angle, and luminance uniformity. If the cell gap is not uniform, a uniform image may not be displayed on the whole screen, which may deteriorate the display quality. Accordingly, a plurality of spacers may be formed on one of the two panels to maintain the uniform cell gap throughout the whole region of the substrate.

The light blocking member including the black matrix prevents light leakage at the boundary of the pixels and a non-display area at the circumference of the display area. The spacer and the light blocking member may be simultaneously formed to simplify a manufacturing process. However, when the height of the spacer is low, it may be difficult to form the light blocking member with sufficient optical density to prevent light leakage in the non-display area.

SUMMARY OF THE INVENTION

Exemplary embodiments of the present invention provide a light blocking member arranged in a non-display area of an LCD which is formed with a spacer.

An exemplary embodiment of the present invention discloses an LCD including a display area and a non-display. The LCD includes a first substrate and a second substrate facing the first substrate, a layer having a first opening, a spacer disposed in the first opening, and a first light blocking member disposed in the non-display area. The spacer is disposed in the first opening to maintain an interval between the first substrate and the second substrate. The spacer and the first light blocking member include the same material.

An exemplary embodiment of the present invention also discloses a manufacturing method of an LCD including a display area and a non-display. The method includes coupling a first substrate and a second substrate together, forming a layer having a first opening on the first substrate, forming a spacer disposed in the first opening, the spacer to maintain an interval between the first substrate and the second substrate, and forming a first light blocking member in the non-display area. The spacer and the first light blocking member are simultaneously formed.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

FIG. 1is a layout view of an LCD according to an exemplary embodiment of the present invention.FIG. 2is a layout view of an equivalent circuit diagram of one pixel of an LCD according to an exemplary embodiment of the present invention.

Referring toFIG. 1andFIG. 2, the LCD according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly300and a gate driver400and a data driver500connected thereto, a gray voltage generator (not shown) connected to the data driver500, a light source unit (not shown) to provide light to the liquid crystal panel assembly300, a light source driver (not shown) to control the light source unit (not shown), and a signal controller (not shown).

The gate driver400or the data driver500may be formed on the lower panel100of the liquid crystal panel assembly300, or may be formed separately in the shape of an integrated circuit (IC) chip.

The liquid crystal panel assembly300includes lower and upper panels100and200, and a liquid crystal layer3interposed between the two panels100and200. As shown inFIG. 1, a plurality of gate lines121proceed in the row direction, and a plurality of data lines171proceed in the column direction, in the liquid crystal panel assembly300. A plurality of pixels are connected to the gate and data lines121and171and arranged roughly in the form of a matrix. A sealant310is formed at the outer boundary of the liquid crystal panel assembly300so as to seal the liquid crystal molecules of the liquid crystal layer3.

The liquid crystal layer3may have positive (+) or negative (−) dielectric anisotropy, and liquid crystal molecules of the liquid crystal layer3may be aligned such that directors thereof stand substantially parallel or perpendicular to the surface of the two display panels100and200when an electric field is not applied thereto.

Alignment layers (not shown) may be formed on the inner surfaces of the display panels100and200. The alignment layers may be vertical alignment layers. Polarizers (not shown) may be formed on the outer surfaces of the display panels100and200.

Referring toFIG. 2, an LCD according to an exemplary embodiment of the present invention includes signal lines including a plurality of gate lines GL, a plurality of pairs of data lines DLa and DLb, and a plurality of storage electrode lines SL, and a plurality of pixels PX connected thereto.

The pixels PX include a pair of sub-pixels PXa and PXb, which include switching elements Qa and Qb, liquid crystal capacitors Clca and Clcb, and storage capacitors Csta and Cstb, respectively.

The switching elements Qa and Qb are three-terminal elements such as thin film transistors formed on the lower panel100. The control terminals of the switching elements Qa and Qb are connected to the gate lines GL, the input terminals thereof are connected to the data lines DLa and DLb, and the output terminals thereof are connected to the liquid crystal capacitors Clca and Clcb and the storage capacitors Csta and Cstb, respectively.

The liquid crystal capacitors Clca and Clcb have sub-pixel electrodes191aand191band a common electrode270as two terminals, and the liquid crystal layer3is interposed between the two terminals as a dielectric.

The storage capacitors Csta and Cstb, which assist the liquid crystal capacitors Clca and Clcb, are formed by overlapping the storage electrode line SL with the sub-pixel electrodes191aand191band interposing an insulator, and a predetermined voltage such as a common voltage Vcom is applied to the storage electrode line SL.

The voltages charged at the two liquid crystal capacitors Clca and Clcb slightly differ from each other. For example, the data voltage applied to one of the liquid crystal capacitors Clca is established to be always lower or higher than the data voltage applied to the other liquid crystal capacitor Clcb. When the voltages of the two liquid crystal capacitors Clca and Clcb are properly controlled, an image viewed from the side of the LCD maximally approximates an image viewed from the front of the LCD, thereby improving the lateral visibility of the LCD.

An LCD according to an exemplary embodiment of the present invention will be described in detail with reference toFIG. 3,FIG. 4,FIG. 5, andFIG. 6.

FIG. 3is a layout view of the “A” region ofFIG. 1.FIG. 4is a cross-sectional view of the LCD taken along line IV-IV′ ofFIG. 3.

Referring toFIG. 3andFIG. 4, an LCD according to an exemplary embodiment of the present invention includes lower and upper display panels100and200facing each other, and a liquid crystal layer3interposed between the two panels100and200.

The lower display panel100will now be described in detail.

A plurality of gate lines121and a plurality of storage electrode lines131and135are formed on an insulation substrate110.

The gate lines121transmit gate signals, and proceed roughly in the transverse direction. The gate lines121each include a plurality of first and second gate electrodes124aand124bwhich protrude upward.

The storage electrode lines include stems131extending substantially parallel to the gate lines121, and a plurality of storage electrodes135which protrude from the stems131.

The shape and disposition of the storage electrode lines131and135may be altered in various manners.

A gate insulating layer140is formed on the gate lines121and the storage electrode lines131and135, and a plurality of semiconductors154aand154bare formed on the gate insulating layer140using amorphous silicon or crystalline silicon.

A plurality of pairs of ohmic contacts163band165bare formed on the semiconductors154aand154b. The ohmic contacts163band165bmay be formed using silicide or n+ hydrogenated amorphous silicon in which n-type impurities are doped at a high concentration.

A plurality of pairs of data lines171aand171band a plurality of pairs of first and second drain electrodes175aand175bare formed on the ohmic contacts163band165band the gate insulating layer140.

The data lines171aand171btransmit data signals, and proceed roughly in the column direction such that they cross the gate lines121and the stems131of the storage electrode lines. The data lines171aand171binclude first and second source electrodes173aand173bbent toward the first and second gate electrode124aand124bin the shape of a letter “U”. The first and second source electrodes173aand173bface the first and second drain electrodes175aand175baround the first and second gate electrodes124aand124b.

The first and second drain electrodes175aand175binclude one end portion partially surrounded by the first and second source electrodes173aand173b, body portions extended upward from the end portions, and wide opposite end portions to be connected with other layers.

However, the shape and disposition of the data lines171aand171bincluding the first and second drain electrodes175aand175bmay be altered in various manners.

The first and second gate electrodes124aand124b, the first and second source electrodes173aand173b, and the first and second drain electrodes175aand175bform first and second thin film transistors (TFT) Qa and Qb together with the first and second semiconductors154aand154b, and the channels of the first and second TFTs Qa and Qb are formed at the first and second semiconductors154aand154bbetween the first and second source electrodes173aand173band the first and second drain electrodes175aand175b.

The ohmic contacts163band165bexist only between the underlying semiconductors154aand154band the overlying data lines171aand171band drain electrodes175aand175bso as to lower the contact resistance therebetween. The semiconductors154aand154bhave exposed portions not covered by the data lines171aand171band the drain electrodes175aand175b, including a portion thereof between the source electrodes173aand173band the drain electrodes175aand175b.

A lower passivation layer180pis formed on the data lines171aand171b, the drain electrodes175aand175b, and the exposed portions of the semiconductors154aand154b, using silicon nitride or silicon oxide.

A color filter230is formed through a lithography process on the lower passivation layer180p. The color filter230may be formed in a pixel area defined by the intersection of the gate line121and the data lines171aand171b, and the respective color filters230may express one of three primary colors of red, green, and blue. The left and right boundaries of the color filter230may be disposed on the data lines171aand171band extend according to the data lines171aand171b. In this case, the color filter230may have a belt shape. Color filters230of the same color may not be adjacent to each other.

The color filter230may include a structure having a photosensitive organic composition and a pigment to realize full colors. For example, the color filter230may include pigments of red, green, or blue that are included in the photosensitive organic composition.

The color filter230may have an opening G1and a groove G2. The opening G1exposes the lower passivation layer180pin the region where the first and second drain electrodes175aand175band the pixel electrode191contact each other. The groove G2is disposed between the neighboring data lines171aand171bbetween the pixel areas. In an exemplary embodiment, color filters230displaying different colors overlap each other between the neighboring data lines171aand171bbetween the pixel areas, and the groove G2is not formed.

An upper passivation layer180qmade of an organic material or an inorganic material is formed on the lower passivation layer180pand the color filter230. The upper passivation layer180qprotects the color filter230, and simultaneously flattens the underlying layers.

The lower passivation layer180pmay prevent the pigment of the color filter230from flowing into the exposed semiconductors154aand154b.

The upper passivation layer180qhas contact holes185aand185bexposing the drain electrodes175aand175b. The contact holes185aand185bare connected to and overlap the opening G1of the color filter230.

A plurality of pixel electrodes191are formed on the upper passivation layer180q. The pixel electrodes191may be formed using a transparent conductive material such as Indium Tin Oxide (ITO) and Indium Zinc Oxide (IZO). The respective pixel electrodes191include first and second sub-pixel electrodes191aand191bseparated from each other by a gap91. The second sub-pixel electrode191bincludes a pair of branches195extending along the data line171. The branches195are disposed between the first sub-pixel electrode191aand the data lines171aand171b, and are connected to the bottom of the first sub-pixel electrode191a. The first and second sub-pixel electrodes191aand191bare connected to the first and second drain electrodes175aand175bthrough the contact holes185aand185bso as to receive data voltages from the first and second drain electrodes175aand175b.

A light blocking member220is formed on the upper passivation layer180q, and a main spacer363M is formed on the pixel electrode191. The light blocking member220is formed at a portion corresponding to the boundary of the pixel area and the first and second TFTs Qa and Qb. However, the light blocking member220is not formed where the pixel electrode191and the drain electrodes175aand175bcontact each other. The main spacer363M may be formed in the contact holes185aand185b.

The main spacer363M fills the contact holes185aand185b, and extends toward the upper panel200. The main spacer363M functions to maintain the interval between the upper panel200and the lower panel100. The main spacer363M may contact the upper panel200.

The light blocking member220and the main spacer363M may be simultaneously formed, and may be made of a material such as a colored organic layer.

The thickness of the main spacer363M may be greater than a height of a cell gap, the cell gap corresponding to the interval of the liquid crystal layer3. The thickness of the main spacer363M may be greater than the height of the cell gap by more than 1 μm.

When the height of the cell gap corresponding to the interval of the liquid crystal layer3is 3.6 μm and the area of the contact holes185aand185bis 22 μm*22 μm, the thickness of the main spacer363M to maintain the height of the cell gap may be greater than 5.0 μm.

The light blocking member220may be formed with a thickness that is less than that of the main spacer363M.

The contact holes185aand185bof the upper passivation layer180qmay have a slope such that the width thereof is decreased closer to the lower side. Accordingly, the width of the main spacer363M formed in the contact holes185aand185bis decreased closer to a lower portion of the main spacer363M compared to a middle portion of the main spacer363M according to the shape of the contact holes185aand185b. On the other hand, the width of the main spacer363M formed on the upper passivation layer180qmay be decreased closer to an upper portion of the main spacer363M compared to a middle portion of the main spacer363M.

The main spacer363M according to an exemplary embodiment of the present invention is filled in the contact holes185aand185bsuch that when an external force is applied, the force is dispersed in a wide area, and thereby a smear defect may be decreased. The smear defect occurs when the elasticity of the spacer is damaged by external pressure.

The panel200will now be described in detail.

In the upper display panel200, a common electrode270is formed on the entire surface of a transparent insulation substrate210, and an alignment layer (not shown) is formed on the common electrode270.

FIG. 5is a layout view of an LCD according to an exemplary embodiment of the present invention, showing the “A” portion ofFIG. 1.FIG. 6is a cross-sectional view taken along line VI-VI′ ofFIG. 5.

The exemplary embodiment shown inFIG. 5andFIG. 6has almost the same configuration as the exemplary embodiment shown inFIG. 3andFIG. 4. However, the LCD according to the exemplary embodiment shown inFIG. 5andFIG. 6further includes an assistance spacer363S formed on the gate line121.

The assistance spacer363S may be formed along with the main spacer363M, and may be further away from the upper panel200than the main spacer363M. However, the assistance spacer363S may be closer to the upper panel200than the light blocking member220. The assistance spacer363S maintains the height of the cell gap along with the main spacer363M.

Referring toFIG. 7, contact assistants81are connected to end portions129of the gate lines121through contact holes181, respectively. The contact assistants81assist the adhesion of the end portions129of the gate lines121to external devices, and protect them. Although not shown, the end portions of the data lines171may have a similar configuration as end portions129of the gate lines121, and contact assistants may be connected to end portions of the data lines171.

Images are displayed at the display area DA of the LCD, and a light blocking member221is formed at the non-display area PA. The light blocking member221of the non-display area PA is formed on the upper passivation layer180q. InFIG. 8, the light blocking member221is formed inside the sealant310, however it may be formed under or outside the sealant310.

The storage electrode line131extends on the left and right sides of the non-display area PA of the LCD roughly in the row direction while standing on the same plane as the gate line121. The storage electrode line131includes outer storage electrodes138. The outer storage electrode138may be roughly square-shaped or rectangular-shaped.

A plurality of storage electrode line connecting members174extend on the left and right sides of the non-display area PA of the LCD roughly in the column direction while standing on the same plane as the data lines171.

Transparent connectors192electrically connect the storage electrode line connecting members174and the outer storage electrodes138with each other. Contact holes183bare formed at the contact area between the transparent connectors192and the storage electrode line connecting members174, and other contact holes183aare formed at the contact area between the transparent connectors192and the outer storage electrodes138. Alternatively, the outer storage electrodes138and the storage electrode line connecting members174may be omitted.

A gate driver400is formed on the left and right sides of the non-display area PA of the LCD and is connected to the gate lines121. The gate driver400includes data signal lines410and gate signal lines420, which are electrically connected to each other via transparent connectors192. The gate signal lines420of the gate driver400are formed on the same plane as the gate lines121, and the data signal lines410of the gate driver400are formed on the same plane as the data lines171. The contact holes183bare formed at the contact area between the transparent connectors192and the data signal lines410of the gate driver400, and the contact holes183aare formed at the contact area between the transparent connectors192and the gate signal lines420of the gate driver400. Alternatively, the gate driver400may not be formed on the lower display panel100, but may be formed on a separate IC chip, and in this case, the contact holes183aand183bthrough which the transparent connectors192contact the data signal line410or the gate signal line420of the gate driver400do not exist.

The features of the non-display area PA of an LCD according to an exemplary embodiment of the present invention, and details relevant to the display area DA thereof, will now be described

Here, the light blocking member221formed in the non-display area PA and the light blocking member220formed in the display area DA are respectively described as the first light blocking member221and the second light blocking member220.

The first light blocking member221may cover all portions where the light leakage may be generated on the insulation substrate110of the non-display area PA. The first light blocking member221may be simultaneously formed with the second light blocking member220and the main spacer363M of the display area DA. Also, the first light blocking member221may be formed using the same material as the second light blocking member220and the main spacer363M of the display area DA.

The first light blocking member221may be formed using the colored organic layer, and have an optical density of 4 to 5. The first light blocking member221may have an optical density of more than 4 to substantially prevent the light leakage. The first light blocking member221is further away from the upper panel200than the main spacer363M. Here, the first light blocking member221may be thinner than the main spacer363M by more than 1 μm.

According to an exemplary embodiment of the present invention, the main spacer363M of the display area DA is formed in the contact holes185aand185bthrough which the pixel electrode191and the drain electrodes175aand175bare contacted with each other. Thus, the thickness of the main spacer363M that is greater than 5.0 μm may be formed while maintaining a height of the cell gap of about 3.6 μm.

The main spacer363M may be disposed at the portion where the organic layer or the inorganic layer is removed such as at the contact holes185aand185b. Therefore, the coating thickness may be increased when coating the main spacer363M and the first light blocking member221of the non-display area PA, and the thickness of the first light blocking member221may also be increased.

Although the main spacer363M may be formed with a thickness of 3.6 μm, the first light blocking member221of the non-display area PA may be formed with a thickness of more than 4.0 μm such that the optical density is more than 4. Accordingly, the first light blocking member221may prevent the light leakage.

Next, a manufacturing method of an LCD according to an exemplary embodiment of the present invention will be described with reference toFIG. 7andFIG. 8.

The TFT Qb including the gate electrode124b, the source electrode173b, the drain electrode175b, and the semiconductor154bis formed on the insulation substrate110including the display area DA and the non-display area PA.

A lower passivation layer180pmade of silicon nitride or silicon oxide is formed on the TFT Qb, and a color filter230having an opening G1and a groove G2is formed through a lithography process.

An upper passivation layer180qhaving a contact hole185bexposing the drain electrode175bis formed on the lower passivation layer180pand the color filter230.

The first light blocking member221of the non-display area PA, the second light blocking member220of the display area DA, and the main spacer363M on the pixel electrode191are formed on the upper passivation layer180q. The main spacer363M maintains the interval between the upper panel200and the lower panel100.

The first light blocking member221may be simultaneously formed with the second light blocking member220and the main spacer363M of the display area DA. Here, a step of reducing the thickness of the first light blocking member221compared with the thickness of the main spacer363M may be executed by using a translucent mask.

Also, the main spacer363M may have a width that decreases closer to the upper and lower portions of the main spacer363M compared to a middle portion of the main spacer363M.

Next, the upper panel200including the common electrode270formed on the insulation substrate210and the lower panel100are combined.