Reference voltage circuit and semiconductor device

A reference voltage circuit includes a first MOS transistor pair having a first MOS transistor of an enhancement type having a gate and a drain connected to each other, and a second MOS transistor of a depletion type having a gate connected to a source of the first MOS transistor, a source connected to the drain of the first MOS transistor, and a drain connected to an output terminal; and a second MOS transistor pair having a third MOS transistor of an enhancement type having a gate and a drain connected to the output terminal and a source connected to the source of the second MOS transistor, and a fourth MOS transistor of a depletion type having a gate connected to the source of the third MOS transistor and a source connected to the output terminal. All the MOS transistors operate in a weak inversion region.

RELATED APPLICATIONS

This application claims priority to Japanese Patent Application No. 2019-021108 filed on Feb. 8, 2019, the entire content of which is incorporated herein by reference.

BACKGROUND OF E INVENTION

1. Field of the Invention

The present invention relates to a reference voltage circuit and a semiconductor device.

2. Description of the Related Art

Conventionally, a reference voltage circuit that determines an output voltage from the sum of the absolute values of the threshold voltages of an enhancement type MOS transistor and a depletion type MOS transistor has been used in a semiconductor device.

It is known that the temperature dependence of a reference voltage as the output of such a reference voltage circuit reduces because the temperature dependences of respective threshold voltages of the enhancement type MOS transistor and the depletion type MOS transistor cancel out. Also, an arbitrarily high reference voltage can be obtained by increasing the number of either the depletion type MOS transistors or the enhancement type MOS transistors (for example, see FIG. 2 to FIG. 4 in Japanese Patent Application Laid-open No. 2015-141462).

SUMMARY OF THE INVENTION

However, in the reference voltage circuit disclosed in Japanese Patent Application Laid-open No. 2015-141462, two or more constant current sources are provided to bias the enhancement type MOS transistor and the depletion type MOS transistor. Since current always flows in two or more paths, it is difficult to reduce the current consumption.

It is an object of the present invention to provide a reference voltage circuit capable of arbitrarily setting a high reference voltage while making the current consumption minute.

A reference voltage circuit according to an embodiment of the present invention includes a first MOS transistor pair, a second MOS transistor pair, and an output terminal. The first MOS transistor pair includes a first MOS transistor of a first-conductivity enhancement type having a gate and a drain connected to each other, and a second MOS transistor of a first-conductivity depletion type having a gate connected to a source of the first MOS transistor, a source connected to the drain of the first MOS transistor, and a drain connected to the output terminal. The second MOS transistor pair includes a third MOS transistor of a first-conductivity enhancement type having a gate and a drain connected to the output terminal and a source connected to the source of the second MOS transistor, and a fourth MOS transistor of a first-conductivity depletion type having a gate connected to the source of the third MOS transistor and a source connected to the output terminal. And all the MOS transistors are configured to operate in a weak inversion region.

According to a reference voltage circuit of the present invention, since current consumption is determined by the current of the first-conductivity enhancement type MOS transistor (first MOS transistor) operating in a weak inversion region, the current consumption can be easily made minute.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1is a circuit diagram for describing a reference voltage circuit according to the embodiment of the present invention.

A reference voltage circuit10according to the embodiment includes first-conductivity (N-channel here) enhancement type MOS transistors11,12, and first-conductivity depletion type MOS transistors21,22. Here, the MOS transistor11and the MOS transistor21constitute the first MOS transistor pair, and the MOS transistor12and the MOS transistor22constitute the second MOS transistor pair.

The connections of respective components of the reference voltage circuit10will be described.

In the MOS transistor11, the source is connected to a ground terminal100, and the gate and the drain are connected to the source of the MOS transistor12. The gate and the drain of the MOS transistor12are connected to an output terminal102. In the MOS transistor21, the source is connected to the source of the MOS transistor12, the gate is connected to the ground terminal100, and the drain is connected to the output terminal102. In the MOS transistor22, the source is connected to the output terminal102, the gate is connected to the source of the MOS transistor21, and the drain is connected to a power supply terminal101. The connection point between the drain of the MOS transistor11and the source of the MOS transistor21is referred to as a node N1.

The operation of the reference voltage circuit10having an above-mentioned structure will be described below.

Fall of the drain voltage of the MOS transistor11is limited by the gate-source voltage of the MOS transistor21. Rise of the source voltage of the MOS transistor21is limited by the gate-source voltage of the MOS transistor11. As a result, the voltage at the node N1stabilizes at a constant voltage in respect to the ground terminal100.

The same relationship also holds between the MOS transistor12and the MOS transistor22, and the voltage at the output terminal102as the connection point between the drain of the MOS transistor12and the source of the MOS transistor22stabilizes at a constant voltage in respect to the node N1.

Here, a threshold voltage VTEof each enhancement type MOS transistor is set larger than the absolute value of a threshold voltage VTDof each depletion type MOS transistor.

Setting of such threshold voltages causes all the MOS transistors11,12and the MOS transistors21,22to operate in a weak inversion region. As a result, the voltage at the output terminal102stabilizes at the output voltage Voutin Equation 1.
Vout=(VTE−VTD)+n·UT·C(1)

Here, n is a weak inversion slope factor, UTis a thermal voltage, and C is a constant based on the design values of the circuit structure and each MOS transistor.

Since the current consumption of the reference voltage circuit10is determined by the drain current of the MOS transistor11operating in the weak inversion region, it is possible to make the current consumption minute. As a result, since there is no need to increase the L length of the MOS transistor or provide a constant current circuit for generating a minute constant current in order to reduce the current consumption, the circuit scale can be reduced.

As can be seen from Equation 1, the first term on the right side indicates that the temperature dependences of the threshold voltage VTEand the threshold voltage VTDcancel out. The temperature dependence of the output voltage Voutcan be reduced by setting the contribution of the second term on the right side smaller than the first term, or by adjusting the temperature dependence of the second term on the right side to cancel out the temperature dependence remaining in the first term.

As described above, according to the reference voltage circuit of the embodiment, since the current consumption is determined by the current of the enhancement type MOS transistor in the weak inversion operation, the current consumption can be made minute with a small circuit scale.

Although the reference voltage circuit according to the embodiment is constructed from two pairs of MOS transistors, the first MOS transistor pair may be composed of plural pairs of MOS transistors when a higher reference voltage is needed.

FIG. 2illustrates the first modified example of the reference voltage circuit according to the embodiment. For example, the reference voltage circuit10amay be constructed from the first MOS transistor pair which is composed of an MOS transistor pair of MOS transistors11a,21aand an MOS transistor pair of MOS transistors11b,21b. Here, a node between the drain of the MOS transistor11aand the source of the MOS transistor21ais denoted by N1a, and a node between the drain of the MOS transistor11band the source of the MOS transistor21bis denoted by N1b.

The operation of the reference voltage circuit10ahaving the above-mentioned structure will be described below.

The MOS transistors11a,11band the MOS transistors21a,21boperate in the same manner as in the reference voltage circuit10ofFIG. 1, and the voltage at the node N1bis expressed by Equation 1.

The same operational relationship holds between the MOS transistor12and the MOS transistor22, and the voltage at the output terminal102as a node between the drain of the MOS transistor12and the source of the MOS transistor22stabilizes at a constant voltage in respect to the node N1b.

Similarly, the MOS transistor12and the MOS transistor22operate in the weak inversion region, and the output voltage Voutat the output terminal102stabilizes at a voltage in Equation 2.
Vout=3/2(VTE−VTD)+n·UT·C(2)

Then, the same is repeated in the above description of the operation when the number of MOS transistor pairs is increased to M pairs. In other words, the number M of pairs of MOS transistors can be adjusted to obtain arbitrarily high voltage proportional to one-half of the voltage as the sum of threshold voltages of enhancement type MOS transistors and depletion type MOS transistors. Further, since the current consumption of the reference voltage circuit10,10ais determined by the drain current of the MOS transistor11,11arespectively operating in the weak inversion region, the current consumption can be made minute.

FIG. 3is a circuit diagram for describing the second modified example of the reference voltage circuit according to the embodiment.

A reference voltage circuit10bis constructed to have a first-conductivity enhancement type MOS transistor13inserted between the MOS transistor11and the ground terminal100in addition to the structure of the reference voltage circuit10inFIG. 1. In the circuit diagram ofFIG. 3, the same components as those inFIG. 1are given the same reference numerals to omit the redundant description thereof.

In the MOS transistor13the source is connected to the ground terminal100, and the gate and the drain are connected to the source of the MOS transistor11. The gate of the MOS transistor21is connected to the source of the MOS transistor13and the ground terminal100.

The operation of the reference voltage circuit10ahaving the above-mentioned structure will be described below.

Since in the reference voltage circuit10bthe MOS transistor11and the MOS transistor13are connected in series, each gate-source voltage is small in a stable condition. In other words, the MOS transistor11and the MOS transistor13have an operating point in the weak inversion region even at a high temperature.

Since the threshold voltage of an MOS transistor generally becomes low at high temperature, the MOS transistor tends to shift from the weak inversion operation to the strong inversion operation. In contrast, since the reference voltage circuit10bhas the structure described above, the MOS transistor11and the MOS transistor13keep the operational points in the weak inversion region even at a high temperature, and hence the current consumption can continue to be small.

As described above, according to the reference voltage circuit10b, the current consumption can be made minute over a wide temperature range in addition to the effect brought from the reference voltage circuit10.

FIG. 4is a circuit diagram for describing the third modified example of the reference voltage circuit according to the embodiment.

In addition to the reference voltage circuit10, a reference voltage circuit20further includes a first-conductivity depletion type MOS transistor23and a second-conductivity (P-channel here) enhancement type MOS transistor31. The MOS transistor23and the MOS transistor31constitute an output circuit of the reference voltage circuit20. In the circuit diagram ofFIG. 4, the same components as those inFIG. 1are given the same reference numerals to omit the redundant description thereof.

In the MOS transistor23the drain is connected to the power supply terminal101, the gate is connected to a node N2, and the source is connected to the output terminal102. In the MOS transistor31the source is connected to the output terminal102, the gate is connected to the node N2, and the drain is connected to the ground terminal100.

The operation of the reference voltage circuit20having the above-mentioned structure will be described below.

The MOS transistors11,12and the MOS transistors21,22operate in the same manner as in the reference voltage circuit10, and the voltage at the node N2between the drain of the MOS transistor12and the source of the MOS transistor22is expressed by Equation 1.

Here, the absolute value of a threshold voltage VTE2of the MOS transistor31is set larger than the absolute value of a threshold voltage VTDof the MOS transistor23. At this time, the MOS transistor31and the MOS transistor23operate in the weak inversion region, and the output voltage Voutat the output terminal102stabilizes at a voltage in Equation 3.
Vout=(VTE−VTD)+n·UT·C+1/2(−VTE2−VTD)  (3)

Since the MOS transistor31operates in the weak inversion region, the current in a path between the power supply terminal101and the ground terminal100through the MOS transistor31is made minute. This makes the increase in current consumption very small due to the addition of the MOS transistor31and the MOS transistor23.

Further, the temperature dependences of the threshold voltage VTE2and the threshold voltage VTDof the third term on the right side of Equation 3 cancel out. This makes the temperature dependence of the output voltage Voutof the reference voltage circuit20small.

In the reference voltage circuit20constructed as described above, since the output impedance is determined by the design values of the MOS transistor31and the MOS transistor23, it is not affected by the number of pairs of enhancement type MOS transistors and depletion type MOS transistors. According to the reference voltage circuit20, the output impedance can be made low when the number of pairs of enhancement type MOS transistors and depletion type MOS transistors increases.

FIG. 5is a circuit diagram for describing a semiconductor device having a reference voltage circuit according to the embodiment. The semiconductor device50includes the reference voltage circuit10according to the embodiment and a main circuit40. The main circuit40receives the reference voltage which is the output voltage provided from the terminal102of the reference voltage circuit10to an input terminal104of the main circuit40. The main circuit is connected between the power supply terminal101and the ground terminal100, and provides a signal from an signal output terminal105.

In the above-mentioned description the reference voltage circuit is not limited to the reference voltage circuit10of the embodiment. Any reference voltage circuit described in the first to the third modified example of the reference voltage circuit (10a,10b,20) according to the embodiment can also be used in the semiconductor device50instead of the reference voltage circuit10.

The embodiment of the present invention is described above though, the present invention is not limited to the aforementioned embodiment, and it is needless to say that various changes can be made without departing from the gist of the present invention.

For example, two or more enhancement type MOS transistors13may be provided in the reference voltage circuit10b.