Method for forming chip package involving cutting process

Structures and formation methods of a chip package are provided. The method includes disposing a semiconductor die over a carrier substrate and forming a protection layer over the carrier substrate to surround the semiconductor die. The method also includes forming a dielectric layer over the protection layer and the semiconductor die. The method further includes cutting an upper portion of the dielectric layer to improve flatness of the dielectric layer. In addition, the method includes forming a conductive layer over the dielectric layer after cutting the upper portion of the dielectric layer.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapid growth. Continuing advances in semiconductor manufacturing processes have resulted in semiconductor devices with finer features and/or higher degrees of integration. Functional density (i.e., the number of interconnected devices per chip area) has generally increased while feature size (i.e., the smallest component that can be created using a fabrication process) has decreased. This scaling-down process generally provides benefits by increasing production efficiency and lowering associated costs.

A chip package not only provides protection for semiconductor devices from environmental contaminants, but also provides a connection interface for the semiconductor devices packaged therein. One smaller type of packaging for semiconductor devices is a chip-scale package (CSP), in which a semiconductor die is placed on a substrate.

New packaging technologies have been developed to further improve the density and functions of semiconductor dies. These relatively new types of packaging technologies for semiconductor dies face manufacturing challenges.

DETAILED DESCRIPTION

FIGS. 1A-1Nare cross-sectional views of various stages of a process for forming a chip package, in accordance with some embodiments. As shown inFIG. 1A, an adhesive layer102and a base layer104are deposited or laminated over a carrier substrate100, in accordance with some embodiments. In some embodiments, the carrier substrate100is used as a temporary support substrate. The carrier substrate100may be made of a semiconductor material, ceramic material, polymer material, metal material, another suitable material, or a combination thereof. In some embodiments, the carrier substrate100is a glass substrate. In some other embodiments, the carrier substrate100is a semiconductor substrate, such as a silicon wafer.

The adhesive layer102may be made of glue, or may be a lamination material, such as a foil. In some embodiments, the adhesive layer102is photosensitive and is easily detached from the carrier substrate100by light irradiation. For example, shining ultra-violet (UV) light or laser light on the carrier substrate100is used to detach the adhesive layer102. In some embodiments, the adhesive layer102is a light-to-heat-conversion (LTHC) coating. In some other embodiments, the adhesive layer102is heat-sensitive. The adhesive layer102may be detached using a thermal operation.

In some embodiments, the base layer104is a polymer layer or a polymer-containing layer. The base layer104may be a polybenzoxazole (PBO) layer, a polyimide (PI) layer, a solder resist (SR) layer, an Ajinomoto buildup film (ABF), a die attach film (DAF), another suitable layer, or a combination thereof. In some embodiments, the base layer104includes multiple sub-layers. In some other embodiments, the base layer104is not formed.

Afterwards, a seed layer106is deposited over the base layer104, as shown inFIG. 1Ain accordance with some embodiments. In some embodiments, the seed layer106is made of a metal material, such as copper or titanium. In some embodiments, the seed layer106is deposited using a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, a spin-on process, another applicable process, or a combination thereof. In some embodiments, the seed layer106may be made of Ti, Ti alloy, Cu, Cu alloy, another suitable material, or a combination thereof. The Ti alloy or the Cu alloy may include silver, chromium, nickel, tin, gold, tungsten, another suitable element, or a combination thereof. In some embodiments, the seed layer106includes multiple sub-layers.

Many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, the seed layer106is not formed.

As shown inFIG. 1B, a mask layer108is formed over the seed layer106, in accordance with some embodiments. The mask layer108has multiple openings110that expose portions of the seed layer106. The openings110of the mask layer108define the positions where conductive structures, such as through package vias, will be formed. In some embodiments, the mask layer108is made of a photoresist material. The openings of the mask layer108may be formed by a photolithography process. The photolithography process may include exposure and development operations.

As shown inFIG. 1C, conductive structures including conductive structures112A,112B,112C, and112D are formed in the openings110of the mask layer108, in accordance with some embodiments. In some embodiments, the conductive structures112A,112B,112C, and112D include conductive pillars. In some embodiments, each of the conductive structures112A,112B,112C, and112D has a linear sidewall. In some embodiments, the sidewalls of the conductive structures112A,112B,112C, and112D are substantially perpendicular to the surface of the seed layer106. In some embodiments, a top view of each of the conductive structures112A,112B,112C, and112D is substantially circular. In some embodiments, widths of the conductive structures112A,112B,112C, and112D are substantially the same. In some other embodiments, widths of some of the conductive structures112A,112B,112C, and112D are different from each other.

In some embodiments, the conductive structures112A,112B,112C, and112D are made of a metal material. The metal material may include Cu, Ti, Au, Co, Al, W, another suitable material, or a combination thereof. In some embodiments, the conductive structures112A,112B,112C, and112D are made of a solder material that includes Sn. In some other embodiments, the conductive structures112A,112B,112C, and112D are made of a metal material that does not include Sn.

In some embodiments, the conductive structures112A,112B,112C, and112D are formed using a plating process. The plating process may include an electroplating process, an electroless plating process, another applicable process, or a combination thereof. However, many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, the conductive structures112A,112B,112C, and112D are formed using a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a spin-on process, another applicable process, or a combination thereof.

In some embodiments, the conductive structures112A,112B,112C, and112D are substantially as high as each other. However, embodiments of the disclosure are not limited thereto. In some other embodiments, one or more of these conductive structures have a height different from that of other conductive structures. As shown inFIG. 1C, the conductive structures112A,112B,112C, and112D have heights H1, H1, H3, and H4, respectively. In some embodiments, the heights H1, H2, H3, and H4are substantially the same. In some embodiments, some of the heights H1, H2, H3,and H4are different from each other, as shown inFIG. 1C.

As shown inFIG. 1D, a cutting tool113is used to cut (mechanically trim) the upper portions of the conductive structures112A,112B,112C, and112D, in accordance with some embodiments. The upper portions of the conductive structures112A,112B,112C, and112D above an imaginary line L will be shaved off by the cutting tool113. The imaginary line L may be set at a level that allows each of the conductive structures112A,112B,112C, and112D to have a height of H5after being cut. In some embodiments, an upper portion of the mask layer108above the imaginary line L and the upper portions of the conductive structures112A,112B,112C, and112D are cut together using the cutting tool113.

As shown inFIG. 1E, after the cutting operation, the top surfaces of the conductive structures112A,112B,112C, and112D are substantially coplanar with each other, in accordance with some embodiments. Each of the conductive structures112A,112B,112C, and112D has a height of H5. In some embodiments, due to the cutting operation, the conductive structures112A,112B,112C, and112D that originally had different heights now have substantially the same height. In some embodiments, scratches may be left at the top surfaces of the conductive structures112A,112B,112C, and112D after being cut by the cutting tool113. The scratches are formed by the cutting tool113.

Even if the conductive structures112A,112B,112C, and112D do not have the same height after deposition (e.g., through plating, CVD, or other suitable forming methods), the cutting operation ensures the conductive structures112A,112B,112C, and112D to have substantially the same height. The top surfaces of the conductive structures112A,112B,112C, and112D are substantially coplanar, which facilitates subsequent processes. In some cases, the plating process for forming the conductive structures112A,112B,112C, and112D may not be required to be performed in a very well controlled manner. In some embodiments, the plating process is performed at a relatively high speed. Accordingly, the cutting (mechanical trimming) operation enables the use of less expensive plating solution during fabrication process. Therefore, the process cost and time are significantly reduced.

As shown inFIG. 1F, the mask layer108is removed, in accordance with some embodiments. Afterwards, the exposed portion of the seed layer106(not covered by the conductive structures including112A,112B,112C, and112D) are removed, as shown inFIG. 1Fin accordance with some embodiments. An etching process may be used to partially remove the seed layer106. The conductive structures including112A,112B,112C, and112D may function as an etching mask during the etching of the seed layer106.

As shown inFIG. 1G, semiconductor dies including semiconductor dies122A and122B are attached on the base layer104, in accordance with some embodiments. In some embodiments, the back sides of the semiconductor dies122A and122B face the base layer104with the front sides of the semiconductor dies122A and122B facing upwards. An adhesive film120may be used to fix the semiconductor dies122A and122B on the base layer104. The adhesive film120may include a die attach film (DAF), a glue, or another suitable film.

Each of the semiconductor dies122A and122B may include a semiconductor substrate114, a dielectric layer116, and conductive pads118at the front side of the semiconductor die. In some embodiments, various device elements are formed in the semiconductor substrate114. Examples of the various device elements include transistors (e.g., metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high voltage transistors, high-frequency transistors, p-channel and/or n-channel field effect transistors (PFETs/NFETs), etc.), diodes, or other suitable elements.

The device elements are interconnected to form integrated circuit devices through conductive features formed in the dielectric layer116. The dielectric layer116may include multiple sub-layers. The conductive features may include multiple conductive lines, conductive contacts, and conductive vias. The integrated circuit devices include logic devices, memory devices (e.g., static random access memories, SRAMs), radio frequency (RF) devices, input/output (I/O) devices, system-on-chip (SoC) devices, other applicable types of devices, or a combination thereof. In some embodiments, the semiconductor die122A or122B is a system-on-chip (SoC) chip that includes multiple functions.

The conductive pads118may be wider portions of some of the conductive lines formed on the dielectric layer116or embedded in the dielectric layer116. Therefore, the device elements in the semiconductor substrate114may be electrically connected to other elements through the conductive pads118and other conductive features.

As shown inFIG. 1G, the seed layer106and each of the conductive structures112A,112B,112C, and112D together have a total height H6. The adhesive film120and each of the semiconductor dies122A and122B together have a total height H7. In some embodiments, the heights H6and H7are substantially the same.

However, many variations and/or modifications can be made to embodiments of the disclosure. In some embodiments, the heights H6and H7are different from each other. In some embodiments, the height H6is greater than the height H7. In some embodiments, the height difference between one of the conductive structures112A,112B,112C, and112D and one of the semiconductor dies122A and122B is substantially equal to the difference between H6and H7. In some embodiments, the height difference is in a range from about 2 μm to about 3 μm.

As shown inFIG. 1H, a protection layer124is formed over the carrier substrate100to surround the conductive structures112A,112B,112C, and112D and the semiconductor dies122A and122B, in accordance with some embodiments. In some embodiments, the protection layer124covers sidewalls of the conductive structures112A,112B,112C, and112D and the semiconductor dies122A and122B.

In some embodiments, the protection layer124exposes (or does not cover) the top surfaces of the conductive structures112A,112B,112C, and112D and the semiconductor dies122A and122B. In some embodiments, the conductive structures112A,112B,112C, and112D penetrate through the protection layer124. The conductive structures112A,112B,112C, and112D are used as through package vias (TPVs) or through integrated fan-out vias (TIVs). In some embodiments, the protection layer124includes a polymer material. In some embodiments, the protection layer124includes a molding compound material. The molding compound material may include an epoxy-based resin with fillers dispersed therein.

In some embodiments, the protection layer124is formed by injecting a molding compound material over the carrier substrate100. In some embodiments, after or during the injecting of the molding compound material, the molding compound material does not cover the top surfaces of the conductive structures112A,112B,112C, and112D and/or the semiconductor dies122A and122B.

In some embodiments, a liquid molding compound material is disposed over the carrier substrate100to encapsulate the conductive structures112A,112B,112C, and112D and the semiconductor dies122A and122B. In some embodiments, a thermal process is then applied to harden the liquid molding compound material and to transform it into the protection layer124. In some embodiments, the thermal process is performed at a temperature in a range from about 200 degrees C. to about 230 degrees C. The operation time of the thermal process may be in a range from about 0.5 hour to about 3 hours.

In some embodiments, a mold is used to assist in the formation of the protection layer124.FIGS. 2A-1 to 2C-1are cross-sectional views of various stages of a process for forming the protection layer124of a chip package, in accordance with some embodiments.FIGS. 2A-2 to 2C-2are top views of various stages of a process for forming the protection layer124a chip package, in accordance with some embodiments.

As shown inFIG. 2A-1, a mold200is disposed over the carrier substrate100, in accordance with some embodiments. In some embodiments, a space230is formed between the mold200and the carrier substrate100, as shown inFIG. 2A-1. In some embodiments, the mold200includes a sealing element201. The sealing element201may be used to cover the peripheral region of the carrier substrate100. In some embodiments, the sealing element201is a sealing ring. The sealing element201may also be used as a settle element that affixes the carrier substrate100under the mold200.

However, many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, the sealing element201is not formed.

In some embodiments, the mold200includes a release film202. The space230is surrounded by the carrier substrate100, the sealing element201, and the release film202. In some embodiments, the release film202is made of a material that has a poor adhesion with a molding compound material used for forming the protection layer124. In some embodiments, the release film202is in direct contact with the conductive structures112A,112B,112C, and112D after the mold200is disposed over the carrier substrate100. In some embodiments, the release film202is also in direct contact with the semiconductor dies122A and122B.

However, many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, the release film202is not formed.

In some embodiments, the mold has one or more openings206. Each of the openings206may be used to allow a flow of a molding compound material204to be injected into the mold200. In some embodiments, one or some of the openings206are used to allow the flow of the molding compound material204to be led out of the mold200. In some embodiments, each of the openings206is used for letting the flow of the molding compound material204enter the mold200. In some other embodiments, the mold200has only one opening206that allow the flow of the molding compound material204to enter the space230.

There are a number of semiconductor dies122disposed over the carrier substrate100, as shown inFIG. 2A-2in accordance with some embodiments. As shown inFIGS. 2A-1 and 2A-2, there is no molding compound material injected over the carrier substrate100at this stage, in accordance with some embodiments.

Afterwards, the molding compound material204is injected into the space230between the mold200and the carrier substrate100, as shown inFIGS. 2B-1 and 2B-2, in accordance with some embodiments. Some of the conductive structures including the conductive structures112A and112D are surrounded by the molding compound material204, as shown inFIG. 2B-1in accordance with some embodiments. Some of the semiconductor dies122including the semiconductor dies122A and122B are partially or completely surrounded by the molding compound material204, as shown inFIGS. 2B-1 and 2B-2in accordance with some embodiments. In some embodiments, the release film202is in direct contact with the conductive structures112A,112B,112C, and112D during the injecting of the molding compound material204. In some embodiments, the release film202is also in direct contact with the semiconductor dies122including the semiconductor dies122A and122B during the injecting of the molding compound material204.

Afterwards, the injected molding compound material204completely fills the space230between the mold200and the carrier substrate100, as shown inFIGS. 2C-1 and 2C-2, in accordance with some embodiments. In some embodiments, the mold200is removed, and the molding compound material204is cured to become the protection layer124, as shown inFIG. 1H. In some embodiments, the molding compound material204is cured after the removal of the mold200. In some other embodiments, the molding compound material204is cured before the removal of the mold200. In some other embodiments, a thermal operation is performed before the removal of the mold200. Afterwards, another thermal operation is used to complete the curing of the molding compound material204. As a result, the protection layer124is formed.

In some embodiments, during the injecting of the molding compound material204for forming the protection layer124, the molding compound material204does not cover the top surfaces of the conducting structures112A,112B,112C, and112D and/or the semiconductor dies122A and122B due to the mold200. As a result, the top surfaces of the conducting structures112A,112B,112C, and112D and the semiconductor dies122A and122B are not covered by the protection layer124, as shown inFIG. 1H. In some embodiments, it is not necessary for the protection layer124to be thinned since the conductive structures112A,112B,112C, and112D and the conductive pads118of the semiconductor dies122A and122B have been exposed without being covered by the protection layer124.

In some other cases, the mold200is not used. In these cases, the conductive structures and the semiconductor dies are covered by the molding compound material. Afterwards, a thinning process may need to be performed to thin down the protection layer so as to expose the conductive structures and the semiconductor dies. An additional passivation layer (such as a PBO layer) and conductive pillars that can sustain the thinning process may need to have been formed previously over each of the semiconductor dies to ensure conductive routes to the semiconductor dies. Fabrication cost and process time are therefore high.

In some embodiments where the mold200is used, since no thinning process to the protection layer124is required, fabrication cost and process time are reduced. Damage due to the thinning process may also be prevented. In some embodiments, no additional passivation layer or conductive pillars needs to be formed on the semiconductor dies, and so the fabrication cost and process time are reduced further.

In some embodiments, the adhesion between the molding compound material204and the release film202is poor. Therefore, the molding compound material204may be prevented from adhering on the mold during the subsequent removal of the mold200. After the removal of the mold200, recesses may be formed at the surface of the molding compound material204. As a result, there are also some recesses126formed at the surface of the protection layer124after the molding compound material204is cured to form the protection layer124.

As shown inFIG. 1H, the protection layer124has recesses126, in accordance with some embodiments. Some of the recesses126are between the semiconductor die122A or122B and one of the conductive structures112A,112B,112C, and112D. Some of the recesses126are between two of the conductive structures, such as between the conductive structures112B and112C. As shown inFIG. 1H, one of the recesses126has a depth D. In some embodiments, the depth D is in a range from about 3 μm to about 10 μm. For example, the depth D may be about 7 μm.

Afterwards, an interconnection structure including multiple dielectric layers and multiple conductive layers is formed over the structure shown inFIG. 1H. As shown inFIG. 1I, a dielectric layer128ais formed over the protection layer124, the conductive structures112A-112D, and the semiconductor dies122A and122B. In some embodiments, the dielectric layer128ais made of one or more polymer materials. The dielectric layer128amay be made of polybenzoxazole (PBO), polyimide (PI), another suitable material, or a combination thereof. In some embodiments, the dielectric layer128ais formed using a spin coating process, a spray coating process, another applicable process, or a combination thereof.

As shown inFIG. 1I, the top surface of the dielectric layer128amay have a surface morphology similar to that below the dielectric layer128a. The dielectric layer128amay also have recesses at positions that correspond to the recesses126formed at the surface of the protection layer124. As shown inFIG. 1I, the dielectric layer128amay have an uneven top surface.

As shown inFIG. 1I, a cutting tool199is provided and will be used to mechanically trim off an upper portion of the dielectric layer128ato improve the flatness of the dielectric layer128a, in accordance with some embodiments. For example, an upper portion of the dielectric layer128aabove an imaginary line L′ will be cut.

As shown inFIG. 1J, after the dielectric layer128ais partially cut, the remaining portion of the dielectric layer128ahas a substantially planarized top surface. The dielectric layer128awith the substantially planarized top surface may facilitate subsequent processes such as a patterning process and a deposition process.

In some embodiments, the surface of the dielectric layer128ais not perfectly planarized. In some embodiments, there are one or more cutting scratches formed on the surface of the dielectric layer128a. The cutting scratches may be formed by the partial cutting of the upper portion of the dielectric layer128a.

FIG. 3Ais a top view of one of various stages of a process for forming a chip package, in accordance with some embodiments. In some embodiments,FIG. 3Ais a top view of the structure shown inFIG. 1J. As shown inFIG. 3A, a number of cutting scratches302are formed on the surface of the dielectric layer128aafter being cut by the cutting tool199. In some embodiments, the structure shown inFIG. 1Iis rotated while being cut by the cutting tool199. As a result, each of the cutting scratches302has a curved track. In some embodiments, the structure shown inFIG. 1Iis moved towards the cutting tool199step by step. For example, after a portion of the dielectric layer128ais cut by the cutting tool199for a predetermined period of time, the structure shown inFIG. 1Iis moved towards the cutting tool199so that another portion of the dielectric layer128ais cut. In some embodiments, the intervals between the cutting scratches302are substantially the same because the distances between each step while the structure shown inFIG. 1Iis moving towards the cutting tool199are substantially the same.

As shown inFIG. 1K, the dielectric layer128ais patterned to form multiple openings129, in accordance with some embodiments. In some embodiments, one of the openings129exposes the conductive structure112A. In some embodiments, one of the openings129exposes conductive features (such as the conductive pads118) of the semiconductor die122A. In some embodiments, the openings129are formed using a photolithography process, a laser drilling process, another applicable process, or a combination thereof. Although the top surface of the dielectric layer128ais formed with some cutting scratches302, the top surface of the dielectric layer128ais still substantially planar, which may facilitate subsequent patterning processes and/or deposition processes. Therefore, the patterning process for forming the openings129becomes easier.

In the embodiments illustrated inFIGS. 1I-1K, the dielectric layer128ais patterned to form the openings129after the upper portion of the dielectric layer128ais cut for planarization. However, many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, the dielectric layer128ais patterned to form the openings129before the upper portion of the dielectric layer128ais cut for planarization.

FIG. 4is a cross-sectional view of one of various stages of a process for forming a chip package, in accordance with some embodiments. In some embodiments, before being planarized, the dielectric layer128ais patterned to form openings129′. Some of the openings129′ expose the conductive structures112A-112D, and some of the openings129′ expose the conductive features (such as the conductive pads118) of the semiconductor dies122A and122B. Afterwards, the cutting tool199is used to partially remove the dielectric layer, as shown inFIG. 4in accordance with some embodiments. As a result, a structure similar to that shown inFIG. 1Kis formed.

Afterwards, conductive layers130aare formed over the dielectric layer128a, as shown inFIG. 1Lin accordance with some embodiments. In some embodiments, the conductive layer128afills the opening129. In some embodiments, one of the conductive layers130ais electrically connected to the conductive structure112A through one of the openings129. In some embodiments, one of the conductive layers130ais electrically connected to the conductive feature (such as the conductive pad118) of the semiconductor die122A through one of the openings129. In some embodiments, the conductive structure112A is electrically connected to the conductive pad118of the semiconductor die122A through one of the conductive layers130a.

FIG. 3Bis a cross-sectional view of one of various stages of a process for forming a chip package, in accordance with some embodiments. In some embodiments,FIG. 3Bis an enlarged view near an interface between one of the conductive layers130aand the dielectric layer128a. As shown inFIG. 3B, there are a number of cutting scratches302formed on the surface of the dielectric layer128a. In some embodiments, the conductive layers130afill some of the cutting scratches (or scoring marks)302, as shown inFIG. 3B. In some embodiments, the interface between the conductive layers130aand the dielectric layer128ahas an undulate morphology.

In some embodiments, each of the cutting scratches302has a width W1or W2that is in a range from about 20 μm to about 60 μm. In some embodiments, the widths W1and W2are substantially the same. In some embodiments, each of the cutting scratches309has a depth h that is in a range from about 0.05 μm to about 0.1 μm.

As shown inFIG. 1M, a dielectric layer128bis formed over the dielectric layer128aand the conductive layers130a, in accordance with some embodiments. In some embodiments, the material and formation method of the dielectric layer128bis the same as or similar to those of the dielectric layer128a. However, embodiments of the disclosure are not limited thereto. In some other embodiments, the dielectric layer128bis made of a dielectric material different from that of the dielectric layer128a. In some embodiments, the dielectric layer128bis made of silicon oxide or the like using a deposition process, such as a chemical vapor deposition (CVD) process.

FIG. 3Cis a cross-sectional view of one of various stages of a process for forming a chip package, in accordance with some embodiments. In some embodiments,FIG. 3Cis an enlarged view near an interface between the dielectric layer128band the dielectric layer128a. In some embodiments, the dielectric layer128bfills some of the cutting scratches302, as shown inFIG. 3C. In some embodiments, the interface between the dielectric layer128band the dielectric layer128ahas an undulate morphology.

Afterwards, multiple dielectric layers including a dielectric layer128cand a passivation layer132and multiple conductive layers including conductive layers130band130care formed, as shown inFIG. 1Min accordance with some embodiments. In some embodiments, conductive bumps134are formed. An under bump metallurgy (UBM) layer (not shown) may be formed between the conductive bumps134and the conductive layers130c. Because the dielectric layer128ais cut previously to have a substantially planar top surface, the subsequent formation of elements over the dielectric layer128amay become easier.

Afterwards, the structure shown inFIG. 1Mis placed upside down on a support element, in accordance with some embodiments. Then, the carrier substrate100and adhesive layer102are removed. Afterwards, a dicing process is performed to separate the structure as shown inFIG. 1Minto multiple chip packages, as shown inFIG. 1Nin accordance with some embodiments. As a result, a chip package with a fan-out structure is formed.

In some embodiments, one or more elements are stacked on or bonded onto the structure as shown inFIG. 1Nbefore the dicing process. As shown inFIG. 1N, another element136is stacked over the structure shown inFIG. 1N, in accordance with some embodiments. The element136may include a chip package, a semiconductor die, one or more passive devices, another suitable structure, or a combination thereof.

In some embodiments, conductive connectors138are formed between the element136and the conductive structures such as the conductive structures112A and112B. Electrical connections between the element136and the semiconductor die122A may therefore be established. In some embodiments, the base layer104is patterned to form openings that expose the seed layer106connecting the conductive structures112A and112B. The conductive connectors138may be formed in the openings and electrically connected to other conductive features of the element136. In some embodiments, the conductive connectors include solder bumps, solder balls, conductive pillars, conductive pillars that contain no tin, another suitable structure, or a combination thereof.

Many variations and/or modifications can be made to embodiments of the disclosure. In some embodiments, the element136is stacked before the dicing process. In some other embodiments, the element136is stacked after the dicing process.

Embodiments of the disclosure form a chip package having a semiconductor die and multiple conductive structures. The conductive structures penetrate through a protection layer (or a molding compound layer) that surrounds the semiconductor die and the conductive structures. A mold is used to assist in the formation of the protection layer. The protection layer may not need to be thinned to expose the conductive structures and/or conductive pads of the semiconductor die. Fabrication cost and process time are significantly reduced. Damage due to the thinning process may also be prevented. Interconnection structure is formed over the protection layer and the semiconductor die for electrical connection. A cutting process is used to provide a dielectric layer of the interconnection structure on the protection layer and the semiconductor die with a substantially planar top surface, which facilitates subsequent formation of other elements including other dielectric layers and other conductive layers. The quality and reliability of the chip package are significantly improved.

In accordance with some embodiments, a method for forming a chip package is provided. The method includes disposing a semiconductor die over a carrier substrate and forming a protection layer over the carrier substrate to surround the semiconductor die. The method also includes forming a dielectric layer over the protection layer and the semiconductor die. The method further includes cutting an upper portion of the dielectric layer to improve flatness of the dielectric layer. In addition, the method includes forming a conductive layer over the dielectric layer after cutting the upper portion of the dielectric layer.

In accordance with some embodiments, a method for forming a chip package is provided. The method includes forming a molding compound layer to surround a semiconductor die and forming a dielectric layer over the molding compound layer and the semiconductor die. The method also includes partially cutting the dielectric layer such that the dielectric layer is substantially planarized. The method further includes forming a conductive layer over the dielectric layer after the dielectric layer is substantially planarized.

In accordance with some embodiments, a chip package is provided. The chip package includes a semiconductor die and a protection layer surrounding the semiconductor die. The chip package also includes a dielectric layer over the semiconductor die and the protection layer, and the dielectric layer has an upper surface with cutting scratches. The chip package further includes a conductive layer over the dielectric layer and filling some of the cutting scratches.