VERTICALLY AND HORIZONTALLY STACKED DEVICE STRUCTURES

A field effect device is provided. The field effect device includes a stack of nano-channels on a substrate, wherein each of the nano channels has a first height, a first width, and a first length, and a vertical nanosheet perpendicular to a major plane of the substrate on opposite sides of the stack of nano-channels, wherein each of the vertical nanosheets has a second height, a second width, and a second length, wherein the second height of the vertical nanosheets is greater than the first width of the nano-channels. The field effect device further includes a gate dielectric layer wrapped around at least a portion of each of the nano-channels and the vertical nanosheets, and a conductive gate fill on the gate dielectric layer.

BACKGROUND

The present invention generally relates to stacked gate-all-around (GAA) device structures, and more particularly to vertically and horizontally stacked nanosheet (NS) GAA device structures.

A Field Effect Transistor (FET) typically has a source, a channel, and a drain, where current flows from the source to the drain, and a gate that controls the flow of current through the device channel. Field Effect Transistors (FETs) can have a variety of different structures, for example, FETs have been fabricated with the source, channel, and drain formed in the substrate material itself, where the current flows horizontally (i.e., in the plane of the substrate), and FinFETs have been formed with the channel extending outward from the substrate, but where the current also flows from a source to a drain. Depending on the doping of the source and drain, an n-FET or a p-FET can be formed. Two FETs also can be coupled to form a complementary metal oxide semiconductor (CMOS) device, where a p-channel MOSFET and n-channel MOSFET are coupled together.

SUMMARY

In accordance with an embodiment of the present invention, a field effect device is provided. The field effect device includes a stack of nano-channels on a substrate, wherein each of the nano channels has a first height, a first width, and a first length, and a vertical nanosheet perpendicular to a major plane of the substrate on opposite sides of the stack of nano-channels, wherein each of the vertical nanosheets has a second height, a second width, and a second length, wherein the second height of the vertical nanosheets is greater than the first width of the nano-channels. The field effect device further includes a gate dielectric layer wrapped around at least a portion of each of the nano-channels and the vertical nanosheets, and a conductive gate fill on the gate dielectric layer.

In accordance with another embodiment of the present invention, a complimentary field effect device is provided. The complimentary field effect device includes a first stack of first nano-channels on a substrate, wherein each of the first nano-channels has a first height, a first width, and a first length, and a first vertical nanosheet perpendicular to a major plane of the substrate on opposite sides of the first stack of nano-channels, wherein each of the vertical nanosheets has a second height, a second width, and a second length, wherein the second height of the vertical nanosheets is greater than the first width of the nano-channels. The complimentary field effect device further includes a first gate dielectric layer wrapped around at least a portion of each of the first nano-channels and the first vertical nanosheets, and a first conductive gate fill on the first gate dielectric layer. The complimentary field effect device further includes a second stack of second nano-channels on the substrate, wherein each of the second nano channels has a third height, a third width, and a third length, and a second vertical nanosheet perpendicular to a major plane of the substrate on opposite sides of the second stack of nano-channels, wherein each of the second vertical nanosheets has a fourth height, a fourth width, and a fourth length, wherein the third width of the second nano-channels is greater than the fourth height of the second vertical nanosheets. The complimentary field effect device further includes a second gate dielectric layer wrapped around at least a portion of each of the second nano-channels and the second vertical nanosheets, and a second conductive gate fill on the second gate dielectric layer.

In accordance with yet another embodiment of the present invention, a method of forming a field effect device is provided. The method includes forming one or more stacks of alternating nano-channels and sacrificial sections on a substrate, and epitaxially growing a sacrificial structure on the alternating nano-channels and sacrificial sections, wherein the sacrificial structure is the same material as the sacrificial sections. The method further includes epitaxially growing a vertical nanosheet on each side of the sacrificial structure; and removing the sacrificial structure to leave a stack of nano-channels on the substrate and a vertical nanosheet on opposite sides of the stack of nano-channels.

DETAILED DESCRIPTION

Embodiments of the present invention relate to a vertically and horizontally stacked gate-all-around (GAA) nanosheet (NS) device including a vertical nanosheet and a channel stack with perpendicular current flow. The current flow in the device(s) can be horizontal (parallel to the major plane of the substrate) from a source to a drain.

In various embodiments, the vertical nanosheets can have a vertical {110} plane that is parallel to the flow of current within the channel, where the channel can be aligned perpendicularly to the substrate. In various embodiments, a channel with a {001} plane and a substrate with a {001} plane can be used to form an n-type field effect transistor (nFET) device. In various embodiments, a channel with a {110} plane and a substrate with a {001} plane can be used to form an p-type field effect transistor (pFET) device. An Si{110} plane can be used for a pFET device, since hole mobility is high on that plane, and an Si{100} plane can be used for an nFET device since electron mobility is high on that plane.

Exemplary applications/uses to which the present invention can be applied include, but are not limited to: high performance logic devices (e.g., NAND gates, NOR gates, etc.).

Referring now to the drawings in which like numerals represent the same or similar elements and initially toFIG.1,FIG.1illustrates perpendicular cross-sectional side views showing a stack of alternating nanosheet channel layers and sacrificial layers on a bottom sacrificial layer and a substrate, in accordance with an embodiment of the present invention.

In one or more embodiments, a bottom sacrificial layer120can be formed on a substrate, where the bottom sacrificial layer120can be formed by an epitaxial growth process on the top surface of the substrate. In various embodiments, the bottom sacrificial layer120can be a semiconductor layer grown on the top surface of the substrate110, where the bottom sacrificial layer120can be, for example, silicon-germanium (SiGe) with a germanium concentration in a range of about 15 atomic percent (at.%) to about 75 at.%, or about 60 at.%.

In various embodiments, the substrate110can be a semiconductor substrate, where the substrate110can be a type IV semiconductor, for example, silicon (Si) or germanium (Ge), or a type IV-IV compound semiconductor, for example, silicon-germanium (SiGe) or silicon carbide (SiC), a type III-V compound semiconductor, for example, gallium arsenide (GaAs), gallium nitride (GaN), or indium phosphide (InP). The substrate material can be a single crystal semiconductor suitable for epitaxial growth of the bottom sacrificial layer120and stack of alternating nanosheet channel layers130and sacrificial layers140on the substrate110and bottom sacrificial layers120.

In one or more embodiments, the nanosheet channel layers130can be, for example, silicon (Si) nanosheet layers formed on the bottom sacrificial layer120and substrate110by epitaxial growth. In various embodiments, the nanosheet channel layers130can be nanowires or nanoellipses (referred to collectively as nano-channels); however, nanosheet is used for consistency to refer to each of the nano-forms.

In various embodiment the nanosheet channel layers130can have a thickness in a range of about 3 nanometers (nm) to about 15 nm, or about 4 nm to about 9 nm, although other thicknesses are also contemplated.

In one or more embodiments, the sacrificial layers140can be, for example, silicon-germanium (SiGe) nanosheet layers formed on the nanosheet channel layers130by epitaxial growth to form the alternating stack of nanosheet channel layers130and sacrificial layers140.

In various embodiments, the sacrificial layers140can have a thickness in a range of about 6 nanometers (nm) to about 20 nm, or about 8 nm to about 15 nm, although other thicknesses are also contemplated.

In various embodiments, the sacrificial layers140can be silicon-germanium (SiGe) with about a germanium concentration of about 15 atomic percent (at.%) to about 35 atomic percent (at.%), or about 25 atomic percent (at.%).

In one or more embodiments, a stack template layer150can be formed on the top most layer, where the stack template layer150can be formed by a blanket deposition, for example, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), physical vapor deposition (PVD), and combinations thereof.

In various embodiments, the stack template layer150can be a dielectric hardmask material, including, but not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon boronitride (SiBN), titanium nitride (TiN), and combinations thereof. The stack template layer150can be patterned by lithography and etching.

FIG.2illustrates perpendicular cross-sectional side views showing a plurality of stack templates formed on alternating nanosheet channel sections and sacrificial sections on a bottom sacrificial section and the substrate, in accordance with an embodiment of the present invention.

In one or more embodiments, the stack template layer150can be patterned by lithographic processes and etching to form one or more stack templates152on the stack of alternating nanosheet channel layers130and sacrificial layers140.

In one or more embodiments, portions of the nanosheet channel layers130and sacrificial layers140can be removed, for example, by selective directional etching (e.g., reactive ion etching (RIE)) to form one or more stacks of alternating nanosheet channel sections132and sacrificial sections142on a bottom sacrificial section122. In various embodiments, a portion of the substrate110beneath the bottom sacrificial layer120can also be removed.

In various embodiments, the nanosheet channel sections132, sacrificial sections142, and bottom sacrificial section122can each have a width in a range of about 5 nm to about 100 nm, or about 10 nm to about 50 nm, or about 15 nm to about 30 nm, although other widths are also contemplated. In various embodiments, a nanowire channel section can have a width in a range of about 5 nm to about 10 nm, or about 7 nm, although other widths are also contemplated. nanosheets and nanowires can be referred to as nano-channels.

FIG.3illustrates perpendicular cross-sectional side views showing formation of a fill layer, lateral epitaxial growth of sacrificial material to form a sacrificial structure, and lateral epitaxial growth of a vertical nanosheet on the sacrificial structure, in accordance with an embodiment of the present invention.

In one or more embodiments, a fill layer160can be formed on the substrate110, where the fill layer160can fill in the space between each adjacent pair of the stack of nanosheet channel sections132and sacrificial sections142on the bottom sacrificial section122. The fill layer160can cover the sidewalls of the bottom sacrificial section122, where the top surface of the fill layer160can be approximately (i.e., within the tolerances of the processes used) coplanar with the interface between the top surface of the bottom sacrificial section122and the bottom surface of the bottom most nanosheet channel section132. In various embodiments, the top surface of the fill layer160can be at or below the top surface of the bottom sacrificial section122.

In one or more embodiments, a sacrificial structure145can be formed on the alternating nanosheet channel sections132and sacrificial sections142, where the sacrificial structure145can be formed by epitaxially growing a sacrificial material on the exposed sidewall surfaces of the nanosheet channel sections132and sacrificial sections142. In various embodiments, the sacrificial structure145can be the same material as the sacrificial sections142, so the sacrificial structure145can be removed with a single selective etch. In various embodiments, the sacrificial structure145can be, for example, a layer of silicon-germanium (SiGe) having about the same germanium concentration as the sacrificial sections142, so the sacrificial structure145can be removed with a single selective etch. In various embodiments, the sacrificial structure145can have a cross-sectional H-shape or ladder-like shape with the sacrificial sections142forming the rungs and the epitaxially grown portion forming the legs.

In one or more embodiments, a vertical nanosheet170can be formed on each side of the sacrificial structure145, where the vertical nanosheet170can be formed by lateral epitaxial growth from the exposed sidewalls of the sacrificial structure(s)145. In various embodiments, the vertical nanosheets170can be, for example, a layer of silicon (Si) grown on the sacrificial structures145, where the vertical nanosheets170and nanosheet channel sections132can remain after selectively removing the sacrificial structure(s)145. A gap can be between facing sidewalls of the adjacent vertical nanosheets170.

In various embodiments, the vertical nanosheet170can have a crystal structure from the epitaxial growth such that the vertical nanosheet(s)170have a {110} crystal plane vertically along the long axis of the vertical nanosheet170when the substrate110is a Si(001) substrate, where the {110} crystal plane can be parallel to the flow of current.

FIG.4illustrates perpendicular cross-sectional side views showing removal of the stack template from the sacrificial structure, in accordance with an embodiment of the present invention.

In one or more embodiments, the one or more stack templates152can be removed, where the one or more stack templates152can be removed using a selective etch. Removal of the one or more stack templates152can expose a top surface of a top most nanosheet channel section132.

FIG.5illustrates perpendicular cross-sectional side views showing a dummy gate fill and dummy gate cap formed on the sacrificial structures and vertical nanosheets, and formation of dummy gate sidewalls on the dummy gate fill and dummy gate cap, in accordance with an embodiment of the present invention.

In one or more embodiments, a dummy gate structure can be formed on the sacrificial structure(s)145, vertical nanosheets170, and stack of nanosheet channel sections132, where the dummy gate structure can include a dummy gate fill180and dummy gate cap190. The dummy gate fill180can be formed on the sacrificial structure(s)145, vertical nanosheets170, and stack of nanosheet channel sections132by a blanket deposition (e.g., CVD, PECVD, PVD). The dummy gate cap190can be formed on the dummy gate fill180and used to pattern the dummy gate fill180to form the dummy gate structures. The dummy gate fill180can fill in the gaps between the vertical nanosheets170and extend over the stack of nanosheet channel sections132. The dummy gate fill180can be a selectively removable material, including, but not limited to, amorphous silicon (a-Si), amorphous germanium (a-Ge), amorphous carbon (a-C), and combinations thereof.

In one or more embodiments, dummy gate sidewalls200can be formed on the dummy gate fill180and dummy gate cap190, where the dummy gate sidewalls200can be formed by depositing a gate sidewall layer and removing portions of the sidewall layer from horizontal surfaces using a selective, directional etch.

In various embodiments, the gate sidewall layer and dummy gate sidewalls200can be an electrically insulating dielectric material, including, but not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON) silicon oxy carbide (SiOC), silicon oxy carbonitride (SiOCN), silicon boro carbonitride (SiBCN), and combinations thereof.

FIG.6illustrates perpendicular cross-sectional side views showing removal of portions of the sacrificial structure, vertical nanosheets, and nanosheet channel sections, in accordance with an embodiment of the present invention.

In one or more embodiments, portions of the sacrificial structure145, vertical nanosheets170, and nanosheet channel sections132extending laterally out beyond the dummy gate sidewalls200can be removed using one or more selective directional etching (e.g., RIE), where etching can stop at the top surface of the fill layer160. Trimming back the nanosheet channel sections132, sacrificial sections145, and bottom sacrificial section122can determine the length of the nanosheet channel sections132beneath the dummy gate structure and dummy gate sidewalls200.

FIG.7illustrates perpendicular cross-sectional side views showing recessing of the sacrificial structure between the nanosheet channel sections, in accordance with an embodiment of the present invention.

In one or more embodiments, the sacrificial structure(s)145and the bottom sacrificial section(s)122can be recessed to form inner spacer cavities between the nanosheet channel sections132, where the sacrificial structure145and the bottom sacrificial section122can be recessed using a selective isotropic etch, for example, a wet chemical etch or dry plasma etch. In various embodiments, the recessed sacrificial structure145and the bottom sacrificial section122can have approximately the same width as the dummy gate fill180and dummy gate cap190.

FIG.8illustrates perpendicular cross-sectional side views showing formation of an inner spacer layer on the recessed sacrificial structures and nanosheet channel sections, in accordance with an embodiment of the present invention.

In one or more embodiments, an inner spacer layer210can be formed on the recessed sacrificial structures145, bottom sacrificial section122, and nanosheet channel sections132, where the inner spacer layer210can be formed by a conformal deposition (e.g., ALD, PEALD). Portions of the inner spacer layer210can be removed using a selective isotropic etch (e.g., Plasma etch). The inner spacer layer210can cover portions of the vertical nanosheets170and nanosheet channel sections132, where the inner spacer layer210is sufficiently thick to fill in the inner spacer cavities.

FIG.9illustrates perpendicular cross-sectional side views showing removal of portions of the inner spacer layer to form inner spacers on the recessed sacrificial structures and nanosheet channel sections, in accordance with an embodiment of the present invention.

In one or more embodiments, the portions of the inner spacer layer210extending outside of the inner spacer cavities can be removed to for inner spacers215between the nanosheet channel sections132and vertical nanosheets170, where the portions of the inner spacer layer210can be removed using a selective directional etch and/or a selective isotropic etch.

FIG.10illustrates perpendicular cross-sectional side views showing formation of source/drains on opposite sides of the vertical nanosheets, nanosheet channel sections, and recessed sacrificial structures, in accordance with an embodiment of the present invention.

In one or more embodiments, source/drains220can be formed on opposite sides of the vertical nanosheets170, nanosheet channel sections132, and recessed sacrificial structures145, where the source/drains220can be formed by lateral epitaxial growth on the exposed semiconductor surfaces of the vertical nanosheets170and nanosheet channel sections132. The source/drains220can extend laterally along the inner spacers215and sacrificial structure145.

FIG.11illustrates perpendicular cross-sectional side views showing formation of an interlayer dielectric (ILD) layer on the source/drains and dummy gate sidewalls, and removal of the dummy gate cap, in accordance with an embodiment of the present invention.

In one or more embodiments, an interlayer dielectric (ILD) layer230can be formed on the source/drains220and dummy gate sidewalls200, where the interlayer dielectric (ILD) layer230can be formed by a conformal deposition (e.g., ALD, PEALD), a blanket deposition (e.g., CVD, PECVD), or a combination thereof.

In one or more embodiments, the dummy gate cap(s)190can be removed using chemical-mechanical polishing (CMP) and/or a selective etch to expose the underlying dummy gate fill180. The CMP can also remove an upper portion of the interlayer dielectric (ILD) layer230to provide a uniform surface.

FIG.12illustrates perpendicular cross-sectional side views showing removal of the dummy gate fill and bottom sacrificial layer and recessing of the fill layer to form gaps between the vertical nanosheets, nanosheet channel sections, and the substrate, in accordance with an embodiment of the present invention.

In one or more embodiments, the dummy gate fill180can be removed using a selective isotropic etch to expose the underlying vertical nanosheets170, nanosheet channel sections132, and recessed sacrificial structures145.

In one or more embodiments, the sacrificial structures145can be removed using a selective isotropic etch to expose the underlying vertical nanosheets170and nanosheet channel sections132.

In various embodiments, a portion of the fill layer160beneath the vertical nanosheets170and sacrificial structures145can be selectively removed. This is for exposing a bottom surface of vertical nanosheets170and sidewall(s) of the sacrificial section(s)122by recessing the fill layer160using a selective isotropic etch, for example, a wet chemical etch or dry plasma etch. In various embodiments, the amount removed by etching can be about the thickness of the vertical nanosheets (e.g., < 10 nm) especially when the top surface of the fill layer160is below the top surface of the bottom sacrificial section122because the bottom sacrificial section122would not need to be exposed by recessing the fill layer160. The sidewall of sacrificial section122may not be exposed, so that it can be selectively removed along with sacrificial structures145.

FIG.13illustrates perpendicular cross-sectional side views showing formation of an active gate structure on the vertical nanosheets and nanosheet channel sections, in accordance with an embodiment of the present invention.

In one or more embodiments, an active gate structure can be formed on the vertical nanosheets170and nanosheet channel sections132, where the active gate structure can include a gate dielectric layer240formed on the exposed surfaces of the vertical nanosheets170and nanosheet channel sections132, and a conductive gate fill250formed on the gate dielectric layer240. The gate dielectric layer240can be formed by a conformal deposition of an electrically insulating dielectric material on the exposed surfaces of the vertical nanosheets170and nanosheet channel sections132. The conductive gate fill250can be formed by a conformal deposition of a conductive material on the gate dielectric layer240.

In various embodiments, the gate dielectric layer240can be an electrically insulating dielectric material, including, but not limited to, silicon oxide, a high-k dielectric material, or a combination thereof. In various embodiments, the high-k dielectric material can include, but not be limited to, hafnium oxide (HfO), zirconium oxide (ZrO), hafnium-zirconium oxide (HfZr)), tantalum oxide (TaO), and combinations thereof.

In various embodiments, the conductive gate fill250can be a metal, including, but not limited to, copper (Cu), tungsten (W), ruthenium (Ru), cobalt (Co), molybdenum (Mo), a conductive metal compound, including, but not limited to, tantalum nitride (TaN), titanium nitride (TiN), tantalum carbide (TaC), titanium carbide (TiC), and combinations thereof. The conductive gate fill250can be a multilayer of a work function material and a metal.

FIG.14illustrates cross-sectional side views of a pFET with narrow nanosheets and an nFET with wide nanosheets on two different regions of a substrate, in accordance with an embodiment of the present invention.

In one or more embodiments, an n-type field effect transistor (nFET) device having wider nanosheets parallel with the plane of the substrate can be formed on a first region of the substrate, and a p-type field effect transistor (pFET) device can be formed on a second region of the substrate, where the first region and second region can be adjacent to form complimentary field effect transistor (CFET) devices. The pFETs can have device channels with a greater amount of {110} surface area, and the nFETs can have device channels with a greater amount of {001} surface area to increase charge carrier mobility. The methods described herein can be used to form FETs having nanosheets with different widths based on masking and lithography to define the width and length of the stack templates for forming the stack template(s) and alternating nanosheet channel sections and sacrificial sections on a bottom sacrificial section and the substrate.