Optical interconnect on bumpless build-up layer package

This disclosure relates generally to an electronic package that can include a die and a dielectric layer at least partially enveloping the die. Electrical interconnects can be electrically coupled to the die and passing, at least in part, through the dielectric layer. An optical emitter can be electrically coupled to the die with a first one of the electrical interconnects and configured to emit light from a first major surface of the electronic package. A solder bump can be electrically coupled to the die with a second one of the electrical interconnects and positioned on a second major surface of the electronic package different from the first major surface.

TECHNICAL FIELD

The disclosure herein relates generally to an optical interconnect on a bumpless build-up layer package and methods therefor.

BACKGROUND ART

Electronic packages have long utilized a variety of modes for transmitting and receiving information from a die contained within the package. Electrical interconnects provide electrical connectivity within the package between the die and the various communication components that can be utilized to transmit and receive electronic signals from and to the die. One such communication component is a conventional solder bump, configured to create a physical electrical connection between the package and another electronic device that communicates with the die. Another such communication component is an optical emitter, such as can be utilized in an optical coupler, that allows for communication utilizing light emission without necessitating a direct physical connection between the package and the communication destination.

DESCRIPTION OF THE EMBODIMENTS

Conventionally, optical emitters, such as vertical cavity surface emitting lasers, are wire bonded components. In various examples, to enable the solder bumps to be positioned on the same side of the package as the die, a vertical cavity surface emitting laser is backside emitting, in which the light emitting surface is on the side of the package opposite the surface with the solder bumps. As vertical cavity surface emitting lasers may be more plentiful and inexpensive in a frontside configuration, such vertical cavity surface emitting lasers may either be substantially incompatible with such package configurations or may be relatively expensive or rare. Additionally, owing to the use of wires within wire bonding technology and to the desire or need for optical access in optical interconnects, embedding the die completely in the package, such as can be the case with standard bumpless build up layer technology may be incompatible for use with optical interconnections using optical emitters.

New methodologies for building packages have been developed that allow for the use of either frontside or backside vertical cavity surface emitting lasers in the package. More generally, a bumpless buildup layer package has been developed that allows for the incorporation of optical interconnects and optical emitters in general. By taking advantage of an etching process, a cavity can be formed in the dielectric of a package that allows an optical emitter to emit light from a first major surface of the package to provide optical interconnection while solder bumps on a second major surface allow for physical electrical coupling.

FIG. 1is a side profile of a package100including a frontside vertical cavity surface emitting laser (VCSEL)102. As is understood in the art, the “front” side of a VCSEL is the side that includes the electrical connects104for the VCSEL102. As the light emitting apertures106are positioned on the same side as the electrical connects104, the VCSEL102is thereby a frontside VCSEL102. In various examples, the frontside VCSEL102is either a standard off-the-shelf VCSEL or is a proprietary design. In various examples, alternative optical emitters can be utilized, including photonic systems that utilize silicon as the optical medium and light emitting diodes (LEDs).

The package100includes a die108coupled to the electrical connects104of the VCSEL with conductive lines110. In various examples, the die108is a silicon die fabricated according to various methods to perform various electronic and computational tasks. In various examples, the conductive lines110are made from copper or other material known or yet to be developed that is useful to conduct electrical signals. For the purposes of this disclosure, the conductive lines110are understood to include conductive layers as well as vias between the conductive layers, both well understood in the art.

The conductive lines110are physically separated and, in various examples, mechanically supported by an insulator112. The insulator112can include separately formed layers of a material, such as a dielectric, that is substantially non-conductive of electrical signals to a degree that would be understood by one of ordinary skill in the art. In various examples, the material of the insulator112can be and is laminated.

The package100includes at least one solder bump114electrically coupled to the die108with a conductive line110. In various examples, the solder bump114is not necessarily made of solder and instead is any electrical connection that allows for a physical electrical connection between the package100and an external component, such as a circuit board or socket. In an example, the package100can output data via at least the VCSEL102and the solder bump114.

In order to seat and mechanically secure a frontside VCSEL102, in which the electrical connects104and the aperture106are on the same side of the VCSEL102, a cavity116is formed in the insulator112of approximately comparable length and width as the VCSEL102, and the VCSEL102is seated in the cavity116. The cavity116can be formed in the insulator112according to any suitable methodology. In various examples, the cavity116is formed according to various etching processes. In various examples, the cavity116is formed according to a plasma etching process, by sandblasting the insulator112, or by photo-exposing and then directly developing a photosensitive dielectric used as the insulator112. The package100optionally includes an etch stop118to block or inhibit further etching upon the etching reaching the etch stop118. The etch stop118can be made of material that is resistant to whatever etching material or process that is utilized to form the cavity116, such as copper. In an example, the etch stop118is a “dummy” conductive line110that is not necessarily coupled to an input or output of or within the package100.

In the illustrated example, the conductive lines110A that couple to the electrical connects104of the VCSEL102are formed after the VCSEL102is positioned in the cavity116. Upon forming the conductive lines110A, a top insulator layer112A is formed to insulate and at least partially mechanically secure the conductive lines110A. In various alternative examples, the cavity116is formed in a single action and conductive lines110and the top insulator layer112A are not formed after the formation of the cavity116. In various alternative examples, the cavity116is not formed through the removal of insulator layer112material but rather through forming the insulator layer112around the space of the cavity116.

The VCSEL102can be secured, at least in part, with the conductive lines110A. Additionally, the formation of the insulator112can provide mechanical support to the VCSEL102, such as by enclosing the VCSEL102in a cavity116that has an opening smaller than the length and/or width of the VCSEL102. In various examples, the package100further optionally includes a die attach film120to provide mechanical support to the VCSEL102and the die108. The die attach film120can be applied to the VCSEL102prior to inserting the VCSEL102into the cavity116or otherwise securing the VCSEL102to the insulator112specifically or the package100generally.

The package100thereby has a first major surface122from which light emitted from the VCSEL102originates and an opposite second major surface124on which the solder bump114is positioned. The light from the VCSEL102travels substantially perpendicular to the first major surface122. In various examples, the major surfaces122,124need not be opposite one another, such as in examples in which the major surfaces122,124are orthogonal with respect to one another. However, in certain such examples, the package100can be configured so that the light output of the VCSEL102can be accessed when the solder bump114is electrically coupled to an external electronic device.

The package100optionally includes an optical interconnect126configured to facilitate the transmission of light form the VCSEL102. In various examples, the optical interconnect126can optionally include, as appropriate, one or more lenses128configured to receive light emitted from the VCSEL102, a prism130or other coupler configured to re-direct light, and a coupler132and optical transmitter134, such as an optical fiber, configured to transmit the light sufficiently coherent that integrity of the data included in the emitted light is maintained during transmission to a destination receptor or detector. In various examples, multiple lenses128can be used to collimate or make substantially parallel light emitted from the VCSEL102in anticipation of transmission of the light along the optical transmitter134.

FIG. 2is a side profile of a package200including a backside vertical cavity surface emitting laser (VCSEL)202. As the light emitting apertures206are positioned on the opposite side as the electrical connects204, the VCSEL202is thereby a backside VCSEL202. In various examples, the backside VCSEL202is either a standard off-the-shelf VCSEL or is a proprietary design. As with the package200, in various examples, alternative optical emitters can be utilized, including photonic systems that utilize silicon as the optical medium and light emitting diodes (LEDs).

In various examples, apart from the backside VSCEL202, the package200can incorporate the same or otherwise similar componentry to that of the package100. The die108, conductive lines110, insulator112, and solder bump114can be the same or essentially the same in the package200as in the package100. The cavity216can similarly be formed as discussed in detail above with respect to the cavity116. The function of the etch stop118can be supplemented by the connects204or can be dispensed with altogether in various examples. Because the connects204can provide mechanical stability for the VCSEL202during manufacture of the package200, the die attach film120may be utilized with respect to the die108but not the VCSEL202. In various examples, the die attach film120may be utilized with respect to the VCSEL202as well.

In the illustrated example, because conductive lines110do not need to reach an external surface of the VCSEL202, the cavity can be of an essentially identical length and width as the VCSEL202. In contrast to various examples of the insulator112of the package100, the insulator112of the package200may not necessarily be formed in a stage or layer after the VCSEL202is coupled to the package200. Consequently, in various examples, etching or other cavity formation method may be performed after the formation of the complete insulator112.

The package200retains the perpendicular or essentially perpendicular emission of light from the first major surface122while the physical electrical connection occurs by way of the solder bump114on the second major surface124. As with the package100, the major surfaces122,124can be on opposite sides of the package200, though various arrangements can places the major surfaces122,124in orientations other than parallel with respect to one another, such as an orthogonal orientation. The lack of obstruction of the physical interconnection with an external electronic component may support the incorporation of the optical interconnect126with respect to the first major surface122.

FIGS. 3A-3Fillustrate a sequential process flow for making the package100utilizing frontside VSCEL102. The process flow may further be utilized for making a variety of packages, while the package100itself may be made according to any suitable process.

InFIG. 3A, the package100is substantially formed or otherwise provided. The conductive lines110and insulator112are formed with respect to the die108. The etch stop118can also be formed, such as by creating a dummy conductive line110. It is noted that, in various conventional die packages that do not necessarily utilize the methodologies disclosed herein, a solder bump may be positioned on the exposed conductive lines110B. In various examples, dry film patterning may be applied to facilitate creating the cavity116.

In various examples, the insulator112is formed through a buildup process of separately and sequentially applying or laminating layers112′,112″ of insulative material. In such an example, the conductive lines110can be formed by sequentially creating conductive layers110′ and vias110″ in sequence with the formation of the dielectric insulation layers112′,112″. Buildup support components, such as a long copper foil300, a dielectric film301, and a cavity copper foil302, can be utilized to support the buildup process.

In various examples, the dielectric film301is a low-modulus laminate film configured to act as an etch stop in examples where the long copper foil300is removed through an etching process. In such examples, the dielectric film301is ultimately removed, such as through sandblasting. In various examples, the cavity copper foil302is removable through wet etching.

InFIG. 3B, the cavity116is formed in the insulator112. In various examples, the cavity116is formed according to methodologies described above, such as etching. In various examples, the cavity is formed to be at least as wide and long as the VSCEL102, as is formed to extend at least as deep as the etch stop118.

InFIG. 3C, the VSCEL102is inserted into the cavity116. In various examples, the VSCEL102is at least partially mechanically adhered by the die attach film120. The die attach film120can have come pre-attached to the VSCEL102or can have been previously applied to the etch stop118or other surface within the cavity116. The cavity116may have been sized so that the connects104are exposed flush with or, in the illustrative example, above the insulator112so as to facilitate subsequent electrical coupling with the connects104.

InFIG. 3D, the conductive lines110A are electrically coupled to the connects104and the insulator layer112A is applied. In various examples, the conductive lines110A and the insulator layer112A are applied in stages according to sequential buildup procedures, as described herein.

InFIG. 3E, the cavity116is expanded to provide optical access to the apertures106. The cavity116may be expanded using the same techniques described above with respect toFIG. 3Babove and throughout. In an example, dry film resist and etching may be utilized to expand the cavity116.

InFIG. 3F, the long copper foil300, dielectric film301, and cavity copper foil302are removed, such as in the manners detailed above, the solder bumps114are applied, and the optical interconnect126is coupled to complete the package100. As illustrated, the conductive lines110couple the connects104, the die108and the solder bumps114, meaning that the output on a solder bump114is the same as the output of the VCSEL102. In various examples, the VCSEL102and solder bumps114are not electrically coupled with respect to one another.

FIGS. 4A-4Dillustrate a sequential process flow for making the package200utilizing a backside VSCEL202. The process flow may further be utilized for making a variety of packages, while the package200itself may be made according to any suitable process.

InFIG. 4A, the package200is substantially formed or otherwise provided. The conductive lines110and insulator112are formed with respect to the die108. The etch stop118that may be included in the package100may be omitted owing to the existing structure of the conductive lines110. As illustrated and in further contrast to the package100, the conductive lines110and insulator112may be entirely or substantially fully formed prior to forming the cavity116.

In various examples, the insulator112is formed through a buildup process of separately and sequentially applying or laminating layers112′,112″ of insulative material. In such an example, the conductive lines110can be formed by sequentially creating conductive layers110′ and vias110″ in sequence with the formation of the dielectric insulation layers112′,112″. Buildup support components, such as a long copper foil300, dielectric film301, and cavity copper foil302, can be utilized to support the buildup process, detailed above.

InFIG. 4B, the cavity116is formed in the insulator112. In various examples, the cavity116is formed according to methodologies described above, such as etching. In various examples, the cavity is formed to be at least as wide and long as the VSCEL202, as is formed to extend at least as deep as the conductive lines110.

InFIG. 4C, the VSCEL202is inserted into the cavity116. In various examples, the VSCEL202is at least partially mechanically secured by electrically coupling the connects204to the conductive lines110. The connects204can be electrically coupled with solder balls304or by other electrical coupling methodologies.

InFIG. 4D, the long copper foil300, the dielectric film301, and cavity copper foil302are removed, the solder bumps114are applied, and the optical interconnect126is coupled to complete the package200. As illustrated, and in contrast to the package100, the conductive lines110do not interconnect the solder bumps114with the connects204of the VCSEL202. In various examples, the VCSEL202and solder bumps114are electrically coupled with respect to one another, as in the package100.

FIG. 5is a flowchart for making the package100,200. The flowchart may be applied to the creation of a variety of packages or other electronic devices in addition to the package100,200. Additionally, the package100may alternatively be made according to any of a variety of suitable methods.

At500, electrical interconnects, such as conductive lines110, are electrically coupled to the die108.

At502, a buildup layer, such as the insulator112, is formed. In an example, the buildup layer112is a dielectric layer made up of a dielectric material. The dielectric layer at least partially or substantially envelops the die108and the electrical interconnects110. In various examples,500and502occur iteratively, with individual electrical interconnect layers110′,110″ and dielectric layers112′,112″ added in discrete stages. In an example,500and502iteratively alternate multiple times until the electrical interconnects110and dielectric layer112reach a predetermined stage, such as may be illustrated inFIGS. 3A and 4A.

At504, the cavity116is formed according to methodologies, such as are disclosed herein. In various examples, etching, such as plasma etching, is utilized to form the cavity116. In an example, dry film patterning is also utilized.

At506, an optical emitter, such as frontside VSCEL102or backside VSCEL202, is positioned within the cavity116.

At508, the optical emitter102,202is electrically coupled to a first one of the electrical interconnects110. The optical emitter102,202is thereby electrically coupled to the die108and is configured to emit light from the first major surface122of the package100,200. In an example, the optical emitter102,202is configured to emit light substantially perpendicular to the first major surface122. In an example, the optical emitter is configured to emit light according to a communication modality, such as to communicate information from the die108to a component external to the package100,200.

At510, in the case of the package100, where the electrical interconnect110A projects, at least in part, from the dielectric layer112, a second dielectric layer112A is formed that at least partially or substantially envelops the electrical interconnect110A and forms, at least in part, the cavity116.

At512, the optical interconnect126is positioned with respect to the optical emitter102,202. In various examples, the optical interconnect126is configured to support communication according to the communication modality from the optical emitter102,202. A lens128of the optical interconnect126is configured to receive light emitted from the optical emitter102,202. An optical transmitter134is configured to transmit light transmitted by the optical emitter102,202and received by the lens128to an optical detector. The optical interconnect126optionally further includes a plurality of lenses128configured to receive and collimate the light emitted from the optical emitter102,202. The optical interconnect126optionally further includes a prism130configured to direct the light received by the lens or lenses128in a direction other than substantially perpendicular to the first major surface122.

At514, a solder bump114is coupled to a second one of the interconnects110and electrically coupled to the die108. The solder bump114is positioned on the second major surface124of the package100. In an example, the second major surface124is opposite the first major surface122.

An example of an electronic device using semiconductor chips and elongated structures as described in the present disclosure is included to show an example of a higher level device application for the present invention.FIG. 6is a block diagram of an electronic device600incorporating at least one package, such as package100,200or other package described in examples herein. The electronic device600is merely one example of an electronic system in which embodiments of the present invention can be used. Examples of electronic devices600include, but are not limited to personal computers, tablet computers, mobile telephones, personal data assistants, MP3 or other digital music players, etc. In this example, the electronic device600comprises a data processing system that includes a system bus602to couple the various components of the system. The system bus602provides communications links among the various components of the electronic device600and can be implemented as a single bus, as a combination of busses, or in any other suitable manner.

An electronic assembly610is coupled to the system bus602. The electronic assembly610can include any circuit or combination of circuits. In one embodiment, the electronic assembly610includes a processor612which can be of any type. As used herein, “processor” means any type of computational circuit, such as but not limited to a microprocessor, a microcontroller, a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a graphics processor, a digital signal processor (DSP), multiple core processor, or any other type of processor or processing circuit.

Other types of circuits that can be included in the electronic assembly610are a custom circuit, an application-specific integrated circuit (ASIC), or the like, such as, for example, one or more circuits (such as a communications circuit614) for use in wireless devices like mobile telephones, pagers, personal data assistants, portable computers, two-way radios, and similar electronic systems. The IC can perform any other type of function.

The electronic device600can also include an external memory620, which in turn can include one or more memory elements suitable to the particular application, such as a main memory622in the form of random access memory (RAM), one or more hard drives624, and/or one or more drives that handle removable media626such as compact disks (CD), digital video disk (DVD), and the like.

The electronic device600can also include a display device616, one or more speakers618, and a keyboard and/or controller630, which can include a mouse, trackball, touch screen, voice-recognition device, or any other device that permits a system user to input information into and receive information from the electronic device600.

ADDITIONAL EXAMPLES

Example 1 may include subject matter (such as an apparatus, a method, a means for performing acts) that can include a method of making a package. The method may comprise electrically coupling electrical interconnects to a die, forming a dielectric layer that at least partially envelops the die and the electrical interconnects, electrically coupling an optical emitter to a first one of the electrical interconnects, wherein the optical emitter is electrically coupled to the die, and wherein the optical emitter is configured to emit light from a first major surface of the package, and forming a solder bump coupled to a second one of the electrical interconnects and electrically coupled to the die, wherein the solder bump is positioned on a second major surface of the package.

In Example 2, the method of Example 1 can optionally further include that the second major surface is opposite the first major surface.

In Example 3, the method of any one or more of Examples 1 and 2 can optionally further include that the optical emitter is configured to emit light substantially perpendicular to the first major surface.

In Example 4, the method of any one or more of Examples 1-3 can optionally further include positioning an optical interconnect with respect to the optical emitter, the optical interconnect comprising a lens configured to receive light emitted from the optical emitter and an optical transmitter configured to transmit the light emitted from the optical emitter to an optical detector.

In Example 5, the method of any one or more of Examples 1-4 can optionally further include that the optical emitter is configured to emit light according to a communication modality.

In Example 6, the method of any one or more of Examples 1-5 can optionally further comprise an optical interconnect that further comprises a plurality of lenses configured to receive and collimate the light emitted from the optical emitter and a prism configured to direct the light received by the plurality of lenses in a direction other than substantially perpendicular to the first major surface.

In Example 7, the method of any one or more of Examples 1-6 can optionally further comprise forming a cavity in the dielectric layer and positioning the optical emitter within the cavity.

In Example 8, the method of any one or more of Examples 1-7 can optionally further include that the dielectric layer comprises a dielectric material, and wherein forming the cavity comprises etching the cavity in the dielectric material of the dielectric layer, sandblasting the dielectric material, and photo-exposing and developing the dielectric material.

In Example 9, the method of any one or more of Examples 1-8 can optionally further include that the optical emitter is a vertical cavity surface emitting laser.

In Example 10, the method of any one or more of Examples 1-9 can optionally further include that the vertical cavity surface emitting laser is a frontside emitting vertical cavity surface emitting laser, that the dielectric layer is a first dielectric layer, that the first electrical interconnect projects, at least in part, from the first dielectric layer relative to the first surface, and can further comprise forming a second dielectric layer at least partially enveloping the first electrical interconnect and forming, at least in part, the cavity.

Example 11 may include subject matter (such as an apparatus, a method, a means for performing acts) that can include an electronic package that comprises a die, a dielectric layer at least partially enveloping the die, electrical interconnects electrically coupled to the die and passing, at least in part, through the dielectric layer, an optical emitter electrically coupled to the die with a first one of the electrical interconnects and configured to emit light from a first major surface of the electronic package, and a solder bump electrically coupled to the die with a second one of the electrical interconnects and positioned on a second major surface of the electronic package different from the first major surface.

In Example 12, the device of Example 11 can optionally further include that the second major surface is opposite the first major surface.

In Example 13, the device of any one or more of Examples 11 and 12 can optionally further include that the optical emitter is configured to emit light substantially perpendicular to the first major surface.

In Example 14, the device of any one or more of Examples 11-13 can optionally further comprise an optical interconnect comprising a lens configured to receive light emitted from the optical emitter and an optical transmitter configured to transmit the light emitted from the optical emitter to an optical detector.

In Example 15, the device of any one or more of Examples 11-14 can optionally further include that the optical emitter is configured to emit light according to a communication modality.

In Example 16, the device of any one or more of Examples 11-15 can optionally further include that the optical interconnect further comprises a plurality of lenses configured to receive and collimate the light emitted from the optical emitter and a prism configured to direct the light received by the plurality of lenses in a direction other than substantially perpendicular to the first major surface.

In Example 17, the device of any one or more of Examples 11-16 can optionally further include that the optical emitter is seated within a cavity in the dielectric layer.

In Example 18, the device of any one or more of Examples 11-17 can optionally further include that the optical emitter is a semiconductor optical emitter.

In Example 19, the device of any one or more of Examples 11-18 can optionally further include that the optical emitter is a vertical cavity surface emitting laser.

In Example 20, the device of any one or more of Examples 11-19 can optionally further include that the vertical cavity surface emitting laser is chosen from a group consisting of a frontside emitting vertical cavity surface emitting laser and a backside emitting vertical cavity surface emitting laser.

Each of these non-limiting examples can stand on its own, or can be combined with one or more of the other examples in any permutation or combination.