Image warping in an image processor

A device that includes integrated circuit includes a tiler circuit, a grid generator, and a warper circuit. The tiler circuit divides the distorted input image data into a plurality of image tiles and stores the image tiles into a memory device. Each image tile is an M×N array of pixel samples where M and N are greater than 1. The grid generator produces a mesh grid that describes a mapping of first pixel locations of the distorted image data to second pixel locations of the corrected image data. The warper circuit reads one or more of the image tiles from the memory device based on the mesh grid and interpolates a warped output image from the image tiles read from memory.

BACKGROUND

Image data captured by an image sensor or received from other data sources is often processed in an image processing pipeline before further processing or consumption. For example, raw image data may be corrected, filtered, or otherwise modified before being provided to subsequent components such as a video encoder. To perform corrections or enhancements for captured image data, various components, unit stages or modules may be employed.

Such an image processing pipeline may be structured so that corrections or enhancements to the captured image data can be performed in an expedient way without consuming other system resources. Although many image processing algorithms may be performed by executing software programs on a central processing unit (CPU), execution of such programs on the CPU would consume significant bandwidth of the CPU and other peripheral resources as well as increase power consumption. Hence, image processing pipelines are often implemented as a hardware component separate from the CPU and dedicated to perform one or more image processing algorithms.

Raw image data may contain visual anomalies (e.g., due to rolling shutter effect) that can cause the resulting output image to appear distorted. For example, if a user causes a device to deviate from a fixed origin while capturing an image (e.g., pan, tilt, zoom, etc.), the resulting output image may contain unintended skew within certain portions of the image. To correct this distortion, a warper can transform pixels of an input image into an output image. However, the degree to which the warper can correct certain types of distortion, such as rotational distortion, may be limited.

SUMMARY

In one embodiment, a device is disclosed that receives input image data and generates corrected output image data. The device includes a memory and an integrated circuit. The integrated circuit includes a tiler circuit, a grid generator, and a warper circuit. The tiler circuit divides the input image data into a plurality of image tiles and stores the image tiles into memory. Each image tile is an M×N array of pixel samples where M and N are integers greater than 1. The grid generator produces a mesh grid that describes a mapping of first pixel locations of the input image data to second pixel locations of the corrected output image data. The warper circuit reads one or more of the image tiles from the memory device based on the mesh grid and generates a warped output image from the image tiles read from memory.

The figures depict, and the detail description describes, various non-limiting embodiments for purposes of illustration only.

DETAILED DESCRIPTION

In one embodiment, an output rescale module of an electronic device receives distorted input image data and generates corrected output image data. The output rescale module includes a tiler circuit that divides an image into a number of image tiles that can be stored in memory, a grid generator circuit that generates a mesh grid, and a warper circuit that reads the image tiles from memory as it maps the distorted input image data into corrected output image data using the mesh grid. By correcting distorted image data using tiled images, the warper circuit can perform a greater degree of vertical deflection in the output image.

Exemplary Electronic Device

Embodiments of electronic devices, user interfaces for such devices, and associated processes for using such devices are described. In some embodiments, the device is a portable communications device, such as a mobile telephone, that also contains other functions, such as personal digital assistant (PDA) and/or music player functions. Exemplary embodiments of portable multifunction devices include, without limitation, the iPhone®, iPod Touch®, Apple Watch®, and iPad® devices from Apple Inc. of Cupertino, Calif. Other portable electronic devices, such as wearables, laptops or tablet computers, are optionally used. In some embodiments, the device is not a portable communications device, but is a desktop computer or other computing device that is not designed for portable use. In some embodiments, the disclosed electronic device may include a touch sensitive surface (e.g., a touch screen display and/or a touch pad). An example electronic device described below in conjunction withFIG. 1(e.g., device100) may include a touch-sensitive surface for receiving user input. The electronic device may also include one or more other physical user-interface devices, such as a physical keyboard, a mouse and/or a joystick.

Figure (FIG. 1is a high-level diagram of an electronic device100, according to one embodiment. Device100may include one or more physical buttons, such as a “home” or menu button104. Menu button104is, for example, used to navigate to any application in a set of applications that are executed on device100. In some embodiments, menu button104includes a fingerprint sensor that identifies a fingerprint on menu button104. The fingerprint sensor may be used to determine whether a finger on menu button104has a fingerprint that matches a fingerprint stored for unlocking device100. Alternatively, in some embodiments, menu button104is implemented as a soft key in a graphical user interface (GUI) displayed on a touch screen.

In some embodiments, device100includes touch screen150, menu button104, push button106for powering the device on/off and locking the device, volume adjustment buttons108, Subscriber Identity Module (SIM) card slot110, head set jack112, and docking/charging external port124. Push button106may be used to turn the power on/off on the device by depressing the button and holding the button in the depressed state for a predefined time interval; to lock the device by depressing the button and releasing the button before the predefined time interval has elapsed; and/or to unlock the device or initiate an unlock process. In an alternative embodiment, device100also accepts verbal input for activation or deactivation of some functions through microphone113. The device100includes various components including, but not limited to, a memory (which may include one or more computer readable storage mediums), a memory controller, one or more central processing units (CPUs), a peripherals interface, an RF circuitry, an audio circuitry, speaker111, microphone113, input/output (I/O) subsystem, and other input or control devices. Device100may include one or more image sensors164, one or more proximity sensors166, and one or more accelerometers168. The device100may include components not shown inFIG. 1.

Device100is only one example of an electronic device, and device100may have more or fewer components than listed above, some of which may be combined into a components or have a different configuration or arrangement. The various components of device100listed above are embodied in hardware, software, firmware or a combination thereof, including one or more signal processing and/or application specific integrated circuits (ASICs).

FIG. 2is a block diagram illustrating components in device100, according to one embodiment. Device100may perform various operations including image processing. For this and other purposes, the device100may include, among other components, image sensor202, system-on-a chip (SOC) component204, system memory230, persistent storage (e.g., flash memory)228, motion sensor234, and display216. The components as illustrated inFIG. 2are merely illustrative. For example, device100may include other components (such as speaker or microphone) that are not illustrated inFIG. 2. Further, some components (such as orientation sensor234) may be omitted from device100.

Image sensor202is a component for capturing image data and may be embodied, for example, as a complementary metal-oxide-semiconductor (CMOS) active-pixel sensor) a camera, video camera, or other devices. Image sensor202generates raw image data that is sent to SOC component204for further processing. In some embodiments, the image data processed by SOC component204is displayed on display216, stored in system memory230, persistent storage228or sent to a remote computing device via network connection. The raw image data generated by image sensor202may be in a Bayer color filter array (CFA) pattern (hereinafter also referred to as “Bayer pattern”).

Motion sensor234is a component or a set of components for sensing motion of device100. Motion sensor234may generate sensor signals indicative of orientation and/or acceleration of device100. The sensor signals are sent to SOC component204for various operations such as turning on device100or rotating images displayed on display216.

Display216is a component for displaying images as generated by SOC component204. Display216may include, for example, liquid crystal display (LCD) device or an organic light emitting diode (OLED) device. Based on data received from SOC component204, display116may display various images, such as menus, selected operating parameters, images captured by image sensor202and processed by SOC component204, and/or other information received from a user interface of device100(not shown).

System memory230is a component for storing instructions for execution by SOC component204and for storing data processed by SOC component204. System memory230may be embodied as any type of memory including, for example, dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) RAMBUS DRAM (RDRAM), static RAM (SRAM) or a combination thereof. In some embodiments, system memory230may store pixel data or other image data or statistics in various formats.

Persistent storage228is a component for storing data in a non-volatile manner. Persistent storage228retains data even when power is not available. Persistent storage228may be embodied as read-only memory (ROM), NAND or NOR flash memory or other non-volatile random access memory devices.

SOC component204is embodied as one or more integrated circuit (IC) chip and performs various data processing processes. SOC component204may include, among other subcomponents, image signal processor (ISP)206, a central processor unit (CPU)208, a network interface210, sensor interface212, display controller214, graphics processor (GPU)220, memory controller222, video encoder224, storage controller226, and various other input/output (I/O) interfaces218, and bus232connecting these subcomponents. SOC component204may include more or fewer subcomponents than those shown inFIG. 2.

ISP206is hardware that performs various stages of an image processing pipeline. In some embodiments, ISP206may receive raw image data from image sensor202, and process the raw image data into a form that is usable by other subcomponents of SOC component204or components of device100. ISP206may perform various image-manipulation operations such as image translation operations, horizontal and vertical scaling, color space conversion and/or image stabilization transformations, as described below in detail with reference toFIG. 3.

CPU208may be embodied using any suitable instruction set architecture, and may be configured to execute instructions defined in that instruction set architecture. CPU208may be general-purpose or embedded processors using any of a variety of instruction set architectures (ISAs), such as the x86, PowerPC, SPARC, RISC, ARM or MIPS ISAs, or any other suitable ISA. Although a single CPU is illustrated inFIG. 2, SOC component204may include multiple CPUs. In multiprocessor systems, each of the CPUs may commonly, but not necessarily, implement the same ISA.

Graphics processing unit (GPU)220is graphics processing circuitry for performing graphical data. For example, GPU220may render objects to be displayed into a frame buffer (e.g., one that includes pixel data for an entire frame). GPU220may include one or more graphics processors that may execute graphics software to perform a part or all of the graphics operation, or hardware acceleration of certain graphics operations.

I/O interfaces218are hardware, software, firmware or combinations thereof for interfacing with various input/output components in device100. I/O components may include devices such as keypads, buttons, audio devices, and sensors such as a global positioning system. I/O interfaces218process data for sending data to such I/O components or process data received from such I/O components.

Network interface210is a subcomponent that enables data to be exchanged between devices100and other devices via one or more networks (e.g., carrier or agent devices). For example, video or other image data may be received from other devices via network interface210and be stored in system memory230for subsequent processing (e.g., via a back-end interface to image signal processor206, such as discussed below inFIG. 3) and display. The networks may include, but are not limited to, Local Area Networks (LANs) (e.g., an Ethernet or corporate network) and Wide Area Networks (WANs). The image data received via network interface210may undergo image processing processes by ISP206.

Sensor interface212is circuitry for interfacing with motion sensor234. Sensor interface212receives sensor information from motion sensor234and processes the sensor information to determine the orientation or movement of the device100.

Display controller214is circuitry for sending image data to be displayed on display216. Display controller214receives the image data from ISP206, CPU208, graphic processor220or system memory230and processes the image data into a format suitable for display on display216.

Memory controller222is circuitry for communicating with system memory230. Memory controller222may read data from system memory230for processing by ISP206, CPU208, GPU220or other subcomponents of SOC component204. Memory controller222may also write data to system memory230received from various subcomponents of SOC component204.

Video encoder224is hardware, software, firmware or a combination thereof for encoding video data into a format suitable for storing in persistent storage128or for passing the data to network interface w10for transmission over a network to another device.

In some embodiments, one or more subcomponents of SOC component204or some functionality of these subcomponents may be performed by software components executed on ISP206, CPU208or GPU220. Such software components may be stored in system memory230, persistent storage228or another device communicating with device100via network interface210.

Image data or video data may flow through various data paths within SOC component204. In one example, raw image data may be generated from the image sensor202and processed by ISP206, and then sent to system memory230via bus232and memory controller222. After the image data is stored in system memory230, it may be accessed by video encoder224for encoding or by display116for displaying via bus232.

In another example, image data is received from sources other than the image sensor202. For example, video data may be streamed, downloaded, or otherwise communicated to the SOC component204via wired or wireless network. The image data may be received via network interface210and written to system memory230via memory controller222. The image data may then be obtained by ISP206from system memory230and processed through one or more image processing pipeline stages, as described below in detail with reference toFIG. 3. The image data may then be returned to system memory230or be sent to video encoder224, display controller214(for display on display216), or storage controller226for storage at persistent storage228.

Example Image Signal Processing Pipelines

FIG. 3is a block diagram illustrating image processing pipelines implemented using ISP206, according to one embodiment. In the embodiment ofFIG. 3, ISP206is coupled to image sensor202to receive raw image data. ISP206implements an image processing pipeline which may include a set of stages that process image information from creation, capture or receipt to output. ISP206may include, among other components, sensor interface302, central control320, front-end pipeline stages330, back-end pipeline stages340, image statistics module304, vision module322, back-end interface342, and output interface316. ISP206may include other components not illustrated inFIG. 3or may omit one or more components illustrated inFIG. 3.

In one or more embodiments, different components of ISP206process image data at different rates. In the embodiment ofFIG. 3, front-end pipeline stages330(e.g., raw processing stage306and resample processing stage308) may process image data at an initial rate. Thus, the various different techniques, adjustments, modifications, or other processing operations performed by these front-end pipeline stages330at the initial rate. For example, if the front-end pipeline stages330process 2 pixels per clock cycle, then raw processing stage306operations (e.g., black level compensation, highlight recovery and defective pixel correction) may process 2 pixels of image data at a time. In contrast, one or more back-end pipeline stages340may process image data at a different rate less than the initial data rate. For example, in the embodiment ofFIG. 3, back-end pipeline stages340(e.g., noise processing stage310, color processing stage312, and output rescale314) may be processed at a reduced rate (e.g., 1 pixel per clock cycle). Although embodiments described herein include embodiments in which the one or more back-end pipeline stages340process image data at a different rate than an initial data rate, in some embodiments back-end pipeline stages340may process image data at the initial data rate.

Sensor interface302receives raw image data from image sensor202and processes the raw image data into image data processable by other stages in the pipeline. Sensor interface302may perform various preprocessing operations, such as image cropping, binning or scaling to reduce image data size. In some embodiments, pixels are sent from the image sensor202to sensor interface302in raster order (i.e., horizontally on a line by line basis). The subsequent processes in the pipeline may also be performed in raster order and the result may also be output in raster order. Although only a single image sensor and a single sensor interface302are illustrated inFIG. 3, when more than one image sensor is provided in device100, a corresponding number of sensor interfaces may be provided in ISP206to process raw image data from each image sensor.

Front-end pipeline stages330process image data in raw or full-color domains. Front-end pipeline stages330may include, but are not limited to, raw processing stage306and resample processing stage308. A raw image data may be in Bayer raw format, for example. In Bayer raw image format, pixel data with values specific to a particular color (instead of all colors) is provided in each pixel. In an image capturing sensor, image data is typically provided in a Bayer pattern. Raw processing stage306may process image data in a Bayer raw format.

The operations performed by raw processing stage306include, but are not limited, sensor linearization, black level compensation, fixed pattern noise reduction, defective pixel correction, raw noise filtering, lens shading correction, white balance gain, and highlight recovery. Sensor linearization refers to mapping non-linear image data to linear space for other processing. Black level compensation refers to providing digital gain, offset and clip independently for each color component (e.g., Gr, R, B, Gb) of the image data. Fixed pattern noise reduction refers to removing offset fixed pattern noise and gain fixed pattern noise by subtracting a dark frame from an input image and multiplying different gains to pixels. Defective pixel correction refers to detecting defective pixels, and then replacing defective pixel values. Raw noise filtering refers to reducing noise of image data by averaging neighbor pixels that are similar in brightness. Highlight recovery refers to estimating pixel values for those pixels that are clipped (or nearly clipped) from other channels. Lens shading correction refers to applying a gain per pixel to compensate for a dropoff in intensity roughly proportional to a distance from a lens optical center. White balance gain refers to providing digital gains for white balance, offset and clip independently for all color components (e.g., Gr, R, B, Gb in Bayer format). Components of ISP206may convert raw image data into image data in full-color domain, and thus, raw processing stage306may process image data in the full-color domain in addition to or instead of raw image data.

Resample processing stage308performs various operations to convert, resample, or scale image data received from raw processing stage306. Operations performed by resample processing stage308may include, but not limited to, demosaic operation, per-pixel color correction operation, Gamma mapping operation, color space conversion and downscaling or sub-band splitting. Demosaic operation refers to converting or interpolating missing color samples from raw image data (for example, in a Bayer pattern) to output image data into a full-color domain. Demosaic operation may include low pass directional filtering on the interpolated samples to obtain full-color pixels. Per-pixel color correction operation refers to a process of performing color correction on a per-pixel basis using information about relative noise standard deviations of each color channel to correct color without amplifying noise in the image data. Gamma mapping refers to converting image data from input image data values to output data values to perform special image effects, including black and white conversion, sepia tone conversion, negative conversion, or solarize conversion. For the purpose of Gamma mapping, lookup tables (or other structures that index pixel values to another value) for different color components or channels of each pixel (e.g., a separate lookup table for Y, Cb, and Cr color components) may be used. Color space conversion refers to converting color space of an input image data into a different format. In one embodiment, resample processing stage308converts RBD format into YCbCr format for further processing.

Central control module320may control and coordinate overall operation of other components in ISP206. Central control module320performs operations including, but not limited to, monitoring various operating parameters (e.g., logging clock cycles, memory latency, quality of service, and state information), updating or managing control parameters for other components of ISP206, and interfacing with sensor interface302to control the starting and stopping of other components of ISP206. For example, central control module320may update programmable parameters for other components in ISP206while the other components are in an idle state. After updating the programmable parameters, central control module320may place these components of ISP206into a run state to perform one or more operations or tasks. Central control module320may also instruct other components of ISP206to store image data (e.g., by writing to system memory230inFIG. 2) before, during, or after resample processing stage308. In this way full-resolution image data in raw or full-color domain format may be stored in addition to or instead of processing the image data output from resample processing stage308through backend pipeline stages340.

Image statistics module304performs various operations to collect statistic information associated with the image data. The operations for collecting statistics information may include, but not limited to, sensor linearization, mask patterned defective pixels, sub-sample raw image data, detect and replace non-patterned defective pixels, black level compensation, lens shading correction, and inverse black level compensation. After performing one or more of such operations, statistics information such as 3A statistics (Auto white balance (AWB), auto exposure (AE), auto focus (AF)), histograms (e.g., 2D color or component) and any other image data information may be collected or tracked. In some embodiments, certain pixels' values, or areas of pixel values may be excluded from collections of certain statistics data (e.g., AF statistics) when preceding operations identify clipped pixels. Although only a single statistics module304is illustrated inFIG. 3, multiple image statistics modules may be included in ISP206. In such embodiments, each statistic module may be programmed by central control module320to collect different information for the same or different image data.

Vision module322performs various operations to facilitate computer vision operations at CPU208such as facial detection in image data. The vision module322may perform various operations including pre-processing, global tone-mapping and Gamma correction, vision noise filtering, resizing, keypoint detection, convolution and generation of histogram-of-orientation gradients (HOG). The pre-processing may include subsampling or binning operation and computation of luminance if the input image data is not in YCrCb format. Global mapping and Gamma correction can be performed on the pre-processed data on luminance image. Vision noise filtering is performed to remove pixel defects and reduce noise present in the image data, and thereby, improve the quality and performance of subsequent computer vision algorithms. Such vision noise filtering may include detecting and fixing dots or defective pixels, and performing bilateral filtering to reduce noise by averaging neighbor pixels of similar brightness. Various vision algorithms use images of different sizes and scales. Resizing of an image is performed, for example, by binning or linear interpolation operation. Keypoints are locations within an image that are surrounded by image patches well suited to matching in other images of the same scene or object. Such keypoints are useful in image alignment, computing cameral pose and object tracking. Keypoint detection refers to the process of identifying such keypoints in an image. Convolution may be used in image/video processing and machine vision. Convolution may be performed, for example, to generate edge maps of images or smoothen images. HOG provides descriptions of image patches for tasks in mage analysis and computer vision. HOG can be generated, for example, by (i) computing horizontal and vertical gradients using a simple difference filter, (ii) computing gradient orientations and magnitudes from the horizontal and vertical gradients, and (iii) binning the gradient orientations.

Back-end interface342receives image data from other image sources than image sensor102and forwards it to other components of ISP206for processing. For example, image data may be received over a network connection and be stored in system memory230. Back-end interface342retrieves the image data stored in system memory230and provide it to back-end pipeline stages340for processing. One of many operations that are performed by back-end interface342is converting the retrieved image data to a format that can be utilized by back-end processing stages340. For instance, back-end interface342may convert RGB, YCbCr 4:2:0, or YCbCr 4:2:2 formatted image data into YCbCr 4:4:4 color format.

Back-end pipeline stages340processes image data according to a particular full-color format (e.g., YCbCr 4:4:4 or RGB). In some embodiments, components of the back-end pipeline stages340may convert image data to a particular full-color format before further processing. Back-end pipeline stages340may include, among other stages, noise processing stage310and color processing stage312. Back-end pipeline stages340may include other stages not illustrated inFIG. 3.

Noise processing stage310performs various operations to reduce noise in the image data. The operations performed by noise processing stage310include, but are not limited to, color space conversion, gamma/de-gamma mapping, temporal filtering, noise filtering, luma sharpening, and chroma noise reduction. The color space conversion may convert an image data from one color space format to another color space format (e.g., RGB format converted to YCbCr format). Gamma/de-gamma operation converts image data from input image data values to output data values to perform special image effects. Temporal filtering filters noise using a previously filtered image frame to reduce noise. For example, pixel values of a prior image frame are combined with pixel values of a current image frame. Noise filtering may include, for example, spatial noise filtering. Luma sharpening may sharpen luma values of pixel data while chroma suppression may attenuate chroma to gray (i.e. no color). In some embodiment, the luma sharpening and chroma suppression may be performed simultaneously with spatial nose filtering. The aggressiveness of noise filtering may be determined differently for different regions of an image. Spatial noise filtering may be included as part of a temporal loop implementing temporal filtering. For example, a previous image frame may be processed by a temporal filter and a spatial noise filter before being stored as a reference frame for a next image frame to be processed. In other embodiments, spatial noise filtering may not be included as part of the temporal loop for temporal filtering (e.g., the spatial noise filter may be applied to an image frame after it is stored as a reference image frame (and thus is not a spatially filtered reference frame).

Color processing stage312may perform various operations associated with adjusting color information in the image data. The operations performed in color processing stage312include, but are not limited to, local tone mapping, gain/offset/clip, color correction, three-dimensional color lookup, gamma conversion, and color space conversion. Local tone mapping refers to spatially varying local tone curves in order to provide more control when rendering an image. For instance, a two-dimensional grid of tone curves (which may be programmed by the central control module320) may be bi-linearly interpolated such that smoothly varying tone curves are created across an image. In some embodiments, local tone mapping may also apply spatially varying and intensity varying color correction matrices, which may, for example, be used to make skies bluer while turning down blue in the shadows in an image. Digital gain/offset/clip may be provided for each color channel or component of image data. Color correction may apply a color correction transform matrix to image data. 3D color lookup may utilize a three dimensional array of color component output values (e.g., R, G, B) to perform advanced tone mapping, color space conversions, and other color transforms. Gamma conversion may be performed, for example, by mapping input image data values to output data values in order to perform gamma correction, tone mapping, or histogram matching. Color space conversion may be implemented to convert image data from one color space to another (e.g., RGB to YCbCr). Other processing techniques may also be performed as part of color processing stage312to perform other special image effects, including black and white conversion, sepia tone conversion, negative conversion, or solarize conversion.

Output rescale module314may resample, transform and correct distortion on the fly as the ISP206processes image data. Output rescale module314may compute a fractional input coordinate for each pixel and uses this fractional coordinate to interpolate an output pixel via a polyphase resampling filter. A fractional input coordinate may be produced from a variety of possible transforms of an output coordinate, such as resizing or cropping an image (e.g., via a simple horizontal and vertical scaling transform), rotating and shearing an image (e.g., via non-separable matrix transforms), perspective warping (e.g., via an additional depth transform) and per-pixel perspective divides applied in piecewise in strips to account for changes in image sensor during image data capture (e.g., due to a rolling shutter), and geometric distortion correction (e.g., via computing a radial distance from the optical center in order to index an interpolated radial gain table, and applying a radial perturbance to a coordinate to account for a radial lens distortion). In one embodiment, operations such as rotating and shearing, perspective warping, rolling shutter compensation, are examples of warping operations that may be performed by a warper circuit of the output rescale module314, as will be described herein.

Output rescale module314may apply transforms to image data as it is processed at output rescale module314. Output rescale module314may include horizontal and vertical scaling components. The vertical portion of the design may implement series of image data line buffers to hold the “support” needed by the vertical filter. As ISP206may be a streaming device, it may be that only the lines of image data in a finite-length sliding window of lines are available for the filter to use. Once a line has been discarded to make room for a new incoming line, the line may be unavailable. In one embodiment, the output rescale module314may generate images tiles from image data in the image data line buffers, and store the tiles into memory. The image tiles can then be retrieved to perform warping operations.

Output rescale module314may statistically monitor computed input Y coordinates over previous lines and use it to compute an optimal set of lines to hold in the vertical support window. For each subsequent line, output rescale module may automatically generate a guess as to the center of the vertical support window. In some embodiments, output rescale module314may implement a table of piecewise perspective transforms encoded as digital difference analyzer (DDA) steppers to perform a per-pixel perspective transformation between a input image data and output image data in order to correct artifacts and motion caused by sensor motion during the capture of the image frame. Output rescale may provide image data via output interface316to various other components of device100, as discussed above with regard toFIGS. 1 and 2.

In various embodiments, the functionally of components302through342may be performed in a different order than the order implied by the order of these functional units in the image processing pipeline illustrated inFIG. 3, or may be performed by different functional components than those illustrated inFIG. 3. Moreover, the various components as described inFIG. 3may be embodied in various combinations of hardware, firmware or software.

Example Output Rescale Module

FIG. 4is a block diagram illustrating the circuits of an output rescale module314and its surrounding circuits, according to one embodiment. The output rescale module314may perform a per-pixel perspective transformation between input image data and output image data in order to correct artifacts caused by sensor motion during the capture of the image frame (e.g., input image). In the embodiment shown inFIG. 4, the output rescale module314contains a tiler circuit402, a warper circuit404, and a grid generator406.

The tiler circuit402receives image data for an input image401from the color processing stage312and generates a tiled version of the input image to store in memory408. The input image401can be in a format such as YCbCr 4:2:2, and the embodiments described herein will assume that the image format is YCbCr 4:2:2. However, in other embodiments the image can be in YCbCr 4:4:4 or other appropriate image formats.

The input image401can have a high resolution and is divided by the tiler circuit402into many different image tiles421. Each image tile is an M×N rectangular array of image samples from the input image with M pixel samples in the horizontal direction and N pixel samples in the vertical direction. M is an integer greater than 1 but smaller than the horizontal resolution of the input image401. N is an integer greater than 1 but smaller than the vertical resolution of the input image. In one embodiment, the input image421is in the YCbCr 4:2:2 format and has a resolution of 4608×2592. The luma data of the input image421can be divided into 32×4 image tiles421, thereby resulting in 93,312 image tiles for the luma data of the input image421. Additionally, the chroma data of the input image can be divided into 32×4 image tiles421, thereby resulting in 93,312 image tiles421for the chroma data.

In one embodiment, the memory408is dynamic random access memory (DRAM). The memory408can be located in an IC chip that is separate from the IC chip that the output rescale module314is located on. For example, the memory408can represent one or more dedicated DRAM memory chips. The memory408may be the same as system memory230shown inFIG. 2. In other embodiments, the output rescale circuit314and the memory408can be located within the same IC chip.

The memory408allows data to be written to and read from the memory408during a memory access transaction. Due to hardware constraints, the number of bytes transferred in a single memory access transaction is typically a fixed number of bytes. For example, if the interface to the memory408is 128 bits wide and the burst length of a memory access transaction is 8 bits, then the fixed size of the memory access transaction is 8×128=1024 bits=128 bytes.

The grid generator406generates a mesh grid407. The mesh grid407represents a mapping of pixel coordinate locations from the input image401to pixel coordinate locations in the output image411. The grid generator406can generate the mesh grid by reading the grid from a memory, or it can generate the mesh grid in other ways.

The warper circuit404retrieves the image tiles421from memory408in accordance with the mesh grid. The warper circuit404uses the image tiles422to perform a warping transformation of the input image401into the output image411(e.g., warped image) that is subsequently sent to the output interface316. Using the image tiles421to perform warping allows the warper circuit404to correct for large amounts of image distortion without increasing the size of the buffer in the warper circuit404, as will be explained herein. The warper circuit can also operate in a streaming mode, in which the warper circuit404receives the input image401line by line from the color processing stage312via the streaming path410, bypassing the tiler circuit402.

FIG. 5is a block diagram illustrating a tiler circuit402, according to one embodiment. In the embodiment shown inFIG. 5, the tiler circuit402includes a luma tiler circuit502, a luma tile buffer504, a chroma tiler circuit508, and a chroma tile buffer510. The tiler circuit402receives input image data for an input image401that includes luma data520and chroma data521. The tiler circuit402reformats the luma data520into luma tiles602and reformats the chroma data521into chroma tiles604. The luma tiles602and the chroma tiles604are examples of the image tiles421fromFIG. 4. In one embodiment, image tiles421may be compressed and stored in memory408in a compressed format. In another embodiment, the image tiles421may be stored in an uncompressed format.

The luma tiler circuit502receives full-resolution luma data as input and divides the luma data520into luma tiles530to be stored in memory.FIG. 6illustrates a luma tile602, according to one embodiment. As shown inFIG. 6, each luma tile contains 128 luma samples (e.g., Y(0,0) to Y(3,31)) that are arranged into a 32×4 memory tile configuration comprising 128 bytes of memory. A single luma tile602is stored into the memory408during a single memory access operation. Thus, the size of the luma tile602is equivalent to the amount of data that can be transferred during a single memory access operation to the memory408. This allows the tiles to be written to and read from the memory408as efficiently as possible.

In order to assemble these tiles, the luma tiler circuit502uses a luma tile buffer504that is equivalent to four 4,608-pixel lines divided into 16 quarter-line segments. The replacement policy for the luma tile buffer504is discussed further in reference toFIG. 7below.

The chroma tiler circuit508receives chroma data521(e.g., chroma data from a 4:2:2 input image) as input and reformats the chroma data521into chroma tiles604to be stored in memory408.FIG. 6illustrates a chroma tile604, according to one embodiment. As shown inFIG. 6, each chroma tile604contains 64 Cb/Cr pairs (e.g., Cb(0,0)/Cr(0,0) to Cb(3,15)/Cr(3,15)) that are arranged into a 32×4 memory tile configuration comprising 128 bytes of memory. A single chroma tile604is stored into the memory408during a single memory access operation. Thus, the size of the chroma tile604is equivalent to the amount of data that can be transferred during a single memory access operation to the memory408. To tile the image, the chroma tiler circuit508uses the chroma tile buffer510that is similar to the luma tile buffer504in size and replacement policy.

FIG. 7illustrates a tile buffer replacement policy702, according to one embodiment. It should be noted that this replacement policy applies to, both, the luma tile buffer504and chroma tile buffer510. Therefore, discussion of the tile buffer replacement policy702will be conducted generically for the purposes of this illustration.

The size of the tile buffer504is substantially smaller than the size of the input image. In one embodiment, substantially smaller means that the tile buffer504can only store less than 10% of the input image401. Because of the small size of the tile buffer504, the entire input image401may not fit into the tile buffer504. The tile buffer replacement policy702provides a technique for efficiently using the small tile buffer504while still allowing tiling operations to occur.

As shown inFIG. 7, the tile buffer504is equivalent to four 4,608-pixel lines in size, and is divided into 16 segments across lines A through D. For lines A, B, and C, the tile buffer504is written to in a linear format, beginning with segment A-M to A-P, and ending with segments C-M to C-P. When segments D-M to D-P are written to, as illustrated in step704, the tile buffer is full because it now stores four lines of the input image401for a subset of the input image401. Once full, column M is evicted from the tile buffer504and is written to memory one tile at a time. Because the tile buffer is 4,608 samples wide and 4 samples tall, each column in the luma tile buffer504contains 36 luma tiles. Similarly, each column in the chroma tile buffer510contains 36 chroma tiles composed of 72 Cb/Cr pairs.

When column M is written to memory, the tile buffer504repopulates column M with the next line of luma data520from the input image, as shown in step706. Column N is also written to memory one tile at a time. The tile buffer then repopulates column N as shown in step708. Additionally, columns O and P are evicted and repopulated with new lines of image data as shown in steps710and712, respectively.

When column P is written to, the tile buffer is full because it now stores four new lines of the input image401for a subset of the input image401. Row A is then evicted/repopulated as shown in step714. Similarly, rows B and C are written to memory408and repopulated as illustrated in step716and718, respectively. This pattern repeats with the eviction/repopulation of row D in step704, and continues alternating between horizontal and vertical output (e.g., evicting rows and writing new lines of image data to the rows, then evicting columns and writing new lines of image data to the columns) until the input image has been completely tiled and stored in memory.

FIG. 8is a block diagram illustrating a warper circuit404, according to one embodiment. The warper circuit404reads image tiles421from memory408based on a mesh grid generated by the grid generator406, and performs a warping transformation on the image tiles421to produce an output image411. The warper circuit404has two modes of operation. A streaming mode is used when the warper circuit404is receiving pixels directly from the color processing stage312or another streaming source (e.g., bypassing the tiler circuit402). The warper circuit404operates in tiled mode when the image source consists of image tiles421written to memory408by the tiler circuit402. In the tiled mode, the warper circuit404can read image tiles421directly from memory408in a non-raster order (i.e., read from memory in any order, not necessarily line by line) to facilitate more warping. In the embodiment illustrated inFIG. 8, the warper circuit includes a grid buffer802, an image buffer804, a memory access circuit806, grid interpolators818, a vertical filter812, and a horizontal filter816. The grid interpolators818include two vertical grid interpolators808and810, and a horizontal grid interpolator814.

The grid buffer802stores pixel coordinate mappings of the mesh grid407and provides the pixel coordinate location mappings to the two vertical grid interpolators808and810throughout the warping process. The mesh grid can be a coarse grid that does not include pixel coordinate location mappings for each coordinate of the output image411, but instead only includes pixel coordinate location mappings for one in every 1,024 pixels of the output image411(e.g. each pixel coordinate location mapping is separated from the next pixel coordinate location mapping by 32 pixels in the horizontal direction and by 32 pixels in the vertical direction). In one embodiment, the grid buffer802can store four lines of the mesh grid, where each line is a maximum of 145 grid points in width. Other embodiments may include coarser or finer mesh grids, non-square mesh grids, irregular mesh grids (e.g., different mesh grid sizes for different portions of the output image411), or a per-pixel mesh grid.

The grid interpolators818perform interpolation of input coordinates of an input grid mesh produced by the grid generator406. The grid interpolators818trace the grid mesh in raster order (i.e., horizontally on a line by line basis) and compute a fractional input Y coordinate for each integral X coordinate, and fetch a new pair of grid coordinates from the grid buffer802for every 32 pixels of output. The grid interpolators818include a vertical grid interpolator808, a second vertical grid interpolator810, and a horizontal grid interpolator814. Vertical grid interpolator808is used to drive the memory access circuit806, which formats memory access requests to fetch additional image tiles from memory408for storage in the image buffer804. Vertical grid interpolator810is used to drive the vertical filter812. Both vertical grid interpolators808and810produce the same interpolation results but do so at different times. Vertical grid interpolator808basically pre-generates pixel coordinate locations of the input image916so that image tiles421at those coordinates can be pre-fetched into the image buffer804. At a later point in time, the vertical grid interpolator810generates the same coordinates of the input image916and requests processing on the image tiles421at those coordinates, which are already pre-fetched into image buffer804.

The horizontal grid interpolator814computes horizontal interpolations of input coordinates to be passed to the horizontal filter816using the grid coordinates generated by the vertical grid interpolator810. This interpolation process will be discussed in greater detail inFIGS. 9A and 9B.

The warper circuit404includes an image buffer804that is used for facilitating the warping process in both streaming and tiled modes. The size of the image buffer804is smaller than the size of the input image. In one embodiment, substantially smaller means that the buffer804can only store less than 10% of the input image401. The image buffer804can include 12 line buffers, where each line buffer is 4,608 samples in width, used to temporarily store image tiles read from memory. In tiled mode, each image tile421is written to exactly one location in the image buffer804. Because each image tile421retrieved from memory408is 32×4 samples, the image buffer804can accommodate 144 columns and 3 rows of tiles in tiled mode. Within each respective tile column, the 3 rows of tiles act as a sliding-window within that column.

In streaming mode, twelve line buffers within an image buffer804provide a unified sliding-window that spans the 4,608 pixel width of the image buffer804. Each pixel of the original input image is mapped directly to an input line of the buffer. In both modes, the line buffers within an image buffer804can be folded up to a factor of 4, trading off the width of a sliding-window for vertical support during the warping process.

The vertical filter812filters each column of the sliding-window with a 9-tap vertical polyphase filter. The vertical filter812reads image tiles from the image buffer804to produce a stream of vertically-filtered pixels that it passes directly to the horizontal filter816for 9-tap horizontal polyphase filtration. If a requested image tile is unavailable in the image buffer804, the vertical filter812will stall until the image tile is available.

FIG. 9Aillustrate a warping process, according to one embodiment. In the embodiment illustrated inFIG. 9A, the warper circuit404performs a piecewise image warp from an input image916(e.g, image containing unintended distortion) to an output image918(e.g., corrected image). The mesh grid407controls the nature of the underlying warping transformation. Most sample locations of the output image918map to a bilinearly interpolated (e.g., vertical and horizontal interpolation) input coordinate of the input image916. The grid interpolators818step through the mesh grid407in raster order, generating the input coordinates associated with each output coordinate by interpolating the input coordinates stored in the grid buffer802. For example, output coordinates910,912, and914map to input coordinates904,906, and908, respectively. The grid interpolators818step through each line of the mesh grid407vertically, and for each line the range of input X coordinates associated with the line is computed from the mesh grid. This range of X coordinates is rounded to integral input pixel coordinates. The grid interpolators818then step through the input image916horizontally, and at each point the corresponding fractional input Y value is computed from the mesh grid407coordinates for use by the vertical filter812. In addition to computing the Y value, the grid interpolators818also compute a fraction X input coordinate while stepping horizontally through the input image916. This X input coordinate is used by the horizontal filter816to select a filtering position.

FIG. 9Billustrates a warping process in both streaming mode926and tiled mode938, according to one embodiment. Both modes use 12 line buffers within an image buffer804(with a maximum input width of 4,608 pixels) to cache a region of the input image. In the streaming mode926, the image buffer804presents a sliding-window consisting of 11 lines (one line is needed for input buffering in streaming mode926) spanning the entire width of the input image. This sliding-window is illustrated inFIG. 9Bbetween lines920and924. Because there are only 11 lines available in the sliding-window rather than 12, the amount of vertical deflection that the warper circuit404is able to perform is limited. Thus, the warper circuit404is only able to correct for slight distortions (e.g.,920). In tiled mode938, the image buffer804can accommodate 144 columns and 3 rows of 32×4 image tiles. Within each respective tile column, the 3 rows of tiles act as a sliding-window within that column. These columns are shown inFIG. 9Bas the distorted image936is partitioned into columns928,930, and934, containing 1 tile, 2 tiles, and 3 tiles, respectively.