Vertical double diffused MOSFET and method of fabricating the same

In a DMOS device, a drift region is located over a substrate and is lightly doped with impurities of a first conductivity type. A plurality of body areas are located in the drift region and doped with impurities of a second conductivity type which is opposite the first conductivity type. A plurality of source areas are respectively located in the body areas and heavily doped with impurities of the first conductivity type. A plurality of bulk areas are respectively located adjacent the source areas and in the body areas, and are heavily doped with impurities of the second conductivity type. A well region partially surrounds the body areas collectively and is doped with impurities of the first conductivity.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is generally directed to semiconductor devices and to methods of fabricating the same. More specifically, the present invention is directed to vertical double diffused metal oxide semiconductor (VDMOS) devices and to methods of fabricating the same.

2. Background of the Invention

In integrated circuit (IC) products, such as hard disk drives (HDD), video tape recorders (VTR), and so forth, double-diffused metal oxide semiconductor (DMOS) devices are widely used in power conversion and control systems requiring high-power transfer and high-speed switching.

Advantageously, DMOS devices exhibit a high-speed switching characteristic, even when operating at a low gate voltage, while having a relatively low on-resistance and a high breakdown voltage. The low-voltage input terminal of the DMOS device results in minimal power consumption.

FIG. 1Ais a cross-sectional view of a conventional DMOS device, andFIG. 1Bis a top plan view thereof. Particularly,FIG. 1Ais cross-sectional view taken along a line I-I′ of FIG.1B.

Referring to FIG.1A andFIG. 1B, an N-type buried layer4is formed at a semiconductor substrate2. A drift region6, which is lightly doped with N-type impurities, is epitaxially formed on the buried layer4and the substrate2.

A plurality of P-type body areas26are formed at predefined areas of the drift region6. A loop-shaped source area30, which is heavily doped with N-type impurities, and a P-type bulk area36, which is surrounded by the source area30, are formed in each body area26.

A sink area8is spaced from the outermost body areas26, and is electrically connected to the buried layer4through the drift region6. Between the sink area8and the outermost body area26, a field oxide layer16is formed in contact with the sink area8.

A drain area32, which is heavily doped with N-type impurities, is formed on the sink area8. The drain area32is loop-shaped and has a predetermined width, as shown in FIG.1B. In the drain area32, drain contacts40are formed at a constant spacing. The drain area32is connected to a drain electrode (not shown) through the drain contacts40.

A gate electrode20is formed over a gate insulating layer18and the drift region6, and is interposed between and partially overlaps the body areas26. The gate electrode20is made of polysilicon. Also, an outer edge of the gate electrode partially overlaps the field oxide layer16. The gate electrode20has a mesh-shaped structure in which a plurality of openings22are formed, as shown inFIG. 1B. Asource contact38is formed in the respective openings22of the gate electrode20. The source area30and the bulk area36are connected to a source electrode (not shown) through the source contact38.

Returning toFIG. 1A, when a predetermined voltage is applied to a drain electrode and a gate electrode, electrons migrate from the source area30to a drain area32through a channel area45, an accumulation region47, the drift region6, the buried layer4, and the sink area8.

Important electrical characteristics of the VDMOS device are an ON-resistance and a breakdown voltage. Here, the “ON-resistance” is the source-to-drain resistance when a transistor of the device is turned on.

The breakdown voltage is affected by the doping densities of the body area26and the drift region6, and is structurally affected by the outermost body area26and the field oxide layer16.

Reference is made toFIG. 1Cfor an explanation as to why the outermost body area26significantly affects the breakdown voltage. When the device operates at a high voltage, a depletion region55is formed at a P-N junction between the body area26and the drift region6. The depletion region55is somewhat planar between the body areas26, while having a curvature portion60outside the outermost body area26. When a high voltage is applied to the DMOS device, an electric field concentrates on the curvature portion60. Thus, the outermost body area26is vulnerable to a breakdown voltage. InFIG. 1C, the reference numeral and symbols ‘42’, ‘D’, ‘S’, and ‘G’ represent an interlayer insulating film, a drain electrode56, a source electrode57, and a gate electrode20, respectively.

An effective way to improve the ON-resistance is to increase a doping density of the drift region6to thereby reduce a resistance at the drift region6. Unfortunately, this lowers the breakdown voltage. In the meantime, if the doping density of the drift region6is lowered to thereby increase the breakdown voltage, the ON-resistance is increased.

In other words, when setting of the doping density of the drift region6, there is a trade-off between increasing the doping density to obtain a low ON-resistance and decreasing the doping density to obtain a high breakdown voltage.

SUMMARY OF THE INVENTION

In view of the foregoing, the present invention provides a DMOS device which has a relatively low ON-resistance while maintaining a stable breakdown voltage, and a method of fabricating the same.

According to an aspect of the invention, a DMOS device includes a drift region which is located over a substrate and which is lightly doped with impurities of a first conductivity type. A plurality of body areas are located in the drift region and doped with impurities of a second conductivity type which is opposite the first conductivity type. A plurality of source areas are respectively located in the body areas and heavily doped with impurities of the first conductivity type. A plurality of bulk areas are respectively located adjacent the source areas and in the body areas, and are heavily doped with impurities of the second conductivity type. A well region partially surrounds the body areas collectively and is doped with impurities of the first conductivity.

According to another aspect of the invention, a DMOS device includes a drift region which is located over the substrate and lightly doped with impurities of a first conductivity type. A plurality of body areas are located in the drift region and doped with impurities of a second conductivity type which is opposite the first conductivity type. A plurality of source areas are respectively located in the body areas and heavily doped with impurities of the first conductivity type. A plurality of bulk areas respectively are surrounded by the source areas and located in the body areas, and heavily doped with impurities of the second conductivity type. A well region partially surrounds the body areas collectively and is doped with impurities of the first conductivity. A buried layer of the first conductively type is interposed between the substrate and the drift region. A gate electrode has a plurality of openings respectively aligned over the source areas and the bulk areas, and a gate insulating layer is interposed between the drift region and the gate electrode. A sink area of the first conductivity type is connected to the buried layer through the drift region, and a drain area of the first conductivity type is located on the sink area.

According to still another aspect of the invention, a method of fabricating a DMOS device is provided which includes forming a drift region over a substrate, the drift region being lightly doped with impurities of a first conductivity type. A well of the first conductivity type is formed in an area of the drift region, and a plurality of body areas of a second conductivity type are formed in the drift region, where at least one of the body areas is formed across an edge of the well so as to be partially formed in the well and partially formed outside the well. A source area is formed in each of the body areas, the source areas being heavily doped with impurities of the first conductivity type, and a bulk area is formed in each of the body areas, the bulk areas being heavily doped with impurities of the second conductivity type and surrounded by the source areas.

According to yet another aspect of the present invention, a method of fabricating a DMOS device is provided which includes forming a heavily doped buried layer of a first conductivity type at an area of a substrate. A drift region of the first conductivity type is formed over the buried layer. A sink area of the first conductivity type is formed which is connected to the heavily doped buried layer through the drift region. A well of the first conductivity type is formed at an area of the drift region. A gate insulating layer and gate electrode are formed over the drift region, the gate electrode and gate insulating layer having a plurality of openings which expose areas of the drift region. A plurality of body areas are formed at the exposed areas of the drift region, wherein at least one of the body areas is formed across an edge of the well so as to be partially formed in the well and partially formed outside the well. A plurality of heavily doped sources areas of the first conductivity type are formed in the body areas. A drain area of the first conductivity type is formed in the sink area, and a plurality of heavily doped bulk areas of the second conductivity type are formed in the body areas, the bulk areas being surrounded by the source areas.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 2Ais a cross-sectional view of a DMOS device according to a preferred embodiment of the present invention, andFIG. 2Bis a top plan view thereof. Particularly,FIG. 2Ais a cross-sectional view taken along a line II-II′ of FIG.2B. In this embodiment, an N-type DMOS device is illustrated by way of example.

Referring to FIG.2A andFIG. 2B, a buried layer104, which is heavily doped with N-type impurities, is formed over a P-type substrate102. An N-type drift region106is formed on the buried layer104by means of conventional epitaxial growth.

A plurality of P-type body areas126are formed at a predefined areas of the drift region106. A loop-shaped source region130, which is heavily doped with N-type impurities, and a bulk area136, which is heavily doped with P-type impurities, are formed in the body area126.

An N-type well110includes at least a portion of the body areas126and is formed at the drift region106. Preferably, an edge of the N-type well110partially overlaps the outermost body areas126. However, the edge does not extend to a curvature portion160on which an electric filed concentrates. A doping density of the body area126is varied by the well110. An outer body area126a, which does not overlap the well110, has a relatively high doping density as compared to an inner body area126boverlapping the well110.

A sink area108is formed apart from the outermost body areas126, and is electrically connected to the buried layer104through the drift region106. A field oxide layer116is formed between the sink area108and the outermost body area126. The field oxide layer116is adjacent to the sink area108.

A drain area132is heavily doped with N-type impurities and is formed on the sink area108. The drain area132is loop-shaped with a constant width, as shown inFIG. 2B. Aplurality of drain contacts140are formed at the drain area132, and are connected to a drain electrode (not shown).

Returning toFIG. 2A, when a constant voltage is equivalently applied to a drain electrode and a gate electrode, electrons migrate from the source area130to the drain region132through a channel area145, an accumulation region147, the drift region106, the buried layer104, and the sink area108.

In the DMOS device, the separate N-type well110is formed to surround the innermost body areas126and to partially overlap the outermost body areas126. Due to the presence of the N-type well100, resistances of the accumulation region147and the drift region106are lowered. Thus, the overall ON-resistance is also lowered. A breakdown voltage is not affected because the N-type well does not overlap the curvature outside the outermost body area. As a result, the breakdown voltage is not affected while lowering the ON-resistance. However, if the doping density of the N-type well110is too high, a breakdown may be generated between the body area126boverlapping the N-type well110and the drift region106. Therefore, it is desirable that the doping density of the N-type well110is higher than that of the drift region106and lower than that of the source region130.

A method of fabricating a vertical DMOS device according to a preferred embodiment of the present invention will now be described with reference to FIG.3A through FIG.3I. In this embodiment, an N-type DMOS device is exemplarily described.

Referring toFIG. 3A, N-type impurities are implanted into a predetermined area of a P-type substrate102. For example, phosphorous (P), arsenic (As) or antimony (Sb) ions may be implanted at a flux density of 1×1014/cm2˜5×1015/cm2.

A drift region106which is lightly doped with N-type impurities is formed on the heavily doped N-type substrate102by conventional epitaxial growth. Heavily doped N-type impurities are diffused to an overlying layer to form an N-type buried layer104, as shown in FIG.3A.

Referring toFIG. 3B, a predetermined region of the drift region106is heavily doped by diffusion of N-type impurities to form a sink area108which is electrically connected to the N-type buried layer104through the drift region106. For example, phosphorous (P), arsenic (As) or antimony (Sb) ions may be implanted at a flux density of 1×1014/cm2˜5×1015/cm2.

Referring toFIG. 3C, a predetermined area of the drift region106is doped with N-type impurities. That is, the N-type impurities are diffused to form an N-type well110. The N-type well110serves to lower an ON-resistance by increasing a doping density of the predetermined area of the drift region106. For example, phosphorous (P), arsenic (As) or antimony (Sb) ions may be implanted at a flux density of 5×1011/cm2˜5×1013/cm2.

Referring toFIG. 3D, a pad oxide layer112and a silicon nitride layer114are formed on the drift region106where the sink area108and the N-type well110are formed. The silicon nitride layer114adjacent to the sink area108is removed to form an opening113.

Referring toFIG. 3E, a semiconductor substrate is thermally oxidized to form a field oxide layer116in the opening113to a thickness of 1000 angstroms to 10000 angstroms. Thereafter, the silicon nitride layer114and the pad oxide layer112are removed. The field oxide layer114prevents a breakdown voltage from being lowered by the density of an electric field.

Referring toFIG. 3F, a gate insulating layer118and a gate conductive layer are formed on an entire surface of the semiconductor substrate including the field oxide layer116. Using a photolithographic process, the gate insulating layer118and the gate conductive layer are patterned to form a gate electrode120having a mesh-shaped opening122. An edge of the gate electrode120partially overlaps the field oxide layer118.

Referring toFIG. 3G, using a photoresist pattern124and the gate electrode120as an ion implanting mask, P-type impurities are implanted into the respective openings122formed between the gate electrodes120to form body areas126. The photoresist pattern124is formed by a conventional photolithographic process. For example, boron (B), boron fluoride (BF2) or indium (In) ions may be implanted at a flux density of 1×1012/cm2˜9×1013/cm2.

The body area126is formed in the previously formed N-type well110. Further, an outermost body area is divided into a body area126bformed in the N-type well and a body area126aformed in the drift region106according to their doping densities. Since a doping density of the N-type well110is higher than that of the drift region106, the doping density of the body area126ais relatively higher than that of the body area126b. Consequently, the body area126bis maintained at the same breakdown voltage characteristic as a conventional device, while the body area126bhas a low threshold voltage Vth because its doping density is lower. Therefore, since a resistance of a channel area is lowered, and the ON-resistance is also lowered.

Referring toFIG. 3H, following removal of the photoresist pattern124, a predetermined diffusion process is carried out to form a body area126.

A conventional photolithographic process is performed to form a photoresist pattern128defining a source area and a drain area. Using the photoresist pattern128, the gate electrode120, and the field oxide layer116as an ion implanting mask, N-type impurities are heavily doped to form a source area130in the body area126and concurrently to form a drain area132in the sink area108. For example, phosphorous (P), arsenic (As) or antimony (Sb) ions may be implanted at a flux density of 1×1014/cm2˜5×1016/cm2.

Referring toFIG. 3I, following removal of the photoresist pattern128, the photolithographic process is re-performed to form a photoresist pattern134defining a bulk area. Using the photoresist pattern134as an ion implanting mask, a P-type bulk area126is formed. For example, boron (B), boron fluoride (BF2) or indium (In) ions may be implanted at a flux density of 1×1012/cm2˜9×1013/cm2.

Following removal of the mask pattern134, an annealing process is performed to form a DMOS structure shown in FIG.2A.

An interlayer insulating film (not shown) is formed on an entire surface of a substrate. The interlayer insulating film is patterned by a photolithographic process to form a source contact138and a drain contact140shown in FIG.2B. The source area130and the bulk area136are connected to a source electrode (not shown) through the source contact138. The drain area132is connected to a drain electrode (not shown) through the drain contact140.

The above embodiments, which are described as examples of the present invention, should not be construed as limiting of the invention. Various modifications or alterations can be easily made to the disclosed embodiment by those skilled in the art without departing from the scope of the present invention.