WAFER-LEVEL PACKAGING STRUCTURE AND METHOD FOR PREPARING SAME

A wafer-level packaging structure and a method for preparing the same are provided, the wafer-level packaging structure includes at least a molding layer and a 3D IPD structure fabricated in the molding layer. The wafer-level packaging structure of the present disclosure can integrate various electronic chips and components such as millimeter wave antenna/capacitor/inductor/electric crystal/GPU/PMU/DDR/flash memory/filter, etc., with higher flexibility and wider compatibility, thus reducing package size and package cost.

CROSS REFERENCE TO RELATED APPLICATION

The present application claims the benefit of priority to Chinese Patent Application No. CN 202210955805.6, entitled “WAFER-LEVEL PACKAGING STRUCTURE AND METHOD FOR PREPARING SAME”, filed with CNIPA on Aug. 10, 2022, the disclosure of which is incorporated herein by reference in its entirety for all purposes.

FIELD OF THE INVENTION

The present disclosure generally relates to the field of semiconductor packaging technology, and in particular, relates to a wafer-level packaging structure and a method for preparing the same.

BACKGROUND OF THE INVENTION

As electronic products such as computers, tablets, mobile phones, car controls, household appliance controls, and Internet of things (IoT) objects have become smaller, faster, more energy-efficient and higher-performing, there is an increasing demand for the miniaturization and integration of chips on these objects. Packaging more functional modules onto a single die has become an important trend in semiconductor packaging.

To achieve product integration, active devices like switches, low noise amplifiers, power amplifiers, basebands, and application processors are integrated onto a single die. Additionally, more wafer-level packaging requires the introduction of RF Integrated Passive Devices (IPDs) like filters to reduce the size of RF modules.

Most related technologies use planar IPDs. Since these IPDs are formed on a 2D plane parallel to the silicon substrate, they can't meet the integration requirements of RF packaging structures or packaging performance, especially at high frequencies.

In related technology, independent IPDs can also be fixed to the substrate using flip-chip bonding or wire bonding. Using these methods to introduce IPDs requires additional packaging space and may cause deterioration of IPD performance due to the introduction of solder balls or wire bonding.

Therefore, integrating 3D IPDs into wafer-level packaging structures is a challenge that needs to be addressed by technical professionals in this field.

SUMMARY OF THE INVENTION

The present disclosure provides a wafer-level packaging structure, including a molding layer, and a 3D IPD structure fabricated in the molding layer, wherein the molding layer includes a first surface and a second surface opposite to the first surface.

The present disclosure further provides a method for preparing a wafer-level packaging structure, including: preparing a molding layer; and forming a 3D IPD structure inside the molding layer.

The wafer-level packaging structure of the present disclosure can integrate various electronic chips and components such as millimeter wave antenna/capacitor/inductor/electric crystal/GPU/PMU/DDR/flash memory/filter, etc., with higher flexibility and wider compatibility, thus reducing package size and package cost.

REFERENCE NUMERALS

DETAILED DESCRIPTION

The embodiments of the present disclosure will be described below. Those skilled can easily understand disclosure advantages and effects of the present disclosure according to contents disclosed by the specification. The present disclosure can also be implemented or applied through other different exemplary embodiments. Various modifications or changes can also be made to all details in the specification based on different points of view and applications without departing from the spirit of the present disclosure.

Refer toFIGS.1-9. It should be noted that the drawings provided in this disclosure only illustrate the basic concept of the present disclosure in a schematic way, so the drawings only show the components closely related to the present disclosure. The drawings are not necessarily drawn according to the number, shape, and size of the components in actual implementation; during the actual implementation, the type, quantity, and proportion of each component can be changed as needed, and the components' layout may also be more complicated.

The present disclosure provides a wafer-level packaging structure, as shown inFIGS.7,8and9, and the wafer-level packaging structure includes a molding layer1and a 3D IPD structure fabricated in the molding layer1.

As an example, a material of the molding layer1includes one or more of epoxy-based resin, liquid thermosetting epoxy resin, and plastic molding compound, and techniques of forming the molding layer1include one of compression molding, transfer molding, liquid seal potting molding, vacuum lamination, and spin coating. A thickness of the molding layer1ranges from 10 um to 200 um, for example, it can be 30 um, 50 um, 80 um, 100 um, 150 um, 180 um, etc.

As an example, the 3D IPD structure includes one or more of a 3D inductive IPD structure21, a 3D capacitive IPD structure22, and a 3D resistive IPD structure.

In one example, as shown inFIGS.7and8, the molding layer1includes a first surface and a second surface opposite to the first surface, and the 3D inductive IPD structure21includes first metal solder pads211, metal pillars212, and second metal solder pads213. Specifically, as an example, the first surface is the bottom surface of the molding layer1, and the second surface is the top surface of the molding layer1. The first metal solder pads211are formed inside the molding layer1and extend inwards from the first surface of the molding layer1; the metal pillars212are formed inside the molding layer1and located over ends of the first metal solder pads211; the second metal solder pads213are formed on the molding layer1and extend outwards from the second surface of the molding layer1; the second metal solder pads213connect the metal pillars212in series, with each of the second metal solder pads213connecting two of the metal pillars212that are respectively located over two adjacent first metal solder pads211, forming a 3D inductive IPD structure21.FIG.7is a cross-sectional view andFIG.8is a three-dimensional view of the structure.

As an example, a material of the first metal solder pads211includes, but is not limited to, copper. Techniques of forming the first metal solder pads211include one of physical vapor deposition, chemical vapor deposition, sputtering, electroplating, and chemical plating. As an example, the first metal solder pads211are arranged parallel to each other.

As an example, the metal pillar212includes one of a copper pillar and a titanium pillar, and the method for forming the metal pillar212includes one of physical vapor deposition (PVD), chemical vapor deposition (CVD), sputtering, electroplating, and chemical plating.

As an example, a material of the second metal solder pads213includes, but is not limited to, copper. Techniques of forming the second metal solder pads213include one of physical vapor deposition, chemical vapor deposition, sputtering, electroplating, and chemical plating. As an example, the second metal solder pads213are arranged parallel to each other.

As an example, as shown inFIG.9, the 3D capacitive IPD structure22includes at least one pair of metal layers221formed in the molding layer1parallel to each other, wherein each pair of the at least one pair of metal layers221is in a plane perpendicular to the first and second surfaces the molding layer1.

Although only a 3D inductive IPD structure21and a 3D capacitive IPD structure22are described, in other embodiments there may be other 3D IPD structures in the packaging structure.

As an example, as shown inFIG.10andFIG.12, the wafer-level packaging structure further includes a first rewiring layer3formed on the first surface of the molding layer1and a second rewiring layer4formed on the second surface of the molding layer1, wherein the first rewiring layer3includes a first dielectric layer31and a first wiring metal layer32formed in the first dielectric layer31, wherein the second rewiring layer4includes a second dielectric layer41and a second wiring metal layer42formed in the second dielectric layer41and connected to the 3D IPD structure2.

The first wiring metal layer32and the second wiring metal layer42are not shown inFIG.10.

As an example, materials of the first dielectric layer31and the second dielectric layer41include at least one of epoxy resin, silicone, polyimide, polybenzoxazoles, benzocyclobutene, silicon oxide, phosphor silica glass, fluorine containing glass, and other suitable materials.

As an example, materials of the first wiring metal layer32and the second wiring metal layer42include at least one of copper, aluminum, and titanium. Techniques of forming the first wiring metal layer32and the second wiring metal layer42include one of physical vapor deposition, chemical vapor deposition, sputtering, electroplating, and chemical plating, The first wiring metal layer32and the second wiring metal layer42are single-layer or multiple-layer structures.

The wafer-level packaging structure may also include other structural layers to form different types of wafer-level packaging structures.

As an example, as shown inFIG.11, the wafer-level packaging structure is an RF ASIC wafer-level packaging structure, and further includes an RF ASIC chip9and solder balls8. The RF ASIC chip9is formed on a surface of the second rewiring layer4and is connected to the second wiring metal layer (not shown); the solder balls8are formed on a surface of the first rewiring layer3and are connected to the first wiring metal layer (not shown).

As another example, as shown inFIG.13, the wafer-level packaging structure is a fan-out wafer-level packaging structure, and further includes metal connection pillars5, chips6, and solder balls7. The metal connection pillars5are formed in the molding layer1and are connected to the first wiring metal layer32and the second wiring metal layer42; the chips6are soldered to the second rewiring layer4and are connected to the second wiring metal layer42; the solder balls7are formed on a surface of the first rewiring layer3and are connected to the first wiring metal layer32.

Material of the solder balls7,8include, but are not limited to, copper or nickel. The first wiring metal layer32may have solder balls7,8directly formed on its surface, or may have metal pillars (not shown) formed thereon first and then have solder balls7,8formed on the metal pillars.

It should be noted that the wafer-level packaging structure of the present disclosure can serve as an RF ASIC wafer-level packaging structure or a fan-out wafer-level packaging structure, and it can also serve as any other packaging structure that requires the integration of a 3D IPD structure.

The present disclosure also provides a method for preparing a wafer-level packaging structure, using which the above-mentioned wafer-level packaging structure can be obtained. The method includes: first preparing a molding layer1; and forming a 3D IPD structure2in the molding layer.

As an example, the 3D IPD structure includes one or more of a 3D inductive IPD structure21, a 3D capacitive IPD structure22, and a 3D resistive IPD structure. Depending on the specific packaging type, the 3D IPD structure2can also be other suitable passive devices.

As an example, the 3D IPD structure2is a 3D inductive IPD structure21, and forming the 3D inductive IPD structure21in the molding layer1may include the steps described below.

First, providing a substrate10having a release layer11as shown inFIG.1, and then forming first metal solder pads211on a surface of the release layer11as shown inFIG.2.

As an example, the substrate10includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate. In one example, the substrate10is a semiconductor substrate, such as a silicon wafer. The shape of the substrate10may be round, square or any other desired shapes. In one example, the substrate10is used to prevent structural layers above it from cracking, warping, breaking, etc. during subsequent manufacturing processes.

The release layer11is used to subsequently separate the substrate10from the molding layer1and the first metal solder pads211. The release layer11includes one of a tape layer and a polymer layer, which is applied to the substrate10by spin coating and then cured by laser curing, ultra-violet (UV) curing, or thermal curing.

As an example, a material of the first metal solder pads211includes, but is not limited to, copper. Techniques of forming the first metal solder pads211include one of physical vapor deposition, chemical vapor deposition, sputtering, electroplating, and chemical plating. As an example, the first metal solder pads211are arranged parallel to each other.

Then, as shown inFIG.3, metal pillars212are formed over ends of the first metal solder pads211. Specifically, each of the first metal solder pads includes two distal ends, and a metal pillar is formed over each of the distal ends.

As an example, the metal pillar212includes one of a copper pillar and a titanium pillar, and the method for forming the metal pillar212includes one of the processes such as physical vapor deposition (PVD), chemical vapor deposition (CVD), sputtering, electroplating, and chemical plating.

Next, a molding layer1covering the metal pillars212and the first metal solder pads211is formed over the release layer11, as shown inFIG.4; then the molding layer1and the metal pillar212are thinned, as shown inFIG.5.

As an example, a material of the molding layer1includes one or more of epoxy-based resin, liquid thermosetting epoxy resin, and plastic molding compound, and techniques of forming the molding layer1include one of compression molding, transfer molding, liquid seal potting molding, vacuum lamination, and spin coating. The molding layer1as shown inFIG.4undergoes thinning and grinding processes to expose the top surfaces of the metal pillars212to obtain a structure as shown inFIG.5.

Next, second metal solder pads213are formed over the molding layer1as shown inFIG.6; the second metal solder pads213connect the metal pillars212in series, with each of the second metal solder pads213connecting two of the metal pillars212that are respectively placed over two adjacent first metal solder pads211.

As an example, a material of the second metal solder pads213includes, but is not limited to, copper. Techniques of forming the second metal solder pads213include one of physical vapor deposition, chemical vapor deposition, sputtering, electroplating, and chemical plating. As an example, the second metal solder pads213are arranged parallel to each other.

Finally, as shown inFIG.7, the substrate10is removed along with the release layer11, thereby forming a 3D inductive IPD structure21.

Refer toFIG.8, which is a three-dimensional view of the structure shown inFIG.7. It can be seen that the 3D inductive IPD structure21is formed inside the molding layer1.

As another example, the 3D IPD structure2is a 3D capacitive IPD structure22, and forming the 3D capacitive IPD structure22in the molding layer1may include the steps described below.

First, providing a substrate having a release layer, forming a molding layer on a surface of the release layer.

Next, etching the molding layer to form at least one pair of parallel openings exposing the release layer;

Then, filling the openings with metal materials to form at least one pair of metal layers221parallel to each other, wherein the at least one pair of metal layers221are spaced apart and parallel to each other, wherein said pair of metal layers221are perpendicular to one of the first and second surfaces of the molding layer;

Finally, removing the release layer to remove the substrate, thereby forming the 3D capacitive IPD structure22, as shown inFIG.9, which is a three-dimensional view of the 3D capacitive IPD structure22.

Although only one method for prepare a 3D inductive IPD structure21or a 3D capacitive IPD structure22is described, in other examples there may be other methods for preparing corresponding 3D IPD structures.

As an example, as shown inFIG.10andFIG.12, the method for preparing a wafer-level packaging structure may further include: forming a first rewiring layer3on a first surface of the molding layer1and a second rewiring layer4on a second surface of the molding layer1, wherein the first rewiring layer3includes a first dielectric layer31and a first wiring metal layer32formed in the first dielectric layer31, wherein the second rewiring layer4includes a second dielectric layer41and a second wiring metal layer42formed in the second dielectric layer41and connected to the 3D IPD structure2.

The first wiring metal layer32and the second wiring metal layer42are not shown inFIG.10.

As an example, materials of the first dielectric layer31and the second dielectric layer41include at least one of epoxy resin, silicone, polyimide, polybenzoxazoles, benzocyclobutene, silicon oxide, phosphor silica glass, fluorine containing glass, and other suitable materials.

As an example, materials of the first wiring metal layer32and the second wiring metal layer42include at least one of copper, aluminum, and titanium. Techniques of forming the first wiring metal layer32and the second wiring metal layer42include one of physical vapor deposition, chemical vapor deposition, sputtering, electroplating, and chemical plating. The first wiring metal layer32and the second wiring metal layer42are single-layer or multiple-layer structures.

Subsequently, the method may include other steps to form different types of wafer-level packaging structures.

As an example, where an RF ASIC wafer-level packaging structure needs to be formed, in a way as shown inFIG.11, the method for preparing the wafer-level packaging structure may also include the steps described below.

First, soldering an RF ASIC chip9to the second rewiring layer4, with the RF ASIC chip9connected to the second wiring metal layer (not illustrated).

Then, forming solder balls8on a surface of the first rewiring layer3, with the solder balls8connected to the first wiring metal layer (not shown), thereby forming the RF ASIC wafer-level packaging structure shown inFIG.11.

As another example, where a fan-out wafer-level packaging structure needs to be formed, as shown inFIG.13, the method for preparing the wafer-level packaging structure further includes the steps described below.

First, forming metal connection pillars5in the molding layer1, with the metal connection pillars5connected to the first wiring metal layer32and the second wiring metal layer42. It is to be noted that the preparation of the metal connection pillars5can be carried out simultaneously with the preparation of the 3D IPD structure2, i.e., while preparing the 3D IPD structure2in the molding layer1, the method includes etching the molding layer1and depositing metal material to form the metal connection pillars5.

Then, soldering chips6to the second rewiring layer42, with the chips6connected to the second wiring metal layer42. Cu—Cu bonding may be used to solder the chips6.

Finally, forming solder balls7on a surface of the first rewiring layer3away from the molding layer1, with the solder balls connected to7the first wiring metal layer32, thereby forming a fan-out wafer-level packaging structure as shown inFIG.13.

Material of the solder balls7,8include, but are not limited to, copper or nickel. The first wiring metal layer32may have solder balls7,8directly formed on its surface, or may have metal pillars (not shown) formed thereon first and then have solder balls7,8formed on the metal pillars.

It should be noted that the methods of the present disclosure can be used to prepare not only the RF ASIC wafer-level packaging structure and fan-out wafer-level packaging structure as described above, but can be also used to prepare any other devices that require the integration of a 3D IPD structure2.

The method for preparing the wafer-level packaging structure of the present disclosure enables the preparation of higher performance system-based packaging structures by preparing integrated 3D IPD structures in the molding layer. In addition, the wafer-level packaging structures of the present disclosure can integrate various electronic chips and components such as millimeter wave antenna/capacitor/inductor/electric crystal/GPU/PMU/DDR/flash memory/filter, etc., with higher flexibility and wider compatibility, thus reducing package size and package cost.

Therefore, the present disclosure effectively overcomes various shortcomings in the existing technology and has high industrial utilization value.

The above-mentioned embodiments are just used for exemplarily describing the principle and effects of the present disclosure instead of limiting the present disclosure. Those skilled in the art can make modifications or changes to the above-mentioned embodiments without going against the spirit and the range of the present disclosure. Therefore, all equivalent modifications or changes made by those who have common knowledge in the art without departing from the spirit and technical concept disclosed by the present disclosure shall be still covered by the claims of the present disclosure.