Single event latch-up (SEL) mitigation techniques

Examples described herein provide for single event latch-up (SEL) mitigation techniques. In an example, a semiconductor structure includes a semiconductor substrate, a p-type transistor having p+ source/drain regions disposed in a n-doped region in the semiconductor substrate, an n-type transistor having n+ source/drain regions disposed in a p-doped region in the semiconductor substrate, a n+ guard ring disposed in the n-doped region and laterally around the p+ source/drain regions of the p-type transistor, and a p+ guard ring disposed laterally around the n-doped region. The p+ guard ring is disposed between the p-type transistor and the n-type transistor.

TECHNICAL FIELD

Examples of the present disclosure generally relate to semiconductor structures of integrated circuits and, in particular, to mitigation of single event latch-up (SEL) in semiconductor structures of integrated circuits.

BACKGROUND

Single event latch-up (SEL) is generally an abnormal high-current state in a device caused by the passage of an energetic particle through sensitive regions of the device structure. SEL can result in the loss of device functionality. In complementary device structures in integrated circuits (such as in complementary metal-oxide-semiconductor (CMOS) structures), SEL can result in a parasitic silicon controlled rectifier (SCR) structure turning on to conduct a current. When the parasitic SCR structure is turned on, a voltage drop across the parasitic SCR structure can result in the parasitic SCR structure continuing to conduct the current. The continuous conduction of the current can damage the integrated circuit, such as by generating heat that can cause melting of components, migration of metal, or other problems.

SUMMARY

Examples described herein provide for single event latch-up (SEL) mitigation techniques. In examples describe herein, a p-type device (e.g., a p-type metal-oxide-semiconductor (PMOS) device) centric approach is described. In some examples, unnecessary guard rings may be obviated, and a layout size of the devices and guard rings on a substrate may be reduced. Additionally, placing devices can be simpler and easier to implement.

An example of the present disclosure is a semiconductor structure. The semiconductor structure includes a semiconductor substrate, a first p-type transistor having first p+ source/drain regions disposed in a first n-doped region in the semiconductor substrate, an n-type transistor having n+ source/drain regions disposed in a p-doped region in the semiconductor substrate, a first n+ guard ring disposed in the first n-doped region and laterally around the first p+ source/drain regions of the first p-type transistor, and a p+ guard ring disposed laterally around the first n-doped region. The p+ guard ring is disposed between the first p-type transistor and the n-type transistor.

Another example of the present disclosure is a semiconductor structure. The semiconductor structure includes a semiconductor substrate, a first transistor having a first source/drain region doped with a dopant of a first conductivity type in the semiconductor substrate, a second transistor having a second source/drain region doped with a dopant of a second conductivity type in the semiconductor substrate, a first guard ring doped with a dopant of the second conductivity type in the semiconductor substrate, and a second guard ring doped with a dopant of the first conductivity type in the semiconductor substrate. The first guard ring is disposed laterally around the first source/drain region and between the first source/drain region and the second source/drain region, and the second guard ring is disposed laterally around the first source/drain region and between the first source/drain region and the second source/drain region.

A further example of the present disclosure is a semiconductor structure. The semiconductor structure includes a p-doped substrate, a first n-well disposed in the p-doped substrate, a first p+ source/drain region of a first p-type transistor disposed in the first n-well, a first n+ guard ring disposed in the first n-well and laterally around the first p+ source/drain region, a p+ guard ring disposed in the p-doped substrate and laterally around the first n-well, and an n+ source/drain region of an n-type transistor disposed in the p-doped substrate.

DETAILED DESCRIPTION

Examples described herein provide for single event latch-up (SEL) mitigation techniques. In examples describe herein, a p-type device (e.g., a p-type metal-oxide-semiconductor (PMOS) device) centric approach is described. A p+ guard ring is formed around one or more p-type devices or around a cluster of p-type devices, where the cluster includes multiple n-wells, each of which having one or more of the p-type devices. Further, interior to the p+ guard ring, an n+ guard ring is formed around the one or more p-type devices (e.g., in each n-well of the one or more p-type devices). In further examples, an additional n+ guard ring, disposed in a separate n-well, is disposed around the n+ guard ring(s) and between the n+ guard ring(s) and the p+ guard ring. By employing such a guard ring scheme, unnecessary guard rings may be obviated, and a layout size of the devices and guard rings on a substrate may be reduced. Additionally, placing devices with such a guard ring scheme can be simpler and easier to implement, including implementation and verification.

Generally, latch-up in complementary FET structures (e.g. complementary metal-oxide-semiconductor (CMOS)) can be caused by the triggering of a parasitic silicon controlled rectifier (SCR) structure. The parasitic SCR structure may be formed by, e.g., a p+ source region of a p-type transistor, an n-well in which the p+ source region is disposed, a p-doped region proximate the n-well (e.g., a p-doped substrate in which the n-well is disposed), and an n+ source region of an n-type transistor disposed in the p-doped region. Hence, these regions can form a PNPN structure (e.g., including bipolar junctions). SEL can be caused by transient current originating from charges generated along the track of an incident charged particle. The transition from planar technology to fin field effect transistor (finFET) technology has generally changed the parameters of the parasitic SCR structure, and has generally eased triggering of SEL. SEL generally creates a current through a parasitic SCR structure that is electrically coupled between a power node and a ground node, and the current, once triggered, may continue to flow as long as a hold voltage is across the parasitic SCR structure.

Guard rings, as described herein, are used to decouple parasitic bipolar junctions of the parasitic SCR structure that can be formed by the complementary transistors. By implementing guard rings, a gain βPNP×βNPNcan be reduced that reduces the likelihood of latch up of the parasitic SCR structure (e.g., by reducing a voltage drop across the parasitic SCR so that the parasitic SCR is less likely to achieve the hold voltage). Examples described herein can achieve this reduced gain in a smaller layout footprint and in a simpler design.

FIGS. 1A and 1Billustrate a SEL mitigation technique according to an example.FIG. 1Aillustrates a layout of a cell100on a semiconductor substrate102, andFIG. 1Billustrates a cross-sectional view of the cell100on the semiconductor substrate102along the cross-section1B-1B shown inFIG. 1A. The cell100can be for a complementary (e.g., CMOS) input/output device, for example. The cell100includes p-type field effect transistors (pFETs)104and n-type FETs (nFETs)106, as illustrated. In other examples, the cell100can include a single pFET and a single nFET, or can include any number and combination of pFETs and nFETs. The cell100can be repeated any number of times on the semiconductor substrate102.

The semiconductor substrate102includes a p-doped semiconductor material (e.g., a p-doped region). For example, the semiconductor substrate102can be silicon doped with a p-type dopant. Other semiconductor material can be implemented. The p-type dopant can be introduced into the semiconductor substrate102during formation of the ingot that is subsequently formed into the semiconductor substrate102, by epitaxially growing a material on the semiconductor substrate102that is doped in situ with the p-type dopant, and/or by implantation of the p-type dopant into the semiconductor substrate102during processing. The concentration of the p-type dopant in the semiconductor substrate102can be in a range from about 1×1013cm−3to about 5×1013cm−3.

An n-well110is formed in the semiconductor substrate102. The n-well110is formed where the pFETs104are to be formed. The n-well110can be formed by implantation of an n-type dopant into the semiconductor substrate102and/or by etching the semiconductor substrate102and epitaxially growing a material that is doped in situ with n-type dopant. In some examples, the concentration of the n-type dopant in the n-well110is greater, such as by an order of magnitude or more, than the concentration of the p-type dopant in the semiconductor substrate102. The concentration of the n-type dopant in the n-well110can be in a range from about 1×1018cm−3to about 5×1018cm−3.

Each of the pFETs104includes source/drain regions112on opposing sides of a respective one of gates114. Each of the source/drain regions112includes a p+ doped region disposed in the n-well110in the semiconductor substrate102. The p+ doped regions can be formed by implantation of a p-type dopant and/or by etching the semiconductor substrate102and epitaxially growing a material that is doped in situ with p-type dopant. The source/drain regions112can be self-aligned with the gates114. Each of the pFETs104further includes a channel region underlying the respective one of the gates114. The channel region is a portion of the n-well110in the semiconductor substrate102. The concentration of the p-type dopant in the p+ doped regions of the source/drain regions112is greater, such as by an order of magnitude or more, than the concentration of the n-type dopant in the n-well110. The concentration of the p-type dopant in the p+ doped regions of the source/drain regions112can be in a range from about 1×1019cm−3to about 1×1021cm−3.

An n+ guard ring116is formed in the n-well110in the semiconductor substrate102and laterally around the pFETs104. The n+ guard ring116can be formed by implantation of an n-type dopant or other technique. The concentration of the n-type dopant in the n+ guard ring116is greater, such as by an order of magnitude or more, than the concentration of the n-type dopant in the n-well110. The concentration of the n-type dopant in the n+ guard ring116can be in a range from about 1×1019cm−3to about 1×1021cm−3.

A p+ guard ring118is formed in the semiconductor substrate102and laterally around the n-well110and n+ guard ring116. The p+ guard ring118can be formed by implantation of a p-type dopant. The concentration of the p-type dopant in the p+ guard ring118is greater, such as by an order of magnitude or more, than the concentration of the p-type dopant in the p-doped semiconductor substrate102. The concentration of the p-type dopant in the p+ guard ring118can be in a range from about 1×1019cm−3to about 1×1021cm−3.

The nFETs106are formed laterally outside of the p+ guard ring118and the n+ guard ring116. Each of the p+ guard ring118and the n+ guard ring116is disposed between the pFETs104and the nFETs106. Each of the nFETs106includes source/drain regions122on opposing sides of respective one of gates124. Each of the source/drain regions122includes an n+ doped region disposed in the p-doped semiconductor substrate102. The n+ doped regions can be formed by implantation of an n-type dopant and/or by etching the semiconductor substrate102and epitaxially growing a material that is doped in situ with n-type dopant. The source/drain regions122can be self-aligned with the gates124. Each of the nFETs106further includes a channel region underlying the respective one of the gates124. The channel region is a portion of the p-doped semiconductor substrate102. The concentration of the n-type dopant in the n+ doped regions of the source/drain regions122is greater, such as by an order of magnitude or more, than the concentration of the p-type dopant in the p-doped semiconductor substrate102. The concentration of the n-type dopant in the n+ doped regions of the source/drain regions122can be in a range from about 1×1019cm−3to about 1×1021cm−3.

Isolation regions128(e.g., shallow trench isolations (STIs)) are formed in the semiconductor substrate102and between various doped regions as shown in the cross-section ofFIG. 1B(and not explicitly identified in the layout ofFIG. 1A). Various contacts132may be formed to the source/drain regions112of the pFETs104, n+ guard ring116, p+ guard ring118, and source/drain regions122of the nFETs106, such as through a dielectric layer134(e.g., interlayer dielectric) over the semiconductor substrate102. The contacts132may be connected to various interconnects to form various circuits. For example, contacts132to the source/drain regions112of the pFETs104and to the source/drain regions122of the nFETs106may be connected to form an input/output circuit that includes the pFETs104and nFETs106. The contacts132to the n+ guard ring116may be connected together to a same node, and the contacts132to the p+ guard ring118may be connected together to a same node.

As illustrated by the layout ofFIG. 1A, the two guard rings (the n+ guard ring116and the p+ guard ring118) are laterally around the pFETs104, while no guard ring is laterally around the nFETs106that is not also around the pFETs104(such as around a larger area of the semiconductor substrate102that is not depicted).

In the following examples, description of various formation techniques and dopant concentrations of doped regions is omitted for brevity. A person having ordinary skill in the art will readily understand a correspondence between regions of the foregoing example and regions of following examples, such that such a person would understand how the preceding description applies to the regions of the following examples. For example, description of the semiconductor substrate102applies to following semiconductor substrates; description of n+ and p+ regions of source/drain regions112and122applies to following n+ and p+ regions of source/drain regions; description of n-well110applies to following n-wells and n-well rings; and description of n+ and p+ guard rings116and118applies to following n+ and p+ guard rings.

FIGS. 2A and 2Billustrate another SEL mitigation technique according to an example.FIG. 2Aillustrates a layout of a stochastic arrangement200on a semiconductor substrate202, andFIG. 2Billustrates a cross-sectional view of the stochastic arrangement200on the semiconductor substrate202along the cross-section2B-2B shown inFIG. 2A. The stochastic arrangement200can be for a complementary (e.g., CMOS) circuit, for example. The stochastic arrangement200includes one pFET204and multiple nFETs206, as illustrated. In other examples, the cell100can include a single pFET and a single nFET, or can include any number and combination of pFETs and nFETs.

The semiconductor substrate202includes a p-doped semiconductor material (e.g., a p-doped region). An n-well210is formed in the semiconductor substrate202. The pFET204includes source/drain regions212on opposing sides of a gate214. Each of the source/drain regions212includes a p+ doped region disposed in the n-well210in the semiconductor substrate202. The pFET204further includes a channel region underlying the gate214. The channel region is a portion of the n-well210in the semiconductor substrate202. A first n+ guard ring216is formed in the n-well210in the semiconductor substrate202and laterally around the pFET204.

An n-well ring220is formed in the semiconductor substrate202laterally around, and separate from, the n-well210. A second n+ guard ring222is formed in the n-well ring220in the semiconductor substrate202, laterally around and separate from the first n+ guard ring216, and laterally around the pFET204. The second n+ guard ring222can be a minority carrier guard ring, and may be omitted (along with the n-well ring220) in some examples. A p+ guard ring224is formed in the semiconductor substrate202and laterally around and separate from the n-well ring220and second n+ guard ring222.

The nFETs206are formed laterally outside of the p+ guard ring224, the second n+ guard ring222, and the first n+ guard ring216. Each of the p+ guard ring224, the second n+ guard ring222, and the first n+ guard ring216is disposed between the pFET204and the nFETs206. Each of the nFETs206includes source/drain regions232on opposing sides of a respective gate234. Each of the source/drain regions232includes an n+ doped region disposed in the p-doped semiconductor substrate202. Each of the nFETs206further includes a channel region underlying the respective gate234. The channel region is a portion of the p-doped semiconductor substrate202.

Isolation regions238(e.g., STIs) are formed in the semiconductor substrate202and between various doped regions as shown in the cross-section ofFIG. 2B(and not explicitly identified in the layout ofFIG. 2A). Various contacts242may be formed to the source/drain regions212of the pFET204, first n+ guard ring216, second n+ guard ring222, p+ guard ring224, and source/drain regions232of the nFETs206, such as through a dielectric layer244(e.g., interlayer dielectric) over the semiconductor substrate202. The contacts242may be connected to various interconnects to form various circuits. For example, contacts242to the source/drain regions212of the pFET204and to the source/drain regions232of the nFETs206may be connected to form any circuit that includes the pFET204and any of the nFETs206. The contacts242to the first n+ guard ring216may be connected together to a same node; the contacts242to the second n+ guard ring222may be connected together to a same node; and the contacts242to the p+ guard ring224may be connected together to a same node.

As illustrated by the layout ofFIG. 2A, the three guard rings (the first n+ guard ring216, the second n+ guard ring222, and the p+ guard ring224) are laterally around the pFET204, while no guard ring is laterally around any of the nFETs206that is not also around any of the pFETs204(such as around a larger area of the semiconductor substrate202that is not depicted).

FIGS. 3A and 3Billustrate a further SEL mitigation technique according to an example.FIG. 3Aillustrates a layout of a cluster arrangement300on a semiconductor substrate302including a cluster of multiple n-wells having different pFETs disposed therein, andFIG. 3Billustrates a cross-sectional view of the cluster arrangement300on the semiconductor substrate302along the cross-section3B-3B shown inFIG. 3A. Aspects of the cluster arrangement300(e.g., relating to the cluster of multiple n-wells) can be applied to a cell like inFIGS. 1A and 1Band to a stochastic arrangement like inFIGS. 2A and 2B. Some features, such as contacts, are omitted fromFIGS. 3A and 3Bto not obscure other features, but a person having ordinary will readily understand the presence and applicability of various features that have been illustrated in and described with respect toFIGS. 1A, 1B, 2A, and 2B.

The cluster arrangement300includes pFETs304a,304b,304c, and304dand a single nFET306formed on a semiconductor substrate302, as illustrated. In other examples, the cluster arrangement300can include any number and combination of pFETs and nFETs. The semiconductor substrate302includes a p-doped semiconductor material (e.g., a p-doped region). Separate n-wells310a,310b,310c, and310dare formed in the semiconductor substrate302. Each of the pFETs304a,304b,304c, and304dincludes source/drain regions312on opposing sides of a respective one of gates314. Each of the source/drain regions312includes a p+ doped region disposed in the respective one of the n-wells310a,310b,310c, and310din the semiconductor substrate302. Each of the pFETs304a,304b,304c, and304dfurther includes a channel region underlying the respective one of the gates314. The channel region is a portion of the respective one of the n-wells310a,310b,310c, and310din the semiconductor substrate302. First n+ guard rings316a,316b,316c, and316dare formed in the n-wells310a,310b,310c, and310d, respectively, in the semiconductor substrate302and laterally around the pFETs304a,304b,304c, and304d, respectively.

More specifically, the pFETs304aare formed in the n-well310a; the pFETs304bare formed in the n-well310b; the pFETs304care formed in the n-well310c; and the pFETs304dare formed in the n-well310d. The first n+ guard ring316ais disposed in the n-well310aand around the pFETs304a; the first n+ guard ring316bis disposed in the n-well310band around the pFETs304b; the first n+ guard ring316cis disposed in the n-well310cand around the pFETs304c; and the first n+ guard ring316dis disposed in the n-well310dand around the pFETs304d. Although four n-wells with two pFETs disposed therein and with a respective first n+ guard ring around the two pFETs are illustrated, any number of n-wells may be implemented with any number of pFETs in each n-well with a respective first n+ guard ring around the pFETs. The separate n-wells310a,310b,310c, and310dpermit a different supply voltage to be implemented at each of the n-wells310a,310b,310c, and310d(e.g., to be connected to source/drain regions312in the n-wells310a,310b,310c, and310d).

An n-well ring320is formed in the semiconductor substrate302laterally around, and separate from, the n-wells310a,310b,310c, and310d. A second n+ guard ring322is formed in the n-well ring320in the semiconductor substrate302, laterally around and separate from the first n+ guard rings316a,316b,316c, and316d, and laterally around the pFETs304a,304b,304c, and304d. The second n+ guard ring322can be a minority carrier guard ring, and may be omitted (along with the n-well ring320) in some examples. A p+ guard ring324is formed in the semiconductor substrate302and laterally around and separate from the n-well ring320and second n+ guard ring322.

The nFET306is formed laterally outside of the p+ guard ring324, the second n+ guard ring322, and the first n+ guard rings316a,316b,316c, and316d. Each of the p+ guard ring324, the second n+ guard ring322, and at least one of the first n+ guard rings316a,316b,316c, and316dis disposed between the pFETs304a,304b,304c, and304dand the nFET306. The nFET306includes source/drain regions332on opposing sides of a gate334. Each of the source/drain regions332includes an n+ doped region disposed in the p-doped semiconductor substrate302. The nFET306further includes a channel region underlying the gate334. The channel region is a portion of the p-doped semiconductor substrate302.

Isolation regions338(e.g., STIs) are formed in the semiconductor substrate302and between various doped regions as shown in the cross-section ofFIG. 3B(and not explicitly identified in the layout ofFIG. 3A). Various contacts (not illustrated) may be formed to the source/drain regions312of the pFETs304a,304b,304c,304d, first n+ guard rings316a,316b,316c, and316d, second n+ guard ring322, p+ guard ring324, and source/drain regions332of the nFET306, such as through a dielectric layer344(e.g., interlayer dielectric) over the semiconductor substrate302. The contacts may be connected to various interconnects to form various circuits.

As illustrated by the layout ofFIG. 3A, three guard rings (at least one of the first n+ guard rings316a,316b,316c, and316d; the second n+ guard ring322; and the p+ guard ring324) are laterally around the respective pFETs304a,304b,304c, and304d, while no guard ring is laterally around the nFET306that is not also around any of the pFETs304a,304b,304c, and304d(such as around a larger area of the semiconductor substrate302that is not depicted).

As shown in the foregoing examples, guard rings are implemented around one or more pFETs, which can obviate the need to implement any guard ring around an nFET that is not also around the pFET(s) (e.g., around a larger area of the chip). This can further reduce unnecessary guard rings that may otherwise be implemented, and can reduce a layout area of a design. Additionally, simpler and easier designs may be implemented since guard rings around nFETs may be obviated.

FIG. 4is an example method400for implementing an SEL mitigation technique according to some examples. In operation402, one or more n-type transistors are formed in a p-doped region in a substrate, and one or more p-type transistors are formed in an n-doped region in the substrate. More specifically, source/drain regions of the n-type transistor(s) are formed in the p-doped region, and source/drain regions of the p-type transistor(s) are formed in the n-doped region. Further, in some examples, multiple n-doped regions may be formed, and one or more p-type transistors may be formed in each of the multiple n-doped regions. As examples, source/drain regions122,232,332of the nFETs106,206,306are formed in the p-doped region (e.g., p-doped semiconductor substrate102,202,302), and source/drain regions112,212,312of the pFETs104,204,304a-dare formed in the n-well110,210,310a-d. The layout of the various transistors may be according to a repeating cell on the substrate or a stochastic layout.

In operation404, a first n+ guard ring is formed in the n-doped region in the substrate and laterally around the source/drain regions of the one or more p-type transistors. In some examples where multiple n-doped regions may be formed, a first n+ guard ring may be formed in each of the multiple n-doped regions and laterally around corresponding source/drain regions in the respective n-doped region. As examples, an n+ guard ring116,216,316a-dis formed in the n-well110,210,310a-dand laterally around the source/drain regions112,212,312of the pFETs104,204,304a-d.

In operation406, optionally, a second n+ guard ring is formed in an n-well ring in the substrate laterally around the n-doped region. In some examples where multiple n-doped regions may be formed, a second n+ guard ring may be formed in an n-well ring that is laterally around the multiple n-doped regions. As examples, a second n+ guard ring222,322is formed in an n-well ring220,320laterally around the n-well110,210,310a-d.

In operation408, a p+ guard ring is formed in the substrate laterally around the n-doped region and, if optionally implemented, the n-well ring. As examples, a p+ guard ring118,224,324is formed laterally around the n-well110,210,310a-dand, if implemented, the n-well ring220,320.

A person having ordinary skill in the art will readily understand that the processing to form the various components formed by the method400ofFIG. 4can be implemented by doping a substrate, such as by implantation, that may be performed according to any appropriate sequence. For example, various components formed by the method400that are illustrated as being formed in different operations may be formed simultaneously or in a different sequence from what is illustrated. Various other features of the SEL mitigation techniques implemented by the method400can be as described with respect to and illustrated in any ofFIGS. 1A-1B, 2A-2B, and3A-3B.

FIG. 5illustrates a field programmable gate array (FPGA) of a programmable integrated circuit (IC)500that may implement SEL mitigation techniques, such as described above, according to some examples. The programmable IC500is implemented on a semiconductor substrate, such as typically included in a die or chip. The various circuits formed in the programmable IC500can be formed of nFETs and pFETs in the semiconductor substrate in a repeating cell layout and/or stochastic layout.

The programmable IC500includes a large number of different programmable tiles including configurable logic blocks (“CLBs”)530, random access memory blocks (“BRAMs”)532, signal processing blocks (“DSPs”)534, input/output blocks (“IOBs”)536, configuration and clocking logic (“CONFIG/CLOCKS”)538, digital transceivers540, specialized input/output blocks (“I/O”)542(e.g., configuration ports and clock ports), and other programmable logic544such as digital clock managers, system monitoring logic, and so forth. The FPGA can also include PCIe interfaces546, analog-to-digital converters (ADC)548, and the like.

In some FPGAs, each programmable tile can include at least one programmable interconnect element (“INT”)550having connections to input and output terminals552of a programmable logic element within the same tile, as shown by examples included inFIG. 5. Each programmable interconnect element550can also include connections to interconnect segments554of adjacent programmable interconnect element(s) in the same tile or other tile(s). Each programmable interconnect element550can also include connections to interconnect segments556of general routing resources between logic blocks (not shown). The general routing resources can include routing channels between logic blocks (not shown) comprising tracks of interconnect segments (e.g., interconnect segments556) and switch blocks (not shown) for connecting interconnect segments. The interconnect segments of the general routing resources (e.g., interconnect segments556) can span one or more logic blocks. The programmable interconnect elements550taken together with the general routing resources implement a programmable interconnect structure (“programmable interconnect”) for the illustrated FPGA.

In an example implementation, a CLB530can include a configurable logic element (“CLE”)560that can be programmed to implement user logic plus a single programmable interconnect element (“INT”)550. A BRAM532can include a BRAM logic element (“BRL”)562in addition to one or more programmable interconnect elements. Typically, the number of interconnect elements included in a tile depends on the height of the tile. In the pictured example, a BRAM tile has the same height as five CLBs, but other numbers (e.g., four) can also be used. A signal processing block534can include a DSP logic element (“DSPL”)564in addition to an appropriate number of programmable interconnect elements. An IOB536can include, for example, two instances of an input/output logic element (“IOL”)566in addition to one instance of the programmable interconnect element550. As will be clear to those of skill in the art, the actual I/O pads connected, for example, to the input/output logic element566typically are not confined to the area of the input/output logic element566.

Some FPGAs utilizing the architecture illustrated inFIG. 5include additional logic blocks that disrupt the regular columnar structure making up a large part of the FPGA. The additional logic blocks can be programmable blocks and/or dedicated logic.

The SEL mitigation techniques can be implemented in any block of the programmable IC500. As an example, the example ofFIGS. 1A and 1Bcan be implemented in the IOBs536, BRAM532, and/or other blocks. Further, the example ofFIGS. 2A and 2Bcan be implemented in the CLBs530and/or other blocks. Any combination of examples may be included in a single IC, such as the programmable IC500ofFIG. 5.