Semiconductor device and data storage system including the same

A semiconductor device and a data storage system including the same are provided. The semiconductor device includes a lower structure including a semiconductor substrate, a circuit element on the semiconductor substrate, a circuit interconnection structure on the semiconductor substrate, the circuit interconnection structure including a plurality of connection patterns on different levels and electrically connected to the circuit element, and a lower insulating structure covering the circuit element and the circuit interconnection structure; and an upper structure including an upper substrate in contact with an upper surface of the lower insulating structure, a stack structure on the upper substrate, the stack structure including interlayer insulating layers and gate electrodes alternately stacked in a vertical direction, and a vertical memory structure penetrating through the stack structure in the vertical direction.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims the benefit under 35 USC 119(a) of Korean Patent Application No. 10-2021-0049014 filed on Apr. 15, 2021 in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes.

BACKGROUND

The present inventive concepts relate to a semiconductor device and a data storage system including the same.

Semiconductor devices capable of storing high-capacity data in electronic systems requiring data storage are in demand. Accordingly, a method for increasing a data storage capacity of a semiconductor device is being studied. For example, as one method for increasing the data storage capacity of a semiconductor device, a semiconductor device including memory cells arranged three-dimensionally instead of memory cells arranged two-dimensionally has been proposed.

SUMMARY

Example embodiments provide a semiconductor device having improved integration.

Example embodiments provide a data storage system including a semiconductor device.

According to some example embodiments, a semiconductor device may include a lower structure including a semiconductor substrate, a circuit element on the semiconductor substrate, a circuit interconnection structure on the semiconductor substrate, the circuit interconnection structure including a plurality of connection patterns on different levels and electrically connected to the circuit element, and a lower insulating structure covering the circuit element and the circuit interconnection structure; an upper structure including an upper substrate in contact with an upper surface of the lower insulating structure, a stack structure on the upper substrate, the stack structure including interlayer insulating layers and gate electrodes alternately stacked in a vertical direction, and a vertical memory structure penetrating through the stack structure in the vertical direction; and a contact plug penetrating through at least a portion of the lower insulating structure such that the contact plug contacts an uppermost connection pattern, among the plurality of connection patterns. The lower insulating structure may include a first insulating layer, a capping layer and a second insulating layer sequentially stacked in a region between the upper substrate and the uppermost connection pattern, and the capping layer may include a material different from a material of the first insulating layer and a material of the second insulating layer.

According to some example embodiments, a semiconductor device may include an upper structure including an upper substrate, a stack structure including interlayer insulating layers and gate electrodes alternately stacked on the upper substrate in a vertical direction, and a vertical memory structure penetrating through the stack structure in the vertical direction; a lower structure under the upper substrate, the lower structure including a semiconductor substrate, a circuit element on the semiconductor substrate, a circuit interconnection structure on the semiconductor substrate, the circuit interconnection structure including at least three connection patterns, the at least three connection patterns including an uppermost connection pattern in an uppermost portion, and a lower connection pattern in a lower portion, an intermediate connection pattern between the uppermost connection pattern and the lower connection pattern, an upper via electrically connecting the uppermost connection pattern and the intermediate connection pattern, and a lower insulating structure covering the circuit element and the circuit interconnection structure, the lower insulating structure including a first insulating layer, a capping layer and a second insulating layer sequentially stacked in a portion between the upper substrate and the uppermost connection pattern; and a contact plug penetrating through the first insulating layer, the capping layer, and the second insulating layer and extending into the uppermost connection pattern. A thickness of the uppermost connection pattern may be greater than a thickness of the intermediate connection pattern, the capping layer may include a material different from a material of the first insulating layer and a material of the second insulating layer, a thickness of the second insulating layer may be greater than a thickness of the capping layer, the thickness of the capping layer may be greater than the thickness of the first insulating layer, the uppermost connection pattern may include an upper surface of which at least a portion has a curved surface shape, and the contact plug may penetrate through a portion of the upper surface of the uppermost connection pattern and extends into the uppermost connection pattern.

According to some example embodiments, a data storage system may include a semiconductor device including an input/output pad; and a controller electrically connected to the semiconductor device through the input/output pad and configured to control the semiconductor device. The semiconductor device may further include an upper structure including an upper substrate in contact with an upper surface of the lower insulating structure, a stack structure on the upper substrate, the stack structure including interlayer insulating layers and gate electrodes alternately stacked in a vertical direction, and a vertical memory structure penetrating through the stack structure in the vertical direction, a lower structure including a semiconductor substrate, a circuit element on the semiconductor substrate, a circuit interconnection structure including a plurality of connection patterns on different levels, the plurality of connection patterns electrically connected to the circuit element, and a lower insulating structure covering the circuit element and the circuit interconnection structure, the lower insulating structure including a first insulating layer, a capping layer and a second insulating layer sequentially stacked in a portion between the upper substrate and the uppermost connection pattern, and a contact plug penetrating through at least a portion of the lower insulating structure such that the contact plug contacts an uppermost connection pattern, of the connection patterns. The capping layer may include a material different from a material of the first insulating layer and a material of the second insulating layer.

DETAILED DESCRIPTION

Hereinafter, spatially relative terms such as “upper,” “middle,” “lower”, vertical, and/or the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. Terms such as “first,” “second,” and “third” may be used to describe various elements. These terms are used to distinguish one element from another element, but the elements are not otherwise limited by the terms. For example, a “first element” may be termed a “second element” without departing from the scope of the disclosure.

Referring toFIGS.1A,1B,2A and2B, a semiconductor device1according to some example embodiments may include a lower structure LS and an upper structure US on the lower structure2.FIG.1Ais a longitudinal cross-sectional view of a semiconductor device, according to some example embodiment taken in the X direction, andFIG.1Bis a longitudinal cross-sectional view of the semiconductor device taken in the Y direction.FIG.2Ais a partially enlarged view of a portion marked with ‘A’ ofFIG.1A, andFIG.2Bis an enlarged view of a portion marked with ‘B’ ofFIG.1A.

The lower structure LS may include a semiconductor substrate3, a circuit element21on the semiconductor substrate3, a circuit interconnection structure63electrically connected to the circuit element21and on the semiconductor substrate3, and a lower insulating structure75covering the circuit element21and the circuit interconnection structure63on the semiconductor substrate3.

The lower structure LS may further include a field region6sdefining an active region6ain the semiconductor substrate3. The field region6smay be formed by, e.g., shallow trench isolation.

The circuit element21may include a peripheral gate9and peripheral sources/drains18. The peripheral gate9may include a peripheral gate dielectric9aand a peripheral gate electrode9bon the peripheral gate dielectric9a.

The peripheral sources/drains18may be disposed within the active region6aand may be spaced apart from each other. The peripheral gate9may be disposed on the active region6abetween the peripheral sources/drains18. An area of the substrate3between the peripheral sources/drains18and under the peripheral gate9may form a channel.

The lower structure LS may further include a gate capping pattern12covering the peripheral gate9, and a gate spacer15covering side surfaces of the peripheral gate9and the gate capping pattern12. The gate capping pattern12may include a material such as silicon nitride. The gate spacer15may include at least one of silicon oxide, silicon oxynitride, or silicon nitride.

The lower structure LS may further include an insulating liner24covering the circuit element21, on the semiconductor substrate3including the active region6aand the field region6s. The insulating liner24may conformally cover surfaces of the gate spacer15and the gate capping pattern12. The insulating liner24may include silicon nitride. The insulating liner24may include a first liner layer24aand a second liner layer24bon the first liner layer24a. The first liner layer24aand the second liner layer24bmay include materials with different etch selectivity. For example, the first liner layer24amay include silicon oxide, and/or the second liner layer24bmay include silicon nitride.

The lower insulating structure75may include a first lower insulating layer27, a second lower insulating layer33, a third lower insulating layer39, a fourth lower insulating layer45, a fifth lower insulating layer51, a sixth lower insulating layer57, a first insulating layer66, a capping layer69, and a second insulating layer72, sequentially stacked. The first lower insulating layer27may be disposed on the insulating liner24.

The circuit interconnection structure63may include a plurality of connection patterns36,48, and60disposed at different height levels. In some embodiments, the plurality of connection patterns36,48, and60may include at least three connection patterns disposed at different height levels. For example, the plurality of connection patterns36,48and60may include an uppermost connection pattern60disposed on the uppermost portion, an intermediate connection pattern48disposed on an intermediate portion, a lower level than the uppermost connection pattern60, and a lower connection pattern36disposed on a lowermost portion, a level lower than the intermediate connection pattern48.

In some embodiments, a thickness of the uppermost connection pattern60may be greater than a thickness of the intermediate connection pattern48. In some embodiments, a thickness of the uppermost connection pattern60may be greater than a thickness of the lower connection pattern36. In some embodiments, the thickness of the uppermost connection pattern60may be greater than the sum of the thickness of the intermediate connection pattern48and the thickness of the lower connection pattern36.

Each of the plurality of connection patterns36,48, and60may include a conductive material pattern and a conductive barrier layer covering side and bottom surfaces of the conductive material pattern. In an illustrative example, the conductive material pattern may include a metal material such as tungsten and/or the like, and the conductive barrier layer may include a metal nitride such as titanium nitride and/or the like. For example, the uppermost connection pattern60may include a metal material pattern59band a conductive barrier layer59acovering side and bottom surfaces of the metal material pattern59b, and the intermediate connection pattern48may include a metal material pattern48band a conductive barrier layer48acovering side and bottom surfaces of the metal material pattern48b.

In an example, the thickness of the conductive barrier layer59amay range from about 40 Angstroms (Å) to about 120 Å. In another example, the thickness of the conductive barrier layer59amay range from about 60 Å to about 100 Å.

The circuit interconnection structure63may further include a plurality of vias30,42, and54disposed at different height levels. The plurality of vias30,42, and54may include a lower via30, an intermediate via42having a higher level than the lower via30, and an upper via54having a higher level than the intermediate via42. Each of the plurality of vias30,42, and54may include a conductive material pattern and a conductive barrier layer covering side and bottom surfaces of the conductive material pattern. For example, the upper via54may include a conductive material pattern54band a conductive barrier layer54acovering side and bottom surfaces of the conductive material pattern54b, and the lower via30may include a conductive material pattern30band a conductive barrier layer30acovering side and bottom surfaces of the conductive material pattern30b. In some embodiments, the conductive material pattern may include a metal and/or the conductive barrier layer may include a metal nitride.

The lower via30may penetrate through the first lower insulating layer27and the insulating liner24and may be electrically connected to the circuit element21. For example, the lower via30may be connected a peripheral source/drain18. The lower connection pattern36may penetrate through the second lower insulating layer33and may be electrically connected to the lower via30. The intermediate via42may penetrate through the third lower insulating layer39and may be electrically connected to the lower connection pattern36. The intermediate connection pattern48may penetrate through the fourth lower insulating layer45and may be electrically connected to the intermediate via42. The upper via54may penetrate through the fifth lower insulating layer51and may be electrically connected to the intermediate connection pattern48. The uppermost connection pattern60may penetrate through the sixth lower insulating layer57and may be electrically connected to the upper via54.

In some example embodiments, the uppermost connection pattern60may have a (e.g., single) damascene structure. For example, forming the uppermost connection pattern60of a single damascene structure may include forming an opening penetrating through the sixth lower insulating layer57and exposing the upper via54, forming a conductive material layer filling the opening and covering the sixth lower insulating layer57, and planarizing the conductive material layer by performing a chemical mechanical polishing process.

The width of the uppermost connection pattern60may increase from the lower region to the upper region, between the first and second side surfaces facing each other. Accordingly, the uppermost connection pattern60may have an inclined side surface.

The uppermost connection pattern60may contact an upper surface of the upper via54and a side surface of an upper region of the upper via54. For example, the conductive barrier layer59aof the uppermost connection pattern60may contact an upper surface of the upper via54and a side surface of an upper region of the upper via54. An upper end of the upper via54may be disposed on a higher level than a lower surface of the uppermost connection pattern60.

In the lower insulating structure75, a portion thereof located on a higher level than the uppermost connection pattern60located on the top of the plurality of connection patterns36,48and60may include the first insulating layer66, the capping layer69and the second insulating layer72. The first insulating layer66may contact upper surfaces of the uppermost connection patterns60and the upper surface of the sixth lower insulating layer57.

The material of the capping layer69may be different from the material of the first insulating layer66and the material of the second insulating layer72. For example, the material of the capping layer69may be silicon nitride and/or a silicon nitride-based insulating material, and the material of the first insulating layer66and the material of the second insulating layer72may be silicon oxide and/or a low dielectric material.

A thickness of the second insulating layer72may be greater than a thickness of the capping layer69. A thickness of the second insulating layer72may be greater than a thickness of the first insulating layer66. A thickness of the first insulating layer66may be less than a thickness of the capping layer69. In another example, the thickness of the first insulating layer66may be substantially the same as the thickness of the capping layer69.

In some examples, the thickness of the capping layer69may range from about 150 Å to about 500 Å. For example, the thickness of the capping layer69may range from about 300 Å to about 400 Å.

In an example, the thickness of the first insulating layer66may be greater than about 10 Å and less than the thickness of the capping layer69. For example, the thickness of the first insulating layer66may be greater than about 30 Å and less than the thickness of the capping layer69.

The upper structure US may include an upper substrate103on the lower insulating structure75, a first inner insulating layer106aand a second inner insulating layer106bpenetrating through the upper substrate103, and an intermediate insulating layer106con an outer side surface of the upper substrate103. The upper substrate103may contact an upper surface of the second insulating layer72.

The upper substrate103may include a lower pattern layer103a, a first intermediate pattern layer103b1and a second intermediate pattern layer103b2spaced apart from each other on the lower pattern layer103a, and an upper pattern layer103con the lower pattern layer103aand covering the first and second intermediate pattern layers103b1and103b2. The lower pattern layer103amay be thicker than each of the first intermediate pattern layer103b1, the second intermediate pattern layer103b2, and the upper pattern layer103c.

At least one of the lower pattern layer103a, the first intermediate pattern layer103b1, and/or the upper pattern layer103cmay include a silicon layer. For example, at least one of the lower patterned layer103a, the first intermediate patterned layer103b1and/or the upper patterned layer103cmay include a doped polysilicon layer (for example, a polysilicon layer having an N-type conductivity).

The second intermediate pattern layer103b2may include a first material layer, a second material layer, and a third material layer sequentially stacked. In some example embodiments of the second intermediate pattern layer103b2, the first material layer and the third material layer may be silicon oxide layers, and/or the second material layer may be a silicon nitride layer.

The upper structure US may further include a stack structure GS, and second capping insulating layers118and130covering at least a portion of the stack structure GS. The stack structure GS may be disposed on the upper substrate103.

The stack structure GS may include a lower stack structure GSa and an upper stack structure GSb disposed on the lower stack structure GSa. The lower stack structure GSa may include first interlayer insulating layers109and first gate layers112gthat are alternately stacked. Among the lower stack structure GSa, an uppermost layer and a lowermost layer may each be a first interlayer insulating layer109.

The upper stack structure GSb may include second interlayer insulating layers121and second gate layers124gthat are alternately stacked. Among the upper stack structure GSb, an uppermost layer and a lowermost layer may each be a second interlayer insulating layer121. The first and second gate layers112gand124gmay be referred to as gate electrodes.

The stack structure GS may have a substantially flat upper surface in a memory cell array area MCA on the upper substrate103, and may have a stepped shape in a step area SA on the upper substrate103. For example, the first gate layers112gand the second124gmay be stacked while being spaced apart from each other in a vertical direction Z in the memory cell array area MCA, and may extend from the memory cell array area MCA to the step area SA to have gate pads GP that are arranged in a stepped shape in the step area SA.

In a first through area TA1in the step area SA, the stack structure GS may include horizontal insulating layers112iadisposed on the same level as at least a portion of the first and second gate layers112gand124g. The horizontal insulating layers112iamay be formed of silicon nitride. The first through area TA1may overlap the first inner insulating layer106a.

The stack structure GS may include horizontal insulating layers112iband124idisposed, respectively, on the same level as at least portions of the first and second gate layers112gand124gin a second through area TA2between the memory cell array areas MCA. The horizontal insulating layers112iband124imay be formed of silicon nitride. The second through area TA2may overlap the second inner insulating layer106b.

The upper structure US may further include a first upper insulating layer151, a second upper insulating layer157, a third upper insulating layer169, a fourth upper insulating layer175, and a fifth upper insulating layer181, sequentially stacked on the stack structure GS and the second capping insulating layer130.

The upper structure US may further include vertical memory structures133penetrating through the stack structure GS in the memory cell array area MCA. The vertical memory structures133may contact the upper substrate103. Regions of the vertical memory structures133, facing the gate layers that may be word lines among the first and second gate layers112gand124g, may include memory cells configured to store information (e.g., of a memory device). Accordingly, the upper structure US may include memory cells arranged three-dimensionally.

The upper structure US may further include an upper isolation pattern148penetrating and dividing one and/or a plurality of second gate layers124g(e.g., positioned in an upper portion, among the second gate layers124g, and may, for example, divide and/or isolate string selection lines). The upper isolation pattern148may be disposed on a higher level than word lines among the gate layers124g. The upper isolation pattern148may be formed of an insulating material such as silicon oxide.

The upper structure US may further include separation structures154penetrating through the first upper insulating layer151and the stack structure GS. The vertical memory structures133may be disposed between the separation structures154adjacent to each other. The separation structures154may penetrates through the upper pattern layer103cand the first intermediate pattern layer103b1and may contact the lower pattern layer103a. In some example embodiments, the separation structures154may be formed of and/or include an insulating material such as silicon oxide and/or a high dielectric material.

In some example embodiments, some and/or each of the separation structures154may include a conductive pattern and an insulating material layer covering side surfaces of the conductive pattern.

The upper structure US may further include contact plugs166in contact with the gate pads GP and extending upwardly in the step area SA, and penetrating through the first and second upper insulating layers151and157. For example, in the step area SA, the upper structure US may include the gate contact plugs166contacting the gate pads GP, extending upwardly and penetrating through the first and second upper insulating layers151and157.

The upper structure US may further include a source contact plug163spaced apart from the first and second gate layers112gand124gand in contact with the lower pattern layer103aof the upper substrate103.

In some example embodiments, as the uppermost connection pattern60(e.g., of the lower structure LS) a plurality of uppermost connection patterns may be disposed. For example, the plurality of upper connection patterns60may include a first upper connection pattern60a, a second upper connection pattern60b, and a third upper connection pattern60c. The first upper connection pattern60amay be disposed below the intermediate insulating layer106c, the second upper connection pattern60bmay be disposed below the first inner insulating layer106a, and the third upper connection pattern60cmay be disposed below the second inner insulating layer106b.

The semiconductor device1may further include peripheral contact plugs160in contact with the plurality of uppermost connection patterns60and electrically connected thereto, and at least penetrating through a portion of the lower insulating structure75positioned on a higher level than the plurality of uppermost connection patterns60. The portion of the lower insulating structure75positioned on a higher level than the plurality of uppermost connection patterns60(e.g., the portion of the lower insulating structure75through which the peripheral contact plugs160may penetrate) may include the first insulating layer66, the capping layer69and the second insulating layer72. Upper surfaces of the peripheral contact plugs160may be disposed on a higher level than an uppermost gate layer among the first and second gate layers112gand124g, and lower surfaces of the peripheral contact plugs160may contact and/or partially penetrate the uppermost connection patterns60.

For example, the peripheral contact plugs160may penetrate through portions of the lower insulating structure75positioned on a higher level than the plurality of uppermost connection patterns60. In some example embodiments, the peripheral contact plugs160may penetrate through the first insulating layer66, the capping layer69, and the second insulating layer72and may extend upwardly. Each of the peripheral contact plugs160may have an upper surface disposed on a level higher than that of an uppermost gate layer among the first and second gate layers112gand124g, and may have a lower surface lower than that of a lowermost gate layer among the first and second gate layers112gand124g. The peripheral contact plugs160may include a conductive material pattern and a conductive barrier layer covering side and bottom surfaces of the conductive material pattern. For example, the peripheral contact plugs160may include a metal material pattern159band a conductive barrier layer159acovering side and bottom surfaces of the metal material pattern159b.

The peripheral contact plugs160may include a first peripheral contact plug160ain contact with the first upper connection pattern60a, a second peripheral contact plug160bin contact with the second upper connection pattern60b, and a third peripheral contact plug160cin contact with the third upper connection pattern60c.

In some example embodiments, the peripheral contact plugs160may extend into the uppermost connection patterns60. In these cases, by increasing the contact area between the peripheral contact plugs160and the uppermost connection patterns60, the contact resistance characteristic may be improved.

A height difference between a lower end of the first peripheral contact plug160aand an upper end of the first upper connection pattern60amay be greater than a thickness of the first insulating layer66. The height difference between a lower end of the first peripheral contact plug160aand an upper end of the first upper connection pattern60amay be greater than a thickness of the capping layer69. For example, the depth of the first peripheral contact plug160ain the first upper connection pattern60amay be greater than the thickness of the first insulating layer66, the capping layer69, and/or the first insulating layer66and the capping layer69.

A peripheral contact plug (e.g., the first peripheral contact plug160a) may penetrate through the intermediate insulating layer106c, the first and second capping insulating layers118and130, and the first and second upper insulating layers151and157. Another peripheral contact plug (e.g., the second peripheral contact plug160b) may penetrate through the first inner insulating layer106aand the first through area TA1to extend upwardly and penetrate through the first and second upper insulating layers151and157. A third peripheral contact plug160cmay penetrate through the second inner insulating layer106band the second through area TA2to extend upwardly and penetrate through the first and second upper insulating layers151and157.

The upper structure US may further include a bit line178a, a peripheral connection interconnection178b, a gate connection interconnection178cand a source connection interconnection178d, penetrating through the fourth upper insulating layer175.

The upper structure US may further include a first peripheral upper contact plug172belectrically connecting the first peripheral contact plug160aand the peripheral connection interconnection178b, a second peripheral upper contact plug172celectrically connecting the second peripheral contact plug160band the gate interconnection178c, and a third peripheral upper contact plug172celectrically connecting the third peripheral contact plug160cand the bit line178a. For example, the first peripheral upper contact plug172bmay be between the first peripheral contact plug160aand the peripheral connection interconnection178b; the second peripheral contact plug160bmay be between the second peripheral contact plug160band the gate interconnection178c; and/or the third peripheral upper contact plug172cmay be between the third peripheral contact plug160cand the bit line178a.

The upper structure US may further include a bit line contact plug172aelectrically connecting the bit line178aand the vertical memory structure133, a gate upper contact plug172felectrically connecting the gate contact plug166and the gate interconnection178c, and a source upper contact plug172eelectrically connecting the source contact plug163and the source interconnection178d. For example, the bit line contact plug172amay be between the bit line178aand the vertical memory structure133; the gate upper contact plug172fmay be between the gate contact plug166and the gate interconnection178c; and/or the source upper contact plug172emay be between the source contact plug163and the source interconnection178d.

The first insulating layer66, the capping layer69, and/or the second insulating layer72, described above, may reduce and/or prevent the uppermost connection patterns60from being deformed and/or damaged due to heat generated during a semiconductor process of forming the upper structure US. For example, the upper substrate103and/or the vertical memory structure133may include a doped silicon layer doped with impurities, and a high-temperature semiconductor process, such as annealing for activating impurities in the doped silicon layer may be performed to form the upper substrate103and/or the vertical memory structure133, and the first insulating layer66, the capping layer69, and/or the second insulating layer72may reduce and/or prevent the uppermost connection patterns60from being deformed and/or damaged during the annealing.

Accordingly, the first insulating layer66, the capping layer69, and the second insulating layer72, described above, may improve reliability of the semiconductor device1.

Furthermore, by disposing the first insulating layer66, which may be formed of silicon oxide, between the capping layer69and the uppermost connection patterns60, leakage current between the uppermost connection patterns60adjacent to each other may be prevented and/or mitigated from occurring.

Accordingly, by forming the portion of the lower insulating structure75positioned on a higher level than the uppermost connection patterns60as the first insulating layer66, the capping layer69and the second insulating layer72that are sequentially stacked; the distance between the uppermost connection patterns60may be reduced, and thus the degree of integration of the circuit interconnection structure63may be improved.

Since the degree of integration of the circuit interconnection structure63is increased, the degree of integration of the semiconductor device1may be improved.

Next, with reference toFIG.3, some examples of the vertical memory structure133, the upper substrate103, the first gate layers112g, and the second gate layers124gwill be described.FIG.3is an enlarged view of a portion marked with ‘C’ ofFIG.1A.

Referring toFIG.3, the vertical memory structure133may include an insulating core pattern142, a channel layer139covering side and bottom surfaces of the insulating core pattern142, a pad pattern145disposed on the insulating core pattern142and in contact with the channel layer139, and an information storage structure136covering at least an outer surface of the channel layer139. The information storage structure136may include a first dielectric layer136a, a second dielectric layer136b, and an information storage layer136dbetween the first and second dielectric layers136aand136b. The second dielectric layer136bmay be interposed between the information storage layer136dand the channel layer139.

In some embodiments, the insulating core pattern142may include silicon oxide. For example, the silicon oxide may have been formed by an atomic layer deposition process, and/or the silicon oxide may have voids formed therein. The second dielectric layer136bmay include silicon oxide and/or silicon oxide doped with impurities. The first dielectric layer136amay include at least one of silicon oxide and/or a high dielectric. The information storage layer136dmay include a material capable of storing information, e.g., by trapping a charge. For example, in some embodiments the information storage layer136dmay include silicon nitride. The information storage layer136dmay include regions configured to store information in a semiconductor device such as a flash memory device (for example, memory cells). The channel layer139may include a silicon layer (for example, an undoped silicon layer). The pad pattern145may include at least one of doped polysilicon, metal nitride (e.g., TiN, and/or the like), metal (e.g., W and/or the like), and/or a metal-semiconductor compound (e.g., TiSi and/or the like.). The bit line contact plug172amay contact and/or be electrically connected to the pad pattern145of the vertical memory structure133.

In a portion of the vertical memory structure133extending into the upper substrate103, the first intermediate pattern layer103b1may penetrate through the information storage structure136and contact the channel layer139, and the information storage structure136may be divided into upper and lower portions by the first intermediate pattern layer103b1. In some embodiments, the first intermediate pattern layer103b1may include a silicon layer having an N-type conductivity.

Between an uppermost first gate layer of the first gate layers112gand a lowermost second gate layer of the second gate layers124g, the vertical memory structure133may include a side slope change portion133V. The side slope change portion133V may indicate a part in which the inclination changes between the adjacent upper side surface and the adjacent lower side surface. For example, the side slope change portion133V may refer to a side portion having a gentle slope between a steep upper side surface and a steep lower side surface.

Each of the first gate layers112gmay include a first layer112aand a second layer112b. Each of the second gate layers124gmay include a third layer124aand a fourth layer124b. The first layer112amay cover upper and lower surfaces of the second layer112band may extend between the vertical memory structure133and the second layer112b. The third layer124amay cover upper and lower surfaces of the fourth layer124band may extend between the vertical memory structure133and the fourth layer124b.

In some example embodiments, the first and third layers112aand124amay include a dielectric material, and the second and fourth layers112band124bmay include a conductive material. For example, the first and third layers112aand124amay include a high-k dielectric such as AlO and/or the like, and the second and fourth layers112band124bmay include a conductive material such as TiN, WN, Ti, W, and/or the like.

In some example embodiments, the first and third layers112aand124amay include a first conductive material (e.g., TiN, W and/or the like), and the second and fourth layers112band124bmay include a second conductive material (e.g., Ti, W, and/or the like) different from the first conductive material.

In some example embodiments, the first and second gate layers112gand124gmay be formed of a doped polysilicon, a metal-semiconductor compound (e.g., TiSi, TaSi, CoSi, NiSi, or WSi), a metal nitride (e.g., TiN, TaN, or WN), and/or a metal (e.g., Ti or W).

Next, various modifications of some components of a semiconductor device according to some example embodiments will be described with reference toFIGS.4to8, respectively.FIGS.4to8are partial enlarged views illustrating modified examples of some components of the semiconductor device1described with reference toFIGS.1A to2B, and are partially enlarged views that may represent an area corresponding to the part indicated by ‘A’ inFIG.1A. Hereinafter, various modifications of the semiconductor device according to some example embodiments described with reference toFIGS.4to8may be applied to the cross-sectional structures ofFIGS.1A and1B, even if there is no separate description.

In a modified example, the peripheral contact plugs described above (for example, the peripheral contact plug160inFIG.2A) may be transformed into a peripheral contact plug160′ as inFIG.4. The peripheral contact plug160′ may include a first portion160s1penetrating through the second insulating layer72, a second portion160s2penetrating through the capping layer69, a third portion160s3penetrating through the first insulating layer66, and a fourth portion160s4extending into the uppermost connection pattern60and contacting the uppermost connection pattern60. In this case, the fourth portion160s4may be defined as a portion in contact with the uppermost connection pattern60at a level at and/or lower than the upper surface of the uppermost connection pattern60. In the peripheral contact plug160′, the first portion160s1may be defined as a portion in and/or in contact with the second insulating layer72, the second portion160s2may be defined as a portion in and/or in contact with the capping layer69, and the third portion160s3may be defined as a portion in and/or in contact with the first insulating layer66.

In the peripheral contact plug160′, a maximum width of the first portion160s1may be greater than a minimum width of the second portion160s2.

In the peripheral contact plug160′, the maximum width of the first portion160s1may be greater than a minimum width of the fourth portion160s4.

In the peripheral contact plug160′, a maximum width of the third portion160s3may be greater than a minimum width of the second portion160s2.

In the peripheral contact plug160′, the maximum width of the third portion160s3may be greater than the minimum width of the fourth portion160s4.

In the peripheral contact plug160′, a maximum width of the fourth portion160s4may be less than the maximum width of the third portion160s3.

A height difference between the lower end of the fourth portion160s4of the peripheral contact plug160′ and an upper end of the uppermost connection pattern60may be greater than the thickness of the first insulating layer66. For example, a distance the fourth portion160s4penetrates into the uppermost connection pattern60may be greater than the thickness of the first insulating layer66.

A height difference between the lower end of the fourth portion160s4of the peripheral contact plug160′ and an upper end of the uppermost connection pattern60may be greater than the thickness of the capping layer69. For example, a distance the fourth portion160s4penetrates into the uppermost connection pattern60may be greater than the thickness of the capping layer69.

In the peripheral contact plug160′, a side surface of the second portion160s2may have a concave shape compared to the side surfaces of the first portion160s1and/or the third portion160s3.

In the peripheral contact plug160′, a lateral inclination of the second portion160s2may be different from a lateral inclination of the first portion160s1.

In the peripheral contact plug160′, a side surface of the second portion160s2may have a curved shape, and a side surface of the first portion160s1may have a substantially straight shape.

Hereinafter, unless otherwise described, the peripheral contact plug may be the peripheral contact plug160inFIG.2Aor the peripheral contact plug160′ inFIG.4.

In a modified example, the uppermost connection pattern described above (for example, the uppermost connection pattern60inFIG.2A) may be transformed into an uppermost connection pattern260as inFIG.5. An upper surface260U of the uppermost connection pattern260may extend from upper ends of a first side surface260S1and a second side surface260S2that oppose each other, and at least a portion of the upper surface260U of the uppermost connection pattern260may be curved. For example, the upper surface260U of the uppermost connection pattern260may have a convex shape.

By forming the upper surface260U of the uppermost connection pattern260in a convex shape, the overall volume of the uppermost connection pattern260may be increased and resistance characteristics may be improved.

As illustrated inFIG.5, the peripheral contact plug160′ may include a first portion160s1penetrating through the second insulating layer72′, a second portion160s2penetrating through the capping layer69′, a third portion160s3penetrating through the first insulating layer66′, and a fourth portion160s4penetrating through a portion of the upper surface260U of the uppermost connection pattern260, extending into the uppermost connection pattern260and contacting the uppermost connection pattern260. A lower end of the peripheral contact plug160′ may be disposed on a level lower than an upper end of the uppermost connection pattern260.

The uppermost connection pattern260may have lower surfaces260B1and260B2including portions extending from the first and second side surfaces260S1and260S2of the uppermost connection pattern260. The first and second side surfaces260S1and260S2of the uppermost connection pattern260may be inclined side surfaces in which widths increase from the lower region to the upper region. The lower surfaces260B1and260B2of the uppermost connection pattern260may include a region positioned on a level higher than lower ends of the first and second side surfaces260S1and260S2.

The lower surfaces260B1and260B2of the uppermost connection pattern260may, respectively, include a portion that extends from the first and second side surfaces260S1and260S2of the uppermost connection pattern260while forming an acute angle.

The lower surfaces260B1and260B2of the uppermost connection pattern260may include first portions260B1adjacent to the first and second side surfaces260S1and260S2of the uppermost connection pattern260, and the second portion260B2between the first portions260B1. In the case of the lower surfaces260B1and260B2of the uppermost connection pattern260, lower ends of the first portions260B1may be disposed on a level lower than that of the second portion260B2. In the lower surfaces260B1and260B2of the uppermost connection pattern260, the first portions260B1may be edge portions, and the second portion260B2may be a central portion.

An upper surface57U of the sixth lower insulating layer57may be flat and/or concave.

The capping layer69described above may be transformed into a capping layer69′ having a wavy shaped upper surface as inFIG.5. For example, the capping layer69′ may include a first capping insulating region69_1having a first upper surface, and a second capping insulating region69_2having a second upper surface higher than the first upper surface. In the capping layer69′, the first upper surface of the first capping insulating region69_1may have a concave shape, and the second upper surface of the second capping insulating region69_2may have a convex shape.

The second capping insulating region69_2may overlap the uppermost connection pattern260. The peripheral contact plug160′ may penetrate through a portion of the second capping insulating region69_2of the capping layer69′ and contact the uppermost connection pattern260.

The first insulating layer66described above may be transformed into a first insulating layer66′ having a wavy shaped upper surface as inFIG.5.

The second insulating layer72described above may be transformed into a second insulating layer72′ having a lower surface having a wavy shape as inFIG.5. An upper surface of the second insulating layer72′ may be substantially flat.

In a modified example, the uppermost connection pattern described above (for example, the uppermost connection pattern60inFIG.2A and/or260inFIG.5) may be transformed into an uppermost connection pattern260′ as inFIG.6. For example, the lower surface of the uppermost connection pattern260′ may including a downward convex shape. The upper via54may penetrate through a portion of the lower surface of the uppermost connection pattern260′ and may extend into the uppermost connection pattern260′.

In a modified example, the uppermost connection pattern described above (for example, the uppermost connection pattern60inFIG.2A and/or260inFIG.5) described above may be transformed into an uppermost connection pattern360as inFIG.7. For example, the uppermost connection pattern360may have a concave upper surface360U. The upper surface360U of the uppermost connection pattern360may be concave while extending from upper ends of the first side surface360S1and the second side surface360S2opposing each other.

By forming the upper surface360U of the uppermost connection pattern360to have a concave shape, a leakage current and/or an electric short between adjacent uppermost connection patterns may be mitigated and/or prevented.

The lower surfaces360B1and360B2of the uppermost connection pattern360may have substantially the same shape as the lower surfaces260B1and260B2of the uppermost connection pattern (260ofFIG.5) as described with reference toFIG.5.

An upper surface57U″ of the sixth lower insulating layer57may be flat and/or convex.

The capping layer69described above may be transformed into a capping layer69″ having a wavy-shaped upper surface as illustrated inFIG.7. For example, the capping layer69″ may include a first capping insulating region69_1′ having a first upper surface, and a second capping insulating region69_2′ having a second upper surface on a lower level than the first upper surface. In the capping layer69″, the first upper surface of the first capping insulating region69_1′ may be convex, and the second upper surface of the second capping insulating region69_2′ may be concave.

The second capping insulating region69_2′ may overlap the uppermost connection pattern360. The peripheral contact plug160′ may penetrate through a portion of the second capping insulating region69_2′ of the capping layer69″ and may contact the uppermost connection pattern360.

The first insulating layer66described above may be transformed into a first insulating layer66″ having a wavy-shaped upper surface as inFIG.7.

The second insulating layer72described above may be transformed into a second insulating layer72″ having a lower surface having a wavy shape as illustrated inFIG.7. An upper surface of the second insulating layer72″ may be substantially flat.

In a modified example, the uppermost connection pattern described above (for example, the uppermost connection pattern360inFIG.7) may be transformed into an uppermost connection pattern360′ as inFIG.8. For example, the lower surface of the uppermost connection pattern360′ may have a shape convex downwardly. The upper via54may penetrate through a portion of a lower surface of the uppermost connection pattern360′ and may extend into the uppermost connection pattern360′.

Next, a modified example of the semiconductor device1according to some example embodiments will be described with reference toFIGS.9and10.FIG.9is a cross-sectional view corresponding toFIG.1A, and illustrates a portion transformed from that inFIG.1A, andFIG.10is a partial enlarged view of an area indicated by ‘A1’ ofFIG.9.

In a modified example, referring toFIGS.9and10, the uppermost connection pattern (e.g., the uppermost connection60inFIGS.1A,1B and2A) of the single damascene structure described above and the upper via (e.g. the upper via54ofFIGS.1A,1B and2A) of the single damascene structure may be transformed into a structure460formed as a dual damascene structure as illustrated inFIGS.9and10. For example, the structure460may include an uppermost connection pattern4601and an upper via460V extending from a portion of the uppermost connection pattern4601. The structure460may include a conductive material pattern459band a conductive barrier layer459acovering side and bottom surfaces of the conductive material pattern459b. Accordingly, the uppermost connection pattern4601and the upper via460V may be integrally formed. The conductive material pattern459bmay be and/or include, for example, a metal material pattern.

In some examples, the fifth and sixth lower insulating layers51may be formed of one lower insulating layer457.

The upper surface of the structure460including the uppermost connection pattern4601and the upper via460V that are integrally formed, for example, the upper surface of the uppermost connection pattern4601, may be variously deformed. Hereinafter, various modifications of the upper surface of the uppermost connection pattern4601will be described with reference toFIGS.11and12, respectively.FIGS.11and12are schematic partial enlarged views respectively illustrating a portion modified inFIG.10.

In a modified example, referring toFIG.11, in a structure560including the uppermost connection pattern560I and the upper via560V that are integrally formed, an upper surface560U of the uppermost connection pattern560I may have substantially the same shape as the upper surface260U of the uppermost connection pattern260ofFIG.5described with reference toFIG.5. For example, the upper surface560U of the uppermost connection pattern560I may have an upwardly convex shape.

An upper surface557U of an insulating layer557surrounding the side surface of the structure560may have a concave shape.

The first insulating layer66′, the capping layer69′ and the second insulating layer72′ substantially identical to those described inFIG.5may be disposed on the structure560and the insulating layer557. Also, the peripheral contact plug160′ may be substantially the same as that described with reference toFIG.5and may contact and/or partially penetrate the uppermost connection pattern560I.

In a modified example, referring toFIG.12, in a structure660including an uppermost connection pattern6601and the upper via660V that are integrally formed, an upper surface660U of the uppermost connection pattern6601may have substantially the same shape as the upper surface360U of the uppermost connection pattern360described with reference toFIG.7. For example, the upper surface660U of the uppermost connection pattern6601may have a concave shape. An upper surface657U of an insulating layer657surrounding the side surface of the structure660may have a convex shape.

The first insulating layer66″, the capping layer69″ and the second insulating layer72″ substantially identical to those described inFIG.7may be disposed on the structure660and the insulating layer657. In addition, the peripheral contact plug160′, which is substantially the same as that described with reference toFIG.7, may contact the uppermost connection pattern6601.

Next, a modified example of the semiconductor device1according to some example embodiments will be described with reference toFIGS.13and14.FIG.13is a cross-sectional view corresponding toFIG.1A, and illustrates a portion deformed from that inFIG.1A, andFIG.14is a partial enlarged view of an area indicated by ‘A2’ ofFIG.13.

In a modified example, referring toFIGS.13and14, the first insulating layer (e.g., the first insulating layer66inFIGS.1A to2A), the capping layer (e.g., the capping layer69inFIGS.1A to2A) and/or the second insulating layer (e.g., the second insulating layer72ofFIGS.1A to2A) described above may be transformed into a first insulating layer766, a capping layer769, and/or a second insulating layer772as inFIGS.13and14.

The second insulating layer772may have a thickness greater than a thickness of each of the first insulating layer766and the capping layer769. The first insulating layer766may have a thickness greater than a thickness of the capping layer769. In some example embodiments, the first insulating layer766may have a thickness substantially equal to the thickness of the capping layer769.

In some example embodiments, the thickness of the capping layer769may range from about 150 Å to about 500 Å.

In some example embodiments, the thickness of the capping layer769may range from about 300 Å to about 400 Å.

The above-described peripheral contact plug (e.g., the peripheral contact plugs160inFIG.2and/or160′ inFIG.4) may be transformed into a peripheral contact plug160″ penetrating through the first insulating layer766, the capping layer769, and the second insulating layer772as inFIGS.13and14. The peripheral contact plug160″ may include a first portion160s1penetrating through the second insulating layer72may include a first portion160s1penetrating through the second insulating layer72, a second portion160s2penetrating through the capping layer69, a third portion160s3penetrating through the first insulating layer66, and a fourth part160s4extending into the uppermost connection pattern60and in contact with the uppermost connection pattern60, similar to the peripheral contact plug140′ described inFIG.4.

For example, in the peripheral contact plug160″, a maximum width of the first portion160s1may be greater than a minimum width of the second portion160s2; the maximum width of the first portion160s1may be greater than a minimum width of the fourth portion160s4. In addition, a maximum width of the third portion160s3may be greater than a minimum width of the second portion160s2. In the peripheral contact plug160″, the maximum width of the third portion160s3may be greater than the minimum width of the fourth portion160s4, and the maximum width of the third portion160s3may be greater than the maximum width of the fourth portion160s4. In the peripheral contact plug160″, the side surface of the second portion160s2may be concave compared to the sides of the first portion1690s1and the third portion160s3.

The first insulating layer766, the capping layer769, and the second insulating layer772may replace the first insulating layer (e.g., the first insulating layer66inFIGS.2A,4and/or10), the capping layer (e.g., the capping layer69ofFIGS.2A,4and/or10), and/or the second insulating layer (e.g., the second insulating layer72ofFIGS.2A,4and/or10), which are described above. Similarly, the first insulating layer766, the capping layer769, and the second insulating layer772may replace the first insulating layer (66′ inFIGS.5,6and11), the capping layer (69′ inFIGS.5,6and11) and the second insulating layer (72′ inFIGS.5,6and11), which are described with reference toFIGS.5,6and11, and may replace the first insulating layer (66′ inFIGS.7,8and12), the capping layer (69′ inFIGS.7,8and12) and the second insulating layer (72′ inFIGS.7,8and12), which are described with reference toFIGS.7,8and12.

Hereinafter, an example in which the first insulating layer766, the capping layer769, and the second insulating layer772replace the first insulating layer66′ inFIG.5, the capping layer69′ inFIG.5, and the second insulating layer72′ inFIG.5will be described with reference toFIG.15. In addition, an example in which the first insulating layer766, the capping layer769, and the second insulating layer772replace the first insulating layer66″ inFIG.7, the capping layer69inFIG.7, and the second insulating layer72″ inFIG.7will be described with reference toFIG.16.

Referring toFIG.15, the first insulating layer (e.g., the first insulating layer66′ inFIG.5), the capping layer (e.g., the capping layer69′ inFIG.5), and the second insulating layer (e.g., the second insulating layer72′ inFIG.5) may be replaced by a first insulating layer766′, a capping layer769′ and a second insulating layer772′, respectively. The first insulating layer766′, the capping layer769′ and the second insulating layer772′ may have the same thickness as that of the first insulating layer766inFIGS.13and/or14, the capping layer769inFIGS.13and/or14, and the second insulating layer772inFIGS.13and/or14.

The first insulating layer766′ may have a wavy upper surface similar to the upper surface of the first insulating layer66′ described with reference toFIG.5, and the capping layer769′ may have the same shape and same thickness as the capping layer69′ described with reference toFIG.5, and the second insulating layer772′ may have a wavy patterned lower surface and a flat upper surface.

Referring toFIG.16, a first insulating layer766″, a capping layer769″ and a second insulating layer772″ may be disposed, which may replace the first insulating layer (e.g., the insulating layer66″ inFIG.7), the capping layer (e.g., the capping layer69″ inFIG.7) and the second insulating layer (e.g., the second insulating layer72″ inFIG.7), respectively. The first insulating layer766″, the capping layer769″, and the second insulating layer772″ may have the same thickness of that of the first insulating layer766ofFIGS.13and/or14), the capping layer769inFIGS.13and/or14), and the second insulating layer772inFIGS.13and/or14.

The first insulating layer766″ may have a wavy upper surface that is the same as that of the upper surface of the first insulating layer66″ described with reference toFIG.7, and the capping layer769″ may have the same shape and same thickness as the capping layer69″ described inFIG.7, and the second insulating layer772″ may have a wavy patterned lower surface and a flat upper surface.

Referring toFIG.17, the capping layer (e.g., the capping layer69inFIGS.2A,4and10,69′ inFIGS.5,6and11,69″ inFIGS.7,8and12,769inFIG.14,769′ inFIG.15,769″ inFIG.16) may be replaced with a capping layer869including at least a first layer869a, a second layer869b, and a third layer869cthat are sequentially stacked. For example, the first and third capping layers869aand869cmay be formed of silicon nitride, and the second layer869bmay be formed of silicon oxide.

The above-described peripheral contact plug (e.g., the peripheral contact plug160inFIG.4) may be replaced with a peripheral contact plug860that includes an upper portion160s1penetrating through the second insulating layer72, second portions860s2a,860s2band860s2cpenetrating through the capping layer869, a third portion860s3penetrating through the first insulating layer66, and a fourth part860s4extending into the uppermost connection pattern60and contacting the uppermost connection pattern60. In the peripheral contact plug860, the second portions860s2a,860s2b, and860s2cpenetrating through the capping layer869may include a lower portion860s2apenetrating through the first layer869a, an intermediate portion860s2bpenetrating through the second layer869b, and an upper portion860s2cpenetrating through the third layer869c. In the peripheral contact plug860, the lower portion860s2and the upper portion860s2cmay have concave sides.

Next, an example of a method of forming a semiconductor device according to some example embodiments will be described with reference toFIG.18.FIG.18is a process flow diagram illustrating an example of a method of forming a semiconductor device according to some example embodiments.

Referring toFIG.18, a circuit element may be formed on a semiconductor substrate (S10). The circuit element may include the circuit element21formed on the semiconductor substrate3as described inFIGS.1A,1B and2B. An insulating liner covering the circuit element may be formed (S20). The insulating liner may be the insulating liner24as described inFIGS.1A,1B and2B.

A plurality of connection patterns positioned on different levels may be formed (S30). The plurality of connection patterns may be the plurality of connection patterns36,48, and60as described with reference toFIGS.1A and1B.

A first insulating layer may be formed (S40). The first insulating layer may be the first insulating layer66as described with reference toFIGS.1A,1B and2A. A capping layer may be formed on the first insulating layer (S50). The capping layer may be the capping layer69as described inFIGS.1A,1B and2A. A second insulating layer may be formed on the capping layer (S60). The second insulating layer may be the second insulating layer72as described with reference toFIGS.1A,1B and2A.

An upper structure including three-dimensionally arranged memory cells may be formed (S70). The upper structure may be the upper structure US as described with reference toFIGS.1A and1B. A contact plug electrically connected to an uppermost connection pattern among the plurality of connection patterns may be formed (S80). The contact plugs may be the peripheral contact plugs160as described with reference toFIGS.1A,1B, and2A.

Next, a data storage system including a semiconductor device according to an example embodiment will be described with reference toFIGS.19and20and21, respectively.

FIG.19is a diagram schematically illustrating a data storage system including a semiconductor device according to some example embodiments.

Referring toFIG.19, a data storage system1000according to some example embodiments may include a semiconductor device1100, and a controller1200electrically connected to the semiconductor device1100to control the semiconductor device1100. The data storage system1000may be a storage device including the semiconductor device1100and/or an electronic device including the storage device. For example, the data storage system1000may be a solid state drive (SSD) device, a universal serial bus (USB), a computing system, a medical device, a communication device, and/or the like including the semiconductor device1100.

In an example embodiment, the data storage system1000may be an electronic system that stores data.

The semiconductor device1100may include a first structure1100F and a second structure1100S on the first structure1100F. The semiconductor device1100may be a semiconductor device according to any one of the example embodiments described above with reference toFIGS.1to17.

For example, the first structure1110F may be the lower structure LS described with reference toFIGS.1A and1B, and the second structure1100S may be the upper structure US described with reference toFIGS.1A and1B.

The first structure1100F may be a peripheral circuit structure including a decoder circuit1110, a page buffer1120, and/or a logic circuit1130. For example, the first structure1100F may include the above-described circuit element21(e.g., inFIGS.1A,1B, and2B). The circuit element21(e.g., inFIGS.1A,1B and2B) may be a transistor constituting a peripheral circuit structure including a decoder circuit1110, a page buffer1120, and a logic circuit1130.

The second structure1100S may be a memory structure including a bit line BL, a common source line CSL, word lines WL, first and second upper gate lines UL1and UL2, first and second lower gate lines LL1and LL2, and memory cell strings CSTR between the bit line BL and the common source line CSL.

The upper substrate103described above may include a silicon layer having an N-type conductivity. In some example embodiments, the silicon layer having an N-type conductivity may be and/or include the common source line CSL. For example, the first intermediate pattern layer103b1(e.g., inFIG.3) in contact with the channel layer139(e.g., inFIG.3) and the lower pattern layer103a(e.g., inFIG.3) in contact with the first intermediate pattern layer103b1may be formed of a silicon layer having an N-type conductivity, and may be the common source line CSL.

In the second structure1100S, each of the memory cell strings CSTR may include lower transistors LT1and LT2adjacent to the common source line CSL, upper transistors UT1and UT2adjacent to the bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1and LT2and the upper transistors UT1and UT2. The number of the lower transistors LT1and LT2and the number of the upper transistors UT1and UT2may be variously modified depending on example embodiments.

In some example embodiments, the upper transistors UT1and UT2may include a string select transistor, and the lower transistors LT1and LT2may include a ground select transistor. The lower gate lines LL1and LL2may be gate electrodes of the lower transistors LT1and LT2, respectively. The word lines WL may be gate electrodes of the memory cell transistors MCT, and the upper gate lines UL1and UL2may be gate electrodes of the upper transistors UT1and UT2, respectively.

The first and second gate layers (e.g.,112gand124ginFIGS.1A and1B) described above may constitute the lower gate lines LL1and LL2, the word lines WL, and the upper gate lines UL1and UL2.

In some example embodiments, the lower transistors LT1and LT2may include a lower erase control transistor LT1and a ground select transistor LT2connected in series. The upper transistors UT1and UT2may include a string select transistor UT1and an upper erase control transistor UT2connected in series. At least one of the lower erase control transistor LT1and the upper erase control transistor UT1may be used for an erase operation of deleting data stored in the memory cell transistors MCT using, for example, a gate induced leakage current (GIDL) phenomenon.

The common source line CSL, the first and second lower gate lines LL1and LL2, the word lines WL, and the first and second upper gate lines UL1and UL2may be electrically connected to the decoder circuit1110through first connection interconnections1115extending from the first structure1100F to the second structure1100S.

The bit lines BL may be electrically connected to the page buffer1120through second connection interconnections1125extending from the first structure1100F to the second structure1100S. The bit lines BL may be the bit lines178aofFIGS.1A and1Bdescribed above.

In the first structure1100F, the decoder circuit1110and the page buffer1120may perform a control operation on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit1110and the page buffer1120may be controlled by a logic circuit1130.

The semiconductor device1100may further include an input/output pad1101. The semiconductor device1100may communicate with the controller1200through the input/output pad1101electrically connected to the logic circuit1130. The input/output pad1101may be electrically connected to the logic circuit1130through an input/output connection wiring1135extending from the first structure1100F to the second structure1100S. Accordingly, the controller1200may be electrically connected to the semiconductor device1100through the input/output pad1101, and may control the semiconductor device1100.

The controller1200may include a processor1210, a NAND controller1220, and a host interface1230. In some embodiments, the data storage system1000may include a plurality of semiconductor devices1100. In this case, the controller1200may control the plurality of semiconductor devices1100.

The processor1210may control the overall operation of the data storage system1000including the controller1200. The processor1210may operate according to a predetermined (and/or otherwise determined) firmware, and may access the semiconductor device1100by controlling the NAND controller1220. The NAND controller1220may include a NAND interface1221that processes communication with the semiconductor device1100. Through the NAND interface1221, a control command for controlling the semiconductor device1100, data to be written to the memory cell transistors MCT of the semiconductor device1100, and data to be read from the memory cell transistors MCT may be transmitted. The host interface1230may provide a communication function between the data storage system1000and an external host. When receiving a control command from an external host through the host interface1230, the processor1210may control the semiconductor device1100in response to the control command.

The controller1200and/or its components (e.g., the processor1210, NAND controller1220, and/or host interface1230) may include and/or be included in processing circuitry such as hardware including logic circuits; a hardware/software combination such as a processor executing software; or a combination thereof. For example, the processing circuitry more specifically may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), and programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc.

FIG.20is a perspective view schematically illustrating a data storage system including a semiconductor device according to some example embodiments.

Referring toFIG.20, a data storage system2000according to some example embodiments may include a main board2001, a controller2002mounted on the main board2001, one or more semiconductor packages2003, and a DRAM2004. The semiconductor package2003and the DRAM2004may be connected to the controller2002by wiring patterns2005formed on the main board2001.

The main board2001may include a connector2006including a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector2006may vary depending on a communication interface between the data storage system2000and the external host. In some example embodiments, the data storage system2000may communicate with an external host according to any one of interfaces such as Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), M-Phy for Universal Flash Storage (UFS), and/or the like. In some example embodiments, the data storage system2000may be operated by power supplied from an external host through the connector2006. The data storage system2000may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from the external host, to the controller2002and the semiconductor package2003.

The controller2002may write data to and/or read data from the semiconductor package2003, and may improve the operating speed of the data storage system2000. In some embodiments, the controller2002may be, include, and or be included in, the controller1200ofFIG.19.

The DRAM2004may be a buffer memory for reducing a speed difference between the semiconductor package2003serving as a data storage space and an external host. The DRAM2004included in the data storage system2000may also operate as a kind of cache memory, and may provide a space for temporarily storing data in a control operation for the semiconductor package2003. When the DRAM2004is included in the data storage system2000, the controller2002may further include a DRAM controller for controlling the DRAM2004, in addition to the NAND controller for controlling the semiconductor package2003.

The semiconductor package2003may include first and second semiconductor packages2003aand2003bspaced apart from each other. Each of the first and second semiconductor packages2003aand2003bmay be a semiconductor package including a plurality of semiconductor chips2200. Each of the semiconductor chips2200may include the semiconductor device according to the example embodiments described above with reference toFIGS.1to17.

Each of the first and second semiconductor packages2003aand2003bmay include a package substrate2100, semiconductor chips2200on the package substrate2100, adhesive layers2300disposed on lower surfaces of the semiconductor chips2200respectively, a connection structure2400electrically connecting the semiconductor chips2200and the package substrate2100, and a molding layer2500covering the semiconductor chips2200and the connection structure2400, on the package substrate2100.

The package substrate2100may be a printed circuit board including upper package pads2130. Each of the semiconductor chips2200may include an input/output pad2210.

In example embodiments, the connection structure2400may be a bonding wire electrically connecting the input/output pad2210and the package upper pads2130. Accordingly, in each of the first and second semiconductor packages2003aand2003b, the semiconductor chips2200may be electrically connected to each other by a bonding wiring method, and may be electrically connected to the package upper pads2130of the package substrate2100. According to example embodiments, in each of the first and second semiconductor packages2003aand2003b, the semiconductor chips2200may also be electrically connected to each other by a connection structure including a through-silicon via (TSV), instead of the bonding wiring-type connection structure2400.

In example embodiments, the controller2002and the semiconductor chips2200may be included in a single package. For example, the controller2002and the semiconductor chips2200may be mounted on a separate interposer substrate different from the main substrate2001, and the controller2002and the semiconductor chips2200may be connected to each other by the wiring formed on the interposer substrate.

FIG.21illustrates cross-sectional views schematically illustrating a semiconductor package according to an example embodiment.FIG.21illustrates an example embodiment of the semiconductor package2003ofFIG.20, and conceptually illustrates a region of the semiconductor package2003, taken along line I-I′ ofFIG.20.

Referring toFIG.21, in a semiconductor package2003, a package substrate2100may be a printed circuit board. The package substrate2100may include a package substrate body portion2120, package upper pads2130disposed on the upper surface of the package substrate body portion2120, lower pads2125disposed on the lower surface of the package substrate body portion2120or exposed through the lower surface thereof, and internal wirings2135electrically connecting the upper pads2130and the lower pads2125inside of the package substrate body portion2120. The upper pads2130may be electrically connected to the connection structures2400. The lower pads2125may be connected to wiring patterns2005of a main substrate2010of a data storage system2000through conductive connection portions2800.

Each of semiconductor chips2200may include a semiconductor substrate3010, and a first structure3100and a second structure3200that are sequentially stacked on the semiconductor substrate3010. The first structure3100may include a peripheral circuit region including peripheral interconnections3110. The second structure3200may include a common source line3205, a gate stack structure3210on the common source line3205, memory channel structures3220and separation structures3230penetrating through the gate stack structure3210, bit lines3240electrically connected to the memory channel structures3220, and gate contact plugs (106inFIG.2A) electrically connected to the word lines WL of the gate stack structure3210. The first structure3100may include the first structure1100F ofFIG.19, and the second structure3200may include the second structure1100S ofFIG.19.

Each of the semiconductor chips2200may include a through interconnection3245electrically connected to the peripheral interconnections3110of the first structure3100and extending into the second structure3200. The through interconnection3245may penetrate through the gate stack structure3210and may be further disposed outside of the gate stack structure3210.

Each of the semiconductor chips2200may further include an input/output connection wiring3265which is electrically connected to the peripheral interconnections3110of the first structure3100and extends into the second structure3200, and an input/output pad2210electrically connected to the input/output connection wiring3265.

InFIG.21, a partially enlarged portion of the semiconductor device1indicated by reference numeral1is to describe that the semiconductor chips2200ofFIG.21may be modified to include the cross-sectional structure as inFIG.1A. Accordingly, each of the semiconductor chips2200may include the semiconductor device1according to the example embodiments described above with reference toFIGS.1A to17.

As set forth above, according to some example embodiments, a circuit interconnection structure including a plurality of connection patterns disposed on different levels on a semiconductor substrate, and a lower insulating structure covering the circuit interconnection structure, may be disposed. An upper structure, including a stack structure including interlayer insulating layers and gate electrodes alternately stacked on the lower insulating structure in a vertical direction, and a vertical memory structure penetrating through the stack structure in the vertical direction, may be disposed. The portion of the lower insulating structure located on a level higher than the uppermost connection pattern may include a first insulating layer, a capping layer and a second insulating layer sequentially stacked. The capping layer may be formed of a material different from the material of the first insulating layer and the second insulating layer. The first insulating layer, the capping layer, and the second insulating layer sequentially stacked in this manner may protect the circuit element and the circuit interconnection structure from a semiconductor process of forming the upper structure. For example, the first insulating layer, the capping layer, and the second insulating layer may reduce and/or prevent the uppermost connection pattern from being deformed or damaged by heat generated during a semiconductor process of forming the upper structure.

In addition, by disposing the first insulating layer between the capping layer and the uppermost connection pattern, leakage current between adjacent uppermost connection patterns may be mitigated and/or prevented.

Accordingly, the degree of integration of the circuit interconnection structure may be improved by forming the portion of the lower insulating structure positioned on a level higher than the uppermost connection pattern, as the first insulating layer, the capping layer and the second insulating layer that are sequentially stacked. Therefore, the degree of integration of the semiconductor device may be improved.