SEMICONDUCTOR STRUCTURE

A semiconductor structure including a substrate and protection structures is provided. The substrate includes a die region. The die region includes corner regions. The protection structures are located in the corner region. Each of the protection structures has a square top-view pattern. The square top-view patterns located in the same corner region have various sizes.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan application serial no. 111128340, filed on Jul. 28, 2022. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND

Technical Field

The invention relates to a semiconductor structure, and particularly relates to a semiconductor structure having a protection structure.

Description of Related Art

When the wafer is diced, the cracks may be created in the die. If the crack extends into the device region of the die, it will cause damage to the circuit in the device region. Therefore, the seal ring is disposed outside the device region to prevent the crack from extending into the device region of the die. However, how to further prevent the crack from extending into the device region of the die is the goal of continuous efforts.

SUMMARY

The invention provides a semiconductor structure, which can prevent the circuit in the device region from being damaged.

The invention provides a semiconductor structure, which includes a substrate and protection structures. The substrate includes a die region. The die region includes corner regions. The protection structures are located in the corner region. Each of the protection structures has a square top-view pattern. The square top-view patterns located in the same corner region have various sizes.

According to an embodiment of the invention, in the semiconductor structure, the die region may further include a device region. The corner regions are located outside the device region.

According to an embodiment of the invention, in the semiconductor structure, the size relationship of two adjacent square top-view patterns may be an increasing relationship in a direction away from the device region.

According to an embodiment of the invention, in the semiconductor structure, the structures may include a first protection structure and a second protection structure. The second protection structure is located between the first protection structure and the device region.

According to an embodiment of the invention, in the semiconductor structure, the size of the square top-view pattern of the first protection structure may be greater than the size of the square top-view pattern of the second protection structure.

According to an embodiment of the invention, in the semiconductor structure, the protection structures may further include a third protection structure. The third protection structure is located between the second protection structure and the device region.

According to an embodiment of the invention, in the semiconductor structure, the size of the square top-view pattern of the first protection structure may be greater than the size of the square top-view pattern of the second protection structure, and the size of the square top-view pattern of the second protection structure may be greater than the size of the square top-view pattern of the third protection structure.

According to an embodiment of the invention, the semiconductor structure may further include at least one seal ring structure. The seal ring structure is located between the corner region and the device region.

According to an embodiment of the invention, in the semiconductor structure, the seal ring structure may surround the device region.

According to an embodiment of the invention, in the semiconductor structure, the top-view shape of the edge profile of the seal ring structure may be an octagon.

According to an embodiment of the invention, the semiconductor structure may further include dummy insertion structures. The dummy insertion structures are located in the empty region of the device region.

According to an embodiment of the invention, in the semiconductor structure, two adjacent square top-view patterns may have the same size.

According to an embodiment of the invention, in the semiconductor structure, the top-view shape of the corner region may be a triangle.

According to an embodiment of the invention, the semiconductor structure may further include dummy insertion structures. The dummy insertion structures are located in the corner region.

According to an embodiment of the invention, in the semiconductor structure, the dummy insertion structure may be located between the protection structure and the device region.

According to an embodiment of the invention, in the semiconductor structure, the size of the top-view pattern of the dummy insertion structure may be smaller than the size of the square top-view pattern of the protection structure.

According to an embodiment of the invention, in the semiconductor structure, the substrate may further include a scribe line region. The scribe line region is located outside the die region.

According to an embodiment of the invention, the semiconductor structure may further include dummy insertion structures. The dummy insertion structures are located in the empty region of the scribe line region.

According to an embodiment of the invention, the semiconductor structure may further include an alignment mark. The alignment mark is located in the scribe line region.

According to an embodiment of the invention, in the semiconductor structure, the alignment mark may be adjacent to the corner region.

Based on the above description, the semiconductor structure according to the invention includes the protection structures, each of the protection structures has the square top-view pattern, and the square top-view patterns located in the same corner region have various sizes. Therefore, the crack can be prevented from extending into the device region of the die region by the protection structures located in the corner region, thereby preventing the circuit in the device region from being damaged. In addition, the protection structures located in the corner region have the effect of relieving stress.

In order to make the aforementioned and other objects, features and advantages of the invention comprehensible, several exemplary embodiments accompanied with drawings are described in detail below.

DESCRIPTION OF THE EMBODIMENTS

The embodiments are described in detail below with reference to the accompanying drawings, but the embodiments are not intended to limit the scope of the invention. For the sake of easy understanding, the same components in the following description will be denoted by the same reference symbols. In addition, the drawings are for illustrative purposes only and are not drawn to the original dimensions. Furthermore, the features in the top view and the features in the cross-sectional view are not drawn to the same scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG.1Ais a top view illustrating a semiconductor structure according to some embodiments of the invention.FIG.1Bis a partially enlarged view of the region R3inFIG.1A.FIG.1Cis a cross-sectional view taken along section line I-I′ inFIG.1B. In the top view of the present embodiment, some components in the cross-sectional view may be omitted to clearly illustrate the configuration relationship between the components in the top view. Furthermore, in the cross-sectional view of the present embodiment, some components in the top view may be omitted to clearly illustrate the configuration relationship between the components in the cross-sectional view.

Referring toFIG.1A,FIG.1B, andFIG.1C, a semiconductor structure10includes a substrate100and protection structures102. The substrate100may be a semiconductor substrate such as a silicon substrate. The substrate100includes a die region R1. In some embodiments, the die region R1may be a region intended to be diced into a die. The die region R1includes corner regions R11. In some embodiments, the top-view shape of the corner region R11may be a triangle. In addition, the die region R1may further include a device region R12. The corner regions Ru are located outside the device region R12. In some embodiments, the top-view shape of the device region R12may be an octagon, but the invention is not limited thereto. Furthermore, the substrate100may further include a scribe line region R2. The scribe line region R2is located outside the die region R1.

The protection structures102are located in the corner region R11. Each of the protection structures102has a square top-view pattern TP. The protection structure102is disposed on the substrate100. In the present embodiment, the protection structures102may include a protection structure102A and a protection structure102B. The protection structure102B is located between the protection structure102A and the device region R12. The protection structure102A may have a square top-view pattern TP1. The protection structure102B may have a square top-view pattern TP2. In some embodiments, the protection structure102A and the protection structure102B may be interconnect structures. In some embodiments, the interconnect structure may include a contact, a via, a conductive line, or a combination thereof. The material of the protection structure102A and the material of the protection structure102B are, for example, copper, tungsten, aluminum, or a combination thereof. Moreover, the number of the protection structures102A and the number of the protection structures102B are not limited to those in the figure. One of ordinary skill in the art may determine the number of the protection structures102A and the number of the protection structures102B according to the product requirement.

In addition, the square top-view patterns TP located in the same corner region R11have various sizes. In the text, the term “dimension” may refer to the side length or area of the square top-view pattern. For example, the size of the square top-view pattern TP1of the protection structure102A may be greater than the size of the square top-view pattern TP2of the protection structure102B, so that the square top-view patterns TP located in the same corner region R11have various sizes. In the present embodiment, the square top-view patterns TP located in the same corner region R11may have two sizes, but the invention is not limited thereto. In other embodiments, the square top-view patterns TP located in the same corner region R11may have three or more sizes. As long as the square top-view patterns TP located in the same corner region R11have various sizes, it falls within the scope of the invention.

In some embodiments, the size relationship of two adjacent square top-view patterns TP may be an increasing relationship in a direction away from the device region R12. For example, the size relationship of the square top-view pattern TP2and the square top-view patterns TP1adjacent to each other may be an increasing relationship in a direction D11away from the device region R12. The size relationship of the square top-view pattern TP2and the square top-view patterns TP1adjacent to each other may be an increasing relationship in a direction D12away from the device region R12. The size relationship of the square top-view pattern TP2and the square top-view patterns TP1adjacent to each other may be an increasing relationship in a direction D13away from the device region R12. In some embodiments, two adjacent square top-view patterns TP may have the same size. For example, two adjacent square top-view patterns TP2may have the same size.

In some embodiments, the semiconductor structure10may further include an isolation structure104. The isolation structure104is disposed in the substrate100. The isolation structure104is, for example, a shallow trench isolation (STI) structure. The material of the isolation structure104is, for example, silicon oxide.

In some embodiments, the semiconductor structure10may further include a dielectric layer106. The dielectric layer106is disposed on the substrate100. The protection structure102may be disposed in the dielectric layer106. In some embodiments, the dielectric layer106may be a multilayer structure. The material of the dielectric layer106is, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

In some embodiments, the semiconductor structure10may further include at least one seal ring structure108. The seal ring structure108may be disposed in the dielectric layer106. The seal ring structure108is located between the corner region Ru and the device region R12. The seal ring structure108may be located in the die region R1. The seal ring structure108may surround the device region R12. In some embodiments, the top view shape of the edge profile of the seal ring structure108may be an octagon. In some embodiments, the seal ring structure108may be an interconnect structure. In some embodiments, the interconnect structure may include a contact, a via, a conductive line, or a combination thereof. The material of the seal ring structure108is, for example, copper, tungsten, aluminum, or a combination thereof. In the present embodiment, the number of the seal ring structures108is, for example, two, but the invention is not limited thereto. As long as the semiconductor structure10includes at least one seal ring structure108, it falls within the scope of the invention.

In some embodiments, the semiconductor structure10may further include dummy insertion structures110. The dummy insertion structures110are located in the corner region R11. The dummy insertion structure110may be located between the protection structure102and the device region R12. The size of the top-view pattern DP of the dummy insertion structure110may be smaller than the size of the square top-view pattern TP of the protection structure102. In some embodiments, the top-view pattern DP of the dummy insertion structure110may be a square. In some embodiments, the dummy insertion structure110may be an interconnect structure. In some embodiments, the interconnect structure may include a contact, a via, a conductive line, or a combination thereof. The material of the dummy insertion structure110is, for example, copper, tungsten, aluminum, or a combination thereof. In addition, the number of the dummy insertion structures110is not limited to the number in the figure. One of ordinary skill in the art may determine the number of the dummy insertion structures110according to the product requirement.

In some embodiments, the semiconductor structure10may further include dummy insertion structures112. The dummy insertion structures112are located in the empty region of the device region R12. In some embodiments, the dummy insertion structure112may be an interconnect structure. In some embodiments, the interconnect structure may include a contact, a via, a conductive line, or a combination thereof. The material of the dummy insertion structure112is, for example, copper, tungsten, aluminum, or a combination thereof. In addition, the number of the dummy insertion structures112is not limited to the number in the figure. One of ordinary skill in the art may determine the number of the dummy insertion structures112according to the product requirement.

In some embodiments, the semiconductor structure10may further include dummy insertion structures114. The dummy insertion structures114are located in the empty region of the scribe line region R2. In some embodiments, the dummy insertion structure114may be an interconnect structure. In some embodiments, the interconnect structure may include a contact, a via, a conductive line, or a combination thereof. The material of the dummy insertion structure114is, for example, copper, tungsten, aluminum, or a combination thereof. In addition, the number of the dummy insertion structures114is not limited to the number in the figure. One of ordinary skill in the art may determine the number of the dummy insertion structures114according to the product requirement.

In some embodiments, the semiconductor structure10may further include an alignment mark116. The alignment mark116is located in the scribe line region R2. The alignment mark116may be adjacent to the corner region R11. In some embodiments, the top-view shape of the alignment mark116may be an L-shape. In some embodiments, the material of the alignment mark116is, for example, metal.

In some embodiments, the semiconductor structure10may further include a via118. The via118is disposed in dielectric layer106and on the seal ring structure108. In some embodiments, the via118may be electrically connected to the seal ring structure108. For example, the via118may be electrically connected to the seal ring structure108A. In some embodiments, the material of the via118is, for example, aluminum.

In some embodiments, the semiconductor structure10may further include a redistribution layer (RDL)120. The redistribution layer120is disposed on the via118. In some embodiments, the redistribution layer120may be electrically connected to the seal ring structure108. For example, the redistribution layer120may be electrically connected to the seal ring structure108A by the via118. In some embodiments, the material of the redistribution layer120is, for example, aluminum.

In some embodiments, the semiconductor structure10may further include a passivation layer122. The passivation layer122may be a single-layer structure or a multilayer structure. The material of the passivation layer122is, for example, silicon oxide, silicon nitride, or a combination thereof. In the present embodiment, the passivation layer122may include a passivation layer122A and a passivation layer122B, but the invention is not limited thereto. The passivation layer122A is disposed on the dielectric layer106and the redistribution layer120. The material of the passivation layer122A is, for example, silicon oxide. The passivation layer122B is disposed on the passivation layer122A. The material of the passivation layer122B is, for example, silicon nitride.

Based on the above embodiments, the semiconductor structure10includes the protection structures102, each of the protection structures102has the square top-view pattern TP, and the square top-view patterns TP located in the same corner region R11have various sizes. Therefore, the crack can be prevented from extending into the device region R12of the die region R1by the protection structures102located in the corner region R11, thereby preventing the circuit in the device region R12from being damaged. In addition, the protection structures102located in the corner region R11have the effect of relieving stress.

FIG.2Ais a top view illustrating a semiconductor structure according to other embodiments of the invention.FIG.2Bis a partially enlarged view of the region R4inFIG.2A.FIG.2Cis a cross-sectional view taken along section line II-II′ inFIG.2B. In the top view of the present embodiment, some components in the cross-sectional view may be omitted to clearly illustrate the configuration relationship between the components in the top view. Furthermore, in the cross-sectional view of the present embodiment, some components in the top view may be omitted to clearly illustrate the configuration relationship between the components in the cross-sectional view.

Referring toFIG.1AtoFIG.1CandFIG.2AtoFIG.2C, the difference between a semiconductor structure20ofFIG.2AtoFIG.2Cand the semiconductor structure10ofFIG.1AtoFIG.1Cis as follow. In the semiconductor structure20, the protection structures102may further include a protection structure102C. The protection structure102C is located between the protection structure102B and the device region R12. The protection structure102C may have a square top-view pattern TP3. In some embodiments, the protection structure102C may be an interconnect structure. In some embodiments, the interconnect structure may include a contact, a via, a conductive line, or a combination thereof. The material of the protection structure102C is, for example, copper, tungsten, aluminum, or a combination thereof. In addition, the number of the protection structures102C is not limited to the number in the figure. One of ordinary skill in the art may determine the number of the protection structures102C according to the product requirement.

The size of the square top-view pattern TP1of the protection structure102A may be greater than the size of the square top-view pattern TP2of the protection structure102B, and the size of the square top-view pattern TP2of the protection structure102B may be greater than the size of the square top-view pattern TP3of the protection structure102C, so that the square top-view patterns TP located in the same corner region R11have various sizes. In the present embodiment, the square top-view patterns TP located in the same corner region R11may have three sizes, but the invention is not limited thereto. As long as the square top-view patterns TP located in the same corner region R11have various sizes, it falls within the scope of the invention.

In the semiconductor structure20, the size relationship of two adjacent square top-view patterns TP may be an increasing relationship in a direction away from the device region R12. For example, the size relationship of the square top-view pattern TP2and the square top-view patterns TP1adjacent to each other may be an increasing relationship in a direction D11away from the device region R12. The size relationship of the square top-view pattern TP3and the square top-view patterns TP2adjacent to each other may be an increasing relationship in the direction D11away from the device region R12. The size relationship of the square top-view pattern TP2and the square top-view patterns TP1adjacent to each other may be an increasing relationship in a direction D12away from the device region R12. The size relationship of the square top-view pattern TP3and the square top-view patterns TP2adjacent to each other may be an increasing relationship in the direction D12away from the device region R12. The size relationship of the square top-view pattern TP2and the square top-view patterns TP1adjacent to each other may be an increasing relationship in a direction D13away from the device region R12. The size relationship of the square top-view pattern TP3and the square top-view patterns TP2adjacent to each other may be an increasing relationship in the direction D13away from the device region R12. In the semiconductor structure20, two adjacent square top-view patterns TP may have the same size. For example, two adjacent square top-view patterns TP2may have the same size. Furthermore, two adjacent square top-view patterns TP3may have the same size.

In addition, in the semiconductor structure10ofFIG.1and the semiconductor structure20ofFIG.2, the same or similar components are denoted by the same reference symbols, and the description thereof is omitted.

Based on the above embodiments, the semiconductor structure20includes the protection structures102, each of the protection structures102has the square top-view pattern TP, and the square top-view patterns TP located in the same corner region R11have various sizes. Therefore, the crack can be prevented from extending into the device region R12of the die region R1by the protection structures102located in the corner region R11, thereby preventing the circuit in the device region R12from being damaged. In addition, the protection structures102located in the corner region R11have the effect of relieving stress.

In summary, in the semiconductor structure of the aforementioned embodiments, each of the protection structures has the square top-view pattern, and the square top-view patterns located in the same corner region have various sizes. Therefore, the crack can be prevented from extending into the device region of the die region by the protection structures located in the corner region, thereby preventing the circuit in the device region from being damaged. In addition, the protection structures located in the corner region have the effect of relieving stress.