Pulse quadrature modulator and method

A pulse quadrature modulator generates both alpha and beta binary signals, each one serial bit switched at an RF carrier frequency at a fraction of a high speed quantization clock. The alpha and beta binary signals each have respective alpha and beta pulse edges nominally occurring at two times the RF carrier frequency. The alpha and beta pulse edges alternate respectively. The alpha and beta pulse edges are each synchronized to the high speed quantization clock switched based on the baseband I and Q signal inputs. First and second switches gate a power signal using a respective of the alpha or beta binary signals to respectively produce first and second power outputs. The first and second switches differentially drive an RF load such as an antenna across the first and second power outputs having pulse edges at nominally at an integer multiple of four times the RF carrier frequency.

BACKGROUND OF THE INVENTIONS

1. Technical Field

The present inventions relate to a quadrature modulated bridge switching power stage that produces a modulated RF signal and, more particularly, relate to a pulse modulated bridge power stage for creating a quadrature modulated RF signal for RF transmission.

2. Description of the Related Art

Quadrature modulation is a method of transmitting a complex baseband signal using a single RF (radio frequency) frequency and an RF power amplifier. The power conversion efficiency of the RF power amplifier is a function of the RF signal envelope peak to average ratio. The power conversion efficiency can be as low as 10% for large peak to average ratio (10 dB). Even for an FM signal which is constant envelope with a peak to average ratio of 0 dB the power conversion efficiency is only about 50%. The remaining power is lost as heat and results in higher power consumption as well as cost and size of a system to eliminate the heat. There is also significant cost and complexity of the mostly analog circuitry to produce the modulated RF power signal.

SUMMARY OF THE INVENTION

Power consumption, directly or indirectly, contributes to a large portion of the cost of RF transmission. Even when the cost of the power consumed is low there is significant cost associated with elimination of the heat from a linear RF amplifier. It is therefore desirable to eliminate the linear RF amplifier and replace it with a switching RF stage. Further, the speed of digital circuits continues to go up and their cost continues to go down. Replacement of the RF mixer, the baseband DACs and the linear RF amplifier reduces cost of the solution while improving power conversion efficiency.

The inventions relate to methods and apparatus to convert a digital baseband signals to a pair of binary signals which switch at the RF carrier frequency. This conversion can be entirely in the digital domain.

To optimize the output power and power conversion it is desirable to switch at the carrier frequency. With a pair of switching signals there are four edges per RF carrier frequency cycle. The edges are created by counting a high speed quantization clock. This allows a relatively low resolution in the choice of the edges. However, using noise shaping techniques it is possible to get higher resolution.

The baseband I and Q signal inputs are input into the system in digital format. The bandwidth of these signals is relatively low. There are a large number of cycles of noise shaping available to create a modulated RF signal with high resolution.

The pair of digital switching signals are output to a switching RF stage which creates the amplified modulated signal with high power, high efficiency and high fidelity. The expensive and power hungry analog circuitry is largely eliminated.

Preferred embodiments for the switching RF power stage modulator have a pair of binary signals alpha binary signal of one serial bit and the beta binary signal of one serial bit. However, additional binary signals are possible with a total of four binary signals. In other embodiments, binary signals with higher multiples of two are possible

Linearity and power conversion of a switching RF power stage are superior to that of a conventional RF lineup to create a modulated RF signal. As semiconductor processes improve the speed of digital circuits and switching circuits more RF systems can be implemented using this invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1illustrates a block diagram of the system of a switching RF power stage modulator driving dipole antenna100. A pulse quadrature modulator102takes inputs digital baseband I101and Q103and a high speed quantization clock109and generates two outputs alpha105and beta107. Alpha105and beta107are binary signal of one serial bit switched at the RF carrier frequency for driving the pair of switches. Note that the alpha signal and the beta signal switch at different times. There is an up transition and a down transition for both signals in a period of the RF carrier frequency. Thus there is a single transition at four times the RF carrier frequency. In other words there is an alpha pulse edge nominally occurring at a rate two times the RF carrier frequency and a beta pulse edge nominally occurring at a rate two times the RF carrier frequency. The RF carrier frequency period is divided into four equal quarters and alpha or beta transitions every quarter of the period of the RF carrier frequency. In embodiments the RF carrier frequency can be a predetermined RF carrier frequency value. The alpha pulse edge and the beta pulse edge are switched based on the baseband I and Q signal inputs. The alpha pulse edge and the beta pulse edge are synchronized to the high speed quantization clock.

Inside RF Switching power stage104, two switches are both connected to ground and connected with passive components106to power supply voltage V+111. The first switch produces a first power output and the second switch produces a second power output. The power is obtained from a power source the power supply voltage V+ with high power conversion efficiency. Dipole antenna115is connected to the two switches. The differential RF signal output113is the signal waveform driving the dipole antenna115. The signal transmitted by the dipole antenna is a modulated sine wave at the RF carrier frequency.

FIG. 2illustrates a block diagram of the system of a switching RF power stage modulator driving monopole antenna200. A pulse quadrature modulator102takes input digital baseband I101and Q103and a high speed quantization clock109and generates two outputs alpha105and beta107. Alpha105and beta107are binary signal of one serial bit switched at the RF carrier frequency for driving the two switches. Note that the alpha signal and the beta signal switch at different times. There is an up transition and a down transition for both signals in a period of the RF carrier frequency. Thus there is a single transition at four times the RF carrier frequency. In other words there is an alpha pulse edge nominally occurring at a rate two times the RF carrier frequency and a beta pulse edge nominally occurring at a rate two times the RF carrier frequency. The RF carrier frequency period is divided into four equal quarters and alpha or beta transitions every quarter of the period of the RF carrier frequency.

Inside RF Switching power stage104, two switches are both connected to ground and connected with passive components106to power supply voltage V+111. The first switch produces a first power output and the second switch produces a second power output. The power is obtained from a power source the power supply voltage V+ with high power conversion efficiency. The differential voltage output113is the differential RF signal output driving the Balun and BPF (band pass filter)202. The output of the Balun and BPF202are connected to the monopole antenna203and ground. Modulated RF output201is a modulated sine wave signal at the monopole antenna203. The alpha pulse edge and the beta pulse edge are switched based on the baseband I and Q signal inputs. The alpha pulse edge and the beta pulse edge are synchronized to the high speed quantization clock.

FIG. 3illustrates a detailed block diagram of the system of a Pulse Quadrature Modulator300with phase and amplitude detector302, quadrant selector304, edge quantizer306and pulse counter308. The phase and amplitude detector302has two digital baseband inputs I101and Q103generate two outputs in the form of ϕ phase301and amplitude303. Note that the RF carrier frequency period is divided into four equal quarters and alpha or beta transitions every quarter. So it is advantageous to input digital baseband inputs I101and Q103at this rate. Typically the digital baseband inputs I101and Q103are not available at this high rate but they can be upsampled to this rate using conventional upsampling techniques.

The ϕ phase301is an input for quadrant selector304and amplitude303is an input for edge quantizer306. The two outputs of quadrant selector304are inputs for edge quantizer306. They are fractional phase307and quadrant305. The signal quadrant305is also connected as an input for pulse counter308. Edge quantizer306takes three inputs quadrant305, fractional phase307, and amplitude303and generates two outputs quantized delay309and quantized duty ratio311. These two outputs are connected with pulse counter308. Pulse counter308has four inputs quadrant305, quantized delay309, quantized duty ratio311and high speed quantization clock109, and generates two outputs alpha105and beta107. RF Switching power stage104takes inputs alpha105and beta107and generates output differential voltage output113which is going to RF load310.

Other embodiments may have four or greater even number of outputs instead of two outputs alpha105and beta107. Larger number of outputs would require larger number of switches. However, with larger number of outputs higher performance would be achieved without reducing the power conversion efficiency of the system.

Note that the quadrant signal has four possible values namely 1, 2, 3 and 4. This corresponds to the four quadrants of the digital baseband inputs I101and Q103. For example, if I and Q are both positive the quadrant is 1, if I is negative and Q is positive the quadrant is 2, if I is negative and Q is negative the quadrant is 3 and if I is positive and Q is negative the quadrant is 4.

Also note that the quarter signal has four possible values namely 1, 2, 3 and 4. It is 1 for the first ¼ of a period of the RF carrier frequency. It is 2 for the second ¼ of the period of the RF carrier frequency. It is 3 for the third ¼ of the period of the RF carrier frequency. It is 4 for the last ¼ of the period of the RF carrier frequency.

FIG. 4illustrates a schematic diagram of the system for quadrant selector304. The ceiling function402takes input from multiplier401and generate output quadrant305. Multiplier401takes input in the form of phase301and 2/pi and produces output Phase times 2/pi. The phase is a number between 0 and 2pi. By this multiplication and the ceiling function an integer between one and four is obtained which corresponds to the four quadrants of the digital baseband signal pair (I, Q). These operations determine which of the four quadrant of the digital baseband inputs I101and Q103lie in when plotted as (I,Q) on a conventional coordinate plane.

The Phase signal is also connected in positive mode with Summation Σ407. Summation Σ407have two signed inputs with the output of the multiplier403is subtracted from the Phase301to generate the output fractional phase307. The fractional phase is the relative phase within a quadrant of the digital baseband signal pair (I, Q). Multiplier403takes two inputs pi/2 and quadrant305and produces an integer multiple of pi/2.

FIG. 5illustrates a block diagram of the system for edge quantizer306. Quantizer502takes two input from fractional phase307and quadrant305and generate output quantized delay309. Nonlinear mapping504takes input as form of amplitude303and generate output unquantized duty ratio501which will input for quantizer506. Amplitude is maximum at duty ratio of half. Amplitude is zero at duty ratio of half. However, at intermediate points there is a nonlinear sinusoidal relationship. Quantizer506takes two input from unquantized duty ratio501and quadrant305and generate output quantized duty ratio311. Quantization is to reduce the bit width of the signals so that binary signal of one serial bit switched at the RF carrier frequency alpha105and beta107can be created by counting the high speed quantization clock109. Quantization causes noise which may not be desirable in the frequencies around the RF carrier frequency. Using noise shaping techniques the quantization noise can be shaped out of the frequency band around the RF carrier frequency. Frequencies away from the RF carrier frequency can be suppressed using the BPF. The antenna and the balun also have an inherent band pass characteristic.

FIG. 6illustrates a block diagram of the system for pulse counter308. Pulse state machine602takes four input from quantized delay309, quantized duty ratio311, quadrant305and quarter601. An n/4 counter604has input high speed quantization clock109and output the signal quarter601. The quarter goes 1 through 4 and is input for Pulse state machine602. The Pulse state machine602and generates two outputs NA603and NB605which will inputs for up down counter606and up down counter608. Up down counter606takes input in the form of NA603from pulse state machine602and high speed quantization clock109and generates output alpha105. Up down counter608takes input in the form of NB605from pulse state machine602and high speed quantization clock109and generates output beta107.

FIG. 7illustrates a schematic diagram of the system of RF switching Power stage with transformer104, switch SWA701is a low side switch connected to the transformer primary winding705and to ground. Voltage V+111is connected to transformer primary winding705and transformer primary winding707. Switch SWB703is a low side switch connected to the transformer primary winding707and to ground. Signal alpha105controls SWA701and signal beta107controls switch SWB703. RF load310is parallel connected to transformer secondary709. The transformer provides, isolation and impedance transformation. The transformer may also provide a bandpass action allowing only frequencies close to the RF carrier frequency to pass.

FIG. 8illustrates a schematic diagram of the system of RF switching transformerless Power stage104, RF load310is connected between the four switches SWAH801, SWAL803, SWBH805, and SWBL807which are connected in an H-bridge. Alpha105controls switch SWAH801, beta107controls switch SWBH805. Alpha bar809controls switch SWAL803, beta bar811controls switch SWBL807. Voltage V+111is connected to the high side of the switches SWAH801and SWBH805. Ground is connected to the low side of the switches SWAL803and SWBL807.

FIG. 9illustrates a timing diagram over time of signal waveforms for power stage with transformer for (I, Q) in first quadrant900. The digital baseband signals (I, Q) sampled at four times the switching frequency is mapped to four edges of the pair of alpha and beta signals. As the duty ratio and fractional phase vary the precise location of the alpha and beta edges vary but the states at the four quarters are known for the entire range of duty ratios and fractional phase values. In each quarter of the alpha and beta cycle there is exactly one edge of one the two alpha and beta signals. The signals are shown for a complete period of the RF carrier frequency and divided into four quarters. Note that the quarter signal has value 1 in the first ¼ period of the RF carrier frequency, it has value 2 in the second ¼ period of the RF carrier frequency, it has value 3 in the third ¼ period of the RF carrier frequency and it has value 4 in the last ¼ period of the RF carrier frequency.

The top waveform is the Modulated RF Output201. The next lower waveform is the Differential Voltage Output113. This signal has three possible values, V+, 0 and −V+. The next waveform is the alpha signal105. This is a binary signal with 0 and 1 as possible values. The next waveform is the beta signal107. This is also a binary signal with 0 and 1 as possible values. The bottom waveform is the Quantization Clock109. It is a high frequency clock and all edges of alpha and beta are synchronized to an edge of this clock signal.FIG. 9corresponds to the digital baseband signals (I, Q) being in the first quadrant. These waveforms are for a power stage with a transformer.

FIG. 10illustrates a Timing diagram over time of signal waveforms for power stage with transformer for (I, Q) in second quadrant1000. The digital baseband signals (I, Q) sampled at four times the switching frequency is mapped to four edges of the pair of alpha and beta signals. As the duty ratio and fractional phase vary the precise location of the alpha and beta edges vary but the states at the four quarters are known for the entire range of duty ratios and fractional phase values. In each quarter of the alpha and beta cycle there is exactly one edge of one the two alpha and beta signals. The signals are shown for a complete period of the RF carrier frequency and divided into four quarters. Note that the quarter signal has value 1 in the first ¼ period of the RF carrier frequency, it has value 2 in the second ¼ period of the RF carrier frequency, it has value 3 in the third ¼ period of the RF carrier frequency and it has value 4 in the last ¼ period of the RF carrier frequency.

The top waveform is the Modulated RF Output201. The next lower waveform is the Differential Voltage Output113. This signal has three possible values, V+, 0 and −V+. The next waveform is the alpha signal105. This is a binary signal with 0 and 1 as possible values. The next waveform is the beta signal107. This is also a binary signal with 0 and 1 as possible values. The bottom waveform is the Quantization Clock109. It is a high frequency clock and all edges of alpha and beta are synchronized to an edge of this clock signal.FIG. 9corresponds to the digital baseband signals (I, Q) being in the second quadrant. These waveform are for a power stage with a transformer.

FIG. 11illustrates a Timing diagram over time of signal waveforms for power stage with transformer for (I, Q) in third quadrant1100. The digital baseband signals (I, Q) sampled at four times the switching frequency is mapped to four edges of the pair of alpha and beta signals. As the duty ratio and fractional phase vary the precise location of the alpha and beta edges vary but the states at the four quarters are known for the entire range of duty ratios and fractional phase values. In each quarter of the alpha and beta cycle there is exactly one edge of one the two alpha and beta signals. The signals are shown for a complete period of the RF carrier frequency and divided into four quarters. Note that the quarter signal has value 1 in the first ¼ period of the RF carrier frequency, it has value 2 in the second ¼ period of the RF carrier frequency, it has value 3 in the third ¼ period of the RF carrier frequency and it has value 4 in the last ¼ period of the RF carrier frequency.

The top waveform is the Modulated RF Output201. The next lower waveform is the Differential Voltage Output113. This signal has three possible values, V+, 0 and −V+. The next waveform is the alpha signal105. This is a binary signal with 0 and 1 as possible values. The next waveform is the beta signal107. This is also a binary signal with 0 and 1 as possible values. The bottom waveform is the Quantization Clock109. It is a high frequency clock and all edges of alpha and beta are synchronized to an edge of this clock signal.FIG. 9corresponds to the digital baseband signals (I, Q) being in the third quadrant. These waveform are for a power stage with a transformer.

FIG. 12illustrates a Timing diagram over time of signal waveforms for power stage with transformer for (I, Q) in fourth quadrant1200. The digital baseband signals (I, Q) sampled at four times the switching frequency is mapped to four edges of the pair of alpha and beta signals. As the duty ratio and fractional phase vary the precise location of the alpha and beta edges vary but the states at the four quarters are known for the entire range of duty ratios and fractional phase values. In each quarter of the alpha and beta cycle there is exactly one edge of one the two alpha and beta signals. The signals are shown for a complete period of the RF carrier frequency and divided into four quarters. Note that the quarter signal has value 1 in the first ¼ period of the RF carrier frequency, it has value 2 in the second ¼ period of the RF carrier frequency, it has value 3 in the third ¼ period of the RF carrier frequency and it has value 4 in the last ¼ period of the RF carrier frequency.

The top waveform is the Modulated RF Output201. The next lower waveform is the Differential Voltage Output113. This signal has three possible values, V+, 0 and −V+. The next waveform is the alpha signal105. This is a binary signal with 0 and 1 as possible values. The next waveform is the beta signal107. This is also a binary signal with 0 and 1 as possible values. The bottom waveform is the Quantization Clock109. It is a high frequency clock and all edges of alpha and beta are synchronized to an edge of this clock signal.FIG. 9corresponds to the digital baseband signals (I, Q) being in the fourth quadrant. These waveforms are for a power stage with a transformer.

FIG. 13illustrates a Timing diagram over time of signal waveforms for power stage without transformer for (I, Q) in first quadrant1300. The digital baseband signals I, Q sampled at four times the switching frequency is mapped to four edges of the pair of alpha and beta signals. As the duty ratio and fractional phase vary the precise location of the alpha and beta edges vary but the states at the four quarters are known for the entire range of duty ratios and fractional phase values. In each quarter of the alpha and beta cycle there is exactly one edge of one the two alpha and beta signals. The signals are shown for a complete period of the RF carrier frequency and divided into four quarters. Note that the quarter signal has value 1 in the first ¼ period of the RF carrier frequency, it has value 2 in the second ¼ period of the RF carrier frequency, it has value 3 in the third ¼ period of the RF carrier frequency and it has value 4 in the last ¼ period of the RF carrier frequency.

The top waveform is the Modulated RF Output201. The next lower waveform is the Differential Voltage Output113. This signal has three possible values, V+, 0 and −V+. The next waveform is the alpha signal105. This is a binary signal with 0 and 1 as possible values. The next waveform is the beta signal107. This is also a binary signal with 0 and 1 as possible values. The bottom waveform is the Quantization Clock109. It is a high frequency clock and all edges of alpha and beta are synchronized to an edge of this clock signal.FIG. 13corresponds to the digital baseband signals (I, Q) being in the first quadrant. These waveforms are for a power stage without transformer.

FIG. 14illustrates a Timing diagram over time of signal waveforms for power stage without transformer for (I, Q) in second quadrant1400. The digital baseband signals (I, Q) sampled at four times the switching frequency is mapped to four edges of the pair of alpha and beta signals. As the duty ratio and fractional phase vary the precise location of the alpha and beta edges vary but the states at the four quarters are known for the entire range of duty ratios and fractional phase values. In each quarter of the alpha and beta cycle there is exactly one edge of one the two alpha and beta signals. The signals are shown for a complete period of the RF carrier frequency and divided into four quarters. Note that the quarter signal has value 1 in the first ¼ period of the RF carrier frequency, it has value 2 in the second ¼ period of the RF carrier frequency, it has value 3 in the third ¼ period of the RF carrier frequency and it has value 4 in the last ¼ period of the RF carrier frequency.

The top waveform is the Modulated RF Output201. The next lower waveform is the Differential Voltage Output113. This signal has three possible values, V+, 0 and −V+. The next waveform is the alpha signal105. This is a binary signal with 0 and 1 as possible values. The next waveform is the beta signal107. This is also a binary signal with 0 and 1 as possible values. The bottom waveform is the Quantization Clock109. It is a high frequency clock and all edges of alpha and beta are synchronized to an edge of this clock signal.FIG. 13corresponds to the digital baseband signals (I, Q) being in the second quadrant. These waveforms are for a power stage without transformer.

FIG. 15illustrates a Timing diagram over time of signal waveforms for power stage without transformer for (I, Q) in third quadrant1500. The digital baseband signals (I, Q) sampled at four times the switching frequency is mapped to four edges of the pair of alpha and beta signals. As the duty ratio and fractional phase vary the precise location of the alpha and beta edges vary but the states at the four quarters are known for the entire range of duty ratios and fractional phase values. In each quarter of the alpha and beta cycle there is exactly one edge of one the two alpha and beta signals. The signals are shown for a complete period of the RF carrier frequency and divided into four quarters. Note that the quarter signal has value 1 in the first ¼ period of the RF carrier frequency, it has value 2 in the second ¼ period of the RF carrier frequency, it has value 3 in the third ¼ period of the RF carrier frequency and it has value 4 in the last ¼ period of the RF carrier frequency.

The top waveform is the Modulated RF Output201. The next lower waveform is the Differential Voltage Output113. This signal has three possible values, V+, 0 and −V+. The next waveform is the alpha signal105. This is a binary signal with 0 and 1 as possible values. The next waveform is the beta signal107. This is also a binary signal with 0 and 1 as possible values. The bottom waveform is the Quantization Clock109. It is a high frequency clock and all edges of alpha and beta are synchronized to an edge of this clock signal.FIG. 15corresponds to the digital baseband signals (I, Q) being in the third quadrant. These waveforms are for a power stage without transformer.

FIG. 16illustrates a Timing diagram over time of signal waveforms for power stage without transformer for (I, Q) in fourth quadrant1600. The digital baseband signals (I, Q) sampled at four times the switching frequency is mapped to four edges of the pair of alpha and beta signals. As the duty ratio and fractional phase vary the precise location of the alpha and beta edges vary but the states at the four quarters are known for the entire range of duty ratios and fractional phase values. In each quarter of the alpha and beta cycle there is exactly one edge of one the two alpha and beta signals. The signals are shown for a complete period of the RF carrier frequency and divided into four quarters. Note that the quarter signal has value 1 in the first ¼ period of the RF carrier frequency, it has value 2 in the second ¼ period of the RF carrier frequency, it has value 3 in the third ¼ period of the RF carrier frequency and it has value 4 in the last ¼ period of the RF carrier frequency.

The top waveform is the Modulated RF Output201. The next lower waveform is the Differential Voltage Output113. This signal has three possible values, V+, 0 and −V+. The next waveform is the alpha signal105. This is a binary signal with 0 and 1 as possible values. The next waveform is the beta signal107. This is also a binary signal with 0 and 1 as possible values. The bottom waveform is the Quantization Clock109. It is a high frequency clock and all edges of alpha and beta are synchronized to an edge of this clock signal.FIG. 16corresponds to the digital baseband signals (I, Q) being in the fourth quadrant. These waveform are for a power stage without transformer.

FIG. 17illustrates a State Space diagram for power stage with transformer1700. There are three possible states: S11701and1702, S21703and S31704. State S1numbered1701and1702corresponds to alpha and beta both equal to zero. State S21703which corresponds to alpha equal to zero and beta equal to one. State S31704corresponds to alpha equal to one and beta equal to zero. Note that the state S1comes twice in the state diagram because the state of alpha and beta both equal to one would cause a short circuit. The conditions for the transition between states are given in the four mini tables shown on the figure. The objective of the State Space diagram is to illustrate the control action for the signals alpha and beta in accordance with the invention. In a period of the RF carrier frequency the system goes clockwise one rotation. Depending on the quadrant of the baseband signals I and Q the starting and ending point are different. Table 1 given below provides a truth table of the control action.

TABLE 1Truth Table for system with transformerStarting StateEnding StateαβQuadrantQuarterαβ001110002410003310004210101200102100103400104300001301002201003101004401011400012300013200014100

FIG. 18illustrates a State Space diagram for a transformerless power stage1800. There are four possible states: S11801, S21802, S31803and S41804. State S1numbered1801corresponds to alpha and beta both equal to zero. State S21802which corresponds to alpha equal to zero and beta equal to one. State S31803corresponds to alpha equal to one and beta equal to zero. State S41804corresponds to both alpha and beta equal to one. The conditions for the transition between states are given in the four mini tables shown on the figure. The objective of the state space diagram is to illustrate the control action for the signals alpha and beta in accordance with the invention. In a period of the RF carrier frequency the system goes clockwise one rotation. Depending on the quadrant of the baseband signals I and Q the starting and ending point are different. Table 2 given below provides a truth table of the control action.

TABLE 2Truth Table for system without transformerStarting StateEnding StateαβQuadrantQuarterαβ001110002410003310004210101211102111103411104311111301112201113101114401011400012300013200014100

The signal processing techniques disclosed herein with reference to the accompanying drawings can be implemented on one or more digital signal processors (DSPs) or other microprocessors. Nevertheless, such techniques could instead be implemented wholly or partially as hardwired circuits. Further, it is appreciated by those of skill in the art that certain well known digital processing techniques are mathematically equivalent to one another and can be represented in different ways depending on choice of implementation.

Any letter designations such as (a) or (b) etc. used to label steps of any of the method claims herein are step headers applied for reading convenience and are not to be used in interpreting an order or process sequence of claimed method steps. Any method claims that recite a particular order or process sequence will do so using the words of their text, not the letter designations.

Any trademarks listed herein are the property of their respective owners, and reference herein to such trademarks is generally intended to indicate the source of a particular product or service.

Although the inventions have been described and illustrated in the above description and drawings, it is understood that this description is by example only, and that numerous changes and modifications can be made by those skilled in the art without departing from the true spirit and scope of the inventions. Although the examples in the drawings depict only example constructions and embodiments, alternate embodiments are available given the teachings of the present patent disclosure.