Semiconductor structure and method of manufacture

In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, an electrical bus embedded in a dielectric material below a surface of a semiconductor substrate is disclosed. Other embodiments are described and claimed.

TECHNICAL FIELD

Embodiments disclosed in the present disclosure relate generally to electrical and semiconductor technology, and more specifically to a semiconductor structure that includes a dielectric structure.

BACKGROUND

For some applications, such as digital, analog, radio-frequency (RF) or mixed signal circuits, networks of electrically conductive interconnects or busses may be formed to provide distribution of signals or power for common use within the die. In one example the electrically conductive interconnects provide distribution of power to the circuits or transistors across the die. However, these interconnects may have relatively high resistance because of their relatively small cross-sectional area. High resistance interconnects leads to power loss in the interconnect themselves, which produces undesired heat and reduces the overall efficiency. Furthermore, resistive losses result in a reduction in the interconnect voltage with increasing distance from the voltage source. Circuit or transistor operation may thus be compromised because of a variation in power supply voltage across the die.

Further, electrically conductive interconnects may be used to provide distribution of circuit signals that are commonly used across the die. In one example such interconnects may provide distribution of the clock signal. In addition to the issues discussed above relating to high resistance, when formed on or in relatively close proximity to a conductive substrate or other conductive elements, parasitic capacitive coupling may cause a reduction in the frequency of operation or a variation in the frequency of operation across the die, again degrading performance. Such parasitic capacitive coupling may also occur between interconnects or between interconnects and devices.

Further, regions of a semiconductor substrate may be physically and electrically isolated from each other. For example mixed signal circuits may include both analog and digital circuit components as well as optional power components. Each of these sub-components may require isolated distribution of their own signals and power over independent interconnects. When such signal and/or power lines come within close proximity to each other or other conductive components, or cross each other, interaction may occur between them resulting in reduced frequency of operation and/or compromised circuit performance, for example by cross-talk, where a signal from one interconnect is coupled into the signal from another interconnect.

For simplicity of illustration and ease of understanding, elements in the various figures are not necessarily drawn to scale, unless explicitly so stated. Further, if considered appropriate, reference numerals have been repeated among the figures to indicate corresponding and/or analogous elements. In some instances, well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present disclosure. The following detailed description is merely exemplary in nature and is not intended to limit the disclosure of this document and uses of the disclosed embodiments. Furthermore, there is no intention that the appended claims be limited by the title, technical field, background, or abstract.

DETAILED DESCRIPTION

In the following description and claims, the terms “comprise” and “include,” along with their derivatives, may be used and are intended as synonyms for each other. In addition, in the following description and claims, the terms “coupled” and “connected,” along with their derivatives, may be used. “Connected” may be used to indicate that two or more elements are in direct physical or electrical contact with each other. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. For example, “coupled” may mean that two or more elements do not contact each other but are indirectly joined together via another element or intermediate elements. Finally, the terms “on,” “overlying,” and “over” may be used in the following description and claims. “On,” “overlying,” and “over” may be used to indicate that two or more elements are in direct physical contact with each other. However, “over” may also mean that two or more elements are not in direct contact with each other. For example, “over” may mean that one element is above another element but not contact each other and may have another element or elements in between the two elements.

FIG. 1shows a plan view of a semiconductor structure100comprising a dielectric structure104and active regions comprising an analog power supply region111, an analog circuit region112, a digital power supply region114, a digital circuit region116, an interconnect for analog power120, an interconnect for digital power122, an interconnect for ground124, a signal interconnect126and a passive element region118. Dielectric structure104may be referred to as a dielectric structure, a dielectric material, a dielectric platform or a dielectric region. Dielectric structure104may be formed at least partially below surface105(FIG. 2) of substrate110and thus may also be referred to as an embedded dielectric structure. Dielectric structure104may be comprised mainly of one or more relatively low dielectric constant materials, for example silicon dioxide. In addition, in some embodiments, dielectric structure104may include one or more voids or air gaps. Since empty space has the lowest dielectric constant (the dielectric constant of empty space is 1), the more empty space or void space incorporated into dielectric structure104, the lower the overall or effective dielectric constant of dielectric structure104.

Ground interconnect124may comprise a main interconnect124and two branches130and132. Branches130and132may also be referred to as taps or local tap. As will be discussed later, branches130and132may couple the main interconnect124to an active region or a passive region, here for example branch130couples to the analog circuit region112and branch132couples to the digital circuit region116.

Active regions111,112,114,116may be comprised of a portion of substrate110. In some embodiments, substrate110may be referred to as a device layer or an active layer. Further, in some embodiments, substrate110may include one or more epitaxial layers or bonded layers. A portion of substrate110may be used as an active area where active devices, such as, for example, transistors or diodes, or portions of active devices, may be subsequently formed. Active devices may be formed in active regions111,112,114,116using conventional MOS (metal oxide semiconductor), complementary metal oxide semiconductor (CMOS), bipolar, or bipolar-CMOS (BiCMOS) processes. The active regions may also be referred to as circuit sections, subsections, sub-circuits, active areas or active area regions or portions of active areas.

Passive devices may be formed in passive region118over dielectric structure104using conventional semiconductor processing. Examples of passive devices may include capacitors, inductors, and resistors or interconnects.

Substrate110may comprise a semiconductor material such as, for example, silicon, and may be doped or undoped depending on the application.

FIG. 2shows a cross-sectional view of semiconductor structure100ofFIG. 1taken along section line2-2ofFIG. 1.FIG. 2illustrates dielectric structure104, ground interconnect124, digital power supply interconnect122and digital power circuit region114. As will be discussed further below, at least a portion of dielectric structure104may be between electrically conductive material122and substrate110. At least a portion of dielectric structure104may be between electrically conductive material124and substrate110. In other embodiments, at least a portion of dielectric structure104may be between at least a portion of electrically conductive material122and124and at least a portion of substrate110.

The semiconductor structure disclosed herein and shown in one example inFIGS. 1 and 2, provides for reduced interconnect resistance, increased frequency of operation and reduced coupling or cross-talk between active and passive devices and/or regions and other conductive elements for example interconnects and a conductive substrate.

The interconnect resistance may be determined by the relationship R (resistance)=ρL/A where ρ is the resistivity of the material, L is the length of the interconnect and A is the cross-sectional area of the interconnect. It is clear that for a given material and interconnect length; increasing the cross-sectional area will result in a corresponding reduction in interconnect resistance. However, in conventional circuits increasing the width of the interconnect to reduce its resistance is undesirable because this consumes more area on the die, reduces the component density and increases the cost of the chip. Increasing the thickness of the interconnect increases the surface topography, leading to increased difficulty of subsequent processing steps, lower yield and higher costs.

Conventional interconnects are formed on the surface or near surface region of the semiconductor substrate. Die size constraints limit the cross-sectional dimensions of typical interconnects to the range of about 0.5 microns×0.5 microns to about 1.0 microns×4.0 microns, with cross-sectional areas in the range of about 0.25 microns2to about 4.0 microns2.

Referring toFIG. 2, interconnects122and124utilize the vertical dimension below surface105of substrate110to form interconnects that may have a larger cross-sectional area than those used to date and thus may have a relatively lower resistance. Representative interconnects122and124may have a width in the range of about 0.5 microns to about 5 microns and a depth in the range of about 1.0 micron to about 30 microns. In one example interconnects122and124may have a width of about 3 microns and a depth of about 10 microns. In this example the cross-sectional area is about 30 microns2, which is a factor of about 30/4 or about 7.5× larger than that of conventional interconnects and thus has a resistance which is about 7.5× less than that of conventional interconnects. This may greatly reduce the power loss in this interconnect, resulting in less undesired heat generation and higher efficiency.

High frequency operation is limited by capacitive coupling between conductive substrate110and other conductive elements such as active elements, passive elements and interconnects. Furthermore capacitive coupling between active and or passive devices, or between interconnects, or between one or more of each of these elements causes cross-talk, where a portion of the signal in one element is coupled to a second element, degrades performance.

Increasing the thickness of a dielectric material between elements may reduce capacitive coupling and cross-talk. Passive elements and interconnects are typically formed on an interlayer dielectric (ILD) layer to separate the conductive interconnect from underlying conductive elements. The typical thickness of an ILD is in the range of about 0.7 microns to about 1.0 microns. The spacing between conventional elements, which controls the extent of cross-talk, is typically in the range of about 0.5 microns to about 1 micron. Increasing the spacing to reduce parasitic capacitive coupling and cross-talk results in an undesirable increase in the die size and greatly increased chip cost. Increasing the thickness of the ILD layer greatly increases the processing complexity, decreases the yield and leads to increased chip costs.

Again, referring toFIG. 2, interconnects122and124may be partially or completely embedded in dielectric structure104. Dielectric structure104underneath interconnects122and124may have a thickness in the range of about 0.5 microns to about 50 microns. Dielectric structure104adjacent to interconnects122and124may have a width in the range of about 1.0 micron to about 12 microns. In comparison to conventional interconnects, the spacing between other interconnects or between an interconnect and other conductive elements, for example other circuits or substrate110is greater by a factor in the range of about 3 to about 20. This greatly reduces the parasitic capacitive coupling to other conductive elements, resulting in higher frequency operation, improved isolation and reduced cross-talk.

Capacitive coupling between passive elements and the substrate or other conductive elements may also result in reduced performance. In one embodiment, passive elements formed in passive region118(FIG. 1) may be separated from the substrate by the thickness of dielectric structure104. For example, passive components such as, for example, inductors, capacitors, or electrical interconnects, may be formed over embedded dielectric structure104and may have reduced parasitic capacitive coupling between these passive components and substrate110since embedded dielectric structure104has a relatively low dielectric constant or permittivity and since the embedded dielectric structure104increases the distance between the passive components and conductive substrate110. In one example the thickness of dielectric structure104may be in the range of about 2.0 microns to about 30 microns

In one example, passive region118may comprise one or more electrically conductive materials forming passive components, for example, aluminum, copper, gold, nickel, permalloy, or doped polycrystalline silicon formed over dielectric structure104. In various examples, passive components may be an inductor, a capacitor, a resistor, or an electrical interconnect and may be coupled to one or more active devices formed in active regions111,112,114and/or116.

Further, dielectric structure104may be used to form relatively high quality passive devices such as, for example, capacitors and inductors having a relatively high quality factor (0) since dielectric structure104may be used to isolate and separate the passive devices from conductive substrate110. Active devices, such as transistors or diodes, may be formed in regions adjacent to, or abutting, the dielectric structure104, and these active devices may be coupled to and employ passive components such as spiral inductors, interconnects, microstrip transmission lines and the like that are formed on a planar upper surface of dielectric structure104. Separating the passive components from substrate110allows higher Q's to be realized for these passive components.

As will be discussed, the structures described inFIGS. 1 and 2may be fabricated before or after fabrication of the active devices. In other words, some embodiments are capable of withstanding relatively high temperature operations required in active device fabrication. In some embodiments, multiple levels of interconnects may be fabricated within dielectric structure104. In other embodiments, an air gap may be formed surrounding a portion of the electrically conductive interconnect, to further reduce parasitic capacitive coupling.

Referring back toFIG. 1,FIG. 1shows active areas111,112,114and116completely surrounded by dielectric structure104. In this case, dielectric structure104may also be used to provide electrical isolation in semiconductor structure100. For example, dielectric structure104may provide electrical isolation between active regions111,112,114and116. Although dielectric structure104inFIG. 1is shown as surrounding all active areas, this is not a limitation of the claimed subject matter. In other embodiments, one or more regions of dielectric structure104may surround none, or one or more of the active or passive area regions and/or one or more regions of dielectric structure104may be formed adjacent to or abutting a portion of one or more active or passive regions. Although rectangular shaped active, passive and power supply regions and a rectangular shaped dielectric structure104are illustrated inFIG. 1, this is not a limitation of the claimed subject matter. In other embodiments, dielectric structure104and active regions, passive regions and power supply regions may have any arbitrary shape. Furthermore the example shown inFIG. 1is not meant to be limiting in terms of the number and types of different regions and any number different regions may be used in other embodiments.

Referring toFIGS. 1 and 2, interconnects120,122,124,126,130and132are shown with rectangular cross-sections, however this is not a limitation of the claimed subject matter and interconnects120,122,124,126,130and132may have any arbitrary cross-sectional shape, for example, circular or square. Again referring toFIGS. 1 and 2, interconnects120,122,124,126,130and132are shown as straight lines, however this is not a limitation of the claimed subject matter and interconnects120,122,124,126,130and132may be formed in any arbitrary shape.

As stated above, dielectric structure104may be comprised mainly of one or more low dielectric constant materials, for example silicon dioxide. Silicon dioxide (SiO2) has a dielectric constant of about 3.9. Accordingly, a solid or filled dielectric structure that includes no voids, such as dielectric structure104, and includes silicon dioxide may have a dielectric constant of about 3.9. In some embodiments described herein, dielectric structure104may include voids occupying a portion of the total volume of dielectric structure104. This may result in an effective dielectric constant reduction in proportion to the ratio of void space to dielectric material.

FIG. 3shows a plan view of semiconductor structure200, in accordance with one or more embodiments.FIG. 4shows a cross-sectional view of semiconductor structure200ofFIG. 3taken along section line4-4ofFIG. 3. Turning first toFIG. 3, semiconductor structure200may comprise dielectric structure104, active regions20and21, conductive bus lines1212, contacts460and465, interconnects1350and substrate110. Conductive bus lines1212may be referred to as bus lines, buried bus lines, interconnects or buried interconnects. InFIG. 3, dielectric structure104and conductive bus lines1212are referenced with dashed lines, indicating that they are below the visible surface. As seen inFIGS. 3 and 4contacts460couple drain region112of FET101to interconnect1350and drain122of FET102to interconnect1350and contacts465couple interconnects1350to bus lines1212.

Referring now toFIG. 4, a field effect transistor (“FET”)101may be formed in active region20and a FET102may be formed in active region21. FET101may be a MOSFET and may include a source region111in a portion of substrate110, a drain region112in a portion of substrate110, a gate oxide114over a portion of substrate110, a gate116over gate oxide114, and a channel region118formed in a portion of substrate110under gate oxide114and between doped regions111and112. FET102may be a MOSFET and may include a source region120in a portion of substrate110, a drain region122in a portion of substrate110, a gate oxide124over a portion of substrate110, a gate126over gate oxide124, and a channel region128formed in a portion of substrate110under gate oxide124and between doped regions120and122. Although one FET is shown in each active region, this is not a limitation of the claimed subject matter and each active region may contain more than one transistor, diode or other active devices.

Although the width of interconnects1350are shown as all the same, this is not a limitation of the claimed subject matter. In other examples, interconnects1350may be of different widths and depths. Similarly although bus lines1212are shown as all having the same widths and depths, this is not a limitation of the claimed subject matter and bus lines1212may have different widths and depths.

Dielectric structure104inFIG. 3is shown as separating active regions20and21. In other embodiments dielectric structure104may partially or fully encircle one or more active regions.

Although only a single active device is shown as being formed in each active region20and21of substrate110, the methods and apparatuses described herein are not limited in this regard. In some embodiments, a plurality of active devices may be formed in active regions20and21of substrate110.

Substrate110may serve as part of a drain region of a vertical transistor (not shown) formed in active region21. In this example, a source contact or electrode (not shown) may be formed on or adjacent to an upper surface of substrate110and a drain electrode (not shown) may be formed on or adjacent to a lower surface of substrate110. During operation, the electrical current flow from the source electrode to the drain electrode in the vertical transistor may be substantially perpendicular to the upper and lower surfaces of semiconductor substrate110. In other words, current flows essentially vertically through the vertical transistor from the electrode located adjacent a top surface of semiconductor structure200to a drain electrode located adjacent to the opposite bottom surface of semiconductor structure200. An example of a vertical transistor is described in U.S. patent application Ser. No. 10/557,135, entitled “POWER SEMICONDUCTOR DEVICE AND METHOD THEREFOR,” filed Nov. 17, 2005, which claims priority to Patent Cooperation Treaty (PCT) International Application Number PCT/US2005/000205 entitled “POWER SEMICONDUCTOR DEVICE AND METHOD THEREFOR,” having an International Filing Date of Jan. 6, 2005 and an International Publication Date of Jul. 28, 2005, the contents of both of these patent applications are incorporated herein by reference in their entirety.

FIGS. 5 to 13illustrate at least one embodiment for making semiconductor structure200ofFIGS. 3 and 4. In this example the interconnect structure is fabricated prior to fabrication of active devices. Turning toFIG. 5,FIG. 5shows a cross-sectional view of semiconductor structure200ofFIG. 4at an early stage of fabrication. At the stage illustrated inFIG. 5, dielectric layer510is formed over substrate110and dielectric layer512is formed over dielectric layer510. In one example dielectric layer510may be silicon dioxide and dielectric layer512may be silicon nitride. Dielectric layer510may comprise, for example, silicon dioxide and have a thickness ranging from about 50 Angstroms (Å) to about 5,000 Å. Dielectric layer510may be formed using deposition techniques or thermal growth techniques such as, for example, thermal oxidation of silicon. Dielectric layer512may comprise, for example, silicon nitride (Si3N4) and have a thickness ranging from about 100 Å to about 2,000 Å. Dielectric layer512may be formed using deposition techniques, for example, low pressure chemical vapor deposition (LPVCD) of silicon nitride.

In an alternate embodiment, only dielectric material510may be formed (not shown). Dielectric layer510may comprise, for example, silicon dioxide and have a thickness ranging from about 1000 Å to about 20,000 Å.

After dielectric layer512is formed, dielectric layer512and dielectric layer510may be patterned using photolithography and etching processes to form openings514and516and masked or covered areas520,521,522and523. Masked areas520,521,522, and523include portions of layers510and512. Masked area520is between two openings514, masked area521is between one opening514and one opening516, masked area522is between two openings516and masked area523defines the periphery of what will become dielectric structure104(FIG. 4). Masked areas520,521,522, and523together form a mask structure513and openings514and516expose portions of substrate110. Photolithography processes or operations involve the use of masks and may sometimes be referred to as masking operations or acts. The photolithography and etching may include forming a layer of a radiation-sensitive material, such as, for example, photoresist (not shown), over dielectric layer512, then exposing the photoresist using, for example, ultraviolet (UV) radiation and developing the resist to form a mask, and then etching portions of dielectric layers512and510to form openings514and516.

Openings514and516may be formed using at least one etching operation. In some embodiments, two or more etching operations may be used to form openings514and516. In some embodiments, silicon nitride layer512may be etched using a wet chemical etch or a dry etch process such as, for example, a reactive ion etch (RIE). Silicon dioxide layer510may be etched using a wet chemical etch or a dry etch process such as, for example, a reactive ion etch (RIE).

The width or diameter of openings514and516and masked areas510,521and522determine the width and separation of interconnects1212(FIG. 4). In one example, openings514and masked areas520,521and522each have a width or diameter equal to about ⅓ of the desired separation between interconnects1212(FIG. 4) and the width or diameter of openings516have a width equal to about the sum of the desired width of interconnect1212and two times the width or diameter of opening514. Although the width or diameter of interconnects1212inFIG. 4may be all the same, this is not a limitation of the claimed subject matter. In other embodiments, semiconductor structure may contain interconnects with different widths or diameters.

In one example openings514and masked areas520,521and522may each be in the range of about 1.0 microns to about 3 microns and openings516may be in the range of about 3.0 microns to about 10 microns. Although the spacing between any two openings (either514and/or516) shown inFIG. 5may be substantially the same, this is not a limitation of the claimed subject matter. The spacing between openings514and the size of openings514do not have to be the same, or substantially the same. Further, although openings514and516may be shown as rectangular, this is not a limitation of the claimed subject matter. Openings514and516may have any shape and may be formed in a periodic or non-periodic arrangement. The width of mask area523is dependent on the circuit layout. In one example the width of masked area523may be in the range of about 3.0 microns to about 1000 microns. In another example the width of masked area523may be in the range of about 5.0 microns to about 10 microns.

Dielectric layer512or a combination of dielectric layer510and dielectric layer512may serve as a hard mask, and may be referred to as a masking layer. Since the photoresist (not shown) over dielectric512may optionally be left in place during the next etch step, it may also be etched as part of the etch step used to etch portions of dielectric layer512, portions of dielectric layer510and portions of substrate110. Dielectric layer512or a combination of dielectric layer510and dielectric layer512may be used as a hard mask to prevent the undesired etching of the upper surface of substrate110during the formation of openings514and516and subsequent removal of a portion of substrate110exposed by openings514and516. In alternate embodiments, the photoresist layer may be made relatively thick such that it is not completely eroded during the etching process. Accordingly the thickness of dielectric material510or the combination of dielectric materials510and512must be large enough so that it is not completely removed during the next etching step.

Turning now toFIG. 6,FIG. 6shows semiconductor structure200ofFIG. 5at a later stage of manufacture. After formation of openings514and516(FIG. 5), cavities614and616may be formed in substrate110using mask513and a wet chemical or dry etch, for example reactive ion etching (RIE) to remove portions of substrate110. In one example cavities614and616may be formed using an anisotropic RIE etch. Cavities614and616may be referred to as voids, open voids, cavities, open cavities, pores, openings or trenches. In one embodiment, cavities614and616may have an aspect ratio (the ratio of the depth to width) of at least two (2). In another example, the aspect ratio may be at least ten (10). For a given width, a larger aspect ratio will result in a larger interconnect cross-sectional area, and thus reduced interconnect resistance. The formation of cavities614and616may form a vertical structure620between two cavities614, a vertical structure621between cavity614and616and a vertical structure622between two cavities616. Vertical structures620,621and622may be comprised of a portion of substrate110.

While the sidewalls690and695inFIG. 6are shown as perpendicular to, or substantially perpendicular to surface105of substrate110, other sidewall profiles may also be utilized and the specific sidewall profile is not a limitation of the claimed subject matter. In one embodiment, one etching step may be used to form cavities614and616, although the methods and apparatuses described herein are not limited in this regard.

FIG. 7shows semiconductor structure200ofFIG. 6at a later stage of manufacture. Referring now toFIG. 7dielectric material104is formed on the exposed surfaces of cavities614and616(FIG. 6). In one example, dielectric material104is silicon dioxide and is formed by thermal oxidation. In this example thermal oxidation may be performed to convert a portion of, all of, or substantially all of, the exposed silicon of cavities614and616to silicon dioxide to form silicon dioxide material104.

As discussed above, the width of vertical structures620,621and622may be in the range of about 3.0 microns or less in some embodiments. In the example where vertical structures620,621and622comprise silicon, the thicker the width of silicon structures620,621and622, the longer it will take to fully oxidize silicon structures620,621and622.FIG. 7shows an example where all of the silicon in silicon structures620,621and622has been completely converted to silicon dioxide. However, this is not a limitation of the claimed subject matter and in other embodiments, only a portion of the silicon in silicon structures620,621and/or622may be converted to silicon dioxide. In one example cavities712may have a width in the range of about 1.0 micron to about 3.0 microns.

In this example the silicon underneath masked areas520(FIG. 5),521(FIG. 5) and 522(FIG. 5) may be completely oxidized and the dimensions of masked areas520(FIG. 5),521(FIG. 5) and 522(FIG. 5) and openings514(FIG. 5) may be substantially equal such that cavities614(FIG. 6) are eliminated through the oxidation process, leaving only oxide104and cavities712. Cavities614may be eliminated because of the 2.2× volume expansion that silicon undergoes when it is oxidized. This volume expansion may also result in a reduction in the width of cavity712compared to the width of cavity616(FIG. 6) before oxidation. In this embodiment, dielectric material104forms the dielectric structure104discussed above with reference toFIG. 4and accordingly dielectric material104may be referred to as dielectric structure104in subsequent figures. As discussed above, in other embodiments, dielectric structure104may include voids and/or more than one dielectric material.

Although the widths of cavities712inFIG. 7are all the same, this is not a limitation of the claimed subject matter. In other embodiments, cavities712may have different widths. The result of this oxidation process is the formation of cavities712in dielectric structure104. Cavities712may eventually be filled or partially filled with an electrically conductive material to form interconnect1212(FIG. 4).

In one example the depth of cavities712may be in the range of about 2 microns to about 40 microns. In another example the depth of cavities712may be in the range of about 4 microns to about 20 microns. In one example spacing between cavities712may be in the range of about 0.2 microns to about 2 microns.

Although cavities712are shown as rectangular, this is not a limitation of the claimed subject matter and cavities712may have any shape and may be formed in a periodic or non-periodic arrangement. In the example shown inFIG. 7all silicon110underneath masked areas520(FIG. 5),521(FIG. 5) and 522(FIG. 5) may be completely oxidized, leaving only oxide and no silicon. In other embodiments, silicon110underneath masked areas520(FIG. 5),521(FIG. 5) and 522(FIG. 5) may only be partially oxidized, leaving some silicon material embedded in oxide104.

Since the dielectric constant of silicon is greater than the dielectric constant of silicon dioxide, reducing the amount of silicon remaining in silicon structures620(FIG. 6),621(FIG. 6) and/or622(FIG. 6) may reduce the effective dielectric constant of dielectric structure104.

FIG. 8shows semiconductor structure200ofFIG. 7at a later stage of manufacture. As discussed above, in this example the interconnect structure may be formed after device fabrication. Turning now toFIG. 8, cavities712may be filled with a sacrificial material812. In one example sacrificial material812may comprise polysilicon and may be formed using low pressure chemical vapor deposition (LPCVD). After formation of sacrificial material812, excess sacrificial material812may be removed, leaving sacrificial material812only in cavities712(FIG. 7) with a surface coplanar or substantially coplanar with surface105of substrate110. Excess sacrificial material812may be removed using wet chemical etching, dry (RIE) etching, chemical mechanical polishing (CMP) or a combination of these processes. Other suitable materials for sacrificial material812include silicon nitride, phosphorus silicate glass (PSG), boron phosphorus silicate glass (BPSG), an oxide formed using tetraethylorthosilicate (TEOS), or the like.

Turning now toFIG. 9,FIG. 9shows semiconductor structure200ofFIG. 8at a later stage of manufacture. At this stage of the process, dielectric layers510and512may be optionally removed. Referring to the example shown inFIG. 9, dielectric layers510and512have been removed. Dielectric layers510and512may be removed as part of the process of removing excess sacrificial material812or in one or more separate steps.

After optional removal of dielectric layers510and512, protection structure920may be formed over sacrificial material812and dielectric structure104for protection during subsequent processing. Protection structure920may comprise one or more layers. In the embodiment shown inFIG. 9protection structure920is comprised of layers910and912.

At the stage illustrated inFIG. 9, dielectric layer910may be formed over sacrificial material812, dielectric structure104and a portion of substrate110, and dielectric layer912may be formed over dielectric layer910. In one example dielectric layer910may be silicon dioxide and dielectric layer912may be silicon nitride. Dielectric layer910may comprise, for example, silicon dioxide and have a thickness ranging from about 50 Å to about 5,000 Å. Dielectric layer910may be formed using deposition techniques, such as for example low pressure chemical vapor deposition (LPVCD). Dielectric layer912may comprise, for example, silicon nitride (Si3N4) and have a thickness ranging from about 100 Å to about 2,000 Å. Dielectric layer912may be formed using deposition techniques, for example, low pressure chemical vapor deposition (LPVCD) of silicon nitride.

After formation of protection structure920, active devices may be formed in portions of substrate110using conventional techniques.FIG. 10shows semiconductor structure200ofFIG. 9at a later stage of manufacture. As seen inFIG. 10, FET101may be formed in active region20and FET102may be formed in active region21. After formation of active devices, active device protection layer1010may be formed over active regions20and21, and protection structure920. Active protection layer1010may comprise dielectric materials such as silicon dioxide, silicon nitride, phosphorus silicate glass (PSG), boron phosphorus silicate glass (BPSG), an oxide formed using tetraethylorthosilicate (TEOS), or the like. In one example active device protection layer1010may comprise silicon dioxide formed by plasma enhanced CVD (PECVD) deposition. In one example the thickness of active device protection layer1010may range from about 0.2 microns to about 5 microns. While active device protection layer1010shown inFIG. 10is comprised of one layer, this is not a limitation of the claimed subject matter and active device protection layer1010may be comprised of more than one layer.

FIG. 11shows semiconductor structure200ofFIG. 10at a later stage of manufacture. After formation of active protection layer1010, active protection layer1010, dielectric layer912and dielectric layer910may be patterned using photolithography and etching processes to form openings1120to expose sacrificial material812(FIG. 10). Openings1120may be formed using at least one etching operation. In some embodiments, two etching or more etching operations may be used to form openings1120. In some embodiments, active protection layer1010may be etched using a wet chemical etch or a dry etch process such as, for example, a reactive ion etch (RIE). Silicon nitride layer912may be etched using a wet chemical etch or a dry etch process such as, for example, a reactive ion etch (RIE). Silicon dioxide layer910may be etched using a wet chemical etch or a dry etch process such as, for example, a reactive ion etch (RIE).

The width of openings1120may be in the range of about 0.5 microns to about 3 microns. In one example openings1120may be in the range of about 1.0 microns to about 2 microns. Although the width of openings1120shown inFIG. 11is substantially the same, this is not a limitation of the claimed subject matter. The width of openings1120do not have to be the same, or substantially the same. Further, although openings1120are shown as rectangular, this is not a limitation of the claimed subject matter. Openings1120may have any shape and may be formed in a periodic or non-periodic arrangement.

After formation of openings1120, sacrificial material812(FIG. 10) may be removed through openings1120. In one embodiment, one etching step may be used to remove sacrificial material812(FIG. 10), although the methods and apparatuses described herein are not limited in this regard. In another embodiment, sacrificial material812(FIG. 10) may be removed in the same etching step as used for removal of a portion of dielectric layer910to form openings1120. In one example sacrificial material812(FIG. 10) may be removed using a vapor phase etch, a wet chemical etch, or a dry etch, for example reactive ion etching (RIE). Removal of sacrificial material812(FIG. 10) leaves cavities1112with sidewalls1190, as shown inFIG. 11. While sidewalls1190are shown as perpendicular or substantially perpendicular to surface105of substrate110this is not a limitation of the claimed subject matter and sidewalls1190may make any arbitrary angle with surface105.

FIG. 12shows semiconductor structure200ofFIG. 11at a later stage of manufacture. After removal of sacrificial material812(FIG. 10) and resulting formation of cavities1112(FIG. 11), cavities1112(FIG. 11) may be filled with an electrically conductive material to form bus lines1212. Bus lines1212may be formed by first filling cavities1112(FIG. 11) with a conductive material followed by optional removal of excess conductive material. In one example the amount of conductive material that may need to be deposited is that sufficient to partially or fully fill cavities1112(FIG. 11). The top surface of bus line1212may range from below surface105of substrate110to coplanar or substantially coplanar with the surface of layer1010. In the example shown inFIG. 12, the top surface of bus line1212may be above surface105of substrate110and below the surface of layer1010.

Bus line1212may be formed using deposition processes such as evaporation, sputtering, or chemical vapor deposition (CVD). Bus line1212may also be formed using plating or electroplating. In one example bus line1212may comprise more than one material deposited sequentially; for example bus line1212may comprise three layers of titanium/titanium nitride/tungsten. The Ti layer may act as an adhesion layer and may be in the range of about 100 Å to about 500 Å thick. The TIN layer may act as a barrier layer and may be in the range of about 200 Å to about 1000 Å thick. The final tungsten layer may then be deposited to partially or completely fill or overfill cavities1112(FIG. 11). The materials and dimensions given here are for one or more embodiments and are not a limitation of the claimed subject matter. Other dimensions may be used.

FIG. 13shows semiconductor structure200ofFIG. 12at a later stage of manufacture. After formation of bus line1212, dielectric layer1310may be formed and patterned to form openings1320to expose one or more bus lines1212and to form openings1322to expose drain112of FET101and drain122of FET102. Dielectric layer1310may comprise dielectric materials such as silicon dioxide, silicon nitride, phosphorus silicate glass (PSG), boron phosphorus silicate glass (BPSG), an oxide formed using tetraethylorthosilicate (TEOS), or the like. In one example dielectric layer1310may comprise silicon dioxide formed by PECVD deposition. In one example the thickness of dielectric layer1310may range from about 0.2 microns to about 5 microns. While dielectric layer1310shown inFIG. 13is comprised of one layer, this is not a limitation of the claimed subject matter and dielectric layer1310may be comprised of more than one layer.

The width of openings1320and1322may be in the range of about 0.25 microns to about 3 microns. In one example openings1320and1322may be in the range of about 0.4 microns to about 1.5 microns. Although the width of openings1320and1322shown inFIG. 13is substantially the same, this is not a limitation of the claimed subject matter. The width of openings1320and1322do not have to be the same, or substantially the same. Further, although openings1320and1322are shown as rectangular, this is not a limitation of the claimed subject matter. Openings1320and1322may have any shape and may be formed in a periodic or non-periodic arrangement. In another embodiment, dielectric layer1310may be omitted.

Turning back toFIG. 4,FIG. 4shows semiconductor structure200ofFIG. 13at a later stage of manufacture. After formation of openings1320to expose bus lines1212and openings1322to expose drain112of FET101and drain122of FET102, interconnects1350may be formed using deposition processes such as evaporation, sputtering, or chemical vapor deposition (CVD). Interconnects1350may also be formed using plating or electroplating. In one example interconnect1350may comprise AuSiCu where the percentage of Si may range from about 0.4% to about 1.5% and the percentage of Cu may range from about 0.4% to about 1.5%. In another example interconnects1350may comprise more than one material deposited sequentially; for example interconnects1350may comprise three layers of titanium/titanium nitride/aluminum+silicon+copper (Ti/TiN/AISiCu). The Ti layer may act as an adhesion layer and may be in the range of about 10 Å to about 500 Å thick. The TiN layer may act as a barrier layer and may be in the range of about 200 Å to about 1000 Å thick. The AI/Si/Cu layer may be in the range of about 0.25 micron to about 4 microns thick. The materials and dimensions given here are for one or more embodiments and are not a limitation of the claimed subject matter. Other materials, for example aluminum+silicon (AISi), titanium+tungsten (TiW) and titanium+tungsten+copper (TiWCu), as well as other dimensions may be used.

After deposition of the interconnect metal it may be patterned using photolithography and etching processes to form interconnect1350. Interconnects1350may be formed using at least one etching operation. In some embodiments, two etching or more etching operations may be used to form interconnects1350. For example interconnect1350may be etched using a wet chemical etch or a dry etch process such as, for example, a reactive ion etch (RIE).

In the example process flow described above, the metallization for the buried bus lines is fabricated after the fabrication of the active devices. In another embodiment shown inFIG. 14, the metallization for the buried bus lines may be fabricated before the fabrication of the active devices. Turning toFIG. 14,FIG. 14shows semiconductor structure300which is comprised of dielectric structure104, conductive bus lines1212and1213, interconnects1350, active region21and substrate110. Conductive bus lines1212and1213may be separated from dielectric structure104by sealed gaps1850A. Conductive bus lines1212and1213may be referred to as bus lines, buried bus lines, interconnects or buried interconnects. Although bus lines1212and1213are shown as all having the same thicknesses, this is not a limitation of the claimed subject matter, and bus lines1212and1213may have different thicknesses. In the example shown inFIG. 14, bus lines1212and1213have different widths, in contrast to the example shown inFIG. 4, where all the bus lines have the same width. While sealed gaps1850A are shown as having the same widths, this is not a limitation of the claimed subject matter and sealed gaps 850 Å may have different widths.

Referring now toFIG. 14, field effect transistor (FET)102may be formed in active region21. FET102may be a MOSFET and may include a source region120in a portion of substrate110, a drain region122in a portion of substrate110, a gate oxide124over a portion of substrate110, a gate126over gate oxide124, and a channel region128formed in a portion of substrate110under gate oxide124and between doped regions120and122. Although one active region and one FET in the active region is shown, this is not a limitation of the claimed subject matter and more than one active region may be present and each active region may contain more than one transistor, diode or other active devices.

Substrate110may serve as part of a drain region of a vertical transistor (not shown) formed in active region21. In this example, a source contact or electrode (not shown) may be formed on or adjacent to an upper surface of substrate110and a drain electrode (not shown) may be formed on or adjacent to a lower surface of substrate110. During operation, the electrical current flow from the source electrode to the drain electrode in the vertical transistor may be substantially perpendicular to the upper and lower surfaces of semiconductor substrate110. In other words, current flows essentially vertically through the vertical transistor from the electrode located adjacent a top surface of semiconductor structure300to a drain electrode located adjacent to the opposite bottom surface of semiconductor structure300. An example of a vertical transistor is described in U.S. patent application Ser. No. 10/557,135, entitled “POWER SEMICONDUCTOR DEVICE AND METHOD THEREFOR,” filed Nov. 17, 2005, which claims priority to Patent Cooperation Treaty (PCT) International Application Number PCT/US2005/000205 entitled “POWER SEMICONDUCTOR DEVICE AND METHOD THEREFOR,” having an International Filing Date of Jan. 6, 2005 and an International Publication Date of Jul. 28, 2005, the contents of both of these patent applications are incorporated herein by reference in their entirety.

FIGS. 15 to 20illustrate another embodiment for making semiconductor structure300ofFIG. 14. In this example the interconnect structure is fabricated after fabrication of active devices.FIG. 15shows semiconductor structure300ofFIG. 14at an early stage of manufacture. The process to fabricate the structure at the stage shown inFIG. 15is the same as the process described previously in reference toFIGS. 5-7of the previous example with the exception that all of the cavities712(FIG. 7) may not have the same width. Turning toFIG. 15, cavities712may have the same width and a second cavity713may have a different width. In this example second cavity713may have a width relatively larger than that of cavity712. The example shown inFIG. 15is not meant to be limiting and there may be any number of cavities each of which may have any width. The width may be in part determined by the required resistance of the bus line. In one example cavities712may have a width in the range of about 1.0 micron to about 3.0 microns and cavities713may have a width in the range of about 2.0 microns to about 10.0 microns.

FIG. 16shows semiconductor structure300ofFIG. 15at a later stage of manufacture. After formation of cavities712(FIG. 15) and 713(FIG. 15), sacrificial layer1410may be formed over dielectric layer512and dielectric structure104including the interior surfaces of cavities712(FIG. 15) and 713(FIG. 15). Sacrificial layer1410may be polysilicon, a dielectric, or any other material that may be subsequently removed, as will be described below. In one example sacrificial layer1410may be able to be selectively etched, without etching dielectric structure104or bus lines1212(FIG. 14) or bus lines1213(FIG. 14). In one example, sacrificial layer1410may be polysilicon deposited by low pressure chemical vapor deposition (LPCVD) and have a thickness in the range of about 0.1 microns to about 3.0 microns. The thickness of sacrificial layer1410may determine the separation between subsequently formed bus line1212(FIG. 14) and/or1213(FIG. 14) and dielectric structure104. In other words, the thickness of sacrificial layer1410may determine the width of sealed gaps1850A (FIG. 14). In one example the thickness of sacrificial layer1410may be in the range of about 0.1 micron to about 3.0 microns.

After formation of sacrificial layer1410, conductive material1420may be formed over sacrificial layer1410to eventually form bus lines1212(FIG. 14) and 1213(FIG. 14). Bus line1212(FIG. 14) may be formed by partially or completely filling cavity712(FIG. 15) and bus line1213(FIG. 14) may be formed by partially or completely filling cavity713(FIG. 15). Conductive material for bus line1212(FIG. 14) and 1213(FIG. 14) may be formed using deposition processes such as evaporation, sputtering, or chemical vapor deposition (CVD), plating or electroplating. The amount of conductive material that may need to be deposited is that sufficient to partially or fully fill cavities712(FIG. 15) and 713(FIG. 15). In one example the thickness of conductive material1420may be sufficient to completely fill cavities712(FIG. 15) and 713(FIG. 15). In another example conductive material1420may be sufficiently thick to completely fill cavities712(FIG. 15) and 713(FIG. 15) and to extend above top surface105of substrate110. In one example conductive material1420may extend above top surface105of substrate110by about 0.1 micron to about 4.0 microns.

In one example conductive material1420may comprise more than one material deposited sequentially, for example conductive material1420may comprise three layers of titanium/titanium nitride/tungsten. The Ti layer may act as an adhesion layer and may be in the range of about 100 Å to about 500 Å thick. The TiN layer may act as a barrier layer and may be in the range of about 200 Å to about 1000 Å thick. The final tungsten layer would then be deposited to partially or completely fill or overfill cavities712(FIG. 15) and 713(FIG. 15). In the example shown inFIG. 16, conductive material1420has been deposited to a thickness to overfill cavities712(FIG. 15) and 713(FIG. 15). The materials and dimensions given here are for one or more embodiments and are not a limitation of the claimed subject matter. Other dimensions may be used.

FIG. 17shows semiconductor structure300ofFIG. 16at a later stage of manufacture. After formation of conductive material1420(FIG. 16), excess conductive material1420(FIG. 16) may be removed to form bus lines1212and1213. The top surface of bus lines1212and1213may range from below surface105of substrate110to coplanar or substantially coplanar with the surface105of substrate110. In the example shown inFIGS. 14 and 17, the top surface of bus lines1212and1213is coplanar or substantially coplanar with surface105of substrate110. Excess conductive material1420(FIG. 16) may be removed using wet chemical etching, dry (RIE) etching, chemical mechanical polishing (CMP) or a combination of these processes. Dielectric layers510and512(FIG. 16) may be optionally removed at this stage of the process. In one example dielectric layers510and512(FIG. 16) may be removed simultaneously with the removal of excess conductive material1420(FIG. 16). In the example shown inFIG. 17, dielectric layers510and512(FIG. 16) have been removed.

After removal of excess conductive material1420(FIG. 16) to form bus lines1212and1213, dielectric layer1610may be formed over portions of substrate110, dielectric structure104, sacrificial material1410and bus lines1212and1213. Dielectric layer1610may comprise dielectric materials such as silicon dioxide, silicon nitride, phosphorus silicate glass (PSG), boron phosphorus silicate glass (BPSG), an oxide formed using tetraethylorthosilicate (TEOS), or the like. In one example dielectric layer1610may comprise silicon dioxide formed by LPCVD deposition. In one example the thickness of dielectric layer1610may range from about 500 A to about 2.0 microns. While dielectric layer1610shown inFIG. 17is comprised of one layer, this is not a limitation of the claimed subject matter and dielectric layer1610may be comprised of more than one layer. In one example dielectric layer1610may comprise a material for which a selective etch exists relative to sacrificial material1410. In other words, sacrificial material1410and dielectric layer1610are chosen such that when etching sacrificial material1410, the etch rate of dielectric layer1610is relatively small compared to the etch rate of sacrificial material1410. In one example the ratio of the etch rates between sacrificial material1410and dielectric layer1610is greater than 40; in another example this ratio is greater than 100.

FIG. 18shows semiconductor structure300ofFIG. 17at a later stage of manufacture.FIG. 19shows a plan view of semiconductor structure300ofFIG. 18. The cross-sectional view shown inFIG. 18is taken along section lines18-18ofFIG. 19. After formation of dielectric layer1610, dielectric layer1610may be patterned using photolithography and etching processes to form openings1720to expose a portion of sacrificial layer1410. Dielectric layer1610may be etched using a wet chemical etch or a dry etch process such as, for example, a reactive ion etch (RIE).

The width of openings1720may be in the range of about 0.1 microns to about 2 microns. In one example the width of openings1720may be in the range of about 0.1 microns to about 0.5 microns less than the width of sacrificial material1410(FIG. 17) at top surface105of substrate110. The width of openings1720may be chosen to facilitate eventual sealing of these holes during formation of dielectric layer1910(FIG. 14). Although the width of openings1720shown inFIG. 18is substantially the same, this is not a limitation of the claimed subject matter. The width of openings1720do not have to be the same, or substantially the same. Further, although openings1720are shown as rectangular, this is not a limitation of the claimed subject matter and openings1720may have any shape.

After formation of openings1720to expose sacrificial material1410, sacrificial material1410may be partially or completely removed to form gaps1850. Gap1850may also be referred to as a void, an air gap, a cavity an empty region, an empty space or the like. Sacrificial material1410may be removed using a vapor etch, a wet chemical etch, a dry reactive ion etch (RIE) or a combination of wet and dry etching. In the example shown inFIG. 18, in the plane of this cross-sectional view, sacrificial material1410has been completely removed surrounding bus lines1212and1213to form gaps1850. As discussed above, gaps1850provides a further decrease in the dielectric constant of the volume surrounding bus lines1212and1213, resulting in a reduction in parasitic capacitance and cross-talk.

Turning toFIG. 19, in one example gaps1850may not completely enclose bus lines1212and1213. In the example shown inFIG. 19, gaps1850are separated by regions in which sacrificial material1410may not be removed. In this example remaining sacrificial material1410between gaps1850may be connected to bus lines1212and1213and connected to dielectric structure104. In this example, remaining sacrificial material1410between gaps1850may act as a support for bus lines1212and1213, to prevent them from twisting or bending. In one example the length of each gap1850may be in the range of about 25 microns to about 200 microns and the length of remaining sacrificial material1410between gaps1850may be in the range of about 1 microns to about 20 microns.

Turning now toFIG. 20,FIG. 20shows semiconductor structure300ofFIG. 18at a later stage of manufacture. After partial or complete removal of sacrificial material1410, capping layer1910may be formed over dielectric layer1610and openings1720(FIG. 18) to form sealed gaps1850A. In other words, when capped, gap1850is identified by reference number1850A and may be referred to as sealed gap, sealed cavity, a sealed gap, a sealed void, a closed cell, a closed cell void or the like.

In some embodiments, sealed gap1850A may be evacuated to a pressure less than atmospheric pressure. In other words, the pressure in sealed gap1850A may be below atmospheric pressure. As an example, the pressure in sealed gap1850A may range from approximately 0.1 Torr to approximately 10 Torr. The type of substance or material within sealed gap1850A is not a limitation of the claimed subject matter. For example, sealed gap1850A may contain a gas, a fluid, or a solid matter.

Capping layer1910may comprise dielectric materials such as silicon dioxide, silicon nitride, phosphorus silicate glass (PSG), boron phosphorus silicate glass (BPSG), an oxide formed using tetraethylorthosilicate (TEOS), or the like. In one example capping layer1910may comprise silicon dioxide formed by LPCVD deposition. In one example the thickness of capping layer1910may range from about 0.2 microns to about 5 microns.

In some embodiments, because of the size of openings1720(FIG. 18), capping layer1910may enter into a portion of sealed gap1850A, but not fill sealed gap1850A, due in part to the relatively small size of the openings1720(FIG. 18).

While capping layer1910shown inFIG. 20is comprised of one layer, this is not a limitation of the claimed subject matter and capping layer1910may be comprised of more than one layer. In one example an optional conformal sealing layer (not shown inFIG. 20) such as, for example, silicon nitride (Si3N4), may be formed on silicon dioxide layer1910to hermetically seal sealed gap1850A. In other words, the optional conformal silicon nitride layer may fill in any openings or cracks in the silicon dioxide capping layer1910, and in general prevent the propagation of gases or moisture into sealed gaps1850A. In some embodiments, sealed gap1850A may be multiple cavities that are physically isolated from each other, as shown inFIG. 20. Accordingly, if capping layer1910experiences a rupture or fracture, this rupture or fracture is contained in a limited area so that any external contamination that propagates into sealed gap1850A through the rupture or fracture may be contained in a limited area due to the physical isolation of the multiple cavities from each other.

In addition to sealing gaps1850(FIG. 18), capping layer1910may also serve as a protective layer for dielectric structure104and bus lines1212and1213during subsequent fabrication of active devices.

Turning now toFIG. 21,FIG. 21shows semiconductor structure300ofFIG. 20at a later stage of manufacture. After formation of capping layer1910, active devices may be formed in portions of substrate110using conventional techniques.

As seen inFIG. 21, FET102may be formed in active region21. After formation of active devices, dielectric layer2010may be formed over active region21and capping layer1920. Dielectric layer2010may comprise dielectric materials such as silicon dioxide, silicon nitride, phosphorus silicate glass (PSG), boron phosphorus silicate glass (BPSG), an oxide formed using tetraethylorthosilicate (TEOS), or the like. In one example dielectric layer2010may comprise silicon dioxide formed by PECVD deposition. In one example the thickness of dielectric layer2010may range from about 0.2 microns to about 5 microns. While dielectric layer2010shown inFIG. 21is comprised of one layer, this is not a limitation of the claimed subject matter and dielectric layer2010may be comprised of more than one layer.

After formation of dielectric layer2010, processing similar to that described in the above example may be performed to form interconnects1350(FIG. 14) resulting in semiconductor structure300shown inFIG. 14. In short this may comprise patterning using photolithography and etching dielectric layer2010, dielectric layer1910and dielectric layer1610to form openings to expose bus line1212and1213and drain122of FET102followed by deposition and patterning of conductive material to form interconnects1350, as shown inFIG. 14.

In the examples described above, one bus line is shown in each cavity. However this is not a limitation of the claimed subject matter, and a plurality of bus lines may be formed in a single cavity. In this case, each bus line may be contacted separately.FIGS. 22-24show an example of one or more embodiments comprising a two-level bus line.FIG. 22shows a plan view of semiconductor structure400,FIG. 23shows a cross-sectional view of semiconductor structure400inFIG. 22taken along section line23-23andFIG. 24shows a cross sectional view of semiconductor structure400inFIG. 22taken along section line24-24.

Turning first toFIG. 24, bus line1212B may be formed over bus line1212A and may be separated from bus line1212B by dielectric layer2610. Bus line1212B may be coupled to interconnect1350A and bus line1212A may be coupled to interconnect1350(FIG. 23). That is, at section line23-23shown inFIG. 23, interconnect1350may be coupled to bottom bus line1212A and at section line24-24shown inFIG. 24interconnect1350A may be coupled to top bus line1212B. Although two vertically stacked bus lines are shown in the example inFIGS. 22-24, this is not a limitation of the claimed subject matter and two or more bus lines may be formed in a single cavity by stacking them either vertically or horizontally.

Turning now toFIG. 22, bus lines1212and1212B are shown with dashed lines, indicating that they are beneath the surface. Bus line1212A is not shown inFIG. 22because it is underneath bus line1212B. The outline of dielectric structure104is also shown with dashed lines, again indicating that it is below the surface. Interconnect1351may couple to bus line1212; the other end of interconnect1351is not shown inFIG. 22.

Field effect transistor (FET)101and FET102may be formed in active region21. FET101may be a MOSFET and may include a source region110in a portion of substrate111, a drain region112in a portion of substrate110, a gate oxide114over a portion of substrate110, a gate116over gate oxide114, and a channel region118formed in a portion of substrate110under gate oxide114and between doped regions110and112. FET102may be formed in active region21and may be a MOSFET and may include a source region120in a portion of substrate110, a drain region122in a portion of substrate110, a gate oxide124over a portion of substrate110, a gate126over gate oxide124, and a channel region128formed in a portion of substrate110under gate oxide124and between doped regions120and122. In one example drain112(FIG. 23) of FET101may be coupled to interconnect1350and drain122(FIG. 24) of FET102may be coupled to interconnect1350A. In this example active region21may contain two FETs, however this is not a limitation of the claimed subject matter and in other embodiments there may be more than one active region and each active region may contain one or more active devices.

Turning now toFIG. 23, a portion of bus line1212B (FIG. 24) over bus line1212A may be removed to provide access to bus line1212A and bus line1212A may be coupled to interconnect1350.

FIGS. 25-31illustrate one embodiment for making semiconductor structure400ofFIGS. 22-24.FIG. 25shows semiconductor structure300ofFIG. 14at an early stage of manufacture. The process to fabricate the structure at the stage shown inFIG. 25may start at the same stage as that of semiconductor structure300shown inFIG. 17.

FIG. 25shows semiconductor structure300ofFIG. 17at a later stage of manufacture. After formation of dielectric layer1610, dielectric layer1610may be patterned using photolithography and etching processes to form opening2575to expose bus line1213(FIG. 17). Dielectric layer1610may be etched using a wet chemical etch or a dry etch process such as, for example, a reactive ion etch (RIE).

After formation of opening2575to bus line1213(FIG. 17), bus line1213(FIG. 17) may be partially removed to form bus line1212A. A portion of bus line1213(FIG. 17) may be removed using a wet chemical, a dry reactive ion etch (RIE) or a combination of wet and dry etching. In one example the vertical thickness of bus line1212A after etching may be in the range of about 20% to about 80% of the depth of cavity713(FIG. 15).

Turning now toFIG. 26,FIG. 26shows semiconductor structure400ofFIG. 25at a later stage of manufacture. After formation of opening2575dielectric layer2610may be formed over dielectric layer1610, a portion of sacrificial material1410and bus line1212A.

Dielectric layer2610may comprise dielectric materials such as silicon dioxide, silicon nitride, phosphorus silicate glass (PSG), boron phosphorus silicate glass (BPSG), an oxide formed using tetraethylorthosilicate (TEOS), or the like. In one example dielectric layer2610may comprise silicon dioxide formed by LPCVD deposition. In one example the thickness of dielectric layer2610may range from about 0.1 microns to about 2 microns.

Turning now toFIG. 27,FIG. 27shows semiconductor structure400ofFIG. 26at a later stage of manufacture. After formation of dielectric layer2610, conductive material2710may be formed over dielectric layer2610. Conductive material2710may be subsequently patterned to become bus line1212B (FIG. 24).

In one example conductive material2710may comprise the same material used to form bus line1212A, although this is not a limitation of the claimed subject matter and in some embodiments bus line1212A may be formed of a different material than bus line1212B. Conductive material2710may be formed to a thickness such that the top surface of conductive material2710over bus line1212A is coplanar or substantially coplanar with surface105of substrate110.

FIG. 28shows semiconductor structure400ofFIG. 27at a later stage of manufacture. After formation of conductive material2710(FIG. 27), excess conductive material2710(FIG. 27) may be removed to form bus line1212B. The surface of bus line1212B may range from below surface105of substrate110to coplanar or substantially coplanar with the surface105of substrate110. In the example shown inFIG. 28, the surface of bus line1212B is coplanar or substantially coplanar with surface105of substrate110. Excess conductive material2710(FIG. 27) may be removed using wet chemical etching, dry (RIE) etching, chemical mechanical polishing (CMP) or a combination of these processes.

Turning now toFIG. 29,FIG. 29shows semiconductor structure400ofFIG. 28at a later stage of manufacture. After formation of bus line1212B dielectric layer2910may be formed over dielectric layer2610and bus line1212B.

Dielectric layer2910may comprise dielectric materials such as silicon dioxide, silicon nitride, phosphorus silicate glass (PSG), boron phosphorus silicate glass (BPSG), an oxide formed using tetraethylorthosilicate (TEOS), or the like. In one example dielectric layer2910may comprise silicon dioxide formed by LPCVD deposition. In one example the thickness of dielectric layer2910may range from about 0.1 microns to about 2 microns.

Turning now toFIG. 30,FIG. 30shows semiconductor structure400ofFIG. 29at a later stage of manufacture. After formation of dielectric layer2910, dielectric layer2910, dielectric layer2610and dielectric layer1610may be patterned using photolithography and etching processes to form openings1720to expose a portion of sacrificial layer1410. Dielectric layers2910,2610and1610may be removed using one or more processes. In one example, dielectric layers2910,2610and1610may be etched using a wet chemical etch or a dry etch process such as, for example, a reactive ion etch (RIE). This process is similar to that described above with reference toFIG. 18.

After formation of openings1720to expose sacrificial material1410, sacrificial material1410may be partially or completely removed to form gaps1850. Gap1850may also be referred to as a void, an air gap, a cavity an empty region, an empty space or the like. Sacrificial material1410may be removed using a vapor etch, a wet chemical etch, a dry reactive ion etch (RIE) or a combination of wet and dry etching. As discussed above, gaps1850provides a further decrease in the dielectric constant of the volume surrounding bus lines1212,1212A and1212B, resulting in a reduction in parasitic capacitance and cross-talk. This process is similar to that described above with reference toFIG. 18. Although not shown, openings1720can be sealed using a nonconformal material such as, for example, oxide, nitride, TEOS oxide, or PSG, formed using PECVD.

After formation of gaps1850, processing similar to that described in the above example with reference toFIGS. 20-21may be performed to form active devices and interconnects resulting in semiconductor structure400shown inFIGS. 22-24.

During fabrication of the structures of one or more embodiments, the oxidation process to form dielectric material104may induce stress in the semiconductor structure. Stress may be induced in the structure as a result of the 2.2× volume expansion that occurs when silicon is oxidized. Stress may have an adverse effect on the performance of active devices. For example stress may result in the formation of dislocations or defects which may cause excessive leakage current. This stress may be partially or substantially removed in a portion or all of the semiconductor structure through the addition of a stress relief trench.

FIG. 31shows semiconductor structure500which may incorporate a stress relief trench3150. Semiconductor structure500is similar to that of semiconductor structure200shown inFIG. 4. In some embodiments stress relief trench3150may partially or substantially reduce the stress in semiconductor material110outside of dielectric structure104. Stress relief trench3150may be formed before or after the formation of dielectric structure104inFIG. 7. In the example shown inFIG. 31stress relief trench3150may be formed after formation of dielectric material104. Stress relief trench3150may be filled with sacrificial material812, as shown in the example inFIG. 31. However this is not a limitation of the claimed subject matter and stress relief trench3150may be filled with any other material, for example a dielectric or a polymer, and in general may contain a gas, a fluid or a solid matter. In some embodiments, stress relief trench3150may be at least partially empty and may be evacuated to a pressure less than atmospheric pressure. In other words, the pressure in stress relief trench3150may be below atmospheric pressure. As an example, the pressure in stress relief trench3150range from approximately 0.1 Torr to approximately 10 Torr.

Accordingly, various structures and methods have been disclosed to provide a relatively thick, embedded dielectric region that may be a dielectric support structure capable of supporting one or more passive devices and in which interconnects may be embedded. In various embodiments, the disclosed semiconductor structure may provide electrical isolation, reduce parasitic substrate capacitance, allow for the formation of passive devices having a relatively high quality factor (Q), and enable relatively higher frequency of operation of any devices formed using, or in conjunction with, a structure that includes the disclosed dielectric structure. In addition, the disclosed dielectric structure and the methods for making the dielectric structure may enable relatively lower interconnect resistance, relatively lower crosstalk between interconnects and between interconnects and other active and/or passive devices, relatively lower parasitic capacitance and may enable relatively higher frequency of operation of any devices formed using, or in conjunction with, a structure that includes the disclosed dielectric structure.

Although specific embodiments have been disclosed herein, it is not intended that the claimed subject matter be limited to the disclosed embodiments. Those skilled in the art will recognize that modifications and variations can be made without departing from the spirit of the claimed subject matter. It is intended that the claimed subject matter encompass all such modifications and variations as fall within the scope of the appended claims.