Circuit for measuring an eye size of data, and method of measuring the eye size of data

A circuit for measuring an eye size generates first sampled data by sampling received data with recovered clock signals and generates second sampled data by sampling the received data with shifted clock signals, in which the recovered clock signals, having different phases, are recovered from the received data. The shifted clock signals are obtained by shifting each phase of at least one of recovered clock signals by respectively predetermined phases. The circuit generates error counts for calculating the eye size of the received data by comparing the first sampled data and the second sampled data and measures the eye size by obtaining a phase range where the error counts are equal to zero. Therefore, the circuit may measure the eye size without interference of frequency offsets and/or jitter of the received data.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. §119(a) of Korean Patent Application No. 2005-77834 filed on Aug. 24, 2005, the contents of which are herein incorporated by reference in its entirety

BACKGROUND OF THE INVENTION

1. Technical Field

The present disclosure relates to a serial data receiver of a data communication system, and more particularly to a circuit and a method of measuring eye size of serial data in a serial data receiver of a data communication system.

2. Discussion of the Related Art

A serializer-deserializer in a data communication system serializes data so as to transfer the serialized data via transmission lines, such as a printed line, and deserializes serialized data that is received.

Typically, the serializer-deserializer includes a preamplifier, an equalizer, a sampler, and a clock data recovery (CDR) circuit.

The serializer-deserializer recovers a frequency of the serialized data in the CDR circuit and supplies a clock signal with the recovered frequency to the sampler. Therefore, the receiver can receive the serialized data even though a transmitter operates and transmits the serialized data with a clock signal having a different frequency from that of a reference clock used in the receiver.

When data are transmitted at a high speed via a transmission line, such as a printed line, inter-symbol interference (ISI) may occur due to the properties of the transmission line. The amplitude and phase of the received data signal can be seriously distorted by the inter-symbol interference, and the distorted amplitude and phase may cause bit errors in the receiver. Thus, as the length of the transmission line becomes longer and the data transmission rate becomes higher, the distortion of the received signal increases.

Since the serializer-deserializer is a kind of a serial interface, the received serial data may include a high degree of jitter. Therefore, when flip-flops or latches used in the sampler receive the data, the eye size of the data is critical to the performance of the device or the entire system.

The preamplifier in the serializer-deserializer amplifies a voltage level of the received data and the equalizer in the serializer-deserializer executes an equalization of the received data to reduce jitter, specifically ISI, in the received data, and then outputs the equalized signal to the sampler.

The equalizer is provided with a control bit to adjust an equalizing strength, based on the jitter properties of the received data. The equalizer can control the equalization function based on the jitter properties. A relatively small eye size of the received data indicates that the equalization is inadequate, and then the equalizer strengthens the equalization. On the contrary, a relatively large eye size of the received data indicates that the equalization is excessive, and the equalizer weakens the equalization so as to obtain an optimized eye size.

The conventional serializer-deserializer uses a decision feedback circuit to detect a variation of the eye size of the signal, instead of directly measuring the eye size of signal at an output node of the equalizer.

SUMMARY OF THE INVENTION

Exemplary embodiments of the present invention provide a circuit for measuring an eye size of a data signal directly at an output terminal of an equalizer in a receiver of a data communication system.

Exemplary embodiments of the present invention provide a receiver of a data communication system including a circuit for measuring an eye size of the data signal.

Exemplary embodiments of the present invention provide a method of measuring an eye size of a data signal directly at an output terminal of an equalizer in the receiver of a data communication system.

In exemplary embodiments of the present invention, a circuit for measuring an eye size includes a sampler and an error counter. The sampler generates first sampled data by sampling received data based on at least one shifted clock signal, in which the at least one shifted clock signal is obtained by shifting each phase of at least one of recovered clock signals by respectively predetermined phases, and the recovered clock signals have phases that are different from each other and that are recovered from the received data. The error counter generates an error count used for calculating the eye size of the received data by comparing the first sampled data with second sampled data, in which the second sampled data are obtained by sampling the received data based on the at least one of the recovered clock signals.

In exemplary embodiments of the present invention, a circuit for measuring an eye size includes: a sampler configured to generate first sampled data by sampling received data based on at least one shifted clock signal, the at least one shifted clock signal being obtained by shifting each phase of at least one of a plurality of clock signals by respectively predetermined phases, and the plurality of the clock signals having different phases from each other; and an error counter configured to generate an error count for calculating the eye size of the received data by comparing the first sampled data with second sampled data, the second sampled data being obtained by sampling the received data based on at least one of recovered clock signals, the recovered clock signals having different phases and being recovered from the received data.

In exemplary embodiments of the present invention, a receiver of a data communication system includes: a clock data recovery (CDR) circuit for generating a plurality of recovered clock signals, the recovered clock signals having different respective phases and being recovered from received data; a first sampler configured to generate first sampled data by sampling the received data based on at least one of the recovered clock signals; and an eye size measuring circuit configured to measure an eye size of the data by comparing the first sampled data with second sampled data, the second sampled data being obtained by sampling the received data based on at least one of the shifted clock signals, the at least one shifted clock signal being obtained by shifting each phase of the at least one of the recovered clock signals by respectively predetermined phases.

In exemplary embodiments of the present invention, a receiver of a data communication system includes a clock data recovery circuit for generating a plurality of recovered clock signals, the recovered clock signals having different respective phases and being recovered from received data; a first sampler configured to generate first sampled data by sampling the received data based on at least one of the recovered clock signals; and an eye size measuring circuit configured to measure an eye size of the data by comparing the first sampled data with second sampled data, the second sampled data being obtained by sampling the received data based on at least one shifted clock signal, the at least one shifted clock signal being obtained by shifting each phase of at least one of a plurality of clock signals by respectively predetermined respective phases.

In exemplary embodiments of the present invention, a method of measuring an eye size of the data includes: generating first sampled data by sampling received data based on at least one of recovered clock signals, the recovered clock signals having different respective phases and being recovered from the received data; shifting each phase of at least one of the recovered clock signals by respectively predetermined phases to generate at least one shifted clock signal; generating second sampled data by sampling the received data based on the at least one shifted clock signal; and generating an error count for calculating the eye size of the received data by comparing the first sampled data with the second sampled data.

In exemplary embodiments of the present invention, a method of measuring an eye size of received data includes: generating first sampled data by sampling received data based on at least one of recovered clock signals, the recovered clock signals having different phases and being recovered from the received data; shifting each phase of at least one of a plurality of clock signals having different phases by respectively predetermined phases to generate at least one shifted clock signal; generating second sampled data by sampling the received data based on the at least one shifted clock signal; and generating an error count for calculating the eye size of the received data by comparing the first sampled data with the second sampled data.

Therefore, the eye size of received data may be measured without interference of frequency offsets and/or jitter of the received data.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

FIG. 1is a block diagram illustrating a receiver1000of a data communication system including a serializer-deserializer according to an exemplary embodiment of the present invention.

Referring toFIG. 1, the receiver1000includes a preamplifier/equalizer100, a first sampler200, a deserializer300, a clock data recovery (CDR) circuit420, a phase locked loop (PLL)416, an eye size measuring circuit400and a serializer/output-driver350.

The preamplifier/equalizer100compensates the amplitude and delay proportions of a received data signal10of a serial data stream received from a transmission line (not shown) and outputs compensated data101to the first sampler200. More specifically, the preamplifier/equalizer100receives the serial data stream via the transmission line, amplifies the voltage level of the received data signal10, and then compensates the received data signal10for jitter or distortion caused by inter-symbol interference with equalization of the amplified data. The preamplifier/equalizer100adjusts the equalizing strength based on a control bit401fed thereto.

The first sampler200samples the compensated data101from the preamplifier/equalizer100with a plurality of recovered clock signals (I, Q, Ib, and Qb)403, which are recovered from the received data10by the CDR circuit420, so as to output sampled data201.

The deserializer300converts the sampled data201that is in a serial form, which were sampled from the received data signal10by the first sampler200, into deserialized data301in parallel form with a conversion ratio of 1:n, that is, one parallel data word is composed of n serial bits.

The CDR circuit420extracts the recovered clock signals (I, Q, Ib, and Qb)403that were fed to the sampler200based on the deserialized data301output from the deserializer300using multiple reference clocks411from the PLL416.

The CDR circuit420, according to an exemplary embodiment of the present invention shown inFIG. 2, can extract the recovered clock signals403, which are recovered from the received data10, based on the sampled data201from the first sampler200instead of the deserialized data301from the deserializer300inFIG. 1.

The eye size measuring circuit400counts the number of errors based on a comparison result between sampled data, which are sampled from the amplified data101of the preamplifier/equalizer100by shifted clock signals (Q′ and Qb′) and the sampled data201from the first sampler200. The eye size measuring circuit400calculates an eye size of the received data10based on the number of errors. The eye size measuring circuit400also generates the control bit401used to adjust the equalizing strength of the preamplifier/equalizer100that is provided to the preamplifier/equalizer100.

The serializer/output-driver350serializes the data303, which has been processed by another functional block (not shown) based on the output301from the deserializer unit300, and transmits the serialized data via a transmission line (not shown). The serialized data may be amplified before being transmitted by the serializer/output-driver350.

FIG. 3is a detailed block diagram illustrating the receiver including an eye size measuring circuit inFIG. 1according to an exemplary embodiment of the present invention.

The serializer/output-driver350inFIG. 1or inFIG. 2is omitted inFIG. 3. A buffer block110inFIG. 3is disposed between the preamplifier/equalizer100and the first sampler200for buffering the output data of the preamplifier/equalizer100to provide the buffered data to the first sampler200and to a second sampler410. Alternatively, however, the output data of the preamplifier/equalizer100may be provided to the first sampler200or the second sampler410directly not via the buffer block110. Buffer units111and113included in the buffer block110may be identical to each other. The buffer block110may include only one buffer unit to provide an output of that one buffer to both the first sampler200and the second sampler410.

The first sampler200includes a flip-flop I210, a flip-flop Q220, a flip-flop Ib230and a flip-flop Qb240. The first sampler200samples the output data101of the preamplifier/equalizer100with respect to the recovered clock signals (I, Q, Ib, and Qb)403from a first phase interpolator412in the CDR420so as to output the sampled data (DI, DQ, DIb, and DQb)201.

The CDR420includes a phase detector422, a CDR loop filter424, a phase interpolator (PI)412, and a phase interpolation controller (PI controller)426.

When a frequency of the received data signal10is f and the deserializer300executes deserialization with a conversion ratio of 1:n, frequencies of the reference clocks411from the PLL416may be presented as f/2 and frequencies of the multiple recovered clocks403may also be presented as f/2. The phase detector422, the CDR loop filter424, and the PI controller426may be operated at a clock frequency f/(2n).

The frequency f/2 is only for illustration purpose. The frequencies of the reference clocks411of the PLL416and the recovered clocks403are not restricted to the frequency f/2, and other frequencies such as f/4 and f/8 may be used as well.

The CDR circuit420recovers the clock signal and the data from the received data signal10through repetitive recovering processes in which the output of the CDR circuit420is fed back to the first sampler200.

Referring toFIGS. 4 through 6, the CDR circuit420operates the phase detector422, the CDR loop filter424, the PI controller426, and the PI412, so that the recovered clock Q and/or the recovered clock Qb from the first PI412can be placed at a center of a pulse of the data201or the data301, according to exemplary embodiments.

The phase detector422detects a phase of the sampled data201outputted from the first sampler200or the deserialized data301outputted from the deserializer300to generate either an up signal or a down signal. For example, when the frequency of the received data signal10is f and the deserializer executes a deserialization with a conversion ratio of 1:n, the phase detector422, the CDR loop filter424and the PI controller426may be operated at a frequency f/2 in the case of receiving the sampled data201from the first sampler200, or at a frequency f/(2n) in the case of receiving the deserialized data301from the deserializer300.

The CDR loop filter424generates an up command or a down command corresponding to the up signal or the down signal, respectively. The PI controller426generates a digital code405to control the first PI412in response to the up command or the down command.

The up command, as well as the down command, may be given as a one bit code, such that a bit value1indicates the up command and a bit value 0 indicates the down command. Furthermore, the digital code405may be given as a four-bit code, hence phases of the recovered clock signals from the first PI412can be adjusted by 22.5°, that is, 360°/16, using the digital code405that is changeable from 0000 to 1111.

As shown inFIG. 5, the PI controller426may increase the digital code by 1 (1 shift) when receiving the up command UP. On the other hand, the PI controller426may decrease the digital code by 1 when receiving the down command DN.

As shown inFIG. 6, when the digital code is shifted four times, the first PI412may increase or decrease the phases of the recovered clocks by 90°, that is, 22.5°×4.

Referring back toFIG. 3, the first PI412receives four clock signals having phases 0°, 90°, 180°, and 270°, respectively, from the PLL416, and interpolates the four clock signals to generate the four recovered clock signals403. The first PI412increases or decreases the phases of the four recovered clock signals403in response to the digital code405from the PI controller426.

The eye size measuring circuit400includes the second sampler410, an error counter430, a shifted clock generator440, and an eye size controller450.

As represented inFIG. 7, the eye size measuring circuit400compares the sampled data DQ′ and DQb′ with the sampled data DQ and DQb. The sampled data DQ′ and DQb′ are sampled from the amplified data101of the preamplifier/equalizer100using the shifted clock signals Q′ and Ob′ of a second PI442, while the sampled data DQ and DQb are sampled from the amplified data101of the preamplifier/equalizer100using the recovered clock signals Q and Qb of the first PI412. Furthermore, the eye size measuring circuit400counts the number of errors, thereby deciding whether the sampled data DQ′ is equal to the sampled data DQ and/or whether the sampled data DQb′ is equal to the sampled data DQb. Hence, the eye size measuring circuit400estimates the eye size of the received data10based on the number of errors.

Additionally, the eye size measuring circuit400generates the control bit401for adjusting the equalizing strength of the preamplifier/equalizer100and provides the control bit401to the preamplifier/equalizer100.

As shown inFIG. 3, shifted clock generator440includes a shifter445and the second PI442.

The shifter445generates a digital code407by successively shifting bits of the digital code405outputted from the PI controller426in the CDR circuit420. The digital code407is provided to the second PI442from the shifter445. The digital code407has digital values corresponding to the digital code405, and based on the digital values, phases of the output clock signals of the second PI422are shifted in a range from −180° to 180°.

The second PI442receives the digital code407and the reference clock signals411from the PLL416whose phases are respectively 0°, 90°, 180°, and 270°. Based on the received digital code407and the reference clock signals411, the second PI442generates the phase-shifted clock signals (Q′ and Qb′)409, which have gradually shifted phases within a maximum range of ±180° with respect to the recovered clock signals (I, Q, Ib, and Qb)403from the first PI412as illustrated inFIG. 7. That is, the shifter445and the second PI442together generate the phase-shifted clock signals (Q′ and Qb′)409, which are shifted on the basis of the recovered clock signals from the CDR circuit420. Therefore, the eye size may be measured without adverse influence caused by frequency offsets of the received data and/or of jitter in the received data signal.

As shown inFIG. 6andFIG. 7, the phase-shifted clock signals (Q′ and Qb′)409are sequentially shifted from −180° to +180° with respect to the phases of the recovered clock signals (I, Q, Ib and Qb)403of the first PI412. Therefore, the phase-shifted clock signals (Q′ and Qb′)409may be scanned for the entire phase range.

The second sampler410shown inFIG. 3samples the amplified data101of the preamplifier/equalizer100or the output data of the buffer block110using the phase-shifted clock signals (Q′ and Qb′)409so as to output sampled data DQ′ and DQb′.

The error counter430counts the number of errors by comparing the sampled data DQ and DQb of the first sampler200with the sampled data DQ′ and DQb′ of the second sampler410.

As shown inFIG. 7, the error counter430decides whether the sampled data DQ and DQb, which are respectively synchronized with the recovered clock signals0and Ob at the center of the received data, are respectively identical to the sampled data DQ′ and DQb′. As described above, the sample data DQ′ and DQb′ are respectively synchronized with the phase-shifted clock signals Q′ and Qb′, which are sequentially scanned from −180° to +180° with respect to the recovered clock signals Q and Qb.

Referring toFIG. 7, when the phase-shifted clock signal Q′ has −180° phase (case (a)), or has +180° (case (d)) with respect to the recovered clock signal Q, the sampled data DQ′ and DQb′ corresponding to the phase-shifted clock signals Q′ and Ob′ may be different from the sampled data DQ and DQb corresponding to the recovered clock signals Q and Qb, respectively, since the sampled data DQ′ and DQb′ are placed within the jitter area of the received data.

When the phase-shifted clock signal Q′ is placed in the left of the recovered clock signal Q (case (b)), that is, the phase-shifted clock signal Q′ has a phase in a range between −180° and 0°, and at the same time the sampled data DQ′ and DQb′ corresponding to the phase-shifted clock signals Q′ and Qb′ are placed outside of the jitter area of the received data, the sampled data DQ and DQb corresponding to the recovered clock signals Q and Qb are respectively identical to the sampled data DQ′ and DQb′ corresponding to the phase-shifted clock signals Q′ and Qb′.

Similarly, when the phase-shifted clock signal Q′ is placed in the right of the recovered clock signal Q and Qb (case (c)), that is, the phase-shifted clock signals Q′ has a phase in a range between 0° and +180°, and at the same time the sampled data DQ′ and DQb′ corresponding to the phase-shifted clock signals Q′ and Qb′ are placed outside of the jitter area of the received data, the sampled data DQ and DQb corresponding to the recovered clock signals Q and Qb are respectively identical to the sampled data DQ′ and DQb′ corresponding to the phase-shifted clock signals Q′ and Qb′.

The sampled data DQ and DQ′ are demultiplexed by the demultiplexer431with a ratio of 1:2, then latched by the latch433to be synchronized, and then inputted to one of the XOR gates. The XOR gate outputs1when the sampled data DQ and DQ′ are identical to each other, but outputs0when the sampled data DQ and DQ′ are different from each other.

Similarly, the sampled data DQb and DQb′ are demultiplexed by the demultiplexer431with a ratio of 1:2, then latched by the latch433to be synchronized, and then inputted to the other XOR gate. The XOR gate outputs1when the sampled data DQb and DQb′ are identical to each other, but outputs0when the sampled data DQb and DQb′ are different from each other.

The 1:2 demultiplexer431is included in order to solve a possible timing limitation of the data comparison. Alternatively, a 1:4 demultiplexer as well as a 1:8 demultiplexer may be adapted for use.

FIG. 8is a timing diagram illustrating an eye size measurement of received data obtained when sequentially shifting the phase-shifted clock signals Q′ and Qb′.

Referring toFIG. 8, the recovered clock signal Q is aligned by the CDR circuit420to the very center of data P1that are provided to the first and second samplers200and410. Output data of the first sampler200are delayed, as shown in data P2, for given delay times during passing the demultiplexers431.

Data P3correspond to a case when the phase-shifted clock signal Q′ is placed at −180° phase with respect to the recovered clock signal Q, while data P4correspond to a case when the phase-shifted clock signal Qb′ is placed at −180° phase with respect to the recovered clock signal Qb′.

When the phase-shifted clock signals Q′ and Ob′ are respectively placed at the center of the recovered clock signals Q and Qb, the sampled data DQ′ and DQb′ of the second sampler410are demulitplexed with a ratio of 1:2 and simultaneously delayed for given delay times, as shown in data P5and P6inFIG. 8, which are passing through the 1:2 demultiplexers in the error counter430. After being synchronized by the latches, the sampled data DQ′ and Dab′ are synchronously outputted from the latches as data P7and P8as shown inFIG. 8.

Similarly, when the phase-shifted clock signals Q′ and Qb′ are respectively placed to the left of the recovered clock signals Q and Qb, the sampled data DQ′ and DQb′ of the second sampler410are demulitplexed with a ratio of 1:2 and simultaneously delayed for given delay times, as shown in data P9and P10, which are passing through the 1:2 demultiplexers. After being synchronized by the latches, the sampled data DQ′ and DQb′ are synchronously outputted from the latches at the same time, as shown in data P11and P12.

When the phase-shifted clock signals Q′ and Qb′ are respectively placed to the right of the recovered clock signals Q and Qb, the sampled data DQ′ and DQb′ of the second sampler410are demulitplexed with a ratio of 1:2 and simultaneously delayed for given delay times, as shown in P13and P14, which are passing through the 1:2 demultiplexers. After being synchronized by the latches, the sampled data DQ′ and DQb′ are outputted from the latches at the same time, as shown in data P15and P16ofFIG. 8.

FIG. 9is a table illustrating a relationship between the error count and the digital code for shifting a recovered clock signal.

The values of the error count inFIG. 9are obtained by summing the output of the XOR gates inFIG. 3, while the digital code405is sequentially shifted so as to sequentially shift the phase-shifted clock signals Q′ and Qb′.

For example, when the digital code is zero, for example, ‘0000’, the phases of the corresponding phase-shifted clock signals Q′ and Qb′ are respectively −180° with respect to the recovered clock signals Q and Qb, and thus the error count is 32. When the digital code is 1, e.g., ‘0001’, the phases of the corresponding phase-shifted clock signals Q′ and Qb′ are respectively −167.5° with respect to the recovered clock signals Q and Qb, and the error count is 21. When the digital code is from 3 to 12, for example, from ‘0011’ to ‘1100,’ the phases of the corresponding phase-shifted clock signals Q′ and Qb′ are respectively within a range of from −112.5° to +112.5° with respect to the recovered clock signals Q and Qb, and the error count is 0. A phase range, in which the error count is zero, indicates the eye size of the received data. In this example, the digital codes405with which all of the error counts are zero, is in the range of from 3 to 12, that is, from −112.5° to +112.5°. Hence, the phase range 225° is the eye size of the received data.

Referring back toFIG. 3, the eye size controller450is provided with the error count451from the error counter430, and it calculates the eye size of the received data signal10. Then the eye size controller450decides the equalizer control bit401for adjusting the equalizing strength of the preamplifier/equalizer100according to the calculated eye size. The eye size controller450provides the equalizer control bit401to the preamplifier/equalizer100.

FIG. 10is a table illustrating a relationship among the error count, the eye size, the equalizer control bit and the digital code for shifting the recovered clock signals.

The eye size controller450inFIG. 3provides the preamplifier/equalizer100with one of the equalizer control bits 00, 01, 10, and 11, and measures the eye sizes depending on the equalizer control bits.

Measuring the error count may be repeated as necessary, for example,50times for every one digital code, represented at the column DIGITAL CODE inFIG. 10. For example, inFIG. 10, when the equalizer control bit represented at the column EQ CONTROL BIT inFIG. 10, is 00 and the digital code is 0, the error count scores 10 out of 50 times. When the equalizer control bit is 00 and the digital code is 2, the error count scores 0 out of 50 times. The eye size may be obtained by counting the number of successive error counts having a value 0.

The eye size controller450may store the measured eye size to a register (not shown). The register may store the digital codes, the error counts, and the equalizer control bits, as well. The register may be included in the eye size controller450or in any other of the components of the system.

As shown inFIG. 10, the eye size is measured as 8 for the equalizer control bit 00, the eye size is 14 for the equalizer control bit 01, the eye size is 12 for the equalizer control bit 10, and the eye size is 6 for the equalizer control bit 11. The eye size has its largest value for the equalizer control bit 01, wherein the eye size 1 with the 4-bit digital code represents a 22.5° phase difference.

Therefore, the eye size controller450sets the equalizer control bit to ‘01’ so as to obtain the largest eye size. An adaptive equalizer may be implemented in such a way that controls the preamplifier/equalizer100to obtain the largest eye size.

Procedures for adjusting a gain of the equalizer using the equalizer control bits are described as follows with reference toFIGS. 11,12and13,.

FIG. 11is a diagram illustrating a two-stage equalizer according to an exemplary embodiment of the invention.FIG. 12is a circuit diagram illustrating a first stage of the two-stage equalizer shown inFIG. 11.FIG. 13is a graph showing adjusted gains of the equalizer inFIG. 12using the equalizer control bit. InFIG. 11, the two-stage equalizer is shown, however, an equalizer having multiple stages more than two may also be used.

Referring toFIG. 11, an equalizer130receives an equalizer control bit value EN0at a control input terminal thereof, and an equalizer132receives an equalizer control bit value EN1at its control input terminal.

Referring toFIG. 12, when the equalizer control bit value EN0is set to 0, an output of an inverter131is a logic ‘high,’ and a switch SW is turned on or closed. Consequently, an equalizing function of the equalizer is deactivated, that is, the equalizing strength is set to 0.

When the equalizer control bit value EN0is set to 1, the output of the inverter131is turned to a logic ‘low,’ and the switch SW is turned off or opened. Consequently, the equalizer130operates as an amplifier and the equalizing function, which amplifies a high-frequency input signal via a signal path including a capacitor C, is activated. Therefore, the gain of the equalizer may be adaptively adjustable and may be set to an optimal value corresponding to the equalizer control bit of the largest eye size.

Various gains of the equalizer versus frequency, which relates to eye size, are shown inFIG. 13.

FIG. 14is a block diagram illustrating a receiver of a digital data communication system according to an exemplary embodiment of the invention.

The receiver inFIG. 14generates phase-shifted clock signals Q′ and Qb′, which are obtained based on clock signal411that is shifted from the reference clock signal REFCLK through the PLL416by a given phase, instead of using the clock signals recovered by the CDR circuit420, as in the receiver inFIG. 3.

FIG. 15is a block diagram illustrating a receiver of a data communication system including a serializer-deserializer according to an exemplary embodiment of the present invention.

The CDR circuit420ofFIG. 15extracts the multiple recovered clocks signals403from the received data10based on the sampled data201from the first sampler200, instead of the deserialized data301from the deserializer300as was shown inFIG. 14.

FIG. 16is a detailed block diagram illustrating the receiver including an eye size measuring circuit as shown inFIG. 14according to exemplary embodiments of the present invention.

The receiver inFIG. 16has substantially the same configuration as the receiver shown inFIG. 3, except configuration of the eye size measuring circuit500is different from that of the eye size measuring circuit400inFIG. 3.

The eye size measuring circuit500inFIG. 16generates phase-shifted15clock signals Q′ and Qb′, which are obtained by the second PI444based on clock signal411that is shifted from the reference clock signal REFCLK through the PLL416by a given phase instead of using the digital code405from the CDR circuit420, as in the receiver shown inFIG. 3.

The second PI444receives the equalizer control bit from the eye size controller450and initiates shifting the phase-shifted clock signals whenever the equalizer control bit is changed.

The CDR circuit420may generate the recovered clock signal403from the received data10using the sampled data201of the first sampler200, as shown inFIG. 15, instead of from the sampled data301of the deserializer300.

FIGS. 17 through 20are detailed block diagrams respectively illustrating different eye size measuring circuits according to exemplary embodiments of the invention.

Eye size measuring circuits as shown inFIGS. 17 through 20have substantially the same configurations as the eye size measuring circuits shown inFIGS. 3 and 16except that the configurations of the second samplers and error counters are different from those of the second samplers and the error counters shown inFIGS. 3 and 16.

The eye size measuring circuit400ashown inFIG. 17includes a second sampler410awhich includes only one Q′ flip-flop411and the error counter430a, which scans only the phase-shifted clock signal Q′ and compares the sampled data DQ with the sampled data DQ′ to count the errors, unlike the eye size measuring circuit400inFIG. 3.

The eye size measuring circuit500ashown inFIG. 18includes a second sampler410awhich is composed of only one Q′ flip-flop411and the error counter430a, which scans only the phase-shifted clock signal Q′ compares the sampled data DQ with the sampled data DQ′ to count the errors, unlike the eye size measuring circuit500shown inFIG. 16.

The eye size measuring circuit400bshown inFIG. 19includes a second sampler410b, which is composed of only one Qb′ flip-flop413and the error counter430b, which scans only the phase-shifted clock signal Qb′ and compares the sampled data DQ with the sampled data DQ′ to count the errors, unlike the eye size measuring circuit400shown inFIG. 3.

The eye size measuring circuit500bshown inFIG. 20includes a second sampler410b, which is composed of only one Qb′ flip-flop413, and the error counter430b, which scans only the phase-shifted clock signal Qb′ and compares the sampled data DQ with the sampled data DQ′ to count the errors, unlike the eye size measuring circuit500shown inFIG. 16.

The eye size measuring circuits according to the exemplary embodiments of the present invention may be adapted to a receiver of a data communication system including a sampler and a CDR circuit. For example, the eye size measuring circuits according to the exemplary embodiments of the present invention may be adapted to a receiver of a data communication system including a serializer-deserializer.

The eye size measuring circuits according to the exemplary embodiments of the present invention, however, are not limited to a receiver of a data communication system including a serializer-deserializer. The eye size measuring circuits according to the exemplary embodiments of the present invention may be adapted to a receiver of a data communication system including a sampler and a CDR circuit, even though the receiver does not include a serializer and/or a deserializer.

According to the exemplary embodiments of the present invention, the eye size measuring circuits, the receivers of data communication systems, and the methods of measuring the eye size generate first sampled data by performing a first sampling of received data by recovered clock signals that are recovered from the received data by the CDR circuit and generate second sampled data by performing a second sampling of the received data by using phase-shifted clock signals, which are shifted from the recovered clock signals by given phases. Error counting is repeatedly performing a comparison of the first and second sampled data and the eye size is measured by obtaining a phase range where the error count is 0. Therefore, the eye size may be measured without adverse influences of frequency offsets and/or jitter of the received data signal.

Furthermore, an adaptive equalizing may be achieved by adjusting an equalizing strength of the equalizer based on equalizer control bits at the time when the measured eye size is maximized.