Dividing work among multiple graphics pipelines using a super-tiling technique

A graphics processing circuit includes at least two pipelines operative to process data in a corresponding set of tiles of a repeating tile pattern, a respective one of the at least two pipelines operative to process data in a dedicated tile, wherein the repeating tile pattern includes a horizontally and vertically repeating pattern of square regions. A graphics processing method includes receiving vertex data for a primitive to be rendered; generating pixel data in response to the vertex data; determining the pixels within a set of tiles of a repeating tile pattern to be processed by a corresponding one of at least two graphics pipelines in response to the pixel data, the repeating tile pattern including a horizontally and vertically repeating pattern of square regions; and performing pixel operations on the pixels within the determined set of tiles by the corresponding one of the at least two graphics pipelines.

FIELD OF THE INVENTION

The present invention generally relates to graphics processing circuitry and, more particularly, to dividing graphics processing operations among multiple pipelines.

BACKGROUND OF THE INVENTION

Computer graphics systems, set top box systems or other graphics processing systems typically include a host processor, graphics (including video) processing circuitry, memory (e.g. frame buffer), and one or more display devices. The host processor may have a graphics application running thereon, which provides vertex data for a primitive (e.g. triangle) to be rendered on the one or more display devices to the graphics processing circuitry. The display device, for example, a CRT display includes a plurality of scan lines comprised of a series of pixels. When appearance attributes (e.g. color, brightness, texture) are applied to the pixels, an object or scene is presented on the display device. The graphics processing circuitry receives the vertex data and generates pixel data including the appearance attributes which may be presented on the display device according to a particular protocol. The pixel data is typically stored in the frame buffer in a manner that corresponds to the pixels location on the display device.

FIG. 1illustrates a conventional display device10, having a screen12partitioned into a series of vertical strips13-18. The strips13-18are typically 1-4 pixels in width. In like manner, the frame buffer of conventional graphics processing systems is partitioned into a series of vertical strips having the same screen space width. Alternatively, the frame buffer and the display device may be partitioned into a series of horizontal strips. Graphics calculations, for example, lighting, color, texture and user viewing information are performed by the graphics processing circuitry on each of the primitives provided by the host. Once all calculations have been performed on the primitives, the pixel data representing the object to be displayed is written into the frame buffer. Once the graphics calculations have been repeated for all primitives associated with a specific frame, the data stored in the frame buffer is rendered to create a video signal that is provided to the display device.

The amount of time taken for an entire frame of information to be calculated and provided to the frame buffer becomes a bottleneck in graphics systems as the calculations associated with the graphics become more complicated. Contributing to the increased complexity of the graphics calculation is the increased need for higher resolution video, as well as the need for more complicated video, such as 3-D video. The video image observed by the human eye becomes distorted or choppy when the amount of time taken to render an entire frame of video exceeds the amount of time in which the display device must be refreshed with a new graphic or frame in order to avoid perception by the human eye. To decrease processing time, graphics processing systems typically divide primitive processing among several graphics processing circuits where, for example, one graphics processing circuit is responsible for one vertical strip (e.g.13) of the frame while another graphics processing circuit is responsible for another vertical strip (e.g.14) of the frame. In this manner, the pixel data is provided to the frame buffer within the required refresh time.

Load balancing is a significant drawback associated with the partitioning systems as described above. Load balancing problems occur, for example, when all of the primitives20-23of a particular object or scene are located in one strip (e.g. strip13) as illustrated inFIG. 1. When this occurs, only the graphics processing circuit responsible strip13is actively processing primitives; the remaining graphics processing circuits are idle. This results in a significant waste of computing resources as at most only half of the graphics processing circuits are operating. Consequently, graphics processing system performance is decreased as the system is only operating at a maximum of fifty percent capacity.

Changing the width of the strips has been employed to counter the system performance problems. However, when the width of a strip is increased, the load balancing problem is enhanced as more primitives are located within a single strip; thereby, increasing the processing required of the graphics processing circuit responsible for that strip, while the remaining graphics processing circuits remain idle. When the width of the strip is decreased (e.g. four bits to two bits), cache (e.g. texture cache) efficiency is decreased as the number of cache lines employed in transferring data is reduced in proportion to the decreased width of the strip. In either case, graphics processing system performance is still decreased due to the idle graphics processing circuits.

Frame based subdivision has been used to overcome the performance problems associated with conventional partitioning systems. In frame based subdivision, each graphics processor is responsible for processing an entire frame, not strips within the same frame. The graphics processors then alternate frames. However, frame subdivision introduces one or more frames of latency between the user and the screen, which is unacceptable in real-time interactive environments, for example, providing graphics for a flight simulator application.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

A multi-pipeline graphics processing circuit includes at least two pipelines operative to process data in a corresponding tile of a repeating tile pattern, a respective one of the at least two pipelines is operative to process data in a dedicated tile, wherein the repeating tile pattern includes a horizontally and vertically repeating pattern of square regions. The multi-pipeline graphics processing circuit may be coupled to a frame buffer that is subdivided into a replicating pattern of square regions (e.g. tiles), where each region is processed by a corresponding one of the at least two pipelines such that load balancing and texture cache utilization is enhanced.

A multi-pipeline graphics processing method includes receiving vertex data for a primitive to be rendered, generating pixel data in response to the vertex data, determining the pixels within a set of tiles of a repeating tile pattern to be processed by a corresponding one of at least two graphics pipelines in response to the pixel data, the repeating tile pattern including a horizontally and vertically repeating pattern of square regions, and performing pixel operations on the pixels within the determined set of tiles by the corresponding one of the at least two graphics pipelines. An exemplary embodiment of the present invention will now be described with reference toFIGS. 2-6.

FIG. 2is a schematic block diagram of an exemplary graphics processing system30employing an example of a multi-pipeline graphics processing circuit34according to one embodiment of the present invention. The graphics processing system30can be implemented with a single graphics processing circuit34or with two or more graphics processing circuits34,54. The components and corresponding functionality of the graphics processing circuits34,54are substantially the same. Therefore, only the structure and operation of graphics processing circuit34will be described in detail. An alternate embodiment, employing both graphics processing circuits34and54will be discussed in greater detail below with reference toFIGS. 4-5.

Graphics data31, for example, vertex data of a primitive (e.g. triangle)80(FIG. 3) is transmitted as a series of strips to the graphics processing circuit34. As used herein, graphics data31can also include video data or a combination of video data and graphics data. The graphics processing circuit34is preferably a portion of a stand-alone graphics processor chip or may also be integrated with a host processor or other circuit, if desired, or part of a larger system. The graphics data31is provided by a host (not shown). The host may be a system processor (not shown) or a graphics application running on the system processor. In an alternate embodiment, an Accelerated Graphics Port (AGP)32or other suitable port receives the graphics data31from the host and provides the graphics data31to the graphics processing circuit34for further processing.

The graphics processing circuit34includes a first graphics pipeline101operative to process graphics data in a first set of tiles as discussed in greater detail below. The first pipeline101includes front end circuitry35, a scan converter37, and back end circuitry39. The graphics processing circuit34also includes a second graphics pipeline102, operative to process graphics data in a second set of tiles as discussed in greater detail below. The first graphics pipeline101and the second graphics pipeline102operate independently of one another. The second graphics pipeline102includes the front end circuitry35, a scan converter40, and back end circuitry42. Thus, the graphics processing circuit34of the present invention is configured as a multi-pipeline circuit, where the back end circuitry39of the first graphics pipeline101and the back end circuitry42of the second graphics pipeline102share the front end circuitry35, in that the first and second graphics pipelines101and102receive the same pixel data36provided by the front end circuitry35. Alternatively, the back end circuitry39of the first graphics pipeline101and the back end circuitry42of the second pipeline102may be coupled to separate front end circuits. Additionally, it will be appreciated that a single graphics processing circuit can be configured in similar fashion to include more than two graphics pipelines. The illustrated graphics processing circuit34has the first and second pipelines101-102present on the same chip. However, in alternate embodiments, the first and second graphics pipelines101-102may be present on multiple chips interconnected by suitable communication circuitry or a communication path, for example, a synchronization signal or data bus interconnecting the respective memory controllers.

The front end circuitry35may include, for example, a vertex shader, set up circuitry, rasterizer or other suitable circuitry operative to receive the primitive data31and generate pixel data36to be further processed by the back end circuitry39and42, respectively. The front end circuitry35generates the pixel data36by performing, for example, clipping, lighting, spatial transformations, matrix operations and rasterizing operations on the primitive data31. The pixel data36is then transmitted to the respective scan converters37and40of the two graphics pipelines101-102.

The scan converter37of the first graphics pipeline101receives the pixel data36and sequentially provides the position (e.g. x, y) coordinates60in screen space of the pixels to be processed by the back end circuitry39by determining or identifying those pixels of the primitive, for example, the pixels within portions81-82of the triangle80(FIG. 3) that intersect the tile or set of tiles that the back end circuitry39is responsible for processing. The particular tile(s) that the back end circuitry39is responsible for is determined based on the tile identification data present on the pixel identification line38of the scan converter37. The pixel identification line38is illustrated as being hard wired to ground. Thus, the tile identification data corresponds to a logical zero. This corresponds to the back end circuitry39being responsible for processing the tiles labeled “A” (e.g.72and75) inFIG. 3. Although the pixel identification line38is illustrated as being hard wired to a fixed value, it is to be understood and appreciated that the tile identification data can be programmable data, for example, from a suitable driver and such a configuration is contemplated by the present invention and is within the spirit and scope of the instant disclosure.

Back end circuitry39may include, for example, pixel shaders, blending circuits, z-buffers or any other circuitry for performing pixel appearance attribute operations (e.g. color, texture blending, z-buffering) on those pixels located, for example, in tiles72,75(FIG. 3) corresponding to the position coordinates60provided by the scan converter37. The processed pixel data43is then transmitted to graphics memory48via memory controller46for storage therein at locations corresponding to the position coordinates60.

The scan converter40of the second graphics pipeline102, receives the pixel data36and sequentially provides position (e.g. x, y) coordinates61in screen space of the pixels to be processed by the back end circuitry42by determining those pixels of the primitive, for example, the pixels within portions83-84of the triangle80(FIG. 3) that intersect the tiles that the back end circuitry42is responsible for processing. Back end circuitry42tile responsibility is determined based on the tile identification data present on the pixel identification line41of the scan converter41. The pixel identification line41is illustrated as being hard wired to VCC; thus, the tile identification data corresponds to a logical one. This corresponds to the back end circuitry42being responsible for processing the tiles labeled “B” (e.g.73-74) inFIG. 3. Although the pixel identification line41is illustrated as being hard wired to a fixed value, it is to be understood and appreciated that the tile identification data can be programmable data, for example, from a suitable driver and such configuration is contemplated by the present invention and is within the spirit and scope of the instant disclosure.

Back end circuitry42may include, for example, pixel shaders, blending circuits, z-buffers or any suitable circuitry for performing pixel appearance attribute operations on those pixels located, for example, in tiles73and74(FIG. 3) corresponding to the position coordinates61provided by the scan converter40. The processed pixel data44is then transmitted to the graphics memory48, via memory controller46, for storage therein at locations corresponding to the position coordinates61.

The memory controller46is operative to transmit and receive the processed pixel data43-44from the back end circuitry39and42; transmit and retrieve pixel data49from the graphics memory48; and in a single circuit implementation, transmit pixel data50for presentation on a suitable display51. The display51may be a monitor, a CRT, a high definition television (HDTV) or any other device or combination thereof.

Graphics memory48may include, for example, a frame buffer that also stores one or more texture maps. Referring toFIG. 3, the frame buffer portion of the graphics memory48is partitioned in a repeating tile pattern of horizontal and vertical square regions or tiles72-75, where the regions72-75provide a two dimensional partitioning of the frame buffer portion of the memory48. Each tile is implemented as a 16×16 pixel array. The repeating tile pattern of the frame buffer48corresponds to the partitioning of the corresponding display51(FIG. 2). When rendering a primitive (e.g. triangle)80, the first graphics pipeline101processes only those pixels in portions81,82of the primitive80that intersects tiles labeled “A”, for example,72and75, as the back end circuitry39is responsible for the processing of tiles corresponding to tile identification0present on pixel identification line38(FIG. 2). In corresponding fashion, the second graphics pipeline102processes only those pixels in portions83,84of the primitive80that intersects tiles labeled “B”, for example73-74, as the back end circuitry42(FIG. 2) is responsible for the processing of tiles corresponding to tile identification1present on pixel identification line41(FIG. 2).

By configuring the frame buffer48according to the present invention, as the primitive data31is typically written in strips, the tiles (e.g.72and75) being processed by the first graphics pipeline101and the tiles (e.g.73and74) being processed by the second graphics pipeline102will be substantially equal in size, notwithstanding the primitive80orientation. Thus, the amount of processing performed by the first graphics pipeline101and the second graphics pipeline102, respectively, are substantially equal; thereby, effectively eliminating the load balance problems exhibited by conventional techniques.

FIG. 4is a schematic block diagram of a frame buffer68partitioned into a super-tile pattern according to an alternate embodiment of the present invention. Such a partitioning would be used, for example, in conjunction with a multi-processor implementation to be discussed below with reference toFIG. 5. As illustrated, the frame buffer68is partitioned into a repeating tile pattern where the tiles, for example,92-99that form the repeating tile pattern are the responsibility of and processed by a corresponding one of the graphics pipelines provided by the multi-processor implementation.

FIG. 5is a schematic block diagram of a graphics processing circuit54which may be coupled with the graphics processing circuit34(FIG. 2), for example, by the AGP32or other suitable port, to form one embodiment of a multi-processor implementation. The graphics processing circuit54is preferably a portion of a stand-alone graphics processor chip or may also be integrated with a host processor or other circuit, if desired, or port of a larger system. The multi-processor implementation exhibits an increased fill rate of, for example, 9.6 billion pixels/sec with a triangle rate of 300 million triangles/sec. This represents a tremendous performance increase as compared to conventional graphics processing systems. The triangle rate is defined as the number of triangles the graphics processing circuit can generate per second. The fill rate is defined as the number of pixels the graphics processing circuit can render per second.

Referring briefly toFIG. 2, in the multi-processor implementation, processed pixel data52from the graphics processing circuit34is provided as a first of two inputs to a high speed switch70. The second input to the high speed switch70is the processed pixel data55from the graphics processing circuit54. The high speed switch70has a switching frequency (f) sufficient to provide the pixel information71to a suitable display device without any detectable latency.

Returning toFIG. 5, the graphics processing circuit54includes a third graphics pipeline201operative to process graphics data in a third set of tiles. The third graphics pipeline201includes front end circuitry135, which may be the front end circuitry35discussed with reference toFIG. 2, a scan converter137and back end circuitry139. The graphics processing circuit54also includes a fourth graphics pipeline202, operative to process graphics data in a fourth set of tiles. The fourth graphics pipeline202includes the front end circuitry135, a scan converter140and back end circuitry142. The third graphics pipeline201and the fourth graphics pipeline202also operate independently of one another. Thus, the graphics processing circuit54is configured as a multi-pipeline circuit, where the back end circuitry139of the third graphics pipeline201and the back end circuitry142of the fourth graphics pipeline202share the front end circuitry135, in that the respective back end circuitry139and142receives the same pixel data from the front end circuitry135. As illustrated, the components of the third and fourth graphics pipelines are present on a single chip. Additionally, the back end circuitry139and the back end circuitry142may be configured to share the front end circuitry35of the graphics processing circuit34. Alternatively, the third and fourth graphics pipelines may be configured to be on multiple chips interconnected by a communication path, for example, a synchronization signal or data bus.

The front end circuitry135may include, for example, a vertex shader, set up circuitry, rasterizer or other suitable circuitry operative to receive the primitive data31from the AGP32and generate pixel data136to be processed by the third graphics pipeline201and fourth graphics pipeline202, respectively. The front end circuitry135generates the pixel data136by performing, for example, clipping, lighting, spatial transformations, matrix operations, rasterization or any suitable primitive operations or combination thereof on the primitive data31. The pixel data136is then transmitted to the respective scan converters137and140of the two graphics pipelines201-202.

The scan converter137of the third graphics pipeline201receives the pixel data136and sequentially provides the position (e.g. x, y) coordinates160in screen space of the pixels to be processed by the back end circuitry139, based on the tile identification data present on pixel identification line138. In corresponding fashion, scan converter140of the fourth graphics pipeline202receives the pixel data136and sequentially provides the position (e.g. x, y) coordinates161in screen space of the pixels to be processed by the back end circuitry143, based on the tile identification data present on pixel identification line141.

Referring toFIG. 4, in the multi-processor implementation, when a logical zero or other suitable value is present on pixel identification line138(e.g. corresponding to the pixel identification line138being tied to ground), the back end circuitry139is responsible for processing, for example, tiles labeled “A0” (e.g.92and95). In corresponding manner, when a logical one or other suitable value is present on pixel identification line141(e.g. corresponding to pixel identification line142being tied to VCC), the back end circuitry142will be responsible for processing the tiles labeled “B0” (e.g.93and94). When a logical zero or other suitable value is present on pixel identification line38(FIG. 2), the back end circuitry39is responsible for processing, for example, the tiles labeled “A1” (e.g.96and99). When a logical one or other suitable value is present on pixel identification line41(FIG. 2), the back end circuitry42is responsible for processing, for example, the tiles labeled “B1” (e.g.97and98). The tile pattern illustrated inFIG. 4is referred to as a super-tile pattern68.

As illustrated, the super-tile pattern68is formed of a horizontally and vertically repeating pattern of regions or tiles92-99, where each tile is a 16×16 pixel array. With this frame buffer configuration, as the primitive data31is typically written in strips, at least one tile (e.g.92) being processed by the third graphics pipeline201and at least one tile (e.g.93) being processed by the fourth graphics pipeline202will be intersected or contain at least a portion of the primitive data31, notwithstanding the primitive orientation; thereby achieving substantially equal load balancing between the pipelines.

Thus, in the multi-processor implementation, each of the graphics pipelines is responsible for processing 1/(M×N) of the tiles present in the partitioned graphics memory68, where M represents the number of pipelines per circuit and N represents the number of graphics processing circuits being used. Thus, in an embodiment where graphics processing circuit34and graphics processing circuit54are combined, for example, through AGP32(FIG. 2), each graphics pipeline101,102,201and202will be responsible for processing one-fourth of the tiles92-99of the repeating tile pattern. This results in increased graphics processing performance as each graphics pipeline is responsible for processing one-quarter of total pixels maintained in the frame buffer68.

FIG. 6is a flow chart of the operations performed by the graphics processing circuit34according to the present invention. In the multi-processor implementation, graphics processing circuits34and54perform substantially the same operations. In step100, the front end circuitry35receives the graphics data31(FIG. 2), for example, vertex data of an object to be rendered and generates corresponding pixel data36(FIG. 2) in response to the primitive data31in step102. The pixel data may be generated by performing, for example, clipping, lighting, spatial transformations. matrix transformations and rasterizing operations on the graphics data31.

In step104, the pixels within a set of tiles of the repeating tile pattern to be processed by a corresponding one of the at least two graphics pipelines in response to the pixel data is determined. This is accomplished, for example, in step105by the scan converter37determining which of tiles (e.g.72and75) of the repeating tile pattern are to be processed by the back end circuitry39based on the tile identification data present on the pixel identification line38. Next, in step106, the scan converter37provides the position coordinates60of the pixels within portions81-82of the triangle80that intersect the tiles (e.g.72and75) to the back end circuitry39.

In step108, pixel operations are performed on the pixels within the determined set of tiles by the corresponding one of the at least two graphics pipelines is performed. This is accomplished, for example, by the back end circuitry39performing color, shading, blending, texturing and/or z-buffering operations on the pixels within the portions (e.g.81-82) of the tiles (e.g.72and75) they are responsible for.

In step109, a determination is made as to whether the processing is complete. If the processing is complete, the process proceeds to step100where vertex data for a new primitive is received. Otherwise, the process ends. In the multi-processor implementation, graphics processing circuit54performs substantially the same operations as discussed above, in conjunction with graphics processing circuit34.

As noted above, a rasterizer setup unit manages the distribution of polygons to the different rasterizer pipelines within a chip. The design divides the screen into multiple square tiles. Each pipeline is responsible for a subset of the tiles. In our design, the tile sizes are 8×8 pixels, 16×16 pixels (default) or 32×32 pixels. However, any number of square pixels or even non-square tiles could be done. It will be recognized that the number of pixels in the tiles be a common divisor of the number of pixels on the screen, in both X and Y directions.

Vertices are given by the application currently executing on the host. The vertices are converted from object space three-dimensional homogeneous coordinate system to a screen based coordinate system. This conversion can be done on the host processor or in the front end section of the graphics chip (i.e. vertex transformation). The screen based coordinate system has at least X and Y coordinates for each vertex.

As shown inFIG. 7, the setup unit creates a bounding box based on the screen space X, Y coordinates of each vertex. This bounding box is then compared against the current tile pattern. This tiling pattern is based on the number of graphics pipelines currently active. In the one pipe configuration, the tiles just repeat and are all mapped to the same pipeline. In the two pipe configuration, a “checkerboard” pattern is created for the pipes and the patterns repeat over the full screen.

The bounding boxes' four corners are mapped to the tile pattern, simply by discarding the lower bits of X & Y. The four corners map to the same or different tiles. If they all map to the same tile, then only the pipeline that is associated with that tile receives the polygon. If it maps to only tiles that are associated with only one pipeline, then again only that pipeline receives the polygon. If it maps to tiles that are associated with multiple pipelines, then the entire polygon is sent to all pipelines. In one implementation, the polygon is broadcast to all pipelines, masking the pipelines that should not receive it. Consequently, polygons can be sent to only one pipe or up to all the pipes, depending on the coverage of the tiles by the polygon.

For super tiling when using multiple graphics chips, the rasterizer setup unit manages the distribution of polygons to different graphics chips. The super tiles, which are a square assembly of pixels, are used to perform load balancing between each processor. Basically, each processor is responsible for generating all of the pixels in its subset of super tiles. The tiles are distributed evenly across all processors, in a checkerboard pattern. The tile size is variable, but one implementation may be 32×32 pixels, or 2×2 tiles. This amount can be changed through programming registers. Super tiles do not have to be of a size which is a common divisor of the screen resolution, but it's more efficient if it is. The number of chips in use should be a power of two.

FIG. 8shows some examples of super tile configurations for various numbers of chips (super tile size or STS). As shown, C# represents the tile that chip # controls. The patterns repeat across the whole screen, in both X & Y directions, until the full screen is fully covered. For odd powers of 2 (STS=2, STS=8), a simple square pattern of different chips cannot be made, so a secondary pattern of checkerboard is applied to generate a square arrangement.

In operation, an application generates vertex data, which assembles into polygons (i.e. 2 vertices for a line, 3 for a triangle). Each vertex's homogeneous object space coordinate (generated by the application) is transformed into screen space coordinates by either the host or the front end of the graphics chip (transform unit or vertex processor). The screen space coordinates hold X, Y coordinates (in screen pixels) for each of the vertices. The polygons coming from an application are all broadcast to all chips. Each chip processes the vertices as needed to generate the same X, Y coordinates for all vertices. Then, each chip creates a bounding box around the polygon as shown inFIG. 7. The X, Y coordinates of each corner of the bounding box is checked against the super tiles that belongs to each processor. If the bounding box overlaps a super tile assigned to a given processor, then that processor must render some or the entire polygon. The setup unit then sends the whole polygon to the various raster pipe(s). If the bounding box does not overlap any of the tiles associated with a processor, then the setup unit rejects the whole polygon and processes the next one.

In this way, triangle setup performance does not scale with each processor (since all polygons go through all setup units), but fill rate (defined as the number of pixels output total) does scale with each processor added.

The above detailed description of the invention and the examples described therein have been provided for the purposes of illustration and description. Although an exemplary embodiment of the present invention has been described in detail herein with reference to the accompanying drawings, it is to be understood that the present invention is not limited to the precise embodiment disclosed, and that various changes and modifications to the invention are possible in light of the above teaching. Accordingly, the scope of the present invention is to be defined by the claims appended hereto.