Frequency hopping for a capacitive touch screen controller

A circuit includes a force driver configured to apply a force signal to a force node associated with a mutual capacitance to be sensed. A sensing circuit receives a sense signal from a sense node associated with said mutual capacitance to be sensed. The sensing circuit operates to generate an output signal indicative of the sensed mutual capacitance. A control circuit controls generation of the force signal to alternate between at least two different frequencies and generate said output signal for each half cycle of the force signal.

TECHNICAL FIELD

The present disclosure generally relates to a capacitive touch screen controllers and, more particularly, to a frequency hopping technique for use in driving and sampling the mutual capacitance.

BACKGROUND

A touch screen is a device that can detect an object in contact with or in proximity to a display area. The display area can be covered with a touch-sensitive matrix that can detect a user's touch by way of a finger or stylus, for example. Touch screens are used in various applications such as mobile phones and other mobile devices. A touch screen may enable various types of user input, such as touch selection of items on the screen or alphanumeric input via a displayed virtual keypad. Touch screens can measure various parameters of the user's touch, such as the location, duration, etc.

One type of touch screen is a capacitive touch screen. A capacitive touch screen may include a matrix of conductive rows and columns overlaid on the display area. In mutual capacitance sensors, the mutual capacitance at the intersection of each row and column of the matrix may be sensed. A change in mutual capacitance between a row and a column may indicate that an object, such as a finger, is touching the screen or is in proximity to the screen near the region of intersection of the row and column.

Mutual capacitance sensing circuits employ a “forcing” signal that is applied to a column conductor of the capacitive touch matrix. A sensing of the coupled signal on respective row conductors is made to detect change in the mutual capacitance. Since the capacitance change caused by a finger is small, noise reduction is important in achieving satisfactory operation. One known source of noise is external noise injected from the environment. In order to achieve a high signal-to-noise ratio (SNR), this source of noise must be taken into account. The power of such external noise sources is often concentrated in a few harmonics.

One known architecture uses a capacitance-to-voltage converter followed by an accumulator and an analog-to-digital converter. During each cycle of operation, a forcing signal having a scanning frequency is applied to the capacitance (at the intersection of a row and column) to be sensed, and charge stored in the capacitance is converted to voltage by the capacitance-to-voltage converter. The voltage is accumulated in the accumulator and converted by the analog-to-digital converter to a digital value indicative of the sensed capacitance. If the scanning frequency is close to any of the noise harmonics, a large amount of noise may be introduced in the sensing operation.

In order to filter the external noise, it is known in the art to implement a frequency hopping technique which changes the scanning frequency and, more particularly, moves the scanning frequency away from the noise harmonics. The number of scanning frequencies available for frequency hopping, and their particular frequency locations, may be limited. In some cases, it is possible that all available scanning frequencies that could be selected by frequency hopping are near noise harmonics. In such a case, noise rejection is not satisfactorily achieved.

A need accordingly exists in the art for an improved frequency hopping technique that supports finer resolution selection of the scanning frequency.

SUMMARY

In an embodiment, a circuit comprises: a force driver configured to apply a force signal to a force node associated with a mutual capacitance to be sensed; a charge to voltage converter having an input coupled to receive a sense signal from a sense node associated with said mutual capacitance to be sensed, said charge to voltage converter comprising: an integrator circuit configured to integrate said sense signal; an input switch coupled between the input of the charge to voltage converter and an input of the integrator circuit; and a reset switch coupled between an output of the integrator circuit and said input of the integrator circuit; and a control circuit configured to control generation of the force signal to alternate between at least two different frequencies and generate, for each half cycle of the force signal, a first control signal for closing the input switch and a second control signal for closing the reset switch.

In an embodiment, a method comprises: applying a force signal to a force node associated with a mutual capacitance to be sensed; integrating a sense signal output from a sense node associated with said mutual capacitance to be sensed; wherein apply the force signal comprises controlling generation of the force signal to alternate between at least two different frequencies; and wherein integrating the sense signal comprises performing integration and resetting the integration within each half cycle of the force signal.

In an embodiment, a circuit comprises: a force driver configured to apply a force signal to a force node associated with a mutual capacitance to be sensed; a sensing circuit having an input coupled to receive a sense signal from a sense node associated with said mutual capacitance to be sensed, said sensing circuit configured to generate an output signal indicative of the sensed mutual capacitance; and a control circuit configured to control generation of the force signal to alternate between at least two different frequencies and generate said output signal for each half cycle of the force signal.

DETAILED DESCRIPTION

The same elements have been designated with the same reference numerals in the different drawings. In particular, the structural and/or functional elements common to the different embodiments may be designated with the same reference numerals and may have identical structural, dimensional, and material properties. For clarity, only those steps and elements which are useful to the understanding of the described embodiments have been shown and will be detailed. In particular, the circuits powered by the power converter have not been detailed, the described embodiments being compatible with usual applications. In the following description, when reference is made to terms “about”, “approximately”, or “in the order of”, this means to within 10%, preferably to within 5%.

Reference is now made toFIG. 1showing a portion of a capacitive touch matrix10comprising a plurality of conductive rows12and plurality of conductive columns14. Each row12and column14is formed by a plurality of serially connected diamond shaped regions16forming a conductive line or trace. The conductive rows12and the conductive columns14cross above or below each other at intersection points, but are not in electrical contact with one another. Because of the diamond pattern, the conductive rows12and the conductive columns14are separated from each other by capacitive gaps18. The diamond pattern may provide decreased capacitance between conductive rows12and conductive columns14. Capacitive touch matrix10may sense an object that modifies the fringing electric field above the capacitive gaps18when the object is in contact or in proximity to the matrix10.

FIG. 2shows that when a conductive row12and a conductive column14are selected, the total capacitance of a capacitor (reference70,FIG. 4) between row and column conductors is the sum of four capacitances20between the four adjacent diamond-shaped regions16of the selected row and column. The mutual capacitance of the capacitor between the selected row12and column14conductors can be sensed to determine whether an object is in contact with or in proximity to the matrix10above the region in which the four capacitances20are formed. Each conductive row12and conductive column14of the capacitive touch matrix10may be selected in succession to sense the capacitances at each intersection position of the touch matrix.

FIG. 3is a block diagram of a touch screen system40that includes the capacitive touch matrix10and an associated touch screen controller42. As discussed above, the capacitive touch matrix10may utilize diamond shaped regions for the row and column conductors. Such structures are not shown inFIG. 3for reasons of clarity. Instead, the conductive rows (R1-Rm)12and conductive columns (C1-Cn)14are more simply illustrated as intersecting conductor line segments. The touch screen controller42includes a row switch matrix44and a column switch matrix46for selection of rows and columns of the capacitive touch matrix, such selection being made to select a particular mutual capacitance within the matrix10for sensing. The column switch matrix46receives a force signal generated by a force driver48and selectively applies the force signal in a sequential manner to each of the columns14. The row switch matrix44sequentially selects one or more of the rows12for connection to a capacitance-to-digital converter circuit50that operates to sense charge of the mutual capacitance for the capacitors in the capacitive touch matrix10and convert that sensed charge to a digital value for output.

Reference is now made toFIG. 4showing details of the touch screen controller42. For simplification of the illustration, details of the row switch matrix44and column switch matrix46for selecting a particular capacitor70in the matrix10at a selected row12sand selected column14sare omitted. The force driver48receives a transmit signal TX and applies the force signal72to a force node74associated with the column14sof the selected capacitor70. The transmit signal TX is an alternating current (AC) signal having an adjustable frequency fadj. In an embodiment, the transmit signal TX is a square wave signal. The force signal72is accordingly also an AC signal, with a corresponding frequency fadj, that is coupled through the selected capacitor to generate a sense signal78output from a sense node80associated with the row12sof the selected capacitor70.

A charge to voltage (C2V) converter circuit84includes an integrator circuit86. The integrator circuit86is formed by an operational amplifier88having a first input90, a second input92and an output94and further includes an integrating capacitor96coupled between the output94and the first input90. A reference voltage (Vref) is applied to the second input92of the operational amplifier. An input switch100is coupled between the sense node80and the first input90of the operational amplifier. Opening and closing of the input switch100is controlled by a first control signal PHI_T. A reset switch102is coupled between the output94and the first input90in parallel with the integrating capacitor96. Opening and closing of the reset switch102is controlled by a second control signal PHI_R. The switches100and102may, for example, be implemented as transistor devices such as MOSFETs.

The C2V converter circuit84integrates charge from the sense signal78output from the sense node80when the first control signal PHI_T transitions to a first logic state configured to close the input switch100. The C2V converter circuit84and generates a voltage at output94whose offset from the reference voltage Vref is indicative of the sensed mutual capacitance at capacitor70. The first control signal PHI_T then transitions to a second logic state configured to open the input switch100and disconnect the C2V converter circuit84from the sense node80. At this point in time, and the second control signal PHI_R transitions to a first logic state configured to close the reset switch102and short across the integrating capacitor96. This results in a resetting of the C2V converter circuit84that drives the voltage at the output94to equal the reference voltage Vref.

The touch screen controller42further includes an analog accumulator (E) circuit110having an input coupled to the output94of the operational amplifier by a switch112. Opening and closing of the switch112is controlled by a third control signal PHI_ACC. The analog accumulator circuit110receives the voltage generated at output94each time the third control signal PHI_ACC transitions to a first logic state configured to close the switch112. The third control signal PHI_ACC is timed to close the switch112just before a time when the second control signal PHI_R closes the reset switch102. Thus, the analog accumulator circuit110receives the integrated voltage that is indicative of the sensed mutual capacitance at capacitor70. The voltages output from the C2V converter circuit84are accumulated by the analog accumulator circuit110over a plurality of accumulation cycles which define a sensing period. Because the C2V converter circuit84integrates on both the positive phase and negative phase of each cycle of the transmit signal TX, the analog accumulator circuit110includes both a positive (+) and negative (−) input in order to be able to accumulate properly for both phases. After the voltage has been received for accumulation, the third control signal PHI_ACC transitions to a second logic state configured to open the switch112.

The touch screen controller42still further includes an analog to digital (A/D) converter circuit120having an input coupled to an output of the analog accumulator circuit110by a sample switch122. Opening and closing of the sample switch122is controlled by a fourth control signal PHI_ADC. The A/D converter circuit120samples the accumulated voltage output from the analog accumulator circuit110each time the fourth control signal PHI_ADC transitions to a first logic state configured to close the switch122. The fourth control signal PHI_ADC is timed to close the switch122at the end of the plurality of accumulation cycles which define the sensing period. The A/D converter circuit120then converts the sampled accumulated voltage and generates a corresponding digital signal124. Once the sampling of the accumulated voltage output is completed, the fourth control signal PHI_ADC transitions to a second logic state configured to open the switch122.

A digital circuit block130is configured to generate the first control signal PHI_T, second control signal PHI_R, third control signal PHI_ACC and fourth control signal PHI_ADC with the appropriate logic states and timings in order to effectuate the operations described above. The digital circuit block130may comprise a logic circuit. The digital circuit block130may, more specifically, comprise a logic circuit, programmable logic, a microcontroller or a microprocessor circuit appropriately designed or programmed to generate the control signals. The digital circuit block130is further configured to generate the transmit signal TX, and the timing of the first control signal PHI_T, second control signal PHI_R, third control signal PHI_ACC and fourth control signal PHI_ADC are dependent on the transmit signal TX.

To address concerns with external noise, the digital circuit block130generates the transmit signal TX as an alternating current (AC) signal having an adjustable frequency fadj that supports frequency hopping. By this it is meant that the digital circuit block130can generate the transmit signal TX to have two or more discrete frequencies. The digital circuit block130receives a system clock CLK having a fixed frequency fclk. The frequency fadj for the transmit signal TX is an integer fraction of the frequency fclk; for example, fadj=fclk/N, where N is an integer value. Because of this relationship, the capability to frequency hop the transmit signal TX is limited to frequencies set by the integer values of N; so, for example, fadj1=fclk/N and fadj2=fclk/(N+1) are two possible frequencies for frequency hopping selection.

FIG. 5Ashows the timing relationship between the transmit signal TX, the first control signal PHI_T and the second control signal PHI_R if the digital circuit block130selects the frequency fadj1 (with a period T=1/fadj1).FIG. 5Bshows the timing relationship between the transmit signal TX, the first control signal PHI_T and the second control signal PHI_R if the digital circuit block130selects the frequency fadj2 (with a period T=1/fadj2). A sensing period130includes a plurality of cycles of the transmit signal TX (in this illustration, three such cycles, this being understood to be an example only).FIGS. 5Aand5B further show the timing relationships for the third control signal PHI_ACC and fourth control signal PHI_ADC.

The resolution of the frequency hopping capabilities is restricted by the integer values of N. A possibility exists, due to the harmonics associated with the external noise, that no value of N will satisfactorily produce an adjustable frequency fadj for the transmit signal TX that supports noise rejection. To address this concern, the digital circuit block130is configured to generate an adjustable frequency fadj for the transmit signal TX with a fractional value. This is accomplished by using two or more values of N within a single sensing period. This operation is illustrated inFIG. 6.

Each sensing period130includes a plurality of integration periods132, wherein each integration period corresponds to one phase or half-cycle (positive or negative) of the TX signal. Within each integration period132, the digital circuit block130asserts the first control signal PHI_T to close switch100and integrate the charge from the capacitor70and then asserts the second control signal PHI_R to close switch102and reset the integrator back to Vref. The length of each integration period is dependent on the adjustable frequency fadj for the transmit signal TX. To produce the fractional value of the adjustable frequency fadj, the digital circuit block130alternates generating the transmit signal TX between two different integer values of N with a certain repetition pattern to produce, taken over the sensing period130, a mixed frequency fmix for the transmit signal TX. In the example shown inFIG. 6, the repetition pattern utilizes three half-cycles of the transmit signal TX with the frequency in each half-cycle set by N, N, N+1 within a pattern repetition period134so as to generate corresponding frequencies of fadj1, fadj1, fadj2 in the transmit signal half-cycles corresponding to the three integration periods. In this case, integration period132′ is associated with half-cycles at frequency fadj2 and integration period132is associated with half-cycles at frequency fadj1. The pattern repetition period134may be repeated as many times as desired within a given sensing period130. This particular repetition pattern will produce a fractional mixed frequency fmix for fadj in accordance with the following equation:

This is, of course, just an example. The pattern repetition period134may include any desired number of integration periods132and132′ with any selected number of frequencies fadj1 and fadj2. For example, the repetition pattern may instead utilize frequencies having half-cycles set by N, N+1, N+1 within the pattern repetition period134so as to generate corresponding frequencies of fadj1, fadj2, fadj2 in the transmit signal half-cycles corresponding to the three integration periods. This particular repetition pattern will produce a fractional mixed frequency fmix for fadj in accordance with the following equation:

More generically, the following equation is given:

Where: M is the number of integration periods132in each pattern repetition period134, and k is the number of integration period132which use the frequency fadj1. In an embodiment, k=1 and the values of M and N then set the fractional mixed frequency fmix. N may have a range of possible values (for example, N={50, 51 . . . 60}). There is a minimum value for N (depending on the time needed to fully transmit a sample and to fully reset the C2V after each transmission) and a maximum value for N (basically given by the speed requirement: larger N=>larger sampling period=>longer time to collect all the samples).

The values of M and k allow for increasing the set of N values, by adding fractions between two consecutive integer values of N (for example, {50, 50+⅛, 50+ 1/7 . . . 50+ 6/7, 50+⅞, 51 . . . 59+⅞, 60}). Actually, since there is a mix of two frequencies corresponding to the periods N and (N+1), the average period is:

It is now clear that k/M simply increments each N. For example, if it is desired to increment in steps of ⅛, then M=8 and the value of k can be changed from 1 to 7.

The values of N and k to be used are determined by a tuning functionality150implementing an algorithm that is triggered for operation if a noisy condition is detected by a noise detector152. During a tuning phase of operation, consecutive scans are performed by the tuning function150, using different values of N and k and comparing the digital outputs from the A/D converter120. The goal is to find the best combination of N and k which gives the least noise (measured as A/D code after the A/D conversion). The search for the optimal combination can be done by incrementing N and k (for each N, in order to sweep the interval [N,N+1]), by dichotomy (e.g. binary search) or by other custom means.

Alternatively, if the noise is pre-characterized and its harmonics are known, the best values of N and k can be predefined and stored as constants (and the tuning algorithm only searches among these values).

Although illustrated separately, it will be understood that the tuning functionality150may comprise a component within the digital circuit block130.

FIG. 7illustrates a simplified example showing how the noise at the fundamental frequency (i.e., the highest power harmonic) is canceled by summing the samples obtained from two sub-optimal frequencies (i.e., fadj1 and fadj2). It will be noted that duration of the pattern repetition period substantially matches an integer multiple of a period of the noise fundamental frequency. This matching is accomplished by appropriate selection of the M, N and k values. In this example, the repetition pattern utilizes N, N+1 within the pattern repetition period134so as to generate corresponding frequencies of fadj1, fadj2; this particular repetition pattern producing a fractional mixed frequency fmix in accordance with the following equation:

Although only two different frequencies (fadj1 and fadj2) are used in the examples presented above, it will be understood that this is by way of example only. The digital circuit block130may provide a repetition pattern that utilizes more than two different frequencies.

With reference once again toFIG. 6, in a preferred embodiment, the digital circuit block130uses a same length136asserted pulse for the first control signal PHI_T to close switch100regardless of the adjustable frequency fadj of the TX signal, but changes the length138,138′ of the asserted pulse for the second control signal PHI_R to close switch102dependent on the adjustable frequency fadj of the TX signal. This is by example only, it being understood that any suitable control may be exercised over the relative lengths of the asserted pulses for the first control signal PHI_T and the second control signal PHI_R so long as the asserted pulses do not overlap and the total length of the asserted pulses substantially equals the length of one phase (positive, negative) of the TX signal. In one embodiment, the second control signal PHI_R is a logical inversion of the first control signal PHI_T. There may be an advantage to fixing the length136of the asserted pulse for the first control signal PHI_T in order to ensure a sufficient and regulated integration time. The lengths138,138′ of the asserted pulse for the second control signal PHI_R must be sufficient to ensure that the integrator is reset to Vref. Appropriate limits may be programmed into the digital circuit block130to ensure proper asserted pulse lengths.

The following advantages of the solution described above are noted: a) more frequencies are made available for selection by the frequency hopping algorithm implemented by the digital circuit block130; b) this allows for a finer resolution when choosing an optimal scanning frequency (having the lowest noise power); c) availability and selection of such a scanning frequency (not available through selection of one value of N) allows for a much higher rejection of external noise; and d) external noise focused at a certain harmonic frequency can be completely or almost completely canceled due to the availability of the fractional mixed frequency.

FIG. 8is a normalized power spectrum plot showing at reference200the spectrum for an ideal frequency fmixi=fclk/(N+0.5) and showing at reference202the spectrum for the fractional mixed frequency fmix obtained by mixing fclk/N and fclk/(N+1) as described above. The two power spectra advantageously substantially match each other except at some distortion locations204where the fractional mixed frequency fmix lacks notches present in the ideal frequency fmixi. The goal is to find an intermediate adjustable scanning frequency fadj for the signal TX such that the fundamental frequency of the noise falls within a notch of the power spectrum for the scanning frequency fadj. Because of the distortion locations204, care must be taken in selecting the fractional mixed frequency fmix to ensure that the noise frequency is present in the notch.

Various embodiments have been described. Various alterations, modifications, and improvements will readily occur to those skilled in the art. Further, the practical implementation of the embodiments which have been described is within the abilities of those skilled in the art based on the functional indications given hereabove.