SEMICONDUCTOR DEVICE, SEMICONDUCTOR MODULE, AND WIRELESS COMMUNICATION APPARATUS

Provided is a semiconductor device (1) having high heat dissipation and high operation reliability. This semiconductor device includes: a semiconductor substrate (10); a first semiconductor layer (20) that is provided on the semiconductor substrate, has a first aperture (20K), and has a first thermal conductivity; a transistor (Tr) provided on the first semiconductor layer; and a heat dissipation unit (40) that is in contact with the semiconductor substrate via the first aperture and has a second thermal conductivity higher than the first thermal conductivity.

TECHNICAL FIELD

The present disclosure relates to a semiconductor device, a semiconductor module, and a wireless communication apparatus.

BACKGROUND ART

In recent years, a semiconductor device including an element having large power consumption, for example, a power amplifier circuit element or the like has been proposed (for example, refer to Patent Literature 1).

CITATION LIST

Patent Literature

SUMMARY OF THE INVENTION

By the way, in a case of such a high output semiconductor element such as a power amplifier, due to its relatively large power consumption, a calorific value caused by an operation of the high output semiconductor element increases. A case is assumed where an operation of a circuit including the high output semiconductor element is lowered when a temperature of the high output semiconductor element and a surrounding temperature increase.

Therefore, a semiconductor device having high heat dissipation and high operation reliability, and a semiconductor module and a wireless communication apparatus including the semiconductor device are desired.

A semiconductor device according to an embodiment of the present disclosure includes a semiconductor substrate, a first semiconductor layer that is provided on the semiconductor substrate, has a first aperture, and has a first thermal conductivity, a transistor provided on the first semiconductor layer, and a heat dissipation unit that is in contact with the semiconductor substrate via the first aperture and has a second thermal conductivity higher than the first thermal conductivity.

In the semiconductor device according to an embodiment of the present disclosure, the first aperture is provided in the first semiconductor layer where the transistor is provided, and the semiconductor substrate is in contact with the heat dissipation unit via the first aperture. Therefore, heat generated in the transistor is efficiently released outside.

MODES FOR CARRYING OUT THE INVENTION

Hereinafter, an embodiment of the present disclosure is described in detail with reference to the drawings. The embodiment described below is a specific example of the present disclosure, and a technique of the present disclosure is not limited to the following modes. In addition, the arrangement, dimensions, dimension ratios, and the like of components in the present disclosure are not limited to the mode illustrated in each drawing.

It is to be noted that the description is given in the following order.0. Background1. Embodiment (Example of Semiconductor Device Including HEMT)1-1. Configuration of Semiconductor Device1-2. Method for Manufacturing Semiconductor Device1-3. Workings and Effects of Semiconductor Device2. Experimental Example3. Example of Application3-1. Example of Application to Semiconductor Module3-2. Example of Application to Wireless Communication Apparatus

In recent years a high electron mobility transistor (HEMT) using a nitride semiconductor has been actively studied and developed. The nitride semiconductor has a larger band gap than Si, GaAs, or the like and has polarization specific to hexagonal crystals. Therefore, the HEMT using the nitride semiconductor is expected as a low-resistance high-withstand-voltage transistor that enables to perform a high-speed operation.

Specifically, application of the HEMT to, for example, a power device and a radio frequency (RF) device has been expected. For example, in base stations of satellite communications, wireless communications, or the like, practical use of a HEMT using AlGan for a barrier layer has been achieved.

By the way, for a semiconductor device used for the power device or the RF, in order to achieve high output and high efficiency, a transistor integrated unit called a multi-finger structure in which a plurality of transistor elements is arranged in parallel may be adopted. In the multi-finger structure, multiple finger portions respectively configuring gate electrodes of the plurality of transistor elements are arranged in parallel, and some of the multiple finger portions are coupled with a plurality of coupling portions, for example, in a winding manner.

However, a set of the plurality of finger portions often accumulates heat generated by the plurality of transistor elements and increases a temperature of the semiconductor device. There is a possibility that the increase in the temperature of the semiconductor device lowers a mobility of electrons, lowers a current amount, and lowers an output voltage. Therefore, as a technique for suppressing a temperature increase, a method is considered for using a material with high heat conductivity near a heat-producing portion or arranging a dummy bump to dissipate heat via the dummy bump.

However, in the future, it is expected that high integration is further requested in order to achieve higher output and higher efficiency.

Therefore, the applicant of the present application has studied to develop a semiconductor device that enables to more efficiently dissipate heat, and has created a semiconductor device with high heat dissipation and high operation reliability.

[1-1. Configuration of Semiconductor Device]

First, a configuration of a semiconductor device1according to an embodiment of the present disclosure is described with reference toFIG.1.FIG.1is a vertical cross-sectional diagram illustrating a configuration example of the semiconductor device1according to the present embodiment. Note that the configuration of the semiconductor device1illustrated inFIG.1is an example, and a configuration of a semiconductor device according to the present disclosure is not limited to this.

As illustrated inFIG.1, the semiconductor device1includes a substrate10, a semiconductor layer20, a transistor integrated unit30, and a heat dissipation unit40. The semiconductor device1includes a high electron mobility transistor (HEMT) using a two-dimensional electron gas layer2DEG to be described layer as a channel. Here, as illustrated inFIG.1, a plane parallel to a plane covered with each of the substrate10and the semiconductor layer20is set as an XY plane, and a direction perpendicular to the XY plane is set as a Z-axis direction. The Z-axis direction is a thickness direction of the substrate10and is also a thickness direction of the semiconductor layer20. Furthermore, in the present embodiment, a direction in which a plurality of transistors Tr to be described later is arranged is set as an X-axis direction, and a direction in which each of a plurality of gate electrodes31to be described later extends is set as a Y-axis direction. The X-axis direction, the Y-axis direction, and the Z-axis direction are perpendicular to each other.

The substrate10is a support of the semiconductor device1. The substrate10is, for example, a silicon (Si) substrate, a silicon carbide (SiC) substrate, a sapphire substrate, a gallium nitride (GaN) substrate, or an aluminum nitride (AlN) substrate. As the Si substrate, for example, a single-crystal Si (111) substrate having a (111) plane as a principal surface is suitable.

Note that the substrate10using the above materials obtains effects of the semiconductor device according to the present disclosure to be described below. All Examples and Reference examples described later are results in a case where the substrate10including Si (111) is used. With the semiconductor device1using a substrate including SiC or a substrate including GaN that has a better single crystallinity and obtains a lower threading dislocation density than Si (111), it is possible to expect to further reduce an off-leak current and increase a voltage resistance. Therefore, it is sufficient to configure the substrate10by selecting a preferred material in accordance with use applications or the like.

The semiconductor layer20is laminated on the substrate10. In a part of the semiconductor layer20, an aperture20K that passes through the semiconductor layer20in the thickness direction, that is, the Z-axis direction is provided. The semiconductor layer20has a laminated structure, in which a buffer layer21, a channel layer22, and a barrier layer23are laminated in order, for example. In the buffer layer21, an aperture21K that passes through the buffer layer21in its thickness direction is provided. In the channel layer22, an aperture22K that passes through the channel layer22in its thickness direction is provided. In the barrier layer23, an aperture23K that passes through the barrier layer23in its thickness direction is provided. These apertures21K to23K communicate with each other and configure the single aperture20K. Note that another layer may be interposed between the buffer layer21and the channel layer22, and another layer may be interposed between the channel layer22and the barrier layer23. In addition, the semiconductor layer20may include another layer other than the buffer layer21, the channel layer22, and the barrier layer23. Note that details of a configuration example of the semiconductor layer20is described later.

The transistor integrated unit30includes the plurality of transistors Tr. In the present embodiment, within a region along the XY plane of the semiconductor device1, a region where the transistor integrated unit30is provided is referred to as an active region AR1, and a region other than the active region AR1is referred to as a peripheral region AR2. The plurality of transistors Tr is provided on the semiconductor layer20. The plurality of transistors Tr is arranged, for example, to be adjacent to each other in the X-axis direction and forms a so-called multi-finger structure. The transistor Tr includes, for example, a gate electrode31, a source electrode32, a drain electrode33, a contact layer34, a contact layer35, and a wiring layer36. Each of the gate electrode31, the source electrode32, the drain electrode33, the contact layer34, the contact layer35, and the wiring layer36extends with the Y-axis direction as a longitudinal direction. The gate electrode31of each of the plurality of transistors Tr serves as a finger portion extending in the Y-axis direction, and the plurality of finger portions is coupled with each other with a plurality of coupling portions, for example, in a winding manner.

The contact layer34is couped to a lower surface of the source electrode32, for example. The contact layer35is couped to a lower surface of the drain electrode33, for example. The contact layers34and35lower a contact resistance with the two-dimensional electron gas layer2DEG formed in the channel layer22. It is preferable that the contact layers34and35include a semiconductor material having a band gap close to a band gap of a semiconductor material configuring the channel layer22. The contact layers34and35are formed, for example, by crystal regrowth of a compound semiconductor. The contact layers34and35are formed, specifically, with a nitride semiconductor in which n-type impurities are introduced. For example, the contact layers34and35may be formed by introducing, for example, silicon (Si) or germanium (Ge) into an epitaxial growth layer of Al1-x-yInxGayN (0≤x≤1, 0≤y≤1, and x+y≤1) to realize a concentration of greater than or equal to 1*1018/cm3.

The gate electrode31has a laminated structure, for example, formed by sequentially laminating a nickel (Ni) layer and a gold (Au) layer. The source electrode32and the drain electrode33have a laminated structure, for example, formed by sequentially laminating a titanium (Ti) layer, an aluminum (Al) layer, a nickel (Ni) layer, and a gold (Au) layer. An insulation film51is provided to cover the source electrode32and the drain electrode33. An insulation film52is further provided on the insulation film51. In addition, the insulation film52covers an inner surface of the aperture20K provided in the peripheral region AR2within the semiconductor layer20. The insulation films51and52protect the source electrode32and the drain electrode33.

In the insulation film51, apertures are respectively provided at positions respectively overlapping the source electrode32and the drain electrode33. The wiring layer36is provided in upper layers of the source electrode32and the drain electrode33. The wiring layer36is electrically connected to each of an upper surface of the source electrode32and an upper surface of the drain electrode33via the apertures of the insulation film51. The wiring layer36is formed, for example, by sequentially laminating a titanium (Ti) layer, a platinum (Pt) layer, and a gold (Au) layer, in order from the side of the substrate10. It is preferable that a thickness of the wiring layer36be sufficiently thicker than both of a thickness of the source electrode32and a thickness of the drain electrode33. That is, it is sufficient that a cross-sectional area of the wiring layer36be larger than both of a cross-sectional area of the source electrode32and a cross-sectional area of the drain electrode33on an XZ plane perpendicular to the Y-axis direction that is the longitudinal direction of the source electrode32, the drain electrode33, and the wiring layer36. An outer surface of the wiring layer36is covered, for example, with an insulation film53. The insulation film53is a passivation film that protects the wiring layer36and a wiring layer41. The insulation film53is a single-layer film including silicon nitride (SiN), for example.

The heat dissipation unit40is in contact with the substrate10via the aperture22K. A thermal conductivity of the heat dissipation unit40is higher than a thermal conductivity of the semiconductor layer20. The heat dissipation unit40has a structure in which the wiring layer41, a pillar42, and a bump43are laminated on the substrate10in order, for example. The wiring layer41includes a material such as metal having higher heat conductivity than the thermal conductivity of the semiconductor layer20. It is desirable that a thermal conductivity of each of the wiring layer41, the pillar42, and the bump43included in the heat dissipation unit40be higher than a thermal conductivity of each layer included in the semiconductor layer20. The wiring layer41has, for example, a laminated structure same as the wiring layer36. An outer surface of the wiring layer41is covered with the insulation film53, for example. A bottom surface of the wiring layer41is in contact with the substrate10and forms a sub contact27. The pillar42includes metal with high heat conductivity, for example, copper (Cu) or the like. The bump43is a metal plating film, for example, including a tin-silver alloy (SnAg) or the like. Furthermore, the heat dissipation unit40is electrically isolated from the transistor Tr of the transistor integrated unit30. Furthermore, a thickness of the heat dissipation unit40is thicker than both of the thickness of the source electrode32and the thickness of the drain electrode33. Furthermore, a volume of the heat dissipation unit40is larger than both of a volume of the source electrode32and a volume of the drain electrode33.

(Detailed Configuration of Semiconductor Layer20)

Next, a detailed configuration of the semiconductor layer20of the semiconductor device1is described with reference toFIG.2.FIG.2is a vertical cross-sectional diagram illustrating an enlarged portion of the semiconductor device1. Note that the configuration of the semiconductor layer20illustrated inFIG.2is an example, and a configuration of a semiconductor layer of the present disclosure is not limited to this.

As illustrated inFIG.2, the semiconductor layer20has a laminated structure in which a first buffer layer21A, a second buffer layer21B, the channel layer22, a spacer layer24, the barrier layer23, and a protection layer25are laminated on the substrate10in order. The first buffer layer21A and the second buffer layer21B configure the buffer layer21. On the protection layer25of the semiconductor layer20, the transistor integrated unit30is provided in which the plurality of transistors Tr each including the source electrode32, the drain electrode33, a gate insulation film Z, and the gate electrode31is arranged. The transistor Tr has, for example, a metal-insulator-semiconductor (MIS) type gate structure. Therefore, in the transistor Tr, for example, the gate electrode31is provided on the semiconductor layer20via the gate insulation film Z. Note that the gate structure of the present disclosure is not limited to the MIS type gate structure, and for example, may be a Schottky type gate structure in which the gate electrode31is directly connected with the semiconductor layer20.

The semiconductor device1according to the present embodiment includes the high electron mobility transistor (HEMT) using the two-dimensional electron gas layer2DEG as a channel. The two-dimensional electron gas layer2DEG is generated due to a difference between a magnitude of polarization of the channel layer22and a magnitude of polarization of the barrier layer23. The two-dimensional electron gas layer2DEG is generated, for example, near an interface KS between the channel layer22and the spacer layer24, within the channel layer22.

The first buffer layer21A and the second buffer layer21B include, for example, an epitaxially grown nitride semiconductor. The first buffer layer21A and the second buffer layer21B enable to relax lattice mismatch between the substrate10and the channel layer22, by controlling a lattice constant of a surface where the channel layer22is provided. Therefore, the first buffer layer21A and the second buffer layer21B enable to further improve a crystal condition of the channel layer22and prevent warpage of the substrate10.

For example, in a case where the substrate10is a single-crystal Si substrate of which a principal surface is the (111) plane and the channel layer22is a GaN layer, the first buffer layer21A may include AlN, and the second buffer layer21B may include AlGaN. However, depending on the configurations of the substrate10and the channel layer22, both of the first buffer layer21A and the second buffer layer21B do not need to exist. Alternatively, only the first buffer layer21A out of the first buffer layer21A and the second buffer layer21B may be provided.

The channel layer22is provided on the second buffer layer21B. The channel layer22includes, for example, a nitride semiconductor having a band gap smaller than a band gap of the spacer layer24and a band gap of the barrier layer23. The channel layer22enables to accumulate carriers in an interface on the side of the barrier layer23, in accordance with the difference between the magnitude of the polarization of the channel layer22and the magnitude of the polarization of the barrier layer23. The channel layer22includes, for example, a group III-V semiconductor.

Specifically, the channel layer22may include Alx5Iny5Ga(1-x5-y5)N (0≤x5≤1,0≤y5≤1, 0≤x5+y5≤1) that is an epitaxially grown nitride semiconductor. For example, the channel layer22includes epitaxially grown gallium nitride (GaN). Alternatively, the channel layer22may include at least one type of indium gallium nitride (InGaN), indium nitride (InN), aluminum gallium nitride (AlGaN), and aluminum indium gallium nitride (AlInGaN). More specifically, the channel layer22may include undoped u-GaN to which impurities are not added. In that case, the channel layer22enables to prevent carrier impurity scattering. Therefore, the channel layer22enables to further enhance mobility of the carrier.

The spacer layer24includes, for example, a nitride semiconductor having a band gap larger than the band gap of the channel layer22. The spacer layer24is provided on the channel layer22. The spacer layer24reduces alloy scattering between the barrier layer23and the channel layer22and prevents deterioration in the carrier mobility of the two-dimensional electron gas layer2DEG due to the alloy scattering.

Specifically, the spacer layer24may include epitaxially grown Alx1Iny1Ga(1-x1-y1)N(0<x1≤1,0≤y1<1,0≤x1+y1≤1). For example, the spacer layer24may include AlN, or may include AlGaN or AlInGaN.

The barrier layer23includes, for example, a nitride semiconductor having a band gap larger than the band gap of the channel layer22. The barrier layer23is provided on the spacer layer24. The barrier layer23enables to accumulate carriers in a region near the barrier layer23within the channel layer22by spontaneous polarization and piezoelectric polarization. As a result, in the semiconductor device1, in a region near the interface KS within the channel layer22, it is possible to form the two-dimensional electron gas layer2DEG with high mobility and high carrier concentration.

Specifically, the barrier layer23includes Alx3Iny3Ga(1-x3-y3)N (x2<x3<1, 0≤y3<1) that is an epitaxially grown nitride semiconductor. Here, x3>0.7 and y3<0.3 may be satisfied. For example, the barrier layer23may include undoped u-Alx3In(1-x3)N to which impurities are not added. In such a case, it is possible to reduce lattice mismatch with GaN in the barrier layer23, and this makes it possible to obtain a crystal with excellent single crystallinity.

In a case where a composition ratio of Al of the barrier layer23is high, in particular, the barrier layer23is likely to be oxidized. In order to prevent such oxidization, it is preferable to provide the protection layer25on the barrier layer23. The protection layer25protects a surface of the barrier layer23from impurities such as chemicals or various ions and maintains the surface of the barrier layer23to be excellent to make it possible to prevent deterioration in operation characteristics of the semiconductor device1. The protection layer25includes, for example, Alx4Iny4Ga(1-x4 y4)N (0≤x4<1, 0≤y4<1) that is an epitaxially grown nitride semiconductor. Note that, in a relation with the nitride semiconductor included in the barrier layer23, it is preferable to satisfy (1-x3-y3)<(1-x4-y4). Therefore, the protection layer25includes, for example, GaN. The protection layer25may include AlInGaN, AlGaN, or InGaN. GaN has the highest single crystallinity. InGaN easily has n-type contact. Regarding AlInGaN and AlGaN, by selecting a composition with a lower Al composition than the barrier layer23, it is possible to obtain a mixed crystal having a larger band gap than GaN and InGaN while performing a function as a protection layer. Having a large band gap is advantageous to obtain a high two-dimensional electron gas concentration. In a case where there is no concern about the characteristics due to the oxidization of the barrier layer23, the protection layer25does not need to exist.

As described above, all of the gate electrode31, the source electrode32, and the drain electrode33include conductive materials. All of the gate electrode31, the source electrode32, and the drain electrode33are provided on the semiconductor layer20. The gate electrode31is arranged between the source electrode32and the drain electrode33. The gate electrode31is provided on the protection layer25, via the gate insulation film Z. Note that the gate electrode31may form schottky junction by contacting with the nitride semiconductor configuring the protection layer25without via the gate insulation film Z.

The gate insulation film Z includes an insulating material. The gate insulation film Z is provided to cover a region that is not covered with any one of the gate electrode31, the source electrode32, and the drain electrode33, within the region on the protection layer25. A configuration material of the gate insulation film Z is, for example, aluminum oxide (Al2O3), silicon dioxide (SiO2), silicon nitride (Si3N4), hafnium oxide (HfO2), or the like. The gate insulation film Z may be a single-layer film including the configuration material described above or may be a multi-layer film in which a plurality of layers including the above-described configuration material is laminated.

[1-2. Method for Manufacturing Semiconductor Device]

Next, an example of a method for manufacturing the semiconductor device1according to the present embodiment is described with reference toFIGS.1and2.

First, the substrate10is prepared, and then, the semiconductor layer20is formed thereon. Specifically, as illustrated inFIG.2, for example, on the substrate10, the first buffer layer21A, the second buffer layer21B, the channel layer22, the spacer layer24, the barrier layer23, and the protection layer25are sequentially epitaxially grown.

Next, the transistor integrated unit30is formed on the semiconductor layer20. Specifically, first, a region, within the semiconductor layer20, where the contact layers34and35should be formed is selectively etched to dig into a predetermined depth. Subsequently, by forming the nitride semiconductor in the selectively etched portion through epitaxial growth, the contact layers34and35are obtained. Subsequently, the source electrode32and the drain electrode33are respectively formed to cover the contact layers34and35. Moreover, the insulation film51(FIG.1) that covers the source electrode32and the drain electrode33is formed. Next, after forming the gate insulation film Z (FIG.2), the gate electrode31is further formed on the gate insulation film Z. As described above, the transistor integrated unit30is formed.

Subsequently, as illustrated inFIG.1, by selectively removing a part of the semiconductor layer20in the peripheral region AR2, the aperture20K is formed. It is possible to form the aperture20K, for example, by dry etching. By forming the aperture20K, an upper surface of the substrate10is exposed. Next, the insulation film52is formed over an entire surface, to cover the aperture20K and the transistor integrated unit30. Subsequently, by selectively removing a part of the insulation film52that covers the substrate10positioned at the bottom surface of the aperture20K, for example, by dry etching, an aperture52K is formed. As a result, the substrate10is exposed again. At the same time as the formation of the aperture52K, a part of the insulation film52that covers the source electrode32and the drain electrode33is also selectively removed.

Subsequently, for example, by sequentially laminating a titanium (Ti) layer, a platinum (Pt) layer, and a gold (Au) layer to fill the aperture52K, the wiring layer41is formed. As a result, the sub contact27in which the wiring layer41and the substrate10are coupled is formed. It is desirable that no insulation film such as an oxidized film do not exist in the interface between the wiring layer41and the substrate10. Furthermore, at the same time as the formation of the wiring layer41, the wiring layer36coupled to each of the source electrode32and the drain electrode33is formed.

After forming the wiring layers41and36, the insulation film53is formed to cover the outer surfaces of the wiring layers41and36. Thereafter, by selectively removing a part of the insulation film53that covers the wiring layer41, an aperture53K is formed. On the wiring layer41exposed in the aperture53K, for example, the pillar42including copper (Cu) and, for example, the bump43including a tin-silver alloy (SnAg) are selectively formed in order, for example, by a plating process. As a result, the heat dissipation unit40is completed.

Through the above process, it is possible to form the semiconductor device1according to the present embodiment.

[1-3. Workings and Effects of Semiconductor Device]

As described above, in the semiconductor device1according to the present embodiment, the transistor integrated unit30is formed in the active region AR1of the semiconductor layer20provided on the substrate10, and the heat dissipation unit40is provided in the peripheral region AR2of the semiconductor layer20. The heat dissipation unit40is in contact with the substrate10via the aperture20K of the semiconductor layer20and forms the sub contact27. Moreover, the thermal conductivity of the heat dissipation unit40is higher than the thermal conductivity of the semiconductor layer20. Therefore, as compared with a case where the substrate10and the heat dissipation unit40are blocked by the semiconductor layer20, heat generated in the transistor integrated unit30is efficiently released to the outside via the heat dissipation unit40. As a result, it is possible for the semiconductor device1to effectively suppress an increase in the temperature at the time of operation.

As a result, the semiconductor device1has high heat dissipation and high operation reliability, and this makes it possible for the semiconductor device1to be more highly integrated.

2. Experimental Example

A thermal resistance of the semiconductor device1illustrated inFIG.1was studied. Specifically, regarding the semiconductor device1illustrated inFIGS.3A and3B, a thermal resistance θj-b of the semiconductor device1when the transistor integrated unit30produces heat was obtained by a simulation.FIG.3Ais a plan view schematically illustrating an overall configuration of the semiconductor device1according to the present example, andFIG.3Bis a cross-sectional diagram schematically illustrating the overall configuration of the semiconductor device1according to the present example. Here, silicon (Si) with a thickness of 200 μm was assumed as the substrate10, and the thermal conductivity was set to 148 W/mK. Furthermore, a thickness of the overall semiconductor layer20was set to two μm, and a thermal conductivity of the overall semiconductor layer20was set to 40 W/mK. Furthermore, the heat dissipation unit40included only the wiring layer41and the pillar42. The aperture20K was filled with the wiring layer41including titanium (Ti) and was brought into contact with the substrate10to allow to form the sub contact27. Moreover, on a side of the pillar42opposite to the substrate10, a heat block71was disposed. The heat block71and the wiring layer41were coupled by the pillar42, and the heat of the semiconductor device1was released to the heat block71via the pillar42. A protection film70including SiN was provided to cover a region other than the heat dissipation unit40. A thermal conductivity of the protection film70was set to 20 W/mK.

Furthermore, it was assumed that, in the semiconductor device1according to the present example, the transistor integrated unit30include 30 transistors Tr arranged in the X-axis direction. Specifically, it was assumed that the gate electrodes31that extend in the Y-axis direction and have the finger length L1 of 50 μm be arranged in the Y-axis direction at an arrangement pitch of 6.4 μm. Furthermore, an ohmic length was set to five μm. An ambient temperature was set to 25° C., and a thermal resistance between the heat block71and an atmosphere was set to 137 K/W. Furthermore, in the present example, a distance L2 in the Y-axis direction between a center position40CP of the heat dissipation unit40and a center position31CP of the gate electrode31was set to each of four levels including 60, 100, 140, and 300 μm, and a thermal resistance was calculated. Moreover, an area of a region of the sub contact27where the wiring layer41is in contact with the substrate10, that is, a contact region area CA was set to 4,900 μm2. Furthermore, as illustrated inFIG.3A, on the XY plane, the center position of the sub contact27and the center position of the transistor integrated unit30matched in the Y-axis direction. Furthermore, in the present example, a calorific value of the transistor integrated unit30was set to 0.5 W.

Furthermore, the thermal resistance θj-b was calculated in accordance with the following formula (1).

Here, TFmaxrepresents a highest temperature of a finger included in the gate electrode31, THmaxrepresents a highest temperature of the heat block71, and Cv represents the calorific value of the transistor integrated unit30.

Reference Example 1-1

For comparison, a thermal resistance of a semiconductor device101as a Reference example 1-1 was studied. In the semiconductor device101as the Reference example 1-1, as illustrated inFIG.4, the semiconductor layer20does not have the aperture20K, and the wiring layer41of the heat dissipation unit40and the substrate10are blocked and separated by the semiconductor layer20. In this way, except for that the semiconductor device101does not include the sub contact27, the semiconductor device101has the configuration same as the semiconductor device1of the Example 1-1.

Regarding the semiconductor device1illustrated inFIGS.3A and3Band the semiconductor device101illustrated inFIG.4, the thermal resistance θj-b when the transistor integrated unit30produces heat was obtained by a simulation. As a propagation path of the heat generated in the transistor integrated unit30, for example, as illustrated inFIG.3B, three paths are mainly considered. That is, a path P1from the gate electrode31to the wiring layer41of the heat dissipation unit40via the protection film70, a path P2from the gate electrode31to the wiring layer41of the heat dissipation unit40via the semiconductor layer20, and a path P3from the gate electrode31to the wiring layer41of the heat dissipation unit40via the semiconductor layer20and the substrate10are considered.

FIG.5Aillustrates a relation between the distance L2 and the thermal resistance θj-b. InFIG.5A, the horizontal axis represents the distance L2 [μm], and the vertical axis represents the thermal resistance θj-b [° C./W]. InFIG.5A, a curved line5C1represents a thermal resistance θj-b in the Example 1-1, a curved line5C2represents a thermal resistance θj-b in the Reference example 1-1, and a curved line5C3represents a difference between the thermal resistance θj-b in the Example 1-1 and the thermal resistance θj-b in the Reference example 1-1. As illustrated inFIG.5A, in a case where the distance L2 is the same, the thermal resistance θj-b in the Example 1-1 was lower than that in the Reference example 1-1. That is, it was possible to confirm that the semiconductor device1according to the Example 1-1 having the sub contact27in which the heat dissipation unit40is in contact with the substrate10has higher heat dissipation than the semiconductor device101according to the Reference example 1-1 in which the heat dissipation unit40is separated from the substrate10by the semiconductor layer20. It is considered that one reason for this is that, in the semiconductor device1according to the Example 1-1, heat propagation through the path P3(FIG.3B) is more satisfactorily performed than the semiconductor device101according to the Reference example 1-1. However, the difference between the thermal resistance θj-b in the Example 1-1 and the thermal resistance θj-b in the Reference example 1-1 was substantially constant, without depending on the distance L2 (refer to curved line5C3).

Here, inFIG.5B, a relation between a value obtained by standardizing the distance L2 with the finger length L1 (=50 μm) and the thermal resistance θj-b is illustrated. InFIG.5B, the horizontal axis represents (distance) L2/(finger length) L1 [−], and the vertical axis on the left side represents the thermal resistance θj-b [° C./W]. Furthermore, inFIG.5B, with reference to the thermal resistance θj-b of the semiconductor device101according to the Reference example 1-1, an improvement effect X [%] was indicated by the vertical axis on the right side inFIG.5B, as an index representing how much the thermal resistance θj-b of the semiconductor device1according to the Example 1-1 was lowered. InFIG.5B, the curved line5C3represents a relation between L2/L1 [−] and the improvement effect X [%]. As illustrated inFIG.5B, it was found that a higher improvement effect X [%] is obtained in a case where L2/L1 [−] is less than or equal to two. That is, it was possible to confirm that, if the heat dissipation unit40is arranged near the transistor integrated unit30to cause L2/L1 [−] to be less than or equal to two, a higher heat dissipation effect is obtained.

Next, the thermal resistance θj-b was evaluated as in the Example 1-1 under conditions similar to the Example 1-1, except that the finger length L1 was set to 100 μm and the arrangement pitch of the gate electrodes31was set to 11.4 μm.

Reference Example 1-2

The thermal resistance θj-b was evaluated as in the Reference example 1-1 under conditions similar to the Reference example 1-1, except that the finger length L1 was set to 100 μm and the arrangement pitch of the gate electrodes31was set to 11.4 μm,

InFIGS.6A and6B, evaluation results of the thermal resistances θj-b in the Example 1-2 and the Reference example 1-2 are illustrated.FIGS.6A and6Bare diagrams respectively corresponding toFIGS.5A and5B. InFIG.6A, the horizontal axis represents the distance L2 [μm], and the vertical axis represents the thermal resistance θj-b [° C./W]. InFIG.6A, a curved line6C1represents the thermal resistance θj-b in the Example 1-2, a curved line6C2represents the thermal resistance θj-b in the Reference example 1-2, and a curved line6C3represents a difference between the thermal resistance θj-b in the Example 1-2 and the thermal resistance θj-b in the Reference example 1-2. As illustrated inFIG.6A, in a case where the distance L2 is the same, the thermal resistance θj-b in the Example 1-2 was lower than that in the Reference example 1-2. However, the difference between the thermal resistance θj-b in the Example 1-2 and the thermal resistance θj-b in the Reference example 1-2 was substantially constant, without depending on the distance L2 (refer to curved line6C3). That is, the Example 1-2 and the Reference example 1-2 indicated substantially similar tendency to the tendency of the Example 1-1 and the Reference example 1-1. InFIG.6B, the horizontal axis represents (distance) L2/(finger length) L1 [−], and the vertical axis on the left side represents the thermal resistance θj-b [° C./W]. Furthermore, inFIG.6B, with reference to the thermal resistance θj-b of the semiconductor device101according to the Reference example 1-2, the improvement effect X [%] was indicated by the vertical axis on the right side inFIG.6B, as an index representing how much the thermal resistance θj-b of the semiconductor device1according to the Example 1-2 was lowered. InFIG.6B, the curved line6C3represents a relation between L2/L1 [−] and the improvement effect X [%]. As illustrated inFIG.6B, it was also found that a higher improvement effect X [%] is obtained in a case where L2/L1 [−] is less than or equal to two. That is, it was possible to confirm that, if the heat dissipation unit40is arranged near the transistor integrated unit30to cause the following condition expression (A) to be satisfied, a higher heat dissipation effect is obtained.

Note that it is preferable that the finger length L1 be, for example, longer than or equal to 25 μm and shorter than or equal to 200 μm.

Next, regarding the semiconductor device1illustrated inFIGS.3A and3B, how the thermal resistance θj-b of the semiconductor device1when the transistor integrated unit30produces heat changes depending on the contact region area CA between the wiring layer41and the substrate10in the sub contact27was obtained by a simulation. In the present example, the distance L2 was set to 100 μm. Furthermore, in the present example, the contact region area CA was set to each of five levels including 4,400, 6,400, 8,400, 9,400, and 14,400 μm2, and a thermal resistance was calculated. Note that other configurations such as the configuration of the transistor integrated unit30were set to be similar to those in the Example 1-1.

Reference Example 2

For comparison, a thermal resistance of the semiconductor device101as a Reference example 2 has been studied. The semiconductor device101as the Reference example 2 has the same configuration as the semiconductor device1according to the Example 2 except that the semiconductor device101does not include the sub contact27.

InFIG.7A, a relation between the contact region area CA and the thermal resistance θj-b is illustrated. InFIG.7A, the horizontal axis represents the contact region area CA [μm2], and the vertical axis represents the thermal resistance θj-b [° C./W]. InFIG.7A, a curved line7C1represents a thermal resistance θj-b in the Example 2, a curved line7C2represents a thermal resistance θj-b in the Reference example 2, and a curved line7C3represents a difference between the thermal resistance θj-b in the Example 2 and the thermal resistance θj-b in the Reference example 2. As illustrated inFIG.7A, in a case where the contact region area CA is the same, the thermal resistance θj-b in the Example 2 was lower than that in the Reference example 2. That is, it was possible to confirm that the semiconductor device1according to the Example 2 including the sub contact27in which the heat dissipation unit40is in contact with the substrate10has higher heat dissipation than the semiconductor device101according to the Reference example 2 in which the heat dissipation unit40is separated from the substrate10by the semiconductor layer20. Furthermore, as the contact region area CA was smaller, the difference between the thermal resistance θj-b in the Example 2 and the thermal resistance θj-b in the Reference example 2 tended to be larger (refer to curved line7C3). It is considered that one reason for this is that, heat is more effectively released in a portion, in the sub contact27, at a position closer to the transistor integrated unit30.

Here, inFIG.7B, a relation between a value obtained by standardizing the contact region area CA with an area CB of the transistor integrated unit30(referred to as FET area below) and the thermal resistance θj-b is illustrated. The FET area CB is defined by (finger length L1)*(the number of fingers)*(arrangement pitch of fingers). Specifically, (FET area) CB=50 μm*30*6.4 μm=9,600 [μm2]. InFIG.7B, the horizontal axis represents (contact region area) CA/(FET area) CB [−], and the vertical axis on the left side represents the thermal resistance θj-b [° C./W]. Furthermore, inFIG.7B, with reference to the thermal resistance θj-b of the semiconductor device101according to the Reference example 2, an improvement effect X [%] was indicated by the vertical axis on the right side inFIG.7Bas an index representing how much the thermal resistance θj-b of the semiconductor device1according to the Example 2 was lowered. InFIG.7B, the curved line7C3represents a relation between CA/CB [−] and the improvement effect X [%]. As illustrated inFIG.7B, it was found that a higher improvement effect X [%] is obtained as CA/CB [−] is smaller. From this, it was found that it is possible to effectively release heat by arranging the sub contact27at a position close to the transistor integrated unit30as possible even if the contact region area CA is small.

3. Example of Application

Subsequently, a semiconductor module that is a first application example of the technique of the present disclosure is described with reference toFIG.8.FIG.8is a schematic perspective view of a configuration of a semiconductor module100.

As illustrated inFIG.8, the semiconductor module100is an antenna-integrated module, for example, in which an edge antenna120and a plurality of front-end components are mounted on a single chip50as a module. The plurality of edge antennae120is formed, for example, on the chip50in an array. The front-end component is, for example, a switch110, a low noise amplifier141, a bandpass filter142, a power amplifier143, or the like. For example, the semiconductor module100may be used as a transceiver for wireless communication.

The semiconductor module100includes the semiconductor device1according to the present embodiment, for example, as a transistor configuring the switch110, the low noise amplifier141, the power amplifier143, or the like. For example, in the 5th generation mobile communication system (5G) using radio waves in a higher frequency band, a radio wave propagation loss is large. Therefore, it is desirable for the semiconductor module100conforming to the 5G to transmit radio waves with higher electric power. As it is possible for the semiconductor module100including the semiconductor device1according to the present embodiment to improve device characteristics, it is possible to perform wireless communication with high output, low power consumption, and high reliability. That is, it is possible to use the semiconductor module100for the 5th generation mobile communication system (5G) more preferably.

Next, a wireless communication apparatus that is a second application example of the technique of the present disclosure is described with reference toFIG.9.FIG.9is a block diagram illustrating a configuration of a wireless communication apparatus200.

As illustrated inFIG.9, the wireless communication apparatus200includes an antenna ANT, an antenna switch circuit203, a high power amplifier HPA, a high frequency integrated circuit radio frequency integrated circuit (RFIC), a baseband unit BB, a voice output unit MIC, a data output unit DT, and an interface unit I/F (for example, wireless local area network (W-LAN), Bluetooth (registered trademark), or the like). The wireless communication apparatus200is a mobile phone system that has multiple functions, for example, voice and data communication, LAN connection, or the like.

At the time of transmission, in the wireless communication apparatus200, a transmission signal is transmitted from the baseband unit BB to the antenna ANT via the high frequency integrated circuit RFIC, the high-power amplifier HPA, and the antenna switch circuit203. Furthermore, in the wireless communication apparatus200, at the time of reception, a reception signal is inputted from the antenna ANT to the baseband unit BB via the antenna switch circuit3and the high frequency integrated circuit RFIC. The reception signal processed by the baseband unit BB is outputted, for example, from the voice output unit MIC, the data output unit DT, or the interface unit I/F to outside the wireless communication apparatus2.

The wireless communication apparatus200includes the semiconductor device1according to the present embodiment, as a transistor configuring the antenna switch circuit203, the high-power amplifier HPA, the high frequency integrated circuit RFIC, the baseband unit BB, or the like. This makes it possible for the wireless communication apparatus200to further improve the device characteristics, and therefore, it is possible to perform wireless communication with high output, low power consumption, and high reliability.

The technique of the present disclosure has been described above with reference to the embodiments and the modification examples. However, the technique of the present disclosure is not limited to the above-described embodiments and the like, and is modifiable in a variety of ways.

In addition, not all of the configurations and the operations described in the embodiments are indispensable as the configurations and the operations of the present disclosure. For example, among the components of the embodiments, any component that is not recited in an independent claim which represents the most generic concept of the present disclosure is to be understood as an optional component.

Terms used throughout this specification and the appended claims should be construed as “non-limiting” terms. For example, the term “including” or “included” should be construed as “not limited to what is described as being included”. The term “having” should be construed as “not limited to what is described as being had”.

The terms used herein include terms that are used merely for convenience of description and that are not used to limit the configuration and the operation. For example, the terms such as “right”, “left”, “upper”, and “lower” only indicate directions in the drawings being referred to.

It is to be noted that the technique of the present disclosure may have the following configurations. According to the technique of the present disclosure having the following configurations, a first aperture is provided in a first semiconductor layer where a transistor is provided, and a semiconductor substrate is in contact with a heat dissipation unit via the first aperture. Therefore, heat generated in the transistor is efficiently released outside. As a result, the semiconductor device according to the present disclosure has high heat dissipation and high operation reliability, and this makes it possible for the semiconductor device to be more highly integrated.

The effect achieved by the technique of the present disclosure is not necessarily limited to the effects described herein and may be any effect described in the present disclosure.

A semiconductor device including:a semiconductor substrate;a first semiconductor layer that is provided on the semiconductor substrate, has a first aperture, and has a first thermal conductivity;a transistor provided on the first semiconductor layer; anda heat dissipation unit that is in contact with the semiconductor substrate via the first aperture and has a second thermal conductivity higher than the first thermal conductivity.
(2)

The semiconductor device according to (1), in which the heat dissipation unit includes metal.

The semiconductor device according to (1) or (2), in which the heat dissipation unit is electrically isolated from the transistor.

The semiconductor device according to any one of (1) to (3), in whichthe transistor includes a source electrode and a drain electrode, anda thickness of the heat dissipation unit is thicker than both of a thickness of the source electrode and a thickness of the drain electrode.
(5)

The semiconductor device according to any one of (1) to (4), in whichthe transistor includes a source electrode and a drain electrode, anda volume of the heat dissipation unit is larger than both of a volume of the source electrode and a volume of the drain electrode.
(6)

The semiconductor device according to any one of (1) to (5), in which the first semiconductor layer includes a group III-V semiconductor.

The semiconductor device according to (6), in which the group III-V semiconductor includes gallium nitride (GaN).

The semiconductor device according to any one of (1) to (3), further including a second semiconductor layer that is provided on an opposite side to the semiconductor substrate as viewed from the first semiconductor layer and has a second aperture communicating with the first aperture, in whichthe heat dissipation unit is in contact with the semiconductor substrate via the first aperture and the second aperture.
(9)

The semiconductor device according to (8), in whichthe first semiconductor layer includes a first nitride semiconductor having a first band gap, andthe second semiconductor layer includes a second nitride semiconductor having a second band gap larger than the first band gap.
(10)

The semiconductor device according to any one of (1) to (10), further including a plurality of the transistors, in whichthe plurality of transistors is arranged to be adjacent to each other in a first direction,each of the plurality of transistors includes a gate electrode that extends in a second direction perpendicular to the first direction, andthe plurality of transistors satisfies a following condition expression (A):

(L2/L1)≤2  (A)where L1 is a length of the gate electrode of each of the plurality of transistors in the second direction, and L2 is a distance in the second direction between a center position of the heat dissipation unit in the second direction and a center position of the gate electrode of each of the plurality of transistors in the second direction.
(11)

The semiconductor device according to (10), in which the length of the gate electrode in the second direction is longer than or equal to 25 μm and shorter than or equal to than 200 μm.

A semiconductor module including:a semiconductor device includinga semiconductor substrate,a first semiconductor layer that is provided on the semiconductor substrate, has a first aperture, and has a first thermal conductivity,a transistor provided on the first semiconductor layer, anda heat dissipation unit that is in contact with the semiconductor substrate via the first aperture and has a second thermal conductivity higher than the first thermal conductivity.
(13)

A wireless communication apparatus includinga semiconductor device includinga semiconductor substrate,a first semiconductor layer that is provided on the semiconductor substrate, has a first aperture, and has a first thermal conductivity,a transistor provided on the first semiconductor layer, anda heat dissipation unit that is in contact with the semiconductor substrate via the first aperture and has a second thermal conductivity higher than the first thermal conductivity.

The present application claims the benefit of Japanese Priority Patent Application No. 2021-130331 filed with Japan Patent Office on Aug. 6, 2021, the entire contents of which are incorporated herein by reference.