Switched capacitor circuit

A switched capacitor circuit includes: an operational amplifier; a first capacitor; a first switch that charges the first capacitor by connecting the first capacitor between an inverting input terminal and an output terminal of the operational amplifier, and discharges the first capacitor by disconnecting the inverting input terminal and the output terminal of the operational amplifier in a predetermined period; and a first output terminal that outputs an output voltage of the switched capacitor circuit, wherein after a predetermined period from a time when the first switch connects the first capacitor between the inverting input terminal and the output terminal of the operational amplifier, the first output terminal and the output terminal of the operational amplifier are connected to each other.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese patent application No. 2010-026441, filed on Feb. 9, 2010, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND

1. Field of the Invention

The present invention relates to a switched capacitor circuit.

2. Description of Related Art

In a circuit that handles a high frequency signal, such as a cellular phone, it is necessary to match a characteristic impedance to transmit a signal power efficiently. Matching the characteristic impedance requires an accurate inductor and capacitor. However, a variation in capacitance value becomes a problem in a semiconductor circuit. Therefore, it is necessary to detect the variation in capacitance value. To detect the variation, both a reference capacitor and an object capacitor are configured to act as switched capacitors. Then, an operational amplifier is driven through these equivalent resistors, thereby detecting the variation in capacitance as a voltage.

FIGS. 3A and 3Bshow an integrator1using a switched capacitor circuit. As shown inFIGS. 3A and 3B, the integrator1includes an operational amplifier OP1, a switching capacitor C1, a feedback capacitor C2, and a switch SW1.

An operation of the integrator1is explained with reference toFIGS. 3A and 3B. As shown inFIG. 3A, the switch SW1is connected to a side of an input terminal Vin. Assume that an input voltage Vin is applied to the input terminal Vin. At this time, the switching capacitor C1is charged according to the voltage Vin.

Referring next toFIG. 3B, the switch SW1is connected to a side of an inverting input terminal of the operational amplifier OP1. Because voltages at both terminals of the switching capacitor C1are set to a ground voltage GND, the electric charge stored in the switching capacitor C1is discharged. In this manner, the switching capacitor C1is repeatedly charged and discharged by alternately repeating the connection states ofFIGS. 3A and 3B. Assuming that a charge and discharge current is represented by Ij and a switching frequency of the switch SW1is represented by Fs at this time, the following expression (1) holds.
Ij=C1×Vin×Fs(1)

As shown in the expression (1), a constant current flows to the switching capacitor C1. Thus, the switching capacitor C1can be considered as an equivalent resistance. Therefore, the integrator1can be considered as an equivalent circuit like a circuit shown inFIG. 3C. A time constant T of this integrator1is represented by the following expression (2). The time constant T depends only on a relative accuracy regardless of an absolute variation of the capacitors C1and C2.

FIGS. 4A to 4Cshow a voltage amplification circuit2using a switched capacitor, in which the configuration of the integrator1shown inFIGS. 3A to 3Bis changed. As shown inFIGS. 4A and 4C, the voltage amplification circuit2includes the operational amplifier OP1, the switching capacitor C1, the feedback capacitor C2, and switches SW1to SW3.

An operation of the voltage amplification circuit2is explained with reference toFIGS. 4A and 4B. As shown inFIG. 4A, the switches SW1and SW2are connected to a side of the inverting input terminal of the operational amplifier ON, and the switch SW3is connected to a side of an output terminal Vout. Assume that an output voltage of the output terminal Vout is represented by Vout. At this time, the capacitors C1and C2are charged.

Referring next toFIG. 4B, the switch SW1is connected to the side of the inverting input terminal, and the switches SW2and SW3are connected to the side of the ground terminal GND. Therefore, the electric charge stored in the capacitors C1and C2are discharged. A charging current I1flows to the capacitor C1and a charging current I2flows to the capacitor C2, due to the repetition of the charge and discharge. These currents I1and I2are expressed by the following expressions (3) and (4), respectively.
I1=C1×Vin×Fs(3)
I2=C1×(Vout−Vin)×Fs(4)

The capacitors C1and C2act as equivalent resistors as seen from the expressions (3) and (4). Then, the voltage amplification circuit2can be considered as an equivalent circuit like a circuit shown inFIG. 4C.

When the output voltage Vout at this time is represented by Vin, Expression (5) holds. The output voltage Vout is represented by a capacitance ratio between the capacitors C1and C2.

In the manner, assuming that the capacitor C2is used as a reference capacitor, for example, a capacitor whose variation is to be detected is connected to the capacitor C1. This makes it possible to detect a variation in capacitance as a voltage.

Note that an integrator that uses a switched capacitor is disclosed in Japanese Unexamined Patent Application Publication No. 2003-203195. A technique in which a low-pass filter is connected in cascade with a switched capacitor filter is disclosed in Japanese Unexamined Patent Application Publication No. 58-198918.

SUMMARY

The present inventor has found a problem as described below. The output voltage Vout of the voltage amplification circuit2ofFIGS. 4A and 4Bhas no relation with the switching frequency Fs as shown by the expression (5). However, since the switches SW1, SW2, and SW3are repeatedly switched in an actual circuit operation, the output terminal Vout of the operational amplifier OP1repeats a connection or an open state with respect to the capacitor C2. Therefore, noise of the switching frequency Fs (hereafter, referred to as switching noise Ns) is superimposed in the same manner as in Japanese Unexamined Patent Application Publication No. 58-198918.

Thus, as shown inFIGS. 5A and 5B, it is necessary to insert a low-pass filter LPF1that includes a resistor R3and a capacitor C3between the output terminal of the operational amplifier OP1and the output terminal Vout to remove the switching noise Ns. In this case, however, it is necessary to increase the order of the low-pass filter LPF1or to increase the driving ability of the output of the operational amplifier OP1to sufficiently remove the switching noise Ns. However, this causes an increase in circuit size or current consumption of the operational amplifier OP1.

A first exemplary aspect of the present invention is a switched capacitor circuit including: an operational amplifier; a first capacitor; a first switch that charges the first capacitor by connecting the first capacitor between an inverting input terminal and an output terminal of the operational amplifier, and discharges the first capacitor by disconnecting the first capacitor between the inverting input terminal and the output terminal of the operational amplifier in a predetermined period; and a first output terminal that outputs an output voltage of the switched capacitor circuit, wherein after a predetermined period from a time when the first switch connects the first capacitor between the inverting input terminal and the output terminal of the operational amplifier, the first output terminal and the output terminal of the operational amplifier are connected to each other.

A second exemplary aspect of the present invention is a switched capacitor circuit that amplitudes an input voltage and outputs at an first output terminal, including: an operational amplifier having a non-inverting terminal receiving the input voltage, an inverting terminal connected with a first node, and an output terminal connected with a second node; a first capacitor connected between a third node and a fourth node; a second capacitor connected between a fifth node and a ground terminal; a third capacitor connected between a sixth node and the ground terminal; a low-pass filter connected between the sixth node and the first output terminal; a first switch that switches a connection between the first node and the third node, or a connection between the third node and the ground terminal in a first predetermined period; a second switch that operates in synchronization with the first switch and switches a connection between the second node and the fourth node, or a connection between the fourth node and the ground terminal in the first predetermined period; a third switch that connects the second node with the sixth node from an open state after a second predetermined period from a time when the second switch connects the second node and the fourth node; and a fourth switch that switches a connection between the first node and the fifth node, or a connection between the fifth node and the ground terminal in the first predetermined period.

In the switched capacitor circuit according to the first exemplary aspect of the present invention, the first switch connects the output terminal of the switched capacitor circuit and the output terminal of the operational amplifier after a predetermined time after the first switch connects the first capacitor between the inverting input terminal and output terminal of the operational amplifier. As a result, the noise which is generated during switching of the first switch and output from the operational amplifier is attenuated, and when the output voltage of the operational amplifier reaches a predetermined value, the output terminal of the switched capacitor circuit and the output terminal of the operational amplifier can be connected together. This prevents transmission of the noise to the output terminal of the switched capacitor circuit. Therefore, it is possible to lower the order of the low-pass filter for attenuating the noise, and there is no need to use a high-performance operational amplifier which has higher power consumption.

The switched capacitor circuit according to an exemplary aspect of the present invention can remove the switching noise without increasing the order of the low-pass filter and without increasing the current consumption of the operational amplifier.

DETAILED DESCRIPTION

An exemplary embodiment of the present invention will be described in detail below with reference to the accompanying drawings. In this exemplary embodiment, a switched capacitor circuit according to the present invention is applied to a voltage amplification circuit100.

FIGS. 1A to 1Ceach show an exemplary configuration and operation of the voltage amplification circuit100in accordance with this exemplary embodiment. As shown inFIGS. 1A to 1C, the voltage amplification circuit100includes an operational amplifier OP1, capacitors C1, C2, and C4, switches SW1to SW4, a low-pass filter LPF1, an input terminal Vin, and an output terminal Vout.

The low-pass filter LPF1includes a capacitor C3and a resistor R3.

The operational amplifier OP1has a non-inverting input terminal connected to the input terminal Vin, an inverting input terminal connected to a node N1, and an output terminal connected to a node N2. Hereinafter, a voltage output from the output terminal of the operational amplifier OP1is represented by Vop.

The switch SW1has a terminal “a” connected to one of terminals of the capacitor C1, a terminal “b” connected to the node N1, and a terminal “c” connected to a ground terminal GND. The switch SW1connects between the terminal “a” and the terminal “b”, or between the terminal “a” and the terminal “c” according to a control signal S1. For instance, when the control signal S1of a low level is input, the terminal “a” and terminal “b” are connected. Moreover, when the control signal S1of a high level is input, the terminal and terminal “c” are connected.

The capacitor C1has one terminal connected to the terminal “a” of the switch SW1and the other terminal connected to the ground terminal GND.

The switch SW2has a terminal “a” connected to one terminal of the capacitor C2, a terminal “b” connected to the node N1, and a terminal “c” connected to the ground terminal GND. The switch SW2connects between the terminal “a” and the terminal “b”, or between the terminal “a” and the terminal “c” according to a control signal S2. For instance, when the control signal S2of the low level is input, the terminal “a” and terminal “b” are connected. Moreover, when the control signal S2of the high level is input, the terminal “a” and terminal “c” are connected.

The capacitor C2has one terminal connected to the terminal “a” of the switch SW2and the other terminal connected to the terminal of the switch SW3.

The switch SW3has a terminal “a” connected to the other terminal of the capacitor C2, a terminal “b” connected to the node N2, and a terminal “c” connected to the ground terminal GND. The switch SW3connects between the terminal “a” and the terminal “b”, or between the terminal “a” and the terminal “c” according to a control signal S3. For instance, when the control signal S3of the low level is input, the terminal “a” and terminal “b” are connected. Moreover, when the control signal S3of the high level is input, the terminal “a” and terminal “c” are connected.

The switch SW4has a terminal “a” connected to the node N2, a terminal “b” connected to a node N3. A terminal “c” of the switch SW4is open. The switch SW4connects between the terminal “a” and the terminal “b”, or between the terminal “a” and the terminal “c” according to a control signal S4. For instance, when the control signal S4of the low level is input, the terminal “a” and terminal “b” are connected. Moreover, when the control signal S4of the high level is input, the terminal “a” and terminal “c” are connected.

The capacitor C4has one terminal connected to the node N3and the other terminal connected to the ground terminal GND.

The resistor R3has one terminal connected to the node N3and the other terminal connected to the output terminal Vout.

The capacitor C3has one terminal connected to the output terminal Vout and the other terminal connected to the ground terminal GND.

An operation of the voltage amplification circuit100is described with reference toFIGS. 1A to 1CandFIG. 2.FIG. 2is a timing diagram that shows the operation of the voltage amplification circuit100. Note that a circuit unit110shown inFIGS. 1A to 1Cis basically similar in configuration to the voltage amplification circuit2. Therefore, the operation of the circuit unit110is also basically similar to that described above with reference toFIGS. 4A to 4C. Therefore, an explanation of a detailed operation of the circuit unit110is omitted, and operation different from that of the voltage amplification circuit2is mainly described in this exemplary embodiment.

First, the control signals S1to S4are all at a high level before a time t1, as shown inFIG. 2. As shown inFIG. 1A, the terminal “a” and the terminal “c” of each of the switches SW1to SW4are connected.

Next, the control signals S1to S3are at a low level at the time t1, as shown inFIG. 2. As shown inFIG. 1B, the terminal “a” and the terminal “b”of each of the switches SW1to SW3are connected. Here, at the time t1, the output terminal of the operational amplifier OP1is electrically connected with the non-inverting input terminal via the capacitor C2from an open state. Therefore, as shown inFIG. 2, the voltage Vop output from the output terminal of the operational amplifier OP1has a disturbed waveform. Thus, a similar switching noise Ns similar to that described above with reference toFIGS. 4A and 4Bis generated.

However, because the control signal S4remains at the high level, the terminal “a” and the terminal “c” of the switch SW4are connected. Therefore, the low-pass filter LPF1and the node N2are electrically disconnected, thereby preventing the switching noise Ns from being transmitted to the low-pass filter LPF1.

Next, at a time t2after a predetermined period from the time t1inFIG. 2, the control signal S4also becomes low level. Therefore, as shown inFIG. 1C, the terminal “a” and the terminal “b” of each of the switches SW1to SW4are connected. Accordingly, the node N2and N3are electrically connected, and the voltage Vop output from the output terminal of the operational amplifier OP1is transmitted to the low-pass filter LPF1. At the time t2, the voltage Vop has no such a disturbed waveform as described above. Thus, no waveform disturbance occurs in the output voltage Vout output from the output terminal Vout of the voltage amplification circuit100.

Next, all the control signals S1to S4become high level at a time t3inFIG. 2. Therefore, the terminal “a” and the terminal “c” of each of the switches SW1to SW4are connected, thereby restoring the configuration as shown inFIG. 1A.

Then, the voltage amplification circuit100repeats the operation described above. This makes it possible to detect a variation in capacitance as a voltage, assuming the capacity C2is used as a reference capacitor and a capacitor whose variation is to be detected is connected to the capacitor C1.

Here, in the voltage amplification circuit2that uses the switched capacitor circuit of the related art, the switching noise is superimposed on the output voltage of the operational amplifier OP1and output. It is necessary to connect the low-pass filter LPF1shown inFIG. 5to remove this switching noise. In this case however, it is necessary to increase the amount of attenuation of the low-pass filter LPF1. Therefore, there is a need to increase the size of the resistor R3and the capacitor C3that constitute the low-pass filter LPF1, or to increase the order of the low-pass filter LPF1. This results in increased circuit size.

Moreover, it is necessary to increase a response speed of the operational amplifier OH when the amount of attenuation of the low-pass filter LPF1cannot be increased, and to rapidly settle the waveform disturbance of the output voltage of the operational amplifier OP1. This requires an increase in driving ability of the output of the operational amplifier OP1, leading to an increase in current consumption of the operational amplifier OP1.

Here, as shown inFIGS. 1B and 2, the terminal “a” of the switch SW4is connected with the terminal “c” thereof, and the node N2and N3are electrically disconnected in the voltage amplification circuit100that uses the switched capacitor circuit of this exemplary embodiment, during a period in which the waveform of the output voltage Vop of the operational amplifier OP1is disturbed. Then, as shown inFIG. 1C, the terminal “a” of the switch SW4is connected with the terminal “b” thereof after the output voltage Vop of the operational amplifier OP1reaches a predetermined voltage, and the nodes N2and N3are electrically connected. This prevents a great disturbance in waveform of the output voltage Vop of the operational amplifier OP1from being transmitted to the low-pass filter LPF1.

Consequently, the amount of attenuation of the low-pass filter LPF1can be reduced, so that the capacitor C3and the resistor R3that constitute the low-pass filter LPF1can be reduced in size. Alternatively, the order of the low-pass filter can be lowered, which makes it possible to employ a one-order low-pass filter like the low-pass filter LPF1. This results in suppressing an increase in the size of the voltage amplification circuit100.

Ideally, it is also possible to omit the low-pass filter LPF1. However, it is necessary to leave the low-pass filter LPF1because, in practice, a waveform disturbance occurs during switching of the switch SW4. Further, the capacity C4is required to maintain the input voltage of the low-pass filter LPF1while the switch SW4is in the open state.

Moreover, an output response of the operational amplifier OP1can be suppressed in this exemplary embodiment. This means that the time t2is delayed. In other word, a time period between the time t1and the time t2can be increased to such extent as to settle the waveform disturbance of the voltage Vop. Therefore, it is possible to suppress a bias current of an output stage of the operational amplifier OP1, and to suppress the current consumption of the operational amplifier OP1. Furthermore, a time constant in phase compensation can be sufficiently increased, thereby stabilizing the circuit.

Note that the present invention is not limited to the exemplary embodiments described above.

While the invention has been described in terms of several exemplary embodiments, those skilled in the art will recognize that the invention can be practiced with various modifications within the spirit and scope of the appended claims and the invention is not limited to the examples described above.