Image sensor having high pixel integration

An image sensor includes a substrate that has a first pixel region and a second pixel region and a microlens layer on a first surface of the substrate. The microlens layer includes a first lens pattern on the first pixel region of the substrate; and a second lens pattern on the second pixel region of the substrate. A width of the first pixel region is greater than a width of the second pixel region, and a height of the first lens pattern is greater than a height of the second lens pattern.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. nonprovisional application claims priority under 35 U. S. C. § 119 to Korean Patent Application No. 10-2020-0128518 filed on Oct. 6, 2020 in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND

The present disclosure relates to an image sensor, and more particularly, to a microlens layer of an image sensor and a method of forming the same.

2. Description of Related Art

An image sensor is a device to convert optical images into electrical signals. An image sensor may be classified into a charge coupled device (CCD) type and a complementary metal oxide semiconductor (CMOS) type. A CMOS type image sensor is abbreviated to CIS (CMOS image sensor). The CIS has a plurality of two-dimensionally arranged pixels. Each of the pixels includes a photodiode. The photodiode serves to convert incident light into electrical signals.

SUMMARY

It is an aspect to provide an image sensor with improved image quality.

According to an aspect of some example embodiments, there is provided an image sensor comprising a substrate that has a first pixel region and a second pixel region; and a microlens layer on a first surface of the substrate. The microlens layer may include a first lens pattern on the first pixel region of the substrate; and a second lens pattern on the second pixel region of the substrate. A width of the first pixel region may be greater than a width of the second pixel region. A height of the first lens pattern may be greater than a height of the second lens pattern.

According to another aspect of some example embodiments, there is provided an image sensor comprising a substrate that has a first pixel region and a second pixel region whose width is different from a width of the first pixel region; a plurality of photoelectric conversion regions that are correspondingly in the first and second pixel regions of the substrate; and a microlens layer on a first surface of the substrate and covering the first and second pixel regions of the substrate. The microlens layer may include a first lens pattern on the first pixel region of the substrate, the first lens pattern having a first curved surface; and a second lens pattern on the second pixel region of the substrate, the second lens pattern having a second curved surface. At a level of a location where the first curved surface meets the second curved surface, a width of the first lens pattern may be greater than a width of the second lens pattern. A height of the first lens pattern may be greater than a height of the second lens pattern.

According to yet another aspect of some example embodiments, there is provided an image sensor comprising a substrate that has a first pixel region and a second pixel region; a plurality of photoelectric conversion regions that are correspondingly in the first and second pixel regions of the substrate; an isolation pattern in the substrate and between the photoelectric conversion regions; a color filter on a first surface of the substrate; a microlens layer on the color filter; a first gate pattern on the first pixel region of the substrate and on a second surface of the substrate; a second gate pattern on the second pixel region of the substrate and on the second surface of the substrate; and a wiring layer on the second surface of the substrate and covering the first and second gate patterns. The substrate may include a first floating diffusion region on the first pixel region of the substrate; and a second floating diffusion region on the second pixel region of the substrate. The microlens layer may include a first lens pattern on the first pixel region of the substrate; a second lens pattern on the second pixel region of the substrate; and a planarized layer between the color filter and the first lens pattern and between the color filter and the second lens pattern. The first and second lens patterns may be on the color filter. A width of the first pixel region may be greater than a width of the second pixel region. A height of the first lens pattern may be greater than a height of the second lens pattern.

DETAILED DESCRIPTION

In this description, like reference numerals may indicate like components. The drawings are not necessarily to scale and some dimensions may be exaggerated to improve legibility and ease of description. The following will now describe an image sensor according to some example embodiments.

FIG.1illustrates a circuit diagram showing a pixel of an image sensor according to some example embodiments.

Referring toFIG.1, each of pixels of an image sensor may include a photoelectric conversion region PD, a transfer transistor Tx, a source follower transistor Sx, a reset transistor Rx, and a selection transistor Ax. The transfer transistor Tx, the source follower transistor Sx, the reset transistor Rx, and the selection transistor Ax may respectively include a transfer gate TG, a source follower gate SG, a reset gate RG, and a selection gate AG.

The photoelectric conversion region PD may be a photodiode that includes an n-type impurity region and a p-type impurity region. A floating diffusion region FD may serve as a drain of the transfer transistor Tx. The floating diffusion region FD may also serve as a source of the reset transistor Rx. The floating diffusion region FD may be electrically connected to the source follower gate SG of the source follower transistor Sx. The source follower transistor Sx may be connected to the selection transistor Ax.

An operation of the image sensor will be explained below with reference toFIG.1. First, a power voltage VDDmay be applied to a drain of the reset transistor Rx and a drain of the source follower transistor Sx under a light-blocked state, such that the reset transistor Rx may be turned on to discharge charges that remain on the floating diffusion region FD. Thereafter, when the reset transistor Rx is turned off and external light is incident on the photoelectric conversion region PD, electron-hole pairs may be generated from the photoelectric conversion region PD. Holes may be transferred to and accumulated on a p-type impurity region of the photoelectric conversion region PD, and electrons may be transferred to and accumulated on an n-type impurity region of the photoelectric conversion region PD. When the transfer transistor Tx is turned on, charges such as electrons and holes may be transferred to and accumulated on the floating diffusion region FD. A gate bias of the source follower transistor Sx may change in proportion to an amount of the accumulated charges, and this may bring about a variation in source potential of the source follower transistor Sx. In this case, when the selection transistor Ax is turned on, charges may be read out as signals transmitted through a column line.

A wiring line may be electrically connected to one or more of the transfer gate TG, the source follower gate SG, the reset gate RG, and the selection gate AG. The wiring line may be configured to apply the power voltage VDDto the drain of the reset transistor Rx or the drain of the source follower transistor Sx. The wiring line may include a column line connected to the selection transistor Ax. The wiring line may be a conductive structure830which will be discussed below inFIG.2B.

FIG.1shows by way of example a pixel that includes one photoelectric conversion region PD and four transistors Tx, Rx, Ax, and Sx, but example embodiments are not limited thereto. For example, in some embodiments, the pixel may be provided in plural, and neighboring pixels may share one of the reset transistor Rx, the source follower transistor Sx, and the selection transistor Ax. Therefore, the image sensor may increase in integration.

FIG.2Aillustrates a plan view showing an image sensor according to some example embodiments.FIG.2Billustrates a cross-sectional view taken along line I-II ofFIG.2A.

Referring toFIGS.2A and2B, an image sensor may include a substrate100, an isolation pattern210, a device isolation pattern220, a first gate pattern G1, a second gate pattern G2, a wiring layer800, a dielectric layer400, a protective layer430, a fence pattern450, color filters CF, and a microlens layer500.

When viewed in plan view, the substrate100may include a pixel array area and an edge area. When viewed in plan view, the pixel array area may be disposed on a central portion of the substrate100. The edge area may surround the pixel array area. Pad terminals (not shown) may be provided on the edge area. The pixel array area may include a plurality of unit pixel groups UPG, and each of the unit pixel groups UPG may include a first pixel region PX1and a second pixel region PX2. The unit pixel groups UPG may constitute an array. The pixels discussed with reference toFIG.1may be correspondingly formed on the first and second pixel regions PX1and PX2of the substrate100. For example, components of the pixel may be provided on each of the first and second pixel regions PX1and PX2. Each of the first and second pixel regions PX1and PX2may output a corresponding photoelectric conversion signal from incident light. According to some example embodiments, the first pixel region PX1may serve as a primary pixel, and the second pixel region PX2may serve as a subsidiary pixel. For example, when the image sensor operates, on each of the unit pixel groups UPG, a photoelectric conversion signal that is output from the second pixel region PX2may be used to correct a photoelectric conversion signal that is output from the first pixel region PX1. Therefore, the image sensor may increase in optical properties and sensing accuracy. The second pixel region PX2, however, is not limited to the subsidiary pixel function mentioned above.

A plurality of first pixel regions PX1may be two-dimensionally arranged in rows and columns. The rows may be parallel to a first direction D1. The columns may be parallel to a second direction D2. The first pixel regions PX1may be arranged in a first diagonal direction D3. The first pixel regions PX1may be arranged in a second diagonal direction D4. In this description, the first direction D1may be parallel to a first surface100aof the substrate100. The second direction D2may be parallel to the first surface100aand different from the first direction D1. For example, in some embodiments, the second direction D2may be substantially orthogonal to the first direction D1. The first diagonal direction D3may be parallel to the first surface100aof the substrate100, and may intersect the first and second directions D1and D2. For example, in some embodiments, the first diagonal direction D3and the first direction D1may make an angle of about 45 degrees with each other, and the first diagonal direction D3and the second direction D2may make an angle of about 45 degrees with each other. The second diagonal direction D4may be parallel to the first surface100a, and may intersect the first direction D1, the second direction D2, and the first diagonal direction D3. For example, in some embodiments, the second diagonal direction D4may be substantially orthogonal to the first diagonal direction D3. A third direction D5may intersect the first direction D1, the second direction D2, the first diagonal direction D3, and the second diagonal direction D4. For example, in some embodiments, the third direction D5may be substantially perpendicular to the first surface100aof the substrate100.

In some embodiments, each of the first pixel regions PX1may have an octagonal shape when viewed in plan view. Each of the first pixel regions PX1may have a first width W11. The first width W11may be measured in the first direction D1, and may be a width at the first surface100aof the substrate100. The first width W11may correspond to an interval between two opposing sidewalls of isolation patterns210which will be discussed below.

When viewed in plan view, each of a plurality of second pixel regions PX2may be surrounded by four adjacent first pixel regions PX1. When viewed in plan view, the second pixel regions PX2may be two-dimensionally arranged along the first and second directions D1and D2. When viewed in the first direction D1, the second pixel regions PX2may be correspondingly disposed between the first pixel regions PX1. In such a configuration, the first pixel regions PX1and the second pixel regions PX2may be alternately disposed in the first direction D1. When viewed in the second direction D2, the second pixel regions PX2may be correspondingly disposed between the first pixel regions PX1. In such a configuration, the first pixel regions PX1and the second pixel regions PX2may be alternately disposed in the second direction D2.

In some embodiments, each of the second pixel regions PX2may have a tetragonal shape when viewed in plan view. Sizes of the second pixel regions PX2may be less than sizes of the first pixel regions PX1. For example, each of the second pixel regions PX2may have a second width W12. The second width W12may be less than the first width W11. The second width W12may be measured in the first direction D1. The second width W12may correspond to an interval between two opposing sidewalls of isolation patterns210which will be discussed below, and may be measured on the first surface100aof the substrate100. In addition, widths of the second pixel regions PX2in the second direction D2may be less than widths of the first pixel regions PX1in the second direction D2. In this description, widths of two components may be compared with each other in the same direction at the same level.

According to some example embodiments, planar shapes and the first widths W11of the first pixel regions PX1may be adjusted, and planar widths and the second widths of the second pixel regions PX2may be adjusted in order that that the first and second pixel regions PX1and PX2may be disposed at high integration density. Therefore, the image sensor may increase in optical properties.

The substrate100may have a first surface100aand a second surface100bthat face each other. The first surface100amay be a rear surface of the substrate100, and the second surface100bmay be a front surface of the substrate100. The substrate100may receive light incident on the first surface100a. The substrate100may be a semiconductor substrate, such as a silicon substrate or a silicon-on-insulator (SOI) substrate. The semiconductor substrate may be, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The substrate100may further include a III-group element. The III-group element may be an impurity having a first conductivity type. The substrate100may include first conductivity type impurities and may thus have the first conductivity type. For example, the first conductivity type impurities may include p-type impurities, such as one or more of aluminum (Al), boron (B), indium (In), and gallium (Ga).

The substrate100may include first photoelectric conversion regions PD1and second photoelectric conversion regions PD2. The first and second photoelectric conversion regions PD1and PD2may be interposed between the first and second surfaces100aand100bof the substrate100. The substrate100may include the first photoelectric conversion regions PD1provided on corresponding first pixel regions PX1. The substrate100may also include the second photoelectric conversion regions PD2provided on corresponding second pixel regions PX2. The first and second photoelectric conversion regions PD1and PD2may further include a V-group element. The V-group element may be an impurity having a second conductivity type. The first and second photoelectric conversion regions PD1and PD2may each be a zone where the substrate100is doped with second conductivity type impurities. In some embodiments, the second conductivity type impurities may have a conductivity type opposite to that of the first conductivity type impurities. The second conductivity type impurities may include n-type impurities, such as one or more of phosphorus, arsenic, bismuth, and antimony. The first and second photoelectric conversion regions PD1and PD2may be disposed deep beneath the second surface100bof the substrate100.

Each of the first and second photoelectric conversion regions PD1and PD2may have a same function and a same role as the function and role of the photoelectric conversion region PD discussed in the example inFIG.1. In contrast, volumes of the second photoelectric conversion regions PD2may be less than volumes of the first photoelectric conversion regions PD1. For example, the widths of the second photoelectric conversion regions PD2may be less than the widths of the first photoelectric conversion regions PD1. Charge storage capabilities of the second photoelectric conversion regions PD2may be less than charge storage capabilities of the first photoelectric conversion regions PD1. The following will discuss a single first pixel region PX1and a single second pixel region PX2by way of example. However, it will be understood that the description applies equally to other first pixel regions PX1and second pixel regions PX2of the image sensor.

The substrate100may be provided therein with the isolation pattern210that defines the first and second pixel regions PX1and PX2. For example, the isolation pattern210may be provided between the first and second pixel regions PX1and PX2of the substrate100. The isolation pattern210may be a pixel isolation pattern. The isolation pattern210may be provided in a first trench191, and the first trench191may be recessed from the second surface100bof the substrate100. In some embodiments, the isolation pattern210may be a deep trench isolation (DTI) layer. The isolation pattern210may further penetrate the first surface100aof the substrate100. The isolation pattern210may have, at a top surface of the isolation pattern210, a width W21less than a width W22at a bottom surface of the isolation pattern210. The top surface of the isolation pattern210may be coplanar with the first surface100aof the substrate100. The bottom surface of the isolation pattern210may stand opposite to the top surface of the isolation pattern210.

The isolation pattern210may include a dielectric isolation pattern211, a conductive isolation pattern215, and a capping pattern217. The dielectric isolation pattern211may be provided along a sidewall of the first trench191. The dielectric isolation pattern211may include, for example, one or more of a silicon-based dielectric material (e.g., silicon nitride, silicon oxide, and silicon oxynitride) and a high-k dielectric material (e.g., hafnium oxide and aluminum oxide). Alternatively, the dielectric isolation pattern211may include a plurality of layers, which layers may include different materials from each other. The dielectric isolation pattern211may have a refractive index less than that of the substrate100. Accordingly, a crosstalk issue may be prevented or reduced between the first and second pixel regions PX1and PX2of the substrate100.

The conductive isolation pattern215may be provided in the dielectric isolation pattern211. The dielectric isolation pattern211may be interposed between the conductive isolation pattern215and the substrate100. When the image sensor operates, the conductive isolation pattern215may be supplied with a negative bias voltage to prevent the occurrence of dark current between the isolation pattern210and the substrate100. The dielectric isolation pattern211may separate the conductive isolation pattern215from the substrate100. Therefore, the conductive isolation pattern215may be electrically divided from the substrate100. The conductive isolation pattern215may include a crystalline semiconductor material, such as polysilicon. The conductive isolation pattern215may further include dopants, which dopants may include first conductivity type impurities or second conductivity type impurities. For example, the conductive isolation pattern215may include doped polysilicon. The conductive isolation pattern215may have a bottom surface that is upwardly convex. However, the bottom surface of the conductive isolation pattern215is not limited to the shape mentioned above, but may be variously changed.

The capping pattern217may be disposed on the bottom surface of the conductive isolation pattern215, and may cover a lower sidewall of the dielectric isolation pattern211. The capping pattern217may fill a lower portion of the first trench191. The dielectric isolation pattern211may further extend into a gap between the substrate100and the capping pattern217. The capping pattern217may include a silicon-containing dielectric material, such as one or more of silicon oxide, tetraethyl orthosilicate (TEOS), and silicon oxynitride. Alternatively, the isolation pattern210may not include the capping pattern217, and the bottom surface of the conductive isolation pattern215may be located at substantially the same level as that of the second surface100bof the substrate100.

The first gate pattern G1and the second gate pattern G2may be disposed on the second surface100bof the substrate100. The first gate pattern G1may be provided on the first pixel region PX1. The second gate pattern G2may be provided on the second pixel region PX2. Each of the first and second gate patterns G1and G2may serve as a gate electrode for one of the transfer transistor Tx, the source follower transistor Sx, the reset transistor Rx, and the selection transistor Ax that are discussed above inFIG.1. For example, each of the first and second gate patterns G1and G2may include one of the transfer gate TG, the source follower gate SG, the reset gate RG, and the selection gate AG.

For simplicity of drawing,FIG.2Bdepicts that a single first gate pattern G1is disposed on the first pixel region PX1, but in some embodiments, a plurality of first gate patterns G1may be disposed on the first pixel region PX1. In addition, a plurality of second gate patterns G2may be disposed on the second pixel region PX2. The following will discuss a single first gate pattern G1and a single second gate pattern G2by way of example.

Each of the first and second gate patterns G1and G2may have a vertical gate structure or a buried gate structure. For example, each of the first and second gate patterns G1and G2may include a first part310and a second part320. The first part310of each of the first and second gate patterns G1and G2may protrude into the substrate100. The first part310may be a vertical segment and may have a major axis parallel to the third direction D5. The second part320may be disposed on the second surface100bof the substrate100. The second part320may be a horizontal segment. The second part320may be connected to the first part310. The second part320may include the same material as that of the first part310. The first and second gate patterns G1and G2may include metal, metal silicide, polysilicon, or any combination thereof. In this case, the polysilicon may include doped polysilicon.

A gate dielectric pattern340may be interposed between the substrate100and each of the first and second gate patterns G1and G2. The gate dielectric pattern340may include, for example, one or more of a silicon-based dielectric material (e.g., silicon oxide, silicon nitride, and silicon oxynitride) and a high-k dielectric material (e.g., hafnium oxide and aluminum oxide).

The substrate100may include a first floating diffusion region FD1and a second floating diffusion region FD2. The first floating diffusion region FD1may be provided in the first pixel region PX1and disposed on one side of the first gate pattern G1. The second floating diffusion region FD2may be provided in the second pixel region PX2and disposed on one side of the second gate pattern G2. The first and second floating diffusion regions FD1and FD2may be adjacent to the second surface100bof the substrate100. The first and second floating diffusion regions FD1and FD2may have bottom surfaces that are spaced apart from the first and second photoelectric conversion regions PX1and PX2, respectively. The first and second floating diffusion regions FD1and FD2may each be a zone doped with second conductivity type impurities (e.g., n-type impurities). Each of the first and second floating diffusion regions FD1and FD2may have substantially a same function and a same role as the function and role of the floating diffusion region FD discussed in the example ofFIG.1. For example, when the image sensor operates, the first floating diffusion region FD1may receive charges generated from the first photoelectric conversion region PD1. The second floating diffusion region FD2may receive charges generated from the second photoelectric conversion region PD2.

The substrate100may include an impurity region111. The impurity region111may be disposed in the substrate100on the first pixel region PX1. The impurity region111may be adjacent to the second surface100bof the substrate100. The impurity region111may have a bottom surface that is spaced apart from the first photoelectric conversion region PD1. Although not shown, in some embodiments, the impurity region111may further be disposed in the substrate100on the second pixel region PX2. The impurity region111may be a zone doped with second conductivity type impurities (e.g., n-type impurities). The impurity region111may be an active region. In this case, the active region may be a zone for operation of a transistor, and may include source/drain regions of the transistor discussed with reference toFIG.1. The transistor may include one of the source follower transistor Sx, the reset transistor Rx, and the selection transistor Ax that are discussed with reference toFIG.1.

The device isolation pattern220may be provided in the substrate100. The device isolation pattern220may define active regions. For example, the device isolation pattern220may define the impurity region111, the first floating diffusion region FD1, and the second floating diffusion region FD2. For example, the device isolation pattern220may be disposed in the substrate100on at least one side of one of the impurity region111, on one side of the first floating diffusion region FD1, and/or on one side of the second floating diffusion region FD2. The device isolation pattern220may be provided in a second trench192, and the second trench192may be recessed from the second surface100bof the substrate100. In some embodiments, the device isolation pattern220may be a shallow trench isolation (STI) layer. For example, the device isolation pattern220may have a height less than a height of the isolation pattern210. A portion of the device isolation pattern220may be connected to a sidewall of the dielectric isolation pattern211. The device isolation pattern220may include, for example, one or more of silicon oxide, silicon nitride, and silicon oxynitride.

The substrate100may include, on the first surface100a, the color filters CF. The color filters CF may be correspondingly disposed on the plurality of unit pixel groups UPG. The color filters CF may constitute color filter arrays. Each of the color filters CF may have a planar shape that corresponds to that of a corresponding unit pixel group UPG. Each of the color filters CF may include one of red, blue, and green filters.

Each of the color filters CF may be disposed on corresponding first and second pixel regions PX1and PX2of a corresponding unit pixel group UPG. Each of the color filters CF may vertically overlap the first photoelectric conversion region PD1and the second photoelectric conversion region PD2. Therefore, the color filter CF may be shared by the first photoelectric conversion region PD1and the second photoelectric conversion region PD2of a corresponding unit pixel group UPG. The first photoelectric conversion region PD1and the second photoelectric conversion region PD2of the corresponding unit pixel group UPG may output a photoelectric signal from light that passes through a single color filter CF. For a given unit pixel group UPG, a photoelectric conversion signal that is output from the second pixel region PX2may be used to correct a photoelectric conversion signal that is output from the first pixel region PX1.

The image sensor may further include the fence pattern450. The fence pattern450may be interposed between two neighboring color filters CF and separate the two neighboring color filters CF. For example, the fence pattern450may optically separate a plurality of color filters CF from each other. The fence pattern450may vertically overlap at least a portion of the isolation pattern210. The fence pattern450may include metal, metal nitride, or a low-refractive material. For example, the fence pattern450may include titanium or titanium nitride. The low-refractive material may include a polymer and nano-particles in the polymer, and may have dielectric properties. The nano-particles may include, for example, silica.

The image sensor may further include the dielectric layer400. The dielectric layer400may be interposed between the substrate100and the color filters CF and between the isolation pattern210and the fence pattern450. The dielectric layer400may be a backside dielectric layer. The dielectric layer400may include a bottom antireflective coating (BARC) layer. In some embodiments, the dielectric layer400may include a plurality of layers. For example, the dielectric layer400may include a fixed charge layer, a buried dielectric layer, a silicon nitride layer, and a capping layer that are stacked on the first surface100aof the substrate100. The fixed charge layer may include metal oxide, such as stacked aluminum and hafnium oxides. The buried dielectric layer may include tetraethyl orthosilicate (TEOS) or silicon oxide. The capping layer may include metal oxide, such as hafnium oxide. The dielectric layer400may exclude one or more of the fixed charge layer, the buried dielectric layer, the silicon nitride layer, and the capping layer.

The image sensor may further include the protective layer430. The protective layer430may be interposed between the dielectric layer400and the color filters CF and between the fence pattern450and the color filters CF. For example, the protective layer430may include aluminum oxide or hafnium oxide. The protective layer430may protect the first and second photoelectric conversion regions PD1and PD2from external environment.

The microlens layer500may be disposed on the first surface100aof the substrate100, and may cover the plurality of unit pixel groups UPG. For example, the microlens layer500may be disposed on the color filters CF. The microlens layer500may include a planarized layer530, a first lens pattern510, and a second lens pattern520. The planarized layer530of the microlens layer500may be disposed on the color filters CF.

The first lens pattern510may be disposed on the planarized layer530of the microlens layer500. The first lens pattern510may be provided on the first pixel region PX1, and may be disposed on a position that corresponds to a position of the first photoelectric conversion region PD1. Accordingly, in the image sensor, a plurality of the first lens patterns510may be provided corresponding respectively to the first pixel regions PX1. The first lens pattern510may have a first surface510aand a bottom surface. The bottom surface of the first lens pattern510may be an imaginary surface, which imaginary surface may be directed toward the substrate100. The first surface510amay be a top surface of the first lens pattern510, which first surface510amay not be directed toward the substrate100. The first surface510aof the first lens pattern510may protrude away from the first surface100aof the substrate100. The first surface510aof the first lens pattern510may be a curved surface. For example, in some embodiments, the first lens pattern510may have a hemispheric cross-section. The first lens pattern510may focus light on the first photoelectric conversion region PD1. A curvature of the first surface510amay adjust a focus of the first lens pattern510. Therefore, it may be possible to adjust an amount of light incident on the first photoelectric conversion region PD1. According to some example embodiments, the first surface510aof the first lens pattern510and the first surface100aof the substrate100may have therebetween a maximum interval A that is about 2.5 to about 3.5 times a first radius. In this description, the first radius may be a radius of an imaginary hemisphere (or an imaginary circle) that is hypothetically formed by at least three points selected from points on the first surface510aof the first lens pattern510. The maximum interval A may correspond to a spacing distance between an uppermost portion on the first surface510aof the first lens pattern510and the first surface100aof the substrate100. When the maximum interval A between the first surface510aof the first lens pattern510and the first surface100aof the substrate100is less than about 2.5 times the first radius, the first photoelectric conversion region PD1may receive a reduced amount of incident light. When the maximum interval A between the first surface510aof the first lens pattern510and the first surface100aof the substrate100is greater than about 3.5 times the first radius, a focus of incident light may be directed toward the device isolation pattern220or the first gate pattern G1. In this case, light may be scattered by the device isolation pattern220or the first gate pattern G1. According to some example embodiments, because the maximum interval A between the first surface510aof the first lens pattern510and the first surface100aof the substrate100is in a range of about 2.5 times to about 3.5 times the first radius, the image sensor may increase in optical properties.

The first lens pattern510may have a first lens width W1and a first height H1. The first lens width W1may be a width at the bottom surface of the first lens pattern510. The bottom surface of the first lens pattern510may be an imaginary surface, which may be located at a same level as a level of a location where the first surface510aof the first lens pattern510meets a second surface520aof the second lens pattern520. The first height H1may be a spacing distance between the uppermost portion of the first surface510aand the bottom surface of the first lens pattern510. For example, the first height H1may be a maximum height of the first lens pattern510. The first height H1may correspond to a difference between a maximum level and a minimum level of the first surface510aof the first lens pattern510. The first height H1may be about 30% to about 50% of the first lens width W1. When the first height H1is less than about 30% of the first lens width W1or greater than about 50% of the first lens width W1, the first photoelectric conversion region PD1may receive a reduced amount of incident light. Since the first height H1is about 30% to about 50% of the first lens width W1, the maximum interval A between the first surface510aof the first lens pattern510and the first surface100aof the substrate100may fall within in a range of about 2.5 times to about 3.5 times the first radius.

The second lens pattern520of the microlens layer500may be disposed on the planarized layer530and placed laterally to the first lens pattern510. The second lens pattern520may be provided on the second pixel region PX2, and may be disposed on a position that corresponds to a position of the second photoelectric conversion region PD2. Accordingly, in the image sensor, a plurality of the second lens patterns520may be provided corresponding respectively to the second pixel regions PX2. The second lens pattern520may have a second surface520aand a bottom surface. The second surface520aof the second lens pattern520may not be directed toward the substrate100. The second surface520aof the second lens pattern520may protrude away from the first surface100aof the substrate100. The second surface520aof the second lens pattern520may be a curved surface. For example, in some embodiments, the first second pattern520may have a hemispheric cross-section. The second lens pattern520may focus light on the second photoelectric conversion region PD2. A curvature of the second surface520aof the second lens pattern520may adjust an amount of light incident on the second photoelectric conversion region PD2. In some embodiments, the curvature of the second surface520aof the second lens pattern520may be different from the curvature of the first surface510aof the first lens pattern510, but example embodiments are not limited thereto.

The second lens pattern520may have a second lens width W2and a second height H2. The second lens width W2may be a width at the bottom surface of the second lens pattern520. The bottom surface of the second lens pattern520may be an imaginary surface and may be located at a same level as a level of a location where the first surface510aof the first lens pattern510meets the second surface520aof the second lens pattern520. The bottom surface of the second lens pattern520may be directed toward the substrate100. The second lens width W2may be less than the first lens width W1. For example, the second lens width W2may be about 30% to about 50% of the first lens width W1. The second height H2may be a maximum height of the second lens pattern520. The second height H2may be a spacing distance between an uppermost portion of the second surface520aof the second lens pattern520and the bottom surface of the second lens pattern520. The second height H2may correspond to a difference between a maximum level and a minimum level of the second surface520aof the second lens pattern520. The second height H2may be less than the first height H1. For example, the second height H2may be about 20% to about 30% of the first height H1. According to some example embodiments, because the second height H2is about 20% to about 30% of the first height H1, and because the second lens width W2is about 30% to about 50% of the first lens width W1, the second photoelectric conversion region PD2may receive an increased amount of incident light, and the image sensor may have high integration of the first and second pixel regions PX1and PX2.

As shown inFIG.2A, when viewed in the first direction D1, a plurality of second lens patterns520may be correspondingly disposed between the first lens patterns510. For example, the first lens patterns510and the second lens patterns520may be disposed alternately with each other in the first direction D1. When viewed in the second direction D2, the second lens patterns520may be correspondingly disposed between the first lens patterns510. The first lens patterns510may be arranged along the first and second diagonal directions D3and D4. When viewed in plan view, each of the plurality of second lens patterns520may be surrounded by four neighboring first lens patterns510. Since the second lens width W2is less than the first lens width W1, the second lens patterns520may be disposed on zones (or non-occupied zones) of the image sensor that are not occupied by the first lens patterns510. Therefore, the first and second pixel regions PX1and PX2may be disposed at high integration density. The non-occupied zones that are not occupied by the first lens patterns510may include the second pixel regions PX2.

The planarized layer530of the microlens layer500may be interposed between the substrate100and the first lens pattern510and between the substrate100and the second lens pattern520. The planarized layer530may have a third height H3. The third height H3may be a spacing distance between a top surface and a bottom surface of the planarized layer530, which top surface of the planarized layer530may be an imaginary surface and may be located at a same level as a level of locations where the first lens patterns510meet the second lens patterns520. The third height H3may be about 0.8 times to about 1.5 times the first height H1. Since the third height H3is equal to or greater than about 0.8 times the first height H1, the focus of the first lens pattern510may not be provided on the planarized layer530, the color filter CF, or the dielectric layer400. Since the third height H3is equal to or less than about 1.5 times the first height H1, the device isolation pattern220may be prevented from scattering light that passes through the first lens pattern510. The first and second lens patterns510and520may be integrally formed with the planarized layer530and connected to each other with no boundary therebetween.

The microlens layer500may be transparent to allow light to pass therethrough. The microlens layer500may include an organic material, such as a polymer. For example, the microlens layer500may include a photoresist material or a thermosetting resin.

The image sensor may further include a coating layer (not shown). The coating layer (not shown) may conformally cover the first surface510aof the first lens pattern510and the second surface520aof the second lens pattern520. The coating layer may include an organic material and may be transparent.

The wiring layer800may be disposed on the second surface100bof the substrate100. The wiring layer800may include a first dielectric layer810, a plurality of second dielectric layers820, and a conductive structure830. The first dielectric layer810may cover the second surface100bof the substrate100, a sidewall of the first gate pattern G1, and a sidewall of the second gate pattern G2. The plurality of second dielectric layers820may be stacked on the first dielectric layer810. The first and second dielectric layers810and820may include a silicon-based dielectric material, such as one or more of silicon oxide, silicon nitride, and silicon oxynitride.

The conductive structure830may be provided in the first and second dielectric layers810and820. The conductive structure830may include a contact plug part, a line part, and a via part. The contact plug part of the conductive structure830may be provided in the first dielectric layer810and electrically connected to one of the first floating diffusion region FD1, the second floating diffusion region FD2, the first gate pattern G1, and the second gate pattern G2. The line part of the conductive structure830may be interposed between two neighboring ones of the first and second dielectric layers810and820. The line part may be connected to the contact plug part. The via part of the conductive structure830may penetrate at least one of the second dielectric layers820and may be connected to the line part.

The wiring layer800may further include a capacitor840. The capacitor840may include a first electrode pattern831, a second electrode pattern832, and a dielectric layer820D. The first electrode pattern831may be provided in the second dielectric layers820. The first electrode pattern831may be electrically connected through the conductive structure830to the second floating diffusion region FD2. The second electrode pattern832may be provided in the second dielectric layers820and spaced apart from the first electrode pattern831. The first and second electrode patterns831and832may include metal or conductive polymer. For example, the first electrode pattern831may be one of line parts of a plurality of conductive structures830. The second electrode pattern832may be another of the line parts of the plurality of conductive structures830. The dielectric layer820D may be interposed between the first electrode pattern831and the second electrode pattern832. In some embodiments, the dielectric layer820D may be a portion of one of the second dielectric layers820. For example, one of the second dielectric layers820may be interposed between the first electrode pattern831and the second electrode pattern832, thereby forming the dielectric layer820D. In this case, the dielectric layer820D and the one of the second dielectric layers820may be connected to each other with no boundary therebetween. The capacitor840may not be connected to the first floating diffusion region FD1, but embodiments are not limited thereto.

According to some example embodiments, a time required for storing charges in the second photoelectric conversion region PD2may be different from that required for storing charges in the first photoelectric conversion region PD1. During a first period in which stored charges is transferred from the first photoelectric conversion region PD1to the first floating diffusion region FD1, the first pixel region PX1may have difficulty in obtaining information of incident light. During the first period, the second photoelectric conversion region PD2may store charges in response to incident light. A single color filter CF may be shared by the first photoelectric conversion region PD1and the second photoelectric conversion region PD2of a unit pixel group UPG. A photoelectric conversion signal that is output from the second pixel region PX2may be used to correct a photoelectric conversion signal that is output from the first pixel region PX1. Therefore, it may be possible to prevent loss of information about light during the first period.

According to some example embodiments, the second photoelectric conversion region PD2may have a storage capacity less than a storage capacity of the first photoelectric conversion region PD1. Since the capacitor840is connected to the second floating diffusion region FD2of the second pixel region PX2, it may be possible to compensate the storage capacity of the second photoelectric conversion region PD2. Accordingly, the image sensor may increase in optical properties.

Differently from that shown inFIGS.2A and2B, in some embodiments the substrate100may omit the second pixel region PX2, and the microlens layer500may omit the second lens pattern520. Additional components, such as the second gate pattern G2and the second floating diffusion region FD2on the second pixel region PX2, may also be omitted. In this case, the first pixel region PX1may have a tetragonal shape when viewed in plan view. Nevertheless, the description set forth above may be applicable to the first height H1and the first lens width W1of the first lens pattern510, and also to the maximum interval A between the first surface510aof the first lens pattern510and the first surface100aof the substrate100.

FIGS.3A to3Gillustrate cross-sectional views showing a method of fabricating an image sensor according to some example embodiments. A duplicate description will be omitted below for conciseness.

Referring toFIG.3A, a substrate100may be prepared which has first and second pixel regions PX1and PX2. The substrate100may be doped with first conductivity type impurities. The substrate100may be doped with second conductivity type impurities to form first and second photoelectric conversion regions PD1and PD2. A second trench192and a device isolation pattern220may be formed on a second surface100bof the substrate100. A first trench191and an isolation pattern210may be formed in the substrate100. A second surface100bof the substrate100may be doped with first conductivity type impurities to form first and second floating diffusion regions FD1and FD2and an impurity region111. A first gate pattern G1and a second gate pattern G2may be respectively formed on the first pixel region PX1and the second pixel region PX2. A wiring layer800may be manufactured by forming first and second dielectric layers810and820and conductive structures830on the second surface100bof the substrate100. In this case, a capacitor840may further be formed.

A first surface100aof the substrate100may undergo a grinding process to thin the substrate100. A dielectric layer400, a fence pattern450, a protective layer430, and a plurality of color filters CF may be formed on the first surface100aof the thinned substrate100.

A preliminary lens layer501may be formed on the first surface100aof the substrate100, thereby covering top surfaces of the color filters CF. The preliminary lens layer501may be formed by a coating process that uses a photoresist material or a thermosetting resin. The preliminary lens layer501may have a top surface that is substantially flat. For example, the top surface of the preliminary lens layer501may be parallel to a first direction D1. In some embodiments, the top surface of the preliminary lens layer501may be parallel to the first surface100aof the substrate100.

A first sacrificial layer611may be formed on the preliminary lens layer501. The first sacrificial layer611may be formed by, for example, a coating process. The first sacrificial layer611may include an organic material. For example, the first sacrificial layer611may include a polymer, such as photoresist. The first sacrificial layer611may be, for example, a resist layer.

Referring toFIG.3B, the first sacrificial layer611may be patterned to form a first preliminary sacrificial pattern610P. The patterning of the first sacrificial layer611may be performed by exposure and development processes. For example, the first sacrificial layer611may be exposed by an exposure process and, after the exposure process, the first sacrificial layer611may include an exposed portion and a non-exposed portion. The exposed portion of the first sacrificial layer611may include a material whose chemical structure is different from that of the non-exposed portion of the first sacrificial layer611. During the development process, one or more of the exposed and non-exposed portion of the first sacrificial layer611may be removed to form the first preliminary sacrificial pattern610P. The first preliminary sacrificial pattern610P may be provided in plural, and the plurality of first preliminary sacrificial patterns610P may be correspondingly formed on the first and second pixel regions PX1and PX2. That is, a first preliminary sacrificial pattern610P of the plurality of the first preliminary sacrificial patterns610P may be formed on each of the first pixel regions PX1and on each of the second pixel regions PX2. The first preliminary sacrificial patterns610P may be laterally spaced apart from each other. In some embodiments, each of the first preliminary sacrificial patterns610P may have a height that is substantially the same height. Top surfaces of the first preliminary sacrificial patterns610P may be parallel to the first direction D1, but embodiments are not limited thereto.

Referring toFIG.3C, the first preliminary sacrificial patterns610P may be reflowed to correspondingly form first sacrificial patterns610. The first preliminary sacrificial patterns610P may be reflowed at a temperature between about 130° C. and about 200° C. During the reflow process, as indicated by the arrows inFIG.3C, the first preliminary sacrificial patterns610P may downwardly flow toward a top surface of the preliminary lens layer501. Top surfaces and sidewalls of the first preliminary sacrificial patterns610P may form first surfaces610aof corresponding ones of the first sacrificial patterns610. The first surfaces610aof the first sacrificial patterns610may each be a curved surface. The first surfaces610aof the first sacrificial patterns610may each have an upwardly convex shape. The first surfaces610aof the first sacrificial patterns610may project from the preliminary lens layer501without being directed toward the preliminary lens layer501. For example, in some embodiments, each of the first sacrificial patterns610may have a hemispheric shape.

The first sacrificial patterns610may be provided on corresponding positions that correspond to the positions of the first and second pixel regions PX1and PX2. The first sacrificial patterns610may be laterally spaced apart from each other. Heights of the first sacrificial patterns610may be identical or similar to each other. Widths of the first sacrificial patterns610may be identical or similar to each other.

Referring toFIG.3D, a second sacrificial layer621may be formed on the preliminary lens layer501, thereby covering the first sacrificial patterns610. The formation of the second sacrificial layer621may include coating an organic material on the preliminary lens layer501and the first sacrificial patterns610. The second sacrificial layer621may include a polymer, such as photoresist. The second sacrificial layer621may be, for example, a resist layer. In some embodiments, the second sacrificial layer621may include a same material as a material of the first sacrificial patterns610. Alternatively, in other embodiments, the second sacrificial layer621may include a different material from the material of the first sacrificial patterns610.

Referring toFIG.3E, the second sacrificial layer621may be patterned to form second preliminary sacrificial patterns620P. The patterning of the second sacrificial layer621may be performed by exposure and development processes similar to the exposure and development process of the patterning of the first sacrificial layer611described above and a repeated description is omitted for conciseness. The second preliminary sacrificial patterns620P may be laterally spaced apart from each other. The second preliminary sacrificial patterns620P may be formed on corresponding first pixel regions PX1of the substrate100, thereby covering corresponding first preliminary sacrificial patterns610P. For example, each of the second preliminary sacrificial patterns620P may cover a corresponding respective one of the first sacrificial patterns610. The second preliminary sacrificial patterns620P may not be formed on the second pixel regions PX2. The second preliminary sacrificial patterns620P may expose the first sacrificial patterns610on the first pixel regions PX1.

Referring toFIG.3F, the second preliminary sacrificial patterns620P may be reflowed to correspondingly form second sacrificial patterns620. Therefore, sacrificial structures630may be formed on corresponding first pixel regions PX1of the substrate100. Each of the sacrificial structures630may include the second sacrificial pattern620and a corresponding respective one of the first sacrificial patterns610. The sacrificial structures630may not be formed on the second pixel regions PX2.

The second preliminary sacrificial patterns620P may be reflowed at a temperature between about 130° C. and about 200° C. During the reflow process, as indicated by arrows inFIG.3F, the second preliminary sacrificial patterns620P may downwardly flow toward the top surface of the preliminary lens layer501. Top surfaces and sidewalls of the second preliminary sacrificial patterns620P may form second surfaces620aof corresponding ones of the second sacrificial patterns620. The second surfaces620aof the second sacrificial patterns620may be externally exposed. The second surfaces620aof the second sacrificial patterns620may form curved surfaces. For example, each of the second surfaces620aof the second sacrificial patterns620may have an upwardly convex shape. In this case, in some embodiments, each of the sacrificial structures630may have a hemispheric shape.

The second sacrificial patterns620may be laterally spaced apart from each other. The second sacrificial patterns620may be provided on corresponding positions that correspond to positions of the first pixel regions PX1. The second sacrificial patterns620may not be provided on the second pixel regions PX2. According to some example embodiments, since the second preliminary sacrificial patterns620P are formed on the first sacrificial patterns610, the second preliminary sacrificial patterns620P may have respective second surfaces each of whose uppermost portions is located at a relatively high level. Therefore, the second surfaces620aof the second sacrificial patterns620may have uppermost portions at a higher level than a level of uppermost portions of the first surfaces610aof the first sacrificial patterns610on the first pixel regions PX1. In some embodiments, the second surfaces620aof the second sacrificial patterns620may have curvatures different from curvatures of the first surfaces610aof the first sacrificial patterns610. Each of the second sacrificial patterns620may have a height that is substantially the same height. Each of the second sacrificial patterns620may have a width that is substantially the same width.

Referring sequentially toFIGS.3G and2B, the first and second sacrificial patterns610and620may undergo an etch-back process to form a microlens layer500. The etch-back process may be performed such that shapes of the first sacrificial patterns610may be transferred onto the preliminary lens layer501, and thus that second lens patterns520may be formed. Shapes of the sacrificial structures630may be transferred onto the preliminary lens layer501, and thus first lens patterns510may be formed.

When a single resist pattern is reflowed to form a sacrificial pattern, the sacrificial pattern may have difficulty in having a height greater than a specific value. The sacrificial pattern may be used to form a lens pattern, which lens pattern may have a curvature limited by that of the sacrificial pattern.

By contrast, the sacrificial structures630may each include the first sacrificial pattern610and the second sacrificial pattern620, and thus may have relatively large heights. As discussed with respect toFIG.3F, on the first sacrificial patterns610, the second preliminary sacrificial patterns620P may be reflowed to form the second sacrificial patterns620. Therefore, the second surfaces620aof the second sacrificial patterns620may have curvatures different from curvatures of the sacrificial pattern formed by reflow of the single resist as in the related art. The curvatures of the second surfaces620aof the second sacrificial patterns620may determine curvatures of the first surfaces510aof the first lens patterns510. The etch-back process may continue until termination of removal of the first sacrificial patterns610and the sacrificial structures630. As a result of the etch-back process, there may be manufactured the microlens layer500including a planarized layer530, a first lens pattern510, and a second lens pattern520. As shown inFIG.2B, the first height H1of the first lens pattern510may be about 30% to about 50% of the first width W1of the first lens pattern510. In addition, the maximum interval A between the first surface510aof the first lens pattern510and the first surface100aof the substrate100may be about 2.5 times to about 3.5 times the first radius. The examples mentioned above may fabricate the image sensor discussed inFIGS.2A and2B.

Differently from that shown, in some embodiments, the substrate100may include no second pixel region PX2, and no component may be formed on the second pixel region PX2. The second sacrificial patterns620discussed inFIG.3Fmay be formed on corresponding first sacrificial patterns610. The etch-back process ofFIG.3Gmay be performed on the sacrificial structures630. Therefore, in this configuration, the description set forth above may be applicable to the first height H1and the first lens width W1of the first lens pattern510, and also to the maximum interval A between the first surface510aof the first lens pattern510and the first surface100aof the substrate100.

FIG.4Aillustrates a cross-sectional view taken along line I-II ofFIG.2A, showing an image sensor according to some example embodiments.

Referring toFIG.4A, an image sensor may include a substrate100, an isolation pattern210A, a first gate pattern G1, a second gate pattern G2, a wiring layer800, a dielectric layer400, a protective layer430, a fence pattern450, color filters CF, and a microlens layer500.

The substrate100may be provided therein with the isolation pattern210that defines first and second pixel regions PX1and PX2. The isolation pattern210A may be identical or similar to the isolation pattern210discussed with respect toFIGS.2A and2B. For example, the isolation pattern210A may define the first and second pixel regions PX1and PX2. In contrast with the isolation pattern210discussed with respect toFIGS.2A and2B, the isolation pattern210A may be provided in a backside trench191A, and the backside trench191A may penetrate a first surface100aof the substrate100. The backside trench191A may have a bottom surface provided in the substrate100. The isolation pattern210A may have a bottom surface that is spaced apart from a second surface100bof the substrate100and is located at a higher level than a level of the second surface100b. Alternatively, in some embodiments, the isolation pattern210A may further penetrate the second surface100bof the substrate100. The isolation pattern210A may have at a top surface a width W21′ greater than a width W22′ at a bottom surface of the isolation pattern210A. The top surface of the isolation pattern210A may be located at a level that is substantially the same level as a level of the first surface100aof the substrate100. The isolation pattern210A may include neither a conductive isolation pattern215nor a capping pattern217that are discussed with respect toFIG.2B, and may include a material that is the same material as a material of the dielectric isolation pattern211discussed with respect toFIG.2B. For example, the isolation pattern210A may include a silicon-based dielectric material that fills the backside trench191A.

Differently from that shown inFIG.4A, the isolation pattern210A may further extend onto the first surface100aof the substrate100, and may further be provided between the substrate100and the dielectric layer400.

For another example, in some embodiments, the isolation pattern210A may include a material that is the same material as a material of the dielectric layer400, and may be connected to the dielectric layer400with no boundary therebetween. In other words, the isolation pattern210A and the dielectric layer400may be integrally formed with each other.

A pixel isolation region120may further be provided in the substrate100. The pixel isolation region120may be provided between the bottom surface of the isolation pattern210A and the second surface100bof the substrate100. The pixel isolation region120may include a III-group element. For example, the pixel isolation region120may be a zone doped with impurities having a first conductivity type (e.g., p-type). The pixel isolation region120and the isolation pattern210A may define the first and second pixel regions PX1and PX2. Alternatively, in some embodiments, the substrate100may omit the pixel isolation region120.

The first and second gate patterns G1and G2may have a planar gate structure. Each of the first and second gate patterns G1and G2may include a second part320, but may omit the first part310discussed with respect toFIG.2B. The first and second gate patterns G1and G2may be located at a level that is the same as or lower than the second surface100bof the substrate100. A gate dielectric pattern340may be interposed between the substrate100and each of the first and second gate patterns G1and G2. The gate dielectric pattern340may not extend into the substrate100.

FIG.4Billustrates a cross-sectional view taken along line I-II ofFIG.2A, showing an image sensor according to some example embodiments.

Referring toFIG.4B, an image sensor may include a substrate100, a first isolation pattern210′, a second isolation pattern210A′, a device isolation pattern220, a first gate pattern G1, a second gate pattern G2, a wiring layer800, a dielectric layer400, a protective layer430, a fence pattern450, color filters CF, and a microlens layer500.

The first isolation pattern210′ may be provided in the substrate100and between first and second photoelectric conversion regions PD1and PD2. The first isolation pattern210′ and a first trench191′ may be substantially the same as the isolation pattern210and the first trench191that are illustrated in and discussed with respect toFIG.2B. For example, the first isolation pattern210′ may include a dielectric isolation pattern211, a conductive isolation pattern215, and a capping pattern217. In contrast, the first isolation pattern210′ may have a top surface at a lower level than a first surface100aof the substrate100.

The second isolation pattern210A′ may be provided in the substrate100between the first and second photoelectric conversion regions PD1and PD2. A backside trench191A′ and the second isolation pattern210A′ may be substantially the same as the backside trench191A and the isolation pattern210A that are illustrated in and discussed with respect toFIG.4A. In contrast toFIG.4A, the second isolation pattern210A′ may be disposed on the first isolation pattern210′. The first and second isolation patterns210′ and210A′ may be connected to each other. For example, the second isolation pattern210A′ may have a bottom surface in contact with a top surface of the first isolation pattern210′. Therefore, the first and second isolation patterns210′ and210A′ may define first and second pixel regions PX1and PX2.

FIG.4Cillustrates a cross-sectional view taken along line I-II ofFIG.2A, showing an image sensor according to some example embodiments.

Referring toFIG.4C, an image sensor may include a substrate100, an isolation pattern210, a device isolation pattern220, a first gate pattern G1, a second gate pattern G2, a wiring layer800, a dielectric layer400, a protective layer430, a fence pattern450, color filters CF, and a microlens layer500.

The microlens layer500may include a first lens pattern510and a second lens pattern520. The first and second lens patterns510and520may be substantially the same as the first and second lens patterns510and520discussed in the example ofFIGS.2A and2B. In contrast toFIGS.2A and2B, the microlens layer500may omit the planarized layer530discussed with respect toFIG.2B. The second lens pattern520may be laterally spaced apart from the first lens pattern510.

The image sensor may further include a transparent protective layer470. The transparent protective layer470may be interposed between the color filters CF and the microlens layer500. The transparent protective layer470may include a dielectric material. The transparent protective layer470may have a top surface that is substantially flat.

According to various embodiments, a first lens pattern may have a top surface whose curvature is adjusted to allow a first photoelectric conversion region to receive an increased amount of incident light. Accordingly, an image sensor may increase in optical properties.

This detailed description of various embodiments should not be construed as limited to the embodiments set forth herein, and it is intended that the embodiments cover various combinations, modifications and variations without departing from the spirit and scope of the appended claims. The appended claims should be construed to include other embodiments not necessarily explicitly described above.