High speed hybrid structure counter having synchronous timing and asynchronous counter cells

A multi-bit counter is provided. The multi-bit counter includes a plurality of asynchronous base counter cells coupled in series, the asynchronous base counter cells having a plurality of input terminals. The multi-bit counter also includes at least one logic gate coupled to at least one of the input terminals of at least one of the plurality of asynchronous base counter cells, a reload signal being input into the asynchronous base counter cells, a clock signal being input into the asynchronous base counter cells, and an input voltage being input into the asynchronous base counter cells, wherein the multi-bit counter is synchronous with the clock signal.

BACKGROUND

1. Technical Field

The present invention is related to a counter circuit and, in particular, to a high-speed hybrid structure counter having synchronous timing and asynchronous counter cells.

2. Discussion of Related Art

Multi-bit counter circuits are needed in many circuit applications, for example in phase-locked loop frequency dividers, and spread spectrum control dividers. In typical applications, counter circuits are at least 16-bits in size, and work at a frequency up to about 800 MHz. Counter circuits used in these typical applications may be either asynchronous or synchronous in their operation. In a synchronous counter circuit, there is a common source of clock pulses driving all of the components of the circuit. In an asynchronous counter circuit, components of the circuit are not driven by a common clock signal, and each component may be driven by a separate clock signal.

An asynchronous frequency divider has a relatively simple structure, and therefore occupies the least area, allowing for increased integration. Asynchronous frequency dividers, however, are delay dependent and are difficult to operate at high frequencies. A synchronous frequency divider, on the other hand, is more stable at nominal and high frequencies, but it has a relatively complicated circuit design, resulting in a larger footprint and increased power consumption, which makes synchronous designs more difficult to integrate. Moreover, synchronous frequency dividers often have a complex control logic, and a long delay path, which impedes the divider from operating. Typically, a delay cell or delay circuit is incorporated into synchronous frequency dividers to compensate for variable delay paths to improve operation at higher frequencies. However, because delay cells can have a large variance, and are often temperature and voltage sensitive, the use of these delay cells often have a negative impact on circuit performance.

Therefore, there is a need for more robust counter circuits capable of operating at higher frequencies while having simpler circuit design and smaller footprints.

BRIEF SUMMARY

In accordance with aspects of the present invention, there is provided a multi-bit counter having synchronous timing, with a base cell formed of multi-bit asynchronous circuits. Some embodiments of a multi-bit timer according to the present invention includes a plurality of asynchronous base counter cells coupled in series, the asynchronous base counter cells having a plurality of inputs, at least one logic gate coupled to at least one of the plurality of asynchronous base counter cells, a reload signal being input into the asynchronous base counter cells, a clock signal being input into the asynchronous base counter cells, and an input voltage being input into the asynchronous base counter cells.

A phase-locked loop feedback programmable divider, utilizing some embodiments of the present invention can include a phase frequency detector, a charge pump and loop filter, a voltage-controlled oscillator, a predivider, and a programmable divider, wherein the programmable divider comprises a multi-bit counter having synchronous timing, the counter including a plurality of asynchronous base counter cells coupled in series.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. Further embodiments and aspects of the invention are described with reference to the accompanying drawings, which are incorporated in and constitute a part of this specification.

DETAILED DESCRIPTION

A novel counter circuit is provided which may have a hybrid synchronous and asynchronous structure. Consistent with the present invention, there is provided a counter having synchronous timing, the counter being comprised of a plurality of asynchronous base counter cells. There is also provided a phase-locked loop feedback divider which makes use of the hybrid counter and a pseudo-synchronous count control circuit.

In order to utilize the benefits of both synchronous and asynchronous designs, a frequency divider having a hybrid structure of both synchronous and asynchronous design may offer a circuit which balances performance, integration ability, and cost. Consistent with embodiments of the present invention, there is provided hybrid structure wherein the circuit may be designed to be synchronous, to take advantage of the benefits of synchronous frequency dividers. The base cell of the synchronous circuit, however, may be multi-bit asynchronous, thus reducing cost and complexity.

Moreover, because embodiments of the base cell may have a multi-bit design, the control logic of the synchronous circuit may be simplified and any associated delay path may be reduced. By utilizing such a hybrid structure, a circuit consistent with the present invention may achieve higher frequencies with reduced area and power cost compared with frequency dividers of the prior art.

FIG. 1is a circuit diagram illustrating a multi-bit counter100consistent with the present invention. As shown inFIG. 1, a multi-bit counter100includes a plurality of base counter cells110(1) through110(N). Although multi-bit counter100can include any number of base counter cells110, the particular example of multi-bit counter100shown inFIG. 1includes (8) base counter cells110(1)-110(8) coupled in series. Into each base counter cell110, a number of signals, for example, four signals, may be input at inputs111-114, and a cell output OPNmay be output at output115. As shown inFIG. 1, counter100has synchronous timing as each base counter cell110has a common clock signal CLK input at input111. A voltage VDDmay be input into a first base counter cell110at input112. An input signal, as described below, may be fed into input112in subsequent base counter cells, cells110(3) though110(N).

A reload signal may be input into each base counter cell110at input113, and a count signal may be input into each base counter cell at input114. A pulse count signal Count, which may comprise an N component and an N+1 component, may be input into each base counter cell at input114.

As shown inFIG. 1, the output signal115of base counter cell110(1), cell output OP1, is directly input into subsequent base counter cell110(2). For subsequent base counter cells110(3. . . N), however, cell outputs OPNare combined in logic gates prior to being input into base counter cell110(3. . . N). For example, as illustrated inFIG. 1, cell output signals OP1and OP2are input into NAND gate120, and the signal output from NAND gate120is input into inverter125. The signal output from inverter125is then input into base counter cell110(3) at input112.

To determine the input signals to base counter cell110(4), cell output signal OP3is input into inverter130, and the signals output from inverter130and cell output OP2is input into NOR gate135. The signal output of NOR gate135is then input into base counter cell110(4) at input112.

To determine the input signals to base counter cell110(5), cell output signals OP3and OP4are input into NAND gate140. The signals output from NAND gate140and cell output OP2is input into NOR gate145, and the signal output from NOR gate145is input into base counter cell110(5) at input112.

To determine the input signals to base counter cell110(6), cell output signal OP5is input into inverter150, and the signal output from inverter150, along with cell output signal OP2and a combined signal including cell output signals OP3and OP4, is input into NOR gate155. The signal output from NOR gate155is then input into base counter cell110(6) at input112.

To determine the input signals to base counter cell110(7), cell output signals OP5and OP6are input into NAND gate160. The signal output from NAND gate160, along with cell output signal OP2and a combined signal including cell outputs signals OP3and OP4is input into NOR gate165. The signal output from NOR gate165is then input into base counter cell110(7) at input112.

To determine the input signals to base counter cell110(8), cell output signals OP5, OP6, and OP7are input into NAND gate170. The output signals from NAND gate170, along with cell output signal OP2and a combined signal including cell output signals OP3and OP4, is input into NOR gate175. The signal output from NOR gate175is then input into base counter cell110(8) at input112.

As illustrated inFIG. 1, the delay path is only as large as two logic gates outside of base counter cell110. By minimizing the delay path, faster counter control logic may be designed. For example, counter circuit100, designed consistent with the present invention, may allow stable performance at frequencies over 800 MHz. Base counter cells110may be synchronous or asynchronous, single bit, or multi-bit. In some embodiments of the present invention, however, base counter cells110include multi-bit asynchronous counter cells, as described below in conjunction withFIG. 2.

FIG. 2shows a circuit diagram illustrating a multi-bit asynchronous base counter cell110, consistent with some embodiments of the present invention. The embodiment of base counter cell110shown inFIG. 2includes two flip-flops210and212coupled to a circuit for building a count reload function202, and a base counter cell output circuit204. In some embodiments of the present invention, flip-flops210and212may be D-type flip-flops, having inputs for data D, clock signal CLK, set signal S, reset signal R, and having output signal Q, and complementary output signalQ. As shown inFIG. 2, complementary output signalQof flip-flop210is fed into clock input CLK of flip-flop212. Thus, because the clock signals input into flip-flop210and flip-flop212may be different, the counter cell is considered asynchronous.

In some embodiments of the present invention, flip-flop210may have a synchronous load214coupled to data input D. Synchronous load214may have inputs D, TI, and TE. An output signal Q of flip-flop210can be input into synchronous load input D. Complementary output signalQof flip-flop210can be input into input TI of synchronous load214. A signal at input112of base counter cell110, as shown inFIG. 1, can be input into input TE of synchronous load214. In some embodiments of the present invention, if the signal input into TE is a logic high, the next state of flip-flop210will be the same as the signal input into TI. If the signal input into TE is a logic low, the next state of flip-flop210will be the same as the signal input into D. Flip-flop212may be a normal D-type flip-flop which performs a divide-by-2 operation on an output signal of flip-flop210.

As shown inFIG. 2, some embodiments of base counter cells110may also include a circuit for building a count reload function202, which, inFIG. 2, includes NAND gates216,218,220, and222, and inverter gates224, and226. The circuit for building a count reload function202may be coupled to flip-flops210and212, and may provide inputs for set S and reset R inputs of flip-flops210and212. To determine the set S and reset R inputs, component N of count signal Count may be input into inverter224, and a second input of NAND gate216. Component N+1 of count signal Count may be input into inverter226and a second input of NAND gate220. The output signal of inverter224is input into the first input of NAND gate218, and the output signal of inverter226is input into the first input of NAND gate222. The reload signal may be input into the first input of NAND gate216, the second input of NAND gate218, the first input of NAND gate220, and the second input of NAND gate222. The output signal of NAND gate216is input into reset input R of flip-flop210, the output signal of NAND gate218is input into set input S of flip-flop210, the output signal of NAND gate220is input into reset input R of flip-flop212, and the output of NAND gate222is input into set input S of flip-flop212.

As also shown inFIG. 2, base counter cell110may further include base counter cell output circuit204, which comprises a NOR gate228. In operation, complementary output signalQof flip-flop210is a first input signal of NOR gate228, and complementary output signalQof flip-flop212is a second input signal of NOR gate228. The output signal from NOR gate228is the output of base counter cell110OPN, which may be used to determine the cell input signal at input112, as shown inFIG. 1. Output signal Q of flip-flops210and212may be used as an input signal for other circuits coupled to base counter cell110, or other base counter cells110coupled in series.

FIG. 3is a diagram of a phase-locked loop programmable frequency divider300which uses the multi-bit counter100such as that shown inFIG. 1in a programmable divider. The embodiment of phase-locked loop programmable frequency divider300shown inFIG. 3includes phase frequency detector302coupled to charge pump/loop filter304, which is coupled to variable controlled oscillator306. A predivider308received the output signal from VCO306and may then be coupled to programmable divider310, which may include multi-bit counter100.

Phase-locked loop programmable frequency divider300may be similar to known phase-locked loop programmable frequency dividers. However, as shown inFIG. 3, phase-locked loop programmable frequency divider300in accordance with the present invention includes multi-bit counter100in programmable divider310. In operation, a reference clock signal Ref_Clock and an output of programmable divider310, as feedback, may be input into phase frequency detector302. An output signal from phase frequency detector302is input into charge pump/loop filter304. An output signal from charge pump/loop filter may be input into voltage-controlled-oscillator306, which outputs a voltage-controlled function FVCOand a signal which is input into predivider308. Predivider308, from the input of voltage-controlled oscillator306and a pulse control signal provided from a counter control circuit (shown inFIG. 4), outputs a signal to programmable divider310. Programmable divider310utilizes the signal from predivider308in conjunction with a count signal Count, input at terminal114as shown inFIGS. 1 and 2, to produce the output signal that is received by phase frequency detector302.

Embodiments of phase-locked loop programmable frequency divider300that incorporate embodiments of multi-bit counter100in programmable divider310may operate at higher frequencies without the need for a large amount of circuit space for a counter. Such utilization may allow phase-locked loop programmable frequency divider300to have better performance and be more easily integrated into smaller devices.

FIG. 4shows a circuit diagram illustrating a count control circuit400according to some embodiments of the present invention. As illustrated inFIG. 4, count control circuit400may include four-input NAND gate402, NOR gate404, flip-flop406, flip-flop408, inverter gate410and inverter gate412. In accordance with some embodiments of the present invention, flip-flops406and408may be D-type flip-flops having data input D, clock signal input CLK for receiving clock signal CLK, set input S, reset input R, and outputs Q andQ. Further consistent with the present invention voltage VDDmay be input into set input S of flip-flop406and into reset input R of flip-flop408, and a reset signal may be input into set input S of flip-flop408and into reset input R of flip-flop406.

As shown inFIG. 4, count control circuit400may receive as input signals or values output from base counter cell110, as shown inFIG. 1andFIG. 2. For example, NAND gate402may receive signals at inputsQ1, and Q0, fromFIG. 2, and OP8, and OP1fromFIG. 1. The signal output from NAND gate402is input into NOR gate404. Along with the output signal of NAND gate402, a combined signal including the signals output from OP3and OP4, and a combined signal including the signals output from OP5, OP6, and OP7, are input into NOR gate404. The signal output from NOR gate404may then be input into data input D of flip-flop406and flip-flop408. A signal output from complementary outputQof flip-flop406may be received by inverter410, and a signal output from complementary outputQof flip-flop408may be received by inverter gate412. The signal output from inverter gate410may be a pulse control, or count control signal, which, as shown inFIG. 3, may be input into predivider308, when count control circuit400is used in phase-locked loop programmable frequency divider300. The signal output from inverter gate412may be the reload signal, which may be input to multi-bit counter cell100and individual base counter cells110, as shown inFIGS. 1 and 2.

As shown inFIG. 4, the delay path may only be as long as NAND gate402, NOR gate404, and NOR gate228(shown inFIG. 2). The reduced delay path also reduces the signal delay in a circuit including multi-bit counter100used in conjunction with count control circuit400. The reduced delay may allow circuits incorporating multi-bit counter100used in conjunction with count control circuit400to have improved performance at higher operating frequencies.

In accordance with some embodiments of the present invention, there is provided a counter having a hybrid synchronous/asynchronous structure, which may allow for increased performance and integration at lower costs. Moreover, when used in a phase-locked loop frequency divider with a count control circuit in accordance with some embodiments of the present invention, the phase-locked loop frequency divider may have improved performance, and may operate at higher frequencies.

Other embodiments consistent with the present invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only. Accordingly, the invention should only be limited by the following claims.