Step-embedded SiGe structure for PFET mobility enhancement

A device, and method for manufacturing the same, including a PFET having an embedded SiGe layer where a shallow portion of the SiGe layer is closer to the PFET channel and a deep portion of the SiGe layer is further from the PFET channel. Thus, the SiGe layer has a boundary on the side facing toward the channel that is tapered. Such a configuration may allow the PFET channel to be compressively stressed by a large amount without necessarily substantially degrading extension junction characteristics. The tapered SiGe boundary may be configured as a plurality of discrete steps. For example, two, three, or more discrete steps may be formed.

FIELD OF THE INVENTION

Aspects of the present invention are generally directed to the use of embedded SiGe in a PFET, and more particularly to forming an embedded SiGe layer that tapers smoothly or in a step-like manner away from a PFET channel in order to provide increased compressive channel stress.

BACKGROUND OF THE INVENTION

As has been previously recognized, embedded silicon germanium (SiGe) technology has become a promising technology for producing silicon high-performance p-type field-effect transistors (PFETs). In particular, it has been shown that embedding SiGe in a silicon substrate next to a PFET channel causes compressive stress on the channel, thereby increasing hole mobility and increasing the performance of the PFET. This compressive stress property is discussed, for example, in an article entitled “35% Drive Current Improvement From Recessed-SiGe Drain Extensions on 37 nm Gate Length PMOS,” by P. R. Chidambaram, et al., 2004 Symposium on VLSI Technology, Digest of Technical Papers, pp. 48-49.

Referring toFIG. 23, which has been substantially reproduced from the above-mentioned reference article, it can be seen that, in general, channel stress is related to the relative distance of the SiGe layer from the channel. More particularly, part (a) ofFIG. 23shows a 30 nm deep layer of SiGe extending toward the channel only as far as the source/drain (SD) region. Part (c) shows the same 30 nm deep layer of SiGe extending toward the channel, but this time extending further (and thus closer to the channel) into the drain extension (DE) region. As can be seen in the graph of part (b), the stress at the center of the channel (distance=0) is approximately 250 MPa for the part (a) configuration, whereas the stress at the center of the channel is approximately 900 MPa for the part (c) configuration. Therefore, it can be seen that channel stress is increased by forming the SiGe layer closer to the channel.

Since compressive channel stress in a PFET is good in that it increases hole mobility in the channel, it would be desirable to be able to increase the channel stress even more. However, attempting to do so most likely results in substantial complications to be overcome, as will be discussed later. Accordingly, new techniques need to be developed to increase channel stress without substantially degrading extension junction characteristics.

BRIEF SUMMARY OF THE INVENTION

Aspects of the present invention solve one or more of the above-stated problems. For example, aspects of the invention are directed to forming a PFET having an embedded SiGe layer where a shallow portion of the SiGe layer is closer to the PFET channel and a deep portion of the SiGe layer is further from the PFET channel. Thus, the SiGe layer has a boundary on the side facing toward the channel that is tapered. Such a configuration may allow the PFET channel to be compressively stressed by a large amount without necessarily substantially degrading extension junction characteristics.

Further aspects of the present invention are directed to forming the tapered SiGe boundary as a plurality of steps. For example, two, three, or more steps may be formed. These aspects provide a practical way to implement the tapered SiGe boundary.

These and other aspects of the invention will be apparent upon consideration of the following detailed description of illustrative embodiments.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

Referring toFIG. 1, an illustrative device PFET device1is shown having a step-embedded SiGe structure. In particular, device portion1includes a silicon body10, over which a polysilicon PFET gate11is formed. Silicon body10has source/drain regions3, as well as a channel region2(shown inFIG. 1as being approximately between vertical broken lines) underneath gate11and between source/drain regions3. The top of gate11is capped with an oxide layer12. Gate11is surrounded laterally on opposing sides by an oxide spacer13. In addition, an SiGe layer14formed on silicon body10over the source/drain regions, on the opposing sides of gate11and channel2. Silicon body10and SiGe layer14are shaped such that, on each of the opposing sides, SiGe layer14has two steps15,16. Step15is formed at a relatively shallow level as compared with step16. In addition, step15is formed so as to be laterally closer to gate11as compared with step16. Thus, PFET1may be considered to have a shallow-and-close step15and a deep-and-far step16on each opposing side. The surface of silicon body10that SiGe layer14is disposed on is likewise shaped so as to cooperatively mate with steps15,16of SiGe layer14.

Looking more closely at the boundary between silicon body10and SiGe layer14, each of first and second steps15,16has a substantially planar side boundary17,19that is substantially parallel to the sidewalls of gate11and/or to each other. However, side boundary17of step15is closer to gate11and/or channel2than side boundary19of step16. For example, side boundary17may be aligned approximately with the outer edge of nearest oxide spacer13, while side boundary19may be laterally spaced from the outer edge of nearest oxide spacer13by a distance L>0, such as approximately L=40 nm, or in the range of, e.g., 40-60 nm. In addition, step15has a substantially planar lower boundary18that is substantially parallel to and shallower than a substantially planar lower boundary5of step16. To summarize the structure of the four boundaries/surfaces as shown inFIG. 1, lower boundary18extends at an angle (such as, e.g., approximately ninety degrees) from side boundary17, side boundary19extends at an angle (such as, e.g., approximately ninety degrees) from lower boundary18and is spaced from side boundary17by at least lower boundary18, and lower boundary5extends at an angle (such as, e.g., approximately ninety degrees) from side boundary19and is spaced from side boundary17and lower boundary18by at least side boundary19. In an illustrative embodiment, lower boundary18of step15may have a depth measured from the bottom of gate11of approximately D1=20 nm, or in the range of, e.g., 15-25 nm, while lower boundary5of step16may have a depth measured from the bottom of gate11in the range of D2=50-60 nm. In general, depth D1may be approximately 40% of depth D2. The above dimensions are merely illustrative; the particular dimensions of SiGe layer14may depend upon the desired properties of PFET1.

It has been found that channel stress increases both as the SiGe layer approaches the channel and as the SiGe layer deepens. One might therefore conclude that channel stress may be increased simply by forming a deep and close SiGe layer. Unfortunately, such a configuration would significantly degrade the extension junction junction leakage current as well as increase SiGe epitaxial layer crystal defects. However, the particular SiGe configuration shown inFIG. 1may allow increased compressive channel stress to be provided without necessarily running into these extension junction and crystal defect problems. This is because the lower portion of SiGe layer14is further from the PFET channel than the upper portion. In other words, the illustrated SiGe configuration allows for the best of both worlds: SiGe close to gate11and/or channel15at a shallow level, and SiGe further from gate11and/or channel2at a deeper level.

Although two steps15,16are illustrated, more than two steps may be used as desired. For example, three, four, or more steps may be formed, each step being deeper into silicon body10and further from gate11and/or channel2than the previous step. It should also be noted that, althoughFIG. 1and various other figures herein show an idealized set of steps with sharp, right-angle boundaries, in practice user steps15,16may be rounded. Moreover, although discrete steps are included in various illustrative embodiments described herein, SiGe layer14may instead (or additionally) be more smoothly tapered with a simple or complex curved boundary without a sharp angle. In addition, where discrete steps are used, the side and lower boundaries of the steps may be at any angle to one another, such as approximately ninety degrees or any other angle. Regardless of whether a stepped boundary and/or a relatively smooth and curved boundary is formed, what is important is that SiGe layer14is formed such that it has a boundary that is closer to the PFET channel at shallower locations and further from the PFET channel at deeper locations.

A first illustrative process for forming a PFET with a stepped SiGe embedded layer will now be described in connection withFIGS. 2-12. Referring toFIG. 2, a silicon-on-insulator (SOI) wafer is provided having a silicon body20, a buried oxide (BOX) layer (not shown) under the silicon body20, and a substrate (not shown) under the BOX layer. Silicon body20may be, for example, 50 to 70 nm in thickness, while the BOX layer may be, for example, approximately 150 nm in thickness. A polysilicon PFET gate21is formed on silicon body20in a conventional manner, and the top of gate21is capped with an oxide layer22that may be, for example, approximately 50 nm in thickness. Gate21may extend from silicon body20by, for example, approximately 100 nm. After reoxidation of the sidewalls of gate21, gate21is surrounded laterally by an oxide spacer23. Oxide spacer23may be, for example, approximately 10 nm in width.

Referring toFIG. 3, a halo implant process is used to form an N-type diffusion region (not shown) and an extension implant process is used to form a P-type diffusion region30underneath oxide spacer23and/or gate21.

Referring toFIG. 4, using oxide spacer23and cap22as a mask, an etching process, such as a conventional reactive-ion etching (RIE) process, is used to etch away a shallow recess having a step region41in region30. This step region41will be used later in the process to help form the upper step of the SiGe layer.

Referring toFIG. 5, a first SiN spacer50is formed on oxide spacer23and on a portion of shallow recessed region30that at least includes the portion of region30that defines step region41.

Referring toFIG. 7, using first SiN spacer50and cap22as a mask, the exposed portion of silicon body20(including the exposed portions of source/drain regions60,61) is etched using an etching process, such as a conventional RIE process, thereby forming a relatively deep recess having a step region71in silicon body20. This step region71will be used later in the process to help form the lower step of the SiGe layer.

Referring toFIG. 8, first SiN spacer50is removed in preparation for forming a SiGe layer over the step regions41,71. Spacer50may be removed by hot H3PO4 wet etching.

Referring toFIG. 9, a SiGe layer90is epitaxially grown on the recessed step regions41,71defined by source/drain regions60,61and by silicon body20. Thus, due to the shape of step regions41and71, SiGe layer90itself forms into a shape having an upper step91and a lower step92. Of course, depending upon the process, any number of steps may be formed.

Referring toFIG. 10, a second SiN spacer100is formed on oxide spacer23and a portion of SiGe layer90using, for example, conventional blanket RIE.

Referring toFIG. 12, a nickel silicide layer120is formed on doped gate111as well as on doped region110(and thus on source/drain regions60,61).

A second illustrative process for forming a PFET with a stepped SiGe embedded layer will now be described in connection withFIGS. 13-22. Referring toFIG. 13, a silicon body1300has a 20-30 nm P-type diffusion region1305formed by an extension implant process underneath a first SiN spacer1304and/or a polysilicon gate1301. The extension implant process may use, e.g., a boron difluoride (BF2) implant at 3 KeV with a dose of 1E15 cm−2 in order to extend diffusion region1305outward from first SiN spacer1304. A halo implant process may also be used, such as an arsenic (A) implant at 60 KeV with a dose of 5E13 cm−2 at a 30 degree angle. First SiN spacer1304surrounds gate1301, and gate1301has a re-oxidation layer1306sandwiched between gate1301and SiN spacer1304. Also, a SiN cap1302is disposed on top of gate1301.

Referring toFIG. 14, using first SiN spacer1304and cap1302as a mask, an etching process, such as a conventional Si RIE process, is used to etch away a shallow recess having a step region1401in diffusion region1305. This step region1401will be used later in the process to help form the upper step of the SiGe layer.

Referring toFIG. 15, an oxide spacer1501is formed on first SiN spacer1304and on a portion of shallow recessed P-type diffusion region1305that at least includes the portion of regions1305that define step regions1401. Oxide spacer1501is about, e.g., 30 nm in thickness and is formed by oxide deposition followed by blanket RIE.

Referring toFIG. 16, source and drain regions1305are implanted. In this example, BF2 implantation is used at approximately 20 KeV, 1×1015cm−2. A thin layer of unimplanted silicon1300remains underneath the source and drain regions1305. This thin layer may be, e.g., about 10 nm in thickness.

Referring toFIG. 17, using oxide spacer1501and cap1302as a mask, the exposed portion of silicon body1300(including the exposed portions of source/drain regions1305) is etched, such as by using a conventional RIE process, thereby forming a relatively deep recess having a step region1701in silicon body1300. This step region1701will be used later in the process to help form the lower step of the SiGe layer. Silicon body1300is etched so as to leave a thin layer (e.g., approximately 10 nm thick) of silicon remaining.

Referring toFIG. 18, oxide spacer1501is removed (for example, using diluted HF wet etching), in preparation for forming a SiGe layer over the step regions1401,1701.

Referring toFIG. 19, in situ Boron-doped SiGe is epitaxially grown on the recessed step regions1401,1701, resulting in a SiGe layer1901that is approximately 60-70 nm in thickness. Boron in SiGe is diffused into silicon body1300, and then P-type diffusion layer1305is extended downward to the BOX (not shown). Thus, due to the shape of step regions1401and1701, SiGe layer1901itself forms into a shape having an upper step1902and a lower step1903. Of course, depending upon the process, any number of steps may be formed.

Referring toFIG. 20, first SiN spacer1304and SiN cap1302are removed (for example, by hot H3PO4 wet etching) to expose the top of polysilicon gate1301.

Referring toFIG. 21, a second SiN spacer2101is formed on re-oxidation layer1306and a portion of SiGe layer1901using, for example, conventional blanket RIE, in order to separate gate1301from source/drain regions1305.

Referring toFIG. 22, a deposition of nickel silicide2201is formed on gate1301, re-oxidation layer1306, and source/drain regions1305, following silicidation annealing. The remaining pure nickel is removed, such as by wet etching.

Thus, new structures, and methods for making such structures, have been described, that allow substantial compressive stress to be placed on a PFET channel without necessarily substantially degrading the properties of the PFET channel.