Systems and methods for designing dummy patterns

Systems and methods for designing a dummy pattern layout for improving surface flatness of a wafer are provided. An exemplary system includes at least one processor and at least one memory storing instructions. The instructions, when executed by the at least one processor, cause the at least one processor to perform operations. The operations include identifying a feature pattern corresponding to a functional region of the wafer. The operations also include determining a property of the feature pattern based on a script associated with the feature pattern. The operations further include determining a dummy pattern rule based on the property of the feature pattern. Moreover, the operations include generating a dummy pattern corresponding to a vacant region of the wafer by wrap-filling dummy units in an adjacent area surrounding the feature pattern based on the dummy pattern rule.

BACKGROUND

Embodiments of the present disclosure relate to computer assisted design-for-manufacturing (DFM) and electronic design automation (EDA) in semiconductor design, and more particularly, to application of dummy patterns in semiconductor design such as three-dimensional (3D) memory device design.

DFM refers to a process of designing or engineering a product in light of facilitating the manufacturing process in order to reduce its manufacturing costs. DFM will allow potential problems to be fixed in the design phase which is the least expensive place to address them. In semiconductor industry, DFM involves defining clearance and/or tolerance among parts and components of a semiconductor device, ensuring flatness of interfaces between layers, etc.

DFM is often implemented using EDA tools, which include software tools for designing electronic systems such as integrated circuits and printed circuit boards. The tools work together in a design flow that chip designers use to design and analyze entire semiconductor chips. Since a modern semiconductor chip can have billions of components, EDA tools are essential for their design.

SUMMARY

In one example, a system is provided for designing a dummy pattern layout for improving surface flatness of a wafer. The system may include at least one processor and at least one memory storing instructions. The instructions, when executed by the at least one processor, may cause the at least one processor to perform operations. The operations may include identifying a feature pattern corresponding to a functional region of the wafer. The operations may also include determining a property of the feature pattern based on a script associated with the feature pattern. The operations may further include determining a dummy pattern rule based on the property of the feature pattern. Moreover, the operations may include generating a dummy pattern corresponding to a vacant region of the wafer by wrap-filling dummy units in an adjacent area surrounding the feature pattern based on the dummy pattern rule.

In another example, a method is provided for designing a dummy pattern layout for improving surface flatness of a wafer. The method may include identifying a feature pattern corresponding to a functional region of the wafer. The method may also include determining a property of the feature pattern based on a script associated with the feature pattern. The method may further include determining a dummy pattern rule based on the property of the feature pattern. Moreover, the method may include generating a dummy pattern corresponding to a vacant region of the wafer by wrap-filling dummy units in an adjacent area surrounding the feature pattern based on the dummy pattern rule.

In a further example, a non-transitory computer-readable medium is provided.

The non-transitory computer-readable medium may store a set of instructions. The instructions, when executed by at least one processor of an electronic device, may cause the electronic device to perform a method for designing a dummy pattern layout for improving surface flatness of a wafer. The method may include identifying a feature pattern corresponding to a functional region of the wafer. The method may also include determining a property of the feature pattern based on a script associated with the feature pattern. The method may further include determining a dummy pattern rule based on the property of the feature pattern. Moreover, the method may include generating a dummy pattern corresponding to a vacant region of the wafer by wrap-filling dummy units in an adjacent area surrounding the feature pattern based on the dummy pattern rule.

DETAILED DESCRIPTION

As used herein, the term “3D memory device” refers to a semiconductor device with vertically oriented strings of memory cell transistors (also referred to as “memory strings,” such as NAND memory strings) on a laterally-oriented substrate so that the memory strings extend in the vertical direction with respect to the substrate. As used herein, the term “vertical/vertically” means nominally perpendicular to the lateral surface of a substrate.

In 3D memory device fabrication, a chemical mechanical polishing/planarization (CMP) process is often used to remove excess conductive and/or dielectric materials from the wafer surface and/or to smooth the wafer surface. The CMP process uses an abrasive and corrosive chemical slurry in conjunction with a polishing pad and retaining ring, typically of a greater diameter than the wafer. The pad and wafer are pressed together by a dynamic polishing head and held in place by the retaining ring. The dynamic polishing head is rotated with different axes of rotation to remove materials and tends to even out any irregular topography, making the wafer flat or planar.

In practice, CMP processes often cause erosion (e.g., to dielectric materials) and dishing (e.g., to metal) due to over-polishing. Erosion and dishing cause non-uniformity on the surface of the wafer. Some processes in semiconductor device (e.g., 3D memory device) fabrication, such as hybrid bonding, require a high degree of uniformity on the bonding interface, thereby susceptive to the adverse effects of erosion and dishing. It is difficult for current systems to meet the high degree of uniformity required by such processes. Therefore, in order to improve the bonding performance, it is needed to reduce the adverse effects caused by erosion and dishing and to improve the surface flatness of the wafer. Embodiments of the present disclosure provide systems and methods that address the aforementioned problems.

The erosion and dishing effects depend on the uniformity of patterns formed on the wafer. A pattern refers to an arrangement of parts or components of a semiconductor device, including, for example, conductive and/or dielectric materials deposited on a substrate or formed on a layer above the substrate, metal traces interconnecting semiconductor components within one layer or across multiple layers, etc. Some functional parts or components occupy a region of a semiconductor wafer, exhibiting a pattern consisting of various shapes, such as lines, blocks, spots, segments, etc. Such a region of the wafer may be referred to as a functional region, and the pattern may be referred to as a feature pattern or design pattern, indicating that the pattern embodies the design features associated with the underlying semiconductor device, such as a 3D memory device.

Because feature patterns normally do not occupy the entire surface area of a wafer, the vacant regions, due to the lack of feature patterns, would cause large density changes if left unsettled, thereby causing erosion and dishing problems. To reduce the erosion and dishing effects, dummy patterns are added to the vacant regions to bridge the discontinuity between feature patterns.FIG. 1Aillustrates an exemplary scheme for adding dummy patterns in the vacant regions of a wafer according to related art. Referring toFIG. 1A, an area100(e.g., a cell) on the wafer surface may contain a first feature pattern110and a second feature pattern112. Each feature pattern may include a plurality of feature units represented by shadowed blocks. A feature unit may include any type of functional component, such as a portion of a conductive or dielectric material, a segment of a metal trace, or the like. It is noted that a feature unit may take any shape and size, not necessarily as square blocks shown inFIG. 1A. Dummy patterns are represented using blank blocks inFIG. 1A, including a plurality of dummy units130(also referred to as dummies for simplicity). A dummy unit may be made of any suitable material (e.g., dielectric, conductive, etc.) and may take any shape and size. Therefore, it is understood that the square blocks shown inFIG. 1Aare exemplary and for illustration purpose only.

In the exemplary scheme shown inFIG. 1A, dummy patterns are formed by filling dummy units within area100from a predetermined starting location, such as a corner location120or a center location122. For example, dummy units may be filled starting from corner location120of area100(e.g., a cell on the wafer) toward an opposite corner location in a row-by-row or column-by-column fashion. In another example, dummy units may be filled starting from center location122of area100toward the boundary, again in a row-by-row or column-by-column fashion. When the dummy units are filled to a region close to a feature pattern, certain placement restrictions may be checked and satisfied, such as the minimum clearance between the dummy units and the feature units. Because dummy units are filled from a fixed location, without taking into consideration the locations of the feature patterns, large gaps between dummy and feature patterns may occur. For example, assume that dummy units inFIG. 1Aare filled from corner location120column-by-column and proceed from left to right, when the dummy units reach feature pattern112, it is determined that the clearance140is not large enough to fit an extra column of dummy units. As a result, a gap150is formed between the dummy pattern and feature pattern112. The change in density due to gap150may cause erosion or dishing during a CMP process that is unsuitable for later-stage processes, such as hybrid bonding.

FIG. 1Billustrates an exemplary dummy pattern layout160having multiple gaps162(thereby causing abrupt density changes) and a resulting bonding interface170obtained via atomic force microscopy (AFM). As shown inFIG. 1B, bonding interface170exhibits a relatively high degree of nonuniformity, indicated by the high contrast between bright spots (corresponding to feature units180) and dark spots (corresponding to dummy units190) throughout the bonding interface. In semiconductor fabrication processes requiring a high degree of uniformity such as hybrid bonding, using bonding interface170may not achieve satisfactory bonding performance.

To alleviate the abrupt density change illustrated inFIGS. 1A and 1B, embodiments of the present disclosure provides systems and methods for designing a dummy pattern layout with controllable density gradients such that the density change is gradual throughout the entire wafer region (e.g., a cell or a chip region) subject to CMP. The block diagram of an exemplary system200is shown inFIG. 2. An exemplary dummy pattern layout generated by system200is shown inFIG. 3. The flowchart of an exemplary method400for designing dummy patterns, such as those shown inFIG. 2, is illustrated inFIG. 4. In the following,FIGS. 2-4will be described together. It is understood that the operations shown in method400are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown inFIG. 4. Systems and methods disclosed herein are applicable to any semiconductor design application that involves wafer surface planarization, such as design-for-manufacturing (DFM), electronic design automation (EDA), semiconductor process simulation, optimization, and/or validation.

Referring toFIG. 2, system200may include a memory230configured to store one or more computer instructions that, when executed by at least one processor, can cause system200to perform various operations disclosed herein. Memory230may be any non-transitory type of mass storage, such as volatile or non-volatile, magnetic, semiconductor-based, tape-based, optical, removable, non-removable, or other type of storage device or tangible computer-readable medium including, but not limited to, a ROM, a flash memory, a dynamic RAM, and a static RAM.

System200may further include a processor210configured to perform the operations in accordance with the instructions stored in memory230. Processor210may include any appropriate type of general-purpose or special-purpose microprocessor, digital signal processor, or microcontroller. Processor210may be configured as a separate processor module dedicated to performing one or more specific operations. Alternatively, processor210may be configured as a shared processor module for performing other operations unrelated to the one or more specific operations disclosed herein. As shown inFIG. 2, processor210may include multiple modules, such as a feature pattern analyzer212, a dummy pattern generator214, a dummy pattern verification unit216, and the like. These modules (and any corresponding sub-modules or sub-units) can be hardware units (e.g., portions of an integrated circuit) of processor210designed for use with other components or to execute a part of a program. AlthoughFIG. 2shows modules212-216all within one processor210, it is contemplated that these modules may be distributed among multiple processors located close to or remotely with each other.

System200may also include a communication interface220. Communication interface220may include any type of communication adaptor, such as an integrated services digital network (ISDN) card, cable modem, satellite modem, or a modem to provide a data communication connection. As another example, communication interface220may include a local area network (LAN) card to provide a data communication connection to a compatible LAN. Wireless links can also be implemented by communication interface220. In such an implementation, communication interface220can send and receive electrical, electromagnetic or optical signals that carry digital data streams representing various types of information via a network. The network can typically include a cellular communication network, a Wireless Local Area Network (WLAN), a Wide Area Network (WAN), or the like. In some embodiments, communication interface220may also include input/output interfaces, such as display interface (e.g., HDMI, DVI, VGA, etc.), audio interface, keyboard interface, mouse interface, printer interface, touch screen interface, etc.

Communication interface220may be configured to exchange information between system200and one or more other systems/devices. For example, communication interface220may communicate with a database240, which may store information about semiconductor device design and/or fabrication, such as mask information, wafer information, feature pattern information, or the like. In some embodiments, processor210may receive information stored in database240through communication interface220. In some embodiments, dummy patterns generated by processor210may be sent to database240for storage.

In another example, a display250may be coupled to system200through communication interface220. Display250may include a Liquid Crystal Display (LCD), a Light Emitting Diode Display (LED), a plasma display, or any other type of display, and provide a Graphical User Interface (GUI) presented on the display for user input and data depiction. The display may include a number of different types of materials, such as plastic or glass, and may be touch-sensitive to receive inputs from the user. For example, the display may include a touch-sensitive material that is substantially rigid, such as Gorilla Glass™, or substantially pliable, such as Willow Glass™. In some embodiments, information about feature patterns and/or dummy patterns may be displayed on display250. In some embodiments, an alert may be triggered and shown on display250after one or more operations performed by processor210are completed.

In a further example, a terminal device260may be coupled to system200through communication interface220. Terminal device260may include a desktop computer, a workstation, a laptop computer, a mobile phone, a tablet, a wearable device, or any other type of device configured to perform computational tasks. In some embodiments, a user may use terminal device260to control system200, for example, to initiate, monitor, or terminate operations related to design, analyze, or generate dummy patterns. In some embodiments, terminal device260may receive dummy pattern layout generated by system200. In some embodiments, terminal device260may receive notification or alerts indicating the status of operations performed by processor210. For example, a signal indicating a generated dummy pattern layout passes a validation process may be communicated to terminal device260through communication interface220. In another example, a signal indicating a generated dummy pattern fails the validation process may be communicated to terminal device260, and terminal device260may initiate another dummy pattern design task to generate an alternative layout.

It is noted that one or more of database240, display250, and/or terminal device260may be part of system200, and may be co-located with system200or located remotely with respect to system200and communicated with system200via a network or any suitable type of communicate link.

Referring toFIG. 4, method400may be performed by processor210. For example, instructions implementing method400may be stored in memory230and executed by processor210. It is contemplated that any step of method400can be performed by processor210alone or jointly by multiple processors. In the following, processor210is used as an example in describing the steps of method400. Method400may include multiple steps, as described below. It is to be appreciated that some of the steps may be optional to perform the embodiments provided herein. Further, some of the steps may be performed simultaneously, or in a different order than shown inFIG. 4.

In step402, processor210may identify a feature pattern corresponding to a functional region of a wafer. For example, processor210may receive feature pattern layout information in an area (e.g., a cell) of the wafer from, for example, database240through communication interface220. An exemplary area300including feature patterns310and320is shown inFIG. 3. Area300may be a cell or a region that contains functional components of a semiconductor device. In some embodiments, the feature pattern layout information may be contained in an electronic file with a proper format, such as an electronic design automation (EDA) file. After receiving the feature pattern layout information, feature pattern analyzer212may analyze the information to identify one or more feature patterns, such as feature patterns310and320shown inFIG. 3. For example, feature pattern analyzer212may identify a feature pattern based on the content of the electronic file, physical layout information, and/or mask information for forming the feature pattern.

After one or more feature patterns are identified by feature pattern analyzer212, method400proceeds to step404, in which processor210may determine a property of the feature pattern. For example, feature pattern analyzer212may determine the property of the feature pattern based on a script associated with the feature pattern, such as an EDA script defining the feature pattern. In some embodiments, feature pattern analyzer212may analyze the EDA script to determine properties such as the size of a feature unit, the pitch (e.g., distance or clearance) between feature units, a density of the feature pattern, or the like. As shown inFIG. 3, feature pattern analyzer212may determine the size322of one or more feature units forming feature pattern320. In another example, feature pattern analyzer212may also determine the pitch324between adjacent feature units. In a further example, feature pattern analyzer212may determine the density of feature pattern320(e.g., in terms of the number of feature units per unit area, the number of feature units per unit length, the size and pitch of the feature units, etc.).

In step406, processor210may determine a dummy pattern rule based on the property of the feature pattern. For example, dummy pattern generator214may determine a dummy pattern rule based on one or more properties determined by feature pattern analyzer212. In some embodiments, the dummy pattern rule may include a density of the dummy pattern. For example, based on size322and/or pitch324, dummy pattern generator214may determine the density of the feature pattern (e.g., in terms of the number of feature units per unit area, the number of feature units per unit length, the size and pitch of the feature units, etc.). In another example, the density of the feature pattern may be determined by feature pattern analyzer212and provided to dummy pattern generator214. In either case, dummy pattern generator214may determine the density of the dummy pattern to be filled in the vacant regions of area300based on the density of the feature pattern. In some embodiments, the density of the dummy pattern may be determined to be substantial the same as or close to the density of the feature pattern to ensure gradual change (if at all) or even no substantial change of the density from the feature pattern to the dummy pattern. For example, the difference between the densities of the dummy pattern and the feature pattern may be controlled to be within a predetermined margin (e.g., less than 20%, less than 15%, less than 10%, less than 5%, less than 2%, less than 1%, etc.). In this way, large or abrupt density change may be alleviated or even avoided.

In step408, dummy pattern generator214may generate a dummy pattern corresponding to a vacant region of the wafer by wrap-filling dummy units in an adjacent area surrounding the feature pattern based on the dummy pattern rule. For example, referring toFIG. 3, dummy units340(represented by shadowed blocks with crossed shadow lines) may be wrap-filled around feature pattern320in the vacant region adjacent to feature pattern320such that dummy units340wrap around the entire perimeter of feature pattern320. As used herein, “wrap-filling” refers to a dummy unit filling technique that places dummy units immediately next to the outer boundary of a feature pattern over the entire outer boundary, subject to the dummy pattern rule. In some embodiments, a single loop of dummy units may be used to wrap around the feature pattern. In other embodiments, multiple layers of dummy unit loops may be used to wrap around the feature pattern. Compared to the filling scheme shown inFIG. 1A, the “wrap-filling” technique starts the dummy unit filling processing in close proximity to the feature pattern, thereby ensuring proper clearance to the feature pattern and smooth continuity of the patterns (e.g., at the transition from the feature pattern to the dummy pattern). For example, the size (represented by side length342) of the wrap-filled dummy units340may be kept substantially the same as or close to the size (represented by side length322) of the feature units in feature pattern320. In another example, pitch344of dummy units340may be kept substantially the same as or close to pitch324of the feature units in feature pattern320. In this way, the wrap-filled dummy units340act as an extension of the feature units on the outer boundary of the feature pattern320, with consistent size and/or pitch, thereby maintaining a relatively constant density transition from feature pattern320to the wrap-filled dummy pattern.

In some embodiments, multiple feature patterns may be wrap-filled first before filling other remaining vacant regions of the wafer. For example, dummy units340may wrap-fill feature pattern320. Similarly, dummy units330may wrap-fill feature pattern310. After all feature patterns are wrap-filled with dummy units, the remaining vacant regions may then be filled with additional dummy units to form the overall dummy pattern.

In some embodiments, multiple feature patterns may be classified by feature pattern analyzer212according to their design-for-manufacturing (DFM) properties (e.g., feature unit size, pitch, density, etc.) into different groups. Each group may be associated with a dummy pattern rule determined by dummy pattern generator214. Wrap-filling of dummy units may be performed to each group according to the corresponding dummy pattern rule. After all groups of feature patterns have been wrap-filled with dummy units, the remaining vacant regions may then be filled with additional dummy units.

In step410, processor210may determine a density gradient between two feature patterns based on a distance between the two feature patterns and a density difference between the two feature patterns. For example, dummy pattern generator214may determine the density gradient indicating a density change of the dummy pattern from the adjacent area (e.g., area of dummy units340where the wrap-filling is performed) to an extended area (e.g., area of dummy units350) further away from feature pattern320. In some embodiments, the density gradient may be represented by a change of pitch between adjacent dummy units. As shown inFIG. 3, an example density gradient is shown in graph370, where the vertical axis represents the density D (e.g., in terms of the pitch between adjacent dummy units), and the horizontal axis x represents the distance between feature patterns310and320. The height of stems344′,352′,354′, and356′ indicates the length of the corresponding pitches344,352,354, and356, respectively. As shown inFIG. 3, pitch344in the adjacent area may be substantially the same as or close to the pitch of feature pattern320. If the same pitch is applied to all the dummy units between feature patterns310and320, it may create a gap between the dummy units when an integer number of dummy units cannot fit within the distance between the two feature patterns. To avoid this situation, the pitch can be gradually increased from the adjacent area toward the extended area, as shown by344′,352′, and354′ in graph370. The pitch may also be gradually decreased as the dummy units approach feature pattern310, as shown by354′ and356′ in graph370. In this way, a gradual change of density can be achieved, avoiding an abrupt change of density.

In some embodiments, the densities of feature patterns310and320may be different. In this case, a density gradient may be determined to gradually change the density from a first density of feature pattern310to a second density of feature pattern320. For example, assume that the pitch (a density indicator) of feature pattern310is 40 (unitless as only the relative value is considered) and the pitch of feature pattern320is 80. Assume that the distance between the two feature patterns (less the wrap-filled adjacent areas) can fit 2 dummy units, as shown by dummy units350inFIG. 3. Then, the three pitches356,354, and352can be set to be 50, 60, and 70, to provide a gradual change of pitch from 40 (pitch of feature pattern310) to 80 (pitch of feature pattern320). Of course, any method that can achieve a gradual change of density can be used.

In some embodiments, density gradient can also be controlled by changing the size of the dummy units. For example, dummy unit of difference sizes may be used instead of or in conjunction with difference pitches to achieve finer control of the density gradient.

In step412, processor210may fill dummy units in the extended area based on the density gradient. For example, dummy pattern generator214may fill dummy units350in the reaming vacant area between feature patterns310and320according to the density gradient (e.g.,356,354,352, etc.). In some embodiments, all the remaining vacant regions may be filled with dummy units with controllable density distribution throughout the entire vacant area. It is noted that “filling” of a dummy unit in a vacant area may refer to a design step in which the location, shape, size, or other properties of the dummy unit are determined. The physical dummy unit, however, may or may not be formed on a semiconductor wafer. However, a semiconductor wafer having a dummy pattern layout arranged based on the design generated by the disclosed systems and methods is also within the purview of this disclosure.

In step414, processor210may verify the dummy pattern layout. For example, dummy pattern verification unit216may include a semiconductor fabrication process simulator, such as a CMP model, to check the density and topography of the dummy pattern layout generated by dummy pattern generator214. If the dummy pattern layout passes the verification process, processor210may store the dummy pattern layout design in memory230and/or database240. In some embodiments, processor210may trigger an alert to notify terminal device260and/or display a notification on display250. On the other hand, if the dummy pattern layout does not pass the verification process, a new dummy pattern design cycle may be initiated to generate a new design or refine or optimize an existing design.

Systems and methods disclosed herein reduce the erosion and dishing effects resulting from CMP processing, thereby improving the surface flatness of a wafer hosting semiconductor devices. For example, some embodiments can achieve a single hole dishing less than 30 Å, meeting the strict requirement to interface topography in later processes such as hybrid bonding. By reducing or even eliminating shape changes in pattern density through wrap-filling and imposing limits to density gradient, the disclosed systems and methods can improve the uniformity of wafer surface after CMP processing, thereby improving the bonding performing in fabricating semiconductor devices.

According to one aspect of the present disclosure, a system designing a dummy pattern layout for improving surface flatness of a wafer is provided. The system includes at least one processor and at least one memory. The memory stores instructions that, when executed by the at least one processor, cause the at least one processor to perform operations. The operations include identifying a feature pattern corresponding to a functional region of the wafer. The operations also include determining a property of the feature pattern based on a script associated with the feature pattern. The operations further include determining a dummy pattern rule based on the property of the feature pattern. Moreover, the operations include generating a dummy pattern corresponding to a vacant region of the wafer by wrap-filling dummy units in an adjacent area surrounding the feature pattern based on the dummy pattern rule.

In some embodiments, the dummy pattern rule includes a density of the dummy pattern.

In some embodiments, the operations include determining the density of the dummy pattern based on a density of the feature pattern. A difference between the densities of the dummy pattern and the feature pattern is within a predetermined margin.

In some embodiments, the operations include extending the dummy pattern from the adjacent area to an extended area further away from the feature pattern based on the dummy pattern rule.

In some embodiments, the dummy pattern rule includes a density gradient indicating a density change of the dummy pattern from the adjacent area to the extended area.

In some embodiments, the operations include determining the density gradient based on a distance between the feature pattern and a second feature pattern and a density difference between the feature pattern and the second feature pattern.

In some embodiments, the operations include filling dummy units in the extended area based on the density gradient.

In some embodiments, the property of the feature pattern includes at least one of a size or a pitch of functional units forming the feature pattern.

In some embodiments, the operations include verifying a layout of the dummy pattern using a semiconductor fabrication process simulator.

According to another aspect of the present disclosure, a method for designing a dummy pattern layout for improving surface flatness of a wafer is provided. The method includes identifying a feature pattern corresponding to a functional region of the wafer. The method also includes determining a property of the feature pattern based on a script associated with the feature pattern. The method further includes determining a dummy pattern rule based on the property of the feature pattern. Moreover, the method includes generating a dummy pattern corresponding to a vacant region of the wafer by wrap-filling dummy units in an adjacent area surrounding the feature pattern based on the dummy pattern rule.

In some embodiments, the dummy pattern rule includes a density of the dummy pattern.

In some embodiments, the method includes determining the density of the dummy pattern based on a density of the feature pattern. A difference between the densities of the dummy pattern and the feature pattern is within a predetermined margin.

In some embodiments, the method includes extending the dummy pattern from the adjacent area to an extended area further away from the feature pattern based on the dummy pattern rule.

In some embodiments, the dummy pattern rule includes a density gradient indicating a density change of the dummy pattern from the adjacent area to the extended area.

In some embodiments, the method includes determining the density gradient based on a distance between the feature pattern and a second feature pattern and a density difference between the feature pattern and the second feature pattern.

In some embodiments, the method includes filling dummy units in the extended area based on the density gradient.

In some embodiments, the property of the feature pattern includes at least one of a size or a pitch of functional units forming the feature pattern.

In some embodiments, the method includes verifying a layout of the dummy pattern using a semiconductor fabrication process simulator.

According to yet another aspect of the present disclosure, a non-transitory computer-readable medium is provided. The non-transitory computer-readable medium stores a set of instructions, when executed by at least one processor of an electronic device, cause the electronic device to perform a method for designing a dummy pattern layout for improving surface flatness of a wafer. The method includes identifying a feature pattern corresponding to a functional region of the wafer. The method also includes determining a property of the feature pattern based on a script associated with the feature pattern. The method further includes determining a dummy pattern rule based on the property of the feature pattern. Moreover, the method includes generating a dummy pattern corresponding to a vacant region of the wafer by wrap-filling dummy units in an adjacent area surrounding the feature pattern based on the dummy pattern rule.

In some embodiments, the dummy pattern rule includes a density of the dummy pattern.

In some embodiments, the method includes determining the density of the dummy pattern based on a density of the feature pattern. A difference between the densities of the dummy pattern and the feature pattern is within a predetermined margin.

In some embodiments, the method includes extending the dummy pattern from the adjacent area to an extended area further away from the feature pattern based on the dummy pattern rule.

In some embodiments, the dummy pattern rule includes a density gradient indicating a density change of the dummy pattern from the adjacent area to the extended area.

In some embodiments, the method includes determining the density gradient based on a distance between the feature pattern and a second feature pattern and a density difference between the feature pattern and the second feature pattern.

In some embodiments, the method includes filling dummy units in the extended area based on the density gradient.

In some embodiments, the property of the feature pattern includes at least one of a size or a pitch of functional units forming the feature pattern.

In some embodiments, the method includes verifying a layout of the dummy pattern using a semiconductor fabrication process simulator.