Display panel

A display panel includes a transistor array substrate which has a plurality of pixels and is formed by providing a plurality of transistors for each pixel, each of the transistor having a gate, a gate insulating film, a source, and a drain. A plurality of interconnections are formed to project to a surface of the transistor array substrate and arrayed in parallel to each other. A plurality of pixel electrodes are provided for each pixel and arrayed between the interconnections on the surface of the transistor array substrate along the interconnections. Each of a plurality of light-emitting layers is formed on each pixel electrode. A counter electrode is stacked on the light-emitting layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2004-283824, filed Sep. 29, 2004, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a display panel using a light-emitting element.

2. Description of the Related Art

Organic electroluminescent display panels can roughly be classified into passive driving types and active matrix driving types. Organic electroluminescent display panels of active matrix driving type are more excellent than those of passive driving type because of high contrast and high resolution. In a conventional organic electroluminescent display panel of active matrix display type described in, e.g., Jpn. Pat. Appln. KOKAI Publication No. 8-330600, an organic electroluminescent element (to be referred to as an organic EL element hereinafter), a driving transistor which supplies a current to the organic EL element when a voltage signal corresponding to image data is applied to the gate, and a switching transistor which performs switching to supply the voltage signal corresponding to image data to the gate of the driving transistor are arranged for each pixel. In this organic electroluminescent display panel, when a scan line is selected, the switching transistor is turned on. At this time, a voltage of level representing the luminance is applied to the gate of the driving transistor through a signal line. The driving transistor is turned on. A driving current having a magnitude corresponding to the level of the gate voltage is supplied from the power supply to the organic EL element through the drain-to-source path of the driving transistor. The organic EL element emits light at a luminance corresponding to the magnitude of the current. In the period from the end of scan line selection to the next scan line selection, the level of the gate voltage of the driving transistor is continuously held even after the switching transistor is turned off. Hence, the organic EL element emits light at a luminance corresponding to the magnitude of the driving current corresponding to the voltage.

To drive the organic electroluminescent display panel, a driving circuit is provided around it to apply a voltage to the scan lines, signal lines, and power supply lines laid on the organic electroluminescent display panel.

In the conventional organic electroluminescent display panel of active matrix driving type, interconnections such as a power supply line to supply a current to an organic EL element are patterned simultaneously in the thin-film transistor patterning step by using the material of a thin-film transistor such as a switching transistor or driving transistor. More specifically, in manufacturing the organic electroluminescent display panel, a conductive thin film as a prospective electrode of a thin-film transistor is subjected to photolithography and etching to form the electrode of a thin-film transistor from the conductive thin film. At the same time, an interconnection connected to the electrode is also formed. For this reason, when the interconnection is formed from the conductive thin film, the thickness of the interconnection equals that of the thin-film transistor.

However, the electrode of the thin-film transistor is designed assuming that it functions as a transistor. In other words, the electrode is not designed assuming that it supplies a current to a light-emitting element. Hence, the thin-film transistor is thin literally. If a current is supplied from the interconnection to a plurality of light-emitting elements, a voltage drop occurs, or the current flow through the interconnection delays due to the electrical resistance of the interconnection. To suppress the voltage drop or interconnection delay, the resistance of the interconnection is preferably low. If the resistance of the interconnection is reduced by making a metal layer serving as the source and drain electrodes of the transistor or a metal layer serving as the gate electrode thick, or patterning the metal layers considerably wide to sufficiently flow the current through the metal layers, the overlap area of the interconnection on another interconnection or conductor when viewed from the upper side increases, and a parasitic capacitance is generated between them. This retards the flow of the current. Alternatively, in a so-called bottom emission structure which emits EL light from the transistor array substrate side, light emitted from the EL elements is shielded by the interconnections, resulting in a decrease in opening ratio, i.e., the ratio of the light emission area. If the gate electrode of the thin-film transistor is made thick to lower the resistance, a planarization film (corresponding to a gate insulating film when the thin-film transistor has, e.g., an inverted stagger structure) to eliminate the step of the gate electrode must also be formed thick. This may lead to a large change in transistor characteristic. When the source and drain electrodes are formed thick, the etching accuracy of the source and drain electrodes degrades. This may also adversely affect the transistor characteristic.

BRIEF SUMMARY OF THE INVENTION

It is an object of the present invention to satisfactorily drive a light-emitting element while suppressing any voltage drop and signal delay.

A display panel according to a first aspect of the present invention comprises: a transistor array substrate which has a plurality of pixels and is formed by providing a plurality of transistors for each pixel, each of the transistor having a gate, a gate insulating film, a source, and a drain;

a plurality of interconnections which are formed to project to a surface of the transistor array substrate and arrayed in parallel to each other;

a plurality of pixel electrodes which are provided for each pixel and arrayed between the interconnections on the surface of the transistor array substrate along the interconnections;

a plurality of light-emitting layers each of which is formed on each pixel electrode; and

a counter electrode which is stacked on the light-emitting layer.

A display panel according to a second aspect of the present invention comprises: a plurality of pixel electrodes;

a plurality of light-emitting layers which are provided for said plurality of pixel electrodes, respectively;

a counter electrodes which is provided for said plurality of light-emitting layers respectively;

a plurality of driving transistors which are connected to said plurality of pixel electrodes, respectively;

a plurality of switch transistors each of which supplies a write current between a source and drain of a corresponding one of said plurality of driving transistors;

a plurality of holding transistors each of which holds a voltage between the source and a gate of a corresponding one of said plurality of driving transistors;

a plurality of feed interconnections which are formed from a conductive layer different from a layer serving as sources, drains, and gates of said plurality of driving transistors, said plurality of switch transistors, and said plurality of holding transistors and connected to the drains of said plurality of driving transistors;

a plurality of select interconnections each of which selects the switch transistor; and

a plurality of common interconnections each of which is connected to the counter electrode.

A display panel according to a third aspect of the present invention comprises: a plurality of pixel electrodes;

a light-emitting layer which is provided for each of said plurality of pixel electrodes;

a counter electrode which is provided for the light-emitting layer;

a driving transistor which is connected to each of said plurality of pixel electrode;

a switch transistor which supplies a write current between a source and drain of the driving transistor;

a holding transistor which holds a voltage between the source and gate of the driving transistor;

a select interconnection which selects the switch transistor;

a common interconnection which is formed from a conductive layer different from a layer serving as sources and drains and a layer serving as gates of the driving transistor, the switch transistor, and the holding transistor and connected to the counter electrode; and

a feed interconnection which is formed from a conductive layer different from the layer serving as the sources, drains, and gates of the driving transistor, the switch transistor, and the holding transistor and connected to the drain of the driving transistor and is thicker than the common interconnection.

A display panel according to a fourth aspect of the present invention comprises: a transistor array substrate which is formed by providing a plurality of transistors for each pixel, each transistor having a gate, a gate insulating film, and a source/drain;

a plurality of pixel electrodes which are provided in a plurality of rows on the transistor array substrate;

a first light-emitting layer which is provided on each of said plurality of pixel electrodes of a first row to emit light of a first color;

a second light-emitting layer which is provided on each of said plurality of pixel electrodes of a second row to emit light of a second color;

a third light-emitting layer which is provided on each of said plurality of pixel electrodes of a third row to emit light of a third color;

a counter electrode which is provided on the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer;

a select interconnection which has a top higher than first light-emitting layer, the second light-emitting layer, and the third light-emitting layer and selects at least one of said plurality of transistors;

a common interconnection which has a top higher than first light-emitting layer, the second light-emitting layer, and the third light-emitting layer and is connected to the counter electrode; and

a feed interconnection which has a top higher than first light-emitting layer, the second light-emitting layer, and the third light-emitting layer and is connected to said plurality of pixel electrodes of said plurality of transistors.

According to the present invention, since the interconnections can be made thick, the resistance of the interconnections can be reduced. When the resistance of the interconnections decreases, the signal delay and voltage drop can be suppressed.

DETAILED DESCRIPTION OF THE INVENTION

The best mode for carrying out the present invention will be described below with reference to the accompanying drawings. Various kinds of limitations which are technically preferable in carrying out the present invention are added to the embodiments to be described below. However, the spirit and scope of the present invention are not limited to the following embodiments and illustrated examples. In the following description, the term “electroluminescence” will be abbreviated as EL.

[Planar Layout of Display Panel]

FIG. 1is a schematic plan view showing adjacent four of a plurality of pixels3provided on an insulating substrate2of a display panel1which is operated by the active matrix driving method. In the display panel1, as for the pixels in the column direction, a plurality of red sub-pixels Pr are arrayed in the horizontal direction (row direction). A plurality of green sub-pixels Pg are arrayed in the horizontal direction. A plurality of blue sub-pixels Pb are arrayed in the horizontal direction. As for the sequence in the vertical direction (column direction), the red sub-pixel Pr, green sub-pixel Pg, and blue sub-pixel Pb are repeatedly arrayed in this order. The 1-dot red sub-pixel Pr, 1-dot green sub-pixel Pg, and 1-dot blue sub-pixel Pb are combined to form one pixel3. Such pixels3are arrayed in a matrix. In the following description, an arbitrary one of the red sub-pixel Pr, green sub-pixel Pg, and blue sub-pixel Pb is represented by a sub-pixel P. The description of the sub-pixel P applies to all the red sub-pixel Pr, green sub-pixel Pg, and blue sub-pixel Pb.

Three signal lines Yr, Yg, and Yb running in the vertical direction form one set. The combination of the three signal lines Yr, Yg, and Yb is called a signal line group4. In each signal line group4, the three signal lines Yr, Yg, and Yb are arranged close to each other. The interval between the adjacent signal line groups4is wider than that between the adjacent signal lines Yr, Yg, and Yb in each signal line group4. One signal line group4is provided in correspondence with one column of pixels3in the vertical direction. That is, the sub-pixels Pr, Pg, and Pb in one column arrayed in the vertical direction are connected to the signal lines Yr, Yg, and Yb of one signal line group4, respectively.

The first signal line Yr supplies a signal to all the red sub-pixels Pr of the column of pixels3in the vertical direction. The second signal line Yg supplies a signal to all the green sub-pixels Pg of the column of pixels3in the vertical direction. The third signal line Yb supplies a signal to all the blue sub-pixels Pb of the column of pixels3in the vertical direction.

A plurality of scan lines X run in the horizontal direction. A plurality of supply lines Z, a plurality of select interconnections89, a plurality of feed interconnections90, and a plurality of common interconnections91are provided in parallel to the scan lines X. One scan line X, one supply line Z, one feed interconnection90, one select interconnection89, and one common interconnection91are provided in correspondence with one line of pixels3in the horizontal direction. More specifically, the common interconnection91is arranged between the red sub-pixel Pr and the green sub-pixel Pg which are adjacent in the vertical direction. The scan line X and select interconnection89are arranged between the green sub-pixel Pg and the blue sub-pixel Pb which are adjacent in the vertical direction. The supply line Z and feed interconnection90are arranged between the blue sub-pixel Pb and the red sub-pixel Pr of the adjacent pixel3. The select interconnections89and feed interconnections90have the same thickness.

The scan line X supplies a signal to all the sub-pixels Pr, Pg, and Pb of the pixels3of one line arrayed in the horizontal direction. The supply line Z also supplies a signal to all the sub-pixels Pr, Pg, and Pb of the pixels3of one line arrayed in the horizontal direction.

When viewed from the upper side, the select interconnection89overlaps the scan line X in the running direction and is thus electrically connected to the scan line X. The feed interconnection90overlaps the supply line Z in the running direction and is thus electrically connected to the supply line Z.

The color of each the sub-pixels Pr, Pg, and Pb is determined by the color of light emitted from an organic EL element20(FIG. 2) (to be described later). The position of each of the sub-pixels Pr, Pg, and Pb, which is represented by a rectangle long in the horizontal direction inFIG. 1, indicates the position of a sub-pixel electrode20a(inFIG. 2) serving as an anode of the organic EL element20. More specifically, when the entire display panel1is viewed from the upper side, the plurality of sub-pixel electrodes20aare arrayed in a matrix. The 1-dot sub-pixel P is determined by one sub-pixel electrode20a. Hence, the plurality of sub-pixel electrodes20aare arrayed in the horizontal direction between the feed interconnection90and the adjacent common interconnection91. Said plurality of sub-pixel electrodes20aare arrayed in the horizontal direction between the common interconnection91and the adjacent select interconnection89. Said plurality of sub-pixel electrodes20aare arrayed in the horizontal direction between the select interconnection89and the adjacent feed interconnection90. When an insulating film which is sufficiently thick so no parasitic capacitance is generated is inserted between the signal line group4and the electrode or interconnection located above the signal line group4, the signal line group4may overlap the sub-pixel electrode20aconnected to it when viewed from the upper side. In addition, the signal line group4may overlap the sub-pixel electrode20aof one sub-pixel adjacent to the sub-pixel connected to the signal line group4when viewed from the upper side. When the display panel1has a bottom emission structure, the signal line group4preferably does not overlap the sub-pixel electrode20awhen viewed from the upper side.

When m and n are integers (m≧2, n≧2), m pixels3are arrayed in the vertical direction, and n pixels3are arrayed in the horizontal direction, the sub-pixel electrodes20aequal in number to the sub-pixels of one column, i.e., (3×m) sub-pixel electrodes20aare arrayed in the vertical direction. The sub-pixel electrodes20aequal in number to the sub-pixels of one row, i.e., n sub-pixel electrodes20aare arrayed in the horizontal direction. In this case, n signal line groups4are arranged, and m scan lines X, m supply lines Z, m select interconnections89, m feed interconnections90, and m common interconnections91are arranged. The total number of select interconnections89, feed interconnections90, and common interconnections91, which also serve as partition walls to prevent leakage of an organic compound-containing solution as a perspective organic EL layer20bof the organic EL element20(to be described later) from the sub-pixels of one row, is (3×m). To partition the organic compound-containing solution in all rows for the sub-pixels of each row, the total number of select interconnections89, feed interconnections90, and common interconnections91must be (3×m+1). To do this, a (3×m+1)th partition dummy interconnection having the same height and same length as the common interconnection91is arranged in the row direction in parallel to the select interconnections89, feed interconnections90, and common interconnections91. The select interconnections89, feed interconnections90, and common interconnections91are used as partition walls, their top portions are higher than the organic EL layer20band the liquid level of the organic compound-containing solution.

The circuit arrangement of the first to third sub-pixels Pr, Pg, and Pb will be described next with reference to the equivalent circuit diagram inFIG. 2. All the sub-pixels Pr, Pg, and Pb have the same arrangement. The organic EL element20, first to third N-channel amorphous silicon thin-film transistors (to be simply referred to as transistors hereinafter)21,22, and23, and a capacitor24are provided for the 1-dot sub-pixel Pi,j. The first transistor21will be referred to as the switch transistor21, the second transistor22will be referred to as the holding transistor22, and the third transistor23will be referred to as the driving transistor23hereinafter. InFIG. 2and the following description, the signal line Y for the red sub-pixel Pr represents the signal line Yr inFIG. 1, the signal line Y for the green sub-pixel Pg represents the signal line Yg inFIG. 1, and the signal line Y for the blue sub-pixel Pb represents the signal line Yb inFIG. 1.

In the switch transistor21, a source21sis electrically connected to the signal line Yj. A drain21dis electrically connected to the sub-pixel electrode20aof the organic EL element20, a source23sof the driving transistor23, and an upper electrode24B of the capacitor24. A gate21gis electrically connected to a gate22gof the holding transistor22, the scan line Xi, and the select interconnection89.

In the holding transistor22, a source22sis electrically connected to a gate23gof the driving transistor23and a lower electrode24A of the capacitor24. A drain22dis electrically connected to a drain23dof the driving transistor23and the supply line Zi. The gate22gis electrically connected to the gate21gof the switch transistor21and the scan line Xi.

In the driving transistor23, the source23sis electrically connected to the sub-pixel electrode20aof the organic EL element20, the drain21dof the switch transistor21, and the electrode24B of the capacitor24. The drain23dis electrically connected to the drain22dof the holding transistor22and the supply line Zi. The gate23gis electrically connected to the source22sof the holding transistor22and the lower electrode24A of the capacitor24.

A counter electrode20cserving as a cathode of the organic EL element20is electrically connected to the common interconnection91.

The sources21sof the switch transistors21of all the red sub-pixels Pr arrayed in a line in the vertical direction are electrically connected to the common signal line Yr. The sources21sof the switch transistors21of all the green sub-pixels Pg arrayed in a line in the vertical direction are electrically connected to the common signal line Yg. The sources21sof the switch transistors21of all the blue sub-pixels Pb arrayed in line in the vertical direction are electrically connected to the common signal line Yb.

The gates21gof the switch transistors21of all the sub-pixels Pr, Pg, and Pb of the pixels3of one row, which are arrayed in the horizontal direction, are electrically connected to the common scan line X. The gates22gof the holding transistors22of all the sub-pixels Pr, Pg, and Pb of the pixels3of one row, which are arrayed in the horizontal direction, are electrically connected to the common scan line X. The drains22dof the holding transistors22of all the sub-pixels Pr, Pg, and Pb of the pixels3of one row, which are arrayed in the horizontal direction, are electrically connected to the common supply line Z. The drains23dof the driving transistors23of all the sub-pixels Pr, Pg, and Pb of the pixels3of one row, which are arrayed in the horizontal direction, are electrically connected to the common supply line Z.

The planar layout of the pixel3will be described with reference toFIGS. 3 to 5.FIG. 3is a plan view mainly showing the electrodes of the red sub-pixel Pr.FIG. 4is a plan view mainly showing the electrodes of the green sub-pixel Pg.FIG. 5is a plan view mainly showing the electrodes of the blue sub-pixel Pb. For the illustrative convenience,FIGS. 3 to 5do not illustrate the sub-pixel electrode20aand counter electrode20cof the organic EL element20.

As shown inFIG. 3, in the red sub-pixel Pr viewed from the upper side, the driving transistor23is arranged along the supply line Z and feed interconnection90. The switch transistor21is arranged along the common interconnection91. The holding transistor22is arranged at a corner of the red sub-pixel Pr near the supply line Z.

As shown inFIG. 4, in the green sub-pixel Pg viewed from the upper side, the driving transistor23is arranged along the common interconnection91. The switch transistor21is arranged along the scan line X and select interconnection89. The holding transistor22is arranged at a corner of the green sub-pixel Pg near the common interconnection91.

As shown inFIG. 5, in the blue sub-pixel Pb viewed from the upper side, the driving transistor23is arranged along the scan line X. The switch transistor21is arranged along the supply line Z and feed interconnection90of the next row. The holding transistor22is arranged at a corner of the blue sub-pixel Pb near the scan line X.

As shown inFIGS. 3 to 5, in all the sub-pixels Pr, Pg, and Pb, the capacitor24is arranged along the signal line group4of the next column.

When a focus is placed on only the switch transistors21of all the sub-pixels Pr, Pg, and Pb in the entire display panel1viewed from the upper side, the plurality of switch transistors21are arrayed in a matrix. When a focus is placed on only the holding transistors22of all the sub-pixels Pr, Pg, and Pb, the plurality of holding transistors22are arrayed in a matrix. When a focus is placed on only the driving transistors23of all the sub-pixels Pr, Pg, and Pb, the plurality of driving transistors23are arrayed in a matrix.

[Layer Structure of Display Panel]

The layer structure of the display panel1will be described with reference toFIG. 6.FIG. 6is a sectional view taken along a line VI-VI inFIGS. 3 to 5.

The display panel1is formed by stacking various kinds of layers on the insulating substrate2which is optically transparent. The insulating substrate2has a flexible sheet shape or a rigid plate shape.

The layer structure of the first to third transistors21to23will be described first. As shown inFIG. 6, the switch transistor21includes the gate21g, part of a gate insulating film31, a semiconductor film21c, a channel protective film21p, impurity-doped semiconductor films21aand21b, the drain21d, and the source21s. The gate21gis formed on the insulating substrate2. The part of the gate insulating film31is formed on the gate21g. The semiconductor film21copposes the gate21gvia the part of the gate insulating film31. The channel protective film21pis formed on the central portion of the semiconductor film21c. The impurity-doped semiconductor films21aand21bare formed on two end portions of the semiconductor film21cto be spaced apart from each other and partially overlap the channel protective film21p. The drain21dis formed on the impurity-doped semiconductor film21a. The source21sis formed on the impurity-doped semiconductor film21b. The drain21dand source21scan have either a single-layer structure or a layered structure including two or more layers.

The driving transistor23includes the gate23g, part of the gate insulating film31, a semiconductor film23c, a channel protective film23p, impurity-doped semiconductor films23aand23b, the drain23d, and the source23s. The gate23gis formed on the insulating substrate2. The part of the gate insulating film31is formed on the gate23g. The semiconductor film23copposes the gate23gvia the part of the gate insulating film31. The channel protective film23pis formed on the central portion of the semiconductor film23c. The impurity-doped semiconductor films23aand23bare formed on two end portions of the semiconductor film23cto be spaced apart from each other and partially overlap the channel protective film23p. The drain23dis formed on the impurity-doped semiconductor film23a. The source23sis formed on the impurity-doped semiconductor film23b. When viewed from the upper side as shown inFIGS. 3 to 5, the driving transistor23is formed into an interdigital shape so that the channel width is large. The drain23dand source23scan have either a single-layer structure or a layered structure including two or more layers.

The holding transistor22has the same layer structure as the driving transistor23, and its sectional view is not illustrated. In all the sub-pixels Pr, Pg, and Pb, the switch transistor21, holding transistor22, and driving transistor23have the same layer structures as described above.

The layer structure of the capacitor24will be described next (FIGS. 3 to 5). The capacitor24has the lower electrode24A, a part of the gate insulating film31, and the upper electrode24B. The lower electrode24A is directly formed on the insulating substrate2. The gate insulating film31is formed on the lower electrode24A. The upper electrode24B opposes the lower electrode24A via a part of the gate insulating film31. In all the sub-pixels Pr, Pg, and Pb, the capacitors24have the same layer structures as described above.

The relationship between the layers of the transistors21to23and capacitor24, the signal lines Y, the scan lines X, and supply lines Z will be described next with reference toFIGS. 3 to 6.

Connection lines96, the gates21gof the switch transistors21, the gates22gof the holding transistors22, the gates23gof the driving transistors23, the lower electrodes24A of the capacitors24of all the sub-pixels Pr, Pg, and Pb, and all the signal lines Yr, Yg, and Yb are formed, using photolithography and etching, by patterning a conductive film formed on the entire surface of the insulating substrate2. The conductive film as the base of the connection lines96, gates21gof the switch transistors21, the gates22gof the holding transistors22, the gates23gof the driving transistors23, the electrodes24A of the capacitors24, and the signal lines Yr, Yg, and Yb will be referred to as a gate layer hereinafter.

The gate insulating film31is an insulating film common to the first to third transistors21,22,23, and capacitors24of all the sub-pixels Pr, Pg, and Pb and is formed on the entire surface. Hence, the gate insulating film31covers the gates21g,22g,23gof the transistors21,22,23, the lower electrodes24A of the capacitors24, and the signal lines Yr, Yg, and Yb.

The drains21d,22d,23dand sources21s,22s,23sof the transistors21,22,23, the upper electrodes24B of the capacitors24of all the sub-pixels Pr, Pg, and Pb, and all the scan lines X and supply lines Z are formed, using photolithography and etching, by patterning a conductive film formed on the entire surface of the gate insulating film31. The conductive film as the base of the drains21dand sources21sof the switch transistors21, the drains22dand sources22sof the holding transistors22, the drains23dand sources23sof the driving transistors23, the upper electrodes24B of the capacitors24, the scan lines X, and the supply lines Z will be referred to as a drain layer hereinafter.

One contact hole92is formed for each pixel3in the gate insulating film31at a portion overlapping the scan line X. The gate21gof the switch transistor21and the gate22gof the holding transistor22of each of the sub-pixels Pr, Pg, and Pb are electrically connected to the scan line X through the contact hole92. Another contact hole94is formed for each 1-dot sub-pixel P in the gate insulating film31at a portion overlapping the signal line Y. In all the sub-pixels Pr, Pg, and Pb, the source21sof the switch transistor21is electrically connected to the signal line Y through the contact hole94(i.e. conductor baried in the hole). One contact hole93is formed for each 1-dot sub-pixel P in the gate insulating film31at a portion overlapping the lower electrode24A. In all the sub-pixels Pr, Pg, and Pb, the source22sof the holding transistor22is electrically connected to the gate23gof the driving transistor23and the lower electrode24A of the capacitor24.

In the red sub-pixel Pr, the drains22d,23dof the second and third transistors22,23are integrated with the supply line Z. In the green sub-pixel Pg and blue sub-pixel Pb, the drains22d,23dof the transistors22,23are provided separately from the supply line Z. The drains22d,23dof the transistors22,23are electrically connected to the supply line Z in the following way.

One connection line96is provided for one pixel3to run through the pixel3in the vertical direction. The connection line96is formed by patterning the gate layer and is covered with the gate insulating film31. A contact hole97is formed in the gate insulating film31at a portion where the supply line Z overlaps the connection line96. The connection line96is electrically connected to the supply line Z through the contact hole97. In the green sub-pixel Pg, a contact hole98is formed in the gate insulating film31at a portion where the connection line96overlaps the drain23dof the driving transistor23. The connection line96is electrically connected to the drain23dof the driving transistor23through the contact hole98. In the blue sub-pixel Pb, a contact hole99is formed in the gate insulating film31at a portion where the connection line96overlaps the drain23dof the driving transistor23. The connection line96is electrically connected to the drain23dof the driving transistor23through the contact hole99. In both the green sub-pixel Pg and the blue sub-pixel Pb, the drains22d,23dof the transistors22,23are electrically connected to the supply line Z and feed interconnection90through the connection line96.

The switch transistors21, holding transistors22, driving transistors23of all the sub-pixels Pr, Pg, and Pb, and all the scan lines X and supply lines Z are covered with a protective insulating film32formed on the entire surface and made of silicon nitride or silicon oxide. The protective insulating film32is divided into rectangles at portions overlapping the scan lines X and supply lines Z. This will be described later in detail.

A planarization film33is formed on the protective insulating film32so that the three-dimensional pattern of the first to third transistors21,22,23, scan lines X, and supply lines Z is eliminated by the planarization film33. That is, the surface of the planarization film33is flat. The planarization film33is formed by hardening a photosensitive resin such as polyimide. The planarization film33is divided into rectangles at portions overlapping the scan lines X and supply lines Z. This will be described later in detail.

To use the display panel1as a bottom emission type, i.e., to use the insulating substrate2as the display screen, transparent materials are used for the gate insulating film31, protective insulating film32, and planarization film33. The layered structure from the insulating substrate2to the planarization film33is called a transistor array substrate50.

An insulating line61parallel to the scan line X is formed on the surface of the planarization film33, i.e., on the surface of the transistor array substrate50between the red sub-pixel Pr and the green sub-pixel Pg. The insulating line61is formed by hardening a photosensitive resin such as polyimide. The common interconnection91narrower than the insulating line61is formed on the insulating line61. The common interconnection91is formed by electroplating and is therefore formed to be much thicker than the signal line Y, scan line X, and supply line Z and project upward from the surface of the planarization film33. The common interconnection91preferably contains at least one of copper, aluminum, gold, and nickel.

A liquid repellent conductive layer55having water repellency/oil repellency is formed on the surface of each common interconnection91. The liquid repellent conductive layers55are formed by reducing and eliminating hydrogen atoms (H) of the thiol group (—SH) of triazyl-trithiol expressed by chemical formula (1), and oxidizing and adsorbing sulfur atoms (S) in the surfaces of the common interconnections91.

The liquid repellent conductive layer55is a film made of a layer of triazyl-trithiol molecules which are regularly arranged on the surface of the common interconnection91. For this reason, the liquid repellent conductive layer55has a very low resistance and conductivity. To make the water repellency/oil repellency more effective, a material in which an alkyl fluoride group substitutes for one or two thiol groups of triazyl-trithiol may be used in place of triazyl-trithiol.

Trenches34open and long in the horizontal direction are formed in the protective insulating film32and planarization film33to penetrate both films at portions overlapping the supply lines Z. Trenches35open and long in the horizontal direction are formed in the protective insulating film32and planarization film33to penetrate both films at portions overlapping the scan lines X. The protective insulating film32and planarization film33are divided into rectangles by the trenches34and35. The feed interconnections90are buried in the trenches34so that the feed interconnections90are formed on the supply lines Z in the trenches34and electrically connected to the supply lines Z. The select interconnections89are buried in the trenches35so that the select interconnections89are formed on the scan lined X in the trenches35and electrically connected to the scan lines X.

The select interconnections89and feed interconnections90are formed by electroplating and are therefore much thicker than the signal lines Y, scan lines X, and supply lines Z. The thickness of the select interconnection89and feed interconnection90is larger than the total thickness of the protective insulating film32and planarization film33so that the select interconnection89and feed interconnection90project upward from the upper surface of the planarization film33. Both the select interconnection89and the feed interconnection90preferably contain at least one of copper, aluminum, gold, and nickel. A hydrophobic insulating film53having water repellency and/or oil repellency is formed on the outer surface of a portion of the select interconnection89, extending from the film33. A hydrophobic insulating film54having water repellency and/or oil repellency is formed on the outer surface of a portion of the feed interconnection90, extending from film33.

The plurality of sub-pixel electrodes20aare arrayed in a matrix on the upper surface of the planarization film33, i.e., the upper surface of the transistor array substrate50. The sub-pixel electrodes20aare formed, using photolithography and etching, by patterning a transparent conductive film formed on the entire surface of the planarization film33.

The sub-pixel electrode20ais an electrode functioning as the anode of the organic EL element20. More specifically, the sub-pixel electrode20apreferably has a relatively high work function so that holes can efficiently be injected in the organic EL layer20b(to be described later). In a bottom emission structure, the sub-pixel electrode20ais transparent to visible light. The sub-pixel electrode20ais formed by using, as the major component, e.g., indium tin oxide (ITO), indium zinc oxide, indium oxide (In2O3), tin oxide (SnO3), zinc oxide (ZnO), or cadmium tin oxide (CTO).

To use the display panel1as a top emission type, i.e., to use the opposite side of the insulating substrate2as the display screen, a reflecting film having high conductivity and high visible light reflectance is preferably formed between the sub-pixel electrode20aand the planarization film33. Alternatively, the sub-pixel electrode20aitself is preferably formed as a reflecting electrode.

One contact hole88is formed for each 1-dot sub-pixel P in the planarization film33and protective insulating film32at a portion overlapped with the sub-pixel electrode20a. A conductive pad is buried in the contact hole88. In each of all the sub-pixels Pr, Pg, and Pb, the sub-pixel electrode20ais electrically connected to the upper electrode24B of the capacitor24, the drain21dof the switch transistor21, and the source23sof the driving transistor23.

The organic EL layer20bof the organic EL element20is formed on the sub-pixel electrode20a. The organic EL layer20bis a light-emitting layer of broad sense. The organic EL layer20bcontains a light-emitting material (phosphor) as an organic compound. The organic EL layer20bhas a two-layer structure in which a hole transport layer and a light-emitting layer of narrow sense are formed sequentially from the sub-pixel electrode20a. The hole transport layer is made of PEDOT (polythiophene) as a conductive polymer and PSS (polystyrene sulfonate) as a dopant. The light-emitting layer of narrow sense is made of a polyfluorene-based light-emitting material.

In the red sub-pixel Pr, the organic EL layer20bemits red light. In the green sub-pixel Pg, the organic EL layer20bemits green light. In the blue sub-pixel Pb, the organic EL layer20bemits blue light.

The organic EL layer20bis independently provided for each sub-pixel electrode20a. When viewed from the upper side, said plurality of organic EL layers20bare arrayed in a matrix. All sub-pixels of one row, which are arrayed in the horizontal direction between the feed interconnection90and the common interconnection91, are the red sub-pixels Pr. Hence, said plurality of sub-pixel electrodes20aarrayed in the horizontal direction between the feed interconnection90and the common interconnection91may be covered with the common organic EL layer20bfor red light emission, which has a long band shape in the horizontal direction. At this time, the organic EL layer20bhas such an electric resistance that no current flows to the organic EL layer20badjacent in the horizontal direction. Similarly, the plurality of sub-pixel electrodes20aarrayed in the horizontal direction between the common interconnection91and the select interconnection89may be covered with the common organic EL layer20bfor green light emission, which has a long band shape in the horizontal direction. The plurality of sub-pixel electrodes20aarrayed in a predetermined row in a line in the horizontal direction between the select interconnection89and the feed interconnection90of the next row (one row after) may be covered with the common organic EL layer20bfor blue light emission, which has a long band shape in the horizontal direction.

The organic EL layer20bis formed by wet coating (e.g., ink-jet method) after coating of the hydrophobic insulating film54and liquid repellent conductive layer55. In this case, an organic compound-containing solution containing an organic compound as the prospective organic EL layer20bis applied to the sub-pixel electrode20a. The liquid level of the organic compound-containing solution is higher than the top of the insulating line61. The thick select interconnection89, feed interconnection90, and common interconnection91whose tops are much higher than that of the insulating line61are formed between the sub-pixel electrodes20aadjacent in the vertical direction to project respect to the surface of the transistor array substrate50. Hence, the organic compound-containing solution applied to a sub-pixel electrode20ais prevented from leaking to the sub-pixel electrodes20aadjacent in the vertical direction. In addition, the select interconnection89, feed interconnection90, and common interconnection91are respectively coated with the hydrophobic insulating film53, hydrophobic insulating film54, and liquid repellent conductive layer55having water repellency and/or oil repellency, which repel the organic compound-containing solution applied to the sub-pixel electrode20a. The organic compound-containing solution applied to the sub-pixel electrode20ais never deposited excessively thick near the end of the liquid repellent conductive layer55, the end of the hydrophobic insulating film53, and the end of the hydrophobic insulating film54as compared to the center of the sub-pixel electrode20a. Hence, the organic EL layer20bformed by drying the organic compound-containing solution can have a uniform thickness in a plane.

The organic EL layer20bneed not always have the above-described two-layer structure. A three-layer structure including a hole transport layer, a light-emitting layer of narrow sense, and an electron transport layer formed sequentially from the sub-pixel electrode20amay be employed. Alternately, a single-layer structure including a light-emitting layer of narrow sense may be used. A layered structure having an electron or hole injection layer inserted between appropriate layers in one of the above layer structures may be employed. Any other layered structures can also be used.

The counter electrode20cfunctioning as the cathode of the organic EL element20is formed on the organic EL layers20b. The counter electrode20cis a common electrode commonly formed on the entire surface for all the sub-pixels Pr, Pg, and Pb. The counter electrode20cis formed on the entire surface and covers the common interconnections91via the liquid repellent conductive layers55. For this reason, as shown in the circuit diagram inFIG. 2, the counter electrode20cis electrically connected to the common interconnections91. Each select interconnection89is coated with the hydrophobic insulating film53. Each feed interconnection90is coated with the hydrophobic insulating film54. Hence, the counter electrode20cis insulated from both the select interconnections89and the feed interconnection90.

The counter electrode20cis preferably formed from a material having a work function lower than the sub-pixel electrode20a, and for example, a single substance or an alloy containing at least one of magnesium, calcium, lithium, barium, indium, and a rare earth metal. The counter electrode20cmay have a layered structure in which the layers of various kinds of materials described above are stacked, or a layered structure in which a metal layer hard to oxidize is deposited in addition to the layers of various kinds of materials described above to lower the sheet resistance. More specifically, a layered structure including a highly pure barium layer having a low work function and provided on the interface side contacting the organic EL layer20b, and an aluminum layer provided to cover the barium layer, or a layered structure including a lithium layer on the lower side and an aluminum layer on the upper side can be used. In a top emission structure, the counter electrode20cmay be a transparent electrode having the above-described thin film with a low work function and a transparent conductive film made of, e.g., ITO on the thin film.

A sealing insulating film56is formed on the counter electrode20c. The sealing insulating film56is an inorganic or organic film provided to cover the entire counter electrode20cand prevent any degradation of the counter electrode20c.

Conventionally, in an EL display panel having a top emission structure, at least part of the counter electrode20cis formed as a transparent electrode of, e.g., a metal oxide having a high resistance value. Such a material can sufficiently reduce the sheet resistance only by increasing the thickness. When the material is thick, the transparency of the organic EL element decreases inevitably. As the screen size becomes large, a uniform potential can hardly be obtained in a plane, and the display characteristic becomes poor.

In this embodiment, however, the plurality of common interconnections91with a low resistance are provided to obtain a sufficient thickness in the horizontal direction. Hence, the sheet resistance value of the entire cathode electrodes of the organic EL elements20can be decreased together with the counter electrode20cso that a sufficiently large current can be supplied uniformly in a plane. In this structure, the common interconnection91reduce the sheet resistance of the cathode electrode. For this reason, the transmittance can be increased by forming the counter electrode20cthin. In a top emission structure, the pixel electrode20amay be made of a reflecting material.

The feed interconnections90which are formed by using a thick conductive layer except the conductive layer to form the thin-film transistors are electrically connected to the supply lines Z1to Zm. For this reason, the delay until the write current or driving current (to be described later) in the plurality of organic EL elements20reaches a predetermined current value, which is caused by the voltage drop in the supply lines Z1to Zmformed by only the conductive layer of the thin-film transistors, can be prevented, and the elements can satisfactorily be driven.

In addition, the select interconnections89which are formed by using a thick conductive layer except the conductive layer to form the thin-film transistors are electrically connected to the scan lines X1to Xm. For this reason, the signal delay caused by the voltage drop in the scan lines X1to Xmformed by only the conductive layer of the thin-film transistors can be prevented, and the switch transistors21and holding transistors22can be switched quickly and driven satisfactorily.

The display panel1can be driven by the active matrix method in the following way. As shown inFIG. 7, a select driver connected to the scan lines X1to Xmsequentially outputs a shift pulse of high level to the scan lines X1to Xmin this order (the scan line X1next to the scan line Xm), thereby sequentially selecting the scan lines X1to Xm. A feed driver is connected to the feed interconnections90. The feed driver applies a write feed voltage VL to supply a write current to the driving transistors23connected to the supply lines Z1to Zmthrough the feed interconnections90in a selection period. The feed driver applies a driving feed voltage VH to supply a driving current to the organic EL elements20through the driving transistors23in a light emission period. The feed driver sequentially outputs the write feed voltage VL of low level (lower than the voltage of the counter electrode of the organic EL elements20) to the supply lines Z1to Zmin this order (the supply line Z1next to the supply line Zm) in synchronism with the select driver, thereby sequentially selecting the supply lines Z1to Zm. While the select driver is selecting the scan lines X1to Xm, a data driver supplies a write current (current signal) to all the signal lines Y1to Ynthrough the drain-to-source paths of the driving transistors23of a predetermined row. At this time, the feed driver outputs the write feed voltage VL of low level from both the interconnection terminals at the two ends of each feed interconnection90, located on the left and right ends of the insulating substrate2to the feed interconnections90connected to the supply lines Z1to Zm. The counter electrode20cand common interconnections91are connected to an external device through the interconnection terminals portions and held at a predetermined common potential Vcom (e.g., ground=0 V).

The direction in which the signal lines Y1to Ynrun is called the vertical direction (column direction). The direction in which the scan lines X1to Xmrun is called the horizontal direction (row direction). In this case, m and n are natural numbers (m≧2, n≧2). The subscript added to the scan line X represents the sequence from the top inFIG. 1. The subscript added to the supply line Z represents the sequence from the top inFIG. 1. The subscript added to the signal line Y represents the sequence from the left inFIG. 1. The first subscript added to the pixel circuit P represents the sequence from the top, and the second subscript represents the sequence from the left. More specifically, let i be an arbitrary natural number of 1 to m, and j be an arbitrary natural number of 1 to n. A scan line Xiis the ith row from the top, a supply line Ziis the ith row from the top, a signal line Yjis the jth column from the left, and a pixel circuit Pi,jis located on the ith row from the top and the jth column from the left. The pixel circuit Pi,jis connected to the scan line Xi, supply line Zi, and signal line Yj.

The pixel circuit Pi,jcomprises the organic EL element20serving as a pixel, the first to third N-channel amorphous silicon thin-film transistors (to be simply referred to as transistors hereinafter)21,22, and23arranged around the organic EL element20, and the capacitor24.

In each selection period, the potential on the data driver side is equal to or lower than the write feed voltage VL output to the feed interconnections90and the supply lines Z1to Zm. The write feed voltage VL is set to be equal to or lower than the common potential Vcom. At this time, no current flows from the organic EL elements20to the signal lines Y1to Yn. As shown inFIG. 2, a write current (pull-out current) having a current value corresponding to the gray level is supplied from the data driver to the signal lines Y1to Yn, as indicated by an arrow A. In the pixel circuit Pi,j, the write current (pull-out current) to the signal line Yjflows from the feed interconnection90and supply line Zithrough the drain-to-source path of the driving transistor23and the drain-to-source path of the switch transistor21. The current value of the current flowing through the drain-to-source path of the driving transistor23is uniquely controlled by the data driver. The data driver sets the current value of the write current (pull-out current) in accordance with an externally input gray level. While the write current (pull-out current) is flowing, the voltage between the gate23gand source23sof the driving transistor23of each of pixel circuits Pi,1to Pi,nof the ith row is forcibly set in accordance with the current value of the write current (pull-out current) flowing to the signal lines Y1to Yn, i.e., the current value of the write current (pull-out current) flowing between the drain23dand source23sof the driving transistor23independently of the change over time in the Vg-Ids characteristic of the driving transistor23. Charges with a magnitude corresponding to the level of this voltage are stored in the capacitor24so that the current value of the write current (pull-out current) is converted into the voltage level between the gate23gand source23sof the driving transistor23. In the subsequent light emission period, the scan line Xichanges to low level so that the switch transistor21and holding transistor22are turned off. The charges on the side of the electrode24A of the capacitor24are confined by the holding transistor22in the OFF state, and a floating state is set. Hence, even when the voltage of the source23sof the driving transistor23is modulated at the time of transition from the selection period to the light emission period, the potential difference between the gate23gand source23sof the driving transistor23is maintained. In the light emission period, the potential of the supply line Ziand the feed interconnection90connected to it equals the driving feed voltage VH which is higher than the potential Vcom of the counter electrode20cof the organic EL element20. Hence, a driving current flows from the supply line Ziand the feed interconnection90connected to it to the organic EL element20in the direction of arrow B through the driving transistor23. Hence, the organic EL element20emits light. The current value of the driving current depends on the voltage between the gate23gand source23sof the driving transistor23. For this reason, the current value of the driving current in the light emission period equals the current value of the write current (pull-out current) in the selection period.

Another active matrix driving method of the display panel1will be described next. As shown inFIG. 8, an oscillation circuit outputs a clock signal to the feed interconnections90and thus supply lines Z1to Zm. The select driver sequentially outputs a shift pulse of high level to the scan lines X1to Xmin this order (the scan line X1next to the scan line Xm), thereby sequentially selecting the scan lines X1to Xm. While the select driver is outputting the shift pulse to one of the scan lines X1to Xm, the clock signal from the oscillation circuit changes to low level. When the select driver selects the scan lines X1to Xm, the data driver supplies a pull-out current (current signal) as the write current to all the signal lines Y1to Ynthrough the drain-to-source paths of the driving transistors23. The counter electrode20cand feed interconnections90are held at the predetermined common potential Vcom (e.g., ground=0 V).

In the selection period of the scan line Xi, the shift pulse is output to the scan line Xiof the ith row so that the switch transistor21and holding transistor22are turned on. In each selection period, the potential on the data driver side is equal to or lower than the clock signal output to the feed interconnections90and supply lines Z1to Zm. The low level of the clock signal is set to be equal to or lower than the common potential Vcom. At this time, no current flows from the organic EL elements20to the signal lines Y1to Yn. As shown inFIG. 2, a write current (pull-out current) having a current value corresponding to the gray level is supplied from the data driver to the signal lines Y1to Yn, as indicated by the arrow A. In the pixel circuit Pi,j, the write current (pull-out current) to the signal line Yjflows from the feed interconnection90and supply line Zithrough the drain-to-source path of the driving transistor23and the drain-to-source path of the switch transistor21. The current value of the current flowing through the drain-to-source path of the driving transistor23is uniquely controlled by the data driver. The data driver sets the current value of the write current (pull-out current) in accordance with an externally input gray level. While the write current (pull-out current) is flowing, the voltage between the gate23gand source23sof the driving transistor23of each of the pixel circuits Pi,1to Pi,nof the ith row is forcibly set in accordance with the current value of the write current (pull-out current) flowing to the signal lines Y1to Yn, i.e., the current value of the write current (pull-out current) flowing between the drain23dand source23sof the driving transistor23independently of the change over time in the Vg-Ids characteristic of the transistor23. Charges with a magnitude corresponding to the level of this voltage are stored in the capacitor24so that the current value of the write current (pull-out current) is converted into the voltage level between the gate23gand source23sof the driving transistor23. In the subsequent light emission period, the scan line Xichanges to low level so that the switch transistor21and holding transistor22are turned off. The charges on the side of the electrode24A of the capacitor24are confined by the holding transistor22in the OFF state, and a floating state is set. Hence, even when the voltage of the source23sof the driving transistor23is modulated at the time of transition from the selection period to the light emission period, the potential difference between the gate23gand source23sof the driving transistor23is maintained. Of the selection period, in a period in which no row is selected, i.e., the clock signal is at high level, and the potential of the feed interconnection90and supply line Ziis higher than the potential Vcom of the counter electrode20cof the organic EL element20and the feed interconnection90, the driving current flows from the feed interconnection90and thus supply line Ziwith a higher potential to the organic EL element20through the drain-to-source path of the driving transistor23in the direction of arrow B. Hence, the organic EL element emits light. The current value of the driving current depends on the voltage between the gate23gand source23sof the driving transistor23. For this reason, the current value of the driving current in the light emission period equals the current value of the write current (pull-out current) in the selection period. Of the selection period, in a period in which any row is selected, i.e., the clock signal is at low level, the potential of the feed interconnection90and thus supply line Ziis equal to or lower than the potential Vcom of the counter electrode20cand feed interconnection90. Hence, no driving current flows to the organic EL element20, and no light emission occurs.

In either driving method as described above, the switch transistor21functions to turn on (selection period) and off (light emission period) of the current between the signal line Yjand the source23sof the driving transistor23. The holding transistor22functions to make it possible to supply the current between the source23sand drain23dof the driving transistor23in the selection period and hold the voltage between the gate23gand source23sof the transistor23in the light emission period. The driving transistor23functions to drive the organic EL element20by supplying a current having a magnitude corresponding to the gray level to the organic EL element20.

As described above, the magnitude of the current flowing to the feed interconnection90equals the sum of the magnitudes of driving currents flowing to the n organic EL elements20connected to the supply line Ziof one column. When a selection period to do moving image driving using pixels for VGA or more is set, the parasitic capacitance of each feed interconnection90increases. The resistance of an interconnection formed from a thin film which forms the gate electrode or the source/drain electrode of a thin-film transistor is so high that the write current (driving current) cannot be supplied to the n organic EL elements20. In this embodiment, the feed interconnections90are formed from a conductive layer different from the gate electrodes or the source/drain electrodes of thin-film transistors of the pixel circuits Pi,1to Pm,n. For this reason, the voltage drop by the feed interconnections90is small. Even in a short selection period, the write current (pull-out current) can sufficiently be supplied without any delay. Since the resistance of the feed interconnection90is lowered by thickening it, the feed interconnection90can be made narrow. In a bottom emission structure, the decrease in pixel opening ratio can be minimized.

Similarly, the magnitude of the driving current flowing to the common interconnection91in the light emission period equals that of the write current (pull-out current) flowing to the feed interconnection90in the selection period. Since the common interconnections91use a conductive layer different from the gate electrodes or the source/drain electrodes of the first to third thin-film transistors of the pixel circuits Pi,lto Pm,n, the common interconnection91can be made sufficiently thick, and its resistance can be lowered. In addition, even when the counter electrode20citself becomes thin and increases its resistance, the voltage of the counter electrode20ccan be uniformed in a plane. Hence, even if the same potential is applied to all the pixel electrodes20a, the light emission intensities of the organic EL layers20balmost equal, and the light emission intensity in a plane can be uniformed.

When the EL display panel1is used as a top emission type, the counter electrode20ccan be made thinner. Hence, light emitted from the organic EL layer20bhardly attenuates while passing through the counter electrode20c. Additionally, since the common interconnections91are respectively provided between the pixel electrodes20aadjacent in the horizontal direction when viewed from the upper side, the decrease in pixel opening ratio can be minimized.

[Widths, Sectional Areas, and Resistivities of Feed Interconnection and Common Interconnection]

When the display panel is driven by the latter of the above-described two driving methods, the feed interconnections90are electrically connected to each other by the first lead interconnection arranged at one edge of the insulating substrate2and are therefore set to an equipotential by the external clock signal. The first lead interconnection is connected to the interconnection terminals at the two ends of the insulating substrate2. Since the voltages applied from external driving circuits to the interconnection terminals are equipotential, the current can quickly be supplied to all the feed interconnections90.

The common interconnections91are connected to each other by the second lead interconnection arranged at an edge different from the edge of the insulating substrate2where the first lead interconnection is provided. A common voltage Vss is applied to the common interconnections91. The second lead interconnection is insulated from the first lead interconnection.

When the display panel1has pixels corresponding to WXGA (768×1366), the desired width and sectional area of the feed interconnection90and common interconnection91are defined.FIG. 9is a graph showing the current vs. voltage characteristic of the driving transistor23and organic EL element20of each sub-pixel.

Referring toFIG. 9, the ordinate represents the current value of the write current flowing between the source23sand drain23dof one driving transistor23or the current value of the driving current flowing between the anode and cathode of one organic EL element20. The abscissa represents the voltage between the drain23dand source23sof one driving transistor23(also the voltage between the gate23gand drain23dof one driving transistor23). Referring toFIG. 9, a solid line Ids max indicates a write current and driving current for the highest luminance gray level (brightest display). A one-dot dashed line Ids mid indicates a write current and driving current for an intermediate highest luminance gray level between the highest luminance gray level and the lowest luminance gray level. A two-dots dashed line Vpo indicates a threshold value between the unsaturation region (linear region) and the saturation region of the driving transistor23, i.e., the pinch-off voltage. A three-dots dashed line Vds indicates a write current flowing between the source23sand drain23dof the driving transistor23. A dot line Iel indicates a driving current flowing between the anode and cathode of the organic EL element20.

A voltage VP1is the pinch-off voltage of the driving transistor23for the highest luminance gray level. A voltage VP2is the drain-to-source voltage of the driving transistor23when a write current for the highest luminance gray level flows. A voltage VELmax (voltage VP4−voltage VP3) is the anode-to-cathode voltage when the organic EL element20emits light by a driving current of the highest luminance gray level, which has a current value equal to that of the write current for the highest luminance gray level. A voltage VP2′ is the drain-to-source voltage of the driving transistor23when a write current for the intermediate luminance gray level flows. A voltage (voltage VP4′−voltage VP3′) is the anode-to-cathode voltage when the organic EL element20emits light by a driving current of the intermediate luminance gray level, which has a current value equal to that of the write current for the intermediate luminance gray level.

To drive the driving transistor23and organic EL element20in the saturation region, a value VX obtained by subtracting (the voltage Vcom of the common interconnection91in the light emission period) from (the driving feed voltage VH of the feed interconnection90in the light emission period) satisfies
VX=Vpo+Vth+Vm+VEL(2)
where Vth (=VP2−VP1for the highest luminance) is the threshold voltage of the driving transistor23, VEL (=VEmax for the highest luminance) is the anode-to-cathode voltage of the organic EL element20, and Vm is an allowable voltage which displaces in accordance with the gray level.

As is apparent fromFIG. 9, of the voltage VX, the higher the luminance gray level is, the higher the voltage (Vpo+Vth) necessary between the source and drain of the transistor23is, and also, the higher the voltage VEL necessary between the anode and cathode of the organic EL element20is. Hence, the allowable voltage Vm becomes low as the luminance gray level becomes high. A minimum allowable voltage Vmmin is VP3−VP2.

The organic EL element20generally degrades and increases its resistance over time no matter whether a low or high molecular weight EL material. It has been confirmed that the anode-to-cathode voltage after 10,000 hrs is about 1.4 to several times that in the initial state. That is, the voltage VEL rises along with the elapse of time even when the luminance gray level does not change. The operation is stable for a long time when the allowable voltage Vm in the initial driving state is as high as possible. Hence, the voltage VX is set such that the voltage VEL becomes 8 V or more and, more preferably, 13 V or more.

The allowable voltage Vm includes not only the increase amount of the resistance of the organic EL element20but also the voltage drop by the feed interconnection90.

If the voltage drop is large because of the interconnection resistance of the feed interconnection90, the power consumption of the EL display panel1considerably increases. Hence, the voltage drop of the feed interconnection90is especially preferably set to 1 V or less.

A pixel width Wp as the row-direction length of one pixel, the number of pixels (1366) in the row direction, the extension portion from the first lead interconnection to one interconnection terminal outside the pixel region, and the extension portion from the first lead interconnection to the other interconnection terminal outside the pixel region are taken into consideration. In this case, the total length of the first lead interconnection is 706.7 mm for the display panel1with a panel size of 32 inches and 895.2 mm for 40 inches. If a line width WL of the feed interconnection90and common interconnection91is large, the area of the organic EL layer20bdecreases structurally. In addition, the overlap parasitic capacitance to other interconnections is also generated, and the voltage drop becomes larger. To prevent this, the line width WL of the feed and common interconnections90,91is preferably suppressed to ⅕ or less the pixel width Wp. In consideration of this, the line width WL is 34 μm or less for the display panel1with a panel size of 32 inches and 44 μm or less for 40 inches. A maximum thickness Hmax of the feed interconnection90and common interconnection91is 1.5 times the minimum process size (4 μm) of the first to third transistors21to23, i.e., 6 μm when the aspect ratio is taken into consideration. A maximum sectional area Smax of the feed interconnection90and common interconnection91is 204 μm2for 32 inches and 264 μm2for 40 inches.

To make the maximum voltage drop of the feed interconnection90and common interconnection911 V or less when the 32-inch display panel1is fully lighted to flow the maximum current, an interconnection resistivity ρ/sectional area S of the feed interconnection90and common interconnection91must be set to 4.7 Ω/cm or less, as shown inFIG. 10.FIG. 11shows the correlation between the sectional area and the current density of the feed interconnection and common interconnection of the 32-inch display panel1. The resistivity allowed when the above-described feed interconnection90and common interconnection91have the maximum sectional area Smax is 9.6 μΩcm for 32 inches and 6.4 μΩcm for 40 inches.

To make the maximum voltage drop of the feed interconnection90and common interconnection911 V or less when the 40-inch display panel1is fully lighted to flow the maximum current, the interconnection resistivity ρ/sectional area S of the feed interconnection90and common interconnection91must be set to 2.4 Ω/cm or less, as shown inFIG. 12.FIG. 13shows the correlation between the sectional area and the current density of the feed interconnection and common interconnection of the 40-inch display panel1.

A median time to failure MTF at which the EL display panel stops operation due to a failure in the feed interconnection90and common interconnection91satisfies
MTF=Aexp(Ea/KbT)/ρJ2(3)
where Ea is an activation energy, KbT=8.617×10−5eV, ρ is the resistivity of the feed interconnection90and common interconnection91, and J is a current density.

The median time to failure MTF of the feed interconnection90and common interconnection91is determined by an increase in resistivity or electromigration. When the feed and common interconnections90,91are set to an Al-based material (Al single substance or an alloy such as AlTi or AlNd), and calculation is done on trial for MTF of 10,000 hrs and an operation temperature of 85° C., the current density J must be 2.1×104A/cm2or less. When the feed interconnection90and common interconnection91are set to Cu, the current density J must be 2.8×106A/cm2or less. It is assumed that materials except Al in an Al alloy have a resistivity lower than Al.

In consideration of these, in the 32-inch display panel1, the sectional area S of the Al-based feed interconnection90and common interconnection91must be 57 μm2or more to prevent any failure in them in the full lighting state for 10,000 hrs, as shown inFIG. 11. The sectional area S of the feed interconnection90and common interconnection91made of Cu must be 0.43 μm2or more, as shown inFIG. 11.

In the 40-inch display panel1, the sectional area S of the Al-based feed interconnection90and common interconnection91must be 92 μm2or more to prevent any failure in them in the full lighting state for 10,000 hrs, as shown inFIG. 13. The sectional area S of the feed and common interconnections90,91made of Cu must be 0.69 μm2or more, as shown inFIG. 13.

In the 32-inch display panel1, the interconnection resistivity ρ/sectional area S of the Al-based feed interconnection90and common interconnection91is 4.7 Ω/cm or less, as described above, assuming that the resistivity of the Al-based material is 4.00 μΩcm. Hence, a minimum sectional area Smin is 85.1 μm2. Since the line width WL of the feed and common interconnections90,91is 34 μm or less, as described above, a minimum thickness Hmin of both interconnections90,91is 2.50 μm.

In the 40-inch display panel1, the interconnection resistivity ρ/sectional area S of the Al-based feed interconnection90and common interconnection91is 2.4 Ω/cm or less, as described above. Hence, the minimum sectional area Smin is 167 μm2. Since the line width WL of the interconnections90,91is 44 μm or less, as described above, the minimum thickness Hmin of the interconnections90,91is 3.80 μm.

In the 32-inch display panel1, the interconnection resistivity ρ/sectional area S of the feed interconnection90and common interconnection91made of Cu is 4.7 Ω/cm or less, as described above, assuming that the resistivity of Cu is 2.10 μΩcm. Hence, the minimum sectional area Smin is 44.7 μm2. Since the line width WL of both interconnections90,91is 34 μm or less, as described above, the minimum thickness Hmin of the interconnections90,91is 1.31 μm.

In the 40-inch display panel1, the interconnection resistivity ρ/sectional area S of the feed interconnection90and common interconnection91made of Cu is 2.4 Ω/cm or less, as described above. Hence, the minimum sectional area Smin is 87.5 μm2. Since the line width WL of both interconnections90,91is 44 μm or less, as described above, the minimum thickness Hmin of the interconnections90,91is 1.99 μm.

Hence, to cause the display panel1to operate normally at a low power consumption, the voltage drop in the feed interconnection90and common interconnection91is preferably set to 1 V or less. To set such a condition, in a 32-inch panel in which the feed interconnection90and common interconnection91are made of an Al-based material, a thickness H is 2.5 to 6.0 μm, the width WL is 14.1 to 34.0 μm, and the resistivity is 4.0 to 9.6 μΩcm. In a 40-inch panel in which both interconnections90,91are made of an Al-based material, the thickness H is 3.8 to 6.0 μm, the width WL is 27.8 to 44.0 μm, and the resistivity is 4.0 to 9.6 μΩcm.

In general, for the Al-based feed interconnection90and common interconnection91, the thickness H is 2.5 to 6.0 μm, the width WL is 14.1 to 44.0 μm, and the resistivity is 4.0 to 9.6 μΩcm.

In a 32-inch panel in which the feed interconnection90and common interconnection91are made of Cu, the thickness H is 1.31 to 6.00 μm, the width WL is 7.45 to 34.00 μm, and the resistivity is 2.1 to 9.6 μΩcm. In a 40-inch panel in which both interconnections90,91are made of Cu, the thickness H is 1.99 to 6.00 μm, the width WL is 14.6 to 44.0 μm, and the resistivity is 2.1 to 9.6 μΩcm.

In general, for the feed interconnection90and common interconnection91made of Cu, the thickness H is 1.31 to 6.00 μm, the width WL is 7.45 to 44.00 μm, and the resistivity is 2.1 to 9.6 μΩcm.

Hence, when an Al-based material or Cu is used for the feed interconnection90and common interconnection91, interconnections90,91of the EL display panel1have the thickness H of 1.31 to 6.00 μm, the width WL of 7.45 to 44.00 μm, and the resistivity of 2.1 to 9.6 μΩcm.

As described above, the common interconnections91formed to project between the lines of the red sub-pixels Pr and the lines of the green sub-pixels Pg in the horizontal direction are formed from a layer different from the electrodes of the first to third transistors21to23. Hence, the common interconnections91can be made thick and have a low resistance. The common interconnections91having a low resistance are electrically connected to the counter electrode20c. For this reason, even when the counter electrode20citself becomes thin and increases its resistance, the voltage of the counter electrode20ccan be uniformed in a plane. Hence, even if the same potential is applied to all the sub-pixel electrodes20a, the light emission intensities of the organic EL layers20balmost equal, and the light emission intensity in a plane can be uniformed.

When the display panel1is used as a top emission type, the counter electrode20ccan be made thinner. Hence, light emitted from the organic EL layer20bhardly attenuates while passing through the counter electrode20c. Additionally, since the common interconnections91are provided between the sub-pixel electrodes20aadjacent in the vertical direction when viewed from the upper side (FIG. 1), the decrease in pixel opening ratio can be minimized.

In addition, the select interconnections89formed to project between the lines of the green sub-pixels Pg and the lines of the blue sub-pixels Pb in the horizontal direction are formed from a layer different from the electrodes of the first to third transistors21to23. Hence, the select interconnections89can be made thick and have a low resistance. The common interconnections91having a low resistance are formed on the thin scan lines X. For this reason, the voltage drop in the scan lines X can be suppressed, and the signal delay in the scan lines X and select interconnections89can be suppressed. That is, when a focus is placed on the column of the sub-pixels P in the horizontal direction, the shift pulse changes to high level in all the sub-pixels P without any delay.

Since the select interconnections89are made thick to decrease the resistance, the select interconnections89can be made narrow. For this reason, the decrease in pixel opening ratio can be minimized.

Furthermore, the feed interconnections90formed to project between the lines of the blue sub-pixels Pb and the lines of the red sub-pixels Pr in the horizontal direction are formed from a layer different from the electrodes of the transistors21to23. Hence, the feed interconnections90can be made thick and have a low resistance. The feed interconnections90having a low resistance are formed on the thin supply lines Z. For this reason, the voltage drop in the supply lines Z can be suppressed, and the signal delay in the supply lines Z and feed interconnections90can be suppressed. For example, when the size of the display panel1is increased without the feed interconnections90, the light emission intensity in a plane may vary due to the voltage drop in the supply lines Z, or some organic EL elements20cannot emit light. In this embodiment, however, since the feed interconnections90having a low resistance are electrically connected to the supply lines Z, the light emission intensity in a plane can be prevented from varying, and the organic EL elements20which cannot emit light can be eliminated.

Since the feed interconnections90are made thick to decrease the resistance, the feed interconnections90can be made narrow. For this reason, the decrease in pixel opening ratio can be minimized.

Since the select interconnections89, feed interconnections90, and common interconnections91formed to project are provided thick, the organic EL layers20bcan have different colors by wet coating. Hence, no special banks to partition the sub-pixels P need be provided, and the display panel1can easily be manufactured.

The present invention is not limited to the above-described embodiment, and various changes and modifications can be made without departing from the spirit and scope of the present invention.

In the above-described embodiment, the first to third transistors21to23have been explained as N-channel field effect transistors. The transistors21to23may be P-channel field effect transistors. In this case, the relationship between the sources21s,22s, and23sof the transistors21to23and the drains21d,22d, and23dof the transistors21to23is reversed in the circuit diagram shown inFIG. 2. For example, when the driving transistor23is a P-channel field effect transistor, the drain23dof the driving transistor23is electrically connected to the sub-pixel electrode20aof the organic EL element20. The source23sis electrically connected to the supply line Z.

In the above-described embodiment, the three transistors21to23are provided per 1-dot pixel. The present invention can be applied to any display panel which has one or more driving transistors per 1-dot sub-pixel P and can be driven by using these transistors by an active driving method independently of the number of transistors and whether the panel is current-driven or voltage-driven.

In the above-described embodiment, the select interconnections89are formed to project between the rows of the green sub-pixels Pg and the rows of the blue sub-pixels Pb. However, instead of the select interconnections89, common interconnections like the common interconnections91may be formed between the rows of the green sub-pixels Pg and the rows of the blue sub-pixels Pb. Therefore, two common interconnections are formed every pixel3In this case, no trench35is formed under the common interconnection. The common interconnection is insulated from the scan line X. The surface of the common interconnection is coated with a liquid repellent conductive layer like the liquid repellent conductive layer55. The common interconnection is electrically connected to the counter electrode20c.

In the above-described embodiment, the signal line Y is patterned from the gate layer. Instead, the signal line Y may be patterned from the drain layer. In this case, the scan line X and supply line Z are patterned from the gate layer, and the signal line Y is arranged above the scan line X and supply line Z.

In the above-described embodiment, the common interconnection91is arranged between the red sub-pixel Pr and green sub-pixel Pg which are adjacent in the vertical direction. The scan line X and select interconnection89are arranged between the green sub-pixel Pg and blue sub-pixel Pb which are adjacent in the vertical direction. The supply line Z and feed interconnection90are arranged between the blue sub-pixel Pb of one of the pixels3and the red sub-pixel Pr of the adjacent pixel3. Hence, the organic EL layer20bof the red sub-pixel Pr, the organic EL layer20bof the green sub-pixel Pg, and the organic EL layer20bof the blue sub-pixel Pb are repeatedly arrayed in this order. That is, in the above-described embodiment, the supply line Z and feed interconnection90, the common interconnection91, and the scan line X and select interconnection89are repeatedly arrayed in this order. In other words, the organic EL layer20bof the red sub-pixel Pr, the organic EL layer20bof the green sub-pixel Pg, and the organic EL layer20bof the blue sub-pixel Pb are repeatedly arrayed in this order. However, they need not always be arrayed in this order. Instead, the scan line X and select interconnection89, or the supply line Z and feed interconnection90may be arranged between the red sub-pixel Pr and green sub-pixel Pg. The common interconnection91, or the supply line Z and feed interconnection90may be arranged between the green sub-pixel Pg and blue sub-pixel Pb. The common interconnection91, or the scan line X and select interconnection89may be arranged between the blue sub-pixel Pb of one of the pixels3and the red sub-pixel Pr of the adjacent pixel3.

A plurality of modifications described above may be combined.