Capacitor structure for power delivery applications

A passive discrete device may include a first asymmetric terminal and a second asymmetric terminal. The passive discrete device may further include first internal electrodes extended to electrically couple to a first side and a second side of the first asymmetric terminal. The passive discrete device may also include second internal electrodes extended to electrically couple to a first side and a second side of the second asymmetric terminal.

BACKGROUND

Field

Aspects of the present disclosure relate to semiconductor devices, and more particularly to a capacitor structure for power delivery applications.

Background

The process flow for semiconductor fabrication of integrated circuits (ICs) may include front-end-of-line (FEOL), middle-of-line (MOL), and back-end-of-line (BEOL) processes. The front-end-of-line process may include wafer preparation, isolation, well formation, gate patterning, spacer, extension and source/drain implantation, silicide formation, and dual stress liner formation. The middle-of-line process may include gate contact formation. Middle-of-line layers may include, but are not limited to, middle-of-line contacts, vias or other layers within close proximity to the semiconductor device transistors or other like active devices. The back-end-of-line process may include a series of wafer processing steps for interconnecting the semiconductor devices created during the front-end-of-line and middle-of-line processes. Successful fabrication of modern semiconductor chip products involves an interplay between the materials and the processes employed.

For integrated circuits in wireless communications devices or other high-speed digital electronics, a power delivery network supplies power to the various components of the overall system. A power delivery network may include a voltage regulator module that regulates voltage for a component. Resonance in a power delivery network is undesirable. Suppressing resonance in a power delivery network may be performed using a capacitor. Surface mount technology (SMT) capacitors may reduce power delivery network resonance/noise in high power, system on chip devices, such as application processors and graphics processors.

SUMMARY

A passive discrete device may include a first asymmetric terminal and a second asymmetric terminal. The passive discrete device may further include first internal electrodes extended to electrically couple to a first side and a second side of the first asymmetric terminal. The passive discrete device may also include second internal electrodes extended to electrically couple to a first side and a second side of the second asymmetric terminal.

A method of fabricating a passive discrete device may include plating first internal electrodes and second internal electrodes within a multilayer ceramic body. The method may also include dipping the multilayer ceramic body at a non-orthogonal angle to define a first asymmetric terminal and a second asymmetric terminal. The method may further include plating the first asymmetric terminal to electrically couple the first internal electrodes at a first side and a second side of the first asymmetric terminal. The method may further include plating the second asymmetric terminal to electrically couple the second internal electrodes at a first side and a second side of the second asymmetric terminal.

A passive discrete device may include a first asymmetric terminal and a second asymmetric terminal. The passive discrete device may further include a first means for electrically coupling to a first side and a second side of the first asymmetric terminal. The passive discrete device may also include a second means for electrically coupling to a first side and a second side of the second asymmetric terminal.

DETAILED DESCRIPTION

For integrated circuits in wireless communication devices or other high-speed digital electronics, a power delivery network supplies power to the various components of the overall system. A power delivery network may include a voltage regulator module that regulates voltage for a component. Suppressing resonance in a power delivery network may be performed using a capacitor. For example, surface mount technology (SMT) capacitors may reduce power delivery network resonance/noise in high power, system on chip devices, such as application processors and graphics processors.

A capacitor is an example of an electrical device used to store energy (e.g., charge) in an electrical field between closely spaced capacitor plates according to a capacitance value. This capacitance value provides a measure of the amount of charge stored by the capacitor at a certain voltage. In addition to their charge storing capability, capacitors are also useful as electronic filters because they enable differentiation between high frequency and low frequency signals.

An exemplary capacitor for suppressing resonance in a power delivery network is a multilayer ceramic chip capacitor (MLCC). This type of capacitor includes alternating ceramic and conductive material (e.g., metal) layers that are stacked to form a multilayer chip. An MLCC may exhibit increased inductance when operating above a self-resonance frequency. This increased inductance, however, is undesirable in power delivery networks. In particular, an MLCC with less inductive (e.g., lower equivalent series inductance (ESL)) and more capacitive (higher capacitance) characteristics is desirable for improving a decoupling effect in power delivery networks.

One aspect of the present disclosure relates to a passive discrete device with a modified internal/external electrode structure that reduces equivalent series inductance and increases capacitance. In one configuration, the reduced equivalent series inductance and increased capacitance are provided by extended, internal electrodes that are better able to confine an electric field between the electrodes. In this configuration, terminals of the multilayer ceramic capacitor device are modified to hold the extended internal electrodes. That is, the terminals of the device are each extended on one side for increasing overall electrical contact. The increased contact is with an extended area of the internal electrodes.

Various aspects of the disclosure provide techniques for fabrication of a passive discrete device having a modified internal/external electrode structure. The process flow for semiconductor fabrication of the passive discrete device may include front-end-of-line (FEOL) processes, middle-of-line (MOL) processes, and back-end-of-line (BEOL) processes. It will be understood that the term “layer” includes film and is not to be construed as indicating a vertical or horizontal thickness unless otherwise stated. As described herein, the term “substrate” may refer to a substrate of a diced wafer or may refer to a substrate of a wafer that is not diced. Similarly, the terms chip and die may be used interchangeably unless such interchanging would tax credulity.

A passive discrete device, according to an aspect of the present disclosure, includes a first asymmetric terminal and a second asymmetric terminal. In this configuration, the passive discrete device also includes first internal electrodes that are extended to electrically couple to a first side and a second side of the first asymmetric terminal. The passive discrete device further includes second internal electrodes that are extended to electrically couple to a first side and a second side of the second asymmetric terminal. In contrast to conventional terminals, the first and second terminals exhibit an asymmetric shape because they are modified to hold the extended first and second internal electrodes. As a result, the first asymmetric terminal and the second asymmetric terminal may be extended on one side to enable electrical coupling to an extended area of the first and second internal electrodes.

FIG. 1illustrates a perspective view of a semiconductor wafer in an aspect of the present disclosure. A wafer100may be a semiconductor wafer, or may be a substrate material with one or more layers of semiconductor material on a surface of the wafer100. When the wafer100is a semiconductor material, it may be grown from a seed crystal using the Czochralski process, where the seed crystal is dipped into a molten bath of semiconductor material and slowly rotated and removed from the bath. The molten material then crystalizes onto the seed crystal in the orientation of the crystal.

The wafer100may be a compound material, such as gallium arsenide (GaAs) or gallium nitride (GaN), a ternary material such as indium gallium arsenide (InGaAs), quaternary materials, or any material that can be a substrate material for other semiconductor materials. Although many of the materials may be crystalline in nature, polycrystalline or amorphous materials may also be used for the wafer100.

The wafer100, or layers that are coupled to the wafer100, may be supplied with materials that make the wafer100more conductive. For example, and not by way of limitation, a silicon wafer may have phosphorus or boron added to the wafer100to allow for electrical charge to flow in the wafer100. These additives are referred to as dopants, and provide extra charge carriers (either electrons or holes) within the wafer100or portions of the wafer100. By selecting the areas where the extra charge carriers are provided, which type of charge carriers are provided, and the amount (density) of additional charge carriers in the wafer100, different types of electronic devices may be formed in or on the wafer100.

The wafer100has an orientation102that indicates the crystalline orientation of the wafer100. The orientation102may be a flat edge of the wafer100as shown inFIG. 1, or may be a notch or other indicia to illustrate the crystalline orientation of the wafer100. The orientation102may indicate the Miller Indices for the planes of the crystal lattice in the wafer100.

Once the wafer100has been processed as desired, the wafer100is divided up along dicing lines104. The dicing lines104indicate where the wafer100is to be broken apart or separated into pieces. The dicing lines104may define the outline of the various integrated circuits that have been fabricated on the wafer100.

Once the dicing lines104are defined, the wafer100may be sawn or otherwise separated into pieces to form the die106. Each of the die106may be an integrated circuit with many devices or may be a single electronic device. The physical size of the die106, which may also be referred to as a chip or a semiconductor chip, depends at least in part on the ability to separate the wafer100into certain sizes, as well as the number of individual devices that the die106is designed to contain.

Once the wafer100has been separated into one or more die106, the die106may be mounted into packaging to allow access to the devices and/or integrated circuits fabricated on the die106. Packaging may include single in-line packaging, dual in-line packaging, motherboard packaging, flip-chip packaging, indium dot/bump packaging, or other types of devices that provide access to the die106. The die106may also be directly accessed through wire bonding, probes, or other connections without mounting the die106into a separate package.

FIG. 2illustrates a cross-sectional view of a die106in accordance with an aspect of the present disclosure. In the die106, there may be a substrate200, which may be a semiconductor material and/or may act as a mechanical support for electronic devices. The substrate200may be a doped semiconductor substrate, which has either electrons (designated N-channel) or holes (designated P-channel) charge carriers present throughout the substrate200. Subsequent doping of the substrate200with charge carrier ions/atoms may change the charge carrying capabilities of the substrate200.

Within a substrate200(e.g., a semiconductor substrate), there may be wells202and204, which may be the source and/or drain of a field-effect transistor (FET), or wells202and/or204may be fin structures of a fin structured FET (FinFET). Wells202and/or204may also be other devices (e.g., a resistor, a capacitor, a diode, or other electronic devices) depending on the structure and other characteristics of the wells202and/or204and the surrounding structure of the substrate200.

The semiconductor substrate may also have a well206and a well208. The well208may be completely within the well206, and, in some cases, may form a bipolar junction transistor (BJT). The well206may also be used as an isolation well to isolate the well208from electric and/or magnetic fields within the die106.

Layers (e.g.,210through214) may be added to the die106. The layer210may be, for example, an oxide or insulating layer that may isolate the wells (e.g.,202-208) from each other or from other devices on the die106. In such cases, the layer210may be silicon dioxide, a polymer, a dielectric, or another electrically insulating layer. The layer210may also be an interconnection layer, in which case it may comprise a conductive material such as copper, tungsten, aluminum, an alloy, or other conductive or metallic materials.

The layer212may also be a dielectric or conductive layer, depending on the desired device characteristics and/or the materials of the layers (e.g.,210and214). The layer214may be an encapsulating layer, which may protect the layers (e.g.,210and212), as well as the wells202-208and the substrate200, from external forces. For example, and not by way of limitation, the layer214may be a layer that protects the die106from mechanical damage, or the layer214may be a layer of material that protects the die106from electromagnetic or radiation damage.

Electronic devices designed on the die106may comprise many features or structural components. For example, the die106may be exposed to any number of methods to impart dopants into the substrate200, the wells202-208, and, if desired, the layers (e.g.,210-214). For example, and not by way of limitation, the die106may be exposed to ion implantation, deposition of dopant atoms that are driven into a crystalline lattice through a diffusion process, chemical vapor deposition, epitaxial growth, or other methods. Through selective growth, material selection, and removal of portions of the layers (e.g.,210-214), and through selective removal, material selection, and dopant concentration of the substrate200and the wells202-208, many different structures and electronic devices may be formed within the scope of the present disclosure.

Further, the substrate200, the wells202-208, and the layers (e.g.,210-214) may be selectively removed or added through various processes. Chemical wet etching, chemical mechanical planarization (CMP), plasma etching, photoresist masking, damascene processes, and other methods may create the structures and devices of the present disclosure.

FIGS. 3A and 3Billustrate various views of a passive discrete device300.FIG. 3Aillustrates a perspective view of the passive discrete device300including layers of capacitor plates (e.g.,320) that are alternatingly coupled to external terminals (e.g.,310). The capacitor plates (e.g.,320) may be surrounded by a dielectric material (e.g., a multilayer ceramic body302). The passive discrete device300may store energy (e.g., charge) in an electrical field between the capacitor plates (e.g.,320) according to a capacitance value. In addition to the charge storing capability, the passive discrete device300is also useful as an electronic filter by enabling differentiation between high frequency and low frequency signals.

FIG. 3Billustrates various views of the passive discrete device300. The passive discrete device300may be used for suppressing resonance in a power delivery network when arranged as a multilayer ceramic capacitor (MLCC) device. In the perspective view, the passive discrete device300includes a first symmetric terminal310A, a second symmetric terminal310B and a multilayer ceramic body302. As shown in the cutaway view, the passive discrete device300includes alternating ceramic and conductive material (e.g., metal) layers that are stacked to form a multilayer chip. Representatively, first inner electrodes320A are electrically coupled (e.g., shorted) at one end to the first symmetric terminal310A. Similarly, second inner electrodes320B are electrically coupled (e.g., shorted) at one end to the second symmetric terminal310B.

As shown in the top view, the first inner electrodes320A are electrically coupled to only a first side312A of the first symmetric terminal310A. Similarly, the second inner electrodes320B are electrically coupled to only a second side312B of the second symmetric terminal310B. As shown in the side view, the first symmetric terminal310A and the second symmetric terminal310B are of equal length. This arrangement of the passive discrete device300may exhibit increased inductance when operating above a self-resonance frequency. This increased inductance, however, is undesirable in power delivery networks. In particular, a passive discrete device with less inductive (e.g., lower equivalent series inductance (ESL)) and more capacitive (higher capacitance) characteristics is desirable for improving a decoupling effect in power delivery networks.

FIGS. 4A to 4Eillustrate various views of a passive discrete device with a modified internal/external electrode structure according to aspects of the present disclosure. As shown inFIG. 4A, a passive discrete device400includes a first asymmetric terminal410A, a second asymmetric terminal410B and a multilayer ceramic body402to conform with the modified internal/external electrode structure shown, for example, inFIGS. 4B to 4E. In aspects of the present disclosure, the modified internal/external electrode structure can provide reduced equivalent series inductance (ESL) and increased capacitance. In one configuration, the reduced equivalent series inductance and increased capacitance are provided by extending internal electrodes to provide an extended area that improves confinement of an electric field between the internal electrodes.

In the configuration shown in the cutaway view ofFIG. 4B, a first asymmetric terminal410A includes a second side414A that is longer than a corresponding side416B of a second asymmetric terminal410B. The second side414A of the first asymmetric terminal410A is lengthened to hold an extended area of a first internal electrode420A. That is, the first asymmetric terminal410A of the passive discrete device400is extended on one side to enable electrical coupling to an extended area of the first internal electrode420A, for example, as shown in the side view ofFIG. 4D.

FIG. 4Cis a top view further illustrating the passive discrete device400with a modified internal/external electrode structure according to aspects of the present disclosure. As shown inFIG. 4C, the passive discrete device400includes a first internal electrode420A that is extended to electrically couple to a portion418A of a first side412A and a second side414A of the first asymmetric terminal410A. The passive discrete device400also includes a second internal electrode420B that is also extended to electrically couple to a portion418B of a first side412B and a second side414B of the second asymmetric terminal410B.

As further illustrated inFIG. 4C, the extension of the first internal electrode420A and the second internal electrode420B, provides a first extended area430A and a second extended area430B. In this configuration, the first side414A of the first asymmetric terminal410A is extended to electrically couple to the first extended area430A of the first internal electrode420A. Similarly, the first side414B of the second asymmetric terminal410B is extended to electrically couple to the second extended area430B of the second internal electrode420B.

FIG. 4Eshows a perspective view of the passive discrete device400including extended areas of the modified internal electrode structure according to aspects of the present disclosure. In this configuration, the first extended area430A and second extended area430B may enhance an electrical field formed between the first internal electrode420A and the second internal electrode420B. By contrast, as shown inFIG. 3B, the first inner electrodes320A only contact the first side312A of the first symmetric terminal310A; and the second inner electrodes320B only contact the first side312B of the second symmetric terminal310B. Consequently, the passive discrete device300FIG. 3Bmay exhibit increased inductance (e.g., increased equivalent series inductance (ESL)) when operating above a self-resonance frequency, which is undesirable in power delivery networks. This ESL, however, may be substantially decreased (e.g., a 30%) by the first extended area430A and the second extended area430B of the passive discrete device400shown inFIG. 4E.

FIG. 5is a diagram illustrating a process500for fabricating a passive discrete device according to aspects of the disclosure. At step510, a first internal electrode420A and a second internal electrode420B are plated within ceramic layers404. For example, the first internal electrode420A and the second internal electrode420B are printed on one of the ceramic layers404(e.g., a first ceramic layer or a second ceramic layer) using a conductive material (e.g., a nickel (Ni) alloy). In this arrangement, the modified stencil is expanded to enable printing of the first extended area430A and the second extended area430B of the internal electrodes. At step520, the ceramic layer may be stacked with other ones of the ceramic layers404, then laminated and cut to form multiple multilayer ceramic bodies.

At step530, a sintering process forms a multilayer ceramic body402. In one aspect of the disclosure, the terminal formation process is modified to provide electrical coupling to the extended areas (e.g., the first extended area430A and the second extended area430B) using a symmetric structure for the terminals. At step540, a termination dipping process is performed at a non-orthogonal angle (e.g., 45°) to define a first asymmetric terminal410A and a second asymmetric terminal410B. The multilayer ceramic body402is dipped into a conductive solution (e.g., Ni, Tin) at the non-orthogonal angle to conform with the extended areas of the extended internal electrodes. At step550, a termination plating process is performed to complete the first asymmetric terminal410A, which is plated to electrically couple to the first internal electrode420A at a first side and a second side of the first asymmetric terminal410A. In addition, the second asymmetric terminal410B is plated to electrically couple to the second internal electrode420B at a first side and a second side of the second asymmetric terminal410B. The first asymmetric terminal410A and the second asymmetric terminal410B may be plated with a copper (Cu) alloy. At step560, testing of the passive discrete device is performed.

In this aspect of the present disclosure, the passive discrete device400is provided with a modified internal/external electrode structure that reduces equivalent series inductance and increased capacitance. In one configuration, the reduced equivalent series inductance and increased capacitance are provided by extended, internal electrodes (e.g., the first extended area430A and the second extended area430B) that improve confinement of an electric field between the internal electrodes (e.g.,420A and420B). In this configuration, the terminals (e.g.,410A and410B) of the passive discrete device400are modified to hold the extended internal electrodes (e.g.,420A and420B). That is, the terminals (e.g.,410A and410B) are extended on one side to enable electrical coupling to an extended area (e.g.,430A and430B) of the internal electrodes (e.g.,420A and420B).

FIG. 6is a flow diagram illustrating a method600for fabricating a passive discrete device according to aspects of the disclosure. At block602, a first internal electrode and a second internal electrode are plated within a multilayer ceramic body. For example, as shown inFIG. 5, a first internal electrode420A and a second internal electrode420B are plated on one of the ceramic layers404. In this arrangement, a printing stencil is modified to enable printing of extended areas (e.g.,430A and430B) of the internal electrodes. This ceramic layer may be stacked with other ones of the ceramic layers404, then laminated and cut to form multiple multilayer ceramic bodies.

Referring again toFIG. 6, at block604, the multilayer ceramic body is dipped at a non-orthogonal angle to define a first asymmetric terminal and a second asymmetric terminal. As shown inFIG. 5, the multilayer ceramic body402is dipped into a solution at a non-orthogonal angle (e.g., 45°) to define the first asymmetric terminal410A and the second asymmetric terminal410B. At block606, the first asymmetric terminal is plated to electrically couple the first internal electrodes at a first side and a second side of the first asymmetric terminal. At block608, the second asymmetric terminal is plated to electrically couple the second internal electrodes at a first side and a second side of the second asymmetric terminal.

For example, as shown inFIG. 4C, the first internal electrode420A is electrically coupled (e.g., shorted) to the first side412A and the second side414B of the first asymmetric terminal410A. Similarly the second internal electrode420B is electrically coupled (e.g., shorted) to the first side412B and the second side414B of the second asymmetric terminal410B. In this arrangement, a first extended area430A of the first internal electrode420A and a second extended area430B of the second internal electrode420B enable improved confinement of an electrical field between, for example, the first internal electrode420A and the second internal electrode420B.

In one configuration, a passive discrete device includes a first asymmetric terminal and a second asymmetric terminal. The passive discrete device further includes a first means for electrically coupling to a first side and a second side of the first asymmetric terminal. The passive discrete device also includes a second means for electrically coupling to a first side and a second side of the second asymmetric terminal. In one aspect of the disclosure, the first means is the first internal electrode ofFIGS. 4B to 4E, configured to perform the functions recited by the first means. In this aspect of the disclosure, the second means is the second internal electrode ofFIGS. 4B to 4E, configured to perform the functions recited by the second means. In another aspect, the aforementioned means may be a device or any layer configured to perform the functions recited by the aforementioned means.

An exemplary capacitor for suppressing resonance in a power delivery network is a multilayer ceramic chip capacitor (MLCC). This type of capacitor includes alternating ceramic and conductive material (e.g., metal) layers that are stacked to form a multilayer chip. An MLCC may exhibit increased inductance when operating above a self-resonance frequency. This increased inductance, however, is undesirable in power delivery networks. In particular, an MLCC with less inductive (e.g., lower equivalent series inductance (ESL)) and more capacitive (higher capacitance) characteristics is desirable for improved a decoupling effect in power delivery networks.

One aspect of the present disclosure relates to a passive discrete device with a modified internal/external electrode structure that reduces equivalent series inductance and increased capacitance. In one configuration, the reduced equivalent series inductance and increased capacitance are provided by extended, internal electrodes. These internal electrodes each provide an extended area for further confinement of an electric field between the internal electrodes. In this configuration, terminals of the multilayer ceramic capacitor device are modified to hold the extended internal electrodes. That is, the terminals of the device are extended on one side to enable electrical coupling to the extended area of the internal electrodes.

FIG. 7is a block diagram showing an exemplary wireless communication system700in which an aspect of the disclosure may be advantageously employed. For purposes of illustration,FIG. 7shows three remote units720,730, and750and two base stations740. It will be recognized that wireless communication systems may have many more remote units and base stations. Remote units720,730, and750include IC devices725A,725C, and725B that include the disclosed passive discrete device. It will be recognized that other devices may also include the disclosed passive discrete device, such as the base stations, switching devices, and network equipment.FIG. 7shows forward link signals780from the base station740to the remote units720,730, and750and reverse link signals790from the remote units720,730, and750to base stations740.

InFIG. 7, remote unit720is shown as a mobile telephone, remote unit730is shown as a portable computer, and remote unit750is shown as a fixed location remote unit in a wireless local loop system. For example, the remote units720,730, and750may be a mobile phone, a hand-held personal communication systems (PCS) unit, a portable data units such as a personal digital assistant (PDA), a GPS enabled device, a navigation device, a set top box, a music player, a video player, an entertainment unit, a fixed location data unit such as a meter reading equipment, or a communications device that stores or retrieves data or computer instructions, or combinations thereof. AlthoughFIG. 7illustrates remote units according to the aspects of the disclosure, the disclosure is not limited to these exemplary illustrated units. Aspects of the disclosure may be suitably employed in many devices, which include the disclosed devices.

FIG. 8is a block diagram illustrating a design workstation used for circuit, layout, and logic design of a semiconductor component, such as the devices disclosed above. A design workstation800includes a hard disk802containing operating system software, support files, and design software such as Cadence or OrCAD. The design workstation800also includes a display804to facilitate design of a circuit806or a semiconductor component808such as a passive discrete device. A storage medium810is provided for tangibly storing the design of the circuit806or the semiconductor component808. The design of the circuit806or the semiconductor component808may be stored on the storage medium810in a file format such as GDSII or GERBER. The storage medium810may be a CD-ROM, DVD, hard disk, flash memory, or other appropriate device. Furthermore, the design workstation800includes a drive apparatus812for accepting input from or writing output to the storage medium810.

Data recorded on the storage medium810may specify logic circuit configurations, pattern data for photolithography masks, or mask pattern data for serial write tools such as electron beam lithography. The data may further include logic verification data such as timing diagrams or net circuits associated with logic simulations. Providing data on the storage medium810facilitates the design of the circuit806or the semiconductor component808by decreasing the number of processes for designing semiconductor wafers.

The steps of a method or algorithm described in connection with the disclosure may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM, flash memory, ROM, EPROM, EEPROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.