TECHNOLOGY TO DETECT POWER CONSUMPTION AND LOW POWER STATES IN EXTERNAL SINK DEVICES TO ENHANCE SYSTEM PERFORMANCE AND IMPROVE USER EXPERIENCES

Systems, apparatuses and methods may provide for technology that allocates a portion of operational power in a source device to an external sink device in response to a connection of the external sink device to the source device, detects a low power state with respect to the external sink device, and decreases the portion of operational power allocated to the external sink device in response to the low power state.

TECHNICAL FIELD

Embodiments generally relate to power management. More particularly, embodiments relate to technology to detect power consumption and low power states in external sink devices to enhance system performance and improve user experiences.

BACKGROUND

Universal Serial Bus (USB) technology (e.g., Universal Serial Bus Type-C Cable and Connector Specification, Release 2.0, August 2019, USB Implementers Forum) provides for charging and/or operating power to be supplied from a source device (e.g., notebook computer, desktop computer, etc.) to one or more external sink devices (e.g., keyboard, mouse, game controller, power bank, smart phone, etc.) connected to the source device. The amount of power supplied to each sink device is typically determined and fixed when the sink device is connected to the source device based on the total power available from the source device and the power demands of all sink devices receiving power from the source device. If the power needs of a sink device decrease, however, the source device may continue to provide the originally allocated amount of power to the sink device in question. As a result, a negative impact on performance and/or energy regulatory body compliance may be encountered in the source device.

DETAILED DESCRIPTION OF EMBODIMENTS

Turning now toFIG.1, a connection24(24a,24b, e.g., USB Type-C connection, THUNDERBOLT connection, etc.) between a source device20(e.g., host such as a mobile/notebook computer or desktop computer) and an external sink device22(e.g., keyboard, mouse, game controller, power bank, smart phone, etc.) is shown. Depending on the circumstances, the source device20and the external sink device22may swap producer/consumer roles. In the illustrated example, the connection24includes a voltage bus24a(VBUS) that provides charging and/or operating power to the external sink device22. The connection24may also include a configuration channel24b(CC) that is used to determine how much operational power in the source device20to allocate to the external sink device22. The amount of operational power to be allocated to the external sink device22may be established via an implicit power setting and/or an explicit power setting.

For example, the external sink device22might be a USB Type-C device that is governed by a power delivery contract, wherein the power delivery contract is either implicitly or explicitly established with the source device20. The power delivery contract defines the operational power of the external sink device22as defined by USB specifications. Table I below demonstrates that an implicit contract may occur through the configuration channel24b, where the source device20pulls up the configuration channel24bto different pull-up resistance (Rp) values26to indicate different current values as defined by USB interface specifications. Explicit contract devices rely on protocol negotiation to determine the power contract.

As will be discussed in greater detail, if the source device20is a mobile system, a challenge may be to determine the actual power consumption from the external sink device22because the power contract only defines the maximum operational power and is not reflective of the actual power that the external sink device22is consuming at any given moment in time. When the external sink device22goes into a low power state such as, for example, the Advanced Configuration and Power Interface (e.g., ACPI Specification, Rev. 6.2, May 2017) D3 mode, the power pre-allocated to the external sink device22from the source device20typically remains with the external sink device22and does not scale down with the actual consumption under conventional approaches.

Accordingly, the central processing unit (CPU, e.g., host processor) of the source device20might continue to work at lower speeds under conventional approaches as there is no existing mechanism to determine the power consumption and eventually reclaim power. Indeed, devices such as human interface devices (HIDs, e.g., keyboards, mice, game controllers) or USB drives often do not consume the maximum allocated implicit power. Moreover, if the source device20is a desktop system, conventional solutions may lack policies that allow the desktop system to switch to a standby voltage rail to meet energy regulatory body compliance depending on the actual power consumption of the external sink device22.

Technology described herein uses different approaches for implicit and explicit contract devices to improve performance and regulatory compliance. Explicit contract devices rely on the ability of a power delivery (PD) controller (not shown) of the source device20to monitor and measure the voltage bus24aload to improve overall system performance and the user experience. For example, the PD controller may report the current drawn in regular intervals to an embedded controller (EC, not shown) of the source device20, wherein the EC consumes the data and enables the CPU and/or graphics processor (e.g., “Gfx”) of the source device20to reclaim power when the external sink device22is in a low power state. Power reclamation enables the source device20to achieve improved CPU and Gfx performance. Embodiments also include enhanced routines involving OS and platform components to take advantage of low power state transitions by connected devices for power reclamation. Implicit contract devices such as HID and USB peripherals consume far less than the contracted power (e.g., as advertised in configuration descriptors “bMaxPower” field). Embodiments take advantage of this advertisement to determine the amount of power pre-allocated to the device by the CPU (e.g., preventing oversubscription).

In desktop systems, embodiments enable customers to implement policies that would allow the source device20to switch to an Advanced Technology eXtended (ATX) standby rail depending on the actual power consumption of the external sink device22. Thus, the technology described herein represents an improvement over existing ecosystems in which the platform reserves the maximum amount of power due to a lack of knowledge within the system, even though the connected USB devices require less power from the system. In a battery-powered device executing, for example, a graphics intensive application, a processing unit (e.g., CPU, host processor, graphics processing unit/GPU, graphics processor, Neural processing Unit/NPU) may be permitted to execute at an operating frequency (e.g., turbo boost mode) that is higher than the rated operating frequency for relatively long periodic bursts. Embodiments therefore enhance system performance by increasing turbo max limits (e.g., power level four/ PL4), which in turn improves the user experience and provides more efficient usage of system resources.

More particularly, embodiments provide two different approaches of determining the current drawn by the external sink device22(e.g., port partner device) including an updated methodology for the OS to detect low power state transitions of the external sink device22and updating peak power limits depending on the actual power consumption of the external sink device22. Mobile and desktop systems with an EC may rely on “Approach One” while desktop platforms without an EC might rely on “Approach Two”.

Approach One: This technology uses current monitoring capability of PD controllers to constantly update the steady state and peak current into host interface registers of the PD controllers. The EC or a system policy manager (e.g., host) reads the registers through an inter-integrated circuit (I2C) interface and updates the CPU with the modified peak power limit when requested by the OS.

Approach Two: In this technology, the PD queries the external sink device22for the battery capacity of the external sink device22to determine if the external sink device22is sufficiently charged or fully charged before switching to the ATX standby rail.

The technology described herein therefore improves CPU/Gfx performance for all mobile systems by reclaiming power during device low power states. On desktop systems, the technology switches to a standby rail depending on the actual device power consumption (e.g., supporting use cases such as charging of phones/power banks while still meeting energy regulatory requirements).

Another aspect of the technology described herein reclaims the power reserved for platform plug and play (PnP) devices through device configuration descriptors and uses the reclaimed power to improve CPU power limits. For example, the source device20might include an interface (e.g., application programming interface/API) for the OS to update the real power requirement retrieved from the descriptors provided by the external sink device22. After successful retrieval, the OS updates platform firmware on the power requirements through the interfaces to reclaim the power reserved for the rest of the platform. Finally, the platform firmware may use the reclaimed power to improve the turbo capability of the CPU by updating the peak power limits.

FIG.2shows a method30of operating a source device. The method30may generally be implemented in a source device such as, for example, the source device20(FIG.1). More particularly, the method30may be implemented in one or more modules as a set of logic instructions stored in a machine- or computer-readable storage medium such as random access memory (RAM), read only memory (ROM), programmable ROM (PROM), firmware, flash memory, etc., in hardware, or any combination thereof. For example, hardware implementations may include configurable logic, fixed-functionality logic, or any combination thereof. Examples of configurable logic include suitably configured programmable logic arrays (PLAs), field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), and general purpose microprocessors. Examples of fixed-functionality logic include suitably configured application specific integrated circuits (ASICs), combinational logic circuits, and sequential logic circuits. The configurable or fixed-functionality logic can be implemented with complementary metal oxide semiconductor (CMOS) logic circuits, transistor-transistor logic (TTL) logic circuits, or other circuits.

The illustrated processing block32provides for allocating a portion of operational power in the source device to an external sink device in response to a connection (e.g., plug and play connection) of the external sink device to the source device. In an embodiment, block32allocates the portion of operational power in accordance with one or more of an explicit power setting/contract or an implicit power setting/contract. Block34detects a low power state with respect to the external sink device. In one example (e.g., Approach One), block34tracks a power consumption measurement (e.g., via a PD controller and/or EC) with respect to the external sink device. In another example, (e.g., Approach Two), block34determines that a battery capacity of the external sink device has exceeded a threshold (e.g., 90%). Block36decreases the portion of operational power allocated to the external sink device in response to the low power state.

In an embodiment, block38determines whether the source device is a mobile system/platform (e.g., notebook computer based on internal configuration information of the source device). If so, block40increases a maximum turbo boost limit of the source device based on the decreased portion of operational power allocated to the external sink device. Thus, if block36decreases the portion of operational power allocated to the external sink device by 300 milliWatts (mW), block40might increase the maximum turbo boost limit by 300mW. If it is determined at block38that the source device is not a mobile system/platform, block42determines whether the source device is a desktop system/platform (e.g., based on internal configuration information of the source device). If so, block44switches the source device to a standby rail based on the decreased portion of operational power allocated to the external sink device. If it is determined at block42that the source device is not a desktop system/platform (e.g., another type of computing system), the method30may bypass blocks40and44and terminate. The method30therefore enhances performance at least to the extent that reclaiming power originally allocated to the external sink device enables the source device to operate at higher frequencies and/or reduce power consumption.

Turning now toFIG.3A, a BIOS or OS phase is shown in which a sink device50is connected to a source device52(52a-52g) including a PD controller52a, an EC52b, a power manager52c(e.g., ACPI manager), an OS driver52d(e.g., USB connector manager/UCM), a connection manager52e(e.g., WINDOWS connection manager, LINUX connection manager), a CPU52f, and a device driver52g. Peak power limits are adjusted when the external sink device50is attached and/or detached to the source device52. During an attach event54, the peak power limit is set based on the power contract with the external sink device50, wherein the amount of power contracted for is subtracted from the overall budget of the source device52before the external sink device50starts sinking. This adjustment is achieved by the PD controller52aasserting a “PROCHOT” signal56, which lowers the operating frequency of the CPU52f, immediately giving ample time for the EC52bto update the peak power limit. After the update, the PD controller52adeasserts58the PROCHOT signal. These operations are repeated whenever the power contract changes.

FIG.3Bshows an OS mapping phase60in which the connector status is notified to the connection manager52evia the OS driver52d. To be able to map the connector to connected devices in a new subroutine62, a new ACPI group is defined under the USB-C connector (CRx) object on a per connector basis. ACPI grouping procedures advertise all possible ACPI objects that could enumerate behind a Type-C connector. The ACPI grouping allows for defining a minimum (min) and maximum (max) power for the port. The max power correlates with the PD contract and the min power correlates with the standby power requirements of the device (e.g., as defined in the appropriate specification). In the example below for an external sink device that supports both USB and Peripheral Component Interconnect Express (PCI-e, e.g., PCI Express® Base Specification 6.0, Version 1.0, Jan. 11, 2022, PCI Special Interest Group) tunneling, the max power is 15 W and min power for standby requirement is 50mW. An OS fine tuning phase64then adjusts the power.

FIG.4shows a D3 entry routine70. When the sink device50idles to the runtime D3 mode (RTD3), the connection manager52eissues a set power limit command72to the OS driver52dwith the power level set to the min value as defined in the ACPI grouping.

FIG.5shows a power adjustment routine80in response to a D3 entry. In the illustrated example, the EC52breceives the set power limit command72and, being a policy manager (PPM), overrides the command72with a different set power limit command82based on the current/power level reported by the PD controller52a. The different set power limit command82enables the PD controller52ato negotiate to a new power contract/setting. After receiving an acknowledgment from PD controller52aon the new power contract change, the EC52balso uses a status message84to update the package peak power limit (e.g., PL4 offset) with the new power level via a platform environment control interface (PECI). In this case, it is expected for the new power limit to be higher than the initial contract level, which provides improved CPU and Gfx performance during peak power events (e.g., “PL4 events”).

FIG.6shows another power adjustment routine90in response to a D3 entry. In the illustrated example, the PD controller52adoes not report the power currently consumed by the device. Rather, the EC52buses the power level reported by the OS as part of the original power level set command72.

FIG.7shows a D3 exit routine100. When the sink device50exits from D3 (low power) to D0 (active), the connection manager52einstructs the OS driver to issue a set power limit command102to the PD controller52awith the power level set to the max value as defined in the ACPI grouping.

FIG.8shows a power adjustment routine111in response to a D3 exit. In the illustrated example, the EC52breceives the command102and issues a message103to update the system on chip (SoC) package peak power limit via the PECI interface before forwarding the command102to the PD controller52a. This approach ensures that the package can operate within the new peak power limit as set by the OS/EC52bbefore providing the power back to the sink device. In this case it, is expected for the new power limit to be lower than the when the sink device was in D3, which lowers the CPU and Gfx performance during peak power events. After receiving an acknowledgment from the dynamic thermal framework on the peak power limit update, the EC52balso notifies the PD controller52a, which then establishes a new PD contract/setting (e.g., restoring the contract/setting back to the original values).

FIG.9shows a method121of reclaiming allocated power. The method121may generally be implemented in a source device such as, for example, the source device20(FIG.1) and/or the source device52(FIG.3A-8). More particularly, the method121may be implemented in one or more modules as a set of logic instructions stored in a machine- or computer-readable storage medium such as RAM, ROM, PROM, firmware, flash memory, etc., in hardware, or any combination thereof. For example, hardware implementations may include configurable logic, fixed-functionality logic, or any combination thereof.

When the EC receives the set power limit command for a port from the OS at block123, the EC first checks at block125whether the port is in a provider (e.g., source) role or a consumer (e.g., sink) role. If the port is in the sink/consumer role, then the ingress power is limited at block127and the illustrated method121terminates. If the port is in the source/provider role and it is determined at block129that the command is not a broadcast command (e.g., system wide power limitation), then the EC checks for the requested power for the individual port at block131. The requested power being greater than the original is an indication that the sink device is exiting from RTD3 and the power levels are to be restored to the original value. In such a case, the EC updates the PL4 offset via the PECI interface at block133and, after restoring the power in block135, updates the PD controller to reflect the change in PD contract and reports success to the OS at block137.

If it is determined at block131that the requested power is less than the original value, then the device is entering RTD3, and the peak power limit is going to be higher. Accordingly, the EC reads the reported power by PD at block139and determines whether the power consumption level is less than the proposed power level at block141. If so, block143uses the reported power to establish a new PD contract, block145updates the PL4 offset via the PECI interface, and block147reports success to the OS. If it is determined at block141that the power consumption level is not less than the proposed power level, then block149reports an error to the OS.

If it is determined at block129that the EC has received a broadcast command from the OS to update all the ports, the EC follows the same concept as for single port and updates the CPU power limits via the PECI interface for improved CPU and Gfx performance whenever the devices are in D3. Thus, block151determines whether the requested power is less than the original value. If so, block153re-distributes the power based on the power policies and block155increases power to the CPU by adjusting the PL4 offset via the PECI interface or keeps the power the same based on battery and power policies. Otherwise, block157lowers the power to the CPU by adjusting the PL4 offset via the PECI interface or keeps the power the same based on the battery and power policies, and block159provides more power to “starving devices” with a mismatched bit set. More particularly, the sink device may request more power up to a maximum amount by setting a bit known as a “capability mismatch” bit, which allows the source device to provide more power to the sink device, if available. The method121then sets the power level at block161.

FIG.10shows a power reclamation routine200for a source device202(202a-202d) including a PD controller202a, an EC202b, an SoC202c(e.g., including a CPU), and an OS framework202d(e.g., including a device driver). When a port partner device204(e.g., external plug and play sink device) is connected to the source device202, the PD Controller202ainstructs the CPU to operate in low frequency mode (LFM), as there will be a change in the system power reserve. After successful power negotiation, the EC202binstructs the CPU firmware to update the PL4 offset to ensure that the system power consumption is within the available power budget.

Once the port partner device204is properly configured, the OS framework202dqueries via the EC the port status and the power configurations. The OS may then use ACPI methods to update the power reserve after parsing the descriptors and change the PL4 offset to a higher optimal value.

If the source device202is a desktop system with the EC202b, during low power system transitions, the EC202bcan determine the power consumed by the port partner device204as reported by PD controller202a. If the power consumed is within the budget allocated for Type-C devices based on ATX standby capacity, the source device202can switch to a standby rail. This approach is particularly useful in supporting the following use cases:Allow the charging of phones or power banks during standby state. When the device is charging, and host ports are sourcing, the EC202bwill not permit switches to the standby rail. When the device has completed charging and is not drawing any power then EC will allow ATX to switch to standby rail.Allowing bus powered alternate mode devices to support wake when particularly these devices are consuming significant power even in idle scenarios (e.g., THUNDERBOLT bus powered devices or devices that require 3W during standby). When wakes are disabled, the EC202bcan allow switches to the standby rail. When wakes are enabled, the EC202bcan prevent switches to the standby rail.

As already noted, another approach determines whether the port partner device204has completed charging. In such a case, the PD controller202aqueries the battery capacity of the port partner device204. If the device is, for example, >90% charged, then the above policies can be implemented.

If (Low power entry)#### Approach TwoIf (PD3.0 sink device)Get_battery_cap_messageWhile (Battery last full charge <= 90% of Design capacity):{SleepGet_battery_cap _messageMaintain PD contract}#### End of code

In the illustrated example, the system110includes a host processor112(e.g., CPU) having an integrated memory controller (IMC)114that is coupled to a system memory116. In an embodiment, an IO module118is coupled to the host processor112. The illustrated IO module118communicates with, for example, a network controller126(e.g., wired and/or wireless), and a mass storage128(e.g., hard disk drive/HDD, optical disc, solid-state drive/SSD, flash memory, etc.). The system110may also include a graphics processor120(e.g., graphics processing unit/GPU) that is incorporated with the host processor112and the IO module118into a system on chip (SoC)130. The computing system110also includes a battery134that provides a battery output.

In one example, the mass storage128and/or the system memory116include instructions132, which when executed by the SoC130and/or the host processor112, causes the SoC130, the host processor112and/or the computing system110to implement one or more aspects of the method30(FIG.2) and/or the method121(FIG.9), already discussed. Thus, execution of the instructions132causes the SoC130, the host processor112and/or the computing system110to allocate a portion of operational power in the computing system110to an external sink device124in response to a connection of the external sink device124to the computing system110, detect a low power state with respect to the external sink device124(e.g., based on power consumption measurements and/or battery capacity), and decrease the portion of the operational power allocated to the external sink device124in response to the low power state. The computing system110is therefore considered performance-enhanced at least to the extent that reclaiming power originally allocated to the external sink device124enables the computing system110to operate at higher frequencies and/or reduce power consumption.

FIG.12shows a semiconductor apparatus140(e.g., chip and/or package). The illustrated apparatus140includes one or more substrates142(e.g., silicon, sapphire, gallium arsenide) and logic144(e.g., transistor array and other integrated circuit/IC components) coupled to the substrate(s)142. In an embodiment, the logic144and implements one or more aspects of the method30(FIG.2) and/or the method121(FIG.9), already discussed.

The logic144may be implemented at least partly in configurable or fixed-functionality hardware. In one example, the logic144includes transistor channel regions that are positioned (e.g., embedded) within the substrate(s)142. Thus, the interface between the logic144and the substrate(s)142may not be an abrupt junction. The logic144may also be considered to include an epitaxial layer that is grown on an initial wafer of the substrate(s)142.

Additional Notes and Examples

Example 1 includes a performance-enhanced source device comprising a processing unit and a memory coupled to the processing unit, the memory including a set of instructions, which when executed by the processing unit, cause the processing unit to allocate a portion of operational power in the source device to an external sink device in response to a connection of the external sink device to the source device, detect a low power state with respect to the external sink device, and decrease the portion of operational power allocated to the external sink device in response to the low power state.

Example 2 includes the source device of Example 1, wherein the instructions, when executed, further cause the processing unit to increase a maximum turbo boost limit of the source device based on the decreased portion of operational power allocated to the external sink device.

Example 3 includes the source device of Example 1, wherein the instructions, when executed, further cause the processing unit to switch the source device to a standby rail based on the decreased portion of operational power allocated to the external sink device.

Example 4 includes the source device of Example 1, wherein to detect the low power state, the instructions, when executed, further cause the processing unit to track a power consumption measurement with respect to the external sink device.

Example 5 includes the source device of Example 1, wherein to detect the low power state, the instructions, when executed, further cause the processing unit to determine that a battery capacity of the external sink device has exceeded a threshold.

Example 6 includes the source device of any one of Examples 1 to 5, wherein the portion of operational power is to be allocated to the external sink device in accordance with one or more of an explicit power setting or an implicit power setting.

Example 7 includes at least one computer readable storage medium comprising a set of instructions, which when executed by a source device, cause the source device to allocate a portion of operational power in the source device to an external sink device in response to a connection of the external sink device to the source device, detect a low power state with respect to the external sink device, and decrease the portion of operational power allocated to the external sink device in response to the low power state.

Example 8 includes the at least one computer readable storage medium of Example 7, wherein the instructions, when executed, further cause the source device to increase a maximum turbo boost limit of the source device based on the decreased portion of operational power allocated to the external sink device.

Example 9 includes the at least one computer readable storage medium of Example 7, wherein the instructions, when executed, further cause the source device to switch the source device to a standby rail based on the decreased portion of operational power allocated to the external sink device.

Example 10 includes the at least one computer readable storage medium of Example 7, wherein to detect the low power state, the instructions, when executed, further cause the source device to track a power consumption measurement with respect to the external sink device.

Example 11 includes the at least one computer readable storage medium of Example 7, wherein to detect the low power state, the instructions, when executed, further cause the source device to determine that a battery capacity of the external sink device has exceeded a threshold.

Example 12 includes the at least one computer readable storage medium of any one of Examples 7 to 11, wherein the portion of operational power is to be allocated to the external sink device in accordance with one or more of an explicit power setting or an implicit power setting.

Example 13 includes a semiconductor apparatus comprising one or more substrates, and logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware, the logic to allocate a portion of operational power in a source device to an external sink device in response to a connection of the external sink device to the source device, detect a low power state with respect to the external sink device, and decrease the portion of operational power allocated to the external sink device in response to the low power state.

Example 14 includes the semiconductor apparatus of Example 13, wherein the logic is further to increase a maximum turbo boost limit of the source device based on the decreased portion of operational power allocated to the external sink device.

Example 15 includes the semiconductor apparatus of Example 13, wherein the logic is further to switch the source device to a standby rail based on the decreased portion of operational power allocated to the external sink device.

Example 16 includes the semiconductor apparatus of Example 13, wherein to detect the low power state, the logic is to track a power consumption measurement with respect to the external sink device.

Example 17 includes the semiconductor apparatus of Example 13, wherein to detect the low power state, the logic is to determine that a battery capacity of the external sink device has exceeded a threshold.

Example 18 includes the semiconductor apparatus of any one of Examples 13 to 17, wherein the portion of operational power is to be allocated to the external sink device in accordance with one or more of an explicit power setting or an implicit power setting.

Example 19 includes a method of operating a performance-enhanced source device, the method comprising allocating a portion of operational power in the source device to an external sink device in response to a connection of the external sink device to the source device, detecting a low power state with respect to the external sink device, and decreasing the portion of operational power allocated to the external sink device in response to the low power state.

Example 20 includes the method of Example 19, further including increasing a maximum turbo boost limit of the source device based on the decreased portion of operational power allocated to the external sink device.

Example 21 includes the method of Example 19, further including switching the source device to a standby rail based on the decreased portion of operational power allocated to the external sink device.

Example 22 includes the method of Example 19, wherein detecting the low power state includes tracking a power consumption measurement with respect to the external sink device.

Example 23 includes the method of Example 19, wherein detecting the low power state includes determining that a battery capacity of the external sink device has exceeded a threshold.

Example 24 includes the method of any one of Examples 19 to 23, wherein the portion of operational power is allocated to the external sink device in accordance with one or more of an explicit power setting or an implicit power setting.

Example 25 includes an apparatus comprising means for performing the method of any one of Examples 19 to 24.

Technology described herein therefore improves CPU and Gfx performance by reclaiming power from USB Type-C ports and providing the reclaimed power back to the system for increased peak power limits. The technology also meets energy regulatory requirements while supporting use cases such as charging phones or power banks, even when the desktop platform is in system low power states (e.g., standby and/or ACPI Sx). Moreover, the technology optimizes, improves, and simplifies OS and firmware (FW) flows for CPU power reclamation.