Semiconductor Device and Method of Forming C2W Package with EMI Shielding

A semiconductor device has a substrate and an electrical component disposed over the substrate. A conductive post is formed over the substrate. An interposer can be disposed over the substrate and the electrical component disposed over the interposer and the conductive post formed over the interposer. An encapsulant is deposited over and around the substrate, electrical component, and conductive post. A shielding material is disposed over the substrate and encapsulant and grounded through the conductive post. The shielding material can be grounded through the interposer. A wire can be embedded in the encapsulant and coupled to the shielding material to ground the shielding material. A conductive via can be formed through the substrate and coupled to the shielding material to ground the shielding material. An interposer can be disposed over the encapsulant. A second shielding material can be disposed over the encapsulant and first shielding material.

FIELD OF THE INVENTION

The present invention relates in general to semiconductor devices and, more particularly, to a semiconductor device and method of forming a chip-to-wafer (C2W) package with EMI shielding.

BACKGROUND OF THE INVENTION

Semiconductor devices are commonly found in modern electronic products. Semiconductor devices perform a wide range of functions, such as signal processing, high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, photo-electric, and creating visual images for television displays. Semiconductor devices are found in the fields of communications, power conversion, networks, computers, entertainment, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.

Semiconductor devices, particularly in high frequency applications, such as radio frequency (RF) wireless communications, often contain one or more integrated passive devices (IPDs) to perform necessary electrical functions. Multiple semiconductor die and IPDs can be integrated into an SiP module for higher density in a small space and extended electrical functionality. Within the SIP module, semiconductor die and IPDs are disposed on a substrate for structural support and electrical interconnect. An encapsulant is deposited over the semiconductor die, IPDs, and substrate.

The SIP module includes high speed digital and RF electrical components, highly integrated for small size and low height, and operating at high clock frequencies and high power rating. An electromagnetic shielding material is commonly conformally applied over the encapsulant. The electromagnetic shielding material reduces or inhibits electromagnetic interference (EMI), radio frequency interference (RFI), and other inter-device interference, for example as radiated by high-speed digital devices, from affecting neighboring devices within or adjacent to SiP module.

Semiconductor die and IPDs can be mounted to a substrate in a C2W type assembly. The C2W assembly may require shielding to reduce or inhibit EMI, RFI, and other inter-device interference.

DETAILED DESCRIPTION OF THE DRAWINGS

The present invention is described in one or more embodiments in the following description with reference to the figures, in which like numerals represent the same or similar elements. While the invention is described in terms of the best mode for achieving the invention's objectives, it will be appreciated by those skilled in the art that it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents as supported by the following disclosure and drawings. The term “semiconductor die” as used herein refers to both the singular and plural form of the words, and accordingly, can refer to both a single semiconductor device and multiple semiconductor devices.

Back-end manufacturing refers to cutting or singulating the finished wafer into the individual semiconductor die and packaging the semiconductor die for structural support, electrical interconnect, and environmental isolation. To singulate the semiconductor die, the wafer is scored and broken along non-functional regions of the wafer called saw streets or scribes. The wafer is singulated using a laser cutting tool or saw blade. After singulation, the individual semiconductor die are disposed on a package substrate that includes pins or contact pads for interconnection with other system components. Contact pads formed over the semiconductor die are then connected to contact pads within the package. The electrical connections can be made with conductive layers, bumps, stud bumps, conductive paste, or wirebonds. An encapsulant or other molding material is deposited over the package to provide physical support and electrical isolation. The finished package is then inserted into an electrical system and the functionality of the semiconductor device is made available to the other system components.

FIG. 1a shows a semiconductor wafer 100 with a base substrate material 102, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk material for structural support. A plurality of semiconductor die or components 104 is formed on wafer 100 separated by a non-active, inter-die wafer area or saw street 106. Saw street 106 provides cutting areas to singulate semiconductor wafer 100 into individual semiconductor die 104. In one embodiment, semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm).

FIG. 1b shows a cross-sectional view of a portion of semiconductor wafer 100. Each semiconductor die 104 has a back or non-active surface 108 and an active surface 110 containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface 110 to implement analog circuits or digital circuits, such as digital signal processor (DSP), application specific integrated circuits (ASIC), memory, or other signal processing circuit. Semiconductor die 104 may also contain IPDs, such as inductors, capacitors, and resistors, for RF signal processing.

An electrically conductive layer 112 is formed over active surface 110 using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer 112 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable electrically conductive material. Conductive layer 112 operates as contact pads electrically connected to the circuits on active surface 110.

An electrically conductive post 114 is formed over conductive layer 112 using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive post 114 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material.

An electrically conductive bump material is deposited over conductive post 114 using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive post 114 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form balls or bumps 116. In one embodiment, bump 116 is formed over an under bump metallization (UBM) having a wetting layer, barrier layer, and adhesive layer. Bump 116 can also be compression bonded or thermocompression bonded to conductive post 114. Bump 116 represents one type of interconnect structure that can be formed over conductive post 114. The interconnect structure can also use bond wires, conductive paste, stud bump, micro bump, or other electrical interconnect.

In FIG. 1c, semiconductor wafer 100 is singulated through saw street 106 using a saw blade or laser cutting tool 118 into individual semiconductor die 104. The individual semiconductor die 104 can be inspected and electrically tested for identification of known good die or unit (KGD/KGU) post singulation.

FIGS. 2a-2s illustrate a process of forming a C2W package with EMI shielding. FIG. 2a shows a cross-sectional view of a portion of substrate 120 including core material 122, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk material for structural support. Alternatively, core material 122 can be a multi-layer flexible laminate, ceramic, copper clad laminate (CCL), glass, or epoxy molding compound. Core material 122 may contain one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), solder resist, polyimide, benzocyclobutene (BCB), polybenzoxazoles (PBO), and other material having similar insulating and structural properties. Substrate 120 has a major surface 124 and major surface 126 opposite surface 124.

FIG. 2b shows a cross-sectional view of a portion of interconnect substrate or interposer 130 formed over surface 124 of substrate 120. Interposer 130 includes one or more conductive layers 132 and one or more insulating layers 134. Conductive layers 132 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layers 132 can be formed using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layers 132 provide horizontal electrical interconnect across interposer 130 and vertical electrical interconnect between the top surface and bottom surface of interposer 130 as a redistribution layer (RDL). Portions of conductive layers 132 can be electrically common or electrically isolated depending on the design and function of semiconductor die 104 and other electrical components. Insulating layers 134 contains one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, and other material having similar insulating and structural properties. Insulating layers 134 can be formed using PVD, CVD, printing, lamination, spin coating, spray coating, sintering or thermal oxidation. Insulating layers 134 provides isolation between conductive layers 132. There can be multiple conductive layers like 132 separated by insulating layers 134.

In another embodiment, conductive layers 132 and insulating layers 134 are individually formed over surface 124 of substrate 120 as interposer 130. For example, a first conductive layer 132 is formed, followed by a first insulating layer 134. Then a second conductive layer 132 is formed, followed by a second insulating layer 134, and so on.

In FIG. 2c, a plurality of electrical components 140a-140b is disposed on surface 136 of interposer 130 and electrically and mechanically connected to conductive layers 132. Electrical components 140a-140b are each positioned over interposer 130 using a pick and place operation. For example, electrical component 140a-140b can be similar to semiconductor die 104 from FIG. 1c with bumps 116 oriented toward surface 136 of substrate 130. Alternatively, electrical components 140a-140b can include other semiconductor die, semiconductor packages, surface mount devices, discrete electrical devices, interconnect structures, or IPDs.

Electrical components 140a-140b are brought into contact with surface 136 of interposer 130 and bonded to conductive layer 132 by reflowing bumps 116. FIG. 2d illustrates electrical components 140a-140b electrically and mechanically connected to conductive layers 132 of interposer 130, as disposed over substrate 120, as a C2W type assembly.

In FIG. 2e, a plurality of conductive posts or columns or pillars 144 is formed over surface 136 of interposer 130. Conductive pins 146 are also formed over surface 136 of interposer 130. Conductive posts 144 and conductive pins can be pre-fabricated and then bonded to surface 136 with solder or conductive paste. The assembly shown in FIG. 2e is referenced as assembly 145.

In another embodiment, conductive posts 144 and conductive pins 146 can be formed prior to mounting electrical components 140a-140b. For example, in FIG. 2f, photoresist layer 147 is formed over surface 136 of interposer 130. In FIG. 2g, a portion of photoresist layer 147 is removed by an etching process or laser direct ablation (LDA) to form openings 148 in the locations of conductive posts 144 and conductive pins 146. In FIG. 2h, openings 148 are filled with conductive material 149, such as Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. In FIG. 2i, photoresist layer 147 is removed leaving conductive posts 144 and conductive pins 146. Electrical components 140a-140b can be added returning to the state of assembly 145 in FIG. 2e.

Substrate 120, interposer 130, and assemblies 145 are in the form of wafer or strip 150, as shown in FIG. 2j. In FIG. 2j, assembly 145 is shown as a block for simplification of explanation, although it is understood that block 145 in FIG. 2j is the same as assembly 145 in FIG. 2e or 21. Each assembly 145 includes a portion of substrate 120 and a portion of interposer 130, electrical components 140a-140b, conductive posts 144, and conductive pins 146.

In FIG. 2k, an encapsulant or molding compound 160 is deposited over and around electrical components 140a-140b, conductive posts 144, conductive pins 146, and surface 136 of interposer 130 using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator. Encapsulant 160 can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler. Encapsulant 160 is non-conductive, provides structural support, and environmentally protects the semiconductor device from external elements and contaminants.

In FIG. 21, a portion of encapsulant 160 is removed by grinder 162 to planarize surface 164 of encapsulant 160 and expose surface 166 of conductive posts 144. FIG. 2m shows encapsulant 160 post grinding with planarized surface 164 and exposed surface 166 of conductive posts 144.

In FIG. 2n, an electrically conductive bump material is deposited over conductive posts 144 using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive post 144 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form balls or bumps 170. In one embodiment, bump 170 is formed over a UBM having a wetting layer, barrier layer, and adhesive layer. Bump 170 can also be compression bonded or thermocompression bonded to conductive post 144. Bump 170 represents one type of interconnect structure that can be formed over conductive post 144. The interconnect structure can also use bond wires, conductive paste, stud bump, micro bump, or other electrical interconnect.

FIG. 20 illustrates wafer 150 with encapsulant 160 and bumps 170. In FIG. 2p, wafer 150 is singulated into individual C2W packages 172 along saw streets 174, each including a portion of substrate 120, a portion of interposer 130, electrical components 140a-140b, conductive posts 144, conductive pins 146, encapsulant 160, and bumps 170. FIG. 2q shows C2W package 172 post singulation. Note that conductive pins 146 are exposed from surface 175 of encapsulant 160.

Electrical components 140a-140b may contain IPDs that are susceptible to or generate EMI, RFI, harmonic distortion, and inter-device interference. For example, the IPDs contained within electrical components 140a-140b may provide the electrical characteristics needed for high-frequency applications, such as resonators, high-pass filters, low-pass filters, band-pass filters, symmetric Hi-Q resonant transformers, and tuning capacitors. In another embodiment, electrical components 140a-140b may contain digital circuits switching at a high frequency, which could interfere with the operation of IPDs in C2W package 172 or other IPD in proximity thereto.

To address EMI, RFI, harmonic distortion, and inter-device interference, shielding material 176 is deposited over surface 126 of substrate 120, as well as surface 175 of encapsulant 160, as shown in FIG. 2r. Electromagnetic shielding material 176 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive material. Alternatively, electromagnetic shielding material 176 can be carbonyl iron, stainless steel, nickel silver, low-carbon steel, silicon-iron steel, foil, conductive resin, carbon-black, and aluminum flake. In yet another embodiment shielding material 176 can be ferromagnetic materials, Ni, Fe, Ni-Fe alloys, amorphous metal alloys, nanocrystalline metal alloys, magnetic sheets, and other metals and composites capable of reducing or inhibiting the effects of EMI, RFI, and other inter-device interference. Shielding material 176 can be formed as multiple layers of conductive and magnetic material. Shielding material 176 is grounded through conductive pins 146, as exposed from surface 175 of encapsulant 160, conductive layer 132, conductive post 144, and bumps 170 to an external ground. The assembly shown in FIG. 2r is referenced as C2W package 178.

In another embodiment, shielding material 180 is deposited over surface 182 of shielding material 176, as well as surface 164 of encapsulant 160 between bumps 170, as shown in FIG. 2s. Electromagnetic shielding material 180 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive material. Alternatively, electromagnetic shielding material 180 can be carbonyl iron, stainless steel, nickel silver, low-carbon steel, silicon-iron steel, foil, conductive resin, carbon-black, aluminum flake, and other metals and composites capable of reducing or inhibiting the effects of EMI, RFI, and other inter-device interference. Shielding material 180 is grounded through shielding material 176, conductive pins 146, as exposed from surface 175 of encapsulant 160, conductive layer 132, conductive post 144, and bumps 170 to an external ground. The assembly shown in FIG. 2s is referenced as C2W package 184.

C2W packages 178 and 184 each contain electrical components 140a-140b, conductive posts 144, conductive pins 146, interposer 130, encapsulant 160, and shielding material 176 to reduce or inhibit the effects of EMI, RFI, and other inter-device interference. Shielding material 176 is grounded through conductive pins 146, as exposed from surface 175 of encapsulant 160, conductive layer 132, conductive post 144, and bumps 170 to an external ground. C2W package 184 further contains shielding material 180 to reduce or inhibit the effects of EMI, RFI, and other inter-device interference. Shielding material 180 is grounded through shielding material 176, conductive pins 146, as exposed from surface 175 of encapsulant 160, conductive layer 132, conductive post 144, and bumps 170 to an external ground.

In another embodiment, continuing from FIG. 2b, conductive posts 190 are formed over surface 136 of interposer 130, as shown in FIG. 3a. Conductive posts 190 can be formed as described in FIG. 2e, or as described in FIGS. 2f-2i. Electrical components 140a-140b are mounted to surface 136 as described in FIGS. 2c-2d, or as described in FIGS. 2f-2i, in a C2W type assembly. Electrical components 140a-140b can be mounted to surface 136 prior to or after forming conductive posts 190. The assembly shown in FIG. 3a is referenced as assembly 192. Substrate 120, interposer 130, and assemblies 192 are in the form of a wafer or strip, similar to FIG. 2j.

In FIG. 3b, an encapsulant or molding compound 194 is deposited over and around electrical components 140a-140b, conductive posts 190, and surface 136 of interposer 130 using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator. Encapsulant 194 can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler. Encapsulant 194 is non-conductive, provides structural support, and environmentally protects the semiconductor device from external elements and contaminants.

In FIG. 3c, a portion of encapsulant 194 is removed by grinder 196 to planarize surface 198 of encapsulant 194 and expose surface 199 of conductive posts 190. FIG. 3d shows encapsulant 190 post grinding with planarized surface 196 and exposed surface 199 of conductive posts 190. A perspective view of the full wafer or strip with planarized encapsulant 194 would be similar to FIG. 20. The wafer or strip would be singulated as described in FIG. 2p, leaving individual assemblies 195 each, containing a portion of substrate 120 and a portion of interposer 130, electrical components 140a-140b, conductive posts 144, and encapsulant 194.

To address EMI, RFI, harmonic distortion, and inter-device interference, shielding material 200 is deposited over surface 126 of substrate 120, as well as surface 202 of encapsulant 194 and surface 204 of interposer 130, as shown in FIG. 3e. Electromagnetic shielding material 200 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive material. Alternatively, electromagnetic shielding material 200 can be carbonyl iron, stainless steel, nickel silver, low-carbon steel, silicon-iron steel, foil, conductive resin, carbon-black, and aluminum flake. In yet another embodiment shielding material 200 can be ferromagnetic materials, Ni, Fe, Ni-Fe alloys, amorphous metal alloys, nanocrystalline metal alloys, magnetic sheets, and other metals and composites capable of reducing or inhibiting the effects of EMI, RFI, and other inter-device interference. Shielding material 200 can be formed as multiple layers of conductive and magnetic material.

In FIG. 3f, shielding material 208 is deposited over surface 206 of shielding material 200, as well as surface 198 of encapsulant 194. Electromagnetic shielding material 208 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive material. Alternatively, electromagnetic shielding material 208 can be carbonyl iron, stainless steel, nickel silver, low-carbon steel, silicon-iron steel, foil, conductive resin, carbon-black, aluminum flake, and other metals and composites capable of reducing or inhibiting the effects of EMI, RFI, and other inter-device interference.

In FIG. 3g, a portion of shielding material 208 is removed by an etching process or LDA using laser 210. In FIG. 3h, an electrically conductive bump material is deposited over conductive posts 190 using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive post 190 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form balls or bumps 216. In one embodiment, bump 216 is formed over a UBM having a wetting layer, barrier layer, and adhesive layer. Bump 216 can also be compression bonded or thermocompression bonded to conductive post 190. Bump 216 represents one type of interconnect structure that can be formed over conductive post 190. The interconnect structure can also use bond wires, conductive paste, stud bump, micro bump, or other electrical interconnect.

Shielding material 208 is grounded through conductive posts 190a, conductive layer 132, conductive posts 190b, and bumps 216 to an external ground. Shielding material 200 is grounded through shielding material 208, conductive posts 190a, conductive layer 132, conductive posts 190b, and bumps 216 to an external ground. The assembly shown in FIG. 3h is referenced as C2W package 220.

In another embodiment, similar to FIG. 3e, shielding material 200 is grounded through conductive wires 230 embedded within encapsulant 194, conductive layer 132, conductive post 190, and bumps 232 to an external ground, as shown in FIG. 4. The assembly shown in FIG. 4 is referenced as C2W package 234.

In another embodiment, similar to FIG. 3e, shielding material 200 is grounded through conductive layer 132, as exposed from surface 204 of interposer 130, conductive post 190, and bumps 240 to an external ground, as shown in FIG. 5. The assembly shown in FIG. 5 is referenced as C2W package 238.

In another embodiment, similar to FIG. 3e, shielding material 200 is grounded through conductive vias 248, as formed through substrate 120, conductive layer 132, conductive post 190, and bumps 246 to an external ground, as shown in FIG. 6. The assembly shown in FIG. 6 is referenced as C2W package 244.

In another embodiment, FIG. 7a shows a cross-sectional view of a portion of wafer or strip substrate 250, similar to substrate 120. Electrical component 252 is mounted to substrate 250, similar to electrical components 140a-140b, as a C2W type assembly. Conductive posts 256 are formed on substrate 250, similar to conductive posts 144. The assembly shown in FIG. 7a is referenced as assembly 260.

FIG. 7b shows the full wafer 250 with a plurality of assemblies 260. In FIG. 7b, assembly 260 is shown as a block for simplification of explanation, although it is understood that block 260 in FIG. 7b is the same as assembly 260 in FIG. 7a. In FIG. 7c, wafer 250 is singulated along saw streets 262 using a saw blade or laser cutting tool into individual assemblies 260, each assembly containing a portion of substrate 250, electrical component 252, and conductive posts 256 disposed around the electrical component, as in FIG. 7a.

In FIG. 7d, the singulated assemblies 260 are mounted to temporary carrier 268 with an adhesive to form reconstituted wafer 270. FIG. 7e shows a perspective view of assemblies 260 mounted to carrier 268 as reconstituted wafer 270.

In FIG. 7f, an encapsulant or molding compound 272 is deposited over and around assemblies 260, each with electrical component 252, conductive posts 256, and a portion of carrier 267, using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator. Encapsulant 272 can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler. Encapsulant 272 is non-conductive, provides structural support, and environmentally protects the semiconductor device from external elements and contaminants.

In FIG. 7g, a portion of encapsulant 272 is removed by grinder 274 to planarize surface 276 of encapsulant 272 and expose a top surface of conductive posts 256. FIG. 7h shows encapsulant 272 post grinding with planarized surface 276.

In FIG. 7i, interconnect substrate or interposer 280 is formed over assemblies 260 and encapsulant 272. Interposer 280 includes one or more conductive layers 282 and one or more insulating layers 284. Conductive layers 282 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layers 282 can be formed using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layers 282 provide horizontal electrical interconnect across interposer 280 and vertical electrical interconnect between the top surface and bottom surface of interposer 280 as an RDL. Portions of conductive layers 282 can be electrically common or electrically isolated depending on the design and function of semiconductor die 104 and other electrical components. Insulating layers 284 contains one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, and other material having similar insulating and structural properties. Insulating layers 284 can be formed using PVD, CVD, printing, lamination, spin coating, spray coating, sintering or thermal oxidation. Insulating layers 284 provides isolation between conductive layers 282. There can be multiple conductive layers like 282 separated by insulating layers 284.

In FIG. 7j, reconstituted wafer 270 is singulated using a saw blade or laser cutting tool 288 into individual assemblies 290, each assembly containing a portion of substrate 250, electrical component 252, conductive posts 256 disposed around the electrical component, encapsulant 272, and a portion of interposer 280. The singulation of wafer 270 exposes conductive layer 282 from a side surface of interposer 280. Carrier 268 is removed by chemical mechanical polishing (CMP), mechanical peel-off, mechanical grinding, thermal bake, UV light, or wet stripping, leaving assembly 290, as shown in FIG. 7k.

An electrically conductive bump material is deposited over conductive layer 282 using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer 282 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form balls or bumps 292. In one embodiment, bump 292 is formed over a UBM having a wetting layer, barrier layer, and adhesive layer. Bump 292 can also be compression bonded or thermocompression bonded to conductive layer 282. Bump 292 represents one type of interconnect structure that can be formed over conductive layer 282. The interconnect structure can also use bond wires, conductive paste, stud bump, micro bump, or other electrical interconnect.

Electrical component 252 may contain IPDs that are susceptible to or generate EMI, RFI, harmonic distortion, and inter-device interference. For example, the IPDs contained within electrical component 252 may provide the electrical characteristics needed for high-frequency applications, such as resonators, high-pass filters, low-pass filters, band-pass filters, symmetric Hi-Q resonant transformers, and tuning capacitors. In another embodiment, electrical component 252 may contain digital circuits switching at a high frequency, which could interfere with the operation of IPDs in C2W package 310 or other IPD in proximity thereto.

To address EMI, RFI, harmonic distortion, and inter-device interference, shielding material 300 is deposited over surface 302 of substrate 250, as well as surface 304 of encapsulant 272 and surface 306 of interposer 280, as shown in FIG. 71. Electromagnetic shielding material 300 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive material. Alternatively, electromagnetic shielding material 300 can be carbonyl iron, stainless steel, nickel silver, low-carbon steel, silicon-iron steel, foil, conductive resin, carbon-black, and aluminum flake. In yet another embodiment shielding material 300 can be ferromagnetic materials, Ni, Fe, Ni-Fe alloys, amorphous metal alloys, nanocrystalline metal alloys, magnetic sheets, and other metals and composites capable of reducing or inhibiting the effects of EMI, RFI, and other inter-device interference. Shielding material 300 can be formed as multiple layers of conductive and magnetic material. Shielding material 300 is grounded through conductive layer 282, as exposed from surface 306 of interposer 280, and bumps 292 to an external ground. The assembly shown in FIG. 71 is referenced as C2W package 310.

C2W packages 310 contains electrical component 252, conductive posts 256, interposer 280, encapsulant 272, and shielding material 300 to reduce or inhibit the effects of EMI, RFI, and other inter-device interference. Shielding material 300 is grounded through conductive layer 282, as exposed from surface 306 of interposer 280 and bumps 292 to an external ground.

FIG. 8 illustrates electrical device 400 having a chip carrier substrate or PCB 402 with a plurality of semiconductor packages disposed on a surface of PCB 402, including C2W packages 178, 184, 220, 234, 238, 244, and 310. Electrical device 400 can have one type of semiconductor package, or multiple types of semiconductor packages, depending on the application.

Electrical device 400 can be a stand-alone system that uses the semiconductor packages to perform one or more electrical functions. Alternatively, electrical device 400 can be a subcomponent of a larger system. For example, electrical device 400 can be part of a tablet, cellular phone, digital camera, communication system, or other electrical device. Alternatively, electrical device 400 can be a graphics card, network interface card, or other signal processing card that can be inserted into a computer. The semiconductor package can include microprocessors, memories, ASIC, logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor die or electrical components. Miniaturization and weight reduction are essential for the products to be accepted by the market. The distance between semiconductor devices may be decreased to achieve higher density.

In FIG. 8, PCB 402 provides a general substrate for structural support and electrical interconnect of the semiconductor packages disposed on the PCB. Conductive signal traces 404 are formed over a surface or within layers of PCB 402 using evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition process. Signal traces 404 provide for electrical communication between each of the semiconductor packages, mounted components, and other external system components. Traces 404 also provide power and ground connections to each of the semiconductor packages.

In some embodiments, a semiconductor device has two packaging levels. First level packaging is a technique for mechanically and electrically attaching the semiconductor die to an intermediate substrate. Second level packaging involves mechanically and electrically attaching the intermediate substrate to the PCB. In other embodiments, a semiconductor device may have the first level packaging where the die is mechanically and electrically disposed directly on the PCB. For the purpose of illustration, several types of first level packaging, including bond wire package 406 and flipchip 408, are shown on PCB 402. Additionally, several types of second level packaging, including ball grid array (BGA) 410, bump chip carrier (BCC) 412, land grid array (LGA) 416, multi-chip module (MCM) or SIP module 418, quad flat non-leaded package (QFN) 420, quad flat package 422, embedded wafer level ball grid array (eWLB) 424, and wafer level chip scale package (WLCSP) 426 are shown disposed on PCB 402. In one embodiment, eWLB 424 is a fan-out wafer level package (Fo-WLP) and WLCSP 426 is a fan-in wafer level package (Fi-WLP). Depending upon the system requirements, any combination of semiconductor packages, configured with any combination of first and second level packaging styles, as well as other electrical components, can be connected to PCB 402. In some embodiments, electrical device 400 includes a single attached semiconductor package, while other embodiments call for multiple interconnected packages. By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate pre-made components into electrical devices and systems. Because the semiconductor packages include sophisticated functionality, electrical devices can be manufactured using less expensive components and a streamlined manufacturing process. The resulting devices are less likely to fail and are less expensive to manufacture, resulting in a lower cost for consumers.