ISOLATION STRUCTURE HAVING DIFFERENT LINERS ON UPPER AND LOWER PORTIONS

An isolation structure for a substrate is disclosed. The isolation structure includes a lower portion having a first liner, and an upper portion having a second liner vertically over the first liner. A first dielectric material is surrounded by the second liner from above and by the first liner from below and laterally. The second liner may include a second dielectric material in at least part thereof. The second liner prevents exposure of end surfaces of a semiconductor layer of the substrate during subsequent processing, which prevents damage such as thinning, agglomeration and/or oxidation that can negatively affect performance of a transistor formed using the semiconductor layer. The second liner also reduces an overall step height of the isolation structure.

BACKGROUND

The present disclosure relates to integrated circuit (IC) structures and, more particularly, to an isolation structure having upper and lower portions with different liners.

Isolation structures are used to electrically separate areas of a semiconductor layer in an IC structure. An isolation structure includes a single silicon nitride liner within a dielectric-filled trench. During formation, the dielectric material is recessed within the trench, which can damage the single liner and can lead to thinning, agglomeration, and oxidation of the exposed end surfaces of the semiconductor layer during subsequent processing. The agglomeration and oxidization of the end surfaces of the semiconductor layer can negatively affect performance of a transistor, such as increased current leakage.

SUMMARY

All aspects, examples and features mentioned below can be combined in any technically possible way.

An aspect of the disclosure provides an isolation structure for a substrate, the isolation structure comprising: a lower portion having a first liner; an upper portion having a second liner vertically over the first liner; and a first dielectric material surrounded by the second liner from above and by the first liner from below and laterally.

An aspect of the disclosure provides an isolation structure for a substrate, the isolation structure comprising: a lower portion having a first U-shaped liner and a first dielectric material within the first U-shaped liner; and an upper portion over the lower portion, the upper portion having a second U-shaped liner and a second dielectric material within at least part of the second U-shaped liner, wherein a lower section of the second U-shaped liner contacts an upper surface of the first dielectric material.

An aspect of the disclosure provides a method, comprising: forming a first U-shaped liner within a trench extending through a semiconductor layer of a substrate; filling at least a portion of the trench with a first dielectric material; forming a second U-shaped liner in the trench over the first dielectric material in the trench and below an upper surface of the semiconductor layer; and filling at least part of the second U-shaped liner with a second dielectric material.

Two or more aspects described in this disclosure, including those described in this summary section, may be combined to form implementations not specifically described herein. The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features, objects and advantages will be apparent from the description and drawings, and from the claims.

DETAILED DESCRIPTION

Reference in the specification to “one embodiment” or “an embodiment” of the present disclosure, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the phrases “in one embodiment” or “in an embodiment,” as well as any other variations appearing in various places throughout the specification are not necessarily all referring to the same embodiment. It is to be appreciated that the use of any of the following “/,” “and/or,” and “at least one of,” for example, in the cases of “A/B,” “A and/or B” and “at least one of A and B,” is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of both options (A and B). As a further example, in the cases of “A, B, and/or C” and “at least one of A, B, and C,” such phrasing is intended to encompass the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B), or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C). This may be extended, as readily apparent by one of ordinary skill in the art, for as many items listed.

FIGS.1-7show cross-sectional views of a method of forming an isolation structure100(FIG.7) according to embodiments of the disclosure. As understood by those with skill in the art, an isolation structure, also referred to as a trench isolation, typically includes a trench filled with a dielectric material, to isolate one region of a substrate from an adjacent region of the substrate. One or more transistors of a given polarity or other devices may be disposed within an area isolated by the isolation structure. As noted, an isolation structure for a substrate may include a single silicon nitride liner within a dielectric-filled trench. During formation, the dielectric material is recessed within the trench, which can damage the single liner and can lead to thinning, agglomeration, and oxidation of the exposed end surfaces of the semiconductor layer during subsequent processing. The agglomeration and oxidization of the end surfaces of the semiconductor layer can negatively affect performance of the transistor, such as increased current leakage.

Embodiments of the disclosure include an isolation structure for a substrate and a related method of forming the isolation structure. The isolation structure includes a lower portion having a first liner, and an upper portion having a second liner vertically over the first liner. A first dielectric material is surrounded by the second liner from above and by the first liner from below and laterally. The second liner may include a second dielectric material in at least part thereof. The second liner prevents exposure of end surfaces of a semiconductor layer of the substrate during subsequent processing, which prevents damage such as thinning, agglomeration, and/or oxidation that can negatively affect performance of a transistor formed using the semiconductor layer. The second liner also reduces an overall step height of the isolation structure.

FIG.1shows a cross-sectional view of a preliminary structure102for a method of forming isolation structure100(FIG.6), according to embodiments of the disclosure. Preliminary structure102includes a substrate110. For purposes of description, substrate110is illustrated and described as a semiconductor-on-insulator (SOI) substrate. An SOI substrate includes a layered semiconductor-insulator-semiconductor substrate in place of a more conventional silicon substrate (bulk substrate). Substrate110includes a semiconductor layer112, sometimes referred to as a semiconductor-on-insulator (SOI) layer, over a buried insulator layer114over a base semiconductor layer116. Semiconductor layer112and base semiconductor layer116may include any semiconductor material described herein. For example, semiconductor layer112may include silicon germanium (SiGe) and base semiconductor layer116may include silicon (Si), germanium (Ge), SiGe, silicon carbide, among other semiconductor materials. Buried insulator layer114may include any appropriate dielectric such as but not limited to silicon dioxide, i.e., forming a buried oxide (BOX) layer. A portion of or the entire semiconductor substrate, including semiconductor layer112, may be stressed. For example, semiconductor layer112may include a compressive SiGe for improving performance of a p-type transistor to be formed therein. The precise thickness of buried insulator layer114and semiconductor layer112may vary widely with the intended application. In certain embodiments, substrate110may be a fully depleted SOI (FDSOI) substrate. FDSOI substrates use a very thin buried insulator layer114(e.g., 5-100 nanometers (nm)) and an ultra-thin semiconductor layer112(e.g., 5-100 nm) over buried insulator layer114that provides the transistor channel. The ultra-thin semiconductor layer112does not need to be doped to create the channel, thus making the transistor “fully depleted.” The ultra-thin semiconductor layer112in an FDSOI substrate is especially vulnerable to damage caused by recessing of an isolation structure extending through it. While embodiments of the disclosure will be described relative to an SOI or FDSOI substrate110, the teachings of the disclosure are applicable to an isolation structure for any semiconductor layer (e.g., SOI or bulk) requiring protection from damage caused by isolation structure formation.

Preliminary structure102includes an initial isolation structure120. Initial isolation structure120may be formed by forming a first liner122within a trench124extending through (at least) semiconductor layer112of substrate110and filling a remaining portion of trench124with a first dielectric material126. More particularly, a mask130may be formed over substrate110and patterned to define opening132that can be used to etch trench124into substrate110. Mask130may include any now known or later developed masking material such as but not limited to photoresist (resist) and nitride. Nitride is usually considered to be a “hard mask. Mask130may include a developable organic planarization layer (OPL) on the layer to be etched, a developable anti-reflective coating (ARC) layer on the developable OPL, and a photoresist mask layer on the developable ARC layer (different layers not shown for clarity). After processing, as will be described, the underlying layer, mask130may be removed. Mask130may be removed using any known removal process appropriate for the mask material, e.g., a wet etch for hard nitride mask or an ashing process (oxygen dry strip process) for a soft resist-based mask, or planarization process such as chemical mechanical polishing. Possible oxide and/or nitride capping layers between semiconductor layer112and mask130have been omitted for clarity. The etching process to form trench124may include any etching chemistry appropriate for substrate110, e.g., a reactive ion etch.

First liner122may be deposited in trench124using any appropriate deposition technique for the liner material used. In certain embodiments, first liner122may include at least one of silicon nitride and silicon oxynitride, and may be deposited using chemical vapor deposition (CVD). First liner122may be U-shaped and thus may also be referenced herein as “first U-shaped liner122.”

FIG.1also shows filling a remaining portion of trench124, i.e., that part not filled by first liner122, with a first dielectric material126to form initial isolation structure120. First dielectric material126may be deposited using any appropriate deposition technique for the first dielectric material126used. In certain embodiments, first dielectric material126may include an oxide and be deposited using CVD. Other materials (and deposition techniques) may also be used, such as but not limited to: fluorinated SiO2(FSG), hydrogenated silicon oxycarbide (SiCOH), porous SiCOH, boro-phospho-silicate glass (BPSG), silicon carbon-nitride (SiCN) and silicon carbide materials. Any excess material may be removed using an appropriate planarization technique, such as but not limited to chemical mechanical polishing (CMP).

Trench124may extend into substrate110to any desired depth D to ensure electrical isolation for devices to be subsequently built on or into substrate110. In this regard, trench124may have a depth D (relative to an upper surface134of semiconductor layer112of substrate110) that would result in an isolation structure that is considered to be a shallow trench isolation structure with a depth D of, for example, 10-100 nm, or a deep trench isolation structure with a depth D of, for example, 50-1000 nm.

FIG.2shows a cross-sectional view of recessing initial isolation structure120, according to embodiments of the disclosure. The recessing may include any etching chemistry appropriate for first dielectric material126, e.g., a reactive ion etch, and/or stripping process to remove first liner122. As shown inFIG.2, the recessing removes first dielectric material126from an upper section of trench124, creating a recessed area136. In addition, the recessing removes at least part of first liner122, e.g., from sidewalls of mask130, end surfaces150,152of semiconductor layer112and sidewalls of buried insulator layer114. As illustrated, the recessing causes first liner122to be shortened in height but retain the afore-mentioned U-shape. At this stage, first liner122includes a first leg140, a second leg142and a bight portion144coupling legs140,142. A depth of recessed area136may be user defined, but typically extends into at least buried insulator layer114to expose end surfaces150,152of semiconductor layer112.FIGS.1-2thus show filling at least a portion of trench124with first dielectric material126. Other methodologies may also be possible to arrive at the same structure as shown inFIG.2.

FIG.3shows a cross-sectional view of forming a second liner160, according to embodiments of the disclosure. More particularly,FIG.3shows forming second liner160in trench124over first dielectric material126and first liner122in trench124. Second liner160, as will be further described, may be U-shaped and thus may also be referenced herein as “second U-shaped liner160.” As illustrated, because recessed area136extends below upper surface134of semiconductor layer112, second liner160extends below upper surface134of semiconductor layer112, i.e., in trench124. Second liner160abuts end surfaces150,152of semiconductor layer112, i.e., it covers end surfaces150,152. In this arrangement, as will be further described, second liner160protects semiconductor layer112from damage from subsequent processing such as thinning, agglomeration or oxidation. Second liner160includes a different material than first liner122. In certain embodiments, second liner160includes at least one of silicon oxy-carbonitride (SiOCN), silicon carbo-nitride (SiCN) and silicon boro-carbon nitride (SiBCN). The materials for second liner160have a slower etch rate than first liner122.

Second liner160is also thicker than first liner122. More particularly, recessed area136is not as deep as initial trench124, which allows a second liner160to be formed thicker than first liner122. As shown inFIG.3, first liner122may have a thickness T1 that is thinner than a thickness T2 of second liner160. In one non-limiting example, second liner160may have a thickness T2 in a range of 6-14 nm, and first liner122may have a thickness T1 in a range of 4-12 nm. Second liner160also extends over an upper surface162of mask130. As noted, second liner160has a U-shape within recessed area136. More particularly, second liner160includes a first leg164, a second leg166and a bight portion168coupling legs164,166.

FIGS.4-5show cross-sectional views of forming a second dielectric material170in second liner160, according to embodiments of the disclosure. Forming second dielectric material170includes at least partially filling second liner160with second dielectric material170. InFIG.4, all of recessed area136and second liner160is shown filled, i.e., an upper surface172of second dielectric material170is coplanar with upper end surfaces174of legs164,166of second liner160. However, as will be described, upper surface172of second dielectric material170may eventually not be coplanar with upper end surfaces174of legs164,166of second liner160. Further, upper surface172of second dielectric material170may eventually be below upper surface134of semiconductor layer112. Second dielectric material170may be deposited using any appropriate deposition technique for the second dielectric material170used. In certain embodiments, second dielectric material170may include an oxide and be deposited using high density plasma chemical vapor deposition (HPD-CVD), forming an HDP-CVD oxide. HDP-CVD oxide has higher density than first dielectric material126, regardless of the latter material's form. Other dielectric materials as listed herein (and deposition techniques) may also be used. In any event, first dielectric material126is different than second dielectric material170. As shown inFIG.5, any excess material may be removed using any appropriate planarization technique, such as but not limited to chemical mechanical polishing (CMP). The planarization may also remove second liner160from over mask130.

FIG.6shows a cross-sectional view of removing mask130, according to embodiments of the disclosure. Mask130may be removed using any now known or later developed technique appropriate for the mask material, such as but not limited to a wet etch for a hard nitride mask. As shown, second liner160does not etch as quickly as mask130and so remains, protecting second dielectric material170therein.

FIG.7shows a cross-sectional view of isolation structure100, according to embodiments of the disclosure. Isolation structure100is shown after additional processing that causes second dielectric material170and second liner160to be initially coplanar with upper surface134of semiconductor layer112, and eventually causes upper surface172of second dielectric material170to be below upper surface134of semiconductor layer112. The additional processing may include but is not limited to: wet etches such as dilute hydrofluoric (DHF) acid wet cleans, and thermal processing such as those used for driving in dopants to semiconductor layer112. The processing reduces a height H1 of second dielectric material170and the overall step height H2 of isolation structure100. The processing also consumes some of second liner160, but the thickness and materials of second liner160do not allow the processing to affect semiconductor layer112in a negative fashion. That is, second liner160continues to protect semiconductor layer112from damage such as thinning, agglomeration and oxidation.FIG.8shows other embodiments in which the processing does not affect second dielectric material170as much as inFIG.7. InFIG.8, second dielectric material170fills more of the U-shape of second liner160than shown inFIG.7, and may include upper surface172coplanar, or closer to coplanar, with upper surface134of semiconductor layer112.

Additional conventional processing, not shown inFIGS.7-8, can be performed with isolation structure100completed. The additional processing may include any now known or later developed front-end-of-line (FEOL) processing to build active devices like transistors, and/or middle-of-line (MOL) and back-end-of-line (BEOL) processing to, among other things, provide electrical interconnections between active devices. The additional processing may also fill a space above isolation structure100with, among other things, additional dielectric material, such as an interlayer dielectric material.

Referring toFIGS.7and8, isolation structure100for substrate110includes a lower portion180having first liner122, and an upper portion182having second liner160vertically over first liner122. First dielectric material126is surrounded by: second liner160from above (i.e., by a lower part of bight portion168from above) and by first liner122from below (i.e., by bight portion144of first liner122) and laterally (i.e., by legs140,142of first liner122). Second liner160abuts end surfaces150,152of semiconductor layer112of substrate110, protecting it from damage. Second liner160is U-shaped, and second dielectric material170is within at least a part of the U-shape of second liner160. As shown inFIG.7, in certain embodiments, second dielectric material170may partially fill the U-shape of second liner160and may include upper surface172thereof below upper surface134of semiconductor layer112. As shown inFIG.8, in other embodiments, second dielectric material170may fill more of the U-shape of second liner160than shown inFIG.7, and may include upper surface172coplanar, or closer to coplanar, with upper surface134of semiconductor layer112.

First dielectric material126is different than second dielectric material170. As described, in one example, first dielectric material126may include a first oxide (e.g., CVD oxide) and second dielectric material170may include a second oxide (e.g., an HDP-CVD oxide), the latter of which has a higher density than first dielectric material126, regardless of the latter's form. Other dielectric materials may also be possible. In certain embodiments, first liner122may include at least one of silicon nitride and silicon oxynitride, and second liner160may include at least one of silicon oxy-carbonitride (SiOCN), silicon carbo-nitride (SiCN) and silicon boro-carbon nitride (SiBCN). Other liner materials are also possible. First liner122is thinner than second liner160, which, in part, allows second liner160to protect semiconductor layer112from damage during the subsequent processing described herein. First liner122and second liner160are both U-shaped.

In other embodiments, isolation structure100includes lower portion180having first U-shaped liner122and first dielectric material126within first U-shaped liner122. Isolation structure100also includes upper portion182over lower portion180. Portions180,182may be referred to as stacked together. Upper portion182has second U-shaped liner160and second dielectric material170within at least part of second U-shaped liner160. As noted, first dielectric material126is different than second dielectric material170. Further, first U-shaped liner122is thinner than second U-shaped liner160. In certain embodiments, shown inFIG.7, second dielectric material170partially fills second U-shaped liner160and includes upper surface172below upper surface134of semiconductor layer112. As shown inFIG.8, in other embodiments, second dielectric material170may fill more of the U-shape of second liner160than shown inFIG.7, and may include upper surface172coplanar, or closer to coplanar, with upper surface134of semiconductor layer112.

In the structures and method described above, a semiconductor material refers to a material whose conducting properties can be altered by doping with an impurity. Semiconductor materials include, for example, silicon-based semiconductor materials (e.g., silicon, silicon germanium, silicon germanium carbide, silicon carbide, etc.) and III-V compound semiconductors (i.e., compounds obtained by combining group III elements, such as aluminum (Al), gallium (Ga), or indium (In), with group V elements, such as nitrogen (N), phosphorous (P), arsenic (As) or antimony (Sb)) (e.g., GaN, InP, GaAs, or GaP). A pure semiconductor material and, more particularly, a semiconductor material that is not doped with an impurity for the purposes of increasing conductivity (i.e., an undoped semiconductor material) is referred to in the art as an intrinsic semiconductor. A semiconductor material that is doped with an impurity for the purposes of increasing conductivity (i.e., a doped semiconductor material) is referred to in the art as an extrinsic semiconductor and will be more conductive than an intrinsic semiconductor made of the same base material. That is, extrinsic silicon will be more conductive than intrinsic silicon; extrinsic silicon germanium will be more conductive than intrinsic silicon germanium; and so on. Furthermore, it should be understood that different impurities (i.e., different dopants) can be used to achieve different conductivity types (e.g., P-type conductivity and N-type conductivity) and that the dopants may vary depending upon the different semiconductor materials used. For example, a silicon-based semiconductor material (e.g., silicon, silicon germanium, etc.) is typically doped with a Group III dopant, such as boron (B) or indium (In), to achieve P-type conductivity, whereas a silicon-based semiconductor material is typically doped a Group V dopant, such as arsenic (As), phosphorous (P) or antimony (Sb), to achieve N-type conductivity. A gallium nitride (GaN)-based semiconductor material is typically doped with magnesium (Mg) to achieve P-type conductivity and with silicon (Si) or oxygen to achieve N-type conductivity. Those skilled in the art will also recognize that different conductivity levels will depend upon the relative concentration levels of the dopant(s) in a given semiconductor region. Furthermore, when a semiconductor region or layer is described as being at a higher conductivity level than another semiconductor region or layer, it is more conductive (less resistive) than the other semiconductor region or layer; whereas, when a semiconductor region or layer is described as being at a lower conductivity level than another semiconductor region or layer, it is less conductive (more resistive) than that other semiconductor region or layer.

Embodiments of the disclosure provide various technical and commercial advantages, examples of which are discussed herein. For example, the second liner prevents exposure of end surfaces of a semiconductor layer of the substrate during subsequent processing, which prevents damage such as thinning, agglomeration and/or oxidation that can negatively affect performance of a transistor formed using the semiconductor layer. The second liner also reduces an overall step height of the isolation structure.