Stacked type semiconductor device including through electrode

There are provided a stacked type semiconductor device and a manufacturing method of the stacked type semiconductor device. The stacked type semiconductor device includes: semiconductor chips stacked to overlap with each other; through electrodes respectively penetrating the semiconductor chips, the through electrodes being bonded to each other; and empty gaps respectively buried in the through electrodes.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean patent application number 10-2020-0030963, filed on Mar. 12, 2020, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

BACKGROUND

1. Technical Field

The present disclosure generally relates to a stacked type semiconductor device and a manufacturing method of the stacked type semiconductor device, and more particularly, to a stacked type semiconductor device including a through electrode and a manufacturing method of the stacked type semiconductor device.

2. Related Art

In a stacked type semiconductor device, semiconductor chips overlap with each other, so that the degree of integration of the semiconductor device can be improved. The semiconductor chips overlapping with each other may be electrically connected to each other through through electrodes. The through electrodes can decrease the length of an interconnection structure between the semiconductor chips overlapping with each other, and thus the semiconductor device having an improved data transmission speed can be provided.

SUMMARY

In accordance with an aspect of the present disclosure, there may be provided a stacked type semiconductor device including: semiconductor chips stacked to overlap with each other; through electrodes respectively penetrating the semiconductor chips, wherein the through electrodes are bonded to each other; and empty gaps respectively buried in the through electrodes.

In accordance with another aspect of the present disclosure, there may be provided a method of manufacturing a stacked type semiconductor device, the method including: forming a first semiconductor chip penetrated by a first through electrode in which a first empty gap is buried; forming a second semiconductor chip penetrated by a second through electrode in which a second empty gap is buried; aligning the first semiconductor chip on the second semiconductor chip; and bonding the first through electrode to the second through electrode.

DETAILED DESCRIPTION

Specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments according to the concept of the present disclosure. Embodiments according to the concept of the present disclosure can be implemented in various forms, and should not be construed as limited to the embodiments set forth herein.

Hereinafter, the terms ‘first’ and ‘second’ are used to distinguish one component from another component. For example, a first component may be referred to as a second component without departing from a scope in accordance with the concept of the present disclosure and similarly, a second component may be referred to as a first component.

Embodiments provide a stacked type semiconductor device capable of improving the stability of a bonding structure, and a manufacturing method of the stacked type semiconductor device.

FIG. 1is a sectional view schematically illustrating a stacked type semiconductor device10in accordance with an embodiment of the present disclosure.FIG. 1is a sectional view taken along a through via region in which through electrodes TE1to TEn of the stacked type semiconductor device10are disposed.

Referring toFIG. 1, the stacked type semiconductor device10may include a plurality of semiconductor chips C1to Cn (n is a natural number of 2 or more). The semiconductor chips C1to Cn may be stacked to overlap with each other. The semiconductor chips C1to Cn may be penetrated by the through electrodes TE1to TEn.

The number and arrangement of through electrodes penetrating each of the semiconductor chips C1to Cn may be various. The through electrodes TE1to TEn respectively penetrating different semiconductor chips C1to Cn may be aligned in a line. A bonding medium such as a bump may be disposed between through electrodes to achieve electrical connection between the through electrodes. In embodiments of the present disclosure, the through electrodes TE1to TEn aligned in a line may be directly bonded to each other without any medium such as a bump, to be electrically connected to each other. The through electrodes TE1to TEn connected to each other may be used as data transmission path.

The semiconductor chips C1to Cn may be the same kind of chips or different kinds of chips. In an embodiment, each of the semiconductor chips C1to Cn may be a memory chip. In another embodiment, at least one of the semiconductor chips C1to Cn may correspond to a logic chip, and the others may correspond to a memory chip. In still another embodiment, at least one of the semiconductor chips C1to Cn may correspond to a logic chip, and the others may correspond to a pixel chip.

Each of the through electrodes TE1to TEn may include a buffer part BP and a vertical part VP extending from the buffer part BP. The vertical part VP of an upper through electrode and the buffer part of a lower through electrode are bonded to each other, so that the through electrodes TE1to TEn are electrically connected to each other.

Hereinafter, a semiconductor chip (e.g., C2) disposed at a relatively upper portion among the semiconductor chips C1to Cn is designated as a first semiconductor chip, and a semiconductor chip (e.g., C3) disposed at a relatively lower portion among the semiconductor chips C1to Cn is designated as a second semiconductor chip. In addition, a through electrode (e.g., TE2) disposed at a relatively upper portion among the through electrodes TE1to TEn is designated by a first through electrode, and a through electrode (e.g., TE3) disposed at a relatively lower portion among the through electrodes TE1to TEn is designated by a second through electrode.

FIG. 2is an enlarged sectional view illustrating region A shown inFIG. 1. buffer parts BP of the through electrodes TE1to TEn described with reference toFIG. 1may include a first buffer part BPa of a first through electrode TE2and a second buffer part BPb of a second through electrode TE3, and vertical parts VP of the through electrodes TE1to TEn described with reference toFIG. 1may include a first vertical part VPa of the first through electrode TE2and a second vertical part VPb of the second through electrode TE3.

Referring toFIG. 2, each of a first semiconductor chip C2and a second semiconductor chip C3may include a substrate110aor110b, a first insulating structure120aor120b, a conductive pad130aor130b, and a second insulating structure140aor140b.

Each of the substrates110aand110bof the first semiconductor chip C2and the second semiconductor chip C3may have a first surface SU1aor SU1band a second surface SU2aor SU2bopposite to the first surface SU1aor SU1b. The first insulating structures120aand120bof the first semiconductor chip C2and the second semiconductor chip C3may be formed on the first surfaces SU1aand SU1bof the substrates110aand110b, respectively. The conductive pad130aof the first semiconductor chip C2may face the first surface SU1aof the substrate110awith the first insulating structure120ainterposed therebetween and the conductive pad130bof the second semiconductor chip C3may face the first surface SU1bof the substrate110bwith the first insulating structure120binterposed therebetween. The second insulating structures140aand140bof the first semiconductor chip C2and the second semiconductor chip C3may be formed to respectively cover a surface of the first insulating structure120a, on which the conductive pad130ais disposed, and a surface of the first insulating structure120b, on which the conductive pad130bis disposed.

The substrate110bof the second semiconductor chip C3may be bonded to the second insulating structure140aof the first semiconductor chip C2. Each of the first through electrode TE2and the second through electrode TE3may fill a buffer hole and a via hole, which correspond thereto. In other words, the first through electrode TE2may fill a first buffer hole BHa and a first via hole VHa, and the second through electrode TE3may fill a second buffer hole BHb and a second via hole VHb.

The first buffer hole BHa may extend toward the second surface SU2afrom the first surface SU1ato penetrate the substrate110aof the first semiconductor chip C2. The first via hole VHa may extend from the first buffer hole BHa, and may penetrate the first insulating structure120a, the conductive pad130a, and the second insulating structure140aof the first semiconductor chip C2. The first buffer part BPa of the first through electrode TE2may be disposed in the first buffer hole BHa. The first vertical part VPa of the first through electrode TE2may extend from the first buffer part BPa and fill the first via hole VHa.

The second buffer hole BHb may extend toward the second surface SU2bfrom the first surface SU1bto penetrate the substrate110bof the second semiconductor chip C3. The second via hole VHb may extend from the second buffer hole BHb, and may penetrate the first insulating structure120b, the conductive pad130b, and the second insulating structure140bof the second semiconductor chip C3. The second buffer part BPb of the second through electrode TE3may be disposed in the second buffer hole BHb. The second vertical part VPb of the second through electrode TE3may extend from the second buffer part BPb and fill the second via hole VHb.

The substrates110aand110bof the first and second semiconductor chips C2and C3may be insulated from the first and second through electrodes TE2and TE3by sidewall insulating patterns151aand151b. The sidewall insulating pattern151amay extend between the buffer part BPa and the substrate110aand between the vertical part VPa and the first insulating structure120a. The sidewall insulating pattern151bmay extend between the buffer part BPb and the substrate110band between the vertical part VPb and the first insulating structure120b. The first vertical part VPa of the first through electrode TE2and the second vertical part VPb of the second through electrode TE3may be in contact with the conductive pads130aand130b, respectively. In an embodiment, the first vertical part VPa of the first through electrode TE2may farther protrude than the sidewall insulating pattern151ato be in contact with the conductive pad130aand the second insulating structure140a, and the first vertical part VPb of the second through electrode TE3may farther protrude than the sidewall insulating pattern151bto be in contact with the conductive pad130band the second insulating structure140b.

Empty gaps may be respectively buried in the first and second through electrodes TE2and TE3. The empty gaps may comprise air-gaps. The empty gaps may include a first empty gap159aburied in the first through electrode TE2and a second empty gap159bburied in the second through electrode TE3. The first vertical part VPa may be disposed between the first empty gap159aand the second empty gap159b.

The first empty gap159amay be disposed in the first buffer hole BHa, and be surrounded by the first buffer part BPa of the first through electrode TE2. That is, the first empty gap159amay be sealed in the first buffer hole BHa by the first buffer part BPa.

The second empty gap159bmay be disposed in the second buffer hole BHb, and be surrounded by the second buffer part BPb of the second through electrode TE3. That is, the second empty gap159bmay be sealed in the second buffer hole BHb by the second buffer part BPb.

Each of the first and second buffer holes BHa and BHb may have a width wider than that of each of the first and second via holes VHa and VHb. Accordingly, a width WB of the buffer part BP shown inFIG. 1can be defined to be greater than a width WA of the vertical part VP. Further, the first and second empty gaps159aand159bcan be formed in the first and second buffer holes BHa and BHb. In an embodiment, each of the first and second buffer holes BHa and BHb may have a curved sidewall extending in a stacked direction in which the first through electrode TE2and the second through electrode TE3are stacked, and each of the first and second via holes VHa and VHb may have a flat sidewall extending in the stacked direction.

The second buffer part BPb may include a recessed part RP recessed to the inside of the second air-gap159bby a pressure generated in bonding between the second buffer part BPb and the first vertical part VPa.

Each of the substrates110aand110bmay be a semiconductor substrate made of silicon, germanium, gallium arsenide, etc.

Each of the first insulating structures120aand120bmay extend to cover an integrated circuit formed in main regions which are not shown in the drawing, and include multi-layered insulating layers.

Each of the conductive pads130aand130bmay be connected to an integrated circuit disposed in main regions of a semiconductor chip corresponding thereto. The conductive pads130aand130bmay be formed of various conductive materials. In an embodiment, the conductive pads130aand130bmay include aluminum.

The second insulating structures140aand140bmay include various insulating materials. In an embodiment, the second insulating structures140aand140bmay include a silicon oxide layer.

Each of the first and second through electrodes TE2and TE3may include a barrier layer153aor153band a metal layer155aor155b. Each of the barrier layers153aand153bmay be formed in a single layer made of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, tungsten nitride, nickel, nickel nitride, etc., or be formed in a double layer including titanium and titanium nitride. Each of the metal layers155aand155bmay include various metals which can be bonded through low temperature plasma annealing. In an embodiment, each of the metal layers155aand155bmay include a metal which can be bonded at 300° C. or less. In an embodiment, each of the metal layers155aand155bmay include copper.

The metal layers155aand155bof the first and second through electrodes TE2and TE3may be bonded to each other. The metal layers155aand155bmay respectively surround the empty gaps159aand159b. In other words, the first empty gap150amay be buried in the metal layer155a, and the second empty gap159bmay be buried in the metal layer155b.

The barrier layers153aand153bmay be respectively formed on sidewalls of the metal layer155aand155b. That is, the barrier layers153aand153bmay be disposed between the metal layer155aand the sidewall insulating pattern151a, and between the metal layer155band the sidewall insulating pattern151b, respectively. The barrier layer153amay extend between the metal layer155aand the conductive pad130a, and between the metal layer155aand the second insulating structure140a. The barrier layer153bmay extend between the metal layer155band the conductive pad130b, and between the metal layer155band the second insulating structure140b.

In accordance with an above-described embodiment of the present disclosure, each of the through electrodes may include a contact surface in contact with a conductive pad, a first bonding surface adjacent to a second surface of a substrate, and a second bonding surface adjacent to a surface of a second insulating structure. For example, the first through electrode TE2may include a contact surface CS in contact with the conductive pad130a, a first bonding surface BS1adjacent to the second surface SU2aof the substrate110a, and a second bonding surface BS2adjacent to a surface of the second insulating structure140a. The second bonding surface BS2may be provided as the contact surface CS. The surface of the second insulating structure140amay be in contact with the second surface SU2bof the substrate110badjacent thereto.

FIG. 3is a block diagram illustrating a memory system300in accordance with an embodiment of the present disclosure.

Referring toFIG. 3, the memory system300may be applied to an electronic device, such as a computer, a digital camera, or a smart phone, to process data.

The memory system300may include a memory controller310and a stacked type memory device320.

The memory controller310may transmit data to the stacked type memory device320or provide a control signal to the stacked type memory device320, according to an access request from a host HOST. The memory controller310may detect an error from data read from the stacked type memory device320, and correct the detected error.

The stacked type memory device320may include two or more memory chips330_1to330_nstacked on each other. Each of the memory chips330_1to330_nmay include a volatile memory device or a nonvolatile memory device. For example, each of the memory chips330_1to330_nmay include a Dynamic Random Access Memory (DRAM), a Read Only Memory (ROM), a Mask ROM (MROM), a Programmable ROM (PROM), an Erasable Programmable ROM (EPROM), an Electrically Erasable Programmable ROM (EEPROM), a NAND flash memory, a NOR flash memory, a Phase change Random Access Memory (PRAM), a Magnetic RAM (MRAM), a Resistive RAM (RRAM), a Ferroelectric RAM (FRAM), etc.

The memory chips330_1to330_nmay be bonded to each other through the through electrodes described with reference toFIGS. 1and2.

FIG. 4is a sectional view illustrating a stacked type memory device400in accordance with an embodiment of the present disclosure.

The stacked type memory device400may include a memory cell array region AR1, a peripheral circuit region AR2, and a through via region AR3. The memory cell array region AR1and the peripheral circuit region AR2may be included a main region of the stacked type memory device400. The through via region AR3may be a region which provides a data transmission path and have through electrodes457aand457bbonded to each other, which are disposed therein.

The stacked type memory device400may include a first memory chip MCa and a second memory chip MCb, which overlap with each other. Each of the first memory chip MCa and the second memory chip MCb may include a semiconductor substrate410aor410b, a first insulating structure420aor420bformed on a surface of the semiconductor substrate410aor410b, and a second insulating structure440aor440bformed on a surface of the first insulating structure420aor420b.

Various impurities for a well structure and a channel may be doped in the semiconductor substrates410aand410b. Isolation layers411aand411bmay be buried in the semiconductor substrates410aand410b.

A memory cell and lines connected to the memory cell may be buried in each of the first insulating structures420aand420bin the memory cell array region AR1. Although a case where the memory cell includes a DRAM cell structure is exemplified inFIG. 4, the present disclosure is not limited thereto. Conductive pads431aand431bmay be buried in the second insulating structures440aand440b, respectively, in the memory cell array region AR1. The conductive pads431aand431bformed in the memory cell array region AR1may be connected to the memory cells via the lines buried in the first insulating structure420aand420b.

A peripheral circuit for controlling an operation of memory cells and lines connected to the peripheral circuit may be buried in each of the first insulating structures420aand420bin the peripheral circuit region AR2. The peripheral circuit may input data to a memory cell or read data from a memory cell, according to a control signal input from the outside (e.g., a memory controller). Conductive pads433aand433bmay be buried in the second insulating structures440aand440b, respectively, in the peripheral circuit region AR2. Each of the conductive pads433aand433bformed in the peripheral circuit region AR2may be connected to the peripheral circuit corresponding thereto via the lines buried in the first insulating structure420aor420bcorresponding thereto.

The first insulating structures420aand420band the second insulating structures440aand440b, which are described above, may extend to the through via region AR3. Through electrodes457aand457bused as a path through which the stacked type memory device400exchanged data or signals with the outside (e.g., the memory controller) of the stacked type memory device400may be formed in the through via region AR3. The through electrodes457aand457bmay be insulated from the substrates410aand410bthrough sidewall insulating patterns451aand451b, respectively, and be electrically connected to conductive pads430aand430bdisposed in the peripheral circuit region AR2, respectively.

The through electrodes457aand457bmay be formed in the same structure as each of the first through electrode TE2and the second through electrode TE3, which are described with reference toFIG. 2.

FIG. 5is a view illustrating a memory system500in accordance with an embodiment of the present disclosure.

Referring toFIG. 5, the memory system500may include high bandwidth memory device (HBM)520and a PROCESSOR530, which are mounted on an interposer510.

The HBM520may be connected to the processor530through the interposer510. The HBM520may include an interface chip521disposed on the interposer510and memory chips523stacked on the interface chip521. The memory chips523and the interface chip521may be electrically connected to each other through a bonding structure of through electrodes as described with reference toFIG. 1. Each of the through electrodes penetrating the memory chips523and the interface chip521may include an empty gap as described with reference toFIG. 2.

The interface chip521may provide an interface for communication between the processor530and the memory chips523.

The processor530may include a memory controller for controlling each HBM520. For example, the processor530may include a Graphic Processing Unit (GPU) or a Central Processing Unit (CPU), in which the memory control is built.

FIG. 6is a block diagram illustrating a memory system600in accordance with an embodiment of the present disclosure.

Referring toFIG. 6, the memory system600may include a memory controller610and a stacked type memory device620.

The memory controller610may control the stacked type memory device620, and include a Static Random Access Memory (SRAM)611, a Central Processing Unit (CPU)612, a host interface613, an error correction block614, and a memory interface615. The SRAM611may be used as a working memory of the CPU612. The CPU612may perform overall control operations for data exchange of the memory controller610. The host interface613is provided with a data exchange protocol of a host Host connected to the memory system600. The error correction block614detects an error included in data read from the stacked type memory device620, and corrects the detected error. The memory interface615performs interfacing with the stacked type memory device620. The memory controller610may further include a Read Only Memory (ROM) which stores code data for interfacing with the host Host, and the like.

The stacked type memory device620may include a plurality of memory packages621_1to621_m. Each of the memory packages621_1to621_mmay be formed in a structure in which a plurality of memory chips623are stacked. The memory chips623may be electrically connected to each other through a bonding structure of through electrodes as described with reference toFIG. 1. Each of the through electrodes penetrating the memory chips623may include an empty gap as described with reference toFIG. 2.

A plurality of channels CH1to CHm may be provided to the memory controller610and the stacked type memory device620. A memory package corresponding to each of the channels CH1to CHm may be electrically connected to the channel. Each of the channels CH1to CHm may be electrically connected to a memory package corresponding thereto through the through electrodes penetrating the memory chips623.

The above-described memory system600may be a memory card or a Solid State Drive (SSD), in which the stacked type memory device620and the memory controller610are coupled to each other. For example, when the memory system600is the SSD, the memory controller610may communicate with the outside (e.g., the host) through one of various interface protocols, such as a Universal Serial Bus (USB) protocol, a Multi-Media Card (MMC) protocol, a Peripheral Component Interconnection (PCI) protocol, a PCI-Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial-ATA (SATA) protocol, a Parallel-ATA (PATA) protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, and an Integrated Drive Electronics (IDE) protocol.

FIG. 7is a block diagram illustrating a computing system in accordance with an embodiment of the present disclosure.

Referring toFIG. 7, the computing system700may include a CPU720, a Random Access Memory (RAM)730, a user interface740, a modem750, and a memory system710, which are electrically connected to a system bus760. When the computing system700is a mobile device, a battery for supplying an operation voltage to the computing system700may be further included, and an application chip set, an image processor, a mobile DRAM, and the like may be further included.

The memory system710may include a memory controller711and a memory device712. The memory device712may be configured identically to the stacked type memory device620described with reference toFIG. 6. The memory controller711may be configured identically to the memory controller610described with reference toFIG. 6.

FIG. 8is a view illustrating a CMOS Image Sensor (CIS)800in accordance with an embodiment of the present disclosure.

Referring toFIG. 8, the CIS800may include a logic chip810and a pixel chip820stacked on the logic chip810.

The logic chip810may include a logic circuit for processing pixel signals from the pixel chip820. The logic circuit may include a row driver, a Correlated Double Sampler (CDS), an Analog-to-Digital Converter (ADC), a timing controller, and the like.

The pixel chip820may include a pixel array. The pixel array may generate an electrical pixel signal by converting incident light. The pixel array may include a plurality of unit pixels arranged in a matrix form. The pixel array may be driven by driving signals provided from the logic chip810.

The logic chip810and the pixel chip820may be penetrated through through electrodes bonded to each other, and be electrically connected to each other through the through electrodes. The through electrodes through which the logic chip810and the pixel chip820are penetrated may be configured identically to the first through electrode TE2and the second through electrode TE3, which are described with reference toFIG. 2.

FIGS. 9A, 9B, 9C, 9D, 9E, 9F, 9G, 9H, 9I, 9J, 10A, and 10Bare sectional views illustrating a manufacturing method of a stacked type semiconductor device in accordance with an embodiment of the present disclosure.FIGS. 9A, 9B, 9C, 9D, 9E, 9F, 9G, 9H, 9I, 9J, 10A, and 10Bare sectional views taken along a through via region of the stacked type semiconductor device.

FIGS. 9A to 9Jare sectional views illustrating an embodiment of a manufacturing method of a semiconductor chip.

Referring toFIG. 9A, a first insulating structure920may be formed on a first surface910S1of a preliminary substrate910A having the first surface910S1and a second surface910S2opposite to the first surface910S1. Although not shown in the drawing, elements and lines for at least one of a memory cell array, a pixel array, a peripheral circuit, and a logic circuit for the semiconductor chip may be formed in a main region (not shown) of the preliminary substrate910A.

The preliminary substrate910A may be a semiconductor substrate made of silicon, germanium, gallium arsenide, etc. Various impurities for a well structure, a channel region, etc. may be doped in the preliminary substrate910A.

The first insulating structure920may extend to cover the main region (not shown) of the preliminary substrate910A. The first insulating structure920may include two or more insulating layers stacked on the preliminary substrate910A.

Subsequently, a conductive pad930may be formed on the first insulating structure920. Subsequently, a second insulating structure940may be formed on the first insulating structure920. The second insulating structure940may be formed to cover the conductive pad930.

Subsequently, the mask pattern941may be formed on the second insulating structure940. The mask pattern941may be patterned by using a photolithography process to have an opening overlapping with the conductive pad930.

A via hole943may be formed by sequentially etching the second insulating structure940, the conductive pad930, and the first insulating structure920through an etching process using the above-described mask pattern941as an etch barrier. The via hole943may be formed to expose the preliminary substrate910A. The via hole943may be formed to a depth to which the via hole943does not penetrate the preliminary substrate910A. In an embodiment, the via hole943may be formed to a depth corresponding to the thickness of a stack structure including the second insulating structure940, the conductive pad930, and the first insulating structure920. A width of the via hole943may be formed narrower than that of the conductive pad930.

Referring toFIG. 9B, after the via hole943is formed, the mask pattern941shown inFIG. 9Amay be removed. Subsequently, a protective layer945may be formed on a sidewall of the via hole943. The protective layer945may be formed of a material having an etching selectivity with respect to the preliminary substrate910A. In an embodiment, the protective layer945may include oxide. The protective layer945may be etched such that the preliminary substrate910A can be exposed through a bottom surface of the via hole943.

Referring toFIG. 9C, a buffer hole947may be formed by etching the preliminary substrate910A through the via hole943. While the preliminary substrate910A is being etched, the first insulating structure920, the conductive pad930, and the second insulating structure940may be protected by the protective layer945shown inFIG. 9B. The protective layer945may be removed after the buffer hole947is formed.

The etching process for forming the buffer hole947may be performed through an isotropic etching process. Accordingly, a sidewall of the buffer hole947may have a curvature greater than that of a sidewall of the via hole943in a direction in which the preliminary substrate910A and the first insulating structure920are stacked. In an embodiment, the buffer hole947may be formed in a circular shape or an elliptical shape.

The buffer hole947may extend to the inside of the preliminary substrate910A from the via hole943. A bottom surface of the buffer hole947may be spaced apart from the second surface91052of the preliminary substrate910A. In other words, the buffer hole947may be formed to a depth to which the buffer hole947does not completely penetrate the preliminary substrate910A.

Referring toFIG. 9D, an insulating layer951L may be formed on a surface of each of the buffer hole947and the via hole943. The insulating layer951L may extend onto a sidewall of the first insulating structure920, which defines the sidewall of the via hole943, a sidewall of the conductive pad930, and a sidewall of the second insulating structure940, and extend onto a top surface of the second insulating structure940. The insulating layer951L may include an oxide layer.

Referring toFIG. 9E, a sacrificial material952may be formed on the insulating layer951L. The sacrificial material952may be formed to fill the buffer hole947and the via hole943, which are shown inFIG. 9D, by using a spin coating process. Subsequently, an upper end of the via hole943shown inFIG. 9Dmay be opened by removing a portion of the sacrificial material952. Hereinafter, the upper end of the via hole943, which is opened when the portion of the sacrificial material952is removed, is defined as an opening OP.

The etching process of the sacrificial material952for forming the opening OP may include an etching process such as an etch-back process. The sacrificial material952may be formed of a material having an etching selectivity with respect to the second insulating structure940and the conductive pad930. In an embodiment, the sacrificial material952may include carbon, a photoresist, or an organic compound.

The opening OP may extend to a level at which the sidewall of the conductive pad930is disposed. In an embodiment, a top surface of the sacrificial material952, which defines a bottom surface of the opening OP, may correspond to a level at which a top surface of the insulating structure920is disposed.

Referring toFIG. 9F, a sidewall insulating layer951is formed by etching an exposed portion of the insulating layer951L shown inFIG. 9E. The sidewall insulating layer951may remain in a state in which the sidewall insulating layer951extends onto the sidewall of the first insulating structure920from a surface of the buffer hole947.

Referring toFIG. 9G, the sidewall insulating layer951may be exposed by selectively removing the sacrificial material952shown inFIG. 9F. Subsequently, a barrier layer953L and a metal layer955L may be sequentially formed on the sidewall insulating layer951.

The barrier layer953L may extend onto the sidewall of the conductive pad930from the sidewall insulating layer951. The barrier layer953L may be connected to the conductive pad930exposed on the sidewall insulating layer951. The barrier layer953L may be formed in a single layer including titanium, titanium nitride, tantalum, tantalum nitride, tungsten nitride, nickel, nickel boride, etc., or be formed in a double layer including titanium and titanium nitride.

The metal layer955L may be formed through a deposition process such as electroplating. In an embodiment, the metal layer955L may include copper. The metal layer955L may be formed on the barrier layer953L to fill the buffer hole947and the via hole943. An air gap959may be buried in the buffer hole947formed to a depth deeper than that of the via hole943. When a width of the buffer hole947is formed wider than that of the via hole943, the empty gap959can be easily buried in the buffer hole947. The metal layer955L may completely fill the via hole943such that the empty gap959can be sealed in the buffer hole947.

Referring toFIG. 9H, a portion of each of the metal layer955L and the barrier layer953L, which are shown inFIG. 9G, may be removed through a planarization process such that the top surface of the second insulating structure940is exposed.

Referring toFIG. 9I, a portion of the preliminary substrate910A may be removed from the second surface910S2of the preliminary substrate910A shown inFIG. 9Hsuch that an end portion of the sidewall insulating layer951is exposed. Accordingly, the thickness of the preliminary substrate910A can be decreased. Hereinafter, the preliminary substrate having the decreased thickness is defined as a bonding substrate910B. The end portion of the sidewall insulating layer951may be exposed in a state in which the end portion farther protrudes than the bonding substrate910B.

Referring toFIG. 9J, the exposed portion of the sidewall insulating layer951shown inFIG. 9Imay be removed. Accordingly, a sidewall insulating pattern951P used as a target may be formed.

Subsequently, a barrier pattern953P may be formed by removing a portion of the barrier layer such that the metal layer955is exposed. The barrier pattern953P and the metal layer955may constitute a through electrode957. The exposed portion of the metal layer955may constitute a protrusion part PP farther protruding than the bonding substrate910B.

The through electrode957formed through the processes described with reference toFIGS. 9A to 9Jmay include a buffer part P1filling the buffer hole947in the bonding substrate910B and a vertical part P2extending from the buffer part P1. The vertical part P2may be formed on the sidewall insulating pattern951P to fill the via hole943penetrating the first insulating structure920, the conductive pattern930, and the second insulating structure940, and be in contact with the conductive pad930.

FIGS. 10A and 10Bare sectional views illustrating a process of bonding a first semiconductor chip970and a second semiconductor chip980. The bonding process between the first semiconductor chip970and the second semiconductor chip980may be performed through a bonding process between wafers, be performed through a bonding process between dies, or be performed through a bonding process between a wafer and a die.

Referring toFIG. 10A, the first semiconductor chip970and the second semiconductor chip989may be respectively penetrated by a first through electrode957aand a second through electrode957b, which are manufactured through the processes described with reference toFIGS. 9A to 9J. A first empty gap959amay be buried in the first through electrode957a, and a second empty gap959bmay be buried in the second through electrode957b.

According to the processes described with reference toFIGS. 9A to 9J, the first through electrode957amay include a first buffer part P1aand a first vertical part P2aextending from the first buffer part P1a. The first buffer part P1amay be disposed in a first buffer hole947apenetrating a first bonding substrate910Ba of the first semiconductor chip970, and surround the first empty gap959a. The first vertical part P2amay extend to penetrate a first insulating structure920a, a first conductive pad930a, and a second insulating structure940aof the first semiconductor chip970. A sidewall of the first buffer part P1a, which faces the first bonding substrate910Ba, and a sidewall of the first vertical part P2a, which faces the first insulating structure920a, may be surrounded by a first sidewall insulating pattern951Pa. The first vertical part P2amay farther protrude than the first sidewall insulating pattern951Pa, and be in contact with the first conductive pad930aof the first semiconductor chip970.

According to the processes described with reference toFIGS. 9A to 9J, the second through electrode957bmay include a second buffer part P1band a second vertical part P2bextending from the second buffer part P1b. The second buffer part P1bmay be disposed in a second buffer hole947bpenetrating a second bonding substrate910Bb of the second semiconductor chip980, and surround the second air gap959b. The second vertical part P2bmay extend to penetrate a first insulating structure920b, a second conductive pad930b, and a second insulating structure940bof the second semiconductor chip980. A sidewall of the second buffer part P1b, which faces the second bonding substrate910Bb, and a sidewall of the second vertical part P2b, which faces the first insulating structure920b, may be surrounded by a second sidewall insulating pattern951Pb. The second vertical part P2bmay farther protrude than the second sidewall insulating pattern951Pb, and be in contact with the second conductive pad930bof the second semiconductor chip980.

The first buffer part P1amay farther protrude than the first bonding substrate910Ba, and the second buffer part P1bmay farther protrude than the second bonding substrate910Bb.

The first semiconductor chip970may be aligned on the second semiconductor chip980such that the first vertical part P2aand the second buffer part P1bface each other.

Referring toFIG. 10B, the first through electrode957aof the first semiconductor chip970may be bonded to the second through electrode957bof the second semiconductor chip980. The first through electrode957aand the second through electrode957bmay be bonded to each other by bonding the first vertical part P2ato the second buffer part P1b.

The bonding process may include a plasma annealing process. The plasma annealing process may be performed at a low temperature of 300° C. or less. During the plasma annealing process, the first through electrode957aand the second through electrode957bmay be bonded to each other by coherence between metal layers of the first through electrode957aand the second through electrode957b.

The metal layer of each of the first through electrode957aand the second through electrode957bmay thermally expand due to heat generated during the above-described bonding process, and repulsive power may occur between the first through electrode957aand the second through electrode957b. A protrusion part of the second through electrode957bmay be recessed to the inside of the second empty gap959bshown inFIG. 10Aby the repulsive power generated between the first through electrode957aand the second through electrode957band the coherence between the metal layers of the first through electrode957aand the second through electrode957b. Accordingly, the shape of the second empty gap959bshown inFIG. 10Amay be deformed in the bonding process as shown inFIG. 10B, and remain as a dented empty gap959b′ having a curvature deviation greater than that of the first empty gap959a. In an embodiment, the dented empty gap959b′ may have a concave portion and a convex portion.

As described above, in accordance with the embodiment of the present disclosure, the repulsive power generated between the metal layers at a bonding interface during the bonding process can be cancelled by a buffering action of the empty gap. Thus, the stability of the bonding structure between the semiconductor chips can be improved.

Although the structure in which the first semiconductor chip970and the second semiconductor chip980are bonded to each other is exemplified in the above, the number of semiconductor chips bonded to each other in the present disclosure is not limited thereto.

In accordance with the present disclosure, repulsive power between through electrodes due to thermal expansion of the through electrodes during a bonding process can be cancelled through empty gaps formed in the through electrodes. Accordingly, the stability of a bonding structure can be improved.