Electro-optic device, electronic device, and method of manufacturing electro-optic device

A liquid crystal device as the electro-optic device according to the application example includes a transistor, a pixel electrode which is provided corresponding to the transistor, and a capacitive wiring of which a part is provided so as to face the pixel electrode between an element substrate and the pixel electrode, and configures a retention capacitor through the pixel electrode and a dielectric layer in which the capacitive wiring is formed so as to be embedded in an insulating film which is provided between the element substrate and the pixel electrode, the surface thereof on the pixel electrode side is planarized along with an insulating film.

BACKGROUND

1. Technical Field

The present invention relates to an electro-optic device, an electronic device, and a manufacturing method of electro-optic device.

2. Related Art

As the above described electro-optic device, for example, there is an active matrix liquid crystal display in which a thin film transistor (TFT) is used as a switching element for pixels.

In this liquid crystal display, a pixel circuit which includes a thin film transistor, and a variety of wirings, electric capacitors, or the like, which are connected to the thin film transistor, or a peripheral circuit thereof is formed on a substrate.

As a configuration of the above pixel circuit, a liquid crystal display is disclosed in JP-A-7-128685, in which a light shielding black matrix is arranged between a pixel electrode and a source line layer through an interlayer insulating film on an active matrix substrate, shields the source line by applying a specific potential, and forms a storage capacitor with the pixel electrode.

According to the liquid crystal display, it is possible to reduce crosstalk due to the potential of the source line, to have a large pixel retention capacitor, and to realize a high aperture ratio, by shielding the source line using the black matrix.

However, in the liquid crystal display in JP-A-7-128685, a step occurs at a portion which is overlapped with the black matrix in the pixel electrode, that is, a portion where the pixel retention capacitor is configured, and there is a problem in that an uneven display may occur by a disorder of an orientation of the liquid crystal molecules in the step portion.

SUMMARY

Application Example 1

An electro-optic device according to the application example includes, a substrate; a transistor; a pixel electrode which is provided to correspond to the transistor; and a capacitive wiring of which a part is provided so as to face the pixel electrode between the substrate and the pixel electrode, and configures a retention capacitor through the pixel electrode and a dielectric layer, in which the capacitive wiring is embedded in an insulating film which is provided between the substrate and the pixel electrode, and of which a surface on the pixel electrode side is planarized along with the insulating film.

According to this configuration, the retention capacitor is configured at a portion where the capacitive wiring and the pixel electrode are overlapped with each other through the dielectric layer. In addition, since in the portion where the dielectric layer is provided are, the surfaces of the capacitive wiring and the insulating film are planarized, unevenness does not occur on the surface of the pixel electrode which is provided through the dielectric layer. That is, it is possible to provide an electro-optic device in which the retention capacitor is configured using the pixel electrode while securing an aperture ratio of pixels, the display unevenness is reduced compared to the related art, and an excellent display quality is secured.

Application Example 2

In the electro-optic device according to the application example, the capacitive wiring may include a first conductive film, and a second conductive film which protects the first conductive film by covering the first conductive film, and the surface of the second conductive film and the surface of the insulating film be on the same plane as each other. According to this, since the first conductive film is protected by the second conductive film, it is possible to configure the retention capacitor with no electrical defects, since the first conductive film is not damaged in the planarizing process of the surface of the capacitive wiring and the surface of the insulating film, and at least a conductivity of the first conductive film is secured.

Application Example 3

In the electro-optic device according to the application example, the pixel electrode may be arranged by crossing the two capacitive wirings which are adjacent and parallel to each other.

Due to this, it is possible to make the electric capacity large in the retention capacitor compared to a case where the pixel electrode is overlapped with one capacitive wiring. In other words, it is possible to easily secure a desired electric capacity.

Application Example 4

An electronic device according to the application example may include the electro-optic device in the application example.

In this manner, it is possible to provide an electronic device in which display unevenness is reduced compared to the related art, and an excellent display quality is secured.

Application Example 5

A method of manufacturing an electro-optic device includes, forming a capacitive wiring layer on a substrate; forming an insulating film by covering the capacitive wiring layer; exposing the capacitive wiring layer from the insulating film by polishing the insulating film, and planarizing the surfaces of the exposed capacitive wiring layer and the insulating film; forming a dielectric layer which covers the exposed capacitive wiring layer and the insulating film; and forming a pixel electrode so that a part of the pixel electrode is overlapped with the capacitive wiring layer through the dielectric layer.

According to the method, the pixel electrode is formed so that a part thereof is overlapped planarly with the capacitive wiring layer, on the dielectric layer which covers the capacitive wiring layer and the insulating film of which surfaces are planarized. Accordingly, unevenness does not occur on the surface of the formed pixel electrode. That is, it is possible to manufacture an electro-optic device in which the retention capacitor is formed using the pixel electrode while maintaining the aperture ratio of pixels, the display unevenness is reduced compared to the related art, and an excellent display quality is secured.

Application Example 6

In a manufacturing method of an electro-optic device according to the application example, the forming of the capacitive wiring layer may include, forming a first conductive film; forming a second conductive film which covers and protects the first conductive film; and forming the capacitive wiring layer by patterning the first conductive film and the second conductive film.

According to the method, since the first conductive film is protected by the second conductive film, it is possible to prevent the first conductive film from being damaged in the process of planarizing the insulating film by polishing thereof. That is, it is possible to form the retention capacitor with no electrical defects by securing at least a conductivity of the first conductive film.

Application Example 7

Another manufacturing method of the electro-optic device according to the application example includes, forming an insulating film on a substrate; forming a groove in the insulating film; filling the groove, and forming a capacitive wiring layer by covering the insulating film; exposing the capacitive wiring layer from the insulating film by polishing the capacitive wiring layer, in the groove, and planarizing surfaces of the exposed capacitive wiring layer and the insulating film; forming a dielectric layer which covers the exposed capacitive wiring layer and the insulating film; and forming a pixel electrode so that a part of the pixel electrode is overlapped with the capacitive wiring layer through the dielectric layer.

According to the method, the capacitive wiring layer is formed in the groove which is formed in advance in the insulating film. Accordingly, it is possible to separate the capacitive wiring layer and the insulating film from each other, and to expose each of them earlier compared to a case where the insulating film is polished. In addition, since the groove is embedded by the capacitive wiring layer, it is possible to prevent the capacitive wiring layer from being excessively polished in order to planarize the surfaces of the capacitive wiring layer and the insulating film.

Application Example 8

In the manufacturing method of an electro-optic device according to the application example, forming the capacitive wiring layer may include, forming a first conductive film; and forming a second conductive film which protects the first conductive film by covering the first conductive film.

According to the method, since the first conductive film is protected by the second conductive film, it is possible to prevent the first conductive film from being damaged when polishing the capacitive wiring layer. That is, it is possible to form a retention capacitor with no electrical defects by securing the conductivity of at least the first conductive film.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

Hereinafter, embodiments in which the invention is embodied will be described according to drawings. In addition, drawings to be used are displayed by being appropriately enlarged or reduced in size so that portions to be described become a recognizable state.

In addition, in the embodiments to be described later, for example, when it is described as “on a substrate”, it may be a case of being arranged so as to come into contact with the upper part of the substrate, a case of being arranged on the substrate through other constructs, or may be a case where a part is arranged so as to come into contact with the upper part of the substrate, and a part is arranged through other constructs.

First Embodiment

According to the embodiment, an active matrix liquid crystal device as an electro-optic device which includes a thin film transistor (TFT) as a switching element of the pixel will be described as an example. The liquid crystal device is able to be preferably used, for example, as an optical modulator (liquid crystal light valve) of a projection-type display device (liquid crystal projector) to be described later.

Liquid Crystal Device

First, a liquid crystal device as an electro-optic device according to the embodiment will be described with reference toFIGS. 1A,1B, and2.FIG. 1Ais a schematic plan view which shows a configuration of the liquid crystal device,FIG. 1Bis a schematic cross-sectional view which is taken along line IB-IB inFIG. 1A, andFIG. 2is an equivalent circuit diagram which shows an electrical configuration of the liquid crystal device.

As shown inFIGS. 1A and 1B, the liquid crystal device100according to the embodiment includes an element substrate10and an opposing substrate20which is arranged opposite thereto, and a liquid crystal layer50which is pinched by the pair of substrates. As the material of the element substrate10and the opposing substrate20, a transparent glass substrate, for example, such as quartz is used.

The element substrate10is larger than the opposing substrate20, both the substrates are bonded to each other via a sealing material40which is arranged in a frame shape, and liquid crystal having a positive or negative dielectric anisotropy is filled into the gap thereof, thereby configuring a liquid crystal layer50. In the sealing material40, an adhesive, for example, thermosetting resin, UV-curable epoxy resin, or the like is used. A spacer (not shown) for maintaining a uniform gap between the pair of substrates is mixed in the sealing material40.

On the inside of the sealing material40which is arranged in the frame shape, a shielding film21which has the same frame shape is provided. The shielding film21is formed of, for example, metal with light shielding properties, or metallic oxide, and the inside of the shielding film21is a display area E having a plurality of pixels P. In addition, it is not shown inFIGS. 1A and 1B, a light shielding unit for planarly separating the plurality of pixels P is provided in the display area E, as well.

A data line driving circuit101is provided between one side portion of the element substrate10and the sealing material40which is located along one side portion of the element substrate10. In addition, a checking circuit103is provided inside the sealing material40which is located along another one side portion facing the one side portion. In addition, a scanning line driving circuit102is provided inside the sealing material40which goes along other two side portions which are orthogonal to the first side portion, and are facing each other. A plurality of wirings105is provided, which connects two scanning line driving circuit102to each other, inside the sealing material40on other one side portion facing the one side portion. Wirings which are connected to the data line driving circuit101and the scanning line driving circuit102are connected to a plurality of external connection terminals104which is arranged along the first side portion.

Hereinafter, description will be made in which a direction which goes along the one side portion is set as the X direction, and a direction which is orthogonal to the one side portion and goes along other two side portions facing each other is set to the Y direction.

In addition, an arrangement of the checking circuit103is not limited thereto, and the checking circuit may be provided at a position which goes along the inside of the sealing material40between the data line sealing material101and the display area E.

As shown inFIG. 1B, on the surface of the liquid crystal layer50side of the element substrate10, a pixel electrode15having light permeability and thin film transistor (TFT)30as the switching element which are provided for each pixel, a signal wiring, and an orientation film18which covers these are formed.

In addition, a light shielding structure is adopted, which prevents a state in which light is input to the semiconductor layer in TFT30, and a switching operation becomes unstable. The light shielding structure will be described later.

On a surface of the liquid crystal layer50of the opposing substrate20, a shielding film21, an interlayer film layer22which is formed so as to cover the shielding film21, a common electrode23which is provided so as to cover the interlayer film layer22, and the orientation film24for covering the common electrode23are provided.

As shown inFIG. 1A, the shielding film21is provided in a frame shape at a position where it is overlapped with a data line driving circuit101, a scanning line driving circuit102, or a checking circuit103planarly. Due to this, light which is input from the opposing substrate20side is shielded, and it plays a role of preventing a malfunction due to the light in the peripheral circuits including these driving circuits. In addition, unnecessary stray light is shielded so as no to be incident on the display area E, and a high contrast is secured in the display of the display area E.

The interlayer film layer22is formed of an inorganic material, for example, such as silicon oxide, and is provided so as to cover the shielding film21, having light transparency. As a formation method of such an interlayer film layer22, for example, there is a formation method using a plasma CVD technique.

The common electrode23is formed of, for example, a transparent conductive film such as ITO, covers the interlayer film layer22, and as shown inFIG. 1A, is electrically connected to a wiring on the element substrate10side by a vertical conduction unit106which is provided four corners of the opposing substrate20.

An orientation film18which covers the pixel electrode15, and an orientation film24which covers the common electrode23are selected on the basis of an optical design of the liquid crystal device100. For example, there is an orientation film which is subject to substantially horizontal orientation processing with respect to liquid crystal molecules, by forming a film using an organic material such as polyimide, and rubbing the surface thereof, or an orientation film which is formed by a vapor growth method using an inorganic material such as SiOx (silicon oxide), and is subject to substantially vertical orientation with respect to the liquid crystal molecules.

As shown inFIG. 2, the liquid crystal device100includes at least a plurality of scanning lines3aas signal lines which are insulated from each other in the display area E and a plurality of data lines6a, and a capacitive wiring3bwhich is arranged so as to be parallel along the data line6a.

A direction in which the scanning line3ais extended is the X direction, and a direction in which the data line6ais extended is the Y direction.

The pixel electrode15, the TFT30, and two retention capacitors C1and C2are provided in a region of the scanning line3a, the data line6a, the capacitive wiring3b, and a region which is separated by these signal lines, and these configure the pixel circuit of the pixel P.

The scanning line3ais electrically connected to a gate of the TFT30, and the data line6ais electrically connected to a source of the TFT30. The pixel electrode15is electrically connected to a drain of the TFT30.

The data line6ais connected to the data line driving circuit101(refer toFIGS. 1A and 1B), and supplies pixel signals D1, D2, . . . , Dn which are supplied from the data line driving circuit101to the pixel P. The scanning line3ais connected to the scanning line driving circuit102(refer toFIGS. 1A and 1B), and supplies main scanning signals SC1, SC2, . . . , SCm which are supplied from the scanning line driving circuit102to each pixel P. The pixel signals D1to Dn which are supplied to the data line6afrom the data line driving circuit101may be sequentially supplied in this order, and may be supplied in a group with respect to the fellows of the plurality of data lines6awhich are adjacent to each other. The scanning line driving circuit102supplies the main scanning signals SC1to SCm with respect to the scanning line3ain a pulse, and linearly sequentially at a predetermined timing.

The liquid crystal device100has a configuration in which the image signals D1to Dn which are supplied from the data line6aare written in the pixel electrode15at a predetermined timing, when the TFT30as the switching element is subject to an on state for a predetermined period due to an input of the main scanning signals SC1to SCm. In addition, the image signals D1to Dn of a predetermined level which are written in the liquid crystal layer50through the pixel electrode15is held for a certain period between the pixel electrode15and the common electrode23which is arranged opposite thereto interposing the liquid crystal layer50.

Since the held image signals D1to Dn are prevented from being leaked, the retention capacitors C1and C2are connected in parallel to the liquid crystal capacitance which is formed between the pixel electrode15and the common electrode23. The retention capacitors C1and C2are provided between the drain of the TFT30and the capacitive wiring3b. The retention capacitors C1and C2are configured such that a part of the pixel electrode15is overlapped with the two capacitive wirings3bwhich are adjacent and parallel to each other through the dielectric layer, though it will be described in detail later. A retention capacitor C1is configured between one of the capacitive wirings3band the pixel electrode15, and a retention capacitor C2is configured between the other capacitive wirings3band the pixel electrode15. The capacitive wiring3bis connected to a fixed potential.

In addition, the checking circuit103which is shown inFIG. 1Ais connected with the data line6a, and it is configured such that a defect behavior or the like of the liquid crystal device100is checked in a manufacturing process of the liquid crystal device100, however, it is omitted in the equivalent circuit inFIG. 2. In addition, the checking circuit103may include a sampling circuit which performs sampling of the image signal and supplies the image signal to the data line6a, and a precharge circuit which previously supplies a precharge signal of a predetermined voltage level to the data line6a.

Such a liquid crystal device100is a transmission type, and adopts an optical design of a normally white mode in which the pixel P becomes a bright display when the pixel P is not driven, or a normally black mode in which the pixel P becomes a black display when the pixel P is driven. A polarizing element is arranged and used according to the optical design in each of the light input side and the light output side.

Subsequently, a planar arrangement and a structure of the pixel P will be described with reference toFIGS. 3 to 6.FIG. 3is schematic plan view which shows the arrangement of the pixel in the liquid crystal device according to the first embodiment, andFIGS. 4A and 4Bare schematic plan views which show a configuration of pixels in the liquid crystal device according to the first embodiment,FIG. 5is a schematic cross-sectional view which shows a structure of pixels taken along line V-V inFIG. 4A, andFIG. 6is a schematic cross-sectional view which shows the structure of pixels taken along line VI-VI inFIG. 4B.

As shown inFIG. 3, the pixel P in the liquid crystal device100has an aperture area of, for example, substantially rectangular in a plane. The aperture area is surrounded by a light shielding non-aperture area which extends in the X direction and Y direction, and is provided in a lattice shape.

The scanning line3ashown inFIG. 2is provided in the non-aperture area which extends in the X direction. A conductive member with a light shielding property is used in the scanning line3a, and at least a part of the non-aperture area is configured by the scanning line3a.

Similarly, the data line6aand the capacitive wiring3bshown inFIG. 2are provided in the non-aperture area which extends in the Y direction. The conductive member with the light shielding property is used in the data line6aand the capacitive wiring3b, as well, and at least a part of the non-aperture area is configured by the data line6aand the capacitive wiring3b.

It is possible to configure the non-aperture area not only by the signal lines which are provided on the element substrate10side, but by the shielding film21which is patterned on the opposing substrate20side.

The TFT30shown inFIG. 2is provided in the vicinity of a crossing of the non-aperture area. By providing the TFT30in the vicinity of the crossing of the non-aperture area with the light shielding property, it is possible to prevent a light malfunction of the TFT30, and to secure the aperture ratio in the aperture area. The detailed structure of the pixel P will be described later, however, the width of the non-aperture area in the vicinity of the crossing becomes large compared to other portions, since the TFT30is provided in the vicinity of the crossing.

The pixel electrode15is arranged so that an outer edge portion thereof is overlapped with respect to the non-aperture area which is provided in the lattice shape.

As shown inFIG. 4A, the TFT30of the pixel P is provided at a crossing of the scanning line3aand the data line6a. The TFT30includes a semiconductor layer30aof an LDD (Lightly Doped Drain) structure having the source region30s, the drain region30d, the channel region30c, a junction region30ewhich is provided between the source region30sand the channel region30c, and a junction region30fwhich is provided between the channel region30cand the drain region30d. The semiconductor layer30ais arranged so as to pass through the crossing and to be overlapped with the scanning line3a.

The scanning line3ahas a rectangular extension portion which is extended in the X and Y directions at the crossing with the data line6a, when planarly viewed. There is provided a gate electrode30gof a bent shape having an opening which is overlapped with the extension portion in the plane, and is not overlapped with the junction region30fand the drain region30d.

A portion of the gate electrode30gwhich is extended in the Y direction is overlapped with the channel region30cin the plane. In addition, the gate electrode30gis extended in the X direction by being bent from a portion which is overlapped with the channel region30c, and of which portions facing each other are electrically connected to the scanning line3a, respectively, by contact holes CNT5and CNT6which are provided by interposing the extension portion of the scanning line3atherebetween.

The contact holes CNT5and CNT6are long rectangular shapes (rectangle) in the X direction when planarly viewed, and are provided at both sides so as to pinch the junction region30falong the channel region30cand the junction region30fof the semiconductor layer30a.

The data line6ais extended in the Y direction, similarly, has the rectangular extension portion at the crossing with the scanning line3a, when planarly viewed, and is electrically connected to the source region30sby a contact hole CNT1which is provided at a portion protruding in the X direction from the extension portion. The portion including the contact hole CNT1becomes a source electrode31(refer toFIG. 5). On the other hand, two contact holes CNT2and CNT3which are overlapped with each other and bonded are provided at the end portion of the drain region30d, and the portion including the contact hole CNT2becomes a drain electrode32(refer toFIG. 5).

A contact hole CNT4is provided in the vicinity of the contact holes CNT2(CNT3). The contact holes CNT3and CNT4are electrically connected to each other by a relay layer3cwhich is provided so as to be overlapped therewith.

The outer edge portion of the pixel electrode15is provided so as to be overlapped with respect to the scanning line3aor the data line6a, and is connected to the contact hole CNT4which is provided at a position overlapped with the scanning line3a, in the embodiment. That is, the pixel electrode15is electrically connected to the drain electrode32through the contact hole CNT4, the relay layer3c, and the contact holes CNT2and CNT3.

As shown inFIG. 4B, the capacitive wiring3bis overlapped with the data line6ain the plane and is extended in the Y direction, and similarly, has the rectangular extension portion at a position corresponding to the crossing of the scanning line3aand data line6a. The pixel electrode15is provided so as to cross two capacitive wirings3bwhich are parallel to each other, in which a portion which is planarly overlapped with one capacitive wiring3b(shaded portion) functions as a retention capacitor C1, and a portion which is planarly overlapped with the other capacitive wiring3b(shaded portion) functions as a retention capacitor C2.

The relay layer3cwhich is rectangular when planarly viewed, and is formed on the same wiring layer as that of the capacitive wiring3bis provided between the two capacitive wirings3b. As described above, the contact hole CNT4is provided so as to be overlapped with the relay layer3c, and is connected to the pixel electrode15.

In addition, similarly, the pixel electrode15is provided in other pixels P, as well, and the retention capacitors C1and C2are configured, though it is not shown inFIG. 4B.

Subsequently, the structure of the pixel P will be more specifically described with reference toFIGS. 5 and 6.

As shown inFIG. 5, first, the scanning line3ais formed on the element substrate10. The scanning line3ais formed of, for example, simple metal which includes at least one of metal of Al, Ti, Cr, W, Ta, Mo, or the like, an alloy, metal silicide, polyimide, nitride, or a lamination of these, and has a light shielding property.

The semiconductor layer30aof an islet is formed on the base insulating film11a, by forming the base insulating film11awhich is formed of, for example, silicon oxide so as to cover the scanning line3a. The semiconductor layer30ais formed of, for example, polycrystalline silicon film, is filled with impurity ion, and forms an LDD structure including the above described source region30s, junction region30e, channel region30c, junction region30f, and the drain region30d.

A first insulating film (gate insulating film)11bis formed so as to cover the semiconductor layer30a. Further, the gate electrode30gis formed at a position facing the channel region30c, by pinching the first insulating film11b.

A second insulating film11cis formed so as to cover the gate electrode30gand the first insulating film11b, and the two contact holes CNT1and CNT2which pass through the first insulating film11band the second insulating film11care formed at a position of being overlapped with respective end portions of the semiconductor layer30a. In addition, the source electrode31and the data line6awhich is connected to the source region30sthrough the contact hole CNT1is formed, by embedding the two contact holes CNT1and CNT2, forming a conductive film using a conductive material with light shielding property such as Al (aluminum) so as to cover the second insulating film11c, and by patterning this. At the same time, a drain electrode32which is connected to a drain range30dthrough the contact hole CNT2is formed. That is, the source electrode31, the data line6a, and the drain electrode32are patterned in the same conductive layer.

An interlayer insulating film12is formed so as to cover the data line6a, the drain electrode32, and the second insulating film11c. The interlayer insulating film12is formed of, for example, silicon oxide, or silicon nitride, and is subject to planarizing processing for planarizing unevenness on a surface which occurs when covering a region where the TFT30is provided. As a method of the planarizing processing, for example, there is Chemical Mechanical Polishing (CMP) processing, spin-coating processing, or the like.

A conductive film with the light shielding property is configured by forming the contact hole CNT3which passes through the interlayer insulating film12at a position of being overlapped with the drain electrode32, and by embedding the contact hole CNT3. The relay layer3cwhich is connected to the drain electrode32through the capacitive wiring3band the contact hole CNT3is formed by patterning the conductive film. It will be more specifically described later, however, the capacitive wiring3band the relay layer3care formed so as to be embedded in the insulating film13, and a surface thereof is planarized so as to be on the same plane as that of the insulating film13which covers the interlayer insulating film12.

In addition, in the above described conductive film with the light shielding property which configures the capacitive wiring3b, or the relay layer3c, a lamination of the first conductive film which is formed of Al (aluminum), and the second conductive film, which is formed of TiN (titanium nitride), or the like, which protects the first conductive film is used.

Subsequently, a dielectric film is formed so as to cover the capacitive wiring3b, or the relay layer3c, and the insulating film13, and patterning is performed so as to remove a portion of the dielectric film which is overlapped with the contact hole CNT4connected to the pixel electrode15, thereby forming a dielectric layer14. As the dielectric film, for example, a single layer film such as a silicon nitride film, oxide hafnium (HfO2), alumina (Al2O3), tantalum oxide (Ta2O5), or a multilayer film in which at least two of these single layer films are laminated may be used.

Subsequently, a transparent conductive film such as ITO, or IZO is formed so as to cover a dielectric layer14, and the pixel electrode15which is connected to the relay layer3cis formed by patterning the transparent conductive film through the contact hole CNT4.

As shown inFIG. 6, the pixel electrode15is patterned so that the outer edge portion thereof is overlapped with the two capacitive wirings3bwhich are adjacent and parallel to each other on the dielectric layer14. The portion of the pixel electrode15which is overlapped with the two capacitive wirings3bthrough the dielectric layer14becomes the retention capacitors C1and C2. Since the surfaces of the capacitive wiring3band the insulating film13are on the same plane, the dielectric layer14which covers these is formed in the flat state, and the surface of the pixel electrode15which is formed on the dielectric layer14is also flat.

In such a wiring structure of the element substrate10, a fixed potential is applied to the capacitive wiring3b. As the fixed potential, an intermediate potential between a driving voltage Vdd and a reference voltage Vss in the liquid crystal device100is applied to the capacitive wiring3b. For example, when the maximum potential of the driving voltage Vdd is 15.5 V and the reference voltage Vss is 0 V, a potential of about 6.5 V+/−1 V is applied as the intermediate potential.

In addition, as a method of connecting the capacitive wiring3bto the fixed potential, for example, there is a method in which the capacitive wiring3bis pulled out to a peripheral region of the outside of the display area E shown inFIG. 1A, and is connected to a wiring which is supplied to the fixed potential.

Manufacturing Method of Liquid Crystal Device

Subsequently, a manufacturing method of a liquid crystal device according to the embodiment will be described with reference toFIGS. 7A to 7F.FIGS. 7A to 7Fare schematic cross-sectional views which show the manufacturing method of the liquid crystal device. Specifically, the figure shows a formation method of the retention capacitor on the element substrate10, and corresponds to the cross-sectional view inFIG. 6.

The structure of the pixel P on the element substrate10is the same as that described above, and hereinafter, the formation method of the capacitive wiring3b, the dielectric layer14, and the pixel electrode15which configure the retention capacitors C1and C2on the interlayer insulating film12will be described in detail.

First, as shown inFIG. 7A, the first conductive film33and the second conductive film34which protects the first conductive film33are formed by covering the interlayer insulating film12.

The first conductive film33is, for example, formed of Al (aluminum), and the thickness thereof is about 500 nm. In the second conductive film34, it is possible to adopt a compound of metal, nitride, and oxygen such as TiN (titanium nitride) in which oxidization and corrosion hardly occurs compared to Al, and which has conductivity. The thickness of the second conductive film34is set to about 500 nm which is approximately the same as that of the first conductive film33, in consideration of formation processing and polishing processing of the insulating film13in later.

Subsequently, as shown inFIG. 7B, capacitive wiring layers35which are parallel to each other with a predetermined gap are formed (formation processing of the capacitive wiring layer), by patterning the first conductive film33and the second conductive film34which are laminated, using, for example, a photolithographic method.

In the insulating film13, it is possible to use silicon oxide or silicon nitride, and the insulating film is formed so that the thickness thereof becomes 1000 nm to 1500 nm using, for example, a plasma CVD technique. In this manner, it is possible to sufficiently cover the capacitive wiring layer35. On the surface of the insulating film13which covers the capacitive wiring layer35, unevenness occurs. According to the embodiment, the insulating film13is formed using SiO2.

Subsequently, as shown inFIG. 7D, the unevenness is removed, the capacitive wiring layer35is exposed, the insulating film13is polished and planarized (polishing processing of the insulating film) until the surface of the exposed capacitive wiring layer35and the surface13aof the insulating film13are on the same plane. The polishing is performed until the thickness of the second conductive film34becomes about 500 nm to 100 nm in the capacitive wiring layer35, not only for the insulating film13, in order to make sure the plane flush. Accordingly, the thickness of the insulating film13and the capacitive wiring layer35after the polishing, that is, the thickness of the capacitive wiring3bis about 600 nm. In the polishing of the insulating film13, it is possible to adopt, for example, chemical mechanical polishing (CMP) processing using a chemical treatment, or a mechanical processing process using abrasive.

Subsequently, as shown inFIG. 7E, the dielectric film is formed by covering the capacitive wiring3band the insulating film13which are on the same plane. As described above, only a portion of the dielectric film corresponding to the contact hole CNT4is removed by etching, and the dielectric layer14is formed (formation processing of the dielectric layer).

As the dielectric film, as described above, it is possible to use a single layer film such as silicon nitride film, oxide hafnium (HfO2), alumina (Al2O3), tantalum oxide (Ta2O5), or a multilayer film in which at least two of these single layer films are laminated may be used. According to the embodiment, the thickness is set to 20 nm to 30 nm, by laminating the alumina (Al2O3) and oxide hafnium (HfO2) in this order, so that the refractivity n becomes about 1.7.

Subsequently, as shown inFIG. 7F, the transparent conductive film such as ITO or IZO is formed on the dielectric layer14, for example, so that the thickness thereof becomes 20 nm to 200 nm, and is patterned using the photolithographic method, thereby forming the pixel electrode15of which a portion is overlapped with the two parallel capacitive wirings3b. According to the embodiment, the pixel electrode15is formed using ITO of which the refractivity n is about 1.9. Due to this, since the refractivity n of the insulating film13formed of SiO2is about 1.46, it is possible to arrange the dielectric layer14between the insulating film13and the pixel electrode15, of which the refractivity n denotes the intermediate value of the insulating film and the pixel electrode. Accordingly, it is possible to secure a desired transmittance in the aperture area, since the refractivity of light on the film interface which is input to a film of which the refractivity n is different is reduced, and the input light is hardly attenuated.

According to the liquid crystal device100and the manufacturing method thereof in the embodiment, following effect can be obtained.

(1) The capacitive wiring3bis formed so as to be embedded in the insulating film13, and the surface13aof the insulating film13and the surface of the capacitive wiring3bare planarized so as to be on the same plane. Accordingly, the surface of the pixel electrode15which is arranged through the dielectric layer14with respect to the insulating film13, or the capacitive wiring3bis planarized without being uneven. Therefore, it is possible to provide the liquid crystal device100in which the display unevenness due to the disorder of orientation of the liquid crystal molecules caused by the unevenness is reduced.

In addition, the pixel electrode15configures the two retention capacitors C1and C2such that the outer edge portion thereof is arranged so as to be overlapped with the two capacitive wirings3bwhich are adjacent and parallel to each other. The retention capacitors C1and C2are provided in the non-aperture area, as shown inFIGS. 3 and 4B, the aperture area is not made narrow by being provided with the provision of the retention capacitors C1and C2. In other words, it is possible to realize the retention capacitors C1and C2with a desired electric capacity, and to secure a high aperture ratio.

That is, it is possible to realize or manufacture the liquid crystal device100in which the display unevenness is reduced, and which has an excellent display quality (bright).

(2) The capacitive wiring layer35is formed of the first conductive film33and the second conductive film34which protects the first conductive film. In addition, in the process of polishing the insulating film13which covers the capacitive wiring layer35, even when the capacitive wiring layer35and the surface13aof the insulating film13are polished so as to be reliably on the same plane, the first conductive film33which configures the capacitive wiring3bis not damaged. Accordingly, it is possible to obtain the retention capacitors C1and C2with no electrical defects, since the electrical property in the first conductive film33is maintained.

Second Embodiment

Electronic Device

FIG. 8is a schematic diagram which shows a configuration of a projection-type display device as an electronic device. As shown inFIG. 8, a projection-type display device1000as the electronic device according to the embodiment includes a polarized illumination device1100which is arranged along a system optical axis L, two dichroic mirrors1104and1105as a light separating element, three reflecting mirrors1106,1107, and1108, five relay lenses1201,1202,1203,1204, and1205, three transmission type liquid crystal light valves1210,1220, and1230as light modulation units, a cross dichroic prism1206as a photosynthesis element, and a projector lens1207.

The polarized illumination device1100is schematically configured by a lamp unit1101as a light source which is formed of a white light source such as an ultra high pressure mercury lamp, or a halogen lamp, an integrator lens1102, and a polarization conversion element1103.

The dichroic mirror1104transmits the green light (G) and blue light (B) by reflecting the red light (R) among polarized light beams which are emitted from the polarized illumination device1100. The other dichroic mirror1105transmits the blue light (B) by reflecting the green light (G) which has transmitted the dichroic mirror1104.

The red light (R) which is reflected in the dichroic mirror1104is input to the liquid crystal light valve1210passing through the relay lens1205after being reflected in the reflecting mirror1106.

The green light (G) which is reflected in the dichroic mirror1105is input to the liquid crystal light valve1220passing through the relay lens1204.

The blue light (B) which has transmitted the dichroic mirror1105inputs to the liquid crystal light valve1230passing through a light guiding system which is formed of three relay lenses1201,1202, and1203, and two reflecting mirrors1107, and1108.

The liquid crystal light valves1210,1220, and1230are arranged opposite with respect to the input surface of each color light of the cross dichroic prism1206, respectively. The color light which is input to the liquid crystal light valves1210,1220, and1230is modulated on the basis of image information (image signal), and is emitted to the cross dichroic prism1206. The prism is formed such that four right angle prisms are attached, and in which a dielectric multilayer film which reflects the red light, and a dielectric multilayer film which reflects the blue light are formed in a cross shape. Three color light beams are synthesized by these dielectric multilayer films, and light which expresses a color image is synthesized. The synthesized light is projected on a screen1300by the projector lens1207as a projection optical system, and the image is displayed by being enlarged.

The above described liquid crystal device100is applied to the liquid crystal light valve1210. The liquid crystal device100is arranged with a gap between a pair of polarizing elements which are arranged in the cross Nichol prism in the input side and output side of the color light. The same is applied to other liquid crystal light valves1220and1230.

According to the projection-type display device1000, it is possible to realize a high display quality, since the display unevenness is reduced, and the liquid crystal device100with a high aperture ratio is used as the liquid crystal light valves1210,1220, and1230.

A variety of modification examples can be considered in addition to the above described embodiments. Hereinafter, the modification examples will be exemplified.

MODIFICATION EXAMPLE 1

In the above described embodiment, the formation method of the retention capacitor in which the surface of the capacitive wiring layer35and the surface13aof the insulating film13are planarized so as to be on the same plane, however, the method is not limited thereto.FIGS. 9A to 9Dare schematic cross-sectional views which show a manufacturing method (formation method of a retention capacitor) of a liquid crystal device in the modification example.

For example, first, as shown inFIG. 9A, a groove12ais formed in a region where a capacitive wiring3bof an interlayer insulating film12as an insulating film is formed (formation processing of groove).

When forming the groove12a, it is possible to form a contact hole CNT3and the groove12ain the same process, for example, when it is controlled so that the etching depth of the interlayer insulating film12is shallower than that of the contact hole CNT3using a half-tone mask, when forming the contact hole CNT3shown inFIG. 5in the interlayer insulating film12.

Subsequently, a capacitive wiring layer35is formed (formation processing of capacitive wiring layer) by laminating a first conductive film33and a second conductive film34, by covering the interlayer insulating film12so as to embed the groove12a.

Subsequently, as shown inFIG. 9B, a capacitive wiring layer35is polished, and the surface12bof the exposed interlayer insulating film12and the surface of the capacitive wiring layer35(that is, capacitive wiring3b) are planarized so as to be on the same plane. For the polishing of the capacitive wiring layer35, for example, it is possible to adopt chemical mechanical polishing (CMP) processing using a chemical treatment, or a mechanical processing process using an abrasive as in the case of the insulating film13. In practice, the interlayer insulating film12is also polished a little for the planarization.

Subsequently, as shown inFIG. 9C, a dielectric layer14is formed (formation processing of dielectric layer) by covering the capacitive wiring3band the interlayer insulating film12.

In addition, as shown inFIG. 9D, a transparent conductive film such as ITO, or IZO is formed on the dielectric layer14, these are patterned using a photolithographic method, thereby forming the pixel electrode15of which a portion is overlapped with two capacitive wirings3bwhich are parallel to each other.

According to a manufacturing method of the liquid crystal device in the modification example (formation method of retention capacitor), processing of forming the insulating film13on the interlayer insulating film12is not necessary. In addition, in the processing of polishing the capacitive wiring layer35, when the polishing speed of the capacitive wiring layer35is faster than that of the interlayer insulating film12, it is possible to expose the capacitive wiring3bfrom the capacitive wiring layer35earlier. In addition, since the groove12ais embedded by the capacitive wiring layer35, it is possible to prevent the capacitive wiring layer35from being excessively polished in order to make the surface thereof be in the same plane with respect to the surface12bof the interlayer insulating film12. In other words, it is possible to avoid waste in film formation, since it is possible to form the capacitive wiring layer35with a thickness which is close to the thickness necessary to form the capacitive wiring3b. It exerts the same effect when compared to a case where the insulating film13in the above described embodiment is polished.

MODIFICATION EXAMPLE 2

The configuration of a capacitive wiring3bin a liquid crystal device is not limited thereto. For example, it is also possible to arrange the capacitive wiring3bin the extension direction (X direction) of a scanning line3a, by removing a portion where a contact hole CNT4of a pixel electrode15is provided. In addition, the capacitive wiring3bmay be provided in a lattice shape as the non-aperture area shown inFIG. 3. In this manner, it is possible to further increase a portion which functions as a retention capacitor.

MODIFICATION EXAMPLE 3

The arrangement of a semiconductor layer30ain the liquid crystal device100is not limited thereto. For example, it is possible to apply the arrangement of a structure of the retention capacitor according to the invention, even when the semiconductor layer30ais arranged in a direction which goes along a data line6a, at the intersection of a scanning line3aand a data line6a, or the semiconductor layer30ais arranged by being bent at the intersection.

MODIFICATION EXAMPLE 4

The electronic device to which the liquid crystal device100is applied is not limited to the projection-type display device1000in the above described embodiment. The liquid crystal device is preferably used as a display unit of, for example, such as a projection-type HUD (Heads Up Display), a direct viewing type HMD (Head-Mounted Display) or an electronic book, a personal computer, a digital still camera, a liquid crystal TV, a video recorder of a viewfinder type, or of a direct-view monitor type, a car navigation system, an electronic organizer, POS, or the like, information terminal devices.

MODIFICATION EXAMPLE 5

The electronic device to which a structure of the retention capacitors C1and C2of the element substrate10is applicable is not limited to the liquid crystal device100. For example, as an active matrix electro-optic device having a transistor, it is possible to apply to a display device such as an organic EL (Electro Luminescence) device, or an electrophoresis apparatus.

When the device is applied to the organic EL device, it is possible to make the film thickness of the functional layer having a function of light emission which is formed on the pixel electrode be uniform, easily. In addition, it is possible to reduce uneven light emission.

When the device is applied to the electrophoresis apparatus, it is possible to make the film thickness of an electrophoresis layer on the pixel electrode be uniform. In addition, it is possible to reduce display unevenness.

This application claims priority to Japan Patent Application No. 2011-081650 filed Apr. 1, 2011, the entire disclosures of which are hereby incorporated by reference in their entireties.