Power conversion device

A first voltage control circuitry controls a first representative value, i.e., an average-value corresponding value of DC capacitor voltages of all converter cells to follow an overall voltage command value. A phase balance control circuitry controls second representative values, i.e., average-value corresponding values of DC capacitor voltages of the converter cells in leg circuits for respective phases to follow the first representative value. A positive-negative balance control circuitry controls deviations of third representative values, i.e., average-value corresponding values of the DC capacitor voltages of the converter cells in the positive and negative arms of the leg circuits for respective phases to become zero between the positive and negative arms. An individual balance control circuitry controls DC capacitor voltages of all the converter cells to follow the third representative values.

CROSS-REFERENCE TO RELATED APPLICATION

The present application is based on PCT filing PCT/JP2021/014451, filed Apr. 5, 2021, the entire contents of which are incorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates to a power conversion device.

BACKGROUND ART

In recent years, in a power conversion device used for high-voltage application such as a power grid, a multilevel converter formed by connecting a plurality of converter cells in series in a multiplexed manner is being put into practice. Such a converter is called a modular multilevel converter (hereinafter, abbreviated as MMC) type, a cascaded multilevel converter (hereinafter, abbreviated as CMC) type, or the like, and is used for conversion from three-phase AC to DC or conversion opposite thereto, for example. The converter generates output voltage using DC capacitor voltages of the converter cells connected in series in a multiplexed manner.

CITATION LIST

Patent Document

SUMMARY OF THE INVENTION

Problem to be Solved by the Invention

DC capacitor voltage in each converter cell of the modular multilevel converter varies through charging/discharging of current flowing through an arm. Therefore, it is necessary to perform control for making a balance within a certain range so that voltage of each converter cell does not become overvoltage.

In a power conversion device described in Patent Document 1, in order to control capacitor voltages of converter cells of a modular multilevel converter so as to be constant, the following controls are performed: average value control for performing control so as to reach the average value of the capacitor voltages in each phase arm for each phase independently, individual balance control for balancing the capacitor voltage of each converter cell for each phase independently, and positive-negative arm balance control for balancing capacitor voltages in the positive and negative arms for each phase independently.

That is, in Patent Document 1, control is performed for each phase independently, to control the capacitor voltages of the converter cells so as to be constant.

An object of the present disclosure is to provide a power conversion device in which voltages of DC capacitors of all converter cells are kept within a certain range and the DC capacitor voltages of the converter cells are averaged, thereby preventing overvoltage of each converter cell.

Means to Solve the Problem

A power conversion device according to the present disclosure includes: a power converter which performs power conversion between an AC grid with a plurality of phases and a DC grid; and a control device which controls the power converter. The power converter includes leg circuits respectively corresponding to the plurality of phases of AC, the leg circuits each having a pair of a positive arm and a negative arm connected in series. Each of the positive arm and the negative arm includes one converter cell or a plurality of converter cells connected in series, the one or each converter cell including a series unit of a plurality of semiconductor switching elements connected in series and a DC capacitor connected in parallel to the series unit. A connection point between the positive arm and the negative arm is connected to the AC grid, and the plurality of leg circuits are connected in parallel between positive and negative DC buses of the DC grid. The control device includes: a first voltage control unit which performs control so that a first representative value which is an average-value corresponding value of DC capacitor voltages of all the converter cells follows a predetermined overall voltage command value, to generate a first voltage command value; a phase balance control unit which performs control so that a second representative value which is an average-value corresponding value of the DC capacitor voltages of the converter cells in the leg circuit for each phase follows the first representative value, to generate a second voltage command value; a positive-negative balance control unit which performs control so that a deviation of third representative values which are average-value corresponding values of the DC capacitor voltages of the converter cells in the positive arm and the negative arm of the leg circuit for each phase becomes zero between the positive arm and the negative arm of the leg circuit for each phase, to generate a third voltage command value; a voltage command value calculation unit which generates an arm modulation command for each arm on the basis of the first voltage command value, the second voltage command value, and the third voltage command value; an individual balance control unit which performs control so that the DC capacitor voltages of all the converter cells follow the third representative values, to generate individual modulation commands for the respective converter cells; and a gate signal generation unit which generates drive signals for the semiconductor switching elements on the basis of the arm modulation commands and the individual modulation commands.

Effect of the Invention

With the power conversion device according to the present disclosure, voltages of DC capacitors of all converter cells are kept within a certain range and the DC capacitor voltages of the converter cells are averaged, whereby overvoltage of each converter cell can be prevented.

DESCRIPTION OF EMBODIMENTS

Hereinafter, a power conversion device according to embodiments of the present disclosure will be described with reference to the drawings.

[Entire Configuration of Power Conversion Device]

FIG.1is a block diagram showing the schematic configuration of a power conversion system including a power conversion device according to embodiment 1.

As shown inFIG.1, a power conversion device100includes a power converter1and a control device7.

The power converter1performs power conversion between AC and DC mutually, the AC side thereof is connected to an AC grid (AC circuit)2as plural-phase AC (e.g., three-phase AC) via a transformer3, and the DC side thereof is connected to a DC grid (DC circuit) (not shown) via a positive DC terminal6P and a negative DC terminal6N.

The power converter1includes three leg circuits8u,8v,8wprovided respectively for U phase, V phase, and W phase of the three-phase AC as the plural-phase AC and connected in parallel between the positive DC terminal6P and the negative DC terminal6N.

The leg circuit8uhas a positive arm9puand a negative arm9nuas a pair of arms, and the positive arm9puand the negative arm9nuare connected in series to each other.

One end of the positive arm9puis connected to the positive DC terminal6P, and one end of the negative arm9nuis connected to the negative DC terminal6N. A connection point4ubetween the positive arm9puand the negative arm9nuis connected to a U-phase terminal of the transformer3.

The leg circuit8vhas a positive arm9pvand a negative arm9nvas a pair of arms, and the positive arm9pvand the negative arm9nvare connected in series to each other.

One end of the positive arm9pvis connected to the positive DC terminal6P, and one end of the negative arm9nvis connected to the negative DC terminal6N. A connection point4vbetween the positive arm9pvand the negative arm9nvis connected to a V-phase terminal of the transformer3.

The leg circuit8whas a positive arm9pwand a negative arm9nwas a pair of arms, and the positive arm9pwand the negative arm9nware connected in series to each other.

One end of the positive arm9pwis connected to the positive DC terminal6P, and one end of the negative arm9nwis connected to the negative DC terminal6N. A connection point4wbetween the positive arm9pwand the negative arm9nwis connected to a W-phase terminal of the transformer3.

Next, the configurations of the leg circuits8u,8v,8wwill be described.

The leg circuits8v,8wfor V phase and W phase have the same configuration as the leg circuit8ufor U phase, and therefore description will be given using the leg circuit8ufor U phase.

The positive arm9puof the leg circuit8uincludes a plurality of converter cells10connected in series and a reactor5uP, and the plurality of converter cells10and the reactor5uP are connected in series to each other.

Similarly, the negative arm9nuof the leg circuit8uincludes a plurality of converter cells10connected in series and a reactor5uN, and the converter cells10and the reactor5uN are connected in series to each other.

The reactor5uP may be provided at any position in the positive arm9pu, and also, the reactor5uN may be provided at any position in the negative arm9nu. The inductance values of the reactors5uP,5uN may be different from each other, and the reactors5uP,5uN may be coupled with reactors for another phase. A configuration in which the reactor5uP is provided only in the positive arm9pumay be adopted, or a configuration in which the reactor5uN is provided only in the negative arm9numay be adopted. Each arm reactor is interposed so as to reduce circulation current circulating in the converter, and only has to be connected in series to the converter cell10. A plurality of arm reactors may be interposed in a distributed manner.

In the following description, when the leg circuits8u,8v,8wneed not be discriminated from each other, they are referred to as leg circuits8. In addition, when the positive arms9pu,9pv,9pwand the negative arms9nu,9nv,9nwneed not be discriminated from each other, they are referred to as arms9or as positive arms9P and negative arms9N.

[Configuration of Converter Cell]

Next, the configuration of the converter cell10composing each leg circuit8will be described.

FIG.2is a circuit diagram showing an example of the configuration of the converter cell10according to embodiment 1.

FIG.3is a circuit diagram showing a configuration example of the converter cell10according to embodiment 1, which is different fromFIG.2.

FIG.4is a circuit diagram showing a configuration example of the converter cell10according to embodiment 1, which is different fromFIG.2andFIG.3.

As the converter cell10, any of the circuit configurations shown inFIG.2toFIG.4may be used, and the circuit configurations may be combined in the positive arm9P and the negative arm9N.

The converter cell10shown inFIG.2includes a series unit of semiconductor switching elements12U,12L connected in series to each other, a DC capacitor15as an energy storage element connected in parallel to the series unit, and a voltage sensor16for detecting a voltage value Vcap of the DC capacitor15. A connection point between the semiconductor switching elements12U and12L is connected to an input/output terminal12aon the positive side, and a connection point between the semiconductor switching element12L and the DC capacitor15is connected to an input/output terminal12bon the negative side.

In the converter cell10having the configuration shown inFIG.2, the semiconductor switching elements12U,12L are controlled such that one of them is turned on and the other is turned off. When the semiconductor switching element12U is ON and the semiconductor switching element12L is OFF, voltage across the DC capacitor15is applied between the input/output terminals12aand12b. Positive-side voltage is applied on the input/output terminal12aside and negative-side voltage is applied on the input/output terminal12bside.

The converter cell10shown inFIG.3includes a series unit of semiconductor switching elements12U,12L connected in series to each other, a DC capacitor15as an energy storage element connected in parallel to the series unit, and a voltage sensor16for detecting a voltage value Vcap of the DC capacitor15. A connection point between the semiconductor switching elements12U and12L is connected to an input/output terminal12bon the negative side, and a connection point between the semiconductor switching element12U and the DC capacitor15is connected to an input/output terminal12aon the positive side.

In the converter cell10having the configuration shown inFIG.3, the semiconductor switching elements12U,12L are controlled such that one of them is turned on and the other is turned off. When the semiconductor switching element12U is OFF and the semiconductor switching element12L is ON, voltage across the DC capacitor15is applied between the input/output terminals12aand12b. Positive-side voltage is applied on the input/output terminal12aside, and negative-side voltage is applied on the input/output terminal12bside.

The converter cell10having the configuration shown inFIG.4includes a series unit of semiconductor switching elements12U1,12L1connected in series to each other, a series unit of semiconductor switching elements12U2,12L2which are also connected in series to each other, a DC capacitor15as an energy storage element, and a voltage sensor16for detecting a voltage value Vcap of the DC capacitor15. The series unit of the semiconductor switching elements12U1,12L1, the series unit of the semiconductor switching elements12U2,12L2, and the DC capacitor15are connected in parallel to each other.

In the converter cell10having the configuration shown inFIG.4, the semiconductor switching elements12U1,12L1are controlled such that one of them is turned on and the other is turned off. Similarly, the semiconductor switching elements12U2,12L2are controlled such that one of them is turned on and the other is turned off. When the semiconductor switching element12U1is ON and the semiconductor switching element12L1is OFF and when the semiconductor switching element12U2is OFF and the semiconductor switching element12L2is ON, voltage across the DC capacitor15is applied between the input/output terminals12aand12b. Positive-side voltage is applied on the input/output terminal12aside, and negative-side voltage is applied on the input/output terminal12bside.

When the semiconductor switching elements12U,12L,12U1,12L1,12U2,12L2are collectively mentioned, they are referred to as semiconductor switching elements12.

[Detectors of Power Conversion Device]

Next, detectors for detecting voltages and currents of the power conversion device100will be described.

The power conversion device100includes a plurality of detectors for detecting voltages and currents of the power conversion device100, in addition to the voltage sensor16for detecting the voltage value Vcap (hereinafter, referred to as DC capacitor voltage value Vcap) of the DC capacitor15.

That is, as shown inFIG.1, current sensors40are provided for detecting arm currents Ipu, Inu, Ipv, Inv, Ipw, Inw flowing through the respective arms9pu,9nu,9pv,9pn,9pw,9nwof the leg circuits8u,8v,8w. In addition, a voltage sensor20is provided for detecting AC voltages Vu, Vv, Vw of the AC grid2, a current sensor30is provided for detecting AC currents Iu, Iv, Iw of the AC grid2, a voltage sensor (not shown) is provided for detecting DC voltage Vdc between the positive DC terminal6P and the negative DC terminal6N, and a current sensor60is provided for detecting DC current Idc flowing through the positive DC terminal6P or the negative DC terminal6N.

[Control Device for Power Converter]

The control device7receives detection values measured by the plurality of detectors. That is, the control device7receives the DC capacitor voltage values Vcap of all the converter cells10, the arm currents Ipu, Inu, Ipv, Inv, Ipw, Inw flowing through the respective arms9pu,9nu,9pv,9pn,9pw,9nw, the AC voltages Vu, Vv, Vw of the AC grid2, the AC currents Iu, Iv, Iw of the AC grid2, and the DC current Idc and the DC voltage Vdc between the positive DC terminal6P and the negative DC terminal6N.

Further, the control device7receives a DC voltage command Vdc* for the DC voltage between the positive DC terminal6P and the negative DC terminal6N, and an overall voltage command value Vcap* which is a command value for the DC capacitor voltages of all the converter cells10. The DC voltage command Vdc* and the overall voltage command value Vcap* may be inputted from outside or may be set or generated in the control device7.

FIG.5is a block diagram showing the control device for the power converter according to embodiment 1.

The control device7includes a first voltage control unit400including an overall voltage control unit200and a current control unit300, a phase balance control unit500, a positive-negative balance control unit600, a voltage command value calculation unit700, an individual balance control unit800, and a gate signal generation unit900.

The first voltage control unit400performs control so that a first representative value Vcap_av which is an average-value corresponding value of the DC capacitor voltages of all the converter cells10follows the predetermined overall voltage command value Vcap*, thus generating first voltage command values Vac*.

The phase balance control unit500performs control so that second representative values Vcapu, Vcapv, Vcapw which are average-value corresponding values of the DC capacitor voltages of the converter cells10in the leg circuits8for the respective phases follow the first representative value Vcap_av, thus generating second voltage command values Vz*.

The positive-negative balance control unit600performs control so that a deviation of third representative values VcapXX_av which are average-value corresponding values of the DC capacitor voltages of the converter cells10in the positive arm and the negative arm of the leg circuit8for each phase, becomes zero between the positive arm and the negative arm of the leg circuit8for each phase, thus generating third voltage command values Vpn*.

The voltage command value calculation unit700generates arm modulation commands Kref on the basis of the first voltage command values Vac*, the second voltage command values Vz*, and the third voltage command values Vpn*.

The individual balance control unit800performs control so that the DC capacitor voltages Vcap of all the converter cells10follow the third representative values VcapXX_av, thus generating individual modulation commands ΔKsm.

The gate signal generation unit900generates gate signals for driving the semiconductor switching elements12on the basis of the arm modulation commands Kref and the individual modulation commands ΔKsm.

As described above, the first voltage control unit400includes the overall voltage control unit200and the current control unit300.

The overall voltage control unit200generates an active current command value Iq* so that a difference between the first representative value Vcap_av and the overall voltage command value Vcap* becomes zero.

The current control unit300generates the first voltage command values Vac* so that active current Iq of the power converter1follows the active current command value Iq* and reactive current Id of the power converter1follows a reactive current command value Id*.

The control device7is composed of a processor1000and a storage device1001, as shown inFIG.14which shows a hardware example thereof. Although not shown, the storage device is provided with a volatile storage device such as a random access memory and a nonvolatile auxiliary storage device such as a flash memory.

Instead of the flash memory, an auxiliary storage device of a hard disk may be provided. The processor1000executes a program inputted from the storage device1001. In this case, the program is inputted from the auxiliary storage device to the processor1000via the volatile storage device. The processor1000may output data such as a calculation result to the volatile storage device of the storage device1001, or may store such data into the auxiliary storage device via the volatile storage device.

The control device7may be formed by a dedicated circuit, or a part or the entirety thereof may be formed by a field programmable gate array (FPGA).

[Currents Flowing in Power Conversion Device]

Here, before describing operation of the control device7in embodiment 1, currents flowing in the power conversion device100will be described with reference toFIG.6.

InFIG.6, respective currents are as follows.Ipu, Ipv, Ipw: currents flowing through the U-phase positive arm9pu, the V-phase positive arm9pv, and the W-phase positive arm9pw.Inu, Inv, Inw: currents flowing through the U-phase negative arm9nu, the V-phase negative arm9nv, and the W-phase negative arm9nw.Iu: AC current for U phase flowing through the AC grid. Halves of the AC current Iu divisionally flow into the U-phase positive arm9puand the U-phase negative arm9nu.Iv: AC current for V phase flowing through the AC grid. Halves of the AC current Iv divisionally flow into the V-phase positive arm9pvand the V-phase negative arm9nv.Iw: AC current for W phase flowing through the AC grid. Halves of the AC current Iw divisionally flow into the W-phase positive arm9pwand the W-phase negative arm9nw.Idc: current flowing through the DC grid. One-third of Idc flows into each of the U-phase arm, the V-phase arm, and the W-phase arm.Izu: a current component obtained by excluding current Iu/2 flowing through the AC power grid from the currents Ipu, Inu flowing through the U-phase arm. The following relationships are satisfied.
Izu=Ipu+Iu/2  (1)
Izu=Inu−Iu/2  (2)Izuc: a circulation current component circulating among the leg circuits8u,8v,8wwithout flowing through the AC grid and the DC grid. When the current Iu is eliminated from the above Expressions (1) and (2), the current component Izu is represented by the following Expression (3).
Izu=(Ipu+Inu)/2  (3)

Thus, the circulation current component Izuc is represented by the following Expression (4).
Izuc=Izu−Idc/3  (4)

Similarly, although not shown,Izv: a current component obtained by excluding current Iv/2 flowing through the AC power grid from the currents Ipv, Inv flowing through the V-phase arm.Izw: a current component obtained by excluding current Iw/2 flowing through the AC power grid from the currents Ipw, Inw flowing through the W-phase arm.

Then, circulation current components Izvc, Izwc are represented by the following Expressions (5) and (6).
Izvc=Izv−Idc/3  (5)
Izwc=Izw−Idc/3  (6)
[Outline of Control for Power Converter]

Next, the outline of control for the power converter1will be described.

In the power converter1, temporal change of the DC capacitor voltage of each converter cell10is a value obtained by dividing AC instantaneous power by the DC capacitor voltage and thus depends on the AC current. Therefore, oscillation with the same frequency as a grid frequency of the AC grid occurs.

In each arm voltage, oscillation with a frequency that is two times the grid frequency of the AC grid occurs due to power pulsation of (AC voltage)×(AC current).

Therefore, in the power converter1, it is important to balance the DC capacitor voltages of the converter cells10within a certain range so that the voltage of each converter cell10does not become overvoltage.

In control for the DC capacitor voltages in the power converter1of embodiment 1, control regarding the following four voltage components is performed.

The first voltage control unit400performs control regarding the first representative value which is an average-value corresponding value of the DC capacitor voltages of all the converter cells10.

The phase balance control unit500performs control regarding the second representative value which is an average-value corresponding value of the DC capacitor voltages of the converter cells10in the leg circuit8for each phase.

The positive-negative balance control unit600performs control regarding the third representative values which are average-value corresponding values of the DC capacitor voltages of the converter cells10in the positive arm and the negative arm of the leg circuit8for each phase.

The individual balance control unit800performs control for individual DC capacitor voltages of the respective converter cells10.

[Variation of DC Capacitor Voltage]

Here, variation of the DC capacitor voltage will be described in more detail.

In the power converter1, the DC voltage Vdc and the DC current Idc have the same polarities between the positive arm and the negative arm, and have the same polarities among the phases.

In a case where AC voltages and AC currents inputted/outputted to/from the power converter1are in a three-phase balanced state, the AC voltages and the AC currents have opposite polarities between the positive arm and the negative arm, and are shifted from each other by 120 degrees among the phases.

That is, oscillations of the DC capacitor voltages with the same frequency as the grid frequency have opposite polarities between the positive arm and the negative arm, and are shifted from each other by 120 degrees among the phases. Oscillations of the DC capacitor voltages with a frequency that is two times the grid frequency have the same polarities between the positive arm and the negative arm, and are shifted from each other by 120 degrees among the phases.

Therefore, in the average of the DC capacitor voltages in only the arm on the one side for one of the plurality of phases, there are both of oscillation with the same frequency as the grid frequency and oscillation with a frequency that is two times the grid frequency.

In the average voltage of the DC capacitors in the leg circuit for each phase, oscillations with the same frequency as the grid frequency are canceled out between the positive arm and the negative arm, so that there is only oscillation of a frequency component that is two times the grid frequency.

In the average of the DC capacitor voltages of all the converter cells, oscillations with the same frequency as the grid frequency and oscillations with a frequency that is two times the grid frequency are both cancelled out between the arms and among the phases, so that there are no oscillation components.

[Details of Control for Power Converter]

Hereinafter, the detailed operation of the control device7for the power converter1will be described.

FIG.7shows a control block diagram of the overall voltage control unit200in embodiment 1.

The overall voltage control unit200receives the DC capacitor voltages Vcap of all the converter cells10(in all arms for all phases), the DC capacitor voltage command value Vcap* (hereinafter, referred to as overall voltage command value Vcap*) for all the converter cells10, and the DC current command value Idc*.

When the DC capacitor voltage values of all the converter cells10are described as a representative, they are referred to as Vcap, as shown inFIG.5, for example. When they are described individually, for example, as shown inFIG.7, the DC capacitor voltages in the U-phase positive arm are referred to as Vcappu1, . . . , Vcappuk, the DC capacitor voltages in the U-phase negative arm are referred to as Vcapnu1, . . . , Vcapnuk, the DC capacitor voltages in the V-phase positive arm are referred to as Vcappv1, . . . , Vcappvk, the DC capacitor voltages in the V-phase negative arm are referred to as Vcapnv1, . . . , Vcapnvk, the DC capacitor voltages in the W-phase positive arm are referred to as Vcappw1, . . . , Vcappwk, and the DC capacitor voltages in the U-phase negative arm are referred to as Vcapnw1, . . . , Vcapnwk.

InFIG.7, a first representative value calculation unit210of the overall voltage control unit200calculates the average-value corresponding value Vcap_av of the DC capacitor voltages Vcap of all the converter cells10. Here, the average-value corresponding value Vcap_av may be the average value obtained by dividing the sum of the DC capacitor voltages Vcap of all the converter cells10by the number of all the converter cells10or the median value of the DC capacitor voltages Vcap of all the converter cells10. The average-value corresponding value Vcap_av calculated in the first representative value calculation unit210is referred to as the first representative value Vcap_av in the present disclosure.

Then, the overall voltage control unit200performs control so that the average-value corresponding value Vcap_av of the DC capacitor voltages Vcap of all the converter cells10follows the predetermined overall voltage command value Vcap*. As the average-value corresponding value Vcap_av of the DC capacitor voltages Vcap of all the converter cells, a filtered value thereof may be used in order to suppress sharp change.

Since a difference between AC power and DC power in the power converter1is common active power among all the converter cells10, the DC capacitor voltages of all the converter cells10are controlled with active current Iq. That is, feedback control is performed by a controller220such as a proportional integral (PI) controller so that a difference between the average-value corresponding value Vcap_av of the DC capacitor voltages Vcap of all the converter cells10and the overall voltage command value Vcap* becomes 0. Then, to a control quantity230having undergone feedback, the DC current command value Idc* or a value obtained by filtering the DC current detection value Idc detected by the current sensor60is added by an adder240, and the resultant control quantity after the addition is outputted as the active current command value Iq*.

Then, the overall voltage control unit200outputs the active current command value Iq* to the current control unit300, and outputs the average-value corresponding value Vcap_av calculated by the first representative value calculation unit210, as the first representative value Vcap_av*, to the phase balance control unit500.

Next, the configuration and operation of the current control unit300in embodiment 1 will be described.

As shown inFIG.5, the current control unit300receives the AC voltages Vu, Vv, Vw detected by the voltage sensor20, the AC currents Iu, Iv, Iw detected by the current sensor30, the active current command value Iq* outputted from the overall voltage control unit200, and the reactive current command value Id* determined from the operation condition of the power conversion device100.

FIG.8shows a control block diagram of the current control unit300in embodiment 1.

In the current control unit300, the active current Iq and the reactive current Id of all the converter cells10in the power converter1are controlled, thereby performing power control of the power converter1.

The active current Iq and the reactive current Id are calculated by performing three-phase/two-phase conversion on the basis of the AC currents Iu, Iv, Iw and a phase θ synchronized with the AC voltages Vu, Vv, Vw, as shown by the following Expression (7).

That is, inFIG.8, a phase detector311having received the AC voltages Vu, Vv, Vw detects the phase θ of the AC voltages Vu, Vv, Vw. Then, a three-phase/two-phase converter310receives the AC currents Iu, Iv, Iw and the phase θ of the AC voltages Vu, Vv, Vw outputted from the phase detector311, and calculates the active current Iq and the reactive current Id on the basis of the above Expression (7).

Next, feedback control is performed by controllers320and330such as PI controllers so that the active current Iq and the reactive current Id respectively follow the active current command value Iq* and the reactive current command value Id*, thereby calculating voltage command values Vd*, Vq* on d and q axes.

Next, a two-phase/three-phase converter350receives the voltage command values Vd*, Vq* on d and q axes, and outputs AC voltage command values Vacu*, Vacv*, Vacw* for the respective phases (U phase, V phase, W phase), using the following Expression (8). When the AC voltage command values Vacu*, Vacv*, Vacw* are collectively mentioned, they are referred to as AC voltage command values Vac*.

Then, the current control unit300outputs the AC voltage command values Vac* (Vacu*, Vacv*, Vacw*) to the voltage command value calculation unit700at a subsequent stage.

Here, the AC voltage command values Vac* (Vacu*, Vacv*, Vacw*) are referred to as the first voltage command values in the present disclosure.

Next, the configuration and operation of the phase balance control unit500in embodiment 1 will be described.

As shown inFIG.5, the phase balance control unit500receives the DC capacitor voltages Vcap of all the converter cells10, the arm currents Ipu, Inu, Ipv, Inv, Ipw, Inw detected by the current sensors40, the DC current Idc detected by the current sensor60, the average-value corresponding value (first representative value) Vcap_av* of all the DC capacitor voltages outputted from the overall voltage control unit200, and circulation current commands value Izpn* (Izpna*, Izpnb) for positive-negative balance outputted from the positive-negative balance control unit600described later.

FIG.9shows a control block diagram of the phase balance control unit500in embodiment 1.

The phase balance control unit500performs control so that the average-value corresponding values (second representative values) Vcapu, Vcapv, Vcapw of the DC capacitor voltages for the respective phases (U phase, V phase, W phase) follow the average-value corresponding value (first representative value) Vcap_av* of all the DC capacitor voltages outputted from the overall voltage control unit200.

A second representative value calculation unit510calculates the average-value corresponding values (second representative values) Vcapu, Vcapv, Vcapw of the DC capacitor voltages of all the converter cells10in the leg circuits8u,8v,8wfor the respective phases (U phase, V phase, W phase).

Each of the average-value corresponding values (second representative values) Vcapu, Vcapv, Vcapw of the DC capacitor voltages of the converter cells10for the respective phases may be the average value of the DC capacitor voltages Vcap for each phase, the median value of the DC capacitor voltages Vcap for each phase, or a representative value calculated from the maximum value and the minimum value of the DC capacitor voltages Vcap for each phase.

The average-value corresponding values (second representative values) Vcapu, Vcapv, Vcapw of the DC capacitor voltages for the respective phases oscillate with a frequency that is two times the grid frequency, and frequency components that are two times the grid frequency are removed from the second representative values Vcapu, Vcapv, Vcapw by filters511,512,513. As the filters511,512,513, moving average filters or notch filters for the frequency that is two times the grid frequency are applied, for example.

Next, values obtained through the filters511,512,513from the second representative values Vcapu, Vcapv, Vcapw are referred to as Vcapu-, Vcapv-, Vcapw-, and the values Vcapu-, Vcapv-, Vcapw- are subjected to three-phase/two-phase conversion by a three-phase/two-phase converter520on the basis of the following Expression (9), thus calculating control values Vcapa, Vcapb.

Next, using controllers521,522, for example, proportional integral (PI) control is performed so that a deviation between the average-value corresponding value (first representative value) Vcap_av* of all the capacitor voltages outputted from the overall voltage control unit200and each of the control values Vcapa, Vcapb becomes zero, thus calculating circulation current command values Iza*, Izb* for phase balance.

Next, the circulation current command values Iza*, Izb* for phase balance and the circulation current command values Izpna*, Izpnb* for positive-negative balance outputted from the positive-negative balance control unit600described later, are respectively added.

Then, using controllers531,532, for example, proportional integral (PI) control is performed so that deviations between control values Iza, Izb outputted from a three-phase/two-phase converter560described later and the values obtained by adding the circulation current command values Iza*, Izb* for phase balance and the circulation current command values Izpna*, Izpnb* for positive-negative balance, become zero, thus outputting output values531a,531b. Then, the output values531a,531bare converted by a two-phase/three-phase converter540, to output voltage command values VzU*, VzV*, VzW* for circulation current. Here, when the voltage command values VzU*, VzV*, VzW* for circulation current are collectively mentioned, they are referred to as the voltage command values Vz*.

Meanwhile, a circulation current calculation unit550of the phase balance control unit500receives the arm currents Ipu, Inu, Ipv, Inv, Ipw, Inw and the DC current Idc, and calculates the circulation currents Izuc, Izvc, Izwc using the above Expressions (3) to (6). Then, the three-phase/two-phase converter560performs three-phase/two-phase conversion of the circulation currents Izuc, Izvc, Izwc on the basis of the following Expression (10), thus outputting the control values Iza, Izb.

As described above, the control values Iza, Izb outputted from the three-phase/two-phase converter560are subjected to, for example, PI control, using the controllers531,532, so that deviations between the control values Iza, Izb and the values obtained by adding the circulation current command values Iza*, Izb* for phase balance and the circulation current command values Izpna*, Izpnb* for positive-negative balance, become zero.

The phase balance control unit500outputs the voltage command values VzU*, VzV*, VzW* for circulation current from the two-phase/three-phase converter540to the voltage command value calculation unit700at a subsequent stage.

When the voltage command values VzU*, VzV*, VzW* are collectively mentioned, they are referred to as the voltage command values Vz* (seeFIG.5).

Also, the voltage command values Vz* (VzU*, VzV*, VzW*) are referred to as the second voltage command values in the present disclosure.

Next, the configuration and operation of the positive-negative balance control unit600in embodiment 1 will be described.

As shown inFIG.5, the positive-negative balance control unit600receives the DC capacitor voltages Vcap of all the converter cells10.

The positive-negative balance control unit600performs control so that the DC capacitor voltages in the positive arms and the DC capacitor voltages in the negative arm are balanced in each of the leg circuits8u,8v,8wfor the respective phases (U phase, V phase, W phase).

In order to eliminate imbalance of the DC capacitor voltages between the positive arm and the negative arm, the direction (current charging/discharging direction) of power flowing into the DC capacitors15needs to be reversed between the positive arm and the negative arm. Since the AC voltages inputted/outputted to/from the power converter1have opposite polarities between the positive arm and the negative arm, 1f-component AC currents having the same polarity are caused to flow in order to charge/discharge the DC capacitors between the positive arm and the negative arm.

FIG.10shows a control block diagram of the positive-negative balance control unit600in embodiment 1.

A third representative value calculation unit610receives the DC capacitor voltage values Vcap of all the converter cells10and calculates an average-value corresponding value (Vcapup_av, Vcapun_av, Vcapvp_av, Vcapvn_av, Vcapwp_av, Vcapwn_av) of the DC capacitor voltages of the converter cells10in each of the positive arm and the negative arm for each phase (U phase, V phase, W phase). Here, the average-value corresponding value may be the average value of the DC capacitor voltages in each of the positive arm and the negative arm for each phase, the median value of the DC capacitor voltages in each of the positive arm and the negative arm for each phase, or a representative value calculated from the maximum value and the minimum value of the DC capacitor voltages in each of the positive arm and the negative arm for each phase.

Then, control is performed so that, for each phase, a difference between the average-value corresponding value (Vcapup_av, Vcapvp_av, Vcapwp_av) of the DC capacitor voltages in the positive arm and the average-value corresponding value (Vcapun_av, Vcapvn_av, Vcapwn_av) of the DC capacitor voltages in the negative arm, becomes zero.

Specifically, as shown inFIG.10, the values of the differences between the average-value corresponding values (Vcapup_av, Vcapvp_av, Vcapwp_av) of the DC capacitor voltages in the positive arm and the average-value corresponding values (Vcapun_av, Vcapvn_av, Vcapwn_av) of the DC capacitor voltages in the negative arm calculated by the third representative value calculation unit610are respectively multiplied by (½) at multipliers, and the multiplied values are filtered through filters621,622,623.

In the calculated average-value corresponding value of the DC capacitor voltages in the arm on one side, there are oscillation with the same frequency as the grid frequency and oscillation with a frequency that is two times the grid frequency. Therefore, in the filters621,622,623, the above values are filtered through moving average filters for the same frequency as the grid frequency, or through notch filters for the same frequency as the grid frequency and notch filters with a frequency that is two times the grid frequency.

Then, the values (referred to as positive-negative balance outputs for respective phases) obtained through the filters621,622,623are subjected to, for example, PI control by controllers631,632,633, and the resultant values are outputted.

Here, in order to eliminate imbalance of the DC capacitor voltages between the positive arm and the negative arm, the direction (current charging/discharging direction) of power flowing into the DC capacitors needs to be reversed between the positive arm and the negative arm. Since the AC voltages inputted/outputted to/from the power converter1have opposite polarities between the positive arm and the negative arm, 1f-component (fundamental-component) AC currents having the same polarity need to be caused to flow in order to charge/discharge the DC capacitors between the positive arm and the negative arm.

That is, with respect to the output values of the controllers631,632,633, magnitudes of AC currents needed for balancing the positive arm and the negative arm for each phase are outputted, and then are multiplied by unit sine waves (Vuunit, Vvunit, Vwunit) having a magnitude of 1 and the same phases as the AC voltages for the respective phases, at multipliers651,652,653, thus calculating 1f-component (fundamental-component) AC currents. Then, these are subjected to three-phase/two-phase conversion by the three-phase/two-phase converter660, thus outputting circulation current command values (Izpna*, Izpnb*) for positive-negative balance.

That is, the values (positive-negative balance outputs for respective phases) obtained through the filters621,622,623are added and then the resultant value is multiplied by (⅓) at a multiplier, thus calculating neutral point voltage Vz. Then, differences between the neutral point voltage Vz and the positive-negative balance outputs for respective phases are subjected to, for example, PI control by the controllers671,672,673, thus outputting the AC voltage commands VpnU*, VpnV*, VpnW* for positive-negative balance. Here, when the AC voltage commands VpnU*, VpnV*, VpnW* are collectively mentioned, they are referred to as the AC voltage command values Vpn* (seeFIG.5).

The voltage command values Vpn* (VpnU*, VpnV*, VpnW*) are referred to as the third voltage command values in the present disclosure.

The positive-negative balance control unit600outputs the circulation current command values Izpn* (Izpna*, Izpnb*) as AC components for the respective phases, and the AC voltage command values Vpn* (VpnU*, VpnV*, VpnW*) as DC components for the respective phases.

The voltage command value calculation unit700receives the DC voltage command value Vdc*, the first voltage command values Vac* (Vacu*, Vacv*, Vacw*) outputted from the current control unit300, the second voltage command values Vz* (VzU*, VzV*, VzW*) outputted from the phase balance control unit500, and the third voltage command values Vpn* outputted from the positive-negative balance control unit600, and calculates voltage command values Vref for the respective arms by the following Expression (11).

That is, voltage command values Vrefpu, Vrefpv, Vrefpw, Vrefnu, Vrefnv, and Vrefnw for the U-phase positive arm, the V-phase positive arm, the W-phase positive arm, the U-phase negative arm, the V-phase negative arm, and the W-phase negative arm are calculated by the following Expression (11).
Vrefpu=Vdc*+VzU*−Vacu*−VpnU*
Vrefpv=Vdc*+VzV*−Vacv*−VpnV*
Vrefpw=Vdc*+VzW*−Vacw*−VpnW*
Vrefnu=Vdc*+VzU*+Vacu*+VpnU*
Vrefnv=Vdc*+VzV*+Vacv*+VpnV*
Vrefnw=Vdc*+VzW*+Vacw*+VpnW*Expression (11)

The voltage command values Vrefpu, Vrefpv, Vrefpw, Vrefnu, Vrefnv, and Vrefnw for the U-phase positive arm, the V-phase positive arm, the W-phase positive arm, the U-phase negative arm, the V-phase negative arm, and the W-phase negative arm calculated as described above, are each divided by a value corresponding to the voltage total value of the DC capacitors15included in the corresponding one of the U-phase positive arm, the V-phase positive arm, the W-phase positive arm, the U-phase negative arm, the V-phase negative arm, and the W-phase negative arm, thus generating arm modulation commands Krefpu, Krefpv, Krefpw, Krefnu, Krefnv, and Krefnw for the U-phase positive arm, the V-phase positive arm, the W-phase positive arm, the U-phase negative arm, the V-phase negative arm, and the W-phase negative arm.

The arm modulation commands Kref (Krefpu, Krefpv, Krefpw, Krefnu, Krefnv, Krefnw) which are calculation results of the voltage command value calculation unit700are outputted to the gate signal generation unit900.

Next, the configuration and operation of the individual balance control unit800in embodiment 1 will be described.

As shown inFIG.5, the individual balance control unit800receives the average-value corresponding values (third representative values) VcapXX_av (Vcappu_av, Vcapnu_av, Vcappv_av, Vcapnv_av, Vcappw_av, Vcapnw_av) of the DC capacitor voltages in the respective arms outputted from the third representative value calculation unit610of the positive-negative balance control unit600, the DC capacitor voltages Vcap of all the converter cells10, the AC currents Iu, Iv, Iw detected by the current sensor30, and the DC current Idc detected by the current sensor60, and performs control so that the DC capacitor voltage detection value Vcap of each converter cell10follows the DC capacitor voltage average-value corresponding value (third representative value) VcapXX_av* in the corresponding arm.

FIG.11shows a block diagram of the individual balance control unit800, and in particular, is a block diagram showing a control unit810corresponding to one converter cell10in the individual balance control unit800. Here, the control unit810shown inFIG.11corresponds to one converter cell10A (seeFIG.1) in the U-phase positive arm.

The individual balance control unit800is composed of collection of control units810whose number is the same as the number of all the converter cells10and which one-by-one correspond to the respective converter cells10.

With reference toFIG.11, control in the individual balance control unit800will be described using one converter cell10A in the U-phase positive arm as a representative example.

The individual balance control unit800uses active power for controlling the DC capacitor voltage of each converter cell10. By changing the output voltage of each converter cell10in accordance with current flowing through each converter cell10, active power of the converter cell10is changed, whereby it becomes possible to suppress variation of the DC capacitor voltage.

In each arm voltage and the DC capacitor voltage of each converter cell, there are an oscillation component with the same frequency as the grid frequency and an oscillation component with a frequency that is two times the grid frequency. Therefore, a deviation between the average-value corresponding value (third representative value) Vcappu_av* of the DC capacitor voltages in the U-phase positive arm and the DC capacitor voltage Vcappu1of one converter cell10in the U-phase positive arm is filtered through a filter820.

Then, a value obtained by filtering, through the filter820, the voltage deviation between the average-value corresponding value (third representative value) Vcappu_av* of the DC capacitor voltages in the U-phase positive arm and the DC capacitor voltage Vcappu1of the converter cell10, is subjected to proportional control by a controller830.

Further, the output value of the controller830is multiplied by the sum of DC current (⅓×Idc) and AC current (½×Iu) for each phase, at a multiplier850, whereby a voltage component having the same phase as current of each converter cell10is calculated, thus generating an individual control voltage command ΔVsm_pu1. Then, the individual control voltage command ΔVsm_pu1is divided by a value corresponding to the DC capacitor voltage Vcappu1, whereby an individual control modulation command ΔKsm_pu1is generated.

As described above, in the individual balance control unit800, with respect to the converter cells10in the U-phase positive arm9pu, the average-value corresponding value Vcappu_av* of the DC capacitor voltages in the U-phase positive arm, the DC capacitor voltages Vcappu1, . . . , Vcappuk of the converter cells10in the U-phase positive arm, the AC current (½×Iu), and the DC current (⅓×Idc) are inputted, and individual control modulation commands ΔKsm_pu1, . . . , ΔKsm_puk are calculated and outputted.

In addition, with respect to the converter cells10in the U-phase negative arm9nu, the average-value corresponding value Vcapnu_av* of the DC capacitor voltages in the U-phase negative arm, the DC capacitor voltages Vcapnu1, . . . , Vcapnuk of the converter cells10in the U-phase negative arm, the AC current (½×Iu), and the DC current (⅓Idc) are inputted, and individual control modulation commands ΔKsm_nu1, . . . , ΔKsm_nuk are calculated and outputted.

In addition, with respect to the converter cells10in the V-phase positive arm9pv, the average-value corresponding value Vcappv_av* of the DC capacitor voltages in the V-phase positive arm, the DC capacitor voltages Vcappv1, . . . , Vcappvk of the converter cells10in the V-phase positive arm, the AC current (½×Iv), and the DC current (⅓×Idc) are inputted, and individual control modulation commands ΔKsm_pv1, . . . , ΔKsm_pvk are calculated and outputted.

In addition, with respect to the converter cells10in the V-phase negative arm9nv, the average-value corresponding value Vcapnv_av* of the DC capacitor voltages in the V-phase negative arm, the DC capacitor voltages Vcapnv1, . . . , Vcapnvk of the converter cells10in the V-phase negative arm, the AC current (½×Iv), and the DC current (⅓×Idc) are inputted, and individual control modulation commands ΔKsm_nv1, . . . , ΔKsm_nvk are calculated and outputted.

In addition, with respect to the converter cells10in the W-phase positive arm9pw, the average-value corresponding value Vcappw_av* of the DC capacitor voltages in the W-phase positive arm, the DC capacitor voltages Vcappw1, . . . , Vcappwk of the converter cells10in the W-phase positive arm, the AC current (½×Iw), and the DC current (⅓×Idc) are inputted, and individual control modulation commands ΔKsm_pw1, . . . , ΔKsm_pwk are calculated and outputted.

In addition, with respect to the converter cells10in the W-phase negative arm9nw, the average-value corresponding value Vcapnw_av* of the DC capacitor voltages in the W-phase negative arm, the DC capacitor voltages Vcapnw1, . . . , Vcapnwk of the converter cells10in the W-phase negative arm, the AC current (½×Iw), and the DC current (⅓×Idc) are inputted, and individual control modulation commands ΔKsm_nw1, . . . , ΔKsm_nwk are calculated and outputted.

When the individual control modulation commands ΔKsm_pu1, . . . , ΔKsm_nwk are collectively mentioned, they are referred to as individual control modulation commands ΔKsm.

The individual control modulation commands ΔKsm (ΔKsm_pu1, . . . , ΔKsm_nwk) calculated by the individual balance control unit800are outputted to the gate signal generation unit900.

The gate signal generation unit900synthesizes the arm modulation commands Kref (Krefpu, Krefnu, Krefpv, Krefnv, Krefpw, Krefnw) outputted from the voltage command value calculation unit700and the individual control modulation commands ΔKsm (ΔKsm_nw1, . . . , ΔKsm_nwk) outputted from the individual balance control unit800, to obtain modulation commands for the respective converter cells10.

That is, with respect to the respective converter cells10in the U-phase positive arm9pu, the arm modulation command Krefpu and each individual control modulation command ΔKsm_pu1, . . . , ΔKsm_puk are synthesized.

In addition, with respect to the respective converter cells10in the U-phase negative arm9nu, the arm modulation command Krefnu and each individual control modulation command ΔKsm_nu1, . . . , ΔKsm_nuk are synthesized.

In addition, with respect to the respective converter cells10in the V-phase positive arm9pv, the arm modulation command Krefpv and each individual control modulation command ΔKsm_pv1, . . . , ΔKsm_pvk are synthesized.

In addition, with respect to the respective converter cells10in the V-phase negative arm9nv, the arm modulation command Krefnv and each individual control modulation command ΔKsm_nv1, . . . , ΔKsm_nvk are synthesized.

In addition, with respect to the respective converter cells10in the W-phase positive arm9pw, the arm modulation command Krefpw and each individual control modulation command ΔKsm_pw1, . . . , ΔKsm_pwk are synthesized.

In addition, with respect to the respective converter cells10in the W-phase negative arm9nw, the arm modulation command Krefnw and each individual control modulation command ΔKsm_nw1, . . . , ΔKsm_nwk are synthesized.

The gate signal generation unit900generates gate signals for performing pulse width modulation (PWM) control for the semiconductor switching elements12of the respective converter cells10, on the basis of comparison between a carrier wave and the synthesized modulation command for each converter cell10, for example.

Effects of Embodiment 1

As described above, according to embodiment 1, the control device includesa first voltage control unit which performs control so that a first representative value which is an average-value corresponding value of DC capacitor voltages of all the converter cells follows a predetermined overall voltage command value, to generate a first voltage command value,a phase balance control unit which performs control so that a second representative value which is an average-value corresponding value of the DC capacitor voltages of the converter cells in the leg circuit for each phase follows the first representative value, to generate a second voltage command value,a positive-negative balance control unit which performs control so that a deviation of third representative values which are average-value corresponding values of the DC capacitor voltages of the converter cells in the positive arm and the negative arm of the leg circuit for each phase becomes zero between the positive arm and the negative arm of the leg circuit for each phase, to generate a third voltage command value,a voltage command value calculation unit which generates an arm modulation command for each arm on the basis of the first voltage command value, the second voltage command value, and the third voltage command value,an individual balance control unit which performs control so that the DC capacitor voltages of all the converter cells follow the third representative values, to generate individual modulation commands for the respective converter cells, anda gate signal generation unit which generates drive signals for the semiconductor switching elements on the basis of the arm modulation commands and the individual modulation commands.

Thus, voltages of the DC capacitors of all the converter cells are kept within a certain range and the DC capacitor voltages of the converter cells are averaged, whereby overvoltage of each converter cell can be prevented.

In addition, the first voltage control unit includesan overall voltage control unit which generates an active current command value so that the first representative value follows the overall voltage command value, anda current control unit which generates the first voltage command value so that active current of the power converter follows the active current command value and reactive current of the power converter follows a reactive current command value.

Thus, the voltages of the DC capacitors of all the converter cells are kept within a certain range, whereby overvoltage of each converter cell can be prevented.

In addition, the individual balance control unit generates the individual modulation commands on the basis of deviations between the third representative values and the DC capacitor voltages of all the converter cells, AC current of the AC grid, and DC current of the DC grid.

Thus, DC capacitor voltages of the converter cells can be averaged, whereby overvoltage of each converter cell can be prevented.

In addition, the positive-negative balance control unit performs control so that the deviation of the third representative values becomes zero between the positive arm and the negative arm of the leg circuit for each phase, to generate a circulation current command value for positive-negative balance, andthe phase balance control unit generates a circulation current command value for phase balance so that each second representative value follows the first representative value, and generates the second voltage command value so that circulation current circulating among the phases of the leg circuits follows a value obtained by adding the circulation current command value for phase balance and the circulation current command value for positive-negative balance outputted from the positive-negative balance control unit.

Thus, the DC capacitor voltages of the converter cells can be averaged among the phases and between the arms, whereby overvoltage of each converter cell can be prevented.

In addition, the phase balance control unit includes filters for removing a frequency that is two times a grid frequency of the AC grid, from the second representative values.

Thus, the DC capacitor voltages of the converter cells are kept within a certain range, whereby overvoltage of each converter cell can be prevented.

In addition, the positive-negative balance control unit includes filters for removing the same frequency as a grid frequency of the AC grid and a frequency that is two times the grid frequency of the AC grid, from the third representative values.

Thus, the DC capacitor voltages of the converter cells are kept within a certain range, whereby overvoltage of each converter cell can be prevented.

In addition, the individual balance control unit includes filters for removing the same frequency as a grid frequency of the AC grid and a frequency that is two times the grid frequency of the AC grid, from deviations between the DC capacitor voltages of all the converter cells and the third representative values.

Thus, the DC capacitor voltages of the converter cells are kept within a certain range, whereby overvoltage of each converter cell can be prevented.

In addition, the gate signal generation unit generates gate signals for the semiconductor switching elements of the respective converter cells in accordance with modulation commands obtained by adding the arm modulation commands and the individual modulation commands.

Thus, the DC capacitor voltages of the converter cells are kept within a certain range and the DC capacitor voltages of the converter cells are averaged, whereby overvoltage of the converter cells can be prevented.

FIG.12is a block diagram showing a control device of a power conversion device according to embodiment 2.

A control device7A in embodiment 2 includes the first voltage control unit400including the overall voltage control unit200and the current control unit300, the phase balance control unit500, the positive-negative balance control unit600, the voltage command value calculation unit700, an individual balance control unit800A, and the gate signal generation unit900.

As compared to the control device7in embodiment 1, the control device7A in embodiment 2 is different in the configuration of the individual balance control unit800A and is different in that the individual balance control unit800A receives the modulation commands Kref outputted from the voltage command value calculation unit700.

Control operations other than that in the individual balance control unit800A are the same as those in embodiment 1, and therefore the description thereof is omitted.

FIG.13shows a block diagram of the individual balance control unit800A, and in particular, is a block diagram showing a control unit810A corresponding to one converter cell10in the individual balance control unit800A. Here, the control unit810A shown inFIG.13corresponds to one converter cell10A (seeFIG.1) in the U-phase positive arm.

With reference toFIG.11, control in the individual balance control unit800A will be described using one converter cell10A in the U-phase positive arm as a representative example.

As in the individual balance control unit810in embodiment 1, in the individual balance control unit810A in embodiment 2, a value obtained by filtering, through the filter820, the voltage deviation between the average-value corresponding value (third representative value) Vcappu_av* of the DC capacitor voltages in the U-phase positive arm and the DC capacitor voltage Vcappu1of the converter cell10, is subjected to proportional control by the controller830. Then, the output value of the controller830is multiplied by the sum of the DC current (⅓×Idc) and the AC current (½×Iu) for each phase, at the multiplier850, whereby a voltage component having the same phase as current of each converter cell10is calculated, thus generating the individual control voltage command ΔVsm_pu1. Then, the individual control voltage command ΔVsm_pu1is divided by a value corresponding to the DC capacitor voltage Vcappu1, whereby the individual control modulation command ΔKsm_pu1is generated.

Meanwhile, the individual balance control unit810A receives the arm modulation command Krefpu for the U-phase positive arm outputted from the voltage command value calculation unit700. Then, the arm modulation command Krefpu and 0 are compared by a comparator861, and the arm modulation command Krefpu and 1 are compared by a comparator862. Then, if 0≤Krefpu≤1 is satisfied, a logical conjunction circuit863outputs 1, and if Krefpu<0 or Krefpu>1 is satisfied, the logical conjunction circuit863outputs 0. The output value of the multiplier850is multiplied by the output value of the logical conjunction circuit863, at a multiplier870.

That is, if the arm modulation command Krefpu for the U-phase positive arm is smaller than 0 or greater than 1 (Krefpu<0 or Krefpu>1), output of the logical conjunction circuit863becomes 0, so that 0 is multiplied at the multiplier870. Thus, if the modulation command Krefpu is smaller than 0 and greater than 1, 0 is outputted as the individual control arm modulation command ΔKsm.

Therefore, if the arm modulation command outputted from the voltage command value calculation unit700is smaller than 0 or greater than 1, output from the individual balance control unit800A becomes zero, so that, in the gate signal generation unit900, the arm modulation command Kref (Krefup, Krefun, Krefvp, Krefvn, Krefwp, Krefnw) outputted from the voltage command value calculation unit700becomes the modulation command for each converter cell10. Then, the gate signal generation unit900generates signals for performing PWM control for the gates of the semiconductor switching elements12of the respective converter cells10on the basis of the arm modulation commands Kref.

As described above, according to embodiment 2, the same effects as in embodiment 1 can be obtained.

In addition, the individual balance control unit makes each individual modulation command be zero in accordance with a value of the arm modulation command generated by the voltage command value calculation unit.

Thus, only in a necessary case in accordance with the value of the arm modulation command generated by the voltage command value calculation unit, the individual balance control is made valid, whereby switching loss in the semiconductor switching elements of the converter cells can be reduced while the DC capacitor voltages can be stabilized in a certain range.

DESCRIPTION OF THE REFERENCE CHARACTERS