Low cost high voltage power FET and fabrication

A power field effect transistor (FET) is disclosed which is fabricated in as few as six photolithographic steps and which is capable of switching current with a high voltage drain potential (e.g., up to about 50 volts). In a described n-channel metal oxide semiconductor (NMOS) embodiment, a drain node includes an n-well region with a shallow junction gradient, such that the depletion region between the n-well and the substrate is wider than 1 micron. Extra photolithographic steps are avoided using blanket ion implantation for threshold adjust and lightly doped drain (LDD) implants. A modified embodiment provides an extension of the LDD region partially under the gate for a longer operating life.

This is a non-provisional of Application No. 61/086,382 filed Aug. 5, 2008, the entirety of which is incorporated herein by reference.

BACKGROUND

This invention relates to the field of integrated circuits; and, more particularly, to low cost, high voltage power field effect transistors (FETs) and their fabrication.

Integrated circuits which interface to analog inputs and outputs (I/Os) and perform specialized functions, such as controlling microelectromechanical systems (MEMS) modules, heaters, valves, relays and other applications, are often built using low cost fabrication process sequences. Photolithographic operations are typically the most costly and complex fabrication process steps involved in building an IC, so a common aspect of low cost fabrication process sequences is a simplified device architecture built with a minimal number of photolithographic steps. Components in ICs built on a simplified device architecture have limited complexity and are not capable of operating at high voltages, for example above 20 volts, so that IC design for specialized functions with high voltage I/Os involves a trade-off between performance and fabrication cost. Accordingly, there is a need for integrated circuits built with few photolithographic steps and capable of controlling higher voltage inputs and outputs.

SUMMARY

The invention provides a low cost, high voltage power field effect transistor (FET) and methods for its fabrication.

In a described example embodiment, an integrated circuit is provided that has an n-channel metal oxide semiconductor (MOS) power FET fabricated with just a small number of photolithographic operations and which can modulate drain current when 30 volts is applied to a drain contact. As described further below, the example MOS power FET embodiment has an n-well with a shallow junction gradient formed in its drain area to provide a wide depletion region which significantly reduces a voltage drop across the gate dielectric. Fabrication with few photolithographic operations is achieved by performing blanket threshold adjust and lightly doped drain (LDD) ion implant processes, without photoresist patterns to block the implants from some regions. A modified example provide an LDD extension in an additional photolithographic step to provide a longer operating lifetime.

An advantage of the instant invention is that functions currently requiring complex integrated circuits may be performed by simpler integrated circuits incorporating the principles of the invention, with attendant cost savings.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

The principles of the invention are described with reference to an example embodiment of an integrated circuit including a power field effect transistor (FET) fabricated with minimal photolithographic operations. The example embodiment provides an FET in the form of a low cost metal oxide semiconductor (MOS) transistor fabricated with as few as six photolithographic steps through contacts, with a doped well having a shallow junction gradient extending into a drain region, a blanket threshold adjust ion implantation step and a blanket lightly doped drain (LDD) ion implantation step, which can operate at high voltage (e.g., around 50 volts) drain potential. A modified embodiment provides the metal oxide semiconductor (MOS) transistor fabricated built with an additional photolithographic step, with the doped well having a shallow junction gradient extending into a drain region and a blanket threshold adjust ion implantation step, which can operate at high voltage (e.g., 50 volts) drain potential for an extended period of time (typically, more than 1000 hours).

FIGS. 1A-1Jillustrate steps in a method of fabricating an integrated circuit including a MOS transistor. For purposes of brevity, only the steps in fabrication of a device including an n-channel MOS (NMOS) transistor are described; however, those skilled in the art to which the invention relates will appreciate that by applying opposite doping (that is, by applying p-type doping where n-type doping is used, and vice versa) the same principles can be applied to the fabrication of an integrated circuit including a p-channel MOS (PMOS) transistor (or both NMOS and PMOS transistors).

FIG. 1Ashows a device100fabricated on a silicon substrate102which may, for example, be a p-type single crystal wafer having an electrical resistivity of 0.5 to 100 ohm-cm. A first sacrificial oxide layer104, such as a 5 to 40 nanometer thick layer of thermally grown silicon dioxide, is formed on a top surface of the substrate102to protect the top surface during subsequent processing. A silicon nitride layer106, such as a 40 to 100 nanometer thick layer of silicon nitride deposited by low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD) processes, is formed over the oxide layer104for the purpose of masking regions defined for active areas in the device100during later field oxide growth. A photoresist layer108is formed and patterned over the silicon nitride layer106using known photolithographic techniques to define regions for a doped well in a drain area of the example MOS transistor. For the example NMOS transistor, the well takes the form of an well doped with an n-type dopant (n-well). An ion implant110of n-type dopants (such as phosphorus, and possibly arsenic and/or antimony, conducted at, for example, a total dose of 1×1012to 1×1014atoms/cm2at one or more energies of 50 and 600 keV) is performed through the silicon nitride layer106and the oxide layer104into regions of the substrate left uncovered by the patterned photoresist layer108, to form an implanted n-well region112that extends to a depth into the substrate102of, e.g., 100 to 1,000 nanometers. After completion of the ion implant110, the photoresist layer108is removed, such as by exposing it to an oxygen containing plasma, followed by a wet clean-up to remove organic residue from the top surface of the silicon nitride layer106.

FIG. 1Bshows the device100after formation of field oxide isolation elements114in the substrate102in regions where the silicon nitride layer106has been removed. The placement of the field oxide isolation elements114can be accomplished, for example, by forming and patterning another layer of photoresist (not shown) over the silicon nitride layer and etching the silicon nitride layer106from regions left uncovered by the patterned photoresist. The field oxide isolation elements114can then be formed by, for example, growing silicon dioxide thermally on the surface of the silicon substrate in regions where the silicon nitride layer106has been removed. The silicon dioxide may, for example, be grown to a thickness of 500 to 200 nanometers in a furnace with an oxygen or steam ambient. During thermal growth of the field oxide isolation elements, the dopants from ion implantation110diffuse in the substrate102to form a diffused n-well region116, which extends from the top surface of the substrate102to a depth of about 500 to 2000 nanometers. A junction gradient between the diffused n-well region116and the substrate102is more than one micron wide. It is advantageous for the field oxide isolation elements114to be formed by a method which also diffuses the dopants from ion implantation110to form the diffused n-well region116with the desired depth and junction gradient. The remainder of the silicon nitride layer106may be removed following the formation of the field oxide isolation elements114.

FIG. 1Cshows the device100during a threshold adjust ion implant operation120. An optional second sacrificial oxide layer118, such as silicon dioxide 10 to 50 nanometers thick, is formed on a top surface of the substrate102to augment any existing oxide for the purpose of protecting the top surface of the substrate102during subsequent processing. In contrast to the implant110, the illustrated ion implant operation120is performed as a blanket implantation of the relevant part of the substrate102, without using a patterned photoresist layer to block portions of the substrate102from dopant implantation. For the described NMOS transistor implementation, p-type dopants (such as boron, and possibly gallium and/or indium, implanted at an energy of 10 to 70 keV at a total dose of 1×1011to 1×1013atoms/cm2) may be implanted to form the implanted threshold adjust dopants122to a depth of 10 to 200 nanometers below the top surface of the substrate102. (The depiction of dopant atoms implanted into field oxide isolation elements114is omitted inFIG. 1Cfor clarity.) Performing the MOS transistor threshold adjust ion implant120without a patterned photoresist is advantageous because it reduces fabrication cost.

FIG. 1Dshows the device100after formation of a transistor gate structure. Previous oxide is removed from the surface of the substrate102, such as by etching in a dilute solution of hydrofluoric acid (HF). A gate dielectric layer124(such as 10 to 30 nanometers thick layer of silicon dioxide, nitrogen-doped silicon dioxide, silicon oxynitride, hafnium oxide, layers of silicon dioxide and silicon nitride, or other insulating material) is formed on the substrate102and a gate electrode layer126(such as a 100 and 1000 nanometers thick layer of deposited polysilicon) is formed over the gate dielectric layer124. The gate electrode layer126and gate dielectric layer124are then patterned into the transistor gate structure such as by etching through a patterned photoresist layer to remove at least the portion of the material (e.g., polysilicon) of gate electrode layer126outside a pattern-defined gate structure region. After forming the gate structure, a conformal dielectric layer128, such as a 10 to 50 nanometers thick layer of silicon dioxide, is formed on exposed surfaces of the gate structure and the substrate102, such as by exposing the device100to an oxidizing ambient at a temperature above 800° C. The conformal dielectric layer128may, of course, also be formed of other materials and by other processes.

FIG. 1Eshows the device100during a lightly doped drain (LDD) ion implantation operation130. Again, as with the ion implant120, the ion implant130is performed as a blanket implantation of the relevant part of the substrate102, without using a patterned photoresist layer to block portion of the substrate from dopant implantation. For the described NMOS transistor implementation, n-type dopants (such as phosphorus, and possibly arsenic and/or antimony, implanted at an energy of 50 to 250 keV at a total dose of 3×1011to 1×1014atoms/cm2) may be implanted to form n-type LDD implanted regions132to a depth of 50 to 200 nanometers below the top surface of the substrate102. The implantation of n-type dopants into the LDD implanted regions132serves to counterdope the prior implantation of p-type dopants in the same regions by the threshold adjust implant120. The patterned gate structure serves to mask against counterdoping of the prior dopants (shown by x's inFIG. 1E) in the channel region below the dielectric124. Performing the LDD ion implant operation130without an additional photoresist pattern is advantageous because it further reduces the fabrication cost.

FIG. 1Fshows the device100during an n-type source and drain (NSD) ion implantation operation136. A photoresist layer134is formed and patterned over dielectric layer128using photolithographic methods to define a source region adjacent to one side of the gate structure124/126, and a drain region spaced, e.g., about 1 to 2 microns away from the other side of the gate structure124/126. For the described NMOS transistor implementation, n-type dopants (such as phosphorus, and possibly arsenic and/or antimony, implanted at one or more energies of 30 to 250 keV at a total dose of 3×1014to 3×1016atoms/cm2) may be implanted into the substrate102through the dielectric layer128to form n-type source/drain (NSD) implanted regions138extending to a depth of 50 to 200 nanometers from the top surface of the substrate102. The patterned photoresist layer134is removed after completing the NSD ion implant136, such as by exposing it to an oxygen containing plasma, followed by a wet clean-up to remove organic residue from the top surface of the dielectric layer128.

FIG. 1Gshows the device100during a p-type source and drain (PSD) ion implantation operation142. A photoresist layer140is formed and patterned over dielectric layer128using photolithographic methods to define a substrate contact area. For the described NMOS transistor implementation, p-type dopants (such as boron, e.g., in the form BF2, and possibly gallium and/or indium, implanted at one or more energies of 10 to 100 keV at a total dose between 3×1014and 3×1016atoms/cm2) may be implanted into the substrate102through the dielectric layer128to form p-type substrate contact implanted regions144extending to a depth of 50 to 200 nanometers from the top surface of the substrate102. The patterned photoresist layer140is removed after completing the PSD implant142ion implanting the second set of p-type dopants142, such as by exposing it to an oxygen containing plasma, followed by a wet clean-up to remove organic residue from the top surface of the dielectric layer128.

FIG. 1Hshows the device100after formation of a pre-metal dielectric (PMD) layer154, such as a layer of silicon dioxide, phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG), deposited by plasma-enhanced chemical vapor deposition (PECVD) to a thickness of about 100 to 2000 nanometers. The PMD layer154may include an optional PMD liner, such as, e.g., a silicon nitride or silicon dioxide PMD liner deposited by PECVD to a thicken, e.g., by a chemical-mechanical polishing (CMP) process, to facilitate interconnect formation. An optional PMD cap layer, such as, e.g., a 10 to 100 nanometer thick layer of hard material like silicon nitride, silicon carbide nitride and/or silicon carbide, may be formed over the PMD layer154. Formation of the PMD layer154may be performed in a thermal process (such as, e.g., at a temperature of 800° C. to 950° C. for about 20 to 120 minutes) which acts to also activate the n-type dopants implanted by implants130,136and the p-type dopants implanted by implant142to form an n-type diffused LDD region146, an n-type diffused source region148, an n-type diffused drain region150, and a p-type diffused substrate contact region152. In an alternative embodiment, a separate anneal may be performed to activate the dopants before formation of the PMD layer154.

FIG. 1Ishows the device100after contact holes156are formed in the PMD layer154. The holes154may be formed by depositing and patterning a photoresist layer over the PMD layer154by photolithographic methods to define contact hole regions, then etching uncovered portions of the PMD layer154and dielectric layer128to expose the n-type diffused drain region150, the n-type diffused source region148and the p-type diffused substrate contact region152. The patterned photoresist layer is removed after forming the contact holes156, such as by exposing it to an oxygen containing plasma, followed by a wet clean-up to remove organic residue from the top surface of the PMD layer154.

FIG. 1Jshows the device100after formation of conductive contacts156,158,160within the contact holes156. A layer of conductive material (such as titanium, tungsten, titanium tungsten, or other metal or conductive material which exhibits good adhesion to the PMD layer154) is formed over the PMD layer154and within the contact holes154by physical vapor deposition (PVD) or other material deposition process. The conductive material is then selectively removed from over the PMD layer154by physical or chemical methods, leaving the conductive material in the contact holes154to form a drain contact156, a source contact158, a substrate contact160, and a gate contact162.

In a mode of operation of the NMOS transistor fabricated as described, a ground potential may be applied to the source contact158and substrate contact160; a gate potential between ground potential and 5 to 10 volts (depending on the thickness the gate dielectric layer124) may be applied to the gate contact; and a drain potential as high as 50 volts may be applied to the drain contact156. This results in the formation of a depletion region at the junction between the diffused n-well region116and the p-type substrate102, which reduces a potential across the gate dielectric layer124. Under application of the voltage differential between the drain and source, the depletion region extends beyond the LDD region146toward the gate region below the gate structure124/126. Current flows between the drain contact156and the source contact158via the n-type diffused drain region150, the n-type diffused LDD region146, an inversion region formed under the gate dielectric layer124(which is desirably modulated by the gate potential), and the n-type diffused source region148.

FIGS. 2A-2Cillustrate steps in a method of fabricating an integrated circuit including a MOS transistor according to a modified form200of the example embodiment already discussed in connection with the description of the fabrication of device100above. The modified device200uses photolithography and selective implantation, rather than a blanket implantation (like implant130used for device100and described above with reference toFIG. 1E), to form an LDD drain region that extends partially under the transistor gate structure. Again, for purposes of brevity, only the steps in fabrication of a device including an n-channel MOS (NMOS) transistor are described, with the realization that those skilled in the art to which the invention relates will readily understand that by using opposite doping the same principles can be applied to the fabrication of an integrated circuit including a p-channel MOS (PMOS) transistor (or both NMOS and PMOS transistors).FIG. 2Ashows the modified device200at a stage of fabrication corresponding to the stage of fabrication shown and described with reference toFIG. 1Cfor the device100. The steps for the fabrication of the example modified device200up to the stage illustrated inFIG. 2Amay be the same as those described for the example device100, so are not repeated.

FIG. 2Ashows the device200(like the previously described device100inFIG. 1C) during a threshold adjust ion implant operation210. Field oxide isolation elements204have already been formed as previously described, and an optional second sacrificial oxide layer208, such as silicon dioxide to a thickness of 10 to 50 nanometers, has also been formed on a top surface of a substrate202. A diffused n-well region206has also been formed in a drain area of the substrate202in the previously described manner. As with implant120, the illustrated implant210is performed as a blanket implantation of the relevant part of the substrate202, without using a patterned photoresist layer to block portions of the substrate202from dopant implantation. As before, for the NMOS transistor implementation, p-type dopants (such as boron, and possibly gallium and/or indium, implanted at an energy between 10 to 70 keV at a total dose of 1×1011to 1×1013atoms/cm2) may be implanted to form the implanted threshold adjust dopants212to a depth of 10 to 200 nanometers below the top surface of the substrate202.

FIG. 2Bshows the device200during an ion implantation operation216to form a lightly doped drain (LDD) region having an extension (into the gate region) not formed in the fabrication of the previously described device100. A photoresist layer214is formed and patterned over the oxide layer208to define a region for an extended LDD region in the drain area of the example MOS transistor. The illustrated photoresist layer shows an opening for the extended LDD region implant only in the drain area; however, it will be understood that the photoresist layer214may be also be patterned to define an optional LDD region for the source area if desired, simultaneously with providing the extended LDD region for the drain area. An ion implant216of n-type dopants216(such as phosphorus, and possibly arsenic and/or antimony, conducted at, for example, an energy between 50 and 250 keV at a total dose between 3×1011and 1×1014atoms/cm2) may be implanted into the substrate202through the oxide layer208to form an n-type extended LDD implanted region218to a depth of 50 to 200 nanometers from the top surface of the substrate202. The implantation of n-type dopants into the LDD implanted region218serves to counterdope the prior implantation of p-type dopants212in the same region by the threshold adjust implant210. The photoresist layer214serves to mask against counterdoping of the prior dopants212(shown by x's inFIG. 2B) in the other regions below the oxide layer208. Although a blanket implant such as implant130ofFIG. 1Ecould also be performed in the fabrication of the modified device200, it is contemplated that the usual procedure would be to perform the selective implantation216without also performing such a blanket implant. The photoresist layer214may, of course, also be patterned to define LDD areas for other transistors on the same IC.

FIG. 2Cshows the device200at a subsequent stage of fabrication, similar to that depicted inFIG. 1Jfor device100, with other features added as previously described with reference to FIGS.1D and1F-1J in connection with device100. As described previously for gate dielectric layer124and gate electrode layer126of device100, a gate dielectric layer220and a gate electrode layer222have been formed and patterned to provide a transistor gate structure, and a conformal dielectric layer224similar to dielectric layer128has been formed over the gate structure and portions of the substrate202. In departure from the fabrication of device100, however, a diffused extended LDD region226(provided by thermal activation of the extended LDD region218) is present in the device200shown inFIG. 2C, and a portion of the patterned gate structure overlaps a portion of the diffused LDD extension region226(e.g., by 0.2 to 1 micron in the illustrated implementation).FIG. 2Calso depicts an n-type diffused drain region228, a p-type diffused contact region232and an n-type diffused source region230which may be formed as previously described for the formations of n-type diffused drain region150, p-type diffused contact region152and n-type diffused source region148.FIG. 2Calso depicts a pre-metal deposition (PMD) layer234and contacts236,238,240and242which may be formed as previously described for the formations of PMD layer154and contacts156,158,160and162.

In a mode of operation of the NMOS transistor of the modified embodiment, similarly to the mode of operation described previously in connection with device100, a ground potential may be applied to the source contact238and the substrate contact240; a gate potential between ground potential and 5 to 10 volts (depending on the thickness the gate dielectric layer220) may be applied to the gate contact; and a drain potential as high as 50 volts may be applied to the drain contact236. This results in formation of a depletion region at the junction between the diffused n-well region206and the p-type substrate202, which reduces a potential across the gate dielectric layer220. Under application of operating voltage, the depletion region will extend under the gate structure beyond the diffused extended LDD region226, thereby enabling the transistor to accommodate the application of high voltages for short periods. Current then flows between the drain contact236and the source contact238via the n-type diffused drain region228, the n-type diffused LDD region226, an inversion region formed under the gate dielectric layer220(which is desirably modulated by the gate potential), and the n-type diffused source region230. The configuration of the instant embodiment in which a portion of the MOS transistor gate structure220/222overlaps a portion of the LDD diffused region226is advantageous because it may increase an operational lifetime of the power FET by a factor of 100.

Those skilled in the art to which the invention relates will appreciate that many other embodiments and variations of embodiments are possible within the scope of the claimed invention.