MEMORY DEVICE WITH PERIPHERAL CIRCUITRY WHICH EXTENDS UNDER A BACK END MEMORY ARRAY

Techniques and mechanisms for accessing memory arrays which are formed in a back end of line (BEOL) of an integrated circuit (IC) die. In an embodiment, a differential sense amplifier of the IC die is coupled to a first array and a second array via a first bit line and a second bit line, respectively. The first bit line and the second bit line extend from a first level of BEOL memory arrays, toward a front end of line (FEOL) of the IC die, on opposite respective sides of first array, wherein the differential sense amplifier is in a footprint region for the first memory array. In another embodiment, a word line driver circuit comprises a two stage charger-discharger circuit which mitigates hot carrier injection.

BACKGROUND

1. Technical Field

This disclosure generally relates to memory devices and more particularly, but not exclusively, to peripheral circuitry which is to provide access to a back end memory array.

2. Background Art

Various types of embedded memory are monolithically integrated with a host IC (i.e., both memory and the host IC fabricated on the same chip). For embedded memory applications, reducing the overall memory array footprint helps achieve larger memories and/or reduce device cost. One form of embedded memory is embedded dynamic random access memory (eDRAM). The architecture of eDRAM is typically based on a 1T-1C cell that includes a cell “write” or “select” transistor and a storage capacitor.

The back end of line (BEOL) of an integrated circuit fabrication process is the portion of IC fabrication where individual semiconductor devices (whether embedded memory or logic transistors) are interconnected to one another with electrically conductive features such as metal interconnect traces (lines) within a given metallization level and metal-filled conductive vias between multiple metallization levels. For some memory devices, a transistor of a memory cell is fabricated in the back-end-of-line (BEOL), with the channel material being a thin film semiconductor material rather than the monocrystalline semiconductor (e.g., Si) typical of front end of line (FEOL) transistors. For some eDRAM, the capacitor is also fabricated in the BEOL and electrically coupled to the transistor through one or more metal interconnect layers formed in the BEOL.

Typically, memory cells implemented in a BEOL are interconnected to peripheral circuitry (e.g., address decoders) which is implemented with CMOS logic fabricated in the FEOL. The interconnection however becomes much more difficult if more than one level of memory cells is implemented in the BEOL. For example, where an IC chip includes two or more memory cell levels, the set of data lines (e.g., 1,024 bit lines) associated with each memory cell array level would need to be routed down to periphery circuitry. However, routing this many lines down from two, three, or more memory array levels would require significant area.

As successive generations of embedded memory technologies continue to increase in number, variety, and capability, there is expected to be an increasing premium placed on improvements to the space efficiency of these circuit architectures.

DETAILED DESCRIPTION

Embodiments discussed herein variously provide techniques and mechanisms for accessing memory arrays which are formed in a back end of line of an integrated circuit (IC) die. The technologies described herein may be implemented in one or more electronic devices. Non-limiting examples of electronic devices that may utilize the technologies described herein include any kind of mobile device and/or stationary device, such as cameras, cell phones, computer terminals, desktop computers, electronic readers, facsimile machines, kiosks, laptop computers, netbook computers, notebook computers, internet devices, payment terminals, personal digital assistants, media players and/or recorders, servers (e.g., blade server, rack mount server, combinations thereof, etc.), set-top boxes, smart phones, tablet personal computers, ultra-mobile personal computers, wired telephones, combinations thereof, and the like. More generally, the technologies described herein may be employed in any of a variety of electronic devices including an IC die having formed therein multiple back end memory arrays.

It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.

As used throughout this description, and in the claims, a list of items joined by the term “at least one of” or “one or more of” can mean any combination of the listed terms. For example, the phrase “at least one of A, B or C” can mean A; B; C; A and B; A and C; B and C; or A, B and C. It is pointed out that those elements of a figure having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

In addition, the various elements of combinatorial logic and sequential logic discussed in the present disclosure may pertain both to physical structures (such as AND gates, OR gates, or XOR gates), or to synthesized or otherwise optimized collections of devices implementing the logical structures that are Boolean equivalents of the logic under discussion.

Here, multiple non-silicon semiconductor material layers may be stacked within a single fin structure. The multiple non-silicon semiconductor material layers may include one or more “P-type” layers that are suitable (e.g., offer higher hole mobility than silicon) for P-type transistors. The multiple non-silicon semiconductor material layers may further include one or more one or more “N-type” layers that are suitable (e.g., offer higher electron mobility than silicon) for N-type transistors. The multiple non-silicon semiconductor material layers may further include one or more intervening layers separating the N-type from the P-type layers. The intervening layers may be at least partially sacrificial, for example to allow one or more of a gate, source, or drain to wrap completely around a channel region of one or more of the N-type and P-type transistors. The multiple non-silicon semiconductor material layers may be fabricated, at least in part, with self-aligned techniques such that a stacked CMOS device may include both a high-mobility N-type and P-type transistor with a footprint of a single transistor.

FIG.1shows features of an IC structure100to provide access to multiple back end memory arrays according to an embodiment. The IC structure100illustrates one example of an embodiment wherein memory arrays are variously formed in a back end of line (BEOL) of an IC die, and wherein circuitry to implement an access of the memory arrays (referred to herein as “peripheral circuitry”), comprises transistors and/or other active circuit components in a front end of line (FEOL) of the IC die. The peripheral circuitry includes (for example) a differential sense amplifier which is coupled to receive signals each from a respective one of two memory arrays—e.g., wherein the differential sense amplifier extends in a footprint region under one of said two memory arrays.

In the example embodiment shown, a front end of line (FEOL) of IC structure100comprises an active layer102which includes active circuit components (e.g., including any of various combinations of transistors, diodes and/or the like) fabricated in and/or on a semiconductor substrate101. Peripheral circuitry105of IC structure100includes a plurality of MOSFETs and/or other transistor circuits in active layer102—e.g., wherein some or all such transistor circuits each comprise a respective channel including a monocrystalline semiconductor.

In some embodiments, a back end of line (BEOL) of IC structure100comprises an alternating arrangement of dielectric material layers110, and dielectric material layers111, wherein interconnect structures variously extend in dielectric material layers110,111to provide connectivity with and/or between circuits of active layer102and/or memory arrays of the BEOL. In one such embodiment, peripheral circuitry105further includes one or more layers of interconnect metallization132embedded in various ones of dielectric material layers110,111. In the exemplary embodiment illustrated, peripheral circuitry105includes metal-one (M1), metal-two (M2) and metal-three (M3) interconnect metallization layers, but may include a different number of interconnect metallization layers in other embodiments.

One or more levels of memory arrays—e.g., including the illustrative memory array levels120shown—are variously formed in different respective vertical (z-axis) regions in the BEOL. By way of illustration and not limitation, one or more eDRAM memory arrays comprise one transistor, one capacitor (1T1C) memory cells, including the cells122variously denoted by dashed lines inFIG.1. For example, a given memory cell array level120comprises thin film transistors (TFTs)121, wherein a given memory array in that memory cell array level120includes a 1T1C memory cell122comprising one TFT121as a cell select transistor. Another of TFTs121is operable as an array level select transistor128, in an embodiment. In still another embodiment, array level select transistor128is implemented in peripheral circuitry105(e.g., with structures of active layer102. As illustrated with IC structure100and the legend150, individual ones of cell select TFTs121include a gate terminal coupled to a word line156, while individual ones of level select transistors128include a gate terminal coupled to a level select line158.

As shown, some or all TFTs121of a given memory cell array level120employ a semiconductor material154, which is separated from word line156or level select line158by a gate dielectric. Additionally or alternatively, word line156and array level select line158are in the same metallization level with TFTs121being “bottom-gate” devices with semiconductor material154having been deposited over word lines156and array level select line158. In other embodiments, TFTs121instead are top-gate devices, multi-gate devices (e.g., having both a top-gate and a bottom-gate), or sidewall-gated devices (e.g., a finFET) as embodiments herein are not limited in this respect.

Within each of the 1T1C memory cells122is a respective capacitor126which, for example, is above a corresponding cell select transistor124. In the illustrated example, there is no capacitor126over array level select transistor128. Alternatively, a dummy capacitor may be present over array level select transistor128if the dummy capacitor does not hinder interconnection of array level select transistor128.

As shown inFIG.1, interconnect metallization from peripheral circuitry105extends up through multiple levels of metallization and couples to any of various bit line structures130each for a respective one of the one or more array levels120. An array level select transistor128facilitates access to a corresponding one or more memory arrays via routing between any number of array levels120and peripheral circuitry105. In other embodiments, in the absence of array level select transistor128, a separate route to peripheral circuitry105would be required for every bit line of every memory cell array level.

In various embodiments, a given bit line structure130comprises a global bit line portion and a level-specific local bit line portion. For example, a local bit line portion of said bit line structure130is within the same metallization level as the global bit line portion, wherein the bit line structure130is coupled to one terminal contact152of an array level select transistor128.

Although the BEOL of IC structure100is shown as comprising multiple array levels120, in other embodiments, the BEOL comprises only one such array level120. Additionally or alternatively, a given array level120comprises multiple memory arrays, in some embodiments—e.g., wherein said multiple arrays are each to be accessed via different respective word lines and different respective bit lines.

As detailed herein, some embodiments facilitate improved space efficiency of a back end memory architecture by providing bit line routing and/or word line routing which enables one or more peripheral circuit components to be positioned, at least in part, in a “footprint area” which is directly under one or more memory arrays that are to be accessed with said one or more peripheral circuit components.

For example, such one or more peripheral circuit components comprise a differential sense amplifier. In one such embodiment, the differential sense amplifier is coupled to a bit line which facilitates access to one memory array, and is further coupled to another bit line which facilitates access to a different memory array. Such a differential sense amplifier provides functionality to compare the respective voltages on the two bit lines—e.g., during a read operation—to determine a data value stored in a corresponding memory cell.

FIG.2shows features of an IC device200to operate multiple memory arrays of a back end according to an embodiment. IC device200illustrates one example of an embodiment which comprises “back end” memory arrays—i.e., memory arrays which are formed in a BEOL of an IC die—and peripheral circuitry to provide access to said back end memory arrays. The peripheral circuitry includes a differential sense amplifier circuit which is coupled to communicate with at least two such memory arrays. A FEOL of such an IC die comprises an active layer including transistors and/or other active circuit components of the differential sense amplifier—e.g., wherein some or all of the differential sense amplifier circuit is located in a footprint region under one or more of the at least two memory arrays. In various embodiments, IC device200provides functionality such as that of IC structure100.

As shown inFIG.2, IC device200comprises back end memory arrays210,220which each comprise respective memory cells that are arranged in rows and columns. For a given one of memory arrays210,220, respective bit lines and respective word lines variously facilitate access to the memory cells thereof. A given bit line extends along a corresponding column, and across rows, of the given memory array, wherein a given word line extends along a corresponding row, and across columns, of that given memory array. In various embodiments illustrated herein, a given column of a memory array (and a corresponding bit line to access said column) extends in a direction along the y-axis shown, whereas a given row of the memory array (and a corresponding word line to access said row) extends in another direction along the x-axis shown.

In the illustrative embodiment shown, array210comprises memory cells211athrough211d(referred to collectively as memory cells211). For example, a first column of array210comprises cells211a,211b, and a second column of array210comprises cells211c,211d, wherein the first column and the second column are accessed with bit lines213,215(respectively). Furthermore, a first row of array210comprises cells211a,211c, and a second row of array210comprises cells211b,211d, wherein the first row and the second row are accessed with word lines212,214(respectively). Although a simplified 2×2 memory array210is shown for illustrative purposes, array210is to typically further comprise one or more other rows (not shown) which, for example, are between the first row and the second row. Additionally or alternatively, array210further comprises one or more other columns (not shown) which, for example, are between the first column and the second column.

Memory array210extends in an array area217(for brevity, sometimes referred to herein simply as an “area”) of a horizontal (x-y) plane—e.g., wherein area217is defined by a maximum horizontal range of memory cells211. In an embodiment, first sides of area217(the first sides opposite each other) are formed by different respective ones of an upper most row of array210or a lower most row of array210. Furthermore, second sides of area217(the second sides opposite each other) are formed by different respective ones of a leftmost column of array210or a rightmost column of array210. Accordingly, memory array210corresponds to a respective footprint region (or simply “footprint”) which is vertically under the array area217, and which is defined by a periphery of area217. In an embodiment, the footprint region for array210comprises a horizontal footprint area250which (for example) is at or under an active layer of IC device200.

Similarly, array220comprises memory cells221athrough221d(referred to collectively as memory cells221). The BEOL comprises bit lines223,225which are to enable access to respective columns of memory cells221—e.g., wherein bit lines223,225provide functionality similar to that of bit lines213,215. Furthermore, word lines222,224are to enable access to respective rows of memory cells221—e.g., wherein word lines222,224provide functionality similar to that of word lines212,214. An array area227for memory array220is defined (for example) by a horizontal range of memory cells221, wherein a periphery of area227defines a respective footprint region under memory array220. Similar to array210, the footprint region for array220comprises a horizontal footprint area260which is at or under the active layer. An area270between footprint areas250,260corresponds to a separation between areas217,227—e.g., wherein the separation is equal to a distance y1 along the y-axis shown.

Memory cells211and memory cells221comprise 1T1C memory cells, for example. In an embodiment, peripheral circuitry of IC device200comprises a differential sense amplifier252which is coupled to bit lines213,223, which facilitate access to memory array210and memory array220(respectively). For example, differential sense amplifier252comprises circuitry to receive respective signals via bit lines213,223, and to compare the voltages thereof to determine a data value stored in a memory cell of one of the arrays210,220. In various embodiments, differential sense amplifier252includes circuitry adapted from any of various conventional differential sense amplifier architectures, which are not detailed herein to avoid obscuring features of said embodiments.

Some embodiments improve space efficiency of a back end memory architecture by positioning differential sense amplifier252at least partially (for example, entirely) in or on one of the footprint areas250,260which are under the arrays210,220that are accessed via differential sense amplifier252. For example, bit lines213,223comprise respective vertical (z-axis) interconnect structures216,226which each extend from the array layer which includes arrays210,220toward an underlying region in which differential sense amplifier252extends. In some illustrative embodiments, interconnect structures216,226variously extend from the array layer—e.g., through the array layer—on opposite respective sides of area217(for example). In one such embodiment, interconnect structure226extends vertically between areas217,227—i.e., over an area270which is between footprint areas250,260.

In providing such routing of interconnect structures216,226past opposite respective sides of area217, some embodiments facilitate an arrangement wherein differential sense amplifier252extends at least partially under the footprint area250under area217(or in an alternative embodiment, at least partially under the footprint area260under area227). In turn, such an arrangement of differential sense amplifier252enables a horizontal distance y1 between areas217,227which is relatively small, as compared to existing architectures. By way of illustration and not limitation, distance y1 is less than 6 microns (μm), in various embodiments—e.g., wherein distance y1 is less than 3 μm, and—in some embodiments, less than 2 μm.

FIG.3shows features of an IC device300to operate back end memory arrays at various respective array levels of according to an embodiment. IC device300illustrates one example of an embodiment wherein peripheral circuitry is coupled to facilitate access to memory arrays in various levels of a BEOL, wherein a differential sense amplifier (and/or other components of the peripheral circuitry) extends in a footprint region under two or more such memory arrays. In various embodiments, IC device300provides functionality of one of IC structures100,200.

As shown inFIG.3, a BEOL of IC device300comprises memory arrays arranged in multiple array levels comprising a first level and a second level over the first level. A FEOL of IC device300comprises peripheral circuitry to variously provide access to said memory arrays. In the example embodiment shown, such peripheral circuitry comprises a differential sense amplifier352—which (for example) provides functionality such as that of differential sense amplifier252—and both level selection circuitry354, level selection circuitry356to variously support an accessing of the first level and the second level.

In the example embodiment shown, the first array level comprises arrays310,320which (for example) correspond functionally to arrays210,220. Array310comprises memory cells311athrough311d(referred to collectively as memory cells311) which are variously accessed via bit lines313,315and word lines312,314. Array320comprises memory cells321athrough321d(referred to collectively as memory cells321) which are variously accessed via bit lines323,325and word lines322,324.

Furthermore, the second array level comprises arrays330,340which (for example) are positioned vertically over arrays310,320(respectively). Array330comprises memory cells331athrough331d(referred to collectively as memory cells331) which are variously accessed via bit lines333,335and word lines332,334. Array340comprises memory cells341athrough341d(referred to collectively as memory cells341) which are variously accessed via bit lines343,345and word lines342,344. In various embodiments, some or all of arrays310,320,330,340each comprise one or more other rows and/or one or more other columns (not shown).

An array area317for memory array310is defined (for example) by a horizontal range of memory cells311, wherein a periphery of area317defines a respective footprint region under memory array310. Similar to array210, the footprint region for array310comprises a horizontal footprint area350which is at or under the active layer. Similarly, a periphery of an array area327for memory array320defines another footprint region which comprises a horizontal footprint area360at or under the active layer.

In the embodiment shown, another array area337for memory array330is defined (for example) by a horizontal range of memory cells331, and a further array area347for memory array340is defined by a horizontal range of memory cells341. In various embodiments, array310extends at least partially in a footprint region for array330, and/or array320extends at least partially in a footprint region for array340. An area370between footprint areas350,360corresponds to a separation between areas317,327(and/or between areas337,347)—e.g., wherein the separation is equal to a distance y2 along the y-axis shown.

Some of all of memory cell311,321,331,341comprise 1T1C memory cells, for example. In an embodiment, peripheral circuitry of IC device300comprises level selection circuitry354, and level selection circuitry356, and further comprises a differential sense amplifier352which is variously coupled to bit lines316,326,36,346via level selection circuitry354and level selection circuitry356.

Level selection circuitry354comprises one or more switches, multiplexer circuits, demultiplexer circuits and/or any of various types of circuitry suitable to selectively enable communication between differential sense amplifier352and either of arrays320,340(via bit lines323,343, respectively). Similarly, level selection circuitry356also comprises any of various types of circuitry which are suitable to selectively enable communication between differential sense amplifier352and either of arrays310,330(via bit lines313,333, respectively). In some embodiments, control signaling (not shown) to variously operate differential sense amplifier352, level selection circuitry354and level selection circuitry356is generated, for example, using digital control circuitry which—for example—is adapted from conventional memory device designs and techniques. Such conventional designs and techniques are not detailed herein to avoid obscuring certain features of such embodiments. The peripheral circuitry of IC device300further comprises word line driver circuits (not shown) to variously communicate with the various word lines of arrays310,320,330,340.

Various embodiments provide efficient space utilization wherein some or all of differential sense amplifier352, level selection circuitry354, and level selection circuitry356extend partially or entirely in or on one of the footprint areas350,360. By way of illustration and not limitation, bit lines313,333comprise respective vertical (z-axis) interconnect structures316,336which each extend from arrays310,330(respectively) toward a coupling with level selection circuitry356at the underlying active layer. Similarly, bit lines323,343comprise respective vertical interconnect structures326,346which each extend from arrays320,340(respectively) toward a coupling with level selection circuitry354at the underlying active layer. In one such embodiment, interconnect structures316,326extend from (e.g., through) the first array level, on opposite respective sides of area317, toward the active layer. Furthermore, interconnect structures336,346extend from (e.g., through) the second array level, on opposite respective sides of area337—and also, through the first array level on opposite respective sides of area317—toward the active layer.

In providing such routing of interconnect structures316,326,336,346relative to areas317,327,337,347, some embodiments facilitate an arrangement wherein differential sense amplifier352, level selection circuitry354, and level selection circuitry356extend at least partially under the footprint area350under area317(or in an alternative embodiment, at least partially under the footprint area360under area327). In turn, such an arrangement of differential sense amplifier352enables a horizontal distance y2 between areas317,327which is relatively small, as compared to existing architectures.

FIG.4shows features of an IC device400to access memory arrays in various back end layers according to an embodiment. IC device400illustrates one example of an embodiment wherein word line driver circuitry is in a footprint area of one or more backend memory arrays. In various embodiments, IC device400provides functionality of one of IC structures100,200,300.

As shown inFIG.4, a BEOL of IC device400comprises memory arrays arranged in multiple array levels comprising a first level and a second level over the first level. A FEOL of IC device400comprises peripheral circuitry to variously provide access to said memory arrays. In the example embodiment shown, such peripheral circuitry comprises word line driver circuits460,462to variously access memory arrays of different respective array levels of a BEOL. In some embodiments, the peripheral circuitry further comprises one or more differential sense amplifiers, and level selection circuitry and/or other components (not shown) which are formed in or on an active layer.

In the example embodiment shown, the first array level and the second array level comprise—respectively—arrays410,430which (for example) correspond functionally to arrays310,330. Array410comprises memory cells411athrough411d(referred to collectively as memory cells411) which are variously accessed via bit lines413,415and word lines412,414. Similarly, array430comprises memory cells431athrough431d(referred to collectively as memory cells431) which are variously accessed via bit lines433,435and word lines432,434. In various embodiments, some or all of arrays410,430each comprise one or more other rows and/or one or more other columns (not shown).

An array area417for memory array410is defined (for example) by a horizontal range of memory cells411, wherein a periphery of area417defines a respective footprint region under memory array410. The footprint region for array410comprises a horizontal footprint area450which is at or under the active layer. In an embodiment, a periphery of an array area437for memory array430defines a footprint region which overlaps (and for example, includes) the footprint region for array410.

Various embodiments provide efficient space utilization wherein some or all of word line driver circuit460and word line driver circuit462extend, partially or entirely, in or on one of the footprint area450which is under both of arrays410,430. By way of illustration and not limitation, word lines412,414comprise respective vertical (z-axis) interconnect structures416,418which variously extend from array410toward a coupling with word line driver circuit460at the underlying active layer.

Similarly, word lines432,434comprise respective vertical interconnect structures436,438which variously extend from array430toward a coupling with word line driver circuit462at the underlying active layer. In some embodiments, interconnect structures416,418extend from the first array level—e.g., from within a periphery of area417—toward the active layer. Additionally or alternatively, interconnect structures436,438extend from (e.g., through) the second array level—and also, through the first array level—toward the active layer. In one such embodiment, interconnect structures436,438extend through the second array level in a region which is outside of the periphery of area437. In providing such routing of interconnect structures416,418,436,438relative to areas417,437—and also, relative to word line driver circuit460and word line driver circuit462—some embodiment variously enable a space efficient positioning of word line driver circuit460and word line driver circuit462in footprint area450.

FIG.5shows features of an IC die500to operate multiple memory arrays of a back end according to an embodiment. IC die500illustrates one example of an embodiment wherein each of multiple differential sense amplifier circuits is in a footprint of a respective plurality of back end memory arrays which (in turn) are to be accesses by that differential sense amplifier circuit. IC die500is shown in a cross-sectional top view of an active layer such as active layer102. In various embodiments, IC die500includes features of IC structure100, and/or one of IC devices200,300, for example.

IC die500comprises various peripheral circuit structures, which are shown inFIG.5relative to various footprint areas510-513that each correspond to (and are in a footprint region of) a different respective one or more back end memory arrays. For example, peripheral circuitry of IC die500comprises column access circuitry COLIO1520which provides differential sense amplifier circuitry to access one or more memory arrays each corresponding to a respective one of area510or area511. In some embodiments, column access circuitry COLIO1520further comprises level selection circuitry with which the differential sense amplifier is selectively access any of multiple array levels—e.g., wherein column access circuitry COLIO1520provides functionality of differential sense amplifier352, level selection circuitry354and level selection circuitry356. In various embodiments, column access circuitry such as COLIO1520further comprises one or more bit line write drivers and/or any of various other suitable circuitry to access a memory array via bit lines.

By way of illustration and not limitation, a differential sense amplifier of column access circuitry COLIO1520is coupled—e.g., via level selection circuitry—to two bit lines (not shown) which extend in the BEOL of IC die500, wherein the two bit lines are to access different respective memory arrays in the same array level. For example, the two bit lines extend from that array level on opposite respective sides of one such memory array—e.g., a first array which defines a footprint region comprising area510. In an embodiment, the two bit lines comprise a first bit line coupled to the first array, and a second bit line which is coupled to a second array which defines a footprint region comprising area511. Furthermore, the second bit line extends from the array level, toward the underlying active layer of IC die500, in a region which is between the first array and the second array.

Peripheral circuitry of IC die500further comprises column access circuitry COLIO2521which similarly includes sense amplifier circuitry—and, in some embodiments, level selection circuitry—to access memory arrays each corresponding to a respective one of area512or area513. A differential sense amplifier of column access circuitry COLIO2521is coupled—in some embodiments, via level selection circuitry—to two bit lines (not shown) which are to access different respective memory arrays in the same array level. The two bit lines extend from that array level on opposite respective sides of one such memory array—e.g., a third array which defines a footprint region comprising area512. For example, the two bit lines comprise a third bit line coupled to the third array, and a fourth bit line which is coupled to a fourth array which defines a footprint region comprising area513. In an embodiment, the fourth bit line extends from the array level, to the underlying active layer of IC die500, in a region which is between the third array and the fourth array.

In various embodiments, peripheral circuitry of IC die500further comprises word line driver circuitry WL1R524which is coupled to word lines which are to access a memory array, in a first array level, which corresponds to area510. Furthermore, word line driver circuitry WL1R526of IC die500is coupled to other word lines which are to access another memory array, also in the first array level, which corresponds to area512. In one such embodiment, word line driver circuitry WL1L525of IC die500is coupled to word lines which are to access another memory array, in the first array level, which corresponds to area511. Further still, word line driver circuitry WL1L527is coupled to word lines which are to access another memory array, in the first array level, which corresponds to area513.

By contrast, word line driver circuitry WL0R522of IC die500is variously coupled via word lines to access any of a first plurality of memory arrays in a second array level that, for example, is over the first array level. For example, one of the first plurality of memory arrays corresponds to area510, wherein another of the first plurality of memory arrays corresponds to area512. Furthermore, word line driver circuitry WL0L523of IC die500is variously coupled via word lines to access any of a second plurality of memory arrays in the second array level. In an embodiment, one of the second plurality of memory arrays corresponds to area511, and another of the second plurality of memory arrays corresponds to area513.

In various embodiments, some or all of the word line driver circuitry WL0R522, WL0L523, WL1R524, WL1L525, WL1R526, WL1L527extend at least in part outside of the footprint areas510-513for the memory arrays to be variously coupled via said word line circuitry. By way of illustration and not limitation, word line driver circuitry WL0R522, WL1R524, and WL1R526are arranged along a first line, in a region between areas510,512(and between column access circuitry COLIO1520and column access circuitry COLIO2521). By contrast, word line driver circuitry WL0L523, WL1L525, and WL1L527are arranged along a second line—parallel to the first line—in a region between areas511,513.

Although some embodiments are not limited in this regard, additional peripheral circuitry MISC528facilitates access to memory arrays each corresponding to a respective one of areas510,511. Similarly, additional peripheral circuitry MISC529facilitates access to memory arrays each corresponding to a respective one of areas512,513. In one example embodiment, MISC528and/or MISC528comprise timer circuitry, column control circuitry, and/or any of various other types of digital controller circuitry which facilitate operations to access the various back end memory arrays of IC die500—e.g., where such additional peripheral circuitry is adapted from conventional memory device architectures.

FIG.6shows features of an IC die600to variously access back end memory arrays according to an embodiment. IC die600illustrates one example of an embodiment wherein differential sense amplifier circuits and word line driver circuits variously extend each in a respective footprint area for a corresponding plurality of back end memory arrays. IC die600is shown in a cross-sectional top view of an active layer such as active layer102. In various embodiments, IC die600includes features of IC structure100, and/or one of IC devices200,300,400, for example.

IC die600comprises various peripheral circuit structures, which are shown inFIG.6relative to various footprint areas610-613that each correspond to (and are in a footprint region of) a different respective one or more back end memory arrays. For example, peripheral circuitry of IC die600comprises column access circuitry COLIO1620—e.g., corresponding functionally to column access circuitry COLIO1520—which is to access memory arrays each corresponding to a respective one of area610or area611. In an embodiment, coupling of column access circuitry COLIO1620to said memory arrays, via various bit lines, is similar the coupling of differential sense amplifier352, level selection circuitry354, and level selection circuitry356to arrays310,320,330,340.

Peripheral circuitry of IC die600further comprises column access circuitry COLIO2621—e.g., corresponding functionally to column access circuitry COLIO2521—which is to access memory arrays each corresponding to a respective one of area612or area613. In an embodiment, coupling of column access circuitry COLIO2621to said memory arrays, via various bit lines, is similar the coupling of differential sense amplifier352, level selection circuitry354, and level selection circuitry356to arrays310,320,330,340.

Peripheral circuitry of IC die600further comprises word line driver circuitry WL0t622which is variously coupled via word lines to access any of a first plurality of memory arrays in a first array level—e.g., wherein one of the first plurality of memory arrays corresponds to area610. In some embodiments, another of the first plurality of memory arrays corresponds to area612(or alternatively, to area611). Furthermore, word line driver circuitry WL1t624of IC die600is variously coupled via word lines to access any of a second plurality of memory arrays in a second array level that, for example, is over the first array level. For example, one of the second plurality of memory arrays corresponds to area610—e.g., wherein another of the second plurality of memory arrays corresponds to area612(or alternatively, to area611). In one example embodiment, word line driver circuitry WL0t622and word line driver circuitry WL1t624corresponds functionally to word line driver circuit460, and word line driver circuit462—e.g., word line driver circuitry WL1t624provides functionality of word line driver circuitry WL0R522, and wherein word line driver circuitry WL0t622provides functionality of both word line driver circuitry WL1R524and word line driver circuitry WL1R526.

Peripheral circuitry of IC die600further comprises word line driver circuitry WL0b623which is variously coupled via word lines to access any of a third plurality of memory arrays in the first array level—e.g., wherein one of the third plurality of memory arrays corresponds to area613. In some embodiments, another of the third plurality of memory arrays corresponds to area611(or alternatively, to area612). Furthermore, word line driver circuitry WL1b625of IC die600is variously coupled via word lines to access any of a fourth plurality of memory arrays in a second array level that, for example, is over the first array level. For example, one of the fourth plurality of memory arrays corresponds to area613—e.g., wherein another of the fourth plurality of memory arrays corresponds to area611(or alternatively, to area612). In one example embodiment, word line driver circuitry WL0b623and word line driver circuitry WL1b625corresponds functionally to word line driver circuit460, and word line driver circuit462—e.g., word line driver circuitry WL1b625provides functionality of word line driver circuitry WL0L523, and wherein word line driver circuitry WL0b623provides functionality of both word line driver circuitry WL1L525and word line driver circuitry WL1L527.

Although some embodiments are not limited in this regard, additional peripheral circuitry MISC628and MISC629variously facilitates access to the back end memory arrays which are variously over areas510-513. For example, circuitry MISC528and MISC529provide timer and/or other digital controller functionality such as that of circuitry MISC628and MISC629, in some embodiments.

In various embodiments, column access circuitry COLIO1620and column access circuitry COLIO2621—as well of some or all of the word line driver circuitry WL0t622, WL0b623, WL1t624, WL1b625, and some or all of the additional peripheral circuitry MISC628and MISC629—are each at least partially (in some embodiments, entirely) within a respective one of footprint areas610-613By way of illustration and not limitation, column access circuitry COLIO1620, word line driver circuitry WL0t622, WL1t624, and circuitry MISC628are variously arranged, along a first line, each in a respective one of areas610,612. By contrast, column access circuitry COLIO2621, word line driver circuitry WL0b623, WL1b625, and circuitry MISC629are variously arranged along a second line—parallel to the first line—each in a respective one of areas611,613. In one such embodiment, area610is separated from area612(and area611from area613) by a region MR615which extends into the BEOL—e.g., wherein region MR615accommodates routing of metallization structures which facilitate signal communication, across the first line and the second line, to a similar arrangement (not shown) of other memory resources similar to those shown inFIG.6.

FIG.7shows features of an IC die700to access memory arrays in various back end layers according to an embodiment. IC die700illustrates one example of an embodiment wherein peripheral circuitry is arranged in a tile area which forms one or more recess structures each to accommodate a portion of a respective other tail area. The peripheral circuitry includes a differential sense amplifier and word line driver circuitry, some or all of which are each in a respective footprint region for a corresponding one or more memory arrays. In various embodiments, IC die700includes features of IC structure100, and/or one of IC devices200,300,400,600, for example.

IC die700comprises various peripheral circuit structures, which are shown inFIG.7relative to various footprint areas710-713,732,733,750,751that each correspond to (and are in a footprint region of) a different respective one or more back end memory arrays. For example, peripheral circuitry of IC die700comprises column access circuitry COLIO1720, column access circuitry COLIO2721, various word line driver circuitry WL0t, WL0t722, WL0b723, WL1t724, WL1b725, circuitry MISC728, and circuitry MISC729which—for example—correspond functionally to column access circuitry COLIO1620, column access circuitry COLIO2621, word line driver circuitry WL0t622, word line driver circuitry WL0b623, word line driver circuitry WL1t624, word line driver circuitry WL1b625, circuitry MISC628, and circuitry MISC629.

In an embodiment, word line driver circuitry WL0t722and word line driver circuitry WL0b723are each to access respective memory arrays in a first array level—e.g., wherein word line driver circuitry WL1t724and word line driver circuitry WL1b725are each to access respective memory arrays in a second array level. In one such embodiment, the peripheral circuitry further comprises word line driver circuitry WL2t726which is variously coupled via word lines to access any of a first plurality of memory arrays in a third array level—e.g., wherein one of the first plurality of memory arrays corresponds to area710. In some embodiments, another of the first plurality of memory arrays corresponds to area712(or alternatively, to area711). Furthermore, word line driver circuitry WL2b727of IC die700is variously coupled via word lines to access any of a second plurality of memory arrays in the third array level. For example, one of the second plurality of memory arrays corresponds to area713—e.g., wherein another of the second plurality of memory arrays corresponds to area711(or alternatively, to area712). In one such embodiment, word line driver circuitry WL2t726extends at least partially outside of area710and/or word line driver circuitry WL2b727extends at least partially outside of area713.

In various embodiments, IC die700further comprises other back end memory arrays (in addition to those which variously correspond each to a respective one of areas710-713), and additional peripheral circuitry to facilitate access to said other back end memory arrays.

By way of illustration and not limitation, the first, second and third levels further comprise arrays which are each over a respective one of the illustrative footprint areas732,733shown. To access such arrays, IC die700further comprises column access circuitry COLIO2741, various word line driver circuitry WL0b743, WL1b745, WL2b747and circuitry MISC749, which—for example—correspond functionally to column access circuitry COLIO2721, word line driver circuitry WL0b723, WL1b725, WL2b727and circuitry MISC729.

Additionally or alternatively, the first, second and third levels further comprise other arrays which are each over a respective one of the illustrative footprint areas750,751shown. To access such other arrays, IC die700further comprises column access circuitry COLIO1760, and various word line driver circuitry WL1t764, WL2t766, which—for example—correspond functionally to column access circuitry COLIO1720, and word line driver circuitry WL1t724, WL2t726. In some embodiments, footprint areas of IC die700are variously separated from one other each by a respective one of regions MR715, MR735that each extend into the BEOL—e.g., wherein regions MR715, MR735have features of region MR615, for example.

In an embodiment a first tile area, at the active layer, has therein peripheral circuitry to access the memory arrays which variously correspond each to a respective one of areas710-713. Furthermore, a second tile area at the active layer has therein peripheral circuitry to access the memory arrays which variously correspond each to a respective one of areas732,733. Further still, a third tile area at the active layer has therein peripheral circuitry to access the memory arrays which variously correspond each to a respective one of areas750,751. In one such embodiment, the first, second and third tile areas each form a respective recess structure to accommodate a portion of some other one of the first, second and third tile areas. Such an arrangement of tile areas further facilitates improved space efficiency, as compared to existing back end memory device architectures.

FIG.8shows features of a word line driver800to facilitate communication via a word line according to an embodiment. The word line driver800illustrates one example of an embodiment which includes a circuit (referred to herein as a “charge-discharge circuit”) that is operable to increase or decrease a voltage at a word line, wherein a delay between two stages of the circuit mitigates hot carrier injection that would otherwise impact driver functionality in the long term. In various embodiments, word line driver800is implemented with IC structure100, with one of IC devices200,300,400, or with one of IC dies500,600,700.

As shown inFIG.8, word line driver800comprises a positive level shifter circuit (Lsp)820, a delay circuit (PDr)830and a NAND gate840that—together—illustrate one example of first circuitry which, based on a word line select signal810, is to selectively operate one type (e.g., p-type) of transistors of a charge-discharge circuit. Furthermore, word line driver800comprises a negative level shifter circuit (LSn)870, a delay circuit (PDf)880and a NOR gate890that—together—illustrate an example of second circuitry which, based on the same word line select signal810, is to selectively operate another type (e.g., n-type) of transistors of that charge-discharge circuit.

In various embodiments, the first circuitry generates a signal822based on select signal810, and further generates another signal842with a first delay and signal822. For example, positive level shifter circuit820applies a positive level shift to select signal810to generate signal822. In one such embodiment, select signal810uses a first voltage level and a second voltage level (less than the first voltage level) which are each to indicate a different respective logic state. By contrast, signal822uses a third voltage level and a fourth voltage level—e.g., instead of (respectively) the first voltage level and the second logic level. For example, the third voltage level is greater than both the fourth voltage level and the first voltage level. In an embodiment, delay circuit PDr830generates a signal832based on an application of the first delay to signal822—e.g., wherein NAND gate840generates signal842based on both of signals822,832.

Furthermore, the second circuitry generates a signal872based on select signal810, and further generates another signal842with a second delay and signal872. For example, negative level shifter circuit870applies a negative level shift to select signal810to generate signal872. In one such embodiment, signal872uses a fifth voltage level and a sixth voltage level to represent respective logic states—e.g., instead of (respectively) the first voltage level and the second voltage level of select signal810. For example, the sixth voltage level is less than both the fifth voltage level and the second voltage level. In an embodiment, delay circuit PDf880generates a signal882based on an application of the second delay to signal872—e.g., wherein NOR gate890generates signal892based on both of signals872,882.

In the example embodiment shown, the charge-discharge circuit of word line driver800comprises a stage860which is coupled to receive signals822,872, and another stage850which is coupled to receive signals842,892. Stages850,860are each coupled to a word line (WL)856that is to be driven with word line driver800. For example, stage860is operable to variously increase and/or decrease a voltage at word line856based on signals822,872. Alternatively or in addition, stage850is operable to variously increase and/or decrease the voltage at word line856based on signals842,892.

By way of illustration and not limitation, stage860comprises n-type transistors861,862which are coupled in series with each other between word line856and a node which is to provide a supply voltage V2. Stage860further comprises p-type transistors863,864which are coupled in series with each other between word line856and another node which is to provide a reference potential865(e.g., a ground voltage) that, for example, is less than the supply voltage V2.

Additionally or alternatively, stage850comprises p-type transistors851,852which are coupled in series with each other between word line856and a node which is to provide a supply voltage V1 (which, for example, is larger than supply voltage V2). Stage850further comprises n-type transistors853,854which are coupled in series with each other between word line856and another node which is to provide a reference potential855that, for example, is less than the reference potential865. In an illustrative scenario according to one embodiment, voltages V1, and V2 are 1.7V and 1.0 V, respectively—e.g., wherein reference potentials855,865are −0.8 V and 0 V, respectively. However, some or all such voltages are different, alternatively, according to implementation-specific details which are not limiting on various embodiments.

The n-type transistors861,862are coupled to operate responsive to signal872, whereas p-type transistors863,864are coupled to operate responsive to signal822. Furthermore, p-type transistor851is coupled to operate responsive to signal842, whereas n-type transistor854is coupled to operate responsive to signal892. Based on the delay factors variously applied with delay circuit PDr830and delay circuit PDf880, an increasing (or alternatively, a decreasing) of the voltage at word line WL856with stages850,860takes place in a multi-stage sequence including two stages which correspond to different respective voltage change rates. In providing a relatively small voltage change rate, followed by a relatively large voltage change rate, some embodiments prevent or otherwise mitigate hot carrier injection that would otherwise impact the long-term operation of a word line driver such as word line driver800.

FIG.9shows a timing diagram900illustrating operations of word line driver800according to one illustrative embodiment. More particularly, timing diagram900shows respective characteristics of signals810,822,832,842,872,882,892, and of word line856, over a period of time905during operation of word line driver800.

In an illustrative “word line fall” scenario according to one embodiment, p-type transistors863,864—during a period of time immediately leading up to the time t3 shown—are both off due to signal822, and word line856is at a relatively high voltage, since p-type transistor851is on. At time t3, signal810begins a transition910to a relatively low voltage, which in turn contributes to respective transitions of signals822,872. Responsive to these respective transitions of signals822,872, stage860begins decreasing a voltage at word line856at a relatively slow rate during the period from time t3 to time t4 (and similarly, from time t9 to time t10). Subsequently, at time t4, signal892begins to undergo respective delayed transition912based on the transition of signal810at time t3. Responsive to delayed transitions912, stage850begins decreasing the voltage at word line856at a relatively large rate, as compared to the rate during the period from time t3 to time t4.

In an illustrative “word line rise” scenario according to another embodiment, p-type transistors863,864—during a period of time immediately leading up to the time t6 shown—are both off due to signal822, and word line856is at a relatively low voltage, since n-type transistor854is on. At time t6, signal810begins a transition920to a relatively high voltage, which in turn contributes to respective transitions of signals822,872. Responsive to these respective transitions of signals822,872, stage860begins increasing a voltage at word line856at a relatively slow rate during the period from time t6 to time t7 (and similarly, from time t0 to time t1). Subsequently, at time t7, signal842begins to undergo respective delayed transition922based on the transition of signal810at time t6. Responsive to delayed transitions922, stage850begins increasing the voltage at word line856at a relatively large rate, as compared to the rate during the period from time t6 to time t7.

FIG.10illustrates a computer system or computing device1000(also referred to as device1000), wherein peripheral circuitry extends under, and is coupled to enable access to, multiple back end memory arrays, in accordance with some embodiments. It is pointed out that those elements ofFIG.10having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

In some embodiments, device1000represents an appropriate computing device, such as a computing tablet, a mobile phone or smart-phone, a laptop, a desktop, an Internet-of-Things (IOT) device, a server, a wearable device, a set-top box, a wireless-enabled e-reader, or the like. It will be understood that certain components are shown generally, and not all components of such a device are shown in device1000.

In an example, the device1000comprises a SoC (System-on-Chip)1001. An example boundary of the SOC1001is illustrated using dotted lines inFIG.10, with some example components being illustrated to be included within SOC1001—however, SOC1001may include any appropriate components of device1000.

In some embodiments, device1000includes processor1004. Processor1004can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, processing cores, or other processing means. The processing operations performed by processor1004include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, operations related to connecting computing device1000to another device, and/or the like. The processing operations may also include operations related to audio I/O and/or display I/O.

In some embodiments, processor1004includes multiple processing cores (also referred to as cores)1008a,1008b,1008c. Although merely three cores1008a,1008b,1008care illustrated inFIG.10, the processor1004may include any other appropriate number of processing cores, e.g., tens, or even hundreds of processing cores. Processor cores1008a,1008b,1008cmay be implemented on a single integrated circuit (IC) chip. Moreover, the chip may include one or more shared and/or private caches, buses or interconnections, graphics and/or memory controllers, or other components.

In some embodiments, processor1004includes cache1006. In an example, sections of cache1006may be dedicated to individual cores1008(e.g., a first section of cache1006dedicated to core1008a, a second section of cache1006dedicated to core1008b, and so on). In an example, one or more sections of cache1006may be shared among two or more of cores1008. Cache1006may be split in different levels, e.g., level 1 (L1) cache, level 2 (L2) cache, level 3 (L3) cache, etc.

In some embodiments, a given processor core (e.g., core1008a) may include a fetch unit to fetch instructions (including instructions with conditional branches) for execution by the core1008a. The instructions may be fetched from any storage devices such as the memory1030. Processor core1008amay also include a decode unit to decode the fetched instruction. For example, the decode unit may decode the fetched instruction into a plurality of micro-operations. Processor core1008amay include a schedule unit to perform various operations associated with storing decoded instructions. For example, the schedule unit may hold data from the decode unit until the instructions are ready for dispatch, e.g., until all source values of a decoded instruction become available. In one embodiment, the schedule unit may schedule and/or issue (or dispatch) decoded instructions to an execution unit for execution.

The execution unit may execute the dispatched instructions after they are decoded (e.g., by the decode unit) and dispatched (e.g., by the schedule unit). In an embodiment, the execution unit may include more than one execution unit (such as an imaging computational unit, a graphics computational unit, a general-purpose computational unit, etc.). The execution unit may also perform various arithmetic operations such as addition, subtraction, multiplication, and/or division, and may include one or more an arithmetic logic units (ALUs). In an embodiment, a co-processor (not shown) may perform various arithmetic operations in conjunction with the execution unit.

Further, an execution unit may execute instructions out-of-order. Hence, processor core1008a(for example) may be an out-of-order processor core in one embodiment. Processor core1008amay also include a retirement unit. The retirement unit may retire executed instructions after they are committed. In an embodiment, retirement of the executed instructions may result in processor state being committed from the execution of the instructions, physical registers used by the instructions being de-allocated, etc. The processor core1008amay also include a bus unit to enable communication between components of the processor core1008aand other components via one or more buses. Processor core1008amay also include one or more registers to store data accessed by various components of the core1008a(such as values related to assigned app priorities and/or sub-system states (modes) association.

In some embodiments, device1000comprises connectivity circuitries1031. For example, connectivity circuitries1031includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and/or software components (e.g., drivers, protocol stacks), e.g., to enable device1000to communicate with external devices. Device1000may be separate from the external devices, such as other computing devices, wireless access points or base stations, etc.

In an example, connectivity circuitries1031may include multiple different types of connectivity. To generalize, the connectivity circuitries1031may include cellular connectivity circuitries, wireless connectivity circuitries, etc. Cellular connectivity circuitries of connectivity circuitries1031refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, 3rd Generation Partnership Project (3GPP) Universal Mobile Telecommunications Systems (UMTS) system or variations or derivatives, 3GPP Long-Term Evolution (LTE) system or variations or derivatives, 3GPP LTE-Advanced (LTE-A) system or variations or derivatives, Fifth Generation (5G) wireless system or variations or derivatives, 5G mobile networks system or variations or derivatives, 5G New Radio (NR) system or variations or derivatives, or other cellular service standards. Wireless connectivity circuitries (or wireless interface) of the connectivity circuitries1031refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), and/or other wireless communication. In an example, connectivity circuitries1031may include a network interface, such as a wired or wireless interface, e.g., so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant.

In some embodiments, device1000comprises control hub1032, which represents hardware devices and/or software components related to interaction with one or more I/O devices. For example, processor1004may communicate with one or more of display1022, one or more peripheral devices1024, storage devices1028, one or more other external devices1029, etc., via control hub1032. Control hub1032may be a chipset, a Platform Control Hub (PCH), and/or the like.

For example, control hub1032illustrates one or more connection points for additional devices that connect to device1000, e.g., through which a user might interact with the system. For example, devices (e.g., devices1029) that can be attached to device1000include microphone devices, speaker or stereo systems, audio devices, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.

As mentioned above, control hub1032can interact with audio devices, display1022, etc. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of device1000. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display1022includes a touch screen, display1022also acts as an input device, which can be at least partially managed by control hub1032. There can also be additional buttons or switches on computing device1000to provide I/O functions managed by control hub1032. In one embodiment, control hub1032manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in device1000. The input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).

In some embodiments, control hub1032may couple to various devices using any appropriate communication protocol, e.g., PCIe (Peripheral Component Interconnect Express), USB (Universal Serial Bus), Thunderbolt, High Definition Multimedia Interface (HDMI), Firewire, etc.

In some embodiments, display1022represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with device1000. Display1022may include a display interface, a display screen, and/or hardware device used to provide a display to a user. In some embodiments, display1022includes a touch screen (or touch pad) device that provides both output and input to a user. In an example, display1022may communicate directly with the processor1004. Display1022can be one or more of an internal display device, as in a mobile electronic device or a laptop device or an external display device attached via a display interface (e.g., DisplayPort, etc.). In one embodiment display1022can be a head mounted display (HMD) such as a stereoscopic display device for use in virtual reality (VR) applications or augmented reality (AR) applications.

In some embodiments and although not illustrated in the figure, in addition to (or instead of) processor1004, device1000may include Graphics Processing Unit (GPU) comprising one or more graphics processing cores, which may control one or more aspects of displaying contents on display1022.

Control hub1032(or platform controller hub) may include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections, e.g., to peripheral devices1024.

It will be understood that device1000could both be a peripheral device to other computing devices, as well as have peripheral devices connected to it. Device1000may have a “docking” connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on device1000. Additionally, a docking connector can allow device1000to connect to certain peripherals that allow computing device1000to control content output, for example, to audiovisual or other systems.

In addition to a proprietary docking connector or other proprietary connection hardware, device1000can make peripheral connections via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.

In some embodiments, connectivity circuitries1031may be coupled to control hub1032, e.g., in addition to, or instead of, being coupled directly to the processor1004. In some embodiments, display1022may be coupled to control hub1032, e.g., in addition to, or instead of, being coupled directly to processor1004.

In some embodiments, device1000comprises memory1030coupled to processor1004via memory interface1034. Memory1030includes memory devices for storing information in device1000. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory device1030can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, flash memory device, phase-change memory device, or some other memory device having suitable performance to serve as process memory. In one embodiment, memory1030can operate as system memory for device1000, to store data and instructions for use when the one or more processors1004executes an application or process. Memory1030can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of device1000.

In some embodiments, device1000comprises temperature measurement circuitries1040, e.g., for measuring temperature of various components of device1000. In an example, temperature measurement circuitries1040may be embedded, or coupled or attached to various components, whose temperature are to be measured and monitored. For example, temperature measurement circuitries1040may measure temperature of (or within) one or more of cores1008a,1008b,1008c, voltage regulator1014, memory1030, a mother-board of SOC1001, and/or any appropriate component of device1000.

In some embodiments, device1000comprises power measurement circuitries1042, e.g., for measuring power consumed by one or more components of the device1000. In an example, in addition to, or instead of, measuring power, the power measurement circuitries1042may measure voltage and/or current. In an example, the power measurement circuitries1042may be embedded, or coupled or attached to various components, whose power, voltage, and/or current consumption are to be measured and monitored. For example, power measurement circuitries1042may measure power, current and/or voltage supplied by one or more voltage regulators1014, power supplied to SOC1001, power supplied to device1000, power consumed by processor1004(or any other component) of device1000, etc.

In some embodiments, device1000comprises one or more voltage regulator circuitries, generally referred to as voltage regulator (VR)1014. VR1014generates signals at appropriate voltage levels, which may be supplied to operate any appropriate components of the device1000. Merely as an example, VR1014is illustrated to be supplying signals to processor1004of device1000. In some embodiments, VR1014receives one or more Voltage Identification (VID) signals, and generates the voltage signal at an appropriate level, based on the VID signals. Various type of VRs may be utilized for the VR1014. For example, VR1014may include a “buck” VR, “boost” VR, a combination of buck and boost VRs, low dropout (LDO) regulators, switching DC-DC regulators, etc. Buck VR is generally used in power delivery applications in which an input voltage needs to be transformed to an output voltage in a ratio that is smaller than unity. Boost VR is generally used in power delivery applications in which an input voltage needs to be transformed to an output voltage in a ratio that is larger than unity. In some embodiments, each processor core has its own VR which is controlled by PCU1010a/band/or PMIC1012. In some embodiments, each core has a network of distributed LDOs to provide efficient control for power management. The LDOs can be digital, analog, or a combination of digital or analog LDOs.

In some embodiments, device1000comprises one or more clock generator circuitries, generally referred to as clock generator1016. Clock generator1016generates clock signals at appropriate frequency levels, which may be supplied to any appropriate components of device1000. Merely as an example, clock generator1016is illustrated to be supplying clock signals to processor1004of device1000. In some embodiments, clock generator1016receives one or more Frequency Identification (FID) signals, and generates the clock signals at an appropriate frequency, based on the FID signals.

In some embodiments, device1000comprises battery1018supplying power to various components of device1000. Merely as an example, battery1018is illustrated to be supplying power to processor1004. Although not illustrated in the figures, device1000may comprise a charging circuitry, e.g., to recharge the battery, based on Alternating Current (AC) power supply received from an AC adapter.

In some embodiments, device1000comprises Power Control Unit (PCU)1010(also referred to as Power Management Unit (PMU), Power Controller, etc.). In an example, some sections of PCU1010may be implemented by one or more processing cores1008, and these sections of PCU1010are symbolically illustrated using a dotted box and labelled PCU1010a. In an example, some other sections of PCU1010may be implemented outside the processing cores1008, and these sections of PCU1010are symbolically illustrated using a dotted box and labelled as PCU1010b. PCU1010may implement various power management operations for device1000. PCU1010may include hardware interfaces, hardware circuitries, connectors, registers, etc., as well as software components (e.g., drivers, protocol stacks), to implement various power management operations for device1000.

In some embodiments, device1000comprises Power Management Integrated Circuit (PMIC)1012, e.g., to implement various power management operations for device1000. In some embodiments, PMIC1012is a Reconfigurable Power Management ICs (RPMICs) and/or an IMVP (Intel® Mobile Voltage Positioning). In an example, the PMIC is within an IC chip separate from processor1004. The may implement various power management operations for device1000. PMIC1012may include hardware interfaces, hardware circuitries, connectors, registers, etc., as well as software components (e.g., drivers, protocol stacks), to implement various power management operations for device1000.

In an example, device1000comprises one or both PCU1010or PMIC1012. In an example, any one of PCU1010or PMIC1012may be absent in device1000, and hence, these components are illustrated using dotted lines.

Various power management operations of device1000may be performed by PCU1010, by PMIC1012, or by a combination of PCU1010and PMIC1012. For example, PCU1010and/or PMIC1012may select a power state (e.g., P-state) for various components of device1000. For example, PCU1010and/or PMIC1012may select a power state (e.g., in accordance with the ACPI (Advanced Configuration and Power Interface) specification) for various components of device1000. Merely as an example, PCU1010and/or PMIC1012may cause various components of the device1000to transition to a sleep state, to an active state, to an appropriate C state (e.g., CO state, or another appropriate C state, in accordance with the ACPI specification), etc. In an example, PCU1010and/or PMIC1012may control a voltage output by VR1014and/or a frequency of a clock signal output by the clock generator, e.g., by outputting the VID signal and/or the FID signal, respectively. In an example, PCU1010and/or PMIC1012may control battery power usage, charging of battery1018, and features related to power saving operation.

The clock generator1016can comprise a phase locked loop (PLL), frequency locked loop (FLL), or any suitable clock source. In some embodiments, each core of processor1004has its own clock source. As such, each core can operate at a frequency independent of the frequency of operation of the other core. In some embodiments, PCU1010and/or PMIC1012performs adaptive or dynamic frequency scaling or adjustment. For example, clock frequency of a processor core can be increased if the core is not operating at its maximum power consumption threshold or limit. In some embodiments, PCU1010and/or PMIC1012determines the operating condition of each core of a processor, and opportunistically adjusts frequency and/or power supply voltage of that core without the core clocking source (e.g., PLL of that core) losing lock when the PCU1010and/or PMIC1012determines that the core is operating below a target performance level. For example, if a core is drawing current from a power supply rail less than a total current allocated for that core or processor1004, then PCU1010and/or PMIC1012can temporarily increase the power draw for that core or processor1004(e.g., by increasing clock frequency and/or power supply voltage level) so that the core or processor1004can perform at a higher performance level. As such, voltage and/or frequency can be increased temporality for processor1004without violating product reliability.

In an example, PCU1010and/or PMIC1012may perform power management operations, e.g., based at least in part on receiving measurements from power measurement circuitries1042, temperature measurement circuitries1040, charge level of battery1018, and/or any other appropriate information that may be used for power management. To that end, PMIC1012is communicatively coupled to one or more sensors to sense/detect various values/variations in one or more factors having an effect on power/thermal behavior of the system/platform. Examples of the one or more factors include electrical current, voltage droop, temperature, operating frequency, operating voltage, power consumption, inter-core communication activity, etc. One or more of these sensors may be provided in physical proximity (and/or thermal contact/coupling) with one or more components or logic/IP blocks of a computing system. Additionally, sensor(s) may be directly coupled to PCU1010and/or PMIC1012in at least one embodiment to allow PCU1010and/or PMIC1012to manage processor core energy at least in part based on value(s) detected by one or more of the sensors.

Also illustrated is an example software stack of device1000(although not all elements of the software stack are illustrated). Merely as an example, processors1004may execute application programs1050, Operating System1052, one or more Power Management (PM) specific application programs (e.g., generically referred to as PM applications1058), and/or the like. PM applications1058may also be executed by the PCU1010and/or PMIC1012. OS1052may also include one or more PM applications1056a,1056b,1056c. The OS1052may also include various drivers1054a,1054b,1054c, etc., some of which may be specific for power management purposes. In some embodiments, device1000may further comprise a Basic Input/Output System (BIOS)1020. BIOS1020may communicate with OS1052(e.g., via one or more drivers1054), communicate with processors1004, etc.

For example, one or more of PM applications1058,1056, drivers1054, BIOS1020, etc. may be used to implement power management specific tasks, e.g., to control voltage and/or frequency of various components of device1000, to control wake-up state, sleep state, and/or any other appropriate power state of various components of device1000, control battery power usage, charging of the battery1018, features related to power saving operation, etc.

In various embodiments, one or more memory resources of device1000—e.g., including some or all memory resources of cache1006and/or memory1030—are provided with circuitry such as that of IC structure100, IC device200, IC device300, or IC device400. Additionally or alternatively, one or more memory resources of device1000are operated with peripheral circuitry which, for example, provides functionality of word line driver800.

In one or more first embodiments, an integrated circuit (IC) die comprises a first memory array comprising first dynamic random access memory (DRAM) cells, a second memory array comprising second DRAM cells, wherein a back end of line (BEOL) of the IC die comprises a first array level, and wherein the first memory array and the second memory array are each in the first array level, and a differential sense amplifier coupled to the first memory array and the second memory array via a first bit line and a second bit line, respectively, wherein the differential sense amplifier is to receive a first signal and a second signal via the first bit line and the second bit line, respectively, and generate, based on each of the first signal and the second signal, an output which indicates a bit value at one of the first DRAM cells or one of the second DRAM cells, wherein the first bit line and the second bit line extend from the first array level, toward a front end of line (FEOL) of the IC die, on opposite respective sides of first memory array, and wherein, at the FEOL, the differential sense amplifier is in a first footprint region corresponding to the first memory array.

In one or more second embodiments, further to the first embodiment, the IC die further comprises a third memory array comprising third DRAM cells, wherein the BEOL of the IC die comprises a second array level, and wherein the third memory array is in the second array level, and first level selection circuitry coupled between the differential sense amplifier and each of the first bit line and a third bit line, wherein the first level selection circuitry is coupled to the third memory array via the third bit line, and wherein the first level selection circuitry is to selectively couple the differential sense amplifier to either of the first array level or the second array level.

In one or more third embodiments, further to the second embodiment, the first level selection circuitry is in the first footprint region.

In one or more fourth embodiments, further to the second embodiment, the IC die further comprises a fourth memory array comprising fourth DRAM cells, wherein the fourth memory array is in the second array level, and second level selection circuitry coupled between the differential sense amplifier and each of the first bit line and a fourth bit line, wherein the second level selection circuitry is coupled to the fourth memory array via the fourth bit line, and wherein the second level selection circuitry is to selectively couple the differential sense amplifier to either of the first array level or the second array level.

In one or more fifth embodiments, further to the fourth embodiment, the first level selection circuitry and the second level selection circuitry are each in the first footprint region.

In one or more sixth embodiments, further to the second embodiment, the IC die further comprises a first word line driver circuit coupled to the second memory array via a first word line, and a second word line driver circuit coupled to the fourth memory array via a second word line, wherein the first word line driver circuit and the second word line driver circuit are each in a second footprint region corresponding to the second memory array.

In one or more seventh embodiments, further to the sixth embodiment, in the second footprint region, a portion of the first word line extends vertically from the first array level toward the FEOL, and wherein a portion of the second word line extends vertically past the first array level, and toward the FEOL, in a region which is outside of a periphery of the second memory array.

In one or more eighth embodiments, further to the sixth embodiment, first peripheral circuitry of the IC die is to access the first memory array, the second memory array, the third memory array and the fourth memory array, wherein the first peripheral circuitry is arranged in a first tile area of the FEOL, and wherein the tile area forms recess structures each at a respective one of opposite ends of the first tile area.

In one or more ninth embodiments, further to the eighth embodiment, the first peripheral circuitry comprises the differential sense amplifier, the first level selection circuitry, the second level selection circuitry, the first word line driver circuit, the second word line driver circuit, and a third word line driver circuit coupled to a fifth memory array via a third word line, wherein a third array level of the BEOL comprises the fifth memory array.

In one or more tenth embodiments, a system comprises an integrated circuit (IC) die comprising a first memory array comprising first dynamic random access memory (DRAM) cells, a second memory array comprising second DRAM cells, wherein a back end of line (BEOL) of the IC die comprises a first array level, and wherein the first memory array and the second memory array are each in the first array level, and a differential sense amplifier coupled to the first memory array and the second memory array via a first bit line and a second bit line, respectively, wherein the differential sense amplifier is to receive a first signal and a second signal via the first bit line and the second bit line, respectively, and generate, based on each of the first signal and the second signal, an output which indicates a bit value at one of the first DRAM cells or one of the second DRAM cells, wherein the first bit line and the second bit line extend from the first array level, toward a front end of line (FEOL) of the IC die, on opposite respective sides of first memory array, and wherein, at the FEOL, the differential sense amplifier is in a first footprint region corresponding to the first memory array, and a display device coupled to the IC die, the display device to display an image based on the bit value.

In one or more eleventh embodiments, further to the tenth embodiment, the IC die further comprises a third memory array comprising third DRAM cells, wherein the BEOL of the IC die comprises a second array level, and wherein the third memory array is in the second array level, and first level selection circuitry coupled between the differential sense amplifier and each of the first bit line and a third bit line, wherein the first level selection circuitry is coupled to the third memory array via the third bit line, and wherein the first level selection circuitry is to selectively couple the differential sense amplifier to either of the first array level or the second array level.

In one or more twelfth embodiments, further to the eleventh embodiment, the first level selection circuitry is in the first footprint region.

In one or more thirteenth embodiments, further to the eleventh embodiment, the IC die further comprises a fourth memory array comprising fourth DRAM cells, wherein the fourth memory array is in the second array level, and second level selection circuitry coupled between the differential sense amplifier and each of the first bit line and a fourth bit line, wherein the second level selection circuitry is coupled to the fourth memory array via the fourth bit line, and wherein the second level selection circuitry is to selectively couple the differential sense amplifier to either of the first array level or the second array level.

In one or more fourteenth embodiments, further to the thirteenth embodiment, the first level selection circuitry and the second level selection circuitry are each in the first footprint region.

In one or more fifteenth embodiments, further to the eleventh embodiment, the IC die further comprises a first word line driver circuit coupled to the second memory array via a first word line, and a second word line driver circuit coupled to the fourth memory array via a second word line, wherein the first word line driver circuit and the second word line driver circuit are each in a second footprint region corresponding to the second memory array.

In one or more sixteenth embodiments, further to the fifteenth embodiment, in the second footprint region, a portion of the first word line extends vertically from the first array level toward the FEOL, and wherein a portion of the second word line extends vertically past the first array level, and toward the FEOL, in a region which is outside of a periphery of the second memory array.

In one or more seventeenth embodiments, further to the fifteenth embodiment, first peripheral circuitry of the IC die is to access the first memory array, the second memory array, the third memory array and the fourth memory array, wherein the first peripheral circuitry is arranged in a first tile area of the FEOL, and wherein the tile area forms recess structures each at a respective one of opposite ends of the first tile area.

In one or more eighteenth embodiments, further to the seventeenth embodiment, the first peripheral circuitry comprises the differential sense amplifier, the first level selection circuitry, the second level selection circuitry, the first word line driver circuit, the second word line driver circuit, and a third word line driver circuit coupled to a fifth memory array via a third word line, wherein a third array level of the BEOL comprises the fifth memory array.

In one or more nineteenth embodiments, a driver circuit comprises first circuitry to receive a word line select signal, the first circuitry to generate a first signal based on the word line select signal, and further to generate a second signal with a first delay and the first signal, second circuitry to receive the word line select signal, the second circuitry to generate a third signal based on the word line select signal, and further to generate a fourth signal with a second delay and the third signal, and a charge-discharge circuit coupled to each of the first circuitry, the second circuitry, and a word line, the charge-discharge circuit comprising a first stage to decrease or increase a voltage at the word line based on the first signal and the third signal, a second stage to decrease or increase the voltage at the word line based on the second signal and the fourth signal.

In one or more twentieth embodiments, further to the nineteenth embodiment, the first circuitry comprises an upper level shifter circuit to generate the first signal based on the word line select signal.

In one or more twenty-first embodiments, further to the twentieth embodiment, the second circuitry comprises a lower level shifter circuit to generate the third signal based on the word line select signal.

In one or more twenty-second embodiments, further to the nineteenth embodiment or the twentieth embodiment, the first circuitry comprises a first delay circuit to generate a fifth signal based on an application of the first delay to the first signal, and a NAND gate circuit to receive both the first signal and the fifth signal, and to output the second signal.

In one or more twenty-third embodiments, further to the twenty-second embodiment, the second circuitry comprises a second delay circuit to generate a sixth signal based on an application of the second delay to the third signal, and a NOR gate circuit to receive both the third signal and the sixth signal, and to output the fourth signal.

In one or more twenty-fourth embodiments, further to the nineteenth embodiment or the twentieth embodiment, the first stage comprises first transistors coupled in series with each other between the word line and a first node to provide a first voltage, and second transistors coupled in series with each other between the word line and a second node to provide a second voltage which is less than the first voltage, and wherein the second stage comprises third transistors coupled in series with each other between the word line and a third node to provide a third voltage, fourth transistors coupled in series with each other between the word line and a fourth node to provide a fourth voltage which is less than the third voltage.

In one or more twenty-fifth embodiments, further to the twenty-fourth embodiment, the first voltage is less than the third voltage, and wherein the second voltage is greater than the fourth voltage.