Method and system for reducing AM/PM distortion in a polar amplifier

Methods and systems for reducing AM/PM distortion in a polar amplifier are disclosed and may comprise adding an offset signal to an amplitude signal in the digital domain and removing the offset signal in the analog domain during polar modulation. A sum of an amplitude signal and an offset signal may be mixed with a phase signal in a first differential amplifier to generate a first voltage signal, and the offset signal may be mixed with the phase signal in a second differential amplifier to generate a second voltage signal, which may be subtracted from the first voltage signal. The amplitude and offset signals may be mixed with the phase signal by modulating a current in the differential amplifiers, which may comprise cascode differential amplifiers. The modulated current may be generated using a current source and a current mirror circuit, which may comprise a cascode current mirror.

FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

FIELD OF THE INVENTION

Certain embodiments of the invention relate to wireless communication transmitters. More specifically, certain embodiments of the invention relate to a method and system for reducing AM/PM distortion in a polar amplifier.

BACKGROUND OF THE INVENTION

A power amplification circuit in a wireless system is typically a large signal device. In wireless systems, the power amplifier circuit may transmit output signals at power levels up to 30 dBm, for example. In such wireless systems, which may, for example, utilize modulation types such as binary phase shift keying (BPSK) or 512 level quadrature amplitude modulation (512-QAM), output power levels may vary widely such that the ratio of the peak power level to the average power level may be large, for example, 10 dBm to 15 dBm. Because of these large swings in output power levels, power amplifier (PA) circuits may distort the output signal. Distortion, however, is a characteristic, which may be observed in PA circuits that are utilized across a wide range of applications, and may not be limited to PA circuits utilized in wireless systems. There are two metrics, which may be utilized to evaluate the distortion performance of PA circuits. These metrics may be referred to as amplitude modulation to amplitude modulation (AM-AM) distortion, and amplitude modulation to phase modulation (AM-PM) distortion.

The AM-AM distortion provides a measure of the output power level, Pout, in response to the input power level, Pin. The input power level, and output power level are each typically measured in units of dBm, for example. In an ideal, non-distorting, PA circuit, the output power level changes linearly in response to a change in the input power level. Thus, for each ΔPinchange in the input power level there may be a corresponding change in the output power level, ΔPout≈αΔPin, where α represents a constant of linearity. The AM-AM distortion may be observed when, for example, the change in the output power level in response to a first change in input power level may be Δ1Pout≈αΔ1Pin, where the change in the output level in response to a second change in the input power level may be Δ2Pout≈βΔ2Pin, when α≠β.

The AM-PM distortion provides a measure of the phase of the output signal in relation to the input signal (or output phase) in response to the input power level. Output phase is typically measured in units of angular degrees. The AM-PM distortion may be observed when, for example, the output phase changes in response to a change in input power level.

Limitations in the performance of PA circuitry due to distortion may be exacerbated when the PA is integrated in a single integrated circuit (IC) device with other radio frequency (RF) transmitter circuitry such as digital to analog converters (DAC), low pass filters (LPF), mixers, and RF programmable gain amplifiers (RFPGA). Whereas the pressing need to increase the integration of functions performed within a single IC, and attendant increase in the number of semiconductor devices, may push semiconductor fabrication technologies toward increasingly shrinking semiconductor device geometries, these very semiconductor fabrication technologies may impose limitations on the performance of the integrated PA circuitry. For example, utilizing a 65 nm CMOS process may restrict the range of input power levels for which the PA provides linear output power level amplification. Requirements for AM-AM and/or AM-PM distortion levels as set forth in a WLAN standard, such as IEEE 802.11, may preclude transmitting output signals at high output power levels for PA circuitry that is fabricated utilizing a 65 nm CMOS process, for example. An exemplary standard for WLAN systems may specify, for example, that the ratio of the AM-AM distortion to output power level not exceed −25 dBm.

One current approach utilized in an attempt to reduce AM-AM distortion and/or AM-PM distortion involves fabricating PA circuitry in discrete IC devices, which are not integrated with other RF transmitter circuitry. The fabrication processes for these IC devices may utilize gallium arsenide (GaAs) and/or gallium nitride (GaN) materials. Silicon (Si), which is a material utilized in CMOS and various other semiconductor fabrication processes offers several advantages in relation to GaAs and/or GaN. First, silicon is a readily available, and inexpensive, material. Second, Si readily bonds to silicon dioxide (SiO2), a commonly utilized insulating layer during semiconductor manufacturing. Third, the integration of other devices with CMOS circuits is simpler in that many circuits are fabricated on Si and thus would have the same thermal mismatch and other mechanical characteristics.

The discrete IC approach imposes its own limitations, however. One such limitation is that by placing the PA circuitry and other RF transmitter circuitry in discrete IC devices, each device may be required to provide external pins that enable interfacing of the discrete devices. Increasing pin count may increase the manufacturing cost of each IC device. Furthermore, additional external circuitry may be required if the interfaces between the discrete IC devices are not compatible. For example, additional external circuitry may be required if the interface from one discrete IC device utilizes single ended input and output (I/O), while the interface from another discrete IC device utilizes differential I/O.

In another current approach utilized in an attempt to reduce AM-AM distortion and/or AM-PM distortion the input power level may be restricted to a narrower range, which may in turn restrict the maximum output power level. One limitation of this approach in wireless systems is that restricting the maximum output power level may reduce the range over which a system may transmit signals to, for example, a node B element of base transceiver station (BTS) in a wireless network. To the wireless network operator, the reduction in range may require that more node B elements, and/or BTSs be deployed, or risk that wireless network users will experience decreased communications quality, and/or dropped calls when communicating via the network.

BRIEF SUMMARY OF THE INVENTION

A system and/or method for reducing AM/PM distortion in a polar amplifier, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims.

DETAILED DESCRIPTION OF THE INVENTION

Certain aspects of the invention may be found in a method and system for reducing AM/PM distortion in a polar amplifier, and may comprise adding an offset signal to an amplitude signal in the digital domain and removing the offset signal in the analog domain during polar modulation in a power amplifier. A sum of an amplitude signal and an offset signal may be mixed with a phase signal in a first differential amplifier to generate a first voltage signal, and the offset signal may be mixed with the phase signal in a second differential amplifier to generate a second voltage signal. The second voltage signal may be subtracted from the generated first voltage signal. The amplitude and offset signals may be mixed with the phase signal by modulating a current in the differential amplifiers, which may comprise cascode differential amplifiers. The modulated current may be generated using a current source and a current mirror circuit, which may comprise a cascode current mirror. The polar amplifier may comprise a power amplifier driver or a power amplifier.

FIG. 1Ais a block diagram illustrating an exemplary mobile terminal, which may be utilized in accordance with an embodiment of the invention. Referring toFIG. 1A, there is shown mobile terminal120that may comprise an RF receiver123a, an RF transmitter123b, a digital baseband processor129, a processor125, a transmit/receive (T/R) switch122, an antenna121and a memory127. The T/R switch122may be communicatively coupled to the RF receiver123aand to the RF transmitter123b. In instances when the T/R switch122is set to “R”, or receive, the antenna121may be communicatively coupled to the RF receiver123a, and in instances when the T/R switch122is set to “T”, or transmit, the antenna121may be communicatively coupled to the RF transmitter123b.

The RF receiver123amay comprise suitable logic, circuitry, and/or code that may enable processing of received RF signals. The RF receiver123amay enable receiving of RF signals in frequency bands utilized by various wireless communication systems, such as Bluetooth, WLAN, EDGE/GSM, and/or CDMA, for example.

The digital baseband processor129may comprise suitable logic, circuitry and/or code that may enable processing and/or handling of baseband signals. In this regard, the digital baseband processor129may process or handle signals received from the RF receiver123aand/or signals to be transferred to the RF transmitter123bfor transmission via a wireless communication medium. The digital baseband processor129may also provide control and/or feedback information to the RF receiver123aand to the RF transmitter123b, based on information from the processed signals. The digital baseband processor129may communicate information and/or data from the processed signals to the processor125and/or to the memory127. Moreover, the digital baseband processor129may receive information from the processor125and/or to the memory127, which may be processed and transferred to the RF transmitter123bfor transmission to the wireless communication medium.

The RF transmitter123bmay comprise suitable logic, circuitry, and/or code that may enable processing of RF signals for transmission. The RF transmitter123bmay enable transmission of RF signals in frequency bands utilized by various wireless communications systems, such as GSM and/or CDMA, for example.

The processor125may comprise suitable logic, circuitry, and/or code that may enable control and/or data processing operations for the mobile terminal120. The processor125may be utilized to control at least a portion of the RF receiver123a, the RF transmitter123b, the digital baseband processor129, and/or the memory127. In this regard, the processor125may generate at least one signal for controlling operations within the mobile terminal120.

The memory127may comprise suitable logic, circuitry, and/or code that may enable storage of data and/or other information utilized by the mobile terminal120. For example, the memory127may be utilized for storing processed data generated by the digital baseband processor129and/or the processor125. The memory127may also be utilized to store information, such as configuration information, that may be utilized to control the operation of at least one block in the mobile terminal120. For example, the memory127may comprise information necessary to configure the RF receiver123ato enable receiving RF signals in the appropriate frequency band.

In operation, the digital baseband processor129may generate and process signals to be transmitted to a wireless media by the RF transmitter123bvia the T/R switch122and the antenna121. The RF transmitter123bmay comprise a polar transmitter and as such may be affected by AM/PM distortion. In an embodiment of the invention, the AM/PM distortion may be reduced by adding an offset in the digital domain, in the digital baseband processor129, for example, and removing the offset signal in the analog domain, in the RF transmitter123b, for example.

FIG. 1Bis a block diagram of an exemplary polar transmitter, in accordance with an embodiment of the invention. Referring toFIG. 1B, there is shown a polar transmitter comprising a digital to analog converter (DAC)107, a phase locked loop (PLL)109, a power amplifier driver (PAD)115, and a power amplifier (PA)118. The exemplary polar transmitter100ofFIG. 1Bmay be representative of the RF transmitter123bofFIG. 1A.

The DAC107may comprise suitable circuitry, logic and/or code that may enable conversion of an incoming digital signal to an analog output. The DAC107may be enabled to receive an input signal, namely, amplitude signal A(t)101. The DAC107may be enabled to generate an output signal111which may be communicated to an input of the PAD115.

The PLL109may comprise suitable circuitry, logic and/or code that may enable generation of an analog output signal in relation to a digital input signal. The PLL109may be enabled to receive an input signal, namely phase signal φ(t)103. The PLL109may be enabled to generate an output signal113, which may be communicated to an input of the PAD115.

The PAD115may comprise suitable circuitry, logic and/or code that may enable receiving of digital and analog input signals and generating an output signal for driving a power amplifier118. The PAD115may be enabled to receive an input power control signal105. Additionally, the PAD115may be enabled to receive as input signals, the output signal113generated by the PLL109and the output signal111generated by the DAC107.

The PA118may comprise suitable circuitry, logic and/or code that may enable receiving of an input signal and generating an amplified output signal. The PA118may be enabled to receive an input signal117generated by the PAD115. The PA118may be enabled to generate a signal that may be communicated to an antenna, switch or filter.

In operation, the amplitude signal A(t)101may be communicated to the input of the DAC107where it may be converted to an analog signal111. The analog signal111may be communicated to an input of the PAD115. The phase signal φ(t)103may be communicated to the input of the PLL109, where it may be converted to a signal which may be expressed using the following relationship:
cos [ωct+φ(t)]
where ωcis the angular frequency of the PLL109.

The amplitude signal A(t)101and the phase signal φ(t)103may comprise the two components of a polar signal. The power control105may be communicated to another input of the PAD115. The power control105may be a digital code utilized for controlling the gain in the PAD115. The PAD115may receive the output signals of the DAC107and the PLL113and generate a signal which may be expressed using the following relationship:
A(t)*cos [ωct+φ(t)].

The signal described by the above relationship may represent a polar signal117for communicating to the power amplifier118. The amplitude of the polar signal117may be adjusted utilizing the power control105. The power amplifier119may receive the polar signal117and generate an output signal119proportional to a product of the gain of the PA118and the polar signal117. The output signal119may be communicated to an antenna for transmission, to a switch, or to a filter.

However, in instances where the phase signal, φ(t), may be affected by the variation of the amplitude signal, A(t), AM/PM distortion may be present, and the actual output signal may be expressed by the following relationship:
A(t)*cos {(ωct+φ(t)+g[A(t)]}
where g[A(t)] is a phase term that may be a function of the amplitude signal A(t). In instances where the magnitude of A(t) may vary significantly, the term g[A(t)] may become significant, which may cause significant AM/PM distortion.

The time variation in the phase signal, g[A(t)] may be larger in cases when the magnitude of A(t) is low. Thus, g[A(t)] may be reduced by adding an offset A0in the digital domain to the amplitude signal A(t), thereby maintaining the magnitude of the amplitude signal, A(t)+A0, at a higher level. The addition of the offset A0may be described further with respect toFIG. 2.

In another embodiment of the invention, the phase signal φ(t), the amplitude signal A(t) and the offset signal A0may be communicated to the PA118, as opposed to the PAD115.

FIG. 2is a block diagram illustrating an exemplary circuit for reducing AM/PM distortion, in accordance with an embodiment of the invention. Referring toFIG. 2, there is shown polar amplifier200comprising current sources201and207, inductors203and205, and transistors Q1, Q2, Q3, Q4, Q5, Q6, Q7and Q8. The polar amplifier200may comprise a power amplifier driver or a power amplifier. The current source201may comprise suitable circuitry, logic and/or code that may be enabled to generate a current that represents the amplitude signal A(t) plus the offset signal Ao. The inductors203and205may be coupled to capacitors, not shown, to define a desired output impedance and tuning frequency of the power amplifier driver200.

The transistors Q5and Q6and the transistors Q7and Q8may comprise current mirrors that may be enabled to communicate a current signal I1proportional to A(t)+A0and the current signal I2proportional to A0to the drain terminals of the transistors Q1and Q2and Q3and Q4, respectively. The transistors Q1and Q2and the transistors Q3and Q4may comprise differential pairs that may be enabled to amplify the phase signal φ(t), that may be coupled to the base terminals of Q1and Q2and to Q3and Q4, respectively. The drain terminal of the transistor Q3may be coupled to the drain terminal of the transistor Q2, and the drain terminal of the transistor Q4may be coupled to the drain terminal of the transistor Q1.

In operation, the current mirror comprising the transistors Q5and Q6may mirror the input current A(t)+Aogenerated by the current source201to generate a current I1, which may be proportional to A(t)+A0, to the source terminals of the differential transistor pair comprising the transistors Q1and Q2. In this regard, the current mirror comprising the transistors Q7and Q8may mirror the input current Aogenerated by the current source207to generate a current I2, which may be proportional to A0, to the source terminals of the differential transistor pair comprising the transistors Q3and Q4.

The phase signal φ(t) may be communicated to the base terminals of the transistors Q1/Q2and Q3/Q4. The differential pair comprising the transistors Q1and Q2may mix the phase signal φ(t) with the current I1, which may be proportional to the amplitude plus the offset signal, A(t)+A0. The differential pair comprising the transistors Q3and Q4may mix the phase signal φ(t) with the current I2, which may be proportional to the amplitude of the offset signal, A0. If the offset signal A0were equal to zero, the output signal, VOUT, may be expressed by the following relationship:
A(t)*cos [ωct+φ(t)]
as was given above for the ideal case of a polar signal with no AM/PM or AM/AM distortion with the PAD115described with respect toFIG. 1B.

In instances when the offset signal may be non-zero, the output signal, VOFF, for the differential pair comprising the transistors Q3and Q4, may be expressed by the following relationship:
A0*cos [ωct+φ(t)]

By utilizing an offset signal A0of high enough magnitude, the variation of the phase signal versus the amplitude signal, denoted by g[A(t)] above, may be minimized, or essentially a constant, denoted by φ0, rendering it ineffective as a source of AM/PM distortion. Because the outputs of the differential pairs comprising Q1/Q2and Q3/Q4may be coupled with the opposite polarity, that is, the drain of Q3, which may correspond to the positive input terminal for the phase signal φ(t), may be coupled to the drain of the transistor Q2, which may correspond to the negative input terminal for the phase signal φ(t), this may result in the cancellation of the portion of the output voltage generated as a result of the offset signal A0for both differential pairs, effectively mitigating AM/PM distortion, and may also reduce AM/AM distortion. In this manner, the output voltage VOUTmay be expressed by the following relationship:
(A(t)+A0)*cos [ωct+φ(t)+φ0]−A0*cos [ωct+φ(t)+φ0]=A(t)*cos [ωct+φ(t)+φ0]
which may be equal to the desired output signal, in which a constant phase offset such as φ0does not affect the phase noise.

FIG. 3is a block diagram illustrating an exemplary cascode circuit for reducing AM/PM distortion, in accordance with an embodiment of the invention. Referring toFIG. 3, there is shown polar amplifier300comprising current sources301and307, inductors303and305, and transistors Q1-Q16. The polar amplifier300may comprise a power amplifier driver or a power amplifier. The current source301may comprise suitable circuitry, logic and/or code that may be enabled to generate a current that represents the amplitude signal A(t) plus the offset signal Ao. The inductors303and305may be coupled to capacitors, not shown, to define a desired output impedance and tuning frequency of the power amplifier driver300.

The transistors Q5, Q6, Q7and Q8may comprise a cascode current mirror that may be enabled to communicate a current signal Iiproportional to A(t)+A0to the drain terminals of the transistors Q1and Q2. The transistors Q13, Q14, Q15and Q16may comprise a cascode current mirror that may be enabled to communicate a current signal I2proportional to A0to the source terminals of the transistors Q9and Q10. The transistors Q1, Q2, Q3and Q4may comprise a cascode differential pair that may be enabled to amplify the phase signal φ(t), which may be coupled to the base terminals of Q1and Q2. The transistors Q9, Q10, Q11and Q12may comprise a cascode differential pair that may be enabled to amplify the phase signal φ(t), that may be coupled to the base terminals of Q9and Q10. The drain terminal of the transistor Q3may be coupled to the drain terminal of the transistor Q11, and the drain terminal of the transistor Q4may be coupled to the drain terminal of the transistor Q12.

The cascode configurations for the circuit illustrated inFIG. 3may increase the linearity of the current sources comprising the transistors Q5, Q6, Q7and Q8and Q13, Q14, Q15and Q16compared to the current sources described with respect toFIG. 2. In addition, the isolation of the cascode differential pairs comprising the transistors Q1, Q2, Q3and Q4and Q9, Q10, Q11and Q12may be increased due to the increased output impedance of the cascode as compared to the differential pairs described with respect toFIG. 2. The bias voltages VB1and VB2may be adjusted to activate or deactivate the circuit.

In operation, the cascode current mirror comprising the transistors Q5, Q6, Q7and Q8may mirror the input current A(t)+Aogenerated by the current source301to generate a current I1, which may be proportional to A(t)+A0, to the common source terminals of the transistors Q1and Q2of the cascode differential transistor pair comprising the transistors Q1, Q2, Q3and Q4. The cascode current mirror comprising the transistors Q13, Q14, Q15and Q16may mirror the input current Aogenerated by the current source307to generate a current I2, which may be proportional to A0, to the common source terminals of the transistors Q9and Q10of the cascode differential transistor pair comprising the transistors Q9, Q10, Q11and Q12.

The phase signal φ(t) may be communicated to the base terminals of the transistors Q1/Q2and Q9/Q10. The cascode differential pair comprising the transistors Q1, Q2, Q3and Q4may mix the phase signal φ(t) with the current I1, which may be proportional to the amplitude signal plus the offset signal, A(t)+A0. The differential pair comprising the transistors Q9, Q10, Q11and Q12may mix the phase signal φ(t) with the current I2, which may be proportional to the amplitude of the offset signal, A0. If the offset signal A0were equal to zero, the output signal, VOUT, may be expressed by the following relationship:
A(t)*cos [ωct+φ(t)]
as was given above for the ideal case of a polar signal with no AM/PM or AM/AM distortion with the PAD115described with respect toFIG. 1B.

By utilizing an offset signal A0of high enough magnitude, the variation of the phase signal versus the amplitude signal, denoted by g[A(t)] above, may be minimized, or essentially a constant, denoted by φ0, rendering it ineffective as a source of AM/PM distortion. Because the cascode differential pairs comprising the transistors Q1, Q2, Q3and Q4and Q9, Q10, Q11and Q12may be coupled with the opposite polarity, i.e. the drain of Q11, which may correspond to the positive input terminal for the phase signal φ(t), may be coupled to the drain of the transistor Q4, which may correspond to the negative input terminal for the phase signal φ(t), this may result in the cancellation of the portion of the output voltage generated as a result of the offset signal A0for both cascode differential pairs, effectively mitigating AM/PM distortion, and may also reduce AM/AM distortion. In this manner, the output voltage VOUTmay be expressed by the following relationship:
(A(t)+A0)*cos [ωct+φ(t)+φ0]−A0*cos [ωct+φ(t)+φ0]=A(t)*cos [ωct+φ(t)+φ0]
which may equal the desired output signal, in which a constant phase offset such as φ0does not affect the phase noise.

FIG. 4is a flow diagram illustrating exemplary steps in the reduction of AM/PM and AM/AM distortion in a polar amplifier, in accordance with an embodiment of the invention. Referring toFIG. 4, in step403, the current source201may generate a current comprising an amplitude signal, A(t) added to an offset signal, A0. The offset signal, A0may also be generated by the current source207. The current mirrors comprising the transistors Q5/Q6and Q7/Q8may generate currents I1and I2proportional to A(t)+A0and A0, respectively. In step407, the phase signal, φ(t) may be communicated to the gate terminals of the differential pairs comprising Q1/Q2and Q3/Q4. In step409, the phase signal φ(t) may be mixed with the current I1and I2by the differential pairs comprising Q1/Q2and Q3/Q4, respectively. In step409, due to the polarity of the output signals of the differential pairs comprising Q1/Q2and Q3/Q4, the offset signal may be cancelled out, resulting in the desired output signal, A(t) cos [ωct+φ(t)] in step413, followed by end step415.

In an exemplary embodiment of the invention, in a polar amplifier, an offset signal A0may be added to an amplitude signal A(t) in the digital domain and removed in the analog domain. A sum of the amplitude signal and the offset signal may be mixed with a phase signal φ(t) in a first differential amplifier Q1/Q2to generate a first voltage signal, and the offset signal A0may be mixed with the phase signal φ(t) in a second differential amplifier Q3/Q4to generate a second voltage signal. The second voltage signal may be subtracted from the generated first voltage signal. The amplitude and offset signals, A(t) and A0, may be mixed with the phase signal φ(t) by modulating a current in the differential amplifiers Q1/Q2and/or Q3/Q4, which may comprise cascode differential amplifiers Q1, Q2, Q3and Q4and/or Q9, Q10, Q11and Q12. The modulated currents I1and I2may be generated using a current source201and207and a current mirror circuit, which may comprise a cascode current mirror Q5, Q6, Q7and Q8and Q13, Q14, Q15and Q16. The polar amplifier may comprise a power amplifier driver or a power amplifier.

Certain embodiments of the invention may comprise a machine-readable storage having stored thereon, a computer program having at least one code section for communicating information within a network, the at least one code section being executable by a machine for causing the machine to perform one or more of the steps described herein.

Accordingly, aspects of the invention may be realized in hardware, software, firmware or a combination thereof. The invention may be realized in a centralized fashion in at least one computer system or in a distributed fashion where different elements are spread across several interconnected computer systems. Any kind of computer system or other apparatus adapted for carrying out the methods described herein is suited. A typical combination of hardware, software and firmware may be a general-purpose computer system with a computer program that, when being loaded and executed, controls the computer system such that it carries out the methods described herein.