Over-voltage tolerant input buffer having hot-plug capability

An input buffer circuit and associated method operable in a normal mode and a hot-plug mode. In one example, the input buffer has an input and a buffer output, and the input buffer may include a pull-up path coupled between a first circuit supply and the buffer output; a pull-down path coupled between the buffer output and a ground reference voltage; a first transistor coupled between the input and the pull-up path to activate the pull-up path; a second transistor coupled between the input and the pull-down path to activate the pull-down path; and a third transistor for protecting the pull-up path from over-voltage. The input buffer circuit may be configured to prevent an over-voltage condition on each of the plurality of transistors and the input buffer circuit may be configured to allow a hot-plug operation.

TECHNICAL FIELD

The present invention relates generally to integrated circuit (IC) input/output (I/O) buffers and, more particularly, to input buffers having over-voltage tolerance and hot-plug capability.

BACKGROUND OF THE INVENTION

In systems, such as communication systems, circuit cards are often required to be replaced without impacting the normal system functionality. Typically, such cards are replaced while the other parts of system continue to receive their full power supply. Because of this requirement, input/output (I/O) pads of integrated circuits or chips included on these cards can have a signal on their pads even when these chips are not receiving their own power supply. This situation is commonly referred to as a “hot-plug” where the chip would be referred to as “hot-pluggable.” For this capability, the chip input receivers (i.e., buffers) must have hot-plug capability. In internal circuit protection terms, the critical current paths should be switched off to accommodate the “live insertion” of a chip into a system where the chip power supply is not yet at its full level, but where a signal may be present at a chip pad.

Because chip technologies are improving by shrinking dimensions to allow for continued performance enhancements, board power supplies typically remain at least one generation behind. Thus, the I/Os inside the chips may be driven using a higher power supply, so both input and output may also see the higher supply voltage. As recognized by the present inventors, such I/Os may need to be protected from supply “over-voltage” conditions where the I/O is essentially supplied by a higher voltage level than the fabrication or core technology used to implement the transistors in the I/O circuitry. Over-voltage protection, in circuit implementation terms, includes, for example, situations where the VGS (transistor gate-to-source voltage), VDS (transistor drain-to-source voltage), and VGD (transistor gate-to-drain voltage) differences across any associated transistor should not be allowed to face more than a designated value, such as 2.75 volts for a given transistor technology. If each such transistor is protected, then the I/O circuit as a whole can be protected.

A conventional approach to implement the hot-plug capability is shown in circuit20ofFIG. 1. There are two basic modes of operation: a “live insertion” mode (e.g., the “hot plug” situation) and a “normal” mode. In the live insertion mode, the NGATE node22is at a voltage level of about PAD-2Vt (i.e., about two transistor threshold voltages below the voltage level applied to the PAD node24) and the PGATE node26is essentially the same voltage level as the NGATE22. Thus, virtually no current path exists through transistor MP1. In the live insertion mode, the circuit20may tolerate up to about 3.6 volts at the PAD24. In the normal mode of operation, the PGATE node26will be about 2Vt (i.e., about two transistor threshold voltages) above the ground level, this will turn on transistor MP1, and NGATE22will be around the VDD level. Thus, the PAD signal24will be substantially passed to the core28by transistor MN1.

This conventional approach ofFIG. 1has two main disadvantages. First, this circuit20cannot take care of over-voltage if the chip power supply is greater than the technology supports, so there is no effective over-voltage protection. For example, if VDD is about 3.6 volts in normal operating conditions and PAD24is about 0 volts, MN1is subjected to an over-voltage condition. Second, the signal passed to the core does not provide a rail-to-rail output and this adversely affects the Vih (minimum input level detectable as a logic high) and Vil (maximum input level detectable as a logic low) levels.

As recognized by the present inventors, what is needed is an input buffer having over-voltage tolerance and hot-plug capability, and if desired, also providing a full rail-to-rail output to the associated chip core. It is against this background that embodiments of the present invention have been developed.

SUMMARY

According to an embodiment of the present invention, an input buffer having over-voltage tolerance based on the chip power supply level is provided, and the input buffer has a hot-plug capability.

According to one broad aspect of another embodiment of the present invention, disclosed herein is an integrated circuit including at least one pad receiving at least one input signal, a core, and at least one input buffer circuit coupled between the pad and the core, the input buffer having a first mode where the input buffer circuit operates as an inverter, and a second mode wherein the input buffer circuit limits the voltage levels within the input buffer. In one embodiment, the first mode includes a normal mode where a supply voltage is applied to the input buffer circuit, and the second mode includes a live-insertion mode where a supply voltage is not applied to the input buffer circuit and an input signal is applied to the at least one pad.

According to one broad aspect of another embodiment of the present invention, disclosed herein is a method of operating an input buffer. In one example, the method includes configuring the input buffer to operate substantially as an inverter in a normal mode and configuring the input buffer to operate substantially to limit internal voltage levels in a live insertion mode.

According to one broad aspect of another embodiment of the present invention, disclosed herein is an input buffer circuit having an input (i.e., PAD inFIG. 2) and a buffer output (i.e., INPUT TO CORE), the input buffer operable in a normal mode and a hot-plug mode. In one example, the input buffer may include a pull-up path coupled between a first circuit supply (i.e., VDD) and the buffer output, and a pull-down path coupled between the buffer output and a ground reference voltage; a first transistor (i.e., MP3) coupled between the input and the pull-up path to activate the pull-up path; a second transistor (i.e., MN3) coupled between the input and the pull-down path to activate the pull-down path; and a third transistor (i.e., MN4) for protecting the pull-up path from over-voltage.

In one example, the input buffer circuit is configured to prevent an over-voltage condition on each of the plurality of transistors and the input buffer circuit is configured to allow a hot-plug operation. In another embodiment, the pull-up path may include a first reference voltage (i.e., V—10) and a first pair of transistors including a first and second pull-up transistor (i.e., MP1and MP2) coupled in series, the first pull-up transistor (i.e., MP1) having a gate coupled with the first transistor (i.e., MP3) and the gate biased by the third transistor (i.e., MN4) and the second pull-up transistor (i.e., MP2) having a gate biased by the first reference voltage (i.e., V—10 which may be approximately 1.0 volts in one example).

In another embodiment, the pull-down path may include a second reference voltage (i.e., V—25) and a second pair of transistors including a first and second pull-down transistor (i.e., MN1and MN2) coupled in series, the first pull-down transistor (i.e., MN2) having a gate coupled with the second transistor (i.e., MN3) and the second pull-down transistor (i.e., MN1) having a gate biased by the second reference voltage (i.e., V—25 which may be approximately 2.5 volts in one example).

In one embodiment, the input buffer circuit may also include a first bias voltage (i.e., PAD_PGATE) for biasing the first transistor (i.e., MP3) and a second bias voltage (i.e., NGATE) for biasing the second transistor (i.e., MN3). In one example, the first bias voltage is approximately 1.0 volts during the normal mode and is approximately the input minus two diode drops during the hot-plug mode. In another example, the second bias voltage is approximately 2.5 volts during the normal mode and is approximately the input minus two diode drops during the hot-plug mode.

According to another aspect of the embodiment, the input buffer provides a full rail-to-rail output level range from the buffer.

The features, utilities and advantages of the various embodiments of the invention will be apparent from the following more particular description of embodiments of the invention as illustrated in the accompanying drawings.

DETAILED DESCRIPTION

Disclosed herein is a circuit which can be used as an input buffer in an integrated circuit. Embodiments of the present invention provide protection of the input buffer components (i.e., transistors) from over-voltage during normal operation as well as during hot-plug or hot-swap operations. In one example, normal operations include when the integrated circuit receives a VDD signal, such as 3.0 to 3.6 volts, and hot-plug or hot-swap operations include when the integrated circuit does not receive a VDD signal but an input signal may still be present on an I/O pad of the integrated circuit. For instance, the hot-plug condition may arise as described above when the integrated circuit is part a circuit board that is dynamically removed from a system that is operating. Various embodiments of the present invention are described herein.

An example of a circuit30according to an embodiment of the present invention is illustrated inFIG. 2.FIGS. 3–5illustrates circuits32,34,36that may be used to generate bias voltages for the circuit30ofFIG. 2.FIG. 6illustrates one possible use of an embodiment of the present invention, for instance, where an integrated circuit40has one or more PADs or I/O pins42, and the buffer circuit30provides a buffer between the signal present at the PAD42and the corresponding INPUT TO CORE signal44.

An embodiment of the present invention will now be described with reference to a buffer circuit30ofFIG. 2in conjunction with Table 1. Embodiments of the present invention provide a circuit30that is over-voltage tolerant in its normal working mode (i.e., when VDD is present) and in addition is over-voltage tolerant during a hot-plug mode (i.e., when VDD is not present but signals are applied to input pads42). In one example, none of the transistors (i.e., MOSFET devices) inFIG. 2see a voltage difference across any of the terminals of more than about 2.75 volts, for example.

As used herein, the term “transistor” or “switch” includes any switching element which can include, for example, n-channel or p-channel CMOS transistors, MOSFETs, FETs, JFETS, BJTs, or other like switching element or device. The particular type of switching element used is a matter of choice depending on the particular application of the circuit, and may be based on factors such as power consumption limits, response time, noise immunity, fabrication considerations, etc. Hence while embodiments of the present invention are described in terms of p-channel and n-channel transistors, it is understood that other switching devices can be used, or that the invention may be implemented using the complementary transistor types.

In the example ofFIG. 2, the input signal PAD42receives the external signal into the integrated circuit, and the output signal INPUT TO CORE44is passed from the buffer30to the core46of the integrated circuit. In one example, the chip power supply VDD is a nominal 3.6 volts (i.e., between 3.0 to 3.6 volts, typically about 3.6 volts) with a core technology intended for a supply of about 2.75 volts, although other voltage ranges are possible depending upon the implementation.

In accordance with an embodiment of the present invention, a signal V—10 is provided which may, in one example, be approximately 1.0 volts, and a signal of V—25 is provided which may be approximately 2.5 volts. These signals can be provided using conventional power supply or regulation techniques or signal reference creation techniques, and may be derived from VDD. Further, the voltage levels of signals PAD-Vt, PAD_PGATE, NWELL, and NGATE can be provided using voltage references, supplies, or logic so that these signals are as listed in Table I, in one example.

InFIG. 2, P-channel transistors MP1and MP2are coupled in series with N-channel transistors and MN1and MN2, in one example. In one embodiment, the source of P-channel transistor MP1is coupled to VDD, the drain of transistor MP1is coupled to the source of transistor MP2, which has its drain coupled with the drain of N-channel transistor MN1. The source of N-channel transistor MN1is coupled with the drain of N-channel transistor MN2, which has its source coupled with VSS. The well of transistors MP1and MP2are coupled with VDD, while the substrate of transistors MN1and MN2are coupled to VSS. The gate of transistor MP1forms node N1, while the gate of transistor MN2forms node N2. The gates of transistors MP2and MN1are driven by signals V—10 and V—25, respectively, in one example.

In one embodiment, N-channel transistor MN4has its gate and drain coupled with signal PAD-Vt, and its source coupled with node N1. The substrate of transistor MN4is coupled with VSS. N-channel transistor MN3has its drain coupled with the PAD signal through resistor R1(i.e., 300–400 ohms, in one example) and its source coupled with the gate of transistor MN2at node N2. The gate of transistor MN3is coupled with the NGATE signal and its well is coupled with VSS, in one example.

The PAD signal42through resistor R1is also coupled with the source of P-channel transistor MP3which has its drain coupled with node N1, and its gate coupled with the signal PAD_PGATE, and its well coupled with NWELL, in one example.

AsFIG. 2shows, a cascoded inverter structure50can be used to protect the devices from over-voltage. This structure can include a pull-up path52, comprising devices MP1and MP2, and a pull-down path54, comprising devices MN1and MN2. Further, one or more regulated supplies (not shown) can be coupled to the circuit30ofFIG. 2to bias one or more particular circuit nodes, such as, for example: PAD-Vt, PAD_PGATE, NWELL, V—25, V—10, and NGATE.

Table I lists examples of values for the circuit30ofFIG. 2during normal operations as well as during a hot-plug or live insertion mode, in accordance with one embodiment of the present invention.

In the normal mode, the circuit30ofFIG. 2works in one example as an inverting buffer with various nodes driven in a manner as shown on Table I to prevent an over-voltage condition for each device. Node V—10 may be approximately 1.0 volt and node V—25 may be approximately 2.5 volts. These signals can be generated using a common resistor divider type of circuit, as one example. The requirements for the signal at node N1may include that it should be more than about 1.0 volt (or about 2Vt above the ground level). Also, the signal level at node N2may be maintained below about 2.5 volts, in order to prevent an over-voltage condition. To implement this, transistors MP3and MN3can be used. The gates of MP3and MN3may be maintained at about 1.0 volts, and about 2.5 volts, respectively, in the normal operating mode, in one example.

Hence, the buffer30acts as an inverter during normal operations when VDD is present since transistors MP3, MN3, MP2and MN1are on. If the PAD voltage input42is high, transistor MN2turns on (and transistor MP1turns off) and the output signal INPUT TO CORE44goes low. If the PAD voltage input42is low, transistor MP1turns on (and transistor MN2turns off) and the output signal INPUT TO CORE44goes high.

In the live insertion/hot-plug mode, PAD_PGATE may be approximately at the PAD potential and NWELL may be essentially at about PAD-Vd, where Vd can be the cut-in voltage for a diode. This will cause transistor MP3to turn off. To prevent the MP3well diode from forward biasing, the well of MP3is coupled with NWELL. Because of this, there may be no leakage through transistor MP3. As the MP3drain can reach about the PAD voltage and node N1can be at about zero potential, MP3can sustain damage due to over-voltage. To reduce the risk of this, transistor MN4may be used to force a level of about PAD-2Vt at node N1.

FIGS. 3–5show examples of circuits32,34,36that may be used to generate the bias voltage levels shown in Table I for the buffer circuit30ofFIG. 2, in accordance with an embodiment of the present invention. Of course, any appropriate bias generation circuits known in the art can be used to generate the signals in accordance with Table 1. As will be described with reference toFIGS. 3–5, these circuits32,34,36can be used to provide signals PAD-Vt, NWELL, PAD_PGATE, and NGATE that may be used for the circuit ofFIG. 2. InFIGS. 3–5, the legend VPWR is the same as VDD inFIG. 2, and the legend VGND is the same as VSS inFIG. 2.

InFIG. 3, circuit32may include three circuit sections60,62,64, in one example. InFIG. 3, the substrate of the N-channel transistors are coupled with VGND, while the wells of the P-channel transistors are coupled with NWELL, in one example.

In a first section60producing signals PAD-Vt, PGATE, and PAD-2Vt, transistors MN11, MN12, MP11, MP12, and MN13are connected in series, in one example. N-channel transistor MN11has its gate coupled with the PAD signal through resistor R1(which may be the same resistor as resistor R1inFIG. 2), and its drain is coupled with its gate.

The source of transistor MN11provides the signal PAD-Vt (which can be used inFIG. 2) and is coupled with the drain and gate of N-channel transistor MN12which is coupled to circuit portion70shown below inFIG. 5. The source of transistor MN12is coupled with the source of P-channel transistor MP1as well as with circuit portion72ofFIG. 5below. The gate of transistor MP11is coupled with signal VPWR, and the drain of transistor MP11is coupled with the source of P-channel transistor MP12. The source of transistor MP12produces the signal PAD-2Vt, while the gate of transistor MP12is coupled with the VPWR signal, in one example. The drain of transistor MP12is coupled with the drain of N-channel transistor MN13to produce the PGATE signal, in one example. N-channel transistor MN13has its gate driven by signal V—25, and its source coupled with signal V—10.

In a second section62for producing bias signal NWELL (which can be used inFIG. 2), P-channel transistor MP13receives at its gate the PGATE signal, and has its source coupled with VPWR, and its drain coupled with the PAD-2Vt signal. The well of transistor MP13is coupled with the NWELL signal, in one example. P-channel transistor MP15has its source coupled with the drain of transistor MP13, and its drain and well connected together and coupled with the NWELL signal.

In a third section64for producing signal PAD_PGATE (which can be used inFIG. 2), P-channel transistor MP14has its source coupled with the drain of transistor MN11which is also coupled to the gate of transistor MP14through resistor R2. The drain of transistor MP14is coupled with the source of P-channel transistor MP16. P-channel transistor MP11has its gate coupled with a PGATE signal, and its source coupled with the drain of transistor MP14, and its drain coupled with the gate of transistor MP15which is coupled with the PAD_PGATE signal.

N-channel transistors MN14and MN15are connected in parallel, with transistor MN14having its gate and drain coupled with VPWR, while the gate and drain of transistor MN15are coupled with the signal PAD-Vt. The source of transistor MN14is coupled with the source of transistor MN15, which is coupled with the drain and gate of transistor MN16. The source of transistor MN16is coupled with the gate and source of N-channel transistor MN17, which has its drain coupled with VPWR.

N-channel transistor MN18has its source coupled with the gate of transistor MN17, and its gate and drain coupled with the gate of transistor MP14and the PAD signal through the series combination of resistors R1and R2. In one example, resistor R2may be 20 k-ohms to 30 k-ohms.

N-channel transistor MN19has its gate coupled with the sources of transistors MN14and MN15and the gate of transistor MN16, and the source of transistor MN19produces the PAD_PGATE signal that drives the gate of transistor MP15. The drain of transistor MN19is coupled with the source of N-channel transistor MN20. Transistor MN20has its gate coupled with signal V—25, and its drain coupled with the signal V—10.

InFIG. 4, one example of a circuit34for generating a signal NGATE (which can be used inFIG. 2) is illustrated in accordance with an embodiment of the present invention. The substrates of the N-channel transistors are coupled with VGND, while the wells of the P-channel transistors are coupled with NWELL, in one example.

InFIG. 4, transistors MN22, MP17, and MN23are coupled in series. The drain and gate of N-channel transistor MN22are coupled with the PAD-Vt signal ofFIG. 3, while the source of transistor MN22generates the NGATE signal which is coupled with the drain of P-channel transistor MP17. The gate of transistor MP17is coupled with the PGATE signal, while the source of transistor MP17is coupled with the source of N-channel transistor MN23. The gate of transistor MN23is coupled with the VWPR signal, while the drain is coupled with the V—25 signal.

The circuit portions70and72ofFIG. 3are shown respectively in circuit36ofFIG. 5. InFIG. 5, the substrates of the N-channel transistors are coupled with VGND, while the wells of the P-channel transistors are coupled with NWELL, in one example.

InFIG. 5, circuit portion72has two N-channel transistors connected in series. Transistor MN25has its source coupled with the source of transistor MP11ofFIG. 3, and its drain and gate coupled together with the source of transistor MN26. Transistor MN26has its gate and drain coupled together with the VDD signal, in one example.

InFIG. 5, circuit portion70has transistors MP18, MP19, MN28, and MN27. In one example, P-channel transistor MP18has its source coupled with the drain of transistor MN12ofFIG. 3, and the gate of transistor MP18inFIG. 5is coupled with the PAD_RES signal, wherein PAD_RES is the node after resistor R1inFIG. 3. The drain of transistor MP18is coupled with the source of P-channel transistor MP19, which has its gate coupled with the PGATE signal. The gate and drain of N-channel transistor MN28are coupled with the drain of transistor MP19. The source of transistor MN28is coupled with the drain and gate of transistor MN27, and the source of transistor MN27is coupled with VGND.

Table II lists examples of values for various voltage signals in the circuit ofFIGS. 3–5during normal operations as well as during a hot-plug or live insertion mode, in accordance with one embodiment of the present invention.

InFIGS. 3–5, NWELL is generated such that there is no current path from VPWR to NWELL in the live-insertion case, and in the normal mode, there is no current path from PAD to VPWR.

In normal condition, transistors MP11and MP12ofFIG. 3will be OFF and PGATE will charge to V—10 (V—10<(V—10-Vt)). This in turn will turn transistor MP13ofFIG. 3ON and PAD-2Vt will reach VDD value. In this condition, node82ofFIG. 3should not be less than 2Vt otherwise transistor MP11ofFIG. 3will face over-voltage. Therefore, the circuit ofFIG. 5is used to keep node82ofFIG. 3at least 2Vt above ground level.

In hot-plug condition, VPWR is 0 volts so that V—10 and V—25 will also be 0 volts. Hence, the voltage of node80ofFIG. 3will charge to PAD-Vt and node82ofFIG. 3will charge to PAD-2Vt. Hence, PAD-Vt and PAD-2Vt are generated.

In section62ofFIG. 3, the NWELL bias circuit is provided. The NWELL signal should be VDD in normal operating condition, and should be biased from PAD during a hot-plug condition. In normal conditions, PGATE is V—10 and PAD_PGATE is also V—10 (from circuit section64ofFIG. 3, since ((VDD-Vt) and (V—25-Vt)>V—10). Therefore, transistors MP13and MP15will be on, and NWELL will charge to VDD potential.

In a hot-plug condition, the voltage drop across resistor R2inFIG. 3will cause transistor MP14to turn on. Transistor MP16will also turn on because PGATE is PAD-2Vt under this condition. Therefore, PAD_PGATE will turn off transistor MP15. But the NWELL signal will be charged to PAD-Vth (one diode drop) by transistor MP3(diode leakage) ofFIG. 2.

FIG. 4generates an NGATE signal for NMOS transistor MN3inFIG. 2. In normal conditions, NGATE will be V—25 and in hot-plug condition NGATE will be PAD-2Vt. Capacitance may be added at this node to avoid excessive switching.

Node80inFIG. 3does not have any discharge path, except as provided by the circuit36ofFIG. 5. In normal conditions, if PAD is VDD, node80will charge to PAD-Vt, and if PAD goes to 0 volts, transistor MN11ofFIG. 3would be exposed to over-voltage; however, through the use of the circuit ofFIG. 5, if PAD is low, the circuit ofFIG. 5will turn on and discharge node80to 2Vt level.

FIG. 6illustrates one possible use of an embodiment of the present invention. InFIG. 6, an integrated circuit40includes a core46and a plurality of pads42for receiving or transmitting external signals. One or more I/O buffers30can be made using embodiments of the present invention for electrically coupling a portion of said core to one or more pads. Embodiments of the present invention can be used in a variety of circuits where buffers may be used, such as in non-volatile memory circuits, programmable logic devices, semiconductors, microprocessors or micro-controllers, logic or programmable logic devices, clock circuits, or the like.

It is understood that while the various aspects of the particular embodiment set forth herein has been described in detail, the present invention could be subject to various changes, substitutions, and alterations without departing from the spirit and scope of the invention. As but a few examples, the particular voltage levels described herein could be changed to different voltage levels, depending on the particular application and processing technologies involved. For example, V—25 may correspond to 2.2 volts, 2.0 volts, 1.8 volts, 1.5 volts, or other voltage, depending on the application and processing technologies involved. Similarly, V—10 may correspond to 1.5 volts, 1.2 volts, 0.8 volts, 0.6 volts, or other voltage, depending on the application and processing technologies involved. In addition, the transistor Vt (threshold voltages) may be essentially any suitable voltage difference. In addition, other types of switching and voltage shifting devices, such as bipolar or other types of transistors may be used to implement an embodiment of this invention.

While the methods disclosed herein have been described and shown with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form equivalent methods without departing from the teachings of the present invention. Accordingly, unless specifically indicated herein, the order and grouping of the operations is not a limitation of the present invention.

While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various other changes in the form and details may be made without departing from the spirit and scope of the invention.