Provided is a reference voltage circuit capable of adjusting an arbitrary output voltage to have arbitrary temperature characteristics. The reference voltage circuit includes: a reference current generating circuit configured to convert a difference between forward voltages of a plurality of PN junction elements into current to generate a first current; a current generating circuit configured to use the first current generated by the reference current generating circuit to generate a second current; and a voltage generating circuit including a first resistive element and a second resistive element, the first resistive element being configured to generate a first voltage having positive temperature characteristics when the first current flows through the first resistive element, the second resistive element being configured to generate a second voltage having negative temperature characteristics when the first current and the second current flow through the second resistive element. The reference voltage circuit outputs a reference voltage obtained by adding the first voltage to the second voltage.

TECHNICAL FIELD

The present invention relates to a bandgap reference voltage circuit for generating a reference voltage, and more specifically, to a technology for adjusting temperature characteristics of the reference voltage.

BACKGROUND ART

FIG. 7is a circuit diagram illustrating a related-art bandgap reference voltage circuit. The related-art bandgap reference voltage circuit includes PMOS transistors602,603,605, and606, NMOS transistors604and609, bipolar transistors611,612, and613, resistors607and608, a start circuit601, an output terminal610, a power supply terminal101, a ground terminal100, and a substrate terminal620.

The connections are now described. The PMOS transistor602has a gate connected to the start circuit601, a drain connected to a gate and a drain of the NMOS transistor609and a gate of the NMOS transistor604, and a source connected to the power supply terminal101. The PMOS transistor603has a drain and a gate both connected to a drain of the NMOS transistor604, and a source connected to the power supply terminal101. The PMOS transistor605has a gate connected to the gate of the PMOS transistor603, a drain connected to the drain and the gate of the NMOS transistor609, and a source connected to the power supply terminal101. The PMOS transistor606has a drain connected to the output terminal610and one terminal of the resistor608, and a source connected to the power supply terminal101. The bipolar transistor613has an emitter connected to the other terminal of the resistor608, a base connected to the ground terminal100, and a collector connected to the substrate terminal620. The NMOS transistor604has the gate connected to the gate of the NMOS transistor609, and a source connected to one terminal of the resistor607. The bipolar transistor611has a base connected to the ground terminal100, an emitter connected to the other terminal of the resistor607, and a collector connected to the substrate terminal620. The bipolar transistor612has a base connected to the ground terminal100, an emitter connected to a source of the NMOS transistor609, and a collector connected to the substrate terminal620.

CITATION LIST

Patent Literature

SUMMARY OF THE INVENTION

However, the related art has a problem in that, when the resistor608is adjusted for adjusting the value of the output voltage generated at the output terminal610, the temperature characteristics of the output voltage may change. In addition, the related art has another problem in that it is difficult to output a voltage equal to or lower than the forward voltage of the PN junction of the bipolar transistor613.

The present invention has been devised in order to solve the above-mentioned problems, and provides a reference voltage circuit capable of adjusting an arbitrary output voltage to have arbitrary temperature characteristics.

In order to solve the related-art problems, a reference voltage circuit according to one embodiment of the present invention is configured as follows.

The reference voltage circuit includes: a reference current generating circuit configured to convert a difference between forward voltages of a plurality of PN junction elements into current to generate a first current; a current generating circuit configured to use the first current generated by the reference current generating circuit to generate a second current; and a voltage generating circuit including a first resistive element and a second resistive element, the first resistive element being configured to generate a first voltage having positive temperature characteristics when the first current flows through the first resistive element, the second resistive element being configured to generate a second voltage having negative temperature characteristics when the first current and the second current flow through the second resistive element. The reference voltage circuit outputs a reference voltage obtained by adding the first voltage to the second voltage.

According to one embodiment of the present invention, an arbitrary output voltage can be adjusted to have arbitrary temperature characteristics.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Now, embodiments of the present invention are described referring to the drawings.

FIG. 1is a block diagram illustrating a basic configuration of a reference voltage circuit of the present invention. InFIG. 1, a reference current generating circuit11can convert a difference between the forward voltages of PN junction elements into current to generate a first current having an arbitrary value. A current generating circuit12uses the first current generated by the reference current generating circuit11to generate a second current. A voltage generating circuit13uses the first current generated by the reference current generating circuit11and the second current generated by the current generating circuit12to cause a predetermined current to flow through a resistor, to thereby generate voltage. Then, the generated voltage is output to an output terminal10as a reference voltage.

First Embodiment

FIG. 2is a circuit diagram illustrating a reference voltage circuit according to a first embodiment of the present invention.

The reference voltage circuit according to the first embodiment includes PMOS transistors111,112,113,114,116,118, and120, NMOS transistors115,117, and119, resistors131,132,104, and105PN junction elements102and103, a ground terminal100, a power supply terminal101, and an output terminal106. The PMOS transistors111,112,113, and114, the NMOS transistor115, and the resistor131form a current generating circuit140. The PMOS transistors116and118, the NMOS transistors117and119, the resistor132, and the PN junction elements102and103form a reference current generating circuit141. The PMOS transistor120and the resistors104and105form a voltage generating circuit142.

The connections are now described. The PMOS transistor111has a gate connected to a gate and a drain of the PMOS transistor112, a drain connected to a node between one terminal of the resistor104and one terminal of the resistor105, and a source connected to the power supply terminal101. The other terminal of the resistor104is connected to the output terminal106, and the other terminal of the resistor105is connected to the ground terminal100. The PMOS transistor112has the drain connected to a source of the PMOS transistor113, and a source connected to the power supply terminal101. The PMOS transistor113has a gate connected to a drain of the NMOS transistor115, and a drain connected to a source of the NMOS transistor115. The NMOS transistor115has the drain connected to a drain of the PMOS transistor114, a gate connected to a gate of the NMOS transistor119, and the source connected to one terminal of the resistor131. The other terminal of the resistor131is connected to the ground terminal100. The PMOS transistor114has a gate connected to a gate of the PMOS transistor116, and a source connected to the power supply terminal101. The PMOS transistor116has the gate connected to a gate of the PMOS transistor118, a drain connected to a drain of the NMOS transistor117, and a source connected to the power supply terminal101. The PMOS transistor118has the gate and a drain both connected to a drain of the NMOS transistor119, and a source connected to the power supply terminal101. The NMOS transistor117has a gate and the drain both connected to the gate of the NMOS transistor119, and a source connected to an anode of the PN junction element102. A cathode of the PN junction element102is connected to the ground terminal100. The resistor132has one terminal connected to a source of the NMOS transistor119, and the other terminal connected to an anode of the PN junction element103. A cathode of the PN junction element103is connected to the ground terminal100. The PMOS transistor120has a gate connected to the drain of the PMOS transistor118, a drain connected to the output terminal106, and a source connected to the power supply terminal101.

Next, the operation of the reference voltage circuit according to the first embodiment is described. For the sake of convenience and easy understanding, a description is given on the assumption that the resistors131,132,104, and105have no temperature dependence. The PN junction elements102and103are formed with an appropriate area ratio (for example, 1:4), and the reference current generating circuit141generates a current represented by Expression 1. Because it is assumed that the resistor132has no temperature dependence, the current to be generated has positive temperature characteristics.

I=1R132×k·Tq×ln⁡(m)(1)
where m represents the area ratio of the PN junction elements102and103, R132 represents a resistance value of the resistor132, k represents the Boltzmann constant, T represents temperature, and q represents electric charges.

The PMOS transistor114and the PMOS transistor118form a current mirror, and hence a current based on the current of the PMOS transistor118flows through the PMOS transistor114. For the sake of convenience and easy understanding, a description is given on the assumption that the same amount of a current I flows. The NMOS transistor115and the NMOS transistor117are the same in size, and have the gates connected to the gate of the NMOS transistor119. The source of the NMOS transistor117is referred to as a node X, the source of the NMOS transistor115is referred to as a node Z, and the node between one terminal of the resistor104and one terminal of the resistor105is referred to as a node W.

The NMOS transistor115and the PMOS transistor113form a negative feedback loop. Because of this, the current I stably flows through the NMOS transistor115from the PMOS transistor114, and the operating point of the NMOS transistor115is thus appropriately determined. The NMOS transistor115and the NMOS transistor117are applied with the same gate voltage and the same drain current, and hence the voltages of the node X and the node Z are the same. The resistance value of the resistor131is represented by R131, and a voltage generated at the PN junction element102is represented by V102. A current that flows through the PMOS transistor113is represented by Iz. The currents I and Iz flow through the resistor131, and hence a voltage of R131×(I+Iz) is generated at the resistor131. In addition, the voltages of the node X and the node Z are the same, and hence the voltage R131×(I+Iz) is equal to the voltage V102 of the node X.

The PMOS transistor111and the PMOS transistor112form a current mirror, and hence a current based on the current of the PMOS transistor112flows through the PMOS transistor111. For the sake of convenience and easy understanding, a description is given on the assumption that the same amount of the current Iz flows. The PMOS transistor120and the PMOS transistor118form a current mirror, and hence a current based on the current of the PMOS transistor118flows through the PMOS transistor120. For the sake of convenience and easy understanding, a description is given on the assumption that the same amount of the current I flows. When the resistance value of the resistor105is represented by R105 and the above-mentioned structure is employed, a predetermined current I+Iz flows through the resistor105, and hence a voltage of R105×(I+Iz) is generated at the resistor105. For the sake of convenience and easy understanding, the resistance values R105 and R131 are equal to each other, in other words, the voltage R131×(I+Iz) of the node Z and the voltage R105×(I+Iz) of the node W are equal to each other.

The voltage of the node X generated at the PN junction element102has negative temperature characteristics. Therefore, the voltage of the node Z and the voltage of the node W also have the negative temperature characteristics.

The current generated by the reference current generating circuit141has the positive temperature characteristics, and hence the current I flowing through the PMOS transistor120also has the positive temperature characteristics. When the resistance value of the resistor104is represented by R104, a voltage of I×R104 is generated across both ends of the resistor104, which has the positive temperature characteristics.

By appropriately setting the sum of the voltage R105×(I+Iz) of the node W having the negative temperature characteristics and the voltage I×R104 that has the positive temperature characteristics and is generated across both ends of the resistor104, an arbitrary output voltage having arbitrary temperature characteristics can be output to the output terminal106. This operation can be achieved by, for example, adjusting the current mirror ratio of the PMOS transistor118and the PMOS transistor120, the current mirror ratio of the PMOS transistor118and the PMOS transistor114, the current mirror ratio of the PMOS transistor112and the PMOS transistor111, and the resistance values of the resistor104and the resistor105.

In addition, as in the current generating circuit140illustrated inFIG. 8, the resistor131may be divided into resistors131ra,131rb, and131rc, and switch elements131sa,131sb, and131scmay be connected between the nodes of the respective resistors and the drain of the PMOS transistor113. By arbitrarily switching those switch elements to adjust the current Iz, it is possible to adjust the voltage of the output terminal106. Whether the resistor131is connected in series or in parallel, and the number of the resistors131are not limited to the configuration of the embodiment. Further, the material of the switch and the number of the switches are not limited to the configuration of the embodiment, and the switch may be a transistor or a fuse.

Note that, the PN junction element can be a saturated connected diode or bipolar transistor, or a MOS transistor operating in weak inversion, and is not limited to any specific form.

Note that, the above description is given on the assumption that the various current mirror ratios are equal to each other. However, as long as an arbitrary output voltage having arbitrary temperature characteristics can be output, the current mirror ratios are not specifically limited.

Note that, the NMOS transistor115and the NMOS transistor117are the same in size in the above description. However, the NMOS transistor115and the NMOS transistor117are not limited to be the same in size as long as the voltage values of the node X and the node Z can be adjusted by adjusting the resistor131and the current value of the current flowing through the PMOS transistor114.

Note that, the above description is given on the assumption that the various resistors have no temperature dependence, but the resistors may have temperature dependences. When such a relationship is established that the current I and the current Iz are obviously inversely proportional to the resistance values, an output voltage, which is to be generated when a current generated based on the relationship flows through the resistors, does not directly depend on the resistance values. It is therefore apparent that, as long as the condition is satisfied that the resistors have the same kind of temperature dependence, the same effect as described above can be expected even when the resistors have the temperature dependences.

Note that, as long as the current I can be generated, the configuration of the reference current generating circuit141is not limited to the configuration of the first embodiment.

Note that, as long as the current Iz can be generated, the configuration of the current generating circuit140is not limited to the configuration of the first embodiment.

Note that, as long as the output voltage can be generated, the configuration of the voltage generating circuit142is not limited to the configuration of the first embodiment.

As described above, according to the reference voltage circuit of the first embodiment, by appropriately setting the sum of the voltage having the negative temperature characteristics and the voltage having the positive temperature characteristics, an arbitrary output voltage having arbitrary temperature characteristics can be obtained.

Second Embodiment

FIG. 3is a circuit diagram illustrating a reference voltage circuit according to a second embodiment of the present invention.FIG. 3differs fromFIG. 2in that the configuration of the reference current generating circuit141is changed.

In the reference voltage circuit according to the second embodiment, the PMOS transistors116and118, an NMOS transistor202, the resistor132, the PN junction elements102and103, and an amplifier201form a reference current generating circuit241. Other configurations are the same as those of the reference voltage circuit according to the first embodiment illustrated inFIG. 2.

The connections are now described. The amplifier201has an inverting input terminal connected to a source of the NMOS transistor202and the anode of the PN junction element102, a non-inverting input terminal connected to one terminal of the resistor132and the drain of the PMOS transistor118, and an output terminal connected to the gate of the PMOS transistor114, the gate of the PMOS transistor116, the gate of the PMOS transistor118, and the gate of the PMOS transistor120. A gate and a drain of the NMOS transistor202are connected to the gate of the NMOS transistor115and the drain of the PMOS transistor116. Other connections are the same as those in the reference voltage circuit according to the first embodiment illustrated inFIG. 2.

Next, the operation of the reference voltage circuit according to the second embodiment is described. For the sake of convenience and easy understanding, a description is given on the assumption that the resistors131,132,104, and105have no temperature dependence. The PN junction elements102and103are formed with an appropriate area ratio (for example, 1:4), and the reference current generating circuit241generates a current represented by Expression 2. Because it is assumed that the resistor132has no temperature dependence, the current to be generated has positive temperature characteristics.

I=1R132×k·Tq×ln⁡(m)(2)
where m represents the area ratio of the PN junction elements102and103, R132 represents a resistance value of the resistor132, k represents the Boltzmann constant, T represents temperature, and q represents electric charges.

The PMOS transistors114,116,118, and120form a current mirror, and hence a current based on the size of each PMOS transistor flows through each PMOS transistor. For the sake of convenience and easy understanding, a description is given on the assumption that the same amount of a current I flows. The NMOS transistor115and the NMOS transistor202are the same in size, and have the gates connected in common to each other. The source of the NMOS transistor202is referred to as a node X, the source of the NMOS transistor115is referred to as a node Z, and the node between one terminal of the resistor104and one terminal of the resistor105is referred to as a node W.

The NMOS transistor115and the PMOS transistor113form a negative feedback loop. Because of this, the current I stably flows through the NMOS transistor115from the PMOS transistor114, and the operating point of the NMOS transistor115is thus appropriately determined. The NMOS transistor115and the NMOS transistor202are applied with the same gate voltage and the same drain current, and hence the voltages of the node X and the node Z are the same. The resistance value of the resistor131is represented by R131, and a voltage generated at the PN junction element102is represented by V102. A current that flows through the PMOS transistor113is represented by Iz. The currents I and Iz flow through the resistor131, and hence a voltage of R131×(I+Iz) is generated at the resistor131. In addition, the voltages of the node X and the node Z are the same, and hence the voltage R131×(I+Iz) is equal to the voltage V102.

The PMOS transistor111and the PMOS transistor112form a current mirror, and hence a current based on the current of the PMOS transistor112flows through the PMOS transistor111. For the sake of convenience and easy understanding, a description is given on the assumption that the same amount of the current Iz flows. The PMOS transistor120and the PMOS transistor116form a current mirror, and hence a current based on the current of the PMOS transistor116flows through the PMOS transistor120. For the sake of convenience and easy understanding, a description is given on the assumption that the same amount of the current I flows. When the resistance value of the resistor105is represented by R105 and the above-mentioned structure is employed, a predetermined current I+Iz flows through the resistor105, and hence a voltage of R105×(I+Iz) is generated at the resistor105. For the sake of convenience and easy understanding, the resistance values R105 and R131 are equal to each other, in other words, the voltage R131×(I+Iz) of the node Z and the voltage R105×(I+Iz) of the node W are equal to each other.

The voltage of the node X generated at the PN junction element102has negative temperature characteristics. Therefore, the voltage of the node Z and the voltage of the node W also have the negative temperature characteristics.

The current generated by the reference current generating circuit241has the positive temperature characteristics, and hence the current I flowing through the PMOS transistor120also has the positive temperature characteristics. When the resistance value of the resistor104is represented by R104, a voltage of I×R104 is generated across both ends of the resistor104, which has the positive temperature characteristics.

By appropriately setting the sum of the voltage R105×(I+Iz) of the node W having the negative temperature characteristics and the voltage I×R104 that has the positive temperature characteristics and is generated across both ends of the resistor104, an arbitrary output voltage having arbitrary temperature characteristics can be output to the output terminal106. This operation can be achieved by, for example, adjusting the current mirror ratio of the PMOS transistor116and the PMOS transistor120, the current mirror ratio of the PMOS transistor116and the PMOS transistor114, the current mirror ratio of the PMOS transistor112and the PMOS transistor111, and the resistance values of the resistor104and the resistor105.

In addition, as in the current generating circuit140illustrated inFIG. 8, the resistor131may be divided into the resistors131ra,131rb, and131rc, and the switch elements131sa,131sb, and131scmay be connected between the nodes of the respective resistors and the drain of the PMOS transistor113. By arbitrarily switching those switch elements to adjust the current Iz, it is possible to adjust the voltage of the output terminal106. Whether the resistor131is connected in series or in parallel, and the number of the resistors131are not limited to the configuration of the embodiment. Further, the material of the switch and the number of the switches are not limited to the configuration of the embodiment, and the switch may be a transistor or a fuse.

Note that, the PN junction element can be a saturated connected diode or bipolar transistor, or a MOS transistor operating in weak inversion, and is not limited to any specific form.

Note that, the above description is given on the assumption that the various current mirror ratios are equal to each other. However, as long as an arbitrary output voltage having arbitrary temperature characteristics can be output, the current mirror ratios are not specifically limited.

Note that, the NMOS transistor115and the NMOS transistor117are the same in size in the above description. However, the NMOS transistor115and the NMOS transistor117are not limited to be the same in size as long as the voltage values of the node X and the node Z can be adjusted by adjusting the resistor131and the current value of the current flowing through the PMOS transistor114.

Note that, the above description is given on the assumption that the various resistors have no temperature dependence, but the resistors may have temperature dependences. When such a relationship is established that the current I and the current Iz are obviously inversely proportional to the resistance values, an output voltage, which is to be generated when a current generated based on the relationship flows through the resistors, does not directly depend on the resistance values. It is therefore apparent that, as long as the condition is satisfied that the resistors have the same kind of temperature dependence, the same effect as described above can be expected even when the resistors have the temperature dependences.

Note that, as long as the current I can be generated, the configuration of the reference current generating circuit241is not limited to the configuration of the second embodiment.

Note that, as long as the current Iz can be generated, the configuration of the current generating circuit140is not limited to the configuration of the second embodiment.

Note that, as long as the output voltage can be generated, the configuration of the voltage generating circuit142is not limited to the configuration of the second embodiment.

As described above, according to the reference voltage circuit of the second embodiment, by appropriately setting the sum of the voltage having the negative temperature characteristics and the voltage having the positive temperature characteristics, an arbitrary output voltage having arbitrary temperature characteristics can be obtained.

Third Embodiment

FIG. 4is a circuit diagram illustrating a reference voltage circuit according to a third embodiment of the present invention.FIG. 3differs fromFIG. 2in that the configuration of the current generating circuit140is changed.

In the reference voltage circuit according to the third embodiment, PMOS transistors301and302, an NMOS transistor304, the resistor131, and an amplifier303form a current generating circuit340. Other configurations are the same as those of the reference voltage circuit according to the first embodiment illustrated inFIG. 2.

The connections are now described. The amplifier303has an inverting input terminal connected to a source of the NMOS transistor304and one terminal of the resistor131, a non-inverting input terminal connected to the source of the NMOS transistor117and the anode of the PN junction element102, and an output terminal connected to a gate of the NMOS transistor304. The other terminal of the resistor131is connected to the ground terminal100. The PMOS transistor302has a gate and a drain both connected to a drain of the NMOS transistor304, and a source connected to the power supply terminal101. The PMOS transistor301has a gate connected to the gate of the PMOS transistor302, a drain connected to the node between one terminal of the resistor104and one terminal of the resistor105, and a source connected to the power supply terminal101. Other connections are the same as those in the reference voltage circuit according to the first embodiment illustrated inFIG. 2.

Next, the operation of the reference voltage circuit according to the third embodiment is described. For the sake of convenience and easy understanding, a description is given on the assumption that the resistors131,132,104, and105have no temperature dependence. The PN junction elements102and103are formed with an appropriate area ratio (for example, 1:4), and the reference current generating circuit141generates the same current as that of the first embodiment. Because it is assumed that the resistor132has no temperature dependence, the current to be generated has positive temperature characteristics. The source of the NMOS transistor117is referred to as a node X, the source of the NMOS transistor304is referred to as a node Z, and the node between one terminal of the resistor104and one terminal of the resistor105is referred to as a node W.

The amplifier303and the NMOS transistor304form a negative feedback loop. Because of this, the voltages of the node X and the node Z are controlled to be the same.

The resistance value of the resistor131is represented by R131, and a voltage generated at the PN junction element102is represented by V102. A current that flows through the PMOS transistor113is represented by Iz. The current Iz flows through the resistor131, and hence a voltage of R131×Iz is generated at the resistor131. In addition, the voltages of the node X and the node Z are the same, and hence the voltage R131×Iz is equal to the voltage V102.

The PMOS transistor301and the PMOS transistor302form a current mirror, and hence a current based on the current of the PMOS transistor302flows through the PMOS transistor301. For the sake of convenience and easy understanding, a description is given on the assumption that the same amount of the current Iz flows. The PMOS transistor120and the PMOS transistor118form a current mirror, and hence a current based on the current of the PMOS transistor118flows through the PMOS transistor120. For the sake of convenience and easy understanding, a description is given on the assumption that the same amount of the current I flows. When the resistance value of the resistor105is represented by R105 and the above-mentioned structure is employed, the predetermined current I+Iz flows through the resistor105, and hence the voltage of R105×(I+Iz) is generated at the resistor105.

The voltage of the node X generated at the PN junction element102has negative temperature characteristics. Therefore, the voltage of the node Z also has the negative temperature characteristics.

In other words, the voltage R131×Iz has the negative temperature characteristics, and hence a voltage component R105×Iz, which is obtained by multiplying this voltage by a resistance ratio and is generated at the resistor105, also has the negative temperature characteristics.

On the other hand, the current generated by the reference current generating circuit141has the positive temperature characteristics, and hence the current I flowing through the PMOS transistor120also has the positive temperature characteristics. When the resistance value of the resistor104is represented by R104, the sum of a voltage component R104×I generated across both ends of the resistor104and a voltage component R105×I generated at the resistor105has the positive temperature characteristics.

By appropriately setting the sum of the voltage component R131×Iz having the negative temperature characteristics and the voltage components R104×I and R105×I having the positive temperature characteristics, an arbitrary output voltage having arbitrary temperature characteristics can be output to the output terminal106. This operation can be achieved by, for example, adjusting the current mirror ratio of the PMOS transistor116and the PMOS transistor120, the current mirror ratio of the PMOS transistor302and the PMOS transistor301, and the resistance values of the resistor104and the resistor105.

In addition, as in the current generating circuit340illustrated inFIG. 9, the resistor131may be divided into the resistors131ra,131rb, and131rc, and the switch elements131sa,131sb, and131scmay be connected between the nodes of the respective resistors and the inverting input terminal of the amplifier. By arbitrarily switching those switch elements to adjust the voltage of the output terminal106, it is possible to adjust the voltage of the output terminal106. Whether the resistor131is connected in series or in parallel, and the number of the resistors131are not limited to the configuration of the embodiment. Further, the material of the switch and the number of the switches are not limited to the configuration of the embodiment, and the switch may be a transistor or a fuse.

Note that, the PN junction element can be a saturated connected diode or bipolar transistor, or a MOS transistor operating in weak inversion, and is not limited to any specific form.

Note that, the above description is given on the assumption that the various current mirror ratios are equal to each other. However, as long as an arbitrary voltage having arbitrary temperature characteristics can be output, the current mirror ratios are not specifically limited.

Note that, the amplifier303is not limited to one form as long as the voltage values of the node X and the node Z can be adjusted.

Note that, the above description is given on the assumption that the various resistors have no temperature dependence, but the resistors may have temperature dependences. When such a relationship is established that the current I and the current Iz are obviously inversely proportional to the resistance values, an output voltage, which is to be generated when a current generated based on the relationship flows through the resistors, does not directly depend on the resistance values. It is therefore apparent that, as long as the condition is satisfied that the resistors have the same kind of temperature dependence, the same effect as described above can be expected even when the resistors have the temperature dependences.

Note that, as long as the current I can be generated, the configuration of the reference current generating circuit141is not limited to the configuration of the third embodiment.

Note that, as long as the current Iz can be generated, the configuration of the current generating circuit340is not limited to the configuration of the third embodiment.

Note that, as long as the output voltage can be generated, the configuration of the voltage generating circuit142is not limited to the configuration of the third embodiment.

As described above, according to the reference voltage circuit of the third embodiment, by appropriately setting the sum of the voltage having the negative temperature characteristics and the voltage having the positive temperature characteristics, an arbitrary output voltage having arbitrary temperature characteristics can be obtained.

Fourth Embodiment

FIG. 5is a circuit diagram illustrating a reference voltage circuit according to a fourth embodiment of the present invention.FIG. 5differs fromFIG. 3in that the configuration of the current generating circuit140is changed, and the NMOS transistor202is eliminated.

In the reference voltage circuit according to the fourth embodiment, the PMOS transistors301and302, the NMOS transistor304, the resistor131, and the amplifier303form the reference current generating circuit340. Other configurations are the same as those of the reference voltage circuit according to the second embodiment illustrated inFIG. 3.

The connections are now described. The amplifier303has the inverting input terminal connected to the source of the NMOS transistor304and one terminal of the resistor131, the non-inverting input terminal connected to the anode of PN junction element102, the drain of the PMOS transistor116, and the inverting input terminal of the amplifier203, and an output terminal connected to the gate of the NMOS transistor304. The other terminal of the resistor131is connected to the ground terminal100. The PMOS transistor302has the gate and the drain both connected to the drain of the NMOS transistor304, and a source connected to the power supply terminal101. The PMOS transistor301has the gate connected to the gate of the PMOS transistor302, the drain connected to the node between the resistor104and the resistor105, and the source connected to the power supply terminal101. Other connections are the same as those in the reference voltage circuit according to the second embodiment illustrated inFIG. 3.

Next, the operation of the reference voltage circuit according to the fourth embodiment is described. For the sake of convenience and easy understanding, a description is given on the assumption that the resistors131,132,104, and105have no temperature dependence. The PN junction elements102and103are formed with an appropriate area ratio (for example, 1:4), and a reference current generating circuit441generates a current having the positive temperature characteristics if the resistor132has no temperature dependence as in the second embodiment. The anode of the PN junction element102is referred to as a node X, the source of the NMOS transistor304is referred to as a node Z, and the node between the resistor104and the resistor105is referred to as a node W.

The amplifier303and the NMOS transistor304form a negative feedback loop. Because of this, the voltages of the node X and the node Z are controlled to be the same.

The resistance value of the resistor131is represented by R131, and a voltage generated at the PN junction element102is represented by V102. A current that flows through the PMOS transistor302is represented by Iz. The current Iz flows through the resistor131, and hence a voltage of R131×Iz is generated at the resistor131. In addition, the voltages of the node X and the node Z are the same, and hence the voltage R131×Iz is equal to the voltage V102.

The PMOS transistor301and the PMOS transistor302form a current mirror, and hence a current based on the current of the PMOS transistor302flows through the PMOS transistor301. For the sake of convenience and easy understanding, a description is given on the assumption that the same amount of the current Iz flows. The PMOS transistor120and the PMOS transistor118form a current mirror, and hence a current based on the current of the PMOS transistor118flows through the PMOS transistor120. For the sake of convenience and easy understanding, a description is given on the assumption that the same amount of the current I flows. When the resistance value of the resistor105is represented by R105 and the above-mentioned structure is employed, the predetermined current I+Iz flows through the resistor105, and hence the voltage of R105×(I+Iz) is generated at the resistor105.

The voltage of the node X generated at the PN junction element102has negative temperature characteristics. Therefore, the voltage of the node Z also has the negative temperature characteristics.

In other words, the voltage R131×Iz has the negative temperature characteristics, and hence the voltage component R105×Iz, which is obtained by multiplying this voltage by a resistance ratio and is generated at the resistor105, also has the negative temperature characteristics.

On the other hand, the current generated by the reference current generating circuit441has the positive temperature characteristics, and hence the current I flowing through the PMOS transistor120also has the positive temperature characteristics. When the resistance value of the resistor104is represented by R104, the sum of a voltage component R104×I generated across both ends of the resistor104and a voltage component R105×I generated at the resistor105has the positive temperature characteristics.

By appropriately setting the sum of the voltage component R131×Iz having the negative temperature characteristics and the voltage components R104×I and R105×I having the positive temperature characteristics, an arbitrary output voltage having arbitrary temperature characteristics can be output to the output terminal106. This operation can be achieved by, for example, adjusting the current mirror ratio of the PMOS transistor116and the PMOS transistor120, the current mirror ratio of the PMOS transistor302and the PMOS transistor301, and the resistance values of the resistor104and the resistor105.

In addition, as in the current generating circuit340illustrated inFIG. 9, the resistor131may be divided into the resistors131ra,131rb, and131re, and the switch elements131sa,131sb, and131scmay be connected between the nodes of the respective resistors and the inverting input terminal of the amplifier. By arbitrarily switching those switch elements to adjust the voltage of the output terminal106, it is possible to adjust the voltage of the output terminal106. Whether the resistor131is connected in series or in parallel, and the number of the resistors131are not limited to the configuration of the embodiment. Further, the material of the switch and the number of the switches are not limited to the configuration of the embodiment, and the switch may be a transistor or a fuse.

Note that, the PN junction element can be a saturated connected diode or bipolar transistor, or a MOS transistor operating in weak inversion, and is not limited to any specific form.

Note that, the above description is given on the assumption that the various current mirror ratios are equal to each other. However, as long as an arbitrary output voltage having arbitrary temperature characteristics can be output, the current mirror ratios are not specifically limited.

Note that, the amplifier303is not limited to one form as long as the voltage values of the node X and the node Z can be adjusted.

Note that, the above description is given on the assumption that the various resistors have no temperature dependence, but the resistors may have temperature dependences. When such a relationship is established that the current I and the current Iz are obviously inversely proportional to the resistance values, an output voltage, which is to be generated when a current generated based on the relationship flows through the resistors, does not directly depend on the resistance values. It is therefore apparent that, as long as the condition is satisfied that the resistors have the same kind of temperature dependence, the same effect as described above can be expected even when the resistors have the temperature dependences.

Note that, as long as the current I can be generated, the configuration of the reference current generating circuit441is not limited to the configuration of the fourth embodiment.

Note that, as long as the current Iz can be generated, the configuration of the current generating circuit340is not limited to the configuration of the fourth embodiment.

Note that, as long as the output voltage can be generated, the configuration of the voltage generating circuit142is not limited to the configuration of the fourth embodiment.

As described above, according to the reference voltage circuit of the fourth embodiment, by appropriately setting the sum of the voltage having the negative temperature characteristics and the voltage having the positive temperature characteristics, an arbitrary output voltage having arbitrary temperature characteristics can be obtained.

Fifth Embodiment

FIG. 6is a circuit diagram illustrating a reference voltage circuit according to a fifth embodiment of the present invention.FIG. 6differs fromFIG. 2in that the configurations of the current generating circuit140and the voltage generating circuit142are changed.

The reference voltage circuit according to the fifth embodiment includes PMOS transistors511and520, resistors504and505, and an output terminal506. The PMOS transistors111,112,113,114, and511, the NMOS transistor115, and the resistor131form a current generating circuit540. The PMOS transistors120and520, the resistors504,505,104, and105form a voltage generating circuit542. Other configurations are the same as those in the reference voltage circuit according to the first embodiment illustrated inFIG. 2.

The connections are now described. The PMOS transistor511has a gate connected to the gate of the PMOS transistor111, a drain connected to a node between one terminal of the resistor504and one terminal of the resistor505, and a source connected to the power supply terminal101. The other terminal of the resistor505is connected to the ground terminal100. The PMOS transistor520has a gate connected to the gate of the PMOS transistor120, a source connected to the power supply terminal101, and a drain connected to the output terminal506and the other terminal of the resistor504. Other connections are the same as those in the reference voltage circuit according to the first embodiment illustrated inFIG. 2.

Next, the operation of the reference voltage circuit according to the fifth embodiment is described. For the sake of convenience and easy understanding, a description is given on the assumption that the resistors131,132,104,105,504, and505have no temperature dependence. The PN junction elements102and103are formed with an appropriate area ratio (for example, 1:4), and the reference current generating circuit141generates a current having the positive temperature characteristics if the resistor132has no temperature dependence as in the first embodiment. The anode of the PN junction element102is referred to as a node X, the source of the NMOS transistor115is referred to as a node Z, the node between the resistor104and the resistor105is referred to as a node W, and the node between the resistor504and the resistor505is referred to as a node Y.

The NMOS transistor115and the PMOS transistor113form a negative feedback loop. Because of this, the current I stably flows through the NMOS transistor115from the PMOS transistor114, and the operating point of the NMOS transistor115is thus appropriately determined. The NMOS transistor115and the NMOS transistor117are applied with the same gate voltage and the same drain current, and hence the voltages of the node X and the node Z are the same. The resistance value of the resistor131is represented by R131, and a voltage generated at the PN junction element102is represented by V102. A current that flows through the PMOS transistor113is represented by Iz. The currents I and Iz flow through the resistor131, and hence a voltage of R131×(I+Iz) is generated at the resistor131. In addition, the voltages of the node X and the node Z are the same, and hence the voltage R131×(I+Iz) is equal to the voltage V102 of the node X.

The PMOS transistor111and the PMOS transistor112form a current mirror, and hence a current based on the current of the PMOS transistor112flows through the PMOS transistor111. For the sake of convenience and easy understanding, a description is given on the assumption that the same amount of the current Iz flows. The PMOS transistor120and the PMOS transistor118form a current mirror, and hence a current based on the current of the PMOS transistor118flows through the PMOS transistor120. For the sake of convenience and easy understanding, a description is given on the assumption that the same amount of the current I flows. When the resistance value of the resistor105is represented by R105 and the above-mentioned structure is employed, a predetermined current I+Iz flows through the resistor105, and hence a voltage of R105×(I+Iz) is generated at the resistor105. For the sake of convenience and easy understanding, the resistance values R105 and R131 are equal to each other, in other words, the voltage R131×(I+Iz) of the node Z and the voltage R105×(I+Iz) of the node W are equal to each other.

The PMOS transistor511and the PMOS transistor112form a current mirror, and hence a current based on the current of the PMOS transistor112flows through the PMOS transistor511. For the sake of convenience and easy understanding, a description is given on the assumption that the same amount of the current Iz flows. The PMOS transistor520and the PMOS transistor118form a current mirror, and hence a current based on the current of the PMOS transistor118flows through the PMOS transistor520. For the sake of convenience and easy understanding, a description is given on the assumption that the same amount of the current I flows. When the resistance value of the resistor505is represented by R505 and the above-mentioned structure is employed, a predetermined current I+Iz flows through the resistor505, and hence a voltage of R505×(I+Iz) is generated at the resistor505. For the sake of convenience and easy understanding, the resistance values R505 and R131 are equal to each other, in other words, the voltage R131×(I+Iz) of the node Z and the voltage R505×(I+Iz) of the node Y are equal to each other.

The voltage of the node X generated at the PN junction element102has negative temperature characteristics. Therefore, the voltage of the node Z and the voltages of the node W and the node Y also have the negative temperature characteristics.

The current generated by the reference current generating circuit141has the positive temperature characteristics, and hence the current I flowing through the PMOS transistors120and520also has the positive temperature characteristics. When the resistance value of the resistor104is represented by R104, a voltage of I×R104 is generated across both ends of the resistor104, which has the positive temperature characteristics. When the resistance value of the resistor504is represented by R504, a voltage of I×R504 is generated across both ends of the resistor504, which has the positive temperature characteristics.

By appropriately setting the sum of the voltage R105×(I+Iz) of the node W having the negative temperature characteristics and the voltage I×R104 that has the positive temperature characteristics and is generated across both ends of the resistor104, an arbitrary output voltage having arbitrary temperature characteristics can be output to the output terminal106. This operation can be achieved by, for example, adjusting the current mirror ratio of the PMOS transistor118and the PMOS transistor120, the current mirror ratio of the PMOS transistor118and the PMOS transistor114, the current mirror ratio of the PMOS transistor112and the PMOS transistor111, and the resistance values of the resistor104and the resistor105.

By appropriately setting the sum of the voltage R505×(I+Iz) of the node Y having the negative temperature characteristics and the voltage I×R504 that has the positive temperature characteristics and is generated across both ends of the resistor504, an arbitrary output voltage having arbitrary temperature characteristics can be output to the output terminal506. This operation can be achieved by, for example, adjusting the current mirror ratio of the PMOS transistor118and the PMOS transistor520, the current mirror ratio of the PMOS transistor118and the PMOS transistor114, the current mirror ratio of the PMOS transistor112and the PMOS transistor511, and the resistance values of the resistor504and the resistor505.

In addition, as in the current generating circuit140illustrated inFIG. 8, the resistor131may be divided into the resistors131ra,131rb, and131rc, and the switch elements131sa,131sb, and131scmay be connected between the nodes of the respective resistors and the drain of the PMOS transistor113. By arbitrarily switching those switch elements to adjust the current Iz, it is possible to adjust the voltages of the output terminal106and506. Whether the resistor131is connected in series or in parallel, and the number of the resistors131are not limited to the configuration of the embodiment. Further, the material of the switch and the number of the switches are not limited to the configuration of the embodiment, and the switch may be a transistor or a fuse.

Note that, the PN junction element can be a saturated connected diode or bipolar transistor, or a MOS transistor operating in weak inversion, and is not limited to any specific form.

Note that, the above description is given on the assumption that the various current mirror ratios are equal to each other. However, as long as an arbitrary output voltage having arbitrary temperature characteristics can be output, the current mirror ratios are not specifically limited.

Note that, the NMOS transistor115and the NMOS transistor117are the same in size in the above description. However, the NMOS transistor115and the NMOS transistor117are not limited to be the same in size as long as the voltage values of the node X and the node Z can be adjusted by adjusting the resistor131and the current value of the current flowing through the PMOS transistor114.

Note that, the above description is given on the assumption that the various resistors have no temperature dependence, but the resistors may have temperature dependences. When such a relationship is established that the current I and the current Iz are obviously inversely proportional to the resistance values, an output voltage, which is to be generated when a current generated based on the relationship flows through the resistors, does not directly depend on the resistance values. It is therefore apparent that, as long as the condition is satisfied that the resistors have the same kind of temperature dependence, the same effect as described above can be expected even when the resistors have the temperature dependences.

Note that, as long as the current I can be generated, the configuration of the reference current generating circuit141is not limited to the configuration of the fifth embodiment.

Note that, as long as the current Iz can be generated, the configuration of the current generating circuit540is not limited to the configuration of the fifth embodiment.

Note that, as long as the output voltage can be generated, the configuration of the voltage generating circuit542is not limited to the configuration of the fifth embodiment.

Note that, the output voltages of two different magnitudes are exemplified in the fifth embodiment. However, even when there are output voltages of more different magnitudes, by similarly increasing the number of the output terminals of the current generating circuit540, it is possible to adjust each output voltage to have arbitrary temperature characteristics and an arbitrary output voltage value. In addition, the number of the current generating circuits540may be increased to individually adjust the voltages of the output terminals106and506.

As described above, according to the reference voltage circuit of the fifth embodiment, by appropriately setting the sum of the voltage having the negative temperature characteristics and the voltage having the positive temperature characteristics, an arbitrary output voltage having arbitrary temperature characteristics can be obtained. Further a second voltage having a different output voltage value and different temperature characteristics can be output.