Heterojunction bipolar transistor and method of manufacturing the same

A bipolar transistor is supported by a single-crystal silicon substrate including a collector contact region. A first epitaxial region forms a collector region of a first conductivity type on the collector contact region. A second epitaxial region forms a base region of a second conductivity type. Deposited semiconductor material forms an emitter region of the first conductivity type. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region.

TECHNICAL FIELD

The present disclosure relates to a heterojunction bipolar transistor and to a method of manufacturing a heterojunction bipolar transistor.

BACKGROUND

For high-frequency applications, bipolar transistors, and in particular heterojunction bipolar transistors (HBT), are currently used. It is known to integrate bipolar transistors in standard CMOS methods.

The fabrication of a bipolar transistor from a stack of semiconductor regions forming the emitter, the base, and the collector of the transistor poses various problems. In particular, a problem is to form a base contact region while keeping a low resistance of access to the base region and a low stray capacitance between the base and the collector.

United States Patent Application Publication No. 2017/0236923, incorporated by reference, teaches a heterojunction bipolar transistor and method of manufacturing. Concerns with this heterojunction bipolar transistor and method of manufacturing include: the process flow is too complicated; the resulting device suffers from concerns with robustness; the nitride remaining at the end of the process flow contributes to reliability issues; the process is difficult to implement at small processing nodes (such as 28 nm) due to the height of the structure leading to difficulties with premetallization dielectric construction and contact patterning modification; and the emitter resistance is not optimal due to the emitter “plug” effect (a key parameter for high speed operation).

It would thus be desirable to have a heterojunction bipolar transistor and a method of manufacturing a heterojunction bipolar transistor that solves at least some of the foregoing problems.

SUMMARY

In an embodiment, a method is provide for manufacturing a bipolar transistor in a structure including a single-crystal silicon substrate coated in succession with a first insulating layer, a silicon layer and a stack of layers comprising a sacrificial layer made of a first material arranged between two insulating layers made of a second material selectively etchable over the first material. The method comprises the steps of: a) etching an opening through the stack of layers, the silicon layer and the first insulating layer to expose a top surface of the substrate; b) laterally recessing the silicon layer within the opening to form an open region that annularly surrounds the opening; c) in the opening, forming by selective epitaxy from the top surface of the substrate, to a level higher than a lower level of the stack, a collector region made of semiconductor material doped with a first conductivity type, wherein the collector region closes off the annular open region to form an annular air spacer between the collector region and the silicon layer; d) in the opening, further forming by selective epitaxy from a top surface of the collector region, to a level at least as high as an upper level of the sacrificial layer, a base region made of semiconductor material doped with a second conductivity type; e) in the opening, further forming by deposition on a top surface of the base region, an emitter region made of semiconductor material doped with the first conductivity type; f) etching said stack to reach the sacrificial layer; g) removing the sacrificial layer to expose a side wall of the base region; and h) forming a first portion of a base contact region by epitaxy from the side wall of the base region exposed by the removal of the sacrificial layer.

In an embodiment, a bipolar transistor comprises: a single-crystal semiconductor substrate; a first insulating layer over the single-crystal semiconductor substrate; a silicon layer over the first insulating layer; a stack of layers over the silicon layer; an opening extending through the stack of layers, the silicon layer and the first insulating layer; a recess of the silicon layer providing an open region that annularly surrounds the opening; a semiconductor collector region doped with a first conductivity type within the opening and resting on the single-crystal semiconductor substrate, said semiconductor collector region closing off the annular open region to form an annular open spacer between the semiconductor collector region and the silicon layer; a semiconductor base region doped with a second conductivity type on top of the semiconductor collector region; a semiconductor emitter region doped with the first conductivity type on the semiconductor base region and laterally extending beyond the base semiconductor region; and a single crystal base contact region extending from a side wall of the semiconductor base region and lying between two insulating layers of said stack.

In an embodiment, a method comprises: forming a collector contact region doped with a first conductivity type in a semiconductor substrate; providing a first insulating layer over the collector contact region; providing a first silicon layer over the first insulating layer; depositing a stack of layers over the first silicon layer, said stack of layers comprising a second insulating layer, a sacrificial layer and a third insulating layer; etching an opening extending through the stack of layers, the first silicon layer and the first insulating layer to expose a portion of the semiconductor substrate at said collector contact region; laterally recessing the first silicon layer within the opening to form an open region that annularly surrounds the opening; epitaxially growing in said opening from the exposed portion of the semiconductor substrate a collector region doped with the first conductivity type that closes said open region to form an annular open spacer; epitaxially growing in said opening from the collector region a base region doped with a second conductivity type; depositing a second silicon layer doped with the first conductivity type in said opening on the base semiconductor layer to form an emitter region; selectively removing the sacrificial layer to expose a side wall of said base region; and epitaxially growing from the exposed side wall a first portion of a base contact region.

DETAILED DESCRIPTION

The same elements have been designated with the same reference numerals in the various drawings and, further, the various drawings are not to scale. For clarity, only those elements which are useful to the understanding of the described embodiments have been shown and are detailed. In particular, certain masks used during the steps of the manufacturing method described hereafter have not been shown.

In the following description, terms “high”, “side”, “lateral”, “top”, “above”, “under”, “on”, “upper”, and “lower” refer to the orientation of the concerned elements in the corresponding drawings.

InFIG. 1, a structure comprises a single-crystal silicon substrate101including insulating structures103, for example, of the deep trench isolation (DTI) type, are provided to delimit a location where a heterojunction bipolar transistor is desired to be formed. At the location of the transistor, substrate101comprises a heavily-doped region105of a first conductivity type, for example, type N. The region105is flush with the upper (top) surface of substrate101and forms a collector contact region for the heterojunction bipolar transistor.

The upper surface of substrate101is coated with an insulating layer107(that is made of silicon dioxide, for example) that is coated with a semiconductor material (for example, silicon) layer109. Layer109may be a polysilicon layer deposited on insulating layer107. Layer109may also be a single-crystal silicon layer. As an example, the layer109may correspond to the silicon layer of a structure of SOI (Semiconductor On Insulator) type. Layer109may have a doping of a second conductivity type, for example, type P.

The deep trench isolation insulating structures103may be formed before the deposition of each of the layers forming the stack of layers111, particularly in the case where silicon layer109is the silicon layer of an SOI-type structure.

A stack of layers111rests on layer109. The stack111comprises a first insulating layer119that is coated with a second insulating layer113(also referred to herein as a first sacrificial layer) that is coated with a third insulating layer115that is coated with a fourth insulating layer117(also referred to herein as a second sacrificial layer). The material of layers115and119and the material of layers113and117are selected to be selectively etchable over each other. In an embodiment, the layers113and117are made of silicon nitride and the layers115and119are made of silicon oxide. The stack111may, for example, have a thickness of 80 nm (which is thinner than a comparable stack of United States Patent Application Publication No. 2017/0236923).

FIG. 2shows the structure after the etching of an opening121that crosses completely through the stack111, the silicon layer109, and the insulating layer107all the way to reach the collector contact region105at the top surface of the substrate101. The etch process used may, for example, comprise major anisotropic and minor isotropic etch steps.

FIG. 3shows the structure after forming, in opening21, a transistor collector region125of the heterojunction bipolar transistor. The collector region125is made of a region of single-crystal silicon formed by selective epitaxy from the top surface of substrate101. The collector region125has a thickness such that a top surface of the collector region125is at least as high as a top surface of the layer109and lower than or equal to a bottom surface of layer115. Preferably, the level of the top surface of collector region125is slightly lower, for example, by from 1 to 3 nm, than the lower surface of layer115. The collector region125is doped during the epitaxy or by implantation after the epitaxy with the first conductivity type. As an example, the collector region125is doped with phosphorus atoms, possibly associated with carbon atoms to limit the exodiffusion of phosphorus atoms, and/or with arsenic atoms.

Because the lateral walls of opening121are not covered by an insulating layer, there is a lateral etching of the silicon layer109caused by the cycled epitaxial process, and this lateral etch forms open regions126at the side edge of the collector125. The open regions126are laterally closed off by the epitaxial growth of the collector region125to form air spacers between the sidewalls of the collector125and the semiconductor layer109. The open regions126completely surround the collector region125, and in this configuration will annularly surround the opening121. The annular region126is thus closed off by the epitaxially grown collector region125. The annular region126may, for example, have cross-sectional dimensions of a height in the range of 10-30 nm and a width in the range of 10-50 nm.

Details of the cyclical epitaxy process used in the formation of the collector region125are provided in U.S. patent application Ser. No. 15/783,109, filed Oct. 13, 2017 entitled “Cyclic Epitaxy Process to Form Air Gap for Isolation for a Bipolar Transistor.”

FIG. 4shows the structure after the forming, in opening121, a transistor base region127comprising a stack of a doped region127aand a silicon capping region127b. The doped region127aof the transistor base region127is made of a single-crystal semiconductor material such as silicon or, preferably, silicon-germanium as in the present embodiment. Doped region127ais formed by selective epitaxy from collector region125. The doped region127ahas a thickness such that a top surface of the doped region127ais higher than a top surface of the insulating layer113but below the top surface of the layer115. The doped region127ais doped with the second conductivity type, preferably during the epitaxy. As an example, doped region127ais doped with boron atoms, possibly associated with carbon atoms to avoid the exodiffusion of the boron atoms. The silicon capping region127bis made of undoped single crystal semiconductor material and is formed by selective epitaxy from the top surface of the doped region127a. The silicon capping region127bhas a thickness such that a top surface of the silicon capping region127bis below the top surface of the layer115.

InFIG. 5, spacers129have been formed in the opening121. The spacers129rest on the top surface of silicon capping region127band border the sidewall surfaces of at least the layer115. An opening123is provided between the spacers129to expose a top surface of the silicon capping region127b. The spacers129have, for example, in cross-sectional view, an L shape. As an example, the spacers129are made of silicon oxide. The spacers are formed by forming a silicon oxide layer on the sidewalls of the layer115and top surface of the silicon capping region127bin the opening121. A nitride deposit is then made on the silicon oxide layer followed by an etch which preferentially removes nitride material from horizontal surfaces. The nitride material remaining after the etch forms a “D” shape spacer131which functions as a mask. This mask is used for perform a further etch to remove a portion of the silicon oxide layer to make the opening123.

The remaining nitride material of the spacer131for the etch mask as well as the silicon nitride layer (second sacrificial layer)117are then removed by using an isotropic etching process. The result is shown inFIG. 6.

A silicon layer133doped with the first conductivity type is deposited all over the structure and fills openings121and123. As an example, the silicon layer is deposited by RTCVD (“Reduced Temperature Chemical Vapor Deposition”), which enables the deposited silicon to be monocrystalline at the interface with the silicon capping region127bof the transistor base region127. A chemical mechanical polish may then be performed to planarize the top surface of the layer133. An etch mask formed by a layer135(made of silicon oxide, for example) is then formed on the planar top surface of layer133. The result is shown inFIG. 7.

Convention lithographic processing is then performed to pattern the etch mask layer135. An anisotropic etch is then performed to remove the unmasked portion of the doped silicon layer133and the unmasked portion of the oxide layer115all the way to nitride layer113. The result is shown inFIG. 8. Thus, a portion133′ of the silicon layer133is left in place and forms the emitter region of the heterojunction bipolar transistor. The emitter region133′ comprises a central portion resting on the transistor base region127at silicon capping region127b(extending through the opening123) and a peripheral portion that laterally extends beyond the base region127and rests on a remaining portion of the layer115.

A deposition of a silicon oxide layer141is made to cover the top of layer135and the side walls of the emitter region133′ and the side walls of the remaining portion of the oxide layer115. Then, an anisotropic etch is performed to remove the silicon oxide from the top surface of the first sacrificial layer113. The result is shown inFIG. 9. In an embodiment, the layer135may be removed prior to the deposition of layer141.

In the step illustrated byFIG. 10, the first sacrificial nitride layer113has been removed by isotropic etching selective over the material of layers115,119and141. This exposes the lateral side wall of the base region127(more specifically, a lateral side wall of the doped region127a).

FIG. 11shows the structure after formation of a first portion149of a base contact region151. The first portion149is made of single-crystal silicon formed by selective epitaxy from the lateral side wall of the base region127. Thus, the portion149of the base contact region151is monocrystalline, which advantageously enables to decrease the resistance at the interface between base contact region151and base region127with respect to the case of a transistor which would have its base contact region made of polysilicon. In this example, the first portion149of base contact region151extends laterally all the way at least to the peripheral edge of the remaining portion of layer141.

Conventional isotropic etching techniques are then used to selectively remove a portion of insulating layer119and expose a top surface of the semiconductor layer109. The result is shown inFIG. 12.

FIG. 13shows the structure after formation of a second portion153of the base contact region151. The second portion153is made of polycrystalline silicon formed by selective epitaxy of doped silicon of the second conductivity type from the top surface of the polysilicon semiconductor layer109and the lateral side wall of the first portion149. In the case where silicon layer109was not doped at the step ofFIG. 1, it may be doped by diffusion of dopant atoms from the base contact region151, and in particular from the first portion149.

An example of the configuration for making electrical contact to the emitter (E), base (B) and collector (C) terminals of the heterojunction bipolar transistor is shown inFIG. 14. A premetallization dielectric layer161covers the structure. A layer of silicide163is provided at each contact location with the collector contact region105, the emitter region133′ and the base contact region151. A metal contact plug165extends through the premetallization dielectric layer161to make contact with the silicide163.

Advantageously, if the starting point for the substrate is a SOI-type structure, then the semiconductor layer109is made of single-crystal silicon and the second portion153of base contact region151will also be made of single-crystal silicon grown by selective epitaxy. Advantageously, the entire base contact region151in such an implementation will be made of single-crystal silicon which enables to decrease the resistance of base contact region151, and thus decrease the resistance of access to the base region127with respect to the case of a transistor where all or part of the base contact region is made of polysilicon.

Access to the collector contact region105for the purpose of exposing the top surface of the substrate101can be achieved by forming a mask over the emitter region133′ and on portions of the base contact region151that laterally extend adjacent to the emitter region133′. An etch may then be performed through the mask. The premetallization dielectric layer161may then be deposited over the structures.

The silicide process to form silicide layers163may be performed using well known techniques at any suitable point in the fabrication process. The silicide layers163are formed at the upper surface of the emitter region133′, on the upper surface of collector contact region105, and on the upper surface of the base contact region151.

In an alternative implementation, the first and second portions149and153of the base contact region151may be formed simultaneously. To achieve this, the nitride layer113is removed to expose the lateral side wall of the base region127and the portion of insulating layer119is removed to expose the top surface of the semiconductor layer109. These removal steps are performed prior to performing any epitaxial growth. Then, the first and second portions149and153are simultaneously formed by epitaxy from the side wall of base region127and the top surface of silicon layer109. A structure similar to that shown inFIG. 12is then obtained.

In the transistor ofFIG. 14, the base contact region151is insulated from the collector region125by the air spacer126and the remaining portion of the layer119. The base contact region151makes contact with the base region127at the level of at least part of the side wall of the base region127. This structure minimizes the risk of diffusion of dopant atoms from the base contact region151to the collector region125. As a result, there is a reduction in base-collector capacitance. Still further, this permits an increase in the doping level of the base contact region151so as to achieve a decrease in access resistance to the base region127without concern that this increased doping will lead to an increase in the base-collector capacitance.

Advantageously, in the transistor ofFIG. 14, the shortest conductive path between the base region127and silicide163for the base contact region151is made of single-crystal semiconductor material. As a result, the resistance of access to the base region127is reduced.

Further, in the transistor ofFIG. 14, the separation between the upper level of base contact region151and the lower level of emitter region133′ can be controlled by the process step of epitaxial growth of the second portion153so as to decrease the stray capacitance between base contact region151and the emitter region133′.

Advantageously, the previously-described method enables to form in self-aligned fashion the collector region125, base region127, and emitter region133′ of a bipolar transistor without providing many masking and/or etch steps.

Each step of the previously-described method is a step currently used in standard CMOS methods, whereby this method is compatible with standard CMOS methods.

As an example, the various previously-described layers, regions, portions may have the following dimensions:a thickness in the range from 10 to 75 nm, for example, 25 nm, for insulating layer107;a thickness in the range from 3 to 20 nm, for example, 7 nm, for silicon layer109;a thickness in the range from 10 to 40 nm, for example, 20 nm, for insulating layer113;a thickness in the range from 5 to 20 nm, for example, 10 nm, for insulating layer119;a thickness in the range from 10 to 50 nm, for example, 25 nm, for layers115and117;a width from 0.1 to 0.3 μm, for example, 0.2 μm, for opening121; anda thickness in the range from 50 to 200 nm, for example, 75 nm, for the silicon layer133.

The doping levels of the various previously-described layers, regions, portions will be selected conventionally.

Specific embodiments have been described. Various alterations, modifications, and improvements will occur to those skilled in the art. In particular, the number and the order of the steps of the previously-described method may be adapted by those skilled in the art. For example, the steps of cleaning the exposed surfaces of the semiconductor regions from which the epitaxies are performed may be provided before each epitaxy step. Additional spacer structures may be provided as needed. During the step of forming the collector region125, only a central and/or lower portion of region125may be doped by selective implantation of dopant atoms.

It will readily occur to those skilled in the art that the previously-indicated conductivity types for the layers, regions, etc. may all be inverted.

Although an embodiment of a method where the base region127is made of silicon-germanium has been described, the base region127may also be formed by epitaxy of silicon, germanium, or another semiconductor material capable of growing by epitaxy from silicon and from which silicon can grow by epitaxy. For example, this method may be used to manufacture transistors using III-V semiconductors.