Semiconductor integrated circuit including a DRAM and an analog circuit

A semiconductor device including an interlayer insulation film formed on a substrate so as to cover first and second regions defined on the substrate, and a capacitor formed over the interlayer insulation film in the first region, wherein the interlayer insulation film includes, in the first region, a stepped part defined by a groove having a bottom surface lower in level than a surface of the interlayer insulation film in the second region.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to semiconductor devices and more particularly to a semiconductor device having a capacitor and a fabrication process thereof.

2. Description of the Related Art

A DRAM is a high-speed semiconductor memory device that stores information in a capacitor formed therein monolithically in the form of electric charges. Thus, DRAMs are used extensively in information processing apparatuses such as a computer as a memory device.

In these days, there is a demand for a semiconductor device in which a DRAM and an analog circuit device are formed monolithically on a common semiconductor substrate. Such an analog circuit device generally includes a capacitor formed in the monolithic state.

FIG. 1shows the construction of a conventional DRAM10.

Referring toFIG. 1, the DRAM10is formed on a Si substrate11on which a memory cell region10A and a peripheral region10B are formed, wherein each of the memory cell region10A and the peripheral region10B includes an active region defined by a field oxide film12. Further, in the active region defined in the cell region10A by the field oxide film12, there are formed polysilicon gate electrodes13A–13C on respective gate oxide films13a–13cas word lines WL. In the substrate11, there are formed diffusion regions11a–11eadjacent to the gate electrodes13A–13C as represented inFIG. 1, wherein each of the gate electrodes13A–13C carries a pair of side wall insulation films. This side wall insulation film may be omitted.

Similarly, there is formed a gate electrode13D in the peripheral region10B via a gate insulation film13d, and diffusion regions11fand11gare formed in the substrate11adjacent to the gate electrode13D. Further, there is formed a high-concentration diffusion region11hin the peripheral region10B in correspondence to a region isolated by the field oxide film12, and there is formed a capacitor electrode13E on the foregoing high-concentration diffusion region11hvia an intervening insulation film13e. It should be noted that the insulation film13ecorresponds to the gate insulation film13dof the gate electrode13D. As a result, the insulation film13eform, together with the capacitor electrode13E and the diffusion region11h, a capacitor C of the analog circuit device that is formed in the peripheral region10B.

It should be noted that the gate electrodes13A–13D, the word line WL, and further the capacitor electrode13E are covered by a first interlayer insulation film14formed on the substrate11so as to continuously cover the foregoing regions10A and10B, and contact holes14A–14C are formed in the interlayer insulation film14so as to expose the diffusion regions11b,11dand11frespectively. It should be noted that the contact holes14A–14C have respective side walls covered by side wall insulation films14a–14c, and bit line electrodes15A and15B are provided on the interlayer insulation film14so as to cover the contact holes14A and14B. Further, an electrode15C is formed on the interlayer insulation film14so as to cover the contact hole14C. Thereby, the side wall insulation film14aprevents the short-circuit between the electrode15A and the electrode13A in the case the position of the contact hole14A is offset. The side wall insulation films14band14cfunction similarly.

Further, the electrodes15A–15C are covered by a second interlayer insulation film16formed on the interlayer insulation film14, and contact holes16A and16B are formed in the interlayer insulation film16so as to expose the diffusion regions11aand11cin the memory cell region10A. The contact holes16A and16B are formed with respective side wall insulation films16aand16b, and polysilicon accumulation electrodes17A and17B are formed on the interlayer insulation film16so as to cover the contact holes16A and16B respectively. Thereby, the side wall insulation films16aand16bprevent the short-circuit between the accumulation electrode17A or17B with the adjacent gate electrode13A or13B.

In the memory cell region10A, it should be noted that the accumulation electrodes17A and17B are covered by a dielectric film18, and the dielectric film18in turn is covered by a polysilicon opposing electrode19. Further, the polysilicon opposing electrode19is covered with a third interlayer insulation film20that covers also the foregoing peripheral region10B continuously, and a contact hole20A and a contact hole20B are formed in the interlayer insulation film20such that the contact hole20A exposes the electrode15C and such that the contact hole20B exposes the electrode13E. Further, electrodes21A and21B are formed on the interlayer insulation film20respectively in correspondence to the contact holes20A and20B. Further, interconnection patterns21C and21D are formed on the interlayer insulation film20. Thereby, the accumulation electrodes17A and17B form, together with the dielectric film18thereon and the opposing electrode19, respective memory cell capacitors.

The DRAM10ofFIG. 1, however, has suffered from a drawback in that there tends to appear a large step height between the memory cell region10A and the peripheral region10B as a result of the repeated etching processes for forming the memory cell capacitors in the memory cell region10A. Further, such a stepped part at the boundary of the memory cell region10A and the peripheral region10B tends to invite accumulation of irregular polysilicon residue, which may cause various unpreferable effects such as short-circuit.

SUMMARY OF THE INVENTION

Accordingly, it is a general object of the present invention to provide a novel and useful semiconductor device and a fabrication process thereof wherein the foregoing problems are eliminated.

Another and more specific object of the present invention is to provide a semiconductor device including a memory cell region, in which a memory cell capacitor is formed, and a peripheral region where no such a memory cell capacitor is formed, wherein the step between the memory cell region and the peripheral region is minimized.

Another object of the present invention is to provide a semiconductor device including a memory cell region, in which a memory cell capacitor is formed, and a peripheral region where no such a memory cell capacitor is formed, wherein the problem of irregular polysilicon pattern remaining at a stepped part formed between the memory cell region and the peripheral region is effectively eliminated.

Another object of the present invention is to provide a fabrication process of a semiconductor device that includes a memory cell region, in which a memory cell capacitor is formed, and a peripheral region where no such a-memory cell capacitor is formed, wherein a capacitor is formed in the peripheral region without increasing the number of the mask steps.

Another object of the present invention is to provide a semiconductor device, comprising:

a substrate defined thereon a first region and a second region;

an interlayer insulation film formed on said substrate so as to cover said first and second regions; and

a capacitor formed on said interlayer insulation film in said first region; and

wherein said interlayer insulation film includes, in said first region, a stepped part defined by a groove having a bottom surface lower in level than a surface of said interlayer insulation film in said second region.

According to the present invention, the problem of etching of the second region, which tends to occur in the semiconductor device that has the first region, or memory cell region, including therein a capacitor and further the second region or a peripheral region, when patterning the capacitor in the first region, is successfully avoided by protecting the second region by a mask process during the foregoing patterning process of the capacitor. As a result, the height of the stepped part formed between the first region and the second region, which otherwise would be formed with a substantial step height, is successfully minimized. Further, by covering the stepped part between the first region and the second region by a conductive pattern, the problem associated with the formation of conductive residue at such a stepped part such as peeling and scattering of the conductive residue is effectively avoided. Further, by forming the capacitor insulation film concurrently with the side wall insulation film of the contact hole formed in the memory cell region, it becomes possible to form a large-capacitance capacitor without increasing the area of the semiconductor device or increasing the number of the mask steps. Further, by forming a dummy memory cell capacitor in the marginal part of the memory cell region such that the edge part of the storage capacitor covers, on the field oxide film, an insulation film identical with the insulation film forming a side wall insulation film of the contact holes for other memory cell capacitors, the problem of unnecessary increase in the area associated with the formation of the dummy memory cell is effectively avoided.

Another object of the present invention is to provide a semiconductor device, comprising:

a substrate;

a first conductive layer formed on said substrate;

an interlayer insulation film formed on said substrate so as to cover said first conductor layer;

a contact hole formed in said interlayer insulation film so as to expose said substrate;

a side wall insulation film covering a side wall of said contact hole;

a conductive side wall film covering a side wall of said side wall insulation film; and

a second conductive layer covering said conductive side wall film in said contact hole, said second conductive layer making an electrical contact with a surface of said substrate.

According to the present invention, it becomes possible, in a semiconductor device in which an analog circuit device having a capacitor and another semiconductor circuit are formed monolithically on a common substrate, to eliminate the problem of pinhole formation in a side wall insulation film that protects a side wall of a contact hole, even in such a case in which a native oxide film is removed from the surface of the substrate exposed by the contact hole by applying a wet etching process using HF, and the like, by providing a conductive layer on the side wall insulation film covering the side wall of the contact hole. The present invention is particularly useful when forming the capacitor in the analog circuit device concurrently with the side wall insulation film, as the conductive layer effectively protects the capacitor insulation film. Thereby, the problem of thinning of the capacitor insulation film or formation of pinhole in the capacitor insulation film is positively eliminated. As the capacitor insulation film and the side wall insulation film of the contact hole are formed simultaneously by the common process, and as the conductor layer on the side wall insulation film and the conductor layer protecting the capacitor insulation film are formed simultaneously by the common process, there occurs no increase in the number of the mask steps.

Another object of the present invention is to provide a semiconductor integrated circuit, comprising:

a substrate;

a first semiconductor device formed on a first region of said substrate;

a second semiconductor device formed on a second region of said substrate;

an interlayer insulation film formed on said substrate;

a first opening formed in a part of said interlayer insulation film covering said first region;

a first electrode covering said first opening;

a second opening formed in a part of said interlayer insulation film covering said second region so as to expose a surface of said substrate;

a second electrode covering said second opening;

an insulation film covering said interlayer insulation film; and

a third electrode formed on said insulation film in correspondence to said first electrode so as to sandwich said insulation film between said first electrode and said third electrode;

said first electrode and said second electrode having a substantially identical composition.

According to the present invention, it becomes possible to form, in a semiconductor integrated circuit in which two or more, different semiconductor circuits such as a DRAM and an analog circuit are formed, the capacitor of the analog circuit and the bit line contact or bit line pattern of the DRAM without increasing the number of the mask steps.

Other objects and further features of the present invention will become apparent from the following detailed description when read in conjunction with the attached drawings.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIGS. 2A–2Cshow the process of forming the memory cell capacitor in the semiconductor device ofFIG. 1according to a first embodiment of the present invention, wherein those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.

Referring toFIG. 2A, the contact hole16B is formed in the second interlayer insulation film16so as to expose the diffusion region11c, and an insulation film16′ is deposited on the interlayer insulation film16so as to cover the side wall of the contact hole16B. Next, in the step ofFIG. 2B, an anisotropic etching process acting substantially perpendicularly to the principal surface of the substrate11is applied on the insulation film16′, and the side wall insulation film16bis formed by removing the insulation film16′ remaining on the interlayer insulation film16.

Next, in the step ofFIG. 2B, a polysilicon film is deposited on the interlayer insulation film16so as to cover the contact hole16B, followed by a patterning process using a resist pattern to form the foregoing accumulation electrode17B.

Further, in the step ofFIG. 2C, the dielectric film18and a polysilicon film constituting the opposing electrode19are deposited consecutively, followed by a patterning process using a resist pattern to form the memory cell capacitor.

In the step ofFIGS. 2A–2C, it should be noted that there are two dry etching processes conducted in the step ofFIG. 2Band another dry etching process in the step ofFIG. 2C. Thereby, in view of the finite, or non-ideal selectivity of the dry etching process, there inevitably is caused a formation of a step at the edge part of the accumulation electrode17B and at the edge part of the opposing electrode19. Thus, in view of the total, or accumulated step height of these steps, there can be a case in which the level of the top surface of the interlayer insulation film16becomes substantially lower than the initial level thereof. Thereby, a large step is formed also on the surface of the interlayer insulation film20in correspondence to the boundary between the memory cell region10A and the peripheral region10B. Further, as a result of the etching of the surface of the interlayer insulation film16, there can be case in which the electrode formed on the interlayer insulation film14may be exposed in the peripheral region10B.

FIGS. 3A–3Fshow the fabrication process of a DRAM according to a second embodiment of the present invention wherein the problems of the first embodiment is eliminated.

Referring toFIG. 3A, a p-type Si substrate31is formed with an n-type well31A and an initial oxide film (not shown) is formed on the substrate with a thickness of about 3 nm. Further, an SiN pattern32is formed thereon with a thickness of about 115 nm, such that the SiN pattern32defines a device isolation region.

Next, in the step ofFIG. 3B, field oxide films33A–33F are formed on the substrate31by a wet oxidation process with a thickness of about 320 nm while using the SiN pattern32as a mask. Further, a p-type well31A is formed in the n-type well31A in correspondence to the memory cell region30A by conducting an ion implantation process of B+. Further, there is formed a p-type well31C in the substrate31in correspondence to a peripheral region30B formed outside the p-type well31B, such that the p-type well31C extends from the peripheral region31B into memory cell region31A and includes the p-type well31B formed in the memory cell region30A. In the actual process of forming the foregoing wells, the p-type well31C may be formed first, followed by the step of forming the n-type well31B. The n-type well31A may be formed by an ion implantation process conducted after the formation of the field oxide films.

Next, in the step ofFIG. 3B, a gate oxide film34is formed on the surface of the substrate31with a thickness of about 8 nm, and an amorphous silicon layer doped with P is formed further on the gate oxide film34by a thermal CVD process with a thickness of about 160 nm. By patterning the amorphous silicon layer by a photolithographic process, gate electrodes35A–35F are formed on the substrate31. Thereby, each of the gate electrodes35A–35F constitutes a part of the word line WL, as is well known in the art. Further, the field oxide films33A and33B in the memory cell region30A carries thereon the word lines WL of different memory cell regions.

Further, an ion implantation process of P+is conducted into the memory cell region30A of the Si substrate31while using the gate electrodes35A–35F as a mask, to form diffusion regions31a–31dof the n−-type such that the diffusion regions31a–35dare located adjacent to the gate electrodes35A–35C. Simultaneously to the formation of the foregoing diffusion regions31a–31d, diffusion regions31h–31kof the n−-type are formed in the peripheral region30B adjacent to the gate electrodes35E and35F, wherein the diffusion regions31h–31kof the n−-type constitute an LDD region of the transistor to be formed in the peripheral region30B. Further, diffusion regions31fand31gof the n−-type are formed also in the n-type well31A of the peripheral region30B adjacent to the gate electrode35D.

Next, the memory cell region30A and the p-type well31C are protected by a resist pattern and an ion implantation of B+is conducted into the exposed n-type well region31A of the peripheral region30B while using the gate electrode35D as a mask, and the conductivity type of the foregoing diffusion regions31fand31gis changed from the n−-type to the p−-type.

Further, the gate electrodes35A–35F are covered by an oxide film, followed by an etch-back process, to form a side wall oxide film on each of the gate electrodes35A–35F.

Next, in the step ofFIG. 3B, the memory cell region30A and the n-type well31A of the peripheral region30B are covered by a resist pattern, ahd diffusion regions31l–31oof the n+-type are formed in the substrate31adjacent to the electrodes35E and35F at the location outside the side wall oxide film thereon, by conducting an ion implantation process of As+while using the gate electrodes35E and35F and the side wall oxide films thereon as a self-aligned mask.

In the step ofFIG. 3B, the substrate31is further covered by a resist pattern such that the n-type well31A of the peripheral region30B is exposed, and an ion implantation process of BF2+is conducted into the substrate31while using the gate electrode35D and the side wall oxide films thereon as a self-aligned mask, to form diffusion regions31pand31qof the p+-type adjacent to the gate electrode at the location outside the side wall oxide films.

Next, in the step ofFIG. 3C, a BPSG film36is deposited on the structure ofFIG. 3Bwith a thickness of about 250 nm, and contact holes36A–36D are formed in the BPSG film36so as to expose the foregoing diffusion regions31b,31e,31pand31n. Further, an oxide film is deposited on the BPSG film36by a thermal CVD process, followed by an etch-back process applied uniformly, to form side wall oxide films36a–36don the side wall of the contact holes36A–36D, respectively. Further, electrodes37A–37D, each formed of a stacking of an amorphous silicon pattern doped with P and a WSi pattern, are formed so as to cover the bottom surface of the contact holes36A–36D, respectively. It should be noted that the electrodes37A and37B in the memory cell region30B constitutes a bit line pattern. By forming the side wall oxide films36a–36don the contact holes36A–36D, the problem of short circuit, which tends to occur when the contact holes are formed at an offset location, between the electrode in the contact hole and the adjacent gate electrode is effectively eliminated.

In the step ofFIG. 3C, another BPSG film38is formed on the foregoing BPSG film36with a thickness of about 350 nm, such that the BPSG film38covers the electrodes37A–37D.

Next, in the step ofFIG. 3D, contact holes38A–38C are formed in the BPSG film38ofFIG. 3Cso as to expose the diffusion regions31a,31cand31dof the memory cell region30A respectively, followed by the step ofFIG. 3Eto form memory cell capacitors such that the memory cell capacitor covers each of the contact holes38A–38C.

FIGS. 4A–4Dshow the process steps between the step ofFIG. 3Dand the step ofFIG. 3Ein detail, wherein those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.

Referring toFIG. 4A, the BPSG film38is covered by an insulation film39of the material having an etching rate smaller than the etching rate of the BPSG film36or38, such as SiO2, SiN or SiON, such that the insulation film39covers the contact hole38B. By applying an etch-back process to the insulation film39thus formed, a side wall insulation film38bis formed such that the side wall insulation film38bcovers the side wall of the contact hole38B as represented inFIG. 4B. It should be noted that the advantageous feature to be noted below can also be obtained even when the etching rate of the insulation film39is generally the same as the etching rate of the BPSG film38.

Next, in the step ofFIG. 4B, a resist pattern40covering the peripheral region30B is formed on the insulation film39and the insulation film39is subjected to an etching process while using the resist pattern40as a mask. As a result of such an etching process, there is formed a surface381in the BPSG film38in correspondence to the memory cell region30A at a level lower than the surface of the BPSG film38in the peripheral region30B, wherein the surface381forms a step S1at the boundary between the memory cell region30A and the peripheral region30B.

Next, in the step ofFIG. 4C, the resist pattern40ofFIG. 4Bis removed and an amorphous silicon layer doped with P is deposited thereon. After patterning the amorphous silicon layer thus deposited, there is formed a storage electrode41forming a part of the memory cell capacitor such that the storage electrode41covers the contact hole38B. It should be noted that the patterning of the storage electrode41is conducted by using a resist pattern (not shown) as a mask. Thus, the level of the surface of the BPSG film38is lowered in the memory cell region30A further from the foregoing level381to a level382. Associated with this, the step height between the memory cell region30A and the peripheral region30B increases from the foregoing step height of S1to S2. It should be noted that there occurs little etching in the insulation film39during the foregoing patterning process of the storage electrode41, as the etching rate of the insulation film39is substantially smaller than the etching rate of the BPSG film38.

Next, in the step ofFIG. 4D, a capacitor insulation film42of the so-called ONO structure is deposited on the structure ofFIG. 4C, followed by a deposition of an amorphous silicon pattern doped with P on the capacitor insulation film42thus deposited. By conducting a patterning process on the amorphous silicon pattern thus deposited, there is formed an opposing electrode43. Thereby, it should be noted that the BPSG film38experiences an etching in the memory cell region30A associated with the patterning of the opposing electrode38and there is formed a groove38G having a bottom surface383at the boundary between the memory cell region30A and the peripheral region30B. As the insulation film39has a reduced etching rate as compared with the BPSG film38, the groove38G forms a step S3which is even larger than the foregoing step S2.

In the foregoing construction of the semiconductor device, it should be noted that the insulation film is formed in the peripheral region30B with an increased thickness increased by the thickness of the insulation film39as compared with the memory cell region30A. Further, in view of the fact that the BPSG film38is protected by the insulation film39, which has a lower etching rate, the problem of the surface level of the BPSG film36becomes lower in the peripheral region than in the memory cell region and the associated problem of the global step height between the memory cell region and the peripheral region becoming larger, are minimized.

In the step ofFIG. 4D, it should be noted that there can be a case in which the insulation film39is removed entirely as a result of the formation of the memory cell capacitor as indicated inFIG. 5. It should be noted thatFIG. 5thus shows a modification of the structure ofFIG. 4D.

It should be noted that the structure ofFIG. 4Dcorresponds to the structure ofFIG. 3E.

Thus, referring back toFIG. 3E, it can be seen that there is formed a memory cell capacitor MC including the storage electrode41, the capacitor dielectric film42and the opposing electrode, in each of the contact holes38A,38B and38C that are formed in the BPSG film38so as to expose the diffusion regions31a,31cand31d.

Next, in the step ofFIG. 3F, a BPSG film44is formed on the structure ofFIG. 3Ewith a thickness of about 350 nm, and interconnection electrodes45A and45B are formed on the BPSG film44so as to make an electrical contract with the electrode37C and the diffusion region31ovia respective contact holes44A and44B. Further, interconnection patterns45C and45D are formed on the BPSG film44.

In the present embodiment, it should be noted that the surface level of the BPSG film38is maintained in the peripheral region. Thus, the problem of the global step formation in the BPSG film44in correspondence to the boundary between the memory cell region30A and the peripheral region30B is reduced, and the focusing at the time of the photolithographic patterning of the electrodes45A and45B or the interconnection patterns45C and45D is reduced substantially.

In the DRAM of the previous embodiment, there can be a case in which the conductor layer constituting the storage electrode41or the opposing electrode43remains unetched along the stepped part S3between the memory cell region30A and the peripheral region30B as an irregular pattern42X at the time of the patterning of the storage electrode41or the opposing electrode43as represented inFIG. 6.

FIGS. 7A and 7Bshow the formation of the memory cell capacitor in the memory cell region30A in a plan view, whereinFIG. 7Acorresponds to the step ofFIG. 4B.

Referring toFIG. 4A, there is formed a stepped part S1at the outer side of the memory cell region30A represented by the broken line as a result of the patterning process conducted by the resist pattern40, and contact holes30A are formed in the memory cell region30A in a row and column formation.

On the other hand,FIG. 4Bcorresponds to the foregoing step ofFIG. 4Dand shows the state in which the capacitors MC, each including the storage electrode41therein, are formed in the memory cell region30A in correspondence to the contact holes38B.

Referring toFIG. 7B, the peripheral region30B is covered by the insulation film39and the foregoing irregular conductor pattern42X is formed along the step S3extending along the boundary between the peripheral region30B and the memory cell region30A. Further, it should be noted that there are formed dummy memory cell capacitors MC′ in the memory cell region30A in correspondence to the part outer side of the region indicated by a broken line, wherein the dummy memory cell capacitor MC′ has a construction identical with the construction of the dummy memory cell MC. As the residual, irregular conductor pattern42X extends along the stepped part S3, there is a substantial risk that the memory cell capacitor MC makes a short-circuit with the conductor pattern42X in the structure in which the memory cell capacitors MC are formed also in the region outside the region indicated by the broken line. Such a short-circuit may occur when there is an error in the mask process for defining the memory cell region30A and the peripheral region30B. Thus, thee dummy memory cell capacitors MC′ are formed along the outer boundary of the memory cell region30A so as to surround the memory cell region30A for avoiding the foregoing problem. Further, the formation of the dummy memory cell capacitors MC′ is preferable in view of the fact that the photoresist pattern tends to become different between the outermost boundary part and the interior of the memory cell region.

It should be noted that the formation of the foregoing conductor pattern42X along the stepped part S3is not particularly controlled. The pattern42X is formed more or less spontaneously. Thus, there is a substantial risk that the conductor pattern42X may scatter during the normal cleaning process. Thus, the conductor pattern42X provides a potential threat with regard to the yield of the semiconductor device, and it is necessary to eliminate the scattering of the residual conductor pattern42X.

FIG. 8shows the construction of a DRAM50according to a third embodiment of the present invention that addresses the foregoing problem.

Referring toFIG. 8, there is formed a conductor pattern42Y covering the foregoing stepped part S3c so as to extend along the stepped part S3, wherein the conductor pattern42Y has a predetermined width and is formed simultaneously to the storage electrode41or the opposing electrode43of the memory cell capacitor C. As the conductor pattern42Y thus formed has a predetermined width defined by a pair of straight edges, the problem of peeling or scattering of the irregular conductor pattern41X pertinent to the conventional device is successfully eliminated.

FIG. 9shows the construction of a DRAM60having a construction similar to that of the DRAM10ofFIG. 1except that the DRAM60includes another capacitor D on a field insulation film12A formed in the peripheral region10B in addition to the capacitor C. InFIG. 9, those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.

In the DRAM10ofFIG. 1explained previously, the capacitor C of the peripheral region10B is formed on the diffusion region defined by the field insulation films12B and12C. Thus, it has been necessary to introduce the impurity element into the substrate11in correspondence to the diffusion region11hwith high concentration level prior to the formation of the gate electrode. After the ion implantation process, it has been necessary to conduct an oxidizing process to form the oxide film13e. Because of such a process that uses an ion implantation process for forming the diffusion region11has a lower electrode of the capacitor C, the conventional DRAM10ofFIG. 1required an additional mask process. Further, because of the use of the high-concentration ion implantation in the construction ofFIG. 1, there has been a tendency that the breakdown characteristic of the capacitor dielectric film of the capacitor C formed by the oxide film13eis deteriorated. Further, the construction ofFIG. 1is disadvantageous in view of device miniaturization as the capacitor C is formed so as to cover the diffusion region11hthat is defined by the field insulation films12B and12C. Such a construction reduces the area of the substrate11available for the transistor.

In the case of the DRAM60ofFIG. 9, the capacitor D is formed in the peripheral region10B wherein the capacitor D includes a lower capacitor electrode13F formed on the field oxide film12A and the upper capacitor electrode15D formed on the interlayer insulation film14of BPSG, wherein the interlayer insulation film14is interposed between the lower and upper capacitor electrodes13F and15D. As the capacitor D of such a construction does not require a mask process for high-concentration ion implantation process and the problem of deterioration of the capacitor oxide film13eis successfully avoided.

On the other hand, the DRAM60ofFIG. 9has a problem, due to the fact that the interlayer insulation film14has a substantial thickness, in that the capacitance for a unit area is very small for the capacitor D and it is necessary to increase the capacitor area substantially in order to secure a sufficient capacitance for the capacitor D.

One may think of forming the capacitor D to have a construction identical with the construction of the memory cell capacitor formed in the memory cell region30A. This approach, however, raises the problem of poor breakdown voltage for the capacitor D, as the voltage applied to the capacitor insulation film of a memory cell capacitor is usually controlled to be within ±½ supply voltage, depending on the High level or Low level stored in the memory cell capacitor. Thereby, it should be noted that the voltage applied to the opposing electrode is set to ½ supply voltage. In the case of the capacitor for use in the peripheral circuit, particularly an analog circuit, it is inevitable that the supply voltage is applied directly to the capacitor electrodes. Thus, the use of the memory cell capacitor for such a purpose causes the problem of poor breakdown characteristic. When the thickness of the capacitor insulation film is increased for improving the breakdown characteristic in the capacitor D having the structure of a memory cell capacitor, on the other hand, the capacitance of the DRAM is decreased simultaneously.

FIGS. 10A–10Cshow the fabrication process of a DRAM70according to a fourth embodiment of the present invention wherein the foregoing problems are eliminated, wherein those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.

Referring toFIG. 10A, there is formed an opening14D exposing the electrode13F on the field oxide film12A in the interlayer insulation film14, in addition to the contact hole14B, and an insulation film140is deposited on the interlayer insulation film12so as to cover the contact hole14B and the opening14D according to respective cross-sectional shape. In the illustrated example, the interlayer insulation film14has a thickness of about 200 nm and the contact hole14B has a size of about 0.3 μm. On the other hand, the opening14D has a size that is determined according to the capacitance that is needed for the capacitor. Generally, the size of the opening14D is much larger than the size of the contact hole14B. With the increase in the integration density, the size of the contact hole14B is reduced further.

Next, in the step ofFIG. 10B, the part of the insulation film140covering the peripheral region10B is covered by a resist pattern and the insulation film140is subjected to an etch-back process in the memory cell region10A. Thereby, a side wall insulation film14bis formed on the side wall of the contact hole14B.

In the step ofFIG. 10B, it should be noted that the insulation film140remains in the peripheral region10B unetched and thus, the bottom part of the opening14D is covered with the insulation film140. It should be noted that the insulation film140is formed by a thermal CVD process with a thickness of about 70 nm. In this case, there is formed a side wall insulation film having a thickness of about 80% or 56 nm (=70×0.8) on the side wall of the contact hole14B, and the contact hole14B thus obtained as an effective size of about 0.2 μm (=0.3 μm−56 nm×2).

Thus, by forming the insulation film140to have a thickness of 70 nm, it is possible to form the contact hole14B to have an effective size of about 0.1 μm for the case in which the initial size of the contact hole14B is 0.2 μm. It should be noted that this size of the contact hole does not cause any specific problem in the DRAM. When the initial size of the contact hole14B is smaller than 0.2 μm, on the other hand, it is necessary to reduce the thickness of the insulation film140. This decrease of the thickness of the insulation film140is preferable in view of the fact that the thickness of the capacitor insulation film in the peripheral region10B experiences a similar decrease. Thus, in the case the capacitance of the analog peripheral circuit is important, the insulation film140is formed to have a reduced thickness.

Next, in the step ofFIG. 10C, the resist pattern is removed and a conductor layer is deposited uniformly. After patterning the conductor layer thus deposited, there are formed an electrode15B covering the contact hole14B and the electrode150covering the opening14D. It should be noted that the electrode150is separated from the electrode13F in the opening14D from the foregoing insulation film140, and because of this, the electrode150forms a capacitor E corresponding to the capacitor D together with the electrode13F and the insulation film140.

In the DRAM70of the present invention, it should be noted that the capacitor E formed on the field oxide film12A uses the insulation film140as the capacitor insulation film, wherein the insulation film140is the film identical with the insulation film forming the side wall insulation film. Thus, the capacitor E has a thin capacitor insulation film, having a thickness less than ⅓ the thickness of the capacitor insulation film of the capacitor D, and associated with this, the capacitor E realized a large capacitance.

During the process of forming the capacitor E, there is an additional mask process for patterning the insulation film140. On the other hand, the overall number of the mask processes does not change in the present embodiment, as the mask process for forming the diffusion region11hcan be eliminated.

FIG. 11shows the overall construction of a DRAM80according to a fifth embodiment of the present invention, wherein those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.

Referring toFIG. 11, the DRAM80includes, in addition to the capacitor E, a capacitor F formed in the peripheral region in correspondence to an opening16C formed in the interlayer insulation film16and further a capacitor G formed in correspondence to an opening16D formed also in the interlayer insulation film16D, wherein the capacitor F includes a lower electrode13G formed on the field oxide film12B concurrently with the gate electrodes13A–13C and is exposed by the foregoing opening16C, a capacitor insulation film160formed simultaneously with the side wall insulation film16aor16bof the contact hole16A or16B so as to cover the opening16C, and an upper electrode21B formed on the capacitor insulation film160so as to cover the opening16C. It should be noted that the capacitor insulation film160corresponds to the insulation film39ofFIG. 4D.

On the other hand, the capacitor G is formed of the diffusion region11hexposed by the opening16D, the capacitor insulation film160formed on the interlayer insulation film16so as to cover the opening16D, and the upper electrode21C formed on the capacitor insulation film160so as to cover the opening16D. It should be noted that the capacitor insulation film160corresponds to the insulation film39ofFIG. 4D.

In the DRAM80of the present embodiment, it should be noted that the capacitor E or F is formed on the field oxide film12A or12B, and thus, there occurs no problem of decrease in the integration density of the integrated circuit. Further, it should be noted that the capacitor insulation film140of the capacitor E is formed of the same insulation film forming the side wall insulation film14aor14b, as noted above. Thereby, it is necessary to conduct an additional mask process for patterning the capacitor insulation film140. However, this increase in the number of the mask process is effectively compensated for by the elimination of the mask process for forming the diffusion region11hthat is used in the step ofFIG. 9for forming the capacitor C. Thereby, there is no overall increase in the number of the mask processes.

In the capacitor F, it should be noted that capacitor insulation film160is formed of an insulation film that also forms the side wall insulation films16aand16b. Thus, there is no need of additional mask processes. As the process of forming the diffusion region11h, used in the process ofFIG. 9, is also eliminated, overall number of the mask steps can be reduced. In the capacitor G, too, the increase in the number of the mask steps is avoided as compared with the case of the capacitor C ofFIG. 9.

It should be noted that the construction ofFIG. 11, showing the capacitors E, F and G, is merely for the purpose of explanation of the principle ofFIGS. 10A–10Cand does not mean that all of these three capacitors have to be provided in the DRAM80.

FIG. 12shows the part of the DRAM10ofFIG. 1including the memory cell region10in detail, wherein those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.

In the construction ofFIG. 12, dummy memory cells similar to the dummy memory cell explained with reference toFIG. 7Bare formed on the peripheral part of the memory cell region10A, while such dummy memory cells, not contributing to the storage of information, causes a decrease in the integration density of the DRAM10.

FIGS. 13A–13Cshow the fabrication process of a DRAM90according to a sixth embodiment of the present invention that addresses the foregoing problem of the prior art, wherein those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.

Referring toFIG. 13A, the contact hole38C is formed so as to expose the field oxide film33B, followed by a deposition of the insulation film39. Next, in the step ofFIG. 13B, the peripheral region30B is protected by a resist pattern and the insulation film39is etched back in the memory cell region30A. As a result, side wall oxide films38aand38bare formed on the contact holes38A and38B, respectively. In the present embodiment, it should be noted that the dummy cells are formed in the peripheral region30B along the boundary between the peripheral region30B and the memory cell region30A.

Next, in the step ofFIG. 13C, storage electrodes41A and41B are formed so as to cover the contact holes38A and38B, and further a storage electrode41C is formed so as to fill the contact hole38C. Thereby, it should be noted that the storage electrodes41A and41B make a contact with the diffusion regions31aand31cin the substrate31respectively, while the storage electrode41C constituting the dummy memory cell is interrupted at the bottom part thereof [by the insulating film39]and does not make a contact with the diffusion region.

After the formation of the storage electrodes41A–41C, there is formed a capacitor dielectric film42so as to cover the storage electrode41A–41C, and an opposing electrode43is formed further on the dielectric film42.

In the present embodiment, the dummy memory cell capacitors are formed on the field oxide film33. Thereby, the dummy memory cell capacitor does not occupy the active area of the substrate unnecessarily, and the integration density of the DRAM is increased.

In the present embodiment, it should be noted that the top part of the dummy storage electrode41C is covered with the foregoing insulation film39. Thus, there occurs no problem even when the contact hole38C is formed so as to penetrate through the field oxide film33B. As long as the top part of the dummy storage electrode41C is covered by the insulation film39, the contact hole38can be formed at an arbitrary location. For example, the contact hole38may be formed on the top of the electrode35C.

FIGS. 14A–14Cshow the fabrication process of a DRAM70A according to a seventh embodiment of the present invention, wherein those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted. It should be noted that the DRAM70A is a modification of the DRAM70described with reference toFIGS. 10A–10C.

Referring toFIG. 14A, a structure similar to the structure ofFIG. 10Ais formed, wherein the structure ofFIG. 14Afurther includes a polysilicon or amorphous silicon film141doped with P such that the conductive film141covers the SiO2film140. It should be noted that the right-side and left-side are reversed inFIGS. 14A–14Cas compared with the representation ofFIGS. 10A–10C.

Next, in the step ofFIG. 14B, the polysilicon film141is patterned by using a resist pattern similar to that ofFIG. 13B, and the SiO2film140underneath is patterned further while using the same resist pattern as a mask. As a result of the patterning, the Si substrate11is exposed at the bottom of the contact hole14B. As will be seen fromFIG. 14B, the SiO2film140covering the side wall of the contact hole14B is further covered by the polysilicon film. Similarly, the SiO2film constituting the capacitor insulation film of the capacitor E is also covered by the polysilicon film141.

Next, the structure ofFIG. 14Bis immersed in an aqueous solution of HF, and the native oxide film is removed from the exposed surface of the Si substrate11. Thereby, the SiO2film140is protected by the polysilicon film141in any of the contact hole14B and the capacitor E and the problem of pinhole formation in the side wall insulation film140of the contact hole14B or in the capacitor insulation film140of the capacitor E is eliminated.

Further, in the step ofFIG. 14C, the bit line electrode15B and the capacitor electrode150are formed respectively on the contact hole14B and the capacitor E so as to cover the polysilicon film141.

As explained before, such a structure allows the treatment in the HF solution for removing the native oxide film from the substrate surface at the bottom part of the contact hole14B. Thereby, it becomes possible to reduce the contact resistance of the bit line and achieve a reliable electrical contact.

In the present embodiment, the bit line electrode15B and the capacitor electrode150may be formed of a conductive material such as W, Al, polysilicon WSi, or a stacked body thereof. Further, it is possible to replace the side wall polysilicon film141by other conductive film such as W.

Thus, it is possible to form the side wall conductive film141by a polysilicon layer doped with P to a first concentration level and the bit line electrode15B as a stacked body of a polysilicon layer doped with P to a second, higher concentration level and a W layer formed thereon. Further, both of the side wall conductive film141and the bit line electrode15B may be formed of W.

FIGS. 15A–15Dshow the fabrication process of a semiconductor integrated circuit200according to an eighth embodiment of the present invention, wherein the semiconductor integrated circuit has a construction in which an analog integrated circuit and a DRAM are formed monolithically on a common substrate101.

Referring toFIG. 15A, a p-type substrate101is formed with an n-type well101A in correspondence to the analog integrated circuit, and an electrode pattern103A is formed in the n-type well101A with a gate oxide film102interposed between the gate electrode pattern103A and the Si substrate101. The gate oxide film102thereby covers the surface of the Si substrate101. It should be noted that the electrode pattern103A has a stacked construction in which a polysilicon film103ais covered by a WSi film103b. Similarly, there are formed a plurality of gate electrodes103B on the DRAM region of the substrate101, wherein the surface of the Si substrate101is covered by the foregoing gate oxide film102. It should be noted that each of the gate electrodes103B has a construction in which the polysilicon film103aand the WSi film103bare stacked similarly to the electrode103A. Each of the electrode pattern103A and the gate electrode patterns103B has a top surface and both side walls covered by an SiN film104.

Next, in the step ofFIG. 15B, an interlayer insulation film105, which may be formed of BPSG, PSG or HSG, is deposited on the structure ofFIG. 15A, followed by a planarization process conducted by a chemical mechanical polishing (CMP) process, and the interlayer insulation film105is formed with an opening105A in correspondence to the electrode pattern103A and further a the bit line contact hole105B and memory cell contact holes105C in correspondence to the diffusion regions (not shown) that are formed in the Si substrate101between the plurality of gate electrodes103B. Thereby, it should be noted that the opening105A exposes the SiN film104on the electrode pattern103A, while the bit line contact hole105B or the memory cell contact hole105C exposes the surface of the Si substrate101. It is preferable to form the interlayer insulation film105such that the interlayer insulation film105has a thickness of at least 50 nm in correspondence to the part above the electrode pattern103A after the planarization process.

Preferably, the opening105and the contact holes105B and105C are formed by an RIE process typically using a mixture of C4F8, Ar, CO and O2such that the RIE process acts preferentially on the silicon oxide film or silicate glass film, such as SiO2film or BPSG as film, as compared with an SiN film. In this case, the formation of the contact hole105B and105C are conducted while using the SiN film104as a self-aligned mask. Thus, according to the present invention, it is not necessary to use a specially made mask or an exposure apparatus for forming the minute contact hole105B or105C, and the contact holes105B and105C are formed simultaneously to the step of forming the opening105A. The etching process for forming the opening105A stops spontaneously in response to the exposure of the SiN film104covering the electrode pattern103A.

Further, in the step ofFIG. 15C, the structure is covered with a conductive amorphous silicon layer (not shown) doped with P with a thickness of 200–400 nm, such that the conductive amorphous silicon layer fills the opening105A and the contact holes105B and105C. Further, the part of the amorphous silicon film covering the interlayer insulation film105is removed by a CMP process, and there are formed conductive amorphous silicon plugs106A–106C such that the amorphous silicon plug106A fills the opening105A, and the amorphous silicon plugs106B and106C fill the contact holes105B and105C. The amorphous silicon plug106A thus formed constitutes the lower electrode of the analog integrated circuit.

Next, in the step ofFIG. 15C, an SiO2film107is deposited on the interlayer insulation film105with a thickness of 30–70 nm, and an opening107A is formed in the SiO2film107so as to expose the conductive plug106B that fills the bit line contact hole105B, by conducting an RIE process while using a mixture of CF4, CHF3and Ar as an etching gas. Further, a polysilicon film108aand a WSi film108bare formed on the SiO2film107with respective thicknesses of 50 nm and 100 nm, wherein the films108aand108bthus deposited are subjected to a patterning process to form a capacitor upper electrode108A in correspondence to the capacitor lower electrode106B. Simultaneously, a bit line electrode108B is formed in correspondence to the conductive plug106B. Thus, both of the capacitor upper electrode108A and the bit line electrode108B have the layered structure in which the polysilicon film108aand the WSi film108bare stacked. The electrode108A form, together with the electrode106A and the intervening SiO2film107, the capacitor C of the analog circuit.

Next, in the step ofFIG. 15D, another interlayer insulation film109of PSG, BPSG or HSG is deposited on the structure ofFIG. 15Csuch that the interlayer insulation film109covers the upper electrode108A and the bit line electrode108B. Further, an opening109A is formed in the interlayer insulation film109thus formed in correspondence to the amorphous silicon plug106C by an RIE process. Further, an SiO2film is deposited on the interlayer insulation film109so as to cover the opening109A, and an anisotropic etching process acting substantially perpendicularly to the principal surface of the substrate101is applied to the SiO2film thus deposited. Thereby, there is formed an SiO2side wall film109B on the side wall of the opening109A. Simultaneously, to the formation of the side wall oxide film109B, there is formed a corresponding opening in the SiO2film107as a result of the RIE process, wherein opening thus formed exposes the conductive plug106C.

Next, a storage electrode110of DRAM is formed on the interlayer insulation film109so as to cover the opening109A by depositing an amorphous silicon layer or a polysilicon layer doped with P, and a capacitor dielectric film111of SiO2or SiN is formed on the surface of the storage electrode110. Further, a cell plate electrode112is formed on the capacitor dielectric film111.

According to the process ofFIGS. 15A–15D, the lower electrode106A is formed simultaneously to the process of forming the amorphous silicon plug106B or106C, and there is no need of extra mask process for patterning the lower electrode106A. Further, the upper electrode108A of the capacitor is formed simultaneously with the bit line electrode108B and there is no extra mask process needed for patterning the upper electrode108A. Thus, according to the present embodiment, it is possible to form an analog integrated circuit including a capacitor and a DRAM on a common substrate, simultaneously and without increasing the number of fabrication steps.

FIGS. 16A and 16Bshow the fabrication process of a semiconductor device220according to a ninth embodiment of the present invention, wherein those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted. It should be noted that the semiconductor device220is a modification of the semiconductor device200described previously.

Referring toFIG. 16A, the opening105A and the contact holes105B and105C are, after the step ofFIG. 15B, filled by P-doped amorphous silicon plugs106A–106C respectively. After applying a CMP process, the SiO2film107is deposited on the interlayer insulation film105, and a P-doped amorphous silicon film107B is deposited further on the SiO2film107. In the step ofFIG. 16A, the opening107A penetrates through the SiO2film107and the amorphous silicon film107B and exposes the amorphous silicon plug106B. Thereby, the opening107A functions as a bit line contact hole.

In the present embodiment, the structure ofFIG. 16Ais subjected to a wet etching process in an aqueous solution of HF, and the native oxide film is removed from the exposed surface of the amorphous silicon plug106B. In this process, it should be noted the SiO2film107is effectively protected from the HF etchant by the P-doped amorphous silicon film107B.

Next, in the step ofFIG. 16B, the upper electrode108A of the capacitor C and the bit line electrode108B are formed on the structure ofFIG. 16Asimilarly to the process ofFIG. 15C.

According to the semiconductor device220of the present embodiment, it becomes possible to remove the native oxide film from the exposed surface of the amorphous silicon plug106B in the step ofFIG. 16Aby applying an HF treatment, and the contact resistance of the bit line electrode108B is reduced substantially. As the SiO2film107is protected by the amorphous silicon film107B, such treatment by HF does not cause the problem of thinning of the capacitor insulation film in the analog integrated circuit.

After the step ofFIG. 16B, the process similar to the process ofFIG. 15Dis conducted, and there is formed a semiconductor device in which an analog integrated circuit including a capacitor C and a DRAM are integrated monolithically on a common substrate.

FIGS. 17A–17Cshow the fabrication process of a semiconductor device230according to a tenth embodiment of the present invention, wherein those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted. It should be noted that the semiconductor device230is a modification of the semiconductor device220described previously.

Referring toFIG. 17A, the opening105A and the contact hole105C are, after the step ofFIG. 15B, filled by P-doped amorphous silicon plugs106A and106C respectively, and a CMP process is applied further thereto, similarly as before. In the present embodiment, on the other hand, the contact hole105B corresponding to the bit line contact is not formed in the step ofFIG. 17A.

Next, in the step ofFIG. 17B, the SiO2film107is deposited on the structure ofFIG. 17A, and the P-doped amorphous silicon film107B is deposited further on the SiO2film107. Further, the opening107A is formed so as to penetrate through the foregoing films107and107B, and the contact hole105B is formed in the interlayer insulation film105.

Further, in the step ofFIG. 17C, the polysilicon film108adoped with P is deposited so as to cover the contact hole105B, and the WSi film108bis deposited further thereon. By conducting a patterning process on the films108aand108b, the upper electrode108A of the capacitor C is formed in correspondence to the lower electrode106A of the capacitor C. Further, the bit line electrode108B is formed so as to cover the contact hole105B simultaneously to the upper electrode108A.

In the present embodiment, too, the lower electrode106A is formed concurrently with the conductive plug106C. Further, the upper electrode108A is formed simultaneously with the conductive plug108B forming the bit line. Thereby, it is not necessary to provide any excessive deposition process or mask process.

FIGS. 18A–18Gshow the fabrication process of a semiconductor device240according to an eleventh embodiment of the present invention.

Referring toFIG. 18A, the semiconductor device240is formed on a p-type substrate201wherein there is formed a device isolation trench201A on the surface of the substrate201between an analog circuit region A and a DRAM circuit region B, and the device isolation trench201A is filled with an SiO2film201B. In the process ofFIG. 18A, there is formed an n-type well (not shown) in the analog circuit region A by conducting thereto an ion implantation process of an n-type impurity such as As.

Next, in the step ofFIG. 18B, there is formed a thermal oxide film202A on the structure ofFIG. 18Auniformly as a result of a thermal oxidation process of the Si substrate201, wherein the thermal oxide film202A thus formed serves for a gate oxide film of the MOSFETs that are formed on the analog circuit region A. Further, the gate oxide film202A is covered with a polysilicon film with a thickness of 100–200 nm. By patterning the polysilicon film thus deposited by a dry etching process that uses a mixture of Cl2and O2as an etching gas while using a resist pattern R as a mask, there is formed a polysilicon pattern203on the gate oxide film202A in the analog circuit region A. Further, by conducting an ion implantation process of an impurity element such as B into the substrate while using the resist pattern R and the polysilicon pattern203as a mask, there is formed a p-type well (not shown) in the substrate201in correspondence to the DRAM region B.

Next, in the step ofFIG. 18C, the thermal oxide film202A exposed at the surface of the Si substrate201is removed by a wet etching process using HF as an etchant, and an SiO2film202B is newly formed on the surface201of the Si substrate201by a thermal oxidation process. As a result of the thermal oxidation process, there is formed also a thermal oxide film on the surface of the polysilicon pattern203in continuation with the SiO2film202B.

Next, in the step ofFIG. 18C, the SiO2film202B is covered consecutively by a P-doped amorphous silicon film204, a W film205and an SiO2film206respectively with the thicknesses of 70 nm, 100 nm and 100 nm. By applying a patterning process consecutively, there are formed a plurality of gate electrodes207in the DRAM region B. Thereby, it should be noted that the patterning of the SiO2film206is conducted by an RIE process using a mixture of CF4, CHF3and Ar as an etching gas, while the patterning of the W film205and the amorphous silicon film204is conducted by an RIE process using a mixture of Cl2and O2as an etching gas.

Further, in the step ofFIG. 18D, an ion implantation process of P or As is conducted into the substrate201in the DRAM region B to form n-type diffusion regions adjacent to each of the gate electrodes207.

Next, in the step ofFIG. 18E, an SiO2film is deposited uniformly on the structure ofFIG. 18D, and the SiO2film thus formed is subjected to an etch-back process acting generally perpendicularly to the principal surface of the substrate201, to form an oxide pattern208covering the top surface and the side walls of the gate electrode207. Further, the oxide pattern208is formed also on the side wall of the polysilicon pattern203. Thereby, the oxide patterns208on the gate electrodes207define therebetween a self-aligned contact hole exposing the surface of the substrate201.

Next, in the step ofFIG. 18F, there is formed a polysilicon film209uniformly on the structure ofFIG. 18Eso as to cover the self-aligned contact holes, and the polysilicon film209thus formed is subjected to a patterning process in the step ofFIG. 18Gsuch that the patterning process is conducted by an RIE process that uses a mixture of Cl2and O2as an etching gas. Thereby, there is formed a conductive plug210B in the self-aligned contact holes in the DRAM region B of the substrate201in electrical contact with the diffusion regions formed thereon. In the analog circuit region A, on the other hand, there is formed a gate electrode210as a result of the patterning of the polysilicon film209.

In the semiconductor device240ofFIG. 18G, the conductive plugs210B are formed in the DRAM region B so as to fill the miniaturized self-aligned contact holes without the need of additional mask processes. Further, the formation of the conductive plugs210B is made simultaneously with the formation of the gate electrode in the analog circuit region A. By forming the conductive plug210B, the need of forming a deep contact hole in the interlayer insulation film covering the structure ofFIG. 18Gis eliminated, and the fabrication of the semiconductor device is facilitated substantially.

FIGS. 19A–19Cshow the fabrication process of a semiconductor device250according to a twelfth embodiment of the present invention, wherein those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.

In the present embodiment, the structure ofFIG. 18Eis covered by an SiO2film by conducting a CVD process. By applying an etch-back process to the SiO2film thus formed, there is formed an SiO2film211A covering the polysilicon pattern203. It should be noted that the SiO2film211A covers the SiO2side wall film208covering the side wall of the polysilicon pattern203. As a result of the patterning of the CVD-SiO2film noted above, there is formed a side wall film211B on the side wall of the SiO2film208covering the gate electrode207.

In the example ofFIG. 19A, it should be noted that the shallow trench structure201B in the substrate201is replaced with an n-type well201C.

Next, in the step ofFIG. 19B, an amorphous silicon film212doped with P is deposited on the structure ofFIG. 19Atypically with a thickness of 100–200 nm. Further, the amorphous silicon film212is patterned in the step ofFIG. 19C, and there is formed an amorphous silicon pattern212A in correspondence to the polysilicon pattern203. Simultaneously, there is formed a conductive plug212B between a pair of adjacent gate electrodes207so that the conductive plug212B makes a contact with the surface of the Si substrate201. Here, the amorphous silicon pattern212A forms, in the analog circuit region A, the capacitor C together with the SiO2film211A and the polysilicon pattern203. Further, the conductive plug212B constitutes an interconnection electrode similar to the conductive plug210B ofFIG. 18G.

FIGS. 20A–20Dshow the fabrication process of a semiconductor device260according to a thirteenth embodiment of the present invention, wherein those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.

Referring toFIG. 20A, an SiO2film213is deposited on the structure ofFIG. 18Dby a CVD process with a thickness of 30–50 nm, wherein the SiO2film213thus formed is subjected to an etch-back process in the step ofFIG. 20B, and an SiO2film213A covering the polysilicon pattern203and an SiO2film213B covering the gate electrode207are formed simultaneously. During this etch-back process, the SiO2film213is protected by a resist pattern (not shown) in correspondence to the analog circuit region. In the step ofFIG. 20A, it should be noted that the shallow trench structure201B ofFIG. 18Dis replaced with the n-type well201C. Further, the SiO2film constituting the top part of the gate electrode207is indicated inFIG. 20Bas a part of the SiO2film213B.

Further, in the step ofFIG. 20C, an amorphous silicon film214doped with P is deposited on the structure ofFIG. 20Bwith a thickness of 100–200 nm. By patterning the amorphous silicon film214thus deposited, there is formed an upper electrode214A of the capacitor C and the conductive plug214B of the DRAM.

FIG. 21shows the construction according to a fourteenth embodiment of the present invention, wherein the construction ofFIG. 21is used in the semiconductor device200ofFIG. 15Dfor making an electrical contact with the capacitor C formed in the analog circuit region. InFIG. 21, those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.

Referring toFIG. 21, there is formed a contact hole109C in the upper interlayer insulation film109so as to expose the upper electrode108A of the capacitor C, and an electrode113A is formed on the interlayer insulation film109so as to fill the contact hole109C. Further, another contact hole109D is formed in the interlayer insulation film109so as to penetrate through the SiO2film107and expose the lower electrode106A. Further, an electrode113B is formed on the interlayer insulation film109so as to cover the contact hole109D.

FIG. 22shows the construction according to a fifteenth embodiment of the present invention, wherein the construction ofFIG. 22is used in the semiconductor device250ofFIG. 19Cfor making an electrical contact with the capacitor C formed in the analog circuit region A. InFIG. 22, those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.

Referring toFIG. 22, a part of the upper electrode212A extends outside the capacitor C to form an extension part212Aex, and the interlayer insulation film213is formed so as to cover the capacitor C. The interlayer insulation film213is formed with a contact hole213A exposing the foregoing extension part212Aex, and there is formed an electrode214A so as to fill the contact hole213A on the interlayer insulation film213. Further, the interlayer insulation film213is formed with a contact hole213B exposing the lower electrode203of the capacitor C, and an electrode214B is formed on the interlayer insulation film213in electrical contact with the lower electrode203via the contact hole213B.

In the description heretofore, the explanation of the invention was made with regard to the embodiments that use a field oxide film for the device isolation. However, the present invention is by no means limited to these specific embodiments but is applicable also to the device that uses a shallow trench isolation for the device isolation structure.

Further, it is not necessary for the contact holes to expose the substrate but the contact holes may make an electrical contact with a corresponding diffusion region via a conductive plug formed in the contact hole.

Further, the present invention is not limited to the embodiments described heretofore, but various variations and modifications may be made without departing from the scope of the invention.

The present application is based on Japanese priority applications No.10-292516 filed Oct. 14, 1998 and No.11-42291 filed Feb. 19, 1999, the entire contents of which are hereby incorporated by reference.