Operational transconductance amplifier and a method for converting a differential input voltage to a differential output current

An operational transconductance amplifier, that may include a first differential pair that comprises a first transistor and a second transistor that are coupled to each other at a certain node; wherein the first differential pair is configured to convert a differential input voltage to first and second output currents; a current source that is coupled to the certain node and may include an adjustable current sources; and a feedback unit that is coupled to the certain node and is configured to (a) receive the differential input voltage, and maintain a voltage of the certain node substantially fixed regardless of changes in the differential input voltage.

BACKGROUND OF THE INVENTION

Operational amplifier that require a responds to large input signals usually use some slew rate boosting techniques. Most operational amplifiers uses a differential input stage constructed with an input pair transistors and a tail current. The current of a differential input stages is defined by its tail current. In the event of a step response, the maximum current the differential pair can drive is limited by the tail current. Common methods to mitigate this challenge is known as current boosting or slew rate enhancement. There are many different slew rate boosting techniques. In general they are divided in to two groups.

Techniques which enhance the output driving current (such as class AB output stage) and ones which boost the input differential pair tail current. Most of the techniques to boost tail current are based on a feedback current branches or voltage nodes further along the signal path of the amplifier. Such techniques defines the amplifier architecture.

SUMMARY

According to an embodiment of the invention there may be provided an operational transconductance amplifier and a method.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1illustrates an example of operational transconductance amplifier10.

The operational transconductance amplifier is configured to drive large current with respect to its input voltage and it may be limited only by the dimensions of the differential input pair.

The suggested operational transconductance amplifier may provide a simple input stage architecture which is insensitive to the type of load it drives or the amplifier architecture. In addition, the operational transconductance amplifier doesn't interfere a differential pair operation, doesn't change its characteristics (including voltage swing, noise or offset).

A differential input pair30that includes a first transistor (M131) and a second transistor (M232) that are coupled to each other at a certain node (at node90) together with a current tail (40). The differential input pair is configured to convert a differential input voltage (which equals the difference between first input voltage VIN121and second input voltage VIN222) to a first output current I111and a second output current I212.

A current source that is coupled to the certain node and may include a fixed tail current source (ITAIL40) and adjustable current sources (third transistor M333and fourth transistor M434). The combination of the fixed tail current from the fixed current source and the currents outputted from the adjustable current sources is a boosted tail current which is driven to the output current (I111I212) according to the input voltages.

In contrary to a common differential pair (in which the maximum output current in either of the current outputs is limited to the fixed current tail current)—the suggested operational transconductance amplifier provides a much higher output current.

Feedback unit (70) that is coupled to the certain node and is configured to (a) receive the differential input voltage, (b) maintain a voltage (VCM91) of the certain node90substantially fixed regardless of changes in the differential input voltage, and (c) control the adjustable current sources (third transistor M333and fourth transistor M434) based on the differential input voltage.

The feedback unit70may include first feedback sub-unit71and second feedback sub-unit72.

First feedback sub-unit71is configured to (a) receive a first input voltage (VIN121), and (b) control a first adjustable current source (M333) of the adjustable current sources, based on the first input voltage.

Second feedback sub-unit72is configured to (a) receive a second input voltage (VIN222), and (b) control a second adjustable current source (M434) of the adjustable current sources, based on the second input voltage.

First feedback sub-unit71is configured to maintain the voltage (VCM91) of the certain node substantially fixed regardless of an increase in the second input voltage (VIN222).

Second feedback sub-unit72is configured to maintain the voltage (VCM91) of the certain node substantially fixed regardless of an increase in the first input voltage (VIN121).

Each one of the first feedback sub-unit and the second feedback sub-unit could be comprises a folded cascode amplifier.

FIG. 1illustrates the first feedback sub-unit71as including a first amplifier61and a first voltage source51that virtually adds a threshold voltage Vth to VCM91(voltage of node90). The first voltage source is coupled to a non-inventing input of the first amplifier61. An inverting input of the first amplifier is fed by the first input voltage VIN121.

FIG. 1illustrates the second feedback sub-unit72as including second amplifier62and a second voltage source52that virtually adds a threshold voltage Vth the VCM91of node90. The second voltage source52is coupled to a non-inventing input of the second amplifier62. An inverting input of the second amplifier62is fed by the second input voltage VIN222.

The first and second amplifiers (61and62) are configured to detect changes in the first and second input voltages (minus Vth) in reference to the VCM91(of node90).

When one of the first and second input voltages drops below (VCM91+VTN) the corresponding amplifier drives its output high turning on the respective adjustable current source out of third and fourth transistors (M333or M434) so as to driver additional tail current to the outputs of M131or M232(for outputting first output current I1and second output current, I2).

The selective operation of the adjustable current sources creates a low impedance on node90enabling first and second transistors M131and M232to behave as a common source NMOS with no limit current. This allows a user to connect any load to the terminal over which the first and second output currents (I1and I2) are supplied.

FIG. 2illustrates an example of operational transconductance amplifier10′.

The first feedback sub-unit71includes seventh transistor M737and serially coupled elements that include (a) first additional fixed current source I343, (b) fifth transistor M535. and (c) second additional fixed current source I545.

The gates of the seventh transistor M737and the first transistor M131receive the first input voltage VIN121.

The second feedback sub-unit72includes eighth transistor M838and serially coupled elements that include (a) third additional fixed current source I444, (b) sixth transistor M636, and (c) fourth additional fixed current source I646.

The gates of the eighth transistor M838and the second transistor M232receive the second input voltage VIN222.

Seventh transistor M737and eighth transistor M838are in a folded cascade connection which allows the wide input swing option. With this architecture, each one of the first and second input voltages can swing between VTH+VDS (drain source voltage) as in a standard differential N-type pair to as high as VDD−VDS (VDD being the voltage supply). To decrease offset and noise of this topology the value of the tail current can be adjust to place the amplifiers at saturation level up to certain differential input level.

This method and device allows to be used in any amplifier design that requires a differential input stage.

The suggested operational transconductance amplifier improves the driving capability of the differential pair with no effect to its other parameters such as input voltages, noise and offset. This concept can be implemented also for a PMOS type differential pair.

FIG. 3is an example of method100.

Method100is for converting a differential input voltage to an amplifier tail current.

Method100may start by steps110,120and130.

Step110may include receiving, by a first differential pair, the differential input voltage. The differential input voltage is a difference between a first input voltage and a second input voltage. The first differential pair may include a first transistor and a second transistor that are coupled to each other at a certain node.

Step110may be followed by step115of converting, by the first differential pair, the differential input voltage to two output currents.

Step120may include feeding, by a current source that is coupled to the certain node, the first differential pair with a boosted tail current. The current source may include an adjustable current sources and may include a fixed tail current source. The boosted tail current is a sum of currents outputted by the first tail current source and the adjustable current sources.

Step130may include receiving, by a feedback unit that is coupled to the certain node, the differential input voltage.

Step130may be followed by step135.

Step135may include maintaining, by the feedback unit, a voltage of the certain node substantially fixed regardless of changes in the differential input voltage. This may be achieved by controlling, by the feedback unit, the adjustable current sources based on the differential input voltage.

The feedback unit may include a first feedback sub-unit and a second feedback sub-unit.

Step130may include receiving, by the first feedback sub-unit, the first input voltage, and receiving, by the second feedback sub-unit, the second input voltage.

Step135may include at least one of the following:

a. Controlling, by the first feedback sub-unit, a first adjustable current source of the adjustable current sources, based on the first input voltage.

b. Controlling, by the second feedback sub-unit, a second adjustable current source of the adjustable current sources, based on the second input voltage.

c. Maintaining, by the first feedback sub-unit, the voltage of the certain node substantially fixed regardless of an increase in the second input voltage.

d. Maintaining, by the second feedback sub-unit, the voltage of the certain node substantially fixed regardless of an increase in the first input voltage.

Each one of the first feedback sub-unit and the second feedback sub-unit may include a folded cascode amplifier or any other eligible amplifier.

FIG. 4is an example of a comparison of relationships between differential input voltage and output currents I1and I2.

Curves201and202represent the relationship between I1and I2(respectively) and the input differential voltage of a prior art circuit.

Curves211and212represent the relationship between I1and I2(respectively) and the input differential voltage of the operational transconductance amplifier ofFIGS. 1-2.

Any reference to any of the terms “comprise”, “comprises”, “comprising” “including”, “may include” and “includes” may be applied to any of the terms “consists”, “consisting”, “consisting essentially of”. For example—any of the rectifying circuits meaning illustrated in any figure may include more components that those illustrated in the figure, only the components illustrated in the figure or substantially only the components illustrated in the figure.

In the foregoing specification, the invention has been described with reference to specific examples of embodiments of the invention. It will, however, be evident that various modifications and changes may be made therein without departing from the broader spirit and scope of the invention as set forth in the appended claims. Moreover, the terms “front,” “back,” “top,” “bottom,” “over,” “under” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.

Those skilled in the art will recognize that the boundaries between logic blocks are merely illustrative and that alternative embodiments may merge logic blocks or circuit elements or impose an alternate decomposition of functionality upon various logic blocks or circuit elements. Thus, it is to be understood that the architectures depicted herein are merely exemplary, and that in fact many other architectures can be implemented which achieve the same functionality. Any arrangement of components to achieve the same functionality is effectively “associated” such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as “associated with” each other such that the desired functionality is achieved, irrespective of architectures or intermedial components. Likewise, any two components so associated can also be viewed as being “operably connected,” or “operably coupled,” to each other to achieve the desired functionality.