Fin-type field effect transistor structure and manufacturing method thereof

A fin-type field effect transistor including a substrate, insulators, a gate stack, a seal spacer, a first offset spacer, and a second offset spacer is described. The substrate has fins thereon. The insulators are located over the substrate and between the fins. The gate stack is located over the fins and over the insulators. The seal spacer is located over the sidewall of the gate stack. The first offset spacer is located over the seal spacer. The second offset spacer is located over the first offset spacer.

BACKGROUND

As semiconductor devices keep scaling down in size, three-dimensional multi-gate structures, such as the fin-type field effect transistor (FinFET), have been developed to replace planar CMOS devices. A structural feature of the FinFET is the silicon-based fin that extends upright from the surface of the substrate, and the gate wrapping around the channel further provides better electrical control over the channel.

DETAILED DESCRIPTION

The embodiments of the present disclosure describe the exemplary manufacturing processes of FinFETs and the FinFETs fabricated therefrom. The FinFET may be formed on bulk silicon substrates in certain embodiments of the present disclosure. Still, the FinFET may be formed on a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate as alternatives. Also, in accordance with the embodiments, the silicon substrate may include other conductive layers or other semiconductor elements, such as transistors, diodes or the like. The embodiments are not used to limit the contexts.

In accordance with the embodiments,FIG. 1is an exemplary flow chart showing the process steps of the manufacturing method for forming a FinFET. The various process steps of the process flow illustrated inFIG. 1may include multiple process steps as discussed below.FIGS. 2A-2Gare perspective views showing the FinFET200at various stages of the manufacturing method for forming the FinFET according to some embodiments of the present disclosure.FIGS. 3A-3Gare cross-sectional views of the FinFET200taken along the line I-I′ ofFIGS. 2A-2Grespectively. It is to be noted that the process steps described herein cover a portion of the manufacturing processes used to fabricate a FinFET device.

FIG. 2Ais a perspective view of the FinFET200at one of various stages of the manufacturing method, andFIG. 3Ais a cross-sectional view of the FinFET200taken along the line I-I′ ofFIG. 2A. In Step10and as shown inFIGS. 2A and 3A, a substrate100having fins102thereon is provided. In some embodiments, the substrate100is a bulk silicon substrate. Depending on the requirements of design, the substrate100may be a p-type substrate or an n-type substrate and include different doped regions. The doped regions may be configured for an n-type FinFET or a p-type FinFET. In some embodiments, the substrate100having the fins102thereon is formed by the following steps: forming a mask layer104over the substrate100; forming a photo-sensitive pattern on the mask layer104and over the substrate100; patterning the substrate100to form trenches106in the substrate100and forming the fins102between the trenches106by etching into the substrate100, using the photosensitive pattern and the mask layer104as etching masks. In some embodiments, the mask layer104is a silicon nitride layer formed by, for example, chemical vapor deposition (CVD). In some embodiments, the trenches106are strip-shaped and arranged in parallel.

FIG. 2Bis a perspective view of the FinFET200at one of various stages of the manufacturing method, andFIG. 3Bis a cross-sectional view of the FinFET200taken along the line I-I′ ofFIG. 2B. In Step12, insulators108are formed between the fins102. The trenches106are filled with an insulating material (not shown). In some embodiments, the insulating material includes silicon oxide, silicon nitride, silicon oxynitride, a spin-on dielectric material, or a low-k dielectric material. The insulating material is formed by high-density-plasma chemical vapor deposition (HDP-CVD), sub-atmospheric CVD (SACVD) or by spin-on. Optionally, a chemical mechanical polish process is performed to remove the projected insulating material and the remaining mask layer104(referring toFIG. 2A). Afterwards, the insulating material filled in the trenches106between the fins102is partially removed by an etching process. In some embodiments, the etching process is performed by using a wet etching process with hydrofluoric acid (HF). In another embodiment, the etching process is performed by using a dry etching process. The insulating material remaining in the trenches106becomes the insulators108with top surfaces108alower than the top surfaces102aof the fins102. Upper portions110of the fins102protrude from the top surfaces108aof the insulators108.

FIG. 2Cis a perspective view of the FinFET200at one of various stages of the manufacturing method, andFIG. 3Cis a cross-sectional view of the FinFET200taken along the line I-I′ ofFIG. 2C. In Step14, a stack structure112is formed over the substrate100and on the insulators108, and across and over the upper portions110of the fins102. InFIG. 2C, two stack structures112are shown. The number of the stack structures112shown here is for illustrative purposes and is not intended to limit the structure of the present disclosure. The stack structures112are arranged in parallel. The stack structure112includes a dielectric layer120and a polysilicon strip122located over the dielectric layer120. In some embodiments, one of the stack structures112covers the upper portions110of the fins102. In some embodiments, the stack structure112is formed by depositing an oxide layer (not shown), depositing a polysilicon layer (not shown) over the oxide layer, and then patterning the polysilicon layer to form the polysilicon strip122and the dielectric layer120.

In Step16, a seal spacer114is formed over the sidewall of the stack structure112(the polysilicon strip122). In some embodiments, the seal spacer114is formed of dielectric materials, such as silicon carbide nitride (SiCN), silicon-carbon-oxy-nitride (SiCON) or a combination thereof. In some embodiments, the seal spacer114has a thickness of 1-2 nm over the polysilicon strip and has a dielectric constant of 4-7. In some embodiments, the seal spacer114is formed by depositing a blanket layer of a dielectric material by atomic layer deposition (ALD) and performing an anisotropic etching process to form the seal spacer114on both sides of the stack structure112. In some embodiments, the seal spacer114is formed of SiCN with a carbon concentration of 1-12 at % (atomic percent) to retain needed etching selectivity and a dielectric constant of 4-7. The ALD SiCN with carbon doped improves the needed etching selectivity for the stack structure112(the polysilicon strip122). Thus, the inside-out gate to contact or gate to source and drain short risk is eliminated. The stack structure112overlaps with and covers portions of the upper portions110of the fins102and the covered portions of the upper portions110of the fins102are used to form channel regions of the FinFET200. Portions of the upper portions110of the fins102that are not covered by the stack structures112are referred to as exposed portions118hereinafter. The extending direction of the stack structure112is perpendicular to the extending direction of the fin102. In some embodiments, light-doped regions116are formed on the exposed portions118of the fins102, and the light-doped regions116are formed by performing an ion implantation.

FIG. 2Dis a perspective view of the FinFET200at one of various stages of the manufacturing method, andFIG. 3Dis a cross-sectional view of the FinFET200taken along the line I-I′ ofFIG. 2D. In Step18, a first offset spacer124is formed over the seal spacer114. In some embodiments, the first offset spacer124is formed of dielectric materials, such as SiCON, SiOF, SiCO or a combination thereof. In some embodiments, the first offset spacer124has a thickness of 2-6 nm over the seal spacer114and has a dielectric constant of 3-5. In some embodiments, the first offset spacer124is formed by depositing a blanket layer of a dielectric material by atomic layer deposition and performing an anisotropic etching process to form the first offset spacer124over the seal spacer114. In some embodiments, the first offset spacer124is formed of SiCON to maintain lowest K to maintain gate to source and drain capacitance.

In Step20, a dummy spacer126is formed over the first offset spacer124. In some embodiments, the dummy spacer126is formed of dielectric materials, such as silicon SiCN, SiCON or a combination thereof. In some embodiments, the dummy spacer126has a thickness of 2-6 nm over the first offset spacer124and has a dielectric constant of 5-7. In some embodiments, the dummy spacer126is formed by depositing a blanket layer of a dielectric material by atomic layer deposition and performing an anisotropic etching process to form the dummy spacer126over the first offset spacer124. In some embodiments, the dummy spacer126is formed of SiCN with a carbon concentration of 0.5-2 at % to help retain the dummy spacer126(1-2 nm at gate to fin bottom corner) robustness during the subsequent etching process and with a dielectric constant of 5-7 while preventing carbon residue induced abnormal epitaxy during SiGe source drain (SD) etching.

In some embodiments, the dummy spacer126and the first offset spacer124are formed by depositing two blanket layers of a dielectric material by atomic layer deposition and performing an anisotropic etching process to form the dummy spacer126and the first offset spacer124.

FIG. 2Eis a perspective view of the FinFET200at one of various stages of the manufacturing method, andFIG. 3Eis a cross-sectional view of the FinFET200taken along the line I-I′ ofFIG. 2E.FIG. 5is a cross-sectional view showing the FinFET at one of the various stages of the manufacturing method according to some alternative embodiments of the present disclosure. In Step22, recesses128are formed in the fins102by removing portions of the fins102that are not covered by the stack structure112(SD etching). In some embodiments, the exposed portions118(FIG. 2D) of the fins102are removed to form the recesses128, for example, by using anisotropic etching, isotropic etching or a combination thereof. In some embodiments, the fins102are recessed below the top surfaces108aof the insulators108. In some embodiments, during the etching of the exposed portions118of the fins102, a portion of the dummy spacer126remains. In some embodiments, as illustrated inFIG. 5, during the etching of the exposed portions118of the fins102, the dummy spacer126is removed.

FIG. 2Fis a perspective view of the FinFET200at one of various stages of the manufacturing method, andFIG. 3Fis a cross-sectional view of the FinFET200taken along the line I-I′ ofFIG. 2F. In Step24, strained material portions130are formed in the recesses128between the insulators108by filling a strained material (not shown) into the recesses128. The strained material portions130are located on opposite sides of the stack structure112. In some embodiments, the material of the strained material portions130includes SiGe, silicon carbon (SiC) or SiP, for example. In some embodiments, the strained material portions130are formed by selectively growing epitaxy. After the recesses128are filled with the strained material, further epitaxial growth of the strained material causes the strained material portions130to expand upward and horizontally beyond the recesses128and above the insulators108. Since the lattice constant of the strained material is different from that of the material of the substrate100, the channel region is strained or stressed to increase carrier mobility of the device and enhance the device performance. In some embodiments, some of the strained material portions130are formed with facets and the portions of the strained material portions130below the top surfaces108aof the insulators108are referred as base portions. Then, the strained material portions130are implanted to form source and drain regions (labelled as130as well). The source and drain regions, also called strained source and drain regions, are located on opposite sides of the stack structure112. In some embodiments, the source and drain regions130are optionally formed with silicide top layers (not shown) by silicidation.

FIG. 2Gis a perspective view of the FinFET200at one of various stages of the manufacturing method, andFIG. 3Gis a cross-sectional view of the FinFET200taken along the line I-I′ ofFIG. 2G. In Step26, a gate stack132is formed after the stack structure112is removed. An inter-layer dielectric layer134is formed over the stack structure112. In some embodiments, the inter-layer dielectric layer134includes carbon-containing oxides, silicate glass, or a suitable dielectric material. In some embodiments, the inter-layer dielectric layer134is made of a single material. In alternative embodiments, the inter-layer dielectric layer134includes a multi-layer structure. The inter-layer dielectric layer134may be filled until its top surface is higher than the top surface of the stack structure112. A planarization step such as CMP is then performed to remove excess of the inter-layer dielectric layer134. In some embodiments, the stack structure112is used as a polish stop layer, so that the top surface of the inter-layer dielectric layer134is substantially level with the top surface of stack structure112. In some embodiments, the dielectric layer120and the polysilicon strips122located over the dielectric layer120are removed by anisotropic etching and the seal spacers114, the first offset spacer124and the dummy spacer126remain.

Then, a gate dielectric layer136is formed in the recesses between the seal spacers114and over the top surfaces and the sidewalls of the fins102. In some embodiments, the material of the gate dielectric layer136includes silicon oxide, silicon nitride or a combination thereof. In some embodiments, the gate dielectric layer136includes a high-k dielectric material, and the high-k dielectric material has a k value greater than 7.0 and includes a metal oxide or a silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb and a combination thereof. In some embodiments, the gate dielectric layer136is formed by ALD, molecular beam deposition (MBD), physical vapor deposition (PVD) or thermal oxidation. Then, a gate electrode layer138is formed over the gate dielectric layer136, over the covered portions (the channel regions) and fills the remaining recesses between the seal spacers114. In some embodiments, the gate electrode layer138includes a metal-containing material, such as Al, Cu, W, Co, Ti, Ta, Ru, TiN, TiAl, TiAlN, TaN, TaC, NiSi, CoSi or a combination thereof. The materials of the gate dielectric layer136and/or the gate electrode layer138are chosen depending on whether the FinFET200is a p-type FinFET or an n-type FinFET. Optionally, a CMP process is performed to remove the excess of the gate dielectric layer136and the gate electrode layer138. The seal spacers114, the first offset spacers124and the dummy spacers126are located over sidewalls of the gate dielectric layer136and the gate electrode layer138. That is, the stack structures112are replaced and the replacement gate stacks132are formed. In some embodiments described herein, the gate stacks132are replacement gates, but the gate stack structures or the fabrication processes thereof are not limited by these embodiments.

In some embodiments, the gate stacks132are located over the insulators108and the source and drain regions (strained material portions130) are located on two opposite sides of the gate stacks132. The gate stack132covers the channel regions of the fins102, and the resultant FinFET200includes a plurality of fins.

FIG. 2His a perspective view of the FinFET200at one of various stages of the manufacturing method, andFIG. 3His a cross-sectional view of the FinFET200taken along the line I-I′ ofFIG. 2G. In Step28, a self-aligned contact process is performed. A portion of the gate electrode layer138is removed to form a recess in the gate electrode layer138. In some embodiments, a portion of the gate electrode layer138is removed by anisotropic etching, isotropic etching or a combination thereof. A cap layer140is formed to fill the recess. The caplayer140is formed of silicon nitride, silicon oxide or a combination thereof, for example. In some embodiments, the cap layer140may be filled until its top surface is higher than the top surface of the inter-layer dielectric layer134. A planarization step such as CMP is then performed to remove excess of the cap layer140.

An inter-layer dielectric layer142is formed over the inter-layer dielectric layer134. In some embodiments, the inter-layer dielectric layer142includes carbon-containing oxides, silicate glass, or a suitable dielectric material. In some embodiments, the inter-layer dielectric layer142is made of a single material. In alternative embodiments, the inter-layer dielectric layer142includes a multi-layer structure. Then, a hard mask layer144is formed over the inter-layer dielectric layer142. In some embodiments, the hard mask layer144is a titanium nitride layer formed by, for example, physical vapor deposition (PVD). Then, the hard mask layer144is patterned. The inter-layer dielectric layer142and the inter-layer dielectric layer134are removed to expose the gate stack132, the seal spacer114, the first offset spacer124, the dummy spacer126and a portion of the strained material portions130by using the patterned hard mask layer144as etching masks.

FIG. 2Iis a perspective view of the FinFET200at one of various stages of the manufacturing method, andFIG. 3Iis a cross-sectional view of the FinFET200taken along the line I-I′ ofFIG. 2I. The patterned hard mask layer144is removed by a wet etching process or a dry etching process, for example. In Step30, a second offset spacer146is formed over the dummy spacer126. In some embodiments, the second offset spacer146is formed of dielectric materials, such as silicon carbide nitride (SiCN), SiC, SiCON or a combination thereof. In some embodiments, the second offset spacer146has a thickness of 3-7 nm over the dummy spacer126and has a dielectric constant of 3-6. In some embodiments, the second offset spacer146is formed by depositing a blanket layer of a dielectric material by atomic layer deposition and performing an anisotropic etching process to form the second offset spacer146over the dummy spacer126. In some embodiments, the dummy spacer126is removed during the etching of the exposed portions118of the fins102, and the second offset spacer146is formed over the first offset spacer124. In some embodiments, the second offset spacer146is formed to maintain a desired thickness to cope with the following etching that is performed to break the bottom portion on top of the fins102(EPI).

In Step32, a treatment process is performed to passivate dangling bonds of the second offset spacer146. In some embodiments, the treatment process includes in-situ forming-gas anneal or UV curing. In some embodiments, in-situ forming-gas anneal or UV curing is performed to passivate dangling bonds that are created during etch, which prevents oxide formation and therefore prevents loss induced by the pre-silicide native oxide removing process.

In accordance with the embodiments,FIG. 4Ais another exemplary flow chart showing the process steps of the manufacturing method for forming a FinFET. The various process steps of the process flow illustrated inFIG. 4Amay include multiple process steps as discussed below.FIG. 4Bis a perspective view showing the FinFET200at various stages of the manufacturing method for forming the FinFET according to some embodiments of the present disclosure.FIG. 4Cis a cross-sectional view of the FinFET200taken along the line I-I′ ofFIG. 4B. It is to be noted that the process steps described herein cover a portion of the manufacturing processes used to fabricate a FinFET device. InFIG. 4A, the Steps10-24are the same as the Steps10-24ofFIG. 1.FIG. 4BandFIG. 4Cshow processes followingFIG. 2FandFIG. 3Frespectively.

As shown inFIGS. 4A-4C, after the strained material portions130are formed in the recesses128between the insulators108by filling a strained material (not shown) into the recesses128(as shown inFIG. 2FandFIG. 3F).

In Step26, the second offset spacer146is formed over the dummy spacer126. In some embodiments, the second offset spacer146is formed of dielectric materials, such as silicon carbide nitride (SiCN), SiC or a combination thereof. In some embodiments, the second offset spacer146has a thickness of 3-7 nm over the dummy spacer126and has a dielectric constant of 3-6. In some embodiments, the second offset spacer146is formed by depositing a blanket layer of a dielectric material by atomic layer deposition and performing an anisotropic etching process to form the second offset spacer146over the seal spacer114. In some embodiments, the dummy spacer126is removed during the etching of the exposed portions118of the fins102, and the second offset spacer146is formed over the first offset spacer124. In some embodiments, the second offset spacer146is formed to maintain a desired thickness to cope with the following etching that is performed to break the bottom portion on top of fin (EPI).

In Step28, a treatment process is performed to passivate dangling bonds of the second offset spacer146. In some embodiments, the treatment process includes in-situ forming-gas anneal or UV curing. In some embodiments, in-situ forming-gas anneal or UV curing is performed to passivate dangling bonds that are created during etch, which prevents oxide formation and therefore prevents loss induced by the pre-silicide native oxide removing process.

In the above embodiments, the seal spacer114is formed of SiCN with a carbon concentration of 1-12 at % to retain needed selectivity and a dielectric constant of 4-7, the first offset spacer124is formed of SiCON to maintain lowest K to maintain gate to source and drain capacitance, the dummy spacer126is formed of SiCN with a carbon concentration of 0.5-2 at % to help retain the dummy spacer (1-2 nm at gate to fin bottom corner) robustness during the subsequent etching process and with a dielectric constant of 5-7 while preventing carbon residue induced abnormal epitaxy during SiGe source drain (SD) etching, and the second offset spacer146is formed to maintain a desired thickness to cope with the following etching that is performed to break the bottom portion on top of fin (EPI). A treatment process includes in-situ forming-gas anneal or UV curing that is performed to passivate dangling bonds of the second offset spacer146.

In some embodiments of the present disclosure, a fin-type field effect transistor including a substrate, insulators, a gate stack, a seal spacer, a first offset spacer is described. The substrate has a plurality of fins thereon. The insulators are located over the substrate and between the fins. The gate stack is located over the fins and on the insulators. The seal spacer is located over the sidewall of the gate stack. The first offset spacer is located over the seal spacer and has a dielectric constant of 3-5.

In some embodiments of the present disclosure, a fin-type field effect transistor including a substrate, insulators, a gate stack, a seal spacer, a first offset spacer, a dummy spacer and a second offset spacer is described. The substrate has a plurality of fins thereon. The insulators are located over the substrate and between the fins. The gate stack is located over the fins and on the insulators. The seal spacer is located over the sidewall of the gate stack, and a material of the seal spacer includes SiCN with a carbon concentration of 1-12 at %. The first offset spacer is located over the seal spacer. The dummy spacer is located over the first offset spacer and a material of the dummy spacer comprises SiCN with a carbon concentration of 0.5-2 at %. The second offset spacer is located over the dummy spacer.

In some embodiments of the present disclosure, a method for forming a fin-type field effect transistor is described. A substrate is provided. The substrate is patterned to form a plurality of fins. Insulators are formed between the fins. A stack structure is formed over the substrate and on the insulators, wherein the stack structure covers portions of the fins. A seal spacer is formed over the sidewall of the stack structure. A first offset spacer is formed over the seal spacer. A dummy spacer is formed over the first offset spacer. A plurality of recesses are formed in the fins by removing a plurality of portions of the fins that are not covered by the stack structure. A plurality of strained material portions are formed in the recesses between the insulators and on two opposite sides of the stack structure. A second offset spacer is formed over the dummy spacer. A treatment process is performed to passivate dangling bonds of the second offset spacer.