Storage device and method for processing power disable signal

A storage device for connection with a host device via an interface bus, includes a storage unit and a storage controller configured to control access to the storage unit and receive a power disable signal from the host device. The storage controller includes a plurality of processing units, each of which receives an interrupt signal to initiate power disable processing, in response to assertion of the power disable signal.

FIELD

Embodiments described herein relate generally to a storage device and a method for processing a power disable signal.

BACKGROUND

In general, a storage device is connected to a host device (or expander) via an interface bus (host interface bus), such as a serial attached SCSI (SAS) bus or a serial AT attachment (SATA) bus. As a standard of such an interface bus, new power disable specifications are developed. The new power disable specifications are associated with device power management functions. In accordance with the new power disable specifications, an initiator (e.g., the host device) can disable power supply to main elements of the storage device as a target, which include a storage controller.

When a hang-up occurs in the interface bus, it is possible that a storage controller in the storage device is also hung up. According to the new power disable specifications, if the initiator (host device) determines that the interface bus is hung up, the host device asserts a power disable signal PWDIS supplied to the target (i.e., the storage device). When the signal PWDIS is asserted, the storage device should execute processing appropriately even if the storage controller of the storage device is hung up.

DETAILED DESCRIPTION

In general, according to one embodiment, a storage device for connection with a host device via an interface bus, includes a storage unit and a storage controller configured to control access to the storage unit and receive a power disable signal from the host device. The storage controller includes a plurality of processing units, each of which receives an interrupt signal to initiate power disable processing, in response to assertion of the power disable signal.

FIG. 1is a block diagram showing an exemplary configuration of a storage system according to an embodiment. The storage system shown inFIG. 1is incorporated in an electronic device, such as a personal computer, a video camera, a music player, a portable terminal, a mobile phone or a printer device.

The storage system comprises a magnetic disk device10and a host device (hereinafter referred to as a host)20. The magnetic disk device10is a storage device and also called a hard disk drive (HDD). In the description below, the magnetic disk device10will be referred to as the HDD10. The HDD10is connected to the host20via a host interface bus30. The host interface bus30is, for example, an SATA bus. The host20utilizes the HDD10as a storage device for the host.

The host interface bus30comprises a data transceiving line (hereinafter referred to as an “SATAIF line”)31, a power disable signal line (hereinafter referred to as a “PWDIS line”)32, and a power supply line33. In the embodiment, the SATAIF line31comprises a pair of transmission signal lines and a pair of received signal lines. The PWDIS line32is used to transfer a power disable signal PWID (hereinafter referred to simply as a signal PWDIS) from the host20to the HDD10. The signal PWDIS is used to disable the supply of power to the essential elements of the HDD10including a storage controller (hereinafter, referred to simply as a controller)18. The power supply line33is used to supply power from the host20to the HDD10. The voltage applied to the HDD10via the power supply line33will be referred to as V1. In the embodiment, the voltage V1is set to 5 V. However, they may be set to another value.

The HDD10comprises a disk (magnetic disk)11, a head (magnetic head)12, a spindle motor (SPM)13, an actuator14, a first power supply controller (hereinafter referred to as a first PWC)15, a motor driver IC (hereinafter referred to as a servo combo or SVC)16, a head IC17, the controller18, a flash ROM (FROM)191, and a dynamic RAM (DRAM)192. The disk11is a magnetic recording medium having two surfaces, one of which, for example, is used as a recording surface for magnetically recording data. The disk11is spun at high speed by the SPM13. The SPM13is driven by a driving current (or driving voltage) applied by the SVC16. The disk11(more specifically, its recording surface) has a plurality of, for example, concentric tracks.

The head12is disposed in a position corresponding to the recording surface of the disk11. The head12is attached to the tip of the actuator14. When the disk11is spun at high speed, the head12floats above the disk11. The actuator14has a voice coil motor (VCM)140as a driving source for the actuator14. The VCM140is driven by a driving current (voltage) applied by the SVC16. When the actuator14is driven by the VCM140, the actuator14moves the head12over the disk11in a radial direction of the disk11so as to draw an arc.

The HDD10may include a plurality of disks. Further, the disk11shown inFIG. 1may have recording surfaces on both sides thereof, and heads may be provided in association with the respective recording surfaces.

The first PWC15outputs voltages V2and V3using the voltage V1applied by the host20via the power supply line33. Further, the first PWC15stops output of the voltage V3when a signal POFF_REQ is asserted, and resumes the output of the voltage V3when the signal POFF_REQ is deasserted. The voltages V2and V3are applied to the SVC16(more specifically, the second PWC160of the SVC16) and the DRAM192, respectively, via power supply lines151and152, respectively. In the embodiment, the voltages V2and V3are set to 5 V and 2.5 V, respectively. However, they may be set to other values.

The first PWC15further generates and holds a status PWDIS_STS (first status signal) indicative of voltage generation (i.e., power supply) based on the signal PWDIS, when the signal PWDIS is deasserted. A HDC182is informed of the status PWDIS_STS.

The SVC16drives the SPM13and the VCM140under the control of the controller18(more specifically, the HDC182in the controller18). The SVC16includes the second PWC (power controller)160. The second PWC160outputs voltages V4, V5, and V6using the voltage V2applied by the first PWC15. The voltages V4to V6are applied to the controller18via a power supply line161. The voltage V6is also applied to the FROM191. The voltage V4is used as a core voltage for the controller18. The voltage V5is used as an operation voltage for an analog circuit, built in the HDC182of the controller18, such as an interface controller (not shown inFIG. 1) connected to the SATAIF line31. The interface controller is also called a physical layer controller. InFIG. 2, the interface controller is omitted. In the embodiment, the voltages V4, V5, and V6are set to 1 V, 1.8 V, and 2.5 V, respectively. However, they may be set to other values.

The head IC17includes a head amplifier (not shown inFIG. 1), and amplifies a signal (i.e., a read signal) read by the head12. The head IC17also includes a write driver (not shown inFIG. 1), and converts write data received from an R/W channel181in the controller18into a write current, and sends the write current to the head12.

The controller18is formed of, for example, a large-scale integrated circuit (LSI) with a plurality of elements integrated on a single chip, called a system-on-a-chip (SOC). The controller18comprises the read/write (R/W) channel181and the hard disk controller (HDC)182.

The R/W channel181processes signals associated with read/write. The R/W channel181digitizes a read signal, and decodes read data from the digitized data. Further, the R/W channel181extracts, from the digitized data, servo data necessary to position the head12. The R/W channel181encodes write data.

The HDC182is connected to the host20via at least the SATAIF line31and the PWDIS line32included in the host interface bus30. The HDC182receives commands (write and read commands, etc.) from the host20via the SATAIF line31. Based on a control program, the HDC182controls data transfer between the host20and the DRAM192and between the DRAM192and the R/W channel181. The HDC182further controls the SVC16based on the control program. In the embodiment, the control program is stored in a particular area on the disk11, and at least part of the control program is loaded to the DRAM192and used when the HDD10is turned on. The control program may be stored in the FROM191.

The FROM191is a rewritable nonvolatile memory. In the embodiment, part of the storage area of the flash ROM19pre-stores an initial program loader (IPL). In the power-on sequence, the IPL is activated to load at least part of the control program from the disk11to the DRAM192. The power-on sequence is executed when the HDD10is turned on.

The DRAM192is a rewritable volatile memory. The DRAM192provides an area to which at least part of the control program is loaded. The DRAM192also includes an area (i.e., a buffer area) for temporarily storing data to be written to the disk11and data read from the disk11. The DRAM192further includes an area (i.e., a backup area) used to back up a predetermined type of information when the signal PWDIS is asserted.

FIG. 2is a block diagram showing an exemplary configuration of the HDC182shown inFIG. 1. The HDC182comprises CPUs201_0,201_1and201_2, programmable interrupt controllers (PIC)202_0,202_1and202_2, and a test-and-set (TAS) register203.

In a normal state, the CPUs201_0,201_1, and201_2execute predetermined processing of different types in parallel in accordance with the control program. Namely, in the normal state, the CPUs201_0,201_1, and201_2carry out their respective shares of an operation (or processing) requested by the HDC182. For instance, the CPU201_0serves as a host CPU for receiving a command from the host20, interpreting the received command, and controlling data transfer between the host20and the DRAM192. The CPU201_1serves as a servo CPU for causing the SVC16to control movement and positioning of the head12. The CPU201_2controls data writing to the disk11and data reading therefrom by the R/W channel181. However, the CPU (servo CPU)201_1may also control data writing to the disk11and data reading therefrom, and the CPU201_2may perform other processing.

When the signal PWDIS has been asserted, the PICS202_0,202_1, and202_2output interrupt signals to the CPUs201_0,201_1, and201_2, respectively. In accordance with the interrupt signals from the PICS202_0,202_1, and202_2, the CPUs201_0,201_1, and201_2execute a test-and-set command using the TAS register203. By the execution of the test-and-set command, a CPU that should perform processing exclusively is determined from the CPUs201_0,201_1, and201_2. The determined CPU performs, for example, backup processing. Although in the embodiment, the HDC182comprises three CPUs, it may comprise two CPUs or four or more CPUs. Namely, it is sufficient if the HDC182comprises a plurality of CPUs.

Referring then toFIGS. 3 to 5, operation of the HDD10according to the embodiment will be described.FIG. 3is a sequence chart for explaining an exemplary operation performed by the system according to the embodiment from when the host20detects a hang-up of the host interface bus30until when the HDC182of the HDD10shifts to a power-off state.FIG. 4is a sequence chart for explaining an exemplary operation performed by the system according to the embodiment from when the HDC182shifts to the power-off state until when the power-on sequence is completed.FIG. 5is a flowchart for explaining an exemplary procedure of the power-on sequence.

It is assumed first that the host20has issued a command to the HDD10via the SATAIF line31of the host interface bus30. In this case, the HDC182of the controller18of the HDD10, in a normal state, executes the command from the host20. Further, in a normal state, the HDC182returns a response indicative of completion of the command to the host20when the command has been executed.

However, a state wherein the HDC182cannot return a response indicative of the completion of the command to the host20may exist for some reason. If, for example, the host20does not receive the response indicative of the completion of the command from the HDD10after it waits for a predetermined period, the host20determines that the host interface bus30(more specifically, the SATAIF line31of the host interface bus30) is hung up. At this time, it is possible that in the HDC182of the HDD10, the host CPU in the CPUs201_0to201_2, e.g., the CPU201_0, which is configured to perform interface (communication) control between the host20and the HDC182, is hung up.

If the host20determines that the host interface bus30is hung up, it asserts the signal PWDIS in the PWDIS line32(for example, the signal is set to high level “H”) (block301). At this time, the application of the voltage V1to the HDD10by the host20is continued.

The signal PWDIS is transmitted to the first PWC15and the controller18in the HDD10via the PWDIS line32. It should be noted that in the embodiment, the first PWC15does not perform any special operation when the signal PWDIS is asserted. The signal PWDIS reaching the controller18is transmitted to the PICS202_0to202_2in the HDC182of the controller18.

The PICS202_0to202_2output interrupt signals to the CPUs201_0to201_2, respectively, upon assertion of the signal PWDIS, as interrupt request signals. Upon receiving the interrupt signals from the PICS202_0to202_2, the CPUs201_0to201_2jump to respective particular interrupt handlers (or interrupt processing routines) corresponding to the interrupt signals. In accordance with the interrupt handlers, the CPUs201_0to201_2execute backup CPU determination processing for determining a CPU that executes backup processing (hereinafter referred to as a backup CPU), as follows (block302).

First, the CPU201_i (i=0, 1, 2) executes a test-and-set command using the TAS register203, if it is not hung up. Namely, the CPU201_i refers to the TAS register203, and determines whether particular data is set in the TAS register203. The TAS register203is used to assign a processing right (in the embodiment, a backup processing right) to a CPU that has first set the particular data in the TAS register203. The CPU that has acquired the backup processing right exclusively executes the backup processing.

If no particular data is set in the TAS register203, i.e., if the TAS register is not locked, the CPU201_i determines that the backup CPU has not been yet determined. In this case, the CPU201_i sets particular data in the TAS register203in order to set itself as the backup CPU, i.e., to acquire the backup processing right. As a result, the TAS register203is locked.

In contrast, if the particular data has been already set in the TAS register203, i.e., if the TAS register203is locked, the CPU201_i determines that another CPU has been already determined as the backup CPU. In this case, the CPU201_i does not acquire the backup processing right.

It is assumed, here, that the CPU201_2in the CPUs201_0to201_2has acquired the backup processing right in the above-described way. It is apparent that the CPU201_2is not hung up and has set the particular data in the TAS register203first. In this case, the CPU201_2(i.e., the backup CPU201_2) performs the backup processing as described below (block303). Note that any hang-up CPU cannot even access the TAS register203.

First, the backup CPU201_2monitors the level of the signal PWDIS at the HDC182for a predetermined length of a sampling period. According to on this, the backup CPU201_2determines whether the signal PWDIS has actually been asserted by the host20. Namely, the backup CPU201_2determines whether or not the signal PWDIS has been erroneously determined to be an asserted signal because of, for example, a noise.

If the level of the signal PWDIS is “H” during the predetermined length of the sampling period, the backup CPU201_2determines that the signal PWDIS has actually been asserted by the host20. In this case, the backup CPU201_2writes information of a predetermined type to the backup area of the DRAM192(i.e., backs up the data). The information of the predetermined type includes status information held in the controller18and indicative of various types of statuses within the controller18. The information of the predetermined type further includes log information, such as a time-series log, held in the controller18and indicative of the history of operations in the controller18. The status information and log information are used for error analysis. Namely, the information of the predetermined type includes information used for error analysis.

After writing the information of the predetermined type in the DRAM192through the backup processing, the backup CPU201_2sets the DRAM192in a self-refresh mode at the end of the backup processing. The information written to the backup area of the DRAM192is saved therein, i.e., does not disappear, as far as the voltage V3is applied to the DRAM192. Similarly, data stored in the buffer area of the DRAM192is saved therein, i.e., does not disappear. The data stored in the buffer area of the DRAM192includes data (so-called dirty data) not yet written to the disk11when the signal PWDIS is asserted. In the embodiment, even when the host20asserts the signal PWDIS in order to invalidate the supply of power to the essential elements in the HDD10including the controller18, the dirty data, the status information, and the log information in the HDD10can be saved in the DRAM192.

Further, the CPU201_2executes a head unload operation if the head12is floating above the disk11. Namely, the CPU201_2unloads (i.e., retracts) the head12from the disk11and moves to a particular place called a ramp, using the SVC16. As a result, when the application of the voltage V2to the SVC16is stopped, the head12is prevented from contacting the disk11because of the stop of the rotation of the disk11.

After finishing the backup processing (block303), the backup CPU201_2asserts the signal POFF_REQ (e.g., sets it to “H”) in order to forcibly stop the application of the voltage V2to the SVC16by the first PWC15(block304). In block304, the backup CPU201_2initializes the TAS register203. As a result, the TAS register203is released from the locked state.

When the backup CPU201_2has asserted the signal POFF_REQ, the first PWC15stops the application of the voltage V2(i.e., the supply of power of the voltage V2) to the SVC16although the voltage V1continues to be applied to the first PWC15by the host20(block305). It should be noted that the first PWC15does not stop the application of the voltage V3to the DRAM192. Thus, the first PWC15continues application of the voltage V3to the DRAM192(i.e., the supply of power of the voltage V3).

When the first PWC15has stopped the application of the voltage V2to the SVC16, the second PWC160of the SVC16stops the application of the voltages V4to V6to the controller18and the application of the voltage V6to the FROM191(block306). This is equivalent to the stop of the application of the voltages V4to V6to the controller18and the stop of the application of the voltage V6to the FROM191by the first PWC15. In contrast, the application of the voltage V3to the DRAM192is continued as mentioned above.

In order to inform the controller18of the stop of the application of the voltages V4to V6to the controller18, the SVC16asserts a signal RESETX (e.g., set the signal to low level “L”) (block307). This signal PRESETX is transmitted to the HDC182. Block306may be executed immediately after block307. The “L” state of the signal RESETX is continued at least during the stop of the application of the voltage V2to the SVC16.

When the second PWC160stops the application of the voltages V4to V6to the controller18, the controller18shifts to the power-off state (block308). At this time, the SATAIF line31is set to a common level.

If the SATAIF line31shifts to the common level after the signal PWDIS is asserted, the host20determines that the host interface bus30may be recovered from the hang-up state. Further, the CPU201_0that caused the assertion of the signal PWDIS may be recovered from the hang-up state. In view of this, the host20de-asserts the signal PWDIS (e.g., set it to “L”) in order to resume the supply of power to the SVC16(block401).

When the signal PWDIS is deasserted, the first PWC15resumes the application of the voltage V2to the SVC16(block402). In block402, the first PWC15sets a valid status PWDIS_STS. The valid status PWDIS_STS is indicative of the fact that the application of the voltage V2to the SVC16(i.e., the supply of power) is resumed in accordance with de-assertion of the once-asserted signal PWDIS. The CPUs201_0to201_2in the HDC182of the controller18are informed of the status PWDIS_STS.

When the application of the voltage V2to the SVC16is resumed, the second PWC160of the SVC16resumes the application of the voltages V4to V6to the controller18and the application of the voltage V6to the FROM191(block403). At this time, the SVC16de-asserts the signal RESETX (e.g., sets it to “H”) in accordance with the resumption of application of the voltage V2(block404). In accordance with the de-assertion of the signal RESETX, the controller18is reset. Namely, in accordance with the start of the application of the voltage V2(i.e., the supply of power), the controller18is reset to the power-on state.

As described above, when the voltage V1is applied to the HDD10by the host20, power-on reset is carried out if the once-asserted signal PWDIS is deasserted. The power-on reset is also carried out in a normal power-on operation during which the application of the voltage V1to the HDD10is started by the host20.

When the controller18is subjected to power-on reset, a predetermined CPU in the HDC182of the controller18, e.g., the CPU201_0, serves as the host CPU and executes a power-on sequence in accordance with the procedure shown in the flowchart ofFIG. 5(block405). In the power-on sequence, the CPU201_0controls an interface controller and thus sets the SATAIF line31in a ready state.

Referring then to the flowchart ofFIG. 5, the power-on sequence will be described. First, the CPU201_0checks the status PWDIS_STS informed by the first PWC15(block501). Subsequently, the CPU201_0determines whether or not the power-on (power-on reset) this time is caused by de-assertion of the signal PWDIS, based on validity of the status PWDIS_STS (block502). As described above, the valid status PWDIS_STS is set by the first PWC15when a once-asserted signal PWDIS is deasserted.

If the status PWDIS_STS is valid in the power-on reset state, the CPU201_0determines that the power-on reset state in this time is caused by the de-assertion of the once-asserted signal PWDIS (Yes in block502). In this case, the CPU201_0executes HDD initialization processing following the power-on caused by the de-assertion of the signal PWDIS (block503). By HDD initialization processing, the elements in the HDD10are initialized. The elements include registers in the R/W channel181. However, the DRAM192is excluded from the initialization targets in block503. As a result, in backup processing (block303inFIG. 3), the information backed up in the backup area of the DRAM192can be prevented from being lost. Data (i.e., data including dirty data) stored in the buffer area of the DRAM192can also be prevented from being lost.

In contrast, if the status PWDIS_STS is invalid in the power-on reset state, the CPU201_0determines that the power-on reset state in this time is caused by a normal power-on in which the application of the voltage V1to the HDD10by the host20is started (No in block502). In this case, the CPU201_0executes HDD initialization processing following the normal power-on (block504). Through the HDD initialization processing in block504, the elements of the HDD10including the DRAM192are initialized.

After executing block503, the CPU201_0writes information that is backed up in the backup area of the DRAM192in the disk11via the R/W channel181and the head IC17(block505). In block505, the CPU201_0also writes, to the disk11, dirty data stored in the buffer area of the DRAM192. In other words, in the embodiment, even if the signal PWDIS is asserted, the application of the voltage V3to the DRAM192is continued, whereby the dirty data is prevented from being lost. Thus, in a power-on sequence executed when the signal PWDIS is deasserted, non-updated data in the disk11can be updated with the dirty data. Further, since the loss of the dirty data can be prevented, the host20can resume access to the HDD10without checking whether any dirty data is lost.

The backup information written to the disk11includes the status information indicative of various statuses in the controller18and time-series log information indicative of the history of the operations in the controller18at the time when the signal PWDIS is asserted. Accordingly, based on the backup information written to the disk11, the cause of the hand-up of the SATAIF line31can be analyzed.

After executing block505, the CPU201_0proceeds to block506. In contrast, after executing block504, the CPU201_0skips block505and proceeds to block506. In block506, the CPU201_0sets the SATAIF line31in a ready state by controlling the interface controller. The ready state of the SATAIF line31is indicative of a state in which the HDD10(more specifically, the HDC182of the HDD10) is communicable with the host20. Thus, if the SATAIF line31is set in the ready state via block503, it indicates that the SATAIF line31is released from the hang-up state.

In the above-described embodiment, the second PWC160is provided in the SVC16. However, it may be provided outside the SVC16. It is apparent that the combination of the first and second PWCs15and160provides a logically single PWC. Further, the HDD10may include a single PWC having functions equivalent to those of the first and second PWCs15and160, instead of the first and second PWCs15and160. In this case, the single PWC may generate the voltages V4to V6from the voltage V1applied via the power supply line33of the host interface bus30.

In the embodiment, a SATA bus is used as the host interface bus30. However, such an interface bus as a SATA express bus, a SAS bus, a SAS express bus, or a peripheral component interconnect (PCI) express bus may be used as the host interface bus30. It is sufficient that the interface bus enables a power disable signal to be transmitted.

Further, in the embodiment, an HDD (magnetic disk device) is used as a storage device. However, a storage device, such as a solid state device (SSD), other than the HDD, may be used instead of the HDD. The SSD is known as a storage device having a recording medium (nonvolatile storage medium) formed of a set of NAND flash memories.

According to at least one embodiment described above, processing can be executed appropriately in a storage device even if a storage controller in the storage device is hung up when a power disable signal is asserted.