A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval must transpire between successive accesses to a given row of the storage cells. Transfer control circuitry is provided to transfer a first amount of data between the plurality of storage banks and an external signal path in response to a first memory access request, the first amount of data being less than a product of the external signal path bandwidth and the minimum access time interval.

FIELD OF THE INVENTION

The present invention relates generally to memory systems and components thereof.

BACKGROUND

Although dynamic random access memory (DRAM) remains the memory of choice for a broad class of computing and consumer electronics applications, DRAM core access times have not scaled with memory bandwidth demand. For example, the minimum time between activation of different storage rows in the same storage bank, tRC, remains in the neighborhood of 40 nanoseconds for predominant core technologies; a substantial access time penalty for processors operating at gigahertz frequencies. Other core access times such as the minimum time between activation of rows in different banks of a multi-bank array, tRR, and minimum time between column access operations (i.e., read or write operations at a specified column address) in the same row, tCC, have also been slow to improve.

Designers have countered core timing limitations through a number of architectural and system-level developments directed at increasing the number of column access operations per row activation (e.g., paging, multi-bank arrays, prefetch operation), and maximizing the amount of data transferred in each column access. In particular, signaling rate advances have enabled progressively larger amounts of data to be transferred per column access, thereby increasing peak memory bandwidth. However, as signaling rates progress deeper into the gigahertz range and the corresponding core access times remain relatively constant, column transaction granularity, the amount of data transferred per column access, is forced to scale upwards and is approaching limits imposed by signal paths within the DRAM itself. Further, the trend in some classes of data processing applications, graphics applications for example, is toward smaller data objects (e.g., triangle fragments of a 3D scene) that are often stored in dispersed memory locations. In such applications, the additional power and resources expended to increase the column transaction granularity may provide only limited increase in effective memory bandwidth as much of the fetched data may not be used.

DETAILED DESCRIPTION

In the following description and in the accompanying drawings, specific terminology and drawing symbols are set forth to provide a thorough understanding of the present invention. In some instances, the terminology and symbols may imply specific details that are not required to practice the invention. For example, the interconnection between circuit elements or circuit blocks may be shown or described as multi-conductor or single-conductor signal lines. Each of the multi-conductor signal lines may alternatively be single-conductor signal lines, and each of the single-conductor signal lines may alternatively be multi-conductor signal lines. Signals and signaling paths shown or described as being single-ended may also be differential, and vice-versa. Similarly, signals described or depicted as having active-high or active-low logic levels may have opposite logic levels in alternative embodiments. As another example, circuits described or depicted as including metal oxide semiconductor (MOS) transistors may alternatively be implemented using bipolar technology or any other technology in which a signal-controlled current flow may be achieved. With respect to terminology, a signal is said to be “asserted” when the signal is driven to a low or high logic state (or charged to a high logic state or discharged to a low logic state) to indicate a particular condition. Conversely, a signal is said to be “deasserted” to indicate that the signal is driven (or charged or discharged) to a state other than the asserted state (including a high or low logic state, or the floating state that may occur when the signal driving circuit is transitioned to a high impedance condition, such as an open drain or open collector condition). Multi-level signaling in which each transmitted symbol conveys more than one bit of information (i.e., bit rate is greater than baud rate) may also be used. A signal driving circuit is said to “output” a signal to a signal receiving circuit when the signal driving circuit asserts (or deasserts, if explicitly stated or indicated by context) the signal on a signal line coupled between the signal driving and signal receiving circuits. A signal line is said to be “activated” when a signal is asserted on the signal line, and “deactivated” when the signal is deasserted. Additionally, the prefix symbol “/” attached to signal names indicates that the signal is an active low signal (i.e., the asserted state is a logic low state). A line over a signal name (e.g., ‘<signal name>’) is also used to indicate an active low signal. The term “terminal” is used to mean a point of electrical connection. The term “exemplary” is used to express an example, not a preference or requirement.

In embodiments described herein, the data transfer capacity of a dynamic random access memory (DRAM) device over a given tCCinterval, a metric referred to herein as a tCCenvelope, is subdivided and allocated to multiple column access transactions, thereby reducing the amount of data transferred in any one transaction, yet maintaining the peak memory bandwidth of the DRAM device. Referring toFIG. 1, for example, instead of following a conventional, single-threaded approach of dedicating each tCCenvelope to a single column access transaction as shown at90, the tCCenvelope is partitioned to enable transfer of multiple smaller sets of data in response to multiple micro-threaded column requests as shown at92. By reducing the column transaction granularity in this manner, the effective bandwidth of the DRAM may be substantially increased over the single-threaded approach as multiple data objects of interest may be specifically addressed in different micro-threaded column access transactions and returned within a given tCCinterval, rather than merely a single data object and its potentially superfluous neighboring data.

In one embodiment, the tCCenvelope is partitioned temporally into a set of partial tCCintervals (tCCp) that are allocated respective micro-threaded column transactions. In another embodiment, the tCCenvelope is spatially partitioned, with data path resources between the memory device core and a host device (e.g., a memory controller) being subdivided and allocated to different micro-threaded column transactions. Referring again toFIG. 1, for example, the data links, DQ, that form an external data path between a memory device and memory controller may be partitioned into two or more subsets of data links, DQp, that are allocated to different micro-threaded column access transactions. In other embodiments, both temporal and spatial partitioning is applied to further reduce the column transaction granularity. InFIG. 1, for example, the tCCenvelope is partitioned temporally into two partial tCCintervals, tCCp, and spatially into two subsets of data links, DQp, thereby reducing the micro-threaded column transaction granularity to one-fourth of the single-threaded column transaction granularity. The tCCenvelope may be subdivided into more or fewer spatial and/or temporal partitions in other embodiments. Also, the multiple micro-threaded column access requests serviced in a partitioned tCCinterval may be directed to an open page of the same storage bank, to open pages of different storage banks, or any combination thereof. Also, in one embodiment, more densely pipelined row operations are used to enable sub-banks within a partitioned bank architecture to be separately addressed, in effect, increasing the number of banks within the memory device and enabling each of multiple micro-threaded column accesses, serviced within the same tCCinterval, to be directed to an independently selected bank, row and column.

Overview of an Exemplary Micro-Threaded Memory Architecture

FIG. 2illustrates an embodiment of a memory device100in which various types of micro-threaded column operations may be performed. The memory device100is assumed, for purposes of description, to be a DRAM device, but may alternately be any type of memory device having multiple storage arrays that share addressing and/or data path resources in a manner that imposes timing constraints on sequential accesses directed to the different storage arrays. Thus, tCCconstraints and tRRconstraints herein may alternatively be other types of memory access constraints that, together with signaling path bandwidth, define corresponding data transfer envelopes. For example, the tCCenvelope partitioning described herein is intended as an instance of more general partitioning of any data transfer envelope defined by an resource-imposed time constraint and signaling path bandwidth. Also, with regard to the timing constraint itself, such constraint may be defined to be a minimum time necessary to avoid resource conflicts within the memory device (e.g., to ensure proper operation), plus an optional tolerance time to account for statistical variation in the time required for circuits and/or signal paths to reach a desired state. A timing constraint may also be enforced or otherwise defined by a timing signal such as a clock signal or strobe signal and thus may be expressed as minimum number of transitions of such timing signal that are to transpire between back-to-back operations in order to avoid resource conflicts within the memory device.

In the particular example shown, the memory device100includes a request interface101, column decoders1030-1033, row decoders1130-1133, data path interfaces105A and105B and eight storage banks, B0-B7. Each storage bank, B0-B7, is formed by a pair of A and B sub-banks (e.g., sub-banks B0-A and B0-B constitute bank B0, sub-banks B1-A and B1-B constitute bank B1, and so forth), with the sub-banks themselves being organized in four groups of four sub-banks each, referred to herein as quadrants. The four quadrants are designated Q0-Q3inFIG. 2. In the embodiment ofFIG. 2, sub-banks in the same quadrant share a row decoder and column decoder, and are all either A or B sub-banks from either the even bank set or odd bank set. For example, quadrant Q0includes even-numbered, group A sub-banks (i.e., B0-A, B2-A, B4-A and B6-A) coupled to column decoder1030via respective column paths (collectively designated1170) and to row decoder1130via respective sets of word lines (collectively designated1150). In the remaining quadrants, Q1includes odd-numbered, group A sub-banks coupled to column decoder1031via column paths1171and to row decoder1131via word lines1151; Q2includes even-numbered, group B sub-banks coupled column decoder1032via column paths1172and to row decoder1132via word lines1152; and Q3includes odd-numbered, group B sub-banks coupled column decoder1033via column paths1173and to row decoder1133via word lines1153. While the architecture of memory device100is carried forward in descriptions of various memory device embodiments described herein, in all cases such memory devices may have any number of banks, any number of sub-banks per bank, and any number of sub-banks per decoder-sharing group.

When operated as part of a memory system, the request interface101of memory device100receives a stream of requests (or commands or instructions) from a memory controller or other host device via a request path (not shown), and issues corresponding control and address signals to the row decoders113and column decoders103to carry out the requested operations. As a matter of terminology, the term “request” is used herein to mean a request, command or instruction issued to the memory device100to cause the memory device to take an action specified in the request or by the context in which the request is received. The action taken by the memory device in response to a given request is referred to as an operation, examples of which include row activation operations, column access operations (which may be read or write accesses) and precharge operations. A request and its corresponding operation are referred to collectively herein as a transaction. Also, some transactions may include multiple component requests and operations. In the case of a DRAM device, for example, a complete data access transaction may be specified by a row-activation request, one or more column access requests and a precharge request. A row activation request is directed to a bank and row of the memory device100(e.g., specified by bank and row addresses included with the request) and is serviced by enabling the contents of the row to be output onto the bit lines of the bank and thereby transferred into a page buffer (e.g., a storage structure formed by latching sense amplifiers coupled respectively to the bit lines). Column access requests are directed to a bank and column of the memory device100(e.g., specified by bank and column addresses included with the request) and are serviced by reading or overwriting data in column-address-specified sub-fields (columns) within the page buffer for the specified bank. After the column accesses directed to an open page (i.e., page buffer content) are completed, a precharge operation may be carried out to precharge the bit lines of the subject bank in preparation for subsequent row activation.

When a row activation request is received, the request interface101recovers bank and row address values from the request and forwards the address values via signal paths1111-1113to the row decoders1130-1133for the bank-address-specified quadrants. In one embodiment, each of the row decoders113includes a first stage decoder to select the set of word lines coupled to a bank-address-specified sub-bank, and a second stage decoder to activate a row-address-specified word line within the selected set of word lines, thereby enabling the contents of the cells coupled to the activated word line onto the bit lines of the selected sub-bank. In other embodiments, the bank and row decoding operation may be carried out in more or fewer decoder stages. Also, one or more row address strobe signals may be issued by the request interface101or other control logic to control the timing of the word line activation.

When a column access request is received in the memory device100, the request interface101recovers bank and column address values from the request and forwards the address values to the column decoders103for the quadrants specified by the bank address. In one embodiment, each of the column decoders103includes a bank multiplexer to enable access to the page buffer for a bank-address indicated sub-bank (i.e., via a selected one of column access paths117), and a column multiplexer to select a column of page buffer storage elements for read or write access. Other circuit arrangements may be used resolve the column access location in alternative embodiments. Also, one or more column address strobe signals may be issued by the request interface101or other control logic in the memory device100to control the timing of the column access.

After column operations in the open page are completed (e.g., read or write operations carried out in response to corresponding column access requests), a precharge request and associated bank address may be received in the request interface101and serviced by deactivating a previously activated word line and precharging the bit lines for the specified bank. After the precharge operation is complete, the specified bank is in condition for another row activation operation.

Still referring toFIG. 2, each of the data path interfaces105A,105B is coupled to respective pairs of column decoders103via column data paths119to enable transfer of read and write data between the column decoders and an external data path (not shown). More specifically, data path interface105A enables data transfer between a first portion of the external data path and selected sense amplifiers within a page buffer (i.e., selected by column decoder1030and1031) via column data paths1190and1191, and data path interface105B enables data transfer between a second portion of the external data path and selected sense amplifiers within a page buffer (i.e., selected by column decoders1032and1033) via column data paths1192and1193.

FIG. 3illustrates more detailed embodiments of the Q0and Q1sub-banks (i.e., sub-banks B0-A through B7-A), column decoders1030/1031, and data interface105A that may be used within the memory device100ofFIG. 2. The Q2and Q3sub-banks, column decoders1032/1033and data interface105B may be implemented in embodiments similar or identical to those depicted inFIG. 3and therefore are not separately described.

In the embodiment ofFIG. 3, each of the sub-banks B0-A to B7-A includes a storage array145and page buffer147coupled to one another via bit lines169. Referring to detail view165, the storage array145is formed by memory cells170arranged in rows and columns. Each column of memory cells170is coupled via a bit line169to a respective sense amplifier168within page buffer147, and each row of memory cells is coupled via a word line166to a row decoder113(or component thereof). In the particular embodiment shown, each memory cell170is a DRAM memory cell formed by a transistor switch (e.g., having a drain coupled to bit line169and a gate coupled to word line166) and a capacitive storage element coupled between the source of the transistor switch and a cell plate reference or other reference node. Memory cells of other types and configurations may be used in alternative embodiments. As discussed above, during a row activation operation, a word line is activated, and contents of the storage cells170coupled to the word line (i.e., the word-line selected row) are enabled onto the bit lines169and thereby transferred to the page buffer147. During a precharge operation, the open page (i.e., content of the page buffer) is closed and the bit lines169precharged in preparation for activation of another row. Refresh operations may be performed in rows of a given sub-bank or set of sub-banks through combinations of activation and precharge operations.

As discussed above, the column decoders1030and1031enable column operations (i.e., read or write operations) directed to open pages within the sub-banks of quadrants Q0and Q1, respectively. In the embodiment ofFIG. 3, each of the column decoders1030,1031includes a set of four column multiplexers149, one for each sub-bank of the corresponding quadrant, and a bank multiplexer151. The bank multiplexer151enables access to (i.e., selects) one of the column multiplexers149in response to a bank address, or at least the most significant bits (MSBs) or other subset of bits within the bank address. Referring to detail view165, the selected column multiplexer149includes a set of multiplexer/demultiplexer circuits164that each enable read or write access to a respective column-address-selected column of storage elements within the page buffer147(column, for short); an operation referred to herein as a column access. In the case of a write operation, the bank multiplexer151and column multiplexer149perform demultiplexing functions, routing data from the data path interface105A to the selected column. In a read operation, the bank multiplexer151and column multiplexer149perform a multiplexing function by routing data from the selected column to the data interface105A. Note that the bank multiplexer151and column multiplexers149may be interchanged in an alternative embodiment, so that the bank multiplexer151is coupled to the sub-bank bit lines169and a single column multiplexer is coupled between the output of the bank multiplexer151and the data path interface105A.

In the embodiment ofFIG. 3, the data path interface105A includes a pair of serdes transceivers173(i.e., serializing/deserializing transceivers that perform a parallel-to-serial conversion of outgoing data and a serial-to-parallel conversion of incoming data) each coupled between an external data path interface171and a respective one of column decoders1030and1031. Each serdes transceiver173includes a data serializer177, transmitter175, data deserializer181and receiver179. In a read operation, the data serializer177performs a multiplexing function by receiving a 128-bit read data value (i.e., column data) from the column decoder103via column data path119and delivering the read data to the transmitter175in the form of a sixteen byte stream. The transmitter175, in turn, transmits each byte via the external data path interface171in successive data transmission intervals. The receiver179and data deserializer181perform the inverse functions of the data serializer177and transmitter175. That is, the receiver179samples signals arriving via the external data path interface171during successive data reception intervals to deliver a stream of sixteen bytes to the data deserializer181. The data deserializer181performs a demultiplexing function by gathering the incoming stream of bytes into a 128-bit data write data value to be delivered to the corresponding column decoder103via column data path119. Although an 8-bit external data path interface171and a 128-bit column data path119are shown, different path widths may be used in alternative embodiments. In alternative embodiments in which data multiplexing/demultiplexing is unnecessary (e.g., external data path width matches the column data size of the memory device), the data serializer177and/or data deserializer181may be omitted.

Still referring toFIG. 3, the transmitters175may be, for example, current-mode or voltage-mode output drivers for generating output waveforms having virtually any amplitude and any type of modulation. Also, the transmitters175may generate multi-bit symbols (i.e., bit rate greater than baud rate), perform various encoding operations (e.g., 8 b/10 b) and/or add error checking information into the outgoing bitstream (e.g., parity bits, error-code correction (ECC) bits, checksum, cyclic-redundancy check values, etc.). The receivers179, similarly, may be designed to sample current-mode or voltage-mode transmissions modulated in any manner, with each sample being resolved into one or more bits according to the number of bits conveyed in each transmitted symbol. The receiver may additionally perform decoding operations and error checking operations. Further, both the transmitter and receiver may be switched between different operating modes and/or frequencies, for example, operating on multi-bit symbols in one mode and single-bit symbols in another mode.

The signaling links that constitute the external data path may be point-to-point or multi-drop, differential or single-ended, and may be used to carry synchronous or asynchronous transmissions. The data path interface105A, accordingly, may be a synchronous or asynchronous signaling interface. In the case of synchronous transmissions, the transmitted data signals may be self-timed (e.g., carrying clocking information within the data waveform) or accompanied by timing signals such as one or more clock signals, strobe signals or the like. In the case of self-timed transmissions, encoding circuitry may be provided in the transmitter175to encode each outgoing bit stream (i.e., the stream transmitted on any single link of the external data path interface in synchronism with one or more transmit clock signals) to ensure sufficient transition density for clock recovery (e.g., 8 b/10 b encoding), and corresponding clock-data recovery circuitry and decoding circuitry may be provided in the receiver179to recover clocking information and the un-encoded transmitted data. Such clocking information, whether received in the form of external timing signals (e.g., clock or strobe signals) or recovered from the incoming bit stream, may be used to control the phase of one or more sampling clock signals that are supplied to the receiver179to trigger sampling of the incoming data signals.

FIG. 4illustrates a single-threaded mode of operation within the memory device100ofFIG. 2and is provided, in part, for contrast with later micro-threaded operating modes described below. Referring to request path201(RQ), a pipelined stream of requests is received over a series of request intervals200, with gray shaded blocks indicating requests that form part of a multi-access read transaction205directed to a selected bank. The striped blocks represent requests directed to other banks. In the exemplary embodiment shown, the request path is operated at a legacy signaling rate (i.e., lower than maximum supported signaling rate) of 0.8 Gigabits per second (Gb/s) per link. Each command is transferred over a pair of transmit intervals, thereby establishing a 2.5 ns request interval. In alternative embodiments, higher or lower signaling rates may be used, and each request may be conveyed in more or fewer transmit intervals.

The request path201is shown as a set of logical pipelines203A,203B and203C to help visualize the relative timing of different types of requests included in the multi-access read transaction205. Pipeline203A is referred to herein as the activation pipeline (RQ-ACT) and carries row activation requests (e.g.,207), each including a row activation command specifier together with bank and row address values to identify the specific row to be activated. Pipeline203B is referred to herein as the column access pipeline (RQ-CA) and carries column access requests (e.g.,209), each including a column access command specifier, specifying either a read or write access, together with bank and column address values to identify the bank and column to be accessed. Pipeline203C is referred to herein as the precharge pipeline and carries precharge requests (e.g.,213) each including a precharge command specifier and bank address to indicate the bank to be precharged.

The multi-access read transaction is initiated when a row activation request207directed to row ‘z’ of bank B0(B0-Rz) is received. The memory device responds to the row activation request by issuing the bank address and row address to the row decoders for bank B0(i.e., row decoders1130and1132). In the particular embodiment shown, the minimum time between row activations in the same bank, tRC, is assumed to be 40 ns so that another row activation request directed to bank B0is not received until sixteen request intervals later, as shown at215. Also, the minimum time between row activations in arbitrarily different banks, tRR, is assumed to be 10 ns, so that another row activation request217is not received until four request intervals later.

The first column access request209of two column access requests that form part of the multi-access read transaction205is received a predetermined time after the activation request207(five request intervals later in this example) and specifies a read at column ‘a’ of the B0open page (B0-Ca). As the minimum time between accesses to the same open page, tCC, is assumed to be 5 ns in this example, and the memory device is operating in single-threaded mode, the second of the two column access requests,211, is received two request intervals after receipt of the first column access request (i.e., a tCCinterval later), and specifies a read at a different column, column ‘b’, of the B0open page (B0-Cb). Referring briefly toFIG. 2, the request interface201responds to the first column access request209by delivering bank and column address values via shaded column address paths1090and1092to the even bank column decoders1030and1032which, in turn, retrieve data from column ‘a’ of the B0-A and B0-B sub-banks as shown. The retrieved column ‘a’ data is then delivered to the data interface via the shaded column data paths1190and1192. The request interface201similarly responds to the second column access request211by delivering bank and column address values to the even bank column decoders2030and2032which then retrieve data from column ‘b’ of the B0-A and B0-B sub-banks and output the data to the data path interfaces105A and105B.

Returning toFIG. 4, the column data retrieved in response to the first column access request209is output onto external DQA and DQB signal paths225in a data transfer operation that begins, a predetermined time after receipt of the column access request209. The correspondence between the column access request209and outgoing (or incoming) column data is illustrated by lead lines227extending from the column access request (i.e., in pipeline203B) to a like-shaded data transfer over signal paths225; a notation used inFIG. 4and other figures described below. In this single-threaded example, column data is transferred in response to the first column access request over the tCCinterval starting at215. More specifically, column ‘a’ data is output from sub-bank B0-A over the DQA links (eight links in this example, though more or fewer links may be provided in alternative embodiments), and column ‘a’ data is output from sub-bank data B0-B over the DQB links, the transfer of column ‘a’ data from the two B0sub-banks thus consuming the entire tCCenvelope as shown. As discussed above, the tCCenvelope is a product of the signaling bandwidth and tCCinterval so that, given a 5 ns tCCinterval (a value assumed throughout the following description, though virtually any memory core technology having the same or different tCCconstraint may be used) and assuming a 3.2 Gb/s signaling rate in each of the 16 DQ links, the tCCenvelope is 32 bytes (i.e., [16 links*3.2 Gb/s/link]*5 ns=256 bits=32 bytes). In the single-threaded example shown, each column access request is serviced per tCCinterval so that the column transaction granularity, CTG, is also 32 bytes. Thus, the column transaction granularity is coextensive with the tCCenvelope.

The column ‘b’ data retrieved in response to the second column access request211is output onto the DQA and DQB signal paths over a tCCinterval that begins at the conclusion of the column ‘a’ data transfer operation. Thus, like the column ‘a’ transaction that precedes it, the column ‘b’ transaction consumes the entire tCCenvelope and therefore has a column transaction granularity of 32 bytes.

Still referring toFIG. 4, a precharge request213is received a predetermined time after the second column access request211(three request intervals in this example) and includes a precharge command specifier (Pre Cmd) and bank address that indicates the bank to be precharged; B0in this case. The request interface executes the requested precharge operation a predetermined time later (e.g., after the column ‘b’ data has been retrieved from the B0-A/B0-B page buffers) by issuing a disable signal to the row decoders for bank B0, and issuing a precharge-enable signal to the page buffers of sub-banks B0-A and B0-B to precharge the sub-bank bit lines. The precharge operation thus closes the page opened in response to the row activation request207and therefore concludes the multi-access read transaction205. Because each of the two column access operations yielded 32 byte transfers, the row transaction granularity (i.e., amount of data transferred for a given row activation, RTG) is 64 bytes. More or fewer column access transactions may be performed for a given row activation in alternative embodiments, yielding correspondingly increased or decreased row transaction granularity.

Assuming that a steady stream of row activation requests and corresponding column access request pairs and precharge requests are received via the request path201, the request path201may remain fully loaded (i.e., no unused request intervals) and the data path225, similarly, may be fully consumed with the requested data transfers, each having 32-byte column transaction granularities and 64-byte row transaction granularities. When the signaling rate on the data path225is increased to the full rate of the memory device, however, the row and column transaction granularities also increase. For example, in one embodiment, the full signaling rate supported by the data path interface105of theFIG. 2memory device is 6.4 Gb/s (other signaling rates may be supported in alternative embodiments). Because the tCCinterval of the memory device remains unchanged, the tCCenvelope is doubled to 64 bytes and, if the single-threaded approach were followed, the column transaction granularity and row transaction granularity would also double to 64 bytes and 128 bytes, respectively. To support the increased column transaction granularity, a number of signal paths within the column decoders and data path interface may need to be increased. Referring toFIGS. 2 and 3, for example, because the 64 byte column transaction granularity corresponds to a 256-bit (32 byte) column access in each of the sub-banks, each of the 128-bit signal paths within the column decoders103(i.e., between the column multiplexer149and bank multiplexer151) and the data path interfaces105A,105B would expand to 256-bit signal paths to support the increased data transfer rate. While potentially realizable, such increased path widths result in increased manufacturing cost and power consumption (i.e., the path widths being increased in each sub-bank and data interface of the memory device) and the headroom available headroom for such increases is shrinking. Also, as discussed above, in applications that tend to access small, dispersed data objects, only a small portion of the data returned in a given column access may be useful. For example, a common triangle size in modern graphics applications is six bytes and, due to rendering order, successively rendered triangles are often unlikely to be acquired in the same column access. In such applications, doubling the column transaction granularity from 32 bytes to 64 bytes may provide little improvement in effective bandwidth.

FIG. 5illustrates a request interface that may be used to support a single-threaded mode of operation within the memory device as well as micro-threaded modes of operation discussed below. The request interface300includes a request decoder301, even-bank row control registers305A,305B (EBRC), odd-bank row control registers307A,307B (OBRC), even-bank column control registers309A,309B (EBCC) and odd-bank column control registers311A,311B (OBCC). The even- and odd-bank row control registers305,307are coupled to the request decoder301via a row bus315, and the even- and odd-bank column control registers309,311are coupled to the request decoder301via a column bus317.

In one embodiment, incoming symbol streams received via request pads303(i.e., from an external request path) are deserialized in an optional request deserializer304to deliver a corresponding stream of n-bit wide requests to the request decoder301. (Note that, while pads are referred to in a number of embodiments herein, in all such cases, capacitive-coupling nodes or any other interface to an external signaling path may be used.) The incoming requests may include virtually any type of requests including, without limitation, the row activation requests, column access requests and precharge requests discussed above, as well as other requests used, for example, to initiate refresh operations within one or more storage banks, program operating modes within the memory device (e.g., selecting between single-threaded mode and one or more of a number of different micro-threaded modes; and selecting between a number of different refresh modes, power modes, precharge modes, etc.), initiate signaling calibration and/or training operations, initiate self-tests and so forth.

The request decoder301, which may be implemented by one or more state machines, microsequencers and/or other control circuitry, decodes each incoming request (e.g., by parsing a command specifier field or operation code field to identify the request) and issues various signals necessary to carry out the requested operation. For example, upon decoding a row activation request having the bank address and row address fields shown in request207ofFIG. 4, the request decoder301may output the row address and bank address onto the row bus315along with a control value that indicates an activation operation and then, depending on whether the activation request is directed to an even or odd bank (e.g., determined by inspection of the least significant bit (LSB) or other bit or bits of the bank address), assert an even-row strobe signal321A (ERS) or odd-row strobe signal321B (ORS) to load the address and control values from the row bus315into the even-bank row control registers305A,305B or odd-bank row control registers307A,307B. Address and control values loaded into even-bank row control registers305are supplied to the even-bank row decoders for the group A and group B sub-banks (i.e., row decoders1130and1132ofFIG. 2) via signal paths1110and1112, respectively, and address and control values loaded into odd-bank row control registers307are supplied to the odd-bank row decoders for the group A and group B sub-banks via signal paths1110and1113. In one embodiment, the delivery of address and control values via paths111initiates the indicated row operation (e.g., activation or precharge) within the corresponding row decoder so that row operations are effectively initiated in response to assertion of the even-row strobe signal321A and odd row strobe signal321B (i.e., when the corresponding registers305and307are updated). In alternative embodiments, the even-row strobe signal321A and odd-row strobe signal321B (or other control signals derived therefrom or independently generated) may be output to the row decoders to initiate row operations therein.

In one embodiment, the request decoder301responds to incoming column access requests in substantially the same manner as row activation requests, except that bank address and column address values included with the requests are output onto the column address bus317together with a control value that indicates, for example, whether a read or write operation is to be performed. Thereafter, the request decoder301asserts either an even-column strobe signal323A (ECS) or odd-column strobe signal323B (OCS) to load the address and control values from the column address bus317into either the even-bank column control registers309A,309B or odd-bank column control registers311A,311B, thereby initiating the specified column access operation in the corresponding column decoder (i.e., the contents of the column control registers309and311are output to corresponding column decoders via paths109to initiate column access operations therein). As with row requests, the request decoder301may inspect one or more bits of the bank address to determine whether a given column access request is directed to an odd or even bank and assert either the even-column strobe signal323A or odd-column strobe signal323B accordingly. Alternatively, the request decoder301may associate incoming column access requests with previously received row activation requests according to a predetermined protocol so that the bank address received in a row activation request is used to determine the set of banks, even or odd, to which a subsequently received column access request is directed. In such an embodiment, the LSB of the bank address (or other bit(s) used to specify the target set of banks) may be omitted from the column access request to enable other requests or information (e.g., precharge information) to be conveyed therein. In either case, bank and column address values (which may omit the LSB bit or other bit(s) of the bank address used to specify the target set of banks) loaded into even-bank column control registers309are output to the even-bank column decoders for the group A and group B sub-banks, respectively (i.e., column decoders1030and1032ofFIG. 7), and bank and column address values loaded into odd-bank column control registers311are output to the odd-bank column decoders.

FIG. 6illustrates an exemplary timing of row and column strobe signal assertions by the request decoder301ofFIG. 5when the memory device100ofFIG. 2is operating in a single-threaded mode. As shown, upon decoding a row activation request207, the request decoder301asserts either an even-row strobe signal321A (ERS) or an odd-row strobe signal321B (ORS) to load either the even-row control registers305A,305B or the odd row control registers307A,307B, respectively, with the bank address, row address and control information provided in the request207, thereby initiating a row activation operation in either the even or odd bank sets. Although assertion of even row strobe signal321A is shown inFIG. 6, odd row strobe signal321B would be asserted to initiate row activation in an odd bank set. The least significant bit of the bank address may be used to control which of the two strobe signals321A and321B is asserted, and therefore need not be loaded into the selected control register. After a tRRinterval has elapsed, another row activation request directed to a different bank is received, and another strobe signal321A or321B is asserted to initiate a corresponding row activation operation.

Upon decoding a column access request209directed to the row activated in response to row activation command207(i.e., specifying the same bank address as row activation command207), the request decoder asserts either an even-column strobe signal323A (ECS) or odd-column strobe signal323B (OCS) to load either the even-column control registers309A,309B or odd-column control registers311A,311B, respectively, with the bank address, column address and control information provided in the request209, thereby initiating a column access operation (e.g., a read or write operation) within the open page for the specified bank. Although assertion of even column strobe signal323A is shown inFIG. 6, odd column strobe signal323B would be asserted to initiate a column access operation in a transaction directed to a bank in the odd bank set. Again, the least significant bit of the bank address may be used to control which of the two strobe signals323A,323B is asserted to initiate a column access operation. After a tCCinterval has elapsed, another column access request211, directed to the same bank as request209but different column address, is received within the request decoder301. Upon decoding the column access request211, the request decoder asserts either the even-column strobe signal323A or odd-column strobe signal323B to load the corresponding pair of registers309A/309B or311A/311B (i.e., the same pair of registers loaded in response to decoding request209, as both requests are directed to the same open page) and thereby initiate a second column access operation directed to the row activated in response to request207. Thus, a column strobe signal (323A or323B) is asserted once per tCCinterval to enable the specified data transfer to be carried out over the complete tCCinterval and using all the links of the DQ path. That is, when the memory device ofFIG. 2is operated in single-threaded mode, the data transfer in response to a column access request consumes the entire tCCenvelope.

Reflecting on the operation of the request interface300ofFIG. 5, it should be noted that because both the even-row control registers305A,305B are operated in lock step (i.e.,305A and305B are loaded in response to the same strobe signal321A), registers305A and305B may be replaced by a single row control register which, when loaded, initiates the specified row operation (e.g., activation or precharge) in the sub-bank quadrants that form the even bank set (i.e., Q0, Q2). Similarly, the odd-row control register pair307A/307B, even-column control register pair309A/309B and odd-column control register pair311A/311B may each be replaced by a respective single register. Further, if the request interface300did not include support for micro-threaded column operations, the entire register set could be reduced to a single row control register and a single column control register, the control and address information loaded into each register being provided to the row and column decoders in all four quadrants of the memory device100. In such an embodiment, the row and column decoders within each quadrant may determine whether to initiate a row or column operation, for example, based on the least significant bit of the bank address (i.e., if BA[0] is a ‘0’, row/column operations are initiated in the decoders of the even quadrants, Q0/Q2, and if BA[0] is a ‘1’, row/column operations are initiated in the decoders of the odd quadrants, Q1/Q3). When the memory device100is operated in micro-threaded mode, however, the additional row control registers enable temporally overlapping row operations in different regions of memory device100and the additional column control registers enable temporally overlapping column operations in different regions of memory device100. In one embodiment, the different regions in which overlapping operations are performed are the even and odd bank sets of memory device100. In another embodiment, the different regions are the four quadrants of the memory device100. These embodiments and others are discussed in further detail below.

Micro-Threaded Memory Transactions

FIGS. 7 and 8illustrate an exemplary sequence of micro-threaded memory transactions that may be performed in the memory device100ofFIG. 2when operated in a micro-threaded mode at full signaling rate (e.g., data path and request path signaling rates increased to 6.4 Gb/s and 1.6 Gb/s, respectively; doubling the 3.2 Gb/s and 0.8 Gb/s legacy signaling rates described above). Rather than allocating the full tCCenvelope to a single column access (i.e., as in the single-threaded mode described in reference toFIGS. 2-6) and redesigning the memory device100to include double-width internal data path widths, the tCCenvelope is subdivided into sub-envelopes that are allocated to alternating transactions in the odd and even bank sets. That is, recognizing that the tRRconstraint applies to arbitrary bank selection and is imposed primarily to avoid conflicting use of resources shared by banks in the same bank set, (e.g., row decoders shared by even banks and row decoders shared by odd banks), it follows that row activation operations directed alternately to the odd and even bank sets may be executed in sub-intervals within the overall tRRinterval, referred to herein as partial tRRintervals, tRRp. Further, because distinct sets of column decoders and distinct data path resources are provided for the even and odd bank sets, micro-threaded column operations directed to the activated rows in alternate bank sets may be executed one after another within a single tCCinterval referred to herein as partial tCCintervals, tCCp. Through this approach, decoder and data path resources within the memory device100that are used at approximately 50% duty in single-threaded mode (i.e., using either the even-bank resources or the odd-bank resources for a given row or column operation) are used concurrently in the micro-threaded mode to support micro-threaded column access operations. Because the data transferred in each micro-threaded column access operation consumes only a portion of a tCCenvelope, reduced column transaction granularity is achieved relative to the granularity for single-threaded operation at the same signaling rate. Thus, data throughput is effectively doubled without having to double the widths of internal data paths of the memory device, while at the same time reducing column transaction granularity.

Referring to the depiction of memory device100inFIG. 7and the row activation pipeline251A shown inFIG. 8, a first row activation request253initiates activation of bank B0, row ‘z’ (i.e., “Rz” inFIG. 7, “Act B0-Rz” inFIG. 8). One tCCinterval later (i.e., four 1.25 ns request intervals later at the exemplary 1.6 Gb/s request path signaling rate shown), a second activation request255initiates activation of bank B1, row ‘y’ (Act B1-Ry). Note that, while two row activation requests253,255are received within a single tRRinterval, the two requests are directed alternately to even and odd banks (B0and B1in this example) and therefore do not conflict. A predetermined time after receipt of the B0-Rz activation request253, a first micro-threaded column access request257specifying a read at bank B0, column ‘a’ is received (i.e., Rd B0-Ca), as shown in column access pipeline251B. Similarly, a predetermined time after receipt of the B1-Ry activation request255, and before the tCCinterval for the first micro-threaded column access request257has elapsed, a second micro-threaded column access request259specifying a read at bank B1, column ‘e’ is received (Rd B1-Ce). Thus, two micro-threaded column access requests257,259are received within a single tCCinterval and, because the requests are directed alternately to odd and even bank sets, are serviced without conflict. More specifically, as shown at275, read data retrieved from column ‘a’ of sub-banks B0-A and B0-B is delivered to the data interfaces105A and105B for transmission on the DQA and DQB links, respectively, during the first half of the tCCinterval starting at271, and read data retrieved from column ‘e’ of sub-banks B1-A and B1-B is delivered to the data interfaces105A and105B for transmission on the DQA and DQB links during a second half of the same tCCinterval. By this arrangement, the 64-byte tCCenvelope is effectively partitioned between two micro-threaded column access operations each having a 32-byte column transaction granularity, with the data for each micro-threaded column access operation being output onto the DQA and DQB links during a respective tCCpinterval as shown in expanded view272. Additionally, because the tCCenvelope is partitioned between column accesses directed to odd and even bank sets, the data transmitted during either partial tCCinterval may be carried by the existing data path interfaces105A/105B. Accordingly, the internal data path width of the memory device100need not be increased to accommodate the increased data path bandwidth, avoiding the added manufacturing/operating costs and headroom issues discussed above.

Still referring toFIGS. 7 and 8, a tCCinterval after receipt of the first B0-directed micro-threaded column access request257, a second micro-threaded column access request261directed to B0and specifying a read at column ‘b’ is received (i.e., Rd B0-Cb). Similarly, a tCCinterval after receipt of the first B1-directed micro-threaded column access request259, a second B1-directed micro-threaded column access request263specifying a read at column ‘f’ is received (i.e., Rd B1-Cf). The second B0-directed and B1-directed micro-threaded column access requests261,263are serviced in the same manner as the first B0-directed and B1-directed micro-threaded column access requests257,259, resulting in transmission of B0, column ‘b’ data over the first half of the tCCinterval (i.e., first tCCpinterval) that immediately succeeds the transmission of the B1, column ‘e’ data, and transmission of B1, column ‘f’ data over the second half of the tCCinterval. Thus, four micro-threaded column operations are executed, resulting in four 32-byte data transfers over a single tRRinterval starting at271. As each row activation yields two 32-byte column data transfers, each within a respective tRRpinterval as shown at274, the row transaction granularity is 64 bytes, half the 128-byte data transfer capacity of the data path over the tRRinterval (i.e., half the 128-byte tRRenvelope).

Precharge requests265and267directed to banks B0and B1are received in the request interface101a predetermined time after receipt of the micro-threaded column access requests261and263directed to the same banks (i.e., as shown in precharge pipeline251C). The precharge requests265,267are serviced in the manner discussed above to close the open pages in the specified banks.

FIG. 9illustrates an exemplary timing of row and column strobe signal assertions by the request decoder301ofFIG. 5when in a micro-threaded mode. As shown, upon decoding a row activation request253directed to an even bank, the request decoder301asserts the even-row strobe signal321A to load even-row control registers305A,305B and thereby deliver bank and address values to the row decoders for the even banks. After a partial tRRinterval (tRRp) has elapsed, a row activation request255directed to an odd bank is received. Upon decoding the odd-bank row activation request255, the request decoder301asserts the odd-row strobe signal321B to load odd-bank row control registers307A,307B and thereby deliver bank and row address values to the row decoders for the odd banks. Thus, assuming a fully loaded row activation pipeline, the request decoder alternately asserts the even-row and odd-row strobe signals321A,321B after each tRRpinterval to deliver bank and row address values alternately to the row decoders for the odd and even bank sets.

Still referring toFIG. 9, upon decoding a column access request257(i.e., a micro-threaded column access request) directed to an even bank, the request decoder301asserts the even-column strobe signal323A to load even-bank column control registers309A,309B and thereby deliver bank and column address values to the column decoders for the even banks. After a partial tCCinterval (tCCp) has elapsed, a column access request259directed to an odd bank is received. Upon decoding the odd-bank column access request259, the request decoder301asserts the odd-column strobe signal323B to load odd-bank column control registers311A,311B and thereby deliver bank and column address values to the column decoders for the odd banks. Thus, assuming a fully loaded column access pipeline, the request decoder301alternately asserts the ECS and OCS signals after each tCCpinterval to deliver bank and column address values alternately to the column decoders for the odd and even bank sets. As shown inFIG. 8, the alternating assertion of the ECS and OCS signals enables a time-staggered transfer of column data for multiple micro-threaded column access operations within a single tCCinterval. The ECS and OCS signals are asserted by the request decoder301during a second tCCinterval in response to column access requests261and263, respectively, thereby enabling the time staggered data transfer to be repeated during a subsequent tCCinterval as shown inFIG. 8.

FIG. 10illustrates exemplary link-staggered micro-threaded memory transactions that may be performed in an alternative embodiment of the memory device100ofFIG. 2. Row activation requests253and255, micro-threaded column access requests257,259,261and263, and precharge requests265and267are received in the request interface101and processed in generally the same manner as discussed above in reference toFIGS. 7-9. However, instead of subdividing the tCCenvelope temporally (i.e., time-staggering the column data output in response to micro-threaded column access requests received in the same tCCinterval), the tCCenvelope is subdivided spatially through concurrent data transfer of the column data for same-tCC-interval micro-threaded column access requests on different portions of the DQA and DQB data paths as shown at375; an operation referred herein to as link staggering. That is, the column data transferred in response to micro-threaded column access request257is transmitted via a first subset of the DQA links and a first subset of the DQB links (e.g., DQA[3:0] and DQB[3:0], while column data transferred in response to micro-threaded column access request259is concurrently (i.e., partly or completely overlapping in time) transmitted via a second subset of the DQA lines and a second subset of the DQB links (e.g., DQA[7:4] and DQB[7:4]). Similarly, the column data transferred in response to micro-threaded column access requests261and263is transmitted during a subsequent tCCinterval over the first and second subsets of DQ links, respectively. The tCCenvelope remains at 64 bytes, with the column transaction granularity and row transaction granularity being 32 bytes and 64 bytes, respectively, as in the temporally-staggered embodiment ofFIG. 8. Thus, the link-staggered approach provides effectively the same benefits as the temporally-staggered approach in terms of reduced row and column transaction granularity, but does so by allocating respective portions of the DQ paths to service the micro-threaded column access requests, instead of respective portions of the tCCinterval.

FIGS. 12A and 12Billustrate exemplary data path interfaces401and411that may be used to support the time-staggered and link staggered data transfers shown inFIGS. 8 and 10, respectively. The data path interface401ofFIG. 12Acorresponds generally to the data path interface105A described in reference toFIG. 3and includes DQA pads171and a pair of transceivers403and405coupled between the pads171and respective column data paths1190and1191. Each transceiver403,405includes a data serializer177and transmitter175to generate an output data stream, and a receiver179and data deserializer181to receive an incoming data stream. More specifically, in the exemplary embodiment shown, the data serializer177converts 128-bit column data values received via the column data path119into a sequence of sixteen 8-bit values (e.g., picking off one byte at a time in round-robin fashion from each of sixteen different offsets within the 128-bit column data) which are delivered to the transmitter175for transmission in respective transmission intervals via the DQA pads171. Conversely, a sequence of sixteen 8-bit values recovered by the receiver179are delivered to the data deserializer181which gathers the values into a 128-bit column data value that is provided to the column decoder via column data path119. In the time-staggered data transfer operation illustrated inFIG. 8, the data transfer path through transceiver403is used during a first partial tCCinterval, and the data transfer path through transceiver405is used during the second partial tCCinterval, as indicated by arrows408A and408B which are shaded to correspond to the column access transactions ofFIG. 8.

In the data path interface411ofFIG. 12B, the eight links of the DQA path are subdivided into two groups of four links, DQA[3:0] and DQA[7:4], and used to transfer data for respective micro-threaded column transactions. Accordingly, a first pair of transceivers413A/415A is coupled to a first set of four DQA pads171A and a second pair of transceivers413B/415B is coupled to a second set of four DQA pads171B, with each individual transceiver including an output data path formed by a data serializer427and transmitter425, and an input data path formed by a receiver429and data deserializer431. As each 128-bit column data value is transferred over half the number of signal links (e.g., four instead of eight), the data serializer is a 1:32 data serializer (i.e., converting the 128-bit column data value into a sequence of thirty-two 4-bit data values) instead of the 1:16 data serializer ofFIG. 12A, and the data deserializer is a 32:1 data deserializer (gathering a sequence of thirty-two 4-bit values into a 128-bit column data value) instead of the 16:1 data deserializer181ofFIG. 12A. Thus, each transceiver413A,415A,413B,415B transfers a 128-bit column data between a column data path119and a smaller number of DQ links, but over twice the interval (i.e., over a full tCCinterval rather than a half tCCinterval).

As in the embodiment ofFIG. 12A, the micro-threaded column transactions serviced in the same tCCinterval are directed alternately to odd and even banks so that one set of four data path links is fed by data from (or feeds data to) one of the column data paths1190and1191over a given tCCinterval, and the other set of four data path links is concurrently fed by data from (or feeds data to) the other of the column data paths1190and1191during the tCCinterval. This data flow arrangement is shown, for example by arrows418A and418B which are shaded to correspond to the column access transactions ofFIG. 10.

ComparingFIGS. 12A and 12B, it can be seen that the data path interfaces401and411differ primarily in the operation of the data serializer and data deserializer circuits. That is, the two four-link transmitters425in transceivers413A and413B may be implemented and connected to the eight DQA pads (i.e.,171A and171B) so as to be equivalent to the single eight-link transmitter175in transceiver403, and the two four-link receivers429in transceivers413A and413B may likewise be equivalent to the eight-link receiver179in transceiver403. The 1:16 data serializers177in transceivers403and405differ from the 1:32 data serializers427in transceivers413A,413B,415A and415B primarily by the manner in which incoming 128-bit column data is distributed to the DQA data pads; data deserializer177delivering 8-bit chunks of the 128-bit column data to eight DQA pads over16transmission intervals and, data deserializer427delivering 4-bit chunks of the 128-bit column data to four DQA pads over32transmission intervals. The 16:1 data deserializers and 32:1 data deserializers are similarly different in the manner of data distribution from DQA pads to column data values. Thus, in one embodiment, the data path interfaces401and411are implemented by a single data path interface circuit having data serializer and data deserializer circuits that are configurable (e.g., through mode register programming) to support either link-staggered or time-staggered data transfer in response to micro-threaded column access requests.

Referring toFIGS. 10 and 12B, it should be noted that, because column data retrieved in response to micro-threaded column access request257will become available for transfer before column data retrieved in response to micro-threaded column access request259, the first-retrieved column data may be buffered (e.g., within the data path interface411) until the second-retrieved column data is available, thereby enabling simultaneous (i.e., fully concurrent) transfer of the column data for the two access requests. Alternatively, as shown inFIG. 11, the first-retrieved column data (i.e., retrieved in response to request257) may be output as soon as it becomes available, thus resulting in a time-staggering of the same-row transmissions on the upper and lower partitions of the data path as shown at385, with transfer of the second-retrieved column data being delayed relative to transfer of the first-retrieved column data by a partial tCCinterval (i.e., tCCp). The transmissions over the signal path partitions are thus partially overlapped (but still concurrent over a partial tCCinterval). Such an approach may be desirable in some applications, as no buffering of column data is required and a single, deterministic memory access latency applies to each micro-threaded column access. By contrast, if column data retrieved in response to a first micro-threaded column access request is buffered to enable simultaneous, link-staggered transfer with column data retrieved in response to a second micro-threaded column access request, the two micro-threaded column access requests may have different, though still deterministic, memory access latencies.

FIGS. 13 and 14illustrate an exemplary sequence of micro-threaded memory transactions that may be performed in the memory device100ofFIG. 2when operated in an alternative micro-threaded mode at full signaling rate (e.g., data and request bandwidth doubled over the legacy 3.2 Gb/s and 0.8 Gb/s signaling rates described above). In the alternative micro-threaded mode, referred to herein as a sub-bank micro-threaded mode, the number of micro-threaded column transactions per tCCenvelope is doubled relative to the micro-threaded mode ofFIGS. 7 and 8by increasing the number of column addresses provided in each column access request, and by applying the pairs of column addresses delivered in each column access request to different sub-banks of the same bank. Referring to the row activation pipeline461A, column access pipeline461B and precharge pipeline461C shown inFIG. 14, for example, a sequence of row activation requests253,255is received as inFIG. 8(i.e., with the pair of requests received within each tRRinterval being directed alternately to even and odd banks), and a sequence of micro-threaded column access requests467,469,471,473are also received as inFIG. 8, but with each access request including a bank address and two column addresses as shown at480. By applying the two column addresses against alternating sub-banks of a specified even or odd bank (i.e., sub-bank micro-threading), two distinct 16-byte column data values may be retrieved per micro-threaded column access, thus achieving 16-byte column transaction granularity. In the particular example ofFIGS. 13 and 14, for instance, a first micro-threaded column access request467specifies a read at column ‘a’ of sub-bank B0-A and a read at column ‘c’ of sub-bank B0-B (i.e., Rd B0-Ca/Cc), while a second micro-threaded column access469received within the same tCCinterval specifies read at column ‘e’ of sub-bank B1-A and a read at column ‘g’ of sub-bank B1-B (Rd B1-Ce/Cg). In a subsequent tCCinterval, two additional micro-threaded column access requests471and473are received, the first specifying a read at columns ‘b’ and ‘d’ of the B0-A and B0-B sub-banks (Rd B0-Cb/Cd), and the second specifying a read at columns ‘f’, and ‘h’ of the B1-A and B1-B sub-banks (Rd B1-Cf/Ch). As shown at275, the tCCenvelope is temporally subdivided between successive tCCpintervals and spatially subdivided between DQA and DQB data path links to accommodate the four column data transfers that correspond to the four column addresses received in each pair of micro-threaded column access requests. Thus, through sub-bank micro-threading, the column transaction granularity is reduced to 16 bytes without reduction in the aggregate amount of transferred data (i.e., peak bandwidth of the memory device is maintained). The row transaction granularity remains at 64 bytes as four 16-byte column data transfers are performed per activated row.

FIG. 15illustrates an embodiment of a request interface500that may be used within the memory device100ofFIG. 2(i.e., to implement request interface101) to enable the micro-threaded memory transactions described in reference toFIGS. 13 and 14. As in the embodiment ofFIG. 5, the request interface500includes a request decoder501to process an incoming stream of requests (i.e., received via pads303and deserialized, if necessary, by optional request deserializer304), even-bank row control registers305A,305B, odd-bank row control registers307A,307B, even-bank column control registers309A,309B and odd-bank column control registers311A,311B. The request interface500also includes a row bus315coupled between the request decoder501and the even- and odd-bank row control registers305,307, a first column bus503A coupled between the request decoder501and the even-bank column control registers309and a second column bus503B coupled between the request decoder501and the odd-bank column control registers311.

Upon decoding a row activation request, the request decoder501outputs the row address and bank address onto the row bus315and, as discussed in reference toFIG. 5, asserts either an even-row strobe signal321A or odd-row strobe signal321B (i.e., depending on whether the request is directed to an even bank or odd bank) to load the bank and row address values into either the even-bank row control registers305or odd-bank row control registers307. Upon decoding a micro-threaded column access request having a bank address and two column addresses (i.e., a sub-bank micro-threaded column access), the request decoder501outputs the first and second column addresses on the first and second column buses503A and503B, respectively, then asserts either an even-column strobe signal323A or odd-column strobe signal323B (i.e., depending on whether the request is directed to an even bank or odd bank) to load the first column address into either the even-bank or odd-bank column control register (305A or307A) for the group A sub-banks (i.e., referring toFIG. 13, the sub-banks in quadrants Q0and Q1), and to load the second column address into the corresponding even-bank or odd-bank column control register (305B or307B) for the group B sub-banks (i.e., sub-banks in quadrants Q2an Q3). In one embodiment, the bank address value received in the sub-banked micro-threaded column access request is output onto both the first and second column buses503A and503B and loaded, along with the first and second column addresses, into either the even-bank or odd-bank column control registers309or311in response to assertion of the even-column load or odd-column strobe signals323A,323B. In an alternative embodiment, a separate bank address bus may be provided and coupled in common to the even and odd-bank column control registers309and311(and to the request decoder501) to enable a bank address supplied thereon to be loaded into bank address fields within those registers (or into separate bank address registers). Also, in another embodiment, a single column bus is coupled to all the column control registers309,311and time-multiplexed to load the first column address into one of column control registers309A and311A, and the second column address into one of column control registers309B and309B in respective address transfer operations. In such an embodiment, distinct strobe signals may be provided to each of the four column control registers309A,309B,311A,311B to enable one column control register to be loaded at a time. Also, in all such embodiments, the two column addresses may be independently specified by the incoming micro-threaded column access request, or may be specified in relation to one another. For example, one of the two addresses may be specified as an arithmetic or logical offset from the other. The offset value may be specified in the column access request, or the column access request may include a value that is used indirectly to determine the offset value, for example, by indexing a lookup table of offset values.

In the embodiment ofFIG. 15, the request decoder501may assert the register strobe signals321A,321B,323A and323B at the times shown inFIG. 9, thereby enabling the two column addresses received in each sub-bank micro-threaded column access request to be applied concurrently within each tCCpinterval (i.e., simultaneously or at least partly overlapping in time) to retrieve respective sets of data from different columns of the same bank. In an embodiment having a shared, time-multiplexed column bus, four column strobe signals (e.g., ECS1, ECS2, OCS1, OCS2) may be asserted in succession to enable two column control register load operations per tCCpinterval. For example signals ECS1and ECS2may be asserted one after another during a first tCCpinterval, and OCS1and OCS2asserted one after another during a second tCCpinterval.

FIGS. 16 and 17illustrate exemplary micro-threaded memory operations in which separate row and column addresses are used to access sub-banks in each of the four quadrants, Q0-Q3, of a memory device530within a single tCCinterval. More precisely, because the request interface531of memory device530delivers unique bank, row and column addresses to the address decoders (i.e., column decoders103and row decoders113) for each quadrant, the storage arrays in each quadrant are effectively converted from sub-banks to banks, thereby yielding a sixteen bank architecture having banks B0-B15as shown inFIG. 16. As in the other memory device embodiments discussed above, memory device530may have more or fewer storage arrays in alternative embodiments, yielding correspondingly more or fewer banks. Also, any of the sixteen banks may include two or more constituent sub-banks.

Referring toFIGS. 16 and 17, the row activation pipeline551A is more densely loaded than in previously described embodiments to deliver row activation requests553,555,557and559directed to banks within each of the four quadrants of the memory device530in a single tRRinterval. That is, the tRRinterval is sub-divided into four tRRpintervals, with a row activation request being received in each. In the specific example shown inFIGS. 16 and 17, rows ‘w’, ‘x’, ‘y’ and ‘z’ are activated one after another in banks B0, B8, B9and B1, respectively (i.e., Act B0-Rw, Act B8-Rx, Act B9-Ry and Act B1-Rz), though rows may be activated in each of the four quadrants in different order in subsequent transactions or in alternative embodiments.

Referring to column access pipeline551B, a predetermined time after the first row activation request553is received, a pair of dual-address micro-threaded column access requests561,563are received over a first tCCinterval550, thereby delivering four bank addresses and four column addresses that may be applied against pages opened in the four quadrants in response to activation requests553,555,557and559. In the particular example shown, the first dual-address micro-threaded column access request561includes a first pair of addresses, Bank Addr1 and Col Addr1 as shown at577, that specify an access at column ‘a’ of bank B0(i.e., in the open page thereof), and a second pair of addresses, Bank Addr2 and Col Addr2, that specify an access at column ‘b’ of bank B8(i.e., Rd B0-Ca/B8-Cb). The second dual-address micro-threaded column access request563specifies an access at column ‘c’ of bank B1and column ‘d’ of bank B9(Rd B1-Cc/B9-Cd). Because each of the four bank addresses provided in the pair of access requests561and563and specifies a bank in a different quadrant of the memory device530, no column decoder or data path conflict arises in servicing the requests. Accordingly, a predetermined time after receipt of the four address values in the pair of access requests561and563, four corresponding sets of column data are transmitted via the data path over a tCCinterval that begins at577. As shown at575, the four sets of column data are transmitted in both link-staggered manner (i.e., two sets of data transferred on the DQA links and two sets transferred on the DQB links) and time-staggered manner (the column data corresponding to the first and access requests561and563being transferred in first and second tCCpintervals, respectively) within the 64-byte tCCenvelope, with each set of column data having a 16 byte column transaction granularity.

Still referring toFIGS. 16 and 17, a second pair of dual-address micro-threaded column access requests565and567are received in the tCCinterval that immediately follows interval550. As in the first pair of access requests561and563, the four bank addresses carried within the second pair of access requests specify accesses at selected columns of the previously activated rows of banks in each of the four quadrants of the memory device530(e.g., Rd B0-Ce/B8-Cf and Rd B1-Cg/B9-Ch). Accordingly, a predetermined time after receipt of the four address values in the second pair of micro-threaded column access requests565and567, four corresponding sets of column data are transmitted via the data path. The four sets of column data are transmitted link-staggered and time-staggered within the 64-byte tCCenvelope, with each set of column data having a 16 byte column transaction granularity. The tRRenvelope remains at 128 bytes (i.e., twice the tCCenvelope as tRR=2tCCin this example), but, due to the four-way partitioning of the tRRinterval, the row transaction granularity is reduced to 32 bytes.

Still referring toFIG. 17, the increased request density in row activation pipeline551A may eliminate request intervals otherwise used to issue precharge requests. In one embodiment, precharge requests that would otherwise be transmitted during the intervals shown at581and583of a precharge request pipeline551C, are instead handled by a sub-field within column access requests. For example, as shown in at577and579, a precharge bit (or bits) may be included with each column access request to indicate whether a precharge operation is to be automatically performed upon conclusion of the requested access. Thus, in access request561, the precharge bit is reset (e.g., “Prechg=0” as shown at577) to defer the precharge operation, leaving the pages of the specified banks (B0and B8) open for one or more subsequent column accesses. In access request567, the precharge bit is set (e.g., “Prechg=1” as shown at579), thereby instructing the memory device530to perform precharge operations in the specified banks (B1and B9) at the conclusion of the specified column accesses.

FIG. 18illustrates an embodiment of a request interface600that may be used to implement request interface531within the memory device530ofFIG. 16and to support the four-way micro-threaded transactions described in reference toFIG. 17. As in the embodiment ofFIGS. 5 and 15, the request interface600includes a request decoder601to process an incoming stream of requests (i.e., received via pads303and deserialized, if necessary, by optional data deserializer304), even-bank row control registers305A,305B, odd-bank row control registers307A,307B, even-bank column control registers309A,309B and odd-bank column control registers311A,311B. The request interface600also includes a row bus315coupled between the request decoder601and the even-bank and odd-bank row control registers305,307and, as in the embodiment ofFIG. 15, first and second column buses503A and503B coupled to the even-bank column control registers109and odd-bank column control registers11, respectively.

Upon decoding a row activation request, the request decoder601outputs the row address and bank address onto the row bus315, then asserts one of four row-register strobe signals605A,605B,607A or607B (ERSA, ERSB, ORSA, ORSB) according to the quadrant specified in the least two significant bits (or other bits) of the bank address; an address field referred to herein as the quadrant address. Assuming, for example, that incoming stream of activation requests is directed in round-robin fashion to quadrants Q0, Q2, Q1and Q4of theFIG. 16memory device530, then the row-register strobe signals605A,605B,607A and607B are asserted one after another in respective tRRpintervals. Other quadrant address sequences may be used in alternative embodiments, resulting in a different sequence of row-register strobe signal assertions.

Upon decoding a dual-address micro-threaded column access (e.g., request561ofFIG. 17), the request decoder601outputs the first bank address and column address values therein onto the first column bus503A and the second bank address and column address values therein (BA2, CA2) onto the second column bus503B, then asserts either an even-column strobe signal323A (ECS) or odd-column strobe signal323B (OCS) according to whether the pair of addressed banks are odd or even. In alternative embodiments, to avoid restrictions on the pair of banks addressed in a given multi-threaded column access request (e.g., enabling a column access directed to an odd bank to be paired with a column access directed to an even bank), separate column strobe signals and column address buses may be provided to each of the column control registers309A,309B,311A and311B, with any pair of the column strobe signals asserted to enable the corresponding column control registers to be simultaneously loaded. Also, as discussed above in reference toFIG. 15, a single time-multiplexed column bus may be coupled to all the column control registers309,311to enable sequential loading of selected column control registers in any order.

FIG. 19illustrates an exemplary timing of control signal assertions by the request decoder601ofFIG. 18. In the particular example shown, row activation requests553,555,557and559are received in respective tRRpintervals, with each request being directed to a different quadrant in the exemplary order described in reference to sequence ofFIGS. 16 and 17(other row activation orders may be used). Thus, the request decoder601asserts the four row-register strobe signals ERSA, ERSB, ORSA, ORSB in respective tRRpintervals, as shown, to transfer the bank and row address values received in the four activation requests to the address-specified row registers305,307. Assuming that the same pattern of row activation requests is received in subsequent tRRintervals (i.e., same quadrant ordering, but arbitrary intra-quadrant bank address and row address), each of the four row-register strobe signals ERSA, ERSB, ORSA, ORSB may be asserted once per tRRinterval in round-robin fashion.

Still referring toFIG. 19, column strobe signals ECS and OCS are asserted on partial tCCintervals (i.e., tCCp) as in the embodiment ofFIG. 9. As discussed, if the request decoder supports an arbitrary column control register loading sequence, four distinct column strobe signals may be generated by the request decoder and asserted in respective tCCpintervals in any order. If the incoming column access requests specify the same quadrant access order in each tRRcycle (or any group of tRRcycles), each of the column strobe signals may be asserted in round-robin fashion once per tRRinterval or, in the case of the shared column strobe signals (ECS and OCS) shown inFIGS. 18 and 19, once per tCCinterval.

FIGS. 20A and 20Billustrate exemplary row requests that may be issued to the memory devices100and530described above to initiate row operations (e.g., row activation operations and precharge operations). More specifically,FIG. 20Aillustrates an exemplary ST-mode (single-threaded mode) row request that is issued when the memory devices100,530are operated in a single-threaded mode, andFIG. 20Billustrates an exemplary MT-mode (micro-threaded-mode) row request issued when the memory devices are operated in a micro-threaded mode. In the particular embodiment shown, each row request is issued in two successive transfers (e.g., during odd and even phases of a clock signal or other timing signal) over a 12 bit request path (RQ0-RQ11) and therefore includes 24 bits. As shown, the ST-mode request includes a three-bit opcode formed by bits “OP,” a three-bit bank address, BA0-BA2, and an eleven-bit row address, R0-R10. The opcode indicates the type of row operation to be performed (e.g., row activation or precharge), the bank address indicates which of the eight banks the row operation is directed to, and the row address indicates, at least in the case of a row activation operation, the row of the selected bank in which the operation is to be performed. The remaining seven bits of the ST-mode row request may be reserved (i.e., as indicated by the designation “rsrv”) or used to carry information for controlling other functions within the memory device. The MT-mode row request ofFIG. 20Bis substantially the same as the ST-mode row request, except that one of the reserved bits in the ST-mode request (e.g., the even phase bit transferred on request link RQ3) is optionally used to carry an additional bank address bit, BA3, thereby enabling selection of one of one of sixteen banks within the 16-bank memory device530ofFIG. 16. In alternative embodiments, row requests ofFIGS. 20A and 20Bmay have different formats, different numbers of bits and may be transmitted in more or fewer transfers over a wider or narrower request path.

FIGS. 21A and 21Billustrate exemplary column requests that may be issued to the memory devices100and530described above to initiate column access operations (e.g., read operations and write operations). More specifically,FIG. 21A, illustrates an exemplary ST-mode (single-threaded mode) column request that is issued when the memory devices100,530are operated in a single-threaded mode, andFIG. 21Billustrates an exemplary MT-mode (micro-threaded mode) column request issued when the memory devices are operated in a micro-threaded mode. In the embodiments shown, the ST-mode and MT-mode column requests are the same size as the corresponding ST-mode and MT-mode row requests (i.e., 24-bit requests formed by odd and even phase transfers over the 12 bit request path, RQ0-RQ11), but may be larger or smaller than the row requests in alternative embodiments. The ST-mode column request includes a five-bit opcode to specify the type of column access to be performed (e.g., read, write, masked write, etc.), a three-bit bank address, BC0-BC2, to specify one of eight open pages to be accessed (i.e., an open page for one of the eight banks), and a 6-bit column address, C4-C9, to specify one of 64 column locations (also called column offsets) within the open page at which the specified column access operation is to be performed. Ten bits of the ST-mode column access request are reserved or allocated to other functions.

The MT-mode column request is similar to the ST-mode column access request except that the reserved bits of the ST-mode column access request are used to carry a second bank address BCy0-BCy2and a second column address, Cy4-Cy9, the first bank address and first column address being carried in the same bits as the bank address and column address of the ST-mode column request, but designated BCx0-BCx2and Cx4-Cx9. By this arrangement, each column request may carry the two distinct bank and column addresses used in the sixteen-bank memory device described in reference toFIGS. 16-19. In alternative embodiments, a second column address, but not a second bank address may be provided in the MT-mode column request (e.g., as in the embodiments described in reference toFIGS. 13-15) and in other alternative embodiments, a single column address and single bank address are provided per column access request (e.g., as in the embodiments described in reference toFIGS. 7-9). Also, in the embodiment described in reference toFIG. 17, the higher density of row activation commands in the row activation pipeline consumes the request path bandwidth that might otherwise be used to transfer precharge commands. Accordingly, in the exemplary MT-mode column request ofFIG. 21A, one bit (i.e., odd phase bit transferred over the RQ11link) is used to indicate whether an auto-precharge operation (AP) is to be performed at the conclusion of the indicated column access operation. In alternative embodiments, the ST-mode and/or MT-mode column requests may have different formats, different numbers of bits and may be transmitted in more or fewer transfers over a wider or narrower request path.

FIGS. 22 and 23illustrate exemplary micro-threaded memory operations in a memory device700having a request interface701and data path interface705A,705B to interface with legacy request and data paths. Referring toFIG. 23, the request interface receives row and column requests (including address components thereof) via a 19-bit request path730formed by a reset line (RESET), chip-select line (CS), row-address-strobe line (RAS), column-address-strobe line (CAS), write-enable line (WE), three bank address lines (BA[2:0]) and eleven address lines (A[10:0]). The data path interface is coupled to an external data path732formed by 32 data lines (DQ), four data-mask lines (DM), four read data strobe lines (RDQS), and four write data strobe lines (WDQS). The data-mask lines are used to carry respective mask bits during masked-write operations, with each mask bit indicating whether a corresponding byte carried on the DQ lines is to be written or not. The read data strobe lines carry read data strobe signals output from the memory device to time reception of corresponding read data in the memory controller or other control device. The write data strobe lines carry write data strobe signals output from the memory controller (or other control device) to time reception of write data within the memory device700. Each of the signal lines in the request path730and/or data path732may be single-ended or differential. Also, in alternative embodiments, different numbers and types of signals may be conducted via the request path730and/or data path732.

In the embodiment ofFIG. 22, memory device700has substantially the same architecture as memory device100ofFIG. 1. That is, the memory device700has four quadrants, Q0-Q3, eight banks B0-B7(each formed by a pair of A and B sub-banks), together with column decoders7030-7033and row decoders7130-7133that correspond to the column decoders1030-1033and row decoders1130-1133ofFIG. 1, though the banks may have different width and/or depth dimensions and the column and row decoders correspondingly revised to accommodate the differently-dimensioned banks. Also, signal paths7090-7093,7110-7113,7150-7153,7170-7173and7190-7193correspond to the signal paths1090-1093,1110-1113,1150-1153,1170-1173and1190-1193ofFIG. 1, though such signal paths may include different numbers of signal lines as necessary to accommodate the different bank dimensions. Further, as with the memory device100, memory device700is assumed for purpose of description to be a DRAM device, but may be any type of memory device having multiple storage arrays that share addressing and/or data path resources in a manner that imposes timing constraints on sequential accesses directed to the different storage arrays. Also, the memory device700may have a different number of banks, sub-banks per bank and/or number of sub-banks per decoder-sharing group in alternative embodiments.

Turning toFIG. 23, a row activation pipeline731A, column access pipeline731B, and precharge pipeline731C illustrate an exemplary sequence of row activation requests, column access requests and precharge requests received in the request interface701via request path730. Referring first to row activation pipeline731A, a pair of row activation requests directed alternately to even and odd banks of the memory device700, are received in each tRRinterval, starting with row activation requests733and735. The request interface701responds to each pair of row activation requests by initiating row activation operations in the corresponding banks of the memory device700.

A predetermined time after receipt of the row activation requests733and735, a sequence of four multi-address, micro-threaded column access requests737,739,741and743are received, each pair of the column access requests being-received in a respective tCCinterval and each individual column access request received within a given tCCinterval being directed the open page for the bank specified in a respective one of row activation requests733and755. Referring toFIGS. 22 and 23, for example, column access request737is directed to the open page of bank B0(opened in response to row activation request733) and specifies accesses therein at column addresses ‘a’ and ‘c.’ Column access request739, received in the same tCCinterval as column access request737, is directed to the open page of bank B1(opened in response to row activation request735) and specifies accesses therein at column addresses ‘e’ and ‘g.’ Column access requests741and743are received in a second tCCinterval, with column access request741directed to columns ‘b’ and ‘d’ of the open page of bank B0, and column access request743directed to columns ‘f’ and ‘h’ of the open page of bank B1. The open pages are closed in precharge operations requested in precharge requests745and747. In the particular embodiment shown, each request interval is 1 ns (i.e., requests are transferred over the individual signal lines of path730at 1 Gb/s), so that an 8 ns tRRconstraint and a 4 ns tCCconstraint are assumed. Also, the tRCconstraint is assumed to be 40 ns, so that activation requests directed to the rows specified in requests733and735are not issued again until after a 40 nS interval has elapsed. Other request transfer rates may be used and different tRR, tCCand/or tRCconstraints may apply in alternative embodiments.

The request decoder responds to the incoming column access requests737,739,741and743by issuing signals to the appropriate column decoders to perform the access operations (e.g., read or write operations), with data that corresponds to each column access being transferred via DQ links DQ[31:0] over a respective partial tCCinterval (tCCp). More specifically, as shown in detail view738, each tCCenvelope is spatially and temporally subdivided so that, over the tCCpinterval starting at736, data that corresponds to column ‘a’ of column access request737(i.e., data being written to column ‘a’ or read from column ‘a’) is transferred via a first portion of the DQ links, DQ[31:16], and data that corresponds to column ‘c’ of column access request737is transferred via a second portion of the DQ links, DQ[15:0]. Similarly, during the next tCCpinterval, data that corresponds to columns ‘e’ and ‘g’ of column access request739is transferred via DQ links, DQ[31:16] and DQ[15:0], respectively. Thus, over the tCCinterval starting at736, data transfers that correspond to four different micro-threaded column access transactions are carried out. In the exemplary embodiment shown, data is transferred over each of the DQ links at 2 Gb/s, so that four bits per link are transferred over each 2 ns tCCpinterval. Consequently, an8-byte column transaction granularity is achieved in a device otherwise having a 32-byte tCCenvelope. During the tCCinterval that follows the Ce/Cg data transfer, four additional data transfers are carried out in response to the micro-threaded column access requests specified in requests741and743. That is, during a first tCCpinterval, data that corresponds to columns ‘b’ and ‘d’ of column access request741is transferred via DQ links DQ[31:16] and DQ[15:0], respectively, and during the next tCCpinterval, data that corresponds to columns ‘f’ and ‘h’ of column access request743is transferred via DQ links DQ[31:16] and DQ[15:0], respectively. Thus, the total amount of data transferred over the tRRinterval starting at736is 64 bytes, with one half of the total tRRenvelope being allocated to data transfer for each of the rows activated in response to row activation requests733and735. That is, the 64-byte tRRenvelope is temporally subdivided between the rows activated in response to requests733and735to achieve a 32-byte row transaction granularity.

Depending on the number of bits required to specify a column address within the memory device ofFIG. 23, the 19-bit request size (i.e., established by the width of request path730) may be insufficient to carry two complete column addresses. In one embodiment, this circumstance is overcome by storing a set of offset values within the memory device700and including an offset select value within incoming multi-address column access requests to select one of the pre-stored offset values. The selected offset value may then be used directly as the second column address or may be combined with a fully specified column address to form a relative column address. For example, in the exemplary format shown at740, column access request737includes an operation specifier, “Col Cmd,” that specifies the type of column access (e.g., read, write, masked write, etc.); a bank address, “Bank Addr,” that specifies the bank to which the column access is directed; a fully-specified column address, “Col Addr1,” that specifies a first column address (e.g., column ‘a’ in request737); and an offset select value, “OSEL,” that specifies a pre-stored offset value to be summed (or otherwise arithmetically or logically combined) with the fully-specified column address to produce the second column address. That is, as shown at742, the offset select value may be applied to the control input of a multiplexer744to select one of n offset values, Coff0-Coff(n−1), to be summed with column address, Ca, in adder746, thereby producing the second column address, Cc.

FIG. 24illustrates a more detailed example of address information provided, via lines BA[2:0] and A[10:0] of request path730, as part of a column access request. The BA[2:0] lines carry a three-bit bank address specifying one of eight banks, while address lines A9and A7-A2carry a fully-specified, seven-bit column address, “Col Addr1.” Address lines A1and A-0carry a two-bit offset select value which is applied to select one of four column addresses, Coff0-Coff3to be added to the fully-specified column address. The resulting relative column address constitutes the second column address, “Col Addr2,” specified in the column access request. The signal carried on address line A8indicates whether a normal precharge or auto-precharge is to be carried out (e.g., the auto-precharge occurring at the conclusion of the specified column access operation), and the signal carried on address line A10is reserved. Different signal encodings on the bank address lines and address lines or other lines of the request path may be used in alternative embodiments. Also, more or fewer column offsets may be stored to enable a larger selection of column offset values. For example, bit A10may be used to carry the most significant bit of an offset select value, thereby enabling selection of one of eight column offset values.

FIG. 25illustrates exemplary configuration information that may be provided in conjunction with a load mode register command issued to the memory device700ofFIG. 22. The load mode register command may be specified, for example, by driving the CS, RAS, CAS, and WE lines of the request path low during a request interval. As shown, the signals carried on lines BA[2:0] indicate the nature of the operation to be performed, with ‘000’ and ‘001’ codes indicating that bits A[10:0] (i.e., the signals carried on lines A[10:0]) are to be loaded into a device mode register or extended mode register, respectively, (e.g., to program device output latency, burst length and/or other device operating characteristics), codes ‘010-110’ being reserved or used for other functions, and code ‘111’ indicating that bits A[10:0] are to be loaded into a micro-thread mode register (i.e., uMode register). In a load to the micro-thread mode register, bits A9and A7-A2form a column offset value to be loaded into one of four column offset fields of the micro-thread mode register, and bits A1and A0indicate which of the four column offset fields, Coff0-Coff3, is to be loaded. Bits A8and A10are coded to one of four values (00, 01, 10, 11) to specify either a single-threaded mode (ST) within the memory device; a two-by-two micro-threaded mode (MT2×2) in which a single column address is provided in each micro-threaded column access request to enable two-way partitioning of the tCCenvelope and with the micro-threaded column accesses in each tRRinterval directed to two different banks(e.g., to enable micro-threading as described in reference toFIGS. 7-9); a four-by-two micro-threaded mode (MT4×2) in which two column address are provided in each micro-threaded column access request to enable four-way partitioning of the tCCenvelope and with the micro-threaded column access in each tRRinterval directed to two different banks (e.g., as described in reference toFIG. 23); and a four-by-four micro-threaded mode (MT4×4) in which four row activation requests are received per tRRinterval to enable each of four dual-address column access requests to be directed to a different bank, thereby achieving four-way partitioning of each tCCinterval and enabling four different banks to be accessed in each tRRinterval (e.g., as described in reference toFIG. 17).

FIGS. 26 and 27illustrate four-by-four micro-threaded memory operations in a memory device750having the data path interfaces705A and705B described in reference toFIGS. 22 and 23to interface with a legacy data path, and having a request interface751that is substantially similar to the request interface701, except that an additional bank address input is provided to receive a fourth bank address bit. By this arrangement, a sequence of row activation requests specifying a bank in each of the four quadrants (Q0-Q3) of the memory device may be received within a single tRRinterval, thereby enabling each of four dual-address column access requests to be directed to a respective one of the four quadrants. Because unique bank, row and column addresses may be delivered to the address decoders (i.e., column decoders703and row decoders713) for each quadrant, the storage arrays in each quadrant are effectively converted from sub-banks to banks, thereby yielding a sixteen bank architecture having banks B0-B15as shown inFIG. 26. As in the other memory device embodiments discussed above, memory device750may have more or fewer storage arrays in alternative embodiments yielding correspondingly more or fewer banks. Also, any of the sixteen banks may include any number of constituent sub-banks.

Referring toFIG. 27, the row activation pipeline755A is more densely loaded than in the embodiment described in reference toFIG. 23to deliver row activation requests763,765,767and769directed to banks with each of the four quadrants of the memory device750in a single tRRinterval. That is, the tRRinterval is sub-divided into four tRRpintervals, with a row activation request being received in each. In the specific example shown inFIGS. 26 and 27, rows ‘w’, ‘y’, ‘x’ and ‘z’ are activated one after another in banks B0, B1, B8and B9, though rows may be activated in each of the four quadrants in different order in subsequent transactions or in alternative embodiments.

Referring to column access pipeline755B, a predetermined time after the first row activation request763is received, a pair of dual-address micro-threaded column access requests771,773are received one after another in a first tCCinterval. The first column access request771is directed to the same bank (B0) as the first row activation request763and specifies a pair of column locations ‘a’ and ‘e’ (e.g., a fully-specified column address and offset select value as discussed in reference toFIGS. 23-25) to be accessed one after another in successive tCCintervals. The second column access request773is similarly directed to the same bank (B1) as the second row activation request765and specifies a pair of column locations ‘c’ and ‘g’ to be accessed one after another in successive tCCintervals. Column data that corresponds to the first column address ‘a’ of column access request771is transferred a predetermined time later over the tCCpinterval starting at770and via the subset of DQ links, DQ[31:16] coupled to the data path interface705A for banks B0-B7. Column data that corresponds to the first column address ‘e’ of column access request773is transferred via the same DQ link subset, DQ[31:16], over the tCCpinterval that starts at772(i.e., over the second half of the tCCinterval that starts at770). During the succeeding tCCinterval, transfers from the open pages are repeated in respective tCCpintervals to transfer B0, column ‘e’ data and B1, column ‘g’ data. Thus, data for the two column access requests directed to low order banks, B0-B7, are transferred in interleaved fashion (i.e., B0-Ca, B1-Cc, B0-Ce, B1-Cg) in respective tCCpintervals and over a subset of the DQ links. Data for the two column access requests775,777directed to high-order banks, B8-B15, are similarly transferred in interleaved fashion (i.e., B8-Cb, B9-Cd, B8-Cf, B9-Ch) in respective tCCpintervals and over the DQ link subset, DQ[15:0]. Overall, the entire data transfer sequence in response to the column access requests775,777occurs over a tRRinterval that starts at772. In the embodiment ofFIG. 27, the data transferred in response to column access requests777and775is delayed by a tCCinterval relative to the data transferred in response to column access requests771,773due to the receipt of the column access requests777and775one tCCinterval after requests771and773. In an alternative embodiment, the data to be transferred in response to the earlier-received pair of column access requests may be buffered, then output over the same tRRinterval as the data transferred in response to the later-received pair of column access requests. In either case, because each 32-byte tCCenvelope is spatially halved and temporally halved to accommodate four micro-threaded column access transactions, an 8-byte column transaction granularity is achieved. Also, because each 64-byte tRRenvelope is subdivided to enable data transfer to or from four different banks, a sixteen byte row transaction granularity is achieved.

Still referring toFIGS. 26 and 27, the relative addressing scheme discussed in reference toFIGS. 23-25may be used to convey the second column address in each of the column access requests771,773,775,777. Also, because an additional bank address bit is provided via line BA[3] of signal path756, the operation encoding shown in the bank address field ofFIG. 25may be different and/or include additional or different operations. Further, because bandwidth for specifying precharge operations is consumed by the more densely loaded row request pipeline755A, precharge operations may be specified by the auto-precharge option indicated inFIG. 24(i.e., A8=1). Such precharge operations are shown in cross-hatched request intervals in the precharge pipeline of755C to provide an example of when such operations are carried out, but are specified in the corresponding column access requests771,773,775and777, rather than in explicit precharge requests.

FIG. 28illustrates an exemplary timing signal arrangement that may be used to convey the fourth bank address bit used in the embodiments ofFIGS. 26 and 27, thereby obviating the added BA signal link and enabling four-by-four micro-threaded operation using the legacy signal path730ofFIG. 23. In the particular example shown, instead of using a full-frequency timing signal790(i.e., clock signal or strobe signal) to time request transfer over the request path, a reduced-frequency timing signal792that exhibits alternating rising and falling edges at the start of every second request interval is used to convey the least significant bank address bit, BA[0], while the BA[2:0] signal lines are used to convey the most significant bank address bits BA[3:1]. If the first quadrant to be accessed in a given tRRinterval is an even quadrant (Q0or Q2), the timing signal792is output with a rising edge that arrives at the memory device synchronously with respect to the corresponding row activation request (or column access request) to convey BA[0]=‘0.’ If the first quadrant to be accessed is an odd quadrant (Q1or Q3), the timing signal is output with a falling edge that arrives at the memory device synchronously with respect to the corresponding row activation request to convey BA[0]=‘1.’ In the embodiment ofFIGS. 26 and 27, the least significant bit of the bank address toggles with each successive row activation request (or column access request), so that edge of the timing signal that corresponds to the second row activation request (or column access request) within a given tRRinterval will select the appropriate odd or even bank set; the opposite bank set selected by the edge of the timing signal that corresponds to the first row activation request. In the particular example shown inFIG. 28, a portion of the row request pipeline755A containing row activation requests763,765,767and769is shown in edge alignment with the timing signal792. The initial rising edge transition of the timing signal792indicates that BA[0] is a 0 so that, by delivering address values BA[3:1]=000 in row activation request763(i.e., via lines BA[2:0] of the request path), bank B0is specified by the row activation request763. The subsequent falling edge transition of the timing signal coincides with the arrival of row activation request765and indicates that BA[0]=1. Accordingly, by delivering address values BA[3:1]=000 in row activation request765, bank B1is specified. Banks B8and B9are similarly specified in row activation requests767and769by specifying BA[3:1]=100 in conjunction with a rising-edge transition and falling-edge transition, respectively, of timing signal792. A clock recovery circuit such as phase-locked loop794may be used to generate an internal timing signal795that is phase aligned with transitions of timing signal792but having a frequency that corresponds, for example, to the frequency of signal790. The internal timing signal795, which may itself be a clock signal or strobe signal, may then be used to control sampling of signals conveyed on the request path in order to capture a new request in each request interval.

FIG. 29illustrates an embodiment of a memory system800that includes a memory controller801and at least one micro-threaded memory device803. The micro-threaded memory device803may be implemented according to any of the above-described embodiments, but for present purpose is assumed to have at least two data path interfaces, DQA and DQB, for accessing respective sets of eight storage banks (i.e., DQA is used to transfer data to and from banks B0-B7, and DQB is used to transfer data to and from banks B8-B15), and a request interface, RQ, for receiving row and column requests and controlling execution of the requested row and column operations. The storage banks themselves are additionally organized in quadrants, Q0-Q3, as described above in reference to memory devices100,530,700and750, though other storage bank organizations may be used. The DQA and DQB data path interfaces are coupled to the memory controller via respective subsets of DQ links802aand802bwithin data path802, and the request interface is coupled to the memory controller via a request path804. In the embodiment shown, the request path804is formed by a set of point-to-point links, while the data path802is formed by multi-drop links (i.e., data path interfaces of one or more other memory devices may be coupled to the data path or a subset of the DQ links thereof). In alternative embodiments, the request path804may be a multi-drop path coupled to request interfaces of one or more additional memory devices (not shown) and/or the data path802may be formed by point-to-point links between the memory controller801and memory device803. Also, the memory device803may be one of multiple memory devices disposed on a memory module and coupled to a buffering circuit via a set of point-to-point links (or a multi-drop path). The buffering circuit may receive requests and/or data directed to any of the memory devices on the memory module, and retransmit the requests and/or data to the target memory device via the corresponding set of point-to-point links.

The memory controller801includes a read transaction queue811(RTQ), write transaction queue815(WTQ), read data buffer819, queue control logic817and host interface810. During an initialization or reconfiguration operation, system configuration requests are delivered to the memory controller801which, in turn, programs the memory device803(including other memory devices if present) to operate in the specified mode, for example, by issuing programming information via request path804, data path802and/or one or more other paths between the memory controller801and the memory device803(e.g., a sideband path, not shown). In one embodiment, for example, the memory controller801or other device may read a configuration memory associated with memory device803(e.g., a serial presence detect (SPD) or the like) to determine operating characteristics, constraints and modes of the memory device803(e.g., in the case of a dual-inline memory module (DIMM) or the like having the memory device803and one or more other like devices mounted thereto, the tCC, tRRand/or tRCconstraints for memory device803may be recorded within the configuration memory), then pass such information back to a processor or other host. The processor may process such information (e.g., as part of basic input-output service (BIOS) code execution), then program the memory controller801to establish a desired memory configuration, including instructing the memory controller801to program the memory device803. For example, the memory controller801may be instructed to issue micro-thread-mode register set commands as described in reference toFIG. 25to program the memory device803for single-threaded operating mode, or any of the micro-threaded operating modes described above (e.g., the MT2×2, MT4×2 and MT4×4 operating modes described above). The memory controller801may also include one or more internal configuration registers that are programmed in response to instructions received via host interface810to establish single-threaded control mode or micro-threaded control mode.

After the memory device803and memory controller801have been configured (or re-configured in the case where operating modes may be switched during run-time operation), one or more host devices such as a general purposes processor, graphics processor, network processor, and/or direct memory access (DMA) controller may issue memory access requests to the memory controller801, including memory read requests, memory write requests, masked write requests, read-modify-write requests and so forth. The incoming memory access requests are received in the queue control logic817which, in turn, queues the requests in either the read transaction queue811or write transaction queue815according to whether they specify read or write access.

The read transaction queue (RTQ)811includes four sets of read queues, Qr0/2/4/6, Qr1/3/5/7, Qr8/10/12/14and Qr9/11/13/15that correspond to four quadrants of storage banks within the memory device803. When read requests are received within the queue control logic817, the queue control logic817determines, based on address information included with the request, the memory device and storage bank to which the request is directed and stores the request in the corresponding read queue. For example, requests directed to bank0of the memory device803are stored in read queue Qr0, requests directed to bank8are stored in read queue Qr8and so forth. By organizing the read requests within the read queues in this manner, the memory controller801is able to issue row activation and column access requests in an order that supports micro-threaded memory access transactions within the memory device803. For example, assuming that each of the four sets of read queues includes at least one memory read request, then the queue control logic817may issue respective enable signals (i.e., EN1, EN2, EN3, EN4, only one of which is shown inFIG. 29) to first stage multiplexers823to control the selection of one of the four read queues from each set during a given tRRinterval. The queue control logic817additionally issues a selection-enable signal (ENp) to second stage multiplexer825to select one of the four first stage multiplexers823to output a read request from a selected read queue during each tRRpinterval or, in the case of column access requests, during each tCCpinterval. That is, the queue control logic817may transition the ENp signal from one state to another at the end of each tRRpor tCCpinterval to select another of the first stage multiplexers823, thereby enabling requests to be directed to each of the four quadrants of the memory device in round robin fashion. The first stage multiplexer825outputs requests to read/write multiplexer827which passes requests from either the read transaction queue811or write transaction queue815onto request path804in response to a control signal (R/W) from the queue control logic817. Read data output from the memory device803in response to the micro-threaded read requests are delivered to the memory controller801via data path802and buffered in a read data buffer819. The queue control logic817associates the read data with corresponding host read requests and outputs the read data to the requesting host device via the host interface.

The write transaction queue815includes four sets of write queues (i.e., Qw0/2/4/6, Qw1/3/5/7, Qw8/10/12/14and Qw9/11/13/15), first stage multiplexers833and second stage multiplexer835, each of which operate in generally the same manner as their counterparts in the read transaction queue811, except that the write queues store and output write data in addition to write requests. Thus, write requests may be issued to each of the four quadrants of the memory device803on even tRRpor tCCpintervals to initiate micro-threaded write transactions therein.

Embodiments in Computer-Readable Media

It should be noted that the various circuits disclosed herein (e.g., memory devices or component circuits thereof) may be described using computer aided design tools and expressed (or represented), as data and/or instructions embodied in various computer-readable media, in terms of their behavioral, register transfer, logic component, transistor, layout geometries, and/or other characteristics. Formats of files and other objects in which such circuit expressions may be implemented include, but are not limited to, formats supporting behavioral languages such as C, Verilog, and HLDL, formats supporting register level description languages like RTL, and formats supporting geometry description languages such as GDSII, GDSIII, GDSIV, CIF, MEBES and any other suitable formats and languages. Computer-readable media in which such formatted data and/or instructions may be embodied include, but are not limited to, non-volatile storage media in various forms (e.g., optical, magnetic or semiconductor storage media) and carrier waves that may be used to transfer such formatted data and/or instructions through wireless, optical, or wired signaling media or any combination thereof. Examples of transfers of such formatted data and/or instructions by carrier waves include, but are not limited to, transfers (uploads, downloads, e-mail, etc.) over the Internet and/or other computer networks via one or more data transfer protocols (e.g., HTTP, FTP, SMTP, etc.).

The section headings provided in this detailed description are for convenience of reference only, and in no way define, limit, construe or describe the scope or extent of such sections. Also, while the invention has been described with reference to specific embodiments thereof, it will be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than restrictive sense.