Methods, apparatuses, and systems related to a semiconductor nitridation passivation are described. An example method includes performing a dry etch process on a semiconductor structure on a wafer in a semiconductor fabrication process. The method further includes performing a dry strip process on the semiconductor structure. The method further includes performing a first wet strip clean process on the semiconductor. The method further includes performing a second wet strip clean process on the semiconductor. The method further includes performing a nitridation passivation on the semiconductor structure to avoid oxidization of the semiconductor structure. The method further performing a spacer material deposition on the semiconductor structure.

TECHNICAL FIELD

The present disclosure relates generally to semiconductor devices and methods, and more particularly to a semiconductor nitridation passivation.

BACKGROUND

Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory, including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), resistive random access memory (ReRAM), and flash memory, among others. Some types of memory devices may be non-volatile memory (e.g., ReRAM) and may be used for a wide range of electronic applications in need of high memory densities, high reliability, and low power consumption. Volatile memory cells (e.g., DRAM cells) require power to retain their stored data state (e.g., via a refresh process), as opposed to non-volatile memory cells (e.g., flash memory cells), which retain their stored state in the absence of power. However, various volatile memory cells, such as DRAM cells may be operated (e.g., programmed, read, erased, etc.) faster than various non-volatile memory cells, such as flash memory cells.

DETAILED DESCRIPTION

Various types of semiconductor structures on memory devices (e.g., those that include volatile or non-volatile memory cells) may include rectilinear trenches and/or round, square, oblong, etc., cavities that may be formed into semiconductor material to create openings thereon for subsequent semiconductor processing steps. Various materials may be deposited using chemical vapor deposition (CVD), plasma deposition, etc. and patterned using photolithographic techniques, doped and etched using vapor, wet and/or dry etch processes to form semiconductor structures on a working surface. Such openings may contain, or be associated with, various materials that contribute to data access, storage, and/or processing, or to various support structures, on the memory device. As an example, sense line contacts (e.g. bit line contacts) may be deposited into these openings to provide the data access, storage, and/or processing.

As design rules shrink, the margin for error in performance decreases. Critical dimensions become smaller and aspect ratios to openings in a semiconductor fabrication process becomes greater. In order to improve the conductivity of a cell of the memory device, a surface area of a semiconductor working surface formed into a column can be increased by increasing the height of the capacitor material column. Increasing the distance between adjacent capacitor columns can increase conductivity and capacitance. Spacer material depositions may be used to increase the pitch/distance between capacitor columns, sense lines and sense line contacts. However, the spacer material depositions may consume the materials within the plurality of sense line pillars that form the sense line contacts.

Consumption of the sense line contacts, particularly the polysilicon material at the bottom of the pillar may increase a sense line contact resistivity. Residuals from the plurality of sense line pillars may also interfere with the conductivity of the semiconductor structure and may cause shorts.

In order to mitigate this issue, a method for a semiconductor nitridation passivation is described further below. As an example, dry etch process may be performed on a semiconductor structure to shape the semiconductor structure. A dry strip process may also be performed, followed by a first wet strip clean and a second wet strip clean process. A spacer material deposition may then be performed on the semiconductor structure. A nitridation passivation may be performed on the semiconductor structure prior to the spacer material deposition to prevent oxidation and/or loss of critical dimension to the semiconductor structure. The nitridation passivation may occur multiple times during semiconductor processing steps and/or storage between steps in a fabrication sequence.

The present disclosure includes methods, apparatuses, and systems related to a semiconductor nitridation passivation. Previous approaches have attempted to protect the semiconductor structure from consumption through oxidation of the semiconductor structure while increasing the resistivity of the structure but have been unsuccessful in accomplishing both. Here, the nitridation passivation may protect the semiconductor structure from oxidation as well consumption during a spacer material deposition and may also nitridize residues/foots from the plurality of sense line pillars.

In one example, conductivity may be increased and resistivity decreased through the widened semiconductor structure width. The semiconductor structure may be by way of example and not by way of limitation, a sense line contact structure, including polysilicon material. An example method includes performing a dry etch process on a semiconductor structure on a wafer in a semiconductor fabrication process. The method further includes performing a dry strip process on the semiconductor structure. The method further includes performing a first wet strip clean process on the semiconductor. The method further includes performing a second wet strip clean process on the semiconductor. The method further includes performing a nitridation passivation on the semiconductor structure to avoid oxidization of the semiconductor structure. The method further performing a spacer material deposition on the semiconductor structure.

In the following detailed description of the present disclosure, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration how one or more examples of the disclosure may be practiced. These examples are described in sufficient detail to enable those of ordinary skill in the art to practice the examples of this disclosure, and it is to be understood that other examples may be utilized and that process, electrical, and/or structural changes may be made without departing from the scope of the present disclosure. As used herein, “a number of” something can refer to one or more such things. For example, a number of capacitors can refer to at least one capacitor.

The figures herein follow a numbering convention in which the first digit or digits correspond to the figure number of the drawing and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures may be identified by the use of similar digits. For example, reference numeral203may reference element “03” inFIG. 2, and a similar element may be referenced as303inFIG. 3. In some instances, a plurality of similar, but functionally and/or structurally distinguishable, elements or components in the same figure or in different figures may be referenced sequentially with the same element number (e.g.,209-1,209-2,209-3inFIG. 2).

FIG. 1illustrates a cross-sectional view100of an apparatus120showing a pair of neighboring memory cells sharing a source/drain region, e.g.,112-1and112-2, and a sense line contact130connecting to a passing sense line104. The pair of neighboring memory cells include access devices123-1,123-2(hereinafter referred to individually or collectively as access devices123) coupled to storage node contacts108-1,108-2(hereinafter referred to individually or collectively as storage note contacts108) and storage nodes131-1,131-2(hereinafter referred to individually or collectively as storage nodes131) in accordance with a number of embodiments of the present disclosure.

The access devices123include gates121-1,121-2, individually or collectively referred to as gates121. The gates121may also be referred to as a gate electrode. The access devices123may include recessed access devices, e.g., a buried recessed access device (BRAD). In the example shown, the gate121may include a first portion126including a metal containing material, e.g., titanium nitride (TiN), and a second portion136including a doped polysilicon to form a hybrid metal gate (HMG)121. The gate121may be separated from a channel135by a gate dielectric137. The gate121separates a first source/drain region116-1and116-2, collectively referred to as first source/drain region116, and a second source/drain region112-1and112-2, collectively referred to as second source/drain region112. In the example ofFIG. 1, two neighboring access devices123are shown sharing a second source/drain region112at a junction. The neighboring access devices123may be formed on a working surface of a semiconductor material on a substrate124.

In the example ofFIG. 1, a storage node131(shown schematically for ease of illustration) is connected to a storage node contact108formed in accordance with the techniques described herein. The storage node contact108may be connected to an active area, e.g., a first source/drain region116of an access device123. An insulation material140(e.g., a dielectric material) may be formed on the spacer material146and the gate mask material138, and in contact with a conductive material130serving as a sense line contact130. The sense line contact130may be connected to a sense line104, e.g., passing sense line orthogonal to a directional orientation of access lines connecting to gates121of the access devices123. In the example illustration ofFIG. 1, the illustrated passing sense line104is actually recessed into the page, parallel to the plane of the drawing sheet so as to be offset a particular depth from the storage nodes131. Access lines connected to gates121may be running perpendicular to a plane of the drawing sheet, e.g., coming out of the page.

In some embodiments the sense line contact130may be a metallic material, e.g., Tungsten (W). The insulation material140may be formed on the spacer material146and the gate mask material138, and in contact with the conductive sense line material130.

FIG. 2Aillustrates a cross-sectional view211of a portion of semiconductor structure of a memory device in association with a semiconductor fabrication sequence for a semiconductor structure nitridation passivation in accordance with a number of examples of the present disclosure.

The example memory device can include a plurality of sense line pillars209-1,209-2, . . . ,209-N (hereinafter referred to collectively as plurality of sense line pillars209). Each of the plurality of sense line pillars209may include a silicate material203, shown to have been formed on an underlying working surface201.

The working surface201may be formed from various undoped or doped materials on which memory device materials may be fabricated. Examples of a relatively inert undoped working surface201may include monocrystalline silicon (monosilicon), polycrystalline silicon (polysilicon), and amorphous silicon, among other possibilities. The working surface201may also be formed from an oxide material selected for dielectric properties.

The silicate material203may, in a number of examples, have been formed from a), polycrystalline silicon (polysilicon). The silicon compound may be silicon dioxide (SiO2), which may be formed by oxidation of silane (SiH4), among other possibilities. The silicon compound may also include monocrystalline silicon (monosilicon) and amorphous silicon, among other possibilities. The silicate material203may be undoped except as needed to connect with the sense line contact.

The silicate material203may be originally formed (e.g., deposited) over a surface of the underlying working surface201. The silicate material203may be formed (e.g., deposited) as a single layer on an upper surface of the working surface201. Alternatively, the silicate material203may be formed (e.g., deposited) as two separate portions (e.g., layers) on the upper surface of the working surface201. For example, the silicate material203may be formed with an opening (such as the opening illustrated between the plurality of sense line pillars209-1and209-2inFIG. 2, illustrated as pillars in this 2-dimensional format but not necessarily pillars in a 3-dimensional format, for example) formed therein from an upper surface of the working surface201to an upper surface of a barrier material205.

A barrier material205may be formed over a surface of the silicate material203opposite from the underlying working surface201. The barrier material205may be formed (e.g., deposited) over an upper surface of the silicate material203. The barrier material205may be formed from a metal material. The barrier material205may be formed from transition metals such as tungsten (W), rhenium (Re), osmium (Os), iridium (Ir), platinum (Pt), titanium (Ti), zirconium (Zr), chromium (Cr), ruthenium (Ru), and palladium (Pd), among other possibilities.

A metal material207may be formed over a surface of the barrier material205opposite from the underlying silicate material203. The metal material207may be formed (e.g., deposited) over an upper surface of the barrier material205. The metal material207may be formed from a metal material selected for conductive properties. The metal material207may be formed from materials similar to the barrier material205. The metal material207may be formed from transition metals such as tungsten (W), rhenium (Re), osmium (Os), iridium (Ir), platinum (Pt), titanium (Ti), zirconium (Zr), chromium (Cr), ruthenium (Ru), and palladium (Pd), among other possibilities.

A nitride material214may be formed over a surface of the metal material207opposite from barrier material205. The nitride material214may be formed (e.g., deposited) over an upper surface of the metal material207. The nitride material214may be formed from a nitride material selected for dielectric properties For example, one or more dielectric and/or resistor nitrides may be selected from boron nitride (BN), silicon nitride (SiNX, Si3N4), aluminum nitride (AlN), gallium nitride (GN), tantalum nitride (TaN, Ta2N), titanium nitride (TiN, Ti2N), and tungsten nitride (WN, W2N, WN2), among other possibilities, for formation of the nitride material214.

An etch process (e.g., a first wet etch process or dry etch process) may be utilized to etch via (e.g., through) the silicate material203, the barrier material205, the metal material207, and/or the nitride material214to form an opening within the previously listed materials (as is illustrated already between plurality of sense line pillars209-1and209-2). Performance of the etch process may result in formation of a column of capacitor material in an opening through any combination of the plurality of sense line pillars209in order to form a resultant opening232that extends from the upper surface of the nitride material214to the surface of the working surface201.

The resultant opening232may have a height in a range of from around 100 Angstroms (or 10 nm) to around 800 Angstroms (or 80 nm). The openings232-1. . .232-N (hereinafter referred to collectively as opening209) may span the length of the plurality of sense line pillars209. In at least one example, the width or diameter for openings232, between the plurality of sense line pillars209may be within a range of approximately 50-150 Angstroms (or 5 to 15 nm). Each of the materials (the silicate material203, the barrier material205, the metal material207, and the nitride material214) can contribute a particular height to the overall height of the structure.

FIG. 2Billustrates a cross-sectional view280of a portion of semiconductor structure of a memory device in an example of a semiconductor fabrication sequence for a semiconductor structure nitridation passivation in accordance with a number of examples of the present disclosure.FIG. 2Billustrates the example semiconductor structure at a particular stage following completion of the example fabrication sequence described in connection withFIG. 2A.

As DRAM devices scale smaller, the width of the sense line pillars209becomes smaller increasing the resistivity of the sense lines. In some embodiments, a non-conductive spacer material deposition may be used to increase the surface area of the semiconductor structure. A spacer material may be deposited on the upper surfaces of the semiconductor structure to widen the space between the plurality of sense line pillars209. The plurality of sense line pillars209may form a conductive pathway including a sense line contact.

The spacer material deposition may form also an isolation pathway for the semiconductor structure. The spacer material deposition may form an isolation layer for the plurality of sense line pillars209. The spacer material deposition may be formed from an oxide material. The spacer material deposition may be deposited from the upper surface of the nitride material214to the upper surface of the working surface201. The spacer material deposition may be used to straighten the openings232and increase the width between the plurality of sense line pillars209. That is, the spacer material deposition may be used to pattern the openings232vertically.

The spacer material deposition may include molecular hydrogen (H2) to reduce the metal material207. In one example, a Tungsten Oxide material (WOx) may be reduced back into Tungsten (W). However, the molecular hydrogen may also etch away the silicate material203. Deformation219may occur as the semiconductor structure waits to be processed. The molecular hydrogen may etch the silicate material203when there is no oxidation layer. The deformation219may occur as the molecular hydrogen etches away a portion of the silicate material203. The deformation219of the silicate material203may interfere with the pathway to the sense line contact. The deformation219of the silicate material203may lead to an increase in sense line contact resistance.

FIG. 2Cillustrates a cross-sectional view282of a portion of semiconductor structure of a memory device in another example of a semiconductor fabrication sequence for a semiconductor structure nitridation passivation in accordance with a number of examples of the present disclosure.

Previous approaches have attempted to provide an additional barrier material202to the silicate material203during the spacer material deposition. The additional barrier material202uses native oxidation on the silicate material203. However, the native oxidation consumes some of the silicate material203material.

The additional barrier material202may be directed towards the bottom surfaces of the semiconductor structure. The additional barrier material202may be directed towards the silicate material203to combat the effects of the spacer material deposition. The additional barrier material202may be directed towards the upper surface of the silicate material203to the upper surface of the working surface201. The additional barrier material202may protect the plurality of sense line pillars209from being etched by the molecular hydrogen. However, the additional barrier material202may cause oxidization of the silicate material203prior to the spacer material deposition. The oxidization from the additional barrier material202may cause the silicate material203to lose additional material. That is, oxidization from the additional barrier material202may cause the silicate material203to lose the portion of the material covered by the additional barrier material202. The loss in silicate material203may lead to an increase in sense line contact resistance.

FIG. 3Aillustrates a cross-sectional view315of a portion of semiconductor structure of a memory device in another example of a semiconductor fabrication sequence for semiconductor structure nitridation passivation in accordance with a number of examples of the present disclosure.

The cross-sectional view315can include the same or similar elements as the example cross-sectional views100,211,280, and282as referenced inFIGS. 1, 2A, 2B, and 2Crespectively. For example, the working surface301is analogous or similar to working surface201ofFIGS. 2A, 2B, and 2C. The silicate material303is analogous or similar to first silicate material203ofFIGS. 2A, 2B, and2C. The barrier material305is analogous or similar to barrier material205ofFIGS. 2A, 2B, and 2C. The metal material307is analogous or similar to metal material207ofFIGS. 2A, 2B, and 2C. The nitride material314is analogous or similar to second nitride material214ofFIGS. 2A, 2B, and 2C. The additional barrier material302is analogous or similar to additional barrier material202ofFIG. 2C. The plurality of sense line pillars309is analogous or similar to plurality of sense line pillars209ofFIGS. 2A, 2B, and 2C. The openings332is analogous or similar to plurality of sense line pillars232ofFIGS. 2A, 2B, and 2C.

During the formation of the plurality of sense line pillars309, a residue of the silicate material303may spread onto the upper surface of the working surface301. The portion of the silicate material303may create a foot318for the silicate material303. The silicate material foot318may be created on the bottom surface of the silicate material303. The silicate material foot318may result in an electrical short from capacitor structure to sense line structure.

FIG. 3Billustrates a cross-sectional view384of a portion of semiconductor structure of a memory device in another example of a semiconductor fabrication sequence for semiconductor structure nitridation passivation in accordance with a number of examples of the present disclosure.FIG. 3Billustrates the example semiconductor structure at a particular stage following completion of the example fabrication sequence described in connection withFIG. 3A.

Previous approaches have attempted to remove the silicate material foot318by oxidation. An additional barrier material302, formed from an oxide material, may be deposited on the semiconductor structure to oxidize the silicate material foot318. The additional barrier material302may be deposited on the bottom surfaces of the semiconductor structure. The additional barrier material302may be deposited on the silicate material303to protect it from the molecular hydrogen (H2) within the spacer material deposition.

The additional barrier material302may be deposited from the upper surface of the silicate material303to the upper surface of the working surface301. The additional barrier material302may be deposited in the openings332between the plurality of sense line pillars309from the upper surface of the silicate material303to the upper surface of the working surface301to ensure coverage of the silicate material foot318. However, in previous approaches the additional barrier material202have been insufficient to oxidize the silicate material foot318. A portion of the silicate material foot318may be oxidized by the additional barrier material302. The unoxidized portion of the silicate material foot318may reduce the pitch/space between the plurality of sense line pillars309, which may lead to reduction in conductivity and possibly shorts.

FIG. 3Cillustrates a cross-sectional view386of a portion of semiconductor structure of a memory device in another example of a semiconductor fabrication sequence for semiconductor structure nitridation passivation in accordance with a number of examples of the present disclosure.FIG. 3Cillustrates the example semiconductor structure at a particular stage following completion of the example fabrication sequence described in connection withFIG. 3A.

A nitridation passivation process306may be employed to decrease etching away of the silicate material303by the molecular hydrogen and decrease sense line contact resistance while completely nitridizing the silicate material foot318. The nitridation material may be formed from a dintrogen (N2) plasma. The semiconductor structure may be purged with dintrogen to remove residual gases such as oxygen. A passivation process may be added to the dinitride purge process. As used herein, “passivation” may refer to the process of treating or coating a surface in order to reduce the chemical reactivity of its surface. Here, the dinitride material passivates the plurality of sense line pillars309from oxidization during the spacer material deposition process. In some examples, a nitridation passivation process306similar to the remote plasma nitridation (RPN) may be used. In other examples, a nitridation passivation process306similar to the decoupled plasma nitridation (DPN) may also be used.

The nitridation passivation process306may occur during semiconductor processing. The nitridation passivation process306may occur while the semiconductor structure waits to be processed. The semiconductor structure may be stored in a Front Opening Universal Pod (FOUP) while waiting to be processed. The nitridation passivation process306may occur within the FOUP. The nitridation passivation process306may protect the semiconductor structure from native oxygen while waiting within the FOUP. The nitridation passivation process306may prevent oxidization of the silicate material303.

In one example, the nitridation passivation may be deposited onto the semiconductor structure. immediately before the spacer material deposition. That is, a dry etch process may be performed on the semiconductor structure, then a dry strip process followed by a first wet strip clean and a second wet strip clean process and then the nitridation passivation process306, followed by the spacer material deposition.

A dry etch may be subsequently used to etch a portion of the materials within the plurality of sense line pillars109. The dry etch may be carried out using plasma. The dry etch plasma may be formed from bromous (HBr/O2) acid. The dry etch process may be followed by a dry strip process. A dry strip process may be carried out using a dry etch plasma. The dry etch strip chemistry may comprise of a mixture of nitrogen gas (N2) and hydrogen gas (H2).

The dry etch strip process may be followed by a first wet strip clean and a second wet strip clean process. The wet strip clean processes may be carried out using a wet etch. The wet etch may be carried out using a dilute hydrofluoric (HF) acid combination. The first wet strip process may contain a dilution at a ratio between 1500 to 2500 parts water to 1 part acid. The second wet strip process may contain a dilution at a ratio between 100 to 500 parts water to 1 part acid. The second wet strip clean process may be followed by the nitridation passivation process and then by the spacer material deposition.

In another example, the nitridation passivation process306may occur after the first wet strip clean process on the semiconductor structure. That is, a dry etch process may be performed on the semiconductor structure, then a dry strip process followed by a first wet strip clean process, and then the nitridation passivation process306, after which the second wet strip clean process will be performed followed by the spacer material deposition.

In one example, the nitridation passivation process306may occur multiple times. For example, the nitridation passivation process306may occur after the dry strip process and also after the wet strip clean process. That is, a dry etch process may be performed on the semiconductor structure, then a dry strip process followed by a first nitridation passivation, and then the first wet strip clean process, after which a second nitridation passivation process will be performed, followed by the second wet strip clean process and then the spacer material deposition. The nitridation passivation process306may occur as needed while the semiconductor structure waits in the FOUP.

In some examples, an elevated temperature anneal process may occur after a nitridation passivation process306within the semiconductor structure. That is, the elevated temperature dilution may occur after the first nitridation passivation. The elevated temperature dilution may also occur after the second nitridation passivation. The anneal process may have an elevated temperature ranging from 500 to 1200 degrees Celsius.

The nitridation passivation process306may be effective at passivating horizontal surfaces. The nitridation passivation process306may be targeted toward the bottom of the semiconductor structure. As such, the nitridation passivation process306may target the silicate material foot (318as illustrated inFIGS. 3A and 3B) at the bottom of semiconductor structure. The silicate material foot is completely nitridized and become non-conductive during the nitridation passivation process306. The non-conductive foot may no longer pose a risk of electrical shorts from capacitor structure to sense line structure. The removal of the silicate material foot may improve protection of the semiconductor structure against potential shorts by a range between 40% to 80%. The removal of all silicate material residue may also decrease sense line contact resistivity by a range between 4% to 15%.

FIG. 4illustrates an example processing apparatus451that may be used in a semiconductor fabrication process. The processing apparatus451may include a chamber452to enclose components configured to perform deposition and/or etch operations on a number of semiconductor devices. The chamber452may further enclose a carrier453to hold a batch of semiconductor wafers454. The processing apparatus451may include and/or be associated with tools including, for example, a pump455unit and a purge456unit configured to introduce and remove appropriate etch chemistries, as described herein, at each point in the semiconductor fabrication sequence. The processing apparatus451may further include a temperature control457unit configured to maintain the chamber452at an appropriate temperature at each of the points in the fabrication sequence. The system450may include a number of chambers452that are each configured to perform particular processes (e.g., a wet etch process, a dry etch process, and/or a deposition process, among others) during the fabrication sequence.

The system450may further include a controller458. The controller458may include, or be associated with, circuitry and/or programming for implementation of, for instance, nitridation passivation on a semiconductor structure. The material may be grown to a size that seals the non-solid space adjacent the storage node contact. Adjustment of such deposition, removal, and etching operations by the controller458may control the critical dimensions (CDs) of the semiconductor devices created in the processing apparatus451.

A host may be configured to generate instructions related to nitridation passivation on a semiconductor structure. The instructions may be sent via a host interface to the controller458of the processing apparatus451. The instructions may be based at least in part on scaled preferences (e.g., in numerically and/or structurally defined gradients) stored by the host, provided via input from another storage system (not shown), and/or provided via input from a user (e.g., a human operator), among other possibilities. The controller458may be configured to enable input of the instructions and scaled preferences to define the CDs of the fabrication of the semiconductor device to be implemented by the processing apparatus451.

The scaled preferences may determine final structures (e.g., the CDs) of passing sense lines and storage node contact. Particular CDs may be enabled by the particular scaled preferences that are input via the instructions. Receipt and implementation of the scaled preferences by the controller458may result in corresponding adjustment, by the processing apparatus451, of a deposition time for the nitridation passivation process, adjustment of a coverage area, height, and/or volume of the nitridation passivation material, among implementation of other possible scaled preferences.

The controller458may, in a number of embodiments, be configured to use hardware as control circuitry. Such control circuitry may, for example, be an application specific integrated circuit (ASIC) with logic to control fabrication steps, via associated deposition and etch processes, nitridation passivation on a semiconductor structure. The controller458may be configured to receive the instructions and direct performance of operations to perform a nitridation passivation on a semiconductor structure as described in connection withFIG. 1-3.

FIG. 5is a functional block diagram of a computing system556including at least one memory system562in accordance with one or more embodiments of the present disclosure. The numbering convention used in connection withFIG. 5does not follow the earlier introduced numbering convention and sequence that applies toFIGS. 1-3. Memory system562may be, for example, a solid-state drive (SSD).

In the embodiment illustrated inFIG. 5, memory system562includes a memory interface564, a number of memory devices568-1, . . .568-N, and a controller566selectably coupled to the memory interface564and memory devices568-1, . . .568-N. Memory interface564may be used to communicate information between memory system562and another device, such as a host558. Host558may include a processor (not shown). As used herein, “a processor” may be a number of processors, such as a parallel processing system, a number of coprocessors, etc. Example hosts may include, or by implemented in, laptop computers, personal computers, digital cameras, digital recording devices and playback devices, mobile telephones, PDAs, memory card readers, interface hubs, and the like. Such a host558may be associated with fabrication operations performed on semiconductor devices and/or SSDs using, for example, a processing apparatus shown at551and described in connection withFIG. 5.

In a number of embodiments, host558may be associated with (e.g., include or be coupled to) a host interface560. The host interface560may enable input of scaled preferences (e.g., in numerically and/or structurally defined gradients) to define, for example, critical dimensions (CDs) of a final structure or intermediary structures of a memory device (e.g., as shown at568) and/or an array of memory cells (e.g., as shown at570) formed thereon to be implemented by the processing apparatus551. The array includes access devices having nitridation passivation on a semiconductor structure according to embodiments described herein. The scaled preferences may be provided to the host interface560via input of a number of preferences stored by the host558, input of preferences from another storage system (not shown), and/or input of preferences by a user (e.g., a human operator).

Memory interface564may be in the form of a standardized physical interface. For example, when memory system562is used for information (e.g., data) storage in computing system556, memory interface564may be a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, or a universal serial bus (USB) interface, among other physical connectors and/or interfaces. In general, however, memory interface564may provide an interface for passing control, address, information, scaled preferences, and/or other signals between the controller566of memory system562and a host558(e.g., via host interface560).

Controller566may include, for example, firmware and/or control circuitry (e.g., hardware). Controller566may be operably coupled to and/or included on the same physical device (e.g., a die) as one or more of the memory devices568-1, . . .568-N. For example, controller566may be, or may include, an ASIC as hardware operably coupled to circuitry (e.g., a printed circuit board) including memory interface564and memory devices568-1, . . .568-N. Alternatively, controller566may be included on a separate physical device that is communicatively coupled to the physical device (e.g., the die) that includes one or more of the memory devices568-1, . . .568-N.

Controller566may communicate with memory devices568-1, . . .568-N to direct operations to sense (e.g., read), program (e.g., write), and/or erase information, among other functions and/or operations for management of memory cells. Controller566may have circuitry that may include a number of integrated circuits and/or discrete components. In a number of embodiments, the circuitry in controller566may include control circuitry for controlling access across memory devices568-1, . . .568-N and/or circuitry for providing a translation layer between host558and memory system562.

Memory devices568-1, . . .568-N may include, for example, a number of memory arrays570(e.g., arrays of volatile and/or non-volatile memory cells). For instance, memory devices568-1, . . .568-N may include arrays of memory cells, such as a portion of an example memory device structured to include storage node contacts. At least one array includes an access device having a storage node contact formed according to the embodiments disclosed herein. As will be appreciated, the memory cells in the memory arrays570of memory devices568-1, . . . . ,568-N may be in a RAM architecture (e.g., DRAM, SRAM, SDRAM, FeRAM, MRAM, ReRAM, etc.), a flash architecture (e.g., NAND, NOR, etc.), a three-dimensional (3D) RAM and/or flash memory cell architecture, or some other memory array architecture including pillars and adjacent trenches.

Memory device568may be formed on the same die. A memory device (e.g., memory device568-1) may include one or more arrays570of memory cells formed on the die. A memory device may include sense circuitry572and control circuitry574associated with one or more arrays570formed on the die, or portions thereof. The sense circuitry572may be utilized to determine (sense) a particular data value (e.g., 0 or 1) that is stored at a particular memory cell in a row of an array570. The control circuitry574may be utilized to direct the sense circuitry572to sense particular data values, in addition to directing storage, erasure, etc., of data values in response to a command from host558and/or host interface560. The command may be sent directly to the control circuitry574via the memory interface564or to the control circuitry574via the controller566.

The embodiment illustrated inFIG. 5may include additional circuitry that is not illustrated so as not to obscure embodiments of the present disclosure. For example, memory device568may include address circuitry to latch address signals provided over I/O connectors through I/O circuitry. Address signals may be received and decoded by a row decoder and a column decoder to access a memory array570. It will be appreciated that the number of address input connectors may depend on the density and/or architecture of memory devices568and/or memory arrays570.

It is to be understood that the terminology used herein is for the purpose of describing particular examples only and is not intended to be limiting. As used herein, the singular forms “a”, “an”, and “the” include singular and plural referents, unless the context clearly dictates otherwise, as do “a number of”, “at least one”, and “one or more” (e.g., a number of memory arrays may refer to one or more memory arrays), whereas a “plurality of” is intended to refer to more than one of such things. Furthermore, the words “can” and “may” are used throughout this application in a permissive sense (i.e., having the potential to, being able to), not in a mandatory sense (i.e., must). The term “include,” and derivations thereof, means “including, but not limited to”. The terms “coupled” and “coupling” mean to be directly or indirectly connected physically and, unless stated otherwise, can include a wireless connection for access to and/or for movement (transmission) of instructions (e.g., control signals, address signals, etc.) and data, as appropriate to the context.

While example examples including various combinations and configurations of semiconductor materials, underlying materials, structural materials, dielectric materials, capacitor materials, working surface materials, silicate materials, nitride materials, buffer materials, etch chemistries, etch processes, solvents, memory devices, memory cells, sidewalls of openings and/or trenches, among other materials and/or components related to a semiconductor structure nitridation passivation have been illustrated and described herein, examples of the present disclosure are not limited to those combinations explicitly recited herein. Other combinations and configurations of the semiconductor materials, underlying materials, structural materials, dielectric materials, capacitor materials, substrate materials, working surfaces, silicate materials, nitride materials, buffer materials, etch chemistries, etch processes, solvents, memory devices, memory cells, sidewalls of openings and/or trenches related to a semiconductor structure nitridation passivation than those disclosed herein are expressly included within the scope of this disclosure.

In the foregoing Detailed Description, some features are grouped together in an example for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the disclosed examples of the present disclosure have to use more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a disclosed example. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate example.