Semiconductor device having redundancy word lines

Disclosed herein is an apparatus that includes first register circuits configured to store a first address, and a comparing circuit configured to compare the first address with a second address. The comparing circuit includes first and second circuit sections. In a first operation mode, the comparing circuit is configured to activate a match signal when the first circuit section detects that the first bit group of the first address matches with the third bit group of the second address and the second circuit section detects that the second bit group of the first address matches with the fourth bit group of the second address. In a second operation mode, the comparing circuit is configured to activate the match signal when the first circuit section detects that the first bit group matches with the third bit group regardless of the second and fourth bit groups.

BACKGROUND

In a semiconductor memory device such as a DRAM, a defective normal word line is replaced by a redundancy word line. However, generally in a refresh operation, a plurality of normal word lines are selected at the same time, so that control of refreshing a redundancy word line instead of a defective normal word line cannot be executed easily. Therefore, in a refresh operation, there is a case of employing a system in which refresh of a defective normal word line is stopped without performing any replacement and all redundancy word lines are refreshed regardless of the use of them. However, in this case, there is a possibility that there are defective redundancy word lines among them. It is not desirable to perform a refresh operation on defective redundancy word lines.

DETAILED DESCRIPTION

Various embodiments of the present disclosure will be explained below in detail with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings that show, by way of illustration, specific aspects, and various embodiments of the present disclosure. The detailed description provides sufficient detail to enable those skilled in the art to practice these embodiments of the present disclosure. Other embodiments maybe utilized, and structural, logical, and electrical changes maybe made without departing from the scope of the present disclosure. The various embodiments disclosed herein are not necessary mutually exclusive, as some disclosed embodiments can be combined with one or more other disclosed embodiments to form new embodiments.

FIG.1is a block diagram showing a configuration of a semiconductor device10according to the present disclosure. The semiconductor device10shown inFIG.1is a DRAM, for example, and includes a memory cell array11, an access control circuit12that performs access to the memory cell array11, and an I/O circuit13that performs input and output of data to and from the memory cell array11. The access control circuit12performs access to the memory cell array11based on a command address signal CA input from an external controller via command address terminals14. In a read operation, data DQ read from the memory cell array11is output to data I/O terminals15via the I/O circuit13. In a write operation, data DQ input from an external controller to the data I/O terminals15is written in the memory cell array11via the I/O circuit13. The access control circuit12includes a redundancy control circuit16and a refresh counter17. When the power of the semiconductor device10is turned on, defective address data having been written in an anti-fuse array18is transferred to the redundancy control circuit16. The anti-fuse array18includes a plurality of anti-fuse sets19.

FIG.2is a schematic diagram for explaining a configuration of the memory cell array11. As shown inFIG.2, the memory cell array11includes a plurality of memory mats20that are arranged in a matrix. Each of the memory mats20includes a plurality of word lines WL and a plurality of bit lines BL, and a memory cell MC is arranged on the intersection of these lines. The word lines WL are driven by a word driver21. The potential generated in the bit line BL is amplified by a sense amplifier22. A redundancy region20R is included in some of the memory mats20. As shown inFIG.3, the redundancy region20R includes a plurality of redundancy word lines RWL. A defective word line WL is replaced by a redundancy word line RWL. The example shown inFIG.3represents a state where a defective word line WL0included in a memory mat20iis replaced by a redundancy word line RWL0included in a memory mat20j, and a defective word line WL1included in the memory mat20jis replaced by a redundancy word line RWL1included in the memory mat20j.

Here, in a case where the command address signal CA indicates an active command, a certain word line WL is selected based on a row address input from an external controller with the active command. At this time, when the row address indicates a defective word line WL, a redundancy word line RWL is selected instead of the word line WL indicated by the row address. As an example, the mw address has a 16-bit configuration. Meanwhile, when the command address signal CA indicates a refresh command, a refresh address is generated by the refresh counter17. Subsequently, a refresh operation is performed on the word line WL or the redundancy word line RWL indicated by the refresh address. As an example, the refresh address has a 14-bit configuration.

FIG.4is a diagram showing an example of count values of the refresh counter17. Each of the count values of the refresh counter17is incremented each time a refresh command is issued. In the example shown inFIG.4, the refresh address has a 14-bit configuration constituted by CBR<13:0>. Among these bits, CBR<12:0> that is a lower-order 13 bit is a real address, and CBR<13> that is a highest-order bit is used as a signal for selecting whether refreshing either a normal word line WL or a redundancy word line RWL. When the highest-order bit CBR<13> indicates 0, a normal word line WL is selected and the highest-order bit CBR<13> indicates 1, a redundancy word line RWL is selected. In a case where the highest-order bit CBR<13> indicates 1, the refresh address has a 7-bit configuration constituted by CBR<6:0>. Therefore, when the highest-order bit CBR<13> indicates 0, addresses of 8192 patterns are expressed with CBR<12:0>, and when the highest-order bit CBR<13> indicates 1, addresses of 128 patterns are expressed with CBR<6:0>. The maximum value of count values of the refresh counter17is 8319, and when the value reaches 8319, it subsequently returns to 0. With this process, after word lines WL as refresh operation targets are selected in the order of an arrow A shown inFIG.2, redundancy word lines RWL are selected in the order of an arrow B. Here, when the row address has a 16-bit configuration, the refresh address CBR<12:0> with the real address thereof having a 13-bit configuration is in a state where the higher-order three bits of the row address are degenerated. Therefore, each time a refresh address is updated, eight word lines WL or eight redundancy word lines RWL are selected at the same time.

FIG.5is a block diagram showing a configuration of the redundancy control circuit16. As shown inFIG.5, the redundancy control circuit16includes a plurality of detection circuits30to3nand an encoding circuit41that receives match signals MCH0to MCHn respectively output from the detection circuits30to3n. The detection circuits30to3nare respectively assigned to corresponding ones of redundancy word lines RWL. Therefore, when there are 128 redundancy word lines RWL,128sets of detection circuits30to3nare provided. A row address RA<15:0> is commonly supplied to a plurality of detection circuits30to3n. In a refresh operation on a normal word address WL, higher-order three bits RA<15:13> of an internally generated row address are added to the refresh address CBR<12:0>. The higher-order three bits RA<15:13> of the row address to be added to the refresh address CBR<12:0> are continuously incremented before starting a refresh operation, thereby sequentially adding eight patterns from b000 to b111. In a refresh operation on a redundancy word line RWL, the refresh addresses CBR<13> and CBR<6:0> are used as row addresses RA as they are. The encoding circuit41generates an address RWLADD of the redundancy word line RWL and a refresh stop signal RMatch based on the match signals MCH0to MCHn.

FIG.6is a block diagram showing a configuration of the detection circuit30. As shown inFIG.6, the detection circuit30includes register circuits RG0to RG15that respectively store therein corresponding one of address bits RR0to RR15, a register circuit RGEn that stores therein an enable bit En, and a comparing circuit42that compares the address bits RR0to RR15and the row address RA<15:0>. The address bits RR0to RR15and the enable bit En to be respectively stored in the register circuits RG0to RG15and RGEn are transferred from corresponding ones of anti-fuse sets19at the time of initialization after turning on the power of the semiconductor device10. Here, the enable bit En is set to be enable (=1) when a corresponding redundancy word line RWL is used for a replacing operation. In this case, the row address RA of a defective word line WL, which is a replacement source, is stored in the register circuit RG0to RG15. Meanwhile, when the corresponding redundancy word line RWL is not used for a replacing operation and when the corresponding redundancy word line RWL is defective, the enable bit En is set to be disable (=0). When the corresponding redundancy word line RWL is defective, the row address RA of the defective redundancy word line RWL is stored in the register circuits RG0to RG6. The detection circuits31to3nshown inFIG.6also have the same circuit configuration as that of the detection circuit30.

Status signals RefRedF and RedDisRef are also input to the comparing circuit42. The status signals RefRedF and RedDisRef are generated by the circuit shown inFIG.7. As shown inFIG.7, the status signals RefRedF and RedDisRef are generated with a disable signal RedDis and a status signal RefRed. The disable signal RedDis is a type of test signals, and as the disable signal RedDis is set to be a high level, a replacing operation of word lines by the redundancy control circuit16is prohibited. The status signal RefRed is a signal that becomes a high level during a period where the redundancy word line RWL is refreshed in a refresh operation. Normally, the disable signal RedDis is in a low level, and in this case the status signal RefRedF is in an inverted level of that of the status signal RefRed, and the status signal RedDisRef has the same level as that of the status signal RefRed.

FIG.8is a circuit diagram of the comparing circuit42. As shown inFIG.8, the comparing circuit42includes exclusive NOR gate circuits XNOR0to XNOR15that respectively generate a bit match signal M<15:0> by comparing each bit of a mw address RR<15:0> stored in the register circuits RG0to RG15and each bit of the row address RA<15:0>, and a logical gate circuit50that generates a match signal MCH (any of MCH0to MCHn) based on the bit match signal M<15:0>. The logical gate circuit50includes a first circuit section51, a second circuit section52, a third circuit section53, and an AND gate circuit54. The first circuit section51receives bit match signals M<13> and M<6:0> and when these signals are in a high level, a hit signal H1is activated to be a high level. Eight bits of row addresses RA<13> and RA<6:0> corresponding to the bit match signals M<13> and M<6:0> constitute a first bit group of a row address RA. The second circuit section52receives bit match signals M<15:14> and M<12:7> and when these signals are in a high level, a hit signal H2is activated to be a high level. Eight bits of row addresses RA<15:14> and RA<12:7> corresponding to the bit match signals M<15:14> and M<12:7> constitute a second bit group of a row address RA. A NAND gate circuit60that receives the status signal RefRedF is provided in the final stage of the second circuit section52. With this configuration, when the status signal RefRedF is at a low level, the hit signal H2becomes a high level regardless of the bit match signals M<15:14> and M<12:7>. The third circuit section53includes an OR gate circuit61that receives an enable signal En and the status signal RefRedF, an OR gate circuit62that receives an inverted enable signal EnF and the status signal RedDisRef, and a NAND gate circuit63that receives outputs from the OR gate circuits61and62to generate an enable signal MCHEn. Subsequently, when the hit signals H1and H2and the enable signal MCHEn are all in a high level, the match signal MCH output from the AND gate circuit54is activated to be a high level.

As described above, the enable bit En is set to be a high level when a corresponding redundancy word line RWL is used for a replacing operation. In this case, as shown inFIG.9A, the row address RR<15:0> that is the same as the row address RA<15:0> of a defective word line WL, which is a replacement source, is stored in the register circuits RG0to RG15. With this process, when the row address RA<15:0> input from an external controller with an active command matches the row address RR<15:0> stored in any of the detection circuits30to3n, a corresponding match signal MCH is activated. In response thereto, the encoding circuit41generates an address RWLADD of a redundancy word line RWL corresponding to the activated match signal MCH. As a result, a redundancy word line RWL indicated by the address RWLADD is selected instead of the word line WL indicated by the input row address RA<15:0>. Meanwhile, in a refresh operation, three bits are added to higher-bits of the refresh address CBR<12:0> output from the refresh counter17, thereby generating a 16-bit row address RA<15:0>. The higher-order three bits of the row address change from b000 to bill, and thus eight types of mw addresses RA<15:0> are generated sequentially. Subsequently, when one or two or more addresses among the eight types of mw addresses RA<15:0> match the row address RR<15:0> stored in any of the detection circuits30to3n, a corresponding match signal MCH is activated. In response thereto, the encoding circuit41activates the refresh stop signal RMatch and a refresh operation on a corresponding word line WL is canceled. As a result, a refresh operation on a defective word line WL is not performed.

Meanwhile, in a case where a corresponding redundancy word line RWL is not used for a replacing operation and where the corresponding redundancy word line RWL is defective, the enable bit En is set to be a low level. Here, in a case where the corresponding redundancy word line RWL is not used for a replacing operation, as shown inFIG.9B, a bit RR<13> stored in the register circuit RG13is set to be a low level. As a result, the match signal MCH is not activated regardless of the value of the row address RA<15:0> input from an external controller with an active command and the value of the refresh address CBR<13:0> that is generated in a refresh operation. Accordingly, the corresponding redundancy word line RWL becomes an unused state. Meanwhile, in a case where the corresponding redundancy word line RWL is defective, as shown inFIG.9C, the bit RR<13> stored in the register circuit RG13is set to be a high level, and a row address RR<6:0> that is the same as the row address RA<6:0> of a defective redundancy word line RWL is stored in the register circuits RG0to RG6. Here, during a period where the redundancy word line RWL is refreshed (RefRedF, CBR<13>=1), the hit signal H2becomes a high level regardless of the bit match signals M<15:14> and M<12:7>, and thus when the refresh address CBR<6:0> and the row address RR<6:0> match each other, the match signal MCH is activated regardless of the remaining address bits RA<15:14> and RA<12:7>. In response thereto, the encoding circuit41activates the refresh stop signal RMatch and a refresh operation on a corresponding redundancy word line RWL is canceled. As a result, a refresh operation on a defective redundancy word line WL is not performed.

FIG.10is a timing chart showing changes in various signals in a refresh operation. As shown inFIG.10, each time a refresh command REF is issued from outside, the refresh address CBR<13:0> generated by the refresh counter17is updated. During a period where the refresh address CBR<13> is 0, that is, a period where a normal word line WL is refreshed, the status signal RefRed becomes a low level. During a period where the refresh address CBR<13> is 1, that is, a period where a redundancy word line RWL is refreshed, the status signal RefRed becomes a high level. In the example shown inFIG.10, the value of the row address RR<15:0> stored in any of the detection circuit30to3nis hFFFF, and its corresponding enable signal En is a high level. In this case, when the value of CBR<12:0> reaches the maximum value, which is h1FFF, at a timing when the higher-order three bits of a row address to be added to CBR<12:0> become b111, the match signal MCH is activated. In response thereto, the refresh stop signal RMatch is activated and a refresh operation on a corresponding word line WL is canceled. Further, in the example shown inFIG.10, the value of the row address RR<6:0> stored in any of the detection circuits30to3nis h03, and its corresponding enable signal En is a low level. In this case, when the value of CBR<6:0> becomes h03, the match signal MCH is activated. In response thereto, the refresh stop signal RMatch is activated and a refresh operation on a corresponding redundancy word line RWL is canceled.

As described above, according to the semiconductor device10of the present disclosure, a refresh operation on defective word lines WL and defective redundancy word lines RWL is not performed, and thus erroneous operations can be prevented from happening. In order to realize this prevention, in a test process performed at a manufacturing stage, the mw address RA<15:0> of a defective word line WL is written in any of the anti-fuse sets19and the row address RA<6:0> of a defective redundancy word line RWL is written in the anti-fuse set19assigned to the corresponding redundancy word line RWL. Subsequently, when the row address RA<15:0> of the defective word line WL is written in the anti-fuse set19, its corresponding enable signal En is set to be a high level. Meanwhile, when the row address RA<6:0> of the defective redundancy word line RWL is written in the anti-fuse set19, its corresponding enable signal En is set to be a low level and a row address RR<13> is set to be a high level.

Although various embodiments have been disclosed in the context of certain preferred embodiments and examples, it will be understood by those skilled in the art that the scope of the present disclosure extends beyond the specifically disclosed embodiments to other alternative embodiments and/or uses of the embodiments and obvious modifications and equivalents thereof. In addition, other modifications which are within the scope of this disclosure will be readily apparent to those of skill in the art based on this disclosure. It is also contemplated that various combination or sub-combination of the specific features and aspects of the embodiments may be made and still fall within the scope of the disclosure. It should be understood that various features and aspects of the disclosed embodiments can be combined with or substituted for one another in order to form varying modes of the disclosed embodiments. Thus, it is intended that the scope of at least some of the present disclosure should not be limited by the particular disclosed embodiments described above.