Semiconductor devices including a plurality of stacked cell structures

A semiconductor device includes a stacked structure of cell structures, an electrode structure, and a heating electrode. Each cell structure includes a capping layer, a selection layer, a buffer layer, a variable resistance layer, and a upper electrode layer sequentially stacked. The electrode structure is in an opening passing through the stacked structure, is electrically isolated from the buffer layer, the variable resistance layer, and the upper electrode layer, and is electrically connected to the selection layer. The heating electrode is between the variable resistance layer and the upper electrode layer and operates to transfer heat to the variable resistance layer.

CROSS-REFERENCE TO RELATED APPLICATION

Korean Patent Application No. 10-2016-0165222, filed on Dec. 6, 2016, and entitled, “Semiconductor Devices,” is incorporated by reference herein in its entirety.

BACKGROUND

One or more embodiments described herein relate to a semiconductor device.

2. Description of the Related Art

Attempts are continually being made to increase the integration of memory devices. One attempt involves the development of a variable-resistance memory device having a vertically stacked arrangement of memory cells.

SUMMARY

In accordance with one or more embodiments, a semiconductor device includes a stacked structure including a plurality of cell structures stacked on a substrate, each of the plurality of cell structures including a capping layer, a selection layer, a buffer layer, a variable resistance layer, and a upper electrode layer sequentially stacked; an electrode structure in an opening through the stacked structure, the electrode structure electrically isolated with the buffer layer, the variable resistance layer, and the upper electrode layer and electrically connected to the selection layer; and a heating electrode between the variable resistance layer and the upper electrode layer, the heat electrode to transfer heat to the variable resistance layer.

In accordance with one or more other embodiments, a semiconductor device includes a stacked structure including a plurality of cell structures stacked on a substrate, each of the plurality of cell structures including an insulation pattern and a lower electrode layer stacked; a selective pattern on a sidewall of an opening through the stacked structure; an electrode structure on the selective pattern and filling the opening; and a variable resistance layer between the lower electrode layer and the selective pattern, the variable resistance layer directly contacting the selective pattern.

In accordance with one or more other embodiments, a semiconductor device includes an electrode structure; and a plurality of cell structures in a stack, wherein each of the plurality of cell structures corresponds to a memory cell and includes a selection layer, a variable resistance layer, a heating layer, and an electrode layer, the electrode structure electrically connected to the selection layer and electrically isolated from the variable resistance layer, the heating layer, and the electrode layer, the heating layer to transfer heat to the variable resistance layer.

DETAILED DESCRIPTION

FIGS. 1 and 2are cross-sectional views illustrating an embodiment of a variable resistance memory device.FIG. 3illustrates a plan view of the variable resistance memory device according to an example embodiment.

Referring toFIG. 1, the variable resistance memory device may include stacked cell structures10a,20aand30aon a substrate100. Each of the cell structures10a,20aand30amay include a capping layer102a, a first buffer layer104a, a selection layer106a, a second buffer layer108a, a variable resistance layer110aand an upper electrode layer112asequentially stacked. The cell structures10a,20aand30amay be stacked in a first direction, which may be substantially perpendicular to a top surface of the substrate100. The number of stacked cell structures10a,20aand30amay vary in different embodiments. An upper capping layer202amay be on an uppermost cell structure30a.

The first buffer layer104amay include an insulation material having a predetermined high selectivity with respect to an insulation material of the second buffer layer108a. Further, each of the first and second buffer layers104aand108amay include a material having a predetermined high selectivity with respect to the capping layer102a. For example, the first buffer layer104amay include silicon oxide, and the second buffer layer108amay include polysilicon, SiC, SiOC, or another material.

The selection layer106amay include an Ovonic threshold switch (OTS) material. The OTS material may have a variable resistance according to temperature at an amorphous state. Thus, the selection layer106aincluding the OTS material may serve as a switching element. In an example embodiment, the OTS material may include germanium (Ge), silicon (Si), arsenic (As) and/or tellurium (Te). Also, the OTS material may further include selenium (Se) and/or sulfur (S).

In example embodiments, the variable resistance layer110amay include a chalcogenide-based material having a phase that changes from an amorphous state to a crystalline state, for example, by Joule heating. For example, the variable resistance layer110amay have a variable resistance according to a phase transition. The variable resistance memory may therefore serve as a phase-change random access memory (PRAM) device.

The chalcogenide-based material may include, for example, a GST material including germanium (Ge), antimony (Sb), and/or tellurium (Te) in a predetermined ratio. In some example embodiments, the variable resistance layer110amay have a superlattice structure that includes a stacked structure containing GeTe—SbTe. In one embodiment, the variable resistance layer may include an In—Sb—Te (IST) material or a Bi—Sb—Te (BST) material.

In some example embodiments, the variable resistance layer110amay include a material having a resistance that changes by a magnetic field or a spin transfer torque (STT). The variable resistance layer110amay include a ferromagnetic material, e.g., iron (Fe), nickel (Ni), cobalt (Co), dysprosium (Dy), gadolinium (Gd), etc. The variable resistance memory device may therefore serve as a magnetic random access memory (MRAM) device.

In some example embodiments, the variable resistance layer110amay include a perovskite material, e.g., STO (SrTiO3), BTO (BaTiO3), PCMO (Pr1-XCaXMnO3), etc., or a transition metal oxide, e.g., zirconium oxide (ZrOX), aluminum oxide (AlOX), hafnium oxide (HfOX), etc. The variable resistance memory device may therefore serve as a resistive random access memory (ReRAM) device.

The upper electrode layer112amay include a metal nitride or a metal silicon nitride. In example embodiments, the upper electrode layer112amay include, e.g., titanium nitride (TiNX), titanium silicon nitride (TiSiNx), tungsten nitride (WNx), tungsten silicon nitride (WSiNx), tantalum nitride (TaNx), tantalum silicon nitride (TaSiNx), zirconium nitride (ZrNx), zirconium silicon nitride (ZrSiNx), titanium aluminum nitride, etc.

The upper capping layer202a, upper electrode layer112a, and the cell structures10a,20a, and30amay include an opening150which exposes an upper surface of the substrate100. A plurality of openings150may be spaced from each other at regular or predetermined intervals.

A second recess may be between the opening150and a sidewall of the first buffer layer104aadjacent to the opening150. A first conductive pattern158amay be on the sidewall of the first buffer layer104a, and may fill the second recess. An upper surface of the first conductive pattern158amay contact a bottom of the selection layer106a. The first conductive pattern158amay surround the opening150and include a conductive material (e.g., tungsten) with an oxide.

A first recess may be between the opening150and a sidewall of the second buffer layer108aadjacent to the opening150. A heating electrode (or heating layer)154amay be on the sidewall of the second buffer layer108aand may fill the first recess. The heating electrode154amay be between the selection layer106aand the variable resistance layer110a. The heating electrode154amay surround the opening150and may transfer Joule heat to the variable resistance layer110a. Thus, the heating electrode154amay have a resistance greater than a resistance of the first conductive pattern158a.

The capping layer102a, the first buffer layer104a, the selection layer106a, the second buffer layer108a, the variable resistance layer110aand the upper electrode layer112amay be sequentially stacked. This stacked structure, the first conductive pattern158a, and the heating electrode154amay correspond to a first structure.

Oxide layers160and160amay be formed on sidewalls of the capping layer102a, the first conductive pattern158a, the selection layer106a, the variable resistance layer110a, the heating electrode154aand the upper electrode layer112aexposed by the opening150. A first oxide layer160may be on the sidewalls of the capping layer102a, the selection layer106a, the variable resistance layer110a, the upper electrode layer112aand the heating electrode154a, and the first oxide layer160may be an insulator. A second oxide layer160amay be on the sidewall of the first conductive pattern158a, and the second oxide layer160amay have conductivity.

A contact plug164may be on the first and second oxide layers160and160aand the substrate100, and may fill the opening150. The contact plug164may include a metal, e.g., tungsten, aluminum, copper, etc.

The second oxide layer160ahaving conductivity may be between the contact plug164and first conductive pattern158a, so that the contact plug164, the second oxide layer160a, and the first conductive pattern158amay be electrically connected with each other. Also, an upper surface of the first conductive pattern158amay contact the selection layer106a. Thus, when an electrical signal is applied through the contact plug164, the electrical signal may be transferred to the selection layer106avia the second oxide layer160aand the first conductive pattern158a. The first conductive pattern158amay have a ring shape surrounding the contact plug164.

However, the first oxide layer160, which is an insulator, may be formed between the contact plug164and each of sidewalls of the capping layer102a, the selection layer106a, the variable resistance layer110a, the upper electrode layer112aand the heating electrode154a. Thus, the contact plug164and each of the capping layer102a, the selection layer106a, the variable resistance layer110a, the upper electrode layer112aand the heating electrode154amay be electrically isolated with each other.

The heating electrode154amay be electrically isolated with the contact plug164and may have a ring shape surrounding the contact plug164. Thus, the variable resistance layer110a, which is adjacent to the contact plug164, may be selectively heated by the heating electrode154a. The variable resistance layer110amay be locally phase-changed, so that a resistance of a portion of the variable resistance layer110amay be changed.

In operation, first, a selection layer106aand a contact plug164in a selected cell structure may be selected. When an electrical signal is applied through the selected contact plug164, currents may flow to the selection layer106avia a second oxide layer160aand/or a first conductive pattern158ain the cell structure contacting the selected contact plug164. Thus, currents may flow through a heating electrode154aon the selection layer106a, so that a portion of a variable resistance layer110acontacting the heating electrode154amay be heated. For example, a ring shaped portion “A” of the variable resistance layer110aadjacent to an opening150may be selectively heated. In one embodiment, the resistance of the ring shaped portion “A” of the variable resistance layer110acontacting the heating electrode154amay be changeable. For example, the ring shaped portion “A” of the variable resistance layer110amay be crystallized to have a predetermined low resistance. Thus, currents may flow through an upper electrode layer112aon the variable resistance layer110a.

As described above, memory cells may be formed in respective ones of the cell structures10a,20aand30aadjacent to the contact plug164. Thus, the variable resistance memory device may include memory cells in a vertically stacked structure to achieve high integration.

FIGS. 4 to 11illustrate stages of an embodiment of a method for manufacturing a variable resistance memory device, which, for example, may be the variable resistance memory device inFIGS. 1 to 3.

Referring toFIG. 4, a preliminary capping layer102, a preliminary first buffer layer104, a preliminary selection layer106, a preliminary second buffer layer108, a preliminary variable resistance layer110and a preliminary upper electrode layer112may be sequentially stacked on a substrate100to form a preliminary structure10. The preliminary capping layer102, the preliminary first buffer layer104, the preliminary selection layer106, the preliminary second buffer layer108, the preliminary variable resistance layer110, and the preliminary upper electrode layer112may be sequentially and repeatedly stacked on the preliminary structure10to form stacked preliminary structures10,20, and30. A preliminary upper capping layer202may be on the uppermost preliminary structure30. InFIG. 4, the case where the preliminary structures10,20, and30sequentially stacked at three levels are illustrated. The memory cells may be vertically stacked in a different number of levels in another embodiment, four or more levels.

The preliminary capping layer102may include, for example, silicon nitride. The preliminary first buffer layer104may be formed of an insulation material having a predetermined high etching selectivity with respect to an insulation material of the preliminary second buffer layer108. The preliminary first buffer layer104may include, for example, silicon oxide. The preliminary second buffer layer108may include, for example, polysilicon, SiC, SiOC, or another material. The preliminary selection layer106may include, for example, an OTS material.

The preliminary variable resistance layer110may include a chalcogenide-based material, e.g., a GST material, an IST material, a BST material, etc. In some example embodiments, the preliminary variable resistance layer110may include a ferromagnetic material. In some example embodiments, the preliminary variable resistance layer110may include a perovskite material or a transition metal oxide. The preliminary upper electrode layer112may include a metal nitride or a metal silicon nitride.

Referring toFIG. 5, the preliminary upper capping layer202and the stacked preliminary structures10,20, and30may be anisotropically etched to form an opening150therethrough. The opening150may expose an upper surface of the substrate100. The etching process may be, for example, a dry etching process.

Thus, the preliminary capping layer202, the preliminary first buffer layer104, the preliminary selection layer106, the preliminary second buffer layer108, the preliminary variable resistance layer110, and the preliminary upper electrode layer112may be transformed into stacked cell structures10a,20a, and30a. Each of the cell structures10a,20a, and30amay include a capping layer102a, a first buffer layer104a, a selection layer106a, a second buffer layer108a, a variable resistance layer110a, and an upper electrode layer112asequentially stacked. An upper capping layer202amay be on the uppermost cell structure30a.

The capping layer102a, the first buffer layer104a, the selection layer106a, the second buffer layer108a, the variable resistance layer110a, the upper electrode layer112a, and the upper capping layer202amay be exposed by a sidewall of opening150.

Referring toFIG. 6, the second buffer layer108aexposed by the sidewall of the opening150may be partially and isotropically etched to form a first recess152. The etching process may include, e.g., a wet etching or an isotropic dry etching process.

Referring toFIG. 7, a heating electrode layer may be on the upper capping layer202aand the sidewall and a bottom of the opening150to fill the first recess152. The heating electrode layer may include a metal nitride, e.g., titanium nitride (TiNx), tungsten nitride (WNx), tantalum nitride (TaNx), zirconium nitride (ZrNx), etc., or a metal silicon nitride, e.g., titanium silicon nitride (TiSiNx), tungsten silicon nitride (WSiNx), tantalum silicon nitride (TaSiNx), zirconium silicon nitride (ZrSiNx), etc. In some example embodiments, the heating electrode layer may include carbon, e.g., C, CN, TiCN, TaCN, or another material.

The heating electrode layer may be etched so that the heating electrode layer may only remain in the first recess152to form a heating electrode154a. The etching process may include, e.g., a wet etching process or an isotropic dry etching process.

Referring toFIG. 8, the first buffer layer104aexposed by the sidewall of the opening150may be partially and isotropically etched to form a second recess156. The etching process may include, e.g., a wet etching or an isotropic dry etching process.

Referring toFIG. 9, a first conductive layer may be formed on the upper capping layer202aand the sidewall and the bottom of the opening150to fill the second recess156. The first conductive layer may include, e.g., tungsten.

The first conductive layer may be etched so that the first conductive layer may only remain in the second recess156to form a first conductive pattern158a. The etching process may include, e.g., a wet etching process or an isotropic dry etching process.

Thus, the capping layer102a, the first conductive pattern158a, the selection layer106a, the heating electrode154a, the variable resistance layer110a, the upper electrode layer112a, and the upper capping layer202amay be exposed by the sidewall of the opening150.

Referring toFIG. 10, the capping layer102a, the first conductive pattern158a, the selection layer106a, the heating electrode154a, the variable resistance layer110a, the upper electrode112a, and the upper capping layer202aexposed by the sidewall of the opening150may be oxidized to form oxide layers160and160aon the sidewall of the opening150. The oxidation process may include, e.g., a plasma oxidation process or a thermal oxidation process.

In the oxidation process, a first oxide layer160, which may be an insulator, may be formed on the sidewalls of the capping layer102a, the selection layer106a, the variable resistance layer110a, the heating electrode,154a, the upper electrode layer112a, and the upper capping layer202a, and a second oxide layer160ahaving conductivity may be formed on the sidewall of the first conductive pattern158a. In the oxidation process, an oxide layer may be formed on the substrate100. Thus, after the oxidation process, the oxide layer on the substrate100may be selectively removed.

Referring toFIG. 11, a conductive layer may be formed on the first and second oxide layers160and160a, the substrate100, and the upper capping layer202ato fill the opening150. The conductive layer may be planarized until an upper surface of the upper capping layer202amay be exposed. Thus, a contact plug164may be formed on the first and second oxide layers160and160aand substrate100to fill the opening150.

The conductive layer may include a metal, e.g., tungsten, aluminum, copper, etc. The conductive layer may be planarized, for example, by a chemical mechanical polishing (CMP) process or an etch back process.

FIGS. 12 and 13illustrate cross-sectional views of another embodiment of a variable resistance memory device. Referring toFIGS. 12 and 13, the variable resistance memory device may include stacked cell structures11a,21a, and31aon the substrate100. Each of the cell structures11a,21aand31amay include the capping layer102a, the selection layer106a, the second buffer layer108a, the variable resistance layer110a, and the upper electrode layer112asequentially stacked. The cell structures11a,21aand31amay be repeatedly stacked in the first direction. The upper capping layer202amay be formed on the uppermost cell structure31a.

The selection layer106amay include an OTS material.

The second buffer layer108amay include an insulation material having a predetermined high selectivity with respect to the capping layer102a. For example, the second buffer layer108amay include silicon oxide. In some example embodiments, the second buffer layer108amay include, e.g., polysilicon, SiC, SiCN, or another material.

The variable resistance layer110aand the upper electrode layer112amay include materials which are substantially the same as materials of the variable resistance layer and the upper electrode layer, respectively, inFIGS. 1 and 3.

The upper capping layer202aand the stacked cell structures11a,21aand31amay include the opening150therethrough. The opening150may expose an upper surface of the substrate100. A plurality of openings150may be spaced apart from each other at regular or predetermined intervals.

A first recess may be formed between the opening150and a sidewall of the second buffer layer108aadjacent to the opening150. A second recess may be formed between the opening150and a sidewall of the variable resistance layer110aadjacent to the opening150. A third recess may be formed between the opening150and a sidewall of the upper electrode layer112aadjacent to the opening150.

The first recess may have a first width in a horizontal direction. The second recess may have a second width in the horizontal direction less than the first width. Thus, a lower surface of the variable resistance layer110a, a sidewall of the second buffer layer108a, and an upper surface of the selection layer106amay be exposed by the first recess. The third recess may have a third width in the horizontal direction equal to or less than the second width.

A heating electrode180amay be positioned at least in the first recess and may be conformally formed on the lower surface of the variable resistance layer110a, the sidewall of the buffer layer108a, and the upper surface of the selection layer106aexposed by the first recess. For example, the heating electrode180amay be between the selection layer106aand the variable resistance layer110a. Thus, the selection layer106aand the variable resistance layer110amay be connected with each other by the heating electrode180a. However, the heating electrode180amay not contact the upper electrode layer112a.

The heating electrode180amay include a material substantially the same as the material of the heating electrode inFIGS. 1 and 3.

An insulation pattern184may be on the heating electrode180aand may fill the first, second, and third recesses. The insulation pattern184may include, e.g., silicon oxide. For example, the capping layer102a, the selection layer106a, and the insulation pattern184may be exposed by the sidewall of the opening150.

A stacked structure may include the capping layer102a, the selection layer106a, the buffer layer108a, the variable resistance layer110a, and the upper electrode layer112a. The stacked structure and heating electrode180amay form a first structure.

A contact plug186may be formed on the capping layer102a, the selection layer106a, the insulation pattern184and the substrate100, and may sufficiently fill the opening150. The contact plug186may include a metal, e.g., tungsten, aluminum, copper, or another material.

The contact plug186may directly contact the sidewall of the selection layer106a. However, the insulation pattern184may be formed between the contact plug186and each of the sidewalls of the heating electrode180a, the variable resistance layer110a, and the upper electrode112a. Thus, each of the heating electrode180a, the variable resistance layer110a, and the upper electrode112amay be electrically isolated with the contact plug186.

The heating electrode180amay be isolated with the contact plug186and may have a ring shape surrounding the contact plug186. For example, the variable resistance layer110aadjacent to the contact plug186may be selectively heated through the heating electrode180a. The variable resistance layer110amay be locally phase-changed, in order to change a resistance of a portion of variable resistance layer110a.

In operation, first, a selection layer106aand a contact plug164in a selective cell structure may be selected. When an electrical signal is applied through a selected contact plug186, currents may flow to the selection layer106ain the selective cell structure contacting the selected contact plug186. Thus, currents may flow through a heating electrode180aon the selection layer106a, in order to heat a portion of a variable resistance layer110acontacting the heating electrode180a. Thus, currents may flow through an upper electrode layer112aon the variable resistance layer110a.

As described above, memory cells may be formed at respective cell structures adjacent to the contact plug186. The variable resistance memory device may therefore have a vertically stacked arrangement of memory cells to achieve high integration.

FIGS. 14 to 19illustrate stages of another embodiment of a method for manufacturing the variable resistance memory device, e.g., the variable resistance memory device inFIGS. 12 to 13.

Referring toFIG. 14, the preliminary capping layer102, the preliminary selection layer106, the preliminary second buffer layer108, the preliminary variable resistance layer110, and the preliminary upper electrode layer112may be sequentially stacked on the substrate100to form a preliminary structure11. The preliminary capping layer102, the preliminary selection layer106, the preliminary second buffer layer108, the preliminary variable resistance layer110, and the preliminary upper electrode layer112may be sequentially and repeatedly stacked on the preliminary structure11to form stacked preliminary structures11,21, and31. The preliminary upper capping layer202may be formed on the uppermost preliminary structure31.

The preliminary capping layer102, the preliminary selection layer106, the preliminary second buffer layer108, the preliminary variable resistance layer110, the preliminary upper electrode layer112, and the preliminary upper capping layer202may include, for examples, materials substantially the same as materials of the preliminary capping layer, the preliminary selection layer, the preliminary buffer layer, the preliminary variable resistance layer, the preliminary upper electrode layer, and the preliminary upper capping layer, respectively, inFIG. 4.

Referring toFIG. 15, the preliminary upper capping layer202and the stacked preliminary structures11,21, and31may be anisotropically etched to form an opening150therethrough. The opening150may expose an upper surface of the substrate100. The etching process may include, for example, a dry etching process.

The preliminary second buffer layer108and the preliminary variable resistance layer110exposed by a sidewall of the opening150may be partially and isotropically etched to form a first recess170and a second recess172. The first recess170may be formed by partially etching the preliminary second buffer layer108. The second recess172may be formed by partially etching the preliminary variable resistance layer110. In example embodiments, the preliminary second buffer layer108may be etched more quickly than the preliminary variable resistance layer110during the isotropic etching process. In some example embodiments, the first recess170and the second recess172may be formed by different isotropic etching processes. Thus, the first recess170may have a first width in the horizontal direction, and the second recess172may have a second width in the horizontal direction less than the first width. The isotropic etching process of the preliminary second buffer layer108and preliminary variable resistance layer110may include, e.g., a wet etching process or an isotropic dry etching process.

Thus, the preliminary capping layer102, the preliminary selection layer106, the preliminary second buffer layer108, the preliminary variable resistance layer110, and the preliminary upper electrode layer112may be transformed into a capping layer102a, a selection layer106a, a second buffer layer108a, a variable resistance layer110a, and an upper electrode layer112a, respectively, including the opening150and the first and second recesses170and172. An upper surface of the selection layer106a, a sidewall of the second buffer layer108a, and a bottom of the variable resistance layer110amay be exposed by the first recess170. A sidewall of the variable resistance layer110aand a bottom of the upper electrode layer112amay be exposed by the second recess172.

Referring toFIG. 16, a heating electrode layer180may be formed on the sidewalls of the openings150and first and second recesses170and172and upper surfaces of the substrate100and the upper capping layer202a. The heating electrode layer180may be formed, for example, of a material substantially the same as the material of the heating electrode layer illustrated inFIG. 7.

In example embodiments, the heating electrode layer180may be conformally formed on inner walls of the first and second recesses170and172. In some example embodiments, the heating electrode layer180may fill the first recess170.

An insulation layer may be formed on the heating electrode layer180to fill the first and second recesses170and172. The insulation layer includes for example, silicon oxide, and may be formed, for example, by a CVD process or an ALD process. The insulation layer may be etched so that the insulation layer may only remain in the first recess170to form a first insulation pattern182. The etching process may include, e.g., a wet etching process or an isotropic dry etching process.

Referring toFIG. 17, the heating electrode layer180on the sidewall of the opening150and the surface of the substrate100may be etched to form a heating electrode180a. The etching process of the heating electrode layer180may include, e.g., a wet etching process or an isotropic dry etching process.

The heating electrode180amay be conformally formed on the sidewall of the second buffer layer108a, the bottom of the variable resistance layer110a, and the upper surface of the selection layer106ain the first recess170. In example embodiments, the heating electrode180amay be also formed on a lower sidewall of the variable resistance layer110a.

During etching the heating electrode layer180, the upper electrode layer112aexposed by the opening150may be partially etched to form a third recess174. In example embodiments, the third recess174may have a third width in the horizontal direction equal to or less than the second width.

Referring toFIG. 18, an insulation layer may be formed on the sidewall of the opening150and the surfaces of the substrate100and the upper capping layers202ato fill the first, second and third recesses170,172and174. The insulation layer may be etched so that the insulation layer only remains in the first, second, and third recesses170,172, and174to form a second insulation pattern. The second insulation pattern may include, e.g., silicon oxide.

The first and second insulation patterns may be merged into one insulation pattern184. The etching process of the insulation layer may include, e.g., a wet etching process or an isotropic dry etching process.

Thus, the capping layer102a, the selection layer106a, and the insulation pattern184may be exposed by the sidewall of the opening150. The insulation pattern184may cover the sidewalls of the heating electrode180a, the variable resistance layer110a, and the upper electrode layer112a

Referring toFIG. 19, a conductive layer may be formed on the capping layer102a, the selection layer106a, the insulation pattern184, the substrate100, and the upper capping layer202ato sufficiently fill the opening150. The conductive layer may be planarized until the upper surface of the upper capping layer202ais exposed to form a contact plug186filling the opening150. The contact plug186may directly contact the selection layer106aand may be electrically isolated with the heating electrode180a, the variable resistance layer110a, and the upper electrode layer112a.

FIGS. 20 and 21are cross-sectional views illustrating another embodiment of a variable resistance memory device.FIG. 22illustrates an embodiment of a plan view of the variable resistance memory device.

Referring toFIGS. 20 and 21, the variable resistance memory device may include stacked cell structures12a,22a, and32aon the substrate100. Each of the cell structures12a,22a, and32amay include the capping layer102a, a lower electrode layer130a, a channel layer132a, a buffer layer134a, the variable resistance layer110a, and the upper electrode layer112asequentially stacked. The cell structures12a,22a, and32amay be stacked in the first direction. The number of stacked cell structures may vary among different embodiments.

The buffer layer134amay include an insulation material having a predetermined high etching selectivity with respect to each of the capping layer102aand the channel layer132a. The buffer layer134amay include, e.g., silicon oxide, SiC, SiOC, etc.

The variable resistance layer110aand the upper electrode layer112amay include materials substantially the same as materials of the variable resistance layer and the upper electrode layer, respectively, illustrated inFIGS. 1 to 3.

The stacked cell structures12a,22a, and32amay include the opening150therethrough. The opening150may expose an upper surface of the substrate100. A plurality of openings150may be spaced apart in regular or predetermined intervals.

A first recess may be formed between the opening150and a sidewall of the buffer layer134aadjacent to the opening150. A heating electrode250may be formed on the sidewall of the buffer layer134ato fill the first recess. The heating electrode250may be between the channel layer132aand the variable resistance layer110a, so that the channel layer132aand the variable resistance layer110amay be connected with each other by the heating electrode250. The heating electrode250may include a material substantially the same as the material of the heating electrode inFIGS. 1 to 3.

A gate insulation layer350may be formed on a sidewall of the opening150. For example, the gate insulation layer350may contact the capping layer102a, the lower electrode layer130a, the channel layer132a, the heating electrode250, the variable resistance layer110a, and the upper electrode layer112aexposed by the opening150. In example embodiments, the gate insulation layer350may include, e.g., silicon oxide. In some example embodiments, the gate insulation layer350may include a metal oxide having a dielectric constant higher than silicon oxide.

A gate electrode360may be formed on the gate insulation layer350to sufficiently fill the opening150. The gate electrode360may have a pillar shape or another shape. The gate electrode360may be formed through the channel layer132a, so that a transistor including the channel layer132a, the gate insulation layer350, and the gate electrode360may be formed at each level. The gate electrode360may serve as a common gate of the transistors and may include a metal, e.g., tungsten, aluminum, copper, or another material.

A first wiring electrically connected with the lower electrode layer130aand a second wiring electrically connected with the upper electrode layer112amay be further formed. Thus, electrical signals may be independently applied to the lower electrode layer130aand the upper electrode layer112aformed at each level.

In example embodiments, edge portions of a plurality of lower electrode layers130amay have a staircase shape. Contact plugs362and conductive patterns may be formed on the edge portions of the lower electrode layers130a. Also, edge portions of a plurality of the upper electrode layers112amay have a staircase shape. The contact plugs362and the conductive patterns may be formed on the edge portions of the upper electrode layers112a.

In operation, first, an electrical signal is applied to a gate electrode360in a selected cell structure to turn on a transistor corresponding to the selected cell structure. When an electrical signal is applied to a lower electrode layer130ain the selected cell structure, currents may flow to a heating electrode250through the turned-on transistor. Thus, a portion of a variable resistance layer110amay be heated by the heating electrode250. Currents may flow through an upper electrode layer112aon the variable resistance layer110a.

Thus, the cell structure formed at each level adjacent to the gate electrode360may serve as a memory cell. A highly integrated memory device may therefore be achieved through the vertically stacked arrangement of the memory cells.

FIGS. 23 to 24illustrate stages of an embodiment of a method for manufacturing a variable resistance memory device, which, for example, may be the variable resistance memory device shown inFIGS. 20 to 22.

Referring toFIG. 23, the preliminary capping layer102, a preliminary lower electrode layer130, a preliminary channel layer132, a preliminary buffer layer134, the variable resistance layer110, and the preliminary upper electrode layer112may be sequentially stacked on the substrate100to form a preliminary structure12. The preliminary capping layer102, the preliminary lower electrode layer130, the preliminary channel layer132, the preliminary buffer layer134, the variable resistance layer110, and the preliminary upper electrode layer112may be sequentially and repeatedly stacked on the preliminary structure12to form stacked preliminary structures12,22, and32. The preliminary upper capping layer202may be formed on the uppermost preliminary structure32.

The preliminary capping layer102, the variable resistance layer110, and the preliminary upper electrode layer112may include materials substantially the same as materials of the preliminary capping layer, the variable resistance layer, and the preliminary upper electrode layer, respectively, illustrated inFIG. 4. The preliminary lower electrode layer130, the preliminary buffer layer134, and the preliminary channel layer132may include materials substantially the same as materials of the lower electrode layer, the buffer layer, and the channel layer, respectively, inFIGS. 20 to 22.

Referring toFIG. 24, the preliminary upper capping layer202and the stacked preliminary structures12,22and32may be anisotropically etched to form a plurality of openings150therethrough. Each of the openings150may expose an upper surface of the substrate100. The etching process may include, for example, a dry etching process.

The preliminary buffer layer134exposed by the sidewalls of the openings150may be partially and isotropically etched to form a first recess. The etching process may include, e.g., a wet etching process or an isotropic dry etching process.

Thus, a cell structure including the capping layer102a, a lower electrode layer130a, a channel layer132a, a buffer layer134a, the variable resistance layer110a, and the upper electrode layer112asequentially stacked may be formed on the substrate100.

A heating electrode layer may be formed on sidewalls of the opening150and the first recess and upper surfaces of the substrate100and the upper capping layer112a. The heating electrode layer may include a material substantially the same as the material of the heating electrode layer illustrated inFIG. 7. The heating electrode layer may be etched so that the heating electrode layer remains only in the first recess to form a heating electrode250. The etching process may include, e.g., a wet etching process or an isotropic dry etching process.

Referring again toFIGS. 20 to 22, a gate insulation layer350may be formed on the sidewall of the opening150and the upper surface of the upper capping layer202a. A gate electrode layer may be formed on the gate insulation layer to fill the opening150. The gate electrode layer may be planarized until the upper surface of the upper capping layer202amay be exposed to form a gate electrode360. The planarization process may include, for example, a CMP process or an etched back process.

FIG. 25illustrates a cross-sectional view of another embodiment of a variable resistance memory device. Referring toFIG. 25, the variable resistance memory device may include a cell structure13aon the substrate100. The cell structure13amay include a capping layer402a, a lower electrode layer404a, a first insulation layer408a, and a variable resistance layer410asequentially stacked. A plurality of cell structures13a,23aand33amay be stacked in the first direction. The number of stacked cell structures13a,23a, and33amay vary in different embodiments. The upper capping layer202amay be formed on the uppermost cell structure33a.

The capping layer402aand variable resistance layer410amay include, for example, materials substantially the same as the materials of the capping layer and the variable resistance layer, respectively, illustrated inFIGS. 1 to 3. The lower electrode layer404amay include, for example, a material substantially the same as the material of the lower electrode layer illustrated inFIGS. 20 to 22.

The upper capping layer202aand the cell structures13a,23aand33amay include a plurality of openings150therethrough. Each of the openings150may expose an upper surface of the substrate100. A first recess may be formed between the opening150and a sidewall of the first insulation layer408aadjacent to the opening150. A heating electrode406amay be formed in the first recess. The heating electrode406amay be spaced apart from the opening150and may surround the opening150.

A second recess may be formed between the opening150and sidewalls of the heating electrode406aand the lower electrode layer404aadjacent to the opening150. An insulation pattern420may be formed in the second recess. The insulation pattern420may be formed on the sidewalls of the heating electrode406aand the lower electrode layer404a. The first insulation layer408aand the insulation pattern420may include, e.g., silicon oxide.

A selective pattern450may be formed on a sidewall of the opening150and may have a cylindrical shape or another shape. The selective pattern450may include, for example, a material substantially the same as the material of the lower electrode layer illustrated inFIGS. 1 to 3.

A contact plug452may be formed on the selective pattern450to sufficiently fill the opening150. The contact plug452may serve as an upper electrode.

In operation, first, an electrical signal may be applied to a lower electrode layer404ain a selective cell structure. Also, currents may flow to a heating electrode406avia the lower electrode layer404a. Thus, a portion of a variable resistance layer410amay be heated by the heating electrode406a, so that currents may flow through the variable resistance layer410a. The selective pattern450may be selected, so that currents may flow through the selective pattern450and the contact plug452.

FIGS. 26 and 27are cross-sectional views illustrating stages of another embodiment of a method for manufacturing the variable resistance memory device, which, for example, may be the variable resistance memory device inFIG. 25.

Referring toFIG. 26, a preliminary capping layer, a preliminary lower electrode layer, a preliminary first insulation layer, and a preliminary variable resistance layer may be sequentially stacked on the substrate100to form a preliminary structure. The preliminary capping layer, the preliminary lower electrode layer, the preliminary selection layer, the preliminary second buffer layer, the preliminary first insulation layer, and the preliminary variable resistance layer may be sequentially and repeatedly stacked on the preliminary structure to form stacked preliminary structures. A preliminary upper capping layer may be formed on an uppermost preliminary structure.

The preliminary upper capping layer and the stacked preliminary structures may be anisotropically etched to form a plurality of openings150therethrough. Each of the openings may expose an upper surface of the substrate100.

The preliminary first insulation layer and the preliminary lower electrode layer exposed by sidewalls of the openings150may be partially and isotropically etched to form first and second recesses190and192. The first recess190may be formed by partially etching the preliminary first insulation layer. The second recess192may be formed by partially etching the preliminary lower electrode layer. In example embodiments, during the isotropic etching process, the preliminary first insulation layer may be etched more quickly than the preliminary lower electrode layer. In some example embodiments, the first recess190and the second recess192may be formed by different isotropic etching processes.

Thus, the first recess190may have a first width in the horizontal direction, and the second recess192may have a second width in the horizontal direction less than the first width. The etching process of the preliminary first insulation layer and the preliminary lower electrode layer may include a wet etching process or an isotropic dry etching process.

Thus, the preliminary capping layer, the preliminary lower electrode layer, the preliminary first insulation layer, and the preliminary variable resistance layer may be transformed into a capping layer, a lower electrode layer, a first insulation layer, and a variable resistance layer, respectively, having the openings150therethrough and the first and second recesses190and192.

Referring toFIG. 27, a heating electrode layer may be formed on sidewalls of the opening150and the first and second recesses190and192and upper surfaces of the substrate100and the upper capping layer202a. The heating electrode layer may be formed, for example, of a material substantially the same as materials of the heating electrode layer illustrated inFIG. 7. In example embodiments, the heating electrode layer may partially fill the first recess190. The heating electrode layer may be etched so that the heating electrode layer may remain only in the first recess190to form a heating electrode406a.

An insulation layer may be formed on the sidewalls of the opening150, the second recess192and the heating electrode406aand the upper surface of the substrate100and the upper capping layer202a. The insulation layer may be formed of, e.g., silicon oxide. In example embodiments, the insulation layer may fill second recess192.

The insulation layer may be etched so that the insulation layer may remain in the second recess192to form an insulation pattern420. The insulation pattern420may cover the sidewalls of the lower electrode layer404aand the heating electrode406a.

Referring again toFIG. 25, a selection layer may be formed on the sidewall of the opening150and the upper surfaces of the substrate100and the upper capping layer202a. The selection layer may be isotropically etched to form a selective pattern450on the sidewall of the opening150. A contact plug452may be formed on the selective pattern450to sufficiently fill the opening150.

FIG. 28is a cross-sectional view illustrating another embodiment of a variable resistance memory device. Referring toFIG. 28, the variable resistance memory device may include a cell structure14aon the substrate100. The cell structure14amay include a plurality of insulation layers422aand a plurality of lower electrode layers424athat are sequentially and alternately stacked. A plurality of cell structures14a,24a, and34amay be stacked in the first direction. An upper capping layer202amay be formed on the uppermost cell structure34a.

The insulation layer422amay include, e.g., silicon oxide or silicon nitride.

The upper capping layer202aand the cell structures14a,24a, and34amay include a plurality of openings150. Each of the openings150may expose an upper surface of the substrate100. A first recess may be formed between the opening150and a sidewall of the lower electrode layer424aadjacent to the opening150. A heating electrode426aand a variable resistance pattern428amay be stacked in the horizontal direction to fill the first recess. Thus, the heating electrode426aand the variable resistance pattern428amay surround the opening150. The heating electrode426amay contact the lower electrode layer424a, and the variable resistance pattern428amay be exposed by the opening150.

A selective pattern450may be formed on a sidewall of the opening150and may have a cylindrical shape or another shape.

A contact plug452may be formed on the selective pattern450to sufficiently fill the opening150. The contact plug452may serve as an upper electrode.

In operation, first, an electrical signal may be applied to a lower electrode layer424ain a selective cell structure for operation. Also, currents may flow to a heating electrode406avia the lower electrode layer424a. Thus, a variable resistance layer410amay be heated by the heating electrode406a, so that current may flow through the variable resistance layer410a. The selective pattern450may be selected, so that currents may flow through the selective pattern450and the contact plug452.

FIGS. 29 and 30are cross-sectional views illustrating stages of another embodiment of a method of manufacturing a variable resistance memory device, which, for example, may be the variable resistance memory device shown inFIG. 28.

Referring toFIG. 29, a preliminary insulation layer and a preliminary lower electrode layer may be sequentially stacked on the substrate100to form a preliminary structure. The preliminary insulation layer and the preliminary lower electrode layer may be sequentially and repeatedly stacked on the preliminary structure to form stacked preliminary structures. A preliminary upper capping layer may be formed on an uppermost preliminary structure. The preliminary upper capping layer and the stacked preliminary structures may be anisotropically etched to form an opening150therethrough. The opening150may expose an upper surface of the substrate100. The preliminary lower electrode layer exposed by a sidewall of the opening150may be partially and isotropically etched to form a recess194.

Thus, stacked cell structures including an insulation layer422aand a lower electrode layer424asequentially stacked may be formed on the substrate100.

Referring toFIG. 30, a heating electrode layer may be formed on sidewalls of the opening150and the recess194and upper surfaces of the substrate100and the upper insulation layer203a. The heating electrode layer may be formed, for example, of a material substantially the same as materials of the heating electrode layer inFIG. 7. In example embodiments, the heating electrode layer may partially fill recess194.

The heating electrode layer may be partially etched to form a heating electrode426a. The heating electrode426amay partially fill the recess194.

A variable resistance layer may be formed on the sidewall of the opening150and the heating electrode426aand surfaces of the substrate100and the upper insulation layer203a. The variable resistance layer may be etched so that the variable resistance layer may remain only in the recess194to form a variable resistance pattern428aon the heating electrode426a.

Referring again toFIG. 28, a selection layer may be formed on the sidewall of the opening150and upper surfaces of the substrate100and the upper insulation layer203a. The selection layer may be isotropically etched to form a selective pattern450on the sidewalls of the opening150. A contact plug452may be formed on the selective pattern450to sufficiently fill the opening150.

FIG. 31illustrates another embodiment of a variable resistance memory device which may include a cell structure15aon the substrate100. The cell structure15amay include the insulation layer422a, a lower electrode layer430, and a heating electrode layer432sequentially stacked. A plurality of cell structures15a,25aand35amay be stacked in the first direction. The number of stacked cell structures15a,25aand35amay vary in different embodiments.

The upper insulation layer203amay be on an uppermost cell structure. The insulation layer422amay include, e.g., silicon oxide or silicon nitride. The upper insulation layer203aand the cell structures15a,25aand35amay include an opening150therethrough. The opening150may expose an upper surface of the substrate100.

A first recess may be formed between the opening150and a sidewall of the lower electrode layer430adjacent to the opening150. A second recess may be formed between the opening150and a sidewall of the heating electrode layer432adjacent to the opening150.

An insulation pattern434may be formed in the first recess and may contact a sidewall of the lower electrode layer430. A variable resistance pattern436may be formed on sidewalls of the insulation layer422aand the heating electrode layer432to fill the second recess. Thus, the variable resistance pattern436may surround the opening150. The variable resistance pattern436may be exposed by the opening150.

A selective pattern450may be formed on the sidewall of the opening150and may have a cylindrical shape or another shape. A contact plug452may be formed on the selective pattern450to sufficiently fill the opening150. The contact plug452may serve as an upper electrode.

Operation of this embodiment of the variable resistance memory device may be substantially the same as the operation illustrated with reference toFIG. 28.

FIG. 32is a cross-sectional view illustrating stages of another embodiment of a method for manufacturing a variable resistance memory device, which, for example, may be the variable resistance memory device shown inFIG. 31.

Referring toFIG. 32, a preliminary insulation layer, a preliminary lower electrode layer, and preliminary heating layer may be sequentially stacked on the substrate100to form a preliminary structure. The preliminary insulation layer, the preliminary lower electrode layer, and the preliminary heating layer may be sequentially and repeatedly stacked on the preliminary structure to form stacked preliminary structures. An upper insulation layer203amay be formed on the uppermost preliminary structure. The upper insulation layer203aand the stacked preliminary structures may be anisotropically etched to form an opening150therethrough. The opening150may expose an upper surface of the substrate100. The preliminary lower electrode layer and the heating electrode layer exposed by a sidewall of the opening150may be partially and isotropically etched to form first and second recesses, respectively.

Thus, stacked cell structures15a,25aand35aincluding an insulation layer422a, a lower electrode layer430, and a heating electrode layer432sequentially stacked may be formed on the substrate100. An insulation layer may be formed on sidewalls of the opening150and first and second recesses and upper surfaces of the substrate100and the upper insulation layer203a. The insulation layer may be partially etched to form an insulation pattern434on the sidewall of lower electrode layer430to partially fill the first recess.

Referring again toFIG. 31, a variable resistance layer may be formed on the insulation layer422a, the insulation pattern434, and the heating electrode layer432exposed by the opening150and the surfaces of the substrate100and the upper insulation layer203ato fill the second recess. The variable resistance layer may be partially etched to form a variable resistance pattern436on the sidewalls of the heating electrode layer432and the insulation pattern434to fill the second recess.

A selection layer may be formed on the sidewall of the opening150and the surfaces of the substrate100and the upper insulation layer203a. The selection layer may be anisotropically etched to form a selective pattern450on the sidewall of the opening150. A contact plug452may be formed on the selective pattern450to sufficiently fill the opening150.

In accordance with one or more of the aforementioned embodiments, the variable resistance memory device may include a vertically stacked arrangement of memory cells to achieve high integration.