Nonvolatile memory device with a metal-insulator-metal (MIM) capacitor in a substrate and integration schemes

A nonvolatile memory device is provided. The nonvolatile memory device comprises a floating gate arranged over a first active region, whereby the first active region is in an active layer of a substrate. A metal-insulator-metal (MIM) capacitor may be provided laterally adjacent to the floating gate, whereby a portion of the metal-insulator-metal capacitor is in the active layer. A contact pillar may connect a first electrode of the metal-insulator-metal capacitor to the floating gate.

FIELD OF THE INVENTION

The disclosed embodiments relate generally to nonvolatile memory devices, and more particularly, to nonvolatile memory devices with a metal-insulator-metal (MIM) capacitor in a substrate and integration schemes.

BACKGROUND

A nonvolatile memory device retains stored data even if power is turned off. An example of a nonvolatile memory device includes electrically erasable programmable read only memory (EEPROM) and flash EEPROM. In typical flash memory architecture, a floating gate may be used to store charges. The floating gate may be arranged over an active region such as a p-well. A source region may be formed in the p-well adjacent to a first side of the floating gate and a drain region may be formed in the p-well adjacent to a second side of the floating gate opposite to the first side. A metal-insulator-metal capacitor may be used to bias the floating gate. The metal-insulator-metal capacitor is in a back-end-of line (BEOL) layer over the floating gate. The term “back-end-of line” may refer to a portion of a semiconductor processing that creates conductive lines carrying power and signals between devices such as transistors to a semiconductor chip interface.

A coupling ratio of the nonvolatile memory device with the metal-insulator-metal capacitor in the back-end-of-line layer over the floating gate is insufficient due to space constraints in the back-end-of-line layer. The issue is further aggravated for advanced technology nodes as feature sizes of the nonvolatile memory device shrinks. The low coupling ratio leads to higher program and erase voltages and a shorter device lifetime. Thus, there is a need to overcome the challenges mentioned above.

SUMMARY

In an aspect of the present disclosure, a nonvolatile memory device is provided. The nonvolatile memory device comprises a floating gate arranged over a first active region, whereby the first active region may be arranged in an active layer of a substrate. A metal-insulator-metal capacitor may be arranged laterally adjacent to the floating gate, whereby a portion of the metal-insulator-metal capacitor may be in the active layer. A contact pillar may connect a first electrode of the metal-insulator-metal capacitor to the floating gate.

In another aspect of the present disclosure, an array of nonvolatile memory devices is provided. The array of nonvolatile memory devices comprises a first active region and a second active region arranged in an active layer of a substrate. A first isolation region and a second isolation region adjacent to the first isolation region may be arranged between the first active region and the second active region. A first array of floating gates may be arranged over the first active region and a second array of floating gates may be arranged over the second active region. A metal-insulator-metal capacitor may be arranged laterally adjacent to the floating gates, whereby a lower portion of the metal-insulator-metal capacitor may be arranged in the first isolation region in the active layer and a first dielectric layer in the substrate. A contact pillar may connect a first electrode of the metal-insulator-metal capacitor to each floating gate.

In yet another aspect of the present disclosure, a method of fabricating a nonvolatile memory device is provided. The method comprises providing a floating gate arranged over a first active region, whereby the first active region may be arranged in an active layer of a substrate. A contact pillar may be provided over the floating gate. A metal-insulator-metal capacitor may be provided laterally adjacent to the floating gate, whereby a portion of the metal-insulator-metal capacitor may be arranged in the active layer and a first electrode of the metal-insulator-metal capacitor may be connected to the floating gate by the contact pillar.

Numerous advantages may be derived from the embodiments described below. The embodiments provide a nonvolatile memory device with a high coupling ratio. A second electrode of the metal-insulator-metal capacitor may be connected to an input terminal. The term “coupling ratio” may refer to the voltage transfer capability from the metal-insulator-metal capacitor to the floating gate. A lower portion of the metal-insulator-metal capacitor may be arranged in a first isolation region. An upper portion of the first isolation region may be surrounded by a second isolation region adjacent to the first active region leading to a compact nonvolatile memory device. The second isolation region may be a shallow trench isolation region. An extension portion of the metal-insulator-metal capacitor may be arranged over an inter metal dielectric (IMD) layer over the floating gate leading to a high capacitance value and a high coupling ratio. The metal-insulator-metal capacitor may extend across at least a length of an active region providing a high coupling ratio for the nonvolatile memory device. A lower portion of the metal-insulator-metal capacitor may be separated from a base layer of the substrate by a portion of the first dielectric layer. Thereby the metal-insulator-metal capacitor is electrically insulated from the base layer of the substrate, leading to a stable device operation.

For simplicity and clarity of illustration, the drawings illustrate the general manner of construction, and certain descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the discussion of the described embodiments of the devices. Additionally, elements in the drawings are not necessarily drawn to scale. For example, the dimensions of some of the elements in the drawings may be exaggerated relative to other elements to help improve understanding of embodiments of the devices. The same reference numerals in different drawings denote the same elements, while similar reference numerals may, but do not necessarily, denote similar elements.

DETAILED DESCRIPTION

The following detailed description is exemplary in nature and is not intended to limit the devices or the application and uses of the devices. Furthermore, there is no intention to be bound by any theory presented in the preceding background of the devices or the following detailed description.

FIG. 1Ais a top down view of a nonvolatile memory device array100, according to an embodiment of the disclosure. Referring toFIG. 1A, a nonvolatile memory device array100is provided. The nonvolatile memory device array100may comprise a first active region102aand a second active region102b. A first array of floating gates112amay be arranged over the first active region102aand a second array of floating gates112bmay be arranged over the second active region102b. A first doped region106may be arranged in the first102aand the second102bactive regions next to a first side116of the first array112aand the second array112bof floating gates, respectively. A second doped region110may be arranged in the first102aand the second102bactive regions next to a second side118of the first array112aand the second array112bof floating gates, respectively. The first side116of the floating gates112aand112bmay be opposite to the second side118. For example, the first doped region106may be a source, the second doped region110may be a drain and a floating gate112aor112bmay be a charge storage region for a nonvolatile memory transistor. The term “floating gate” may refer to a gate electrode that is electrically isolated from an input terminal and may be capacitively coupled to the input terminal. There may not be direct current flowing from the input terminal to the floating gate during a reading operation.

A contact114may be arranged over the first doped region106and a contact124may be arranged over the second doped region110for connection to external input terminals. A metal-insulator-metal (MIM) capacitor108may be provided laterally adjacent to the floating gates112aand112b, whereby a lower portion of the metal-insulator-metal capacitor108may be arranged in a substrate. For simplicity, the substrate is not shown inFIG. 1A. An extension portion of the metal-insulator-metal capacitor108is depicted as a dashed outline. The extension portion of the metal-insulator-metal capacitor108may at least partially overlap laterally with a portion of the first102aand the second102bactive regions and the first array112aand the second array112bof floating gates. In one embodiment, the metal-insulator-metal capacitor108may extend across at least part of a length of the first102aand the second102bactive regions thereby providing a nonvolatile memory device array100with a high coupling ratio. In another embodiment, the metal-insulator-metal capacitor108may extend beyond the length of the first102aand the second102bactive regions. A contact pillar120aand120bmay connect a first electrode122of the metal-insulator-metal capacitor108to the first array112aand the second array112bof floating gates, respectively. A contact150may couple a second electrode128of the metal-insulator-metal capacitor108to an external input terminal.

FIG. 1Bis a cross-section view of the nonvolatile memory device array100shown inFIG. 1Ataken along section line A-A′, according to an embodiment of the disclosure. Referring toFIG. 1B, the first active region102aand the second active region102bmay be in an active layer158of a substrate178. A first isolation region152aand a second isolation region156amay be in the active layer158of the substrate178between the first102aand the second102bactive regions. The first isolation region152amay extend to a first dielectric layer160of the substrate178in one embodiment. In another embodiment, the first isolation region152amay extend to an upper portion of the first dielectric layer160. A lower portion of the metal-insulator-metal capacitor108may be positioned in the first isolation region152a. In one embodiment, the lower portion of the capacitor108may extend vertically within the thickness of the active layer158. In another embodiment, the lower portion of the capacitor108may extend vertically below the active layer158into the first dielectric layer160of the substrate178in one embodiment and in an upper portion of the first dielectric layer160of the substrate178.

The first isolation region152amay surround the lower portion of the metal-insulator-metal capacitor108. In one embodiment, the first isolation region152amay surround a side surface and a bottom surface of the lower portion of the metal-insulator-metal capacitor108. In an alternative embodiment, the first isolation region152amay surround the side surface of the lower portion of the metal-insulator-metal capacitor108and the bottom surface of the metal-insulator-metal capacitor108may be in contact with the first dielectric layer160of the substrate178. The second isolation region156amay be adjacent to an upper portion of the first isolation region152a. In one embodiment, the second isolation region156amay partially surround an upper portion of the first isolation region152a. In another embodiment, the second isolation region156amay completely surround the upper portion of the first isolation region152a. The first isolation region152amay be deep trench isolation (DTI) and the second isolation region156amay be shallow trench isolation (STI). The first isolation region152amay be within the second isolation region156a. The lower portion of the metal-insulator-metal capacitor108does not take up additional lateral space as it may be in the first isolation region152a. In one embodiment, the first152aand the second156aisolation regions may be between the lower portion of the metal-insulator-metal capacitor108and the first active region102abelow the first array of floating gates112aand the second active region102bbelow the second array of floating gates112b.

Isolation regions152and156may be laterally adjacent to the first active region102aor the second active region102b. The isolation region156may be adjacent to an upper portion of the isolation region152. The isolation region156may be a shallow trench isolation and the isolation region152may be a deep trench isolation. In an alternative embodiment, a lower portion of the metal-insulator-metal capacitor108may be arranged in the isolation region152.

The substrate178may comprise a base layer162, the first dielectric layer160over the base layer162and the active layer158over the first dielectric layer160. In one embodiment, the base layer162may be made of a suitable semiconductor material, for example silicon. In one embodiment, the first dielectric layer160may be made of a suitable dielectric material, for example silicon dioxide. In one embodiment, the active layer158may be made of a suitable semiconductor material, for example silicon. In one embodiment, the substrate178may be silicon on insulator (SOI) substrate. In a preferred embodiment, the lower portion of the first dielectric layer160and a portion of the first isolation region152may be between the metal-insulator-metal capacitor108and the base layer162of the substrate178to electrically insulate the metal-insulator-metal capacitor108from the base layer162of the substrate leading to a stable device operation. In an alternative embodiment, the lower portion of the first dielectric layer160may be between the metal-insulator-metal capacitor108and the base layer162of the substrate178. In yet another embodiment, a portion of the first isolation region152amay be between the metal-insulator-metal capacitor108and the base layer162of the substrate178.

Inter layer dielectric (ILD) layer166amay be provided over the substrate178. An upper portion of the metal-insulator-metal (MIM) capacitor108may extend vertically in the inter layer dielectric layer166aabove the substrate178. Inter metal dielectric (IMD) layer166bmay be provided over the inter layer dielectric layer166a. An extension portion of the upper portion of the metal-insulator-metal capacitor108may extend laterally in the inter metal dielectric layer166babove the inter layer dielectric layer166aand at least partially overlap laterally with the first112aand the second112barrays of floating gates.

A first electrode122of the metal-insulator-metal capacitor108may be arranged on a side surface and a bottom surface of the metal-insulator-metal capacitor108. For example, the first electrode122may be conformally formed on at least the side surfaces and the bottom surface of an opening104through the first isolation region152aand the inter layer dielectric layer166a. A dielectric layer126may be arranged over the first electrode122of the metal-insulator-metal capacitor108. The dielectric layer126may be made of a high dielectric constant (high-k) dielectric layer in a preferred embodiment. The term “high dielectric constant dielectric layer” may refer to a layer of dielectric material with a dielectric constant greater than 20. In an alternative embodiment, the dielectric layer126may be made of silicon dioxide or silicon nitride (Si3N4). A second electrode128of the metal-insulator-metal capacitor108may be arranged over the high dielectric constant dielectric layer126. A contact pillar120amay connect the first electrode122of the metal-insulator-metal capacitor108to the first array of floating gates112a. A contact pillar120bmay connect the first electrode122of the metal-insulator-metal capacitor108to the second array of floating gates112b.

TABLE 1 illustrates an exemplary set of biasing conditions for the nonvolatile memory device array100shown inFIGS. 1A and 1B. Programming may be by hot carrier injection. For example, during program, a voltage of approximately 12 V may be applied to the metal-insulator-metal capacitor108. 0 V may be applied to the first doped region106or the source of a selected nonvolatile memory transistor. A voltage of approximately 12 V may be applied to the second doped region110or the drain of a selected nonvolatile memory transistor. 0 V may be applied to the substrate178through the base region162. The programming conditions create a strong vertically oriented electric field in a channel region between the first doped region106and the second doped region110of the selected nonvolatile memory transistor resulting in injection of hot electrons to an edge portion of a floating gate112aor112bof the selected nonvolatile memory transistor near the second doped region110. The term “hot electrons” may refer to electrons that have gained a high kinetic energy as a result of a strong electric field.

Erasing may be by hot hole injection. During erase, for example, 0V may be applied to the metal-insulator-metal capacitor108. A voltage of approximately 0 V may be applied to the first doped region106and the substrate178through the base region162. A voltage of approximately 18 V may be applied to the second doped region110. Hot holes may be generated in the channel region between the first doped region106and the second doped region110and injected into the floating gates112aand112bto recombine with the electrons stored in the floating gates112aand112b. The nonvolatile memory device array100may be erased simultaneously. The term “hot holes” may refer to holes that have gained a high kinetic energy as a result of a strong electric field.

During a reading operation, a voltage of approximately 2.5 V may be applied to the metal-insulator-metal capacitor108of a selected nonvolatile memory transistor. A voltage of approximately 1 V may be applied to the second doped region110or the drain of the selected nonvolatile memory transistor. 0 V may be applied to the first doped region106or the source and the substrate178through the base region162. A current may be detected at the second doped region110depending on a threshold voltage of the selected nonvolatile memory transistor. For example, the threshold voltage of the selected nonvolatile memory transistor is low after erase and a current may be detected at the second doped region110. A program operation may lead to a high threshold voltage of the selected nonvolatile memory transistor and less current or negligible current may be detected at the second doped region110.

FIGS. 2 to 7illustrate a fabrication process flow for the array of nonvolatile memory devices100illustrated inFIG. 1B, according to some embodiments of the disclosure.FIG. 2is a cross-section view of a partially completed nonvolatile memory device array100, according to an embodiment of the disclosure. Referring toFIG. 2, a substrate178may be provided. The substrate178may comprise a base layer162, a first dielectric layer160arranged over the base layer162and an active layer158arranged over the first dielectric layer160. A first isolation region152aand a second isolation region156amay be provided in the substrate178. The second isolation region156amay be adjacent to an upper portion of the first isolation region152a. The first active region102aand the second active region102bmay be formed adjacent to the second isolation region156a. Isolation regions152and156may be provided in the substrate178adjacent to the first active region102aor the second active region102b. The second isolation region156aand the isolation region156may thereby define an area of the first102aand the second102bactive regions. In one embodiment, the first102aand the second102bactive regions may be doped p-type to form a p-well region.

The formation of the second isolation region156aand the isolation region156may include forming an opening in the active layer158by a conventional photolithography process followed by a wet or dry etch process. The conventional photolithography process may include depositing a photoresist layer over the active layer158followed by exposure and developing to form a photoresist pattern. A wet or dry etch process may be used to remove a portion of the active layer158not covered by the photoresist pattern to thereby form the opening in the active layer158. The photoresist layer may subsequently be removed. A suitable dielectric material, for example borophosphosilicate glass (BPSG), tetraethyl orthosilicate (TEOS), or any other suitable dielectric material may be deposited into the opening in the active layer158by a suitable deposition process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD) or any other suitable deposition processes. A suitable planarization process, such as chemical mechanical polishing (CMP) may be used to remove a portion of the borophosphosilicate glass layer from a top surface of the active layer158leaving behind another portion of the borophosphosilicate glass layer in the opening in the active layer158thereby forming the second isolation region156aand the isolation region156.

The formation of the first isolation region152aand the isolation region152may include forming an opening in the second isolation region156aand the isolation region156, respectively, the active layer158and a portion of the first dielectric layer160by a conventional photolithography process followed by a wet or dry etch. A layer of suitable dielectric material, for example high density plasma (HDP) silicon dioxide or any other suitable dielectric material may be deposited in the opening by a suitable deposition process such as chemical vapor deposition, atomic layer deposition, physical vapor deposition or any other suitable deposition processes. A suitable planarization process, such as chemical mechanical polishing may be used to remove a portion of the silicon dioxide layer from a top surface of the second isolation region156aand the isolation region156and the active layer158leaving behind another portion of the silicon dioxide layer in the opening in the second isolation region156aand the isolation region156, respectively, the active layer158and a portion of the first dielectric layer160thereby forming the first isolation region152aand the isolation region152, respectively.

FIG. 3is a cross-section view of a partially completed nonvolatile memory device array100after formation of a first array112aand a second array112bof floating gates, a spacer structure172aand172b, a gate dielectric layer170aand170b, and an etch stop layer176, according to an embodiment of the disclosure. Referring toFIG. 3, a layer of suitable dielectric material, for example silicon dioxide, may be deposited over the active layer158, the first active region102a, the second active region102b, the first isolation region152aand the second isolation region156aby a suitable deposition process such as chemical vapor deposition, atomic layer deposition, physical vapor deposition or any other suitable deposition processes. A layer of doped polysilicon may be deposited over the silicon dioxide layer by a suitable deposition process such as chemical vapor deposition, atomic layer deposition, physical vapor deposition or any other suitable deposition processes. In one embodiment, the polysilicon layer may be doped n-type. A conventional photolithography process followed by a wet or dry etch may be used to pattern the doped polysilicon layer and the silicon dioxide layer under the doped polysilicon layer to leave behind a portion of the doped polysilicon layer and the silicon dioxide layer over the first active region102athereby forming the first array of floating gates112aand the gate dielectric layer170aunder the first array of floating gates112a, respectively. Similarly, a conventional photolithography process followed by a wet or dry etch may be used to pattern the doped polysilicon layer and the silicon dioxide layer under the doped polysilicon layer to leave behind a portion of the doped polysilicon layer and the silicon dioxide layer over the second active region102bthereby forming the second array of floating gates112band the gate dielectric layer170bunder the second array of floating gates112b. A layer of suitable dielectric material such as silicon dioxide, silicon nitride (Si3N4) or silicon oxynitride (SiON) may be deposited over the first array112aand the second array112bof floating gates by a suitable deposition process such as chemical vapor deposition, atomic layer deposition, physical vapor deposition or any other suitable deposition processes. The silicon dioxide layer may be patterned by anisotropic etching to leave behind a portion of the silicon dioxide layer over a sidewall of the first array112aand the second array112bof floating gates to thereby form the spacer structures172aand172b, respectively. A layer of suitable dielectric material, for example silicon nitride may be deposited over the active layer158, the first isolation region152a, the second isolation region156a, the isolation structures152and156, the spacer structures172aand172b, the first array112aand the second array112bof floating gates by a suitable deposition process such as chemical vapor deposition, atomic layer deposition, physical vapor deposition or any other suitable deposition processes to thereby form the etch stop layer176. The term “anisotropic etching” may refer to an etching process that is directional in nature.

FIG. 4is a cross-section view of a partially completed nonvolatile memory device array100after formation of an inter layer dielectric layer166aand contact pillars120aand120b, according to an embodiment of the disclosure. A layer of suitable dielectric material, for example silicon dioxide, high density plasma (HDP) undoped silicate glass (USG), tetraethyl orthosilicate (TEOS), or any other suitable dielectric material, may be deposited over the etch stop layer176by a suitable deposition process such as chemical vapor deposition, atomic layer deposition, physical vapor deposition or any other suitable deposition processes to thereby form the inter layer dielectric layer166a. An opening may be formed in the inter layer dielectric layer166aand the etch stop layer176to expose a portion of the first array112aand the second array112bof floating gates. The opening may be formed by a conventional photolithography process followed by a wet or dry etch. A layer of suitable conductive material, for example tungsten (W), may be deposited in the opening by a suitable deposition process such as chemical vapor deposition, atomic layer deposition, physical vapor deposition or any other suitable deposition processes. A suitable planarization process such as chemical mechanical planarization may be used to remove a portion of the tungsten layer from a top surface of the inter layer dielectric layer166aleaving behind another portion of the tungsten layer in the opening to thereby form the contact pillar120aover the first array of floating gates112aand the contact pillar120bover the second array of floating gates112b.

FIG. 5is a cross-section view of a partially completed nonvolatile memory device array100after formation of an opening104in the inter layer dielectric layer166a, the etch stop layer176and a portion of the first isolation region152a, according to an embodiment of the disclosure. Referring toFIG. 5, the opening104may be formed by a conventional photolithography process followed by a wet or dry etch. The opening104may be formed in the inter layer dielectric layer166aand the etch stop layer176between the first array112aand the second array112bof floating gates. In one embodiment, the opening104may extend to a portion of the first isolation region152abetween the first102aand the second102bactive regions. The first isolation region152amay be laterally displaced from the first array112aand the second array112bof floating gates. In a preferred embodiment, a portion of the first isolation region152amay be arranged over a side surface and a bottom surface of the opening104. In an alternative embodiment, the opening104may extend to a bottom surface of the first isolation region152ato expose a portion of the first dielectric layer160at the bottom surface of the opening104.

FIG. 6is a cross-section view of a partially completed nonvolatile memory device array100after formation of a layer of conductive material132, a dielectric layer136and a layer of conductive material138, according to an embodiment of the disclosure. Referring toFIG. 6, a layer of a suitable conductive material, for example titanium nitride (TiN), Titanium (Ti) or any other suitable conductive material may be deposited over the inter layer dielectric layer166a, the contact pillar120aover the first array of floating gates112a, the contact pillar120bover the second array of floating gates112band the side surface and the bottom surface of the opening104to thereby form the conductive material layer132. A layer of suitable high dielectric constant dielectric material, for example hafnium oxide (HfO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), tantalum oxide (Ta2O5), zirconium oxide (ZrO2), hafnium silicate (HfSiO4) or any other suitable high dielectric constant dielectric material may be deposited over the layer of conductive material132to thereby form the dielectric layer136. A layer of suitable conductive material, for example tungsten (W), Aluminum (Al) or any other suitable conductive material may be deposited over the dielectric layer136and fill up the opening104, thereby forming the conductive material layer138. The deposition processes of the layer of conductive material132, the dielectric layer136and the layer of conductive material138may be by a suitable deposition process such as chemical vapor deposition, atomic layer deposition, physical vapor deposition or any other suitable deposition processes.

FIG. 7is a cross-section view of a partially completed nonvolatile memory device array100after formation of a first electrode122, a dielectric layer126and a second electrode128, according to an embodiment of the disclosure. Referring toFIG. 7, the conductive layer138may be patterned to form the second electrode128of a metal-insulator-metal capacitor108. A suitable patterning process, for example, a lithographic process, may be used to leave behind a portion of the conductive layer138in the opening104in the inter layer dielectric layer166aand at least partially over the top surface of the inter layer dielectric layer166a. The dielectric layer136may also be patterned simultaneously with conductive layer138or separately to form the dielectric layer126. The conductive layer132may similarly be patterned simultaneously with conductive layer138and dielectric layer136or separately to form the first electrode122of the metal-insulator-metal capacitor108. In an example, the patterning of the conductive layer138, the dielectric layer136and the conductive layer132may be by a conventional photolithography process followed by a wet or dry etch process.

The nonvolatile memory device array100ofFIG. 7is further processed to form the final device shown inFIG. 1B. Referring back toFIG. 1B, a cross-section view of a nonvolatile memory device array100after formation of a metallization layer168and inter metal dielectric (IMD) layer166bis shown, according to an embodiment of the disclosure. The metallization layer168may be formed by a conventional lift-off process. For example, a layer of photoresist may be deposited over a top surface of the inter layer dielectric layer166aand the second electrode128of the metal-insulator-metal capacitor108. An opening may be formed in the photoresist layer by exposure and developing to expose the second electrode128of the metal-insulator-metal capacitor108. A layer of suitable conductive material, for example copper (Cu), aluminum (Al) or any other suitable conductive material may be deposited in the opening by a suitable deposition process such as electroplating, chemical vapor deposition, physical vapor deposition or any other suitable deposition processes. The photoresist layer may be removed to leave behind a portion of the copper layer over the second electrode128of the metal-insulator-metal capacitor108to thereby form the metallization layer168. A suitable dielectric material, for example silicon dioxide, undoped silicate glass (USG), fluorinated silicate glass (FSG), tetraethyl orthosilicate (TEOS), or any other suitable dielectric material, may be deposited over the inter layer dielectric layer166aand the metallization layer168to thereby form inter metal dielectric layer166b.

The terms “first”, “second”, “third”, and the like in the description and in the claims, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the device described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. The terms “left”, “right”, “front”, “back”, “top”, “bottom”, “over”, “under”, and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the device described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein. Similarly, if a method is described herein as comprising a series of steps, the order of such steps as presented herein is not necessarily the only order in which such steps may be performed, and certain of the stated steps may possibly be omitted and/or certain other steps not described herein may possibly be added to the method. Furthermore, the terms “comprise”, “include”, “have”, and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or device that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article, or device.

While several exemplary embodiments have been presented in the above detailed description of the device, it should be appreciated that number of variations exist. It should further be appreciated that the embodiments are only examples, and are not intended to limit the scope, applicability, dimensions, or configuration of the devices in any way. Rather, the above detailed description will provide those skilled in the art with a convenient road map for implementing an exemplary embodiment of the devices, it being understood that various changes may be made in the function and arrangement of elements and method of fabrication described in an exemplary embodiment without departing from the scope of this disclosure as set forth in the appended claims.