Systems and methods for creating frequency-dependent RC extraction netlist

A method includes approximating a physical characteristic of a semiconductor substrate with a frequency-dependent circuit, and creating a technology file for the semiconductor substrate based on the frequency-dependent circuit. The physical characteristic of the semiconductor substrate identified by one of an electromagnetic simulation or a silicon measurement. The technology file is adapted for use by an electronic design automation tool to create a netlist for the semiconductor substrate and is stored in a non-transient computer readable storage medium.

FIELD

The disclosed system and method relate to integrated circuits. More particularly, the disclosed system and method relate to modeling and fabricating integrated circuits that connected by an interposer.

BACKGROUND

Integrated circuits (“ICs”) are incorporated into many electronic devices. IC packaging has evolved such that multiple ICs may be vertically joined together in so-called three-dimensional (“3D”) packages in order to save horizontal area on a printed circuit board (“PCB”). These 3D IC packages may use an interposer, which may be formed from a semiconductor material such as silicon, for coupling one or more dies to a PCB. Interposers affect the operating characteristics of the ICs that are bonded or otherwise coupled to the interposer due to the resistance and capacitance (“RC”) of the semiconductor substrate.

DETAILED DESCRIPTION

The disclosed system and method advantageously create technology (“tech”) files and netlists that account for electrical coupling between front-side and back-side conductors of a floating semiconductor substrate. The tech files and nelists may advantageously be created such that they may be implemented in an existing EDA tools without requiring new simulation engines to be designed. Additionally, the methodology described herein may be applied to develop tech files and netlists that account for thermal stress, power, or other changes in complex physical behaviors.

For example,FIG. 1illustrates one example of a three-dimensional (“3D”) integrated circuit (“IC”) package100in which first and second IC chips102,104are coupled to a printed circuit board (“PCB”)106using an interposer108. As will be understood by one skilled in the art, IC chips102,104may be bonded to interposer108using conductive bumps110, which may be referred to as a “ubump”. Conductive bumps110may also be used to couple interposer110to PCB106. As will be understood by one skilled in the art, ubumps110connecting the IC chips102,104to interposer108may have different sizes and electrical properties than the ubumps110connecting the interposer110to PCB106.

Interposer108includes front-side and back-side interconnect layers112,114with a semiconductor substrate116sandwiched therebetween. In some applications, substrate116is not grounded and thus is electrically floating. Front- and back-side interconnect layers112,114each may include a plurality of metal layers (e.g., M1, M2, etc.) and dielectric layers. As shown inFIG. 1, front-side interconnect structure112may include conductors118,130disposed in a first metal layer (i.e., M1) and a conductor132disposed in a second metal layer (i.e., M2). Conductor118in front-side interconnect layer112may be electrically connected to metal conductor122in back-side interconnect layer114by way of a through-silicon via (“TSV”)124that extends from front-side surface126of semiconductor substrate116to rear-side surface128of semiconductor substrate116.

Front- and back-side interconnect layers112,114may also include conductors130,132,134that are not connected to each other. Although front and rear conductors130,132,134are not conductively connected to each other, electrical coupling (i.e., capacitive and/or inductive coupling) between conductors130,132, and134occurs during operation of 3D IC100. Electrical coupling also can occur between conductors in the same side of semiconductor substrate116. For example, electrical coupling may occur between conductor118and130if there is no conductive connection between them. Coupling may also occur between adjacent TSVs124that extend through semiconductor substrate116. The electrical coupling between conductors in the interposer degrades the performance of the 3D IC as conventional simulation software does not analyze the effects of such coupling.

FIG. 2is a flow diagram of one example of an improved method200for generating an RC tech file that includes physical characteristics that approximate the coupling experienced by a floating semiconductor interposer108. As will be understood by one skilled in the art, the RC tech file includes process-specific parameters such as layer thicknesses, resistance, capacitance, and s-parameters of various layers. Tech files are used by simulation tools for simulating the response of the proposed IC design under various operating conditions as described in U.S. Patent Application Publication No. US2009/0077507 in the name of Hou et al., entitled “Method of Generating Technology file for Integrated Circuit Design Tools”, the entirety of which is incorporated by reference herein. The flow diagram ofFIG. 2may be performed using a system, such as system300illustrated inFIG. 3. System300includes an electronic design automation (“EDA”) tool302such as “IC COMPILER”™, sold by Synopsis, Inc. of Mountain View, Calif., which may include a place and route tool304, such as “ZROUTE”™, also sold by Synopsis. Other EDA tools302may be used, such as the “VIRTUOSO” custom design platform or the Cadence “ENCOUNTER”® digital IC design platform may be used, along with the “VIRTUOSO” chip assembly router304, all sold by Cadence Design Systems, Inc. of San Jose, Calif.

EDA tool302is a special purpose computer formed by retrieving stored program instructions from a non-transient computer readable storage medium306,308and executing the instructions on a general purpose processor (not shown). Examples of non-transient computer readable storage mediums306,308include, but are not limited to, read only memories (“ROMs”), random access memories (“RAMs”), flash memories, or the like. Tangible, non-transient machine readable storage mediums306,308are configured to store data generated by the place and route tool304.

EDA tool302also includes an RC extraction tool310, having a capacitance engine312and a resistance engine314, as well as an electromagnetic (“EM”) simulation tool316. RC extraction tool310is configured to perform RC timing analysis of the circuit patterns of interposer108such that the RC timing analysis is performed based on the layout.

Router304is capable of receiving an identification of a plurality of cells to be included in an integrated circuit (“IC”) or interposer layout318, including a list320of pairs of cells within the plurality of cells to be connected to each other. Router304may be equipped with a set of default design rules322and tech file324. In addition, an RC tech file326developed by process200(shown inFIG. 2) provides parameters for a floating interposer108. As described below, these physical parameters are based on a frequency-dependent circuit model that approximates the semiconductor's response to an electromagnetic wave.

Referring again toFIG. 2, an interposer pattern or layout318is received and/or created at EDA tool302at block202. As will be understood by one skilled in the art, the interposer patterns may include the length, width, and thickness of the interposer108as well as the lengths, widths, and thicknesses of the conductors in the front- and back-sides112,114of interposer108.

The interposer108is analyzed by EM simulation tool316and/or by analyzing silicon data at block204. EM simulation tool316provides a full-wave analysis of the physical characteristics of the interposer108including the floating semiconductor substrate108. The results of the EM simulation may provide a user of EDA tool302with a graphical representation of the real and imaginary components of the s- and y-parameters as will be understood by one skilled in the art and as shown inFIGS. 5A and 5B. Such graphical representation may be displayed on a display (not shown inFIG. 3) as will be understood by one skilled in the art.

Equations 1 and 2 below relate the curl of the electric field strength, E, and the magnetic field strength, H, to dielectric permittivity, magnetic permeability, and conductivity.
∇×Ē=−jωμHEq. 1
∇×H=jω∈Ē+σĒEq. 2
Where,

∈ is the dielectric permittivity;

μ is the magnetic permeability; and

σ is the conductivity.

The physical characteristics of the interposer (e.g., dielectric permittivity, magnetic permeability, and conductivity) are related to current density, J, as set forth in Equations 3 and 4 below.

ρ is charge; and

t is time.

FIG. 4Ais a cross-sectional view of one example of a two (2) conductors (ports)140,142in an interposer, andFIG. 4Billustrates the EM simulation or silicon measurement of the two (2) ports in accordance withFIG. 4A. In some embodiments, port140is a conductor disposed in the back-end interconnect layer114and port142is a conductor in the front-end interconnect layer112; however, one skilled in the art will understand that the ports may be in the same or different metal layer in the front- or back-side interconnect structure112,114. The EM simulation of the two ports140,142provides the “scattering parameter” or “s-parameter”, and the admittance parameter, sometimes referred to herein as “y-parameter”), of the interposer or other tested device. The relationship between the s-parameter and voltage is set forth below in Equation 5.

As mentioned above, EM simulation tool316generates curves of the s- and y-parameters as a function of frequency as illustrated inFIGS. 5A and 5B.FIG. 5Billustrates the s- and y-parameters as a function of frequency provided by the EM simulation system. Specifically, graph502illustrates the real portion of the y-parameter, graph504illustrates the imaginary portion of the y-parameter, graph506illustrates the magnitude of the s-parameter, and graph508illustrates the phase of the s-parameter.

At block206, a frequency-dependent circuit is selected that best approximates the s-parameter between the conductors140,142. As will be understood by one skilled in the art, the frequency dependency circuit is selected for creating a pi-circuit model of the semiconductor. For example,FIG. 6Aillustrates three components of the y-parameter, Ya, Yb, and Yc, as they relate to conductors140and142in the semiconductor substrate, andFIG. 6Billustrates the corresponding circuit diagram ofFIG. 6A. The matrix set forth below in Equation 6 is used to solve for the components Ya, Yb, and Yc shown inFIGS. 6A and 6B.

Components Yb and Yc are adequately modeled and simulated by the capacitance and resistance engines312,314of the EDA tool302that are configured to model pure conductive and pure dielectric components. Consequently, the frequency-dependent circuit may only be selected for y-component Ya, which corresponds to the semiconductor substrate116between conductors140and142. Various frequency dependent circuits may be selected for approximating the physical response of the semiconductor substrate based on the EM simulation data.

For example,FIG. 7Aillustrates a frequency-dependent resistor-capacitor (“RC”) circuit144including a resistor148disposed in parallel with a capacitor148between conductors140and142, andFIG. 7Billustrates a frequency-dependent RC circuit150comprising a resistor146disposed in series with capacitor148between conductors140and142.FIG. 7Cillustrates a an RCL circuit160including a resistor146disposed in parallel with a capacitor148and an inductor162, which are all disposed between conductors140and142.FIG. 7Dillustrates an RCL circuit170in which resistor146, capacitor148, and inductor162are coupled in series between conductors140and142. One skilled in the art will understand that other frequency-dependent circuits may be used to approximate the EM simulation results; however, more complex circuits result in more complex computations.

At block208, the frequency-dependent circuit selected at block206is used to develop relationships between the resistance, capacitance, frequency, and the s- and y-parameters. For example, if the selected frequency-dependent circuit is the RC circuit144illustrated inFIG. 7A, then the following equation may be used for Ya.

Ya=1RD+jω⁢⁢CDEq.⁢7Where,R=RDD;C=CDD;
and

D is the length of conductors140and142.

If the selected frequency-dependent circuit is the RC circuit150illustrated inFIG. 7B, then the following equation may be used for Ya.

Equation 9 may be used for Ya if the frequency-dependent circuit is the RCL circuit160illustrated inFIG. 7C

If the RCL circuit170is used for the frequency-dependent circuit, then Equation 10 is used to compute Ya as follows.

If the frequency-dependent circuit is RC circuit144illustrated inFIG. 6A, then a relationship is determined for the capacitance and resistance of the substrate with respect to frequency. For example,FIGS. 8A and 8Brespectively illustrate graphs of capacitance versus frequency and resistance versus frequency that may be generated during the EM simulation. A capacitance value C0for a specified frequency value, fC0, is selected at a point along line802inFIG. 8A. The selected value of C0and fC0may be checked for accuracy using a piecewise linear, piecewise quadratic approach, or another approach using higher order mathematical approximations.

For example, in the piecewise linear approach approximations are made for the slope of curves802and806, which are disposed on opposite sides of the selected value for C0. The capacitance, C, is then defined by two equations with n=1:

As the values for C1, C0, fC0, fC1are known fromFIG. 8A, then Equations 11a may be solved for SC1as follows:

A similar method may be used for Equation 11b. The piecewise quadratic approach may use the following equations for f≦f01:
C1=C0+SC1(fC1−fC0)1+SC2(fC1−fC0)2Eq. 13a
C2=C0+SC2(fC2−fC0)1+SC2(fC2−fC0)2Eq. 13b

Equations 13a and 13b have two unknowns, SC1and SC2and the rest of the values may be derived from the graph inFIG. 8Aor a table or equation corresponding to the graph. Accordingly, the unknowns may be solved for in a linear equation since there are two equations and two unknowns. The same procedure is used for f>fC01as will be understood by one skilled in the art.

Similarly, a resistance value R0for a specified frequency value fR0is selected at a point along line804of the resistance versus frequency curve ofFIG. 8Bsuch that two curves810,812are defined on either side of point R0. The methods that may be implemented for determining R0are similar to those described above with respect to C0and f0and redundant detailed descriptions are not provided.

One skilled in the art will understand that piecewise linear and quadratic linear approximations may be performed by system300in an at least partially or fully automated process in response to user input to system300, which may be made using an input device (not shown) including, but not limited to, a mouse, a keyboard, a trackball, a touch screen, or the like. For example, a user may select an initial point for C0and R0and in response system300may use the underlying tables of data from which the graphical representations are generated to iteratively interpolate solutions in accordance with the piecewise linear and/or quadratic linear methods described above.

One or more RC tech files326are created at block410based on the approximations of block408. The one or more RC tech files326may be configured in different formats for different interposer layouts318. For example,FIG. 9Aillustrates one example of a tech file format900for an interposer108including one or more conductors in the front-end interconnect structure112and/or back-end interconnect structure114.FIGS. 9B-9Gare examples of the cross-sections of interposers having different numbers of conductors and metal layers. More particularly,FIG. 9Billustrates one example of an interposer including one or more conductors130-1,130-2, . . . ,130-ndisposed in a first metal layer, M1, of front-side interconnect structure112separated from each other by a distance, e.g., B1, B2, . . . , Bn-1, and from a conductor134in a back-end interconnect structure. Each conductor130in the M1layer of front-side interconnect structure112has a width, w11, w12, . . . w1n, as well as a sensitivity value to conductor134, e.g., S1, S2, . . . Sn, for frequencies less than or equal to the f0frequency.

FIG. 9Cillustrates one example of an interposer including a plurality of conductors132in a second metal layer M2that are spaced apart from each other and from conductor134disposed in the back-side interconnect structure114. An example of an interposer including a plurality of conductors130,132in metal layers M1and M2that are spaced apart from each other and from conductor134in back-side interconnect structure114is illustrated inFIG. 9D. In the embodiments illustrated inFIGS. 9E,9F, and9G, a plurality of conductors are disposed in a single metal layer, which may be metal layers M1or M2in the front-side interconnect structure112or in the back-side interconnect structure114.

Referring again toFIG. 9A, the RC tech files may include width values for k conductors in back-end interconnect structure114as well as for n conductors in a first metal layer, M1, and m conductors in a second metal layer, M2, of the front-end interconnect structure112. The RC tech file may also include capacitance per length values and resistance per length values as well as frequency dependent sensitivity values based on the approximations at block208. For example, the RC tech file may include sensitivities for coupling between conductors in the back-end interconnect structure114and in the first metal layer of the front-end interconnect structure112at frequencies less than or equal to the f0frequency, i.e., S1, S2, . . . , Sn, and sensitivities for conductors in the second metal layer at frequencies greater than the f0frequency, i.e., S1, S2, . . . , Sm. The RC tech file may also include sensitivities for coupling between conductors in the back-end interconnect structure114and in the second metal layer of the front-end interconnect structure112at frequencies less than or equal to the f0frequency, i.e., S1, S2, . . . Sn, and sensitivities for conductors in the second metal layer at frequencies greater than the f0frequency, i.e., S1, S2, . . . , Sm.

For the piecewise linear approach, the capacitance per length and resistance per length stored in the RC tech file may be calculated as follows:

w1minis a minimum width of a front-side conductor;

w2minis a minimum width of a back-side conductor;

C0is the capacitance between the first and second conductors at a user-specified frequency;

Sc1is the sensitivity for frequencies less than or equal to frequency f0; and

Sc2is the sensitivity for frequencies greater than frequency f0.

If the piecewise linear approach is used, then the columns S1and S′1in RC tech file900are populated and the remaining sensitivity columns, i.e., S2, S′2, S3, S′3, . . . Sp, and S′p, are not populated. For higher order mathematical approximations, the sensitivity columns will be further populated for each of the widths of each of the conductors in each of the metal layers. For example, if a piecewise quadratic mathematical approximation is used, then columns S1, S2, S′1, and S′2will be populated.

FIG. 10Aillustrates one example of a tech file1000format for an interposer108including one or more TSV array, such as the two (2) TSV arrays160-1,160-2illustrated inFIGS. 10B and 10C. As shown inFIG. 10A, tech file1000may include a number of TSVs arrays160, a number of TSVs124in the first TSV array, e.g., TSV array160-1, a number TSVs124in a second TSV array, e.g., TSV array160-2, capacitance per length, resistance per length, and the sensitivities for frequencies greater than or less than frequency f0.

FIG. 11Aillustrates one example of a tech file1100for an interposer including at least one TSV124and at least one conductor disposed in front-side interconnect structure112(as illustrated inFIG. 11B) and/or back-side interconnect structure114(as illustrated inFIG. 11C). As shown inFIG. 11A, tech file1100may include a number of TSVs124in the TSV array160, capacitance per length, resistance per length, and the sensitivities for frequencies greater than or less than frequency f0.

At block210, the RC tech files312may be stored in a non-volatile computer readable storage medium such as a read only memory (“ROM”), a random access memory (“RAM”), flash memory, or the like. The stored RC tech file may be used by system300in a method of simulating and fabricating an interposer108. For example,FIG. 12is a flow diagram of one example of a method1200for simulating and fabricating an interposer108.

At block1202, an interposer design is received at system300. The place and route tool304performs placement, which determines the location of each element of the IC containing the patterns of the interposer108. After placement, the routing step adds wires needed to properly connect the placed components while obeying all design rules for the IC. This placement and routing may be performed by a “fabless” designer, for example.

System300may retrieve a tech data file324from computer readable storage medium306at block1206for performing RC extraction. RC extraction includes checking to ensure that the layout meets the design requirements before converting the design files into pattern generator files. For example, analysis is performed to obtain capacitance and resistance for specific geometric descriptions of conductors in the design to create an estimation of the capacitance and resistance from a process which is called parasitic RC extraction. RC extraction tool310has software and hardware that translates a geometric description of conductor and insulator objects, or other shapes described in a candidate IC design file or database, to associated parasitic capacitance values.

In order to perform RC extraction, the RC tech files324,326are respectively retrieved from a non-transient machine readable storage medium306at blocks1204and1206. As described above, RC tech file326may include parameters for RC sensitivities for the couplings through the semiconductor substrate of interposer108.

At block1208, one or more netlists are created for the interposer108or other device. The netlists include values of R, C, and sensitivities and are used to prepare timing analysis for user-specified frequencies at block1210and frequency domain analysis at block1212. As will be understood by one skilled in the art, blocks1210and1212may be simultaneously performed, block1210may be performed before block1212, or block1212may be performed before block1210. The timing and frequency domain analyses are used to evaluate whether the interposer108or other circuit meets timing specifications. If the specifications are not met, then EDA tool300repeats the place and route step, RC extraction, and timing and frequency analyses one or more times, until the timing analysis of the interposer108or other circuit meets specifications.

When all functional and timing requirements are satisfied by the design, the design is complete, and may be turned over for final sign-off check. The design is then provided to an IC foundry to fabricate a mask and the ICs at block1214.

In some embodiments, a method includes approximating a physical characteristic of a semiconductor substrate identified by the electromagnetic simulation with a frequency-dependent circuit, and creating a technology file for the semiconductor substrate based on the frequency-dependent circuit. The technology file is adapted for use by an electronic design automation tool to create a netlist for the semiconductor substrate and is stored in a non-transient computer readable storage medium.

In some embodiments, a system includes a non-transient machine readable storage medium storing at least one technology file generated by an electronic design automation (“EDA”) tool and an RC extraction tool within the EDA tool. The technology file is based on a frequency-dependent circuit that approximates at least one physical characteristic of a semiconductor substrate in response to an electromagnetic wave. The RC extraction tool is configured to generate a netlist based on the technology files and perform at least one of a timing analysis or a frequency domain analysis of the semiconductor substrate based on the netlist.

In some embodiments, a method includes generating a netlist for a semiconductor substrate based on a technology file stored in a non-transient computer readable storage medium, performing at least one of a timing analysis or a frequency domain analysis of the semiconductor substrate based on the netlist, and storing a result of the timing analysis or the frequency domain analysis in a non-transient computer readable storage medium. The technology file approximates at least one physical characteristic of the semiconductor substrate based on a frequency-dependent circuit model.

The disclosed systems and methods advantageously create tech files and netlists that account for electrical coupling between front-side and back-side conductors of a floating semiconductor substrate. The tech files and netlists may advantageously be created such that they may be implemented in an existing EDA tools without requiring significant overhaul to these existing systems. Additionally, the methodology described herein may be applied to develop tech files and netlists that account for thermal stress, power, or other changes in complex physical behaviors.

The methods described herein may be at least partially embodied in the form of computer-implemented processes and apparatus for practicing those processes. The disclosed methods may also be at least partially embodied in the form of computer program code embodied in tangible, non-transient machine readable storage media, such as RAMs, ROMs, CD-ROMs, DVD-ROMs, BD-ROMs, hard disk drives, flash memories, or any other non-transient machine-readable storage medium, wherein, when the computer program code is loaded into and executed by a computer, the computer becomes an apparatus for practicing the method. The methods may also be at least partially embodied in the form of computer program code, whether loaded into and/or executed by a computer, such that, when the computer program code is loaded into and executed by a computer, the computer becomes an apparatus for practicing the methods. When implemented on a general-purpose processor, the computer program code segments configure the processor to create specific logic circuits. The methods may alternatively be at least partially embodied in a digital signal processor formed of application specific integrated circuits for performing the methods.

Although the system and method have been described in terms of exemplary embodiments, they are not limited thereto. Rather, the appended claims should be construed broadly, to include other variants and embodiments of the disclosed system and method, which may be made by those skilled in the art without departing from the scope and range of equivalents of the system and method.