Redundancy circuitry for a semiconductor memory device

A redundancy circuitry for a semiconductor memory device comprising a matrix of memory elements and a plurality of programmable non-volatile memory registers. The non-volatile memory registers being programmable to store addresses of defective memory elements that must be replaced by redundancy memory elements. The redundancy circuitry comprises a combinatorial circuit supplied by address signals and supplying the non-volatile registers with an inhibition signal for inhibiting the selection of redundancy memory elements when a memory element of the matrix is addressed whose address coincides with the address stored in a non-programmed memory register.

CROSS-REFERENCE TO RELATED APPLICATIONS 
The present invention is related to European Application No. 93830493.8. 
This European application is a basis for priority for a co-pending United 
States application filed in the U.S. Patent Office under attorney docket 
no. 853063.407 and bearing a title of "Integrated Circuitry for Checking 
the Utilization Rate of Redundancy Memory Elements in a Semiconductor 
Memory Device." This application also claims priority from European 
Application No. 93830491.2, filed on Dec. 7, 1993. Both of the above 
European applications are incorporated by reference herein. 
TECHNICAL FIELD 
The present invention relates to a redundancy circuitry for a semiconductor 
memory device. 
BACKGROUND OF THE INVENTION 
In the manufacture of semiconductor memories defects are frequently 
encountered that afflict a limited number of memory elements in the memory 
matrix. The reason for the high probability of defects of this type 
resides in that in a semiconductor memory device the greatest part of the 
chip area is occupied by the memory matrix; moreover, it is in the memory 
matrix, and not in the peripheral circuitry, that the manufacturing 
process characteristics are usually pushed to limits. 
In order to avoid that the presence of a limited number of defective memory 
elements, from among many millions, forces the rejection of the entire 
chip, and therefore decreases the manufacturing process yield, a number of 
"redundancy memory elements" are added to the chip. These additional 
memory elements are used as a replacement of those elements that, during 
testing of the memory device, prove defective. Selection circuits, with 
which the integrated component must necessarily be provided, and which 
allow the above-mentioned functional replacement of a defective memory 
element with a redundancy memory element, are indicated as a whole with 
the name of "redundancy circuitry." The set of redundancy memory elements 
and circuitry is defined for short as "redundancy". 
The redundancy circuitry comprises programmable non-volatile memory 
registers suitable to store those address configurations corresponding to 
the defective memory elements; such registers are programmed once and for 
all during the memory device testing, and must retain the information 
stored therein even in absence of the power supply. 
In practical implementations of redundancy, both rows ("word lines") and 
columns ("bit lines") of redundancy memory elements are provided in the 
memory matrix. Each redundancy word line or bit line is associated with a 
respective non-volatile memory register, wherein the address of a 
defective word line or bit line is stored so that, whenever the defective 
word line or bit line is addressed, the corresponding redundancy word line 
or bit line is selected. This implies that each non-volatile memory 
registers must be made up of a number of programmable memory cells at 
least equal to the number of bits in the row address bus, if the register 
is associated with a redundancy word line, or in the column address bus, 
if the register is instead associated with a redundancy bit line. Each 
memory cell of a memory register is therefore dedicated to store the 
logical state of a particular address bit, in the row or column address 
configurations, corresponding to a defective word line or bit line, and 
comprises at least one programmable memory element, a circuit for 
programming the memory element, a circuit for reading the information 
stored in the memory element and a circuit for comparing said information 
with the current logical state of the address bit associated with the 
memory cell. 
If each non-volatile memory register is made up of a number of programmable 
memory cells exactly equal to the number of bits in the row address bus or 
in the column address bus, an ambiguous selection can take place. This 
ambiguity occurs because unprogrammed non-volatile memory registers, 
associated with unused redundancy word lines or bit lines, store that 
particular address configuration corresponding to the unprogrammed 
condition of the memory cells, and this particular address configuration 
belongs to the set of all the possible address configurations for the 
memory device. For example, when a non-defective word line or bit line is 
addressed whose address coincides with the logical configuration of the 
memory cells in an unprogrammed memory register, the redundancy word line 
or bit line associated with said unprogrammed register will be selected 
instead of the non-defective word line or bit line. The situation is even 
worse in memory devices where two or more redundancy word lines or bit 
lines are not used. In this case, the unprogrammed condition is the same 
for all the memory cells of the non-volatile memory registers, addressing 
the non-defective word line or bit line whose address coincides with the 
configuration of the unprogrammed memory cells would cause said two or 
more redundancy word lines or bit lines to be selected simultaneously. 
To prevent such unacceptable ambiguous or even simultaneous selection, each 
non-volatile memory register is provided with an additional programmable 
memory cell (called "guard memory cell" or "control memory cell") which 
allows the selection of the associated redundancy word line or bit line 
only when the guard cell is programmed. 
This causes a significant increase in the overall chip area. 
SUMMARY OF THE INVENTION 
In view of the state of art described, the object of the present invention 
is to realize a redundancy circuitry wherein it is not necessary to 
provide each non-volatile memory register with a respective guard memory 
cell. 
According to the present invention, such object is attained by means of a 
redundancy circuitry for a semiconductor memory device comprising a matrix 
of memory elements, which comprises a plurality of programmable 
non-volatile memory registers, which are programmable to store addresses 
of defective memory elements which must be replaced by redundancy memory 
elements, characterized by comprising combinatorial circuit means supplied 
by address signals and supplying the non-volatile registers with an 
inhibition signal for inhibiting the selection of redundancy memory 
elements when a memory element of the matrix is addressed whose address 
coincides with the address stored in a non-programmed memory register. 
By taking advantage of the known logical state stored in the unprogrammed 
memory elements, it is possible, by means of a redundancy circuitry 
according to the invention, to prevent unused redundancy word lines or bit 
lines from being selected when addressing a non-defective word line or bit 
line whose address configuration coincides with that stored in the 
non-programmed non-volatile memory registers by just supplying the 
redundancy circuitry with an inhibition signal when said address 
configuration is supplied to the memory device. No guard memory cells are 
necessary in the non-volatile memory registers, and the chip area is thus 
reduced. 
The features of the present invention will be made more evident by the 
following detailed description of a particular embodiment.

DETAILED DESCRIPTION OF THE INVENTION 
A redundancy circuitry according to the invention is integrated in a memory 
device chip and comprises a plurality of non-volatile memory registers 1, 
each associated with a respective redundancy word line or bit line (not 
shown in the drawings). The plurality of non-volatile memory registers 1 
can be divided into two sets, a first set comprising all the non-volatile 
registers 1 which are associated with redundancy word lines, and a second 
set comprising all the non-volatile registers which are instead associated 
with redundancy bit lines. In FIG. 1, two non-volatile registers 1 are 
shown which belong to a same set comprising i+1 registers 1, that in the 
following is assumed to be the first set. As regards the second set, the 
following description is still valid, provided that the terms "row" and 
"word line" are replaced by the terms "column" and "bit line". 
Each non-volatile memory register 1 is supplied with row address signals 
A0-An, which taken as a whole represent a row address bus ADD; the row 
address bus ADD also supplies row decoding circuits (not shown) for the 
selection of a particular word line in the memory matrix. 
Each non-volatile register 1 comprises a plurality of programmable 
non-volatile memory cells MC0-MCn; each of said cells MC0-MCn is supplied 
with one of the row address signals A0-An and comprises, in a per-se known 
way, at least one programmable non-volatile memory element 6, a first 
circuit 5 for programming said memory element 6, a second circuit 7 for 
reading the information stored in the non-volatile memory element 6 and a 
third circuit 8 for comparing said information with the current logical 
state of the respective row address signal A0-An (FIG. 2). All the memory 
cells MC0-MCn of a non-volatile memory register 1 are supplied with a 
signal PGM supplied by a control circuitry 4 of the memory device to 
enable the programming of the memory element 6; different non-volatile 
memory registers 1 are supplied with different signals PGM, so that one 
register 1 is programmable at a time. Each memory cell MC0-MCn has an 
output signal CMP0-CMPn which is activated whenever the current logical 
state of the respective row address signal A0-An coincides with the 
logical state stored in the non-volatile memory element 6 of the cell 
MC0-MCn. 
The control circuit 4 is a logic control circuit of any suitable type, many 
being well known in the art. The circuit 4 includes those circuits 
generally provided on a memory to control their operating modes. In the 
simplest case, the control circuit 4 is comprised of logic gates which, 
according to voltage levels present on certain external pins or input 
signal lines, enable various modes of the memory, such as the programming 
mode, the read mode, a factory specified test mode, or the like. The exact 
structure and specific functions of the circuit 4 will vary from chip to 
chip and can be quite complex. However, such control circuitry is part of 
memory chips today and those with skill in the art will be able to select 
or design such a circuit for each memory chip using known circuits and 
general background knowledge based on the use of circuit 4 as described 
herein. 
Each non-volatile memory register 1 further comprises a redundancy word 
line selection circuit 2 which is supplied with all the signals CMP0-CMPn 
and generates a signal RS0-RSi used to select one redundancy word line and 
to deselect a defective word line whose address coincides with the address 
configuration stored in the non-volatile register 1. 
The redundancy circuitry also comprises a combinatorial circuit 3 supplied 
with the row address bus ADD and generating a signal DIS which is 
individually supplied to all the redundancy word line selection circuits 
2. 
At the end of the manufacturing process of the memory device, all the 
programmable non-volatile memory elements 6 included in the memory cells 
MC0-MCn of all the non-volatile memory registers 1 are in a well known and 
defined logical state, i.e., in the virgin or non-programmed state. In the 
case of UV EPROM devices, this is assured by an exposure to UV light 
during the final steps of the manufacturing process; in the case of EEPROM 
or Flash EEPROM devices, both UV light exposure and electrical erasure can 
be performed to guarantee that all the non-volatile memory elements 6 of 
the non-volatile registers 1 are in the same starting condition. 
During the memory device testing, the address configurations corresponding 
to defective word lines or bit lines are programmed into respective 
nonvolatile memory registers 1. Each time a defective word line or bit 
line is encountered, the testing machine puts the memory device in a 
condition such that the control circuitry 4 activates one signal PGM, to 
enable the programming of the memory cells MC0-MCn of a given non-volatile 
memory register 1. In this way any successive attempt to address said 
defective word lines or bit lines will automatically cause redundancy word 
lines or bit lines to be addressed. At the end of this phase, it is 
possible that some redundancy word lines or bit lines are left unused, and 
the associated non-volatile memory registers 1 are therefore left in their 
unprogrammed state. 
The combinatorial circuit 3 is designed to recognize if all the address 
signals ADD currently supplied to the memory device are in a logical state 
coincident with the well known virgin or non-programmed state of the 
programmable memory elements 6 in the memory cells MC0-MCn of non-volatile 
registers 1. In such a scenario, the combinatorial circuit activates the 
signal DIS which inhibits the generation of the redundancy word line or 
bit line selection signals RS0-RSi. In this way even if no guard memory 
cells are provided in the non-volatile registers 1, no ambiguous 
selections of redundancy word lines or bit lines take place when the 
memory device is supplied with an address coincident with that stored in 
non-programmed registers 1. Similarly, this preferred embodiment also 
prevents that, when two or more redundancy word lines or bit lines are not 
used, the addressing of the non-defective word line or bit line having an 
address configuration coincident with that stored in the respective non 
programmed non-volatile registers 1 causes said two or more unused 
redundancy word line or bit line to be simultaneously selected. 
Obviously, this solution prevents defective word lines or bit lines having 
an address configuration coincident with that stored in non-programmed 
non-volatile registers 1 from being repaired, since redundancy word lines 
or bit lines selection is inhibited whenever said address configuration is 
encountered. This however does not constitute a great drawback, since the 
probability of having defective memory elements in such word lines or bit 
lines is small. This means that even if memory device chips having defects 
in such word lines or bit lines are to be rejected, the overall process 
yield is nevertheless improved, because the reduction in the chip area a 
greater number of chips are obtained in each semiconductor wafer. 
The combinatorial circuit 3 can be constructed as a part of the row or 
column address decoding circuits, the signal DIS being, in this case, one 
of the word line or bit line selection signals. It is known that said 
address decoding circuits are made up of a plurality of identical blocks, 
each decoding a particular configuration of the address signals. In 
practice the address configuration stored in non-programmed registers 1 is 
represented by an "all 0" or by an "all 1" configuration. Moreover, the 
blocks performing the decoding of such address configurations are 
typically physically located at the periphery of the address decoding 
circuits. As a result, it is simple, from the point of view of the 
physical layout of the device, to extract the signal DIS from the address 
decoding circuits and to supply it to the redundancy circuitry. 
FIG. 3 shows one example of combinatorial circuit 3, which generates signal 
DIS when address bus A0-An carries the selected address corresponding to 
that stored in the unprogrammed non-volatile registers 1. Circuit 3 
includes an n-input NOR gate 20, which generates a high logic state at its 
output when a low logic state is simultaneously present on all its inputs. 
Some or all of the inputs may include inverters, which may either be 
integral with NOR gate 20 or external thereto. The pattern of inverters 
determines the selected address, which when present on the address bus 
will cause NOR gate 20 to generate at its output a high logic state, i.e., 
activate DIS. In the example shown in FIG. 3, no inverters are used; thus, 
address 0 is the selected address stored in the unprogrammed registers 1. 
Although shown as a NOR gate, combinatorial circuit 3 may be formed from 
other circuits without departing from the spirit and scope of the 
invention. For example, various combinations of inverters, AND, OR and 
NAND gates may be used. 
The discussion provided herein will enable those skilled in the art to make 
modifications to the described embodiment that do not depart from the 
spirit and the scope of the present invention. Accordingly, the present 
invention is not limited to the above-described preferred embodiment.