Source and drain architecture in an active region of a P-channel transistor by tilted implantation

In sophisticated P-channel transistors, which may frequently suffer from a pronounced surface topography of the active regions with respect to the surrounding isolation regions, superior performance may be achieved by using a tilted implantation upon forming the deep drain and source regions, preferably with the tilt angle of 20 degrees or less, thereby substantially avoiding undue lateral dopant penetration into sensitive channel areas.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Generally, the present disclosure relates to the field of semiconductor manufacturing, and, more particularly, to contact areas of transistors having a shallow drain and source dopant profile.

2. Description of the Related Art

Semiconductor devices, such as advanced integrated circuits, typically contain a large number of circuit elements, such as transistors, capacitors and the like, which are formed on an appropriate substrate having formed thereon a crystalline semiconductor layer. Due to the large number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections of the individual circuit elements may generally not be established within the same level on which the circuit elements are manufactured, but require one or more additional “wiring” layers, which are also referred to as metallization layers. These metallization layers generally include metal-containing lines, providing the inner-level electrical connection, and also include a plurality of inter-level connections, which are also referred to as “vias,” that are filled with an appropriate metal and provide the electrical connection between two neighboring stacked metallization layers.

To establish the connection of the circuit elements to the first metallization layer, an appropriate contact structure is provided that connects to a respective contact region of a circuit element, such as a gate electrode and the drain/source regions of field effect transistors, and to a respective metal line in the first metallization layer. The vertical contact structure, including a plurality of contacts or contact plugs, is formed in an inter-layer dielectric material that encloses and passivates the circuit elements.

The continuing shrinkage of dimensions of circuit elements, such as transistors, has been, and will remain, a major goal of semiconductor manufacturers, since significant gain in performance of semiconductor devices may be accomplished in terms of operating speed, production costs and the like. For example, the gate length of field effect transistors has now reached 0.05 μm and less and, hence, fast and powerful logic circuitry, such as microprocessors, storage devices and the like, may be formed on the basis of these transistors, due to increased packing density, thereby also providing the possibility of incorporating more and more functions into a single die region. For instance, the amount of storage incorporated into modern CPUs has steadily increased, thereby enhancing overall performance of microprocessors. In other cases, complex analog and digital circuitry may be provided on the same semiconductor chip, thereby offering enhanced control functionality for a plurality of electronic devices. Upon reducing the feature sizes of the semiconductor circuit elements in the device level, however, the dimensions of the metal lines and vias in the wiring level of the semiconductor devices also have to be reduced since the contact areas of the circuit elements have to be connected to the metallization level so that at least the contact structure and lower lying metallization levels may also require a significant reduction in size of the individual metal lines and vias.

It should be appreciated that, for highly scaled semiconductor devices, typically, electrical performance of the metallization system including the contact level has a significant influence on the overall performance of the semiconductor device due to parasitic capacitance and the parasitic resistivity of the metal features. Consequently, in modern semiconductor devices, frequently, highly conductive metals, such as copper and the like, may be used in combination with dielectric materials of reduced permittivity in order to restrict signal propagation delay caused by the metallization system. On the other hand, in the device level, a reduction of the channel length of field effect transistors in combination with very high dopant concentrations in the drain and source regions and gate electrodes may be used in view of reducing the overall series resistance of the individual circuit elements. However, in order to further reduce the series resistance of transistor devices and other circuit elements in the device level, the resistivity of highly doped silicon-based semiconductor areas is typically reduced by incorporating an appropriate metal species, for instance in the form of a metal silicide. The corresponding metal silicide may have a reduced sheet resistivity compared to even highly doped semiconductor materials and, hence, a respective manufacturing sequence is typically incorporated in sophisticated process techniques in order to form appropriate metal silicide regions in the drain and source areas or other contact areas of circuit elements, possibly in combination with providing a respective metal silicide in the gate electrodes.

Recently, well-approved metal silicides in the form of cobalt di-silicide are increasingly being replaced by metal silicide components of enhanced conductivity, such as nickel silicide. Although significant performance advantages may be associated with the incorporation of a nickel silicide into the drain and source areas of the transistors, it turns out, however, that, in the manufacturing sequence for forming metal silicides, significant yield loss and a less than expected increase of performance may be observed in view of device failures, which may frequently be caused by short circuits “shorting” the PN junctions of the transistors in the drain and source areas.

These device failures are frequently associated with a pronounced surface topography of the active semiconductor regions, which in turn may be caused by a complex manufacturing sequence for forming sophisticated transistor devices, in particular with P-channel transistors. For example, a significant gain in performance may be accomplished by inducing certain strain conditions in the active regions of the transistors since a strained silicon material may have significantly altered electronic characteristics, in particular with respect to charge carrier mobility, which may be taken advantage of with respect to increasing overall conductivity and thus switching speed of the transistors. To this end, appropriate semiconductor alloys, such as silicon/germanium and the like, are frequently incorporated into a portion of the active regions by selective epitaxial growth techniques in order to obtain a strained state of the grown semiconductor alloy due to a mismatch of the natural lattice constants of these materials with respect to the lattice constant of the silicon base material.

In other sophisticated approaches, the electronic characteristics of at least a portion of the active region may be adjusted, for instance, in terms of threshold voltage of the transistors by incorporating an appropriate semiconductor alloy, such as a silicon/germanium alloy, which may thus result in a modification of the band gap energy at the vicinity of an interface formed by a gate dielectric material and the active region. For example, in sophisticated approaches, gate electrode structures of field effect transistors may be provided on the basis of a high-k dielectric material in combination with a metal-containing electrode material, which may require appropriate adaptations of the electronic characteristics of the active region, at least in the vicinity of the gate dielectric material for at least some transistor devices. Also in this case, sophisticated selective epitaxial growth techniques are usually applied, which may also result in a modified surface topography, thereby causing significant irregularities upon forming the metal silicide regions, in particular of P-channel transistors, as will also be explained in more detail with reference toFIGS. 1a-1f.

FIG. 1aschematically illustrates a top view of a semiconductor device100in which a transistor150, i.e., a field effect transistor, is provided, in the form of a P-channel transistor. As illustrated, the transistor150comprises a semiconductor region103, which is also referred to herein as an active region, indicating that at least one transistor is to be formed in and above the corresponding semiconductor region. The active region103is typically formed from a silicon-based semiconductor layer, which is appropriately laterally divided into a plurality of active regions by means of an isolation region102, such as a shallow trench isolation region comprised of silicon dioxide, silicon nitride and the like. Furthermore, a gate electrode structure160is formed on the active region103and extends also into the isolation region102as may be required for connecting to other transistors and/or for allowing the reliable contacting of the gate electrode structure160by appropriate contact elements, as is also discussed above. As indicated above, the isolation region102may laterally delineate the active region103, thereby defining respective sidewalls103S, which thus represent the boundaries of the active region103in a width direction, indicated as W. Similarly, in a length direction L, sidewalls103T represent the boundaries of the active region103, which, in the illustrative embodiment, may have a substantially rectangular shape.

FIG. 1bschematically illustrates a cross-sectional view taken along the line Ib ofFIG. 1a. As illustrated, the isolation region102formed in a semiconductor layer103H may be significantly recessed, as indicated by102R, with respect to the active region103. The degree of recessing102R may significantly depend on the process history of the transistor150, wherein, in sophisticated applications, the corresponding sidewalls103T may be represented by rather steep sidewalls, which may have a significant influence on the finally obtained dopant profile of drain and source regions151. Moreover, in the manufacturing stage shown, the gate electrode structure160is formed on the active region103and comprises a sidewall spacer structure165, which is typically used as an implantation mask when adjusting the concentration profile of the drain and source regions151and which may also be used in the subsequent processing, at least partially, as a mask for forming metal silicide regions in the active region103. Furthermore, the gate electrode structure160comprises an electrode material161, such as a polysilicon material and the like, possibly in combination with a metal-containing electrode material162, such as titanium nitride and the like. Furthermore, a gate dielectric layer164, possibly in combination with a high-k dielectric material163, may be provided in sophisticated applications. Furthermore, as shown, a strain-inducing semiconductor alloy103A, for instance in the form of a silicon/germanium alloy and the like, may be provided so as to induce certain strain conditions in order to improve overall transistor performance. For example, by incorporating a silicon/germanium alloy as the material103A, a compressive strain is induced, which in turn may result in superior conductivity of holes, thereby improving performance of P-channel transistors. Furthermore, a semiconductor alloy103B, such as a silicon/germanium alloy, may be provided as a part of the active region103in order to adjust the threshold voltage of the transistor150in combination with the gate electrode structure160, which may have incorporated therein a high-k dielectric material and the electrode material162.

It should be appreciated that, in some sophisticated transistor architectures, a buried insulating layer (not shown) may be formed below the semiconductor layer103H, when a silicon-on-insulator (SOI) configuration is to be used. In this case, the significant recessing102R may extend almost down to the buried insulating layer.

FIG. 1cschematically illustrates a cross-sectional view of the device100along the line Ic ofFIG. 1a. As shown, also in this case, the sidewalls103S, i.e., the sidewalls delineating the active region103in the length direction (seeFIG. 1a), may have a rather steep configuration. Moreover, as shown, the drain and source regions151may extend to a certain depth within the active region103, depending on the implantation parameters used for incorporating the drain and source dopant species, as will be described later on in more detail. Furthermore, in an SOI architecture, the depth of the drain and source regions may be selected so as to extend to the buried insulating layer, wherein, typically, the dopant concentration at the bottom of the deep drain and source regions151D is less than in an upper portion thereof.

It should be appreciated that, for convenience, the gate electrode structure160, which would actually not be visible in this section, is indicated in dashed lines.

The semiconductor device100as shown inFIGS. 1a-1cmay be formed on the basis of the following process strategies. The size, position and shape of the active region103is determined by forming the isolation region102, which may be accomplished by applying well-established lithography, etch, deposition, planarization and anneal techniques in which appropriate trenches are formed in the semiconductor layer103H, thereby obtaining a plurality of active regions such as the region103. Prior to or after forming the isolation region102, the basic dopant concentration in the various active regions103may be established by, for instance, ion implantation in combination with an appropriate masking regime so as to provide the active regions for P-channel transistors and N-channel transistors, possibly with different threshold voltage values, as required by the overall design rules. Thereafter, appropriate materials are deposited or formed and are appropriately patterned on the basis of highly complex lithography techniques and etch processes in order to form the gate electrode materials161,162and the dielectric materials163,164. A corresponding process sequence may comprise a plurality of complex patterning processes in order to incorporate appropriate work function metal species for the corresponding transistor type under consideration.

Furthermore, as discussed above, if the semiconductor alloy103B is to be provided, for instance when requiring a corresponding adaptation of the electronic characteristics, for instance when providing sophisticated gate materials, the complex gate patterning process is preceded by a process sequence in which an appropriate semiconductor alloy is selectively grown on those active regions that require a corresponding adaptation of the electronic characteristics. During the corresponding process sequence, hard mask materials have to be provided and patterned, followed by cleaning processes and the selective epitaxial growth process, wherein this sequence may generally result in a more or less pronounced material loss in the isolation regions102, for instance caused by patterning the hard mask materials, performing cleaning processes and removing the hard mask materials. After patterning the gate electrode materials161,162, the processing may be continued by forming cavities in the active region103in order to incorporate the semiconductor material103A, if required, wherein also a complex process sequence is to be applied, i.e., the etching of the active region103, while masking any other active regions that do not require the incorporation of the strain-inducing semiconductor material, such as active regions of N-channel transistors. Furthermore, the complex process may include performing any cleaning processes and finally depositing the material103A, followed by the removal of any hard mask materials, which may also result in significant material erosion in the isolation regions102. Thereafter, if required, implantation processes are typically applied for forming a portion of the drain and source regions151.

Generally, it is to be noted that, upon reducing the overall transistor dimensions and in particular the gate length, i.e., inFIG. 1b, the horizontal extension of the electrode materials161,162, an appropriate adaptation of the drain and source concentration profiles has to be applied in order to preserve the desired transistor characteristics, such as channel controllability, leakage currents and the like. On the other hand, in view of reducing the overall series resistance in the transistors, a relatively high dopant concentration is to be provided in the drain and source regions151. Frequently, in the vicinity of a channel area155, the depth of the concentration profile is to be selected less compared to the depth of the concentration profile of “deep” drain and source regions151D. To this end, typically any drain and source extension regions151E may be formed, for instance by providing an appropriate offset spacer element (not shown) and incorporating drain and source dopant species with an appropriate implantation energy and dose. Thereafter, the spacer structure165may be formed and further implantation processes are typically applied so as to incorporate further drain and source dopant species in order to form the regions151D that appropriately connect to the extension regions151E. Similarly, the depth of the concentration profile of the regions151D is to be reduced upon further shrinking the overall transistor dimensions. Thus, the depth of the areas151D may be comparable or even less than the degree of recessing102R.

FIG. 1dschematically illustrates the device100in a further advanced manufacturing stage. As shown, a metal silicide166is formed in the gate electrode structure160and also a metal silicide156is formed in the active region103. As discussed above, typically, the metal silicide regions156are provided so as to reduce the overall contact resistivity between contact elements (not shown) to be formed in a later manufacturing stage, which in turn connect the transistor150to a metallization system still to be formed. In highly scaled semiconductor devices, the contribution of the contact resistivity with respect to the overall performance of the transistor150is increasingly gaining in importance so that sophisticated materials are typically provided in the active region103in view of superior device performance. For example, nickel, possibly in combination with a certain amount of platinum, is frequently used in order to form nickel silicide. It turns out, however, that nickel silicide forms a Schottky barrier with a semiconductor material, wherein the height of the barrier may be significantly reduced when increasing the dopant concentration of the adjacent semiconductor material. Thus, in view of providing a maximum surface area of the metal silicide156that is available for charge carrier exchange with the drain and source regions151, any interfaces formed by the silicide material156and semiconductor material should be positioned within highly doped areas of the drain and source regions151. If a relatively high Schottky barrier exists between a moderately doped semiconductor material and the nickel silicide156, extension of the metal silicide156into the remaining active region103, i.e., “shorting” the corresponding PN junctions, may be disadvantageous in bulk configuration due to significantly increased leakage currents and other parasitic effects, since even a short circuit may be induced for operating voltages that are comparable to the relatively high Schottky barrier. Furthermore, a “shorting” of the PN junctions, although tolerable, may also be disadvantages in an SOI architecture, since the relatively high Schottky barrier caused by the moderate doping concentration in the well region may result in increased series resistance of the transistor, even though the transistor may remain substantially functional. On the other hand, the reduced dopant concentration in the deeper areas of the drain and source regions151may also cause reduced transistor performance, even though the metal silicide regions156may be embedded in the drain and source regions, since current flow from contact elements to the transistor may preferably occur via the metal silicide. In this case, however, the deep areas of the metal silicide156may contribute to a significantly increased overall resistance due to the relatively pronounced Schottky barrier.

That is, during the silicidation process, typically an appropriate refractory metal is deposited and is subsequently heat treated so as to initiate silicon and metal diffusion. On the other hand, chemical reaction is substantially suppressed on any dielectric surface areas. Consequently, the spacer structure165and the isolation region102may act as efficient silicidation masks, while on the other hand the sidewalls103T and103S (seeFIG. 1c) are efficiently silicided, thereby forming the metal silicide156that may thus be positioned outside of the deep drain and source areas151D or may be positioned in an area of the drain and source regions which have a reduced dopant concentration, thereby encountering an increased Schottky barrier.

FIG. 1eschematically illustrates the situation in the cross-sectional view as indicated inFIG. 1aas section Ic, wherein also at the sidewalls103S, metal silicide156D extends deeply into the active region103.

FIG. 1fschematically illustrates a top view of the device100in which the peripheral areas103P at or in the vicinity of the sidewalls103T,103S are illustrated, in which the metal silicide may extend deeply into the active region103, thereby possibly causing significant device failures or generally reducing overall performance of the transistor devices.

Consequently, in particular, sophisticated P-channel transistors may suffer from increased yield loss and reduced performance, when the gate length may be 40 nm and less in transistor architectures requiring the incorporation of a strain-inducing silicon/germanium alloy, thereby making this basically a very promising approach less attractive in volume production environments. Therefore a plurality of approaches has been discussed. For example, avoiding the significant recessing of the isolation structures102during the formation of sophisticated P-channel transistors has been proposed, however, without giving any details as to the practical implementation of an improved strategy in this respect. Another alternative would be the increase of the drain and source dopant concentration by implanting a higher dopant dose. As discussed above, however, significantly modifying the dopant concentration in highly scaled transistors may be associated with a plurality of additional effects, which in turn may not be compatible with the overall device requirements. In this respect, it turns out that the dopant concentration is strictly limited for a technology of 40 nm and less, since otherwise the drain and source regions would unduly penetrate the channel region and increase the device leakage currents. That is, a higher dose implantation process without additional lateral dopant diffusion into the channel region would require increased width of the corresponding spacer elements, which is generally not compatible with sophisticated device architectures due to a limited pitch of gate electrode structures in densely packed device regions. Therefore, an increase of implantation dose may not be a promising solution.

Instead of increasing the implantation dose, the implantation energy could be increased in order to generate a more homogeneous dopant profile throughout the depth of the drain and source regions. It turns out, however, that significant increase of the implantation energy may not be compatible with the overall gate configuration, that is, undue dopant incorporation into the channel region may occur upon increasing the implantation energy.

A promising approach is described in the non-published U.S. patent application Ser. No. 13/052,583, filed by the applicant of the present application, entitled “Shallow Source and Drain Architecture in an Active Region of a Semiconductor Device Having a Pronounced Surface Topography by Tilted Implantation.” According to this concept, tilted implantation processes may be applied with tilt angles of 30 degrees or greater in an attempt to incorporate additional dopant species into the deeper drain and source areas through exposed sidewall surface areas in order to embed the resulting deep metal silicide regions in a semiconductor material of increased dopant concentration. Upon applying this concept, however, it has been observed that the resulting gain in transistor performance is less pronounced as expected, thereby indicating that the significant surface topography of the active region of, in particular, P-channel transistors still significantly influences the behavior of sophisticated semiconductor devices. Therefore, the concept disclosed in this patent application may still require additional improvement in order to provide a strategy appropriate for volume production techniques in view of semiconductor devices including p-channel transistors having a gate length of 40 nm and less in combination with sophisticated gate electrode structures.

In view of the situation described above, the present disclosure relates to manufacturing techniques and semiconductor devices in which appropriate contact areas, such as metal silicide regions, may be provided in active regions requiring a sophisticated dopant profile and having a pronounced surface topography, while avoiding or at least reducing the effects of one or more of the problems identified above.

SUMMARY OF THE INVENTION

Generally, the present disclosure provides manufacturing techniques and semiconductor devices in which the probability of creating device failures upon forming contact regions, such as metal silicide regions, in sophisticated semiconductor devices is reduced by appropriately adapting the dopant profile to the pronounced surface topography of the active regions of P-channel transistors. It has been recognized that the implantation of the drain and source dopant species at an appropriately selected tilt angle with respect to the width direction of the active region may result in superior transistor performance of the P-channel transistors, while undue lateral penetration of the channel region by the drain and source dopants is suppressed by avoiding the usage of any tilt angle along the length direction of the active region. In some illustrative embodiments of the present disclosure, that tilt angle is restricted to a range of 20 degrees and less, thereby obtaining superior performance for sophisticated P-channel transistors with a gate length of 40 nm and less. Consequently, appropriate spacer technologies may still be applied so as to adjust the lateral dopant profile in the vicinity of the channel region, while nevertheless an increased averaged dopant concentration is obtained at peripheral areas of the active region so that superior resistance conditions across the full width of the transistor may be achieved. Hence, the resulting metal silicide may be reliably embedded in highly doped semiconductor material, however, without unduly affecting the lateral dopant profile in the vicinity of the channel region, since the inclination or tilt during the implantation occurs in a plane that is normal to the top surface of the active region and substantially parallel to the gate electrode structure.

One illustrative method disclosed herein comprises performing an implantation process in the presence of a gate electrode structure so as to introduce drain and source dopant species through a first sidewall and a second sidewall of an active region of a P-channel transistor of a semiconductor device, wherein the active region is laterally enclosed by an isolation region that is recessed with respect to the active region and wherein the first and second sidewalls define a width of the active region. Furthermore, the method comprises forming a metal silicide in the active region.

A further illustrative embodiment disclosed herein comprises forming a gate electrode structure on an active region of a semiconductor device, wherein the active region has a length and a width and is laterally delineated by an isolation region that is recessed with respect to the active region. The method further comprises introducing drain and source dopant species into the active region by performing an implantation process, which includes at least two different tilt angles with respect to a normal of a top surface of the active region and defined in a first plane that is normal to the top surface of the active region and parallel to a width direction. The implantation process further includes a non-varying implantation angle defined in a second plane that is normal to the top surface and perpendicular to the width direction. Additionally, the method comprises forming a metal silicide in a portion of the active region.

One illustrative semiconductor device disclosed herein comprises an isolation region formed above a substrate. Moreover, the semiconductor device comprises a silicon-containing active region of a P-channel transistor laterally enclosed by the isolation region, which is recessed with respect to the silicon-containing active region. The silicon-containing active region has a length delimited by a pair of first sidewalls and a width delimited by a pair of second sidewalls. Additionally, the semiconductor device comprises a gate electrode structure formed on the silicon-containing active region and drain and source regions. The drain and source regions comprise a first averaged dopant concentration at the first sidewalls that is less than a second averaged dopant concentration at the second sidewalls. Moreover, the semiconductor device comprises a metal silicide formed in a portion of the silicon-containing semiconductor region, wherein the metal silicide is positioned within the drain and source regions.

DETAILED DESCRIPTION

The present disclosure generally addresses the problem of reduced transistor performance in sophisticated P-channel transistors due to a pronounced surface topography in combination with metal silicide regions, wherein the solution as proposed in the above-identified co-pending US application may result in a less than expected gain in performance, although a certain amount of dopant species may be incorporated through exposed sidewall surface portions of the active regions. It has been recognized that superior transistor performance for P-channel transistors may be accomplished without unduly contributing to the overall process complexity by restricting the incorporation of drain and source dopant species to exposed sidewall surface areas, which define the width of the P-channel transistor. In this manner, highly sophisticated lateral dopant profiles at the channel areas may still be obtained on the basis of appropriate spacer techniques, since the used angles may not substantially affect the lateral dopant profile in this sensitive area. On the other hand, at the periphery with respect to the transistor width, a significantly increased averaged dopant concentration is obtained, thereby contributing to superior drive current capability, since, even at the peripheral regions, a reduced transition resistance from the metal silicide into the semiconductor material may be achieved due to the increased averaged dopant concentration. In particular for SOI devices, in which a “shorting” of the PN junctions may not result in nonfunctional transistors, a significant increase of overall performance of the P-channel transistors may be observed.

Furthermore, it has been recognized that the tilted implantation parallel to the gate electrode structure may be restricted to tilt angles on the magnitude of 20 degrees and less, thereby obtaining superior performance compared to larger tilt angles. Without intending to restrict the present application to the following explanation, it is assumed that a moderate tilt angle parallel to the gate electrode structure may, on the one hand, result in an increased averaged dopant concentration at the peripheral regions that define the width of the transistor, and, on the other hand, enable a more homogeneous dopant distribution in the remaining portion of the drain and source regions. For example, upon selecting a moderate tilt angle in the above-specified range, the implantation energy may be appropriately adapted so as to still retain a desired penetration depth without inducing undue modifications or damage in sensitive device areas, for instance at end portions of the gate electrode structure. Thus, in some illustrative embodiments, the drain and source regions, i.e., the deep portions thereof, may be formed on the basis of the tilt angle of moderate amount with an appropriately adapted implantation energy without requiring any further adaptation of the overall process flow. On the other hand, the lateral dopant profile in the vicinity of the channel region is substantially not affected so that the dopant profile in this area may still be efficiently adjusted on the basis of sidewall spacers and the like.

In some illustrative embodiments, the gate electrode structures of the P-channel transistors may have the same orientation throughout the entire semiconductor device so that a single implantation process without any additional masking steps may be applied. That is, during the implantation process, the semiconductor device may be rotated by 180 degrees in order to realize at least two different tilt angles, which may have the same or a different amount, so that, in a zero degree position and a 180 degrees position, dopant species may be efficiently incorporated into the peripheral areas of the active region.

In other illustrative embodiments, transistors having differently oriented gate electrode structures or active regions may be covered by an appropriate implantation mask so as to not unduly affect the lateral dopant profile in the vicinity of the channel regions of these transistors. Thereafter, a further implantation process, for instance using the same process parameters, may be applied after removing the implantation mask and covering the previously implanted transistors with a further implantation mask.

With reference toFIGS. 2a-2f, further illustrative embodiments will now be described in more detail, wherein reference may also be made toFIGS. 1a-1f, if required.

FIG. 2aschematically illustrates a top view of a semiconductor device200comprising a semiconductor region or active region203, in and above which a P-channel transistor250is formed. The semiconductor region or active region203may be comprised of a silicon-containing semiconductor material, which may enable the formation of a metal silicide in a later manufacturing stage. As shown, the active region203may have a width203W, i.e., the lateral dimension along a width direction (FIG. 1a), wherein it should be appreciated that the width203W may vary along a length203L of the active region203if a non-rectangular geometric configuration is to be considered. The size, shape and position of the active region203is determined by an isolation region202, as is also discussed above with reference to the semiconductor device100. Moreover, in the manufacturing stage shown, a gate electrode structure260is formed on the active region203and also extends into the isolation region203, depending on the overall device configuration.

Generally, the transistor250may have any appropriate configuration, for instance the transistor250may have a configuration as shown inFIGS. 1band1cwhen referring to the transistor150, for instance with respect to the configuration of the active region203and with respect to the gate electrode structure260. In other cases, these components may have any other appropriate configuration, as required. Furthermore, in the manufacturing stage shown, the transistor250may receive a drain and source dopant species in order to implement an increased averaged concentration which may provide superior process conditions at a peripheral area203P upon forming appropriate contact areas, such as metal silicide regions in a later manufacturing stage. As previously discussed with reference to the semiconductor device100as shown inFIG. 1f, the periphery203P, for instance at sidewalls203T defining the width203W, may be highly critical and may be exposed due to the recessed configuration of the isolation region202. It has been recognized, however, that peripheral areas203Q at sidewalls203S that define a length203L may be less critical, for instance with respect to SOI architectures and with respect to configurations in which other components may cover the peripheral regions203Q, for instance when forming dummy gate electrode structures and the like. The width of the peripheral areas203P,203Q may be 20 nm or less. Thus, in some illustrative embodiments, at least a portion of the drain and source dopant species may be incorporated through the exposed sidewall surface areas203T by applying implantation processes using an appropriate tilt angle. For example, as shown inFIG. 2a, in some illustrative embodiments, an implantation process may comprise a first implantation step205A in which an appropriate tilt angle is used in order to incorporate the drain and source dopant species through one of the sidewalls203T, and a second implantation step205B may be applied so as to incorporate the dopant species through the oppositely positioned sidewall203T. To this end, for each of the implantation steps205A,205B, a respective tilt angle with an amount or magnitude of 20 degrees or less may be selected in a plane206that is parallel to the width direction, i.e., inFIG. 2a, the vertical direction. For example, for a substantially non-tilted implantation direction, which corresponds to a direction perpendicular to the drawing plane ofFIG. 2a, a tilt of the implantation direction in a plane that is perpendicular to the drawing plane ofFIG. 2aand that is aligned, i.e., parallel, to the width direction, may result in appropriate tilt angles for the implantation steps205A,205B, respectively.

As discussed above, by selecting the magnitude or amount of the tilt angles of the implantation steps205A,205B according to the above-specified range, the lateral dopant profile in the vicinity of the gate electrode structure260may still be adjusted by any sidewall spacers formed thereon, which thus enables the implementation of reduced gate length of 40 nm and less, such as 32 nm and less. In some illustrative embodiments, the magnitude of the respective tilt angles during the implantation steps205A,205B is selected to 15 degrees or less, while in other cases a tilt angle is selected with an amount of 8.5-12.5 degrees.

FIG. 2bschematically illustrates a cross-sectional view taken along the width direction, i.e., along the section IIb ofFIG. 2a. As shown, the semiconductor device200may comprise a substrate201, above which may be formed the active region203, which may represent a corresponding semiconductor island of a semiconductor layer, as is also discussed above with reference to the semiconductor device100. In the embodiment shown, a buried insulating layer201A may be provided below the active region203, thereby forming an SOI architecture. Furthermore, the isolation region202may be significantly recessed compared to a top surface203G of the active region, as is also previously discussed, for example due to a previously performed process sequence for incorporating a strain-inducing semiconductor alloy203A, such as a silicon/germanium alloy, as is also previously explained. It should be appreciated that, with reference to the components described so far, the same criteria may apply as previously discussed with reference to the semiconductor device100. Hence, a corresponding detailed description of these components and techniques for forming the same may be omitted.

As shown, the implantation process comprising the steps205A,205B may be performed on the basis of respective tilt angles α, β, which are defined in the plane206. The plane206may be normal or orthogonal with respect to the top surface203G and may be oriented in parallel to the width direction203W, thereby enabling a variation of the implantation angle with respect to the exposed sidewall surfaces203T, without affecting the lateral dopant profile in the vicinity of the gate electrode structure260, which is indicated in dashed lines, which, however, would not be visible in the cross-sectionalFIG. 2b. It should be appreciated that the tilt angles α, β may be considered as two different tilt angles, since, even if these angles are of the same magnitude, the orientation is different with respect to a normal of the top surface203G. Consequently, upon selecting the tilt angles α, β to be 20 degrees or less, an appropriate implantation energy may be selected so as to obtain a desired relatively homogeneous dopant distribution within the active region203with an appropriate penetration depth, while additionally an increased dopant concentration may be obtained in the peripheral regions203P (FIG. 2a) compared to conventional strategies. For example, the averaged dopant concentration in the peripheral region203P may be higher compared to strategies in which a substantially non-tilted implantation is applied in order to form the deep drain and source regions in the active region203. Furthermore, the averaged dopant concentration in the peripheral region203P may be higher compared to the averaged dopant concentration at the peripheral regions203Q (FIG. 2a), at least at a depth in the vicinity of the buried insulating layer201A.

It should be appreciated that, due to the moderate magnitude of the tilt angles, a corresponding adaptation of the implant energies may not substantially affect any other device components or subsequent processes. That is, compared to tilt angles of 30 degrees and significantly higher, in the present embodiments, only a moderate increase of energy may be required so as to obtain substantially the target penetration depth. Consequently, the additional penetration length into the gate electrode structure260at end (seeFIG. 2a) during the tilted implantation steps205A,205B may not alter the desired transistor characteristics, since typically the length of the end portions of the gate electrode structures260that extend above the isolation region202is greater compared to the additional penetration length caused by the moderate tilt angles α, β.

FIG. 2cschematically illustrates a cross-sectional view taken along a length direction, i.e., along the section IIc ofFIG. 2a. As shown, the transistor250may comprise drain and source regions251, deep portions251D thereof may be formed during the implantation steps205A/205B, as discussed above. Furthermore, the drain and source regions251may comprise extension regions251E, which substantially determine the lateral dopant profile in a channel region255. Furthermore, in some illustrative embodiments, a threshold voltage adjusting semiconductor alloy203B may be formed as a part of the channel region255below the gate electrode structure260. The gate electrode structure260may comprise gate dialectic materials264,263, for instance in the form of conventional dielectric materials, high-k dielectric materials and the like, as is also discussed above. Additionally, electrode materials262and261may be provided and these materials may be laterally encapsulated by a spacer structure265having an appropriate width so as to determine the lateral profile of the drain and source regions251, as is also discussed above. The components described so far may be formed on the basis of manufacturing techniques as are also described above.

Upon performing the implantation process comprising the steps205A/205B, the drain and source dopant species may be incorporated in a substantially vertical manner with respect to the top surface of the active region203so that the previously established lateral dopant profile of the extension regions251E may not be significantly affected upon forming the deep drain and source regions251D. Furthermore, since dopant penetration through the exposed portions of the sidewalls203S (FIG. 2b) is substantially suppressed, a somewhat reduced averaged dopant concentration may be encountered in the peripheral regions203Q compared to the peripheral regions203P (seeFIG. 2a), in particular in the vicinity of the buried insulating layer201A.

FIG. 2dschematically illustrates a top view of the semiconductor device200according to further illustrative embodiments in which a second P-channel transistor250B may be provided with an orientation that is different compared to the orientation of the transistor250. For example, the gate electrode structure260of the transistor250B may be oriented perpendicularly with respect to the gate electrode structure260of the transistor250. In this case, during the implantation process205, comprising the steps205A,205B as discussed above, the transistor250B may be masked on the basis of an appropriate implantation mask206, such as a resist mask. Thus, undue penetration of drain and source dopant species into areas covered by the gate electrode structure260of the transistor250B may be avoided.

FIG. 2eschematically illustrates the device200in a further advanced manufacturing stage in which the transistor250is masked by an appropriate implantation mask208, such as a resist mask, while the transistor250B is exposed to the implantation process205comprising the steps205A/205B as discussed above, wherein, however, generally the device200is appropriately adjusted to the corresponding ion beam of the process205so as to achieve a tilt angle parallel with respect to the gate electrode structure, as is also explained above. Consequently, the previously established dopant profile in the transistor250may be reliably preserved by the mask208, while the process parameters of the process205may be appropriately selected for the transistor250B. For example, the same implantation parameters and tilt angles may be selected, while, in other cases, at least one process parameter, such as the amount of the tilt angles, the implantation energy and the like, may be selected differently in order to appropriately tune the resulting transistor characteristics. It should be appreciated that the corresponding implantation masks may be readily formed on the basis of well-established lithography techniques.

FIG. 2fschematically illustrates a cross-sectional view of the semiconductor device200in a further advanced manufacturing stage. The cross-section is taken along the width direction, i.e., along the section IIb ofFIG. 2a. As shown, a contact level220may be formed so as to enclose and thus passivate the transistor250. To this end, appropriate dielectric materials, such as a layer221and a layer222, for instance provided in the form of silicon nitride, silicon dioxide and the like, may be formed above the active region203, wherein one or more contact elements223may be provided so as to connect to the drain and source regions251. Furthermore, a metal silicide256may be formed in the active region203and may be substantially completely embedded in the deep drain and source regions251D so as to ensure a reduced series resistance in the transistor250. That is, since the metal silicide256, which may be provided in the form of a nickel-containing silicide material, is embedded in a semiconductor material having a moderately high dopant concentration, the corresponding Schottky barrier is relatively low, thereby providing superior drive current capability. In particular due to the preceding process for forming the deep drain and source regions251D, an increased averaged dopant concentration may be obtained in the peripheral regions203P, which thus provides a current path that extends across the entire width of the active region203, which in turn may translate into superior performance of the transistor250.

The contact level220and the contact elements223may be formed on the basis of any well-established process techniques. It should be appreciated that the metal silicide256may be formed in accordance with process strategies as also previously discussed with reference to the semiconductor device100, thereby providing superior process conditions at the peripheral regions203P. In other cases, however, the metal silicide256may be formed locally at the contact elements223, depending on the overall process strategy. Also in this case, the increased averaged dopant concentration and the peripheral regions203P may contribute to superior transistor performance. Furthermore, in this case, a reduced contact resistance may be obtained, in the case that one or more of the contact elements223may be positioned in close proximity to the peripheral regions203P.

As a result, the present disclosure provides manufacturing techniques and semiconductor devices in which overall drive current capability and thus generally performance of P-channel transistors may be enhanced by specifically incorporating an increased averaged dopant concentration at the peripheral regions203P, which define the effective width of the P-channel transistors. It has been recognized that by having a tilted implantation parallel to the gate electrode structures, the deep drain and source regions may be formed such that superior dopant concentrations are obtained, while on the other hand undue lateral penetration of the channel areas may be avoided during the tilted implantation process. Furthermore, a magnitude of 20 degrees or less has been identified as a highly efficient tilt angle for P-channel transistors having a gate length of 40 nm and less. For example, for P-channel transistors of the 32 nm technology, improvement of transistor performance of several percent with respect to on-resistance and linear on-current has been observed for an amount of 10 degrees of the tilt angles during the formation of the deep drain and source regions compared to P-channel transistors formed on the basis of a non-tilted implantation sequence. It should be appreciated that the above-described embodiments refer to an SOI architecture, in which a “shortening” of the PN junctions may not result in a complete device failure. In other illustrative embodiments (not shown), a bulk configuration, i.e., a configuration in which the active region may directly connect to a crystalline semiconductor material of the substrate, may be used, thereby, in addition to achieving superior performance as described above, significantly reducing the probability of causing a short of the PN junctions in the vicinity of the peripheral regions that define the effective width of the transistors.