MEMORY CELL WITH INDEPENDENTLY-SIZED ELEMENTS

Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element formed in series with the switch element. A smallest lateral dimension of the switch element is different than a smallest lateral dimension of the memory element.

TECHNICAL FIELD

The present disclosure relates generally to semiconductor devices, and more particularly to memory cell architectures and methods of forming the same.

BACKGROUND

Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory, including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), resistance variable memory, and flash memory, among others. Types of resistance variable memory include phase change material (PCM) memory, programmable conductor memory, and resistive random access memory (RRAM), among others.

Non-volatile memory are utilized as memory devices for a wide range of electronic applications in need of high memory densities, high reliability, and data retention without power. Non-volatile memory may be used in, for example, personal computers, portable memory sticks, solid state drives (SSDs), digital cameras, cellular telephones, portable music players such as MP3 players, movie players, and other electronic devices.

Constant challenges related to memory device fabrication are to decrease the size of a memory device, increase the storage density of a memory device, reduce power consumption, and/or limit memory device cost. Some memory devices include memory cells arranged in a two dimensional array, in which memory cells are all arranged in a same plane. In contrast, various memory devices include memory cells arranged into a three dimensional (3D) array having multiple levels of memory cells.

DETAILED DESCRIPTION

Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element formed in series with the switch element. A smallest lateral dimension of the switch element is different than a smallest lateral dimension of the memory element.

Embodiments of the present disclosure implement a memory cell in a cross point memory array in which the switch element dimensions are independent from the memory element dimensions. Size independence between the switch element and the memory element allows for an unlimited number of combinations of memory element size relative to select element size, which in turn facilitates addressing specific electrical properties associated with particular cross point array applications. With the ability to independently size the switch element and the memory element in a same stack of materials forming a memory cell, e.g., using phase change material (PCM), in a cross point array, the current density for the memory element can be different than the current density for the switch element. For example, in a phase change mechanism in the memory element can be improved without resulting in undue switching stress on the switch element.

The figures herein follow a numbering convention in which the first digit or digits correspond to the drawing figure number and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures may be identified by the use of similar digits. For example,106may reference element “06” inFIG. 1, and a similar element may be referenced as306inFIG. 3A. Also, as used herein, “a number of” a particular element and/or feature can refer to one or more of such elements and/or features.

As used herein, the term “substantially” intends that the modified characteristic needs not be absolute, but is close enough so as to achieve the advantages of the characteristic. For example, “substantially parallel” is not limited to absolute parallelism, and can include orientations that are at least closer to a parallel orientation than a perpendicular orientation. Similarly, “substantially orthogonal” is not limited to absolute orthogonalism, and can include orientations that are at least closer to a perpendicular orientation than a parallel orientation.

FIG. 1is a perspective view of a portion of a memory array100in accordance with a number of embodiments of the present disclosure. In the example shown inFIG. 1, memory array100is a cross point memory/switch memory array, e.g., a phase change memory array. However, embodiments of the present disclosure are not so limited. Embodiments of the present disclosure can comprise a two dimensional (2D) cross point memory array, or a three dimensional (3D) cross point memory array with more decks between word lines and bit lines.

Array100can be a cross-point array having memory cells102located at the intersections of a number of conductive lines, e.g., access lines104, which may be referred to herein as word lines, and a number of conductive lines, e.g., data/sense lines106, which may be referred to herein as bit lines. As illustrated inFIG. 1, word lines104can be parallel or substantially parallel to each other and can be orthogonal to bit lines106, which can be parallel or substantially parallel to each other. However, embodiments are not so limited. Word lines104and/or bit lines106can be a conductive material such as tungsten, copper, titanium, aluminum, and/or other metals, for example. However, embodiments are not so limited. In a number of embodiments, array100can be a portion, e.g., a level, of a three-dimensional array, e.g., a multi-level array, (described further with respect toFIG. 2) in which other arrays similar to array100are at different levels, for example above and/or below array100.

Each memory cell102can include a memory element114, e.g., storage element, coupled in series with a respective switch element110, e.g., selector device, and/or access device. The memory cell can have a number of electrodes adjacent the memory element114and switch element110, including a first, e.g., top, electrode, second, e.g., middle, electrode, and/or third, e.g., bottom, electrode. The memory element114can be, for example, a resistive memory element. The memory element114can be formed between a pair of electrodes, e.g., first electrode116and second electrode112. The memory element can be comprised of a resistance variable material such as a phase change memory (PCM) material, for example. As an example, the PCM material can be a chalcogenide alloy such as a Germanium-Antimony-Tellurium (GST) material, e.g., Ge—Sb—Te materials such as Ge2Sb2Te5, Ge1Sb2Te4, Ge1Sb4Te7, Ge8Sb5Te8, Ge4Sb4Te7, etc., or an indium(In)-antimony(Sb)-tellurium(Te) (IST) material, e.g., In2Sb2Te5, In1Sb2Te4, In1Sb4Te7, etc., among other phase change memory materials. The hyphenated chemical composition notation, as used herein, indicates the elements included in a particular mixture or compound, and is intended to represent all stoichiometries involving the indicated elements. Other phase change memory materials can include Ge—Te, In—Se, Sb—Te, Ga—Sb, In—Sb, As—Te, Al—Te, Ge—Sb—Te, Te—Ge—As, In—Sb—Te, Te—Sn—Se, Ge—Se—Ga, Bi—Se—Sb, Ga—Se—Te, Sn—Sb—Te, In—Sb—Ge, Te—Ge—Sb—S, Te—Ge—Sn—O, Te—Ge—Sn—Au, Pd—Te—Ge—Sn, In—Se—Ti—Co, Ge—Sb—Te—Pd, Ge—Sb—Te—Co, Sb—Te—Bi—Se, Ag—In—Sb—Te, Ge—Sb—Se—Te, Ge—Sn—Sb—Te, Ge—Te—Sn—Ni, Ge—Te—Sn—Pd, and Ge—Te—Sn—Pt, for example. However, embodiments of the present disclosure are not limited to a particular type of PCM material. Further, embodiments are not limited to memory elements comprising PCM materials. For instance, the memory elements can comprise a number of resistance variable materials such as binary metal oxides, colossal magnetoresistive materials, and/or various polymer-based resistive variable materials, among others.

For simplicity,FIG. 1shows the memory element114and the switch element110having similar dimensions. However, as is discussed below, a memory cell102can be formed with a memory element114having different dimension(s), e.g., critical dimension, cross-sectional area, etc., than the switch element110.

The switch element110can be a two terminal device such as a diode, an ovonic threshold switch (OTS), or an ovonic memory switch (OMS). However, embodiments of the present disclosure are not limited to a particular type of switch element110. For example, the switch element110can be a field effect transistor (FET), a bipolar junction transistor (BJT), or a diode, among other types of selector devices. The switch element110can be formed between a pair of electrodes, e.g., the second electrode and a third electrode112and108. AlthoughFIG. 1illustrates a configuration having the memory element114formed over the switch element110, embodiments of the present disclosure are not so limited. According to various embodiments of the present disclosure the switch element110can be formed over the memory element114, for example.

In a number of embodiments, the switch elements110corresponding to memory cells102can be OTS's having a chalcogenide selector device material. In such embodiments, the chalcogenide material of the switch element110may not actively change phase, e.g., between amorphous and crystalline, such as a chalcogenide resistance variable material of the memory element. Instead, the chalcogenide material of the switch element can change between an “on” and “off” state depending on the voltage potential applied across memory cell102. For example, the “state” of the OTS can change when a current through the OTS exceeds a threshold current or a voltage across the OTS exceeds a threshold voltage. Once the threshold current or voltage is reached, an on state can be triggered and the OTS can be in a conductive state. In this example, if the current or voltage potential drops below a threshold value, the OTS can return to a non-conductive state.

In a number of embodiments, the memory element114can comprise one or more of the same material(s) as the switch element110. However, embodiments are not so limited. For example, memory element114and switch element110can comprise different materials.

Memory cells102can be programmed to a target data state, e.g., corresponding to a particular resistance state, by applying sources of an electrical field or energy, such as positive or negative electrical pulses, to the cells, e.g., to the storage element of the cells, for a particular duration. The electrical pulses can be, for example, positive or negative voltage or current pulses.

FIG. 2illustrates a three dimensional (3D) memory array in accordance with a number of embodiments of the present disclosure. The 3D memory array comprises a plurality of memory cells202-1,202-2, e.g., memory element in series with a switch element as described with respect toFIG. 1.FIG. 2shows a first memory array comprising memory cells202-1formed between word lines204-1and bits lines206, and a second memory array comprising memory cells202-2formed between word lines204-2and bits lines206. That is, the first memory array formed below bit lines206and the second memory array formed above bit lines206share common bit lines206therebetween.

FIG. 2is a simplified diagram that does not precisely reflect the three dimensional physical dimensions of the various features illustrated, including the exact proximity of features to one another.FIG. 2should not be considered as to be representative of the precise topological positioning of the various elements. Rather,FIG. 2provides an overview of the electrical scheme for a 3D memory array, and the approximate relative arrangement of the various features. AlthoughFIG. 2shows a 3D array comprising2memory arrays, embodiments of the present invention are not so limited, and can include additional memory array(s) arranged into a number of levels.

FIGS. 3A and 3Billustrate cross-sectional views of memory cells in perpendicular directions in accordance with a number of embodiments of the present disclosure.FIG. 3Ashows a cross-section in a first direction, e.g., side view, of a portion of a memory array, such as that shown inFIG. 1.FIG. 3Bshows a cross-section in a second direction, e.g., end view, of a portion of a memory array, such as that shown inFIG. 1.FIGS. 3A and 3Bshow some additional detail than that shown and described with respect toFIG. 1. The memory cells shown inFIGS. 3A and 3Bcan be similar to those described with respect toFIGS. 1 and 2.

As shown inFIG. 3A, a stack of materials can be formed over a word line304. For example, the stack of materials can include a third electrode308formed over the word line304, a switch element310formed over the third electrode308, a second electrode312formed over the switch element310, a memory element314formed over the second electrode312, and a first electrode316formed over the memory element314. A bit line306can be formed over the stack extending left-to-right inFIG. 3Aand into-and-out-of the paper inFIG. 3B. Word line304extends perpendicularly to bit line306. That is, word line304extends into-and-out-of the paper inFIG. 3Aand left-to-right inFIG. 3B. Likewise, the third electrode308can extend similarly to the word line304, as shown inFIGS. 3A and 3B.

For simplicity, all the components of the stack are shown having similar measurements in each of several directions. However, according to embodiments disclosed herein, the memory element314and switch element310can have one or more different directions from one another and/or electrode(s). InFIGS. 3A and 3B, the stack of materials is shown being square when viewed from the side and end perspectives.

As shown inFIG. 3A, sealing material321can be formed around the word line stacks and filling material320can be formed in the areas between the word line stacks. A dielectric material322can be formed over sealing material321and filling material320in the areas between the word line stacks, as shown inFIG. 3A.

As shown inFIG. 3B, sealing material324can be formed around the bit line stacks and filling material323can be formed in the areas between the bit line stacks. Dielectric material322can be formed over sealing material324and filling material323in the areas between the bit line stacks, as shown inFIG. 3B.

The cross point array100of memory cells shown inFIGS. 1 and 2can be created through dry etch patterning in two perpendicular directions, e.g., corresponding to the direction of the word lines304and the bit lines306. Materials corresponding to respective conductive lines and components of the memory cell can be bulk deposited and etched to form the various features. The dry etch patterning in two perpendicular directions forms the various conductive lines and the stacks corresponding to individual memory cells. For example, a first etch can define one direction of the stack, e.g., a row structure separated by first trenches, self-aligned to the underlying conductive lines, e.g., word lines304, which in turn can be connected to other circuitry.

As shown inFIG. 3Aand described above, the row structures and trenches can be sealed in between the word line304, e.g., with sealing material321, and filled with filling material320and dielectric material322. Subsequently, a material comprising the bit lines306, e.g., conductive material, can be deposited on top of the row structures, sealing material321, filling material320, and dielectric material322. A second etch process can be used to form second trenches that define the bit lines306in a direction perpendicular to the word lines304, and again self-aligned to the stacks associated with the memory cells (down to the third electrodes308). Thereafter, the second trenches and third electrodes308can be sealed, e.g., by sealing materials324and filling material323, and the second trenches filled by dielectric material322. The result of the above-described sequence is an array of stacks, e.g., active pillars, corresponding to respective memory cells and isolated from one another by dielectric material322. Word lines304below the memory cells connect the stacks in one direction, and bit lines306above the memory cells connect the stacks in a perpendicular direction.

FIGS. 4A and 4Billustrate cross-sectional views in a same cross section of different sized stacks corresponding to a memory cell in accordance with a number of embodiments of the present disclosure. That is,FIGS. 4A and 4Bshow the same cross section before (FIG. 4A) and after (FIG. 4B) a dimension modification, e.g., isotropic etch. The respective stacks shown inFIGS. 4A and 4Bcan be formed by dry etch patterning in two perpendicular directions described above with respect toFIGS. 3A and 3B. For example, dry etching can be used to form the stacks corresponding to individual memory cells. As will be further described according to embodiments herein, dry etching can be used to control the various dimensions of the stack, e.g., width and length of a cross-sectional area of the switch and memory elements, in a plane perpendicular to a direction between the switch element and the memory element.

For example inFIG. 4A, the dry etch patterning in two perpendicular directions can be used to form a relatively wider stack (comprising word line404A, third electrode408A, switch element410A, second electrode412A, memory element414A, and first electrode416A). InFIG. 4B, a relatively thinner stack (comprising word line404B, third electrode408B, switch element410B, second electrode412B, memory element414B, and first electrode416B). Because the dry etch patterning in two perpendicular directions is self-aligning, all of the components of the relatively wider stack, shown inFIG. 4A, have the same dimensions. Further, all of the components are wider than all of the components of the relatively thinner stack shown inFIG. 4B. That is, using the dry etch patterning in two perpendicular directions to control width of the memory element, for example, results in the widths of all other components in the stack being likewise controlled to the same width.

During the dry etch patterning in two perpendicular directions to form stacks corresponding to memory cells, it is beneficial to have a constant vertical etch profile so as to better define bottom components. This ensures proper isolation throughout the stack (particularly for bottom components), and avoids worsening aspect ratios.

Critical dimension (CD) is the finest line resolvable associated with etch patterning, e.g., etching using a pattern to delineate areas to be etched from areas not to be etched. As used herein, lateral dimension (LD) is a dimension in a plane that is perpendicular to a direction between the switch element and a corresponding memory element of a memory cell, e.g., perpendicular to the orientation of the stack of materials comprising the memory cell. The LD can be a CD (discussed above) or a modified dimension (discussed below). For example, a stack can have a rectangular volume. The rectangular volume can have a longest dimension in a direction the switch element and the corresponding memory element.

Modified dimension (MD) is a lateral dimension of a memory cell stack that has been modified from those dimensions achieved by etch patterning, e.g., such as by an additional isotropic etch. For example, MD can be a desired design rule implementation dimension. Smallest lateral dimension is a stack component, e.g., memory element, select element, etc., dimension other than length, e.g., width, depth, having the least magnitude, where length is oriented in the direction between memory element and select element.

For dry etch patterning in two perpendicular directions, the word line CD can be defined by lithography or pitch multiplication, hard mask, and dry etch, mainly during a first part of the process through hard masking. According to various embodiments of the present disclosure, and as described below, the MD can be further defined from a CD by additional selective etching, e.g., isotropic etching.

The lateral dimension, e.g., CD, of the relatively wider stack shown inFIG. 4Ais greater than the lateral dimension, e.g., CD, of the relatively thinner stack shown inFIG. 4B. However, the LD of the memory element414A is the same as the LD of the switch element410A, in the stack shown inFIG. 4A. The LD of the memory element414B is the same as the LD of the switch element410B in the stack shown inFIG. 4B. That is, the ratio of LD of the memory element to LD of the switch element, e.g., LD(ME)/LD(SE), is 1 for the stacks shown inFIGS. 4A and 4B. Electrical performance of a memory cell is related to the LD and profile of the memory elements414A/B and switch elements410A/B. Therefore, the electrical performance of the memory elements414A/B and switch elements410A/B is not independent in the stacks shown inFIGS. 4A and 4B.

FIGS. 5A and 5Billustrate cross-sectional views of stacks corresponding to a memory cell having different sized memory elements in accordance with a number of embodiments of the present disclosure.FIGS. 5A and 5Billustrate a configuration and method by which the LD of the memory element and the LD of the switch element can be independent. Functionality of a memory cell can be modulated by controlling the dimension(s), e.g., LD, of the memory element with respect to the dimension(s), e.g., LD, of the switch element. Where the dimension(s) of the memory element are not independent of the dimension(s) of the switch element, increasing the current density in the memory element by decreasing the dimension(s) of the memory element causes the current density to correspondingly increase by the same amount in the switch element. This can be detrimental to the functional characteristics of the switch element. That is, improving the operability of the memory element may decrease the operability of the switch element where the dimension(s) of the memory element are not independent of the dimension(s) of the switch element.

FIG. 5Ashows a stack formed by having word line504, third electrode508, switch element510, second electrode512, memory element514A, and first electrode516.FIG. 5Bshows a stack formed by having word line504, third electrode508, switch element510, second electrode512, memory element514B, and first electrode516. As shown inFIG. 5A, memory element514A is relatively wider than memory element514B shown inFIG. 5B. All other stack components are substantially the same size in the stacks ofFIGS. 5A and 5B.

According to various embodiments, the stack shown inFIG. 5Bcan be formed from the stack shown inFIG. 5A. To form the stack shown inFIG. 5B, the stack shown inFIG. 5Acan be subjected to a selective/isotropic process, which is step able to etch the memory element selectively with respect to other materials in a non-directional manner, e.g., selective to a particular material such as that from which the memory element is formed more than other materials and isotropic such that etching can have a horizontal effect. As shown, an isotropic dry etch that is able to selectively etch the memory element material can recess the memory element sidewalls without affecting the other exposed stack component materials. The selective/isotropic process includes an etch with an isotropic component (but does not necessarily intend that the etch be 100% isotropic). Also, selectivity need not be 100% selective to the intended particular material and completely exclude all other materials. For example, the same chemistry can have different etch rates for PCM and OTS material, neither of which may be null.

After the selective etch, e.g., selective isotropic dry etch to the memory element material with respect to other materials, the memory element sidewalls513shown inFIG. 5Bare recessed with respect to other portions of the stack, e.g., relative to word line504, relative to switch element510, relative to an electrode, etc. Since the resulting lateral dimension of the memory element514B is less than the lateral dimension of the switch element510(switch element dimension did not change by the selective isotropic dry etch that is selective to the memory element material), LD(ME)/LD(SE)<1.

AlthoughFIG. 5Ashows a complete stack is formed, which might then be subjected to an etch selective to the memory element material, e.g., selective isotropic dry etch to a particular component material with respect to other materials, according to various embodiments of the present disclosure, the selective etch, e.g., selective to the memory element material with respect to other materials, can be implemented after directional etching of the memory element, but before directional etching of the underlying component, e.g., second electrode512. Therefore, another example dry etching sequence to accomplish a memory element of reduced dimension relative to other stack components, and/or word line504width, can be:1. Directional etch first electrode5162. Directional etch memory element514A3. Selective etch able to etch the memory element514A selective with respect to other materials)4. Directional etch second electrode5125. Directional etch switch element5106. Directional etch third electrode5087. Directional etch word line504
The selective etch step can alternatively be performed at other times during the process, e.g., after the directional etch of word line504, since the etch is performed to etch the memory element and to avoid etching materials other than the memory element material. The amount of reduction in a lateral dimension of the material removed by the selective isotropic dry etch can be controlled, for example, by the duration of the selective isotropic dry etch, among others. With the ability to independently adjust dimension(s) of one stack component, e.g., memory element514A lateral dimension relative to switch element510lateral dimensions, electrical characteristics of the stack, e.g., current density in memory element514B and switch element510can be independently controlled to improve operating characteristics.

According to a number of embodiments of the present disclosure, the selective isotropic dry etch can have a same chemistry as the directional etch for a particular material, e.g., memory element material. However, the etch conditions can be altered to achieve an isotropic etch. For example, a directional etch of the memory element514A can be implemented with a strong plasma, whereas the selective isotropic dry etch can use the same chemistry but different plasma conditions such as different pressure and/or by changing the (ion) bias voltage. According to a number of embodiments, the bias voltage (Vb) of a conductor dry etching chamber can be turned off with the pressure set to be higher relative to the directional etch bias voltage. As a result, ions in the plasma may be less accelerated to a surface of an in-situ wafer which is being processed in the etching chamber, e.g., upon which the stack is formed. Thus, there may be little, if any, bombardment on exposed surface layers. Hence, the plasma-wafer interaction is chemical rather than physical.

According to some embodiments, a gas mixture including hydrogen-based components can be used for the step able to etch the memory element material selectively with respect to other materials, e.g., selective isotropic dry etch where the gas mixture is selective to etch the memory element material more than other materials. Further, an X-based gas mixture can be used for the step able to etch the switch element material selectively with respect to other materials, e.g., selective isotropic dry etch where the gas mixture is selective to etch the switch element material more than other materials. In this example, X can be one or more of fluorine (F), chlorine (Cl) or bromine (Br). Other isotropic etch processes can be used under certain circumstances such as a wet etch, e.g., where other stack components that may be affected are not yet exposed by a directional dry etch.

FIGS. 6A and 6Billustrate cross-sectional views of stacks corresponding to a memory cell having different sized switch elements in accordance with a number of embodiments of the present disclosure.FIGS. 6A and 6Balso illustrate a configuration and method by which the LD of the memory element and the LD of the switch element can be independent by changing the dimension(s) of a switch element relative to a memory element.

FIG. 6Ashows a stack formed by having a word line604, third electrode608, switch element610A, second electrode612, memory element614, and first electrode616.FIG. 6Bshows a stack formed by having word line604, third electrode608, switch element610B, second electrode612, memory element614, and first electrode616. As shown inFIG. 6A, switch element610A in the stack is relatively wider than switch element610B shown in the stack ofFIG. 6B. In this example embodiment, all other stack components can be substantially the same size between the stacks shown inFIGS. 6A and 6B.

According to various embodiments, the stack shown inFIG. 6Bcan be formed from the stack shown inFIG. 6A. To form the stack shown inFIG. 6B, the stack shown inFIG. 6Acan be subjected to a step able to etch the memory element material selectively to other materials, e.g., selective isotropic dry etch selective to etch a particular material such as that from which the memory element is formed more than other materials and isotropic such that etching can have a horizontal etching effect on the switch element610A. As shown, an etch selective to the switch element material with respect to other materials can recess the switch element sidewalls without affecting the other exposed stack component materials, including the memory element.

After the selective etch, e.g., selective dry etch to etch the switch element material more than other materials, the switch element sidewalls615shown inFIG. 6Bare recessed with respect to other portions of the stack, e.g., relative to word line604, relative to memory element614, relative to an electrode, etc. Since the resulting lateral dimension of the switch element610B is less than the lateral dimension of the memory element614(memory element dimension did not change by the selective isotropic dry etch that is selective to the switch element material), LD(ME)/LD(SE)>1.

AlthoughFIG. 6Ashows a complete stack is first formed, which might then be subjected to a selective isotropic dry etch (selective to a particular component material), according to various embodiments of the present disclosure, the step able to etch the switch element material selectively to other materials, e.g., selective dry etch that etches the switch element material more than other materials, can be implemented after directional etching of the switch element610A, but before directional etching of the underlying component, e.g., third electrode608. Therefore, another example dry etching sequence to accomplish a switch element of reduced dimension relative to other stack components, and/or word line604width, can be:1. Directional etch first electrode6162. Directional etch memory element6143. Directional etch second electrode6124. Directional etch switch element610A5. Selective etch able to etch the switch element610A selective to other materials.6. Directional etch third electrode6087. Directional etch word line604
The selective etch step can alternatively be performed at other times during the process, e.g., after the directional etch of word line610A, since the etch is performed to etch the switch element material and to avoid etching materials other than the switch element material. The amount of reduction in a lateral dimension of the material removed by the selective isotropic dry etch can be controlled, for example, by the duration of the selective isotropic dry etch, among others. With the ability to independently adjust dimension(s) of another stack component, e.g., switch element610A lateral dimension relative to select element510lateral dimensions, electrical characteristics of the stack, e.g., current density in memory element614and switch element61011can further be independently controlled to improve operating characteristics.

According to a number of embodiments of the present disclosure, the selective isotropic dry etch can be similar to that described above with respect to the memory element514A shown inFIG. 5A, except instead being selective to the switch element610A material. In this manner, it is possible to modulate the switch element610B lateral dimension(s) as desired relative to lateral dimension(s) of other stack components, e.g., memory element614and/or electrode(s) and/or word line604. Considering the directional and selective isotropic dry etches, stack component dimension(s), including critical dimension and/or area in a plane perpendicular to the stack orientation, can be controlled in one or more of the following ways:1. Reduce lateral dimension(s) of all components of the entire stack (including both memory element and switch element) by directional dry etch, e.g., via lithography or pitch multiplication and hard mask etch process.2. Reduce the lateral dimension(s) of only the memory element via a selective isotropic dry etch (selective to memory element material).3. Reduce the lateral dimension(s) of only the switch element via a selective isotropic dry etch (selective to switch element material).
Reduction of lateral dimensions of components in the stack can be implemented on walls of a stack, e.g., stack walls having a direction parallel to edges of the word line and/or stack walls having a direction parallel to edges of the word line. For example, the reduction can be applied to walls along a single direction or along multiple, e.g., perpendicular, directions, as discussed further below. Stack component lateral dimension(s) can be relatively increased, for example, by increasing the lateral dimension(s) of the entire stack and selectively reducing lateral dimension(s) of certain components, thus leaving lateral dimension(s) of other stack components relatively wider.

FIGS. 7A and 7Billustrate cross-sectional views of stacks corresponding to a memory cell having different sized memory and switch elements in accordance with a number of embodiments of the present disclosure.FIGS. 7A and 7Billustrate a combined configuration and method by which the lateral dimension(s), e.g., CD, of the memory element and the lateral dimension(s), e.g., CD, of the switch element can be independent. According to this example embodiment the lateral dimension(s) of both a switch element and a memory element can be changed relative to other stack components, e.g., electrodes, word line, bit line, etc. Furthermore, the lateral dimension(s) of the switch element and memory element can both be reduced by a same, or different, amount relative to one another.

FIG. 7Ashows a stack formed by having a word line704, third electrode708, switch element710A, second electrode712, memory element714A, and first electrode716.FIG. 7Bshows a stack formed by having a word line704, third electrode708, switch element710B, second electrode712, memory element714B, and first electrode716. As shown inFIG. 7A, switch element710A is relatively wider than switch element710B shown inFIG. 7B. Memory element714A shown inFIG. 7Ais relatively wider than memory element714B shown inFIG. 7B. Furthermore,FIG. 7Balso shows that memory element714B is thinner relative to switch element710B. Although,FIG. 7Bshows memory element714B being reduced by an amount such that it is thinner relative to switch element710B, according to other embodiments switch element710B can be reduced by an amount such that the switch element710B has the same dimension(s) as the memory element714B, or is thinner relative to memory element714B. In this example embodiment, all other stack components can be substantially the same size between the stacks shown inFIGS. 7A and 7B.

According to various embodiments, the stack shown inFIG. 7Bcan be formed from the stack shown inFIG. 7A. To form the stack shown inFIG. 7B, the stack shown inFIG. 7Acan be subjected to a plurality of selective isotropic dry etches, e.g., reach selective to a different material) so as to recess the material of the selected stack component without affecting the other exposed stack component materials.

After a step able to etch the switch element material selectively to other materials, e.g., selective dry etch to etch the switch element material more than other materials, and after a step able to etch the memory element material selectively to other materials, e.g., selective isotropic dry etch to etch the memory element material more than other materials, the memory element sidewalls717and switch element sidewalls719are both recessed with respect to other portions of the stack, e.g., relative to word line704, relative to an electrode, etc. Also the resulting lateral dimension of the memory element is less than the lateral dimension of the switch element, LD(ME)/LD(SE)<1. According to various other embodiments, the resulting lateral dimension of the memory element is greater than the lateral dimension of the switch element such that LD(ME)/LD(SE)>1.

As discussed with respect toFIGS. 5A,5B,6A, and6B, although a completely formed stack is shown inFIG. 7A, which can be subjected to a plurality of selective isotropic dry etches, e.g., one selective to memory element material and one selective to switch element material, according to various embodiments of the present disclosure, the selective isotropic dry etches can be implemented respectively after directional etching of the particular stack component to be subjected to a selective isotropic dry etch, but before directional etching of the underlying stack component. Therefore, another example dry etching sequence that can be used to accomplish the result shown by the stack shown inFIG. 7Bcan be:1. Directional etch first electrode7162. Directional etch memory element714A3. Selective etch able to etch the memory element714A selective to other materials4. Directional etch second electrode7125. Directional etch switch element710A6. Selective able to etch the switch element710A selective to other materials7. Directional etch third electrode7088. Directional etch word line704
The respective selective etch steps can alternatively be performed in an order other than that shown in the process above. The amount of reduction in a lateral dimension of the material removed by a particular selective isotropic dry etch can be controlled, for example, by the duration of the particular selective isotropic dry etch. Respective selective isotropic dry etches can have different durations, for example, so as to independently control amounts of the selected material to be removed thereby.

FIGS. 8A and 8Billustrate cross-sectional views of stacks corresponding to a memory cell having non-vertical stack wall and different sized switch elements in accordance with a number of embodiments of the present disclosure. For any number of reasons, stack walls may not be formed to be completely vertical.FIGS. 8A and 8Bshow that the selective isotropic dry etch techniques described above can be applied to components of a stack having non-vertical stack wall to compensate for the different component dimensions that can result when the stack walls are not completely vertical.

That is, one or more selective isotropic dry etch can be used to modulate the stack sidewall slope, e.g., the memory element and/or switch element portions of the stack. Improving the verticality of a stack sidewall initially having a tapered profile can improve the verticality of the word line and/or bit line as well. Generally, better stack sidewall verticality facilitates better etching performance for memory cells with a large aspect ratio, and can reduce the risk of bit line-to-bit line leakage, as well.

FIG. 8Ashows a stack formed by having word line804, third electrode808, switch element810A, second electrode812, memory element814, and first electrode816.FIG. 8Bshows a stack formed by having a word line804, third electrode808, switch element810B, second electrode812, memory element814, and first electrode816. Similar to that shown and described with respect toFIGS. 6A and 6B, the dimension(s) of switch element810A in the stack shown inFIG. 8Acan be reduced to the result shown for switch element810B in the stack ofFIG. 8Bby a selective isotropic dry etch.

The switch element810B in the stack shown inFIG. 8Bis shown being reduced in lateral dimension(s) to those of the memory element814. Current density through a particular stack component, e.g., memory element, switch element, is determined by the area of the component through which current can flow. As such, the memory element814in the stack shown inFIG. 8Acan have a higher current density than the switch element810A since the lateral dimension(s) of the memory element814(and thus the area bounded by the lateral dimension(s)) are less than the lateral dimension(s) of the switch element810A. After a selective isotropic dry etch is used to reduce lateral dimension(s) of switch element810A, as shown in the stack ofFIG. 8B, switch element810B is now the same size as memory element814. Therefore, current densities can be made similar, e.g., brought back to an intended proportionality associated with vertical stack sidewall.

Some additional benefits can be realized from the memory cell configurations and methods for achieving same than those previously discussed including word line and/or bit line cleaning. A selective isotropic dry etch process can help in removing resputtered polymers, e.g., directional dry etch by-products, from the stack sidewalls corresponding to the word line and/or bit line respectively. Often the polymers on the stack sidewalls can induce a high vertical leakage in an array having such memory cells if not completely removed by wet cleaning. According to some embodiments, the selective isotropic dry etch process described herein can function to clean the stack sidewalls from even very low volatile polymers.