Stable DC current source with common-source output stage

A current source is provided for use with integrated circuits such as programmable logic device integrated circuits. The current source has an operational amplifier with positive and negative inputs and an output. The output is connected to a common-source output stage. A current mirror circuit is connected between the common-source output stage and a positive power supply. An external circuit-board-mounted resistor and capacitor are connected in parallel between the common-source output stage and ground. The negative input of the operational amplifier receives a bandgap reference voltage. A feedback path is used to feed back a feedback signal from the output stage to the positive input of the operational amplifier. The feedback arrangement ensures that the bandgap reference voltage is applied across the external resistor, which, through operation of the common-source output stage and the current mirror circuit, establishes the magnitude of the current source output.

BACKGROUND

This invention relates to integrated circuit current sources, and more particularly, to stable low-noise integrated circuit reference current circuits.

Alternating current (AC) and direct current (DC) current sources are used in a variety of integrated circuit applications. AC current sources have output currents that are controlled as a function of time. DC current sources have a fixed current and are therefore sometimes referred to as current references.

Stability and noise immunity are important characteristics for accurate DC current sources. Even though DC current sources operate at DC (O Hz), noise and the potential for unwanted signal oscillations are generally always present. If the circuit is unstable and prone to AC noise, DC performance will be adversely affected. DC current sources should also be relatively immune to changes in their system environment, so as not to place undesirable constraints on system designers.

SUMMARY

The present invention provides a stable low-noise DC current source. The current source is formed using an integrated circuit device mounted on a circuit board. The integrated circuit device contains a reference voltage source such as a bandgap reference circuit. The bandgap reference circuit supplies a bandgap reference voltage.

An operational amplifier on the device has positive and negative inputs and an output. The output of the operational amplifier is connected to a common-source output stage. The common-source output stage may be formed from a p-channel metal-oxide-semiconductor transistor having a gate, a source, and a drain. The gate is connected to the output of the operational amplifier. A feedback path connected between the drain and the positive input feeds back a feedback signal to the input of the operational amplifier. The feedback signal maintains the voltage on the drain of the common-source output stage at the same level as the bandgap reference voltage supplied to the negative input to the operational amplifier.

A resistor and capacitor are mounted on the circuit board in parallel between the drain of the p-channel transistor and ground or other suitable power supply voltage. Because the voltage of the drain is maintained at the bandgap reference voltage through the feedback arrangement, the voltage on the drain establishes a known current through the resistor. According to Ohm's law, the current through the resistor is equal to the bandgap reference voltage divided by the magnitude of the resistance of the resistor. This current flows through the main branch of a current mirror. The current mirror has at least one other branch whose current magnitude is tied to the magnitude of the current through the main branch. The current flowing through this additional branch serves as the reference current output for the current source.

The capacitor that is connected in parallel with the resistor serves as a low-pass filter that helps to stabilize the voltage on the drain of the p-channel transistor and therefore the reference current.

DETAILED DESCRIPTION

The present invention relates to current sources for integrated circuits. The current source circuitry of the present invention may be incorporated into any suitable integrated circuit, such as an application-specific-integrated circuit, a digital signal processing circuit, a microprocessor, a programmable logic device integrated circuit, or any other suitable analog or digital circuit.

A current source in accordance with the present invention provides a stable DC output current. DC current sources are sometimes referred to as current references or reference sources, because the output current is stable enough to be considered a reference value. The output current from a DC current source can be used in any desired application. For example, the output current from a DC current source on a programmable logic device might be used as a source of current that establishes the drive strength of an output driver (as an example).

In general, current references should exhibit low noise by being relatively immune to high-frequency (AC) effects. Current references should also be stable and not prone to undesirable oscillations. Because integrated circuits in which the current references are implemented may be installed in a wide variety of systems, it is also desirable to make current references relatively immune to environmental effects. For example, it is desirable to make current references robust enough that they are not adversely affected by varying levels of parasitic board capacitance. Current references that operate consistently regardless of the system environments in which they are installed by a system designer simplify the design process and reduce the potential for errors.

Current references in accordance with the present invention have low noise, are stable, and are relatively immune to changes in system environment.

A circuit diagram of a conventional DC current source is shown inFIG. 1. The current source10ofFIG. 1has three parts—integrated circuit device12, package14, and board16. Current source circuitry18is formed as part of the integrated circuit device12. Pads such as pad20on device12are used to electrically connect device12to its package14. Package14has conductive paths such as conductive path22and pins such as pin24that are used to electrically connect package14to board16. Board16is a circuit board on which numerous conductive paths such as path25and board-level components such as resistor26are connected. In the arrangement shown inFIG. 1, resistor26is connected between package pin24and a terminal28that is connected to a source of ground potential (e.g., 0 volts). Components such as resistor26are often referred to as external components, because they are not part of integrated circuit12and package14.

Current source circuitry18has a bandgap reference circuit32that provides a stable bandgap reference voltage on path34. Path34is connected to the positive input of operational amplifier36. The negative terminal of operational amplifier36receives a feedback signal on feedback line37.

The output of operational amplifier36is connected to node38(referred to herein as node A). An internal capacitor40connects node A to ground. Node A is connected to the gate terminal of n-channel metal-oxide-semiconductor (NMOS) transistor42. The gate, source, and drain of transistor42are labeled “G”, “S”, and “D”, respectively. As shown inFIG. 1, the drain of transistor42is connected to a current mirror44formed of p-channel metal-oxide-semiconductor (PMOS) transistors46and48. The current mirror transistors46and48are coupled between a source of positive power supply voltage30(labeled Vcc) and the drain of transistor42. The current mirror transistor48supplies a reference current IREFat current source output line50.

Transistor42is connected to circuitry18in a “source-follower” configuration. In this arrangement, the voltage at the source of transistor42follows the gate voltage of transistor42(i.e., VSis approximately equal to Vg-Vt, where Vtis the threshold voltage for transistor42).

The voltage on the gate of transistor42serves to regulate the behavior of transistor42. The voltage at node52(labeled node B inFIG. 1) is fed back to the negative terminal of operational amplifier36via feedback path37. As a result of this feedback arrangement, any discrepancy between the voltage at node B and the reference voltage on path34serves as an error signal. The error signal directs amplifier36to either increase or decrease the voltage on node A. This voltage adjustment, in turn, serves to increase or decrease the bias voltage on the gate of transistor42.

The effect of this feedback arrangement is to maintain the voltage of node B at the same voltage as the output of bandgap reference circuit32. Consider, for example, the situation in which the voltage at node B falls slightly below the reference voltage on line34. In this situation, the operational amplifier36senses that the voltage on its positive input terminal is higher than the voltage on its negative input terminal. In response, the operational amplifier raises its output voltage, which increases the gate voltage of transistor42. The increased gate voltage on transistor42decreases the drain-source resistance of transistor42and lowers the drain-source voltage drop across transistor42. As a result, the voltage on node B rises. This continues until the voltages at node B and line34are equal.

Similarly, if the voltage at node B is slightly above the bandgap reference voltage on line34, the operational amplifier36will lower its output voltage. This lowers the gate voltage of transistor42and increases the drain-source resistance of transistor42. The increased drain-source resistance of transistor42increases the drain-source voltage drop across transistor42and lowers the voltage on node B until it matches the bandgap reference voltage.

The operational amplifier36serves to buffer the output of the bandgap reference circuit32from the effects of the downstream circuitry. If operational amplifier36were not used, downstream circuit changes could cause the bandgap reference voltage on line34to sag. With the configuration ofFIG. 1, however, the current flowing through line34to the positive input terminal of operational amplifier36is negligible, which isolates bandgap reference circuit32from the rest of the current source circuitry18.

The operation of circuitry18ensures that the voltage at node B remains fixed at the bandgap reference voltage (VBG). This voltage is passed to resistor26via pad20and pin24and lines22and25. The voltage at ground terminal28is typically 0 volts, so the current passing through external resistor26is equal to VBG divided by Rext, according to Ohm's law. The drain-source current of transistor46is the same as the current flowing through resistor26. The resistance value of the external resistor26therefore sets the drain-source current of transistor46to VBG/Rextand, through the operation of the current mirror44, sets the current source output current at line50(IREF).

The performance of the conventional current source circuit ofFIG. 1may be understood with reference to the circuit model shown inFIG. 2. The circuit model54ofFIG. 2is highly simplified, but is helpful in understanding the performance of circuitry18.

Operational amplifier36ofFIG. 1is modeled using ideal amplifier56and the low-pass filter made up of resistor58and capacitor60. The source follower amplifier ofFIG. 1(transistor42) is modeled using ideal amplifier62and the low-pass filter made up of resistor64and capacitor66. The input to circuit54is on the left-hand side ofFIG. 2. The output is on the right.

The values of the components in the model ofFIG. 2are related to the current source circuitry ofFIG. 1. In particular, the value of R1in the circuit model represents the impedance of operational amplifier36. The capacitance C1represents the magnitude of capacitor40. The output impedance of transistor42is R2. The parasitic capacitance associated with node B is C2. This parasitic capacitance includes the capacitances associated with pad20, package trace22, package pin24, board trace25and attached external components such as resistor26. Because of the presence of many components external to device10, the parasitic capacitance C2is strongly influenced by the decisions made by the system designer.

The DC current source circuitry ofFIG. 1is operated at DC. No high-frequency AC signals are intentionally introduced into the current source. However, modeling the AC behavior of the DC current source is helpful, because noise effects occur at AC frequencies. A DC circuit that has a high AC gain and which is unstable will tend to be noisy.

The low-pass filters ofFIG. 2create AC resonances in the circuit. These resonances appear as “poles” when a Bode plot mathematical circuit analysis is performed. Magnitude and phase Bode plots showing the AC response of circuit54as a function of frequency f are shown inFIG. 3. In the upper graph ofFIG. 3, output signal magnitude is plotted as a function of frequency. Output signal phase is plotted as a function of frequency in the lower graph. The lower-frequency pole in the Bode plots is referred to as the dominant pole. The higher-frequency pole in the Bode plots is referred to as the secondary pole.

The positions of the dominant and secondary poles have important implications for the behavior of the circuit54. For example, when the poles are closely spaced, the circuit tends to be less stable, because frequencies in the vicinity of the poles are near resonances. Spacing the poles far apart in frequency tends to improve stability. Circuit performance can also be gauged using phase margin calculations, which provide insight into damping effects and circuit stability.

The Bode plots ofFIG. 3capture two scenarios. In the first scenario, represented by the solid lines in the upper and lower plots, the system designer has created a system environment in which the parasitic capacitance C2is low (e.g., 1 pF). In the second scenario, represented by the dotted lines in the upper and lower plots, the system designer has created a system environment in which the parasitic capacitance is high (e.g., 0.1 μF).

The position of the poles inFIG. 3are inversely related to the RC products associated with the low-pass filter. The position of the dominant pole, fA, is inversely proportional to the product R1C1. For a given design implementation of circuit18, this value is fixed. There are practical limits to both R1and C1(e.g., due to real estate limitations and device considerations), but both are generally made large, to ensure that the dominant pole at fAis located at a relatively low frequency.

The position of the secondary pole is inversely proportional to the product R2C2. In a source follower design such as that used in circuit18ofFIG. 1, the value of R2is low and is fixed. This causes the secondary pole to be located at a relatively high frequency, so long as the capacitance C2is not too high.

The value of the parasitic capacitance C2is influenced by the system environment in which device18is installed. The electrical characteristics of the system in which the device18is installed therefore influence the position of the secondary pole. When device18is installed in a system with short narrow paths and small pads, the parasitic capacitance C2is low and the secondary pole is located at a relatively high frequency fB. When device18is installed in a system with long wide paths and large pads, the capacitance C2is high and the secondary pole shifts to a lower frequency fB′.

The dominant and secondary poles cause break points in the output magnitude Bode plot. For example, as shown in the upper portion ofFIG. 3, there is a break point68associated with the dominant pole and a break point70associated with the secondary pole in the low-capacitance output magnitude trace72. Similarly, there is a break point74associated with the dominant pole and a break point76associated with the secondary pole in the high-capacitance output magnitude trace78.

The values of R1and C1are fixed, so the location of the first break points (i.e., the frequency fAof the dominant pole) is unaffected by the change in parasitic capacitance C2. However, the second break points70and76are significantly affected. When C2is low, the break point occurs at a high frequency fB, as shown by break point70. When C2is high, the break point position shifts to the lower frequency fB′, as shown by break point76.

The dominant and secondary poles also affect the phase plot. Each pole contributes a 90° phase shift in the phase plot. When the poles are spaced far apart, as in the low-parasitic capacitance scenario, the phase plot is characterized by a trace90that has two well-separated 90° phase shifts. When the poles are spaced close together, as in the high-capacitance scenario, the phase plot is characterized by a trace92that has a single 180° phase shift.

The different shapes of the Bode phase plots that result as the secondary pole shifts position have a significant influence on the phase margin of the circuit. To determine the phase margin, the zero intercepts of magnitude traces72and78are located. These intercepts represent the unit-gain frequencies for the low-capacitance and high-capacitance scenarios, respectively. In the present example, the unit-gain frequency associated with low-C2trace72is fG, as indicated by point80inFIG. 3. The unit-gain frequency associated with high-C2trace78is fG′, as indicated by point82.

The phases at the unit gain frequencies fGand fG′ represent the phase margins for the low-parasitic-capacitance and high-parasitic-capacitance scenarios, respectively. As shown by line84, phase trace interception point88, and line94, the phase margin associated with the conventional low-C2scenario is P1. Line86, phase trace interception point96, and line98show that the phase margin associated with the conventional high-C2scenario is P2.

AsFIG. 3demonstrates, the phase margin and therefore the damping and stability performance of the conventional current source ofFIG. 1can be strongly influenced by the system environment in which device18is installed. The dependence of the performance of the current source on its environment is generally undesirable, because this complicates the design process and introduces an opportunity for error. Moreover, the smaller phase margin P1and reduced frequency spacing between the dominant and secondary poles that is associated with the high C2scenario are indicative of lower circuit performance compared to the higher phase margin P2and wider pole spacing associated with the low C2scenario. If conventional circuitry of the type shown inFIG. 1is used in a highly capacitive system environment, performance will suffer.

The present invention provides an improved DC current source architecture. An illustrative current source100using DC current source circuitry in accordance with the invention is shown inFIG. 4. The current source100ofFIG. 4includes an integrated circuit device102, a package104, and a board106. Current source circuitry134is formed as part of the integrated circuit device102. Integrated circuit device102may be a programmable logic device integrated circuit, a digital signal processor, an application-specific integrated circuit, a microprocessor, or any other suitable integrated circuit.

Pads such as pad132on device102are used to electrically connect device102to its package104. Pads132may be wire bonding pads, solder ball pads, or any other suitable input-output electrical contacts for connecting device102to package104.

Package104has conductive paths such as conductive path136and pins such as pin138that are used to electrically connect package104to board106. Pins138may be dual-inline package leads, pins in pin grid array packages, or any other suitable connecting structures. In the example ofFIG. 4, there is a pad132and a pin138associated with packaging device102and circuitry134in a package. If desired, additional, intermediate-level package structures may be used to package device102, in which case there may be more than two associated structures involved in mounting device102to a board. Moreover, in a typical device102and package104, there are numerous pads132and numerous pins138. The arrangement ofFIG. 4is merely illustrative.

As shown inFIG. 4, package pin138is electrically connected to board106. Board106is preferably a circuit board with numerous conductive paths such as path140. Numerous board-level components such as resistor142and capacitor144are mounted on board106. Components such as resistor142and capacitor144may be provided using one or more resistors and capacitors connected together in series and/or in parallel. In the arrangement shown inFIG. 4, resistor142and capacitor144are connected in parallel between package pin138and ground146(i.e., a terminal146that is connected to a source of ground potential at 0 volts). Components such as resistor142and capacitor144are often referred to as external components, because they are not part of integrated circuit102and package104.

Current source circuitry134has a bandgap reference circuit124that provides a stable bandgap reference voltage on path122. Path122is connected to the negative input of operational amplifier120. The positive terminal of operational amplifier120receives a feedback signal on feedback line126. The polarity of the input terminals of operational amplifier120is the opposite of that for operational amplifier36of the conventional current source circuit ofFIG. 1, because current source circuitry134ofFIG. 4has a common-source output stage made up of transistor128, rather than a source-follower output stage. Operational amplifier120is preferably implemented using operational amplifier circuitry formed as an integral portion of integrated circuit102.

As shown inFIG. 4, the output of operational amplifier120is connected to node118(referred to herein as node A). No internal capacitor is used to connect node A to ground. Node A is connected to the gate terminal of p-channel metal-oxide-semiconductor (PMOS) transistor128. The gate, source, and drain of transistor128are labeled “G”, “S”, and “D”, respectively. The source of transistor128is connected to the main branch of a current mirror116formed from p-channel metal-oxide-semiconductor (PMOS) transistors110and112. The current mirror transistors110and112are coupled between a source of positive power supply voltage108(labeled Vcc) and the source of transistor116. The current mirror transistor112supplies a reference current IREFat the current source output line114associated with a secondary branch of the current mirror.

In the example ofFIG. 4, current mirror116has two branches—the main branch formed from transistor110and the secondary branch formed from transistor112. This is merely illustrative. Current mirror116may have any suitable number of secondary branches, each of which may have any suitable current magnitude ratio relative to the main branch current (i.e., relative to the drain-source current of transistor110).

Transistor128forms an output stage for the current source circuitry134and is connected to circuitry134in a common source configuration. In this arrangement, the output stage has a high output resistance (modeled as resistance R2inFIG. 5). The voltage at the drain of transistor128(node B) moves in the opposite direction from the voltage at node A. When the voltage at node A rises, transistor128tends to be turned off, which increases its resistance and lowers the voltage at node B.

The voltage at node B is fed back to the positive terminal of operational amplifier120via feedback path126. This feedback arrangement ensures that the voltage at node B is maintained at a value equal to the bandgap reference voltage VBG produced at the output of bandgap reference circuit124on line122. The difference in voltage between node B and path122serves as an error signal for amplifier120. The error signal directs amplifier120to either increase or decrease the voltage on node A. This voltage adjustment serves to decrease or increase the bias voltage on the gate of transistor128, which makes the node B voltage rise or fall as needed to match the reference voltage from circuit124.

As an example, consider the situation in which the voltage at node B falls slightly below the reference voltage on line122. In this situation, the operational amplifier120senses that the voltage on its positive input terminal is lower than the voltage on its negative input terminal. In response, the operational amplifier lowers its output voltage, which decreases the gate voltage of transistor128. The decreased gate voltage on transistor128tends to turn transistor128on, which decreases the drain-source resistance of transistor128and lowers the drain-source voltage drop across transistor128. As a result, the voltage on node B rises. This continues until the voltages at node B and line122are equal.

Similarly, if the voltage at node B is slightly above the bandgap reference voltage on line122, the operational amplifier120will raise its output voltage. This raises the gate voltage of transistor128and increases the drain-source resistance of transistor128. The increased drain-source resistance of transistor128increases the drain-source voltage drop across transistor128and lowers the voltage on node B until it matches the bandgap reference voltage.

The operational amplifier120serves to buffer the output of the bandgap reference circuit124from the effects of the downstream circuitry. If operational amplifier120were not used, downstream circuit changes could cause the bandgap reference voltage on line122to sag. With the configuration ofFIG. 4, however, the current flowing through line122to the negative input terminal of operational amplifier120is negligible, which isolates bandgap reference circuit124from the rest of the current source circuitry134.

The operation of circuitry134ensures that the voltage at node B remains fixed at the bandgap reference voltage (VBG). This voltage is passed to resistor142via pad132, pin138, and lines136and140. The voltage at ground terminal146is typically 0 volts, so the current passing through external resistor142is equal to VBG divided by Rext, according to Ohm's law. The drain-source current of transistor128is the same as the current flowing through resistor142. The resistance value of the external resistor142therefore sets the drain-source current of transistor128to VBG/Rext and, through the operation of the current mirror116, sets the current source output current at line114(IREF).

The performance of the current source circuit ofFIG. 4may be understood with reference to the simplified circuit model54ofFIG. 2, which was previously used to model the behavior of the conventional current source ofFIG. 1. The circuit model54ofFIG. 2is highly simplified, but is helpful in understanding the performance of theFIG. 4current source circuitry.

Operational amplifier120ofFIG. 4is modeled using ideal amplifier56and the low-pass filter made up of resistor58and capacitor60inFIG. 2. The common source amplifier ofFIG. 4(transistor128) is modeled using ideal amplifier62and the low-pass filter made up of resistor64and capacitor66. The input to circuit54is on the left-hand side ofFIG. 2. The output is on the right.

The values of the components in the model ofFIG. 2are related to the current source circuitry ofFIG. 4. In particular, the value of R1in the circuit model represents the impedance of operational amplifier120. With the arrangement ofFIG. 4, there is no purposefully added extra capacitor component comparable to capacitor40ofFIG. 1, so the capacitance C1represents the magnitude of the parasitic capacitance associated with node A. The output impedance of transistor128is R2. Because the output stage in circuitry134uses a common source configuration, the value of R2is relatively high.

When modeling the current source ofFIG. 4, the capacitance C2represents the parasitic capacitance associated with the external components inFIG. 4combined with the capacitance of capacitor144. The parasitic capacitance contributions to capacitance C2include the capacitances associated with pad132, package trace136, package pin138, board trace140and attached external components such as resistor142. The system designer is typically instructed to include an external capacitor144on board106. The capacitance of capacitor144represents another contribution to the magnitude of C2.

The DC current source circuitry ofFIG. 4is operated at DC (0 Hz). However, as with the modeling performed in connection with the conventional current source ofFIG. 1, it is helpful to model the AC behavior of the DC current source ofFIG. 4, because noise effects occur at AC frequencies.

Magnitude and phase Bode plots showing the AC response of the circuit model54of the current source circuit ofFIG. 4as a function of frequency f are shown inFIG. 5. In the upper graph ofFIG. 5, output signal magnitude is plotted as a function of frequency. Output signal phase is plotted as a function of frequency in the lower graph.

The frequency of the pole associated with operational amplifier120is inversely proportional to the product of R1and C1. The frequency of the pole associated with output stage transistor128is inversely proportional to the product of R2and C2. In contrast to the conventional current source ofFIG. 1, the dominant pole in the circuit ofFIG. 4is associated with the output stage and the secondary pole is associated with operational amplifier120. This is because the value of R2is high due to the use of the common source configuration for transistor128and because the value of C2is generally high due to the use of external capacitor144. The product of R1and C1, in contrast, is relatively low. R1is associated with the internal resistance of operational amplifier120, which is preferably low. There is no added capacitor associated with node A, so the capacitance C1is only due to parasitics and is also low.

The Bode plots ofFIG. 5capture two scenarios. In the first scenario, represented by the solid lines in the upper and lower plots, a system designer has created a current source100in which the capacitance C2is low (e.g., 1 pF, due to the use of a small external capacitor144or the omission of capacitor144). In the second scenario, represented by the dotted lines in the upper and lower plots, the system designer has created a current source10in which the capacitance C2is high (e.g., 0.1 μF due to the use of an approximately 0.1 μF external capacitor144).

The position of the secondary pole, fA, which is inversely proportional to the product R1C1, is fixed for a given design implementation of circuit134. As a result, the plots ofFIG. 5show only a single value of fA. There are practical limits to both R1and C1(e.g., due to real estate limitations and device considerations), but both are generally made relatively small, to ensure that the secondary pole at fAis located at a relatively high frequency.

The position of the dominant pole, which is inversely proportional to the product R2C2, is affected by the value of C2. In a common source design such as that used in circuit134ofFIG. 4, the value of R2is high and is fixed. This causes the dominant pole to be located at a relatively low frequency, so long as the capacitance C2is not too low. The value of the capacitance C2is influenced by the system environment in which device102is installed (parasitics) and by the value of external capacitor144. If a sufficiently large external capacitor144is used, the capacitance of capacitor144dominates and the influence of parasitic capacitances may be neglected.

Although R2is fixed, the position of the secondary pole is influenced by changes in C2. When C2is low, the dominant pole is located at a relatively high frequency fB. When C2is high, the dominant pole shifts to a lower frequency fB′.

The dominant and secondary poles cause break points in the output magnitude Bode plot. For example, as shown in the upper graph ofFIG. 5, there is a break point148associated with the secondary pole and a break point150associated with the dominant pole in the low-C2output magnitude trace152. Similarly, there is a break point154associated with the secondary pole and a break point156associated with the dominant pole in the high-C2output magnitude trace158.

The values of R1and C1are fixed, so the location of the secondary break points (i.e., the frequency fAof the secondary pole) is unaffected by the change in capacitance C2. However, the dominant break points150and156are significantly affected. When C2is low, the break point occurs at a high frequency fB, as shown by break point150. When C2is high, the break point position shifts to the lower frequency fB′, as shown by break point156.

The dominant and secondary poles affect the phase plot in the lower half ofFIG. 5. Each pole contributes a 90° phase shift in the phase plot, but unlike the conventional scenario ofFIGS. 1 and 3, the phase curves associated with theFIG. 4circuit always have two well-separated 90° phase shifts. This is because increasing the capacitance C2causes the dominant pole position to shift to a frequency fB′ that is farther from fAthan frequency fB. This is in contrast to the conventional arrangement ofFIGS. 1 and 3, in which increases to C2cause the poles to move closer to each other, indicating instability. The circuit ofFIG. 4is therefore not susceptible to instabilities induced by increases in C2, but rather becomes more stable in the event that C2is increased. The common source configuration of transistor128(FIG. 4) ensures that R2will be high, so fBwill be relatively low, even if C2is relatively low. If C2is made large by a system designer, the product of R2C2will be even larger and the current source ofFIG. 4will be even more stable.

To determine the phase margin for the circuit ofFIG. 4under both low-C2and high-C2scenarios, the zero intercepts of magnitude traces152and158ofFIG. 5are located. These intercepts represent the unit-gain frequencies for the low-capacitance and high capacitance scenarios, respectively. The unit-gain frequency associated with low-C2trace152is fG, as indicated by point160inFIG. 5. The unit-gain frequency associated with high-C2trace158is fG′, as indicated by point162.

The phases at the unit gain frequencies fGand fG′ represent the phase margins for the low-C2and high-C2scenarios, respectively. As shown by line164, phase trace interception point166, and line168, the phase margin associated with the conventional low-C2scenario is P1. Line170, phase trace interception point172, and line174show that the phase margin P2that is associated with the conventional high-C2scenario is greater than the low-C2phase margin P1.

AsFIG. 5demonstrates, the current source ofFIG. 4in accordance with the present invention has a higher phase margin and a larger dominant-to-secondary pole spacing as C2increases, indicating improved damping and stability. In contrast, the phase margin and pole-to-pole spacing in the conventional current source ofFIG. 1degrade as C2increases. The larger phase margin P2and increased frequency spacing between the dominant and secondary poles that is associated with the high C2scenario in the current source ofFIG. 4are indicative of good AC noise performance.

AC noise performance may also be improved through the use of higher gain in the output stage of the current source. In the conventional circuit ofFIG. 1, the output stage source follower has a gain of about 0.5. As a result, the gain of operational amplifier36must be relatively high to ensure adequate overall gain. This tends to exacerbate AC noise effects in conventional current sources.

In the current source ofFIG. 4, in contrast, the gain of common source amplifier128is about 2. This allows the overall gain between the negative terminal input to operational amplifier120and node B to be maintained at an acceptably high level to ensure an adequate feedback signal over path126, while reducing the gain contribution from the operational amplifier circuit120. Because of the potential for reducing the gain of operational amplifier120, it may be possible to lower the resistance R1associated with amplifier120, further ensuring that R1is small and fAis large.

Moreover, the use of large capacitances for capacitor144not only stabilizes the circuit by moving the dominant pole farther from the secondary pole, but also creates a low-pass filter that reduces AC noise on node138. Because the AC noise filtering properties of capacitor144stabilize the DC voltage level across resistor142, the current through resistor142is made more stable, which increases the stability of IREF.