Method for implementing level shifter circuits for integrated circuits

A low power level shifter circuit includes an input inverter operating in a domain of a first voltage supply. The input inverter receives an input signal and provides a first inverted signal. An output inverter operating in a domain of a second voltage supply coupled to the input inverter and provides an output signal having a voltage level corresponding to the second voltage supply and a logic value corresponding to the input signal. The second voltage supply is higher than the first voltage supply. A leakage current control circuit includes a finisher transistor connected between the second voltage supply and the input to the output inverter and a path control transistor control a path between the first voltage supply and the input inverter.

FIELD OF THE INVENTION

The present invention relates generally to the data processing field, and more particularly, relates to a method for implementing voltage level shifter circuits and low power level shifter circuits for integrated circuits.

DESCRIPTION OF THE RELATED ART

Level shifter circuits are utilized in integrated circuits for changing the voltage of a signal from a first voltage to a second voltage, such as from a high to a low operating voltage, or from a low to a high operating voltage.

As technology advances, scaling of the power supply voltage occurs for power reduction and reliability reasons. Certain types of circuits are more sensitive to this reduction in voltage such as analog, memory and input/output (I/O) circuits. To combat this, many chip designs have added extra power supply domains to use in these sensitive circuits.

Referring toFIGS. 1A, and1B, there is shown a prior art circuit100including a first power supply voltage VDDA and a second higher power supply voltage VDDB. Circuit100includes a pair of inverters with an input inverter receiving an input signal and providing an output OUTPUT_B. The input inverter is defined by a series connected P-channel field effect transistor (PFET)102and an N-channel field effect transistor (NFET)104connected between the first power supply voltage VDDA and ground. An output inverter is defined by a series connected PFET106and NFET108connected between the second power supply voltage VDDB and ground.

The input inverter output OUTPUT_B is applied to the output inverter that provides an output signal OUTPUT.

As shown inFIGS. 1A, and1B when static logic gates are connected normally at the interface between a lower VDDA and a higher VDDB, problems can result. For example, as illustrated inFIG. 1Bas VDDB rises greater than a PFET threshold voltage above VDDA, the output inverter PFET106will turn on and DC current will flow through the output inverter gate connected to VDDB. This prevents a good zero level on the output node, as indicated by the label>0 at the OUTPUT inFIG. 1B.

Referring also toFIG. 2, the problem can be exacerbated with wider gates in which multiple PFETs could be turned on and leak DC current.FIG. 2illustrates a prior art two-input NAND gate200including a pair of input inverters, defined by PFET202and NFET204, and PFET206and NFET208, receiving INPUT1and INPUT2and connected between the first power supply voltage VDDA and ground. NAND gate200includes PFET210, NFET212, and PFET216, NFET218having a respective gate input connected to the respective common connection of PFET202and NFET204, and PFET206and NFET208and providing output OUTPUT_B and operating in the domain of the second power supply voltage VDDB. OUTPUT_B is applied to the output inverter defined by PFET220, NFET222that provides an output signal OUTPUT. When VDDB rises greater than a PFET threshold voltage above VDDA, each of the PFETs210,216, and NFET222can turn on leaking DC current.

FIG. 3illustrates a prior art level shifter circuit300. Level shifter circuit300includes an input inverter302connected to a first voltage supply domain VDD1receiving an input signal IN. Level shifter circuit300includes a pair of cross-coupled PFETs304,306respectively connected between a second voltage supply domain VDD2and a respective NFET308,310. In operation with an input signal IN of logical 1, NFET308is turned on and input inverter302provides a logical 0, NFET310is turned off. PFET306is turned on driving the output OUT to VDD2and PFET304turned off. With an input signal IN of logical 0, NFET308is turned off and input inverter302provides a logical 1, NFET310is turned on, driving the output OUT to logical 0 and PFET304turned on. The gate input to PFET306approaches VDD2and PFET306is turned off.

Problems with many known level shifter circuits include degraded power and performance characteristics. For example, in the prior art level shifter circuit300shoot through current can result on both transitions from low to high and from high to low. Also prior art level shifter circuit300fails to enable high frequency operation that may be required for some particular applications.

A need exists for an effective mechanism for implementing voltage level shifters and low power level shifters for integrated circuits.

SUMMARY OF THE INVENTION

A principal aspect of the present invention is to provide a method for implementing voltage level shifters and low power level shifters for integrated circuits. Other important aspects of the present invention are to provide such method for implementing voltage level shifters and low power level shifters for integrated circuits substantially without negative effect and that overcome many of the disadvantages of prior art arrangements.

In brief, a method for implementing voltage level shifter circuits and low power level shifter circuits are provided for integrated circuits. A low power level shifter circuit includes an input inverter operating in a domain of a first voltage supply. The input inverter receives an input signal and provides a first inverted signal. An output inverter operating in a domain of a second voltage supply coupled to the input inverter and provides an output signal having a voltage level corresponding to the second voltage supply and a logic value corresponding to the input signal. The second voltage supply is higher than the first voltage supply. A leakage current control circuit includes a finisher transistor connected between the second voltage supply and the input to the output inverter and a path control transistor controlling a path between the first voltage supply and the input inverter.

In accordance with features of the invention, the level shifter circuit enables enhanced power and performance characteristics. The level shifter circuit reduces overall shoot through current while limiting shoot through current to one transition. The level shifter circuit enables reduced fan-in. The level shifter circuit is implemented with various static logic circuits, such as NAND level shifter gates and NOR level shifter gates.

In accordance with features of the invention, the finisher transistor is activated to provide the voltage level corresponding to the second voltage supply to the input to the output inverter and the path control transistor is turned off to open the path responsive to a one logic value of the first inverted signal.

In accordance with features of the invention, the finisher transistor is turned off responsive to a zero logic value of the first inverted signal and the path control transistor is activated to maintain the path between the first voltage supply and the input inverter.

In accordance with features of the invention, the finisher transistor is a P-channel field effect transistor (PFET) and the path control transistor is a PFET. In one embodiment, a gate of the finisher PFET is connected to the output of the output inverter of the level shifter circuit. The output of the output inverter is inverted and applied to a gate of the path control PFET. In another embodiment, a gate of the finisher PFET is connected by an inverter to the input of the output inverter of the level shifter circuit. The input of the output inverter is applied to a gate of the path control PFET. The input signal can be applied via an odd number of inverters to a gate of the path control PFET. The input of the output inverter can be applied via an even number of inverters to a gate of the path control PFET.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In accordance with features of the invention, level shifter circuits are provided having excellent power and performance characteristics. The novel level shifter circuits reduce overall shoot through current while limiting shoot through current, for example, to one transition. The novel level shifter circuits also reduce fan-in. The method for implementing the level shifter circuits advantageously is applied to various static logic circuits, for example, NAND and NOR level shifter gates.

Having reference now to the drawings, inFIG. 4Athere is shown an exemplary level shifter circuit generally designated by the reference character400in accordance with the preferred embodiment. Level shifter circuit400includes an input inverter402operating in a domain of a first power supply voltage VDDA. The input inverter receives an input signal INPUT and provides a first inverted signal OUTPUT_B. An output inverter404operating in a domain of a second power supply voltage VDDB coupled to the input inverter402that provides an output signal OUTPUT having a voltage level corresponding to the second voltage supply and a logic value corresponding to the input signal. The second power supply voltage VDDB is higher than the first power supply voltage VDDA.

The input inverter402is defined by a series connected P-channel field effect transistor (PFET)406and an N-channel field effect transistor (NFET)408. The output inverter404is defined by a series connected PFET410and NFET412connected between the second power supply voltage VDDB and ground. The input inverter output OUTPUT_B is applied to the output inverter404that provides the output OUTPUT.

Level shifter circuit400includes a leakage current control circuit414including a finisher transistor416connected between the second power supply voltage VDDB and the input to the output inverter404and a path control transistor418controlling a path between the first power supply voltage VDDA and the input inverter402. An inverter defined by a series connected PFET420and NFET422is connected between the second power supply voltage VDDB and ground having a common gate input connected to the OUTPUT and providing a gate input at a node FB to the path control PFET418. The finisher PFET416has a gate input connected to the OUTPUT.

It should be understood that the present invention is not limited to the level shifter circuit400as shown. For example, the path control PFET418could be provided between PFET406and NFET408, with PFET406connected to first power supply voltage VDDA.

Referring also toFIG. 4B, the operation of level shifter circuit400may be understood as follows. When the INPUT is a one logic value, such as at VDDA, OUTPUT_B is at ground (0V). OUTPUT is at the second voltage level VDDB, thus the finisher PFET416is off and FB is at 0 with the path control PFET418turned on to maintain the path between the first power supply voltage VDDA and the input inverter402. When the INPUT goes to a zero logic value (0V), OUTPUT_B rises to the first voltage level VDDA, OUTPUT falls to 0V which turns on the finisher PFET416and FB rises to VDDB. The path control PFET418turned off so that the path from OUTPUT_B to VDDA on the input gate402is cut off and the finisher PFET416is fully activated, causing the rise of OUTPUT_B to VDDB. Thus, level shifter circuit400avoiding DC current flow problems of prior art arrangements that result when the second voltage level VDDB is greater than a PFET threshold voltage above the first voltage level VDDA.

Referring toFIG. 5, there is shown an exemplary level shifter circuit generally designated by the reference character500in accordance with the preferred embodiment. Level shifter circuit500is a two input NAND level shifter circuit including a NAND gate502operating in a domain of a first power supply voltage VDDA. The NAND gate502receives a respective input signal INPUT1, and input signal INPUT2, and provides a NAND signal OUTPUT_B. An output inverter504operating in a domain of a second power supply voltage VDDB is coupled to the NAND gate502. The output inverter504provides an output signal OUTPUT having a voltage level corresponding to the second voltage supply and a logic value corresponding to the input signal. The second power supply voltage VDDB is higher than the first power supply voltage VDDA.

The NAND gate502is defined by a pair of PFETs503and505connected to a pair of series connected NFETs506and508that are connected between the drain of PFET503and ground. The output inverter504is defined by a series connected PFET510and NFET512connected between the second power supply voltage VDDB and ground. The NAND output OUTPUT_B is applied to the output inverter504that provides the output signal OUTPUT.

NAND level shifter circuit500includes a leakage current control circuit514including a finisher transistor516connected between the second power supply voltage VDDB and the input to the output inverter504and a path control transistor518controlling a path between the first power supply voltage VDDA and the NAND gate502. An inverter defined by a series connected PFET520and NFET522is connected between the second power supply voltage VDDB and ground having a common gate input connected to the OUTPUT and providing a gate input to the path control PFET518. The finisher PFET516has a gate input connected to the OUTPUT.

Operation of the leakage current control circuit514of NAND level shifter circuit500provides the same functions as the leakage current control circuit414of level shifter circuit400.

Referring toFIG. 6, there is shown another exemplary level shifter circuit generally designated by the reference character600in accordance with the preferred embodiment. Level shifter circuit600includes an input inverter602operating in a domain of a first power supply voltage VDDA. The input inverter receives an input signal INPUT and provides a first inverted signal OUTPUT_B. An output inverter604operating in a domain of a second power supply voltage VDDB coupled to the input inverter602that provides an output signal OUTPUT having a voltage level corresponding to the second voltage supply and a logic value corresponding to the input signal. The second power supply voltage VDDB is higher than the first power supply voltage VDDA.

The input inverter602is defined by a series connected P-channel field effect transistor (PFET)606and an N-channel field effect transistor (NFET)608. The output inverter604is defined by a series connected PFET610and NFET612connected between the second power supply voltage VDDB and ground. The input inverter output OUTPUT_B is applied to the output inverter604that provides the output signal OUTPUT.

Level shifter circuit600includes a leakage current control circuit614including a finisher transistor616connected between the second power supply voltage VDDB and the input to the output inverter604and a path control transistor618controlling a path between the first power supply voltage VDDA and the input inverter602. An even number of series connected inverters are arranged to provide at node FB a gate input to the path control transistor618. As shown, a pair of series connected inverters are respectively defined by a series connected PFET620and NFET622, and a series connected PFET624and NFET626is connected between the second power supply voltage VDDB and ground. A common gate input of PFET620and NFET622is connected to the OUTPUT_B. which provide a gate input to a common gate input of PFET624and NFET626. The inverted output of PFET624and NFET626at node FB provides the gate input to the path control PFET618. The finisher PFET616has a gate input connected to the OUTPUT.

Operation of the leakage current control circuit614of level shifter circuit600provides the same overall functions as the leakage current control circuit414of level shifter circuit400.

Referring toFIG. 7, there is shown another exemplary level shifter circuit generally designated by the reference character700in accordance with the preferred embodiment. Level shifter circuit700includes an input inverter702operating in a domain of a first power supply voltage VDDA. The input inverter receives an input signal INPUT and provides a first inverted signal OUTPUT_B. An output inverter704operating in a domain of a second power supply voltage VDDB coupled to the input inverter702that provides an output signal OUTPUT having a voltage level corresponding to the second voltage supply and a logic value corresponding to the input signal. The second power supply voltage VDDB is higher than the first power supply voltage VDDA.

The input inverter702is defined by a series connected P-channel field effect transistor (PFET)706and an N-channel field effect transistor (NFET)708. The output inverter704is defined by a series connected PFET710and NFET712connected between the second power supply voltage VDDB and ground. The input inverter output OUTPUT_B is applied to the output inverter704that provides the output signal OUTPUT.

Level shifter circuit700includes a leakage current control circuit714including a finisher transistor716connected between the second power supply voltage VDDB and the input to the output inverter704and a path control transistor718controlling a path between the first power supply voltage VDDA and the input inverter702. An inverter defined by a series connected PFET720and NFET722is connected between the first power supply voltage VDDA and ground having a common gate input connected to the INPUT and providing a gate input at a node FA to the path control PFET718. The finisher PFET716has a gate input connected to the OUTPUT.

Operation of the leakage current control circuit714of level shifter circuit700provides the same overall functions as the leakage current control circuit414of level shifter circuit400.

Referring toFIG. 8, there is shown another exemplary level shifter circuit generally designated by the reference character800in accordance with the preferred embodiment. Level shifter circuit800includes an input inverter802operating in a domain of a first power supply voltage VDDA. The input inverter receives an input signal INPUT and provides a first inverted signal OUTPUT_B. An output inverter804operating in a domain of a second power supply voltage VDDB coupled to the input inverter802that provides an output signal OUTPUT having a voltage level corresponding to the second voltage supply and a logic value corresponding to the input signal. The second power supply voltage VDDB is higher than the first power supply voltage VDDA.

The input inverter802is defined by a series connected PFET806and NFET808. The output inverter804is defined by a series connected PFET810and NFET812connected between the second power supply voltage VDDB and ground. The input inverter output OUTPUT_B is applied to the output inverter804that provides the output signal OUTPUT.

Level shifter circuit800includes a leakage current control circuit814including a finisher transistor816connected between the second power supply voltage VDDB and the input to the output inverter804and a path control transistor818controlling a path between the first power supply voltage VDDA and the input inverter802. An inverter defined by a series connected PFET820and NFET822is connected between the second power supply voltage VDDB and ground having a common gate input connected to the input inverter output OUTPUT_B and providing a gate input to the finisher PFET816. The path control transistor818has a gate input connected to the input inverter output OUTPUT_B.

Operation of the leakage current control circuit814of level shifter circuit800provides the same overall functions as the leakage current control circuit414of level shifter circuit400.

Referring toFIG. 9, there is shown another exemplary level shifter circuit generally designated by the reference character900in accordance with the preferred embodiment. Level shifter circuit900includes an input inverter902operating in a domain of a first power supply voltage VDDA. The input inverter receives an input signal INPUT and provides a first inverted signal OUTPUT_B. An output inverter904operating in a domain of a second power supply voltage VDDB coupled to the input inverter902that provides an output signal OUTPUT having a voltage level corresponding to the second voltage supply and a logic value corresponding to the input signal. The second power supply voltage VDDB is higher than the first power supply voltage VDDA.

The input inverter902is defined by a series connected P-channel field effect transistor (PFET)906and an N-channel field effect transistor (NFET)908. The output inverter904is defined by a series connected PFET910and NFET912connected between the second power supply voltage VDDB and ground. The input inverter output OUTPUT_B is applied to the output inverter904that provides the output signal OUTPUT.

Level shifter circuit900includes a leakage current control circuit914including a finisher transistor916connected between the second power supply voltage VDDB and the input to the output inverter904and a path control transistor918controlling a path between the first power supply voltage VDDA and the input inverter902. An even number of series connected inverters are arranged to provide at node FB a gate input to the path control transistor618. As shown, a pair of series connected inverters are respectively defined by a series connected PFET920and NFET922, and a series connected PFET924and NFET926is connected between the second power supply voltage VDDB and ground. A common gate input of PFET920and NFET922is connected to the OUTPUT_B, which provide a gate input to a common gate input of PFET924and NFET926. The inverted output of PFET924and NFET926at node FB provides the gate input to the path control PFET918. The inverted output of PFET920and NFET922provides the gate input to the finisher PFET916.

Operation of the leakage current control circuit914of level shifter circuit900provides the same overall functions as the leakage current control circuit414of level shifter circuit400.

Referring toFIG. 10, there is shown another exemplary level shifter circuit generally designated by the reference character1000in accordance with the preferred embodiment. Level shifter circuit1000includes fewer devices than the other embodiments ofFIGS. 4A,5,6,7, and9. Level shifter circuit1000includes an input inverter1002operating in a domain of a first power supply voltage VDDA. The input inverter receives an input signal INPUT and provides a first inverted signal OUTPUT_B. An output inverter1004operating in a domain of a second power supply voltage VDDB coupled to the input inverter1002that provides an output signal OUTPUT having a voltage level corresponding to the second voltage supply and a logic value corresponding to the input signal. The second power supply voltage VDDB is higher than the first power supply voltage VDDA.

The input inverter1002is defined by a series connected PFET1006and NFET1008. The output inverter1004is defined by a series connected PFET1010and NFET1012connected between the second power supply voltage VDDB and ground. The input inverter output OUTPUT_B is applied to the output inverter1004that provides the output signal OUTPUT.

Level shifter circuit1000includes a leakage current control circuit1014including a finisher transistor1016connected between the second power supply voltage VDDB and the input to the output inverter1004and a path control transistor1018controlling a path between the first power supply voltage VDDA and the input inverter1002. The input inverter output OUTPUT_B is applied to a gate input of the path control transistor1018. The finisher PFET1016has a gate input connected to the OUTPUT.

Operation of the leakage current control circuit1014of level shifter circuit1000provides the same functions as the leakage current control circuit414of level shifter circuit400.