Nonvolatile memory device and method of manufacturing the same

Provided are a nonvolatile memory device and a method of manufacturing the same. The device includes a semiconductor substrate; a source region and a drain region disposed in the semiconductor substrate and a channel region interposed between the source and drain regions; a first tunnel oxide layer disposed on the channel region near the source region; a second tunnel oxide layer disposed on the channel region near the drain region; a first charge trapping layer disposed on the first tunnel oxide layer; a second charge trapping layer disposed on the second tunnel oxide layer; a blocking oxide layer covering the first and second charge trapping layers; a charge isolation layer interposed between the first and second charge trapping layers; and a gate electrode disposed on the blocking oxide layer.

This application claims the priority of Korean Patent Application No. 2003-75781, filed on Oct. 29, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a nonvolatile memory device and a method of manufacturing the same.

2. Description of the Related Art

A nonvolatile semiconductor memory (NVSM) is categorized into a floating gate type or a metal insulator semiconductor (MIS) type in which two or more kinds of dielectric layers are stacked.

A floating type NVSM functions as a memory using potential wells, and an erasable programmable read only memory (EPROM) tunnel oxide (ETOX) structure is being widely used as a flash electrically erasable and programmable read only memory (flash EEPROM).

An MIS type NVSM functions as a memory using trap sites that exist between a dielectric layer and a bulk or between dielectric layers. Typically, the MIS type NVSM can be classified into a metal-oxide-nitride-oxide-silicon (MONOS) type, a silicon-oxide-nitride-oxide-silicon (SONOS) type, and the likes.

FIG. 1is a cross-sectional view of a conventional NVSM having a MONOS or SONOS type structure.

Referring toFIG. 1, a source region16S and a drain region16D are disposed in a semiconductor substrate11and separated apart from each other. A tunnel oxide layer12, a charge trapping layer13, a blocking oxide layer14, and a gate electrode15are sequentially stacked on a channel region17interposed between the source and drain regions16S and16D. Insulating spacers18are formed on the sidewalls of the stacked structure. The tunnel oxide layer12is formed of thermal oxide, the charge trapping layer13is formed of silicon nitride, and the blocking oxide layer14is formed of oxide using wet oxidation or chemical vapor deposition (CVD). In the case of the MONOS type, the gate electrode15is formed of a metal. In the case of the SONOS type, the gate electrode15is formed of doped polysilicon.

The programming and erasing of the conventional NVSM will be described now.

At the outset, during programming, if a sufficiently high positive (+) voltage is applied to the gate electrode15, electrons emitted from the semiconductor substrate11tunnel the tunnel oxide layer12and are injected into the charge trapping layer13. In this case, the blocking oxide layer14disposed on the charge trapping layer13prevents the electrons injected in the charge trapping layer14from leaking into the gate electrode15and also prevents injection of holes from the gate electrode15into the charge trapping layer13. The electrons, which are injected into the charge trapping layer13through the tunnel oxide layer12, are trapped in a bulk trap of the charge trapping layer13or in an interfacial trap between the charge trapping layer13and the blocking oxide layer14, and a threshold voltage increases.

During erasing, by applying a negative (−) voltage to the gate electrode15, the trapped electrons are emitted to the semiconductor substrate11so that a threshold voltage is reduced to the same value as before programming.

In recent years, with the developments in nanotechnologies, much research into the use of an NVSM and a 2-bit-per-cell NVSM using nano-crystals has been conducted.

FIG. 2is a cross-sectional view of a conventional NVSM using nano-crystals.

Referring toFIG. 2, a source region26S and a drain region26D are disposed in a semiconductor substrate21and separated apart from each other. A tunnel oxide layer22, a charge trapping layer23, a blocking oxide layer24, and a gate electrode25are sequentially stacked on a channel region27interposed between the source and drain regions26S and26D. Insulating spacers28are disposed on the sidewalls of the stacked structure. The charge trapping layer23is formed of clusters or dots having a size of several to several tens of nm, namely, nano-crystals23NC.

A method of manufacturing the charge trapping layer23formed of the nano-crystals23NC is disclosed in the following two papers.

(I) “A Silicon Nanocrystals Based Memory by Sandip Tiwari et al., Appl. Phys. Lett. 68(10) p. 1377(1996)”: A tunnel oxide layer having a thickness of 1.1 to 1.8 nm is formed on a semiconductor substrate in which source and drain regions are disposed. Nanocrystals having a diameter of 5 nm, which constitute a charge trapping layer, are formed on the tunnel oxide layer by a space of 5 nm using a CVD apparatus. The density of the nanocrystals is about 1×1012/cm−2. A 7-nm blocking oxide layer is formed on the charge trapping layer, and a gate electrode is formed on the blocking oxide layer.

(II) “Fast and Long Retention-Time nano-Crystal Memory by Hussein I. Hanafi et al., IEEE Trans. Electron Device, Vo1. 43, p. 1553(1996)”: A 5 to 20-nm oxide layer is formed on a semiconductor substrate. A high concentration of Si or Ge ions are implanted into the oxide layer and supersaturated. In this case, the ions are implanted with about 5 KeV and a dose of about 5×1015ions/cm2. The doped oxide layer is annealed in an N2atmosphere at 950° C. for 30 minutes, thereby growing Si or Ge nano-crystals in the oxide layer to a diameter of 5 nm. A source region and a drain region are formed in the semiconductor substrate and separated a predetermined distance apart from each other, and a gate electrode is formed on a portion of the oxide layer corresponding to a channel region interposed between the source and drain regions.

The conventional NVSMs using nano-crystals have the advantages of the foregoing conventional MONOS or SONOS type NVSMs. Also, charges, which are injected into nano-crystals of a charge trapping layer, cannot easily move between the nano-crystals. Accordingly, in comparison with the conventional MONOS or SONOS type NVSMs, NVSMs using nano-crystals can suppress lateral diffusion of charges, be effectively embodied as 2-bit-per-cell NVSMs, and be easily downscaled.

However, when a conventional NVSM using nano-crystals is embodied as a 2-bit-per-cell memory, it is very difficult to scale down the NVSM to a nanoscale or terascale ultrahigh-integrated device. For example, to manufacture a 2-bit-per-cell device, charges are partially injected into charge trapping layers adjacent to source and drain regions. In the case of a short channel, both a superposition effect and a lateral diffusion of charges occur during the injection of the charges, thus disturbing 2-bit-per-cell operations of the NVSM. To solve this problem, channel length should be maintained above a predetermined value. In this case, it is impossible to further scale down NVSMs and further increase the integration density thereof. Accordingly, the foregoing conventional NVSMs using nano-crystals cannot meet the requisitions of the next-generation semiconductor technologies, such as low voltage, subminiature size, ultrahigh integration, high performance, and high reliability.

SUMMARY OF THE INVENTION

The present invention provides a nonvolatile semiconductor memory device (NVSM), which meets the requisitions of the next-generation semiconductor technologies, such as low voltage, subminiature size, ultrahigh integration, high performance, and high reliability, writes at least two bits per cell, and can be downscaled to a nanoscale size or less.

Also, the present invention provides a method of manufacturing the above-described NVSM.

According to an aspect of the present invention, there is provided an NVSM comprising a semiconductor substrate; a source region and a drain region disposed in the semiconductor substrate and a channel region interposed between the source and drain regions; a first tunnel oxide layer disposed on the channel region near the source region; a second tunnel oxide layer disposed on the channel region near the drain region; a first charge trapping layer disposed on the first tunnel oxide layer; a second charge trapping layer disposed on the second tunnel oxide layer; a blocking oxide layer covering the first and second charge trapping layers; a charge isolation layer interposed between the first and second charge trapping layers; and a gate electrode disposed on the blocking oxide layer.

Each of the first and second tunnel oxide layers may be about 1 to 5 nm thick.

Each of the first and second charge trapping layers may be about 15 to 100 nm in length.

Each of the first and second charge trapping layers may include a plurality of nano-crystals having the form of clusters or dots.

The first and second charge trapping layers may be formed of at least one selected from the group consisting of tungsten, molybdenum, cobalt, nickel, platinum, rhodium, palladium, and iridium, or a mixture or alloy thereof.

The first and second charge trapping layers may be formed of one selected from the group consisting of silicon, germanium, a mixture of silicon and germanium, III–V group compounds, and II–VI group compounds.

The charge isolation layer may be about 10 to 100 nm in length, and the blocking oxide layer may be about 3 to 150 nm thick.

According to another aspect of the present invention, there is provided a method of manufacturing an NVSM. The method includes forming an oxide layer on a semiconductor substrate, wherein the semiconductor substrate is divided into a source section, a gate section, and a drain section, and the gate section includes a first charge trapping section, a charge isolation section, and a second charge trapping section; implanting impurity ions into a portion of the oxide layer formed in the first and second charge trapping sections separated by the charge isolation section; forming a plurality of nano-crystals in the portion of the oxide layer formed in the first and second charge trapping sections by crystallizing the implanted impurity ions using crystallization annealing; and depositing a gate electrode material on the portion of the oxide layer in which the nano-crystals are embedded and removing the gate electrode material and the oxide layer except in the gate section using a gate etching process.

According to yet another aspect of the present invention, there is provided a method of manufacturing an NVSM. The method includes forming a first oxide layer on a semiconductor substrate, wherein the semiconductor substrate is divided into a source section, a gate section, and a drain section, and the gate section includes a first charge trapping section, a charge isolation section, and a second charge trapping section; implanting impurity ions into the first oxide layer; forming a plurality of nano-crystals in the first oxide layer by crystallizing the implanted impurity ions using crystallization annealing; forming an etch preventing pattern and etch preventing spacers on a portion of the first oxide layer in which the nano-crystals are embedded, such that the a portion of first oxide layer formed in the charge isolation section is exposed; forming a hole in the first oxide layer by etching the first oxide layer using the etch preventing pattern and the etch preventing spacers as an etch mask, such that the hole separates the portion of the first oxide layer in which the nano-crystals are embedded from the remaining portion thereof; removing the etch preventing pattern and the etch preventing spacers and forming a second oxide layer such that the hole is filled with the second oxide layer; and depositing a gate electrode material on the portion of the first oxide layer in which the nano-crystals are embedded and the second oxide layer and etching the gate electrode material and the first oxide layer except in the gate section using a gate etching process.

According to further another aspect of the present invention, there is a method of manufacturing an NVSM. The method includes forming a first oxide layer on a semiconductor substrate, wherein the semiconductor substrate is divided into a source section, a gate section, and a drain section, and the gate section includes a first charge trapping section, a charge isolation section, and a second charge isolation section; forming a plurality of nano-crystals on the first oxide layer; forming a second oxide layer on the first oxide layer on which the nano-crystals are formed; forming an etch preventing pattern and etch preventing spacers on a portion of the second oxide layer in which the nano-crystals are embedded, such that a portion of the second oxide layer formed in the charge isolation region is exposed; forming a hole in the first and second oxide layers by etching the first and second oxide layers using the etch preventing pattern and the etch preventing spacers as an etch mask, such that the hole separates the portion of the second oxide layer in which the nano-crystals are embedded from the remaining portion thereof; removing the etch preventing pattern and the etch preventing spacers and forming a third oxide layer such that the hole is filled with the third oxide layer; and depositing a gate electrode material on the portion of the second oxide layer in which the nano-crystals are embedded and the third oxide layer and removing the gate electrode material and the first and second oxide layers except in the gate section using a gate etching process.

According to still further another aspect of the present invention, there is provided a method of manufacturing an NVSM. The method includes sequentially forming a first oxide layer and a polysilicon layer on a semiconductor substrate, wherein the semiconductor substrate is divided into a source section, a gate section, and a drain section, and the gate section includes a first charge trapping section, a charge isolation section, and a second charge trapping section; forming an oxidation preventing pattern and an oxidation preventing spacers on the polysilicon layer such that a portion of the polysilicon layer formed in the charge isolation region is exposed; forming a second oxide layer on the exposed portion of the polysilicon layer by performing an oxidation process using the oxidation preventing pattern and the oxidation preventing spacers; removing the oxidation preventing pattern and the oxidation preventing spacers and forming a polysilicon pattern by etching the polysilicon layer using the second oxide layer as an etch mask; implanting impurity ions into the first oxide layer using the polysilicon pattern as a mask; forming a plurality of nano-crystals by crystallizing the implanted ions using crystallization annealing; forming polysilicon layer spacers on the both sidewalls of the polysilicon pattern and completing a gate electrode comprised of the polysilicon pattern and the polysilicon layer spacers; and removing the second oxide layer and an exposed portion of the first oxide layer.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 3is a cross-sectional view of a nonvolatile semiconductor memory device (NSVM) writing two bits per cell according to the present invention.

Referring toFIG. 3, a semiconductor substrate31, in which an active region is defined by forming an isolation layer (not shown), is provided. A source region36S and a drain region36D, between which a channel region37is interposed, are disposed in the semiconductor substrate31and separated apart from each other. A first tunnel oxide layer32L is disposed on the channel region37near the source region36S, and a second tunnel oxide layer32R is disposed on the channel region37near the drain region36D. The first and second tunnel oxide layers32L and32R are separated from each other by a charge isolation layer33C. A first charge trapping layer33L is disposed on the first tunnel oxide layer32L, and a second charge trapping layer33R is disposed on the second tunnel oxide layer32R. The first and second charge trapping layer33L and33R are separated from each other by the charge isolation layer33C. A blocking oxide layer34covers the first and second charge trapping layers33L and33R. A gate electrode35is disposed on the blocking oxide layer34. Insulating spacers38are formed on the sidewalls of the above-described stacked structure including the gate electrode35.

Meanwhile, each of the first and second charge trapping layers33L and33R includes a plurality of nano-crystals33NC. The nano-crystals33NC look to be stuck in a lower end portion of the blocking oxide layer34.

A distance between the source and drain regions36S and36D is several tens to several hundreds of nm. Thus, the channel region37scales several tens to several hundreds of nm. The first and second tunnel oxide layers32L and32R each have a thickness of several nm, for example, about 1 to 5 nm, and the lengths thereof depend on the lengths of the first and second charge trapping layers33L and33R, respectively. The first and second tunnel oxide layers32L and33R each may have a larger thickness than described above, but are preferably as thin as possible to achieve successful erasing, low programming voltage, and rapid programming unless other problems are generated.

Each of the first and second charge trapping layers33L and33R includes the plurality of nano-crystals33NC, which look like clusters or dots having a size of several to several tens of nm, for example, about 1 to 15 nm. Each of the nano-crystals33NC operates independently by 1 bit, has a length of about 15 to 100 nm, and is formed of a semiconductor or a metal. A space between the nano-crystals33NC may be several to several tens of nm, for example, about 1 to 10 nm, but preferably 5 to 10 nm to prevent disturbance caused by lateral diffusion of charges.

Normally, if a space between nano-crystals is less than 5 nm, lateral diffusion occurs between charges injected into a charge trapping layer near a source region and charges injected into a charge trapping layer near a drain region, thereby disturbing 2-bit-per-cell operations.

However, the NVSM of the present invention includes the first and second charge trapping layers33L and33R, which are isolated by the charge isolation layer33C. Thus, even if a space between the nano-crystals33NC is less than 5 nm, 2-bit-per-cell operations are not disturbed.

The first and second charge trapping layers33L and33R may be formed of at least one selected from the group consisting of tungsten, molybdenum, cobalt, nickel, platinum, rhodium, palladium, and iridium. Also, the first and second charge trapping layers33L and33R may be formed of a mixture or an alloy containing at least one selected from the group consisting of tungsten, molybdenum, cobalt, nickel, platinum, rhodium, palladium, and iridium. Also, the first and second charge trapping layers33L and33R may be formed of a semiconductor selected from the group consisting of silicon, germanium, a mixture of silicon and germanium, III–V group compounds (combinations of III group elements such as Al, Ga, and In and V group elements such as P, As, and Sb), and II–VI group compounds (combinations of II group elements such as Zn, Cd, and Hg and VI group elements such as O, S, Se, and Te).

The charge isolation layer33C corresponds to a region disposed on the channel region37, where the nano-crystals33NC are not formed. The charge isolation layer33C is formed of the same material as the first and second tunnel oxide layers32L and32R and the blocking oxide layer34. To prevent the lateral diffusion of charges between the first and second trapping layers33L and33R, the length of the charge trapping layer33C may be 5 nm or more. However, to enhance reliability, the length of the charge isolation layer33C is preferably at least 10 nm, for example, about 10 to 100 nm. The blocking oxide layer34prevents electrons injected in the first and second charge trapping layers33L and33R from leaking in the gate electrode35and also prevents injection of holes from the gate electrode35into the charge trapping layers33L and33R. Accordingly, the blocking oxide layer34may be at least thicker than the first and second tunnel oxide layers32L and32R. Therefore, the blocking oxide layer34may be, for example, 3 to 150 nm thick, but is preferably 6 to 70 nm thick to facilitate the function of the blocking oxide layer34and the downscaling of the NVSM.

In the meantime, all the foregoing or the following ranges of numerical values include not only those being applied to conventional devices but also those that cannot be applied to the conventional devices due to some problems caused by the downscaling of devices. In the present invention, since the first and second charge isolation layers33L and33R are isolated by the charge isolation layer33C, the problems of the conventional NVSM using nano-crystals can be solved. Therefore, an NVSM, which meets low voltage, subminiature size, ultrahigh integration, high performance, and high reliability, can be obtained.

The gate electrode35may be formed of any conductive material for a typical gate electrode, for example, polysilicon, a metal, or a polycide including metal-silicide formed on polysilicon. As the linewidth of the gate electrode35becomes smaller owing to the high integration of semiconductor devices, the gate electrode35may be formed of a highly conductive metal or a polycide rather than polysilicon in order to suppress an increase in resistance.

The conditions under which the foregoing NVSM of the present invention operates are basically the same as or similar to those under which conventional NVSMs having a MONOS or SONOS structure or conventional NVSMs using nano-crystals operate. Therefore, the conditions under which the NVSM of the present invention operate will not be presented here.

Hereinafter, a method of manufacturing the foregoing NVSM according to the present invention will be described.

FIGS. 4A through 4Eare cross-sectional views illustrating a method of manufacturing the NVSM shown inFIG. 3according to a first embodiment of the present invention.

Referring toFIG. 4A, an isolation layer (not shown) is formed in a semiconductor substrate31using a typical isolation technique, thereby defining an active region. The active region of the semiconductor substrate31is divided into a section where a source region will be formed (hereinafter, a source section S), a section where a gate will be formed (hereinafter, a gate section G), and a section where a drain region will be formed (hereinafter, a drain section D) according to design rules. The gate section G includes a section where a first charge trapping layer will be formed (hereinafter, a first charge trapping section GL), a section where a charge isolation layer will be formed (hereinafter, a charge isolation section GC), and a section where a second charge trapping layer will be formed (hereinafter, a second charge trapping section GR). The first charge trapping section GL is connected to the source section S, the second charge trapping section GR is connected to the drain section D, and the charge isolation section GC is interposed between the first and second charge trapping sections GL and GR. An oxide layer41is formed on the semiconductor substrate31. The oxide layer41is formed to a thickness equivalent to the sum of the thickness of a tunnel oxide layer, the size of nano-crystals forming a charge trapping layer, and the thickness of a blocking oxide layer, which will be defined later. Thus, the oxide layer41is formed to a thickness of about 5 to 170 nm using an ordinary oxidation process. The range of about 5 to 170 nm is obtained from a minimum and a maximum of the sum of thicknesses of the respective elements as described with reference toFIG. 3.

Referring toFIG. 4B, a first photoresist pattern42is formed on the oxide layer41while exposing the first charge trapping section GL and at least a portion of the source section S. A first ion implantation process is performed using the first photoresist pattern42as an ion implantation mask, thereby implanting metal ions or semiconductor ions into the oxide layer41. As a result, a first ion implantation region33LI is formed in the oxide layer41.

The first ion implantation region33LI is an important element that determines the thickness of a tunnel oxide layer that will be defined later. Thus, since the first ion implantation process is performed at an appropriate energy considering that the thickness of the first tunnel oxide layer32L shown inFIG. 3is 1 to 5 nm, the first ion implantation region33LI can be formed about 1 to 5 nm apart from the semiconductor substrate31.

Referring toFIG. 4C, the first photoresist pattern42is removed. A second photoresist pattern43is formed on the oxide layer41while exposing the second charge trapping section GR and at least a portion of the drain section D. A second ion implantation process is implemented using the second photoresist pattern43as an ion implantation mask, thereby implanting metal ions or semiconductor ions into the oxide layer41. As a result, a second ion implantation region33RI is formed in the oxide layer41. When the first and second ion implantation processes using the first and second photoresist patterns42and43are finished, a portion of the oxide layer41formed in the charge isolation section GC is not doped with ions.

The second ion implantation region33RI is formed under the same conditions under which the first ion implantation region33LI is formed, except for positions. That is, the second ion implantation process is performed in the same manner as the first ion implantation process.

Referring toFIG. 4D, the second photoresist pattern43is removed, and the resultant structure from which the second photoresist pattern43is removed is annealed using crystallization annealing. As a result, the metal or semiconductor ions existing in the first and second ion implantation regions33LI and33RI are crystallized so that a plurality of nano-crystals33NC are formed in the first and second ion implantation regions33LI and33RI.

If the nano-crystals33NC are formed of Si or Ge, the crystallization annealing is performed in an N2atmosphere at 950° C. for 30 minutes. If the nano-crystals33NC are formed of other semiconductor or metal than Si or Ge, the crystallization annealing is performed under conditions of gaseous atmosphere, temperature, and time appropriate for the material. The nano-crystals33NC have the form of clusters or dots having a size of several to several tens of nm, for example, about 1 to 15 nm. Also, a space between the nano-crystals33NC is several to several tens of nm, for example, about 1 to 10 nm, preferably, about 5 to 10 nm. The size and space of the nano-crystals33NC can be adjusted by controlling the conditions of the first and second ion implantation processes or the crystallization annealing.

Thereafter, a gate electrode material (not shown) is deposited on the oxide layer41in which the nano-crystals33NC are embedded. Next, the gate electrode material and the oxide layer41are etched using a gate mask (not shown) covering the gate section G as an etch mask until the semiconductor substrate31is exposed. Then, the gate mask is removed. As a result, a gate electrode35is formed on a blocking oxide layer34and a charge isolation layer33C, as shown inFIG. 4E. Thereafter, conductive impurity ions are implanted into the source and drain sections S and D, thereby forming a source region36S and a drain region36D. Thus, the NVSM shown inFIG. 3is completed.

In the first embodiment, the first and second tunnel oxide layers32L and32R are divided from the blocking oxide layer34by the nano-crystals33NC embedded in the oxide layer41. Thus, each of the first and second tunnel oxide layers32L and32R is about 1 to 5 nm thick, and the blocking oxide layer34is about 3 to 150 nm thick. The first charge trapping layer33L includes nano-crystals33NC embedded in a portion of the oxide layer41formed in the first charge trapping section GL, while the second charge trapping layer33R includes nano-crystals embedded in a portion of the oxide layer41formed in the second charge trapping section GR. As a result of the gate etching process, each of the first and second charge trapping layers33L and33R becomes about 15 to 100 nm thick. The charge isolation layer33C corresponds to a region of the oxide layer41where no nano-crystals33NC exist, and has a length of 10 to 100 nm. A distance between the source and drain regions36S and36D disposed on both sides of the gate electrode35is several tens to several hundreds of nm and thus, the channel region37also scales several tens to several hundreds of nm.

FIGS. 5A through 5Fare cross-sectional views illustrating a method of manufacturing the NVSM shown inFIG. 3according to a second embodiment of the present invention.

Referring toFIG. 5A, an isolation layer (not shown) is formed in a semiconductor substrate31using an ordinary isolation technique, thereby defining an active region. The active region of the semiconductor substrate31is divided into a source section S, a gate section G, and a drain section D according to design rules. The gate section G includes a first charge trapping section GL, a charge isolation section GC, and a second charge trapping section GR. The first charge trapping section GL is connected to the source section S, and the second charge trapping section GR is connected to the drain section D. The charge isolation section GC is interposed between the first and second charge trapping sections GL and GR. A first oxide layer51is formed on the semiconductor substrate31. The first oxide layer51is preferably formed to a thickness equivalent to the sum of the thickness of a tunnel oxide layer, the size of nano-crystals forming a charge trapping layer, and the thickness of a blocking oxide layer, which will be defined later, but may be formed thicker or thinner than a desired thickness because the thickness of the first oxide layer51can be controlled during subsequent processes. Thus, the first oxide layer51is formed using an ordinary oxidation process to a thickness of about 5 to 170 nm or thinner or thicker. The range of about 5 to 170 nm is obtained from a minimum and a maximum of the sum of thicknesses of the respective elements as described with reference toFIG. 3. Then, metal ions or semiconductor ions are implanted into the first oxide layer51, thereby forming an ion implantation region33I.

The ion implantation region33I is an important element that determines the thickness of a tunnel oxide layer that will be defined later. Thus, since the ion implantation process is performed at an appropriate energy considering that each of the first and second tunnel oxide layers32L and32R shown inFIG. 3is 1 to 5 nm thick, the ion implantation region33I can be formed about 1 to 5 nm apart from the semiconductor substrate31.

Referring toFIG. 5B, the metal or semiconductor ions of the ion implantation region33I are crystallized using crystallization annealing, thereby forming a plurality of nano-crystals33NC. For example, if the nano-crystals33NC are formed of Si or Ge, the crystallization annealing is performed in an N2atmosphere at 950° C. for 30 minutes. If the nano-crystals33NC are formed of other semiconductor or metal than Si or Ge, the crystallization annealing is performed under conditions of gaseous atmosphere, temperature, and time appropriate for the material. The nano-crystals33NC have the form of clusters or dots having a size of several to several tens of nm, for example, about 1 to 15 nm. Also, a space between the nano-crystals33NC is several to several tens of nm, for example, 1 to 10 nm, preferably, 5 to 10 nm. The size and space of the nano-crystals33NC can be adjusted by controlling the conditions of the ion implantation process or the crystallization annealing.

Referring toFIG. 5C, an etch preventing pattern52is formed on the first oxide layer51in which the nano-crystals33NC are embedded, while exposing the gate section G. Also, etch preventing spacers53are formed on the sidewalls of the etch preventing pattern52. Thus, a window that exposes a portion of the first oxide layer51formed in the charge isolation section GC is formed by the etch preventing pattern52and the etch preventing spacers53. The etch preventing pattern52and the etch preventing spacers53are formed of a material having a high etch selectivity with respect to oxide, for example, polysilicon or nitride. The window is a space where the charge isolation layer33C shown inFIG. 3is formed through subsequent etch process and oxide layer filling process. This window should be formed to a length of about 10 to 100 nm. A conventional exposure apparatus fails to obtain the 10 to 100-nm window. Accordingly, to form the 10 to 100 nm window, the etch preventing pattern52is first formed using a conventional exposure apparatus, and then the etch preventing spacers53are formed on the sidewalls of the etch preventing pattern52by controlling the thickness.

Referring toFIG. 5D, the first oxide layer51is etched using the etch preventing pattern52and the etch preventing spacers53as an etch mask, thereby forming a hole54. During this etching process, an etch target is preferably set such that the nano-crystals33NC embedded in the first oxide layer51are removed but the semiconductor substrate31is not exposed. If the etch preventing pattern52and the etch preventing spacers53are removed later while the semiconductor substrate31is being exposed, the semiconductor substrate31gets etch damage so that the electrical characteristics of the NVSM may be degraded.

Referring toFIG. 5E, the etch preventing pattern52and the etch preventing spacers53are removed, and then a second oxide layer55is filled in the hole54. The filling of the second oxide layer55may be performed using the following two methods. First, an oxide layer is deposited on the first oxide layer51including the hole54, planarized using chemical mechanical polishing (CMP) or the like, and then cleaned such that the second oxide layer55is filled in the hole54. In this method, even if the first oxide layer51was initially formed thinner or thicker than a desired thickness (i.e., about 5 to 170 nm), the final thickness of the first oxide layer51can reach the desired thickness by the planarization and cleaning processes. Second, an oxide layer is grown using thermal oxidation so that the second oxide layer55is filled in the hole54. During the thermal oxidation, oxide is grown slowly on the first oxide layer51, while oxide is grown rapidly on the semiconductor substrate31disposed on the bottom surface of the hole54.

Referring toFIG. 5F, a gate electrode material is deposited on the first oxide layer52in which the nano-crystals33NC are embedded and the second oxide layer51filled in the hole54. Next, the gate electrode material and the first oxide layer51are etched using a gate mask (not shown) covering the gate section G as an etch mask, thereby forming a gate electrode35. Then, a source region36S and a drain region36D are formed by implanting ions into the source and drain sections S and D, respectively, and insulating spacers38are formed. As a result, the NVSM shown inFIG. 3is completed.

In the second embodiment, the first and second tunnel oxide layers32L and32R are divided from the blocking oxide layer34by the nano-crystals33NC embedded in the first oxide layer51. Thus, each of the first and second tunnel oxide layers32L and32R is about 1 to 5 nm thick, and the blocking oxide layer34is about 3 to 150 nm thick. The first charge trapping layer33L includes nano-crystals33NC embedded in a portion of the first oxide layer51formed in the first charge trapping section GL, while the second charge trapping layer33R includes nano-crystals embedded in a portion of the first oxide layer51formed in the second charge trapping section GR. As a result of the gate etching process, each of the first and second charge trapping layers33L and33R becomes about 15 to 100 nm thick. The charge isolation layer33C corresponds to a region of the second oxide layer55where no nano-crystals33NC exists, and has a length of 10 to 100 nm. A distance between the source and drain regions36S and36D disposed on both sides of the gate electrode35is several tens to several hundreds of nm and thus, the channel region37also scales several tens to several hundreds of nm.

FIGS. 6A through 6Eare cross-sectional views illustrating a method of manufacturing the NVSM shown inFIG. 3according to a third embodiment of the present invention.

Referring toFIG. 6A, an isolation layer (not shown) is formed in a semiconductor substrate31using an ordinary isolation technique, thereby defining an active region. The active region of the semiconductor substrate31is divided into a source section S, a gate section G, and a drain section D, and the gate section G includes a first charge trapping section GL, a charge isolation section GC, and a second charge trapping section GR. The first charge trapping section GL is connected to the source section S, the second charge trapping section GR is connected to the drain section D, and the charge isolation section GC is interposed between the first and second charge trapping sections GL and GR. A first oxide layer61is formed on the semiconductor substrate31. The first oxide layer61functions as the tunnel oxide layers32L and32R shown inFIG. 3and is formed using thermal oxidation to a thickness of about 1 to 5 nm. A plurality of nano-crystals33NC are formed on the first oxide layer61by performing deposition using a CVD apparatus. The nano-crystals33NC are formed of a metal or a semiconductor in the form of clusters or dots having a size of several to several tens of nm, for example, about 1 to 15 nm. A space between the nano-crystals33NC is several to several tens of nm, for example, about 1 to 10 nm, preferably, 5 to 10 nm. The size and space of the nano-crystals33NC can be adjusted by controlling conditions under which the CVD process is performed. A second oxide layer62is formed on the first oxide layer61on which the nano-crystals33NC are formed. The second oxide layer62functions as the blocking oxide layer34shown inFIG. 3and is formed using an ordinary oxidation process to a thickness of about 3 to 150 nm. However, the second oxide layer62may be formed thicker or thinner than a desired thickness at this moment since its thickness can be controlled during subsequent processes.

Referring toFIG. 6B, an etch preventing pattern63is formed on the second oxide layer62in which the nano-crystals33NC are embedded, such that the gate section G is exposed. Then, etch preventing spacers64are formed on the sidewalls of the etch preventing pattern63. Thus, a window that exposes a portion of the second oxide layer62formed in the charge isolation section GC is formed by the etch preventing pattern63and the etch preventing spacers64. The etch preventing pattern63and the etch preventing spacers64are formed of a material having a high etch selectivity with respect to oxide, for example, polysilicon or nitride.

The window is a space where the charge isolation layer33C shown inFIG. 3is formed using subsequent etching process and oxide filling process. The window is formed to a length of about 10 to 100 nm.

A process of forming the window is as follows.

Specifically, the etch preventing pattern63is first formed using an exposure apparatus, and then the etch preventing spacers64are formed on the sidewalls of the etch preventing pattern63by controlling the thickness, such that the window has a length of about 10 to 100 nm.

Referring toFIG. 6C, the first and second oxide layers61and62are etched using the etch preventing pattern63and the etch preventing spacers64as an etch mask, thereby forming a hole65. During the etching process, an etch target is set such that the nano-crystals33NC embedded in the second oxide layer62are removed but the semiconductor substrate31is not exposed due to the remaining first oxide layer61. If the etch preventing pattern62and the etch preventing spacers63are removed later while the semiconductor substrate31is being exposed, the semiconductor substrate31gets etch damage so that the electrical characteristics of the NVSM may be degraded.

Referring toFIG. 6D, the etch preventing pattern63and the etch preventing spacers64are removed, and then a third oxide layer66is filled in the hole65. The filling of the third oxide layer66may be performed using the following two methods. First, an oxide layer is deposited on the second oxide layer62including the hole65, planarized using CMP or the like, and then cleaned such that the third oxide layer66is filled in the hole65. In this method, even if the second oxide layer62was initially formed thinner or thicker than a desired thickness (i.e., about 5 to 170 nm), the final thickness of the second oxide layer62can reach the desired thickness by the planarization and cleaning processes. Second, an oxide layer is grown using thermal oxidation so that the third oxide layer66is filled in the hole65. During the thermal oxidation, oxide is grown slowly on the second oxide layer62, while oxide is grown rapidly on the semiconductor substrate31disposed on the bottom surface of the hole65.

Referring toFIG. 6E, a gate electrode material is deposited on the second oxide layer62in which the nano-crystals33NC are embedded and the third oxide layer66filled in the hole65. Next, the gate electrode material and the first and second oxide layers61and62are etched using a gate mask (not shown) covering the gate section G as an etch mask, thereby forming a gate electrode35. Then, a source region36S and a drain region36D are formed by implanting ions into the source and drain sections S and D, respectively, and insulating spacers38are formed. As a result, the NVSM shown inFIG. 3is completed.

In the third embodiment, during the gate etching process, the first oxide layer61functions as the first and second tunnel oxide layers32L and32R shown inFIG. 3, and the second oxide layer62functions as the blocking oxide layer34shown inFIG. 3. The first charge trapping layer33L includes nano-crystals33NC embedded in a portion of the second oxide layer62formed in the first charge trapping section GL, while the second charge trapping layer33R includes nano-crystals embedded in a portion of the second oxide layer62formed in the second charge trapping section GR. As a result of the gate etching process, each of the first and second charge trapping layers33L and33R becomes about 15 to 100 nm thick. The charge isolation layer33C corresponds to a region of the third oxide layer66where no nano-crystals33NC exists, and has a length of 10 to 100 nm. A distance between the source and drain regions36S and36D disposed on both sides of the gate electrode35is several tens to several hundreds of nm and thus, the channel region37also scales several tens to several hundreds of nm.

FIGS. 7A through 7Fare cross-sectional views illustrating a method of manufacturing the NVSM shown inFIG. 3according to a fourth embodiment of the present invention.

Referring toFIG. 7A, an isolation layer (not shown) is formed in a semiconductor substrate31using an ordinary isolation technique, thereby defining an active region. The active region of the semiconductor substrate31is divided into a source section S, a gate section G, and a drain section D according to design rules, and the gate section G includes a first charge trapping section GL, a charge isolation section GC, and a second charge trapping section GR. The first charge trapping section GL is connected to the source section S, the second charge trapping section GR is connected to the drain section D, and the charge isolation section GC is interposed between the first and second charge trapping sections GL and GR. A first oxide layer71is formed on the semiconductor substrate31. The first oxide layer71is formed to a thickness equivalent to the sum of the thickness of a tunnel oxide layer, the size of nano-crystals forming a charge trapping layer, and the thickness of a blocking oxide layer, which will be defined later. Thus, the first oxide layer71is formed to a thickness of about 5 to 90 nm using an ordinary oxidation process. The range of about 5 to 90 nm is obtained from a minimum and a maximum of the sum of thicknesses of the respective elements as described with reference toFIG. 3. A doped polysilicon layer72for a gate electrode is formed on the first oxide layer71. An oxidation preventing pattern73is formed on the doped polysilicon layer72such that the gate section G is exposed, and oxidation preventing spacers74are formed on the sidewalls of the oxidation preventing pattern73. By the oxidation preventing pattern73and the oxidation preventing spacers74, a window that exposes a portion of the doped polysilicon layer72formed in the charge isolation section GC is formed. The oxidation preventing pattern73and the oxidation preventing spacers74are formed of nitride. The window is a space where the charge isolation layer33C shown inFIG. 3will be formed and should be formed to a length of about 10 to 100 nm. A conventional exposure apparatus fails to obtain the 10 to 100 nm window. Accordingly, to form the 10 to 100 nm window, the oxidation preventing pattern73is first formed using a conventional exposure apparatus, and then the oxidation preventing spacers74are formed on the sidewalls of the etch preventing pattern74by controlling the thickness.

Referring toFIG. 7B, by performing an oxidation process using the oxidation preventing pattern73and the oxidation preventing spacers74, a second oxide layer75is formed on the exposed polysilicon layer72.

Referring toFIG. 7C, the oxidation preventing pattern73and the oxidation preventing spacers74are removed. Thereafter, the doped polysilicon layer72is etched using the second oxide layer75as an etch mask, thereby forming a polysilicon pattern72P. Thus, the polysilicon pattern72remains only in the charge isolation section GC to a linewidth of 10 to 100 nm, which a conventional exposure apparatus fails to obtain, and the first oxide layer71is exposed around the polysilicon pattern72P. By using the second oxide layer75and the polysilicon pattern72P as an ion implantation mask, metal ions or semiconductor ions are implanted into the first oxide layer71. As a result, a first ion implantation region33LI is formed in the first oxide layer71formed in the first charge trapping section GL and the source section S. Also, a second ion implantation region33RI is formed in the first oxide layer71formed in the second charge trapping section GR and the drain section D.

The first and second ion implantation region33LI and33RI are important elements that determine the thickness of a tunnel oxide layer that will be defined later. Thus, since the ion implantation process is performed at an appropriate energy considering that the thickness of each of the first and second tunnel oxide layers32L and32R shown inFIG. 3is 1 to 5 nm, the first and second ion implantation regions33LI and33RI can be formed about 1 to 5 nm apart from the semiconductor substrate31.

Referring toFIG. 7D, the metal ions or semiconductor ions implanted into the first and second ion implantation regions33LI and33RI are crystallized using crystallization annealing, thereby forming a plurality of nano-crystals33NC. For example, if the nano-crystals33NC are formed of Si or Ge, the crystallization annealing is performed in an N2atmosphere at 950° C. for 30 minutes. If the nano-crystals33NC are formed of other semiconductor or metal than Si or Ge, the crystallization annealing is performed under conditions of gaseous atmosphere, temperature, and time appropriate for the material. The nano-crystals33NC have the form of clusters or dots having a size of several to several tens of nm, for example, 1 to 15 nm. Also, a space between the nano-crystals33NC is several to several tens of nm, for example, 1 to 10 nm, preferably, 5 to 10 nm. The size and space of the nano-crystals33NC can be adjusted by controlling the conditions of the ion implantation process or the crystallization annealing.

Referring toFIG. 7E, a doped polysilicon layer for a gate electrode is formed on the entire structure including the first oxide layer71in which the nano-crystals33NC are embedded, and polysilicon layer spacers76are formed on the both sidewalls of the polysilicon pattern72P using a spacer etching process. Thus, a gate electrode35, which is formed of the polysilicon pattern72P and the polysilicon layer spacers76, is formed. The polysilicon layer spacers76are important elements that determine the length of a charge trapping layer that will be defined later. Thus, since the deposition thickness of the polysilicon layer and the spacer etching process are controlled considering that the length of each of the first and second charge trapping layers33L and33R is about 15 to 100 nm, the polysilicon layer spacers76can be appropriately formed.

Referring toFIG. 7F, the second oxide layer75formed on the polysilicon pattern72P and the first oxide layer71exposed around the polysilicon layer spacers76are removed using an oxide etching process, thereby completing the gate electrode35. Thereafter, a source region36S and a drain region36D are formed by implanting ions into the source and drain sections S and D, respectively, and insulating spacers38are formed. As a result, the NVSM shown inFIG. 3can be obtained. Meanwhile, in order to reduce sheet resistance, the gate electrode35may have a polycide structure, in which polysilicon and metal-silicide are stacked using a salicide process using a metal such as Ti or Co.

In the fourth embodiment, the first and second tunnel oxide layers32L and32R are divided from the blocking oxide layer34by the nano-crystals33NC embedded in the first oxide layer71. Thus, each of the first and second tunnel oxide layers32L and32R is about 1 to 5 nm thick, and the blocking oxide layer34is about 3 to 150 nm thick. The first charge trapping layer33L includes nano-crystals33NC embedded in a portion of the first oxide layer71formed in the first charge trapping section GL, while the second charge trapping layer33R includes nano-crystals embedded in a portion of the first oxide layer71formed in the second charge trapping section GR. As a result of the gate etching process, each of the first and second charge trapping layers33L and33R becomes about 15 to 100 nm thick. The charge isolation layer33C corresponds to a region of the first oxide layer71where no nano-crystals33NC exist, and has a length of 10 to 100 nm due to the polysilicon pattern72P. A distance between the source and drain regions36S and36D disposed on both sides of the gate electrode35is several tens to several hundreds of nm and thus, the channel region37also scales several tens to several hundreds of nm.

As described above, the NVSM of the present invention includes the tunnel oxide layer, the charge trapping layers including the plurality of nano-crystals, and the blocking oxide layer, which are stacked between the channel region and the gate electrode. In this NVSM, the first and second charge trapping layers are separated from each other by the charge isolation layer and formed near the source and drain regions, respectively. As a result, no lateral diffusion occurs between charges injected into the first charge trapping layer near the source region and charges injected into the second charge trapping layer near the drain region, thus resulting in no disturbance. Accordingly, the NVSM of the present invention can be reduced to a nanoscale size or less, and the further downscaling of conventional 2-bit-per-cell NVSMs is enabled. Also, the NVSM of the present invention can meet the requisitions of the next-generation semiconductor technologies, such as low voltage, subminiature size, ultrahigh integration, high performance, and high reliability.

Moreover, since the NVSM of the present invention can be manufactured using a conventional CMOS process, it can be mass-produced not only as stand-alone products but also embedded products.

While the present invention has been particularly shown and described with reference to preferred embodiments thereof, it should be appreciated that the scope of the invention is not limited to the detailed description of the invention hereinabove, which is intended merely to be illustrative, but rather defined by the subject matter disclosed in the following claims.