Integrated circuit for driving pixel of display panel, pixel driving device, and pixel defect detecting method

The present disclosure relates to an integrated circuit, a pixel driving device and a pixel defect detecting method and provides a device and method to sense a voltage of a light emitting diode of a pixel through a data line and to compare the sensed voltage with a reference range, thereby determining a pixel defect.

CROSS REFERENCE TO RELATED APPLICATION

This application claims priority to Republic of Korea Patent Application No. 10-2021-0134042 filed on Oct. 8, 2021, which is hereby incorporated by reference in its entirety.

BACKGROUND

1. Field of Technology

The present disclosure relates to an integrated circuit for driving a pixel of a display panel, a pixel driving device, and a pixel defect detecting method.

2. Related Technology

With the progress of informatization, various display devices capable of visualizing information have been developed. Examples of the display devices which have been recently developed or are being developed include a liquid crystal display (LCD), organic light emitting diode (OLED) display device, plasma display panel (PDP) and the like. With the development of display technology, such display devices are designed to properly display high-resolution images.

However, although the above-described display devices can properly display high-resolution images, it is difficult to reduce the sizes of the display devices. For example, large-sized OLED display devices which have been developed until now only have a size of 80 inches (approximately 2 m) or 100 inches (approximately 25 m), and thus are not suitable for fabricating a large-sized display device having a horizontal length of 10 m or more.

Recently, much attention has been paid to a light emitting diode (LED) display device as a method for solving such a size problem. The LED display device may include a necessary number of modularized LED pixels, which are arranged to constitute one large-sized panel. Alternatively, the LED display device may include a necessary number of unit panels each having a plurality of LED pixels, which are arranged to form one large-sized panel structure. According to the LED display device technology, a necessary number of LED pixels may be expanded and arranged, which makes it easy to implement a large-sized display device.

The LED display device is advantageous to the diversification of panel sizes as well as the size enlargement. Thus, the horizontal and vertical lengths of the LED display device may be adjusted to various values according to a proper arrangement of LED pixels.

A display panel having LEDs arranged therein may be driven through a variety of methods. Representative examples of the driving method may include a pulse amplitude modulation (PAM) method and a pulse width modulation (PWM) method. The PAM method is to supply a pixel with an analog voltage corresponding to the grayscale value of the pixel, and control the magnitude of a current, flowing through the pixel, to a different value depending on the analog voltage, and the PWM method is to adjust the time during which a current is supplied to a pixel according to the grayscale value of the pixel.

The display panel may include a plurality of pixels. According to a current flowing through an LED included in each of the pixels, the LED may emit light to display a desired image.

However, when a defect occurs in the LED included in each of the pixels, the corresponding pixel cannot be normally displayed. In order to detect defects of the plurality of pixels, a plurality of defect detection circuits corresponding to the number of the pixels need to be added. Thus, the area of a display circuit is inevitably increased.

The discussions in this section are only to provide background information and does not constitute an admission of prior art.

SUMMARY

Under such a background, in one aspect, various embodiments are directed to providing an integrated circuit for driving a pixel of a display panel, in which a driving circuit for providing a data voltage to drive each pixel can sense a voltage (e.g. voltage of anode terminal or forward voltage drop) of a light emitting diode included in each pixel and detect a defect (e.g. open or short) of the pixel, and a pixel driving device and a pixel defect detecting method.

In one aspect, the present disclosure provides an integrated circuit comprising: a driving circuit configured to provide a data voltage to a pixel of a panel through a data line connected to the pixel, to sense a voltage of a light emitting diode of the pixel through the data line, and to compare the voltage of the light emitting diode with a reference voltage; and a detection circuit configured to receive, from the driving circuit, a comparison result between the voltage of the light emitting diode and the reference voltage and to identify a defect of the pixel on the basis of the received comparison result.

In another aspect, the present disclosure provides a pixel driving device comprising: an amplifier configured to provide a data voltage to a pixel through the data line connected with the pixel of a panel; and a first switch connected between the pixel and an output terminal of the amplifier, wherein, when the first switch is closed, the amplifier receives a source voltage through a first input terminal thereof and provides the data voltage to the pixel through the data line connected to an output terminal thereof and, when the first switch is open, the amplifier receives a reference voltage through the first input terminal thereof, receives the voltage of the light emitting diode included in the pixel sensed through the data line through a second input terminal thereof, and outputs a comparison result between the reference voltage and the voltage of the light emitting diode through the output terminal.

In still another aspect, the present disclosure provides a pixel defect detecting method for detecting a defect in a pixel of a display panel having a plurality of pixels arranged therein, the pixel defect detecting method comprising: providing a data voltage to the pixel by an amplifier connected with the pixel through a data line in a first time period; receiving, by the amplifier, a reference voltage and a voltage of a light emitting diode included in the pixel and outputting a comparison result between the reference voltage and the voltage of the light emitting diode in a second time period; and identifying a defect of the pixel on the basis of the comparison result between the reference voltage and the voltage of the light emitting diode.

According to the present embodiments, the driving circuit for providing a data voltage to drive each pixel may sense a voltage (e.g. voltage of anode terminal or forward voltage drop) of the light emitting diode included in each pixel and detect a defect (e.g. open or short) of the pixel. Thus, a separate comparator does not need to be added, in order to detect whether each pixel has a defect.

Furthermore, the amplifier included in the driving circuit which provides the data voltage for driving each pixel may be reused as a comparator for pixel defect determination, which makes it possible to reduce the area of the display circuit.

Furthermore, the display device simultaneously sense a plurality of pixels arranged in the same row, among a plurality of pixels arranged in the display panel, and determine whether each of the pixels have a defect, which makes it possible to minimize the pixel defect determination speed.

DETAILED DESCRIPTION OF EMBODIMENTS

FIG.1is a configuration diagram of a display device in accordance with an embodiment.

Referring toFIG.1, a display device100may include a panel (or display panel)110and a panel driving circuit (or driving circuit) for driving the panel110. The panel driving circuit may include a data driving circuit120, a gate driving circuit140and a data processing circuit150. The display device100may further include a detection circuit130.

The panel110may include a plurality of data lines DL, a plurality of gate lines GL and a plurality of pixels P (or sub-pixels SP), which are arranged therein. In an embodiment, at least some of the plurality of data lines DL and the plurality of gate lines GL may be used as a plurality of sensing lines SL.

The circuits120,140and150for driving one or more components included in the panel110may be referred to as panel driving circuits or driving circuits. For example, at least one of the data driving circuit120, the gate driving circuit140and the data processing circuit150may be each referred to as a panel driving circuit or a driving circuit. The above-described circuits120,140and150may be each referred to as a panel driving circuit or driving circuit, and the entire circuits or a plurality of circuits may be referred to as panel driving circuits or driving circuits.

In the panel driving circuit, the gate driving circuit140may supply a scan signal having a turn-on voltage or turn-off voltage to each of the pixels P through the corresponding gate line GL. When the scan signal having the turn-on voltage is supplied to each of the pixels P, the corresponding pixel P is connected to the data line DL. When the scan signal having the turn-off voltage is supplied to each of the pixels P, the corresponding pixel P is disconnected from the data line DL.

In the panel driving circuit, the data driving circuit120supplies a data voltage to the data line DL. The data voltage supplied to the data line DL, which is, for example, a voltage corresponding to a grayscale value of each pixel, may be transferred to the pixel P connected to the data line DL according to the scan signal.

In an embodiment, the data driving circuit120may use at least some of the data lines DL as the sensing lines SL. For example, the data driving circuit120may sense a voltage of a light emitting diode (e.g. LED) within a pixel P through the data line DL, which is to supply a data voltage to each pixel P. Here, the voltage may be a forward drop voltage measured at an anode end of the light emitting diode. When the display device100operates in a first mode (e.g. display driving mode) in the first time period, the data driving circuit120may supply a data voltage to each of the pixels P through the data line DL. When the display device100operates in a second mode (e.g. pixel defect detecting mode) in the second time period, the data driving circuit120may sense a voltage of the light emitting diode (e.g. LED) within the pixel P by using the data line DL as the sensing line SL. When the display device100operates in the second mode (e.g. pixel defect detecting mode), the data driving circuit120may detect a defect (e.g. open or short) of the pixel P by comparing the voltage of the light emitting diode within the pixel P (for example, a forward drop voltage measured at an anode end of the light emitting diode), which is sensed through the data line DL, with at least one reference voltage.

For example, when the display device100operates in the second mode (e.g. pixel defect detecting mode), the data driving circuit120may compare the voltage of the light emitting diode within the pixel P (for example, a forward drop voltage measured at an anode end of the light emitting diode) and sensed through the data line DL, to a first reference voltage, and transmit the comparison result to the detection circuit130. The detection circuit130may identify (or determine) whether the light emitting diode included in the pixel P is open based on the comparison result.

When the display device100operates in the second mode (e.g. pixel defect detecting mode), the data driving circuit120may compare the voltage of the light emitting diode within the pixel P (for example, a forward drop voltage measured at an anode end of the light emitting diode) and sensed through the data line DL, to a second reference voltage, and transmit the comparison result to the detection circuit130. The detection circuit130may identify (or determine) whether the LED included in the pixel P is shorted based on the comparison result. An operation method in detail of the pixel defect detecting operation of the data driving circuit120and the detection circuit130will be described below in detail with reference toFIG.4and the following drawings.

In the panel driving circuit, the data processing circuit150may supply various control signals to one or more of the data driving circuit120, the detection circuit130and the gate driving circuit140. The data processing circuit150may generate a gate control signal GCS for controlling the start of a scan according to a timing implemented in each frame, and transmit the generated gate control signal GCS to the gate driving circuit140. The data processing circuit150may convert image data inputted from outside into image data RGB suitable for a data signal format used in the data driving circuit120, and output the image data RGB to the data driving circuit120. Furthermore, the data processing circuit150may transmit a data control signal DCS for controlling the data driving circuit120to supply a data voltage to each of the pixels P according to each timing.

The data driving circuit120may be referred to as a source driving. The gate driving circuit140may be referred to as a gate driving. The data processing circuit150may be referred to as a timing controller T-CON or a controller. The data driving circuit120and the detection circuit130may be included in one integrated circuit125, and referred to as a source driving integrated circuit (IC). Furthermore, the data driving circuit120, the detection circuit130and the data processing circuit150may be included in one integrated circuit, and referred to as an IC. The present embodiment is not limited to such names. In the following descriptions, however, the descriptions of some generally known components in the source driving, the gate driving and the timing controller will be omitted herein. Thus, for understandings of the embodiment, it should be considered that such some components are omitted.

The panel (or display panel)110may be an LED panel. At this time, the pixels P (or sub-pixels SP) arranged in the panel110may include an LED and one or more transistors. The panel (or display panel)110may be an OLED panel. At this time, the pixels P arranged in the panel110may include an OLED and one or more transistors. The LED or OLED included in each of the pixels P may be damaged with the use of the display device. For example, when the LED or OLED included in each of the pixels P is open or shorted, the LED or OLED may not normally emit light even though a preset normal current flows therethrough. In an embodiment, the data driving circuit120may sense a forward voltage drop of the light emitting diode (e.g. the LED or OLED) included in each of the pixels P, for example, the voltage at the anode terminal of the light emitting diode, and compare the sensed forward voltage drop to one or more reference voltages, thereby detecting a defect of the light emitting diode. In the following embodiments, the case in which the light emitting diode is an LED will be taken as an example, for convenience of description. However, the present embodiments are not limited thereto.

FIG.2is a detailed configuration diagram of a display device in accordance with an embodiment.

Referring toFIG.2, a display device200may include a controller210, a driving circuit220, a detection circuit230, and a plurality of pixels P arranged in a display panel. The controller210may perform at least some functions or the entire functions of the data processing circuit150ofFIG.1, and control a pixel defect detecting operation in accordance with an embodiment which will be described below. The driving circuit220may include the data driving circuit120ofFIG.1, and further include the gate driving circuit140ofFIG.1. The detection circuit230may include the detection circuit130ofFIG.1. The driving circuit220and the detection circuit230may be included in one IC225, and referred to as a source driving IC. Furthermore, the driving circuit220, the detection circuit230and the controller210may be included in one IC, and referred to as an IC.

The pixel P may include a converting circuit240, a light emitting diode (e.g. LED or OLED), a first transistor TR1(e.g. driving transistor), a second transistor TR2(e.g. light emitting control transistor) and a third transistor TR3(e.g. detection control transistor). In the following descriptions, an LED will be taken as an example of the light emitting diode, for convenience of description. However, the LED may be replaced with various types of different light emitting diodes including an OLED. The pixel P may be formed in a silicon back plane, and the transistors TR1to TR3arranged in the pixel P may be formed in a complementary metal-oxide-silicon (CMOS) type.

The LED may be composed of an anode electrode, an organic layer, a cathode electrode and the like. The LED emits light while the anode electrode is connected to a driving voltage EVDD (or driving high voltage) and the cathode electrode is connected to a ground voltage EVSS (or driving low voltage), under control of the first transistor TR1and/or the second transistor TR2.

The first transistor TR1may control the brightness of the LED by controlling a driving current supplied to the LED. A first node N1of the first transistor TR1may be electrically connected to the anode electrode of the LED through the second transistor TR2, and serve as a source or drain node. A second node N2of the first transistor TR1may be connected to the converting circuit240. A third node N3of the first transistor TR1may be electrically connected to a driving voltage line DVL for supplying the driving voltage EVDD, and serve as a drain or source node. The converting circuit240may be electrically connected between the driving circuit220and the second node N2of the first transistor TR1, and the first transistor TR1may be turned on or off according to an output of the converting circuit240. As illustrated inFIG.3which will be described below, the converting circuit240may include one or more transistors and one or more capacitors, receive a data voltage from the driving circuit220, and convert the received data voltage through the PWM or PAM method. In an embodiment, lines through which the data voltage from the driving circuit220is supplied to the converting circuit240may be referred to as data lines DL. In an embodiment, at least some of the data lines DL may be used also as sensing lines SL as will be described below.

In an embodiment, when the display device200operates in a first mode (e.g. display driving mode) in a first time period, the driving circuit220may supply the data voltage to the converting circuit240through the data line DL. As described above, the converting circuit240may turn on the first transistor TR1to pass a current through the LED, thereby causing the LED to emit light.

When the display device200operates in a second mode (e.g. pixel defect detecting mode) in a second time period, the driving circuit220may sense a voltage of the LED within the pixel P (for example, a voltage VAapplied to an anode end of the LED, such as a forward drop voltage) by using at least some of the data lines DL as the sensing lines SL. For example, the driving circuit220may share and use a line between the driving circuit220and a fourth node N4as the sensing line SL.

In an embodiment, when the display device200operates in the second mode (e.g. pixel defect detecting mode), the driving circuit220may turn on the third transistor TR3according to a detection control signal DETECT_EN, and thus sense a voltage of the LED from a sixth node N6, for example, a voltage VAapplied to the anode terminal of the LED (e.g. forward voltage drop). More specifically, when the third transistor TR3is turned on by the detection control signal DETECT_EN while the display device200operates in the second mode (e.g. pixel defect detecting mode), the voltage VAapplied to the anode terminal of the LED may correspond to a voltage VSOURCE applied to a fifth node N5between the driving circuit220and the third transistor TR3. The driving circuit220may check the voltage VAof the sixth node N6by sensing the voltage of the fifth node N5.

In an embodiment, the driving circuit220may compare the voltage of the LED (for example, a voltage VAapplied to an anode end of the LED, such as a forward drop voltage) and sensed through at least some of the data lines DL, to one or more reference voltages, thereby detecting a defect of the LED. For example, when the display device200operates in the second mode (e.g. pixel defect detecting mode), the driving circuit220may compare the voltage of the LED and sensed through at least some of the data line DL, to a first reference voltage, and transmit the comparison result to the detection circuit230. The detection circuit230may identify (or determine) whether the LED included in the pixel P is open, based on the comparison result with the first reference voltage.

When the display device200operates in the second mode (e.g. pixel defect detecting mode), the driving circuit220may compare the voltage VA, of the LED and sensed through at least some of the data lines DL, to a second reference voltage, and transmit the comparison result to the detection circuit230. The detection circuit230may determine whether the LED included in the pixel P is shorted, based on the comparison result with the second reference voltage. The pixel defect detecting operation of the driving circuit220and the detection circuit230will be described below in detail with reference toFIG.4and the following drawings.

FIG.3is a detailed configuration diagram of the display device in accordance with an embodiment. Referring toFIG.3, the converting circuit240ofFIG.2may include one transistor and one capacitor. However, this is only an example, and the converting circuit240is not limited to the example ofFIG.3. In an embodiment, the display device200including the converting circuit240may operate according to an active matrix method.

In an embodiment, the converting circuit240may include a fourth transistor TR4and a storage capacitor Cstg, but is not limited thereto. The first transistor TR1may control the brightness of the LED by controlling a driving current supplied to the LED. The first node N1of the first transistor TR1may be electrically connected to the anode electrode of the LED through the second transistor TR2, and serve as a source or drain node. The second node N2of the first transistor TR1may be electrically connected to a source or drain node of the fourth transistor TR4(e.g. switching transistor SWT) of the converting circuit240, and serve as a gate node. The third node N3of the first transistor TR1may be electrically connected to a driving voltage line DVL for supplying the driving voltage EVDD, and serve as a drain or source node.

The fourth transistor TR4of the converting circuit240may be electrically connected between the data line DL and the second node N2of the first transistor TR1, and turned on by a scan signal received through a gate line GL1. When the fourth transistor TR4is turned on, a data voltage Vdata supplied from the driving circuit220through the data line DL may be transferred to the second node N2of the first transistor TR1.

The storage capacitor Cstg may be electrically connected between the first and second nodes N1and N2of the first transistor TR1. The storage capacitor Cstg may be a parasitic capacitor existing between the first and second nodes N1and N2of the first transistor TR1, or an external capacitor which is intentionally designed outside the first transistor TR1.

The third transistor TR3may connect the sixth node N6and the sensing line SL. As the third transistor TR3is turned on by the detection control signal DETECT_EN supplied through a gate line GL2, the voltage VAformed in the anode electrode of the LED may be sensed by the driving circuit220.

In an embodiment, the driving circuit220may compare the voltage VA, formed in the anode electrode of the LED and sensed through at least some of the data lines DL, to one or more reference voltages, thereby detecting a defect of the LED.

For example, when the display device200operates in the second mode (e.g. pixel defect detecting mode), the driving circuit220may compare the voltage VAof the LED (for example, a voltage VAapplied to an anode end of the LED, such as a forward drop voltage) and sensed through at least some of the data lines DL, to the first reference voltage, and transmit the comparison result to the detection circuit230. The detection circuit230may identify (or determine) whether the LED included in the pixel P is open, based on the comparison result.

When the display device200operates in the second mode (e.g. pixel defect detecting mode), the driving circuit220may compare the voltage VAof the LED (for example, a voltage VAapplied to an anode end of the LED, such as a forward drop voltage) and sensed through at least some of the data lines DL, to the second reference voltage, and transmit the comparison result to the detection circuit230. The detection circuit230may identify (or determine) whether the LED included in the pixel P is shorted, based on the comparison result. The pixel defect detecting operation of the driving circuit220and the detection circuit230will be described below in detail with reference toFIG.4and the following drawings.

In an embodiment, the above-described display device100may operate in the display driving mode (for example, in the first mode) in the first time period and operate in the pixel defect detecting mode (for example, in the second mode) in the second time period. The operation periods of the first mode and the second mode may be divided as shown in Table 1 below.

Referring to Table 1, the operation period of the display device100or200in the first mode (e.g. display driving mode) may be divided into an initialization period, a programming period, a light emission period and a reset period. The operation period of the display device100or200in the second mode (e.g. pixel defect detecting mode) may be divided into an initialization period, a programming period, a comparison period, a logic processing period and a reset period. The programming period may be referred to as a precharge period. An operation in the reset period may be the same as or similar to that in the initialization period. An operation in the initialization period of the first mode may be the same as or similar to that in the initialization period of the second mode. An operation in the programming period of the first mode may be the same as or similar to that in the programming period of the second mode. An operation in the reset period of the first mode may be the same as or similar to that in the reset period of the second mode. The operations in the first mode may be the same as or similar to operations of a general display device in the display driving mode, and conducted according to the method described with reference toFIGS.1to3. Hereafter, the situation in which the display device100or200operates in the second mode (e.g. pixel defect detecting mode) will be described with reference toFIGS.4to6. Among the operations in the second mode, an operation ofFIG.4may correspond to the initialization period, an operation ofFIG.5may correspond to the programming period, and an operation ofFIG.6may correspond to the comparison period and/or the logic processing period.

In an embodiment, the driving circuit220illustrated inFIGS.4to6may include an amplifier221(e.g. a source amplifier or an output buffer), a first switch (SW1)222and a second switch (SW2)223. However, the driving circuit220is not limited thereto. The first switch222may be located on the data line DL at an output terminal of the amplifier221. The second switch223may be connected to the detection circuit230at the output terminal of the amplifier221. The first switch222or the second switch223may be implemented by a switching element. Here, a switching element may comprise various types of transistors such as a filed effect transistor (FET) or a bipolar junction transistor (BJT). However, embodiments described below are not limited thereto.

The switch between open and close states of the first switch222and/or the second switch223may be performed under control of the controller210. In an embodiment, the amplifier221may operate as an output buffer in the first mode (e.g. display driving mode), and operate as a comparator in the second mode (e.g. pixel defect detecting mode). When the amplifier221operates as an output buffer, the amplifier221may output a voltage having a level identical or similar to that of an input voltage (for example, a data voltage corresponding to a grayscale value of each pixel). In the following descriptions, a positive (+) terminal (for example, a non-inverting terminal) of the amplifier221will be referred to as a first input terminal, and a negative (−) terminal (for example, an inverting terminal) of the amplifier221will be referred to as a second input terminal. However, the preset embodiment is not limited thereto. In an embodiment, when the first and second input terminals are set in the opposite way, a result of the amplifier221may be processed as the opposite result of that in the following descriptions.

FIG.4is a diagram illustrating an operation of the circuit in the initialization period in accordance with an embodiment. Referring toFIG.4, the first and second switches222and223included in the driving circuit220may be controlled to be open in the initialization period. In the initialization period, the first to third transistors TR1to TR3may be turned off. As the switches and the transistors are controlled to be open or turned off in the initialization period, the nodes and the capacitor (e.g. the storage capacitor Cstg ofFIG.3) which are included in the pixel P of the display device may be reset and initialized.

FIG.5is a diagram illustrating an operation of the circuit in the programming period in accordance with an embodiment. Referring toFIG.5, the first switch222of the driving circuit220may be switched from the open state to the closed state in the programming period. In the programming period, a test voltage for pixel defect detection may be inputted to the first input terminal of the amplifier221. The amplifier221may operate as an output buffer in the programming period, and a current corresponding to the test voltage inputted to the first input terminal of the amplifier221may be supplied to the converting circuit240through the output terminal of the amplifier221. In the programming period, the transistor (e.g. fourth transistor TR4) within the converting circuit240may be turned on, and the current inputted to the converting circuit240may be stored in the capacitor (e.g. storage capacitor Cstg) within the converting circuit240.

FIG.6is a diagram illustrating an operation of the circuit in the comparison period in accordance with an embodiment. Referring toFIG.6, the first switch222of the driving circuit220may be switched from the closed state to the open state in the comparison period. In the comparison period, the second switch223of the driving circuit220may be switched from the open state to the closed state.

In the comparison period, the second and third transistors TR2and TR3may be turned on. As the second and third transistors TR2and TR3are turned on in the comparison period, the voltage VAat the anode terminal (e.g. the sixth node N6) of the LED may be sensed by the driving circuit220. For example, when the third transistor TR3is turned on, the sixth node N6corresponding to the anode terminal of the LED may be connected to the fifth node N5through the third transistor TR3, and the fifth node N5may be connected to the data line DL at the fourth node N4. The voltage VAof the anode terminal (e.g. the sixth node N6) of the LED may be inputted to the second input terminal of the amplifier221through a feedback line of the driving circuit220.

In the comparison period, one or more reference voltages (e.g. first reference voltage or second reference voltage) may be inputted to the first input terminal of the amplifier221. For example, the amplifier221of the driving circuit220may compare the first reference voltage inputted to the first input terminal to the sensing voltage VSOURCE of the LED, inputted to the second input terminal, and transmit the comparison result to the detection circuit230through the second switch223. The detection circuit230may determine whether the LED included in the pixel P is open, based on the comparison result. For example, when the comparison result indicates that the sensing voltage of the LED is larger than the first reference voltage, the detection circuit230may identify (or determine) that the LED is open.

Furthermore, the amplifier221of the driving circuit220may compare the second reference voltage inputted to the first input terminal to the sensing voltage VSOURCE of the LED inputted to the second input terminal, and transmit the comparison result to the detection circuit230through the second switch223. The detection circuit230may determine whether the LED included in the pixel P is shorted, on the basis of the comparison result. For example, when the comparison result indicates that the sensing voltage of the LED is smaller than the second reference voltage, the detection circuit230may identify (or determine) that the LED is shorted.

Hereafter, a voltage sensed by the driving circuit220when the LED is normal or abnormal (e.g. open or shorted) will be described with reference toFIGS.7A,7B,8A,8B,9A and9B.FIGS.7A and7Billustrate an equivalent circuit when the LED is normal, and a sensing voltage (e.g. forward voltage drop) of the LED,FIGS.8A and8Billustrate an equivalent circuit when the LED is open, and a sensing voltage (e.g. forward voltage drop) of the LED, andFIGS.9A and9Billustrate an equivalent circuit when the LED is shorted, and a sensing voltage (e.g. forward voltage drop) of the LED.

Referring toFIGS.7A and7B, when the detection control signal is applied to the third transistor TR3to turn on the third transistor T3in case that the LED is normal, the voltage VSOURCE of the fifth node N5, sensed by the driving circuit220(e.g. amplifier221), rises to a voltage value of 2 to 3 V from the initial voltage value. For example, the anode terminal of the LED may retain a voltage of 2 to 3 V according to a forward voltage, while the LED is normal.

Referring toFIGS.8A and8B, when the detection control signal is applied to the third transistor TR3to turn on the third transistor T3in case that the LED is open so that a defect occurred, the voltage VSOURCE of the fifth node N5, sensed by the driving circuit220(e.g. amplifier221), gradually rises and retains the driving voltage EVDD higher than the voltage (e.g. 2 to 3 V) in the normal state. For example, since the LED is open, no current flows through the LED. Thus, the driving voltage EVDD is applied to the sixth node N6and the fifth node N5. In an embodiment, a voltage between the voltage (e.g. 2 to 3 V) in the normal state and the driving voltage EVDD may be set to the first reference voltage, and the first reference voltage may be compared to the voltage sensed through the fifth node N5, in order to determine whether the LED is open so that a defect occurred. For example, when the voltage sensed through the fifth node N5is higher than the first reference voltage, the LED may be determined to be open.

Referring toFIGS.9A and9B, when the detection control signal is applied to the third transistor TR3to turn on the third transistor T3in case that the LED is shorted so that a defect occurred, the voltage VSOURCE of the fifth node N5, sensed by the driving circuit220(e.g. amplifier221), falls and retains the ground voltage EVSS or GND (e.g. 0 V) lower than the voltage (e.g. 2 to 3 V) in the normal state. For example, since the LED is shorted, the voltage of the fifth node N5becomes equal to the ground voltage EVSS. In an embodiment, a voltage between the voltage (e.g. 2 to 3 V) in the normal state and the ground voltage EVSS may be set to the second reference voltage, and the second reference voltage may be compared to the voltage sensed through the fifth node N5, in order to determine whether the LED is shorted so that an error occurred. For example, when the voltage sensed through the fifth node N5is lower than the second reference voltage, the LED may be determined to be shorted.

FIG.10is a detailed configuration diagram of a display device in accordance with an embodiment. Referring toFIG.10, the display device may include a controller210, a plurality of driving circuits1010(e.g. n driving circuits), a plurality of pixels P (e.g. n pixels), a level shifter1020and a detection circuit1030. Each of the driving circuits1010may include an amplifier1014, a first switch (SW1)1011, a second switch (SW2)1012, a third switch (SW3)1013and an output switch (OUT SW)1015. For example, a first driving circuit1010afor driving a first pixel P1may include an amplifier1014a, a first switch1011a, a second switch1012a, a third switch1013aand an output switch1015a, and an nthdriving circuit1010nfor driving an nthpixel Pn may include an amplifier1014n, a first switch1011n, a second switch1012n, a third switch1013nand an output switch1015n. For convenience of description, a line connected to the pixel P from the output switch1015may be referred to as a first output line OUT1, and a line connected between the amplifier1014and the output switch1015may be referred to as a second output line OUT2. In accordance with an embodiment, at least some driving circuits of the plurality of driving circuits1010may be connected to a first level shifter1021of the level shifter1020, and the other driving circuits may be connected to a second level shifter1022of the level shifter1020.

Hereafter, an operation of the display device in the pixel defect detecting mode (e.g. second mode) in accordance with an embodiment will be described with reference toFIGS.10to12.FIGS.11and12are timing diagrams of signals operated in the display device ofFIG.10, in accordance with an embodiment.

Referring toFIG.11, a period from T0to T1may correspond to the initialization period, a period from T1to T4may correspond to the programming period, a period from T4to T7may correspond to the comparison period, a period from T7to T11may correspond to the logic processing period, and a period from T11may correspond to the reset period (or initialization period). In each of the periods, a clock signal CLK may be supplied to the driving circuit220according to a preset cycle or frequency (e.g. several MHz). The controller210may open/close each of the switches included in the display device, and supply a control signal (e.g. gate control signal) to each of the pixels P, such that at least one transistor included in the pixel P is turned on or off.

In the initialization period from T0to T1, the first switch (SW1)1011and the output switch (OUT SW)1015may be controlled to be closed, and the third switch1013may be controlled to be open. In the initialization period, a preset source voltage SOURCE IN may be inputted to the first input terminal of the amplifier1014, and the output switch1015may be controlled to be closed. Thus, the source voltage may be applied to the first output line OUT1and the second output line OUT2.

The controller210may control the driving circuit to switch from the initialization period to the programming period at T1. For example, the controller210may close the first switch1011and the output switch1015at T1. In the programming period, a test voltage for pixel defect detection may be inputted to the first input terminal (e.g. positive (+) terminal) of the amplifier1014. The amplifier1014may operate as an output buffer in the programming period, and a current corresponding to the test voltage inputted to the first input terminal of the amplifier1014may be supplied to the converting circuit240of each pixel P through the output terminal of the amplifier1014. In the programming period, the transistor (e.g. fourth transistor TR4) within the converting circuit240may be turned on, and the current inputted to the converting circuit240may be stored in the capacitor (e.g. storage capacitor Cstg) within the converting circuit240.

The controller210may control the driving circuit to switch from the programming period to the comparison period at T4. The controller210may open the output switch1015at T2before the programming period is switched to the comparison period at T4, and open the first switch1011at T3. When the programming period of the driving circuit is switched to the comparison period at T4, the controller210closes the third switch1013.

In order to determine whether the LED is open, the controller210may supply a first reference voltage (SOURCE IN H)1100to the first input terminal. For example, when the LED is open, the voltage of the LED, sensed by the driving circuit1010, may correspond to the driving voltage EVDD. Therefore, a voltage between the voltage (e.g. 2 to 3 V) in the normal state and the driving voltage EVDD may be set to the first reference voltage. When the LED is open in the comparison period, a voltage (SOURCE OUT1)1101of the first output line OUT1may gradually rise and correspond to the driving voltage EVDD as illustrated inFIG.11. When the LED is normal in the comparison period, a voltage (SOURCE OUT1)1102of the first output line OUT1may be retained at a voltage of 2 to 3 V as illustrated inFIG.11. When the LED is shorted in the comparison period, a voltage (SOURCE OUT1)1103of the first output line OUT1may fall and correspond to the ground voltage EVSS or GND (e.g. 0 V) as illustrated inFIG.11.

When the LED is open in the comparison period, the voltage1101of the first output line OUT1gradually rises as illustrated inFIG.11, and becomes higher than the first reference voltage (SOURCE IN H)1100at T6. The amplifier1014may operate as a comparator in the comparison period. As the third switch1013is controlled to be closed in the comparison period, a voltage sensed for the LED may be inputted to a second input terminal (e.g. negative (−) terminal) of the amplifier1014through a feedback line. For example, the voltage of the second output line OUT2corresponds to a result obtained by comparing the first reference voltage1100inputted to the first input terminal to the voltage1101of the first output line OUT1inputted to the second input terminal, through the amplifier1014. Therefore, the voltage of the second output line OUT2may become a high signal in the period from T4to T6, and become a low signal in the period from T6to T11.

The controller210may switch the comparison period to the logic processing period at T7. For example, the controller210may sequentially close the second switches1012of the plurality of pixels at T7, such that the signals of the second output lines OUT2, which are the comparison results of the amplifiers1014in the respective pixels, are transmitted to the level shifter1020and the detection circuit1030. The level shifter1020may include the first level shifter1021and the second level shifter1022. The level shifter1020may convert the level of an input signal into a voltage level which can be processed by the detection circuit1030, for example, a voltage level corresponding to a digital signal. In an embodiment, the plurality of pixels included in the display panel may be sorted into first group pixels and second group pixels, the voltage levels of the first group pixels may be converted by the first level shifter1021, and the voltage levels of the second group pixels may be converted by the second level shifter1022. The signals converted by the level shifter1020may be inputted to the detection circuit1030. The detection circuit1030may check a result received from each of the pixels at the timing that the second switch1012is closed, for example, the signal of the second output line OUT2. When the signal of the second output line OUT2for a specific pixel is a low signal, the detection circuit1030may determine that the corresponding pixel is open, thereby checking a defect. As illustrated inFIG.11, the controller210may sequentially close the second switches1012of a plurality of pixels P (e.g. a plurality of pixels arranged in the same row among the plurality of pixels arranged in the panel) within one first mode operation period (e.g. the comparison period and the logic processing period), and thus sense voltages of the plurality of LEDs included in the respective pixels (for example, a voltage applied to an anode terminal of a light emitting diode, such as a forward drop voltage) at the same time. For example, the plurality of driving circuits1010may sequentially transmit the comparison results with the first reference voltage for the plurality of LEDs to the level shifter1020and the detection circuit1030within one first mode operation period.

Referring toFIG.12, a period from T0to T1may correspond to an initialization period, a period from T1to T4may correspond to a programming period, a period from T4to T7may correspond to a comparison period, a period from T7to T11may correspond to a logic processing period, and a period from T11may correspond to a reset period (or initialization period). In each of the periods, a clock signal CLK may be supplied to the driving circuit220according to a preset cycle or frequency (e.g. several MHz). The controller210may open/close each of the switches included in the display device, and supply a control signal (e.g. gate control signal) to each of the pixels P, such that at least one transistor included in the pixel P is turned on or off.

In the initialization period from T0to T1, the first switch (SW1)1011and the output switch (OUT SW)1015may be controlled to be closed, and the third switch (SW3)1013may be controlled to be open. As a preset source voltage SOURCE IN is inputted to the first input terminal of the amplifier1014and the output switch1015is controlled to be closed, the source voltage may be applied to the first output line OUT1and the second output line OUT2.

The controller210may control the driving circuit to switch from the initialization period to the programming period at T1. For example, the controller210may close the first switch1011and the output switch1015at T1. In the programming period, a test voltage for pixel defect detection may be inputted to the first input terminal (e.g. positive (+) terminal) of the amplifier1014. The amplifier1014may operate as an output buffer in the programming period, and a current corresponding to the test voltage inputted to the first input terminal of the amplifier1014may be supplied to the converting circuit240of each pixel P through the output terminal of the amplifier1014. In the programming period, the transistor (e.g. fourth transistor TR4) within the converting circuit240may be turned on, and the current inputted to the converting circuit240may be stored in the capacitor (e.g. storage capacitor Cstg) within the converting circuit240.

The controller210may control the driving circuit to switch from the programming period to the comparison period at T4. The controller210may open the output switch1015at T2before the programming period is switched to the comparison period at T4, and open the first switch1011at T3. When the programming period is switched to the comparison period at T4, the controller210closes the third switch1013.

In order to determine whether the LED is shorted, the controller210may supply a second reference voltage (SOURCE IN L)1200to the first input terminal. For example, when the LED is shorted, the voltage of the LED, sensed by the driving circuit1010, may correspond to the ground voltage EVSS. Therefore, a voltage between the voltage (e.g. 2 to 3 V) in the normal state and the ground voltage EVSS may be set to the second reference voltage. When the LED is shorted in the comparison period, a voltage1201of the first output line OUT1may fall and correspond to the ground voltage EVSS or GND (e.g. 0 V) as illustrated inFIG.12. When the LED is normal in the comparison period, a voltage (SOURCE OUT1)1202of the first output line OUT1may be retained at a value of 2 to 3 V as illustrated inFIG.12. When the LED is open in the comparison period, the voltage1201of the first output line OUT1may gradually rise and correspond to the driving voltage EVDD as illustrated inFIG.12.

When the LED is shorted in the comparison period, a voltage1203of the first output line OUT1falls as illustrated inFIG.12, and becomes lower than the second reference voltage (SOURCE IN L)1200at time T5. The amplifier1014may operate as a comparator in the comparison period. As the third switch1013is controlled to be closed in the comparison period, a voltage sensed for the LED may be inputted to the second input terminal (e.g. negative (−) terminal) of the amplifier1014through a feedback line. For example, the voltage of the second output line OUT2corresponds to a result obtained by comparing the second reference voltage1200inputted to the first input terminal to the voltage1201of the first output line OUT1inputted to the second input terminal, through the amplifier1014. Therefore, the voltage of the second output line OUT2may become a high signal in the period from T5to T11.

The controller210may control the driving circuit to operate in the logic processing period at T7. For example, the controller210may sequentially close the second switches1012of a plurality of pixels (e.g. a plurality of pixels arranged in the same row among the plurality of pixels arranged in the panel) at T7, such that the signals of the second output lines OUT2, which are the comparison results of the amplifiers1014in the respective pixels, are transmitted to the level shifter1020and the detection circuit1030. The detection circuit1030may check a result received from each of the pixels at the timing that the second switch1012is closed, for example, the signal of the second output line OUT2. When the signal of the second output line OUT2for a specific pixel is a high signal, the detection circuit1030may determine that the corresponding pixel is shorted, thereby checking a defect.

Table 2 below shows the signals of the second output line OUT2in the normal state, the open state and the shorted state when the input signal is at the first reference voltage SOURCE IN H as described with reference toFIG.11, and the signals of the second output line OUT2in the normal state, the open state and the shorted state when the input signal is at the second reference voltage SOURCE IN L as described with reference toFIG.12.

Referring to Table 2, an open LED may be detected by the first reference voltage, and a shorted LED may be detected by the second reference voltage. In an embodiment, the display device may simultaneously check whether a plurality of pixels (e.g. a plurality of pixels arranged in the same row among the plurality of pixels arranged in the panel) are open, during one pixel defect detecting mode period as illustrated inFIG.11, and simultaneously check whether a plurality of pixels (e.g. a plurality of pixels arranged in the same row among the plurality of pixels arranged in the panel) are shorted, during one pixel defect detecting mode period as illustrated inFIG.12. For example, the display device may simultaneously check whether a plurality of pixels (e.g. a plurality of pixels arranged in the same row among the plurality of pixels arranged in the panel) are normal, open or shorted, through the two comparison periods. In the above-described embodiments, the case in which the display panel operates in the first mode and the second mode has been taken as an example. However, the display panel may operate to perform the functions by the second mode.