Electronic component package and method of manufacturing the same

An electronic component package includes a frame having a cavity, an electronic component disposed in the cavity of the frame, a first metal layer disposed on an inner wall of the cavity of the frame, an encapsulant encapsulating the electronic component, and a redistribution layer disposed below the frame and the electronic component.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims benefit of priorities to Korean Patent Application No. 10-2015-0065507, filed on May 11, 2015 and Korean Patent Application No. 10-2015-0131398, filed on Sep. 17, 2015 with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND

The present disclosure relates to an electronic component package and a method of manufacturing the same.

2. Description of Related Art

An electronic component package technology is a package technology for electrically connecting an electronic component to a printed circuit board (PCB), such as a main board of an electronic device, or the like, and protecting the electronic component from external impacts, and is distinguished from technology for embedding an electronic component in a printed circuit board, such as an interposer board. Meanwhile, recently, one main trend of developing technology associated with electronic components is to decrease a component size. Therefore, in a package field, in accordance with a rapid increase in demand for a small-sized electronic component, or the like, a package having a number of pins while having a small size has been required.

One of package technologies suggested in order to satisfy the technical requirements as described above is a wafer level package (WLP) technology using redistribution of an electrode pad of an electronic component formed on a wafer. As a wafer level package (WLP), there are a fan-in wafer level package (fan-in WLP) and a fan-out wafer level package (fan-out WLP). In particular, the fan-out WLP may be useful for implementing a number of pins while having a small size, and thus, recently, the fan-out WLP has been actively developed.

SUMMARY

Meanwhile, in a case of a wafer level package as described above, in which an electronic component is simply encapsulated using a general encapsulating material, it was difficult to suitably control excessive heat generation in accordance with high-functionality of the package, or the like, and an electromagnetic wave.

An aspect of the present disclosure may provide an electronic component package which effectively decreases heat generated in an electronic component and an electromagnetic wave, and a method of manufacturing the same to efficiently manufacture the electronic component package.

According to an aspect of the present disclosure, an electronic component package may include a frame having a metal layer introduced into an encapsulation region of an electronic component in the package.

DETAILED DESCRIPTION

Hereinafter, embodiments of the present disclosure will be described with reference to schematic views illustrating embodiments of the present disclosure. In the drawings, for example, due to manufacturing techniques and/or tolerances, modifications of the shape shown may be estimated. Thus, embodiments of the present disclosure should not be construed as being limited to the particular shapes of regions shown herein, for example, to include a change in shape results in manufacturing. The following embodiments may also be constituted by one or a combination thereof.

The contents of the present disclosure described below may have a variety of configurations and propose only a required configuration herein, but are not limited thereto.

Electronic Device

FIG. 1is a block diagram schematically illustrating an example of an electronic device system.

Referring toFIG. 1, an electronic device1000may accommodate a main board1010therein. Chip-related components1020, network-related components1030, other components1040, and the like, may be physically and/or electrically connected to the main board1010. These components may be coupled to other components to be described below, thereby forming various signal lines1090.

The chip related components1020may include a memory chip such as a volatile memory (for example, a dynamic random access memory (DRAM)), a non-volatile memory (for example, a read only memory (ROM)), a flash memory, etc.; an application processor chip such as a central processor (for example, a central processing unit (CPU)), a graphics processor (for example, a graphic processing unit (GPU)), a digital signal processor, a cryptographic processor, a micro processor, a micro controller, etc.; a logic chip such as an analog-to-digital converter, an application-specific integrated circuit (ASIC), and the like. However, the chip related components1020are not limited thereto, and may also include other types of chip related components. Further, these components1020may be combined with each other.

The network-related component1030may include protocols such as Wi-Fi (Institute of Electrical and Electronics Engineers (IEEE) 802.11 family, or the like), worldwide interoperability for microwave access (WiMAX) (IEEE 802.16 family, or the like), IEEE 802.20, long term evolution (LTE), evolution data only (Ev-DO), high speed packet access+(HSPA+), high speed downlink packet access+(HSDPA+), high speed uplink packet access+(HSUPA+), enhanced data GSM environment (EDGE), global system for mobile communications (GSM), global positioning system (GPS), general packet radio service (GPRS), code division multiple access (CDMA), time division multiple access (TDMA), digital enhanced cordless telecommunications (DECT), Bluetooth, 3G, 4G, 5G protocols, and any other wireless and wired protocols designated after the above-mentioned protocols. However, the network-related components1030are not limited thereto, and may also include any of a plurality of other wireless or wired standards or protocols. Further, these components1030may be combined with each other together with the above-mentioned chip-related components1020.

Other components1040may include a high-frequency inductor, a ferrite inductor, a power inductor, ferrite beads, low-temperature co-firing ceramics (LTCC), an electro-magnetic interference (EMI) filter, a multilayer ceramic condenser (MLCC), or the like, but are not limited thereto. In addition to the above-mentioned components, other passive elements, and the like, used for various purposes may be included. Further, other components1040may be combined with each other together with the above-mentioned chip-related components1020and/or the above-mentioned network-related components1030.

The electronic device1000may include other components which may or may not be physically and/or electrically connected to the main board1010depending on the kind of electronic device1000. An example of these other components may include a camera1050, an antenna1060, a display1070, a battery1080, an audio codec (not illustrated), a video codec (not illustrated), a power amplifier (not illustrated), a compass (not illustrated), an accelerometer (not illustrated), a gyroscope (not illustrated), a speaker (not illustrated), a mass storage device (for example, a hard disk drive) (not illustrated), a compact disk (CD) (not illustrated), a digital versatile disk (DVD) (not illustrated), and the like. However, these other components are not limited thereto, and may also include other components, and the like, used for various purposes depending on the kind of electronic device1000.

The electronic device1000may be a smartphone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game console, a smart watch, or the like. However, the electronic device1000is not limited thereto, and may also be any other electronic device processing data as well as the above-mentioned electronic devices.

FIG. 2schematically illustrates an example of an electronic component package applied to an electronic device.

The electronic component package may be used for various purposes in various electronic devices1000as described above. For example, a main board1110may be accommodated in a body1101of a smartphone1100, and various electronic components1120may be physically and/or electrically connected to the main board1110. Further, another component, for example, a camera1130, which may or may not be physically and/or electrically connected to the main board1110, may be accommodated in the body1101. In this case, some of the electronic components1120may be the chip-related components as described above, and the electronic component package100may be, for example, an application processor among the chip-related components, but the electronic component1120and the electronic component package100are not limited thereto.

Electronic Component Package

FIG. 3is a cross-sectional diagram schematically illustrating an example of an electronic component package.

FIG. 4is a schematic cut-away plan diagram of the electronic component package taken along line I-I′ ofFIG. 3.

Referring toFIGS. 3 and 4, the electronic component package100A according to the example may include a frame110having a cavity110X; an electronic component120disposed in the cavity110X of the frame110; a first metal layer111disposed on an inner wall of the cavity110X of the frame110; a second metal layer112B disposed on a lower surface110B of the frame110; a third metal layer112A disposed on an upper surface110A of the frame110; an encapsulant150encapsulating the electronic component120; and a redistribution layer130disposed below the frame110and the electronic component120. Here, the term “disposed below” may include a case in which a target component is disposed in the corresponding direction but does not contact a component to be a basis as well as a case in which the target component directly contacts the component to be the basis.

In general, an electronic component package has a structure in which the surrounding of an electronic component is simply molded and enclosed with an encapsulant such as an epoxy molding compound (EMC), or the like. In this case, heat generated in the electronic component is mostly radiated downwardly along the redistribution layer, and only a significantly small amount of heat is transferred toward the encapsulant having low heat conductivity, and thus heat radiation characteristics may be deteriorated. Conversely, in a case of introducing the frame110having the metal layers111,112A, and112B in an encapsulation region of the electronic component120, warpage of the package may be effectively controlled by the frame110, and heat may be easily diffused through various routes by the metal layers111,112A, and112B, and thus heat radiation characteristics may be improved.

Further, in a case of adopting a structure in which the surrounding of the electronic component is simply molded and enclosed with the encapsulant such as the epoxy molding compound (EMC), or the like, operation characteristics, and the like, of an electronic device in which the electronic component is mounted may be deteriorated by electromagnetic interference (EMI) caused by an electromagnetic wave generated in the electronic component or introduced externally. On the contrary, in a case of introducing the frame110having the metal layers111,112A, and112B in the encapsulation region of the electronic component120, generally, since the metal layers111,112A, and112B may also shield the electromagnetic wave, problems caused by the electromagnetic interference may also be solved.

Hereinafter, each of the configurations of the electronic component package100A according to the example will be described in more detail.

The frame110may be a configuration for supporting the package100A, and due to the frame110, rigidity may be maintained and thickness uniformity may be secured. The frame110may have the upper surface110A and the lower surface110B opposing the upper surface110A, and the cavity110X may be formed to penetrate between the upper and lower surfaces110A and110B. The electronic component120may be disposed in the cavity110X to be spaced apart from the frame110, and as a result, the frame110may enclose around side surfaces of the electronic component120.

A material of the frame110is not particularly limited as long as it may support the package. For example, an insulating material may be used. Here, as the insulating material, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin in which a reinforcement material, such as a glass fiber or an inorganic filler, is impregnated in the thermosetting resin and the thermoplastic resin, for example, a pre-preg, Ajinomoto build-up film (ABF), FR-4, a bismaleimide triazine (BT) resin, or the like, may be used. Alternatively, a metal having excellent rigidity and heat conductivity may be used. In this case, as the metal, an Fe—Ni based alloy may be used. Here, in order to secure adhesive force with a molding material, an interlayer insulating material, or the like, such as a Cu plating layer may be formed on a surface of the Fe—Ni based alloy. In addition, glass, ceramic, plastic, or the like, may be used.

A cross-sectional thickness of the frame110is not particularly limited, and may be designed depending on a cross-sectional thickness of the electronic component120. For example, the cross-sectional thickness of the frame110may be, for example, 100 μm to 500 μm or so depending on the kind of electronic component120.

The electronic components120may be various active components (for example, a diode, a vacuum tube, a transistor, or the like) or passive components (for example, an inductor, a condenser, a resistor, or the like). Alternatively, the electronic component120may be an integrated circuit (IC) chip in which several hundreds to several millions or more of elements are integrated with each other. If necessary, the electronic component120may be an electronic component in which the integrated circuit is packaged in a flip chip form. The integrated circuit may be, for example, an application processor chip such as a central processor (for example, a central processing unit (CPU)), a graphics processor (for example, a graphics processing unit (GPU)), a digital signal processor, a cryptographic processor, a micro processor, a micro controller, or the like, but is not limited thereto.

The electronic component120may include an electrode pad120P electrically connected to the redistribution layer130. The electrode pad120P may be a configuration for electrically connecting the electronic component120externally, and as a material for forming the electrode pad120P, any conductive material may be used without particular limitation. As the conductive material, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), an alloy thereof, or the like, may be used, but the material for forming the electrode pad120P is not limited thereto. The electrode pad120P may be redistributed by the redistribution layer130. The electrode pad120P may be embedded or may protrude.

In a case in which the electronic component120is the integrated circuit, the electrode component120may have a body (not denoted by a reference numeral), a passivation layer (not denoted by a reference numeral), and the electrode pad120P. The body may be formed, for example, based on an active wafer. In this case, as a base material of the body, silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like, may be used. The passivation layer may serve to protect the body from external factors and be formed of, for example, an oxide film, a nitride film, or the like. Alternatively, the passivation layer may be formed of a double layer of an oxide film and a nitride film. As the material for forming the electrode pad120P, a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), an alloy thereof, or the like, may be used. A surface on which the electrode pad120P is formed may become an active layer.

The cross-sectional thickness of the electronic component120is not particularly limited, and may be changed depending on the kind of electronic component120. For example, in a case in which the electronic component is the integrated circuit, the cross-sectional thickness of the electronic component120may be 100 μm to 480 μm or so, but is not limited thereto.

The first metal layer111may basically allow heat generated in the electronic component120to be diffused and dispersed toward the frame110, and shield electromagnetic waves. The first metal layer111may be disposed on the inner wall of the cavity110X, thereby enclosing around the side surfaces of the electronic component120. The first metal layer111may be a layer entirely covering the inner wall of the cavity110X. In this case, problems of heat generation and electromagnetic interference may be more effectively controlled. The first metal layer111may contain a conductive material, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), an alloy thereof, or the like.

The second metal layer112B may diffuse heat transferred through the first metal layer111, or the like, downwardly from the package100A. In addition, the second metal layer112B may further improve an electromagnetic wave shielding effect. The second metal layer112B may be disposed on the lower surface110B of the frame110, and according to the example, the second metal layer112B may be a layer entirely covering the lower surface110B, and thus the problems of heat generation and electromagnetic interference may be more effectively controlled. The second metal layer112B may also contain a conductive material, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), an alloy thereof, or the like.

If necessary, the second metal layer112B may be connected to a redistribution pattern serving as a ground (GND) pattern among conductive patterns132of the redistribution layer130. Alternatively, the second metal layer112B may be connected to a dummy pattern among the conductive patterns132of the redistribution layer130. In this case, heat may be more easily dispersed downwardly from the package100A. However, the second metal layer112B is not limited thereto, and heat may also be transferred by diffusion in a state in which the second metal layer112B is not connected to the conductive pattern132.

The third metal layer112A may diffuse heat transferred through the first metal layer111, or the like, upwardly from the package100A. In addition, the third metal layer112A may further improve the electromagnetic wave shielding effect. The third metal layer112A may be disposed on the upper surface110A of the frame110, and according to the example, the third metal layer112A may be a layer entirely covering the upper surface110A, and thus the problems of heat generation and electromagnetic interference may be more effectively controlled. The third metal layer112A may also contain a conductive material, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), an alloy thereof, or the like.

The redistribution layer130may be a configuration for redistributing the electrode pad120P of the electronic component120. Several tens to several hundreds of electrode pads120P having various functions may be redistributed through the redistribution layer130, and physically and/or electrically connected externally depending on the functions thereof through an external connection terminal165to be described below.

The redistribution layer130may include an insulating layer131, a conductive pattern132disposed on the insulating layer131, and a conductive via133penetrating through the insulating layer131. In the electrode component package100A according to the example, the redistribution layer130may be composed of a single layer. However, the redistribution layer130is not limited thereto, and may be composed of a plurality of layers as described below.

As a material of the insulating layer131, an insulating material may be used. In this case, as the insulating material, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin in which a reinforcement material, such as a glass fiber or an inorganic filler, is impregnated in the thermosetting resin and the thermoplastic resin, for example, a pre-preg, Ajinomoto build-up film (ABF), FR-4, a bismaleimide triazine (BT) resin, or the like, may be used. In a case of using a photosensitive insulating material such as a photo imageable dielectric (PID) resin, the insulating layer131may be formed to be thinner, and a fine pitch may be easily implemented. The insulating layers131may be formed of the same material as each other, or different materials from each other, if necessary. A thickness of the insulating layer131is also not particularly limited. For example, a thickness of the insulating layer131except for the conductive pattern132may be 5 μm to 20 μm or so, and in the consideration of a thickness of the conductive pattern132, the insulating layer131may have a thickness of 15 μm to 70 μm or so.

The conductive pattern132may serve as a redistribution pattern, and as a material for forming the conductive pattern132, a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), an alloy thereof, or the like, may be used. The conductive patterns132and142may perform various functions depending on a design of the corresponding layer. For example, the conductive pattern132may perform a role of a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, or the like. Here, the signal (S) pattern may include various signal patterns, for example, a data signal pattern, or the like, except for the GND pattern, the PWR pattern, and the like. Further, the conductive pattern132may perform a role of a via pad, an external connection terminal pad, or the like. A thickness of the conductive pattern132is also not particularly limited. For example, each of the conductive patterns132may have a thickness of 10 μm to 50 μm or so.

If necessary, a surface treatment layer may be further formed on an exposed conductive pattern132among the conductive patterns132. The surface treatment layer is not particularly limited as long as it is known in the art. For example, the surface treatment layer may be formed by electrolytic gold plating, electroless gold plating, organic solderability preservative (OSP) surface treatment or electroless tinplating, electroless silver plating, electroless nickel plating/displacement gold plating, direct immersion gold (DIG) plating, hot air solder leveling (HASL), or the like.

The conductive via133may electrically connect the conductive pattern132, the electrode pad120, and the like, to each other, which are formed on different layers from each other, thereby forming an electric path in the package100A. A conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), an alloy thereof, or the like, may be used as a material for forming the conductive via133. The conductive via133may also be completely filled with the conductive material, or the conductive material may be formed on a wall of the via. Further, all shapes known in the art, such as a tapered shape of which a diameter is decreased downwardly, a reversely tapered shape of which a diameter is increased downwardly, a cylindrical shape, and the like, may be applied to the conductive via133.

The encapsulant150may be a configuration for protecting the electronic component120. To this end, the encapsulant150may encapsulate the electronic component120. A shape of the encapsulant150is not particularly limited as long as the encapsulant150at least partially encloses the electronic component120. According to the example, the encapsulant150may cover upper portions of the frame110and the electronic component120. As a result, the encapsulant may fill the remaining space in the cavity110X of the frame110. Here, the term “covers upper portions” may include a case in which a target component is disposed in the corresponding direction but does not contact a component to be a basis as well as a case in which the target component directly contacts the component to be the basis. Meanwhile, the encapsulant150fills the cavity110X, and thus the encapsulant150may serve to decrease buckling of the electronic component120while serving as an adhesive depending on a specific material of the encapsulant150.

The encapsulant150may be composed of a plurality of layers formed of a plurality of materials. For example, a space in the cavity110X may be filled with a first encapsulant, and then, the upper portions of the frame110and the electronic component120may be covered with a second encapsulant. Alternatively, after covering the upper portions of the frame110and the electronic component120at a predetermined thickness while filling the space in the cavity110X using the first encapsulant, the second encapsulant may be used to cover the first encapsulant again at a predetermined thickness. Besides, the encapsulant150may be applied in various forms.

A specific material of the encapsulant150is not particularly limited. For example, as the material of the encapsulant150, an insulating material may be used. Here, as the insulating material, similarly, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin in which a reinforcement material, such as a glass fiber or an inorganic filler, is impregnated in the thermosetting resin and the thermoplastic resin, for example, a pre-preg, ABF, FR-4, a BT resin, a photo imageable dielectric (PID) resin, or the like, may be used. Further, a molding material known in the art such as an epoxy molding compound (EMC), or the like, may also be used.

The encapsulant150may have an elastic modulus lower than that of a material of the frame110. For example, the encapsulant150may have an elastic modulus of 15 GPa or less, for example, 50 MPa to 15 GPa or so. As the elastic modulus of the encapsulant150is relatively decreased, warpage of the package100A may be further decreased through a buckling effect and a stress dispersion effect on the electronic component120. In detail, since the encapsulant150fills the space of the cavity110X, the encapsulant150may have the buckling effect on the electronic component120, and since the encapsulant150covers the electronic component120, the encapsulant150may disperse and alleviate stress generated in the electronic component120. However, in a case in which the elastic modulus is excessively small, the encapsulant150may not perform basic roles thereof due to excessive deformation.

If necessary, a conductive particle may be contained in the encapsulant150for shielding the electromagnetic wave. As the conductive particle, any conductive particle may be used as long as it may shield the electromagnetic wave. For example, the conductive particle may be formed of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), solder, or the like. However, these materials are only examples, and the conductive particle is not particularly limited thereto.

An interval of the space in the cavity110X filled with the encapsulant150is not particularly limited, and may be optimized by a person with ordinary skill in the art. For example, the interval may be 10 μm to 150 μm or so, but is not limited thereto.

The electronic component package100A according to the example may further include an external layer160disposed below the redistribution layer130. The external layer160may be a configuration for protecting the redistribution layer130from external physical or chemical damages, or the like. The external layer160may have an opening161exposing at least a portion of the conductive pattern132of the redistribution layer130. The opening161may expose one surface of a portion of the conductive patterns132, but in some cases, the opening161may expose a side surface thereof.

A material of the external layer160is not particularly limited. For example, a solder resist may be used. Besides, the same material as that of the insulating layer131of the redistribution layer130, for example, the same PID resin may also be used. The external layer160may be generally a single layer, but may be configured as a plurality of layers, as needed.

The electronic component package100A according to the example may further include an external connection terminal165externally exposed through a lower surface of the external layer160. The external connection terminal165may be a configuration for physically and/or electrically connecting the electronic component package100A externally. For example, the electronic component package100A may be mounted on a main board of an electronic device through the external connection terminal165. The external connection terminal165may be disposed in the opening161and connected to the conductive pattern132exposed to the opening161. Therefore, the external connection terminal165may also be electrically connected to the electronic component120.

The external connection terminal165may be formed of a conductive material, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), solder, or the like. However, these materials are only examples, and the material of the external connection terminal165is not particularly limited thereto. The external connection terminal165may be a land, a ball, a pin, or the like. The external connection terminal165may be formed of a multilayer or a single layer. In a case in which the external connection terminal165is formed of the multilayer, the external connection terminal165may contain a copper pillar and solder, and in a case in which the external connection terminal165is formed of the single layer, the external connection terminal165may contain tin-silver solder or copper. However, these cases are only examples, and the external connection terminal165is not limited thereto.

Some of the external connection terminals165may be disposed in a fan-out region. The fan-out region may be defined as a region deviated from a region in which the electronic component120is disposed. That is, the electronic component package100A according to the example may be a fan-out package. In the case of the fan-out package, reliability may be more excellent as compared to a fan-in package, a plurality of I/O terminals may be implemented, and 3D interconnection may be easily performed. Further, since the fan-out package may be mounted on an electronic device without a separate board as compared to a ball grid array (BGA) package, a land grid array (LGA) package, or the like, the fan-out package may be manufactured to have a reduced thickness, and price competitiveness may be excellent.

The number, an interval, a disposition shape, or the like, of external connection terminal165are not particularly limited, and may be sufficiently changed by a person skilled in the art depending on a design. For example, the number of external connection terminals165may be several tens to several thousands depending on the number of electrode pads120P of the electronic component120, but is not limited thereto. The number of external connection terminals165may be more than or less than the above-mentioned range.

FIGS. 5A through 5Eillustrate an example of a schematic manufacturing process of the electronic component package ofFIG. 3.

Among descriptions of the example of the manufacturing process of the electronic component package100A, a description overlapping the description of the electronic component package100A described above will be omitted, and a difference therebetween will be mainly described below.

Referring toFIG. 5A, a frame110may be prepared. Here, A indicates a plan diagram of the frame110, and B illustrates a cross section of some region capable of being utilized as a unit package in A. The frame110may be manufactured to have various sizes to thereby be utilized so that mass production may be easily performed. That is, after preparing a large size frame110, a plurality of electronic component packages100A may be manufactured through a process to be described below. Then, the plurality of electronic component packages100may be singulated into individual packages100by sawing. A fiducial mark for excellent pick-and-place (P&P) may be provided on the frame110, and thus a position at which an electronic component120is mounted may be more accurately confirmed through the fiducial mark, thereby improving manufacturing completeness.

Referring toFIG. 5B, a cavity110X penetrating through the frame110may be formed. Here, A indicates a plan diagram of the frame110in which the cavities110X are formed, and B illustrates a cross section of some region capable of being utilized as a unit package in A. A method of forming the cavity110X is not particularly limited. For example, the cavity110X may be formed by a mechanical and/or laser drill method, a sand-blasting method using polishing particles, a dry etching method using plasma, or the like. In a case in which the cavity110X is formed using a mechanical drill and/or the laser drill, desmear treatment such as a permanganate method, or the like, may be performed to remove resin smear in the cavity110X. A size, a shape, or the like, of the cavity110X may be designed to be suitable for a size, a shape, the number, or the like, of an electronic component120to be mounted.

Referring toFIG. 5C, metal layers111,112A, and112B may be formed on upper and lower surfaces110A and110B of the frame110and an inner wall of the cavity110X. Here, A indicates a plan diagram of the frame110in which the metal layers111,112A, and112B are formed, and B illustrates a cross section of some region capable of being utilized as a unit package in A. The metal layers111,112A, and112B may be formed by a method known in the art. For example, the metal layers111,112A, and112B may be formed by electrolytic copper plating, electroless copper plating, or the like. In more detail, the metal layers111,112A, and112B may be formed by a method such as a chemical vapor deposition (CVD) method, a physical vapor deposition (PVD) method, a sputtering method, a subtractive method, an additive method, a semi-additive process (SAP), a modified semi-additive process (MSAP), or the like, but is not limited thereto.

Referring toFIG. 5D, the electronic component120may be disposed in the cavity110X. The electronic component120may be disposed in a face-down manner so that the electrode pad120P faces downwardly. However, the electronic component120is not limited thereto, and if necessary, the electronic component120may also be disposed in a face-up manner. Thereafter, the electronic component120may be encapsulated using an encapsulant150. The encapsulant150may fill a space in the cavity110X while covering upper portions of the frame110and the electronic component120. The encapsulant150may be formed by a method known in the art. For example, the encapsulant150may be formed by laminating a precursor of the encapsulant150and curing the laminated precursor. Alternatively, the encapsulant150may be applied in a state in which a lower portion of the cavity110is closed using a tape (not illustrated), or the like, so as to encapsulate the electronic component120, and then the applied encapsulant150may be cured. The electronic component120may be fixed by curing. As the method of laminating the precursor, for example, a method of performing a hot press method of pressing an object at a high temperature for a predetermined time, cooling the object to room temperature by decompression, and then separating a working tool in a cold press by cooling, or the like, may be used. As an application method, for example, a screen printing method of applying ink using a squeegee, a spray printing method of misting ink to apply the ink, or the like, may be used.

Referring toFIG. 5E, a redistribution layer130may be formed below the frame110and the electronic component120. In detail, an insulating layer131may be formed below the frame110and the electronic component120, and then, a conductive pattern132and a conductive via133may be formed, and thus the redistribution layer130may be formed.

The insulating layer131may be formed by a method known in the art. For example, the insulating layer131may be formed by a method of laminating a precursor of the insulating layer131and curing the laminated precursor, a method of applying a material of the insulating layer131and curing the applied material, or the like, but is not limited thereto. As the method of laminating the precursor, for example, a method of performing a hot press method of pressing an object at a high temperature for a predetermined time, cooling the object to room temperature by decompression, and then separating a working tool in a cold press by cooling, or the like, may be used. As an application method, for example, a screen printing method of applying ink using a squeegee, a spray printing method of misting ink to apply the ink, or the like, may be used. The curing process, which is a post-process, may be a process of drying the encapsulation material so as not be completely cured in order to use a photolithography process, or the like.

The conductive pattern132and the conductive via133may also be formed by a method known in the art. First, a via hole (not illustrated) may be formed using the mechanical drill and/or laser drill as described above, and in a case in which the insulating layer131contains a PID resin, or the like, the via hole may also be formed using a photolithography method. The conductive pattern132and the conductive via133may be formed using a dry film pattern by electrolytic copper plating, electroless copper plating, or the like.

After the redistribution layer130is formed, an external layer160may be formed below the redistribution layer130. Similarly, the external layer160may be formed by a method of laminating a precursor of the external layer160and curing the laminated precursor, a method of applying a material for forming the external layer160and curing the applied material, or the like. Thereafter, an opening161may be formed in the external layer160so that the conductive pattern132is at least partially exposed. The opening161may be formed using a mechanical drill and/or laser drill. Alternatively, the opening161may be formed by a photolithography method.

After the opening161is formed in the external layer160, an external connection terminal165disposed in the opening161may be formed. A method of forming the external connection terminal165is not particularly limited, and the external connection terminal165may be formed by a method well-known in the art depending on a structure or shape thereof. The external connection terminal165may be fixed by reflow, and in order to increase fixation power, a portion of the external connection terminal165may be embedded in the external layer160, and the other portion thereof may be externally exposed, thereby improving reliability. In some cases, only the opening161may be formed, and the external connection terminal165may be formed by a separate process in a purchase customer of the package100A as needed.

FIG. 6is a cross-sectional diagram schematically illustrating another example of the electronic component package.

FIG. 7is a schematic cut-away plan diagram of the electronic component package taken along line II-II′ ofFIG. 6.

Referring toFIGS. 6 and 7, in an electronic component package100B according to another example, an encapsulant150may also enclose outer side surfaces of a frame110. When the frame110is enclosed by the encapsulant150as described above, the frame110is not externally exposed, and thus reliability may be improved by prevention of oxidation, or the like. Since a description of each of the configurations included in the electronic component package100B according to another example overlaps the description described above, a description thereof will be omitted. Further, since a method of manufacturing the electronic component package100B according to another example is the same as the method of manufacturing the electronic component package100A described above except for forming the frame110so that the encapsulant150encloses the outer side surfaces of the frame110, etc., a description thereof will be omitted.

FIG. 8is a cross-sectional diagram schematically illustrating another example of the electronic component package.

FIG. 9is a schematic cut-away plan diagram of the electronic component package taken along line III-III′ of FIG.8.

Referring toFIGS. 8 and 9, an electronic component package100C according to another example may further include a penetration wiring113penetrating through a frame110, and second and third metal layers112B and112A disposed on lower and upper surfaces110B and110A of the frame110may be patterned. Hereinafter, each of the configurations included in the electronic component package100C according to another example will be described in more detail, but a description overlapping the description described above will be omitted, and a difference therebetween will be mainly described.

The penetration wiring113penetrating through the upper and lower surfaces110A and110B of the frame110may serve to electrically connect conductive patterns disposed on different layers to each other, and a material for forming the penetration wiring113, a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), an alloy thereof, or the like, may be used. Upper and lower portions of the electronic component package100C may be electrically connected to each other through left and right side surfaces of the electronic component120by the penetration wiring113, and thus space utilization may be significantly increased. Therefore, the electronic component package100C may be applied to a package on package (PoP), or the like, through connection in a three-dimensional structure, and thus the electronic component package100C may be widely applied to various current modules or package application products. The number, an interval, a disposition shape, and the like, of the penetration wiring113are not particularly limited, and may be sufficiently changed by a person skilled in the art depending on a design. The penetration wiring113may be connected to a pad pattern serving as a pad of the penetration wiring among the second and third metal layers112B and112A. For example, the penetration wiring113may be disposed only in a specific region of the frame110as illustrated inFIG. 9depending on a shape of another package mounted on the electronic component package100C. Unlike this, the penetration wiring113may be disposed on the entire surface of the frame110. In a case of using a metal, for example, an Fe—Ni based alloy, or the like, as the material of the frame110, an insulating material may be disposed between the metal and the penetration wiring113and/or the metal layers112A and112B for electrical insulation with the penetration wiring113or the metal layers112A and112B.

The second and third metal layers112B and112A may also serve as redistribution patterns, and as a material for forming the second and third metal layers112B and112A, a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), an alloy thereof, or the like, may be used. The second and third metal layers112B and112A may perform various functions depending on a design of the corresponding layer. For example, the second and third metal layers112B and112A may perform roles of a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, a bond finger (BF) pattern, and the like. Here, the signal (S) pattern may include various signal patterns, for example, a data signal pattern, or the like, except for the GND pattern, the PWR pattern, the bond finger (BF) pattern, and the like. Further, the second and third metal layers112B and112A may perform roles of a via pad, a penetration wiring pad, an external connection terminal pad, and the like. A thickness of the second and third metal layers112B and112A is also not particularly limited. For example, each of the second and third metal layers112B and112A may have a thickness of 10 μm to 50 μm or so. In some cases, the second and third metal layers112B and112A may be dummy patterns without a redistribution function. According to another example, the second and third metal layers112B and112A may not be connected to a first metal layer111. However, in a case in which the second and third metal layers112B and112A are ground (GND) patterns or dummy patterns, the second and third metal layers112B and112A may be connected to the first metal layer111, but are not limited thereto.

In the electronic component package100C according to another example, an encapsulant150may have an opening151at least partially exposing the third metal layer112A disposed on the upper surface110A of the frame110. Further, the electronic component package100C may further include an external connection terminal175externally exposed through an outer edge surface of the encapsulant150. The external connection terminal175may be a configuration for physically and/or electrically connecting another electronic component, another package, or the like, on the electronic component package100C to the electronic component package100C. For example, another electronic component package may be mounted on the electronic component package100C through the external connection terminal175, thereby forming a package-on-package structure. The external connection terminal may be disposed in the opening151of the encapsulant150and connected to the third metal layer112A exposed through the opening151. Therefore, the external connection terminal may be electrically connected to the electronic component120.

The external connection terminal175may be formed of a conductive material, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), solder, or the like. However, these materials are only examples, and the material of the external connection terminal175is not particularly limited thereto. The external connection terminal175may be a land, a ball, a pin, or the like. The external connection terminal175may be formed of a multilayer or a single layer. In a case in which the external connection terminal175is formed of the multilayer, the external connection terminal175may contain a copper pillar and solder, and in a case in which the external connection terminal175is formed of the single layer, the external connection terminal175may contain tin-silver solder or copper. However, these cases are only examples, and the external connection terminal175is not limited thereto.

Meanwhile, unlike that illustrated inFIGS. 8 and 9, the electronic component package100C according to another example may also be modified in a form in which a characteristic form of the electronic component package100B described above is applied. Further, since a method of manufacturing the electronic component package100C according to another example is the same as that of the electronic component package100A described above except for forming the penetration wiring130in the frame110in advance and patterning the second and third metal layers112B and112A, etc., a description thereof will be omitted.

FIG. 10is a cross-sectional diagram schematically illustrating another example of the electronic component package.

FIG. 11is a schematic cut-away plan diagram of the electronic component package taken along line IV-IV′ ofFIG. 10.

Referring toFIGS. 10 and 11, an electronic component package100D according to another example may further include a penetration wiring113penetrating through a frame110, and second and third metal layers112B and112A disposed on lower and upper surfaces110B and110A of the frame110may be patterned. In addition, the electronic component package100D may include an outer edge conductive pattern152disposed on the encapsulant150, and an outer edge conductive via153partially penetrating through the encapsulant150. Hereinafter, each of the configurations included in the electronic component package100D according to another example will be described in more detail, but a description overlapping the description described above will be omitted, and a difference therebetween will be mainly described.

Similarly, the number, an interval, a disposition shape, and the like, of penetration wiring113penetrating through the upper and lower surfaces110A and110B of the frame110are not particularly limited, and may be sufficiently changed by a person skilled in the art depending on a design. For example, the penetration wiring113may be disposed on the entire surface of the frame110as illustrated inFIG. 11depending on a shape of another package mounted on the electronic component package100D. Unlike this, the penetration wiring113may be disposed only in a specific region of the frame110.

The outer edge conductive pattern152disposed on the encapsulant150may serve as a redistribution pattern, and as a material for forming the outer edge conductive pattern152, a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), an alloy thereof, or the like, may be used. A specific example is as described above. The outer edge conductive pattern152may perform various functions depending on a design of the corresponding layer. For example, the outer edge conductive pattern152may perform a role of aground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, or the like. Here, the signal (S) pattern may include various signal patterns, for example, a data signal pattern, or the like, except for the ground (GND) pattern, the power (PWR) pattern, and the like. Further, the outer edge conductive pattern152may perform a role of a via pad, an external connection terminal pad, or the like. The outer edge conductive pattern152may be disposed on the entire surface of the encapsulant150, and an external connection terminal175may also be disposed on an entire surface of a cover layer170to be described below in accordance with the outer edge conductive pattern152, and thus the electronic component package may be variously designed. A thickness of the outer edge conductive pattern152is also not particularly limited. For example, each of the outer edge conductive patterns152may have a thickness of 10 μm to 50 μm or so. If necessary, the outer edge conductive pattern152may be disposed to substantially mostly cover an upper region of the electronic component120based on an area of a plane occupied by the electronic component120. In this case, since all surfaces of the electronic component120are enclosed by conductive ingredients, electromagnetic waves may be effectively shielded.

The outer edge conductive via153partially penetrating the encapsulant150may be electrically connected conductive patterns112A and152formed on different layers from each other, thereby forming an electrical path in the package100D. A conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), an alloy thereof, or the like, may also be used as a material for forming the outer edge conductive via153. The outer edge conductive via153may be completely filled with the conductive material, or the conductive material may be formed on a wall of the via. Further, all shapes known in the art, such as a tapered shape of which a diameter is decreased downwardly, a reversely tapered shape of which a diameter is increased downwardly, a cylindrical shape, and the like, may be applied to the outer edge conductive via153.

The electronic component package100D according to another example may further include a cover layer170disposed on the encapsulant150. The cover layer170may be a configuration for protecting the encapsulant150, the outer edge conductive pattern152, and the like, from external physical or chemical damages, or the like. The cover layer170may have an opening171at least partially exposing the outer edge conductive pattern152disposed on the encapsulant150. The opening171may expose one surface of a portion of the outer edge conductive patterns152, but in some cases, the opening171may expose a side surface thereof. A material of the cover layer170is not particularly limited. For example, a solder resist may be used. In addition, various PID resins may be used. If necessary, the cover layer170may be composed of a plurality of layers.

The electronic component package100D according to another example may further include an external connection terminal175disposed in the opening171of the cover layer170. The external connection terminal175may be disposed in the opening171and connected to the outer edge conductive pattern152exposed to the opening171. The external connection terminal175may be formed of a conductive material, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), solder, or the like. However, these materials are only examples, and the material of the external connection terminal175is not particularly limited thereto. The external connection terminal175may be a land, a ball, a pin, or the like. The external connection terminal175may be formed of a multilayer or a single layer. In a case in which the external connection terminal175is formed of the multilayer, the external connection terminal175may contain a copper pillar and solder, and in a case in which the external connection terminal175is formed of the single layer, the external connection terminal175may contain tin-silver solder or copper. However, these cases are only examples, and the external connection terminal175is not limited thereto. If necessary, various separate passive components (not illustrated) may also be disposed in the openings171.

Meanwhile, unlike that illustrated inFIGS. 10 and 11, the electronic component package100D according to another example may also be modified in a form in which a characteristic form of the electronic component package100B described above is applied. Further, since a method of manufacturing the electronic component package100D according to another example is the same as the method of manufacturing the electronic component package100A described above except for forming the outer edge conductive pattern152, the outer edge conductive via153, etc., a description thereof will be omitted.

FIG. 12is a cross-sectional diagram schematically illustrating another example of the electronic component package.

FIG. 13is a schematic cut-away plan diagram of the electronic component package taken along line V-V′ ofFIG. 12. Referring toFIGS. 12 and 13, in an electronic component package100E according to another example, among electronic components120and124, at least one may be an integrated circuit120, and at least another may be a passive component124. Hereinafter, each of the configurations included in the electronic component package100E according to another example will be described in more detail, but a description overlapping the description described above will be omitted, and a difference therebetween will be mainly described.

The integrated circuit120may be a chip in which at least hundreds to millions or more of various elements are integrated with each other. For example, the integrated circuit120may be an application processor chip such as a central processor (for example, a central processing unit (CPU)), a graphics processor (for example, a graphics processing unit (GPU)), a digital signal processor, a cryptographic processor, a micro processor, a micro controller, or the like, but is not limited thereto. The passive component124may be, for example, an inductor, a condenser, a resistor, or the like, but is not limited thereto. The integrated circuit120may be electrically connected to a redistribution layer130through an electrode pad120P. The passive component124may be electrically connected to the redistribution layer through an electrode pad (not illustrated), for example, an external electrode.

The numbers, intervals, disposition shapes, and the like, of the integrated circuit120and the passive component124are not particularly limited, and may be sufficiently changed by a person skilled in the art depending on a design. For example, the integrated circuit120may be disposed in the vicinity of the center of a cavity110X, and the passive component124may be disposed in the vicinity of an inner wall of the cavity110X, but the integrated circuit120and the passive component124are not limited thereto. In addition, only a single integrated circuit120may be disposed, and a plurality of passive components124may be disposed. However, the integrated circuit120and the passive component124are not limited thereto. That is, a plurality of integrated circuits120and a single passive component124may be disposed. Alternatively, only a single integrated circuit120and a single passive component124may also be disposed, or a plurality of integrated circuits120and a plurality of passive components may also be disposed.

Meanwhile, unlike that illustrated inFIGS. 12 and 13, the electronic component package100E according to another example may also be modified in a form in which characteristic forms of the electronic component packages100B to100D described above are applied. Further, since a method of manufacturing the electronic component package100E according to another example is the same as the method of manufacturing the electronic component package100A described above except for disposing the integrated circuit120and the passive component124together with each other as the electronic components120and124, etc., a description thereof will be omitted.

FIG. 14is a cross-sectional diagram schematically illustrating another example of the electronic component package.

FIG. 15is a schematic cut-away plan diagram of the electronic component package taken along line VI-VI′ ofFIG. 14.

Referring toFIGS. 14 and 15, an electronic component package100F according to another example may include a plurality of electronic components120and122. Hereinafter, each of the configurations included in the electronic component package100F according to another example will be described in more detail, but a description overlapping the description described above will be omitted, and a difference therebetween will be mainly described.

The plurality of electronic components120and122may be the same as or different from each other. The plurality of electronic components120and122may include electrode pads120P and122P electrically connected to a redistribution layer130, respectively. The electrode pads120P and122P may be redistributed by the redistribution layer130, respectively. The numbers, intervals, disposition shapes, and the like, of the plurality of electronic components120and122are not particularly limited, and may be sufficiently changed by a person skilled in the art depending on a design. For example, the number of plurality of electronic components120and122may be two as illustrated inFIGS. 14 and 15, but is not limited thereto. That is, three, four, or more electronic components may be disposed.

Meanwhile, unlike that illustrated inFIGS. 14 and 15, the electronic component package100F according to another example may also be modified in a form in which characteristic forms of the electronic component packages100B to100E described above are applied. Further, since a method of manufacturing electronic component package100F according to another example is the same as the method of manufacturing the electronic component package100A described above except for disposing the plurality of electronic components120and122, etc., a description thereof will be omitted.

FIG. 16is a cross-sectional diagram schematically illustrating another example of the electronic component package.

FIG. 17is a schematic cut-away plan diagram of the electronic component package taken along line VII-VII′ ofFIG. 16.

Referring toFIGS. 16 and 17, an electronic component package100G according to another example may include a plurality of cavities110X1and110X2, and electronic components120and122may be disposed in the cavities110X1and110X2, respectively. Hereinafter, each of the configurations included in the electronic component package100G according to another example will be described in more detail, but a description overlapping the description described above will be omitted, and a difference therebetween will be mainly described.

Areas, shapes, or the like, of the plurality of cavities110X1and110X2may be the same as or different from each other, and the electronic components120and122disposed in the cavities110X1and110X2, respectively, may also be the same as or different from each other. The numbers, intervals, disposition shapes, and the like, of the plurality of cavities110X1and110X1and the electronic components120and122disposed therein, respectively, are not particularly limited, and may be sufficiently changed by a person skilled in the art depending on a design. For example, the number of plurality of cavities110X1and110X2may be two as illustrated inFIGS. 16 and 17, but is not limited thereto. That is, the number of plurality of cavities110X1and110X2may be three, four, or more. Further, the number of electronic components120and122disposed in the cavities110X1and110X2, respectively, may be one as illustrated inFIGS. 16 and 17, but is not limited thereto. That is, the number of electronic components120and122may be two, three, or more.

Meanwhile, unlike that illustrated inFIGS. 16 and 17, the electronic component package100G according to another example may also be modified in a form in which characteristic forms of the electronic component packages100B to100F described above are applied. Further, since a method of manufacturing the electronic component package100G according to another example is the same as the method of manufacturing the electronic component package100A described above except for forming the plurality of cavities110X1and110X2, and then disposing the electronic components120and122therein, respectively, etc., a description thereof will be omitted.

FIG. 18is a cross-sectional diagram schematically illustrating another example of the electronic component package.

Referring toFIG. 18, in an electronic component package100H according to another example, metal layers111and112B may be disposed only on an inner wall of a cavity110X and a lower surface110B of a frame110. Hereinafter, each of the configurations included in the electronic component package100H according to another example will be described in more detail, but a description overlapping the description described above will be omitted, and a difference therebetween will be mainly described.

In some cases, a metal layer112A may not also be disposed on an upper surface110A of the frame110as in the electronic component package100H according to another example. However, only when the metal layers111and112B are disposed on the inner wall of the cavity110X and the lower surface110B of the frame110may a heat radiation effect and an electromagnetic wave shielding effect be sufficiently obtained.

Meanwhile, unlike that illustrated inFIG. 18, the electronic component package100H according to another example may also be modified in a form in which characteristic forms of the electronic component package100B to100G described above are applied. Further, since a method of manufacturing the electronic component package100H according to another example is the same as the method of manufacturing the electronic component package100A described above except that the metal layer112A is not formed on the upper surface110A of the frame110, etc., a description thereof will be omitted.

FIG. 19is a cross-sectional diagram schematically illustrating another example of the electronic component package.

Referring toFIG. 19, an electronic component package100I according to another example may further include a metal layer158disposed on an encapsulant150. Hereinafter, each of the configurations included in the electronic component package100I according to another example will be described in more detail, but a description overlapping the description described above will be omitted, and a difference therebetween will be mainly described.

In a case in which the electronic component package100I has the metal layer158, heat radiation characteristics and electromagnetic wave shielding characteristics may be further improved. As a material for forming the metal layer158, any conductive material may be used without particular limitation. As the conductive material, similarly, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), an alloy thereof, or the like, may be used, but the conductive material is not limited thereto.

Meanwhile, unlike that illustrated inFIG. 19, the electronic component package100I according to another example may also be modified in a form in which characteristic forms of the electronic component package100B to100H described above are applied. Further, since a method of manufacturing the electronic component package100I according to another example is the same as the method of manufacturing the electronic component package100A described above except for forming the metal layer158on the encapsulant150, etc., a description thereof will be omitted.

FIG. 20is a cross-sectional diagram schematically illustrating another example of the electronic component package.

Referring toFIG. 20, in an electronic component package100J according to another example, redistribution layers130and140may be composed of a plurality of layers. Hereinafter, each of the configurations included in the electronic component package100J according to another example will be described in more detail, but a description overlapping the description described above will be omitted, and a difference therebetween will be mainly described.

The redistribution layers130and140may be composed of a plurality of layers depending on the kind of electronic component, and unlike that illustrated inFIG. 20, the redistribution layers130and140may be composed of two or more layers. The redistribution layers130and140may include insulating layers131and141, conductive patterns132and142, and a conductive via133, respectively. Since a description of the redistribution layers130and140is the same as described above, the description thereof will be omitted.

Meanwhile, unlike that illustrated inFIG. 20, the electronic component package100J according to another example may also be modified in a form in which characteristic forms of the electronic component packages100B to100I described above are applied. Further, since a method of manufacturing the electronic component package100J according to another example is the same as the method of manufacturing the electronic component package100A described above except that the redistribution layers130and140are composed of the plurality of layers, etc., a description thereof will be omitted.

FIG. 21is a cross-sectional diagram schematically illustrating another example of the electronic component package.

Referring toFIG. 21, in an electronic component package100K according to another example, some of conductive patterns132and142included in redistribution layers130and140may be disposed to substantially mostly cover a lower region of the electronic component120based on an area of a plane occupied by an electronic component120.

Hereinafter, each of the configurations included in the electronic component package100K according to another example will be described in more detail, but a description overlapping the description described above will be omitted, and a difference therebetween will be mainly described.

Some of the conductive patterns132and142disposed to substantially mostly cover the lower region of the electronic component120based on the area of the plane occupied by the electronic component120may be a ground (GND) pattern or a dummy pattern. However, in any case, since all surfaces of the electronic components120are enclosed by conductive ingredients, an electromagnetic wave may be effectively shielded.

Meanwhile, unlike that illustrated inFIG. 21, the electronic component package100K according to another example may also be modified in a form in which characteristic forms of the electronic component packages100B to100J described above are applied. Further, since a method of manufacturing the electronic component package100K according to another example is the same as the method of manufacturing the electronic component package100A described above except that some of the conductive patterns132and142included in the redistribution layers130and140are disposed to substantially cover all of the lower region of the electronic component120based on the area of the plane occupied by the electronic component120, etc., a description thereof will be omitted.

FIG. 22illustrates heat radiation simulation results of various electronic component packages.

FIG. 23illustrates temperature-cross sectional area distribution of the electronic component packages ofFIG. 22.

A base model is a case in which an electronic component is simply encapsulated with an encapsulant, case1is a case in which a frame is introduced, but metal layers are disposed on upper and lower surfaces of the frame, case2is a case in which a metal layer is also disposed on an inner wall of a cavity, and case3is a case in which a thickness of the metal layers disposed on the upper and lower surfaces of the frame is increased from 10 μm to 30 μm. As illustrated in FIG.22, it may be appreciated that a heat radiation effect may be further increased in a direction from the base model toward case3. That is, it may be appreciated that heat may be more easily diffused. Further, it may be appreciated that particularly in a case in which a thickness of the metal layer is 30 μm or more, the heat radiation effect may be excellent.

As set forth above, according to exemplary embodiments in the present disclosure, the electronic component package capable of solving various problems caused by heat generation and electromagnetic interference, and the method of manufacturing the same to efficiently manufacture the electronic component package may be provided.

Meanwhile, in the present disclosure, the term ‘connected to’ includes that one component is not only directly connected to another component, but is also indirectly connected to another component through an adhesive, or the like. Meanwhile, the term ‘electrically connected’ includes both of a case in which one component is physically connected to another component and a case in which any component is not physically connected to another component. Meanwhile, in the present disclosure, terms “first”, “second”, and the like, are used to distinguish one component from another component, and do not limit a sequence, importance, and/or the like, of the corresponding components. In some cases, a first component may be named a second component, and a second component may also be similarly named a first component, without departing from the scope of the present disclosure.

Meanwhile, a term “example” used in the present disclosure does not mean the same example, but is provided in order to emphasize and describe different unit features. However, the above suggested examples may also be implemented to be combined with a feature of another example. For example, even though particulars described in a specific example are not described in another example, it may be understood as a description related to another example unless described otherwise.

Meanwhile, terms used in the present disclosure are used only in order to describe an example rather than limiting the present disclosure. Here, singular forms include plural forms unless a context clearly indicates otherwise.