Output stage of operational amplifier and method in the operational amplifier

An embodiment discloses an operational amplifier comprising: an input stage; an output stage communicatively coupled to the input stage, wherein the output stage further comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a first current source, a fifth transistor, a sixth transistor and a second current source, wherein a second node of the first transistor is connected to the input stage (vin), a third node of the first transistor is connected to a third node of the fourth transistor, ground (gnd), a third node of the fifth transistor and a third node of the third transistor, a first node of the first transistor is connected to a first node of the first current source, a second node of the sixth transistor and a second node of the second transistor.

CROSS REFERENCE OF RELATED APPLICATIONS

This application claims priority to Chinese Application number 201710707753.X entitled “operational amplifier and method in the operational amplifier,” filed on Aug. 17, 2017 by Beken Corporation, which is incorporated herein by reference.

TECHNICAL FIELD

The present application relates to circuits and more particularly, but not exclusively, to an operational amplifier and method in the operational amplifier.

BACKGROUND

Conventional output stage of class AB operational amplifier needs a relatively high output stage biasing to generate a normal operation voltage, such as a sum of at least two gates to source voltage in field effect transistors (Vgs). Otherwise, the operational amplifier may not work properly.

SUMMARY

An operational amplifier comprises an input stage; an output stage communicatively coupled to the input stage, wherein the output stage comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a first current source, a fifth transistor, a sixth transistor and a second current source; wherein a second node of the first transistor is connected to the input stage (vin), a third node of the first transistor is connected to a third node of the fourth transistor, ground (gnd), a third node of the fifth transistor and a third node of the third transistor, a first node of the first transistor is connected to a first node of the first current source, a second node of the sixth transistor and a second node of the second transistor; a third node of the sixth transistor and second node of the second current source, a second node of the first current source, and a third node of the second transistor are connected to a power supply (Vdd); a first node of the second transistor is connected to a first node of the third transistor and configured to output voltage (vo); a second node of the third transistor is connected to a connection point between a first node of the fifth transistor and a first node of the second current source; and both a first node and a second node of the fourth transistor are connected to both a second node of the fifth transistor and a first node of the sixth transistor.

Another operational amplifier comprises an input stage; an output stage communicatively coupled to the input stage, wherein the output stage comprises a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a second current source, a third node of the fifth transistor and a third node of the third transistor are connected to a power supply (Vdd), a second node of the sixth transistor is connected to the input stage and connected to a second node of the second transistor; a third node of the sixth transistor and a first node of the second current source, and a third node of the second transistor are connected to ground (gnd), both a second node and a first node of the fourth transistor are connected to the second node of the fifth transistor; a first node of the second transistor is connected to a first node of the third transistor and configured to output voltage (vo); a second node of the third transistor is connected to a connection point between the first node of the second current source and a first node of the seventh transistor; and both a first node and a second node of the fourth transistor are connected to both a second node of the fifth transistor and a first node of the sixth transistor.

A method in an operational amplifier, wherein the operational amplifier comprises an input stage; an output stage communicatively coupled to the input stage, wherein the output stage further comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a first current source, a fifth transistor, a sixth transistor and a second current source; wherein a second node of the first transistor is connected to the input stage (vin), a third node of the first transistor is connected to a third node of the fourth transistor, ground (gnd), a third node of the fifth transistor and a third node of the third transistor, a first node of the first transistor is connected to a first node of the first current source, second node of the sixth transistor and a second node of the second transistor; a third node of the sixth transistor and second node of the second current source, a second node of the first current source, and a third node of the second transistor are connected to a power supply (Vdd); a first node of the second transistor is connected to a first node of the third transistor and configured to output voltage (vo); a second node of the third transistor is connected to a connection point between a first node of the fifth transistor and a first node of the second current source; and both a first node and a second node of the fourth transistor are connected to both second node of the fifth transistor and a first node of the sixth transistor; wherein the method comprises receiving, by the input stage, input voltage; and outputting, by a connection point of the first node of the second transistor and the first node of the third transistor, the output voltage, wherein the third transistor is always on.

A method in an operational amplifier, wherein the operational amplifier comprises an input stage; an output stage communicatively coupled to the input stage, wherein the output stage comprises a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a second current source, a third node of the fifth transistor and a third node of the third transistor are connected to a power supply (Vdd), a second node of the sixth transistor is connected to the input stage and connected to a second node of the second transistor; a third node of the sixth transistor and a first node of the second current source, and a third node of the second transistor are connected to ground (gnd), both a second node and a first node of the fourth transistor are connected to the second node of the fifth transistor; a first node of the second transistor is connected to a first node of the third transistor and configured to output voltage (vo); a second node of the third transistor is connected to a connection point between the first node of the second current source and a first node of the fifth transistor; and both a first node and a second node of the fourth transistor are connected to both a second node of the fifth transistor and a first node of the sixth transistor; wherein the method comprises receiving, by the input stage, input voltage;

and outputting, by a connection point of the first node of the second transistor and the first node of the third transistor, the output voltage, wherein the second transistor is always on.

According to embodiments of the invention, the operational amplifier can be operated with lower operation voltage, such that the operational amplifier can be operated in more scenarios.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

FIG. 1is a circuit diagram illustrating an output stage of an operational amplifier100according an embodiment of the invention.

The operational amplifier100comprises an input stage Vin, and an output stage communicatively coupled to the input stage. The output stage comprises a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a first current source I1, a fifth transistor M5, a sixth transistor M6and a second current source I2.

A second node of the first transistor M1is connected to the input stage vin. A third node of the first transistor M1is connected to a third node of the fourth transistor M4, ground gnd, a third node of the fifth transistor M5and a third node of the third transistor M3. A first node of the first transistor M1is connected to a first node of the first current source I1, a second node of the sixth transistor M6and a second node of the second transistor M2. Note without loss of generality, a first node of a current source represents the side where an arrow is point to, that is, towards the direction the current flows to, while a second node of a current source represents the opposite side of the current flow, that is, where the current flows from.

A third node of the sixth transistor M6and second node of the second current source I2, a second node of the first current source I1, and a third node of the second transistor M2are connected to a power supply Vdd.

A first node of the second transistor M2is connected to a first node of the third transistor M3and configured to output voltage vo.

A second node of the third transistor M3is connected to a connection point between a first node of the fifth transistor M5and a first node of the second current source I2.

Both a first node and a second node of the fourth transistor M4are connected to both a second node of the fifth transistor M5and a first node of the sixth transistor M6.

FIG. 2shows another embodiment of the circuit diagram for the operational amplifier200. In addition to including all the circuit elements shown in the circuit100ofFIG. 1, the operational amplifier200further comprises a seventh transistor M7. The seventh transistor M7is connected in serial between the first node of fifth transistor M5and the first node of the second current source I2, and a connection point between the first node of the second current source I2and a second node of the seventh transistor M7is connected to a first node of the seventh transistor M7.

Referring toFIG. 2, wherein the first transistor M1, the third transistor M3, the fourth transistor M4, the fifth transistor M5and the seventh transistor M7are NMOS transistors. The second transistor M2and the sixth transistor M6are PMOS transistors.

Referring toFIG. 2, when the input circuit is in an equilibrium state, the current passing through the second transistor M2equals to the current passing through the third transistor M3. Further, a loop including the fifth transistor M5, the sixth transistor M6, the seventh transistor M7and the second current source I2determines a gate voltage of the third transistor M3. When vin rises, the voltage on the point N1decreases, therefore the current passing through the second transistor M2and the sixth transistor M6increases, therefore gate voltages of the fourth transistor M4and the fifth transistor M5rise, and gate voltage on the third transistor M3drops. When the current passing through the third transistor M3decreases to be a multiple times of the current of the second current source I2, the current passing through the third transistor M3will no longer decease (the multiplier is determined by the ratio of the third transistor M3and the seventh transistor M7). However, the current passing through the second transistor M2will continue to rise with the rise of vin, and the excess current is used to drive the external load.

When the voltage of input stage vin drops, the current passing through the second transistor M2and the sixth transistor M6begins to decrease. The gate voltages of the fourth transistor M4and the fifth transistor M5begin to drop, and the current passing through the fifth transistor M5decreases. Therefore the gate voltage of the third transistor M3rises, and the current passing through the third transistor M3starts to rise. The current passing through the second transistor M2begins to drop until the current passing through the second transistor M2reaches a multiple of the current of I2, which is determined by both the ratio of the sixth transistor M6and the second transistor M2and the ratio of the fourth transistor M4and the fifth transistor M5. Therefore the minimum operational voltage, that is vdd, can be higher than the larger one between the voltage between gate and source of the second transistor M2(Vgs2) and the voltage between gate and source of the third transistor M3(Vgs3). Note the lowest voltage on N1is 0, therefore vdd>vgs(m2). Meanwhile the maximum voltage on N2is Vdd, therefore , Vdd>vgs(M3). Therefore Vdd should be larger than the both vgs(M2) and Vgs (M3).

Referring back toFIG. 1, inFIG. 1, the circuit does not include the seventh transistor M7. When the voltage at a first node N1(VN1) decreases, the absolute value increases, and the current passing through the sixth transistor M6increases. As a result, the current passing through the fourth and fifth transistors M4and M5increase. Since the second current source I2maintains unchanged, the current IN2 passing through the second node N2, which corresponds a second node of the third transistor M3, may be 0. Therefore the voltage at the third node N3, which is the first node of the fifth transistor M5may be zero. Therefore the third transistor M3is off. In other words, in the operational amplifier100shown inFIG. 1, the third transistor M3may be on or off depending on the voltage of VN1, or input stage voltage vin. When vin increases, VN1 decreases, and when vin decreases, VN1 increases. On the other hand, the second transistor M2is always on no matter what is the input stage voltage vin. If the operational amplifier operates normally, M6is always on, therefore M2is always on. If M2is off then the circuit enters slew rate, and M2is finally on when in an equilibrium state. In other words, the operational voltage (vdd) may be higher than the Vgs of both the second transistor M2and the third transistor M3. Note if Vdd is lower than vgs(M3), then M3will not be on, and there is no pull down current. If the output stage drives ground resistor, then the circuit works. However if the output stage drives a power supply resistor, the circuit does not work because there is no pull down power. The operational amplifier100inFIG. 1may be a class AB type operational amplifier, or a class B type operational amplifier when the third transistor does not work.

In comparison toFIG. 1, the operational amplifier200inFIG. 2further comprises a seventh transistor M7. With the presence of the seventh transistor M7, there is always a current passing through the seventh transistor M7as long as there is a positive power supply voltage vdd. Therefore, there is always a current passing through the gate of the third transistor M3. In other words, in the operational amplifier200shown inFIG. 2, the third transistor M3is always on. Further, the second transistor M2is always on no matter what is the input stage voltage vin. The operational amplifier200inFIG. 2is a class AB type operational amplifier.

FIG. 3is a circuit diagram illustrating an operational amplifier300according an embodiment of the invention. The output stage is the same as that has already been discussed with respect toFIG. 2, therefore its details are omitted for the clarity of description. The input stage further comprises an eighth transistor M8, a ninth transistor M9, a tenth transistor M10and an eleventh transistor M11, and a third current source I3.

A second node of the eighth transistor M8is configured to receive a positive input voltage vinp. A second node of the ninth transistor M9is configured to receive a negative input voltage vinn. Both a third node of the eighth transistor M8and a third node of the ninth transistor M9are connected to a first node of the third current source I3. A second node of the third current source I3is connected to the power supply vdd.

A first node of the eighth transistor M8is connected to a first node of the tenth transistor M10. A first node of the ninth transistor M9is connected to a first node of the eleventh transistor M11. A second node of the ten transistor M10is connected to the second node of the eleventh transistor M11. Both a third node of the tenth transistor M10and a third node of the eleventh transistor M11are connected to ground.

The eighth transistor M8and the ninth transistor M9comprise PMOS, and the tenth transistor M10and the eleventh transistor M11comprise NMOS.

The first node of the eighth, ninth, tenth and eleventh M8, M9, M10and M11transistors comprises a drain. The second node of the eighth, ninth, tenth and eleventh M8, M9, M10and M11transistors each comprises a gate. The third node of the eighth, ninth, tenth and eleventh transistors M8, M9, M10and M11each comprises a source.

FIG. 4is a circuit diagram illustrating an operational amplifier400according an embodiment of the invention. The operational amplifier comprises an input stage vin; an output stage communicatively coupled to the input stage vin, wherein the output stage comprises a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6and a second current source I2.

A third node of the fifth transistor M5and a third node of the third transistor M3are connected to a power supply Vdd. A second node of the sixth transistor M6is connected to the input stage vin and connected to a second node of the second transistor M2.

A third node of the sixth transistor M6and a first node of the second current source I2, and a third node of the second transistor M2are connected to ground gnd. Both a second node and a first node of the fourth transistor M4are connected to the second node of the fifth transistor M5. A first node of the second transistor M2is connected to a first node of the third transistor M3and configured to output voltage vo. A second node of the third transistor M3is connected to a connection point between the first node of the second current source I2and a first node of the fifth transistor M5.

Both a first node and a second node of the fourth transistor M4are connected to both a second node of the fifth transistor and a first node of the sixth transistor M6.

Alternatively, the operational amplifier400further comprises a seventh transistor M7, which is shown in the dashed block which represents that the seventh transistor M7is optional. The seventh transistor M7is connected in serial between the first node of fifth transistor M5and the first node of the second current source I2. A connection point between the first node of the second current source I2and a second node of the seventh transistor M7is connected to a first node of the seventh transistor M7.

FIG. 5is a circuit diagram illustrating an operational amplifier500according another embodiment of the invention. The output stage is the same as that has already been discussed with respect toFIG. 4, therefore its details are omitted for the clarity of description. The operational amplifier500further comprises an input stage. The input stage comprises a tenth transistor M10, an eleventh transistor M11, an eighth transistor M8, a ninth transistor M9and a third current source I3.

A second node of the tenth transistor M10is configured to receive a positive voltage input vinp, and a second node of the eleventh transistor M11is configured to receive a negative voltage input vinn. A third node of the tenth transistor M10and a third node of the eleventh transistor M11are connected to a first node of the third current source13. A second node of the third current source13is connected to a power supply vdd, a first node of the eighth transistor M8and a second node of the eighth transistor M8are connected to a second node of the ninth transistor M9. Both a third node of the eighth transistor M8and a third node of the ninth transistor M9are connected to ground gnd.

Alternatively, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the seventh transistor M7, the tenth transistor M10and the eleventh transistor M11are PMOS transistors, and the second transistor M2, the sixth transistor M6, the eighth transistor M8and the ninth transistor M9are NMOS transistors.

FIG. 6is a flow chart diagram illustrating a method600in an operational amplifier according an embodiment of the invention. The operational amplifier comprises an input stage vin, and an output stage communicatively coupled to the input stage. The output stage comprises a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a first current source I1, a fifth transistor M5, a sixth transistor M6and a second current source I2. A second node of the first transistor M1is connected to the input stage vin. A third node of the first transistor M1is connected to a third node of the fourth transistor M4, ground gnd, a third node of the fifth transistor M5and a third node of the third transistor M3. A first node of the first transistor M1is connected to a first node of the first current source I1, a second node of the sixth transistor M6and a second node of the second transistor M2. A third node of the sixth transistor M6and second node of the second current source I2, a second node of the first current source I1, and a third node of the second transistor M2are connected to a power supply Vdd. A first node of the second transistor M2is connected to a first node of the third transistor M3and configured to output voltage vo. A second node of the third transistor M3is connected to a connection point between a first node of the fifth transistor M5and a first node of the second current source I2. Both a first node and a second node of the fourth transistor M4are connected to both a second node of the fifth transistor M5and a first node of the sixth transistor M6. The method600comprises receiving in block610, by the input stage, input voltage; and outputting in block620, by a connection point of the first node of the second transistor M2and the first node of the third transistor M3, the output voltage vo, wherein the second transistor M2is always on. Further, if the operational amplifier requires pull down power, vdd also should be larger than vgs(M3).

From the foregoing, it will be appreciated that specific embodiments of the technology have been described herein for purposes of illustration, however various modifications can be made without deviating from the spirit and scope of the present invention. Accordingly, the present invention is not restricted except in the spirit of the appended claims.

Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims the word “comprising” does not exclude other elements or steps, and the indefinite article “a” or “an” does not exclude a plurality. Even if particular features are recited in different dependent claims, the present invention also relates to the embodiments including all these features. Any reference signs in the claims should not be construed as limiting the scope.

Features and aspects of various embodiments may be integrated into other embodiments, and embodiments illustrated in this document may be implemented without all of the features or aspects illustrated or described. One skilled in the art will appreciate that although specific examples and embodiments of the system and methods have been described for purposes of illustration, various modifications can be made without deviating from the spirit and scope of the present invention. Moreover, features of one embodiment may be incorporated into other embodiments, even where those features are not described together in a single embodiment within the present document. Accordingly, the invention is described by the appended claims.