Ferroelectric nonvolatile code data output device

A ferroelectric nonvolatile code data output device comprises a code bus command processing unit, a code bus decoder unit, a function block unit, a code bus, a data buffer and a data selecting unit. The ferroelectric nonvolatile code data output device for outputting code data stored in a nonvolatile coding cell for the operation of a nonvolatile ferroelectric memory (hereinafter, referred to as “FeRAM”) to outside of chip through an input/output port to easily check corresponding data values.

BACKGROUND ART

1. Field of the Invention

The present invention generally relates to a data output device, and more specifically, to a ferroelectric nonvolatile code data output device for outputting code data stored in a nonvolatile coding cell for the operation of a nonvolatile ferroelectric memory (hereinafter, referred to as “FeRAM”) to outside of chip through an input/output port to easily check corresponding data values.

2. Description of the Prior Art

Generally, a ferroelectric memory device comprises nonvolatile coding cells in a function block such as a reconfiguration block or a redundancy block for storing various code data required in the operation of a chip.

However, it is necessary to output code data stored in the nonvolatile coding cells to the outside of the chip and to check the code data. That is, it is necessary to ascertain which coding cell data are currently stored in the reconfiguration block, whether the stored coding cell data are accurate or when the corresponding coding cell data are updated.

In case of the redundancy block, it is necessary to output the coding cell data stored in the redundancy block to the outside of the chip in order to ascertain what fail address data used in each redundancy coding block are or whether there is a redundancy block that is not used. Meanwhile, the existing fail address code data should be obtained to repair fail bits additionally generated in a burn-in-test. That is, the application of distinction results obtained by distinguishing the existing fail addresses from those newly generated to the redundancy algorithm can improve the redundancy efficiency.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to output code data stored in nonvolatile coding cells of each function block in a nonvolatile ferroelectric memory to the outside of a chip to check the code data.

In an embodiment, a ferroelectric nonvolatile code data output device comprises a code bus command processing unit, a code bus decoder unit, a function block unit, a code bus, a data buffer and a data selecting unit. The code bus command processing unit activates a decoder enable signal and a code selecting enable signal when a code data output command is applied. The code bus decoder unit selectively activates a selecting signal in response to a decoder input signal when the decoder enable signal is activated. The function block unit, which comprises a plurality of function blocks for storing nonvolatile code data required in an operation of a chip, outputs the code data in response to the selecting signal. The code bus, which is shared by the function blocks, transmits the code data applied by the function block unit. The data buffer temporarily stores data inputted and outputted through an input/output port. The data selecting unit selectively connects the data buffer to one of a data bus and the code bus which transmit data of a memory cell array in response to the code selecting enable signal.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1is a diagram illustrating a FeRAM chip where code data stored in a function block are outputted through an input/output port according to an embodiment of the present invention.

In an embodiment, a FeRAM chip includes various function blocks such as a reconfiguration block which frequently changes parameters. The corresponding parameters are outputted through an input/output (hereinafter, abbreviated as “I/O”) port where cell data are inputted and outputted in order to easily check parameters stored in such function blocks.

When various burn-in-tests are performed, new fail addresses are additionally generated therefrom. In order to repair the fail addresses, the existing fail address code data stored in the redundancy block should be checked.

As a result, the corresponding code data are outputted through an I/O port in order to easily check the fail address code data currently stored in the redundancy block according to an embodiment of the present invention.

FIG. 2is a diagram illustrating a code data input/output device according to an embodiment of the present invention.

In an embodiment, a code data I/O device comprises a code bus command processing unit100, a code bus decoder unit200, a function block unit300, a code bus400, a memory cell array unit500, a data bus600, a data selecting unit700, a data buffer800and an I/O port900.

When the code data output command for outputting code data through the I/O port900is applied, the code bus command processing unit100activates a decoder enable signal DEC_EN and a code selecting enable signal Code_MUX_EN to output the signals to the code bus decoder unit200and the data selecting unit700, respectively.

When a decoder enable signal DEC_EN is activated, the code bus decoder unit200selectively activates selecting signals SEL<1>˜SEL<n> in response to a decoder input signal, and controls the output operation of the code data of the function block unit300. When the decoder enable signal DEC_EN is activated, the code bus decoder unit200selectively activates one of the selecting signals SEL<1>˜SEL<n> corresponding to specific function blocks310and320of the function block unit300in response to the decoder input signal and outputs the activated signal to the corresponding function block. The code bus decoder unit200comprises a plurality of code bus decoders210and220which correspond one by one to the functions blocks310and320. The code bus decoders210and220selectively activates the selecting signals SEL<1>˜SEL<n> to output the activated signals to the corresponding function blocks310and320in response to the decoder input signal.

The function block unit300stores nonvolatile code data required in the operation of the chip in nonvolatile coding cells, and applies the code data to the code bus400in response to the selecting signals SEL<1>˜SEL<n>. The function block unit300comprises a plurality of the function blocks310and320which correspond one by one to a plurality of code bus decoders210and220and store different kinds of code data. Each of the function blocks310and320comprises a plurality of unit code bus driving units (n) for storing the code data and applying the code data to the code bus400in response to the selecting signals SEL<1>˜SEL<n>.

The code bus400connects the block unit300and the data selecting unit700so that the code bus400is shared by the function blocks310and320in the chip, and transmits the applied code data to the data selecting unit700in response to the selecting signals SEL<1>˜SEL<n>.

The memory cell array unit500stores write data applied externally through the I/O port900, and senses and amplifies the stored data to output the data to the data bus600.

The data bus600which connects the memory cell array unit500to the data selecting unit700transmits write data to the memory cell array unit500and data sensed in the memory cell array unit500to the data selecting unit700.

The data selecting unit700selectively changes a data path in response to the code selecting enable signal Code_MUX_EN to connect the data buffer800to one of the code bus400and the data bus600. That is, the data selecting unit700connects the code bus400to the data buffer800when the code selecting enable signal Code_MUX_EN is activated, and connects the data bus600to the data buffer800to exchange data when the code selecting enable signal Code_MUX_EN is inactivated.

The data buffer800temporarily stores data inputted and outputted through the I/O port900.

FIG. 3is a circuit diagram illustrating a code bus decoder ofFIG. 2.

When the decoder enable signal DEC_EN is activated, the code bus decoders210and220selectively activate one of the selecting signals SEL<1>˜SEL<n> in response to decoder input signals IN<1>˜IN<2n> to output the activated signals to the corresponding function blocks310and320. Each of the code bus decoders210and220comprises a plurality of AND gates AND1˜ANDn each for performing an AND operation on the decoder enable signal DEC_EN and the decoder input signals IN<1>, IN<2>˜IN<2n-1>, IN<2n> to selectively activate the selecting signals SEL<1>˜SEL<n>.

FIG. 4is a diagram illustrating a function block ofFIG. 2.

The function block310as a redundancy block for storing redundancy code data comprises a plurality of unit code bus driving units310_1˜310—nwhich share the code bus400. Each of unit code bus driving units310_1˜310—ncomprises a plurality (m) of nonvolatile coding cells for storing code data COD<1>˜COD<m> each having m bits and for regulating a voltage level of the code bus400in response to the code data COD<1>˜COD<m> stored when the selecting signals SEL<1>˜SEL<n> are activated, thereby inducing code data to the code bus400.

Each of the unit code bus driving units310_1˜310—ncomprises m nonvolatile coding cells, which includes code block unit312_1˜312—nfor storing code data of m bits and code bus output units314_1˜314—nthat are connected to the code bus400to induce the code data COD<1>˜COD<m> to code bus400, respectively, in response to the selecting signals SEL<1>˜SEL<n>.

FIG. 5is a diagram illustrating a unit code bus driving unit ofFIG. 4.

The code block unit312—ncomprises a plurality (m) of nonvolatile coding cells312—n1˜312—nmfor storing the nonvolatile code data COD<1>˜COD<m>.

The code bus output unit314—ncomprises a plurality of coding drivers314—n1˜314—nmwhich correspond one by one to the coding cells312—n1˜312—nmand code bus lines CBL<1>˜CBL<m>. The plurality of coding drivers314—n1˜314—nmchange voltage levels of the code bus lines CBL<1>˜CBL<m> in response to the code data COD<1>˜COD<m> of the coding cells312—n1˜312—nmwhen the corresponding selecting signal SEL<n> is activated.

FIG. 6is a circuit diagram illustrating a nonvolatile coding cell312—nmofFIG. 5.

The nonvolatile coding cell312—nmcomprises a pull-up switch P1, a pull-up driving unit315, a data I/O unit316, a ferroelectric capacitor unit317, a pull-down driving unit318and a pull-down switch N5.

The pull-up switch P1is a PMOS transistor which is connected between a power voltage VCC terminal and the pull-up driving unit315and has a gate to receive a pull-up enable signal ENP. The pull-up switch P1applies a power voltage VCC to the pull-up driving unit315when the pull-up enable signal ENP is activated.

The pull-up driving unit315drives the power voltage VCC applied from the pull-up switch P1. The pull-up driving unit315comprises PMOS transistors P2and P3which are connected with a latch type between the pull-up switch P1and the data I/O unit316.

The data I/O unit316inputs and outputs the code data COD<m> and/COD<m> in response to a write enable signal ENW. The data I/O unit316comprises NMOS transistors N1and N2which are connected between both data storage nodes of the coding cell312—nmand both output terminals/COD<m> and COD<m>, respectively. A write enable signal ENW is applied to gates of the NMOS transistors N1and N2.

The ferroelectric capacitor unit317generates a voltage difference in both data storage nodes in response to a cell plate signal CPL to store the code data COD<m> and/COD<m> applied through the data I/O unit316.

The pull-down driving unit318drives a ground voltage VSS applied from the pull-down switch N5. The pull-down driving unit318comprises NMOS transistors N3and N4which are connected with a latch type between the ferroelectric capacitor unit317and the pull-down switch N5.

The pull-down switch N5is a NMOS transistor which is connected between the pull-down driving unit318and the ground voltage VSS terminal and has a gate to receive a pull-down enable signal ENN. When the pull-down enable signal ENN is activated, the pull-down switch N5applies the ground voltage VSS to the pull-down driving unit318.

The cell plate signal CPL is transited to ‘high’ by a power-up detection pulse generated when power reaches a stabilized level. Charges stored in ferroelectric capacitors FC1and FC2generate a voltage difference in both data storage nodes by capacitance load of the ferroelectric capacitors FC3and FC4when the cell plate signal CPL is applied as ‘high’. When a sufficient voltage difference is generated in both storage nodes of the coding cell, the pull-up enable signal ENP and the pull-down enable signal ENN are activated to ‘low’ and ‘high’, respectively, to amplify data of both output terminals. When the amplification is completed, the cell plate signal CPL is transited to ‘low’, so that destroyed high data of the ferroelectric capacitor FC1or FC2is restored.

FIG. 7is a diagram illustrating a code bus output unit314—nofFIG. 5.

The coding drivers314—n1˜314—nmcomprise NMOS transistors N6, N7˜N10, N11which are connected serially between the ground voltage VSS terminal and the code bus lines CBL<1>˜CBL<m> and have gates to receive the corresponding code data COD<1>˜COD<m> and the selecting signal SEL<n>. In other words, when the selecting signal SEL<n> is activated, the NMOS transistors N7, N9and N11are turned on, so that signal levels of the corresponding code bus lines CBL<1>˜CBL<m> are determined in response to the code data COD<1>˜COD<m>.

FIG. 8is a timing diagram illustrating the operation of the code driver (314—nm) ofFIG. 7.

At the initial stage of the operation, the code bus line CBL<m> is precharged to a high level. When the decoder enable signal DEC_EN is activated, the code bus decoder unit200activates the selecting signal SEL<n>. When the NMOS transistor N11is turned on by activation of the selecting signal SEL<n>, a voltage level of the code bus line CBL<m> precharged to the high level is determined depending on that of the corresponding code data COD<m>. That is, when the code data COD<m> is ‘high’, the NMOS transistor N10is turned on, so that the code bus line CBL<m> is pulled down to the ground voltage VSS. However, when the code data COD<m> is ‘low’, the NMOS transistor N10is turned off, so that the code bus line CBL<m> is kept at the high level.

When the code bus command processing unit100is activated to check code data of the specific function block, the code bus command processing unit100activates the decoder enable signal DEC_EN and the code selecting enable signal Code_MUX_En to ‘high’.

When the code selecting enable signal Code_MUX_EN is activated, the data selecting unit700changes the data path for connecting the data bus600to the data buffer800into one for connecting the code bus400to the data buffer800.

When the decoder enable signal DEC_EN is activated, the code bus decoders210and220selectively activate one of the selecting signals SEL<1>˜SEL<n> corresponding to the specific function blocks310and320in response to the decoder input signals IN<1>˜IN<2n>. That is, the code bus decoder unit200controls the code data COD<1>˜COD<m>stored in the different function blocks210and220so that they may not be simultaneously applied to the code bus400.

When the selecting signals SEL<1>˜SEL<n> are activated, the voltage level of the code bus400is changed by the code data COD<1>˜COD<m> as shown inFIG. 8to be applied to the code bus400.

The code data COD<1>˜COD<m> applied to the code bus400are outputted to the I/O port900through the data buffer800by the path change of the data selecting unit700.

As described above, a ferroelectric nonvolatile code data output device according to an embodiment of the present invention outputs code data stored in nonvolatile coding cells of each function block to the outside of a chip through an I/O port for the operation of the chip, thereby improving the efficiency of the chip.

While the invention is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and described in detail herein. However, it should be understood that the invention is not limited to the particular forms disclosed. Rather, the invention covers all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined in the appended claims.