Integrated circuit package assemblies including a glass solder mask layer

Embodiments of the present disclosure are directed towards techniques and configurations for integrated circuit package assemblies including a glass solder mask layer and/or bridge. In one embodiment, an apparatus includes one or more build-up layers having electrical routing features and a solder mask layer composed of a glass material, the solder mask layer being coupled with the one or more build-up layers and having openings disposed in the solder mask layer to allow coupling of package-level interconnect structures with the electrical routing features through the one or more openings. Other embodiments may be described and/or claimed.

FIELD

Embodiments of the present disclosure generally relate to the field of integrated circuits, and more particularly, to techniques and configurations for integrated circuit package assemblies including a glass solder mask layer.

BACKGROUND

Currently, integrated circuit (IC) package assemblies may include a solder mask layer composed of polymer as an outermost layer of a package substrate to facilitate formation of second-level or “package-level” interconnects. However, present polymer-based solder mask layers may be associated with higher loss and/or cross-talk resulting in lower power efficiency for electrical signals routed through the second-level interconnects. Cleaning of build-up layers of the package substrate may be difficult in current processes that utilize a polymer-based solder mask layer. Additionally, forming openings in the polymer-based solder mask layer may be costly.

Emerging IC package assemblies may further include a bridge configured to route electrical signals between dies mounted on the IC package assembly. Current techniques to align and/or couple the bridge with the IC package assembly may be costly or may not be capable of fabricating fine line and space and provide high input/output (I/O) count between dies or may be otherwise challenging owing to constraints in temporary position alignment technology and/or differences in coefficient of thermal expansion (CTE) between the bridge and other materials of the IC package assembly.

DETAILED DESCRIPTION

In various embodiments, the phrase “a first feature formed, deposited, or otherwise disposed on a second feature,” may mean that the first feature is formed, deposited, or disposed over the second feature, and at least a part of the first feature may be in direct contact (e.g., direct physical and/or electrical contact) or indirect contact (e.g., having one or more other features between the first feature and the second feature) with at least a part of the second feature.

FIG. 1schematically illustrates a cross-section side view of an example integrated circuit (IC) package assembly100, in accordance with some embodiments. In some embodiments, the IC package assembly100may include a package substrate104coupled with one or more dies (e.g., dies102a,102band102c) and circuit board122, as can be seen. In various embodiments, the IC package assembly100may refer to only the package substrate104.

In some embodiments, the dies102a,102bmay be mounted on or attached to the package substrate104according to a wide variety of suitable configurations including, for example, being directly coupled with the package substrate104in a flip-chip configuration, as depicted. In the flip-chip configuration, an active side of the dies102a,102bis attached to a surface of the package substrate104using die interconnect structures106such as bumps, pillars, bonding pads or other suitable structures that may also electrically couple the dies102a,102bwith the package substrate104. The active side of the dies102a,102band102cmay include a plurality of active integrated circuit (IC) devices such as, for example, transistor devices. In some embodiments, the dies102a,102bare configured in a side-by-side arrangement on the package substrate104, as can be seen.

In some embodiments, a die102cmay be coupled with die102ain a stacked flip-chip configuration, as can be seen. The die102amay include one or more through-silicon vias (TSVs)101that are configured to route electrical signals of the die102cbetween the die102cand the package substrate104through the die102a. Electrical signals of the dies102a,102band102cmay be routed between the dies102a,102band102cand the package substrate104through the die interconnect structures106. In some embodiments, the electrical signals include input/output (I/O) signals and/or power/ground associated with operation of the dies102a,102band102c. Each of the dies102a,102band102cmay represent a discrete unit made from a semiconductor material using semiconductor fabrication techniques such as thin film deposition, lithography, etching and the like. In some embodiments, the dies102a,102band102cmay be, include, or be a part of a processor, memory, system on chip (SoC) or ASIC in some embodiments. In one embodiment, the die102ais a processor and at least one of dies102bor102cis memory. The dies102a,102band102cmay be configured to serve other functions in other embodiments.

In some embodiments, an electrically insulative material107such as, for example, molding compound or underfill material (not shown) may encapsulate at least a portion of one or more of the dies102a,102band102c. In the depicted example ofFIG. 1, the die102ais partially encapsulated by the electrically insulative material107, the die102bis fully encapsulated by the electrically insulative material107and the die102cis not encapsulated (e.g., in direct contact with) by the electrically insulative material107at all. The IC package assembly100may include other suitable configurations of the electrically insulative material107in other embodiments.

In some embodiments, the electrically insulative material107may include an underfill material between the dies102a,102band102cand the package substrate104and a molding compound disposed on inactive surfaces of the dies102a,102band102c. In other embodiments, the electrically insulative material107may include a molding underfill material that is disposed between the dies102a,102band102cand the package substrate104and on inactive surfaces of the dies102a,102band102c. The electrically insulative material107may include, for example, epoxy-based materials including suitable filler materials.

The package substrate104may include one or more build-up layers (hereinafter “build-up layers103”) having electrical routing features103adisposed in an electrically insulative material103bor dielectric material. Although three build-up layers103are depicted in the example ofFIG. 1, the package substrate104may include more or fewer build-up layers in other embodiments. In some embodiments, the build-up layers may include bumpless build-up layers.

The electrical routing features103amay include metal (e.g., copper) structures such as, for example, traces, trenches, vias, lands, pads or other structures that provide corresponding electrical pathways for electrical signals of the dies102a,102band102cthrough the package substrate104(e.g., from side S2to side S1). In some embodiments, the electrical pathways may be arranged in a fanout configuration.

In some embodiments, the package substrate104is an epoxy-based laminate substrate having a core and/or build-up layers such as, for example, an Ajinomoto Build-up Film (ABF) substrate. The electrically insulative material103bmay be an organic material in some embodiments. The package substrate104may include other suitable types of substrates or materials in other embodiments.

According to various embodiments, the package substrate104includes a solder mask layer105composed of a glass material. In some embodiments, the solder mask layer105is disposed on side S1of the build-up layers103, which is disposed opposite to side S2of the build-up layers103as can be seen. The glass material of the solder mask layer105may include, for example, silica, quartz, nano fiber enhanced glass/organic or other similar glass materials. In some embodiments, the solder mask layer105has a thickness of the glass material ranging from 15 to 50 microns in a direction (e.g., up and down inFIG. 1) that is substantially perpendicular to a plane formed by the solder mask layer105. The glass material may include other suitable materials or thicknesses in other embodiments.

The glass material of the solder mask layer105may be optically transparent at a wavelength of light within the visible spectrum (e.g., from 390 nanometers (nm) to 700 nm) to facilitate alignment of the package substrate104during formation of the package-level interconnect structures112or attachment of the package substrate104with another electrical component (e.g., circuit board122). In some embodiments, alignment feature(s) such as, for example, the electrical routing features103a(e.g., a via pit), may be visible on a side S1of the one or more build-up layers103through the solder mask layer105. A camera can be used to capture one or more images of the alignment feature(s) to facilitate alignment of the package substrate104for assembly processing.

In some embodiments, the glass material of the solder mask layer105may have a coefficient of thermal expansion (CTE) from 1 to 10. In one embodiments, the CTE of the glass material is from 3 to 7. In embodiments where the dies102a,102band102care composed of silicon (Si) or other material having a CTE that is closely matched with the CTE of the glass material, the CTE of the solder mask layer105may be more closely matched to the CTE of the dies102a,102band102cthan a solder mask layer composed of polymer material, which may reduce warpage or other thermal processing defects of the IC package assembly100. In some embodiments, a CTE of the solder mask layer105may be selected to match a CTE of other components of the package substrate104such as, for example, electrically insulative material107or build-up layers103to mitigate thermal warpage effects.

In some embodiments, the solder mask layer105includes one or more openings (e.g., opening109) that allow coupling of package-level interconnect structures112(e.g., solder balls113) with the electrical routing features103athrough the openings. The openings may have a diameter (e.g., a critical dimension (CD)) that is about 200 microns (e.g., ranging from 100 microns to 300 microns) in some embodiments. A pitch between at least two individual openings of the one or more openings may be less than or equal to 400 microns. The pitch may be uniform between adjacent openings in some embodiments. Other values for diameter, CD or pitch can be used in other embodiments.

Using glass material for the solder mask layer105may be less costly to fabricate than using polymer material for the solder mask layer. The glass material may reduce a moisture update (e.g., provide greater barrier to undesirable moisture in the package substrate104) of the package substrate104relative to a polymer solder mask layer. Additionally, the glass material of the solder mask layer105may reduce loss or cross-talk of the electrical signals relative to a solder mask layer composed of polymer material and, thus, increase power efficiency for the electrical signals in the IC package assembly100.

The solder mask layer105may be an outermost layer of the package substrate104that is configured to protect the build-up layers103and facilitate formation of the package-level interconnect structures112to couple the package substrate with other electrical components such as, for example, circuit board122.

In some embodiments, the package substrate104may further include a bridge interconnect structure (hereinafter “bridge108”) electrically coupled with the dies102aand102bthrough die interconnect structures106and configured to route electrical signals between dies102aand102b. The bridge108may be composed of glass or a semiconductor material (e.g., Si) and include electrical routing features (not shown) to route the electrical signals. The bridge108may be disposed in or within a plane formed by the build-up layers103. For example, as can be seen in the depicted embodiment, the bridge108is embedded in the build-up layers103. In other embodiments, the bridge108may be disposed in a plane formed by the build-up layers103, but formed separately from the build-up layers103, as can be seen for example inFIG. 3g. In some embodiments, the package substrate104may not include a bridge108at all. In other embodiments, the package substrate104may include the bridge108and a solder mask layer composed of a polymer material.

The IC package assembly100may further include package-level interconnect structures112(e.g., second-level interconnects) coupled with the package substrate104through the openings (e.g., opening109) in the solder mask layer105. In some embodiments, the package-level interconnect structures112include ball-grid array (BGA) structures such as, for example, solder balls113. In other embodiments, the package-level interconnect structures112include land-grid array (LGA) structures (e.g., LGA structures213ofFIG. 2g). The package-level interconnect structures112may include other suitable interconnect structures in other embodiments.

The package substrate104may be coupled with a circuit board122in some embodiments. The package-level interconnect structures112may be coupled with one or more pads110or analogous structures of the circuit board122to route electrical signals of the dies102a,102band102cbetween the package substrate104and the circuit board122. The pads110may be composed of any suitable electrically conductive material such as metal including, for example, nickel (Ni), palladium (Pd), gold (Au), silver (Ag), copper (Cu), and combinations thereof. Other suitable techniques to physically and/or electrically couple the package substrate104with the circuit board122may be used in other embodiments.

The circuit board122may be a printed circuit board (PCB) composed of an electrically insulative material such as an epoxy laminate. For example, the circuit board122may include electrically insulating layers composed of materials such as, for example, polytetrafluoroethylene, phenolic cotton paper materials such as Flame Retardant 4 (FR-4), FR-1, cotton paper and epoxy materials such as CEM-1 or CEM-3, or woven glass materials that are laminated together using an epoxy resin prepreg material. Structures (not shown) such as traces, trenches, vias, etc. may be formed through the electrically insulating layers to route the electrical signals of the dies102a,102band102cthrough the circuit board122. The circuit board122may be composed of other suitable materials in other embodiments. In some embodiments, the circuit board122is a motherboard (e.g., motherboard602ofFIG. 6).

The IC package assembly100may include components configured in a wide variety of other suitable configurations in other embodiments including, for example, suitable combinations of flip-chip and/or wire-bonding configurations, use of interposers, multi-chip package configurations including system-in-package (SiP) and/or package-on-package (PoP) configurations to route electrical signals between the dies102a,102band102cand other components of the IC package assembly100in some embodiments.

FIGS. 2a-gschematically illustrate various stages of fabrication of an example IC package assembly200including a solder mask layer105composed of a glass material, in accordance with some embodiments. The IC package assembly200may be fabricated using the solder mask layer105as a substrate for fabrication of the build-up layers103on the solder mask layer105.

FIG. 2adepicts the IC package assembly subsequent to coupling the solder mask layer105with a temporary carrier and forming build-up layers103on the solder mask layer105, which serves as a substrate (e.g., core layer) during formation of the build-up layers103. In some embodiments, the solder mask layer105includes a sheet of glass that is bonded to a temporary carrier216using adhesive layer214.

Subsequent to coupling the solder mask layer105with the temporary carrier216, build-up layers103may be formed on the solder mask layer105using any suitable process. For example, the build-up layers103may be formed by depositing a metal, roughening a surface of the metal, depositing a seed layer, depositing photoresist on the seed layer, patterning the photoresist (e.g., using lithography) to provide designated circuitry (e.g., electrical routing features103a) of the metal layer, depositing metal on the seed layer by electroplating process, removing the photoresist, etching the seed layer and depositing a dielectric material (e.g., electrically insulative material103b) on the patterned metal layer (e.g., by spin-on, chemical vapor deposition (CVD) or laminate processes. The build-up layers103may be formed using other techniques in other embodiments.

The temporary carrier216may include any suitable material to structurally support the fabrication of the build-up layers103on the solder mask layer105. In some embodiments, the material of the temporary carrier216is selected to have a CTE that matches a CTE of components of the IC package assembly200such as, for example, the solder mask layer105, the build-up layers103, the dies (e.g., dies102a,102bofFIG. 2c) and/or electrically insulative material (e.g., electrically insulative material107ofFIG. 2e) to reduce or mitigate warpage effects.

The material of the adhesive layer214may include any suitable adhesive configured to withstand processes associated with fabrication of the build-up layers103. For example, in an embodiment where a thermal process is used to cure the electrically insulative material103bof the build-up layers103, the material of the adhesive layer214may be selected such that the material of the adhesive layer214does not interfere with curing of the build-up layers103. In some embodiments, openings217may be formed in the electrically insulative material103busing any suitable technique to expose portions of the electrical routing features103a, thereby allowing die attachment to the electrical routing features103a.

FIG. 2bdepicts the IC package assembly200subsequent to forming die interconnect structures106electrically coupled with the electrical routing features103a. The die interconnect structures106may include, for example, bumps or pillars formed in the openings217ofFIG. 2ain some embodiments. In other embodiments, the die interconnect structures106may be coupled with one or more dies prior to attaching the die(s) to the package substrate104.

FIG. 2cdepicts the IC package assembly200subsequent to attaching dies102aand102bto the package substrate104using the die interconnect structures106. In some embodiments, the dies102aand102bmay be attached to the package substrate104using a reflow process to form joints of solderable material between the dies102a,102band the package substrate104. A single reflow process may be used to simultaneously couple the dies102a,102bwith the package substrate104in some embodiments. In other embodiments, a thermocompression bonding (TCB) technique may be used to attach the dies102a,102bto the package substrate104. The package substrate104may be bonded with the dies102a,102busing a panel-level bonding process (e.g., for higher throughput) or wafer-level bonding process, according to various embodiments.

FIG. 2ddepicts the IC package assembly200subsequent to depositing an electrically insulative material107(e.g., molding compound or underfill material) to at least partially encapsulate one or more dies102aand102b. In the depicted embodiment, the deposited electrically insulative material107fully encapsulates both dies102aand102b.

FIG. 2edepicts the IC package assembly200subsequent to decoupling the temporary carrier216and the package substrate104. In some embodiments, decoupling the temporary carrier216may be performed by using a thermal process to provide a temperature that causes the adhesive layer214to lose tackiness. For example, the adhesive layer214may be elevated to a temperature above a glass transition (Tg) temperature of the adhesive layer214and the IC package assembly200may slide off the temporary carrier. Any residual material from the adhesive layer214or previous assembly processing may be removed by a cleaning process performed on exposed surfaces of the solder mask layer105. Other suitable mechanisms or techniques to decouple the temporary carrier216and the solder mask layer105may be used in other embodiments.

FIG. 2fdepicts the IC package assembly200subsequent to forming openings (e.g., opening109) in the solder mask layer and forming BGA structures (e.g., solder balls113) in the openings. The openings may be formed by any suitable technique including, for example, a wet etch process that is configured to remove the glass material and is selective to the material (e.g., copper) of the underlying electrical routing features103a.

FIG. 2gdepicts an alternative toFIG. 2f. InFIG. 2g, the IC package assembly200is depicted subsequent to forming openings similar toFIG. 2fand after forming LGA structures213in the openings. The LGA structures213may be formed by depositing material into the openings to fill the vias and depositing and/or patterning additional material on the filled vias to form the LGA structures213. Other suitable techniques may be used to form the BGA or LGA structures.

In some embodiments, the fabrication of the IC package assembly200may further include forming a bridge (e.g., bridge108ofFIG. 1) disposed in a plane of the build-up layers103. The bridge may be formed, for example, by embedding the bridge in build-up layers103(e.g., a final build-up layer) as part of the formation of the build-up layers103or forming a cavity in the build-up layers103and placing bridge in the cavity subsequent to formation of the build-up layers, according to any suitable technique. The bridge may be formed during fabrication described in connection withFIG. 2aprior to attaching the die interconnect structures106or dies102a,102b.

FIGS. 3a-hschematically illustrate various stages of fabrication of an example IC package assembly300including a bridge (e.g., bridge108ofFIG. 1), in accordance with some embodiments. The IC package assembly300may be fabricated by attaching dies to a die attach film, molding the dies and using the molding compound, dies and die attach film as a substrate for fabrication of build-up layers and the bridge.

FIG. 3adepicts the IC package assembly300subsequent to coupling a die attach film303with a temporary carrier216using adhesive layer214. In some embodiments, the die attach film303may be composed of an uncured or not fully cured polymer material including, for example, an epoxy-based material with filler. In some embodiments, the die attach film303may be composed of an organic laminate material. In one embodiment, the die attach film303is composed of a same or similar material as build-up layers (e.g., build-up layers103ofFIG. 1 or 3f). The adhesive layer may be thermally and/or mechanically releasable according to various embodiments.

FIG. 3bdepicts the IC package assembly300subsequent to placing dies102a,102bon the die attach film303and curing the die attach film303. In some embodiments, die interconnect structures106are formed on the dies102a,102bprior to placing the dies102a,102bon the die attach film303. Curing the die attach film303may increase adhesion between the dies102a,102band the die attach film303. A shortest distance between the dies102a,102bmay range from 50 microns to 100 microns in some embodiments. The shortest distance between the dies102a,102bmay have other values in other embodiments.

In some embodiments, the die attach film303may be composed of anisotropically conductive material such as, for example, electrical ACF (anisotropic conductive film) with a conductive filler phase to provide an anistropic conductive film. In embodiments, the anisotropic conductive film may be used to route electrical signals through the die attach film303(e.g., to/from dies102a,102b) instead of die interconnect structures106.

FIG. 3cdepicts the IC package assembly300subsequent to depositing an electrically insulative material107(e.g., molding compound) on the dies102a,102band the die attach film303, as can be seen. In some embodiments, the electrically insulative material107is deposited to fully encapsulate the dies102a,102bas depicted. In other embodiments, the electrically insulative material107is deposited to partially encapsulate the dies102a,102b(e.g., leaving an inactive side of the dies exposed).

FIG. 3ddepicts the IC package assembly300subsequent to decoupling the die attach film303from the temporary carrier216. The IC package assembly300may be flipped (e.g., oriented about 180 degrees relative to a position of the IC package assembly300during processing ofFIGS. 3a-c) and cleaned. For example, the die attach film303may be cleaned to remove residue of the adhesive layer214or other contaminants associated with assembly process.

FIG. 3edepicts the IC package assembly300subsequent to recessing the die attach film303to expose the die interconnect structures106. The die attach film303may be recessed by grinding or planarizing process such as, for example, chemical-mechanical polish (CMP). Other suitable techniques to recess the die attach film303may be used in other embodiments.

FIG. 3fdepicts the IC package assembly300subsequent to coupling a bridge108with the dies102a,102b, forming build-up layers103on the die attach film303to form a package substrate104with electrical routing features103athrough electrically insulative material103band forming package-level interconnect structures (e.g., solder balls113) on the build-up layers103. The bridge108may be attached to die interconnect structures106(e.g., by TCB, conductive underfill or reflow process) and a laminate layer of electrically insulative material103bmay be deposited on the bridge108and patterned to allow formation of electrical routing features103athrough the electrically insulative material103b. For example, metal may be deposited in the patterned laminate layer to provide a first build-up layer of the build-up layers103. Multiple layers of laminate material and/or metal may be deposited to form multiple build-up layers of the build-up layers103.

In the depicted embodiment, the die attach film303serves as a substrate upon which the build-up layers103are formed. As previously described, the die attach film303may be a same material as the electrically insulative material103b. In this regard, the die attach film303may be considered to be part of the build-up layers103of the package substrate104in some embodiments. In an embodiment where the die attach film303is an anisotropic conductive film, the bridge108may be directly coupled with the anisotropic conductive film and use the anisotropic conductive film to provide an electrical pathway between the bridge108and dies102a,102b(e.g., without using die interconnect structures106).

The bridge108may be embedded in the build-up layers103and configured to route electrical signals between the dies102a,102b. The electrical routing features103amay be configured to route electrical signals between the dies102a,102band package-level interconnect structures (e.g., solder balls113) disposed on side S1of the build-up layers103. In some embodiments, the electrical routing features103aare arranged in a fanout configuration.

According to various embodiments, a thinner bridge108or thicker build-up layer may facilitate embedding of the bridge108according toFIG. 3f. For example, a bridge108having a thickness less than or equal to 45 microns may be embedded in the build-up layers103. The bridge108may be embedded and have other thicknesses in other embodiments.

FIG. 3gdepicts an alternative arrangement to the IC package assembly300ofFIG. 3f. InFIG. 3g, the IC package assembly300is depicted subsequent to forming build-up layers103on the die attach film303, coupling a bridge108with the dies102a,102b, and forming package-level interconnect structures (e.g., solder balls113) on the build-up layers103. In embodiments according toFIG. 3g, the bridge108may be coupled with the dies102a,102bsubsequent to forming the build-up layers103on the die attach film303. In some embodiments, the bridge108may be coupled with the dies102a,102bprior to or subsequent to coupling the package-level interconnect structures with the package substrate104.

For example, in one embodiment, an opening may be left open during fabrication of the build-up layers103to provide a cavity for placement/coupling of the bridge108with the dies102a,102b. In other embodiments, an opening may be formed through the build-up layers103using a patterning process. For example, the build-up layers103may be composed of a photosensitive material that is amenable to masking, patterning and etch. In other embodiments, the build-up layers103may be patterned using a sacrificial layer or materials that are removed by exposure to heat or chemicals.

According to various embodiments, providing a cavity for attachment of the bridge108may be performed for an IC package assembly300that has a thicker bridge108or thinner build-up layer relative to the IC package assembly300ofFIG. 3f.

FIG. 3hdepicts the IC package assembly300ofFIG. 3gsubsequent to planarizing the electrically insulative material107to expose a surface of the dies102a,102b, as can be seen. The electrically insulative material107may be planarized using, for example, a CMP process. The exposed dies102a,102bmay facilitate heat transfer away from the dies102a,102bin some embodiments. A similar technique may be used to expose the dies102a,102bof other package configurations described herein including, for example, the IC package assembly300ofFIG. 3f.

In some embodiments, the fabrication of the IC package assembly300may further include forming a solder mask layer (e.g., solder mask layer105ofFIG. 1) composed of a glass material. The solder mask layer may be formed, for example, by coupling a thin sheet of glass to an outermost build-up layer of the build-up layers103(e.g., side S1of the build-up layers103) and forming openings (e.g., opening109ofFIG. 1). The solder mask layer may be formed prior to or subsequent to coupling the bridge108with the dies102a,102b, according to various embodiments. In some embodiments (e.g., IC package configuration300ofFIG. 3f), the solder mask layer may be formed subsequent to coupling the bridge108with the dies102a,102band forming the build-up layers103and prior to coupling the package-level interconnect structures (e.g., solder balls113). In other embodiments (e.g., IC package configuration300ofFIG. 3g), the solder mask layer may be formed prior to coupling the bridge108with the dies102a,102band coupling the package-level interconnect structures and subsequent to forming the build-up layers103.

FIG. 4schematically illustrates a flow diagram for a method400of fabricating an IC package assembly (e.g., IC package assembly200ofFIGS. 2a-g) including a solder mask layer (e.g., solder mask layer105ofFIGS. 2a-g). The method may comport with embodiments described in connection withFIGS. 2a-gaccording to various embodiments.

At402, the method400may include providing a substrate composed of a glass material. The substrate may, for example, include a sheet of glass that is configured to serve as a solder mask layer (e.g., solder mask layer105ofFIG. 2a) of a package substrate (e.g., package substrate104ofFIG. 2a).

At404, the method400may include forming one or more build-up layers (e.g., build-up layers103ofFIG. 2a) on the substrate. The build-up layer(s) may include electrical routing features (e.g., electrical routing features103a) disposed in electrically insulative material (e.g., electrically insulative material103b). In some embodiments, the build-up layers are formed by depositing a metal on the substrate, patterning the metal to define one or more of the electrical routing features and depositing a laminate material on the patterned metal. The build-up layers may be formed according to techniques described in connection withFIG. 2aor other well-known techniques.

At406, the method400may include forming openings (e.g., opening109ofFIG. 2f) through the substrate to form a solder mask layer on a first side (e.g., side S1ofFIG. 2for2g) of the build-up layer(s). In some embodiments, forming the openings includes performing a wet etch process to remove portions of the glass material. The openings may be formed according to techniques described in connection withFIG. 2f. The openings may allow coupling of one or more package-level interconnect structures (e.g., solder balls113) with the electrical routing features in the build-up layer(s) through the openings.

At408, the method400may include attaching one or more dies (e.g., dies102a,102bofFIG. 2c) to a second side (e.g., side S2ofFIG. 2c) of the build-up layers opposite to the first side. In some embodiments, attaching the die(s) forms an electrical connection between the die(s) and the electrical routing features of the buildup layer(s). The dies may be attached according to techniques described in connection withFIGS. 2band2c.

At410, the method400may include forming package-level interconnect structures (e.g., solder balls113ofFIG. 2for LGA structures213ofFIG. 2g) coupled with the build-up layer(s) through the openings in the solder mask layer. The package-level interconnect structures may be formed by depositing electrically conductive material such as metal, solderable material, or combinations thereof. In some embodiments, the package-level interconnect structures may include BGA or LGA structures. The package-level interconnect structures may be formed according to techniques described in connection withFIGS. 2fand2g.

The method400may include other suitable actions including other embodiments described in connection withFIGS. 2a-gorFIGS. 3a-h. For example, the method400may further include forming a molding compound by depositing electrically insulative material (e.g., electrically insulative material107ofFIG. 2d) to at least partially encapsulate one or more of the die(s), electrically coupling the die(s) with a bridge (e.g., bridge108ofFIG. 1) composed of glass or silicon, or using a temporary carrier for fabrication of the IC package assembly. For example, the substrate may be coupled with a temporary carrier (e.g., temporary carrier216ofFIG. 2a) prior to forming the build-up layer(s) and the substrate may be decoupled from the temporary carrier subsequent to forming the one or more build-up layers, attaching the one or more dies and forming the molding compound.

FIG. 5schematically illustrates a flow diagram for a method500of fabricating an IC package assembly (e.g., IC package assembly300ofFIGS. 3a-h) including a bridge (e.g., bridge108ofFIGS. 3f-h), in accordance with some embodiments. The method500may comport with embodiments described in connection withFIGS. 3a-haccording to various embodiments.

At502, the method500may include coupling two or more dies (e.g., dies102a,102bofFIG. 3b) with a die attach film (e.g., die attach film303ofFIG. 3b). The dies may be coupled according to techniques described in connection withFIG. 3b. In some embodiments, the die attach film may be coupled with a temporary carrier (e.g., temporary carrier216ofFIG. 3a) prior to coupling the two or more dies with the die attach film.

At504, the method500may include forming a molding compound (e.g., electrically insulative material107ofFIG. 3c) to at least partially encapsulate the two or more dies. The molding compound may be deposited according to techniques described in connection withFIG. 3c. In some embodiments, the temporary carrier may be decoupled from the die attach film subsequent to forming the molding compound.

At506, the method500may include forming one or more build-up layers on the die attach film. The die attach film (together with other structural components such as, for example, the dies and/or molding compound) may serve as a substrate upon which the build-up layer(s) are formed. The build-up layer(s) may be formed according to techniques described in connection withFIG. 3for3g.

At508, the method500may include coupling a bridge (e.g., bridge108ofFIG. 3for3g) composed of glass or silicon with two of the two or more dies, the bridge being disposed in a plane of the one or more build-up layers. In some embodiments, coupling the bridge may be performed prior to or during formation of the build-up layer(s) such that the bridge is embedded in the build-up layer(s) (e.g., the IC package assembly300ofFIG. 3f). In other embodiments, coupling the bridge may be performed subsequent to forming the build-up layer(s) such that the bridge is exposed (e.g., the IC package assembly300ofFIG. 3g). For example, an opening (e.g., cavity) may be formed through the build-up layers and the bridge may be coupled with the dies through the opening, the bridge being disposed in the opening.

The method500may include other suitable actions including other embodiments described in connection withFIGS. 2a-gorFIGS. 3a-h. For example, the method500may further include forming a solder mask layer composed of a glass material on the build-up layers (e.g., on side S1of the build-up layers103ofFIG. 3f), forming openings through the solder mask layer and/or forming package-level interconnect structures electrically coupled with the build-up layer(s) (e.g., through the solder mask layer).

Various operations are described as multiple discrete operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. For example, actions of the method400or500may be performed in another suitable order than depicted.

Embodiments of the present disclosure may be implemented into a system using any suitable hardware and/or software to configure as desired.FIG. 6schematically illustrates a computing device600that includes an IC package assembly (e.g., IC package assembly100ofFIG. 1) as described herein, in accordance with some embodiments. The computing device600may house a board such as motherboard602. The motherboard602may include a number of components, including but not limited to a processor604and at least one communication chip606. The processor604may be physically and electrically coupled to the motherboard602. In some implementations, the at least one communication chip606may also be physically and electrically coupled to the motherboard602. In further implementations, the communication chip606may be part of the processor604.

The computing device600may include a plurality of communication chips606. For instance, a first communication chip606may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip606may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor604of the computing device600may be packaged in an IC assembly (e.g., IC package assembly100ofFIG. 1) that includes a solder mask layer (e.g., solder mask layer105ofFIG. 1) and/or bridge (e.g., bridge108ofFIG. 1) as described herein. For example, the circuit board122ofFIG. 1may be a motherboard602and the processor604may be a die102amounted on a package substrate104ofFIG. 1. The package substrate104and the motherboard602may be coupled together using package-level interconnect structures112. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip606may also include a die (e.g., die102aofFIG. 1) that may be packaged in an IC assembly (e.g., IC package assembly100ofFIG. 1) as described herein. In further implementations, another component (e.g., memory device or other integrated circuit device) housed within the computing device600may include a die (e.g., die102aofFIG. 1) that may be packaged in an IC assembly (e.g., IC package assembly100ofFIG. 1) as described herein.

EXAMPLES

According to various embodiments, the present disclosure describes an apparatus (e.g., IC package assembly) comprising one or more build-up layers having electrical routing features and a solder mask layer composed of a glass material, the solder mask layer being coupled with the one or more build-up layers and having openings disposed in the solder mask layer to allow coupling of package-level interconnect structures with the electrical routing features through the one or more openings. In some embodiments, the glass material is optically transparent, includes silica and has a coefficient of thermal expansion (CTE) from 3 to 7. In some embodiments, a pitch between two of the openings is less than or equal to 400 microns.

In some embodiments, the solder mask layer is coupled with a first side of the one or more build-up layers, the apparatus further comprising a die coupled with a second side of the one or more build-up layers, the second side being disposed opposite to the first side, wherein the electrical routing features are configured to route electrical signals of the die through the one or more build-up layers. In some embodiments, the die is a first die and the electrical routing features are first electrical routing features, the apparatus further comprising a second die coupled with the first die or the second side of the one or more build-up layers, wherein the one or more build-up layers include second electrical routing features that are configured to route electrical signals of the second die through the one or more build-up layers. In some embodiments, the second die is coupled with the second side of the one or more build-up layers, the apparatus further comprising a bridge composed of glass or silicon disposed in a plane formed by the one or more build-up layers, the bridge being configured to route electrical signals between the first die and the second die.

In some embodiments, the apparatus further includes a molding compound configured to at least partially encapsulate the die and the package-level interconnect structures, wherein the package-level interconnect structures include ball-grid array (BGA) or land-grid array (LGA) structures coupled with the first side of the one or more build-up layers through the openings.

According to various embodiments, the present disclosure describes a method comprising providing a substrate composed of a glass material, forming one or more build-up layers on the substrate, the one or more build-up layers having electrical routing features and forming openings through the substrate to form a solder mask layer composed of the glass material to allow coupling of one or more package-level interconnect structures with the electrical routing features through the openings.

In some embodiments, forming the one or more build-up layers comprises depositing a metal on the substrate, patterning the metal to define one or more of the electrical routing features and depositing a laminate material on the patterned metal. In some embodiments, the substrate is coupled with a first side of the one or more build-up layers, the method further comprising attaching one or more dies with a second side of the one or more build-up layers, wherein attaching the one or more dies forms an electrical connection between the one or more dies and the electrical routing features of the one or more build-up layers.

In some embodiments, the method further includes forming a molding compound to at least partially encapsulate the one or more dies. In some embodiments, the method further includes coupling the substrate with a temporary carrier prior to forming the one or more build-up layers and decoupling the temporary carrier from the substrate subsequent to forming the one or more build-up layers, attaching the one or more dies and forming the molding compound.

In some embodiments, attaching the one or more dies further comprises attaching a first die and a second die with the second side of the one or more build-up layers and electrically coupling the first die and the second die with a bridge composed of glass or silicon, the bridge being disposed in a plane formed by the one or more build-up layers and being configured to route electrical signals between the first die and the second die. In some embodiments, forming the openings comprises performing a wet etch process to remove portions of the glass material.

In some embodiments, the method further includes depositing electrically conductive material to form the package-level interconnect structures, wherein the package-level interconnect structures are electrically coupled with the electrical routing features of the one or more build-up layers through the openings.

According to various embodiments, the present disclosure describes another method comprising coupling a first die and a second die with a die attach film, forming a molding compound to at least partially encapsulate the first die and the second die, forming one or more build-up layers on the die attach film, the one or more build-up layers having electrical routing features configured to route electrical signals of the first die and the second die through the one or more build-up layers and coupling a bridge composed of glass or silicon with the first die and the second die to route electrical signals between the first die and the second die, the bridge being disposed in a plane of the one or more build-up layers.

In some embodiments, coupling the bridge is performed prior to forming the one or more build-up layers such that the bridge is embedded in the one or more build-up layers. In some embodiments, coupling the bridge is performed subsequent to forming the one or more build-up layers, the method further comprising forming an opening through the one or more build-up layers, wherein the bridge is disposed in the opening.

In some embodiments, the method further includes coupling the die attach film with a temporary carrier prior to coupling the first die and the second die with the die attach film and decoupling the temporary carrier from the die attach film subsequent to forming the molding compound. In some embodiments, the method further includes forming a solder mask layer composed of a glass material on the one or more build-up layers. In some embodiments, the method further includes forming one or more package-level interconnect structures, wherein the package-level interconnect structures are electrically coupled with the electrical routing features of the one or more build-up layers through the solder mask layer.

According to various embodiments, the present disclosure describes a system (e.g., computing device) comprising a package substrate including one or more build-up layers having one or more electrical routing features, and a solder mask layer composed of a glass material, the solder mask layer being coupled with a first side of the one or more build-up layers and having one or more openings disposed in the solder mask layer, a die coupled with a second side of the one or more build-up layers, the second side being disposed opposite to the first side, wherein the electrical routing features are configured to route electrical signals of the die through the one or more build-up layers and a circuit board coupled with first side of the one or more build-up layers using package-level interconnect structures that are coupled with the electrical routing features through the openings in the solder mask layer.

In some embodiments, the die is a first die and the electrical routing features are first electrical routing features, the system further comprising a second die coupled with the second side of the one or more build-up layers, wherein the one or more build-up layers include second electrical routing features that are configured to route electrical signals of the second die through the one or more build-up layers and a bridge composed of glass or silicon disposed in a plane formed by the one or more build-up layers, the bridge being configured to route electrical signals between the first die and the second die. In some embodiments, the system further includes one or more of an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, or a camera coupled with the circuit board, wherein the system is one of a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.