Piecewise linear gain amplifier

A piecewise linear gain amplifier circuit includes a differential preamplifier and a plurality of transconductors. The differential preamplifier is electrically coupled to a differential input having an input voltage. The transconductors are electrically coupled in parallel with each other. Each transconductor includes a respective differential input that is electrically coupled to a differential output of the differential preamplifier. In addition, each transconductor includes a respective differential output that is electrically coupled to a common differential PWL output. Each transconductor has a different linear input range. An optional attenuation circuit can be electrically coupled in parallel to the differential preamplifier. The differential output of the attenuation circuit can be electrically coupled to a differential input of another transconductor, and that transconductor can have a differential output that is electrically coupled to the common differential PWL output.

TECHNICAL FIELD

This application relates generally to solid-state circuit amplifiers.

BACKGROUND

Voltage amplifiers are used in a variety of applications including analog-to-digital converters. One type of amplifier used to achieve a wide dynamic range is a log amplifier which has a gain that is proportional to the natural log of the input voltage. One problem with log amplifiers is that the output-input voltage transfer characteristic (essentially its gain and gain behavior) varies significantly with environment factors such as process and temperature. Furthermore, at high input voltages, when the gain saturates, the corresponding output voltage also depends on process and temperature.

SUMMARY

Example embodiments described herein have innovative features, no single one of which is indispensable or solely responsible for their desirable attributes. The following description and drawings set forth certain illustrative implementations of the disclosure in detail, which are indicative of several exemplary ways in which the various principles of the disclosure may be carried out. The illustrative examples, however, are not exhaustive of the many possible embodiments of the disclosure. Without limiting the scope of the claims, some of the advantageous features will now be summarized. Other objects, advantages and novel features of the disclosure will be set forth in the following detailed description of the disclosure when considered in conjunction with the drawings, which are intended to illustrate, not limit, the invention.

An aspect of the invention is directed to a piecewise linear (PWL) gain amplifier circuit comprising: a differential preamplifier electrically coupled to a differential input, the differential input having an input voltage across the differential input; an attenuation circuit electrically coupled to the differential input, the attenuation circuit in parallel electrically with the differential preamplifier; and a plurality of transconductors, each transconductor having a respective differential output that is electrically coupled to a common differential PWL output. The plurality of transconductors comprises: a first transconductor having a differential input that is electrically coupled to a differential output of the differential preamplifier, the first transconductor having a first linear input range; a second transconductor having a differential input that is electrically coupled to the differential output of the differential preamplifier, the second transconductor having a second linear input range, the first and second transconductors in parallel electrically with each other; and a third transconductor having a differential input that is electrically coupled to a differential output of the attenuation circuit, the third transconductor having a third linear input range. The first linear input range is less than the second linear input range, and the second linear input range is less than the third linear input range.

In one or more embodiments, each transconductor comprises a differential transconductor. In one or more embodiments, each differential transconductor comprises: a first transistor having a gate terminal, a source terminal, and a drain terminal, the gate terminal of the first transistor electrically coupled to a first line of the differential output of the differential preamplifier; a first degeneration resistor electrically coupled to the source terminal of the first transistor; a second transistor having a gate terminal, a source terminal, and a drain terminal, the gate terminal of the second transistor electrically coupled to a second line of the differential output of the differential preamplifier; and a second degeneration resistor electrically coupled to the source terminal of the second transistor.

In one or more embodiments, the first and second transistors of each differential transconductor comprise NMOS transistors. In one or more embodiments, for each differential transconductor: the drain terminal of the first transistor is electrically coupled to a first line of the respective differential output of a respective transconductor, and the drain terminal of the second transistor is electrically coupled to a second line of the respective differential output of the respective transconductor. In one or more embodiments, a first load resistor is electrically coupled to a first line of the common differential PWL output, and a second load resistor is electrically coupled to a second line of the common differential PWL output. In one or more embodiments, the first and second lines of the common differential PWL output are electrically coupled to first and second input terminals, respectively, of an operational amplifier, the operational amplifier and the first and second load resistors forming a transimpedance amplifier. In one or more embodiments, the operational amplifier comprises first and second output terminals; a first feedback line is electrically coupled to the first input terminal, the first output terminal, and the first load resistor; and a second feedback line electrically is coupled to the second input terminal, the second output terminal, and the second load resistor.

In one or more embodiments, the differential preamplifier comprises: a first preamplifier transistor having a gate terminal, a source terminal, and a drain terminal, the gate terminal of the first preamplifier transistor electrically coupled to a first line of the differential input; a first preamplifier degeneration resistor electrically coupled to the source terminal of the first preamplifier transistor; a second preamplifier transistor having a gate terminal, a source terminal, and a drain terminal, the gate terminal of the second preamplifier transistor electrically coupled to a second line of the differential input; a second preamplifier degeneration resistor electrically coupled to the source terminal of the second preamplifier transistor; a first preamplifier load resistor electrically coupled to the drain terminal of the first preamplifier transistor; and a second preamplifier load resistor electrically coupled to the drain terminal of the second preamplifier transistor.

In one or more embodiments, the first and second preamplifier transistors comprise NMOS transistors. In one or more embodiments, each differential transconductor comprises: a first transistor having a gate terminal, a source terminal, and a drain terminal, the gate terminal of the first transistor electrically coupled to a first line of the differential output of the differential preamplifier; a first degeneration resistor electrically coupled to the source terminal of the first transistor; a second transistor having a gate terminal, a source terminal, and a drain terminal, the gate terminal of the second transistor electrically coupled to a second line of the differential output of the differential preamplifier; and a second degeneration resistor electrically coupled to the source terminal of the second transistor.

In one or more embodiments, a first transconductor bias current flows through the first or second degeneration resistor of the first differential transconductor, the first and second degeneration resistors of the first differential transconductor having a first degeneration resistance, a second transconductor bias current flows through the first or second degeneration resistor of the second differential transconductor, the first and second degeneration resistors of the second differential transconductor having a second degeneration resistance, and a preamplifier bias current flows through the first or second preamplifier degeneration resistor, the first and second degeneration resistors of the differential preamplifier having a preamplifier degeneration resistance. In one or more embodiments, the preamplifier bias current (IPRE), the first transconductor bias current (IB1), the second transconductor bias current (IB2), the preamplifier degeneration resistance (RPRE), the first degeneration resistance (RS1), and the second degeneration resistance (RS2), have the following relationship:

IP⁢R⁢E×RP⁢R⁢EGP⁢R⁢E>IB⁢2×RS⁢2>IB⁢1×RS⁢1
where GPREis a gain of the differential preamplifier.

In one or more embodiments, a first load resistor is electrically coupled to a first line of the common differential PWL output, a second load resistor is electrically coupled to a second line of the common differential PWL output, the first and second load resistors have a load resistance (RTIA), a first transition voltage (VOX) corresponds to an outer limit of the first linear input range of the first transconductor, a second transition voltage (VOY) corresponds to an outer limit of the second linear input range of the second transconductor, and the first transition voltage (VOX), the second transition voltage (VOY), the first transconductor bias current (IB1), the second transconductor bias current (IB2), and the load resistance (RTIA) have the following relationship: |VOX=2IB1×RTIA, and |VOY|=2IB2×RTIA. In one or more embodiments, the first and second transconductor bias currents (IBllIB2) are proportional to 1/RTIA, such that the first and second transition voltages (VOX, VOY) are substantially constant over a variation in a semiconductor manufacturing process, a temperature of the PWL gain amplifier circuit, and/or a supply voltage at the common differential PWL output.

In one or more embodiments, a first load resistor is electrically coupled to a first line of the common differential PWL output, a second load resistor is electrically coupled to a second line of the common differential PWL output, the first and second load resistors have a load resistance (RTIA), a first transition voltage (VOX) corresponds to an outer limit of the first linear input range of the first transconductor, a second transition voltage (VOY) corresponds to an outer limit of the second linear input range of the second transconductor, and the first transition voltage (VOX), the second transition voltage (VOY), the first transconductor bias current (IB1), the second transconductor bias current (IB2), and the load resistance (RTIA) have the following relationship: |VOX|=2IB1×RTIA, and |VOY|=2IB2×RTIA. In one or more embodiments, the first and second transconductor bias currents (IB1, IB2) are proportional to 1/RTIA, such that the first and second transition voltages (VOX, VOY) are substantially constant over a variation in a process, a temperature of the PWL gain amplifier circuit, and/or a supply voltage at the common differential PWL output.

In one or more embodiments, when an absolute value of the input voltage is less than a first transition voltage, the differential preamplifier and each transconductor contribute to a voltage gain of the input voltage, and the first transition voltage corresponds to an outer limit of the first linear input range of the first transconductor. In one or more embodiments, when the absolute value of the input voltage is between the first transition voltage and a second transition voltage, only the differential preamplifier and the second and third transconductors contribute to the voltage gain of the input voltage, the second transition voltage is higher than the first transition voltage, and the second transition voltage corresponds to an outer limit of the second linear input range of the second transconductor. In one or more embodiments, when the absolute value of the input voltage is greater than the second transition voltage, only the differential preamplifier and the third transconductor contribute to the voltage gain of the input voltage.

Another aspect of the invention is directed to a piecewise linear (PWL) gain amplifier circuit comprising: a differential preamplifier electrically coupled to a differential input, the differential input having an input voltage across the differential input; and a plurality of transconductors electrically coupled in parallel with each other, each transconductor having: a respective differential input that is electrically coupled to a differential output of the differential preamplifier, and a respective differential output that is electrically coupled to a common differential PWL output, wherein each transconductor has a different linear input range.

In one or more embodiments, the plurality of transconductors comprises a first transconductor having a first linear output range and a second transconductor having a second linear output range, and the first linear input range is less than the second linear output range. In one or more embodiments, the plurality of transconductors further comprises a third transconductor having a third linear output range, and the second linear output range is less than the third linear output range. In one or more embodiments, each transconductor comprises a differential transconductor.

DETAILED DESCRIPTION

A piecewise linear (PWL) gain amplifier includes a differential preamplifier and a plurality of transconductors. Each transconductor has a respective linear input range (LIR). The differential preamplifier (PREAMP) has a differential input having an input voltage Vinacross the differential input. The differential output of the PREAMP is electrically coupled to the transconductors, which are electrically coupled in parallel with each other. The LIR of the first transconductor is less than that of the second transconductor; the LIR of the second transconductor is less than that of the third transconductor, and so on.

A first transition voltage corresponds to the outer limit of the LIR of the first transconductor. A second transition voltage corresponds to the outer limit of the LIR of the second transconductor. When the absolute value of the input voltage is below the first transition voltage (e.g., between the first transition voltage and 0 V), the PREAMP and each transductor contribute to the voltage gain of the input voltage Vin. When the absolute value of the input voltage is between the first transition voltage and the second transition voltage, only the PREAMP, the second transconductor, and the third transconductor contribute to the voltage gain of the input voltage Vin. When the absolute value of the input voltage is higher than the second transition voltage, only the PREAMP and the third transductor contribute to the voltage gain of the input voltage Vin.

An optional attenuation circuit can be electrically coupled in parallel with the PREAMP. The attenuation circuit has a differential input having an input voltage Vinacross the differential input. The differential output of the attenuation circuit is electrically coupled to another transconductor (e.g., a fourth transconductor) that has a higher LIR than the transconductors that are electrically coupled to the PREAMP. The optional attenuation circuit and transconductor can increase the dynamic range of the PWL gain amplifier.

FIG.1is an example graph10of a simplified 3-segment voltage transfer function of a PWL gain amplifier according to an embodiment. The graph10illustrates three linear gain regions labeled as GX, GY, and GZ. These regions (GX, GY, and GZ) are the incremental voltage gains between |Vin| and |Vout| for the PWL amplifier where GX>GY>GZ. When |Vin|<VX, the amplifier exhibits a gain of GX, followed by a gain of GYfor VX<|Vin|<VY, and then a voltage gain of GZfor |Vin|>VY(where VX<VY). VXand VYare the first and second transition voltages, respectively, in graph10.

FIG.2is a circuit diagram of a PWL gain amplifier circuit20according to an embodiment. The gain amplifier circuit20is configured to implement an N-segment PWL voltage transfer function have N linear gain regions. In some embodiments, the PWL gain amplifier circuit20can implement the 3-segment PWL linear voltage transfer function illustrated in graph10. N can be a positive integer that is greater than or equal to 2 (e.g., 2, 3, 4, or another positive integer greater than or equal to 2).

The PWL gain amplifier circuit20includes a differential preamplifier A0, an attenuation circuit B0, and a plurality of transconductors Gm1, Gm1, . . . GmN(in general, transconductor Gm). The differential preamplifier A0and attenuation circuit B0are electrically coupled in parallel to each other and have a respective differential input200,210that has a differential input voltage Vin(e.g., a positive input voltage Vipand a negative input voltage Vinon each line of the respective differential input200,210).

The differential outputs225of the transconductor Gmare electrically coupled to each other at a common differential PWL output230having a differential output voltage Vout. Each side232,234of the common differential PWL output230is electrically coupled to a respective load resistor RTIAto amply the differential output voltage Voutto a supply voltage VDDat supply line240.

Each transconductor Gmhas an LIR over which the output current is a linear function (or approximately a linear function) of the differential input voltage at the differential input of the transconductor Gm. Gm1has a first LIR, Gm2has a second LIR, Gm3has a third LIR, and so on. GmN−1has an (N−1) LIR. The LIR of Gm1<LIR of Gm2<LIR of Gm3< . . . <LIR of GmN−1. The attenuation circuit B0decreases the magnitude of the input voltage Vin, which contributes to GmNhaving the largest LIR, thus increasing the dynamic range of the PWL gain amplifier circuit20. As such, each transconductor Gmhas a different LIR with GmNhaving the largest LIR.

The transductors Gmcan comprise differential pair transconductors or other transconductors. Each transconductor Gmcan be the same type or different type of transconductor than the other transductors Gm.

In operation, when the absolute value of the input voltage is lower than a first transition voltage (e.g., between the first transition voltage and 0), the differential preamplifier A0and each transductor Gmcontribute to the voltage gain of the input voltage Vin. The first transition voltage corresponds to the outer limit of the LIR of Gm1. When the absolute value of the input voltage is between the first transition voltage and a second transition voltage, the differential preamplifier A0and all transductors Gmexcept Gm1contribute to the voltage gain of the input voltage Vin. Transconductor Gm1does not contribute to the voltage gain of the input voltage Vinwhen the absolute value of the input voltage Vinis greater than the first transition voltage because transconductor Gm1is saturated.

The second transition voltage corresponds to the outer limit of the LIR of Gm2. When the absolute value of the input voltage is between the second transition voltage and a third transition voltage, the differential preamplifier A0and all transductors Gmexcept Gm1and Gm2contribute to the voltage gain of the input voltage Vin. Transconductors Gm1and Gm2do not contribute to the voltage gain of the input voltage Vinwhen the absolute value of the input voltage Vinis greater than the second transition voltage because transconductors Gm1and Gm2are saturated.

In general, the Mthtransition voltage corresponds to the outer limit of the LIR of GmM. M is a positive integer that is greater than or equal to 1 and less than or equal to N. When the absolute value of the input voltage is between the (M−1)thtransition voltage and the Mthtransition voltage, the differential preamplifier A0and all transductors Gmexcept transductor(s) Gm1. . . GmMcontribute to the voltage gain of the input voltage Vin. In other words, the differential preamplifier A0and transconductors GmM+1. . . GmNcontribute to the voltage gain of the input voltage Vinwhen the absolute value of the input voltage is between the (M−1)thtransition voltage and the Mthtransition voltage. Transconductors Gm1. . . GmMdo not contribute to the voltage gain of the input voltage Vinwhen the absolute value of the input voltage is between the (M−1)thtransition voltage and the Mthtransition voltage.

When the absolute value of the input voltage is greater than the (N−1)thtransition voltage, only the differential preamplifier A0and transductor GmNcontribute to the voltage gain of the input voltage Vin. Transconductors Gm1. . . GmN−1do not contribute to the voltage gain of the input voltage Vinwhen the absolute value of the input voltage is between the (M−1)thtransition voltage and the Mthtransition voltage.

FIG.3is a circuit diagram of a PWL gain amplifier circuit30according to an embodiment. PLW amplifier circuit30includes a differential preamplifier300, an attenuation circuit310and three differential-pair transconductors D1, D2, and D3. PWL gain amplifier circuit30can be the same as PWL gain amplifier circuit20when PWL gain amplifier circuit20includes three transductors Gm(i.e., transconductors Gm1, Gm2, and Gm3, where N=3).

The differential preamplifier300includes first and second preamplifier transistors MPRE,P, MPRE,N. The preamplifier transistors MPRE,P, MPRE,Nare illustrated as NMOS transistors. In other embodiments, both MPRE,P, MPRE,Ncan be PMOS transistors. In a preferred embodiment, the preamplifier transistors MPRE,P, MPRE,Nare the same type of transistor (e.g., both NMOS or both PMOS). An enlarged view of differential preamplifier300is illustrated inFIG.4. The gate terminal302of each preamplifier transistor MOP, MON is electrically coupled to a respective line of differential input311. Specifically, a positive input line312is electrically coupled to the gate terminal302of preamplifier transistor MPRE,P, and a negative input line314is electrically coupled to the gate terminal302of preamplifier transistor MPRE,N. A respective degeneration resistor RPREis electrically coupled to a source terminal304of each preamplifier transistor MPRE,P, MPRE,N. A respective preamplifier load resistor RLis electrically coupled to a drain terminal306of each preamplifier transistor MPRE,P, MPRE,N. The degeneration resistors RPREpreferably have the same resistance value. In addition, the preamplifier load resistors RLpreferably have the same resistance value.

A bias current IPREflows through each degeneration resistor RPREand twice the bias current IPRE(i.e., 2IPRE) flows through the bias transistor301to ground. The bias transistor301can function as a bias current source. In another embodiment, the bias transistor301can be cascoded. The bias transistor301is preferably the same type of transistor (e.g., NMOS or PMOS) as the preamplifier transistors MPRE,P, MPRE,N. The differential preamplifier300has a differential output305represented as positive output line308and negative output line309. The gain (GPRE) of the differential amplifier300is approximately equal (e.g., +/−10%) to RL/RPRE. Differential preamplifier300can be the same as or different than differential preamplifier A0.

Returning toFIG.3, the attenuation circuit310includes a first resistor RAthat is electrically coupled in series with a respective input line312,314and a second resistor RB that is electrically coupled in parallel with first resistors RA. As such, the attenuation circuit310attenuates the input voltage Vinby a factor of

RBRB+RA.
The attenuation circuit310can have other configurations, and thus provide other attenuation factors in other embodiments. The attenuation circuit310has a differential output315represented as positive output line318and negative output line319. The attenuation circuit310can be the same as or different than attenuation circuit B0.

Each differential-pair transconductor D1, D2, and D3(in general, differential-pair transconductor DN) includes first and second preamplifier transistors MP, MNand first and second degeneration resistors RS. For example, differential-pair transconductor D3includes first and second differential-amplifier transistors MLP, MLNand first and second degeneration resistors RSL. The degeneration resistors RSLpreferably have the same resistance value. Differential-pair transconductor D1includes first and second differential-amplifier transistors M1P, M1Nand first and second degeneration resistors RS1. The degeneration resistors RS1preferably have the same resistance value. Differential-pair transconductor D2includes first and second differential-amplifier transistors M2P, M2Nand first and second degeneration resistors RS2. The degeneration resistors RS2preferably have the same resistance value. The differential-pair transconductors D1, D2, and D3can be the same as transconductors Gm1, Gm2, and Gm3, respectively, when PWL gain amplifier circuit20includes only three transductors Gm.

The differential-pair transistor MP, MNare illustrated as NMOS transistors. In other embodiments, one or both differential-amplifier transistor(s) MP, MNcan be PMOS transistors. In a preferred embodiment, differential-pair transistor(s) MP, MNare the same type of transistor (e.g., NMOS or PMOS). Each differential-pair transistor MP, MNincludes a gate terminal502, a source terminal504, and a drain terminal506. The gate terminal502of each differential-amplifier transistor MP, MNis electrically coupled to a respective input line. For D1and D2, the gate terminals502are electrically coupled to the output lines308,309(e.g., the differential output305) of the differential preamplifier300. For example, the gate terminal502of differential-pair transistor MPin D1and D2is electrically coupled to positive output line308, which is electrically coupled to the drain terminal306of preamplifier transistor MPRE,P. In addition, the gate terminal502of differential-pair transistor MNin D1and D2is electrically coupled to negative output line309, which is electrically coupled to the drain terminal306of preamplifier transistor MPRE,N. Thus, D1and D2each has a differential input that is electrically coupled to the differential output305of the differential preamplifier300.

For D3, the gate terminals502are electrically coupled to the output lines318,319(e.g., the differential output315) of the attenuation circuit310. For example, the gate terminal502of differential-pair transistor MPin D3is electrically coupled to the positive output line318of attenuation circuit310. In addition, the gate terminal502of differential-pair transistor MNin D3is electrically coupled to the negative output line319of attenuation circuit310. Thus, D3has a differential input that is electrically coupled to the differential output315of the attenuation circuit310.

A respective degeneration resistor RSis electrically coupled to the source terminal504of each differential-amplifier transistor MP, MN. Fora given differential-pair transconductor, the degeneration resistors RSpreferably have the same resistance value. The degeneration resistors RSof different differential-pair transconductors can have the same or different values. A bias current IBNflows through each degeneration resistor RSand twice the bias current IBN(i.e., 2IBN) flows through the bias transistor501to ground. The bias transistor501can function as a current source. In another embodiment, the bias transistor501can be cascoded. The bias transistor501is preferably the same type of transistor (e.g., NMOS or PMOS) as the differential-pair transistors MP, MN.

The drain terminal506of each differential-amplifier transistor MP, MNis electrically coupled to a respective side of a differential output510. For example, the drain terminal506of differential-amplifier transistor MPis electrically coupled to a common positive output line512. In addition, the drain terminal506of differential-amplifier transistor MNis electrically coupled to a common negative output line514. As illustrated inFIG.3, each differential output510is electrically coupled to a common differential PWL output520, which is electrically coupled to a differential PWL amplifier circuit output530. The differential PWL amplifier circuit output530has a positive output voltage Vopand a negative output voltage Vomwhere the PWL output voltage Vout=Vop− Vom. The common differential PWL output520can be the same as common differential PWL output230. For example, the common differential PWL output520includes first and second sides522,524(e.g., positive and negative sides, respectively) that can the same as the first and second sides322,324(e.g., positive and negative sides, respectively) of common differential PWL output230.

In some embodiments, the preamplifier transistors MPRE,P, MPRE,Nand the differential-amplifier transistors MN, MPcan be sized to have approximately equal current densities (e.g., within +/−1-5% of each other). The bias currents and degeneration resistor values can be chosen and/or configured such that the following relationship applies:

In this configuration, the input voltage required to completely steer the entire respective bias currents towards one leg of the differential pair will be smallest for D1followed by D2and then the PREAMP. This can be represented mathematically by Equations (1) and (2).
|Vin|>VX=2(IB1×RS1/GPRE)⇒IM1P=2IB1,IM1N=0(Vin>VX)&IM1P=0,IM1N=2IB1(Vin<−VX)  (1)
|Vin|>VY=2(IB2×RS2/GPRE)⇒IM2P=2IB2,IM2N=0(Vin>VY)&IM2P=0,IM2N=2IB2(Vin<−VY)  (2)

The corresponding output voltages when input voltage Vinequals VXand VY(depicted above) are represented by Equations (3) and (4).
|VOX|=2IB1×RTIA(3)
|VOY|=2IB2×RTIA(4)

In addition to the PREAMP, D1, and D2,FIG.3depicts another differential pair, D3, realized by NMOS transistors MLPand MLN. The input voltage to D3is attenuated by

RBRB+RA,
which together with the degeneration resistor RSLensures that the voltage required to steer the entire bias current towards one leg of D3is significantly larger than VY(see Equation (2)). Essentially, this realizes a near-constant gain for the entire input voltage range of the PWL amplifier and is represented by Equation (5).

Using Equations (1)-(5), the PWL voltage transfer characteristics of graph10can now be described with respect to PWL gain amplifier circuit30. When 0<|Vin|<VX, the PREAMP, D1, D2, and D3contribute to the total voltage gain, which can be characterized as

GX≈RLRS×(Gm⁢1+Gm⁢2)×RT⁢I⁢A+GZ,
where Gm1and Gm2are the total effective transconductances realized by D1and D2, respectively, when |Vin|=VX. Next, when VX<|Vin|<VY, D1is saturated and the PREAMP, D2, and D3contribute to the total voltage gain, which can be characterized as

GY≈RLRS×Gm⁢2×RT⁢I⁢A+GZ.
Finally, when |Vin|>VY, the voltage gain is equal to GZas depicted in Equation (5). As such, the LIR of D1<LIR of D2<LIR of D3.

It is noted that by changing the values of the resistors and bias currents, the gains GX, GY, and GZ as well as the breakpoints of the voltage transfer characteristic (VX, VY, VOX, VOY) (e.g., the values of VX, VY, VOX, and/or VOY) can be programmed and/or configured. Especially, if the bias currents IB1and IB2are made inversely proportional to the load resistor RTIA, the output transition voltages VOXand VOYare substantially constant (e.g., within less than or equal to +/−1%) against variations in semiconductor manufacturing process, temperature (e.g., temperature of the PWL gain amplifier circuit30), and/or supply voltage. For example, a semiconductor foundry manufactures integrated circuits at “typical” process conditions, in which case the NMOS and PMOS transistors (e.g., M) are manufactured with “typical” parameters (e.g., speed, etc.). The semiconductor foundry may shift (e.g., vary) the process overtime, which may result in relatively slower or relatively faster conditions.

Therefore, in operation, when the absolute value of the input voltage is lower than a first transition voltage VX(e.g., between 0 and VX), the differential preamplifier300and each differential-pair transductor D1-D3contribute to the voltage gain of the input voltage Vin. The first transition voltage corresponds to the outer limit of the LIR of differential-pair transductor D1. When the absolute value of the input voltage is between the first transition voltage VXand a second transition voltage VY, the differential preamplifier A0and differential-pair transductor D2and attenuator together with D3contribute to the voltage gain of the input voltage Vin. Differential-pair transductor D1does not contribute to the voltage gain of the input voltage Vinwhen the input voltage Vinis greater than the first transition voltage VXbecause differential-pair transductor D1is saturated. The second transition voltage VYcorresponds to the outer limit of the LIR of differential-pair transductor D2.

When the absolute value of the input voltage is greater than the second transition voltage VY, only the differential preamplifier300and the differential-pair transductor D3contribute to the voltage gain of the input voltage Vin. Differential-pair transductors D1and D2do not contribute to the voltage gain of the input voltage Vinwhen the input voltage Vinis greater than the second transition voltage VYbecause differential-pair transductor D1and D2are saturated.

FIG.6is a graph60of the LIR of a transconductor according to an embodiment. The LIR extends from a negative input voltage −VLIRto a positive input voltage +VLIR. In the LIR, the output current Ioutvaries linearly (or approximately linearly) with the input voltage Vin. The linear relationship between the input voltage Vinand output current Ioutis the gain600of the transconductor. When the absolute value of the input voltage Vinis greater than VLIR, the transconductor is saturated and the gain is 0 (or approximately 0). Graph60can represent the LIR of any of the transconductors described herein including transconductors Gmand differential-pair transconductors D1, D2, and D3, though the gain600of each transconductor may be different.

FIG.7is a circuit diagram of a PWL gain amplifier circuit70according to an alternative embodiment. PWL gain amplifier circuit70is the same as PWL amplifier gain circuit20except that in PWL gain amplifier circuit70the common differential PWL output230is electrically coupled to an operational amplifier (Opamp) and load resistors RTIAare wrapped around the Opamp in respective feedback circuits to form a transimpedance amplifier700. For example, the Opamp includes first and second input terminals702,704and first and second output terminals712,714. A first feedback line710is electrically coupled to the first input terminal702, the first output terminal712, and the first load resistor RTIA. A second feedback line720is electrically coupled to the second input terminal704, the second output terminal714, and the second load resistor RTIA.

FIG.8is a circuit diagram of a PWL gain amplifier circuit80according to an alternative embodiment. PWL gain amplifier circuit80is the same as PWL amplifier gain circuit20except that PWL gain amplifier circuit80does not include the attenuation circuit B0and the corresponding transconductor GmN. Thus, PWL gain amplifier circuit80has one less transconductor Gm(e.g., for a total of N−1 transconductors Gm) compared to PWL gain amplifier circuit80(e.g., which has a total of N transconductors Gm). Each transconductor Gmhas a different LIR. In some embodiments, the PWL gain amplifier circuit80can be configured such that the LIR of Gm1<LIR of Gm2. . . <LIR of GmN.

In some embodiments, the output of the PWL gain amplifier circuit80can include a transimpedance amplifier that is the same as transimpedance amplifier700in PWL gain amplifier circuit70.

FIG.9is an example graph90of a simplified 3-segment voltage transfer function that can be produced with PWL gain amplifier circuit80according to an embodiment. Graph90is the same as graph10except that region GZhas a gain of 0 (i.e., a slope of 1). Both graph10,90illustrate the relationship GX>GY>GZ. Graph90can be produced when the PWL gain amplifier circuit80includes 2 transconductor (i.e., N=2). Graph90can be modified to include additional linear gain regions when N>2.

The graph90illustrates three linear gain regions labeled as GX, GY, and GZ. These regions (GX, GY, and GZ) are the incremental voltage gains between |Vin| and |Vout| for the PWL amplifier where GX>GY>GZ. When |Vin|<VX, the amplifier exhibits a gain of GX, followed by a gain of GYfor VX<|Vin|<VY, and then a voltage gain of GZfor |Vin|>VY(where VX<VY). VXand VYare the first and second transition voltages, respectively, in graph90.

The invention should not be considered limited to the particular embodiments described above, but rather should be understood to cover all aspects of the invention as fairly set out in the attached claims. Various modifications, equivalent processes, as well as numerous structures to which the invention may be applicable, will be apparent to those skilled in the art to which the invention is directed upon review of this disclosure. The claims are intended to cover such modifications and equivalents.