Semiconductor device and inverter

A semiconductor device includes: a semiconductor base having a first main surface and a second main surface which are opposite to each other; a first main electrode formed on the first main surface and electrically connected to the semiconductor base; a first control electrode pad formed on the first main surface; a first insulating film interposed between the semiconductor base and the first control electrode pad; a peripheral withstand voltage holding structure formed in a peripheral region surrounding the first main electrode and the first control electrode pad on the first main surface; a second main electrode formed on the second main surface and electrically connected to the semiconductor base; a second control electrode pad formed on the second main surface; and a second insulating film interposed between the semiconductor base and the second control electrode pad, wherein the second control electrode pad is surrounded by the second main electrode.

BACKGROUND OF THE INVENTION

Field

The present invention relates to a semiconductor device having a double gate structure including control electrodes on cathode and anode sides and an inverter using the semiconductor device as a switching device.

Background

A circuit in which an AC-DC converter for converting alternating current (AC) into direct current (DC) is combined with a DC-AC converter to perform conversion to an arbitrary frequency or voltage is called an “inverter.” Since the inverter can variably control an output voltage and its frequency, the inverter can freely control a rotating speed of a motor and is used as a variable speed apparatus for the motor.

In past days, bipolar transistors were used as switching devices for inverters for small capacity areas, and gate turn-off thyristors (GTO) were used for medium-large capacity areas. Currently, insulated gate bipolar transistors (IGBT) are mainly used, which achieves both high controllability/high speed by voltage control using a MOS gate structure and high current carrying performance that is a main feature of bipolar devices.

Semiconductor devices having the double gate structure have been devised to especially improve switching performance of bipolar devices. Research into double gate IGBTs applying the double gate structure to IGBTs is currently underway. A double gate IGBT has a structure in which a gate electrode is formed on an emitter-side main surface and a control gate electrode is formed on a collector-side main surface on the opposite side to the emitter-side main surface (e.g., see JP 2010-123667 A).

SUMMARY

A peripheral withstand voltage holding structure is formed on a peripheral region of the emitter-side main surface. Electrodes of the peripheral withstand voltage holding structure are not connected to external lead electrodes and covered with a protective film of low thermal conductivity. On the other hand, a control gate electrode pad is positioned at an outer peripheral portion of the collector-side main surface and is electrically connected to a lead frame via solder. A gate insulating film of low thermal conductivity is interposed between a control gate electrode pad and a p+-type collector layer. Since only one outer peripheral side of the control gate electrode pad faces the collector electrode and is insulated by an insulating film, heat is not easily dissipated from the control gate electrode pad side to the collector electrode side. Therefore, conventional double gate IGBTs have structures in which heat is dissipated easily from neither the emitter-side main surface nor the collector-side main surface. Since the conventional double gate IGBTs thus have both of a region of high heat dissipation efficiency where a main electrode is formed and the peripheral region of low heat dissipation efficiency, the temperature in the double gate IGBTs is likely to become non-uniform when a large loss occurs. Especially when a short circuit accident occurs, which may trigger a drastic temperature change, a risk of causing thermal breakdown near the peripheral region or the gate electrode pad increases.

The present invention has been made to solve the above-described problems, and it is an object of the present invention to provide a semiconductor device and an inverter capable of reducing the risk of causing thermal breakdown.

A semiconductor device according to the present disclosure includes: a semiconductor base having a first main surface and a second main surface which are opposite to each other; a first main electrode formed on the first main surface and electrically connected to the semiconductor base; a first control electrode pad formed on the first main surface; a first insulating film interposed between the semiconductor base and the first control electrode pad; a peripheral withstand voltage holding structure formed in a peripheral region surrounding the first main electrode and the first control electrode pad on the first main surface; a second main electrode formed on the second main surface and electrically connected to the semiconductor base; a second control electrode pad formed on the second main surface; and a second insulating film interposed between the semiconductor base and the second control electrode pad, wherein the second control electrode pad is surrounded by the second main electrode.

In the present disclosure, the second control electrode pad is surrounded by the second main electrode which is a heat dissipation path. This facilitates heat dissipation from the peripheral region of the second control electrode pad, and can thereby reduce temperature non-uniformity. As a result, it is possible to improve the operation performance of the semiconductor device and reduce the risk of causing thermal breakdown.

DESCRIPTION OF EMBODIMENTS

A semiconductor device and an inverter according to the embodiments of the present disclosure will be described with reference to the drawings. The same components will be denoted by the same symbols, and the repeated description thereof may be omitted.

First Embodiment

FIG. 1is a plan view of an emitter-side main surface of a semiconductor device according to a first embodiment. A semiconductor base1is obtained by epitaxially growing a semiconductor layer on a semiconductor substrate and has an emitter-side main surface and a collector-side main surface, which are opposite to each other. An emitter-side IGBT region including an emitter electrode2and a gate electrode pad3, and a peripheral region surrounding the emitter-side IGBT region are formed on the emitter-side main surface of the semiconductor base1. The emitter electrode2is provided so as to surround three sides of the gate electrode pad3. A peripheral withstand voltage holding structure4is formed in the peripheral region.

FIG. 2is a plan view of the collector-side main surface of the semiconductor device according to the first embodiment. A collector-side IGBT region including a collector electrode5and a control gate electrode pad6is formed on the collector-side main surface. In the present embodiment, the control gate electrode pad6is positioned at the center of the chip and the entire peripheral region thereof is surrounded by the collector electrode5. The collector electrode5is provided so as to cover the region of the collector-side main surface other than the control gate electrode pad6. Therefore, the collector electrode5is positioned in the entire peripheral region of the collector-side main surface facing the peripheral withstand voltage holding structure4.

FIG. 3is a cross-sectional view along I-II inFIG. 1. A field stop layer8composed of an n+-type impurity layer of high impurity concentration is formed on a p+-type collector layer7. An n−-type drift layer9of lower impurity concentration than that of the field stop layer8is formed on the field stop layer8. A p-type base layer10having a predetermined thickness is formed on the n−-type drift layer9.

A plurality of trenches11are formed so as to penetrate the p-type base layer10and reach the n−-type drift layer9. The plurality of trenches11are provided at a predetermined pitch (interval) and have a striped structure with the trenches extending in a depth direction inFIG. 3, that is, with the trenches extending in parallel to the vertical direction of the paper surface or an annular structure with the trenches extending in parallel to the vertical direction of the paper surface and then being turned around at their distal ends.

The p-type base layer10is divided into a plurality of portions by the plurality of trenches11. Some of the divided portions are p-channel layers12constituting channel regions. An n+-type emitter region13is formed on a side face of the trench11in a surface layer of the p-channel layer12. The n+-type emitter region13has higher impurity concentration than that of the n-type drift layer9and is terminated in the p-type base layer10.

A gate insulating film14is formed so as to cover an inner wall surface of each trench11. A gate electrode15made of doped polysilicon or the like is formed on the gate insulating film14in the trench11. An insulating film16is formed on the emitter-side main surface of the semiconductor base1so as to cover the top of the gate electrode15.

A p-type diffusion layer18is formed on the n−-type drift layer9so as to surround the p-type base layer10. A doped polysilicon layer17is formed above the p-type diffusion layer18with the insulating film16interposed therebetween. The doped polysilicon layer17is electrically connected to the gate electrode15and electrically connected to the gate electrode pad3through a contact hole19formed in the insulating film16. Therefore, the gate electrode15is electrically connected to an external part via the doped polysilicon layer17and the gate electrode pad3.

The emitter electrode2is formed on the insulating film16. The emitter electrode2is electrically connected to the n+-type emitter region13and the p-channel layer12through a contact hole20formed in the insulating film16. In this way, the emitter-side IGBT region is constructed.

In the peripheral region surrounding the emitter-side IGBT region, a plurality of p-type guard ring layers21are formed on the n-type drift layer9as a multiplexed ring structure. The p-type diffusion layer18and the p-type guard ring layers21are formed deeper than the p-type base layers10. A plurality of outer peripheral electrodes22are provided on the insulating film16so as to correspond to the plurality of p-type guard ring layers21. The plurality of p-type guard ring layers21are electrically connected to the respective outer peripheral electrodes22through contact holes23formed in the insulating film16. The plurality of outer peripheral electrodes22are electrically separate from each other and have a multiplexed ring structure as in the case of the p-type guard ring layers21.

An n+-type layer24is formed on the surface layer of the n−-type drift layer9so as to surround the p-type guard ring layers21. An electrode25is formed on the n+-type layer24and they are electrically connected together. The n+-type layer24and the electrode25constitute an equipotential ring (EQR) structure. Parts of the peripheral region to which no electrical connection is made are covered with a protective film26. The peripheral withstand voltage holding structure4of the peripheral region of the emitter-side main surface is constructed in this way.

High concentration n+-type collector layers27are selectively formed on the collector side surface of the p+-type collector layer7. A plurality of trenches28are formed so as to penetrate the p+-type collector layer7, the n+-type collector layer27and the field stop layer8and reach the n−-type drift layer9. The plurality of trenches28are provided in a striped shape at a predetermined interval, for example, at equal intervals.

A gate insulating film29is formed so as to cover the inner wall surface of each trench28. A control gate electrode30made of doped polysilicon or the like is formed on the gate insulating film29in the trench28.

All the control gate electrodes30are electrically connected to each other in separate cross sections. The collector electrode5is in contact and electrically connected with the p+-type collector layer7and the n+-type collector layer27. An insulating film31is formed on the collector-side main surface of the semiconductor base1so as to cover the control gate electrode30.

The control gate electrode pad6is electrically connected to a doped polysilicon layer33through a contact hole32formed in the insulating film31. The doped polysilicon layer33is connected to the control gate electrode30through a contact hole34formed in the insulating film31. The collector electrode5is provided so as to surround the control gate electrode pad6, a peripheral region of which is covered with the protective film35, and is separated from the control gate electrode30by the insulating film31and the protective film35. The collector-side IGBT region is constructed in this way.

The double gate IGBT according to the present embodiment is constructed as described above. The double gate IGBT is connected to the external part as described below. The emitter electrode2is connected to a lead frame37which is an external lead electrode via solder36. The collector electrode5is connected to a lead frame39which is an external lead electrode via solder38. A current flows between the collector and the emitter through the lead frame39, the solder38, the collector electrode5, the semiconductor base1, the emitter electrode2, the solder36and the lead frame37.

Electrical connection between the gate electrode15and the outside is achieved by bonding a bonding wire40to the gate electrode pad3. A voltage can be applied to the control gate electrode30by joining a bonding wire41to the control gate electrode pad6. The double gate IGBT as a whole is packaged by coating with resin or the like and part of the external lead electrode protrudes to the outside of the packaging, which constitutes a contact with the apparatus. Since the emitter electrode2and the collector electrode5are connected to the lead frames37and39which are the external lead electrodes via the solder36and38, it is possible to secure a large heat dissipation area, a total volume of the region over which heat spreads in several microseconds and a heat capacity.

Next, operation of the semiconductor device according to the present embodiment will be described. First, since no gate voltage is applied to the gate electrode15in an OFF state, no inversion layer is formed in the p-channel layer12. For this reason, the current between the collector and the emitter is turned OFF. When a positive gate voltage is applied to the gate electrode15, an inversion layer is formed in the p-channel layer12, a current flows between the collector and the emitter, resulting in an ON state.

In this operation, when a positive voltage with respect to the collector voltage (e.g., voltage V>0) is applied to the control gate electrode30, this voltage forms an n-channel layer in the p+-type collector layer7via the gate insulating film29. When the n+-type collector layer7, the n-channel layer and the field stop layer8become a conduction path, which causes a bias potential of pn junction composed of the p+-type collector layer7and the field stop layer8to decrease. Therefore, the hole quantity injected from the p+-type collector layer7to the n+-type emitter region13side is reduced during an ON state. The conduction path constructed of the n+-type collector layer7, the n-channel layer and the field stop layer8becomes an outflow path for electrons accumulated in the n−-type drift layer9to the collector electrode5during turn-off switching operation. For this reason, annihilation of electrons accumulated in the n−-type drift layer9is fastened. Therefore, it is possible to reduce a switching loss while increasing a steady-state loss as device characteristics.

On the other hand, when a negative voltage with respect to the collector voltage (e.g., voltage V<0) is applied to the control gate electrode30, this voltage affects the field stop layer8and the p+-type collector layer7which becomes the collector region via the gate insulating film29. Thus, in the p+-type collector layer7, holes move in a direction in which they are accumulated. In the field stop layer8, electrons move in a direction in which they are reduced. Thus, the hole quantity injected from the p+-type collector layer7to the n+-type emitter region13side increases during an ON state. Therefore, it is possible to reduce a steady-state loss while increasing a switching loss as device characteristics.

As described above, the control gate electrode30can adjust the hole quantity in the p+-type collector layer7which becomes the collector region of the IGBT and the electron quantity in the field stop layer8. It is therefore possible to adjust a steady-state loss and a switching loss of the semiconductor device to optimum values after the device manufacturing process ends. Furthermore, an application designer or an apparatus user can set optimum losses in accordance with use conditions of the drive frequency or the like by controlling the voltage applied to the control gate electrode30. Furthermore, development of time-consuming custom device manufacturing steps such as adjustment of device manufacturing conditions and repetition of try and error of application evaluation becomes unnecessary. Even when the drive frequency and temperature change during operation, it is possible to set the device performance such as loss characteristics and surge characteristics to values optimum for the frequency and temperature by adjusting the voltage applied to the control gate electrode30.

Next, effects of the present embodiment will be described in comparison with comparative examples.FIG. 4is a plan view of the collector-side main surface of the semiconductor device according to a comparative example.FIG. 5is a cross-sectional view along I-II inFIG. 4. In the comparative example, the control gate electrode pad6is positioned in the peripheral region of the collector-side main surface. Only one side of the peripheral region of the control gate electrode pad6faces the collector electrode5and is insulated and separated by the insulating film31and the protective film35. The control gate electrode pad6is electrically connected to the lead frame43which is the external lead electrode via the solder42.

The heat of the semiconductor base1generated by a loss is dissipated from the collector-side main surface using the collector electrode5electrically connected to the semiconductor base1and the lead frame39connected to the collector electrode5as a heat dissipation path. Therefore, the larger the contact area between the semiconductor base1and the collector electrode5, the contact area between the collector electrode5and the lead frame39or the larger the thermal conductivity of the collector electrode5and the lead frame39, the more efficiently the heat is dissipated. On the other hand, the gate insulating film29having small thermal conductivity is interposed between the control gate electrode pad6and the semiconductor base1. For this reason, heat is not easily dissipated from the control gate electrode pad6.

In the comparative example, only one side of the peripheral region of the control gate electrode pad6faces the collector electrode5, and so heat is not easily dissipated from the control gate electrode pad6side to the collector electrode5side. In contrast, in the present embodiment, the control gate electrode pad6is surrounded by the collector electrode5which is a heat dissipation path. This facilitates heat dissipation from the peripheral region of the control gate electrode pad6, and can thereby reduce temperature non-uniformity. As a result, it is possible to improve the operation performance of the semiconductor device and reduce the risk of causing thermal breakdown.

Furthermore, the gate insulating film29of low thermal conductivity is interposed between the control gate electrode pad6and the semiconductor base1, and so heat of the semiconductor base1is not easily dissipated from the control gate electrode pad6. Therefore, the heat of the region of the control gate electrode pad6needs to be dissipated from the emitter-side main surface. More specifically, when more than half of the region of the emitter-side main surface facing the control gate electrode pad6is positioned outside the region of the emitter electrode2, heat dissipation to the emitter electrode2reduces, which may start affecting the IGBT performance and reduce short circuit tolerance to approximately ⅔ or below.

In contrast, in the present embodiment, the control gate electrode pad6is positioned at the center of the collector-side main surface of the semiconductor base1. Therefore, the region of the emitter-side main surface facing the control gate electrode pad6is not the peripheral region from where heat is not easily dissipated, but is the region in which the emitter electrode2is formed. Since the emitter electrode2is electrically connected to the n+-type emitter region13, the region in which the emitter electrode2is formed is excellent in heat dissipation. This makes it possible to secure excellent heat dissipation.

Note that heat is also dissipated to a certain degree from the gate electrode pad3via the bonding wire40, and so the region of the emitter-side main surface facing the control gate electrode pad6may be the region in which the gate electrode pad3is formed.

In the event of a short circuit accident, even if the device can manage to remain safe without thermal breakdown and be protected from current interruption, a supply voltage VCE is applied to the IGBT immediately after completion of the protective operation. A leakage current caused by a supply voltage flows at a high temperature section of the IGBT caused by temperature non-uniformity, a product of the leakage current and the supply voltage is generated as a loss and consumed as heat. The leakage current increases when the temperature is high and if a loss by the leakage current is large with respect to the amount of heat dissipation, positive feedback may be applied, leading to thermal breakdown. For this reason, it is important to provide a structure of the IGBT that prevents temperature non-uniformity. Particularly in the peripheral region where the peripheral withstand voltage holding structure4for blocking the voltage is formed, a leakage current density is likely to become larger than the region in which the emitter electrode2is formed. The peripheral region of the emitter-side main surface has substantially no efficient heat dissipation path. In contrast, in the present embodiment, the collector electrode5is positioned in the peripheral region of the collector-side main surface facing the peripheral withstand voltage holding structure4. The collector electrode5is electrically connected to the lead frame39which is the external lead electrode via the solder38. Therefore, the peripheral region of the collector-side main surface also has a heat dissipation path.

Furthermore, the bonding wire41is joined to the control gate electrode pad6as the external lead electrode. The bonding wire41has higher positioning accuracy with respect to the control gate electrode pad6compared to a case where the lead frame43is soldered as the comparative example. Therefore, it is possible to reduce misalignment and reduce the size of the control gate electrode pad6. This makes it possible to relatively increase the size of the collector electrode5, thereby improve heat dissipation from the collector electrode5and reduce temperature non-uniformity caused by the control gate electrode pad6.

Second Embodiment

FIG. 6is a plan view of an emitter main surface side of a semiconductor device according to a second embodiment.FIG. 7is a plan view of a collector-side main surface of the semiconductor device according to the second embodiment. The size and the position of the control gate electrode pad6in the second embodiment are different from those in the first embodiment. The control gate electrode pad6is a rectangle having a size of 1.2 mm×1.5 mm, and one side of the rectangle is located at a peripheral end of the chip.

An index of heat dissipation efficiency with respect to the collector electrode5is calculated by dividing the unit perimeter of the control gate electrode pad6by the unit area of the control gate electrode pad6. The index can be increased by downsizing the control gate electrode pad6to achieve rapid heat dissipation and reduce temperature non-uniformity. Furthermore, since the plane shape of the control gate electrode pad6is rectangular, even when one side is located at a peripheral end of the chip which is not surrounded by the collector electrode5, heat is dissipated from three sides surrounded by the collector electrode5to the collector electrode5side.

Note that the plane shape of the control gate electrode pad6is not limited to rectangular, but may be semicircular, fan-shaped, pentagonal or higher polygonal. In any case, it is only required that any part other than the one side of the perimeter of the control gate electrode pad6be surrounded by the collector electrode5. Thus, heat is dissipated from the surrounded part to the collector electrode5. More specifically, it is preferable that 75% or more of the perimeter of the control gate electrode pad6be surrounded by the collector electrode5. In this case, if the control gate electrode pad6can be downsized, an effect equivalent to surrounding the whole perimeter can be obtained. For example, when the control gate electrode pad6is reduced to a size of 1.2 mm×1.5 mm as in the case of the present embodiment, such temperature non-uniformity that affects the IGBT performance may not be generated.

The collector electrode5is positioned in the region facing the gate electrode pad3and the emitter electrode2is positioned in the region facing the control gate electrode pad6. That is, the gate electrode pad3and the control gate electrode pad6are positioned such that they do not overlap when projected in a plan view. Therefore, the gate electrode pad3and the control gate electrode pad6are not provided in regions facing each other. It is thereby possible to prevent heat from being accumulated between the gate electrode pad3and the control gate electrode pad6which are inferior in heat dissipation.

The double gate structure according to the first or second embodiment is not limited to an IGBT that allows short circuit protection and self-shutdown operation, but is also applicable to a device such as a GTO which does not have current saturation characteristics and cannot perform short circuit protection and self-shutdown. For example, when an OFF voltage is applied immediately after temperature non-uniformity caused by a temperature rise in the GTO due to a surge current, thermal runaway due to a leakage current may occur. Therefore, a reduction of temperature non-uniformity is also important to the GTO. However, since the GTO has an operating frequency approximately 1 to 2 digits lower than that of the IGBT, the influence of the present embodiment is not significantly large. On the other hand, for transistors for which a self-shutdown operation for protection against short circuit is required, temperature non-uniformity for several microseconds affects the performance, and so the configuration according to the first or second embodiment is particularly effective.

The semiconductor base1is not limited to a base formed of silicon, but instead may be formed of a wide-bandgap semiconductor having a bandgap wider than that of silicon. The wide-bandgap semiconductor is, for example, a silicon carbide, a gallium-nitride-based material, or diamond. A semiconductor device formed of such a wide-bandgap semiconductor has a high voltage resistance and a high allowable current density, and thus can be miniaturized. The use of such a miniaturized semiconductor device enables the miniaturization and high integration of the semiconductor module in which the semiconductor device is incorporated. Further, since the semiconductor device has a high heat resistance, a radiation fin of a heatsink can be miniaturized and a water-cooled part can be air-cooled, which leads to further miniaturization of the semiconductor module. Further, since the semiconductor device has a low power loss and a high efficiency, a highly efficient semiconductor module can be achieved.

Third Embodiment

FIG. 8is a diagram illustrating an inverter according to a third embodiment. An AC-DC converter100converts AC power of a power supply101to DC power. The AC-DC converter100includes diodes D1, D2, D3and D4and a power supply smoothing capacitor C1. ADC-AC inverter102converts the DC power outputted from the AC-DC converter100to AC power and supplies the AC power to a coil of a motor103. The DC-AC inverter102includes switching devices Q1to Q6such as an IGBT and free-wheel diodes D5to D10connected in reverse parallel to the switching devices Q1to Q6. A drive circuit104drives the switching devices Q1to Q6. The drive circuit104includes a signal processing section105and an output section106. The signal processing section105includes a microcomputer107and signal processing circuits105ato105fthat process signals from the microcomputer107. The output section106includes output circuits106ato106fthat output control signals from the signal processing circuits105ato105fto the respective switching devices Q1to Q6. Using the semiconductor device according to the first or second embodiment as the switching devices Q1to Q6makes it possible to reduce the risk of causing thermal breakdown, and thereby obtain a highly reliable inverter.

The entire disclosure of Japanese Patent Application No. 2019-151898, filed on Aug. 22, 2019 including specification, claims, drawings and summary, on which the convention priority of the present application is based, is incorporated herein by reference in its entirety.