Semiconductor device and memory system

According to one embodiment, a semiconductor device includes receiving terminals on a surface of a substrate to receive first signals and transmitting terminals on the surface of the substrate to transmit second signals. The transmitting terminals are symmetrically positioned on the surface of the substrate with respect to the receiving terminals at a substantially 90 degree rotation about a rotation center position. The ordering of the transmitting terminals along the surface of the substrate from the rotation center position matches the ordering of the receiving terminals along the surface of the substrate from the rotation center position.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2021-154443, filed Sep. 22, 2021, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor device and a memory system.

BACKGROUND

Memory systems of certain types comprise electronic components mounted on a printed circuit board. In such memory systems, several communication chips or other electronic components are often interconnected as a ring daisy chain. Longer interconnections by a ring daisy chain generally causes an increase in power consumption and a reduction in a communication rate.

DETAILED DESCRIPTION

In general, according to one embodiment, a semiconductor device includes a plurality of receiving terminals on a surface of a substrate. The receiving terminals are configured to receive first signals. A plurality of transmitting terminals is on the surface of the substrate. The transmitting terminals are configured to transmit second signals. The plurality of transmitting terminals are symmetrically positioned on the surface of the substrate with respect to the plurality of receiving terminals at a substantially 90 degree rotation about a rotation center position. An ordering of the plurality of transmitting terminals along the surface of the substrate from the rotation center position matches an ordering of the plurality of receiving terminals along the surface of the substrate from the rotation center position.

Certain example embodiments will be described hereinafter with reference to the drawings.

First Embodiment

FIG.1is a block diagram illustrating a configuration of a memory system according to a first embodiment. As illustrated inFIG.1, a memory system1includes a plurality of communication chips11(four communication chips11A to11D) and a plurality of memory devices12(eight memory devices12A to12H) that are mounted on a memory module board10. The memory module board10is a printed circuit board in this example. The communication chips11A to11D are semiconductor devices connected by a ring daisy chain13. The memory system1is a semiconductor device formed on one substrate (e.g., printed circuit board, device card, etc.) and used in, for example, a memory card such as an SD card, an SSD (Solid State Drive), or a main memory of a computer-type device.

The memory system1is connected to a host31(on a mother board30) via a connection section20. The connection section20is configured to connect the memory system1to the mother board30and is implemented by, for example, a socket, a card edge connector, or a jumper cable. The host31is, for example, an electronic circuit device such as a processor, an ASIC (Application Specific Integrated Circuit) or an FPGA (Field Programmable Gate Array), or an electronic device incorporating such a processor or the like.

The communication chip11A is connected to the memory devices12A and12B. Likewise, the communication chip11B is connected to the memory devices12C and12D, the communication chip11C is connected to the memory devices12E and12F, and the communication chip11D is connected to the memory devices12G and12H.

Of the communication chips11A to11D, at least the communication chip11A includes an interface circuit for communicating with the host31via the connection section20. The host31may be an external host device in some instances. Each of the communication chips11A to11D has functions as a bridge device (bridge communication connection) and a memory controller. Each of the communication chips11A to11D is able to access any of the connected memory devices12A to12H in response to a request received from the host31.

The communication chips11A to11D are each directly connected to two of the memory devices12. It is noted that the disclosure is not limited to this example, and the communication chips11A to11D may be each connected to just one memory device12or three or more memory devices12. The communication chips11A to11D are each connected to at least one memory device12.

The memory devices12A to12H are, for example, NAND flash memories. The memory devices12A to12H may be other type semiconductor memories. For example, SRAM, DRAM, MRAM, or PRAM may be used the memory devices12A to12H.

FIG.2is an explanatory diagram of an example of a communication chip11according to the first embodiment. The communication chip11A will be described as representative of the communication chips11A to11D since each may have the same general configurations.

The communication chip11A includes a receiving terminal group RXG for the daisy chain13, a transmitting terminal group TXG for the daisy chain13, and a transmitting/receiving terminal group TRXG for communication with the host31.

The receiving terminal group RXG includes eight receiving terminals rx0to rx7disposed in an outermost edge portion on one side of the communication chip11A. The plurality of receiving terminals rx0to rx7receive a first signal. In this example, the pairs of receiving terminals rx0and rx1, rx2and rx3, rx4and rx5, and rx6and rx7are each a differential pair of terminals.

The transmitting terminal group TXG includes eight transmitting terminals tx0to tx7disposed in an outermost edge portion on another side of the communication chip11A. The plurality of transmitting terminals tx0to tx7transmit a second signal that can be different from the first signal. The pairs of transmitting terminals tx0and tx1, tx2and tx3, tx4and tx5, and tx6and tx7are each a differential pair of terminals. The side with the receiving terminal group RXG and the side with the transmitting terminal group TXG meet at a corner of the communication chip11A.

The transmitting/receiving terminal group TRXG includes four transmitting terminals TX0to TX3and four receiving terminals RX0to RX3disposed in an outermost edge portion on a side opposite to the side on which the receiving terminal group RXG is disposed. The communication chip11A communicates with the host31using four lanes (channels) for each of transmission and reception.

The receiving terminals rx0to rx7of the receiving terminal group RXG and the transmitting terminals tx0to tx7of the transmitting terminal group TXG are disposed in an order and a position relationship of rotation symmetry by 90 degrees with respect to each group about a rotation center position C that is virtually defined in the communication chip11A. That is, the transmitting terminals tx0to tx7are disposed at positions such that rotating about the rotation center position C by 90 degrees would cause the transmitting terminals tx0to tx7to respectively overlap (or substantially so) the receiving terminals rx0to rx7. The rotation center position C is a point on a straight line passing through centers of the receiving terminals rx0to rx7and near the corner portion of the communication chip11A. The rotation center position C is a virtual point on a surface on which the receiving terminals rx0to rx7and the transmitting terminals tx0to tx7of the communication chip11A are disposed. In the example ofFIG.2, the rotation center position C is provided on the communication chip11A so that the transmitting terminals tx0to tx7are disposed in the outermost edge portion of the communication chip11A. It is noted that when positions of the receiving terminal group RXG and those of the transmitting terminal group TXG are opposite from those illustrated inFIG.2, a point on a straight line passing through centers of the transmitting terminals tx0to tx7and near the corner portion of the communication chip11A is the rotation center position C.

In the present embodiment, arranging the receiving terminals rx0to rx7and the transmitting terminals tx0to tx7in the order and the position relationship of the rotation symmetry by 90 degrees makes it possible to optimize (ensure a shortest length, greatest linearity, and most equal length between different portions of) the daisy chain13on the memory module board10.

While each of the receiving terminal group RXG, the transmitting terminal group TXG, and the transmitting/receiving terminal group TRXG includes eight terminals in this example, the number of terminals is not limited to eight and may be greater than or less than eight. The number of terminals in the receiving terminal group RXG, the transmitting terminal group TXG, and the transmitting/receiving terminal group TRXG corresponds to the number of lanes (channels) of each communication chip11.

Furthermore, physical disposition of each of the receiving terminal group RXG, the transmitting terminal group TXG and the transmitting/receiving terminal group TRXG is not limited to that ofFIG.2and other dispositions may be adopted. For example, the transmitting/receiving terminal group TRXG may be disposed in an outermost edge portion on a side opposed to the side on which the transmitting terminal group TXG is disposed.

It is noted that a shape of each of the receiving terminal group RXG, the transmitting terminal group TXG, and the transmitting/receiving terminal group TRXG is not necessarily a rectangle as illustrated inFIG.2. The shape may be, for example, a circle, an oval, or a square. Moreover, it is often desirable that the terminals within each of the receiving terminal group RXG, the transmitting terminal group TXG, and the transmitting/receiving terminal group TRXG be apart from the other terminals.

While the receiving terminals rx0to rx7and the transmitting terminals tx0to tx7are disposed in the outermost edge portions of the communication chip11A, the disposition is not limited to this, and the receiving terminals rx0to rx7and the transmitting terminals tx0to tx7may be disposed in other ways on the communication chip11A, such as illustrated inFIG.3.

FIG.3is an explanatory diagram illustrating another example of a communication chip11according to the first embodiment. As illustrated inFIG.3, the receiving terminals rx0to rx7and the transmitting terminals tx0to tx7may be disposed at particular positions (offset from the outermost edge portions) of the communication chip11A but still with the 90 degrees rotational symmetry with respect to each other about the rotation center position C. The rotation center position C is still a point on a straight line passing through centers of the receiving terminals rx0to rx7and is near the corner portion of the communication chip11A, but not aligned to the corner as inFIG.2.

FIG.4illustrates a specific example of disposition of four communication chips11disposed on a memory module board10according to the first embodiment.

As illustrated inFIG.4, the communication chip11A is disposed on the memory module board10so that the transmitting/receiving terminal group TRXG of the communication chip11A is closest to the connection section20. Specifically, the communication chip11A is disposed at a position of an intersecting point between an X direction and a Y direction (intersecting point between an X-axis and a Y-axis) on the memory module board10ofFIG.4so that the transmitting/receiving terminal group TRXG of the communication chip11A are opposed to the connection section20.

The communication chips11B,11C, and11D are disposed counterclockwise from the communication chip11A in this order. That is, inFIG.4, the communication chip11B is disposed at a position offset in the X direction from the communication chip11A, the communication chip11C is disposed at a position in offset the Y direction from the communication chip11B, the communication chip11D is disposed at a position offset in the −X direction from the communication chip11C, and the communication chip11A is disposed at a position offset in the −Y direction from the communication chip11D.

The communication chip11B is rotated by 90 degrees counterclockwise with respect to disposition of the communication chip11A so that the transmitting terminals tx0to tx7of the communication chip11A are opposed to the receiving terminals rx0to rx7of the communication chip11B.

The communication chip11C is rotated by 90 degrees counterclockwise with respect to disposition of the communication chip11B so that the transmitting terminals tx0to tx7of the communication chip11B are opposed to the receiving terminals rx0to rx7of the communication chip11C.

The communication chip11D is rotated by 90 degrees counterclockwise with respect to disposition of the communication chip11C so that the transmitting terminals tx0to tx7of the communication chip11C are opposed to the receiving terminals rx0to rx7of the communication chip11D. The transmitting terminals tx0to tx7of the communication chip11D are thereby facing the receiving terminals rx0to rx7of the communication chip11A.

The memory system1of this example includes four communication chips11(11A to11D) each including the receiving terminals rx0to rx7and the transmitting terminals tx0to tx7. Each communication chip11according to the first embodiment includes the receiving terminals rx0to rx7and the transmitting terminals tx0to tx7that are disposed in the order and the position relationship of the rotation symmetry by 90 degrees with respect to each other about the virtual rotation center position C. Each communication chip11is disposed on the memory module board10so that the receiving terminals rx0to rx7thereof are facing the transmitting terminals tx0to tx7of an adjacent communication chip11. Each communication chip11is disposed on the memory module board10so that the transmitting terminals tx0to tx7thereof are facing the receiving terminals rx0to rx7of another adjacent communication chip11.

The memory system1can thereby ensure the smallest length, the highest linearity, and most equal length of connections in the ring daisy chain13connecting the communication chips11A to11D. As a result, the memory system1enables saving of power consumption of the memory module board10and an increase in a communication rate and/or stabilization of communication characteristics among the communication chips11A to11D.

Second Embodiment

FIG.5is a side view illustrating configurations of a memory system according to the second embodiment. Memory system1A illustrated inFIG.5has several components that are similar in configuration and function as those of memory system1. Such similar components in the first and second embodiments are denoted by same reference symbols.

The memory system1A includes four communication chips11(11E to11H) that are mounted on a memory module board10A, which can be a printed circuit board. The memory module board10A has a front (upper) surface10Aa and a back (lower) surface10Ab. The communication chips11E and11F are mounted on the front surface10Aa, and the communication chips11G and11H are mounted on the back surface10Ab. The four communication chips11E to11H are mutually connected by a ring daisy chain13.

Although not specifically illustrated inFIG.5, the memory devices12(seeFIG.1) with which the communication chips11E and11F communicate are mounted on the front surface10Aa, and the memory devices12with which the communication chips11G and11H communicate are mounted on the back surface10Ab.

FIG.6is an explanatory diagram of the communication chip11according to the second embodiment. The communication chip11E will be described as representative of communication chips11E to11H since each may have the same general configuration.

The communication chip11E includes a receiving terminal group RXG for the daisy chain13, a transmitting terminal group TXG for the daisy chain13, and a transmitting/receiving terminal group TRXG for communication with the host31.

The receiving terminal group RXG includes eight receiving terminals rx0to rx7disposed in an outermost edge portion on one side of the communication chip11E. The transmitting terminal group TXG includes eight transmitting terminals tx0to tx7disposed in an outermost edge portion on the same side with the receiving terminals rx0to rx7. The transmitting/receiving terminal group TRXG includes four transmitting terminals TX0to TX3and four receiving terminals RX0to RX3disposed in an outermost edge portion on a side different from the one side of the communication chip11E on which the receiving terminals rx0to rx7and transmitting terminals tx0to tx7are disposed. While depicted inFIG.6with the receiving terminal group RXG and the transmitting terminal group TXG disposed on a side opposite the transmitting/receiving terminal group TRXG, the receiving terminal group RXG and the transmitting terminal group TXG, in other examples, the transmitting/receiving terminal group TRXG need not be opposite the receiving terminal group RXG and the transmitting terminal group TXG.

The receiving terminals rx0to rx7of the receiving terminal group RXG and the transmitting terminals tx0to tx7of the transmitting terminal group TXG are disposed in an order and a position relationship with 180 degrees rotation symmetry with respect to each other about a rotation center position CA that is virtually defined in the communication chip11E. That is, the transmitting terminals tx0to tx7are disposed at positions rotating about the rotation center position CA by 180 degrees with respect to the receiving terminals rx0to rx7. The rotation center position CA is either a point on a straight line passing through centers of the receiving terminals rx0to rx7and near one side of the communication chip11E, or a point on a straight line passing through centers of the transmitting terminals tx0to tx7and near the one side of the communication chip11E. The rotation center position CA is a virtual point on a surface on which the receiving terminals rx0to rx7and the transmitting terminals tx0to tx7of the communication chip11E are disposed.

While the receiving terminals rx0to rx7and the transmitting terminals tx0to tx7are disposed in the outermost edge portion of the communication chip11E as illustrated inFIG.6, the possible examples are not limited to this, and the receiving terminals rx0to rx7and the transmitting terminals tx0to tx7may be positioned on the communication chip in other ways, such as illustrated inFIG.7, for example.

FIG.7depicts another example configuration of a communication chip11according to the second embodiment. As illustrated inFIG.7, the receiving terminals rx0to rx7and the transmitting terminals tx0to tx7may be disposed at particular positions of the communication chip11E with respect to each other about a rotation center position CB, which is not centered along an edge of the communication chip11and is furthermore offset from an outer edge towards the interior of the communication chip11.

FIG.8is a perspective view illustrating disposition of four communication chips11disposed on the memory module board10A according to the second embodiment.FIG.8is a partial exploded view.FIG.8illustrates that the communication chips11G and11H as taken off from the back surface10Ab of the memory module board10A, but this is for purposes of description only and the communication chips11G and11H are actually mounted on the back surface10Ab.

The communication chip11E is disposed on the front surface10Aa so that the side on which the transmitting/receiving terminal group TRXG of the communication chip11E is disposed faces the connection section20.

The communication chip11F is disposed on the front surface10Aa so that the receiving terminal group RXG and the transmitting terminal group TXG of the communication chip11F face the transmitting terminal group TXG and the receiving terminal group RXG of the communication chip11E.

The communication chip11G is disposed on the back surface10Ab so that the receiving terminal group RXG and the transmitting terminal group TXG of the communication chip11G are opposed to the transmitting terminal group TXG and the receiving terminal group RXG of the communication chip11F across the thickness of memory module board10A.

The communication chip11H is disposed on the back surface10Ab so that the receiving terminal group RXG and the transmitting terminal group TXG of the communication chip11H are opposed to the transmitting terminal group TXG and the receiving terminal group RXG of the communication chip11G. The communication chip11H is disposed so that the receiving terminal group RXG and the transmitting terminal group TXG of the communication chip11H are opposed to the transmitting terminal group TXG and the receiving terminal group RXG of the communication chip11E across the thickness of memory module board10A.

The memory system1A includes the four communication chips11(11E to11H) each including the receiving terminals rx0to rx7and the transmitting terminals tx0to tx7. Each communication chip11according to the second embodiment includes the receiving terminals rx0to rx7and the transmitting terminals tx0to tx7that are disposed to have 180 degrees rotational symmetry with respect to each other about the virtual rotation center position CA or CB. Each communication chip11is disposed on either the front surface10Aa or the back surface10Ab of the memory module board10A so that the receiving terminals rx0to rx7and the transmitting terminals tx0to tx7thereof are opposed to the transmitting terminals tx0to tx7and the receiving terminals rx0to rx7of either an adjacent communication chip11on the same surface or another communication chip11opposed across the thickness of the memory module board10A.

The memory system1A can thereby ensure the smallest length, the highest linearity, and the most equal length of connections in the ring daisy chain13connecting the communication chips11E to11H, similarly to the first embodiment. As a result, the memory system1A enables saving of power consumption of the memory module board10A and an increase in a communication rate and/or stabilization of communication characteristics among the communication chips11E to11H.

While the memory system1A according to the second embodiment includes four communication chips11E to11H mounted on the memory module board10A, the memory system1A may be configured so that just two communication chips11are mounted thereon. For example, the two communication chips11may be mounted on the front surface10Aa or the back surface10Ab of the memory module board10A so that the receiving terminals rx0to rx7and the transmitting terminals tx0to tx7of the two communication chips11are opposed to each other like the communication chips11E and11F or the communication chips11G and11H. Alternatively, for example, one communication chip11may be mounted on each of the front surface10Aa and the back surface10Ab of the memory module board10A so that the receiving terminals rx0to rx7of one of the two communication chips11are opposed to the transmitting terminals tx0to tx7of the other communication chip11across the thickness of memory module board10A like the communication chips11E and11H or the communication chips11F and11G.