Statistical sensitivity analyzer

A method including evaluating a configuration of a device for a selected device parameter and determining a value of the selected device parameter in a first optimal configuration that improves a performance of the device is provided. The method includes determining a sensitivity of the performance of the device relative to the value of the selected device parameter and determining a performance metric that differentiates the first optimal configuration with a second optimal configuration based on the sensitivity of the performance of the device. The method includes ranking the first optimal configuration and the second optimal configuration based on the performance metric and simulating the performance of the device with a second device parameter in one of the first optimal configuration or the second optimal configuration, based on the ranking. A system and a computer readable medium to perform the above method are also provided.

TECHNICAL FIELD

Embodiments described herein are generally related to the field of statistical analysis of integrated circuit designs. More specifically, embodiments described herein are related to methods for performing sensitivity analysis of integrated circuit designs including hardware and software.

BACKGROUND

Current integrated circuit (IC) design is largely dedicated to large systems integrating software and hardware to perform multiple tasks simultaneously, or almost simultaneously. Some of these designs include system on a chip (SoC) configurations, typically designed to execute different applications that compete for system resources (e.g., memory, processor time, and bus bandwidth). Due to the large number of operating parameters to consider, system designers typically explore obvious extreme parameter corners that may render inefficient design architectures. Moreover, some combinations of parameter values may be overlooked, resulting in system flaws that may be fatal in certain situations. Also, in some situations it may be desirable for a designer to choose a configuration from two different configurations with seemingly similar performance, that is more beneficial for a certain architecture. In such circumstances, it is desirable to have a tool that systematically and exhaustively explores the parameter space to find the areas where a distinction between two different configurations may be highlighted more clearly.

SUMMARY

In certain aspects, a computer-implemented method for analyzing a device performance is described. The computer-implemented method includes evaluating a configuration of a device for a selected device parameter and determining a value of the selected device parameter in a first optimal configuration of the device that improves a performance of the device. The computer-implemented method also includes determining a sensitivity of the performance of the device relative to the value of the selected device parameter and determining a performance metric that differentiates the first optimal configuration with a second optimal configuration for the device based on the sensitivity of the performance of the device. The computer-implemented method also includes ranking the first optimal configuration and the second optimal configuration of the device based on the performance metric and simulating the performance of the device with a second device parameter in one of the first optimal configuration or the second optimal configuration, based on the ranking.

In certain aspects, a system is described. The system includes a memory storing instructions, and at least one processor that executes the instructions to evaluate a configuration of a device for a selected device parameter and to determine a value of the selected device parameter in a first optimal configuration of the device that improves a performance of the device. The at least one processor further executes instructions to determine a sensitivity of the performance of the device relative to the value of the selected device parameter and to determine a performance metric that differentiates the first optimal configuration with a second optimal configuration for the device based on the sensitivity of the performance of the device. The at least one processor further executes instructions to determine a rank of the first optimal configuration and the second optimal configuration of the device based on the performance metric and to simulate the performance of the device with a second device parameter in one of the first optimal configuration or the second optimal configuration, based on the rank.

In certain aspects, a non-transitory, machine-readable storage medium is described that includes machine-readable instructions for causing a processor to execute a method. The method includes evaluating a configuration of a device for a selected device parameter and determining a value of the selected device parameter in a first optimal configuration of the device that improves a performance of the device. The method also includes determining a sensitivity of the performance of the device relative to the value of the selected device parameter and determining a performance metric that differentiates the first optimal configuration with a second optimal configuration for the device based on the sensitivity of the performance of the device. The method also includes ranking the first optimal configuration and the second optimal configuration of the device based on the performance metric and simulating the performance of the device with a second device parameter in one of the first optimal configuration or the second optimal configuration, based on the ranking.

In certain aspects, a system is described including a means for storing instructions. The system further includes a means to execute the instructions to evaluate a configuration of a device for a selected device parameter and to determine a value of the selected device parameter in a first optimal configuration of the device that improves a performance of the device. The means to execute the instructions further executes instructions to determine a sensitivity of the performance of the device relative to the value of the selected device parameter and to determine a performance metric that differentiates the first optimal configuration with a second optimal configuration for the device based on the sensitivity of the performance of the device. The means to execute the instructions further executes instructions to determine a rank of the first optimal configuration and the second optimal configuration of the device based on the performance metric and to simulate the performance of the device with a second device parameter in one of the first optimal configuration or the second optimal configuration, based on the rank.

In the figures, elements and steps denoted by the same or similar reference numerals are associated with the same or similar elements and steps, unless indicated otherwise.

DETAILED DESCRIPTION

General Overview

Embodiments disclosed herein include a statistical system analyzer (SSA) for providing sensitivity analysis of a system architecture (e.g., an SoC) using simulation data obtained with suitably combined parameters. SSA allows a designer to explore areas of a device parameter space to model the system architecture according to a specific environment. The environment may include physical environmental properties such as temperature, or user-related properties such as rate of use (e.g., data traffic, network conditions, and the like), and type of application. SoC designers make use of multiple input blocks including memories, processors, and the like, e.g., “third party intellectual property (IP).” Third party IP may be provided by multiple vendors and have device parameters that can be adjusted by the designer when assembling the multiple devices into an SoC. During assembly, in some embodiments the designer may use an application that configures the parameters for the different IPs to study the performance of the SoC to identify device parameters that may be changed, and how.

In some embodiments, and without limitation, a tool as disclosed herein also includes a software parameter for an SoC, such as logic commands, in addition to hardware properties (e.g., a compiler parameter). Compiler parameters may determine the type of executable program that runs the SoC, which may impact its performance. In some embodiments, a software parameter for an SoC may include a specific algorithm implementation to achieve the same result (e.g., the same type of hardware control or data processing). Further, in some embodiments software parameters may include different constants to, for instance, change the degree of accuracy, the precision, the amount of buffering, or the number of processes or threads in an application. In some embodiments, software parameters for an SoC may involve a tradeoff between speed, power requirements, resource footprint, signal-to-noise ratios, and the like, which the designer may desire to evaluate in detail. Further, software parameters for an SoC in embodiments consistent with the present disclosure may include a selection of whether to run an algorithm on a computer processing unit (CPU), or in a graphics processing unit (GPU). In this regard, the designer may desire to evaluate trade-offs between power requirements, performance, and complexity by selecting between CPU and GPU execution.

In SoC design, three types of properties available to the designer may be distinguished. A first type includes properties that can be directly configured (controllable properties) by the designer. For example, some controllable properties of a system may include the depth of a first-in-first-out (FIFO) buffer, or the clock frequency at which certain circuit component operates, or a bus bandwidth. The designer sets proper values for the controllable properties to optimize the design. A second type includes properties that the designer may desire to monitor during simulation (observable properties). Observable properties may describe the “quality” of the design. One example of an observable property may include the latency of a given operation (e.g., a command execution such as a read/write operation, or a logic operation, or a hardware reconfiguration), or a device bandwidth (e.g., usage of an IP for a selected operation or function). Without limitation, the designer may have no control as to the value of an observable property. Accordingly, the designer may set up quantitative measurements of the observable properties to collect data during simulation. A third type includes properties of the environment (environmental properties) in which the design is expected operate. The designer does not control these properties, (e.g., the use rate of the SoC and the like). In some embodiments, the environmental properties may be included in the SSA tool as test bench parameters to evaluate the performance of a SoC under different conditions.

In some embodiments, SSA tools use a system performance database obtained through a campaign of SoC simulations. Each simulation reports measurements for observable properties under a certain configuration of the design (controllable properties) operating in a certain configuration of the environment (environmental properties). Based on data collected from the measurements and stored in the system performance database, the SSA tool renders a statistical model of the system that highlights the dependency of the “observable” featured from the “environment” and “controllable” ones. The resulting data enables the designer to predict the system performance for different design choices (e.g., after certain assumptions about the environment). Accordingly, the SSA tool provides a profile of design parameters to achieve a desired performance of an SoC, including hardware and software.

Evaluating the design choices for hardware and software and their interactions for a system designer and evaluating Pareto optimality for the allocation of different resources across the SoC. A Pareto optimality defined for a performance metric is a device configuration wherein a change in any device parameter is likely to reduce the performance of the device relative to the selected metric. In some embodiments, the SSA tool optimizes certain property of the design and allows the designer to determine the sensitivity of the design to certain properties: refining the analysis on areas of the parameter space that have more impact on system performance. In some embodiments, an SSA tool may indicate to the designer certain areas of a device parameter space that may be desirable to explore with further SoC simulations.

In some embodiments, an SSA tool as disclosed herein enable the designer to compare multiple Pareto configurations in terms of a new parameter (e.g., power) to break a tie between two or more Pareto configurations.

The disclosed system addresses a technical problem tied to computer technology and arising in the realm of computer simulation of hardware, namely the technical problem of accurately analyzing the performance of an SoC having multiple device and software parameters. The disclosed system solves this technical problem by including a database of simulation results accessible through an application that enables the designer to select, de-select, refine and explore different areas of a device (and software) parameter space, to perform detailed statistical analysis form the selected data, and to request further simulations in refined areas of the device and software parameter space.

FIG. 1illustrates a system10configured to perform a statistical sensitivity analysis for an SoC, according to some embodiments. A client host102includes a processor12configured to execute instructions stored in a memory20. Memory20may include an application22, which includes commands that when executed by processor12cause client host102to perform methods consistent with the present disclosure. Application22may include a runtime software program running on client host102to issue commands to control an SSA tool100. For example, application22may include an application to control SSA tool100for SoC121. SoC121may include an RTL compiler language (e.g., an ASIC RTL file) configured to handle hardware and software that controls the hardware. Client host102may also include a communications module18that enables client host102to transfer data, provide commands and receive instructions from SSA tool100through a network150. Client host102may be coupled with an input device14(e.g., a mouse, a keyboard, a touch screen display, and the like) and to an output device16(e.g., a display, a speaker, and the like). Accordingly, a user of client host102may enter commands and queries to client host102with input device14, and receive graphic and other information from client host102via output device16. In some embodiments application22may control input device14and output device16through a graphic user interface (GUI), enabling a user to have access to SSA tool100and perform the SSA analysis on SoC121.

SSA tool100may include a memory30, a processor36, and a communications module38to transfer data, receive commands and provide instructions from client host102through network150. Analysis engine101includes a bottleneck analyzer103, and a sensitivity analyzer105.

A system performance database140stores data results from multiple simulation samples on SoC121run with SSA tool100. In some embodiments, system performance database140stores values of environmental properties, controllable properties, and observable properties resulting from multiple simulations of SoC121.

FIG. 2illustrates a block diagram of a statistical sensitivity analysis of SoC221, according to some embodiments. SoC221includes a software203to control a computer processing unit (CPU)201. CPU201executes commands from software203, reads data from, and writes data to, a memory220through a first bus210-1and a second bus210-2(hereinafter, collectively referred to as “buses210”). CPU201may also provide commands to, and exchange data with, a field processing unit (FPU)225. In addition, SoC221may include a first master processor205-1and a second master processor205-2(hereinafter, collectively referred to as “master processors205”). As can be seen, CPU201and master processors205compete for the resources and bandwidth in buses210, memory220, and FPU225.

Bottleneck analyzer103and sensitivity analyzer105are part of analysis engine101in SSA tool100as disclosed herein. Bottleneck analyzer103and sensitivity analyzer105enable the revision of multiple scenarios, or combinations of controllable, environmental, and observable properties. For example, bottleneck analyzer103may bring about configurations wherein more than one of CPU201or masters205attempt to access memory220, or FPU225, causing undue latency in the execution of certain operations. Likewise, sensitivity analyzer105may bring about configurations (e.g., one or more environmental properties) wherein at least one of the observable properties is characteristically sensitive to changes in one or more controllable properties.

In some embodiments, analysis engine101initially performs simulations over a limited sampling of the device (and software) parameter space with selected system configurations. In the simulations, given a system configuration, a random selection of data traffic is provided to SoC221and the results of the simulations are stored in system performance database140. For example, in some embodiments the random selection of data may include sets of video frames formed from random pixel values (e.g., when the SoC is a video-cam controller). In some embodiments, the simulations may include sets of video frames selected at random from other video frames or pictures available to SSA tool100. The results stored in system performance database140may include values of selected observable properties of the SoC. Based on the results, and using machine-learning techniques from prior simulation history stored in system performance database140, bottleneck analyzer103and sensitivity analyzer105select additional simulation configurations to provide a refined analysis. Accordingly, bottleneck analyzer103and sensitivity analyzer105increase the simulation and analysis efficiency by concentrating on areas of the parameter space for controllable and environmental properties that are critical for performance of SoC221(e.g., desirable ranges of one or more observable properties).

In some embodiments, analysis engine101is configured to determine one or more Pareto points, including ranges of values for controllable properties and environmental properties wherein the performance of SoC221is optimal, in terms of at least one observable property (e.g., a metric). Moreover, in some embodiments analysis engine101is configured to find a differentiating criterion between two or more competing Pareto points. For example, in some embodiments two Pareto points in different controllable and environmental ranges may provide similar performance of SoC221for one or more observable property, and analysis engine101may determine a high sensitivity of SoC221with respect to a third observable property, which may then be a “tie-breaker” for the two or more competing Pareto points.

SSA tool100may also be configured to observe multiple cost metrics to rank feasible solutions for the design of SoC221, including software203. In general, SSA tool100may be used as a stand-alone tool, in various platforms.

FIG. 3illustrates an SoC321configured to perform operations having a sensitivity for a selected performance parameter, according to some embodiments. Without limitation, SoC321includes two computer processing units (CPUs)301-0and301-1(collectively referred to, hereinafter, as “CPUs301”), and two memories320-0and320-1(collectively referred to, hereinafter, as “memories320”). Memories320may include volatile memories such as FIFO buffers, random access memories (RAMs) including dynamic RAMs (DRAMs), static RAMs (SRAMs), and the like. In some embodiments, memories320may also include non-volatile memories such as a flash memory, a disk memory (e.g., a hard drive), or any other magnetic device. CPUs301are coupled with memories320through buses310-0and310-1(collectively referred to, hereinafter, as “buses310”). A traffic source315injects traffic347(e.g., data) to be processed by either of CPUs301, and a traffic sink330removes data349form SoC321(e.g., to clear memories320, or to send data349to an external memory or other SoC). Without limitation, traffic source315injects data347into memory320-0. Thereafter, CPU301-0may access a data portion345from memory320-0, to perform a first operation (e.g., run a background function). Likewise, CPU301-1may access a data portion343from memory320-0to perform a second operation (e.g., run a first function independent of the background function).

As a result of the second function, CPU301-1may transfer a data341to memory320-1. Traffic sink330may periodically clear data349from memories320so that traffic source315may continue to load data347into SoC321.

In some embodiments, SSA tool100may include multiple rates at which traffic source315injects data347to memory320-0. Without limitation, SSA tool100may include three different injection rates for data347: “High,” “Medium,” and “Low” For exemplary purposes, and with no limitation a High injection rate may include a period of 20 microseconds (μs) for data injection, a Medium injection rate may include a period of 35 μs for data injection, and a Low injection rate may include a period of 50 μs for data injection. Further, SSA tool100may include tiered levels for controllable properties, as follows: A clock speed of CPU301-1may be tiered into three levels. For example, in some embodiments the clock speed of CPU may be selected from 200 megahertz (MHz), 300 MHz, and 500 MHz. Likewise, the SSA tool may include three levels for the buffer size of memory320-0. For example, in some embodiments SSA tool100may provide a selection of 2 kilobytes (KB), 4 KB, or 8 KB for the buffer size in memory320-0. The number of levels associated with the controllable properties of the SoC design may vary according to the desire of the designer and the computational capabilities of the device running SSA tool100. Moreover, the number of levels may be different for different controllable properties of the SoC (e.g., the buffer size in memory320-0may include five levels while the clock speed of CPU301-1may include ten levels).

SSA tool100may include a latency of the first function in CPU301-1as an observable property (or metric). In some embodiments, SSA tool100may identify the latency for the first function as the primary constraint. Further, in some embodiments the SSA tool may include the bandwidth of a socket coupled to memory320-0in bus310-1as a second observable property or metric. Moreover, in some embodiments SSA tool100may include the latency of the background function in CPU301-0as another observable property.

Accordingly, a SoC designer may use SSA tool100to address the frame rate of computation for the first function by SoC321under different environmental conditions. The SoC designer may then adjust the different controllable properties to verify the performance of the SoC, which may be focused on the frame rate for executing the first function.

FIG. 4illustrates a control panel422to set constraints401-1through401-5(hereinafter, collectively referred to as “constraints401”) in the performance metrics and select design properties in a statistical sensitivity analysis, according to some embodiments. Control panel422includes a field410that lists parameter values and ranges that are a concern (or desirable) for the designer. For example, a constraint401-1includes an application latency between 2 to 3 μs, at most. A checkmark indicates the boundary edge of the constrained range for the design property. A peak bandwidth constraint401-2may include a percentage between 0% to 16%, at most. A quietness constraint401-3may be desirably between 40% to 50%, at least. A peak latency401-4for an application (e.g., a background function), or an average latency for the application may be between 190 and 200 ns, at most.

In some embodiments, control panel422offers the designer the ability to select target features of the SoC to analyze, such as FIFO depth420-1or CPU clock frequency420-2(hereinafter, collectively referred to as “target features420”). Further, control panel422may also offer the designer the ability to select or de-select scenarios430. Accordingly a scenario may be determined by a value or a range of values for an environmental property, such as a traffic injection rate. For example, for an SoC configured to collect and process video frames from a camera, scenarios430may include traffic injection as the period of time lapsed between the receipt of each of the video frames (e.g., 20 μs, 35 μs, 50 us and longer). In some embodiments, control panel422offers the designer the ability to add or delete new scenarios430through an “Add” button435and a “Delete” button437.

As an example, a designer may be interested in the performance of SoC321wherein the latency401-1of the first function on CPU301-1is at most 3 μs: The designer may deselect constraints401-2through401-5. In this configuration all possible values may be considered for the observable properties of the SoC. Further, the designer may select both FIFO length420-1(e.g., the buffer depth of memory320-0) and a CPUCLK420-2(e.g., the clock speed of CPU301-1) as target features to adjust. Control panel422may further include a lock button440to fix the selected settings (e.g., target features420) for the simulation, and a save button445to store the setting for further use.

FIGS. 5A-Billustrate confidence windows522including distributions of performance values for a selected design parameter in SoC321, according to some embodiments.

FIG. 5Aincludes a confidence window522showing a field510including distributions of values for the selected design parameters in a field520. For example, in some embodiments the selected design parameter may include a FIFO depth of memory320-0may be set to 8 KB (e.g., the longest size for the buffer in memory320-0). The distributions in field510indicate a percentage of simulations conducted under the selected scenario (cf. scenario430) that meet the performance constraint chosen (e.g. latency401-1of the first function in CPU301-1less than 2 to 3 μs), for the environmental properties selected530-1and530-2(hereinafter collectively referred to as “environmental properties530”). Without limitation,530-1and530-2have been selected as generation periods of 20 μs and 35 μs, respectively (cf. scenario430). A filter field550allows the designer to select specific values420-1and420-2for the controllable properties when the designer clicks a “Filter” button525. With the CPUCLK box in filter field550unchecked, field510displays the distribution values of all the clock speeds of CPU301-1available (e.g., 200 MHz, 300 MHz, and 500 MHz).

For example, in a scenario530-1with traffic generation period of 20 μs, the first column in field510indicates that 97% of the simulations conducted produce a latency of the first function less than 2 to 3 μs when a CPU301-1clock operates at 500 MHz. Under the same scenario, for a CPU301-1running a 300 MHz clock, 27% of the simulations produce a latency of the first function less than 2 to 3 μs. And for a CPU301-1clock at 200 MHz, only 13% of the simulations produce a latency of the first function less than 2 to 3 μs.

Likewise, in a scenario530-2with traffic generation period of 35 μs (e.g., a somewhat more relaxed environment), the first column in field510indicates that 97% of the simulations conducted produce a latency of the first function less than 2 to 3 μs when a CPU301-1clock operates at 500 MHz. Under the same scenario, for a CPU301-1running a 300 MHz clock, 96% of the simulations produce a latency of the first function less than 2 to 3 μs. And for a CPU301-1clock at 200 MHz, only 21% of the simulations produce a latency of the first function less than 2 to 3 μs. Confidence window522includes a sliding scale517that the designer may adjust between minimum and maximum values (e.g., 0% and 100%, respectively), to qualify the values in field510as “pass” (e.g., displayed in a slanted hatch) or “fail” (e.g., displayed in vertical hatch). For example, the user may adjust sliding scale517to about 90% so that all the values in field510above 90% are displayed as “pass” conditions (e.g., in slanted hatch). Accordingly, all values in field510below 90% are displayed as “fail” conditions (e.g., in vertical hatch). Sliding scale517gives the designer a measure of confidence that certain property values satisfy a desired condition for the SoC.

In summary, SSA tool100unambiguously identifies a Pareto point at (BUFFER DEPTH, CPUCLK)=(8 MB, 500 MHz) for scenario530-1when the primary performance metric is the latency of the first function.

FIG. 5Bincludes confidence window522with similar characteristics asFIG. 5A, except that in filter field550, the FIFO depth420-1of memory320-0is set to a middle level of 4 KB. Likewise toFIG. 5A, the parameter constraint includes latency401-1of the first function in CPU301-1less than 2 to 3 μs. Also, field510includes distributions of values for the design parameters in field520, selected through filter button525in field550. Further, in scenario530-1(e.g., generation period of 20 μs), the first column in field510indicates that 28% of the simulations conducted produce a latency of the first function less than 2 to 3 μs when a CPU301-1clock operates at 500 MHz. Under the same scenario, for a CPU301-1running a 300 MHz clock, 8% of the simulations produce a latency of the first function less than 2 to 3 μs. For a CPU301-1clock at 200 MHz, only 2% of the simulations produce a latency of the first function less than 2 to 3 μs.

Likewise, in scenario530-2(e.g., generation period of 35 μs), the first column in field510indicates that 97% of the simulations conducted produce a latency of the first function less than 2 to 3 μs when a CPU301-1clock operates at 500 MHz. Under the same scenario, for a CPU301-1running a 300 MHz clock, 71% of the simulations produce a latency of the first function less than 2 to 3 μs. And for a CPU301-1clock at 200 MHz, only 5% of the simulations produce a latency of the first function less than 2 to 3 μs.

With the results shown inFIGS. 5A-B, a designer may conclude that for a higher traffic rate of about 20 μs (scenario530-1), SoC321may operate best with a FIFO depth of 8 KB in memory320-1, and a CPU301-1running a clock at 500 MHz. For a medium traffic rate of about 35 μs (scenario530-2), the designer may conclude that a FIFO depth of 8 KB in memory320-1, and a CPU301-1running a clock at 300 MHz is feasible. For scenario530-2(e.g., traffic rate of about 35 μs) the designer may conclude that a FIFO depth of 4 KB in memory320-1, and a CPU301-1running a clock at 500 MHz is also feasible. Accordingly, for a 35 μs traffic condition (scenario530-2) a designer may find two Pareto points. In such circumstances, the designer may use SSA tool100to refine the analysis of SoC321for different combination of target features420(FIFO depth420-1, CPUCLK420-2) and break the performance tie between the configurations (8 KB, 300 MHz) and (4 KB, 500 MHz).

SSA tool100provides several choices to the designer: for a traffic rate of 20 μs (scenario530-1), a FIFO depth420-1of 4 KB may be discarded for SoC321because the performance fails for any CPUCLK420-2(200 MHz, 300 MHz, and 500 MHz). The same holds under CPUCLK420-2below 300 MHz when FIFO depth420-1is 8 KB. For a traffic rate of 35 μs (scenario530-2), no further analysis is necessary for a FIFO depth420-1of 8 KB and a CPUCLK420-2above 300 MHz, because these combinations pass the performance test. Further, in scenario530-2, when FIFO depth420-1is 8 KB, SSA tool100may provide a direct solution to find more feasible solutions between 200 MHz (21% compliance=fail) and 300 MHz (96% compliance=pass, cf.FIG. 5A).

FIGS. 6A-Cillustrate confidence windows622to compare two Pareto points in the distributions of values for selected design parameter, according to some embodiments. Likewise toFIGS. 5A-B, a parameter constraint includes latency401-1of the first function in CPU301-1less than 2 to 3 μs. Also, a field610includes distributions of values for design parameters420-1and420-2in field520selected through filter button525in filter field550. Sliding scale517in confidence windows622gives the designer a measure of confidence that certain property values satisfy a desired condition for the SoC. The designer may be interested to find feasible solutions where FIFO size of memory320-0is medium (4 KB) and CPU301-1clock is 300 MHz. In the embodiments illustrated, in addition to scenarios530-1and530-2, a scenario630with slower traffic rate of 50 μs has been included as an environmental parameter to refine the analysis. To do this, the designer adds scenario630to scenarios430from control panel422(e.g., after clicking Add button435).

FIG. 6Aillustrates field610including a FIFO depth of 4 KB with CPUCLK420-2unchecked in filter550. In scenario530-1, with traffic generation period of 20 μs, field610indicates that 28% of the simulations conducted produce a latency of the first function less than 2 to 3 μs when a CPU301-1clock operates at 500 MHz. Under the same scenario, for a CPU301-1running a 300 MHz clock, 8% of the simulations produce a latency of the first function less than 2 to 3 μs. And for a CPU301-1clock at 200 MHz, only 2% of the simulations produce a latency of the first function less than 2 to 3 μs.

In a scenario530-2, with traffic generation period of 35 μs, field610indicates that 97% of the simulations conducted produce a latency of the first function less than 2 to 3 μs when a CPU301-1clock operates at 500 MHz. Under the same scenario, for a CPU301-1running a 300 MHz clock, 71% of the simulations produce a latency of the first function less than 2 to 3 μs. And for a CPU301-1clock at 200 MHz, only 5% of the simulations produce a latency of the first function less than 2 to 3 μs. And in a scenario630with traffic generation period of 50 μs, field610indicates that 97% of the simulations conducted produce a latency of the first function less than 2 to 3 μs when a CPU301-1clock operates at 500 MHz. Under the same scenario, for a CPU301-1running a 300 MHz clock, 90% of the simulations produce a latency of the first function less than 2 to 3 μs. And for a CPU301-1clock at 200 MHz, 22% of the simulations produce a latency of the first function less than 2 to 3 μs.

FIG. 6Billustrates field610including a FIFO depth of 2 KB with CPUCLK420-2unchecked in filter550. In scenario530-1, field610indicates that 7% of the simulations conducted produce a latency of the first function less than 2 to 3 μs when a CPU301-1clock operates at 500 MHz. Under the same scenario, for a CPU301-1running a 300 MHz clock, 5% of the simulations produce a latency of the first function less than 2 to 3 μs. And for a CPU301-1clock at 200 MHz, only 2% of the simulations produce a latency of the first function less than 2 to 3 μs.

In scenario530-2, field610indicates that 26% of the simulations conducted produce a latency of the first function less than 2 to 3 μs when a CPU301-1clock operates at 500 MHz. Under the same scenario, for a CPU301-1running a 300 MHz clock, 14% of the simulations produce a latency of the first function less than 2 to 3 μs. And for a CPU301-1clock at 200 MHz, only 2% of the simulations produce a latency of the first function less than 2 to 3 μs. And in scenario630, field610indicates that 53% of the simulations conducted produce a latency of the first function less than 2 to 3 μs when a CPU301-1clock operates at 500 MHz. Under scenario630, for a CPU301-1running a 300 MHz clock, 19% of the simulations produce a latency of the first function less than 2 to 3 μs. And for a CPU301-1clock at 200 MHz, 2% of the simulations produce a latency of the first function less than 2 to 3 μs.

In view of the above results, a designer may note that, in a scenario with a slow traffic rate of 50 μs, and operating at a CPUCLK=300 MHz, the probability to satisfy a latency of the first function less than 2 to 3 μs has changed dramatically from 90% to 19%, by reducing FIFO depth from 4 KB to 2 KB. Accordingly, the performance of SoC321in terms of first function latency is highly sensitive to the FIFO size in the above environment.

FIG. 6Cincludes a further results from SSA tool100, wherein the designer has unchecked FIFO depth tab420-1and has selected tab420-2for a CPUCLK speed of 300 MHz, in filter550. Field610indicates that, in scenario630, for a FIFO depth of 8 KB, 96% of the simulations satisfy latency constraint401-1. For a FIFO depth of 4 KB, 90% of the simulations satisfy latency constraint401-1. However, the probability of SoC321to satisfy latency constraint401-1is reduced to 19% for a FIFO depth of 2 KB. Accordingly, the latency performance sensitivity of SoC321to FIFO depth is high when the FIFO depth changes between 2 KB and 4 KB. However, the latency performance sensitivity is lower for a FIFO depth between 4 KB (90%) and 8 KB (96%).

Accordingly, in scenario630, (FIFO, CPUCLK)=(4 KB, 300 MHz) is a Pareto point, and a refined analysis may be avoided for FIFO depths higher than 4 KB and CPUCLK higher than 300 MHz. In scenario630, when CPUCLK=300 MHz, there may be more feasible solutions when FIFO depth is smaller than 4 KB. In scenario630, the performance sensitivity of SoC321to buffer depth is high. For example, the impact of buffer depth to the first function latency may be large.

FIGS. 7A-Dillustrate observe windows722with results in a sensitivity analysis for an additional performance metric, according to some embodiments. In some embodiments the performance metric may be defined by a parameter constraint including latency401-1of the first function in CPU301-1less than 2 to 3 μs. In some embodiments, the additional performance metric is a peak bandwidth usage711of memory320-0. A field710illustrates the analysis results with the additional performance metric for different scenarios430(e.g., scenario530-1, scenario530-2, and scenario630). In some embodiments, including the peak bandwidth of memory usage in field710may help a designer to break the tie (e.g., in scenario530-2), between the two Pareto points identified with (FIFO, CPUCLK)=(8 KB, 300 MHz) and (4 KB, 500 MHz). The difference between the two Pareto points in terms of peak bandwidth usage of memory320-0may be a tie breaking criterion.

To obtain the results in field710, SSA tool100searches in system performance database140the number of clock cycles of memory320-0used for transactions of CPU301-1(e.g., to implement first function) in each of a successive sequence of time windows, for a selected period of time. SSA tool100determines a maximum of this number each time CPU301-1executes the first function (in percent, relative to the total number of clock cycles of memory320-0during the selected period of time in the simulation). For a given first function latency, it may be desirable that the peak bandwidth usage of memory320-0be kept low, because the remaining clock cycles could be used by memory320-0to handle transactions other than those from CPU301-1(or transactions from CPU301-1other than the first function). Field710shows how this maximum number is distributed in the executions of the first function for the three scenarios430. A sliding scale717may be adjusted according to a performance of SoC321with respect to the additional performance metric.

Accordingly, and without limitation,FIGS. 7A-Blist three tiers of peak bandwidth usage711. Tier721indicates a range between 0% to 16% percent of peak bandwidth usage711. Tier723indicates a range between 16% to 33% percent of peak bandwidth usage711. Tier725indicates a range between 33% to 50% percent of peak bandwidth usage711.

FIG. 7Aillustrates the results in field710for the first Pareto point (8 KB, 300 MHz) in all three scenarios430(e.g., scenario530-1, scenario530-2, and scenario630). Field710shows that the majority of the simulations tend to tier723(slanted hatch background) of peak memory usage. Accordingly, in scenario530-1, 92% of the execution of the first function occupies 16%-33% of the clock cycles in memory320-0. In scenario530-2, 98% of the execution of the first function occupies 16%-33% of the clock cycles in memory320-0. In scenario630, 98% of the execution of the first function occupies 16%-33% of the clock cycles in memory320-0.

FIG. 7Billustrates the results in field710for the second Pareto point (4 KB, 500 MHz) in all three scenarios430(e.g., scenario530-1, scenario530-2, and scenario630). Field710shows that the majority of the simulations tend to tier725(slanted hatch background) of peak memory usage, leaving less availability to serve transactions for the other CPU, this tendency does not change much in the different scenarios530. Accordingly, for the second Pareto point in scenario530-1, 88% of the execution of the first function occupies 33%-50% of the clock cycles in memory320-0. In scenario530-2, 96% of the execution of the first function occupies 33%-50% of the clock cycles in memory320-0. And in scenario630, 96% of the execution of the first function occupies 33%-50% of the clock cycles in memory320-0.

To further enable a designer to make a choice between the two Pareto points,FIGS. 7C-Dlist seven tiers of additional performance metrics. In some embodiments, the additional performance metrics are, without limitation, a peak latency751c(cf.FIG. 7C) and an average latency751d(cf.FIG. 7D) for the performance of the background application (e.g., by CPU301-2).

To obtain the results inFIGS. 7C-D, SSA tool100searches in system performance database140for the execution time stamps of the background function, and determines the latency for each execution. SSA tool100determines a peak751cof the background function latency over a period when one iteration of the first function was executed in CPU301-1. Likewise, and using the same statistical sample, SSA tool100determines an average751dof the background function latency.FIG. 7Cshows how peak latency751cdistributes, andFIG. 7Dshows how peak latency751ddistributes, in the simulations for the two Pareto points.

FIG. 7CLists seven tiers of peak latency751cfor the background application. Tier731cindicates a peak latency751c(in nanoseconds, ns) between 190 ns and 200 ns. Tier733cindicates a peak latency751cbetween 200 ns and 210 ns. Tier735cindicates a peak latency751cbetween 210 ns and 220 ns. Tier737cindicates a peak latency751cbetween 220 ns and 230 ns. Tier739cindicates a peak latency751cbetween 230 ns and 240 ns. Tier741cindicates a peak latency751cbetween 240 ns and 250 ns. And tier743cindicates a peak latency751cof more than 250 ns. For the first Pareto point (8 KB, 300 MHz), field710indicates that in scenario530-2, 37% of the peak latency751cis within tier737c. For the second Pareto point (4 KB, 500 MHz), field710indicates that in scenario530-2, only 10% of the peak latency751cis within tier737c.

Further, SSA tool100provides a designer an indication that the second Pareto point (4 KB, 500 MHz) tends to increase the peak latency751cof CPU301-0. Further, there are instances when CPU301-0executes the background function without interference by CPU301-1: about 20% for (8 KB, 300 MHz, cf. peak latency739c), and 30% for (4 KB, 500 MHz, cf. peak latency739c); this tendency does not change much for different scenarios430.

FIG. 7D: Lists seven tiers of average latency751dfor the background application. In analogy withFIG. 7C: Tier731dindicates an average latency751d(in nanoseconds, ns) between 190 ns and 200 ns. Tier733dindicates an average latency751dbetween 200 ns and 210 ns. Tier735dindicates an average latency751dbetween 210 ns and 220 ns. Tier737dindicates an average latency751dbetween 220 ns and 230 ns. Tier739dindicates an average latency751dbetween 230 ns and 240 ns. Tier741dindicates an average latency751dbetween 240 ns and 250 ns. And tier743dindicates an average latency751dof more than 250 ns. For the first Pareto point (8 KB, 300 MHz), field710indicates that in scenario530-2, 33% of average latency751dis within tier735d, while only 4% is within tier737d. For the second Pareto point (4 KB, 500 MHz), field710indicates that in scenario530-2, 16% of average latency751dis within tier735d, while only 5% of the average latency751dis within tier737d.

Therefore, SSA tool100indicates to the designer that for the first Pareto point (8 KB, 300 MHz), CPU301-0could complete virtually all executions of its function within 220 ns (e.g., according to field710: 40%+14%+33%=87% on average, below 220 ns). For the second Pareto point (4 KB, 500 MHz), the latency of CPU301-0tends to be more spread out (e.g., 40%+9%+16%=65% on average, below 220 ns), influenced more sensitively by the activity of CPU301-1.

FIG. 8is a flow chart illustrating steps in a method800for evaluating multiple design architectures for a SoC (e.g., SoC121,221, or321), according to some embodiments. At least some of the steps in method800may be performed by a computer having a processor executing commands stored in a memory of the computer (e.g., client host102or SSA tool100, processors12or36, and memories20or30). In some embodiments, at least some of the commands may be stored as part of an SSA application installed in a computer (e.g., application22in client host102). Further, steps as disclosed in method800may include retrieving, editing, and/or storing files in a database that is part of, or is communicably coupled to, the computer (e.g., system performance database140). Methods consistent with the present disclosure may include at least some, but not all of the steps illustrated in method800, performed in a different sequence. Furthermore, methods consistent with the present disclosure may include at least two or more steps as in method800, performed overlapping in time, or almost simultaneously.

In some embodiments, at least one or more of the steps in method800may be performed in a cloud computing environment, wherein a computer may include servers, such as a master server and a slave server. Accordingly, at least some of the steps illustrated in method800may be performed in parallel in different processors, following separate computational threads. For example, each of the separate computational threads may be performed by at least one of slave servers in each of multiple applications and processors dedicated to the specific computational thread.

Step802includes evaluating a device configuration for a selected device parameter. In some embodiments, step802includes evaluating a design architecture for a selected parameter. In some embodiments, the device configuration includes a controllable property of a system on a chip and an environmental property of the system on a chip, and step802includes retrieving the device configuration from a system performance database. In some embodiments, the selected device parameter a logic command for a compiler, that provides an instruction to a system on a chip, and step802includes retrieving a result from the instruction to the system on a chip, the result stored in a system performance database. In some embodiments, step802includes executing multiple simulations of the device performance under multiple combinations of device parameter values including the value of the selected device parameter, and populating a system performance database with the device performance. In some embodiments, step802includes deselecting at least one device parameter from the device configuration based on the sensitivity of the device performance relative to the at least one device parameter. In some embodiments, step802includes evaluating a configuration for a selected rate of data injection to a system on a chip.

Step804includes determining a value of the selected device parameter in a first optimal configuration of the device that improves the performance of the device. In some embodiments, step804includes finding a value of the selected device parameter for a Pareto point. In some embodiments, step804includes finding a Pareto point for the selected parameter. In some embodiments, step804includes receiving a user selection of a pass and fail score for the value for an observable property, and displaying the value for the observable property according to the pass and fail score. In some embodiments, step804includes extracting performance metrics of interest from a system performance database for evaluating a configuration of the device with a selected device parameter.

Step806includes determining a sensitivity of the performance of the device relative to the value of the selected device parameter. In some embodiments, step806includes determining a combination of parameter values that does not affect the device performance. In some embodiments, step806includes determining a range of parameter values with a highly sensitive device performance. In some embodiments, step806includes selecting a device parameter for evaluating the device configuration based on the sensitivity of the device performance relative to a value of the device parameter.

Step808includes determining a performance metric (e.g., an observable property) that differentiates at least two otherwise optimal device configurations (e.g., the first optimal device configuration from a second optimal device configuration) based on the sensitivity of the performance of the device. In some embodiments, step808includes determining a parameter value that is a tie-breaker for other parameter values in the performance of the device.

Step810includes ranking the first optimal configuration and the second optimal configuration of the device based on the performance metric. In some embodiments, step810includes ranking multiple optimal configurations of the device based on a cost metric. In some embodiments, step810includes observing multiple cost metrics to rank optimal configurations of the device. In some embodiments, step810includes sorting a display of multiple optimal configurations of the device according to a desired value of the performance of the device.

Step812includes simulating the performance of the device with a second device parameter in one of the first optimal configuration or the second optimal configuration, based on the ranking. In some embodiments, step812includes identifying an area of a device parameter space to select the second device parameter based on the sensitivity of the performance of the device relative to the value of the selected parameter. In some embodiments, step812includes adding multiple simulations for configurations of the device from the identified area of the device parameter space (e.g., controllable properties and environmental properties). In some embodiments, step812may include identifying border areas in the device parameter space where the SoC performance is met (e.g., an observable property has a value within a selected constraint) near areas where the SoC performance is not met. In some embodiments, step812may also include identifying a selected area in the device parameter space with a high sensitivity of the SoC performance (e.g., where the SoC performance varies considerably between neighboring points in the area). Accordingly, step812includes determining more SoC simulations in the identified areas to add data to the database and perform a more accurate statistical analysis of the SoC.

FIG. 9is a flow chart illustrating steps in a method900for evaluating a statistical sensitivity in a design architecture of a SoC, according to some embodiments (e.g., SoC121,221, or321). At least some of the steps in method900may be performed by a computer having a processor executing commands stored in a memory of the computer (e.g., client host102or SSA tool100, processors12or36, and memories20or30). In some embodiments, at least some of the commands may be stored as part of an SSA application installed in a computer (e.g., application22in client host102). Further, steps as disclosed in method900may include retrieving, editing, and/or storing files in a database that is part of, or is communicably coupled to, the computer (e.g., system performance database140). Methods consistent with the present disclosure may include at least some, but not all of the steps illustrated in method900, performed in a different sequence. Furthermore, methods consistent with the present disclosure may include at least two or more steps as in method900, performed overlapping in time, or almost simultaneously.

In some embodiments, at least one or more of the steps in method900may be performed in a cloud computing environment, wherein a computer may include servers, such as a master server and a slave server. Accordingly, at least some of the steps illustrated in method900may be performed in parallel in different processors, following separate computational threads. For example, each of the separate computational threads may be performed by at least one of slave servers in each of multiple applications and processors dedicated to the specific computational thread.

Step902includes executing one or more simulations for a combination of one or more available design parameter values and one or more environment scenarios, and populating the database. In some embodiments, step902may include executing a command such as:$ cd platform_ssa

Assuming that a design for the SoC is under directory “./platform_ssa” (e.g., in memory20of client host102) including a “project.tcl” file that describes multiple device configurations. Accordingly, step902may include accessing a setup file using a command as follows:$source setup.csh

Step902may also include a command$ make sim_all_par BDW_JOBS=N

That simulates all device configurations from the file “project.tcl” on (at most) N parallel processes. In some embodiments, step902may include serial simulation of all device configurations from the file “project.tcl” with a “make sim_all” command.

In some embodiments, the results from the simulations in step902may be stored in the database, which is named “ssa.db” (for illustrative purposes only), using the command:$ make ssa

Step904includes extracting performance metrics of interest from the database to compile an input file (e.g. with a “.dat” extension). In some embodiments, step904may include forming a CSV file “ssa.dat”. Accordingly, step904may include launching the SSA application (from ./bin/ssa). Step904may include forming a reference “.dat” file in the package with a path./platform_ssa/demo_ssa_input/demo.dat

Step906includes starting the statistical sensitivity analysis. In some embodiments, step906may include selecting from the window of the SSA application in the client host computer the option “File→New.” Further, step906may include selecting the option “ssa.dat”→“Open” to open the data file including the simulations results for the SoC. The SSA application may issue a prompt “Do you want to load the feature configuration?” In some embodiments, the user may reply “No,” to create a new “.fea” file from scratch. Thereafter, the user may follow the GUI directions to proceed with the statistical sensitivity analysis.

Step908includes creating a “feature” file (e.g., with a “.fea” extension) that describes the metric parameters for statistical sensitivity analysis. A file “ssa.fea” is be generated in the local directory for future use. In some embodiments, the user may select “Open” when the “.fea” file is already available. A reference “.fea” file may be included in the package with a path./platform_ssa/demo_ssa_input/demo.fea

After clocking “No,” follow the SSA application. In step908, the user may check “Don't care” for any device parameter that should not be included in the analysis. In some embodiments, step908may also include marking the type of device parameter to be selected: a controllable property (e.g. FIFO, CPUCLK), an observable property (e.g. APP_LAT, PEAK_BW), or an environmental property (e.g. GenPeriod). Adjust the ordering of values (or mark feature as “Unordered”). In step908, the SSA application may allow values in the text box can be moved up and down by “Select & Drag.” In some embodiments, sorting the device parameter values may be desirable for the primary feasibility constraints, e.g.: Order APP_LAT from higher value (MORE) to lower (US_FROM_1_0_UPTO_2_0).

FIG. 10is a flow chart illustrating steps in a method1000for determining metrics and parameters for features in a design architecture of a SoC (e.g., SoC121,221, or321), according to some embodiments. At least some of the steps in method1000may be performed by a computer having a processor executing commands stored in a memory of the computer (e.g., client host102or SSA tool100, processors12or36, and memories20or30). In some embodiments, at least some of the commands may be stored as part of an SSA application installed in a computer (e.g., application22in client host102). Further, steps as disclosed in method1000may include retrieving, editing, and/or storing files in a database that is part of, or is communicably coupled to, the computer. Methods consistent with the present disclosure may include at least some, but not all of the steps illustrated in method1000, performed in a different sequence. Furthermore, methods consistent with the present disclosure may include at least two or more steps as in method1000, performed overlapping in time, or almost simultaneously.

In some embodiments, at least one or more of the steps in method1000may be performed in a cloud computing environment, wherein a computer may include servers, such as a master server and a slave server. Accordingly, at least some of the steps illustrated in method1000may be performed in parallel in different processors, following separate computational threads. For example, each of the separate computational threads may be performed by at least one of slave servers in each of multiple applications and processors dedicated to the specific computational thread.

Step1002includes selecting features desired for the analysis and deselecting undesired features. The features in step1002may include properties of the SoC that the designer may be interested on testing, as disclosed herein. For example, a buffer size, a clock speed, a bandwidth for a bus socket and the like.

Step1004includes selecting a type of the desired feature. In some embodiments, step1004includes selecting one of a controllable, observable, or environmental properties, as disclosed herein. Controllable property: a depth of a FIFO buffer (e.g. for a memory in the SoC). Observable property: a peak bandwidth of the memory socket on the bus. Environmental property: injection traffic rate, such as a camera frame rate for an SoC that controls a digital video camera. Another example of environmental properties may be the user selectable settings for the operating mode of an appliance or device (e.g., a smart phone, a camera, and the like) that includes the SoC. For example, an environmental property may include a user selection of picture resolution for an SoC in a digital camera, or a video frame rate selection for an SoC in a video camera (e.g., for surveillance video, or high definition video, and the like).

Step1006includes adjusting an order for display according to the values of the desired feature.

FIG. 11is a block diagram illustrating an example computer system1100with which the methods and steps illustrated in methods800-1000can be implemented, according to some embodiments. In certain aspects, computer system1100can be implemented using hardware or a combination of software and hardware, either in a dedicated server, integrated into another entity, or distributed across multiple entities.

Computer system1100includes a bus1108or other communication mechanism for communicating information, and a processor1102coupled with bus1108for processing information. By way of example, computer system1100can be implemented with one or more processors1102. Processor1102can be a general-purpose microprocessor, a microcontroller, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a Programmable Logic Device (PLD), a controller, a state machine, gated logic, discrete hardware components, or any other suitable entity that can perform calculations or other manipulations of information. In some embodiments, processor1102may include modules and circuits configured as a ‘placing’ tool or engine, or a ‘routing’ tool or engine, to place devices and route channels in a circuit layout, respectively and as disclosed herein.

Computer system1100includes, in addition to hardware, code that creates an execution environment for the computer program in question, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them stored in an included memory1104, such as a Random Access Memory (RAM), a flash memory, a Read Only Memory (ROM), a Programmable Read-Only Memory (PROM), an Erasable PROM (EPROM), registers, a hard disk, a removable disk, a CD-ROM, a DVD, or any other suitable storage device, coupled to bus1108for storing information and instructions to be executed by processor1102. Processor1102and memory1104can be supplemented by, or incorporated in, special purpose logic circuitry.

Computer system1100further includes a data storage device1106such as a magnetic disk or optical disk, coupled to bus1108for storing information and instructions.

Computer system1100is coupled via input/output module1110to various devices. The input/output module1110is any input/output module. Example input/output modules1110include data ports such as USB ports. The input/output module1110is configured to connect to a communications module1112. Example communications modules1112include networking interface cards, such as Ethernet cards and modems. In certain aspects, the input/output module1110is configured to connect to a plurality of devices, such as an input device1114and/or an output device1116. Example input devices1114include a keyboard and a pointing device, e.g., a mouse or a trackball, by which a user can provide input to the computer system1100. Other kinds of input devices1114are used to provide for interaction with a user as well, such as a tactile input device, visual input device, audio input device, or brain-computer interface device. For example, feedback provided to the user can be any form of sensory feedback, e.g., visual feedback, auditory feedback, or tactile feedback; and input from the user can be received in any form, including acoustic, speech, tactile, or brain wave input. Example output devices1116include display devices, such as a LED (light emitting diode), CRT (cathode ray tube), or LCD (liquid crystal display) screen, for displaying information to the user.

Methods as disclosed herein may be performed by computer system1100in response to processor1102executing one or more sequences of one or more instructions contained in memory1104. Such instructions may be read into memory1104from another machine-readable medium, such as data storage device1106. Execution of the sequences of instructions contained in main memory1104causes processor1102to perform the process steps described herein (e.g., as in methods800-1000). One or more processors in a multi-processing arrangement may also be employed to execute the sequences of instructions contained in memory1104. In alternative aspects, hard-wired circuitry may be used in place of or in combination with software instructions to implement various aspects of the present disclosure. Thus, aspects of the present disclosure are not limited to any specific combination of hardware circuitry and software.

In one aspect, a term field effect transistor (FET) may refer to any of a variety of multi-terminal transistors generally operating on the principals of controlling an electric field to control the shape and hence the conductivity of a channel of one type of charge carrier in a semiconductor material, including, but not limited to a metal oxide semiconductor field effect transistor (MOSFET), a junction FET (JFET), a metal semiconductor FET (MESFET), a high electron mobility transistor (HEMT), a modulation doped FET (MODFET), an insulated gate bipolar transistor (IGBT), a fast reverse epitaxial diode FET (FREDFET), and an ion-sensitive FET (ISFET).