Formation of holes in substrates using dewetting coatings

Methods and systems for forming holes in a substrate using dewetting coating are described herein.

TECHNICAL FIELD

Embodiments of the present invention relate to the field of electronic device manufacturing, more specifically, to methods and systems for forming holes in substrates.

BACKGROUND

In the current state of electronic device manufacturing, integrated circuits are commonly formed on and within multilayered substrates. During various stages of the formation of such substrates, cavities or holes are typically created in the substrates in order to form various electronic components including, for example, conductive interconnects such as vias. Currently, various approaches may be employed in order to form such holes including, for example, laser drilling.

Employing such techniques for creating holes, however, can be fairly expensive because of the cost of laser equipment and replacement of lasers and lenses. Further, such laser processes are relatively limited as they are limited to formation of holes having diameters that are 60 μm or greater. Furthermore, as electronic components become smaller and smaller and the density of such components in circuit substrate increases, the cost of employing such processes for forming holes have also increased.

DETAILED DESCRIPTION OF THE INVENTION

For the purposes of the present invention, the phrase “A/B” means A or B. For the purposes of the present invention, the phrase “A and/or B” means “(A), (B), or (A and B).” For the purposes of the present invention, the phrase “at least one of A, B and C” means “(A), (B), (C), (A and B), (A and C), (B and C) or (A, B and C).” For the purposes of the present invention, the phrase “(A)B” means “(B) or (AB),” that is, A is an optional element.

The description may use the phrases “in various embodiments,” or “in some embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present invention, are synonymous.

According to various embodiments of the present invention, methods and systems are provided for forming holes in a substrate using dewetting coatings. For the embodiments, a dewetting coating may refer to a coating that comprises a material that prevents other materials, with which it is incompatible, from adhering or attaching onto it. In some embodiments of the present invention, the holes that are formed may be substantially cylindrical in shape and have diameters less than or equal to about 50 μm, which are substantially impossible to form under the prior art, using e.g. laser technology. Such holes may, in some instances be used to form conductive interconnects such as vias.

In order to form one or more holes in a substrate, a substrate may be initially provided. In some embodiments of the present invention, the substrate may be a patterned substrate while in other embodiments the substrate may be an unpatterned substrate. Dewetting coating may then be placed at one or more selected locations on a surface of the substrate leaving one or more unselected locations of the surface of the substrate uncoated. A dielectric layer may then be deposited on the coated and uncoated locations of the surface of the substrate. After depositing the dielectric layer, one or more holes may be preliminarily formed in portions of the dielectric layer over the one or more selected locations with dielectric layer lips disposed around each of the one or more preliminarily formed holes. After the one or more holes are preliminarily formed, the dielectric layer lips may be removed in order to form one or more finalized holes. In some embodiments of the present invention, the holes may then be filled with conductive material to form one or more vias.

In various embodiments of the present invention, a system that includes, among other things, a coating unit, a deposition unit, a thermal unit, and an etching unit may be employed in order to form the holes as described previously. These and other aspects of embodiments of the present invention will be described in greater detail below.

FIGS. 1 to 8depict various stages of forming vias in a substrate by forming holes in the substrate using dewetting coating in accordance with various embodiments of the present invention. In particular,FIG. 1depicts a patterned substrate10with a surface14that includes conductive interconnects12. The phrase “conductive interconnect” as used herein refers to a broad range of conductive terminals such as vias, metal lines, traces, pads, and so forth. Note that the conductive interconnect12on the right side is elongated because it represents, for example, the side view of a metal line or trace. Although not depicted, in some embodiments of the present invention, the substrate10may include additional conductive interconnects and/or other electronic components.

FIG. 2depicts a stamp18placing dewetting coating16at selected locations on the surface14of the substrate10, while leaving unselected locations on the surface14of the substrate10uncoated. In particular, and as depicted, the dewetting coating16is stamped onto selected locations on the conductive interconnects12. In various embodiments of the present invention, the dewetting coating may comprise surfactants such as trimethoxysilane surfactants, thiol surfactants, alcohol surfactants, and so forth. Alternatively, the dewetting coating may comprise of alkoxysilanes such as octadecyltrichlorosilane, heptadecafluoro 1,1,2,2, tetrahydrodecyl trichlorosilane. In still other embodiments, the dewetting coating may comprise n-alkanethiol. In some embodiments, the dewetting coating may include nanomaterials such as silica and titania, dispersed in a solvent or a polymer matrix, wherein the polymer matrix may be an epoxy, a polyimide, a polyester, and so forth. In some alternative embodiments of the present invention, rather than using a stamp18to deposit the dewetting coating16at selected locations on the surface14of the substrate10, the dewetting coating16may be deposited by immersion coating and patterned by ultraviolet (UV) lithography.

In some embodiments of the present invention, prior to placing the dewetting coating16at selected locations on the surface14of the substrate10, the locations on the surface14of the substrate10where the dewetting coating16is to be placed may be initially roughened using, for example, a plasma etching process such as a Desmear process. This may, in some instances, facilitate the formation of holes above those locations in subsequent operations as will be described below.

Once the dewetting coating16has been placed at the selected locations, the stamp18is removed as depicted inFIG. 3. Next, a dielectric layer20may be deposited onto the selected (i.e., dewetting coating16) and unselected locations of the substrate10as depicted inFIG. 4. The dielectric layer20may be deposited such that the dielectric layer20has a substantially planar surface located opposite of the substrate10. A wide variety of methods may be used to deposit the dielectric layer20uniformly onto the substrate10including, for example, vacuum lamination, spin coating, and so forth. The dielectric layer20may comprise a polyimide, a polyester, a polyamide, a polyolefin, an epoxy, a bismaleimide, and so forth.

The substrate10may then be thermally treated to form, preliminarily, holes22in the portions of the dielectric layer20above the dewetting coating16as depicted inFIG. 5. If the selected locations were roughened as previously described, such roughing may facilitate the formation of the holes22. Formed along with the holes22are dielectric layer lips24around the holes22and on top of the dewetting coating16. The dielectric layer lips24may comprise the same material comprising the dielectric layer20and may protrude above the planar surface of the dielectric layer20and on top of the dewetting coating16. In various embodiments of the present invention, the temperature and the length of the thermal treatment may depend upon the compositions and thickness of the dielectric layer20and the dewetting coating16.

In some embodiments of the present invention, the holes22may be spontaneously generated by the thermal treatment. Alternatively, the formation of the holes22may be initiated using various methods. For example, in a first method, air may be blown over the entire substrate in order to initiate the hole formations. In a second method, air may be blown perpendicular to and directly at the points where hole formations are desired. The first two techniques may cause waves to form on portions of the dielectric layer20that is on top of the dewetting coating16, which may initiate the dewetting process. In a third method, capillary suction may be employed at the specified locations (i.e., at the portions of the dielectric layer20above the dewetting coating16). And in a fourth method, a pin may be used to poke or prick the specified locations. For the embodiments, these initiating procedures may be performed either just prior to the thermal treatment or during the thermal treatment.

After the preliminarily formations of the holes22, the dielectric layer lips24may be removed to form finalized holes22as depicted inFIG. 6. In some embodiments of the present invention, the removal of the dielectric layer lips24may include only the removal of the portions of the dielectric layer lips24protruding above the planar surface of the dielectric layer20, or alternatively, the removal of all of the dielectric layer lips24that is on top of the dewetting coating16as depicted inFIG. 6. The removal of the dielectric layer lips24may be needed in order to assure that the dielectric layer20is planarized and/or to remove the excess dielectric material on top of the dewetting coating16because such excess dielectric material may not attach very well to the underlying dewetting coating16and may eventually break off. Various methods may be used to remove the dielectric layer lips24including, for example, plasma etching such as a Desmear process.

Next, the dewetting coating16at the bottom of the holes22may be removed as depicted inFIG. 7. In some embodiments of the present invention, the dewetting coating16may be either washed away or evaporated away by exposing the dewetting coating16to UV light (e.g., if the dewetting coating16is made of material that reacts with UV light). Alternatively, if the dewetting coating16is not reactive to UV light, it may be removed using, for example, plasma etching. In still other alternative embodiments, the dewetting coating16may be left at the bottom of the holes22particularly if, for example, the dewetting coating16is made of material that is electrically conductive or if it is not necessary to have the bottom of the holes22be electrically conductive (e.g., if the holes to be formed are not for formations of vias that are to be coupled to underlying conductive interconnects).

After removing the dewetting coating16from the bottom of the holes22, the holes22may be filled with conductive material26to form vias (conductive terminals) as depicted inFIG. 8. In some embodiments, the formed vias may have diameters that are equal to or less than about 50 μm. The conductive material26used to fill the holes22may be one of a variety of materials including, for example, copper, aluminum, silver, gold, and so forth. Although the holes22are depicted as being completely filled, in alternative embodiments of the present invention, the holes22may only be plated with a conductive material26. Once the vias or conductive terminals are formed, additional patterning of the substrate10may be subsequently performed. Note that in alternative embodiments of the present invention and as previously described, the dewetting coating16may be left trapped at the bottom of the holes22underneath the conductive material26.

FIG. 9depicts a process that generally corresponds to the process described previously in accordance with various embodiments of the present invention. For the embodiments, the process100may begin when a substrate is patterned at102. After patterning the substrate, one or more selected locations on the substrate may be roughened at104. In some embodiments of the present invention, the one or more selected locations may be one or more selected locations located on the surfaces of conductive interconnects that may be disposed on the substrate.

Next, dewetting coatings may be placed at the one or more selected locations while leaving unselected locations on the substrate uncoated at106. A dielectric layer may then be deposited on the substrate on both the selected and unselected locations at108. The substrate may then be thermally treated to form, preliminarily, one or more holes in portions of the dielectric layer over the one or more selected locations at110. In various embodiments of the present invention, the hole formations may be initiated using one or more of various alternative methods (e.g., air blowing, capillary suction, and pin poking). In preliminarily forming the one or more holes in the dielectric layer, dielectric layer lips may form around the one or more holes and on top of the dewetting coating.

Subsequently, the dielectric layer lips may be removed to form one or more finalized holes at112. The dewetting coating at the one or more selected locations may then be removed from the bottom of the holes at114. A conductive material may then be deposited into the one or more holes to form one or more vias at116. After the one or more vias are formed, additional patterning of the substrate may be performed at118. Note that one or more of the above described operations such as the roughening of the selected locations and removing the dewetting coating may be eliminated from the process100in various alternative embodiments of the present invention. Further, additional operations may be included in the process100in other embodiments of the present invention. Although this process100is directed to the formation of holes for via formation, the general process for forming holes as described above may be applied to formation of holes for other purposes.

FIG. 10depicts a system for forming holes in accordance with various embodiments of the present invention. The system200includes a coating unit202, a deposition unit204, a thermal unit206, and an etching unit208, as shown. The system200may be adapted to implement the processes described above. For example, the coating unit202may selectively place a dewetting coating at one or more selected locations on a surface of a substrate while leaving one or more unselected locations of the surface of the substrate uncoated. The deposition unit204may then deposit a dielectric layer on the coated and uncoated locations of the surface of the substrate. The thermal unit206may then thermally treat the substrate to form preliminarily one or more holes in portions of the dielectric layer over the one or more selected locations with dielectric layer lips disposed around each of the one or more preliminarily formed holes. And the etching unit208may then remove the dielectric layer lips to contribute towards finalized formation of the one or more holes. In some embodiments of the present invention, the coating unit202is a stamping unit for stamping dewetting coating at the one or more selected locations on the surface of the substrate or an immersion coating and UV lithography unit for placing the dewetting coating at the one or more selected locations on the surface of the substrate.