One-time programmable memory array having small chip area

A memory cell includes a first select transistor, a first following gate transistor, an antifuse transistor, a second following gate transistor, and a second select transistor. The first select transistor has a first terminal coupled to a bit line, a second terminal, and a gate terminal coupled to a word line. The first following gate transistor has a first terminal coupled to the second terminal of the first select transistor, a second terminal, and a gate terminal coupled to a following control line. The antifuse transistor has a first terminal coupled to the second terminal of the first following gate, and a gate terminal coupled to an antifuse control line. The second following gate transistor and the second select transistor are disposed symmetrically to the first following gate transistor and the second select transistor with respect to the antifuse transistor.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a memory array, and more particularly, a one-time programmable memory array having small chip area.

2. Description of the Prior Art

Non-volatile memory (NVM) is a type of memory that retains information it stores even when no power is supplied to memory blocks thereof. Some examples include magnetic devices, optical discs, flash memory, and other semiconductor-based memory topologies. According to the programming times limit, non-volatile memory devices are divided into multi-time programmable (MTP) memory and one-time programmable (OTP) memory.

FIG. 1shows a conventional OTP memory array10of prior art. The memory array10includes a plurality of memory cells100, each including a select transistor110, a following gate transistor120and an antifuse transistor130. The select transistor110is used to select the memory cell to be programmed. To avoid the select transistor110from being broken down due to the high voltage when programming the memory cell100, the following gate transistor120is added between the antifuse transistor130and the select transistor110. When programming the memory cell100, the antifuse transistor130is ruptured and behaves as a metal-oxide-semiconductor capacitor, such that data of logic “1” can be written into the OTP memory cell100.

FIG. 2shows a layout of the OTP memory cells100. InFIG. 2, the two memory cells100are disposed in two different active areas AA1and AA2respectively. Also, due to the design rule of the layout, isolation structures, such as dummy poly PO and poly over diffusion edge PODE, are added between the active areas for the stability of the manufacturing process. Similarly, all the OTP memory cells100of the OTP memory array10are disposed in different active areas. Therefore, the dummy isolation structures can be found everywhere in the layout of the OTP memory array, which largely increases the chip area required by the OTP memory array10. Thus, how to use the chip area more efficiently and design a memory array with small chip area has become an issue to be solved.

SUMMARY OF THE INVENTION

One embodiment of the present invention discloses a memory cell. The memory cell includes a first select transistor, a first following gate transistor, an antifuse transistor, a second following gate transistor, and a second select transistor.

The first select transistor has a first terminal coupled to a bit line, a second terminal, and a gate terminal coupled to a word line. The first following gate transistor has a first terminal coupled to the second terminal of the first select transistor, a second terminal, and a gate terminal coupled to a following control line. The antifuse transistor has a first terminal coupled to the second terminal of the first following gate transistor, a second terminal, and a gate terminal coupled to an antifuse control line. The second following gate transistor has a first terminal coupled to the second terminal of the antifuse transistor, a second terminal, and a gate terminal coupled to the following control line. The second select transistor has a first terminal coupled to the second terminal of the second following gate transistor, a second terminal coupled to the bit line, and a gate terminal coupled to the word line.

Another embodiment of the present invention discloses a memory array. The memory array includes a plurality of memory cells, each includes a first select transistor, a first following gate transistor, an antifuse transistor, a second following gate transistor, and a second select transistor.

The first select transistor has a first terminal coupled to a bit line, a second terminal, and a gate terminal coupled to a word line. The first following gate transistor has a first terminal coupled to the second terminal of the first select transistor, a second terminal, and a gate terminal coupled to a following control line. The antifuse transistor has a first terminal coupled to the second terminal of the first following gate transistor, a second terminal, and a gate terminal coupled to an antifuse control line. The second following gate transistor has a first terminal coupled to the second terminal of the antifuse transistor, a second terminal, and a gate terminal coupled to the following control line. The second select transistor has a first terminal coupled to the second terminal of the second following gate transistor, a second terminal coupled to the bit line, and a gate terminal coupled to the word line. Memory cells disposed in a same column are disposed in a same active area.

DETAILED DESCRIPTION

FIG. 3shows a memory array20according to one embodiment of the present invention. The memory array20includes M×N memory cells2001,1to200M,N, where M and N are positive integers. Each memory cell2001,1to200M,Nincludes a first select transistor210, a first following gate transistor220, an antifuse transistor230, a second following gate transistor240, and a second select transistor250.

The memory cells2001,1to200M,Nhave similar structures and operation principles. For example, the first select transistor210of the memory cell2001,1has a first terminal coupled to a bit line BL1, a second terminal, and a gate terminal coupled to a word line WL1. The first following gate transistor220of the memory cell2001,1has a first terminal coupled to the second terminal of the first select transistor210of the memory cell2001,1, a gate terminal coupled to a following control line FL, and a second terminal. The antifuse transistor230of the memory cell2001,1has a first terminal coupled to the second terminal of the first following gate transistor220of the memory cell2001,1, a gate terminal coupled to an antifuse control line AF1, and a second terminal. The second following gate transistor240of the memory cell2001,1has a first terminal coupled to the second terminal of the antifuse transistor230of the memory cell2001,1, a gate terminal coupled to the following control line FL, and a second terminal. The second select transistor250of the memory cell2001,1has a first terminal coupled to the second terminal of the second following gate transistor240of the memory cell2001,1, a second terminal coupled to the bit line BL1, and a gate terminal coupled to the word line WL1.

Since the first select transistor210and the second select transistor250of the memory cell2001,1are coupled to the same word line WL1, the first select transistor210and the second select transistor250of the memory cell2001,1are operated simultaneously. Also, since the first following gate transistor220and the second following gate transistor240of the memory cell2001,1are coupled to the same following control line FL, the first following gate transistor220and the second following gate transistor240of the memory cell2001,1are operated simultaneously.

In addition, inFIG. 3, memory cells disposed in the same row are coupled to the same antifuse control line, the same following control line, the same word line, and different bit lines. For example, the memory cells2001,1to2001,Nare disposed in the same row, and memory cells2001,1to2001,Nare coupled to the same antifuse control line AF1, the same following control line FL, and the same word line WL1. Also, the memory cell2001,1is coupled to the bit line BL1while the memory cell2001,Nis coupled to the bit line BLN. Similarly, the memory cells200M,1to200M,Nare disposed in the same row, and memory cells200M,1to200M,Nare coupled to the same antifuse control line AFM, the same following control line FL, and the same word line WLM. Also, the memory cell200M,1is coupled to the bit line BL1while the memory cell200M,Nis coupled to the bit line BLN.

Furthermore, memory cells disposed in the same column are coupled to different antifuse control lines, different word lines, the same following control line, and the same bit line. For example, the memory cells2001,1to200M,1are disposed in the same column, the memory cell2001,1is coupled to the antifuse control line AF1and the word line WL1, while the memory cell200M,1is coupled to the antifuse control line AFMand the word line WLM. Also, the memory cell2001,1and the memory cell200M,1are coupled to the same the following control line FL and the same bit line BL1. Similarly, the memory cells2001,Nto200M,Nare disposed in the same column, the memory cell2001,Nis coupled to the antifuse control line AF1and the word line WL1, while the memory cell200M,Nis coupled to the antifuse control line AFMand the word line WLM. Also, the memory cell2001,Nand the memory cell200M,Nare coupled to the same the following control line FL and the same bit line BLN. In the present embodiment, memory cells2001,1to200M,Nare coupled to the same following control line FL, however, the memory cells2001,1to200M,Ncan still be operated independently by other control lines. Although memory cells disposed in different rows can be coupled to different antifuse control lines as shown inFIG. 3, in some embodiments of the present invention, the antifuse control lines AF1to AFMmay also be coupled together and be operated simultaneously.FIG. 4shows voltages of the control lines coupled to the memory cells2001,1to200M,Nduring the program operation of the memory cell2001,1. During the program operation of the memory cell2001,1, the word line WL1can be in a range from a first voltage V1to a second voltage V2, the following control line FL can be in a range from the second voltage V2to a third voltage V3, the antifuse control line AF1can be at the third voltage V3, and the bit line BL1can be at a fourth voltage V4.

The third voltage V3is greater than the second voltage V2, the second voltage V2is greater than the first voltage V1, and the first voltage V1is greater than the fourth voltage V4. In some embodiments, for memory array manufactured with the 16 nm process, the third voltage V3can be 5V, the second voltage V2can be 1.8V, the first voltage V1can be 0.8V, and the fourth voltage V4can be the ground voltage. However, in other embodiments, if the memory array is manufactured with other processes, the third voltage V3, the second voltage V2, the first voltage V1, and the fourth voltage V4may have different values according to the requirement.

During the program operation of the memory cell2001,1, the first select transistor210, the first following gate transistor220, the second following gate transistor240, and the second select transistor250of the memory cell2001,1are turned on. Therefore, the antifuse transistor230of the memory cell2001,1will be ruptured by the high voltage difference between the antifuse control line AF1and the bit line BL1, that is, the voltage difference between the third voltage V3and the fourth voltage V4.

Also, during the program operation of the memory cell2001,1, the memory cell2001,Ndisposed in the same row as the memory cell2001,1should not be programmed. Therefore, the bit line BLNcoupled to the unselected memory cell2001,Ncan be at the first voltage V1. In this case, the voltage difference applied to the antifuse transistor230of the memory cell2001,Nwill not be high enough to rupture the antifuse transistor230of the memory cell2001,Nand the memory cell2001,Nwill not be programmed.

Furthermore, during the program operation of the memory cell2001,1, the memory cell200M,1disposed in the same column as the memory cell2001,1should not be programmed. Therefore, the word line WLMcoupled to the unselected memory cell200M,1can be at the fourth voltage V4, and the antifuse control line AFMcoupled to the unselected memory cell200M,1can be at the fourth voltage V4. In this case, since the antifuse control line AFMis at a low voltage, the memory cell200M,1will not be programmed.

Also, although the voltage of the antifuse control line AF1may be different from the voltage of the rest of the antifuse control lines, such as the antifuse control line AFMas shown inFIG. 4during the program operation of the memory cell2001,1, the antifuse control lines AF1to AFMmay also be set to be at the same voltage in some embodiments of the present invention. That is, the antifuse control lines AF1to AFMcan be coupled together and be operated simultaneously. In this case, since the word line WLMis still at the fourth voltage V4, the unselected memory cell200M,1will not be programmed. Furthermore, the other unselected memory cells disposed in different columns from the memory cell2001,1, such as the memory cell200M,N, may apply the same operation as the memory cell2001,Nin this case.

FIG. 5shows voltages of the control lines coupled to the memory cells2001,1to200M,Nduring the read operation of the memory cell2001,1. During a read operation of the memory cell2001,1, the word line WL1is at a first voltage V1, the following control line FL can be at the first voltage V1, the antifuse control line AF1can be in a range from the first voltage V1to the second voltage V2, and the bit line BL1can be at a fourth voltage V4. In this case, the first select transistor210, the first following gate transistor220, the second following gate transistor240, and the second select transistor250of the memory cell2001,1are turned on so that the data stored in the antifuse transistor230of the memory cell2001,1can be read from the bit line BL1.

Also, during the read operation of the memory cell2001,1, the memory cell2001,Ndisposed in the same row as the memory cell2001,1may not be read. Therefore, during the read operation of the memory cell2001,1, the bit line BLNcoupled to the unselected memory cell2001,Ncan be at the first voltage V1. In this case, the first select transistor210, the first following gate transistor220, the second following gate transistor240, and the second select transistor250of the memory cell2001,Ncan be turned off so that the data stored in the antifuse transistor230of the memory cell2001,Nwill not be read from the bit line BLN.

Furthermore, during the read operation of the memory cell2001,1, the memory cell200M,1disposed in the same column as the memory cell2001,1should not be read. Therefore, during the read operation of the memory cell2001,1, the word line WLMcoupled to the unselected memory cell200M,1can be at the fourth voltage V4, and the antifuse control line AFMcoupled to the unselected memory cell200M,1can be at the fourth voltage V4. In this case, the first select transistor210and the second select transistor250of the memory cell200M,1can be turned off so that the data stored in the antifuse transistor230of the memory cell200M,1will not be read from the bit line BL1.

Also, although the voltage of the antifuse control line AF1may be different from the voltage of the rest of the antifuse control lines, such as the antifuse control line AFMas shown inFIG. 5during the read operation of the memory cell2001,1, the antifuse control lines AF1to AFMmay also be set to be at the same voltage in some embodiments of the present invention. That is, the antifuse control lines AF1to AFMcan be coupled together and be operated simultaneously. In this case, since the word line WLMis still at the fourth voltage V4, the unselected memory cell200M,1will not be read. Furthermore, the other unselected memory cells disposed in different columns from the memory cell2001,1, such as the memory cell200M,N, may apply the same operation as the memory cell2001,Nin this case.

In some embodiments, the memory array may support reverse read operations for reading the data in the memory cell.FIG. 6shows voltages of the control lines coupled to the memory cells2001,1to200M,Nduring the reverse read operation of the memory cell2001,1. During the reverse read operation of the memory cell2001,1, the word line WL1can be in a range from the first voltage V1to the second voltage V2, the following control line FL can be in a range from the first voltage V1to the second voltage V2, the antifuse control line AF1can be at the fourth voltage V4, and the bit line BL1can be in a range from the first voltage V1to the second voltage V2. In this case, the first select transistor210, the first following gate transistor220, the second following gate transistor240, and the second select transistor250of the memory cell2001,1are turned on so that the data stored in the antifuse transistor230of the memory cell2001,1can be read from the bit line BL1.

Also, during the reverse read operation of the memory cell2001,1, the memory cell2001,Ndisposed in the same row as the memory cell2001,1should not be read. Therefore, during the reverse read operation of the memory cell2001,1, the bit line BLNcoupled to the unselected memory cell2001,Ncan be at the fourth voltage V4. In this case, the first select transistor210, the first following gate transistor220, the second following gate transistor240, and the second select transistor250of the memory cell2001,Ncan be turned off so that the data stored in the antifuse transistor230of the memory cell2001,Nwill not be read from the bit line BLN.

Furthermore, during the reverse read operation of the memory cell2001,1, the memory cell200M,1disposed in the same column as the memory cell2001,1should not be read. Therefore, during the reverse read operation of the memory cell2001,1, the word line WLMcoupled to the unselected memory cell200M,1can be at the fourth voltage V4, and the antifuse control line AFMcoupled to the unselected memory cell200M,1can be at the fourth voltage V4. In this case, the first select transistor210and the second select transistor250of the memory cell200M,1can be turned off so that the data stored in the antifuse transistor230of the memory cell200M,1will not be read from the bit line BL1.

Also, in some embodiments, the antifuse control lines AF1to AFMcan be coupled together and be operated simultaneously during the reverse read operation of the memory cell2001,1. In this case, since the word line WLMis still at the fourth voltage V4, the unselected memory cell200M,1will not be read. Furthermore, the other unselected memory cells disposed in different columns from the memory cell2001,1, such as the memory cell200M,N, may apply the same operation as the memory cell2001,Nin this case.

Since the first select transistor210and the first following gate transistor220are operated simultaneously with the second select transistor250and the second following gate transistor240, the read current generated by each of the memory cells2001,1to200M,Nof the memory array20can be outputted to the corresponding bit line through two different paths. Therefore, the gate width of the first select transistor210, the gate width of the second select transistor250, the gate width of the first following gate transistor220, and the gate width of the second following gate transistor240can be smaller than the gate width of the select transistor110of prior art without affecting the driving ability. For example, by reducing the gate widths of the first select transistor210, the second select transistor250, the first following gate transistor220, and the second following gate transistor240by 50%, the two current paths formed by the first select transistor210, the first following gate transistor220, the second following gate transistor240, and the second select transistor250can still sustain the original driving ability.

FIG. 7shows structures of the memory cells2001,1and2002,1of the memory array20according to one embodiment of the present invention. The memory cells2001,1and2002,1have the same structures.FIG. 8shows a layout of the memory cells2001,1and2002,1of the memory array20.

InFIG. 7, the first select transistor210further includes a first source/drain extension region214coupled to the first terminal212of the first select transistor210and a second source/drain extension region216coupled to the second terminal218of the first select transistor210. The first source/drain extension region214and the second source/drain extension region216of the first select transistor210are disposed below the gate terminal210G of the first select transistor210.

The first following gate transistor220further includes a first source/drain extension region224coupled to the first terminal222of the first following gate transistor220, and a second source/drain extension region226coupled to the second terminal228of the first following gate transistor220. The first source/drain extension region224and the second source/drain extension region226are disposed below the gate terminal220G of the first following gate transistor220.

The antifuse transistor230further includes a first source/drain extension region234coupled to the first terminal232of the antifuse transistor230, and a second source/drain extension region236coupled the second terminal238of the antifuse transistor230. The first source/drain extension region234and the second source/drain extension region236of the antifuse transistor230are disposed below the gate terminal230G of the antifuse transistor230.

The second following gate transistor240includes a first source/drain extension region246coupled to the second terminal248of the second following gate transistor240, and a second source/drain extension region244coupled to the first terminal242of the second following gate transistor240. The first source/drain extension region246and the second source/drain extension region244are disposed below the gate terminal240G of the second following gate transistor240.

The second select transistor250includes a first source/drain extension region254coupled to the first terminal252of the second select transistor250and a second source/drain extension region256coupled to the second terminal258of the second select transistor250. The first source/drain extension region254and the second source/drain extension region256of the second select transistor250are disposed below the gate terminal250G of the second select transistor250.

Since the first terminal212of the first select transistor210and the second terminal258of the second select transistor250of the memory cell2001,1are both coupled to the bit line BL1, the memory cell2001,1can be disposed in the same active area AA with other memory cells that are coupled to the same bit line BL1. That is, memory cells disposed in the same column can all be disposed in the same active area. For example, since the memory cell2002,1to memory cell200M,1are also coupled to the bit line BL1, the memory cell2002,1to memory cell200M,1can also be disposed in the same active area AA as the memory cell2001,1.

By sharing the same active area, most of the isolation structures, such as dummy poly or poly over diffusion edge used in the prior art, can be saved, and the memory array20can use the area efficiently. Although each of the memory cells2001,1to200M,Nmay include more transistors than the memory cell100, the gate widths of the first select transistor210, the second select transistor250, the first following gate transistor220and the second following gate transistor240can be smaller than the gate widths of the select transistor110and the following gate transistor120of prior art. Therefore, the total chip area of the memory array20can still be reduced significantly. For example, the gate widths W200of the first select transistor210, the second select transistor250, the first following gate transistor220and the second following gate transistor240as shown inFIG. 8can be 50% smaller than the gate widths W100of the select transistor110and the following gate transistor120as shown inFIG. 2. In this case, the area of the memory array20can be 30% smaller than the memory array of prior art without deteriorating the driving ability.

In some embodiments of the present invention, the first select transistor210, the first following gate transistor220, the second following gate transistor240, and the second select transistor250are N-type metal-oxide-semiconductor transistors, and the antifuse transistor230is formed as a metal-oxide-semiconductor capacitor. In this case, the first terminal212and the second terminal218of the first select transistor210, the first terminal222and the second terminal228of the first following gate transistor220, the first terminal232and the second terminal238of the antifuse transistor230, the first terminal242and the second terminal248of the second following gate transistor240, the first terminal252and the second terminal258of the second select transistor250can be N-type doped sources or drains. Also, the source/drain extension regions214,216,224,226,234,236,244,246,254, and256can be N-typed doped regions having lower doping density than the sources and drains.

The source/drain extension regions can help to reduce the punch through effect. However, since two current paths of each of the memory cell2001,1to200M,Nare controlled by the first select transistor210, the second select transistor250, the first following gate transistor220and the second following gate transistor240, the punch through effect on the antifuse transistor230can be avoided by the select transistors and the following gate transistors without adding first source/drain extension region234and the second source/drain extension region236.

FIG. 9shows a structure of the memory cell300according to one embodiment of the present invention. The memory cells300and2001,1have similar structures. The main difference between the two memory cells is in that the memory cell300includes the first select transistor210, the first following gate transistor320, the antifuse transistor330, the second following gate transistor340, and the second select transistor250.

The first following gate transistor320includes the first source/drain extension region224coupled to the first terminal222of the first following gate transistor320, but does not include the second source/drain extension region226as the first following gate transistor220. The antifuse transistor330does not include the first source/drain extension region234and the second source/drain extension region236. Also, The second following gate transistor340includes the first source/drain extension region246coupled to the second terminal248of the second following gate transistor340, but does not include the second source/drain extension region244as the second following gate transistor240.

By removing the source/drain extension regions near the antifuse transistor330, the junction leakage current generated by the antifuse transistor330of the memory cell300can be reduced so as to reduce the power consumption of the memory cell300.

Since both the first terminal212of the first select gate210and second terminal258of the second select gate250of the memory cell300are still coupled to the bit line BL1, the memory cell300can be disposed in the same active area AA with other memory cells that are coupled to the same bit line BL1. That is, memory cells disposed in the same column can still be disposed in the same active area. Therefore, when using the memory cell300to replace the memory cells2001,1to200M,Nin the memory array20, the total chip area can still be smaller than the memory array of prior art.

Furthermore, in some embodiments, some of the source/drain extension regions can be replaced by modified source/drain extension regions having even lower doping density than the source/drain extension regions.FIG. 10shows a structure of the memory cell400according to one embodiment of the present invention. The memory cells400and2001,1have similar structures. The main difference between the two memory cells is in that the memory cell400includes the first select transistor210, the first following gate transistor420, the antifuse transistor430, the second following gate transistor440, and the second select transistor250.

The first following gate transistor420includes the first source/drain extension region224coupled to the first terminal222of the first following gate transistor420, and a modified source/drain extension region426coupled to the second terminal228of the first following gate transistor420. The first source/drain extension region224and the modified source/drain extension region426are disposed below the gate terminal220G of the first following gate transistor420.

The antifuse transistor430include a modified source/drain extension region434coupled to the first terminal232and the second terminal238of the antifuse transistor430. The modified source/drain extension region434is disposed below the gate terminal230G of the antifuse transistor430.

The second following gate transistor440includes the first source/drain extension region246coupled to the second terminal248of the second following gate transistor440, and a modified source/drain extension region444coupled to the first terminal242of the second following gate transistor440. The first source/drain extension region246and the modified source/drain extension region444are disposed below the gate terminal240G of the second following gate transistor440.

In this case, the antifuse transistor430is formed as an antifuse varactor. Also, since both the first terminal212of the first select gate210and second terminal258of the second select gate250of the memory cell400are still coupled to the bit line BL1, the memory cell400can be disposed in the same active area AA with other memory cells that are coupled to the same bit line BL1. That is, memory cells disposed in the same column can still be disposed in the same active area. Therefore, when using the memory cell400to replace the memory cells2001,1to200M,Nin the memory array20, the total chip area can still be smaller than the memory array of prior art.

FIG. 11shows a structure of the memory cell500according to one embodiment of the present invention. The memory cells500and2001,1have similar structures. The main difference between the two memory cells is in that the memory cell500includes the first select transistor210, the first following gate transistor520, the antifuse transistor530, the second following gate transistor540, and the second select transistor250.

InFIG. 11, the second terminal228of the first following gate transistor520, the first terminal232and the second terminal238of the antifuse transistor530, and the first terminal242of the second following gate transistor540are disposed in a well W1. In some embodiments, the first select transistor210, the first following gate transistor520, the second select transistor250, and the second following gate transistor540are formed by N-type metal-oxide-semiconductor field effect transistors, and the well W1can be an N-well.

In this case, the antifuse transistor530is formed as an antifuse varactor. Also, since both the first terminal212of the first select gate210and the second terminal258of the second select gate250of the memory cell500are still coupled to the bit line BL1, the memory cell500can be disposed in the same active area AA with other memory cells that are coupled to the same bit line BL1. That is, memory cells disposed in the same column can still be disposed in the same active area. Therefore, when using the memory cell500to replace the memory cells2001,1to200M,Nin the memory array20, the total chip area can still be smaller than the memory array of prior art.

In addition, in the memory array20, the gate oxide thickness of the gate terminal210G of first select transistor210, the gate oxide thickness of the gate terminal220G of first following gate transistor220, the gate oxide thickness of the gate terminal230G of antifuse transistor230, the gate oxide thickness of the gate terminal240G of the second following gate transistor240, and the gate oxide thickness of the gate terminal250G of the second select transistor250are substantially the same.

However, in some embodiments, since the select transistors and the following gate transistors may receive external signals, the select transistors and the following gate transistors may be formed as input/output devices, which are capable of enduring higher voltages, while the antifuse transistor may be formed as a core device, which has a lower voltage endurance. In this case, the gate oxide thickness of the select transistors and the gate oxide thickness of the following gate transistors may be greater than the gate oxide thickness of the antifuse transistor.

FIG. 12shows a structure of the memory cell600according to one embodiment of the present invention. The memory cells600and2001,1have the similar structures. The main difference between the two memory cells is in that memory cell600includes the first select transistor610, the first following gate transistor620, the antifuse transistor630, the second following gate transistor640, and the second select transistor650while the gate oxide thickness of the gate terminal of the first select transistor610, the gate oxide thickness of the gate terminal of the first following gate transistor620, the gate oxide thickness of the gate terminal of the second following gate transistor640, and the gate oxide thickness of the gate terminal of the second select transistor650are substantially the same and are greater than the gate oxide thickness of the gate terminal of the antifuse transistor630. In this case, the memory cell600can be operated with signals of higher voltage than the memory cell2001,1.

In summary, since each of the memory cells provided by the embodiments of the present invention can be coupled to the corresponding bit line through two different paths, the gate widths of the transistors of each memory cell can be reduced, and the memory cells coupled to the same bit line can be disposed in the same active region. Therefore, the total area of the memory arrays using the memory cells provided by the embodiments of the present invention can be significantly reduced without affecting the driving ability.