Intelligent riser testing device and methods

A solution is the iRiser. The iRiser is a PCIe riser, designed to work with SANBlaze test systems but capable of operation in any PCIe slot on any computer. The iRiser includes a dedicated ASIC or programmed FPGA that cycles any of 32 signals, including power and reset, and samples power at up to 1 million samples per second, to any connected PCIe devices (such as sixteen NVMe drives under test in a SANBlaze test system, or more if larger testing systems are used). This allows precise insertion of any signal, including power and reset, at any desired testing point, and precise measurement of power drawn during any test condition, including transitions such as power on/off, reset, and low power state returning to running state. The iRiser can write measurement data to a host controller through direct memory access, providing the data synchronized to precise test conditions with zero overhead.

BACKGROUND

Field of Technology

This relates to computer testing devices, and more specifically to monitoring power load of PCIe devices under test.

Background

SANBlaze produces SSD drive validation test systems, capable of simultaneously testing 16 NVMe drives. Current SANBlaze test systems measure power drawn by each device under test once per second. A higher granularity measurement is needed for precise monitoring during specific test conditions.

Existing solutions use FPGA boards to test SSD drives. They simultaneously test many drives, and push host processor performance to maximize testing capabilities. The existing solutions are capable of controlling power and reset testing, but are currently limited on the granularity of such testing due to processing limitations.

The existing solutions are also dedicated to testing SSD drives, and not directly expandable to test other similarly connectable devices.

What is needed, therefore, is a system and method that can simultaneously test multiple connected PCIe devices, precisely control signals including power and reset to those devices, and monitor power to each device under test in a way that is precisely synchronized with the test without adding overhead on a host processor of the testing device.

BRIEF SUMMARY

A solution is the iRiser. The iRiser is a PCIe riser, designed to work with SANBlaze test systems but capable of operation in any PCIe slot on any computer. The iRiser includes either a dedicated ASIC or programmed FPGA that cycles any of 32 signals, including power and reset, and samples power at up to 1 million samples per second, to any connected PCIe devices (such as sixteen NVMe drives under test in a SANBlaze test system, or more if larger testing systems are used). This allows precise insertion of any signal, including power and reset, at any desired testing point, and precise measurement of power drawn during any test condition, including transitions such as power on/off, reset, and low power state returning to running state. Further, the iRiser can write measurement data to a host controller through direct memory access, providing the data synchronized to precise test conditions with zero overhead.

DETAILED DESCRIPTION, INCLUDING THE PREFERRED EMBODIMENT

In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which are shown, by way of illustration, specific embodiments which may be practiced. It is to be understood that other embodiments may be used, and structural changes may be made without departing from the scope of the present disclosure.

Operation

Existing SANBlaze systems, such as the SANBlaze SBExpress-RM4, are dedicated systems for rapid high-scale simultaneous testing of multiple peripheral component interconnect express (PCIe) solid state drives (SSDs). These systems utilize internal field-programmable gate array (FPGA) cards, such as cards with the Xilinx 7 Series FPGA, configured for specific device testing. The solutions discussed herein may be implemented on these same FPGA cards to provide enhance testing capabilities, on different FPGA cards dedicated to testing different PCIe devices, on a PCIe riser card which may be added into the same test systems, or on a PCIe riser card which connects as an interposer into any PCIe slot on a computer motherboard, and into which a PCIe device or another PCIe card may connect, extending the testing capabilities to any PCIe device. Alternative to the FPGA cards, the same functionality may be implemented in a dedicate application specific integrated circuit (ASIC) card. The examples and discussion herein focus on a preferred embodiment through the PCIe riser (hereinafter referred to as the “card”), but the functionality remains the same across all possible cards. Referring toFIGS.1-3, in the preferred embodiment host system100is a test system configured to test PCIe devices. Card110connects to host system100, and in turn device under test120connects to card110.

In order to control different signals to the device under test, different general purpose input/output (GPIO) pins are configured. Each pin may control a different signal, including power and reset signals to the device under test. One example configuration may include 32 GPIO pins as in Table 1:

TABLE 1GPIO #GPIO Name0PERST port 01PERST port 12Disable 12 V3Enable refclk port 04Enable refclk port 15Serial Hot Plug Button port 06Serial Hot Plug Button port 17Power Disable to Drive8Port 0 present9Port 1 Present10Hold low to enable dual port11To drive connector pin 112To drive connector pin213Force present disable port 014Force present disable port 115Hold low to reset mi i2c16User_GPIO0 Pin1 User Connector17User_GPIO1 Pin2 User Connector18User_GPIO2 Pin3 User Connector19User_GPIO3 Pin5 User Connector20User_GPIO4 Pin6 User Connector21Front RED LED Lower22Front RED LED Upper24Enable slot to pex lane 025Enable slot to pex lane 126Enable slot to pex lane 227Enable slot to pex lane 328Enable pex to slot lane 029Enable pex to slot lane 130Enable pex to slot lane 231Enable pex to slot lane 3

The GPIO pins may be toggled between input and output. When in output mode, the value in each pin controls a specific signal to the device under test.

Referring also toFIG.4, power to each device under test may be measured400by an analog to digital (AtoD) converter (ADC) measuring voltage over a precision shunt resistor. With card clock speeds of 100 MHz or greater and current ADCs, this enables sampling410power at up to one million samples per second, with potential for faster sampling with further hardware development. To get this data to the host processor, the card may be configured to write420the ADC power samples into a dedicated physical memory buffer on the host system via direct memory access (DMA) writes. Memory registers on the card may be configured to store configuration for the host memory buffer, for example through a 64-bit base address, a 32-bit current offset, and a 32-bit buffer size as detailed in Table 2:

TABLE 2RegisterPurpose0x220-0x227DMA physical base address0x228-0x22bDMA current byte offset0x22c-0x22fDMA buffer max byte size

Each sample stored in the host system physical memory is 16-bytes long and logged into a 16-byte boundary. Different formats may be used, with a preferred format including a type identifier (indicating it is an ADC sample), followed by a wrap count (the number of times the writes to the memory buffer have wrapped around, if enabled), followed by the data (the ADC value), followed by a timestamp (the number of clock ticks since the card was booted). This format is illustrated in Table 3:

TABLE 30x0-0x0TYPE (0x80 for ADC sample)0x1-0x1WRAP COUNT (# of times the writes to memorybuffer have wrapped around, if enabled)0x2-0x3NOT USED0x4-0x7DATA (ADC value, little endian)0x8-0xfTIMESTAMP (number of clock ticks since devicewas booted, little endian)

With the power data written to host memory via DMA, it is available to the host processor without any increase in processing burden on the host processor. To be useful, the data needs to be connected to the specific tests applied to the device under test. Referring also toFIG.5, this is accomplished through control500of the power data sampling and synchronization with specific testing.

The power sample writing to host memory may be toggled510between two different modes. In continuous mode, the power samples are continuously written to host physical memory through DMA, and when the end of the allocated memory buffer is reached the sample writing wraps512back to the beginning of the buffer. As long as the host system reads the data from the buffer in intervals shorter than the time to fill the buffer, no power data is lost. In fast mode, samples are written into the memory buffer, and power sampling stops514once the buffer is full. This mode may be preferable when sampling around specific testing events. A specific register on the card may be dedicated to controlling power sampling, where bits may be set by the host system to enable or disable520power sampling, set specific mode510, set to clear530the sample data, and to toggle between standard and average sampling530. The clear data bit is preferably set520before data sampling begins (or resets), to clear data and start writing at the beginning of the memory buffer. Standard sampling mode may write every ADC sample, while average sampling may average consecutive samples on the card, and write that average sample to the host memory buffer. An example ADC state machine control register is detailed in Table 4:

Referring also toFIG.6, The sample data may be synchronized with testing through action commands performed by the card. For example, the ADC control register may be followed by a register holding a current action, and another register holding a next action. The action values may be written600directly into the action command registers by the host system, or may be written into RAM or series of registers on the card for sequential insertion into the action command registers. For example, 0x800-0xfff may be reserved as 128 “slots” holding 128-bit/16-byte action values. Each action value may be 16 bytes long, and may contain 610 output register data, direction register data, a counter before next action, a save slot number for input register value and next action slot number. An example action register is detailed in Table 5:

Finer integration control may be achieved by adding620a type to specific actions, and allowing different action types to control the power sampling through controlling the ADC as an alternative to controlling the GPIO pins. In this case, a “type” may modify how an action value is processed, with an example of such detailed in Table 6:

This fully integrates starting and stopping power sampling in between specific testing actions on any of the signals controlled by the GPIO pins. Test actions may be further enhanced by configuration630of a “glitch” bit, which may be the top bit in the counter register. With the glitch bit set, the action is loaded as normal, but when the counter expires the value on the GPIO pins reverts to their prior values from before the “glitch” action was loaded, and then the next action is loaded as normal. This allows inserting specific signal glitches at any point of any test program.