Stacked contact with low aspect ratio

An integrated circuit structure includes a semiconductor substrate; a metallization layer over the semiconductor substrate; a first dielectric layer between the semiconductor substrate and the metallization layer; a second dielectric layer between the semiconductor substrate and the metallization layer, wherein the second dielectric layer is over the first dielectric layer; and a contact plug with an upper portion substantially in the second dielectric layer and a lower portion substantially in the first dielectric layer. The contact plug is electrically connected to a metal line in the metallization layer. The contact plug is discontinuous at an interface between the upper portion and the lower portion.

TECHNICAL FIELD

This invention relates generally to integrated circuits, and more particularly to the formation of contact plugs connecting semiconductor devices and metallization layers.

BACKGROUND

In modern integrated circuits, semiconductor devices are formed on semiconductor substrates, and are connected through metallization layers. The metallization layers are interconnected to the semiconductor devices through contact plugs. Also, external pads are connected to the semiconductor devices through the contact plugs.

FIG. 1illustrates conventional plugs for connecting the semiconductor devices to the metallization layers. Transistor4, which symbolizes the semiconductor devices, is formed on semiconductor substrate2. Inter-layer dielectric (ILD)10is formed on the semiconductor devices. Contact plugs6are formed in ILD10to connect source and drain regions14and gate16of transistor4to metal lines7in metallization layer8. Typically, the formation of contact plugs6includes forming openings in ILD10, and then filling the openings with tungsten plugs. A single damascene is then performed to form metallization layer8.

With the increasing down-scaling of integrated circuits, the conventional contact plugs6experience shortcomings. While the horizontal dimensions, such as the width W of contact plugs6, are continuously shrinking, the thickness T of ILD10is not reduced accordingly to the same scale as width W of contact plugs6. Accordingly, the aspect ratio of contact plugs6continuously increases. This lack of proper scaling incurs several problems. For example, the top width W of contact plugs6is typically greater than the bottom width W′. Therefore, top corners of contact plugs6may be shortened, partially due to optical proximity effects and the inaccurate control of the etching processes. High aspect ratio also results in difficulties in the control of the bottom profile of contact openings, which in turn results in unexpected circuit degradation, and even device failure.

Accordingly, what is needed in the art is a new contact structure and formation methods for solving the above-discussed problems.

SUMMARY OF THE INVENTION

In accordance with one aspect of the present invention, an integrated circuit structure includes a semiconductor substrate; a metallization layer over the semiconductor substrate; a first dielectric layer between the semiconductor substrate and the metallization layer; a second dielectric layer between the semiconductor substrate and the metallization layer, wherein the second dielectric layer is over the first dielectric layer; and a contact plug with an upper portion substantially in the second dielectric layer and a lower portion substantially in the first dielectric layer. The contact plug is electrically connected to a metal line in the metallization layer. The contact plug is discontinuous at an interface between the upper portion and the lower portion.

In accordance with another aspect of the present invention, an integrated circuit structure includes a semiconductor substrate; a metallization layer over the semiconductor substrate; a first dielectric layer between the semiconductor substrate and the metallization layer; a second dielectric layer between the semiconductor substrate and the metallization layer, wherein the second dielectric layer is over the first dielectric layer; and a contact plug. The contact plug includes a lower portion substantially in the first dielectric layer; an upper portion substantially in the second dielectric layer, wherein the upper portion is electrically connected to a metal line in the metallization layer; and a diffusion barrier layer between and adjoining the lower portion and the upper portion of the contact plug.

In accordance with yet another aspect of the present invention, an integrated circuit structure includes a semiconductor substrate; a semiconductor device at a surface of the semiconductor substrate; an etch stop layer over the semiconductor device; a first dielectric layer over the etch stop layer; a first contact plug substantially in the first dielectric layer and in contact with the semiconductor device; and a dual damascene structure. The dual damascene structure includes a second contact plug physically connected to the first contact plug, wherein the second contact plug is in a second dielectric layer; a third dielectric layer over the second dielectric layer; and a metal line in the third dielectric layer, wherein the metal line and the second contact plug are continuously interconnected.

In accordance with yet another aspect of the present invention, a method for forming an integrated circuit structure includes providing a semiconductor substrate; forming a first dielectric layer over the semiconductor substrate; forming a lower portion of a contact plug substantially in the first dielectric layer; forming a second dielectric layer over the first dielectric layer; forming an upper portion of the contact plug substantially in the second dielectric layer, wherein the upper portion and the lower portion of the contact plug are physically connected; and forming a metallization layer over the second dielectric layer, wherein the metallization layer comprises a metal line electrically connected to the upper portion of the contact plug.

In accordance with yet another aspect of the present invention, a method for forming an integrated circuit structure includes providing a semiconductor substrate; forming a semiconductor device at a surface of the semiconductor substrate; forming an etch stop layer over the semiconductor device; forming a first dielectric layer over the etch stop layer; forming a first opening in the first dielectric layer, wherein a component of the semiconductor device is exposed through the first opening; filling the first opening with a conductive material to form a lower portion of a contact plug; forming a second dielectric layer over the first dielectric layer; forming a second opening in the second dielectric layer, wherein the lower portion of the contact plug is exposed through the second opening; filling the second opening with a conductive material to form an upper portion of a contact plug; forming a third dielectric layer over the second dielectric layer; forming a trench in the third dielectric layer; and filling the trench with a conductive material to form a metal line connecting to the upper portion of the contact plug.

The advantageous features of the present invention include reducing aspect ratio of contact plugs, and reducing top corner shortening of the contact plugs. The bottom profile of the contact plugs may also be improved.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

A novel stacked contact plug structure is provided. The intermediate stages of manufacturing a preferred embodiment of the present invention are illustrated. The variations of the preferred embodiment are then discussed. Throughout the various views and illustrative embodiments of the present invention, like reference numbers are used to designate like elements.

FIG. 2though9illustrate cross-sectional views of a first embodiment of the present invention. Referring toFIG. 2, substrate20is provided. Substrate20is preferably a semiconductor substrate, which may include single crystalline semiconductor materials such as silicon, or compound materials having commonly used group III, group IV and group V elements. Regions22are illustrated to symbolize semiconductor device components, which will be in contact with the subsequently formed contact plugs. Regions22may be source and drain regions (or the corresponding silicide regions) of transistors, contact pads of resistors, and silicide regions. Also, regions22symbolize contact regions formed over substrate20, such as gate electrodes, plates of capacitors, and corresponding silicide regions.

Etch stop layer (ESL)24is formed over substrate20and regions22. In an embodiment, ESL24includes silicon nitride. In other embodiments, ESL24includes other commonly used dielectric materials, such as silicon oxynitride, silicon oxycarbide, silicon carbide, and the like. A thickness T1of ESL24is preferably less than about 600 Å, and more preferably between about 200 Å and about 600 Å.

Inter-layer dielectric (ILD)26is formed over ESL24. In an embodiment, ILD26has a thickness T2of less than about 300 nm, and more preferably less than about 200 nm. The dielectric constant (k value) of ILD26is preferably less than about 4. Exemplary materials of ILD26include phosphosilicate glass (PSG), undoped silicon oxide, and other commonly used ILD materials.

For the patterning of ILD26and ESL24, photoresist30, and optionally antireflective coating (ARC) are formed. In an exemplary embodiment, photoresist30is formed on dielectric anti-reflective-coating (DARC)28. Photoresist30is then patterned. In alternative embodiment, top-anti-reflective-coating (TARC, not shown) may be formed on photoresist30.

FIGS. 3 and 4illustrate the forming and filling of contact openings32. Preferably, as shown inFIG. 3, an anisotropic etching removes portions of DARC28and ILD26, forming contact openings32. Exposed portions of ESL24are then removed through contact openings32, exposing underlying regions22. InFIG. 4, lower contact plugs34are formed. Preferably, lower contact plugs34include contact liners36and fillers38, which may be formed by depositing contact liners36on the bottom and sidewalls of contact openings32, followed by the filling of fillers38. Contact liners36preferably include TiN with a preferred thickness of less than about 50 Å. Fillers38preferably include tungsten, although other conductive materials such as aluminum, AlCu, copper, and the like may also be included.

FIGS. 5 through 9illustrate a dual damascene process. ESL40is first formed on ILD26and contact plugs34. ESL40may include silicon oxynitride, silicon oxycarbide, silicon carbide, and the like. Thickness T3of ESL40is preferably less than about 600 Å, and more preferably between about 200 Å and about 600 Å.

A dielectric layer42, which may include dielectric portion421and dielectric portion422, is formed over ESL40. In a first embodiment, dielectric portions421and422comprise the same materials, and are formed as a continuous layer. In other embodiments, dielectric portions421and422comprise the same or different materials, with an optional ESL44formed therebetween. Dielectric portion421preferably has a low k value, for example, less than about 3.5, although dielectric materials with higher k values may be used. Exemplary materials include PSG, undoped silicon oxide, fluorinated silicon glass (FSG), carbon-doped silicon oxide, organic low-k dielectric, and the combinations thereof. Further, the k value of dielectric portion421is preferably lower than the k value of ILD26. Thickness T4of dielectric portion421is preferably between about ½ and about ⅔ of the total thickness of T2, T3and T4, wherein the total thickness preferably equals to the desired ILD thickness for the existing formation technology. Exemplary thickness T4of dielectric portion421is preferably between about 1000 Å and about 2500 Å. The preferred formation methods of dielectric layer42include spin-on, chemical vapor deposition (CVD) or other known methods. Next, DARC48and photoresist50are formed.

Referring toFIG. 7, polymer54is filled into via openings52. Photoresist58is formed and patterned, which defines patterns for metal lines in the bottom metallization layer.FIG. 8illustrates the formation of trench openings60, for example, by etching, wherein trench openings60preferably have a width of less than about 65 nm. In the embodiment ESL44is formed between dielectric portions421and422, ESL44is used to stop the formation of trench openings60. Otherwise, time-mode is used to control the depth of trench openings60to a desired value.

The embodiment discussed in the preceding paragraphs uses a via-first approach, in which via openings52are formed before trenches60. In alternative embodiments, trench-first approach may be taken, in which trench openings60are formed before the formation of via openings52. One skilled in the art will realize the corresponding process steps.

Referring toFIG. 9, diffusion barrier layers62are formed in via openings52and trench openings60. Diffusion barrier layers62preferably comprise Ti, Ta, TiN, TaN, and the like. The remaining via openings52and trench openings60are then filled with conductive materials, preferably copper or copper alloys. A chemical mechanical polish is then performed to remove excess materials. The remaining portion of the conductive material forms upper contact plugs64and metal lines66. In the preferred embodiment, the resistivity of upper contact plugs64and metal lines66is lower than that of lower contact plugs34. In the resulting structure as shown inFIG. 9, metal lines66and dielectric portion422form the bottom metallization layer, typically referred to as M1. Upper contact plugs64and lower contact plugs34in combination form upper portions and lower portions of contact plugs, respectively.

FIGS. 10 through 13illustrate a second embodiment of the present invention, wherein single damascene processes are used to form upper contact plugs and the bottom metallization layer M1. The initial process steps are essentially the same as shown inFIGS. 2though4. Next, as shown inFIG. 10, ESL70, ILD72, DARC74and photoresist76are sequentially formed, wherein the thickness of ESL70and ILD72are preferably the same as thicknesses T3and T4as inFIG. 5, respectively. ILD72may include essentially the same materials as dielectric portion421(refer toFIG. 9). Photoresist76is then patterned.

Next, as shown inFIG. 11, contact openings78are formed, exposing lower contact plugs34. Width W2of contact openings78may be greater than, equal to, or smaller than width W1of lower contact plugs34, and both are preferably less than about 50 nm. Referring toFIG. 12, contact openings78are filled with conductive materials to form upper contact plugs, which include contact liners82and fillers84. Contact liners82may include either the same materials as contact liners36, or the same materials as diffusion barrier layers62(refer toFIG. 9), while fillers84may include the same materials as fillers38, or the same materials as metal lines66(refer toFIG. 9).

Next, as shown inFIG. 13, metallization layer86is formed using a single damascene process, wherein metal lines88are formed in the trenches of dielectric layer94. Preferably, metal lines88each include a diffusion barrier layer90and a copper line92. ESL96may be formed between dielectric layer94and ILD72.

FIG. 14illustrates an application of the embodiments of the present invention, which illustrates stacked contact plugs connected to source and drain regions of transistor100. Like reference numerals inFIG. 9are used to indicate like components inFIG. 14. The lower portions34of contact plugs electrically contact regions22, which include source and drain regions and a gate electrode. The upper portions64of the stacked contact plugs are stacked on lower portions34. Metal lines66are formed in metallization layer M1and are connected to contact plugs64.

It is noted that regardless whether the top portions of contact plugs are formed using single damascene processes or dual damascene processes, the top portions and bottom portions of the contact plugs are discontinuous at their interfaces. First, the discontinuity is resulted from diffusion barrier layers62(refer toFIG. 9) or contact liners82(refer toFIG. 13). Second, the materials of the upper portions and lower portions of the contact plugs may be different. In addition, even if the mask for forming the upper portions and lower portions have the same size, since contact plugs and vias are typically tapered, at the interfaces of the upper portions and lower portions of the contact plugs, the cross-sectional dimensions of the upper portions and lower portions of the contact plugs may be different, an exemplary embodiment is also shown inFIG. 14.

The embodiments of the present invention have several advantageous features. Since the contact plugs in the present invention are separated as lower portions and upper portions, the aspect ratios of the lower portions and upper portions are significantly lower than that of contact plugs formed in a single step. For example, with a contact plug having a height of about 3500 Å and a width of about 400 Å, the aspect ratio is about 8.75. With a thickness of about one half of 3500 Å, the aspect ratio is reduced to about 4.4. Accordingly, the problems related with the high aspect ratio, such as top corner shorting, uncontrollable bottom profiles, are at least reduced, and possibly eliminated.

An additional advantageous feature of the present invention is the reduction in parasitic capacitance. Since the contact plugs are separated as upper portions and lower portions, the parasitic capacitance between each of the contact plugs and corresponding neighboring plugs are divided into a top capacitance and a bottom capacitance connected in parallel. Since dielectric materials with lower k values than conventional ILDs may be used for the formation of upper portions of the contact plugs, the top capacitance is reduced. Accordingly, the entire capacitance between a contact plug and the respective neighboring contact plugs is reduced.