Semiconductor ESD device and method

An embodiment semiconductor device has a first device region disposed on a second device region within an ESD device region disposed within a semiconductor body. Also included is a third device region disposed on the second device region, a fourth device region adjacent to the second device region, a fifth device region disposed within the fourth device region, and a sixth device region adjacent to the fourth device region. The first and fourth regions have a first semiconductor type, and the second, third, fifth and sixth regions have a second conductivity type opposite the first conductivity type. An interface between the fourth device region and the sixth device region forms a diode junction. The first, second, fourth and fifth device regions form a silicon controlled rectifier.

TECHNICAL FIELD

This invention relates generally to semiconductor devices and methods, and more particularly to an ESD protection device and method.

BACKGROUND

As electronic components are becoming smaller and smaller along with the internal structures in integrated circuits, it is becoming easier to either completely destroy or otherwise impair electronic components. In particular, many integrated circuits are highly susceptible to damage from the discharge of static electricity. Generally, electrostatic discharge (ESD) is the transfer of an electrostatic charge between bodies at different electrostatic potentials or voltages, caused by direct contact or induced by an electrostatic field. The discharge of static electricity, or ESD, has become a critical problem for the electronics industry.

Device failures resulting from ESD events are not always immediately catastrophic or apparent. Often, the device is only slightly weakened but is less able to withstand normal operating stresses. Such a weakened device may result in reliability problems. Therefore, various ESD protection circuits are typically included in circuits to protect its various components.

Silicon Controlled Rectifier (SCR) or thyristor devices are commonly used for Electrostatic-Discharge (ESD) protection. On one hand, the SCR provides a compact and effective structure for conducting the very large currents that are associated with ESD events. One the other hand, SCR devices are prone to high leakage currents, particularly at high temperatures, high latchup sensitivity due to low holding voltages, and high triggering voltages.

A transistor's physical size limits the voltage that the transistor can withstand without being damaged. Therefore, as the geometries of the transistors that make up integrated circuits are reduced, there is a corresponding reduction in transistor breakdown voltage. As such, the high triggering voltage of the SCR device poses a difficulty in providing ESD protection for densely populated integrated circuits. Furthermore, as semiconductor circuits become more targeted toward very low power and low voltage applications, however, the high leakage currents associated with SCR devices poses difficulties with power sensitive applications.

SUMMARY OF THE INVENTION

In an embodiment, a semiconductor device has a first device region of disposed on a second device region within an ESD device region disposed within a semiconductor body. Also included is a third device region disposed on the second device region, a fourth device region adjacent to the second device region, a fifth device region disposed within the fourth device region, and a sixth device region adjacent to the fourth device region. The first and fourth regions have a first semiconductor type, and the second, third, fifth and sixth regions have a second conductivity type opposite the first conductivity type. An interface between the fourth device region and the sixth device region forms a diode junction. The first device region is coupled to a first ESD node and the fifth device region is coupled to a second ESD node. The first, second, fourth and fifth device regions form a silicon controlled rectifier.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The present invention will be described with respect to preferred embodiments in a specific context, namely a silicon controlled rectifier (SCR) ESD structure. The invention may also be applied, however, to other semiconductor structures.

FIG. 1aillustrates a known ESD protection device10. This circuit includes an SCR12that includes p-type anode18, n-type cathode24, n-type n-base SCR region20, and p-type p-base SCR region22. Anode18and trigger element30are coupled to a node to be protected16and reference node34, which is typically ground. The trigger element30causes trigger current ITRIG32to flow whenever the voltage at node16exceeds a certain threshold. Typical required trigger thresholds are between 1V and 20V. The presence of a trigger current ITRIG32causes the SCR to conduct a large current, IESD36.

FIG. 1bis an equivalent circuit representation of ESD protection device10in a non-conducting state where the voltage at node16is less than the threshold of the trigger device and the SCR is not conducting a large current IESD36. In the non-conducting state, the SCR can be modeled as a bipolar latch that includes bipolar junction transistor (BJT) PNP device40, and a BJT NPN device42. The representative PNP device is made up of the p-type anode18as the emitter, the n-base region20as the base, and p-base region22as the collector. The representative NPN device is made up of n-base region20as the collector, p-base region22as the base, and n-type cathode24as the emitter. When trigger current ITRIG32flows from the base of representative PNP40in response to a voltage transient at node16, the collector of the representative PNP40is pulled high, thereby turning on NPN42, which pulls the base of PNP40down toward the potential at reference node34. A large current IESD36then flows though the bipolar latch modeled by transistors40and42.

Turning toFIG. 1c, once the SCR12is latched, the SCR can be modeled as a forward biased PIN diode where the intrinsic region50includes n-base region20and p-base region22. When the SCR12is turned on IESD36will continue to flow even if ITRIG32is no longer applied. An SCR fabricated in a submicron process will typically conduct 10 mA to 100 mA per μm width. The SCR will stop conduction once IESD36falls below a holding current, typically 1 μA to 1 mA per μm of width.

FIG. 2aillustrates ESD protection device100according to an embodiment of the present invention. Protection device100has an SCR having anode18, n-type trigger region20, p-type trigger region22and n-type cathode24. In addition, protection device100has n-type region54adjacent to p-type trigger region22, where an interface between the n-type region54and p-type trigger region22forms diode junction51. The diode formed at this junction is referred to as a shield diode. Trigger element52is coupled to n-type trigger region56and n-type region54. Resistance Rsubrepresents a substrate resistance to ground. In some embodiments, resistance43is a parasitic resistance of a p-type substrate. In further embodiments, resistance43is a parasitic resistance of other p-type layers besides the substrate, such as a well, epitaxial layer, or other layer.

During the operation of ESD protection device100, trigger element52pulls n-type trigger region low, drawing current ITRIG1from the SCR. In addition, trigger element52pulls n-type region54high, which further reverse biases diode junction51. As the bias voltage of a diode junction changes, resistance Rsubchanges. In one embodiment, resistance Rsubincreases monotonically to the reverse bias of diode junction51. Furthermore, as the reverse bias across diode junction51increases, the magnitude of trigger current ITRIG1required to trigger the SCR decreases. In one embodiment the voltage across diode junction51is a reverse bias voltage. However, in alternative embodiments, diode junction51can be forward biased. In an embodiment, ESD protection device100having n-type region54and diode junction51triggers with a lower current than embodiments without n-type region54and diode junction51, such as the embodiment shown inFIG. 1a.

FIG. 2billustrates a circuit model of embodiment ESD protection device100. SCR57is modeled as representative PNP transistor40, NPN transistor42, diode41and substrate resistance43. In an embodiment, trigger element53activates the SCR device by pulling the base of representative PNP transistor40low, while trigger element55pulls the cathode of diode41high, thereby lowering trigger current ITRIG1.

FIG. 2dillustrates a circuit model of embodiment ESD protection device130. SCR68is modeled as representative PNP transistor40, NPN transistor42, diode49and substrate resistance47. In an embodiment, trigger element65activates the SCR device by pulling the base of representative NPN transistor42high, while trigger element63pulls the anode of diode49low, thereby lowering trigger current ITRIG1.

FIG. 3aillustrates embodiment ESD device having an SCR with n-type region54disposed adjacent to p-type trigger region22. N-type trigger region20of the SCR is coupled to the drain of NMOS device104, the gate of which is coupled to an RC network having capacitor102and resistor108. During an ESD event, when node151is pulled high, the gates of NMOS devices104and106are pulled high via capacitor102. NMOS device104sinks trigger current ITRIG1from n-type trigger region20of the SCR via the drain, and NMOS device106pulls n-type region54is pulled high via source. The action of both NMOS devices simultaneously draws trigger current ITRIG1from the SCR, while, at the same time, lowering trigger current ITRIG1. Some embodiments using MOS type trigger devices have a relatively much lower leakage current, particularly at elevated temperatures, compared to devices that do not employ MOS type trigger devices. One reason for the lower leakage is that NMOS devices104and106have a much lower leakage than some non-MOS trigger devices (i.e. diodes), when the ESD device is in an inactive state.

In an embodiment, the source of NMOS device106is coupled to n-type region54via resistor110and coupled to ground via resistor112. Trigger current ITRIG1can be adjusted by sizing resistors110and112. In one embodiment, a low trigger current ITRIG1is set by using a low value of resistance for resistor110, and a high value of resistance for resistor112. In some embodiments, the value for resistor110can be as low as zero ohms, and the value for resistor112can very high, using, for an example an open circuit. In a further embodiment, a high trigger current ITRIG1is set by using a large value for resistor110and a low value for resistor112. Furthermore, in case PN junction51is forward-biased by a positive potential at p-type region22with respect to n-type region54, the n-type54injects electrons into the substrate causing an undesired current path, which is suppressed by resistor110and112. In an embodiment, a further undesired current path into the source of NMOS106is suppressed by resistor110.

In an embodiment, the RC time constant of resistor108and capacitor102is about 20 ns, however, in alternative embodiments, a higher or lower time constant can be used. In one embodiment, capacitor102is about 2 pF and resistor108is about 10 KΩ. Alternatively, other values can be used for capacitor102and resistor108. In an embodiment, the RC time constant is chosen to be large enough to adequately couple the onset of an ESD event, yet be fast enough to recover from the ESD event once the ESD event has terminated. In a further embodiment, a separate RC circuit can be used for each of NMOS devices104and106.

In an embodiment, one or more series diodes120ato120nare coupled between node151and p-type anode18of the SCR. Each diode coupled in series causes a corresponding increase of the trigger voltage of ESD device150. In alternative embodiment, series diodes120ato120ncan be omitted.

In an alternative embodiment, the other device types besides NMOS can be used, for example PMOS, BJTs, JFETS, and other transistors types. Furthermore, in an alternative embodiment, the polarity of the SCR device and or the supporting devices can be inverted. For example, inFIG. 3b, ESD device160having with an SCR device having a p-type region58adjacent to the n-type trigger region20can be used. In such as case, the adjacent p-type region58is pulled low by PMOS source follower154, and p-type trigger region22is pulled high by PMOS transistor156during an ESD event. Substrate resistor159represents the resistance Rsub of an n-type layer and/or substrate. Similar toFIG. 3a, values of resistors153and158can be chosen to adjust the trigger current of ESD device160.

FIG. 3cillustrates ESD device170according to an alternative embodiment of the present invention. The embodiment ofFIG. 3cis similar to the embodiment ofFIG. 3a, except that n-type region54is coupled to ground via resistor114instead of being driven by a transistor. During an ESD event, the potential of n-type region54is at ground, the intrinsic depletion zone of the junction builds up and reaches deep into the substrate, thereby lowering the trigger current of ESD device170. In some embodiments, the shield diode can be even forward biased during triggering. In one embodiment, the n-well of the shield diode increases the resistance of the p-well/p-substrate by reducing its effective cross-section. In an embodiment, the trigger current of ESD device170is lowered by adjusting the resistance of resistor114.

FIG. 3dillustrates ESD device180according to another embodiment of the present invention. The embodiment ofFIG. 3dis similar to the embodiment ofFIG. 3a, except that n-type region54is coupled directly to capacitor102and resistor108instead of through a transistor.

FIG. 3eillustrates ESD device190according to a further embodiment of the present invention. The embodiment ofFIG. 3eis similar to the embodiment ofFIG. 3a, except that the n-type region54is coupled to node151via resistor116. Here, n-type region54is pulled high directly from node151during an ESD event, thereby reducing the trigger current of the SCR device.

FIG. 4aillustrates a layout view of SCR200according to an embodiment of the present invention. The anode of the SCR device is formed by p+ regions202and203, the n-type trigger region is formed by n-well205, the p-type trigger region is formed by is formed by p-well210, the n-type cathode is formed by n+ region206, and the adjacent n-type region is formed by n-well208. Contact can be made to n-well208via n+ region214. Here, a diode junction is formed at the boundary of n-well208and p-well210, as well as at a boundary of n-well208and a p-type substrate beneath the n-well (not shown). An optional substrate ring formed by p+ region212surrounds the active portion of SCR200. Anodes202and203, trigger contact204, cathode206and optional substrate ring212have contacts on the upper surface of these regions. Only the contacts216on optional substrate ring212are shown for clarity, however, it should be noted all of these regions can have contacts. In an embodiment, contacts to anode regions202and203are coupled to a node to be protected, cathode region206is coupled to ground, and trigger contact region G2and n-type region208are coupled to a trigger device. For the sake of clarity of explanation herein, anode regions202and203has further been labeled A, trigger contact region204is labeled G, cathode region206is labeled C, and n-type region208is labeled D.

It should be noted that the embodiment layout ofFIG. 4ais just one example of a layout of an embodiment ESD device. Alternative embodiments can be arranged differently with respect to dimensions and placement of the various regions, as well as the number of each of the various regions. For example, some embodiments may employ a single anode region or multiple anode regions. Some alternative embodiments may also employ multiple cathode regions and shield diode regions.

In an embodiment, N-type cathode region206and trigger region204are made from an n-type source/drain implant. In some embodiments, the cathode region206and trigger region204have the same doping so that cathode region206and trigger region204can be implanted at the same mask and processing step. For example, Arsenic ions can be implanted with a dose of about 1×1014cm−2to about 5×1021cm−2and an implant energy between about 10 keV and about 50 keV. In other embodiments, other materials, such as Phosphorus, can be implanted. The resulting doping concentration for these n-type regions is typically greater than 1021cm−3. In an alternative embodiment, cathode region206and trigger region204can be implemented in separate steps.

In an embodiment, p-type anode202and203and optional substrate ring212are made from a p-type source/drain implant. For example, boron ions can be implanted with a dose of about 5×1013cm−2to about 5×1021cm−2and an implant energy between about 5 keV and about 50 keV. In other embodiments, other materials, such as BF2, can be implanted. The final doping concentration for these p-type regions is typically greater than 1021cm−3. Again, these p-type regions are preferably implanted at the same mask step. Alternatively, these regions may be implanted during different mask steps.

A portion of the top surface of anode regions202and203, cathode region206, optional substrate ring212, and shield diode contact region214include silicided regions224on top of which contacts (not shown) are fabricated. These silicided regions are fabricated using conventional techniques.

In an embodiment, p-wells210and n-wells205and208are first fabricated in a p-type substrate201of a semiconductor wafer. N-type cathode region206, n-type trigger region204, n-type shield diode contact region214, p-type anode202and203and p-type optional substrate ring212are then fabricated within these wells as shown inFIGS. 4band4c. Silicide224is formed on the surface of N-type cathode region206, n-type trigger region204, n-type shield diode contact region214, p-type anode202and203and p-type optional substrate ring212, and contacts (not shown) are then coupled to silicide layers224. Semiconductor processing continues with the application of metallization and dielectric layers until processing is complete. Alternatively, other processing steps and sequences may me used.

FIG. 5illustrates layout view250of ESD device180shown inFIG. 3d. The core of SCR including anode regions202and203, cathode region206, shield diode region208is similar to the layout ofFIG. 4a. Capacitor102is implemented as NCAP270having poly silicon disposed over n-well274and with n+ regions276disposed adjacent, and diodes272are implemented according to techniques known in the art. Resistor108is implemented as poly silicon resistor268having a blocked-silicide region266in which the silicide is blocked. Similarly, resistors110and112are implemented as poly silicon resistors having blocked silicided regions256and258respectively. NMOS104is implemented using a single striped NMOS device having poly silicon gate260and n+ source and drain regions262and264, respectively. The resistors, NMOS device and capacitor are coupled together using a single piece of polysilicon, however, in alternative embodiments, these devices can be coupled together using different routing layers such as different levels of metal and polysilicon depending on the particular layout and device technology. The NMOS device is coupled to n-type trigger region204via metal interconnect274. Other connections to regions202,203,206,210,276,262,264, and212are not shown for simplicity of illustration, however, these regions are connected according to techniques known in the art. It should be further noted that the layout ofFIG. 5is just one example of how to layout an ESD device according to an embodiment of the present invention.

In alternative embodiments, other resistors types besides poly silicon resistors can be used to implement resistors108,110and112, such as n-well resistors. Also, other capacitor types can be used besides an NCAP to implement capacitor102, such as MIMCAP, PMOSCAP. Furthermore, the geometry of NMOS device104can be different with respect to size and with respect to the number of gate stripes. It should be noted that in embodiments employing the shield diode, the size of the NMOS trigger device can be smaller than ESD devices that do not employ embodiment shield diodes. In some embodiments, the trigger device can be made smaller in that the lower trigger current achieved using embodiment shield diode techniques reduces the required trigger current to activate the ESD device. Because less current is needed to trigger the ESD device, smaller trigger devices can be used, thereby reducing layout area with respect to conventional devices.

Turning toFIG. 6a, 2-dimensional array-type embodiment of ESD device300is shown. N+ cathode region612is formed as a grid that surrounds directly triggered anode regions and indirectly triggered anode regions. Each anode region has a p-base p-well region606aand n-base n-well region616. In alternative embodiments, however, these p-base and n-base regions may comprise other types of regions, for example substrate and EPI regions. In the directly triggered anode regions, p+ anode regions618(labeled A1) reside in n-well n-base regions616along with n+ trigger contact regions620(G2). In an embodiment, these regions are directly triggered by n+ trigger contact regions620. It should be noted that n+ cathode region612is disposed above p-well region606/606a, thereby allowing coupling between anodes through p-well606/606a. In an embodiment, anode regions618and trigger regions620are sized to a minimum geometry along at least one dimension and distance Y between anode regions is preferably about 1 μm, although in alternative embodiments other dimensions may be used. In the indirectly triggered anode regions, p+ anode regions614reside in n-well n-base regions616. In an embodiment, these indirectly triggered anode regions are triggered via the substrate. Anode regions614(labeled A2) are preferably sized larger than anode regions618in order to conduct higher currents, as is discussed in U.S. patent application Ser. No. 12/138,208, entitled “Semiconductor ESD Device and Method of Making Same,” which is incorporated herein by reference in its entirety. In an embodiment, regions A1are sparsely distributed with respect to regions A2.

N-well608, which forms a shield diode region according to an embodiment of the present invention, is disposed adjacent to p-well606/606aand surrounds the cathode region grid612. N+ region610is disposed within n-well608in order to facilitate contact to the n-well.FIG. 6ashows n+ region610being a continuous region within n-well608. Alternatively, n+ region610can be broken up into two or more sections within n-well610. Optional substrate contact region604surrounds n-well region608.

FIG. 6bshows a circuit model representation330of the 2-dimensional array-type ESD structure300shown inFIG. 6a. Bipolar latch334represents directly triggered anode regions and bipolar latch336represents indirectly triggered anode regions. Trigger device104is illustrated as an NMOS device104coupled to resistor108and capacitor102in this embodiment, however, other trigger devices, such as diodes can be used. Bipolar latch336is triggered by current flowing underneath cathode612in p-well606a. This coupling is designated as Rpwell. The potential across shield diode340modulates substrate resistance Rsub. In an embodiment, the cathode of the shield diode is coupled to ground via resistor114. Since the cathode of shield diode is at ground potential, the resistance to substrate Rsub is modulated by n-well region608reducing the effective cross-section of the substrate underneath, and by additionally reducing the cross-section of the p-substrate by the zero-bias depletion layer of shield diode340. In alternative embodiments, shield diode340can be coupled according to the embodiments ofFIGS. 3a,3b,3dand3e.

FIG. 7illustrates an embodiment implementation of the ESD devices described herein. Embodiment ESD device702is coupled between VDD and I/O pin708and provides protection for I/O pin708against positive going ESD disturbances (i.e. positive ESD stress at VDD, IO at ground). Embodiment ESD device704is coupled between VSS and I/O pin708and provides protection for I/O pin708against positive ESD disturbances at IO to VSS at ground). Embodiment ESD device706is coupled between VDD and VSS and provides protection for the power supply.

FIG. 8illustrates transmission line pulse (TLP) characteristics800of an embodiment ESD device802compared to TLP characteristics of a SCR-based device804that does not utilize a shield diode or an MOS triggering device. The x-axis is TLP voltage, and the y-axis is TLP current. The embodiment ESD device exhibits a lower trigger current and lower trigger voltage. Furthermore, the TLP characteristics of the embodiment ESD device802does not exhibit latchback characteristics806evident in trace804.

FIG. 9illustrates a graph900comparing leakage characteristics at 125° C. between embodiment SCR device902, and SCR device904that does not utilize an embodiment shield diode and MOSFET triggering devices. It can be seen that the embodiment ESD device consumes over ten times less leakage current at Vdd=2V than a SCR device that does not utilize an embodiment shield diode and MOSFET triggering devices.

FIG. 10illustrates TLP characterization920of embodiment devices according to the embodiment ofFIG. 3chaving different numbers of series diodes. Trace910represents a device having 1 series diode, trace912represents a device having 2 series diodes, trace914represents a device having 3 series diodes, and trace916represents a device having 4 series diodes. It can be seen that the trigger and holding voltages of an embodiment ESD device can be adjusted according to the number of series diodes.

Advantages of embodiments of the present invention include, smaller semiconductor area because a smaller trigger device is needed to source trigger current due to the reduced trigger current necessary. A further advantage of embodiments includes lower leakage current because of the lower leakage of NMOS devices.