Multi-bit flip-flop with enhanced fault detection

A processing system includes a processor core, a peripheral component, and a flip-flop unit in at least one of the processor core and the peripheral component. The flip-flop unit can include a master latch, and two slave latches coupled to an output of the master latch. The first slave latch is formed over a first doped well region of a semiconductor substrate. The second slave latch is formed over a second doped well region of the semiconductor substrate. A comparator is coupled to an output of the first slave latch and to an output of the second slave latch. An output of the comparator indicates whether a state stored in the first slave latch is the same as a state stored in the second slave latch.

BACKGROUND

1. Field of the Disclosure

The present disclosure relates in general to semiconductor devices, and more specifically to multi-bit master latches with enhanced fault detection.

2. Description of the Related Art

As consumers demand smaller processing devices, the integrated circuits within the devices also must shrink. As the size of the semiconductor memory devices decreases, the bit cell area also decreases, causing an increase in the possibility of failures induced by soft error rate (SER) and/or single event upset (SEU). SER and SEU can occur, for example, when external energy (such as energy due to alpha particle bombardment) is imparted onto the circuit, causing bit values in a memory, voltage detectors and/or other devices, to change to erroneous values. Therefore, as device geometries continue to shrink, error detection becomes increasingly important. Additionally, it is important to reduce power consumed by error detection so that energy costs are reduced and portable devices can operate for longer time periods between battery recharges.

Flip-flops are often used as the basic storage element in circuit design. When the circuit enters a low power mode the clock signal may be deactivated and the flip-flops may transfer the state to low leakage latches (e.g., a balloon latch). When the power supply is restored to the flip-flop, a signal (e.g., restore, active) may be asserted to transfer the state from the latches back to the flip-flops.

DETAILED DESCRIPTION

Embodiments of systems, devices and methods disclosed herein provide multi-bit flip-flop units with transient fault detection. Each flip-flop unit includes a master latch circuit with two slave latches coupled to the output of the master latch circuit. The slave latches are implemented in different wells in a substrate as far apart as possible from one another so that events causing soft errors or single event upsets in circuitry coupled to one well are less likely to affect circuitry coupled to the other well. The data input to one slave latch can be inverted relative to the other slave latch to improve immunity from common-cause faults. The outputs from both slave latches are compared using an open drain comparator (ODC). The output from multiple ODCs are then connected to an open drain fault bus with a level shifter and provided to a fault collection and control unit. The ODC for each flip-flop can be placed between the slave latches and other unrelated flip-flop to increase lateral distance to corresponding flip-flop. The flip-flop units detect soft or transient errors caused by energetic particles while considerably reducing space requirements and costs associated with completely redundant backup processor cores.

FIG. 1is a block diagram of a processing system100with fault detection and collection capabilities according to one embodiment that includes one or more processor cores102, fault collection and control unit104, one or more peripheral devices106, and system control module108. Processor core(s)102and peripheral device(s)106can include one or more multi-bit flip-flop units110that are capable of detecting and reporting soft errors in state retaining slave latches associated with the flip-flop units110to fault collection and control unit104on respective fault buses114,116. Fault collection and control unit104provides error or fault information from the flip-flop units110to system control module108. The fault information can include the location of the flip-flop units110reporting the faults and the number of faults detected per fault bus over a specified period of time. System control module108receives the fault information from fault collection and control unit104and determines whether to issue a reset or interrupt signal to a processor102or peripheral106encountering soft errors and/or a single event upset.

Processing system100can be any suitable type of computer system and may be implemented as system on chip (SOC) with all components on a single substrate, or as with components implemented on two or more substrates.

Peripherals106can include devices implemented with integrated circuit technology such as various types of logic circuitry, memory, low voltage detection circuits, and high voltage detection circuits, among others.

For master latch200, inverter210has an input terminal coupled to receive data (D), a supply voltage terminal coupled to voltage VDD, and an output terminal coupled to an input terminal of transmission gate212. Inverter216has an input terminal coupled to the output terminal of transmission gate212, a supply voltage terminal coupled to voltage VDD, and an output terminal coupled to an input terminal of inverter218and an input terminal of inverter220. Inverter218further has a supply voltage terminal coupled to voltage VDD, and an output terminal coupled to an input terminal of transmission gate214. Inverter220further has a supply voltage terminal coupled to voltage VDD, and an output terminal coupled to an input terminal of transmission gate222and an input terminal of inverter232. Transmission gate212is coupled to a true clock signal (CPI) and a complementary clock signal (CPN) and allows the output of inverter210to pass to the input terminal of inverter216when the true clock signal CPI goes low. Transmission gate214is coupled to true clock signal (CPI) and complementary clock signal (CPN) opposite to transmission gate212so the output of inverter218passes to the input terminal of inverter216when the true clock signal CPI goes high, thereby latching the value of the data D.

For slave latch202, transmission gate222is coupled to a true clock signal (CPI) and a complementary clock signal (CPN) to allow the output of inverter220to pass to the input terminals of respective inverters228and230when the true clock signal CPI goes high. Inverter228further has a supply voltage terminal coupled to voltage VDD, and an output terminal coupled to an input terminal of inverter226. Inverter230further has a supply voltage terminal coupled to voltage VDD, and an output terminal coupled to control gates of P-channel transistors248and252and N-channel transistor250in comparator206. Inverter226further has a supply voltage terminal coupled to voltage VDD, and an output terminal coupled to an input terminal of transmission gate224. Transmission gate224is coupled to true clock signal (CPI) and complementary clock signal (CPN) opposite to transmission gate222so the output of inverter226passes to the input terminals of inverters228and230when the true clock signal CPI goes low, thereby latching the value of the data D.

For slave latch204, transmission gate234is coupled to a true clock signal (CPI) and a complementary clock signal (CPN) to allow the output of inverter232to pass to the input terminals of respective inverters240and242when the true clock signal CPI goes high. Inverter240further has a supply voltage terminal coupled to voltage VDD, and an output terminal coupled to an input terminal of inverter238. Inverter242further has a supply voltage terminal coupled to voltage VDD, and an output terminal coupled to control gates of P-channel transistors244and254and N-channel transistor246in comparator206. Inverter238further has a supply voltage terminal coupled to voltage VDD, and an output terminal coupled to an input terminal of transmission gate236. Transmission gate236is coupled to true clock signal (CPI) and complementary clock signal (CPN) opposite to transmission gate234so the output of inverter238passes to the input terminals of inverters240and242when the true clock signal CPI goes low, thereby latching the value of the data D.

Note that in the example shown, the input to slave latch204is inverted compared to the input to slave latch202to help provide immunity to common-cause faults such as signal integrity issues and power supply noise. In embodiments where the input to one of the slave latches202,204is inverted compared to the input to the other slave latch, a fault indicator can be set to indicate a fault when the state of slave latch202matches the state of slave latch204. In other embodiments where the input to one of the slave latches202,204is the same as the input to the other slave latch, a fault indicator can be set to indicate a fault when the state of slave latch202does not match the state of slave latch204. In the other embodiments, the circuitry of comparator206will be rearranged to output a high signal when the state of slave latch202does not match the state of slave latch204.

For comparator206shown, P-channel transistor244has a source terminal coupled to supply voltage VDD, a gate terminal coupled to the output of slave latch204and a drain terminal coupled to a drain terminal of N-channel transistor246and to the gate electrode of P-channel transistor256. N-channel transistor246further has a gate terminal coupled to the output of slave latch204and a source terminal coupled to a drain terminal of N-channel transistor250. P-channel transistor248has a source terminal coupled to supply voltage VDD, a gate terminal coupled to the output of slave latch202and a drain terminal coupled to the drain terminal of P-channel transistor244and to the gate electrode of P-channel transistor256. N-channel transistor250further has a gate terminal coupled to the output of slave latch202and a source terminal coupled to ground. P-channel transistor252has a source terminal coupled to supply voltage VDD, a gate terminal coupled to the output of slave latch202and a drain terminal coupled to a source terminal of P-channel transistor254. P-channel transistor254further has a gate terminal coupled to the output of slave latch204and a drain terminal coupled to the drain terminal of P-channel transistor256. P-channel transistor256has a source electrode coupled to supply voltage VDD, a gate terminal coupled to the drain terminals of P-channel transistors244,248, and a drain terminal coupled to the drain terminal of P-channel transistor254. The output of comparator at the drain terminals of P-channel transistors254,256indicates whether the output of slave latch202matched the output of slave latch204. If the outputs of slave latches202,204do not match, a fault will be indicated by comparator206.

FIG. 3is a block diagram of an embodiment of fault bus114(and116) that may be used in the processing system100ofFIG. 1. The output terminal of one or more flip-flop units110can be coupled to fault bus114,116. One end of each fault bus114,116is coupled to ground through a respective resistor310,312. Another end of each fault bus114,116is coupled to ground through respective resistor330,334. A pull-up device such as P-channel transistor328,332is coupled in series with a respective one of resistors330,334. A source terminal of each P-channel transistor328,332is coupled to supply voltage VDD and a drain terminal of each P-channel transistor328,332is coupled to a first terminal of a respective one of resistors330,334. A second terminal of each resistor330,334is coupled to a respective ground or second supply voltage. The resistors310,330,312,334coupled to ground may be part of a standard end cap cell. A gate terminal of each P-channel transistor328,332is coupled to a respective fault injection port324,326that allows the fault line on each bus114,116to be pulled high during customer testing and debug.

An input terminal to a level shifter316,320in each of detection registers314,318are also coupled respective fault buses114,116. Level shifters316,320translate the combined output signals from all flip-flop units110coupled to a respective bus114,116from an attenuated level to a full level before the fault signal is provided to fault collection and control unit104(FIG. 1). Detection registers314,318can be implemented with a set/reset latch circuit or other suitable device, with the output of the level shifter316,320providing the input to the latch circuit. The output of each detection register314,318is provided to fault collection and control unit104.

Note that all flip-flop units110coupled to a fault bus114,116can be associated with a particular device or component in processing system. When a fault is detected, fault collection and control unit104can report the problem and the fact that the problem is occurring in a specific component, such as a particular processing core102or peripheral106, to system control108. If a reset or interrupt needs to be issued to correct the problem, the corrective action can be localized to the specific core102or peripheral106to help minimize impact on the rest of processing system100.

FIG. 4is a layout diagram of an embodiment of an eight bit flip-flop unit110that may be used in the processing system100ofFIG. 1. Flip-flop unit110includes a first section402with a first set of four master latches200coupled to a first set of four slave latches202(shown as ML/SL0, ML/SL1, ML/SL2, ML/SL3), a second set of slave latches204(shown as SL4, SL5, SL6, SL7), and a second set of comparators206(shown as COMP4, COMP5, COMP6, COMP7). Flip-flop unit110further includes a second section404with a second set of four master latches200coupled to a second set of four slave latches202(shown as ML/SL4, ML/SL5, ML/SL6, ML/SL7), a first set of slave latches204(shown as SL0, SL1, SL2, SL3), and a first set of comparators206(shown as COMP0, COMP1, COMP2, COMP3).

Slave latches SL0, SL1, SL4, SL5, comparators COMP0, COMP1, COMP4, COMP5, and master/slave latches ML/SL2, ML/SL3, ML/SL6, ML/SL7are implemented using a second well408, which is another doped region in a semiconductor substrate400that is physically and electrically isolated from first well406. The output of each comparator206is coupled to a fault pin410centrally located between first and second portions402,404of flip-flop unit110. The fault pin410is coupled to fault bus114.

Using one of wells406,408to implement one of the slave latches204, and the other well to implement the master latch200and other slave latch202increases the probability that both slave latches will not be affected by the same upset event. If both slave latches202,204were implemented in the same well406or408, they would be more likely to be affected by the same upset event. In embodiments where the input to slave latch204is not inverted, and a comparison between slave latches202,204indicates they both have the same state, no error will be detected by the comparator even though both slave latches202,204may have changed to an erroneous state during the upset event. In embodiments where the input to slave latch204is inverted, and a comparison between slave latches202,204indicates they both have different states, no error will be detected by the comparator even though both slave latches202,204may have changed to an erroneous state during the upset event.

Additionally, slave latches204can be positioned as far as possible from master latch200and slave latch202. For example, master latch and slave latch ML/SL0are positioned in first portion402of substrate400and corresponding slave latch SL0is positioned in the second portion404of substrate400. COMP0is also positioned in the second portion404of substrate400between master and slave latch ML/SL0and slave latch SL0to increase the physical distance between the slave latches202,204to the greatest extent possible.

FIG. 5is a layout diagram of an embodiment of a four bit flip-flop unit110that may be used in the processing system100ofFIG. 1. Flip-flop unit110includes a first section502with a first set of two master latches200coupled to a first set of two slave latches202(shown as ML/SL2, ML/SL3), a second set of slave latches204(shown as SL0, SL1), and a second set of comparators206(shown as COMP0, COMP1). Flip-flop unit110further includes a second section504with a second set of two master latches200coupled to a second set of two slave latches202(shown as ML/SL1, ML/SL0), a first set of slave latches204(shown as SL2, SL3), and a first set of comparators206(shown as COMP2, COMP3).

Slave latches202,204, comparators206, and master latches200are implemented using a first well506, which is a doped region in a semiconductor substrate500.

The output of each comparator206is coupled to a fault pin510centrally located between first and second portions502,504of flip-flop unit110. The fault pin510is coupled to fault bus114.

Slave latches204can be positioned as far as possible from master latch200and slave latch202. For example, master latch and slave latch ML/SL0are positioned in first portion502of substrate500and corresponding slave latch SL0is positioned in the second portion504of substrate500. COMP0is also positioned in the second portion504of substrate500between master and slave latch ML/SL0and slave latch SL0to increase the physical distance between the slave latches202,204to the greatest extent possible.

By now it should be appreciated that in some embodiments, a processing system (100) can include a processor core (102), a peripheral component (106), and a flip-flop unit (110) in at least one of the processor core and the peripheral component. The flip-flop unit can include a master latch (200), and two slave latches (202,204) coupled to an output of the master latch. The first slave latch is formed over a first doped well region of a semiconductor substrate. The second slave latch (204) is formed over a second doped well region of the semiconductor substrate. A comparator (206) is coupled to an output of the first slave latch and to an output of the second slave latch. An output of the comparator indicates whether a state stored in the first slave latch is the same as a state stored in the second slave latch.

In another aspect, the master latch can be formed over the first doped well region.

In another aspect, the second slave latch can be positioned at a distance greater than a closest possible distance from the master latch.

In another aspect, the first slave latch and the master latch can be positioned in a first standard cell and the second slave latch can be positioned in a second standard cell at a farthest possible distance from the first slave latch and the master latch.

In another aspect, the system can further comprise a fault bus. The output of the comparator can be coupled to the fault bus.

In another aspect, the flip-flop unit can further include a plurality of: master latches, first and second slave latches, and comparators, and the output from the comparator and a plurality of outputs from the plurality of comparators can be coupled to the fault bus.

In another aspect, the fault bus can be coupled to a detection register with a level shifter to amplify the output from the comparator and the plurality of outputs from the plurality of comparators.

In another aspect, the fault bus can be connected to end cap cells at both ends of a standard cell row.

In another aspect, one of the end cap cells can include a pull-down device to enable wire-ORing of multiple fault signals, and the system can further comprise a controlled pull-up device to allow fault injection during testing.

In another aspect, the system can further comprise a fault collection and control unit coupled to the fault bus. A fault indication is set when either the state stored in the first slave latch is not the same as the state stored in the second slave latch, and the output of the master latch is input to the second slave latch; or the state stored in the first slave latch is the complement of the state stored in the second slave latch, and the output of the master latch is inverted before being input to the second slave latch.

In another aspect, the system can further comprise a system control unit coupled between the fault collection and control unit and the processor core, and between the fault collection and control unit and the peripheral. The fault indication from the fault collection and control unit can indicate a location of a fault and the system control unit can take corrective action based on the location of the fault indication.

In other embodiments, a flip-flop unit (110) can include a plurality of master latches (200) formed over a first doped well region of a semiconductor substrate, and a plurality of first slave latches (202) coupled to an output of a respective one of the master latches. The first slave latch can be formed over the first doped well region. A plurality of second slave latches (204) can be coupled to the output of the respective one of the master latches. The second slave latch can be formed over a second doped well region of the semiconductor substrate. A plurality of comparators (206) can each be coupled to an output one of the plurality of first slave latches and to an output of one of the plurality of the second slave latches. An output of each of the comparators indicates whether a state stored in the one of the plurality of first slave latch is the same as a state stored in the one of the plurality of the second slave latch. The output of each of the comparators can be coupled to a fault bus.

In another aspect, each of the plurality of the first slave latches and the master latches can be positioned in a respective first standard cell and each of the plurality of the second slave latches can be positioned in a second standard cell. The second standard cell can be at a farthest possible distance from the first slave latch and the flip-clop circuit.

In another aspect, the fault bus can be coupled to a detection register with a level shifter to amplify the output from the outputs of the plurality of comparators.

In another aspect, the fault bus can be connected to an end cap cell at one end and the end cap cell includes a pull-down device to enable wire-ORing of multiple fault signals, and the flip-flop unit can further comprise a controlled pull-up device to allow fault injection during testing.

In another aspect, the plurality of comparators can be positioned between the plurality of master latches and the plurality of second slave latches.

In another aspect, a first half of the plurality of master latches and first slave latches can be positioned in a first column (402) of a layout and a first half of the second slave latches can be associated with the first half of the plurality of master latches and first slave latches are in a second column (404) of the layout. A second half of the plurality of master latches and first slave latches are positioned in the second column of the layout and a second half of the second slave latches associated with the second half of the plurality of master latches and first slave latches are in the first column of the layout.

In still other embodiments, a method can comprise storing an output from a master latch as a state in a first slave latch, and storing the output from the master latch as a state in a second slave latch. The first slave latch and the master latch can be implemented using a first doped well of a semiconductor substrate, and the second slave latch can be implemented using a second doped well of the semiconductor substrate. The state stored in the first slave latch can be compared to the state stored in the second slave latch. A fault indicator can be based on whether the state stored in the first slave latch matches the state stored in the second slave latch.

In another aspect, the method can further comprise taking corrective action in a processing system component based on the fault indicator.

In another aspect, the method can further comprise coupling a plurality of fault indicators to a fault bus, and level shifting the plurality of fault indicators to translate a reduced voltage level on the fault bus to a full voltage level.

Also for example, in one embodiment, the illustrated elements of systems disclosed herein are circuitry located on a single integrated circuit or within a same device. Alternatively, the systems may include any number of separate integrated circuits or separate devices interconnected with each other. Also for example, a system or portions thereof may be soft or code representations of physical circuitry or of logical representations convertible into physical circuitry. As such, a system may be embodied in a hardware description language of any appropriate type.

Processing system100is a computer system such as a personal computer system. Other embodiments may include different types of computer systems. Computer systems are information handling systems which can be designed to give independent computing power to one or more users. Computer systems may be found in many forms including but not limited to mainframes, minicomputers, servers, workstations, personal computers, notepads, personal digital assistants, electronic games, automotive and other embedded systems, cell phones and various other wireless devices. A typical computer system includes at least one processing unit, associated memory and a number of input/output (I/O) devices.

Although the present disclosure has been described in considerable detail with reference to certain preferred versions thereof, other versions and variations are possible and contemplated. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiments as a basis for designing or modifying other structures for carrying out the same purposes of the present disclosure without departing from the scope of the disclosure as defined by the appended claims.