Semiconductor integrated circuit device

Efficient reduction in power consumption is achieved by combinational implementation of a power cutoff circuit technique using power supply switch control and a DVFS technique for low power consumption. A power supply switch section fed with power supply voltage, a circuit block in which a power cutoff is performed by the power supply switch section, and a level shifter are formed in a DEEP-NWELL region formed over a semiconductor substrate. Another power supply switch section fed with another power supply voltage, a circuit block in which a power cutoff is performed by the power supply switch section, and a level shifter are formed in another DEEP-NWELL region formed over the semiconductor substrate. In this arrangement, there arises no possibility of short-circuiting between different power supplies via each DEEP-NWELL region formed over the semiconductor substrate.

CROSS-REFERENCE TO RELATED APPLICATIONS

The disclosure of Japanese Patent Application No. 2009-45780 filed on Feb. 27, 2009 and Japanese Patent Application No. 2009-236189 filed on Oct. 13, 2009 each including the specification, drawings and abstract are incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

The present invention relates to techniques for enhancing characteristics of semiconductor integrated circuit devices, and more particularly to techniques for low power consumption thereon.

Recent years have seen an increasing demand for low power consumption in semiconductor integrated circuit devices, typified by system LSI devices used for mobile apparatus or the like. In the art of low power consumption, there are known a power cutoff circuit technique and a DVFS (Dynamic Voltage Frequency Scaling) technique, for example.

In the power cutoff circuit technique, a semiconductor integrated circuit device is divided into a plurality of internal circuit blocks, and an inactive circuit block is powered off to suppress a leak current that would otherwise cause a significant amount of power consumption.

In the DVFS technique, an operating frequency and voltage to be applied to a circuit block such as a processor is dynamically varied in response to requirement for current performance. In cases where a plurality of circuit blocks use different power supply voltages, it is required to provide a level shifter (level shift circuit) for varying voltage levels of signals to be sent and received between core regions.

SUMMARY OF THE INVENTION

The present inventors have studied the above-noted power cutoff circuit technique and DVFS technique regarding combinational implementation thereof for the purpose of further reducing power consumption in semiconductor integrated circuit devices.

More specifically, the present inventors examined the practicability of the following scheme in addition to low-power-consumption control by means of DVFS: In an arrangement wherein a circuit is divided into a plurality of circuit blocks, a power supply VSS having a reference potential (ground potential) or a power supply VDD having a voltage higher than the reference potential is turned off or on for each divided circuit block by using a power supply switch.

To allow each circuit block to be cut off from the power supply VSS by using the power supply switch, it is required that a PWELL region (p-type well region, p-type semiconductor region) including n-channel MOSFETs or the like formed thereon should be isolated from a p-type semiconductor substrate by a DEEP-NWELL region (deep n-type well region, deep n-type semiconductor region). If there is no DEEP-NWELL region formed between the PWELL region and the p-type semiconductor substrate, the PWELL region is in contact with the p-type semiconductor substrate. In such a formation, a short-circuit occurs between PWELL regions formed in a plurality of circuit blocks through the p-type semiconductor substrate.

A voltage of the power supply VSS is applied to each PWELL region included in each circuit block. Even if it is attempted to cut off the power supply VSS in a certain circuit block by means of power supply switch control, the voltage of the power supply VSS applied to each PWELL region in another circuit block is fed to each PWELL region in the circuit block concerned, thereby making it impossible to cut off the power supply VSS therein. To circumvent this problematic condition, it is required to form a DEEP-NWELL region as mentioned above.

The present inventors also examined the practicability of a scheme of using DVFS for a plurality of circuit blocks in combination with the above-mentioned power cutoff circuit technique in which a DEEP-NWELL region is formed. In cases where there is a difference between power supply voltages in the plural circuit blocks, it is required to interpose a level shifter between core regions. Regarding this arrangement, the present inventors found the following problem:

FIG. 26shows an explanatory diagram of an exemplary layout of transistor formation for a level shifter, wherein a PWELL region is isolated from a p-type semiconductor substrate by a DEEP-NWELL region examined by the present inventors.FIG. 27shows a sectional diagram of an exemplary cross-section taken along the solid line A-B-C-D inFIG. 26.

Referring toFIG. 26, there is shown a layout pattern of a transistor100and a transistor101included in a level shifter.

The transistor100is formed over an NWELL region104formed in a DEEP-NWELL region103, and the transistor101is formed over an NWELL region109formed in the same DEEP-NWELL region103.

That is, as illustrated, the transistor100and the transistor101are formed over the same DEEP-NWELL region103overlying a p-type semiconductor substrate102.

At the location where the transistor100is formed, an NWELL region104is formed over the DEEP-NWELL region103. In the NWELL region104, there are disposed a p-type semiconductor region105serving as a drain, and a p-type semiconductor region106serving as a source. At the upper position of these p-type semiconductor regions105and106, a gate108is formed via an oxide film107.

Further, at the location where the transistor101is formed, an NWELL region109is formed over the DEEP-NWELL region103. In the NWELL region109, there are disposed a p-type semiconductor region111serving as a drain, and a p-type semiconductor region110serving as a source. At the upper position of these p-type semiconductor regions110and111, a gate113is formed via an oxide film112.

In the above-mentioned arrangement wherein the transistors100and101included in a level shifter are formed over the same DEEP-NWELL region103, a short-circuit occurs between a sending-side power supply VDD and a receiving-side power supply VDD2through the DEEP-NWELL region103as indicated inFIG. 27.

As described above, the present inventors found that, in an arrangement wherein a level shifter is required for combinational use of the DVFS technique and the power cutoff circuit technique with DEEP-NWELL region formation, there arises a problem of short-circuiting between the sending-side power supply VDD and the receiving-side power supply VDD2.

It is therefore an object of the present invention to provide a technique for achieving efficient reduction in power consumption by combinational implementation of the power cutoff circuit technique using power supply switch control and the DVFS technique for low power consumption.

The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description with reference to the accompanying drawings.

The representative features of the present invention are briefed below:

In carrying out the present invention and according to one aspect thereof, there is provided a semiconductor integrated circuit device comprising a plurality of circuit blocks that are allowed to be powered off, wherein operating frequencies and power supply voltages fed to the circuit blocks can be varied dynamically, and wherein level shifters in the circuit blocks are formed in respective different WELL isolation regions over a semiconductor substrate.

Enumerated below are advantageous effects to be provided according to the representative aspects of the present invention:

(1) Low-power-consumption control can be carried out by performing a combination of a first low-power-consumption control operation and a second low-power-consumption control operation.

(2) Based on the above item (1), precise control is applicable to reduction in power consumption in a semiconductor integrated circuit device, thereby making it possible to further decrease the amount of power to be consumed.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following detailed description of the preferred embodiments according to the present invention, some aspects of the present invention are separately described in a plurality of sections or in a plurality of forms corresponding to individual preferred embodiments for the sake of convenience in explanation as required. It is to be noted, however, that these sections and forms are mutually related unless otherwise specified, i.e., each section or form pertaining to a certain aspect separately described hereinbelow is in whole or in part associated with the other sections or forms concerned in such a fashion as a modified embodiment, additional arrangement, or supplementary implementation. Further, where specific numeric values regarding component elements (quantities, ranges, and other values) are indicated in the following description of the preferred embodiments, it is to be understood that the present invention is not limited to the indicated specific values, and that larger or smaller values than the indicated specific values may be applied unless otherwise specified or unless preconditioned basically on the principle of operation. Furthermore, in the description of the preferred embodiments, it will be obvious to those skilled in the art that some component elements thereof (including some elementary steps thereof or the like) are not necessarily required unless otherwise specified or unless definitely required on the principle of operation. Likewise, where conditions such as configurations, positions, and relationships of component elements or the like are described regarding the preferred embodiments, it is to be understood that conditions analogous thereto such as substantially approximate or similar configurations, positions, and relationships are also included therein. The same shall also apply to numeric values (quantities, ranges, and other values) in the description of the preferred embodiments.

The present invention will now be described in detail by way of example with reference to the accompanying drawings showing the preferred embodiments thereof. Throughout the accompanying drawings, like reference characters designate like or corresponding parts to avoid repetitive description thereof. In the following description of the preferred embodiment, no duplicative explanation is given regarding identical or similar parts unless otherwise necessary.

FIG. 1shows an explanatory diagram of an exemplary configuration of a semiconductor integrated circuit device according to a preferred embodiment 1 of the present invention;FIGS. 2(a) and2(b) show explanatory diagrams of exemplary operation modes arranged by means of DVFS and power cutoff in the semiconductor integrated circuit device inFIG. 1;FIG. 3shows an explanatory diagram of an exemplary configurational layout of level shifters disposed in circuit blocks of the semiconductor integrated circuit device inFIG. 1;FIG. 4shows a circuit diagram of an exemplary circuit arrangement of a sending-side level shift section and a receiving-side level shift section in the semiconductor integrated circuit device inFIG. 1;FIG. 5shows a plan view of an exemplary layout of device elements indicated by the solid line A-B-C-D inFIG. 4;FIG. 6shows a sectional diagram of an exemplary cross-section taken along the solid line A-B-C-D inFIG. 5;FIG. 7shows an exemplary diagram of an exemplary wiring arrangement of the sending-side level shift section and the receiving-side level shift section inFIG. 4; andFIG. 8shows an explanatory diagram of another exemplary wiring arrangement of the sending-side level shift section and the receiving-side level shift section inFIG. 4.

According to the preferred embodiment 1 of the present invention, a semiconductor integrated circuit device1comprises a plurality of circuit blocks2to4as shown inFIG. 1. The circuit block2(a first circuit block) is arranged as a region fed with a voltage of a power supply VDD.

The circuit block3,4(a second circuit block) is arranged as a region fed with a voltage of a power supply VDD2having a voltage level that can be dynamically varied by means of DVFS (a second low-power-consumption control operation).

The power supply VDD2, which is of a variable voltage type, is controlled by a Power Management Unit (PMU)5disposed in a circuit block18shown inFIG. 3. The circuit block18is fed with power supply voltage VDD, and no power supply switch section is provided therein. The circuit block18is a so-called “always-on region” wherein a power cutoff is not performed.

The PMU5, which serves as a power supply switch control section and a frequency/power supply control section, issues a voltage regulation instruction (control signal) to a power supply IC6coupled to the semiconductor integrated circuit device1for frequency/power supply control. In accordance with the voltage regulation instruction, the power supply IC6generates an arbitrary level of power supply voltage VDD2. It is to be noted that the power supply IC6is not limited to an external IC coupled to the semiconductor integrated circuit device1as exemplified inFIG. 1, and that the power supply IC6may be included in the semiconductor integrated circuit device1.

The circuit blocks2,3, and4are coupled respectively with a power supply switch section7(a first power supply switch section), a power supply switch section8(a second power supply switch section), and a power supply switch section9(a second power supply switch section), each comprising n-channel MOS transistors coupled in parallel. In these power supply switch sections, a gate insulating film of each n-channel MOS transistor thereof is formed to have a thickness larger than that of a gate insulating film of MOS transistors used in the other regions for the purpose of enhancing dielectric strength in gate insulation.

The power supply switch section7is coupled between the circuit block2and a power supply VSS so as to provide a coupling node serving as a virtual power supply VSSM1. The power supply switch section8is coupled between the circuit block3and the power supply VSS so as to provide a coupling node serving as a virtual power supply VSSM2.

Further, the power supply switch section9is coupled between the circuit block4and the power supply VSS so as to provide a coupling node serving as a virtual power supply VSSM3(refer toFIG. 4for which description will be given later).

The power supply switch sections7to9are coupled to power supply controllers10to12(PSWC; power supply switch control sections), respectively. Under the direction of the power supply switch controllers10to12, the power supply switch sections7to9are turned on/off, respectively. Thus, each of the circuit blocks2to4is powered off independently (a first low-power-consumption control operation; a first power control state).

Upon receiving an instruction output from the PMU5, the power supply switch controllers10to12deliver control signals to the power supply switch sections7to9for control thereof, respectively. In the power supply switch sections7to9, a gate insulating film of each transistor thereof may be formed to have a thickness equal to that of a gate insulating film of n-channel MOS transistors used in a core region. In this case, it is to be noted that the power supply VDD is used for the power supply switch controllers10to12.

Further, in the circuit blocks2to4, there are provided level shifters13to15, respectively. These level shifters13to15are used for converting signal voltage levels at the time of signal transmission/reception between the circuit block2and the circuit block3or between the circuit block2and the circuit block4.

Still further, the semiconductor integrated circuit device1includes a level shifter16disposed for each input/output terminal. The level shifter16performs a voltage level conversion operation on input/output signals (conversion from an amplitude level of power supply voltage VCC into an amplitude level of power supply voltage VDD) for each input/output section coupled to an external circuit. Each input/output section is driven by a power supply VCCQ and power supply VSSQ that have voltages thereof fed from external circuits.

Furthermore, the semiconductor integrated circuit device1includes a level shifter17for converting a signal voltage level of each control signal to be output from the PMU5to the power supply IC6, and a level shifter17afor converting a voltage level of each instruction to be output from the PMU5to the power supply switch controllers10to12.

FIGS. 2(a) and2(b) show explanatory diagrams of exemplary operation modes provided by means of DVFS and power cutoff thorough use of the power supply switch sections7to9.

As shown inFIG. 2(a), the semiconductor integrated circuit device1is provided with active operation modes and standby modes. The active operation modes includes an “overdrive” mode, a “normal” mode, and an “underdrive” mode; and the standby modes includes a “clock stop” mode, a “cutoff 1” mode, and a “cutoff 2” mode.

InFIG. 2(b), there is shown a graph indicating voltage levels of the power supply VDD2, voltage levels of the virtual reference power supply VSSM, and operating frequencies of clock signaling in respective modes mentioned above.

First, the active operation modes are described below: In the “overdrive” mode included therein, the voltage level of the power supply VDD2is increased from approximately 1.2 V assigned as a normal voltage value to approximately 1.3 V, and the operating frequency of clock signaling is also increased to approximately 800 MHz, for example. Both the level of power consumed and the operating frequency of clock signaling are maximized in the “overdrive” mode.

Further, in the “normal” mode, the voltage level of the power supply VDD2is approximately 1.2 V, and the operating frequency of clock signaling is approximately 600 MHz, for example.

Still further, in the “underdrive” mode, the voltage level of the power supply VDD2is decreased to approximately 1.0 V, and the operating frequency of clock signaling is also decreased to approximately 200 MHz, for example. Both the level of power consumed and the operating frequency of clock signaling are minimized in the “underdrive” mode in comparison of the three active operation modes.

As described above, the operating frequency of clock signaling and the voltage level of the power supply VDD2are increased in a situation where higher-frequency operation is required. Alternatively, the operating frequency of clock signaling and the voltage level of the power supply VDD2are decreased in a situation where lower-frequency operation is performed.

Thus, power consumption in active operation can be reduced efficiently.

The standby modes are then described below: In the “clock stop” mode included therein, a clock signal is stopped, and a power supply voltage VDD2of approximately 1.2 V is applied, for example. The “clock stop” mode does not allow a power cutoff to be made by the power supply switch sections8and9.

Further, in the “cutoff 1” mode, the clock signal is also stopped, and a power supply voltage VDD2of approximately 1.2 V is applied, for example. A power cutoff is made by the power supply switch sections8and9in the “cutoff 1” mode.

Still further, in the “cutoff 2” mode, the clock signal is also stopped, and the voltage level of the power supply VDD2is decreased to approximately 1.0 V, for example. A power cutoff is made by the power supply switch sections8and9in the “cutoff 2” mode.

In cases where the clock signal is just stopped under standby condition, there remains a disadvantage of current leakage. With respect to the “clock stop” mode in which the clock signal is just stopped, it is possible to further reduce standby current requirement by performing a power cutoff using the power supply switch sections8and9under the standby condition. In this case, a decrease in power supply voltage brings about even further reduction in standby current. Therefore, in the “cutoff 2” mode, the voltage level of the power supply VDD2is decreased further, contributing to a more advantageous effect on reduction in current leakage.

FIG. 3shows an explanatory diagram of an exemplary configurational layout of the level shifter13disposed in the circuit block2and the level shifter14disposed in the circuit block3.

The level shifter13disposed in the circuit block2comprises a sending-side level shift section13a(a first sending-side level shifter) and a receiving-side level shift section13b(a second receiving-side level shifter). Likewise, the level shifter14disposed in the circuit block3comprises a sending-side level shift section14a(a second sending-side level shifter) and a receiving-side level shift section14b(a first receiving-side level shifter).

Through the sending-side level shift section13a, a signal output from the circuit block2is converted into a differential signal, which is then output to the receiving-side level shift section14b. Through the sending-side level shift section14a, a signal output from the circuit block3is converted into a differential signal, which is then output to the receiving-side level shift section13b.

Upon receipt of the differential signal, the receiving-side level shift section13bconverts the received differential signal into an amplitude level of power supply voltage VDD. On the other hand, upon receipt the differential signal, the receiving-side level shift section14bconverts the received differential signal into an amplitude level of power supply voltage VDD2. Although not shown inFIG. 3, the circuit block4also includes a sending-side level shift section and a receiving-side level shift section arranged in a fashion similar to that described above.

As shown inFIG. 3, the circuit block2, and the circuit block18, which is used as an always-on region constantly fed with power supply voltage VDD, are formed over a DEEP-NWELL region19serving as a WELL isolation region. The circuit blocks3and4are formed over a DEEP-NWELL region20fed with power supply voltage VDD2. These DEEP-NWELL regions19and20are disposed isolatedly in a mutually independent fashion.

FIG. 4shows a circuit diagram of an exemplary circuit arrangement of the sending-side level shift section13aand the receiving-side level shift section14b. Each level shifter is arranged as a circuit for converting two different kinds of power supply voltages. The power supply VDD is used for the sending-side level shifter. The power supply VDD2is used for the receiving-side level shifter and a succeeding-stage output buffering section thereof. The circuit having a configuration mentioned above is provided as a cell.

The sending-side level shift section13acomprises transistors T1to T4, and the receiving-side level shift section14bcomprises transistors T6, T7, and T9to T14. A transistor T5is an element included in the power supply switch section7, and a transistor T8is an element included in the power supply switch section8.

The transistors T1and T2are arranged to configure an inverter coupled in series between the power supply VDD and the virtual power supply VSSM1. A signal output from the circuit block2is input to an input part of the inverter configured by the transistors T1and T2.

The transistors T3and T4are also arranged to configure an inverter coupled in series between the power supply VDD and the virtual power supply VSSM1. An output part of the inverter configured by the transistors T1and T2is coupled to an input part of the inverter configured by the transistors T3and T4.

One power electrode part (drain) of the transistor T5is coupled to the virtual power supply VSSM1, and the other power electrode part (source) of the transistor T5is coupled to the power supply VSS.

One power electrode part (source) of each of the transistors T9and T10is coupled to the power supply VDD2, and between the other power electrode part (drain) of the transistor T9and the virtual power supply VSSM2, the transistors T6and T7are coupled in series to configure an inverter.

Likewise, between the other power electrode part (drain) of the transistor T10and the virtual power supply VSSM2, the transistors T11and T12are coupled in series to configure an inverter. One power electrode part (drain) of the transistor T8is coupled to the virtual power supply VSSM2, and the other power electrode part (source) of the transistor T8is coupled to the power supply VSS.

Further, the transistors T13and T14are arranged to configure an inverter coupled in series between the power supply VDD2and the virtual power supply VSSM2.

The transistor T10has a gate thereof coupled to an output part of the inverter configured by the transistors T6and T7, and the transistor T9has a gate thereof coupled to an output part of the inverter configured by the transistors T11and T12.

A signal output from the inverter configured by the transistors T3and T4is applied as a differential signal to an input part of the inverter configured by the transistors T6and T7. Likewise, a signal output from the inverter configured by the transistors T1and T2is applied as a differential signal to an input part of the inverter configured by the transistors T11and T12.

Further, an output part of the inverter configured by the transistors T6and T7is coupled to an input part of the inverter configured by the transistors T13and T14, and an output part of the inverter configured by the transistors T13and T14is arranged to serve as an output part of the receiving-side level shift section14b.

FIG. 5shows a plan view of an exemplary layout of device elements indicated by the solid line A-B-C-D inFIG. 4.

In the sending-side level shift section13ashown on the left ofFIG. 5, the transistor T3is disposed at the upper left position thereof, and the transistor T4is disposed at the lower left position thereof.

The transistor T5included in the power supply switch section7is disposed at the right position of the transistor T4.

In the receiving-side level shift section14bshown on the right ofFIG. 5, the transistor T8included in the power supply switch section8is disposed at the lower left position thereof. The transistor T7is disposed at the right position of the transistor T8, and the transistor T6is disposed at the upper position of the transistor T7.

The transistor T3, shown inFIG. 5, is formed in an NWELL region21overlying the DEEP-NWELL region19. The transistors T4and T5are formed in a PWELL region22aand a PWELL region22overlying the DEEP-NWELL region19, respectively.

The transistor T6is formed in an NWELL region23overlying the DEEP-NWELL region20that is disposed isolatedly from the DEEP-NWELL region19. The transistors T7and T8are formed in a PWELL region24aand a PWELL region24overlying the DEEP-NWELL region20, respectively.

FIG. 6shows a sectional diagram of an exemplary cross-section taken along the solid line A-B-C-D inFIG. 5.

As shown at the left and right positions inFIG. 6, the DEEP-NWELL region19and the DEEP-NWELL region20are isolatedly formed respectively in a mutually independent fashion over a p-type semiconductor substrate25. Over the DEEP-NWELL region19, the NWELL region21is disposed between the PWELL region22a(left side) and the PWELL region22(right side).

In the NWELL region21, a p-type semiconductor region26and a p-type semiconductor region27are formed to serve as a source and drain of the transistor T3, respectively. Over the p-type semiconductor regions26and27, a gate29is formed via an oxide film28.

In the PWELL region22a, an n-type semiconductor region30and an n-type semiconductor region31are formed to serve as a drain and source of the transistor T4, respectively. Over the n-type semiconductor regions30and31, a gate33is formed via an oxide film32.

In the PWELL region22, an n-type semiconductor region34and an n-type semiconductor region35are formed to serve as a source and drain of the transistor T5, respectively. Over the n-type semiconductor regions34and35, a gate37is formed via an oxide film36.

In the PWELL region24, an n-type semiconductor region38and an n-type semiconductor region39are formed to serve as a source and drain of the transistor T8, respectively. Over the n-type semiconductor regions38and39, a gate41is formed via an oxide film40.

In the PWELL region24a, an n-type semiconductor region42and an n-type semiconductor region43are formed to serve as a source and drain of the transistor T7, respectively. Over the n-type semiconductor regions42and43, a gate45is formed via an oxide film44.

In the NWELL region23, a p-type semiconductor region47and a p-type semiconductor region46are formed to serve as a source and drain of the transistor T6, respectively. Over the p-type semiconductor regions46and47, a gate49is formed via an oxide film48.

As mentioned above, since the DEEP-NWELL region19and the DEEP-NWELL region20are formed isolatedly in a mutually independent fashion, a short-circuit between the power supply VDD and the power supply VDD2that have different voltage levels can be prevented owing to isolation between the DEEP-NWELL regions19and20.

Further, over each DEEP-NWELL region, the sending-side level shift section and the receiving-side level shift section each have only one power supply. It is therefore possible to make a topological arrangement similar to that for other standard cells. Thus, there can be provided a higher degree of freedom in layout design and an affinity for standard cells.

FIG. 7shows an exemplary wiring arrangement of the sending-side level shift section13aand the receiving-side level shift section14b(or the receiving-side level shift section13band the sending-side level shift section14b).

As shown inFIG. 7, the sending-side level shift section13aand the receiving-side level shift section14bare provided with a wiring arrangement therebetween comprising a True wiring line50and a Bar wiring line51for feeding differential signals, and a power wiring line52for feeding power supply voltage VDD (or power supply voltage VSS).

In the wiring arrangement mentioned above, the True wiring line50and the Bar wiring line51are formed to have a length substantially equal to each other. (It is preferable that the lengths of the True wiring line50and the Bar wiring line51should be substantially equal to each other within a range of allowing a delay to an extent that a through-current value has no adverse effect on operations of the semiconductor integrated circuit device1.)

Thus, a delay time in differential signal propagation can be reduced significantly, and a through-current in the receiving-side level shift section14bcan also be reduced.

Further, the power wiring line52is so disposed as to provide shielding between the True wiring line50and the Bar wiring line51, thereby making it possible to reduce crosstalk noise due to possible cross-coupling between the wiring line50and the Bar wiring line51.

FIG. 8shows an explanatory diagram of another exemplary wiring arrangement of the sending-side level shift section14aand the receiving-side level shift section14b.

While the power wiring line52for feeding power supply voltage VDD (or power supply voltage VSS) is disposed sandwich-wise between the True wiring line50and the Bar wiring line51in the exemplary wiring arrangement shown inFIG. 7, the two power wiring lines may be disposed sandwich-wise between the True wiring line50and the Bar wiring line51, i.e., the power wiring line52for feeding power supply voltage VDD and a power wiring line53for feeding power supply voltage VSS may be disposed sandwich-wise between the True wiring line50and the Bar wiring line51as shown inFIG. 8.

According to the preferred embodiment 1 of the present invention, there is provided a principal feature that the DEEP-NWELL region19and the DEEP-NWELL region20are formed isolatedly in a mutually independent fashion and that the sending-side level shift section13aand the receiving-side level shift section14bare disposed in the DEEP-NWELL region19and the DEEP-NWELL region20, respectively, as shown inFIGS. 5 and 6. As described in the foregoing, in the configuration shown inFIG. 27examined by the present inventors, there arises a problem of possible short-circuiting between the power supply VDD and the power supply VDD2through the DEEP-NWELL region103. Contrastingly, in the preferred embodiment 1 of the present invention, the DEEP-NWELL region19and the DEEP-NWELL region20are formed isolatedly in a mutually independent fashion to prevent short-circuiting between the power supply VDD and the power supply VDD2.

In cases where a plurality of DEEP-NWELL regions are disposed isolatedly, it is required to provide a space between the DEEP-NWELL regions. That is, in comparison with the formation of a single DEEP-NWELL region, a larger plane area is required to cause an increase in chip plane size. Hence, for common applications, the formation of a plurality of isolated DEEP-NWELL regions is regarded as disadvantageous. Nonetheless, since the present inventors have found a problem of possible short-circuiting between the power supply VDD and the power supply VDD2, the DEEP-NWELL region19and the DEEP-NWELL region20are formed isolatedly in a mutually independent fashion for the purpose of solving this problem. Thus, it has become possible to inventively implement a combination of power cutoff and DVFS techniques.

FIG. 9shows an explanatory diagram of an exemplary configurational layout of level shifters disposed in circuit blocks according to a preferred embodiment 2 of the present invention;FIG. 10shows a circuit diagram of an exemplary circuit arrangement of a sending-side level shift section and a receiving-side level shift section included in each of the level shifters inFIG. 9;FIG. 11shows a plan view of an exemplary layout of device elements indicted by the solid lines A-B, C-D-E-F, and G-H inFIG. 10; andFIG. 12shows a sectional diagram of an exemplary cross-section taken along the solid lines A-B, C-D-E-F, and G-H inFIG. 10.

According to the preferred embodiment 2 of the present invention, the sending-side level shift section13aand the receiving-side level shift section14bare formed in an always-on region of the p-type semiconductor substrate25between the DEEP-NWELL region19and the DEEP-NWELL region20as shown inFIG. 9.

WhileFIG. 9shows an example in which the circuit block18used as an always-on region is formed in the DEEP-NWELL region19, there may be provided a modified arrangement wherein the circuit block18is formed in a region other than the DEEP-NWELL region19.

Referring toFIG. 10, there is shown an exemplary circuit configuration of the sending-side level shift section13aand the receiving-side level shift section14b.

In the sending-side level shift section13a, being different from the preferred embodiment 1 shown inFIG. 4, the transistor T5is coupled between the virtual power supply VSSM1and the power supply VSS in the circuit block2, and the other power electrode part of each of the transistors T2and T4is coupled to the power supply VSS.

Similarly, in the receiving-side level shift section14b, being different from the preferred embodiment 1 shown inFIG. 4, the transistor T8is coupled between the virtual power supply VSSM2and the power supply VSS in the circuit block3, and the other power electrode part of each of the transistors T7, T12, and T14is coupled to the power supply VSS. Since the other coupling arrangements are similar to those shown inFIG. 4, no repetitive description thereof is given here.

FIG. 11shows a plan view of an exemplary layout of device elements indicated by the solid lines A-B, C-D-E-F, and G-H inFIG. 10.

As shown on the left of theFIG. 11, the transistor T5is formed in the PWELL region22overlying the DEEP-NWELL region19. The PWELL region22is so formed as to be surrounded by the NWELL region21.

At the right position of the transistor T5, the transistor T4is formed over the p-type semiconductor substrate25(FIG. 12), and at the upper position of the transistor T4, the transistor T3is formed over the NWELL region21a.

At the right position of the transistor T3, the transistor T6is formed over the NWELL region23a, and at the lower position of the transistor T6, the transistor T7is formed over the p-type semiconductor substrate25.

Further, the transistor T8is formed in the PWELL region24overlying the DEEP-NWELL region20. The PWELL region24is so formed as to be surrounded by the NWELL region23.

FIG. 12shows a sectional diagram of an exemplary cross-section taken along the solid lines A-B, C-D-E-F, and G-H inFIG. 10.

For the transistor T5, the DEEP-NWELL region19is formed over the p-type semiconductor substrate25, and the PWELL region22is formed over the DEEP-NWELL region19.

In the PWELL region22, an N-type semiconductor region54and an N-type semiconductor region55are formed to serve as a drain and source of the transistor T5, respectively. Over the n-type semiconductor regions54and55, a gate57is formed via an oxide film56.

For the transistor T4, an n-type semiconductor region59and an n-type semiconductor region58are formed to serve as a drain and source of the transistor T4, respectively. Over the n-type semiconductor regions58and59, a gate61is formed via an oxide film60.

For the transistor T3, the NWELL region21ais formed over the p-type semiconductor substrate25. In the NWELL region21a, a p-type semiconductor region62and a p-type semiconductor region63are formed to serve as a drain and source of the transistor T3, respectively. Over the p-type semiconductor regions62and63, a gate65is formed via an oxide film64.

Further, for the transistor T7, the NWELL region23ais formed over the p-type semiconductor substrate25. In the NWELL region23a, a p-type semiconductor region67and a p-type semiconductor region66are formed to serve as a drain and source of the transistor T7, respectively.

Over the p-type semiconductor regions66and67, a gate69is formed via an oxide film68. Still further, the transistors T6and T7are formed in the same manner as for the transistors T4and T5.

In the preferred embodiment 2 arranged as described above, since no DEEP-NWELL region is provided under the sending-side level shift section13aand the receiving-side level shift section14b, there arises no possibility of short-circuiting between the power supply VDD and the power supply VDD2, allowing combinational implementation of DVFS and power consumption control by means of power supply VSS cutoff.

FIG. 13shows an explanatory diagram of an exemplary pulse-latch-type shifter circuits included in a semiconductor integrated circuit device according to a preferred embodiment 3 of the present invention;FIG. 14is a circuit diagram of an exemplary pulse generating section included in the pulse-latch-type shifter circuit inFIG. 13;FIG. 15shows a circuit diagram of an exemplary pulse latch section included in the pulse-latch-type shifter circuit inFIG. 13;FIG. 16shows a timing chart of an exemplary operation of the pulse-latch-type shifter circuit inFIG. 13; andFIG. 17shows an explanatory diagram of an exemplary layout of the pulse-latch-type shifter circuits inFIG. 13.

According to the preferred embodiment 3 of the present invention, pulse-latch-type shifter circuits70and74are used as shown inFIG. 13, in lieu of the sending-side level shift section13aand the receiving-side level shift section14bexemplified in the preferred embodiments 1 and 2 described above.

The pulse-latch-type shifter circuit70is disposed in the circuit block2, for example. In the pulse-latch-type shifter circuit70, an amplitude signal of power supply voltage VDD2is converted into an amplitude signal of power supply voltage VDD, which is then subjected to latching. The pulse-latch-type shifter circuit74is disposed in the circuit block3, for example. In the pulse-latch-type shifter circuit74, an amplitude signal of power supply voltage VDD is converted into an amplitude signal of power supply voltage VDD2, which is then subjected to latching.

The pulse-latch-type shifter circuit70comprises a driver71, a pulse generating section72, and a plurality of pulse latch sections73. The pulse-latch-type shifter circuit74is configured similarly to the pulse-latch-type shifter circuit70.

The pulse latch section73allows a level shift operation on the receiving side only. The pulse-latch-type shifter circuit70in the circuit block2is formed over the DEEP-NWELL region19. The pulse-latch-type shifter circuit74in the circuit block3(4) is formed over the DEEP-NWELL region20.

As shown inFIG. 14, the pulse generating section72comprises a logical AND circuit, inverters Iv1to Iv3, and a logical NAND circuit. One input part of the logical AND circuit is arranged to receive a clock signal4) output via the driver71, and the other input part of the logical AND circuit is arranged to receive an undefined-state prevention signal.

The output part of the logical AND circuit is coupled to the inverters IV1to Iv3arranged in series. The output part of the inverter Iv3is coupled to one input part of the NAND circuit, and the other input part of the NAND circuit is coupled to the output part of the logical AND circuit.

In the circuit configuration mentioned above, the output part of the logical AND circuit serves as an output terminal of the pulse generating section72. A one-shot pulse signal P1(P2), based on a delay operation by the inverters, is output from the pulse generating section72.

Further, as shown inFIG. 15, the pulse latch section73comprises a level conversion part73aand a latch part73b. The level conversion part73ahas a circuit configuration in which p-channel MOS transistors Tr1and Tr2, and n-channel MOS transistors Tr3and Tr4are coupled in series between the power supply VDD and a reference potential. The latch part73bhas a circuit configuration including inverters Iv4and Iv5.

A gate of each of the transistors Tr2and Tr3is arranged to receive an input signal, and a gate of the transistor Tr4is arranged to receive the one-shot pulse signal P1output from the pulse generating section72. A gate of the transistor Tr1is arranged to receive an inverted one-shot pulse signal /P1, which is an inverted signal of the one-shot pulse signal P1.

In the pulse latch section73, when a sending-side circuit block is powered off, a clock signal CK goes Low due to an undefined state of input.

Referring toFIG. 16, there is shown a timing chart of the pulse-latch-type shifter circuit70.

The following signals are indicated in the timing chart ofFIG. 16; clock signal φ1, one-shot pulse signal P1output from the pulse generating section72, input signal D2to the pulse latch section73, and output signal D1from the pulse latch section73.

When a High signal is output from the circuit block3, the one-shot pulse signal P1output from the pulse generating section72and the inverted one-shot pulse signal /P1thereof are input to the gates of the transistors Tr4and Tr1, respectively, thereby causing the level conversion part73ato output a Low signal having a converted voltage level.

The Low signal output from the level conversion part73ais latched by the latch part73b, and then the Low signal thus latched is inverted to a High signal, which is then output from the latch part73bas the D1signal to be input to the circuit block2.

When a Low signal is output from the circuit block3, the level conversion part73aconverts the level of the Low signal to output a High signal having a converted voltage level.

Referring toFIG. 17, there is shown an exemplary layout of the pulse-latch-type shifter circuits70and the pulse-latch-type shifter circuits74. As illustrated inFIG. 17, since each of the pulse-latch-type shifter circuits70and74is fed with power voltage from a single power supply, there arises no possibility of short-circuiting in the DEEP-NWELL region. It is therefore allowed to arrange circuits in the DEEP-NWELL region with a higher degree of freedom in layout design.

In the preferred embodiment 3, since the pulse-latch-type shifter circuit70and the pulse-latch-type shifter circuit74are arranged as described above, a level shift operation is allowed by using logical function blocks on the receiving side only, thereby making it possible to prevent a short-circuit between the power supply VDD and the power supply VDD2.

FIG. 18shows an explanatory diagram of an exemplary circuit arrangement of level shifters and a synchronizing circuit included in a semiconductor integrated circuit device according to a preferred embodiment 4 of the present invention;FIG. 19shows a circuit diagram of an exemplary circuit arrangement in which a path selector is provided at a stage posterior to signal synchronization conducted by the synchronizing circuit inFIG. 18;FIG. 20shows a circuit diagram of an exemplary circuit arrangement of a receiving-side level shift section inFIG. 19;FIG. 21shows an explanatory diagram of an exemplary operation in the circuit arrangement inFIG. 19;FIG. 22shows an explanatory diagram of another exemplary operation in the circuit arrangement inFIG. 19;FIG. 23shows an explanatory diagram of an exemplary operation in the circuit arrangement inFIG. 19under the condition that a sending-side circuit block is powered off;FIG. 24shows a circuit diagram of another exemplary operation in the receiving-side level shift section inFIG. 19; andFIG. 25shows an exemplary diagram of an exemplary circuit arrangement in which the circuit illustrated inFIG. 18is used as a clock signal line circuit.

According to the preferred embodiment 4 of the present invention, as shown inFIG. 18, an output signal from the sending-side level shift section13ais received by the receiving-side level shift section14b, and then a level-converted signal output from the receiving-side level shift section14bis synchronized with a clock signal CKB by a synchronizing circuit75for signal output operation.

Since the power supply VDD and the power supply VDD2have different voltage levels, a latency difference may occur in clock signaling. To prevent this, it is required to carry out synchronization by using the synchronizing circuit75. Over the DEEP-NWELL region20(FIG. 3), the synchronizing circuit75is formed at a succeeding stage of the receiving-side level shift section14b.

Referring toFIG. 19, there is shown a circuit diagram of an exemplary circuit arrangement in which a path selector76is provided at a stage posterior to signal synchronization conducted by the synchronizing circuit75inFIG. 18.

When the voltage levels of the power supply VDD and the power supply VDD2are equal to each other, the path selector76selects a signal path over which an output signal from the circuit block2is input to a logical circuit section of the circuit block3without conditioning through the sending-side level shift section13aand the receiving-side level shift section14b.

The path selector76comprises inverters Iv6and Iv7, and transistors Tr5to Tr12. The transistors Tr5to Tr8are coupled in series between the power supply VDD2and the power supply VSS.

Likewise, the transistors Tr9to Tr12are also coupled in series between the power supply VDD2and the power supply VSS. The transistors Tr5, Tr6, Tr9, and Tr10are formed as p-channel MOS elements, and the transistors Tr7, Tr8, Tr11, and Tr12are formed as n-channel MOS elements.

A select signal PASSSEL output from a voltage setting register or the like is applied to an input part of the inverter Iv6and a gate of each of the transistors Tr8and Tr9.

An output part of the synchronizing circuit75is coupled to a gate of each of the transistors Tr6and Tr7, and an output part of the inverter Iv6is coupled to a gate of each of the transistors Tr5and Tr12.

Further, a gate of each of the transistors Tr10and Tr11is arranged to receive the signal output from the circuit block2. A power electrode part common to the transistors Tr6and Tr7and a power electrode part common to the transistors Tr10and Tr11are coupled to an input part of the inverter Iv7. An output part of the inverter Iv7, which serves as an output terminal of the path selector76, is coupled to the logical circuit section of the circuit block3.

Referring toFIG. 20, there is shown a circuit diagram of an exemplary circuit arrangement of the receiving-side level shift section14binFIG. 19.

As shown inFIG. 20, the receiving-side level shift section14bis provided with an output-enable terminal E for receiving an output-enable signal delivered from the PMU5, for example. The receiving-side level shift section14bis provided with transistors T15and T16, which are additional transistors further included in the circuit arrangement ofFIG. 10according to the preferred embodiment 2.

The transistor T15is formed as an n-channel MOS element, and the transistor T16is formed as a p-channel MOS element. One power electrode part of the transistor T15is coupled to a power electrode part common to the transistors T7and T12, and the other power electrode part of the transistor T15is coupled to the power supply VSS.

One power electrode part of the transistor T16is coupled to the power supply VDD2, and the other power electrode part of the transistor T16is coupled to a power electrode part common to the transistors T6and T7.

Further, a gate of the transistor T15and a gate of the transistor T16are arranged to receive the output-enable signal. When a Low level signal is input to the output-enable terminal E, an output from the receiving-side level shift section14bis fixedly set to a Low level, i.e., the receiving-side level shift section14bis put in a disabled state. Since the other coupling arrangements are similar to those shown inFIG. 10, no repetitive description thereof is given here.

When the voltage levels of the power supply VDD and the power supply VDD2are equal to each other, the select signal PASSSEL output from the voltage setting register or the like is set to a Low state. In this case, as shown inFIG. 21, the transistors Tr9and Tr12turn on to cause the circuit block2to output a node-A signal via the transistors Tr9to Tr12and the inverter Iv7thereof.

In the above-mentioned operation, the Low level signal is input to the output-enable terminal E of the receiving-side level shift section14bso that an output from the receiving-side level shift section14bis fixedly set to a Low level. Since the voltage levels of the power supply VDD and the power supply VDD2are equal to each other, the maximum amplitude level of the node-A signal (gate voltage at the transistors Tr10and Tr11) becomes equal to the voltage level of the power supply VDD2. Hence, even when the transistors9and Tr12are put into conduction, the transistors Tr10and Tr11arranged to form an inverter are not switched into conduction at the same time, thereby preventing a through-current from flowing through a line of the transistors Tr9to Tr12.

Further, when the voltage levels of the power supply VDD and the power supply VDD2are equal to each other, it is not required to perform signal synchronization. Therefore, a clock signal input to the synchronizing circuit75is stopped.

Contrastingly, when the voltage levels of the power supply VDD and the power supply VDD2are different from each other, the select signal PASSSEL is set to a High state. Thus, as shown inFIG. 22, the transistors Tr5and Tr8turn on to allow a signal output from the circuit block2.

That is, a signal is output through the sending-side level shift section13a, the receiving-side level shift section14b, the synchronizing circuit75, the transistors Tr5to Tr8, and the inverter Iv7.

In this case, since the transistors Tr9and Tr12turn off, a through-current does not flow even if “node A” shown inFIG. 22provides an amplitude level of power supply voltage VDD.

Referring toFIG. 23, there is shown an explanatory diagram of an exemplary operation under the condition that the sending-side circuit block2is powered off.

When the sending-side circuit block2is powered off, there occurs a condition that signals on the True and Bar wiring lines of the sending-side level shift section13aand a signal at node A inFIG. 23are undefined.

In this case, the Low level signal is input to the output-enable terminal E, and the select signal PASSSEL is set to a High state. Thus, a Low signal state is fixedly set up in the receiving-side level shift section14b, causing the transistors Tr9and Tr12to turn off. Hence, a through-current does not flow even if “node A” provides an amplitude level of power supply voltage VDD.

Further, while undefined potential processing is performed by the path selector76disposed in the receiving-side circuit block3in the exemplary operation shown inFIG. 23, there may be provided a modified arrangement in which an undefined potential processing circuit77is disposed in the circuit block18serving as an always-on region as shown inFIG. 24, for example.

An input part of the inverter Iv8is arranged to receive a power-off signal STOP to be output from the PMU5when the circuit block2is powered off. An output part of the inverter Iv8is coupled to a gate of each of the transistors T17and T20.

The transistors T17to T19are coupled in series between the power supply VDD and the power supply VSS. One power electrode part of the transistor T20is coupled to a power electrode part common to the transistors T18and T19, and the other electrode part of the transistor T20is coupled to the power supply VSS.

Further, the power electrode part common to the transistors T18and T19is coupled to a gate of each of the transistors Tr10and Tr11.

When the circuit block2is powered off, the power-off signal STOP having a Low level is input to the undefined potential processing circuit77. Thus, the undefined potential processing circuit77outputs a Low-level-fixed signal to turn off the transistors Tr9and Tr12, thereby preventing a through-current from flowing through a line of the transistors Tr9to Tr12.

Furthermore, the present invention is applicable not only to a signal line but also to a clock line for a clock signal CKA such as shown inFIG. 25, for example.

The circuit arrangement exemplified inFIG. 25is similar to that shown inFIG. 19except that the clock signal CKA is sent and received. Operations inFIG. 25are also similar to those inFIG. 19. When the voltage levels of the power supply VDD and the power supply VDD2are equal to each other, it is not required to perform a voltage level conversion operation. Hence, the select signal PASSSEL is set to a Low state to select a path not including the sending-side level shift section13aand the receiving-side level shift section14b.

When the voltage levels of the power supply VDD and the power supply VDD2are different from each other, the select signal PASSSEL is set to a High state to select a path including the sending-side level shift section13aand the receiving-side level shift section14b.

Thus, a latency increase can be prevented in clock signaling to be performed through the sending-side level shift section13a, the receiving-side level shift section14b, and the synchronizing circuit75.

According to the preferred embodiment 4, since a delay time in signal transmission/reception can be reduced, it is possible to enhance the reliability of the semiconductor integrated circuit device1.

While the present invention has been described in detail with respect to specific embodiments thereof, it is to be understood that the present invention is not limited by any of the details of description and that various changes and modifications may be made in the present invention without departing from the spirit and scope thereof.