ARRAY SUBSTRATES AND LIQUID CRYSTAL PANELS

The present disclosure relates to an array substrate and a liquid crystal panel. The array substrate includes a substrate and a plurality of first gate lines, a plurality of second gate lines, and a plurality of data lines arranged on the same side of the substrate, and a plurality of common electrode lines intersecting with the first gate lines. The first gate lines, the second gate lines, and the common electrode lines are parallel to and spaced apart from each other. The adjacent first gate lines and the second gate lines, and two adjacent data lines cooperatively define one pixel area. The pixel area is configured with a first pixel electrode and a second pixel electrode, and a first TFT and second TFT. The first/second pixel electrode and the common electrode are isolated from the first/second insulation layers.

CROSS REFERENCE

This application claims the priority of Chinese Patent Application No. 20161014366.8, entitled “Array substrates and liquid crystal panels”, filed on Mar. 11, 2016, the disclosure of which is incorporated herein by reference in its entirety.

FIELD OF THE INVENTION

The present invention relates to display technology field, and more particularly to an array substrate and a liquid crystal panel.

BACKGROUND OF THE INVENTION

Liquid crystal display (LCD) is a commonly used electronic device characterized by attributes such as low power consumption, small dimension, and light weight, and thus has been widely adopted. Conventionally, the pixels within the LCD include a certain number of display fields, such that the displayable viewing angle is fixed. That is, the liquid crystal panel cannot switch between different viewing angles.

SUMMARY OF THE INVENTION

The technical issue that the embodiment of the present invention solves is to provide a flat panel and flat panel display, achieving the resolution increase of the flat panel display in the same area.

In one aspect, an array substrate includes: a substrate and a plurality of first gate lines, a plurality of second gate lines, and a plurality of data lines arranged on the same side of the substrate, the substrate comprises a first surface, and the first gate lines are arranged on the first surface, the first gate lines extend along a first direction and spaced apart from each other along a second direction, the second gate lines are arranged on the first surface, the second gate lines extend along the first direction, and are spaced apart from each other along the second direction, each of the second gate lines is arranged between two adjacent first gate lines, the array substrate further comprises a plurality of common electrode lines on the first surface, each of the common electrode lines is arranged between adjacent first gate lines and the second gate lines, the adjacent first gate lines and the second gate lines, and two adjacent data lines cooperatively define one pixel area; the array substrate further comprises a first pixel electrode, a second pixel electrode, a first TFT, and a second TFT, the first pixel electrode is isolated from the common electrode lines by a first insulation layer, and the second pixel electrode is isolated from the first pixel electrode by a second insulation layer, a number of the display fields of the second pixel electrode is greater than the number of the display fields of the first pixel electrode, the first gate lines is arranged in the pixel area formed in a rim of the first TFT,the first TFT comprises a first gate area and a first source area, the first gate area electrically connects to the first gate lines forming the pixel area, the first source area electrically connects to the first pixel electrode, the second gate lines is arranged in the pixel area formed in the rim of the second TFT, the second TFT comprises a second gate area and a second drain area, the second gate area electrically connects to the second gate line forming the pixel area, and the second drain area electrically connects to the second pixel electrode, when a condition that the first gate lines receive the scanning signals transitions to the condition that the second gate lines receive the scanning signals, the array substrate transitions from a first viewing angle mode to a second viewing angle mode, when the condition that the second gate lines receives the scanning signals transitions to the condition that the first gate lines receives the scanning signals, the array substrate transitions from the second viewing angle mode to the first viewing angle mode, wherein the viewing angle of the first viewing angle mode is smaller than that of the second viewing angle mode.

Wherein the second pixel electrode comprises a first main branch and a second main branch, and the second main branch intersects with the first main branch to form four display fields, the second pixel electrode within each of the display fields comprises a first sub-branch, a second sub-branch, and a third sub-branch, the first sub-branch extends from the first main branch, the second sub-branch extends from an intersection of the first main branch and the first sub-branch, and the third sub-branch extends from the first sub-branch, and the first sub-branch, the second sub-branch, and the third sub-branch are parallel to each other, and are spaced apart from each other.

Wherein the first main branch and the first sub-branch are perpendicular to each other and intersect with each other, the intersection is at a middle point of the first main branch and of the first sub-branch, the first sub-branch is symmetrical to the third sub-branch with respect to the second sub-branch, a length of the second sub-branch is greater than the length of the first sub-branch, and the length of the second sub-branch is greater than the length of the third sub-branch.

Wherein the first insulation layer covers the first gate area, the second gate area, and the common electrode line, the first pixel electrode is arranged on the first insulation layer, and the first pixel electrode corresponds to the common electrode line, the first TFT further comprises a first trench layer and the first drain area, the first trench layer is arranged above the first insulation layer, the first trench layer corresponds to the first gate area, and the first trench layer and the first pixel electrode are spaced apart from each other, the first source area and the first drain area are arranged at two opposite ends of the first trench layer, and the first source area covers a portion of the first pixel electrode, and the second insulation layer covers the first source area and the first drain area.

Wherein the first TFT also comprises a first ohmic contact layer arranged between the first source area and the first trench layer, and the first ohmic contact layer is configured for reducing the contacting resistance between the first source area and the first trench layer.

Wherein the first ohmic contact layer further comprises a second ohmic contact layer arranged between the first drain area and the first trench layer, the second ohmic contact layer is configured for reducing the contacting resistance between the first drain area and the first trench layer.

Wherein the second TFT comprises a second trench layer and a second source area, the second trench layer is arranged on the first insulation layer, and the second trench layer corresponds to the second gate area, the second trench layer and the first pixel electrode are spaced apart from each other, the second source area and the second drain area are arranged at two opposite ends of the second trench layer, the second drain area and the first pixel electrode are spaced apart from each other, the second insulation layer covers the second source area and the second drain area, the second insulation layer comprises a through hole corresponding to the second drain area, and the second pixel electrode is arranged on the second insulation layer, and the second pixel electrode connects to the second drain area via the through hole.

Wherein the second TFT further comprises a third ohmic contact layer arranged between the second source area and the second trench layer, and the third ohmic contact layer is configured for reducing the contacting resistance between the second source area and the second trench layer.

Wherein the second TFT further comprises a fourth ohmic contact layer arranged between the second drain area and the second trench layer, and the fourth ohmic contact layer is configured for reducing the contacting resistance between the second drain area and the second trench layer.

In another aspect, a liquid crystal panel includes the above liquid crystal panel.

In view of the above, the array substrate10includes a plurality of first gate lines120aand a plurality of second gate lines120b.Each of the second gate lines120bis arranged between two adjacent first gate lines120a.The adjacent first gate lines120aand the second gate lines120b,and two adjacent data lines130cooperatively define one pixel area. On the array substrate10, the first gate lines120a,the second gate lines120b,and the data lines130forms a plurality of pixel areas arranged in a matrix. Each of the pixel areas includes the first TFT150corresponding to the first gate lines120aand a first pixel electrode170a,and each of the pixel areas includes the second TFT160corresponding to the second gate lines120band the second pixel electrode170b.The number of the display fields of the second pixel electrode170bis greater than the number of the display fields of the first pixel electrode170a.When the condition that the first gate lines120areceive the scanning signals transitions to the condition that the second gate lines120breceive the scanning signals, the array substrate10transitions from a first viewing angle mode to a second viewing angle mode. When the condition that the second gate lines120breceives the scanning signals transitions to the condition that the first gate lines120areceives the scanning signals, the array substrate10transitions from the second viewing angle mode to the first viewing angle mode, wherein the viewing angle of the first viewing angle mode is smaller than that of the second viewing angle mode. In this way, the two viewing angle modes are transitions to each other.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Embodiments of the present invention are described in detail with the technical matters, structural features, achieved objects, and effects with reference to the accompanying drawings as follows. It is clear that the described embodiments are part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments to those of ordinary skill in the premise of no creative efforts obtained, should be considered within the scope of protection of the present invention.

FIG. 1is a top view of the array substrate in accordance with one embodiment.FIG. 2is an enlarged view of the first gate line, the second gate line, and the data line formed within one pixel area ofFIG. 1.FIG. 3is a cross sectional view of the structure ofFIG. 2along the II-II line.

The array substrate10includes a substrate110and a plurality of first gate lines120a,a plurality of second gate lines120b,and a plurality of data lines130. The substrate110includes a first surface110a,and the first gate lines120aare arranged on the first surface110a.In addition, the first gate lines120aextend along a first direction (D1) and spaced apart from each other along a second direction (D2). The second gate lines120bare arranged on the first surface110a.The second gate lines120bextend along the first direction (D1), and are spaced apart from each other along the second direction (D2). In addition, each of the second gate lines120bis arranged between two adjacent first gate lines120a.The array substrate10further includes a plurality of common electrode lines140on the first surface110a. Each of the common electrode lines140is arranged between adjacent first gate lines120aand the second gate lines120b.The adjacent first gate lines120aand the second gate lines120b,and two adjacent data lines130cooperatively define one pixel area. On the array substrate10, the first gate lines120a,the second gate lines120b,and the data lines130forms a plurality of pixel areas arranged in a matrix. With respect to one pixel area, the array substrate10further includes a first pixel electrode170a,a second pixel electrode170b,a first TFT150, and a second TFT160. The first pixel electrode170ais isolated from the common electrode lines140by a first insulation layer180a,and the second pixel electrode170bis isolated from the first pixel electrode170aby a second insulation layer180b.The number of the display fields of the second pixel electrode170bis greater than the number of the display fields of the first pixel electrode170a.The first gate lines120ais arranged in the pixel area formed in a rim of the first TFT150. The first TFT150includes a first gate area151and a first source area154. The first gate area151electrically connects to the first gate lines120aforming the pixel area. The first source area154electrically connects to the first pixel electrode170a.The second gate lines120bis arranged in the pixel area formed in the rim of to the second TFT160. The second TFT160includes a second gate area161and a second drain area165. The second gate area161electrically connects to the second gate line120bforming the pixel area, and the second drain area165electrically connects the second pixel electrode170b.When the condition that the first gate lines120areceive the scanning signals transitions to the condition that the second gate lines120breceive the scanning signals, the array substrate10transitions from a first viewing angle mode to a second viewing angle mode. When the condition that the second gate lines120breceives the scanning signals transitions to the condition that the first gate lines120areceives the scanning signals, the array substrate10transitions from the second viewing angle mode to the first viewing angle mode, wherein the viewing angle of the first viewing angle mode is smaller than that of the second viewing angle mode. The first direction (D1) may be x-axis, and the second direction (D2) may be y-axis.

Specifically, when the first gate lines120areceives the scanning signals, the first gate area151of the first TFT150electrically connects to the first gate lines120a,and the first drain area155of the first TFT150electrically connects to the first pixel electrode170a.Thus, the scanning signals are loaded on the first pixel electrode170avia the first TFT150. At this moment, a first electrical field is formed between the first pixel electrode170aand the common electrode lines140. When the same scanning signals are loaded on the second gate lines120b,that is, the second gate lines120breceive the scanning signals, as the second gate area161of the second TFT160electrically connects to the second gate lines120band the second gate area161of the second TFT160electrically connects to the second pixel electrode170b,the scanning signals are loaded on the second pixel electrode170bvia the second TFT160. At this moment, a second electrical field is formed between the second pixel electrode170band the common electrode lines140. As the number of the display fields of the second pixel electrode170bis greater than the number of the display fields of the first pixel electrode170a,the second electrical field is more divergent than the first electrical field. For the reason, when the array substrate10is adopted in the LCD, the rotating angle of the liquid crystal molecules within the LCD may be larger, such that the viewing angle of the second viewing angle mode is greater than the viewing angle of the first viewing angle mode. Usually, the first viewing angle mode may also be referred to as a narrow viewing angle mode, and the second viewing angle mode may also be referred to as a wide viewing angle mode. When the condition that the second gate lines120areceives the scanning signals transitions to the condition that the first gate lines120breceives the scanning signals, the array substrate10transitions from the narrow viewing angle mode to the wide viewing angle mode. At this moment, the viewing angle of the array substrate10is wider. When the condition that the second gate lines120breceives the scanning signals transitions to the condition that the first gate lines120areceives the scanning signals, the array substrate10transitions from the narrow viewing angle mode to the wide viewing angle mode. At this moment, the viewing angle of the array substrate10is narrower.

FIG. 4is a schematic view of the second pixel electrode ofFIG. 2. The second pixel electrode170bincludes a first main branch171and a second main branch172, and the second main branch172intersects with the first main branch171to form four display fields, wherein the dashed rectangle indicates one display field. The second pixel electrode170bwithin each of the display fields includes a first sub-branch173, a second sub-branch174, and a third sub-branch175. The first sub-branch173extends from the first main branch171, the second sub-branch174extends from an intersection of the first main branch171and the first sub-branch172, and the third sub-branch175extends from the first sub-branch172. In addition, the first sub-branch173, the second sub-branch174, and the third sub-branch175are parallel to each other, and are spaced apart from each other. In the embodiment, the number of the display field of the170athe number of the display field of the first pixel electrode170ais one.

In the embodiment, the first main branch171and the first sub-branch172are perpendicular to each other and intersect with each other. The intersection is at a middle point of the first main branch171and of the first sub-branch172. The first sub-branch173is symmetrical to the third sub-branch175with respect to the second sub-branch174. In addition, the length of the second sub-branch174is greater than the length of the first sub-branch173, and the length of the second sub-branch174is greater than the length of the third sub-branch175. Preferably, the length of the first sub-branch173is equal to the length of the third sub-branch175.

Referring toFIG. 3, the first insulation layer180acovers the first gate area151, the second gate area161, and the common electrode line140. The first pixel electrode170ais arranged on the first insulation layer180a,and the first pixel electrode170acorresponds to the common electrode line140. The first TFT150further includes a first trench layer153and the first drain area155. The first trench layer153is arranged above the first insulation layer180a,the first trench layer153corresponds to the first gate area151, and the first trench layer153and the first pixel electrode170aare spaced apart from each other. The first source area154and the first drain area155are arranged at two opposite ends of the first trench layer153, and the first source area154covers a portion of the first pixel electrode170a. The second insulation layer180bcovers the first source area154and the first drain area155.

The first TFT150also includes a first ohmic contact layer156arranged between the first source area154and the first trench layer153. The first ohmic contact layer156is configured for reducing the contacting resistance between the first source area154and the first trench layer153.

The first ohmic contact layer156further includes a second ohmic contact layer157arranged between the first drain area and the first trench layer153. The second ohmic contact layer157is configured for reducing the contacting resistance between the first drain area155and the first trench layer153. It can be understood that the first TFT150may only include the first ohmic contact layer156or the second ohmic contact layer157. Alternatively, the first TFT150may include the first ohmic contact layer156and the second ohmic contact layer157.

The second TFT160includes a second trench layer163and a second source area164. The second trench layer163is arranged on the first insulation layer180a,and the second trench layer163corresponds to the second gate area161. The second trench layer163and the first pixel electrode170aare spaced apart from each other. The second source area164and the second drain area165are arranged at two opposite ends of the second trench layer163. The second drain area165and the first pixel electrode170aare spaced apart from each other. The second insulation layer180bcovers the second source area164and the second drain area165. The second insulation layer180bincludes a through hole181corresponding to the second drain area165, and the second pixel electrode170bis arranged on the second insulation layer180b.In addition, the second pixel electrode170bconnects to the second drain area165via the through hole181.

The second TFT160further includes a third ohmic contact layer166arranged between the second source area164and the second trench layer163. The third ohmic contact layer166is configured for reducing the contacting resistance between the second source area164and the second trench layer163.

The second TFT160further includes a fourth ohmic contact layer167arranged between the second drain area165and the second trench layer163. The fourth ohmic contact layer167is configured for reducing the contacting resistance between the second drain area165and the second trench layer163. It can be understood that the second TFT160may only include the third ohmic contact layer166or the fourth ohmic contact layer167. Alternatively, the second TFT160may include the third ohmic contact layer166and the fourth ohmic contact layer167.

In the embodiment, the first source area154and the second drain area165connect to the data lines130to receive the data signals of the data lines130.

In the embodiment, the substrate110may be a transparent insulation substrate including, but not limited to, a glass substrate or a plastic substrate.

The first gate lines120a,the second gate lines120b,and the common electrode line140may be formed by the method below. A first metal layer is arranged on a first surface111aof the substrate110. The first metal layer includes, but not limited to, any one or some of Al, Mo, and Cu. The first metal layer may be formed by Physical Vapor Deposition (PVD). The thickness of the first metal layer may be in a range from 3000 to 6000 angstrom. Afterward, the first metal layer is patterned to form the120a,the second gate lines120b,and the common electrode lines140. The pattern of the first metal layer may be formed by exposure, development, etching, or stripping via a mask.

The first insulation layer180amay be formed by Plasma Enhanced Chemical Vapor Deposition (PECVD) to deposit an insulation layer having a thickness in a range from 2000 to 5000 angstroms. The insulation layer may be, but not limited to, SiNx.

The first trench layer153, the second trench layer163, the first ohmic contact layer156, the second ohmic contact layer157, the third ohmic contact layer166, and the fourth ohmic contact layer167may be made by the methods below. First, an a-si layer is deposited on the first insulation layer180avia PECVD, the thickness of the a-si layer is in a range from 1500 to 3000 angstroms. The patterning process is then applied to the a-si layer to maintain the portion of the a-si layer corresponding to the first gate area151and corresponding to the second gate area161. To simply the descriptions, the portion of the a-si layer corresponding to the first gate area151is referred to as a first a-si portion, and the portion of the a-si layer corresponding to the second gate area161is referred to as a second a-si portion. An ion-doping process is applied to two ends of the first a-si portion to form the first ohmic contact layer156and the second ohmic contact layer157, and the area of the first a-si portion that has not been applied with the ion-doping is the first trench layer153. The ion-doping process is applied to two ends of the second a-si portion to form the third ohmic contact layer166and the fourth ohmic contact layer167, and the area of the second a-si portion that has not been applied with the ion-doping is the second trench layer163. In one embodiment, the ion doping process relates to N-type ion-doping.

The first source area154, the first drain area155, the second source area164, and the second drain area165may be formed by the method below. A second metal layer is formed. The second metal layer includes any one or some of the Al, Mo, and Cu. The second metal layer may be formed by PVD. The thickness of the second metal layer may be in a range from 3000 to 6000 angstrom. Afterward, the second metal layer is patterned to form the first source area154, the first drain area155, the second source area164, and the second drain area165. The pattern of the second metal layer may be formed by exposure, development, etching, or stripping via a mask.

The second insulation layer180bmay be formed by PECVD to deposit an insulation layer having a thickness in a range from 2000 to 5000 angstroms. The insulation layer may be, but not limited to, SiNx. The through hole181of the second may be formed by exposure, development, etching, or stripping via a mask.

The first pixel electrode170aand the second pixel electrode may be formed by the method below. The PVD method is adopted to deposit transparent conductive material having the thickness in a range from 400 to 1000 angstroms. Afterward, the exposure, development, etching, or stripping process is adopted with the mask. The transparent conductive material may be, but not limited to, Indium Tin Oxide (ITO).

The present disclosure also relates to a liquid crystal panel.FIG. 5is a schematic view of the liquid crystal panel in accordance with one embodiment. The liquid crystal panel1includes an array substrate10, a CF substrate20, and a liquid crystal layer30. The array substrate10is opposite to the CF substrate20, and the array substrate10and the CF substrate20are spaced apart from each other. The liquid crystal layer30is arranged between the array substrate10and the CF substrate20. The array substrate10may be the array substrates in the above.

In view of the above, the array substrate10includes a plurality of first gate lines120aand a plurality of second gate lines120b.Each of the second gate lines120bis arranged between two adjacent first gate lines120a.The adjacent first gate lines120aand the second gate lines120b,and two adjacent data lines130cooperatively define one pixel area. On the array substrate10, the first gate lines120a,the second gate lines120b,and the data lines130forms a plurality of pixel areas arranged in a matrix. Each of the pixel areas includes the first TFT150corresponding to the first gate lines120aand a first pixel electrode170a,and each of the pixel areas includes the second TFT160corresponding to the second gate lines120band the second pixel electrode170b.The number of the display fields of the second pixel electrode170bis greater than the number of the display fields of the first pixel electrode170a.When the condition that the first gate lines120areceive the scanning signals transitions to the condition that the second gate lines120breceive the scanning signals, the array substrate10transitions from a first viewing angle mode to a second viewing angle mode. When the condition that the second gate lines120breceives the scanning signals transitions to the condition that the first gate lines120areceives the scanning signals, the array substrate10transitions from the second viewing angle mode to the first viewing angle mode, wherein the viewing angle of the first viewing angle mode is smaller than that of the second viewing angle mode. In this way, the two viewing angle modes are transitions to each other.