LINEAR REGULATOR CIRCUIT

Disclosed here is a linear regulator circuit including an input line, an output line, a P-channel output transistor connected between the input line and the output line, a feedback circuit that performs feedback control on a gate voltage of the output transistor such that an output voltage of the output line approaches a target level, and a protective circuit that clamps the gate voltage of the output transistor such that the gate voltage does not fall below a voltage level lower than the output voltage by a predetermined voltage.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority benefit of Japanese Patent Application No. JP 2021-122230 filed in the Japan Patent Office on Jul. 27, 2021. Each of the above-referenced applications is hereby incorporated herein by reference in its entirety.

BACKGROUND

The present disclosure relates to a linear regulator.

Various electronic circuits and electronic devices use a linear regulator circuit in order to generate a voltage that maintains a fixed voltage level without depending on a power supply voltage (input voltage).

An example of the related art is disclosed in Japanese Patent Laid-open No. 2007-157070.

SUMMARY

Depending on uses, an input voltage VINof the linear regulator circuit may vary greatly. When the input voltage VINbecomes lower than a target voltage level VOUT(REF)of an output voltage VOUT, a gate voltage VPGof an output transistor of the linear regulator circuit is greatly lowered by feedback. At this time, the output transistor is fully on, and thus VOUT=VIN.

When the input voltage VINrises sharply to a voltage level higher than the target level VOUT(REF)from this state while the output transistor is fully on, the output voltage VOUTrises so as to follow the input voltage VIN, so that an overshoot occurs.

The present disclosure has been made in view of such circumstances. As a certain example of the present disclosure, it is desirable to provide a linear regulator circuit that can suppress an overshoot.

A linear regulator circuit according to a certain example of the present disclosure includes an input line, an output line, a P-channel output transistor connected between the input line and the output line, a feedback circuit that performs feedback control on a gate voltage of the output transistor such that an output voltage of the output line approaches a target level, and a protective circuit that clamps the gate voltage of the output transistor such that the gate voltage does not fall below a voltage level lower than the output voltage by a predetermined voltage.

Another example of the present disclosure is also a linear regulator circuit. This linear regulator circuit includes an input line, an output line, a P-channel output transistor connected between the input line and the output line, a feedback circuit that performs feedback control on a gate voltage of the output transistor such that an output voltage of the output line approaches a target level, and a protective circuit that is connected between the output line and a gate of the output transistor, and conducts and supplies a current from the output line to the gate of the output transistor when a potential difference between the output voltage and the gate voltage exceeds a predetermined voltage.

It is to be noted that any combinations of the above constituent elements as well as examples obtained by mutually replacing constituent elements and expressions between a method, a device, a system, and the like are also effective as examples of the present invention. Further, the description of this section does not describe all of essential features of the present invention, and therefore, subcombinations of these features described can be the present invention.

According to a certain example of the present disclosure, an overshoot can be suppressed.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Outline of Embodiments

An outline of a few illustrative embodiments of the present disclosure will be described. This outline describes, in a simplified manner, a few concepts of one or a plurality of embodiments as an introduction to the following detailed description for a purpose of basic understanding of the embodiments, and does not limit the scope of the invention or the disclosure. This outline is neither a comprehensive outline of all conceivable embodiments nor intended to identify important elements of all of the embodiments or to demarcate the scope of a part or all of examples. For convenience, “one embodiment” may be used to refer to one embodiment (an example or a modification) or a plurality of embodiments (examples or modifications) disclosed in the present specification.

A linear regulator circuit according to one embodiment includes an input line, an output line, a P-channel output transistor connected between the input line and the output line, a feedback circuit that performs feedback control on a gate voltage of the output transistor such that an output voltage of the output line approaches a target level, and a protective circuit that clamps the gate voltage of the output transistor such that the gate voltage does not fall below a voltage level lower than the output voltage by a predetermined voltage.

When an input voltage VINbecomes lower than a target voltage level VOUT(REF)of the output voltage VOUT, the feedback circuit tries to lower the gate voltage VPGof the output transistor of the linear regulator circuit. However, the gate voltage VPGis clamped by the protective circuit so as not to fall below the voltage level (clamp level) lower than the output voltage VOUTby the predetermined voltage Δ.

Supposing that VPG=VOUT−ΔV and VOUT≈VINhold, a gate-to-source voltage VGSof the output transistor is clamped at ΔV. Suppose that the input voltage VINsharply rises to a voltage level higher than the target level VOUT(REF)from this state. Because the gate-to-source voltage VGSof the output transistor is immediately previously clamped at ΔV, an overshoot of the output voltage VOUTcan be suppressed even when the input voltage VINrises.

In one embodiment, the protective circuit may be connected between the output line and a gate of the output transistor, and may conduct and supply a current from the output line to the gate of the output transistor when a potential difference between the output voltage and the gate voltage exceeds a predetermined voltage. According to this configuration, the current flowing from the output line via the protective circuit can raise the gate voltage of the output transistor. The output voltage does not change even when the current is supplied from a path other than the output line to the gate of the output transistor. However, in this configuration, the current flowing from the output line to the gate acts in a direction of decreasing the output voltage, and can therefore further suppress the overshoot.

A linear regulator circuit according to one embodiment includes an input line, an output line, a P-channel output transistor connected between the input line and the output line, a feedback circuit that performs feedback control on a gate voltage of the output transistor such that an output voltage of the output line approaches a target level, and a protective circuit that is connected between the output line and a gate of the output transistor, and conducts and supplies a current from the output line to the gate of the output transistor when a potential difference between the output voltage and the gate voltage exceeds a predetermined voltage.

In one embodiment, the protective circuit may include a gate element that conducts when a voltage across the gate element exceeds a threshold voltage.

In one embodiment, the gate element may include a P-channel transistor having a gate and a drain connected to each other.

In one embodiment, the protective circuit may include a current source that becomes active when a voltage across the current source exceeds a threshold voltage.

In one embodiment, the protective circuit may include a rectifying element that allows a flow of a current going from the output line to the gate of the output transistor, and interrupts an opposite current.

In one embodiment, the rectifying element may include a field-effect transistor having a gate and a source connected to each other.

In one embodiment, the rectifying element may include a diode.

In one embodiment, the protective circuit may include a switch that is off when the linear regulator circuit is disabled.

In one embodiment, the protective circuit may include a switch that is off when the gate voltage of the output transistor is higher than a predetermined threshold value.

In one embodiment, the linear regulator circuit may be integrated on one semiconductor substrate. “Integrated” includes a case where all of circuit constituent elements are formed on the semiconductor substrate and a case where main circuit constituent elements are integrated. A part of resistances, capacitors, and the like may be provided outside the semiconductor substrate for adjustment of circuit constants. Integrating the circuit on one chip can reduce a circuit area, and hold characteristics of the circuit elements uniform.

Embodiment

A preferred embodiment will hereinafter be described with reference to the drawings. Identical or equivalent constituent elements, members, and processing depicted in each drawing are identified by the same reference numerals, and repeated description thereof will be omitted as appropriate. In addition, the embodiment is not restrictive of the invention but is illustrative, and all features described in the embodiment and combinations thereof are not necessarily essential to the invention.

In the present specification, a “state in which a member A is connected to a member B” includes a case where the member A and the member B are physically directly connected to each other and a case where the member A and the member B are indirectly connected to each other via another member that does not affect an electrically connected state or does not hamper functions.

Similarly, a “state in which a member C is provided between the member A and the member B” includes not only a case where the member A and the member C or the member B and the member C are directly connected to each other but also a case where the member A and the member C or the member B and the member C are indirectly connected to each other via another member that does not affect an electrically connected state or does not hamper functions.

In addition, a description that a “signal A (voltage or current) is according to a signal B (voltage or current)” means that the signal A has correlation to the signal B, and specifically means (i) a case where the signal A is the signal B, (ii) a case where the signal A is in proportion to the signal B, (iii) a case where the signal A is obtained by level-shifting the signal B, (iv) a case where the signal A is obtained by amplifying the signal B, (v) a case where the signal A is obtained by inverting the signal B, (vi) a freely selected combination thereof, or the like. It is understood by those skilled in the art that the scope of “according” is determined according to kinds and uses of the signals A and B.

Axes of ordinates and axes of abscissas in waveform charts and timing diagrams referred to in the present specification are enlarged or reduced as appropriate in order to facilitate understanding, and each waveform depicted therein is simplified or exaggerated or emphasized in order to facilitate understanding.

FIG.1is a circuit diagram of a linear regulator circuit100according to an embodiment. The linear regulator circuit100receives an input voltage VINat an input terminal IN (input line102), generates an output voltage VOUTstabilized at a predetermined target level VOUT(REF), and supplies the output voltage VOUTto a load (not depicted) connected to an output terminal OUT (output line104). The linear regulator circuit100is referred to also as a low drop output (LDO).

The linear regulator circuit100is integrated on one semiconductor substrate. The linear regulator circuit100may be an integrated circuit (IC) of the linear regulator circuit alone, or may be an internal power supply included in an IC having another function.

The linear regulator circuit100includes an output transistor110, a feedback circuit120, and a protective circuit130. The output transistor110is a P-channel metal oxide semiconductor field effect transistor (MOSFET). The output transistor110has a source thereof connected to the input line102, and has a drain thereof connected to the output line104. In addition, an output capacitor C1is connected to the output line104.

The feedback circuit120performs feedback control on the gate voltage VPGof the output transistor110such that the voltage of the output line104approaches a target level. For example, the feedback circuit120includes resistances R11and R12and an error amplifier112. The resistances R11and R12generate a feedback voltage VFBby voltage-dividing the output voltage VOUT. The error amplifier112generates the gate voltage VPGof the output transistor110by amplifying an error between the feedback voltage VFBand a reference voltage VREF. The feedback circuit120stabilizes the output voltage VOUTat the target level VOUT(REF)determined according to the reference voltage VREF.

The protective circuit130clamps the gate voltage VPGof the output transistor110such that the gate voltage VPGdoes not fall below a voltage level (referred to as a clamp level) lower than the output voltage VOUToccurring in the output line104by a predetermined voltage ΔV.

Preferably, the protective circuit130is connected between the output line104and the gate of the output transistor110, and is configured to conduct and supply a current Ix from the output line104to the gate of the output transistor110when a potential difference between the output voltage VOUTand the gate voltage VPGexceeds the predetermined voltage ΔV.

The above is the configuration of the linear regulator circuit100. Operation thereof will next be described. Advantages of the linear regulator circuit100are clarified by comparison with a comparative technology. Accordingly, a description will first be made of an overshoot occurring in a linear regulator circuit according to the comparative technology.

FIG.2is an operation waveform chart of a linear regulator circuit100R according to the comparative technology. The linear regulator circuit100R according to the comparative technology is obtained by omitting the protective circuit130from the linear regulator circuit100ofFIG.1.

Before time to, the input voltage VINhas a voltage level V0higher than the target level VOUT(REF)of the output voltage VOUT. The gate voltage VPGof the output transistor110at this time is a voltage level VPG0.

For a period of time t1to t2, the input voltage VINhas a voltage level V1lower than the target level VOUT(REF)of the output voltage VOUT. At this time, due to feedback by the feedback circuit120, the gate voltage VPGof the output transistor110is lowered to a voltage level (0 V in the present example) VPG1lower than the output voltage VOUT, and the output transistor110is in a fully on state. The output voltage VOUTassumes a voltage level close to the input voltage VIN(=V1).

Suppose that the input voltage VINrises sharply toward the original voltage level V0higher than the target level VOUT(REF)of the output voltage VOUTat time t2. Due to a response delay of the feedback circuit120, the gate voltage VPGis delayed in changing from VPG1to VPG0. During this delay, the output transistor110is fully on, and therefore, a relation VOUT≈VINholds. When the input voltage VINrises while the relation VOUT≅VINis maintained, the output voltage VOUTrises so as to follow the rise in the input voltage VIN. Thereafter, due to feedback by the feedback circuit120, when the gate voltage VPGapproaches VPG0, the output voltage VOUTapproaches the target level VOUT(REF).

Thus, in the comparative technology, when the input voltage VINrises sharply, the output voltage VOUTovershoots.

Operation of the linear regulator circuit100will next be described.FIG.3is an operation waveform chart of the linear regulator circuit100ofFIG.1.

A state before time to is similar to that ofFIG.2(comparative technology). The input voltage VINhas a voltage level V0higher than the target level VOUT(REF)of the output voltage VOUTThe gate voltage VPGof the output transistor110at this time is higher than a clamp level VCLbased on the output voltage VOUT, and is therefore at the same voltage level VPG0as inFIG.2without being affected by the protective circuit130.

For a period of time t1to t2, the input voltage VINhas a voltage level V1lower than the target level VOUT(REF)of the output voltage VOUT. At this time, the feedback circuit120tries to lower the gate voltage VPGto the voltage level VPG0inFIG.2. However, the protective circuit130conducts and supplies a current Ix from the output line104to the gate of the output transistor110when a potential difference VOUT−VPGbetween the output voltage VOUTand the gate voltage VPGexceeds a predetermined voltage ΔV. The supply of the current Ix raises the gate voltage VPGof the output transistor110, and holds the potential difference from the output voltage VOUTfixed at ΔV. At this time, the gate voltage VPGis clamped by the clamp level VCL=VOUT−ΔV. The gate-to-source voltage VGSof the output transistor110in the period of time t1to t2is small as compared with that of the comparative technology (FIG.2).

At time t2, the input voltage VINrises sharply toward the original voltage level V0higher than the target level VOUT(REF)of the output voltage VOUTThe gate-to-source voltage VGSof the output transistor110at this time is small as compared with the comparative technology. Thus, even when the input voltage VINrises, an amount of increase in the output voltage VOUTis suppressed as compared with the comparative technology. An overshoot can thereby be suppressed.

In addition, in the present embodiment, a time taken for the gate voltage VPGto reach the voltage level VPG0after time t2is shortened as compared with the comparative technology. An overshoot can be thereby suppressed.

In addition, the protective circuit130has a configuration for supplying the current Ix from the output line104to the gate of the output transistor110. This current Ix is supplied from the output capacitor C1. Thus, the current Ix decreases the output voltage VOUT, or acts also in a direction of suppressing an overshoot of the output voltage VOUTHence, the effect of overshoot suppression is stronger than a case where the current Ix for raising the gate voltage VPGis supplied from a part (for example, the input line102) other than the output line104.

Operation of the linear regulator circuit100has been described above.

The present disclosure covers various devices and methods grasped as the block diagram or circuit diagram ofFIG.1or derived from the above description, and is not limited to a specific configuration. In the following, more specific configuration examples and embodiments will be described not to narrow the scope of the present disclosure but to facilitate understanding of essences and operation of the present disclosure or the present invention and clarify the essences and operation of the present disclosure or the present invention.

First Embodiment

FIG.4is a circuit diagram of a linear regulator circuit100A according to a first embodiment. A protective circuit130A includes a gate element132. The gate element132is in a shut-off state when a voltage across the gate element132is smaller than the threshold voltage VTHThe gate element132conducts when the voltage across the gate element132exceeds the threshold voltage VTH. The threshold voltage VTHis set according to ΔV. When the gate element132conducts, the current Ix flows from the output line104to the gate of the output transistor110, and the gate voltage VPGis clamped.

Second Embodiment

FIG.5is a circuit diagram of a linear regulator circuit100B according to a second embodiment. A protective circuit130B includes a rectifying element134in addition to the gate element132. When the gate element132is formed by using a MOSFET or the like, the gate element132is in a state of conducting in an opposite direction at all times because of the presence of a body diode (parasitic diode) BD. Hence, in a state in which the gate voltage VPGof the output transistor110is higher than the output voltage VOUT, a current flows from the gate of the output transistor110to the output line104, which is not desirable.

In addition, there is a possibility of the body diode BD of the gate element132generating a non-zero output voltage VOUTin the output line104while the linear regulator circuit100B is stopped.

The rectifying element134is provided to eliminate the effects of the body diode BD of the gate element132. The rectifying element134allows a flow of the current Ix going from the output line104to the gate of the output transistor110, and interrupts an opposite current.

FIG.6is a circuit diagram depicting a specific example of a configuration (100C) of the linear regulator circuit100B inFIG.5. A protective circuit130C includes a P-channel transistor MP1corresponding to the gate element132and an N-channel transistor MN1corresponding to the rectifying element134.

The source of the P-channel transistor MP1is connected to the output line104. The gate and drain of the P-channel transistor MP1are connected to each other. When a voltage across the P-channel transistor MP1(drain-to-source voltage) becomes higher than a gate threshold value Vt of the P-channel transistor MP1, the P-channel transistor MP1is turned on, and the current Ix flows.

The P-channel transistor MP1can conduct in an opposite direction at all times due to the body diode of the P-channel transistor MP1.

The source of the N-channel transistor MN1is connected to the drain of the P-channel transistor MP1. The drain of the N-channel transistor MN1is connected to the gate of the output transistor110. The gate and source of the N-channel transistor MN1are connected to each other. Hence, the channel of the N-channel transistor MN1is shut off at all times, and does not contribute to the operation of the protective circuit130C. The body diode of the N-channel transistor MN1interrupts the current going from the gate of the output transistor110to the output line104.

The protective circuit130C conducts, and the current Ix flows when a potential difference between the output voltage VOUTand the gate voltage VPGexceeds ΔV defined by Vf+Vt, where Vf is a forward voltage of the body diode of the transistor MN1, and Vt is the threshold voltage of the P-channel transistor MP1.

Third Embodiment

FIG.7is a circuit diagram of a linear regulator circuit100D according to a third embodiment. A protective circuit130D includes a switch136in place of the rectifying element134inFIG.5. An enable signal EN of the linear regulator circuit100D is input to the switch136. The switch136is on during operation of the linear regulator circuit100D. While the linear regulator circuit100D is stopped, the switch136is off, and therefore, the occurrence of a nonzero output voltage VOUTin the output line104can be prevented.

Fourth Embodiment

FIG.8is a circuit diagram of a linear regulator circuit100E according to a fourth embodiment. A protective circuit130E includes a switch138. A reverse current flows in the protective circuit130D when VPG>VOUT, that is, when VPG>VOUT(REF). A comparator COMP1compares the gate voltage VPGwith the threshold voltage VTH. The comparator COMP1turns off the switch138when VPG>VTH, and turns on the switch138when VPG<VTH. It suffices to define the threshold value VTHaccording to the target level VOUT(REF)of the output voltage VOUT.

Modifications

The foregoing embodiments are illustrative, and it is understood by those skilled in the art that combinations of constituent elements and processes of those embodiments are susceptible of various modifications. Such modifications will be described in the following.

With regard to the protective circuit130, the positions of the gate element132and the rectifying element134may be interchanged. In addition, inFIG.6, the gate element132may be formed by an N-channel transistor, and the rectifying element134may be formed by a P-channel transistor.

The gate element132is not limited to a MOS transistor.FIG.9is a circuit diagram depicting modifications of the protective circuit130. The gate element132may, for example, be a current source that becomes active and generates the current Ix when a voltage across the current source exceeds a threshold value. Alternatively, the gate element132may be a Zener diode ZD1. In addition, the gate element132may be a diode formed by using a bipolar transistor.

The embodiments are illustrative, and it is to be understood by those skilled in the art that there are various modifications of combinations of constituent elements and processes of those embodiments and that such modifications are also included in the scope of the present disclosure or the present invention.