Thin film transistor and display device including the same

One object of the present invention is reduction of off current of a thin film transistor. Another object of the present invention is improvement of electric characteristics of the thin film transistor. Further, another object of the present invention is improvement of image quality of the display device including the thin film transistor. The thin film transistor includes a semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or a conductive film which is provided over a gate electrode with the gate insulating film interposed therebetween and which is provided in an inner region of the gate electrode so as not to overlap with an end portion of the gate electrode, a film covering at least a side surface of the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film, a pair of wirings formed over the film covering the side surface of the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a thin film transistor and a display device using the thin film transistor at least in a pixel portion.

2. Description of the Related Art

In recent years, techniques for forming a thin film transistor using a semiconductor thin film (with a thickness of about several tens to several hundreds of nanometers) which is formed over a substrate having an insulating surface have attracted attention. A thin film transistor is widely used in an electronic device such as ICs and electro-optical devices, and their development especially as a switching element for a display device has been accelerated.

As a switching element of a display device, a thin film transistor using an amorphous semiconductor film for a channel formation region, a thin film transistor using a polycrystalline semiconductor film with a crystal grain diameter of 100 nm or more for a channel formation region, or the like is used. As a method for forming a polycrystalline semiconductor film, a technique is known in which a pulsed excimer laser beam is shaped into a linear laser beam with an optical system and an amorphous silicon film is crystallized by being scanned and irradiated with the linear laser beam.

As a switching element of a display device, a thin film transistor using a microcrystalline semiconductor film with a crystal grain diameter of less than 100 nm for a channel formation region is also used (see Reference 1: Japanese Published Patent Application No. H4-242724 and Reference 2: Japanese Published Patent Application No. 2005-49832).

SUMMARY OF THE INVENTION

A thin film transistor using a polycrystalline semiconductor film for a channel formation region has advantages in that its field effect mobility is two or more orders of magnitude greater than that of a thin film transistor using an amorphous semiconductor film for a channel formation region and a pixel portion of a display device and peripheral driver circuits thereof can be formed over the same substrate. However, the thin film transistor using a polycrystalline semiconductor film requires a more complicated process than the thin film transistor including an amorphous semiconductor film because of crystallization of the semiconductor film. Thus, there are problems such as reduction in yield and increase in cost.

Further, an inverted staggered thin film transistor using a microcrystalline semiconductor film for a channel formation region has problems in that the crystallinity of an interface region between a gate insulating film and the microcrystalline semiconductor film is low and electric characteristics of the thin film transistor are poor.

In addition, an inverted staggered thin film transistor using a microcrystalline semiconductor film for a channel formation region can improve ON current compared to an inverted staggered thin film transistor using an amorphous semiconductor film for a channel formation region; however, off current also increases. A display device using thin film transistors having high off current has a problem in that contrast decreases and power consumption increases.

In view of the above problems, it is an object of the present invention to reduce off current of a thin film transistor. In addition, it is another object of the present invention to improve electric characteristics of a thin film transistor. Further, it is still another object of the present invention to improve image quality of a display device using the thin film transistor.

One aspect of the present invention is a thin film transistor including a semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or a conductive film which is provided over a gate electrode with a gate insulating film interposed therebetween and which is provided in an inner region of the gate electrode so as not to overlap with an end portion of the gate electrode, a film covering at least a side surface of the semiconductor film containing germanium at a concentration ranging greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film, and a pair of wirings formed over the film covering the side surface of the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film. The film covering the side surface of the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film is an amorphous semiconductor film or an insulating film. Further an impurity semiconductor film to which an impurity element imparting one conductivity type is added, which forms a source region and a drain region, may be formed in contact with the film covering the side surface of the semiconductor film or the conductive film.

Another aspect of the present invention is a thin film transistor including a semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or a conductive film which is provided over a gate electrode with an insulating film interposed therebetween and which is provided in an inner region of the gate electrode so as not to overlap with an end portion of the gate electrode, an amorphous semiconductor film covering a top surface and a side surface of the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film, and an impurity semiconductor film to which an impurity element imparting one conductivity type is added, which forms a source region and a drain region formed over the amorphous semiconductor film. Note that an end portion of the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film on the source and drain regions side may overlap with the amorphous semiconductor film and the impurity semiconductor film. Further, an end portion of the amorphous semiconductor film may be located beyond the source and drain regions.

Further, in the present invention described above, an amorphous semiconductor film which is different from the above-described amorphous semiconductor film may be provided on the top surface of the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film.

Another aspect of the present invention is a thin film transistor including a semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or a conductive film which is provided over a gate electrode with a gate insulating film interposed therebetween and which is provided in an inner region of the gate electrode so as not to overlap with an end portion of the gate electrode, an amorphous semiconductor film formed over the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film, an impurity semiconductor film formed over the amorphous semiconductor film to which an impurity element imparting one conductivity type is added and which forms source and drain regions, an insulating film covering a side surface of the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film, an insulating film covering a side surface of the amorphous film and a side surface of the impurity semiconductor film, and a pair of wirings which are formed over the insulating film and in contact with the impurity semiconductor film.

Another aspect of the present invention is a thin film transistor including a semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or a conductive film which is provided over a gate electrode with a gate insulating film interposed therebetween and which is provided in an inner region of the gate electrode so as not to overlap with an end portion of the gate electrode, an amorphous semiconductor film formed over the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film, an insulating film covering a side surface of the semiconductor film and a side surface of the amorphous semiconductor film, an impurity semiconductor film to which an impurity element imparting one conductivity type is added, which forms a source region and a drain region formed over the insulating film, and a pair of wirings in contact with the impurity semiconductor film.

Note that an end portion of the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film on the source region and the drain region side overlap with the insulating film.

As the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. %, an amorphous germanium film, an amorphous silicon germanium film, a microcrystalline germanium film, a microcrystalline silicon germanium film, a polycrystalline germanium film, a polycrystalline silicon germanium film, or the like is employed. Further, as the conductive film, a metal film, a metal alloy film, a metal nitride film, a metal carbide film, a metal boride film, a metal silicide film, or the like is employed.

In addition, another aspect of the present invention is a method for manufacturing the above-described thin film transistor.

Further, another aspect of the present invention is a display device including a pixel electrode connected to the above-described thin film transistor.

Further, another aspect of the present invention is manufacturing a display device using the above-described thin film transistor for a pixel portion, and furthermore, for a drive circuit. The thin film transistor of the present invention has higher field effect mobility and a higher ON current compared to a transistor using an amorphous semiconductor film because a semiconductor film to which a donor having low resistivity is added is formed in contact with a gate insulating film in the thin film transistor of the present invention, whereby part of or entire drive circuit can be formed over the same substrate as the pixel portion and a system-on-panel can be formed.

The display device includes a light-emitting device and a liquid crystal display device in its category. The light-emitting device and the liquid crystal display device include a light-emitting element and a liquid crystal element, respectively. The light-emitting element includes, in its category, an element whose luminance is controlled by a current or a voltage, and specifically includes an organic EL (electroluminescence) and an inorganic EL.

In addition, the display device includes, in its category, a panel in which a display element is sealed, and a module in which an IC and the like including a controller are mounted on the panel. Further another aspect of the present invention relates one mode of an element substrate before the display element is completed in the manufacturing process of the display device, and the element substrate is provided with a means for supplying a current or a voltage to the display element in each of a plurality of pixels. Specifically, the element substrate may be in a state provided with only a pixel electrode of the display element, a state after a conductive film to be a pixel electrode is formed and before the conductive film is etched to form the pixel electrode, or any other state.

Note that the display device in this specification refers to an image display device, a light-emitting device, or a light source (including a lighting device). Further, the display device includes any of the following modules in its category: a module including a connector such as an flexible printed circuit (FPC), tape automated bonding (TAB) tape, or a tape carrier package (TCP); a module having TAB tape or a TCP which is provided with a printed wiring board at the end thereof; and a module having an integrated circuit (IC) which is directly mounted on a display portion by a chip on glass (COG) method.

According to the present invention, a semiconductor film with low resistivity containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or a conductive film with low resistivity is formed on a surface of an insulating film, an amorphous semiconductor film or an insulating film is formed, which covers a side surface of the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film, and a pair of wirings are formed over the amorphous semiconductor film or the insulating film, whereby increase of ON current and field effect mobility and improvement of electrical characteristics of the thin film transistor can be realized as well as reduction of off current of the thin film transistor. In addition, by manufacturing a display device including the thin film transistor, the image quality of the display device can be improved.

DETAILED DESCRIPTION OF THE INVENTION

Embodiment modes of the present invention will be explained with reference to the drawings. Note that the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details thereof can be modified in various ways without departing from the purpose and the scope of the invention. Thus, the present invention is not interpreted while limiting to the following description of the embodiment modes. In the following structure, the reference numeral indicating the same part will be used in common throughout the drawings.

In this embodiment mode, a structure of a thin film transistor will be described, which has higher field effect mobility, a higher ON current, and a lower off current compared with a conventional thin film transistor including a microcrystalline semiconductor film in a channel formation region, with reference toFIGS. 1A and 1B,FIG. 2,FIG. 3,FIG. 4,FIG. 5,FIG. 6,FIG. 7,FIGS. 8A to 8C,FIGS. 9A to 9F, andFIGS. 35A and 35B.

FIG. 1Aillustrates a thin film transistor in which a gate electrode51is formed over a substrate50, gate insulating films52aand52bare formed over the gate electrode51, a semiconductor film58containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or a conductive film58is formed over the gate insulating films52aand52b, a buffer layer42is formed over the semiconductor film58containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film58, a pair of source and drain regions72to which an impurity element functioning as a donor is added is formed over the buffer layer42, and wirings71ato71care formed over the pair of source and drain regions72to which an impurity element functioning as a donor is added.

Described below is an example of the semiconductor film58containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film58. As the semiconductor film58containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. %, an amorphous germanium film, an amorphous silicon germanium film, a microcrystalline germanium film, a microcrystalline silicon germanium film, a polycrystalline germanium film, a polycrystalline silicon germanium film, or the like is employed.

The microcrystalline germanium film or the microcrystalline silicon germanium film here is a film including a semiconductor having an intermediate structure between amorphous and crystalline structures (including single crystal and polycrystal). Such a film is a semiconductor which has a third state that is stable in terms of free energy, and is a crystalline semiconductor which has short-range order and lattice distortion, and column-like or needle-like crystals with a grain size, seen from the film surface, of 0.5 nm to 20 nm grown in the direction of a normal line with respect to the surface of the substrate. An amorphous semiconductor is present between a plurality of microcrystalline germanium or between a plurality of microcrystalline silicon germanium.

Further, as the conductive film, a metal film, a metal alloy film, a metal nitride film, a metal carbide film, a metal boride film, a metal silicide film, or the like is employed.

As the metal film, a film formed of aluminum, copper, titanium, neodymium, scandium, molybdenum, tantalum, tungsten, cobalt, nickel, silver, gold, platinum, tin, or iridium, or a metal alloy film formed of two or more of these elements can be used as appropriate. In addition, the metal film can be formed of a single layer or a stacked layer of the above-described metal films or metal alloy films.

As the metal nitride film, a titanium nitride film, a zirconium nitride film, a hafnium nitride film, a tantalum nitride film, a vanadium nitride film, a niobium nitride film, a chromium nitride film, a lanthanum nitride film, an yttrium nitride film, or the like can be used. In addition, the metal nitride film can be formed of a single layer or a stacked layer of the above-described metal nitride films

As the metal carbide film, a titanium carbide film, a hafnium carbide film, a niobium carbide film, a tantalum carbide film, a vanadium carbide film, a zirconium carbide film, a chromium carbide film, a cobalt carbide film, molybdenum carbide film, a tungsten carbide film or the like can be used. In addition, the metal carbide film can be formed of a single layer or a stacked layer of the above-described metal carbide films.

As the metal boride film, a titanium boride film can be used.

As the metal silicide film, a platinum silicide film, a titanium silicide film, a molybdenum silicide film, a nickel silicide film, a chromium silicide film, a cobalt silicide film, a vanadium silicide film, a tungsten silicide film, a zirconium silicide film, a hafnium silicide film, a niobium silicide film, a tantalum silicide film, or the like can be used. In addition, the metal silicide film can be formed of a single layer or a stacked layer of the above-described metal silicide films.

Further, a stacked layer film formed of two or more of the metal film, the metal nitride film, the metal carbide film, the metal boride film, and the metal silicide film can be employed.

By providing the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film over the gate insulting film, resistance at the interface between the gate insulating film52band the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film can be reduced, whereby a thin film transistor with high field effect mobility and a high ON current can be manufactured.

The semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film is preferably formed to have a thickness greater than or equal to 5 nm and less than or equal to 50 nm, preferably, greater than or equal to 5 nm and less than or equal to 20 nm.

A concentration of oxygen and a concentration of nitrogen in the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % are each preferably set to 3×1019atoms/cm3typically, more preferably, less than 3×1018atoms/cm3. A concentration of carbon is preferably set to less than or equal to 3×1018atoms/cm3. By decreasing a concentration of oxygen, nitrogen, or carbon to be mixed into the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. %, when the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % is a microcrystalline semiconductor film, a generation of defects in the microcrystalline semiconductor film can be suppressed. Furthermore, oxygen or nitrogen in a microcrystalline semiconductor film hinders crystallization. Therefore, in the case where the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % is a microcrystalline semiconductor film, by relatively decreasing a concentration of oxygen or nitrogen in the microcrystalline semiconductor film, crystallinity of the microcrystalline semiconductor film can be increased.

Further, the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % in this embodiment mode is an n-type semiconductor. Therefore, by adding an impurity element functioning as an acceptor at the same time as or after film formation, a threshold voltage can be controlled. A typical example of the impurity element functioning as an acceptor is boron, and an impurity gas such as B2H6or BF3is preferably mixed into silicon hydride at from 1 ppm to 1000 ppm, preferably from 1 ppm to 100 ppm. A concentration of boron is preferably set to 1×1014atoms/cm3to 6×1016atoms/cm3.

It is preferable that the buffer layer42cover side and top surfaces of the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film58. Furthermore, the gate insulating film52band the buffer layer42are preferably in contact with each other at the periphery of the semiconductor film58containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film58.

Further, as illustrated inFIG. 1B, a first buffer layer62covering the top surface of the semiconductor film58containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film58and a second buffer layer42acovering the a top surface of the first buffer layer62and the side surface of the semiconductor film58containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film58may be formed instead of the buffer layer42illustrated inFIG. 1A.

As the buffer layer42, the first buffer layer62, and the second buffer layer42a, an amorphous semiconductor film is used. Alternatively, an amorphous semiconductor film containing fluorine or chlorine is used. Each thickness of the buffer layer42and the second buffer layer42ais set to be 50 nm to 200 nm. Examples of the amorphous semiconductor film are an amorphous silicon film, an amorphous silicon film including germanium, and the like.

Since the buffer layer42or the second buffer layer42ais provided between the semiconductor film58containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film58and the wirings71ato71c, the semiconductor film58containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film58and the wirings71ato71care not in contact with each other. In addition, since the buffer layer42and the second buffer layer42aare each formed of an amorphous semiconductor film, each energy gap of the buffer layer42and the second buffer layer42ais larger than that of the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. %, resistivity thereof is higher, and the carrier mobility thereof is lower than that of the semiconductor film58containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film58. Therefore, in the thin film transistor to be formed later, the buffer layer42or the second buffer layer42afunction as a high-resistance region, and can reduce leakage current generated between the source drain regions72and a microcrystalline semiconductor film58. Further, off current can be reduced.

As for the semiconductor film58containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive layer58, when the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % is formed of a microcrystalline semiconductor film, an amorphous semiconductor film, or an amorphous film containing hydrogen, nitrogen, or halogen is formed on the surface of the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % as the buffer layer42or the second buffer layer42a, whereby spontaneous oxidation of a surface of crystal grains contained in the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % can be prevented. In particular, in a region of the microcrystalline semiconductor film where an amorphous semiconductor is in contact with microcrystal grains, a crack is likely to be caused due to local stress. If a crack is exposed to oxygen, the crystal grains are oxidized to form silicon oxide. However, the buffer layer42or the first buffer layer62is formed over the surface of the semiconductor film58containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film58, whereby oxidation of the microcrystal grains can be prevented. Therefore, a defect of capture of carriers can be reduced or a region in which carriers are prevented from moving can be reduced.

As the substrate50, any of the following substrates can be used: non-alkaline glass substrates made of barium borosilicate glass, aluminoborosilicate glass, aluminosilicate glass, and the like by a fusion method or a float method; ceramic substrates; plastic substrates having heat resistance enough to withstand a process temperature of this manufacturing process; and the like. Alternatively, a metal substrate of a stainless steel alloy and the like with the surface provided with an insulating film may be employed. When the substrate50is a mother glass, the substrate may have any of the following sizes: the first generation (320 mm×400 mm), the second generation (400 mm×500 mm), the third generation (550 mm×650 mm), the fourth generation (680 mm×880 mm, or 730 mm×920 mm), the fifth generation (1000 mm×1200 mm, or 1100 mm×1250 mm), the sixth generation (1500 mm×1800 mm), the seventh generation (1900 mm×2200 mm), the eighth generation (2160 mm×2460 mm), the ninth generation (2400 mm×2800 mm, or 2450 mm×3050 mm), the tenth generation (2950 mm×3400 mm), and the like.

The gate electrode51is formed using a metal material. As a metal material, aluminum, chromium, titanium, tantalum, molybdenum, copper, or the like is applied. The gate electrode51is preferably formed using aluminum or a stacked layer structure of aluminum and a barrier metal. As a barrier metal, a refractory metal such as titanium, molybdenum, or chromium is applied. A barrier metal is preferably provided for preventing hillocks and oxidation of aluminum.

The gate electrode51is formed to have a thickness greater than or equal to 50 nm and less than or equal to 300 nm. By setting the thickness of gate electrode51to be greater than or equal to 50 nm and less than or equal to 100 nm, a disconnection of a semiconductor film, an insulating film, or a wiring, which is formed later can be prevented. The gate electrode51is formed to have a thickness greater than or equal to 150 nm and less than or equal to 300 nm, which leads to reduction in resistance of the gate electrode51and increase in area of a display device using the gate electrode.

Since the semiconductor film and the wiring are formed over the gate electrode51, the gate electrode51is preferably processed to have a tapered end portion so that breaking of the semiconductor film and the wiring thereover due to level differences is prevented. Further, although not illustrated, a wiring or a capacitor wiring which is connected to the gate electrode can also be formed at the same time.

The gate insulating films52aand52bcan each be formed using a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film with a thickness of 50 nm to 150 nm. Here, an mode is described in which a silicon nitride film or a silicon nitride oxide film is formed as the gate insulating film52a, and a silicon oxide film or a silicon oxynitride film is formed as the gate insulating film52bto form a stacked-layer structure. Note that instead of a two-layer structure, the gate insulating film can be formed of a single layer of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film.

By forming the gate insulating layer52awith use of a silicon nitride film or a silicon nitride oxide film, adhesion between the substrate50and the gate insulating film52ais increased. When a glass substrate is used for the substrate50, impurities from the substrate50can be prevented from diffusing into the semiconductor film58containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film58, the buffer layer42, and the second buffer layer42a, and furthermore, oxidation of the gate electrode51can be prevented. That is to say, film peeling can be prevented, and electric characteristics of a thin film transistor which is completed later can be improved. Further, the gate insulating films52aand52bwith a thickness of greater than or equal to 50 nm are preferable because the gate insulating films52aand52bwith the above thickness can alleviate reduction in coverage caused by unevenness due to the gate electrode51.

Here, a silicon oxynitride film refers to a film that contains more oxygen than nitrogen and, in the case where measurements are performed using Rutherford backscattering spectrometry (RBS) and hydrogen forward scattering (HFS), includes oxygen, nitrogen, silicon, and hydrogen at concentrations from 55 to 65 at. %, 1 to 20 at. %, 25 to 35 at. %, and 0.1 to 10 at. %, respectively. Further, a silicon nitride oxide film refers to a film contains more nitrogen than oxygen and, in the case where measurements are performed using RBS and HFS, includes oxygen, nitrogen, silicon, and hydrogen at concentrations from 15 to 30 at. %, 20 to 35 at. %, 25 to 35 at. %, and 15 to 25 at. %, respectively. Note that percentages of nitrogen, oxygen, silicon, and hydrogen fall within the ranges given above, where the total number of atoms contained in the silicon oxynitride film or the silicon nitride oxide film is defined as 100 at. %.

When an n-channel thin film transistor is formed, phosphorus may be added as a typical impurity element to the pair of source and drain regions72formed of an impurity semiconductor film to which an impurity element imparting one conductivity type is added, and an impurity gas such as PH3may be added to silicon hydride. When a p-channel thin film transistor is formed, boron may be added as a typical impurity element, and an impurity gas such as B2H6may be added to silicon hydride. By setting a concentration of phosphorus or boron to 1×1019to 1×1021atoms/cm3, the impurity semiconductor film to which an impurity imparting one conductivity type is added can have an ohmic contact with the wirings71ato71c, and functions as the source and drain regions. The pair of source and drain regions72can be formed of a microcrystalline semiconductor film or an amorphous semiconductor film. The pair of source and drain regions72are formed with a thickness greater than or equal to 2 nm and less than or equal to 50 nm. When the pair of source and drain regions72are thinned, throughput can be increased.

The wirings71ato71care preferably formed of a single layer or stacked layer of aluminum; copper; or an aluminum alloy to which an element for preventing migration or hillocks or an element for improving heat resistance property, such as silicon, titanium, neodymium, scandium, or molybdenum, is added. Alternatively the wirings may have a stacked layer structure in which a film on a side in contact with the impurity semiconductor film to which an impurity element imparting one conductivity type is added is formed of titanium, tantalum, molybdenum, tungsten, or a nitride of any of these elements, and an aluminum film or an aluminum alloy film is formed thereover. Further alternatively, top and bottom surfaces of aluminum or an aluminum alloy may be each covered with titanium, tantalum, molybdenum, tungsten, or nitride thereof to form a stacked layer structure. Here, the conductive film having a three-layer structure of the conductive films71ato71cis indicated as the conductive film, and a stacked layer structure in which molybdenum films are used as the wirings71aand71cand an aluminum film is used as the wiring71b, or a stacked layer structure in which titanium films are used as the wirings71aand71cand an aluminum film is used as the wiring71bis employed.

Although the thin film transistor illustrated inFIG. 1Ahas a structure in which a side surface of the buffer layer42is in contact with the wiring71ato71c, the thin film transistor may have a structure as illustrated inFIG. 2, in which a buffer layer87is not in contact with the wirings71ato71cand the wirings71ato71c are formed over the buffer layer87with a pair of source and drain regions88interposed therebetween. Such a transistor can be formed with a photolithography process using a multi-tone mask. The details thereof will be described in Embodiment Mode 4.

By employing the structure illustrated inFIG. 2, the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film58is not in contact with the pair of source or drain regions88formed of an impurity semiconductor film to which an impurity element imparting one conductivity type is added and the wirings71ato71c, whereby leakage current and off current of the thin film transistor can be reduced.

A thin film transistor having a structure different from that inFIGS. 1A and 1BandFIG. 2will be described with reference toFIG. 3.

In a thin film transistor illustrated inFIG. 3, the gate electrode51is formed over the substrate50, the gate insulating films52aand52bare formed over the gate electrode51, the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film58is formed over the gate insulating films52aand52b, the buffer layer42is formed over the semiconductor film58containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film58, and the pair of source and drain regions72to which an impurity element functioning as a donor is added are formed over the buffer layer42. Side surfaces of the semiconductor film58containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film58, the buffer layer42, and the pair of source and drain regions72are covered with an insulating film67aand pairs of the wirings71ato71care formed over the pair of source and drain regions72and the insulating film67a.

As the insulating film67a, a film similar to the gate insulating films52aand52bcan be used. Alternatively, an organic resin can be used. Since the insulating film67acovers at least the side surface of the semiconductor film58containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film58, the semiconductor film58containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film58and the wirings71ato71care not in contact with each other, whereby leakage current and off current can be reduced. The buffer layer42is formed between the semiconductor film58containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film58and the source and drain regions72. The energy gap of the buffer layer42is larger than that of the semiconductor film58containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film58, and resistivity thereof is high, and mobility thereof is as low as one-fifth to one-tenth of that of the semiconductor film58containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film58. For this reason, in the transistor to be formed later, the buffer layer42functions as a high-resistance region, whereby leakage current generated between the source and drain regions72and the semiconductor film58containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film58can be reduced. Further, off current can be reduced.

Further, although the thin film transistor illustrated inFIG. 3has a structure in which the pair of source and drain regions72are formed over the buffer layer42and the insulating film67acovers part of the pair of source and drain regions72and the side surface of the pair of source and drain regions72, structures illustrated inFIG. 4andFIGS. 35A and 35Bcan be employed. The insulating film67acovers the side surfaces of the semiconductor film58containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film58and the buffer layer42and one contact hole68ais formed over the buffer layer42to surround an insulating film67b(seeFIG. 35A). In this case, the insulating67aand the insulating film67bare separated. Alternatively, a pair of contact holes68band68cmay be formed (seeFIG. 35B). In this case, the insulating film67aand the insulating film67bare connected. Further a pair of source and drain regions70are formed over the insulating film67aand connected to the buffer layer42via the contact holes68band68c. In addition, the pairs of wirings71ato71care formed over the pair of source and drain regions70.

As illustrated inFIG. 4, by forming a contact hole around the insulating film67b, the insulating film67bsurrounded by the contact hole functions as a channel protection film; therefore, the buffer layer is not overetched during separation of the source and drain regions70and damage to the buffer layer due to etching can be reduced. Further, in the case where a pair of contact holes are formed, the insulating film67aand the insulating film67bare connected to each other, and a region in the insulating film67bfunctions as a channel protection film; therefore, the buffer layer is not overetched during separation of the source and drain regions70and damage to the buffer layer due to etching can be reduced. A manufacturing method of such thin film transistors will be described in Embodiment Mode 6.

By employing the structure illustrated inFIG. 4, the semiconductor film58containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film58is not in contact directly with the pair of source and drain regions70and the wirings71ato71c, whereby leakage current and off current of the thin film transistor can be reduced.

Note that while a mode in which end portions of the wirings71ato71cand end portions of the pair of source and drain regions70are not aligned is described here, a structure may alternatively be employed in which the end portions of the wirings71ato71cand the end portions of the pair of source and drain regions72are aligned as illustrated inFIG. 5.

Next, a thin film transistor in which a gate insulating film has a different structure from the gate insulating film of the above thin film transistors is described with reference toFIG. 6.

Instead of the gate insulating films52aand52bof the thin film transistors illustrated inFIGS. 1A and 1B,FIG. 2,FIG. 3,FIG. 4, andFIG. 5, three gate insulating films52a,52b, and52cmay be formed as illustrated inFIG. 6. As the gate insulating film52c, which is a third layer, a silicon nitride film or a silicon nitride oxide film with a thickness of about 1 nm to 5 nm can be formed.

As a method for forming a silicon nitride film or a silicon nitride oxide film with a thickness of about 1 nm to 5 nm as the third gate insulating layer, a plasma CVD method can be employed. Further, it is also possible to have the gate insulating film52bundergo nitridation treatment with high-density plasma to form a silicon nitride film on the surface of the gate insulating film52b. By nitridation treatment using high-density plasma, a silicon nitride film that contains nitrogen at a higher concentration can be obtained. High-density plasma is produced by using a microwave with a high frequency, for example, 1 GHz or 2.45 GHz. With high-density plasma, which has the characteristic of having a low electron temperature, a layer can be formed with less plasma damage and few defects compared to a layer formed by a conventional plasma treatment because the kinetic energy of active species is low. In addition, carrier mobility can be increased because surface roughness of the gate insulating film52ccan be reduced.

Further, instead of the semiconductor film58containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film58in the thin film transistor illustrated inFIGS. 1A and 1B,FIG. 2,FIG. 3,FIG. 4,FIG. 5, andFIG. 6, conductive particles60are dispersed over the gate insulating film52band a semiconductor film61containing germanium as its main component can be formed over the conductive particles60and the gate insulating film52b.

Next, the operation mechanism of the thin film transistor in which the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film and the buffer layer are stacked over the gate insulating film as illustrated inFIGS. 1A and 1B,FIG. 2,FIG. 3,FIG. 4,FIG. 5,FIG. 6, andFIG. 7is described below. In the following description, as a typical example of the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film, a microcrystalline germanium film is used, and an amorphous silicon film is used for the buffer layer.

FIGS. 8A to 8Care energy band diagrams of the thin film transistor of the present invention,FIGS. 9A,9C, and9E are cross-sectional views of the thin film transistor, andFIGS. 9B,9D, and9F are equivalent circuit diagrams.

FIG. 9Aillustrates a thin film transistor in which a substrate20, a gate electrode21, a gate insulating film22, a microcrystalline germanium film23as an example of a semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or a conductive film, an amorphous silicon film24as a buffer layer, a source region25S, a drain region25D, a source electrode26S, and drain electrode26D are stacked.

FIG. 9Billustrates an equivalent circuit of the thin film transistor inFIG. 9A. Here, resistance RSamainly represents a resistance value of the source region25S and the amorphous silicon film24; resistance RDamainly represents a resistance value of the drain region25D and the amorphous silicon film24; resistance Racmainly represents a resistance value of the amorphous silicon film24; and resistance Rμcmainly represents a resistance value of the microcrystalline germanium film23.

FIG. 8Ais a band diagram of the thin film transistor inFIG. 9Ain a state in which voltage is not applied to the gate electrode21and shows a case where a Fermi level Ef of the amorphous silicon film24and a Fermi level Efm of the gate electrode are equal to each other.

The microcrystalline germanium film23of this embodiment mode is an n-type semiconductor, and the Fermi energy Ef is close to a conduction band energy Ec in the microcrystalline germanium film23. In addition, the microcrystalline germanium film23is an n-type film, and the amorphous silicon film24is an i-type film. Further, when the band gap (an energy difference between the bottom Ec of the conduction band and the top Ev of the valence band) of the microcrystalline germanium film23is 1.0 eV, for example, and the band gap of the amorphous silicon film is 1.7 eV, for example, an n-i junction is formed at the interface between the microcrystalline germanium film23and the amorphous silicon film24. Thus, the energy band near the interface between the microcrystalline germanium film23and the amorphous silicon film24curves, and the bottom Ec of the conduction band of the microcrystalline germanium film23is below the bottom Ec of the conduction band of the amorphous silicon film24.

Then, the gate electrode21is supplied with positive voltage, the source electrode26S is grounded to have ground potential, and the drain electrode26D, is supplied with positive voltage. The path through which current flows between the drain electrode26D and the source electrode26S at this time is illustrated inFIG. 9C. As denoted by a dotted line inFIG. 9C, drain current flows through the drain electrode26D, the drain region25D, the amorphous silicon film24, a part close to the interface with the gate insulating film22of the microcrystalline germanium film23, the amorphous silicon film24, the source region25S, and the source electrode26S. In other words, a carrier path between the drain electrode26D and the source electrode26S is formed through the source electrode26S, the source region25S, the amorphous silicon film24, a part close to the interface with the gate insulating film22of the microcrystalline germanium film23, the amorphous silicon film24, the drain region25D, and the drain electrode26D.

FIG. 9Dillustrates an equivalent circuit of the thin film transistor illustrated inFIG. 9C. Here, forward bias is applied at the interface between the source region25S and the amorphous silicon film24, so that the resistance RSarepresents a resistance value of the source region25S and the amorphous silicon film24connected in forward direction, and the resistance RSais low. In addition, at the interface between the drain region25D and the amorphous silicon film24, reverse bias is applied and a depletion layer is formed, so that the resistance RDais high. The resistance Rμcrepresents a resistance value of the microcrystalline germanium film23, which is inverted. Here, the inverted microcrystalline germanium film23refers to a microcrystalline germanium film in which conduction electrons are induced to the interface with the gate insulating film by applying potential to the gate electrode. The resistance RSais considered much lower than the resistance RDaand the resistance Rμc.

FIG. 8Bis a band diagram of the thin film transistor illustrated inFIG. 9Cin a state in which positive voltage, typically, positive voltage which is high enough to form an inversion layer, is applied to the gate electrode21. By application of positive voltage to the gate electrode21, an energy band in the microcrystalline germanium film23curves, and a region where the bottom Ee of the conduction band is lower than the Fermi level Ef, that is, an inversion layer is formed, and electrons are induced to a region of the microcrystalline germanium film23which is close to the interface with the gate insulating film22so as to enhance the density of conduction electrons. A positive voltage at which the inversion layer begins to be formed substantially equals to the threshold voltage Vth.

In an actual device structure, the resistance RDais typically formed by the amorphous silicon film with a thickness of about 0.1 μm to 0.3 μm. On the other hand, the resistance Rμcis typically formed by the microcrystalline germanium film with a length of about 3 μm to 6 μm. Therefore, the traveling distance of carriers in the channel is 10 to 30 times as long as that in the amorphous silicon film. By making the resistance Rμcof the microcrystalline germanium film much smaller than the resistance Racof the amorphous silicon film, ON current and field effect mobility of the thin film transistor can be increased. Therefore, by forming the microcrystalline germanium film over the gate insulating film, electric conductivity of the film formed over the gate insulating film can be improved.

On the other hand, the gate electrode21is supplied with negative voltage, the source electrode26S is grounded to have ground potential, and the drain electrode26D is supplied with positive voltage. A drain-current and carrier path at this time is illustrated inFIG. 9E. The path through which drain current flows between the drain electrode26D and the source electrode26S at this time is illustrated. As denoted by a dotted line inFIG. 9E, drain current flows through the drain electrode26D, the drain region25D, the vicinity of the surface of the amorphous silicon film24, the source region25S, and the source electrode26S. In other words, a carrier path between the drain electrode26D and the source electrode26S is formed through the source electrode26S, the source region25S, the vicinity of the surface of the amorphous silicon film24, the drain region25D, and the drain electrode26D.

FIG. 9Fillustrates an equivalent circuit of the thin film transistor illustrated inFIG. 9E. Here, forward bias is applied at the interface between the source region25S and the amorphous silicon film24, so that the resistance RSarepresents a resistance value of the source region25S and the amorphous silicon film24connected in forward direction, and the resistance RSais low. In addition, at the interface between the drain region25D and the amorphous silicon film24, reverse bias is applied and a depletion layer is formed, so that the resistance RDais high. The resistance Racrepresents a resistance value of the amorphous silicon film. It is considered that the resistance RSais much lower than the resistance RDaand the resistance Rac.

FIG. 8Cis a band diagram of the thin film transistor illustrated inFIG. 9Ein a state in which negative voltage is applied to the gate electrode21. By applying negative voltage to the gate electrode21, electrons are forced away from the interface between the gate insulating film22and the microcrystalline germanium film23. As a result, the electron density is depleted, and a depletion layer is formed. In this condition, conduction electrons are removed from the conduction band, and at the interface between the microcrystalline germanium film23and the gate insulating film22, the bottom Ec of the conduction band of the microcrystalline germanium film23is higher than the Fermi level Ef. In addition, the surface of the microcrystalline germanium film23has higher resistance than the amorphous silicon film24. Accordingly, when negative voltage is applied to the gate electrode21, electrons pass through the amorphous silicon film24, so that current flows. In the vicinity of the interface between the amorphous silicon film24and the drain region, reverse bias is applied, and a depletion layer is formed, so that the resistance RDais increased. However, when the amorphous silicon film24has defects, impurity elements, or recombination centers, the defects, the impurity elements, or the recombination centers function as a leakage path, whereby a depletion layer does not spread and off current flows. Therefore, the amorphous silicon film24is formed of a film which forms perfect bonding at the interface with the drain region and has less impurity elements, less defects, and less recombination centers. That is, by forming the amorphous silicon film24whose photoelectric current is high and whose dark current is low, leakage current of the thin film transistor can be reduced.

Note that the microcrystalline germanium film is used for the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film. Alternatively, when a conductive film is used, the energy band curves at the interface between the conductive film and the buffer layer so as to be aligned with the Fermi level. Therefore, thin film transistor characteristics which are similar to characteristics of the above-described thin film transistors can be obtained.

As described in this embodiment mode, when positive voltage is applied to the gate electrode, the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % is used as a travel region for carriers; while when negative voltage is applied to the gate electrode, the amorphous semiconductor film with low conductivity is used as a travel region for carriers. Thus, a thin film transistor with a high ON/OFF ratio can be obtained. That is, a thin film transistor which has high ON current and high field effect mobility and which can suppress off current can be manufactured.

By providing a film with low resistivity over a gate insulating film, a semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or a conductive film here, ON current and field effect mobility of the thin film transistor can be improved. Further, by providing an amorphous semiconductor film or an insulating film to cover side surfaces of the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film, off current of the thin film transistor can be reduced. That is, a higher-performance thin film transistor can be formed. Accordingly, a driving frequency of a display device can be increased, whereby a panel size can be increased and high density of pixels can be well achieved. In addition, since the thin film transistor of this embodiment mode is an inverted staggered thin film transistor, thin film transistors can be manufactured over a large substrate with fewer steps.

In this embodiment mode, another structure of the thin film transistor illustrated in Embodiment Mode 1 is described with reference toFIG. 1AandFIGS. 34A and 34B. AlthoughFIG. 1Ais referred to here, this embodiment mode can be applied to as appropriate to the thin film transistors illustrated in other drawings in Embodiment Mode 1.

InFIG. 1A, the end portion of the pair of source and drain regions72functioning as source and drain regions overlaps with the end portion of the semiconductor film58containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film58.

Further, in addition to the structure, as for the thin film transistor illustrated inFIG. 34A, when the end portion of the pair of source and drain regions72functioning as source and drain regions and the end portion of the semiconductor film58containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film58substantially align. In a thin film transistor in which the pair of source and drain regions72functioning as source and drain regions and the semiconductor film58containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film58overlap as illustrated inFIG. 1A, or end portions thereof are substantially aligned as indicated by a dotted line inFIG. 34A, a traveling distance of carriers is shortened and thus ON current can be improved.

Alternatively, a so-called off-set structure illustrated inFIG. 34Bin which the end portion of the pair of source and drain regions72functioning as source and drain regions does not overlap with the end portion of the semiconductor film58containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film58can be employed. With such a structure, the pair of source and drain regions functioning as source and drain regions and the semiconductor film58containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film58are spaced; accordingly, an electric field in the buffer layer42is relieved and off current can be reduced.

In this embodiment mode, a process for manufacturing a thin film transistor having high field effect mobility, high ON current, and low off current is described. Here, as a typical example, a method for manufacturing the thin film transistor ofFIG. 1Bin Embodiment Mode 1 is described.

An n-channel thin film transistor having an amorphous semiconductor film or a microcrystalline semiconductor film has higher field effect mobility than a p-channel thin film transistor having an amorphous semiconductor film or a microcrystalline semiconductor film and thus the n-channel thin film transistor is more suitable for being used in a driver circuit. It is preferable that all thin film transistors formed over one substrate have the same polarity in order to reduce the number of manufacturing steps. Further, when a semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % is used for a semiconductor film45containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or a conductive film45, an n-channel transistor is employed.

As illustrated inFIG. 10A, the gate electrode51is formed over the substrate50and the gate insulating films52aand52bare formed over the gate electrode51.

The gate electrode51is formed by a sputtering method, a CVD method, a plating method, a printing method, a droplet discharge method, or the like using any of the metal materials which are given as materials for the gate electrode51in Embodiment Mode 1. Here, a molybdenum film is formed as a conductive film over the substrate50by a sputtering method and is etched using a resist mask which is formed using a first photomask. Thus, the gate electrode51is formed.

The gate insulating films52aand52bcan each be a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film which is formed by a CVD method, a sputtering method, or the like. Here, a mode is described in which a silicon nitride film or a silicon nitride oxide film is formed as the gate insulating film52a, and a silicon oxide film or a silicon oxynitride film is formed as the gate insulating film52bto form a stacked layer structure.

Next, the semiconductor film45containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film45is formed over the gate insulating film52b. As a method for forming the semiconductor film45containing germanium at a concentration greater than or equal to 5 at,% and less than or equal to 100 at. % or the conductive film45, a thermal CVD method, a plasma CVD method, an ECRCVD method, an ion plating method, a sputtering method, a vacuum deposition method, or the like can be employed as appropriate.

The semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % is formed by a thermal CVD method, a plasma CVD method, an ECRCVD method, an ion plating method, a sputtering method, a vacuum deposition method, or the like. Further the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % formed by a thermal CVD method, a plasma CVD method, an ECRCVD method, an ion plating method, a sputtering method, a vacuum deposition method, or the like may be subjected to heat treatment to be crystallized. As heat treatment, heat may be added or laser beam irradiation or lamp light irradiation may be performed.

In the case of forming the semiconductor film45containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film45by a plasma CVD method or an ECRCVD method, in a reaction chamber of a film formation apparatus, a deposition gas containing silicon or germanium and hydrogen are mixed, and an amorphous semiconductor film or a microcrystalline semiconductor film is formed using glow discharge plasma. Note that in the case of forming an amorphous semiconductor film, an amorphous semiconductor film can be formed by glow discharge plasma using a deposition gas containing silicon or germanium without using hydrogen.

In the step of forming the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. %, glow discharge plasma is generated by applying high-frequency power with a frequency of 1 MHz to 20 MHz, typically 13.56 MHz, or high-frequency power with a frequency of more than 20 MHz to about 120 MHz, typically 27.12 MHz or 60 MHz. Alternatively, glow discharge plasma is generated by applying micro wave with a high-frequency power frequency of 1 GHz or 2.54 GHz.

As typical examples of the deposition gas containing silicon or germanium, SiH4, Si2H6, GeH4, and Ge2H6are given.

In the film formation treatment of the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film, helium may be added to a reaction gas, in addition to a deposition gas containing silicon or germanium and hydrogen. Helium has an ionization energy of 24.5 eV, which is the largest among all gases, and has a metastable state in the level of about 20 eV, which is a little lower than the ionization energy; therefore, only about 4 eV, the difference therebetween, is necessary for ionization during discharging. Therefore, the discharge starting voltage also has the lowest value among all gases. By such characteristics, plasma can be held stably with helium. Further, since uniform plasma can be formed, even if the area of a substrate over which the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film is deposited is large, plasma having uniform density can be obtained.

Further, an amorphous semiconductor film or a microcrystalline semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % can be formed by sputtering with helium, argon, neon, or the like using a germanium target, a silicon germanium target, or the like.

In addition, by adding heat to an amorphous semiconductor film or a microcrystalline film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. %, a crystalline semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % can be formed.

Similarly, the conductive film can be formed by a thermal CVD method, a plasma CVD method, an ECRCVD method, an ion plating method, a sputtering method, a vacuum deposition method, or the like.

Here, as the semiconductor film45containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film45, a microcrystalline germanium film is formed by glow discharge plasma mixing germane with hydrogen and/or a rare gas. Germane is diluted with hydrogen and/or a rare gas to be 10 times to 2000 times thinner. Thus, a large amount of hydrogen and/or a rare gas is needed. The substrate heating temperature is 100° C. to 400° C., preferably 250° C. to 350° C. Further, by using a deposition gas containing silicon together with hydrogen and a deposition gas containing germanium, a microcrystalline silicon germanium film is formed as the semiconductor film45containing germanium as its main component.

Next, a first buffer layer54is formed. As the first buffer layer54, an amorphous semiconductor film can be formed by a plasma CVD method using a deposition gas containing silicon or germanium. Alternatively, by dilution of a deposition gas containing silicon or germanium with one or plural kinds of rare gases selected from helium, argon, krypton, and neon, an amorphous semiconductor film can be formed. Furthermore, an amorphous semiconductor film containing hydrogen can be formed using hydrogen with a flow rate of 1 to 10 times, preferably 1 to 5 times as high as that of a deposition gas containing silicon or germanium. In addition, halogen such as fluorine or chlorine may be added to the above-described hydrogenated semiconductor film or the amorphous semiconductor film containing hydrogen.

Alternatively, as the first buffer layer54, an amorphous semiconductor film can be formed by sputtering with hydrogen or a rare gas using a semiconductor target such as a silicon target, a silicon germanium target, a germanium target.

As the amorphous semiconductor film, an amorphous silicon film, an amorphous silicon germanium film, or the like is given.

The thickness of the first buffer layer54is set to be 10 nm to 100 nm, preferably, 30 nm to 50 nm.

An amorphous semiconductor film or an amorphous film containing hydrogen, nitrogen, or halogen is formed, as a buffer layer54, on the surface of the semiconductor film45containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film45, whereby native oxidation of a surface of crystal grains contained in the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % can be prevented when the semiconductor film45containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film45is formed of a microcrystalline semiconductor film. In particular, in a region where an amorphous semiconductor is in contact with microcrystal grains, a crack is likely to be caused due to distortion of local stress. If a crack is exposed to oxygen, crystal grains are oxidized to form silicon oxide. However, the first buffer layer54is formed on the surface of the semiconductor film45containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film45, whereby oxidation of the microcrystal grains can be prevented.

In addition, it is preferable that the first buffer layer54be formed by a plasma CVD method at a temperature of 300° C. to 400° C. after forming the semiconductor film45containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film45. This film formation treatment supplies hydrogen to the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. %, and the same effect as hydrogenating the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % can be obtained. In other words, by depositing the first buffer layer54over the semiconductor film45containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film45, hydrogen is diffused into the semiconductor film45containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film45, whereby dangling bonds can be terminated.

Then, a resist is applied over the first buffer layer54, then, the resist is exposed to light and developed through a photolithography process using a second photomask to form a resist mask. Then, using the resist mask, the first buffer layer54and the semiconductor film45containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film45are etched to form the first buffer layer62and the semiconductor film58containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film58.

Then, as illustrated inFIG. 10C, a second buffer layer41and an impurity semiconductor film55to which an impurity element imparting one conductivity type is added are formed over the first buffer layer62and the gate insulating film52b.

The second buffer layer41is formed in a manner similar to that of the first buffer layer54. In some cases, the second buffer layer42is partly etched in a later step of formation of source and drain regions, and therefore is preferably formed with a thickness such that the second buffer layer42is partly left after the etching. Typically, it is preferable to form the second buffer layer41with a thickness greater than or equal to 30 nm and less than or equal to 500 nm, preferably greater than or equal to 50 nm and less than or equal to 200 nm.

In a display device in which high voltage (e.g., about 15 V) is applied to thin film transistors, typically, in a liquid crystal display device, if the first buffer layer54and the second buffer layer41are formed thick, withstand drain voltage is increased. Therefore, deterioration of the thin film transistors can be reduced even if high voltage is applied to the thin film transistors.

Since the first buffer layer54and the second buffer layer41are each formed using an amorphous semiconductor film or an amorphous semiconductor film containing hydrogen or a halogen, the first buffer layer54and the second buffer layer41have a larger energy gap, higher resistivity and lower mobility than the semiconductor film45containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film45. Therefore, in a thin film transistor which is completed later, the first buffer layer and the second buffer layer, which are formed between the source and drain regions and the semiconductor film45containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film45, serve as high resistance regions; therefore off current of the thin film transistor can be reduced. When the thin film transistor is used as a switching element of a display device, the contrast of the display device can be improved.

In the case of forming an n-channel thin film transistor, phosphorus may be added as a typical impurity element to form the semiconductor film55to which an impurity element imparting one conductivity type is added; for example, an impurity gas such as PH3may be added to a deposition gas containing silicon or germanium. If a p-channel thin film transistor is formed, boron, which is a typical impurity element, may be added; for example, a gas containing an impurity element such as B2H6may be added to a deposition gas containing silicon or germanium as source gas. By setting a concentration of phosphorus or boron to 1×1019to 1×1021at./cm3, the impurity semiconductor film55can have an ohmic contact with wirings71ato71cwhich is formed later, and functions as the source and drain regions. The impurity semiconductor film55to which an impurity element imparting one conductivity type is added can be formed of a microcrystalline semiconductor film or an amorphous semiconductor film. The impurity semiconductor film55to which an impurity element imparting one conductivity type is added is formed with a thickness greater than or equal to 2 nm and less than or equal to 50 nm. By reducing the thickness of the impurity semiconductor film to which an impurity element imparting one conductivity type is added, the throughput can be improved.

Then, a resist mask is formed over the impurity semiconductor film55to which an impurity element imparting one conductivity type is added. The resist mask is formed by a photolithography technique. Here, a resist which is applied over the impurity semiconductor film55to which an impurity element imparting one conductivity type is added is exposed to light using a third photomask and developed to form the resist mask.

Then, using the resist mask, the second buffer layer41and the impurity semiconductor film55to which an impurity element imparting one conductivity type is added are etched and separated to form the second buffer layer42and an impurity semiconductor film63to which an impurity imparting one conductivity type is added as illustrated inFIG. 11A. Then, the resist mask is removed.

The second buffer layer42covers the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film58, whereby leakage current between the source and drain regions formed over the second buffer layer42and the semiconductor film58containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film58can be prevented. In addition, leakage current between the wiring and the semiconductor film58containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film58can be prevented.

Then, as illustrated inFIG. 11B, conductive films65ato65care formed over the impurity semiconductor film63to which an impurity element imparting one conductivity type is added and the gate insulating film52b. The conductive films65ato65are formed by a sputtering method, a CVD method, a printing method, a droplet discharge method, a vapor deposition method, or the like. Here, the conductive film having a three-layer structure of the conductive films65ato65cis illustrated, and a stacked layer structure in which molybdenum films are used as the conductive films65aand65cand an aluminum film is used as the conductive film65b, or a stacked layer structure in which titanium films are used as the conductive films65aand65cand an aluminum film is used as the conductive films65bis employed. The conductive films65ato65care formed by a sputtering method or a vacuum evaporation method.

The conductive films65ato65ccan be formed using any of the metal materials which are listed as materials for the wirings71ato71cin Embodiment Mode 1.

Then, a resist mask is formed over the conductive film65cthrough a photolithography process using a fourth photomask.

Then, the conductive films65ato65care etched using the resist mask to form pairs of the wirings71ato71c(which serve as source and drain electrode) as illustrated inFIG. 11C.

Then, the impurity semiconductor film63to which an impurity element imparting one conductivity type is added is etched and separated using the resist mask. As a result, the pair of source and drain regions72can be formed as illustrated inFIG. 11C. Note that in this etching process, the second buffer layer42is also partly etched. The second buffer layer42which is partly etched and has a depressed portion is referred to as a second buffer layer43. The source and drain regions and the depressed portion of the buffer layer can be formed in the same process. The depth of the depressed portion of the second buffer layer43is set to half to one-third of the thicknesses of the thickest region in the second buffer layer43, whereby the leak path between the source region and the drain region can be spaced long. Accordingly, leakage current between the source region and drain region can be reduced. Then, the resist mask is removed.

Next, dry etching may be performed under such a condition that the second buffer layer43which is exposed is not damaged and an etching rate of the second buffer layer43is low. Through this step, an etching residue on the second buffer layer43between the source and drain regions, a residue of the resist mask, and a contamination source in the apparatus used for removal of the resist mask can be removed, whereby the source and drain regions can be certainly insulated. As a result, leakage current of the thin film transistor can be reduced; therefore, a thin film transistor with small off current and high withstand voltage can be manufactured. Note that a chlorine gas may be used for an etching gas, for example.

Through the above-described process, a channel-etched thin film transistor74can be formed.

Next, as illustrated inFIG. 12A, a protective insulating film76is formed over the wirings71ato71c, the source and drain regions72, the second buffer layer43, and the gate insulating film52b. The protective insulating film76can be formed in a manner to that of the gate insulating films52aand52b. Note that the protective insulating film76is provided to prevent intrusion of contaminating impurities such as organic matters, metal, or water vapor contained in the atmosphere; thus, a dense film is preferably used for the protective insulating film76. Further, by using a silicon nitride film as the protective insulating film76, the oxygen concentration in the second buffer layer43can be 5×1019at./cm3or less, preferably 1×1019at./cm3or less, so that the second buffer layer43can be prevented from being oxidized.

Then, an insulating film101is formed over the protective insulating film76. The insulating film101is formed using a photosensitive organic resin here. Then, the insulating film101is exposed to light using a fifth photomask and developed to form an insulating film102with an opening being exposed the protective insulating film76as illustrated inFIG. 12B. Then, the protective insulating film76is etched using the insulating film102to form a contact hole111which partly exposes the wiring71c.

Then, as illustrated inFIG. 12C, a pixel electrode77is formed in the contact hole111. Here, after a conductive film is formed over the insulating film102, the conductive film is etched using a resist mask which is formed through a photolithography process using a sixth photomask, whereby the pixel electrode77is formed.

Alternatively, the pixel electrode77can be formed using a conductive composition containing a conductive high-molecular compound (also referred to as a conductive polymer). The pixel electrode77which is formed of a conductive composition preferably has a sheet resistance of 10000 Ω/square or less and a transmittance for light at a wavelength of 550 nm of 70% or more. In addition, the resistivity of the conductive high-molecular compound contained in the conductive composition is preferably 0.1 Ω·cm or less.

As the conductive high-molecular compound, a so-called π-electron conjugated conductive high-molecular compound can be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, a copolymer of two or more kinds thereof, and the like can be given.

Here, as the pixel electrode77, a film of ITO is formed by a sputtering method, and then, a resist is applied to the ITO film. Then, the resist is exposed to light using the sixth photomask and developed. Then, the ITO film is etched using the resist mask to form the pixel electrode77.

Note thatFIG. 12Cis a cross-sectional view taken along line Q-R inFIG. 13. InFIG. 13, it is not illustrated that the end portions of source and drain regions72are exposed and located beyond the end portion of the wiring71c. Furthermore, one of the pair of wirings surrounds the other wiring (specifically, the former wiring is in a U-shape or a C-shape). Thus, an area in which carriers travel can be increased, and thus the amount of current can be increased and an area of the thin film transistor can be reduced. In addition, the semiconductor film58containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film58, the gate insulating films52aand52b, and the wirings71ato71coverlap over the gate electrode51, and thus an influence by unevenness due to the gate electrode51is small and reduction in coverage and generation of leakage current can be suppressed.

Further, in the case of a liquid crystal display device, the wirings71ato71cwhich is connected to a signal line serves as a source and the wirings71ato71cwhich is connected to a pixel electrode serves as a drain, and by making the source have a U-shape or a C-shape (that is, the shape with an upper surface shape having a curve around the drain with the insulating film interposed therebetween) with which a region of the source which faces the drain is larger than a region of the drain which faces the source, parasitic capacitance between the gate electrode (gate wiring) and the drain can be reduced. Therefore, a thin film transistor in which voltage drop in the drain electrode side is reduced can be formed. In addition, the display device with a thin film transistor having such a structure can have improved response speed of pixels. In particular, in the case of thin film transistors formed in pixels in a liquid crystal display device, since drop in drain voltage can be reduced, response speed of a liquid crystal material can be improved.

Through the above-described process, a thin film transistor and an element substrate which can be used for a display device can be formed.

Although this embodiment mode describes a channel-etched thin film transistor, this embodiment mode can be applied to a channel-protective thin film transistor. In specific, it is possible to form a channel protection film over the second buffer layer and to provide the pair of impurity semiconductor films over the channel protection film and the second buffer layer.

According to this embodiment mode, a high-performance thin film transistor can be manufactured. Accordingly, a driving frequency of a display device can be increased and the panel size can be increased and higher density of pixels can be achieved.

In this embodiment mode, a process for manufacturing a thin film transistor having high field effect mobility, high ON current, and low off current is described. In addition, a process for manufacturing a thin film transistor is described through which the number of photomasks can be less than that in Embodiment Mode 3. Here, as a typical example, a method for manufacturing the thin film transistor ofFIG. 2in Embodiment Mode 1 is described.

In a manner similar to that in Embodiment Mode 3, as illustrated inFIG. 14A, a conductive film is formed over the substrate50; a resist is applied to the conductive film; and the conductive film is partly etched using a resist mask which is formed through a photolithography process using a first photomask to form the gate electrode51. Then, the gate insulating films52aand52bare formed over the gate electrode51. Then, the semiconductor film58containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film58and the first buffer layer62are formed over the gate insulating film52bthrough photolithography process using a second photomask. Then, a second buffer layer41, the impurity semiconductor film55to which an impurity imparting one conductivity type is added, and the conductive films65ato65care formed in that order over the first buffer layer62. Then, a resist is applied to the conductive film65c.

As the resist, a positive resist or a negative resist can be used. Here, a positive resist is used.

Then, the resist is irradiated with light using a multi-tone mask as a third photomask, so that the resist is exposed to the light to be a resist mask81.

Light exposure using a multi-tone mask is described here with reference toFIGS. 15A to 15D.

A multi-tone mask can perform three levels of light exposure to obtain an exposed portion, a half-exposed portion, and an unexposed portion; with which one-time light exposure and development process can form a resist mask with regions of plural thicknesses (typically, two kinds of thicknesses) to be formed. Accordingly, by using a multi-tone mask, the number of photomasks can be reduced.

As illustrated inFIG. 15A, the gray-tone mask159aincludes a light-transmitting substrate163provided with a light-blocking portion164and a diffraction grating165. The light transmittance of the light-blocking portion164is 0%. On the other hand, the diffraction grating165has a light transmitting portion in a slit form, a dot form, a mesh form, or the like with intervals of equal to or less than the resolution limit of light used for the exposure, and therefore controls the light transmittance. The diffraction grating165can be in a slit form, a dot form, or a mesh form with regular intervals; or in a slit form, a dot form, or a mesh form with irregular intervals.

For the light-transmitting substrate163, a light-transmitting substrate such as a quartz substrate can be used. The light-blocking portion164and the diffraction grating165can be formed using a light-blocking material such as chromium or chromium oxide, which absorbs light.

When the gray-tone mask159ais irradiated with light, a light transmittance166of the light-blocking portion164is 0% and the light transmittance166of a region where neither the light-blocking portion164nor the diffraction grating165is provided is 100% as illustrated inFIG. 15B. The light transmittance166of the diffraction grating165can be controlled in a range of 10% to 70%. The light transmittance in the diffraction grating165can be controlled by adjusting the interval of slits, dots, or meshes of the diffraction grating and the pitch thereof.

As illustrated inFIG. 15C, the half-tone mask159bincludes the light-transmitting substrate163provided with a semi-light-transmitting portion167and a light-blocking portion168. The semi-light-transmitting portion167can be formed using MoSiN, MoSi, MoSiO, MoSiON, CrSi, or the like. The light-blocking portion168can be formed using a light-blocking material such as chromium or chromium oxide, which absorbs light.

When the half-tone mask159bis irradiated with light, a light transmittance169of the light-blocking portion168is 0% and the light transmittance169of the region where neither the light-blocking portion168nor the semi-light-transmitting portion167is provided is 100% as illustrated inFIG. 15D. The light transmittance169of the semi-light-transmitting portion167can be controlled in a range of 10% to 70%. The light transmittance in the semi-light-transmitting portion167can be controlled by a material of the semi-light-transmitting portion167.

After light exposure using the multi-tone mask, development is carried out, whereby the resist mask81including regions having different thicknesses can be formed, as illustrated inFIG. 14A.

Next, with the resist mask81, the second buffer layer41, the impurity semiconductor film55to which an impurity element imparting one conductivity type is added, and the conductive films65ato65care etched and separated. As a result, the second buffer layer42, the impurity semiconductor film63to which an impurity element imparting one conductivity type is added, and conductive films85ato85cas illustrated inFIG. 14Bcan be formed.

Next, ashing is performed on the resist mask81. As a result, the areas and the thickness of the resist are reduced. Accordingly, a region of the resist having a small thickness (a region overlapping with a part of the gate electrode51) is removed to form a separated resist mask86as illustrated inFIG. 14C.

Then, the conductive films85ato85care etched and separated using the resist mask86. As a result, pairs of wirings92ato92cas illustrated inFIG. 16Acan be formed. By wet etching the conductive films85ato85cusing the resist mask86, end portions of the conductive films85ato85care etched isotropically. As a result, the wirings92ato92cwith smaller areas than the resist mask86can be formed.

Then, the impurity semiconductor film63to which an impurity element imparting one conductivity type is added is etched using the resist mask86to form the pair of source and drain regions88as illustrated inFIG. 16B. Note that the second buffer layer42is also etched partly in this etching step. The partly etched second buffer layer is referred to as a second buffer layer87. Note that the second buffer layer87has a depressed portion. The source and drain regions and the depressed portion of the second buffer layer can be formed in the same process. Here, the second buffer layer87is partly etched using the resist mask86having a smaller area than the resist mask81; accordingly, the second buffer layer87is protruded from the source and drain regions88. In addition, the end portions of the wirings92ato92care not aligned with those of the source and drain regions88, and the end portions of the source and drain regions88are located beyond the end portions of the wirings92ato92c. After that, the resist mask86is removed.

Next, dry etching may be performed under such a condition that the buffer layer which is exposed is not damaged and an etching rate of the buffer layer is low. Through this step, an etching residue on the buffer layer between the source and drain regions, a residue of the resist mask, and a contamination source in the apparatus used for removal of the resist mask can be removed, whereby the source and drain regions can be certainly insulated. As a result, leakage current of the thin film transistor can be reduced; therefore, a thin film transistor with small off current and high withstand voltage can be manufactured. Note that a chlorine gas may be used for an etching gas, for example.

Through the above-described process, a channel-etched thin film transistor83can be formed. In addition, the thin film transistor can be formed using two photomasks.

After that, through a process similar to the process in Embodiment Mode 1, the protective insulating film76and the insulating film102are formed over the wiring92ato92c, the source and drain regions88, the second buffer layer87, and the gate insulating film52b, then, a contact hole is formed through a photolithography process using a fourth photomask as illustrated inFIG. 16C.

Then, the pixel electrode77is formed over the insulating film102through a photolithography process using a fifth photomask. Note thatFIG. 16Cis a cross-sectional view taken along line U-V inFIG. 17.

In this manner, a thin film transistor can be manufactured. Further, an element substrate which can be used for a display device can be formed.

Through the above-described process, an element substrate having a thin film transistor which can be used for a display device can be formed with photomasks the number of which is reduced by one compared to the number in Embodiment Mode 3.

In this embodiment mode, a process for manufacturing a thin film transistor having high mobility and ON current, and low off current is described below. Here, as a typical example, a method for manufacturing the thin film transistor ofFIG. 3in Embodiment Mode 1 is described.

In a manner similar to that in Embodiment Mode 3, the gate electrode51and the gate insulating films52aand52bare formed over the substrate50. Then, a semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or a conductive film is formed over the gate insulating film52b, and a buffer layer and an impurity semiconductor film to which an impurity element imparting one conductivity type is added are formed in that order over the semiconductor film. Then, a resist mask56is formed over the impurity semiconductor film to which an impurity element imparting one conductivity type is added, and the impurity semiconductor film to which an impurity element imparting one conductivity type is added, the buffer layer, and the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film are etched, whereby the semiconductor film58containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film58, the buffer layer42, and the impurity semiconductor film63to which an impurity element imparting one conductivity type is added are formed as illustrated inFIG. 18A.

Then, as illustrated inFIG. 18B, an insulating film67is formed over the impurity semiconductor film63to which an impurity element imparting one conductivity type is added and the gate insulating film52b. The insulating film67can be formed using a material similar to the material for the gate insulating films52aand52bas appropriate.

Then, a resist mask68is formed over the insulating film67. The resist mask68is provided to form an insulating film by partly etching the insulating film67. The insulating film is provided in a manner such that the wirings which are formed later are prevented from being in contact with a semiconductor film58containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or a conductive film58, and is in contact with the impurity semiconductor film63to which an impurity imparting one conductivity type is added. The resist mask68preferably has an opening which is smaller than an area of an upper surface of the insulating film63to which an impurity element imparting one conductivity type is added.

Then, as illustrated inFIG. 18C, the insulating film67is etched using the resist mask68to form the insulating film67awhich covers an end portion of the impurity semiconductor film63to which an impurity imparting one conductivity type is added.

Then, as illustrated inFIG. 19A, the conductive films65ato65care formed over the insulating film67aand the impurity semiconductor film63to which the impurity element imparting one conductivity type is added as in Embodiment Mode 3, and the resist mask66is formed over the conductive films65ato65c.

Then, as illustrated inFIG. 19B, the wirings71ato71care formed by etching the conductive films65ato65cusing the resist mask66.

Then, the impurity semiconductor film63to which an impurity element imparting one conductivity type is added is etched and separated using the resist mask66. As a result, the pair of source and drain regions72can be formed as illustrated inFIG. 20A. Note that in this etching process, the buffer layer42is also partly etched. The buffer layer which is partly etched and has a depressed portion is referred to as the buffer layer73.

Through the above-described process, a channel-etched thin film transistor31can be formed. Since the semiconductor film58containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film58and the wirings71ato71care isolated by the insulating film67a, leakage current between the semiconductor film58containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film58and the wirings71ato71ccan be reduced. Accordingly, a thin film transistor with low off current can be formed.

Then, a protective insulating film76is formed over the wiring71c, the gate insulating film52band the buffer layer73in a manner similar to that in Embodiment Mode 3. Then, the protective insulating film76is partly etched to form a contact hole and expose the wiring71cpartly. Then, as illustrated inFIG. 20C, the pixel electrode77is formed in the contact hole as in Embodiment Mode 3. Through the above-described process, an element substrate can be manufactured.

Through the above-described process, an element substrate having a thin film transistor with low off current can be manufactured. By using the element substrate, a display device with high contrast can be manufactured.

Next, a method for manufacturing a channel-protective thin film transistor, as illustrated inFIG. 4, in which leakage current can be reduced is described below.

In a manner similar to that of Embodiment Mode 3, a gate electrode51and gate insulating films52aand52bare formed over a substrate50. Then, through a process similar to the process in Embodiment Mode 5, a semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or a conductive film is formed over the gate insulating film52b. Then, a buffer layer is formed over the semiconductor film. Then, a resist mask is formed over the buffer layer, and then the buffer layer and the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film are etched to form the semiconductor film58containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film58and a buffer layer42.

Then, the insulating film67as illustrated inFIG. 18Bis formed over the buffer layer42, and the gate insulating film52b. Then, a resist mask is formed over the insulating film67and the insulating film67is etched using the resist mask to form the insulating films67aand67bas illustrated inFIG. 21A. Note that one contact hole may be formed around the insulating film67b. In that case, the insulating film67aand the insulating film67bare separated. Alternatively, a pair of contact holes may be formed. In that case, the insulating film67aand the insulating film67bare connected to each other. As a result, the insulating film67awhich covers an end portion of the buffer layer can be formed over the buffer layer42as well as the insulating film67bwhich serves as a channel protection film in the thin film transistor which is completed later.

Then, an impurity semiconductor film69to which an impurity element imparting one conductivity type is added is formed over an exposed portion of the buffer layer42, and the insulating films67aand67b. The impurity semiconductor film69to which an impurity element imparting one conductivity type is added can be formed in a manner similar to the impurity semiconductor film55to which an impurity imparting one conductivity type is added, which is described in Embodiment Mode 3.

Then, conductive films65ato65care formed over the impurity semiconductor film69to which an impurity element imparting one conductivity type is added. Then, a resist mask66is formed over the conductive films65ato65c.

Then, as illustrated inFIG. 21B, the conductive films65ato65care etched using the resist mask66to form wirings71ato71c. Then, the impurity semiconductor film69to which an impurity imparting one conductivity type is added is etched and separated using the resist mask66. As a result, a pair of source and drain regions70can be formed as illustrated inFIG. 21B. Note that in this etching process, the insulating film67bis also partly etched. The insulating film67bwhich is partly etched and has a depressed portion is referred to as a channel protection film67c.

Through the above-described process, a channel-protective thin film transistor32can be formed. Since the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film and the pair of source and drain regions70are isolated by the insulating film67a, leakage current between the semiconductor film58containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film58and the pair of source and drain regions70can be reduced. Accordingly, a thin film transistor with low off current can be formed. In addition, the channel protection film67ccan also be formed in formation of the insulating film67afor reducing leakage current.

Then, the protective insulating film76and the pixel electrode77which is in contact with the wiring71cvia the protective insulating film76are formed as illustrated inFIG. 21C, whereby an element substrate can be manufactured.

Through the above-described process, an element substrate having a thin film transistor with low off current can be manufactured. By using the element substrate, a display device with high contrast can be manufactured.

Next, a method for manufacturing a thin film transistor as illustrated inFIG. 5, in which leakage current can be reduced is described below.

After forming the wirings71ato71c, which are illustrated inFIG. 11Cand described in Embodiment Mode 3, the wirings92ato92c, which are illustrated inFIG. 16Band described in Embodiment Mode 4, the wirings71ato71c, which are illustrated inFIG. 19Band described in Embodiment Mode 5, or the wirings71ato71c, which are illustrated inFIG. 4and described in Embodiment Mode 6; a resist mask66or86is removed. Then, impurity semiconductor films63and69to which an impurity element imparting one conductivity type is added may be etched using the wirings71ato71cor the wiring92ato92cas a mask. As a result, the thin film transistor as illustrated inFIG. 5in which end portions of the wirings71ato71cor92ato92care aligned with end portions of the source and drain regions70,72, or88can be formed.

Next, a method for manufacturing a thin film transistor as illustrated inFIG. 7, in which leakage current can be reduced is described below.

Described inFIG. 7is one mode of a thin film transistor in which conductive particles60are dispersed over a gate insulating film52band in which a semiconductor film61containing germanium as its main component, covering the conductive particles60and the gate insulating film52bis included, instead of the semiconductor film58containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film58of the thin film transistors described in Embodiment Mode 1 to Embodiment Mode 7. Further a buffer layer62in contact with the semiconductor film61containing germanium as its main component is formed. Further, a buffer layer42acovering side of the semiconductor film61containing germanium as its main component and top and side of the buffer layer62.

The conductive particles60are formed by a thermal CVD method, a plasma CVD method, an ECRCVD method, an ion plating method, a sputtering method, a vacuum deposition method, or the like.

Next, by forming the film containing germanium as its main component over the conductive particles60, adhesion of the film containing germanium as its main component can be improved. Further, crystal growth is performed using the conductive particles60as crystal nuclei, whereby a microcrystal germanium film is formed as the semiconductor film61containing germanium as its main component.

When the semiconductor film61is formed by a CVD method, hydrogen is introduced to a reaction chamber of a plasma CVD apparatus together with a deposition gas containing germanium, a high-frequency power is applied to generate plasma, and an amorphous germanium film or a microcrystalline germanium film is formed as the semiconductor film61containing germanium as its main component. Alternatively, a deposition gas containing silicon is used together with hydrogen and a deposition gas containing germanium to form an amorphous silicon germanium film or a microcrystalline silicon germanium film.

Note that as one mode of forming an amorphous germanium film as the semiconductor film61containing germanium as its main component, an amorphous germanium film can be formed by glow discharge plasma using a deposition gas containing germanium in a reaction chamber. Alternatively, by dilution of a deposition gas containing germanium with one or plural kinds of rare gases selected from helium, argon, krypton, and neon, and by glow discharge plasma, an amorphous germanium film can be formed. Furthermore, an amorphous germanium film can be formed by glow discharge plasma using hydrogen with a flow rate greater than or equal to 1 and less than or equal to 10 times, preferably greater than or equal to 1 and less than or equal to 5 times as high as that of a deposition gas containing germanium. In addition, by using a deposition gas containing silicon together with a hydrogen and deposition gas containing germanium, an amorphous silicon germanium film can be formed as the semiconductor film61containing germanium as its main component.

Further, as one mode of forming a microcrystalline germanium film as the semiconductor film61containing germanium as its main component, a deposition gas containing germanium, which is germane here, and hydrogen and/or a rare gas are mixed, and a microcrystalline germanium film is formed by glow discharge plasma. Germane is diluted with hydrogen and/or a rare gas to be 10 times to 2000 times thinner. Therefore, a large amount of hydrogen and/or a rare gas is needed. The substrate heating temperature is 100° C. to 400° C., preferably 250° C. to 350° C. Further, by using a deposition gas containing silicon together with hydrogen and a deposition gas containing germanium, a microcrystalline silicon germanium film is formed as the semiconductor film61containing germanium as its main component.

In the step of forming the semiconductor film61containing germanium as its main component, glow discharge plasma is generated by applying high-frequency power with a frequency of 1 MHz to 20 MHz, typically 13.56 MHz, or high-frequency power with a frequency of more than 20 MHz to about 120 MHz, typically 27.12 MHz or 60 MHz. Alternatively, high-frequency plasma, for example, with a frequency of 1 GHz or 2.45 GHz can be employed.

After forming the conductive particles and the semiconductor film containing germanium as its main component, instead of the semiconductor film45containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film45which are described in Embodiment Mode 3, the thin film transistor illustrated inFIG. 7can be manufactured in a process similar to that in Embodiment Mode 3. Further, the thin film transistor can be formed in a process similar to that in any of Embodiment Modes 4 to 7.

In this embodiment mode, a preferred mode of Embodiment Modes 1 to Embodiment Mode 8 is described with reference toFIGS. 25A and 25B.

FIG. 25Aillustrates one mode of a thin film transistor of the present invention.FIG. 25Bis an enlarged view44of an upper portion of the buffer layer42.

In the present invention, the buffer layer42has a depressed portion in its upper portion. This is because in formation of the pair of source and drain regions72by etching an impurity semiconductor film to which an impurity element imparting one conductivity type is added, the buffer layer is also partly etched. In an etching step for forming the pair of source and drain regions72, it is preferable to perform anisotropic etching. As anisotropic etching, reactive ion beam etching (RIBE) using electronic cyclotron resonance (ECR) plasma, inductively coupled plasma (ICP) etching, or the like may be used. As a result, the depressed portion of the buffer layer42has a side surface42chaving an angle of 70° or more and 90° or less, preferably 80° or more and 90° or less to the substrate surface, whereby etching damage to the side surface42cin the depressed portion can be reduced.

The side surface42cof the depressed portion of the buffer layer42is a region where carriers flow when positive or negative voltage is applied to a gate electrode51. In this region, if there is a few defects due to etching damage, carriers are not easily trapped and can easily move when positive voltage is applied to the gate electrode51. Therefore, ON current and field effect mobility can be improved, which is preferable.

With the above-described structure, a thin film transistor with higher ON current and higher field effect mobility can be manufactured.

In this embodiment mode, a step before formation of the semiconductor film45containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film45described in Embodiment Mode 3 to Embodiment Mode 9 is described below. Here, Embodiment Mode 3 is used for description as a typical example, but this embodiment mode can be applied to any of Embodiment Modes 4 to 9 as appropriate.

As illustrated inFIG. 10A, the gate electrode51is formed over the substrate50, and the gate insulating films52aand52bare formed over the gate electrode51.

Next, a surface of the gate insulating film52bis subjected to plasma treatment. Typically, the surface of the gate insulating film52bis exposed to plasma, such as hydrogen plasma, ammonia plasma, helium plasma, argon plasma, or neon plasma. As plasma treatment, a substrate provided with the gate insulating film52bis placed in a reaction chamber. In addition, a gas such as hydrogen, ammonia, helium, argon, or neon is introduced into the reaction chamber, and glow discharge is carried out, whereby plasma such as hydrogen plasma, ammonia plasma, helium plasma, argon plasma, or neon plasma is generated and a surface of the gate insulating film can be exposed to the plasma.

By exposing the surface of the gate insulating film52bto plasma such as hydrogen plasma, ammonia plasma, helium plasma, argon plasma, or neon plasma, defects of the surface of the gate insulating film can be reduced. Typically, dangling bonds on the surface of the gate insulating film52bcan be terminated. Then, a semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or a conductive film is formed, thus, defects at the interface of the gate insulating film52band the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film can be reduced. Accordingly, trapping of carriers by defects can be reduced, whereby ON current can be improved.

In this embodiment mode, a film formation apparatus which can be used in a film formation process of the above embodiment modes and flow of a substrate therein are described below.

Description is made of a structure suitable for forming a gate insulating film, a semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at,% or a conductive film, a buffer layer, and an impurity semiconductor film to which an impurity element imparting one conductivity type is added, as an example of a plasma CVD apparatus which can be used for a film formation process of this embodiment mode. In this embodiment mode, as examples of the gate insulating film and the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film, a gate insulating film and a semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % are described.

FIG. 22illustrates an example of a multi-chamber plasma CVD apparatus having a plurality of reaction chambers. The apparatus is provided with a common chamber423, a load/unload chamber422, a first reaction chamber400a, a second reaction chamber400b, a third reaction chamber400c, and a fourth reaction chamber400d. This apparatus is a single wafer-processing type in which a substrate set in a cassette in the load/unload chamber422is transferred to/from each reaction chamber by a transfer mechanism426in the common chamber423. A gate valve425is provided between the common chamber423and each chamber so that treatment performed in the chambers does not interfere with each other.

Each reaction chamber is used for a different purpose, depending on the kinds of thin films to be formed. For example, an insulating film such as a gate insulating film is formed in the first reaction chamber400a, a semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % is formed in the second reaction chamber400b, a buffer layer which serves as a high resistance region of a thin film transistor is formed in the third reaction chamber400c, and an impurity semiconductor film to which an impurity element functioning as a donor and imparting one conductivity type is added, which forms a source and a drain, is formed in the fourth reaction chamber400d. Needless to say, the number of reaction chambers is not limited to four and may be increased or decreased as necessary.

A turbo-molecular pump419and a dry pump420are connected to each reaction chamber as an evacuation means. The evacuation means is not limited to a combination of these vacuum pumps and can be other vacuum pumps as long as they can evacuate the reaction chamber to a pressure of about 10−1Pa to 10−5Pa. A butterfly valve417which can interrupt vacuum evacuation is provided between the evacuation means and each reaction chamber. A conductance valve418can control an evacuation speed to adjust the pressure in each reaction chamber.

Note that the second reaction chamber400bin which a semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % is formed may be connected to a cryopump421which performs vacuum evacuation to an ultra-high vacuum. By using the cryopump421, the reaction chamber can be evacuated to an ultra-high vacuum of a pressure of lower than 10−5Pa. In this embodiment mode, the pressure in the reaction chamber is set to be at an ultra-high vacuum lower than 10−5Pa, which is effective in reduction of the oxygen concentration and the nitrogen concentration in the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. %. As a result, the oxygen concentration in the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % can be set to less than or equal to 1×1016at./cm3. When the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % is formed of a microcrystalline semiconductor film, by reducing concentrations of oxygen and nitrogen in the microcrystalline semiconductor film, a defect in the film is reduced and then crystallinity thereof can be increased, whereby the mobility of a carrier can be improved.

The gas supply means408includes the cylinder410which is filled with a gas used for the process, such as a rare gas or a semiconductor source gas typified by silane or germane, the stop valve412, the mass flow controller413, and the like. A gas supply means408gis connected to the first reaction chamber400aand supplies a gas for depositing the gate insulating film. A gas supply means408iis connected to the second reaction chamber400band supplies a gas for forming the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film. A gas supply means408bis connected to the third reaction chamber400cand supplies a gas for forming a buffer layer. A gas supply means408nis connected to the fourth reaction chamber400dand supplies a gas for forming an n-type semiconductor film, for example. A gas supply means408asupplies argon, a gas supply means408fis a system for supplying an etching gas used for cleaning the reaction chamber. These are common lines for reaction chambers.

A high-frequency power supply means for generating plasma is connected to each reaction chamber. The high-frequency power supply means includes a high-frequency power source404and a matching box406.

Each reaction chamber can be used for a different purpose depending on the kinds of thin films to be formed. Since each thin film has an optimum temperature for formation, the reaction chambers are provided separately, so that formation temperatures can be easily controlled. Further, the same kind of films can be repeatedly deposited, so that influence of residual impurities attributed to a film formed previously can be excluded. Particularly, in the case of the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. %, it is possible to prevent germanium from mixing into the buffer layer. Therefore, the concentration of an impurity in the buffer layer can be reduced, and off current in the thin film transistor can be reduced.

Then, one mode of a plasma CVD apparatus in which a gate insulating film, a semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. %, a buffer layer, and an impurity semiconductor film to which an impurity element imparting one conductivity type is added are formed successively in one reaction chamber is described with reference toFIG. 23.

The apparatus is provided with the common chamber423, the load/unload chamber422, a waiting chamber401, and the reaction chamber400a. This apparatus is a single wafer-processing type in which a substrate set in a cassette in the load/unload chamber422is transferred to/from each chamber by the transfer mechanism426in the common chamber423. The gate valve425is provided between the common chamber423and each chamber so that treatment performed in the chambers does not interfere with each other.

The turbo-molecular pump419and the dry pump420are connected to the reaction chamber400aas an evacuation means. The evacuation means is not limited to the combination of these vacuum pumps, and may be another vacuum pump as long as the evacuation can be performed to attain a degree of vacuum of about from 10−1Pa to 10−5Pa. The butterfly valve417, which can interrupt vacuum evacuation, is provided between the evacuation means430and the reaction chamber. The conductive valve418can control an evacuation speed to adjust the pressure in each reaction chamber. Further, the cryopump421may be connected to the reaction chamber400a.

The gas supply means408includes the cylinder410in which a gas used for the process, such as hydrogen or a semiconductor source gas typified by silane and germane is filled, the stop valve412, the mass flow controller413, and the like. The gas supply means408g,408i,408a,408n, and408fare connected to the reaction chamber400a.

A high-frequency power supply means403for generating plasma is connected to each reaction chamber. A high-frequency power supply means403includes the high-frequency power source404and the matching box406.

Next, a process for forming a plurality of films successively by the plasma CVD apparatus illustrated inFIG. 23is described with reference toFIGS. 24A to 24C.

FIG. 24Aillustrates the plasma CVD apparatus ofFIG. 23in a simplified manner.FIG. 24Bis a schematic view illustrating a process for successively forming a gate insulating film and a semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % (hereinafter, referred to as a μc-Ge film) over a substrate provided with a gate electrode. An arrow of a dotted line indicates flow of the substrate and an arrow of a solid line indicates flow of the forming process.

As illustrated inFIG. 24B, the inner wall of the reaction chamber400ais cleaned with fluorine radicals or the like (S461), to remove residual impurities in the reaction chamber400a. Then, the inner wall of the reaction chamber400ais coated with a film which is similar to the gate insulating film (S462). Due to this coating step, metals which form the reaction chamber400acan be prevented from mixing into the gate insulating film as impurities.

Then, the substrate set in the cassette in the load/unload chamber422is transferred to the reaction chamber400aby the transfer mechanism426in the common chamber423as indicated by the arrow al. Then, the gate insulating film, which is a silicon oxynitride film here, is formed over the substrate in the reaction chamber400a(S463).

Next, the substrate over which the gate insulating film is formed is transferred to the waiting chamber401by the transfer mechanism426in the common chamber423as indicated by an arrow a2, and the substrate is kept in waiting state (S464). Then, the inner wall of the reaction chamber400ais cleaned with fluorine radicals or the like (S465) to remove residual impurities in the reaction chamber400a. Then, the inner wall of the reaction chamber400ais coated with an amorphous semiconductor film (S466). By this cleaning and coating, components (oxygen, nitrogen, or the like) of the gate insulating film which is deposited on the inner wall of the reaction chamber400aand metals which form the reaction chamber400acan be prevented from mixing, as impurities, into the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. %. In addition, in the case where the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % is formed of a microcrystalline semiconductor film, the crystallinity of the microcrystalline semiconductor film can be improved. Then, the substrate is transferred to the reaction chamber400aby the transfer mechanism426in the common chamber423, as indicated by an arrow a3, to form the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % in the reaction chamber400a(S467). Here, as the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. %, germane and hydrogen are used as a source gas, and a microcrystalline germanium film is formed.

Then the substrate over which the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % is formed is transferred to the waiting chamber401by the transfer mechanism426in the common chamber423as indicated by the arrow a2(S470). After that, the inner wall of the reaction chamber400ais cleaned with fluorine radicals or the like (S468) to remove residual impurities in the reaction chamber400a. Then, the inner wall of the reaction chamber400ais coated with an amorphous semiconductor film (S469). By this cleaning and coating, metals which form the reaction chamber400acan be prevented from mixing, as impurities, into the amorphous semiconductor film which is formed later. Accordingly, the amorphous semiconductor film can serve as a high resistance region. Then, the substrate is transferred to the reaction chamber400aby the transfer mechanism426in the common chamber423, as indicated by the arrow a3, to form an amorphous semiconductor film as a first buffer layer in the reaction chamber400a(S471). Here, as the amorphous semiconductor film, a silane and hydrogen are used as a source gas and an amorphous silicon film is formed.

The substrate over which the first buffer layer is formed is set in the cassette in the load/unload chamber422by the transfer mechanism426in the common chamber423as indicated by an arrow a4. Through the above-described process, the gate insulating film, the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. %, and the first buffer layer can be formed successively over the substrate over which the gate electrode has been formed. Next, the inner wall of the reaction chamber400ais cleaned with fluorine radicals or the like (S472) to remove residual impurities in the reaction chamber400a. Then, the inner wall of the reaction chamber400ais coated with a film which is similar to the gate insulating film (S473). Then, another substrate which is set in the cassette in the load/unload chamber422is transferred to the reaction chamber400a, and the steps similar to the above steps are performed on the substrate, starting with film formation of a gate insulating film (S463), to successively form the gate insulating film, a semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. %, and a first buffer layer.

After the gate insulating films, the semiconductor films containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. %, and the first buffer layers are formed over all the substrates set in the cassette in the load/unload chamber422, the cassette is transferred from the load/unload chamber422to be subjected to a next process.

Note that although the substrate over which the gate insulating film and the μc-Ge film is formed is kept in a waiting state in the waiting chamber401, the substrate may be kept in a waiting state in the load/unload chamber422. Thus, the plasma CVD apparatus can be simplified and cost can be reduced.

FIG. 24Cillustrates a process for successively forming a second buffer layer and an impurity semiconductor film to which an impurity element imparting one conductivity type is added (hereinafter, referred to as an n+a-Si film) over the first buffer layer and the semiconductor layer containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. %, which has been formed to have an island shape. An arrow of a dotted line indicates flow of the substrate and an arrow of a solid line indicates flow of the forming process.

As illustrated inFIG. 24C, the inner wall of the reaction chamber400ais cleaned with fluorine radicals or the like (S481), to remove residual impurities in the reaction chamber400a. Then, the inner wall of the reaction chamber400ais coated with a film which is similar to the second buffer layer (S482). Here, an amorphous silicon film is formed. By this coating step, metals which form the reaction chamber400acan be prevented from mixing into the gate insulating film as impurities.

Then, the substrate set in the cassette in the load/unload chamber422is transferred to the reaction chamber400aby the transfer mechanism426in the common chamber423as indicated by the arrow a1. Then, the second buffer layer, which is an amorphous silicon film here, is formed over the substrate in the reaction chamber400a(S483).

Next, the impurity semiconductor film to which an impurity element imparting one conductivity type is added (here, referred to as the n+a-Si film) is formed over the substrate over which the second buffer layer has been formed (S484). Here, since the main components in the amorphous silicon film and the n+a-Si film are the same and the amorphous silicon does not contain any contaminant for the n+a-Si film, a coating step is not necessarily performed before formation of the n+a-Si film.

Next, the substrate over which the n+a-Si film has been formed is set in the cassette in the load/unload chamber422by the transfer mechanism426in the common chamber423as indicated by an arrow a4. Through the above-described process, the second buffer layer and the n+a-Si film can be formed successively over the substrate over which the island shaped semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % has been formed. Next, the inner wall of the reaction chamber400ais cleaned with fluorine radicals or the like (S485) to remove residual impurities in the reaction chamber400a. Then, the inner wall of the reaction chamber400ais coated with a film which is similar to the second buffer layer (S486). Then, another substrate which is set in the cassette in the load/unload chamber422is transferred to the reaction chamber400a, and the steps similar to the above steps are performed on the substrate, starting with film formation of a second buffer layer (S483) to successively form a second buffer layer and the n+a-Si film.

After the second buffer layers and n+a-Si films are formed over all the substrates set in the cassette in the load/unload chamber422, the cassette is transferred from the load/unload chamber422to be subjected to a next process.

Through the above-described process, a plurality of films can be formed successively without being exposed to the air. Further, the films can be formed without contaminants mixing into the films.

Note that a semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % is used in this embodiment mode; however, a conductive film can be formed by using a source gas for the conductive film in a gas supply system. Further, a reaction chamber in which sputtering can be performed is connected to the film formation apparatus illustrated inFIG. 22, FIG,23, andFIG. 24A, whereby the conductive film can be formed successively.

In this embodiment mode, a liquid crystal display device including a thin film transistor described in the above-described embodiment modes will be described below as one mode of the display device. Here, a vertical alignment (VA) liquid crystal display device is described with reference toFIG. 26,FIG. 27andFIG. 28. The VA mode is a kind of form in which orientation of liquid crystal molecules of a liquid crystal panel is controlled. The VA mode liquid crystal display device is a form in which liquid crystal molecules are vertical to a panel surface when voltage is not applied. In this embodiment mode, it is devised to particularly separate pixels into some regions (sub-pixels) so that molecules are aligned in different directions in the respective regions. This is referred to as multi-domain or multi-domain design. In the following description, a liquid crystal display device with multi-domain design is described.

FIG. 26andFIG. 27illustrate a pixel structure of a VA mode liquid crystal panel.FIG. 27is a plane view over a substrate600.FIG. 26illustrates a cross-sectional structure taken along a line Y-Z inFIG. 27. The following explanation will be made with reference to these drawings.

In this pixel structure, a plurality of pixel electrodes624and626is included in one pixel, and thin film transistors628and629are connected to the pixel electrodes624and626, respectively, through a planarization film622. The thin film transistors628and629are driven by different gate signals. That is, a pixel of multi-domain design has a structure in which a signal applied to each of the pixel electrodes624and626is independently controlled.

The pixel electrode624is connected to the thin film transistor628via a wiring618in a contact hole623. Further, the pixel electrode626is connected to the thin film transistor629via a wiring619in a contact hole627. A gate electrode602of the thin film transistor628and a gate electrode603of the thin film transistor629are separated so that different gate signals can be given thereto. On the other hand, a wiring616functioning as a data line is used in common for the thin film transistors628and629. The thin film transistors628and629can be manufactured by the methods described in the above-described embodiment modes. Further a capacitor wiring690is formed.

The pixel electrodes624and626have different shapes. The pixel electrodes624and626are separated by a slit625. The pixel electrode626is formed so as to surround the outside of the pixel electrode624which is expanded in a V-shape. Timing of voltage application is made to vary between the pixel electrodes624and626by the thin film transistors628and629in order to control orientation of the liquid crystal. When different gate signals are supplied to the gate wirings602and603, operation timings of the thin film transistors628and629can vary. An orientation film648is formed over the pixel electrodes624and626.

A counter substrate601is provided with a light-blocking film632, a coloring film636, and a counter electrode640. Moreover, a planarization film637is formed between the coloring film636and the counter electrode640to prevent alignment disorder of the liquid crystal. In addition, the orientation film646is provided for the counter electrode640.FIG. 28illustrates a structure on a counter substrate side. The counter electrode640is an electrode shared by different pixels and a slit641is formed. This slit641is disposed so as to alternatively mesh with the slit625on the side of the pixel electrodes624and626, whereby an oblique electric field is generated effectively to control orientation of liquid crystals. Accordingly, the direction in which liquid crystals are oriented is made different depending on a place, and a viewing angle of the liquid crystal panel is expanded.

In this specification, a substrate, a coloring film, a light-blocking film, and a planarization film form a color filter. Note that either the light-blocking film or the planarization film, or both of them are not necessarily formed over the substrate.

The coloring film has a function of preferentially transmitting light of a predetermined wavelength range, among light of the wavelength range of visible light. In general, a coloring film which preferentially transmits light of a wavelength range of red light, a coloring film which preferentially transmits light of a wavelength range of blue light, and a coloring film which preferentially transmits light of a wavelength range of green light are combined to be used for the color filter. However, the combination of the coloring films is not limited to the above combination.

A first liquid crystal element is formed by overlapping the pixel electrode624, the liquid crystal layer650, and the counter electrode640. A second liquid crystal element is formed by overlapping of the pixel electrode626, the liquid crystal layer650, and the counter electrode640. This is a multi-domain structure in which the first liquid crystal element and the second liquid crystal element are included in one pixel.

Although a vertical alignment (VA) mode liquid crystal display device is described here, the element substrate formed in accordance with the above-described embodiment modes can also be applied to an FFS mode liquid crystal display device, an IPS mode liquid crystal display device, a TN mode liquid crystal display device, and the like.

Through the above-described steps, the liquid crystal display device can be manufactured. Since an inverted staggered thin film transistor with small off current and high electric characteristics is used for the liquid crystal display device of this embodiment mode, the liquid crystal display device with high contrast and high visibility can be manufactured.

In this embodiment mode, a light-emitting device including a thin film transistor in accordance with any of the above-described embodiment modes will be described as one mode of a display device. Here, a structure of a pixel included in the light-emitting device will be described.FIG. 29Aillustrates one mode of a top view of the pixel, andFIG. 29Billustrates one mode of a cross-sectional structure of the pixel corresponding to a line A-B inFIG. 29A.

A display device including a light-emitting element utilizing electroluminescence is described as a light-emitting device. Light emitting elements utilizing electroluminescence are classified according to whether a light emitting material is an organic compound or an inorganic compound. In general, the former is referred to as an organic EL element, the latter as an inorganic EL element. In this embodiment mode, the process for manufacturing the thin film transistor in accordance with any of the above-described embodiment modes can be used.

In an organic EL element, by application of a voltage to a light-emitting element, electrons and holes are separately injected from a pair of electrodes into a layer containing a light-emitting organic compound, and current flows. The electrons and holes (i.e., carriers) are recombined, and thus, the light-emitting organic compound is excited. The light-emitting organic compound returns to a ground state from the excited state, thereby emitting light. Because of such a mechanism, such a light emitting element is referred to as a current-excitation light emitting element.

InFIGS. 29A and 29B, a first thin film transistor74acorresponds to a thin film transistor for switching which controls input of a signal to a pixel electrode, and a second thin film transistor74bcorresponds to a thin film transistor for driving which controls supply of current or voltage to a light-emitting element94.

A gate electrode of the first thin film transistor74ais connected to a scanning line51a, one of a source and a drain thereof is connected to a wiring71ato71cwhich function as signal lines, and the other of the source and the drain is connected to a gate electrode51bof the second thin film transistor74bvia a wiring71dto71f. One of a source and a drain of the second thin film transistor74bis connected to a power source line93ato93c, and the other of the source and the drain is connected to a first electrode79of light-emitting element via a wiring93dto93f. A gate electrode, a gate insulating film, and the power supply line93aof the second thin film transistor74bform a capacitor element96, and the other of the source and the drain of the first thin film transistor74ais connected to the capacitor element96.

Note that the capacitor96corresponds to a capacitor for holding a voltage between the gate and the source or between the gate and the drain of the second thin film transistor74b(hereinafter referred to as a gate voltage) when the first thin film transistor74ais off, and the capacitor96is not necessarily provided.

In this embodiment mode, the first thin film transistor74aand the second thin film transistor74bcan be each formed using the thin film transistor described in the above-described embodiment modes. Here, the first thin film transistor74aand the second thin film transistor74bare formed of n-channel thin film transistors; however, the first thin film transistor74amay be formed of an n-channel thin film transistor and the second thin film transistor74bmay be formed of a p-channel thin film transistor. Alternatively, the first thin film transistor74aand the second thin film transistor74bmay be formed of p-channel thin film transistors.

A protective insulating film76is formed over the first thin film transistor74aand the second thin film transistor74b, a planarization film78is formed over the protective insulating film76, and then the first electrode79is formed to be connected to a wiring93fin a contact hole formed in the planarization film78and the protective insulating film76. The planarization film78is preferably formed using an organic resin such as acrylic, polyimide, or polyamide, or a siloxane polymer. Since the first electrode79is uneven due to the contact hole, a partition wall91having an opening is provided to cover the uneven portion of the first electrode79. In the opening of the partition wall91, an EL layer92is formed so as to be in contact with the first electrode79, and a second electrode93is formed so as to cover the EL layer92. A protective insulating film95is formed so as to cover the second electrode93and the partition wall91.

Here, a light-emitting element94with a top emission structure will be described as a light-emitting element. The light-emitting element94with a top emission structure can emit light even over the first thin film transistor74aor the second thin film transistor74b; thus, a light emission area can be increased. However, if a base film of the EL layer92is uneven, the thickness is nonuniform due to unevenness, and the second electrode93and the first electrode79are short-circuited, so that a display defect is caused. Therefore, a planarization film78is preferably provided.

The light-emitting element94corresponds to a region where the first electrode79and the second electrode93sandwich the EL layer92. In the case of the pixel illustrated inFIG. 29B, light from the light-emitting element94is emitted to the second electrode93side as indicated by an outline arrow.

As the first electrode79functioning as a cathode, a known conductive film can be used as long as it has a low work function and reflects light. For example, Ca, Al, MgAg, AlLi, or the like is preferably used. The light-emitting layer92may be formed using either a single layer or a plurality of stacked layers. When the EL layer92is formed using a plurality of stacked layers, an electron-injection layer, an electron-transporting layer, a light-emitting layer, a hole-transporting layer, and a hole-injecting layer are stacked in this order over the first electrode79functioning as a cathode. Note that all these layers are not necessarily provided. The second electrode93functioning as an anode is formed using a light-transmitting conductive material such as a light-transmitting conductive film of indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, indium tin oxide including titanium oxide, ITO, indium zinc oxide, or indium tin oxide to which silicon oxide is added.

Here, a light-emitting element with a top emission structure in which light emission is extracted through a surface opposite to a substrate side is described; however, a light-emitting element with a bottom emission structure in which light emission is extracted through a surface on the substrate side, or a light-emitting element with a dual emission structure in which light emission is extracted through the surface opposite to the substrate side and the surface on the substrate side can be used as appropriate.

Although an organic EL element is described here as a light-emitting element, an inorganic EL element can also be provided as a light-emitting element.

Note that, in this embodiment mode, an example in which a thin film transistor for controlling the driving of a light-emitting element (the driving thin film transistor) is connected to the light-emitting element is described; however, a thin film transistor for controlling current may be connected between the driving thin film transistor and the light-emitting element.

Through the above-described process, a light-emitting display device can be manufactured. Since an inverted staggered thin film transistor with small off current and high electric characteristics is used for the light-emitting device of this embodiment mode, the light-emitting display device with high contrast and high visibility can be manufactured.

Next, a structure of a light-emitting panel, which is one mode of a light-emitting device of the present invention, is described below.

FIG. 30Aillustrates a mode of a display panel in which a pixel portion6012formed over a substrate6011is connected to signal line driver circuits6013that are formed separately. The pixel portion6012and a scanning line driver circuits6014are each formed using the thin film transistor described in the above-described embodiment modes. By forming the signal line driver circuit with a thin film transistor by which higher field effect mobility can be obtained than a thin film transistor in which an amorphous semiconductor film is used for a channel formation region, operation of the signal line driver circuit, which demands a higher driving frequency than the scanning line driver circuit, can be stabilized. Note that the signal line driver circuits6013may be formed using a transistor using a single crystal semiconductor for a channel formation region, a thin film transistor using a polycrystalline semiconductor for a channel formation region, or a transistor using SOI for a channel formation region. The pixel portion6012, the signal line driver circuits6013, and the scanning line driver circuits6014are each supplied with potential of a power source, various signals, and the like via an FPC6015. Further, a protection circuit may be provided between the signal line driver circuits6013and the FPC6015or between the signal line driver circuits6013and the pixel portion6012. The protection circuit includes one or more elements selected from a thin film transistor, a diode, a resister element, a capacitor element, and the like.

Note that the signal driver circuit and the scanning line driver circuit may both be formed over the same substrate as that of the pixel portion.

Also, when the driver circuit is separately formed, a substrate provided with the driver circuit is not always required to be attached to a substrate provided with the pixel portion, and may be attached to, for example, the FPC.FIG. 30Billustrates a mode of a panel of a display device in which signal line driver circuits6023are formed separately and are connected to a pixel portion6022and scanning line driver circuits6024that are formed over a substrate6021. The pixel portion6022and the scanning line driver circuit6024are each formed using the thin film transistor described in the above-described embodiment modes. The signal line driver circuits6023are connected to the pixel portion6022via an FPC6025. The pixel portion6022, the signal line driver circuits6023, and the scanning line driver circuits6024are each supplied with potential of a power source a variety of signals, and the like via the FPC6025. Further, a protection circuit may be provided between the signal line driver circuits6023and the FPC6025or between the signal line driver circuits6023and the pixel portion6022.

Furthermore, only part of the signal line driver circuit or only part of the scanning line driver circuit may be formed over the same substrate as the pixel portion using the thin film transistor described in the above-described embodiment modes, and the rest may be formed separately and electrically connected to the pixel portion.FIG. 30Cillustrates a mode of a panel of a display device in which an analog switch6033aincluded in a signal driver circuit is formed over a substrate6031, over which a pixel portion6032and scanning line driver circuits6034are formed, and shift registers6033bincluded in the signal line driver circuit is formed separately over a different substrate and then attached to the substrate6031. The pixel portion6032and the scanning line driver circuit6034are each formed using the thin film transistor described in the above-described embodiment modes. The shift resistors6033bincluded in the signal line driver circuit are connected to the pixel portion6032via an FPC6035. The pixel portion6032, the signal line driver circuit, and the scanning line driver circuits6034are each supplied with potential of a power source, a variety of signals, and the like via the FPC6035. Further, a protection circuit may be provided between the shift register6033band the FPC6035or between the shift register6033band the analog switch6033a.

As illustrated inFIGS. 30A to 30C, in display devices of this embodiment mode, all or a part of the driver circuit can be formed over the same substrate as the pixel portion, using the thin film transistor described in the above-described embodiment modes.

Note that there are no particular limitations on a connection method of a separately formed substrate, and a known method such as a COG method, a wire bonding method, or a TAB method can be used. Further, a connection position is not limited to the position illustrated inFIGS. 30A to 30C, as long as electrical connection is possible. Also, a controller, a CPU, a memory, or the like may be formed separately and connected.

Note that the signal line driver circuit used in the present invention includes a shift register and an analog switch. In addition to the shift register and the analog switch, another circuit such as a buffer, a level shifter, or a source follower may be included. Also, the shift resistor and the analog switch is not always required to be provided, and for example a different circuit such as a decoder circuit by which selection of signal line is possible may be used instead of the shift resistor, and a latch or the like may be used instead of the analog switch.

The display device or the like obtained according to the present invention can be used for an active matrix display device panel. That is, the present invention can be applied to all electronic devices incorporating them in display portions.

Examples of such electronic devices include cameras such as a video camera and a digital camera, a head-mounted display (a goggle-type display), a car navigation system, a projector, a car stereo, a personal computer, and a portable information terminal (e.g., a mobile computer, a cellular phone, and an e-book reader). Examples of these devices are illustrated inFIGS. 31A to 31D.

FIG. 31Aillustrates a television device. A television device can be completed by incorporating a display panel into a housing as illustrated inFIG. 31A. A main screen2003is formed using the display panel, and other accessories such as a speaker portion2009and an operation switch are provided. In such a manner, a television device can be completed.

As illustrated inFIG. 31A, a display panel2002using a display element is incorporated in a housing2001. When a receiver2005is used, general reception of TV broadcast can be performed; moreover, communication of information in one way (from a transmitter to a receiver) or in two ways (between a transmitter and a receiver or between receivers) by connection to a wired or wireless communication network through a modem2004can also be performed. The television device can be operated by using a switch incorporated in the housing or a remote control unit2006. Also, a display portion2007for displaying output information may also be provided in the remote control unit.

Further, the television device may include a sub screen2008formed using a second display panel for displaying channels, sound volume, and the like, in addition to the main screen2003. In this structure, the main screen2003may be formed using a liquid crystal display panel, and the sub screen may be formed using a light-emitting display panel. Alternatively, a structure may be employed in which the main screen2003is formed using a light-emitting display panel, the sub screen is formed using a light-emitting display panel, and the sub screen can be turned on and off.

FIG. 32is a block diagram illustrating a main structure of the television device. A display panel is provided with a pixel portion921. A signal line driver circuit922and a scanning line driver circuit923may be mounted on the display panel by a COG method.

As for other external circuits, the television device includes a video signal amplifier circuit925which amplifies a video signal among signals received by a tuner924; a video signal processing circuit926which converts a signal output from the video signal amplifier circuit925into a color signal corresponding to each color of red, green, and blue; a control circuit927which converts the video signal into an input specification of a driver IC; and the like. The control circuit927outputs signals to each of the scanning line side and the signal line side. When digital driving is performed, a structure may be employed in which a signal dividing circuit928is provided on the signal line side and an input digital signal is divided into m signals to be supplied.

Among the signals received by the tuner924, an audio signal is transmitted to an audio signal amplifier circuit929, and an output thereof is supplied to a speaker933through an audio signal processing circuit930. A control circuit931receives control information on receiving station (receiving frequency) and volume from an input portion932and transmits a signal to the tuner924and the audio signal processing circuit930.

Needless to say, the invention is not limited to the television device and can be used as a large area display medium for various applications such as a monitor of a personal computer, an information display at a train station, airport and the like, an advertisement display on the streets, and the like.

The display device described in the above-described embodiment mode is applied to each of the main screen2003and the sub screen2008, whereby mass productivity of television devices with improved image quality, such as contrast, can be increased.

FIG. 31Billustrates one example of a cellular phone2301. The cellular phone2301includes a display portion2302, an operation portion2303, and the like. The display device described in any of the preceding embodiment modes is applied to the display portion2302, so that mass productivity of the mobile phone with improved image quality, such as contrast, can be increased.

A portable computer illustrated inFIG. 31Cincludes a main body2401, a display portion2402, and the like. The display device described in any of the preceding embodiment modes is applied to the display portion2402, so that mass productivity of the computer with improved image quality, such as contrast, can be improved.

FIG. 31Dillustrates a desk lamp including a lighting portion2501, a shade2502, an adjustable arm2503, a support2504, a base2505, and a power supply switch2506. The desk lamp can be manufactured by applying the light-emitting device of the present invention to the lighting portion2501. Note that the lamp includes ceiling lights, wall lights, and the like in its category. Use of the display device described in any of the preceding embodiment modes can increase mass productivity and provide inexpensive desk lamps.

FIGS. 33A to 33Cillustrate an example of a structure of a smartphone to which the present invention is applied.FIG. 33Ais a front view,FIG. 33Bis a rear view, andFIG. 33Cis a development view. The smartphone has two housings1001and1002. The smartphone has both a function of a cellular phone and a function of a portable information terminal, and incorporates a computer which conducts a variety of data processing in addition to verbal communication; therefore, it is called smartphone.

The smartphone has the two housings1001and1002. The housing1001includes a display portion1101, a speaker1102, a microphone1103, operation keys1104, a pointing device1105, a front camera lens1106, a jack1107for an external connection terminal, an earphone terminal1008, and the like, while the housing1002includes a keyboard1201, an external memory slot1202, a rear camera lens1203, a light1204, and the like. In addition, an antenna is incorporated in the housing1001.

In addition to the above-described structure, the smartphone may incorporate a non-contact IC chip, a small size memory device, or the like.

The housing1001and housing1002(FIG. 33A) which are put together to be lapped with each other are developed by sliding as illustrated inFIG. 33C. In the display portion1101, the display device described in the above embodiment mode can be incorporated, and display direction can be changed depending on a use mode. Because the front camera lens1106is provided in the same plane as the display portion1101, the cellular phone can be used as a videophone. A still image and a moving image can be taken by the rear camera1203and the light1204by using the display portion1101as a viewfinder.

The speaker1102and the microphone1103can be used for videophone, recording, playback, and the like without being limited to verbal communication. With use of the operation keys1104, operation of incoming and outgoing calls, simple information input of electronic mails or the like, scrolling of a screen, cursor motion and the like are possible.

If much information is needed to be treated, such as documentation, use as a portable information terminal, and the like, the use of the keyboard1201is convenient. When the housing1001and the housing1002which are put together to be lapped with each other (FIG. 33A) are developed by sliding as illustrated inFIG. 33Cand the smartphone is used as a portable information terminal, smooth operation can be conducted by using the keyboard1201and the pointing device1105. The jack1107for an external connection terminal can be connected to an AC adaptor and various types of cables such as a USB cable, and charging and data communication with a personal computer or the like are possible. Moreover, a large amount of data can be stored by inserting a storage medium into the external memory slot1202and can be moved.

In the rear surface of the housing1002(FIG. 33B), the rear camera1203and the light1204are provided, and a still image and a moving image can be taken by using the display portion1101as a viewfinder.

Further, the smartphone may have an infrared communication function, a USB port, a function of receiving one segment television broadcast, a non-contact IC chip, an earphone jack, or the like, in addition to the above-described functions and structures.

Use of the display device described in the preceding embodiment modes can increase mass productivity.

This application is based on Japanese Patent Application serial no. 2007-339409 filed with Japan Patent Office on Dec. 28, 2007, the entire contents of which are hereby incorporated by reference.