Determining timing associated with an input or output of an embedded circuit in an integrated circuit for testing

Method and system for testing an integrated circuit and more particularly, for determining timing associated with an input or output of an embedded circuit, in an integrated circuit for testing are described. A bit is adjustably delayed with a first adjustable delay to provide a delayed bit. The delayed bit is provided to a bus, such as an input bus for example, of the embedded circuit as a second vector. A third vector is output from the embedded circuit responsive to the second vector. A fourth vector is obtained having second multiple bits. The fourth vector is compared with the third vector to determine a period of delay associated with at least approximately a maximum operating frequency of the embedded circuit.

FIELD OF THE INVENTION

One or more aspects of the invention relate generally to integrated circuits and, more particularly, to determining timing associated with an input or output of an embedded circuit in an integrated circuit for testing.

BACKGROUND OF THE INVENTION

One such FPGA is the Xilinx Virtex® FPGA available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124. Another type of PLD is the Complex Programmable Logic Device (“CPLD”). A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, for example, using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.

For purposes of clarity and not limitation, FPGAs are described below though other types of integrated circuits having embedded circuits may be used. FPGAs may include one or more embedded blocks, such as one or more embedded microprocessors. For example, a microprocessor may be located in an area reserved for it, generally referred to as a “processor block.”

Heretofore, performance of an embedded block in programmable logic of an FPGA (“FPGA fabric”) was determined by building a ring oscillator and measuring timing associated with an input or output of an embedded block. A maximum frequency of operation may be determined from what is known as a Minimum Cycle Time of the ring oscillator. In other words, the minimum time in which a signal cycles through the ring oscillator may be used to determine a maximum frequency of operation of an embedded block included as part of the ring of the ring oscillator. Unfortunately, as embedded blocks become more complex, it becomes more problematic to test to find a Minimum Cycle Time as associated with a particular active path in an embedded block. For example, an embedded block may involved complex input sequences to operate properly. Or, it may take many cycles to observe results of testing.

Accordingly, it would be desirable and useful to provide means for determining timing associated with a maximum frequency of operation of an embedded block in an integrated circuit that is not as constrained by complex input sequences or has less test cycle latency or both than in the past.

SUMMARY OF THE INVENTION

One or more aspects of the invention generally relate to integrated circuits and, more particularly, to determining timing associated with an input or output of an embedded circuit in an integrated circuit.

An aspect of the invention is a method for testing an integrated circuit. A first vector is obtained having first multiple bits. The first vector is pipelined to provide a pipelined version of the first vector responsive to a clock signal. A bit of the first multiple bits of the pipelined version of the first vector is provided to a first adjustable delay. A remainder of the first multiple bits of the pipelined version of the first vector is provided to an input bus of an embedded circuit, the embedded circuit being provided as part of the integrated circuit. The bit is adjustably delayed with the first adjustable delay to provide a delayed bit that is delayed with respect to the remainder of the first multiple bits. The delayed bit is provided to the input bus of the embedded circuit. The first multiple bits including the delayed bit are provided to the input bus as a second vector. A third vector is output from the embedded circuit responsive to the second vector. A fourth vector is obtained having second multiple bits. The fourth vector is compared with the third vector to determine a first minimum period of delay associated with at least approximately a maximum operating frequency of the embedded circuit.

Another aspect of the invention is another method for testing an integrated circuit. A first vector having first multiple bits is obtained by an input bus of an embedded circuit, the embedded circuit being provided as part of the integrated circuit. A second vector having second multiple bits is output from an output bus of the embedded circuit responsive to the first vector and to a clock signal. A bit of the second multiple bits of the second vector is provided to a first adjustable delay. A remainder of the second multiple bits is provided to a pipeline. The bit is adjustably delayed with the first adjustable delay to provide a delayed bit that is delayed with respect to the remainder of the second multiple bits. The delayed bit is provided to the pipeline. The second multiple bits including the delayed bit are provided to the pipeline as a third vector. The third vector is provided from the pipeline responsive to the clock signal. A fourth vector having third multiple bits is obtained. The fourth vector is compared with the third vector to determine a first minimum period of delay associated with at least approximately a maximum operating frequency of the embedded circuit.

Yet another aspect of the invention is a test system for an integrated circuit. The system includes: a first storage device is for storing a first vector of a set of function verification vectors; an embedded circuit under test; a comparison circuit; a second storage device for storing a set of expected results vectors associated with the set of function verification vectors; and a delay macro for programming programmable logic to provide a delay line. The delay line is programmable to adjust delay of the delay line. The delay macro is programmably coupled to receive a bit signal and is configured to provide a delayed bit signal. The bit signal is from a first vector of the set of function verification vectors. The storage device, the delay line, and the embedded circuit operate with reference to a same clock signal. The embedded circuit is coupled to receive the first vector with the delayed bit signal and is configured to provide a second vector in response to the first vector with the delayed bit signal. The comparison circuit is coupled to receive the second vector and a third vector, the third vector being from the set of expected results vectors and being associated with the first vector. The comparison circuit is configured to compare the second vector with the third vector to identify at least approximately a first maximum frequency of operation of the embedded circuit for input to an input bus thereof.

DETAILED DESCRIPTION OF THE DRAWINGS

In the following description, numerous specific details are set forth to provide a more thorough description of the specific embodiments of the invention. It should be apparent, however, to one skilled in the art, that the invention may be practiced without all the specific details given below. In other instances, well known features have not been described in detail so as not to obscure the invention. For ease of illustration, the same number labels are used in different diagrams to refer to the same items; however, in alternative embodiments the items may be different.

FIG. 1illustrates an FPGA architecture100that includes a large number of different programmable tiles including multi-gigabit transceivers (“MGTs”)101, configurable logic blocks (“CLBs”)102, random access memory blocks (“BRAMs”)103, input/output blocks (“IOBs”)104, configuration and clocking logic (“CONFIG/CLOCKS”)105, digital signal processing blocks (“DSPs”)106, specialized input/output ports (“I/O”)107(e.g., configuration ports and clock ports), and other programmable logic108such as digital clock managers, analog-to-digital converters, system monitoring logic, and so forth. Some FPGAs also include dedicated processor blocks (“PROC”)110.

In some FPGAs, each programmable tile includes a programmable interconnect element (“INT”)111having standardized connections to and from a corresponding interconnect element111in each adjacent tile. Therefore, the programmable interconnect elements111taken together implement the programmable interconnect structure for the illustrated FPGA. Each programmable interconnect element111also includes the connections to and from any other programmable logic element(s) within the same tile, as shown by the examples included at the right side ofFIG. 1.

In the pictured embodiment, a columnar area near the center of the die (shown shaded inFIG. 1) is used for configuration, I/O, clock, and other control logic. Vertical areas109extending from this column are used to distribute the clocks and configuration signals across the breadth of the FPGA.

Some FPGAs utilizing the architecture illustrated inFIG. 1include additional logic blocks that disrupt the regular columnar structure making up a large part of the FPGA. The additional logic blocks can be programmable blocks and/or dedicated logic. For example, the processor block110shown inFIG. 1spans several columns of CLBs and BRAMs.

Note thatFIG. 1is intended to illustrate only an exemplary FPGA architecture. The numbers of logic blocks in a column, the relative widths of the columns, the number and order of columns, the types of logic blocks included in the columns, the relative sizes of the logic blocks, and the interconnect/logic implementations included at the right side ofFIG. 1are purely exemplary. For example, in an actual FPGA more than one adjacent column of CLBs is typically included wherever the CLBs appear, to facilitate the efficient implementation of user logic. FPGA100illustratively represents a columnar architecture, though FPGAs of other architectures, such as ring architectures for example, may be used. FPGA100may be a Virtex-4™ FPGA from Xilinx of San Jose, Calif.

Examples of complex circuit blocks that may be included in an FPGA, in addition to a microprocessor, include for example an Ethernet media access control (“EMAC”) block and a Peripheral Component Interconnect (“PCI”) block, among other known types of blocks. Furthermore, variations of these blocks, for example a PCI Express (“PCIe”) block, may be used. Notably, although these examples are used, other known complex circuits may be embedded as circuit blocks in an integrated circuit. The integrated circuit in which such blocks may be embedded may be an FPGA; however, other known integrated circuits have complex circuit blocks embedded in them, and they too may be used. Sometimes an integrated circuit with one or more embedded blocks is referred to as a “System-on-Chip” (“SoC”). The example of an FPGA is used to describe how a Built-In Self-Test (“BIST”) circuit may be implemented using programmable logic. This programmable logic used to provide the BIST circuit may thereafter be returned to a pool of resources after testing, where such pool of resources may be available to a user. However, it should be appreciated that either or both programmable logic or hardwired logic may be used for implementing the BIST circuit described. In the example of hardwired logic, such BIST circuit may be optioned out, using one-time programmable elements, such as fuses for example, after testing. Furthermore, although an FPGA example is described herein, programmable logic in other types of integrated circuits may be used to provide a BIST circuit as described herein.

FIG. 2Ais a block diagram depicting an exemplary embodiment of an integrated circuit200having a BIST circuit provided in part using delay macro209. In this example embodiment, delay macro209is for an input side of an embedded block210.FIG. 2Bis a block diagram depicting an exemplary embodiment of integrated circuit200having a BIST circuit provided in part using delay macro209for an output side of an embedded block210. Integrated circuit200is described in additional detail with simultaneous reference toFIGS. 2A and 2B.

A clock signal205is provided to stimulus vector generator201, embedded block210, and comparison circuit220. Thus, it should be appreciated that synchronous operation may be responsive to clock signal205. Stimulus vector generator201provides a stimulus vector202, one at a time, to embedded block210. Stimulus vector202may be a number of bits in width. Any one bit203of such bits may be provided to delay macro209inFIG. 2A.

Delay macro209, as indicated inFIG. 2A, receives a bit203of stimulus vector202and delays it prior to returning such bit203D back to stimulus vector202. Thus, embedded block210receives stimulus vector202, but with one bit203D delayed more than all of the other bits of stimulus vector202. Embedded block210may receive stimulus vector202to any type of signal input bus thereof, such as an address, control, or data bus for example. The bit of stimulus vector202selected for additional delay, namely bit203D, may be identified using static timing analysis. Thus, a bit having the most likely impact on frequency of operation from all bits of stimulus vector202may be identified. Alternatively, each bit of stimulus vector202may be tested, for example sequentially, to determine which bit has the most impact on frequency of operation with respect to embedded block210.

With continuing reference toFIG. 2A, embedded block210, responsive to receiving stimulus vector202with one of the bits delayed by delay macro209, provides outcome vector212. Thus, outcome vector212is provided by embedded block210responsive to processing stimulus vector202. Outcome vector212may be provided to a comparison circuit220. Comparison circuit220may be configured to compare outcome vector212with an expected vector214in association with stimulus vector202. In other words, stimulus vector202may be a function verification input vector for verifying function of embedded block210. Outcome vector212of embedded block210, responsive to a function verification input, namely stimulus vector202, has an expected result, namely an expected vector214, with which comparison circuit220may compare outcome vector212. Notably, comparison circuit220may have access to a store of expected vectors214. Thus, stimulus vector generator201may be a function data generator, and comparison circuit220may be used to verify proper operation of embedded block210prior to testing for a maximum frequency of operation, namely prior to insertion of an added delay.

With reference toFIG. 2B, in this example, stimulus vector202is provided from stimulus vector generator201to embedded block210without delaying any bits. In this example, the output side of embedded block210provides outcome vector212responsive to stimulus vector202. A bit203of outcome vector212is provided to delay macro209. This bit203provided to delay macro209is delayed and provided back to outcome vector212for input of outcome vector212with such a delayed bit203D to comparison circuit220. Comparison circuit220may then compare outcome vector212with an expected vector214as described above.

With reference toFIGS. 2A and 2B, outcome of comparison circuit220may be used to indicate the frequency at which an input or output as associated with embedded block210, respectively, fails before other associated inputs or outputs. Thus, the signal passing into or out of an associated input or output pin of an embedded block that fails before other signals of the same signal bus is the frequency limiting signal. Delay macro209is adjustable to determine at what point of added delay to a signal, whether an input signal or an output signal, such signal fails because the expected bit value in an expected vector for that signal is incorrect. Accordingly, the resultant vectors330and331provided from comparison circuit220indicate a maximum frequency of operation. As described with respective reference toFIGS. 2A and 2B, an input side or an output side of embedded block210may be tested to determine when a signal associated with a pin of a bus fails. Accordingly, as there may be multiple stimulus vectors202for an embedded block210, there may be multiple associated expected vectors214for such stimulus vectors202. Thus, it should be appreciated that which pin of a signal bus may be tested may depend upon the particular stimulus vector used. Additionally, it should be appreciated that there may be multiple signal buses for an embedded block210. Accordingly, the pin being tested may change responsive to the signal bus used.

Thus, by providing a test pattern from stimulus vector generator201for a programmed added delay provided via delay macro209, resultant data may be compared with expected results. The test pattern may be provided with increases in clock frequency of clock signal205for the added delay setting until the resultant data does not match the expected results. Moreover, the added delay setting provided by delay macro209may be increased or decreased, and the testing with increasing clock frequency repeated.

To more clearly understand an example of how a BIST circuit as described above may be implemented,FIGS. 3A and 3Bare block diagrams depicting exemplary embodiments of input side BIST circuit300and output side BIST circuit320, respectively. With reference toFIG. 3A, input side BIST circuit300is further described. Notably, input side BIST circuit300is described in terms of an FPGA implementation; however, as indicated above, other types of integrated circuits may be used. In this example, BIST circuit300is used to determine a maximum frequency associated with an input pin of an input bus311of embedded block210. It should be appreciated that as the frequency of a clock signal, such as clock signal205ofFIGS. 2A and 2Bis increased, input or output paths may fail within a reasonable frequency range. Thus, the maximum frequency of operation of embedded block210may be determined by identifying an input that, when delayed, fails before all other inputs of the same signal bus.

In this example, input control logic304, which may be implemented in programmable logic of an FPGA, is used to control a stimulus vector generator201. Stimulus vector generator201may be implemented in programmable logic or memory302, or a combination thereof. For this example, memory302is used. Memory302for an FPGA implementation may be BRAM. However, it should be appreciated that other types of memory may be used. Memory302may be used for storing one or more stimulus vectors202. Responsive to control by input control logic304, which may receive clock signal205ofFIGS. 2A and 2B, a stimulus vector202of bit width [N:0], for N a positive integer greater than 0, is provided to pipeline305. Pipeline305may be implemented using programmable logic. More particularly, pipeline305may include (N+1) flip-flops, which may be formed in whole or in part in programmable logic, in parallel.

FIG. 6is a circuit diagram depicting an exemplary embodiment of a pipeline600. Pipeline600may be used to implement pipeline305ofFIG. 3A. Pipeline600is clocked responsive to clock signal205where a bit from each of the bits0through N of an input vector601is provided to a respective data input port of flip-flops602-0through602-N.

With renewed reference toFIG. 3Aand continuing reference toFIG. 6, one of outputs603-0through603-N of outputs603, namely bit203, is provided to an adjustable delay306, and the remainder of output603is provided directly to an input bus311of an embedded block210. Notably, delay macro209may instantiate a pipeline, such as pipeline305, and an adjustable delay, such as adjustable delay306, in programmable logic.

N bits of pipeline vector307are provided directly from pipeline305to input bus311of embedded block210, and a bit203output from pipeline305is provided to adjustable delay306, which delays such bit prior to providing such bit203D to input bus311of embedded block210. In this particular example, the 0th bit is used; however, it should be appreciated that any of the bits output from pipeline305may be coupled to be delayed by adjustable delay306.

FIG. 7is a block diagram depicting an exemplary embodiment of instantiation of a delay macro700in programmable logic. Delay macro700may be used to implement adjustable delay306ofFIGS. 3A and 3B. A programmable interconnect point (“PIP”)701is used to couple an output of a pipeline, such as pipeline600, to a slice702of a CLB710. A single slice may be used to provide an incremental delay of an output from a pipeline prior to providing such bit to an input bus of an embedded block. Thus, for example, a single slice702may be used to provide such delay.

Another PIP, namely PIP703, may be used to couple the output of slice702to a pin of a bus of an embedded block210. However, in this particular example, it is shown that slices702and704of CLB710, as well as712and714of CLB711, may be serially coupled to one another in two directions to form a delay chain.

Thus, it should be appreciated that delay macro700effectively implements a delay chain, the delay of which is adjustable by reprogramming programmable logic. Notably, although it is shown that one or more CLBs may be programmed to provide such a delay chain, other types of delay chains may be used for delay macro700. For example, a tapped delay line is another form of a delay chain that may be used.

Returning toFIG. 3A, adjustable delay306may thus be programmed to provide an initial delay to bit203D. This initial delay may be increased or decreased by reprogramming adjustable delay306. Thus, a variety of different delay may be added to a bit203output from pipeline305for providing a delayed bit203D to input bus311. Delay macro209ofFIGS. 2A and 2B, which may be delay macro700ofFIG. 7, may be used to insert a delay block, such as adjustable delay306, where the added delay is greater than the delay associated with the slowest sequential path within a design using embedded block210, such that the path with the added delay block becomes what is generally known as the “critical path” of a design. The range of delays may be sufficient to determine a maximum frequency of operation of embedded block210. Responsive to input308, namely output307from pipeline305combined with delay bit203D from adjustable delay306, embedded block210provides an outcome vector212from output bus312.

It should be appreciated that there is a delay associated with adjustable delay306, a delay associated with pipeline305, and a delay associated with embedded block210, which in combination form a time interval360, namely “T_period_A.”FIG. 5Ais a flow diagram depicting an exemplary embodiment of a setup time calculation flow500. Setup time calculation flow500is for an input side of an embedded block, such as embedded block210ofFIG. 3A. With simultaneous reference toFIGS. 3A and 5A, each of those figures is further described. Time interval360, as indicated in block501, includes a clock-to-output time of a flip-flop of pipeline305as associated with providing an output bit203to adjustable delay306. Notably, clock-to-output timing of each of the flip-flops of pipeline305may be equal or at least substantially the same and may be known. Additionally, time interval360includes a delay associated with adjustable delay306. Lastly, time interval360includes a delay associated with a setup time of a circuitry associated with an input pin of input bus311of embedded block210. This input pin is associated with a path under test in embedded block210.

Outcome vector212, which may be an (M+1)-bit wide vector, namely [M:0], for M a positive integer greater than 0, may be provided to an optional pipeline315or may be provided directly to output control logic314. Notably, depending on for example a difference in frequency between an input side and an output side of embedded block210, M may be larger or smaller than N. Additionally, M may be equal to N. Output of optional pipeline315may be provided to output control logic314.

Output control logic314may be coupled to memory322. Memory322for an FPGA implementation may be BRAM. Memory322may include at least one expected vector214as associated with the at least one stimulus vector202. Thus, output control logic314may cause memory322to output an expected vector214responsive to control signal310. Expected vector214, which may be the same bit width as outcome vector212, may be provided to an optional pipeline325or directly provided to output control logic314. Notably, optional pipelines315and325may be instantiated in programmable logic flip-flops. Output of optional pipelines315and325may be respectively provided to output control logic314. Output control logic314may be configured to compare vectors214and212to provide a resultant vector330, which indicates the result of such comparison. In other words, memory322, pipelines315and325, and output control logic314may be part of comparison circuit220ofFIG. 2A, and delay macro209ofFIG. 2Amay instantiate pipelines315and325in programmable logic.

With reference toFIG. 3B,FIG. 3Bplaces adjustable delay306on the output side of embedded block210. As many of the blocks of BIST circuit320ofFIG. 3Bare the same as those of BIST circuit300ofFIG. 3A, the description of such blocks is not repeated for purposes of clarity. Stimulus vector202ofFIG. 3B, which is output from memory302and provided to pipeline305, is one bit less than stimulus vector202ofFIG. 3A. In other words, pipeline vector317is [(N−1):0] bits in width. Accordingly, pipeline305ofFIG. 3Bmay be one register stage less than pipeline305ofFIG. 3A.

Pipeline vector317is provided to input bus311of embedded block210. Pipeline vector317is one bit less than stimulus vector202. In response to pipeline vector317, embedded block210provides outcome vector212. Outcome vector212has a bit203which is provided to adjustable delay306. Notably, adjustable delay306ofFIG. 3Bneed not be the same adjustable delay ofFIG. 3A; however, for purposes of clarity by way of example and not limitation, a same adjustable delay306is used on both input and output sides of embedded block210.

Notably, outcome vector212, when output from embedded block210, is (M+1) bits wide. In this example, M, [M:1], bits of outcome vector212are provided to pipeline415. Memory322, pipelines415and425, and output control logic314may be part of comparison circuit220ofFIG. 2B, and delay macro209ofFIG. 2Bmay instantiate pipelines415and425in programmable logic. A bit203from output bus312of outcome vector212is provided to adjustable delay306for added delay. In this example, the 0th bit is used; however, any one of the (M+1) bits may have delay added to them. This bit203from outcome vector212has delay added to it by adjustable delay306to provide a delay bit203D. Delayed bit203D is added back into outcome vector212, as generally indicated by dashed circle408, and hereafter referred to as “outcome vector408.” Thus, output from output bus312is provided to pipeline415, where one of the bits is delayed by adjustable delay306longer than all the other bits of outcome vector221to provide outcome vector408to pipeline415. As described above, this additional delay may be adjustably increased to determine the maximum frequency of operation on an output side of embedded block310.

A time interval370, namely T_period_A ofFIG. 5B, as associated with embedded block210, adjustable delay306, and pipeline415, may be determined. Referring toFIG. 5B, there is shown a flow diagram depicting an exemplary embodiment of a clock-to-output flow510for an embedded block, such as embedded block210ofFIG. 3B. With simultaneous reference toFIGS. 3B and 5B, those FIGS. are further described.

Time interval370may include a clock-to-output time interval of embedded block210. This clock-to-output time interval is associated with bit signal203as provided from output bus312. Additionally, a delay of adjustable delay306may be included as part of time interval370. Lastly, bit signal203D as provided to pipeline415may have associated therewith a setup time of a flip-flop of pipeline415which may be included in time interval370. Thus, as indicated in block511, time interval370, namely another “T_period_A,” may be defined. Output of pipeline415, which may be (M+1) bits wide, is provided to output control logic314as previously described. Memory322may have stored therein one or more expected vectors214as associated with stimulus vectors202. Responsive to a control signal310from output control logic314, memory322may output an expected vector214to pipeline425. This expected vector214may be output from pipeline425to output control logic314for comparison with the output of pipeline415to provide resultant vector331.

Thus, with reference toFIGS. 3A and 3B, it should be appreciated that delay of adjustable delay306may be set to determine a point at which the frequency of operation of embedded block210, on an input or output side, respectively, is too great. Accordingly, a maximum frequency of operation may be determined for both an input side and an output side responsive to resultant vectors330and331, respectively. Notably, at the point in time that a maximum frequency of operation is determined, the values of time intervals360and370when inverted indicate such maximum frequency of operation.

To mirror a path of a delay chain, such as implemented via delay macro209ofFIGS. 2A and 2B, a reference design may be implemented.FIG. 4is a schematic diagram depicting an exemplary embodiment of a reference design400. An input401is provided to reference design400. Input401is provided along separate parallel paths402and403. Path403is a series of flip-flops, namely in this example flip-flops404and405coupled in series. The output of flip-flop405is provided as an input to an exclusive NOR (“XNOR”) gate410. With reference to path402, input401is provided to an input flip-flop411. The output of input flip-flop411is provided to an input port of adjustable delay306. Notably, adjustable delay306is the same as used in either or both ofFIGS. 3A and 3B. More particularly, adjustable delay306ofFIG. 4may be set to the same delay value used to determine a maximum frequency of operation, on either an input or output side or both, of embedded block210ofFIGS. 2A and 2B. Output of adjustable delay306is provided to output flip-flop412. Output of output flip-flop412is provided as another input to XNOR gate410. Accordingly, setting adjustable delay306to a same delay used to determine a maximum frequency of operation of embedded block210, may be used to determine a maximum frequency of operation of reference design400. Thus, by clocking flip-flops404,405,411, and412responsive to clock signal205, where clock signal205is adjusted in frequency in order to determine when outputs of paths403and402are not equal to one another as indicated by result445output from XNOR gate410. Thus, output445indicates when a maximum frequency of operation for reference design400has been determined.

With renewed reference toFIG. 5Aand continuing reference toFIG. 4, a time interval465may be determined. More particularly, time interval465includes a clock-to-output time of flip-flop411, a delay time interval of adjustable delay306, and a setup time interval of flip-flop412. Notably, for reference design400, clock-to-output timing of flip-flop411and setup time of flip-flop412may be considered known intervals. Furthermore, it should be appreciated that an inverted value of time interval465, namely “T_period_B,” is associated with a maximum frequency of operation of reference design400. This time interval465is indicated in each of blocks502ofFIGS. 5A and 5B.

By subtracting the result obtained in block502from the result obtained in block501ofFIG. 5A(“A-B”), the times of the delay lines, namely the delay associated with adjustable delay306, will cancel out. Furthermore, assuming that all flip-flops in programmable logic have essentially the same clock-to-output timing, as well as setup timing, clock-to-output timing of flip-flops will also cancel out. Thus, the result of subtracting the time interval associated with block502from the time interval associated with block501results in a setup time of a flip-flop being subtracted from a setup time of embedded block210as indicated in block503. Stated another way, as indicated in block504, setup time of an embedded block for an input side, such as embedded block210ofFIG. 3A, may be determined by subtracting the time interval as associated with block501from the time interval as associated with block502and adding to that result a setup time for a flip-flop. As a setup time for a flip-flop is known, once the maximum frequencies of operation are determined for BIST circuit300ofFIG. 3Aand reference design400ofFIG. 4, those frequencies may be subtracted from one another. The result of the subtraction may have added to it a setup time of a flip-flop in order to determine the setup time associated with a target pin of an embedded block, such as an input pin of input bus311of embedded block210ofFIG. 3A.

Likewise, with reference toFIG. 5B, the result of block502may be subtracted from the result of block511as indicated in block513. Again, the delay associated with adjustable delay306in each instance will cancel out. Additionally, in this example, the setup time of the flip-flops will cancel out as well. This leaves the clock-to-output time interval of the embedded block, such as an output side of embedded block210ofFIG. 3B, less the clock-to-output time of a flip-flop. As indicated in block514, this may be rewritten to express that the clock-to-output timing of an embedded block is equal to the value obtained at511subtracted from the value obtained at502, plus the clock-to-output time of a flip-flop. Again, the clock-to-output time of flip-flop is known. Thus, once a maximum frequency of operation of BIST circuit320ofFIG. 3Bis determined, and a maximum frequency of operation of a reference design400is determined, the maximum frequency of the reference design400may be subtracted from the maximum frequency of the BIST circuit320; the clock-to-output timing of a flip-flop may be added to that result to determine the clock-to-output timing of an embedded block output pin, namely a target output pin of output bus312of embedded block210ofFIG. 3B.

FIG. 8is a flow diagram depicting an exemplary embodiment of a testing flow800. At801, a target pin is identified, such as of an input bus or an output bus of an embedded block coupled to a BIST circuit. At802, a delay is added to one bit, as associated with the target pin identified at801, in association with a stimulus vector that is input to the embedded block or output from the embedded block responsive to the stimulus vector. At803a clock signal having a frequency is applied. At804, a test pattern, namely including the stimulus vector, is provided.

The clock frequency operates the embedded block and the BIST circuit being tested using the test pattern. At805, the result of the test pattern run with the clock frequency obtained is compared with an associated expected result that may be stored in the comparison circuit of the BIST circuit. If the expected result and the actual result do not match, then generally a maximum frequency of operation may have been determined. If the expected and actual results match, then at806the clock frequency is increased and testing flow800resumes at803for the identified target pin. Notably, there may be a range of clock frequencies of operation, and thus testing may exhaust this range. Accordingly, delay may be increased, and the range of clock frequencies reused to continue testing. Cycles of testing flow800may be repeated with increasing clock frequencies until that clock frequency is found at which expected and actual results do not match.