TRANSISTOR WITH FRONT-SIDE AND BACK-SIDE CONTACTS AND ROUTING

Described herein are transistors with front-side and back-side routing, and IC devices including such transistors. The transistor includes a channel material having a longitudinal structure and formed in a dielectric material. A source region encloses a first portion of the channel material, a gate electrode encloses a second portion of the channel material, and a drain region encloses a third portion of the channel material. Each of the source region, gate electrode, and drain region have a first face and a second face opposite the first face, the first and second faces co-planar with the faces of the dielectric material. A first contact is coupled to the first face of the source region, and a second contact is coupled to the second face of the source region.

TECHNICAL FIELD

This disclosure relates generally to the field of integrated circuit (IC) structures and devices, and more specifically, to transistors with front-side and back-side contacts and routing incorporated in such IC structures and devices.

BACKGROUND

Conventional transistors have a channel extending between a source region and a drain region, and a gate over the channel to turn the transistor on or off. The source region and drain region are each coupled to a respective contact that applies a voltage to the region. Similarly, the gate is connected to a contact to apply a current to the gate. In some transistors, the contacts are all on the front-side or top of the device. In some transistors, one or both of the source and drain contacts may be moved to the back-side or bottom of the device.

DETAILED DESCRIPTION

Overview

In general, a field-effect transistor (FET), e.g., a metal-oxide-semiconductor (MOS) FET (MOSFET), is a three-terminal device that includes source, drain, and gate terminals and uses electric field to control current flowing through the device. A FET typically includes a channel material, a source region and a drain region provided in the channel material, and a gate stack that includes a gate electrode material, alternatively referred to as a “work function” material, provided over a portion of the channel material between the source and the drain regions, and, optionally, also includes a gate dielectric material between the gate electrode material and the channel material.

Conventional FETs are controlled using a source contact that is coupled to the source region, a gate contact that is coupled to the gate stack, and a drain contact that is coupled to the drain region. Each contact can apply a voltage to the respective region, e.g., the source contact applies a voltage to the source region, and the gate contact applies a voltage to the gate stack. Various arrangements for the source, gate, drain, and contacts have been realized. For example, in some prior transistors, the source and drain regions, and the source and drain contacts, are on the front-side of the device; the gate may be on either the front-side or the back-side. In other arrangements, the source and drain regions and contacts are on the back-side of the device. In still other arrangements, the source region and source contact is on the front-side of the device, while the drain region and drain contact are on the back-side of the device, or vice versa; as is commonly known, source and drain terminals are interchangeable in transistors.

In each of these arrangements, the source and drain regions are formed either on or near the front-side of the channel material, or on or near the back-side of the channel material. Furthermore, each region (source, gate, and drain) has one contact for controlling the voltage on the region. In some applications, it is advantageous to have multiple contacts coupled to some or all of the source, gate, and drain, e.g., so that one or more of the transistor regions can be controlled from both sides of the device, i.e., the back-side and the front-side.

Described herein are transistors with front-side and back-side contacts and corresponding methods and devices. The transistor includes a channel material, e.g., a fin-shaped channel material having a longitudinal structure that extends parallel to an upper face of a support structure, e.g., a substrate. The channel material may be embedded in a dielectric material that has a first face and a second face, each of which are parallel to the support structure. A first source or drain (S/D) region encloses one portion of the channel material. The first S/D region has a first face parallel to the support structure, e.g., along the first face of the dielectric material, and a second face opposite the first face, e.g., along the second face of the dielectric material. A gate electrode encloses a second portion of the channel material, and a second S/D region encloses a third portion of the channel material; the gate electrode is between the first and second S/D regions.

The first S/D region has a first S/D contact coupled to its first face, and a second S/D contact coupled to its second face. The first S/D contact may be a front-side contact, and the second S/D contact a back-side contact, or vice versa (depending on the orientation of the device). In some embodiments, both of the first and second S/D regions have two S/D contacts on opposite sides of the transistor. In some embodiments, the gate electrode has two gate contacts on opposite sides of the transistor. In different embodiments, different regions (source, gate, and drain) may each have one or two contacts. For example, in an IC device with many transistors, different transistors may have different contact arrangements. Furthermore, contacts on either side may be coupled to metal routing (e.g., vias and trenches) to additional devices, including on other layers of a multi-layer IC device. For example, a transistor may be coupled to two capacitors, one on either side of the transistor layer. This allows a single transistor to serve as an access transistor for two different memory cells. More generally, enclosing the channel material with two S/D regions and a gate electrode, the transistor can be accessed from both sides, which permits greater flexibility in routing arrangements and control over the transistors.

In some embodiments, the channel material may be in the form of one or more nanoribbons or nanowires. As used herein, the term “nanoribbon” refers to an elongated semiconductor structure having a long axis parallel to a support structure (e.g., a substrate, a chip, or a wafer) over which a transistor arrangement is provided. In some settings, the term “nanoribbon” has been used to describe an elongated semiconductor structure that has a rectangular transverse cross-section (i.e., a cross-section in a plane perpendicular to the longitudinal axis of the structure), while the term “nanowire” has been used to describe a similar structure but with a circular or square-like transverse cross-section. In the present disclosure, the term “nanoribbon” is used to describe both such nanoribbons (including nanosheets) and nanowires, as well as elongated semiconductor structures with a longitudinal axis parallel to the support structures and with having transverse cross-sections of any geometry (e.g., oval, or a polygon with rounded corners).

The transistors with front-side and back-side contacts described herein may be implemented in one or more components associated with an IC or/and between various such components. In various embodiments, components associated with an IC include, for example, transistors, diodes, power sources, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. Components associated with an IC may include those that are mounted on IC or those connected to an IC. The IC may be either analog or digital and may be used in a number of applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. The IC may be employed as part of a chipset for executing one or more related functions in a computer.

The drawings are intended to show relative arrangements of the elements therein, and the device assemblies of these figures may include other elements that are not specifically illustrated (e.g., various interfacial layers). Similarly, although particular arrangements of materials are discussed with reference to the drawings, intermediate materials may be included in the devices and assemblies of these drawings. Still further, although some elements of the various device views are illustrated in the drawings as being planar rectangles or formed of rectangular solids and although some schematic illustrations of example structures are shown with precise right angles and straight lines, this is simply for ease of illustration, and embodiments of these assemblies may be curved, rounded, or otherwise irregularly shaped as dictated by, and sometimes inevitable due to, the manufacturing processes used to fabricate semiconductor device assemblies. Therefore, it is to be understood that such schematic illustrations may not reflect real-life process limitations which may cause the features to not look so “ideal” when any of the structures described herein are examined using e.g., scanning electron microscopy (SEM) images or transmission electron microscope (TEM) images. In such images of real structures, possible processing defects could also be visible, e.g., not-perfectly straight edges of materials, tapered vias or other openings, inadvertent rounding of corners or variations in thicknesses of different material layers, occasional screw, edge, or combination dislocations within the crystalline region, and/or occasional dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but that are common within the field of device fabrication. Inspection of layout and mask data and reverse engineering of parts of a device to reconstruct the circuit using e.g., optical microscopy, TEM, or SEM, and/or inspection of a cross-section of a device to detect the shape and the location of various device elements described herein using e.g., Physical Failure Analysis (PFA) would allow determination of presence of one or more non-planar transistor arrangements with asymmetric gate enclosures as described herein.

For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term “between,” when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges. The meaning of “a,” “an,” and “the” include plural references. The meaning of “in” includes “in” and “on.”

In the following detailed description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. For example, as used herein, a “logic state” of a ferroelectric memory cell refers to one of a finite number of states that the cell can have, e.g. logic states “1” and “0,” each state represented by a different polarization of the ferroelectric material of the cell. In another example, as used herein, a “READ” and “WRITE” memory access or operations refer to, respectively, determining/sensing a logic state of a memory cell and programming/setting a logic state of a memory cell. In other examples, the term “connected” means a direct electrical or magnetic connection between the things that are connected, without any intermediary devices, while the term “coupled” means either a direct electrical or magnetic connection between the things that are connected or an indirect connection through one or more passive or active intermediary devices. The term “circuit” means one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. In yet another example, a “high-k dielectric” refers to a material having a higher dielectric constant (k) than silicon oxide. The terms “oxide,” “carbide,” “nitride,” etc. refer to compounds containing, respectively, oxygen, carbon, nitrogen, etc.

Fabricating Transistors with Front-Side and Back-Side Contacts

FIG.1is a flow diagram of an example method100for fabricating a transistor with front-side and back-side contacts, according to some embodiments of the present disclosure.FIGS.2-10illustrate various stages in the manufacture of an example IC structure according to the fabrication method100, in accordance with some embodiments.

A number of elements referred to in the description ofFIGS.2-14with reference numerals are illustrated in these figures with different patterns, with a legend showing the correspondence between the reference numerals and patterns being provided at the bottom of each drawing page containingFIGS.2-14. For example, the legend illustrates thatFIGS.2-14use different patterns to show a support structure202, a channel material204, and a dielectric material206. Furthermore, although a certain number of a given element may be illustrated in some ofFIGS.2-14(e.g., two channels around which two transistors are formed), this is simply for ease of illustration, and more, or less, than that number may be included in an IC structure according to various embodiments of the present disclosure. In general, an IC structure will include many more transistors than illustrated here. Still further, various IC structure views shown inFIGS.2-14are intended to show relative arrangements of various elements therein, and that various IC structures, or portions thereof, may include other elements or components that are not illustrated.

Turning toFIG.1, the method100may begin with a process102that includes providing a channel material embedded in a dielectric material.FIG.2illustrates a cross-section of a pair of longitudinal channels204-A and204-B in an example y-x plane of an exemplary reference coordinate system x-y-z utilized inFIGS.2-12. The channels204-A and204-B are referred to jointly as channel material204or simply channels204. During the method100, a first transistor is formed around channel204-A, and a second transistor is formed around channel204-B. The two channels and two transistors are merely exemplary, and many more transistors may be formed along a single channel and/or along additional channels.

The channel material204is embedded in a dielectric material206. The dielectric material206is a support structure for the channel material204. The channel material204has a longitudinal structure, extending in the x-direction in the reference frame ofFIG.2. The dielectric material206extends along the x-y plane, so the channel material204extends in a direction (e.g., the x-direction) that is parallel to the dielectric material206.

The dielectric material206and channels204may be formed over a support structure, e.g., the support structure202shown inFIG.3.FIG.3is one example cross-section ofFIG.2taken through the channel material204(e.g., along the plane shown inFIG.2as a plane AA′).FIG.3shows that the channel material204is shaped as fins302-A and302-B, referred to jointly as fins302. The fins302are enclosed by the dielectric material206, which extends over a support structure202. The fins302extend away from the support structure202in a direction substantially perpendicular to the support structure202, i.e., perpendicular to an upper face309of the support structure202and extending in the z-direction in the exemplary reference coordinate system x-y-z. As noted above, the fins302also extend in the x-direction, e.g., into the page in the orientation ofFIG.3, as illustrated inFIG.2. As noted above,FIG.2is a cross-section of the channels204; for example,FIG.2is a cross-section taken along the plane shown inFIG.3as plane BB′.

FIG.4is a second example cross-section along a plane AA′ of the example arrangement shown inFIG.2.FIG.4shows an alternate configuration of the channel material204in which each channel204includes a respective set of nanoribbons402.FIG.2may be a cross-section taken along the plane shown inFIG.4as plane CC′. In the example ofFIG.4, the first channel204-A includes four stacked nanoribbons402, e.g., nanoribbons402-1-A and402-2-A, referred to jointly as nanoribbons402. The nanoribbons402may take the form of a nanowire or nanoribbon, for example. In some embodiments, an area of a transversal cross-section of the nanoribbons402(i.e., an area in the y-z plane of the example coordinate system x-y-z shown inFIG.4) may be between about 25 and 10000 square nanometers, including all values and ranges therein (e.g., between about 25 and 1000 square nanometers, or between about 25 and 500 square nanometers). In some embodiments, a width of the nanoribbon204(i.e., a dimension measured in a plane parallel to the support structure202and in a direction perpendicular to a long axis of the nanoribbon402, e.g., along the x-axis of the example coordinate system shown inFIG.2) may be at least about 3 times larger than a height of the nanoribbon402(i.e., a dimension measured in a plane perpendicular to the support structure202, e.g., along the z-axis of the example coordinate system shown inFIG.4), including all values and ranges therein, e.g., at least about 4 times larger, or at least about 5 times larger. Although the nanoribbons402illustrated inFIG.4are shown as having a rectangular cross-section, the nanoribbons402may instead have a cross-section that is square, a cross-section that is rounded at corners or otherwise irregularly shaped, etc. While each channel204is shown as including a stack of four nanoribbons402, in other embodiments, each channel204may include fewer (e.g., one, two, or three) nanoribbons402, or a greater number of nanoribbons402. Furthermore, while the nanoribbons402in each channel204are stacked vertically (e.g., nanoribbon402-1-A is stacked over nanoribbon402-2-A), in other embodiments, multiple nanoribbons402comprising a channel204may have a different arrangement.

While the cross-sections inFIGS.5-11depict an example in which each channel204includes the set of nanoribbons402shown inFIG.4, it should be understood that in other embodiments, the channel204may have the fin shape shown inFIG.3.

In the examples shown inFIGS.3and4, the dielectric material206and support structure202are depicted as two different layers. The support structure202has an upper face309, and the dielectric material206has a lower face307over the upper face309of the support structure202. The dielectric material206further has an upper face305opposite the lower face307. In other embodiments, the channels204are formed directly in the support structure202, e.g., in an upper portion of the support structure202.

In some embodiments, the dielectric material206may be an insulator material formed over the support structure202. For example, the dielectric material206may be any suitable interlayer dielectric (ILD) material. In some embodiments, such an insulator material may be a high-k dielectric including elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used for this purpose may include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate. In other embodiments, the dielectric material206may be a low-k dielectric material. Some examples of low-k dielectric materials include, but are not limited to, silicon dioxide, carbon-doped oxide, silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fused silica glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass.

In some embodiments, the channel material204may be composed of semiconductor material systems including, for example, N-type or P-type materials systems. In some embodiments, an IC device may include both N-type and P-type materials, e.g., the channel204-A is a P-type semiconductor, and the channel204-B is a P-type semiconductor. In some embodiments, the channel material204may include a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In some embodiments, the channel material204may include a combination of semiconductor materials where one semiconductor material may be used for the channel portion, and another material, sometimes referred to as a “blocking material,” may be used between the channel portion and the support structure202over which the transistor is provided, e.g., as the dielectric material206or a portion of the dielectric material206. In some embodiments, the channel material204may include a monocrystalline semiconductor, such as silicon (Si) or germanium (Ge). In some embodiments, the channel material204may include a compound semiconductor with a first sub-lattice of at least one element from group III of the periodic table (e.g., Al, Ga, In), and a second sub-lattice of at least one element of group V of the periodic table (e.g., P, As, Sb). In some embodiments, the channel material204is an epitaxial semiconductor material deposited in the dielectric material206using an epitaxial deposition process. The epitaxial semiconductor material may have a polycrystalline structure with a grain size between about 2 nanometers and 100 nanometers, including all values and ranges therein.

For some example N-type transistor embodiments (i.e., for the embodiments where the transistor is an N-type metal-oxide-semiconductor (NMOS)), the channel material204may advantageously include a III-V material having a high electron mobility, such as, but not limited to InGaAs, InP, InSb, and InAs. For some such embodiments, the channel material204may be a ternary III-V alloy, such as InGaAs, GaAsSb, InAsP, or InPSb. For some InxGa1-xAs fin embodiments, In content (x) may be between 0.6 and 0.9, and may advantageously be at least 0.7 (e.g., In0.7Ga0.3As). In some embodiments with highest mobility, the channel material204may be an intrinsic III-V material, i.e., a III-V semiconductor material not intentionally doped with any electrically active impurity. In alternate embodiments, a nominal impurity dopant level may be present within the channel material204, for example to further fine-tune a threshold voltage Vt, or to provide HALO pocket implants, etc. Even for impurity-doped embodiments however, impurity dopant level within the channel material304may be relatively low, for example below 1015dopant atoms per cubic centimeter (cm−3), and advantageously below 1013cm−3.

For some example P-type transistor embodiments (i.e., for the embodiments where the transistor is a P-type metal-oxide-semiconductor (PMOS)), the channel material204may advantageously be a group IV material having a high hole mobility, such as, but not limited to Ge or a Ge-rich SiGe alloy. For some example embodiments, the channel material204may have a Ge content between 0.6 and 0.9, and advantageously may be at least 0.7. In some embodiments with highest mobility, the channel material204may be intrinsic III-V (or IV for P-type devices) material and not intentionally doped with any electrically active impurity. In alternate embodiments, one or more a nominal impurity dopant level may be present within the channel material204, for example to further set a threshold voltage (Vt), or to provide HALO pocket implants, etc. Even for impurity-doped embodiments however, impurity dopant level within the channel portion is relatively low, for example below 1015cm−3, and advantageously below 1013cm−3.

In some embodiments, the channel material204, e.g., the channel material of the nanoribbons402, may be a thin-film material, such as a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In general, if the transistor formed around the nanoribbon is a thin-film transistor (TFT), the channel material204may include one or more of tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, N- or P-type amorphous or polycrystalline silicon, germanium, indium gallium arsenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphite, and black phosphorus, each of which may possibly be doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, and magnesium, etc. In some embodiments, the channel material204may have a thickness between about 5 and 75 nanometers, including all values and ranges therein. In some embodiments, a thin-film channel material may be deposited at relatively low temperatures, which allows depositing the channel material within the thermal budgets imposed on back-end fabrication to avoid damaging other components, e.g., front end components such as the logic devices.

The method100may proceed with a process104that includes etching the dielectric material206around portions of the channel material204. A result of this process is illustrated inFIGS.5A and5B, showing portions502etched in the dielectric material206and around portions of the channels204-A and204-B in the process104.

FIG.5Ais a top view of the IC structure including the channels204-A and204-B with portions502of the dielectric material206along each of the channels204-A and204-B removed. In particular, along each channel204-A and204-B, three portions of the dielectric material206are removed: along channel204-A, portions502-1-A,502-2-A, and502-3-A are removed, and along channel204-B, portions502-1-B,502-2-B, and502-3-B are removed. The outlines of the channels204-A and204-B are shown inFIG.5Afor reference, but the full channels204are not visible from the top view. Instead, the etching process104exposes three portions of each channel204, while the other portions of the channels204remain embedded in and enclosed by the dielectric material206. Each etched portion502of dielectric material206is etched down to the support structure202, exposing the support structure inFIG.5A; in other embodiments, the etching may not extend to the support structure202, or may extend partially into the support structure202.

FIG.5Bshows a cross-section through the etched portions of the dielectric material206, e.g., along each of the AA′, DD′, and EE′ planes inFIG.5A. Note thatFIG.5Bshows a single cross-section; the cross-section through each of the AA′, DD′, and EE′ planes is substantially identical.FIG.5Bshows two etched portions502-A and502-B (e.g., any of the pairs of portions502-1-A and502-1-B,502-2-A and502-2-B, and502-3-A and502-3-B) of dielectric material206around two respective exposed portions of the channel material204. As shown inFIG.5B, the channel material204is exposed on all sides, including the bottom face of the channel material204(i.e., the face nearest to the support structure202). In the nanoribbon example shown inFIG.5B, the dielectric material206between the nanoribbons have also been removed by the process104.

FIG.5Afurther shows a fourth plane, FF′, in a region between the etched portions502-1and502-2.FIG.4, discussed above, shows the cross-section along the plane FF′, with the channel material204surrounded by the dielectric material206along this plane. The cross-section is similar for the region between the etched portions502-2and502-3.FIG.5Aalso shows two distances,510and512, where the distance510represents the distance between the two etched portions502-1and502-2, and the distance512represents the distance between the two etched portions502-2and502-3. Each of the distances510and512may be between about 1 nanometer and 10 nanometers, including all values and ranges therein, e.g., between about 2 nanometers and 5 nanometers. While the distances510and512may typically be the same or approximately the same, in some embodiments, the distance510may be different from the distance512.

The dielectric material206surrounding the non-exposed portions of the channel204(e.g., the portions of dielectric material206between the etched portions502-1and502-2and between the etched portions502-2and502-3) support the exposed portions of the channel204, which are no longer directly surrounded and supported by the portions of dielectric material206that were etched in the process104. While the channels204are depicted as extending further in the x-direction than the first and third portions502-1and502-3, in other examples, the etched portion502-1and/or the etched portion502-3surround around an end of the channel204.

Any suitable processes may be used in the process104to form the etched portions502, e.g., any suitable lithographic process in combination with a suitable etching process. In various embodiments, suitable lithographic processes may include photolithography, electron-beam lithography, etc., possibly in combination with using a mask, e.g., a hardmask. The lithographic processes may be used to define locations and dimensions for the etched portions502. In various embodiments, a suitable etching process is used to remove the portions502of the dielectric material206, e.g., using dry etch, wet etch, reactive ion etch (RIE), ion milling, etc. For example, any suitable anisotropic etch process, e.g., a dry etch, may be used in the process104to etch the dielectric material206through the openings defined by the lithographic process (e.g., openings defined in a photoresist material, not shown inFIG.5) to form the portions502. In some embodiments, during the etch of the dielectric material206in the process104, the IC structure may be heated to elevated temperatures, e.g., to temperatures between about room temperature and 200 degrees Celsius, including all values and ranges therein, to promote that byproducts of the etch are made sufficiently volatile to be removed from the surface.

The method100may proceed with a process106that includes depositing source and drain materials around two exposed portions of each channel204. A result of this process is illustrated inFIGS.6A and6B, showing source and drain regions enclosing two portions of each of the channels. As described above, the source and drain regions of a transistor are interchangeable, and a nomenclature of a first S/D region and a second S/D region of a transistor has been introduced for use in the present disclosure. InFIGS.6A and6B, reference numeral208-1is used to label the first S/D region (e.g., reference numeral208-1-A refers to the first S/D region of the first transistor, and reference numeral208-1-B refers to the first S/D region of the second transistor), and reference numeral208-2is used to label the second S/D region (e.g., reference numeral208-2-A refers to the second S/D region of the first transistor, and reference numeral208-2-B refers to the second S/D region of the second transistor).

As shown inFIG.6A, the first etched portion502-1along each channel204and the third etched portion504-3along each channel204are filled in with a S/D material.FIG.6Bshows a cross-section through the first S/D regions208-1, e.g., along the DD′ plane inFIG.6A, and through the second S/D regions208-2, e.g., along the EE′ plane inFIG.6A; the cross-section through each of the DD′ and EE′ planes is substantially identical. As shown inFIG.6B, the S/D region208encloses the channel material204on all sides, including below the bottom face of the channel material204(i.e., the face nearest to the support structure202). In the nanoribbon example shown inFIG.6B, the S/D region208extends into the areas between the nanoribbons, enclosing each individual nanoribbon. Each S/D region208has a first face that is co-planar with the upper face305of the dielectric material206, and a second face that is co-planar with the lower face307of the dielectric material206.

The S/D regions208may generally be formed using a deposition process. In particular, an epitaxial deposition process may be carried out to fill the etched portions502-1and502-3with material that is used to fabricate the S/D regions208. A conformal deposition process, such as atomic layer deposition (ALD) or chemical vapor deposition (CVD), may be used to deposit the S/D regions208. Conformal deposition generally refers to deposition of a certain coating on any exposed surface of a given structure. A conformal coating may, therefore, be understood as a coating that is applied to exposed surfaces of a given structure, and not, for example, just to the horizontal surfaces. In some implementations, the S/D regions208may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the S/D regions208may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions208.

The method100may proceed with a process108that includes depositing a gate electrode around the other etched portion of each channel204. A result of this process is illustrated inFIGS.7A and7B, showing a gate stack enclosing a portion of each of the channels204-A and204-B. Each gate stack includes a gate dielectric210enclosing a portion of the channel material204, and a gate electrode212enclosing the gate dielectric210. Depositing the S/D regions208and gate electrodes212provides a transistor700formed along a channel204.FIG.7Aincludes two transistors: a first transistor700-A, formed around the first channel204-A, and a second transistor700-B, formed around the second channel204-B. InFIG.7B, reference numeral210-A refers to the gate dielectric of the first transistor700-A, reference numeral210-B refers to the gate dielectric of the second transistor700-B, reference numeral212-A refers to the gate electrode of the first transistor700-A, and reference numeral212-B refers to the gate electrode of the second transistor700-B.

As shown inFIG.7A, the second etched portion502-2along each channel204is filled in with the gate electrode material.FIG.7Bshows an example cross-section through the gate, e.g., along the AA′ plane inFIG.7A. As shown inFIG.7B, the gate electrode212encloses the channel material204on all sides, including below the bottom face of the channel material204(i.e., the face nearest to the support structure202). In the nanoribbon example shown inFIG.7B, the gate dielectric210extends into the areas between the nanoribbons, enclosing the set of nanoribbons, and the gate electrode212encloses the gate dielectric210. Each gate electrode212has a first face that is co-planar with the upper face305of the dielectric material206, and a second face that is co-planar with the lower face307of the dielectric material206. These faces may also be referred to as the first face705and second face707of the transistors; the first face705and second face707of the transistors are co-planar with the upper face305and lower face307of the dielectric material206, respectively.

FIG.7Cshows an alternate cross-section AA′ through the gate. InFIG.7C, the gate dielectric210encloses each individual nanoribbon, but does not encompass the full area between the nanoribbons. For example, the gate dielectric210does not extend into a region710between two of the nanoribbons forming the second channel204-B. InFIG.7C, the gate electrode212encloses each nanoribbon, which has been previously enclosed by the gate dielectric210. The gate electrode212extends into the areas between the gate dielectric210, e.g., the gate electrode212extends into the region710between two of the nanoribbons. Whether the gate dielectric210fully encloses the set of nanoribbons, as shown inFIG.7B, or encloses the individual nanoribbons while leaving a gap between the nanoribbons, as shown inFIG.7C, depends on the thickness of the gate dielectric210and the distance between the nanoribbons.

Each gate may generally be formed using a deposition process that includes depositing the gate dielectric210and then depositing the gate electrode212. For example, a conformal deposition process, such as ALD or CVD, may be used to deposit the gate dielectric210and/or gate electrode212.

In some embodiments, the gate dielectric210may include one or more high-k dielectrics. Examples of high-k materials that may be used in the gate dielectric210may include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric210during manufacture of the transistor to improve the quality of the gate dielectric210.

The gate electrode212may include at least one P-type work function metal or N-type work function metal, depending on whether the transistor is a PMOS transistor or an NMOS transistor (P-type work function metal used as the gate electrode212when the transistor is a PMOS transistor and N-type work function metal used as the gate electrode212when the transistor is an NMOS transistor). As noted above, a single device may include one or more NMOS transistors and one or more PMOS transistors, e.g., the first transistor700-A is an NMOS transistor, and the second transistor700-B is a PMOS transistor. For a PMOS transistor, metals that may be used for the gate electrode212may include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide). For an NMOS transistor, metals that may be used for the gate electrode212include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). In some embodiments, the gate electrode212may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further layers may be included next to the gate electrode212for other purposes, such as to act as a diffusion barrier layer or/and an adhesion layer.

While the method100andFIGS.6and7show the S/D regions208being deposited before the gate dielectric210and gate electrode212, these processes may be completed in any order, e.g., the gate dielectric210and gate electrode212may be deposited before the S/D regions208, or the S/D region208may be deposited after the gate dielectric210and before the gate electrode212.

The method100may proceed with a process110that includes depositing front-side contacts coupled to the S/D regions and gate of a transistor700. A result of this process is illustrated inFIGS.8A-8C, showing a top view and cross-section views of source, gate, and drain contacts on a front-side of the pair of transistors700-A and700-B.

InFIGS.8A-8C, reference numeral214-1is used to label the first front-side S/D contact (e.g., reference numeral214-1-A refers to the first front-side S/D contact of the first transistor, and reference numeral214-1-B refers to the first front-side S/D contact of the second transistor), reference numeral214-2is used to label the front-side gate contact (e.g., reference numeral214-2-A refers to the front-side gate contact of the first transistor, and reference numeral214-2-B refers to the front-side gate contact of the second transistor), and reference numeral214-3is used to label the second front-side S/D contact (e.g., reference numeral214-3-A refers to the second front-side S/D contact of the first transistor, and reference numeral214-3-B refers to the second front-side S/D contact of the second transistor). The first front-side S/D contact214-1, front-side gate contact214-2, and second front-side S/D contact214-3are jointly referred to as front-side contacts214.

As shown inFIG.8A, the front-side contacts214are formed over the S/D regions208and gate electrodes212on the first face705of the transistors.FIG.8Bshows a cross-section through the gate electrodes212, e.g., along the AA′ plane inFIG.8A.FIG.8Cshows a cross-section through the first S/D regions208-1, e.g., along the DD′ plane inFIG.8A, and through the second S/D regions208-2, e.g., along the EE′ plane inFIG.8A; the cross-section through each of the DD′ and EE′ planes is substantially identical. The front-side contacts214extend in a direction perpendicular to the first face705of the transistors, e.g., in the direction of the z-axis shown inFIGS.8B and8C. As shown inFIGS.8B and8C, the front-side contacts214may decrease in width moving downward along the z-axis and approaching the first face705of the transistors700. The front-side contacts214are substantially trapezoidal, as seen inFIGS.8B and8C, with the width of the tops of the front-side contacts214(i.e., farther away from the S/D regions208) being larger than the width of the bottoms of the front-side contacts214(i.e., closer to the S/D regions208), where both of these widths are measured along the y-axis of the example coordinate system shown.

The front-side contacts214are formed of one or more electrically conductive materials for providing electrical connectivity to the S/D regions208and gate electrodes212. In various embodiments, one or more layers of metal and/or metal alloys may be used to form the front-side contacts214. For example, the electrically conductive materials of the front-side contacts214may include one or more metals or metal alloys, with materials such as copper, ruthenium, palladium, platinum, cobalt, nickel, hafnium, zirconium, titanium, tantalum, and aluminum, tantalum nitride, tungsten, doped silicon, doped germanium, or alloys and mixtures of any of these. In some embodiments, the front-side contacts214may include one or more electrically conductive alloys, oxides, or carbides of one or more metals. In some embodiments, the front-side contacts214may include a doped semiconductor, such as silicon or another semiconductor doped with an N-type dopant or a P-type dopant. Metals may provide higher conductivity, while doped semiconductors may be easier to pattern during fabrication. AlthoughFIGS.8A-8Cillustrate the front-side S/D contacts214-1and214-3and front-side gate contacts214-2with a single pattern, suggesting that the material composition of the front-side contacts214-1,214-2, and214-3are the same, this may not be the case in some other embodiments. For example, in some embodiments, the material composition of the front-side S/D contacts214-1and214-3may be different from the material composition of the front-side gate contacts214-2.

In some embodiments, the method100may proceed with a process112that includes processing additional front-side layers. One or more additional layers may be processed over the front-side of the IC device having the transistors700. For example, one or more interconnect layers, memory layers, device layers, etc. may be fabricated on the front-side of the IC device. Two examples of IC devices with a layer of transistors700and additional front-side layers are shown inFIGS.13and14.

The method100may proceed with a process114that includes flipping the IC device and grinding the support structure202. This process is illustrated inFIG.9A, which shows a cross-section view of the IC device being flipped, andFIG.9B, which shows the result of grinding the support structure202.

After the front-side contacts214are formed on the front-side of the transistors, the front-side of the IC device is flipped and attached to a carrier structure902, e.g., a second support structure, as illustrated inFIG.9A. The relative positions of the first face705and second face707are flipped, with the second face707above the first face705in the second illustration ofFIG.9A. The carrier structure902may be similar to any of the support structures202described above. In some embodiments, the carrier structure902may be formed from one or more semiconductor materials, while in other embodiments, the carrier structure902may be formed from one or more insulator materials, e.g., any of the dielectric materials described with respect to the dielectric material206. While the carrier structure902and support structure202are illustrated with the same pattern, the carrier structure902may have a different material composition from the support structure202. The IC device may be flipped over and pressed onto the carrier structure902, with suitable pressure and/or heat to adhere the carrier structure902to the IC device (e.g., to the front-side contacts214as shown inFIG.9A, or the front-side of another layer processed over the transistors700and front-side contacts214). A bonding material may be used to attach the IC device to the carrier structure902. In some embodiments, if the additional layers fabricated in process112provide sufficient mechanical support for the IC device, a carrier structure902may not be used.

After the IC device is flipped, the support structure202on the back-side may be grinded to reveal the back-sides of the transistors700, i.e., the second face707. In the example shown inFIG.9B, the support structure202is completely removed, i.e., to a thickness of 0 nanometers. In other embodiments, a portion of the support structure202remains, e.g., the support structure202is grinded to a thickness less than about 5 microns, including any range therein, e.g., between 1 nanometers and 50 nanometers. An example in which a portion of the support structure202remains after grinding is shown inFIG.11. Grinding the support structure202to reveal the transistors700may be performed using any suitable thinning/polishing processes as known in the art.

The method100may proceed with a process116that includes depositing back-side contacts coupled to the S/D regions and gate of a transistor700. A result of this process is illustrated inFIGS.10A-10C, showing a top view and cross-section views of source, gate, and drain contacts on a back-side of the pair of transistors700-A and700-B. Note thatFIG.10Ashows the top-side view of the flipped IC device. The relative locations of transistor700-A and700-B are flipped relative to their locations inFIGS.8A-8C(e.g., transistor700-A is on the right side inFIG.10A, and transistor700-B is on the left side inFIG.10B) after the IC device was flipped, as shown inFIG.9A.

InFIGS.10A-10C, reference numeral216-1is used to label the first back-side S/D contact (e.g., reference numeral216-1-A refers to the first back-side S/D contact of the first transistor, and reference numeral216-1-B refers to the first back-side S/D contact of the second transistor), reference numeral216-2is used to label the back-side gate contact (e.g., reference numeral216-2-A refers to the back-side gate contact of the first transistor, and reference numeral216-2-B refers to the back-side gate contact of the second transistor), and reference numeral216-3is used to label the second back-side S/D contact (e.g., reference numeral216-3-A refers to the second back-side S/D contact of the first transistor, and reference numeral216-3-B refers to the second back-side S/D contact of the second transistor). The first back-side S/D contact216-1, back-side gate contact216-2, and second back-side S/D contact216-3are jointly referred to as back-side contacts216.

As shown inFIG.10A, the back-side contacts216are formed over the S/D regions208and gate electrodes212on the second face707of the transistors.FIG.10Bshows a cross-section through the gate electrodes212, e.g., along the AA′ plane inFIG.10A.FIG.10Cshows a cross-section through the first S/D regions208-1, e.g., along the DD′ plane inFIG.10A, and through the second S/D regions208-2, e.g., along the EE′ plane inFIG.10A; the cross-section through each of the DD′ and EE′ planes is substantially identical. The front-side contacts216extend in a direction perpendicular to the second face707of the transistors, e.g., in the direction of the z-axis shown inFIGS.10B and10C. As shown inFIGS.10B and10C, the back-side contacts216may decrease in width moving downward along the z-axis and approaching the second face707of the transistors700. The back-side contacts216are substantially trapezoidal, as seen inFIGS.10B and10C, with the width of the tops of the back-side contacts216(i.e., farther away from the S/D regions208) being larger than the width of the bottoms of the back-side contacts216(i.e., closer to the S/D regions208), where both of these widths are measured along the y-axis of the example coordinate system shown. The front-side contacts214and back-side contacts216both decrease in width moving towards the transistors700-A and700-B. For example, in the flipped orientation shown inFIG.10B, the front-side contact214-2-B decreases in width moving upwards along the z-axis and towards the first face705, and the back-side contact216-2-B increases in width moving upwards along the z-axis and away from the second face707.

The back-side contacts216are formed of one or more electrically conductive materials for providing electrical connectivity to the S/D regions208and gate electrodes212, such as any of the materials described with respect to the front-side contacts214. AlthoughFIGS.10A-10Cillustrate the back-side S/D contacts216-1and216-3and back-side gate contacts216-2with a single pattern, suggesting that the material composition of the back-side contacts216-1,216-2, and216-3are the same, this may not be the case in some other embodiments. Furthermore, althoughFIGS.10A-10Cillustrate the back-side contacts216and front-side contacts214with different patterns, suggesting that the material composition of the back-side contacts216and front-side contacts214are different, in some embodiments, the back-side contacts216and front-side contacts214may comprise the same material.

While each transistor700-A and700-B is illustrated as having three front-side contacts and three back-side contacts, in other embodiments, a given transistor700may have a subset of these contacts, e.g., a transistor700may have only back-side contacts or only front-side contacts, or a transistor may not have a full set of front-side and/or back-side contacts. For example, a transistor700may have front-side and back-side S/D contacts, but only a front-side gate contact. Any combination of contacts on the front-side and back-side may be used. In an IC device with many transistors700, different transistors may have different sets of contacts, e.g., some transistors have both front-side contacts and back-side contacts, and other transistors have only front-side contacts.

The arrangement shown inFIGS.10A-10C(and other figures of the present disclosure) is intended to show relative arrangements of some of the components therein, and in particular, the arrangements of the transistors700and the front-side and back-side contacts. An IC device including one or more of the transistors700may include other components that are not illustrated. For example, a dielectric spacer may be provided between one or both of the S/D contacts and the gate contacts in order to provide additional electrical isolation between the source, gate, drain contacts.

In some embodiments, the method100may proceed with a process118that includes processing additional back-side layers. One or more additional layers may be processed over the back-side of the IC device having the transistors700. For example, one or more interconnect layers, memory layers, device layers, etc. may be fabricated on the back-side of the IC device. Two examples of IC devices with a layer of transistors700and additional front-side and back-side layers are shown inFIGS.13and14.

FIG.11illustrates a cross-section view of gate contacts formed in a support structure on the back-side of the transistor, according to some embodiments of the present disclosure. As noted above in relation toFIG.9B, in some embodiments, a portion of the support structure202remains after the grinding process. In this example, the back-side contacts216are deposited through the remaining support structure202. For example, portions of the support structure202are etched away, and the back-side contacts216are deposited in the etched portions.

FIG.12illustrates an example back-side contact layout for two neighboring transistors, according to some embodiments of the present disclosure. WhileFIGS.10A-10Cshow each S/D region208and each gate electrode212of the transistors700-A and700-B having an individuated back-side contact216, in some embodiments, a back-side contact216may span across two or more transistors. In the example shown inFIG.12, the first S/D contact spans the first S/D regions of the neighboring transistors700-A and700-B, and the gate contact spans the gate electrodes of the neighboring transistors700-A and700-B, while each of the transistors700-A and700-B has a respective individuated second S/D contact. One or more front-side contacts214may span across two or more neighboring transistors in a similar manner.

Example IC Devices Having Transistors with Front-Side and Back-Side Contacts

As described above with respect to processes112and118, in some embodiments, one or more additional front-side layers and/or back-side layers are processed over the front-sides and/or back-sides of the transistors700.FIG.13is a cross-section of an example IC device having transistors with front-side and back-side contacts and routing, according to some embodiments of the present disclosure. In this example, a transistor layer1300includes an array of the transistors700formed in the dielectric material206. The transistors700are formed as described with respect toFIGS.2-7. A single pattern is shown to represent the cross-section of the transistors700, but it should be understood that the transistors700may have the cross-sections shown inFIG.3or4,6, and7at various points along their length. Front-side contacts214and back-side contacts216are formed on either side of the transistor layer1300, as described with respect toFIGS.8-10.

On either side of the transistor layer1300and the contacts214and216are additional layers processed over the front-side and back-side layers. For example, one or more interconnect layers1310and a memory layer1320are processed over the front-side contacts214. These layers1310and1320may be formed after the front-side contacts214are formed in process110and before the support structure is flipped and grinded to reveal the back-side of the transistor layer1300in process114. The interconnect layer1310provides routing of electrical signals to additional devices on or connected to the front-side of the transistor layer1300. For example, a first portion of the interconnect layer1310couples one of the transistors700ato a first capacitor1302aformed in the memory layer1320, and a second portion of the interconnect layer1310couples a second one of the transistors700bto a second capacitor1302bformed in the memory layer1320.

In general, a memory cell may include a capacitor for storing a bit value, or a memory state (e.g., logical “1” or “0”) of the cell, and an access transistor controlling access to the cell (e.g., access to write information to the cell or access to read information from the cell). Such a memory cell may be referred to as a “1T-1C memory cell,” highlighting the fact that it uses one transistor (i.e., “1T” in the term “1T-1C memory cell”) and one capacitor (i.e., “1C” in the term “1T-1C memory cell”). The capacitor of a 1T-1C memory cell may be coupled to one S/D region of the access transistor (e.g., to the first S/D region208-1of the transistor700), while the other S/D region (e.g., the second S/D region208-2of the transistor700) of the access transistor may be coupled to a bit-line (BL), and a gate terminal of the access transistor may be coupled to a word-line (WL). The other electrode of the capacitor is coupled to a plate-line (PL). The WL, BL, and PL are used together to read and program the capacitor.

In the example shown inFIG.13, the transistor700ais an access transistor for the capacitor1302a, and the transistor700bis an access transistor for the capacitor1302b. Additional layers, such as one or more interconnect layers1340and a memory layer1350, are processed over the back-side contacts216. The interconnect layer1340provides routing of electrical signals to additional devices on or connected to the back-side of the transistor layer1300. For example, the illustrated portion of the interconnect layer1340couples the transistor700ato a third capacitor1302cformed in the memory layer1350. In this example, the transistor700aserves as an access transistor to a capacitor1302ain the front-side memory layer1320and a capacitor1302cin the back-side memory layer1350.

In this example, the IC device includes front-side bond pads1360formed on the memory layer1320and back-side bond pads1370formed on the back-side memory layer1350. The bond pads1360and1370may be electrically coupled with the memory layers1320and1350and configured to route electrical signals to other external devices. In some embodiments, the bond pads1360and1370may be coupled to one or more additional layers formed over the memory layers1320and1350, e.g., to an additional interconnect layer not shown inFIG.13. Solder bonds may be formed on the bond pads1360and1370to mechanically and/or electrically couple the IC device with another component (e.g., a circuit board).

FIG.14is a cross-section of a second example IC device having transistors with front-side and back-side contacts and routing, according to some embodiments of the present disclosure.FIG.14shows a similar arrangement toFIG.13, with a transistor layer1300coupled to front-side and back-side interconnect layers and devices. In the example shown inFIG.14, a portion of the support structure202remains, and the back-side contacts216are formed through the support structure202, as described with respect toFIG.11.

Example Devices

The transistors with front-side and back-side contacts disclosed herein may be included in any suitable electronic device.FIGS.15-18illustrate various examples of apparatuses that may include one or more of the transistors with front-side and back-side contacts disclosed herein.

FIGS.15A and15Bare top views of a wafer and dies that include one or more IC structures with one or more transistors with front-side and back-side contacts in accordance with any of the embodiments disclosed herein. The wafer1500may be composed of semiconductor material and may include one or more dies1502having IC structures formed on a surface of the wafer1500. Each of the dies1502may be a repeating unit of a semiconductor product that includes any suitable IC structure (e.g., the IC structures as shown in any ofFIGS.2-14, or any further embodiments of the IC structures described herein). After the fabrication of the semiconductor product is complete (e.g., after manufacture of one or more IC structures with one or more transistors with front-side and back-side contacts as described herein, included in a particular electronic component, e.g., in a transistor or in a memory device), the wafer1500may undergo a singulation process in which each of the dies1502is separated from one another to provide discrete “chips” of the semiconductor product. In particular, devices that include one or more IC structures with one or more transistors with front-side and back-side contacts as disclosed herein may take the form of the wafer1500(e.g., not singulated) or the form of the die1502(e.g., singulated). The die1502may include one or more transistors (e.g., one or more of the transistors1640ofFIG.16, discussed below) and/or supporting circuitry to route electrical signals to the transistors, as well as any other IC components (e.g., one or more IC structures with one or more transistors with front-side and back-side contacts). In some embodiments, the wafer1500or the die1502may include a memory device (e.g., a static random-access-memory (SRAM) device), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die1502. For example, a memory array formed by multiple memory devices may be formed on a same die1502as a processing device (e.g., the processing device1802ofFIG.18) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

FIG.16is a cross-sectional side view of an IC device1600that may include one or more IC structures with one or more transistors with front-side and back-side contacts in accordance with any of the embodiments disclosed herein. The IC device1600may be formed on a substrate1602(e.g., the wafer1500ofFIG.15A) and may be included in a die (e.g., the die1502ofFIG.15B). The substrate1602may be any substrate as described herein. The substrate1602may be part of a singulated die (e.g., the dies1502ofFIG.15B) or a wafer (e.g., the wafer1500ofFIG.15A).

The IC device1600may include one or more device layers1604disposed on the substrate1602. The device layer1604may include features of one or more transistors1640(e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)) formed on the substrate1602. The device layer1604may include, for example, one or more source and/or drain (S/D) regions1620, a gate1622to control current flow in the transistors1640between the S/D regions1620, and one or more S/D contacts1624to route electrical signals to/from the S/D regions1620. The transistors1640may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors1640are not limited to the type and configuration depicted inFIG.16and may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include FinFET transistors, such as double-gate transistors or tri-gate transistors, and wrap-around or all-around gate transistors, such as nanoribbon and nanowire transistors.

Each transistor1640may include a gate1622formed of at least two layers, a gate electrode layer and a gate dielectric layer.

The gate electrode layer may be formed on the gate interconnect support layer and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor, respectively. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer or/and an adhesion layer.

In some embodiments, when viewed as a cross-section of the transistor1640along the source-channel-drain direction, the gate electrode may be formed as a U-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In other embodiments, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In other embodiments, the gate electrode may be implemented as a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may be implemented as one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers. In some embodiments, the gate electrode may consist of a V-shaped structure (e.g., when a fin of a FinFET transistor does not have a “flat” upper surface, but instead has a rounded peak).

Although not specifically shown inFIG.16, the IC device1600may include one or more transistors with front-side and back-side contacts at any suitable location in the IC device1600.

The S/D regions1620may be formed within the substrate1602adjacent to the gate1622of each transistor1640, using any suitable processes known in the art. For example, the S/D regions1620may be formed using either an implantation/diffusion process or a deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate1602to form the S/D regions1620. An annealing process that activates the dopants and causes them to diffuse farther into the substrate1602may follow the ion implantation process. In the latter process, an epitaxial deposition process may provide material that is used to fabricate the S/D regions1620. In some implementations, the S/D regions1620may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D regions1620may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions1620. In some embodiments, an etch process may be performed before the epitaxial deposition to create recesses in the substrate1602in which the material for the S/D regions1620is deposited.

Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the transistors1640of the device layer1604through one or more interconnect layers disposed on the device layer1604(illustrated inFIG.16as interconnect layers1606-1610). For example, electrically conductive features of the device layer1604(e.g., the gate1622and the S/D contacts1624) may be electrically coupled with the interconnect structures1628of the interconnect layers1606-1610. The one or more interconnect layers1606-1610may form an ILD stack1619of the IC device1600.

The interconnect structures1628may be arranged within the interconnect layers1606-1610to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures1628depicted inFIG.16). Although a particular number of interconnect layers1606-1610is depicted inFIG.16, embodiments of the present disclosure include IC devices having more or fewer interconnect layers than depicted.

In some embodiments, the interconnect structures1628may include trench contact structures1628a(sometimes referred to as “lines”) and/or via structures1628b(sometimes referred to as “holes”) filled with an electrically conductive material such as a metal. The trench contact structures1628amay be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the substrate1602upon which the device layer1604is formed. For example, the trench contact structures1628amay route electrical signals in a direction in and out of the page from the perspective ofFIG.16. The via structures1628bmay be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the substrate1602upon which the device layer1604is formed. In some embodiments, the via structures1628bmay electrically couple trench contact structures1628aof different interconnect layers1606-1610together.

The interconnect layers1606-1610may include a dielectric material1626disposed between the interconnect structures1628, as shown inFIG.16. The dielectric material1626may take the form of any of the embodiments of the dielectric material provided between the interconnects of the IC structures disclosed herein.

In some embodiments, the dielectric material1626disposed between the interconnect structures1628in different ones of the interconnect layers1606-1610may have different compositions. In other embodiments, the composition of the dielectric material1626between different interconnect layers1606-1610may be the same.

A first interconnect layer1606(referred to as Metal 1 or “M1”) may be formed directly on the device layer1604. In some embodiments, the first interconnect layer1606may include trench contact structures1628aand/or via structures1628b, as shown. The trench contact structures1628aof the first interconnect layer1606may be coupled with contacts (e.g., the S/D contacts1624) of the device layer1604.

A second interconnect layer1608(referred to as Metal 2 or “M2”) may be formed directly on the first interconnect layer1606. In some embodiments, the second interconnect layer1608may include via structures1628bto couple the trench contact structures1628aof the second interconnect layer1608with the trench contact structures1628aof the first interconnect layer1606. Although the trench contact structures1628aand the via structures1628bare structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer1608) for the sake of clarity, the trench contact structures1628aand the via structures1628bmay be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments.

A third interconnect layer1610(referred to as Metal 3 or “M3”) (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer1608according to similar techniques and configurations described in connection with the second interconnect layer1608or the first interconnect layer1606.

The IC device1600may include a solder resist material1634(e.g., polyimide or similar material) and one or more bond pads1636formed on the interconnect layers1606-1610. The bond pads1636may be electrically coupled with the interconnect structures1628and configured to route the electrical signals of the transistor(s)1640to other external devices. For example, solder bonds may be formed on the one or more bond pads1636to mechanically and/or electrically couple a chip including the IC device1600with another component (e.g., a circuit board). The IC device1600may have other alternative configurations to route the electrical signals from the interconnect layers1606-1610than depicted in other embodiments. For example, the bond pads1636may be replaced by or may further include other analogous features (e.g., posts) that route the electrical signals to external components.

FIG.17is a cross-sectional side view of an IC device assembly1700that may include components having or being associated with (e.g., being electrically connected by means of) one or more IC structures with transistors with front-side and back-side contacts in accordance with any of the embodiments disclosed herein. The IC device assembly1700includes a number of components disposed on a circuit board1702(which may be, e.g., a motherboard). The IC device assembly1700includes components disposed on a first face1740of the circuit board1702and an opposing second face1742of the circuit board1702; generally, components may be disposed on one or both faces1740and1742. In particular, any suitable ones of the components of the IC device assembly1700may include any of the transistors with front-side and back-side contacts, disclosed herein.

The IC device assembly1700illustrated inFIG.17includes a package-on-interposer structure1736coupled to the first face1740of the circuit board1702by coupling components1716. The coupling components1716may electrically and mechanically couple the package-on-interposer structure1736to the circuit board1702and may include solder balls (as shown inFIG.17), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

The package-on-interposer structure1736may include an IC package1720coupled to an interposer1704by coupling components1718. The coupling components1718may take any suitable form for the application, such as the forms discussed above with reference to the coupling components1716. Although a single IC package1720is shown inFIG.17, multiple IC packages may be coupled to the interposer1704; indeed, additional interposers may be coupled to the interposer1704. The interposer1704may provide an intervening substrate used to bridge the circuit board1702and the IC package1720. The IC package1720may be or include, for example, a die (the die1502ofFIG.15B), an IC device (e.g., the IC device1600ofFIG.16), or any other suitable component. In some embodiments, the IC package1720may include one or more transistors with front-side and back-side contacts, as described herein. Generally, the interposer1704may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer1704may couple the IC package1720(e.g., a die) to a ball grid array (BGA) of the coupling components1716for coupling to the circuit board1702. In the embodiment illustrated inFIG.17, the IC package1720and the circuit board1702are attached to opposing sides of the interposer1704; in other embodiments, the IC package1720and the circuit board1702may be attached to a same side of the interposer1704. In some embodiments, three or more components may be interconnected by way of the interposer1704.

The IC device assembly1700may include an IC package1724coupled to the first face1740of the circuit board1702by coupling components1722. The coupling components1722may take the form of any of the embodiments discussed above with reference to the coupling components1716, and the IC package1724may take the form of any of the embodiments discussed above with reference to the IC package1720.

The IC device assembly1700illustrated inFIG.17includes a package-on-package structure1734coupled to the second face1742of the circuit board1702by coupling components1728. The package-on-package structure1734may include an IC package1726and an IC package1732coupled together by coupling components1730such that the IC package1726is disposed between the circuit board1702and the IC package1732. The coupling components1728and1730may take the form of any of the embodiments of the coupling components1716discussed above, and the IC packages1726and1732may take the form of any of the embodiments of the IC package1720discussed above. The package-on-package structure1734may be configured in accordance with any of the package-on-package structures known in the art.

FIG.18is a block diagram of an example computing device1800that may include one or more components including one or more IC structures with one or more transistors with front-side and back-side contacts in accordance with any of the embodiments disclosed herein. For example, any suitable ones of the components of the computing device1800may include a die (e.g., the die1502ofFIG.15B) having one or more transistors with front-side and back-side contacts as described herein. Any one or more of the components of the computing device1800may include, or be included in, an IC device1600(FIG.16). Any one or more of the components of the computing device1800may include, or be included in, an IC device assembly1700(FIG.17).

A number of components are illustrated inFIG.18as included in the computing device1800, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the computing device1800may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die.

Additionally, in various embodiments, the computing device1800may not include one or more of the components illustrated inFIG.18, but the computing device1800may include interface circuitry for coupling to the one or more components. For example, the computing device1800may not include a display device1806, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device1806may be coupled. In another set of examples, the computing device1800may not include an audio input device1824or an audio output device1808but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device1824or audio output device1808may be coupled.

The computing device1800may include battery/power circuitry1814. The battery/power circuitry1814may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the computing device1800to an energy source separate from the computing device1800(e.g., AC line power).

The computing device1800may include a display device1806(or corresponding interface circuitry, as discussed above). The display device1806may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.

The computing device1800may include an audio output device1808(or corresponding interface circuitry, as discussed above). The audio output device1808may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.

The computing device1800may include an audio input device1824(or corresponding interface circuitry, as discussed above). The audio input device1824may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).

The computing device1800may include a GPS device1818(or corresponding interface circuitry, as discussed above). The GPS device1818may be in communication with a satellite-based system and may receive a location of the computing device1800, as known in the art.

The computing device1800may include an other output device1810(or corresponding interface circuitry, as discussed above). Examples of the other output device1810may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

SELECT EXAMPLES

Example 1 provides an IC device that includes a support structure; a channel material having a longitudinal structure; a first S/D region enclosing a first portion of the channel material, the first S/D region having a first face parallel to the support structure and a second face opposite the first face; a gate electrode enclosing a second portion of the channel material; a second S/D region enclosing a third portion of the channel material, the second portion between the first portion and the third portion; a first S/D contact coupled to the first S/D region on the first face; and a second S/D contact coupled to the first S/D region on the second face.

Example 2 provides the IC device according to example 1, where the channel material is a fin, the fin extending in a direction perpendicular to the support structure.

Example 3 provides the IC device according to example 1, where the channel material includes at least one nanoribbon where, in general, the term “nanoribbon” refers to an elongated semiconductor structure such as a nanoribbon or a nanowire, having a long axis parallel to the support structure.

Example 4 provides the IC device according to any of the preceding examples, where the support structure is a dielectric material, and the channel material is disposed within the dielectric material.

Example 5 provides the IC device according to example 4, where the support structure encloses a fourth portion of the channel material, the fourth portion between the first portion and the second portion, and the support structure further encloses a fifth portion of the channel material, the fifth portion between the second portion and the third portion.

Example 6 provides the IC device according to any of the preceding examples, where a distance between the first S/D and the gate is between about 1 nanometer and 10 nanometers including all values and ranges therein, e.g., between about 2 nanometers and 5 nanometers.

Example 7 provides the IC device according to any of the preceding examples, where the channel material is in a layer over the support structure, and the second S/D contact extends through the support structure to the first S/D region.

Example 8 provides the IC device according to any of the preceding examples, the IC device further including a third S/D contact coupled to a first face of the second S/D region and a fourth S/D contact coupled to a second face of the second S/D region.

Example 9 provides the IC device according to any of the preceding examples, the IC device further including a first gate contact coupled to a first face of the gate electrode and a second gate contact coupled to a second face of the gate electrode.

Example 10 provides the IC device according to any of the preceding examples, where the first S/D contact extends in a direction perpendicular to the first face, a first portion of the first S/D contact farther from the first face being wider than a second portion of the first S/D contact nearer to the first face, and the second S/D contact extends in a direction perpendicular to the second face, a first portion of the second S/D contact farther from the second face being wider than a second portion of the second S/D contact nearer to the second face.

Example 11 provides the IC device according to any of the preceding examples, the IC device further including a gate dielectric enclosing the second portion of the channel material, the gate dielectric disposed between the second portion of the channel material and the gate electrode.

Example 12 provides transistor arrangement that includes a structure of a channel material; a first S/D region enclosing a first portion of the structure, the first S/D region having a top face and a bottom face; a gate electrode enclosing a second portion of the structure, the gate electrode having a top face and a bottom face; and a second S/D region enclosing a third portion of the structure, the second S/D region having a top face and a bottom face, where the top faces of the first S/D region, the gate electrode, and the second S/D region are within a first plane, and the bottom faces of the first S/D region, the gate electrode, and the second S/D region are within a second plane.

Example 13 provides the transistor arrangement according to example 12, further including a first S/D contact coupled to the top face of the first S/D region and a second S/D contact coupled to the bottom face of the first S/D region.

Example 14 provides the transistor arrangement according to example 13, further including a third S/D contact coupled to the top face of the second S/D region and a fourth S/D contact coupled to the bottom face of the second S/D region.

Example 15 provides the transistor arrangement according to any of examples 12-14, further including a first gate contact coupled to the top face of the gate electrode and a second gate contact coupled to the bottom face of the gate electrode.

Example 16 provides the transistor arrangement according to any of examples 12-15, where the structure of the channel material includes a plurality of nanoribbons.

Example 17 provides the transistor arrangement according to any of examples 12-16, where the transistor arrangement is partially enclosed by a support structure, the support structure having a top face in the first plane and a bottom face in the second plane.

Example 18 provides a method of fabricating an IC device, the method including forming a channel material embedded in a support structure, the channel material having a longitudinal structure extending in a direction parallel to an upper face the support structure; etching regions of the support structure around a first portion, a second portion, and a third portion of the channel material; forming a first S/D region that encloses the first portion of the channel material; forming a second S/D region that encloses the third portion of the channel material; forming a gate that encloses the second portion of the channel material; forming a first set of contacts on a first side of the first S/D region, the second S/D region, and the gate; and forming a second set of contacts on a second side of the first S/D region, the second S/D region, and the gate, the second side opposite the first side.

Example 19 provides the method according to example 18, further including forming a first interconnect layer over the first set of contacts, the first interconnect layer including conductive material coupled to at least a portion of the first set of contacts; and forming an interconnect layer over the second set of contacts, the second interconnect layer including conductive material coupled to at least a portion of the second set of contacts.

Example 20 provides the method according to example 18, further including grinding at least a portion of the support structure on a side of the support structure opposite the first set of contacts.

Example 21 provides an IC device including a support structure having a front face and a back face; a channel material at least partially enclosed in the support structure; and a plurality of transistors formed in the support structure and along the channel material, one of the transistors including a first S/D region enclosing a first portion of the channel material, a gate electrode enclosing a second portion of the channel material, and a second S/D region enclosing a third portion of the channel material.

Example 22 provides the IC device according to example 21, further including a first interconnect layer on the front face of the support structure and a second interconnect layer on the back face of the support structure.

Example 23 provides the IC device according to example 22, further including a capacitor coupled to the first S/D region via the first interconnect layer, the capacitor and the first transistor forming a memory cell.

Example 24 provides the IC device according to any of examples 21-23, further including first and second S/D contacts coupled to opposite sides of the first S/D region, and third and fourth S/D contacts coupled to opposite sides of the second S/D region.

Example 25 provides the IC device according to any of examples 21-23, further including an S/D contact coupled to the first S/D region, the S/D contact further coupled to an S/D region of a second transistor of the plurality of transistors.

Example 26 provides the IC device according to any of examples 21-25, where the support structure includes a first layer and a second layer, the channel material is at least partially enclosed in the first layer, and at least one contact extends through the second layer and coupled to the first S/D region of the transistor.

Example 27 provides an IC package that includes an IC die, including one or more of the memory/IC devices according to any one of the preceding examples. The IC package may also include a further component, coupled to the IC die.

Example 28 provides the IC package according to example 27, where the further component is one of a package substrate, a flexible substrate, or an interposer.

Example 29 provides the IC package according to examples 27 or 28, where the further component is coupled to the IC die via one or more first level interconnects.

Example 30 provides the IC package according to example 29, where the one or more first level interconnects include one or more solder bumps, solder posts, or bond wires.

Example 31 provides a computing device that includes a circuit board; and an IC die coupled to the circuit board, where the IC die includes one or more of the transistors/IC devices according to any one of the preceding examples (e.g., transistors/IC devices according to any one of examples 1-26), and/or the IC die is included in the IC package according to any one of the preceding examples (e.g., the IC package according to any one of examples 27-30).

Example 32 provides the computing device according to example 31, where the computing device is a wearable computing device (e.g., a smart watch) or hand-held computing device (e.g., a mobile phone).

Example 33 provides the computing device according to examples 31 or 32, where the computing device is a server processor.

Example 35 provides the computing device according to examples 31 or 32, where the computing device is a motherboard.

Example 36 provides the computing device according to any one of examples 31-34, where the computing device further includes one or more communication chips and an antenna.