Vertical DRAM cell with wordline self-aligned to storage trench

A dynamic random access memory (DRAM) device. The DRAM device is formed in a substrate having a top surface and a trench with a sidewall formed in the substrate. A signal storage node is formed using a bottom portion of the trench and a signal transfer device is formed using an upper portion of the trench. The signal transfer device includes a first diffusion region coupled to the signal storage node and extending from the sidewall of the trench into the substrate, a second diffusion region formed in the substrate adjacent to the top surface of the substrate and adjacent the sidewall of the trench, a channel region extending along the sidewall of the trench between the first diffusion region and the second diffusion region, a gate insulator formed along the sidewall of the trench extending from the first diffusion region to the second diffusion region, a gate conductor filling the trench and having a top surface, and a wordline having a bottom adjacent the top surface of the gate conductor and a side aligned with the sidewall of the trench.

TECHNICAL FIELD 
The present invention relates generally to a dynamic random access memory 
(DRAM) device and, more particularly, to a vertical DRAM device having a 
wordline self-aligned to a storage trench. 
BACKGROUND OF THE INVENTION 
In the semiconductor industry, there is an ever-increasing desire to 
increase memory density and performance. These goals are often achieved by 
scaling dynamic random access memory (DRAM) devices to smaller dimensions 
and operating voltages. 
Vertical DRAM devices use a trench to form both a signal storage node and a 
signal transfer device. Vertical DRAM devices have been proposed to 
increase memory density because they decouple the length of the vertical 
signal transfer device channel from the minimum feature size. This 
configuration allows longer channel lengths without a proportional 
decrease in memory density. Channel length may then be properly scaled 
relative to gate oxide thickness and relative to junction depth to reduce 
channel doping, minimize junction leakage, and increase retention times. 
FIG. 1 shows a partial cross-sectional view of a vertical DRAM device or 
cell 100 formed in a substrate 101 (typically P-silicon). The DRAM cell 
100 is formed using a trench (DT or deep trench) having a sidewall 122. 
The DRAM cell 100 includes a signal storage node (partially shown) 102 
which includes a storage node conductor 104 (typically N+ polysilicon) and 
a collar oxide 106. The signal transfer device of the DRAM cell 100 
includes a first diffusion region 108, a second diffusion region 
110(typically N+ silicon), a channel region 112, a gate insulator 114, and 
a gate conductor 116 (typically N+ polysilicon). 
The gate conductor 116 is coupled to the wordline 118. The wordline 118 
comprises an N+ polysilicon lower layer 118A, a WSi.sub.x middle layer 
118B, and a nitride cap layer 118C. The second diffusion region 110 is 
covered by a nitride layer 120. The storage node conductor 104 is covered 
by a trench-top oxide (TTO) 123. A shallow trench isolation (STI) region 
128 is formed to provide isolation for DRAM device 100. 
The trench sidewall 122 of the DRAM cell 100 is a distance W from the 
sidewall 124 of the trench of an adjacent DRAM cell. For DRAM cells 100 
occupying a 5F.sup.2 surface area of the substrate 101, where F is the 
minimum feature size, the distance W between adjacent trench sidewalls may 
be 2F. With a trench-to-trench distance W of 2F, a wordline 118 can 
overlap past the sidewall 122 of the trench by a distance of 0.5F. This 
configuration allows adequate overlap of the gate conductor 116 by 
wordline 118 even in the worst case of misalignment when DT and wordline 
bias are under control. DRAM cell density on a wafer may be increased by 
decreasing the trench-to-trench spacing W. As trench-to-trench spacing W 
is reduced below 2F, the probability that the wordline conductor will not 
overlap the trench edge increases because the layed out overlap of the 
wordline to the trench is reduced below 0.5F while the alignment tolerance 
remains constant. 
DRAM cell 100 in FIG. 1 has a wordline 118 which does not completely 
overlap the trench sidewall 122. This incomplete overlap causes the etch 
used to form the wordline 118 to cut into the underlying gate conductor 
116 as illustrated by the gate conductor over-etch 105. Over-etch 105 may 
result in damage to the gate insulator 114 and a failure of the gate 
conductor 116 to overlap the second diffusion region 110. 
To overcome the shortcomings of conventional DRAM devices, a new vertical 
DRAM device is provided. An object of the present invention is to provide 
a vertical DRAM device that has a wordline conductor self-aligned to the 
sidewall of the trench. A related object is to provide a process of 
manufacturing such a vertical DRAM device. Another object is to provide a 
pair of vertical DRAM devices each having a respective wordline and each 
formed using a respective trench in which the distance between the 
respective trenches equals the distance between respective wordlines. It 
is still another object to provide a vertical DRAM device having a 
wordline positioned above the surface of the substrate. 
SUMMARY OF THE INVENTION 
To achieve these and other objects, and in view of its purposes, the 
present invention provides a dynamic random access memory device formed in 
a substrate. The substrate has a top surface and has a trench having a 
sidewall formed in the substrate. A signal storage node is formed using a 
bottom portion of the trench and a signal transfer device is formed using 
an upper portion of the trench. The signal transfer device includes a 
first diffusion region coupled to the signal storage node and extending 
from the sidewall of the trench into the substrate, a second diffusion 
region formed in the substrate adjacent to the top surface of the 
substrate and adjacent to the sidewall of the trench, a channel region 
extending along the sidewall of the trench between the first diffusion 
region and the second diffusion region, a gate insulator formed along the 
sidewall of the trench extending from the first diffusion region to the 
second diffusion region, a gate conductor filling the trench and having a 
top surface, and a wordline having a bottom adjacent the top surface of 
the gate conductor and a side aligned with the sidewall of the trench. 
It is to be understood that both the foregoing general description and the 
following detailed description are exemplary, but are not restrictive, of 
the invention.

DETAILED DESCRIPTION OF THE INVENTION 
Referring now to the drawing, in which like reference numbers refer to like 
elements throughout, an exemplary process of manufacturing a vertical DRAM 
device according to the present invention is described with reference to 
FIGS. 2 through 8. FIG. 2 is a partial cross-sectional view of a wafer 
after deep trench processing as known to those skilled in the art. A 
nitride layer 226 is formed upon a substrate 201 such as P-silicon, for 
example, before the deep trench processing. In an exemplary embodiment, a 
thin thermal oxide (not shown) may be formed on the surface of the 
substrate 201 before forming the nitride layer 226. The thin thermal oxide 
may reduce defects in the substrate 201. In an exemplary embodiment, 
before etching the deep trenches, an oxide layer (not shown) may be formed 
over the nitride layer 226 to serve as a bard etch mask. 
Each vertical DRAM device 200, 230 is formed in the substrate 201 using a 
trench (DT or deep trench) having sidewalls 222, 223. The DRAM cell 200 
includes a signal storage node (partially shown) 202 which includes a 
storage node conductor 204 and a collar oxide 206. The signal transfer 
device of the DRAM cell 200 includes a first diffusion region 208, a 
channel region 212, a gate insulator 214, and a gate conductor 216 
(typically polysilicon). 
The storage node conductor 204 is isolated from the gate conductor 216 by a 
trench-top oxide (TTO) 224. In an exemplary embodiment of the present 
invention, the trench-top oxide 224 has a thickness greater than the 
thickness of the gate insulator 214. The TTO 224 may be formed thicker by 
thermally growing an oxide layer that will grow thicker on the storage 
node conductor 204, which is comprised of N+ polysilicon in this exemplary 
embodiment, than on the substrate 201, which is P-silicon in this 
embodiment. Alternatively, the TTO 224 may be formed by high density 
plasma (HDP) silicon dioxide deposition. The gate conductor 216 is then 
deposited and planarized to the surface of the pad nitride layer 226. In 
an exemplary embodiment, the gate conductor 216 comprises heavily doped 
polysilicon. 
FIG. 2A is a top view of an array of DRAM devices 200 shown in FIG. 2 
according to an exemplary layout. A wafer may include both an array region 
in which DRAM devices 200 are formed and a support region in which support 
circuitry is formed. FIG. 2B is a partial cross-sectional view of support 
circuitry at a stage in processing corresponding to FIG. 2. 
As shown in FIG. 3, shallow trench isolation (STI) regions 228 are formed 
to provide isolation between adjacent devices 200, 230. In the exemplary 
embodiment shown in FIG. 3, the STI regions 228 are formed by first 
patterning the wafer and then etching an STI trench to a level below the 
first diffusion region 208 to provide sufficient isolation between the 
first diffusion regions 208 of adjacent devices 200, 230. The oxide used 
to form STI regions 228 is then deposited and planarized to the surface of 
the pad nitride 226. In an exemplary embodiment, high density plasma (HDP) 
oxide deposition is used to fill the high aspect ratio STI trench. 
FIG. 3A is a top view of an array of the DRAM devices shown in FIG. 3 
according to an exemplary layout. The dashed lines illustrate the boundary 
236 of the deep trenches cut off by the STI region 228. FIG. 3B is a 
partial cross-sectional view of support circuitry at a stage in processing 
corresponding to FIG. 3 illustrating that STI regions 228 are also formed 
in the support regions of the wafer. 
As shown in FIG. 3C, the pad nitride layer 226 in the support regions is 
then patterned and etched down to the substrate 201 to define active area 
regions. A sacrificial oxide 280 is then grown on the exposed substrate 
201. Well implants (represented by arrows 270) are next performed. 
As shown in FIG. 3D, the sacrificial oxide 280 is removed and a gate 
insulator layer 282 is formed. A layer of polysilicon is then deposited 
and polished to the surface of the nitride pad layer 226 to form a gate 
conductor 284. This polishing step removes from the array region excess 
polysilicon and oxide which were formed during support region processing. 
Gate conductor implants (represented by arrows 272) are then performed 
into the gate conductor 284 to establish the doping of the gate conductor 
284. 
A photoresist 238 is then deposited upon the wafer and patterned as shown 
in FIG. 4. The photoresist 238 is intentionally misaligned with the deep 
trenches in this exemplary embodiment to illustrate that wordlines (formed 
later) will be aligned to the deep trenches regardless of the alignment of 
the pattern of the photoresist 238. FIG. 4A is a top view of the DRAM 
devices shown in FIG. 4. FIG. 4B is a partial cross-sectional view of 
support circuitry at a stage in processing corresponding to FIG. 4. 
As shown in FIG. 5, the exposed oxide in the STI regions 228 is etched 
selective to pad nitride layer 226, polysilicon gate conductor 216, and 
photoresist 238. In an exemplary embodiment of the present invention, the 
exposed oxide is etched using reactive ion etching (RIE). In an exemplary 
embodiment of the present invention, the bottom 239 of the etched oxide is 
above the top surface of the substrate 201 as illustrated by distance D. 
This configuration helps to avoid shorts between the gate conductor 216 
and the substrate 201. 
The oxide etch may result in a small amount of the gate conductor 216 being 
removed without adverse consequences. A wordline-to-substrate 201 short 
may occur if the gate conductor 216 is etched to a level below the surface 
of the substrate 201. The wordline-to-substrate 201 short may be avoided 
by adding spacers (not shown) on the exposed sidewalls of the substrate 
201 before depositing the wordline conductor. 
As shown in FIG. 6, the photoresist 238 is then stripped and the exposed 
polysilicon gate conductor 216 is isotropically etched selective to oxide 
STI region 228 and pad nitride layer 226. This etch forms a damascened 
channel for a wordline conductor including the union of the opening formed 
in the STI region 228 and the opening formed in the gate conductor 216. In 
the exemplary embodiment shown in FIG. 6, the polysilicon gate conductor 
216 is etched to a level above the top surface of the silicon substrate 
201. In an exemplary embodiment and as shown in FIG. 6, the isotropic etch 
of the polysilicon gate conductor 216 may result in a top surface 217 of 
the polysilicon gate conductor 216 which is tapered so that the top 
surface 217 is slightly higher towards the gate insulator 214. This taper 
helps to protect the gate insulator 214 from damage caused by the etch. 
FIG. 6A is a partial cross-sectional view of support circuitry at a stage 
in processing corresponding to FIG. 6. As shown in FIG. 6A, the isotropic 
etch described with regard to FIG. 6 recesses the gate conductor 284 to 
form a channel 292 for gate conductor wiring. 
As shown in FIG. 7, a wordline conductor 218, 232 is then deposited, 
planarized, and recessed below the surface of the pad nitride layer 226. 
FIG. 7A is a top view of the device shown in FIG. 7 after the wordline 
218, 232 has been deposited. FIG. 7A illustrates that the wordline 
conductor 218 of DRAM device 200 is aligned with the sidewall 222 of the 
deep trench and the wordline conductor 232 of DRAM device 230 is aligned 
with the sidewall 246 despite misalignment of the wordline mask 
photoresist 238 (see FIG. 4). Positioning the wordline conductor 218 in 
alignment with the sidewall 222 of the deep trench and above the top 
surface of the substrate 201 provides a processing advantage by 
eliminating the need for a protection spacer to prevent a short between 
the wordline conductor 218 and the substrate 201. 
In the exemplary embodiment shown in FIG. 7, the wordline conductor 218 
comprises tungsten silicide. The material of wordline conductor 218 is not 
limited to tungsten silicide; rather, other conductive materials may be 
used as are known to those skilled in the art. In another exemplary 
embodiment, for example, the wordline conductor 218 comprises tungsten. A 
conductive material (not shown) may optionally be deposited to form a 
liner on the interior of the channel region 212 before deposition of the 
wordline conductor 218. The conductive liner, which may be comprised of 
tungsten nitride, for example, may protect the wordline conductor 218 from 
reacting with adjacent material during subsequent hot processing steps. 
In an exemplary embodiment, an insulating spacer (not shown) may be formed 
coincident with the sidewall 222 of the trench before depositing the 
wordline conductor 218. The spacer may provide additional protection 
against a short between the wordline conductor 218 and the substrate 201. 
In this case, the wordline conductor 218 would be a predetermined distance 
away from alignment with the sidewall 222 of the trench. 
In another exemplary embodiment (not shown), the etch through the STI 
region 228 and the etch through the gate conductor 216 extend to a depth 
near or below the top surface of the substrate 201. Shorts to the 
substrate 201 may then be prevented by depositing an insulator before 
depositing the wordline conductor 218. This embodiment may be used to 
increase the thickness of the wordline conductor 218 to reduce wordline 
conductor resistance. 
As shown in FIG. 7, the sidewall 222 of the trench of DRAM cell 200 is a 
distance W from the sidewall 246 of the trench of an adjacent DRAM cell 
230. The wordline conductor 218 corresponding to DRAM cell 200 has a 
sidewall 219 and the wordline conductor 232 of adjacent DRAM cell 230 has 
a sidewall 233. In this exemplary embodiment, the sidewalls 219, 233 of 
the wordline conductors 218, 232 are each aligned with the sidewalls 222, 
246 of their respective trenches and are a distance W apart. In another 
exemplary embodiment (not shown), only one of the wordline conductors 218, 
232 has its sidewall 219, 233 aligned with the sidewall 222, 246 of its 
respective trench. In another exemplary embodiment (not shown), one or 
more of the wordline conductors 218, 232 are spaced a predetermined 
thickness away from the sidewalls 222, 246 of their respective trenches. 
After the wordline conductor 218 has been deposited, an oxide layer 240 is 
then deposited upon the wordline conductor 218, by chemical vapor 
deposition (CVD), for example. The oxide layer 240 is then planarized to 
the top surface of the pad nitride layer 226. 
FIG. 7B is a partial cross-sectional view of support circuitry at a stage 
in processing corresponding to FIG. 7. As shown in FIG. 7B, the gate 
conductor wiring 290 is formed in the support region while the wordline 
conductors 218, 232 are formed in the array region. 
As shown in FIG. 8, the pad nitride layer 226 is then removed selective to 
the oxide of the STI region 228 and the oxide layer 240. A screen oxide 
layer (not shown) is then grown and array region p-well implants (not 
shown) are performed. An N+ dopant is then implanted to form the second 
diffusion region (bit line diffusion) 210. 
FIG. 8A is a partial cross-sectional view of support circuitry at a stage 
in processing corresponding to FIG. 8. Source and drain implants may then 
be performed in the support region to form diffusion regions 288 (FIG. 
8A). Oxide spacers 242 are then formed on the sidewalls 219, 233 of the 
wordline conductors 218, 232 (FIG. 8) and on the sidewalls of the support 
gates (FIG. 8A). A bit line conductor 244 such as polysilicon is then 
deposited and planarized. The bit line conductor 244 may be removed from 
the support region in preparation for later formation of tungsten studs 
286, or, alternatively, tungsten studs 286 may be used throughout instead 
of using a polysilicon bit line conductor 244 in the array region. 
A process of manufacture according to the present invention provides a DRAM 
device having improved performance due to reduced wordline resistance. The 
RC delay of wordline gates most distant from a wordline driver rise more 
slowly than closer wordline gates. By decreasing the resistance of the 
wordline, the RC time constant seen by the wordline driver is reduced. 
This advantage allows the wordline voltage to rise more rapidly, resulting 
in improved performance by reducing the skew of rise time along the 
wordline. A process of manufacture according to the present invention has 
reduced sensitivity to wordline etching tolerances because the wordline is 
formed in a trench and because the trench etch through the gate conductor 
is selective to the gate insulator. This allows for a thicker and, 
therefore, lower-resistance wordline, if desired. 
The present invention also allows the use of metal wordlines without the 
disadvantages associated with wordlines formed by subtractive etch 
processes. A subtractive etch to pattern a wordline stack is often 
followed by formation of a sidewall oxide to heal damage caused by the 
subtractive etch. Non-metal wordlines are often used to avoid problems 
associated with the reactivity of metal with the sidewall oxide. 
In contrast, the wordline according to the present invention is formed in a 
channel etched into the STI region and into the gate conductor. Thus, a 
metal wordline may be used because the wordline is not patterned by a 
subtractive etch. Metal wordlines allow the resistance of the wordlines to 
be further reduced. In an exemplary embodiment of the present invention, a 
wordline has a resistance less than 1 ohm/square (where square is the 
cross-sectional distance of the wordline in the direction of current 
divided by the distance perpendicular to the current). 
Metal wordlines may also be used to simultaneously reduce the resistance 
and capacitance of a wordline. The reduced resistance of a metal wordline 
allows a wordline to have a smaller sidewall area while still achieving a 
desired resistance. The smaller sidewall area reduces wordline capacitance 
between the wordline and a bit line stud, for example. 
Although illustrated and described above with reference to certain specific 
embodiments, the present invention is nevertheless not intended to be 
limited to the details shown. Rather, various modifications may be made in 
the details within the scope and range of equivalents of the claims and 
without departing from the spirit of the invention.