Testing device and testing method for power converters

A power converter to be tested is supplied with arm current from a hysteresis converter in a state in which it is connected to an auxiliary converter through a line. In the power converter and the auxiliary converter, a circulation operation is performed in which a current path bypassing power storage elements is formed between an output terminal of the power converter and an output terminal of the auxiliary converter, after the start of output of arm current in accordance with a reference current command value in which an AC component and a DC component are superimposed, until a DC component of arm current reaches a predetermined level. After execution of the circulation operation, in the power converter and the auxiliary converter, voltage control of the power storage elements and the output terminals is started.

CROSS-REFERENCE TO RELATED APPLICATION

The present application is based on PCT filing PCT/JP2019/044417, filed Nov. 12, 2019, the entire contents of which is incorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates to a testing device and a testing method for power converters.

BACKGROUND ART

In power conversion devices for use in high voltage applications such as power systems, multilevel converters formed with a plurality of converter cells connected in series in multiple stages have recently been put to practice. These converters are called modular multilevel converter (MMC) systems or cascaded multilevel converter (CMC) systems.

For testing a single cell of these converters, for example, Japanese Patent Laying-Open No. 2016-10295 (PTL 1) and NPL 1 below describe a testing system for performing operation verification for each converter by simulating current similar to that in actual operation and feeding the current through a converter cell.

In PTL 1, a bridge circuit including a plurality of bridge-connected converters (MMC) operates such that DC power from a DC power source is converted to be supplied to an AC load, whereby voltage and current supplied per converter in actual operation are simulated to verify the operation of each converter. NPL 1 describes a testing system including a unit converter, an auxiliary converter having substantially the same structure as the unit converter, a hysteresis converter, and a reactor.

CITATION LIST

Patent Literature

Non Patent Literature

NPL 1: Yung Tang, Li Ran et al, “Design and Control of a Compensated Submodule Testing Scheme for Modular Multilevel Converter”, 2016 IEEE Applied Power Electronics Conference and Exposition (APEC)

SUMMARY OF INVENTION

Technical Problem

Unfortunately, in PTL 1, at least four converters (MMC) need be connected to form a bridge circuit, and a DC reactor is connected to each converter. This configuration may lead to size increase of the testing system.

The configuration in NPL 1 is useful as a testing system for a unit converter, but there is no mention as to initial charging of a capacitor included in the unit converter to be tested. On the other hand, in initial charging immediately after start of testing, the capacitor voltage may become unbalanced between the unit converter and the auxiliary converter to cause unstable circuit operation.

The present disclosure is made in order to solve such a problem, and an object of the present disclosure is to stabilize circuit operation at the start of testing a power converter.

Solution to Problem

An aspect of the present disclosure provides a testing device for a power converter. The power converter to be tested includes first and second main switching elements connected in series through a first terminal, and a first power storage element connected in parallel with a series connection of the first and second main switching elements. The testing device includes an auxiliary converter, a line electrically connecting the power converter and the auxiliary converter, a current output circuit, and a control circuit to control the current output circuit, the power converter, and the auxiliary converter. The auxiliary converter includes a series connection of first and second auxiliary switching elements connected in series through a second terminal, and a second power storage element connected in parallel with the series connection. The current output circuit is connected to the first and second terminals and outputs test current for the power converter in accordance with a reference current command value in which an AC current command value and a DC current command value are superimposed. The control circuit executes circulation operation to fix ON and OFF of the first and second main switching elements and the first and second auxiliary switching elements such that a current path bypassing the first and second power storage elements is formed between the first and second terminals until a DC component of the test current reaches a predetermined level, after start of output of the test current from the current output circuit in accordance with the reference current command value. Further, the control circuit starts ON and OFF control of the first and second main switching elements and the first and second auxiliary switching elements for voltage control at least including control of voltages of the first and second power storage elements in accordance with a power storage element voltage command value, after the DC component reaches the predetermined level.

Another aspect of the present disclosure provides a testing method for a power converter. The power converter to be tested includes first and second main switching elements connected in series through a first terminal, and a first power storage element connected in parallel with a series connection of the first and second main switching elements. The power converter is tested in a state in which the power converter is electrically connected to an auxiliary converter through a line, the auxiliary converter including a series connection of first and second auxiliary switching elements connected in series through a second terminal, and a second power storage element connected in parallel with the series connection. The testing method includes the steps of: after start of output of test current from a current output circuit connected to the first and second terminals in accordance with a reference current command value in which an AC current command value and a DC current command value are superimposed, executing a circulation operation until a DC component of the test current reaches a predetermined level; and after the DC component reaches the predetermined level, starting ON and OFF control of the first and second main switching elements and the first and second auxiliary switching elements for voltage control at least including control of voltages of the first and second power storage elements in accordance with a power storage element voltage command value. In the circulation operation, in the power converter and the auxiliary converter, ON and OFF of the first and second main switching elements and the first and second auxiliary switching elements are fixed such that a current path bypassing the first and second power storage elements is formed between the first and second terminals.

Advantageous Effects of Invention

According to the present disclosure, voltage control of the first and second power storage elements in accordance with the power storage element voltage command value is started after the DC component of test current supplied to the power converter and the auxiliary converter rises, so that the only active power that flows from the power output circuit to the power converter and the auxiliary converter is the power under voltage control of the first and second power storage elements. Consequently, the voltage between first and second power storage elements can be prevented from abruptly becoming unbalance at the start of testing of the power converter, and the circuit operation can be stabilized.

DESCRIPTION OF EMBODIMENTS

Embodiments of the present disclosure will be described in detail below with reference to the drawings. In the following, like or corresponding parts in the drawings are denoted by like reference signs and a description thereof is basically not repeated.

First Embodiment

FIG.1is a circuit diagram illustrating a first configuration example of a testing system including a testing device according to the present embodiment.

Referring toFIG.1, a testing system1aaccording to the present embodiment includes a control circuit2, a power converter100xto be tested, an auxiliary converter200x, a line110, and a current output circuit for outputting test current that simulates actual operation. The current output circuit can be configured with a hysteresis converter300and a reactor L1. Hereinafter the inductance value of reactor L1is also denoted by L1. The part of testing system1aexcluding power converter100xto be tested forms the testing device according to the present embodiment.

Power converter100xto be tested includes, for example, switching elements Q11and Q12connected in series and a power storage element C1. Hereinafter the capacitance of power storage element C1is also denoted by C1. Power storage element C1is connected in parallel with a series connection of switching elements Q11and Q12. The connection node of switching elements Q11and Q12is connected to an output terminal T11. That is, switching elements Q11and Q12are connected in series through output terminal T11. Switching element Q11is driven ON and OFF by a gate drive circuit Gd11, and switching element Q12is driven ON and OFF by a gate drive circuit Gd12.

In power converter100x, output terminal T11corresponds to “first terminal”, switching elements Q11and Q12correspond to “first and second main switching elements”, and power storage element C1corresponds to “first power storage element”.

Auxiliary converter200xhas a configuration similar to power converter100xand includes switching elements Q21and Q22connected in series and a power storage element C2. Hereinafter the capacitance of power storage element C2is also denoted by C2. Power storage element C2is connected in parallel with a series connection of switching elements Q21and Q22. Switching elements Q21and Q22are connected in series through an output terminal T21. Switching element Q21is driven ON and OFF by a gate drive circuit Gd21, and switching element Q22is driven ON and OFF by a gate drive circuit Gd22.

Although auxiliary converter200xhas a circuit configuration similar to power converter100x, the constituent elements need not be completely identical. For example, there may be a difference in that switching elements Q11and Q12of power converter100xare formed of silicon carbide (SiC)-metal oxide semiconductor field effect transistors (MOSFETs), whereas switching elements Q21and Q22of auxiliary converter200xare formed of Si-insulated gate bipolar transistors (IGBTs).

In auxiliary converter200x, output terminal T21corresponds to “second terminal”, switching elements Q21and Q22correspond to “first and second auxiliary switching elements”, and power storage element C2corresponds to “second power storage element”.

Hysteresis converter300includes a first leg301, a second leg302, and a power storage element C3. First leg301includes switching elements Q31and Q32connected in series through a terminal T31. Second leg302includes switching elements Q33and Q34connected in series through a terminal T32. First leg301, second leg302, and power storage element C3are connected in parallel. Switching elements Q31to Q34are driven ON and OFF by gate drive circuits Gd31to Gd34.

Reactor L1is connected between terminal T31of hysteresis converter300and output terminal T11of power converter100x. Terminal T32of hysteresis converter300is electrically connected to output terminal T21of auxiliary converter200x. Reactor L1may be connected between terminal T32of hysteresis converter300and output terminal T21of auxiliary converter200x. In this case, terminal T31of hysteresis converter300and output terminal T11of power converter100xmay be electrically connected, not through the reactor. That is, reactor L1is connected at least one of: between terminal T31and output terminal T11; and between terminal T32and output terminal T21. Hereinafter the inductance of reactor L1is also denoted by L1.

Line110connects the respective negative electrodes of power storage element C1of power converter100xand power storage element C2of auxiliary converter200x. Thus, a current path in which current Iarm (hereinafter also referred to as arm current Iarm) output from hysteresis converter300for testing power converter100xpasses through power converter100xand auxiliary converter200xcan be formed between terminals T31and T32of hysteresis converter300. That is, terminal T31corresponds to “first test terminal”, terminal T32corresponds to “second test terminal”, and arm current Iarm corresponds to an embodiment of “test current”.

Control circuit2controls the operation of power converter100x, auxiliary converter200x, and hysteresis converter300. For example, control circuit2can be configured with a microprocessor including a central processing unit (CPU)2a, a memory2b, and an input/output (I/O) circuit2c. Input/output circuit2cexecutes input of detection values by sensors arranged in testing system1aand output of control signals to constituent elements of testing system1a.

Control circuit2can implement control functions illustrated in the block diagrams described later through software processing in which CPU2aexecutes computational processing under instructions of a program stored in memory2b. Alternatively, control circuit2may implement some or all of the control functions through hardware processing by dedicated electronic circuitry.

In testing system1a, in power converter100x, a sensor VT1is arranged for detecting a voltage Vcap1(hereinafter also referred to as capacitor voltage Vcap1) of power storage element C1. Similarly, in auxiliary converter200x, a sensor VT2is arranged for detecting a voltage Vcap2(hereinafter referred to as capacitor voltage Vcap2) of power storage element C2. Further, in testing system1a, a sensor CT1is arranged for detecting arm current Iarm. The detection values by these sensors VT1, VT2, and CT1are transmitted to control circuit2.

Control circuit2generates gate signals G31to G34for controlling ON and OFF of switching elements Q31to Q34included in hysteresis converter300, gate signals G11and G12for controlling ON and OFF of switching elements Q11and Q12included in power converter100x, and gate signals G21and G22for controlling ON and OFF of switching elements Q21and Q22included in auxiliary converter200x.

Gate signals G11, G12, G21, G22, and G31to G34are transmitted to gate drive circuits Gd11, Gd12, Gd21, Gd22, and Gd31to Gd34. Gate drive circuits Gd11, Gd12, Gd21, Gd22, and Gd31to Gd34drive switching elements Q11, Q12, Q21, Q22, and Q31to Q34ON and OFF, in response to gate signals G11, G12, G21, G22, and G31to G34. Gate signals G11, G12, G21, G22, and G31to G34may be transmitted to gate drive circuits Gd11, Gd12, Gd21, Gd22, and Gd31to Gd34in the form of optical signals using an optical fiber or in the form of electrical signals using a cable.

Power supply for driving control circuit2, gate drive circuits Gd11, Gd12, Gd21, Gd22, Gd31to Gd34, and sensors VT1, VT2, and CT1can be supplied using an external power source such as a not-shown switching power supply. Alternatively, a main circuit power supply device used as the power supply by a voltage conversion function from stored energy of power storage elements C1and C2may be arranged.

Control of power converter100x, auxiliary converter200x, and hysteresis converter300by control circuit2will now be described.

FIG.2is a block diagram illustrating a control configuration of hysteresis converter300.

Referring toFIG.2, control circuit2shown inFIG.1includes a hysteresis control unit20. Hysteresis control unit20controls arm current Iarm output from hysteresis converter300, in accordance with a reference current command value Iarm*. Specifically, arm current Iarm is controlled in a certain range defined by a hysteresis width command value ΔIarm* around the reference current command value Iarm*. As described above, arm current Iarm passes through reactor L1, power converter100x, and auxiliary converter200xand is detected by sensor CT1.

FIG.3shows a waveform diagram of arm current Iarm for explaining control operation of hysteresis converter300.

Referring toFIG.3, the reference current command value Iarm* is expressed by the following equation (1) in which a DC current command value Idc* and an AC current command value Iac*·sin(ωt+θ) are superimposed.
Iarm*=Idc*+Iac*·sin(ωt+θ)  (1)

In equation (1), for time t, ω and θ represent the angular frequency and the phase of an AC component. Passage current in actual operation of each converter cell of the MMC can be simulated by applying the reference current command value Iarm* by superimposing the DC current command value (Idc*) and the AC current command value (Iac*·sin(ωt+θ)). Although the DC component (DC current command value) Idc* may be set to a negative value (the direction in which current flows from power converter100xinto hysteresis converter300), a case of Idc*>0 will be described below.

An upper limit current command value Iarmh*(=Iarm*+ΔIarm) and a lower limit current command value Iarml* (=Iarm*−ΔIarm) are set based on the reference current command value Iarm* and the preset hysteresis width command value ΔIarm.

Referring toFIG.1again, in hysteresis converter300, in a first period in which switching elements Q31and Q34are turned ON and switching elements Q32and Q33are turned OFF, a positive pulse voltage with DC voltage of power storage element C3as an amplitude is output between terminals T31and T32. Conversely, in a second period in which switching elements Q32and Q33are turned ON and switching elements Q31and Q34are turned ON, a negative pulse voltage with DC voltage of power storage element C3as an amplitude is output between terminals T31and T32. In the first period in which a positive pulse voltage is output, arm current Iarm rises, while in the second period in which a negative pulse voltage is output, arm current Iarm lowers.

Referring toFIG.2andFIG.3again, hysteresis control unit20generates gate signals G31to G34, based on comparison of the detected arm current Iarm with the upper limit current command value Iarmh* and the lower limit current command value Iarml*.

Specifically, in the first period in which arm current Iarm rises, the first period is kept until arm current Iarm reaches the upper limit current command value Iarmh*. That is, gate signals G31to G34are generated such that switching elements Q31and Q34are turned ON and switching elements Q32and Q33are turned OFF.

When the rising arm current Iarm reaches the upper limit current command value Iarmh*, switching to the second period is executed. As a result, gate signals G31to G34are generated such that switching elements Q32and Q33are turned ON and switching elements Q31and Q34are turned OFF.

The second period is kept until arm current Iarm lowers to the lower limit current command value Iarml*. When arm current Iarm lowers to the lower limit current command value Iarml*, switching to the first period is executed. As a result, gate signals G31to G34are generated such that switching elements Q31and Q34are turned ON and switching elements Q32and Q33are turned OFF.

In this way, the first period and the second period are alternately provided based on the comparison with the upper limit current command value Iarmh* and the lower limit current command value Iarml*, so that arm current Iarm follows the reference current command value Iarm* to be controlled in the range of Iarm*±ΔIarm*.

An operation command signal HYSon for hysteresis converter300is further input to hysteresis control unit20. When the operation command signal HYSon is “1”, hysteresis control unit20generates gate signals G31to G34in accordance with the arm current control described above. On the other hand, when the operation command signal HYSon is “0”, hysteresis control unit20fixes all of gate signals G31to G34to “0” such that switching elements Q31to Q34are kept OFF.

Referring now toFIG.4toFIG.8, control of power converter100xand auxiliary converter200xin steady operation of testing system1awill be described.

Referring toFIG.4, control circuit2shown inFIG.1further includes a voltage control unit10to control power converter100xand auxiliary converter200x. Voltage control unit10includes an output voltage command value generator11and pulse width modulation (PWM) controllers12and13.

Output voltage command value generator11outputs an output voltage command value Vcell1for power converter100xand an output voltage command value Vcell2for auxiliary converter200x. The output voltage command value Vcell1corresponds to a command value of voltage at output terminal T11with respect to a negative electrode voltage of power storage element C1in power converter100x. Similarly, the output voltage command value Vcell2corresponds to a command value of voltage at output terminal T21with respect to a negative electrode voltage of power storage element C2in auxiliary converter200x. The output voltage command value Vcell1corresponds to “first output voltage command value”, and the output voltage command value Vcell2corresponds to “second output voltage command value”.

Output voltage command value generator11calculates the output voltage command values Vcell1and Vcell2, based on a reference output voltage command value Vcell*, the reference current command value Iarm*, a power storage element voltage command value Vcap*, the capacitor voltage Vcap1detected by sensor VT1, and the capacitor voltage Vcap2detected by sensor VT2. A voltage control execution command CTRLon for giving an instruction to execute and stop voltage control is further input to output voltage command value generator11.

Here, the reference output voltage command value Vcell* is given by the following equation (2).
Vcell*=Vdc*+Vac*·sin(ωt+θ)  (2)

In equation (2), for time t, ω is the angular frequency of an AC component and is common to equation (1). φ is the phase of the AC component and is set separately from θ in equation (1) and may be either φ≠θ or φ=θ. The reference output voltage command value Vcell* is also applied such that a DC voltage command value (Vdc*) and an AC voltage command value (Vac*·sin(ωt+φ)) are superimposed so that the output voltage in actual operation of each converter cell of the MMC can be simulated.

FIG.5shows a setting example of the power storage element voltage command value Vcap* and the reference current command value Iarm* of the arm current at the start of testing in testing system1a.

Referring toFIG.5, in testing system1a, at the start of supply of arm current Iarm in accordance with the reference current command value Iarm* from the hysteresis converter300(t=0), the DC component Idc* (absolute value) in equation (1) is set to 0 (|Idc*|=0) and, after t=0, gradually rises toward a setting value (Idcs) in a steady state. On the other hand, the AC component Iac* in equation (1) is basically kept to a certain value from the start of testing in testing system1a.

Furthermore, with the phase θ=0 in equation (1), at t=0, hysteresis converter300can start operation from the state of the reference current command value Iarm*=0.

The power storage element voltage command value Vcap* is a command value for the capacitor voltages Vcap1and Vcap2. The power storage element voltage command value Vcap* is basically set to Vcaps corresponding to the voltage of power storage elements C1and C2in actual operation (steady state) of each converter cell of the MMC. However, at the start of voltage control (time ts), power storage elements C1and C2are not charged, and therefore Vcap* is gradually raised from an initial value (for example, 0 or a minimal value). After Vcap*=Vcaps is attained, Vcap*=Vcaps is kept.

FIG.6is a block diagram illustrating a configuration example of output voltage command value generator11.

Referring toFIG.6, output voltage command value generator11includes a first computing unit11ato generate a voltage control command value Vc1for power converter100xand a second computing unit11bto calculate a voltage control command value Vc2for auxiliary converter200x.

First computing unit11aincludes a deviation computing unit11aA, a lowpass filter11aB, a proportional control unit11aC, and a multiplication unit11aD. Deviation computing unit11aA calculates a voltage deviation of the capacitor voltage Vcap1(the detection value by sensor VT1) from the power storage element voltage command value Vcap* (FIG.5). The voltage deviation calculated by deviation computing unit11aA is input to lowpass filter11aB. The voltage deviation (Vcap*−Vcap1) corresponds to “first voltage deviation”.

Proportional control unit11aC outputs a value obtained by multiplying the voltage deviation having temporal change smoothed by lowpass filter11aB by a predetermined control gain Kp (proportional gain). Multiplication unit11aD generates a multiplication value of the output value from proportional control unit11aC and the reference current command value Iarm* as the voltage control command value Vc1for compensating for the voltage deviation (Vcap*−Vcap1). That is, the voltage control command value Vc1corresponds to “first voltage control command value”.

Second computing unit11bincludes a deviation computing unit11bA, a lowpass filter11bB, a proportional control unit11bC, and a multiplication unit11bD. Deviation computing unit11bA calculates a voltage deviation of the capacitor voltage Vcap2(the detection value by sensor VT2) from the power storage element voltage command value Vcap* (FIG.5). The voltage deviation (Vcap*-Vcap2) corresponds to “second voltage deviation”.

The voltage deviation calculated by deviation computing unit11bA is input to lowpass filter11bB, and proportional control unit11bC outputs a value obtained by multiplying the voltage deviation output from lowpass filter11bB by a control gain Kp (proportional gain). Multiplication unit11bD generates a multiplication value of the output value from proportional control unit11bC and the reference current command value Iarm* as a voltage control command value Vc2for compensating for the voltage deviation (Vcap*−Vcap2). That is, the voltage control command value Vc2corresponds to “second voltage control command value”.

Output voltage command value generator11further includes an addition unit11aE, a subtraction unit11bE, and multiplication units11aF and11bF.

Addition unit11aE outputs a value obtained by adding the reference output voltage command value Vcell* to the voltage control command value Vc1by first computing unit11a. Multiplication unit11aF outputs a multiplication value of the output value from addition unit11aE and the voltage control execution command CTRLon set to “0” or “1” as the output voltage command value Vcell1of power converter100x.

When the voltage control is ON, CTRLon=“1” and Vcell1=Vcell*+Vc1is set. That is, the output voltage command value Vcell1is calculated such that a voltage in accordance with the reference output voltage command value Vcell* is output from output terminal T11and power storage element C1is charged and discharged in accordance with the power storage element voltage command value Vcap*, in power converter100x.

On the other hand, subtraction unit11bE outputs a value obtained by subtracting the voltage control command value Vc2by second computing unit11bfrom the reference output voltage command value Vcell*. Multiplication unit11bF outputs a multiplication value of the output value from subtraction unit11bE and the voltage control execution command CTRLon as the output voltage command value Vcell2of auxiliary converter200x.

Therefore, when CTRLon=“1”, Vcell2=Vcell*−Vc2is set. As a result, the capacitor voltages Vcp1and Vcp2can be controlled by the same control block (FIG.6), considering that arm current Iarm input to power converter100xis output from auxiliary converter200x. That is, the output voltage command value Vcell2is controlled such that a voltage in accordance with the reference output voltage command value Vcell* is output from output terminal T21and power storage element C2is charged and discharged in accordance with the power storage element voltage command value Vcap*, in auxiliary converter200x.

When CTRLon=“0” is set in order to turn OFF the voltage control, Vcell1=Vcell2=0 is fixed.

FIG.7shows another configuration example of output voltage command value generator11.

Referring toFIG.7, first computing unit11aand second computing unit11bdiffer from the configuration example inFIG.6in arrangement of lowpass filters11aB and11bB. Specifically, lowpass filters11aB and11bB receive the capacitor voltages Vcap1and Vcap2(detection values of sensors VT1and VT2), and deviation computing units11aA and11bA subtract the capacitor voltages Vcap1and Vcap2passed through the lowpass filters from the power storage element voltage command value Vcap* (FIG.5) to calculate voltage deviations input to proportional control units11aC and11bC. With such a configuration, the output voltage command value Vcell1(first output voltage command value) for power converter100xand the output voltage command value Vcell2(second output voltage command value) for auxiliary converter200xcan also be calculated in the same manner as inFIG.6.

The control computation based on the voltage deviation can also be executed by another known control method such as proportional integral (PI) control, instead of proportional control units11aC and11bC inFIG.6andFIG.7.

Referring toFIG.4again, PWM controller12for power converter100xgenerates gate signals G11and G12, based on the output voltage command value Vcell1from output voltage command value generator11and a carrier voltage Vcarr that is a voltage value of a carrier signal. The carrier signal is formed of, for example, triangular waves or sawtooth waves having a certain frequency. Therefore, the carrier voltage Vcarr repeatedly rises and falls in accordance with the frequency of the carrier wave in a predetermined voltage range.

FIG.8is a circuit diagram illustrating a configuration example of the PWM controller.

Referring toFIG.8, PWM controller12includes a voltage comparator12a, a NOT circuit12b, and AND circuits12cand12d. Voltage comparator12aoutputs a comparison result between the output voltage command value Vcell1and the carrier voltage Vcarr. For example, when Vcell1>Vcarr, voltage comparator12aoutputs “1”, and when Vcell1<Vcarr, voltage comparator12aoutputs “0”. NOT circuit12binverts an output value of voltage comparator12a.

AND circuit12creceives an output value of voltage comparator12aand a gate ON signal (GATEon). AND circuit12dreceives an output value of NOT circuit12band a gate ON signal (GATEon).

When GATEon=“1”, G11=“1” and G12=“0” are set in a period of Vcell1>Vcarr. Conversely, G11=“0” and G12=“1” are set in a period of Vcell1<Vcarr. In this way, gate signals G11and G12are set to mutually exclusive levels. In actuality, when the levels of gate signals G11and G12are switched, a period in which G11=G12=“0” is provided as a dead time. It is noted that “set to mutually exclusive levels” in the present embodiment includes provision of a dead time at a time of level transition.

On the other hand, when GATEon=“0”, G11=G12=“0” is fixed and switching elements Q11and Q12are kept OFF. As a result, the switching operation of power converter100xcan be stopped using the gate ON signal (GATEon).

PWM controller13for auxiliary converter200xcan also be configured in the same manner as inFIG.8. Specifically, the output voltage command value Vcell2is input to voltage comparator12a, instead of the output voltage command value Vcell1, so that gate signal G21can be output from AND circuit12c, and gate signal G22can be output from AND circuit12d.

Power converter100xand auxiliary converter200xare controlled in accordance withFIG.4toFIG.8so that ON and OFF of switching elements Q11and Q12are controlled in power converter100xsuch that the voltage at output terminal T11follows the output voltage command value Vcell1(first output voltage command value). As a result, power converter100xcan operate to output a voltage in accordance with the reference output voltage command value Vcell* from output terminal T11in a state in which power storage element C1is charged in accordance with the power storage element voltage command value Vcap* while arm current Iarm passes in accordance with the reference current command value Iarm*. As a result, in testing system1a, power converter100xcan be tested such that actual operation of each converter cell of the MMC is simulated.

Similarly, in auxiliary converter200x, ON and OFF of switching elements Q21and Q22are controlled such that the voltage at output terminal T21follows the output voltage command value Vcell2(second output voltage command value). As a result, auxiliary converter200xoperates to absorb voltage fluctuations that occur when power converter100xoperates as described above and prevent influence on the power supply side (hysteresis converter300).

On the other hand, there are concerns in the following points, immediately after the start of testing in a period until a steady state is reached.

In a state in which power converter100xoutputs a voltage in accordance with the reference output voltage command value Vcell* from output terminal T11under passage of current in accordance with the reference current command value Iarm* (Iarm*>0), a power Pcell* flowing into power converter100xis represented by the following equation (3) as average power in one cycle of the fundamental wave in accordance with the angular frequency co.
Pcell*=Vdc*×Idc*+Vac*×Iac*×cos(φ−θ)/2  (3)

Equation (3) is obtained by integrating instantaneous power represented by the product of Iarm* in equation (1) and Vcell* in equation (2), over one cycle of the fundamental wave, that is, a period of ωt=0 to 2π.

On the other hand, in auxiliary converter200x, in a state in which a voltage in accordance with the reference output voltage command value Vcell* is output from output terminal T21under passage of current (−Iarm*) in a direction opposite to that in power converter100x, a power Paux* flowing into auxiliary converter200xis represented by the following equation (4) as average power in one cycle of the fundamental wave in accordance with the angular frequency co.
Paux*=−Vdc*×Idc*−Vac*×Iac*×cos(0−θ)/2  (4)

Here, power storage element C1included in power converter100xis charged and discharged by the instantaneous power flowing into power converter100x. Similarly, power storage element C2included in auxiliary converter200xis charged and discharged by the instantaneous power flowing into auxiliary converter200x. On the other hand, as can be understood from equation (3) and equation (4), the relation Paux*=−Pcell* holds between the average power Pcell* flowing into power converter100xand the average power Paux* flowing into auxiliary converter200x.

Because of this, for power storage elements C1and C2, when one of the power storage elements is charged, the other power storage element is discharged. Therefore, when a state in which the capacitor voltages Vcap1and Vcap2of power storage elements C1and C2are stable, specifically, a state in which voltage fluctuations are zero before and after one cycle of the fundamental wave, is a steady state, it is understood that the condition for reaching the steady state is Pcell*=0. Pcell*=0 is solved for equation (3) to yield the following equation (5).
Vdc*×Idc*=−Vac*×Iac*×cos(φ−θ)/2  (5)

In a steady state, the reference output voltage command value Vcell* and the reference current command value Iarm* are applied such that equation (5) holds. Typically, the reference output voltage command value Vcell* (Vdc*, Vac*, φ) and the reference current command value Iarm* (Idc*, Iac*, θ) are set to correspond to the voltage output by one converter cell in the actual MMC and the current flowing through the converter cell. That is, the DC current command value Idc*=Idcs in a steady state illustrated inFIG.5is set such that the above equation (5) holds.

Here, as described with reference toFIG.4, hysteresis converter300operates such that arm current Iarm is between the upper limit current command value Iarmh* (=Iarm*+ΔIarm) and the lower limit current command value Iarml* (=Iarm*−ΔIarm). Therefore, if the reference current command value Iarm* has the DC component Idc* at the start of operation, the actual arm current Iarm may fall significantly below the lower limit current command value Iarml* (in particular when Idc*>0) or may significantly exceed the upper limit current command value Iarmh* (in particular, when Idc*<0). As a result, an abrupt change of arm current Iarm may occur. Otherwise, a human-induced error in control may be triggered.

As described above, in the present embodiment, Idc* is set as shown inFIG.5and the phase θ=0 is set in equation (1), whereby supply of arm current by hysteresis converter300is started from the state of the reference current command value Iarm*=0, thereby preventing such an abrupt change of arm current Iarm.

As illustrated inFIG.5, the DC component Idc* of the reference current command value Iarm* gradually rises over time from t=0. In doing so, when power converter100xand auxiliary converter200xperform switching operation in a period until Idc* rises to a region where the above equation (5) is satisfied, one of power storage elements C1and C2is charged and the other is discharged, causing unbalance between the capacitor voltages Vcap1and Vcap2. If there is unbalance between the capacitor voltages Vcap1and Vcap2, a voltage difference occurs between output terminals T11and T21at a timing when ON of switching element Q11on the upper side in power converter100xand ON of switching element Q21on the upper side in auxiliary converter200xoverlap each other, and the voltage difference is superimposed on a voltage to be applied to reactor L1, which may influence the operation (current control) of hysteresis converter300.

Therefore, in testing system1aaccording to the present embodiment, a control process described below is executed in order to avoid the problem as described above and stabilize the operation in a transition period from the start of operation to a steady state.

FIG.9is a flowchart illustrating a control process in testing according to the first embodiment in testing system1aaccording to the present embodiment.

Referring toFIG.9, when testing of power converter100xin testing system1ais started, control circuit2executes a circulation step S1and a voltage control start step S2.

The circulation step S1includes step S1A of fixing switching element Q11(upper side) at OFF and fixing switching element Q12(lower side) at ON in power converter100x. The circulation step S1further includes step S1B of fixing switching element Q21(upper side) at OFF and fixing switching element Q22(lower side) at ON in auxiliary converter200x. For example, G11=G21=“0” and G12=G22=“1” can be set by setting CTRLon=“0” inFIG.6orFIG.7and setting GATEon=“1” inFIG.8. Alternatively, aside fromFIG.4,FIG.6orFIG.7, andFIG.8, a configuration for directly setting G11=G21=“0” and G12=G22=“1” at the circulation step S1may be provided.

The circulation step S1further includes step S1C of operating hysteresis converter300in accordance with the reference current command value Iarm* set from Iac* and Idc* that make a transition from the start of operation (1=0) in accordance withFIG.5. For example, at time t0, the process at step S1C is performed by changing HYSon from “0” to “1”. Thereafter, HYSon=“1” is kept throughout the testing of power converter100x. Steps S1A to S1C are depicted to be successively performed as separate steps, for the sake of convenience, but actually performed in parallel.

At the circulation step S1including steps S1A to S1C, arm current Iarm from hysteresis converter300circulates without charging power storage elements C1and C2through a path of terminal T31—output terminal T11—switching element Q12—line110—switching element Q22—output terminal T21-terminal T32.

In execution of the circulation step S1, control circuit2executes a determination step J1for transition to the voltage control start step S2. At the determination step J1, it is determined whether a DC component of arm current Iarm from hysteresis converter300rises to a determination value Ir. The determination value Ir is determined in advance to correspond to, for example, Idcs inFIG.5.

At the determination step J1, the DC current command value Idc* (the DC component of the reference current command value Iarm*) set in accordance withFIG.5as a DC component of arm current Iarm can be compared with the determination value Ir. Alternatively, the detection value (sensor CT1) of arm current Iarm in a phase in which the AC component of the reference current command value Iarm* is zero may be compared with the determination value Ir.

Until the DC component of arm current Iarm reaches the determination value Ir, the determination at the determination step J1is NO and the circulation step S1is continued. On the other hand, control circuit2executes the voltage control start step S2at a timing when the DC component of arm current Iarm reaches the determination value Ir (when the determination is YES at the determination step J1). For example, at a timing of time is inFIG.5, the determination at the determination step J1is YES. As described above, since HYSon=“1” is kept, output of arm current Iarm in accordance with reference current command value Iarm* by hysteresis converter300is thereafter continued.

The voltage control start step S2includes step S2A of starting voltage control of power storage elements C1and C2in power converter100xand auxiliary converter200xand step S2B of starting PWM control by power converter100xand auxiliary converter200x. For example, the process at steps S2A and S2B is performed by changing CTRLon inFIG.6orFIG.7from “0” to “1” with GATEon=“1” inFIG.8being kept.

At this timing, since there is no voltage difference between the capacitor voltages Vcap1and Vcap2of power storage elements C1and C2, current due to the voltage difference does not occur even when switching operation by the ON/OFF control of switching elements Q11and Q12in power converter100xand switching operation by the ON/OFF control of switching elements Q21and Q22in auxiliary converter200xare started.

In this state, output voltage command values Vcell1and Vcell2are set based on the voltage difference between the power storage element voltage command value Vcap* and the capacitor voltages Vcap1and Vcap2shown inFIG.5, whereby power storage elements C1and C2are gradually charged. Furthermore, in a steady state after the determination is YES at the determination step J2, switching operation of power converter100xis executed under passage of arm current Iarm in accordance with the reference current command value Iarm* in a steady state, in accordance with the reference output voltage command value Vcell* set to simulate the operation of the power converter100xalone in actual operation of the MMC.

After the steady state, the output voltage of power converter100xand the output voltage of auxiliary converter200xmay have different values in accordance with voltage control of power storage elements C1and C2, due to sensor errors and occurrence of loss.

At the voltage control start step S2, step S2A and step S2B may be started stepwise. That is, only the voltage control of power storage elements C1and C2may be started (step S2A), and PWM control by power converter100xand auxiliary converter200xmay be started (step S2B) after the capacitor voltages Vcap1and Vcap2are controlled to the power storage element voltage command value Vcap*. In this case, in a period until step S2B is executed, the reference output voltage command value Vcell* can be fixed to a certain value (for example, Vcell*=0).

As described above, in the testing system according to the first embodiment, voltage control of power storage elements C1and C2in accordance with the power storage element voltage command value Vcap* is started after the DC component of arm current Iarm rises to a steady state level. Because of this, the only active power that flows from the power output device (hysteresis converter)300into power converter100xand auxiliary converter200xis the power under voltage control of power storage elements C1and C2, so that the voltages of power storage elements C1and C2are prevented from becoming unbalance abruptly, and circuit operation at the start of testing can be stabilized.

Furthermore, auxiliary converter200xconnected to power converter100xto be tested through line110is arranged, and auxiliary converter200xis operated in the same manner as power converter100x, so that the difference between the output voltage of power converter100xand the output voltage of auxiliary converter200xis always substantially zero. As a result, the positive or negative pulse voltage produced by switching operation of hysteresis converter300is dominant in the voltage applied to reactor L1. Consequently, the operation of hysteresis converter300is stabilized to improve control stability of arm current Iarm flowing through power converter100x(test target), so that the testing of power converter100xcan be executed even more stably.

Second Embodiment

In a second embodiment, a control process in which a charging step S3of pre-charging power storage elements C1and C2is executed before the circulation step S1will be described.

FIG.10is a flowchart illustrating a control process in testing according to the second embodiment.

Referring toFIG.10, the charging step S3includes step S3A of turning OFF switching elements Q11and Q12in power converter100xand switching elements Q21and Q22in auxiliary converter200x. For example, the process at step S3A can be executed by fixing GATEon=“0” inFIG.8.

The charging step S3further includes step S3B of operating hysteresis converter300with the reference current command value Iarm*=0. Therefore, at the charging step S3, hysteresis converter300generates arm current Iarm such that the rise and the fall are repeated between the upper limit current command value Iarmh*=ΔIarm and the lower limit current command value Iarml*=−ΔIarm.

FIG.11shows an exemplary operation waveform diagram at the charging step S3.

Referring toFIG.11, the difference (absolute value) between the upper limit current command value Iarmh* and the reference current command value Iarm* (=0) is equal to the difference (absolute value) between the lower limit current command value Iarml* and the reference current command value Iarm* (=0). Therefore, since the upper limit current command value Iarmh* and the lower limit current command value Iarml* are symmetric in sign with respect to zero, arm current Iarm is controlled to AC current symmetric in sign with respect to zero (average value=0) in which a period of Iarm>0 and a period of Iarm<0 periodically appear.

FIG.12shows a circuit diagram illustrating the operation of power converter100xand auxiliary converter200xin a period of Iarm>0.

Referring toFIG.12, at the charging step S3, since switching elements Q11, Q12, Q21, and Q22are fixed at OFF, the path of arm current Iarm is ensured by the antiparallel diodes of the switching elements.

In a period of Iarm>0, arm current Iarm flowing from terminal T31toward output terminal T11flows from output terminal T21to terminal T32through a path of antiparallel diode D11of switching element Q11—power storage element C1—antiparallel diode D22of switching element Q22. As a result, power storage element C1is charged by arm current Iarm generated depending on the voltage difference (VDC−Vcap1) between the voltage (VDC) of power storage element C3of hysteresis converter300and the capacitor voltage Vcap1of power storage element C1.

FIG.13shows a circuit diagram illustrating the operation of power converter100xand auxiliary converter200xin a period of Iarm<0.

In a period of Iarm<0, arm current Iarm flowing from terminal T32toward output terminal T21flows from output terminal T11to terminal T31via antiparallel diode D21of switching element Q21—power storage element C2—antiparallel diode D12of switching element Q12. As a result, power storage element C2is charged by arm current Iarm generated depending on the voltage difference (VDC−Vcap2) between the voltage (VDC) of power storage element C3and the capacitor voltage Vcap2of power storage element C2.

Referring toFIG.11again, since the period of Iarm>0 and the period of Iarm<0 alternately appear, power storage element C1and power storage element C2are alternately charged substantially uniformly. In doing so, the inclination of arm current is proportional to (VDC−Vcap1)/L1in a period in which arm current Iarm rises, and the inclination of arm current is proportional to −(VDC−Vcap2)/L1in a period in which arm current Iarm lowers.

Therefore, with the capacitor voltages Vcap1and Vcap2rising, the inclination of arm current Iarm gradually decreases and the cycle of AC current also gradually increases. Then, when the capacitor voltage Vcap1or Vcap2rises to the voltage (VDC) of power storage element C3of hysteresis converter300, arm current Iarm becomes zero.

When this state is reached, hysteresis converter300is no longer able to charge power storage elements C1and C2at the charging step S3because switching elements Q31to Q34are not switched. In the example inFIG.11, when Vcap1=VDC is reached, charging of power storage elements C1and C2is terminated. At this point of time, the switching operation of hysteresis converter300is stopped in a state in which energy is stored in reactor L1. Because of this, a voltage difference corresponding to the stored energy occurs between the capacitor voltages Vcap1and Vcap2.

Referring toFIG.10again, in execution of the charging step S3, control circuit2executes the determination step J2for a termination condition of the charging step. For example, when the capacitor voltages Vcap1and Vcap2rise to the vicinity of the voltage (VDC) of power storage element C3or when a predetermined time passes since the start of the charging step S3, the determination can be set to YES at the determination step J2. On the other hand, the determination is NO at the determination step J2until the rise of the capacitor voltages Vcap1and Vcap2or the elapse of a predetermined time is detected.

Alternatively, at the determination step J2, extinction of arm current Iarm (Iarm=0) based on the termination of charging of power storage elements C1and C2shown inFIG.11may be detected. For example, when a state of |Iarm|<ε (ε≈0) continues for a predetermined time, control circuit2can detect Iarm=0 and the determination at the determination step J2can be set to YES. On the other hand, the determination at the determination step J2is NO until Iarm=0 is detected.

While the determination at the determination step J2is NO, a transition to the circulation step S1is awaited and the charging step S3is continued. On the other hand, when the determination at the determination step J2is YES, control circuit2executes the circulation step S1, the determination step J1, and the voltage control start step S2similar to those in the first embodiment (FIG.9). That is, the operation of testing system1aafter the determination at the determination step J2is YES is similar to that in the first embodiment and a detailed description thereof will not be repeated. In the second embodiment, a modification is necessary such that the power storage element voltage command value Vcap* shown inFIG.5is set to a value equivalent to DC voltage VDC, at time is when voltage control is started.

As described above, in the control process in testing in the testing system according to the second embodiment, since the charging step S3is added, power storage elements C1and C2are charged to a substantially uniform voltage in advance when the process proceeds to the voltage control start step S2after the circulation step S1is finished. Accordingly, while unbalance between the capacitor voltages Vcap1and Vcap2of power storage elements C1and C2is prevented, the time taken for the capacitor voltages Vcap1and Vcap2of power storage elements C1and C2to reach the reference output voltage command value Vcell* can be reduced after the start of voltage control.

In particular, in the voltage control after the voltage control start step S2(FIG.4), power storage elements C1and C2are gradually charged while charge and discharge are repeated. It is therefore understood that, with the voltage control alone, it takes some time to raise the capacitor voltages Vcap1and Vcap2to the reference output voltage command value Vcell* from a state of the capacitor voltage Vcap1=Vcap2=0.

In contrast, in the charging step S3described above, power storage elements C1and C2are charged without a period in which power storage elements C1and C2are discharged. Therefore, it is understood that since the process can pass through the charging step S3, the time taken to charge power storage elements C1and C2can be reduced compared with charging with the voltage control alone. In this way, in the process control in testing according to the second embodiment, testing can be performed more efficiently because the time from the start of testing to reach a steady state is reduced.

Third Embodiment

In a third embodiment, a modification of the charging step S3described in the second embodiment will be described.

As described with reference toFIG.11, after the charging step S3is finished in the second embodiment, a voltage difference equivalent to the stored energy in reactor L1occurs between the capacitor voltages Vcap1and Vcap2of power storage elements C1and C2. In the third embodiment, the charging step S3for suppressing such a voltage difference will be described.

FIG.14is a flowchart illustrating a control process in testing according to the third embodiment.

Referring toFIG.14, in the third embodiment, control circuit2also executes the charging step S3prior to the circulation step S1illustrated inFIG.9. The charging step S3includes step S3A similar to that inFIG.10and step S3C of operating hysteresis converter300with a constant duty. That is, at the charging step S3according to the third embodiment, step S3C is executed instead of step S3B of operating hysteresis converter300with the reference current command value Iarm*=0.

At step S3C, control circuit2controls hysteresis converter300such that a first period in which switching elements Q31and Q34are turned ON and switching elements Q32and Q33are turned OFF and a second period in which switching elements Q32and Q33are turned ON and switching elements Q31and Q34are turned ON in certain switching cycles are alternately provided in accordance with a certain ratio of period lengths (duty) in certain cycles.

For example, the ratio of the length T1of the first period to the length T2of the second period (T1:T2) is set to a certain value in accordance with the ratio of capacitances of power storage elements C1and C2(C1:C2) (T1:T2=C1:C2). For example, the process at step S3C can be performed by preliminarily generating a signal pattern specific to the charging step S3of gate signals G11, G21, G22, and G22for turning ON and OFF of switching elements Q11, Q21, Q22, and Q22according to a switching pattern in accordance with the constant duty.

FIG.15shows an exemplary operation waveform diagram at the charging step S3according to the third embodiment.

Referring toFIG.15, when C1=C2, T1:T2=1:1, that is, a duty of 50(%) is set. As a result, the first period in which hysteresis converter300outputs a positive voltage pulse between terminal T31and terminal T32to raise arm current Iarm (Q31and Q34are turned ON and Q32and Q33are turned OFF) and a second period in which hysteresis converter300outputs a negative voltage pulse between terminal T31and terminal T32to lower arm current Iarm (Q32and Q33are turned ON and Q31and Q34are turned OFF) are alternately provided in time lengths of 1:1.

In the operation example inFIG.15, initial phase adjustment is performed to adjust the length of the initial first period (the length half the normal one) such that arm current Iarm is symmetric in sign, from arm current Iarm=0 (t=0). Consequently, arm current Iarm attains a waveform symmetric in sign at the start of testing (t=0).

As a result, a period of arm current Iarm>0 in which power storage element C1is charged through the current path inFIG.12and the capacitor voltage Vcap1rises and a period of arm current Iarm<0 in which power storage element C2is charged through the current path inFIG.13and the capacitor voltage Vcap2rises are alternately provided in equal time lengths. Consequently, power storage elements C1and C2are alternately charged equally.

Arm current Iarm gradually attenuates with the rise of the capacitor voltages Vcap1and Vcap2because hysteresis converter300performs switching operation with a fixed switching frequency of switching elements Q31to Q34. Therefore, at last, the difference between the voltage VDC (FIG.12,FIG.13) of power storage element C3and the capacitor voltages Vcap1and Vcap2disappears, and the stored energy in reactor L1decreases when charging is terminated. Consequently, the voltage difference between the capacitor voltages Vcap1and Vcap2at the end of charging can be significantly reduced compared with the second embodiment (FIG.11).

FIG.16shows an operation waveform diagram of another example in which the charging step is executed without performing the initial phase adjustment illustrated inFIG.15.

Referring toFIG.16, when the initial phase adjustment is not executed, arm current Iarm is not symmetric in sign immediately after the start of the charging step S3, and therefore charging proceeds disproportionately in one of power storage element C1or C2. As a result, unbalance is caused to some extent between the capacitor voltages Vcap1and Vcap2.

However, since hysteresis converter300is subjected to constant duty control, arm current Iarm attenuates with the progress of charging of power storage elements C1and C2. Accordingly, the voltage applied to reactor L1decreases, and the voltage difference between the capacitor voltages Vcap1and Vcap2also gradually decreases.

Consequently, at the end of charging in the charging step S3, there is no significant difference in voltage and current behavior betweenFIG.15with the initial phase adjustment andFIG.16with no initial phase adjustment. That is, it is understood that the initial phase adjustment in starting the constant duty control is not essential at the charging step according to the third embodiment.

Referring toFIG.14again, control circuit2executes the determination step J2for termination of the charging step when the charging step S3is executed. As shown inFIG.15andFIG.16, at the charging step S3in the third embodiment, extinction of arm current Iarm (Iarm=0) is also detected at the end of charging of power storage elements C1and C2. The determination step J2inFIG.14therefore may also be a process similar to the determination step J2inFIG.12. In the third embodiment, a modification is also necessary such that the power storage element voltage command value Vcap* shown inFIG.5is set to a value equivalent to the DC voltage VDC, at time is when voltage control is started.

Also inFIG.14, the charging step S3is continued while the determination at the determination step J2is NO, but when the determination at the determination step J2is YES, control circuit2executes the circulation step S1, the determination step J1, and the voltage control start step S2similar to those in the first embodiment (FIG.9). InFIG.14(third embodiment), the operation of testing system1aafter the determination at the determination step J2is YES is similar to that in the first embodiment and a detailed description thereof will not be repeated.

As described above, in the control process in testing with the testing system according to the third embodiment, in addition to the effect described in the second embodiment, unbalance between the capacitor voltages Vcap1and Vcap2can be suppressed at the end of charging of power storage elements C1and C2at the charging step S3. Consequently, the operation of voltage control start can be further stabilized.

Finally, modifications of the configuration of testing system1ashown inFIG.1will be described.

FIG.17is a circuit diagram illustrating a first modification of the configuration of the testing system including the testing device according to the present embodiment.

Referring toFIG.17, in a testing system1baccording to the first modification, line110is arranged to connect the positive electrodes of power storage element C1of power converter100xand power storage element C2of auxiliary converter200x. This configuration can also ensure a path of arm current Iarm, including power converter100xto be tested and auxiliary converter200x. The configuration of the other part of testing system1bis similar to that of testing system1a(FIG.1) and a detailed description will not be repeated.

In testing system1binFIG.17, the circulation step S1can be implemented by turning ON switching element Q11and turning OFF switching element Q12in power converter100x, and turning ON switching element Q21and turning OFF switching element Q22in auxiliary converter200x. At the charging step S3in the second and third embodiments, power storage element C2is charged in a period of Iarm>0 and power storage element C1is charged in a period of Iarm<0 by turning OFF switching elements Q11and Q12in power converter100xand turning OFF switching elements Q21and Q22in auxiliary converter200x.

Alternatively, as shown inFIG.18, the configuration of the power converter to be tested and the auxiliary converter is also not limited to the example inFIG.1.

FIG.18is a circuit diagram illustrating a second modification of the configuration of the testing system including the testing device according to the present embodiment.

Referring toFIG.18, a testing system1caccording to the second modification differs in that it includes a power converter100yand an auxiliary converter200yinstead of power converter100xand auxiliary converter200xin the half-bridge construction shown inFIG.1andFIG.17.

Power converter100yto be tested further includes switching elements Q13and Q14connected in series, in addition to the configuration of power converter100x(FIG.1). The series connection of switching elements Q13and Q14is connected in parallel with power storage element C1and the series connection of switching elements Q11and Q12. Power converter100yhas a full-bridge construction. Switching elements Q13and Q14are driven ON and OFF by gate drive circuits Gd13and Gd14, in response to gate signals G13and G14from control circuit2. Switching elements Q13and Q14correspond to “third and fourth main switching elements”.

Similarly, auxiliary converter200yfurther includes switching elements Q23and Q24connected in series, in addition to the configuration of auxiliary converter200x(FIG.1). The series connection of switching elements Q23and Q24is connected in parallel with power storage element C2and the series connection of switching elements Q21and Q22. Switching element Q23and Q24are driven ON and OFF by gate drive circuits Gd23and Gd24, in response to gate signals G23and G24from control circuit2. Switching elements Q23and Q24correspond to “third and fourth auxiliary switching elements”.

Line110is arranged to connect the connection node of switching elements Q13and Q14to the connection node of switching elements Q23and Q24to ensure a path of arm current Iarm, including power converter100yto be tested and auxiliary converter200y. The configuration of the other part of testing system1cis similar to that of testing system1a(FIG.1) and a detailed description will not be repeated.

In testing system1cinFIG.18, the circulation step S1can be implemented by turning ON switching elements Q12and Q14and turning OFF switching elements Q11and Q13in power converter100yand turning ON switching elements Q22and Q24and turning OFF switching elements Q21and Q23in auxiliary converter200y. At the charging step S3in the second and third embodiments, power storage elements C1and C2connected in series can be charged by full-wave rectification of arm current Iarm, throughout the period of Iarm>0 and the period of Iarm<0, by turning OFF switching elements Q11to Q14in power converter100xand turning OFF switching elements Q21to Q24in auxiliary converter200y.

In each of testing systems1band1cshown inFIG.17andFIG.18, auxiliary converter200x,200yconnected to power converter100x,100yto be tested through line110is arranged, and auxiliary converter200x,200yis operated in the same manner as power converter100x,100y, whereby the difference between the output voltage of power converter100x,100yand the output voltage of auxiliary converter200x,200ycan be always substantially zero. Consequently, the operation of hysteresis converter300can be stabilized, and the control stability of arm current Iarm flowing through power converter100x,100y(test target) can be improved, thereby stabilizing the operation of testing system1b,1c, in the same manner as described in the first embodiment.

In this way, in the testing system according to the present embodiment, each of the power converter to be tested and the auxiliary converter includes a series connection of switching elements and a power storage element connected in parallel with the series connection and may have any circuit configuration as long as a current path that does not include the power storage element can be formed at the circulation step.

A configuration including hysteresis converter300and reactor L1has been described as an example of “power output circuit” for outputting arm current Iarm (test current) that simulates actual operation of power converter100xto be tested. However, the “power output circuit” may have any configuration that has a function of outputting arm current Iarm in accordance with the reference current command value Iarm*.

For example, the “current output circuit” may be formed using a current source with high control responsivity, instead of hysteresis converter300and reactor L1. Also in this case, a charging current path for power storage elements C1and C2with antiparallel diodes can be formed by fixing the switching elements at OFF in power converter100x,100yand auxiliary converter200x,200yin a state in which the current source outputs AC current symmetric in sign with respect to zero. That is, the charging step S3in the second and third embodiments can be implemented similarly.

Embodiments disclosed here should be understood as being illustrative rather than being limitative in all respects. The scope of the present disclosure is shown not in the foregoing description but in the claims, and it is intended that all modifications that come within the meaning and range of equivalence to the claims are embraced here. These novel embodiments can be carried out in other various modes and susceptible to a variety of omission, replacement, and changes without departing from the spirit of the disclosure. These embodiment and modifications thereof are embraced in the scope and spirit of the disclosure and embraced in the range of equivalence to the disclosure recited in the claims.

REFERENCE SIGNS LIST