System and method for operating a switching transistor

In accordance with an embodiment, a method of operating a switching transistor includes turning-off the switching transistor by transferring charge from a gate-drain capacitance of the switching transistor to a charge storage device, and turning-on the switching transistor by transferring charge from the charge storage device to a gate of the switching transistor. Turning off the switching transistor includes hard-switching and turning-on the switching transistor includes soft-switching.

TECHNICAL FIELD

The present invention relates generally to an electronic device, and more particularly, to a system and method for operating a switching transistor.

BACKGROUND

Switched-mode circuits, including switched-mode power supplies and motor controllers, are pervasive in many electronic applications from computers to automobiles. Generally, voltages within a switched-mode power supply system are generated by performing a DC-DC, DC-AC, and/or AC-DC conversion by operating a switch coupled to an inductor or a transformer. Switched-mode power supplies are usually more efficient than other types of power conversion systems because power conversion is performed by controlled charging and discharging a low loss component, such as an inductor or transformer, thereby reducing energy lost due to power dissipation across resistive voltage drops. Similarly, switched-mode motor controllers may be used to efficiently commutate DC brushless motors with low losses in the driving circuitry.

With respect to implementing a switched-mode circuit, specialized driving circuitry is used to efficiently drive a switching transistor coupled to the various magnetic components. Such circuitry may be configured to provide switching signals at appropriate speeds and voltage levels. These voltage levels may be established, for example, by using external DC supply voltages, voltage regulators, level shifters, charge pumps and other circuits to ensure that the switching transistor is turned-on and off. Each time the driving circuitry drives the switching transistor through one switching cycle, power may be consumed due to the charging and discharging of the input capacitance of the switching transistor.

SUMMARY

In accordance with an embodiment, a method of operating a switching transistor includes turning-off the switching transistor by transferring charge from a gate-drain capacitance of the switching transistor to a charge storage device, and turning-on the switching transistor by transferring charge from the charge storage device to a gate of the switching transistor. Turning off the switching transistor includes hard-switching and turning-on the switching transistor includes soft-switching.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The present invention will be described with respect to preferred embodiments in a specific context, namely a system and method for driving switching MOSFET and extracting energy from the switching MOSFET for further reuse. Embodiments of the present invention may also be applied to various systems that utilize switching transistors, such as switched-mode power supplies (SMPS) and various H-bridge drivers. Embodiments may also be directed toward driving capacitive gated devices such as super junction MOSFETs, IGBTs, gallium nitride (GaN) MOSFET gate-injection transistors, GaN high electron mobility transistors (HEMT).

In an embodiment of the present invention, the energy used to drive the gate or control node of a switching transistor is harvested from the gate-drain capacitance of the switching transistor itself. Accordingly, during nominal operation of the all or part of the energy used to drive the gate of the switching transistor may be obtained from charging and discharging of the switching transistor instead of or in additional to power supplied by the local power supply of the gate driver.

During operation of an embodiment gate driver, charge entering the gate-drain capacitance and/or gate-source capacitance of the switching transistor is stored as the switching transistor is being turned-off. As the gate of the switching transistor is pulled low and as the drain voltage of the switching transistor increases in voltage, current flowing from the gate-drain capacitance and/or gate-source capacitance of the switching transistor is used to magnetize an inductor coupled to the gate of the switching transistor. This energy stored in the inductor may be transferred to a capacitor or other energy storage device. When the switching transistor is turned-on again, the energy stored in the capacitor or other energy storage device is used to charge the gate of the switching transistor in order to turn it on. When a zero-voltage or valley switching scheme is used, that is, when the switching transistor is turned-on when the drain voltage is zero or a low voltage, the amount of energy harvested when the switching transistor is turned off may exceed the amount of energy needed to charge the gate-source capacitance of the switching transistor in order to turn it on. Accordingly, this harvested energy may be used to power the gate driver itself and/or other circuits.

In an embodiment of the present invention, a resonant gate driver circuit is configured to extract energy from a switching transistor, typically a MOSFET. However, the method is applicable to any capacitive gated devices. During a turn-off event of the switching transistor, energy is stored across a gate-drain capacitor while a drain node is charged. During the turn-off event, a gate voltage is discharged by connecting it to an inductor via a first switch. The energized inductor transfers its energy to a storage capacitor coupled to it. The first switch is turned-off after one-half of the resonant period to allow transfer of energy to the storage capacitor. When the gate voltage is discharged, the storage capacitor is isolated from the gate of the switching transistor via the first switch, until it is time for next turn-on event. Until the next turn-on event occurs, a second switch connected between the gate and a reference terminal of the switching transistor is activated and kept on to discharge residual charge across gate to the reference terminal. During the turn-on event, the second switch is turned-off and the first switch is turned-on. The harvested energy stored in the storage capacitor is transferred via the inductor to charge the gate of the switching transistor. The amount of time needed to transfer energy across an LC resonant tank formed by the inductor and a combination of the storage capacitor and a gate-source capacitor is controlled by the resonant period of the tank. The first switch is turned-off after one half of the resonant period of the LC resonant tank. A third switch coupled between a driver power supply and the gate node of the switching transistor is turned-on to replenish energy loss during transfer and pull the gate to the driver power supply.

FIG. 1illustrates a block diagram of a fly back converter100that includes a switching transistor M coupled to a primary winding ground of transformer106. During operation, switching transistor M is turned-on and off via a switching driver102and magnetizes the primary winding of transformer106. When switching transistor M is turned-off, current induced in the secondary winding of transformer106charges capacitor C and provides power to a load represented by load impedance ZLvia rectifying diode D. Controller104provides a pulse-width modulated signal to switching driver102and may be used to control the output voltage and/or output current for fly back converter100. Over the course of switching transistor M on and off, power is transferred from switching driver102each time the gate of switching transistor M is charged. Hence, in some conventional switching drivers, the total power dissipated by switching driver102is proportional to the switching frequency, as well as the gate capacitance of transistor M. In some embodiments, fly back converter100includes isolated coupler105that provides a feedback signal to controller104based on the output voltage and/or output current of fly back converter100. In various embodiments, an isolated coupler105may be implemented using an opto-coupler, magnetic transformer, capacitive coupling circuit, or other isolating coupler circuit known in the art.

FIG. 2aillustrates an embodiment gate driving system200that includes a resonant gate driver circuit210coupled between the gate of switching transistor M0and capacitor Cin. As shown, the resonant gate driver circuit210is implemented as an H-bridge circuit having switches M1, M2, M3and M4and inductor Lr coupled across the H-bridge circuit. Capacitors CGD, CGS and CDS coupled to switching transistor M0represent the parasitic gate-drain, gate-source and drain-source capacitances of switching transistor M0, respectively. As shown, switches M1, M2, M3and M4are implemented using NMOS transistors. Alternatively, switches M1, M2, M3and M4may be implemented using other transistor types or other switching structures.

During operation, energy is harvested from the gate-drain capacitance CGD of switching transistor M0and stored in capacitor Cin when switching transistor M0is turned off using a hard switching topology, and energy is transferred from capacitor Cin to the gate of switching transistor M0when switching transistor M0is turned on. In some embodiments, energy may be harvested from the gate-source capacitance CGS as well.

Various types of switching topologies are used to drive switching transistors on or off in a switched mode power supply system. Two of these topologies include hard switching and soft switching. During a hard switching turn on event, a voltage equal to at least the supply voltage is applied across the transistor and current increases through the transistor. An overlap of the voltage and the current causes a power loss during a hard switching turn on. During the hard switching turn off, the current through the transistor decreases and the voltage across the output of the transistor increases. A similar overlap of voltage and current during turn off causes a switching power loss. Besides switching losses, hard switching topology is associated with electro-magnetic-interference (EMI) due to high dv/dt and di/dt and device stress.

A soft switching topology is used to improve some of the issues observed in hard switching. Soft switching involves switching of the transistor after an output voltage or current reaches zero value. Soft switching may be implemented using a zero voltage switching (ZVS) topology or a zero current switching (ZCS) topology during turning on or off a transistor. Zero voltage switching is used to reduce switching loss during turn on where the gate voltage is applied after the output voltage of the transistor is brought to a minimum or zero value. A zero current switching is used during turn off and the gate voltage is discharged after the drain current of the transistor reached a minimum or zero value.

In an embodiment, switching transistor M0is turned off by turning on transistor M4, which discharges the gate-source capacitance CGS of switching transistor M0via inductor Lr. As switching transistor M0is being turned off, the drain-source voltage VDS increases across switching transistor M0and charges the gate-drain capacitance CGD. In order to prevent the gate voltage VGSfrom being pulled up via the gate-drain capacitance CGD, charge continues to be pulled from charged gate-drain capacitance CGD via inductor Lr, and inductor Lr is energized during this discharge. In some embodiments, switch M4is closed for one-quarter of the resonant period to discharge the gate voltage. This resonant period is based on the product of inductor Lr and the gate capacitance of switching transistor M0or any external capacitor connected across the gate and source of the switching transistor M0. Next, the switch M2and the switch M3are closed, thereby allowing inductor Lr to provide a charging current to capacitor Cin, while ensuring that the gate voltage of the switching transistor is held at ground. In some embodiments, switch M3may remain open to allow the energy of the inductor to be transferred to capacitor Cin via the body diode of switch M3. It should be understood that charging current across the body diode of switch M3when the switch remains open may result in some power loss.

The stored energy in capacitor Cin may be utilized when turning-on switching transistor M0by closing switch M3and opening switch M2. Accordingly, the energy stored in capacitor Cin is transferred to the gate of switching transistor M0via inductor Lr in order to charge the gate of switching transistor M0. In some embodiments, after one-half of the resonant period, switch M3is opened and switch M1is closed to allow energy from the capacitor Cin to be transferred to gate-source capacitance CGS. Switch M1also ensures that the gate of the switching transistor is held at the same voltage as Cin when switching transistor M0is turned-on.

In some embodiments, more energy may be transferred from gate-drain capacitance CGD and gate-source capacitance CGS of the switching transistor M0to capacitor Cin than is transferred from the capacitor Cin to the gate of switching transistor M0. Such a condition may arise, for example, when VDS during turn-on is less than the resulting VDS immediately after the switching transistor M0is turned-off. In some embodiments, a valley switching scheme and/or zero-voltage switching schemes known in the art may be used to satisfy such a condition.

In embodiments where more energy is transferred from gate-drain capacitance CGD and gate-source capacitance CGS of switching transistor M0to capacitor Cin than is transferred from capacitor Cin to the gate of switching transistor M0, the voltage across capacitor Cin continues to increase as the capacitor receives charge from gate-drain capacitance CGD and gate-source capacitance CGS of switching transistor M0. In order to prevent the voltage across the various circuit components from exceeding their maximum rated voltages, zener diode216is used to clamp the voltage across capacitor Cin. A diode218coupled to supply node VCC allows pre-charging of capacitor Cin during startup. In various embodiments, the zener clamp voltage of zener diode216is greater than VCC. In alternative embodiments, other known clamping circuits may be used.

FIG. 2aalso illustrates a switch controller230for generating controlling signals for switches M1, M2, M3and M4. The signal S1controls the switch M1, the signal S2controls the switch M2, the signal S3controls switch M3, and the signal S4controls switch M4. The control signal going high indicates a turn-on event of the switch and the control signal remaining low indicates a turn-off event of the switch. The amount of time that switches M3and M4are turned-on is predetermined and based on the values of inductor Lr, gate-source capacitance CGS and capacitor Cin. In the present embodiment, the switches are implemented by an n-channel MOSFET. Alternatively, other types of transistors or devices may be used, for example, a p-channel MOSFET, a BJTs, or a JFET, or other device types depending on the particular embodiment and specifications. In such alternative embodiments, the behavior of switch controller230may be modified to provide suitable signals to the various alternative transistor types.

In various embodiments, an energy transfer from the capacitor Cin to the gate-source capacitor CGS via the inductor Lr is used to turn on the switching transistor. The switching transistor turns on by having gate-source capacitor CGS charged thereby increasing the gate to source voltage. In an embodiment, a rate of change of voltage of a gate to source node of the switching transistor may be controlled by adjusting a value of the inductor Lr coupled to the gate of the switching transistor. A combination of the value of the inductor Lr and the gate-source capacitance CGS controls the rate of change of voltage of the gate to source node during the turn on event of the switching transistor.

FIG. 2billustrates a waveform diagram showing various signals within the embodiment gate driving system200that shows timing information in the horizontal axis and voltage and current information in the vertical axis. The waveform labeled VCincorresponds to the voltage across capacitor Cin, waveform labeled VDScorresponds to a voltage across a drain and a source of the transistor M0, the waveform labeled VGScorresponds to a gate to source voltage of the transistor M0, and the waveform labeled ILRcorresponds to the current flowing through the inductor Lr. The waveform diagram inFIG. 2balso describes various currents and voltages for a pre-charge and a non-pre-charge mode of gate driving during turn-off event of the transistor M0. In a pre-charge mode driving, the inductor Lris pre-charged by having an overlap of the switch signals S2and S3. In the non-pre-charge mode driving, there is no overlap of the switch signals S2and S3, as shown in the waveform during transistor turn-on event. In a pre-charge mode driving, the current in the inductor is higher and higher energy is built up. Accordingly, the charging of VCGSis faster than non-pre-charge mode driving.

FIG. 2billustrates a waveform diagram of various signals during the switching transistor M0turn-off event for both pre-charge and non-pre-charge driving conditions. The duration of pre-charge is indicated by the overlap of the signals S1and S4. The switching transistor M0is initially turned-on and gate voltage VGSis at a level higher than gate threshold voltage. The VGSis held high by having signal S1high; indicating that switch M1is closed. Signal S4goes high first and provides a pre-charge path for the inductor via switch M1, inductor Lr and switch M4. Pre-charging is stopped when signal S1goes low after some time. The inductor current is supplied by the body diode of switch M2and VGSgoes below ground reference until signal S2goes high. This closes the switch M2and VGSis held at ground reference. The inductor current re-circulates back to Vcin via switch M2, inductor Lr and switch M3. Accordingly, voltage Vcin increases during this time. The waveforms for non-pre-charge driving shows that signal S1and signal S4are non-overlapping. The inductor current ILR starts building up when signal S4goes high, thereby closing switch M4. The VGSis held high as the transistor is on at the beginning. The voltage VGSstarts discharging when signal S4goes high and it is discharged via inductor Lr to ground reference terminal. The switch M4is opened when the signal S4goes low and VDSstarts switching when VGSfalls below MOSFET gate threshold voltage. Signal S2goes high after that and causes the inductor current to recirculate back to capacitor Cin via body diode of switch M3.

As shown inFIG. 2c, the inductor current ILRstarts at zero, signal S2is high indicating that switch M2is closed, and signals S1, S3and S4are low indicating switches M1, M3and M4are open respectively. The voltage across capacitor Cin is denoted by Vcin and is shown at 10 V, and voltage VGSat the gate of the switching transistor M0is about 0 V, indicating that the switching transistor M0is turned-off. Next, the signal S3goes high thereby closing switch M3. During this time, switch M2and M3are closed and this condition pre-charges the inductor Lr and current builds up across the inductor, as shown in the current waveform ILR. The voltage Vcin shows a dip during this time, as the charging current is being provided by capacitor Cin. The signal S2then goes low, indicating that switch M2is open and that VGSis charged to Vcin. The signal S3goes low indicating that switch M3is opened, and the signal S1goes high indicating that switch M1is closed. This causes the excess inductor current to circulate back to capacitor Cin. This is shown by Vcin going back high after dipping low for a short while. Switch M4remains open during this time as indicated by a low S4signal.

As shown inFIG. 2c, the waveform with non-pre-charge driving condition indicates signals S2and S3are non-overlapping. The signal S2remains high at the beginning and indicates a low VGSvoltage at the gate of the switching transistor M0. After some time, signal S2goes low to open switch M2and signal S3goes high to close switch M3. This causes the inductor to be charged as shown in current build up in the waveform ILR. The Vcin dips during this time to indicate the energy being taken from capacitor Cin. When the signal S3goes low and signal S1goes high, the inductor current re-circulates through the switch M1. At this time, Vcin stops dipping. The non-pre-charge method consumes less energy than the pre-charge method in some embodiments.

FIG. 3illustrates another embodiment of a switching gate driver system300that includes a high-side gate driver302and a low side gate driver304. In some embodiments, the low side gate driver304may also provide power to an auxiliary system306referenced to ground. The low side gate driver304is similar to switching gate driving system200illustrated inFIG. 2a, and includes a storage capacitor CLS to store energy harvested from a switching transistor M_LS. A resonant inductor Lr1is used to transfer energy from the storage capacitor CLS to the gate of the switching transistor M_LS in a manner similar to that is described above with respect toFIGS. 2ato2c.

The high-side gate driver302is similar to the low side driver304and includes a storage capacitor CHS coupled between a driver power supply and a source of the switching transistor M_HS. An inductor Lr2is used to transfer energy from the storage capacitor CHS to the gate of the switching transistor M_HS. A diode D_HS is used as bootstrap diode to provide power to the high side gate drivers. Similarly, an optional diode D is connected in series with the power supply VCC to block current flow to the supply during energy harvesting in the low side driver.

The embodiment switching gate driver system300shown inFIG. 3may be used to provide switching for systems that utilize both high-side and low side switches such as power supplies and motor controllers. In some embodiments, an auxiliary circuit represents circuitry that may be locally powered by energy harvested from the gain-drain capacitance CGD_LS of the low-side transistor M_LS. Examples of such circuitry may include, for example, other circuits and systems that support switching gate driver system300, such as controllers, bias circuitry, PWM generators, and the like. In some embodiments, switching gate driver system300may be used to provide power to an isolated portion of a system, such as the primary side of a switched mode power supply having a secondary side controller.

FIG. 4illustrates a further embodiment of the switching gate driver system400that includes a gate driver circuit401coupled to a gate of switching transistor M0. The structure of the gate driver circuit401is similar to the structure of the gate driver shown inFIG. 2a, with the exception of an interface between the H-bridge circuit and a power supply VCC. As shown inFIG. 4, the driver power supply is coupled to the power supply VCC via a pass switch420. This pass switch420is controlled by a comparator418, which functions as a charge storage monitoring circuit and compares voltage at capacitor Cin to a minimum reference voltage. In some embodiments, the minimum reference voltage is generated by a resistor416and a zener diode414. When the voltage across the capacitor Cin falls below the voltage level set by zener diode414, comparator418turns-on pass switch420and the voltage across capacitor Cin is pulled to the power supply VCC. In alternative embodiments, the minimum reference voltage may be generated using many different methods such as using external voltage source or a voltage divider, or an on-chip voltage reference. During energy extraction, voltage at capacitor Cin continues to increase when the harvested energy exceeds the energy dissipated by the gate driver401. Accordingly, zener diode412, which is coupled in parallel to capacitor Cin, is used to clamp the voltage across capacitor Cin such that extra energy is dissipated across zener diode412.

FIG. 5aillustrates another embodiment switching gate driver system500that is configured to drive a gate of a switching transistor M0with a resonant inductor Lr and a combination of a storage capacitor CS and a gate-source capacitor CGS. The resonant inductor Lr is coupled to the gate of the switching transistor M0via a switch Ms3, as well as to the storage capacitor CS to form a resonant LC tank when switch Ms3is closed. As shown, the gate driver system500includes a switch Ms1that is used to pull the gate of the switching transistor M0to a driver supply voltage Vcc to turn-on switching transistor M0. It also includes a switch Ms2to pull the gate of the switching transistor M0to a reference voltage to turn-off switching transistor M0. In some embodiments, by selectively activating and deactivating the resonant condition of the LC tank, the gate of the switching transistor M0can be pulled high or low to turn it on or off. In various embodiments, resonant inductor Lr may be implemented using discrete and/or integrated inductors and storage capacitor CS may be implemented using discrete and/or integrated capacitors. In further embodiments, additional capacitance may be coupled in parallel with gate-source capacitance CGS of switching transistor M0.

In an embodiment, switch Ms3is implemented using a series combination of n-channel MOSFETs M3aand M3bhaving their body diodes facing in opposite directions. Switches Ms1, Ms2and Ms3are implemented using n-channel MOSFETs. Alternatively, other types of transistors or devices may be used, for example, p-channel MOSFETs, BJTs or JFETs, or other device types depending on the particular embodiment and its specifications.

As shown inFIG. 5a, a switching signal generator520produces switching signals S1, S2and S3that drive switches Ms1, Ms2and Ms3, respectively. A high-level signal for S1indicates a closing of switch Ms1and a low-level signal for S1indicates an opening of switch Ms1. This is true for signals S2and S3controlling switches Ms2and Ms3respectively. Alternatively, switching signals S1, S2, and S3may be active low, for example, in embodiments that utilize p-channel MOSFETs for H-bridge switching transistors.

Switching transistor M0is first turned-on by closing switch Ms1while the switch Ms2and the switch Ms3remain open. The switch Ms1pulls the gate voltage of the switching transistor M0to the driver power supply Vcc, thereby turning it on.

Next, the switching transistor M0is turned-off by opening the switch Ms1and by closing switch Ms3to activate an LC tank formed by an inductor Lr and a combination of storage capacitor CS and the capacitance seen at the gate of switching transistor M0. Energy stored in gate-source capacitance CGS and gate-drain capacitance CGD during the turn-off of switching transistor M0is harvested by transferring energy from the input capacitance of switching transistor M0to storage capacitor CS via inductor Lr and switch Ms3. In some embodiments, switch Ms3is turned-on for one-half of a resonant period of the resonant LC tank formed by inductor Lr and the capacitance at the gate of the switching transistor M0. During this period, the energy is transferred and transfer stops when the switch Ms3is opened. Subsequent to this period, the gate voltage of the switching transistor M0may further be discharged by closing switch Ms2.

In order to turn-on switching transistor M0, switch Ms3is again turned-on to transfer charge from storage capacitor CS to the gate of switching transistor M0. After one-half of a resonant period, switch Ms3is opened and switch Ms1is closed to provide additional charge to pull the gate of the switching transistor M0to driver power supply Vcc. As switching transistor M0is turned on, the energy extracted from gate-drain capacitance GGD during turn-off and stored in storage capacitor CS is reused.

In embodiments, a net positive energy may be harvested by turning-on the switching transistor M0at a voltage that is less than a final settling voltage of the transistor, for example, using valley switching and/or zero voltage switching (ZVS). In some embodiments, ZVS and/or valley switching is performed by ensuring that the drain node of the switching transistor M0is below a particular voltage and/or has reach a local minimum when transistor M0is turned-on. In other embodiments, the switching transistor M0is turned-on after the voltage across the output of the switching transistor M0is below a predetermined threshold.

In another embodiment, the switching transistor is turned-on under ZVS and/or valley switching conditions, there may be enough excess energy stored in storage capacitor CS when switching transistor M0is turned-off, that this excess energy may be used to power other portions of the driver system. This may occur when the voltage of CGS is higher than the sum of VCC and the forward voltage of the body diode of the transistor used to implement the switch Ms1, after storage capacitor CS has transferred its extracted energy during turn on. In this case, the excess energy is transferred to an energy storage (not shown) coupled to VCC. In some embodiments, switching gate driver system500may not need its own power supply after the first charging of the gate of the switching driver is complete.

FIG. 5billustrates a waveform diagram showing various signals within embodiment switching gate driving system500with a timing information in the horizontal axis and voltage and current information in the vertical axis. The waveform labeled VS1, VS2, and VS3correspond to the switch control signals for switches Ms1, Ms2and Ms3respectively, the waveform labeled IS1corresponds to current going through switch Ms1, the waveform labeled ILRcorresponds to current going through inductor Lr, the waveform labeled ICGScorresponds to current through gate-drain capacitance of the switching transistor M0, the waveform labeled VCGScorresponds to voltage at the gate of transistor M0, and Vcscorresponds to voltage across storage capacitor CS.

As shown inFIG. 5b, it is assumed that before time t0, the switching transistor M0is fully turned-on by having the gate voltage pulled to driver power supply Vcc. At time t0, the switch Ms3is closed and resonant condition due to gate-source capacitance CGS, inductor Lr, and storage capacitor CS is established. This initiates energy transfer from gate-source capacitance CGS to storage capacitor CS by charging the inductor Lr. The switch Ms3is closed for one-half of a resonant cycle to allow inductor Lr to magnetize as shown inFIG. 5b. The period between t0and t1is determined by values of gate-source capacitance CGS of switching transistor M0, storage capacitor CS and inductor Lr according to:

t1-t0=2⁢π⁢LR⁢1(1CS+1CGS)2,1
where LRis the inductor, CS is the storage capacitor and CGS is the capacitance of gate-source of the switching transistor M0.

At time t1, switch Ms3is opened and switch Ms2is closed, and VCGSis pulled to the reference voltage V0. In some embodiments, the time between t1and t2is selected to ensure the gate voltage discharges to the reference voltage V0, which may be ground, for example. This discharge is shown by the current ICGSin the waveform diagram. Switch Ms2is opened at time t2, which isolates the energy stored in the storage capacitor CS. All of the switches are kept open until time t3, when it is time to turn-on switching transistor M0. At time t3, switch Ms3is closed and the resonant circuit is formed again, thereby initiating energy transfer from storage capacitor CS to gate-source capacitance CGS by charging the inductor Lr. The switch is kept closed until time t4to ensure energy transfer between storage capacitor CS and the gate of switching transistor M0. In some embodiments, the time from t3to t4is one-half of a resonant period as described by Equation 1. The resonant current building up in the inductor Lr is shown as a positive half sine wave in the waveform ILR. During the time period from t3to t4, the voltage across the storage capacitor CS is discharged from a higher value of VH2to a lower value of VL2and the voltage across gate-source capacitance CGS increases from a reference voltage V0to a higher value VH.

In some embodiments, the voltage of gate-source capacitance CGS may not fully increase to Vcc due to energy loss during the energy transfer process. At time t4, the switch Ms3is opened and the switch Ms1is closed, and the gate voltage VCGSis pulled from VHto Vcc via switch Ms1. The time between t4and t5may be long enough to fully charge VCGSfrom VHto Vcc. The period between t4and t5is the time when energy is used from Vcc. This energy is very small when VHis very close to Vcc. The positive spike in current IS1and ICGSare an indication of energy used from Vcc. The switch Ms1is opened after time t5, however, in some embodiments this switch can be kept on for a longer period to avoid accidental turn-off of the switching transistor M0. The cycle is repeated when the switch Ms3is closed to transfer energy from gate-source capacitance CGS and gate-drain capacitance CGS of switching transistor M0.

FIG. 6aillustrates another embodiment system600that includes a gate driver602that is configured to drive alternatively between two switching transistors M1and M2that share a common reference voltage supply. In an embodiment, inductor Lr is coupled to the gate control node of M1and M2via independent switches SB and SA respectively. System600further includes a gate pull up switch S1coupled between a supply VCC and the gate control node of M1, and a gate pull down switch S2, coupled between the control node of M1and a reference voltage supply. A switch S3is used to pull up the gate of switching transistor M2, and switch S4is used to pull-down the gate of switching transistor M2. The inductor Lr has two capacitors CS1and CS2connected to its opposite end. These two capacitors CS1and CS2may be connected or disconnected from the reference supply by two independent switches SD and SC respectively. A capacitance CGD1represents the parasitic capacitor between the gate and the drain of transistor M1, and a capacitance CGS1represents the parasitic capacitor between the gate and the source of transistor M1. Similarly, a capacitance CGD2represents a parasitic capacitor between the gate and the drain of the switching transistor M2, and a capacitor CGS2represents a parasitic capacitor between the gate and the source of the switching transistor M2.

During operation, system600transfers charge back and forth between the gates of transistors M1and M2via the inductor Lr and a series of switches. This is done by energizing the inductor Lr and storing energy across one of the two capacitors CS1and CS2connected at each end of the inductor Lr. The switches SA and SB control the direction of the energy transfer to and from the gates of the two switching transistors M1and M2. The switches SC and SD control the energy storage in capacitors CS2and CS2respectively. The switches SC and SD are connected to the bottom plates of the capacitors CS2and CS1respectively to select the corresponding capacitor in which the energy is being stored. Switches S2and S4are connected to the gates switching transistor M1and M2respectively and they are used to ensure discharge of any residual charges left over after energy transfer via resonant action. The switches SA and SB are coupled to the inductor Lr in a direction such that their body diodes prevent inductor Lr from being energized when one of the switching transistors M1and M2is being turned off and the other is turned on. In other words, it prevents stored energy from the storage capacitors being depleted unintentionally during gate switching.

FIG. 6aalso illustrates an embodiment switch controller604that may be used to generate control signals used to drive switches SA, SB, SC, SD, S1, S2, S3and S4for embodiment system600. As shown, signal VS1controls the gate control node of switch S1, signal VS2controls switch S2, signal VS3controls switch S3, signal VS4controls the switch S4, signal VSAcontrols switch SA, signal VSBcontrols switch SB, signal VSCcontrols switch SC, and signal VSDcontrols switch SD. A high switch control signal from switch controller604, indicates an on switch condition, and a low switch control signal indicates an off switch condition.

FIG. 6billustrates a waveform diagram showing various signals within embodiment system600. Timing information is shown in the horizontal axis and voltage and current is shown in the vertical axis. Before time t0, it is assumed that all switches are turned off and the switching transistor M1is turned on by having its gate voltage VCGS1at a supply voltage Vcc. At time t0, signals VSBand VSCgo high, thus turn on the switches SB and SC. The switch SC connects the bottom plate of the capacitor CS2to reference supply voltage common to switching transistors M1and M2. The turning on of switch SB creates a resonant LC tank formed by inductor Lr, capacitor CS2and capacitor CGS1. The energy from capacitor CGS1is then transferred to capacitor CS2via inductor Lr. The switch SB and SC are kept on for one-half of the resonant period. The resonant current in the inductor ILRis shown in the waveform that follows a negative half sine wave. The voltage VCGS1at the gate terminal of switching transistor M1is discharged and reaches to a lower value of VLfrom a higher value of VH. At the same time, the voltage at the storage capacitor CS1, labeled Vcs1in the waveform, starts building. At time t1, switch SB is turned off at time t1to stop the resonant current from transferring energy back to the capacitor CGS1and the switches SD and S2are turned on. The switch S2is turned on to discharge the gate voltage VCGS1to the reference voltage from its lower value of VL. The switch S2remains turned on until time t2. Alternatively, the switch S2may be kept on until time t10in order to ensure the VCGS1remains off.

As shown inFIG. 6b, the switch SD connects the bottom plate of capacitor CS1to the reference voltage terminal such that an LC resonant tank is formed between inductor Lr, capacitor CS1and capacitor CS2, when switch SD is turned on. Switches SC and SD are kept on for one-half of the resonant period to transfer the energy stored in capacitor CS2to be transferred to the capacitor CS1. The transfer ends at time t3when switches SC and SD are turned off. Between time t3and t4, all the switches are turned off and capacitor CS1stores all the energy. The time interval between t3and t4is controlled by the dead time requirement between switching transistors M1and M2or specific converter requirement. At time t4, switches SA and SD are turned on, thereby coupling inductor Lr to the gate control node of switching transistor M2and connecting the bottom plate of capacitor CS1to the reference terminal. Thus, a resonance condition occurs using the components CS1, Lr and CGS2.

A charge transfer from capacitor CS1to the capacitor CGS2takes place, as shown by a half sine wave of current in ILR. The switch SA is turned on to allow inductor current to decay to zero at t5when it is turned off. The time period between t4and t5, is one-half of the resonant period and the gate voltage VCGS2goes from a lower value of V0to a higher value of VH. At the same time, the voltage at capacitor CS1goes from a higher value of VH2to a lower value of VL2. The voltage at capacitor CGS2reaches from its lowest value V0to a higher value VH. Switch S3is turned on at t5to pull the VCGS2to VCC and may remain on for a time interval between t5and t6, or switch S3may remain on until time t7, depending on the dead time between the activation of switching transistors M1and M2or according to the particular requirements of the system.

As shown inFIG. 6b, all switches are turned-off during the interval t6and t7. At time t7, the energy transfer is initiated from capacitor CGS2to capacitor CS1. This is done by turning on switches SA and SD. The activation of switch SD couples the bottom plate of capacitor CS1to the reference terminal and activation of the switch SA forms a resonant tank between capacitor CGS2, inductor Lr and capacitor CS1. Switch SA is kept on for one-half of the resonant period to allow energy transfer from capacitor CGS2to capacitor CS1, and at time t8, the switch SA is turned off. The resonant current ILR is shown by a positive half sine wave and current through capacitor CGS2as negative. The switches SB and SA block the charging of CS2and CGS1respectively. During the time period between t7and t8, the VCGS2swings from Vcc to a lower value VLand at the same time voltage VCS1swings from a lower value VL2to a higher value VH2, thus ensuring energy transfer from CGS2to CS1. At time t8, the switch SA is turned off and switches S4and SC are turned on. Switch SA prevents charge transfer back from capacitor CS1to capacitor CGS2. Switch S4short circuits capacitor CGS2to the reference terminal to ensure that VCGS2reaches ground potential from its lower value of VL. By turning on switch SC and turning off switches SA and SB, a resonant circuit is formed between capacitor CS1, inductor Lr and capacitor CS2such that resonant current flowing through ILR transfers energy from capacitor CS1to capacitor CS2. This energy transfer ends at time t10, when the energy is transferred to CS2and voltage VCS2has attained voltage VH2. At time t10, all of the switches are turned off such that no current flows through the inductor as shown inductor current waveform ILR and the switches remain off until t11. In an embodiment, time interval period between t11and t10is adjusted depending on a dead time requirement between switching transistors M1and M2and/or in accordance with the requirements of the particular system.

At time t11, switches SB and SC are turned on to form a resonant tank between capacitor CS2, inductor Lr and capacitor CGS1. The energy from capacitor CS2is then transferred to capacitor CGS1through the inductor Lr. The inductor current ILRthus follows a positive half sine wave, the voltage at VCGS1goes from a lower voltage VLto a higher voltage VHat time t12, and the voltage at storage capacitor CS2swings from VH2to VL2. The switches SB and SC are turned-off at t12, and at the same time switch S1is turned-on to pull VCGS1from VHto Vcc. The switch S1may be turned-off at t13or kept on until t7. A further cycle of alternative charging repeats after t13. In some embodiments, switches S1and S3are turned on for short duration in order to pull the gate voltage of switching transistors M1and M2from VH toVcc.

FIG. 7aillustrates an embodiment converter system700that utilizes an embodiment switching gate driver system600described above. The converter system700includes a first stage power converter702followed by a second stage power converter704. In an embodiment, first stage power converter702may be a switched-mode AC/DC converter configured to be coupled to an AC power grid and configured to provide power factor correction (PFC). The second stage power converter704may be a switched DC/DC converter that converts the DC output of the first stage power converter702to a different DC voltage. In one example, the power converter702may be a switched-mode power converter that converts an AC line voltage up to about 400 Vdc, and second stage power converter704may convert the output of first stage power converter702to a lower voltage such as 12 V in order to supply power to an electronic system such as a computer. Alternatively, first stage power converter702may be a DC/DC converter and/or other voltages may be used.

In an embodiment, embodiment gate driver circuits described above may be used to implement gate driver circuits in first stage power converter702and second stage power converter704.

FIG. 7billustrates an embodiment AC/DC power converter702that may be used to implement the first stage power converter702illustrated inFIG. 7a. As shown, power converter702includes a series inductor Lr followed by an H-bridge circuit that includes high-side transistors714and low-side transistors718. Each of high-side transistors714is driven by an embodiment resonant high-side gate driver circuit712, and each of low-side transistors718are driven by embodiment resonant low-side gate driver circuit716described in embodiments above. During operation, PFC controller720produces switching signals for high-side transistors714and for low-side transistors718such that the voltage across capacitor C is rectified. In some embodiments, PFC controller720controls the switching signals such that the AC input current is in phase with the AC input voltage. PFC controller720may be configured to activate high-side transistors714and low-side transistors718using soft-switching methods known in the art in order to reduce switching losses.

FIG. 7cillustrates an embodiment DC/DC power converter704that may be used to implement the second stage converter704illustrated inFIG. 7a. As shown, DC/DC power converter704is configured as an LLC converter having a half-bridge circuit with transistors724and726followed by a resonant capacitor Cr coupled in series with resonant inductor Lr and primary winding732of a transformer. On the secondary side, transistors728and730are coupled to the secondary winding734of the transformer. Each transistor724,726,728and730is driven by a corresponding embodiment resonant gate driver744,746,748and750as described in embodiments above.

During operation, LLC controller722produces switching signals that activate resonant gate drivers744,746,748and750. In particular, LLC controller722drives half-bridge transistors724and726near a resonant frequency of power converter702to control the output voltage according to LLC control methodologies known in the art. LLC controller722further operates the secondary-side switching transistors728and730as synchronous rectifiers according to synchronous rectifier control schemes known in the art. In some embodiments, the various transistors are controlled using soft-switching methods known in the art. It should be appreciated that power converters702and704illustrated inFIGS. 7band 7care just two of many possible embodiment power converter topologies that may be used in embodiment power supply systems.

In some embodiments, the energy harvested from gate-drain capacitance CGD may be used to supplement the power used to drive the switching transistor. For example, in the embodiment fly back circuit ofFIG. 1, an embodiment gate driver circuit may be used to drive the switching transistor such that at least 50% of the energy used to drive the switching transistor was harvested from the gate-drain capacitance of the switching transistor during a previous cycle. In some embodiments, the circuit may harvest other percentages of the power used to drive the switching transistor. This harvested power may even exceed the amount of power used to turn on the switching transistor.

FIG. 8illustrates a flowchart of an embodiment method800of operating switching transistor. In step802, a switching transistor is turned-off when a voltage across the switching transistor is above a first voltage level. In step804, charge is transferred from gate-drain capacitance of the switching transistor to a charge storage device. In some embodiments, charge is also transferred from the gate-source capacitance of the switching transistor. Next in step806, a switching transistor is turned-on when the voltage across the switching transistor is below a second voltage level, which is lower than the first voltage level. Finally, in step808, the charge is transferred from the storage device to a gate of the switching transistor.

The general figure of merit (FOM) for a switching MOSFET is a product of Qgd*Ron, where Qgd is gate-drain charge and Ron is the on-resistance of the switching MOSET. In some embodiments of the present invention, however, larger Cgd translates into more energy being extracted from the gate-drain capacitance of the switching transistor when the switching transistor is being turned-off. Accordingly, in some embodiments, very good performance may be achieved even when Qgd*Ron are not minimized. The higher Qgd translates to higher energy extraction during MOSFET turn-off. Furthermore, with larger Qgd, the gate drive current waveform is may be different and allow charging and discharging of Cgd at highest current resonant point instead of classic miller capacitance current for conventional MOSFET. This may enable similar or even faster switching speeds while increasing Qgd or increasing Ron without sacrificing the switching speed or gate losses. Furthermore, a well-controlled resonant gate drive tends to have smooth switching waveforms without the conventional voltage overshoot seen in hard-switching gate drivers where the dv/dt of VGScan be finely controlled by the value of the resonant inductor Lr.

In various embodiments, energy can be extracted during turning-off of a switching transistor with a resonant inductor and a storage capacitor. The extracted energy is stored in the storage capacitor for re-use during turning-on of the switching transistor. A net positive energy is achieved when the energy extracted during turn-off is larger than the energy used to turn-on the switching transistor under ZVS condition including all switching and resistive losses. An equation is shown below to satisfy the condition for the net positive energy:
0.5LrI2−Gate Drive Losses>0.5(CGS+CGD)VGS22,
where Lris the resonant inductor, I is the maximum/peak current through the inductor during turn-off of the switching transistor, VGSis the gate-source voltage of the switching transistor during turn-on, CGSis the gate-source capacitor and CGDis the gate-drain capacitor of the switching transistor. The term LrI2represents the energy transferred via the resonant inductor Lrand stored in a storage capacitor or referred to as the extracted energy. The gate drive losses include switching and other resistive losses while driving the switching transistor. The right side of the equation denotes the energy required to turn-on the switching transistor under ZVS condition. The current I through the inductor can be expressed in terms of the capacitor CGD, gate-source voltage VGSand gate-drain voltage VDSacross the switching transistor. The equation may be further simplified by considering the gate drive losses as a fraction of the total energy extracted.

In an embodiment, using a switching MOSFET that has a CGDto CGSratio of greater than 0.3 may yield a net positive energy when operated at a VGSof 10 V and a VDSof 50 V. In other embodiments, the ratio can be as low as 0.01 or as high as 1 to achieve net positive energy. It should be understood that above example is one of many ways to achieve net positive energy for different CGSto CGDratio, VGS, and VDSof the switching transistor.

Embodiments of the present invention may be applied to various switching applications. For example, embodiment gate drivers may be used in synchronous buck converters, AC and DC switched-mode power supplies, half-bridge and full-bridge drivers that are used, for example, in brushless DC motor drives. An advantage of some embodiments includes the ability to extract energy during resonant gate switching from the charging of gate-drain capacitor Cgd during transistor turn-off events and storing this energy for reuse. It is to be noted that during zero voltage switching, the gate driver does not need to charge gate-drain capacitor Cgd in the reverse direction, during turn-on event, and hence the stored energy is not supplied back. Therefore, the energy extracted during turn-off event contributes towards the efficiency of the system. In some embodiments, the energy extracted from charging of gate-drain capacitor Cgd and stored in a storage capacitor may be higher than the total energy consumption of the gate driver itself. In such cases, the power supply needed for the driver may be supplied by extracted energy. Embodiment systems and methods may also be applied to provide an autonomous power supply generator for the gate driver.

Embodiments of the present invention are summarized here. Other embodiments can also be understood from the entirety of the specification and the claims filed herein. One general aspect includes a method of operating a switching transistor that includes turning-off the switching transistor by transferring charge from a gate-drain capacitance of the switching transistor to a charge storage device, and turning-on the switching transistor by transferring charge from the charge storage device to a gate of the switching transistor. Turning-off the switching transistor includes hard-switching and turning-on the switching transistor includes soft-switching.

Implementations may include one or more of the following features. The method where transferring the charge from the gate-drain capacitance of the switching transistor to the charge storage device includes coupling an inductor between a reference node and the gate of the switching transistor, magnetizing the inductor with the charge from the gate-drain capacitance of the switching transistor, coupling the inductor between the gate of the switching transistor and the charge storage device a first time, and charging the charge storage device as the inductor demagnetizes; and transferring charge from the charge storage device to the gate of the switching transistor includes coupling the charge storage device to the gate of the switching transistor a second time. The method where coupling the inductor between the reference node and the gate of the switching transistor includes turning-on a first switch coupled between the inductor and the reference node; and coupling the charge storage device to the gate of the switching transistor the second time includes turning-on a second switch coupled between the inductor and the charge storage device. The method where the first switch includes a first transistor; the second switch includes a second transistor; and coupling the inductor between the gate of the switching transistor and the charge storage device the first time includes coupling the inductor to the charge storage device by at least one of turning-on the second transistor and using a body diode of the second transistor.

In some embodiments, coupling the inductor between the gate of the switching transistor and the charge storage device the first time further includes turning off the first switch and turning on a third switch coupled between the gate of the switching transistor and a reference terminal of the switching transistor. In some embodiments, the charge storage device includes a capacitor.

Implementations may further include the method where turning-off the switching transistor further includes transferring charge from a gate-source capacitance of the switching transistor to the charge storage device. The method where transferring charge from the gate-drain capacitance of the switching transistor to the charge storage device includes closing a switch coupled in series with an inductor and a capacitor of the charge storage device for a first time period; and transferring charge from the charge storage device to the gate of the switching transistor includes closing the switch for a second time period. In some embodiments, the first time period and the second time period may be one-half of a resonant time period of an LC tank formed by the inductor and an input capacitance of the switching transistor.

In some embodiments, the stored energy transferred from the switching transistor to the charge storage device is greater than 50% of energy transferred from the charge storage device to the gate of the switching transistor. In other embodiments, the stored energy transferred from the switching transistor to the charge storage device may be at least 100% of the energy transferred from the charge storage device to the gate of the switching transistor.

Implementations may further include the method where the switching transistor includes a high-side switching transistor. The method where the switching transistor includes a high-side switching transistor. In some embodiments, the switching transistor includes a super junction MOSFET. In other embodiments, the switching transistor includes a gallium nitride (GaN) high electron mobility transistor (HEMT).

The method may also include turning-off the switching transistor when a voltage across the switching transistor reaches a local maximum. In some embodiments, turning-on the switching transistor includes turning on the switching transistor when a voltage across the switching transistor reaches a local minimum and/or zero volts. In some embodiments, the method further includes monitoring a voltage of the charge storage device; and coupling the charge storage device to an external power supply when a voltage of the charge storage device falls below a predetermined threshold. The method may further include controlling a rate of change of a gate to source voltage of the switching transistor by adjusting an inductance of an inductor coupled to the gate of the switching transistor.

A further general aspect includes a circuit having a gate driver configured to be coupled to a gate of a switching transistor and to a charge storage device, where the gate driver configured to: turn-off the switching transistor by transferring charge from a gate-drain capacitance of the switching transistor to a charge storage device, where the switching transistor is turned-off using hard switching; and turn-on the switching transistor by transferring charge from the charge storage device to a gate of the switching transistor. The switching transistor is turned-on using hard switching.

Implementations may include one or more of the following features. The circuit where: the gate driver includes an inductor configured to be coupled to the gate of the switching transistor; and the gate driver is further configured to transfer charge from the gate-drain capacitance of the switching transistor to the charge storage device by coupling the inductor between a reference node and the gate of the switching transistor, magnetizing the inductor with the charge from the gate-drain capacitance of the switching transistor, coupling the inductor between the gate of the switching transistor and the charge storage device a first time, and charging the charge storage device as the inductor demagnetizes, and transfer charge from the charge storage device to the gate of the switching transistor by coupling the charge storage device to the gate of the switching transistor a second time. The circuit where the gate driver further includes: a first switch coupled between the inductor and the reference node; and a second switch coupled between the inductor and the charge storage device, where the gate driver is configured to couple the inductor between the reference node and the gate of the switching transistor by turning on the first switch, and couple the charge storage device to the gate of the switching transistor the second time by turning on the second switch.

Implementations may further include the circuit where the first switch has a first transistor; the second switch has a second transistor; and the gate driver is configured to couple the inductor between the gate of the switching transistor and the charge storage device the first time via a body diode of the second transistor. The circuit where the gate driver includes: an inductor and a switch coupled in series forming a switched inductor circuit, the switched inductor circuit configured to be coupled between the charge storage device and the gate of the switching transistor, where the gate driver circuit is further configured to transfer charge from a gate-drain capacitance of the switching transistor to the charge storage device by closing the switch for a first time period, and transfer charge from the charge storage device to the gate of the switching transistor by closing the switch for a second time period.

In some embodiments, the first time period and the second time period are one-half of a resonant time period of an LC tank formed by the inductor and an input capacitance of the switching transistor. In some embodiments the charge storage device includes a capacitor. Stored energy transferred from the gate of the switching transistor to the charge storage device may be greater than 50% of energy transferred from the charge storage device to the gate of the switching transistor. In some cases, stored energy transferred from the gate of the switching transistor to the charge storage device is at least 100% of energy transferred from the charge storage device to the gate of the switching transistor.

Implementations may also include the circuit where the gate-drain capacitance of the switching transistor is at least one-tenth of a gate-source capacitance of the switching transistor. In some embodiments, the circuit includes the switching transistor. The switching transistor may include a high-side switching transistor, and, in some embodiments, the switching transistor includes a super junction MOSFET. The gate driver may be configured to turn-on the switching transistor when a voltage across the switching transistor is zero volts.

In various embodiments, circuit further includes a charge storage monitoring circuit configured to monitor a voltage of the charge storage circuit; and a switch coupled between the charge storage device and an external power supply, where the charge monitoring circuit is configured to close the switch when a voltage of the charge storage device falls below a predetermined threshold. The charge storage monitoring circuit may include a comparator having a first input node coupled to the charge storage device, a second input node coupled to a reference voltage node, and an output coupled to a control node of the switch. In some embodiments, the circuit further includes the charge storage device.

In an embodiment, the circuit includes: the switching transistor; a transformer having a first winding coupled to the switching transistor; a secondary side circuit including a secondary controller coupled to secondary-side switching that are coupled to a second winding of the transformer; and an isolated communications link coupled between the secondary controller and an input to the gate driver, where stored energy transferred from the charge storage device to the switching transistor is greater than 50% of energy transferred from the charge storage device to the gate of the switching transistor.

A further general aspect includes a method of driving a first switching transistor and a second switching transistor, the method including: turning-off the first switching transistor including transferring a charge from a gate of the first switching transistor to a charge storage device; after turning-off the first switching transistor, turning-on the second switching transistor including transferring the charge from the charge storage device to a gate of the second switching transistor; after turning-on the second switching transistor, turning-off the second switching transistor including transferring the charge from the gate of the second switching transistor to the charge storage device; and after turning-off the second switching transistor, turning-on the first switching transistor including transferring the charge from the charge storage device to the gate of the first switching transistor.

Implementations may include one or more of the following features. The method where turning-off the first switching transistor includes turning-off the first switching transistor when a voltage across the first switching transistor is greater than a first voltage level; turning-off the second switching transistor includes turning-off the second switching transistor when a voltage across the second switching transistor is greater than the first voltage level; turning-on the first switching transistor includes turning-on the first switching transistor when the voltage across the first switching transistor is less than a second voltage level, where the second voltage level is less than the first voltage level; and turning-on the second switching transistor includes turning-on the second switching transistor when the voltage across the second switching transistor is less than the second voltage level. In some embodiments, turning-on the second switching transistor includes using at least 50% of energy taken from the gate of the first switching transistor while turning-off the first switching transistor.

In an embodiment, transferring the charge from the gate of the first switching transistor to the charge storage device includes charging a first capacitor via an inductor; transferring the charge from the gate of the second transistor to the charge storage device includes charging a second capacitor via the inductor; transferring the charge from the charge storage device to the gate of the first transistor includes transferring the charge from the second capacitor to the first capacitor via the inductor and transferring the charge from the first capacitor to the gate of the first transistor via the inductor; and transferring the charge from the charge storage device to the gate of the second transistor includes transferring the charge from the first capacitor to the second capacitor via the inductor and transferring the charge from the second capacitor to the gate of the second transistor via the inductor.

Implementations further include the method where: transferring the charge from the gate of the first switching transistor to the charge storage device includes charging a first capacitor via an inductor by closing a first switch coupled between the gate of the first switching transistor and a first terminal of the inductor, closing a second switch coupled between a second terminal of the inductor and a reference node, opening a third switch coupled between the second terminal of the inductor and the gate of the second switching transistor, and opening a fourth switch coupled between the first terminal of the inductor and the reference node; transferring the charge from the gate of the second transistor to the charge storage device includes charging a second capacitor via the inductor by opening the first switch, opening the second switch, closing the third switch and closing the fourth switch; transferring the charge from the charge storage device to the gate of the first transistor includes transferring the charge from the second capacitor to the first capacitor via the inductor by opening the first switch, closing the second switch, opening the third switch and closing the fourth switch, and transferring the charge from the first capacitor to the gate of the first transistor via the inductor by closing the first switch, closing the second switch, opening the third switch and opening the fourth switch; and transferring the charge from the charge storage device to the gate of the second transistor includes transferring the charge from the first capacitor to the second capacitor via the inductor by opening the first switch, closing the second switch, opening the third switch and closing the fourth switch, and transferring the charge from the second capacitor to the gate of the second transistor via the inductor by opening the first switch, opening the second switch, closing the third switch and closing the fourth switch.

In an embodiment, the steps of closing the first switch, closing the second switch, closing the third switch and closing the fourth switch includes closing the respective switches for a half-resonant cycle of an LC tank formed by the inductor, the first capacitor and the second capacitor.

One general aspect includes a power supply system including: a switching transistor circuit configured to drive an inductive load; a charge storage capacitor coupled to a gate of the switching transistor; a gate driver circuit configured to turn-off the switching transistor, transfer a first energy from the switching transistor to the charge storage capacitor when turning-off the switching transistor; and turn-on the switching transistor by transferring a second energy from the charge storage capacitor to the gate of the switching transistor, where the first energy is at least 50% of the second energy.

Implementations may include one or more of the following features. The system where the switching transistor circuit includes a gallium nitride (GaN) high electron mobility transistor (HEMT). In some embodiments, the first energy is at least 100% of the second energy. The gate driver may be configured to turn-off the switching transistor using hard switching; and the gate driver is configured to turn-on the switching transistor using soft-switching.