Semiconductor device, battery monitoring device, and voltage detection method of battery cell

A semiconductor device including plural first switches, each provided so as to correspond to one of plural battery cells connected in series, each first switch including one end connected to a corresponding battery cell and another end connected to one electrode of a corresponding charge storage section of plural charge storage sections, each of the charge storage sections being provided so as to correspond to one of the plural battery cells, and another electrode of each charge storage section being connected to a fixed potential; plural second switches, each provided so as to correspond to one of the plural first switches, each second switch including one end connected to the other end of the corresponding first switch; and processing section connected to each other end of the plural second switches, that processes voltages supplied via the second switches.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 USC 119 from Japanese Patent Application No. 2015-142276, filed on Jul. 16, 2015, the disclosure of which is incorporated by reference herein.

BACKGROUND

Technical Field

The present disclosure relates to a semiconductor device, a battery monitoring device, and a voltage detection method of a battery cell.

Related Art

As a technique for detecting a cell voltage of each of plural battery cells connected in series, the following technology is known. For example, in Japanese Patent Application Laid-Open (JP-A) No. 2001-56350, a voltage detection circuit for detecting voltages of an assembled battery including plural sample-and-hold circuits configured capable of holding a voltage of each unit battery between both electrodes of each capacitor, is described. In this voltage detection circuit, a capacitor group in which plural capacitors are connected in series is provided so as to corresponds to an assembled battery including plural unit batteries connected in series, and switches for sample-and-hold are provided at each of plural parallel lines. The plural parallel lines connect, between the assembled battery and the capacitor group, both electrodes of each unit battery and both electrodes of each capacitor that are arranged at the same order with each other. The voltage detection circuit includes a switch control means that simultaneously turns OFF the switches for sample-and-hold, and a voltage detection means detects a voltage between both electrodes of each capacitor by sequentially taking in a voltage between predetermined portions of the capacitor group when the switches for sample-and-hold are turned OFF.

However, in the voltage detection circuit described in JP-A No. 2001-56350, since the switches for sample-and-hold are connected to both electrodes of the capacitor, noise generated by operation of the sample-and-hold switches influences to the charges to be stored in the capacitor, and thus, accuracy of voltage detection of each unit battery (battery cell) may be decreased.

Recent years, in the battery monitoring devices, accuracy in detection of the cell voltage has been increasingly required, and decrease in accuracy of voltage detection as described above has become unacceptable.

SUMMARY

The present disclosure provides a semiconductor device that may improve detection accuracy of the cell voltage.

A semiconductor device according to a first aspect includes: plural first switches, each provided so as to correspond to one of plural battery cells connected in series, each first switch including one end connected to a corresponding battery cell and another end connected to one electrode of a corresponding charge storage section of plural charge storage sections, each of the charge storage sections being provided so as to correspond to one of the plural battery cells, and another electrode of each charge storage section being connected to a fixed potential; plural second switches, each provided so as to correspond to one of the plural first switches, each second switch including one end connected to the other end of the corresponding first switch; and processing section connected to each other end of the plural second switches, that processes voltages supplied via the second switches.

A battery monitoring device according to a second aspect includes: the semiconductor device according to the first aspect; the plural battery cells; and the plural charge storage sections.

A voltage detection method of a battery cell according to a third aspect includes: providing plural charge storage sections such that each charge storage section corresponds to one of plural battery cells connected in series, the plural charge storage sections each including one electrode connected to a fixed potential; connecting each of the plural battery cells to another electrode of the corresponding charge storage section, to charge each of the plural charge storage sections; disconnecting a connection between each of the plural battery cells and each of the plural charge storage sections at a same timing; and sequentially detecting a charging voltage of each of the plural charge storage sections.

According to the above aspects, the present disclosure may provide a semiconductor device, a battery monitoring device, and a voltage detection method of a battery cell that may improve detection accuracy of the cell voltage.

DETAILED DESCRIPTION

Hereinafter, exemplary embodiments of the present disclosure is described with reference to the drawings. Note that the same reference numerals are added to the same or equivalent components and portions in the drawings, and redundant description thereof is omitted, if appropriate.

First Exemplary Embodiment

FIG. 1is a diagram illustrating a configuration of a battery monitoring device100according to a first exemplary embodiment of the present disclosure. The battery monitoring device100is configured including an assembled battery1, a capacitor group2, and a battery monitoring IC (Integrated Circuit)3.

The assembled battery1includes plural battery cells11,12, and13that are connected in series. In an example illustrated inFIG. 1, the number of battery cells configuring the assembled battery1is three. However, the number of battery cells configuring the assembled battery1may be increased or decreased, if appropriate.

The capacitor group2is configured to include capacitors21,22, and23, each of which is provided respectively so as to correspond to the battery cells11,12, and13. One electrode of each of the capacitors21,22, and23is fixed to a around potential, and the other electrode is connected to the battery monitoring IC3. The number of capacitors included in the capacitor group2may be increased or decreased depending on the number of battery cells, if appropriate.

The battery monitoring IC3is configured as a semiconductor device including an integrated circuit formed on a semiconductor substrate. The battery monitoring IC3is configured to include cell voltage input terminals31,32, and33, capacitor connection terminals36,37, and38, a around terminal30, a power supply terminal39, an output terminal35, a sample-and-hold switch group4, a cell selection switch group5, a signal processing circuit6, and a control circuit7.

The connection point between the positive electrode of the battery cell11and the negative electrode of the battery cell12is connected to the cell voltage input terminal31of the battery monitoring IC3. The connection point between the positive electrode of the battery cell12and the negative electrode of the battery cell13is connected to the cell voltage input terminal32of the battery monitoring IC3. The positive electrode of the battery cell13is connected to the cell voltage input terminal33of the battery monitoring IC3.

The opposite side electrode of the capacitor21, opposite to the electrode fixed to the ground potential, is connected to the capacitor connection terminal36. The opposite side electrode of the capacitor22, opposite to the electrode fixed to the ground potential, is connected to the capacitor connection terminal37. The opposite side electrode of the capacitor23, opposite to the electrode fixed to the ground potential, is connected to the capacitor connection terminal38.

The sample-and-hold switch group4is configured to include sample-and-hold switches41,42, and43, each of which is provided respectively so as to correspond to the battery cells11,12, and13. The input end of the sample-and-hold switch41is connected to the positive electrode of the corresponding battery cell11via the cell voltage input terminal31. The output end of the sample-and-hold switch41is connected to the opposite side electrode of the capacitor21, opposite to the electrode fixed to the ground potential, via the capacitor connection terminal36. In a case in which the sample-and-hold switch41is turned ON, the capacitor21and the battery cell11are connected to each other, and the capacitor21is charged by a voltage of the positive electrode of the battery cell11.

The input end of the sample-and-hold switch42is connected to the positive electrode of the corresponding battery cell12via the cell voltage input terminal32. The output end of the sample-and-hold switch42is connected to the opposite side electrode of the capacitor22, opposite to the electrode fixed to the ground potential, via the capacitor connection terminal37. In a case in which the sample-and-hold switch42is turned ON, the capacitor22and the battery cell12are connected to each other, and the capacitor22is charged by a voltage of the positive electrode of the battery cell12.

The input end of the sample-and-hold switch43is connected to the positive electrode of the corresponding battery cell13via the cell voltage input terminal33. The output end of the sample-and-hold switch43is connected to the opposite side electrode of the capacitor23, opposite to the electrode fixed to the ground potential, via the capacitor connection terminal38. In a case in which the sample-and-hold switch43is turned ON, the capacitor23and the battery cell13are connected to each other, and the capacitor23is charged by a voltage of the positive electrode of the battery cell13.

The cell selection switch group5has high potential side switches56, and58, each of which is provided respectively so as to correspond to the battery cells11,12, and13, and the sample-and-hold switches41,42, and43.

The input end of the high potential side switch56is connected to the output end of the sample-and-hold switch41. The output end of the high potential side switch56is connected to a high potential side input end a1of the signal processing circuit6.

The input end of the high potential side switch57is connected to the output end of the sample-and-hold switch42. The output end of the high potential side switch57is connected to the high potential side input end a1of the signal processing circuit6.

The input end of the high potential side switch58is connected to the output end of the sample-and-hold switch41. The output end of the high potential side switch58is connected to the high potential side input end a1of the signal processing circuit6.

The cell selection switch group5further has a low potential side switch51whose input end is connected to the ground potential via the ground terminal30, and low potential side switches52,53each of which is provided so as to correspond to the sample-and-hold switches41and42that are corresponding respectively to the battery cells11and12, except for the battery cell13positioned at the highest potential.

The input end of the low potential side switch52is connected to the output end of the sample-and-hold switch41. The output end of the low potential side switch52is connected to a low potential side input end a2of the signal processing circuit6.

The input end of the low potential side switch53is connected to the output end of the sample-and-hold switch42. The output end of the low potential side switch53is connected to the low potential side input end a2of the signal processing circuit6.

The input end of the low potential side switch51is connected to the ground terminal30. The output end of the low potential side switch51is connected to the low potential side input end a2of the signal processing circuit6.

The control circuit7supplies control signals to the sample-and-hold switches41,42, and43(the sample-and-hold switch group4), the low potential side switches51,52,53, and the high potential side switches56,57,58(the cell selection switch group5), to control ON/OFF of those switches.

The signal processing circuit6processes the voltages supplied via the switches configuring the cell selection switch group5, and outputs an output signal indicating magnitude of each cell voltage of the battery cells11,12, and13from the output terminal35. The signal processing circuit6is operated by a power supply voltage supplied from the positive electrode of the battery cell13via the power supply terminal39. Note that, the signal processing circuit6may be supplied by a voltage in which a voltage level positive electrode of the battery cell13is adjusted by a DC-DC converter.

FIG. 2is a circuit block diagram illustrating an example configuration of the signal processing circuit6. As illustrated inFIG. 2, the signal processing circuit6is configured to include, for example, a buffer amplifier61, a level-shift circuit64, and an A/D (analog/digital) converter70.

The buffer amplifier61is configured to include operational amplifier circuits62and63. The non-inverting input terminal of the operational amplifier circuit62is connected to the high potential side input end a1of the signal processing circuit6, and the inverting input terminal is connected to the output terminal of the operational amplifier circuit62. Namely, the operational amplifier circuit62configures a voltage follower, and performs impedance conversion of a voltage input to the input end a1while keeping its magnitude, and outputs the voltage. Similarly, the non-inverting input terminal of the operational amplifier circuit63is connected to the low potential side input end a2of the signal processing circuit6, and the inverting input terminal is connected to the output terminal of the operational amplifier circuit63. Namely, the operational amplifier circuit63configures a voltage follower, and performs impedance conversion of a voltage input to the input end a2while keeping its magnitude, and outputs the voltage.

The level-shift circuit64is configured to include an operational amplifier circuit65, and resistor elements66,67,68, and69. The non-inverting input terminal of the operational amplifier circuit65is connected to the output terminal of the operational amplifier circuit62via the resistor element66. Further, the non-inverting input terminal of the operational amplifier circuit65is connected to the ground potential via the resistor element69. The inverting input terminal of the operational amplifier circuit65is connected to the output terminal of the operational amplifier circuit63via the resistor element67. Further, the inverting input terminal of the operational amplifier circuit65is connected to the output terminal of the operational amplifier circuit65via the resistor element68. The level-shift circuit64is a difference voltage output circuit that outputs a difference voltage. The difference voltage is a difference between a voltage input to the input end a1and a voltage input to the input end a2, and has a level with the ground potential as a reference.

The A/D converter70generates a digital signal according to a voltage output from the level-shift circuit64, and outputs the digital signal from the output terminal35.

Hereinafter, operation is described of the battery monitoring device100.FIG. 3is a timing chart illustrating operation of the battery monitoring IC3, in a case in which the cell voltages of the battery cells11,12, and13are detected.

First, the control circuit7controls the sample-and-hold switches41,42, and43to be turned ON simultaneously. Thus, the capacitor21and the battery cell11are connected to each other, and the capacitor21is charged by the voltage of the positive electrode of the battery cell11. Similarly, the capacitor22and the battery cell12are connected to each other, and the capacitor22is charged by the voltage of the positive electrode of the battery cell12. Also, the capacitor23and the battery cell13are connected to each other, and the capacitor23is charged by the voltage of the positive electrode of the battery cell13. In a case in which charging of the capacitors21,22,23are completed, the control circuit7controls the sample-and-hold switches41,42, and43to be turned OFF simultaneously. In a case in which the sample-and-hold switches41,42, and43are turned from ON to OFF at the same timing, the cell voltages of the battery cells11,12, and13are sampled at the same point in time. Note that, in this sampling process, the capacitors21,22, and23needs to be in full charged state, and thus, timings when the sample-and-hold switch41,42, and43are turned ON does not need to be the same.

Next, the control circuit7controls, out of the switches configuring the cell selection switch group5, the low potential side switch51and the high potential side switch56to be turned ON. Thus, the high potential side input end a1of the signal processing circuit6is connected to the capacitor21, and the low potential side input end a2of the signal processing circuit6is connected to the ground potential. Namely, the voltage corresponding to the cell voltage of the battery cell11is input to the signal processing circuit6. The signal processing circuit6performs impedance conversion process, level-shift process, and digital conversion process to the input voltage, and outputs an output signal indicating the cell voltage of the battery cell11from the output terminal35. Note that, since the signal processing circuit6receives the voltage input to the input ends a1and a2by the buffer amplifier61having high input impedance, the charges stored in the capacitor21are kept without being discharged. Namely, the voltage sampled from the cell voltage of the battery cell11is kept in the capacitor21.

Next, the control circuit7controls, out of the switches configuring the cell selection switch group5, the low potential side switch52and the high potential side switch57to be turned ON. Thus, the high potential side input end a1of the signal processing circuit6is connected to the capacitor22, and the low potential side input end a2of the signal processing circuit6is connected to the capacitor21. Namely, the voltage corresponding to the cell voltage of the battery cell12is input to the signal processing circuit6. The signal processing circuit6performs impedance conversion process, level-shift process, and digital conversion process to the input voltage, and outputs the output signal indicating the cell voltage of the battery cell12from the output terminal35. Note that, since the signal processing circuit6receives the voltage input to the input ends a1and a2by the buffer amplifier61having high input impedance, the charges stored in the capacitors21and22are kept without being discharged. Namely, the voltage sampled from the cell voltage of the battery cell12is kept in the capacitor22.

Next, the control circuit7controls, out of the switches configuring the cell selection switch group5, the low potential side switch53and the high potential side switch58to be turned ON. Thus, the high potential side input end a1of the signal processing circuit6is connected to the capacitor23, and the low potential side input end a2of the signal processing circuit6is connected to the capacitor22. Namely, the voltage corresponding to the cell voltage of the battery cell13is input to the signal processing circuit6. The signal processing circuit6performs impedance conversion process, level-shift process, and digital conversion process to the input voltage, and outputs the output signal indicating the cell voltage of the battery cell13from the output terminal35. Note that, since the signal processing circuit6receives the voltage input to the input ends a1and a2by the buffer amplifier61having high input impedance, the charges stored in the capacitor22and23are kept without being discharged. Namely, the voltage sampled from the cell voltage of the battery cell13is kept in the capacitor23.

Here,FIG. 5is a diagram illustrating a configuration of a battery monitoring device100X according to a comparative example. The battery monitoring device100X according to the comparative example is different from the battery monitoring device100according to the exemplary embodiment of the present disclosure described above, in that the battery monitoring device100X does not have a sample-and-hold switch group and a capacitor group for sample-and-hold.

Hereinafter, a case in which the cell voltages of the battery cells11,12, and13are detected by the battery monitoring device100X according to the comparative example, will be described.

The control circuit7controls, out of the switches configuring the cell selection switch group5, the low potential side switch51and the high potential side switch56to be turned ON. Thus, the high potential side input end a1of signal processing circuit6is connected to the positive electrode of the battery cell11, and the low potential side input end a2of the signal processing circuit6is connected to the ground potential. Namely, the cell voltage of the battery cell11is input to the signal processing circuit6. The signal processing circuit6performs impedance conversion process, level-shift process, and digital conversion process to the input voltage, and outputs the output signal indicating the cell voltage of the battery cell11from the output terminal35.

Next, the control circuit7controls, out of the switches configuring the cell selection switch group5, the low potential side switch52and the high potential side switch57to be turned ON. Thus, the high potential side input end a1of the signal processing circuit6is connected to the positive electrode of the battery cell12, and the low potential side input end a2of the signal processing circuit6is connected to the negative electrode of the battery cell12. Namely, the cell voltage of the battery cell12is input to the signal processing circuit6. The signal processing circuit6performs impedance conversion process, level-shift process, and digital conversion process to the input voltage, and outputs the output signal indicating the cell voltage of the battery cell12from the output terminal35.

Next, the control circuit7controls, out of the switches configuring the cell selection switch group5, the low potential side switch53and the high potential side switch58to be turned ON. Thus, the high potential side input end a1of the signal processing circuit6is connected to the positive electrode of the battery cell13, and the low potential side input end a2of the signal processing circuit6is connected to the negative electrode of the battery cell13. Namely, the cell voltage of the battery cell13is input to the signal processing circuit6. The signal processing circuit6performs impedance conversion process, level-shift process, and digital conversion process to the voltage input, and outputs the output signal indicating the cell voltage of the battery cell13from the output terminal35.

In this way, in the battery monitoring device100X according to the comparative example, the battery cells11,12, and13are sequentially connected to the signal processing circuit6, and the respective cell voltages are sequentially detected. Namely, in the battery monitoring device100X according to the comparative example, the cell voltages of the battery cells11,12, and13are detected and output at different point in time from each other. In order to accurately detect the state of each of the battery cells configuring the assembled battery, it is desirable to detect the cell voltages at the same point in time for each of the battery cells. In the battery monitoring device100X according to the comparative example, the cell voltage cannot be measured at the same point in time, and thus, may be difficult to accurately detect the states of the battery cells11,12, and13.

On the other hand, in the battery monitoring IC3and the battery monitoring device100according to the present disclosure, since the sample-and-hold switches41,42, and43are turned ON, and then turned OFF at the same timing, the cell voltages of the battery cells11,12, and13are sampled at the same timing. The cell voltages of the battery cells11,12, and13that are respectively stored in the capacitors21,22, and23are then sequentially transmitted to the signal processing circuit6to be processed. Therefore, the battery monitoring device100according to the present disclosure may detect the cell voltages of the battery cells11,12, and13configuring the assembled battery1at the same point in time, and thus, may accurately detect the states of the battery cells11,12, and13.

In the battery monitoring IC3and the battery monitoring device100according to the present exemplary embodiment, one electrode of each of the capacitors21and23is fixed to the ground potential. Therefore, in comparison with the voltage detection circuit described in JP-A No. 2001-56350, in which both electrodes of the capacitor are connected to the switch for sample-and-hold, the present exemplary embodiment may reduce influence of noise generated by operation of the switch for sample-and-hold. Namely, the battery monitoring IC3and the battery monitoring device100according to the exemplary embodiment may improve detection accuracy of the cell voltage of each of the battery cells compared to the conventional devices.

Further, in the voltage detection circuit described in JP-A No. 2001-56350, in a case in which the voltages between both electrodes of each of the capacitors are sequentially detected, connects the low potential side electrode of each of the capacitors to the ground potential by turning the selection switch ON. Thus, the charges stored in the capacitors are almost completely discharged. Namely, in the voltage detection circuit described in JP-A No. 2001-56350, charging and discharging of the capacitor are repeated every time when detecting the cell voltage. Accordingly, power is consumed in each section of the battery (battery cell) every time when detecting the cell voltage. In addition, when the cell voltage is detected, since each capacitor is required to be fully charged from fully discharged state, a relatively long sampling time may be required.

On the other hand, in the battery monitoring IC3and the battery monitoring device100according to the exemplary embodiment of the present disclosure, since the cell voltages sampled in the capacitors21,22, and23are received by the buffer amplifier61of the signal processing circuit6, the charges stored in the capacitors21,22, and23are kept without being discharged. Therefore, since charging and discharging are not repeated at every time when the cell voltages are detected, power consumption of the battery cells11,12, and13may be suppressed when sampling the cell voltage. In addition, even after the detection of the cell voltage, since the charges stored in the capacitors21,22, and23are kept, and since charging the capacitors from fully discharged state are not required when the cell voltages are detected next time, the sampling time may be shortened. Therefore, the battery monitoring device100according to the exemplary embodiment of the present disclosure may shorten the time required for detection of the cell voltages, compared to the voltage detection circuit described in JP-A No. 2001-56350.

In the battery monitoring IC3and the battery monitoring device100according to the exemplary embodiment, as described above, charges stored in the capacitors21,22, and23are kept, and the voltages of the capacitors21,22, and23are stable. Therefore, since a sufficient processing time may be secured in analog-digital conversion process by the A/D converter, detection accuracy of the cell voltage may be improved.

In the battery monitoring IC3and the battery monitoring device100according to the exemplary embodiment, since the capacitors21,22, and23are provided outside the battery monitoring IC3, the chip size of the battery monitoring IC may be reduced, when compared to a case in which the capacitors21,22, and23are incorporated in the battery monitoring IC3.

Second Exemplary Embodiment

FIG. 4is a diagram illustrating a configuration of a battery monitoring device100A according to a second exemplary embodiment of the present disclosure. The battery monitoring device100A is different from the battery monitoring device100according to the first exemplary embodiment described above, in that the battery monitoring device100A further includes resistor elements26,27, and28provided respectively no as to correspond to the battery cells11,12, and13. Since other components are the same as of the battery monitoring device100according to the first exemplary embodiment, descriptions thereof will be omitted.

One end of the resistor element26is connected to the connection point between the positive electrode of the battery cell11and the negative electrode of the battery cell12. The other end of the resistor element26is connected to the cell voltage input terminal31. Namely, one end of the sample-and-hold switch41connected to the positive electrode of the corresponding battery cell11via the resistor element26.

One end of the resistor element27is connected to the connection point between the positive electrode of the battery cell12and the negative electrode of the battery cell13. The other end of the resistor element27is connected to the cell voltage input terminal32. Namely, one end of the sample-and-hold switch42is connected to the positive electrode of the corresponding battery cell12via the resistor element27.

One end of the resistor element28is connected to the positive electrode of the battery cell13. The other end of the resistor element28is connected to the cell voltage input terminal33. Namely, one end of the sample-and-hold switch43is connected to the positive electrode of the corresponding battery cell13via the resistor element28.

Hereinafter, operation of the battery monitoring device100A according to the second exemplary embodiment will be described. In the battery monitoring device100A according to the second exemplary embodiment, operation of the battery monitoring IC3during detection of the cell voltages of the battery cells11,12, and13is the same as of the battery monitoring device100according to the first exemplary embodiment, and therefor is illustrated in the timing chart ofFIG. 3.

First, the control circuit7controls the sample-and-hold switches41,42, and43to be turned ON simultaneously. In a case in which the sample-and-hold switch41is turned ON, the capacitor21and the battery cell11are connected to each other via the resistor element26. A filter is configured by the capacitor21and the resistor element26, and the capacitor21is charged by the cell voltage of the battery cell11in which high frequency noise is removed and is averaged.

Similarly, in a case in which the sample-and-hold switch42is turned ON, the capacitor22and the battery cell12are connected to each other via the resistor element27. A filter is configured by the capacitor22and the resistor element27, and the capacitor22is charged by the cell voltage of the battery cell12in which high frequency noise is removed and is averaged.

In a case in which the sample-and-hold switch43is turned ON, the capacitor23and the battery cell13are connected to each other via the resistor element28. A filter is configured by the capacitor23and the resistor element28, and the capacitor23is charged by the cell voltage of the battery cell13in which high frequency noise is removed and is averaged.

The control circuit7, in a case in which charging of the capacitors21,22,23are completed, controls the sample-and-hold switches41,42, and43to be turned OFF simultaneously. Accordingly, in a case in which the sample-and-hold switches41,42, and43are turned from ON to OFF at the same timing, cell voltages of the battery cells11,12, and13are sampled at the same point in time. Note that, in this sampling process, the capacitors21,22, and23need to be full charged states, and thus, timings when the sample-and-hold switch41,42, and43are turned ON does not need to be the same.

Next, the control circuit7controls, out of the switches configuring the cell selection switch group5, the low potential side switch51and the high potential side switch56to be turned ON. Thus, the high potential side input end a1of the signal processing circuit6is connected to the capacitor21, and the low potential side input end a2of the signal processing circuit6is connected to the ground potential. Namely, the voltage corresponding to the cell voltage of the battery cell11, in which high frequency noise is removed and is averaged, is input to the signal processing circuit6. The signal processing circuit6performs impedance conversion process, level-shift process, and digital conversion process to the input voltage, and outputs the output signal indicating the cell voltage of the battery cell11from the output terminal35. Note that, since the signal processing circuit6receives the voltages input to the input ends a1and a2by the buffer amplifier61having high input impedance, the charges stored in the capacitor21are kept without being discharged.

Next, the control circuit7controls, out of the switches configuring the cell selection switch group5, the low potential side switch52and the high potential side switch57to be turned ON. Thus, the high potential side input end a1of the signal processing circuit6is connected to the capacitor22, and the low potential side input end a2of the signal processing circuit6is connected to the capacitor21. Namely, the voltage corresponding to the cell voltage of the battery cell12, in which high frequency noise is removed and is averaged, is input to the signal processing circuit6. The signal processing circuit6performs impedance conversion process, level-shift process, and digital conversion process to the input voltage, and outputs the output signal indicating the cell voltage of the battery cell12from the output terminal35. Note that, since the signal processing circuit6receives the voltages input to the input ends a1and a2by the buffer amplifier61having high input impedance, the charges stored in the capacitor21and22are kept without being discharged.

Next, the control circuit7controls, out of the switches configuring the cell selection switch group5, the low potential side switch53and the high potential side switch58to be turned ON. Thus, the high potential side input end a1of the signal processing circuit6is connected to the capacitor23, and the low potential side input end a2of the signal processing circuit6is connected to the capacitor22. Namely, the voltage corresponding to the cell voltage of the battery cell13, in which high frequency noise is removed and is averaged, is input to the signal processing circuit6. The signal processing circuit6performs impedance conversion process, level-shift process, and digital conversion process to the input voltage, and outputs the output signal indicating the cell voltage of the battery cell13from the output terminal35. Note that, since the signal processing circuit6receives the voltage input to the input ends a1and a2by the buffer amplifier61having high input impedance, the charges stored in the capacitor22and23are kept without being discharged.

As described above, in the battery monitoring device100A according to the second exemplary embodiment of the present disclosure, filter circuits are configured by the capacitors21,22,23and the resistor elements26,27,28in a case in which the cell voltages of the battery cells11,12, and13are sampled. Thus, since the capacitors21,22, and23are charged by the cell voltages in which the high frequency noise are removed and are averaged, the second exemplary embodiment may further improve detection accuracy of the cell voltages. In addition, in the battery monitoring device100A according to the present exemplary embodiment, since the capacitors21,22, and23have both of a sampling function for holding the cell voltage and a filter function for removing high frequency noise, the filter function may be achieved only by inserting the resistor elements26,27, and28without separately adding the capacitors for filtering.

Note that, in the exemplary embodiment, a case in which the resistor elements26,27, and28are provided outside the battery monitoring IC3has been described. However, the resistor elements26,27, and28may be provided inside the battery monitoring IC3.

In the above first and second exemplary embodiments, cases in which the A/D converter70is included in the battery monitoring IC3have been described. However, the present disclosure is not limited thereto. For example, the A/D converter70may be included inside a microcomputer communicatively connected to the battery monitoring IC3.

In the above first and second exemplary embodiments, for example, in a case in which the cell voltage of the battery cell12is detected, the low potential side switch52and the high potential side switch57are turned ON, the voltage of the capacitor21and the voltage of the capacitor22are simultaneously input to the signal processing circuit6, and a difference of the voltages input is processed by the signal processing circuit6. However, the present disclosure is not limited thereto. Namely, the voltage of the capacitor21and the voltage of the capacitor22may be sequentially input to the signal processing circuit6, and the difference between the voltages may be obtained inside the signal processing circuit6.

Note that, the battery monitoring IC3is an example of the semiconductor device according to the present disclosure. The battery monitoring device100and100A are examples of the battery monitoring device according to the present disclosure. The battery cells11,12, and13are examples of the battery cell according to the present disclosure. The capacitors21,22, and23are examples of the charge storage section according to the present disclosure. The sample-and-hold switches41,42, and43are examples of the first switch according to the present disclosure. The high potential side switches56,57, and58are examples of the second switch according to the present disclosure. The low potential side switches51,52, and53are examples of the third switch according to the present disclosure. The signal processing circuit6is an example of the processing section according to the present disclosure. The control circuit7is an example of the control section according to the present disclosure. The buffer amplifier61is an example of the buffer amplifier according to the present disclosure. The cell voltage input terminals31,32, and33are examples of the first terminal according to the present disclosure. The capacitor connection terminals36,37, and38are examples of the second terminal according to the present disclosure. The input end a1is an example of the first input end according to the present disclosure. The input end a2is an example of the second input end according to the present disclosure. The resistor elements26,27, and28are examples of the resistor element according to the present disclosure.