Switching device of digital amplifier and method for driving the same

A switching device of a digital amplifier and a method for controlling the same are disclosed. In accordance with the present invention, a linearity is maintain even for a short pulse width since a data signal having a pulse width shorter than a predetermined length. Moreover, when an MLP signal is located at both sides of a compensating signal without overlapping with each other, a problem due to a common mode may be prevented.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of Korean Patent Applications No. 10-2010-0007404 filed on Jan. 27, 2010 and 10-2010-0078207 filed on Oct. 13, 2010, which are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a switching device of a digital amplifier and a method for controlling the same, and more particularly to a switching device of a digital amplifier and a method for controlling the same wherein a distortion occurring in a digital amplifier due to a pulse width of a PWM signal may be prevented using an MLP signal and a compensating signal.

2. Description of the Related Art

A digital amplifier also known as class D amplifier transmits an electric power by switching transistors. Since the digital amplifier is not only highly efficient but also does not need a heat sink, the digital amplifier may be easily miniaturized.

FIG. 1is block diagram exemplifying a conventional digital amplifier.

Referring toFIG. 1, a PCM (Pulse Code Modulation) signal is converted to a PWM (Pulse Width Modulation) signal by a PWM converter20. As shown inFIG. 2, the PWM signal has a pulse width corresponding to the amplitude of an analog signal. The PWM signal shown inFIG. 2is a BD modulated PWM signal which has a value of +1, a value of zero or a value of −1 according to the amplitude of the analog signal.

The PWM signal is applied to and drives a switch module30. When the PWM signal has the value of +1, the PWM converter20outputs a logical high as a signal P and a logical low as a signal N. On the contrary, when the PWM signal has the value of −1, the PWM converter20outputs the logical low as the signal P and the logical high as the signal N. When the PWM signal has the value of zero, the PWM converter20outputs the logical low as the signal P and the logical low as the signal N.

A signal A and a signal B outputted by the switch module30driven by the signal P and the signal N are passed through a low-pass filter40to be applied to a speaker50. A difference between the signal A and the signal B, i.e., VDD, zero or −VDD is applied to the low-pass filter40.

The switch module30is composed of semiconductors. Particularly, as shown inFIG. 1, the switch module30may be embodied using the plurality of semiconductors.

The semiconductors included in the switch module30perform switching operations according to a signal applied to a gate of the semiconductors. When the pulse width of the PWM signal applied to the gate of the semiconductors is sufficiently long, i.e., when the pulse width of the PWM signal is sufficiently longer than a switching time of the semiconductors, the semiconductors perform the switching operations normally. However, when the pulse width of the PWM signal is shorter than a predetermined length, the semiconductors cannot perform the switching operations normally resulting in a distortion of an output signal of the switch module30.

Particularly, since the pulse width of the PWM signal is very short about a zero-crossing (shown inFIG. 2as dotted line) of the analog signal, the distortion may occur in the output signal of the switch module30. Therefore, a sound quality of audio signal outputted by the speaker50may be degraded.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a switching device of a digital amplifier and a method for controlling the same wherein a distortion occurring in a digital amplifier due to a pulse width of a PWM signal may be prevented using an MLP signal and a compensating signal.

In order to achieve above-described object of the present invention, there is provided a switching device for driving a load according to a data signal included in a frame of a PWM signal, comprising: a controller for outputting an MLP signal; and a compensating signal when [data]≦[MPC] is satisfied, wherein a pulse width of the compensating signal is sum of [data] and [MLP]; and a switch module for performing a switching operation according to the MLP signal and the compensating signal (where [MLP] is a pulse width of a reference pulse, [data] and [MPC] are pulse widths of the data signal and the MLP signal, respectively).

Preferably, [MPC] satisfies ([MLP]+[MPC])≦(a length of the frame−[MPW]) (where [MPW] is a minimum pulse width).

Preferably, the MLP signal and the compensating signal are located within the frame, and overlap with each other with respect to a time axis.

Preferably, the MLP signal and the compensating signal are located within the frame, and not overlapping with each other with respect to a time axis.

Preferably, an interval between the MLP signal and the compensating signal is zero.

Preferably, an interval between the MLP signal and the compensating signal is non-zero.

Preferably, the MLP signal is located before and after the compensating signal with each other with respect to the time axis.

There is also provided a switching device for driving a load according to a data signal included in a frame of a PWM signal, comprising: a controller for outputting an MLP signal; and a first compensating signal when [data]≦[MPC] is satisfied, wherein a pulse width of the first compensating signal is sum of [data] and [MLP], a second compensating signal; and a third compensation signal when [MPC]<[data]≦([MPC]+[MLP]) is satisfied, wherein a pulse width of the second compensation signal is a sum of [MPC] and [MLP], and a pulse width of the third compensation is [MLP]−([data]−[MPC]); and a switch module for performing a switching operation according to the MLP signal, the first compensating signal, the second compensating signal and the third compensating signal (where [MLP] is a pulse width of a reference pulse, [data] and [MPC] are pulse widths of the data signal and the MLP signal, respectively).

Preferably, [MPC] is satisfied [MLP]+[MPC]≦(a length of the frame−[MPW]) (where [MPW] is a minimum pulse width).

Preferably, the MLP signal, each of the first compensating signal, the second compensating signal and the third compensating signal is located within the frame, and overlaps with each other with respect to a time axis.

Preferably, each of the first compensating signal, the second compensating signal and the third compensating signal is located within the frame, and not overlapping with each other with respect to a time axis.

Preferably, intervals between the MLP signal and the first compensating signal, and the second compensating signal and the third compensation signal are zero, respectively.

Preferably, intervals between the MLP signal and the first compensating signal, and the second compensating signal and the third compensation signal are non-zero, respectively.

Preferably, the MLP signal is located before and after the first compensating signal with each other with respect to the time axis.

In order to achieve above-described object of the present invention, there is provided a method for driving a switching device driving a load according to a data signal included in a frame of a PWM signal, the method comprising steps of: (a) determining whether [data]≦[MPC] is satisfied; (b) outputting an MLP signal; and a compensating signal when [data]≦[MPC] is satisfied, wherein a pulse width of the compensating signal is sum of [data] and [MLP]; and (c) performing a switching operation by applying the MLP signal and the compensating signal outputted in the step (b) on a switch module.

Preferably, the MLP signal and the compensating signal are located within the frame, and overlap with each other with respect to a time axis.

Preferably, the MLP signal and the compensating signal are located within the frame, and not overlapping with each other with respect to a time axis.

Preferably, an interval between the MLP signal and the compensating signal is zero.

Preferably, an interval between the MLP signal and the compensating signal is non-zero.

Preferably, the MLP signal is located before and after the compensating signal with each other with respect to the time axis.

In order to achieve above-described object of the present invention, there is provided a method for driving a switching device driving a load according to a data signal included in a frame of a PWM signal, the method comprising steps of: (a) determining whether [data]≦[MPC] is satisfied; (b) outputting an MLP signal; and a first compensating signal when [data]≦[MPC] is satisfied, wherein a pulse width of the first compensating signal is sum of [data] and [MLP]; (c) performing a switching operation according to the MLP signal and the compensating signal outputted in the step (b); (d) determining whether [MPC]<[data]≦[MPC]+[MLP] is satisfied; (e) outputting a second compensating signal; and a third compensating signal when [MPC]<[data]≦[MPC]+[MLP] is satisfied, wherein a pulse width of the second compensating signal is sum of [MPC] and [MLP], and a pulse width of the third compensating signal is [MLP]−([data]−[MPC]); and (f) performing the switching operation according to the second compensating signal and the third compensating signal outputted in the step (e) (where [MLP] is a pulse width of a reference pulse, [data] and [MPC] are pulse widths of the data signal and the MLP signal, respectively).

Preferably, each of the MLP signal, the first compensating signal, the second compensating signal and the third compensating signal is located within the frame, and overlaps with each other with respect to a time axis.

Preferably, each of the first compensating signal, the second compensating signal and the third compensating signal is located within the frame, and not overlapping with each other with respect to a time axis.

Preferably, intervals between the MLP signal and the first compensating signal and the second compensating signal and the third compensation signal are zero, respectively.

Preferably, intervals between the MLP signal and the first compensating signal and the second compensating signal and the third compensation signal are non-zero, respectively.

Preferably, the MLP signal is located before and after the first compensating signal with each other with respect to the time axis.

DETAILED DESCRIPTION OF THE EMBODIMENTS

A switching device of a digital amplifier and a method for controlling the same in accordance with the present invention will be described in detail with reference to accompanied drawings.

Definitions of terms used herein will be given prior to detailed description of the present invention.

[MLP] is the minimum number of unit pulses that ensures linearity. As shown inFIG. 3, when a pulse width of an input pulse inputted in a switching module is greater than [MLP], a linear relationship is established between the pulse width inputted in the switching module and a pulse width of an output pulse outputted therefrom. When the pulse width inputted in the switching module is less than [MLP], a non-linear relationship is established between the pulse width inputted in the switching module and the pulse width outputted therefrom. That is, [MLP] is the minimum number of unit pulses for establishing the linear relationship between pulse widths of the input pulse and the output pulse.

An MLP signal is a pulse signal wherein a length of which is [MLP]. For instance, when [MLP]=3, the MLP signal has the length of 3 clocks.

[MPC] is the number of unit pulses that determines whether to compensate or not, i.e., a reference pulse width. For instance, when [MPC]=120, the pulse which has the pulse width equal to or less than 120 clocks is compensated, and the pulse which has the pulse width greater than 120 clocks is not compensated.

[data] is a pulse width of a data signal included in a frame of a PWM signal.

A switching device in accordance with the present invention is described herein after in more detail with reference toFIG. 4.

FIG. 4is a block diagram exemplifying a switching device100in accordance with the present invention.

Referring toFIG. 4, the switching device100in accordance with the present invention comprises a controller110and a switch module120.

The controller110receives a PWM signal from a PWM converter200, which converts a PCM signal to the PWM signal. The controller110processes the PWM signal to generate a signal P and a signal N for driving the switch module120.

The switch module120performs a switching operation according to the signal P and the signal N outputted from the controller110. The switch module120outputs a signal A and a signal B as output signals. The signal A and the signal B is passed through a low-pass filter210to be drive a speaker220.

The switch module120may comprise an H-bridge switch circuit as shown inFIG. 1.

A driving operation of the switch module120wherein the controller110processes the PWM signal to drive the switch module120, and the signal A and the signal B as output signals of the switch module120are described hereinafter in more detail.

FIGS. 5athrough5dare graphs exemplifying a data signal, an MLP signal and a compensating signal in accordance with a first embodiment of the present invention, where [MLP]=3 and [MPC]=5.

FIG. 5aillustrates a graph wherein a case where the pulse width of the data signal included in the frame of the PWM signal is six, i.e., [data]=6, and the amplitude thereof is +1. Referring toFIG. 5a, since [data] is greater than [MPC] (=5), the controller110outputs the data signal as the signal A and zero as the signal B.

FIG. 5billustrates a graph wherein a case where the pulse width of the data signal included in the frame of the PWM signal is six, i.e., [data]=6, and the amplitude thereof is −1. Referring toFIG. 5b, since [data] is greater than [MPC] (=5), the controller110outputs zero as the signal A and the data signal as the signal B.

FIG. 5cillustrates a graph wherein a case where the pulse width of the data signal included in the frame of the PWM signal is two, i.e., [data]=2, and the amplitude thereof is +1. Referring toFIG. 5c, since [data] is equal to or less than [MLP] (=3), the controller110outputs the compensating signal as the signal A having a pulse width of [data]+[MLP] and outputs the MLP signal as the signal B.

That is, the compensating signal having the pulse width of 5 is outputted as the signal A and the MLP signal having the pulse width of 3 is outputted as the signal B. Since [the signal A−the signal B] is applied to the speaker220, the signal applied to the speaker220is substantially same as the data signal.

FIG. 5dillustrates a graph wherein a case where the pulse width of the data signal included in the frame of the PWM signal is two, i.e., [data]=2, and the amplitude thereof is Referring toFIG. 5d, since [data] is equal to or less than [MLP] (=5), the controller110outputs the MLP signal as the signal A and outputs the compensating signal as the signal B having the pulse width of [data]+[MLP].

That is, the MLP signal having the pulse width of 3 is outputted as the signal A and the compensating signal having the pulse width of 5 is outputted as the signal B. Since [the signal A−the signal B] is applied to the speaker220, the signal applied to the speaker220is substantially same as the data signal.

As shown inFIGS. 5athrough5d, when [data] is greater than [MPC], the controller110outputs the data signal, and when [data] is equal to or less than [MPC], the controller110outputs the MLP signal and the compensating signal wherein the pulse width of the compensating signal is [data]+[MLP], to drive the switch module120.

FIGS. 6athrough6dare graphs exemplifying the data signal, the MLP signal and compensating signals in accordance with a second embodiment of the present invention, where [MLP]=3 and [MPC]=5.

FIG. 6aillustrates a graph wherein a case where the pulse width of the data signal included in the frame of the PWM signal is two, i.e., [data]=2, and the amplitude thereof is +1. Referring toFIG. 6a, since [data] is equal to or less than [MPC] (=5), the controller110outputs the first compensating signal as the signal A having the pulse width of [data]+[MLP], and outputs the MLP signal as the signal B.

That is, the first compensating signal having the pulse width of 5 is outputted as the signal A, and the MLP signal having the pulse width of 3 is outputted as the signal B. Since [the signal A−the signal B] is applied to the speaker220, the signal applied to the speaker220is substantially same as the data signal.

FIG. 6billustrates a graph wherein a case where the pulse width of the data signal included in the frame of the PWM signal is two, i.e., [data]=2, and the amplitude thereof is −1. Referring toFIG. 6b, since [data] is equal to or less than [MPC] (=5), the controller110outputs the MLP signal as the signal A and outputs the first compensating signal as the signal B having the pulse width of [data]+[MLP].

That is, the MLP signal having the pulse width of 3 is outputted as the signal A and the first compensating signal having the pulse width of 5 is outputted as the signal B. Since [the signal A−the signal B] is applied to the speaker220, the signal applied to the speaker220is substantially same as the data signal.

FIG. 6cillustrates a graph wherein a case where the pulse width of the data signal included in the frame of the PWM signal is six, i.e., [data]=6, and the amplitude thereof is +1. Referring toFIG. 6c, since [data] is greater than [MPC] but equal to or less than [MPC]+[MLP] (=8), the controller110outputs the second compensating signal as the signal A having the pulse width of [MPC]+[MLP] (=8) and outputs the third compensating signal as the signal B having the pulse width of [MLP]−([data]−[MPC]) (=2).

Since [the signal A−the signal B] is applied to the speaker220, the signal applied to the speaker220is substantially same as the data signal.

FIG. 6dillustrates a graph wherein a case where the pulse width of the data signal included in the frame of the PWM signal is six, i.e., [data]=6, and the amplitude thereof is −1. Referring toFIG. 6d, since [data] is greater than [MPC] but equal to or less than [MPC]+[MLP], the controller110outputs the third compensating signal as the signal A having the pulse width of [MLP]−([data]−[MPC]) (=2) and outputs the second compensating signal as the signal B having the pulse width of [MPC]+[MLP] (=8).

Since [the signal A−the signal B] is applied to the speaker220, the signal applied to the speaker220is substantially same as the data signal.

FIG. 6eillustrates a graph wherein a case where the pulse width of the data signal included in the frame of the PWM signal is seven, i.e., [data]=7, and the amplitude thereof is +1. Referring toFIG. 6e, since [data] is greater than [MPC] but equal to or less than [MPC]+[MLP] (=8), the controller110outputs the second compensating signal as the signal A having the pulse width of [MPC]+[MLP] (=8) and outputs the third compensating signal as the signal B having the pulse width of [MLP]−([data]−[MPC]) (=1).

Since [the signal A−the signal B] is applied to the speaker220, the signal applied to the speaker220is substantially same as the data signal.

FIG. 6fillustrates a graph wherein a case where the pulse width of the data signal included in the frame of the PWM signal is seven, i.e., [data]=7, and the amplitude thereof is −1. Referring toFIG. 6f, since [data] is greater than [MPC] but equal to or less than [MPC]+[MLP] (=8), the controller110outputs the third compensating signal as the signal A having the pulse width of [MLP]−([data]−[MPC]) (=1) and outputs the second compensating signal as the signal B having the pulse width of [MPC]+[MLP] (=8).

Since [the signal A−the signal B] is applied to the speaker220, the signal applied to the speaker220is substantially same as the data signal.

FIG. 6gillustrates a graph wherein a case where the pulse width of the data signal included in the frame of the PWM signal is eight, i.e., [data]=8, and the amplitude thereof is +1. Referring toFIG. 6g, since [data] is greater than [MPC] but equal to or less than [MPC]+[MLP] (=8), the controller110outputs the second compensating signal as the signal A having the pulse width of [MPC]+[MLP] (=8) and outputs the third compensating signal as the signal B having the pulse width of [MLP]−([data]−[MPC]) (=0).

Since [the signal A−the signal B] is applied to the speaker220, the signal applied to the speaker220is substantially same as the data signal.

FIG. 6hillustrates a graph wherein a case where the pulse width of the data signal included in the frame of the PWM signal is eight, i.e., [data]=8, and the amplitude thereof is −1. Referring toFIG. 6h, since [data] is greater than [MPC] but equal to or less than [MPC]+[MLP] (=8), the controller110outputs the third compensating signal as the signal A having the pulse width of [MLP]−([data]−[MPC]) (=0) and outputs the second compensating signal as the signal B having the pulse width of [MPC]+[MLP] (=8).

Since [the signal A−the signal B] is applied to the speaker220, the signal applied to the speaker220is substantially same as the data signal.

FIG. 6iillustrates a graph wherein a case where the pulse width of the data signal included in the frame of the PWM signal is nine, i.e., [data]=9, and the amplitude thereof is +1. Referring toFIG. 6i, since [data] is greater than [MPC]+[MLP], the controller110outputs the data signal as the signal A and zero as the signal B.

FIG. 6jillustrates a graph wherein a case where the pulse width of the data signal included in the frame of the PWM signal is nine, i.e., [data]=9, and the amplitude thereof is −1. Referring toFIG. 6j, since [data] is greater than [MPC]+[MLP] (=8), the controller110outputs zero as the signal A and the data signal as the signal B.

As shown inFIGS. 6athrough6j, when [data] is less than [MPC], the controller110outputs the MLP signal; and the first compensating signal wherein the pulse width of the first compensating signal is [data]+[MLP]. When [data] is greater than [MPC] but equal to or less than [data]+[MLP], the controller110outputs the second compensating signal wherein the pulse width of the second compensating signal is [MPC]+[MLP]; and the third compensating signal wherein the pulse width of the third compensating signal is [MLP]−([data]−[MPC]) to drive the switch module120. That is, with respect to [MPC], the data signal is compensated for in the amount of [MLP] when [data]≦[MPC], and the data signal is compensated until [MLP]−([data]−[MPC]) is zero when [MPC]<[data] as increasing [data] increases. When [data]>[MPC]+[MLP] is satisfied as [data] increases further, the data signal is outputted without compensation.

[MPC] may vary according to the PWM signal used. For instance, when a length of one frame is 128 clocks, ([MPC]+[MLP])≦(128−[MPW]) must be satisfied. MPW is a minimum pulse width wherein a pulse width of a longest pulse included in the frame is 128 clocks when the length of one frame is 128 clocks, and MPW is 4, for example. Therefore, ([MPC]+[MLP])≦124 is satisfied, when [MLP]=3 is satisfied, and [MPC] may be selected from a value smaller than 121 clocks.

FIGS. 7athrough7care graphs exemplifying the data signal, the MLP signal and the compensating signal in accordance with a third embodiment of the present invention, where [MLP]=3 and [MPC]=5.

In accordance with the third embodiment of the present invention, when [data] is greater than [MPC], the controller110outputs the signals same as the signal A and the signal B shown inFIGS. 5aand5b.

When [data] is equal to or less than [MPC], the controller110outputs the signals same as the signal A and the signal B shown inFIGS. 7athrough7c.

FIG. 7aillustrates a graph wherein a case where the pulse width of the data signal included in the frame of the PWM signal is two, i.e., [data]=2, and the amplitude thereof is +1. Referring toFIG. 7a, since [data] is equal to or less than [MPC] (=5), the controller110outputs the compensating signal as the signal A having the pulse width of [data]+[MLP] and the MLP signal as the signal B.

That is, the compensating signal having the pulse width of 5 is outputted as the signal A and the MLP signal having the pulse width of 3 is outputted as the signal B. Since [the signal A−the signal B] is applied to the speaker220, the signal applied to the speaker220is substantially same as the data signal.

While the MLP signal and the compensating signal shown inFIG. 5coverlap with each other with respect to a time axis, the MLP signal and the compensating signal shown inFIG. 7ado not overlap with each other with respect to the time axis. Particularly, an interval between the MLP signal and the compensating signal shown in7ais zero. That is, the MLP signal is adjacent to the compensating signal.

FIG. 7billustrates a graph wherein a case where the pulse width of the data signal included in the frame of the PWM signal is two, i.e., [data]=2, and the amplitude thereof is −1. Referring toFIG. 7b, since [data] is equal to or less than [MPC] (=5), the controller110outputs the MLP signal as the signal A and outputs the compensating signal as the signal B having the pulse width of [data]+[MLP].

That is, the MLP signal having the pulse width of 3 is outputted as the signal A and the compensating signal having the pulse width of 5 is outputted as the signal B. Since [the signal A−the signal B] is applied to the speaker220, the signal applied to the speaker220is substantially same as the data signal.

While the MLP signal and the compensating signal shown inFIG. 5doverlap with each other with respect to the time axis, the MLP signal and the compensating signal shown inFIG. 7bdo not overlap with each other with respect to the time axis. Particularly, the interval between the MLP signal and compensating signal shown inFIG. 7bis zero. That is, the MLP signal is adjacent to the compensating signal.

FIG. 7cillustrates a graph wherein a case where the pulse width of the data signal included in the frame of the PWM signal is two, i.e., [data]=2, and the amplitude thereof is +1. Referring toFIG. 7c, since [data] is equal to or less than [MPC] (=5), the controller110outputs the compensating signal as the signal A having the pulse width of [data]+[MLP] and the MLP signal as the signal B.

That is, the compensating signal having the pulse width of 5 is outputted as the signal A and the MLP signal having the pulse width of 3 is outputted as the signal B. Since [the signal A−the signal B] is applied to the speaker220, the signal applied to the speaker220is substantially same as the data signal.

The MLP signal and the compensating signal shown inFIG. 7cdo not overlap with each other and the interval between the MLP signal and the compensating signal is also non-zero. That is, the MLP signal is outputted in a manner that a predetermined time gap exists before and after the compensating signal with respect to the time axis between the MLP signal and the compensating signal.

FIGS. 8athrough8care graphs exemplifying the data signal, the MLP signal and compensating signals in accordance with a fourth embodiment of the present invention, where [MLP]=3 and [MPC]=5.

The fourth embodiment shown inFIG. 8adiffers from the second embodiment shown inFIG. 6ain that the MLP signal and the first compensating signal do not overlap with each other. Even when the MLP signal and the first compensating signal do not overlap with each other, the signal applied to the speaker220is substantially same as the data signal because [the signal A−the signal B] is applied to the speaker220. Therefore, in view of the signal applied to the speaker220, the fourth embodiment shown inFIG. 8ais substantially same as the second embodiment shown inFIG. 6a.

Particularly, an interval between the MLP signal and the first compensating signal shown inFIG. 8ais zero. That is, the MLP signal is adjacent to the compensating signal. However, it is not necessary for the MLP signal to be adjacent to the first compensating signal, and it is sufficient if the MLP signal and the compensating signal are located within the same frame.

Similar to the fourth embodiment shown inFIG. 8a, the MLP signal and the first compensating signal of the second embodiment shown inFIG. 6bdo not overlap with each other.

The fourth embodiment shown inFIG. 8bdiffers from the second embodiment shown inFIG. 6cis that the first compensating signal and the second compensating signal do not overlap with each other. Even when the first compensating signal and the second compensating signal do not overlap with each other, the signal applied to the speaker220is substantially same as the data signal because [the signal A−the signal B] is applied to the speaker220.

Particularly, the interval between the first compensating signal and the second compensating signal shown inFIG. 8bis zero. That is, the first compensating signal is adjacent to the second compensating signal. However, it is not necessary for the first compensating signal to be adjacent to the second compensating signal, and it is sufficient if the first compensating signal and the second compensating signal are located within the same frame.

Similar to the fourth embodiment shown inFIG. 8b, the first compensating signal and the second compensating signal of the second embodiment shown inFIG. 6ddo not overlap with each other.

The fourth embodiment shown inFIG. 8cdiffers from the second embodiment shown inFIG. 6ein that the first compensating signal and the second compensating signal do not overlap with each other. Even when the first compensating signal and the second compensating signal do not overlap with each other, the signal applied to the speaker220is substantially same as the data signal because [the signal A−the signal B] is applied to the speaker220. Therefore, in view of the signal applied to the speaker220, the fourth embodiment shown inFIG. 8cis substantially same as the second embodiment shown inFIG. 6e.

Particularly, the interval between the first compensating signal and the second compensating signal shown inFIG. 8cis zero. That is, the first compensating signal is adjacent to the second compensating signal. However, it is not necessary for the first compensating signal to be adjacent to the second compensating signal, and it is sufficient if the first compensating signal and the second compensating signal are located within the same frame.

Similar to the fourth embodiment shown inFIG. 8c, the first compensating signal and the second compensating signal of the second embodiment shown inFIG. 6fdo not overlap with each other.

When the MLP signal is located at both sides of the compensating signal without overlapping with each other similar to the third embodiment shown inFIGS. 7athrough7cand the fourth embodiment shown inFIGS. 8athrough8c, a problem due to a common mode wherein both of the signal A and the signal B is +1 may be prevented.

FIG. 9is a graph exemplifying a relationship between pulse widths of an input signal and an output signal in accordance with the present invention.

As shown inFIG. 9, the linearity between the pulse widths of the input signal and the output signal is maintained even when the input pulse is less than [MLP].

FIG. 10is a flow diagram illustrating a method for controlling the switching device in accordance with the first embodiment of the present invention.

Referring toFIG. 10, the data signal included in the frame of the PWM signal transmitted by the PWM converter is received (S100).

Thereafter, whether [data]≦[MPC] is satisfied is determined (S110).

When [data]>[MPC] is satisfied, the controller outputs the signal A and the signal B shown inFIGS. 5aand5b(S150). Since the signal A and the signal B outputted in the step S150are described above with reference toFIGS. 5aand5b, detailed descriptions of the signal A and the signal B are omitted.

When [data]≦[MPC] is satisfied, the controller generates and outputs the MLP signal and the compensating signal shown inFIGS. 5c,5dand7athrough7c(S120and S130). The compensating signal has the pulse width of [data]+[MLP]. The MLP signal and the compensating signal outputted in the step S130are described above with reference toFIGS. 5c,5dand7athrough7c, detailed descriptions of the MLP signal and the compensating signal are omitted.

Thereafter, the switch module is driven by the output signal of the controller (S140). The output signal of the switch module is passed through a low-pass filter to be driven a speaker.

FIG. 11is a flow diagram illustrating a method for controlling the switching device in accordance with the second embodiment of the present invention.

Referring toFIG. 11, the data signal included in the frame of the PWM signal transmitted by the PWM converter is received (S200).

Thereafter, whether [data]≦[MPC] is satisfied is determined (S210).

When [data]≦[MPC] is satisfied, the MLP signal and the first compensating signal having the pulse width of [data]+[MLP] are outputted (S220). That is, the controller outputs the signal A and the signal B shown inFIGS. 6aand6b. Since the signal A and the signal B outputted in the step S220are described above with reference toFIGS. 6aand6b, detailed descriptions of the signal A and the signal B are omitted.

Thereafter, the switching module performs the switching operating according to the MLP signal and the first compensating signal outputted in the step S220(S230).

When [data]≦[MPC] is not satisfied, whether [MPC]<[data]≦[MPC]+[MLP] is satisfied is determined (S240).

When [MPC]<[data]≦[MPC]+[MLP] is satisfied, the second compensating signal having the pulse width of [MPC]+[MLP] and the third compensating signal having the pulse width of [MLP]−([data]−[MPC]) are outputted (S250). That is, the controller outputs the signal A and the signal B shown inFIGS. 6cthrough6h. Since the signal A and the signal B outputted in the step S250are described above with reference toFIGS. 6cthrough6h, detailed descriptions of the signal A and the signal B are omitted.

Thereafter, the switching module performs the switching operating according to the second compensating signal and the third compensating signal outputted in the step S250(S260).

When [MPC]<[data]≦[MPC]+[MLP] is not satisfied, i.e., satisfying [data]>[MPC]+[MLP], the data signal and a signal having the pulse width of zero are outputted (S270). That is, the controller outputs the signal A and the signal B shown inFIGS. 6ithrough6j. Since the signal A and the signal B outputted in the step S270are described above with reference toFIGS. 6ithrough6j, detailed descriptions of the signal A and the signal B are omitted.

Thereafter, the switching module performs the switching operating according to the data signal and the signal having the pulse width of zero (S280).

The switching device of the digital amplifier and the method for controlling the same in accordance with the present invention has following advantages.

In accordance with the present invention, the linearity is maintain even for the short pulse width since the data signal having the pulse width shorter than a predetermined length. Therefore, the distortion occurring during the driving of the speaker is prevented.

Particularly, when the MLP signal is located at both sides of the compensating signal without overlapping with each other, the problem due to the common mode may be prevented thereby improving a characteristic of the digital amplifier.

While the present invention has been particularly shown and described with reference to the preferred embodiment thereof, it will be understood by those skilled in the art that various changes in form and details may be effected therein without departing from the spirit and scope of the invention as defined by the appended claims.