Multiplexing input circuit

An input circuit having a plurality of channels, each channel includes a conductor line, first and second transistors inserted in series into the conductor line and a third transistor. When a channel is not selected, the first and second transistors are turned off and the third transistor is turned on to clamp the conductor line at a predetermined constant voltage. When a channel is selected, the third transistor is turned off and first and second transistors are turned on to transfer the corresponding information input therethrough.

BACKGROUND OF THE INVENTION 
(1) Field of the Invention 
The present invention relates to an input circuit, more particularly to an 
input circuit constructed having a plurality of channels provided with 
input ports and input/outputs ports and where the plurality of channels 
deal mainly with analog signals. 
(2) Description of the Prior Art 
A recent trend in many fields is for automatic data processing and, 
therefore, for introduction of microcomputers and the like. Such data 
processing involves a great deal of information. The data is input one by 
one and successively processed. To input the information, an input circuit 
having a plurality of channels is usually used. Each of the plurality of 
channels transfers certain kinds of information, designated thereto in 
advance, to a predetermined internal circuit at specified timings. 
Such an input circuit is fabricated as an integrated circuit (IC). The 
plurality of channels, each including, for example, one or more 
metal-oxide-semiconductor (MOS) transistors, must be arranged with a very 
small pitch therebetween. This, contrary to the desired electrical 
independence of the plurality of channels, results in increased manual 
interference between, which produces undesired noise such as crosstalk. 
The undesired noise reduces the accuracy of the information input to the 
circuit and the accuracy of the data processing. 
The above-mentioned problem will be analyzed in greater detail later, but, 
in conclusion, it is effective to fabricate the input circuit so as to, 
first, prevent a high voltage signal on one channel from influencing 
neighboring channels and, second, make the voltage level of each channel 
stable. 
Conventionally, this is done by arranging the plurality of channels with a 
relatively large pitch therebetween. This, however, is disadvantageous 
from the viewpoint of achieving high IC density. 
SUMMARY OF THE INVENTION 
It is an object of the present invention to fabricate an input circuit so 
as to overcome the problems of mutual interference, crosstalk, incorrect 
input of the information, and reduced data processing accuracy. 
The above object is attained by employing three transistors in each 
channel, each transistor being selectively turned on to fix the voltage of 
conductors at a predetermined level in each of the channels other than a 
selected channel.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
FIG. 1 is a circuit diagram of one example of a prior art input circuit. In 
FIG. 1, reference numeral 11 represents, as a whole, an input circuit. The 
input circuit is constructed with a plurality of channels 12-0, 12-1, 
12-2, - - - 12-n, each having the same construction. Taking the channel 
12-1 as an example, a conductor line 13-1 is arranged therein, one end of 
which is connected to a port 14-1 and the other end of which is connected 
to a node N commonly connected to other channels, i.e., 12-0, 12-2, - - - 
12-n. A transistor 15-1 is inserted in series at the middle of the 
conductor line. 
When the input circuit 11 is mounted on a semiconductor chip provided with 
a microcomputer thereon, a branched route is often introduced, brancing, 
for example, from a portion between the port 14-1 and the transistor 15-1 
and reaching a buffer 16-1. In this case, the port 14-1 functions not only 
as an input port, but also as an input/output port. Incidentally, in this 
figure, the buffer is illustrated specifically only for a buffer 16-n. 
The plurality of channels 12-0 through 12-n are sequentially made active. 
Thus, the information for the channels is input one after another through 
the corresponding activated channel. In order to selectively make the 
plurality of channels active one after another, port selection signals 
PS.sub.0 through PS.sub.n are applied to gates of the transistors 15-0 
through 15-n at predetermined timings. In this case, if, for example, the 
port 14-2 is inherently used as the input/output port, the transistor 15-2 
is maintained in a cut-off state by continuously supplying the signal 
PS.sub.2 having a "L" (low) level. 
The sequentially selected information inputs are supplied one by one to a 
predetermined internal circuit 17 mounted on the same chip. "Predetermined 
internal circuit" means a circuit after the input circuit 11. It is not 
essential in the present invention, however, to clearly define how it is 
constructed and for what purpose it exists. For example, the predetermined 
circuit 17 can be a so-called successive approximation type analog/digital 
(A/D) converter. In such a case, reference numeral 18 corresponds to a 
comparator; 19 to a successive approximation register; and 20 to a 
digital/analog (D/A) converter. The reason why such an A/D converter is 
taken as an example is that the input circuit of the present invention 
exhibits remarkable merits for analog signals as the aforesaid information 
inputs received at the ports 14-0, 14-1, and so on. To be more specific, 
the analog information inputs may indicate unprocessed data, for example, 
humidity measurement data, temperature measurement data, atmospheric 
pressure measurement data, or the like. These analog inputs are usually 
converted into digital signals, then supplied, as corresponding digital 
data, to the microcomputer for processing. However, the input circuit 11 
has a problem, as previously mentioned, with the accuracy of the 
information inputs. For example, when an analog signal is received at the 
port with a voltage level of, for example 1 V, the analog signal 
incorrectly appears at the node N with an error voltage of (1+.alpha.) V. 
The present inventors found through experiments that the noise of 
+.alpha.V is produced when one or more of the ports 14-0 through 14-n are 
used as input/outputs ports. Assuming that, for example, the port 14-2 is 
used as an input/output port and, at the same time, this input/output port 
14-2 receives a digital signal having a magnitude of about 5 V, as in a 
transistor-transistor logic (TTL) IC, the analog signal of, for example 1 
V, inputted from, for example, the port 14-1, varies according to 
(1+.alpha.) V when reaching the node N. The error voltage of +.alpha.V is 
for example, about 10 mV. The value of 10 mV itself is considerably small, 
however, it may result in a 1 bit error when the register 19 of the 
predetermined internal circuit 17 is formed as an 8-bit register and the 
allowable maximum voltage for the A/D conversion voltage is rated at 2.56 
V. 
In the above example, the transistor 15-2 is maintained in a cut-off state, 
since the related port 14-2 is used for the input/output port. Regardless 
of the existence of the cut-off transistor 15-2, the noise of +.alpha.V, 
induced by the digital signal of about 5 V at the port 14-2, is actually 
produced at the node N. 
The reasons for this are not clear, but it is considered that since the 
transistor 15-2 is usually made of a MOS field effect transistor (FET), a 
slight voltage variation due to the 5 V digital signal occurs at the node 
N by way of parasitic capacitors between the source and drain and between 
the drain and gate thereof. The noise caused by the above-mentioned fact 
is still maintained, even if the channels are arranged with a large pitch. 
Also, it is considered that there is interference between the channels. 
This interference may occur regardless of which port is used as the 
input/output port. At the conductor lines 13-0 through 13-n, except for 
the conductor line connected to the input/output port, corresponding 
analog voltages successively appear at high speed. All of the analog 
voltage levels are not constant, but vary in accordance with corresponding 
information inputs. This means that any selected channel is placed under 
circumstances in which the voltage level is not fixed, but always 
variable. This fact also causes an unstable voltage level of each 
information input. 
FIG. 2 is a circuit diagram of an input circuit according to an embodiment 
of the present invention. In FIG. 2, members the same as those of FIG. 1 
are represented by the same reference numerals or symbols (same for later 
figures). Accordingly, is a newly proposed input circuit 11', each of the 
channels is comprised of three transistors. The channels have the same 
construction, so only one of the channels, i.e., the channel 12'-1, is 
referred to in the following explanation. The channel 12'-1 comprises a 
first transistor 21-1, a second transistor 22-1, and a third transistor 
23-1. The first and second transistors 21-1 and 22-1 are inserted in 
series into the conductor line 13-1. The gates of these transistors are 
connected with each other via a gate lead 24-1. A third transistor 23-1 is 
connected between ground GND and a portion of the conductor line 13-1 
arranged between the first and second transistors 21-1 and 22-1. Further, 
a port selection signal PS.sub.1 is applied to the third transistor 23-1 
at its gate. The signal PS.sub.1 has an inverted level with respect to the 
port selection signal PS.sub.1 to be applied to both gates of the first 
and second transistors 21-1 and 22-1. Therefore, both the first and second 
transistors 21-1 and 22-1 are in an on or off state with respect to an off 
or on state of the third transistor 23-1. It should be understood that the 
port selection signals PS.sub.0 through PS.sub.n, also PS.sub.0 through 
PS.sub.n, are selected one after another, as in FIG. 1. FIG. 3 depicts 
waveforms of port selection signals shown in FIGS. 1 and 2. Rows (1), (2), 
(3), (4), (5), and (6) represent the port selection signals PS.sub.1, 
PS.sub.2, PS.sub.n, PS.sub.1, PS.sub.2, and PS.sub.n, respectively. 
Assuming that the channel 12'-1 is in a selection state now, the 
corresponding port selection signal PS.sub.1 is an "H" (high) level (the 
remaining signals PS.sub.0, PS.sub.2 through PS.sub.n are an "L" level). 
Therefore, the inverted port selection signal PS.sub.1 is the "L" level 
(the remaining inverted signals PS.sub.0, PS.sub.2 through PS.sub.n are of 
"H"). Under these conditions, the third transistor 23-1 of the selected 
channel 12'-1 is turned off by the signal PS.sub.1, and, thereby, the 
corresponding information input given at the port 14-1 is transferred to 
the node N by way of the first and second transistors 21-1 and 22-1, both 
conductive by the signal PS.sub.1. Under the same conditions as above, 
regarding the other channels 12'-0, 12'-2 through 12'-n, the respective 
conductors 13-0, 13-n through 13-2, sandwiched by the respective first and 
second transistors, are forcibly clamped at ground level. This is because, 
the third transistor of each of the nonselected channels is turned on. 
The second transistor (22) for each nonselected channel is needed to 
prevent the thus forcibly clamped ground level from travelling into the 
selected channel. The thus forcibly clamped ground level on the conductor 
lines of the nonselected channels is effective for impeding the transfer 
of noise to the node N therethrough, the noise induced by signals supplied 
to the nonselected ports 14-0 and 14-2 through 14-n. 
Due to the above-mentioned relationship between the port selection signal 
(PS) and the inverted port selection signal (PS), taking the channel 12'-1 
as an example, the conductor lines 13-0, 13-2, etc. of neighboring 
channels, such as 12'-0, 12'-2, are fixed at ground level. Further, the 
gate leads 24-0, 24-1, etc. of the neighboring channels are fixed at the 
"L" level. Still further, the gate lead 24-1 for channel 12'-1 now in the 
selection state is fixed at the "H" level. This means that the related 
channel 12'-1 has a stable or fixed voltage level. This also applies to 
other selected channels. Consequently, each information input can be 
transferred to the node N, maintaining the voltage level that is at its 
port without being affected by any external level variation. 
FIG. 4 is a partial top plane view of the circuit shown in FIG. 2, 
illustrating some sets of the second and third transistors (22, 23) and 
their neighboring members. The members referenced with the same numerals 
or characters as those of FIG. 2 are identical to those of FIG. 2. Symbols 
LPS.sub.0 through LPS.sub.2 and LPS.sub.0 through LPS.sub.2, are gate 
conductors for transferring the signals PS.sub.0 through PS.sub.2 and 
PS.sub.0 through PS.sub.2, respectively, shown in FIG. 2. Solid lines 
referenced by N.sup.+ indicate an enclosure of an N.sup.+ diffusion layer. 
Hatchings are employed not for representing cross-sectional regions as 
usual, but for clearly distinguishing polysilicon layers. As understood 
from FIG. 4, the addition of second and third transistors (22, 23) into 
the circuit of FIG. 1 does not impede achievement of a high degree of IC 
integration. That is, the conductors 12'-0, 24-0, 12'-1, and 24-1, etc., 
are arranged with very small pitches, regardless of the existence of the 
transistors (22, 23). 
As explained above in detail, according to the present invention, there is 
provided an input circuit, having a plurality of channels which are 
activated one after another, with the advantage that the information input 
to each selected channel can be transferred therethrough to the following 
predetermined internal circuit without being affected by other nonselected 
channels and, therefore, can be kept at the voltage level that is at its 
port.