SUBSTRATE FOR SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME

A substrate for a semiconductor package includes a semiconductor chip mounting region; a bonding terminal region including at least one bonding terminal; at least one plating line extending across the semiconductor chip mounting region; a plating line prohibition region at an opposite side of the bonding terminal region from the semiconductor chip mounting region; and a plating line removal region that is between the bonding terminal region and the semiconductor chip mounting region and is free of a portion of the plating line so that each of the at least one bonding terminal is electrically isolated.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to and the benefit of Korean Patent Application No. 10-2022-0171827 filed in the Korean Intellectual Property Office on Dec. 9, 2022, the entire content of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

(a) Field of the Invention

The present disclosure relates to a substrate for a semiconductor package and a semiconductor package including the same.

(b) Description of the Related Art

Packaging is an essential part of semiconductor manufacturing and design. Semiconductor devices continue to be developed with higher density integration and compactization. Even in packaging in which a semiconductor chip is mounted on a substrate, it may be desirable to shorten a wiring distance and increase a mounting density.

One of the semiconductor packaging methods includes mounting a semiconductor chip on a substrate, electrically connecting the semiconductor chip to the substrate by means of wire bonding, and molding the semiconductor chip with a resin such as an epoxy. The substrate includes terminals for connection with the semiconductor chip and terminals for connection with an external device. These terminals are typically plated with nickel or gold.

Electroplating is widely used to plate the terminals of the substrate. A plating line for electroplating is formed on the substrate for electrically connecting all terminals of the substrate. After the plating is completed, a portion of the plating line is removed so that all terminals are electrically isolated. Specifically, a plating line removal region including the portion of the plating line is set, and the portion of the plating line within the plating line removal region is removed by etching or the like to remove an electrical connection. However, a portion of a plating line outside the plating line removal region remains connected to the terminals, and the remnants (also referred to as a stub) of the plating line may adversely affect a signal characteristic of a semiconductor package.

Though the number of terminals increases with increasing density and compactization of a semiconductor, a size of the substrate is limited. Accordingly, the disposition of the plating line and setting of the plating line removal region is increasing in importance.

Conventionally, there have been various proposals for the disposition of the plating line and the setting of the plating line removal region, but the proposals are generally not suitable for application to newer semiconductor package shapes. The conventional proposals are suitable for a type of a package in which a relatively small semiconductor chip is mounted at a center of a relatively wide substrate, but may not be suitable for more modern semiconductor package shapes.

In particular, according to demand for compactization and high density integration, a package in which a relatively large semiconductor chip is mounted on a substrate of a limited size, a package in which two or more semiconductor chips are mounted on one substrate, a package in which two or more semiconductor chips are stacked and/or the like have been introduced. However, in these packages, there is a restriction on the disposition of the plating line and the setting of the plating line removal region. Currently, an optimal or desired design that may be applied to these packages has not been proposed.

SUMMARY

Embodiments of the present disclosure propose an optimal or desirable disposition of a plating line and an optimal or desirable setting of a plating line removal region applicable to a compact and highly integrated semiconductor package.

According to a first aspect of the present disclosure, a substrate for a semiconductor package is provided. The substrate for the semiconductor package includes: a semiconductor chip mounting region that is on one surface of the substrate and is configured for mounting a semiconductor chip thereon; a bonding terminal region that is next to the semiconductor chip mounting region with a distance therebetween, and includes at least one bonding terminal configured for connection to a bonding pad of the semiconductor chip by a wire; at least one plating line configured to supply electricity for electroplating, that is formed on the one surface of the substrate between the at least one bonding terminal and the semiconductor chip mounting region, and is connected to each of the at least one bonding terminal; a plating line prohibition region that is at an opposite side of the bonding terminal region from the semiconductor chip mounting region, and is configured to inhibit formation of the at least one plating line; and a plating line removal region that is between the bonding terminal region and the semiconductor chip mounting region, and is free of a portion of the at least one plating line so that each of the at least one bonding terminal is electrically isolated.

The semiconductor chip mounting region, the plating line removal region, the bonding terminal region, and the plating line prohibition region may be sequentially arranged in a length direction of the substrate, and the semiconductor chip mounting region, the plating line prohibition region, and the substrate have substantially a same width.

The plating line prohibition region may be configured as a second semiconductor chip mounting region for mounting a second semiconductor chip therein.

The substrate may further include a second bonding terminal region that is at an opposite side of the plating line prohibition region from the bonding terminal region, and includes at least one bonding terminal configured for connection to a bonding pad of the second semiconductor chip by a wire.

The substrate may further include at least one second plating line configured to supply electricity for electroplating, that extends from the at least one bonding terminal of the second bonding terminal region.

According to a second aspect of the present disclosure, a semiconductor package is provided. The semiconductor package includes: a substrate including a plurality of bonding terminals and a plating line on one surface of the substrate; a first semiconductor chip that is mounted on the one surface of the substrate and includes a plurality of bonding pads formed near at least one edge on a top surface of the first semiconductor chip; and a second semiconductor chip that is mounted on the one surface of the substrate at a distance from the first semiconductor chip, and includes a plurality of bonding pads formed near at least one edge on a top surface of the second semiconductor chip, wherein, the plurality of bonding terminals are between the first semiconductor chip and the second semiconductor chip and are connected to the plurality of bonding pads of the first semiconductor chip and the plurality of bonding pads of the second semiconductor chip by wires, the plating line is between the plurality of bonding terminals and the first semiconductor chip and is connected to each of the plurality of bonding terminals, and a plating line removal region is between the first semiconductor chip and the plurality of bonding terminals and is free of a portion of the plating line so that each of the plurality of bonding terminals is electrically isolated.

The first semiconductor chip, the plurality of bonding terminals, and the second semiconductor chip may be sequentially arranged in a length direction of the substrate, and the first semiconductor chip, the second semiconductor chip, and the substrate have substantially a same width. In some embodiments, each of the width of the first semiconductor chip and the width of the second semiconductor chip may be 80% or more of the width of the substrate. In other embodiments, each of the width of the first semiconductor chip and the width of the second semiconductor chip may be 90% or more of the width of the substrate, or a difference between the width of the first semiconductor chip (or the width of the second semiconductor chip) and the width of the substrate may be 150 μm or less.

A distance between the first semiconductor chip and the plurality of bonding terminals may be 500 μm to 600 μm.

The length of the removed plating line may be 100 μm to 200 μm.

After the portion of the plating line in the plating line removal region is removed, a length of the plating line that remains connected to each of the plurality of bonding terminals may be 200 μm or less.

The semiconductor package may further include a plurality of second bonding terminals that are at an opposite side of the second semiconductor chip from the plurality of bonding terminals and are connected to a plurality of bonding pads of the second semiconductor chip by wires.

The plating line may extend across a region of the top surface of the substrate in which the first semiconductor chip is mounted.

According to a third aspect of the present disclosure, a semiconductor package is provided.

The semiconductor package includes: a substrate that includes connection terminals on a bottom surface that are configured for connection with an external device, bonding terminals on a top surface, which are connected to a semiconductor chip by wires, and via holes and conductive lines configured to facilitate electrical connections to the connection terminals and the bonding terminals; and a first semiconductor chip and a second semiconductor chip that are arranged along a length direction of the substrate and have substantially a same width as a width of the substrate, wherein, a plurality of bonding pads are arranged along a width direction of the first semiconductor chip near one edge of a top surface thereof facing the second semiconductor chip, a plurality of bonding pads are arranged along a width direction of the second semiconductor chip near one edge of a top surface thereof facing the first semiconductor chip, a plurality of bonding terminals are arranged along a width direction of the substrate between the first semiconductor chip and the second semiconductor chip, the plurality of bonding terminals are connected to the plurality of bonding pads of the first semiconductor chip and the plurality of bonding pads of the second semiconductor chip by wires, all of the plurality of bonding terminals are connected to at least one plating line which is configured to supply electricity for electroplating, and is on the substrate between the plurality of bonding terminals and the first semiconductor chip, a plating line removal region, which is free of a portion of the at least one plating line, is between the first semiconductor chip and the plurality of bonding terminals to electrically separate the plurality of bonding terminals from each other, a distance between the second semiconductor chip and the plurality of bonding terminals is less than one-third of a distance between the first semiconductor chip and the plurality of bonding terminals, and the distance between the first semiconductor chip and the plurality of bonding terminals is 150 μm or more and the distance between the second semiconductor chip and the plurality of bonding terminals is 150 μm or less.

The distance between the first semiconductor chip and the plurality of bonding terminals may be 500 μm to 600 μm, and a length of the plating line removed by the plating line removal region may be 100 μm to 200 μm.

The length of the at least one plating line that is connected to the plurality of bonding terminals may be 200 μm or less.

In the second and third aspects of the present disclosure, the first semiconductor chip may be a memory chip, and the second semiconductor chip may be a buffer chip.

In the second and third aspects of the present disclosure, the first semiconductor chip may be a stack provided by stacking eight NAND flash memory chips, wherein the NAND flash memory chips are stacked in a stepwise manner so that the bonding pads of each of the NAND flash memory chips are arranged toward the plurality of bonding terminals. Herein, the stack, the at least one plating line, the plating line removal region, the plurality of bonding terminals, the buffer chip, and the plurality of second bonding terminals may constitute a first set, the semiconductor package may further include a second set that is adjacent to the first set and has a same configuration as the first set, and the first set and the second set may be symmetrical to each other.

The embodiments of the present disclosure may effectively achieve compactization and high integration while beneficially keeping a signal characteristic of a semiconductor package by disposition of a plating line and setting of a plating line removal region in which a length of the plating line remaining connected to bonding terminals is reduced or minimized in the semiconductor package in which a relatively large semiconductor chip is mounted on a substrate of a limited size.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, example embodiments will be described with reference to the accompanying drawings. Accordingly, the drawings and description are to be regarded as illustrative in nature and not restrictive. The same reference numerals are used for the same components in the drawings, and duplicate descriptions thereof are omitted. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. It is noted that aspects described with respect to one embodiment may be incorporated in different embodiments although not specifically described relative thereto. That is, all embodiments and/or features of any embodiments can be combined in any way and/or combination.

In addition, because size and thickness of each component shown in the drawings and a ratio between components are arbitrarily adjusted for better understanding and ease of description, embodiments of the present disclosure is not limited thereto.

Further, in the specification, the phrase “on a plane” or in a “plan view” means when an object portion is viewed from above, and the phrase “in a side view” means when an object portion is viewed from the side.

FIG.1is a schematic plan view and a schematic side view illustrating a state before a plating line removal region is provided in a substrate for a semiconductor package according to an embodiment of the present disclosure.

The substrate100may be a printed circuit board. Although not shown inFIG.1, terminals for connection with an external device may be provided at a bottom surface of the substrate100. These terminals may have a shape of a bump or a ball, but embodiments are not limited thereto.

A semiconductor chip mounting region110, a bonding terminal region120, and a plating line prohibition region130are sequentially provided on a top surface of the substrate100along a length direction of the substrate100. In the side view, the semiconductor chip mounting region110and the plating line prohibition region130are illustrated as having a certain height on the substrate, but this is only for convenience of explanation. The semiconductor chip mounting region110is a region on the substrate100to which a semiconductor chip is attached with an adhesive or the like. The plating line prohibition region130is a region on the substrate100in which formation of a plating line is prohibited.

Formation of the plating line is prohibited within the plating line prohibition region130. That is, no plating line exists within the plating line prohibition region130, and no plating line has been previously formed. Conventionally, a pattern of the plating line is formed for electroplating, and then a portion of the pattern is removed by etching or the like after electroplating. However, a surface of a region from which the plating line is removed is not the same as a surface before forming the plating line pattern. When a treatment, such as etching or the like is performed on a surface to remove the plating line, a physical and/or chemical property of the surface is changed. Accordingly, when a semiconductor chip is bonded to the surface, the adhesive force facilitating the bonding may be degraded. Such a change in a surface characteristic due to a process of forming the pattern of the plating line and then removing a portion of the pattern does not occur in the plating line prohibition region130. Therefore, the plating line prohibition region130does not cause a problem of low adhesion when another semiconductor chip or another part is bonded, and may be used as a space for forming another complex circuit pattern.

A plurality of bonding terminals122are provided within the bonding terminal region120. AlthoughFIG.1shows a limited number of bonding terminals122, in practice, a large number of bonding terminals122are disposed at a high density with fine intervals in the bonding terminal region120. The plating line140extends from one side of the bonding terminal region120toward the semiconductor chip mounting region110, since the plating line prohibition region130is disposed at an opposite side of the bonding terminal region120. The plating line is formed between the semiconductor chip mounting region110and the bonding terminal region120, and is connected to each of the bonding terminals122.

The bonding terminals122may protrude upward from the top surface of the substrate100or may be recessed inward from the top surface. The bonding terminals122are also referred to as lead fingers, connection pads, or the like, and may have various shapes. Although not shown inFIG.1, the bonding terminals122may be respectively connected to bumps below the substrate100through wires and via holes.

The substrate100has the semiconductor chip mounting region110on the top surface of the substrate on which the semiconductor chip is to be mounted. The semiconductor chip is attached to the semiconductor chip mounting region110using an adhesive or the like.

A width of the semiconductor chip mounting region110is substantially the same as that of the substrate100. An embodiment where the width of the semiconductor chip mounting region is substantially the same as that of the substrate includes not only an embodiment where the width of the semiconductor chip mounting region110is completely identical to that of the substrate100but also an embodiment where the width of the semiconductor chip mounting region110is smaller than that of the substrate100and a space between the semiconductor chip mounting region110and the substrate100is so small that it is difficult to form conductive lines or the like thereon. For example, a difference between the width of the semiconductor chip mounting region110and the width of the substrate100may be 150 μm or less. In an embodiment, the width of the semiconductor chip mounting region may be 80% or more of the width of the substrate, and, in some embodiments, the width of the semiconductor chip mounting region may be 90% or more of the width of the substrate.

A size of a semiconductor package may be limited by a requirement of a device on which the semiconductor package is mounted. An information device may be required to be thin and multi-functional, and thus, compactization and high density integration may be required for the semiconductor package. Therefore, a substrate for the semiconductor package may have a limited size, while a size of a semiconductor chip of a large capacity is relatively large. The present embodiment may enable a large-capacity semiconductor chip to be mounted on the substrate100by providing a maximum width of the semiconductor chip mounting region110.

The substrate100includes the plating line140for plating the bonding terminals122. The plating line140is connected to all the bonding terminals122to be plated, and extends from the bonding terminals122toward the semiconductor chip mounting region110. InFIG.1, the plating lines140extend from all the bonding terminals122and then are connected to each other. However, a pattern of the plating line140is not limited to a pattern shown inFIG.1. Because the plating line140is configured to perform electroplating by supplying electricity to all the bonding terminals122, any pattern that may achieve this purpose may be used.

To connect an external power supply device and the plating line140, an extension line of the plating line may be formed outside the substrate100after the plating lines are connected to each other. In other embodiments, the plating line140may be connected to a ground line provided on the substrate100, and power for electroplating may be supplied through the ground line.

Although the pattern of the plating line140for supplying external power for electroplating may be designed in various ways, it should be considered that a portion of the plating line may be removed so that the bonding terminals122are electrically isolated from each other after completion of electroplating. The portion of the plating line140may be removed by etching. A process of setting a region for removing the portion of the plating line and removing the plating line within the set region by the etching is called etching back. Thus, a plating line removal region may be free of a portion of one or more plating lines140to electrically isolate the bonding terminals122.

Setting the plating line removal region is an important design consideration. In an embodiment of the present disclosure, a state in which the plating line removal region is formed is shown inFIG.2.

Referring toFIG.2, the plating line removal region145is disposed between the semiconductor chip mounting region110and the bonding terminal region120. A portion of the plating line within the plating line removal region145is removed by a treatment, such as etching or the like. Thereby, the bonding terminals122are electrically isolated from each other.

To provide the plating line removal region145between the semiconductor chip mounting region110and the bonding terminal region120, a distance between the semiconductor chip mounting region110and the bonding terminal region120is set greater than a distance between the plating line prohibition region130and the bonding terminal region120. In an embodiment, the distance between the plating line prohibition region130and the bonding terminal region120is less than one-third of the distance between the semiconductor chip mounting region110and the bonding terminal region120.

A length of a plating line stub that remains connected to the bonding terminals122after the portion of the plating line is removed by the plating line removal region145is reduced or minimized by disposing the plating line removal region145between the semiconductor chip mounting region110and the bonding terminal region120. Because the plating line stub affects a signal characteristic, it is generally desirable to leave the plating line stub as short as possible.

In a comparative example described with reference toFIGS.8and9, the plating line removal region145is disposed at an opposite side of the semiconductor chip mounting region110from the bonding terminals122. In this embodiment, a plating line stub connected to the bonding terminals122remains across the semiconductor chip mounting region110. This may degradation of the signal characteristic as will be described below.FIG.3is a partially enlarged view of a circled portion inFIG.2. The plating line removal region145is disposed between the bonding terminals122and the semiconductor chip mounting region110. The plating line140is partially cut by the plating line removal region145.

In an embodiment, a distance (d1+d2+d3) between the semiconductor chip mounting region110and the plurality of bonding terminals is 500 μm to 600 μm. A width (d2) of the plating line removal region145according to the length direction of the substrate100is 100 μm to 200 μm.

In an embodiment, a length (d1) of the plating line stub remaining connected to the bonding terminals122after the plating line is partially removed is about 200 μm. In this embodiment, the width (d2) of the plating line removal region145according to the length direction of the substrate100is about 150 μm, and a distance (d3) between the plating line removal region145and the semiconductor chip mounting region110is about 200 μm. These dimensions may be suitable for stably providing the plating line removal region145by an etching process without affecting the bonding terminals122and the semiconductor chip mounting region110.

According to the present embodiment, by reducing or minimizing the length of the plating line stub while providing the largest region where the semiconductor chip is mounted, there is no or reduced deterioration in a signal characteristic due to formation and removal of the plating line, and the substrate for the semiconductor package may have a high-density layout and may also provide a region for mounting an additional semiconductor chip.

FIG.4is a schematic plan view and a schematic side view of a substrate for a semiconductor package according to another embodiment of the present disclosure. Like the substrate ofFIG.2, the substrate100includes the semiconductor chip mounting region110, the plating line removal region145, a bonding terminal region120a, and a plating line140a. Because the description of features with reference toFIGS.2and3may be applicable to these configurations, a repeated description thereof is omitted.

A bonding terminal region120bincluding bonding terminals124and a plating line140bconnected to the bonding terminals124are provided at an opposite side of the plating line prohibition region130from the bonding terminal region120a. In addition, the plating line prohibition region130is a second semiconductor chip mounting region on which a second semiconductor chip is mounted.

The bonding terminals124within the bonding terminal region120bare connected to bonding pads of the semiconductor chip mounted on the second semiconductor chip mounting region130by wires. Because the plating line140bis disposed at an edge of the substrate100, a degree of freedom in designing a pattern of the plating line is high. Although a limited number of bonding terminals are shown inFIG.4for simplicity of explanation, many conductive lines may be provided on the substrate in addition to the bonding terminals, and thus a pattern connecting the bonding terminals to the plating line may be adaptively designed.

According to the present embodiment, a substrate capable of mounting two semiconductor chips with high space efficiency while reducing or minimizing an influence of the plating line on a signal characteristic is provided.

FIG.5is a perspective view illustrating a semiconductor package according to an embodiment of the present disclosure. The semiconductor package1000includes a substrate1200and a first semiconductor chip1100and a second semiconductor chip1500mounted on the substrate1200. A basic structure of the substrate1200is substantially the same as that of the substrate100shown inFIG.4. Although not shown inFIG.5, the semiconductor package1000may include a molding layer on and at least partially covering the first semiconductor chip1100and the second semiconductor chip1500to protect the semiconductor chips from impact, humidity, temperature, and the like. For example, the molding layer may include an insulating resin or an epoxy molding compound (EMC).

The first semiconductor chip1100and the second semiconductor chip1500are mounted along a length direction of the substrate1200. A width of the first semiconductor chip1100is equal to or slightly smaller than that of the substrate1200. In an embodiment, a difference between a width of the first semiconductor chip1100and a width of the substrate1200is 150 μm or less. A width of the second semiconductor chip1500is substantially the same as that of the substrate1200. In an embodiment, each of the width of the first semiconductor chip1100and the width of the second semiconductor chip1500may be 80% or more of the width of the substrate1200, and in some embodiments, may be 90% or more.

In an embodiment, at least one of the first semiconductor chip1100and the second semiconductor chip1500may have a sufficiently smaller width than that of the substrate1200. In this case, there may be a space on the substrate at one side or both sides of the first semiconductor chip1100and/or the second semiconductor chip1500in a width direction. This space may be filled with another circuit pattern or another component for high integration.

In the present embodiment, a plurality of bonding pads1110are provided on a top surface of the first semiconductor chip1100. The bonding pads1110are connected to first bonding terminals1220on the substrate1200by wires1120. A length of the wire1120may be relatively short to suppress a signal delay. To meet such requirement, the bonding pads1110are arranged near one edge proximal to the first bonding terminals1220on a top surface of the first semiconductor chip1100.

The first bonding terminals1220are arranged in a width direction between the first semiconductor chip1100and the second semiconductor chip1500. Because a plating line removal region1450is provided between the first semiconductor chip1100and the first bonding terminals1220, a distance between the first semiconductor chip1100and the first bonding terminals1220is about three times greater than a distance between the second semiconductor chip1500and the first bonding terminals1220. In this embodiment, the distance between the first semiconductor chip1100and the first bonding terminals1220is 150 μm or more, and the distance between the second semiconductor chip1500and the first bonding terminals1220is 150 μm or less.

Although it is generally desirable that the distance between the second semiconductor chip1500and the first bonding terminals1220be as short as possible, the distance between the first semiconductor chip1100and the first bonding terminals1220may be a certain distance long enough to stably provide the plating line removal region1450. In an embodiment, the certain distance is 500 μm to 600 μm.

A plating line1400is provided between the first bonding terminals1220and the first semiconductor chip1100, and is connected to each of the first bonding terminals1220. A portion of the plating line is removed after electroplating, and the remaining portion of the plating line remains unremoved. After a portion of the plating line is removed, the remaining portion of the plating line is still connected to the first bonding terminals1220, and is called a plating line stub

The shorter a length of the plating line stub is, the less an influence is of a signal characteristic. In an embodiment, the length of the plating line stub is 200 μm or less. Because a physical/chemical characteristic of a surface changes when the plating line within the plating line removal region is removed by an etching process, if the plating line removal region is provided below the first semiconductor chip1100, adhesion of the first semiconductor chip1100may be adversely affected. If the plating line removal region1450is provided between the first semiconductor chip1100and the bonding terminals1220as in the embodiment of the present disclosure, the above problem may not occur.

In addition, when the plating line removal region is provided at an opposite side of the first semiconductor chip from the bonding terminals as shown inFIG.9, the plating line may extend below the first semiconductor chip. In this case, the plating line stub may become relatively long, and signal characteristics may be adversely affected. If the plating line removal region is provided between the first semiconductor chip and the bonding terminals as in an embodiment of the present disclosure, the above problem may not occur because the length of the plating line stub remains relatively short.

A plurality of bonding pads are arranged on a top surface of the second semiconductor chip1500near one edge proximal to the first semiconductor chip1100, and the plurality of bonding pads are connected to the first bonding terminals1220by wires.

In an embodiment, second bonding terminals1240may be disposed at an opposite side of the second semiconductor chip1500from the first bonding terminals1220. The second bonding terminals1240are connected to bonding pads provided on the top surface of the second semiconductor chip1500by wires. A separate plating line for plating the second bonding terminals1240may be formed. A pattern of the plating line and a plating line removal region for the second bonding terminals1240may be appropriately set in various ways.

In an embodiment, the first semiconductor chip may be a memory chip and the second semiconductor chip may be a buffer chip. In another embodiment, the first semiconductor chip may be a memory chip and the second semiconductor chip may be a controller chip. Alternatively, the second semiconductor chip may be a memory chip and the first semiconductor chip may be a buffer chip or a controller chip. In an embodiment, the memory chip may be a NAND flash memory chip. When the first semiconductor chip is the memory chip, a width of the memory chip may have a maximum value allowed by the substrate so that the memory chip may have a maximum capacity while being mounted on the substrate having a limited size.

FIG.6is a schematic perspective view of a semiconductor package according to another embodiment of the present disclosure. The semiconductor package1000′ of the present embodiment includes a semiconductor chip stack1100′ in which a plurality of first semiconductor chips are stacked in a chip-on-chip type. InFIG.6, the semiconductor chip stack1100′ includes eight semiconductor chips, but this is merely an example, and for example, the semiconductor chip stack1100′ may include four or sixteen semiconductor chips. The second semiconductor chip1500is mounted on the substrate1200, and the first and second bonding terminals1220and1240are respectively provided on both sides of the second semiconductor chip1500.

The plating line removal region1450is provided between the semiconductor chip stack1100′ and the first bonding terminals1220. Because the embodiment ofFIG.5can be referred to for description of the remaining components except for the semiconductor chip stack, a detailed description of the remaining components is omitted herein.

Because a plurality of semiconductor chips are stacked in a stepwise manner in the semiconductor chip stack1100′, bonding pads are provided on a top surface of each semiconductor chip near one edge thereof. In the present embodiment, the bonding pads of each semiconductor chip are arranged near one edge proximal to the first bonding terminals1220.

In an embodiment, the semiconductor chip stack1100′ is a stack of memory chips and the second semiconductor chip1500is a buffer chip. Alternatively, the second semiconductor chip1500may be a controller chip. The memory chip may be a NAND flash memory chip. To maximize storage capacity, a chip stack may be provided by stacking NAND flash memory chips in a chip-on-chip form. As shown inFIG.6, the semiconductor chip stack1100′ may include eight NAND flash memory chips.

To maximize storage capacity, the number of cells in the memory chip may increase. This means that a size of the memory chip increases. However, there is a limitation that the size of the memory chip may not be greater than a size of a substrate for a package of the memory chip. This limitation may be overcome by vertically stacking memory chips. The present embodiment may improve or optimize disposition of the plating line and setting of the plating line removal region so that it is configured to mount the memory chip having a width as large as a width of the substrate. Furthermore, the present embodiment may increase or maximize storage capacity by stacking a plurality of memory chips.

FIG.7is a schematic side view of a semiconductor package according to another embodiment of the present disclosure. The semiconductor package1000″ of the present embodiment includes a pair of semiconductor chip stacks1100′. The pair of the semiconductor chip stacks1100′ are disposed in mirror symmetry with each other. The first bonding terminals1220connected to each semiconductor chip stack1100′, the second semiconductor chip1500, the second bonding terminals1240, the plating line1400, and the plating line removal region1450are also disposed on the substrate in mirror symmetry with each other.

The configuration and arrangement of the first bonding terminals, the second semiconductor chip, the second bonding terminals, the plating line, and the plating line removal region disposed on both sides of the substrate, have been described with respect to the previous embodiments, a repeated description thereof is omitted.

In an embodiment, each of the pair of semiconductor chip stacks1100′ may be a stack in which eight NAND flash memory chips are stacked. Thus, sixteen NAND flash memory chips may be included in one semiconductor package. The pair of flash memory chip stacks may operate with two channels. The second semiconductor chip may be a buffer chip or a controller chip.

FIGS.8to10show the comparative example and a comparative experimental result for describing signal characteristics of embodiments of the present disclosure.

Referring toFIG.8, the semiconductor chip mounting region110, the bonding terminal region120, and the plating line prohibition region130are sequentially disposed on a substrate for a semiconductor package along a length direction of the substrate, and this configuration is the same as that of the embodiment ofFIG.1.

On the other hand, in the comparative example, the plating line140extends across the semiconductor chip mounting region110. As shown inFIG.9, in the comparative example, the plating line removal region145is provided at an opposite side of the semiconductor chip mounting region110. That is, the plating line removal region145is disposed at an opposite side of the semiconductor chip mounting region110from the bonding terminal region120.

In an example where the plating line removal region145overlaps the semiconductor chip mounting region110, as described above, a problem in which an adhesive force of the semiconductor chip is weakened may occur. In the comparative example, the plating line removal region145is disposed outside the semiconductor chip mounting region110, and the bonding terminals122are electrically separated by removing a portion of the plating line140within the plating line removal region145.

A position of the plating line removal region145of the comparative example ofFIG.9is different from that of the plating line removal region145of the embodiment ofFIG.2when the comparative example ofFIG.9is compared with the embodiment ofFIG.2. For this reason, a distance between the semiconductor chip mounting region110and the bonding terminal region120of the comparative example ofFIG.9may be shorter than that of the embodiment ofFIG.2. However, as can be seen from an experimental result ofFIG.10, an advantage obtained by shortening the distance between the semiconductor chip mounting region110and the bonding terminal region120is significantly lower than an advantage obtained by providing the plating line removal region140between the semiconductor chip mounting region110and the bonding terminal region120.

FIG.10shows measurement results of an input-output signal characteristic of the semiconductor package including the substrate for the semiconductor package shown inFIG.2and an input-output signal characteristic of the semiconductor package including the substrate for the semiconductor package shown inFIG.9.

In this comparison experiment, a NAND flash memory chip is mounted at the semiconductor chip mounting region, and a buffer chip is mounted at the plating line prohibition region130. Two semiconductor packages used in the experiment had the same configuration except for a position of the plating line removal region145. InFIG.10, (a) is the measurement result of the input-output signal characteristic of the semiconductor package manufactured according to an arrangement structure shown inFIG.9, and (b) is the measurement result of the input-output signal characteristic of the semiconductor package manufactured according to an arrangement structure shown inFIG.2.

From the measurement results, it is easy to see that the input-output signal characteristics ofFIG.10(b)are superior to those ofFIG.10(a). In the semiconductor package according to the comparative example, a length of the plating line stub remaining connected to each bonding terminal122is relatively long. A long plating line stub unnecessarily acts as an antenna or causes a problem in which a signal is reflected so that it deteriorates an overall signal characteristic of the semiconductor package.

FIG.11schematically shows a substrate for a semiconductor package according to another embodiment of the present disclosure. In the substrate100for the semiconductor package according to the present embodiment, after the plating line140is formed in the same manner as in the substrate for the semiconductor package ofFIG.8, the plating line removal region145is provided between the semiconductor chip mounting region110and the bonding terminal region120.FIG.12shows a semiconductor package1000including the substrate for the semiconductor package ofFIG.11. The first semiconductor chip1100is mounted at the semiconductor chip mounting region110, and the second semiconductor chip1500is mounted at the plating line prohibition region130.

In the embodiments according toFIGS.11and12, the plating line140extends below the first semiconductor chip, but a length of the plating line stub is relatively short because the plating line removal region1450is provided between the first semiconductor chip1100and the bonding terminals1220. Because the length of the plating line stub is relatively short, a problem in which a signal characteristic is degraded due to a long plating line stub may not occur.

In a semiconductor package in which a relatively large semiconductor chip is mounted on a substrate having a limited size for compactization and high integration, the embodiments of the present disclosure may provide a substrate for the semiconductor package having a plating line that does not degrade or deteriorate a signal characteristic, does not weaken an adhesive force of the semiconductor chip, and has an arrangement of the plating line removal region. A semiconductor package including the substrate may be further provided.

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