A method, apparatus, and system in which an embedded memory comprises one or more electrically-alterable non-volatile memory cells that include a coupling capacitor, a read transistor, and a tunneling capacitor. The coupling capacitor has a first gate composed of both N+ doped material and P+ doped material, and a P+ doped region abutted to a N+ doped region. The P+ doped region abutted to the N+ doped region surrounds the first gate. The read transistor has a second gate. The tunneling capacitor has a third gate composed of both N+ doped material and P+ doped material.

FIELD OF THE INVENTION

This invention generally relates to embedded memories. More particularly an aspect of this invention relates to an embedded memory having one or more electrically-alterable non-volatile memory cells.

BACKGROUND OF THE INVENTION

A non-volatile memory retains the contents of the information stored in a memory cell even when the power is turned off. Many System-on-Chip (SoC) design teams find themselves confronting a seeming conundrum: How to design non-volatile memory (NVM) into a SoC project. To achieve a single chip solution, the design team typically has little option but to select a special process technology that trails the most current standard logic process by two or three technology generations. This choice generally requires additional processing steps that increase wafer costs. Alternatively, the team could implement a less efficient, more costly, slower, and larger two-chip solution by separating the SoC and the NVM into discrete components.

FIG. 1illustrates a prior technique of creating a non-volatile memory cell. The previous technique created a two polysilicon layers for the nonvolatile memory cell. The second polysilicon layer was the word line, and the word line receives a bias voltage. The bias voltage is coupled from the word line to the first polysilicon layer, referred to as a floating gate, by a coupling capacitor. The floating gate is separated from the PWell of the polysilicon by an insulating material. The floating gate in connection with the PWell creates the cell channel or read transistor. The read transistor typically communicates the logical information stored by that particular memory cell during normal operations.

Typically, the read transistor for that memory cell functions as both the sensing component to communicate the information stored during normal operations, and a charging component to allow either erasing or programming information stored in that memory cell. The second polysilicon layer, the word line, typically is used to couple voltage into the floating poly gate either for write or read operations. Next, electrons charge through the coupling capacitor into the floating gate to store the information.

To create a prior non-volatile memory cell, typically a standard CMOS-based logic process is used as a starting foundation. Next, additional process steps are incorporated into the logic process flow to create the non-volatile memory cells. Examples of such additional process steps include second polysilicon deposition junction dopant optimization, etc. Integrating “non-volatile memory”-specific process steps into the standard CMOS-based logic process creates complications which require extensive qualifications. Consequently, embedded non-volatile memory technologies generally lag advanced logic fabrication processes by several generations. For a system-on-chip (SoC) approach, which requires embedding a non-volatile memory, a design team may have no choice but to accept a logic flow process usually two to three generations behind the current advanced standard logic process as well as the addition to that process of seven to eight additional lithographic masks. This prior approach not only typically increases the wafer cost, but also falls short of the peak performance that the most advanced standard logic process can deliver.

Also, the performance and reliability of a SiO2-based non-volatile memory cell typically degrades under extended program and erases operations due to the cycling-induced degradation of the SiO2. The previous technique of subjecting all of the non-volatile memory cell components to the higher program and erase voltages typically hastens the degradation of the SiO2.

SUMMARY OF THE INVENTION

A method, apparatus, and system in which an embedded memory comprises one or more electrically-alterable non-volatile memory cells that include a coupling capacitor, a read transistor, and a tunneling capacitor. The coupling capacitor has a first gate composed of both N+ doped material and P+ doped material, and a P+ doped region abutted to a N+ doped region. The P+ doped region abutted to the N+ doped region surrounds the first gate. The read transistor has a second gate. The tunneling capacitor has a third gate composed of both N+ doped material and P+ doped material.

DETAILED DISCUSSION

In the following description, numerous specific details are set forth, such as examples of specific data signals, named components, connections, arrangement of components, etc., in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well known components or methods have not been described in detail but rather in a block diagram in order to avoid unnecessarily obscuring the present invention. Further specific numeric references, such as first gate, may be made. However, the specific numeric reference should not be interpreted as a literal sequential order but rather interpreted that the first gate is different than a second gate. Thus, the specific details set forth are merely exemplary. The specific details may be varied from and still be contemplated to be within the spirit and scope of the present invention. The term coupled is defined as meaning connected either directly or indirectly through another component.

In general, various methods, apparatuses, and systems are described in which an embedded memory comprises one or more electrically-alterable non-volatile memory cells that include a coupling capacitor, a read transistor, and a tunneling capacitor. The coupling capacitor has a first gate composed of both N+ doped material and P+ doped material, and a P+ doped region abutted to a N+ doped region. The P+ doped region abutted to the N+ doped region surrounds the first gate. The read transistor has a second gate. The tunneling capacitor has a third gate composed of both N+ doped material and P+ doped material. In an embodiment, all of the aforementioned gates may be connected together to form a single floating gate.

FIG. 2illustrates a cross-sectional view of an embodiment of an electrically-alterable non-volatile memory cell. The electrically-alterable non-volatile memory cell200consists of a coupling capacitor202, a read transistor204, and a tunneling capacitor206. The coupling capacitor202comprises a first gate208composed of both N+ doped material259and P+ doped material258. The N+ doped and P+ doped gate208is surrounded by a first P+ doped region210abutted to a first N+ doped region218. In between the first gate208and the first P+ doped region210abutted to the first N+ doped region218are a first spacer230and a second spacer232. An insulating material228exists between the first gate208and the N+ doped NWell region234. The P+ doped region210connects to the first side of the insulating material228and the N+ doped region218connects to the second side of the insulating material228. On either side of the coupling capacitor202exists shallow trench isolations236,238. Mounted on the first N+ doped region218is one or more N+ contacts245. Mounted on the first P+ doped region210is one or more P+ contacts246. The N+ contacts245and P+ contacts246may be electrically connected, for example, by a wire to be logically and electrically the same point, a common T terminal, but physically still separated components.

The tunneling capacitor206includes a second gate226composed of both N+ doped material259and P+ doped material258. A second N+ doped region224and a second P+ doped region222abut together and surround the second gate226. In between the regions224,222and the second gate226exists a third spacer246and a fourth spacer248. Further, insulating material228exists between the second gate226and the N+ doped NWell region234. The second P+ doped region222connects to the first side of the insulating material228and the second N+ doped region224connects to the second side of the insulating material228. Also, shallow trench isolations240,242exist on either side of the tunneling capacitor206. Mounted on the second N+ doped region224is one or more N+ contacts250. Mounted on the second P+ doped region222is one or more P+ contacts251. The N+ contacts250and P+ contacts251may be electrically connected, for example, by a wire to be logically and electrically the same point, a common B terminal, but physically still separated components.

The read transistor204consists of a third gate220separated from a third N+ region252and a fourth N+ region254abut together. The third gate220isolates from the N+ regions252,254through use a fifth spacer256and sixth spacer260. Insulating material228exists between the third gate220and a P-substrate244. The first gate208of the coupling capacitor202and the second gate226of the tunneling capacitor206are predominately doped N+. However, each of these gates has one or more partitioned areas258where in those areas they are doped P+. In an embodiment, a floating gate260encompasses the first gate208, the second gate226, and the third gate220. The floating gate260is fabricated from a single layer of polysilicon using a complementary metal oxide semiconductor logic process employing equal to or less than 0.35 micron technology.

The drain terminal262of the read transistor204connects to the third N+ region252. The source terminal264connects to the fourth N+ region254. Shallow trench isolations238,242exist on either side of the read transistor204. Note, in an embodiment, LOCOS (local oxidation of silicon) may be used instead of shallow trench isolations.

In an embodiment, the electrically-alterable non-volatile memory cell200consists of three discrete components to allow the sensing component, such as the read transistor204, to be discrete from the charging component, such as the tunneling capacitor206and coupling capacitor202combination. Having the sensing component discrete from the charging component enhances the reliability of those components and increases their lifetime. A much higher voltage is required to perform erasing and programming operations through the charging components than the voltage required for a read operation through the sensing component. By allowing the sensing component to be discrete from charging component allows the sensing component to not be subject to the erasing and programming voltages which are higher than the sensing voltage, thereby reducing stress on the sensing component and increasing its reliability.

In an embodiment, the charge mode component operates as a capacitive divider to facilitate programming and erasing of information stored in the electrically-alterable non-volatile memory cell by symmetrical movement of charge. Thus, through the symmetrical movement of charge the programming and erasing voltages may be approximately the same value.

FIG. 2illustrates the dopings of an exemplary negative channel-MOS, electrically-alterable, non-volatile memory cell. In embodiment, arsenic is impregnated into either metal or polysilicon to create an N+ doping. In embodiment, boron is impregnated into either a metal or polysilicon to create a P+ doping. In an embodiment, if the substrate material is changed from P-substrate to N-substrate, then the NWells should change to PWells and all other polarities will be the compliments of what is illustrated inFIG. 2. In an embodiment, the thickness of the insulating material328is approximately seventy angstrom units and composed of SiO2.

In an embodiment, the P+ regions and N+ regions of the tunneling capacitor206and the coupling capacitor202are used as a source supply of negative electrons, i.e. negative charge and holes, i.e. positive charge. The second P+ region222of the tunneling capacitor206and the first P+ region210of the coupling capacitor202are used as a source of positive holes during erasing and programming operations. The second N+ region224of the tunneling capacitor206and the first N+ region218of the coupling capacitor202are used as a source of negative electrons during erasing and programming operations. In an embodiment, a lower programming and erasing voltage is achievable because both N+ regions and P+ regions exist in the capacitors. In an embodiment, the lower programming and erase voltages may be, for example, 7.0 volts or lower. In an embodiment, the tunneling capacitor206employs a tunneling mechanism such as a Fowler-Nordhiem tunneling process, for programming and erasing. In an embodiment, the electrically-alterable non-volatile memory cell200can be reprogrammed multiple times such as five hundred times, a thousand times, or more.

FIG. 3aillustrates a top-down view of an embodiment of the floating gate fabricated by a single layer of polysilicon and the P+ and N+ regions surrounding the coupling capacitor gate and the tunneling capacitor gate. In an embodiment, the coupling capacitor gate308is comprised of one or more P+ partitioned areas358a,358band a predominant N+ doped area331. The coupling capacitor gate308is deposited onto an insulating material (not shown) that separates the coupling capacitor gate308from the N+ doped NWell region334.

The first P+ doped region310abutted to the first N+ doped region318surrounds the coupling capacitor gate308. In an embodiment, the coupling capacitor gate308acts as the coupling capacitor's first plate and the second plate of the capacitor is the first P+ doped region310abutted to the first N+ doped region318. Also, the first P+ doped region310abutted to the first N+ doped region318connects to the insulating material. Mounted on the first N+ doped region218is one or more N+ contacts345. Mounted on the first P+ doped region210is one or more P+ contacts346. As noted, in an embodiment, the N+ contacts345and P+ contacts346may be electrically connected to form a common T terminal.

The N+ doped gate of the read transistor320deposits onto the insulating material (not shown) separating the N+ gate of the read transistor320and the P-substrate of the read transistor (not shown). Mounted on top of the third N+ region352is the Source terminal364. Mounted on top of the fourth N+ region354is the Drain terminal362. Note,FIG. 3aillustrates an exemplary embodiment of a NMOS read transistor implementation of the memory cell.

The tunneling capacitor is similarly arranged as the coupling capacitor. The tunneling capacitor gate326is predominantly N+ doped material331with one or more P+ doped partitioned areas358b. The second P+ region322abuts to the second N+ region324. The second P+ region322abutted to the N+ region324surrounds the tunneling capacitor gate326. In an embodiment, the tunneling capacitor gate326acts as the tunneling capacitor's first plate and the second plate of the capacitor is the second P+region322abutted to the second N+ doped region324. Mounted on the second N+ doped region324is one or more N+ contacts350. Mounted on the second P+ doped region322is one or more P+ contacts351. As noted, in an embodiment, the N+ contacts350and P+ contacts351may be electrically connected to form a common B terminal. In an embodiment, at least 70% of the floating gate360material is N+ doped331and the remainder of the floating gate360is one or more partitioned areas that are doped P+358a,358b.

In an embodiment, the floating polysilicon gate360encompasses the tunneling capacitor gate326, the read transistor gate320, and the coupling capacitor gate308. In an embodiment, the floating polysilicon gate360is folded over into a horizontal plane to assist the embedded memory to be manufactured in a standard logic process with a single layer of polysilicon.

In both the tunneling capacitor and the coupling capacitor, the P+ doped region322,310abutted to the N+ doped region318,324act as charge sources to allow more efficient bi-directional charging of the floating gate360. Therefore, a lower programming and erase voltage can be used when charging the floating gate360to store information such as logical 1 or logical 0. In an embodiment, the charge mode component consists of the tunneling capacitor and the coupling capacitor. In an embodiment, the charge mode component is used to both program and erase information stored in the memory cell.

As noted,FIG. 3aillustrates an NMOS embodiment of the memory cell, in an PMOS embodiment, at least 70% of the floating gate may be P+ doped and one or more of the remaining area of the floating gate are doped N+. In an embodiment, the floating gate may be a different geometric shape such as a rectangle with areas appropriately doped P+ for the tunneling capacitor and the coupling capacitor. In an embodiment, at least 90% of the floating gate is N+ doped.

FIG. 3billustrates a top-down view of an embodiment of a Positive-channel-MOS non-volatile memory cell using a floating gate fabricated from a single layer of polysilicon similar to the NMOS implementation shown inFIG. 3a.FIG. 3billustrates an exemplary embodiment of a PMOS read transistor implementation of the memory cell300. The memory cell structure300is similar to the NMOS read transistor implementation shown inFIG. 2except as noted.

The N+ doped gate of the read transistor320bdeposits onto the insulating material separating the N+ gate of the read transistor320and a third Nwell region334. Mounted on top of the third P+ region352bis the Source terminal364b. Mounted on top of the fourth P+ region354bis the Drain terminal362b.

FIGS. 4A,4B and4C illustrate a schematic diagram of an embodiment of the electrically-alterable non-volatile memory cell. Referring toFIGS. 4A,4b, and4c, the electrically-alterable non-volatile memory cell400consists of the tunneling capacitor406(CT), the coupling capacitor402(CC) and the read transistor404(RT). These three components share a single floating gate460. The coupling capacitor402, in conjunction with the tunneling capacitor406, forms the charging component. The charging component is operable to facilitate programming and erasing of information stored in the electrically-alterable non-volatile memory cell400. The sense component communicates information stored in the electrically-alterable non-volatile memory cell400during a read operation. Thus, the charge operation enables retention of information after the power is turned off while the sense operation allows the previously stored information to be accessed after powering the memory back up. In an embodiment, the sense component is the read transistor404. Note, theFIGS. 4A,4B and4C illustrate an exemplary PMOS structure. Note,FIGS. 8a–8cdescribe a similar schematic for a PMOS read transistor implementation.

Referring toFIG. 4A, the electrically-alterable non-volatile memory cell400is set up for a programming operation. The programming voltage is applied to terminal T446, which modulates the floating gate460. Electrically reprogramming the electrically-alterable non-volatile memory cell400requires higher than nominal voltage to charge up the floating gate460. In general, the non-volatile memory cell is considered programmed when the net charge introduced into the floating gate460is predominantly negative. This results in a net increase in the threshold voltage of the Read transistor404. Conversely, the electrically-alterable non-volatile memory cell400is considered erased when the negative charges that were introduced during program are successfully removed from the floating gate460. In an embodiment, the electrically-alterable non-volatile memory cell program and erase operations are achieved by means of quantum mechanically tunneling of electrons into and out of floating gate460through the tunneling capacitor406to alter the charge state of the memory cell.

In an embodiment, the tunneling mechanism is known as Fowler Nordheim (FN) tunneling and can be expressed as

where JFN is the tunneled current density, EOX=(VP−VFB−VS)/tox is the effective oxide electric field, and the two physical parameters A & B. Vp is the applied high voltage, VFB is the flat-band voltage, VS is the silicon surface band bending at the SiO2/Si interface and tox is the thickness of the tunnel gate oxide.

Therefore, to program the electrically-alterable non-volatile memory cell400, a positive voltage VPRG is applied to terminal T446while the terminal B450is grounded as shown inFIG. 4(a). Due to the capacitive coupling of the coupling capacitor402and tunneling capacitor406, large electric field strength will result to drop across the tunneling capacitor406. When the oxide electric field is sufficiently high for FN tunneling to occur, electrons from the Nwell region through the N+ region can tunnel through the insulating material and readily inject into the floating gate. In an embodiment, the area of the coupling capacitor402and tunneling capacitor406s are appropriately scaled to provide maximum capacitive coupling.

In an embodiment, the charge coupled to the floating gate equals:
Vcouple=CC/(CC+CT)*Vp

where Vcouple is the charge coupled to the floating gate. CC is the capacitance value of the coupling capacitor. CT is the capacitance value of the tunneling capacitor. Vp is the voltage applied to the terminal T.

Referring toFIG. 4b, the electrically-alterable non-volatile memory cell400is set up for an erase operation. The applied voltages on terminal B450and terminal T446are reverse from the programming mode to extract these excess electrons out of the electrically-alterable non-volatile memory cell400. A positive +VERASE is applied to terminal B450and 0V is applied to terminal T446. The electrons in the floating gate460now tunnel out of the floating gate which reduces the negative charge from the floating gate. In an embodiment, when the negative charge is removed from the floating gate460then the electrically-alterable non-volatile memory cell400stores a logical 0. In an embodiment, a low voltage, VR, is applied to the drain terminal462and source terminal464of the Read transistor404during either program or erase to minimize FN tunneling occurring at the Read transistor404. In an embodiment, the erase/programming voltage may be 6.5 volts or less.

Referring toFIG. 4cthe electrically-alterable non-volatile memory cell400is set up for a read operation. A sense voltage is applied to the drain terminal462and the source terminal464is grounded. The read transistor404communicates the information stored by that memory cell based upon the charge stored in the floating gate460. The charge stored in the floating gate460modulates conductivity of the read transistor404. For example, when the net charge introduced into the floating gate is predominantly negative the conductivity of the read transistor404is decreased indicating that this memory cell stores a logical 1. Note, during a read operation the T terminal446and B terminal450are maintained at the same voltage potential. This assists to minimizing read disturbs. A read disturb happens when the content of a memory cell that is being read is unintentionally altered from a logical 1 to a logical 0, or vice versa.

FIG. 5illustrates an exemplary embodiment of a portion of the electrically-alterable non-volatile memory cell fabricated using a single layer of polysilicon from a CMOS logic process employing, for example, a 1.0 or less micron technology. The portion of the electrically-alterable non-volatile memory cell500illustrated consists of the single polysilicon layer forming the floating gate560, one or more partitioned P+ doped areas538in the predominantly N+ doped floating gate560, a coupling capacitor502, an insulation layer528, a read transistor504on the P-substrate, and shallow trench isolations536,538,542separating the components.

In prior techniques, the non-volatile memory cell was formed either by a dual poly-layered process, or a single poly-layered process that required additional steps over the standard CMOS logic process. Typically, in the prior techniques, thirty-five or so lithographic mask steps were required. Extra process steps included: a second poly process module, memory cell special implant process module, special dielectric formation, etc.

However, in an embodiment, the floating polysilicon gate560is folded over into a horizontal plane to assist the embedded memory to be manufactured in a standard logic process with a single layer of polysilicon. Further, the insulating layer528for isolating the gates through the tunnel oxide layer is thinner and provides less insulation as compared to the previous technique of dual polysilicon gates vertically stacked over each other illustrated inFIG. 1.

As noted above, the floating gate560may be used to store the charge and the bias voltage may be applied to the coupling capacitor502. In an embodiment, the floating gate560may be made from either polysilicon or metal.

FIG. 6illustrates an exemplary process of generating an embedded memory from the memory component designs with a memory compiler.

In block605, the designs for each memory component for the embedded memory are supplied to the memory compiler. A memory compiler may be a software program comprised of multiple algorithms and designs for the purpose of generating a circuit design and a layout in a space available on a target chip. The set of application-specific algorithms and interfaces of the memory compiler may used by system IC integrators to rapidly create hundreds of silicon-proven memory cores. The memory compiler receives the memory component designs and utilizes those memory component designs in conjunction with memory circuit designs to optimize a circuit design and layout in the space available on a target chip. The electrically-alterable non-volatile memory cell may be a basic memory building block utilized in a design from a non-volatile random access memory compiler.

In block610, the memory compiler generates a circuit design and layout in the space available on a target chip. The memory compiler stores the data representing the embedded memory typically on a machine-readable medium. The memory compiler then provides design to be used to generate one or more lithographic masks to be used in the fabrication of that embedded memory.

In block615, the machine to generate the lithographic masks receives the circuit design and layout from the memory compiler. The machine generates one or more lithographic masks to be used to transfer that circuit design onto the chip.

In block620, a fabrication facility fabricates the chips with the embedded memories using the lithographic masks generated from the memory compiler's circuit design and layout. Fabrication facilities may use standard CMOS logic process employing 0.50 μm, 0.35 μm, 0.25 um, 0.18 μm, 0.13 rum, 0.10 μm, or less, technologies to fabricate the chips. The size of the CMOS logic process employed typically defines the smallest minimum lithographic dimension that can be fabricated on the chip using the lithographic masks, which in turn determines minimum component size. In an embodiment, light is shown through these lithographic masks onto the chip to transfer the circuit design and layout for the embedded memory onto the chip itself. In an embodiment, the embedded memory containing one or more electrically-alterable non-volatile memory cell can be embedded into a SoC and can be fabricated in a state-of-the-art, leading edge standard logic process with no additional process steps or additional special masks. In an embodiment, the electrically-alterable non-volatile memory cell compiler is designed for embedded applications in the standard CMOS logic process.

In one embodiment, the software used to facilitate the memory compiler can be embodied onto a machine-readable medium. A machine-readable medium includes any mechanism that provides (e.g., stores and/or transmits) information in a form readable by a machine (e.g., a computer). For example, a machine-readable medium includes read only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; DVD's, electrical, optical, acoustical or other form of propagated signals (e.g., carrier waves, infrared signals, digital signals, EPROMs, EEPROMs, FLASH, magnetic or optical cards, or any type of media suitable for storing electronic instructions. Slower mediums could be cached to a faster, more practical, medium.

FIG. 7illustrates a cross sectional view of the dopings and cell structure of an exemplary positive channel-MOS electrically-alterable non-volatile memory cell. In an embodiment, the electrically alterable non-volatile memory cell700may include components similar to those illustrated inFIG. 2such as a coupling capacitor702having a first gate708composed of both N+ doped material759and P+ doped material758, and a P+ doped region710abutted to a N+ doped region718. However, the polarities and components making up the read transistor slightly differ. The N+ doped gate of the read transistor720is surrounded by a third P+ region752and a fourth P+region754. Insulating material728separates the N+ gate of the read transistor720and a third Nwell region734. Mounted on top of the third P+ region752is a P+ contact, the Source terminal764. Mounted on top of the fourth P+ region754is a P+ contact, the Drain terminal762. The memory cell700inFIG. 7operates similarly to the negative channel-MOS memory cell illustrated inFIG. 2except for the polarities of the components being different.

In an embodiment, each component is in its own discrete well. The read transistor704is in a first Nwell734a. The tunneling capacitor706is in a second Nwell734b. Lastly, the coupling capacitor is in a third Nwell734c.

Also, in an embodiment, the gate of each capacitor may be entirely doped N+ or entirely doped P+.

FIGS. 8A,8B and8C illustrate a schematic diagram of an embodiment of a PMOS implementation of the electrically-alterable non-volatile memory cell. Referring toFIGS. 8A,8b, and8c, the electrically-alterable non-volatile memory cell800consists of the tunneling capacitor806(CT), the coupling capacitor802(CC) and the read transistor804(RT). These three components share a single floating gate860. In an embodiment, this represents an exemplary positive channel-MOS electrically-alterable non-volatile memory cell. The operation of the exemplary positive channel-MOS electrically alterable non-volatile memory cell is similar to that previously described inFIGS. 4a,4b, and4c. A notable exception is that the source terminal864and drain terminal862of the read transistor804are tied to the same potential voltage through the common Nwell.

In an embodiment, the logic consists of electronic circuits that follow the rules of Boolean Logic, software that contain patterns of instructions, or any combination of both. An embedded memory typically is made up an array of rows and columns of memory cells.

In an embodiment, an exemplary memory compiler may comprise the following. A graphic user interface, a common set of processing elements, and a library of files containing design elements such as circuits, control logic, and cell arrays that define the complier. In an embodiment, object code in a set of executable software programs. A nonvolatile random access memory compiler architecture that includes one or more electrically-alterable non-volatile memory cells is a serial/parallel memory featuring a static random access memory (SRAM) section overlaid bit-for-bit with a nonvolatile electrically alterable read only memory (EAROM). The nonvolatile random access memory compiler is designed for embedded applications in the generic TSMC 0.18 um logic process. No additional special masks or special process steps are required. The nonvolatile random access memory design allows data to be easily transferred from SRAM to EAROM section (STORE operation) and back from EAROM to SRAM section (RECALL operations). The STORE and RECALL operations work simultaneously with all memory bits. The STORE operation may be usually completed in less than 300 ms (around 20 us per bit for the largest 16384 bit instance) and the RECALL operation is completed in 10 us or less (around 0.6 ns per bit for the largest 16384 bit instance).

The nonvolatile random access memory is designed for unlimited serial and parallel access to the SRAM section and minimum of 1000 STORE operations to the EAROM. Data retention is specified to be greater than 10 years in power off state (storage) or idle mode and unlimited in the keep mode. Endurance (data changes per bit) is specified to be 100 or more.

For applications where low pin count interface is essential a serial access port can be used (SHIFT cycle). During the SHIFT cycle the SRAM section is reconfigured as a single long shift register and data can be shifted serially in via the serial input (SI) pin and observed on the serial output (SO) pin.

As noted, in an embodiment, a designer chooses the specifics of the memory configuration to produce a set of files defining the requested memory instances. A memory instance may include front end views and back end files. The front end views support documentation, simulation, debugging, and testing. The back end files, such as a layout, physical LEF, etc are for layout and fabrication.

While some specific embodiments of the invention have been shown the invention is not to be limited to these embodiments. For example, the doping of the components may be reversed for implementing a NMOS structure. Geometric arrangements of the components may change. Dopings of the components may change, etc. The invention is to be understood as not limited by the specific embodiments described herein, but only by scope of the appended claims.