SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

An apparatus includes: a semiconductor substrate having a first region, a second region and a third region; a first wiring above the first region of the semiconductor substrate; a second wiring above the second region of the semiconductor substrate; a third wiring above the third region of the semiconductor substrate; and a first insulating film on each of the first, second and third wirings. A height of an upper surface of the first wiring is lower than a height of an upper surface of the second wiring; wherein the height of an upper surface of the second wiring is lower than a height of an upper surface of the third wiring Each of portions of the first insulating film disposed above the first, second and third wirings has an equal film thickness.

BACKGROUND

Recently, in semiconductor devices such as dynamic random access memory (DRAM), increased memory capacity is desired, and increases in memory capacity are being achieved with finer processing dimensions. However, this results in a thinner insulating film over the wirings, and shorts between wirings may occur in some cases.

DETAILED DESCRIPTION

Various embodiments of the present disclosure will be explained below in detail with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings that show, by way of illustration, specific aspects, and various embodiments of the present disclosure. The detailed description provides sufficient detail to enable those skilled in the art to practice these embodiments of the present disclosure. Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of the present disclosure. The various embodiments disclosed herein are not necessary mutually exclusive, as some disclosed embodiments can be combined with one or more other disclosed embodiments to form new embodiments.

Hereinafter, a semiconductor device and a method of forming the same according to an embodiment will be described with reference to the drawings. In the following description, dynamic random access memory (hereinafter referred to as DRAM) is given as an example of the semiconductor device. In the description of the embodiment, common or related elements and elements that are substantially the same are denoted with the same signs, and the description thereof will be reduced or omitted. In the drawings referenced hereinafter, the dimensions and dimensional ratios of each unit in each of the drawings do not necessarily match the dimensions and dimensional ratios in the embodiment. Furthermore, in the following description, the Y direction is the direction at a right angle to the X direction. Also, the Z direction is the direction at a right angle to the X-Y plane defined as the plane of a semiconductor substrate, and is also referred to as the vertical direction.

Hereinafter, the semiconductor device according to the embodiment will be described.FIGS.1,2, and3illustrate a schematic configuration of a semiconductor device formed on a semiconductor substrate2.FIG.1illustrates a schematic configuration of a memory cell region.FIG.2illustrates a schematic configuration of a sense amplifier or sub-word driver region (SA/SWD region). The sense amplifier or sub-word driver is connected to the memory cell region.FIG.3illustrates a schematic configuration of a peripheral circuit region.

As illustrated inFIG.1, an isolation4, word lines6, bit lines8, and capacitors18are provided on the semiconductor substrate2. The region other than the isolation4is an active region3. The semiconductor substrate2includes a disc-shaped single-crystal silicon wafer provided with a main surface that has been given a mirror finish, for example. The isolation4includes a plurality of insulating films embedded in trenches formed in the semiconductor substrate2, for example.

As illustrated inFIG.1, the plurality of word lines6each extend in the X direction. The word lines6include a layered film of a plurality of conducting films. The plurality of bit lines8each extend in the Y direction. The bit lines8include a layered film of a plurality of conducting films. The word lines6and bit lines8contain conducting materials such as polysilicon, titanium nitride (TiN), and tungsten (W) doped with an impurity such as phosphorus, arsenic, or boron, for example.

The bit lines8are connected to the active region3through a bit line contact8ain the region adjacent to one of the word lines6in the X direction. The capacitors18are connected to the active region3through a first capacitor contact plug10, a second capacitor contact plug12, and a pad14in the region adjacent to another of the word lines6in the X direction. The first capacitor contact plug10and the second capacitor contact plug12contain conducting materials such as titanium nitride (TiN) and tungsten (W), for example. The first capacitor contact plug10, the second capacitor contact plug12, and the pad14penetrate through a first interlayer insulating film9provided on the isolation4and the bit lines8. The pad14contains a conducting material such as tungsten, for example.

The capacitors18are provided with a multilayer film of a first capacitor electrode18a, a capacitance insulating film18b, and a second capacitor electrode18c. The first capacitor electrode18acontains a conducting material such as titanium nitride (TiN), for example. The capacitance insulating film18bcontains an insulating material such as zirconium oxide (ZrOx), for example. The second capacitor electrode18ccontains a conducting material such as titanium nitride, for example.

The first capacitor electrode18apenetrates through a second interlayer insulating film15and a third interlayer insulating film16provided on the first interlayer insulating film9and the pad14. The second capacitor electrode18chas a pillar shape and extends in the Z direction.

The capacitance insulating film18band the second capacitor electrode18care provided on the sides of the first capacitor electrode18a. The capacitors18are interconnected by beams20and upper capacitor insulation22. An inter-capacitor insulating film21is embedded between the capacitors18. The beams20contain an insulating material such as silicon nitride (SiN), for example. The inter-capacitor insulating film21contains an insulating material such as silicon dioxide (SiO2), for example. The upper capacitor insulation22is provided on top of the capacitors18and the inter-capacitor insulating film21. The upper capacitor insulation22contains an insulating material such as silicon nitride, for example.

On top of the upper capacitor insulation22, a first plate electrode24and a second plate electrode26are provided. The first plate electrode24contains a conducting material such as polysilicon doped with phosphorus or arsenic, for example. The second plate electrode26contains a conducting material such as tungsten, for example. The first plate electrode24and the second plate electrode26are connected to the second capacitor electrode18cin a different location not illustrated in the drawings.

A fourth interlayer insulating film29is provided on top of the second plate electrode26. The fourth interlayer insulating film29contains an insulating material such as silicon dioxide, for example. On the upper surface of the second plate electrode26, a first upper wiring contact plug30is connected to the second plate electrode26. The first upper wiring contact plug30contains a conducting material such as tungsten, for example. A seed layer31and a first upper wiring32are connected to the first upper wiring contact plug30. The seed layer31covers the lower and side surfaces of the first upper wiring32. The seed layer31contains a conducting material such as titanium or a copper (Cu) alloy, for example. The first upper wiring32contains a conducting material such as copper, for example. The first upper wiring contact plug30and the first upper wiring32penetrate through the fourth interlayer insulating film29.

A fifth interlayer insulating film34and a sixth interlayer insulating film35are disposed on the fourth interlayer insulating film29, the seed layer31, and the first upper wiring32. The fifth interlayer insulating film34contains an insulating material such as silicon nitride, for example. The sixth interlayer insulating film35contains an insulating material such as silicon dioxide, for example. A seed layer37, a second wiring contact plug36, and a second upper wiring38are connected to the first upper wiring32. The second wiring contact plug36and the second upper wiring38are configured as one, without a boundary. The seed layer37covers the lower and side surfaces of the second wiring contact plug36and the second upper wiring38. The seed layer37contains a conducting material such as titanium or a copper alloy, for example. The second wiring contact plug36and the second upper wiring38contain a conducting material such as copper, for example.

As illustrated inFIG.2, in the sense amplifier or sub-word driver region, a first peripheral transistor gate40of a transistor forming the circuit of a sense amplifier or a sub-word driver is provided on the semiconductor substrate2where an isolation5is provided. The first peripheral transistor gate40is provided with a first conducting section40b, a second conducting section40c, and a third conducting section40don a gate insulating film40aprovided on the semiconductor substrate2. The gate insulating film40acontains an insulating material such as silicon dioxide, for example. The first conducting section40b, the second conducting section40c, and the third conducting section40dcontain conducting materials. The first conducting section40bcontains titanium nitride, for example. The second conducting section40ccontains polysilicon doped with an impurity such as phosphorus, arsenic, or boron, for example. The third conducting section40dcontains tungsten, for example.

A sidewall insulating film42is provided on the side surfaces of the first peripheral transistor gate40. The first peripheral transistor gate40and the sidewall insulating film42are covered by an insulating film43. The sidewall insulating film42contains silicon dioxide, for example. The insulating film43contains silicon nitride, for example. A first wiring lower contact plug46ais provided beside the first peripheral transistor gate40. The first wiring lower contact plug46acontains tungsten surrounded and covered by a barrier metal including titanium and titanium nitride.

A peripheral interlayer insulating film48is provided on the first peripheral transistor gate40. The peripheral interlayer insulating film48contains silicon nitride, for example. A plurality of first wirings50are provided on the peripheral interlayer insulating film48. The first wiring50contains a conducting material such as tungsten, for example. The second interlayer insulating film15is provided on top of the first wiring50. The second interlayer insulating film15contains silicon dioxide, for example. The first wiring50and the first wiring lower contact plug46aare connected by a first wiring upper contact plug46b. The first wiring upper contact plug46bpenetrates through the peripheral interlayer insulating film48. The first wiring upper contact plug46bcontains tungsten surrounded and covered by a barrier metal including titanium and titanium nitride.

A second wiring contact plug53and a second wiring54are provided on the second interlayer insulating film15. The lower and side surfaces of the second wiring contact plug53and the second wiring54are covered by a barrier metal52. The second wiring contact plug53penetrates through the second interlayer insulating film15, and the first wiring50and the second wiring contact plug53are connected through the barrier metal52. The second wiring contact plug53and the second wiring54are configured as one, without a boundary in between. The second wiring contact plug53and the second wiring54contain a conducting material such as tungsten, for example. The barrier metal52contains titanium and titanium nitride. An under-wiring insulating film51is provided between the second wiring54and the second interlayer insulating film15. The under-wiring insulating film51contains silicon dioxide, for example. The upper and side surfaces of the second interlayer insulating film15, the second wiring54, and the under-wiring insulating film51are covered by the third interlayer insulating film16. The third interlayer insulating film16contains silicon nitride, for example.

The fourth interlayer insulating film29is provided on top of the third interlayer insulating film16. A first upper wiring contact plug60is connected to the second wiring54. A seed layer61and a first upper wiring62are connected to the first upper wiring contact plug60. The first upper wiring contact plug60and the first upper wiring62penetrate through the fourth interlayer insulating film29. The first upper wiring contact plug60, the seed layer61, and the first upper wiring62are each included in the same layer as the first upper wiring contact plug30, the seed layer61, and the first upper wiring32described above, and contain the same materials.

The fifth interlayer insulating film34and the sixth interlayer insulating film35are disposed on the fourth interlayer insulating film29, the seed layer61, and the first upper wiring62. A seed layer63, a second upper wiring contact plug64, and a second upper wiring66are connected to the first upper wiring62. The second upper wiring contact plug64and the second upper wiring66are configured as one, without a boundary. The seed layer63covers the lower and side surfaces of the second upper wiring contact plug64and the second upper wiring66. The seed layer63, the second upper wiring contact plug64, and the second upper wiring66are included in the same layer as the seed layer37, the second wiring contact plug36, and the second upper wiring38described above, and contain the same materials.

As illustrated inFIG.3, in the peripheral circuit region, a second peripheral transistor gate68of a transistor forming a peripheral circuit is provided on the semiconductor substrate2where the isolation5is provided. The second peripheral transistor gate68is provided with a first conducting section68b, a second conducting section68c, and a third conducting section68don a gate insulating film68aprovided on the semiconductor substrate2. The gate insulating film68a, the first conducting section68b, the second conducting section68c, and the third conducting section68dare each included in the same layer as the gate insulating film40a, the first conducting section40b, the second conducting section40c, and the third conducting section40ddescribed above, and contain the same materials.

The sidewall insulating film42is provided on the side surfaces of the second peripheral transistor gate68. A third wiring contact plug70is connected to an upper portion of the second peripheral transistor gate68. The third wiring contact plug70contains tungsten surrounded and covered by a barrier metal including titanium and titanium nitride.

The peripheral interlayer insulating film48is provided on the second peripheral transistor gate68. A third wiring72is provided on the peripheral interlayer insulating film48. The third wiring contact plug70is included in the same layer as the first wiring50, and contains the same material. The second interlayer insulating film15is provided on top of the third wiring72. A fourth wiring contact plug75and a fourth wiring76are provided on the upper surface of the third wiring72. The lower and side surfaces of the fourth wiring contact plug75and the fourth wiring76are covered by a barrier metal74. The fourth wiring contact plug75penetrates through the second interlayer insulating film15, and the first wiring50and the fourth wiring contact plug75are connected through the barrier metal74. The fourth wiring contact plug75and the fourth wiring76are configured as one, without a boundary in between. The barrier metal74, the fourth wiring contact plug75, and the fourth wiring76are included in the same layer as the barrier metal52, the second wiring contact plug53, and the second wiring54, and contain the same materials. The under-wiring insulating film51is provided between the fourth wiring76and the second interlayer insulating film15. The upper and side surfaces of the second interlayer insulating film15, the fourth wiring76, and the under-wiring insulating film51are covered by the third interlayer insulating film16.

The fourth interlayer insulating film29is provided on top of the third interlayer insulating film16. A third upper wiring contact plug80is connected to the fourth wiring76on the upper surface of the fourth wiring76. A seed layer81and a third upper wiring82are connected to the third upper wiring contact plug80. The seed layer81covers the lower and side surfaces of the third upper wiring82. The third upper wiring contact plug80and the third upper wiring82penetrate through the fourth interlayer insulating film29. The third upper wiring contact plug80, the seed layer81, and the third upper wiring82are each included in the same layer as the first upper wiring contact plug30, the seed layer31, and the first upper wiring32described above, and contain the same materials.

The fifth interlayer insulating film34and the sixth interlayer insulating film35are disposed on the fourth interlayer insulating film29, the seed layer81, and the third upper wiring82. A seed layer83, a fourth upper wiring contact plug84, and a fourth upper wiring86are connected to the third upper wiring82. The fourth upper wiring contact plug84and the fourth upper wiring86are configured as one, without a boundary. The seed layer83covers the lower and side surfaces of the fourth upper wiring contact plug84and the fourth upper wiring86. The seed layer83, the fourth upper wiring contact plug84, and the fourth upper wiring86are each included in the same layer as the seed layer37, the second wiring contact plug36, and the second upper wiring38described above, and contain the same materials.

As illustrated inFIGS.1,2, and3, the height H1of the upper surface of the pad14is lower than the height H2of the upper surface of the first wiring50. The height H2of the upper surface of the first wiring50is lower than the height H3of the upper surface of the third wiring72. The heights H1, H2, and H3are defined as distances from the back surface of the semiconductor substrate2, for example. The film thickness T1of the second interlayer insulating film15on the pad14, the film thickness T2of the second interlayer insulating film15on the first wiring50, and the film thickness T3of the second interlayer insulating film15on the third wiring72are the same.

Next, a method of forming the semiconductor device according to the embodiment will be described. The description of the method of forming the semiconductor device according to the embodiment starts from the process by which the first interlayer insulating film9, the pad14, the first wiring50, and the third wiring72have been formed. As illustrated inFIGS.2,3, and4, the second interlayer insulating film15is formed. The second interlayer insulating film15is deposited using chemical vapor deposition (CVD), for example.

Next, as illustrated inFIGS.7,8, and9, a first sacrificial film90and a second sacrificial film92are formed on the second interlayer insulating film15. The first sacrificial film90contains silicon nitride, for example, and is deposited by CVD and atomic layer deposition (ALD), for example. The second sacrificial film92is an insulating film containing carbon, and is formed by a coating method, for example. The second sacrificial film92is formed to have a flat upper surface.

Next, as illustrated inFIGS.10,11, and12, anisotropic dry etching technology is used to etch back the second sacrificial film92, the first sacrificial film90, and the second interlayer insulating film15. The anisotropic dry etching at this stage is performed using conditions whereby the etch rate is the same for the first sacrificial film90, the second sacrificial film92, and the second interlayer insulating film15. The anisotropic dry etching causes the film thickness T1of the second interlayer insulating film15remaining on the pad14, the film thickness T2of the second interlayer insulating film15remaining on the first wiring50, and the film thickness T3of the second interlayer insulating film15remaining on the third wiring72to be the same thickness.

Next, as illustrated inFIGS.13,14, and15, the under-wiring insulating film51is deposited on the second interlayer insulating film15. The under-wiring insulating film51is deposited using CVD. Next, a contact hole94opening over the first wiring50and a contact hole96opening over the third wiring72are formed. The contact holes94and96are formed using known lithography technology and anisotropic dry etching technology.

Next, as illustrated inFIGS.16,17, and18, the conducting material to serve as the barrier metal52and74and the conducting film to serve as the second wiring54and fourth wiring76are deposited on the under-wiring insulating film51. The conducting material to serve as the barrier metal52and74and the conducting film to serve as the second wiring54and fourth wiring76are deposited by CVD, for example. The barrier metal52and74are included in the same layer. The second wiring54and fourth wiring76are included in the same layer.

Next, as illustrated inFIGS.19,20, and21, the conducting material to serve as the barrier metal52and74and the conducting film to serve as the second wiring54and fourth wiring76are patterned, thereby forming the second wiring contact plug53, the second wiring54, the fourth wiring contact plug75, and the fourth wiring76. The patterning is performed by known lithography technology and anisotropic dry etching technology. Note that, as illustrated inFIG.19, in the memory cell region, the conducting material to serve as the barrier metal52and the conducting film to serve as the second wiring54are removed.

Next, as illustrated inFIGS.22,23, and24, the third interlayer insulating film16is deposited to cover the top of the second interlayer insulating film15, the side surfaces of the under-wiring insulating film51, the side surfaces of the barrier metal52and74, and the upper and side surfaces of the second wiring54and fourth wiring76. The third interlayer insulating film16is deposited using ALD, for example.

Next, as illustrated inFIGS.1,2, and3, in the memory cell region, the capacitors18, the first upper wiring contact plug30, the first upper wiring32, the second wiring contact plug36, the second upper wiring38, and the like are formed on the third interlayer insulating film16. In the sense amplifier or sub-word driver region, the first upper wiring contact plug60, the first upper wiring62, the second upper wiring contact plug64, the second upper wiring66, and the like are formed. In the peripheral circuit region, the third upper wiring contact plug80, the third upper wiring82, the fourth upper wiring contact plug84, the fourth upper wiring86, and the like are formed. According to the above processes, the semiconductor device according to the embodiment is formed.

As described above usingFIGS.10,11, and12, in the embodiment, anisotropic dry etching technology is used to etch back the second sacrificial film92, the first sacrificial film90, and the second interlayer insulating film15. With this arrangement, the film thicknesses T1, T2, and T3of the second interlayer insulating film15on the pad14, the first wiring50, and the third wiring72are the same while satisfying the condition that “height of upper surface of pad14<height of upper surface of first wiring50<height of upper surface of third wiring72”. Accordingly, the second interlayer insulating film15on the first wiring50and on the third wiring72does not thin out, nor are the upper surfaces of the first wiring50and the third wiring72exposed. Consequently, damage imparted to the first wiring50or the third wiring72by anisotropic dry etching can be suppressed. Therefore, the refresh characteristics and row hammer characteristics of the semiconductor device according to the embodiment can be improved.

As above, DRAM is described as an example of the semiconductor device according to the embodiment, but the above description is merely one example and not intended to be limited to DRAM. Memory devices other than DRAM, such as static random-access memory (EPROM), (SRAM), flash memory, erasable programmable read-only memory (magnetoresistive random-access memory (MRAM), and phase-change memory, for example, can also be applied as the semiconductor device. Furthermore, devices other than memory, including logic ICs such as a microprocessor and an application-specific integrated circuit (ASIC), for example, are also applicable as the semiconductor device according to the embodiment.

Although various embodiments have been disclosed in the context of certain preferred embodiments and examples, it will be understood by those skilled in the art that the scope of the present disclosure extends beyond the specifically disclosed embodiments to other alternative embodiments and/or uses of the embodiments and obvious modifications and equivalents thereof. In addition, other modifications which are within the scope of this disclosure will be readily apparent to those of skill in the art based on this disclosure. It is also contemplated that various combination or sub-combination of the specific features and aspects of the embodiments may be made and still fall within the scope of the disclosure. It should be understood that various features and aspects of the disclosed embodiments can be combined with or substituted for one another in order to form varying modes of the disclosed embodiments. Thus, it is intended that the scope of at least some of the present disclosure should not be limited by the particular disclosed embodiments described above.