Energy harvesting interface with improved impedance matching, method for operating the energy harvesting interface, and energy harvesting system using the energy harvesting interface

An energy harvesting interface receives an electrical signal from an inductive transducer and supplies a supply signal. The interface includes an input branch with a first switch and a second switch connected together in series between a first input terminal and an output terminal. The interface further includes a third switch and a fourth switch connected together in series between a second input terminal and the output terminal. A first electrical-signal-detecting device, coupled across the second switch, detects a first threshold value of an electric storage current in the inductor of the transducer. A second electrical-signal-detecting device, coupled across the fourth switch, detects whether the electric supply current that flows through the fourth switch reaches a second threshold value lower than the first threshold value. The second threshold is derived from the electric storage current.

PRIORITY CLAIM

This application claims priority to Italian Application for Patent No. TO2014A000128 filed Feb. 14, 2014, the disclosure of which is incorporated by reference.

TECHNICAL FIELD

The present invention relates to an energy harvesting interface with improved impedance matching, a method for operating the energy harvesting interface, and an energy harvesting system comprising the energy harvesting interface.

BACKGROUND

As is known, systems for harvesting energy (also known as “energy-scavenging systems”) from intermittent environmental-energy sources (i.e., ones that supply energy in an irregular way) have aroused and continue to arouse considerable interest in a wide range of technological fields. Typically, energy harvesting systems are configured to harvest, store, and transfer energy generated by mechanical or thermal sources to a generic load of an electrical type.

Low-frequency vibrations, such as, for example, mechanical vibrations of disturbance in systems with moving parts may be a valid source of energy. The mechanical energy is converted, by one or more appropriate transducers (for example, piezoelectric or electromagnetic devices) into electrical energy, which may be used for supplying an electrical load. In this way, the electrical load does not require batteries or other supply systems, which are cumbersome and present a low resistance in regard to mechanical stresses.

FIG. 1is a schematic illustration in the form of functional blocks of an energy harvesting system of a known type.

FIG. 2shows, according to a simplified circuit representation, the energy harvesting system ofFIG. 1.

The energy harvesting system ofFIG. 1comprises: a transducer2, for example of an electromagnetic or piezoelectric type, subject in use to environmental mechanical vibrations and configured to convert mechanical energy into electrical energy, typically into AC (alternating current) voltages; a scavenging interface4, for example comprising a diode-bridge rectifier circuit (also known as Graetz bridge), configured to receive at input the AC signal generated by the transducer2and supplying at output a DC (direct current) signal for charging a capacitor5connected to the output of the rectifier circuit4; and a DC-DC converter6, connected to the capacitor5for receiving at input the electrical energy stored by the capacitor5and supplying it to an electrical load8. Thus, the capacitor5has the function of an element for storing energy, which is made available, when required, to the electrical load8for operation of the latter.

This type of interface, which operates as a peak detector, presents some drawbacks. The efficiency of the system1ofFIG. 1is markedly dependent upon the signal generated by the transducer2. In the absence of the DC-DC converter6, the efficiency rapidly drops to zero (i.e., the system1is unable to harvest environmental energy) when the amplitude of the signal of the transducer2(signal VTRANSD) assumes a value lower, in absolute value, than VOUT+2VTH_Dwhere VOUTis the voltage across the capacitor5, and VTH_Dis the threshold voltage of the diodes that form the energy harvesting interface4. As a consequence of this, the maximum energy that may be stored in the capacitor5is limited to the value Emax=0.5·COUT·(VTRANSDMAX−2VTH_D)2. If the amplitude of the signal VTRANSDof the transducer2is lower than twice the threshold voltage VTH_Dof the diodes of the rectifier of the energy harvesting interface4(i.e., VTRANSD<2VTH_D), then the efficiency of the system1is zero, the voltage across the output capacitor5is zero, the environmental energy is not harvested, and the electrical load8is not supplied.

When the DC-DC converter6(of a boost type) is set between the output capacitor5and the electrical load8, it is possible to make up for the drop in efficiency. However, in this situation, the current supplied by the transducer and rectified by the diode bridge is not regulated and is not actively controlled. Consequently, the impedance RLOADrepresented schematically inFIG. 2cannot be matched to the series impedance RSof the transducer2. This in any case causes a global loss of efficiency of the system1.

A further solution, which enables active control of the current supplied by the transducer2, envisages use of an AC-DC converter. This solution, for example proposed by IEEE TRANSACTIONS ON POWER ELECTRONICS, Vol. 25, No. 8, August 2010, pp. 2188-2199 (incorporated by reference), envisages the use of a closed-loop boost converter that exploits directly the series inductance of the transducer and generates a regulated voltage that charges the output capacitor. It is thus possible to supply the electrical load8directly by the output capacitor, without the aid of a DC-DC converter6of the type illustrated inFIG. 1. The control loop enables the voltage on the output capacitor for being kept substantially constant. However, this solution presents some disadvantages. For instance, if the load requires a supply power that exceeds the maximum power that the output capacitor may supply, the regulated output voltage drops to zero in a substantially immediate way. Furthermore, in this condition, the AC-DC converter is unable to make up immediately for the voltage drop on the output capacitor, harvesting further energy for supply of the electrical load. The energy harvesting efficiency is thus jeopardized.

SUMMARY

Embodiments provide an energy harvesting interface, a method for operating the energy harvesting interface, a system for harvesting environmental energy comprising the energy harvesting interface, and an apparatus comprising the environmental-energy harvesting system that will enable the aforementioned problems and disadvantages for being overcome.

The energy harvesting interface (in particular, having the configuration of a rectifier circuit) may be connected between an input-signal source (in particular, a variable voltage signal) and an electrical load (with the optional interposition of a DC-DC converter configured to supply to the electrical load a voltage signal having a voltage level accepted by the electrical load). The energy harvesting interface comprises, according to one embodiment, a first switch and a second switch, set in series with respect to one another, connected between an input terminal of the interface and a reference terminal of the interface, set at constant voltage (e.g., ground voltage, in particular 0 V). The interface further comprises a third switch and a fourth switch, set in series with respect to one another, connected between an input terminal of the interface and the reference terminal of the interface on which the energy is harvested.

The energy harvesting interface further comprises a control logic, coupled to the control terminals of the first and second switches, configured to open/close the first and second switches by an appropriate control signal.

The energy harvesting interface further comprises, as has been said, additional, third and fourth, switches, each having a control terminal. In use, for a polarity of the transduced input signal, the third and fourth switches are kept closed and are used during steps of detection of the current that flows through them, by the control logic. These detection steps define passage from a condition of storage of energy harvested by the transducer (exploiting the inductor integrated in the transducer itself) to a condition of transfer of said energy at output, for example to a storage capacitor and/or to an electrical load.

The storage capacitor is coupled to the output of the energy harvesting interface, for example, via diodes or controlled switches. The electrical load may be coupled in parallel to the storage capacitor, said electrical load being supplied by the energy stored in the capacitor.

As has already been said, a DC-DC converter, of buck, or boost, or buck/boost type may be optionally set between the capacitor and the electrical load.

In a first operating condition, and for a first polarity of the transduced voltage, the first and second switches are closed and the energy harvesting interface stores electrical energy; the diode guarantees that during this operating condition the energy will not flow to the storage capacitor.

In a second operating condition, and for the first polarity of the transduced voltage, the first switch is opened and the second switch is kept closed; the capacitor is charged by the electrical energy previously stored during the first operating condition and transferred through the diode.

In the aforementioned first and second operating conditions, the third and fourth switches are kept closed (i.e., ON).

Passage from the first operating condition to the second operating condition, and vice versa, is cyclic. When the transduced voltage has a second polarity opposite to the first polarity (e.g., the first polarity is positive, and the second polarity is negative), the above operations are carried out in a similar way by appropriately controlling the third and fourth switches and keeping the first and second switches closed (ON).

The temporal duration of the first and second operating conditions is calculated by appropriate blocks for detecting the current that flows between the inputs of the energy harvesting interface and the reference terminal. These values are then supplied to the control logic that controls the switches according to one aspect.

The energy harvesting interface is described in detail with reference to an application thereof, in particular as rectifier circuit of an energy harvesting system set between a voltage source and a storage element and/or an electrical load.

DETAILED DESCRIPTION OF THE DRAWINGS

FIG. 3Ashows an energy harvesting system20comprising a rectifier circuit24, according to one embodiment.

In general, the energy harvesting system20comprises: a transducer22(similar to the transducer2ofFIG. 1) including its own output terminals22′,22″; the rectifier circuit24, including a first input terminal25′ and a second input terminal25″, electrically coupled, respectively, to the output terminals22′,22″ of the transducer22, a first output terminal26′, and a reference terminal26″; and a storage element27, for example a capacitor, connected between the first output terminal26′ and the reference terminal26″ of the rectifier circuit24, and configured to store electrical charge supplied at output from the rectifier circuit24. According to one embodiment, the reference terminal26″ is a ground-voltage reference terminal GND, for example equal to approximately 0 V. Other reference voltages may be used.

The transducer22is, for example, an electromagnetic transducer, and is represented schematically for including a voltage generator22a, configured to supply a voltage VTRANSD, an inductor22b(typical of the electromagnetic transducer) having an inductance LS, and a resistor22chaving a resistance RS, connected in series to the inductor22b.

On the output of the rectifier circuit24, in parallel with the storage element27, there may be connected an electrical load28, configured for being supplied by the charge stored in the storage element27or by means, for example, of a DC-DC converter (not illustrated in the figures) in the case where the electrical load requires a voltage value different from the voltage generated at output from the rectifier circuit24.

Connected in series together between the first input terminal25′ and the reference terminal26″ of the rectifier circuit24are a high-voltage (HV) switch30aand a low-voltage (LV) switch30b, in particular of the voltage-controlled type. The switches30aand30bare, for example, N-channel field-effect transistors (FETs).

The HV switch30ais a device that is able to withstand high voltages. According to one embodiment, the HV switch30ais a DMOS transistor configured to operate with gate-to-drain voltages (VGD) and drain-to-source voltages (VDS) ranging between 30 and 50 V, for example 40 V.

In addition to DMOSs, it is likewise possible to use drift MOSs and drain extension MOSs, which are transistors that may withstand high voltages between drain and source terminals, and between gate and drain terminals. It may be noted that the range of voltages indicated is purely indicative and non-limiting. Technologies configured to withstand voltages higher than 50 V are known and under development, and may likewise be used in the context of the present circuit.

The LV switch30bis a low-voltage device. According to one embodiment, the LV switch30bis a CMOS transistor configured to operate with gate-to-source voltages (VGS) ranging, for example, between 1 and 5 V, in particular 2.5-3.6 V, for example 3.3 V. Other technologies for low-voltage transistors envisage slightly higher operating voltages, for example in the region of 4-5 V.

It is evident that the values appearing indicate a possible embodiment, and vary according to the technology used for the transistors and to the specific application.

The first input terminal25′ is electrically coupled to the first output terminal26′ by a diode36. The diode36is chosen for having a low forward threshold voltage, in the region of 0.6-0.7 V, for maximizing the efficiency of the rectifier, above all in the steps where the voltage stored on the output capacitor is low.

According to an alternative embodiment (not illustrated), the diode36may be replaced by a MOSFET, for example, of the N-channel type. As is known, a MOSFET has an internal diode (parasitic diode). In this case, the MOSFET may be operated in an active way (by actively controlling turning-on and turning-off of the MOSFET), or in a passive way (by turning off the MOSFET and exploiting the internal parasitic diode).

Furthermore, the rectifier circuit24comprises a further HV switch31aand a further LV switch31b, connected together in series and electrically coupled between the second input terminal25″ and the reference terminal26″ of the rectifier circuit24. The switches31aand31bare similar to the switches30aand30b, and such that the HV switch31ais a device that is able to withstand high gate-to-drain voltages and drain-to-source voltages (for example 30-50 V, in particular 40 V), whereas the LV switch31bis a low-voltage device, for example a CMOS, which is able to withstand low gate-to-source voltages (for example, 1-5 V, in particular 2.5-3.6V, even more in particular 3.3 V). Other technologies for low-voltage transistors envisage slightly higher operating voltages, for example in the region of 4-5 V.

The second input terminal25″ is electrically coupled to the first output terminal26′ by a diode38, similar to the diode36. According to an alternative embodiment (not illustrated), the diode38may be replaced by a MOSFET, for example an N-channel MOSFET. As is known, a MOSFET has an internal diode (parasitic diode). In this case, said MOSFET may be operated in a active way (by actively controlling turning-on and turning-off of the MOSFET), or in a passive way (by turning off the MOSFET and exploiting the internal parasitic diode).

For simplicity of description, the HV switches30aand31awill hereinafter be referred to, respectively, as “high-voltage (HV) transistors30aand31a”, without this implying any loss of generality, and the LV switches30band31bbe referred to, respectively, as “low-voltage (LV) transistors30band31b”, without this implying any loss of generality.

Likewise, the terms “transistor closed” or “transistor ON” will hereinafter refer to a transistor biased so to enable conduction of electric current between its source and drain terminals, i.e., configured to behave as a closed switch, and the terms “transistor open” or “transistor OFF” will hereinafter refer to a transistor biased so not to enable conduction of electric current between its source and drain terminals, i.e., configured to behave ideally as an open or inhibited switch.

FIG. 3Bshows the energy harvesting system20ofFIG. 3A, where the switches have been replaced by respective transistors. Each transistor is further represented with its own internal diode (parasitic diode).

With reference toFIG. 3B, the drain terminal D of the HV transistor30ais connected to the first input terminal25′ of the rectifier circuit24, whereas the source terminal S of the HV transistor30ais connected to the drain terminal D of the LV transistor30b; the source terminal S of the LV transistor30bis instead connected to the reference terminal26″. The diode36has its cathode electrically coupled to the output terminal26′ of the rectifier circuit24and its anode electrically coupled to the first input terminal25′ of the rectifier circuit24.

As regards the HV transistor31aand LV transistor31b, these are connected between the second input terminal25″ and the reference terminal26″ of the rectifier circuit24so that the source terminal S of the LV transistor31bis connected to the reference terminal26″, the drain terminal D of the HV transistor31ais connected to the second input terminal25″, and the remaining drain terminal D of the LV transistor31band source terminal S of the HV transistor31aare connected together.

The diode38has its cathode electrically coupled to the output terminal26′ of the rectifier circuit24and its anode electrically coupled to the second input terminal25″ of the rectifier circuit24. During positive half-cycles of the input voltage VIN, the voltage is rectified by appropriately driving the HV transistor30a, keeping the transistors30b,31a,31bin the ON state. Instead, during negative half-cycles of the input voltage VIN, the voltage is rectified by appropriately driving the HV transistor31a, keeping the transistors31b,30a,30bin the ON state.

According to one embodiment, the rectifier circuit24further comprises a control circuit and a control logic, designated inFIG. 3AorFIG. 3Bby the reference numbers60and70, and better described with reference toFIGS. 8 and 9. Furthermore, the control logic60implements the steps of the method ofFIG. 11.

In use, for example for positive values of the voltage VIN, the HV transistor30aand the LV transistor30bare kept ON for at least a time interval TDELAYfor storing energy in the inductor22b(situation illustrated schematically inFIG. 4A). During this step, storage of the energy in the inductor22bis guaranteed by the fact that the diode36does not conduct. Furthermore, also the transistors31aand31bare kept in the ON state.

Then, when the time interval TDELAYhas elapsed and the energy stored (current flowing) in the inductor22bhas reached a minimum threshold value ITH, the HV transistor30ais turned off. A current may thus flow from the inductor22b, through the diode36, to the storage element27/electrical load28. This situation is illustrated schematically inFIG. 4B.

As has been said, the input signal VINis a variable signal, i.e., having a polarity that varies in time. For negative polarities of VIN, what has been described with reference toFIGS. 4A and 4Bis in any case valid by controlling in a similar way the transistors31aand31b. The steps of control of these transistors are not herein described for brevity, but are apparent to the person skilled in the branch on the basis of what has so far been described.

According to one embodiment, in both of the operating conditions ofFIGS. 4A and 4B, for positive polarities of the input voltage VIN, the LV transistor30bis always kept closed, and the control logic60drives just the HV transistor30ainto the open/closed state. Likewise, for negative polarities of the input voltage VIN, the control logic60drives just the HV transistor31ainto the open/closed state, whereas the LV transistor31bis always kept closed. This situation is schematically represented inFIG. 3B, which shows a voltage generator, configured to generate a voltage VDD, coupled to the control terminals G of the LV transistors30band31b. The voltage VDDis chosen with a value such as to drive the LV transistors30band31binto the closed state.

During the step ofFIG. 4B, where the current stored in the inductor22bis transferred at output on the storage element27by the diode36(or alternatively the diode38, according to the polarity of the input voltage VIN), an increase in the output voltage VOUTis noted.

Hereinafter, operation of the rectifier24is described more fully with reference to a circuit model valid for one polarity (in particular, the positive polarity) of the input signal VIN, for greater simplicity and clarity of description. As has been said, what has been described may in any case be readily applicable to control of the transistors31aand31b, in the case of negative polarity of the input signal VIN.

FIG. 4Ashows a circuit equivalent to the circuit ofFIG. 3AorFIG. 3B, for positive half-waves of the input voltage VIN. The diode36, in this condition, does not conduct. The transistors30aand30bare ON. In this operating condition, the transistors30aand30bare ideally replaced by respective resistors which have a resistance RHVONand, respectively, RLVON(ON-state resistance of the transistors30aand30b).

The current ILthat flows in the inductor22bis equal to the current IONthat traverses the transistors30aand30bin the ON state. The value of the current ILincreases until it reaches a maximum, or peak, value Ip(see the graph ofFIG. 5A).

The current IONreaches the peak value Ipat time t=tc=TDELAY. For simplicity, it is assumed that the starting instant t0is 0 μs.

Once the time interval TDELAYhas elapsed and assuming that the current ILthat flows in the inductor22bhas reached a value equal to, or higher than, the threshold value ITH, the operating condition represented schematically inFIG. 4Bis reached.

The time interval TDELAYis the interval between the instant of closing of the HV transistor30a(at time t0) and the instant of opening of the HV transistor30a(at time tc).

The value of threshold current ITHis chosen on the basis of the values of the maximum or of the minimum short-circuit current that the transducer supplies. It is the ratio between the maximum or minimum voltage VTRANSDand the series resistance RS, which depends on the application of the rectifier circuit24.

These values depend upon the characteristics of the transducer22and upon the environmental stresses to which the transducer22is subjected. In particular, the value of threshold current ITHis chosen much lower than the peak value Ipthat is expected for being reached in the application in which the rectifier circuit24is used. For instance, assuming that peak values Ipof approximately 150 mA are reached, the threshold ITHmay be chosen between approximately 5-10 mA. It is for being noted that the choice of a threshold current ITHtoo close to the peak value Ipentails a low efficiency. In fact, according to what has been described, current is transferred at output only when the threshold ITHis exceeded; all the portions of the signal VTRANSDthat generate a current with peak value Ip<ITHdo not give a contribution of charge transferred at output.

With reference toFIG. 4B, at time tc, the HV transistor30ais opened, and the diode36starts to conduct. The current ILthat flows from the inductor22bto the output26′ of the rectifier24is the current IOUTthat charges the capacitor27. In this step, the current in the inductor22bdecreases with a constant slope, until it reaches the predefined value IOFF(at time tmax, see againFIG. 5A).

IOFFis a constant value, given by Ip/K, where K is a constant higher than 1 (chosen as explained hereinafter).FIG. 5ashows the plot of the current ILat time t (in microseconds). The curve of the current ILreaches the peak value Ipat the instant tc, where the HV transistor30ais opened (seeFIG. 5B).

Then, between tcand tmax(time interval TCHARGE) the current ILdecreases until it reaches the value IOFF=Ip/K.

FIG. 5Bshows, using the same time scale as that ofFIG. 5A, the plot of the current IONthat flows through the HV transistor30aduring the step ofFIG. 4Aof charging of the inductor22b. In the time interval t0-tc, the current IONfollows the same plot as that of the current IL; at the instant tc, the HV transistor30ais opened and consequently the current IONdrops to zero.

FIG. 5Cshows, using the same time scale as that ofFIGS. 5A and 5B, the plot of the output current IOUT. The current IOUTremains at a zero value in the time interval t0−tcto reach the peak value Ipat the instant tcin which the capacitor27is electrically coupled to the inductor22b. Then, between tcand tmax(within the time interval TCHARGE), the energy stored in the inductor22bsupplies and charges the capacitor27.

At time tmax, when the current that flows to the capacitor27reaches the threshold value IOFF, the HV transistor30ais closed so that the inductor22bcharges again, as has already been described. The steps of charge and discharge of the inductor22b(and, consequently, of supply of the capacitor27/load28) repeat in a cyclic way.

The integral of the curve of IOUT(FIG. 5C) between time tcand time tmaxindicates the charge QCYCLEtransferred between the input and the output of the rectifier24in the time interval TCHARGE. In order to maximize the efficiency of transfer of charge between the input and the output of the rectifier24, it is expedient to maximize the value of the power PCYCLEtransferred at output from the rectifier circuit24in each cycle of charge/discharge of the inductor22b. The power PCYCLEis defined as PCYCLE=VOUT·ICYCLE, where ICYCLEis given by ICYCLE=QCYCLE/TCYCLE, where TCYCLEis the time interval between t0and tmax(TCYCLE=TDELAY+TCHARGE).

It is noted that PCYCLEis given by the following relation (where IONassumes the peak value Ip)

From the foregoing relation it may be noted how the power PCYCLEis a function of the design parameters TDELAYand K, and of the external variables VTRANSD(voltage of the transducer, not predictable) and VOUT(voltage across the capacitor27, which is not predictable either). Maximizing the value of PCYCLEthus means finding the optimal values of TDELAYand K such that the curve of PCYCLEreaches a maximum value, or a value close to the maximum, or an optimal value definable according to the particular application and design requirements.

The curve of PCYCLEreaches an optimal value when the output of the transducer22and the input of the rectifier circuit24show the same impedance (they are, that is, matched). The best coupling efficiency ηCOUPLEbetween the transducer22and the rectifier circuit24is given by PCYCLEOPT/PTRANSDMAX, where PCYCLEOPTis the value of PCYCLEcalculated with optimal values of TDELAYand K, and PTRANSDMAXis given by (VTRANSD)2/4RS.

Optimization of the value of PCYCLEenables an optimal value of the time interval TDELAYand of the factor K for being obtained (and vice versa) as a function of the value of VTRANSDand VOUT. However, the dependence of TDELAYupon VTRANSDand VOUTis irrelevant for practical purposes, and the value of coupling efficiency ηCOUPLEreaches values higher than 95% for values of VTRANSDand VOUTof practical interest.

FIG. 6shows the plot of the coupling efficiency ηCOUPLEas the values TDELAYand K vary. The graph ofFIG. 6may be easily obtained from the expression of PCYCLEby varying the parameters TDELAYand K (fixing the values of the external variables VTRANSDand VOUT). To each value of ηCOUPLEthere corresponds a pair of values TDELAYand K. It is thus possible to obtain automatically the pair of optimal values TDELAYand K to obtain a desired value of coupling efficiency ηCOUPLE. In the graph ofFIG. 6, the darker areas are the ones in which the value of coupling efficiency ηCOUPLEis higher; instead, the lighter areas are the ones in which the value of coupling efficiency ηCOUPLEis lower (low values of TDELAYand high values of K, or high values of TDELAYand low values of K).

In the specific case, a good compromise for the choice of the values of TDELAYand K, in order to have contained consumption levels and good coupling efficiency, is obtained by choosing TDELAY=40 μs and K=1.75. It is, however, evident that the choice of the values of TDELAYand K depends upon the field of application, and these values may thus be chosen freely according to the need (in general with K≧1).

FIG. 7shows, by functional blocks, a control circuit70for driving the HV transistor30ain order to implement the operating conditions ofFIGS. 4aand 4b. The control circuit70operates, in particular, for positive half-waves (VIN+) of the input signal VIN. The LV transistors30band31bare biased at constant voltage VDD, for being kept always in the ON state. The value of the voltage VDDis thus chosen on the basis of the characteristics of these transistors, with the purpose of driving them into the ON state.

In order to drive the HV transistor31afor negative half-waves of the input signal VIN, a circuit architecture is used similar to the one illustrated for the control circuit70(see, for example,FIG. 10).

In greater detail, the control circuit70comprises a first current detector72, coupled between the source terminal S and the drain terminal D of the LV transistor30b, for detecting (during the step ofFIG. 4A) the instant in which the current IONthat flows through the LV transistor30b(and, consequently, also through the HV transistor30a) exceeds the threshold ITH. When this condition is detected, and the interval TDELAYhas elapsed, the control logic60drives the HV transistor30ainto inhibition, thus controlling passage to the operating condition ofFIG. 4B. In addition, the current detector72participates in generation, in the step ofFIG. 4A, of a scaled copy ION/K of the current that flows in the LV transistor30b, as illustrated more clearly hereinafter.

FIG. 8shows in greater detail the first current detector72, according to one embodiment. With reference toFIG. 8, a first portion of the current detector72comprises a comparator86configured to receive at input, on its non-inverting terminal, the voltage signal present on the source terminal S of the HV transistor30a(or likewise on the drain terminal of the LV transistor30b) and, on its inverting terminal, a voltage signal VTHidentifying the threshold ITH(by an appropriate voltage-to-current conversion, in itself obvious). The comparator86generates at output a digital signal VOUT_TH, which assumes the low logic level “0” when ION<ITHand the high logic level “1” when ION≧ITH(or vice versa). In greater detail, the comparator86is configured to receive, at input on its non-inverting terminal, the voltage signal present on the source terminal of the HV transistor30a(signal VIN+), and, at input on its inverting terminal, a threshold-voltage signal VTHsuch that VTH=ITH·(RHVON+RLVON) where, as has already been said, RHVONis the ON-state resistance of the HV transistor30a, and RLVONis the ON-state resistance of the LV transistor30b. When the voltage on the source terminal of the HV transistor30aexceeds the threshold VTH, the output of the comparator86changes state to signal that the threshold has been exceeded (and thus to indicate that IL=ION≧ITH).

The signal at output from the comparator86is supplied to the control logic60. The control logic60monitors the duration of the time interval TDELAYand, when the time interval TDELAYhas elapsed, turns off the HV transistor30a.

Passage of the time interval TDELAYmay alternatively be monitored by the comparator86. In this case, the signal at output from the comparator86assumes a high logic level when ION≧ITHand t≧TDELAY, and the control logic60turns off the HV transistor30aat the rising edge of the digital signal generated by the comparator86.

A second portion of the current detector72comprises a negative feedback loop including a comparator89, which controls the current that flows on an output branch90of the current detector72, by acting on the control terminal of a transistor91belonging to the output branch90. The output branch90further comprises an additional transistor92, connected in series to the transistor91. Note that the transistor92is a low-voltage transistor, for example a CMOS. In particular, the transistor92is configured to operate with gate-to-source voltages in the range 1-5 V, in particular 2.5 V-3.6 V, for example at 3.3 V. Other low-voltage-transistor technologies envisage slightly higher operating voltages, for example in the region of 4-5 V.

In particular, the transistor92is of the same type as the LV transistor30b, but is sized so that it has dimensions (measured in terms of width-to-length aspect ratio W/L) F times lower than the LV transistor30band is configured to conduct a current F times lower than the value assumed by ION(current that flows through the LV transistor30b). The LV transistor30band the transistor92further have their respective control terminals connected together and biased at the voltage VDD.

The negative feedback loop of the current detector72controls the gate voltage of the transistor91so that the drain voltage of the transistor92will be equal to the voltage across the capacitor88. In use, current always flows in the output branch90. In the step ofFIG. 4A, the current is variable and equal to ION/F, whereas in the step ofFIG. 4Bthe current is constant and equal to Ip/F. Sizing of the transistor92guarantees that the current that flows in the output branch90is a fraction1/F of the current ION(or of its peak value Ip, as has been said).

The negative feedback, obtained by the comparator89and the transistor91, ensures that the drain voltages of the transistors30band92will be identical. Consequently, the current that flows through the transistor92assumes values equal to the value of IONscaled by the factor F (when IONreaches the peak value Ip, this current will be equal to Ip/F). There is thus generated a scaled copy of the factor F of the peak current Ip. Since both of the transistors30band92are low-voltage transistors (e.g., CMOSs) they provide excellent matching properties so that the factor F is minimally affected by problems of mismatch between the transistors30band92(as, instead, would be the case, where the transistors30band92were high-voltage transistors). This enables a scaled copy of the peak current Ipfor being obtained that is stable and with reproducible value.

The negative feedback provided by the comparator89ensures that the signal at input to the non-inverting terminal of the comparator89and the signal at input to the inverting terminal of the comparator89are equal so that the LV transistor30band the transistor92have the same source-to-drain and drain-to-gate voltages.

A current mirror90′, made in a per se known manner, is used for repeating the current ION/F that flows in the branch90and supplying it at output from the current detector72.

The first current detector72further comprises a transistor87having a drain terminal common to the source terminal of the HV transistor30a, and its source terminal coupled to a capacitor88(the second terminal of the capacitor88is connected to the reference voltage GND). The control terminal G of the transistor87is connected to the control terminal G of the HV transistor30aand to a biasing terminal at the voltage VGATE_LS. In this way, the HV transistor30aand the transistor87are driven into the ON/OFF state at the same time, using the same signal VGATE_LS(in particular, with reference toFIG. 7, the signal generated at output from a first driving device76).

During the time interval TDELAY(situation ofFIG. 4A), the HV transistor30ais ON (the signal VGATE_LShas a value such as to drive the HV transistor30ainto the ON state). In the same way, also the transistor87is ON. The capacitor88is consequently charged at the voltage present on the first input terminal25′ of the rectifier circuit24(in the figure, the voltage across the capacitor88is designated by VC_SAMPLE).

The comparator89is connected to the source terminal of the transistor87and, when the transistor87is ON, it receives at input (on its non-inverting terminal) the voltage of the drain terminal of the LV transistor30b, and at input (on its inverting terminal) the signal present on the drain terminal of the transistor92and on the source terminal of the transistor91; the output of the comparator89is coupled to the control terminal G of the transistor91. The transistor91is always ON; the comparator89biases the control terminal of the transistor91so that the current ION/F flows in the branch90, as is desired.

When the HV transistor30ais OFF, also the transistor87is OFF, and the capacitor88is in the floating state, ensuring, during the time interval TCHARGE, a current having a practically constant value through the transistor92and equal to Ip/F.

In fact, during the step of supply of the capacitor27/load28, the capacitor88ensures maintenance of the voltage VC_SAMPLEacross it, guaranteeing a substantially constant input signal (but for the losses of the capacitor88) on the non-inverting input of the comparator89. This enables generation of the current ION/F for being kept unaltered on the output branch90of the first current detector72during the step ofFIG. 4B(in this step, the current IONhas reached the peak value Ip, and consequently a current Ip/F flows in the output branch90of the first current detector72).

To return toFIG. 7, the control circuit70further comprises a second current detector74, coupled between the source terminal S and the drain terminal D of the LV transistor31b.

The second current detector74is configured to detect the value of current IOUTthat flows through the LV transistor31bduring the operating step ofFIG. 4B, i.e., following upon charging of the capacitor27. In particular, the second current detector74co-operates with the control logic60in order to detect whether the current IL=IOUTthrough the LV transistor31breaches the minimum value envisaged IOFF=Ip/K. The output signal of the second current detector74, which indicates the value of current through the LV transistor31b, is supplied at input to the control logic60.

The second current detector74receives at input the current ION/F (generated by the first current detector72, as described previously), and switches when the current through the LV transistor31breaches the minimum value envisaged, given by IOFF=Ip/K.

The control circuit70further comprises the first driving device76and a second driving device78, which are coupled, respectively, between the control logic60and the control terminal G of the HV transistor30aand between the control logic60and the control terminal G of the HV transistor31a. The first driving device76and the second driving device78are, in themselves, of a known type, and are configured to drive the transistors30a,31ainto the opening/closing condition on the basis of a respective control signal received from the control logic60. In particular, in the operating condition ofFIG. 4A(positive half-wave of the transduced signal VTRANSD), the control logic60drives, via the first driving device76, the HV transistor30ainto the ON state and, via the second driving device78, the HV transistor31ainto the ON state. On the basis of the signal generated at output from the first current detector72, the control logic60detects whether the current IL=IONhas reached (and/or exceeded) the threshold value ITHand whether the time TDELAYhas elapsed: if so, the control logic60drives, via the first driving device76, the HV transistor30ainto the OFF state and, via the second driving device78, maintains the HV transistor31ain the ON state. Then, the control logic60monitors, on the basis of the signal received from the second current detector74, the value of the current IL=IOUTthrough the LV transistor31bto control passage from the operating condition of supply of the capacitor27/load28(FIG. 4B) to the operating condition of storage of energy in the inductor22b(FIG. 4a).

The current detector74is electrically coupled to a node X set between the drain terminal D of the LV transistor31band the source terminal S of the HV transistor31a, for receiving at input an intermediate voltage signal VXpresent on said node X. The current detector74includes a coupling transistor85, of an N type, having its drain terminal coupled to the node X and its gate terminal biased at voltage VDD. As in the case mentioned previously, the voltage VDDis chosen with a value such as to drive into the ON state the coupling transistor85, which thus remains always ON during the operating steps of the energy harvesting system.

The current detector74further includes a comparator84, having an inverting input electrically coupled to the reference voltage GND and a non-inverting input electrically coupled to the source terminal of the coupling transistor85. In other words, the non-inverting input of the comparator84and the source terminal of the coupling transistor85are coupled to the same node Y, having a voltage VY. The node Y further receives the current signal ION/F generated at output by the first current detector72.

The comparator84generates at output a signal VOUTCOMPthat is configured to assume alternatively a high logic value “1” and a low logic value “0” according to the value assumed by the signal VY.

The coupling transistor85presents in use an internal resistance (channel resistance, or ON-state resistance) RDMY=G·RLS, where RLSis the internal resistance (channel resistance, or ON-state resistance) of the LV transistor31b. In other words, the resistance RDMYis chosen equal to a multiple G of RLS.

In use, it is found that the voltage VXon the node X is given by:
VX=−IL·RLS

and the voltage VYon the node Y is given by
VY=VX+G·RLS·ION/F

The output VOUTCOMPof the comparator84changes its logic value when the voltage VYreaches the threshold defined by the reference voltage GND, in this example chosen equal to 0 V. We obtain that the output of the comparator84changes its logic value when VY=0. From this condition it follows that the output VOUTCOMPidentifies the fact that, the value of scaled copy ION/K has been reached by the output current IL=IOUT. In fact, setting VY=0 in the previous equation, we have that the threshold current IL(i.e., the threshold current IOUT) is equal to (G/F)·ION. The constant K is consequently equal to F/G. It is pointed out that, as illustrated previously, in use, the value of IONat which there occurs passage from the step ofFIG. 4Ato the step ofFIG. 4Bis equal to Ip. Consequently, we find that the change of logic value of the signal VOUTCOMPidentifies that the threshold (G/F)·Ip=Ip/K has been reached.

With reference once again toFIG. 7, the signal VOUTCOMPof the comparator84is received by the control logic60, which controls, on the basis of the value of VOUTCOMPreceived, passage from the step ofFIG. 4Bto the step ofFIG. 4A. For instance, a value VOUTCOMP=“0” identifies a situation in which the current IOUThas not yet reached the threshold IOFF; instead, a value VOUTCOMP=“1” identifies a situation in which VY=0 and the current IOUThas reached the threshold IOFF.

Preferably, the transistors31b,92and85are low-voltage transistors manufactured with the same technology (e.g., CMOS technology) so that they guarantee optimal matching properties such that the factor G is minimally affected by problems of mismatch between the transistors31b,92, and85(as instead would be the case, where both of the transistors were high-voltage transistors). Stabilizing G around a desired value corresponds to stabilizing the values of K and F around the values chosen. The parameter K thus has a minimal spread around the chosen and desired value.

According to one embodiment, the transistors92(FIG. 8) and85(FIG. 9) are provided in the form of modular transistors. The transistors92and85may be obtained as a series or parallel combination of the same basic module for minimizing the mismatch between the factors F and G, and thus render the parameter K “stable”.

For instance, the transistor92is formed by connecting, in parallel to one another, a plurality of basic modules (each module being a low-voltage MOSFET with aspect ratio Wb/Lb) so that the source terminals of each basic module are electrically connected together to a common source node, and the drain terminals of each basic module are electrically connected together to a common drain node. The gate terminals of each basic module are selectively driven into the ON state or the OFF state to form, in use, the transistor92, the aspect ratio W/L of which is a multiple of the aspect ratio Wb/Lbof each basic module. In this way, by turning on/turning off selectively one or more basic modules, it is possible to regulate the total amount of current carried by the transistor92and consequently regulate the value of the ratio 1:F between the transistor92and the transistor30b.

A similar solution may be applied to form the transistor85, with variable value of G. In this case, it is possible to connect, in parallel to one another, a plurality of series of basic modules of low-voltage MOSFETs, which have the same aspect ratio (for example, Wb/Lb). Each series of basic modules presents, in use, a respective electrical resistance to the passage of the current. By selectively activating/deactivating the series of the basic modules that form the transistor85, it is thus possible to regulate the value of electrical resistance represented by the transistor85in use. The transistor85behaves as a resistor with a variable resistance that may be selected according to the requirement.

Consequently, the values of F and G may be chosen according to the need, as a function of the value of the parameter K that it is desired to use for the specific application.

Turning-on/turning-off of the basic modules of the transistors85and92is performed by the control logic during use. For this purpose, the control logic includes a memory83that stores the information regarding which and/or how many basic modules of the transistors85and92are for being turned on. If the memory83is of the re-writeable type, this information may be updated/modified according to the need.

The transistors30b,92and85are the components via which we it is possible to control ITH, the factors F and G, and consequently the factor K. By providing them in a modular form, as has been described, they may be readily configured via the memory83and appropriate driving devices, for enabling/disabling a certain number of basic modules thus obtaining respective equivalent transistors, which have a desired respective aspect ratio W/L.

Thus, with just one device, appropriately configured via the information stored in the integrated memory83, it is possible to vary freely ITH, TDELAYand K and thus adapt to a very wide range of transducers available on the market.

With reference toFIG. 10, a control circuit70′ is illustrated for driving both of the HV transistors30aand31ainto the ON/OFF state in order to implement the operating conditions of charging of the inductor22band supply of the capacitor27(and/or load28) for positive half-waves (VIN+) and negative half-waves (VIN−) of the input signal VIN.

Elements of the control circuit70′ that are similar to elements of the control circuit70ofFIG. 7are designated by the same reference numbers and will not be described any further.

The control circuit70′ comprises, in addition to what has already been described with reference to the control circuit70ofFIG. 7, a third current detector72′, and a fourth current detector74′.

The third current detector72′ is similar to the first current detector72, and consequently is not described and illustrated any further in the figures. The third current detector72′, unlike the first current detector72, is electrically coupled between the reference terminal GND (corresponding to the source terminal of the LV transistor31b) and the drain terminal of the LV transistor31b, and generates at output a current signal (ION/F)′.

The fourth current detector74′ is similar to the second current detector74, and consequently is not described and illustrated any further in the figures. The fourth current detector74′, unlike the second current detector74, is electrically coupled between the reference terminal GND (corresponding to the source terminal of the LV transistor30b) and the drain terminal of the LV transistor30b, and further receives at input the current signal (ION/F)′ generated by the third current detector72′.

Operation of the third and fourth current detectors is altogether similar to what has already been described with reference to the first and second current detectors72and74and consequently is immediately evident to a person skilled in the branch.

In use, when a positive half-wave of the input signal VINis detected, the control logic60monitors just the signals generated at output from the first signal detector72(VOUT_TH) and from the second signal detectors74(VOUTCOMP) to evaluate passage from the step of charging of the inductor22bto the step of supply of the capacitor27/load28, and vice versa. Instead, when a negative half-wave of the input signal VINis detected, the control logic60monitors just the signals generated at output from the third signal detector72′ (VOUT_TH′) and from the fourth signal detectors74′ (VOUTCOMP′) to evaluate passage from the step of charging of the inductor22bto the step of supply of the capacitor27/load28, and vice versa.

The control logic60implements the method for control of the HV transistors30a,30b,31aand31bdescribed previously and illustrated schematically inFIG. 11, by a flowchart.

With reference toFIG. 11(step100), the HV transistors30aand31aare closed. It is considered in the sequel of the description that the LV transistors30band31bwill always be in the closed state (situation ofFIG. 3B).

In this way, the inductor22bis charged via the current IL=IONthat flows through the HV transistors30aand31a.

The value of current IL=IONis monitored (step102) for detecting whether it reaches (or exceeds) the required threshold value ITH. At the same time, the control logic60monitors the time interval TDELAY. In this case, the time t0of start of the time interval TDELAYcorresponds to the instant of closing of the HV transistors30a,31a, according to step100.

In the case where the current ILhas not reached the threshold ITHor the time TDELAYhas not elapsed (output NO from step102), it is necessary to wait for both of these conditions for being satisfied and the control logic60maintain the system20in the states100,102until the condition IL≧ITHis satisfied. Otherwise (output YES from step102), control passes to the next step104.

In step104a check is made to verify whether the input voltage VINhas positive or negative polarity. This operation may be performed by the comparator86, which receives the signal VIN+at input.

As has already been said, a circuit equivalent to what is illustrated inFIG. 8is coupled (in a way not illustrated in the figure) to the HV transistor31a, and used in a similar way for receiving the signal with negative polarity VIN−.

In the case where the input voltage VINhas a positive polarity, control passes to step106(output YES from step104), where the HV transistor30ais opened, thus supplying the capacitor27/load28via the diode36.

In the case where the input voltage VINhas a negative polarity, control passes instead to step108(output NO from step104), where the capacitor27/load28is supplied via the diode38.

From steps106and108control passes to step110, where the control logic60monitors just one between the signals VOUTCOMPand VOUTCOMP′ (from the second current detector74and, respectively, fourth current detector74′, according to the polarity of the input signal) to detect whether the current IOUTassumes a value equal to IOFF. As long as IOUT>IOFF, the control logic60keeps the system20in the step of charging of the capacitor27/supply of the load28. When IOUT≦IOFF, control returns to step100. Steps100-104are carried out, as described with reference toFIGS. 5a-5c, in a time interval equal to at least TDELAYuntil the current in the inductor reaches the threshold ITH, whereas steps106-110are carried out in a time interval equal to TCHARGE.

The control logic60is, for example, a microcontroller, or finite-state machine, configured to drive the HV transistors30aand31ain order to execute the steps of the method ofFIG. 11. In particular, the control logic is integrated in the same device that forms the energy harvesting interface according to the present invention (i.e., it is not an external component).

According to an embodiment alternative to the one illustrated inFIGS. 3A and 3B, the diodes36and38may be replaced by a respective N-channel MOSFET, or by any active component appropriately controlled for implementing the steps described. This embodiment is illustrated inFIG. 12(energy harvesting system20′). These transistors are designated by the reference numbers36′ and38′, respectively. The transistors36′ and38′ are controlled in an active way, by actively driving them in conduction or inhibition. This control is carried out by the control logic60, possibly by interposition of respective driving blocks. More in particular, the control logic60turns on the transistor36′ at positive half-waves of the input voltage VINand as it verifies that the current IONhas reached the value Ipfor getting energy to flow to the capacitor27/load28. Likewise, the control logic60turns on the transistor38′ at negative half-waves of the input voltage VINand at as it verifies that the current IONhas reached a value, in modulus, equal to Ipfor getting energy to flow to the capacitor27/load28.

FIG. 13shows, by a flowchart, a method for control of the HV transistors30a,30b,31a,31b,36′ and38′.

With reference toFIG. 13(step120), the HV transistors30aand31aare closed. The transistors36′ and38′ instead, are opened. It is assumed, in the sequel of the description, that the LV transistors30band31bare always in the closed state. In this way, the inductor22bis charged via the current IL=IONthat flows through the HV transistors30aand31a.

The value of current IL=IONis monitored (step122) for detecting whether it reaches (or exceeds) the threshold value ITHrequired. At the same time, the control logic60monitors the time interval TDELAY. In this case, the time t0of start of the time interval TDELAYcorresponds to the instant of closing of the HV transistors30a,31a, according to step120.

In the case where the current ILhas not reached the threshold ITHor the time TDELAYhas not elapsed (output NO from step122), it is necessary to wait for both of these conditions for being satisfied, and the control logic60keeps the system20in the states120,122until the condition IL≧ITHis satisfied. Otherwise (output YES from step122), control passes to the next step124.

In step124, a check is made to verify whether the input voltage VINhas positive or negative polarity.

In the case where the input voltage VINhas a positive polarity, control passes to step126(output YES from step124), where the HV transistor30ais turned off and the transistor36′ is turned on, thus supplying the capacitor27/load28via the transistor36′.

In the case where the input voltage VINhas a negative polarity, control passes instead to step128(output NO from step124), where the capacitor27/load28is supplied via the transistor38′.

From steps126and128control passes to step130, where the control logic60monitors just one between the signals VOUTCOMPand VOUTCOMP′ (according to the polarity of the input signal) to detect whether the current IOUTassumes a value equal to IOFF. As long as IOUT>IOFF, the control logic60keeps the system20in the step of charging of the capacitor27/supply of the load28. When IOUT≦IOFF, control returns to step120.

FIG. 14shows a vehicle200comprising the energy harvesting system20ofFIGS. 3A, 3Bor the energy harvesting system20′ ofFIG. 12. The vehicle200is, in particular, an automobile. It is evident, however, that the energy harvesting system20,20′ may be used in any vehicle200or in systems or apparatuses different from a vehicle. In particular, the energy harvesting system20,20′ may find application in generic systems in which it is desirable to harvest, store, and use environmental energy, in particular by conversion of mechanical energy into electrical energy.

With reference toFIG. 14, the vehicle200comprises one or more transducers22coupled in a per se known manner to a portion of the vehicle200subject to mechanical stress and/or vibrations, for converting said mechanical stress and/or vibrations into electric current.

The energy harvesting system20,20′ is connected to one or more electrical loads28a, . . . ,28n, for example via interposition of a DC-DC converter. In particular, according to an application of the present invention, the electrical loads28a, . . . ,28ncomprise TPM (tyre-parameter monitoring) sensors250for monitoring tire parameters202. In this case, the TPM sensors250are coupled to an internal portion of the tires202of the vehicle200. Likewise, also the transducers22(for example, of an electromagnetic or piezoelectric type) are coupled to an internal portion of the tires202. The stress of the transducers22while the vehicle200is travelling causes production of an electric current/voltage signal at output from the transducer22by conversion of mechanical energy into electrical energy. The electrical energy thus produced is stored, as described previously, in the storage element27and supplied, via the DC-DC converter that may possibly be present, to the TPM sensors250.

According to one embodiment, the energy harvesting system20,20′, comprising one or more transducers and the TPM sensors250, are glued inside one or more tires202. The impact of the tire202on the ground during motion of the vehicle200enables production of electrical energy.

As an alternative to what is illustrated inFIG. 14, the energy harvesting system20,20′ may be set in any other portion of the vehicle200, and/or used for supplying an electrical load different from, or additional to, the TPM sensors250.

Another possible application of the energy harvesting system20,20′ is generation of electrical energy by exploiting the mechanical energy produced by an individual when he is walking or running. In this case, the energy harvesting system20,20′ is set inside the shoes300of said individual (for example, in the sole) as illustrated schematically inFIG. 15. In systems configured for fitness purposes, where it is of particular interest to count the number of steps, it is useful to recover energy from the vibrations induced by walking or running for being able to supply, without the use of batteries, acceleration sensors and/or RFID transmitters that are able to communicate with cellphones, music-playing devices, or with any other apparatus involved in processing information regarding the steps.

From an examination of the characteristics provided according to the present disclosure the advantages that it affords emerge clearly.

In particular, the parameter K has a highly reproducible value (minimal spread) for increasing the performance, sturdiness, and efficiency of the system20,20′, minimizing the mismatch between the positive polarity and negative polarity of the signal of the transducer and preventing phenomena of reversal of the flow of current from the capacitor27to the input terminals25′,25″ of the rectifier circuit24.

The scavenging efficiency is likewise high even when the amplitude of the signal VTRANSDof the transducer22is lower than the voltage value stored in the capacitor27, thus overcoming a limitation of the diode-bridge rectifier architecture.

Furthermore, since in the case of a transducer22of an electromagnetic type the rectifier24exploits the inductor22bof the transducer22, the scavenging efficiency is high even when the amplitude of the signal of the transducer is low. In this way, the limitation imposed by the diode-bridge rectifiers, which require a voltage of the transducer VTRANSDhigher than 2VTH_D, where VTH_Dis the threshold voltage of the diodes of the rectifier, is overcome.

Using a high-voltage (HV) technology for the capacitor27and for the energy harvesting interface, it is possible to store high voltages, and thus high energy, in the capacitor, consequently increasing the autonomy of operation of the TPM sensors250.

The method described enables implementation of an active control (of the mean value and of the ripple) of the current supplied by the transducer, and enables an optimal impedance matching between the transducer22and the energy harvesting interface24. This ensures a high efficiency ηSCAVof the energy harvesting interface24birrespective of the speed of rotation of the tyres202and of the conditions of storage of the energy in the capacitor27.

Furthermore, as has been said, the value of the interval TDELAYmay be varied according to the particular application in which the rectifier24operates. The rectifier24thus finds use in systems different from the energy harvesting system20,20′, based upon electromagnetic transducers of any type.

In addition, the rectifier circuit24may be used with transducers of some other type, with interposition of an appropriate circuit between the transducer and the rectifier circuit configured to provide an energy accumulator similar to the inductor22b.

Further, the rectifier24and the energy harvesting system20,20′ are of a fully integrated type, and consequently require minimal installation space.

Finally, environmental-energy harvesting is obtained even when the signal of the transducer is lower than the voltage value stored on the output capacitor, which is not possible using a diode-bridge interface of a known type as illustrated inFIG. 1. According to the present invention, the energy harvesting interface24is thus able to harvest energy even when the power supplied by the transducer is very low.

Finally, it is clear that modifications and variations may be made to what has been described and illustrated herein, without thereby departing from the scope of the present invention, as defined in the annexed claims.

In particular, according to one embodiment, the rectifier circuit24may comprise a number of transistors different from what has been described. For instance, the rectifier circuit24may be a half-wave rectifier, comprising just the current detectors72and74or, alternatively, just the current detectors72′ and74′. Use of a half-wave rectifier may be advantageous in the case where the input signal VINis of a known type and comprises only positive (or negative) half-waves. Its use is, however, not recommended (albeit possible) in energy harvesting systems in so far as part of the input signal would be lost, at the expense of the efficiency of the system as a whole.

Furthermore, it is not always necessary for both the conditions t>TDELAYand IL>ITHexpressed with reference to the operating condition ofFIG. 4Afor being satisfied. In particular, for voltage signals generated by transducers22of a known type, the voltage value always reaches peaks such as to enable the threshold ITHfor being exceeded within the time TDELAY. Furthermore, an appropriate choice of TDELAYalways guarantees, for practical purposes, reaching of a minimum acceptable threshold ITH.

In addition, there may be present a plurality of transducers22, indifferently all of the same type or of different types. For instance, the transducer/transducers may be chosen in the group comprising: electrochemical transducers (configured to convert chemical energy into an electrical signal), electromechanical transducers (configured to convert mechanical energy into an electrical signal), electro-acoustic transducers (configured to convert variations of acoustic pressure into an electrical signal), electromagnetic transducers (configured to convert a magnetic field into an electrical signal), photo-electric transducers (configured to convert light energy into an electrical signal), electrostatic transducers, thermoelectric transducers, piezoelectric transducers, thermo-acoustic transducers, thermomagnetic transducers, and thermo-ionic transducers.