Switched current resistor programmable gain array for low-voltage wireless LAN and method using the same

A switched current resistor (SCR) PGA for constant-bandwidth gain control includes an inverting amplifier, a feedback resistor forming a feedback loop between an output side and an input side of the inverting amplifier, and a switched current resistor (SCR) array connected in parallel to the feedback resistor, and configured to tune a gain range between a maximum and a minimum. The SCR array includes a plurality of switched resistors, each comprising a switch in series with a resistor. When the plurality of switched resistors are switched by a gain-control logic, a plurality of switched current sources and a plurality of grounded resistors are switched correspondingly to deliver a transient current, an equivalent of which flows through the plurality of grounded resistors out from the input side of the inverting amplifier, leading to a feedback factor of the PGA being constant.

BACKGROUND OF INVENTION

1. Field of the Invention

The present invention relates generally to a switched-current resistor (SCR) programmable gain array (PGA) targeted for wireless local area network (WLAN) applications. More specifically, embodiments of the present invention relate to an SCR PGA, where an SCR array may be employed in parallel with a feedback resistor to achieve constant bandwidth transient-free gain control.

2. Background Art

The rapid evolution of CMOS technology has accelerated the integration of mixed-signal systems, such as the wireless transceiver on a single chip. In the case of a zero intermediate-frequency (IF) or low IF receiver architecture targeted toward IEEE 802.11 a/b/g WLAN applications, signal levels arriving at the baseband are scaled to around a 0 dBm range for analog-to-digital conversion. With technology scaling, capacitive coupling in a zero IF receiver would increase enough to contribute to the de-offset problem. The dc-offset problem may be mitigated through the employment of a low-IF receiver, which also allows for increased integration. However, appropriate design of constituent circuits is vital under low voltage (LV) constraints.

FIG. 1shows the block diagram of a low-IF receiver100in a dual-receive conversion configuration. The receiver100may include a Radio Frequency (RF) input105, a Low Noise Amplifier (LNA)110followed by a mixer115with a Local Oscillator Reference Frequency (LORF) in the RF range. Due to the difference in the “in-phase” I and the “quadrature” Q signal, mixers120and125may have different IF reference frequencies (LOIF(I) and LOIF(Q)). Baseband channel selection filters130and135, and the PGAs140and145, complete the typical low IF receiver block diagram. PGAs are usually standard inverting amplifiers employing a switched-resistor bank for gain control. Terminals150and155constitute the output. A single synthesizer may synthesize both the IF and RF Local Oscillator (LO) frequencies.

The dynamic-range requirement from the antenna (input terminal105) to the baseband may approximately equal 0 to 80 dB, with the majority of the gain achieved in the baseband. If the radio front-end offers a 0 to 30 dB range, the baseband channel selection filters130and135, along with the PGAs140and145have to offer another 0 to 50 dB of controllable gain. Although cascading multiple PGAs may lead to such high gain ranges, excess bandwidths are required of the PGAs, sometimes equal to ten times the bandwidth of the channel-selection filters, to ensure stable selectivity against gain.

Technology scaling within submicron scales, when accompanied with a standard power supply, may not necessitate a significant change in the design of analog blocks.FIG. 2(a) shows a standard inverting amplifier250employing a switched-resistor bank Rfb220for gain control, which serves as a PGA200. However, in tune with the burgeoning sub-volt nanoscale processes, the classic switched-resistor PGA200shown inFIG. 2(a) may be rendered ineffectual because of insufficient LV headroom.

One way to render an inverting amplifier250suitable for a minimum drain supply voltage (VDD) is to use a level shifter. As shown inFIG. 2(a), an extra input common-mode feedback (I-CMFB)270may explicitly bias the virtual ground Vvg+and Vvg−to a common-mode voltage Vcm,in, which is the minimum saturation voltage VDSsat(typically 0.1 V) necessary for the transistor to act as a current sink Ib260. The lowest possible VDDmay be estimated by taking into account the voltage requirement into the input stage252(see the p-MOS differential pair252inFIG. 2(b)), and may be expressed as:
VDD>|VT,p+|2VSDsat+2VDSsat,  (1)
where VT,pis the p-channel transistor threshold voltage, and VSDsatis the source-drain saturation voltage.FIG. 2(b) shows the input252and output254stages of the inverting amplifier250of the PGA200.

For a VT,pof −0.65 V, the lowest possible VDDis approximately 1V. The output254stage of the inverting amplifier250may be a typical class-A amplifier254(seeFIG. 2(b)), which delivers a high swing output by locking the output-common mode voltage (Vcm,out) to VDD/2. SS inFIG. 2(b) refers to signal swing. However, a large output swing may require an output common-mode feedback (O-CMFB)290. For example, a resistive detector may be required to extract Vcm,outfor conversion into a current signal for the back-end current amplifier. Gain tuning may be accomplished by varying either the feed-forward resistor Rff215or the feedback resistor Rfb220via a switched-resistor bank comprising n-MOS transistor switches and associated resistors. Resistor215may also be included in the non-inverting terminal and resistor220in the feedback loop thereof. Therefore, the resistors in the non-inverting terminal and the feedback loop thereof are intentionally left unlabeled. The switches may be placed at Vvg+and Vvg−to gain enough overdrive voltage (VOD) of roughly 0.3V. VODmay be expressed as:
VOD=VDD−VT,n−VDS,sat,  (2)
where VT,nis the n-channel transistor threshold voltage.

Additionally, two distinct reference voltages, Vref,in272of 0.1 V and Vref,out285of 0.5 V may be required (seeFIG. 2(a)). Resistors255and275refer to Rcm,inand Rcm,outrespectively, and resistors265and280appropriately refer to Rcm,in/2 and Rcm,out/2 respectively. Terminals205and210constitute the input (Vin+and Vin−) of the PGA200, and terminals292and294constitute the output (Vout+and Vout−). Amplifiers267and268are constituent elements of I-CMFB270and O-CMFB290respectively. Vref,out285should be buffered in order to be able to drive the O-CMFB290that drains static current.

SUMMARY OF INVENTION

According to one aspect of one or more embodiments of the present invention, an SCR PGA for constant bandwidth gain control includes an inverting amplifier, a feedback resistor forming a feedback loop between an output side and an input side of the inverting amplifier, and an SCR array connected in parallel to the feedback resistor, and configured to tune a gain range between a maximum and a minimum. The SCR array includes a plurality of switched resistors, each comprising a switch in series with a resistor. A constituent switched resistor of the plurality of switched resistors is connected to another switched resistor in parallel. When the plurality of switched resistors are switched by a gain-control logic, a plurality of switched current sources and a plurality of grounded resistors are switched correspondingly such that the plurality of switched current sources deliver a transient current, an equivalent of which flows through the plurality of grounded resistors out from the input side of the inverting amplifier, leading to a feedback factor of the PGA being constant.

According to one aspect of one or more embodiments of the present invention, a receiver for use in wireless local area networks includes a low noise amplifier, a first mixer with a first local oscillator reference frequency in an RF range, a second mixer with a second local oscillator reference frequency in an IF range, a channel selection filter, and an SCR PGA. The SCR PGA includes an inverting amplifier, a feedback resistor forming a feedback loop between an output side and an input side of the inverting amplifier, and an SCR array connected in parallel to the feedback resistor and configured to tune a gain range between a maximum and a minimum. The SCR array includes a plurality of switched resistors, each comprising a switch in series with a resistor. A constituent switched resistor of the plurality of switched resistors is connected to another switched resistor in parallel. When the plurality of switched resistors are switched by a gain-control logic, a plurality of switched current sources and a plurality of grounded resistors are switched correspondingly such that the plurality of switched current sources deliver a transient current, an equivalent of which flows through the plurality of grounded resistors out from the input side of the inverting amplifier, leading to a feedback factor of the PGA being constant.

According to one aspect of one or more embodiments of the present invention, a method for realizing a constant bandwidth transient-free gain control in a PGA includes connecting a feedback resistor across an input side and an output side of the inverting amplifier, connecting an SCR array in parallel to the feedback resistor, the SCR array being configured to tune a gain range between a maximum and a minimum and including a plurality of switched resistors, each comprising a switch in series with a resistor, and switching the plurality of switched resistors by a gain-control logic such that a plurality of switched current sources and a plurality of grounded resistors are switched correspondingly to deliver a transient current, an equivalent of which flows through the plurality of grounded resistors out from the input side of the inverting amplifier, leading to a feedback factor of the PGA being constant. A constituent switch resistor of the plurality of switched resistors is connected to another switched resistor in parallel.

DETAILED DESCRIPTION

Although the aforereferenced PGA structure ofFIG. 2may be LV compliant, gain tuning through either Rff215or Rfb220may vary the feedback factor independently of VDD, resulting in a gain-dependent output bandwidth. Secondly, as the input impedance of the PGA is mainly governed by Rff215, varying Rff215without adopting a preceding buffer of high impedance may draw a gain-dependent current from the previous stage. The previous stage may be a mixer or a passive filter in a receiver. In order to avoid high impedance buffers and mitigate the effects of loading in a multistage PGA, Rfb220may be tuned instead. However, tuning of Rfb220may induce another gain-dependent dc current Ifb,dcin the feedback loop due to the unequal common-mode levels of Vcm,outand Vcm,in. This gain-dependent dc current may be expressed as:

Ifb,dc=(Vcm,out-Vcm,inRfb)(3)
These unequal common-model levels and the associated gain-dependent dc current may entail a long settling time to re-stabilize the input-output (I/O) CMFBs and the opamp at a new quiescent operating point.

In general, embodiments of the present invention describe an SCR PGA that provides for gain-independent output bandwidths, sinks out the unwanted gain-dependent dc current, and dispels the need for buffers. In one or more embodiments, such an SCR PGA may be operational underneath a very low-voltage (LV) VDDof 1V or less. For simplicity sake, a VDDof 1V is assumed in the detailed description below. One of ordinary skill in the art will recognize that other VDDvalues may be used in accordance with one or more embodiments of the present invention.

FIG. 3shows an SCR PGA300in accordance with one or more embodiments of the invention Analogous toFIG. 2(a), amplifier350is the inverting amplifier, resistor Rff315is the feed forward resistor, and resistor Rfb320is the feedback resistor. In one or more embodiments, as resistor315may also be included in the non-inverting terminal of amplifier350, the resistor in the non-inverting terminal is intentionally left unlabeled. Terminals305and310constitute the input (Vin), CMFB circuits370and390are the I-CMFB and O-CMFB respectively, and terminals392and394constitute the output (Vout). Current sink360is the current sink Ib, resistors355and375refer to Rcm,inand Rcm,outrespectively, and resistors365and380appropriately refer to Rcm,inand Rcm,out/2 respectively. Amplifiers367and368are constituent elements of I-CMFB370and O-CMFB390respectively.

In one or more embodiments, a set of switched resistors322,1to322,n (i.e. Rfb,1. . . Rfb,n) may be added in parallel with Rfb320to achieve a tunable gain range between a maximum of

-RfbRff
and a minimum of

In one or more embodiments, equalizing the last two terms of Equation (4) over process, voltage, and temperature (PVT) variation is not complicated because Vcm,outand Vcm,in(seeFIG. 2(b)) are mirrors of Vref,out385and Vref,in372respectively. In one or more embodiments, Vref,out385and Vref,in372may be generated underneath one master VDD(for e.g., Vref,out=VDD/2, and Vref,in=VDD/10), while Rfb,n322,n and Rx,n324,n may be synthesized using the same unit resistor Ru(for e.g., Rfb,n=αnRu=4Rx,n, for n=1, 2, 3 . . . . Here αnis a positive integer representing a resistive ratio). Any PVT variation may result in a common-mode disturbance in the last two terms of Equation (4). In one or more embodiments, matching the first term of Equation (4) to the rest may involve an extra signal conversion such that the newly generated switched current sources (Ilfb,1. . . Ilfb,n) may track the PVT variations of322,1. . .322,n (Rfb,1. . . Rfb,n),324,1. . .324,n (Rx,1. . . Rx,n) Vref,out385, and Vref,in372. In one or more embodiments, the SCR bank may be driven by two potential levels, VDDand VSS.

FIG. 4shows a LV resistor-current (R-to-I) conversion circuit400for generating Vref,out, Vref,inand Ilfb,1. . . Ilfb,n, as discussed above, in accordance with one or more embodiments of the invention. Such a circuit may approach the ideal Ifb, 1. . . Ifb, n, as governed by Equation (4). In one or more embodiments, the R-to-I conversion circuit400may include a reference-voltage generation section460, an R-to-I conversion section470, and a switched current source section480. In one or more embodiments, an error amplifier Aerror425in a feedback loop may track the absolute value of P3420underneath a fixed voltage Vz. Therefore, the corresponding reference current Ifb,refis proportional to

1R3.
In one embodiment, Vzmay be a mirror of Vxthat may be set to 0.1 V (VDD/10), thereby enabling Aerror425to be realized via a p-channel differential pair. Resistors405,410,415are resistors R1, R2, R4respectively, and transistor430is a dummy transistor Md. Ifb,refmay be mirrored afterward to the switched current sources Ilfb,1. . . Ilfb,nthrough transistors M1435to Mb,1, . . . Mb,n, which may feature the same ratios of Rfb,1to Rfb,1. . . Rfb,n. Ilfb,nmay be related to the normalized Rfb,1through example Equation (5) as:

Making Ilfb,nproportional to just

VzRfb,n
may be done by substituting R3420with

Rfb,14.
This may equalize the numerator of Equation (5) to the second term of Equation (4), (i.e., 4Vz=Vcm,out−Vcm,in), resulting in example Equation (6)

Substituting Equation (6) back into the first term of Equation (4), and replacing Rfb,nand Rx,nin accordance with αnRu=Rfb,n=4Rx,nmay lead to example Equation (7) as:

In one or more embodiments, as Vz, Vcm,out, and Vcm,in(seeFIG. 2(b) andFIG. 4)are mirrors of Vx=VDD/10, Vref,out=VDD/2, and Vref,in =VDD/10, the error voltage (Vδ) associated with VDD, and the error resistance (Rδ) associated with Rumay have no effect on the balancing of Equation (7). This may be expressed as example Equation (8):

In one or more embodiments, as seen from example Equation (8), the R-to-I conversion circuit may yield an overall PVT-insensitive operation, whose employment may further the static and dynamic performances of the SCR PGA.

In one or more embodiments, the current mirror M1to Mb,1. . . Mb,nmay raise the precision by adding

R4=R3⁡(VD-Vz)Vz,
thereby level shifting the drain voltage VDof M1to match that of Mb,1. . . Mb,n.

In one or more embodiments, the overall resistor matching, and the ground-noise rejection of Aerror425and Aref440may be enhanced by selecting, for example,

R1=R29=R3=R44=R5=R64,
thereby resulting in a resistor spread of just 9. Here, Aref440may form a non-inverting amplifier for buffering Vref,out. InFIG. 4, resistors445and450refer to resistors R5, one side of which is driven at VSS, and R6respectively.

In one or more embodiments, Ilfb,1. . . Ilfb,nmay be switched through transistors Ms,1. . . Ms,nrather than Mb,1. . . Mb,nsuch that Ms,1. . . Ms,nmay attain the maximum overdrive voltage, leading to reduced device sizes and lower charge injection values. In one embodiment, as only the current paths are opened, the gate-to-source capacitance of Mb,1. . . Mb,nmay be kept charged for a faster turn-on time.

In one or more embodiments, connecting Mb,1. . . Mb,nto VDDmay prevent charge injection of Ms,1. . . Ms,nfrom coupling to the gates thereof through a body-to-gate parasitic capacitance thereof, thereby theoretically yielding 200% to 300% shorter transients depending on the gain step.

In one or more embodiments, the feedback factor βPGAmay be expressed as example Equation (9):

In one or more embodiments, βPGAmay be stabilized when the two conditions ((10) and (11)) specified below are satisfied concurrently.

As conditions (10) and (11) depend on relative ratio rather than absolute values, βPGAmay be robustly stabilized against gain over PVT. Advantages of a constant βPGAmay include unvarying settling time and constant stopband rejection.

In one or more embodiments, the constancy of PGA may practically depend on the ratio of resistances of Rcm,into Rffof and Rx,1. . . Rx,n. Even with a large Rcm,inin comparison to Rff∥Rx,1. . . ∥Rx,n, βPGAmay only vary in very small quantities, leading to only a small bandwidth variation. In one or more embodiments, identical PGAs may be cascaded to attain required gain range. Although identical cascaded PGAs reduce bandwidth, which is multiplied by a factor of

21N-1
(N being the number of cascaded stages), a large βPGAmay result in a net bandwidth enlargement, with an obvious increase in power due to increase in the number of PGAs.

It will be obvious to one of ordinary skill in the art that the abovementioned SCR circuit details, transistor types and choices, R-to-I conversion circuit elements, R-to-I conversion choice parameters, input and output sections of the SCR PGA all are explained for clarity purposes and any variations in them would not depart from the scope of the invention. Modifications in the aforementioned are well within the scope of the invention.

In one or more embodiments, dc-offset cancellation may be incorporated for a fully differential circuit implementation, whereby the even-harmonic distortion may be suppressed effectively such that only the odd harmonics are dominant. In one embodiment, an example determination of the third-harmonic distortion (HD3) of a highly linear resistor in series with a nonlinear n-MOS switch would require an assumption of reception of the sinusoidal signal by the terminal in the resistor side, with the terminal in the switch side being grounded. HD3 may then be expressed in the form of example Equation (12) as:

In one or more embodiments, the squared output thermal noise of the PGA may be lowered by keeping the resistor spread small and increasing the level of Vcm,in.

As discussed above, one or more embodiments of the SCR PGA offers advantages, not limited to a stable feedback factor, transient-free gain control, and elimination of loading effects in a multi-stage PGA. In one or more embodiments, stable selectivity against gain is ensured as the bandwidth requirement of the PGA may be relaxed. In one such embodiment, the bandwidth requirement of the PGA may be relaxed to less than 20 MHz. In one or more embodiments, reduction of the settling times in gain change may be achieved, and one or more embodiments may offer enhanced stopband rejection.

While the invention has been described with respect to an exemplary embodiment of an SCR PGA for achieving a constant bandwidth transient-free gain control, those skilled in the art, having benefit of this disclosure, will appreciate that other embodiments can be devised which do not depart from the scope of the invention as disclosed herein. Accordingly, the scope of the invention should be limited only by the attached claims.