Semiconductor device free of gate spacer stress and method of manufacturing the same

A semiconductor device that prevents gate spacer stress and physical and chemical damages on a silicide region, and a method of manufacturing the same, according to an exemplary embodiment of the present invention, includes a substrate, isolation regions formed in the substrate, a gate pattern formed between the isolation regions on the substrate, an L-type spacer adjacent to the sidewall of the gate pattern and extended to the surface of the substrate, source/drain silicide regions formed on the substrate between the end of the L-type spacer extended to the surface of the substrate and the isolation regions, via plugs electrically connected with the source/drain silicide regions, an interlayer dielectric layer which is adjacent to the L-type spacer and which fills the space between the via plugs layer formed on the gate pattern and the substrate, and a signal-transfer line formed on the interlayer dielectric layer.

CROSS REFERENCE TO RELATED FOREIGN APPLICATION

This application claims priority from Korean Patent Application No. 10-2006-0084852 filed on Sep. 4, 2006, in the Korean Intellectual Property Office, the contents of which are herein incorporated by reference in their entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present disclosure is directed to a semiconductor device and method of manufacturing the same. More particularly, the present disclosure is directed to a semiconductor device free from the stress of gate spacers and physical and chemical damage on silicide regions and method of manufacturing the same.

2. Description of the Related Art

As the density of semiconductor devices increases, it has becoming increasingly difficult to use conductive polycrystalline silicon to secure enough conductivity for semiconductor devices to operate in a stable condition. As a result, conductive parts, previously composed of conductive polycrystalline silicon, such as gate electrodes, source/drain regions, contacts or via plugs, and signal transfer lines, have been gradually replaced by metallic materials. However, it is challenging to make metal patterns as compared to polycrystalline silicon. Also, because a semiconductor substrate is not metal, if metal contacts the semiconductor substrate, voids are formed in the metal. This not only makes the structure unstable, but also increases resistance such that the structure cannot be used in a semiconductor device. Therefore, the pattern is not formed of pure metal, but of silicide and metal. After the pattern is formed of silicon, a silicide layer is formed by combining a silicon pattern with metal. However, the silicide layer can be damaged where the characteristics of the silicide layer deteriorate and the shape of the silicide layer changes. Especially, the damage and the transformation of the silicide pattern of the source/drain region have an impact on the deterioration of characteristics as compared to the damage and the transformation of other parts.

Also, a gate spacer is generally formed from the transistors (or gates) of a semiconductor device. A gate spacer typically is formed of materials having a high degree of density and solidity. Due to the increasing integration of semiconductor devices and the small geometry of patterns, the stress generated by a gate spacer is becoming a concern. The volume of a semiconductor device increases or decreases in a repeated fashion as it absorbs or generates heat during manufacturing. As a result, various types of stresses are generated depending on the differences of heat expansion coefficients of elements forming the semiconductor device. These stresses deteriorate the characteristics of the source/drain and channel region of the semiconductor devices. Such stresses have been considered unimportant since they had an insignificant impact on the characteristics of a semiconductor device, but the impact of theses stresses has become more significant. Consequently, there is a need for research and development avoiding or relieving the stress caused by a gate spacer. Research has been conducted on removing the gate spacer. If the gate spacer is removed, the silicide region, which is comparatively weak, can cause trouble.

SUMMARY OF THE INVENTION

Embodiments of the present invention provide a semiconductor device which can prevent gate spacer stress, and physical and chemical damage to a silicide region.

Embodiments of the present invention also provide a method of manufacturing a semiconductor device which can prevent gate spacer stress, and physical and chemical damage to a silicide region.

Embodiments of the present invention should not be construed as being limited to the above object, and the above stated objects as well as other objects and features of embodiments of the present invention will become clear to those skilled in the art upon review of the following description.

According to an aspect of the present invention, there is provided a semiconductor device including a substrate, isolation regions formed in the substrate, a gate pattern formed between the isolation regions on the substrate, an L-type spacer adjacent to the sidewall of the gate pattern and having an end extended to the surface of the substrate, source/drain silicide regions formed on the substrate between the end of the L-type spacer extended to the surface of the substrate and the isolation regions, via plugs formed on the gate pattern and the substrate and electrically connected with the source/drain silicide regions, an interlayer dielectric layer which is adjacent to the L-type spacer and which fills the space between the via plugs layer, and a signal transfer line formed on the interlayer dielectric layer.

According to another aspect of the present invention, there is provided a method of fabricating a semiconductor device including forming isolation regions in a substrate, forming a gate pattern on the substrate, forming an L-type spacer layer which covers the upper region and the sidewall of the gate pattern, forming a gate spacer layer on the L-type spacer layer, forming an L-type spacer on the sidewall of the gate pattern and extended to the substrate and a gate spacer by patterning the L-type spacer layer and the gate spacer layer, and simultaneously exposing the surface of the substrate between the gate spacer and the isolation regions, forming a source/drain silicide region on the exposed substrate, forming a sacrificial metal layer on the source/drain silicide region, removing the gate spacer, removing the sacrificial metal layer, forming an interlayer dielectric layer which covers the gate pattern and the source/drain silicide region, and forming via plugs electrically connected with the source/drain silicide region by vertically penetrating the interlayer dielectric layer.

According to another aspect of the present invention, there is provided a method of fabricating a semiconductor device including forming isolation regions in a substrate, forming a gate pattern on the substrate, forming an L-type spacer layer which covers the upper region and the sidewall of the gate pattern, forming a gate spacer layer on the L-type spacer layer, forming an L-type spacer on the sidewall of the gate pattern and extended to the substrate and a gate spacer by patterning the L-type spacer layer and the gate spacer layer, and exposing the surface of the substrate corresponding to between the gate spacer and the isolation regions, forming a source/drain silicide region on the exposed substrate, forming a source/drain pad metal layer on the source/drain silicide region, removing the gate spacer, forming an interlayer dielectric layer which covers the gate pattern and the source/drain silicide region, and forming via plugs electrically connected with the source/drain silicide region by vertically penetrating the interlayer dielectric layer.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Hereinafter, a structure of the semiconductor device and a method of manufacturing the same will be described with reference to drawings.

FIG. 1A through 1Eare vertical views illustrating semiconductor devices according to various exemplary embodiments of the present invention.

Referring toFIG. 1A, a semiconductor device according to an exemplary embodiment of the present invention includes isolation regions210formed on a substrate205, a gate pattern245formed on the substrate205between the isolation regions210, source/drain silicide regions260aformed on the substrate205between the gate pattern245and the isolation regions210, a gate silicide region260bformed on the gate pattern245, via plugs290electrically connected with the gate silicide region260band the source/drain regions260a, an interlayer dielectric layer280which covers the gate pattern245, source/drain silicide region260a, the gate silicide region260b, and the isolation region210, and fills the space between the via plugs290, and signal transfer lines300formed on the interlayer dielectric layer280.

The gate pattern245comprises a gate-insulating layer220, a gate electrode230, and an L-type spacer240. The gate pattern245further comprises the gate silicide region260b.

The via plugs290comprise liners295at the interface between the via plugs290and the interlayer dielectric layer280.

The source/drain silicide regions260acan have the same height as the surface of the substrate205.

The gate silicide region260bcan protrude to expose the side of the gate pattern245. That is, the source/drain silicide regions260acan be formed not lower than the surface of the substrate205, and the gate silicide region260bcan be formed higher than the top of the L-type spacer240.

Source/drain regions215can be formed of impurities implanted at one side of the source/drain silicide regions260aand inside of the substrate205under the L-type spacers240.

A halo ion implantation region217can be formed on the one side of the source/drain regions215and the inside of the substrate205under the L-type spacer240or the gate-insulating layer220.

For example, a silicon substrate, a silicon-germanium (SiGe) substrate, a compound semiconductor substrate, a SOI (silicon on insulator) substrate, or SOS (silicon on sapphire) substrate can be used as the substrate205. In case of a silicon germanium substrate, the substrate can be formed by a germanium implantation or a chemical combinational growth of germanium on an activation area between the isolation areas210, and near the surface of the silicon substrate. Alternatively, only the source/drain region215can be a SiGe region. If only the source/drain region215is the SiGe region, the SiGe region can be formed after the gate pattern245is formed. The SiGe region has a small distance between atoms, so the channel characteristics can be stabilized.

The isolation regions210, for example, can be shallow trench isolation (STI) regions. The forming method of the isolation region210is well known, and the size and the shape of the isolation regions210is adjustable according to the semiconductor device, so it is not be described in detail.

The source/drain regions215are formed on the substrate, which the L-type spacer240is extended to the surface of. One side of the source/drain region215can be formed by aligning the part of the L-type spacer210formed on the side of the gate pattern245. In an exemplary embodiment of the present invention, the source/drain region215can include the source/drain silicide region260a. That is, after the source/drain region215is formed, part of the source/drain region215can become a silicide, thereby forming the source/drain silicide region260a. Therefore, the source/drain region215can be extended or formed under the source/drain silicide region260a. It is not illustrated in this drawing in order to avoid complicating the drawing.

The halo ion implantation region217can be adjacent to one side of the source/drain region, and formed under the vertex of the L-type spacer240. The halo ion implantation region217is the region in which opposite polarity ions of the source/drain region215are implanted.

The gate-insulating layer220of the gate pattern245insulates the substrate205from the gate electrode230. For example, the gate-insulating layer can be silicon oxide, an insulating silicon compound such as silicon nitride or silicon oxynitride, an insulating compound including aluminum oxide, aluminum oxynitride, or hafnium oxide, or any other inorganic insulating material. In an exemplary embodiment of the present invention, silicon oxide is used.

The gate electrode230of the gate pattern245is separated form the substrate205by the gate-insulating layer220. The gate electrode230can be a conductive material such as silicon, conductive compound, metal, or metal silicide. The gate electrode230can be a multilayered structure. For example, the gate electrode230can be formed of two layers by stacking a silicon layer and a silicide layer, or three or the more layers formed by stacking a metal layer on the two layers. In an exemplary embodiment of the present invention, the gate electrode230is a single layer in order to aid understanding the present invention. Therefore, the present invention is not restricted by the single layer, but includes the various multi layers.

The L-type spacer240of the gale pattern245is formed by wrapping a side of the gate-insulating layer220and the gate electrode230. The L-type spacer240is in direct contact with the interlayer dielectric layer280. The L-type spacer240may have a uniform thickness. That is, an insulating layer, which is conventionally known as a “gate spacer” is different from the L-type spacer240. The conventional “gate spacer” has a thin thickness on the upper side of the gate electrode, that is, a distant region from the surface of the substrate, and has a thick thickness on the lower side of the gate electrode, that is a near region to the surface of the substrate. (See reference number250ofFIGS. 2D through 2F, below) But, the L-type spacer240of this exemplary embodiment has uniform thickness independent of the distance from the upper and lower regions of the gate electrode230and the surface of the substrate205, as illustrated inFIG. 1A.

Also, the L-type spacer240can define the source/drain silicide region260aon the substrate205. As illustrated inFIG. 1A, the end of the L-type spacer240can define the end of the source/drain silicide region260a. Also, the top of the L-type spacer240wrapping the gate electrode230can define the bottom of the gate silicide region260b.

The L-type spacer240can be formed of a double layer. For example, two or more silicon oxide, silicon nitride, silicon oxynitride layers can be stacked to form the L-type spacer240. Specifically, the L-type spacer240can be formed of silicon oxide directly on the gate pattern245, or the L-type spacer240, which is not directly in contact with the gate pattern245, can be formed of silicon nitride. Also, the L-type spacer240can be formed by stacking same material. For example, it can be formed by stacking multiple layers of nitride having different formation combinations. Specifically, various oxides can be stacked such as an oxide formed by low temperature oxidation, high temperature oxidation, plasma method, and others.

The source/drain silicide regions260acan be formed in the substrate205. In an exemplary embodiment of the present invention, the source/drain silicide regions260aare formed of nickel silicide, and the surface heights of the source/drain silicide regions260aare same as the surface height of the substrate205. In other words, the surface height of the source/drain silicide regions260ais not lower than the surface height of the substrate205. According to these exemplary embodiments of the present invention, because the source/drain silicide regions260aare not attacked physically or chemically with a gate spacer removing process, the surface height of the source/drain regions260acannot be formed lower than the surface height of the substrate205. Also, the source/drain silicide regions260acan be formed at a depth of the order of 100 Å in the direction of the inside of the substrate205. For example, the depth of the source/drain regions260acan be about 200 Å to about 500 Å.

The gate silicide region260bcan be formed on the gate electrode230, and the lowermost part of the gate silicide region260bis not higher than the top of the L-type spacer240. The gate silicide region260bcan be formed of nickel silicide. The source/drain silicide regions260aand the gate silicide region260bcan be formed by electroless plating. A detailed description of electroless plating will be provided in the method of manufacturing the semiconductor device according to various exemplary embodiments of the present invention.

An etch stopper (not shown) can be formed on the L-type spacer240. The etch stopper can stop an etch process on the surface of the silicide regions260a,260bwhile a via hole is formed in a following process. For example, the etch stopper can be formed of silicon nitride. The etch stopper is not illustrated inFIG. 1Ain order to aid understanding the present invention.

The interlayer dielectric layer280can be formed of silicon oxide. For example, silicon oxide formed by high density plasma method can be used. The quality of the silicon oxide formed by high density plasma method is excellent and solid, and its filling quality is good, so the conformal interlayer dielectric layer280can be formed. Also, the interlayer dielectric layer280can be formed of a multilayered structure. Same series materials such as silicon oxide formed by different forming methods can be used. Various characteristics can be made to differ by the different forming methods in spite of the same series material. For example, a silicon oxide layer having a good filling characteristic can be formed at the lower region, and a silicon oxide layer having an excellent dielectric characteristic can be formed at the upper region. Alternatively, a silicon oxide layer having an excellent dielectric characteristic can be formed in the lower region, and a solid silicon oxide layer can be formed in the upper region. For example, a TEOS layer can be formed at the lower region, and a HDP oxide layer can be formed at the upper region.

The liners295prevent via plugs290from having direct contact with the interlayer dielectric layer280, and can improve adhesion. If via plugs290contact with the interlayer dielectric layer280directly, impurities or various ions can migrate. That is, diffusion can occur. The liners295can prevent the diffusion. Also, if the adhesion between the via plugs290and the interlayer dielectric layer280is not good, the liners295can improve the adhesion. For example, the liners295can be formed of Ti/TiN less than about 200 Å thick in an exemplary embodiment, but other embodiments of the invention are not restricted thereto. Also, inorganic material or dielectric material such as silicon nitride can be used as the liners295. As illustrated inFIG. 1A, the liners295can be formed between the via plugs290and the interlayer dielectric layer280, and between the via plugs and the silicide regions260a,260b.

The signal transfer lines300can be formed of metal such as tungsten or aluminum. Each of the signal transfer lines300can be electrically connected with the via plug290. Also, a material layer similar to the liners295can be formed exterior to the signal transfer lines300. That is, the material layer can be formed which prevents atoms from migrating and which improves adhesion between the signal transfer line300and another layer.

Referring toFIG. 1B, a semiconductor device according to another exemplary embodiment of the present invention includes via plugs290extending under a lower region of a surface of silicide regions260a,260bto electrically connect to silicide regions260a,260b, as compared with the exemplary embodiment of the present invention illustrated inFIG. 1A. In other words, a part of the silicide regions260a,260bare recessed, and the recessed surface of the silicide regions260a,260bcontact the via plugs290. Therefore, contact size can be increased. When the silicide regions260a,260bare recessed and in contact with the via plugs290, not only the bottom of the via plugs290, but also the part of the side of the via plugs290can contact the silicide regions260a,260b. That is, the contact resistance between the via plugs290and the silicide regions260a,260bcan be decreased. Also, liners295can be formed between the via plugs290and the silicide regions260a,260b. The height of the silicide regions260a,260bsurface, exempting the contact of the via plugs290and the silicide regions260aand260b, is maintained.

Referring toFIG. 1C, a semiconductor device according to another exemplary embodiment of the present invention includes via plugs290electrically connected an elevated pad metal layers270a,270bon a silicide regions260a,260bas compared with the exemplary embodiment of the present invention illustrated inFIG. 1A. The elevated pad metal layers270a,270bon the silicide regions260a,260bcan be referred to as a sacrificial metal layer. The pad metal layers270a,270bon the silicide regions260a,260bcan decrease the vertical length of the via plugs290, therefore an aspect ratio of a via hole or the via plugs290can be decreased. Therefore, the pattern of the semiconductor device can be easily formed. If the pad metal layers270a,270bare formed, the vertical length of the via plugs290is decreased. It has the same effect as enlargement of the cross section of the via plugs290. That is, the resistance of the via plugs290decreases. Therefore, the characteristics of the semiconductor device can be improved.

The pad metal layers270a,270binclude a source/drain pad metal layers270aand the gate pad metal layers270bin an exemplary embodiment. But, the source/drain pad metal layers270aand the gate pad metal layers270bare formed independently each other. For example, the source/drain pad metal layers270acan be formed, but the gate pad metal layer270bcannot be formed. Because the surface of the source/drain silicide regions260acan affect the semiconductor device more than the gate silicide region260b, the gate pad metal layer270bcannot be formed on the gate silicide region260b. The pad metal layers270a,270bcan be formed of metals including but not limited to Pt, Pd, Ti, Ta, V, Ir, Ru, W, Co, Ni, Al, or a metal compound with a thickness in the range of about 200 Å to about 500 Å.

Referring toFIG. 1D, a semiconductor device according to another exemplary embodiment of the present invention includes via plugs290formed on a recessed surface of an elevated pad metal layer270and electrically connected with the silicide regions260a,260b. Because a contact size of the via plugs290and the pad metal layers270a,270belevated on the silicide regions260a,260bcan be increased, the contact resistance between the via plugs290and the silicide regions260a,260bcan be decreased. Liners295can be formed between the via plugs290and the pad metal layers270aand270b.

Referring toFIG. 1E, a semiconductor device according to another exemplary embodiment of the present invention includes an upper interlayer dielectric layer285having a greater hardness than an interlayer dielectric layer280between the interlayer dielectric layer280and a signal transfer line300. If the interlayer dielectric layer280is silicon oxide, the upper interlayer dielectric layer285having a greater hardness than silicon oxide, such as silicon nitride or silicon oxynitride, can be formed on the interlayer dielectric layer280. The upper interlayer dielectric layer285can fix interlayer dielectric layer280, can perform as an etch stop layer or chemical mechanical polishing (CMP) etch stopper in a subsequent process, and can perform as a barrier layer which prevents the migration of impurities between the each layer. In an exemplary embodiment, via holes290can be formed on the interlayer dielectric layer280by dry etching after a pattern mask (not shown) is applied to form via plugs290. The upper interlayer dielectric layer285, for example, can be formed of silicon nitride, silicon oxynitride, silicon oxide formed by another method with the interlayer dielectric layer280in a shape of a single layer or multi-layered structure. For example, the upper interlayer dielectric layer285can be formed of double layer of silicon oxide and silicon oxynitride or another combination. Also, the upper interlayer dielectric layer285can be formed between the interlayer dielectric layer280and a signal transfer line300.

The semiconductor device illustrated inFIG. 1Eincludes the exemplary embodiment illustrated inFIG. 1D. The various exemplary embodiments of the present invention are not exclusive, but can be combined each other. That is, an exemplary embodiment can be freely selected and combined to perform this invention.

Exemplary embodiments of the present invention include only the L-type spacer240on the sidewall of the gate pattern245as a gate spacer, and the conventional gate spacer is excluded.

A conventional gate spacer typically includes a gate spacer formed on the side wall of the gate pattern245, a thin vertical dielectric pattern on the upper, more distant region of the gate electrode230, and a thick pattern on the lower, nearer region of the gate electrode230(see reference number250ofFIGS. 2D through 2F). In general, the gate spacer is formed with a dense dielectric material in order to have a high selectivity to a surrounding dielectric such as the gate-insulating layer220or the L-type spacer240. The gate spacer can be formed of silicon nitride or silicon oxynitride. The dense dielectric gate spacer creates a tensile stress or compressive stress due to the heat generated during manufacturing or operations. The stress physically affects on the source/drain region215, the silicide regions260a,260b, or channel regions, therefore the performance of the semiconductor device deteriorates and the reliability of the semiconductor device decreases.

Therefore, semiconductor devices having no gate spacer, according to the various exemplary embodiment of the present invention, do not deteriorate and can maintain high reliability during manufacturing and operations.

Also, because semiconductor devices according to various exemplary embodiments of the present invention include the source/drain silicide regions260anot lower than the surface of the substrate205, the channel characteristic is not impaired. That is, the operation of the transistor is excellent. If exemplary embodiments of the present invention are not applied, the source/drain silicide regions260acan be physically and chemically damaged.

In an exemplary embodiment of the present invention, forming nickel silicide provides superior planarization characteristics as well as superior semiconductor characteristics since it can make the surface height of the source/drain silicide regions260athe same as the surface height of the substrate205, which in turn provides favorable conditions when a semiconductor device is manufactured. The method of forming nickel silicide will be described later.

Hereinafter, a method of manufacturing a semiconductor device according to an exemplary embodiment of the present invention will be described with reference toFIGS. 2A through 2K.FIG. 2A through 2Kare vertical views illustrating a method of manufacturing device according to exemplary embodiment of the present invention.

Referring toFIG. 2A, isolation regions210are formed in a substrate205, and a gate-insulating layer220a, a gate electrode layer230a, and a gate mask layer235are formed on a whole surface of a substrate205.

For example, a silicon substrate, a silicon-germanium (SiGe) substrate, a compound semiconductor substrate, a silicon-on-insulator (SOI) substrate, or silicon-on-sapphire (SOS) substrate can be used as the substrate205. The silicon-germanium substrate can be formed by implanting germanium or growing silicon germanium in an active region between the isolation regions210near the surface of a silicon substrate. Alternatively, only a source/drain region can be a silicon germanium substrate. If only the source/drain region is the silicon germanium substrate, the silicon germanium substrate can be formed after a gate pattern is formed.

The isolation regions210, for example, can be formed by a shallow trench isolation (STI) method. The STI method involves, for example, etching the substrate205to a depth on the order of 1000 Å to form the surface of the substrate, and filling it with insulating material. The STI forming method is a well known to those in the art, and is not described in detail in the present disclosure.

The gate insulating layer220acan be silicon oxide, an insulating silicon compound such as silicon nitride or silicon oxynitride, an insulating compound including aluminum oxide, aluminum oxynitride, or hafnium oxide, or any other insulating inorganic material. In an exemplary embodiment of the present invention, silicon oxide is used. The gate insulating layer220acan be made to a thickness on the order of 10 Å by an oxidation method or an oxide-deposition method.

The gate electrode layer230acan be made with a conductive material such as silicon, a conductive compound, metal, or metal silicide. In an exemplary embodiment of the present invention, the gate electrode layer230ais a single layer in order to aid understanding and to avoid complicated description. Also, the gate conductive layer230acan be formed by stacking two or more material layers. For example, a metal-silicide compound layer using metal such as tungsten on silicon can be formed. The metal-silicide layer can be formed by heat treatment after a metal layer is formed on a silicon layer. Also, the gate electrode layer230acan be a three layered structure by having an additional metal layer on top of a metal-silicide layer or can be a structure having more than three layers. In order to avoid complicated drawings and description, the formation of only a single gate electrode layer230ais illustrated and described, but it is understood that the gate electrode layer230aincludes not only a single layered structure, but also a multi-layered structure. The gate electrode layer230acan be formed to a thickness on the order of 1000 Å, for example, in the range of 3000 Å to 5000 Å.

The gate electrode layer230acan be formed by deposition method, and additional heat treatment and ion implantation can be performed after the deposition. For example, the layer can be heated in the order of 100° C. to stabilize a crystal status of the gate electrode layer230a, and ion implanted with group III or group V, such as boron (B), phosphorous (P), or arsenic (As).

The gate mask layer235can be used as an etch mask when the gate electrode layer230ais patterned. In an exemplary embodiment, the gate mask layer235is silicon nitride, but another material layer can be used as the gate mask layer235such as silicon oxynitride. The gate mask layer235can be formed by deposition method. For example, the thickness of the gate mask layer235is about 1000 Å to about 2000 Å in an exemplary embodiment.

Also, an anti-reflective layer (ARL) can be formed on the gate electrode layer230aor the gate mask layer235in order to stabilize the following process. The ARL can be formed of organic or inorganic material. The organic material can be formed of high molecular resin, or the inorganic material can be formed of silicon nitride or silicon oxynitride. The ARL can be formed to a thickness in the order of 100 Å. Since the thickness can be verified according to a wavelength of light used in photolithography processes, a detailed description is omitted. The ARL is not illustrated in this drawing in order to avoid complicating the description of the present invention.

Referring toFIG. 2B, a gate electrode230band a gate-insulating layer220are formed by patterning the gate electrode layer230aand the gate insulating film220a. Specifically, a mask pattern (not shown) is formed on the gate electrode layer230afor patterning, the gate electrode230band the gate-insulating layer220are formed by etching, and the mask pattern is removed. For example, the mask pattern can be a photoresist pattern. Alternatively, as already described in connection withFIG. 2A, if the gate mask layer235is formed, the gate mask layer235is patterned, and then the gate electrode230band the gate-insulating layer220are patterned with the patterned gate mask layer235as an etch mask. Also, the patterned gate mask layer235can remain on the gate electrode230b. In this drawing, in order to aid understanding of the present invention, only the gate electrode230band the gate-insulating layer220remain after patterning.

Referring toFIG. 2C, an L-type spacer layer240aand a gate spacer layer250aare formed on the entire surface of the gate electrode230band the substrate205. The L-type spacer layer240acan be a silicon oxide layer, and formed by deposition method, and the L-type spacer layer240acan be formed to a thickness on the order of 10 Å. Alternatively, the L-type spacer layer240acan be a multi-layered structure. In this case, the L-type spacer layer240acan include at least two layers selected from the group including silicon oxide, silicon nitride, silicon oxynitride, and others. The selected materials need not be different. That is, the L-type spacer layer240acan be formed by stacking two silicon oxide layers. In addition, methods of forming the same material can be changed. For example, if two or more layers of silicon oxide are stacked, the L-type spacer layer240ais formed at a low temperature by deposition method, and then the L-type spacer layer240ais formed at a high temperature by a plasma method. In addition to the previous methods, the L-type spacer can be formed by various other methods.

Before the gate spacer layer250ais formed, source/drain region215ofFIG. 1A through 1Ecan be formed. The source/drain region215can be formed by implanting P, As, or B ions after an L-type spacer layer240ais formed, or while an L-type spacer layer240ais formed (in the case of the multi-layered structure). The source/drain region215naturally aligns the part of the L-type spacer layer240aformed on the sidewall of the gate electrode230b. Also, the halo ion implantation region217ofFIGS. 1A through 1Ecan be formed with the source/drain region215. The halo ion implantation region217can be formed after or before the source/drain region215is formed.

The halo ion implantation region217can be formed by implanting opposite polarity ions to ions which are implanted or which will be implanted in the source/drain region215. Because halo ion implantation is performed while tilting the substrate205, the halo ion implantation region217can be formed under the vertical part of the L-type spacer layer240aformed on the sidewall of the gate electrode230b. The halo ion implantation217and the source/drain region215can be overlapped. If the concentration of the source/drain region215is higher than the concentration of the halo ion implantation region217, it is unlikely that the concentration of the source/drain region215will be diluted.

The gate spacer layer250ais a layer to form a gate spacer on the sidewall of the gate electrode230in the subsequent process, and can be formed of silicon nitride by a deposition method to a thickness in the order of 100 Å. Here, before the gate spacer layer250ais formed, the light doped source/drain region215can be formed. Phosphorous (P), Arsenic (As), or both can be implanted as an impurity. This process is generally known as a light doped drain (LDD) (N−) source/drain215forming process. Also, an ion implantation region having the opposite polarity to the source/drain region217can be formed. For example, boron (B) ions can be implanted. This process is generally known as a halo or pocket-well forming process. This exemplary embodiment is known as a NMOS. The PMOS is the reverse of the NMOS polarity. Specifically, a P-process has a boron (B) implantation at the source/drain region215, and the halo or pocket well forming process has a phosphorous (P) or arsenic (As) implantation.

Referring toFIG. 2D, a gate spacer250and an L-type spacer240are formed. Specifically, a first dry etch process is performed on the entire surface to transform a gate spacer layer250ato the gate spacer250, a next wet or dry etch process is performed to transform the L-type spacer layer240ato the L-type spacer240. The dry etch process to form the gate spacer250can be performed with plasma status main etch gas comprising F— or Cl— with plasma status Ar, O2, and others. The dry etch process to form the gate spacer250is well known and not described in the present invention. The L-type spacer240can be formed by performing either a wet etch process or a dry etch process. In an exemplary embodiment of the present invention, the L-type spacer240can be formed by performing a wet etching process with an etchant containing dilute HF. When the wet etch process is used, the surface of the substrate205does not receive plasma damage caused by the etch process and the wet etch process can be performed continuously. When the gate spacer250is formed, the upper region and the side of upper region of the gate electrode230bare exposed and the surface of the substrate205corresponding to the source/drain region215is also exposed.

In this step, before forming the L-type spacer250, a process to implant impurities in the substrate205corresponding to the source/drain region215can be formed. Impurities can be implanted with P, As, or B ions, and relatively higher concentrations compared to previous impurities implantation processes, for example more than twice higher concentration, can be applied. Typically, it is known as an N+ or P+ formation process. It is not described in the drawing to aid understanding of the technical concepts of the present invention since it overlaps with the source/drain silicide regions to be formed later. It is also not described in the drawing since it may not be performed. In particular, N+ or P+ regions may not be formed when silicide regions are formed.

Referring toFIG. 2E, silicide regions260aand260bare formed on an upper region of the exposed gate electrode230and the upper region of the source/drain region215. In more detail, the silicide regions260a,260bare formed by forming a metal layer (not shown) for silicide on the upper region of the exposed gate electrode230and the upper region of the source/drain region215and performing heat treatment. The metal layer for silicidation can be formed by electroless plating or physical deposition such as sputtering. The silicide regions260a,260bcan be formed, after the metal layer for silicidation is formed, by applying heat of several hundreds ° C. to induce the combination of the metal layer and silicon atoms for silicidation. In the present exemplary embodiment of the present invention, the metal layer for silicidation is a nickel layer. When nickel is used for forming silicide, the height of silicide regions260a,260bcan have the same or similar height of the substrate205or gate electrode230before forming silicide. When the metal layer for silicidation is formed using a physical deposition method, an additional step to remove the metal layer that has not become a silicidation layer can be performed. When the metal layer for silicidation is formed by electroless plating, the metal layer can be selectively formed in the area where silicon is exposed, which includes the upper region of the gate electrode230and the surface of the substrate205which corresponds to the area of the source/drain. Thus, the process to remove the metal layer for silicidation can be skipped, if silicide regions260a,260bare formed by forming the metal layer for silicidation using electroless plating. In an exemplary embodiment of the present invention, the metal layer is formed for silicidation using electroless plating.

The silicide regions260can be formed, after the metal layer for silicidation is formed, by forming an additional metal layer for metal alloy (not shown) and applying heat treatment. In particular, the metal layer for silicidation can be formed using nickel. The metal layer for metal alloy can also be formed using electroless plating. The metal layer for metal alloy can be formed after forming the metal layer for silicidation, however, the metal layer for metal alloy can be formed simultaneously with the metal layer for silicidation. For example, in a case where both metal layers are formed at the same time, they can be formed using plating solutions having metal atoms for silicide and metal atoms for metal alloy. In this step, the ratio of the metal layer for silicidation to the metal layer for metal alloy is the same as the ratio of the metal atoms for silicide to the metal atoms for metal alloy in the plating solution. The containment ratio can be set as an atomic percentage (atomic %). When the two metal layers are alloyed, the atoms of each of the metal layers can be put in the plating solution according to the atom ratio of the two metal layers. Note that each of the metal layers is alloyed according to the atom percentage. In an exemplary embodiment of the present invention, the plating solution has an atomic ratio of the metal atom for silicidation to the metal atom for the metal alloy of less than 30 atomic percentages. In other words, the ratio of the metal layer for silicidation to the metal layer for metal alloy can be under 10:3 atomic percentage. Nonetheless, since this is one exemplary embodiment of the present invention, the present invention is not limited to these specific numbers.

Referring toFIG. 2F, sacrificial metal layers270a,270bare formed on the surface of the silicide regions260a,260b. The sacrificial metal layers270a,270bcan be selectively formed on the surface of the silicide regions260a,260busing electroless plating. In an exemplary embodiment of present invention, the sacrificial metal layers270a,270bcan be formed using Pt or Pd, but they are not limited to these types of metal since they can be formed using various other types of metal. In the description ofFIG. 2E, in the case when the metal layer for alloy is formed, the sacrificial metal layers270a,270bcan be formed of the same metal that is used to form the metal layer for alloy. In the descriptions ofFIG. 2E, if the metal layer for alloy is not formed or removed after it is formed, the sacrificial metal layers270a,270bcan be formed directly on the silicide regions260a,260b. Also, the sacrificial metal layers270a,270bcan be directly formed on the metal layer for alloy without removing the metal layer for alloy. In other words, the sacrificial metal layers270a,270bcan be formed regardless of the metal layer for alloy described inFIG. 2E.

The sacrificial metal layers270a,270bcan be formed using electroless plating to a thickness of approximately 100 Å in an exemplary embodiment, but other embodiments of the present invention are not limited to this thickness. In other exemplary embodiments of the present invention, the sacrificial metal layers270a,270bcan be used as pad metal layers. In this case, the thickness can be about 500 Å. Also, the sacrificial metal layers270a,270bare formed by forming source/drain sacrificial metal layers270aand the gate sacrificial metal layer270bindependently. For example, there can be a case that the source/drain sacrificial metal layer270ais formed, whereas the gate sacrificial metal layer270bis not formed.

Referring toFIG. 2G, the gate spacer250is removed. The gate spacer250can be removed using either a dry etch method or a wet etch method. When the gate spacer250is removed using a dry etch method, the etchant comprises an F— or Cl— plasma. When the gate spacer250is removed using a wet etch method, the gate spacer250can be removed using phosphoric acid. If phosphoric acid is used, the gate spacer250can be etched using phosphoric acid heated at higher than room temperature, for example, at 40° C. If an additional wet etching process is used, it can be performed with a subsequent cleaning process. If the gate spacer250is removed by a wet etch process, because the subsequent cleaning process is a wet process, they can be performed in the same location.

Referring toFIG. 2H, the sacrificial metal layer270is removed. The sacrificial metal layer270can be removed using, for example, either aqua regia or a mixture of H2SO4and H2O2. Although the metal layer for alloy can be formed under the sacrificial metal layer270, the sacrificial metal layer270is removed. If the metal layer for alloy exists, the metal layer for alloy can be removed with the sacrificial metal layer270. As a result, the surface of the silicide regions260a,260bcan be exposed.

Referring toFIG. 2I, an interlayer dielectric layer280is formed. Then via holes290aare formed by vertically penetrating the interlayer dielectric layer280so that the surface of the silicide regions260are exposed. For example, the interlayer dielectric layer280can be formed of silicon oxide, or the interlayer dielectric layer280can be formed using a combination of silicon oxide layers having different physical properties. For example, the interlayer dielectric layer280can be formed by sequentially forming a TEOS layer and an HDP oxide layer. However, this is exemplary, and other dielectric layers can be formed as a single layer or as multiple layers.

Additionally, before the via holes290aare formed, if the interlayer dielectric layer280is formed with silicon oxide, a dielectric layer having greater hardness than that of the interlayer dielectric layer280(not shown; refer toFIG. 1E) can be additionally formed on the interlayer dielectric layer280. For example, a dielectric layer having a greater hardness than that of silicon oxide, such as silicon nitride or silicon oxynitride, can be formed on the interlayer dielectric layer280. The harder dielectric layer can fasten the interlayer dielectric layer280, can perform the function of van etch stop layer or a CMP (chemical mechanical polishing) stop layer in the subsequent process, and also block movement of interlayer impurities. In an exemplary embodiment of the present invention, the via holes290acan be formed by performing a dry etch process on top of the interlayer dielectric layer280after forming pattern masks (not shown) to form the via holes290a. The layer having a greater hardness than that of the interlayer dielectric layer280corresponds to the upper dielectric layer285in the descriptions ofFIG. 1E.

Referring toFIG. 2J, a liner layer295ais formed on the interior wall of the via holes290a. The liner layer295a, for example, can be a metal layer such as Ti/TiN or can be an inorganic dielectric layer such as silicon nitride. If the interlayer dielectric layer280is an oxide layer, the liner layer295aprevents the material formed inside via holes290afrom having a direct contact to the oxide layer. As illustrated in the drawing, the liner layer295acan be formed on top of the interlayer dielectric layer280, also it can be formed on the bottom area of the via holes290asuch that it has a direct contact with the silicide regions260aand260b.

Referring toFIG. 2K, via plugs290are formed inside the via holes290a. Specifically, the via plugs290are formed by stuffing conductive materials inside the via holes290aafter a node isolation of the liner layer295a. In order to perform the node isolation of the liner layer295a, a material for the node isolation of the liner layer295ais formed extensively inside the via holes290a, on the interlayer dielectric layer280and on the liner layer295a, and then a whole surface etch process or a CMP process is performed for node isolation of the liner layer295a. After node isolation of the liner layer295a, the material layer is removed and the via plugs290are formed by stuffing conductive material inside the via holes290a. The via plug290, for example, can be formed using tungsten or other types of metal. In particular, the material to form the via plugs290fills the inside of the via holes and can be formed on top of the interlayer dielectric layer280. The surface of the via plug290is processed such that the surface has the same height as the surface height of the interlayer dielectric layer280.

Then, the semiconductor device shown inFIG. 1Ais completed by forming signal-transfer wires300that are electrically connected to the via plugs290. The signal-transfer wires300are formed of conductive materials, for example, tungsten, aluminum, or copper. If a method such as dual damascene is used, the via plugs290and the signal-transfer wires300can be formed simultaneously. The dual damascene method is well known and is not described in detail in the present invention.

While embodiments of the present invention have been particularly shown and described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that the scope of the invention is given by the appended claims, rather than the preceding description, and all variations and equivalents which fall within the range of the claims are intended to be embraced therein. Therefore, it should be understood that the above embodiments are not limiting, but illustrative in all aspects. As described above, according to the semiconductor device with free of gate spacer stress and method of manufacturing the same in the exemplary embodiments of the present invention, the source/drain, the gate electrode, the channel region do not get stress caused by the gate spacer, and physical and chemical damages are not introduced in the source/drain region. As a result, the characteristics of the semiconductor device are improved, and productivity and yield can be improved due to the method of manufacturing semiconductor devices provided by the various exemplary embodiments of the present invention.