Semiconductor devices with active regions of different heights

Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a first transistor having a first active area, and a second transistor having a second active area. A top surface of the first active area is elevated or recessed with respect to a top surface of the second active area, or a top surface of the first active area is elevated or recessed with respect to a top surface of at least portions of an isolation region proximate the first transistor.

TECHNICAL FIELD

The present invention relates generally to the fabrication of semiconductor devices, and more particularly to manufacturing transistors.

BACKGROUND

A transistor is an element that is used frequently in semiconductor devices. There may be millions of transistors on a single IC, for example. A common type of transistor used in semiconductor device fabrication is a metal oxide semiconductor field effect transistor (MOSFET), as an example. A transistor typically includes a gate dielectric disposed over a channel region in a substrate, and a gate electrode formed over the gate dielectric. A source region and a drain region are formed on either side of the channel region within the substrate.

Complementary metal oxide semiconductor (CMOS) devices utilize both p type and n type channel transistor devices in complementary configurations. The p type and n type transistor devices of CMOS devices are typically referred to as p channel metal oxide semiconductor (PMOS) field effect transistors (PFETs) and n channel metal oxide semiconductor (NMOS) field effect transistors (NFETs), for example. A PFET is formed in an n well (e.g., a well implanted with n type dopants) and an NFET is formed in a p well. An isolation region such as a shallow trench isolation (STI) region is formed between the n well and p well of the PFET and the NFET, respectively, to electrically isolate the active device regions.

What are needed in the art are improved methods of fabricating CMOS devices and other semiconductor devices comprising transistor devices, and structures thereof.

SUMMARY OF THE INVENTION

These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by embodiments of the present invention, which provide novel semiconductor devices, CMOS devices, and methods of fabrication thereof.

In accordance with an embodiment of the present invention, a semiconductor device includes a first transistor having a first active area, and a second transistor having a second active area. A top surface of the first active area is elevated or recessed with respect to a top surface of the second active area, or a top surface of the first active area is elevated or recessed with respect to a top surface of at least portions of an isolation region proximate the first transistor.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

CMOS devices and other semiconductor devices comprising transistors can be challenging to manufacture. For example, in CMOS devices, PFET and NFET devices have different operating characteristics and parameters. NFETs tend to have more junction leakage than PFETs, due to different behaviors of the dopants used. It can be difficult to tune processing parameters of both PFET and NFET transistors and optimize performance of a CMOS device, for example.

As one example, in some CMOS devices and applications, it may be desirable in some applications for active areas to be elevated of some transistors, such as PFETs, with respect to isolation regions, in order to maximize device performance of the PFETs. Elevating active areas of PFETs would result in a wrap-around of a gate dielectric and gate deposited over the active area, increasing an effective width of the gate, because of the additional surface area of the gate material over the channel region. However, elevating active areas of other transistors such as NFETs in the same CMOS device may result in high junction leakage and degradation of device performance of the NFETs. Thus, recessing isolation regions for all types of transistors of CMOS devices may not be possible in some applications.

Embodiments of the present invention provide novel integration schemes for selectively recessing isolation regions proximate active areas of PFETs, but not proximate active areas of NFETs of CMOS devices. Several methods will be described herein that provide optimization of performance for both PFETs and NFETs of CMOS devices. Embodiments of the present invention may also be implemented in semiconductor devices comprising other types of transistors, to be described further herein. Embodiments of the present invention may also be used to form multiple gate transistors in some regions of a semiconductor device, but not others, also to be described further herein. Integration schemes are also disclosed wherein isolation regions are elevated proximate active areas of some transistors, but not proximate active areas of other transistors, or wherein isolation regions are more elevated proximate active areas of some transistors than proximate active areas of other transistors.

Embodiments of the present invention provide novel semiconductor devices that comprise transistors with elevated or recessed active areas in some regions with respect to isolation regions, yet the active areas of transistors in other regions are not elevated or recessed, but rather, may be substantially coplanar with the isolation regions. Embodiments of the present invention also provide semiconductor device wherein top surfaces of active areas of some transistors are elevated or recessed with respect to active areas of other transistors. For example, embodiments of the present invention include semiconductor devices wherein a first transistor comprises a first active area, and a second transistor comprises a second active area. A top surface of the first active area is elevated or recessed with respect to a top surface of the second active area.

The present invention will be described with respect to embodiments in a specific context, namely, in the formation of CMOS devices. Embodiments of the present invention may also be applied, however, to other semiconductor devices that utilize more than one type of transistor.

Embodiments of the present invention will next be described with reference toFIGS. 1 through 12. Referring first toFIG. 1, a cross-sectional view of a semiconductor device100is shown. The semiconductor device100includes a workpiece101comprising a semiconductor substrate, body, or wafer comprising silicon or other semiconductor materials, for example. The workpiece101may also include other active components or circuits, not shown. The workpiece101may comprise single-crystal silicon, for example. The workpiece101may include other conductive layers or other semiconductor elements, e.g., transistors, capacitors, diodes, etc. Compound semiconductors, GaAs, InP, Si/Ge, or SiC, as examples, may be used in place of silicon. The workpiece101may comprise a silicon-on-insulator (SOI) substrate or germanium-on-insulator (GOI) substrate, as examples.

The workpiece101comprises a first region102and a second region104proximate the first region102. There may be a plurality of first regions102and second regions104across a surface of the workpiece101, for example, not shown. The semiconductor device100includes a first transistor130in the first region102and a second transistor132in the second region104. In some embodiments, the first transistor130comprises a PFET formed over a first well region106, and the second transistor132comprises an NFET formed over a second well region108. The first well region106may comprise an n well, and the second well region108may comprise a p well, if the transistors130and132comprise a PFET and an NFET of a CMOS device. Alternatively, the first and second transistors130and132may comprise other types of transistors, for example. The second transistor130may comprise a different type of transistor than the first transistor132, to be described further herein.

Alternatively, the well regions106and108may both comprise n wells and/or p wells, for example, implanted with the same or different dopant types or the same or different dopant concentrations, for example. Alternatively, the first well region106may comprise a p well, and the second well region108may comprise an n well, as another example.

The view shown inFIG. 1comprises a cross-sectional view cut through a source or drain region124and126of the transistors130and132. Source and drain regions124and126of the first transistor130and the second transistor132will later be formed in a top portion of the first well region106and second well region108, respectively, for example.

Isolation regions110are disposed in a top portion of the workpiece101. At least one isolation region110is formed between the first well region106of the first transistor130and the second well region108of the second transistor132. The isolation regions110may be formed by forming trenches in the workpiece101and forming at least one insulating material in the trenches.

The isolation regions110may comprise one or more insulating liners112and114disposed within and lining the trenches, and a fill material116formed over the liners112and114. The liners112and114may comprise at least one insulating liner comprising an oxide material layer, a nitride material layer, or combinations or multiple layers thereof. The fill material116may comprise an insulator or a semiconductive material, as examples. Alternatively, the liners112and114and fill material116may comprise other materials. The isolation regions110alternatively may comprise a single material comprising an insulating fill material and may not comprise a liner, for example.

The source and/or drain region124and a channel region128athat will later be formed in the first well region106(see the top view ofFIG. 2) comprise an active area124/128aof the first transistor130. The active area124/128aof the first transistor130is also referred to herein as a first active area124/128a. The source and/or drain region126and a channel region128bthat will later be formed in the second well region108(see the cross-sectional view ofFIG. 4) comprise an active area126/128bof the second transistor132. The active area126/128bof the second transistor132is also referred to herein as a second active area126/128b.

In accordance with some embodiments of the present invention, the top surface123of the active area124/128aof the first transistor130, but not the top surface127of the active area126/128bof the second transistor132, is elevated (or recessed, shown in phantom at123′), with respect to top surface125and/or top surface129of isolation regions110disposed proximate the first transistor130and the second transistor132, respectively, creating a step height. The top surfaces123or123′ of the active area of the first transistor130may be elevated or recessed by an amount or dimension d1, for example, wherein dimension d1comprises about +/−100 nm or less in some embodiments. In some applications, the step height or dimension d1may comprise about +/−5 to 10 nm, as another example. Alternatively, dimension d1may comprise other values, depending on the technology and/or the transistor130requirements. The elevated active area of the first transistor130may improve the performance of the first transistor130in some embodiments, to be described further herein.

In other embodiments, dimension d1of the step height may comprise about 100 nm or greater. For example, the novel methods to be described herein may be used to form multiple gate transistors130such as FinFETs in some regions of the semiconductor device100. The multiple gate transistors130may comprise an active area comprising a dimension d1above the top surface of the workpiece101by several hundred nm to several μm in these embodiments, for example. Embodiments of the present invention may be used to create FinFETs or other multiple gate transistors130on the same chip as planar transistors132, to be described further herein.

FIG. 2shows a top view of the first transistor130of the semiconductor device100shown inFIG. 1in the view at2-2, illustrating the active area124/128aof the first transistor130. The first well region106comprises an area where source and drain regions124will later be formed. A channel region128awill later be formed between the source region and drain regions124. The source and drain regions124and channel region128awill later be formed within the first well region106of the first transistor130, for example. The source and drain regions124, shown as first well regions106inFIG. 2, may not terminate at the top and bottom as shown inFIG. 2, but may be larger and may extend vertically downwards and upwards to route to an adjacent transistor, for example, not shown.

Next, a gate dielectric material134and a gate material136are formed over the workpiece101, and the gate material136and the gate dielectric material134are patterned using lithography, forming a gate136and a gate dielectric134over the channel regions128aand128b, as shown in a cross-sectional view inFIG. 4and in a top view inFIG. 5. Then, the source and drain regions124and126are formed, as shown inFIG. 3.

FIG. 3shows a cross-sectional view of the semiconductor device100shown inFIG. 1, after a semiconductive region118is formed within the first well region106of the first transistor130and after a semiconductive region120is formed within the second well region108of the second transistor132. The semiconductive region118of the first transistor130may comprise a p+ material118, and the semiconductive region120of the second transistor132may comprise an n+ material120, if the first transistor130comprises a PFET and the second transistor132comprises an NFET. Alternatively, the semiconductive regions118and120of the source and drain regions124and126, respectively, may comprise other types of materials.

FIG. 3shows a cross-sectional view of the transistors130and132of semiconductor device100proximate the source or drain regions124and126, respectively, for example. The conductive materials118and120of the transistors130and132may be formed using implantation processes, deposition processes, or epitaxial growth processes, for example. The conductive materials118and120may comprise a stress material such as embedded SiGe or other compound semiconductor material adapted to introduce a stress to the adjacent channel regions128aand128b, for example. The conductive materials118and120may both comprise p+ material or n+ material in some embodiments. The conductive materials118and120form the source and drain regions124and126of the first and second transistors130and132, respectively.

An optional silicide (not shown) may later be formed over the p+ material118and the n+ material120, for example. The optional silicide and the p+ material118may comprise a source and/or drain region124of the first transistor130, and the silicide and the n+ material120may comprise a source and/or drain region126of the second transistor132.

FIG. 4shows a cross-sectional view of the transistors130and132of semiconductor device100proximate the gate136and channel128aand128bregions. A gate dielectric134is formed over the channel regions128aand128band may be formed using an oxidation process, for example. Alternatively, the gate dielectric134may be deposited, e.g., if the gate dielectric134comprises a high dielectric constant k material. The gate136is formed over the gate dielectric134of the first and second transistors130and132. The gate dielectric134and gate136wrap around the first transistor130, e.g., in a vertical direction, due to the elevated active area124/128aof the first transistor130over the channel region128in some embodiments, which increases device100performance in some embodiments. The gates136may extend horizontally across the workpiece101, or the gates136may be patterned in each region102and104, as shown in phantom inFIGS. 4 and 5.

FIG. 5shows a top view of the first transistor130of the semiconductor device100shown inFIGS. 3 and 4, illustrating the gate136in the top view. To correlateFIG. 5withFIGS. 3,4, and6,FIG. 3shows a cross-sectional view of the device100in a view at3-3inFIG. 5;FIG. 4shows a cross-sectional view of the device in a view at4-4inFIG. 4; andFIG. 6shows a cross-sectional view of the first transistor130of the semiconductor device100shown inFIG. 4rotated by ninety degrees and shown in a view at6-6inFIG. 5, for example. Sidewall spacers comprising insulating materials may be formed on the sidewalls of the gate136and gate dielectric134, not shown.

Embodiments of the present invention provide novel methods of creating a step height (e.g., comprising dimension d1) between the active areas of the first transistor130and at least portions of isolation regions110proximate the first transistor130, to be described further herein. The top surface of the active area124/128aof the first transistor130is elevated or recessed with respect to the top surface of the active area126/128bof the second transistor132, for example.

To manufacture the semiconductor device100, referring again toFIG. 1, the workpiece101is provided. The workpiece101may include a pad oxide and a pad nitride disposed over the pad oxide, for example, not shown. Isolation regions110are formed in the workpiece101and in the pad oxide and pad nitride. The isolation regions110may be formed by disposing a photosensitive material and an optional hard mask (not shown) over the workpiece101. The photosensitive material may comprise a photoresist, for example. The hard mask may comprise one, two, or more material layers. The hard mask may comprise a nitride material layer, and an oxide material layer disposed over the nitride material layer, for example. The photosensitive material and optional hard mask are patterned using lithography with a pattern for trenches, and exposed portions of a top portion of the workpiece101are etched away using the patterned photosensitive material and/or hard mask, patterning the top portion of the workpiece101with trenches. The photosensitive material and/or hard mask is then removed.

The trenches may be filled with at least an insulating material to form at least one isolation region110. In some embodiments, the at least one isolation region110comprises at least one insulating liner112or114and a fill material116disposed over the at least one insulating liner112or114.

For example, the trenches may be lined with a first liner112, by depositing the first liner112over the workpiece101and the trenches patterned in the workpiece101, pad oxide, and pad nitride. The first liner112may comprise an oxide such as silicon dioxide, for example, although other materials may also be used. An optional second liner114may be deposited over the first liner112, as shown. The second liner114may comprise a nitride such as silicon nitride, for example, although other materials may also be used. A fill material116is formed over the liners112and114to fill the trenches.

The fill material116may comprise an insulating material such as silicon oxide, silicon nitride, or combinations thereof, for example. The fill material116may comprise a high density plasma (HDP) oxide or a tetra ethyl oxysilane (TEOS)-based oxide, examples. In some embodiments, the fill material116may comprise a semiconductive material such as silicon, which may improve stress properties of the isolation region110, e.g., by providing a stress match for the material of the workpiece101. The liners112and114are optional: if the fill material116comprises an insulating fill material, the liners112and114may not be included in the isolation regions110, for example.

Excess portions of the fill material116and the optional liners112and114may be removed from over the top surface of the workpiece101, e.g., from over the pad nitride, using an etch process and/or a chemical mechanical polish (CMP) process, for example, forming the isolation regions110within the top surface of the workpiece101. The isolation regions110may comprise shallow trench isolation (STI) regions in some embodiments, for example, although the isolation regions110may alternatively comprise other types of isolation regions, such as deep trench (DT) isolation regions or field oxide regions, as examples. The isolation regions110may extend into the workpiece101about 300 nm or less in some embodiments, although alternatively, the isolation regions110may extend into the workpiece101by greater than about 300 nm, as examples.

The workpiece101may be planarized using a CMP process adapted to stop on the pad nitride, for example. The pad nitride and the pad oxide may then be removed using an etch process and/or CMP process. The top surface of the isolation region110may extend slightly above the top surface of the workpiece101after the pad nitride and pad oxide removal, e.g., by a few nm to about 20 nm. The isolation region110may be sequentially reduced in height slightly throughout the manufacturing process, e.g., by about 1 or 2 nm with each subsequent cleaning and etch process, for example, so that by the end of the manufacturing process for the transistors130and132, the isolation regions110are substantially coplanar with the top surface of the workpiece101, except in region102where a step height d1is intentionally created in accordance with embodiments of the present invention. Alternatively, the isolation regions110may be etched or polished using a CMP process so that they are substantially coplanar with the workpiece101top surface, for example. However, for purposes of discussion herein, the isolation regions110are shown as being substantially coplanar with portions of the top surface of the workpiece101other than the active areas124/128aof the first transistor130inFIGS. 1,3,4, and7through12, for example.

An isolation region110is disposed between the first well region106of the first transistor130and the second well region108of the second transistor132, as shown. An isolation region110may be formed on an opposite side of the first transistor130, e.g., on the left side inFIG. 1, to define the first active area124/128athat comprises the source and drain regions124and the channel region128aof the first transistor130. An isolation region110may be formed on an opposite side of the second transistor132, e.g., on the right side inFIG. 1, to define the active areas126/128bthat comprise the source and drain regions126and the channel region128bof the second transistor132.

At this point in the manufacturing process flow, the step height or dimension d1between the active area of the first transistor130and portions of isolation regions110proximate the first transistor130is formed, using one or more embodiments of the present invention, which are shown inFIGS. 7 through 12. The step height d1may be formed by elevating the top surface of the first active area124/128aof the first transistor130, by lowering a top surface of at least a portion of the isolation regions110at least proximate the first transistor130so that the height of the active area124/128aof the first transistor130is greater or less than the height of at least portions of the isolation regions110proximate the first transistor130, or by removing or lowering a top portion of the workpiece101, e.g., the active areas124/128aof the first transistor130proximate the isolation regions110.

For example, in a first embodiment of the present invention shown inFIG. 7in a cross-sectional view, a step height comprising dimension d1is created between the active area124/128a(e.g., the top portion of the first well region106and also the channel region128a) of the first transistor130and portions of isolation regions110proximate the first transistor130using a masking material140and an etch process142. The masking material140is formed over the entire workpiece101, e.g., over the isolation regions110and the active areas124/128aand126/128bof the first transistor130and the second transistor132, respectively. The masking material140may comprise a photosensitive material such as a photoresist, for example. The masking material140is patterned using lithography to remove the masking material140from over the first region102, e.g., from over the active area124/128aof the first transistor130and from over portions of the isolation regions110proximate the first transistor130, as shown.

An etch process142is then used to reduce the height of or recess portions of the isolation regions110proximate the first transistor130. The etch process142may comprise an etch process that is adapted to remove the materials112,114, and116of the isolation regions110, but not the material106of the active areas124/128aof the first transistor130, for example. The etch process142may comprise a dry or wet etch process, for example. The etch process142may comprise a selective etch process adapted to recess the isolation region110proximate the first well region106of the first transistor130, as another example. The etch process142may comprise a CxFy-based or CxHyFz-based reactive ion etch (RIE) process or a HF-based wet etch process, as examples, although other etch chemistries may also be used.

The top surface123of the active area124/128aor the first well region106of the first transistor130comprises a height that is greater than the top surface125of portions of the isolation regions110proximate the first transistor130, as shown. The height of the top surface123is also referred to herein as a first height, for example. The top surface127of the active area126/128bor the second well region108of the second transistor132and the top surface129of portions of the isolation regions110proximate the second transistor132comprise substantially the same height as the first height of the top surface123of the first transistor130in this embodiment, as shown. The top surface125of portions of the isolation regions110proximate the first transistor130comprises a second height, wherein the first height is greater than the second height, for example.

In some embodiments, the lithography process used to pattern the masking material140may utilize a dedicated lithography mask (not shown), e.g., designed specifically for patterning the masking material140. Thus, an additional lithography mask may be required to pattern the masking material140before recessing portions of the isolation regions110proximate the first transistor130.

In other embodiments, the lithography process used to pattern the masking material140may comprise or utilize a lithography mask (also not shown) used to pattern or alter another portion or element of the semiconductor device100. The lithography mask may comprise the same mask that is used to form the first well region106(e.g., using dopant implantation) of the first transistor130in the first region102, as one example. As another example, the lithography mask may comprise the same mask that is used to adjust a threshold voltage (Vt) of the first transistor130, e.g., by implanting a material or substance into the first well region106of the first region102. Alternatively, other lithography masks used to mask the second region104of the workpiece101while the first region102of the workpiece101is altered may also be used. Advantageously, no additional lithography masks are required in these embodiments, providing a cost savings.

The embodiment shown inFIG. 7may alternatively be used to recess the workpiece101or active area124/128aor126/128b(e.g., the well regions106or108) of one of the transistors130or132, respectively. For example,FIG. 8shows an embodiment wherein the etch process142is adapted to etch the active area124/128acomprising the well region106of transistor130in the first region102. Alternatively, the first region102may be masked, and the well region106may be recessed using the etch process142, for example, not shown. A top portion of the workpiece101, e.g., the first well region106of the first transistor130is removed or lowered using the etch process142, proximate the isolation regions110of the first region102of the workpiece101. The top surface123′ of the well region106is lower than the top surface of the isolation region125by amount d1in this embodiment, as shown.

In accordance with a second embodiment of the present invention, a selective etch process144may be used to recess the isolation regions110, or alternatively, to recess the first well region106of the first region102, without the use of a lithography mask.FIG. 9shows a cross-sectional view of a semiconductor device100, illustrating a method of creating a step height d1between the active area124/128aof the first transistor130and isolation regions110, using a selective etch process144to etch away top portions of the isolation regions110and also recessing the active area126/128b(e.g., the upper portion of the second well region108) of the second transistor132. The second well region108of the second transistor132may be implanted with a different dopant material than the first well region106of the first transistor130in this embodiment. Because the second well region108of the second transistor132is implanted with a different dopant material than the first well region106of the first transistor130, an etch process144comprising an etch selectivity of the first well region106to the second well region108may be selected, so that a masking material is not required, as in the first embodiment.

The first well region106of the first transistor130may be implanted with phosphorus (P), and the second well region108of the second transistor132may be implanted with arsenic (As), as examples. The different dopants implanted in the first well region106and the second well region108may create an etch selectivity between the first well region106and the second well region108, for example, so that the second well region108material etches away more rapidly than the first well region106material using certain etch chemistries.

For example, in the embodiment shown inFIG. 9, the etch process144may comprise a wet etch process adapted to etch the isolation regions110and the second well region108, but not the first well region106of the first transistor130. If the second well region108is highly doped, e.g., having a doping concentration of about 1020cm−3, an etch selectivity of about 5:1 may be achieved using an alkaline solution of KOH, NaOH, or LiOH, as examples. Alternatively, different doping concentrations of the second well region108and different etch chemistries may also be used for the selective etch process144, for example.

Furthermore, in the embodiment shown inFIG. 9, before selectively etching the second well region108of the second region104to create the step height d1, the active areas124/128aand126/128bof both the first transistor130and the second transistor132may first be elevated, e.g., using an epitaxial growth process. Alternatively, before selectively etching the second well region108of the second region104, the isolation regions110may be recessed, e.g., by using an etch process adapted to recess the isolation regions110, but not the active areas124/128aand126/128bof the first and second transistors130and132. Either the first well region106or the second well region108may be selectively etched, for example.

In the embodiment shown inFIG. 9, the top surface123of the active area or the first well region of the first transistor130comprises a first height that is greater than the top surface125of the isolation regions110proximate the first transistor130. The top surface123of the active area or the first well region of the first transistor130comprises a first height that is also greater than the top surface127of the active area or the second well region of the second transistor130and the top surface129of the isolation regions110proximate the second transistor132. The top surface125of the isolation regions110proximate the first transistor130, the top surface127of the active area or the second well region of the second transistor130, and the top surface129of the isolation regions110proximate the second transistor132comprise a second height, wherein the first height of the top surface123of the first transistor130is greater than the second height, in this embodiment.

A selective etch process144may alternatively be used to remove a top portion of the first well region106, but not remove the isolation region110material or the second well region108. The etch process144may be adapted to selectively etch or remove the first well region106selective to the isolation region110and second well region108in this embodiment, for example. Thus, the first well region106of the first transistor130in the first region102is selectively etched to create a negative step height or dimension d1, as shown in phantom inFIG. 9. The top surface123′ of the first well region106is lower than the top surfaces of the isolation regions125proximate the first well region106, and is also lower than the top surfaces129of the isolation regions110proximate the second well region108and lower than the top surface127of the second well region108, for example.

The selective etch process144may be adapted to remove a top portion of the isolation regions110at a faster rate than the first well region106and second well region108material is removed in some embodiments. For example, the selective etch process144may be adapted to remove a top portion of the first well region106at a faster rate than the second well region108is removed, in some embodiments. The different etch rates in the first well region106in the first region102and the second well region108in the second region104may be achieved as a result of different dopant concentrations in the well regions106and108, for example. For example, as shown inFIG. 9in phantom, the etch process144may result in the second well region108having a top surface127′ having a height above the isolation regions110of an amount or dimension d2, wherein dimension d2is less than (or alternatively, greater than, not shown) dimension d1of the height of the top surface123of the first well region106above the top surfaces125and129of the isolation region110.

FIG. 10is a cross-sectional view of a semiconductor device100, illustrating a method of creating a step height d1between the first active area124/128aof the first transistor130and isolation regions110in accordance with a third embodiment of the present invention, using a selective epitaxial growth process146to increase the height of the first active area124/128aor first well region106of the first transistor130, as shown at148.

The epitaxial growth process146may comprise introducing SiCl4into a processing chamber that the workpiece101is disposed in, and elevating the temperature to at least about 1,000 degrees C. in the presence of H2for several minutes, as an example. Alternatively, the selective epitaxial growth process146of the first well region106or active area of the first transistor130may comprise other chemistries, temperatures, and time periods, for example. The epitaxial growth process146results in the duplication of the pattern of the top surface of the first well region106of the first transistor130upwardly, as shown by the epitaxial growth at148, creating the step height d1between the first active area124/128aof the first transistor130and the isolation regions110. Advantageously, a lithography mask and process are not required for this embodiment.

The selective epitaxial growth process146may be adapted to grow semiconductive material on top surfaces of the first well region106and the second well region108at different growth rates. The different growth rates in the first well region106in the first region102and the second well region108in the second region104may be achieved using different dopant concentrations in the well regions106and108. For example, as shown inFIG. 10in phantom, the epitaxial growth process146may be adapted to increase the height or top surface127′ of the second well region108by an amount or dimension d2, wherein dimension d2is less than (or alternatively, greater than, not shown) dimension d1of the height or top surface123of the first well region106above the top surfaces125and129of the isolation region110.

In the embodiment shown inFIG. 10, before the selective epitaxial growth process146, the top surfaces125and129of the isolation regions110may be elevated above the top surfaces of the first and second well regions106and108, not shown, e.g., by an amount substantially equal to a thickness of a pad nitride disposed over the workpiece101during the fabrication of the isolation regions. The first and second well regions106and108may be recessed using an etch process, and then the selective epitaxial growth process146may be performed. The isolation regions110may later optionally be recessed using an etch process adapted to etch the isolation regions110but not the first or second well regions106and108. Or, alternatively, the isolation regions110may be gradually and sequentially reduced in height by various cleaning processes and/or etch processes used to fabricate the semiconductor device100in subsequent manufacturing steps.

FIG. 11is a cross-sectional view of a semiconductor device100, illustrating a method of creating a step height d1between the active area124/128aof the first transistor130and portions of isolation regions110proximate the first transistor130in accordance with a fourth embodiment of the present invention, using a masking material150to cover the second transistor132in the second region104of the workpiece101and using a selective epitaxial growth process152to increase the height of the active areas124/128aof the first transistor130.

The masking material150may comprise a hard mask including a nitride material, an oxide material, or combinations and/or multiple layers thereof, as examples, although alternatively, the masking material150may comprise other materials. The masking material150may be patterned using a dedicated lithography mask, or alternatively, the masking material150may be patterned using a lithography mask used to pattern or alter the first region102of the workpiece101in other manufacturing process steps, as described with reference to the embodiment shown inFIG. 7.

The masking material150protects the active area126/128bof the second transistor132, preventing growth or elevation of the active area126/128bor second well region108of the second transistor132. The selective epitaxial growth process152may comprise similar chemistries, temperatures, and time periods as described for epitaxial growth process146ofFIG. 10, for example. After the top surface123of the active area124/128ain the first region102is elevated, the masking material150is removed. The masking material150may be removed during a pre-cleaning step before a gate oxide such as gate dielectric134shown inFIG. 4is deposited, for example.

The epitaxial growth process152results in the duplication of the pattern of the top surface of the first well region106of the first transistor130upwardly, as shown by the epitaxial growth at154, creating the step height comprising dimension d1between the active area124/128aof the first transistor130and the isolation regions110proximate the active areas124/128aof the first transistor130.

The fourth embodiment shown inFIG. 11is particularly advantageous in some applications, because the epitaxial growth process152may be used to form a multiple gate transistor130in the first region102of the workpiece102, as shown inFIG. 12in a cross-sectional view. Because the second region104of the workpiece101is masked with the masking material150, a 1:0 epitaxial growth rate is achieved (e.g., there is no growth at all in the second region104), so that the epitaxial growth process152may be continued for a longer period of time to achieve a relatively large dimension d1above the top surface125of the isolation regions110. Dimension d1may comprise hundreds of nm or several μm, for example, in some embodiments. Dimension d1may be designed based on the requirements of the multiple gate transistor130to be formed, for example. Thus, one or more multiple gate transistors130may be formed in the first region102on the same workpiece101that planar transistors132are formed in the second region104.

As in the other embodiments described herein, the channel regions128aof the active areas124/128aare also elevated (not shown) with respect to portions of the isolation regions110proximate the active areas124/128ausing the epitaxial growth process152, as can be seen in the view shown inFIG. 6.

The multiple gate transistors130ofFIG. 12may comprise FinFET devices wherein gates may be formed over two sidewalls of the elevated channel region128a, for example. The multiple gate transistors130may also comprise tri-gate devices wherein gates are formed over the sidewalls and the top surface of the elevated channel region128a. The multiple gate transistors130may also comprise other multiple gate devices having more than one gate, for example.

The other embodiments described herein with respect toFIGS. 7 through 11may also be used to form elevated active regions124/128aof multiple gate transistors130, resulting in a structure shown inFIG. 12having substantially and/or extremely elevated active regions124/128a, for example.

In the embodiments shown inFIGS. 9 through 12, the top surface123′ of the active area124/128a(e.g., only the first well region106of the active area124/128ais shown in the views ofFIG. 9 through 12) of the first transistor130may comprise a first height that is greater than the top surface125of the isolation regions110proximate the first transistor130. The top surface123′ of the active area124/128aof the first transistor130may also comprise a height that is greater than the top surface127of the active area126/128bof the second transistor130and the top surface129of the isolation regions110proximate the second transistor132. The top surface125of the isolation regions110proximate the first transistor130, the top surface127of the active area126/128bof the second transistor132, and the top surface129of the isolation regions110proximate the second transistor132may comprise a second height, wherein the first height of the top surface123′ of the active area124/128aof the first transistor130is greater than the second height, in these embodiments.

In the embodiments shown inFIG. 8and inFIG. 9in phantom, the top surface123of the active area124/128a(e.g., only the first well region106of the active area124/128ais shown in the views ofFIG. 9 through 12) of the first transistor130may comprise a first height that is less than the top surface125of the isolation regions110proximate the first transistor130. The top surface123of the active area124/128aof the first transistor130may also comprise a height that is less than the top surface127of the active area126/128bof the second transistor130and the top surface129of the isolation regions110proximate the second transistor132. The top surface125of the isolation regions110proximate the first transistor130, the top surface127of the active area126/128bof the second transistor130, and the top surface129of the isolation regions110proximate the second transistor132may comprise a second height, wherein the first height of the top surface123of the active area124/128aof the first transistor130is less than the second height, in these embodiments.

Two or more of the methods described herein with reference toFIGS. 7 through 12may be used to create the step height d1between the active area of the first transistor130and at least portions of isolation regions110proximate the first transistor130in accordance with embodiments of the present invention. The methods described herein may be integrated to optimally tune step heights d1between active area of first transistors130and at least portions of isolation regions110proximate the first transistors130, while avoiding degrading, altering, or affecting the performance of the second transistors132, because a step height is not formed proximate the active areas126/128bof the second transistors132, in some embodiments, or because less of a step height is formed proximate the active areas126/128bof the second transistors132than step height d1of the active areas124/128aof the first transistors130, in other embodiments, as shown in phantom inFIGS. 9 and 10at d2.

For example, a method of manufacturing a semiconductor device100may comprise forming at least one of the plurality of isolation regions110in the first region102and in the second region104of the workpiece101. The first active area124/128aof the first transistor, the second active area126/128bof the second transistor132, and the plurality of isolation regions110may be substantially coplanar as initially formed, for example. Alternatively, the plurality of isolation regions110may initially be slightly elevated above the top surfaces of the first well regions106and the second well region108, for example, not shown. The method may include the steps of: a) masking the second region104of the workpiece101, and then removing top portions of the plurality of isolation regions110proximate the first active area124/128a, as shown inFIG. 7; b) masking the second region104of the workpiece101, and then removing top portions of the first active area124/128a, as shown inFIG. 8; c) selectively etching away a top portion of the plurality of isolation regions110and the second active area126/128b, as shown inFIG. 9; d) selectively etching away a top portion of the plurality of isolation regions110and the second active area126/128b, decreasing the height of the first active area124/128ato the first height by a first amount and decreasing a height of the second active area126/128bby a second amount, wherein the second amount is less than the first amount, as shown inFIG. 9in phantom at127′; e) selectively etching away a top portion of the first active area124/128a, as shown in phantom inFIG. 9at123′; f) increasing a height of the first active area124/128ato the first height using a selective epitaxial growth process146, as shown inFIG. 10; g) increasing the height of the first active area124/128ato the first height by a first amount and increasing a height of the second active area126/128bby a second amount using a selective epitaxial growth process146, wherein the second amount is less than the first amount, as shown inFIG. 10in phantom at127′; h) masking the second region104of the workpiece101and increasing a height of the first active area124/128ato the first height using an epitaxial growth process, as shown inFIGS. 11 and 12; or i) a combination of at least two of the steps a), b), c), d), e), f), g), or h) described above, for example.

After the embodiments of the present invention shown and described inFIGS. 7 through 12, processing of the semiconductor device100is then continued to complete the fabrication process. For example, referring again toFIGS. 3 through 6, a gate dielectric material134may be deposited or formed over the workpiece101, and a gate material136may be deposited over the gate dielectric material134. The gate dielectric material134may comprise an oxide material, a nitride material, silicon oxide, or a high dielectric constant (k) material having a dielectric constant of greater than about 3.9, as examples. The gate material136may comprise a conductive material such as a semiconductive material or a metal, as examples. Alternatively, the gate dielectric material134and the gate material136may comprise other materials.

The gate material136and the gate dielectric material134may be patterned, e.g., using lithography to form a gate136and a gate dielectric134of the transistors130and132. Sidewall spacers (not shown) comprising an insulating material may be formed over sidewalls of the gate136and the gate dielectric134, and the well regions106and108may be implanted with dopants to form semiconductive regions118and120of the source and drain regions124and126of the first and second transistors130and132, respectively. For example, if the first transistor130comprises a PFET and the second transistor132comprises an NFET, a source and drain region124comprising a p+ region118may be formed in the workpiece101of the first transistor130, and a source and drain region126comprising an n+ region120may be formed in the workpiece101of the second transistor132. The source and drain regions124and126may alternatively be formed by etching trenches in the workpiece101and filling the trenches with a semiconductive material118or120, for example. The semiconductive regions118and120, and/or the gates136may be silicided, by forming a metal layer over the workpiece101and heating the workpiece101, causing a portion of the atoms proximate the top surface of the semiconductive regions118and120and/or the gates136to combine with the metal of the metal layer, forming the silicide. Any excess remaining metal layer is then removed, leaving a top surface of a portion of the active area124/128aof the first transistor130and/or a top surface of a portion of the active area126/128bof the second transistor132comprising a silicide, not shown.

An insulating material may be formed over the workpiece101, and vias or contacts may be formed in the insulating material to make electrical contact to portions of the first and second transistors130and132, e.g., the source and drain regions124and126of transistor130and132, respectively, and/or the gate136regions. Conductive lines or contact pads may be coupled to and formed over the vias or contacts, not shown.

Embodiments of the present invention achieve technical advantages by providing novel structures for semiconductor devices100and novel methods of manufacture thereof. Embodiments of the present invention may be used to elevate or recess active areas124/128aof one or more transistors130in a first region102, but not other transistors132in a second region104of a workpiece101. In other embodiments, a different step height d1is formed in the first region102than is formed in the second region104, as shown in phantom at d2inFIGS. 9 and 10. Three or more regions102or104may also be manufactured, wherein different amounts of elevated or recessed active areas124/128aare formed in each region102or104, for example.

A plurality of different types of transistors130and132may be manufactured in a plurality of first regions102or second region104, for example. Transistors130and132comprising PFETs, NFETs, multiple gate transistors, high voltage transistors, low voltage transistors, and transistors having a variety of operating characteristics such as various current ratings, threshold voltages, and other parameters, may be formed in a plurality of the regions102and104. The elevation or recess of the active areas124/128a, e.g., the step heights d1and d2, of the various transistors130and132across the workpiece101may be varied according to the requirements for each type of transistor130and132, advantageously. Thus, embodiments of the present invention provide several methods of “tuning” the step heights d1and d2between active areas124/128aand126/128band portions of isolation regions110proximate the active areas124/128aand126/128baccording to the transistor130or132type.

One or more regions102may be formed on a semiconductor device100that have a positive or negative step height d1. A plurality of regions102having different step heights d1on a semiconductor device100may also be formed. Different step heights d1may be formed for transistors130in a plurality of regions102across a surface of a workpiece101, depending on the transistor130requirements, for example, optimizing performance of many or all types of transistors130on a semiconductor device100.

In some applications, the first transistors130in the first regions102described herein may comprise PFETs, as an example. In some applications, the first transistors130comprising the step height d1may comprise high voltage transistors, as another example. The first transistors130may comprise high voltage devices that are adapted to operate at a voltage of about +/−3.0 V or greater, for example. In some embodiments, the first transistors130may comprise low voltage transistors, as yet another example. The first transistors130may comprise low voltage devices that are adapted to operate at voltage levels of less than about +/−3.0 V, for example. Alternatively, the first transistors130may comprise other types of transistor devices than PFETs, such as NFETs, FinFETs, tri-gate FETs, other transistors, or static random access memory (SRAM) devices or other devices.

Embodiments of the present invention also include methods of manufacturing semiconductor devices100comprising CMOS devices and other types of devices manufactured using the methods described herein. For example, in one embodiment, a CMOS device100includes a workpiece101, and a first transistor130comprising a PFET130is disposed on the workpiece101. The PFET130includes a first active area124/128ain the workpiece101having a first height123. A second transistor132comprising an NFET132is also disposed on the workpiece101proximate the PFET130, wherein the NFET132includes a second active area126/128b. At least one isolation region110is disposed in the workpiece101proximate the PFET130and the NFET132, at least a portion of the at least one isolation region110having a second height at least proximate the PFET130, wherein the first height is greater than or less than the second height.

In another embodiment, a method of manufacturing a semiconductor device100comprising a CMOS device includes providing the workpiece101, forming the PFET130in the first region102, and forming the NFET132in the second region104. The method includes forming a plurality of isolation regions110in the workpiece101proximate the PFET130and the NFET132, at least a portion of the plurality of isolation regions110having a second height at least proximate the PFET130, wherein the first height of the active area of the PFET130is greater than the second height.

Advantages of embodiments of the present invention include providing novel methods of elevating active areas of one or more types of transistors such as first transistors130described herein, while not elevating active areas of other types of transistors such as second transistors132. Advantageously, the amount of the isolation region110recess (or elevation) may be tuned for the particular types of transistor130and132to achieve an amount of junction leakage for each type of transistor130or132. A step height d1may be created in some transistors130but not in other transistors132, using one or more of the methods described herein.

For example, higher performance CMOS devices may be fabricated using the methods described herein. As one example, PFETs130with improved performance may be achieved by recessing at least portions of isolation regions110proximate the PFETs130. The effective gate136width Weff, e.g., measured electrically, of the PFETs130may be increased or maximized due to the step height d1created by the increased amount of gate136material that is formed proximate the elevated active area. The “on” current Ionof the PFETs130may be increased as a result of the increased effective gate136width Weff, increasing the performance of the PFETs130.

A high leakage current of transistors such as NFETs132, which may have a high amount of junction leakage, particularly if an isolation region110proximate the NFETs132were to be recessed, is avoided by embodiments of the present invention, by not recessing isolation regions110proximate the NFETs132. Optimization between performance of the PFETs130and leakage current of NFETs132can thus be achieved by embodiments of the present invention described herein. Embodiments of the present invention advantageously allow separate tunability of isolation region110recesses to active areas for PFETs130and NFETs132.

In other embodiments, shown in phantom at127′ inFIGS. 9 and 10, a greater step height is formed in the active areas124/128aof the first transistors130in the first region102than in the step height formed in the active areas126/128bof the second transistors132in the second region104, for example. For example, the step height of the first active areas124/128acomprises a dimension d1that is greater than the step height of the second active areas126/128bcomprising dimension d2. The difference between dimensions d1and d2may comprise several nm or more, for example. Thus, embodiments of the present invention provide novel semiconductor device100designs and manufacturing methods wherein active areas124/128aof some transistors130protrude more away from top surfaces of isolation regions110than active areas126/128bof other transistors132protrude away from the top surfaces of the isolation regions110, for example.

After the manufacturing process steps described herein with respect toFIGS. 7 through 12, subsequent cleaning processes and/or etch processes may result in the top surfaces of the isolation regions110being lowered slightly. Thus, all of the embodiments described herein may result in semiconductor device100designs and manufacturing methods wherein active areas124/128aof some transistors130protrude more away from top surfaces of isolation regions110than active areas126/128bof other transistors132protrude away from the top surfaces of the isolation regions110, for example, which may be an advantage in some applications, because siliciding of top surfaces of the active areas124/128aand/or126/128bis facilitated.

Optimization of performance of different types or groups of first transistors130and second transistors132is achievable using embodiments of the present invention described herein. Embodiments of the present invention advantageously allow separate tunability of isolation region110recesses or elevated areas to active areas124/128aand126/128bof first transistors130and second transistors132in multiple regions102and104across a surface of a workpiece101. Some regions102may be treated and processed using the methods described herein differently than regions104are treated and processed, allowing the ability to select certain groups of types of transistors and devices wherein the active areas of the transistors and devices (e.g., in regions102) are elevated or recessed with respect to the active areas of transistors or devices in regions104.

The novel semiconductor devices100, CMOS devices, and manufacturing methods described herein are easily and inexpensively implementable into manufacturing process flows for semiconductor devices100. For example, the novel methods and structures described herein may easily be implemented into existing manufacturing process flows, lithography mask designs, and lithography tools and systems, with few additional processing steps being required for implementation of the invention.

Embodiments of the present invention also provide novel methods of forming one or more three-dimensional multiple gate transistors in some regions102of a workpiece101, as shown inFIG. 12. The multiple gate transistors130comprise vertical active areas124/128a, for example. The multiple gate transistors130may be formed in some regions, but not other regions104, of a workpiece101. Alternatively, the multiple gate transistors may be fabricated over an entire workpiece101, for example. Thus, FinFETs and other 3D multi-gate transistors may be formed on the same chip as planar transistors132are formed, advantageously.