Semiconductor package

A semiconductor package includes a first semiconductor chip comprising a semiconductor substrate and a redistribution pattern on a top surface of the semiconductor substrate, the redistribution pattern having a hole exposing an inner sidewall of the redistribution pattern, a second semiconductor chip on a top surface of the first semiconductor chip, and a bump structure disposed between the first semiconductor chip and the second semiconductor chip. The bump structure is disposed in the hole and is in contact with the inner sidewall of the redistribution pattern.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2020-0086234, filed on Jul. 13, 2020, in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND

Embodiments of the inventive concepts relate to a semiconductor package and, more particularly, to a semiconductor package including a bump structure.

Techniques of stacking semiconductor chips have been developed to improve integration densities and performance of semiconductor devices. For example, in a multi-chip package technique, a plurality of semiconductor chips may be mounted in a single semiconductor package. In a system-in-package technique, different kinds of semiconductor chips may be stacked in a single semiconductor package capable of operating as one system. A reduction in thickness of a semiconductor package may be required to miniaturize an electronic device. In addition, a semiconductor package may be required to have a heat dissipation property capable of effectively dissipating heat generated from stacked semiconductor chips in operation of the semiconductor package.

SUMMARY

Embodiments of the inventive concepts may provide a miniaturized semiconductor package.

Embodiments of the inventive concepts may also provide a semiconductor package capable of reducing a distance between stacked semiconductor chips and improving thermal properties.

In an aspect, a semiconductor package may include a first semiconductor chip comprising a semiconductor substrate and a redistribution pattern on a top surface of the semiconductor substrate, the redistribution pattern having a hole exposing an inner sidewall of the redistribution pattern, a second semiconductor chip on a top surface of the first semiconductor chip, and a bump structure disposed between the first semiconductor chip and the second semiconductor chip. The bump structure may be disposed in the hole and may be in contact with the inner sidewall of the redistribution pattern.

In an aspect, a semiconductor package may include a first semiconductor chip comprising a semiconductor substrate and a redistribution pattern disposed on a top surface of the semiconductor substrate, the redistribution pattern having a hole, a second semiconductor chip on a top surface of the first semiconductor chip, a solder pattern provided in the hole so as to be in contact with an inner sidewall of the redistribution pattern, and a pillar pattern disposed between the solder pattern and the second semiconductor chip.

In an aspect, a semiconductor package may include a package substrate, a first semiconductor chip mounted on the package substrate, a second semiconductor chip disposed on a top surface of the first semiconductor chip, and a bump structure disposed between the first semiconductor chip and the second semiconductor chip. The first semiconductor chip may include a first semiconductor substrate, a first circuit layer disposed on a bottom surface of the first semiconductor substrate and comprising first integrated circuits, a first through-structure disposed in the first semiconductor substrate, a first redistribution pattern disposed on a top surface of the first semiconductor substrate and connected to the first through-structure, a first protective layer on a top surface of the first redistribution pattern, and an upper insulating layer between the first semiconductor substrate and the first redistribution pattern. The second semiconductor chip may include a second semiconductor substrate, a second circuit layer disposed on a bottom surface of the second semiconductor substrate and comprising second integrated circuits, and a chip pad disposed on a bottom surface of the second circuit layer and electrically connected to the second integrated circuits. The first redistribution pattern may have a hole exposing an inner sidewall of the first redistribution pattern. The bump structure may include a solder pattern provided in the hole so as to be in contact with the inner sidewall of the first redistribution pattern, and a pillar pattern between the solder pattern and the chip pad of the second semiconductor chip.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The same reference numerals or the same reference designators may denote the same elements or components throughout the specification.

Semiconductor packages according to example embodiments of the inventive concepts will be described hereinafter.

FIG.1Ais a cross-sectional view illustrating a semiconductor package, according to example embodiments of the inventive concepts.FIG.1Bis an enlarged view of a region ‘I’ ofFIG.1A.FIG.1Cis a plan view illustrating arrangement of a bump structure, a first redistribution pattern and a through-structure, according to example embodiments of the inventive concepts.FIG.1Dis an enlarged view of a region ‘II’ ofFIG.1Aand corresponds to a cross-sectional view taken along a line III-III′ ofFIG.1C.

Referring toFIGS.1A,1B,1C, and1D, a semiconductor package may include a first semiconductor chip100, a second semiconductor chip200, and a bump structure300. The semiconductor package may further include a package substrate900and external terminals950. The package substrate900may include an insulating base layer910, substrate pads920, and internal interconnection lines930. The insulating base layer910may include a single layer or a plurality of layers. The substrate pads920may be exposed at a top surface of the package substrate900. Top surfaces of the substrate pads920may be coplanar with a top surface of the package substrate900. Otherwise, the top surfaces of the substrate pads920may be disposed at a different level from the top surface of the package substrate900. The internal interconnection lines930may be disposed in the insulating base layer910and may be connected to the substrate pads920. In the present specification, it will be understood that when a component is referred to as being “electrically connected” to another component, it may be connected directly to the other component or an intervening component may be present. In the present specification, it will be understood that when a component is referred to as being electrically connected to the package substrate900, it may be electrically connected to the internal interconnection line930. The substrate pads920and the internal interconnection lines930may include a metal such as copper, aluminum, tungsten, and/or titanium. For example, the package substrate900may be a printed circuit board having a circuit pattern. Alternatively, a redistribution layer may be used as the package substrate900. When the redistribution layer is used as the package substrate900, the insulating base layer910may include a photosensitive polymer or a photoimageable dielectric (PID) material. When the redistribution layer is used as the package substrate900, the internal interconnection lines930may include a seed layer and a metal layer on the seed layer.

The external terminals950may be provided on a bottom surface of the package substrate900and may be connected to the internal interconnection line930. For example, the external terminals950may be in contact with lower substrate pads940, which may be exposed at a bottom surface of the package substrate900. External electrical signals may be transmitted to the internal interconnection line930through the external terminal950. The external terminal950may include a solder ball. The external terminal950may include a metal such as a solder material. The solder material may include tin (Sn), silver (Ag), zinc (Zn), and/or any alloy thereof.

The terms “contact” or “in contact with,” as used herein, refer to a direct connection (i.e., touching) unless the context indicates otherwise. Terms such as “same,” “equal,” “planar,” or “coplanar,” as used herein when referring to orientation, layout, location, shapes, sizes, amounts, or other measures do not necessarily mean an exactly identical orientation, layout, location, shape, size, amount, or other measure, but are intended to encompass nearly identical orientation, layout, location, shapes, sizes, amounts, or other measures within acceptable variations that may occur, for example, due to manufacturing processes. The term “substantially” may be used herein to emphasize this meaning, unless the context or other statements indicate otherwise. For example, items described as “substantially the same,” “substantially equal,” or “substantially planar,” may be exactly the same, equal, or planar, or may be the same, equal, or planar within acceptable variations that may occur, for example, due to manufacturing processes.

The first semiconductor chip100may be mounted on the top surface of the package substrate900. The first semiconductor chip100may include a first semiconductor substrate110, a first circuit layer120, a first chip pad150, a first through-structure140, a first redistribution pattern160, and a first protective layer180. For example, the first semiconductor substrate110may include a semiconductor material such as silicon, germanium, or silicon-germanium. The first semiconductor substrate110may have a top surface110aand a bottom surface110bwhich are opposite to each other.

The first circuit layer120may be disposed on the bottom surface110bof the first semiconductor substrate110. The first circuit layer120may include a first insulating layer121, first integrated circuits123, and a first interconnection structure125, as illustrated inFIG.1B. The first integrated circuits123may be provided on the bottom surface110bof the first semiconductor substrate110. For example, the first integrated circuits123may include transistors. The first integrated circuits123may include a logic circuit, a memory circuit, and/or a combination thereof. The first insulating layer121may be disposed on the bottom surface110bof the first semiconductor substrate110and may cover the first integrated circuits123. Even though not shown in the drawings, the first insulating layer121may include a plurality of stacked layers. The first insulating layer121may include a silicon-containing insulating material. For example, the silicon-containing insulating material may include silicon oxide, silicon nitride, silicon oxynitride, and/or tetraethyl orthosilicate. The first interconnection structure125may be provided in the first insulating layer121. The first interconnection structure125may be electrically connected to the first integrated circuits123. In the present specification, it may be understood that when a component is referred to as being electrically connected to a semiconductor chip, it may be electrically connected to integrated circuits of the semiconductor chip. The first interconnection structure125may include an interconnection pattern and a via pattern connected to the interconnection pattern. The interconnection pattern may have a long axis extending in a direction parallel to the bottom surface110bof the first semiconductor substrate110. A long axis of the via pattern may be parallel to a direction intersecting the bottom surface110bof the first semiconductor substrate110. The via pattern may be disposed between a plurality of the interconnection patterns and may be connected to the interconnection patterns. A width of each of the interconnection patterns may be greater than a width of the via pattern connected directly thereto. The first interconnection structure125may include a metal such as copper, aluminum, titanium, or tungsten.

The first chip pad150may be exposed at a bottom surface of the first semiconductor chip100. The first chip pad150may be disposed on a bottom surface of the first circuit layer120. The first chip pad150may be electrically connected to the first integrated circuits123through the first interconnection structure125. The first chip pad150may include a different material from that of the first interconnection structure125. The first chip pad150may include a metal such as aluminum. The first chip pad150may be a plurality of chip pads150.

The first semiconductor chip100may further include a first lower insulating pattern130, as illustrated inFIG.1B. The first lower insulating pattern130may be provided on a bottom surface of the first insulating layer121and may cover an edge portion of the first chip pad150. For example, the first lower insulating pattern130may contact side surfaces of the first chip pads150, and the edge portion of a bottom surface of each first chip pad150. The first lower insulating pattern130may expose at least a portion of the first chip pad150. For example, the first lower insulating pattern130may expose a center portion of each first chip pad150. The first lower insulating pattern130may include an insulating polymer or a silicon-based insulating material.

The semiconductor package may further include a bonding bump350. As illustrated inFIG.1A, the bonding bump350may be disposed between the package substrate900and the first semiconductor chip100and may be electrically connected to the package substrate900and the first semiconductor chip100. For example, the bonding bump350may be connected to the substrate pad920and the first chip pad150. The bonding bump350may contact a top surface of the substrate pad920and a bottom surface of the first chip pad150. The bonding bump350may include a solder ball, a bump, or a pillar. The bonding bump350may include a conductive material. The bonding bump350may be a plurality of bonding bumps350.

The first through-structure140may be disposed in the first semiconductor substrate110. The first through-structure140may penetrate the top surface110aand the bottom surface110bof the first semiconductor substrate110. The first through-structure140may further penetrate at least a portion of the first circuit layer120. For example, the first through-structure140may further penetrate an upper portion of the first insulating layer121, as illustrated inFIG.1B. The first through-structure140may be electrically connected to at least one of the first chip pad150and the first integrated circuits123through the first interconnection structure125. The first through-structure140may be a plurality of first through-structures140, and each first through-structure140may be electrically connected to at least one corresponding first chip pad150.

InFIGS.1A and1D, the first redistribution pattern160may be disposed on the top surface110aof the first semiconductor substrate110. In the present specification, it may be understood that when a component is referred to as being “on” another component, it may be directly on the other component or an intervening component may be present. For example, in some embodiments, a first upper insulating layer170may further be disposed between the top surface110aof the first semiconductor substrate110and the first redistribution pattern160. The first upper insulating layer170may include a silicon-containing insulating material. Even though not shown in the drawings, the first upper insulating layer170may include a plurality of stacked layers. If the first redistribution pattern160is in direct contact with the top surface110aof the first semiconductor substrate110, bonding strength between the first redistribution pattern160and the first semiconductor substrate110may be relatively weak. However, according to the embodiments, the first redistribution pattern160may be stably fixed to the first semiconductor substrate110by the first upper insulating layer170.

The first redistribution pattern160may cover the first through-structure140. For example, one end portion of the first redistribution pattern160may be disposed on a top surface of the first through-structure140and may be in contact with the top surface of the first through-structure140. The first redistribution pattern160may be electrically connected to the first through-structure140. Thus, the first redistribution pattern160may be electrically connected to the first integrated circuits123and the package substrate900through the first through-structure140.

The first redistribution pattern160may have a first hole169, as illustrated inFIG.1D. The first hole169may penetrate a top surface of the first redistribution pattern160and may expose an inner sidewall160cof the first redistribution pattern160. The first hole169may further penetrate a bottom surface of the first redistribution pattern160to expose the first upper insulating layer170or the first semiconductor substrate110. The first hole169may not vertically overlap with the first through-structure140. In the present specification, the term “vertical” may mean “vertical to the top surface110aof the first semiconductor substrate110”. LikeFIG.1C, the first hole169may be spaced apart from the first through-structure140when viewed in a plan view. The first hole169may have a rounded quadrilateral shape when viewed in a plan view. The planar shape of the first hole169may be variously modified. For example, the first hole169may have an octagonal shape or a circular shape when viewed in a plan view.

The first redistribution pattern160may include a seed pattern161and a conductive pattern162. For example, the seed pattern161may include at least one of titanium or copper. The bottom surface of the first redistribution pattern160may mean a bottom surface of the seed pattern161. The conductive pattern162may be disposed on the seed pattern161, and may be in contact with a top surface of the seed pattern161. The conductive pattern162may include a metal such as copper, nickel, or any alloy thereof. The conductive pattern162may be formed by an electroplating process using the seed pattern161as an electrode. A thickness of the conductive pattern162may be greater than a thickness of the seed pattern161. Thickness may refer to the thickness or height measured in a direction perpendicular to the top surface110aof the first semiconductor substrate110. The top surface of the first redistribution pattern160may mean a top surface of the conductive pattern162. For the purpose of ease and convenience in illustration, the seed pattern161and the conductive pattern162of the first redistribution pattern160are not separately illustrated in other drawings exceptFIG.1D. However, the first redistribution pattern160may include the seed pattern161and the conductive pattern162in the other drawings.

The first protective layer180may be provided on the top surface110aof the first semiconductor substrate110. For example, the first protective layer180may cover the top surface and an outer sidewall of the first redistribution pattern160and a top surface of the first upper insulating layer170. The first protective layer180may contact the top surface and an outer sidewall of the first redistribution pattern160and a top surface of the first upper insulating layer170. The first protective layer180may be an organic insulating layer. For example, the first protective layer180may include a photosensitive polymer or a photoimageable dielectric material. For example, the photosensitive polymer or the photoimageable dielectric material may include at least one of photosensitive polyimide, polybenzoxazole, a phenol-based polymer, or a benzocyclobutene-based polymer. The first protective layer180may not extend into the first hole169of the first redistribution pattern160. The first protective layer180may not cover the inner sidewall160cof the first redistribution pattern160. The first protective layer180may have a first opening189. The first opening189may penetrate a top surface180aand a bottom surface of the first protective layer180. The first opening189may be connected to the first hole169. The first opening189may expose an inner sidewall180cof the first protective layer180. The inner sidewall180cof the first protective layer180may be coplanar with the inner sidewall160cof the first redistribution pattern160.

The second semiconductor chip200may be disposed on the first semiconductor chip100. A kind of the second semiconductor chip200may be different from a kind of the first semiconductor chip100. For example, the first semiconductor chip100may be a logic chip, and the second semiconductor chip200may be a memory chip. Alternatively, the kind of the second semiconductor chip200may be the same as the kind of the first semiconductor chip100. For example, each of the first and second semiconductor chips100and200may be a memory chip. As illustrated inFIG.1A, a width of the second semiconductor chip200may be equal to a width of the first semiconductor chip100. Alternatively, the width of the second semiconductor chip200may be different from the width of the first semiconductor chip100.

The second semiconductor chip200may include a second semiconductor substrate210, a second circuit layer220, and a second chip pad250. The second semiconductor substrate210may include at least one of the materials described as the examples of the first semiconductor substrate110. The second circuit layer220may be disposed on a bottom surface210bof the second semiconductor substrate210. The second circuit layer220may include a second insulating layer221, second integrated circuits223, and a second interconnection structure225, as illustrated inFIG.1D. The second integrated circuits223may be provided on the bottom surface210bof the second semiconductor substrate210. For example, the second integrated circuits223may include transistors. The second integrated circuits223may include a logic circuit, a memory circuit, and/or a combination thereof. The second insulating layer221may be provided on the bottom surface210bof the second semiconductor substrate210and may cover the second integrated circuits223. Even though not shown in the drawings, the second insulating layer221may include a plurality of stacked layers. The second insulating layer221may include a silicon-containing insulating material. The second interconnection structure225may be provided in the second insulating layer221. The second interconnection structure225may be electrically connected to the second integrated circuits223. The second interconnection structure225may include an interconnection pattern and a via pattern connected to the interconnection pattern. The interconnection pattern may have a long axis extending in a direction parallel to the bottom surface210bof the second semiconductor substrate210. A long axis of the via pattern may be parallel to a direction intersecting the bottom surface210bof the second semiconductor substrate210. The via pattern may be disposed between a plurality of the interconnection patterns and may be connected to the interconnection patterns. A width of each of the interconnection patterns may be greater than a width of the via pattern connected directly thereto. The second interconnection structure225may include a metal such as copper, aluminum, titanium, or tungsten.

The second chip pad250may be exposed at a bottom surface of the second semiconductor chip200. The second chip pad250may be disposed on a bottom surface of the second circuit layer220. The second chip pad250may be electrically connected to the second integrated circuits223through the second interconnection structure225. The second chip pad250may include a different material from that of the second interconnection structure225. For example, the second chip pad250may include a metal such as aluminum.

The second semiconductor chip200may further include a second lower insulating pattern230. The second lower insulating pattern230may be disposed on the bottom surface of the second circuit layer220and may expose the second chip pad250. The second lower insulating pattern230may cover an edge portion of the second chip pad250. For example, the second lower insulating pattern230may contact the bottom surface of the second circuit layer220, a side surface of the second chip pad250, and the edge portion of the bottom surface of the second chip pad250. The second lower insulating pattern230may include a silicon-based insulating material or an insulating polymer.

The bump structure300may be disposed between the first and second semiconductor chips100and200and may be electrically connected to the first and second semiconductor chips100and200. The bump structure300may include a solder pattern310and a pillar pattern320. The solder pattern310may be provided in the first hole169of the first redistribution pattern160and may cover the inner sidewall160cof the first redistribution pattern160. For example, the solder pattern310may be in contact with the inner sidewall160cof the first redistribution pattern160. The solder pattern310may also be provided in the first opening189of the first protective layer180and may be in contact with the inner sidewall180cof the first protective layer180. The solder pattern310may include tin (Sn), silver (Ag), zinc (Zn), and/or any alloy thereof. A bottom surface310bof the solder pattern310may correspond to a bottom surface of the bump structure300. The bottom surface310bof the solder pattern310may be disposed at a lower level than the top surface of the first redistribution pattern160. In the present specification, the term “level” may mean a vertical level. A difference in level between two surfaces may be measured in a direction perpendicular to the top surface110aof the first semiconductor substrate110. In some embodiments, the bottom surface310bof the solder pattern310may be coplanar with a bottom surface of the first redistribution pattern160. A shape of the bottom surface310band a sidewall of the solder pattern310may correspond to a shape of a bottom surface169band a sidewall of the first hole169. As illustrated inFIG.1C, a planar shape of the solder pattern310may correspond to the planar shape of the first hole169. The solder pattern310may have a rounded quadrilateral shape when viewed in a plan view. The planar shape of the solder pattern310may be variously modified. For example, the solder pattern310may have an octagonal shape or a circular shape when viewed in a plan view.

The pillar pattern320may be disposed between the solder pattern310and the second semiconductor chip200. For example, the pillar pattern320may be disposed between the solder pattern310and the second chip pad250and may be connected to the solder pattern310and the second chip pad250. A lower portion of the pillar pattern320may be surrounded by the solder pattern310. For example, a bottom surface320bof the pillar pattern320may be in contact with the solder pattern310. A sidewall of the lower portion of the pillar pattern320may be covered by the solder pattern310. For example, the sidewall of the lower portion of the pillar pattern320may be in contact with the solder pattern310. However, embodiments of the inventive concepts are not limited thereto. At least a portion of the pillar pattern320may be provided in the first opening189. For example, the bottom surface320bof the pillar pattern320may be disposed at a lower level than the top surface180aof the first protective layer180. Thus, a height A1of the bump structure300may be reduced. A width of the pillar pattern320may be substantially uniform. A top surface320aof the pillar pattern320may correspond to a top surface of the bump structure300. The pillar pattern320may include a conductive material such as copper. As illustrated inFIG.1C, the pillar pattern320may have a rounded quadrilateral shape when viewed in a plan view. Alternatively, the pillar pattern320may have an octagonal shape or a circular shape when viewed in a plan view. Electrical connection between the first and second semiconductor chips100and200and the bump structure300will be described hereinafter.

FIG.1Eis an enlarged view corresponding to the region ‘II’ ofFIG.1Ato illustrate a process of electrically connecting first and second semiconductor chips. InFIG.1E, the first integrated circuits and the first interconnection structure are omitted for the purpose of ease and convenience in illustration.

Referring toFIG.1E, a second semiconductor chip200may be prepared. The second semiconductor chip200may include the second semiconductor substrate210, the second circuit layer220, the second chip pad250, and the second lower insulating pattern230, as described above. At this time, a preliminary bump structure300P may be formed on the second chip pad250of the second semiconductor chip200. The preliminary bump structure300P may include a pillar pattern320and a preliminary solder pattern310P. The preliminary solder pattern310P may have a solder ball shape. For example, a lower portion of the preliminary solder pattern310P may have a shape such as a hemisphere. The second semiconductor chip200may be disposed on the first semiconductor chip100in such a way that the preliminary solder pattern310P is provided in the first hole169of the first redistribution pattern160. A reflow process of the preliminary solder pattern310P may be performed. The reflow process may be performed at a temperature equal to or higher than a melting point of the preliminary solder pattern310P. However, embodiments of the inventive concepts are not limited thereto. Even though a central axis of the preliminary bump structure300P may be offset from a central axis of the first hole169by a process error, since the preliminary solder pattern310P is provided in the first hole169, the solder pattern310may be in good contact with the inner sidewall160cof the first redistribution pattern160after completion of the reflow process. As a result, the bump structure300described inFIGS.1A to1Dmay be formed, and the first and second semiconductor chips100and200may be electrically connected to each other through the bump structure300. As illustrated inFIG.1A, the bump structure300may include a plurality of bump structures300laterally spaced apart from each other. The first hole169may include a plurality of first holes169separated from each other. If the first holes169are omitted, in the reflow process, a plurality of the preliminary solder patterns310P may have flowability and thus may come in contact with each other. In this case, an electrical short may occur between the bump structures300. However, according to the embodiments, the first holes169may physically isolate the preliminary solder patterns310P, respectively. Since each of the preliminary solder patterns310P is provided in a corresponding one of the first holes169, the preliminary solder patterns310P may not come in contact with each other even though they have flowability. Thus, it is possible to prevent occurrence of an electrical short between a plurality of the solder patterns310. As a result, reliability of the bump structure300and the semiconductor package including the same may be improved.

Referring again toFIGS.1A to1D, the bump structure300may be electrically connected to the first through-structure140through the first redistribution pattern160. Since the first redistribution pattern160is provided, the bump structure300and the first through-structure140may not be vertically aligned with each other. Thus, arrangement of the bump structure300and the first through-structure140may be freely designed.

A molding layer400may be disposed on the top surface of the package substrate900to cover the first semiconductor chip100and the second semiconductor chip200. UnlikeFIG.1A, in some embodiments, the molding layer400may cover sidewalls of the first and second semiconductor chips100and200but may expose a top surface of the second semiconductor chip200. The molding layer400may include an insulating polymer such as an epoxy molding compound (EMC).

A first underfill layer410may be provided in a first gap region between the package substrate900and the first semiconductor chip100to seal or surround the bonding bump350. The first underfill layer410may include an insulating polymer such as an epoxy molding compound (EMC). In some embodiments, the first underfill layer410may include a different material from that of the molding layer400.

A second underfill layer420may be provided in a second gap region between the top surface of the first semiconductor chip100and the bottom surface of the second semiconductor chip200. The second underfill layer420may seal or surround the bump structure300. The second underfill layer420may cover a sidewall of the pillar pattern320. The second underfill layer420may include an insulating polymer such as an epoxy molding compound (EMC). However, the second underfill layer420may include a different material from that of the molding layer400. For example, the insulating polymer of the second underfill layer420may have a different chemical structure, number average molecular weight, substituted group or composition ratio from that of the insulating polymer of the molding layer400.

If the first hole169and the first opening189are omitted, the bottom surface of the bump structure300may be disposed at the same level as or a higher level than the top surface180aof the first protective layer180. In this case, a distance A2between the first and second semiconductor chips100and200may be equal to or greater than the height A1of the bump structure300. However, according to the embodiments, since a portion of the bump structure300is provided in the first hole169, the distance A2between the first and second semiconductor chips100and200may be less than the height A1of the bump structure300. Thus, the distance A2between the first and second semiconductor chips100and200may be reduced, and a height of the semiconductor package may be reduced. Here, the distance A2between the first and second semiconductor chips100and200may be a distance between a bottom surface of the second lower insulating pattern230and the top surface180aof the first protective layer180disposed on the first redistribution pattern160. The distance A2between the first and second semiconductor chips100and200may be substantially equal to a thickness of the second underfill layer420. The thickness of the second underfill layer420may correspond to a thickness of the second underfill layer420disposed on the top surface180aof the first protective layer180disposed on the first redistribution pattern160. In other words, the thickness of the second underfill layer420may be measured at a position vertically overlapping with the first redistribution pattern160. The height A1of the bump structure300may be defined as a distance between the top surface320aof the pillar pattern320and the bottom surface310bof the solder pattern310. The thickness of the second underfill layer420may be less than the distance between the top surface320aof the pillar pattern320and the bottom surface310bof the solder pattern310.

If the height A1of the bump structure300is greater than 30 μm, a height of the semiconductor package may be increased. In some embodiments, the height A1of the bump structure300may range from about 5 μm to about 30 μm.

If the distance A2between the first and second semiconductor chips100and200is greater than 20 μm, it may be difficult to miniaturize a semiconductor package. In some embodiments, the distance A2between the first and second semiconductor chips100and200may range from about 3 μm to about 20 μm. Thus, the semiconductor package may be further miniaturized.

A sum of a depth of the first hole169and a depth of the first opening189may substantially correspond to a difference between the height A1of the bump structure300and the distance A2between the first and second semiconductor chips100and200. The sum of the depth of the first hole169and the depth of the first opening189may be a difference A3in level between the top surface180aof the first protective layer180and the bottom surface169bof the first hole169. If the difference A3in level between the top surface180aof the first protective layer180and the bottom surface169bof the first hole169is less than 2 μm, a sufficient reduction in height of the semiconductor package may be difficult even though the bump structure300is disposed in the first hole169. If the difference A3in level between the top surface180aof the first protective layer180and the bottom surface169bof the first hole169is greater than 20 μm, a sum of thicknesses of the first redistribution pattern160and the first protective layer180may be too great. In this case, it may be difficult to reduce a height of the first semiconductor chip100. However, according to some embodiments, the difference A3in level between the top surface180aof the first protective layer180and the bottom surface169bof the first hole169may range from about 2 μm to about 10 μm. Thus, the height (or thickness) of the semiconductor package may be reduced.

The second underfill layer420may have a relatively low thermal conductivity. For example, the thermal conductivity of the second underfill layer420may be lower than a thermal conductivity of the bump structure300. Particularly, the thermal conductivity of the second underfill layer420may be lower than a thermal conductivity of the solder pattern310and a thermal conductivity of the pillar pattern320. The thermal conductivity of the second underfill layer420may be lower than a thermal conductivity of the first redistribution pattern160, a thermal conductivity of the first through-structure140, a thermal conductivity of the second chip pad250, and a thermal conductivity of the second interconnection structure225. As the thickness of the second underfill layer420increases, a heat dissipation property of the semiconductor package may be deteriorated. For example, if the thickness of the second underfill layer420is greater than 20 μm, the heat dissipation property of the semiconductor package may be deteriorated. However, according to the embodiments, since the thickness of the second underfill layer420is reduced, heat generated from the first semiconductor chip100in operation of the semiconductor package may be rapidly released or dissipated to the outside. The thickness of the second underfill layer420may range from about 3 μm to about 20 μm. Thus, thermal properties of the semiconductor package may be improved.

FIG.2Ais a view illustrating a bump structure and a first redistribution pattern according to example embodiments of the inventive concepts.FIG.2Ais an enlarged view corresponding to the region ‘II’ ofFIGS.1A and1sa cross-sectional view corresponding to the line ofFIG.1C. Hereinafter, the descriptions to the same components and/or features as in the above embodiments will be omitted for the purpose of ease and convenience in explanation.

Referring toFIG.2A, a semiconductor package may include a first semiconductor chip100, a second semiconductor chip200, and a bump structure300. The first semiconductor chip100may include a first semiconductor substrate110, a first through-structure140, a first upper insulating layer170, a first redistribution pattern160, and a first protective layer180. The first redistribution pattern160may be substantially the same as described with reference toFIGS.1A to1D. However, a first hole169may penetrate the top surface of the first redistribution pattern160but may not penetrate the bottom surface160bof the first redistribution pattern160. A bottom surface169bof the first hole169may be provided in the first redistribution pattern160. The bottom surface169bof the first hole169may be at a higher level than the bottoms bottom surface160bof the first redistribution pattern160. Thus, the bottom surface169bof the first hole169may expose the first redistribution pattern160. A difference A3in level between the top surface180aof the first protective layer180and the bottom surface169bof the first hole169may range from about 2 μm to about 10 μm.

The bump structure300may include a solder pattern310and a pillar pattern320, and the solder pattern310may be provided in the first hole169of the first redistribution pattern160so as to be in contact with the bottom surface169bof the first hole169and the inner sidewall160cof the first redistribution pattern160. For example, a bottom surface310band a sidewall of the solder pattern310may be in contact with the first redistribution pattern160. A contact area between the solder pattern310and the first redistribution pattern160may be increased, and thus the solder pattern310may be better electrically connected to the first redistribution pattern160. The bottom surface310bof the solder pattern310may be disposed at a higher level than the bottom surface160bof the first redistribution pattern160. The solder pattern310may be spaced apart from the first upper insulating layer170.

FIG.2Bis a view illustrating a first redistribution pattern and a first protective layer according to example embodiments of the inventive concepts.FIG.2Bis an enlarged view corresponding to the region ‘II’ ofFIGS.1A and1sa cross-sectional view corresponding to the line ofFIG.1C. Hereinafter, the descriptions to the same components and/or features as in the above embodiments will be omitted for the purpose of ease and convenience in explanation.

Referring toFIG.2B, a semiconductor package may include a first semiconductor chip100, a second semiconductor chip200, and a bump structure300.

A first protective layer180may have a first opening189. A width of the first opening189may be greater than a width of the first hole169. For example, the width of the first opening189at the bottom surface of the first protective layer180may be greater than the width of the first hole169at the top surface160aof the first redistribution pattern160. Thus, the first opening189may expose the top surface160aof the first redistribution pattern160and the inner sidewall180cof the first protective layer180. The inner sidewall180cof the first protective layer180may not be aligned with the inner sidewall160cof the first redistribution pattern160. The first hole169and the first opening189may be formed by different processes.

A solder pattern310may fill the first hole169and may be in contact with the inner sidewall160cof the first redistribution pattern160. The solder pattern310may also be provided in the first opening189. The solder pattern310may extend onto the exposed top surface160aof the first redistribution pattern160and the inner sidewall180cof the first protective layer180. Thus, a sidewall of the solder pattern310may have a stepped shape.

FIG.2Cis a view illustrating a semiconductor package according to example embodiments of the inventive concepts.FIG.2Cis an enlarged view corresponding to the region ‘II’ ofFIGS.1A and1sa cross-sectional view corresponding to the line ofFIG.1C. Hereinafter, the descriptions to the same components and/or features as in the above embodiments will be omitted for the purpose of ease and convenience in explanation.

Referring toFIG.2C, a semiconductor package may include a first semiconductor chip100, a second semiconductor chip200, and a bump structure300. The first semiconductor chip100may include a first semiconductor substrate110, a first through-structure140, a first upper insulating layer170, a first redistribution pattern160, and a first protective layer180and may further include a first lower redistribution pattern163and a first lower protective layer183. The first semiconductor substrate110, the first through-structure140, the first upper insulating layer170, the first redistribution pattern160and the first protective layer180may be substantially the same as described with reference toFIGS.1A to1D. However, the first redistribution pattern160may not be in direct contact with the first through-structure140.

The first lower redistribution pattern163may be disposed between the top surface110aof the first semiconductor substrate110and the first redistribution pattern160. For example, the first lower redistribution pattern163may be disposed between the first upper insulating layer170and the first redistribution pattern160. The first lower redistribution pattern163may be disposed on the first through-structure140and may be in contact with the first through-structure140. The first lower redistribution pattern163may include substantially the same material as the first redistribution pattern160.

The first lower protective layer183may be disposed on the first lower redistribution pattern163and the first upper insulating layer170to cover the first lower redistribution pattern163and the first upper insulating layer170. The first lower protective layer183may be an organic insulating layer. For example, the first lower protective layer183may include a photosensitive polymer or a photoimageable dielectric material. The first lower protective layer183may include the same material as the first protective layer180, and an interface between the first protective layer180and the first lower protective layer183may not be visible or distinguished. However, embodiments of the inventive concepts are not limited thereto.

A conductive pattern165may be provided in the first lower protective layer183and may penetrate the first lower protective layer183. The conductive pattern165may be disposed on the first lower redistribution pattern163and may be connected to the first lower redistribution pattern163. The conductive pattern165may include, for example, a metal.

The first redistribution pattern160may be disposed on the first lower protective layer183and the conductive pattern165. For example, the first redistribution pattern160may contact top surfaces of the first lower protective layer183and the conductive pattern165. The first redistribution pattern160may be spaced apart from the first upper insulating layer170. The first redistribution pattern160may be connected to the first through-structure140through the conductive pattern165and the first lower redistribution pattern163. The first redistribution pattern160may have a first hole169. The bump structure300may be provided in the first hole169, and the solder pattern310may be in contact with the inner sidewall160cof the first redistribution pattern160. The first lower redistribution pattern163may not have the first hole169. The bump structure300may be spaced apart from the first lower redistribution pattern163.

In certain embodiments, the first lower redistribution pattern163may include a plurality of stacked first lower redistribution patterns163, and the first lower protective layer183may include a plurality of stacked first lower protective layers183. In this case, the first lower protective layers183may be disposed between the first lower redistribution patterns163.

FIG.2Dis a view illustrating electrical connection of a bump structure and a first through-structure according to some embodiments of the inventive concepts.FIG.2Dis an enlarged view corresponding to the region ‘II’ ofFIGS.1A and1sa cross-sectional view corresponding to the line ofFIG.1C. Hereinafter, the descriptions to the same components and/or features as in the above embodiments will be omitted for the purpose of ease and convenience in explanation.

Referring toFIG.2D, a semiconductor package may include a first semiconductor chip100, a second semiconductor chip200, and a bump structure300. The first semiconductor chip100may include a first semiconductor substrate110, a first through-structure140, a first upper insulating layer170, a first redistribution pattern160, and a first protective layer180and may further include a first lower redistribution pattern163, a first lower protective layer183, and a conductive pattern165. The first through-structure140, the first redistribution pattern160, the first protective layer180, the first lower redistribution pattern163, the first lower protective layer183, and the conductive pattern165may be substantially the same as described with reference toFIG.2C.

However, the first lower protective layer183may have a lower opening188. The lower opening188may penetrate a top surface and a bottom surface of the first lower protective layer183and may be connected to the first hole169of the first redistribution pattern160. The first lower redistribution pattern163may have a lower hole168. The lower hole168may penetrate a top surface of the first lower redistribution pattern163. The lower hole168may be connected to the first hole169and the first opening189through the lower opening188.

The bump structure300may be provided in the first opening189, the first hole169, the lower opening188, and the lower hole168. The solder pattern310may be in contact with an inner sidewall163cof the first lower redistribution pattern163and the inner sidewall160cof the first redistribution pattern160. The solder pattern310may be electrically connected to the first through-structure140through the first redistribution pattern160and the first lower redistribution pattern163. The solder pattern310may also cover an inner sidewall of the first lower protective layer183and the inner sidewall of the first protective layer180.

In the embodiments ofFIGS.2A to2D, the semiconductor package may further include at least one of the package substrate900, the molding layer400, the first underfill layer410, and the bonding bump350, described in the embodiments ofFIGS.1A to1D. The first semiconductor chip100may further include the first circuit layer120and the first lower insulating pattern130. The embodiments ofFIGS.1A to1D, the embodiments ofFIG.2A, the embodiments ofFIG.2B, the embodiments ofFIG.2C, and the embodiments ofFIG.2Dmay be combined with each other. For example, inFIGS.2B and2C, the first hole169penetrates the top surface and the bottom surface of the first redistribution pattern160. Alternatively, the first hole169may penetrate the top surface of the first redistribution pattern160but may not penetrate the bottom surface of the first redistribution pattern160. In this case, the bottom surface of the first hole169may be disposed in the first redistribution pattern160, and the bottom surface and the sidewall of the solder pattern310may be in contact with the first redistribution pattern160.

In the semiconductor packages ofFIGS.2A to2D, a height of the bump structure300, a distance between the first and second semiconductor chips100and200, a thickness of the second underfill layer420, and a difference in level between the top surface of the first protective layer180and the bottom surface of the first hole169may satisfy the conditions described above in the embodiments ofFIGS.1A to1D.

FIG.3is a cross-sectional view illustrating a semiconductor package according to example embodiments of the inventive concepts. The present embodiments will be described with reference toFIGS.3and1D, and the descriptions to the same components and/or features as in the above embodiments will be omitted for the purpose of ease and convenience in explanation.

Referring toFIG.3, a semiconductor package may include a package substrate900, a first semiconductor chip100, a plurality of second semiconductor chips200, and a plurality of bump structures300. The semiconductor package may further include a plurality of external terminals950, a molding layer400, a first underfill layer410, and a plurality of second underfill layers420. The semiconductor package may be a three-dimensional (3D) stack package.

The first semiconductor chip100may be mounted on the package substrate900. The first semiconductor chip100may include a first semiconductor substrate110, a first circuit layer120, a first lower insulating pattern130, a first through-structure140, a first redistribution pattern160, and a first protective layer180.

The plurality of second semiconductor chips200may be mounted on a top surface of the first semiconductor chip100. The second semiconductor chips200may be laterally spaced apart from each other. In the present specification, the term “laterally” may mean “in a direction parallel to a top surface110aof the first semiconductor substrate110”. A kind of the second semiconductor chips200may be different from a kind of the first semiconductor chip100. For example, a size, a function and/or the number of input/output (I/O) terminal(s) of the second semiconductor chip200may be different from that (those) of the first semiconductor chip100. The I/O terminal may be a chip pad. In some embodiments, a width of each of the second semiconductor chips200may be less than a width of the first semiconductor chip100. Each of the second semiconductor chips200may perform a different function from that of the first semiconductor chip100. For example, the first semiconductor chip100may be a logic chip, and the second semiconductor chips200may be memory chips. The memory chips may include volatile memory chips such as DRAM chips or SRAM chips. Alternatively, the memory chips may include non-volatile memory chips such as NAND flash memory chips. Each of the second semiconductor chips200may include a second semiconductor substrate210, a second circuit layer220, and second chip pads250, as described in the embodiments ofFIGS.1A to1D. The second semiconductor chip200may further include a second lower insulating pattern230.

The bump structures300may be disposed between the first semiconductor chip100and the second semiconductor chips200. Each of the second semiconductor chips200may be connected to the first semiconductor chip100and the package substrate900through the bump structures300. Each of the bump structures300may include a solder pattern310and a pillar pattern320. The solder pattern310may be provided in the first hole169of the first redistribution pattern160and may be in contact with the inner sidewall160cof the first redistribution pattern160. Thus, the semiconductor package may be miniaturized, and thermal properties of the semiconductor package may be improved. A pitch P1of a plurality of the pillar patterns320may be less than a pitch P2of a plurality of the external terminals950.

The second underfill layers420may be respectively disposed in second gap regions between the first semiconductor chip100and the second semiconductor chips200to seal or surround the bump structures300.

The molding layer400may cover sidewalls of the first and second semiconductor chips100and200but may expose top surfaces of the second semiconductor chips200. Alternatively, the molding layer400may also cover the top surfaces of the second semiconductor chips200.

The semiconductor package may further include a heat dissipation structure700. The heat dissipation structure700may be disposed on the top surfaces of the second semiconductor chips200and a top surface of the molding layer400. In some embodiments, the heat dissipation structure700may further extend onto a sidewall of the molding layer400. The heat dissipation structure700may include a heat sink, a heat slug, or a thermal interface material (TIM) layer. The heat dissipation structure700may include, for example, a metal.

FIG.4Ais a cross-sectional view illustrating a semiconductor package according to example embodiments of the inventive concepts.FIG.4Bis an enlarged view of a region ‘IV’ ofFIG.4A. Hereinafter, the descriptions to the same components and/or features as in the above embodiments will be omitted for the purpose of ease and convenience in explanation.

Referring toFIGS.4A and4B, a semiconductor package may include a package substrate900, external terminals950, an interposer substrate800, interposer bumps850, a chip stack1000, a third semiconductor chip500, and a molding layer400. The package substrate900may be substantially the same as described with reference toFIGS.1A to1D. A plurality of the external terminals950may be provided on a bottom surface of the package substrate900.

The interposer substrate800may be disposed on the package substrate900. The interposer substrate800may include metal pads820and metal interconnection lines830. The metal pads820may be exposed at a top surface of the interposer substrate800. The metal interconnection lines830may be provided in the interposer substrate800and may be connected to the metal pads820. In the present specification, it may be understood that when a component is referred to as being electrically connected to the interposer substrate800, it may be electrically connected to the metal interconnection line830. The metal pads820and the metal interconnection lines830may include a metal such as copper, aluminum, tungsten, and/or titanium. The interposer bumps850may be disposed between the package substrate900and the interposer substrate800and may be connected to the package substrate900and the interposer substrate800. For example, the interposer bumps850may be connected to the substrate pads920and the metal interconnection lines830. each of the interposer bumps850may include a solder ball. The interposer bumps850may include a metal such as a solder material.

The chip stack1000may be mounted on the top surface of the interposer substrate800. The chip stack1000may include a first semiconductor chip100, a second semiconductor chip200, and a plurality of bump structures300. The first semiconductor chip100may be mounted on the top surface of the interposer substrate800. The first semiconductor chip100may include a first semiconductor substrate110, first chip pads150, a first circuit layer120, first through-structures140, first redistribution patterns160, and a first protective layer180. The first semiconductor chip100may further include a first lower insulating pattern130, as inFIG.1B. Bonding bumps350may be disposed between the interposer substrate800and the first semiconductor chip100. The bonding bumps350may be disposed between the metal pads820and the first chip pads150and may be connected to the metal pads820and the first chip pads150.

The second semiconductor chip200may be disposed on a top surface of the first semiconductor chip100. The bump structures300may be disposed between the first and second semiconductor chips100and200. Each of the bump structures300may be substantially the same as described above. For example, the solder pattern310may be provided in the first hole169and may be in direct contact with the inner sidewall160cof the first redistribution pattern160, as illustrated inFIG.4B. Thus, a height of the chip stack1000may be reduced.

The second semiconductor chip200may include a plurality of stacked second semiconductor chips200. A kind of the second semiconductor chips200may be different from a kind of the first semiconductor chip100. For example, the first semiconductor chip100may be one of a logic chip, a buffer chip, and a system-on-chip (SOC), and the second semiconductor chips200may be a different one of a logic chip, a memory chip, a buffer chip, and a system-on-chip (SOC). In the present specification, the memory chip may include a high bandwidth memory (HBM) chip. For an example, the first semiconductor chip100may be the logic chip, and the second semiconductor chips200may be the HBM chips.

Hereinafter, the second semiconductor chips200will be described in detail. Each second semiconductor chip200may include a second semiconductor substrate210, a second circuit layer220, and second chip pads250, as described in the embodiments ofFIGS.1A to1D. Each second semiconductor chip200may further include second through-structures240, second redistribution patterns260, a second upper insulating layer270, and a second protective layer280. The second through-structures240, the second upper insulating layer270, the second redistribution patterns260, and the second protective layer280may be substantially the same as the first through-structures140, the first upper insulating layer170, the first redistribution patterns160, and the first protective layer180described in the embodiments ofFIGS.1A to1D, respectively. For example, the second upper insulating layer270may be disposed on a top surface of the second semiconductor substrate210. The second upper insulating layer270may include a silicon-based insulating material. The second through-structures240may be disposed in the second semiconductor substrate210. The second through-structures240may penetrate the second semiconductor substrate210and the second upper insulating layer270. As illustrated inFIG.4B, the second through-structures240may further penetrate an upper portion of the second insulating layer221of the second circuit layer220and may be connected to the second interconnection structures225of the second circuit layer220. The second through-structures240may be electrically connected to at least one of the second chip pads250and the second integrated circuits223through the second interconnection structures225.

The second redistribution pattern260may be disposed on the top surface of the second semiconductor substrate210and may be connected to the second through-structure240. For example, the second redistribution pattern260may cover the second upper insulating layer270and may be in contact with top surfaces of the second through-structures240. Each second redistribution pattern260may have a second hole269. The second hole269may expose an inner sidewall260cof the second redistribution pattern260.

The second protective layer280may be provided on the second redistribution patterns260. The second protective layer280may have second openings289, and each second opening289may be connected to a corresponding one of the second holes269. UnlikeFIG.4B, a width of a bottom end of the second opening289may be greater than a width of a top end of the second hole269. In this case, the second opening289may expose a top surface of the second redistribution pattern260and an inner sidewall of the second protective layer280. In this case, the inner sidewall of the second protective layer280may not be coplanar with the inner sidewall260cof the second redistribution pattern260. A difference in level between a top surface of the second protective layer280and a bottom surface of the second hole269may range from about 2 μm to about 10 μm.

Even though not shown in the drawings, the second semiconductor chip200may further include a second lower redistribution pattern and a second lower protective layer. The second lower redistribution pattern and the second lower protective layer may be substantially the same as the first lower redistribution pattern163and the first lower protective layer183described in the embodiments ofFIG.2C or2D, respectively.

An uppermost second semiconductor chip200may not include the second through-structures240, the second redistribution patterns260, and the second protective layer280. Each of the second semiconductor chips200may further include a second lower insulating pattern230, as illustrated inFIG.4B.

Hereinafter, electrical connection between the plurality of second semiconductor chips200through the bump structures300will be described. Other bump structures300may be disposed between the second semiconductor chips200. The second semiconductor chips200may include a lower semiconductor chip and an upper semiconductor chip which are adjacent to each other. Here, the upper semiconductor chip may be disposed on a top surface of the lower semiconductor chip. In the bump structure300between the lower semiconductor chip and the upper semiconductor chip, the solder pattern310may be provided in the second hole269of the lower semiconductor chip and may be in contact with the inner sidewall260cof a corresponding second redistribution pattern260. Thus, a thickness of the chip stack1000and a thickness of the semiconductor package may be reduced. For example, a distance A4between the second semiconductor chips200may be less than a height A1of a corresponding bump structure300. The corresponding bump structure300may correspond to the bump structure300between the second semiconductor chips200adjacent to each other. The distance A4between the second semiconductor chips200may be a distance between the top surface of the second protective layer280on the second redistribution pattern260of the lower semiconductor chip and a bottom surface of the second lower insulating pattern230of the upper semiconductor chip. The distance A4between the second semiconductor chips200may range from about 3 μm to about 20 μm. The height A1of the bump structure300may range from about 5 μm to about 30 μm.

A bottom surface of the solder pattern310may be in contact with the second upper insulating layer270. In certain embodiments, the bottom surface of the second hole269may be disposed in the second redistribution pattern260. In this case, the bottom surface of the solder pattern310may be connected to the second redistribution pattern260. The solder pattern310may be connected to the second through-structure240through the second redistribution pattern260of the lower semiconductor chip. The pillar pattern320may be connected to the second chip pad250of the upper semiconductor chip. Thus, the upper semiconductor chip and the lower semiconductor chip may be electrically connected to each other.

As illustrated inFIG.4A, a pitch P1of a plurality of the pillar patterns320may be less than a pitch P2of the external terminals950. The pitch P1of the pillar patterns320may be less than a pitch P3of a plurality of the interposer bumps850.

The semiconductor package may further include a first underfill layer410, a second underfill layer420, a third underfill layer430, and a fourth underfill layer440. The first underfill layer410and the second underfill layer420may be substantially the same as described with reference toFIGS.1A to1D.

The third underfill layer430may be disposed in a third gap region between the second semiconductor chips200. For example, the third underfill layer430may be disposed between the second semiconductor chips200to seal or surround a corresponding bump structures300. The distance between the second semiconductor chips may be substantially equal to a thickness of a corresponding third underfill layer430. The thickness of the third underfill layer430may be less than the height A1of the corresponding bump structure300. For example, the thickness of the third underfill layer430may range from about 3 μm to about 20 μm. The thickness of the third underfill layer430may be equal to a distance between the bottom surface of the second lower insulating pattern230of the upper semiconductor chip and the top surface of the second protective layer280on the second redistribution pattern260of the lower semiconductor chip. The third underfill layer430may include an insulating polymer. For example, the third underfill layer430may include an epoxy-based polymer.

The third semiconductor chip500may be mounted on the top surface of the interposer substrate800. The third semiconductor chip500may be laterally spaced apart from the chip stack1000. The third semiconductor chip500may include a central processing unit (CPU) or a graphic processing unit (GPU). Connection bump360may be provided between chip pads of the third semiconductor chip500and corresponding metal pads820. each of the connection bumps360may include at least one of a solder ball or a pillar. The connection bumps360may include a metal such as a solder material. The third semiconductor chip500may be electrically connected to the first semiconductor chip100, the second semiconductor chips200and/or the external terminals950through the connection bumps360and the metal interconnection lines830.

The fourth underfill layer440may be disposed in a fourth gap region between the interposer substrate800and the third semiconductor chip500. The fourth underfill layer440may seal or surround the connection bump360. The fourth underfill layer440may include an epoxy-based polymer.

The molding layer400may cover sidewalls of the first and second semiconductor chips100and200and a sidewall of the third semiconductor chip500. The molding layer400may expose a top surface of an uppermost one of the second semiconductor chips200and a top surface of the third semiconductor chip500. Alternatively, the molding layer400may also cover the top surface of the uppermost second semiconductor chip200and/or the top surface of the third semiconductor chip500. The molding layer400may include an epoxy-based polymer. In some embodiments, the molding layer400may include a different material from that of the first to fourth underfill layers410,420,430and440.

The semiconductor package may further include a heat dissipation structure700. The heat dissipation structure700may be disposed on the top surface of the uppermost second semiconductor chip200, the top surface of the third semiconductor chip500, and a top surface of the molding layer400. In some embodiments, the heat dissipation structure700may further extend onto a sidewall of the molding layer400.

In the semiconductor package ofFIG.3and the semiconductor package ofFIGS.4A and4B, the package substrate900, the molding layer400, the first underfill layer410, and the second underfill layer420may be substantially the same as described in the embodiments ofFIGS.1A to1D. The first semiconductor substrate110, the first circuit layer120, the first through-structures140, the first redistribution patterns160, the first protective layer180, and the bump structures300may be substantially the same as described in the embodiments ofFIGS.1A to1D. In certain embodiments, the first redistribution patterns160and the bump structures300may be substantially the same as described in the embodiments ofFIG.2A. In certain embodiments, the first redistribution patterns160and the first protective layer180may be substantially the same as described in the embodiments ofFIG.2B. In certain embodiments, the first semiconductor chip100may further include the first lower redistribution pattern and the first lower protective layer, as described in the embodiments ofFIG.2C or2D.

According to the embodiments of the inventive concepts, the bump structure may be disposed between the first semiconductor chip and the second semiconductor chip. The first semiconductor chip may include the first redistribution pattern having the first hole. The bump structure may be disposed in the first hole and may be in contact with the inner sidewall of the first redistribution pattern. The bottom surface of the bump structure may be disposed at a lower level than the top surface of the first redistribution pattern. Thus, the distance between the first and second semiconductor chips may be reduced, and the semiconductor package may be miniaturized.

Since the bump structure is disposed in the first hole, occurrence of an electrical short between the bump structures may be inhibited or prevented. The thickness of the underfill layer between the first and second semiconductor chips may be reduced, and thus the heat dissipation property of the semiconductor package may be improved.