A multi-processor according to an example of the invention comprises a first control unit which stores first compressed data acquired externally in a first memory, a hardware decoding unit which decodes the first compressed data stored in the first memory and storing the decoded data in a second memory, an encoding processor element which includes at least one of a plurality of processor elements, encodes the decoded data stored in the second memory in accordance with encoding software stored in a third memory, and stores second compressed data obtained by encoding the decoded data in a fourth memory, and a second control unit which outputs the second compressed data stored in the fourth memory to the outside.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2007-145264, filed May 31, 2007, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a multi-processor including a plurality of processor elements.

2. Description of the Related Art

Patent reference 1 (Jpn. Pat. Appln. KOKAI Publication No. 2004-356850) discloses a compressed moving image encoding apparatus including a software unit which decompresses compressed moving image data by software, a data storage unit which stores the moving image data processed by the software processing unit, and a hardware processing unit which performs compression processing for moving image data in the data storage unit by using hardware.

Patent reference 2 (Jpn. Pat. Appln. KOKAI Publication No. 2001-27986) discloses a data processing apparatus including a software processing unit which implements predetermined data processing by using software, and a hardware processing unit which implements predetermined data processing by using hardware.

Patent reference 3 (Jpn. Pat. Appln. KOKAI Publication No. 2000-115277) discloses an arrangement including a first codec formed by hardware and a second codec which performs encoding/decoding by executing software.

Patent reference 4 (Jpn. Pat. Appln. KOKAI Publication No. 9-84004) discloses a technique of using microprocessors capable of parallel processing to process a portion including many complicated computations and using hardware including a block loader or a VLC decoder to perform processing which is relatively simple but is essentially difficult to parallelize.

Patent reference 5 (Jpn. Pat. Appln. KOKAI Publication No. 2005-70938) discloses a signal processing apparatus which implements a high throughput and high flexibility by load distribution using software and hardware in signal processing using an image compression/decompression algorithm with a large processing amount.

With the recent popularization of terrestrial digital broadcasting and BS high-definition broadcasting, video data associated with these broadcastings are processed by DVD recorders, personal computers, and the like. The number of software applications for processing video data such as terrestrial digital broadcasting and BS high-definition broadcasting data may tend to increase.

When a personal computer performs transcodec of converting video data compressed in a given format into video data compressed in another format, since the CPU (Central Processing Unit) performs processing for transcodec, the load concentrates on the CPU. The transcodec includes a decoding processing for encoded data encoded by a method such as mpeg2, H.264, or the like, and an encoding processing for decoded data by the decoding processing such as exchanging a specific format, bit rate, resolution, or the like.

When the CPU intensively processes transcodec, the processing speed of another software application executed by the CPU may decrease. In addition, as the load is applied to the CPU, it may become difficult to execute transcodec itself in real time.

When a GPU (Graphics Processing Unit) is to perform transcodec, since the GPU is essentially a processor for computer graphics processing, the cost effectiveness of the processing to be executed decreases. In addition, as systems which handle video data, systems which use the video output functions of a chip set and include no GPU are widely used.

BRIEF SUMMARY OF THE INVENTION

A multi-processor according to the first example of the present invention comprises a first control unit which stores first compressed data acquired externally in a first memory, a hardware decoding unit which decodes the first compressed data stored in the first memory and storing the decoded data in a second memory, an encoding processor element which includes at least one of a plurality of processor elements, encodes the decoded data stored in the second memory in accordance with encoding software stored in a third memory, and stores second compressed data obtained by encoding the decoded data in a fourth memory, and a second control unit which outputs the second compressed data stored in the fourth memory to the outside.

A multi-processor according to the second example of the present invention comprises a first control unit which stores first compressed data acquired externally in a first memory, a hardware decoding unit which decodes the first compressed data stored in the first memory and stores decoded data in a second memory, an editing processor element which includes at least one of a plurality of processor elements, and generates edited data by editing the decoded data stored in the second memory in accordance with editing software stored in a third memory, an encoding processor element which includes at least one of the plurality of processor elements, encodes the edited data generated by the editing processor element in accordance with encoding software stored in a fourth memory, and stores second compressed data obtained by encoding in a fifth memory, and a second control unit which outputs the second compressed data stored in the fifth memory to the outside.

A multi-processor according to the third example of the present invention comprises a first control unit which stores first compressed data acquired externally in a first memory, a hardware decoding unit which decodes the first compressed data stored in the first memory and stores decoded data in a second memory, an editing processor element which includes at least one of a plurality of processor elements, and generates edited data by editing the decoded data stored in the second memory in accordance with editing software stored in a third memory, a hardware encoding unit which encodes the edited data generated by the editing processor element and stores second compressed data obtained by encoding in a fourth memory, and a second control unit which outputs the second compressed data stored in the fourth memory to the outside.

DETAILED DESCRIPTION OF THE INVENTION

The embodiments of the present invention will be described below with reference to the views of the accompanying drawing. Note that the same reference numerals denote parts having similar functions in the following views of the drawing, and a repetitive description will be omitted.

First Embodiment

This embodiment exemplifies a multi-processor which decodes (decompresses) compressed video data by hardware, because video data is often compressed in a fixed format, and flexibly encodes video data by software using a programmable processor element (e.g., a DSP: Digital Signal Processor) which can convert data into formats corresponding to various devices.

FIG. 1is a block diagram showing an example of the multi-processor according to this embodiment.

A multi-processor1has an arrangement in which a hardware decoding unit2, a hardware decoding unit3, a plurality of processor elements4ato4d, a high-speed general-purpose interface (PCIe I/F)5such as PCI Express, a memory interface6, a control processor7, a data transfer unit (DMAC: Direct Memory Access Controller)8, and the like are connected to each other through an internal bus (Interconnect Network)9.

The general-purpose interface5exchanges data with an external device10via a bus11.

The memory interface (memory controller)6is connected to memories12ato12ewhich are used by the hardware decoding units2and3and the processor elements4ato4d.

The memories12ato12erespectively store compressed video data13areceived by the multi-processor1, video data13bobtained by decoding the compressed video data13a, compressed video data13cobtained by editing/compressing the video data13b, editing software13d, and encoding software13e. Note that the memories12ato12ecan be arbitrarily combined with each other. For example, the memories12ato12ecan be implemented by one memory.

At least one of the memories12ato12emay store various contents such as an operating system used for the control processor7which controls the processor elements4ato4d, referred image data in the decoding executing, and the like.

The control processor7is a processor which controls the hardware decoding units2and3, the processor elements4ato4d, the data transfer unit8, and the like.

The data transfer unit8performs data transfer between the general-purpose interface5and the memory interface6.

The hardware decoding unit2comprises hardware which decodes data compressed in the first format (e.g., mpeg2/mpeg1).

The hardware decoding unit3comprises hardware which decodes data compressed in the second format (e.g., H.264/VC1).

The processor elements4ato4dcan perform parallel operation under the control of the control processor7. At least one of the processor elements4ato4dexecutes the editing software13din the memory12din accordance with the control processor7to generate edited data.

At least one of the processor elements4ato4dexecutes the encoding software13ein the memory12ein accordance with the control processor7, and encodes various types of data such as the decoded video data13bor edited data.

This embodiment exemplifies the case in which the multi-processor1comprises the four processor elements4ato4d, the number of processor elements incorporated in the multi-processor1can be arbitrarily changed as long as the number of processor elements is two or more.

That is, in the multi-processor1, the hardware decoding unit2or3which is hardware decodes data, and the encoding software13eoperating on at least one of the processor elements4ato4dencodes data.

The resolution of video data and the number of formats are fixedly set by, for example, the specifications of terrestrial digital broadcasting, satellite digital broadcasts, cable television, HD-DVD, and Blu Ray. In this embodiment, therefore, the hardware decoding unit2or3which is hardware decodes the compressed video data13a. In general, implementing a given process by using hardware will reduce the chip area.

There are various types of apparatuses which play back compressed video data, including, for example, cellular phones, portable video players, DVD recorders, game machines and computer systems. No unified resolution or format is set for such various types of playback apparatuses for compressed video data. In many cases, the manufacturers of the respective products freely determine resolutions and formats. In the multi-processor1according to this embodiment, therefore, in order to flexibly encode video data in accordance with the format of a playback apparatus for the compressed video data, the processor elements4ato4dperform encoding of video data by using the encoding software13e.

The encoding software13ecan be updated, and hence can cope with changes in the specifications of the playback apparatus for compressed video data or encoding after the multi-processor1is shipped out.

Processing by the multi-processor1having the above arrangement will be described with reference toFIGS. 2 to 5.

FIG. 2is a block diagram showing an example of operation up to storing the compressed video data13ain the memory12aupon receiving it in this embodiment (first step).

The control processor7controls the data transfer unit8. The data transfer unit8transfers the compressed video data (compressed video stream)13a, received by the general-purpose interface5from the external device10via the bus11, to the memory interface6via the internal bus9. The memory interface6stores the compressed video data13ain the memory12a.

More specifically, the control processor7supplies a transfer source address, a transfer destination address, a transfer data size, and a transfer instruction to the data transfer unit8. The data transfer unit8stores the transfer source address, the transfer destination address, and the transfer data size in the internal register. In accordance with the contents of this register, the data transfer unit8transfers the compressed video data13afrom the general-purpose interface5to the memory interface6via the internal bus9, and stores the compressed video data13ain the memory12a.

FIG. 3is a block diagram showing an example of operation up to decoding the compressed video data13aand storing the decoded video data13bin the memory12b(second step). AlthoughFIG. 3exemplifies the case in which the hardware decoding unit2is used, the same applies to a case in which the hardware decoding unit3is used.

The control processor7controls the hardware decoding unit2. The hardware decoding unit2acquires the compressed video data13astored in the memory12avia the memory interface6and the internal bus9, decodes the compressed video data13a, and stores the decoded video data13bin the memory12bvia the internal bus9and the memory interface6.

More specifically, the control processor7supplies a read address, a write address, and a decode instruction to the hardware decoding unit2. The hardware decoding unit2stores the read address and the write address in the internal register. In accordance with the contents of this register, the hardware decoding unit2reads out the compressed video data13afrom the memory12aand writes the decoded video data13bin the memory12b.

FIG. 4is a block diagram showing an example of operation up to editing the decoded video data13b, encoding edited video data, and storing the encoded video data in the memory12c(third step).

The control processor7controls at least one of the processor elements4ato4d(inFIG. 4, the processor elements4ato4d). At least one of the processor elements4ato4daccesses the editing software13dstored in the memory12dand the encoding software13estored in the memory12evia the memory interface6and the internal bus9, acquires the decoded video data13bstored in the memory12b, edits the decoded video data13bby operation based on the editing software13d, encodes the edited data by operation based on the encoding software13e, and stores the compressed video data13cobtained by encoding the edited data in the memory12cvia the internal bus9and the memory interface6.

More specifically, the control processor7selects at least one of the processor elements4ato4d(inFIG. 4, the processor elements4ato4d) which executes the editing software13dand the encoding software13e. As this selection technique, the control processor7can use a technique of selecting one of the processor elements4ato4dwhich is in a standby state in which no processing is executed or whose processing amount is small. Note that the control processor7can execute the editing software13dand the encoding software13eby using all the processor elements4ato4dwithout selecting at least one of specific processor elements. It suffices to execute the editing software13dand the encoding software13eby using either the same processor element or different processor elements.

The control processor7supplies a read address, a write address, an edit instruction, and an encode instruction to the selected processor elements4ato4d. The selected processor elements4ato4deach store the read address and the write address in the internal register. In accordance with the contents of the register, each of the selected processor elements4ato4dreads out the decoded video data13bfrom the memory12b, and writes the compressed video data13cobtained by editing and encoding in the memory12c.

FIG. 5is a block diagram showing an example of operation of transferring the compressed video data13cstored in the memory12cto the external device10(fourth step).

The control processor7controls the data transfer unit8. The data transfer unit8transfers the compressed video data13cstored in the memory12cto the general-purpose interface5via the memory interface6and the internal bus9. The general-purpose interface5transmits the compressed video data13cto the external device10via the bus11.

More specifically, the control processor7supplies a transfer source address, a transfer destination address, a transfer data size, and a transfer instruction to the data transfer unit8. The data transfer unit8stores the transfer source address, the transfer destination address, and the transfer data size in the internal register. In accordance with the contents of this register, the data transfer unit8transfers the compressed video data13cto the general-purpose interface5via the memory interface6and the internal bus9, and transmits the compressed video data13cto the external device10via the bus11.

FIG. 6is a block diagram showing an application example of the multi-processor1according to this embodiment.FIG. 6exemplifies a case in which the multi-processor1is incorporated in a computer system14.

In this embodiment, the computer system14comprises a CPU15, a memory16, a GPU17, a memory/processor control connection unit18, an I/O control connection unit19, and the multi-processor1.

The computer system14acquires data from a USB20a, an audio device20b, a network20c, an HDD or DVD20d, and a tuner20e, and supplies data to the USS20a, the audio device20b, the network20c, and HDD or DVD20d.

The memory/processor control connection unit18and the memory16are connected to each other via a bus21ahaving a bandwidth (transfer rate) of, for example, 8 GBytes/sec.

The memory/processor control connection unit18and the GPU17are connected to each other via a bus21bhaving a bandwidth of, for example, 4 GBytes/sec.

The memory/processor control connection unit18and the CPU15are connected to each other via a bus21chaving a bandwidth of, for example, 8 GBytes/sec.

The memory/processor control connection unit18and the I/O control connection unit19are connected to each other via a bus21dhaving a bandwidth of, for example, 1 GByte/sec.

The I/O control connection unit19and the multi-processor1are connected to each other via the bus11having a bandwidth of, for example, 1 GByte/sec.

Data transfer is performed with a bandwidth of, for example, 100 MBytes/sec between the I/O control connection unit19and the USB20aand between the I/O control connection unit19and the audio device20b.

Data transfer is performed with a bandwidth of, for example, 250 MBytes/sec between the I/O control connection unit19and the network20c, between the I/O control connection unit19and the HDD or DVD20d, and between the I/O control connection unit19and the tuner20e.

The I/O control connection unit19is a chip which connects the devices20ato20eand other constituent elements of the computer system14.

The memory/processor control connection unit18connects the memory16, the CPU15, and the GPU17.

The operation of the computer system14will be described below.

The I/O control connection unit19receives the compressed video data13afrom the USB20a, the audio device20b, the network20c, the HDD or DVD20d, or the tuner20e, and transfers the compressed video data13ato the multi-processor1via the bus11.

The multi-processor1receives the compressed video data13a, decodes the data by the internal hardware, executes necessary editing processing by using the editing software13d, encodes the edited data by using the encoding software13e, generates the compressed video data13cin the format handled by the computer system14, and transfers the compressed video data13cto the I/O control connection unit19via the bus11.

The I/O control connection unit19transfers the compressed video data13cto the memory/processor control connection unit18via the bus21d.

The memory/processor control connection unit18transfers the compressed video data13cto one of the CPU15, the memory16, and GPU17via one of the buses21c,21a, and21b.

Upon receiving the compressed video data13c, the CPU15decodes the compressed video data13cby using a decoding function15a. The CPU15then stores decoded video data22in the memory16via the bus21c, the memory/processor control connection unit18, and the bus21a.

Upon receiving the compressed video data13c, the GPU17decodes the compressed video data13cby using a decoding function17a. The GPU17then performs processing for outputting the decoded video data22.

Note that the GPU17may store the decoded video data22in the memory16via the bus21b, the memory/processor control connection unit18, and the bus21a. The GPU17may output the video data22decoded by the CPU15.

The memory16stores, for example, the compressed video data13cor the video data22obtained by decoding the compressed video data13c, and software used by the CPU15, the GPU17, and the like.

In contrast, the I/O control connection unit19receives compressed video data from one of the CPU15, the memory16, and the GPU17via one of the buses21c,21a, and21b, the memory/processor control connection unit18, and the bus21d. The I/O control connection unit19transfers this received compressed video data to the multi-processor1via the bus11.

The multi-processor1receives the compressed video data, internally decodes the data, executes necessary editing processing, compresses the edited data again, and transfers the compressed video data to the I/O control connection unit19via the bus11.

The I/O control connection unit19outputs this compressed video data to one of the USB20a, the audio device20b, the network20c, and the HDD or DVD20d.

One of data transferred from one of the CPU15, the memory16, and the GPU17to the multi-processor1and data transferred from the multi-processor1to one of the CPU15, the memory16, and the GPU17may not be compressed.

As described above, in the computer system14, for data transfer between the CPU15and the memory/processor control connection unit18, between the memory16and the memory/processor control connection unit18, and between the GPU17and the memory/processor control connection unit18, a bandwidth of 8 CBytes/sec or 4 GBytes/sec is set.

In contrast to this, for data transfer between the memory/processor control connection unit18and the I/O control connection unit19and between the I/O control connection unit19and the multi-processor1, a bandwidth of 1 GByte/sec are set.

That is, the bandwidth for data transfer between the CPU15and the memory/processor control connection unit15, between the memory16an the memory/processor control connection unit15, and between the GPU17and the memory/processor control connection unit15are larger than the bandwidth for data transfer between the memory/processor control connection unit18and the I/O control connection unit19and between the I/O control connection unit19and the multi-processor1.

Assume that video data is to be transferred along the route of the I/O control connection unit19, bus21d, memory/processor control connection unit18, bus21a, and memory16. In this case, although the bus21dbetween the memory/processor control connection unit18and the I/O control connection unit19has a bandwidth of 1 GByte/sec, since it is necessary to allow data transfer of other data between the memory/processor control connection unit18and the I/O control connection unit19during the transfer of this video data, the bus21dcannot use the entire bandwidth of 1 GByte/sec for the transfer of the video data. If a limitation is imposed on the bandwidth at the time of transfer of video data, it sometimes becomes difficult to ensure the real time performance of the video data.

In this embodiment, however, since the compressed video data13cis transferred between the memory/processor control connection unit18and the I/O control connection unit19, data transfer can be performed with a margin left on the bandwidth of the bus in the computer system14. This makes it possible to ensure the real time performance of even video data with a large data size.

That is, in this embodiment, since compressed video data is transferred on the bus21din the computer system14, even if data transfers overlap one another, data transfer can be done while the real time performance is ensured.

The above effects are described in detail. For example, the bandwidth required for conventional NTSC data transfer was 320 (width)×240 (height)×3 (colors)×60 (frame/sec)=about 15 MBytes/sec. When, however, video data for high-definition broadcasting is to be handled, a bandwidth of 1920 (width)×1080 (height)×3 (colors)×60 (frame/sec)=about 180 MBytes/sec is required. In order to transfer video data for high-definition broadcasting in one direction and the other direction of a bus, a bandwidth of about 360 MBytes/sec is required. In practice, since it is necessary to transfer control information and the like as well, a larger bandwidth is required.

For example, a bus conforming to the first specification defined such that the number of slots is one (×1) and the bandwidth is 133 MBytes/sec or a bus conforming to the second specification defined such that the number of slots is one (×1) and the bandwidth is 250 MBytes/sec lacks in bandwidth when transferring high-definition broadcasting video data with the above size.

For example, a bus conforming to the second specification defined such that the number of slots is four (×4) has a bandwidth of 1 GByte/sec. However, this bus has a data transfer efficiency of 60% to 70% in a normal state, and one data transfer may overlap another data transfer. This makes it impossible to transfer video data by using the entire bandwidth of 1 GByte/sec. data size of the encoded data encoded by the method such as mpeg2, H.264, or the like, is less than 30 Mbps at the high-definition broadcasting. data transfer rate of the encoded data encoded by the method such as mpeg2, H.264, or the like, is about 4 MBytes/sec and less than 10 MBytes/sec at the high-definition broadcasting

In the computer system14including the multi-processor1according to this embodiment, since video data is transferred upon being compressed in a format corresponding to the computer system14, it is possible to output even large-volume data such as video data for high-definition broadcasting while ensuring its real time performance.

In the multi-processor1according to this embodiment, at least one of the processor elements4ato4d, hardware decoding unit2, and hardware decoding unit3generates the compressed video data13cby decoding, editing, and encoding the compressed video data13a. However, it suffices to execute processing (transcodec) of converting compressed video data in a given format into compressed video data in another format, as in a case in which data compressed by mpeg2 is converted into data compressed by H.264, without executing editing processing.

In this embodiment, editing processing includes, for example, extracting a highlight scene of a sport program and a specific feature of a news program by using an image processing technique and a sound processing technique. In this case, based on sound changes or breaks, telops of video data, and the like, editing processing is performed to extract, from the video data, data which exceeds a predetermined number of times of playback, data of a portion where the sound volume increases, data having a given feature, video data of a specific person based on facial recognition, and the like.

In addition, editing processing can be the processing of converting video data into data corresponding to an output device, e.g., changing the number of pixels or resolution.

Furthermore, editing processing can be the processing of implementing a user interface, for example, extracting feature points from video data and performing input control on the basis of the gesture of a user included in the video data.

In this embodiment, hardware executes fixed processing (processing that is relatively low in possibility or frequency of being changed), e.g., decoding compressed video data for terrestrial digital broadcasting, decoding compressed video data for BS high-definition broadcasting, and decoding compressed video data stored in a recording medium such as a DVD or a hard disk.

In contrast to this, in this embodiment, one of the processor elements4ato4dexecutes, by using software, processing whose main processing contents are fixed but part of which changes depending on an application, e.g., the processing of performing encoding itself in accordance with predetermined processing contents while changing part of processing contents in accordance with an output destination. More specifically, processor elements operate on the basis of software to implement the processing of encoding data into H.264 data and storing it in, for example, a hard disk or DVD, the processing of encoding data into mpeg2 data and storing it in, for example, a DVD, the processing of executing bit rate conversion of data to mpeg2 data to reduce its volume, and the processing of encoding data into mpeg4 data and storing it in, for example, a portable game machine or portable music player.

Likewise, one of the processor elements executes editing processing such as facial recognition processing, feature point extraction, sound recognition, and telop (character) recognition by using software.

The multi-processor1according to this embodiment does not have any video output function and uses the chip set function. Since the multi-processor1is not equipped with any texture unit or rastorizer for computer graphics processing, the chip area can be reduced as compared with a GPU. Using the multi-processor1makes it unnecessary to use any GPU for transcodec. This allows the GPU to perform processing to be essentially performed and can improve the cost effectiveness of the chip.

The multi-processor1according to this embodiment can efficiently execute transcodec, and can perform data transfer while ensuring the real time performance of video data.

Second Embodiment

The second embodiment exemplifies a modification of the multi-processor1according to the first embodiment described above.

FIG. 7is a block diagram showing an example of the multi-processor according to this embodiment.

A multi-processor23is almost the same as the multi-processor1inFIG. 1but is different from it in that it further includes a hardware encoding unit24.

In the multi-processor23, operation up to storing decoded video data13bin a memory12bupon receiving compressed video data13aby a general-purpose interface5is the same as that in the multi-processor1according to the first embodiment.

In the multi-processor23, a control processor7controls at least one of processor elements4ato4d. At least one of the processor elements4ato4daccesses editing software13dstored in the memory12d, and acquires the decoded video data13bstored in the memory12b. This processor element then edits the decoded video data13bby operation based on the editing software13d, and transfers the edited data to the hardware encoding unit24.

The control processor7controls the hardware encoding unit24. The hardware encoding unit24encodes edited data and stores compressed video data13cobtained by encoding in a memory12c.

The control processor7controls a data transfer unit8. The data transfer unit8transmits the compressed video data13cstored in the memory12cfrom the general-purpose interface5to the outside.

The multi-processor23according to this embodiment described above also executes encoding by hardware. Using the multi-processor23according to this embodiment can obtain the same effects as those of the first embodiment. The multi-processor23is suitable for encoding as well as decoding when encoding is fixed processing, and can increase the processing speed.

Third Embodiment

The third embodiment will be described, referring to the case where multi processor1or23described in relation to the foregoing embodiments is provided for a television.

FIG. 8is a block diagram showing an example of a television provided with a multi processor according to the third embodiment.

The television25comprises an antenna26, a decoder unit27, a display unit28, and a memory29. The memory29may be incorporated in the television25; alternatively, it may be embodied as an external memory. The decoder unit27is made of a decoder chip, for example. The display unit28is made of an LCD panel, for example.

The television25further comprises a multi processor30and a memory32. The television25may incorporate the multi processor30; alternatively, it may employ an external element as the multi processor30.

A description will now be given of how the structural elements operate where the television25is not provided with the multi processor30or does not use the multi processor30.

The antenna26receives an encoded data stream. The encoded data stream is, for example, data on terrestrial digital broadcasting, or the like.

The decoder unit27decodes an encoded data stream received by the antenna26, and the decoded data stream is transmitted to the display unit28.

The display unit28performs image display on the basis of the decoded data stream.

A description will be given of the case where the television25is provided with the multi processor30and this multi processor30is used.

The decoder unit27has a software transfer function27aof transmitting software31from the memory29to the multi processor30.

The multi processor30records the received software31in the memory32, and activates the software31.

The antenna26receives an encoded data stream. The transfer destination switching function27bof the decoder unit27permits the encoded data stream received by the antenna26to be transmitted to the multi processor30.

The multi processor30decodes the encoded data stream. The multi processor30executes processing based on the software31with respect to the decoded data stream. The multi processor30encodes the processed data stream. Then, the multi processor30transmits the encoded data stream to the decoder unit27. The memory32is used when the multi processor30executes processing based on the software31, decode processing and encode processing.

The processing based on the software31includes processing for increasing or decreasing a frame rate, IP conversion processing, resolution conversion processing, and various kinds of image processing such as image frame-interpolation processing.

The decoder unit27decodes the encoded data stream received from the multi processor30and transmits the decoded data stream to the display unit28.

The display unit28performs image display on the basis of the decoded data stream.

FIG. 9is a block diagram showing an example of the multi processor30provided for the television25.

The multi processor30includes an interface33, a bus34, a DMAC35, a hardware-decoder36, a hardware-encoder37, and processor elements (processor engines)38a-38dsuch as a digital signal processor (DSP).

The data transfer between the decoder unit27and the interface33is executed, using a band which is narrower than that used by the data transfer performed inside the multi processor30or that used by the data transfer performed between the bus34and the memory32.

The memory32is a memory used by the processor elements38a-38d, the hardware-decoder36and the hardware-encoder37.

The DMAC35controls the data transfer performed between the structural elements of the multi processor30through the use of the bus34. In addition, the DMAC35controls the data transfer performed between the memory32and the structural elements of the multi processor30through the use of the bus34.

The software31is supplied from the decoder unit27to the memory32by way of the interface33and the bus. The software31is stored in the memory32.

The encoded data stream is supplied from the decoder unit27to the memory32by way of the interface33and the bus34. The encoded data stream is stored in the memory32.

The hardware-decoder36reads the encoded data stream from the memory32by way of the bus34, decodes the read data stream, and supplies the decoded data stream to the memory32through the bus34. The decoded data stream is stored in the memory32.

The processor elements38a-38dread the software31from the memory32through the use of the bus34, and executes the read software31. The processor elements38a-38dexecute image processing with respect to the decoded data stream stored in the memory32. The processor elements38a-38dsupplies the processed data stream to the memory32by way of the bus34. The processed data stream is stored in the memory32.

The hardware-encoder37receives the processed data stream which is supplied thereto from the memory32through the bus34. The hardware-encoder37encodes the processed data stream. The hardware-encoder37supplies the encoded data stream to the memory32by way of the bus34. The encoded data stream is stored in the memory32.

The encoded data stream34stored in the memory32is transmitted to the decoder unit27by way of the bus34and the interface33.

In the third embodiment, the encoded data stream is transferred from the decoder unit27to the multi processor30. The multi processor30decodes the encoded data stream and records it in the memory32.

The processor elements38a-38dprocess the decoded data stream, encode the processed data stream, and supply the encoded data stream back to the decoder unit27. Owing to this feature, the third embodiment can save the transmission band which may be required between the decoder unit27and the multi processor30. In addition, various kinds of processing can be executed with respect to the data stream.

The third embodiment is advantageous in that various image processing functions can be realized by using a narrow-band bus (which is only required to enable transmission of an encoded data stream) and by additionally employing the multi processor30and the memory32.

In the third embodiment, the multi processor30encodes a data stream once again after image processing, and then supplies the encoded data stream back to the decoder unit27.

Owing to this feature, the decoder unit27can uniformly handle both the encoded data stream received from the antenna26and the encoded data stream received from the multi processor30. For example, the encoded data stream received from the antenna26and the encoded data stream received from the multi processor30can be in the form of mpeg2 TS format, in which case the decoder unit27decodes a data stream of the mpeq2 TS format.

In the third embodiment, software may be used for the switching the multi processor31between the mode in which the hardware-decoder36is used and the mode in which the hardware-encoder37is used. In addition, the multi processor30may be configured to receive data stream which has not yet been encoded. Furthermore, the multi processor30may be configured to transmit a processed data stream to a decoder unit without encoding the processed data stream.

The above embodiments exemplify the cases in which the data handled by the multi-processors1and23and the computer system14are video data. However, the present invention can be applied to other data in the same manner.

In addition, the multi-processor1or23can be provided for devices such as a DVD recorder as well as being applied to the computer system14such as a personal computer.

The multi-processors1and23according to the respective embodiments can temporarily store edited data and encode the edited data stored in the memory upon accessing it.

In the multi-processors1and23according to the respective embodiments, the operations of the control processor7and data transfer unit8may be implemented by processor elements.