Method of manufacturing semiconductor device and semiconductor device

Reliability of a semiconductor device is improved. Each of a plurality of terminals formed on a chip mounting surface included in a wiring substrate has a shape in which a narrow width portion is arranged between adjacent wide width portions in plan view. Moreover, a center of a tip end surface of each of a plurality of protruding electrodes formed on a semiconductor chip mounted on the wiring substrate is arranged at a position where it overlaps the narrow width portion in plan view, and the plurality of terminals and the plurality of protruding electrodes are electrically connected to each other via a solder member.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority from Japanese Patent Application No. 2012-286078 filed on Dec. 27, 2012, the content of which is hereby incorporated by reference into this application.

TECHNICAL FIELD OF THE INVENTION

The present invention relates to a semiconductor device and a manufacturing technique thereof, and, for example, relates to a technique effectively applied to a semiconductor device in which a protruding electrode of a semiconductor chip is connected to a terminal on a substrate via a solder member.

BACKGROUND

Japanese Patent Application Laid-Open Publication No. 2000-77471 (Patent Document 1) describes a mounting method (flip-chip mounting system) in which a bump electrode made of gold formed on a semiconductor chip and a connection pad of a wiring substrate are connected to each other via a solder member.

SUMMARY

The inventors of the present application have studied about a so-called flip-chip connection system in which a wiring substrate and a semiconductor chip are electrically connected to each other via a plurality of protruding electrodes formed on an electrode forming surface of the semiconductor chip.

In the flip-chip mounting system, a plurality of protruding electrodes formed on a plurality of pads of a semiconductor chip and a plurality of terminals (bonding leads) formed on a chip mounting surface of a wiring substrate are electrically connected to each other via a connection member (bonding member) such as a solder member. However, when a layout pitch between terminals (such as the protruding electrodes) adjacent to each other is shortened, existence of a problem has been found out in a viewpoint of reliability of the connection between the protruding electrodes and the terminals.

The above and other preferred aims and novel characteristics will be apparent from the description of the present specification and the accompanying drawings.

A method of manufacturing a semiconductor device according to one embodiment is to provide a configuration in which a narrow width portion is arranged between adjacent wide width portions in plan view in each of a plurality of terminals formed on a chip mounting surface of a wiring substrate. Moreover, a method of manufacturing a semiconductor device according to one embodiment is to electrically connect between the terminals and a plurality of protruding electrodes via a solder member so that center of a tip surface of each of the protruding electrodes formed on a semiconductor chip overlaps the narrow width portion in plan view.

According to the one embodiment, reliability of the semiconductor device can be improved.

DETAILED DESCRIPTION

(Explanation of Description Format, Basic Term, and Usage in Present Application)

In the present application, aspects will be described in a plurality of sections for convenience when required as a matter of convenience. However, these sections are not separately independent from each other unless otherwise stated, and the one of each part of a single example relates to a detailed part, a part of, or the entire of the other as a modification example and others regardless of the context of the description. Also, the repetitive descriptions of the same parts are omitted. Further, each component in the aspects is dispensable unless otherwise stated, when being logically limited to the number thereof, and except the case where the number is apparently limited to a specific number from the context.

Similarly, in the description of the aspects or others, when “formed of A” or others is described for materials, compositions, or others, components other than A are not eliminated unless otherwise or except the case where they are apparently not so from the context. For example, when referring to components, “X containing A as a main component” or others is meant. For example, even when referring to “silicon member” or others, this is not limited to pure silicon, and it is needless to say that this also includes SiGe (silicon germanium) alloy, multi metal alloy containing other-type silicon as a main component, and a member containing other additive and others. In addition, even when referring to gold plating, Cu layer, nickel-plating, and others, they include not only pure components but also members containing gold, Cu, nickel, and others as a main component, respectively, unless otherwise stated or except the case where they are apparently not so.

Further, when referring to the specific number and amount, range, and the like), the number may be larger or smaller than the specific number unless otherwise stated, the case where the number is logically limited to the specific number, or except the case where the number is apparently limited to a specific number from the context.

Still further, in each drawing of the embodiments, the same or similar parts are denoted by the same or similar reference symbols or reference numbers, and the description thereof is not repeated.

Still further, in the present application, terms of an upper surface and a lower surface are sometimes used. However, there are various aspects as mounting aspects of the semiconductor package, and therefore, for example, the upper surface may be arranged below the lower surface in some cases after the semiconductor package is mounted. In the present application, a plane on an element formation surface side of a semiconductor chip is referred to as a front surface, and a plane on an opposite side to the front surface is referred to as a rear surface. Moreover, a plane on a chip mounting surface side of a wiring substrate is referred to as the upper surface or the front surface, and a plane positioned on an opposite side to the upper surface is referred to as the lower surface.

Moreover, in the accompanying drawings, hatching or others is omitted even in a cross-sectional surface in some cases in which it makes the drawings more complicated or in which a space is clearly distinguished. With reference to this, a background contour line is omitted even in a closed hole in plan view in some cases in which it is clear from explanations or others. Further, hatching or a dot pattern is applied even not in a cross-sectional surface in order to clearly indicate that the corresponding portion is not the space or to clearly indicate a border of a region.

First Embodiment

Semiconductor Device

FIG. 1is a plan view illustrating the entire structure of a chip mounting surface side of a semiconductor device of the present embodiment.FIG. 2is a cross-sectional view taken along a line A-A ofFIG. 1. Moreover,FIG. 3is a plan view illustrating a front surface side (a surface facing a wiring substrate) of the semiconductor chip illustrated inFIG. 1. Further,FIG. 4is a plan view illustrating a chip mounting surface side of the wiring substrate from which the semiconductor chip illustrated inFIG. 1is removed, andFIG. 5is a plan view illustrating a rear surface side (a mounting surface side) of the semiconductor device illustrated inFIG. 1. Note that, inFIGS. 2 to 5, in order to easily illustrate shapes of a pad2dand a terminal11included in the semiconductor device1of the present embodiment, plane dimensions of a plurality of the pads2dand terminals11are illustrated to be larger than those dimensions explained as exemplified below.

As illustrated inFIG. 1, the semiconductor device1of the present embodiment has a semiconductor chip2and a wiring substrate (referred to also as a base member or an interposer)3that is a base member on which the semiconductor chip2is mounted and which is electrically connected to the semiconductor chip2.

The semiconductor chip2has a front surface2a(seeFIGS. 2 and 3) and a rear surface2b(seeFIGS. 1 and 2) positioned on an opposite side of the front surface2a, which form a quadrangular shape in plan view. For example, in an example illustrated inFIG. 3, a plane shape of the semiconductor chip2is square having a side length of about 5 mm. Moreover, the semiconductor chip2has a side surface2c(seeFIG. 2) positioned between the front surface2aand the rear surface2b.

Moreover, the semiconductor chip2is provided with a semiconductor substrate (whose illustration is omitted) made of, for example, silicon, and a plurality of semiconductor elements (whose illustration is omitted) such as transistors are formed on a main surface serving as an element formation surface of the semiconductor substrate. On the main surface of the semiconductor substrate, a wiring layer (whose illustration is omitted) provided with a plurality of wires and an insulating film for electrically insulating between the plurality of wires is stacked. The plurality of wires on the wiring layer are electrically connected to the plurality of semiconductor elements to form an integrated circuit.

Moreover, on the front surface2a(seeFIG. 3) of the semiconductor chip2, a plurality of pads (referred to also as electrode pads, bonding pads, and chip electrodes)2dare formed. The plurality of pads2dare formed on the uppermost layer of the wiring layer stacked on the semiconductor substrate, and are electrically connected to the plurality of semiconductor elements via the plurality of wires of the wiring layer. Further, the front surface2aof the semiconductor chip2is covered with an insulating film made of, for example, silicon oxide (SiO2) or others. However, on the plurality of pads2d, an opening is formed in the insulating film covering the front surface2a. And, the pad2dis exposed from the insulating film in the opening. In this manner, the plurality of pads2dformed on the front surface2aof the semiconductor chip2are electrically connected to the plurality of semiconductor elements included in the semiconductor chip2, and are functioned as external terminals (in other words, electrodes) of the semiconductor chip2.

In the present embodiment, for example, as illustrated inFIG. 3, the plurality of pads2dare arranged along four side surfaces2c(sides) of the semiconductor chip2. The front surface2aof the semiconductor chip2is partitioned, for example, into a main circuit formation region (logical circuit formation region) on which a main circuit (referred to also as a core circuit) such as a logical circuit is formed and into an input/output terminal formation region (referred to also as an I/O region) in which the plurality of pads2dare arranged. Moreover, in the example illustrated inFIG. 3, the main circuit formation region is formed in a center portion of the front surface2a, and the input/output terminal formation region is arranged so as to surround the main circuit formation region. Even when, for example, a stress occurs in the plurality of pads2d, influence of the stress on the main circuit can be suppressed by partitioning the main circuit formation region and the input/output terminal formation region from each other as described above. Moreover, by collecting the input/output terminal formation region on a peripheral edge portion of the front surface2a, the number of the pads2dserving as the external terminals can be increased, and an area of the main circuit formation region can be enlarged.

Moreover, in the present embodiment, the plurality of pads2dare arranged in a plurality of rows (two rows inFIG. 3) along the four side surfaces2cof the semiconductor chip2. In other words, the semiconductor chip2is provided with a plurality of first-row pads2d1arranged along the side surfaces2cand a plurality of second-row pads2d2arranged between the first-row pads2d1and the side surfaces2c. Note that in the present embodiment, the first-row pads2d1and the second-row pads2d2(whose illustration is omitted) are arranged outside the main circuit formation region. However, if a configuration capable of relaxing the stress is adopted to the pads2dor if the stress is not considered, for example, the first-row pads2d1may be arranged inside the main circuit formation region.

The first-row pads2d1and the second-row pads2d2are provided so as to correspond to the respective four side surfaces2cof the semiconductor chip2. By arranging the pads2dalong the respective side surfaces2cin the plurality of rows as described above, the number of the pads2dcan be increased more than that in a case of arrangement in a single row. When the pads2dare arranged in the plurality of rows as described above, it is preferred to arrange them in a so-called zigzag (chidori in Japanese) arrangement in which the first-row pads2d1and the second-row pads2d2are alternately arranged along the side surfaces2cas illustrated inFIG. 3. By arranging the pads2din the zigzag arrangement, a wire2e(seeFIG. 8described later) is arranged between the first-row pads2d1adjacent to each other so as to be electrically connected to the second-row pads2d2. In other words, the first-row pad2d1can be arranged between the wires connected to the second-row pads2d2. Therefore, a wiring layout on the main surface of the semiconductor chip2is efficiently performed (provides a narrower pitch), and therefore, the number of the pads2dserving as the external terminals can be increased, and the area of the main circuit formation region can be enlarged.

As illustrated inFIGS. 1 and 2, the semiconductor chip2is mounted on the wiring substrate3. The wiring substrate3has an upper surface (referred to also as a chip mounting surface or a front surface)3a(seeFIGS. 2 and 4) and a lower surface (referred to also as a mounting surface or a rear surface)3b(seeFIGS. 2 and 5) positioned on an opposite side of the upper surface3a, which form a quadrangular shape in plan view. For example, in an example illustrated inFIG. 3, a plane shape of the wiring substrate3is square having a side length of about 7 mm to 8 mm. Moreover, the wiring substrate3also has a side surface3c(seeFIG. 2) positioned between the upper surface3aand the lower surface3b.

As illustrated inFIG. 4, on the upper surface3aof the wiring substrate3, a plurality of terminals (for example, bonding leads)11are arranged. More specifically, the wiring substrate3has an insulating layer15that is a base member referred to as a core layer or a core material, and conductor patterns made of, for example, copper (Cu) including a plurality of terminals11and wires connected to the terminals11are formed on the upper surface15aof the insulating layer15. These conductor patterns covered with a solder resist film (referred to also as an insulating film and a protective film)16formed on the upper surface15a. Moreover, in the solder resist film16, openings16aare formed at positions where the plurality of terminals11are arranged, and the plurality of terminals11are exposed from the solder resist film16in the openings16a.

Moreover, in plan view, the plurality of terminals11are arranged at positions where they overlap the plurality of pads2dof the semiconductor chip2(seeFIG. 3). Therefore, in the present embodiment, the plurality of terminals11are arranged along the respective sides of the chip mounting region which is the region overlapping the semiconductor chip2(more specifically, respective sides of a chip mounting portion forming the quadrangular shape in plan view). Moreover, in the present embodiment, the plurality of pads2dare arranged in a plurality of rows (two rows inFIG. 4) along the respective sides of the chip mounting region which is the region overlapping the semiconductor chip2. In other words, the upper surface3aof the wiring substrate3is provided with a plurality of first-row terminals (first-row bonding leads)11awhich are arranged along the respective sides of the chip mounting region and a plurality of second-row terminals (second-row bonding leads)11bwhich are arranged between the first-row terminals11aand the respective sides of the chip mounting region. In still other words, the plurality of terminals11include the plurality of first-row terminals11aelectrically connected to the plurality of first-row pads2d1and the plurality of second-row terminals11belectrically connected to the plurality of second-row pads2d2. Moreover, the first-row terminals11aand the second-row terminals11bare arranged at positions where they face to the pads2d(seeFIG. 3) of the semiconductor chip2, respectively. Therefore, they are arranged in the zigzag arrangement so as to correspond to the arrangement of the pads2d.

Meanwhile, as illustrated inFIG. 5, a plurality of lands12serving as external terminals of the semiconductor device1are arranged on the lower surface3bof the wiring substrate3, and the plurality of lands12are bonded to a plurality of solder balls13serving as mounting terminals when the semiconductor device1is mounted on a mounting substrate not illustrated. More specifically, as illustrated inFIG. 2, the wiring substrate3has the insulating layer15, and conductor patterns made of, for example, copper (Cu) including the plurality of lands12and wires connected to the lands12are formed on the lower surface15bof the insulating layer15. These conductor patterns are covered with a solder resist film (referred to also as an insulating film or a protective film)17formed in a manner so as to cover the lower surface15b. Moreover, in the solder resist film17, openings17aare formed at positions where the lands12are arranged, and the plurality of lands12are exposed from the solder resist film17in the openings17a. Further, the solder balls13to be bonded to the lands12are conductive bonding members used for electrically connecting the plurality of terminals on the mounting substrate side with the plurality of lands12when the semiconductor device1is mounted on the mounting substrate not illustrated.

Moreover, as illustrated inFIG. 5, in plan view, the plurality of lands12and the solder balls13are arranged in a line-column shape (referred to also as an array shape or a matrix shape). As the semiconductor device1, a package in which the plurality of lands12(or the solder balls13) serving as external terminals are arranged in the matrix shape on a mounting surface is referred to as an area-array type of a semiconductor device. In the area-array type of the semiconductor device1, the lower surface3bof the wiring substrate3to be the mounting surface can be effectively utilized as a layout space for the external terminals, and therefore, the number of terminals can be increased while suppressing the increase in the mounting area.

Further, as schematically illustrated inFIG. 2, the plurality of terminals11of the wiring substrate3are electrically connected to the plurality of lands12via the plurality of wires14electrically connecting between the upper surface3aside and the lower surface3bside of the wiring substrate3. In this manner, when the mounting substrate not illustrated and the semiconductor chip2are electrically connected to each other, the wiring substrate3is functioned as an interposer for intermediating between the mounting substrate and the semiconductor chip2.

Note thatFIG. 2schematically illustrates the plurality of wires14each indicated by using a straight line. However, the plurality of wires14include a wire that is drawn in each wiring layer included in the wiring substrate3and an interlayer wire (via wire) that electrically connects between the plurality of wiring layers included in the wiring substrate3. Moreover, as one example,FIG. 2illustrates the wiring substrate3provided with four wiring layers (total four layers including the first layer in the upper surface15aof the insulating layer15, the second layer and the third layer formed between the upper surface15aand the lower surface15b, and the fourth layer in the lower surface15b). However, the number of the wiring layers is not limited to the four layers, and can be changed in accordance with the number of terminals and the wiring layout.

In the present embodiment, as illustrated inFIG. 2, the mounting is performed so that the semiconductor chip2is mounted on the wiring substrate3in a state that the front surface2aof the semiconductor chip2faces to the upper surface3aof the wiring substrate3, that is, performed by a so-called flip-chip mounting method (face-down mounting method). The plurality of terminals11are arranged at positions where they face to the plurality of pads2dof the semiconductor chip2, and are electrically connected thereto as illustrated inFIG. 2via a plurality of protruding electrodes (for example, pillar-shaped electrodes)4and solder members5. Moreover, the semiconductor chip2is fixed onto the upper surface3aof the wiring substrate3via the plurality of protruding electrodes4and the solder members5. That is, the semiconductor chip2is fixed onto the wiring substrate3and is electrically connected to the wiring substrate3by bonding the protruding electrodes4formed on the pads2dto the terminals11via the solder members5.

Each of the protruding electrodes4of the present embodiment is made of, for example, copper (Cu), and is a pillar-shaped electrode formed in a column shape. Note that the shape of the protruding electrode4is not limited to the column shape but may be formed in a rectangular column shape. Moreover, as a component material of the protruding electrode bonded to the electrode pad of the semiconductor chip, not only copper (Cu) but also, for example, gold (Au) may be used. However, by using the protruding electrodes4made of copper (Cu) as in the present embodiment, a material cost can be reduced remarkably.

Moreover, each of the solder members5and the solder balls13of the present embodiment is made of a so-called lead-free solder that does not practically contain lead (Pb), such as only tin (Sn), tin-bismuth (Sn—Bi), tin-silver (Sn—Ag), tin-silver-copper (Sn—Ag—Cu), or others. Here, the lead-free solder refers to a compound having a content of lead (Pb) of 0.1 wt % or less, and this content is defined as a standard of RoHs (Restriction of Hazardous Substances) directive.

Moreover, an under fill resin (sealing body)6is arranged between the front surface2aof the semiconductor chip2and the upper surface3aof the wiring substrate3, and a bonding portion between the pad2dand the terminal11is sealed by the under fill resin6. In this manner, by sealing the bonding portion between the pad2dand the terminal11by using the under fill resin6, a stress applied on the periphery of the bonding portion between the pad2dand the terminal11can be dispersed and relaxed. However, the flip-chip mounting method is not limited to the aspect in which the under fill resin6is arranged between the semiconductor chip2and the wiring substrate3as illustrated inFIG. 2, and can be applied to a configuration in which the under fill resin6is not arranged as a modified example.

Peripheral Structure of Terminal Bonding Portion

Next, a detailed structure of the periphery of the bonding portion between the pad2dand the terminal11illustrated inFIG. 2will be explained.FIG. 6is an enlarged plan view illustrating a planar positional relation between the terminal and the protruding electrode in a “B” portion ofFIG. 4. Moreover,FIG. 7is an enlarged cross-sectional view taken along a line C-C ofFIG. 6, andFIG. 8is an enlarged cross-sectional view taken along a line D-D ofFIG. 6. Also,FIG. 9is an enlarged cross-sectional view illustrating a state in which a solder member is previously applied prior to connection of the protruding electrode to the wiring substrate illustrated inFIG. 7.

The plurality of terminals11illustrated inFIG. 6are electrically connected to the plurality of wires14formed on the upper surface3aof the wiring substrate3and covered with a solder resist film16, respectively. The plurality of terminals11and the plurality of wires14are conductor patterns which are made of the same material as each other and can be formed as one batch. In the present embodiment, it is explained that a portion of the conductor pattern formed on the upper surface3aof the wiring substrate3, which is covered with the solder resist film16, is as the wire14, and a portion thereof which is exposed from the solder resist film16is as the terminal11.

As illustrated inFIG. 6, each of the plurality of terminals11has a wide width portion (referred to also as a thick width portion)11wformed of a portion having a width (a length in a Y direction orthogonal to an X direction in which the terminal11extends in an example illustrated inFIG. 6) W2 in plan view. Moreover, each of the plurality of terminals11has a narrow width portion (referred to also as a thin width portion)11nformed integrally with the wide width portion11wand formed of a portion having a width (a length in the Y direction orthogonal to the X direction in which the terminal11extends) W1 smaller than the width W2 in the planar view. In the present embodiment, the width W2 of the wide width portion11wis almost the same as the width WB of the protruding electrode4, and is, for example, about 30 μm to 35 μm. On the other hand, the width W1 of the narrow width portion11nis smaller (narrower) than the width W2, and is, for example, about 20 μm. And, the plurality of protruding electrodes4(in other words, the pads2d) are arranged at positions where they overlap the narrow width portions11nof the plurality of terminals11, and are connected thereto via the solder member5illustrated inFIGS. 7 and 8. Note that, when each protruding electrode4has the column shape, the width WB of the protruding electrode4is defined by a bottom surface of the column shape or a diameter of the bottom surface. Moreover, when each protruding electrode4has a quadrangular column shape, the width WB of the protruding electrode4is defined by a bottom surface of the quadrangular column shape or a length of one side of the bottom surface.

Incidentally, from a viewpoint of increasing a bonding area between the solder member5and the terminal11in the region facing the protruding electrode4, the protruding electrode4is preferred to be arranged at the position where it overlaps the wide width portion11w. However, in the present embodiment, the protruding electrode4is arranged at the position where it overlaps the narrow width portion11nbecause of the following reasons. Each protruding electrode4of the present embodiment is made of copper (Cu) that is more easily oxidized than gold (Au). And, if an oxide film is formed on a surface of each protruding electrode4, the wettability of the solder member5is lowered, and therefore, the bonding strength between the solder member5and the protruding electrode4is lowered. Therefore, the surface of each protruding electrode4is subjected to a heating treatment (local reflow treatment) while being previously covered with a solder member (solder member to be a raw material of the solder member5) so as to be bonded to the terminal11.

Meanwhile, the terminals11of the present embodiment are made of copper (Cu) as described above. Therefore, as the same as the case of the protruding electrodes4, if the oxide film is formed on a surface of each terminal11, the wettability of the solder member5is lowered, and therefore, the bonding strength between the solder member5and the terminal11is lowered. Therefore, the surface of each terminal11is subjected to a heating treatment (local reflow treatment) while being previously covered with a solder member (solder member to be a raw material of the solder member5) so as to be bonded with the protruding electrode4. In this manner, by the bonding step in the state in which the raw material of the solder member5is previously applied to the surface of each protruding electrode4and the surface of each terminal11, the bonding strength of the bonding portion between the protruding electrode4and the terminal11can be improved.

However, in the case of the bonding step in the state in which the solder member to be the raw material of the solder member5is previously applied to the surface of each protruding electrode4and the surface of each terminal11, a large amount of the solder member is required in order to securely cover the surfaces of each terminal11and each protruding electrode4. More particularly, when the solder member to be the raw material of the solder member5is applied to the surface of each terminal11by using a printing method (described in detail later), a thickness of, for example, about 15 μm to 18 μm is formed.

This case increases the amount of the solder member5formed by integrally combining the solder members applied to each protruding electrode4and each terminal11to each other. Therefore, it has been found that, when a distance between a tip surface4sof each protruding electrode4(seeFIG. 8) and the upper surface of each terminal11is narrowed by the mounting of the semiconductor chip2, a part of the solder member5interpolated between the tip surface4sof each protruding electrode4and the upper surface of each terminal11undesirably protrudes on the periphery of the bonding region (for example, between the protruding electrodes4adjacent to each other, illustrated inFIG. 8).

And, when the part of the solder member5protrudes on the periphery of the bonding region, the terminals11adjacent to each other are electrically connected to each other via the protruded solder member5depending on the distance between the adjacent terminals11(or between the protruding electrodes4), and a possibility of short circuit is caused. That is, this is a cause of reduction of the reliability in the semiconductor device. In other words, a configuration in which the short circuit between the adjacent terminals11(or between the protruding electrodes4) is prevented even when the part of the solder member5protrudes becomes an obstructive factor in improving a degree of integrity of the terminals by shortening the distance among many terminals. That is, it becomes an obstructive factor in a sophisticated (or downsized) semiconductor device.

As countermeasures to the above-described problem, the following methods are considered. In order to prevent or suppress the formation of the oxide film on the surface of each terminal11, one method in which the surface of the terminal11is coated with a metal film made of a material such as gold (Au) that is more hardly oxidized than copper (Cu) is considered. In this case, even when the solder member to be the raw material of the solder member5is not previously applied on the surface of the terminal11, the lowering of the wettability of the solder member5on the surface of the terminal11can be suppressed. However, in this case, the solder member5flows to the periphery of the bonding region in the reflow treatment, which results in a cause of conduction failure between the protruding electrode4and the terminal11.

Moreover, another method in which the solder member to be the raw material of the solder member5is applied (formed) on the surface of each terminal11by using a plating method is considered. For example, according to an electrolytic plating method, the solder member (solder film) to be the raw material of the solder member5can be applied with a thickness of about 5 μm. However, in order to apply (form) the solder member by the electrolytic plating method, it is required to connect each of the plurality of terminals11to a wire (power supply line) used for carrying a current. That is, in the wiring substrate3, it is required to secure a space for arranging the power supply line for the electrolytic plating, and therefore, the downsizing of the wiring substrate is difficult. Moreover, the degree of freedom for layout for the wires14to be connected to the terminals11of the wiring substrate3is lowered.

Moreover, when the solder member is applied by using an electroless plating method, while it is not required to arrange the power supply line, the solder member tends to be unevenly applied. In other words, the solder member is not formed at the positions facing the protruding electrodes4of the terminals11in some cases. Moreover, in the electroless plating method, a plated film is deposited through a reduction action, and therefore, the terminals11made of copper (Cu) are eroded by the used plating solution, and the bonding failure tends to occur when the protruding electrodes4are bonded to the narrow width portions11nof the terminals11as in the present embodiment.

Accordingly, the present inventors of the present application have studied in view of the above-described problems, and have found out the configurations as illustrated inFIGS. 6 to 8. That is, each of the plurality of terminals11has the wide width portion (section)11whaving the width W2 in the planar view and the narrow width portion11nbeing formed integrally with the wide width portion11wand having the width W1 smaller than the width W2 in the planar view. And, the protruding electrodes4are arranged at the positions where they overlap the narrow width portions11nand are bonded thereto via the solder member5. In other words, bonding regions for bonding the protruding electrodes4overlap the narrow width portions11nof the terminals11.

In the method of applying the solder member to the surfaces of the plurality of terminals11by using the printing method, a solder paste containing a solder component and a flux component (component for activating the solder component) or many solder particles (solder powder) with a flux paste (paste containing the flux component) is/are applied to the surfaces of the terminals11. Then, the heating treatment (reflow treatment) is performed while the flux component and the solder component are in contact with each other, so that the solder component is melted to be formed integrally therewith. At this time, the melted solder component (melted solder) is influenced by the surface tension of the melted solder itself so as to be deformed as having a physically stable shape.

Here, when the plane shape of each terminal11on which the solder member is applied is not a simple shape such as a quadrangular shape, the melted solder is deformed by the influence of the surface tension in accordance with the shape of the terminal11. That is, when there are a wide width portion and a narrow width portion in a metal pattern extending in a certain direction, the melted solder tends to be easily gathered toward the wide width portion.

When this tendency is adapted to an example illustrated inFIG. 6, much melted solder is gathered to the wide width portion11w, so that a dome-shaped (or hemispherical) solder member (solder mass)5a1is formed in accordance with the shape of the wide width portion11was illustrated inFIG. 9. On the other hand, on the narrow width portion11nillustrated inFIG. 6, more particularly, on the region adjacent to the wide width portion11w, an amount of the solder member (in other words, solder film)5a2formed by the melted solder as illustrated inFIG. 9is less than that on the wide width portion11wsince the melted solder is moved toward the wide width portion11w.

And, the melted solder is cooled, and residues of the flux component and others are removed by rinsing, so that the solder member (more specifically, the solder member to be the raw material of the solder member5) is applied on the terminals11while the shape formed by the surface tension of the melted solder is maintained. That is, of the solder member5apreviously applied onto the surface of each terminal11, the amount (or the thickness) of the solder member5a2formed on the narrow width portion11nis smaller than the amount (or the thickness) of the solder member5a1formed on the wide width portion11w. In other words, in the present embodiment, each of the plurality of terminals11has the shape having the wide width portion11wand the narrow width portion11n, so that the solder member5a2can be stably thinly formed even when, for example, the method of applying the solder member5aby the printing method is used.

For example, in the present embodiment, the thickness of the solder member5a1(a distance from the upper surface of the terminal11to the highest point of the solder member5a1) is 10 μm or larger. However, when the solder member5ais applied by the printing method, it is particularly preferred that the thickness of the solder member5a1be 15 μm or larger. On the other hand, the thickness of the solder member5a2(a distance from the upper surface of the terminal11to the highest point of the solder member5a2) is 7 μm or smaller. However, when the thickness of the solder member5a1is set to 20 μm or larger, the thickness of the solder member5a2is 10 μm or smaller in some cases.

In this manner, according to the present embodiment, the thickness of the solder member5a2applied onto the narrow width portion11ncan be stably thinly formed. Therefore, by arranging the protruding electrode4(seeFIG. 7) on the thinly-formed solder member5a2(that is, at the position where it overlaps the narrow width portion11n) and bonding it to the solder member5a2, the amount of the solder member5for connecting the protruding electrode4with the terminal11as illustrated inFIGS. 7 and 8can be controlled to an appropriate amount.

Therefore, the reduction of the reliability of the semiconductor device1caused by the protruded solder member5on the periphery of the bonding region can be prevented or suppressed. In other words, the reliability of the semiconductor device1can be improved. Moreover, in the present embodiment, since the solder member5acan be stably formed by the printing method, the wire (more specifically, the power supply line) for the electrolytic plating is not formed on the wiring substrate3. Therefore, the layout space for the power supply line and the peripheral space can be eliminated, and therefore, a planar size of the wiring substrate3can be downsized. In other words, the mounting area of the semiconductor device1can be reduced. Moreover, since the power supply line is not provided, the degree of freedom for designing the wiring layout can be improved.

Further, according to the present embodiment, since the printing method can be adopted as the method of applying the solder member5a, the wiring substrates can be stably mass-produced even when they need to be mass-produced. In the case of the adoption of the above-described method, a part of the solder member5a1of the solder member5aillustrated inFIG. 9, which is arranged on the wide width portion11w, is moved toward the protruding electrode4side by bonding with the protruding electrode4. However, as illustrated inFIG. 7, much of it remains on the wide width portion11w. On the other hand, the thickness of the solder member5a2of the solder member5aillustrated inFIG. 9, which is arranged between the bonding portion with the protruding electrode4and the region covered with the solder resist film16is not largely changed by bonding with the protruding electrode4, and it remains thereon as the solder member5a2as illustrated inFIG. 7.

Therefore, in the semiconductor device1of the present embodiment to which the above-described method is adopted, the thickness of the solder member5wof the solder member5for bonding the protruding electrode4and the terminal11, which is arranged closer to the wide width portion11wside than the bonding portion with the protruding electrode4(the region sandwiched by the tip surface4sand each terminal11) is thicker than the thickness of the solder member5a2thereof, which is arranged closer to the narrow width portion11nside (on an opposite side to the wide width portion11w) than the bonding portion with the protruding electrode4. However, the thickness of the solder member5nof the solder member5, which is arranged in the bonding portion with the protruding electrode4(the region sandwiched by the tip surface4sand the narrow width portion11w) is thicker than the solder member5wthereof, which is arranged on the wide width portion11w, because of the influence of the surface tension in some cases.

As a modified example of the present embodiment, note that, even when the solder member5ais formed by adopting a different method from the printing method, the melted solder is deformed in accordance with the shape of each terminal11as described above by performing a thermal treatment (heating treatment) to the solder member applied onto the terminals11so that the solder member is melted. Therefore, even in the case of adopting, for example, the plating method (electrolytic plating method or electroless plating method), when the plated film of the solder member is formed so as to have a thickness of, for example, about 10 μm or larger, it is effective to adopt the configuration of the present embodiment so that the solder member is melted prior to the bonding with the protruding electrode4to form the solder member5aillustrated inFIG. 9.

Moreover, from the viewpoint of stably thinly forming the thickness of the solder member5a2, it is only required to form the widths of the wide width portion11wand the narrow width portion11nformed on each terminal11so as to have relatively different widths from each other. Therefore, as a modified example of the terminal11illustrated inFIG. 6, it is also allowed that, for example, the width W2 of the wide width portion11wis wider than the width WB of each protruding electrode4, and the width W1 of the narrow width portion11nis almost the same as the width of each protruding electrode4. However, from the viewpoint of downsizing the planar dimensions of the plurality of terminals11, it is preferred to form the width W2 of the wide width portion11was almost the same as the width WB of each protruding electrode4, and form the width W1 of the narrow width portion11nto be narrower than the width of each protruding electrode4as illustrated inFIG. 6.

In this case, as illustrated inFIG. 8, a part of the tip surface4sof each protruding electrode4is arranged so as to protrude outside the terminal11. Therefore, from the viewpoint of suppressing the lowering of the bonding strength due to the bonding of the protruding electrode4at the position where it overlaps the narrow width portion11n, it is preferred to form the solder member5nso as to cover the upper surface11cand the two side surfaces11dof the terminal11. In this manner, the contact area between the solder member5nand the terminal11can be increased, and therefore, the lowering of the bonding strength can be suppressed.

Method of Manufacturing Semiconductor Device

Next, a method of manufacturing the semiconductor device of the present embodiment will be explained. The semiconductor device1of the present embodiment is manufactured so as to follow a flow illustrated inFIG. 10.FIG. 10is an explanatory diagram illustrating an outline of the manufacturing steps of the semiconductor device of the present embodiment. Each step will be explained in detail below with reference toFIGS. 11 to 31.

Substrate Provision Step

First, in a substrate provision step illustrated inFIG. 10, a wiring substrate20illustrated inFIGS. 11 and 12is provided.FIG. 11is a plan view illustrating the entire configuration of the wiring substrate provided in the substrate provision step illustrated inFIG. 10, andFIG. 12is an enlarged cross-sectional view taken along a line E-E ofFIG. 11.

As illustrated inFIG. 11, the wiring substrate20provided in the present step is provided with a plurality of product formation regions20ainside a frame portion (referred to also as a frame body)20b. More specifically, the plurality of (inFIG. 11, 27) product formation regions20aare arranged in the row-column pattern. The wiring substrate20is a so-called multiple-piece taking substrate having the plurality of product formation regions20aeach corresponding to the wiring substrate3illustrated inFIG. 1and dicing lines (referred to also as dicing regions)20cformed between the respective product formation regions20a. In this manner, by using the multiple-piece taking substrate provided with the plurality of product formation regions20a, the production efficiency can be improved.

Moreover, as illustrated inFIG. 12, in each of the product formation regions20a, configuration members of the wiring substrate3explained with reference toFIGS. 1 to 9are formed. More specifically, the wiring substrate20is provided with an insulating layer15, which is made of, for example, a resin and which has an upper surface15aand a lower surface15bon a side opposite to the upper surface15a.

Moreover, each of the product formation regions20aof the wiring substrate20is provided with a plurality of terminals11arranged on the upper surface3aside, a plurality of lands12arranged on the lower surface3bside, and a plurality of wires14for electrically connecting between the plurality of terminals11and lands12. Further, an upper side of the upper surface15aand a lower side of the lower surface15bof the insulating layer15are covered with solder resist films16and17, respectively, and a plurality of terminals (bonding leads)11are exposed from the solder resist film16in openings16aformed in the solder resist film16. In the present embodiment, the plurality of terminals11are exposed in one opening16a. Moreover, in a plurality of openings17aformed in the solder resist film17, the plurality of lands12are respectively exposed from the solder resist film17.

Moreover, each of conductor patterns (the terminals11, the lands12, and the wires14) provided in the wiring substrate20is made of a metal material containing copper (Cu) as a main component. In the present embodiment, as a method of forming these conductor patterns, for example, a subtract method, a semi-additive method, or others is used. According to such a method, as illustrated inFIG. 6described above, the shape of each terminal11can be formed so as to have the wide width portion11whaving the width W2 in the planar view and the narrow width portion11nbeing formed integrally with the wide width portion11wand having the width W1 smaller than the width W2 in the planar view. Therefore, each of the plurality of terminals11included in the wiring substrate20provided in the present step has a plane shape having the wide width portion11wand the narrow width portion11nas illustrated inFIG. 6.

Further, onto the upper surfaces11cof the plurality of terminals11, a plurality of solder members5aare previously applied. These solder members5aare a raw material of the solder members5illustrated inFIG. 2as described above. Moreover, each solder member5ais applied so that the amount of the solder member5a2of the solder member5apreviously applied (formed) on the surface of each terminal11, which is formed on the narrow width portion11n, is smaller than the amount of the solder member5a1thereof, which is formed on the wide width portion11w. In other words, each of the plurality of terminals11is provided with a region (narrow width portion11n) on which the solder member5a2is applied thinly (for example, to have a thickness of 7 μm or smaller) adjacent to the wide width portion11w.

The solder member5ais formed by using, for example, the printing method as described above. Hereinafter, a method of forming the solder member5a2by using the printing method will be explained.FIG. 13is an explanatory view schematically illustrating one example of the method of forming the solder member illustrated inFIG. 12, andFIG. 14is an explanatory view schematically illustrating one example of the method of forming the solder member illustrated inFIG. 12by using a different method from the method illustrated inFIG. 13.

In the method of forming the solder member illustrated inFIG. 13, first, in step S1(a substrate provision step illustrated inFIG. 10), the wiring substrate20provided with the plurality of terminals11formed thereon is provided. Next, in step S2(a solder-member application step illustrated inFIG. 10), a solder paste “Pss” is applied (for example, printed) onto the plurality of terminals11. This solder paste Pss is a solder member containing a solder component and a flux component for activating the solder component, and exerting a paste property at a room temperature. In the present embodiment, the solder paste Pss is not applied independently onto each of the plurality of terminals11, but is applied so as to cover the plurality of terminals11as one batch. By adopting such an applying method, the application step can be simplified.

Next, in step S3(a thermal treatment step illustrated inFIG. 10), the solder paste Pss is subjected to a thermal treatment (referred to also as a heating treatment or a reflow treatment) so that the solder component contained in the solder paste Pss is melted. Note that a heating temperature at this time depends on a melting point of the solder component. However, when, for example, a tin-silver (Sn—Ag)-based lead-free solder is adopted, it is heated at 240° C. to 280° C. In the present step, a flux (flux component) “FL” contained in the solder paste Pss activates the solder component of the solder paste Pss, so that the wettability of the melted solder Ms for the terminals11can be improved.

Moreover, in the present step, the melted solder Ms is influenced by the surface tension, and is deformed so as to form the physically stable shape. Therefore, as the solder member5aillustrated inFIG. 9 or 12, much of the melted solder Ms (seeFIG. 13) is gathered on the wide width portion11w. As a result, the thickness of the melted solder Ms on the narrow width portion11nillustrated inFIG. 13can be stably thinly formed with, for example, 7 μm or smaller. Next, in step S4(a rinse step illustrated inFIG. 10), the melted solder Ms is solidified by cooling the melted solder Ms so as to form the solder member5a. Moreover, by rinsing the peripheral portion of each terminal11, residues of the flux FL remaining on the periphery of the solder members5aare removed, so that a wiring substrate20with the solder members5aformed thereon as illustrated inFIG. 12is obtained.

On the other hand, the method of forming the solder member illustrated inFIG. 14is as follows. First, in the step S1illustrated inFIG. 14(substrate provision step illustrated inFIG. 10), a wiring substrate20with a plurality of terminals11formed thereon is provided. Next, in the step S2(the substrate provision step illustrated inFIG. 10), the plurality of terminals11formed on the wiring substrate20are soaked in treatment liquid, and then, is dried, so that an adhesive film “NF” is formed on surfaces (upper surface and side surfaces) of each terminal11. The adhesive film NF is formed by a chemical reaction between the metal on the surfaces of the terminal11and the treatment liquid, and therefore, the adhesive film NF can be formed on the exposed surfaces (upper surface and side surfaces) of the terminal11.

Next, in the step S3(the solder-member application step illustrated inFIG. 10), a large number of solder particles (solder powder, solder member) “Pws” are applied (printed) onto the plurality of terminals11, and are adhered onto the adhesive film NF. Since the adhesive film NF is selectively formed on the surfaces of the terminals11, the solder particles Pws are not adhered onto the upper surface15aof the insulating layer15even when the solder particles Pws are applied onto the plurality of terminals11as one batch. Therefore, the solder particles Pws can be selectively adhered onto the terminals11. Thus, in the method illustrated inFIG. 14, the amount of the solder component adhered onto the periphery of each terminal11can be reduced more than that in the method illustrated inFIG. 13. Moreover, by adjusting an average particle size of the solder particles Pws, the amount of the solder component adhered to the periphery of the terminal11can be controlled. That is, by decreasing the average particle size of the solder particles Pws, the amount of the solder component adhered onto the periphery of the terminal11can be decreased. On the other hand, by increasing the average particle size of the solder particles Pws, the amount of the solder component adhered onto the periphery of the terminal11can be increased.

Next, in step S4(the solder-member application step illustrated inFIG. 10), a paste containing the flux FL (flux paste) is applied (printed) so as to cover the plurality of terminals11and the solder particles Pws. Since the flux FL is applied in order to activate the solder particles (solder component) Pws to improve the wettability for the terminals11, it is applied so as to, for example, cover the plurality of terminals11as one batch from the viewpoint of simplifying the application step. Next, in step S5(a thermal treatment step illustrated inFIG. 10), the solder particles Pws are subjected to a thermal treatment (a heating treatment, or a reflow treatment) so that the solder component is melted.

Note that a heating temperature at this time depends on the melting point of the solder component. However, when a tin-silver (Sn—Ag)-based lead-free solder is adopted, it is heated at 240° C. to 280° C. In the present step, the flux FL applied onto the solder particles Pws activates the solder component, so that the wettability of the melted solder Ms for the terminals11can be improved. Moreover, in the present step, as described above, the melted solder Ms is influenced by the surface tension, and is deformed so as to form the physically stable shape. Therefore, as the solder member5aillustrated inFIG. 9 or 12, much of the melted solder Ms (seeFIG. 13) is gathered onto the wide width portion11w. Next, in step S6(a rinsing step illustrated inFIG. 10), the melted solder Ms is solidified by cooling the melted solder Ms so as to form the solder members5a. Moreover, by rinsing the peripheral portion of each terminal11and removing the residues of the flux FL remaining on the periphery of the solder members5a, a wiring substrate20with the solder members5aformed thereon as illustrated inFIG. 12is obtained.

Note that the above-described methods of forming the solder members5aare explained by exemplifying two methods that are considered to be particularly preferable among methods studied by the inventors of the present application. Therefore, it is needless to say that various modifications can be made within the scope of the invention.

Semiconductor-Chip Provision Step

In a semiconductor-chip provision step illustrated inFIG. 10, the above-described semiconductor chip2illustrated inFIG. 3is provided.FIG. 15is a perspective view illustrating a semiconductor wafer provided in a wafer provision step illustrated inFIG. 10, andFIG. 16is an enlarged cross-sectional view illustrating the periphery of the pads formed in one chip region of the semiconductor wafer illustrated inFIG. 15. Moreover,FIG. 17is an enlarged cross-sectional view illustrating a state in which the protruding electrodes are formed on the plurality of pads illustrated inFIG. 16,FIG. 18is an enlarged cross-sectional view illustrating a state in which the solder member is attached to the tip surfaces of the protruding electrodes illustrated inFIG. 17,FIG. 19is an enlarged cross-sectional view illustrating a state in which a mask illustrated inFIG. 18is removed, andFIG. 20is an enlarged cross-sectional view illustrating a state in which the solder member illustrated inFIG. 19is heated to be deformed into the dome shape.

The semiconductor chip illustrated inFIG. 3is manufactured as, for example, follows. First, in the wafer provision step illustrated inFIG. 10, a wafer (semiconductor wafer)25illustrated inFIG. 15is provided. The wafer25provided in the present step has the front surface2aand the rear surface2bpositioned on the side opposite to the front surface2a, each of which has a substantially round plane shape as illustrated inFIG. 15. Moreover, the wafer25has a plurality of chip regions (device regions)25a, and each of the chip regions25acorresponds to the semiconductor chip2illustrated inFIG. 3. Further, a scribe line (scribe region)25bis formed between the adjacent chip regions25a. The scribe lines25bare formed into a lattice shape so as to partition the front surface2aof the wafer25into the plurality of chip regions25a. Moreover, on the scribe line25b, a plurality of conductor patterns such as a TEG (Test Element Group) and an alignment mark are formed for checking whether or not the semiconductor element or others formed inside the chip region25ais correctly formed.

In the wafer25provided in the present step, a plurality of semiconductor elements (whose illustration is omitted) such as transistors are formed on the main surface (element formation surface) of the semiconductor substrate made of, for example, silicon (Si). Moreover, on the main surface of the semiconductor substrate, as illustrated inFIG. 16, wiring layers (whose illustrations are omitted) each provided with a plurality of wires2eand an insulating film2ffor insulating between the adjacent wires2eare stacked, and a plurality of pads (referred to also as electrode pads, bonding pads, or chip electrodes)2delectrically connected to the plurality of wires2eare formed in the uppermost layer of the layers. The plurality of pads2dare electrically connected to the plurality of semiconductor elements via the plurality of wires2eof the wiring layer. That is, in the wafer25provided in the present step, an integrated circuit is previously formed on the main surface of the semiconductor substrate. Moreover, while the front surface2aof the semiconductor chip2is covered with an insulating film2gmade of, for example, silicon oxide (SiO2) or others, openings2hare formed on the plurality of pads2din the insulating film2gcovering the front surface2a. And, the pads2dare exposed from the insulating film in the openings2h.

Next, in the protruding-electrode formation step illustrated inFIG. 10, the metal film is deposited on each of the plurality of pads2das illustrated inFIG. 17to form the protruding electrodes4. In the present embodiment, as illustrated inFIG. 17, a mask26is arranged (more specifically, fixed) onto the front surface2aof the wafer25. And, through holes26aare formed at positions where the protruding electrodes4are formed. The through holes26acan be formed by using, for example, a photolithography technique and an etching technique.

Subsequently, by depositing the metal film inside the through holes26a, the protruding electrodes4are formed. In the present embodiment, a copper film is deposited. A method of depositing the metal film is not particularly limited, and the deposition step may be performed by using, for example, a plating method. Moreover, when a metal film different from the copper film is formed on an interface between the copper film and the pads2dor on the tip surfaces4sof the protruding electrodes4, the film can be easily formed by sequentially depositing a different metal material.

In this manner, when the protruding electrodes4are formed by depositing the metal film, stress applied onto the pads2dcaused in bonding the protruding electrodes4and the pads2dcan be reduced. More particularly, the stress can be significantly reduced as compared with a method of press-bonding (including thermally press-bonding) the protruding electrodes onto the pads. Therefore, the reduction of the reliability due to damage of the chip regions25ain forming the protruding electrodes can be suppressed.

Moreover, by depositing the metal film while the plurality of through holes26aare formed in the mask26, the plurality of (large number of) protruding electrodes4can be formed as one batch. Therefore, the protruding electrodes4can be efficiently formed. Moreover, since the protruding electrodes4are formed prior to partitioning the wafer25, the protruding electrodes4can be formed on the plurality of chip regions25aas one batch. Therefore, the protruding electrodes4can be formed efficiently. In this manner, the protruding electrodes4which are formed by depositing the metal film inside the through holes26aof the mask26become column-shaped electrodes each having a three-dimensional column shape. Further, the planar shape of the protruding electrode4is formed in accordance with the opening shape of the through hole26a. For example, in the present embodiment, by forming the through hole26ahaving a round opening shape, the protruding electrode4having the column shape can be obtained.

Next, in a solder-member formation step illustrated inFIG. 10, by depositing the solder film on each of the tip surfaces4sof the protruding electrodes4as illustrated inFIG. 18, the solder members5bare formed thereon. In the above-described protruding-electrode formation step in the present embodiment, the metal film is deposited in the middle of each through hole26a(seeFIG. 17), and then, a solder film is successively deposited thereon (without removing the mask26). Thus, by, for example, depositing the copper film, and then, successively depositing the solder film, the formation of the oxide film on the copper film prior to forming the solder film can be prevented. Therefore, the bonding strength of the bonding interfaces between the solder members5band the protruding electrodes4can be improved.

Moreover, by covering the tip surfaces4sof the protruding electrodes4with the solder members5bin the present step, exposure of the tip surfaces4sto the atmosphere can be prevented, and therefore, a state in which the oxide film is difficult to be formed on the tip surfaces4scan be maintained. Therefore, the bonding strength of the bonding interfaces between the solder members5band the protruding electrodes4can be improved. As a result, as illustrated inFIG. 8, the bonding strength of the bonding interfaces between the solder members5and the tip surfaces4scan be improved.

In order to more securely suppress the oxidation of the protruding electrodes4, note that a nickel (Ni) film may be formed on the tip surfaces4sof the protruding electrodes4. However, when the nickel film is formed, the number of plating steps (step time) increases, and therefore, it is preferred to directly form the solder members5bonto the tip surfaces4sof the protruding electrodes4as in the present embodiment.

Next, by removing the mask26(seeFIG. 18), and then, performing the rinsing, the side surfaces of the protruding electrodes4are exposed as illustrated inFIG. 19. In this state, each solder member5bhas the column shape as similar to each protruding electrode4. However, by performing the thermal treatment (heating treatment) so as to melt at least a part of each solder member5b, the shape of the solder member5bis deformed by the influence of the surface tension of the melted solder so as to form the dome shape as illustrated inFIG. 20. In this manner, by performing the thermal treatment, the tip surfaces4sof the protruding electrodes4and the solder members5bare firmly bonded to each other. Moreover, the solder members5bare more stable in the dome shape as illustrated inFIG. 20, and therefore, are suppressed from dropping off from the protruding electrodes and being damaged.

By using each of the steps as described above, a wafer25is obtained so that the plurality of protruding electrodes4are formed (bonded) onto the front surfaces (upper surfaces) of the plurality of pads2d, and besides, the plurality of solder members5bare formed on the tip surfaces4sof the plurality of protruding electrodes4.

Next, a tape (whose illustration is omitted) for the back grind is pasted onto the front surface of the wafer25on which the plurality of protruding electrodes4are formed, and the rear surface of the wafer25is polished (ground), so that a wafer25having a desired thickness is obtained. Note that, when the thickness of the provided wafer25is already thin in the wafer provision stage, or when it is not required to be thin, this grinding step can be eliminated.

Next, in a dicing step illustrated inFIG. 10, the wafer25illustrated inFIG. 20is divided (diced) for each of the chip regions25aso that a plurality of pieces of the semiconductor chips2illustrated inFIG. 3are obtained. In the present step, the wafer25is cut and divided along the scribe lines25billustrated inFIG. 15. As a cutting method, although not particularly limited, a cutting method using a dicing blade (rotary blade) or a cutting method using a laser irradiation can be adopted.

Chip Mounting Step

In a chip mounting step illustrated inFIG. 10, the semiconductor chip2is arranged on the wring substrate20so that the front surface2afaces to the upper surface3aof the wiring substrate20, as illustrated inFIG. 21, and the plurality of terminals11and the plurality of pads2dare electrically connected to each other.FIG. 21is an enlarged cross-sectional view illustrating a state in which the semiconductor chip is mounted on the wiring substrate illustrated inFIG. 12. Moreover,FIG. 22is an enlarged plan view illustrating a planar positional relation between the protruding electrodes and the terminals obtained when the semiconductor chip is arranged on the wiring substrate. Further,FIG. 23is an enlarged cross-sectional view taken along a line C-C ofFIG. 22, andFIG. 24is an enlarged cross-sectional view taken along a line D-D ofFIG. 22. Still further,FIG. 25is an enlarged cross-sectional view illustrating a state in which facing-arranged solder members as illustrated inFIG. 23are in contact to each other, andFIG. 26is an enlarged cross-sectional view illustrating a state in which facing-arranged solder members as illustrated inFIG. 24are in contact to each other. Moreover,FIG. 27is an enlarged cross-sectional view illustrating a state in which the contacted solder members illustrated inFIG. 25are integrally formed with each other, andFIG. 28is an enlarged cross-sectional view illustrating a state in which the contacted solder members illustrated inFIG. 26are integrally formed with each other.

In the present step, first, as illustrated inFIGS. 22 to 24, the semiconductor chips2are arranged on the wiring substrate20so that the front surfaces2aface to the upper surface3aof the wiring substrate20(in a semiconductor-chip arrangement step). At this time, as illustrated inFIGS. 23 and 24, each of the tip surfaces4sof the plurality of protruding electrodes4is arranged on each of the narrow width portions11n(positions where they overlap the narrow width portions11n) of the terminals11. In other words, the solder member5battached to each tip surface4sof the protruding electrodes4is arranged so as to face to each of the narrow width portions11nof the terminals11. This arrangement is for bonding the protruding electrode4to the region where the solder member5ais thinly formed, that is, to the bonding region on the narrow width portion11n.

Moreover, as illustrated inFIG. 23, in the present embodiment, the tip surface4sof each protruding electrode4is arranged so as not to overlap the wide width portion11wof each terminal11. However, as illustrated inFIG. 23, the solder member5a1arranged on the wide width portion11whas the dome shape whose top portion is located in the center of the wide width portion11w. Therefore, the thickness of the solder member5a1in a peripheral edge portion of the wide width portion11w(that is, in a foot portion of the solder member5a1) is thinner that in the center thereof. Therefore, even when a part of the peripheral edge portion of the tip surface4sof the protruding electrode4overlaps the wide width portion11w, the amount of the protruding portion of the solder member5(seeFIG. 21) from the terminal11can be reduced further than that in the case in which the center portion of the tip surface4sis arranged on the wide width portion11w.

However, from a viewpoint of securely reducing the amount of the protruding portion of the solder member5from the terminal11for securely suppressing the short-circuiting failure, it is preferred to arrange the entire tip surface4sof the protruding electrode4so as not to overlap the wide width portion11wof the terminal11as illustrated inFIG. 23. Moreover, from a viewpoint of shortening a period of time taken when the temperatures of the solder members5aand5breach their melting points or higher in a thermal step (thermal treatment process, local reflow treatment) described later, it is preferred to previously heat the solder members5aand5bin the state as illustrated inFIGS. 23 and 24(to perform a previous thermal step).

However, at this stage, it is not required to melt the solder members5aand5bbut only required to previously heat them. As a method of heating the solder members5a, the wiring substrate20is fixed to a heat stage (a substrate holding base provided with a heating unit such as a heater; whose illustration is omitted), and a temperature of the heat stage is set to, for example, about 100° C. Thus, the solder members5acan be heated via the conductor patterns (the terminals11, etc.) formed on the wiring substrate20. Moreover, by heating the semiconductor chips2by the heating unit such as the heater (whose illustration is omitted), the solder member5battached to the semiconductor chip2can be heated. The semiconductor chip2can be heated at a temperature higher than that of the wiring substrate20, and therefore, is previously heated at a temperature higher than that of the wiring substrate20, for example, at about 200° C.

Next, as illustrated inFIGS. 25 and 26, a distance between the semiconductor chips2and the wiring substrate3is made shorter so that the solder members5aand5bare in contact with each other (in a solder-member contact step). At this time, as illustrated inFIG. 25, the solder member5bis made in contact with the solder member5a2of the solder member5a, which is arranged on the narrow width portion11nof each terminal11. Moreover, as illustrated inFIG. 26, in order to make the plurality of solder members5band the plurality of solder members5ain contact with each other, it is preferred to heat at least either one of the solder members5aand the solder members5bso as to be hardened as hard as being deformed after the contact. This is because, even when the thicknesses of the protruding electrodes4and the solder members5aand5bare varied, all the solder members5aand5bcan be in contact with each other by contacting the solder members5aand5bso that either one thereof is dug into the other.

Moreover, in this state, the solder members5aand5bare further heated up to their melting points or higher (in the heating step (referred to also as a thermal treatment step or a local reflow step)). Although the heating temperature is varied depending on the melting points of the solder members5aand5b, they are heated at a temperature of 240° C. to 280° C. when the tin-silver (Sn—Ag)-based lead-free solder is adopted. In the present step, they are heated while the solder members5aand5bare in contact with each other, and therefore, the solder member5acan be heated by, for example, heat transfer from the solder member5b. Then, when each of the solder members5aand5bis melted, the solder members5aand5bare formed integrally with each other. That is, the solder members5aand5bare in a so-called “wet state”. And, by cooling the melted solder after they are formed integrally with each other, the solder member5(more specifically, the solder member5n) illustrated inFIGS. 27 and 28is formed.

In this manner, by bringing the solder members5aand5binto the wet state, they can be firmly bonded to each other. Moreover, when the solder members5aand5bare formed integrally with each other, they are deformed so as to have the physically stable shape by the surface tension of the integrated melted solder. Therefore, as illustrated inFIG. 27, a part of the solder members arranged on the wide width portions11wof the terminals11are moved toward the protruding electrodes4. However, as described above, the melted solder tends to be gathered toward the wide width portion11whaving a wider plane area due to the influence of the surface tension, and therefore, much of the melted solder remains on the wide width portion11w. That is, the amount of the melted solder moved toward the tip surfaces4s(seeFIG. 28) of the protruding electrodes4is limited.

Therefore, the shape of the solder member5formed in the present step tends to have a shape exemplified inFIGS. 27 and 28. That is, the thickness of the solder member5nof the solder member5, which is arranged on the bonding portion with the protruding electrode4(the region sandwiched by the tip surface4sand the terminal11), is substantially equal to (the solder member5nis slightly thicker than) the thickness of the solder member5wthereof, which is arranged on the wide width portion11w. On the other hand, the thickness of the solder member5a2of the solder member5, which is arranged adjacent to the bonding portion with the protruding electrode4and arranged on a side opposite to the solder member5w, is hardly changed, and is thinner than those of the solder members5wand5n.

Moreover, in a cross-sectional surface of the bonding portion with the protruding electrode4in a width direction (a direction orthogonal to a direction of extending the terminal11), the amount of the solder member5nis smaller as illustrated inFIG. 28, and therefore, the amount of the protrusion of the solder member5nin the width direction can be suppressed. As a result, the short-circuit (short) between the adjacent solder members5ncan be suppressed. That is, the reduction of the reliability of the semiconductor device can be suppressed. In other words, by suppressing the amount of the protrusion of the solder member5n, the distance between the adjacent terminals11(the distance between the protruding electrodes4, and the distance between the pads2d) can be made shorter, and therefore, the degree of integration can be improved.

Sealing Step

Next, in a sealing step illustrated inFIG. 10, an under fill resin6is supplied between the front surface2aof the semiconductor chip2and the upper surface3aof the wiring substrate20as illustrated inFIG. 29so as to seal the bonding portion between the pad2dand the terminal11.FIG. 29is an enlarged cross-sectional view illustrating a state in which the under fill resin is supplied between the semiconductor chip and the wiring substrate as illustrated inFIG. 21. In the present step, for example, a nozzle27for supplying the resin is arranged outside the side surface2cof the semiconductor chip2, and the under fill resin6that is, for example, a thermosetting resin is supplied between the front surface2aof the semiconductor chip2and the upper surface3aof the wiring substrate20. In this manner, the respective bonding portions among the pads2d, the protruding electrodes4, the solder members5, and the terminals11, can be sealed as one batch. By sealing the bonding portions between the pads2dand the terminals11with the under fill resin6as described above, the stress applied to the bonding portions can be dispersed via the under fill resin6, and therefore, this manner is preferable from a viewpoint of improving the connection reliability between the pads2dand the terminals11. However, the application of the technique explained in the present embodiment is not limited to the semiconductor device using the under fill resin6, and the technique can be also applied to a semiconductor device without arranging the under fill resin6illustrated inFIG. 29as a modified example to the present embodiment. In this case, the sealing step illustrated inFIG. 10can be eliminated. Moreover, even when the under fill resin6is used, as different from the present embodiment in which the under fill resin6is supplied between the semiconductor chip2and the wiring substrate20subsequent to the arrangement of the semiconductor chip2on the wiring substrate20, the semiconductor chip2may be arranged on the wiring substrate20subsequent to the previous arrangement of the under fill resin6on the chip mounting region of the wiring substrate20.

Ball Mounting Step

Next, in a ball mounting step illustrated inFIG. 10, the plurality of solder balls13are bonded onto the plurality of lands12formed on the lower surface3bof the wiring substrate20as illustrated inFIG. 30.FIG. 30is an enlarged cross-sectional view illustrating a state in which the solder balls are bonded onto the plurality of lands after the wiring substrate illustrated inFIG. 29is turned upside down. In the present step, after the wiring substrate20is turned upside down as illustrated inFIG. 30, the solder balls13are arranged on the plurality of lands12exposed from the lower surface3bof the wiring substrate20, respectively, and then, they are heated, so that the plurality of solder balls13and the lands12are bonded to each other. By the present step, the plurality of solder balls13are electrically connected to the semiconductor chips2via the wiring substrate20. However, the application of the technique explained in the present embodiment is not limited to the so-called BGA (Ball Grid Array) type semiconductor device with bonding of the solder balls13. For example, as a modified example of the present embodiment, the technique may be applied to a so-called LGA (Land Grid Array) type semiconductor device to be shipped in a state in which the lands12are exposed without forming the solder balls13or a state in which a solder paste is applied onto the lands12so as to be thinner than that onto the solder balls13.

Separating Step

Next, in a separating step as illustrated inFIG. 10, the wiring substrate20is separated into pieces for each of the product formation regions20aas illustrated inFIG. 31.FIG. 31is a plan view (bottom view) illustrating a state in which the multiple-piece taking wiring substrate illustrated inFIG. 30is separated. In this step, as illustrated inFIG. 31, the wiring substrate20is cut along dicing lines (dicing regions)20cso that a plurality of separated semiconductor devices1are obtained. Although a cutting method is not particularly limited, a method of cutting the wiring substrate using, for example, a dicing blade (rotary blade) can be used.

By using each of the above-described steps, the semiconductor device1explained with reference toFIGS. 1 to 4is obtained. Then, necessary inspections and tests such as an appearance inspection and an electrical test are performed thereon, and then, shipping or mounting on a not-illustrated mounting substrate is performed.

Second Embodiment

The above-described first embodiment has explained the technique of reducing the amount of the protrusion of the solder member5by bonding each protruding electrode4at the position where it overlaps the narrow width portion11nof each terminal11having the wide width portion11wand the narrow width portion11n. The present embodiment will explain a technique of further stably controlling the amount of the protrusion of the solder member5by bonding each protruding electrode4at a position where it overlaps the narrow width portion11nof each terminal11having the narrow width portion11nformed between adjacent wide width portions11w.

FIG. 32is an enlarged plan view illustrating a planar positional relation between the terminals and the protruding electrodes of the present embodiment that is a modified example ofFIG. 6. Moreover,FIG. 33is an enlarged plan view illustrating one of the plurality of terminals illustrated inFIG. 32so as to be enlarged. Further,FIG. 34is an enlarged cross-sectional view taken along a line C-C ofFIG. 32, andFIG. 35is an enlarged cross-sectional view taken along a line D-D ofFIG. 32. Moreover,FIG. 36is an enlarged cross-sectional view illustrating a state in which a solder member is previously applied prior to connecting protruding electrodes to a wiring substrate illustrated inFIG. 34. Further,FIG. 37is an enlarged plan view illustrating a state in which a solder member is previously applied prior to connecting protruding electrodes to a wiring substrate illustrated inFIG. 33. Still further,FIG. 38is an enlarged plan view illustrating a state in which a solder member is previously applied prior to connecting protruding electrodes to a wiring substrate illustrated inFIG. 6. Still further,FIG. 39is an enlarged plan view illustrating a state in which protruding electrodes are connected to terminals illustrated inFIG. 38.

Note that the present embodiment is a modified example of the above-described first embodiment, and the technique explained in the above-described first embodiment can be applied to the present embodiment except for differences explained below. Therefore, in the present embodiment, the differences between the above-described first embodiment and the present embodiment will be focused for explanation, and repetitive explanations will be omitted.

Moreover, the plurality of terminals11illustrated inFIG. 32are electrically connected to a plurality of wires14formed on the upper surface3aof the wiring substrate3and coated with the solder resist film16, respectively. Each of the plurality of terminals11and the plurality of wires14are conductor patterns which are made of the same material as each other and can be formed as one batch. In the present embodiment, as similar to the above-described first embodiment, a portion of the conductor patterns formed on the upper surface3aof the wiring substrate3, which is covered with the solder resist film16will be explained as the wire14, and a portion thereof which is exposed from the solder resist film16will be explained as the terminal11. Also, the same goes for a modified example explained below.

As illustrated inFIG. 32, in a semiconductor device1A of the present embodiment, each of the plurality of terminals11in the planar view is different in the shape from that of the semiconductor device1of the above-described first embodiment illustrated inFIG. 6. As illustrated inFIG. 32, each of the plurality of terminals11included in the semiconductor device1A of the present embodiment has a plurality of wide width portions11wand a narrow width portion whose width (length in a Y direction illustrated inFIG. 32) is narrower than those of the wide width portions11w. More specifically, in each terminal11, two wide width portions11ware arranged, and a narrow width portion11nis arranged between these two wide width portions11w, and each protruding electrode4is connected at a position where it overlaps this narrow width portion11n. In other words, wide width portions11w1and11w2are provided (connected) on both sides of the narrow width portion11nwhich is the bonding portion with the protruding electrode4.

More specifically, as illustrated inFIG. 33, each of the plurality of terminals11included in the semiconductor device1A has a narrow width portion11nhaving an end portion (connecting portion) NE1 and an end portion (connecting portion) NE2 in the X direction in plan view, and besides, having a width (a length along the Y direction orthogonal to the X direction) W1. Moreover, each of the plurality of terminals11has a wide width portion11w1having a width W2 (a length along the Y direction) larger than the width W1, and besides, being connected to the end portion NE1 of the narrow width portion11n. Further, each of the plurality of terminals11has a wide width portion11w2having a width W3 (a length along the Y direction) larger than the width W1, and besides, being connected to the end portion NE2 of the narrow width portion11n. And, in the planar view, the center of the tip surface4s(seeFIG. 35) of each protruding electrode4is arranged between the wide width portion11w1and the wide width portion11w2of the terminal11.

The present embodiment is the same as the above-described first embodiment in that the center of the tip surface4sof each protruding electrode4is arranged at the position where it overlaps the narrow width portion11nin each terminal11having the wide width portion11wand the narrow width portion11n. Therefore, the same effects as those of the above-described first embodiment can be obtained.

Moreover, according to the present embodiment, the narrow width portion11nis arranged between the adjacent wide width portions11w1and11w2, and therefore, the following effects can be obtained in addition to the effects explained in the above-described first embodiment.

First, in the present embodiment, since the narrow width portion11nis bonded between the adjacent wide width portions11w1and11w2, the thickness of the solder member5apreviously formed in the terminal11as illustrated inFIGS. 36 and 37is easily controlled. As explained in the above-described first embodiment, when the solder member5ais melted, the melted solder is influenced by the surface tension of the melted solder itself, and therefore, the melted solder tends to be gathered toward the region having the relatively large area. When this tendency is adapted to the present embodiment, much of the melted solder is gathered to the wide width portion11w1as illustrated inFIG. 36, and a dome-shaped (or a hemispherical-shaped) solder member (solder mass)5a1is formed in accordance with the shape of the wide width portion11w1. Moreover, much of the melted solder is gathered to the wide width portion11w2, and a dome-shaped (or a hemispherical-shaped) solder member (solder mass)5a3is formed in accordance with the shape of the wide width portion11w2. On the other hand, on the narrow width portion11n, the melted solder is moved toward the wide width portion11w, and therefore, the amount of the solder member5a2formed on the narrow width portion11nbecomes less than those of the solder members5a1and5a3formed on the wide width portions11w1and11w2.

Here, in the aspect explained in the above-described first embodiment, as illustrated in, for example,FIG. 38, the amount of the solder member5a2is gradually less as it is distant further from the border between the wide width portion11wand the narrow width portion11n. Therefore, depending on the position of the tip surface of the protruding electrode4(seeFIG. 7), the amount of the solder member5a2in the step of bonding with the protruding electrode4is too small in some cases. For example, when the bonding position between the protruding electrode4and the terminal11in the planar view illustrated inFIG. 22is distant from the border between the wide width portion11wand the narrow width portion11nbut is in vicinity of the solder resist film16, it is difficult to control the amount of the solder member5a. Therefore, when the amount of the solder member5aat the bonding position with the protruding electrode4is extremely small, this is a cause of the reduction in the bonding strength.

Meanwhile, according to the present embodiment, the thickness of the solder member5a2bonded onto the narrow width portion11nsandwiched by the wide width portions11w1and11w2can be controlled by a separated distance L1 between the end portions NE1 and NE2 (in other words, a separated distance L1 between the wide width portions11w1and11w2). Therefore, the thickness of the solder member5a2can be controlled within a predetermined range at any position as long as the position is located between the wide width portions11w1and11w2, that is, the position where it overlaps the narrow width portion11n. That is, the thickness of the solder member5a2to be formed on the narrow width portion11ncan be made stably thinner than that of the above-described first embodiment. Therefore, according to the present embodiment, by arranging each protruding electrode4(seeFIG. 34) on the thinly-formed solder member5a2(that is, between the wide width portions11w1and11w2) to be bonded to the solder member5a2, the amount of the solder member5(more specifically, the solder member5n) for bonding the protruding electrode4and the terminal11can be controlled to be an appropriate amount.

Moreover, in an example illustrated inFIG. 37, an area of the wide width portion11w1and an area of the wide width portion11w2are made equal to each other in the planar view. By forming the areas of the wide width portion11w1and the wide width portion11w2so as to be equal to each other as described above, the amount of the solder member5a(more specifically, the amounts of the solder member5a1and the solder member5a3) gathered to each of the wide width portions11w1and11w2can be equal to each other. In this case, the thickness of the solder member5a2formed on the narrow width portion11ncan be further easily controlled.

Also, by forming the areas of the wide width portions11w1and11w2so as to be equal to each other, the amounts of solder members5obtained after the bonding with the protruding electrode4can be equal to each other as illustrated inFIG. 33. More specifically, the amount of the solder member5w1formed on the wide width portion11w1and the amount of the solder member5w2formed on the wide width portion11w2as illustrated inFIG. 33can be equal to each other. By controlling the amounts of the solder members5w1and5w2in this manner, it becomes possible to easily control the amount of the solder member5nformed between the solder members5w1and5w2. Therefore, as illustrated inFIG. 33, it is possible to easily control the amount of the solder member5nformed on the periphery of the bonding portion between the protruding electrode4and the terminal11.

Moreover, in the example illustrated inFIG. 33, the width W2 of the wide width portion11w1and the width W3 of the wide width portion11w2are made equal to each other. More specifically, in the example illustrated inFIG. 33, in the planar view, the area of the wide width portion11w1and the area of the wide width portion11w2are made equal to each other, and the width W2 of the wide width portion11w1and the width W3 of the wide width portion11w2are made equal to each other. In other words, in the example, illustrated inFIG. 33, in the plan view, the wide width portions11w1and11w2have the same shape as each other. By forming the wide width portions11w1and11w2to have the same shape, the shapes of the solder members5ato be gathered to the wide width portions11w1and11w2respectively (more specifically, the shapes of the solder member5a1and the solder member5a3) can be made equal to each other, as illustrated inFIG. 36andFIG. 37. In this case, the thickness of the solder member5a2to be formed on the narrow width portion11ncan be more easily controlled.

As seen from comparison ofFIG. 8explained in the above-described first embodiment withFIG. 35of the present embodiment, according to the present embodiment, it is possible to increase the amount of the solder members5flowing round to the side surface11dof the narrow width portion11narranged on the region to which the protruding electrode4is bonded. Thus, according to the present embodiment, the bonding strength between the solder member5and the narrow width portion11ncan be improved.

As illustrated inFIG. 38, when the wide width portion11wis bonded to only one end portion NE1 of the narrow width portion11n, the width W4 of the solder member5a2arranged in the periphery of the narrow width portion11nis smaller in the planar view as being farther from the vicinity of the end portion NE1. In this case, as illustrated inFIG. 39, when the protruding electrode4is bonded, the solder member5b(seeFIG. 26) previously formed on the protruding electrode4and the solder member5a2(seeFIG. 38) are formed integrally with each other. Therefore, the width W4 of the solder member5nin the planar view is locally larger in the periphery of the protruding electrode4. However, since the amount of the solder members5a2previously formed on the bonding portion with the protruding electrode4is small, and since the melted solder tends to gather onto the wide width portion11w, the width W4 of the solder member5nis not so large.

On the other hand, in the case of the present embodiment, as illustrated inFIG. 37, since the wide width portions11ware arranged on the both end portions of the narrow width portion11n, the width W4 of the solder member5a2arranged in the periphery of the narrow width portion11nin the planar view is larger than that of the aspect illustrated inFIG. 38. That is, in the present embodiment, prior to the bonding with the protruding electrode4, the width W4 of the solder member5a2in the planar view is already larger as illustrated inFIG. 37. When the protruding electrode4is bonded onto the narrow width portion11nin this state, the width W4 of the solder member5nin the planar view is further larger in the periphery of the protruding electrode4as illustrated inFIG. 33. As a result, as illustrated inFIG. 35, it is possible to increase the amount of the solder member5nflowing round to the side surface11dof the narrow width portion11narranged in the region to which the protruding electrode4is bonded.

When the amount of the solder member5nflowing round to the side surface11dof the narrow width portion11nis excessively large, this excess is a cause of reduction of reliability since a part of the solder member5nprotrudes onto the periphery of the bonding region so that the adjacent terminals are connected electrically to each other. However, according to the present embodiment, the width W4 of the solder member5a2arranged in the periphery of the wide width portion11nin the planar view can be controlled by the width W2 of the wide width portion11w1, the width W3 of the wide width portion11w2, and the separated distance L between the end portions NE1 and NE2. That is, according to the present embodiment, it is possible to increase the amount of the solder member5nflowing round to the side surface11dof the narrow width portion11n, and besides, to prevent the excess protrusion of the solder member5nonto the periphery of the bonding region. As a result, since the short-circuit between the adjacent terminals11or others can be suppressed, and since the bonding strength between the terminals11and the solder members5can be improved, the reliability can be further improved than that of the aspect explained in the above-described first embodiment.

Method of Manufacturing Semiconductor Device

Next, a method of manufacturing a semiconductor device of the present embodiment illustrated inFIGS. 32 to 35will be explained. The semiconductor device of the present embodiment can be manufactured by using the same method of manufacturing the semiconductor device explained in the above-described first embodiment. More specifically, in the substrate provision step illustrated inFIG. 10, the present embodiment is different from the above-described first embodiment in that, in each of the plurality of terminals11formed in the product formation regions20aof the wiring substrate20(seeFIG. 11), the narrow width portion11nis connected between the plurality of wide width portions11was illustrated inFIGS. 32 to 35. Moreover, in the above-described chip mounting step, the present embodiment is different from the above-described first embodiment in that the center of the tip surface4sof the protruding electrode4is positioned between the adjacent wide width portions11w1and11w2. It can be manufactured as similar to the above-described first embodiment in the other points, and therefore, the repetitive explanations will be omitted.

However, from the studies made by the inventors of the present application, it has been found that the application of the configuration of the terminals11explained in the present embodiment provides a more preferable manufacturing method than that of the application of the configuration of the terminals11explained in the above-described first embodiment. In the present section, as a modified example of the method of manufacturing the semiconductor device explained in the above-described first embodiment, an aspect in which the application of the configuration of the terminals11explained in the present embodiment is more preferable will be explained.FIG. 40is an explanatory diagram illustrating an outline of manufacturing steps of a semiconductor device that is a modified example of that illustrated inFIG. 10.

A manufacturing step illustrated inFIG. 40is different from the manufacturing step illustrated inFIG. 10explained in the above-described first embodiment in a timing at which the chip mounting step is performed. That is, the manufacturing step illustrated inFIG. 10adopts a method in which, subsequent to the electrical connection of the semiconductor chips2with the wiring substrate20, the connection portion is sealed with the under fill resin6(hereinafter, the method is referred to as “post injection method”). On the other hand, the manufacturing step illustrated inFIG. 40adopts a method in which, prior to the mounting of the semiconductor chip2on the wiring substrate20in the chip mounting step, a sealing material is arranged on the chip mounting region (in a sealing-material arrangement step illustrated inFIG. 40), and then, the semiconductor chip2is pressed onto the wiring substrate20via an adhesive material so as to be electrically connected to the wiring substrate20(hereinafter, the method is referred to as “previous coating method”).

In the case of the post injection system explained in the above-described first embodiment, as illustrated inFIG. 29, resin is supplied from a nozzle27arranged in the vicinity of a space between the semiconductor chip2and the wiring substrate20, the under fill resin6is filled into the space by utilizing capillary action. In this case, since the resin is filled into the space by utilizing the capillary action, process time (time required for the resin injection) for one product formation region20abecomes long. Moreover, a space for moving the nozzle27along the side surface2cof the semiconductor chip2is required. Therefore, a width of the under fill resin6spreading on the periphery of the semiconductor chip2tends to be thick.

On the other hand, in the case of the previous coating method illustrated inFIG. 40, the sealing material is previously arranged between the semiconductor chip2and the wiring substrate20, and therefore, this method is more preferable than the above-described post injection system in that the process time for one product formation region20ais shortened so that the manufacturing efficiency is improved. Moreover, it is not necessary to move the nozzle27along the side surface2cof the semiconductor chip2, and therefore, the amount (protruding amount) of the sealing material6A (seeFIGS. 34 and 35) spreading on the periphery of the semiconductor chip2is reduced, and thus, this method is advantageous more than the post injection system by this reduction from a viewpoint of downsizing of the semiconductor device. Further, even when the arrangements (layouts) of the pad2dformed on the front surface2aof the semiconductor chip2and the protruding electrode4formed on this pad2dare complicated (in such an aspect that the pad2dand the protruding electrode4are formed in the center portion of the front surface2a), this method is more advantageous than the post injection system from a viewpoint of the filling property of the sealing material6A.

However, according to the studies made by the inventors of the present application, it has been found that the amount of the solder member5(seeFIG. 35) in the case of the previous coating method flowing round to the side surface11d(seeFIG. 35) of the narrow portion11n(seeFIG. 35) is less than the amount thereof in the case of the post injection system since the sealing material6A (seeFIGS. 34 and 35) previously arranged in the chip mounting region tends to easily interrupt the deformation of the solder member5in the reflow treatment. When the amount of the solder member5flowing round to the side surface11dof the narrow width portion11nis decreased, the bonding strength between the solder member5and the terminal11is decreased, and therefore, this causes the reduction of the reliability.

Accordingly, as a result of further studies made by the inventors of the present application, it has been found that the bonding strength between the solder member5and the terminal11can be improved even in the case of application of the previous coating method by the application of the configuration of the terminals11of the present embodiment explained with reference toFIGS. 32 to 39since the amount of the solder member5flowing round to the side surface11dof the narrow width portion11nis previously increased prior to the bonding with the protruding electrode4.

Hereinafter, the method of manufacturing the semiconductor device illustrated inFIG. 40will be explained in detail by mainly describing a difference from the aspect explained in the above-described first embodiment.

Substrate Provision Step

First, in a substrate provision step illustrated inFIG. 40, a wiring substrate20A is provided as illustrated inFIG. 41.FIG. 41is an enlarged cross-sectional view illustrating a modified example ofFIG. 12. The wiring substrate20provided in the substrate provision step and illustrated inFIG. 41is different from that of the above-described first embodiment in the shape of the terminal11formed in the product formation region20aand the shape of the solder member5aformed on the terminal11. That is, as explained with reference toFIG. 37, the substrate is different from the wiring substrate20explained in the above-described first embodiment in that each of the plurality of terminals11provided on the wiring substrate20A (seeFIG. 41) provided in the present embodiment has the wide width portion11w1bonded to one end portion NE1 of the narrow width portion11nand has the wide width portion11w2bonded to the other end portion NE2.

Moreover, as illustrated inFIG. 37, the solder member5apreviously formed on each terminal11includes: a solder member5a1that is a portion bonded to the wide width portion11w; a solder member5a3that is a portion bonded to the wide width portion11w2; and a solder member5a2that is a portion bonded to the narrow width portion11n. Further, the widths of the solder members5aland5a3(that is, lengths thereof in a Y direction illustrated inFIG. 37) are larger than the width W2 of the wide width portion11w1and the width W3 of the wide width portion11w2, respectively. On the other hand, the width W4 of the solder member5a2is larger than the width W1 of the narrow width portion11n, but smaller than the widths W2 and W3. As seen from comparison betweenFIGS. 37 and 38, the narrow width portion11nis formed between the adjacent wide width portions11win the present embodiment, and therefore, the width W4 of the solder member5a2is larger than the width W4 of the solder member5a2illustrated inFIG. 38.

As described above, while the solder member5apreviously formed on the terminal11included in the wiring substrate20A provided in the present first embodiment is different from the solder member5aexplained in the above-described embodiment in the shape, the method of forming the solder member5ais the same as the method explained in the above-described first embodiment. For example, the method of forming the solder member explained in the above-described first embodiment with reference toFIG. 13or the method of forming the solder member that is the modified example explained with reference toFIG. 14may be adopted.

Except for the above-described different points, the wiring substrate20A of the present embodiment is the same as the wiring substrate20explained in the above-described first embodiment. For example, as similar to the wiring substrate20illustrated inFIG. 11, the wiring substrate20A is provided with a plurality of product formation regions20ainside the frame portion20b. Moreover, except for the above-described different points, the substrate provision step of the present embodiment is the same as the substrate provision step explained in the above-described first embodiment. Therefore, the repetitive explanations thereof will be omitted.

Sealing-Material Arrangement Step

Next, in a sealing-material arrangement step illustrated inFIG. 40, an insulating sealing material6A is arranged on a chip mounting region2p1of the product formation region20aof the wiring substrate20A as illustrated inFIGS. 42 and 43.FIG. 42is an enlarged cross-sectional view illustrating a state in which the sealing material is arranged on the product formation region of the wiring substrate illustrated inFIG. 41. Moreover,FIG. 43is an enlarged plan view illustrating the product formation region illustrated inFIG. 42.

The sealing material6A arranged on the product formation region20ain the present step is made of an insulating (non-conductive) material (such as a resin material). Moreover, the sealing material6A is made of a resin material that is hardened (raised) in a degree of hardness (hardness) by applying energy thereto, and includes, for example, a thermosetting resin in the present embodiment. Further, the sealing material6A obtained prior to the hardening is softer than the terminal11illustrated inFIG. 42, and therefore, can be deformed by pressing the semiconductor chip2(seeFIG. 34) thereto in the chip mounting step illustrated inFIG. 40.

Moreover, the sealing materials6A obtained prior to the hardening are roughly classified into the following two types depending on difference in a handling method. One of them is made of a paste-like resin (insulating material paste) referred to as NCP (Non-Conductive Paste), and there is a method of application of the material onto the chip mounting regions2p1from a nozzle not illustrated. The other is made of a previously film-like shaped resin (insulating film) referred to as NCF (Non-Conductive Film), and there is a method of carrying and pasting the film-state material onto the chip mounting region2p1. The examples illustrated inFIGS. 42 and 43illustrate an example in which the sealing material6A being the insulating material film (NCF) is arranged on the chip mounting region2p1and is pasted thereon so as to be tightly adhered onto the upper surface3aof the wiring substrate20A. Although not illustrated, an insulating material paste (NCP) may be also used as a modified example.

As illustrated inFIG. 34, the sealing material6A has a function for sealing the protruding electrode4to be the electrical connection portion between the semiconductor chip2and the wiring substrate3. Therefore, it is preferred to arrange the sealing material6A so as not to cause a space between the front surface2aof the semiconductor chip2and the upper surface3aof the wiring substrate3. Therefore, in the present embodiment, as illustrated inFIG. 43, the sealing material6A being the insulating film is arranged so as to cover entirely the chip mounting region2p1to be a planned region on which the semiconductor chip2(seeFIG. 34) is to be formed. In this case, as illustrated inFIG. 42, the solder members5aformed on the terminal11and the periphery of the terminal11are covered with the sealing material6A.

However, when an insulating material paste is used as a modified example, it is only required to cover at least a part of the chip mounting region2p1by the sealing material6A being the insulating paste in the present step since the insulating material paste is pressed and spread in the chip mounting step illustrated inFIG. 40.

Chip Mounting Step

Also, in a chip mounting step illustrated inFIG. 40, as illustrated inFIG. 44, the semiconductor chip2is arranged on the chip mounting region2p1so that the front surface2afaces to the upper surface3aof the wiring substrate20A, and the plurality of terminals11and the plurality of pads2dare electrically connected to each other.FIG. 44is an enlarged cross-sectional view illustrating a state in which the semiconductor chip is mounted on a wiring substrate illustrated inFIG. 42. Moreover,FIG. 45is an enlarged plan view illustrating a planar positional relation between the protruding electrode and the terminal obtained when the semiconductor chip is arranged on the wiring substrate. Further,FIG. 46is an enlarged cross-sectional view taken along a line C-C ofFIG. 45, andFIG. 47is an enlarged cross-sectional view taken along a line D-D ofFIG. 45. Also,FIG. 48is an enlarged cross-sectional view illustrating a state in which the contacted solder members as illustrated inFIG. 46are formed integrally with each other, andFIG. 49is an enlarged cross-sectional view illustrating a state in which the contacted solder members as illustrated inFIG. 47are formed integrally with each other. Moreover,FIG. 50is an enlarged cross-sectional view illustrating a study example ofFIG. 49.

In the present step, first, as illustrated inFIGS. 45 to 47, the semiconductor chip2is arranged on the wiring substrate20A so that the front surface2afaces to the upper surface3aof the wiring substrate20A (in a semiconductor-chip arrangement step). At this time, as illustrated inFIGS. 46 and 47, the center of the tip surface4sof the protruding electrode4is positioned between the wide width portion11w1and the wide width portion11w2of the terminal11. In other words, in the present step, the center of the tip surface4sof the protruding electrode4is arranged on the narrow width portion11nof the terminal11(at a position overlapping the narrow width portion11n). In still other words, in the present step, a solder member5bmounted on the tip surface4sof the protruding electrode4is arranged so as to face to the solder member5a2of the solder members5aformed on the terminal11, the solder member5a2being a portion bonded to the narrow width portion11nof the terminal11.

Moreover, by making the distance between the front surface2aof the semiconductor chip2and the upper surface3aof the wiring substrate20A shorter, the solder members5band5aare in contact with each other. In the present step, for example, by pressing a pressing jig not illustrated from the rear surface2bside (see FIG.44) of the semiconductor chip2, the protruding electrode4is penetrated through the sealing material6A so that the solder members5aand5bcan be in contact with each other. At this time, the sealing member6A is tightly adhered to the front surface2aof the semiconductor chip2.

In the above-described first embodiment, it has been explained that the solder members5aand5bare preferably previously heated (are subjected to the previous thermal step) from the viewpoint of shortening the time required for the temperatures of the solder members5aand5bto reach the melting points or higher. However, as illustrated inFIG. 40, in the case of the application of the previous coating method, the previous heating hardens the sealing material6A, and therefore, is a factor of interruption of the deformation of the solder members5aand5b. Therefore, in the case of the previous coating method, it is preferred to maintain the soft sealing material6A without performing the previous heating treatment.

Next, as illustrated inFIGS. 46 and 47, the solder members5aand5bare heated up to the melting points or higher in the state in which the solder members5aand5bare in contact with each other. When the solder members5aand5bare softened, the distance between the semiconductor chip2and the wiring substrate20A can be further shortened than that in the state illustrated inFIGS. 46 and 47. As explained in the above-described first embodiment, the heating temperature is varied depending on the melting points of the solder members5aand5b. However, when a tin-silver (Sn—Ag) based lead-free solder is applied, they are heated at a temperature from 240° C. to 280° C. In the present step, since the solder members5aand5bare heated in contact with each other, the solder member5acan be heated by, for example, heat transfer from the solder member5b. And, when each of the solder members5aand5bis melted, the solder members5aand5bare formed integrally with each other. That is, the solder members5aand5bare brought into a so-called “wet state”. By cooling the melted solder after the integral formation, the solder member5as illustrated inFIGS. 48 and 49is formed.

Here, as explained in the above-described first embodiment, in the case of the application of the post injection system, since the solder member is melted in a state with a void space in the periphery of the solder members5aand5b, the melted solder is deformed by the surface tension of the solder component so as to form nearly the spherical shape. However, as illustrated inFIG. 40, in the case of the application of the previous coating method, the sealing material6A is arranged in the periphery of the solder members5aand5bin the step of melting the solder members5aand5b. Since the sealing material6A contains the thermosetting resin, the sealing material6A is partially started to be hardened by the heat transfer from the solder members5aand5b. Therefore, the partially-hardened sealing material6A becomes the factor of the interruption of the deformation of the solder members. In other words, in the case of the application of the previous coating method, the fluidity of the melted solder is lower than that in the case of the application of the post injection system.

Therefore, in the case of the application of the previous coating method, the shape of the solder member5is limited in accordance with melting rates of the solder members5aand5band with a hardening rate of the sealing material6A. There are various modified examples as the shape of the solder member5. For example, when the sealing material6A in the periphery of the solder members5aand5bis hardened before the solder members5aand5billustrated inFIG. 47are formed integrally with each other, a side surface of the solder member5nis constricted in the planar view as illustrated inFIG. 49in some cases. In this manner, in the case of the application of the previous coating method, the fluidity of the melted solder is lowered, and therefore, the shapes of the solder members5aand5bobtained prior to the chip mounting step tend to be reflected.

Incidentally, for example, as illustrated inFIG. 38, in the case when, the wide width portion11wis bonded to one end portion of the narrow width portion11nwhile the wide width portion11wis not bonded to the other end portion, the width W4 of the solder member5a2in the bonding region with the protruding electrode4(seeFIG. 39) is narrowed as described above. Therefore, for example, as illustrated inFIG. 50, the width W4 of the solder member5nis smaller than the width of the protruding electrode4in some cases. In other words, in the bonding region with the protruding electrode4, the width of the solder member5nflowing round to the side surface11dof the narrow width portion11nis thin. In this case, the thinning becomes a cause of the reduction of the bonding strength between the solder member5and the terminal11.

On the other hand, according to the present embodiment, as illustrated in the above-describedFIG. 37, prior to the present step, the width W4 of the solder member5a2previously formed in the bonding region with the protruding electrode4can be increased. Moreover, from the viewpoint of increasing the width W4 of the solder member5a2, it is particularly preferred to set the length L1 of the narrow width portion11nillustrated inFIG. 37as large as the width W2 of the wide width portion11w1and the width W3 of the wide width portion11w2or as being smaller than the widths W2 and W3. In this manner, according to the present embodiment, even in the case of the application of the previous coating method in which the fluidity of the melted solder is reduced by the sealing material6A, the width of the solder member5nflowing round to the side surface11dof the narrow width portion11ncan be increased as illustrated inFIG. 49by increasing the width W4 of the solder member5a2.

That is, according to the present embodiment, even in the case of the application of the previous coating method, the width of the solder member5nflowing round to the side surface11dof the terminal11can be increased in the vicinity of the bonding region with the protruding electrode4, and therefore, the bonding strength between the solder member5nand the terminal11can be improved. And, by improving the bonding strength between the solder member5nand the terminal11, the reliability of the semiconductor device1A illustrated inFIG. 32can be improved.

Note that each step of the manufacturing steps ofFIG. 40except for the substrate provision step, the sealing-material arrangement step, and the chip mounting step described above are the same as those of the above-described first embodiment, the repetitive explanations thereof will be omitted.

Modified Example of Second Embodiment

As described above, basic configurations of the present embodiment have been explained, and various modified examples can be applied to the present embodiment. Hereinafter, preferable aspects of the present embodiment will be further explained with modified examples thereof.

First Modified Example

Extending Distance of Wide Width Portion

First, lengths L2 and L3 of the wide width portions11w1and11w2in the X direction illustrated inFIG. 33will be explained.FIG. 51is an enlarged plan view illustrating a terminal in the modified example ofFIG. 33. The terminal30illustrated inFIG. 51is different from the terminal11illustrated inFIG. 33in that the lengths L2 and L3 of the wide width portions11w1and11w2are shorter than the widths W2 (a length in the Y direction) and the width W3 (a length in the Y direction), respectively. That is the same as the terminal11illustrated inFIG. 33in other points. As described above, when the solder member is applied onto the terminal30by using the printing method, and then, the solder member is heated and melted, the melted solder is deformed in accordance with the shape of the terminal30. That is, when there are the wide width portion and the narrow width portion in the metal pattern extending in a certain direction, the melted solder tends to be gathered toward the wide width portion.

This tendency occurs regardless of the lengths L2 and L3 of the wide width portions11w1and11w2, and therefore, the melted solder can be gathered toward the wide width portions11w1and11w2side provided on the both ends of the narrow width portion11nif the wide width portions11w1and11w2are formed. Therefore, as illustrated inFIG. 51, for example, the wide width portions11whaving lengths L2 and L3 that are shorter than the widths W2 and W3 can be applied. A plane area of the terminal30illustrated inFIG. 51can be smaller than that of the terminal11illustrated inFIG. 33, and therefore, the separated distance between the adjacent terminals11can be made wider. In other words, since the plane area of the terminal30illustrated inFIG. 51can be smaller than that of the terminal11illustrated inFIG. 33, an arrangement pitch between the plurality of terminals30can be further reduced.

However, depending on a relation between the plane area of the wide width portion11w1and the applied amount of the entire solder member5a, the amount of the solder member5nto be bonded to the narrow width portion11nis increased as illustrated inFIG. 33in some cases. Therefore, from a viewpoint of reducing the amount of the solder member5a2in the bonding region with the protruding electrode4so as to reduce the protruded amount thereof, it is preferred to form the lengths L2 and L3 of the wide width portions11w1and11w2to be long as illustrated inFIG. 33. According to the studies made by the inventors of the present application, by forming the lengths L2 and L3 of the wide width portions11w1and11w2to be longer than the widths W2 and W3, respectively, the amount of the solder member5narranged on the narrow width portion11ncan be stably reduced.

Second Modified Example

Extending Distance of Narrow Width Portion

Next, the separated distance L1 between the end portions NE1 and NE2, that is, an extending distance of the narrow width portion11nwill be explained.FIG. 52is an enlarged plan view illustrating a terminal in another modified example ofFIG. 33. The terminal illustrated inFIG. 52is different from the terminal11illustrated inFIG. 33in that the separated distance L1 between the wide width portions11w1and11w2, that is, the extending distance of the narrow width portion11nalong the X direction, is shorter than the width WB of the protruding electrode4. That is the same as the terminal11illustrated inFIG. 33in other points.

As illustrated inFIG. 52, when the separated distance L1 between the wide width portions11w1and11w2is shorter than the width WB of the protruding electrode4, a part of the tip surface of the protruding electrode4is arranged at a position where it overlaps each of the wide width portions11w1and11w2. In this case, in comparison with the terminal11illustrated inFIG. 33, the plane area of the narrow width portion11nis relatively small, and therefore, the protruded amount of the solder member5nis easily increased.

However, as explained by usingFIG. 37, when the narrow width portion11nis bonded between the adjacent wide width portions11w1and11w2, the amount of the solder member5a2formed on the narrow width portion11nis less than the amounts of the solder members5a1and5a3formed on the wide width portions11w1and11w2. This phenomenon similarly occurs also in the case of the short extending distance of the narrow width portion11nas seen in the terminal31. Therefore, by bonding the protruding electrode4and the terminal31to each other so that the center of the tip surface of the protruding electrode4overlaps the narrow width portion11n, the protruding electrode4can be bonded to a region where the amount of the solder member5a(seeFIG. 37) is relatively small. Moreover, in the case of the arrangement of the wide width portions11w1and11w2in the vicinity of the narrow width portion11nthat is the bonding region with the protruding electrode4, when the solder members5aand5b(seeFIG. 47) are melted to be formed integrally with each other, the melted solder tends to partially flow out toward the wide width portions11w1and11w2. Therefore, by arranging the center of the tip surface of the protruding electrode4so as to be positioned between the wide width portions11w1and11w2in the above-described chip mounting step, the protruded amount of the solder member5ncan be reduced.

Moreover, in the case of the terminal31, the plane area of the bonding region with the protruding electrode4which is formed of the wide width portions11w1and11w2and the narrow width portion11ncan be smaller than that of the terminal11illustrated inFIG. 33. Therefore, from the viewpoint of reducing the plane area of the terminal11, the terminal31is more preferably used.

Moreover, as described above, in the case of the application of the previous coating method when the sealing material6A is arranged, the shape of the previously-formed solder member5ais difficult to deform, and therefore, it is preferred to increase the amount of the solder member5a2flowing round to the side surface11dof the narrow width portion11nfrom the viewpoint of improving the bonding strength between the solder member5and the narrow width portion11n. In the case of the terminal31, since the extending distance of the narrow width portion11nis short, the amount of the solder member5a2flowing round to the side surface11dof the narrow width portion11ncan be more than that of the terminal11illustrated inFIG. 33. Therefore, from the viewpoint of improving the bonding strength between the terminal11and the solder member5, the separated distance L1 between the wide width portions11w1and11w2is preferably shorter than the width WB of the protruding electrode4as illustrated inFIG. 52.

As described above, from the viewpoint of improving the bonding strength between the solder member5and the narrow width portion11nand reducing the protruded amount of the solder member5n, it is particularly preferred to form the separated distance L1 between the wide width portions11w1and11w2to be equal to the width WB of the protruding electrode4.

Third Modified Example

Shape of Terminal

Next, a modified example in which shapes of members to be bonded to the wide width portion11w1and the wide width portion11w2are made equal to each other will be explained.FIG. 53is an enlarged plan view illustrating a terminal in another modified example ofFIG. 33. The terminal32illustrated inFIG. 53is different from the terminal11illustrated inFIG. 33in that a narrow width portion11n3is formed on an opposite side of a side on which the wide width portion11w1is bonded to the narrow width portion11n. That is the same as the terminal11illustrated inFIG. 33in other points.

In addition to the wide width portions11w1and11w2and the narrow width portion11n, the terminal32illustrated inFIG. 53is provided with the following portion. That is, the terminal32has a narrow width portion11n2that is a portion having a width W5 (a length along the Y direction) smaller than the widths W2 and W3 (lengths along the Y direction) and being arranged between the wide width portion11w2and a wire14. The narrow width portion11n2is coated with a solder resist film16, and is made of the same material and is formed with the same width as that of the wire14electrically connected (integrally formed) with the terminal32. Note that the narrow width portion11n2also has the terminal11illustrated inFIG. 33, the terminal30illustrated inFIG. 51, and the terminal31illustrated inFIG. 52.

Moreover, the terminal32has a narrow width portion11n3that is a portion having a width W6 (a length in the Y direction) smaller than the widths W2 and W3 and being arranged on a side H2 on an opposite side of a side H1 of the wide width portion11w1, which is bonded to the narrow width portion11n. That is, the terminal32has the narrow width portion11n3that is bonded to the side opposite to the narrow width portion11nthrough the wide width portion11w1.

Moreover, the width W5 of the narrow width portion11n2and the width W6 of the narrow width portion11n3are equal to each other, and are also equal to the width (the length in the Y direction) of the wire14, in, for example, the example illustrated inFIG. 53. In the case of the terminal11illustrated inFIG. 33, it has been explained that the areas of the wide width portions11w1and11w2and the shapes thereof are preferably made equal to each other from the viewpoint of setting the amounts of the melted solder gathered onto the wide width portion11w1and the melted solder gathered onto the wide width portion11w2to be equal to each other. However, while the narrow width portion11n2is bonded to the wide width portion11w2, a portion corresponding to the narrow width portion11n2is not bonded to the wide width portion11w1, and therefore, they are technically different from each other in the gathering state of the melted solder.

Accordingly, in the terminal32illustrated inFIG. 53, the narrow width portion11n3having the same width W6 as that of the narrow width portion11n2is bonded to the wide width portion11w1. Thus, the amount of the melted solder that gathers to the wide width portion11w1and the amount of the melted solder that gathers to the wide width portion11w2are made equal to each other with high accuracy.

Moreover, the further application of the configuration of the terminal32illustrated inFIG. 53can be applied to the configuration illustrated inFIG. 54.FIG. 54is an enlarged plan view illustrating a modified example ofFIG. 32. For example, each of the aspects described above has been explained as the aspect in which, while one end portion of each of the terminals11,30,31, and32is not bonded to another conductor pattern, the other end portion thereof is bonded to the wire14.

In an example illustrated inFIG. 54, the both end portions of the terminal32are bonded to the respective wires14. A wiring substrate35illustrated inFIG. 42is different from the wiring substrate3illustrated inFIG. 32in that the both ends of the terminal32are bonded to the respective wires14coated with the solder resist film16. That is the same as the wiring substrate3in other points.

As illustrated inFIG. 54, when the both end portions of the terminal32are bonded to the respective wires14, the terminals can be bonded to a wiring layer in a lower layer (a wire of the wiring layer in the lower layer) via either one of the wires14. That is, while it is required to form a via wire in order to electrically connect to the wire of the wiring layer in the lower layer, the both end portions of the terminal32are bonded to the respective wires14in the case of the wiring substrate35. Therefore, the degree of freedom in layout for the via wire can be improved.

Other Modified Example

For example, in the above-described embodiments, the explanations have been made regarding the aspect in which the plurality of protruding electrodes4formed on the peripheral edge of the semiconductor chip2are bonded to the terminals,11,30,31, and32, formed on the wiring substrates3,20,20A, and35. However, for example, as similar to the semiconductor device1B illustrated inFIG. 55, the pad2dand the protruding electrode4are formed in the center portion of the front surface2aof the semiconductor chip2, and this protruding electrode4is electrically connected to the wiring substrate3in some cases.FIG. 55is a cross-sectional view illustrating a semiconductor device in a modified example ofFIG. 2. In this case, the configurations of the terminals11,30,31, and32explained in the above-described embodiments can be applied as bonding leads bonded to the protruding electrode4formed in the center portion of the front surface2aof the semiconductor chip2.

Moreover, for example, in the above-described embodiments, the explanations have been made regarding the semiconductor device1in which one semiconductor chip2is mounted on the wiring substrate3by using the flip-chip mounting system. However, the number of the semiconductor chips mounted on the wiring substrate is not limited to one. For example, the invention can be applied to a semiconductor device of an SIP (System in Package) type in which a plurality of semiconductor chips are stacked. Moreover, for example, the invention can be applied to a semiconductor device referred to as POP (Package on Package) formed by stacking another semiconductor device on the wiring substrate3.

Further, for example, in the above-described embodiments, the explanations have been made regarding the aspect of the bonding with the protruding electrode4made of, for example, copper (Cu) and formed into the column shape, via the solder member5. However, various modified examples can be applied. For example, even in usage of a protruding electrode made of gold (Au) and formed by using a ball bonding technique is used, when the protruding electrode is bonded to a solder member coated on the terminal11in a state in which a solder member has been previously adhered on the protruding electrode, the short-circuit failure occurs in some cases depending on the protruded amount of the solder member as described above. Therefore, by using the techniques explained in the above-described embodiments, this problem can be suppressed.

Further, for example, in the above-described embodiments, as the explanations for the method of manufacturing the semiconductor device, the explanations have been made regarding the aspect of usage of so-called multiple-piece taking substrate having the plurality of product formation regions20a. However, as a modified example, a wiring substrate previously separated into individual product formation regions each corresponding to one semiconductor device can be also used. In this case, the separating step illustrated inFIGS. 10 and 40can be omitted.