VOLTAGE REGULATOR

The voltage regulator includes: an error amplification circuit, outputting a signal amplifying a difference between a reference voltage and a feedback voltage; a source ground amplification circuit, amplifying the signal supplied from the error amplification circuit and outputting the signal as a control signal; and an output transistor, including a gate to which the control signal is supplied and outputting an output voltage. The source ground amplification circuit includes: a phase advance compensation circuit, containing a resistor and a capacitor; a load, containing a resistor and an offset generation element generating an offset voltage; and a transistor, containing: a gate receiving the signal output from the error amplification circuit; a source being connected with a first end of the resistor and a first end of the capacitor, the resistor and the capacitor being contained in the phase advance compensation circuit; and a drain connected with the load.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefits of Japanese application no. 2023-047165, filed on Mar. 23, 2023 and Japanese application no. 2023-213500, filed on Dec. 19, 2023. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND

Technical Field

The present invention relates to a voltage regulator.

Description of Related Art

In general, a voltage regulator may receive a power voltage and generate a constant output voltage, and maintain the output voltage at a constant value even if the power voltage or a load current varies. For example, a voltage regulator includes a reference voltage source, an error amplification circuit, an output transistor, and a phase compensation circuit using a Miller capacitor.

However, in the conventional voltage regulator, since delay compensation according to the Miller capacitor is used for phase compensation of a control loop, a delay occurs in the response of the output voltage to a sudden change of a load current.

SUMMARY

The present invention provides a voltage regulator in which an output voltage responds to a sudden change of a load current more quickly than the conventional art.

According to at least one aspect of the present invention, a voltage regulator includes: an error amplification circuit, outputting a signal amplifying a difference between a reference voltage and a feedback voltage; a source ground amplification circuit, amplifying the signal supplied from the error amplification circuit and outputting the signal as a control signal; and an output transistor, including a gate to which the control signal is supplied and outputting an output voltage. The source ground amplification circuit includes: a phase advance compensation circuit, containing a resistor and a capacitor; a load, containing an offset generation element and a resistor, the offset generation element generating an offset voltage; and a first transistor, containing a gate receiving the signal output from the error amplification circuit, a source connected with a first end of the resistor and a first end of the capacitor, the resistor and the capacitor being contained in the phase advance compensation circuit, and a drain connected with the load.

According to the present invention, a voltage regulator in which an output voltage responds to a sudden change of a load current more quickly than the conventional art can be provided.

DESCRIPTION OF THE EMBODIMENTS

In the following, a voltage regulator according to the embodiments of the present invention is described based on the drawings.

First Embodiment

FIG.1is a circuit diagram of a voltage regulator100which is an example of a voltage regulator according to a first embodiment of the present invention.

The voltage regulator100includes a power terminal101, a ground terminal102, a reference voltage source120, an error amplification circuit121, a resistor122, a PMOS transistor123, an NMOS transistor124, a resistor125, a capacitor126, a PMOS transistor127, a resistor128, a resistor129, and an output terminal110. The ground terminal102is a power terminal that supplies a power voltage (referred to as “ground voltage” in the following) of OV (zero volt) as an example of a power voltage serving as a reference of a circuit operation. The resistor122, the PMOS transistor123, the NMOS transistor124, the resistor125, and the capacitor126form a source ground amplification circuit103.

The source ground amplification circuit103includes a load, a phase advance compensation circuit, and the NMOS transistor124. The load contains the resistor122and the PMOS transistor123. The phase advance compensation circuit includes the resistor125and the capacitor126. In addition, the source ground amplification circuit103includes an input port103aand an output port103b. Here, the input port103ais a connection point of an output terminal of the error amplification circuit121and the gate of the NMOS transistor124, and is a node that receives a signal supplied from the error amplification circuit121. The output port103bis a connection point among the drain of the NMOS transistor124, the gate and the drain of the PMOS transistor123, and the gate of the PMOS transistor127, and is a node that outputs a control voltage to the gate of the PMOS transistor127.

In the reference power source120, a port is connected with a non-inverting input terminal (+) of the error amplification circuit121and the other port is connected with the ground terminal102.

In the NMOS transistor124, the gate is connected with the output terminal of the error amplification circuit121, the source is connected with a first end of the resistor125and a first end of the capacitor126, and the drain is connected with the gate and the drain of the PMOS transistor123and the gate of the PMOS transistor127.

In the resistor122, a first end is connected with the power terminal101, and a second end is connected with the source of the PMOS transistor123.

In the resistor125, a second end is connected with the ground terminal102. In the resistor126, a second end is connected with the ground terminal102.

In the PMOS transistor127as the output transistor, the source is connected with the power terminal101, and the drain is connected with the output terminal110and a first end of the resistor128. In the resistor128, a second end is connected with a first end of the resistor129and an inverting input terminal (−) of the error amplification circuit121. In the resistor129, a second end is connected with the ground terminal102.

Then, an operation of the voltage regulator100is described.

The power terminal101supplies a predetermined power voltage. The ground terminal102supplies the ground voltage.

The output terminal110is an output terminal of the voltage regulator100, and sets the voltage of the output terminal110as an output voltage VOUT. The resistor128and the resistor129divide the output voltage VOUT to generate a feedback voltage VFB. The error amplification circuit121compares the amplitudes of the feedback voltage VFB and the reference voltage VREF output from the reference voltage source to output an error voltage VERR from the output terminal. The error voltage VERR is supplied to the source ground amplification circuit103(more specifically, the gate of the NMOS transistor124).

In the source ground amplification circuit103, an advance compensation is generated by using the NMOS transistor124, the resistor125, and the capacitor126. In addition, an offset voltage is generated between two ends, i.e., the source and the drain, of the PMOS transistor123serving as an offset generation element. That is, the offset generation element is configured by the PMOS transistor123. In the source ground amplification circuit103, since the offset voltage is generated between the source and the drain of the PMOS transistor123, the impedance of the load is reduced, and the gain is reduced. A signal amplified by the source ground amplification circuit103is supplied, as a control circuit, from the output port103bto the gate of the PMOS transistor127. The PMOS transistor127receives, at the gate, a voltage VGATE as the control signal, and outputs, at the drain, an output voltage VOUT. The output voltage VOUT is supplied to the output terminal110connected with the drain of the PMOS transistor127.

Then, the reason why the impedance of the load of the source ground amplification circuit103, the load containing the resistor122and the PMOS transistor123, is reduced will be explained.

Since the gate and the drain of the PMOS transistor123are connected, the impedance between the source and the gain is reduced, and the PMOS transistor123operates as an offset generation element that generates an offset voltage between the source and the gain. A control signal for conducting the PMOS transistor127, that is, a voltage of the PMOS transistor127between the gate and the source, is generated by using the offset voltage and a voltage across the resistor122. In this way, since the offset voltage is present in the load, the voltage of the resistor122(voltage across the resistor122) is lower than the case where the offset voltage is not present. As a result, the impedance of the load of the source ground amplification circuit103is reduced.

According to the voltage regulator100, by adding an advance compensation of the control loop to the source ground amplification circuit103and further reducing the gain, the phase margin of the voltage regulator100can be secured. In addition, according to the voltage regulator100, since a delay compensation according to a Miller capacitor is not used in the control loop, the output voltage can more quickly respond to a sudden change of the load current than a voltage regulator using the delay compensation according to the Miller capacitor. That is, the delay time of the response of the output voltage to a sudden change of the load current can be shorter than the conventional art.

Second Embodiment

FIG.2is a circuit diagram of a voltage regulator200which is an example of a voltage regulator according to a second embodiment of the present invention.

Compared with the voltage regulator100, the voltage regulator200differs in further including an overcurrent protection circuit106, and the rest of the voltage regulator200is substantially the same as the voltage regulator100. Thus, the description of the embodiment focuses on the overcurrent protection circuit106. For components repeating those of the voltage regulator100, the same reference symbols are used, and the description thereof is omitted.

The voltage regulator200includes the power terminal101, the ground terminal102, the reference voltage source120, the error amplification circuit121, the resistor122, the PMOS transistor123, the NMOS transistor124, the resistor125, the capacitor126, the PMOS transistor127, the resistor128, the resistor129, an overcurrent protection circuit106, and the output terminal110.

The overcurrent protection circuit106includes a PMOS transistor131, a resistor132, and an NMOS transistor133. The PMOS transistor131and the resistor132form a voltage generation circuit that generates a voltage VN1at a node N1that serves as a connection point between the PMOS transistor131and the resistor132.

The overcurrent protection circuit106has connection ports106ato106dfor external connection of the overcurrent protection circuit106. The connection port106ais connected with the output terminal of the error amplification circuit121and the gate of the NMOS transistor124. The connection port106bis connected with the ground terminal102. The connection port106cis connected with the gate and the drain of the PMOS transistor123, the gate of the NMOS transistor124, and the gate of the PMOS transistor127, and receives the voltage VGATE. The connection port106dis connected with the power terminal101.

In the PMOS transistor131, the source is connected with the power terminal101, the gate is connected with the connection point among the drain of the NMOS transistor124, the gate and the drain of the PMOS transistor123, and the gate of the PMOS transistor127, and the drain is connected with a port of the resistor132. In the resistor132, the other port is connected with the ground terminal102. In the NMOS transistor133, the drain is connected with the connection point of the output terminal of the error amplification circuit121and the gate of the NMOS transistor124, the source is connected with the ground terminal102, and the gate is connected with the node N1. That is, as a switch, the NMOS transistor133switches a path connecting the output terminal of the error amplification circuit121and the ground terminal102between a conductive (ON) state and an open (OFF) state in accordance with the voltage VN1as an example of a voltage based on the control signal.

Then, an operation of the voltage regulator200is described. In the description of the operation of the voltage regulator200, the description mainly focuses on the case where the output terminal110is shorted to the ground terminal102, and the overcurrent protection circuit106is operating.

The same voltage VGATE is applied to the gate of the PMOS transistor131and the gate of the PMOS transistor127that are the same node. Proportional drain currents flow through the PMOS transistor131and the PMOS transistor127. The drain current of the PMOS transistor127flows to the resistor132and generates the voltage VN1at the node N1.

Assuming that the drain currents of the PMOS transistors127,131increase, and the voltage VN1exceeds a threshold voltage of the NMOS transistor133, the NMOS transistor133is turned ON, and the gate voltage of the NMOS transistor124decreases. In the case where the gate voltage of the NMOS transistor124decreases, the voltage VGATE increases. Thus, the drain current of the PMOS transistor127and the drain current of the PMOS transistor131decrease. In this way, in the voltage regulator200, a negative feedback loop is formed, and the overcurrent protection circuit106performs an overcurrent protection operation in accordance with the negative feedback of the negative feedback loop formed in the voltage regulator200.

Like the voltage regulator100, according to the voltage regulator200, the output voltage can more quickly respond to a sudden change of a load current than the conventional art. In addition, in the voltage regulator200, the negative feedback loop that turns ON the PMOS transistor133to decrease the drain currents of the PMOS transistors127,131in the case where the drain currents of the PMOS transistors127,131increase and the voltage VN1exceeds the threshold voltage of the NMOS transistor133is formed. Thus, it is possible to carry out overcurrent protection. According to the voltage regulator200, the source ground circuit103is included in the negative feedback loop that is formed. Thus, the overcurrent protection function can quickly respond to a sudden change of the load current. That is, the overcurrent protection function can more quickly respond to a sudden change of the load current than the conventional art.

Although the embodiment of the present invention has been described above, the present invention is not limited to the above embodiment, and various changes may be made within the range without departing from the spirit of the present invention. These embodiments and their modifications are included within the scope and gist of the present invention, as well as within the scope of the present invention described in the claims and its equivalents.