Solid-state imaging device

A plurality of pixels are two-dimensionally arranged on a semiconductor substrate. Each of the pixels includes: two photodiodes each generating charge by photoelectric conversion; first and second memories spaced apart from each other between the two photodiodes as viewed in cross section; a first readout gate reading charge from the two photodiodes to the first memory; and a second readout gate reading charge from the two photodiodes to the second memory.

BACKGROUND

The present disclosure relates to a solid state imaging device that can be used for distance measurement.

Solid state imaging devices known in the art use a time of flight (TOF) technique for distance measurement. Such a solid state imaging device detects an image of light reflected from an object irradiated with pulsed light from a light emitting diode (LED), and obtains distance information based on a delay time of the reflected light with respect to the irradiation light.

Specifically, a pixel structure called a charge distribution structure, for example, is used. In this structure, a plurality of capacitors are connected to a single photodiode generating charge by photoelectric conversion. Charges are read from the photodiode at different timings in synchronization with light emission from an LED, and the read charges are separately accumulated in the capacitors. The distance to an object is calculated based on the amount of the charges accumulated in the capacitors (see Japanese Unexamined Patent Publication No. 2008-89346).

SUMMARY

The known charge distribution pixel structure includes a large photodiode. This prevents an electric field for reading charge from the photodiode from being effectively formed. In addition, the distance over which charge travels from the photodiode is long. The foregoing factors make it difficult to read charge from the photodiode within a sufficiently short time relative to the TOF.

It is an object of the present disclosure to increase the speed at which charge is read from a photodiode of a solid state imaging device.

According to the present disclosure, a photodiode forming part of a single pixel is divided into a plurality of smaller photodiodes, between each adjacent pair of which a plurality of memories are interposed to accumulate charge.

A solid state imaging device according to an aspect of the present disclosure includes a plurality of pixels which are two-dimensionally arranged on a semiconductor substrate, each of the pixels including: two photodiodes each generating charge by photoelectric conversion; first and second memories spaced apart from each other between the two photodiodes as viewed in cross section; a first readout gate reading charge from the two photodiodes to the first memory; and a second readout gate reading charge from the two photodiodes to the second memory.

Driving the first readout gate allows a portion of the charge generated by each of the two photodiodes to be read, at high speed, into the first memory interposed between the two photodiodes. Driving the second readout gate at a different timing from the timing at which the first readout gate is driven allows another portion of the charge generated by each of the two photodiodes to be read, at high speed, into the second memory interposed between the two photodiodes.

According to the present disclosure, a photodiode forming part of a single pixel is divided into a plurality of smaller photodiodes, between each adjacent pair of which a plurality of memories are interposed to accumulate charge. This reduces the distance over which charge travels from each photodiode to an associated one of the memories. As a result, the speed at which charge is read from the photodiode of a solid state imaging device can be increased.

DETAILED DESCRIPTION

FIG. 1is a plan view showing a pixel structure of a solid state imaging device according to an embodiment of the present disclosure. The solid state imaging device shown inFIG. 1includes a plurality of pixels which are two-dimensionally arranged on a semiconductor substrate.FIG. 1shows one rectangular pixel100having an aspect ratio of substantially 1:2, and other pixels arranged in a staggered manner around the pixel100. The other pixels also have a shape and a structure identical or similar to those of the pixel100shown in detail inFIG. 1.

The pixel100includes first and second photodiodes PD1and PD2, first and second memories MEM1and MEM2, first and second readout gates RG1and RG2, overflow drains OFDs, first and second floating diffusion portions FD1and FD2, first and second transfer gates TG1and TG2, a reset transistor RS, and a source follower (an amplifier transistor) SF. The first and second floating diffusion portions FD1and FD2, the drain of the reset transistor RS, and the gate of the source follower SF are connected together through a metal interconnect5.

The first and second photodiodes PD1and PD2are devices generating charge by photoelectric conversion, and are spaced apart from each other. The first and second memories MEM1and MEM2are spaced apart from each other between the first and second photodiodes PD1and PD2as viewed in cross section. The first readout gate RG1is a polysilicon layer, and overlaps with the borders between the first memory MEM1and the first and second photodiodes PD1and PD2to read charge from the first and second photodiodes PD1and PD2to the first memory MEM1. The second readout gate RG2is a polysilicon layer, and overlaps with the borders between the second memory MEM2and the first and second photodiodes PD1and PD2to read charge from the first and second photodiodes PD1and PD2to the second memory MEM2. The overflow drains OFDs each discharge a surplus of charge from an associated one of the first and second photodiodes PD1and PD2, and are each provided on a side of the associated one of the first and second photodiodes PD1and PD2remote from the first and second memories MEM1and MEM2.

The first and second floating diffusion portions FD1and FD2are adjacent to the first and second memories MEM1and MEM2, respectively. The first transfer gate TG1is a polysilicon layer, and is used to transfer charge from the first memory MEM1to the first floating diffusion portion FD1. The second transfer gate TG2is a polysilicon layer, and is used to transfer charge from the second memory MEM2to the second floating diffusion portion FD2.

The reset transistor RS is used to reset charge accumulated in the first and second floating diffusion portions FD1and FD2. The source follower RS is a transistor configured to output a voltage signal in response to the charge accumulated in the first and second floating diffusion portions1-D1and FD2. The reference character PW inFIG. 1denotes a contact to a p-well provided in an n-type semiconductor substrate.

FIG. 2is a cross-sectional view taken along line II-II shown inFIG. 1. The first and second silicon photodiodes PD1and PD2are formed in a surface of a semiconductor substrate9made of silicon with an isolation region10interposed therebetween as a shallow trench isolation (STI) region. Diffusion layers serving as the overflow drains OFDs are formed outward of the first and second photodiodes PD1and PD2, respectively. A polysilicon layer11forming various gates, and metal interconnect layers12are sequentially formed on the surface of the semiconductor substrate9. Furthermore, lenses13(not shown inFIG. 1) are provided to effectively concentrate light onto the first and second photodiodes PD1and PD2.

FIG. 3is a cross-sectional view taken along line III-III shown inFIG. 1. As shown inFIG. 3, the first memory MEM1is formed between the first and second photodiodes PD1and PD2as viewed in cross section. The first readout gate RG1is formed as a portion of the polysilicon layer11overlapping with the borders between the first memory MEM1and the first and second photodiodes PD1and PD2. Furthermore, to prevent light from entering the first memory MEM1, a light blocking film14(not shown inFIG. 1) is made of, for example, tungsten or tungsten nitride, and covers upper and side surfaces of the first readout gate RG1. Two floating diffusion portions “FDs” shown inFIG. 3are each a floating diffusion portion of an adjacent pixel.

FIG. 4is a cross-sectional view taken along line IV-IV shown inFIG. 1. The first and second memories MEM1and MEM2are formed in the surface of the semiconductor substrate9with the isolation region10as an STI region interposed therebetween. The first and second floating diffusion portions FD1and FD2are adjacent to the first and second memories MEM1and MEM2, respectively. The first transfer gate TG1is a portion of the polysilicon layer11, and is used to transfer charge from the first memory MEM1to the first floating diffusion portion FD1. The second transfer gate TG2is a portion of the polysilicon layer11, and is used to transfer charge from the second memory MEM2to the second floating diffusion portion FD2.

FIG. 5is a circuit diagram of the single pixel100of the solid state imaging device shown inFIG. 1. The first and second photodiodes PD1and PD2are each connected through an associated one of the overflow drains OFDs to a power supply VDD. The first and second photodiodes PD1and PD2are connected through the first and second readout gates RG1and RG2to the first and second memories MEM1and MEM2, respectively. The first and second memories MEM1and MEM2are connected through the first and second transfer gates TG1and TG2to the first and second floating diffusion portions FD1and FD2, respectively. In this embodiment, the first and second floating diffusion portions FD1and FD2are connected together through the metal interconnect5as described above, and are thus shown inFIG. 5as a single floating diffusion portion FD1/FD2. This floating diffusion portion FD1/FD2is connected to a power supply VDDC through the reset transistor RS, and is connected also to the gate of the source follower SF. The source follower SF is a transistor interposed between the power supply VDD and a signal line SIG.

FIG. 6is a timing diagram for explaining the principal of how the solid state imaging device shown inFIG. 1measures the distance to an object. In this embodiment, L is the distance from an LED to an object to which pulsed light is emitted from the LED, and Tp is the period of time during which the LED is in an on state, i.e., the period of time from a time t11to a time t13. The light emitted travels over the distance 2 L at a speed c (=3.0×108 m/s) before returning to the solid state imaging device by being reflected off the object. Thus, the following formula (1) holds.
L=c×(Δt/2)  (1)
where Δt is a delay period of time of received light with respect to the light emitted. A pulse of the received light rises at the time t12at which the period of time Δt elapses since the time t11, and falls at the time t14at which the period of time Δt elapses since the time t13. Thus, the first and second photodiodes PD1and PD2generate charge by photoelectric conversion only from the time t12to the time t14.

Meanwhile, the first readout gate RG1is opened only during the period of time Tp from the time t11to the time t13, and the second readout gate RG2only during a period of time starting from the time t13and being equal to the period of time Tp. In this case, the following relation holds.
Δt/Tp=S2/(S1+S2)  (2)
where S1is the amount of charge read via the first readout gate RG1to the first memory MEM1, and S2is the amount of charge read via the second readout gate RG2to the second memory MEM2. The following formula holds based on the formulae (1) and (2).
L=(c×Tp)/2×S2/(S1+S2)  (3)
That is to say, the distance L to the object can be determined based on the amounts S1and S2of charge distributed to the first and second memories MEM1and MEM2.

FIG. 7is a timing diagram for explaining how the solid state imaging device shown inFIG. 1operates. A period of time to a time t0is a reset period of time T0, a period of time from the time t0to a time t1is a signal accumulation period of time T1, and a signal reading period of time T2starts from the time t1.

During the reset period of time T0, the overflow drains OFD are off, the first and second transfer gates TG1and TG2are on, the power supply VDDC is on, and the reset transistor RS is on. Next, the LED is blinked, and the first and second readout gates RG1and RG2are alternately driven by pulses. During this period of time, the charges generated in the first and second photodiodes PD1and PD2flow to the first and second memories MEM0and MEM1, respectively. However, since the first and second transfer gates TG1and TG2are on, the charges flow through the reset transistor RS to the power supply VDDC without being accumulated in the first and second memories MEM1and MEM2.

Next, the first and second transfer gates TG1and TG2, the power supply VDDC, and the reset transistor RS are all turned off. From this time, the signal accumulation period of time T1starts. During the signal accumulation period of time T1, the LED blinks. The reflected LED light is photoelectrically converted by the first and second photodiodes PD1and PD2. During this period of time, since the first and second readout gates RG1and RG2are alternately driven by pulses, the charges generated in the first and second photodiodes PD1and PD2are distributed to the first and second memories MEM1and MEM2in accordance with the length of the delay period of time Δt described above. This charge distribution operation is preferably repeated multiple times. Consequently, needed signal charges S1and S2are accumulated in the first and second memories MEM1and MEM2, respectively.

Next, the first and second readout gates RG1and RG2stop being driven by pulses, and the overflow drains OFDs are turned on. From this time, the signal reading period of time T2starts. During the signal reading period of time T2, charge is selectively transferred to the floating diffusion portion FD1/FD2through control over the first and second transfer gates TG1and TG2. Specifically, opening the first transfer gate TG1allows charge accumulated in the first memory MEM1to be transferred to the floating diffusion portion FD1/FD2, whereas opening the second transfer gate TG2allows charge accumulated in the second memory MEM2to be transferred to the floating diffusion portion FD1/FD2. The detailed description of driving during the signal reading period of time T2will be omitted.

As can be seen from the foregoing description, according to this embodiment, a photodiode forming part of the single pixel100is divided into the two smaller photodiodes PD1and PD2, between which the two memories MEM1and MEM2are interposed to accumulate charge. This reduces the distance over which charge travels from each of the photodiodes PD1, PD2to an associated one of the memories MEM1and MEM2. As a result, the speed at which charge is read from the photodiode PD1, PD2increases.

In addition, arranging a plurality of pixels in a staggered manner improves the area efficiency. This allows the photodiodes PD1and PD2and the memories MEM1and MEM2to have a large area. Thus, more signal charges can be handled.

Furthermore, the first and second floating diffusion portions FD1and FD2to each of which an associated one of the two transfer gates TG1and TG2selectively transfers signal charge are connected together through the metal interconnect5, and the source follower SF serving as an amplifier transistor for signal output is connected to the first and second floating diffusion portions FD1and FD2in common. This can reduce variations in output signal, thus achieving more accurate distance measurement.

In this embodiment, the readout gates RG1and RG2are disposed over the entire upper surfaces of the memories MEM1and MEM2, respectively. However, the readout gates RG1and RG2may each overlap with only the borders between an associated one of the memories MEM1and MEM2and the photodiodes PD1and PD2.

A STI region is used as the isolation region10. However, the isolation region10may be formed by implantation. The semiconductor substrate9should not be limited to an n-type substrate, but may be a p-type substrate.

An on-chip color filter layer may be embedded in an opening of one of the metal interconnect layers12, may be interposed between one of the metal interconnect layers12and the lenses13, or may cover the lenses13.

FIG. 8is a cross-sectional view showing a variation of the pixel structure shown inFIG. 3. As shown inFIG. 8, photodiodes PD1and PD2may each extend under memories MEM1and MEM2. Such a configuration allows the photodiodes PD1and PD2to each have its area increased.

FIG. 9is a cross-sectional view showing another variation of the pixel structure shown inFIG. 3. In the example shown inFIG. 9, two photodiodes PD1and PD2are connected together through a region under the memories MEM1and MEM2. Such a configuration allows the photodiodes PD1and PD2to each have its area further increased.

FIG. 10is a plan view showing a variation of the pixel structure shown inFIG. 1. Just like the pixel100shown inFIG. 1, a pixel200shown in a central portion ofFIG. 10includes first and second photodiodes PD1and PD2, first and second memories MEM1and MEM2, first and second readout gates RG1and RG2, overflow drains OFD, first and second floating diffusion portions FD1and FD2, and first and second transfer gates TG1and TG2. InFIG. 10, the first floating diffusion portion FD1of the pixel200, a first floating diffusion portion FD1of one of pixels which are arranged in a staggered manner around the pixel200which is adjacent to the pixel200in the upper left direction in the drawing, the drain of a reset transistor RS, and the gate of a source follower SF are connected together through a metal interconnect5. The second floating diffusion portion FD2of the pixel200, a second floating diffusion portion FD2of another one of pixels which are arranged in a staggered manner around the pixel200which is adjacent to the pixel200in the lower left direction in the drawing, and the gate of a source follower SF are connected together through a metal interconnect6.

According to the configuration shown inFIG. 10, connecting the source follower SF serving as an amplifier transistor for signal output to the first or second floating diffusion portions FD1or FD2of two adjacent pixels in common allows, for example, signals of charges accumulated in the first and second floating diffusion portions FD1and FD2of the pixel200to be output at the same time. Thus, a memory for temporarily storing data can be omitted from an arithmetic circuit at a subsequent stage.

FIG. 11is a plan view showing another variation of the pixel structure shown inFIG. 1.FIG. 11shows an example in which the single pixel100inFIG. 1is divided into two pixels300independent of each other. The reference character BAR1inFIG. 11denotes a first barrier formed, as a potential barrier, by ion implantation to prevent charge from being read from a first photodiode PD1to a second memory MEM2. The reference character BAR2denotes a second barrier formed, as another potential barrier, by ion implantation to prevent charge from being read from a second photodiode PD2to a first memory MEM1.

According to the configuration shown inFIG. 11, charge generated by photoelectric conversion in the first photodiode PD1can be read into only one of the first and second memories MEM1and MEM2, i.e., the first memory MEM1, and charge generated by photoelectric conversion in the second photodiode PD2can be read into only the other one of them, i.e., the second memory MEM2. Thus, the pixels300shown inFIG. 11operate as two independent pixels to obtain a normal image. In addition, a set of the pixels300shown inFIG. 11is identical to the pixel100shown inFIG. 1except the presence of the first and second barriers BAR1and BAR2. Thus, the set of the pixels300can be fabricated differently from the pixel100with ease.

FIG. 12is a plan view showing an exemplary imaging region including both the pixel100shown inFIG. 1and the set of the pixels300shown inFIG. 11. An imaging region20shown inFIG. 12includes a plurality of pixels which are two-dimensionally arranged in a matrix. Odd-numbered ones R1, R3, and R5of rows in the imaging region20each include such pixels300as shown inFIG. 11. These pixels are used to obtain a normal image, and are aligned with one another. On the other hand, even-numbered ones R2, R4, and R6of the rows each include such pixels100as shown inFIG. 1. These pixels are used for distance measurement, and are aligned with one another. That is to say, two types of pixels are both disposed on a single semiconductor substrate. Thus, the application area of the solid state imaging device is expanded.

How the pixels100shown inFIG. 1and the pixels300shown inFIG. 11are arranged should not be limited to the example shown inFIG. 12. For example, the number of the pixels100shown inFIG. 1or the pixels300shown inFIG. 11may be increased. The type of the pixels does not need to vary from row to row, and may vary from column to column. Alternatively, the pixels may also be arranged in a special regular pattern. Thus, the pixels may be freely arranged.

As can be seen from the foregoing description, a solid state imaging device according to the present disclosure can improve the speed at which charge is read from a photodiode, and is useful as a solid state imaging device that can be used for distance measurement.