DISPLAY PANEL HAVING LARGER DISPLAY AREA AND METHOD OF MANUFACTURING THE SAME

A display apparatus includes an array substrate that includes a display area including a pixel and a non-display area adjacent to the display area, an opposite substrate facing the array substrate, a liquid crystal layer disposed between the array substrate and the opposite substrate, and a signal input pad electrically connected to the pixel to apply an external input signal to the pixel. Each of the array substrate and the opposite substrate has an inner surface facing the liquid crystal layer and an outer surface opposite to the respective inner surface, and the signal input pad is disposed on the outer surface of either the array substrate or the opposite substrate.

DETAILED DESCRIPTION

FIG. 1is an exploded perspective view showing a display apparatus according to an exemplary embodiment of the present invention.

Referring toFIG. 1, a display apparatus includes a display panel100, a backlight unit200, an upper cover410, and a lower cover420.

The display panel100may be any type of display panel, such as a liquid crystal display panel, an electrophoretic display panel, an electrowetting display panel, etc. In the present exemplary embodiment, as a representative example, a liquid crystal display panel will be described as the display panel.

The display panel100has a rectangular shape with long sides and short sides, and includes a display area DA in which an image is displayed and a non-display area NDA disposed adjacent to, and surrounding, the display area DA. In addition, the display panel100includes an array substrate110, an opposite substrate120facing the array substrate110, and a liquid crystal layer (not shown) interposed between the array substrate110and the opposite substrate120. The display panel100further includes polarizing plates (not shown) respectively attached to its outer surfaces, i.e., an outer surface of the array substrate110and an outer surface of the opposite substrate120.

The array substrate110includes a plurality of pixels (not shown) arranged in the display area DA in a matrix arrangement. Each pixel includes a plurality of sub-pixels having different colors. For instance, each sub-pixel can have a red, green, or blue color. Thus, a light exiting from each sub-pixel takes on one of the red, green, or blue colors. In addition, each pixel includes a gate line (not shown), a data line (not shown) insulated from the gate line while crossing the gate line, and a pixel electrode (not shown). Further, each pixel includes a thin film transistor (not shown) electrically connected to the gate line, the data line, and the pixel electrode. The thin film transistor switches a driving signal applied to the pixel electrode.

A seal pattern (not shown) is disposed in the non-display area of the array substrate110to couple the array substrate110to the opposite substrate120.

The opposite substrate120includes color filters (not shown), each of which realizes a predetermined color using the light provided from the backlight unit200, and a common electrode (not shown) disposed on the color filters to face the pixel electrode. In this embodiment, each color filter has one of red, green, or blue colors, and is formed by a deposition or coating process. Meanwhile, in the present exemplary embodiment, the color filters are disposed on the opposite substrate120, but they should not be limited thereto or thereby. That is, the color filters may instead be disposed on the array substrate110.

The liquid crystal layer includes liquid crystal molecules arranged in a specific direction in response to an electric field generated by voltages respectively applied to the pixel electrode and the common electrode, and thus the liquid crystal layer controls a transmittance of the light passing through the liquid crystal molecules, thereby displaying desired images.

Meanwhile, in the non-display area NDA, a signal input pad (not shown) is disposed on an outer surface of the array substrate110or the opposite substrate120. The signal input pad is connected to a flexible printed circuit board140on which a driver IC141is mounted, and the flexible printed circuit board140is connected to an external circuit module (not shown). The driver IC141has applied thereto various control signals from the external circuit module, and applies a driving signal to the display panel100in response to the various control signals.

The backlight unit200is disposed behind the display panel100. The backlight unit200includes a light guide plate210, a light source unit220including a plurality of light sources, an optical member230, and a reflective sheet240.

The light guide plate210is disposed under the display panel100and guides the light emitted from the light source unit220to the display panel100. Particularly, the light guide plate210is overlapped with at least the display area DA of the display panel100. The light guide plate210includes an exit surface from which the light exits, a lower surface facing the exit surface, and side surfaces connecting the exit surface and the lower surface. At least one of the side surfaces faces the light source unit220to serve as a light incident surface onto which the light emitted from the light source unit220is incident, and a side surface facing the light incident surface serves as a light reflective surface to reflect the light.

The light source unit220includes a printed circuit board222and the light sources221, e.g., light emitting diodes, mounted on the printed circuit board222.

Here, the light sources221may emit light having the same color, e.g., a white light.

In addition, different light sources221may emit light having different colors. In detail, in one embodiment, a portion of the light sources221emits a red light, a portion of the light sources221emits a green light, and a remaining portion of the light sources221emits a blue light.

The light source unit220is disposed to emit light while facing at least one side surface of the light guide plate210, and provides the light to the display panel100through the light guide plate210.

The optical member230is disposed between the light guide plate210and the display panel100. The optical member230helps direct the light exiting through the light guide plate210from the light source unit220. In addition, the optical member230includes a diffusion sheet236, a prism sheet234, and a protective sheet232, which are sequentially stacked one on another.

The diffusion sheet236diffuses the light exiting from the light guide plate210. The prism sheet234condenses the light diffused by the diffusion sheet236to allow the light to travel in a direction substantially vertical to the display panel100. The light exiting from the prism sheet234is vertically incident onto the display panel100. The protective sheet232is disposed on the prism sheet234to protect the prism sheet234from external impact.

In the present exemplary embodiment, the optical member230includes one diffusion sheet236, one prism sheet234, and one protective sheet232, but it should not be limited thereto or thereby. That is, at least one of the diffusion sheet236, the prism sheet234, and the protective sheet232of the optical member230may be provided in plural number, or one of the diffusion sheet236, the prism sheet234, and the protective sheet232may be omitted from the optical member230.

The reflective sheet240is disposed under the light guide plate210and reflects the light that leaks from the light guide plate without being directed to the display panel100, to direct this leaked light up to the display panel100. The reflective sheet240includes a light reflective material to reflect the light. The reflective sheet240is disposed on the lower cover420and reflects the light emitted from the light source unit220. As a result, the reflective sheet240increases an amount of the light provided to the display panel100.

In the present exemplary embodiment, the light source unit220is disposed to provide light to the side surface of the light guide plate210, but it should not be limited thereto or thereby. That is, the light source unit220may be disposed to provide light to a lower surface of the light guide plate210. In addition, in a case that the light guide plate210is omitted from the backlight unit200, the light source unit220may be disposed under the display panel100, and thus the light emitted from the light source unit220may be directly provided to the display panel100.

The upper cover410is disposed on the display panel100. The upper cover410is provided with a display window411formed therethrough to expose the display area DA of the display panel100. The upper cover410is coupled with the lower cover420to support a front edge portion of the display panel100.

The lower cover420is disposed under the backlight unit200. The lower cover420provides a space to accommodate the display panel100and the backlight unit200therein. In addition, the lower cover420is coupled with the upper cover410to form a volume that accommodates the display panel100and the backlight unit200therein.

FIG. 2is a lower perspective view of the display panel shown inFIG. 1,FIG. 3is a partially enlarged view showing a portion A ofFIG. 2,FIG. 4is a plan view showing the display panel shown inFIG. 2,FIG. 5is a partially enlarged view showing a portion B ofFIG. 4,FIG. 6is a rear plan view showing the display panel shown inFIG. 2,FIG. 7is a partially enlarged view showing a portion C ofFIG. 6,FIG. 8is a lower perspective view showing a connection state between the display panel shown inFIG. 2and a flexible printed circuit board, andFIG. 9is a cross-sectional view showing a portion of the display panel shown inFIG. 8.

Referring toFIGS. 2 to 9, the display panel100includes the display area DA in which an image is displayed and the non-display area NDA disposed adjacent to the display area DA. The non-display area NDA surrounds the display area DA.

In addition, the display panel100includes the array substrate110, the opposite substrate120facing the array substrate110, the liquid crystal layer (not shown) interposed between the array substrate110and the opposite substrate120, and the signal input pad SIP disposed on the outer surface of the array substrate110or the opposite substrate120in the non-display area NDA. For instance, the signal input pat SIP is disposed on the outer surface of the array substrate110.

The array substrate110has a shape corresponding to that of the display panel100, and thus the array substrate110includes the display area DA and the non-display area NDA. The pixels are arranged in the display area DA of the array substrate110in a matrix form, and each pixel includes a thin film transistor TFT and pixel electrode115.

In detail, the array substrate110includes a first base substrate111, thin film transistor TFTs disposed on the first base substrate111in the display area DA, and pixel electrodes115connected to respective TFTs.

The first base substrate111corresponds to the display area DA and the non-display area NDA and has a rectangular plate shape with long sides and short sides. In addition, the first base substrate111includes an upper surface facing the opposite substrate120, a lower surface opposite to the upper surface, and a side surface connecting the upper surface and the lower surface.

The first base substrate111is formed of a transparent insulating material to transmit the light. In addition, the first base substrate111may be a rigid type substrate such as a glass substrate, a quartz substrate, a glass ceramic substrate, a crystalline glass substrate, etc., or a flexible type substrate such as a film substrate containing an organic polymer layer, a plastic substrate, etc. The materials used to form the first base substrate111have high heat-resistance when the first base substrate111is formed.

The thin film transistor TFT is disposed on the first base substrate111and includes a semiconductor layer SCL, a gate electrode GE, a source electrode SE, and a drain electrode DE. In detail, the thin film transistor TFT includes a gate electrode GE disposed on the first base substrate111, a gate insulating layer112covering the gate electrode GE, a semiconductor layer SCL disposed on the gate insulating layer112, and source and drain electrodes SE and DE connected to both ends of the semiconductor layer SCL. In the present exemplary embodiment, the semiconductor layer SCL includes a channel area overlapped with the gate electrode GE when viewed in a plan view, a source area making contact with the source electrode SE, and a drain area making contact with the drain electrode DE. The gate electrode GE of the thin film transistor TFT is connected to the gate line GL that transmits a scan signal or a gate signal to the thin film transistor TFT. The source electrode SE is connected to the data line DL that transmits the data voltage to the thin film transistor TFT.

As the above-mentioned thin film transistor, a bottom gate thin film transistor in which the gate electrode GE is disposed under the semiconductor layer SCL has been described, but the thin film transistor should not be limited to this configuration. That is, a top gate thin film transistor in which the gate electrode GE is disposed on the semiconductor layer SCL may be used as the above-mentioned thin film transistor TFT.

The thin film transistor TFT is electrically connected to the signal input pad SIP through a signal line SL. The signal line SL may be a gate line GL or a data line DL and may be extended into the non-display area NDA. When the signal input pad SIP is connected to a gate line GL, the signal input pad SIP may be a gate pad, and when the signal input pad SIP is connected to a data line DL, the signal input pad SIP may be a data pad.

The signal input pad SIP is disposed on the outer surface of the array substrate110or the opposite substrate120. For instance, the signal input pad SIP is disposed on the outer surface of the array substrate110, i.e., the lower surface of the first base substrate111. In addition, the signal input pad SIP makes contact with the flexible printed circuit board140on which the driver IC141is mounted. The driver IC141receives the various control signals from the external circuit module and applies the driving signal used to drive the display panel100to the thin film transistor TFT through the signal input pad SIP in response to the various control signals.

The signal input pad SIP is electrically connected to the signal line SL by a connection line CL formed along the side surface of the first base substrate111. In detail, the connection line CL includes a first portion CL1 disposed on the signal line SL, a second portion CL2 connected to the first portion CL1 and disposed on the side surface of the first base substrate111, and a third portion CL3 disposed on the lower surface of the first base substrate111to connect the second portion CL2 and the signal input pad SIP.

Meanwhile, a protective layer114is disposed on the thin film transistor TFT. The protective layer114is provided with a contact hole CH formed therethrough to expose a portion of the drain electrode DE. In addition, the protective layer114may have a multi-layer structure. For instance, the protective layer114may include an inorganic protective layer to cover the thin film transistor TFT and the gate insulating layer112and an organic protective layer disposed on the inorganic protective layer. The organic protective layer removes a step-difference occurring due to the thin film transistor TFT to planarize an upper surface thereof.

The pixel electrode115is disposed on the protective layer114and electrically connected to the drain electrode DE through the contact hole CH. The pixel electrode115can be any transparent conductor, and in particular can include a transparent conductive oxide, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

In the non-display area NDA, a common voltage pad117is disposed on the protective layer114. The common voltage pad117makes contact with the seal pattern SP, which has conductive properties to allow a common voltage to be applied to a common electrode125of the opposite substrate120. The common voltage pad117can be any transparent conductor, and in particular can include a transparent conductive oxide, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

The seal pattern SP surrounds the display area DA to couple the array substrate110to the opposite substrate120, and prevents liquid crystal molecules of the liquid crystal layer130from leaking.

The seal pattern SP may be, but is not limited to, an anisotropic conductive material having an insulating property in a first direction D1, e.g., a direction substantially parallel to the opposite substrate120, and a conductive property in a second direction D2 perpendicular to the first direction D1, i.e. vertical. Accordingly, the seal pattern SP applies the common voltage to the common electrode125through the common voltage pad117.

The opposite substrate120is disposed in the display area DA and the non-display area NDA and has an area equal to or greater than an area of the array substrate110. The area of the opposite substrate120is substantially the same as the array substrate110. Alternatively, in the case that the area of the opposite substrate120is greater than the area of the array substrate110, a non-overlap area NOA exists between the opposite substrate120and the array substrate110.

The opposite substrate120includes a second base substrate121and the common electrode125disposed on the second base substrate121. The second base substrate121has an area equal to or greater than the area of the first base substrate111. It is preferred that the area of the second base substrate121is substantially the same as the area of the first base substrate111. In addition, the second base substrate121may be a rigid type substrate or a flexible type substrate similar to the first base substrate111. The common electrode125can include a transparent conductive oxide as the pixel electrode115. Further, the common electrode125applies the common voltage provided through the seal pattern SP to each pixel.

The liquid crystal layer130includes liquid crystal molecules. The liquid crystal molecules are arranged in specific directions by the electric field generated between the pixel electrode115and the common electrode125, to control the transmittance of the light passing through the liquid crystal layer130. Accordingly, the liquid crystal layer130transmits the light provided from the backlight unit200in response to the electric field, and thus the display panel110displays images.

As described above, the signal input pad SIP is disposed on the outer surface of the array substrate110, i.e., the lower surface of the first base substrate111, and the signal input pad SIP is electrically connected to the signal line SL through the connection line CL formed along the side surface of the first base substrate111. Thus, the non-display area of the display panel100may be reduced. Since the non-display area NDA of the display panel100is reduced, a display apparatus employing the display panel100may reduce the space corresponding to the non-display area NDA in the upper and lower covers, which are prepared to accommodate the display panel100.

FIGS. 10 to 13are cross-sectional views explaining a method of manufacturing the display panel shown inFIGS. 8 and 9.

Referring toFIG. 10, the array substrate110is manufactured. The array substrate110includes display area DA and non-display area NDA adjacent to the display area DA.

In addition, the array substrate110includes the first base substrate111, the thin film transistor TFT disposed on the first base substrate111, the pixel electrode115connected to the thin film transistor TFT, the signal line SL connected to the thin film transistor TFT and extended into the non-display area NDA, and the common voltage pad117disposed in the non-display area NDA.

Hereinafter, a method of manufacturing the array substrate110will be described in detail.

The first base substrate111is prepared. The first base substrate111transmits light therethrough and has a rectangular plate shape with long sides and short sides. The first base substrate111includes an upper surface, a lower surface facing the upper surface, and side surfaces connecting the upper surface and the lower surface. In addition, the first base substrate111is disposed in the display area DA and the non-display area NDA.

When the first base substrate111is prepared, the thin film transistor TFT is formed on the first base substrate111. The thin film transistor TFT includes the gate electrode GE, the semiconductor layer SCL, the source electrode SE, and the drain electrode DE.

To form the thin film transistor TFT, the gate electrode GE is formed on the first base substrate111and the gate insulating layer112is formed on the first base substrate111to cover the gate electrode GE. Then, the semiconductor layer SCL is formed on the gate insulating layer112, and the source electrode SE and the drain electrode DE are formed on the semiconductor layer SCL to be respectively connected to the source area and the drain area of the semiconductor layer SCL. The area of the semiconductor layer SCL between the source area and the drain area serves as a channel area. In addition, the signal line SL is formed in the non-display area NDA together with the source and drain electrodes SE and DE. The signal line SL may be formed by extending the data line connected to the source electrode SE to the non-display area NDA.

After the thin film transistor TFT is formed, the protective layer114is formed to cover the thin film transistor TFT. The protective layer114includes the inorganic material, the organic material, or a compound of organic and inorganic materials.

Then, the protective layer114is patterned to remove a portion thereof, and thus the contact hole CH is formed to expose a portion of the drain electrode DE. A portion of the protective layer114in the non-display area NDA is also removed when the contact hole CH is formed, thereby exposing a portion of the signal line SL that is connected to the thin film transistor TFT.

When the portion of the drain electrode DE is exposed, the transparent conductive oxide is deposited and patterned. Due to the patterning process, the pixel electrode115is formed in the display area DA to be connected to the drain electrode DE of the thin film transistor TFT through the contact hole CH. In addition, the common voltage pad117is formed in the non-display area NDA by the patterning process.

Referring toFIG. 11, after the array substrate110is formed, the seal pattern SP is disposed in the non-display area NDA of the array substrate110. That is, the seal pattern SP surrounds the display area DA and is overlapped with the common voltage pad117.

The seal pattern SP may be, but is not limited to, an anisotropic conductive material having an insulating property in the first direction D1, e.g., the direction substantially parallel to the opposite substrate120, and a conductive property in the second direction D2 perpendicular to the first direction D1.

Then, the liquid crystal layer130including liquid crystal molecules is disposed in the display area DA.

Next, the opposite substrate120, that includes the second base substrate121and the common electrode125disposed on the second base substrate121, is prepared.

The opposite substrate120is disposed in the display area DA and the non-display area NDA, and has the area equal to or greater than the area of the array substrate110. The area of the opposite substrate120is substantially the same as the array substrate110. Alternatively, in the case that the area of the opposite substrate120is greater than the area of the array substrate110, the non-overlap area NOA exists between the opposite substrate120and the array substrate110.

The opposite substrate120includes the second base substrate121and the common electrode125disposed on the second base substrate121. The second base substrate121has an area equal to or greater than the area of the first base substrate111. It is preferred that the area of the second base substrate121is substantially the same as the area of the first base substrate111. In addition, the second base substrate121may be a rigid type substrate or a flexible type substrate similar to the first base substrate111. The common electrode125includes the same transparent conductive oxide as the pixel electrode115.

Then, the opposite substrate120is disposed such that the common electrode125faces the array substrate110. The array substrate110and the opposite substrate120are coupled to each other by the seal pattern SP. As described above, since the seal pattern SP is disposed to surround the display area DA and couples the array substrate110to the opposite substrate120, the liquid crystal molecules of the liquid crystal layer130may be prevented from leaking.

The seal pattern SP makes contact with the common electrode125of the opposite substrate120. Accordingly, the seal pattern SP is applied with the common voltage through the common voltage pad117to apply the common voltage to the common electrode125. The common electrode125applies the common voltage to each pixel.

In the present exemplary embodiment, the liquid crystal layer130is formed after the seal pattern SP is formed, and then the array substrate110is coupled to the opposite substrate120, but they should not be limited thereto or thereby. For instance, the liquid crystal layer130may be formed by forming the seal pattern SP, coupling the array substrate110to the opposite substrate120, and injecting the liquid crystal molecules between the array substrate110and the opposite substrate120.

Referring toFIG. 12, when the array substrate110is coupled to the opposite substrate120, the signal input pad SIP and the connection line CL are formed.

The signal input pad SIP is formed on the outer surface of the array substrate110, i.e., on the lower surface of the first base substrate111.

As described above, the connection line CL connects the signal line SL to the signal input pad SIP along the side surface of the first base substrate111. In detail, the connection line CL includes first portion CL1 disposed on the signal line SL, second portion CL2 connected to the first portion CL1 and disposed on the side surface of the first base substrate111, and third portion CL3 disposed on the lower surface of the first base substrate111to connect the second portion CL2 and the signal input pad SIP.

In the present exemplary embodiment, the signal input pad SIP and the connection line CL may be substantially and simultaneously formed by an aerosol jet printing method.

Different from a conventional inkjet printing method, the aerosol jet printing method is used to form electrical wirings having superior conductivity. To this end, the ink is atomized by using carrier gas sprayed at high speed, and the atomized ink is sprayed to a surface of the substrate to form a metal ink. Then, when the metal ink is sintered by a laser, electrical wirings having superior conductivity are formed. In addition, since the aerosol jet printing method is a non-contact pattern forming method, damage to the substrate is reduced when compared to the conventional inkjet printing method.

Referring toFIG. 13, after the connection line CL and the signal input pad SIP are formed, the flexible printed circuit board140(on which the driver IC141is mounted) is attached to the signal input pad SIP.

In the display panel manufactured by the above-mentioned processes, the signal input pad SIP is disposed on the outer surface of the array substrate110, i.e., on the lower surface of the first base substrate111and is electrically connected to the signal line SL through the connection line CL formed along the side surface of the first base substrate111. That is, the signal input pads SIP are located on the outer surface of substrate110rather than being located on the opposite surface, thus increasing the amount of components in the non-display area NDA of the opposite surface. Thus, the non-display area NDA of the display panel may be reduced. As described above, since the non-display area NDA of the display panel100is reduced, a display apparatus employing the display panel100may reduce the space corresponding to the non-display area NDA in the upper and lower covers.

Finally, the display panel is accommodated in the upper and lower covers together with the backlight unit, so that the display apparatus is manufactured.

Hereinafter, a display panel according to another exemplary embodiment will be described in detail with reference toFIGS. 14 to 22. InFIGS. 14 to 22, the same reference numerals denote the same elements inFIGS. 1 to 13, and thus detailed descriptions of the same elements will be omitted in order to avoid redundancy.

FIG. 14is a perspective view showing a display panel according to another exemplary embodiment of the present invention,FIG. 15is a partially enlarged view showing a portion D ofFIG. 14,FIG. 16is a plan view showing the display panel shown inFIG. 14,FIG. 17is a partially enlarged view showing a portion E ofFIG. 16,FIG. 18is a perspective view showing a connection state between the display panel shown inFIG. 14and a flexible printed circuit board, andFIG. 19is a cross-sectional view showing the display panel shown inFIG. 18.

Referring toFIGS. 14 to 19, a display panel100includes a display area DA and a non-display area NDA surrounding the display area DA.

The display panel100includes an array substrate110, an opposite substrate120facing the array substrate110, a liquid crystal layer130disposed between the array substrate110and the opposite substrate120, and a signal input pad SIP disposed on the outer surface of the array substrate110or the opposite substrate120to correspond to the non-display area NDA. For instance, the signal input pad SIP may be disposed on the outer surface of the opposite substrate120.

The array substrate110has a shape corresponding to that of the display panel100, and thus includes display area DA and non-display area NDA. In addition, the array substrate110includes a first base substrate111, a thin film transistor TFT disposed on the upper surface of the first base substrate111, and a pixel electrode115connected to the thin film transistor TFT.

The first base substrate111is disposed in the display area DA and the non-display area NDA and has a rectangular plate shape with long sides and short sides. In addition, the first base substrate111includes an upper surface facing the opposite substrate120, a lower surface opposite to the upper surface, and a side surface connecting the upper surface and the lower surface.

The thin film transistor TFT is disposed on the first base substrate111and includes a semiconductor layer SCL, a gate electrode GE, a source electrode SE, and a drain electrode DE. The source electrode SE is connected to the data line DL that applies the data voltage to the thin film transistor TFT.

The thin film transistor TFT is electrically connected to the signal input pad SIP through the signal line SL. The signal line SL may be the gate line GL or the data line DL. In the present exemplary embodiment, in the case that the signal input pad SIP is connected to the gate line GL, the signal input pad SIP may be the gate pad. In addition, in the case that the signal input pad SIP is connected to the data line DL, the signal input pad SIP may be the data pad.

A protective layer114is disposed on the thin film transistor TFT. The protective layer114is partially opened to form a contact hole CH through which a portion of the drain electrode DE is exposed.

The pixel electrode115is disposed on the protective layer114and is electrically connected to the drain electrode DE through the contact hole CH.

The opposite substrate120includes the display area DA and the non-display area NDA, and has an area equal to or smaller than an area of the array substrate110. The area of the opposite substrate120can be substantially the same as the array substrate110. Alternatively, in the case that the area of the opposite substrate120is smaller than the area of the array substrate110, a non-overlap area NOA exists between the opposite substrate120and the array substrate110.

The opposite substrate120includes a second base substrate121and the common electrode125disposed on the second base substrate121. The second base substrate121has an area equal to or smaller than the area of the first base substrate111. It is preferred that the area of the second base substrate121is substantially the same as the area of the first base substrate111. In addition, the second base substrate121includes a lower surface facing the array substrate110, an upper surface opposite to the lower surface, and a side surface connecting the lower surface and the upper surface.

A seal pattern SP is disposed between the array substrate110and the opposite substrate120to correspond to the non-display area NDA. The seal pattern SP is conductive, and makes contact with a common voltage pad117, so that a common voltage is applied to the common electrode125of the opposite substrate120through the seal pattern SP.

The signal input pad SIP is disposed on the outer surface of the opposite substrate120in the non-display area NDA, i.e., on the upper surface of the second base substrate121. In addition, the signal input pad SIP is connected to a flexible printed circuit board140on which a driver IC is mounted.

The signal input pad SIP is electrically connected to the signal line SL through a connection line CL formed along the side surface of the second base substrate121. In detail, the connection line CL includes a fourth portion CL4 disposed on the signal line SL, a fifth portion CL5 connected to the fourth portion CL4 and disposed on the outer surface of the seal pattern SP, a sixth portion CL6 connected to the fifth portion CL5 and disposed on the lower surface of the second base substrate121, a seventh portion CL7 connected to the sixth portion CL6 and disposed on the side surface of the second base substrate121, and an eighth portion CL8 disposed on the upper surface of the second base substrate121to connect the seventh portion CL7 and the signal input pad SIP.

As described above, the signal input pad SIP is disposed on the outer surface of the opposite substrate120, i.e., on the upper surface of the second base substrate121, and the signal input pad SIP is electrically connected to the signal line SL through the connection line CL formed along the side surface of the second base substrate121. Thus, the non-display area NDA of the display panel100may be reduced. Since the non-display area NDA of the display panel100is reduced, the display apparatus employing the display panel100may reduce the space corresponding to the non-display area NDA in the upper and lower covers, which are prepared to accommodate the display panel100.

FIGS. 20 to 22are cross-sectional views explaining a method of manufacturing the display panel shown inFIGS. 18 and 19.

Referring toFIG. 20, the array substrate110and the opposite substrate120are prepared and coupled to each other using the seal pattern SP.

The array substrate110includes first base substrate111, thin film transistor TFT disposed on the first base substrate111, pixel electrode115connected to the thin film transistor TFT, signal line SL connected to the thin film transistor TFT and extending into the non-display area NDA, and common voltage pad117disposed on the non-display area NDA.

The opposite substrate120includes display area DA and non-display area NDA, and has an area equal to or smaller than the area of the array substrate110. The area of the opposite substrate120is substantially the same as the array substrate110. Alternatively, in the case that the area of the opposite substrate120is smaller than the area of the array substrate110, non-overlap area NOA exists between the opposite substrate120and the array substrate110.

The opposite substrate120includes second base substrate121and common electrode125disposed on the second base substrate121. The second base substrate121has an area equal to or smaller than the area of the first base substrate111. It is preferred that the area of the second base substrate121is substantially the same as the area of the first base substrate111. In addition, the second base substrate121includes a lower surface facing the array substrate110, an upper surface opposite to the lower surface, and a side surface connecting the lower surface and the upper surface.

Referring toFIG. 21, after the array substrate110and the opposite substrate120are coupled to each other, the signal input pad SIP electrically connected to the signal line SL, and the connection line CL connecting the signal line to the signal input pad SIP, are formed.

The signal input pad SIP is formed on the outer surface of the opposite substrate120, i.e., on the upper surface of the second base substrate121. In addition, the connection line CL includes fourth portion CL4 disposed on the signal line SL, fifth portion CL5 connected to the fourth portion CL4 and disposed on the outer surface of the seal pattern SP, sixth portion CL6 connected to the fifth portion CL5 and disposed on the lower surface of the second base substrate121, seventh portion CL7 connected to the sixth portion CL6 and disposed on the side surface of the second base substrate121, and eighth portion CL8 disposed on the upper surface of the second base substrate121to connect the seventh portion CL7 and the signal input pad SIP.

In the present exemplary embodiment, the signal input pad SIP and the connection line CL may be substantially and simultaneously formed by an aerosol jet printing method.

Referring toFIG. 22, after the connection line CL and the signal input pad SIP are formed, the flexible printed circuit board140on which the driver IC141is mounted is attached to the signal input pad SIP.

Then, when the display panel100and the backlight unit are accommodated in the space between the upper cover and the lower cover, the display apparatus is manufactured.