Data slicer capable of calibrating current mismatch

A data slicer includes a comparator coupled with an input signal and a reference signal for generating a sliced signal, a waveform generator for generating a calibration signal, a pulse extension device coupled to the comparator and the waveform generator for modifying the duty cycle of the sliced signal or the calibration signal to output, a charge pump coupled between the pulse extension device and a first node for charging and discharging the first node according to the signal output from the pulse extension device, a determining circuit for adjusting the data slicer according to the level change at the first node, and a feedback device coupled between the first node and the comparator for generating the reference signal.

BACKGROUND OF INVENTION

1. Field of the Invention

The invention relates to a data slicer, and more particularly, to a data slicer capable of calibrating charge and discharge current mismatch.

2. Description of the Prior Art

Digital data slicers, which compare analog signals with a reference level signal to determine whether the binary value of the input signal is “0” or “1”, i.e. to convert analog input signals into digital output signals, are widely used in transmission systems.

Please refer toFIG. 1showing a block diagram of a conventional digital data slicer100. The data slicer100has a comparator110, an inverter115, a charge pump120, and a low pass filter130. The charge pump includes a current source121, a first switch122, a second switch123, and a current sink124. InFIG. 1, the first switch122or the second switch123is turned on when the signal input to its control end is at high level respectively. When a sliced signal Voutis at high level, the first switch122is turned on and the second switch123is turned off, and the voltage source121charges node A. When the sliced signal Voutis at low level, the first switch122is turned off and the second switch123is turned on, and the current sink124discharges node A.

After processing voltage signals at node A with the low pass filter130, a reference signal Vrefis generated, and the comparator110can generate the sliced signal Voutby comparing an input signal Vinwith the reference signal Vref. Theoretically, the current generated by the current source121or the current sink124must be the same in order to have a stable and accurate performance on data slicing.

However, it is very difficult to manufacture a current source121and a current sink124having the same charge or discharge current. Under the condition that there is a current mismatch between them, after a few periods, the error will be accumulated so that the whole system might become unstable and generate an erroneous sliced signal Vout. This is the main problem in the prior art.

SUMMARY OF INVENTION

It is therefore a primary objective of the claimed invention to provide a data slicer capable of calibrating current mismatch in order to solve the problem mentioned above.

Briefly, a data slicer includes a comparator coupled with an input signal and a reference signal for generating a sliced signal, a waveform generator for generating a calibration signal, a pulse extension device coupled to the comparator and the waveform generator for modifying the duty cycle of the sliced signal or the calibration signal to output, a charge pump coupled between the pulse extension device and a first node for charging and discharging the first node according to the signal output from the pulse extension device, a determining circuit for adjusting the data slicer according to the level change at the first node, and a feedback device coupled between the first node and the comparator for generating the reference signal.

DETAILED DESCRIPTION

Please refer toFIG. 2showing a block diagram of a digital data slicer200according to the first embodiment of the present invention. The data slicer200includes a comparator210for generating a sliced signal Voutaccording to an input signal Vinand a reference signal Vref, a waveform generator220for generating a calibration signal Videalin duty cycle of 50%, a multiplexer230coupled with the comparator210and the waveform generator220for selectively outputting the sliced signal Voutor the calibration signal Videalaccording to a selection signal SEL, a pulse extension device240coupled with the multiplexer230for modifying the duty cycle of the sliced signal Voutor the calibration signal Videal, a tunable charge pump250coupled between the pulse extension device240and a first node A for charging or discharging the first node A according to a first modifying signal V1and a second modifying signal V2, a feedback device (a low pass filter260in this embodiment) coupled between the first node A and the comparator210for generating the reference signal Vref, a determining circuit290for adjusting the data slicer200according to the level change at the first node A, an integrator270coupled with the first node A, and an analog-to-digital converter (ADC)280coupled between the integrator270and the determining circuit290.

Furthermore, in the present embodiment, the pulse extension device240includes a pulse extender241for modifying the duty cycle of the sliced signal Voutor the calibration signal Videalin order to generate the first modifying signal V1, and an inverter242coupled with the pulse extender241for generating the second modifying signal V2, inverse to the first modifying signal V1. The tunable charge pump250includes a tunable current source251, a first switch252, a second switch253(the first switch252and the second switch253will be turned on when their input signal is at high level), and a tunable current sink254. For example, when the first modifying signal V1is at high level and the second modifying signal V2is at low level, the first switch252is turned on and the second switch253is turned off. And when the first modifying signal V1is at low level and the second modifying signal V2is at high level, the first switch252is turned off and the second switch253is turned on.

When the data slicer200is in a calibration mode, the multiplexer230outputs the calibration signal Videalto the pulse extension device240according to the selection signal SEL. The calibration signal Videalis a periodic signal with period TCand duty cycle preset to 50%. And initially the output of the pulse extension device240equals to its input before the pulse extension device240being adjusted by the determining circuit290. Theoretically, if the tunable charge pump250is an ideal one, the level increase at node A due to the charging process should be exactly eliminated by the discharging process during each period TCof the calibration signal Videal. In result, the level at node A at each time instant N·TCshould remain the same value for any integer N. However, in practical, the tunable charge pump250would not be an ideal one so that the charging current always mismatches the discharging current, which in turn results in that the level at node A will change rather than stay at a constant value. To solve this problem, the level at node A is fed to the integrator270to get the accumulated level at the node A. The output of the integrator270is then fed to the ADC280to get a digital version of the accumulated level at the node A. Let U(N) denote the digital version of the accumulated level at the node A at time instant N·TC, where N is an integer. The determining circuit290is then employed to compare the values of U(N1) and U(N2) with N1<N2in order to determine how to adjust the data slicer200.

When the value of the output signal of the ADC280decreases, i.e. U(N1)>U(N2), based on the structure shown inFIG. 2, the determining circuit290can calibrate the mismatch in one of the following manners: adjusting the pulse extender241to enlarge the duty cycle of the first modifying signal V1, adjusting the tunable current source251to enlarge the charging current, or adjusting the tunable current sink254to lessen the discharging current (of course, more than one of these manners can be executed at the same time). On the other hand, when the value of the output signal of the ADC280increases, i.e. U(N1)<U(N2), the determining circuit290can calibrate the mismatch in the inverse of the above three manners.

In the structure shown inFIG. 2, the first modifying signal V1is inverse to the second modifying signal V2; the first switch252and the second switch253are turned on and off alternately. However, the first modifying signal V1does not necessarily have to be exactly inverse to the second modifying signal V2. The determining circuit290can adjust the duty cycle of the first modifying signal V1and the second modifying signal V2respectively in order to increase the resolution of the adjustment. Please refer toFIG. 3showing a block diagram of a digital data slicer300according to the second embodiment of the present invention. The difference between the data slicer300in the second embodiment and the data slicer200in the first embodiment is that a pulse extension device240in the second embodiment includes a first pulse extender341coupled with a multiplexer230for receiving a sliced signal Voutor a calibration signal Videalto modify their duty cycle in order to generate a first modifying signal V1, an inverter342coupled to the multiplexer230for receiving the sliced signal Voutor the calibration signal Videalto output them after inversion, and a second pulse extender343coupled to the inverter342for receiving an inverse version of the sliced signal Voutor the calibration signal Videalto modify their duty cycle in order to generate a second modifying signal V2. In this embodiment, a determining circuit290is capable of calibrating both the first pulse extender341and the second pulse extender343. Based on the structure shown inFIG. 3, when the value of an output signal of an ADC280decreases, i.e. U(N1)>U(N2), besides the three calibration methods mentioned above, a fourth manner to increase the adjustment resolution more is available by adjusting the second pulse extender343to shorten the duty cycle of the second modifying signal V2.

In the embodiments described above, the first switch252and the second switch253will be turned on when their signal input is at high level. However, it is also possible to have another design where one of the switches is to be turned on when its signal input is at high level, while the other switch turned on when its signal input is at low level. Please refer toFIG. 4showing a block diagram of a digital data slicer400according to the third embodiment of the present invention. The difference between the data slicer400in the third embodiment and the data slicer200in the first embodiment is that a pulse extension device240in the third embodiment does not include any inverter, and a first switch452of a tunable charge pump250is turned on when its signal input is at high level and a second switch453of a tunable charge pump250is turned on when its signal input is at low level. Except this difference, the operation in the third embodiment is the same as that in the first embodiment. However, the adjustment resolution in the third embodiment may not be as good as that in the second embodiment.

As an example, the person skilled in the art can simply combine a single OR gate (or AND gate) with a single buffer (for delaying signals) into a single pulse extension unit, and combine a plurality of pulse extension units with one or more multiplexers controlled by the determining circuit290into any of the pulse extender described above. Also, as an example, the person skilled in the art can simply compose the tunable current source (or the tunable current sink) by using a plurality of current sources (or current sinks) combined with different switches controlled by the determining circuit290.

In addition, an advantageous property of the present invention is described as below: The calibration strategy according to the present invention is flexible so that the present invention is feasible for a variety of operating frequencies. For instance, assume that in the three embodiments described above, the adjustment resolution, denoted by RT, of the pulse extension device240is T/100, and the adjustment resolution, denoted by RI, of the tunable charge pump250is I/100 (I and T are preset constants). For example, consider the data slicer is processing low frequency signals wherein the period of the data is T and the charging/discharging current of the tunable charge pump250is to be I/10. It can be seen that the ratio of T to RTis higher that that of I/10 to RI. Therefore if an error exists, the determining circuit290can coarsely tune the tunable charge pump250and finely tune the pulse extension device240. Another example, consider the data slicer is processing high frequency signals, wherein the period of the data is T/10 and the charging/discharging current of the tunable charge pump250is to be I (assuming that the current in high frequency operation of the tunable charge pump250is 10 times to that in low frequency operation). It can be seen that the ratio of T/10 to RTis lower that that of I to RI. Therefore if an error exists, the determining circuit290can finely tune the tunable charge pump250and coarsely tune the pulse extension device240. Accordingly, the system can operate under a high power or low power environment and is still capable of calibrating current mismatch.

Among the three embodiments described above, if the value of the output signal of the ADC280remains the same or are substantially the same, i.e. U(N1)≈U(N2), it would mean the determining circuit290has successfully calibrated the current mismatch. In this case the system can then end the calibration mode and enter into a signal slicing mode. The selection signal will switch the multiplexer230to output the sliced signal Voutto the pulse extension device240. And in the closed loop composed of the comparator210, the multiplexer230, the pulse extension device240, the tunable charge pump250, and the low pass filter260, the sliced signal Voutcan accurately represent the value of the input signal Vin.

In contrast to the prior art, the data slicer according to the present invention is capable of calibrating current mismatch so that an error may not be enlarged as in the prior art. Moreover, the system according to the present invention can apply different calibration methods according to different operating frequencies so that the processing range can be improved and the stability under different conditions can be improved.