Multi-supply dual port register file

A multi-supply dual port register file is disclosed. The register file may be used for transferring data between two power domains that operate on different voltages or frequencies. The register file comprises a memory cell that stores the data transferred between the domains. The memory cell may be independently supplied by a reference voltage independent of that of the memory periphery. A write power domain write data to the memory cell in accordance with its operating voltage and frequency and an independent read power domain may read data from the memory cell in accordance with its independent operating voltage and frequency. The register file facilitates efficient crossing between the read and write power domains.

BACKGROUND

1. Technical Field

The present disclosure is related to a multi-supply dual port register file and, in particular, a multi-supply dual port register file adapted for first input first output (FIFO) use between different power domains.

2. Description of the Related Art

FIG. 1shows a diagram of two domains10,12coupled via an interface14. Each domain10,12may comprise electronic circuitry, which may be analog or digital circuitry. For example, the first domain10may be a processor, whereas the second domain12may be a system-on-chip (SoC) that is built around the processor and designed to work with the processor. The two domains10,12may operate at different voltage levels. For example, the first domain may operate at a voltage level of 0.7 volts (V), whereas the second domain may operate at a voltage level of 0.8V. In addition, the two domains10,12may operate at different frequencies. For example, the first domain10as a processor domain may operate at a higher frequency of 1.5 gigahertz (GHz), whereas the second domain, which is the SoC may operate at a lower frequency of 500 megahertz (MHz). Furthermore, the first domain10and the second domain12may be in different power domains. The first and second domain10,12may be in different power domains if they can each be10,12selectively switched off or if the supply voltage of one domain10,12is not connected (or shorted) with the supply voltage of the other domain10,12. Accordingly, the two domains10,12may be supplied with the same voltage level but remain as two independent power domains.

As shown inFIG. 1, the domains10,12are each coupled to the interface14. The interface14, which is bidirectional comprises a first unidirectional interface14aand a second unidirectional interface14b. Although the bidirectional interface is shown inFIG. 1, any unidirectional interface14a,bmay alternatively be used. The interface14may be used for transferring data between the domains10,12. The bidirectional interface14or the unidirectional interfaces14a,bmay be a register file, such as a dual-port register file, a bridge or a first-in first-out (FIFO queue), among others. The first domain10may supply data to the first unidirectional interface14a(for example, by writing data to the interface14a) and the second domain12may read the data from the interface14a. The interface14amay enable voltage, clock or power domain crossing, whereby data of the first domain10, which operates at a different voltage or clock frequency than the second domain12or is in a different power domain than the second domain12, may be supplied to the second domain12and vice-versa. The interface14amay accordingly facilitate domain crossing between voltage, clock or power domains.

FIG. 2shows a diagram of the two domains10,12electrically coupled via an interface14a. The interface14acomprises a plurality of data elements16a-d(collectively referred to herein by the numeral alone), a multiplexer18, a voltage level shifting and power isolation unit20, write control logic22and read control logic23. Data of the first domain10is written using write control logic22to the interface14aand read by the second domain12from the interface14ausing read control logic24.

The first domain10outputs, to the write control logic22, data to be sent to the second domain12. The write control logic22provides the data to one or more of the plurality of data elements16. For example, each data element16may be a flip-flop and may receive one bit of data from the write control logic22and store the bit. Thereafter, the bits stored by the plurality of data elements16are outputted to the multiplexer. It is noted that although a plurality of data elements116are shown inFIG. 2, only one data element may be used. The write control logic22may also receive a read pointer signal26from the read control logic24and send a write pointer signal28to the read control logic24. The read pointer signal26and the write pointer signal28may be used to synchronize a timing of data reading and writing and/or to indicate placement of an ordering of the storage of the bits in one of the plurality data elements16.

The read control logic24outputs a selection signal30to the multiplexer18. Based on the selection signal30, the multiplexer18outputs a selected data bit from a data element16to the voltage level shifter and power isolation unit20. The voltage level shifter and power isolation unit20modifies the voltage level of the selected data bits to be compliant with that of the second domain12. For example, if the voltage level of the first domain is 0.7V whereas the voltage level of the second domain12is 0.8V, the voltage level shifter and power isolation unit20outputs a voltage level-modified data bit to the second domain12. Continuing with the example, the voltage level of the outputted data bit is 0.8V and in accordance with the second domain12. Level shifting slows the operation of the interface14and introduces delay in the data transfer between the two domains10,12.

It is noted that shifting the voltage level of the data from a voltage level of the first domain10to a voltage level of the second domain12increases the latency of the data transfer through the interface14a. In alternative implementations, the voltage level shifter and power isolation unit20may be in the data path between the plurality of data elements16and the multiplexer18. However, that results in increasing the size of the interface14acircuitry due to the fact that a plurality of data bits are each voltage level-shifted prior to being provided to the multiplexer18.

It is desirable to have an interface that provides efficient data transfer between isolated power domains, such as power domains that operate at different voltages or frequencies.

BRIEF SUMMARY

A dual port register file for transferring data between a first domain (a write domain) and a second domain (a read domain) is disclosed. The write domain may include electrical circuitry that operates at a specified voltage and frequency and may be electrically isolated from the read domain, which may operate at a different voltage and frequency. The dual port register file enables frequency and voltage cross-over, whereby data is trafficked over the dual port register file between the two domains operating at different frequencies and voltages/power domains. The dual port register file enables efficient transfer of data without a dedicated voltage level shifter, power isolation or frequency synchronization.

The dual register file includes a memory cell that is electrically coupled to the write domain and the read domain. The memory cell is used to store data trafficked between the two domains. The memory cell has a number of write domain electrical nodes. The write domain electrical nodes are electrically connected to the write domain. To write data to the memory cell, the write domain supplies voltages to the electrical nodes. The supplied voltages have levels that are in accordance with the operating voltage of the write domain. Similarly, the memory cell has a number of read domain electrical nodes that are electrically coupled to the read domain. To read data to the memory cell, the read domain supplies voltages to the electrical nodes, whereby the supplied voltages have levels in accordance with the operating voltage of the read domain.

DETAILED DESCRIPTION

FIG. 3shows a circuit schematic of a dual-port register file40. The dual-port register file40comprises an eight-transistor (8-T) bit cell42and a pre-charge transistor44that are electrically coupled. The 8-T bit cell42comprises a four-transistor (4-T) static memory cell46(hereinafter memory cell46), a first write access transistor48, a second write access transistor50and a read port52comprising a first read transistor54and a second read transistor56that are in stack.

The memory cell46comprises a first inverter58and a second inverter60that are cross-coupled.FIG. 3shows the configuration of the internal transistors of the cross-coupled inverters58,60. The first inverter58comprises a p-channel transistor66and an n-channel transistor68. The gates of the p-channel transistor66and the n-channel transistor68are electrically coupled to a second node64of the memory cell46. The drain of the n-channel transistor68and the drain of the p-channel transistor66are electrically coupled to a first node62of the memory cell46. The source of the p-channel transistor66is electrically coupled to a memory cell reference voltage node70and the source of the n-channel transistor68is electrically coupled to an array grounding node72.

The second inverter60also comprises a p-channel transistor74and an n-channel transistor76. The gates of the p-channel transistor74and the n-channel transistor76are both electrically coupled to the first node62of the memory cell46. The drain of the n-channel transistor76and the drain of the p-channel transistor74are electrically coupled to the second node64of the memory cell46. The source of the p-channel transistor74is electrically coupled to the memory cell reference voltage node70, whereas the source of the n-channel transistor76is electrically coupled to the array grounding node72.

The source terminal of the first write access transistor48is electrically coupled to a write bit line (WBL)78, and the drain terminal of the first write access transistor48is electrically coupled to the first node62of the static memory cell46. Furthermore, the source terminal of the second write access transistor50is electrically coupled to a complementary write bit line (WBLB)80, and the drain terminal of the second write access transistor50is electrically coupled to the second node64of the static memory cell46. The gate terminals of the write access transistors48,50are respectively electrically coupled to a write word line (WWL)82that enables writing data to the static memory cell46.

The drain of the first read transistor54is electrically coupled to a read bit line (RBL)84and the source of the first read transistor54is electrically coupled to the drain of the second read transistor56. The source of the second read transistor56, on the other hand, is connected to a read port ground terminal86. The gate of the first read transistor54is electrically coupled to a read word line (RWL)88and the gate of the second read transistor56is electrically coupled to the second node64of the memory cell46.

The pre-charge transistor44, which is a p-channel transistor, is electrically coupled, at its drain, to the RBL84. The source of the pre-charge transistor44is electrically coupled to a sensing node90used to sense the voltage of the RBL84. The gate of the pre-charge transistor44is electrically coupled to a gate drive node92.

The WBL78and the WBLB80are each electrically coupled to a first power supply node100and a second power supply node102of the first domain10, respectively. Furthermore, the RWL88and the RBL84are each electrically coupled to a first power supply node104and a second power supply node106of the second domain12, respectively. In addition, the gate drive node92and the sensing node90of the pre-charge transistor44are each electrically coupled to a third power supply node108and a fourth power supply node110of the second domain12, respectively.

The dual-port register file40ofFIG. 3is used to enable power domain crossing between the first domain10that writes data to the dual-port register file40and the second domain12that reads data from the dual-port register file40. The different power domains that write data to the dual-port register file40and read data from the dual-port register file40are isolated.

Furthermore, the memory cell46and the two write access transistors48,50is isolated in a power supply sense from the remainder of the memory periphery. A memory cell reference voltage (Vcell) provided at the memory cell reference voltage node70may be higher than the reference voltage of either the first domain10or the second domain12. That is because the memory cell46may require a minimum voltage to operate that is higher than that provided by the first domain10(the read domain) or the second domain12(the write domain). However, the Vcell may also be a third power supply node of the first domain10.

The WBL78and WBLB80are both driven by the first power supply node100and the second power supply node102, respectively, of the first domain10. The voltage level of the WBL78or the WBLB80whether they are asserted or de-asserted is dictated by the voltage level of the first domain10and is in accordance with the voltage level of the first domain10. In an alternate arrangement, WBL78and WBLB80can also be coupled with the Vcell supply voltage, while the rest of the memory periphery for write operations is coupled with the first power domain10.

To write data (i.e., a bit) to the static memory cell46, the WWL82is first asserted. As a result, the first and second write access transistors48,50are switched on thus connecting the first node62of the static memory cell46to the WBL78and connecting the second node64of the static memory cell46to the WBLB80. The WBL78carries the data that is sought to be written to the static memory cell46and is asserted when a logical one is sought to be written and is de-asserted when a logical zero is sought to be written. Conversely, the WBLB80is set to be a complement of the WBL78and is de-asserted when a logical one is sought to be written and asserted when a logical zero is sought to be written.

For example, if a logical one is to be written to the memory cell46and the voltage level of the first domain is 0.7V, the voltage level at the first power supply node100is set to 0.7V to assert the WBL78and the voltage level at the second power supply node102is set to 0V. Because the second node64of the memory cell46is electrically coupled to the WBLB80when the WWL82is asserted, the voltage level at the second node64will be 0V. Thus, the p-channel transistor66of the first inverter58is turned on and the voltage level at the first node62of the memory cell46takes on the Vcell voltage supplied at the memory cell reference voltage node70. Accordingly, the memory cell46will be in a different domain than the first domain10.

To read the bit stored in the memory cell46, the voltage level of the first power supply node104of the second domain12is set to the reference voltage of the second domain12thus turning on the first read transistor54of the read port52. Further, the voltage level of the second power supply node106is set to the reference voltage of the second domain12to pre-charge the RBL84.

If a logical one is stored in the memory cell46, the second node64of the memory cell46is grounded and, accordingly, the second read transistor56is switched off. While the second read transistor56is switched off, the RBL84remains pre-charged at the reference voltage of the second domain12. When the voltage level of the third power supply node108is set to reference voltage of the second domain12, the pre-charge transistor44is switched off and the reference voltage of the second domain12is sensed at the fourth power supply node110. Sensing the reference voltage at the fourth power supply node110indicates that a logical one is stored in the memory cell46.

Conversely, if a logical zero is stored in the memory cell46, the voltage level at the second node of the memory cell46will be the reference voltage (Vcell) of the memory cell46. Accordingly, the second read transistor56of the read port52will be switched on and the RBL84starts discharging, and will continue to discharges to ground under current scenario. Accordingly, when the voltage level of the third power supply node108is set to reference voltage of the second domain12, the pre-charge transistor44is switched off, and a lower voltage level at RBL84is sensed at the fourth power supply node110. Sensing the reduced (using conventional sense amplifier) or zero voltage (using a conventional inverter stage) at the fourth power supply node110indicates that a logical zero is stored in the memory cell46.

The power supply configuration ofFIG. 3, ensures that the first domain10(read domain) and the second domain12(write domain) are isolated and domain cross-over is prevented. The first domain10writes data to the memory cell46by driving the first power supply node100and the second power supply node102in accordance with the reference voltage of the first domain10and at the operational frequency of the first domain10. In addition, the second domain12reads data from the memory cell46by driving the first power supply node104, second power supply node106and third power supply node108of the second domain12in accordance with the reference voltage of the second domain12and at the operational frequency of the second domain12. Further, the memory cell46is in a power domain isolated from the first domain10and the second domain12.