Mixed-height high speed reduced area cell library

A mixed-height cell library for designing integrated circuits is provided. The mixed-height cell library includes a first plurality of cells having a first track height and a second plurality of cells having a second track height that are configured to be coupled to the first plurality of cells at respective power and ground rail lines. A method for mixed-height cell placement and optimization is also provided. The method comprises abutting cells of different track heights to form a plurality of rows of cells by coupling power and ground rails of the cells at a secondary layer that is different from a primary layer that is used to connect active material and determining whether re-ordering cells within rows allows for further compaction of adjacent rows. The method further comprises re-ordering cells within rows so to allow for further compaction of adjacent rows. The method also includes the steps of splitting rows vertically to minimize the distance between the split rows.

FIELD OF THE INVENTION

The present invention relates generally to integrated circuit design and specifically to a mixed-height cell libraries.

BACKGROUND OF THE INVENTION

The Integrated Circuit (IC) design process typically involves specifying the functionality of the chip in a standard hardware programming language such as verilog; synthesizing/mapping the circuit description into basic gates of a Standard Cell Library using Computer Aided Design (CAD) tools such as Synopsys' DesignCompiler; placing and routing the gate netlist using CAD tools, and finally verifying proper connectivity and functionality of the circuit.

While all of these steps are very important in determining the quality of the Integrated Circuit, for most of these steps, the achievable quality of implementation is design dependent. However, the Standard Cell Library can make all IC designs better, i.e., the quality of the Standard Cell Library influences all designs, and as such it has a far reaching influence on the quality of chips. The standard cell library provides the ingredients of a chip and thus limits the achievable quality of the final product.

Many library development efforts have focused on high speed designs. However, library improvement opportunities on the lower frequency end of the spectrum (e.g., Bluetooth or Gigabit PHY products) exist as well. In the past, technology scaling had provided the necessary speed increases. With the advent of technology scaling, higher and higher levels of integration became possible due to the shrinking device sizes. Technology scaling was providing not only an area scaling but also a delay scaling. According to Moore's “Law”, chips were doubling their speed every 18 months. While this “law” has been applicable for more than 20 years, a point has been reached where process scaling no longer delivers the expected speed increases. This is mainly due to the fact certain device parameters have reached atomic scales. One of the consequences of this speed saturation due to technology scaling is that designers must work harder at each stage of the design flow to achieve the last remaining circuit performance. Even small speed increases will come at significantly higher design efforts than in the past. Therefore having the best standard cell library is critical.

One technique being considered to achieve higher library speeds is the implementation of a 14-track standard cell library. This library has a cell height 40% larger than that of the base line standard cell library that is 10-tracks. The extra height allows for more active area (transistors) to be packed into cells and thus makes for more speed-efficient building blocks. However, the speed increase comes with a cost of added area and power which many portable applications are not able to tolerate. The added area increases fabrication costs, while the added power consumption (both dynamic and leakage power) reduces the battery life of products using the resulting chips.

What is therefore needed are design tools, such as enhanced Standard Cell Libraries, that can produce circuits having optimal speed and area.

What is further needed is an enhanced standard cell library that allows smooth intermixing of any track height cells and provides an effective way to combine the area/power efficiency of “short” cells with the speed advantage of “tall” cells.

The present invention will now be described with reference to the accompanying drawings. In the drawings, like reference numbers may indicate identical or functionally similar elements. Additionally, the left-most digit(s) of a reference number may identify the drawing in which the reference number first appears.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1Adepicts a high-level environment100used in the design of integrated circuits, according to embodiments of the present invention. Design environment100includes specification tools102, synthesis tools104, placement/routing tools106, verification tools108, and cell library110.

During the design process, the functionality of the chip is specified in a specification tool102using a standard hardware programming language such as verilog. The resulting circuit description is synthesized/mapped into the basic gates of cell library110, using one or more synthesis tools120such as Synopsys' DesignCompiler, produced by Synopsys, Inc. of Mountain View, Calif. The resulting gate netlist is then placed and routed using placement/routing tools106such as Magma's BlastFushion, produced by Magma, Inc. of San Jose, Calif. Finally, the connectivity and functionality of the integrated circuit are verified using a verification tool108.

While each of these components is important for the final quality of the resulting integrated circuit, the quality of implementation achievable by most of these components is design dependent. For example, a good verilog code specifying a circuit A, does not make an independent circuit B any better. However, an adequate cell library makes all designs better. The quality of the cell library influences all designs and as such has a far reaching influence on the quality of the resulting integrated circuit chip.

A standard cell library includes hundreds of cells that can be selectively combined to design a larger circuit. Each cell in the library is associated with a specific logic function. Each logic function may be implemented in one or more predefined cells. For example, a logic function may have multiple layouts, each having different characteristics.

A cell in a cell library is laid out relative to a grid defined by horizontal and vertical tracks. The number of horizontal tracks defines the height of the cell and the number of vertical tracks defines the width of the cell. The number of horizontal tracks determining the height of the cell are referred to interchangeably throughout as “height” or “track height.” “Layer” as referred to herein indicates one or more of the multiple layers of a die on which a chip is fabricated. Layers are typically represented in different colors by physical design tools such as Virtuoso by Cadence Design Systems, Inc. of San Jose, Calif.

Conventional standard cell libraries are comprised of cells having the same track height. However, mixed height cell libraries are also possible. A standard cell library is generally classified by its track height. For example, a 10-track library is composed of cells having heights of 10 tracks. The widths of cells in a library may vary. In conventional libraries, heights of cells are consistent to enable cells of the cell library to be readily combined to create larger circuits.

In embodiments presented herein, cell library110is modified to include mixed-height cells. The use of these mixed-height cells results in circuits having significant reduction in area with no associated loss of speed. Cell library110is composed of a base of cells from an existing X-Track Standard Cell Library and a set of cells having different heights are added to these baseline cells to generate a mixed-height cell library. The goal of a mixed-height cell library110is to provide an efficient library of cells that optimizes area, speed and power in integrated circuits synthesized using the mixed-height cell library.

The type and number of cells added to the existing X-Track cell library are dependent upon the efficiency required for the synthesis tool or application. Adding too many cells to a cell library may significantly reduce the efficiency of the synthesis tool and the quality of the resulting integrated circuit. This is because the synthesis tool may have difficulty handling a large number of choices for a specific logic function. Accordingly, mixed-height cells may only be provided for commonly used logic functions. Commonly used functions include, but are not limited to, AND gates, NAND gates, inverters, OR gates, NOR gates, and flip flops. As would be appreciated by persons of skill in the art, as design tools become more sophisticated, mixed-height cell library110can be further extended to include mixed-height cells for a majority or all supported logic functions.

Each cell in cell library110is associated with a set of data characterizing the cell. Example data includes the drive strength (speed) and leakage power characteristics associated with the cell. A synthesis tool uses the data or a subset of the data to determine which cell to select for the required logic function. For example, for tasks which have an extra timing margin but strict area constraints, the design tool may select a cell having less drive strength (slower speed) but smaller area. For tasks which have limited timing margin but flexible area constraints, the design tool may select a cell having greater drive strength (faster speed) and greater area.

FIG. 1Billustrates a stick-diagram layout of an exemplary cell112in cell library110. Cell112comprises power rail or VDD114, ground rail or VSS116, p-type diffusion material (p+)118, and n-type diffusion material (n−)120. Power rail114and p-type diffusion material118are embedded in n-well122. Polysilicon inputs124a-nintersect with p-type diffusion material118and n-type diffusion material120forming transistors. For example, where polysilicon input124intersects p-type diffusion material118, a p-type Metal Oxide Semiconductor (PMOS) transistor is formed, and where polysilicon input124intersects n-type diffusion material120, an n-type Metal Oxide Semiconductor (NMOS) transistor is formed. Connectors128a-bare used to connect power and ground connections to p-type diffusion material118or n-type diffusion material120. Output126outputs the result for cell112. The placement of polysilicon inputs124, connectors128and output126determines the type of logic function being implemented by cell112. For example, the logic function implemented by cell112is that of a NOT gate. It is to be appreciated by a person of skill in the art that the type of logic function implemented is arbitrary, design dependent and may vary. Cell library110typically comprises multiple cells implementing each common logic function that are used by designers and synthesis tools to create circuits.

FIG. 1Cillustrates an example physical design layout of a cell140created using a layout tools such as Virtuoso by Cadence Design Systems, Inc. of San Jose, Calif. Cell140includes VDD or power rail142, VSS or ground rail144, p-type diffusion material146, n-type diffusion material148, n-well150, polysilicon inputs151a-b, connectors154a-d, and output152. Position of inputs151a-b, connectors154a-d, and output152determine the logic function of cell140. Cell140implements a NAND gate logic function. Cell140has a track height of X (e.g. 10-track height) and is conventionally combined with other cells that have the same track height as described below.

FIG. 1Dillustrates a conventional physical design layout of a circuit using three cells. In a conventional same-height cell library, cell140can be coupled to other cells in the library by abutting the power and ground rails of cell140with corresponding power and ground rails of other cells in the library. For example, inFIG. 1D, cell150and cell160have the same track height as cell140. This allows cells140,150, and160to be connected by abutting their respective power and ground rails. However, speed, area, power and performance are limited by using cells that have the same cell height. Therefore, it is desirable to use cells having different heights for certain applications.FIGS. 2A-2Bdescribed below illustrate the problems encountered when coupling cells of different track heights.

2.0 High-Speed Reduced Area Cell Library

FIG. 2Aillustrates exemplary stick diagram of cell200and cell202that have different track heights. In the example inFIG. 2A, cell200has a track height X and cell202has a track height Y where X is greater than Y. Unlike the example shown inFIG. 1D, cell200and cell202have different track heights and cannot be combined at their respective power and ground rails because of this difference in track heights. In another example,FIG. 2Billustrates exemplary physical layout of cell204and206that have different track heights. In this example, cell204has a track height, of 10 and cell206has a track height of 8. Cells204and cell206cannot be combined by abutting their respective power and ground rails because of the difference in track heights. Embodiments presented herein overcome this limitation by providing mixed height cells that can be combined at respective power and ground layers.

FIG. 3Aillustrates an exemplary stick diagram layout of mixed-height cells that are integer multiples in track height, according to an embodiment of the invention. Cell300has a track height of X and cell302has a track height of 2X (a double height cell). Cell302is formed by extending p-type diffusion material304, n-well301and n-type diffusion material306to an area having a height that is twice the height of diffusion material of the corresponding cell300while keeping the distance between power and ground rail lines for cell302the same as the distance between power and rail lines for cell300. The same distance between power and ground rails for cell300and cell302allows them to be coupled at their respective power and ground rail lines.

FIG. 3Billustrates an exemplary physical design layout of mixed-height cells that are integer multiples in track height, according to an embodiment of the invention. In this example, cell310has a track height of 8 and cell312has a track height of 16 (double height cell). The n-well, p-type diffusion material and n-type diffusion material of cell312has been extended to form a 16-track cell312while maintaining the same distance between the power and ground rails in cell312as in cell310. The same distance between power and ground rails in cell310and cell312allows cell310and cell312to be abutted at their respective power and ground rails. This method provides substantially more active area per cell area and may be used as the preferred method of implementation for double height cells that are not flip-flops.

FIGS. 4A,4B depict an alternative technique for providing mixed-height cells.FIG. 4Aillustrates an exemplary stick diagram layout of mixed-height cells that are integer multiples in track height, according to an embodiment of the invention.FIG. 4Aillustrates the cell300(fromFIG. 3A) having a height track height X and a cell402having a track height of 2X. Cell300includes a single power rail310and a single ground rail312along with a single p-type diffusion material314and a single n-type diffusion material316. Cell402is a double height cell that includes ground rail410and ground rail412, n-type diffusion material414and n-type diffusion material416, p-type diffusion material418and p-type diffusion material420along with a single power rail408.

Cell402is created by forming a flipped mirror image of cell300over a horizontal axis passing through power rail310. As seen inFIG. 4A, even though cell402is twice the track height of cell300, the distance between power rail408and ground rail410of cell402and the distance between power rail310and ground rail312of cell300is the same allowing cell300and cell402to be abutted at power rail310and power rail408and at ground rail312and ground rail410respectively.

FIG. 4Billustrates an exemplary physical design layout of mixed-height cells that are integer multiples in track height according to an embodiment of the invention. Cell310(fromFIG. 3A) has a track height of 8 and cell460has a track height of 16. Cell460is twice the track height of cell310and is created by forming a mirror image of cell310over a horizontal axis that passes through its power rail line. Cell460includes a single power rail line, two ground rail lines, two n-type diffusion layers and two p-type diffusion layers. Cell310and cell460can be combined at their respective power and ground rail since the distance between the power line and a first ground line of cell460is the same as the distance between the power and ground rail lines of cell310. This method of creating double-height cells for a mixed height cell library is preferably applicable for creating flip-flops or other complex cells, where instead of laying down a master cell and a slave cell next to each other in a single height cell, the cells are arranged one on top of each other in a double height cell formation thereby roughly taking the same amount of area but allowing extra topological freedom for wiring. In the examples illustrated inFIGS. 3-4, the mixed height cells are double-height or twice the height of the single height cells. However, it is to be appreciated that the mixed height cells can be any integer multiple in height of the single track height cells.

FIG. 4Cdepicts a graph490comparing frequency vs. area for cells from a mixed track height cell library and cells from a standard single track cell library. Curve492depicts frequency vs. area for cells from a single track library (e.g. 10-track library). Curve494depicts frequency vs. area for a cell from a mixed height library (e.g. a 8/16 track library). As seen in graph490, once the frequency of a logic cell from either a standard library or a mixed height library drops under a certain frequency threshold (e.g. around 250 MHz inFIG. 4C), the area no longer decreases or decreases minimally. This is because all logic functions are implemented at or close to their minimal size. Typically, larger cells can operate at a higher frequency but take up significantly more area. As seen in graph492, frequency decreases sharply with area for a single 10-track library. A single 8-track library could reduce area by up to 20%. However, there are two issues since the 8-track library will have only a few horizontal tracks and very little active area. First, only a small number of logic functions could be implemented using the 8-track library thereby increasing the need for cells with greater drive strength to be used and thereby degrading the area savings of the 8-track library. Second, the frequency of a single track (e.g. 8-track) library decreases significantly with increase in area. In particular, the above mentioned single 8-track library slows down by about 30% with relatively proportionate increase in area. This again works against the potential area savings by increasing the need for cells with higher drive strength which inherently have a larger area. Also, the frequency slowdown limits the range of applications such a library could be used in.

Embodiments presented herein address these short comings by introducing a mixed height library comprising very low track height cells (for example 8-track cells) and corresponding high track double-height cells (for example 16-track cells). These double height cells provide a more efficient way to implement higher drive strength cells, as they are able to more efficiently fit active devices in available active area. At the same time, at low frequencies only very few of these double height cells are needed, so design area is not critically impacted. Furthermore, given the double height topology, these cells provide further routing resources in the most important lowest metal layer while concurrently reducing congestion for higher metal layers. These extra routing resources then make it possible to implement more complex functions, functions that were not feasible when using a single small track height library (e.g. an 8-track). As frequency increases, more double-height cells get utilized allowing speed-ups beyond that of a 10-track cell library. For example, graph494indicates the frequency vs. area enhancement from using a mixed height cell library (e.g. 8/16 mixed track height library). At around 100 MHz the area savings for the mixed height 8/16-track library in graph494are over 14% when compared to the single height 10-track library in graph492. As the frequency increases even to 400 MHz, the area savings in graph494are still over 10% when compared to graph492of the single track library. Furthermore, a drive strength of bigger cells in the mixed-height library is higher than a drive strength of smaller cells. The leakage power of the bigger cells in the mixed-height library is greater than a leakage power of smaller cells. For example, double height cells may have twice the drive strength and leakage power of the corresponding single height cells. Similarly, cells that are integer multiples in height of other cells may have integer multiple of drive strength and leakage power of the corresponding single height cells. In embodiments, mixed height cell libraries may be used only in critical paths to preserve area saving while maintaining desired frequency. Furthermore, combining a short track height cell with a double height cell reduces area, power and/or leakage power since the double height cell provides the increased drive strength (more power) while the smaller cell provides the area and leakage power savings.

FIG. 5Aillustrates an example stick diagram layout of cells in a mixed height library, according to an embodiment of the invention. In the example ofFIG. 5A, cell500has a track height of X and cell502has a track height of Y, where Y is greater than X.

The distance between power rail504and ground rail506of cell500is the same as the distance between power rail508and ground rail510of cell502. In conventional libraries that have cells of the same track height, power and ground rails are routed in the same layer that is used to connect the active areas that include p-type diffusion material and n-type diffusion material. The layer that is used to connect the active areas may be different from the layer that includes p-type diffusion material and n-type diffusion material. In conventional design methodology, the distance between power and ground rails cannot be the same for cells having different track heights since it leads to overlap of power rail and ground rails with wires that connect active areas such as p-type diffusion material and n-type diffusion materials. Therefore, conventional library designs are limited to single track height cells since cells of different track heights cannot be combined due to difference in distance between respective power and ground rails. In the embodiment presented inFIG. 5A, power rail508is at a different layer (e.g. metal2layer) of the chip than the wires that connect p-type diffusion material512and hence there is no contact between power rail508and wires that connect p-type diffusion material512. Similarly ground rail510is at a different layer of the chip as the wires that connect the n-type diffusion material516and hence there is no contact between ground rail510and the wires that connect n-type diffusion material516. Since there is no contact between power/ground rails and active areas, power rail508can overlap p-type diffusion material512and ground rail510can overlap n-type diffusion material516while not having actual physical contact between power/ground rails and active areas. Power rail504and ground rail506are also at the same layer of a chip (e.g. metal2layer) as power rail508and ground rail510. Since there is no restriction on where power rail508and ground rail510can be placed in relation to p-type diffusion material512and n-type diffusion material516, power rail508and ground rail510can be arranged so that the distance between them is the same as the distance X between power rail504and ground rail506of cell500. Since the distance between power rail504and ground rail506and power rail508and ground rail510is the same, cells500and cell502can be combined at their respective power and ground layers.

Similarly,FIG. 5Billustrates a physical design layout of cells of a mixed height library according to an embodiment of the invention. In this example, cell520and cell522have a different track height while having the same distance between power and ground rails. Power rail524and ground rail526of cell520and power rail528and ground rail530of cell522are at the same layer (e.g metal layer2) and this layer is different from the layer that connects active material for cell520and cell522. As a result cell520and cell522can be combined at their respective power and ground rails.

FIG. 5Cillustrates example optimization in a row of cells according to an embodiment of the invention. In the example inFIG. 5C, row550illustrates how conventionally formed cells of different track heights with different distances between power and ground rails cannot be combined in a single row. In row550, cell522aand cell554ahave a greater cell height than other cells in row550. As can be seen in row550, the power and ground rails do not abut. Since the distance between power and ground rails of cell552aand cell554ais greater than that of other cells in row550, cell552aand cell554acannot be placed in row550.

In contrast to row550, row560includes cells552band cell554bformed according to an embodiment of the invention as inFIG. 5C. In row560, cell552band554bhave a greater cell height than other cells in row560but, according to an embodiment of the invention, cell552band cell554broute their power rail and ground rail at the same distance and the same layer (e.g. metal layer2) as the other cells in row560. Hence, cells552band cell554bcan be combined with cells in row560by abutting respective power and ground rails.

3.0 Method for Creating and Using Mixed Height Cell Libraries

FIG. 8Ais an example flowchart800illustrating steps performed to create a mixed height cell library, according to an embodiment of the invention. Flowchart800will be described with continued reference to the example embodiments depicted inFIGS. 3-4. However, flowchart800is not limited to these embodiments. Note that some steps shown in flowchart800do not necessarily to have to occur in the order shown.

In step802, a minimum first track height is determined based on a desired amount of active area, clearance area, design rule check (DRC) constraints and performance requirements. For example, a minimum track height X as illustrated inFIGS. 3A and 4Ais determined based on a desired amount of active area, clearance area, design rule constraints and performance requirements.

In step804, a first plurality of cells of the first track height are created. For example, cell300of track height X is created.

In step806, a second plurality of cells of a second track height that is an integer multiple of the first track height are created while maintaining the same distance between power and ground rails as the first plurality of cells. For example, cell302and cell402may be created with a track height that is twice that of cell300. The distance between power and ground rail of cell302and cell402is the same as the distance between the power and ground rail of cell300enabling cell300, cell302and/or cell402to be coupled at respective power and ground rail lines. As described above, cell302is created by stretching the active areas i.e. p-type diffusion material304and n-type diffusion material306. Cell402is created by forming a mirror image of cell300along a horizontal axis that passes through its power rail line while maintaining the distance between power rail408and ground rail410to be the same as the distance between power rail310and ground rail312.

FIG. 8Billustrates an example flowchart840illustrating steps performed to use a mixed height cell library according to an embodiment of the invention. Flowchart840will be described with continued reference to the example embodiments depicted inFIG. 3-4. However, flowchart840is not limited to these embodiments. Note that the steps shown in flowchart840do not necessarily have to occur in the order shown.

In step842, a cell of a first track height is selected. For example, cell300of a track height X is selected.

In step844, a cell of a second track height is selected that is an integer multiple of the cell of the first track height from step842. For example, cell302of track height 2X is selected. In step846, the first cell is coupled with the second cell at the respective power and ground rail lines. For example, cell300is coupled to cell302at respective power and ground rail lines since the distance between power and ground rail lines for cell300and cell302in the mixed height library are the same. In another example, cell300is coupled to double track height cell402by coupling power rail310to power rail408and ground rail312to ground rail410.

FIG. 9Aillustrates an example flowchart900illustrating steps performed to create a mixed height cell library, according to an embodiment of the invention. In contrast to the example embodiment in flowchart800, the present embodiment in flowchart900does not require mixed-height cells to be integer multiples in height. Flowchart900will be described with continued reference to the example operating environment depicted inFIGS. 5A-C. However, flowchart900is not limited to these embodiments. Note that some steps shown in flowchart900do not necessarily have to occur in the order shown.

In step902, a minimum first track height is determined based on one or more of desired active area, clearance area, design rule check (DRC) constraints and performance requirements. For example, a minimum track height X as illustrated inFIG. 5Ais determined based on a desired amount of active area, clearance area, design rule constraints and performance requirements.

In step904, a first plurality of cells of a first track height as determined in step902are created with a first distance between power and ground rails. The distance between power and ground rails is determined based on desired clearance area and DRC constraints. The power and ground rails are created on a different layer than the one that is used to connect active materials (p-type diffusion material and n-type diffusion material). For example, cell500of track height X is created. Power rail504and ground rail506of cell500are on a layer (e.g. metal layer2) that is different from a layer (e.g. metal layer1) that is used to connect p-type diffusion material505and n-type diffusion material507.

In step906, a second plurality of cells of a track height Y that is greater than a track height X are created. The distance between power and ground rails for the second plurality of cells is the same as the distance between power and ground rails for the first plurality of cells from step904. For example, cell502of a track height Y that is greater than a track height X of cell500is created. Power rail508and ground rail510of cell502are on the same layer as power rail504and ground rail506of cell500. P-type diffusion material512and n-type diffusion material516are on the same layer as p-type diffusion material505and n-type diffusion material507. Power rail508and ground rail510of cell502can overlap p-type diffusion material512and n-type diffusion material since they are on a different layer than the one that is used to connect p-type diffusion material512and n-type diffusion material516.

FIG. 9Billustrates an example flowchart940illustrating steps performed to use cells from a mixed track library, according to an embodiment of the invention. Flowchart940will be described with continued reference to the example embodiment depicted inFIGS. 5A-C. However, flowchart940is not limited to these embodiments. Note that some steps shown in flowchart940do not necessarily have to occur in the order shown.

In step942, a cell of a first track height is selected. For example, cell500of a track height X is selected.

In step944, a cell of a second track height greater or lesser than the first track height is selected. For example, cell502of a track height Y that is greater than track height X of cell500is selected.

In step946, the first cell of the first track height is coupled to the second cell the second track height at respective power and ground rail lines. The power and ground rail lines of the respective cells are at a different layer than the one that is used to connect the respective active areas of the two cells. For example, power rail504is coupled to power rail508and ground rail506is coupled to ground rail510of cell502. In another example, as shown inFIG. 5C, cell552band cell554B are combined with cells of a lesser track height in row560since the power and ground rail lines of cell552B and cell554B are at the same distance as the power and rail lines of other cells in row560.

4.0 Method for Mixed-Height Cell Placement and Optimization

FIG. 10illustrates an example flowchart1000illustrating steps performed to optimize a floorplan according to an embodiment of the invention. Flowchart1000will be described with continued reference to the example in operating environment depicted inFIGS. 6A-D. However, flowchart1000is not limited to these embodiments. Note that some steps shown in flowchart1000do not necessarily have to occur in the order shown.

In step1002, cells of the same and/or different track height are abutted at respective power and ground rails to form multiple rows of cells. For example,FIG. 6Aillustrates an example initial placement of cells in this step. Floorplan600includes six rows of cells602-612. Row602, row604and row606have cells of the same track height. Rows608-612includes cells of mixed track heights that are combined together using the techniques described above. Row608, row610and row612have cells of different track heights coupled at respective power and ground rails that are at a different layer than the one that is used to connect active areas for the cells602-612.

During initial placement, floorplan600has the worst case row spacing for all rows. The worst case row spacing is determined by the height of the highest cells in adjacent rows that face each other. As seen inFIG. 6A, row608, row610and row612cannot be compacted together because of overlap in active areas of different sized cells.

In step1004, cells in rows having mixed-height cells are rearranged within their respective rows based so as to minimize the vertical distance between adjacent rows. In many cases, a lot of area can be recovered by local transformations of the placement. Step1004is optional.FIG. 6Billustrates an floorplan620which is a result of step1004. In floorplan620, row602, row604and row606are compacted to reduce the distance between them since the cells in row602, row604and row606have the same track height. In step1004, rows that do not have vertical space constraints may be compacted to reduce distance between them for initial floorplan optimization. In contrast, the cells in row608, row610and row612cannot be compacted because of potential overlap of active areas of cells having different track heights. However, according to an embodiment of the invention, cells in row608,610and612can be re-ordered within their respective rows to further allow compaction of row608, row610and row612. For example, cell614in row610and cell616in row612may be re-ordered in respective row610and row612to remove vertical row constraints which allow further compaction of row608, row610and row612.

In step1006, the rows with re-arranged cells are compacted to further reduce the distance between adjacent rows.FIG. 6Cillustrates a floorplan as a result of a second compaction step according to an embodiment of the invention. As seen inFIG. 6C, floorplan640illustrates further compaction of row608with row610and of row610with row612, due to re-ordering of cell614and cell616within respective rows. Rearranging cells within rows requires rerouting to compensate for the rearrangement. Routing adjustments are made to row610and row612to compensate for the re-ordering of cell614and cell616. The decision on which cells are to be re-ordered may also be based on critical path constraints and the extent of required rerouting. In an embodiment, only rows that are not part of a critical path are eligible for re-arrangement of cells.FIG. 6Dillustrates a side-by-side comparison of floorplan600and floorplan640. As seen inFIG. 6D, floorplan620provides a much more compact floorplan than floorplan600due to compaction of the top three rows602-606. Floorplan640provides further compaction in comparison to floorplan620due to rearrangement of cells616and614which allows for further compaction of the bottom three rows610-612.

FIG. 11illustrates an example flowchart1100illustrating steps performed to optimize placement of cells, according to an embodiment of the invention. For example, flowchart1100will be described with continued reference to the example embodiments depicted inFIGS. 7A-D. However, flowchart1100is not limited to these embodiments. Note that some steps shown in flowchart1100do not necessarily have to occur in the order shown.FIG. 7Aillustrates placement of mixed height cells in floorplan700prior to the optimization steps of flowchart1100. Floorplan700includes rows702-712. In this example, each of the rows702-712include at least one cell having a larger track height than other cells in the row. The minimum possible separation between rows702-712under design rules constraints is determined based on the highest cells that face each other in adjacent rows. For example, the vertical distance between adjacent rows determines the amount of compaction that is possible for each row.

In step1102, rows are split vertically into two or more portions based on distance between adjacent rows. For example, a first portion of adjacent rows may include cells such that opposing cells in adjacent rows are of the same height while a second portion of adjacent rows may includes cells of different track height are facing each other. If the rows are split into the first and second portions then the first portion of the adjacent row can be further compacted compared to the second portion.FIG. 7Billustrates a floorplan720derived from step1102. InFIG. 7Brows702-712from the floorplan700are vertically split to form rows702a-712aand rows702b-712b. Since each row in floor plan720has been divided into two distinct rows, each of the split rows can be optimized individually for compaction. Rows702a-cand rows708b-712bhave cells of the same track height and can be further compacted.

In step1104, cells may be re-ordered within the respective rows to further allow compaction between adjacent rows. For example, cells in rows708a-712amay be re-ordered within their respective rows so as to minimize the vertical distance between adjacent rows.

In step1106, rows are compacted to reduce vertical distance between adjacent rows.FIG. 7Cillustrates an example floor plan740derived from step1106. In the example inFIG. 7C, rows702a-706aand rows708b-712bfrom floorplan720have been compacted to generate area-efficient floorplan740. The compaction in floor plan740is possible because rows702-712were split into two slices thereby allowing slices to be compacted further. In an embodiment, cells within split rows702a-712aand702b-712bmay be re-ordered (as described inFIGS. 6A-D) to allow for further compaction between rows.FIG. 7Dillustrates a side-by-side comparison of floorplan700and floorplan740. As seen inFIG. 7D, significant savings in area are achieved by splitting and compacting rows in floorplan700to form floorplan740.

AlthoughFIGS. 7B-7Ddepict two slices, any number of slices can be used in the optimization. In this method, the area penalty introduced by two maximum height cells that share an x-span is reduced to a slice in which they reside and is not propagated to the entire row. This allows the compaction and optimizations described in flowchart1100to be performed on a slice by slice basis.

CONCLUSION