ARITHMETIC PROCESSING DEVICE AND METHOD FOR CONTROLLING THE SAME

An arithmetic processing device includes a cache memory, a first controller configured to control the cache memory and a second controller assigned a non-cache space to be accessed without use of the cache memory, wherein, when a condition, that out-of-order processing of a first and a second access requests for the non-cache space is possible and access targets of the first and second access requests are the same, is satisfied, the first controller issues the second access request to the second controller without waiting for a completion notification from the second controller with respect to the first access request previously issued to the second controller, and when the condition is not satisfied, the first controller issues the second access request to the second controller after waiting for a completion notification from the second controller with respect to first access request previously issued to the second controller.

DESCRIPTION OF EMBODIMENT

An embodiment of the present disclosure is described below in detail with reference to the accompanying drawings.

FIG. 1is a block diagram illustrating an example of the configuration of an arithmetic processing system including an arithmetic processing device, peripheral devices, and so on. The arithmetic processing system illustrated inFIG. 1includes a CPU10, a main memory11, an external device12, and another CPU13. The CPU10serves as an arithmetic processing device. The CPU10includes CPU cores21-1to21-n, a secondary cache controller22, a system controller23, and a secondary cache memory24. The CPU cores21-1to21-nhave substantially the same configuration. As represented by the CPU core21-1, each of the CPU cores21-1to21-nincludes an arithmetic unit30, an instruction controller31, a primary cache memory32, a primary cache controller33, and a TLB34. The secondary cache controller22includes address identifiers38-1to38-ncorresponding to the respective CPU cores21-1to21-n. The system controller23includes a memory controller35, a PCIe controller36, and a CPU interface controller37.

InFIG. 1, boundaries between the functional blocks and other functional blocks, which are represented by the boxes, basically indicate functional boundaries, and may or may not correspond to separation of physical positions, separation of electrical signals, control and logical separation, and so on. Each functional block may indicate a single hardware module physically separated from another functional block to some extent or may indicate one function of a hardware module into which the functional block and another functional block are physically integrated together.

The CPU cores21-1to21-nshare the secondary cache memory24and access the secondary cache memory24via the secondary cache controller22. The CPU cores21-1to21-nalso access the memory controller35, the PCIe controller36, and the CPU interface controller37, included in the system controller23, via the secondary cache controller22. The memory controller35controls the main memory11, which is an external memory. The PCIe controller36controls the external device12, such as a PCIe card. The CPU interface controller37controls exchange of information with the CPU13, which has a configuration and functions that are the same as or similar to those of the CPU10. The memory controller35, the PCIe controller36, and the CPU interface controller37, included in the system controller23, are allocated non-cache spaces accessed without use of the primary and secondary cache memories32and24.

The instruction controller31decodes an instruction fetched from the primary cache memory32. In accordance with a result of the decoding, the instruction controller31controls execution of an arithmetic instruction issued from the arithmetic unit30. The instruction controller31also issues an access request (an instruction unit request (IU-REQ)), such as a load instruction or a store instruction, to the primary cache controller33to execute processing, such as data loading or data storage, on the primary cache memory32.

Upon receiving the access request IU-REQ issued from the instruction controller31, the primary cache controller33refers to the TLB34to translate a virtual address in the access request into a physical address. As illustrated inFIG. 8, the TLB34contains translation table entries (TTEs), each having an E bit50(a field TTEe) indicating whether or not there is a side effect in a corresponding access space and a PA51indicating a physical page number. When an access-target address in the access request corresponds to a memory space in a device that performs in-order processing, TTEe=1 is obtained upon reference to the TLB34. When an access-target address in the access request corresponds to a memory space in a device that is capable of performing out-of-order processing of access requests, TTEe=0 is obtained upon reference to the TLB34.

A physical address obtained from the virtual address and the PA51by referring to the TLB34includes an NC bit indicating whether the physical address is a cacheable space or a non-cacheable space. When the NC bit indicates a non-cacheable space, the primary cache controller33issues a non-cache request NC-REQ to the secondary cache controller22. When the NC bit indicates a cacheable space, the primary cache controller33executes access to the primary cache memory32. The primary cache memory32and the secondary cache memory24have a hierarchical structure. Thus, when the access does not “hit” in the primary cache memory32, access to the secondary cache memory24is executed via the secondary cache controller22. The primary cache controller33and the secondary cache controller22control the cache memories (that is, the primary cache memory32and the secondary cache memory24).

FIG. 2illustrates an example of the format of the access request IU-REQ. As illustrated inFIG. 2, the access request IU-REQ, which is issued from the instruction controller31to the primary cache controller33, includes an instruction code (opcode)41and a virtual address42. The instruction code41indicates the type of a corresponding instruction. For example, the instruction code41indicates that a corresponding instruction is, for example, a store instruction (write instruction) or a load instruction (read instruction). The virtual address42indicates a target accessed by a store instruction, a load instruction, or the like.

FIG. 3illustrates an example of the format of the access request NC-REQ. As illustrated inFIG. 3, the access request NC-REQ, which is issued from the primary cache controller33to the secondary cache controller22, includes a non-cache instruction code (opcode)43and a physical address44, and a core-ID49. The non-cache instruction code43indicates the type of a corresponding instruction. For example, the non-cache instruction code43indicates that a corresponding instruction is, for example, a non-cache store instruction (write instruction) or a non-cache load instruction (read instruction). The physical address44includes an NC bit45, a CPU-ID46serving as a CPU identifier, a CTL-ID47serving as controller identifier, and an address48. The core-ID49indicates a CPU core identifier.

As described above, the NC bit45indicates whether an access-target address (that is, a target specified by the address48) is a cacheable space or a non-cacheable space. The CPU-ID46is an identifier for identifying the CPU10or13to be accessed by the access request NC-REQ. For example, when the access request NC-REQ accesses the PCIe controller36in the CPU10illustrated inFIG. 1, the CPU-ID46serves as an identifier for identifying the CPU10illustrated inFIG. 1. When the access request NC-REQ accesses a PCIe controller in the CPU13illustrated inFIG. 1, the CPU-ID46serves as an identifier for identifying the CPU13illustrated inFIG. 1. The CTL-ID47is an identifier for identifying the memory controller35, the PCIe controller36, or the CPU interface controller37to be accessed. For example, when the access request NC-REQ accesses the PCIe controller36in the CPU10illustrated inFIG. 1, the CTL-ID47serves as an identifier for identifying the PCIe controller36. The address48is an access-target physical address in the memory space. For example, when the access request NC-REQ accesses the PCIe controller36in the CPU10illustrated inFIG. 1, the address48indicates a specific address in the memory space allocated to the PCIe controller36. The core-ID49is created from an access request NC-REQ from the corresponding CPU core21-1, . . . , or21-nand serves as an identifier for identifying the CPU core21-1, . . . , or21-nthat is the request source of the access request NC-REQ.

FIGS. 4A and 4Bare flowcharts illustrating a flow of access-request issuance processing. Access-request issuance processing is described with reference toFIGS. 4A and 4B.

In operation S1inFIG. 4A, the instruction controller31issues an access request IU-REQ. In operation S2, the primary cache controller33first receives the access request IU-REQ. On the basis of the virtual address in the access request, the primary cache controller33refers to the TLB34to obtain a physical address corresponding to the virtual address. The primary cache controller33further checks the NC bit in the physical address to determine whether or not the access request is to access a non-cache space. When the access request is to access a cache space, general cache-access control is executed on the primary cache memory32and/or the secondary cache memory24. When the access request is to access a non-cache space, processing in operation S3and the subsequent operations is executed.

In operation S3, the primary cache controller33determines whether or not the value of the field TTEe obtained by referring to the TLB34is 0. When the field TTEe does not indicate 0 (that is, TTEe=1), this means that the access-target memory space is on a device that performs in-order processing. In this case, in operation S4, the primary cache controller33determines whether or not a completion notification (that is, a notification indicating that execution of requested processing is completed) with respect to a request immediately prior to that access request has already been received from the device to be accessed or the system controller23. When the completion notification has already been received, the primary cache controller33issues an access request NC-REQ to the secondary cache controller22(in operation S8). When the completion notification has not been received, the primary cache controller33waits in operation S5until the completion notification from the device to be accessed or the system controller23arrives. When the completion notification arrives, the primary cache controller33issues an access request NC-REQ to the secondary cache controller22(in operation S8).

Thus, upon determining that out-of-order processing of access requests for the non-cache space is not possible, the primary cache controller33waits for a completion notification with respect to an access request previously issued to the secondary cache controller22. The completion notification arrives via the system controller23from the device to be accessed or arrives from the system controller23. After waiting for the completion notification with respect to the previously issued access request (that is, when the completion notification arrives), the primary cache controller33issues the access request currently being processed to the secondary cache controller22.

When the result of the determination in operation S3indicates TTEe=0, this means that the access-target memory space corresponds to a device that is capable of performing out-of-order processing of access requests. In this case, in operation S6, the primary cache controller33checks whether or not a response NC-TKN from the secondary cache controller22with respect to an immediately prior request has been received. This response NC-TKN is a response that the secondary cache controller22, when an access request is issued to the system controller23, sends to the primary cache controller33without waiting for the above-described completion notification.

When the response NC-TKN has not been received (NO in operation S6), the process proceeds to operation S7in which the primary cache controller33waits until the response NC-TKN arrives. Upon receiving the response NC-TKN (YES in operation S6), the primary cache controller33issues an access request NC-REQ to the secondary cache controller22in operation S8.

Thus, upon determining that out-of-order processing of access requests for the non-cache space is possible, the primary cache controller33waits for a response to an access request previously issued to the secondary cache controller22. The response in this case is a response that the secondary cache controller22, when an access request is issued to the system controller23, sends to the primary cache controller33without waiting for a completion notification. After waiting for the response to the previously issued access request (that is, when the response arrives), the primary cache controller33issues the access request currently being processed to the secondary cache controller22.

In operation S9, the secondary cache controller22receives the access request from the primary cache controller33. In operation S10inFIG. 4B, the secondary cache controller22checks an issuance count of requests to the system controller23. In this case, the issuance count of requests is the number of, out of requests that have been issued from the secondary cache controller22to the system controller23, requests for which corresponding completion notifications have not arrived from the system controller23.

When the result of the determination in operation S10indicates that the issuance count is 0, the process proceeds to operation S11in which the secondary cache controller22issues an access request to the system controller23and also sends a response NC-TKN to the primary cache controller33. The secondary cache controller22further holds (stores) the address in the issued access request and increments the issuance count by 1.

When the result of the determination in operation S10indicates that the issuance count is larger than 0 and less than “full”, the process proceeds to operation S12in which the secondary cache controller22compares a stored address of the immediately prior access request with the address in the access request currently being processed. This comparison is performed in order to check an access target (“destination”).

When the condition that the access targets of two access requests (that is, the immediately preceding and current access requests) are the same is satisfied, (that is, “same destination” in operation S12), the process proceeds to operation S11in which the secondary cache controller22issues an access request to the system controller23. In this case, the secondary cache controller22issues the access request currently being processed to the system controller23, without waiting for the completion notification from the system controller23with respect to the access request previously issued to the system controller23. As described above, the system controller23includes multiple controllers (that is, the memory controller35, the PCIe controller36, and the CPU interface controller37). Thus, for issuing an access request to the system controller23, the secondary cache controller22issues the access request to, of the memory controller35, the PCIe controller36, and the CPU interface controller37, one controller indicated by the CTL-ID47in the physical address (seeFIG. 3) in the access request NC-REQ. When two access requests access the same one of the memory controller35, the PCIe controller36, and the CPU interface controller37, the secondary cache controller22determines that the access targets of the two access requests are the same. More specifically, when the NC bits45, the CPU-IDs46, and the CTL-IDs47located at the top-bit sides in the physical addresses44(illustrated inFIG. 3) in two access requests match each other, the secondary cache controller22determines that the access targets of the two access requests are the same. Even when the addresses48at the bottom-bit sides in two access requests are different from each other, the secondary cache controller22determines that the access targets of the two access requests are the same.

When the condition that the access targets of two (that is, immediately preceding and current) access requests are the same is not satisfied (that is, “different destinations” in operation S12), the process proceeds to operation S13in which the secondary cache controller22waits until the issuance count reaches 0. The issuance count is decremented by 1, each time a completion notification (that is, a completion notification NC-END indicating that execution of requested processing is completed) from the system controller23with respect to an access request already issued to the system controller23arrives. When the issuance count reaches 0, the secondary cache controller22issues the access request currently being processed to the system controller23(in operation S11). Thus, when the condition that the access targets are the same is not satisfied, the secondary cache controller22waits for a completion notification from the system controller23with respect to an access request previously issued to the system controller23. After waiting for the completion notification from the system controller23with respect to the previously issued access request, the secondary cache controller22issues the access request currently being processed to the system controller23. When the number of access requests previously issued to the system controller23is plural, the secondary cache controller22issues the access request currently being processed to the system controller23after waiting for completion notifications from the system controller23with respect to all of the access requests.

When the result of the determination in operation S10indicates that the issuance count is “full”, the process proceeds to operation S13in which the secondary cache controller22waits until the issuance count is less than “full”. In this case, the term “full” refers to the number of requests that the secondary cache controller22is able to receive, and depends on, for example, the capacity of a buffer built into the secondary cache controller22that holds received requests.

In operation S14, the system controller23(the memory controller35, the PCIe controller36, or the CPU interface controller37) receives the access request, and issues a request to the corresponding device, as appropriate. That is, the system controller23issues a request to the main memory11, the external device12, the CPU13, or the like. For example, when the PCIe controller36receives the request and the received request is to access the register in the PCIe controller36, the system controller23does not issue a request to the external device12. On the other hand, when the received request is to access the external device12, the PCIe controller36issues a request to the external device12.

When the device or the system controller23performs processing for the request and completes the processing in operation S15, the system controller23sends a completion notification NC-END indicating that the processing is completed to the secondary cache controller22. As described above, each time a completion notification NC-END arrives, the secondary cache controller22performs processing for decrementing the issuance count by 1.

FIG. 5illustrates an example of an operation of access-request issuance processing. First, the instruction controller31issues a request IU-REQ1 to the primary cache controller33. When the field TTEe corresponding to the request IU-REQ1 indicates 0, the primary cache controller33issues a non-cache request NC-REQ1 to the secondary cache controller22. In this case, when the instruction controller31issues next requests IU-REQ2 and IU-REQ3 and the corresponding fields TTEe indicate 0, corresponding non-cache requests NC-REQ2 and NC-REQ3 wait at the primary cache controller33.

Upon receiving the non-cache request NC-REQ1 from the primary cache controller33, the secondary cache controller22immediately issues the non-cache request NC-REQ1 to the system controller23, since the issuance count in the initial state is 0. In this case, the issuance count is incremented by 1 (in operation S51). Simultaneously with, in parallel with, immediately before, or immediately after the issuance of the non-cache request NC-REQ1, the secondary cache controller22issues a response NC-TKN1 to the primary cache controller33as a notification indicating the issuance of the non-cache request NC-REQ1. Upon receiving the response NC-TKN1, the primary cache controller33issues the next non-cache request NC-REQ2 to the secondary cache controller22.

Upon receiving the non-cache request NC-REQ2, the secondary cache controller22compares the access target of the non-cache request NC-REQ1 with the access target of the non-cache request NC-REQ2. When the access targets are the same, (that is, the same destination), the secondary cache controller22immediately issues the non-cache request NC-REQ2 to the system controller23. In this case, the issuance count is incremented by 1 (in operation S52). Simultaneously with, in parallel with, immediately before, or immediately after the issuance of the non-cache request NC-REQ2, the secondary cache controller22issues a response NC-TKN2 to the primary cache controller33as a notification indicating the issuance of the non-cache request NC-REQ2. Upon receiving the response NC-TKN2, the primary cache controller33issues the next non-cache request NC-REQ3 to the secondary cache controller22.

Upon receiving the non-cache request NC-REQ3, the secondary cache controller22compares the access target of the non-cache request NC-REQ2 with the access target of the non-cache request NC-REQ3. When the access targets are the same (that is, “same destination”), the secondary cache controller22immediately issues the non-cache request NC-REQ3 to the system controller23. In this case, the issuance count is incremented by 1 (in operation S53). Simultaneously with, in parallel with, immediately before, or immediately after the issuance of the non-cache request NC-REQ3, the secondary cache controller22issues a response NC-TKN3 to the primary cache controller33as a notification indicating the issuance of the non-cache request NC-REQ3.

When request completion notifications NC-END1 and NC-END2 are sent from the system controller23to the secondary cache controller22, the secondary cache controller22decrements the issuance counts by 1 for each of the completion notifications NC-END1 and NC-END2 (in operations S54and S55).

FIG. 6illustrates another example of the operation of the access-request issuance processing. First, the instruction controller31issues a request IU-REQ1 to the primary cache controller33. When the field TTEe corresponding to the request IU-REQ1 indicates 0, the primary cache controller33issues a non-cache request NC-REQ1 to the secondary cache controller22. In this case, when the instruction controller31issues next requests IU-REQ2 and IU-REQ3 and the corresponding fields TTEe indicate 0, corresponding non-cache request NC-REQ2 and NC-REQ3 wait at the primary cache controller33.

Upon receiving the non-cache request NC-REQ1 from the primary cache controller33, the secondary cache controller22immediately issues the non-cache request NC-REQ1 to the system controller23, since the issuance count in the initial state is 0. In this case, the issuance count is incremented by 1 (in operation S61). Simultaneously with, in parallel with, immediately before, or immediately after the issuance of the non-cache request NC-REQ1, the secondary cache controller22issues a response NC-TKN1 to the primary cache controller33as a notification indicating the issuance of the non-cache request NC-REQ1. Upon receiving the response NC-TKN1, the primary cache controller33issues the next non-cache request NC-REQ2 to the secondary cache controller22.

Upon receiving the non-cache request NC-REQ2, the secondary cache controller22compares the access target of the non-cache request NC-REQ1 with the access target of the non-cache request NC-REQ2. Since the access targets are different from each other (that is, “different destinations” in operation S62), the secondary cache controller22causes the non-cache request NC-REQ2 to wait until a completion notification NC-END1 with respect to the non-cache request NC-REQ1 previously issued to the system controller23arrives. When the completion notification NC-END1 with respect to the non-cache request NC-REQ1 arrives from the system controller23, the secondary cache controller22decrements the issuance count by 1 (in operation S63). As a result, since the issuance count reaches 0, the secondary cache controller22issues the non-cache request NC-REQ2 to the system controller23. In response to the issuance, the issuance count is incremented by 1 (in operation S63). Simultaneously with, in parallel with, immediately before, or immediately after the issuance of the non-cache request NC-REQ2, the secondary cache controller22issues a response NC-TKN2 to the primary cache controller33as a notification indicating the issuance of the non-cache request NC-REQ2. Upon receiving the response NC-TKN2, the primary cache controller33issues a next non-cache request NC-REQ3 to the secondary cache controller22.

Upon receiving the non-cache request NC-REQ3, the secondary cache controller22compares the access target of the non-cache request NC-REQ2 with the access target of the non-cache request NC-REQ3. Since the access targets are different from each other (that is, “different destinations” in operation S64), the secondary cache controller22causes the non-cache request NC-REQ3 to wait until a completion notification NC-END2 with respect to the non-cache request NC-REQ2 previously issued to the system controller23arrives.

When the request completion notification NC-END2 is sent from the system controller23to the secondary cache controller22, the secondary cache controller22decrements the issuance count by 1 (in operation S65).

FIG. 7illustrates yet another example of the operation of the access-request issuance processing. In the example illustrated inFIG. 7, operations of the instruction controller31, the primary cache controller33, and the secondary cache controller22are substantially the same as those illustrated inFIG. 5. In the example inFIG. 7, unlike the case inFIG. 5, the request processing performed by the system controller23or the device is completed on the non-cache request NC-REQ1 earlier than on the non-cache request NC-REQ2. As a result, the system controller23issues, to the secondary cache controller22, a completion notification NC-END2 with respect to the non-cache request NC-REQ2 earlier than a completion notification NC-END1 with respect to the non-cache request NC-REQ1. Since the fields TTEe corresponding to the non-cache requests NC-REQ1 and NC-REQ2 indicate 0, the access-target memory spaces correspond to a device that is capable of out-of-order processing of access requests. Thus, as in the case of the operation example illustrated inFIG. 7, the processing of the non-cache request NC-REQ2 issued later may be executed prior to the processing of the non-cache request NC-REQ1 issued earlier and the completion notification NC-END2 corresponding to the non-cache request NC-REQ2 may be issued earlier. Thus, when out-of-order processing of access requests is possible, the processing of a subsequently issued access request may be started earlier and completed earlier than the processing of a previously issued access request or may be started later and completed earlier than the processing of a previously issued access request. That is, when out-of-order processing of access requests is possible, the order of processing may be different from the order of issuances of the access requests. In addition, the different order of processing from the order of issuances of the access requests does not cause any inconvenience in the result of the processing.

FIG. 9is a diagram illustrating a circuit configuration for the access-request issuance processing. CPU cores21-1to21-nissue non-cache requests NC-REQ to a secondary cache controller22. The secondary cache controller22has address determiners38-1to38-ncorresponding to the respective CPU cores21-1to21-n. Each of the address determiners38-1to38-nconfirms the destination of the corresponding non-cache request NC-REQ. Upon receiving a non-cache request NC-REQ from any of the CPU cores21-1to21-n, the corresponding one of the address determiners38-1to38-nholds the address in the non-cache request NC-REQ. In the confirmation of the destination, the CPU-ID46and the CTL-ID47in the non-cache request NC-REQ currently being processed are compared with those in the immediately prior non-cache request NC-REQ to determine whether or not the destinations thereof are the same. After the non-cache request NC-REQ is issued to a system controller23, the address in the non-cache request NC-REQ is continuously held. A selector39arbitrarily selects an executable one of the non-cache requests NC-REQ received from the CPU cores21-1to21-nand issues the selected non-cache request NC-REQ to the system controller23. When the secondary cache controller22receives a request completion notification NC-END from the system controller23, a responder40in the secondary cache controller22checks a core-ID attached to the completion notification NC-END and sends the completion notification NC-END back to, of the CPU cores21-1to21-n, the CPU core that is the issuance source of the non-cache request NC-REQ.

While the present disclosure has been described above in conjunction with the embodiment, the present disclosure is not limited to the embodiment and various modifications and changes may be made thereto without departing from the scope of the appended claims.