Memory data access apparatus and method thereof

The present disclosure provides a memory data access apparatus and method thereof. The memory data access apparatus includes a cache memory and a processing unit. The processing unit is configured to: execute a memory read instruction, wherein the memory read instruction includes a memory address; determine that access of the memory address in the cache memory is missed; determine that the memory address is within a memory address range, wherein the memory address range corresponds to a data access amount; and read data blocks corresponding to the data access amount from the memory address of a memory.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority of Taiwan application No. 108144948 filed on Dec. 9, 2019, which is incorporated by reference in its entirety.

BACKGROUND

Field of the Invention

The present invention relates generally to a memory data access apparatus and method thereof, more particularly, to a memory data access apparatus and method thereof for cache memory.

Description of Related Art

In conventional computer architectures, a cache memory is primarily disposed between a processing unit and a general memory (e.g., a random-access memory). When the processing unit executes the memory read instruction, it may first search the cache memory that has a faster access speed to determine whether there is the corresponding data. If yes, the processing unit may read the desired data directly in the cache memory; in other words, the processing unit does not have to search for the desired data in the general memory that has a slower access speed, thereby saving the read time. If not, the processing unit has to resort to the general memory that has a slower access speed so as to read the desired data.

Nonetheless, since the cache memory has a higher cost and relatively limited storage space, the utilization of the cache memory and the contents stored therein shall be disposed properly, so as to increase the overall access efficiency.

BRIEF SUMMARY OF THE INVENTION

Some embodiments of the present invention provide a memory data access method, including: executing a memory read instruction, wherein, the memory read instruction includes a memory address; determining that access of the memory address in the cache memory is missed; determining that the memory address is within a memory address range, wherein, the memory address range corresponds to a data access amount; and reading data blocks corresponding to the data access amount from the memory address of a memory.

Some embodiments of the present invention provide a memory data access apparatus. The memory data access apparatus includes a cache memory and a processing unit. The processing unit is configured to: execute a memory read instruction, wherein the memory read instruction includes a memory address; determine that access of the memory address in the cache memory is missed; determine that the memory address is within a memory address range, wherein the memory address range corresponds to a data access amount; and read data blocks corresponding to the data access amount from the memory address of a memory.

DETAILED DESCRIPTION

Embodiments of the present invention are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of the disclosure.

Conventionally, when the cache memory read encounters the cache miss, it will read the data of a fixed size in the general memory; therefore, it is less flexible in terms of utilization. The present invention provides a memory data access apparatus and method, which may, depending on needs, dynamically adjust the size of the data that should be read in the general memory, so as to increase the utilization flexibility greatly.

Please refer toFIG.1A, which is a block diagram of a memory data access apparatus10according to some embodiments of the present invention. The memory data access apparatus10includes a processing unit101and a cache memory103. In some embodiments, the processing unit101is electrically coupled to the cache memory103for transmitting data and signals. In some embodiments, the memory data access apparatus10is electrically coupled to a memory90for transmitting data and signals. The relevant access operation of the memory data is discussed below in details.

Specifically, when the processing unit101needs to access data in the memory90, the processing unit101executes a memory read instruction100. In this case, the memory read instruction100includes a memory address ADDR. Then, before accessing the memory90, the processing unit101determines whether there is data corresponding to the memory address ADDR in the cache memory103with a faster access speed. If yes, the access of the cache memory103is a cache hit, and the processing unit101reads the data corresponding to the memory address ADDR directly in the cache memory103.

On the other hand, if the processing unit101determines that the cache memory103does not have data corresponding to the memory address ADDR; it means that the access of the cache memory103is a cache miss; in other words, the processing unit101determines that the memory address ADDR encounters the cache miss during the cache memory read, then the processing unit101needs to perform a read operation further to the memory90.

Specifically, the processing unit101determines whether the memory address ADDR is within a memory address range RAG. If not, the processing unit101reads a data block DB having the size of a single cache line at the memory address ADDR of the memory90, and writes it into the cache memory103, so that the processing unit101can access the data corresponding to the memory address ADDR in the cache memory103later.

On the other hand, the memory address range RAG corresponds to an data access amount AMT, and if the processing unit101determines that the memory address ADDR is within the memory address range, the processing unit101reads data block DB corresponding to the data access amount AMT at the memory address ADDR of the memory90, and writes the data block DB into the cache memory103. In some embodiments, the data access amount AMT is at least twice the size of the cache line.

In some embodiments, the memory address range RAG and its corresponding data access amount AMT are pre-determined and stored in at least one register. Please refer toFIG.1B; in some embodiments, the memory data access apparatus10further includes a register101aand a register101b, electrically coupled to the processing unit101. The register101ais configured to store the memory address range RAG, and the register101bis configured to store the data access amount AMT.

Please refer toFIG.1C, in some embodiments, the register101astores a plurality of memory address ranges RAG_1 to RAG_N, and the register101bstores a plurality of amounts of data access AMT_1 to AMT_N. In this case, the plurality of memory address ranges RAG_1 to RAG_N and the plurality of amounts of data access AMT_1 to AMT_N correspond to each other one-to-one. Accordingly, when the processing unit101determines that the memory address ADDR is within the memory range RAG_n, the processing unit101can read the data block DB corresponding to the data access amount AMT_n from the memory address ADDR of the memory90.

In some embodiments, the operation of writing the data block DB into the cache memory103may further include more detailed operations. Please refer toFIG.1D, which is a schematic diagram of the cache way of the cache memory103according to some embodiments of the present invention. In this case, the cache memory103includes a plurality of cache ways TAG_a to TAG_d. Each cache way has fields of 0 to 7.

When the processing unit101determines that the memory address ADDR is within the memory address range RAG, the processing unit101selects a cache way (e.g., the cache way TAG_b) from a plurality of cache ways TAG_a to TAG_d. In the meantime, the processing unit101divides the data block DB into a plurality of line data DB_1 to DB_3. In this case, the size of each line data is the same as the size of each cache line, and the line data DB_1 to DB_3 have the corresponding memory addresses ADDR_1 to ADDR_3.

Next, the processing unit101sequentially determines whether or not writing the line data DB_1 to DB_3 into the selected cache memory103. Specifically, for each line data, the processing unit101determines whether the corresponding memory address is stored in any cache way of the cache memory103. If not, the processing unit101writes the corresponding memory address into the selected cache way and writes this line data into the corresponding location of the cache memory103.

If the processing unit101determines that the corresponding memory address is stored in one cache way of the cache memory103, the processing unit101further determines whether the corresponding memory address is stored in the selected cache way. If yes, the processing unit101abandons this line data. If not, the processing unit101cleans the corresponding cache data in the cache memory103. Then, the processing unit101writes the corresponding memory address into the selected cache way, and writes this line data into a corresponding location of the cache memory103.

For example, please refer toFIG.1E; regarding the cache way line data DB_1, the processing unit101determines that the corresponding memory address ADDR_1 is not stored in the cache memory103. Therefore, the processing unit101writes the corresponding memory address ADDR_1 into the selected cache way, and writes the line data DB_1 into the corresponding location of the cache memory103.

For example, please refer toFIG.1F; regarding the line data DB_2, the processing unit101determines that the corresponding memory address ADDR_2 is stored in the cache way of the cache memory103. Therefore, the processing unit101further determines that the corresponding memory address ADDR_2 is stored in the selected cache way. Hence, the processing unit101abandons the line data DB_2.

For example, please refer toFIG.1G, regarding the line data DB_3, the processing unit101determines that corresponding memory address ADDR_3 is stored in the cache way of the cache memory103. Therefore, the processing unit101further determines that the corresponding memory address ADDR_3 is not stored in the selected cache way. Hence, the processing unit101cleans the corresponding cache line data in the cache memory103. Then, the processing unit101writes the corresponding memory ADDR_3 address into the selected cache way, and writes the line data DB_3 into the corresponding location of the cache memory103.

Other examples and figures are provided below to provide a more thorough description regarding the operation of writing the data block into the cache memory according to the present invention. Please refer toFIG.2A, which is a schematic diagram of the register and cache memory of the present invention. The register A stores memory address ranges: 0x2000 to 0x3ffff, and 0x5000 to 0x6ffff, and the register B stores data access amounts: two cache lines and three cache lines. In this case, the memory address range of 0x2000 to 0x3ffff correspond to the data access amount of two cache lines, and the memory address range of 0x5000 to x6ffff corresponds to the data access amount of three cache lines.

On the other hand, the cache memory C includes a plurality of cache ways Way-0 to Way-3, and each cache way has fields of 0 to 7. In this case, as shown in the figures, the cache ways Way-0 to Way-3 have had a plurality of memory addresses of 2000, 8060, A080, 51A0 and 20C0 stored therein. It should be noted that the memory addresses of the above-mentioned cache way have corresponding data in the other portion of the cache memory C, and to facilitate the understanding of the technology of the present invention, these data are not shown; however, persons having ordinary skill in the art would understand it readily.

Please refer toFIG.2B, in which the memory read instruction includes the memory address of 0x7040, and the processing unit determines that the memory address of 0x7040 is not within the memory address range of 0x2000 to x3ffff or 0x5000 to 0x6ffff. Hence, the processing unit reads the data block having the size of a single cache line at the memory address of 0x7040 of the memory. Then, the processing unit selects the Way-1, and writes the corresponding memory address of 0x7040 into the Way-1. In the meantime, the processing unit writes the data block corresponding to the memory address of 0x7040 into cache memory.

Please refer toFIG.2C, in which the memory read instruction includes the memory address of 0x2040, and the processing unit determines that the memory address of 0x2040 is within the memory address range of 0x2000 to x3ffff. Hence, the processing unit reads the data block having the data access amount of two cache lines at the memory address 0x2040 of the memory. This data block can be divided into a data having a start address of 0x2040 and a size of one cache line, and a data having a start address of 0x2060 and a size of one cache line.

Then, the processing unit selects the Way-0, and writes the corresponding memory address of 0x2040 into the Way-0. In the meantime, the processing unit writes the data block corresponding to the memory address of 0x2040 into the cache memory. Subsequently, the processing unit determines that the memory address of 0x2060 is not stored in any cache way of the cache memory, and hence, the processing unit writes the corresponding memory address of 0x2060 into the Way-0. In the meantime, the processing unit writes the data block corresponding to the memory address of 0x2060 into cache memory.

Please refer toFIG.2D, in which the memory read instruction includes the memory address of 0x5000, and the processing unit determines that the memory address of 0x5000 is within the memory address range of 0x5000 to 0x6ffff. Hence, the processing unit reads the data block having the data access amount of three cache lines at the memory address 0x5000 of the memory. This data block can be divided into a data having a start address of 0x5000 and the size of one cache line, a data having a start address of 0x5020 and the size of one cache line, and a data having a start address of 0x5040 and the size of one cache line.

Next, the processing unit selects the Way-2, and writes the corresponding memory address 0x5000 into the Way-2. In the meantime, the processing unit writes the data block corresponding to memory address 0x5000 into the cache memory. Subsequently, the processing unit determines that the memory address of 0x5020 does not exist in any cache way of the cache memory, and hence, the processing unit writes the corresponding memory address of 0x5020 into the Way-2. In the meantime, the processing unit writes the data block corresponding to the memory address of 0x5020 into the cache memory.

Then, the processing unit determines that the memory address of 0x5040 does not exist in any cache way of the cache memory, and hence, the processing unit writes the corresponding memory address of 0x5040 into the Way-2. In the meantime, the processing unit writes the data block corresponding to the memory address of 0x5040 into the cache memory.

Please refer toFIG.2E, in which the memory read instruction includes the memory address of 0x20A0, and the processing unit determines that the memory address 0x20A0 is within the memory address range of 0x2000 to x3ffff. Hence, the processing unit reads the data block having the data access amount of two cache lines at the memory address 0x20A of the memory. This data block can be divided into a data having a start address of 0x20A0 and the size of one cache line, and a data having a start address of 0x20C0 and the size of one cache line.

Next, the processing unit selects the Way-2, and writes the corresponding memory address of 0x20A0 into the Way-2. In the meantime, the processing unit writes the data block corresponding to the memory address of 0x20A0 into the cache memory. Subsequently, the processing unit determines that the memory address of 0x20C0 exists in the cache way Way-2 of the cache memory, and therefore, the processing unit would not write the memory address 0x20C0 into the Way-2 once again. In the meantime, the processing unit abandons the data block corresponding to the memory address of 0x20C0.

Please refer toFIG.2F, in which the memory read instruction includes the memory address of 0x5180, and the processing unit determines that the memory address 0x5180 is within the memory address range of 0x5000 to 0x6ffff. Hence, the processing unit reads the data block having the data access amount of three cache lines at the memory address 0x5180 of the memory. This data block can be divided into the data having a start address of 0x5180 and the size of one cache line, the data having a start address of 0x51A0 and the size of one cache line, and the data having a start address of 0x51C0 and the size of one cache line.

Then, the processing unit selects the cache way Way-3, and writes the corresponding memory address of 0x5180 into the Way-3. In the meantime, the processing unit writes the data block corresponding to the memory address of 0x5180 into the cache memory. Subsequently, the processing unit determines that the memory address of 0x51A0 exists in the cache way Way-0 of the cache memory; then, after the processing unit further determines that the selected cache way Way-3 is different from the memory address of 0x51A0 existing in the cache way Way-0 of the cache memory, the processing unit clear the memory address of 0x51A0 of the cache way Way-0, and clears the corresponding cache line data. Then, the processing unit writes the corresponding memory address of 0x51A0 into the Way-3. In the meantime, the processing unit writes the data block corresponding to the memory address of 0x51A0 into cache memory.

Subsequently, the processing unit determines that the memory address of 0x51C0 does not exist in any a cache way of the cache memory, and hence, the processing unit writes the corresponding memory address of 0x51C0 into the Way-2. In the meantime, the processing unit writes the data block corresponding to the memory address of 0x51C0 into the cache memory.

Some embodiments of the present invention include a memory data access method, and the process flow thereof is shown inFIG.3. The memory data access method of these embodiments is implemented by a memory data access apparatus (such as the memory data access apparatus10of the above-mentioned embodiments). Detailed operations of such methods are provided below.

First, step S301is executed to execute a memory read instruction. In this case, the memory read instruction includes a memory address. Then, step S302is executed to determine whether the memory address is a hit in a cache memory read. If yes, then step S303is executed to read the corresponding data in the cache memory. If it is a cache miss, then step S304is executed to determine whether the memory address is within a memory address range. In this case, the memory address range corresponds to a data access amount.

If the memory address is not within the memory address range, then step S305is executed to read the data block having the size of a single cache line at the memory address of a memory. If the memory address is within the memory address range, then step S306is executed to read the data block corresponding to the data access amount at the memory address of the memory.

Some embodiments of the present invention include a memory data access method, and the process flow thereof is shown inFIGS.4A and4B. The memory data access method of these embodiments is implemented by a memory data access apparatus (such as, memory data access apparatus10of the above-mentioned embodiments). Detailed operations of the method are provided below.

First, step S401is executed to execute a memory read instruction. In this case, the memory read instruction includes a memory address. Next, step S402is executed to determine whether the memory address is a hit in a cache memory read. If yes, step S403is executed to read the corresponding data in the cache memory. If it is a cache miss, step S404is executed to determine whether the memory address is within a memory address range. In this case, the memory address range corresponds to a data access amount.

If the memory address is not within the memory address range, step S405is executed to read a data block having the size of a single cache line at the memory address of a memory. Step S407is executed to write this data block into the cache memory. If the memory address is within the memory address range, then step S406is executed to read the data block corresponding to the data access amount from the memory address of the memory. Step S407is executed to write this data block into the cache memory.

In some embodiments, step S407can be further divided into the operations described inFIG.4B. Specifically, step S407ais executed to select a cache way from a plurality of cache ways of the cache memory for storing data. Step S407bis executed to divide the data block into a plurality of line data. In this case, the size of each line data is the same as the size of a cache line.

For each line data, step S407cis executed to determine whether this line data is stored in a cache memory; in other words, whether it matches one of the cache line data of the cache memory. If not, step S407dis executed to write this line data into the selected cache way of the cache memory, and step S407cis repeatedly executed for the next line data. If yes, step407eis executed to determine whether this line data is stored in the selected cache way of the cache memory.

If it is determined that this line data is stored in the selected cache way of the cache memory, then step S407fis executed to abandon the line data, and step S407cis repeatedly executed for the next line data. If it is determined that this line data is stored in another cache way of the cache memory, then step S407gis executed to clean the cache line data, in the cache memory, corresponding to this line data. Then, step S407dis executed to write this line data into the selected cache way of the cache memory, and step S407cis repeatedly executed for the next line data. Step S407cto step S407gare repeated until all the line data are processed.

It should be noted that in some embodiments, in the above mentioned memory data access apparatus, the processing unit includes logic circuit such as central processing units (CPUs) capable of carrying out computation and instructions, compared with the cache memory, a general memory includes the memory (Random Access Memory, RAM) having a slower access speed; however, this is not a limitation to the embodiments of the implementations of the hardware components of the present invention.

In some embodiments, the cache memory includes a Level 1 cache memory (L1 Cache memory). In some embodiments, the cache memory includes a Level 2 cache memory (L2 Cache memory). In some embodiments, the register may be a built-in register of the processing unit; however, this is not a limitation to the embodiments of the implementations of the hardware components of the present invention.