Analog-to-digital converter circuit and method of implementing an analog-to-digital converter circuit

An analog-to-digital converter circuit is described. The analog-to-digital converter circuit comprises an amplifier circuit configured to receive a differential analog input signal at a first amplifier input associated with a first amplifier current path and a second amplifier input associated with a second amplifier current path, and to generate an amplified differential analog input signal at a first amplifier output associated with the first amplifier current path and a second amplifier output associated with the second amplifier current path; a first capacitor coupled between the first amplifier input and the second amplifier output; a second capacitor coupled between the second amplifier input and the first amplifier output; and a latch circuit having a first latch input coupled to the first amplifier output and a second latch input coupled to the second amplifier output, wherein the latch circuit is configured to generate a differential digital output signal, based upon the amplified differential analog input signal, at a first latch output and a second latch output.

FIELD OF THE INVENTION

The present invention relates generally to integrated circuit devices, and in particular, to circuits for and methods of implementing an analog-to-digital converter circuit.

BACKGROUND OF THE INVENTION

Comparators are frequently used in analog-to-digital converters (ADCs) to make decisions on input signal voltage or current levels, where the decision is usually made with respect to a reference signal. On a circuit level, the comparator may be implemented using clocked latch circuitry. The clocked latch circuitry causes the output of the comparator to latch on high or low supply levels. When the input signal is very close to the predefined reference threshold, any noise or distortion in the signal path may lead to a wrong decision at the comparator output. Therefore, a pre-amplifier may be introduced before the clocked latch circuitry to amplify the signal to a desirable level.

Signal amplification enhances the overall conversion accuracy of the comparator having a pre-amplifier and a clocked latch. In a typical Successive Approximation Register (SAR) based ADC design, a capacitive digital-to-analog converter (CDAC) holds the input sampled signal at the comparator inputs. In high-speed ADCs, smaller capacitors values of the CDAC are essential to realize high conversion rates. However, a CDAC having smaller capacitors is more susceptible to picking up parasitic noise coupling, which makes kick-back noise an obstacle for ultra-high-speed ADCs. While the pre-amplifier serves as an isolating stage between the clocked latch and the capacitive DAC, it still contributes significant level of transient disturbance.

Therefore, a circuit for implementing an analog-to-digital converter that reduces the kick-back noise would be beneficial.

SUMMARY OF THE INVENTION

An analog-to-digital converter circuit is described. The analog-to-digital converter circuit comprises an amplifier circuit configured to receive a differential analog input signal at a first amplifier input associated with a first amplifier current path and a second amplifier input associated with a second amplifier current path, and to generate an amplified differential analog input signal at a first amplifier output associated with the first amplifier current path and a second amplifier output associated with the second amplifier current path; a first capacitor coupled between the first amplifier input and the second amplifier output; a second capacitor coupled between the second amplifier input and the first amplifier output; and a latch circuit having a first latch input coupled to the first amplifier output and a second latch input coupled to the second amplifier output, wherein the latch circuit is configured to generate a differential digital output signal, based upon the amplified differential analog input signal, at a first latch output and a second latch output.

A method of implementing an analog-to-digital converter circuit is also described. The method comprises receiving a differential analog input signal at a first amplifier input of a first amplifier path of an amplifier circuit and a second amplifier input of a second amplifier path of the amplifier circuit, reducing noise at the first amplifier input and the second amplifier input by coupling a first capacitor between the first amplifier input and a second amplifier output and coupling a second capacitor between the second amplifier input and a first amplifier output; generating an amplified differential analog input signal at the first amplifier output and the second amplifier output; latching data at a first latch input that is coupled to the first amplifier output and at a second latch input that is coupled to the second amplifier output; and generating a differential digital output signal, based upon the amplified differential analog input signal, at a first latch output and a second latch output.

Other features will be recognized from consideration of the Detailed Description and the Claims, which follow.

DETAILED DESCRIPTION

While the specification includes claims defining the features of one or more implementations of the invention that are regarded as novel, it is believed that the circuits and methods will be better understood from a consideration of the description in conjunction with the drawings. While various circuits and methods are disclosed, it is to be understood that the circuits and methods are merely exemplary of the inventive arrangements, which can be embodied in various forms. Therefore, specific structural and functional details disclosed within this specification are not to be interpreted as limiting, but merely as a basis for the claims and as a representative basis for teaching one skilled in the art to variously employ the inventive arrangements in virtually any appropriately detailed structure. Further, the terms and phrases used herein are not intended to be limiting, but rather to provide an understandable description of the circuits and methods.

The circuits and methods relate to Analog-to-Digital Converter (ADC) designs, and particularly Successive Approximation Register (SAR) based ADCs that are capable of receiving high-speed data. The circuits and methods enhance the conversion accuracy of a comparator of the ADC by reducing the kick-back noise from the comparator. A neutralization technique for pre-amplifier circuitry effectively reduces the kick back noise, enabling the use of a smaller net capacitance in a CDAC. The smaller net capacitance enables a higher signaling bandwidth that is essential in utilizing the ADCs for high-speed wireline and wireless applications.

According to one implementation, an analog-to-digital converter circuit comprises a first capacitor coupled between a first amplifier input and a second amplifier output of an amplifier circuit, and a second capacitor coupled between a second amplifier input and a first amplifier output the amplifier circuit. The first and second capacitors reduce the kickback noise, and make it possible to use smaller capacitors in the CDAC circuit.

Turning first toFIG. 1, a block diagram of an integrated circuit including a receiver having an analog-to-digital converter circuit is shown. In particular, an input/output port102is coupled to a control circuit104that controls programmable resources106having configuration memory108. Configuration data may be provided to the configuration memory108by a configuration controller110. The configuration data enables the operation of configurable logic elements109. While CLEs are shown by way of example as one type of programmable resource, it should be understood that other programmable resources could be implemented. A memory112may be coupled to the control circuit104and the programmable resources106. A receiver circuit114may be coupled to the control circuit104, programmable resources106and the memory112, and may receive signals external to the integrated circuit device by way of I/O port116. Other I/O ports may be coupled to circuits of the integrated circuit device, such as I/O port118that is coupled to the control circuit104as shown. A clocking network120is coupled to various elements of the circuit ofFIG. 1. The circuits and methods of receiving data described in more detail below may be implemented by various elements of the circuit ofFIG. 1, and particularly the receiver circuit114to receive a differential analog input signal as described below.

Turning now toFIG. 2, a block diagram of an SAR-based analog-to-digital converter circuit200that may be implemented in the receiver ofFIG. 1is shown. The SAR-based analog-to-digital converter circuit200comprises a comparator circuit202, operating as an analog-to-digital converter, coupled to a first capacitive network204and a second capacitive network206that forms a CDAC circuit207. A Successive Approximation Register (SAR) circuit208is coupled to an output of the comparator circuit202, and controls the operation of the first capacitive network204and the second capacitive network206to determine a value of an input signal. More particularly, first control lines210comprises a plurality of control lines having a control line for each of a plurality of switches212controlling a corresponding capacitor. The switch212comprises a first terminal214coupled to a reference voltage (vref) at a reference voltage node213and a second terminal216coupled to a ground voltage (GND). The switch212enables the routing of either the reference voltage or the ground voltage to a node218of the switch that is coupled to a first terminal of a corresponding capacitor. Six capacitors220-230are shown, where a corresponding switch212controls the application of either the reference voltage or ground voltage to the first terminal of the capacitor. A second terminal of the each of the capacitors220-230is coupled to a first input232of the comparator circuit202. A first input voltage (yin) of a differential pair of analog input voltages is also coupled to the input232by way of a switch234.

Second control lines240comprises a plurality of control lines having a control line for each of a plurality of switches242controlling a corresponding capacitor. Each switch242comprises a first terminal244coupled to the reference voltage and a second terminal246coupled to the ground voltage. The switch242enables the routing of either the reference voltage or the ground voltage to a node248of the switch that is coupled to a first terminal of a corresponding capacitor. Six capacitors250-260are shown, where a corresponding switch242controls the application of either the reference voltage (at the reference voltage node243) or ground voltage to the first terminal of the capacitor. A second terminal of the each of the capacitors250-260is coupled to a second terminal262of the comparator circuit202. A second input voltage (vip) of a differential pair of analog input voltages is also coupled to the input terminal262by way of a switch264. Differential digital outputs von and vop are coupled to corresponding inputs of the SAR circuit208. In particular, an output266of the comparator circuit202is coupled to a corresponding input267of the SAR circuit208, and an output268is coupled to a corresponding input269of the SAR circuit208. A determination of the input voltages yin and vip are generated at an output270of the SAR circuit. It should be noted that while the pre-amplifier is shown implemented with NMOS transistors, the transistors ofFIG. 3could be implemented as PMOS transistors, depending upon the voltage level at the input of the pre-amplifier.

In operation, the switches234and264are closed, allowing the yin signal to charge the capacitors220-230and the vip signal to charge to capacitors250-260in a first stage, where the switches212are set so that the node218is coupled to the second reference terminal216and the switches242are set so that the nodes248are coupled to the second terminal246to enable the capacitors to charge. The values at the inputs232and262represent captured differential analog input signals associated with the differential analog input signals yin and vip. The switches212and242are then sequentially decoupled, where a comparison is made to determine the value of the input signal.

In order to meet the bandwidth requirement, a front-end switch and buffer cannot drive a large CDAC, and the size of capacitors of the CDAC array have to be minimized for speed. As will be described in more detail in reference toFIG. 5, the capacitators, which extend from a large capacitance value of capacitators220and250to smaller capacitance values230and260, respectively, are sequentially enabled or disabled until there is no difference between the inputs of the comparators. During a discharge mode, the switches234and264are opened, and the switches212and242are set to enable discharging of the capacitor.

Turning now toFIG. 3, a block diagram of an amplifier circuit and a latch circuit of the comparator circuit202ofFIG. 2is shown. The comparator circuit202comprises a pre-amplifier302coupled to a latch circuit304. The pre-amplifier is made of a NMOS differential pair with resistor load, and comprises a PMOS reset switch to reset the preamp output for overdrive recovery. More particularly, the pre-amplifier302comprises a first transistor306associated with a first amplifier current path307and a second transistor308associated with a second amplifier current path309coupled in parallel between a high power reference voltage (avcc_h) and a node310coupled to the ground voltage (GND) by way of a current source312. Each of the transistors306and308comprises a source coupled to the node310, and a drain coupled to a corresponding resistor314and316. That is, a drain of the transistor306is coupled to a first terminal of the resistor314, which has a second terminal coupled to a node318receiving the high power reference voltage. A drain of the transistor308is coupled to a first terminal of the resistor316, which has a second terminal coupled to the node318.

Kickback noise is a result of finite isolation between input and output of an analog-to-digital converter, especially for the comparator202because input can be much smaller (e.g. in the millivolt (mV) range) than the output, which can be as high as the reference voltage avcc_I (i.e. approximately 0.9V). Since the comparator is running sequentially in the SAR ADC, any disturbance on the comparator input will slow down ADC conversion speed, as the comparator has to wait for the input to be stable before making a correct decision in next cycle. For example, if the output is 900 mV and kick back noise of 1 mV requires isolation of approximately 60 dB, an input to the comparator of less than 1 mV will become negative voltage if noise at the inputs of the comparator is out of phase with input signal. Therefore, an output of the comparator that should be positive would be mistakenly determined to be negative due to kickback noise. In addition, the kickback noise is even worse if input impedance is high, as the noise coupled to input of the comparator is proportional to source impedance. Because the input impedance is chosen to be high to achieve a high speed in an SAR DAC, the implementation of the capacitors320and322in the comparator202provides a significant benefit in an SAR DAC.

In order to account for kickback noise produced by the pre-amplifier, a capacitor, for each of the input terminals of the pre-amplifier302, is coupled between an input terminal associated with one amplifier current path and the output terminal associated with the other amplifier current path. More particularly, a first capacitor320is coupled between a first input terminal321(coupled to receive the vip input signal), such as at the gate of the transistor306, and a second output terminal326. A second capacitor322is coupled between a second input terminal323(coupled to receive the yin input signal), such as at the gate of the transistor308, and a first output terminal324. That is, the source and drains of each of the transistors implemented as capacitors320and322are coupled together to form source/drain nodes. One of the source/drain node or the gate of the transistor implemented as a capacitor320is coupled to the gate of the transistor306, and the other of the source/drain node or the gate of the transistor implemented as a capacitator320is coupled to the second output terminal326. Similarly, one of the source/drain node or gate of the transistor implemented as the capacitor322is coupled to a gate of the transistor308, and the other source/drain node and the gate is coupled to the first output terminal324. The transistors implementing the capacitors320and322may be implemented as a transistor with half the size of the input transistors306and308. For example, transistors306and308may have a gate width of approximately 3 micrometers (μm) and a gate length of approximately 16 nanometers (nm), while the transistors implemented as capacitors320and322may have a gate width of approximately 1.5 μm and a gate length of approximately 16 nm. The capacitors in each path effectively add capacitance to the other path to create an equal capacitance to cancel out the kickback current due to drain variation. The capacitors320and322may be approximately 2 femtofarads (fF).

A reset switch328, shown here as a transistor having a gate coupled to receive a reset signal (rst_pre), is implemented for the pre-amplifier302to reset the output nodes of the pre-amplifier. The reset signal may be a low speed clock signal that also controls the switches234and264. The first output terminal324is coupled to a first input332of the latch circuit304, and the second output terminal326is coupled to a second input334of the latch circuit304. Differential digital output signals vop and von are generated at differential output terminals336and338, which are outputs of the comparator circuit202coupled to the SAR circuit208.

Accordingly, the implementation of the capacitors320and322are cross-coupled between the inputs and outputs of the pre-amplifier and function as blocking capacitors to reduce the DC offset, reduce noise on the inputs of the comparator, and reduce kick-back from clocked latch. It should be noted that the neutralization technique is more effective in the pre-amplifier than in the latched comparator because of the small signal nature of the input to the comparator. That is, the cross-coupled capacitators320and322reduce kickback noise as a result of current from the output nodes to the drains of the transistors306and308that may be relatively large compared to the input signal to the pre-amplifier.

Turning now toFIG. 4, is a more detailed block diagram of the amplifier circuit and a latch circuit of a comparator ofFIG. 2is shown. As shown in the implementation ofFIG. 4, the latch circuit304comprises a clock latch having a first transistor402coupled in parallel with a second transistor404. A gate of the first transistor402is coupled to the output terminal326and a gate of the second transistor404is coupled to the output terminal324. Cross-coupled transistors406and408are also coupled between the drains of the transistors402and404and a second pair of cross-coupled transistors410and411at output nodes412and413, which correspond to the output terminals338and336of the latch circuit304. Drains of the transistors410and411are coupled to a low power reference voltage (avcc_I) at a node414. The high power reference avcc_h is provided to the pre-amplifier302to ensure that the signal provided to the inputs of the latch circuit304is large enough to ensure accurate outputs of the latch. Sources of the transistors402and404are coupled to a transistor416at a node418, where the transistor416controls a current path to ground.

The circuit ofFIG. 4further comprises transistors for resetting nodes of the clocked latch using a reset latch (rst_latch) signal. The reset latch signal is coupled to a gate of N-channel transistor416, and turns on the transistor416to enable the latching of data on the output terminals324and326to the output nodes413and412when the reset latch signal is high. A plurality of PMOS transistors are also provided reset nodes of the latch. In particular, a first PMOS transistor419is coupled between the drains of transistors402and404, and the sources of transistors406and408are coupled to the drains of transistors420and422respectively. A transistor424is also coupled across the drains of transistors406and408. Transistors426and428are also coupled in parallel with transistors410and411, respectively. The PMOS transistors are provided to ensure that the nodes of the latch are quickly returned to desired voltages.

Turning now toFIG. 5, a timing diagram shows the waveform of the signal at the inputs to the comparator circuit ofFIG. 2. In operation, the capacitors of the circuit ofFIG. 2are selectively switched in or out, from the higher capacitor values to the lower capacitor values, to determine a value of the yin and vip signals. The capacitors preferably decrease in size by a factor of 2 (from the first capacitor220to the last capacitor230and from the first capacitor250to the last capacitor260) so that the voltages applied to the inputs of the comparator will enable the comparator to determine when the difference between the yin and vip values is equal to zero. That is, by the capacitors are selectively applied to the input nodes until the correct combination of capacitors enables convergence to the voltage value that results in a zero difference between the yin and vip values. In particular, during a sample and hold (S&H) period between times t0and t1, the switches234and264are closed, enabling the capacitors to charge. After the switches234and264are opened at time t1, bits generated on control lines210and240controlling a corresponding capacitor are then selectively switched, from the most significant bit, bit6, to the least significant bit, bit0, to determine the voltage associated with the capacitors that lead to a zero differential between the input signal, and therefore to determine the magnitude of the analog inputs signals yin and vip. An example of the switching of capacitors to enable a convergence to a zero differential at the inputs of the comparator is shown inFIG. 5, where 6 capacitors enable a seven bit output (enabling the detection of one of 128 bit voltage levels).

Because the minimized capacitance at the pre-amplifier input leads to increased input impedance, CDAC is susceptible to kick back noise from latch, even with pre-amplifier, as illustrated with the noise signals shown inFIG. 5. The kick back noise during the conversion period appears as dynamic error, and therefore degrades the ADC's overall accuracy. The waveform shown by the lighter lines indicates the noise on the output signal of the comparator that would be present in a conventional circuit. In order to minimize the error, the neutralization technique of implementing capacitors320and322reduces noise on the output signal. As shown by the solid waveforms inFIG. 5, the kickback cancellation technique effectively reduces the conversion error, which significantly improves the overall ADC performance. This technique enables much smaller CDAC design without sacrificing accuracy, which enables high speed, highly accurate, low power ADC design.

Turning now toFIG. 6, a flow chart shows a method of implementing an analog-to-digital circuit. The method ofFIG. 6may be implemented using an amplifier circuit having first and second amplifier inputs and first and second amplifier outputs, such as amplifier circuit302comprising a pre-amplifier, where an amplified differential analog input signal is generated at the first amplifier output and the second amplifier output. The amplifier circuit may comprise capacitors that are coupled between inputs and outputs, as described above reference toFIG. 3.

In particular first capacitor, such as capacitor320, may be coupled between the first amplifier input associated with a first amplifier current path and the second amplifier output associated with a second amplifier current path. The first capacitor may comprise a third transistor having a source connected to a drain to form a source/drain node of the third transistor, where one of a gate and the source/drain node of the third transistor is coupled to the gate of a first transistor and the other of the gate and the source/drain node of the third transistor is coupled to a drain of a second transistor.

A second capacitor such as capacitor322may be coupled between the second amplifier input associated with the second current path and the first amplifier output associated with the first current path. The second capacitor may comprise a fourth transistor having a source connected to a drain to form a source/drain node of the fourth transistor, where one of a gate and the source/drain node of the fourth transistor is coupled to the gate of the second transistor and the other of the gate and the source/drain node of the fourth transistor is coupled to a drain of the first transistor. A first resistive load may be coupled between a reference voltage and the first transistor of the first amplifier current path, wherein a first input signal of the differential analog input signal is coupled to a gate of the first transistor. Similarly, a second resistive load may be coupled between the reference voltage and the second transistor of the second amplifier current path, wherein a second input signal of the differential analog input signal is coupled to a gate of the second transistor.

According to the method ofFIG. 6, a differential analog input signal is received at the first amplifier input and the second amplifier input at a block602. An amplified differential analog input signal is generated at a first amplifier output and a second amplifier output at a block604. Data is latched at a first latch input coupled to the first amplifier output and at a second latch input coupled to the second amplifier output at a block606. A differential digital output signal based upon the amplified differential analog input signal is generated at a first latch output and a second latch output at a block608.

During operation, a current source is coupled from a source of the first transistor and a source of the second transistor to a ground node, such as by a current source312shown inFIG. 3. A clock signal is coupled to a clock input of the clocked latch, such as shown inFIG. 4, to enable the resetting the latch. The latch may be reset after the capacitors220-230and250-260are charged and the switches234and264are then opened.

Turning now toFIG. 7, a method of implementing an analog-to-digital converter circuit in a capacitive DAC is shown. That is, the amplifier circuit may be implemented as part of a comparator used in a capacitive DAC, as described above. More particularly, a first plurality of capacitors may be selectively coupled to the first amplifier input of the amplifier circuit to provide an analog voltage to the first amplifier input at block702. A second plurality of capacitors may be selectively coupled to the second amplifier input of the amplifier circuit to provide an analog voltage to the second amplifier input at a block704. After the capacitators are charged during a sample and hold period, the capacitor are selectively toggled by a higher speed clock than the clock controlling the switches234and264and the reset signal to enable convergence to a zero differential value between inputs of the comparator, as set forth above. A first input of a successive approximation register circuit may be coupled to the first latch output and a second input of the successive approximation register may be coupled to the second latch output at a block706, where an output value indicating a voltage level of the input signal is generated at an output of the successive approximation register circuit at a block708. While the method ofFIGS. 6 and 7may be implemented using the circuits as described above in reference toFIGS. 1-4, other suitable circuits could be implemented.

It can therefore be appreciated that new circuits and methods of implementing an analog-to-digital converter circuit have been described. It will be appreciated by those skilled in the art that numerous alternatives and equivalents will be seen to exist that incorporate the disclosed invention. As a result, the invention is not to be limited by the foregoing embodiments, but only by the following claims.