Asymmetric network infrastructure with distributed broadcast-select switch and asymmetric network interface controller

Network infrastructure systems including asymmetric Distributed Broadcast Select Switches and Asymmetric Network Interface Controllers for implementation in asymmetric networks and more particularly in cluster networks are provided.

FIELD OF THE INVENTION

The present disclosure relates to network infrastructure, and particularly to cluster network architecture including network switches and network interface controllers, their configuration and interconnection.

BRIEF SUMMARY

According to a first aspect, there is provided a system for a communication infrastructure in a network, the system comprising: an asymmetric crossbar switch including a crossbar switch fabric having N ingress ports and M egress ports, and N×M cross-points, each egress and ingress port having the same capacity, N being less than M, and the asymmetric crossbar switch configured to controllably switch to any egress port a signal arriving at any one ingress port; and at least one select receiver, each select receiver coupled to K egress ports of the M egress ports.

In some embodiments, the asymmetric crossbar switch is comprised in a distributed broadcast select switch (DBSS) controlling the asymmetric crossbar switch to switch signals received over the ingress ports to the egress ports with use of packet addresses in said signals.

In some embodiments, the N ingress ports of the DBSS are coupled to N transmitters and N×K of the M egress ports of the DBSS are coupled to the at least one select receiver, the at least one select receiver consisting of N select receivers, K being less than N, and M greater than or equal to N×K.

In some embodiments, each select receiver is comprised in a corresponding asymmetric network interface controller (ANIC) comprising K input ports and at least one output port, the number of output ports less than K.

In some embodiments, each ANIC comprises a selection and buffer logic for buffering and selecting packets received by the corresponding select receiver, wherein each select receiver includes K receivers each including one of said K input ports.

In some embodiments M is equal to N×K.

In some embodiments, the network comprises a Clos network, wherein M is equal to (N/2)×(K+1), wherein the DBSS is implemented as a last stage top of rack switch of the Clos network.

In some embodiments, a first N/2 of the N ingress ports are coupled to an adjacent level of the Clos network to the DBSS, a second N/2 of the N ingress ports are coupled to a previous hop DBSS, and N egress ports of the DBSS are coupled to a next hop DBSS.

In some embodiments, the network comprises a cluster network. In some embodiments, the cluster network is a direct interconnection cluster network.

According to another aspect, there is provided a system for a communication infrastructure in a network, the system comprising: an asymmetric network interface controller (ANIC) comprising at least one transmitter and a select receiver including K receivers, each receiver having an input port and each transmitter having an output port, each input and output port having the same capacity, the number of transmitters less than K.

In some embodiments, the ANIC comprises a selection and buffer logic for buffering and selecting packets received by the K receivers of the select receiver.

In some embodiments, the input ports of the ANIC are coupled to K egress ports of an asymmetric crossbar switch.

In some embodiments, the ANIC is comprised in a compute node of a cluster network.

In some embodiments, the ANIC is comprised in storage equipment of a datacenter network.

According to another aspect, there is provided a system for a communication infrastructure in a network, the system comprising: an asymmetric crossbar switch comprising a crossbar switch fabric having N ingress ports and M egress ports, and N×M cross-points, each egress and ingress port having the same capacity, N not equal to M, and the asymmetric crossbar switch configured to controllably switch to any egress port a signal arriving at any one ingress port. In some embodiments N is less than M.

In some embodiments, the N ingress ports of the DBSS are coupled to N transmitters and N×K of the M egress ports of the DBSS are coupled N select receivers, each select receiver coupled to K egress ports, K being less than N, and M greater than or equal to N×K.

The foregoing and additional aspects and embodiments of the present disclosure will be apparent to those of ordinary skill in the art in view of the detailed description of various embodiments and/or aspects, which is made with reference to the drawings, a brief description of which is provided next.

DETAILED DESCRIPTION

Contemporary networks are popularly built with symmetric switch fabric and network ports that have the same transmitting and receiving capability. Symmetric networks with the same transmitting and receiving capacity are popularly deployed in Telecom networks, Data centers, High-Performance Computing, and various kinds of clusters. While symmetric network design fits some networks in which the major workload is peer-to-peer even, e.g. telephone, such a configuration is often not well suited for communication traffic of a cluster network, in which multicast and incast are prevalent.

Asymmetric networks with more receiving capacity than transmitting capacity have been proposed quite early in the form of shared media Ethernet, and have been deployed for home access networks, e.g. GPON, GEPON etc.

In the middle of the 1990s, after the optical fibre network became available, optical-based networks were intensively studied, and optical broadcast-select networks were also discussed, including designs with WDM in which they are visibly asymmetric for multiple wavelengths receivers. While the optical WDM enhanced architecture has many advantages, many of them are fixed cross-connection based. The optical switch-based architectures are slow for the lack of fast optical switch components, and more importantly, these architectures cannot be seamlessly integrated into silicon switch chips.

The Broadcast Select Switch (B&S) has been studied for some time, and is currently well-known technology. When optical fibre communication became available, researchers found the B&S switch an interesting architecture again and proposed many new optical fibre-based architectures. The study of optical B&S switches shows the remarkable performance gain of multicast. However, these new optical architectures ask the owners to build an additional optical infrastructure with independent optical switches or cross-connections. The challenge and inconvenience of that proposal is not only extra financial construction and maintenance costs, but also the limited performance and flexibility of currently available optical switches.

Multicast and incast traffic patterns are long-standing challenges in the design and management of cluster networks. In cluster networks, each storage and/or computing node communicates with more than one peer to collaborate, which introduces multicast. Within a network based so heavily on multicast, the occurrence of incast is practically guaranteed. Furthermore, even in networks whose network traffic is only unicast, it needs to be perfectly balanced to reduce random instances of incast. However, in the transit between equivalent balanced network configurations, burst incast still occurs. In the traffic patterns of cluster networks, multicast and incast are essential. It should be understood that other kinds of networks including those which are not cluster networks exhibit multicast and incast traffic patterns.

With multicast and incast traffic, the demands on the receiving capacity of network interface controllers is consistently higher than the demands on transmitting capacity. The cluster network should be constructed with asymmetric elements, namely with network interface controllers which have a greater receiving capacity than transmitting capacity, and often in combination with switches having greater egress capacity than ingress capacity. Combinations of asymmetric switches and asymmetric network interface controllers form asymmetric network infrastructure which advantageously addresses the asymmetric nature of the demands created by multicast and incast traffic patterns.

Techniques for developing reliable multicast have been proposed, for example, the popular Gossip protocol implementation is an overlay on top of unicast, but that introduces high latency and a heavy burden to the switch fabric. Another recent proposal, one by the inventors listed in connection with the present disclosure, for a reliable multicast over Optical Distributed Broadcast-Select Switch (ODBSS), is notably asymmetric for the transceivers and switch fabric. While it introduces a scalable, reliable, and arbitrary multicast service with low-latency, it demands an N×(N{circumflex over ( )}2) switch fabric and N receiving bandwidth for each receiving port. That can only be implemented with DWDM optical with a relatively small subnet, e.g. 40-400 ports.

As mentioned above, the asymmetric network is much more appropriate for cluster networks for its multiple peers' collaboration communication pattern. Direct interconnection networks or direct connection networks, e.g. Torus, Hypercube and Meshes, used to be the major architecture for cluster networks before the rise of the VLSI (Very-large-scale integration) based switch, but even today, direct interconnection networks are still used in many cluster networks. Since their transceivers are physically symmetric, it is easy to ignore that they often work in asymmetric modes in that transmitters often use less of their capacity while the receivers often are fully loaded.

Disclosed herein are Distributed Broadcast Select Switches (DBSSs) and Asymmetric Network Interface Controllers (ANICs), which are not optically coupled, for implementing generic asymmetric cluster networks to solve the aforementioned currently open problems of multicast and incast traffic patterns as well as the costs and other drawbacks of optical WDM and B&S architectures mentioned above. Also disclosed are example embodiments of asymmetric networks constructed with those interface controllers and switches, including combinations with popular network topologies: Multi-stage networks (e.g. FatTree) and Direct Interconnection Networks (e.g. Torus and Hypercube). Such combinations are believed to improve peak bandwidth and locality and to lower latency and power consumption

Distributed Broadcast Select Switch (DBSS)

With reference toFIG.1, a Distributed Broadcast Select Switch (DBSS)120that is not coupled with optical switches nor optical cross-connections, will now be discussed.

The DBSS120, primarily is comprised of an asymmetric crossbar switch101having ingress ports or inputs104for receiving ingress or input signals102and egress ports or outputs107for transmitting egress or output signals103. The DBSS120includes a switching fabric with cross-points105for switching ingress signals102to the output ports107. The cross-points105of the switching fabric of the crossbar switch101may be implemented with any structure capable of forwarding data toward the next egress lines and toward the egress ports such as the cross-point105. With reference also toFIG.11, a cross point1105(corresponding to cross-point105ofFIG.1) will now be discussed. Data packets1108are shifted through registers1104, first in both directions, however, control1102determines whether the packet continues in either directions or both, i.e. shifted toward the egress port (downward inFIG.11) and/or shifted to continue to the next egress line in the crossbar switch101. InFIG.11there is independent control of whether the data packet is to be forwarded in either direction, however in some embodiments the packet is automatically copied to the next egress line and only whether the packet is to continue to be shifted toward the egress port is controlled. Clock signal1188is provided to each shift register1104and control1102circuit. Although not shown, the asymmetric crossbar switch101is controlled by a controller of the DBSS120which uses packet addressing, for example, MAC addresses, to configure which of the inputs104, is switched to which of the outputs107for incoming packets. As such, control circuits1102are ultimately controlled by a controller of the DBSS120.

The asymmetric crossbar switch101and the DBSS120are asymmetric, specifically, the number of outputs107exceeds the number of inputs104. Each input104and output107has the same network traffic capacity and hence, since each output107at any one time is switched from one of the inputs104, each input104may be switched to one or more of the outputs107at any one time. It is also noted that the inputs104and outputs107are generic and data agnostic, i.e. any of the inputs104may be switched to any of the outputs107. This is to be distinguished from typical known crossbar switches which are either symmetrical, having the exact same number of inputs and outputs, or are arranged to switch signals of different types and having special functions to corresponding preset lines and outputs.

In one embodiment, N transmitters (not shown) connected to the DBSS's120N inputs102have a corresponding N select receivers (not shown) connected to the DBSS's120N×K outputs107, each of the N select receivers having K (K<<N) receiving ports for receiving K output connections112each.FIG.1has K output connections112shown in a group from the outputs107of the crossbar switch101. Each group of K output connections112, in this embodiment are destined for one asymmetric network interface controller (ANIC) housing a single select receiver described further below.

Each output103of the crossbar switch is connected to one of N incoming connections102. The crossbar switch has N×(N×K) (i.e. N2K) cross-points105. This is K times higher than a typical cross-bar which has N×N (i.e. N2) cross points, but still, much less than N×(N×N) (i.e. N3) proposed by the authors in an ODBSS. Although the DBSS120cannot achieve arbitrary lossless multicast, the dynamic functioning of a silicon asymmetric crossbar switch101introduces other features the static optical cross-connection lacks.

In some embodiments, the number of outputs107is not related to the number of inputs104according to the formulas noted above. In some embodiments, the number of select receivers does not equal the number of inputs104. In other embodiments, the number of outputs107does not equal an integer multiple of the inputs104. In some embodiments, with N inputs, only a subset of the outputs of each group of N groups of outputs are connected to the same ANIC.

In some embodiments, the number of outputs107is greater than the number of inputs104. In some embodiments, the number of inputs104is not equal to the number of outputs107and in some embodiments, is greater than the number of outputs107.

Asymmetric Network Interface Controller (ANIC)

In the embodiments of the DBSS120discussed above in which multiple (K) output signals112are destined for the same ANIC, a select function is delayed into the network interface controllers, in contrast to a standard Broad-Select Switch (B&S) for which no selection is made in the network interface controller.

With reference toFIG.2, an asymmetric network interface controller (ANIC)240according to an embodiment, as it functions within the communications model200for an asymmetric cluster network will now be discussed.

In the ANIC240, the transmitter249has one transmitting port outputting an output connection206and the select receiver245has K receivers246for receiving K input connections212over K input ports214, one input port214for each receiver246, hence the network interface controller is asymmetric. The selection and buffer logic247chooses the packet that is addressed into this ANIC240, and drops all non-related ones. Since the asymmetric architecture is receive oriented, the selection and buffer logic247of the select receiver245has the prerogative to drop and select packets according to whatever condition, criteria, or high-level logic (e.g. data/application L4-L7) are implemented for its decision to drop and select packets. The selection and buffer logic may be implemented in hardware, software, firmware, or any combination thereof. With reference also toFIG.12, in one embodiment, selection and buffer logic1247(corresponding to selection and buffer logic247ofFIG.2) includes K FIFO buffers1243, one for each of the incoming signals212ofFIG.2, which are passed to the K FIFO buffers1243from the K receivers246ofFIG.2as K incoming signals1244. A reader circuit1242reads the data into K/2 data streams1248.

The packets are then forwarded up the protocol stack (e.g. RDMA/TCP/DPDK/OTHERS225, VERBS/SOCKET/SPDK/OTHERS215) to the application210. The application210may send data packets208for transmission back through the protocol layer stack215225for transmission by the transmitter249in the ANIC240. The packet streams248emerging from the selection and buffer logic247of the select receiver245need not equal K/2 data streams1248as shown in the example ofFIG.12, but may in fact have any capacity less than or equal to the incoming K signals212and as such the packet streams248generally consist of any of 1 to K streams.

The ANIC240and the collaborated software and firmware protocol stack215225offer a very low loss-ratio because packet loss at this stage is very expensive. The loss ratio achieved within the RDMA stack is as low as one of 68 billion.

Each receiver246of the array of K receivers246in the select receiver245can each handle a full line-speed incoming packet of its own single port214, in a lossless manner. Then, the selection and buffer logic247manages the address table, and passes packets to upper layers but drops any packets not selected for forwarding.

The proposed asymmetric switch and interface controller enhances both incast and multicast traffic. For incast traffic, the asymmetric interface controller can take up to K incoming streams simultaneously. That is K times more powerful than commercially popular one port receivers.

For multicast traffic, the asymmetric switch will copy and deliver the multicast packet to all addressed interface controllers, and the interface controllers will deliver the packet to applications and/or data. Since K<<N, loss is still inevitable but is managed to occur prior to the last stage. Since there is no congestion after the copy function, as soon as the packet-copy begins, the architecture is capable of supporting extremely low loss ratios, e.g. one of 10 billion.

In some embodiments, network infrastructure includes asymmetric network interface controllers ANICs240each of which is connected to a DBSS120similar to that ofFIG.1, via K connections. In some embodiments, the asymmetric network interface controller (ANIC)240is coupled to one or more known switches which have been configured to provide the ANIC240with multiple simultaneous connections over its K input ports214. In some embodiments, the network infrastructure includes ANICs240but does not include any DBSS120similar to that ofFIG.1. In some embodiments, the network infrastructure includes the ANIC240in a computing node, storage equipment, or other network node or network equipment. In some embodiments the number of transmitters249is greater than one but less than the number K of receive ports214.

With reference toFIG.3, network infrastructure330including a combination of a DBSS similar to that ofFIG.1and an ANIC similar to that ofFIG.2according to an embodiment, will now be discussed.

The network infrastructure330includes a combination of a DBSS320such as that ofFIG.1specifically having N inputs304and N×K outputs307destined for N select receivers (Select RX NIC)345, each having K input ports314.

The DBSS320, is comprised of an asymmetric crossbar switch301having ingress ports or inputs304for receiving ingress or input signals302and egress ports or outputs307for transmitting egress or output signals303. The DBSS320includes a switching fabric with cross-points305for switching ingress signals302to the output ports307. The cross-points305of the switching fabric of the crossbar switch301may be implemented with any structure capable of forwarding data toward the next egress lines and toward the egress ports such as the cross-point described in association withFIGS.1and11. Although not shown, the asymmetric crossbar switch301is controlled by a controller of the DBSS320which uses packet addressing, for example, MAC addresses, to configure which of the inputs304, is switched to which of the outputs307for incoming packets.

The asymmetric crossbar switch301and the DBSS320are asymmetric, specifically, the number N×K of outputs307exceeds the number N of inputs304. Each input304and output307has the same network traffic capacity and hence, since each output307at any one time is switched from one of the inputs304, each input304may be switched to one or more of the outputs307at any one time. It is also noted that the inputs304and outputs307are generic and data agnostic, i.e. any of the inputs304may be switched to any of the outputs307.

In the embodiment shown, N transmitters (not shown) connected to the inputs302of the DBSS320have a corresponding N select receivers345connected to the N×K outputs307of the DBSS320, each of the N select receivers345having K receiving ports314for receiving K output connections312each. A group of K output connections312from the outputs307of the asymmetric crossbar switch301is shown inFIG.3. Each group of K output connections312, in this embodiment is destined for one asymmetric network interface controller (ANIC not shown) which includes a select receiver345receiving each signal312at one of its K input ports314.

Each output303of the crossbar switch is connected to one of N incoming connections302. The crossbar switch has N×(N×K) (i.e. N2K) cross-points305.

In this embodiment, with N inputs, all of the outputs (K) of each group of N groups of outputs are connected to the same ANIC.

Synergize With Multi-Stage Network

Generally, the proposed asymmetric switch and interface controller can be used in any arbitrary network topology, including popular multi-stage networks, e.g. FatTree in current Datacenters and torus. Datacenters could deploy only Asymmetric Network Interface Controllers (ANICs), or both asymmetric switches and ANICs to improve their performance with respect to incast and multicast.

With reference toFIGS.4,5, and6, a DBSS ToR switch420working in tandem with Asymmetric Network Interface Controllers (ANICs)440as a last stage of an asymmetric Clos network600will now be discussed. In data centers, the Clos network is well known (also referred to as a FatTree), and the last stage is well-known as a ToR (Top of Rack) switch.

A popular three-stage Clos network500is shown inFIG.5. Each of the switches510,512,514in the network infrastructure of the Clos network500has an input capacity which is the same as its output capacity and since the capacity of each input is the same as each output, the Clos network500has the same number of inputs504as outputs507and the same number of input connections502as output connections506. The total number of outputs or inputs each switch possesses depends upon the network topology. In the example shown inFIG.5, there are fewer switches510,514at the base and the top of the tree than there are switches512in the middle of the tree, and hence the switches510,514at the base and the top of the tree each have more inputs and outputs than the number of inputs and outputs possessed by each switch512in the middle of the tree.

With reference toFIG.4, a network infrastructure450variation of a combination of a DBSS similar to that ofFIG.1implemented as an asymmetric (ToR) switch (DBSS ToR420) and servers including the ANIC440similar to that ofFIG.2, will now be discussed.

The network infrastructure450includes a combination of a DBSS ToR420specifically having 2N inputs404and N×(K+1) outputs407, N×K of which are destined for N select receivers (Select RX NIC)445, each having K input ports414, and the remaining N outputs407generating N output signals418for the next hop (another DBSS ToR420).

The DBSS ToR420, primarily is comprised of an asymmetric crossbar switch401having ingress ports or inputs404for receiving ingress or input signals402and egress ports or outputs407for transmitting egress or output signals403. The DBSS ToR420includes a switching fabric with cross-points405for switching ingress signals402to the output ports407. In the embodiment depicted inFIG.4, half of the ingress signals402are from a previous hop402A (another DBSS ToR420) while the other half of the ingress signals402B are from the adjacent layer of the Clos network. In this embodiment, there are a total of 2N ingress signals402, N from a previous hop402A and N from the adjacent level in the Clos network402B.

The cross-points405of the switching fabric of the crossbar switch401may be implemented with any structure capable of forwarding data toward the next egress lines and toward the egress ports such as the cross-point described in association withFIGS.1and11. Although not shown, the asymmetric crossbar switch401is controlled by a controller of the DBSS ToR420which uses packet addressing, for example, MAC addresses, to configure which of the inputs404, is switched to which of the outputs407for incoming packets.

The asymmetric crossbar switch401and the DBSS ToR420are asymmetric, specifically, the number N×(K+1) (K≥2) of outputs407exceeds the number 2N of inputs404. Each input404and output407has the same network traffic capacity and hence, since each output407at any one time is switched from one of the inputs404, each input404may be switched to one or more of the outputs407at any one time. It is also noted that the inputs404and outputs407are generic and data agnostic, i.e. any of the inputs404may be switched to any of the outputs407.

In the embodiment shown, 2N transmitters (not shown) connected to the 2N inputs402of the DBSS ToR420have a corresponding N select receivers445connected to the N×K outputs407of the DBSS ToR420, each of the N select receivers445having K receiving ports414for receiving K output connections412each. A group of K output connections412from the outputs407of the asymmetric crossbar switch401is shown inFIG.4. Each group of K output connections412, in this embodiment, is destined for one asymmetric network interface controller (ANIC)440which includes a select receiver445receiving each signal412at one of its K input ports414. In some embodiments each ANIC440is housed in a server (not shown) which is connected to the DBSS ToR420via a group of K outputs412.

The remaining N output connections418are destined for the next hop, i.e. the next DBSS ToR420.

Each output403of the asymmetric crossbar switch401is connected to one of 2N incoming connections402. The crossbar switch has 2N×(N×(K+1)) cross-points405. In this embodiment, with 2N inputs, only a subset (K) of all the outputs (K+1) of each group of N groups of outputs are connected to the same ANIC440.

The architecture of the DBSS ToR420utilized in the last stage, as illustrated inFIG.4is similar the DBSS120illustrated inFIG.1. Indeed, this is just a specific deployment of the generic architecture ofFIG.1. In other embodiments, notable differences of next-hop traffic demand different K and N from that shown specifically inFIG.4.

A Clos network600including multiple DBSS ToR switches620similar to the DBSS ToR420ofFIG.4is shown inFIG.6. As described in connection withFIG.4, the DBSS ToR620has 2N inputs where half (N) of these inputs602B are from the adjacent layer of the other switches610in the Clos network, and the other half (N) of these inputs602A are from the previous hop i.e. a previous DBSS ToR620. As discussed in connection withFIG.4, N outputs618proceed to the next hop (another DBSS ToR620not shown) while N×K outputs612are output and destined for N ANICs (not shown). InFIG.6, each bold arrow (of the set of N) in the outputs612represents K output signals.

DBSS and ANIC in Direct Interconnection Network

Direct Interconnection Networks were introduced before the switch and is still popularly used in High-Performance Computing and other cluster network based applications. The multi-dimensional approach to network scaling and its routing and control are well studied in Direct Interconnection Networks such as Torus, Hypercube, and B-Cube. A well-known 2D torus direct-interconnection network700is illustrated inFIG.7, in which nodes710are directly connected by connections708in a square mesh of two dimensions, each dimension looping back on itself, forming the topology of a 2D torus.

It should be noted that the connections in this known network do not have any logic functionality. Switching and other logic functions are distributed into the computing-storage-switch nodes710.

With reference toFIG.8, a hybrid DBSS augmented 2D torus direct-interconnection network800will now be discussed. The direct interconnected 2D torus of known networks is retained, and nodes810are directly connected by connections808in a standard manner to form a 2D torus direct-interconnection network.

Augmenting this network infrastructure are first DBSSs820B, each first DBSS820B connected to all nodes810of a corresponding “row” of the mesh defining the torus and second DBSSs820A, each second DBSS820A connected to all nodes of a corresponding “column” of the mesh defining the torus. Each DBSS820A820B acts as a hub connected to all nodes810of a corresponding orthogonal “slice” of the mesh defined by the dimensions of the torus.

Each connection between the DBSS820A820B and a node810includes output signals812from the DBSS820A820B to the node810and input signals806to the DBSS820A820B from the node810. In some embodiments, the total number of output signals812per connection is greater than the total number of input signals806per connection. In some embodiments, the number of input signals806to any DBSS820A820B from nodes it is connected to is N, and the total number of output signals812to nodes it is connected to is N×K.

Each node810in the embodiment ofFIG.8includes an ANIC (not shown) for every DBSS820A820B it is connected to, each ANIC receiving the K output signals812of that connection.

As can be extrapolated fromFIG.8, augmenting the direct-interconnection network with DBSSs820A820B can reduce the longest hop-count, or network diameter, as well as latency depending upon the overall size of the network and its topology. For instance, in a 2D Mesh/Torus of 12×12=144 nodes, the longest hop-count is 2 vs. 22 (11+11). That could lead to better latency by a factor of at least 10× and possibly much more, the bigger the cluster, the better the latency advantage.

Deployment into the Existing Network

Without limiting consideration to any specific network topology, multicast in the network can be described as a 1: N tree, as shown inFIG.9with multicast connections908connecting nodes910.FIG.10illustrates multicast through the same network enhanced by DBSSs1020added into the multicast tree arbitrarily to enhance the multicast function, by helping to reduce the depth of the tree, which in turn reduces the overall load and latency of the entire multicast process.

Some multicast connections1008are replaced by DBSSs1020as hyperedges, each of which multicast1012to some nodes further down the tree to reduce the tree's depth through the DBSS1020. The asymmetric nature of the DBSS1020enable it to switch to more output connections than the number of its inputs. In some embodiments the nodes1010include ANICs, while in other embodiments, they do not.

In one embodiment, the DBSS is deployed using a Spine-Leaf-ToR network topology commonly used in datacenters. In this case, the DBSS is added either within a rack or in-between racks to enhance multicast. In this deployment method, an asymmetric interface controller (or extra interface controller) is provided on the receiving side of the servers.