Semiconductor device

A semiconductor device includes a substrate, an electrode layer disposed on the substrate, and a tri-layered gate-control stack sandwiched between the substrate and the electrode layer. The tri-layered gate-control stack includes a ferroelectric layer disposed on the substrate, a mid-gap metal layer sandwiched between the ferroelectric layer and the substrate, and an anti-ferroelectric layer. The anti-ferroelectric layer is sandwiched between the substrate and the mid-gap metal layer. Alternatively, the ferroelectric layer and the mid-gap metal layer are sandwiched between the anti-ferroelectric layer and the substrate.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including ferroelectric (hereinafter abbreviated as FE) material and anti-ferroelectric (hereinafter abbreviated as AFE) material.

2. Description of the Prior Art

A semiconductor device means any device which can function by utilizing semiconductor characteristics, such as an electro-optical device, a semiconductor circuit, and an electronic device. Accordingly, semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment, as example.

Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layer, conductive layers, and semiconductor layers over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. Since the semiconductor integrated circuit industry has experienced rapid growth and improvement, technological advances in semiconductor materials and design have produced increasingly smaller and more complex circuits. Consequently, the number of interconnected devices per unit of area has increased as the size of the smallest components that can be reliably created has decreased. However, as the size of the smallest components has decreased, numerous challenges have risen. As features become closer, current leakage can become more noticeable, signals can crossover more easily, and power usage has become a significant concern. Typically, when a gate bias of a metal-oxide-semiconductor field effect transistor (hereinafter abbreviated as MOS FET) device is below the threshold voltage Vth, the current flow between the source and the drain, which is defined as the subthreshold current, is supposed to be zero. Or, the subthreshold current was supposed to be very small and thus in early analytical models of the electrical behavior of MOS FET were even assuming a zero off-state current/subthreshold current. Those skilled in the art should have known there is a linear relationship between the subthreshold current and the gate voltage, which is recognized as subthreshold swing (SS). A small subthreshold swing is highly desired since it improves the ratio between the on and off currents, and therefore reduces leakage currents. Using a device with a small subthreshold swing therefore has advantages such as suppression of power consumption due to reduction in operation voltage and reduction in off leakage current. However, the subthreshold swing cannot be less than 60 mV/sec due to the physical limit of MOS FET device in state-of-the-art. Thus, it is still in need to reduce the subthreshold swing despite the physical limit.

SUMMARY OF THE INVENTION

According to an aspect of the present invention, a semiconductor device is provided. The semiconductor device includes a substrate, an electrode layer disposed on the substrate, and a tri-layered gate-control stack sandwiched between the substrate and the electrode layer. The tri-layered gate-control stack further includes a ferroelectric (FE) layer disposed on the substrate, an anti-ferroelectric (AFE) layer sandwiched between the FE layer and the substrate, and a mid-gap metal layer sandwiched between the FE layer and the AFE layer.

According to another aspect of the present invention, a semiconductor device is provided. The semiconductor device includes a substrate, an electrode layer disposed on the substrate, and a tri-layered gate-control stack sandwiched between the substrate and the electrode layer. The tri-layered gate-control stack further includes an AFE layer disposed on the substrate, a mid-gap metal layer sandwiched between the AFE layer and the substrate, and a FE layer sandwiched between the AFE layer and the mid-gap metal layer.

According to still another aspect of the present invention, a semiconductor device is provided. The semiconductor device includes a substrate, an electrode layer disposed on the substrate, and a tri-layered gate-control stack sandwiched between the substrate and the electrode layer. The tri-layered gate-control stack further includes an amorphous dielectric layer, a mid-gap metal layer disposed between the amorphous dielectric layer and the substrate, and a polycrystalline dielectric layer. The mid-gap metal layer directly contacts the amorphous dielectric layer. And the amorphous dielectric layer and the polycrystalline dielectric layer both include hafnium oxide materials.

According to the semiconductor devices provided by the present invention, the tri-layered gate-control stack is provided between the electrode layer and the substrate, and the tri-layered gate-control stack includes the FE layer, the AFE layer and the mid-gap metal layer. It is noteworthy that in the tri-layered gate-control stack, the mid-gap metal layer is always sandwiched between the FE layer and the substrate while the AFE layer is disposed on or under the dual-layered structure consisting of the FE layer and the mid-gap metal layer. The FE layer is provided to enhance electric fields created by the electrode layer and the mid-gap metal layer is provided to homogenize the enhanced electric fields. Furthermore, the AFE layer is provided to render negative capacitance effect. The tri-layered gate-control stack is therefore used to replace conventional high-k gate dielectric layer according to the present invention, and the semiconductor device provided by the present invention therefore obtains smaller subthreshold swing.

DETAILED DESCRIPTION

Please refer toFIG. 1, which is a schematic drawing illustrating a semiconductor device provided by a first preferred embodiment of the present invention. As shown inFIG. 1, a semiconductor device100is proved by the preferred embodiment, and the semiconductor device100includes a substrate102such as silicon substrate, silicon-containing substrate, or silicon-on-insulator (hereinafter abbreviated as SOI) substrate. A plurality of isolation structures (not shown) is formed in the substrate102. The isolation structures can be shallow trench isolations (STIs), but not limited to this. The isolation structures are used to define a plurality of active regions for accommodating p-typed FET (hereinafter abbreviated as pFET) devices and/or n-typed FET (hereinafter abbreviated as nFET) devices, and to provide electrical isolation. In some preferred embodiments of the present invention, a semiconductor layer such as a fin structure involved in fin field effect transistor (FinFET) approach can be provided. The fin structure can be formed by patterning a single crystalline silicon layer of a SOI substrate or a bulk silicon substrate by photolithographic etching pattern (PEP) method, multi patterning method, or, preferably, spacer self-aligned double-patterning (SADP), also known as sidewall image transfer (SIT) method. And the fin structure can be taken as the substrate102in the preferred embodiment.

An electrode layer110is disposed on the substrate102. In the preferred embodiment, metal gate approach is integrated. Accordingly, the electrode layer110includes at least a work function metal layer110a, and the work function metal layer110aincludes various metal materials depending on the conductivity type of the semiconductor device100to be formed: In some embodiments of the present invention, the semiconductor device100is a p-typed semiconductor device, and the work function metal layer110aincludes any suitable metal material having a work function between about 4.8 eV and about 5.2 eV such as titanium nitride (TiN), tantalum nitride (TaN), titanium carbide (TiC), tantalum carbide (TaC), tungsten carbide (WC), or aluminum titanium nitride (TiAlN), but not limited to this. Alternatively, in some embodiments of the present invention, the semiconductor device100is an n-typed semiconductor device, and the work function metal layer110aincludes any suitable metal material having a work function between about 3.9 eV and about 4.3 eV, such as titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), or hafnium aluminide (HfAl), but not limited to this. Additionally, the work function metal layer110acan be a single-layered structure or a multi-layered structure. The electrode layer110further includes a gap-filling metal layer110b, and the gap-filling metal layer110bcan be a single metal layer or a multiple metal layer including superior gap filing ability, such as Al, Ti, Ta, W, Nb, Mo, Cu, TiN, TiC, TaN, Ti/W, or Ti/TiN, but not limited to this. Furthermore, it is well-known to those skilled in the art that a bottom barrier layer, an etch stop layer, and/or a top barrier layer can be included in the electrode layer110if required. As shown inFIG. 1, a bottom barrier layer112is sandwiched between the electrode layer110and the substrate100, and an etch stop layer114is sandwiched between the electrode layer110and the bottom barrier layer112. Additionally, a top barrier layer (not shown) can be sandwiched between the work function metal layer110aand the gap-filling metal layer110b. The etch stop layer114preferably includes material including etching rate different from the bottom barrier layer112. For example but not limited to, the bottom barrier layer112can be a TiN layer and the etch stop layer114can be a TaN layer.

Please still refer toFIG. 1. The semiconductor device100provided by the preferred embodiment further includes a tri-layered gate-control stack120sandwiched between the substrate102and the electrode layer110. The tri-layered gate-control stack120includes a FE layer122disposed on the substrate102, an AFE layer126sandwiched between the FE layer122and the substrate102, and a mid-gap metal layer124sandwiched between the FE layer122and the AFE layer126. In some embodiments of the present invention, the FE layer122includes a material selected from the group consisting of lead zirconate titanate (bZrTiO3, PZT), lead lanthanum zirconate titanate (PbLa(TiZr)O3, PLZT), strontium bismuth tantalate (SrBiTa2O9, SBT), bismuth lanthanum titanate ((BiLa)4Ti3O12, BLT), and barium strontium titanate (BaSrTiO3, BST). The AFE layer126includes a material selected from the group consisting of lead indium niobate (Pb(InNb)O3), niobium-sodium oxide (NbNaO3), lead zirconate (ZrPbO3), lead lanthanum zirconate titanate (TiZrLaPbO3), lead zirconate titanate (TiZrPbO3), ammonium dihydrogen phosphate (NH4H2PO4, ADP), and ammonium dihydrogen arsenate (NH4H2AsO4, ADA). It is noteworthy that the FE layer122and the AFE layer126can include the same elementary material but with different crystalline morphologies and/or composition ratio. For example, both of the FE layer122and the AFE layer126can include hafnium oxide material such as HfZrOx, but the FE layer122includes amorphous HfZrOx while the AFE layer126includes polycrystalline HfZrOx. It is noteworthy that hafnium oxide material can still include other elementary material such as Zr in accordance with the present invention. In other words, in some embodiments of the present invention, the FE layer122is taken as an amorphous or a fractionally crystalized dielectric layer and the AFE layer126is taken as a polycrystalline dielectric layer. The mid-gap metal layer124includes metal having a work function between valence band and conduction band. The mid-gap metal layer124includes metal nitride such as, for example but not limited to, TiN, TaN, titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), or molybdenum nitride (MoN). In other embodiments of the present invention, the mid-gap metal layer124can include nickel silicide (NiSi), tungsten silicide (WSi), cobalt silicide (CoSi2), or titanium tungsten (TiW), but not limited to this.

It is noteworthy that since an antiferromagnetic state will transfer to a paramagnetic state at a temperature over the Neel temperature, high-k last approach is adopted in the preferred embodiments of the present invention in order to avoid the above mentioned issue. It is well-known to those skilled in the art that in the high-k last approach, a dummy gate or a replacement gate (not shown) is formed on the substrate102and followed by forming elements of a FET device such as light doped drains (LDDs)106, a spacer104, and a source/drain108. The dummy gate includes a dielectric layer (not shown), a conductive layer such as a polysilicon layer (not shown), and a patterned hard mask (not shown). The spacer104can be a single-layered structure or a multi-layered structure, but not limited to this. Furthermore, selective strain scheme (SSS) can be used in the preferred embodiments of the present invention. For example, a selective epitaxial growth (SEG) method can be used to form the source/drain. When the semiconductor device100is the p-typed transistor, epitaxial silicon layers of SiGe are used to form the source/drain. When the semiconductor device100is the n-typed transistor, epitaxial silicon layers of SiC or SiP are used to form the source/drain. Additionally, salicides (not shown) can be formed on the source/drain108. After forming the semiconductor device100, an etch liner such as a contact etch stop layer (hereinafter abbreviated as CESL) (not shown) is selectively formed on the substrate100, and an interlayer dielectric (hereinafter abbreviated as ILD) layer130is subsequently formed. Next, a planarization process such as chemical mechanical polishing (CMP) process is performed to planarize the ILD layer130and the CESL. The patterned hard mask is then removed to expose the conductive layer of the dummy gate and followed by removing the conductive layer and the dielectric layer of the dummy gate. Consequently, a gate trench (not shown) is formed on the substrate102. In some preferred embodiments of the present invention, an oxide liner128can be formed in the gate trench and followed by forming the tri-layered gate-control stack120in the gate trench. And after forming the tri-layered gate-control stack120, the abovementioned metal layers are formed. Accordingly, the tri-layered gate-control stack120includes a U shape in the preferred embodiments. The oxide liner128serves as an interfacial layer (IL), and the interfacial layer provides a superior interface between the substrate102and the tri-layered gate-control stack120. Additionally, the bottom barrier layer112and the etch stop layer114are sandwiched between the tri-layered gate-control stack120and the electrode layer110as shown inFIG. 1. It should be easily understood to those skilled in the art that in still other preferred embodiments of the present invention, high-k first approach can be adopted and thus the tri-layered gate-control stack120includes a flap shape in those preferred embodiments.

According to the semiconductor device100provided by the preferred embodiment, the tri-layered gate-control stack120sandwiched between the electrode layer110and the substrate102is provided. The FE layer122(or, the material layer including the ferroelectric characteristic due to its amorphous or fractionally crystalized morphology, such as the amorphous or fractionally crystalized dielectric layer) of the tri-layered gate-control stack120is used to enhance the electric fields created by the electrode layer110. However, it is found the electric fields enhanced by the FE layer122are inhomogeneous. Therefore, the mid-gap metal layer124sandwiched between the FE layer122and the substrate102is provided. The mid-gap metal layer124directly contacts the FE layer (the amorphous or fractionally crystalized dielectric layer) and homogenizes the electric fields enhanced by the FE layer122. Furthermore, the AFE layer126(the material layer including anti-ferroelectric characteristic due to its polycrystalline morphology, such as the polycrystalline dielectric layer) is provided to render negative capacitance effect. Consequently, the subthreshold swing is reduced. Compared with the device including the convention high-k gate dielectric layer, the subthreshold swing of the semiconductor device100provided by the present invention is significantly reduced from 60 mV/dec to 10 mV/dec, which is beyond the physical limit. And thus both leakage current and power consumption are reduced.

Please refer toFIG. 2, which is a schematic drawing illustrating a semiconductor device provided by a second preferred embodiment of the present invention. It should be noted that elements the same in the first and second preferred embodiments can be formed by the same method with the same material, thus those details are omitted in the interest of brevity. As shown inFIG. 2, a semiconductor device200is proved by the preferred embodiment, and the semiconductor device200includes a substrate202. A plurality of isolation structures (not shown) is formed in the substrate202. The isolation structures are used to define a plurality of active regions for accommodating pFET devices and/or nFET devices, and to provide electrical isolation. Furthermore, a semiconductor layer such as a fin structure involved in FinFET approach can be provided and taken as the substrate202in some preferred embodiments of the present invention.

An electrode layer210is disposed on the substrate202. In the preferred embodiment, metal gate approach is integrated. Accordingly, the electrode layer210includes at least a work function metal layer210a, and the work function metal layer210aincludes various metal materials depending on the conductivity type of the semiconductor device200to be formed: In some embodiments of the present invention, the semiconductor device200is a p-typed semiconductor device, and the work function metal layer210aincludes any suitable metal material having a work function between about 4.8 eV and about 5.2 eV. Alternatively, in some embodiments of the present invention, the semiconductor device200is an n-typed semiconductor device, and the work function metal layer210aincludes any suitable metal material having a work function between about 3.9 eV and about 4.3 eV. Additionally, the work function metal layer210acan be a single-layered structure or a multi-layered structure. The electrode layer210further includes a gap-filling metal layer210b, and the gap-filling metal layer210bcan be a single metal layer or a multiple metal layer including superior gap filing ability. Furthermore, it should be easily understood to those skilled in the art that a bottom barrier layer, an etch stop layer, and/or a top barrier layer can be included in the electrode layer210if required. As shown inFIG. 2, a bottom barrier layer212is sandwiched between the electrode layer210and the substrate200while an etch stop layer214is sandwiched between the electrode layer210and the bottom barrier layer212. Additionally, a top barrier layer (not shown) can be sandwiched between the work function metal layer210aand the gap-filling metal layer210b. And the etch stop layer214preferably includes material including etching rate different from the bottom barrier layer212.

Please still refer toFIG. 2. The semiconductor device200provided by the preferred embodiment further includes a tri-layered gate-control stack220sandwiched between the substrate202and the electrode layer210. The tri-layered gate-control stack220includes an AFE layer226disposed on the substrate202, a mid-gap metal layer224sandwiched between the AFE layer226and the substrate202, and a FE layer222sandwiched between the AFE layer226and the mid-gap metal layer224. As mentioned above, the FE layer222and the AFE layer226can include different materials, or the same elementary material but with different crystalline morphologies and/or composition ratio. In other words, the FE layer222can be taken an amorphous or a fractionally crystalized dielectric layer while the AFE layer226can be taken as a polycrystalline dielectric layer.

As mentioned afore, since an antiferromagnetic state will transfer to a paramagnetic state at a temperature over the Neel temperature, high-k last approach is adopted in preferred embodiments of the present invention in order to avoid the above mentioned issue. It is well-known to those skilled in the art that in the high-k last approach, a dummy gate or a replacement gate (not shown) is formed on the substrate202and followed by forming elements of a FET device such as LDDs206, a spacer204, and a source/drain208. And after forming a CESL (not shown) and an ILD layer230, the dummy gate is removed to form a gate trench (not shown) on the substrate202. In some preferred embodiments of the present invention, an oxide liner228can be formed in the gate trench and followed by forming the tri-layered gate-control stack220in the gate trench. And after forming the tri-layered gate-control stack220, the abovementioned metal layers are formed. Accordingly, the tri-layered gate-control stack220includes a U shape in the preferred embodiments. The oxide liner228serves as an interfacial layer, and the interfacial layer provides a superior interface between the substrate202and the tri-layered gate-control stack220. Additionally, the bottom barrier layer212and the etch stop layer214are sandwiched between the tri-layered gate-control stack220and the electrode layer210as shown inFIG. 2. It should be easily understood to those skilled in the art that in still other preferred embodiments of the present invention, high-k first approach can be adopted and thus the tri-layered gate-control stack220includes a flap shape in those preferred embodiments.

According to the semiconductor device200provided by the preferred embodiment, the tri-layered gate-control stack220sandwiched between the electrode layer210and the substrate202is provided. The FE layer222(or the amorphous or fractionally crystalized dielectric layer) of the tri-layered gate-control stack220is used to enhance the electric fields created by the electrode layer210. However, it is found the electric fields enhanced by the FE layer222are inhomogeneous. Therefore, the mid-gap metal layer224sandwiched between the FE layer222and the substrate202is provided. The mid-gap metal layer224directly contacts the FE layer (the amorphous or fractionally crystalized dielectric layer) and homogenizes the electric fields enhanced by the FE layer222. Furthermore, the AFE layer226(the polycrystalline dielectric layer) is provided to render negative capacitance effect. Consequently, the subthreshold swing is reduced. Compared with the device including the convention high-k gate dielectric layer, the subthreshold swing of the semiconductor device200provided by the present invention is significantly reduced to be lower than 60 mV/dec, which is still beyond the physical limit. And thus both leakage current and power consumption are reduced.

According to the semiconductor devices provided by the present invention, the tri-layered gate-control stack is provided between the electrode layer and the substrate, and the tri-layered gate-control stack includes the FE layer (or the amorphous or fractionally crystalized dielectric layer in some conditions), the AFE layer (or the polycrystalline dielectric layer in some conditions), and the mid-gap metal layer. It is noteworthy that in the tri-layered gate-control stack, the mid-gap metal layer is always sandwiched between the FE layer and the substrate while the AFE layer is disposed on or under the dual-layered structure consisting of the FE layer and the mid-gap metal layer. Preferably, the mid-gap metal layer directly contacts the FE layer. The FE layer is provided to enhance electric fields of the electrode layer and the mid-gap metal layer is provided to homogenize the enhanced electric fields. Furthermore, the AFE layer is provided to render negative capacitance effect. The tri-layered gate-control stack is therefore used to replace conventional high-k gate dielectric layer according to the present invention, and the semiconductor device provided by the present invention obtains smaller subthreshold swing, and thus both leakage current and power consumption are reduced.