Semiconductor package and method of fabricating the same

A method of fabricating a semiconductor package includes forming a capping pattern on a chip pad of a semiconductor device. The semiconductor device includes a passivation pattern that exposes a portion of the chip pad, and the capping pattern covers the chip pad. The method further includes forming a redistribution layer on the capping pattern. Forming the redistribution layer includes forming a first insulation pattern on the capping pattern and the passivation pattern, forming a first opening in the first insulation pattern by performing exposure and development processes on the first insulation pattern, in which the first opening exposes a portion of the capping pattern, and forming a redistribution pattern in the first opening.

TECHNICAL FIELD

Exemplary embodiments of the inventive concept relate to a semiconductor package and a method of fabricating the same, and more particularly, to a semiconductor package including a redistribution layer and a method of fabricating the same.

DISCUSSION OF THE RELATED ART

A semiconductor package is provided to implement an integrated circuit chip in electronic products. Typically, a semiconductor package is configured such that a semiconductor chip is mounted on a printed circuit board (PCB), and bonding wires or bumps are used to electrically connect the semiconductor chip to the printed circuit board. As advancements are made in the electronics industry, research is being performed to improve the reliability and durability of semiconductor packages.

SUMMARY

Exemplary embodiments of the inventive concept provide a semiconductor package having improved reliability and durability, and a method of fabricating the same.

According to exemplary embodiments of the inventive concept, a method of fabricating a semiconductor package includes forming a capping pattern on a chip pad of a semiconductor device. The semiconductor device includes a passivation pattern that exposes a portion of the chip pad, and the capping pattern covers the chip pad. The method further includes forming a redistribution layer on the capping pattern. Forming the redistribution layer includes forming a first insulation pattern on the capping pattern and the passivation pattern, forming a first opening in the first insulation pattern by performing exposure and development processes on the first insulation pattern, in which the first opening exposes a portion of the capping pattern, and forming a redistribution pattern in the first opening.

According to exemplary embodiments of the inventive concept, a method of fabricating a semiconductor package includes forming a chip pad on a semiconductor device, and forming a passivation pattern on the semiconductor device and the chip pad. The passivation pattern includes an opening that exposes a portion of the chip pad. The method further includes forming a capping pattern in the opening. The capping pattern covers the chip pad. The method further includes disposing the semiconductor device on a redistribution layer, and electrically connecting the chip pad to the redistribution layer by forming a connector between the capping pattern and the redistribution layer.

According to exemplary embodiments of the inventive concept, a semiconductor package includes a redistribution layer and a semiconductor device disposed on the redistribution layer. The semiconductor device includes a chip pad and a passivation pattern. The passivation pattern includes a pad opening that exposes a portion of the chip pad. The semiconductor package further includes a capping pattern disposed in the pad opening and covering the chip pad, and a molding pattern disposed on the redistribution layer and covering the semiconductor device. The redistribution layer includes a first insulation pattern in direct contact with the passivation pattern and extending onto a bottom surface of the molding pattern, and a redistribution pattern disposed on the first insulation pattern and electrically connected to the capping pattern.

According to exemplary embodiments of the inventive concept, a semiconductor package includes a redistribution layer and a semiconductor device disposed on the redistribution layer. The semiconductor device includes a chip pad and a passivation pattern. The passivation pattern includes a pad opening that exposes a portion of the chip pad. The semiconductor package further includes a capping pattern disposed in the pad opening and covering the chip pad, and a connector disposed between the redistribution layer and the capping pattern and coupled to the capping pattern.

According to exemplary embodiments of the inventive concept, a semiconductor package includes a redistribution layer and a semiconductor device disposed on the redistribution layer. The semiconductor device includes a chip pad and a passivation pattern. The passivation pattern includes a pad opening that exposes a portion of the chip pad. The semiconductor package further includes a capping pattern disposed in the pad opening and covering the chip pad, a first opening disposed in the redistribution layer that exposes a portion of the capping pattern, and a redistribution pattern disposed in the first opening and contacting the exposed portion of the capping pattern.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

Exemplary embodiments of the present inventive concept will be described more fully hereinafter with reference to the accompanying drawings. Like reference numerals may refer to like elements throughout the accompanying drawings.

It will be understood that when a component, such as a film, a region, a layer, or an element, is referred to as being “on”, “connected to”, “coupled to”, or “adjacent to” another component, it can be directly on, connected, coupled, or adjacent to the other component, or intervening components may be present (unless the context clearly indicates otherwise). It will also be understood that when a component is referred to as being “between” two components, it can be the only component between the two components, or one or more intervening components may also be present (unless the context clearly indicates otherwise). It will also be understood that when a component is referred to as “covering” another component, it can be the only component covering the other component, or one or more intervening components may also be covering the other component (unless the context clearly indicates otherwise).

FIG. 1Aillustrates a cross-sectional view showing a semiconductor device according to exemplary embodiments of the inventive concept.FIG. 1Billustrates an enlarged view showing section A ofFIG. 1Aaccording to exemplary embodiments of the inventive concept.FIG. 1Cillustrates an enlarged view showing section B ofFIG. 1Baccording to exemplary embodiments of the inventive concept.

Referring toFIGS. 1A, 1B, and 1C, in an exemplary embodiment, a semiconductor device100includes a semiconductor substrate110, a circuit layer120, a passivation pattern160, and a chip pad150. The semiconductor device100may be, for example, a semiconductor chip including a memory chip, a logic chip, or any combination thereof. The semiconductor substrate110may include a semiconductor material such as, for example, silicon, germanium, or silicon-germanium. The circuit layer120is disposed on one surface of the semiconductor substrate110. As illustrated inFIG. 1B, the circuit layer120may include an insulation layer121, integrated devices125(also referred to as integrated circuits125), and internal lines123. The integrated devices125are disposed on the one surface of the semiconductor substrate110. The integrated devices125may include, for example, transistors. The insulation layer121is disposed on the one surface of the semiconductor substrate110, and covers the integrated devices125. The insulation layer121may include a plurality of layers. The internal lines123are disposed in the insulation layer121. The internal lines123are electrically connected to the integrated devices125. Herein, when components are referred to as being electrically connected/coupled to each other, the components may be directly connected/coupled to each other, or may be indirectly connected/coupled to each other through another conductive component. Further, when a component is described as being electrically connected to the semiconductor device100, the component may be electrically connected to the integrated devices125of the semiconductor device100.

The chip pad150is disposed on the circuit layer120. The chip pad150may include metal such as, for example, aluminum. One or more chip pads150may be electrically connected to the integrated devices125through the internal lines123.

The passivation pattern160is disposed on the circuit layer120. The passivation pattern160includes a pad opening169that exposes a surface150bof the chip pad150. The surface150bof the chip pad150stands opposite to the semiconductor substrate110(e.g., the surface150bof the chip pad150does not face the semiconductor substrate110). The passivation pattern160extends onto and covers an edge of the chip pad150. The passivation pattern160covers a sidewall150cof the chip pad150and a portion of the surface150bof the chip pad150. The portion of the surface150bof the chip pad150that is covered by the passivation pattern160is adjacent to the sidewall150cof the chip pad150. The passivation pattern160may include a silicon-containing insulating material such as, for example, silicon oxide, silicon nitride, silicon oxynitride, and/or tetraethyl orthosilicate (TEOS). The passivation pattern160may be a multi-layer pattern.

A capping pattern CP is disposed in the pad opening169and covers the chip pad150. In an exemplary embodiment, the capping pattern CP completely covers the portion of the chip pad150that is exposed through the pad opening169. In an exemplary embodiment, the capping pattern CP completely covers the chip pad150. For example, in an exemplary embodiment, the capping pattern CP completely covers the exposed portion of the chip pad150that is exposed through the pad opening169, and further covers the remaining portion of the chip pad150that is not exposed through the pad opening169(e.g., with the passivation pattern160disposed therebetween). The capping pattern CP further extends onto a sidewall of the pad opening169and onto a surface160bof the passivation pattern160. In an exemplary embodiment, the capping pattern CP fully fills the pad opening169. For example, as illustrated inFIG. 1C, in an exemplary embodiment, the capping pattern CP formed in the pad opening169includes a surface CPb that is disposed at a higher level than the surface160bof the passivation pattern160. The surface CPb of the capping pattern CP and the surface160bof the passivation pattern160stand opposite to the semiconductor substrate110(e.g., the surface CPb of the capping pattern CP and the surface160bof the passivation pattern160do not face the semiconductor substrate110). Alternatively, in an exemplary embodiment, the capping pattern CP partially fills the pad opening169. The capping pattern CP may include metal such as, for example, copper. The capping pattern CP protects the chip pad150from reactive materials including, for example, chlorine ions.

Referring toFIG. 1C, in an exemplary embodiment, a recess159is disposed on the surface150bof the chip pad150in an area that is exposed through the pad opening169. The capping pattern CP is disposed on the surface150bof the chip pad150, and fills the recess159. Alternatively, in an exemplary embodiment, the recess159is not included. For convenience of illustration, the insulation layer121, the integrated devices125, and the internal lines123are only shown inFIGS. 1A and 1B, and are omitted in the other figures.

FIGS. 2A to 2Gillustrate enlarged cross-sectional views of section A ofFIG. 1A, and illustrate a method of fabricating a semiconductor device according to exemplary embodiments of the inventive concept. For convenience of explanation, a further description of elements and processes previously described may be omitted below. The method of fabricating a semiconductor device according to exemplary embodiments will be described with reference toFIG. 1AandFIGS. 2A to 2G.

Referring toFIG. 2A, a semiconductor device100including a semiconductor substrate110, a circuit layer120, and a chip pad150is prepared. The semiconductor substrate110may be, for example, a wafer-level or chip-level substrate. The chip pad150may be formed by, for example, an electroless plating process. A passivation pattern160is formed on the circuit layer120and covers the chip pad150. The passivation pattern160may be formed by a deposition process such as, for example, plasma vapor deposition or high density plasma chemical vapor deposition.

A first resist layer991is formed on the passivation pattern160. The first resist layer991partially exposes the passivation pattern160. The formation of the first resist layer991may include, for example, forming a coating layer of a photoresist material and patterning the coating layer. The patterning of the coating layer may be performed by, for example, exposure and development processes.

Referring toFIG. 2B, a pad opening169is formed in the passivation pattern160and exposes the chip pad150. An etching process using the first resist layer991as an etching mask may be performed on the passivation pattern160to form the pad opening169. The etching process may be, for example, a dry etching process or a wet etching process. In an exemplary embodiment, the pad opening169has a diameter less than that of the chip pad150. In an exemplary embodiment, a width of the pad opening169in a cross-sectional view is less than that of the chip pad150. The pad opening169partially exposes the surface150bof the chip pad150, and an edge of the chip pad150is covered by the passivation pattern160. Thereafter, the first resist layer991is removed.

Referring toFIG. 2C, the semiconductor device100may be inspected for electrical characteristics. The electrical inspection may be, for example, an electrical die sorting (EDS) test. For example, the chip pad150may be contacted with a probe2000to inspect electrical connections and characteristics between the chip pad150and the integrated circuits125(seeFIG. 1B). After the probe2000contacts the chip pad150, in an exemplary embodiment, a recess159is formed on the surface150bof the chip pad150due to contacting with the probe2000. The recess159is described above with reference toFIG. 1C. For convenience of illustration, the recess159is shown inFIGS. 1C and 2C, and is omitted in the other figures.

Impurities may remain on the surface150bof the chip pad150. The impurities may include, for example, compounds produced in processes or residues of the first resist layer991shown inFIGS. 2A and 2B. Cleaning and heat treatment processes may be performed on the chip pad150to remove the impurities. When the heat treatment process is performed at a temperature less than about 100° C., it may be difficult to remove the impurities or the solution used in the cleaning process. Thus, in exemplary embodiments, the heat treatment process may be performed at a temperature ranging from about 100° C. to about 150° C. A solution used in the cleaning process may further be removed during the heat treatment process.

Referring toFIG. 2D, a seed layer180is conformally formed on the passivation pattern160and in the pad opening169. The seed layer180covers the chip pad150exposed through the pad opening169and covers a sidewall of the passivation pattern160exposed through the pad opening169. The seed layer180may include a first seed layer181and a second seed layer182stacked on the first seed layer181. The first seed layer181may include, for example, titanium or titanium tungsten (TiW), and the second seed layer182may include, for example, copper. A deposition process may be used to form the first and second seed layers181and182.

A second resist layer992is formed on the seed layer180. The second resist layer992partially exposes the seed layer180. For example, the second resist layer992may expose the seed layer180in an area in which the seed layer180is disposed over the chip pad150. The formation of the second resist layer992may include, for example, forming a coating layer of a photoresist material and patterning the coating layer. The patterning of the coating layer may be performed, for example, by exposure and development processes. When the second resist layer992is patterned, an unwanted residue of the second resist layer992may remain on the chip pad150and/or in the pad opening169. A removal process may further be performed to remove this unwanted residue from the chip pad150and/or the pad opening169.

Referring toFIG. 2E, a conductive pattern185is formed by, for example, an electroplating process in which the seed layer180is used as an electrode. The conductive pattern185is selectively formed on a portion of the seed layer180that is exposed by the second resist layer992. The conductive pattern185fills the pad opening169. In exemplary embodiments, the conductive pattern185includes the same material as that of the second seed layer182. For example, in an exemplary embodiment in which the second seed layer182includes copper, the conductive pattern185includes copper.

Referring toFIG. 2F, the second resist layer992is removed to expose the seed layer180.

Referring toFIG. 2G, an etching process is performed to remove the portion of the seed layer180that is not covered by the conductive pattern185to form the capping pattern CP. In exemplary embodiments, a first etching process may be performed to remove the second seed layer182and to expose the first seed layer181. The first etching process may be, for example, a wet etching process. The conductive pattern185may be partially removed together with the second seed layer182during the first etching process. The conductive pattern185may have a thickness greater than that of the second seed layer182. After the first etching process, the conductive pattern185may remain and the second seed layer182may also remain on a bottom surface of the conductive pattern185. A second etching process may then be performed to remove the portion of the first seed layer181that is not covered by the conductive pattern185and to expose the passivation pattern160. When the second etching process is performed, the first seed layer181has an etch selectivity with respect to the conductive pattern185. Therefore, after the second etching process, the conductive pattern185and the first seed layer181on the bottom surface of the conductive pattern185are not removed. The capping pattern CP includes the seed layer180and the conductive pattern185stacked on the seed layer180.

In exemplary embodiments, a contact resistance is improved between the chip pad150and the capping pattern CP because the impurities and unwanted residue are removed, as described above with reference toFIGS. 2C and 2D. Through the above-described processes, the semiconductor device100shown inFIGS. 1A to 1Cis fabricated. The semiconductor device100may be fabricated at a wafer level.

For convenience of illustration, the seed layer180and the conductive pattern185are shown inFIGS. 2D, 2E, 2F, and 2G, and are omitted from the other figures. In addition, for convenience of illustration, the semiconductor substrate110and the circuit layer120are omitted inFIGS. 3A to 11Bdescribed below.

A semiconductor package and a method of fabricating the semiconductor package according to exemplary embodiments of the inventive concept will be described hereinafter.

FIGS. 3A to 3Eillustrate cross-sectional views showing a method of fabricating a semiconductor package according to exemplary embodiments of the inventive concept.FIG. 3Fillustrates an enlarged view showing section A′ ofFIG. 3Eaccording to exemplary embodiments of the inventive concept. For convenience of explanation, a further description of elements and processes previously described may be omitted below. In the following description with reference toFIGS. 3A to 11B,FIG. 3Eis used as a reference when referring to a top surface, a bottom surface, an upper portion, and a lower portion.

Referring toFIG. 3A, a semiconductor device100and a molding pattern200are disposed on a carrier substrate900. A carrier adhesive layer910is interposed between the carrier substrate900and the semiconductor device100, and between the carrier substrate900and the molding pattern200. The semiconductor device100includes the capping pattern CP described above. The semiconductor device100may be the semiconductor device100described with reference toFIGS. 1A to 1C, and fabricated as described with reference toFIGS. 2A to 2G. The molding pattern200is formed on the carrier substrate900and covers at least a portion of the semiconductor device100. For example, in an exemplary embodiment, the molding pattern200covers a top surface100aand a side surface of the semiconductor device100. In an exemplary embodiment, the molding pattern200covers the side surface of the semiconductor device100, and exposes the top surface100aof the semiconductor device100. In an exemplary embodiment, the molding pattern200contacts and covers an entirety of the semiconductor device100except for the portion of the semiconductor device100that contacts the carrier substrate900and/or the carrier adhesive layer910. The molding pattern200may include an insulating resin such as, for example, an epoxy molding compound (EMC). The molding pattern200may further include a filler dispersed in the insulating resin. The filler may include, for example, silicon oxide (SiO2). The molding pattern200has a bottom surface200bthat is disposed at substantially the same level as the surface160bof the passivation pattern160. The carrier adhesive layer910and the carrier substrate900are removed to expose the capping pattern CP, a bottom surface of the semiconductor device100, and the bottom surface200bof the molding pattern200. The bottom surface of the semiconductor device100may correspond to the surface160bof the passivation pattern160and a bottom surface of the capping pattern CP.

Referring toFIG. 3B, a first insulation pattern310is formed on the bottom surface of the semiconductor device100and the bottom surface200bof the molding pattern200. The first insulation pattern310may be formed, for example, by a deposition or coating process. In an exemplary embodiment, the first insulation pattern310is in direct contact with the surface160bof the passivation pattern160, the capping pattern CP, and the bottom surface200bof the molding pattern200. In an exemplary embodiment, the chip pad150is not in contact with the first insulation pattern310, and is spaced apart from the first insulation pattern310by the capping pattern CP. The first insulation pattern310may include, for example, a photosensitive polymer. The photosensitive polymer may include, for example, one or more of photosensitive polyimide (PSPI), polybenzoxazole (PBO), phenolic polymer, and benzocyclobutene (BCB) polymer.

The first insulation pattern310is patterned to form a first opening319in the first insulation pattern310. The first opening319exposes the capping pattern CP. The patterning of the first insulation pattern310may be performed, for example, by exposure and development processes. For example, in photolithography, a pattern preformed on a mask is transferred to a layer on a surface by imaging the pattern onto a photoresist which overlies the layer. Exposure processes as referred to herein may refer to such a process. Further, the development process as referred to herein may be, for example, a positive-tone development (PDT) process or a negative-tone development (NTD) process.

Referring toFIG. 3C, a first redistribution pattern315is formed in the first opening319and on the first insulation pattern310. The first redistribution pattern315is coupled to the capping pattern CP. For example, in an exemplary embodiment, the first redistribution pattern315is in direct contact with the capping pattern CP, and is spaced apart from the chip pad150. The first redistribution pattern315includes a via portion and a line portion. The via portion of the first redistribution pattern315is provided in the first opening319, and the line portion of the first redistribution pattern315is disposed on a bottom surface of the first insulation pattern310. The first redistribution pattern315may be configured such that the via portion is connected to the line portion. The first redistribution pattern315may include metal such as, for example, copper. The first redistribution pattern315may be formed by forming a seed pattern in the first opening319and on the first insulation pattern310, and then performing an electroplating process that uses the seed pattern. A resist pattern may further be formed on the seed pattern, and the electroplating process may include selectively forming a metal pattern on the seed pattern exposed by the resist pattern. A removal process may be performed on a portion of the seed pattern exposed by the metal pattern. The seed pattern may include one or more of, for example, copper and titanium. The metal pattern may include, for example, copper. However, the formation of the first redistribution pattern315is not limited thereto, and may be changed according to exemplary embodiments of the inventive concept.

Referring toFIG. 3D, a second insulation pattern320, a second redistribution pattern325, a third insulation pattern330, and a third redistribution pattern335are formed on the first insulation pattern310. In exemplary embodiments, the second insulation pattern320covers the first redistribution pattern315. The second insulation pattern320may be formed, for example, by a deposition or coating process. The second insulation pattern320may include, for example, a photosensitive polymer. Exposure and development processes may be performed such that the second insulation pattern320is patterned to form a second opening329in the second insulation pattern320. The second opening329exposes the first redistribution pattern315.

The second redistribution pattern325is formed in the second opening329and on a bottom surface of the second insulation pattern320, and is coupled to the first redistribution pattern315. The second redistribution pattern325may include a via portion and a line portion. For example, the second redistribution pattern325may be formed by forming a seed pattern in the second opening329and on the bottom surface of the second insulation pattern320, and then performing an electroplating process that uses the seed pattern. The second redistribution pattern325may include, for example, copper.

The third insulation pattern330is formed on the bottom surface of the second insulation pattern320and covers the second redistribution pattern325. The third insulation pattern330may include, for example, a photosensitive polymer. Exposure and development processes may be performed such that the third insulation pattern330is patterned to form a third opening339in the third insulation pattern330. The third opening339exposes the second redistribution pattern325. The third redistribution pattern335is formed in the third opening339, and includes a conductive material such as, for example, copper. In exemplary embodiments, the third redistribution pattern335further extends onto the third insulation pattern330. Through the processes described above, a redistribution layer300may be formed to include the first, second, and third insulation patterns310,320, and330and the first, second, and third redistribution patterns315,325, and335.

The number of the insulation patterns310,320, and330and the number of the redistribution patterns315,325, and335may be variously changed. For example, in exemplary embodiments, the redistribution layer300may further include a fourth redistribution pattern and a fourth insulation pattern that are formed on the third insulation pattern330. In other exemplary embodiments, the redistribution layer300may include neither the third redistribution pattern335nor the third insulation pattern330.

Referring toFIGS. 3E and 3F, in an exemplary embodiment, a terminal pad410and an external terminal400are formed on the third redistribution pattern335exposed by the third insulation pattern330. The terminal pad410is interposed between the external terminal400and the third redistribution pattern335, and is electrically connected to the external terminal400and the third redistribution pattern335. The external terminal400is electrically connected to the chip pad150through the redistribution patterns315,325, and335and the capping pattern CP. In this description, the phrase “electrically connected to the redistribution layer300” means “electrically connected to at least one of the redistribution patterns315,325, and335of the redistribution layer300.” In an exemplary embodiment, when viewed in a plan view, the external terminal400does not overlap the capping pattern CP. For example, in an exemplary embodiment, the external terminal400is not aligned with the capping pattern CP along a first direction D1. The first direction D1is substantially perpendicular to the top surface100aof the semiconductor device100. In an exemplary embodiment, when viewed in a plan view, the external terminal400overlaps the molding pattern200. Since the redistribution patterns315,325, and335are provided, the arrangement of the external terminal400is not limited by the arrangement of the capping pattern CP. The external terminal400may include, for example, one or more of a solder ball, a bump, and a pillar. The external terminal400may include a conductive material such as, for example, metal. Through the processes described above, a semiconductor package10may be fabricated.

As shown inFIG. 3F, in an exemplary embodiment, the capping pattern CP is formed on the chip pad150, the passivation pattern160exposes a portion of the chip pad150, and the capping pattern CP covers the exposed portion of the chip pad150. The first opening319is formed in the first insulation pattern310by, for example, performing exposure and development processes on the first insulation pattern310. The first opening319exposes a portion of the capping pattern CP, and the first redistribution pattern315is formed in the first opening319such that it contacts the exposed portion of the capping pattern CP.

In exemplary embodiments, the redistribution layer300has a thickness less than that of a printed circuit board (PCB). Thus, the size of the semiconductor package10that includes the redistribution layer300may be reduced, and a compact-sized semiconductor package10may be realized.

FIGS. 4A and 4Billustrate cross-sectional views showing a method of fabricating a semiconductor package according to exemplary embodiments of the inventive concept. For convenience of explanation, a further description of elements and processes previously described may be omitted below.

Referring toFIG. 4A, the semiconductor device100is disposed on the carrier substrate900. The semiconductor device100includes the capping pattern CP. A plurality of the semiconductor devices100is disposed on the carrier substrate900. The plurality of semiconductor devices100is adhered to the carrier substrate900via the carrier adhesive layer910. The molding pattern200is disposed on the carrier substrate900and covers the semiconductor devices100. The carrier adhesive layer910and the carrier substrate900are removed to expose the bottom surface200bof the molding pattern200, the surface160bof the passivation pattern160, and the capping pattern CP. The capping pattern CP prevents the chip pad150from being exposed to the outside.

Referring toFIG. 4B, the redistribution layer300is formed on the exposed capping pattern CP, the exposed surface160bof the passivation pattern160, and the exposed bottom surface200bof the molding pattern200. The redistribution layer300includes the insulation patterns310,320, and330and the redistribution patterns315,325, and335. The redistribution layer300may be formed by the same processes as those described above with reference toFIGS. 3B to 3D. In an exemplary embodiment, the redistribution layer300is formed at a panel or wafer level. The terminal pad410and the external terminal400are formed on a bottom surface of the redistribution layer300. The molding pattern200and the redistribution layer300may be diced along a dot-and-dash line, which may result in fabricating a plurality of semiconductor packages10separated from one another. The semiconductor packages10may be fabricated at a chip, panel, or wafer level. For convenience of explanation, the following description refers to a single semiconductor package10. However, it is to be understood that the method of fabricating a semiconductor package as described below is not limited to chip-level fabrication.

FIG. 5illustrates a cross-sectional view showing a semiconductor package according to exemplary embodiments of the inventive concept. For convenience of explanation, a further description of elements and processes previously described may be omitted below.

Referring toFIG. 5, in an exemplary embodiment, a semiconductor package11includes the redistribution layer300and the semiconductor device100. Unlike the semiconductor package10ofFIG. 3E, the semiconductor package11does not include the molding pattern200. The semiconductor device100has a width W1that is about equal to the width W2of the redistribution layer300.

The first insulation pattern310, the first redistribution pattern315, the second insulation pattern320, the second redistribution pattern325, the third insulation pattern330, and the third redistribution pattern335may be sequentially formed on the bottom surface of the semiconductor device100, thereby forming the redistribution layer300. The first insulation pattern310covers the surface160bof the passivation pattern160and the capping pattern CP. The capping pattern CP prevents the first insulation pattern310from contacting the chip pad150. The redistribution layer300may be formed by the same processes as those described above with reference toFIGS. 3B to 3D.

FIGS. 6A to 6Cillustrate cross-sectional views showing a method of fabricating a semiconductor package according to exemplary embodiments of the inventive concept. For convenience of explanation, a further description of elements and processes previously described may be omitted below.

Referring toFIG. 6A, the first insulation pattern310, the first redistribution pattern315, the second insulation pattern320, the second redistribution pattern325, the third insulation pattern330, and the third redistribution pattern335are formed on the carrier substrate900, thereby forming the redistribution layer300. The first insulation pattern310is formed on the carrier substrate900. The carrier adhesive layer910is further interposed between the first insulation pattern310and the carrier substrate900. The first insulation pattern310may include, for example, a photosensitive polymer. In exemplary embodiments, the first insulation pattern310is patterned to form the first opening319in the first insulation pattern310. The patterning of the first insulation pattern310may be performed, for example, by exposure and development processes. The first opening319exposes the carrier adhesive layer910or the carrier substrate900. The first redistribution pattern315is formed in the first opening319and on the first insulation pattern310.

The second insulation pattern320, the second redistribution pattern325, the third insulation pattern330, and the third redistribution pattern335may be formed by the processes described above with reference toFIGS. 3C and 3D. The second insulation pattern320may include, for example, a photosensitive polymer. The second insulation pattern320includes the second opening329that exposes the first redistribution pattern315. The second redistribution pattern325is formed in the second opening329and on the second insulation pattern320, and is electrically connected to the first redistribution pattern315. The third insulation pattern330is formed on the second insulation pattern320and covers the second redistribution pattern325. The third insulation pattern330may include, for example, a photosensitive polymer. The third insulation pattern330includes the third opening339. The third redistribution pattern335is disposed in the third opening339and is electrically connected to the second redistribution pattern325. The third insulation pattern330exposes a portion of the third redistribution pattern335. A first conductive pad345is formed on the exposed portion of the third redistribution pattern335and is electrically connected to the third redistribution pattern335.

Referring toFIG. 6B, the semiconductor device100is disposed on the redistribution layer300, for example, on the third insulation pattern330. The semiconductor device100includes the capping pattern CP, and the capping pattern CP faces the redistribution layer300. In an exemplary embodiment, the capping pattern CP is aligned with the first conductive pad345. A first connector351is formed between the capping pattern CP and the first conductive pad345. In an exemplary embodiment, the first connector351is spaced apart and physically separated from the chip pad150, and is in direct and physical contact with the capping pattern CP. The semiconductor device100is electrically connected to the redistribution patterns315,325, and335via the first connector351. The first connector351may be, for example, a solder ball, bump, or pillar. The molding pattern200is formed on the redistribution layer300and covers the semiconductor device100. In an exemplary embodiment, the molding pattern200further extends into a gap between the semiconductor device100and the third insulation pattern330, thereby encapsulating the first connector351. Alternatively, in an exemplary embodiment, an under-fill pattern may further be formed to fill the gap between the semiconductor device100and the third insulation pattern330. The carrier adhesive layer910and the carrier substrate900are removed to expose the first insulation pattern310and a portion of the first redistribution pattern315.

Referring toFIG. 6C, in an exemplary embodiment, the terminal pad410and the external terminal400are formed on the bottom surface of the redistribution layer300. The terminal pad410is formed between the external terminal400and the exposed portion of the first redistribution pattern315. The external terminal400is formed on the terminal pad410and is electrically connected to the redistribution patterns315,325, and335. Through the processes described above, a semiconductor package12may be fabricated.

Alternatively, in an exemplary embodiment, the molding pattern200is omitted and the semiconductor device100has a width that is substantially the same as the width of the redistribution layer300, as illustrated inFIG. 5.

FIG. 7illustrates a cross-sectional view showing a semiconductor package according to exemplary embodiments of the inventive concept. For convenience of explanation, a further description of elements and processes previously described may be omitted below.

Referring toFIG. 7, in an exemplary embodiment, a semiconductor package13includes a semiconductor chip101in addition to the redistribution layer300, the semiconductor device100, and the molding pattern200. The semiconductor device100may be the semiconductor device100described above with reference toFIGS. 1A to 2G. For example, in the semiconductor device100shown inFIG. 7, the capping pattern CP covers the chip pad150exposed through the pad opening169.

The semiconductor chip101may have a function identical to or different from that of the semiconductor device100. The semiconductor chip101may include, for example, a contact chip pad151and a passivation layer161. The contact chip pad151may be electrically connected to integrated circuits of the semiconductor chip101. The semiconductor chip101does not include the capping pattern CP. In such a configuration, the contact chip pad151is exposed at a bottom surface of the semiconductor chip101.

In an exemplary embodiment, the redistribution layer300, the semiconductor device100, and the molding pattern200may be formed and disposed by the processes described above with reference toFIGS. 3A to 3D. In an exemplary embodiment, the first redistribution pattern315is in direct and physical contact with the contact chip pad151. Alternatively, in an exemplary embodiment, the redistribution layer300may be formed by the processes described above with reference toFIGS. 6A to 6C. In this case, the first connector351(seeFIG. 6C) may be provided in plural, and the plurality of first connectors351may be interposed between the redistribution layer300and the contact chip pad151, and between the redistribution layer300and the capping pattern CP. The contact chip pad151may be directly coupled to one of the first connectors351.

FIG. 8illustrates a plan view showing a semiconductor package according to exemplary embodiments of the inventive concept.FIGS. 9A and 9Cillustrate cross-sectional views taken along line I-II ofFIG. 8, showing a method of fabricating a semiconductor package according to exemplary embodiments of the inventive concept.FIG. 9Billustrates an enlarged view showing section C ofFIG. 9Aaccording to exemplary embodiments of the inventive concept. For convenience of explanation, a further description of elements and processes previously described may be omitted below.

Referring toFIGS. 8, 9A, and 9B, in an exemplary embodiment, a connection substrate500is disposed on the carrier substrate900. The carrier adhesive layer910is further disposed between the connection substrate500and the carrier substrate900. The connection substrate500includes a hole590penetrating through the connection substrate500. For example, in an exemplary embodiment, the hole590is formed in a printed circuit board (PCB), and the printed circuit board having the hole590is used as the connection substrate500. In an exemplary embodiment, the hole590entirely penetrates the connection substrate500. When viewed in a plan view, the hole590may be formed on a central portion of the connection substrate500. The hole590exposes the carrier adhesive layer910or the carrier substrate900. The connection substrate500includes a base layer510and a conductive structure520. The base layer510includes a plurality of stacked base layers510. The plurality of base layers510may include an insulating material. For example, the base layers510may include a carbon material (e.g., graphite or graphene), a ceramic, or a polymer (e.g., nylon, polycarbonate, or polyethylene). The hole590penetrates the base layers510. The conductive structure520is disposed in the base layers510. As illustrated inFIG. 9B, in an exemplary embodiment, the conductive structure520includes a first pad521, a conductive line523, vias524, and a second pad522. The first pad521is disposed on a bottom surface500bof the connection substrate500. The conductive line523is interposed between the base layers510. The vias524penetrate the base layers510and connect to the conductive line523. The second pad522is disposed on a top surface500aof the connection substrate500and coupled to at least one of the vias524. The second pad522is electrically connected to the first pad521through the vias524and the conductive line523. In an exemplary embodiment, the second pad522and the first pad521do not align with each other along the first direction D1. The second pad522and the first pad521may differ from each other in number or arrangement. The conductive structure520may include metal. For example, the conductive structure520may include one or more of copper, aluminum, gold, lead, stainless steel, silver, iron, and an alloy thereof.

As illustrated inFIG. 9A, in an exemplary embodiment, the semiconductor device100is disposed on the carrier substrate900. The semiconductor device100includes the capping pattern CP, as described with reference toFIGS. 1A to 1C. When viewed in a plan view, the semiconductor device100may be disposed on a central portion of the carrier substrate900. The capping pattern CP faces the carrier substrate900. The semiconductor device100is disposed in the hole590of the connection substrate500. The semiconductor device100may be provided before or after the connection substrate500is disposed.

The molding pattern200is formed on the semiconductor device100and the connection substrate500. The molding pattern200may fill a gap between the semiconductor device100and the connection substrate500. In this case, the molding pattern200may affix the semiconductor device100to the connection substrate500. The molding pattern200may include an insulating polymer such as, for example, an epoxy-based polymer. For example, the molding pattern200may include an adhesive insulation film such as, for example, an Ajinomoto Build-up Film (ABF). The molding pattern200may be formed by attaching an adhesive insulation film onto the connection substrate500and the semiconductor device100.

The carrier adhesive layer910and the carrier substrate900are removed to expose the capping pattern CP, the passivation pattern160, the bottom surface200bof the molding pattern200, and the bottom surface500bof the connection substrate500.

Referring toFIGS. 8 and 9C, in an exemplary embodiment, the first insulation pattern310, the first redistribution pattern315, the second insulation pattern320, the second redistribution pattern325, the third insulation pattern330, and the third redistribution pattern335are sequentially formed on the capping pattern CP, the passivation pattern160, and the bottom surface200bof the molding pattern200, thereby forming the redistribution layer300. The redistribution layer300may be formed by substantially the same processes as those described above with reference toFIGS. 3B to 3D. The redistribution layer300extends onto the bottom surface500bof the connection substrate500. The first insulation pattern310covers the capping pattern CP, the surface160bof the passivation pattern160, the bottom surface200bof the molding pattern200, and the bottom surface500bof the connection substrate500. In an exemplary embodiment, the first insulation pattern310is in direct and physical contact with the capping pattern CP, the passivation pattern160, the molding pattern200, and the connection substrate500. The first redistribution pattern315may be provided in plural. One of the plurality of first redistribution patterns315may be electrically connected to the capping pattern CP, and another one of the plurality of first redistribution patterns315may be electrically connected to the first pad521. The capping pattern CP is electrically connected to the external terminal400or the first pad521through the redistribution patterns315,325, and335. In exemplary embodiments, the conductive structure520is electrically connected to the external terminal400or the semiconductor device100via the redistribution patterns315,325, and335.

In an exemplary embodiment, an upper hole290is formed in the molding pattern200and exposes the second pad522of the conductive structure520. Through the processes described above, a semiconductor package14may be fabricated.

FIG. 9Dillustrates a cross-sectional view taken along line I-II ofFIG. 8, showing a semiconductor package according to exemplary embodiments of the inventive concept. For convenience of explanation, a further description of elements and processes previously described may be omitted below.

Referring toFIGS. 8 and 9D, in an exemplary embodiment, a semiconductor package15includes an upper redistribution layer600in addition to the redistribution layer300, the semiconductor device100, the connection substrate500, and the molding pattern200. The arrangement of the connection substrate500, the providing of the semiconductor device100, the formation of the redistribution layer300, and the formation of the molding pattern200may be substantially the same as those described above with reference toFIGS. 9A to 9C. In exemplary embodiments, a conductor550is formed in the upper hole290and fills the upper hole290. The conductor550may include, for example, metal.

The upper redistribution layer600is disposed on a top surface of the molding pattern200. The upper redistribution layer600includes a first upper insulation pattern610, a second upper insulation pattern620, a first upper redistribution pattern615, and a second upper redistribution pattern625. The first upper insulation pattern610is disposed on the molding pattern200. The first upper insulation pattern610may include, for example, a photosensitive polymer. The first upper redistribution pattern615is disposed on the first upper insulation pattern610and extends into the first upper insulation pattern610. The first upper redistribution pattern615is coupled to the conductor550. The second upper insulation pattern620is disposed on the first upper insulation pattern610and covers the first upper redistribution pattern615. The second upper insulation pattern620may include, for example, a photosensitive polymer. The second upper redistribution pattern625is disposed in the second upper insulation pattern620. In an exemplary embodiment, the second upper redistribution pattern625may further extend onto a top surface of the second upper insulation pattern620. The first and second upper redistribution patterns615and625may include metal such as, for example, copper. The upper redistribution layer600may be formed by substantially the same processes used to form the redistribution layer300as described above with reference toFIGS. 3B to 3D. The number of the upper insulation patterns610and620and the number of the upper redistribution patterns615and625may be variously changed. A second conductive pad650is formed on the upper redistribution layer600and coupled to the second upper redistribution pattern625. The second conductive pad650is electrically connected to the semiconductor device100or the external terminal400via the upper redistribution patterns615and625and the conductive structure520. The second conductive pad650may include, for example, metal. In an exemplary embodiment, the second conductive pad650does not align with the second pad522along the first direction D1. For example, in an exemplary embodiment, when viewed in a plan view, the second conductive pad650overlaps the semiconductor device100. The arrangement of the second conductive pad650is not restricted by the arrangement of the second pad522.

FIGS. 9E and 9Fillustrate cross-sectional views taken along line I-II ofFIG. 8, showing a method of fabricating a semiconductor package according to exemplary embodiments of the inventive concept. For convenience of explanation, a further description of elements and processes previously described may be omitted below.

Referring toFIG. 9E, in an exemplary embodiment, the carrier substrate900is prepared to include the redistribution layer300. The carrier adhesive layer910is interposed between the carrier substrate900and the redistribution layer300. The redistribution layer300may be fabricated as described with reference toFIGS. 6A and 6B. The first conductive pad345is provided in plural on the redistribution layer300. The semiconductor device100is disposed on the redistribution layer300such that the capping pattern CP faces the redistribution layer300. When viewed in a plan view, the semiconductor device100may be disposed on a central portion of the redistribution layer300. The first connector351is formed between the capping pattern CP and one of the first conductive pads345. The first connector351electrically connects the semiconductor device100to the redistribution patterns315,325, and335. A first under-fill pattern210is formed in a gap between the redistribution layer300and the semiconductor device100, thereby encapsulating the first connector351.

The connection substrate500is disposed on the redistribution layer300. The connection substrate500is described above with reference toFIGS. 8 and 9A. A second connector352is formed between the first pad521and another one of the first conductive pads345, and is coupled to the first conductive pad345and the first pad521. The conductive structure520is electrically connected to the redistribution patterns315,325, and335via the second connector352. The second connector352may include a conductive material, and may include one or more of a solder ball, a bump, and a pillar. A second under-fill pattern220is formed in a gap between the redistribution layer300and the connection substrate500, thereby encapsulating the second connector352.

In an exemplary embodiment, the molding pattern200is formed on the semiconductor device100and the connection substrate500, and fills a gap between the semiconductor device100and the connection substrate500. Alternatively, in an exemplary embodiment, the first under-fill pattern210is not formed, and the molding pattern200further extends into a gap between the redistribution layer300and the semiconductor device100. In an exemplary embodiment, the second under-fill pattern220is not formed, and the molding pattern200further extends into a gap between the redistribution layer300and the connection substrate500. The carrier adhesive layer910and the carrier substrate900are removed to expose the bottom surface of the redistribution layer300. Referring toFIG. 9F, the terminal pad410and the external terminal400are formed on the bottom surface of the redistribution layer300. The terminal pad410is formed on the first redistribution pattern315exposed by the first insulation pattern310. The external terminal400is electrically connected to the semiconductor device100or the conductive structure520via the redistribution patterns315,325, and335. The upper hole290is formed in the molding pattern200and exposes the second pad522of the conductive structure520. Through the processes described above, a semiconductor package16may be fabricated.

In an exemplary embodiment, the upper redistribution layer600illustrated inFIG. 9Dis further formed on the molding pattern200.

FIG. 9Gillustrates a cross-sectional view taken along line I-II ofFIG. 8, showing a semiconductor package according to exemplary embodiments of the inventive concept. For convenience of explanation, a further description of elements and processes previously described may be omitted below.

Referring toFIG. 9G, in an exemplary embodiment, a semiconductor package17includes a first semiconductor package14′ and a second semiconductor package30. The first semiconductor package14′ may be fabricated as illustrated inFIGS. 9A to 9C. For example, the first semiconductor package14′ may include the redistribution layer300, the semiconductor device100, the connection substrate500, and the molding pattern200.

The second semiconductor package30is disposed on the first semiconductor package14′. The second semiconductor package30includes a package substrate710, an upper semiconductor chip720, and an upper molding pattern730. The package substrate710may be a printed circuit board or may include a printed circuit board. Alternatively, the redistribution layer300fabricated as illustrated inFIGS. 3B to 3DorFIG. 6Amay be used as the package substrate710. A metal pad705is disposed on a bottom surface of the package substrate710. The upper semiconductor chip720is disposed on the package substrate710. The upper semiconductor chip720may include, for example, a memory circuit, a logic circuit, or any combination thereof. The upper semiconductor chip720may be electrically connected through the package substrate710to the metal pad705, as indicated by the dotted lines inFIG. 9G. For example, inFIG. 9G, a dotted line schematically indicates an internal conductive line within the package substrate710. The upper molding pattern730is disposed on the package substrate710and covers the upper semiconductor chip720. The upper molding pattern730may include an insulating polymer such as, for example, an epoxy-based polymer.

The second pad522and the metal pad705are electrically connected to each other through a connection terminal750interposed therebetween. The connection terminal750may be, for example, a solder ball, bump, or pillar. In such a configuration, the second semiconductor package30is electrically connected to the semiconductor device100and the external terminal400via the connection terminal750. In exemplary embodiments, since the connection substrate500is provided, the connection terminal750may be freely arranged. For example, in exemplary embodiments, the number and arrangement of the connection terminal750is not restricted by those of the first pad521. As a result, integrated circuits may be freely arranged in the package substrate710.

In another exemplary embodiment, the semiconductor package15described with reference toFIG. 9Dmay be used as the first semiconductor package14′. In this case, the connection terminal750is disposed between the second conductive pad650(seeFIG. 9D) and the metal pad705. Since the upper redistribution layer600is provided, the connection terminal750may be freely arranged. For example, the connection terminal750may be provided in plural, and when viewed in a plan view, at least one of the plurality of connection terminals750may overlap the semiconductor device100. In another exemplary embodiment, the semiconductor package16fabricated as illustrated inFIGS. 9E and 9Fmay be used as the first semiconductor package14′.

FIGS. 10A and 10Billustrate cross-sectional views showing a method of fabricating a semiconductor package according to exemplary embodiments of the inventive concept. For convenience of explanation, a further description of elements and processes previously described may be omitted below.

Referring toFIG. 10A, in an exemplary embodiment, the semiconductor device100is disposed on the carrier substrate900. The capping pattern CP faces the carrier substrate900. The carrier adhesive layer910is disposed between the carrier substrate900and the semiconductor device100. In the exemplary embodiment illustrated inFIG. 10A, the connection substrate500ofFIG. 9Ais not provided, and instead of the connection substrate500, a metal pillar is disposed on the carrier substrate900to form a conductive structure520′. For example, the conductive structure520′ may include the metal pillar. The conductive structure520′ is spaced apart from the semiconductor device100. The molding pattern200is formed on the carrier substrate900and covers the semiconductor device100. The molding pattern200encapsulates a sidewall of the conductive structure520′ and fills a gap between the conductive structure520′ and the semiconductor device100, and exposes a top surface520aof the conductive structure520′. For example, in an exemplary embodiment, the molding pattern200covers an entirety of the sidewall of the conductive structure520′, fills an entirety of the gap between the conductive structure520′ and the semiconductor device100, and exposes the top surface520aof the conductive structure520′.

The carrier adhesive layer910and the carrier substrate900are removed to expose the capping pattern CP, the passivation pattern160, the bottom surface200bof the molding pattern200, and a bottom surface of the conductive structure520′.

Referring toFIG. 10B, in an exemplary embodiment, the first insulation pattern310, the first redistribution pattern315, the second insulation pattern320, the second redistribution pattern325, the third insulation pattern330, and the third redistribution pattern335are formed on the capping pattern CP, the passivation pattern160, the bottom surface200bof the molding pattern200, and the bottom surface of the conductive structure520′ to form the redistribution layer300. The redistribution layer300may be formed by substantially the same processes as those discussed above with reference toFIGS. 3B to 3D. In an exemplary embodiment, the first insulation pattern310is in direct contact with the capping pattern CP, the passivation pattern160, the bottom surface200bof the molding pattern200, and the bottom surface of the conductive structure520′. The first redistribution pattern315may be provided in plural. One of the plurality of first redistribution patterns315is coupled to the capping pattern CP, and another one of the plurality of first redistribution patterns315is coupled to the conductive structure520′. The semiconductor device100is electrically connected to the conductive structure520′ via the redistribution patterns315,325, and335.

A plurality of terminal pads410and a plurality of external terminals400are provided on the bottom surface of the redistribution layer300and electrically connected to the redistribution patterns315,325, and335. For example, one of the plurality of external terminals400is electrically connected to the semiconductor device100via the redistribution patterns315,325, and335, and another one of the plurality of external terminals400is electrically connected to the conductive structure520′ via the redistribution patterns315,325, and335. Through the processes described above, a semiconductor package18may be fabricated.

FIG. 10Cillustrates a cross-sectional view showing a semiconductor package according to exemplary embodiments of the inventive concept. For convenience of explanation, a further description of elements and processes previously described may be omitted below.

Referring toFIG. 10C, in an exemplary embodiment, a semiconductor package19includes the upper redistribution layer600in addition to the redistribution layer300, the semiconductor device100, the molding pattern200, and the conductive structure520′. The redistribution layer300, the semiconductor device100, the molding pattern200, and the conductive structure520′ may be formed by the processes described above with reference toFIGS. 10A and 10B.

The first upper insulation pattern610, the second upper insulation pattern620, the first upper redistribution pattern615, and the second upper redistribution pattern625are formed on the molding pattern200to form the upper redistribution layer600. The formation of the first upper insulation pattern610, the second upper insulation pattern620, the first upper redistribution pattern615, and the second upper redistribution pattern625may be substantially the same as that described above with reference toFIG. 9D. The upper redistribution patterns615and625are coupled to the conductive structure520′. The second conductive pad650is disposed on the upper redistribution layer600. The second conductive pad650is coupled to the conductive structure520′ via the upper redistribution patterns615and625.

FIGS. 10D and 10Eillustrate cross-sectional views showing a method of fabricating a semiconductor package according to exemplary embodiments of the inventive concept. For convenience of explanation, a further description of elements and processes previously described may be omitted below.

Referring toFIG. 10D, in an exemplary embodiment, the carrier substrate900is prepared to include the redistribution layer300. The redistribution layer300may be formed as illustrated inFIG. 6A. The carrier adhesive layer910is disposed between the carrier substrate900and the semiconductor device100.

The semiconductor device100is disposed on the redistribution layer300such that the capping pattern CP faces the redistribution layer300. The first connector351is formed between the capping pattern CP and one of the first conductive pads345. The first connector351electrically connects the semiconductor device100to the redistribution patterns315,325, and335. A first under-fill pattern may further be formed in a gap between the redistribution layer300and the semiconductor device100.

A metal pillar is disposed on the redistribution layer300to form the conductive structure520′. The conductive structure520′ is electrically connected to the redistribution patterns315,325, and335.

The molding pattern200is formed on the redistribution layer300and covers the semiconductor device100. The molding pattern200covers a sidewall of the conductive structure520′, and exposes the top surface520aof the conductive structure520′. The carrier adhesive layer910and the carrier substrate900are removed to expose the bottom surface of the redistribution layer300.

Referring toFIG. 10E, in an exemplary embodiment, a plurality of terminal pads410and a plurality of external terminals400are disposed on the bottom surface of the redistribution layer300, and electrically connected to the redistribution patterns315,325, and335. For example, the external terminals400are electrically connected to the semiconductor device100or the conductive structure520′ via the redistribution patterns315,325, and335. Through the processes described above, a semiconductor package20may be fabricated.

FIG. 10Fillustrates a cross-sectional view showing a semiconductor package according to exemplary embodiments of the inventive concept. For convenience of explanation, a further description of elements and processes previously described may be omitted below.

Referring toFIG. 10F, in an exemplary embodiment, a semiconductor package21includes a first semiconductor package18′ and a second semiconductor package30. The first semiconductor package18′ may be fabricated as illustrated inFIGS. 10A and 10B. For example, the first semiconductor package18′ may include the redistribution layer300, the semiconductor device100, the molding pattern200, and the conductive structure520′.

The second semiconductor package30is disposed on the first semiconductor package18′. The second semiconductor package30may be substantially the same as the second semiconductor package30ofFIG. 9G. For example, the second semiconductor package30may include the package substrate710, the upper semiconductor chip720, and the upper molding pattern730.

The conductive structure520′ and the metal pad705are electrically connected to each other through the connection terminal750interposed therebetween. A third conductive pad560is interposed between the conductive structure520′ and the connection terminal750. The upper semiconductor chip720is electrically connected to the redistribution patterns315,325, and335via the connection terminal750.

Alternatively, in an exemplary embodiment, the semiconductor package19described with reference toFIG. 10Cmay be used as the first semiconductor package18′. The connection terminal750may be formed between the upper redistribution layer600and the package substrate710, and may be coupled to the second conductive pad650(seeFIG. 10C) and the metal pad705. Since the upper redistribution layer600is provided, the connection terminal750may be freely arranged. Alternatively, in an exemplary embodiment, the semiconductor package20fabricated as illustrated inFIGS. 10D and 10Emay be used as the first semiconductor package18′.

FIG. 11Aillustrates a cross-sectional view showing a semiconductor module according to exemplary embodiments of the inventive concept.FIG. 11Billustrates an enlarged view showing section A″ ofFIG. 11Aaccording to exemplary embodiments of the inventive concept. For convenience of explanation, a further description of elements and processes previously described may be omitted below.

Referring toFIGS. 11A and 11B, in an exemplary embodiment, a semiconductor module1includes a module substrate1000, an under-fill layer1200, and a semiconductor package10. The module substrate1000may include a printed circuit board. A module pad1004is disposed on a top surface of the module substrate1000. The semiconductor package10may be the semiconductor package10fabricated as illustrated inFIGS. 3A to 3F. Alternatively, in exemplary embodiments, the module substrate1000may be mounted thereon with the semiconductor package11fabricated as shown inFIG. 5, the semiconductor package12fabricated as shown inFIGS. 6A to 6C, the semiconductor package13ofFIG. 7, the semiconductor package14fabricated as shown inFIGS. 9A to 9C, the semiconductor package15ofFIG. 9D, the semiconductor package16fabricated as shown inFIGS. 9E and 9F, the semiconductor package17ofFIG. 9G, the semiconductor package18fabricated as shown inFIGS. 10A and 10B, the semiconductor package19ofFIG. 10C, the semiconductor package20fabricated as shown inFIGS. 10D and 10E, or the semiconductor package21ofFIG. 10F. Referring toFIG. 11A, the external terminal400is coupled to the module pad1004. The semiconductor package10is electrically connected to the module substrate1000via the external terminal400. The under-fill layer1200is interposed between the module substrate1000and the semiconductor package10, thereby encapsulating the external terminal400. In an exemplary embodiment, the under-fill layer1200is in physical contact with the redistribution layer300.

Referring toFIG. 11B, in an exemplary embodiment, the under-fill layer1200includes an insulating polymer1201and reactive materials1205. The insulating polymer1201may include, for example, an epoxy-based polymer. The reactive materials1205may be present in the insulating polymer1201. The reactive materials1205may include, for example, chlorine ions. Alternatively, the reactive materials1205may include, for example, chemical materials or air.

Referring to a comparative example in which a semiconductor module that does not include the capping pattern CP is supplied with voltage or current, reactive materials in an under-fill layer may flow into a redistribution layer. When the reactive materials contact a chip pad, the chip pad may suffer damage (e.g., corrosion). In contrast, referring again toFIG. 11B, according to exemplary embodiments of the inventive concept, the capping pattern CP covers the portion of the chip pad150that is exposed through the pad opening169. As a result, the reactive materials1205may be prevented from passing through the capping pattern CP, or the amount of the reactive materials1205that are able to pass through the capping pattern CP may be reduced. Therefore, exemplary embodiments of the inventive concept prevent or reduce damage to the chip pad150.

According to exemplary embodiments of the inventive concept, the capping pattern CP does not react with the reactive materials1205, or has an extremely low reactivity to the reactive materials1205. For example, according to exemplary embodiments, reactivity between the capping pattern CP and the reactive materials1205is less than reactivity between the chip pad150and the reactive materials1205. Thus, in exemplary embodiments, the capping pattern CP is not damaged by the reactive materials1205. As a result, reliability and durability of the semiconductor module1according to exemplary embodiments of the inventive concept is improved.

According to exemplary embodiments of the inventive concept, a capping pattern covers the portion of a chip pad exposed through a pad opening. The capping pattern prevents the chip pad from contacting a redistribution layer. Thus, the chip pad may be prevented from being damaged by reactive materials, or the amount of damage to the chip pad as a result of the reactive materials may be reduced. Accordingly, a semiconductor package having improved reliability and durability is provided according to exemplary embodiments of the inventive concept.

In addition, the semiconductor package according to exemplary embodiments of the inventive concept includes the redistribution layer, resulting in a reduction in the size of the semiconductor package (e.g., the semiconductor package may become compact-sized).