Digital regulator in power management

A method and system for controlling a plurality of output voltages.

BACKGROUND

A large number of supply voltages may be required in complex technical systems including, but not limited to, mobile phones, digital cameras, and other computing devices, comprising a plurality of differing functional units. Each individual voltage domain often has to satisfy different technical requirements such as output voltage/current, noise, dynamic behavior, etc. To that end, individual analog voltage regulators may be employed, with each analog voltage regulator being individually designed and set. However, if integrated regulators are involved, the designs are redone whenever there is a technological change. Employing individual analog voltage regulators may lead to long design times, risk for redesigns, high current consumption, and large chip area consumption, all of which may be undesirable. Therefore, it is desired to provide an improved voltage regulator system and method of employing the same.

DETAILED DESCRIPTION

The present disclosure describes a digital voltage regulator multiplex system. Many specific details are set forth in the following description and inFIGS. 1-4to provide a thorough understanding of various implementations. One skilled in the art will understand, however, that the subject matter described herein may have additional implementations, or that the concepts set forth may be practiced without several of the details described in the following description.

The digital voltage regulator multiplex scheme of the present disclosure employs a central digital control module to control a plurality of output voltages that may be used in devices that require a plurality of supply voltages such as mobile phones, digital cameras, and other computing devices. The central digital control module facilitates a digital voltage regulator multiplex scheme having a smaller “footprint” (chip area employed) as compared with analog regulators. Further, any redesign of the digital voltage regulator multiplex scheme is facilitated by having a central digital control and thus, the digital voltage regulator multiplex scheme is easily transferable between technologies.

FIG. 1shows an overview of a system100of a plurality of voltage regulators employing a multiplex scheme. System100comprises transistors102a-f, multiplexer104, digital control module106, memory108, reset control110, analog-to-digital converter (ADC)112, digital-to-analog convertor (DAC)114, and switches116. Input to system100are input sources118aand118b, however, system100may comprise any number of input sources depending on the type of application desired. Input sources118aand118bprovide input voltages along paths120aand120bto system100. System100outputs a voltage at output terminals122a-fand maintains a desired constant voltage at output terminals122a-f, described further below. In an implementation, the voltage at output terminals122a-fmay have a tolerance of approximately 1%, and in a further implementation, 10%. However, the tolerance may be higher than 10% depending on the application desired.

In the present example, transistors102are p-channel FETs (field-effect transistors), however, transistors102may be any type of transistor including, but not limited to, n-channel FETs, npn bipolar transistors, and pnp bipolar transistors. Each of transistors102has four terminals associated therewith, terminals124,126,128, and130. As will be apparent to one skilled in the art from the figures, terminal124is the source terminal; terminal126is the drain terminal; terminal128is the gate terminal; and terminal130is the body (or commonly referred to as base, bulk, or substrate) terminal. Transistors102establish the state of output terminals122a-f, described further below. For simplicity of illustration, only terminals for transistor102aare noted onFIG. 1.

Input source118ais connected to terminal124of transistors102a-c; however, input source118amay be connected to terminal124of any subset of transistors102a-f. Further, input source118bis connected to terminal124of transistors102d-f. However, input source118bmay be connected to terminal124of any subset of transistors102a-f. Each of output terminals122a-fof system100are connected to terminals126a-f, respectively. Each of switches116a-fof system100are connected to terminals128a-f, respectively (with terminals128a-fultimately being connected to digital control module106, described further below). Each of terminals130are connected to terminals126.

Multiplexer104is configured to selectively output a signal from transistors102and input sources118determined by digital control module106. More specifically, multiplexer104is connected to terminals126a-fof transistors102and input sources118such that multiplexer104is configured to receive the signal associated with the voltage at terminals126a-fand input sources118. Further, multiplexer104is configured to receive a control signal output via control path132by digital control module106. Based upon the control signal of digital control module106, multiplexer104selects one of the signals associated with the voltage at terminals126a-fand input sources118to output such that digital control module106receives the signal it selected corresponding to the output at terminals126a-fand input sources118via ADC112. In a further implementation, multiple analog-to-digital converters (not shown) may be employed in place of multiplexer104.

Digital Control Module106

Digital control module106is configured to control transistors102such that a desired constant voltage is maintained at output terminals122a-f, described further below. In a further implementation, the voltage at output terminals122a-fis user defined. Digital control module106is connected to terminals128of transistors102via switches116. Further, digital control module106is connected to switches116via DAC114and buffer134. Switches116are configured to receive control signals generated by digital control module106via control path136such that digital control module106controls switches116. More specifically, digital control module106controls switches116such that any desired combination of switches116may be in an “open” state or a “closed” state, as desired. A “closed” state is defined as digital control module106being connected to terminals128while and “open” state is defined as digital control module106not being connected to terminals128.

Digital control module106is further coupled to memory108and control interface138. Memory108stores a desired state of output terminals122a-f, described further below. In a further implementation, memory108stores the value of the voltage at terminals128. Control interface138provides an interface for a user of system100.

Reset control110is configured to receive central reset signal140and debug enable signal142. Central reset signal140is used to reset digital control module106. Often, the generated supply voltage(s) (i.e. input voltages along paths120aand120b) are used in software based systems and debugging of the software may be required. To that end, during debugging of system100, it is not unusual to reset system100. In such cases it may be desired to keep the output voltages (i.e. voltages at output terminals122a-fcontrolled if system100is in reset. Therefore, debug enable signal142is used to disable the reset of digital control module106when a debugger is connected.

Process Model

FIG. 2shows a process200of employing system100. In process200, the example is shown with respect to a single transistor (102a) of transistors102. However, process200may be applied to all of transistors102or any subset (combination) of transistors102.

At step202, a desired voltage V1to be maintained at output terminal122ais determined. Voltage V1may be determined by a load (not shown) connected to output terminal122a. In a further implementation, voltage V1may determined by a user employing control interface138. A magnitude of the desired voltage V1is stored in memory108. In a further implementation, the magnitude of voltage V1is communicated from memory108to digital control module106.

At step204, digital control module106is connected to terminal128aof transistor102aby controlling a state of switch116a. More specifically, digital control module106controls the state of switch116asuch that switch116ais in a “closed” state. In an implementation, digital control module106alters the state of switch116afrom an “open” state to a “closed” state. In a further implementation, digital control module106maintains the state of switch116ain the “closed” state.

At step206, digital control module106establishes a voltage V2of terminal128aof transistors102a. More specifically, digital control module106communicates with terminal128aof transistor102avia DAC114and buffer134to establish a voltage V2of terminal128a. Voltage V2of terminal128ahas a magnitude such that the desired magnitude of voltage V1is established at output terminal122a(also terminal126aof transistor102a). This voltage V2is maintained at terminal128aby means of a gate capacitance, or other capacitance, or any other circuit at terminal128a.

At step208, digital control module106selects the signal output at terminal126a. More specifically, digital control module106outputs a control signal via control path132such that multiplexer104selects the signal output at terminal126awith digital control module106receiving the signal output at terminal126avia ADC112.

At step210, digital control module determines if voltage V2at terminal128aof transistor102ais to be altered. More specifically, digital control module106compares a magnitude of the voltage V1at output terminal122a(also terminal126a) with the desired magnitude of voltage V1in memory108to define a voltage difference. If the voltage difference is greater than a predetermined value, at step212, digital control module106communicates with terminal128aof transistor102avia DAC114and buffer134to establish the voltage V2of terminal128asuch that voltage V1at terminal126ais obtained, analogous to that described above at step206. If there voltage difference is not greater than a predetermined value/percentage, at step214, the process is ended. In a further implementation, process200may be looped iteratively until a desired voltage is obtained at output terminal122a(also terminal126a). In a still a further implementation, process200may be looped iteratively infinitely. In still a further implementation, the signal output at terminals126a-fmay be sampled at predetermined time intervals for comparison with desired magnitudes of voltage V1in memory108to determine if alteration of the voltage at terminals128ais needed.

The above process200may be applied across all or a portion of transistors102in any sequence desired until the desired voltages are obtained at terminals122. More specifically, digital control module106selects a transistor of transistors102to control such that voltages at output terminals122a-fare maintained.

Detailed View of Digital Control Module106

FIG. 3shows a detailed view of digital control module106. Digital control module106comprises proportional-integral derivative (PID) controller300, digital control logic module302, peak detection module304, and τ-estimation module306. For simplicity of illustration, only transistor102ais shown, however, any, the following may be applied to all of transistors102or any subset (combination) of transistors102.

Digital control logic module302is configured to receive the signal output at input source118a(analogous to receiving the signal through multiplexer106as described above with respect toFIG. 1) via ADC310(analogous to receiving via ADC112as described above with respect toFIG. 1). PID controller300is configured to receive the voltage at terminal126aof transistor102a(analogous to receiving the signal through multiplexer106as described above with respect toFIG. 1) via ADC308(analogous to receiving via ADC112as described above with respect toFIG. 1). The load at terminal126aof transistor102ais shown by load314. To that end, parameters corresponding to the signal output at input source118aand input to digital control logic module106are communicated to PID controller300. PID controller300communicates with terminal128aof transistor102avia DAC312(analogous to communicating via DAC114as described above with respect toFIG. 1) to establish a voltage V2of terminal128abased upon the parameters passed from digital control logic module102to PID controller300.

Peak detection module304is configured to receive the voltage at terminal126aof transistors102avia ADC308. Peak detection module304is employed for detection of rising oscillations of the voltage V1at terminal126a(as well as other phenomenon) which may indicate an instable system. When, or at about the time that, a peak is detected, coefficients of PID controller300may be adjusted to better damp the regulation loop described herein and increase system stability if desired. This information is communicated to digital control logic module302.

τ-estimation module306is configured to receive the voltage at terminal126aof transistor102avia ADC308. τ-estimation module306is employed to estimate the rise time of the voltage V1at terminal126aafter initial activation of system100. The rise time may be employed to estimate the load characteristics of system100and initial selection of coefficients of PID controller300. This information is communicated to digital control logic module302.

Peak detection module304and τ-estimation module306enable system100to automatically adapt to different loads at output terminals122a-f. As a result, a single design of system100may be employed in multiple different applications.

Detailed View of Further Implementation of Transistors102

FIG. 4shows a detailed view of a further implementation of transistors102. More specifically, each of transistors102may be implemented as a plurality of transistors400connected in parallel with connected terminals (i.e. the gate, source, drain, and body terminals). The transistors400are switched individually resulting in a change of the effective transistor (i.e. transistors102) width, power density, current carrying capability, etc. of the transistor102. The width of the transistors400, at a given voltage between the gate terminal and the source terminal thereof, have a correlation with the current of transistor400, and thus the switching of transistors400may be employed for regulation of the current in place of altering the voltage between the gate and source terminals as discussed with reference toFIGS. 1 and 2. As a result, less area and power may be required as compared with a DAC-PMOS transistor combination.

Benefits of Employing System100

Employing the aforementioned system100and process200may offer the following benefits: (1) a single control module (digital control module106) for each of transistors102(i.e. the control loop), however, in a further implementation, digital control module106may be implemented as a plurality of digital control modules; (2) individual parameters for each of transistors102(i.e. the control loop); (3) digital design may easily be transferred to new technologies; (4) small chip area in comparison with analog regulators (particularly in nanometer technologies); (5) simple low-power mode by clock reductions, no constant bias current; and (6) reduced costs in chip production tests.

CONCLUSION