RC extraction for single patterning spacer technique

A method includes performing a place and route operation using an electronic design automation tool to generate a preliminary layout for a photomask to be used to form a circuit pattern of a semiconductor device. The place and route operation is constrained by a plurality of single patterning spacer technique (SPST) routing rules. Dummy conductive fill patterns are emulated within the EDA tool using an RC extraction tool to predict locations and sizes of dummy conductive fill patterns to be added to the preliminary layout of the photomask. An RC timing analysis of the circuit pattern is performed within the EDA tool, based on the preliminary layout and the emulated dummy conductive fill patterns.

FIELD

The present subject matter relates to semiconductor fabrication generally, and more specifically to use of electronic design automation tools to fabricate small circuit geometries.

BACKGROUND

In semiconductor fabrication processes, the resolution of a photoresist pattern begins to blur at about 45 nanometer (nm) half pitch. To continue to use fabrication equipment purchased for larger technology nodes, double exposure methods have been developed.

Double exposure involves forming patterns on a single layer of a substrate using two different masks in succession on the same layer of the substrate. A set of first patterns are formed using the first mask. The patterns in the second mask are positioned so as to form second patterns that are interleaved between the first patterns formed by the first mask. As a result, a minimum line spacing in the combined pattern can be reduced while maintaining good resolution. In a method referred to as double dipole lithography (DDL), the patterns to be formed on the layer are decomposed and formed on a first mask having only horizontal lines, and on a second mask having only vertical lines. The first and second masks are said to have 1-dimensional (1-D) patterns, which can be printed with existing lithographic tools.

Another form of double exposure using two masks is referred to as double patterning technology (DPT). Unlike the 1-D approach of DDL, DPT in some cases allows a vertex (angle) to be formed of a vertical segment and a horizontal segment on the same mask. Thus, DPT generally allows for greater reduction in overall IC layout than DDL does. DPT is a layout splitting method analogous to a two coloring problem for layout splitting in graph theory. The layout polygon and critical space are similar to the vertex and edge of the graph respectively. Two adjacent vertices connected with an edge should be assigned different colors. Only two “color types” can be assigned. Each pattern on the layer is assigned a first or second “color”; the patterns of the first color are formed by a first mask, and the patterns of the second color are formed by a second mask. A graph is 2-colorable only if it contains no odd-cycle and loop. Although DPT has advantages, it is computationally intensive.

When two different photomasks are used to pattern the same layer, misalignment of patterns can occur.

DETAILED DESCRIPTION

This description of the exemplary embodiments is intended to be read in connection with the accompanying drawings, which are to be considered part of the entire written description. In the description, relative terms such as “lower,” “upper,” “horizontal,” “vertical,”, “above,” “below,” “up,” “down,” “top” and “bottom” as well as derivative thereof (e.g., “horizontally,” “downwardly,” “upwardly,” etc.) should be construed to refer to the orientation as then described or as shown in the drawing under discussion. These relative terms are for convenience of description and do not require that the apparatus be constructed or operated in a particular orientation.

U.S. patent application Ser. No. 12/907,640, filed Oct. 19, 2010, is incorporated by reference herein in its entirety. A double patterning technology using a Single-Patterning Spacer Technique (SPST) is described therein.

FIG. 1shows a plurality of first patterns (A patterns)26A1and second patterns (B patterns)26B1that are generated by a placing and routing tool, and are desired to be formed on a substrate20. The substrate20may be a semiconductor wafer20. For example, these patterns26A1,26B1may be formed in a back end of line (BEOL) inter-layer dielectric (ILD) layer of an integrated circuit (IC) formed on the wafer20. The patterns26A1,26B1comprise functional portions that are desired, for example, to connect two or more other circuit elements or portions (not shown) to each other. For example, the patterns26A1may connect conductive vias (not shown) that carry signals to or from circuits in the active layers of the substrate or other interconnect layers or to bond pads to be formed over the substrate20.

FIGS. 2A-2Cshow three steps in the performance of an SPST method. In the SPST method, a plurality of tracks, labeled “A tracks” and “B tracks” are laid out in an alternating pattern. In some embodiments, the A tracks may be spaced apart from each other by a minimum distance for forming clear patterns with a single exposure of a single photomask at a given technology node (without using a double patterning technique). Thus, an adjacent A track and B track are closer to each other than the minimum distance. In some embodiments described below, the B tracks are midway between the A tracks, and the spacing between A tracks is uniform.

FIG. 2Ashows a plurality of first patterns (A patterns)42A formed on a photomask38. The A patterns42A are to be patterned onto a substrate20using a photolithographic process. Patterns42A comprise portions42A1,42A2and42A3. The patterns42A1comprise functional portions that are desired to connect two or more other circuit elements or portions (not shown) to each other. Patterns42A1correspond to the desired A patterns26A1shown inFIG. 1. The router also lays out the locations of the B patterns42B1, but in the SPST method, the B patterns are not included in the photomask38.

Additional dummy A patterns42A2,42A3are formed on the mask38, and patterned onto the substrate20. The dummy A patterns42A2,42A3may be inserted by a semiconductor foundry for ease of fabrication. For example, dummy A patterns42A2,42A3may be inserted for purpose of defining the boundaries of spacers50(FIG. 2B) that are subsequently used as a hardmask for forming the B patterns26B1,26B2(FIG. 2C). Some of the dummy A patterns42A3extend along the longitudinal axis of the A patterns42A1. Other dummy patterns42A2extend in a perpendicular direction from the A patterns42A1and/or the dummy A patterns42A3. These perpendicular dummy patterns42A2are also referred to herein as “breaker patterns”. In the particular example ofFIGS. 2A-2C, the dummy patterns42A2,42A3are all provided for defining the hardmask50to form the B patterns.

AlthoughFIGS. 2A-2Cshow the A patterns42A1and dummy A patterns42A2,42A3as distinct regions, all of the patterns shown inFIG. 2Amay be formed on a single photomask38and patterned on a single layer of the semiconductor substrate20in a single exposure and etch operation. Patterns42A1,42A2,42A3in the photomask38are indistinguishable from each other, and all appear as continuous patterns that are subjected to the same processing.

FIG. 2Bshows the layout of the A patterns42A1,42A2,42A3after they are transferred to the substrate20. In some embodiments, the patterns42A1,42A2,42A3are formed by etching trenches in the surface of the ILD material, depositing a conductive material (e.g., copper) in the trenches, and planarizing the surface, using chemical mechanical polishing (CMP). The ILD material can then be etched back, so that at least a portion of the patterns42A1,42A2,42A3extends above the substrate20. A conformal layer of silicon oxide, silicon nitride, or silicon oxynitride is formed over the patterns and the exposed ILD surface. The conformal layer is etched back using an anisotropic etch (e.g., dry etch) to form sidewall spacers50adjacent to the patterns42A1,42A2,42A3. These sidewall spacers50merge to cover the entire region of the substrate, except in the regions52which coincide with the planned locations of the B patterns. The spacers50thus form a hardmask for depositing the B patterns.

FIGS. 2D and 2Eare cross sectional views taken along section lines2D-2D and2E-2E inFIG. 2B.FIG. 2Dshows that the thickness T of the spacers50defines a region52sized to match the desired line width of the B patterns. InFIG. 2D, the distance between the two patterns42A is greater than twice the thickness T of the spacers50, so that an empty region52is formed between the two spacers50. For example, given a distance AA between adjacent tracks, a width WAof the A patterns, and a width WBof the B patterns, the thickness T of the conformal layer may be 0.5*(AA−WB−WA).

FIG. 2Eshows two A patterns formed in a region where no B pattern is to be formed. The distance between the two patterns42A3and42A2inFIG. 2Eis less than or equal to twice the thickness T of the spacers50, so that the spacers merge to form a continuous mass of spacer material between patterns42A3and42A2.

The regions52are then filled with a conductive material (e.g., copper) and the top surface is again planarized to form the B patterns in the locations of the regions52, as shown inFIG. 2C.

FIG. 2Cshows the layout of the conductive material as finally formed on the substrate20, including A patterns26A1,26A2,26A3and B patterns26B1,26B2. Although various portions26A1,26A2,26A3,26B1,26B2of the patterns are given different designations and cross hatching, the A pattern portions26A1,26A2,26A3are all indistinguishable from each other, and the B pattern portions26B1,26B2are indistinguishable from each other.

The patterns26A1,26A2,26A3on the substrate20correspond to the patterns42A1,42A2,42A3in the photomask38as described above, and their description is not repeated for brevity. The B patterns include the desired patterns26B1as shown inFIG. 1, and additional dummy portions26B2. The dummy B portions26B2do not affect the function or connections of the B patterns. The dummy portions26B2may be added to the layout by the foundry to simplify the formation of the hardmask50for forming the B patterns.

In other embodiments (not shown), additional dummy A portions26A2,26A3may be formed to change the shape of the hardmask50, so that the B patterns26B1can be formed without also forming the dummy B patterns26B2. The choice of adding dummy A and/or dummy B patterns can be made by the foundry to simplify the fabrication without affecting function of the IC.

The pattern generator files are then used to produce patterns called photomasks masks by an optical or electron beam pattern generator.

FIG. 3Ais a flow chart of a method of layout and timing analysis for the patterns shown inFIG. 1, using electronic design automation (EDA) tools.

Block300is a place and route tool, and may be a commercially available tool, for example. The tool performs placement, which determines the location of each active element of the IC containing the patterns ofFIG. 1. After placement, the routing step adds wires needed to properly connect the placed components while obeying all design rules for the IC. This placement and routing may be performed by a “fabless” designer, for example.

Block302is the RC extraction block. After the candidate layout ofFIG. 1is complete, it is then checked to ensure that it meets the design requirements before converting the design files into pattern generator files. For example, analysis is performed on the circuit design ofFIG. 1to obtain capacitance and resistance for specific geometric descriptions of conductors in the design, creating an estimation of the capacitance and resistance from a process which is called parasitic resistance and capacitance (RC) extraction. The place and route tool300includes an RC analysis engine having software and hardware that translates a geometric description of conductor and insulator objects, or other shapes described in a candidate IC design file or database, to associated parasitic capacitance values.

Block304performs a timing analysis of the circuitry ofFIG. 1, based on the RC extraction data. The place and route tool300includes a timing analysis engine that evaluates whether the circuitry ofFIG. 1meets timing specifications. If the specifications are not met, then the place and route tool repeats the place and route step, RC extraction302and timing analysis304one or more times, until the timing analysis of the circuitry ofFIG. 1meets specifications.

When all functional and timing requirements are satisfied by the design, the design is complete, and may be turned over for final sign-off check. With increasing frequency, the design ofFIG. 1is then provided to an IC foundry to fabricate the ICs.

Block306performs layout fixing and dummy insertion. This function may be performed by an independent integrated circuit foundry, for example. Each foundry uses its own particular variations of the fabrication technology. For example, the foundry may have its preferred techniques for implementing double patterning and/or optical proximity correction (OPC). Thus, in block306, the foundry may provide the design service or provide the utility to help adding dummy patterns42A2and42A3to the design of photomask38(which subsequently result in addition of the dummy patterns26B2to the IC). One of ordinary skill in the art understands that any dummy patterns (not shown) added to the photomask for OPC purposes are intended to return the final circuit patterns to their as-designed configuration, and do not effect the RC timing analysis (i.e., OPC dummy patterns appear on the mask, but do not substantially appear in the IC). However the addition of dummy patterns42A2,42A3actually results in the formation of additional patterns26A2,26A3on the substrate. Thus, the final patterns26A1,26A2,26A3(including dummies) on the substrate are different from the patterns42A1(without dummies) that were analyzed by the timing analysis block304within the place and route tool300. Similarly, when the B patterns are subsequently formed on the substrate20, they include the dummy B patterns26B2, which are not reflected in the RC extraction and timing analysis performed by the place and route tool300.

Thus, at blocks308and310, the final RC extraction sign off and timing analysis signoff are based on the patterns ofFIG. 2C(including the dummy patterns26A2,26A3and26B2). Because the designer had optimized its design based on its timing analysis of the patterns26A1,26B1ofFIG. 1, the modified layout as shown inFIG. 2Cmay not satisfy all timing requirements. Then further optimization iterations, through Block300, Block306, Block308and Block310are required.

FIG. 3Bis a flow chart of a method for using electronic design automation (EDA) tools to lay out the desired circuitry ofFIG. 2Cin an automated manner that allows the RC extraction engine inside place and route tool to predict/emulate the dummy patterns26A2,26A3and26B2in the design prior to the RC extraction and timing analysis. Further, the layout of the original patterns42A1,42B1by the router is constrained by a set of SPST friendly routing rules, so as to generate a layout from which the RC extraction engine302can predict the RC characteristics of the final circuit as shown inFIG. 2C. This can be accomplished using the designer's existing EDA tool, through a modified set of (SPST friendly) design rules.

The SPST friendly design rules constrain the spacings among the various patterns26A1and26B1in the designer's place and route process, so that the longitudinal dummy pattern segments26A3and26B2can be created by place and route tool directly. In addition, the perpendicular (breaker) dummy patterns26A2can be emulated by RC extraction engine. This will cause the RC extraction to account for the breaker patterns26A2.

Block300′ is the placement and routing block. The place and route operation uses an electronic design automation tool to generate a preliminary layout for a photomask to be used to form a circuit pattern of a semiconductor device, the place and route operation being constrained by a plurality of single patterning spacer technique (SPST) routing rules;

The SPST routing rules cause alternating first tracks and second tracks to be laid out, and first and second patterns to be laid out along the first and second tracks respectively, such that the first patterns are to be included in the photomask, and the second patterns are to be excluded from the photomask but defined between spacers, the spacers to be formed adjacent the circuit pattern formed using the first patterns of the photomask.

Block301includes rule driven layout fixing which can be implemented using a commercially available place and route tool during the designer's place and route optimization, configured to include the SPST friendly design rules described below. The router is given design rules which constrain the allowable spacings among the patterns26A1and26B1to lengths which simplify their computation according to a predetermined rule, and cause the router to create the dummy patterns26A3and26B2for purpose of the RC analysis and timing analysis.

Block303provides SPST aware RC extraction within the place & route tool. The inputs to the RC extraction include the router output based on the SPST friendly design rules. As noted above, these rules cause the router to provide spacings among the patterns26A1and26B1such that the dummy patterns26A3and26B2automatically created by the router before the RC extraction. Also, the length and width of the breaker patterns26A2is predicted.

Block304performs the timing analysis within the designer's EDA tool, based on the RC analysis as modified above, to account for the dummy patterns26A2,26A3and26B2. The designer's EDA tool300′ thus performs a timing analysis tool that evaluates whether the circuitry ofFIG. 2Cmeets timing specifications. If the specifications are not met, then the place and route tool repeats the place and route step300′, RC extraction303and timing analysis304one or more times, until the timing analysis of the circuitry ofFIG. 2Cmeets specifications.

Block307provides rule driven dummy insertion. This insertion of the dummy patterns may be performed after the design is complete. Because the SPST friendly design rules are used, the dummy patterns inserted in block307are substantially the same as those predicted by the RC extraction engine during the RC extraction analysis. As noted above, the design rules to the router constrain the spacings among patterns26A1and26B1. Thus, the actual timing for the A patterns, including the dummy patterns26A2,26A3inserted in the A pattern mask38, and the B patterns, including the dummy patterns26B2, will more closely match the RC timing analysis performed in place & route stage.

Blocks308and310provide the final sign off of RC extraction and timing analysis, respectively, as is provided inFIG. 3A. Because the SPST friendly design rules allow the place and route tool to predict the dummy patterns ofFIG. 2C, the final sign off RC extraction308and final sign off timing Analysis310can provide substantially the same result as the place and route tool's RC extraction303and timing analysis304.

FIG. 4Ais a diagram showing the operation of an SPST routing rule that constrains an end-to-end distance between the first patterns42A1in the layout, as defined to the router. The end-to-end distance can be either: twice a width of the spacers, as shown by distance402; or a distance404greater than or equal to a sum of twice a width SW of the spacers plus a minimum permitted length MDL of dummy conductive fill patterns. In other words, this router design rule prohibits the router from using an end-to-end distance that is less than the combined width of the two spacers that merge, as shown inFIG. 2E. This rule also prohibits end-to-end distances which are greater than the combined width 2*SW of two spacers, but too small to layout an A dummy pattern42A3having the minimum dummy length MDL. Thus, when the RC extraction tool encounters an AA end-to-end distance of 2*SW, it assumes no dummy; and when it encounters a distance greater than or equal to 2*SW+MDL, is assumes there is an A dummy pattern.

FIG. 4Bis a diagram showing an SPST routing rule that constrains an end-to-end distance between the second patterns42B1. Also shown is an SPST routing rule that constrains a minimum length MBL of a perpendicular dummy conductive pattern42A2, where the perpendicular dummy conductive pattern42A2extends perpendicular to and abutting one of the first patterns42A1, for forming a perpendicular spacer50p(FIG. 2B) to define an end of one of the second patterns42B1. The minimum length MBL of breaker dummy conductive pattern42A2is measured in a direction parallel to the one of the first patterns42A1.

As shown inFIG. 4B, the SPST routing rules constrain the end-to-end distance between the second patterns42B1to be either: a distance412which is a sum of twice the width SW of the spacers plus the minimum length MBL of the perpendicular (breaker) dummy conductive pattern42A2; or greater than or equal to a distance414which is a sum of four times a width SW of the spacers plus twice the minimum length MBL of the perpendicular (breaker) dummy conductive pattern plus a minimum permitted length MDL of dummy conductive fill patterns. Thus, when the RC extraction tool encounters a BB end-to-end distance of 2*SW+MBL, it assumes no dummy; and when it encounters a distance greater than or equal to 4*SW+2*MBL+MDL, it assumes there is a B dummy pattern42B2.

FIG. 4Cis a diagram showing an SPST routing rule that constrains an end-to-jog distance between an end of one of the second patterns42B1and a jog42AJ in one of the first patterns to be either: a distance422which is a width SW of the spacers; or a distance424, which is greater than or equal to a sum of three times a width SW of the spacers plus the minimum length MBL of the perpendicular dummy conductive pattern plus a minimum permitted length MDL of dummy conductive fill patterns. Thus, when the RC extraction tool encounters an end-to-jog distance of SW, it assumes no dummy; and when it encounters a distance greater than or equal to 3*SW+MBL+MDL, is assumes there is a B dummy pattern.

FIGS. 4D and 4Eshow a method for emulating the perpendicular (breaker) dummy conductive fill patterns42A2using an RC extraction tool to predict locations and sizes of dummy conductive fill patterns to be added to the preliminary layout of the photomask, without actually laying out the breaker patterns42A2within the router. For example, the router provides a layout for the A patterns which includes the desired patterns42A1and the longitudinal A dummy patterns42A2. RC extraction tools include the capability to input etch tables which specify the edge bias of the photolithographic process. The RC extraction tool uses the etch table for simulating edge bias.

FIG. 4Dshows a typical application of the etch tables by the RC extraction tool for a space between two A patterns42A1and two B patterns42B1. The etch table indicates to the RC extraction tool that along portions P1, where the A patterns42A1and B patterns42B1run adjacent to each other, a first etch bias EB1occurs. Meanwhile, along portion P2, where there is no B pattern42B1between the A patterns42A1an, a second etch bias EB2occurs, wherein EB2is greater than EB1.

FIG. 4Eshows graphically how the design rules are configured to input to the RC extraction tool to emulate the perpendicular dummy patterns42A2. As inFIG. 4D, the region is divided into a first portion P3having a B pattern42B1between the A patterns42A1, and a second portion P4having no B pattern42B1between the A patterns42A1. First portion P3has a length that extends beyond the end of the B pattern42B1by the spacer width SW. The second portion P4has a length that is the BB end-to-end distance minus 2*SW. Thus, the portion P4has two regions of length SW above and below it, in which there is no B pattern (spacers are to be formed in these regions). Thus, where two B patterns are separated by an end-to-end distance, breakers are to be generated on both of the adjacent A patterns, extending in towards each other. The breakers each extend in by a perpendicular distance of 0.5*SW. The longitudinal length of the breaker is given by the BB end-to-end distance minus 2*SW. The RC extractor is thus able to predict the configuration and RC value of the breaker for the timing analysis.

When the RC extraction tool receives the inputs as described inFIGS. 4A to 4E, it can readily predict the inclusion of the dummy A and dummy B patterns42A3,42B2, and the perpendicular dummy conductive patterns42A2. The RC extraction tool is thus able to provide more accurate RC extraction output data for performing the timing analysis. This reduces or eliminates errors which would be included in the timing analysis if the RC extraction does not account for the dummy patterns42A2,42A3and42B2.

FIG. 5is a flow chart of a method for layout and patterning.

At step500, the identification of circuit components to be included in the IC layout is received, for example, in the form of a design netlist.

At step502, placing and routing are performed using an EDA tool, to generate a preliminary layout constrained by the above described SPST design rules. The preliminary layout includes the A patterns42A1and B patterns42B1.

A step504, the AA end-to-end spacing is constrained to equal either 2*SW or be greater than or equal to 2*SW+MDL.

At step506, the BB end-to-end spacing is constrained to equal either 2*SW+MBL or be greater than or equal to 4*SW+MDL+2 MBL.

A step508, the BA end-to-jog spacing is constrained to equal either SW or be greater than or equal to 3*SW+MDL+MBL

At step510, the A patterns42A1, and the B patterns42b1are included in a layout.

At step512, the A patterns, and B patterns, are provided to the RC extraction tool.

At step514, the dummy patterns are emulated (predicted) within the place and route EDA tool; and the RC extraction is performed to provide an RC timing analysis of the circuit pattern, based on the preliminary layout42A1,42B1, predicted dummy patterns42A3,42B2(predicted by RC extraction tool) and the perpendicular dummy conductive fill patterns42A2(derived by RC extraction tool based on the special breaker design rule provided).

At step516, timing analysis is performed based on the RC extraction, which accounts for all the patterns42A1,42A2,42A3,42B1, and42B2.

At step518, the photomask is formed, with the A patterns42A1and A dummy patterns42A2and42A3inserted therein.

At step520, the substrate is patterned to form the A patterns and A dummies42A1,42A2and42A3. This may include forming a trench, filling the trench with conductive material, planarizing the substrate by CMP to remove excess conductive material, and etching back part of the ILD to form a step height between the surface of the ILD and the top surface of the conductive material.

At step522, the spacers50are formed abutting the sides of the A patterns42A1,42A2and42A3so as to define regions52between the spacers. This may include applying a conformal coating of silicon oxide, nitride or oxynitride over the ILD and A patterns, and then performing an anisotropic dry etch, to remove the portions of the conformal coating which overlie the A patterns.

At step524, the defined regions52between the spacers50are filled with a conductive material (e.g., copper) to form the second patterns42B1and42B2. The patterns thus formed are more accurately represented by the RC timing analysis, which accommodated all the predicted and emulated dummy patterns.

FIG. 6shows a system100for performing a method described above, having an electronic design automation (EDA) tool110such as “IC COMPILER”™, sold by Synopsis, Inc. of Mountain View, Calif., including a router120such as “ZROUTE”™, also sold by Synopsis. Other EDA tools110may be used, such as the “VIRTUOSO” custom design platform or the Cadence “ENCOUNTER”® digital IC design platform may be used, along with the “VIRTUOSO” chip assembly router120, all sold by Cadence Design Systems, Inc. of San Jose, Calif. The EDA tool110is a special purpose computer formed by retrieving stored program instructions from a computer readable storage medium112and executing the instructions on a general purpose processor.

The EDA tool includes a place and route tool120and an RC extraction tool121. A tangible machine readable storage medium130stores data generated by the place and route tool120. The data represent a preliminary layout for a photomask to be used to form a circuit pattern of a semiconductor device, the preliminary layout being constrained by a plurality of single patterning spacer technique (SPST) routing rules;

The RC extraction tool121is configured to emulate dummy conductive fill patterns42A2,42A3,42B2by predicting locations and sizes of dummy conductive fill patterns to be added to the preliminary layout of the photomask; and perform RC timing analysis of the circuit pattern42A1,42A2,42A3,42B1,42B2, such that the RC timing analysis is performed based on the preliminary layout and the emulated dummy conductive fill patterns.

One or more computer readable storage media130are provided to store input data used by the EDA tool110. The router120is capable of receiving an identification of a plurality of cells to be included in an integrated circuit (IC) layout, including a list132of pairs of cells within the plurality of cells to be connected to each other.

The router may be equipped with a set of default design rules134, which may be used for larger technology nodes (e.g., 90 nm), which do not include any B patterns between the A patterns, where the A distance between A patterns is at least equal to the minimum distance for clear patterning using a single mask and single etch.

In addition, a technology file136includes SPST friendly design rules as described above with respect toFIGS. 4A to 4C, and etch table137as described above with respect toFIGS. 4D and 4E. The SPST routing rules cause alternating first tracks and second tracks to be laid out, and first and second patterns to be laid out along the first and second tracks respectively, such that the first patterns are to be included in the photomask, and the second patterns are to be excluded from the photomask but defined between spacers, the spacers to be formed adjacent the circuit pattern formed using the first patterns of the photomask. Compliance with the SPST routing rules ensures that the layout42A1,42B1generated by the place and route tool120can be predictably modified by predictable additions of dummy patterns42A2,42A3,42B2, to form an SPST compliant photomask for the A pattern. The SPST compliant photomask for the A pattern in turn ensures that the B patterns can be formed by forming the spacers50between the A patterns and filling the region52between the spacers.

The RC extraction tool121is configured to use an etch table for simulating edge bias. The system further comprising a second machine readable storage medium portion storing a first etch table137. The first etch table137includes first data for simulating a first edge bias EB2(FIG. 4D) of the a first portion of one of the first patterns42A1between longitudinal locations of two of the second patterns42B1. The breaker design rule described above enable prediction of a second portion42A2of one of the first patterns between longitudinal locations of two of the second patterns, to emulate the perpendicular dummy patterns42A2.

In the embodiments described above, the design rules predict the configuration and location of the breaker patterns26A2during the routing step. In an alternative embodiment (not shown), the breaker patterns42A2are emulated by inputting an alternative etch table to the RC extract for use in the sections which will include the breaker patterns. For example, in some embodiments, a first etch table is input to the RC extraction tool including first data for simulating a first edge bias of the a first portion of one of the first patterns adjacent one of the second patterns, and a second etch table is input to the RC extraction tool including second data for simulating a second edge bias of a second portion of one of the first patterns not adjacent to any of the second patterns, wherein the first and second data are different from each other.

In some embodiments, a method comprises performing a place and route operation using a place and route electronic design automation tool110to generate a preliminary layout for a photomask38to be used to form a circuit pattern26A of a semiconductor device. The place and route operation is constrained by a plurality of single patterning spacer technique (SPST) routing rules136. Dummy conductive fill patterns are emulated using an RC extraction engine within the place and route EDA tool to predict locations and sizes of dummy conductive fill patterns to be added to the preliminary layout of the photomask. An RC timing analysis of the circuit pattern is performed within the place and route EDA tool, based on the preliminary layout and the emulated dummy conductive fill patterns.

In some embodiments, a system comprises a tangible machine readable storage medium storing data generated by a place and route tool. The data represent a preliminary layout for a photomask to be used to form a circuit pattern of a semiconductor device. The preliminary layout is constrained by a plurality of single patterning spacer technique (SPST) routing rules. An RC extraction engine within the place and route EDA tool is configured to: emulate dummy conductive fill patterns by predicting locations and sizes of dummy conductive fill patterns to be added to the preliminary layout of the photomask; and perform RC timing analysis of the circuit pattern. The RC timing analysis is performed within the place and route EDA tool based on the preliminary layout and the emulated dummy conductive fill patterns.