Gate cut using selective deposition to prevent oxide loss

Semiconductor devices and methods of forming the same include forming gate stacks across a semiconductor fin, each gate stack having a gate conductor. An interlayer dielectric is formed between the gate stacks. A protective layer is formed on the interlayer dielectric that leaves the gate stacks exposed. The gate conductor of at least one gate stack is etched away. A dielectric liner is formed in a gap left by the etched gate conductor.

BACKGROUND

Technical Field

The present invention generally relates to semiconductor device fabrication and, more particularly, to transistor fabrication using gate-cut processes.

Description of the Related Art

The amount by which a gate structure extends past a last fin in a replacement metal gate fabrication process is an important dimension for logic scaling. Multiple voltage-threshold thickness differences in p-type and n-type field effect transistors (FETs) can limit the work function metal coverage of the end fin and can impede electrostatic control of the channel. In particular, the material of the gate stack accumulates on both the final fin and on other nearby structures, such that the gate stack on the sidewalls of the fin may meet and merge with the gate stack forming on the other structures.

To account for this, an etch of the gate stack is often used after the formation of an inter-layer dielectric to ensure that extraneous gate stack material is removed. This process uses an aggressive anisotropic plasma etch to maintain a vertical sidewall of the nearby structures (e.g., electrical contact structures). However, exposed interlayer dielectric material is attacked by the aggressive etch, which can result in a recess in this material. If the interlayer dielectric is recessed by a significant amount (e.g., greater than about 7 nm), conductive interconnect strapping can be blocked due to residual material blocking the needed etches.

SUMMARY

A method of forming a semiconductor device includes forming gate stacks across a semiconductor fin, each gate stack having a gate conductor. An interlayer dielectric is formed between the gate stacks. A protective layer is formed on the interlayer dielectric that leaves the gate stacks exposed. The gate conductor of at least one gate stack is etched away. A dielectric liner is formed in a gap left by the etched gate conductor.

A method of forming a semiconductor device includes forming gate stacks across a semiconductor fin on a semiconductor substrate, each gate stack having a gate conductor. The semiconductor substrate includes at least one shallow trench isolation region. An interlayer dielectric is formed between the plurality of gate stacks. A self-assembled monolayer is formed on a top surface of each gate stack. A hafnium dioxide layer is formed on the interlayer dielectric, leaving the self-assembled monolayer exposed. The gate conductor of at least one gate stack is etched away over the at least one shallow trench isolation region. The hafnium dioxide layer is removed after etching away the gate conductor. A dielectric liner is formed in a gap left by the etched gate conductor.

A semiconductor device includes a semiconductor fin. A gate stack is formed over the semiconductor fin. Source and drain regions are formed at respective sides of the gate stack. A dielectric liner is formed parallel to the gate stack. An interlayer dielectric is formed between the gate stack and the dielectric liner, wherein a top surface of the interlayer dielectric between the gate stack and the dielectric liner is not recessed.

DETAILED DESCRIPTION

Embodiments of the present invention form a protective layer on an interlayer dielectric that prevents a subsequent gate cut etch from damaging the dielectric material. To selectively apply the protective layer, such that it does not also cover the gate stack, a protective monolayer is formed on the gate stack that prevents the protective layer from adhering.

Referring now toFIG. 1, a top-down view of a step in the fabrication of fin field effect transistors (FETs) is shown. The top-down view identifies two cross sections, A and B, which will be used in subsequent figures to describe the structures shown and subsequent processing steps. A semiconductor substrate102is shown having semiconductor fins104. Shallow trench isolation (STI) areas106are formed between sets of fins. Gate structures108are formed over the fins104. At this stage, it is specifically contemplated that the gate structures108are formed with a full gate stack. Source and drain regions110are formed for at least one of the gate structures108.

The semiconductor substrate102may be a bulk-semiconductor substrate. In one example, the bulk-semiconductor substrate may be a silicon-containing material. Illustrative examples of silicon-containing materials suitable for the bulk-semiconductor substrate include, but are not limited to, silicon, silicon germanium, silicon germanium carbide, silicon carbide, polysilicon, epitaxial silicon, amorphous silicon, and multi-layers thereof. Although silicon is the predominantly used semiconductor material in wafer fabrication, alternative semiconductor materials can be employed, such as, but not limited to, germanium, gallium arsenide, gallium nitride, cadmium telluride, and zinc selenide. Although not depicted in the present figures, the semiconductor substrate102may also be a semiconductor on insulator (SOI) substrate.

The fins104may be formed from the semiconductor substrate using, for example, photolithographic patterning and an anisotropic etch such as, e.g., reactive ion etching (RIE). RIE is a form of plasma etching in which during etching the surface to be etched is placed on a radio-frequency powered electrode. Moreover, during RIE the surface to be etched takes on a potential that accelerates the etching species extracted from plasma toward the surface, in which the chemical etching reaction is taking place in the direction normal to the surface. Other examples of anisotropic etching that can be used at this point of the present invention include ion beam etching, plasma etching or laser ablation.

Alternatively, the fins104can be formed by spacer imaging transfer, which is also known as sidewall image transfer. In sidewall image transfer processes, an initial sacrificial structure is formed at, for example, a smallest feature size that can be created using a given photolithographic technology. Spacer structures are then formed on sidewalls of the sacrificial structures using a conformal deposition process. These spacer structures can be made extremely thin (e.g., about 5 nm). The spacer structures are then used to pattern an underlying semiconductor layer (e.g., the semiconductor substrate104) with an anisotropic etch, creating fins104having dimensions substantially smaller than the smallest feature size.

The STI regions106may be formed by etching a trench in the semiconductor substrate102using, for example, a dry etching process such as RIE or plasma etching. The trenches may optionally be lined with a conventional liner material such as, e.g., an oxide, and then the trench is filled with polysilicon or another like STI dielectric material. The STI dielectric may optionally be densified after deposition.

The source and drain structures110are specifically contemplated as being epitaxially grown, in situ doped semiconductors, but it should be understood that other embodiments are also contemplated that include formation and doping by, e.g., conformal deposition and ion implantation.

Referring now toFIG. 2, a cross-sectional view of a step in the fabrication of fin FETs along cross-section A is shown. In this view, the gate structure108is revealed as being a full gate stack, with a gate dielectric layer202, a work function metal layer204, and a gate conductor206.

It is specifically contemplated that the gate dielectric may be formed from a high-k dielectric material, though other dielectric materials may be used instead. A high-k dielectric material is defined herein as a material having a dielectric constant greater than that of silicon dioxide. Examples of high-k dielectric materials include but are not limited to metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. The gate dielectric material may further include dopants such as lanthanum and aluminum.

The work function metal layer204may be a p-type work function metal layer or an n-type work function metal layer. As used herein, a “p-type work function metal layer” is a metal layer that effectuates a p-type threshold voltage shift. In one embodiment, the work function of the p-type work function metal layer ranges from 4.9 eV to 5.2 eV. As used herein, “threshold voltage” is the lowest attainable gate voltage that will turn on a semiconductor device, e.g., transistor, by making the channel of the device conductive. The term “p-type threshold voltage shift” as used herein means a shift in the Fermi energy of a p-type semiconductor device towards a valence band of silicon in the silicon containing substrate of the p-type semiconductor device. A “valence band” is the highest range of electron energies where electrons are normally present at absolute zero. In one embodiment, a p-type work function metal layer may be formed from titanium nitride, titanium aluminum nitride, ruthenium, platinum, molybdenum, cobalt, and alloys and combinations thereof.

As used herein, an “n-type work function metal layer” is a metal layer that effectuates an n-type threshold voltage shift. “N-type threshold voltage shift” as used herein means a shift in the Fermi energy of an n-type semiconductor device towards a conduction band of silicon in a silicon-containing substrate of the n-type semiconductor device. The “conduction band” is the lowest lying electron energy band of the doped material that is not completely filled with electrons. In one embodiment, the work function of the n-type work function metal layer ranges from 4.1 eV to 4.3 eV. In one embodiment, the n-type work function metal layer is formed from at least one of titanium aluminum, tantalum nitride, titanium nitride, hafnium nitride, hafnium silicon, or combinations thereof. It should be understood that titanium nitride may play the role of an n-type work function metal or a p-type work function metal, depending on the conditions of its deposition.

Referring now toFIG. 3, a cross-sectional view of a step in the fabrication of fin FETs along cross-section B is shown. In this view, the structural relationship of the gate dielectric202and the work function metal layer204is shown, with the work function metal layer204extending over the top of the gate dielectric layer202to seal against the sidewall of the gate spacers302. The gate spacers302may be formed from any appropriate dielectric material such as silicon nitride. An inter-layer dielectric404is filled in around the gate structures and polished down to the level of the gate conductor206using, e.g., a CMP process. The inter-layer dielectric404may be formed from any appropriate dielectric material such as, e.g., silicon dioxide.

CMP is performed using, e.g., a chemical or granular slurry and mechanical force to gradually remove upper layers of the device. The slurry may be formulated to be unable to dissolve, for example, the gate conductor material, resulting in the CMP process's inability to proceed any farther than that layer.

Referring now toFIG. 4, a cross-sectional view of a step in the fabrication of fin FETs along cross-section B is shown. In one embodiment, a self-assembled monolayer402is selectively deposited on the gate conductor206. The self-assembled monolayer402may have any appropriate chemistry where one end of a polymer chain binds to the surface of the gate conductor206(e.g., binds to a metal) without binding to dielectric surfaces of the interlayer dielectric304or the gate spacers302. A single layer of the polymer is thereby formed solely on the gate conductor206, leaving the dielectric surfaces exposed after the unbound polymer material is washed away. A protective layer404is then deposited on the exposed dielectric surfaces but does not bind to the self-assembled monolayer402.

The self-assembled monolayer402may be formed using, e.g., thiols-RSH, RSR′, phophonic acids, R3P, R2P=0, selenium acids, RSeH, RSeSeR′, or alkyl or aryl organic chains. Self-assembled monolayers of organosulfur compounds which bind to metals can be formed from thiols, disulfides, and sulfides and can form monolayers through adsorption from either a liquid or vapor phase. The sulfur-based functionality attaches to the metal, leaving the rest of the compound unbound. The self-assembled monolayer402then includes an organized layer of typically amphiphilic molecules. Generally a head group is connected to an alkyl chain, but could also include some aromatic moiety, in which a tail end can be functionalized (e.g., to specify wetting and interfacial properties). The tail end may in particular be functionalized to prevent growth of the dielectric on the attached metal surface. A carbon chain length of the alkyl chain will, in some embodiments, be adjustable to maximize surface coverage on the metal. Self-assembled monolayers can also be formed from a mixture of thiols, asymmetric disulfides, and assymetric dialkylsulfides.

These substances will bind at one end to the gate conductor206, leaving the unbound end free, resulting in an oriented single layer of the substance. The protective layer404may be formed from, e.g., hafnium dioxide using hafnium oxide precursors such as alkyl amide, alkoxide, diketonate, and chloride. Hafnium dioxide films may be deposited using, e.g., atomic layer deposition (ALD) from fluoride, hafnium tetraiodide, hafnium nitrate, hafnium tetrachloride, tetrakis-ethylmethylamino hafnium, or alkoxide 3-Methyl-3-pentoxide. The hafnium dioxide may be selectively deposited on the exposed dielectric area through plasma based or thermal atomic layer deposition.

Referring now toFIG. 5, a cross-sectional view of a step in the fabrication of fin FETs along cross-section B is shown. The self-assembled monolayer402is ached away with a plasma etch, leaving the gate conductor206exposed. A tri-layer of an organic planarizing layer502, an anti-reflection coating504, and a resist layer506are deposited by any appropriate deposition process including, e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), gas cluster ion beam (GCIB) deposition, or spin-on deposition. It is specifically contemplated that the anti-reflection coating504may be formed from titanium oxide/titanium, which will be etched in the subsequent etch of the gate conductor206and work function metal layer204. The resist layer506is lithographically etched to provide the gate cut pattern, leaving open an area where further etching will take place.

The gate dielectric layer502may be formed by any appropriate process including, e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or gas cluster ion beam (GCIB) deposition. CVD is a deposition process in which a deposited species is formed as a result of chemical reaction between gaseous reactants at greater than room temperature (e.g., from about 25° C. about 900° C.). The solid product of the reaction is deposited on the surface on which a film, coating, or layer of the solid product is to be formed. Variations of CVD processes include, but are not limited to, Atmospheric Pressure CVD (APCVD), Low Pressure CVD (LPCVD), Plasma Enhanced CVD (PECVD), and Metal-Organic CVD (MOCVD) and combinations thereof may also be employed. In alternative embodiments that use PVD, a sputtering apparatus may include direct-current diode systems, radio frequency sputtering, magnetron sputtering, or ionized metal plasma sputtering. In alternative embodiments that use ALD, chemical precursors react with the surface of a material one at a time to deposit a thin film on the surface. In alternative embodiments that use GCIB deposition, a high-pressure gas is allowed to expand in a vacuum, subsequently condensing into clusters. The clusters can be ionized and directed onto a surface, providing a highly anisotropic deposition.

Referring now toFIG. 6, a cross-sectional view of a step in the fabrication of fin FETs along cross-section B is shown. The anti-reflection coating204, organic planarizing layer202, gate conductor206, and work function metal layer204are etched away in the area exposed by the resist layer506using one or more anisotropic etches such as, e.g., RIB. An additional sidewall spacer may be deposited after the etch of the organic planarizing layer502and before etching the gate conductor206to prevent an undercut of the organic planarizing layer502during the subsequent etch(es). Damage to the interlayer dielectric304and the spacers302is prevented by the protective layer404. Experiments have shown that a protective layer as thin as about 1.5 nm is sufficient to protect the dielectric structures during an anisotropic etch of the work function metal layer204and gate conductor206that removes more than about 80 nm of said materials. In some embodiments the gate dielectric202may also be etched using a selective wet or dry etch to strip the gate dielectric202without recessing interlayer dielectric or undercutting other materials more than a few nanometers. In some embodiments, the protective layer404may also be etched using a selective wet or dry etch to strip the protective layer404without recessing interlayer dielectric or undercutting other materials more than a few nanometers.

Referring now toFIG. 7, a cross-sectional view of a step in the fabrication of fin FETs along cross-section B is shown. The remaining resist layer506, anti-reflective coating504, and organic planarizing layer502are removed, along with the protective layer404. A dielectric liner702is deposited in the space left by the etched-away gate conductor206and may be formed from, e.g., silicon nitride. It should be understood that the protective layer404may be removed before or after the formation of the dielectric liner702. A CMP process is used to polish the dielectric liner702down to the level of the interlayer dielectric304. At this stage the top surface of the interlayer dielectric304exhibits no divots or recesses that would result from performing the previous anisotropic etch without having a protective layer404.

At this stage, subsequent processing steps may be performed to recess the remaining gate conductors206and to form a self-aligned contact cap, as well as conductive contacts to the gate conductors206and the source/drain regions110. It should be understood that the formation of an interlayer dielectric304that lacks recesses at the top surface can also be accomplished without a self-assembled monolayer if the protective layer404can be selectively deposited on only the interlayer dielectric304(or on only the interlayer dielectric304and the spacer302) taking advantage of different surface reactivities between materials.

Referring now toFIG. 8, a cross-sectional view of a step in an alternative embodiment of the fabrication of fin FETs along cross-section B is shown. In this embodiment, the gate contact802is recessed down to the level of the work function metal layer204before deposition of the self-aligned contact cap. This reduces the amount of etching needed and reduces the threat of etching through the protective layer404and into the interlayer dielectric304.

The self-assembled monolayer804is deposited across the top surface of the recessed gate conductor802and the work function metal layer204. A thin adhesion layer (not shown) may be formed on the sidewalls of the spacers302so that the self-assembled monolayer804will also accumulate on the sidewalls of the spacers302. The adhesion layer may be formed from, e.g., titanium nitride, before formation of the gate conductor. When the gate conductor is subsequently recessed, a selective etch is used to preserve the adhesion layer. The anisotropic etch of one region's gate recessed gate conductor802and work function metal layer204then proceeds as described above, with the interlayer dielectric304being protected from the etch by the protective layer404. Processing then continues, as described above, with dielectric liners being formed and conductive contacts being put in place.

In a further alternative embodiment, where the protective layer404is deposited only on the interlayer dielectric304, the adhesion layer is omitted from the spacers302so that none of the self-assembled monolayer804accumulates thereon. Any damage to the spacers302is refilled by the subsequent deposition of the dielectric material for the dielectric liner or the self-aligned contact caps.

Referring now toFIG. 9, a method for fabricating fin FETs using a gate cut process is shown. Block902forms the semiconductor fins104on the semiconductor substrate102. As noted above, the fins104may be formed by any appropriate anisotropic etch or by a sidewall image transfer process. The fins104may be formed by removing material from the semiconductor substrate102or may, alternatively, be formed by etching a separate layer on top of the semiconductor substrate and may, therefore, be formed from the same material as the substrate102or from a different material.

Block904forms a gate stack over the fins104. In the present embodiments the gate stack may include a gate dielectric layer202, a work function metal layer204, and a gate conductor204, but it should be understood that other gate stack configurations (e.g., lacking a work function metal layer204or having additional layers) may be used instead. The gate stack may be formed by successive deposition processes using any appropriate conformal deposition process.

Block906forms an interlayer dielectric304around the fins104and the gate stacks, filling such spaces and providing structural support and electrical isolation. It is specifically contemplated that a flowable oxide deposition by, e.g., a spin-on process may be used to form the interlayer dielectric304. At this point, block907may optionally recess the gate conductor206, but it should be understood that in other embodiments the gate conductor206may be recessed after formation of the dielectric liner in block916.

Block908forms a self-assembled monolayer402on the exposed surface(s) of the gate conductor206using any appropriate self-assembling material that selectively binds to the metallic material of the gate conductor206. Block910then forms protective layer404on exposed surfaces of the interlayer dielectric304from, e.g., hafnium dioxide. Because the material of the protective layer404does not bind to the self-assembled monolayer402, the protective layer404is formed solely on the exposed dielectric material (optionally including the top surfaces of spacers302).

Block912then performs the gate cut, using an anisotropic etch to remove the material of the gate conductor206and the work function metal layer204in at least one region. The protective layer404protects the top surface of the interlayer dielectric304from damage during this etch. Block914then removes the protective layer404, revealing a top surface of the interlayer dielectric304with no recessing (though it should be understood that the protective layer404need not be stripped in all embodiments and may instead be left on the interlayer dielectric304to be removed in a later CMP process). Block916forms a dielectric liner in the cut region and optionally over recessed gate conductors802.

Block918then finishes the device. This may include recessing the gate conductors206, forming self-aligned contact caps over the recessed gate conductors, and forming electrical contacts by etching access holes through the interlayer dielectric302and the self-aligned contact caps and depositing a conductive material.

Having described preferred embodiments of a gate cut using selective deposition to prevent oxide loss (which are intended to be illustrative and not limiting), it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments disclosed which are within the scope of the invention as outlined by the appended claims. Having thus described aspects of the invention, with the details and particularity required by the patent laws, what is claimed and desired protected by Letters Patent is set forth in the appended claims.