SILICON CARBIDE SEMICONDUCTOR DEVICE

A p++-type outer peripheral contact region is provided in an edge termination region and surrounds a periphery of an active region in a rectangular shape having rounded corners, in a plan view. The p++-type outer peripheral contact region faces a gate runner on a front surface of a semiconductor substrate via an insulating layer. In the active region, a p++-type region is provided facing a gate pad on the front surface of the semiconductor substrate via the insulating layer. The p++-type outer peripheral contact region and the p++-type region are provided apart from p++-type contact regions that form source contacts with a source electrode. The p++-type contact regions and contact holes in which the source contacts are formed are disposed in a uniform layout spanning an entire area of the active region so that an end side and a center side of the active region have the same layout.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2022-131373, filed on Aug. 19, 2022, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Embodiments of the invention relate to silicon carbide semiconductor device.

2. Description of the Related Art

Conventionally, a metal oxide semiconductor field effect transistor (MOSFET) having an insulated gate with a three-layered structure including a metal, an oxide film, and a semiconductor further has a body diode built into the semiconductor substrate thereof. The body diode of the MOSFET is a parasitic p-intrinsic-n (pin) diode formed by a pn junction (main junction) between a p++-type contact region, a p-type base region, an n−-type drift region, and an n+-type drain region.

A structure of a conventional SiC-MOSFET that uses silicon carbide (SiC) as a semiconductor material is described.FIG.8is a plan view depicting a layout when the conventional silicon carbide semiconductor device is viewed from the front side of a semiconductor substrate thereof.FIGS.9A,9B,10A,10B,11A, and11Bare enlarged plan views of a portion ofFIG.8.FIGS.9A,9B,10A,10B,11A, and11B depict examples of different layouts of p++-type contact regions111.FIGS.9A,10A, and11Aeach depicts a portion (close to a corner of an active region101) in a rectangular frame AA inFIG.8whileFIGS.9B,10B, and11Beach depicts a portion (close to a corner of a p++-type region114) in a rectangular frame BB inFIG.8.

A conventional silicon carbide semiconductor device110depicted inFIGS.8to11Bis a vertical SiC-MOSFET having, in an active region101, a general trench gate structure (not depicted) provided in a semiconductor substrate100, at a front side of the semiconductor substrate100. The trench gate structure is configured by a p-type base region, n+-type source regions, the p++-type contact regions111(refer toFIGS.9A to11B), gate trenches, gate insulating films, and gate electrodes. The body diode is formed by a pn junction (not depicted) between the p++-type contact regions111, the p-type base region, an n−-type drift region, and an n+-type drain region.

The gate trenches extend linearly in a first direction X that is parallel to the front surface of the semiconductor substrate100. Between any adjacent two of the gate trenches (in a mesa portion), the n+-type source regions and the p++-type contact regions111are selectively provided between the front surface of the semiconductor substrate100and the p-type base region and are in contact with the p-type base region. The n+-type source regions and the p++-type contact regions111are in ohmic contact with a source electrode (not depicted) at the front surface of the semiconductor substrate100, via contact holes112of an interlayer insulating film (not depicted).

Each of the p++-type contact regions111is provided centered between a corresponding two of the gate trenches (not depicted) in a second direction Y that is parallel to the front surface of the semiconductor substrate100and orthogonal to the first direction X; the p++-type contact regions111are apart from the gate trenches and scattered in island-like shapes at a predetermined pitch in the first direction X (FIG.9A to11B). A single unit cell (functional unit of a device, portion surrounded by a rectangular frame103inFIGS.9A,9B) of the SiC-MOSFET is configured by the trench structure that includes one of the island-like shaped p++-type contact regions111, and multiple unit cells are disposed adjacent to one another in both the first and second directions X, Y.

The p++-type contact regions111are scattered in island-like shapes, whereby a cell pitch (arrangement interval of the unit cells) may be reduced as compared to an instance in which the p++-type contact regions111extend linearly having substantially the same length as that of the gate trenches in a longitudinal direction of the gate trenches (the first direction X). The p++-type contact regions111, which each has a relatively large surface area as compared to that closer to a center (chip center: center of the semiconductor substrate100) of the active region101, are disposed in a vicinity of an inner periphery of a p++-type outer peripheral contact region113that surrounds a periphery of the active region101and a vicinity of an outer periphery of the p++-type region114directly beneath a gate pad (not depicted), etc.

As an example of a layout of the p++-type contact regions111, in a known structure, at portions104a,104bfacing the p++-type outer peripheral contact region113and/or portions105a,105bfacing the p++-type region114directly beneath the gate pad, the p++-type contact regions111extend to be relatively long in the first direction X (FIGS.9A to11B). Further, a structure is known in which at the portions104b,105bfacing the p++-type outer peripheral contact region113and the p++-type region114in the second direction Y, a width w101of the p++-type contact regions111is relatively wide in the second direction Y (FIGS.9A,10A,11A).

Further, a structure is known in which an end111aof an outermost (closest to a chip end: closest to an end of the semiconductor substrate100) one of the p++-type contact regions111in the second direction Y has, in a plan view of the device, a fan-like shape with a center angle of 90 degrees and an arc-shape along an inner periphery of a corner113a, at the portion104cfacing the corner113aof the p++-type outer peripheral contact region113. Further, a structure is known in which in the portion104c, the p++-type contact regions111adjacent to the fan-like shaped end111aof the outermost one of the p++-type contact regions111extend to be relatively long in the first direction X (FIGS.10A,11A).

The end111aof the outermost one of the p++-type contact regions111in the second direction Y has a width corresponding to a radius R101of the fan-like shape in the plan view and is disposed protruding between the p++-type outer peripheral contact region113and an adjacent one pf the p++-type contact regions111adjacent to the end111aat the inner side thereof in the second direction Y (FIGS.10A,11A).FIG.11Adepicts an instance in which the radius R101of the end111aof the p++-type contact region111is about 10 times larger as compared to that inFIG.10A. The contact holes112have substantially a same size and substantially a same shape in the plan view as that of the p++-type contact regions111, respectively, exposed by the contact holes112(not depicted inFIG.11A).

The p++-type outer peripheral contact region113is provided in an edge termination region102, between the front surface of the semiconductor substrate100and the p-type base region (not depicted) and is in contact with the p-type base region. The p++-type outer peripheral contact region113is electrically connected to the source electrode. The p++-type outer peripheral contact region113, along a border between the active region101and the edge termination region102, surrounds the periphery of the active region101, which has a substantially rectangular shape in the plan view. The corner113aof the p++-type outer peripheral contact region113is curved in an arc shape having a predetermined curvature.

The p++-type region114is provided in the active region101, between the front surface of the semiconductor substrate100and the p-type base region, so as to be in contact with the p-type base region and face the gate pad on the front surface of the semiconductor substrate100, via an insulating layer. The p++-type region114is disposed in a vicinity of the border between the active region101and the edge termination region102and is electrically connected to the source electrode, via the p++-type outer peripheral contact region113. The p++-type region114has, in the plan view, a substantially rectangular shape facing an entire area of the surface of the gate pad, which has a substantially rectangular shape in the plan view.

In the conventional silicon carbide semiconductor device110described above, unlike during normal operation (state of forward bias between a drain and source), reverse bias between the drain and source occurs during deadtime during synchronous rectification of the SiC-MOSFET and energy regeneration to a load side by the SiC-MOSFET. Thus, the pn junction (main junction) between the p++-type contact regions111, the p-type base region, the n−-type drift region, and the n+-type drain region is forward biased, the body diode conducts, and forward current (hole current) flows through the body diode.

As for a conventional SiC-MOSFET, a device has been proposed in which a p++-type outer peripheral contact region is disposed apart from the n+-type source regions in the longitudinal direction of the gate trenches or is disposed apart from the gate trenches in a lateral direction of the gate trenches, whereby current controllability by gate voltage control is enhanced (for example, refer to Japanese Laid-Open Patent Publication No. 2020-004876). In Japanese Laid-Open Patent Publication No. 2020-004876, the p++-type contact regions and the contact holes are scattered a predetermined interval in the longitudinal direction of the gate trenches and the p++-type contact regions are exposed by the contact holes, respectively.

SUMMARY OF THE INVENTION

According to an embodiment of the invention, a silicon carbide semiconductor device includes: a semiconductor substrate containing silicon carbide and having an active region, the semiconductor substrate having a first main surface and a second main surface opposite to each other; a first semiconductor region of a first conductivity type, provided in the semiconductor substrate; a second semiconductor region of a second conductivity type, provided in the active region, between the first main surface of the semiconductor substrate and the first semiconductor region; a plurality of third semiconductor regions of the first conductivity type, selectively provided between the first main surface and the second semiconductor region; a plurality of fourth semiconductor regions of a second conductivity type, selectively provided between the first main surface and the second semiconductor region, an impurity concentration of the plurality of fourth semiconductor regions being higher than an impurity concentration of the second semiconductor region; a plurality of trenches penetrating through the third semiconductor regions and the second semiconductor region and reaching the first semiconductor region; a plurality of gate electrodes, each provided in a corresponding one of the trenches via a gate insulating film; an interlayer insulating film provided at the first main surface, the interlayer insulating film covering the plurality of gate electrodes; a plurality of contact holes penetrating through the interlayer insulating film in a depth direction of the silicon carbide semiconductor device and reaching the first main surface, thereby exposing respective ones of the plurality of fourth semiconductor regions and respective ones of the plurality of third semiconductor regions; a first electrode in contact with the plurality of third semiconductor regions and the plurality of fourth semiconductor regions, via the plurality of contact holes; and a second electrode in contact with the second main surface of the semiconductor substrate. The plurality of fourth semiconductor regions are regularly disposed in in an entire area of the active region. The plurality of contact holes are regularly disposed in the entire area of the active region.

DETAILED DESCRIPTION OF THE INVENTION

First, problems associated with the conventional techniques are discussed. In the conventional silicon carbide semiconductor device110described above (refer toFIGS.8to11B), when the body diode conducts (forward conducts), so-called bipolar degradation (degradation of forward conduction due to the body diode) such as increases in on-voltage Von, increases in forward voltage Vf, etc. occur. A reason for this is that, due to conduction of the body diode, basal plane dislocations (BPDs) grow in the semiconductor substrate100, which contains silicon carbide as a semiconductor material, and the basal plane dislocations become stacking faults (SFs), whereby conduction loss increases.

The semiconductor substrate100is formed by epitaxially growing an epitaxial layer of a predetermined conductivity type on an n+-type starting substrate that constitutes the n+-type drain region and the trench structure is formed in the epitaxial layer, at the surface thereof. Due to conduction of the body diode, forward current of the body diode flows, whereby holes that are injected into the n−-type drift region from the p++-type contact regions111, via the p-type base region, recombine with electrons in the n−-type drift region. BPDs of the semiconductor substrate100receive energy, such as light that is close to the band gap of silicon carbide and emitted due to this recombination, whereby the BPDs grow into stacking faults.

There are many BPDs in the n+-type starting substrate and typically, BPDs of the n+-type starting substrate grow from an interface between the n+-type starting substrate and an n−-type epitaxial layer (the n−-type drift region), to inside the n−-type drift region, along a (0001) plane and at an angle corresponding to an off-angle (normally, about 4 degrees) in a <11-20> direction and become stacking faults. The stacking faults grow to a vicinity of an interface of the pn junction and further expand in a <1-100> direction in the n−-type drift region. Expansion of the stacking faults progresses in an entire area of the active region in which holes are present at a critical concentration 1 x1015/cm3or greater. The stacking faults are resistance components of electron flow and thus, conduction loss increases and bipolar degradation occurs.

Portions where the p++-type contact regions111and the contact holes112are significantly longer relatively, the portions104ato104c,105a,105bthat have wide widths, and the like have low resistance in the semiconductor substrate100, forward current (hole current) of body diode easily flows, and hole current density increases. As a result, hole current density at the interface between the n+-type starting substrate and the n−-type epitaxial layer increases and a threshold of stacking fault growth is exceeded. For example, in the conventional structure (refer toFIGS.8to11B), it was confirmed by the inventor that stacking faults appear, when the current density of the forward current of the body diode is in a range of 200 A/cm2to 400 A/cm2.

A structure of a silicon carbide semiconductor device according to an embodiment is described.FIG.1is a plan view depicting a layout when the silicon carbide semiconductor device according to the embodiment is viewed from a front side of a semiconductor substrate thereof.FIGS.2,3, and4are cross-sectional views along cutting line A-A′, cutting line B-B′, and cutting line C-C′ inFIG.1, respectively.FIG.2depicts a cell structure of a SiC-MOSFET disposed in an active region51.FIG.2depicts four adjacent unit cells (functional units of the device).FIG.3depicts the structure of a portion of an edge termination region52.FIG.4depicts the structure directly beneath a gate pad14(side thereof facing an n+-type drain region1).

FIGS.5A,5B,6A and6Bare enlarged plan views of examples of layouts of a portion ofFIG.1.FIGS.5A,5B,6A and6Bdepict examples of different layouts of p++-type contact regions6.FIGS.5A and6Adepict a portion (vicinity of a corner (vertex portion of a rectangle)51aof the active region51) in a rectangular frame D inFIG.1;FIGS.5B and6Bdepict a portion (vicinity of a corner of a p+-type region44directly beneath a gate pad14) in a rectangular frame E inFIG.1. InFIGS.5A,5B,6A and6B, to clearly depict the layout of the p++-type contact regions6, among portions configuring a trench structure in the active region51, only the p++-type contact regions6and contact holes11aare depicted while the other portions are not depicted.

A silicon carbide semiconductor device10according to the embodiment depicted inFIGS.1to6Bis a vertical SiC-MOSFET having, in a semiconductor substrate (semiconductor chip)30thereof containing silicon carbide, a trench structure in a front side of the semiconductor substrate30, in the active region51. The active region51is a region through which a main current (drift current) flows in a direction orthogonal to a front surface of the semiconductor substrate30, when the silicon carbide semiconductor device10is on. The unit cells each having the same structure of the SiC-MOSFET are disposed adjacent to one another in the active region51. The active region51has, in a plan view of the silicon carbide semiconductor device10, for example, a substantially rectangular shape in which a corner51athat is chamfered and curved into an arc; the active region51is provided in substantially a center (the chip center) of the semiconductor substrate30.

The edge termination region52is a region between the active region51and an end (chip end) of the semiconductor substrate30and surrounds a periphery of the active region51in substantially a rectangular shape. The edge termination region52has a function of mitigating electric field of the front side of the semiconductor substrate30and sustaining a breakdown voltage. The breakdown voltage is a usage voltage limit at which no malfunction or destruction of the silicon carbide semiconductor device10occurs. In the edge termination region52, for example, a general voltage withstanding structure such as a junction termination extension (JTE) structure, a field limiting ring (FLR) configured by a p-type region48, etc. is disposed.

The semiconductor substrate30is formed by sequentially growing epitaxial layers32,33constituting an n−-type drift region (first semiconductor region)2and p-type base regions (second semiconductor regions)4, respectively, on a front surface of an n+-type starting substrate31that contains silicon carbide. The semiconductor substrate30has, as the front surface, a first main surface having the p-type epitaxial layer3and has, as a back surface, a second main surface having the n+-type starting substrate31(back surface of the n+-type starting substrate31). The front surface of the n+-type starting substrate31is, for example, a (0001) plane having an off-angle of about 4 degrees in a <11-20> direction. The n+-type starting substrate31is the n+-type drain region (seventh semiconductor region)1.

The trench structure is configured by the p-type base regions4, n+-type source regions (third semiconductor regions)5, the p++-type contact regions (fourth semiconductor regions)6, gate trenches7, gate insulating films8, and gate electrodes9. The gate trenches7penetrate through the p-type epitaxial layer33in a depth direction Z from the front surface of the semiconductor substrate30, reach the n−-type epitaxial layer (first-conductivity-type epitaxial layer)32, and terminate in later-described n-type JFET regions3. The gate trenches7extend linearly in the first direction X, which is parallel to the front surface of the semiconductor substrate30.

A longitudinal direction (the first direction X) of the gate trenches7is, for example, a <11-20> direction and a lateral direction (the second direction Y, which is parallel to the front surface of the semiconductor substrate30and orthogonal to the first direction X) of the gate trenches7is, for example, a <1-100> direction. The gate electrodes9are provided in the gate trenches7, respectively, via the gate insulating films8, respectively. Between any adjacent two of the gate trenches7(in a mesa portion), the p-type base regions4, n+-type source regions5, and the p++-type contact regions6are each selectively provided between the front surface of the semiconductor substrate30and the n−-type drift region2.

A body diode (parasitic pin diode) is formed by a pn junction (main junction)34between the p++-type contact regions6, the p-type base regions4, later-described p+-type regions21,22, a later-described n-type JFET regions3, a later-described n-type current spreading region3a, the n−-type drift region2, and the n−-type drain region1. The n+-type source regions5and the p++-type contact regions6are diffused regions formed by ion-implantation in the p-type epitaxial layer33. In the p-type epitaxial layer33, a portion thereof excluding the diffused regions formed by ion implantation constitutes the p-type base regions4. The p-type base regions4are provided spanning an entire area between the gate trenches7that are adjacent to one another.

The n+-type source regions5and the p++-type contact regions6are selectively provided between the front surface of the semiconductor substrate30and the p-type base regions4. The n+-type source regions5and the p++-type contact regions6each form, at the front surface of the semiconductor substrate30, an ohmic contact with a source electrode (first electrode)12and has a lower surface (surface facing the n+-type drain region1) in contact with the p-type base regions4. The n+-type source regions5are in contact with the gate insulating films8at sidewalls of the gate trenches7and extend substantially a same length (length in the longitudinal direction) in the first direction X as that of the gate trenches7. The p++-type contact regions6are provided apart from the gate trenches7and adjacent to the n+-type source regions5. The p++-type contact regions6are disposed in a uniform layout spanning an entire area of the active region51.

The p++-type contact regions6being disposed in a uniform layout means the following. The p++-type contact regions6are provided having substantially the same shape in the plan view of the silicon carbide semiconductor device and substantially the same dimensions in all the mesa portions. In particular, each of the p++-type contact regions6, for example, in substantially a center of each of the mesa portions in the second direction Y, has substantially the same width (width in the second direction Y) and substantially the same length in the first direction X and extends linearly (FIGS.5A and5B), or the p++-type contact regions6each has substantially the same dimensions and substantially the same shape in the plan view and are apart from one another (scattered) in island-like shapes at a predetermined pitch in the first direction X (FIGS.6A and6B). In other words, the p++-type contact regions6are provided in a stripe pattern and all terminate at substantially the same position in the first direction X or have substantially the same dimensions and substantially the same shape in the plan view and are provided in dot shapes apart from one another at equal intervals and equal in number in the first direction X (matrix-like pattern).

In the first direction X, a shortest distance x1from the p++-type contact regions6to a later-described p++-type outer peripheral contact region43in the edge termination region52, preferably, may be substantially the same in all the mesa portions. In this instance, all the gate trenches7terminate at substantially the same position in the first direction X. In other words, even when the corner51aof the active region51is curved into an arc-shape, the end of the outermost one (closest to the chip end) of the p++-type contact regions6in the second direction Y does not terminate closer to the chip center in the first direction X than are the ends of the other p++-type contact regions6like in the conventional structure (refer toFIG.9A) but rather is terminated at substantially the same position in the first direction X as the ends of the other p++-type contact regions6.

In the first direction X, even an in instance in which the shortest distance x1from the p++-type contact regions6to the p++-type outer peripheral contact region43is relatively and slightly longer close to the corner51aof the active region51(for example, about 1 μm to 2 μm), the current density of the forward current of the body diode increases about 1% and thus, is acceptable. For example, in an instance in which the p++-type contact regions6extend linearly in the first direction X, provided that the length (length in the first direction X) of the p++-type contact regions6whose ends are positioned close to the corner51aof the active region51is within −5% of the length of the other p++-type contact regions6, an effect of the present embodiment is obtained.

In the first direction X, the shortest distance x1from the p++-type contact regions6to the p++-type outer peripheral contact region43is a distance in the first direction X from the p++-type contact regions6(in an instance in which in each of the mesa portions, the p++-type contact regions6are apart from one another in island-like shapes in the first direction X, an outermost one of the p++-type contact regions6in the first direction X), to the p++-type outer peripheral contact region43. Further, a width of the p++-type contact regions6in the second direction Y is substantially the same for all the p++-type contact regions6and at the end of the outermost one of the p++-type contact regions6in the second direction Y, the layout in which the width locally increases like in the conventional structure (refer toFIGS.10A and11A) is not adopted.

Further, a shortest distance x2, in the first direction X, from the p++-type contact regions6to the p++-type region44is substantially the same in all the mesa portions that face a later-described p++-type region44in the first direction X. The shortest distance x2, in the first direction X, from the p++-type contact regions6to the p++-type region44in the mesa portions that face the p++-type region44in the first direction X is a distance, in the first direction X, from an end of the p++-type contact regions6(in an instance in which in each of the mesa portions, the p++-type contact regions6are apart from one another in island-like shapes in the first direction X, an end of a closest one of the p++-type contact regions6closest to the p++-type region44in the first direction X), that is, the end thereof that faces the p++-type region44, to the p++-type region44.

Further, the outermost ones of the p++-type contact regions6in the second direction Y (i.e., the p++-type contact regions6that face the p++-type outer peripheral contact region43in the second direction Y) and the closest ones of the p++-type contact regions6closest to the p++-type region44in the second direction Y (i.e., the p++-type contact regions6that face the p++-type region44in the second direction Y) are disposed in the same layout as that of the p++-type contact regions6in the center side of the active region51, and a layout in which the width is greater in the second direction Y than the widths of the other p++-type contact regions6and a layout in which the shape in the plan view differs like in the conventional structure (refer toFIGS.10A,10B,11A, and11) are not adopted.

In this manner, even when the corner51aof the active region51curves in an arc-shape and the p++-type region44is partially disposed in the active region51, the p++-type contact regions6are disposed in a uniform layout spanning an entire area of the active region51so that the center side and the end side of the active region51both have substantially the same layout. The p++-type contact regions6of the embodiment are free of portions that are relatively significantly longer and portions that have wide widths like those portions in the conventional structure (corresponds to portions indicated by reference characters104a,104b,104c,105a,105binFIGS.9A to11B). Substantially the same length, substantially the same shape, and substantially the same distance mean, respectively, the same length, the same shape, and the same distance within a range that includes an allowable error due to manufacturing process variation.

One unit cell of the SiC-MOSFET is configured by the trench structure that includes one of the p++-type contact regions6. In particular, in an instance in which the p++-type contact regions6extend linearly in the first direction X, the unit cell (portion surrounded by a two-dot/single-dashed line53inFIGS.5A and5B) of the SiC-MOSFET has a linear shape extending in the first direction X and is disposed in plural adjacent to one another in the second direction Y. In an instance in which the p++-type contact regions6are apart from another in island-like shapes, each unit cell (portion surrounded by the two-dot/single-dashed line53inFIGS.6A and6B) of the SiC-MOSFET is provided in an island-like shape, the unit cells are provided adjacent to one another in the first and second directions X, Y, at the same pitch as that of the p++-type contact regions6.

Further, in the active region51, between the front surface of the semiconductor substrate30and the p-type base regions4, the p++-type region (sixth semiconductor region)44is selectively provided adjacent to the p-type base regions4but apart from the n+-type source regions5and the p++-type contact regions6. The p++-type region44faces the gate pad14on the front surface of the semiconductor substrate100, via an interlayer insulating film11. The p++-type region44is continuous with the later-described p++-type outer peripheral contact region43and is electrically connected to the source electrode12, via the p++-type outer peripheral contact region43. The p++-type region44has substantially the same dimensions and substantially the same shape in the plan view as that of the gate pad14and the p++-type region44faces an entire area of the surface of the gate pad14.

The p++-type region44is diffused region formed in the p-type epitaxial layer33by ion implantation. The p++-type region44, for example, is formed concurrently with the p++-type contact regions6. The unit cells of the SiC-MOSFET may be disposed between the p++-type region44and the later-described p++-type outer peripheral contact region43. The p++-type contact regions6of the unit cells disposed between the p++-type region44and the p++-type outer peripheral contact region43are also disposed in the same layout as that of the p++-type contact regions6of the other unit cells and thus, as described above, the layout of the p++-type contact regions6is uniform spanning an entire area of the active region51.

Between the n−-type drift region2and the p-type base regions4, at deep positions closer to the n+-type drain region1than are bottoms of the gate trenches7, the p+-type regions21,22, and the n-type JFET regions3are selectively provided. The n-type current spreading region3ais provided between the n−-type drift region2and the p+-type regions21,22and the n-type JFET regions3. An impurity concentration of the n-type current spreading region3ais substantially the same as that of the n-type JFET regions3or is an impurity concentration between that of the n-type JFET regions3and that of the n−-type drift region2. The p+-type regions21,22, the n-type JFET regions3, and the n-type current spreading region3aare diffused regions formed in the n−-type epitaxial layer32by ion implantation. The p+-type regions21,22and the n-type JFET regions3may terminate at the same depth positions toward the n+-type drain region1or the n-type current spreading region3amay extend between the n−-type drift region2and the p+-type regions21,22.

The p+-type regions21,22are fixed to the potential of the source electrode12and have a function of mitigating electric field applied to the gate insulating films8by depleting when the SiC-MOSFET (the silicon carbide semiconductor device10) is off (or cause the n-type JFET regions3to deplete, or both). The p+-type regions21,22extend linearly and have substantially the same length as that of the gate trenches7in the first direction X. The p+-type regions21are provided apart from the p-type base regions4and face the bottoms of the gate trenches7in the depth direction Z, respectively. The p+-type regions21may be in contact with the gate insulating films8at the bottoms of the gate trenches7, respectively, or may be apart from the gate trenches7.

The p+-type regions22are provided between the gate trenches7that are adjacent to one another and are in contact with the p-type base regions4but apart from the gate trenches7and the p+-type regions21. The p+-type regions22are provided, respectively, in the mesa portions (between the gate trenches7that are adjacent to one another), at substantially the centers of the mesa portions in the second direction Y, the p+-type regions22face the p++-type contact regions6in the depth direction Z. A width (in the second direction Y) of the p+-type regions22is suitably set according to a width (in the second direction Y) of an n-type junction FET (JFET) region3that is between an adjacent two of the p+-type regions21,22, said width may be at least equal to the width (in the second direction Y) of one of the p++-type contact regions6or may be less than the width (in the second direction Y) of one of the p++-type contact regions6.

In each of the p+-type regions22, a portion thereof facing the n+-type drain region1and a portion thereof facing one of the n+-type source regions5may have substantially the same impurity concentration or each of the p+-type regions22may have a two-layer structure in which the portion facing the n+-type drain region1and the portion facing the n+-type source regions5each has a different impurity concentration. The n-type current spreading region3ais a so-called current spreading layer (CSL) that reduces carrier spreading resistance. The n-type JFET regions3are adjacent to the p+-type regions21,22, have an upper surface (surface facing the n+-type source regions5) that is in contact with the p-type base regions4, and a lower surface (surface facing the n+-type drain region1) that is in contact with the n-type current spreading region3a. The n-type JFET regions3are regions for guiding electron flow in a direction of the lower surface by low resistance.

Further, the n-type JFET regions3reach the gate trenches7in the second direction Y and are in contact with the gate insulating films8. The n-type JFET regions3may be omitted. In an instance in which the n-type JFET regions3are omitted, instead of the n-type JFET regions3, the n-type current spreading region3ais between any adjacent two of the p+-type regions21,22, reaches the p-type base regions4, reaches the gate trenches7in the second direction Y, and is in contact with the gate insulating films8. A portion of the n−-type epitaxial layer32excluding the diffused regions (the p+-type regions21,22, the n-type JFET regions3, and the n-type current spreading region3a) formed by ion implantation constitutes the n−-type drift region2.

The interlayer insulating film11is provided in an entire area of the front surface of the semiconductor substrate30and covers the gate electrodes9. In the interlayer insulating film11, the contact holes11aare provided in a uniform layout spanning an entire are of the active region51. In other words, the contact holes11aare provided having substantially the same shape in the plan view and substantially the same dimensions in all the mesa portions, and the contact holes11aexpose the n+-type source regions5and the p++-type contact regions6. In particular, the contact holes11aare provided in the mesa portions, respectively, extend linearly (in a striped pattern at the surface of the active region51) in the first direction X and have substantially the same width (width in the second direction Y) and substantially the same length in the first direction X. The entire surface of each of the p++-type contact regions6is exposed by the contact hole11athat is in the same respective mesa portion.

The source electrode12is in ohmic contact with the n+-type source regions5and the p++-type contact regions6at the front surface of the semiconductor substrate30, via the contact holes11aof the interlayer insulating film11, and the source electrode12is electrically connected to the n+-type source regions5, the p++-type contact regions6, and the p-type base regions4. The source electrode12covers substantially an entire area of the front surface of the semiconductor substrate30in the active region51. The source electrode12, for example, in the plan view, has a substantially rectangular shape (not depicted) in which a portion is recessed inward (toward the chip center). The source electrode12further serves as a source pad (electrode pad). On the interlayer insulating film11in the active region51, the gate pad14is provided apart from the source electrode12.

The gate pad14is electrically connected to all the gate electrodes9via a later-described gate runner. The gate pad14, for example, has a substantially rectangular shape (not depicted) in the plan view. The gate pad14, for example, in a vicinity of a border between the active region51and the edge termination region52, is provided in a recess where the portion of the source electrode12is recessed and thereby has three sides that face the source electrode12. A drain electrode (second electrode)13is provided in an entire area of the back surface (back surface of the n+-type starting substrate31) of the semiconductor substrate30. The drain electrode13is in ohmic contact with the semiconductor substrate30and is electrically connected to the n+-type drain region1(the n+-type starting substrate31).

In the edge termination region52, between the active region51and the voltage withstanding structure, the p-type base regions4extend between the front surface of the semiconductor substrate30and the n−-type drift region2, from the active region51. Hereinafter, an extended portion of the p-type base regions4extending to the edge termination region52is regarded as a p-type base extension portion42. A p+-type region41is provided between the n−-type drift region2and the p-type base extension portion42. The p+-type region41, for example, is a diffused region formed in the p-type epitaxial layer33concurrently with the p+-type regions22of the active region51. The p+-type region41may extend between the p-type base regions4and the n−-type drift region2directly beneath (closer to the n+-type drain region1than is the gate pad14) the gate pad14.

The p++-type outer peripheral contact region (fifth semiconductor region)43is provided between the front surface of the semiconductor substrate30and the p-type base extension portion42and is in contact with the p-type base extension portion42. The p++-type outer peripheral contact region43, for example, is a diffused region formed in the p-type epitaxial layer33concurrently with the p++-type contact regions6of the active region51. The p++-type outer peripheral contact region43, along the border between the active region51and the edge termination region52, surrounds the periphery of the active region51in substantially a rectangular shape. A corner43aof the p++-type outer peripheral contact region43is curved having an arc shape of a predetermined curvature. The p++-type region44is connected to the p++-type outer peripheral contact region43.

The p++-type outer peripheral contact region43is electrically connected to the source electrode12, via the p-type base extension portion42. The p++-type outer peripheral contact region43has a function of suppressing increases of the potential of a region (p-type outer peripheral region40) directly beneath the gate pad14due to a steep increase in the voltage applied to the drain electrode13. The surface (the front surface of the semiconductor substrate30) of the p++-type outer peripheral contact region43is covered by a field oxide film45. the p-type outer peripheral region40, which is formed by stacking the p++-type outer peripheral contact region43, the p-type base extension portion42, and the p+-type region41, surrounds the periphery of the active region51in substantially a rectangular shape.

In the edge termination region52, the field oxide film45is provided between the front surface of the semiconductor substrate30and the interlayer insulating film11. The field oxide film45may extend between the interlayer insulating film11and the front surface of the semiconductor substrate30in the active region51so as to face an entire area of the gate pad14. Between the active region51and the voltage withstanding structure, a gate polysilicon wiring layer46is provided between the field oxide film45and the interlayer insulating film11. On the gate polysilicon wiring layer46, a gate metal wiring layer47is provided via a contact hole11bof the interlayer insulating film11.

The gate metal wiring layer47is connected to the gate pad14. The gate polysilicon wiring layer46and the gate metal wiring layer47surround the periphery of the active region51and configure the gate runner. The gate electrodes9are connected to the gate polysilicon wiring layer46, at the ends of the gate trenches7in the longitudinal direction. Via the gate polysilicon wiring layer46and the gate metal wiring layer47, all the gate electrodes9are electrically connected to the gate pad14. An entire area of the surface of the gate runner, in the depth direction Z, faces all of the p++-type outer peripheral contact region43, the p-type base extension portion42, and the p+-type region41, via an insulating layer (the field oxide film45and the interlayer insulating film11).

Operation of the silicon carbide semiconductor device10according to the embodiment (SiC-MOSFET) is described. During normal operation, voltage that is positive with respect to the source electrode12is applied to the drain electrode13(forward bias between the drain and source), whereby the pn junction34between the p++-type contact regions6, the p-type base regions4, the p+-type regions21,22, the n-type JFET regions3, the n-type current spreading region3a, the n−-type drift region2, and the n+-type drain region1is reverse biased. In this state, when the voltage applied to the gate electrodes9is less than a gate threshold voltage, the SiC-MOSFET maintains an off-state.

On the other hand, when voltage that is positive with respect to the source electrode12is applied to the drain electrode13and the voltage applied to the gate electrodes9is at least equal to the gate threshold voltage, a channel (n-type inversion layer) is formed in portions of the p-type base regions4, along the sidewalls of the gate trenches. As a result, a main current (drift current) flows from the n+-type drain region1, through the n−-type drift region2, the n-type current spreading region3a, the n-type JFET regions3, and the channel, to the n+-type source regions5, whereby the SiC-MOSFET (the silicon carbide semiconductor device10) turns on.

Further, during deadtime during synchronous rectification of the SiC-MOSFET or when energy is regenerated to the load-side by the SiC-MOSFET, between the drain and source is reversed biased. Thus, the pn junction34between the p++-type contact regions6, the p-type base regions4, the p+-type regions21,22, the n-type JFET regions3, the n-type current spreading region3a, the n−-type drift region2, and the n+-type drain region1is forward biased, the body diode conducts (forward conduction), and the forward current of the body diode flows closer to the chip center than is the p++-type outer peripheral contact region43.

As described above, the p++-type contact regions6and the contact holes11aare disposed in a uniform layout spanning an entire area of the active region51, whereby variation of resistance in the semiconductor substrate30, at the surface of the active region51may be suppressed. As a result, at the surface of the active region51, variation of current density of forward current (hole current) of the body diode may be suppressed and even when the body diode conducts, the hole current density at an interface between the n+-type starting substrate31and the n−-type epitaxial layer32is inhibited from exceeding a threshold for stacking fault (SF) growth.

Thus, as compared to the conventional structure (refer toFIGS.8to11B), stacking fault growth from basal plane dislocations (BPD) of the n+-type starting substrate31during conduction of the body diode may be suppressed. In particular, in the conventional structure, the inventor confirmed that stacking faults appeared when the current density of the forward current of the body diode was in a range of 200 A/cm2to 400 A/cm2whereas in the present embodiment, the inventor confirmed that stacking faults appeared when the current density of the forward current of the body diode increased to about 500 A/cm2.

As described above, according to the embodiment, the p++-type contact regions forming source contacts with the source electrode and the contact holes where the source contacts are formed are disposed in a uniform layout spanning an entire area of the active region so that the end side and the center side of the active region have the same layout. As a result, variation of internal resistance of the semiconductor substrate, at the surface of the active region may be suppressed and variation of the current density of the forward current (hole current) of the body diode, at the surface of the active region may be suppressed. Thus, even when the body diode conducts, increases in the hole current density at the interface between the n+-type starting substrate and the n−-type epitaxial layer may be suppressed, and bipolar degradation may be suppressed.

A relationship between the layout of the p++-type contact regions6and bipolar degradation was verified.FIG.7Ais a table showing layouts of the p++-type contact regions of samples of an experimental example.FIG.7Bis a table showing verification results for the samples of the experimental example. InFIG.7B, the probability of occurrence of a bipolar degradation defect in the samples (semiconductor chips on which vertical SiC-MOSFETs are fabricated) of the experimental example is indicated as a ratio of the number of semiconductor chips in which a bipolar degradation defect occurred (numerator) to the total number of evaluated semiconductor chips (denominator). A semiconductor chip for which the on-voltage Von increases 10% after conduction as compared to before conduction is regarded to have a bipolar degradation defect.

Design conditions for samples 1, 2, 3, 4, 5, 6, and 7 of the experimental example are shown inFIG.7A. The samples 1 to 4 are each a vertical SiC-MOSFET with a trench structure that has the structure of the silicon carbide semiconductor device10according to the embodiment described above (refer toFIGS.1to6) and the p++-type contact regions6are disposed in a uniform layout spanning an entire area of the active region51. In particular, in each of the samples 1 to 3, each of the p++-type contact regions6has the same width and the same length spanning an entire area of the active region51and extends linearly in the first direction X, forming a striped pattern (FIGS.5A and5B). In the sample 4, each of the p++-type contact regions6has the same dimensions and the same shape in the plan view spanning an entire area of the active region51and is disposed apart from the other p++-type contact regions6in an island-like shape (dot shape) (FIGS.6A and6Bs.5).

The samples 1 to 3 are assumed to have cell pitches of 4.5 μm, 5 μm, and 7 μm, respectively, and a ratio of an area of the p++-type contact regions6of one unit cell (hereinafter, amount of the area occupied by the p++-type contact regions6) to an area (surface area) of one unit cell is assumed to be 22.2%, 20%, and 14.2% for the samples 1 to 3, respectively. In the sample 4, the cell pitch is assumed to be 6 μm and the amount of the area occupied by the p++-type contact regions6is assumed to be 16.7%. In the samples 1 to 4, the layout of the p++-type contact regions6is the same in both the end side and the center side of the active region51(in the figure, indicated as “uniform”). In the samples 1 to 3, the contact holes11ahave the same width and the same length and extend linearly in the first direction X, forming a striped pattern.

The samples 5 to 7 are vertical SiC-MOSFETs with a planar gate structure in which the surface areas of the p++-type contact regions, which are disposed apart from one another in island-like shapes (dot shapes) in the active region, are increased locally. In the samples 5 to 7, the cell pitch is assumed to be 10.2 μm and the amount of the area occupied by the p++-type contact regions is assumed to be 13.7%. In particular, in the samples 5 to 7, only an outermost one of the p++-type contact regions in the second direction Y extends linearly in the first direction X and a width in the second direction Y is relatively wide (corresponds to the portion104bof the p++-type contact regions111, facing the p++-type outer peripheral contact region113in the second direction Y, in the conventional structure depicted inFIGS.9A,10A).

In addition, in the samples 6 and 7, the outermost one of the p++-type contact regions in the second direction Y has an end in the second direction Y, that in the plan view has a fan-like shape with a center angle of 90 degrees and an arc-shape along an inner periphery of a corner of the active region, at a portion facing the corner of the active region (corresponds to the portion104cof the p++-type contact regions111, facing the corner113aof the p++-type outer peripheral contact region113, in the conventional structure depicted inFIGS.9A and10A). The end of the outermost one of the p++-type contact regions in the second direction Y has a radius r (corresponds to R101) of 30 μm in the sample 6 and 300 μm in the sample 7.

Results of conducting the body diodes of the samples 1, 2, 3, 4, 5, 6, and 7 of the experimental example to verify the presence/absence of bipolar degradation defects are shown inFIG.7B(results for the sample 4 are not depicted). InFIG.7B, measurements 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, and 13 are set so that the greater is the measurement number (Measurement No.), generally, the larger is the current load and the stricter are the conditions. For the measurements 1, 2, and 3, current densities in the forward direction were 100 A/cm2, 200 A/cm2, and 300 A/cm2in the body diode of the SiC-MOSFET and direct current was passed therethrough for 20 minutes. For the measurement 4, the current density in the forward direction of the body diode of the SiC-MOSFET was 100 A/cm2and direct current was passed therethrough for 60.

For the measurement 5, the current density in the forward direction of the body diode of the SiC-MOSFET was 400 A/cm2and direct current was passed therethrough for 5 minutes. For the measurement 6, the current density in the forward direction of the body diode of the SiC-MOSFETbody diode was 350 A/cm2and direct current was passed therethrough for 20 minutes. For the measurements 7 to 13, the current densities in the forward direction of the body diode of the SiC-MOSFET were 400 A/cm2, 500 A/cm2, 600 A/cm2, 700 A/cm2, 800 A/cm2, 900 A/cm2, and 1000 A/cm2, respectively, and pulsed current was passed therethrough for 20 minutes.

As for the samples of the experimental example, in the samples 1 to 3, the measurements 4 to 13 were performed sequentially. In the samples 1 to 3, the measurements 1 to 3 in which the current load is smaller than that of the measurement 4, were not performed. In the sample 4, the measurement 4 was performed. In the samples 5 and 6, sequentially from the measurement 1 to the measurement 9 in which a bipolar degradation defect occurred in all the evaluated chips (evaluated semiconductor chips) were performed. In the samples 5 and 6, the measurements 10 to 13 for which the current load is greater than that of the measurement 9 were not performed. In the sample 7, sequentially from the measurement 1 to the measurement 7 in which a bipolar degradation defect occurred in all the evaluated chips were performed. In the sample 7, the measurements 8 to 13 for which the current load is greater than that of the measurement 7 were not performed.

InFIG.7B, results for measurement conditions under which the current load to the evaluated chips was progressively increased and the number of defects increased are indicated in bold lettering. From the results of the samples 5 to 7 of the experimental example depicted inFIG.7B, it was confirmed that at a portion facing a corner of the active region, bipolar degradation defects occur at a lower current density (measurement conditions for small measurement numbers), the greater is the relative amount of the surface area of the p++-type contact regions. In the sample 7, in which the outermost one of the p++-type contact regions in the second direction Y, has a fan-like shape in the plan view and the end thereof in the second direction Y has the radius r of 300 μm, which is large, it was confirmed that stacking faults concentrate and are generated from the contact hole that exposes the end of the fan-like shape in the plan view.

On the other hand, from the results of the samples 1 to 3 of the experimental example depicted inFIG.7B, it was confirmed that for the samples 1 to 3, even under the measurement conditions of a large current load, the probability of occurrence of a bipolar degradation defect is small as compared to the samples 5 to 7. In other words, like the silicon carbide semiconductor device10according to the embodiment described above, the p++-type contact regions6and the contact holes11aare disposed in a layout that is uniform spanning an entire area of the active region51so that both the center side and the end side of the active region51have the same layout, whereby increases in the hole current density at an interface between the n+-type starting substrate31and the n−-type epitaxial layer32are suppressed and bipolar degradation may be suppressed.

Further, from the results of the samples 1 to 3 of the experimental example depicted inFIG.7B, it was confirmed that the probability of occurrence of bipolar degradation defects may be reduced the smaller is the amount of the area occupied by the p++-type contact regions6. Therefore, preferably, the amount of the area occupied by the p++-type contact regions6may be small. Further, while not depicted, for the sample 4, results of the measurement 4 confirmed that all the evaluated chips of the sample 4 were free of bipolar degradation defects. Further, as for the sample 4, the presence or absence of bipolar degradation defects is estimated by detecting stacking faults, based on photo luminescence (PL) in the semiconductor substrate30.

In the sample 4, the amount of the area occupied by the p++-type contact regions6is set to be between the amount of the area occupied by the p++-type contact regions6in the sample 2 and the amount of the area occupied by the p++-type contact regions6in the sample 3. Therefore, in an instance in which the measurements 5 to 13 are performed sequentially for the sample 4, as verification results for the sample 4, it is presumed that a probability of occurrence of bipolar degradation defect between the verification results for the sample 2 and the verification results for the sample 3 are obtained. Accordingly, it was confirmed that by disposing the p++-type contact regions6and the contact holes11ain a layout that is uniform spanning an entire area of the active region51, bipolar degradation defects may be suppressed independent of the pattern of the layout.

In the foregoing, the present invention may be variously modified, for example, in the embodiments described above, dimensions, impurity concentrations, etc. of regions, the cell pitch, etc. may be suitably set according to necessary specifications. For example, the cell pitch and the amount of the area occupied by the p++-type contact regions of the samples 1 to 4 of the experimental example correspond to the silicon carbide semiconductor device according to the embodiment (vertical SiC-MOSFET with a trench structure) described above are one example and the cell pitch may be about 5.2 μm and the amount of the area occupied by the p++-type contact regions may be about 19.2%.

Further, even in an instance in which an electrode pad other than the gate pad is provided in the active region, the p++-type regions are disposed directly beneath the electrode pad, similarly as with the gate pad. Further, the positional relationship between the p++-type regions directly beneath the electrode pad and the p++-type contact regions of SiC-MOSFET in the first and second directions is set to be the same as the positional relationship between the p++-type regions directly beneath the gate pad and the p++-type contact regions of the SiC-MOSFET in the first and second directions.

According to the invention described above, variation of resistance in the semiconductor substrate at the surface of the active region may be suppressed. As a result, variation of current density of forward current (hole current) of the body diode at the surface of the active region may be suppressed and thus, even when the body diode conducts, increases in the hole current density in the semiconductor substrate may be suppressed.

The silicon carbide semiconductor device according to the present invention achieves an effect in that bipolar degradation may be suppressed.

As described, the silicon carbide semiconductor device according to the present invention is useful for power semiconductor devices used in power converting equipment, power source devices of various types of industrial machines, etc.