Semiconductor device package and method of manufacturing the same

The present disclosure provides a semiconductor device package. The semiconductor device package includes a first semiconductor device, a first conductive layer and a second conductive layer. The first semiconductor device has a first conductive pad. The first conductive layer is disposed in direct contact with the first conductive pad. The first conductive layer extends along a direction substantially parallel to a surface of the first conductive pad. The second conductive layer is disposed in direct contact with the first conductive pad and spaced apart from the first conductive layer.

TECHNICAL FIELD

The present disclosure generally relates to a semiconductor device package and a method of manufacturing the same, and to a semiconductor device package having a conductive layer and a method of manufacturing the same.

DESCRIPTION OF THE RELATED ART

A semiconductor device package can have one or more semiconductor devices disposed on a carrier and encapsulated by an encapsulant. In order to improve performance of the semiconductor device package, some semiconductor devices can be stacked in the semiconductor device package, which can minimize device footprint on the carrier to ease future miniaturization.

SUMMARY

In one or more embodiments, a semiconductor device package includes a first semiconductor device, a first conductive layer and a second conductive layer. The first semiconductor device has a first conductive pad. The first conductive layer is disposed in direct contact with the first conductive pad. The first conductive layer extends along a direction substantially parallel to a surface of the first conductive pad. The second conductive layer is disposed in direct contact with the first conductive pad and spaced apart from the first conductive layer.

In one or more embodiments, a semiconductor device package includes a first semiconductor device, a second semiconductor device and a first conductive layer. The first semiconductor device has a first surface. The second semiconductor device is stacked on the first semiconductor device. The second semiconductor device has a first surface substantially perpendicular to the first surface of the first semiconductor device and a second surface substantially parallel to the first surface of the first semiconductor device. The first conductive layer is disposed in direct contact with the first surface of the first semiconductor device, the first surface of the second semiconductor device, and the second surface of the second semiconductor device.

In one or more embodiments, a method for manufacturing a semiconductor device package includes providing a first semiconductor device. The first semiconductor device has a first conductive pad. The method further includes stacking a second semiconductor device on the first semiconductor device. The method further includes forming an insulation material on the first semiconductor device and the second semiconductor device. The method further includes partially removing the insulation material to form a supporting structure in a corner. The corner is defined by a portion of a surface of the first semiconductor device and a portion of a surface of the second semiconductor device. The method further includes forming a first conductive layer and a second conductive layer both directly contacting the first conductive pad and spaced apart from each other.

DETAILED DESCRIPTION

Embodiments of the present disclosure are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of the disclosure.

FIG. 1illustrates a cross-sectional view of a semiconductor device package100in accordance with some embodiments of the present disclosure. The semiconductor device package100may include a semiconductor device110, a semiconductor device120, a semiconductor device130, a conductive layer210, a conductive layer220, a supporting structure160, a supporting structure170and an encapsulation layer180.

The semiconductor device110may have a surface110a(which may also be referred to as “an upper surface”). The semiconductor device110may have a conductive pad111. The semiconductor device110may be attached to a carrier101through an adhesive layer191. The carrier101may include, for example but not limited thereto, a molding compound, bismaleimide triazine (BT), polyimide (PI), polybenzoxazole (PBO), a solder resist, an Ajinomoto build-up film (ABF), polypropylene (PP), an epoxy-based material, or a combination of two or more thereof. The carrier101may include an interconnection structure, such as a redistribution layer (RDL) or a grounding element. The carrier101may include one or more conductive pads in proximity to, adjacent to, or embedded in and exposed at a surface of the carrier101. The carrier101may include a solder resist (or solder mask) on a surface of the carrier101to fully expose or to expose at least a portion of the conductive pads for electrical connections.

The semiconductor device120may be stacked on the semiconductor device110. The semiconductor device120may be attached to the semiconductor device110through an adhesive layer192. The semiconductor device120may have a surface120s(which may also be referred to as “a lateral surface”) substantially perpendicular to the surface110aof the semiconductor device110. The semiconductor device120may have a surface120a(which may also be referred to as “an upper surface”) substantially parallel to the surface110aof the semiconductor device110. The semiconductor device120may have a conductive pad121.

The semiconductor device130may be stacked on the semiconductor device120. The semiconductor device130may be attached to the semiconductor device120through an adhesive layer193. The semiconductor device130may have a surface130a(which may also be referred to as “an upper surface”) and a surface130s(which may also be referred to as “a lateral surface”) substantially perpendicular to the surface130a.In some embodiments, the surface130sof the semiconductor device130may be substantially perpendicular to the surface120aof the semiconductor device120. In some embodiments, the surface130aof the semiconductor device130may be substantially parallel to the surface120aof the semiconductor device120. The semiconductor device130may have a conductive pad131.

Each of the semiconductor devices110,120, and130may include a chip or a die including a semiconductor substrate, one or more integrated circuit devices and one or more overlying interconnection structures therein. The integrated circuit devices may include active devices such as transistors and/or passive devices such as resistors, capacitors, inductors, or a combination thereof. In some embodiments, a height of the semiconductor devices110,120, and/or130may be in a range from about 100 μm to about 300 μm.

The conductive layer210may electrically connect the semiconductor device110to the semiconductor device120. The conductive layer210may be disposed in direct contact with the conductive pad111of the semiconductor device110. The conductive layer210may extend along a direction substantially parallel to a surface111a(which may also be referred to as “an upper surface”) of the conductive pad111. The conductive layer210may extend onto and directly contact a portion of the surface111aof the conductive pad111. The conductive layer210may be disposed in direct contact with the conductive pad121of the semiconductor device120. The conductive layer210may extend along a direction substantially parallel to a surface121a(which may also be referred to as “an upper surface”) of the conductive pad121. The conductive layer210may extend on and directly contact a portion of the surface121aof the conductive pad121. The conductive layer210may be disposed in direct contact with the surface110aof the semiconductor device110, the surface120sof the semiconductor device120and the surface120aof the semiconductor device120. In some embodiments, the conductive layer210may have a slanted surface. In some embodiments, the conductive layer210may have a curved surface. In some embodiments, a thickness of the conductive layer210may be in a range from about 7 μm to about 15 μm.

The conductive layer220may electrically connect the semiconductor device120to the semiconductor device130. The conductive layer220may be spaced apart from the conductive layer210. In some embodiments, the conductive layer220may be spaced apart from the conductive layer210by a distance D1of at least 20 μm, at least 30 μm, at least 40 μm or at least 50 μm. The conductive layer220may be disposed in direct contact with the conductive pad121of the semiconductor device120. The conductive layer220may extend along a direction substantially parallel to a surface121aof the conductive pad121. The conductive layer220may extend onto and directly contact a portion of the surface121aof the conductive pad121. The conductive layer220may be disposed in direct contact with the surface120aof the semiconductor device120. The conductive layer220may be disposed in direct contact with the conductive pad131of the semiconductor device130. The conductive layer220may extend along a direction substantially parallel to a surface131a(which may also be referred to as “an upper surface”) of the conductive pad131. The conductive layer220may extend onto and directly contact a portion of the surface131aof the conductive pad131. The conductive layer220may be disposed in direct contact with the surface130sof the semiconductor device130. The conductive layer220may be in direct contact with the surface130aof the semiconductor device130. In some embodiments, the conductive layer220may have a slanted surface. In some embodiments, the conductive layer220may have a curved surface. In some embodiments, a thickness of the conductive layer220may be in a range from about 7 μm to about 15 μm.

In some embodiments, the conductive layer210and/or the conductive layer220may include, for example but not limited thereto, aluminum (Al), gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), other metal(s) or alloy(s), or a combination of two or more thereof.

Stacked semiconductor devices are usually electrically connected through wire bonding or by conductive pillars. An encapsulation layer is then formed to cover the semiconductor devices and the wires and/or the pillars. The wires and/or pillars have a relatively great length. The relatively long wires and/or pillars can be damaged during the operation of encapsulation (e.g., the wires and/or pillars may be broken by a relatively strong molding flow), which may greatly increase the difficulty as well as the manufacturing cost of the rework process of the wires and/or pillars. In contrast, with the design of the conductive layers210and220in accordance with some embodiments of the present disclosure, the length of each of the conductive layers210and220can be relatively short. Therefore, the damage of the conductive layer210and/or the conductive layer220caused by the relatively strong molding flow can be avoided. Thus, the difficulty as well as the manufacturing cost of the rework process of the conductive layer210and/or the conductive layer220can be significantly reduced, and the yield and reliability of the semiconductor device package100can be increased.

In addition, in the manufacturing process of a semiconductor device package, defects may be found in the semiconductor devices, and abnormalities may occur in the formation process of the conductive layer(s), which may increase the difficulty and the manufacturing cost of the rework process of the semiconductor device package. With the design of the conductive layers210and220in accordance with some embodiments of the present disclosure, the conductive layer210and the conductive layer220can be relatively short in length and can electrically connect the semiconductor device120to the semiconductor device110and the semiconductor device130, respectively. Accordingly, the semiconductor devices110,120and130can be electrically connected through a conductive structure including separated relatively short conductive segments (e.g., conductive layers210and220), the chance of damage of the whole conductive structure can be reduced significantly, and hence the damage of part of these conductive segments (e.g., the conductive layer210or the conductive layer220) can require fewer components (e.g., fewer pieces of the semiconductor devices) to be reworked. Thus, the difficulty and the manufacturing cost of the rework process of the semiconductor device package100can be significantly reduced, and the manufacturing yield of the semiconductor device package100can be significantly increased.

Moreover, with the design of the conductive layers210and220in accordance with some embodiments of the present disclosure, different semiconductor devices (e.g., semiconductor devices110,120and130) can be electrically connected to different signal sources through different conductive layers, which can provide greater design flexibility and more device applications. Furthermore, the relatively short conductive layers210and220can reduce undesired electrical interferences (e.g., inductance effect when the package is working at a relatively high frequency) and thus can provide an improved electrical performance, and a relatively smaller elevational space can be occupied.

The supporting structure160may be disposed on the semiconductor device110. A portion110a1of the surface110aof the semiconductor device110and a portion120s1of the surface120sof the semiconductor device120may define a corner C1. The supporting structure160may be disposed in the corner C1.

The supporting structure160may be disposed in direct contact with the surface120sof the semiconductor device120. The supporting structure160may be in direct contact with the portion110a1of the surface110aof the semiconductor device110. The supporting structure160may be in direct contact with the portion120s1of the surface120sof the semiconductor device120. The conductive layer210may be disposed in direct contact with the supporting structure160. The conductive layer210may be in direct contact with a portion110a1of the surface110aof the semiconductor device110. The conductive layer210may be in direct contact with a portion120s2of the surface120sof the semiconductor device120. In some embodiments, an interface between the supporting structure160and the semiconductor device120and an interface between the conductive layer210and the semiconductor device120may be continuous. In some embodiments, the supporting structure160may have a sloped concave surface. The conductive layer210may be in direct contact with the sloped concave surface of the supporting structure160. In some embodiments, a thickness of the conductive layer210at the corner C1may be in a range from about 10 μm to about 13 μm.

The supporting structure170may be disposed on the semiconductor device120. A portion120a1of the surface120aof the semiconductor device120and a portion130s1of the surface130sof the semiconductor device130may define a corner C2. The supporting structure170may be disposed in the corner C2.

The supporting structure170may be disposed in direct contact with the surface130sof the semiconductor device130. The supporting structure170may be in direct contact with the portion120a1of the surface120aof the semiconductor device120. The supporting structure170may be in direct contact with the portion130s1of the surface130sof the semiconductor device130. The conductive layer220may be disposed in direct contact with the supporting structure170. The conductive layer220may be in direct contact with a portion120a2of the surface120aof the semiconductor device120. The conductive layer220may be in direct contact with a portion130s2of the surface130sof the semiconductor device130. In some embodiments, an interface between the supporting structure170and the semiconductor device130and an interface between the conductive layer220and the semiconductor device130may be continuous. In some embodiments, the supporting structure170may have a sloped concave surface. The conductive layer220may be in direct contact with the sloped concave surface of the supporting structure170. In some embodiments, a thickness of the conductive layer220at the corner C2may be in a range from about 10 μm to about 13 μm.

In some embodiments, the supporting structure160and/or the supporting structure170may include, for example but not limited thereto, an ABF, polyimide (PI), an epoxy-based material, or a combination of two or more thereof.

When a conductive layer having a relatively small thickness (e.g., equal to or less than 15 μm) is formed in a corner defined by two surfaces substantially perpendicular to each other, the portion of the conductive layer in the corner may easily crack or break due to the relatively sharp angle defined by the two surfaces of the corner. In accordance with some embodiments of the present disclosure, the conductive layer (e.g., conductive layer210and/or conductive layer220) may be formed on the supporting structure (e.g., the supporting structure160and/or the supporting structure170) disposed in the corner (e.g., the corner C1and/or the corner C2), thus the conductive layer can be raised up and supported by the supporting structure at the corner, and the angle of the conductive layer at the corner can be smoothed. Accordingly, the cracking or breaking issues of conductive layer(s) formed at the corner(s) having sharp angles can be avoided, and the reliability of the conductive layer(s) can be improved.

The encapsulation layer180may be disposed on the semiconductor device110, the semiconductor device120, the semiconductor device130, the conductive layer210and conductive layer220. The encapsulation layer180may be in direct contact with the conductive pad111of the semiconductor device110. The encapsulation layer180may be in direct contact with the conductive pad121of the semiconductor device120. The encapsulation layer180may be in direct contact with the conductive pad131of the semiconductor device130. In some embodiments, the encapsulation layer180may include, for example, but is not limited to, an epoxy resin having fillers, a molding compound (e.g., an epoxy molding compound or other molding compounds), polyimide, a phenolic compound or material, a material with a silicone dispersed therein, or a combination thereof.

In accordance with some embodiments of the present disclosure, as illustrated inFIG. 1, the semiconductor device package100may further include semiconductor devices110′ and120′, supporting structures160′ and170′ and conductive layers210′ and220′. The semiconductor device110′ may have a conductive pad111′. The semiconductor device120′ may have a conductive pad121′. The semiconductor device130may further have a conductive pad131′. The semiconductor device110′ may be attached to the carrier101through an adhesive layer191′. The semiconductor device120′ may be attached to the semiconductor device110′ through an adhesive layer192′. The semiconductor device120′ may be attached to the semiconductor device130through the adhesive layer193. The semiconductor device130may be stacked on the semiconductor devices120and120′. The conductive layer220′ may be spaced apart from the conductive layer210′ above the semiconductor device120′. The conductive layer210′ and the conductive layer220′ may directly contact the conductive pad121′ of the semiconductor device120. The conductive layer220′ may directly contact the conductive pad131′ of the semiconductor device130. The conductive layer210′ may directly contact the conductive pad111′ of the semiconductor device110. In some embodiments, as shown inFIG. 1, the semiconductor device package100may have a symmetric structure with respect to the semiconductor device130.

FIG. 2illustrates a perspective view of a portion of the semiconductor device package100in accordance with some embodiments of the present disclosure. The figure has been simplified for a better understanding of the aspects of the present disclosure.

As illustrated inFIG. 2, the conductive layer210may extend onto and directly contact a portion of the upper surface (e.g., surface120a) of the semiconductor device120. The conductive layer210may extend onto and directly contact a portion of the lateral surface (e.g., surface120s) of the semiconductor device120. The conductive layer210may extend onto and directly contact a portion of the upper surface (e.g., surface110a) of the semiconductor device110. Two opposite end portions of the conductive layer210may extend onto and directly contact the conductive pad111of the semiconductor device110and the conductive pad121of the semiconductor device120, respectively. In some embodiments, the conductive layer210may extend continuously onto and throughout the surface121aof the conductive pad121, the surface120aof the semiconductor device120, the surface120sof the semiconductor device120, the surface110aof the semiconductor device110and the surface111aof the conductive pad111to electrically connect the conductive pad121of the semiconductor device120to the conductive pad111of the semiconductor device110.

As illustrated inFIG. 2, the conductive layer220may extend onto and directly contact a portion of the upper surface (e.g., surface130a) of the semiconductor device130. The conductive layer220may extend onto and directly contact a portion of the lateral surface (e.g., surface130s) of the semiconductor device130. The conductive layer220may extend onto and directly contact a portion of the upper surface (e.g., surface120a) of the semiconductor device120. Two opposite end portions of the conductive layer220may extend onto and directly contact the conductive pad121of the semiconductor device120and the conductive pad131of the semiconductor device130, respectively. In some embodiments, the conductive layer220may extend continuously onto and throughout the surface131aof the conductive pad131, the surface130aof the semiconductor device130, the surface130sof the semiconductor device130, the surface120aof the semiconductor device120and the surface121aof the conductive pad121to electrically connect the conductive pad131of the semiconductor device130to the conductive pad121of the semiconductor device120. The conductive layer210may be spaced apart from the conductive layer220above the conductive pad121.

FIG. 3Aillustrates an enlarged top view of a portion of a semiconductor device package in accordance with some embodiments of the present disclosure. The conductive layer210may cover a portion121A of the conductive pad121. The portion121A of the conductive pad121may be in direct contact with the conductive layer210. The conductive layer220may cover a portion121B of the conductive pad121. The portion121B of the conductive pad121may be in direct contact with the conductive layer220. The portion121A of the conductive pad121may be opposite to the portion121B of the conductive pad121. The portion121A of the conductive pad121may be spaced apart from the portion121B of the conductive pad121. In some embodiments, a width W2of the conductive pad121may be substantially greater than a width W1of the conductive layer210.

FIG. 3Billustrates an enlarged top view of a portion of a semiconductor device package in accordance with some embodiments of the present disclosure. The structure inFIG. 3Bis similar to the structure inFIG. 3Aexcept that, in some embodiments, a width W3of the conductive pad121may be less than a width W1of the conductive layer210.

FIG. 3Cillustrates an enlarged top view of a portion of a semiconductor device package in accordance with some embodiments of the present disclosure. The structure inFIG. 3Cis similar to the structure inFIG. 3Aexcept that, in some embodiments, a width W4of the conductive pad121may be substantially equal to a width W1of the conductive layer210.

FIG. 4Aillustrates an enlarged cross-sectional view of a portion of a semiconductor device package in accordance with some embodiments of the present disclosure. The structure inFIG. 4Ais similar to the structure of the corresponding portion inFIG. 1except that, in some embodiments, the conductive pad421of the semiconductor device120may include a pad421A and a pad421B spaced apart from each other. The conductive layer210and the conductive layer220may be disposed in direct contact with the pad421A and the pad421B, respectively. The pad421A may be electrically connected to the pad421B through an internal interconnection structure (not shown) within the semiconductor device120.

FIG. 4Billustrates an enlarged cross-sectional view of a portion of a semiconductor device package in accordance with some embodiments of the present disclosure. The structure inFIG. 4Bis similar to the structure of the corresponding portion inFIG. 1except that, in some embodiments, the conductive pad422of the semiconductor device120may protrude from the surface120aof the semiconductor device120. The conductive pad422may have a surface422a(which may also be referred as “an upper surface”) and a surface422s1(which may also be referred to as “a lateral surface”) substantially perpendicular to the surface422a.The conductive layer210may be in direct contact with the surface422aand the surface422s1of the conductive pad422of the semiconductor device120. The conductive pad422may have a surface422s2opposite to the surface422s1. The conductive layer220may be in direct contact with the surface422aand the surface422s2of the conductive pad422.

FIG. 4Cillustrates an enlarged cross-sectional view of a portion of a semiconductor device package in accordance with some embodiments of the present disclosure. The structure inFIG. 4Cis similar to the structure of the corresponding portion inFIG. 1except that, in some embodiments, the conductive layer410may include sub-layers411,412and413.

The sub-layer411may be disposed in direct contact with the conductive pad121. The sub-layer412may be disposed in direct contact with the sub-layer411. The sub-layer413may be disposed in direct contact with the sub-layer412. In some embodiments, the sub-layer411and the sub-layer412may be seed layers, and the sub-layer413may be a conductive layer. The seed layer411may be disposed in direct contact with the surface110aof the semiconductor device110. The seed layer411may be disposed in direct contact with the conductive pad111of the semiconductor device110. The seed layer411may be disposed in direct contact with the conductive pad121of the semiconductor device120. The conductive layer420may include sub-layers421,422and423. In some embodiments, the sub-layer421and the sub-layer422may be seed layers, and the sub-layer423may be a conductive layer. The seed layer421may be disposed in direct contact with the conductive pad121of the semiconductor device120and the conductive pad131of the semiconductor device130. In some embodiments, the seed layer421may be formed of or include titanium (Ti), and the seed layer412may be formed of or include copper (Cu).

FIG. 5illustrates a cross-sectional view of a semiconductor device package200in accordance with some embodiments of the present disclosure. The semiconductor device package200may include semiconductor devices110,110′,120,120′ and130, conductive layers210,210′,220and220′, supporting structures150,150′,160,160′,170and170′, an encapsulation layer180, an interconnection structure610, an electrical contact620and an external connector630.

The interconnection structure610may be disposed on the semiconductor devices110,110′,120,120′ and130. The interconnection structure610may include redistribution layers (RDL). The interconnection structure610may include conductive units (such as pads, wires, and/or vias) and a dielectric layer. A portion of the conductive units may be covered or encapsulated by the dielectric layer while another portion611of the conductive units may be exposed from the dielectric layer to provide electrical connections for the semiconductor devices110,110′,120,120′ and130.

The electrical contact620(e.g., a solder ball) may be disposed between the interconnection structure610and the semiconductor devices110,110′,120,120′ and130. The electrical contact620may directly contact the exposed portion611of the conductive units of the interconnection structure610. The electrical contact620may directly contact the conductive layer220. The electrical contact620may directly contact the conductive layer220′. In some embodiments, the electrical contact620may include a conductive bump.

The external connector630(e.g. a solder ball) may be disposed on a surface of the interconnection structure610facing away from the semiconductor devices110,110′,120,120′ and130. The external connector630can provide electrical connections between the semiconductor package devices110,110′,120,120′ and130and external components (e.g. external circuits or circuit boards). In some embodiments, the external connector630may include a controlled collapse chip connection (C4) bump, a ball grid array (BGA) and/or a land grid array (LGA).

FIGS. 6A, 6B, 6C, 6D, 6E, 6F, 6G, 6H, 6I, 6J, 6K and 6Lillustrate a method of manufacturing a semiconductor device package100in accordance with some embodiments of the present disclosure. Various figures have been simplified for a better understanding of the aspects of the present disclosure.

Referring toFIG. 6A, a carrier101may be provided. A semiconductor device110having a conductive pad111may be disposed on the carrier101. A semiconductor device110′ having a conductive pad111′ may be disposed on the carrier101. The semiconductor devices110and110′ may be attached to the carrier101through an adhesive layer191and an adhesive layer191′, respectively. A semiconductor device120having a conductive pad121may be stacked on the semiconductor device110. A semiconductor device120′ having a conductive pad121′ may be stacked on the semiconductor device110′. The semiconductor devices120may be attached to the semiconductor device110through an adhesive layer192. The semiconductor devices120′ may be attached to the semiconductor device110′ through an adhesive layer192′. A semiconductor device130having conductive pads131and131′ may be stacked on the semiconductor devices120and120′. In some embodiments, the adhesive layer191,191′,192,192′ and/or193may include a die attach film (DAF).

Referring toFIG. 6B, an insulation material510may be formed on the semiconductor devices110,110′,120,120′ and130. The insulation material510may cover the semiconductor devices110,110′,120,120′ and130and at least a portion of a surface101a(which may also be referred to as “an upper surface”) of the carrier101. In some embodiments, the insulation material510may include PI, epoxy resin, or a combination thereof. In some embodiments, the insulation material510may be formed by a coating process, such as a spin coating process.

Referring toFIG. 6C, the insulation material510may be partially removed. A plurality of exposure processes E1, E2and E3may be performed on a plurality of portions of the insulation material510. In some embodiments, each of the exposure processes E1, E2and E3may use a respective alignment mask. Each respective alignment mask may correspond to each of the edge portions (e.g., edge portions110E,120E and130E inFIG. 7D) of the semiconductor devices110,110′,120,120′ and130.

Referring toFIG. 6D, after the exposure processes E1, E2and E3are performed on the portions of the insulation material510, a development process may then be performed to remove the exposed portions of the insulation material510. The remained unexposed portions of the insulation material510may form supporting structures150,160and170. Partially removing the insulation material510may expose a plurality of edge portions110E,120E and130E of the semiconductor devices110,110′,120,120′ and130. The edge portions110E of the semiconductor devices110and110′ may be defined by the exposure process E1. The edge portions120E of the semiconductor devices120and120′ may be defined by the exposure process E2. The edge portions130E of the semiconductor device130may be defined by the exposure process E3.

Referring toFIG. 6E, a seed layer520may be formed on the supporting structures150,160and170and the semiconductor devices110,110′,120,120′ and130. In some embodiments, the seed layer520may include multiple layers, for example, a titanium (Ti) layer and a copper (Cu) layer formed on the titanium (Ti) layer. In some embodiments, the seed layer520may be formed by sputtering.

Referring toFIG. 6F, a photoresist material530may be formed on the seed layer520.

Referring toFIG. 6G, the photoresist material530may be partially removed. A plurality of exposure processes E4, E5and E6may be performed on a plurality of portions of the photoresist material530. In some embodiments, each of the exposure processes E4, E5and E6may use a respective alignment mask. Each respective alignment mask may correspond to the location of each of the conductive layers to be formed subsequently (e.g., conductive layers210,220and230).

Referring toFIG. 6H, after the exposure processes E4, E5and E6are performed on the portions of the photoresist material530, a development process may then be performed to remove the exposed portions of the photoresist material530to form a patterned photoresist layer PR. The patterned photoresist layer PR has a plurality of openings to expose a plurality of predetermined regions R1, R2and R3. Portions of the seed layer520at the predetermined regions R1, R2and R3may be exposed from the patterned photoresist layer PR.

Referring toFIG. 6I, a conductive material layer540may be formed on the plurality of predetermined regions R1, R2and R3. The conductive material layer540may be formed directly contacting the seed layer520. In some embodiments, the conductive material layer540may be formed by an electroplating process.

Referring toFIG. 6J, after the conductive material layer540is formed on the plurality of predetermined regions R1, R2and R3, the patterned photoresist layer PR may be removed. After the conductive material layer540is formed on the plurality of predetermined regions R1, R2and R3, portions of the seed layer520under the patterned photoresist layer PR may be removed. In some embodiments, the patterned photoresist layer PR may be removed by a stripping process. In some embodiments, the portions of the seed layer520may be removed by a wet etching process. After the patterned photoresist layer PR and the portions of the seed layer520under the patterned photoresist layer PR are removed, conductive layers210,220and230are formed in the predetermined regions R2, R3and R1, respectively. The conductive layers210,220and230may include portions of the conductive material layer540and portions of the seed layer520.

Referring toFIG. 6K, an encapsulation material550may be formed on the semiconductor devices110,110′,120,120′ and130. The encapsulation material550may be formed on the conductive layers210,210′,220,220′,230and230. The encapsulation material550may cover the conductive layers210,210′,220,220′,230and230.

Referring toFIG. 6L, the encapsulation material550may be partially removed to form an encapsulation layer180. The encapsulation material550may be partially removed to expose a portion of the conductive layer220. The encapsulation material550may be partially removed to expose a portion of the conductive layer220′. In some embodiments, the encapsulation material550may be partially removed by a grinding process.

FIG. 7A,FIG. 7B,FIG. 7C,FIG. 7DandFIG. 7Eillustrate a method of manufacturing a semiconductor device package200in accordance with some embodiments of the present disclosure. Various figures have been simplified for a better understanding of the aspects of the present disclosure.

Referring toFIG. 7A, an interconnection structure610with external connectors630formed thereon may be provided. The interconnection structure610may be formed on a carrier801. The external connectors630may be formed on the interconnection structure610.

Referring toFIG. 7B, a carrier802may be attached to the interconnection structure610and the external connectors630. The carrier802may be bonded to a surface of the interconnection structure610where the external connectors630are located. The carrier801may then be removed to expose a portion611of the conductive units and/or redistribution layers of the interconnection structure610. One or more electrical contacts620may then be formed directly contacting the exposed portion611.

Referring toFIG. 7D, the interconnection structure610may be bonded to the stacked semiconductor devices (e.g., semiconductor devices110,110′,120,120′ and130). The interconnection structure610may be bonded to the conductive layers220and220′ through the electrical contacts620.

Referring toFIG. 7E, the carrier101may be removed to form the semiconductor device package200.

FIG. 8illustrates a cross-sectional view of a semiconductor device package1in accordance with some embodiments of the present disclosure. The semiconductor device package1may include a substrate2, stacked semiconductor devices3,4,5and6, a conductive layer7and an insulation layer8. The semiconductor devices3,4,5and6may have conductive pads3a,4a,5aand6a,respectively. The substrate2may have a conductive pad2a.The conductive layer7may electrically connect the conductive pads2a,3a,4a,5aand6a.The conductive layer7may be spaced apart from the upper surfaces and the lateral surfaces of the semiconductor devices3,4,5and6by the insulation layer8. The insulation layer8may be a continuous layer having through holes. Portions of the conductive layer7may be filled in the through holes of the insulation layer8to electrically connect to the conductive pads2a,3a,4a,5aand6a.The semiconductor device package1may further include laser-blocking layers9a,9b,9cand9ddisposed on the conductive pads3a,4a,5aand6a,respectively. In some embodiments, the laser-blocking layers9a,9b,9cand/or9dmay be formed of or include nickel (Ni), lead (Pb), gold (Au), or a combination of two or more thereof. The conductive layer7may directly contact the laser-blocking layers9a,9b,9cand9d.The conductive layer7may be spaced apart from the conductive pads3a,4a,5aand6aby the laser-blocking layers9a,9b,9cand9d,respectively. The conductive layer7can electrically connect all of the conductive pads3a,4a,5aand6aof the semiconductor devices3,4,5and6to the conductive pad2aof the substrate2. The conductive layer7is relatively long and may be damaged in subsequent processes, which may increase the difficulty and the manufacturing costs of the rework process of the conductive layer7.

In accordance with some embodiments illustrated inFIG. 1, the conductive layer7electrically connecting all of the semiconductor devices3,4,5and6to the substrate2can have a relatively great length. In the manufacturing process of the semiconductor device package1, defects may be found in the semiconductor devices3,4,5and/or6, abnormalities may occur in the formation process of the relatively long conductive layer7, and the conductive layer7may also be damaged during the operation of encapsulation. Any or all of these situations may increase the difficulty as well as the manufacturing cost of the rework process of the damaged conductive layer7. In addition, in accordance with some embodiments illustrated inFIG. 1, all of the semiconductor devices3,4,5and6can only be connected to the same signal source while sharing the same conductive layer7. Moreover, the relatively great length of the conductive layer7may also occupy a relatively great elevational space, and the relatively great length of the conductive layer7may raise some issues (e.g., inductance effect when the package is working at a relatively high frequency).

FIG. 9illustrates a cross-sectional view of a semiconductor device package10in accordance with some embodiments of the present disclosure. The semiconductor device package10may include a carrier15, semiconductor devices11and12, wires13,14,16and17and an encapsulation layer18. The semiconductor devices11and12may be stacked on the carrier15and encapsulated by the encapsulation layer18. The semiconductor device11and12may be electrically connected to the carrier1through the wires13and14, respectively. The relatively great length of the wires13,14,16and17may occupy a relatively great elevational space (e.g., about 150 μm in height), which may cause an undesired inductance effect. Moreover, the wires13,14,16and17may also be damaged during the operation of encapsulation (e.g., the wires13,14,16and17may be broken by a relatively strong molding flow).

In some embodiments, multiple wires may be bonded to one single conductive pad of the semiconductor device11and/or the semiconductor device12. However, due to the reduced size of the conductive pad, the first formed wire on the conductive pad may be damaged or broken by the later formed wire in the wire bonding process. In addition, the large diameter of the wires (e.g., about 15 μm to about 50 μm) may adversely affect the precision of the wiring bonding process of multiple wires on a single conductive pad.

FIG. 10illustrates a cross-sectional view of a semiconductor device package20in accordance with some embodiments of the present disclosure. The semiconductor device package20may include semiconductor devices21and22, conductive pillars23and24, an encapsulation layer28, electrical contacts29and an interconnection structure30. The stacked semiconductor devices21and22may be electrically connected to the interconnection structure30through the conductive pillars23and24, respectively. The conductive pillars23and24may be formed by, for example, forming through holes within the encapsulation layer28by a laser drilling process, followed by filling a conductive material in the through holes. The laser drilling process may suffer from low manufacturing yields. In addition, the relatively long conductive pillars23and24can be damaged during the operation of encapsulation (e.g., the conductive pillars may be broken by a relatively strong molding flow), which may greatly increase the difficulty as well as the manufacturing cost of the rework process of the conductive pillars. Moreover, it is difficult to control the uniformity of the heights of the conductive pillars, which may increase the difficulty of subsequent planarization processes.

As used herein, the terms “approximately,” “substantially,” “substantial” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. As used herein with respect to a given value or range, the term “about” generally means within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. Ranges can be expressed herein as being from one endpoint to another endpoint or between two endpoints. All ranges disclosed herein are inclusive of the endpoints unless specified otherwise. The term “substantially coplanar” can refer to two surfaces within micrometers (μm) of lying along the same plane, such as within 10 μm, within 5 μm, within 1 μm, or within 0.5 μm of lying along the same plane. When referring to numerical values or characteristics as “substantially” the same, the term can refer to the values lying within ±10%, ±5%, ±1%, or ±0.5% of an average of the values.

The foregoing outlines features of several embodiments and detailed aspects of the present disclosure. The embodiments described in the present disclosure may be readily used as a basis for designing or modifying other processes and structures for carrying out the same or similar purposes and/or achieving the same or similar advantages of the embodiments introduced herein. Such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions, and alterations may be made without departing from the spirit and scope of the present disclosure.