SEMICONDUCTOR LIGHT EMITTING DEVICE

A semiconductor light emitting device includes a substrate and a semiconductor multilayer stacked on the substrate. The semiconductor multilayer includes an n-side clad layer stacked above the substrate, an active layer stacked above the n-side clad layer, and a p-side clad layer stacked above the active layer. The semiconductor multilayer includes a first plane perpendicular to a stacking direction in which the semiconductor multilayer is stacked, and a lattice constant inside the first plane is an anisotropy constant.

TECHNICAL FIELD

The present disclosure relates to semiconductor light emitting devices.

BACKGROUND ART

Conventionally, laser light is used in processing applications, and thus high-power and high-efficient laser light sources are required. As the high-power and high-efficient laser light sources, semiconductor laser elements are utilized. As a high-power semiconductor laser element, a light emitting array element is known in which light emitting points serving as heat sources are dispersed and arranged in an array. A plurality of beams of laser light from the light emitting array element as described above are combined using an optical system into one beam of laser light to be used. In this case, when warpage occurs in the light emitting array element, intervals between the light emitting points are displaced, and thus the combination efficiency of the laser light from the light emitting array element and the optical system is lowered. The efficiency of the light source as a whole is lowered accordingly.

As a conventional technique for solving the problem as described above, for example, a light emitting array element disclosed in Patent Literature (PTL) 1 is known. The light emitting array element disclosed in PTL 1 will be described below with reference toFIG. 32.FIG. 32is a perspective view schematically showing the configuration of light emitting array element2001disclosed in PTL 1. As shown inFIG. 32, light emitting array element2001includes substrate2004and semiconductor multilayers2010. In light emitting array element2001, dividing grooves are formed between light emitting points to extend partway through substrate2004from semiconductor multilayers2010. In this way, in the light emitting array element disclosed in PTL 1, warpage attempts to be suppressed.

CITATION LIST

Patent Literature

SUMMARY OF INVENTION

Technical Problem

In a laser chip including a substrate and a semiconductor multilayer stacked on the substrate, in a free-standing state, between the semiconductor multilayer and the substrate, there is a difference in the lattice constant of a plane (for example, in GaN, a c-plane) perpendicular to the stacking direction of the semiconductor multilayer. In other words, a lattice mismatch occurs between the semiconductor multilayer and the substrate. In order to improve the warpage of a laser chip which has significant warpage resulting from a lattice mismatch, it is necessary to provide a wide groove in a semiconductor multilayer which is the source of distortion. When the laser chip is junction-down mounted on a mounting substrate or the like in a state where the wide groove is provided in the semiconductor multilayer as described above, a void is generated in the region of the groove, with the result that the heat dissipation property of the laser chip deteriorates. Hence, the light output property of the laser chip mounted is lowered.

The present disclosure solves the problems as described above, and an object thereof is to provide a semiconductor light emitting device which can reduce distortion resulting from a lattice mismatch.

Solution to Problem

In order to solve the problems described above, a semiconductor light emitting device according to an aspect of the present disclosure is a semiconductor light emitting device that emits light in a direction of resonance, the semiconductor light emitting device includes: a substrate; and one or more semiconductor multilayers stacked on the substrate, each of the one or more semiconductor multilayers includes: an n-side clad layer stacked above the substrate; an active layer stacked above the n-side clad layer; and a p-side clad layer stacked above the active layer, each of the one or more semiconductor multilayers includes a first plane perpendicular to a stacking direction in which the one or more semiconductor multilayers are stacked, and a lattice constant inside the first plane is an anisotropy constant.

In order to solve the problems described above, a semiconductor light emitting device according to another aspect of the present disclosure includes a substrate; and one or more semiconductor multilayers stacked on the substrate, each of the one or more semiconductor multilayers includes: an n-side clad layer stacked above the substrate; an active layer that is stacked above the n-side clad layer and includes at least Al; and a p-side clad layer stacked above the active layer, each of the one or more semiconductor multilayers includes a first plane perpendicular to a stacking direction in which the one or more semiconductor multilayers are stacked, the first plane includes, inside the first plane, a first orientation and a third orientation that is tilted relative to the first orientation, the substrate includes a second plane perpendicular to the stacking direction, the second plane includes, inside the second plane, a second orientation parallel to the first orientation and a fourth orientation that is tilted relative to the second orientation and is parallel to the third orientation, a first lattice constant in the first orientation is equal to a second lattice constant in the second orientation, and a third lattice constant in the third orientation is less than a fourth lattice constant in the fourth orientation.

Advantageous Effects of Invention

According to the present disclosure, it is possible to provide a semiconductor light emitting device which can reduce distortion resulting from a lattice mismatch.

DESCRIPTION OF EMBODIMENTS

Embodiments of the present disclosure will be described below with reference to drawings. The embodiments described below show specific examples of the present disclosure. Hence, values, shapes, materials, constituent elements, the arrangements, positions, and connection forms of the constituent elements, and the like which are shown in the embodiments below are examples, and are not intended to limit the present disclosure.

The drawings each are schematic views, and are not exactly shown. Hence, in the drawings, scales and the like are not necessarily the same as each other. In the drawings, substantially the same configurations are identified with the same reference signs, and the repeated description thereof is omitted or simplified.

In the present specification, the terms “upward” and “downward” do not indicate an upward direction (vertically upward) and a downward direction (vertically downward) in absolute spatial recognition but are used as terms which are defined by a relative positional relationship based on the order of layers stacked in a multilayer configuration. The terms “upward” and “downward” are applied not only to a case where two constituent elements are spaced with another constituent element present between the two constituent elements but also to a case where two constituent elements are arranged in contact with each other.

A semiconductor light emitting device according to embodiment 1 will be described.

Configuration

The configuration of semiconductor light emitting device100according to the present embodiment will first be described with reference toFIGS. 1 and 2.FIGS. 1 and 2are respectively a schematic top view and a schematic cross-sectional view of semiconductor light emitting device100according to the present embodiment.FIG. 2shows a cross section taken along line II-II inFIG. 1. InFIGS. 1 and 2and parts of drawings described later, first direction D1, second direction D2, and third direction D3which are perpendicular to each other are shown.

Semiconductor light emitting device100is a semiconductor device which emits light. In the present embodiment, semiconductor light emitting device100is a laser chip which emits laser light. The direction of emission of the light of semiconductor light emitting device100is a direction parallel to first direction D1shown inFIGS. 1 and 2. In other words, the direction of resonance of the light (that is, the direction of a resonator) is a direction parallel to first direction D1shown inFIGS. 1 and 2. The light (laser light) is mainly emitted from one of both end surfaces of semiconductor light emitting device100shown inFIG. 1in first direction D1.

In the present embodiment, semiconductor light emitting device100further includes p electrodes114and n electrode116.

Semiconductor multilayer109includes n-side clad layer111which is stacked above substrate110, active layer112which is stacked above n-side clad layer111, and p-side clad layer113which is stacked above active layer112. In the present embodiment, semiconductor multilayer109includes a gallium nitride-based semiconductor. A stacking direction in which semiconductor multilayer109is stacked is a direction parallel to third direction D3shown inFIGS. 1 and 2. In other words, the stacking direction is a direction perpendicular to the major surface of substrate110on which semiconductor multilayer109is stacked and is the direction of thickness of the layers of the semiconductor multilayer. In the present embodiment, semiconductor light emitting device100includes a plurality of semiconductor multilayers109. A width of each of semiconductor multilayers109in the direction of resonance is less than a total of widths in a direction (second direction D2) perpendicular to the direction of resonance and the stacking direction.

Furthermore, as shown inFIGS. 1 and 2, a plurality of p electrodes114are provided on p-side clad layers113. A current is injected between p electrodes114and n electrode116provided on the back surface (lower surface inFIG. 2) of substrate110.

Both end surfaces of semiconductor multilayer109in first direction D1form a resonator, and a region into which the current is injected with p electrode114is sandwiched between both the end surfaces. A direction perpendicular to both the end surfaces, that is, first direction D1is defined as the direction of resonance of the light. As shown inFIG. 1, semiconductor light emitting device100may include one or more resonators which correspond to one or more p electrodes114. Semiconductor light emitting device100may have a laser array structure which includes a plurality of resonators.

As shown inFIG. 2, in the regions of p-side clad layer113located on the sides (second direction D2) of p electrode114, a pair of grooves121are provided which extend parallel to the direction of resonance (that is, first direction D1). In this way, in p-side clad layer113of semiconductor multilayer109, a ridge for confining the light and the current can be formed.

In the present embodiment, semiconductor light emitting device100includes one or more groove regions120which are arranged above substrate110and which extend parallel to the direction of resonance. When semiconductor light emitting device100includes a plurality of semiconductor multilayers109, between one semiconductor multilayer109and other semiconductor multilayers109, one or more groove regions120deeper than grooves121for forming the ridges are formed. For the number of one or more groove regions120, for example, a relationship may be satisfied in which a number obtained by subtracting1from the total number of semiconductor multilayers109is greater than the total number of groove regions120. In other words, for the total number L (L is an integer greater than or equal to 2 or more) of semiconductor multilayers109and the total number M (M is an integer greater than or equal to 0) of groove regions120, a relationship of L-1>M may be satisfied.

When semiconductor light emitting device100includes a plurality of resonators, between a certain resonator and resonators other than the certain resonator, at least one groove region120deeper than groove121for forming the ridge is provided.

Although the depth of groove region120is not particularly limited as long as groove region120is deeper than groove121, groove region120may reach substrate110. In this way, it is possible to reduce distortion resulting from a lattice mismatch between substrate110and semiconductor multilayer109.

Here, the crystal structure of n-side clad layer111in the present embodiment will be described with reference toFIG. 3.FIG. 3is schematic views showing the states of the crystal structures of substrate110and semiconductor multilayer109in the present embodiment. Schematic views (a) and (b) inFIG. 3respectively show the crystal structures of cross sections of substrate110and n-side clad layer111in a region of square frame III inFIG. 1perpendicular to the direction of resonance. Here, the cross section of n-side clad layer111perpendicular to the stacking direction is an example of a first plane perpendicular to the stacking direction included in semiconductor multilayer109, and is also referred to as the first plane in the following description. The cross section of substrate110perpendicular to the stacking direction is an example of a second plane perpendicular to the stacking direction included in substrate110, and is also referred to as the second plane in the following description.

Lattice constant dcm inside the first plane of n-side clad layer111shown in schematic view (b) inFIG. 3in the direction of resonance is equal to lattice constant dsm inside the second plane of substrate110shown in schematic view (a) in the direction of resonance (first direction D1). A state where lattice constant dsm is equal to lattice constant dcm is not limited to a state where lattice constant dsm is completely identical to lattice constant dcm, and includes a state where they are substantially the same. For example, a state where a difference between lattice constant dsm and lattice constant dcm is less than or equal to 0.01% of lattice constant dsm or lattice constant dcm is also included in the state where lattice constant dsm is equal to lattice constant dcm.

Lattice constant dca inside the first plane of n-side clad layer111shown in schematic view (b) inFIG. 3in a direction of tilt that is tiled relative to the direction of resonance is less than lattice constant dsa inside the second plane of substrate110shown in schematic view (a) in a direction of tilt.

In other words, for the lattice constants described above, a relationship represented by formulae (1) and (2) below is established.

Instead of the relationship represented by formulae (1) and (2) above, a relationship represented by formula (3) below may be established.

In the present embodiment, the stacking direction of semiconductor multilayer109is the direction of a c-axis in the crystal structure of substrate110. Substrate110and semiconductor multilayer109in the present embodiment have a crystal structure of a hexagonal system. The direction of tilt is a crystal orientation which is determined by a crystal structure, and in the present embodiment, the direction of tilt is a direction which is tilted at 60 degrees or 120 degrees relative to the direction of resonance inside the first plane or inside the second plane.

The direction of tilt in the first plane and the direction of tilt in the second plane are parallel to each other. In other words, the direction of tilt in the first plane and the direction of tilt in the second plane are the same direction. Here, a state where the direction of tilt in the first plane and the direction of tilt in the second plane are parallel to each other includes not only a state where the direction of tilt in the first plane and the direction of tilt in the second plane are completely parallel to each other but also a state where they are substantially parallel. For example, a state where the direction of tilt in the first plane and the direction of tilt in the second plane are displaced from a completely parallel state by the degree of a change in the direction of tilt caused by the anisotropy of the lattice constant is also included in the state where the direction of tilt in the first plane and the direction of tilt in the second plane are parallel to each other.

The fact that although planes are equivalent from the point of view of crystal symmetry, the lattice constant is different depending on the plane orientation is defined as the lattice constant being an anisotropy constant. For example, the lattice constant inside the first plane of semiconductor multilayer109is an anisotropy constant.

A difference between lattice constant dsa in the second plane in the direction of tilt and lattice constant dca in the first plane in the direction of tilt is, for example, greater than or equal to 0.03% of lattice constant dsa or lattice constant dca. The difference between lattice constant dsa in the second plane in the direction of tilt and lattice constant dca in the first plane in the direction of tilt may be greater than or equal to 0.05% of lattice constant dsa or lattice constant dca. In this way, the anisotropy of the lattice constant in the first plane is more remarkable. The difference between lattice constant dsa in the second plane in the direction of tilt and lattice constant dca in the first plane in the direction of tilt may be less than or equal to 0.1% of lattice constant dsa or lattice constant dca.

In the present embodiment, substrate110may include gallium nitride (GaN). For example, substrate110may be a GaN single crystal substrate which is oriented to the c-axis. In other words, substrate110may include GaN, and the major surface (surface on which semiconductor multilayer109is stacked) of substrate110may be a c-plane. Substrate110may include silicon carbide (SiC) or sapphire. As substrate110, a crystalline substrate having a lattice mismatch for semiconductor multilayer109may be used instead. The width (that is, the length of the resonator) of substrate110in the direction of resonance is, for example, 2 mm. The width (that is, the width in second direction D2) of substrate110perpendicular to the direction of resonance and the stacking direction is 10 mm. As described above, the depth of groove region120may reach substrate110. For example, the depth of groove region120is 4 μm from the surface of semiconductor light emitting device100(that is, the upper surface of semiconductor multilayer109). Although the width of groove region120(that is, the width in second direction D2) is not particularly limited, the width is, for example, 100 μm. The cross-sectional shape of groove region120may be concave in the cross section as shown inFIG. 2. In the present embodiment, the width of groove region120does not depend on the position in the direction of depth to be constant. In other words, the cross-sectional shape of groove region120in the present embodiment is a single-step shape (rectangular shape). The cross-sectional shape of groove region120may be such a tapered shape that as groove region120extends closer to n electrode116on the back surface of substrate110in the cross section as shown inFIG. 2, the width is decreased (that is, the width is decreased toward the end) or may be such a tapered shape that as groove region120extends closer to n electrode116on the back surface of substrate110, the width is increased (that is, the width is increased toward the end). The cross-sectional shape of groove region120may be such a multistep shape that the width is stepwise changed in the cross section as shown inFIG. 2.

N-side clad layer111is stacked on substrate110. In the present embodiment, the thickness of n-side clad layer111may be greater than or equal to 1 μm. For example, the thickness of n-side clad layer111may be 3 μm, and the composition thereof may be n-AlxGa1-xN (0<x<1). N-side clad layer111may be doped with Si. For example, the concentration of Si may be 1×1017cm−3.

Active layer112is stacked on n-side clad layer111. Active layer112includes, for example, a gallium nitride-based material. In the present embodiment, active layer112is a quantum well active layer in which a well layer including InxGa1-xN (0<x<1) and a barrier layer including AlxInyGaN (0≤x,y) are alternately stacked. Active layer112includes, for example, two well layers. As long as active layer112is a quantum well active layer, the number of well layers is not limited to two. The number of well layers may be one or three or more.

P-side clad layer113is stacked on active layer112. In the present embodiment, semiconductor light emitting device100includes a plurality of ridges serving as current paths. In the present embodiment, p-side clad layer113is a superlattice layer in which100layers including AlGaN and having a thickness of 3 nm and100layers including GaN and having a thickness of 3 nm are alternately stacked and whose thickness is 0.6 μm. P-side clad layer113may be doped with Mg. For example, the concentration of Mg may be 1×1019cm−3.

The configuration of p-side clad layer113is not limited to this configuration. The thickness of p-side clad layer113may be greater than or equal to 0.1 μm and less than or equal to 1 μm. The composition of p-side clad layer113may be p-AlxGa1-xN (0<x<1). The concentration of Mg may be 1×1019cm−3.

P electrode114may be, for example, a single-layer film or a multilayer film which includes at least one of Cr, Ti, Ni, Pd, Pt, and Au. For example, p electrode114is a multilayer film (Pd/Pt) in which Pd and Pt are stacked in layers sequentially from the side of p-side clad layer113, and p electrodes114are arranged with an interval (pitch) of 225 μm in second direction D2. The width of p electrode114(that is, the width in second direction D2) is, for example, 16 μm.

In the present embodiment of substrate110, n electrode116is a multilayer film (Ti/Pt/Au) in which Ti, Pt, and Au are stacked in layers sequentially from the side of substrate110. The configuration of n electrode116is not limited to this configuration. N electrode116may include another conductive material.

Although not shown in the figure, semiconductor light emitting device100further includes a current block layer and a p-side pad electrode. The current block layer is an insulating layer which covers the region other than p electrode114on the upper surface of semiconductor multilayer109. The current block layer is, for example, a SiO2film, a SiN film, or the like whose thickness is greater than or equal to 100 nm and less than or equal to 500 nm. The current block layer is, for example, a layer whose thickness is 200 nm and which includes SiO2.

P-side pad electrode is a pad-shaped electrode which covers p electrode114, and examples thereof include a multilayer film (Ti/Au) in which Ti and Au are stacked in layers, a multilayer film (Ti/Pt/Au) in which Ti, Pt, and Au are stacked in layers, a multilayer film (Ni/Au) in which Ni and Au are stacked in layers, and the like.

An example of the configuration of the semiconductor light emitting device according to the present embodiment is shown in table 1.

Effects

Effects of semiconductor light emitting device100according to the present embodiment will then be described using the results of experiments shown inFIGS. 4A to 7B.FIGS. 4A and 4Bare graphs showing X-ray reciprocal lattice mapping of semiconductor light emitting device100according to the present embodiment in the direction of resonance and in the direction of tilt, respectively. The direction of tilt inFIG. 4Bis a direction which is tilted at 120° relative to the direction of resonance.FIG. 5is a graph showing the result of the measurement of X-ray diffraction (2 θ/w) in semiconductor light emitting device100according to the present embodiment.FIG. 6is a graph showing the result of the measurement of the amount of warpage of semiconductor light emitting device100according to the present embodiment.FIG. 6shows a relationship between the width of n-side clad layer111(the width in second direction D2) and the amount of warpage.FIG. 7A and 7Bare respectively graphs showing the results of Raman spectrum measurements in semiconductor light emitting device100according to the present embodiment.FIG. 7Ashows a relationship between a Raman peak position and a position in the stacking direction.FIG. 7Ashows the result of the measurements at6dry etching (DE) ratios (that is, the ratio of a total of the widths of all groove regions120to the width of semiconductor light emitting device100in second direction D2).FIG. 7Bshows a relationship between the DE ratio and the Raman peak position.FIG. 7Bshows the result of the measurements in positions in the stacking direction.

The present inventor performed experiments using the semiconductor light emitting device which included groove regions120arranged at regular intervals in second direction D2. The thickness of substrate110used in the present experiments was 80 μm, and the thickness of semiconductor multilayer109was 4.0 μm. The thickness of n-side clad layer111included in semiconductor multilayer109was 3.0 μm. The width of semiconductor light emitting device100in the direction of resonance and the width in second direction D2were 2 mm and 9 mm, respectively. The interval between groove regions120in second direction D2was 225 μm. The depth of groove region120was 4.5 μm. In other words, in groove regions120, all of semiconductor multilayers109and part of substrate110were removed by dry etching.

In the structure described above, anisotropic flexibility in deformation is given to n-side clad layers111which are divided by groove regions120and which are elongated in the direction of resonance. By the action on n-side clad layers111caused by groove regions120, it is possible to lower flexibility in the deformation of n-side clad layers111in the direction of resonance and to increase flexibility in the deformation in the direction of tilt. Consequently, in the direction of resonance, n-side clad layers111maintain the same state as before the formation of groove regions120, and in the direction of tilt, n-side clad layers111can approach a free (free-standing) state for the deformation.

By the effects described above, the lattice constant of n-side clad layer111is maintained to be substantially the same lattice constant of substrate110in the direction of resonance (that is, a difference between the lattice constant of n-side clad layer111and the lattice constant of substrate110is less than or equal to 0.01% of n-side clad layer111or substrate110). On the other hand, n-side clad layer111includes Al, and thus the lattice constant of n-side clad layer111in the direction of tilt is less than the lattice constant of substrate110which does not include Al.

By the configuration as described above, the relationship represented by formulae (1) and (2) or the relationship represented by formula (3) is established.

The present inventor used the X-ray reciprocal lattice mapping shown inFIGS. 4A and 4Bto check the deformation of the crystal structure of n-side clad layer111indicated by the relationships described above. The X axis (that is, the horizontal axis) ofFIGS. 4A and 4Bcorresponds to the reciprocal of the lattice constant in the stacking direction of semiconductor multilayer109, and the Y axis (that is, the vertical axis) ofFIGS. 4A and 4Bcorresponds to the reciprocal of the lattice constant of a plane perpendicular to the stacking direction of semiconductor multilayer109.

As indicated by the result of the experiment in the direction of resonance inFIG. 4A, a peak position in the direction of the X axis corresponding to the lattice constant of substrate110substantially coincides with a peak position in the direction of the X axis corresponding to the lattice constant of n-side clad layer111. Hence, it is found that the lattice constants of substrate110and n-side clad layer111in the direction of resonance are substantially the same as each other.

On the other hand, as indicated by the result of the experiment in the direction of tilt inFIG. 4B, a peak position in the direction of the X axis corresponding to the lattice constant of n-side clad layer111is higher than a peak position in the direction of the X axis corresponding to the lattice constant of substrate110. Hence, it is found that the lattice constant of n-side clad layer111in the direction of tilt is less than the lattice constant of substrate110in the direction of tilt.

The deformation of n-side clad layer111in the stacking direction caused by the deformation of the crystal structure in n-side clad layer111was checked by the measurement of X-ray diffraction (2 θ/ω) shown inFIG. 5. The measurement of X-ray diffraction was performed on three types of samples that were a wafer which was not formed into a piece immediately after the crystal growth of semiconductor multilayer109(that is, before chip processing), a semiconductor light emitting device which was formed into a piece without formation of groove regions120and a semiconductor light emitting device which was formed into a piece and in which groove regions120were formed.

When the measurement was performed on the three types of samples, it was found that only in the semiconductor light emitting device in which groove regions120were formed, the peak position in n-side clad layer111was shifted such that its peak was at a higher angle than the peaks in the other samples. This indicates that the lattice constant in a direction tilted relative to the direction of resonance was decreased and that thus the lattice constant in the stacking direction was increased.

In the state of the semiconductor light emitting device in which groove regions120are formed as described above, distortion in the direction of tilt which is caused by a lattice mismatch between substrate110and semiconductor multilayer109that is the cause of the warpage of substrate110is reduced as compared with distortion in the direction of resonance.

The present inventor checked the effect of the reduction of the distortion described above by the dependence of the amount of warpage of the semiconductor light emitting device in a direction perpendicular to the direction of resonance on the width of the n-side clad layer shown inFIG. 6and the dependence of Raman spectra shown on the groove ratio (DE ratio) shown inFIGS. 7A and 7B.

First, since inFIG. 6, the interval between groove regions120in the semiconductor light emitting device which is the measurement target is 225 nm, the amount of warpage where the width of the n-side clad layer shown inFIG. 6is plotted at a point of 225 nm corresponds to the amount of warpage of a semiconductor light emitting device without formation of groove regions120(that is, the semiconductor light emitting device of the conventional technique). When the amount of warpage of the semiconductor light emitting device without formation of groove regions120as described above is compared with the amount of warpage of the semiconductor light emitting device in which groove regions120are formed to reduce the width of the n-side clad layer, it has been confirmed that the amount of warpage is non-linearly lowered relative to the width of the n-side clad layer.

It has been confirmed that as shown inFIG. 6, the width of the n-side clad layer is set less than or equal to about 200 μm and that thus the amount of warpage can be reduced. In the present embodiment, it is said that since the length of the resonator is 2 mm, when the ratio of the length of the resonator to the width of the n-side clad layer (that is, the width of semiconductor multilayer109in a direction perpendicular to the direction of resonance and the stacking direction) is greater than or equal to 10, it is possible to reduce the amount of warpage.

Since it is predicted from the conventional technique that the amount of warpage is linearly changed, the result of the measurement shown inFIG. 6indicates that distortion was reduced in semiconductor light emitting device100according to the present disclosure more than in the semiconductor light emitting device of the conventional technique.

The state of stress of semiconductor multilayer109was evaluated from the amounts of shift of peak positions in the Raman spectra shown inFIGS. 7A and 7B. InFIG. 7B, the Raman peak positions of substrate110, n-side clad layer111, and active layer112are represented by a circle, a triangle, and a square, respectively.

When the Raman spectrum in the center of the ridge in the stacking direction (the center of the ridge in second direction D2) was measured, it was confirmed that as shown inFIGS. 7A and 7B(in particular,FIG. 7B), as the groove ratio (DE ratio) was increased, the Raman peak position of n-side clad layer111was shifted to the side of a larger number of waves. This indicates that tensile stress (distortion) received by n-side clad layer111was reduced. Hence, it was confirmed that the lattice constant of n-side clad layer111was decreased, that thus a lattice mismatch between n-side clad layer111and substrate110was reduced, and that consequently, distortion which caused warpage was reduced. It was also confirmed that a dislocation occurring in an interface between substrate110and n-side clad layer111(that is, the interface between substrate110and semiconductor multilayer109) was suppressed to, for example, 107cm−2or less.

It has been confirmed by the experiments described above that even when the width of groove region120is reduced as compared with the conventional technique, the warpage of the semiconductor light emitting device is sufficiently reduced.

As described above, in semiconductor light emitting device100according to the present embodiment, it is possible to realize a laser chip in which the width of groove region120is narrow and in which warpage is reduced. For example, when the DE ratio is greater than or equal to 10%, the warpage of semiconductor light emitting device100can be reduced. When the DE ratio is greater than or equal to 20%, the warpage of semiconductor light emitting device100can be more reduced. When the DE ratio is greater than or equal to 30%, tensile stress received by n-side clad layer111can be almost completely alleviated, and thus the warpage of semiconductor light emitting device100can be further reduced. In semiconductor light emitting device100as described above, even when junction-down mounting is performed, since the width of groove region120is narrow, the occurrence of a void in groove region120can be suppressed. Hence, a laser chip in which the heat dissipation property and laser properties thereof are satisfactory can be realized.

Manufacturing Method

A method of manufacturing semiconductor light emitting device100according to the present embodiment will then be described with reference toFIGS. 8A to 8E.FIGS. 8A to 8Eare schematic cross-sectional views showing steps in the method of manufacturing semiconductor light emitting device100according to the present embodiment. InFIGS. 8A to 8E, cross sections in the same position as inFIG. 2are shown.

Semiconductor light emitting device100according to the present embodiment is manufactured through steps (a) to (f) described below.

(a) As shown inFIG. 8A, a crystal growth technique such as metal-organic chemical vapor deposition (MOCVD) is first used to stack n-side clad layer111, active layer112, and p-side clad layer113on substrate110in this order. In this way, semiconductor multilayer109is stacked on substrate110.

(b) Then, as shown inFIG. 8B, a dry etching technique is used to produce grooves121for forming ridges. In this way, the ridge is formed between two grooves121.

(c) Then, as shown inFIG. 8C, the dry etching technique is used to form groove region120between two adjacent ridges.

(d) Then, as shown inFIG. 8D, photolithography and a vacuum deposition technique are used to form p electrodes114on the ridges. Although not shown in the figure, regions other than p electrodes114are covered with a current block layer including a dielectric. Furthermore, although not shown in the figure, a p-side pad electrode is formed on p electrodes114and the current block layer.

(e) Then, as shown inFIG. 8E, the photolithography and the vacuum deposition technique are used to form n electrode116on the back surface (lower surface inFIG. 8E) of substrate110.

(f) Then, semiconductor light emitting device100is cut out by cleavage or dicing. In other words, a plurality of semiconductor light emitting devices100formed on a wafer are formed into pieces.

A semiconductor light emitting device according to embodiment 2 will then be described. The semiconductor light emitting device according to the present embodiment differs from semiconductor light emitting device100according to embodiment 1 in the configuration of the groove region. The semiconductor light emitting device according to the present embodiment will be described below mainly on differences from semiconductor light emitting device100according to embodiment 1.

Configuration

The configuration of the semiconductor light emitting device according to the present embodiment will first be described with reference toFIGS. 9 and 10.FIGS. 9 and 10are respectively a schematic top view and a schematic cross-sectional view of semiconductor light emitting device200according to the present embodiment.FIG. 10shows a cross section taken along line X-X inFIG. 9.

Semiconductor light emitting device200is a laser chip including a GaN-based material and the like, and includes, as shown inFIG. 10, substrate210and semiconductor multilayers209stacked on substrate210. In the present embodiment, semiconductor light emitting device200further includes p electrodes214and n electrode216. Although not shown in the figure, semiconductor light emitting device200further includes, as with semiconductor light emitting device100according to embodiment 1, a p-side pad electrode and a current block layer.

Semiconductor multilayer209includes n-side clad layer211which is stacked above substrate210, active layer212which is stacked above n-side clad layer211, and p-side clad layer213which is stacked above active layer212.

Semiconductor light emitting device200includes a plurality of p electrodes214arranged on p-side clad layer213. A current is injected between p electrodes214and n electrode216provided on the back surface of substrate210.

Semiconductor light emitting device200includes one or more resonators. In the present embodiment, semiconductor light emitting device200is a laser array which includes a plurality of resonators. In the regions of p-side clad layer213located on the sides of p electrode214, a pair of grooves221are provided which extend parallel to the direction of resonance. In this way, in p-side clad layer213of semiconductor multilayer209, a ridge for confining the light and the current can be formed.

In the present embodiment, semiconductor light emitting device200includes one or more groove regions which are arranged above substrate210and which extend parallel to the direction of resonance. When semiconductor light emitting device200includes a plurality of semiconductor multilayers209, between one semiconductor multilayer209and other semiconductor multilayers209, the groove region deeper than groove221for forming the ridge is formed. In the present embodiment, semiconductor light emitting device200includes, for example, three groove regions220a,220b,and220cbetween two adjacent resonators. In other words, semiconductor light emitting device200has a concavo-convex structure which includes a plurality of groove regions220a,220b,and220cbetween two adjacent resonators. For example, in semiconductor light emitting device200, the number of semiconductor multilayers209may be less than the number of groove regions.

When in the present embodiment, the direction of tilt in a first plane included in n-side clad layer211and the direction of tilt in a second plane included in substrate210are assumed to be a direction which is tilted at 60 degrees or 120 degrees relative to the direction of resonance, as in embodiment 1, the relationship represented by formulae (1) and (2) or the relationship represented by formula (3) is established.

In the present embodiment, the depth of each of groove regions220a,220b,and220creaches substrate210. The depth of each of groove regions220a,220b,and220cis, for example, 4 μm from the surface of semiconductor light emitting device200. Although the width of each of groove regions220a,220b,and220cis not particularly limited, the width is, for example, 30 μm. Each of an interval between groove region220aand groove region220band an interval between groove region220band groove region220cis, for example, 30 μm. In other words, the width of the concavo-convex structure (the width in second direction D2) including the three groove regions is 150 μm.

An example of the configuration of semiconductor light emitting device200according to the present embodiment is shown in table 2.

Effects

Effects of semiconductor light emitting device200according to the present embodiment will then be described. Since in semiconductor light emitting device200according to the present embodiment, it is possible to reduce distortion, in the direction of tilt, of n-side clad layer211adjacent in second direction D2to a plurality of groove regions, the warpage of semiconductor light emitting device200in a direction perpendicular to the direction of resonance can be reduced while the volume of n-side clad layer211in the concavo-convex structure is being increased.

Consequently, even when junction-down mounting is performed, the occurrence of a void in each of the groove regions can be suppressed, and thus a laser chip in which the heat dissipation property and laser properties thereof are satisfactory can be realized.

Manufacturing Method

A method of manufacturing semiconductor light emitting device200according to the present embodiment is the same as the method of manufacturing semiconductor light emitting device100according to embodiment 1.

A semiconductor light emitting device according to embodiment 3 will be described. The semiconductor light emitting device according to the present embodiment differs from semiconductor light emitting device100according to embodiment 1 in that a smaller number of groove regions are provided. The semiconductor light emitting device according to the present embodiment will be described below mainly on differences from semiconductor light emitting device100according to embodiment 1.

Configuration

The configuration of the semiconductor light emitting device according to the present embodiment will first be described with reference toFIGS. 11 and 12.FIGS. 11 and 12are respectively a schematic top view and a schematic cross-sectional view of semiconductor light emitting device300according to the present embodiment.FIG. 12shows a cross section taken along line XII-XII inFIG. 11.

Semiconductor light emitting device300is a laser chip including a GaN-based material and the like, and includes, as shown inFIG. 12, substrate310and semiconductor multilayers309stacked on substrate310. In the present embodiment, semiconductor light emitting device300further includes p electrodes314and n electrode316. Although not shown in the figure, semiconductor light emitting device300further includes, as with semiconductor light emitting device100according to embodiment 1, a p-side pad electrode and a current block layer. Semiconductor multilayer309includes n-side clad layer311which is stacked above substrate310, active layer312which is stacked above n-side clad layer311, and p-side clad layer313which is stacked above active layer312.

Semiconductor light emitting device300includes a plurality of p electrodes314arranged on p-side clad layer313. A current is injected between p electrodes314and n electrode316provided on the back surface of substrate310.

Semiconductor light emitting device300includes one or more resonators. In the present embodiment, semiconductor light emitting device300is a laser array which includes a plurality of resonators. In the regions of p-side clad layer313located on the sides of p electrode314, a pair of grooves321are provided which extend parallel to the direction of resonance. In this way, in p-side clad layer313of semiconductor multilayer309, a ridge for confining the light and the current can be formed.

In the present embodiment, semiconductor light emitting device300includes one or more groove regions320which are arranged above substrate310and which extend parallel to the direction of resonance. When semiconductor light emitting device300includes a plurality of semiconductor multilayers309, between one semiconductor multilayer309and other semiconductor multilayers309, groove region320deeper than groove321for forming the ridge is formed. In the present embodiment, as shown inFIG. 11, between two p electrodes314adjacent in second direction D2, groove region320is not necessarily formed. In other words, the number of groove regions320in the present embodiment is less than the number of resonators. Preferably, for example, groove region320is formed on at least one of the sides (second direction D2) of the resonator.

When in semiconductor light emitting device300according to the present embodiment, the direction of tilt in a first plane included in n-side clad layer311and the direction of tilt in a second plane included in substrate310are assumed to be a direction which is tilted at 60 degrees or 120 degrees relative to the direction of resonance, as in embodiment 1, the relationship represented by formulae (1) and (2) or the relationship represented by formula (3) is established.

An example of the configuration of the semiconductor light emitting device according to the present embodiment is shown in table 3.

Effects

Effects of semiconductor light emitting device300according to the present embodiment will then be described. Since in semiconductor light emitting device300according to the present embodiment, it is possible to reduce distortion, in a direction perpendicular to the direction of resonance, of n-side clad layer311sandwiched between two adjacent groove regions320, the warpage of semiconductor light emitting device300in the direction perpendicular to the direction of resonance can be reduced while the volume of n-side clad layer311included in semiconductor light emitting device300is being increased.

Consequently, even when junction-down mounting is performed, the occurrence of a void in groove region320can be suppressed, and thus a laser chip in which the heat dissipation property and laser properties thereof are satisfactory can be realized.

Manufacturing Method

A method of manufacturing semiconductor light emitting device300according to the present embodiment is the same as the method of manufacturing semiconductor light emitting device100according to embodiment 1.

A semiconductor light emitting device according to embodiment 4 will be described. The semiconductor light emitting device according to the present embodiment differs from semiconductor light emitting device100according to embodiment 1 in the inclusion of a single resonator and the composition of the active layer. The semiconductor light emitting device according to the present embodiment will be described below mainly on differences from semiconductor light emitting device100according to embodiment 1.

Configuration

The configuration of the semiconductor light emitting device according to the present embodiment will first be described with reference toFIGS. 13 and 14.FIGS. 13 and 14are respectively a schematic top view and a schematic cross-sectional view of semiconductor light emitting device400according to the present embodiment.FIG. 14shows a cross section taken along line XIV-XIV inFIG. 13.

Semiconductor light emitting device400is a laser chip including a GaN-based material and the like, and includes, as shown inFIG. 14, substrate410and semiconductor multilayer409stacked on substrate410. In the present embodiment, semiconductor light emitting device400further includes p electrode414and n electrode416. Although not shown in the figure, semiconductor light emitting device400further includes, as with semiconductor light emitting device100according to embodiment 1, a p-side pad electrode and a current block layer. Semiconductor multilayer409includes n-side clad layer411which is stacked above substrate410, active layer412which is stacked above n-side clad layer411, and p-side clad layer413which is stacked above active layer412. In the present embodiment, semiconductor light emitting device400includes single p electrode414arranged on p-side clad layer413. A current is injected between p electrode414and n electrode416provided on the back surface of substrate410.

Active layer412in the present embodiment includes at least Al. Active layer412has a quantum well structure, and the composition of each of a well layer and a barrier layer is represented by AlxInyGaN (0≤x,y). The band gap of active layer412is larger than the band gap of GaN and is smaller than the band gap of each of n-side clad layer411and p-side clad layer413. Active layer412is a quantum well active layer in which the well layer including AlxInyGaN (0≤x,y) and the barrier layer including AlxInyGaN (0≤x,y) are alternately stacked, and includes, for example, two well layers. For example, the well layer includes Al0.06GaN, and the barrier layer includes Al0.10GaN. The number of well layers is not limited to two, and may be one or three or more.

As described above, semiconductor light emitting device400according to the present embodiment is a single emitter laser chip which includes a single resonator. In the regions of p-side clad layer413located on the sides of p electrode414, a pair of grooves421are provided which extend parallel to the direction of resonance. In this way, in p-side clad layer413, a ridge for confining the light and the current can be formed.

Semiconductor light emitting device400includes one or more groove regions420which are arranged above substrate410and which extend parallel to the direction of resonance. In the present embodiment, at least one or more groove regions420are provided outside grooves421for forming the ridge in second direction D2. Groove region420is not necessarily limited to part which is sandwiched between a pair of side walls and which has a concave shape, and groove region420may be part which has a step-shaped (or staircase-shaped) cross-sectional view as shown inFIG. 14. Groove region420may reach substrate410. The depth of groove region420is, for example, 2 μm from the surface of semiconductor light emitting device400. Although the width of groove region420is not particularly limited, the width is, for example, 50 μm.

When in semiconductor light emitting device400according to the present embodiment having the configuration as described above, the direction of tilt in a first plane included in n-side clad layer411and the direction of tilt in a second plane included in substrate410are assumed to be a direction which is tilted at 60 degrees or 120 degrees relative to the direction of resonance, as in embodiment 1, the relationship represented by formulae (1) and (2) or the relationship represented by formula (3) is established.

An example of the configuration of semiconductor light emitting device400according to the present embodiment is shown in table 4.

Effects

Effects of semiconductor light emitting device400according to the present embodiment will then be described with reference toFIGS. 15A and 15B.FIGS. 15A and 15Bare respectively a diagram schematically showing a relationship between the energy band structure of the semiconductor light emitting device of the conventional technique and the distortion of an active layer and a diagram schematically showing a relationship between the energy band structure of the semiconductor light emitting device according to the present embodiment and the distortion of the active layer. InFIGS. 15A and 15B, the energy levels of a conduction band and a valence band are represented by Ec and Ev, respectively.

The semiconductor light emitting device of the conventional technique differs from semiconductor light emitting device400according to the present embodiment in that no groove region is formed, and is the same as semiconductor light emitting device400in the other respects.

The active layer in the semiconductor light emitting device of the conventional technique has a lattice mismatch for a substrate. Hence, the active layer is in a state where tensile distortion is applied thereto. Therefore, an electric field caused by the distortion is generated inside the active layer. Consequently, as shown inFIG. 15A, the gradient of an energy band structure is steep, and thus electrons and holes are spatially isolated. Hence, the overlap integral of the wave function of electrons and holes is decreased, and thus recombination efficiency is lowered. The efficiency of light emission of the semiconductor light emitting device is lowered accordingly.

On the other hand, in semiconductor light emitting device400according to the present embodiment, the lattice constant of n-side clad layer411in the direction of tilt is decreased, and thus tensile distortion applied to active layer412is less than the tensile distortion in the conventional technique. Hence, the electric field caused by the internal distortion is reduced. Consequently, the overlap integral of the wave function of electrons and holes is increased, and thus recombination efficiency is increased. Therefore, the efficiency of light emission of semiconductor light emitting device400is enhanced.

Since in the present embodiment, it is possible to reduce distortion, in a direction perpendicular to the direction of resonance, of n-side clad layer411sandwiched between two groove regions420, the warpage of semiconductor light emitting device400in the direction perpendicular to the direction of resonance can be reduced while the volume of n-side clad layer411included in semiconductor light emitting device400is being increased.

Consequently, even when junction-down mounting is performed, the occurrence of a void in groove region420can be suppressed, and thus a laser chip in which the heat dissipation property and laser properties thereof are satisfactory can be realized.

Manufacturing Method

A method of manufacturing semiconductor light emitting device400according to the present embodiment is the same as the method of manufacturing semiconductor light emitting device100according to embodiment 1.

A semiconductor light emitting device according to embodiment 5 will be described. The semiconductor light emitting device according to the present embodiment differs from semiconductor light emitting device400according to embodiment 4 in the composition of the active layer and the shape of the groove region. The semiconductor light emitting device according to the present embodiment will be described below mainly on differences from semiconductor light emitting device400according to embodiment 4.

Configuration

The configuration of the semiconductor light emitting device according to the present embodiment will first be described with reference toFIGS. 16 and 17.FIGS. 16 and 17are respectively a schematic top view and a schematic cross-sectional view of semiconductor light emitting device500according to the present embodiment.FIG. 17shows a cross section taken along line XVII-XVII inFIG. 16.

Semiconductor light emitting device500is a laser chip including a GaN-based material and the like, and includes, as shown inFIG. 17, substrate510and semiconductor multilayers509stacked on substrate510. In the present embodiment, semiconductor light emitting device500further includes p electrode514and n electrode516. Although not shown in the figure, semiconductor light emitting device500further includes, as with semiconductor light emitting device100according to embodiment 1, a p-side pad electrode and a current block layer. Semiconductor multilayer509includes n-side clad layer511which is stacked above substrate510, active layer512which is stacked above n-side clad layer511, and p-side clad layer513which is stacked above active layer512. In the present embodiment, semiconductor light emitting device500includes single p electrode514arranged on p-side clad layer513. A current is injected between p electrode514and n electrode516provided on the back surface of substrate510.

Unlike active layer412in embodiment 4, active layer512in the present embodiment does not include Al. For example, active layer512has the same configuration as active layer112in embodiment 1 or the like.

Semiconductor light emitting device500according to the present embodiment is a single emitter laser chip which includes a single resonator. In the regions of p-side clad layer513located on the sides of p electrode514, a pair of grooves521are provided which extend parallel to the direction of resonance. In this way, in p-side clad layer513, a ridge for confining the light and the current can be formed.

Semiconductor light emitting device500includes one or more groove regions520which are arranged above substrate510and which extend parallel to the direction of resonance. In the present embodiment, at least one or more groove regions520are provided outside grooves521for forming the ridge in second direction D2. The width of groove region520in the present embodiment in second direction D2is less than the width of groove region420in embodiment 4 in second direction D2, and semiconductor multilayers509are arranged not only inside but also outside groove regions420in second direction D2.

Groove region520may reach substrate510, and is deeper than at least active layer512to reach n-side clad layer511. The depth of groove region520is, for example, 4 μm from the surface of semiconductor light emitting device500. Although the width of groove region520is not particularly limited, the width is, for example, 30 μm.

When in semiconductor light emitting device500according to the present embodiment having the configuration as described above, the direction of tilt in a first plane included in n-side clad layer511and the direction of tilt in a second plane included in substrate510are assumed to be a direction which is tilted at 60 degrees or 120 degrees relative to the direction of resonance, as in embodiment 1, the relationship represented by formulae (1) and (2) or the relationship represented by formula (3) is established.

An example of the configuration of semiconductor light emitting device500according to the present embodiment is shown in table 5.

Effects

Effects of semiconductor light emitting device500according to the present embodiment will then be described. Since in semiconductor light emitting device500according to the present embodiment, it is possible to reduce distortion, in a direction perpendicular to the direction of resonance, of n-side clad layer511sandwiched between two groove regions520, the warpage of semiconductor light emitting device500in the direction perpendicular to the direction of resonance can be reduced while the volume of n-side clad layer511included in semiconductor light emitting device500is being increased.

Consequently, even when junction-down mounting is performed, the occurrence of a void in groove region520can be suppressed, and thus a laser chip in which the heat dissipation property and laser properties thereof are satisfactory can be realized.

If groove region520reaches an end of semiconductor light emitting device500in second direction D2, when junction-down mounting is performed, semiconductor light emitting device500is easily tilted, with the result that yield in the mounting is lowered. On the other hand, since in the present embodiment, semiconductor multilayers509are arranged at the ends of semiconductor light emitting device500in second direction D2, semiconductor light emitting device500can be supported at two or more places at the time of junction-down mounting, with the result that it is possible to reduce the tilt of semiconductor light emitting device500at the time of junction-down mounting. Hence, the yield in the mounting can be enhanced.

Manufacturing Method

A method of manufacturing semiconductor light emitting device500according to the present embodiment is the same as the method of manufacturing semiconductor light emitting device100according to embodiment 1.

A semiconductor light emitting device according to embodiment 6 will be described. The semiconductor light emitting device according to the present embodiment differs from semiconductor light emitting device100according to embodiment 1 in the shape of the groove region. The semiconductor light emitting device according to the present embodiment will be described below mainly on differences from semiconductor light emitting device100according to embodiment 1.

Configuration

The configuration of the semiconductor light emitting device according to the present embodiment will first be described with reference toFIGS. 18 and 19.FIGS. 18 and 19are respectively a schematic top view and a schematic cross-sectional view of semiconductor light emitting device600according to the present embodiment.FIG. 19shows a cross section taken along line XIX-XIX inFIG. 18.

Semiconductor light emitting device600is a laser chip including a GaN-based material and the like, and includes, as shown inFIG. 19, substrate610and semiconductor multilayers609stacked on substrate610. In the present embodiment, semiconductor light emitting device600further includes p electrodes614and n electrode616. Although not shown in the figure, semiconductor light emitting device600further includes, as with semiconductor light emitting device100according to embodiment 1, a p-side pad electrode and a current block layer. Semiconductor multilayer609includes n-side clad layer611which is stacked above substrate610, active layer612which is stacked above n-side clad layer611, and p-side clad layer613which is stacked above active layer612. In the present embodiment, semiconductor light emitting device600includes a plurality of p electrodes614arranged on p-side clad layers613. A current is injected between p electrodes614and n electrode616provided on the back surface of substrate610.

Semiconductor light emitting device600includes one or more resonators. In the present embodiment, semiconductor light emitting device600is a laser array which includes a plurality of resonators. In the regions of p-side clad layer613located on the sides of p electrode614, a pair of grooves621are provided which extend parallel to the direction of resonance. In this way, in p-side clad layer613of semiconductor multilayer609, a ridge for confining the light and the current can be formed.

In the present embodiment, semiconductor light emitting device600includes one or more groove regions620which are arranged above substrate610and which extend parallel to the direction of resonance. When semiconductor light emitting device600includes a plurality of semiconductor multilayers, between one semiconductor multilayer609and other semiconductor multilayers609, groove region620deeper than groove621for forming the ridge is formed. The depth of groove region620may reach substrate610. For example, the depth of groove region620is 4 μm from the surface of semiconductor light emitting device600. The shape of groove region620may be such a tapered shape that as the groove deepens, the width is decreased toward the end in the cross section shown inFIG. 19. Although the width of groove region620is not particularly limited, the width is, for example, 100 μm at the narrowest part.

When in semiconductor light emitting device600according to the present embodiment, the direction of tilt in a first plane included in n-side clad layer611and the direction of tilt in a second plane included in substrate610are assumed to be a direction which is tilted at60° or120° relative to the direction of resonance, as in embodiment 1, the relationship represented by formulae (1) and (2) or the relationship represented by formula (3) is established.

An example of the configuration of semiconductor light emitting device600according to the present embodiment is shown in table 6.

Effects

Effects of semiconductor light emitting device600according to the present embodiment will then be described. Since in semiconductor light emitting device600according to the present embodiment, it is possible to reduce distortion, in a direction perpendicular to the direction of resonance, of n-side clad layer611sandwiched between two groove regions620, the warpage of semiconductor light emitting device600in the direction perpendicular to the direction of resonance can be reduced while the volume of n-side clad layer611included in semiconductor light emitting device600is being increased.

Consequently, even when junction-down mounting is performed, the occurrence of a void in groove region620can be suppressed, and thus a laser chip in which the heat dissipation property and laser properties thereof are satisfactory can be realized.

In the present embodiment, groove region620has the tapered shape, and thus the side walls of groove region620are tilted, with the result that the rate of coverage at the time of film formation of the current block layer and the p-side pad electrode is increased. Consequently, a leak through a step disconnection can be reduced, and thus a highly reliable laser chip can be realized.

Manufacturing Method

A method of manufacturing semiconductor light emitting device600according to the present embodiment is the same as the method of manufacturing semiconductor light emitting device100according to embodiment 1.

A semiconductor light emitting device according to embodiment 7 will be described. The semiconductor light emitting device according to the present embodiment differs from semiconductor light emitting device100according to embodiment 1 in the depth of the groove region. The semiconductor light emitting device according to the present embodiment will be described below mainly on differences from semiconductor light emitting device100according to embodiment 1.

Configuration

The configuration of the semiconductor light emitting device according to the present embodiment will first be described with reference toFIGS. 20 and 21.FIGS. 20 and 21are respectively a schematic top view and a schematic cross-sectional view of semiconductor light emitting device700according to the present embodiment.FIG. 21shows a cross section taken along line XXI-XXI inFIG. 20.

Semiconductor light emitting device700is a laser chip including a GaN-based material and the like, and includes, as shown inFIG. 21, substrate710and semiconductor multilayers709stacked on substrate710. In the present embodiment, semiconductor light emitting device700further includes p electrodes714and n electrode716. Although not shown in the figure, semiconductor light emitting device700further includes, as with semiconductor light emitting device100according to embodiment 1, a p-side pad electrode and a current block layer. Semiconductor multilayer709includes n-side clad layer711which is stacked above substrate710, active layer712which is stacked above n-side clad layer711, and p-side clad layer713which is stacked above active layer712. In the present embodiment, semiconductor light emitting device700includes a plurality of p electrodes714arranged on p-side clad layers713. A current is injected between p electrodes714and n electrode716provided on the back surface of substrate710.

Semiconductor light emitting device700includes one or more resonators. In the present embodiment, semiconductor light emitting device700is a laser array which includes a plurality of resonators. In the regions of p-side clad layer713located on the sides of p electrode714, a pair of grooves721are provided which extend parallel to the direction of resonance. In this way, in p-side clad layer713of semiconductor multilayer709, a ridge for confining the light and the current can be formed.

In the present embodiment, semiconductor light emitting device700includes one or more groove regions720which are arranged above substrate710and which extend parallel to the direction of resonance. When semiconductor light emitting device700includes a plurality of p electrodes714, between one p electrode714and other p electrodes714, at least one groove region720deeper than groove721for forming the ridge is formed. In the present embodiment, groove region720reaches n-side clad layer711but does not reach substrate710. The depth of groove region720is not particularly limited as long as the depth of groove region720reaches n-side clad layer711but does not reach substrate710. For example, the depth of groove region720is 3 μm from the surface of semiconductor light emitting device700. Although the width of groove region720is not particularly limited, the width is, for example, 100 μm.

When in semiconductor light emitting device700according to the present embodiment, the direction of tilt in a first plane included in n-side clad layer711and the direction of tilt in a second plane included in substrate710are assumed to be a direction which is tilted at 60 degrees or 120 degrees relative to the direction of resonance, as in embodiment 1, the relationship represented by formulae (1) and (2) or the relationship represented by formula (3) is established.

An example of the configuration of semiconductor light emitting device700according to the present embodiment is shown in table 7.

Effects

Effects of semiconductor light emitting device700according to the present embodiment will then be described. Since in semiconductor light emitting device700according to the present embodiment, it is possible to reduce distortion, in a direction perpendicular to the direction of resonance, of n-side clad layer711sandwiched between two groove regions720, the warpage of semiconductor light emitting device700in the direction perpendicular to the direction of resonance can be reduced while the volume of n-side clad layer711included in semiconductor light emitting device700is being increased.

Consequently, even when junction-down mounting is performed, the occurrence of a void in groove region720can be suppressed, and thus a laser chip in which the heat dissipation property and laser properties thereof are satisfactory can be realized.

Since in the present embodiment, n-side clad layer711is not separated by groove region720, it is possible to suppress abnormal cleavage at ends where n-side clad layer711is separated when cleavage for forming the end surfaces of the resonators is performed. Hence, in the present embodiment, a highly reliable laser chip can be realized.

Manufacturing Method

A method of manufacturing semiconductor light emitting device700according to the present embodiment is the same as the method of manufacturing semiconductor light emitting device100according to embodiment 1.

A semiconductor light emitting device according to embodiment 8 will be described. The semiconductor light emitting device according to the present embodiment differs from semiconductor light emitting device100according to embodiment 1 in the shape of the groove region. The semiconductor light emitting device according to the present embodiment will be described below mainly on differences from semiconductor light emitting device100according to embodiment 1.

Configuration

The configuration of the semiconductor light emitting device according to the present embodiment will first be described with reference toFIGS. 22 and 23.FIGS. 23 and 23are respectively a schematic top view and a schematic cross-sectional view of semiconductor light emitting device800according to the present embodiment.FIG. 23shows a cross section taken along line XXIII-XXIII inFIG. 23.

Semiconductor light emitting device800is a laser chip including a GaN-based material and the like, and includes, as shown inFIG. 23, substrate810and semiconductor multilayers809stacked on substrate810. In the present embodiment, semiconductor light emitting device800further includes p electrodes814and n electrode816. Although not shown in the figure, semiconductor light emitting device800further includes, as with semiconductor light emitting device100according to embodiment 1, a p-side pad electrode and a current block layer. Semiconductor multilayer809includes n-side clad layer811which is stacked above substrate810, active layer812which is stacked above n-side clad layer811, and p-side clad layer813which is stacked above active layer812. In the present embodiment, semiconductor light emitting device800includes a plurality of p electrodes814arranged on p-side clad layers813. A current is injected between p electrodes814and n electrode816provided on the back surface of substrate810.

Semiconductor light emitting device800includes one or more resonators. In the present embodiment, semiconductor light emitting device800is a laser array which includes a plurality of resonators. In the regions of p-side clad layer813located on the sides of p electrode814, a pair of grooves821are provided which extend parallel to the direction of resonance. In this way, in p-side clad layer813of semiconductor multilayer809, a ridge for confining the light and the current can be formed.

In the present embodiment, semiconductor light emitting device800includes one or more groove regions820which are arranged above substrate810and which extend parallel to the direction of resonance. When semiconductor light emitting device800includes a plurality of semiconductor multilayers809, between one semiconductor multilayer809and other semiconductor multilayers809, at least one groove region820deeper than groove821for forming the ridge is formed.

In the present embodiment, groove region820has a two-step shape, that is, a staircase shape of two steps. As shown inFIG. 23, a groove in the first step of groove region820reaches n-side clad layer811, and a groove in the second step reaches substrate810.

Although the depth of the groove in the first step of groove region820is not particularly limited as long as the depth reaches n-side clad layer811, the depth is, for example, 3 μm from the surface of semiconductor light emitting device800. Although the width of the groove in the first step of groove region820is not particularly limited, the width is, for example, 100 μm.

Although the depth of the groove in the second step of groove region820is not particularly limited as long as the depth reaches substrate810, the depth is, for example, 4 μm from the surface of semiconductor light emitting device800. Although the width of the groove in the second step of groove region820is not particularly limited, the width is, for example, 2 μm.

Although in the present embodiment, groove region820has the two-step shape, groove region820may have a staircase shape of three or more steps, that is, a multistep shape of three or more steps.

When in semiconductor light emitting device800according to the present embodiment, the direction of tilt in a first plane included in n-side clad layer811and the direction of tilt in a second plane included in substrate810are assumed to be a direction which is tilted at 60 degrees or 120 degrees relative to the direction of resonance, as in embodiment 1, the relationship represented by formulae (1) and (2) or the relationship represented by formula (3) is established.

An example of the configuration of semiconductor light emitting device800according to the present embodiment is shown in table 8.

Effects

Effects of semiconductor light emitting device800according to the present embodiment will then be described. Since in semiconductor light emitting device800according to the present embodiment, it is possible to reduce distortion, in a direction perpendicular to the direction of resonance, of n-side clad layer811sandwiched between two groove regions820, the warpage of semiconductor light emitting device800in the direction perpendicular to the direction of resonance can be reduced while the volume of n-side clad layer811included in semiconductor light emitting device800is being increased.

Consequently, even when junction-down mounting is performed, the occurrence of a void in groove region820can be suppressed, and thus a laser chip in which the heat dissipation property and laser properties thereof are satisfactory can be realized.

In the present embodiment, groove region820has the two-step shape. Since groove region820in the present embodiment has a staircase shape as described above, as compared with the single-step groove region, the rate of coverage at the time of film formation of the current block layer and the p-side pad electrode is increased. Consequently, a leak through a step disconnection can be reduced, and thus a highly reliable laser chip can be realized.

Manufacturing Method

A method of manufacturing semiconductor light emitting device800according to the present embodiment is the same as the method of manufacturing semiconductor light emitting device100according to embodiment 1.

A semiconductor light emitting device according to embodiment 9 will be described. In the present embodiment, examples of the configurations of a p-side pad electrode and an n electrode in the semiconductor light emitting device will be described. The semiconductor light emitting device according to the present embodiment will be described below mainly on the configurations of the p-side pad electrode and the n electrode.

Configuration

The configuration of the semiconductor light emitting device according to the present embodiment will first be described with reference toFIGS. 24 to 29.FIGS. 24 to 26are schematic top views showing examples of the configuration of the p-side pad electrode in semiconductor light emitting device900according to the present embodiment. Top views (a) inFIGS. 24 to 26show top views of semiconductor light emitting device900before the p-side pad electrode is formed. Top views (b) inFIGS. 24 to 26show top views of semiconductor light emitting device900after the p-side pad electrode is formed.

FIGS. 27 to 29are schematic bottom views showing examples of the configuration of the n-side electrode in semiconductor light emitting device900according to the present embodiment. Bottom views (a) inFIGS. 27 to 29show bottom views of semiconductor light emitting device900before the n electrode is formed. Bottom views (b) inFIGS. 27 to 29show bottom views of semiconductor light emitting device900after the n electrode is formed.

Semiconductor light emitting device900according to the present embodiment is a laser chip including a GaN-based material, and includes substrate910and semiconductor multilayers. Substrate910and the semiconductor multilayer in the present embodiment respectively have the same configurations as substrate110and semiconductor multilayer109in embodiment 1. Semiconductor light emitting device900includes p electrodes914, the p-side pad electrode, and the n electrode. Although not shown in the figure, semiconductor light emitting device900further includes a current block layer as with semiconductor light emitting device100according to embodiment 1.

The semiconductor multilayer in the present embodiment includes an n-side clad layer (not shown inFIGS. 24 to 29) which is stacked above substrate910, an active layer (not shown inFIGS. 24 to 29) which is stacked above the n-side clad layer, and p-side clad layer913which is stacked above the active layer.

Semiconductor light emitting device900according to the present embodiment includes one or more groove regions920which are arranged above substrate910and which extend parallel to the direction of resonance. Groove region920has the same configuration as groove region120in embodiment 1.

In semiconductor light emitting device900as described above, for example, the configurations of the p-side pad electrode as shown in FIGS.24to26can be applied.

One p-side pad electrode915paas shown inFIG. 24which covers a substantially entire top surface of substrate910may be applied to semiconductor light emitting device900. As shown inFIG. 24, p-side pad electrode915pacovers substantially entire top surfaces of the semiconductor multilayers including the tops of p electrodes914and substantially entire surfaces of groove regions920. In other words, p-side pad electrode915pais continuously formed on all resonators and groove regions920. P-side pad electrode915pais an integral electrode which supplies a current to all the resonators.

P-side pad electrodes915pbas shown inFIG. 25which are arranged on the top surfaces of the resonators and which are equal in number to the resonators may be applied to semiconductor light emitting device900.

For example, p-side pad electrodes915pbequal in number to the resonators are separated from each other by groove regions920. For example, when semiconductor light emitting device900includes38resonators, semiconductor light emitting device900may include38p-side pad electrodes915pb.

A plurality of p-side pad electrodes915pcas shown inFIG. 26may be applied to semiconductor light emitting device900. Each of p-side pad electrodes915pcshown inFIG. 26collectively covers the top surfaces of a plurality of resonators. The p-side pad electrodes915pcare separated from each other by groove regions920. For example, each of p-side pad electrodes915pcmay collectively cover two resonators. For example, when semiconductor light emitting device900includes 38 resonators, semiconductor light emitting device900may include 19 p-side pad electrodes915pb.

In semiconductor light emitting device900according to the present embodiment, the configurations of various p-side pad electrodes as described above can be applied.

In semiconductor light emitting device900, for example, the configurations of n electrodes as shown inFIGS. 27 to 29can be applied.

One n electrode916na shown inFIG. 27which covers a substantially entire bottom surface of substrate910may be applied to semiconductor light emitting device900. N electrode916nais an integral electrode which supplies a current to a plurality of resonators.

N electrodes916nbas shown inFIG. 28which are arranged in positions corresponding to the resonators and which are equal in number to the resonators may be applied to semiconductor light emitting device900. N electrodes916nbequal in number to the resonators are separated from each other by regions of substrate910opposite the bottom of groove regions920. For example, when semiconductor light emitting device900includes38resonators, semiconductor light emitting device900may include38n electrodes916nb.

A plurality of n electrodes916ncas shown inFIG. 29may be applied to semiconductor light emitting device900. Each of n electrodes916ncshown inFIG. 29collectively covers the bottom surfaces of a plurality of resonators. N electrodes916ncare separated from each other by regions of substrate910opposite the bottom of groove regions920. Each of n electrodes916ncmay collectively cover two resonators. For example, when semiconductor light emitting device900includes38resonators, semiconductor light emitting device900may include 19 n electrodes916nb.

An example of the configuration of semiconductor light emitting device900according to the present embodiment is shown in table 9.

Effects

Effects of semiconductor light emitting device900according to the present embodiment will then be described. Since in semiconductor light emitting device900according to the present embodiment, it is possible to reduce distortion, in a direction perpendicular to the direction of resonance, of the n-side clad layer sandwiched between two groove regions920, the warpage of semiconductor light emitting device900in the direction perpendicular to the direction of resonance can be reduced while the volume of the n-side clad layer included in semiconductor light emitting device900is being increased.

Consequently, even when junction-down mounting is performed, the occurrence of a void in groove region820can be suppressed, and thus a laser chip in which the heat dissipation property and laser properties thereof are satisfactory can be realized.

In the present embodiment, a difference in thermal coefficient of expansion between the p-side pad electrode and the n electrode and substrate910is utilized, and thus it is possible to more accurately control the warpage.

When a plurality of semiconductor light emitting devices are manufactured on one wafer, the layout of the electrodes is changed inside a wafer surface, and thus it is possible to reduce variations in the equality of the substrate and the semiconductor multilayer.

Manufacturing Method

Although a method of manufacturing semiconductor light emitting device900according to the present embodiment is the same as the method of manufacturing semiconductor light emitting device100according to embodiment 1, temperature control may be performed at the time of film formation of the p-side pad electrode and the n electrode to more accurately control the warpage.

A semiconductor light emitting device according to embodiment 10 will be described. The semiconductor light emitting device according to the present embodiment differs from semiconductor light emitting device100according to embodiment 1 in that the semiconductor light emitting device is not a laser chip but a light emitting diode (LED). The semiconductor light emitting device according to the present embodiment will be described below mainly on differences from semiconductor light emitting device100according to embodiment 1.

Configuration

The configuration of the semiconductor light emitting device according to the present embodiment will first be described with reference toFIGS. 30 and 31.FIGS. 30 and 31are respectively a schematic top view and a schematic cross-sectional view of semiconductor light emitting device1000according to the present embodiment.FIG. 31shows a cross section taken along line XXXI-XXXI inFIG. 30.

Semiconductor light emitting device1000is a light emitting element including a GaN-based material and the like, and includes, as shown inFIG. 31, substrate1010and semiconductor multilayers1009stacked on substrate1010. In the present embodiment, semiconductor light emitting device1000further includes p electrodes1014and n electrode1016. Although not shown in the figure, semiconductor light emitting device1000further includes, as with semiconductor light emitting device100according to embodiment 1, a p-side pad electrode and a current block layer. Semiconductor multilayer1009includes n-side clad layer1011which is stacked above substrate1010, active layer1012which is stacked above n-side clad layer1011, and p-side clad layer1013which is stacked above active layer1012. In the present embodiment, semiconductor multilayer1009includes a gallium nitride-based semiconductor. Semiconductor light emitting device1000includes a plurality of p electrodes1014arranged on p-side clad layers1013. In the present embodiment, each of p electrodes1014is a transparent electrode including a transparent conductive film. On part of the top of p electrode1014, a wiring electrode (not shown) is provided. A current is injected between p electrodes1014and n electrode1016provided on the back surface of substrate1010.

Active layer1012includes AlxInyGaN (0≤x,y). In this way, active layer1012has a large band gap due to GaN. The band gap of active layer1012is smaller than the band gaps of n-side clad layer1011and p-side clad layer1013.

Semiconductor light emitting device100includes one or more groove regions1020arranged above substrate1010. In the present embodiment, as shown inFIG. 30, semiconductor light emitting device1000includes a plurality of groove regions1020. As shown inFIG. 31, each of groove regions1020may reach substrate1010. In this way, it is possible to reduce distortion resulting from a lattice mismatch between substrate1010and semiconductor multilayer1009.

Here, the crystal structure of n-side clad layer1011in the present embodiment will be described.

Semiconductor multilayer1009includes a first plane perpendicular to a stacking direction in which semiconductor multilayer1009is stacked. The first plane includes, inside the plane, a first orientation and a third orientation which is tilted relative to the first orientation. In the present embodiment, an orientation which is tilted at 60 degrees or 120 degrees relative to the first orientation inside the first plane is assumed to be the third orientation. In the present embodiment, n-side clad layer1011of semiconductor multilayer1009includes the first plane.

On the other hand, substrate1010includes a second plane perpendicular to the stacking direction. The second plane includes, inside the plane, a second orientation parallel to the first orientation and a fourth orientation which is tilted relative to the second orientation and which is parallel to the third orientation. In the present embodiment, an orientation which is tilted at 60 degrees or 120 degrees relative to the second orientation inside the second plane is assumed to be the fourth orientation.

First lattice constant dcm of n-side clad layer1011in the first orientation is equal to second lattice constant dsm of substrate1010in the second orientation. Here, a state where first lattice constant dcm is equal to second lattice constant dsm is not limited to a state where first lattice constant dcm is completely identical to second lattice constant dsm, and includes a state where they are substantially the same. For example, a state where a difference between lattice constant dsm and lattice constant dcm is less than or equal to 0.01% of lattice constant dsm or lattice constant dcm is also included in the state where lattice constant dsm is equal to lattice constant dcm.

Third lattice constant dca of n-side clad layer1011in the third orientation is less than fourth lattice constant dsa of substrate1010in the fourth orientation.

In other words, for the lattice constants described above, a relationship represented by formulae (4) and (5) below is established.

Instead of the relationship represented by formulae (4) and (5) above, a relationship represented by formula (6) below may be established.

Semiconductor multilayer1009is, for example, a GaN-based semiconductor. The first orientation is preferably any one of [1-100] orientation, [0-110] orientation, and [−1010] orientation. Preferably, the third orientation is any one of [1-100] orientation, [0-110] orientation, and [−1010] orientation and is one of two orientations having Miller indices different from the first orientation.

An example of the configuration of the semiconductor light emitting device according to the present embodiment is shown in table10.

Effects

Effects of semiconductor light emitting device1000according to the present embodiment will then be described.

Active layer1012in the present embodiment has a lattice mismatch for substrate1010as with active layer412in embodiment 4, and thus active layer1012is in a state where tensile distortion is applied thereto. Therefore, an electric field caused by the distortion is generated inside active layer1012. Consequently, the gradient of an energy band structure is steep, and thus electrons and holes are spatially isolated. Hence, the overlap integral of the wave function of electrons and holes is decreased, and thus recombination efficiency is lowered. The efficiency of light emission of the semiconductor light emitting device is lowered accordingly.

In the present embodiment, groove region1020is formed, and thus as described above, the lattice constant of n-side clad layer1011in the third orientation perpendicular to the stacking direction is decreased, with the result that the tensile distortion applied to active layer1012is decreased. Hence, the electric field caused by the internal distortion is reduced. Consequently, the overlap integral of the wave function of electrons and holes is increased, and thus recombination efficiency is increased. Therefore, the efficiency of light emission of semiconductor light emitting device1000is enhanced.

Manufacturing Method

A method of manufacturing semiconductor light emitting device1000according to the present embodiment is the same as the method of manufacturing semiconductor light emitting device100according to embodiment 1 except that the groove for forming the ridge is not formed and that p electrode1014includes the transparent conductive film.

Variations and the Like

Although the semiconductor light emitting device according to the present disclosure has been described above based on the embodiments, the present disclosure is not limited to the embodiments described above.

Embodiments obtained by performing various variations conceived by a person skilled in the art on the embodiments described above and embodiments realized by arbitrarily combining the constituent elements and the functions in the embodiments described above without departing from the spirit of the present disclosure are also included in the present disclosure.

For example, the p-side pad electrode and the n electrode in embodiment 9 may be applied to the semiconductor light emitting devices according to the other embodiments.

Although in the embodiments described above, as the semiconductor light emitting device, the examples of the laser chip and the LED are described, the semiconductor light emitting device according to the present disclosure is not limited to these examples. For example, the semiconductor light emitting device may be a super luminescent diode.

Although in the embodiments described above, the semiconductor multilayer includes the n-side clad layer, the active layer, and the p-side clad layer, a layer other than those may be inserted. For example, a buffer layer may be inserted between the substrate and the n-side clad layer or a light guide layer adjacent to the active layer may be inserted.

INDUSTRIAL APPLICABILITY

For example, the semiconductor light emitting device according to the present disclosure can be applied as a high-power and high-efficient light source to a processing device, an illumination device and the like.