Resistive random-access memory devices and methods of fabrication

A memory apparatus includes an interconnect in a first dielectric above a substrate and a structure above the interconnect, where the structure includes a diffusion barrier material and covers the interconnect. The memory apparatus further includes a resistive random-access memory (RRAM) device coupled to the interconnect. The RRAM device includes a first electrode on a portion of the structure, a stoichiometric layer having a metal and oxygen on the first electrode, a non-stoichiometric layer including the metal and oxygen on the stoichiometric layer. A second electrode including a barrier material is on the non-stoichiometric layer. In some embodiments, the RRAM device further includes a third electrode on the second electrode. To prevent uncontrolled oxidation during a fabrication process a spacer may be directly adjacent to the RRAM device, where the spacer includes a second dielectric.

BACKGROUND

For the past several decades, feature size reduction has been a key focus for industrial-scale semiconductor process development. Scaling to smaller dimensions enables a higher density of functional elements per chip, smaller chips, and also reduced cost. However, as the industry approaches the physical limits of traditional scaling, it is becoming increasingly important to look for non-traditional types of devices that can offer new functionality. One such example is non-volatile memory based on resistive random-access memory (RRAM) devices.

Non-volatile on-chip embedded memory with resistive random-access memory (RRAM) devices can improve energy and computational efficiency of a system on chip (SOC). However, the technical challenges of creating an appropriate stack for fabrication of RRAM devices with high device endurance present formidable roadblocks to commercialization of this technology. Specifically, endurance refers to long term repeated switching of an RRAM device between high and low resistance state with minimal variation in switching parameters. It is high desirable for a large number of individual RRAM devices to switch repeatedly within a given voltage and current range for functional embedded memory applications. As such, significant improvements are still needed in engineering material layer stacks for endurance improvement in RRAM devices.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

A resistive random-access memory (RRAM) device and methods of fabrication are described. In the following description, numerous specific details are set forth, such as structural schemes and detailed fabrication methods in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as transistor operations and switching operations associated with embedded memory, are described in lesser detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.

In some instances, in the following description, well-known methods and devices are shown in block diagram form, rather than in detail, to avoid obscuring the present disclosure. Reference throughout this specification to “an embodiment” or “one embodiment” or “some embodiments” means that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. Thus, the appearances of the phrase “in an embodiment” or “in one embodiment” or “some embodiments” in various places throughout this specification are not necessarily referring to the same embodiment of the disclosure. Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

The terms “over,” “under,” “between,” and “on” as used herein refer to a relative position of one component or material with respect to other components or materials where such physical relationships are noteworthy. For example, in the context of materials, one material or material disposed over or under another may be directly in contact or may have one or more intervening materials. Moreover, one material disposed between two materials may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first material “on” a second material is in direct contact with that second material/material. Similar distinctions are to be made in the context of component assemblies. As used throughout this description, and in the claims, a list of items joined by the term “at least one of” or “one or more of” can mean any combination of the listed terms.

Here, an in-plane magnet refers to a magnet that has magnetization in a direction substantially along the plane of the magnet. For example, a magnet with a magnetization which is in an x or y direction and is in a range of 0 (or 180 degrees)+/−20 degrees relative to an x-y plane of a device.

The term “free” or “unfixed” here with reference to a magnet refers to a magnet whose magnetization direction can change along its easy axis upon application of an external field or force (e.g., Oersted field, spin torque, etc.). Conversely, the term “fixed” or “pinned” here with reference to a magnet refers to a magnet whose magnetization direction is pinned or fixed along an axis and which may not change due to application of an external field (e.g., electrical field, Oersted field, spin torque).

As used throughout this description, and in the claims, a list of items joined by the term “at least one of” or “one or more of” can mean any combination of the listed terms. Unless otherwise specified in the explicit context of their use, the terms “substantially equal,” “about equal” and “approximately equal” mean that there is no more than incidental variation between two things so described. In the art, such variation is typically no more than +/−10% of a predetermined target value.

Integration of a memory array with low voltage logic circuitry, such as logic circuitry operational at a voltage less than or equal to 1 Volt, may be advantageous since it enables higher operation speeds compared to having physically separate logic and memory chips. Additionally, approaches to integrating an RRAM device with a transistor to create embedded memory presents material challenges that have become far more formidable with scaling. As transistor operating voltages are scaled down in an effort to become more energy efficient, RRAM memory devices that are connected in series with such transistors are also required to function at lower voltages and currents.

Non-volatile memory devices, such as resistive random-access memory (RRAM) devices, depend on a phenomenon of resistance switching to store information. The non-volatile memory device functions as a variable resistor where the resistance of the device may switch between a high resistance state and a low resistance state. Resistance switching relies on a change in conductivity of the RRAM device. In particular, a switching layer determines the conductivity. In one embodiment, the conductivity is modulated by formation and dissolution of a conductive filament in the switching layer.

The conductive filament may be created in an RRAM device by a one-time electro-forming process, where a voltage is applied between two electrodes located on either side of the switching layer. The electro-forming process may cause an electrical breakdown within the switching layer leading to a formation of the conductive filament. The electro-forming voltage depends on the material composition, thickness and quality of the switching layer and can dictate a size of the conductive filament being formed within the switching layer. A low electro-forming voltage is desirable as it creates a conductive filament that supports low current to switch an RRAM device between a high and a low resistance state. A low current operation is desirable from a power savings perspective. In some embodiments, the electro-forming voltage may be reduced by inserting an oxygen exchange layer between the switching layer and an electrode.

The oxygen exchange layer may be a metal that acts as a source or sink of oxygen vacancies. However, during the fabrication process, sidewall portions of the oxygen exchange layer may become damaged and oxidized. During operation, the inventors have found that while RRAM device with a metal oxygen exchange layer may enable formation of form conductive filaments at low electro-forming voltages, the RRAM devices suffer from retention failures. An example of retention failure observed is a drifting of the resistance level of a RRAM device from a programmed low resistance level to a level above a predetermined reference level over a 24-hour time period. The inventors believe that the oxygen exchange layer may suffer from oxidation during the fabrication process for reliable device operation. When oxidation of a metal oxygen exchange layer is not uniform a non-uniform partially oxidized metal film may be formed. Sidewall portions of the oxygen exchange layer may be particularly vulnerable to non-uniform partial oxidation. The non-uniformity of a partially oxidized oxygen exchange layer can lead to a high level of variability in device performance.

Increasing the size of the conductive filament formed during the electro-forming process may mitigate variability. However, during the process of resistance switching a larger conductive filament may require a larger electrical current to dissolve and re-form compared to a relatively smaller conductive filament. A low current operation is desirable for embedded memory applications where the RRAM device may be coupled to a transistor. The maximum current delivered by the transistor to the RRAM device may not meet the threshold current requirement for filament formation and dissolution if the conductive filament formed during the electro-forming process becomes too large in size. In examples, where the transistor threshold current is not a limitation, increasing filament size can also lead to endurance problems. Endurance problem may be defined as the number of switching cycles that an RRAM device can complete before it is stuck in the high resistance state.

The inventors have found that the problems associated with uncontrolled partial oxidation may be solved by replacing a metal oxygen exchange layer with a non-stoichiometric layer. The non-stoichiometric layer may include a metal and oxygen where the metal to oxygen ratio is not stoichiometrically proportional. The non-stoichiometric layer may include a same metal as the metal of the switching layer for added benefits such as retention improvement.

In accordance with an embodiment of the present disclosure, a memory apparatus includes an interconnect in a first dielectric above a substrate and a structure above the interconnect, where the structure includes a diffusion barrier material and covers the interconnect. The memory apparatus further includes a resistive random-access memory (RRAM) device coupled to the interconnect. The RRAM device includes a first electrode on a portion of the structure, a stoichiometric layer having a metal and oxygen on the first electrode, a non-stoichiometric layer including the metal and oxygen on the stoichiometric layer. A second electrode including a barrier material is on the non-stoichiometric layer. In some embodiments, the RRAM device further includes a third electrode for fabrication advantages on the second electrode. To prevent uncontrolled oxidation during a fabrication process a spacer may be directly adjacent to the RRAM device, where the spacer includes a second dielectric.

FIG.1Aillustrates a cross-sectional illustration of a memory apparatus100A above a substrate101. As shown, memory apparatus100A includes an RRAM device102on a portion of a structure104. The structure104includes a diffusion barrier material, (herein referred to as electrode104). The RRAM device102includes a bottom electrode106, and a stoichiometric layer108on the bottom electrode106. The stoichiometric layer108supports a conductive filament during operation and is herein referred to as switching layer108. The switching layer108includes a metal and oxygen in substantially stoichiometric proportions. The RRAM device102further includes a non-stoichiometric layer110including the metal and oxygen on the switching layer108, an electrode112on the non-stoichiometric layer110and a top electrode114on the electrode112. In the illustrative embodiment, the memory apparatus100A further includes a spacer116directly adjacent to the RRAM device, where the spacer116includes a dielectric, and a conductive interconnect118directly below and coupled with the barrier electrode104.

In an embodiment, the bottom electrode106includes a noble metal. The noble metals Ir, Pt and Pd provide excellent resistance to oxidation. However, a ruthenium bottom electrode106may oxidize and remain conductive with no adverse effect to the RRAM device102.

In an exemplary embodiment, the switching layer108includes oxygen and tantalum. When the switching layer108includes a metal such as tantalum having an oxidation state +5, the switching layer108has a chemical composition of Ta2O5. The thickness of the switching layer108may vary on the desired voltage operating range. In one embodiment, the switching layer108has a thickness of at least 1 nm. In exemplary embodiments, the switching layer108has a thickness between 2 nm and 5 nm. The magnitude of the electro-forming voltage, discussed above, is proportional to a thickness of the switching layer108. In some embodiments, the switching layer108includes a stoichiometric oxide that may not be structurally homogenous across the cross-sectional plane inFIG.1A. For example, a portion of the switching layer108inside a sidewall108A may have lattice dislocations, indicative of damage during the fabrication process.

The non-stoichiometric layer110acts as a source of oxygen vacancies or as a sink for oxygen atoms in filamentary RRAM devices and is herein referred to as oxygen exchange layer110. The oxygen vacancies migrate to and from the oxygen exchange layer110into the switching layer108, in response to an applied voltage between the top electrode114and bottom electrode106. Migration of oxygen vacancies enable resistance switching in the RRAM device100A. In an exemplary embodiment, the oxygen exchange layer110includes tantalum and oxygen for example, TaXOY, where O is oxygen and wherein the ratio between X and Y is between 1:0.8 to 1:1.2. In some embodiments, the ratio between X and Y is substantially close to 1:0.8. In other embodiments, the ratio between X and Y is substantially close to 1:1.2. In an embodiment, the oxygen exchange layer110has a thickness between 5 nm and 20 nm. The thickness may depend on the ratio between X and Y in TaxOy. In an embodiment, the oxygen exchange layer110has a gradient in oxygen concentration. The concentration of oxygen may decrease from an interface119A between the switching layer108and the oxygen exchange layer110toward interface119B between the oxygen exchange layer110and the electrode112. The oxygen gradient may such that the ratio between X and Y in TaxOyat interface119A is substantially close to 1:1.2 and the ratio between X and Y in TaxOyat interface119B is substantially close to 1:0.8.

In an embodiment, the electrode112includes ruthenium, platinum, iridium, palladium, tungsten, tantalum or an alloy including nitrogen and at least one of Ta, Ti or W. The electrode112has a thickness between 2 nm and 10 nm and may depend on the material. In some embodiments, metals that are difficult to pattern for example, Pt, Ir, Pd have a thickness that is 5 nm or less.

In an embodiment, the top electrode114includes a metal such as Ta, Ti or W or an alloy including nitrogen and at least one of Ta, Ti or W. The top electrode114has a thickness that is between 20 nm and 50 nm. In some embodiments, such as is illustrated, the top electrode114has a curved outermost surface114A.

In an embodiment, the electrode104includes an alloy including nitrogen and at least one of Ta, Ti or W. The electrode104has a cross-sectional width, WIV, as shown. In the illustrative embodiment, WIVis greater than a cross-sectional width, WBEof the bottom electrode106. In some embodiments, WIVmay also be less than WBE. In embodiments, when WIVis less than WBE, the RRAM device102has portions on a dielectric120laterally adjacent to electrode104.

Conductive interconnect118may include lateral runs (e.g., metallized trenches) and vertical runs (e.g., metallized vias). As shown, the metallization structure118has an uppermost surface that is coplanar or substantially co-planar with an uppermost surface of an adjacent dielectric122. In an embodiment, the metallization structure118includes a barrier layer118A, and a fill metal118B on the barrier layer118A. In an embodiment, the barrier layer118A includes tantalum nitride, tantalum or ruthenium. In an embodiment, the fill metal118B includes W, Co, Ni or Cu. In the illustrative embodiment, for example, a width, WCIof the metallization structure118is representative of the largest dimension of the metallization structure118, within the cross-sectional plane of the RRAM device100A. In exemplary embodiments, WCIis less than WIV. In some embodiments, the WCIis substantially similar to WIV. In some such embodiments, the electrode104covers the conductive interconnect118.

The spacer116may be utilized to prevent uncontrollable oxidation of one or more layers in the RRAM device100A. As shown, the spacer116is adjacent to outer most surface114of the top electrode include sidewall portions and a top surface.

As shown, when WBEis less than WIV, the spacer116is also on a portion of the electrode104. The dielectric liner has a composition that is substantially free of metal. In an exemplary embodiment, the dielectric liner includes silicon and nitrogen.

In the illustrative embodiment, the memory apparatus100A includes a metallization contact126. The metallization contact126may include a barrier layer and a fill material. In an embodiment, the composition of the barrier layer and the fill material may be substantially the same as the barrier layer118A and the fill metal118B.

In an embodiment, RRAM device102is scaled laterally in size and approach a lateral thickness (along the Y-axis) of the metallization contact126. In such an embodiment, any misalignment between the metallization contact126and the RRAM device100A may cause portions of the metallization contact126to extend along a section of the outermost surface114A and down a sidewall of the RRAM device102. For advantageous device operation, a lowermost portion of the metallization contact126should not extend below the oxygen exchange layer110.

In some such embodiments, the top electrode114includes a conductive material that is relatively easy to pattern and is substantially thicker than 10 nm. The top electrode114may be between 50 nm-100 nm, in some examples, which provides sufficient thickness as an intermediate layer for coupling with the metallization contact126above.

In an embodiment, the dielectric120and122include silicon and at least one of oxygen, carbon or nitrogen. In one embodiment, dielectric120includes silicon and nitrogen and dielectric122includes silicon, oxygen and nitrogen. In a different embodiment dielectric120includes silicon and nitrogen and dielectric122includes silicon, and oxygen.

In an embodiment, the substrate101includes a suitable semiconductor material such as but not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI). In another embodiment, substrate101includes other semiconductor materials such as germanium, silicon germanium or a suitable group III-N or a group III-V compound. Logic devices such as MOSFET transistors and access transistors and may be formed on the substrate101. Logic devices such as access transistors may be integrated with plurality of memory apparatus each including RRAM device102to form embedded memory. Embedded memory including RRAM devices and logic MOSFET transistors may be combined to form functional integrated circuit such as a system on chip.

In some embodiments, the bottom electrode104and the electrode112include a noble metal and top electrode104includes a metal having an affinity for oxygen. In some such embodiments, portions inside a sidewall of the top electrode114may include oxygen.

FIG.1Bincludes a cross sectional illustration of a memory apparatus100B where the bottom electrode106and the electrode112include a noble metal. In an exemplary embodiment, bottom electrode includes Ru, the electrode112includes a noble metal and the top electrode114includes at least one of Ta, TaN, TiN. In one such exemplary embodiment, the top electrode114has a top electrode portion114B and a top electrode portion114C adjacent to the top electrode portion114B. As shown, the top electrode portion114C is between the dashed line130and the outer surface114A. The top electrode portion114B includes tantalum and top electrode portion114C includes tantalum and oxygen. In an embodiment, the top electrode portion114C has an oxygen concentration that is substantially uniform. In an embodiment, the top electrode portion114C has a lateral thickness, TTE, that is between 2 nm-5 nm (across the cross-sectional plane in the Y-direction). The top electrode portion114C may have a lateral thickness, TTE, that correlates with a vertical thickness, TBE, of the bottom electrode. For example, the greater TBEis, the greater is TE.

In an embodiment, when the bottom electrode includes Ru, the oxygen exchange layer110includes an inner portion110A and an outer portion110B adjacent to the inner portion, as shown. In an embodiment, the inner portion is substantially non-stoichiometric and the outer portion is substantially stoichiometric. In the illustrative embodiment, where the oxygen exchange layer110has a chemical composition of TaXOY, the ratio between X and Y in the inner portion110A is between between 1:0.8 to 1:1.2. In one such embodiment, the outer portion110B has a chemical composition that is Ta2O5. In an embodiment, the outer portion110B has a chemical composition that is substantially the same as the chemical composition of the switching layer108. In an embodiment, outer portion110B has a lateral thickness, TOELin a cross-sectional plane ofFIG.1Bthat is between 1 nm and 3 nm. In an embodiment, TOELcorrelates with TBE. For example, the greater TBEis, the greater is TOEL. A bottom electrode including Ru, may have a thickness TBEthat ranges between 5 nm and 10 nm.

In some embodiments, top electrode portion114A adds undesirable electrical resistance to the RRAM device. Added electrical resistance increases the burden on applied voltage during operation. In some such embodiments, the contact metallization structure126extends into the conductive top electrode portion114B (inside dashed line130), as shown.

FIG.1Cillustrates a plan-view of the RRAM device inFIG.1B, in accordance with an embodiment of the present disclosure. The areas of the various layers shown represent a lowermost surface of the electrode104and an uppermost surface of the conductive interconnect118. The spacer116and metallization contact126are not shown for clarity. As shown, the electrode104has a lowermost surface area that is greater than a lowermost surface area of the conductive interconnect118(inside dashed lines). The electrode104also covers the conductive interconnect118, as shown. A plan view area of a lowermost surface of the RRAM device102is also shown in the Figure. In the illustrative embodiment, the RRAM device102has a lowermost surface area that is less than the lowermost surface area of the electrode104.

FIG.2illustrates a flow chart for a method to fabricate an RRAM device, in accordance with an embodiment of the present disclosure. In an embodiment, the method200begins in operation210by forming a conductive layer above a conductive interconnect. The method200continues in operation220by forming a layer including oxygen and a metal on the conductive layer. The method200continues in operation230by forming a non-stoichiometric layer on the layer including oxygen and metal. The method200continues in operation240by forming an electrode layer on the non-stoichiometric layer. The method200continues in operation250by patterning the electrode layer, the non-stoichiometric layer, the layer including oxygen and metal, and the conductive layer to form a structure having sidewalls.

FIGS.3A-3Fillustrate cross-sectional views of the memory apparatus100A illustrated inFIG.1Aevolving as a fabrication method, such as method200, is practiced.

FIG.3Aillustrates a metallization structure118surrounded by a dielectric122formed above a substrate101. In an embodiment, the metallization structure118is formed in a dielectric122by a damascene or a dual damascene process. In an embodiment, the metallization structure118includes a barrier layer, such as ruthenium, titanium nitride, ruthenium, tantalum or tantalum nitride, and a fill metal, such as cobalt, nickel, copper or tungsten. In an embodiment, the metallization structure118is fabricated using a subtractive etch process when materials other than copper are utilized. In some examples, the dielectric122includes a silicon and at least one or nitrogen, oxygen or carbon. In an embodiment, the dielectric122has an uppermost surface122A that is substantially co-planar with an uppermost surface118C of the metallization structure118. In some examples, metallization structure118may be electrically connected to a circuit element such as an access transistor (not shown). Logic devices such as access transistors may be integrated with memory devices such as a RRAM device to form embedded memory.

FIG.3Aalso illustrates an electrode104formed above the conductive interconnect118. In an embodiment, a conductive layer including a diffusion barrier material is blanket deposited on the uppermost surfaces118C and122A. In an embodiment, the conductive layer is patterned by forming a mask on the conductive layer and performing a plasma etch process to form electrode104. A dielectric120is blanket deposited on the surface104A of the electrode104and on the dielectric surface122A. In an embodiment, the dielectric120is blanket deposited using a physical vapor deposition (PVD) or a chemical vapor deposition (CVD), or a plasma enhanced chemical vapor deposition (PECVD) process.

FIG.3Billustrates the structure ofFIG.3Afollowing a process to planarize the first dielectric and portions of the electrode. In an embodiment, the planarization includes a chemical mechanical polish (CMP) process. In the illustrative embodiment, CMP process is utilized to planarize the dielectric120and portions of the electrode104to form uppermost surfaces104A and120A that are substantially co-planar as shown.

FIG.3Billustrates the structure ofFIG.3Afollowing the formation of a material layer stack300utilized in the formation of an RRAM device, on a dielectric surface120A and on the electrode surface104A. In 1 an embodiment, a conductive layer301is blanket deposited by a physical vapor deposition (PVD), a chemical vapor deposition (CVD), a plasma enhanced chemical vapor deposition (PECVD) or an atomic layer deposition process (ALD). In an embodiment, the conductive layer301includes noble metals Ir, Pt, Pd or Ru. The choice of materials utilized to form the conductive layer301results in conductive layer301having a low electrical resistivity, such as an electrical resistivity between 100-250 μ-Ω-cm.

In an embodiment, the conductive layer301may be planarized before deposition of additional layers of the material layer stack300. Planarization may enable the top surface301A of the conductive layer301to have a surface roughness that is less than 1 nm. A surface roughness of less than 1 nm enables a layer303having a uniform thickness to be deposited on surface of the conductive layer301. A uniform thickness in the layer303is desirable to reduce variation in forming voltage in a large collection of RRAM devices. In an embodiment, the layer303includes a material is the same or substantially the same as the material of the switching layer108.

In other embodiments, a stoichiometric layer303is deposited on the conductive layer301without breaking vacuum, as shown. In an embodiment, the stoichiometric layer303is a material that includes oxygen and tantalum having a composition Ta2O5. The stoichiometric layer303may be formed using an atomic layer deposition (ALD) process. The ALD process may be characterized by a slow and a controlled deposition rate resulting in a metal oxide film with a stoichiometric oxygen content. In some embodiments, the stoichiometric layer303is deposited using a physical vapor deposition (PVD) process. The PVD process may include depositing a metal oxide film in an ambient containing oxygen flowing at a constant rate. The stoichiometric layer303is deposited to a thickness between 2 nm and 5 nm.

The deposition method is continued with the formation of a non-stoichiometric layer305on the stoichiometric layer303. The PVD process may include depositing a metal oxide film in an ambient containing oxygen flowing at a constant rate. The deposition process may form a non-stoichiometric layer305that is slightly deficient in oxygen concentration resulting in a film that is deficient in oxygen content. In some such embodiments, the non-stoichiometric layer305has an oxygen concentration gradient with higher concentration of oxygen proximate to the stoichiometric layer surface303A and a lower concentration of oxygen distal from a conductive layer surface307A. Such an arrangement may preferably provide greater oxygen vacancies in a location that aids with filament formation and dissolution.

The non-stoichiometric layer305may include a material having a composition and a thickness, such as is described above in association with the oxygen exchange layer110such as TaXOY. Utilizing a metal that is the same as the metal of the stoichiometric layer303enables an upper portion of the stoichiometric layer303to maintain oxygen vacancies after an anneal process (to be described further below). The presence of oxygen vacancies may reduce the electro-forming voltage during operation. In an embodiment, the non-stoichiometric layer305is blanket deposited on the stoichiometric layer303, for example, using a PVD process.

The deposition method is continued with the formation of the conductive layer307on the non-stoichiometric layer305. In an embodiment, the conductive layer307includes a material that is the same as or substantially the same as the material of the electrode112(described in association withFIG.1A). Referring again toFIG.3C. The conductive layer307may be deposited using a PVD process. In one example the conductive layer307and the non-stoichiometric layer305are deposited sequentially in a same chamber or in a same tool without breaking vacuum. Sequential deposition without an air-break may prevent an uppermost portion of the non-stoichiometric layer305from becoming stoichiometric. Oxidation of the non-stoichiometric layer305can introduce variability in electro-forming voltage and variability in switching voltages during RRAM device operation. In some embodiments, the conductive layer307includes a metal of the stoichiometric layer303and the metal of the non-stoichiometric layer305, i.e. Ta.

The conductive layer307is utilized as a work function electrode and may include a material that is substantially difficult to pattern when deposited to a thickness greater than 5 nm. In some such embodiments, the conductive layer307is deposited to a thickness of approximately 10 nm and a top electrode layer309is deposited on the conductive layer307. Portions of the top electrode layer309may be sacrificed during subsequent processing operations. In an embodiment, the top electrode layer309is blanket deposited using one of the deposition processes described above. The top electrode layer309is deposited to a thickness between 20 nm and 100 nm. In some embodiments, the top electrode layer309includes a metal of the stoichiometric layer303and the metal of the non-stoichiometric layer305, i.e. Ta. In other embodiments, the top electrode layer309and the conductive layer307each includes a metal of the stoichiometric layer303and the metal of the non-stoichiometric layer305, i.e. Ta. In some such embodiments, top electrode layer309further includes nitrogen.

In one embodiment, the conductive layer301includes ruthenium, conductive layer307layer includes a noble metal excluding ruthenium, and the top electrode layer309includes Ta, Ti or W or an alloy including nitrogen and at least one of Ta, Ti or W. In second embodiment, conductive layer301includes a noble metal excluding ruthenium, conductive layer307layer includes a noble metal excluding ruthenium, and the top electrode layer309includes Ta, Ti or W or an alloy including nitrogen and at least one of Ta, Ti or W. In a third embodiment, the conductive layer301includes a noble metal excluding ruthenium, conductive layer307layer includes ruthenium, and the top electrode layer309includes Ta, Ti or W or an alloy including nitrogen and at least one of Ta, Ti or W.

Upon deposition of the top electrode layer309, the RRAM material layer stack300, may be subjected to a high temperature anneal process. In an embodiment, anneal temperatures reach up to 400° C. and last for a time period of up to 60 minutes. Annealing is a thermal phenomenon that may drive the oxygen from the stoichiometric layer303, creating oxygen vacancies, Vo, in the switching layers. When the non-stoichiometric layer305and stoichiometric layer303both include Ta, some oxygen from the stoichiometric layer303may diffuse toward the non-stoichiometric layer305above during the anneal process. The process is insufficient to fully oxidize the non-stoichiometric layer305.

After annealing the material layer stack300, a mask311is formed on the material layer stack300. In the illustrative embodiment, the mask311is formed on the top electrode layer309. In some embodiments, the mask311is formed by a lithographic process. In other embodiments, the mask311includes a dielectric material that has been patterned. The mask311defines a size of an RRAM device that will subsequently be formed.

FIG.3Dillustrates the structure ofFIG.3Cfollowing an etch process used to etch a plurality of layers of the material layer stack300to form an RRAM device350. In an embodiment, an anisotropic plasma etch process is used to pattern the top electrode layer309to form a top electrode114. Portions of the top electrode114may be eroded during the etch process resulting in an outmost surface114A that is curved as shown. The plasma etch is continued to etch the conductive layer307, the non-stoichiometric layer305, the stoichiometric layer303and the conductive layer301to form oxygen exchange layer110, switching layer108and electrode104, respectively.

In some embodiments, portions of one or more layers of the material layer stack300may become damaged by attack from energetic ion species during the plasma etch. In some such embodiments, the anneal process described above can be performed after the plasma etch process is completed.

In an embodiment, the plasma etch may be stopped after etching the conductive layer301and exposing the conductive layer301. A sacrificial spacer may be formed surrounding a portion of a partially patterned material layer stack300(above conductive layer301, for example). The conductive layer301may be etched after formation of the spacer. In an embodiment, where the conductive layer301includes ruthenium, a plasma etch process may utilize oxygen to pattern the ruthenium. The sacrificial spacer may protect portions of the partially patterned material layer stack300, such as the oxygen exchange layer110from becoming oxidized. After etching the conductive layer301to form the bottom electrode106, the sacrificial spacer may be removed. In such an embodiment, the bottom electrode may protrude laterally beyond the switching layer108.

FIG.3Eillustrates the structure ofFIG.3Dfollowing the formation of a dielectric spacer layer114covering the RRAM device350. The dielectric spacer layer114may be blanket deposited by a PVD, PECVD or an ALD process. In some embodiments, the dielectric spacer layer114is deposited immediately after forming the bottom electrode106and forms a hermetic seal completely around the RRAM device350, including sidewall and top surfaces. The spacer116may be formed on the structure of the RRAM device350without breaking vacuum. In an embodiment, the dielectric spacer layer114includes a material such as silicon nitride, silicon carbide, carbon-doped silicon nitride, silicon dioxide. In an embodiment, the dielectric spacer layer has a thickness between 5 nm and 50 nm.

FIG.3Fillustrates the structure ofFIG.3Efollowing the formation of a dielectric352on the dielectric spacer layer114and following the formation of contact metallization126on the RRAM device350. The contact metallization126may be formed on the RRAM device350after deposition of a dielectric352on the RRAM device350. In an embodiment, a via opening (not shown) may be formed in the dielectric352. In the illustrative embodiment, the via opening via opening etches a portion of the dielectric spacer layer114to expose the top electrode114. In an embodiment, one or more materials of the contact metallization126may be deposited into the via opening and subsequently planarized to form metallization structure126. Depending on the size of the via opening, the spacer116may or may not remain on a top surface114B of the top electrode114. In the illustrative embodiment, a portion of the spacer116remains on the top surface114B.

Depending on the choice of materials and on fabrication processes, the RRAM device350may include all embodiments of the RRAM device100A or RRAM device100B described above.

FIG.4Aillustrates an I-V plot, demonstrating concepts involved with filament formation and voltage cycling (reading and writing) in an RRAM device, such as an RRAM device400depicted inFIG.4B, in accordance with embodiments of the present disclosure. RRAM device400is the same or substantially the same as the RRAM device102described in association withFIG.1A. Referring again toFIG.4A, the initial operation of the RRAM device400begins by applying a voltage, between the top electrode114and the bottom electrode104, that increases in magnitude until it reaches a value VElectro-Forming(point A to B). In an embodiment, VElectro-Formingis less than 1.6V. In an “intentional” one-time breakdown process, known as electro-forming, oxygen vacancies, Vo, are removed from the oxygen exchange layer110into the switching layer108and into the switching layer108to augment the vacancies created during the anneal process described above. Movement of vacancies in response to an electric field generated in the RRAM device400leads to a formation of a “conductive filament” in the switching layer108. In an embodiment, the conductive filament may extend across switching layer108(point B).

FIG.4Bdepicts an illustration of a conductive filament402in the RRAM device400, in an accordance with an embodiment of the present disclosure. It is to be appreciated that a size of the conductive filament402may be determined by resistance of the RRAM device before the process of electro-forming and by the electroforming voltage. With a conductive filament402, bridging from the top electrode114to the bottom electrode104, the RRAM device400is said to be almost immediately conductive. Referring again to the I-V plot, RRAM device400becomes conductive and the current through the RRAM device starts to increase (point B to C), until it reaches a predetermined compliance current, IComp. The current through the RRAM device400does not continue to increase beyond IComp. In an embodiment, when the RRAM device is coupled with a transistor, ICompmay be the maximum current that the transistor can deliver to the RRAM device400. At point C, the RRAM device400is in a low resistance state.

By reducing the magnitude of the voltage (while maintaining a positive polarity) between the top electrode114and bottom electrode104(moving from point C to D and then to point A), causes a reduction in a strength of the electric field. By applying a voltage of an opposite polarity between the top electrode114and bottom electrode104(moving from point A to F), causes a reversal in a direction of the electric field. In response to the change in the direction of the electric field, the oxygen vacancies move towards the oxygen exchange layer110, leading to a dissolution of the conductive filament402in the switching layer108and in the switching layer108. Filament dissolution takes place at a critical voltage (point F), termed VReset. In an embodiment, VResetis between −0.8 V and −1.0 V. Increasing the magnitude of the voltage beyond VResetchanges the current flowing through the device.

FIG.4Cdepicts an illustration of a dissolved filament404in the RRAM device400, in an accordance with an embodiment of the present disclosure. With a dissolved filament404, the current through the RRAM device400decreases dramatically and the device returns to a high resistance state (point G).

Referring again to the I-V plot inFIG.4A, it is to be appreciated that the high resistance level of the RRAM device, point G, is different and lower in magnitude compared to the resistance level of the device before the onset of the forming process. In other words, the resistance level of the RRAM device400in a high resistance state can be over 10 times smaller than the virgin resistance (discussed above). By decreasing the magnitude of the voltage, traversing from point G to H and then to point I in the I-V plot, the dissolved filament is recreated again (at point I) under the action of vacancy migration. At a critical voltage, VSet, the filament completely bridges the top electrode114and the bottom electrode104and current begins to flow through the RRAM device400. In an embodiment, VSetis less than 1.0 V. The RRAM device is, once again, said to be in a conductive or a low resistance state (at point J). The filament, that is recreated at point J, may have a size that is comparable to the size of the filament formed during the electro-forming process.

Cycling of an RRAM device400in this manner, where the resistance levels remain unchanged when the voltage between the top electrode114and the bottom electrode104is set to 0V, leads to non-volatile memory effect. By increasing the magnitude of the voltage to at least 0.05V, the resistance state of the RRAM device400can be read. In one example, a voltage of 0.05V to 0.2V, referred to as a read voltage, VR, is much less than the switching voltage (Vsetor VReset) and does not perturb the resistance state of the RRAM device400. It is to be appreciated that the values Vsetand VReset, generally refer to a portion of a voltage that may be applied to a transistor in series with the RRAM device400. The RRAM device400coupled with a transistor in this manner is given the term embedded memory.

FIG.5illustrates a two-terminal spin orbit memory device such as memory apparatus100A including an RRAM device102coupled to an access transistor500.

In an embodiment, the transistor500is on a substrate501and has a gate502, a source region504, and a drain region506. In the illustrative embodiment, an isolation508is adjacent to the source region504, drain region506and portions of the substrate501. In some implementations of the disclosure, such as is shown, a pair of sidewall spacers510are on opposing sides of the gate502.

The transistor500further includes a gate contact512above and electrically coupled to the gate502, and a drain contact514above and electrically coupled to the drain region506, and a source contact516above and electrically coupled to the source region504, as is illustrated inFIG.5. The transistor500also includes dielectric518adjacent to the gate502, source region504, drain region506, isolation508, sidewall spacers510, gate contact512, drain contact514and source contact516.

In an embodiment, the memory apparatus100A has one or more structural and material properties described above in association withFIG.1A. In the illustrative embodiment, the memory apparatus100A includes an RRAM device102on a portion of an electrode104, bottom electrode106, on the electrode104, and a switching layer108on the bottom electrode106. The switching layer108supports a conductive filament during operation. The switching layer108includes a metal and oxygen in substantially stoichiometric proportions. The RRAM device102further includes an oxygen exchange layer110including the metal and oxygen on the switching layer108, an electrode112on the oxygen exchange layer110and a top electrode114on the electrode112. In the illustrative embodiment, the memory apparatus100A further includes a spacer116directly adjacent to the RRAM device, where the spacer116includes a dielectric. The electrode104is above and coupled with conductive interconnect118and adjacent to dielectric518. In the illustrative embodiment, the conductive interconnect118is on and above with the drain contact514. A contact metallization126, is coupled with the top electrode114as shown. Contact metallization126may be connected to one or more circuit elements.

In other embodiments, a memory apparatus having one or more features of memory apparatus100B may be coupled with the transistor500.

Gate contact512and source contact516are each coupled with interconnects. In the illustrative embodiment, gate contact512is coupled with a source interconnect522and the source contact516is coupled with a gate interconnect524. A dielectric526is adjacent to source interconnect522, gate interconnect524, memory device100, source contact516and gate contact512. As shown, the dielectric spacer116extends laterally beyond the memory apparatus100A and over the dielectric518to the gate interconnect524and source interconnect522. The dielectric spacer116also extends on a portion of the gate contact512and source contact516, as shown.

In an embodiment, the underlying substrate501represents a surface used to manufacture integrated circuits. Suitable substrate501includes a material such as single crystal silicon, polycrystalline silicon and silicon on insulator (SOI), as well as substrates501formed of other semiconductor materials. In some embodiments, the substrate501is the same as or substantially the same as the substrate101. The substrate501may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates. In an embodiment, the transistor500associated with substrate501are metal-oxide-semiconductor field-effect transistors (MOSFET or simply MOS transistors), fabricated on the substrate501. In some embodiments, the transistor500is an access transistor500. In various implementations of the disclosure, the transistor500may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoril6on and nanowire transistors.

The gate electrode502B of the access transistor500of substrate501is formed on the gate dielectric layer502A and may consist of at least one P-type work function metal or N-type work function metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode502B may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a conductive fill layer.

The sidewall spacers510may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers include deposition and etching process operations. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack. As shown, the source region504and drain region506are formed within the substrate adjacent to the gate stack of each MOS transistor. The source region504and drain region506are generally formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source region504and drain region506. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate501may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source region504and drain region506. In some implementations, the source region504and drain region506may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the source region504and drain region506may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source region504and drain region506.

In an embodiment, the source contact516, the drain contact514and gate contact512each include a multi-layer stack. In an embodiment, the multi-layer stack includes two or more distinct layers of metal such as a layer of Ti, Ru or Al and a conductive cap on the layer of metal. The conductive cap may include a material such as W or Cu.

In an embodiment, the source interconnect522, gate interconnect524, and contact metallization126includes a material that is the same or substantially the same as the material of the conductive interconnect118.

The isolation508and dielectric518and526may each include any material that has sufficient dielectric strength to provide electrical isolation. Materials may include silicon and one or more of oxygen, nitrogen or carbon such as silicon dioxide, silicon nitride, silicon oxynitride, carbon doped nitride or carbon doped oxide.

FIG.6illustrates a computing device600in accordance with embodiments of the present disclosure. As shown, computing device600houses a motherboard602. Motherboard602may include a number of components, including but not limited to a processor601and at least one communications chip604or605. Processor601is physically and electrically coupled to the motherboard602. In some implementations, communications chip605is also physically and electrically coupled to motherboard602. In further implementations, communications chip605is part of processor601.

Depending on its applications, computing device600may include other components that may or may not be physically and electrically coupled to motherboard602. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset606, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). In an embodiment, the battery is coupled to power at least one of the processor or the volatile or non-volatile memory.

Processor601of the computing device600includes an integrated circuit die packaged within processor601. In some embodiments, the integrated circuit die of processor601includes one or more transistors, interconnect structures, and non-volatile memory devices such as transistor500, source interconnect522, gate interconnect524, contact metallization126, and conductive interconnect118, and memory apparatus100A including RRAM device102, respectively (FIG.5). Referring again toFIG.6, the term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

Communications chip605also includes an integrated circuit die packaged within communication chip605. In another embodiment, the integrated circuit die of communications chips604,605includes one or more transistors, interconnect structures, non-volatile memory devices, conductive structures and metallization structures such as transistor500, source interconnect522, gate interconnect524, contact metallization126, and conductive interconnect118, and memory apparatus100A including RRAM device102, respectively (FIG.5). Referring again toFIG.6, depending on its applications, computing device600may include other components that may or may not be physically and electrically coupled to motherboard602. These other components may include, but are not limited to, volatile memory (e.g., DRAM)607,608, non-volatile memory (e.g., ROM)610, a graphics CPU612, flash memory, global positioning system (GPS) device613, compass614, a chipset606, an antenna616, a power amplifier609, a touchscreen controller611, a touchscreen display617, a speaker615, a camera603, and a battery618, as illustrated, and other components such as a digital signal processor, a crypto processor, an audio codec, a video codec, an accelerometer, a gyroscope, and a mass storage device (such as hard disk drive, solid state drive (SSD), compact disk (CD), digital versatile disk (DVD), and so forth), or the like. In further embodiments, any component housed within computing device600and discussed above may contain a stand-alone integrated circuit memory die that includes one or more arrays of NVM devices including one or more memory apparatus each coupled with a transistor.

FIG.7illustrates an integrated circuit (IC) structure700that includes one or more embodiments of the disclosure. The integrated circuit (IC) structure700is an intervening substrate used to bridge a first substrate702to a second substrate704. The first substrate702may be, for instance, an integrated circuit die. The second substrate704may be, for instance, a memory module, a computer mother, or another integrated circuit die. Generally, the purpose of an integrated circuit (IC) structure700is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an integrated circuit (IC) structure700may couple an integrated circuit die to a ball grid array (BGA)707that can subsequently be coupled to the second substrate704. In some embodiments, the first and second substrates702/704are attached to opposing sides of the integrated circuit (IC) structure700. In other embodiments, the first and second substrates702/704are attached to the same side of the integrated circuit (IC) structure700. And in further embodiments, three or more substrates are interconnected by way of the integrated circuit (IC) structure700.

The integrated circuit (IC) structure may include metal interconnects708and vias710, including but not limited to through-silicon vias (TSVs)712. The integrated circuit (IC) structure700may further include embedded devices714, including both passive and active devices. Such embedded devices714include capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, device structure including transistors, such as transistor500(described inFIG.5) coupled with a memory apparatus100A including RRAM device102, in accordance with an embodiment of the present disclosure. Referring again toFIG.7, the integrated circuit (IC) structure700may further include embedded devices714such as one or more resistive random-access devices, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the integrated circuit (IC) structure700. In accordance with embodiments of the present disclosure, apparatuses or processes disclosed herein may be used in the fabrication of integrated circuit (IC) structure700.

Accordingly, one or more embodiments of the present disclosure relate generally to the fabrication of embedded microelectronic memory. The microelectronic memory may be non-volatile, wherein the memory can retain stored information even when not powered. One or more embodiments of the present disclosure relate to the fabrication of a memory apparatus including an RRAM device having a non-stoichiometric oxygen exchange layer above a stoichiometric switching layer. The memory apparatus may be used in an embedded non-volatile memory application.

Thus, embodiments of the present disclosure include RRAM devices and methods of fabrication.

In a first example, memory apparatus includes an interconnect in a first dielectric above a substrate, a structure above the interconnect, where the structure includes a diffusion barrier material. The structure substantially covers the interconnect. A resistive random-access memory (RRAM) device is coupled to the interconnect, the RRAM device includes a first electrode on a portion of the structure, a stoichiometric layer including metal and oxygen on the first electrode, a non-stoichiometric layer including the metal and oxygen on the stoichiometric layer, a second electrode including a barrier material on the non-stoichiometric layer and a third electrode on the second electrode. A spacer is directly adjacent to the RRAM device where the spacer includes a second dielectric.

In second examples, for any of the first example, the first electrode includes a noble metal.

In third examples, for any of the first through second examples the stoichiometric layer and the non-stoichiometric layer each include tantalum.

In fourth examples, for any of the first through third examples, the stoichiometric layer has a chemical composition of Ta2O5, and wherein the sub-stoichiometric layer has a chemical composition of TaxOY, where O is oxygen and wherein the ratio between X and Y is between 1:1.08 to 1:1.2.

In fifth examples, for any of the first through fourth examples, the sub-stoichiometric layer has a gradient in oxygen concentration, where the concentration of oxygen decreases away from an interface between the non-stoichiometric layer and the stoichiometric layer toward the second electrode.

In sixth examples, for any of the first through fifth examples, the stoichiometric layer has a thickness in the range of 2 nm-5 nm, where the non-stoichiometric layer has a thickness in the range of 5 nm-15 nm, and wherein the non-stoichiometric layer has a thickness that is between 2 and 3 times the thickness of the stoichiometric layer.

In seventh examples, for any of the first through sixth examples, the first electrode includes a noble metal, and where the second electrode includes a noble metal.

In eighth examples, for any of the first through seventh examples, the third electrode includes tantalum or an alloy, and where the alloy includes nitrogen and at least one of tantalum, tungsten or titanium.

In ninth examples, for any of the first through eighth examples, the non-stoichiometric layer has a sidewall, and where a portion of the non-stoichiometric layer adjacent to the sidewall is substantially oxidized.

In tenth examples, for any of the first through ninth examples the portion of the non-stoichiometric layer adjacent to the sidewall has a lateral width of less than 3 nm as measured from the sidewall.

In eleventh examples, for any of the first through tenth examples, the third electrode has an outer most sidewall surface, and wherein a portion of the third electrode adjacent to the outmost sidewall surface includes oxygen.

In twelfth examples, for any of the first through eleventh examples, the spacer is on a portion of an uppermost surface of the diffusion barrier, and on an uppermost surface of the third electrode.

In a thirteenth example, for any of the first through twelfth examples, the memory apparatus further includes a metallization structure in contact with a portion of the third electrode.

In a fourteenth example, a memory apparatus includes an interconnect in a dielectric above a substrate, a diffusion barrier on an uppermost surface of the interconnect, where the diffusion barrier has a lowermost surface area that is greater than the uppermost surface area of the interconnect and further where the diffusion barrier covers the interconnect. A resistive random-access memory apparatus is coupled to the interconnect, the RRAM device includes a bottom electrode including ruthenium on a portion of the diffusion barrier, a stoichiometric layer including oxygen and tantalum on the first electrode, layer including tantalum and oxygen on the stoichiometric layer. The layer further includes an inner portion and an outer portion adjacent to the inner portion, where the inner portion is non-stoichiometric and the outer portion is substantially stoichiometric. A barrier electrode is on the layer including the tantalum and oxygen, and a top electrode on the barrier electrode, where the top electrode includes a first portion and a second portion adjacent to the first portion, where the first portion includes tantalum and a second portion includes tantalum and oxygen.

In fifteenth examples, for any of the fourteenth examples, the stoichiometric layer has a chemical composition, Ta2O5, and wherein the layer including tantalum and oxygen has a chemical composition of TaXOY, where O is oxygen and where the ratio between X and Y is between 1:1.08 to 1:1.2.

In sixteenth examples, for any of the fourteenth through fifteenth examples, the outer portion that is substantially stoichiometric has a thickness between 2 nm to 5 nm. In seventeenth examples, for any of the fourteenth through sixteenth examples, the sub-stoichiometric layer has a gradient in oxygen concentration, and where the concentration of oxygen decreases away from an interface between the non-stoichiometric layer and the stoichiometric layer toward the barrier electrode.

In eighteenth examples, for any of the fourteenth through seventeenth examples, the first electrode has a thickness between 5 nm and 10 nm.

In a nineteenth example, for any of the fourteenth through eighteenth examples, the bottom electrode includes Ru and the second electrode includes a noble metal.

In twentieth examples, for any of the fourteenth through nineteenth examples, the top electrode includes an outermost surface, and where a portion of the top electrode adjacent to the outmost surface includes oxygen.

In twenty first examples, for any of the fourteenth through twentieth examples, the portion of the top electrode adjacent to the outer most surface including oxygen has a lateral thickness that correlates with a vertical thickness of the bottom electrode, where the lateral thickness is orthogonal to the vertical thickness, and where the vertical thickness is measured from an interface between an uppermost surface of the diffusion barrier and a lowermost surface of the bottom electrode.

In a twenty second example, a system includes a processor, a radio transceiver coupled to the processor, where the transceiver includes a transistor. The transistor includes a drain contact coupled to a drain, a source contact coupled to a source and a gate contact coupled to a gate. The radio transceiver further includes a resistive random-access memory (RRAM) device coupled with the drain contact, the RRAM device includes a first electrode above the drain contact, a stoichiometric layer including metal and oxygen on the first electrode, a non-stoichiometric layer including the metal and oxygen on the stoichiometric layer, a second electrode on the sub-stoichiometric layer and a third electrode on the barrier electrode. A spacer directly is adjacent to the RRAM device, where the spacer includes a second dielectric.

In twenty third examples, for any of the twenty second examples, the system further includes a battery coupled to power at least one of the processor or memory.