Integrating thermoelectric elements into wafer for heat extraction

An embodiment of the present invention is a technique to provide heat extraction for semiconductor devices. At least a thermoelectric film is fabricated onto a bare wafer. The backside of the bare wafer is bonded to an active wafer having at least a device. The bonded bare and active wafers are annealed.

BACKGROUND

1. Field of the Invention

Embodiments of the invention relate to the field of semiconductor, and more specifically, to heat extraction.

2. Description of Related Art

Heat extraction from, or cooling, microelectronic devices or processors is challenging due to their high average power dissipation and localized high heat flux areas, or hot spots. As operating frequency increases for high performance processors, heat extraction is becoming a fundamental design problem.

Existing techniques to solve the above problem are inadequate. Traditional techniques include the use of a heat sink to dissipate heat generated from the device or processor. Typically, the heat sink is attached to the silicon die via a heat spreader. This method has a number of disadvantages. First, the heat extraction is not efficient because of inefficient thermal interface between the heat sink and the silicon die. Second, there is no flexibility in localized control of cooling because the heat sink is attached to the entire silicon die. Third, the manufacturing process is inefficient because the heat sink is placed onto the silicon die after the die has been created.

DESCRIPTION

An embodiment of the present invention is a technique to provide heat extraction for semiconductor devices. At least a thermoelectric film or device is fabricated onto a bare wafer. The backside of the bare wafer is bonded to an active wafer having at least a device. The bonded bare and active wafers are annealed.

One embodiment of the invention may be described as a process which is usually depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be re-arranged. A process is terminated when its operations are completed. A process may correspond to a method, a procedure, a method of manufacturing or fabrication, etc.

One embodiment of the present invention provides a technique to extract heat from semiconductor devices such as microprocessors. When a microprocessor operates at high frequencies, heat fluxes may be generated locally or in large regions. Heat fluxes on large areas may be as high as greater than 100 W/cm2. For local areas, the values may be even much higher (e.g., >600 W/cm2). One embodiment of the present invention incorporates thermoelectric converters (TEC's), elements, films, or modules into a wafer to be bonded with a wafer that contains the microelectronic devices.

FIG. 1is a diagram illustrating a process100to provide heat extraction to semiconductor devices in which one embodiment of the invention can be practiced. The process100starts with an active wafer110and a bare wafer130. The active wafer110and the bare wafer130will be bonded together.

The active wafer110is a wafer that contains the dies1151to115Nof devices or processors that heat extraction needs to be provided. The active wafer110may be thinned to a suitable thickness to a thinned active wafer120. The bare wafer130is a silicon wafer that has thermoelectric films or elements1351to135Kto provide cooling or refrigeration to the devices or processors of the dies when they are powered. The thermoelectric films or elements1351to135Kare fabricated onto the bare wafer130at appropriate locations corresponding to the locations that need to have thermal control on the active wafer110or120such as localized hot spots that generate heat when the devices are powered and running. The thermoelectric films or elements1351to135Kare made of a suitable thermoelectric material such as an alloy comprising at least one of bismuth (Bi), tellurium (Te), antimony (Sb), lead (Pb), silicon (Si), germanium (Ge). As is known by one skilled in the art, any suitable thermoelectric material may be used. In one embodiment, the alloy may be one of Bi and Te, Sb and Te, Zn and Sb, Te, Ag, Ge, and Sb, and Pb and Te. Examples are Bi2Te3, Sb2Te3. Power control signals may be provided so that they may be selectively and/or individually turned on or off.

The bare wafer130may be thinned to a thinned bare wafer140to a desired thickness before bonding. The desired thickness may be a few hundred microns. There is typically an optimal thickness beyond which the heat extraction result may become worse. The thin bare wafer140provides better thermal interface because the heat transfer between the two wafers is more efficient. The bare wafer130is then coated by a thin interlayer150such as a surfactant to enhance bonding. Similarly, the thinned bare wafer140is coated with a thin interlayer150.

The active wafer110or the thinned active wafer120is then bonded to either the coated bare wafer130or the coated thinned bare wafer140. The results are the bonded wafers160,170,180, and190. During bonding, the two wafers are aligned so that their areas match such that the thermoelectric films are at locations corresponding to the locations on the active wafer110or the thinned active wafer120that need heat extraction. Typically, these locations are known in advance in the design and fabrication of the active wafer110or120. These locations are then mapped to the bare wafer130or140for registration or matching. The thermoelectric films are then located at these matching locations. Then the backside of the bare wafer130or the thinned bare wafer140is bonded to the active wafer110or the thinned active wafer120.

The two wafers are then annealed at moderate temperatures such as from 250° C. to 500° C. to form a good covalent bond between the two wafers. The annealing is done by heating the bonded wafers to the desired temperature for a time period (e.g., a few hours) and then allowing the bonded wafers to cool down. The result is a good thermal interface between the two wafers and a mechanically strong bond.

During the fabrication process, the bonded wafers are singulated to provide die assemblies. Each die assembly includes a die having an active device, a substrate from the bare wafer bonded to the die, and at least a thermoelectric film fabricated on the substrate to remove heat from the die when the active device is powered.

The invention offers the following benefits. First, there is an efficient heat removal from the active wafer110or120due to the reduced thermal interface resistance of the direct bonding. Second, the thermoelectric elements offer the ability to cool localized regions of the active die as well as larger regions depending on the need. Third, the external power delivery to the thermoelectric elements is easy because these elements are in the backside of the bonded wafers. Fourth, scalability can be achieved by thinning the wafers to appropriate thickness prior to bonding. Fifth, the thermoelectric elements may be turned on and off at selected regions by suitable power connections thereby conserving power. Lastly, the manufacturing process may be efficient because the two wafers can be processed separately prior to bonding.

FIG. 2is a flowchart illustrating a process200to provide heat extraction to semiconductor devices according to one embodiment of the invention.

Upon START, the process200fabricates at least a thermoelectric film onto a bare wafer (Block210). Next, the process200coats the backside of the bare wafer with a thin interlayer to enhance the bonding (Block220). Then, the process200aligns the backsides of the bare wafer with an active wafer that contains at least a device or processor (Block230). Next, the process200bonds the two wafers together (Block240).

Then, the process200anneals the bonded wafers by heating them to a desired temperature (e.g., from 250° C. to 500° C.) and then allowing them to cool down (Block250). The process200is then terminated.

FIG. 3is a diagram illustrating the effect of die thickness on thermal performance according to one embodiment of the invention. The diagram shows curves310,320,330,340, and350. The horizontal axis is the power input to the thermoelectric in Watts (W). The vertical axis is the junction temperature in degrees Celsius (° C.).

The curves show the thermal performance as a function of power consumption and the die thickness. The die thickness is directly related to the distance between the hot spot and the thermoelectric films. For this experiment and simulation, a thermal test die is used. It has a 400 μm×400 μm hot spot located in the center. The hot spot is powered to 3 W, resulting in a local hot spot flux of 1875 W/cm2. The rest of the die is powered uniformly at 100 W. The curve310corresponds to a constant temperature without using the thermoelectric elements. The curves320,330,340, and350correspond to using thermoelectric elements at various die thicknesses of 0.75 mm, 0.375 mm, 0.28125 mm, and 0.1875 mm, respectively.

It is shown that there is a significant improvement in thermal performance when the thickness is reduced from 0.75 mm to 0.375 mm. Reducing the die thickness further, however, does not improve the performance. In fact, the curve350shows that the thermal performance becomes even worse. Therefore, there is an optimal die thickness that provides the lowest junction temperature. It is expected that the actual results depend on the thermoelectric geometry, material, and power map on the active side of the die.