Diffused bitline replacement in stacked wafer memory

Techniques are disclosed herein for creating metal BLs in stacked wafer memory. Using techniques described herein, metal BLs are created on a bottom surface of a wafer. The metal BLs can be created using different processes. In some configurations, a salicide process is utilized. In other configurations, a damascene process is utilized. Using metal reduces the resistance of the BLs as compared to using non-metal diffused BLs. In some configurations, wafers are stacked and bonded together to form three-dimensional memory structures.

BACKGROUND

Memory technologies are struggling to keep up with the demands of computing devices. Not only are computing devices becoming smaller, these devices may utilize more bandwidth compared to previous devices. In an attempt to address these demands, different types of memory continue to be developed. Some of these memories include carbon nanotube random access memory (RAM), ferroelectric RAM (FRAM), magnetoresistive RAM (MRAM), phase-change memory (PCM), resistive RAM (ReRAM), and the like.

In some cases, three-dimensional (3D) integration technologies are used with different memory technologies to better utilize space as compared to a single layer of memory. Generally, 3D integration technologies include two or more layers of integrated circuits (ICs) including memory that are stacked vertically, and then connected using through-silicon vias (TSV). This stacking of memory can reduce interconnect wire length, which may result in improved performance and reduced power consumption. To access memory cells, wordlines (WLs) and bitlines (BLs) are utilized. In some memory technologies, BLs are buried within a silicon wafer that are located beneath the transistors and memory cells. Creating buried BLs that meet the performance requirements of some memory technologies can be challenging.

DETAILED DESCRIPTION

The following detailed description is directed to technologies for creating metal BLs in stacked wafer memory. Using techniques described herein, metal BLs are created on a bottom surface of a wafer. Using metal BLs reduces resistance and can increase performance of memory devices as compared to using non-metal buried BLs. According to examples described herein, wafers can be stacked and bonded together to form three-dimensional memory structures that include metal BLs.

As used herein, the term “wafer” refers to a thin slice of semiconductor material, such as a crystalline silicon, used in electronics for the fabrication of integrated circuits. A wafer serves as a substrate for microelectronic devices built in and over the wafer. In some examples, the wafer is an epitaxial wafer which may have different layers. For instance, the wafer can include different conductivity layers.

According to some configurations, the transistors and memory cell structures for the memory are created within the wafer. In some examples, trenches for defining BLs and WLs can be lithographically patterned and etched into the wafer. Oxide material is deposited to provide isolation between different areas of the wafer, such as the areas between BLs and WLs. Chemical-mechanical polishing (CMP), or some other polishing technique, can be used to remove the excess oxide material. Generally, the BLs are disposed under transistors (e.g., vertical transistors) of a transistor array and can be electrically connected to drain regions of the vertical transistors.

The transistor array is positioned above the BLs and includes an array of transistors, such as vertical pillar transistors, or some other type of transistors. Generally, vertical pillar transistors may be utilized to increase the device density on the wafer as compared to transistors that are not vertical pillar transistors.

The storage elements of memory cells may be positioned above the top of the transistors. The memory cells may include but are not limited to, dynamic RAM (DRAM), ferroelectric RAM (FRAM), magnetoresistive RAM (MRAM), phase-change memory (PCM), resistive RAM (ReRAM), nanotube random access memory (RAM), and the like. For static RAM (SRAM) memoires the memory cell may include cross coupled transistors at the same level as other transistors. Generally, any type of memory cell can be utilized. An electrical contact can also be created that couples to one or more of the transistors or some other connector. In some instances, the electrical contact is a metal, such as tungsten.

The metal BLs are created on the bottom surface of the wafer. In some examples, the wafer is flipped over such that the bottom surface of the wafer is on top, and the top surface of the memory cells is on the bottom. Flipping the wafer is performed to make the process of removing a portion of the bottom of the wafer easier as compared to not flipping the wafer. A handle wafer may be attached to the top surface of the substrate to assist with flipping and further processing. After flipping the wafer, the substrate can be removed using a wafer thinning process. For instance, back-grinding, CMP, and/or some other wafer thinning process can performed to expose the diffused BLs. Generally, wafer thinning is the process of removing material from the backside of a wafer to a desired final target thickness. Prior to back-grinding, wafers are typically laminated with UV-curable back-grinding tape, which helps protect the wafer from damage. In some configurations, all or a portion of the diffused BLs may also be removed.

After any back-grinding is performed, one or more processes may be performed to increase the conductivity of the diffused BLs, or the region beneath the transistors forming BLs. For example, additional doping of the diffused BLs can be performed, in-situ doped silicon may be epitaxially grown (e.g., using vapor-phase epitaxy (VPE), chemical vapor deposition (CVD), . . . ), and/or metal BLs may be created. The metal BLs can be created using different technologies, such as a self-aligned silicide (“salicide”) process or a damascene process. The salicide process may include, for example, deposition of a thin transition metal layer over the bottom layer of the wafer. Different metals can be utilized. Some example metals include, but are not limited to titanium, cobalt, nickel, platinum, and tungsten.

The wafer may then be heated (e.g., rapid thermal anneal (RTA), laser spike, etc.) allowing the transition metal to react with the silicon associated with the BLs created earlier to form a low-resistance transition metal silicide. Generally, silicides provide benefits such as being low resistance, being easy to etch, providing good contacts to other materials, and being compatible with different semiconductor processes. Following the reaction of the transition metal with the BL regions of the wafer, any remaining transition metal is cleaned (e.g., by chemical etching).

In other configurations, the metal BLs can be created using a damascene process. According to some examples, a barrier layer may be utilized to protect the other components of the wafer. The barrier layer may be formed on the surfaces of trenches using a process such as a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process. In the damascene process, a portion of the BL trenches may be etched where the metal BLs are to be located. Copper, or other electrically conductive metal, is disposed such that the metal overfills the trenches. CMP, or other technique, can be used to remove the metal that extends above the top of the trenches such that the BLs are isolated. The metal that is located within the trenches becomes the metal BLs.

Two or more wafers can be stacked and bonded to create three-dimensional memory structures. Different boding processes can be utilized. For example, direct or fusion bonding, surface activated bonding, plasma activated bonding, glass frit bonding, adhesive bonding, and the like may be utilized. According to some examples, direct or fusion bonding may be utilized to bond the different layers that define the three-dimensional memory structure. Prior to bonding one or more additional layers may be deposited on the wafer. For example, an oxide layer may be deposited to protect the metal BLs and/or to increase the strength of the bond, depending on the bonding process utilized. In some configurations, a vertical via is etched through the layers and then filled with a conductive material to electronically couple the different layers of the three-dimensional memory structure. In other configurations, the metal BLs on one memory layer can be connected to metal BLs on a different memory layer.

Additional details regarding the various technologies and processes described above will be presented below with regard toFIGS. 1-6.

In the following detailed description, references are made to the accompanying drawings that form a part hereof, and that show, by way of illustration, specific examples. The drawings herein are not drawn to scale. Like numerals represent like elements throughout the several figures (which may be referred to herein as a “FIG.” or “FIGS.”).

FIG. 1is a schematic diagram depicting an illustrative memory array that includes metal BLs. As illustrated,FIG. 1shows a schematic diagram105of a memory array, a cross-section115of a transistor array and memory cells, and a cross-section125that includes metal BLs disposed on a bottom surface of the wafer.

Schematic diagram105illustrates a memory array, such as a 4F2memory array that includes vertical transistors, such as a vertical pillar transistor (VPT) coupled to memory cell storage elements110. As will be appreciated, conventional techniques can be used to create the memory array, such as 4F2memory array. While a 4F2memory array is illustrated, other memory arrays can be utilized. Generally, the memory cells are addressable via the WLs104, such as WLs104A-104B), and BLs102, such as BLs102A-102C. As illustrated, the channel of a VPT is built on a buried BL102and under a memory cell storage element110. The buried BLs may be created by doping a portion of the substrate101and etching through it to isolate the individual BLs, such as BLs102A,102B, and102C. The WLs104of the VPT surround the silicon channel and are used to control the gate of the VPT.

Diagram105illustrates four WLs104A-104D, that are positioned above and perpendicular to the BLs102A-102C such that the WLs104and the BLs102intersect at each of the memory cells. As illustrated, the BLs102are diffused BLs which are positioned above the substrate101. According to some configurations, the diffused BLs are doped regions of the substrate such that conductivity of the BLs102is increased.

Cross-section115shows a transistor array and memory cell storage elements built on top of the transistors. Different techniques can be utilized to create the transistors that form the transistor array. The transistors120and memory cell storage elements110form a plurality of memory cells that form a memory array.

Generally, the memory array includes a plurality of memory cells that are arranged in columns and rows. As can be seen by referring to diagram105, the different rows are connected to different WLs and the memory cells in different columns are connected to different WLs. The BLs and the WLs are used to address the memory cells. The gates of the transistors120in a row are electronically connected to the same WL. The memory cells in different columns are connected to different BLs102.

According to some configurations, the BLs and WLs may be defined by removing portions of the wafer (e.g., by etching). The BLs and WLs can be created using shallow trench isolation (STI) or other techniques or procedures. Generally, the STI process involves etching a pattern of trenches in the silicon of the wafer, depositing one or more dielectric materials (such as silicon dioxide) to fill the trenches, and removing the excess material using a polishing technique such as CMP, or some other technique.

In some examples, after creating the buried BLs, which may also be referred to herein as “diffused BLs”, and the WLs in the silicon, the transistors120may be formed. According to some examples, the WLs are etched back to remove a portion of the material from the WLs. The gates of the transistors can then be created. For instance, isotropic sputtering can be used to deposit the gate material. In other examples, such as for a metalsemiconductor field-effect transistor (MESFET) the gate oxide can be grown using a chemical vapor deposition (CVD) process, a thermal oxidation process, or some other process.

After forming the gates, oxide can be deposited to cover the gate material. The excess gate material and oxide can be removed using CMP, or other techniques. The gates of transistors120A are then split by etching, or other techniques. The memory cell storage elements110are then built on a top surface of the transistors. The memory cell storage elements110may be built using memory technologies such as, but not limited to SRAM, DRAM, FRAM, MRAM, PCM, ReRAM, nanotube, and the like. Generally, any type of memory cell storage element110can be created using the techniques described herein.

Cross-section125illustrates metal BLs130disposed on a bottom surface of the wafer. In some examples, the wafer is flipped over such that the bottom surface108of the wafer is located on top, and the top surface of the memory cell storage elements110, or a material covering the memory cell storage elements110is located on the bottom. After flipping the wafer, the bottom substrate layer101of the wafer can be removed. For instance, as briefly discussed above, back-grinding, or other technique, can be performed to remove the substrate101and expose the diffused BLs102. According to some examples, none, a portion, or all of the diffused BLs102can be removed by further back-grinding, or some other technique.

After wafer thinning is performed, one or more procedures can be performed. For example, the metal BLs130can be created. The metal BLs130can be created using different techniques or procedures. For example, metal BLs130can be created using a salicide process. The salicide process may include deposition of a thin transition metal layer over the bottom layer of the wafer. The wafer may then be heated (e.g., by a rapid thermal anneal (RTA) process, laser spike process, etc.) allowing the transition metal to react with the silicon to form a low-resistance transition metal silicide. Following the reaction, any remaining transition metal may be cleaned (e.g., by chemical etching).

Two or more wafers can be stacked and bonded to create three-dimensional memory structures. Different bonding processes can be utilized. For example, direct or fusion bonding, surface activated bonding, Plasma activated bonding, Glass frit bonding, adhesive bonding, and the like may be utilized. According to some examples, direct or fusion bonding may be utilized to bond the different layers that define the three-dimensional memory structure. In some configurations, a vertical via is etched through the layers and then filled with a conductive material to electrically couple the different layers. The resistivity of the metal BLs130is less compared to non-metal BLs, thereby allowing better performance and less resistance between the different layers of the three-dimensional memory structure as compared to non-metal BLs.

In other configurations, the metal BLs130can be created using a damascene process. According to some examples, a barrier layer is utilized to protect the other components of the wafer. In the damascene process, a portion of the BL trenches are etched where the metal BLs are to be located. Copper, or other conductive metal (e.g., tungsten, titanium, aluminum, titanium nitride, tantalum, tantalum nitride, cobalt, nickel, . . . ), is disposed such that the metal overfills the trenches. CMP, or other techniques, can be used to remove the metal that extends above the top of the trenches such that the BLs are electrically isolated. The metal that is located within the trenches becomes the metal BLs. The metal utilized may be a metal or a metal alloy material such as but not limited to copper, tungsten, cobalt, aluminum, or any other suitable metal or metal alloy fill material.

According to some configurations, doping can be performed from the backside of the wafer such that the diffused BLs102are more conductive. In yet other configurations, in-situ doped silicon may be epitaxially grown (e.g., using vapor-phase epitaxy (VPE), chemical vapor deposition (CVD), . . . ) on the bottom portion of the diffused BLs102. Given that the backside is accessible, the source regions (or drain regions) of the transistors may be formed or augmented. In some instances, this may reduce or eliminate certain doping steps from the top side earlier in the process thereby reducing cost and complexity. As discussed above, any combination of these approaches can be performed. More details regarding creating the metal BLs130are provided below with reference toFIGS. 2-6.

FIG. 2Ais a schematic diagram depicting an illustrative memory array that includes metal BLs that are adjacent to transistors120associated with memory cell storage elements110. As illustrated, wafer200shows the BLs130located adjacent to a bottom surface of the transistors120.

As briefly discussed above, the thickness of the wafer is reduced before creating the metal BLs130. In some configurations, the substrate101and other material covering the bottom of the transistors120is thinned. According to some examples, the material covering the bottom of the transistors120may be removed such that the metal BLs130are in direct contact with the bottom surface of the transistors120. In other cases, substantially all of the material of the wafer covering the bottom of the transistors120is removed. For example, a portion of the diffused BLs102remain. According to some examples, a timed back-grinding process can be performed. For instance, back-grinding can be performed for a predetermined time such that a desired amount of material is consistently removed from different wafers. According to other examples, CMP process can be performed to remove the material covering the bottom of the transistors120and stop at the bottom of dielectrics such as the bottom of shallow trench isolations.

FIG. 2Bis a schematic diagram depicting an illustrative memory array that includes metal BLs130and regions210located between adjacent transistors120to isolate the transistors. Isolating the transistors120can decrease the capacitance and increase the electrical resistance such that unwanted electrical flow of charge carriers is diminished.

In some examples, regions between adjacent areas may be isolated by depositing a material that has different electrical properties from the material comprising the transistors. According to some examples, the material deposited within the isolation regions210is a low-k dielectric material. A low-k dielectric has a small relative dielectric constant relative to silicon dioxide. Generally, replacing the silicon dioxide with a low-k dielectric reduces parasitic capacitance. As illustrated, the isolation regions include210A,210B,210C,210D,210E,210F,210G,210H,210I,210J, and210K.

FIG. 3is a schematic diagram depicting an illustrative three-dimensional memory array that includes metal BLs130. As illustrated, 3D memory300includes a first memory array305stacked on a second memory array315that is stacked on a third memory array325. While three memory arrays are shown stacked in this example, in other examples more or fewer memory arrays may be stacked and/or bonded to create 3D memory.

The memory arrays305,315, and325can be electronically coupled via the metal BLs130by vertically etching an area310and filling the area with a conductive material, such as Tungsten, or some other metal or material that is utilized in electrical connections. In other examples, the metal BLs130can be wired together as illustrated by indicator312.

FIG. 4is a schematic diagram depicting different stages for creating metal BLs in a memory array using a salicide process. As discussed, the metal BLs130can be created using different technologies. For example, metal BLs130can be created using a salicide process.

As illustrated,FIG. 4includes a cross-section405that shows diffused BLs created during an earlier stage of the fabrication process. Referring to cross-section405, a plurality of diffused BLs410A,410B,410C,410D, and410E are shown. As discussed above, trenches can be etched into a wafer before forming the transistors120or building the memory cells110. The BLs410A,410B,410C,410D, and410E are isolated from regions402A,402B,402C,402D,402E, and402F.

Cross-section415illustrates deposition of a metal layer412on the bottom of the wafer. As discussed herein, the salicide process can include deposition of a thin transition metal layer over all or a portion of the bottom layer of the wafer.

Cross-section425illustrates the wafer after applying heat to the wafer. For example, the wafer can be heated using rapid thermal anneal (RTA), laser spikes, or the like. The heating of the wafer allows the metal layer412to react with the silicon of the wafer to form a low-resistance transition metal silicide. In the illustrated examples, the transition metal does not react with regions402A,402B,402C,402D,402E, and402F of the wafer but does react with the diffused BLs410A,410B,410C,410D, and410E. Referring to cross-section view425it can be seen that a portion of the metal layer has interacted with the BLs410A,410B,410C,410D, and410E.

Cross-section435illustrates the wafer after cleaning. Following the reaction of the metal with the wafer caused by the heating, any remaining transition metal is cleaned (e.g., by CMP). Metal414A,414B,414C,414D, and414E is shown covering BLs410A,410B,410C,410D, and410E.

FIG. 5is a schematic diagram depicting different stages for creating metal BLs using a damascene process in a memory array.

As illustrated,FIG. 5includes a cross-section505that shows diffused BLs130created during an earlier stage of the fabrication process. Referring to cross-section505, a plurality of diffused BLs410A,410B,410C,410D, and410E are shown. As discussed above, trenches can be etched into a wafer before forming the transistors or building the memory cells. The BLs410A,410B,410C,410D, and410E are isolated from regions402A,402B,402C,402D,402E, and402F.

Cross-section515shows etching a lower portion of the BLs410A,410B,410C,410D, and410E. As illustrated, the etching removes regions520A,520B,520C,520D, and520E.

According to some configurations, one or more processes may be performed to increase the conductivity of the diffused BLs. For example, additional doping of the diffused BLs can be performed, in-situ doped silicon may be epitaxially grown (e.g., using vapor-phase epitaxy (VPE), chemical vapor deposition (CVD), . . . ), and the like.

Cross-section525shows creating a barrier layer (or liner) within the BLs410A,410B,410C,410D, and410E before depositing metal using the damascene process. In some configurations, a silicide process is used to create the barrier layer that is between the top of the regions520A,520B,520C,520D, and520E and the bottom of the BLs410A,410B,410C,410D, and410E as illustrated by elements530A,530B,530C,530D, and530E. In other examples, the barrier layer may cover the walls formed between the BLs410A,410B,410C,410D, and410E and the regions402A,402B,402C,402D,402E, and402F. In yet other examples, a barrier layer may not be created when creating metal BLs using the process illustrated inFIG. 5.

Cross-section535shows an area540that is filled with a metal using a damascene process. According to some configurations, copper, tungsten, or other metal or alloy, is disposed within area540such that the metal overfills the trenches. In yet other examples, aluminum can be utilized.

Cross-section545shows the wafer after cleaning the wafer to remove the excess metal. According to some examples, CMP, or other technique, can be used to remove the metal that extends above the top of the trenches such that the metal BLs are isolated as illustrated by regions550A,550B,550C,550D, and550E.

Cross-section555shows the wafer after filling regions adjacent to the metal BLs regions with a low-k dielectric. In some examples, at least a portion of the regions402A,402B,402C,402D,402E, and402F are etched. Regions560A,560B,560C,560D, and560E are then filled with a low-k dielectric material.

FIG. 6is a flow diagram showing an example process600that illustrates aspects of creating metal BLs130in a three-dimensional memory in accordance with examples described herein.

The logical operations described herein are referred to variously as operations, structural devices, acts, or modules. These operations, structural devices, acts, and modules may be implemented using different techniques or procedures. It should also be appreciated that more or fewer operations may be performed than shown in the FIGS. and described herein. These operations may also be performed in parallel, or in a different order than those described herein.

The process600may include at610creating elements of the memory array. As discussed above, the transistors120, the memory cell storage elements110and the diffused BLs102and WLs104can be created using, for example, shallow trench isolation (STI). STI includes etching the silicon wafer to create trenches that define the BLs and WLs. As also discussed above, different techniques can be utilized depending on the type of transistors being created. The memory cell storage elements110may be created using one or more different memory technologies. For example, the memory cells may include but are not limited FRAM, MRAM, PCM, ReRAM, nanotube, DRAM, and the like.

At612, the memory cells are created. As discussed above, the memory cells may be created using one or more different memory technologies. For example, the memory cells may include but are not limited to SRAM, DRAM, FRAM, MRAM, PCM, ReRAM, nanotube, and the like.

At614, an electrical contact may be created for the layer. The electrical contact may be a metal, such as but not limited to tungsten, or some other metal. In other examples, the metal BLs130may be used to electrically couple the different layers of the memory array,

At616, the wafer is flipped, and wafer thinning is performed. As discussed above, the wafer is flipped such that the top of the wafer is now the bottom of the wafer, and the bottom of the wafer closest to the bottom surface of the transistors is now the top surface. All or a portion of the material disposed below the bottom surface of the transistors can be back-grinded and/or removed using some other technique or procedure.

At618, one or more procedures can be performed after thinning the backside of the wafer. As discussed above, additional doping of the diffused BLs can be performed, and/or in-situ doped silicon may be epitaxially grown (e.g., using vapor-phase epitaxy (VPE), chemical vapor deposition (CVD), . . . ).

At620, the metal BLs are created. As discussed above, the metal BLs are deposited on the bottom side of the wafer. In some examples, the metal BLs130are disposed using a salicide process that includes depositing a silicide metal on the bottom of the wafer, performing a heat/anneal process (e.g., using RTA, laser spike), and then removing the portion of the metal such that the BLs are exposed. In other examples, a damascene process can be utilized to create BLs of copper, or some other metal. CMP can be utilized to isolate the metal BLs.

In some examples, a liner, or barrier layer, may be placed before electroplating the metal in the damascene process. For example, a barrier layer can be created that includes a dielectric material, such as a low-K dielectric. A low-K dielectric material is a material having a dielectric constant that is lower than the dielectric constant of silicon dioxide.

At620, the wafer can be bonded to another wafer. As discussed above, the wafer can be bound using a variety of different bonding techniques. In some examples, to create a memory structure using stacked wafers, a via is created, and then filled with a metal to electronically couple the metal contacts located on the different layers. In other examples, the different layers of the memory can be electronically coupled using wires that couple to the metal BLs130or some other element within each of the layers.

Based on the foregoing, it should be appreciated that technologies for creating metal BLs have been presented herein. The subject matter described above is provided by way of illustration only and should not be construed as limiting. Furthermore, the claimed subject matter is not limited to implementations that solve any or all disadvantages noted in any part of this disclosure. Various modifications and changes may be made to the subject matter described herein without following the example examples and applications illustrated and described, and without departing from the true spirit and scope of the present invention, which is set forth in the following claims.