Apparatuses and methods for charge pump regulation

Certain embodiments of the present invention include an apparatus comprising a charge pump, configured to provide an output voltage at an output node of the charge pump, and a charge pump regulator circuit coupled to the charge pump. One such charge pump regulator circuit is configured to control the charge pump to increase the output voltage during a first period of time. Such a charge pump regulator circuit can also cause a node of a circuit coupled to the output node of the charge pump to reach a target voltage level during a second time period.

BACKGROUND

A charge pump generally includes capacitors and/or other electrical components to create either a higher or lower voltage power source. Charge pumps are typical in many different types of electronics and are often used as high voltage power supplies. A charge pump can be characterized in terms of its output impedance. The smaller the output impedance of the pump, the closer it will behave as an ideal power supply (an ideal power supply has zero output impedance). For example, during the programming stage of non-volatile memories, charge pumps are often used to provide a programming voltage to a memory cell of the memory. Typical charge pumps also include a charge pump regulation loop that controls the output voltage of the charge pump. For example, the charge pump “on-off” regulation loop might detect when the output voltage of the charge pump has reached a target voltage level and deactivate the charge pump until the regulation loop determines that the output voltage of the charge pump falls below the target voltage level. Once the charge pump has reached the target voltage level for a given charge cycle, the charge pump regulation loop might activate and deactivate the charge pump as necessary to maintain the output voltage of the charge pump around the target voltage level. In this condition, the amount of charge available to the load per unit of time is reduced, thus the output impedance of the charge pump increases and its performance is reduced. Traditional regulation loops only account for the output voltage of the charge pump, without accounting for whether or not the circuit elements receiving charge from the pump are provided with sufficient voltage.

DETAILED DESCRIPTION

Certain details are set forth below to provide a sufficient understanding of embodiments of the invention. However, it will be clear to one skilled in the art that embodiments of the invention may be practiced without these particular details. Moreover, the particular embodiments of the present invention described herein are provided by way of example and should not be used to limit the scope of the invention to these particular embodiments. In other instances, well-known circuits, control signals, timing protocols, and software operations have not been shown in detail in order to avoid unnecessarily obscuring the disclosure.

In highly integrated circuits, such as integrated circuit memory (e.g., three-dimensional (3D) NAND memory), the integrated circuitry may result in physical limitations that adversely affect the performance of the circuit. One of the possible physical limitations is layout bottlenecks, which result from a limited space within the apparatus to realize connections between components. Layout bottlenecks act like resistors positioned between components. As a result of this behavior, a voltage drop occurs between connected components. In the case of 3D NAND memory, a bottlenecking resistance can occur between a charge pump and a word line being programmed by the charge pump. The consequence of this layout and the bottlenecking resistance is that traditional charge pump regulators will determine that the output voltage of the charge pump reaches the target voltage level before the word line reaches the target voltage level. When the output voltage of the charge pump reaches the target voltage level, a regulator circuit may deactivate the charge pump, increasing the output impedance of the pump and reducing the rate at which charge is delivered to the word line (thus slowing the programming process).

For example, if a word line has a target programming voltage level of 26V, when the output voltage of the charge pump reaches the target level of 26V, the word line may not yet have reached the target voltage level, such as due to a voltage drop between the charge pump and the word line due to the bottlenecking resistance. The practical effect is that the voltage supplied to the word line is less than the voltage provided by the charge pump. As mentioned above, the typical charge pump regulator detects the output voltage level of the charge pump but not the voltage level of the word line and deactivates the charge pump once the target voltage level is detected. The charge pump effectively slows down the rate at which voltage is provided to the word line and as a result the rate at which the word line is charging slows. This effect limits the overall speed of the 3D NAND memory by reducing the speed at which word lines may be programmed. Disclosed herein are various charge pump regulator circuits which may, for example, improve the charging time for the word lines.

Exemplary embodiments of the present invention will now be discussed with reference to the several drawings.

FIG. 1illustrates an apparatus100(e.g., an integrated circuit, a memory device, a memory system, an electronic device or system, a smart phone, a tablet, a computer, a server, etc.) according to an embodiment of the disclosure. Apparatus100may generally include a charge pump102, a charge pump regulator circuit104, an effective resistance106, a circuit108, an AND gate110, and an oscillator input112.

Charge pump102can include an electrical circuit that receives an input signal and outputs a signal at an output node having a higher absolute output voltage (e.g., more positive or more negative) than that of the input signal. Charge pump102may be any circuit element or combination of circuit elements capable of receiving an input voltage and outputting a higher absolute output voltage. Charge pump102may include, for example, capacitors, transistors, and/or any other appropriate circuit components. In various embodiments, the charge pump102may be used to provide one or more circuits108with a voltage at a particular target voltage level. The output node of charge pump102is generally coupled to one or more circuits108and a charge pump regulator circuit104. Operation of the charge pump102is described in further detail below with respect toFIG. 6.

Charge pump regulator circuit104can include an electrical circuit coupled to the output node of charge pump102. A charge pump regulator circuit104may include one or more circuit components configured to provide a regulator circuit output signal114to selectively activate or deactivate the charge pump102. Charge pump regulator circuit104may control the charge pump102to be deactivated after the charge pump102has provided sufficient charge to the circuits108to which the charge pump102is coupled. Charge pump regulator circuit104may include a comparator (seeFIGS. 2-4), the inputs and/or output of which may be configured to ensure that charge pump102remains active until sufficient time has passed for the circuits108to reach the target voltage level.

A circuit108can include circuit components, elements, and or devices that receive charge from charge pump102in order to reach a target voltage level at a particular node of the circuit108. For simplicity, the circuits108may be modeled as capacitors that receive charge during the time period that the charge pump102is active. However, those skilled in the art will appreciate that the circuits108may be any circuit component or combination of components that can be charged over time. For example, in non-volatile memories, the circuits may represent for example, word lines, word line drivers, or decoder circuits of the memory that charge as part of the programming function of the memory. In such embodiments, the circuits108may have a target voltage level, Vpgm, to which a node of the circuits should be charged in order to satisfactorily complete the programming function.

As discussed above, one physical limitation of tightly integrated circuits, such as 3D NAND memories, is an unavoidable impedance, or effective resistance, that results from layout bottlenecks in the device layout. This physical constraint may be modeled as an effective resistance106in the embodiment ofFIG. 1. Those skilled in the art will appreciate that effective resistance106may not be a separate resistance circuit, but rather an artifact of physical limitations of conductive signal lines when charge is provided through the tightly integrated apparatus100. Effective resistance106may result in a voltage drop, which may cause the level of voltage at a node of the circuit108to be less than the level of the voltage being provided at an output node of the charge pump102.

To control the output of the charge pump102, a charge pump regulator circuit104may be coupled to the output node of the charge pump102. Charge pump regulator circuit104may be coupled to an AND gate110, which also receives, as an input, a signal from an oscillator112. The oscillator112can provide a periodic signal used for the charging operation of the charge pump102. For example, in a 3D NAND memory, the oscillator may provide a periodic signal during the program operation of the circuits108. The AND gate110may provide a periodic signal (e.g., based on the periodic signal from the oscillator) or a signal having a constant level (e.g., a logically low signal) based on the regulator circuit output signal114. For example, when the regulator circuit output signal114is a logically low signal, the AND gate110provides a logically low signal to the charge pump102, regardless of the state of the signal provided by the oscillator112. As a result, the charge pump102does not operate to provide a pumped output voltage. In contrast, when the regulator circuit output signal114is a logically high signal, the AND gate110provides as an output the periodic signal provided to it by the oscillator112. As a result, the charge pump102operates to provide a pumped output voltage. Thus, the charge pump regulator circuit104can effectively activate or deactivate the charge pump102for operation. In an example embodiment, an AND gate is a simple implementation for “on-off” regulation scheme, although other gates can be used as well.

FIG. 2is a schematic diagram depicting an apparatus, generally designated200, in accordance with an embodiment of the present invention. Apparatus200generally includes a charge pump202, a charge pump regulator circuit204, an effective resistance206, a circuit208, an AND gate210, an oscillator212, and a regulator output signal214. In the embodiment ofFIG. 2, charge pump202, charge pump regulator circuit204, effective resistance206, circuit208, AND gate210, oscillator212, and regulator output signal214may each be implemented as charge pump102, charge pump regulator circuit104, effective resistance106, circuit108, AND gate110, oscillator112, and regulator output signal114, respectively, as described above with respect toFIG. 1.

Charge pump regulator circuit204may include a comparator216. Comparator216may be any type of comparator capable of receiving two input signals, and outputting a signal based on which of the two input signals has a greater voltage, such as an operational amplifier. In the embodiment ofFIG. 2, comparator216provides the regulator output signal214to the AND gate210. Comparator216may receive two input signals, feedback signal218and reference signal226. Each of feedback signal218and reference signal226may have an associated voltage level. The voltage level of the reference signal226may be related to the target output voltage level for the charge pump202. For example, the voltage level of the reference signal may be equal to the target output voltage level, or in some embodiments, scaled to be less than the target output voltage level.

As shown inFIG. 2, if the voltage level of feedback signal218is less than the voltage level of reference signal226, then comparator216outputs a high regulator output signal214to AND gate210. As a result, as previously discussed, the control logic210provides a periodic signal to the charge pump202that is based on the periodic signal provided by the oscillator212so that the charge pump202operates to provide a pumped output voltage. If the voltage level associated with feedback signal218is not less than the voltage level of reference signal226, then comparator216provides a low regulator output signal214to AND gate210, which deactivates charge pump202. Those skilled in the art will appreciate that the embodiment of charge pump regulator circuit204, as described below may include greater, fewer, or different components than those described without departing from the scope of this disclosure.

Feedback signal218may be provided by a parallel RC circuit, including a resistor220and a capacitor224, coupled to a second resistor222, as shown inFIG. 2. In various embodiments, the resistors220and222may be fixed resistors, variable resistors, or a combination thereof. The output node of charge pump202may also be coupled to the parallel RC circuit. In the embodiment ofFIG. 2, the voltage level associated with feedback signal218may be a fraction of the output voltage level of charge pump202, where the fraction is determined by the relative resistances of the resistors220and222. For example, if resistor220has a resistance R1and resistor222has a resistance R2, then the voltage level of feedback signal218equals the level of the voltage output by charge pump202reduced by a factor of R2/(R1+R2). In operation, as the output voltage level of the charge pump202increases, so does the voltage level of feedback signal218.

Reference signal226may be configurable to change the reference voltage against which feedback voltage218may be compared by comparator216. In the embodiment ofFIG. 2, reference signal226may have a voltage level that is related to (e.g., scaled down from the actual voltage) the target voltage levels of charge pump202and circuits208(e.g., 26V). For example, the voltage level of the reference signal226may be reduced by the factor of the parallel RC circuit. However, as noted above, the voltage level at a node of the circuit208may be less than the level of the voltage on the output node of the charge pump202because of, for example, a voltage drop across effective resistance206. Therefore, while the output voltage of the charge pump202reaches the target voltage level, the target nodes of circuits208may have not yet reached the target voltage level. To account for this voltage difference, charge pump regulator circuit204may detect the occurrence of t0, and raise the voltage level of reference signal226for a time period, Δt, so that the voltage level of reference signal226remains higher for that time period. Raising the voltage level of the reference signal226effectively raises the target voltage level for the charge pump202. As a result, charge pump202remains active until the level of the output voltage of the charge pump202reaches the increased target voltage level. By keeping charge pump202active after it reaches the initial target voltage level, the time required for the target nodes of circuits208to reach the desired target voltage level may be reduced, which can result in an overall increase in speed for a memory (e.g., 3D NAND memory).

To effect the transition of the voltage associated with reference signal226, charge pump regulator circuit204may include a t0edge detector circuit228, a Δt circuit230, a multiplexer circuit234, and a number of reference voltages236. The t0edge detection circuit228may be coupled to regulator output signal214and detect when the value of the regulator output signal changes, which represents the point in time at which the output node of charge pump202reaches the initial target voltage level (i.e., t0). In one embodiment, t0edge detector circuit228may be implemented using a simple latch circuit, such as a D flip-flop.

The Δt circuit230determines, either statically or dynamically, the amount of time, Δt, that charge pump202should remain active for the target nodes of circuits208to reach the desired target voltage level. Δt may be a time period based on known quantities of charge pump202output, effective resistance206, and circuits208. Accordingly, Δt may be embodied in preprogrammed logic, as will be appreciated by one skilled in the art. In this embodiment, Δt is statically determined based on known quantities. In other embodiments, Δt may be dynamically determined. Dynamic determination of Δt may be implemented based on the rate at which the circuits208charge prior to the time t0, such as by measuring the rate of voltage increase at target nodes of circuits208prior to t0and calculating the additional time necessary, Δt, for the target nodes of circuits208to reach the target voltage level.

Multiplexer234may include any circuit component or combination of circuit components capable of receiving multiple input signals and a selector signal and providing an output signal based on the input signals and the selector signal. Reference voltages236may be a set of signals, each of which has a different associated voltage level. In various embodiments, reference voltages236may be provided by a voltage divider circuit, as shown inFIG. 2. Reference voltages236may provide the input signals to multiplexer234, and the output signal232of Δt circuit230may provide the selector signal to multiplexer234to select which of the reference voltages236to be provided as the reference voltage226, as shown inFIG. 2.

In operation, the apparatus200operates to increase the output voltage from the beginning of the charge cycle until t0. Δt t0, the t0edge detection circuit228detects the transition of the regulator output signal214provided by comparator216. Upon detection of t0, the t0edge detection circuit228provides a triggering signal to Δt circuit230. The Δt circuit230determines, either statically or dynamically, the required Δt for which the charge pump should remain active and a new voltage that should be associated with reference signal226, as described above. The Δt circuit230may provide output signal232to multiplexer234as a multibit selector signal, which designates a particular reference voltage signal236to output. Multiplexer234may provide the designated reference voltage236to comparator216as reference signal226. In various embodiments, after the time period Δt expires, the Δt circuit230may provide a second output signal232to multiplexer234which designates that multiplexer234should reduce the voltage level of reference signal226provided to comparator216. By dynamically raising the voltage level of reference signal226, charge pump regulator circuit204may ensure that charge pump202continues to provide (e.g., supply) charge to circuits208for a sufficient amount of time to ensure that target nodes of circuits208reach the target voltage level.

FIG. 3is a schematic diagram depicting an apparatus, generally designated300, in accordance with an embodiment of the present invention. Apparatus300generally includes a charge pump302, a charge pump regulation circuit304, an effective resistance306, one or more circuits308, an AND gate310, and an oscillator312. Charge pump302, charge pump regulator circuit304, effective resistance306, circuits308, AND gate310, and oscillator312may each be implemented as charge pump102, charge pump regulator circuit104, effective resistance106, circuits108, AND gate110, and oscillator112, as described above with respect toFIG. 1.

Charge pump regulator circuit304may include a comparator316, which receives as inputs a reference signal326, and a feedback signal318, and outputs a regulator output signal314based on the relative voltages of the input signals. In the embodiment ofFIG. 3, the reference signal326may carry a fixed voltage. Feedback signal318may carry a configurable voltage, which may be manipulated during a charge cycle, as described in further detail below. Those skilled in the art will appreciate that the embodiment of charge pump regulator circuit304, as described below may include greater, fewer, or different components than those described without departing from the scope of this disclosure.

Feedback signal318may be provided by a parallel RC circuit coupled in series to a variable voltage divider. Feedback signal318may be related to the output voltage level of the charge pump302, for example, the voltage level of feedback signal318may be equal to the output voltage level of the charge pump302or configurably scaled to be less than the output voltage level of the charge pump302. The parallel RC circuit may include a resistor320, having a fixed resistance, R1, and a capacitor324, having a fixed capacitance, Cc. The parallel RC circuit may be coupled in series with a plurality of resistors322. The resistors322may be selectively included or excluded (by shorting the circuit around them) from feedback signal318by a decoder334to change the voltage level of feedback signal318. The output voltage signal of pump302may be scaled by the parallel RC circuit and the resistors322to provide feedback signal318. By selectively including or excluding resistors322, the factor by which the output voltage level of charge pump302is scaled may be changed, which results in a different voltage level provided by feedback voltage318.

Charge pump regulator circuit304may further include a t0edge detector circuit328coupled to regulator output signal314and coupled to a Δt circuit330, which is coupled to the decoder334. The t0edge detection circuit may be any combination of electronic components capable of detecting a change in the output signal of the regulator output signal314, and outputting a signal in response to detecting the change. In one embodiment, t0edge detector circuit328may be implemented using a simple latch circuit, such as a D flip-flop.

The Δt circuit330may be any combination of electronic components whose output reflects a particular period of time, Δt, between when the output node of the charge pump302reaches the target voltage level and when the target nodes of circuits308reach the target voltage level if the charge pump302remains active. The Δt circuit330may determine the time period either statically or dynamically, as described above with respect toFIG. 2. In the embodiment ofFIG. 3, Δt circuit330may determine a new scaling factor by which the output voltage level of charge pump302may be reduced so that the voltage level of feedback signal318is less than the voltage level of reference signal326until the voltage level of the target nodes of circuits308reaches the target voltage level. Based on the new scaling factor, Δt circuit330may provide a multibit selector signal332to decoder334. Decoder334may be any combination of electronic components capable of selectively activating one or more output signals responsive to a received input signal (i.e., selector signal334).

In operation, the embodiment ofFIG. 3provides a mechanism for selectively changing (e.g., altering, adjusting, modifying or the like) the voltage of feedback signal318responsive to the output node of charge pump302reaching the target voltage level in order to ensure that the charge pump302remains active for a time, Δt, during which the target nodes of circuits308continue to charge to the target voltage level. Initially, the charge pump302begins charging the circuits308and the voltage level of feedback signal318is less than the voltage level of reference signal326. As the output voltage level of the charge pump302increases, so does the voltage level of feedback signal318. When the output voltage level of the charge pump302reaches the target voltage level, the voltage level of feedback signal318becomes greater than the voltage level of reference signal326. In response, the comparator316changes the logical value of the regulator output signal314. The t0detector circuit328detects the change in the logical value of regulator output signal314, and transmits a signal to Δt circuit330. The Δt circuit330determines a new scaling factor which may be applied to the output voltage level of charge pump302to reduce the voltage level of feedback signal318for the statically or dynamically determined time period, Δt. The Δt circuit330provides a multibit selector signal332to decoder334, which initiates a change in the output signals of decoder334to selectively remove some of the resistors322from the circuit by shorting around the resistors322. By shorting the circuit around some of the resistors322, the total resistance of the variable voltage divider may be reduced, which also reduces the scaling factor applied to the output voltage level of the charge pump302and reduces the voltage level of feedback signal318. The reduced voltage level of feedback signal318may be less than the voltage level of reference signal326, which triggers the comparator316to change the logical value of regulator output signal314and reactivate the charge pump302. Decreasing the voltage level of feedback signal318effectively raises the target voltage level for the charge pump302. Once the time period Δt, has passed, the Δt circuit330may transmit a new multibit selector signal332to the decoder334, which resets the scaling factor to its original value and increases the voltage level of feedback signal318to a value greater than the voltage level of reference signal326, triggering a change in the logical value of regulator output signal314and deactivating the charge pump302.

FIG. 4is a schematic diagram depicting an apparatus, generally designated400, in accordance with an embodiment of the present invention. The embodiment ofFIG. 4generally includes a charge pump402, a charge pump regulator circuit404, an effective resistance406, one or more circuits408, an AND gate410, and an oscillator412. In various embodiments, charge pump402, charge pump regulator circuit404, effective resistance406, circuits408, AND gate410, and oscillator412may each be implemented as charge pump102, charge pump regulator circuit104, effective resistance106, circuits108, AND gate110, and oscillator112, respectively, as described above with respect toFIG. 1.

Charge pump regulator circuit404generally includes a comparator416, resistors420and422, capacitor424, reference signal426, t0edge detector circuit428, analog timer436, and multiplexer430. Resistor420and capacitor424may be coupled in parallel to form a parallel RC circuit. Charge pump402may be coupled to the parallel RC circuit which may be coupled to resistor422, and comparator416. The voltage level of the output node of charge pump402may be reduced by a scaling factor, which depends on the relative resistances of resistors420and422and the capacitance of capacitor424as described above with respect toFIG. 2. The parallel RC circuit and resistor422provide feedback signal418to comparator416, which has a voltage level related to the voltage level of the output node of the charge pump402(e.g., reduced by the scaling factor). Comparator416may receive, as a second input signal, reference signal426, which may have a constant voltage level associated with it (e.g., equal to a target voltage level of the charge pump402and circuits408). The output signal of the comparator416may be coupled to the multiplexer430and the t0edge detector circuit428. Those skilled in the art will appreciate that the embodiment of charge pump regulator circuit404, as described below may include greater, fewer, or different components than those described without departing from the scope of this disclosure.

The t0edge detector circuit428may be any combination of components capable of detecting a change in the logical value of the output of the comparator416. The t0edge detector circuit may include an AND gate432and a D flip-flop434, as shown inFIG. 4. In various embodiments, the output of the comparator may be coupled, either directly or indirectly, to the AND gate432. The output of AND gate432may be coupled to the clock input of the D flip-flop432. The D flip-flop432may receive as a data input, a constant voltage signal, such as Vcc. The output of the D flip-flop432may be the output of the t0edge detector circuit, and may be coupled to the multiplexer430as a selector signal and coupled to the analog timer circuit436.

The analog timer circuit436may include any combination of electronic components capable of charging for a particular (e.g., predetermined) period of time, and outputting a signal responsive to the particular time period elapsing. In the embodiment ofFIG. 4, analog timer circuit436generally includes a current starved inverter438, a capacitor440, and an inverter442having an associated threshold voltage. The current starved inverter438may be any combination of electronic components for which the propagation delay of the inverter is configurable. The capacitor440may be a fixed or trimmable capacitor, and may be used to configure the propagation delay of the current starved inverter438. In the embodiment ofFIG. 4, the capacitor440has a capacitance, Ctimer. The inverter442may be any type of inverter having a known threshold voltage, Vtrip. In the embodiment ofFIG. 4, the current starved inverter receives, as an input, the output of t0edge detector circuit428. The current starved inverter438is coupled to the capacitor440and the inverter442. The output of the inverter442may be coupled to the reset of D flip-flop434.

In operation, charge pump402increases the output voltage level at the circuit408and the parallel RC circuit which, in combination with resistor422, provides feedback signal418to comparator416. As the output voltage level of the charge pump402increases, so does the voltage level associated with feedback signal418. During the initial portion of the charging cycle, when the voltage level of the reference signal426is greater than the voltage level of the feedback signal418, the output of the comparator may be logically high, and the output of the t0edge detector circuit may be logically low, which will allow the output of the comparator to pass through the multiplexer430to regulator output signal414. When voltage at the output node of the charge pump402reaches the target voltage level at t0, the voltage level of feedback signal418will surpass the voltage level of reference signal426, triggering a change in the logical value of the output signal of the comparator416. When the output of comparator416changes, the output signal of the AND gate432may change its logical value.

As described above, AND gate432may be coupled to the clock input of the D flip-flop434. Accordingly, when the output of the AND gate432changes, the output of D flip-flop434changes to reflect the constant voltage applied to the data input of the D flip-flop434. When the output of the D flip-flop434changes, the selector signal444may change the regulator output signal414of the multiplexer430to be logically high based on a constant input signal446. The logically high output of the D flip-flop434triggered by the transition of the comparator output may also be provided to the analog timer circuit436as described above. The output of the D flip-flop434may pass through the current starved inverter438and begin to charge the capacitor440. During the particular time, Δt, charge may build up on the capacitor440until the voltage reaches the threshold voltage, Vtripof the inverter442. Once the threshold voltage is reached (i.e., after the time period, Δt, has elapsed), the output of the inverter442may change and provide a signal to the reset input of the D flip-flop434. Once the D flip-flop is reset, the selector signal444may reset to a logically low value, which triggers the multiplexer430to allow the output of the comparator to pass to regulator output signal414.

The effect of charge pump regulator circuit404is to allow the charge pump402to charge until the voltage on an output node of the charge pump402reaches the target voltage level, and then to delay the output of the comparator by a particular time period, Δt, using an analog timer circuit. During the timer period, Δt, the charge pump402may continue to provide charge to the circuits408until the voltage at target nodes of the circuits408reaches the target voltage level.

FIGS. 5A-Cdepict timing diagrams for an apparatus in accordance with the embodiment ofFIG. 2.FIG. 5Adepicts the value of reference signal226during a charge cycle. From the beginning of the charge cycle until t0, reference signal226has a first voltage level, Vref. At time t0, the voltage of the reference signal226increases to a second voltage level, Vref′. Reference signal226maintains the second voltage level for a time period, Δt, and then decreases to the first voltage level.FIG. 5Bdepicts the value of feedback signal318during a charge cycle. From the beginning of the charge cycle until t0, feedback signal318has a first voltage level, VN. At time t0, the voltage of the feedback signal318decreases to a second voltage level, VN′. Feedback signal318maintains the second voltage level for a time period, Δt, and then increases back to the first voltage level.FIG. 5Cdepicts the voltage at a target node of the circuit208during the same time period asFIG. 5A or 5B. From the beginning of the charge cycle to a time, t0, the voltage supplied to the circuits208increases approximately linearly. Without the charge pump regulator circuit204, at t0the rate at which voltage is supplied to circuits208would decrease as the charge pump202begins to activate and deactivate. With the charge pump regulator circuit204, at t0the increase in the voltage level of reference signal226controls the charge pump202to remain active and results in the target nodes of circuits208being charged to the target voltage level more quickly than if the voltage level of the reference signal226remained constant.

FIG. 6depicts a charge pump, generally designated600, in accordance with an embodiment of the present invention. Charge pump600may be implemented as charge pump102,202,302, and/or402as described above. Charge pump600may include a plurality of charge pump stages602coupled in series. Each charge pump stage may include a capacitor604having an associated capacitance (e.g., C1, C2, etc.) coupled to a clock signal. Capacitors604in alternating charge pump stages602may receive non-overlapping clock signals. The charge pump may receive as an input a voltage VDDand provide a charge pump output signal to a charge pump regulator circuit (e.g., charge pump regulator circuit104) and a circuit (e.g., circuit108) as described above with respect toFIGS. 1-4. The circuits may represent, for example, word lines, word line drivers or decoder circuits of the memory that charge as part of the programming function of the memory.

FIG. 7illustrates a portion of a memory700according to an embodiment of the present invention. The memory700includes an array702of memory cells. The memory cells may be non-volatile memory cells, but may also be volatile memory cells (e.g., DRAM, SDRAM), or any other type of memory cells. Command signals, address signals and write data signals are applied to the memory700as sets of sequential input/output (“I/O”) signals transmitted through an I/O bus704. Similarly, read data signals are output from the memory700through the I/O bus704. The I/O bus704is connected to an I/O control unit706that routes the signals between the I/O bus704and an internal data bus708, an internal address bus710, and an internal command bus712. The memory700also includes a control logic unit714that receives a number of control signals either externally or through the command bus712to control the operation of the memory700.

The address bus710applies block-row address signals to a row decoder716and column address signals to a column decoder718. The row decoder716and column decoder718may be used to select blocks of memory or memory cells for memory operations, for example, read, program, and erase operations. The column decoder718enables write data signals to be applied to columns of memory corresponding to the column address signals and allow read data signals to be coupled from columns corresponding to the column address signals.

In response to the memory commands decoded by the control logic unit714, the memory cells in the array702are read, programmed, or erased. Read, program, and erase circuits720coupled to the memory array702receive control signals from the control logic unit714and include voltage generators for generating various pumped voltages for read, program and erase operations.

After the row address signals have been applied to the address bus710, the I/O control unit706routes write data signals to a cache register722. The write data signals are stored in the cache register722in successive sets each having a size corresponding to the width of the I/O bus704. The cache register722sequentially stores the sets of write data signals for an entire row or page of memory cells in the array702. All of the stored write data signals are then used to program a row or page of memory cells in the array702selected by the block-row address coupled through the address bus710. In a similar manner, during a read operation, data signals from a row or block of memory cells selected by the block-row address coupled through the address bus710are stored in a data register724. Sets of data signals corresponding in size to the width of the I/O bus704are then sequentially transferred through the I/O control unit706from the data register724to the I/O bus704.

Those of ordinary skill would further appreciate that the various illustrative logical blocks, configurations, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software executed by a processor, or combinations of both. Various illustrative components, blocks, configurations, modules, circuits, and steps have been described above generally in terms of their functionality. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.