Trench gate type transistor

The invention provides a trench gate type transistor in which the gate capacitance is reduced, the crystal defect is prevented and the gate breakdown voltage is enhanced. Trenches are formed in an N− type semiconductor layer. A uniformly thick silicon oxide film is formed on the bottom of each of the trenches and near the bottom, being round at corner portions. A silicon oxide film is formed on the upper portion of the sidewall of each of the trenches, which is thinner than the silicon oxide film and round at corner portions. Gate electrodes are formed from inside the trenches onto the outside thereof. The thick silicon oxide film reduces the gate capacitance, and the thin silicon oxide film on the upper portion provides good transistor characteristics. Furthermore, with the round corner portions, the crystal defect does not easily occur, and the gate electric field is dispersed to enhance the gate breakdown voltage.

REFERENCE TO RELATED APPLICATIONS

This application is a national stage application under 35 USC 371 of International Application No. PCT/JP2008/068116, filed Sep. 26, 2008, which claims priority from Japanese Patent Application No. 2007-255091, filed Sep. 28, 2007, the contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a trench gate type transistor and a method of manufacturing the same.

2. Description of the Related Art

A DMOS transistor is a double-diffused MOS field effect transistor and used as a power semiconductor device for a power supply circuit, a driver circuit or the like. A trench gate type transistor is known as a type of DMOS transistor.

This trench gate type transistor is configured by forming a gate insulation film115in a trench114formed in a semiconductor layer112and forming a gate electrode116covering the gate insulation film115in the trench114as shown inFIG. 27. A body layer and a source layer (not shown) are further formed in the front surface of the semiconductor layer112on the sidewall of the trench114by double-diffusion in the vertical direction.

A trench gate type transistor is described in Japanese Patent Application Publication Nos. 2005-322949, 2003-188379 and 2005-510087.

However, the conventional trench gate type transistor has problems that the gate capacitance (of the gate electrode116, the gate insulation film115and the semiconductor layer112) is large, the semiconductor layer112near the trench114easily has crystal defects, and the gate breakdown voltage is low due to gate electric field concentration.

SUMMARY OF THE INVENTION

The main features of the invention are as follows.

The invention provides a trench gate type transistor including a semiconductor layer, a gate insulation film formed in a trench formed in the semiconductor layer and extending onto the semiconductor layer on an outside of the trench, a gate electrode formed on the gate insulation film, and a body layer formed in the semiconductor layer near its front surface and contacting the gate insulation film on a sidewall of the trench, the gate insulation film having a first thickness on an upper portion of the sidewall of the trench, and a second thickness on a lower portion of the sidewall of the trench and on a bottom surface of the trench, the second thickness being larger than the first thickness, and the trench being round from the bottom surface to the sidewall.

With this structure, since the gate insulation film is thick on the lower portion of the sidewall of the trench and on the bottom surface of the trench, the gate capacitance is reduced accordingly. Furthermore, since the gate insulation film is thin on the upper portion of the sidewall of the trench, good transistor characteristics (low threshold, low on-resistance) are obtained. Furthermore, since the trench is round from the bottom surface to the sidewall, the semiconductor layer near the trench does not easily have crystal defects, and the gate electric field is dispersed to enhance the gate breakdown voltage.

The invention also provides a method of manufacturing a trench gate type transistor, including: forming a trench in a semiconductor layer; forming an oxide film on a front surface of the semiconductor layer including in the trench by thermally oxidizing the semiconductor layer formed with the trench; forming a photoresist reinforcement film on the oxide film; forming a photoresist layer on the photoresist reinforcement film including in the trench; leaving the photoresist layer and the photoresist reinforcement film only in the trench by etching back the photoresist layer and the photoresist reinforcement film to expose the oxide film; removing the oxide film on the front surface of the semiconductor layer and on an upper portion of a sidewall of the trench by etching the exposed oxide film using the photoresist layer and the photoresist reinforcement film as a mask; removing the photoresist layer and the photoresist reinforcement film; forming a gate oxide film having a first thickness on the upper portion of the sidewall of the trench and a second thickness on a lower portion of the sidewall of the trench and on a bottom surface of the trench by thermal oxidation, the second thickness being larger than the first thickness; forming a gate electrode on the gate oxide film; and forming a body layer on the sidewall of the trench so as to contact the gate oxide film.

The invention also provides a method of manufacturing a trench gate type transistor, including: forming a trench in a semiconductor layer; forming an oxide film on a front surface of the semiconductor layer including in the trench by thermally oxidizing the semiconductor layer formed with the trench; forming a photoresist reinforcement film on the oxide film; forming a BARC on the photoresist reinforcement film including in the trench; forming a photoresist layer on the BARC including in the trench; exposing the BARC on an active region by forming an opening in the photoresist layer on the active region by exposure and development; leaving the BARC and the photoresist reinforcement film in the trench by etching back the BARC and the photoresist reinforcement film using the photoresist layer as a mask to expose the oxide film; removing the oxide film on the front surface of the semiconductor layer and on an upper portion of a sidewall of the trench by etching the exposed oxide film using the photoresist layer and the photoresist reinforcement film as a mask; removing the photoresist layer, the BARC and the photoresist reinforcement film; forming a gate oxide film having a first thickness on the upper portion of the sidewall of the trench and a second thickness on a lower portion of the sidewall of the trench and on a bottom surface of the trench by thermal oxidation, the second thickness being larger than the first thickness; forming a gate electrode on the gate oxide film; and forming a body layer on the sidewall of the trench so as to contact the gate oxide film.

The trench gate type transistor and the method of manufacturing the same of the invention reduce the gate capacitance. Furthermore, the crystal defects are prevented and the gate breakdown voltage is enhanced.

DETAILED DESCRIPTION OF THE INVENTION

First Embodiment

A first embodiment of the invention will be described referring to figures.FIG. 1is a plan view for explaining a trench gate type transistor and a method of manufacturing the same of the embodiment of the invention.FIGS. 2(A) to 14(A)are cross-sectional views ofFIG. 1along line A-A, andFIGS. 2(B) to 14(B)are cross-sectional views ofFIG. 1along line B-B. In the following description, the trench gate type transistor is referred to as a transistor simply. The conductive type of this transistor is not limited, but the following description is given for a case of an N channel type transistor.

First, the schematic plan structure of the transistor of the embodiment will be described referring toFIG. 1. Here, only main elements will be described. In this transistor, an N+ type semiconductor layer11and an N− type semiconductor layer12are formed on a P type semiconductor substrate10, and a plurality of trenches14each having short sides and long sides is formed in the N− type semiconductor layer12on the front surface side through a region where a body layer19is formed. A gate electrode18is formed in each of the trenches14with a gate insulation film (not shown) being interposed therebetween. The gate electrodes18are connected to each other in one ends of the trenches14, extending onto the outside of the trenches14. The gate electrodes18extending onto the outside of the trenches14are connected to wires (not shown) through contact holes H1provided in an interlayer insulation film (not shown).

It is noted that other high breakdown voltage MOS transistor (not shown) may be formed on the same N− type semiconductor layer12near this transistor.

Hereafter, the trench gate type transistor and the method of manufacturing the same of the embodiment will be described referring to figures.

As shown inFIG. 2, the N+ type semiconductor layer11and the N− type semiconductor layer12are formed by doping N type impurities in the front surface of the P type semiconductor substrate10and then epitaxially growing the semiconductor layers. Hereafter, the description is given supposing that the semiconductor substrate10is of a silicon single crystal substrate and the N+ type semiconductor layer11and the N− type semiconductor layer12are of a silicon single crystal semiconductor layer, but the invention is not limited to this. Then, a silicon oxide film13is formed on the N− type semiconductor layer12by a CVD method or a thermal oxidation treatment. Furthermore, a photoresist layer R1having an opening M1is formed on the silicon oxide film13. The opening M1has a plurality of rectangles with short sides and long sides.

Then, as shown inFIG. 3, the silicon oxide film13is etched using the photoresist layer R1as a mask to form an opening13M in the silicon oxide film13. After the photoresist layer R1is removed, the N− type semiconductor layer12is etched using the silicon oxide film13as a hard mask to form the plurality of trenches14with short sides and long sides corresponding to the opening13M. This etching is dry-etching using etching gas containing SF6, for example. Therefore, the corner portions12A and12B of the N− type semiconductor layer12at the bottoms of the trenches14are formed to be round (i.e. curved). Preferably, the depth of the trench14is about 1.5 μm, the long side is about 50 μm, and the short side is about 0.5 μm. The silicon oxide film13is then removed.

Then, as shown inFIG. 4, a thermal oxidation treatment is performed to the N− type semiconductor layer12including in the trenches14to form a silicon oxide film15A. Preferably, the thickness of the silicon oxide film15A at this time is about 100 nm. The silicon oxide film15A is formed to be round from the bottoms to the sidewalls of the trenches14, reflecting the round corner portions12A and12B of the N− type semiconductor layer12at the bottoms of the trenches14. The silicon oxide film15A is also formed to be round (i.e. curved) at a portion extending from inside the trenches14onto the N− type semiconductor layer12on the outside of the trenches14, i.e., at the upper end portions of the sidewalls of the trenches14by this thermal oxidation treatment. As for the interface of the silicon oxide film15A and the N− type semiconductor layer12, the corner portions12C and12D of the N− type semiconductor layer12at the upper ends of the sidewalls of the trenches14are round (i.e. curved).

When other high breakdown voltage MOS transistor is formed on the same N− type semiconductor layer12, the silicon oxide film15A is formed simultaneously with the gate oxide film of this transistor. The thickness of the silicon oxide film15A depends on the breakdown voltage characteristics of the MOS transistor.

Then, as shown inFIG. 5, a photoresist reinforcement film16is formed on the silicon oxide film15A including in the trenches14by a CVD method or the like. The photoresist reinforcement film16prevents the silicon oxide film15A to be left from being removed by etching solution entering the interface of a photoresist layer R2and the silicon oxide film15A in a wet etching process described below. The photoresist reinforcement film16is preferably made of a silicon nitride film and the thickness is about 60 nm.

Then, as shown inFIG. 6, a photoresist layer R2is formed on the photoresist reinforcement film16including in the trenches14. Then, as shown inFIG. 7, the photoresist layer R2and the photoresist reinforcement film16are partially etched back and removed. By this process, the photoresist layer R2and the photoresist reinforcement film16remain only in the trenches14, and the silicon oxide film15A is exposed from the end portions of the trenches14onto the outside thereof.

Then, as shown inFIG. 8, the exposed silicon oxide film15A is etched using the photoresist layer R2and the photoresist reinforcement film16as a mask. This etching is preferably wet etching using hydrofluoric acid type etching solution or the like. By this process, the silicon oxide film15A is removed on the front surface of the N− type semiconductor layer12and from the upper portions of the sidewalls of the trenches14(i.e. in the region near the opening portions of the trenches14) onto the outside of the trenches14, thereby exposing the N− type semiconductor layer12there. The region of the silicon oxide film15A removed in the trenches14is about 600 nm to 1 μm from the opening portions of the trenches14toward the bottoms. Then, as shown inFIG. 9, the photoresist layer R2and the photoresist reinforcement film16are removed.

Then, as shown inFIG. 10, a thermal oxidation treatment is performed to the N− type semiconductor layer12to form a silicon oxide film15B from the upper portions of the sidewalls of the trenches14onto the outside of the trenches14, which is thinner than the silicon oxide film15A on the bottoms of the trenches14. The silicon oxide film15B on the upper end portions of the sidewalls of the trenches14is formed to be round (i.e. curved), reflecting the round corner portions12C and12D of the N− type semiconductor layer12. The silicon oxide film15A and the silicon oxide film15B function as a gate insulation film.

The thickness of the thin silicon oxide film15B on the upper portions of the sidewalls of the trenches14(an example of a first thickness of the invention) is about 7 to 20 nm, and preferably about 15 nm. The thickness of the silicon oxide film15A on the bottoms of the trenches14(an example of a second thickness of the invention) is about 50 to 200 nm, and preferably about 100 nm.

Then, as shown inFIG. 11, a polysilicon layer18P is formed covering the silicon oxide film15A and the silicon oxide film15B, and impurities are doped therein. The impurities are preferably of an N type impurity.

Next, as shown inFIG. 12, a photoresist layer R3is formed on the polysilicon layer18P in a region partially overlapping the end portions of the trenches14. Then, the polysilicon layer18P is etched using the photoresist layer R3as a mask to form the gate electrodes18extending from inside the trenches14onto the end portions of the trenches on the outside. The leading portions18S of the gate electrodes18extending from inside the trenches14onto the outside contact the thin silicon oxide film15B at the round corner portions12C. Furthermore, the gate electrodes18are connected to each other on the silicon oxide film15B on the outside of the trenches14. This etching is plasma etching, for example. The photoresist layer R3is then removed.

Then, as shown inFIG. 13, P type impurities are ion-implanted in the N− type semiconductor layer12around each of the trenches14in the vertical direction to form the P type body layer19. Furthermore, N type impurities are ion-implanted in the front surface of the body layer19along the long sides of the trenches14to form a source layer21. It is preferable to perform a heat treatment for the activation and the modulation of the impurity distributions of the body layer19and the source layer21.

Then, as shown inFIG. 14, an interlayer insulation film24is formed covering the silicon oxide film15B and the gate electrodes18. Wiring layers25are formed on the interlayer insulation film24, being connected to the gate electrodes18through the contact holes H1provided in the interlayer insulation film24. Furthermore, source electrodes23are formed on the interlayer insulation film24, being connected to the source layer21through contact holes H2provided in the silicon oxide film15B and the interlayer insulation film24.

In the transistor thus completed, when a potential of the threshold or more is applied from the wiring layers25to the gate electrodes18, the surface of the body layer19on the sidewalls of the trenches14is inverted into the N type to form channels. Therefore, current flows between the source electrodes23and the N− type semiconductor layer12and the N+ type semiconductor layer11as a drain D.

Since the silicon oxide film15A is formed thick on the bottoms of the trenches14and the sidewalls near the bottoms, the gate capacitance (of the gate electrode18, the silicon oxide film15A and the N− type semiconductor layer12) is reduced.

Furthermore, since the corner portions12A and12B of the N− type semiconductor layer12are formed to be round, on the bottoms of the trenches14and the sidewalls near the bottoms, the N− type semiconductor layer12does not easily have crystal defects, and the thickness of the silicon oxide film15A becomes constant and the gate electric field is dispersed so that the reduction of the gate breakdown voltage is prevented.

On the other hand, since the thin silicon oxide film15B is formed as the gate insulation film on the active region (the region formed with the body layer19) of the transistor on the upper portions of the sidewalls of the trenches14, good transistor characteristics (low threshold, low on-resistance) are obtained.

Furthermore, since the silicon oxide film15B is formed to be round on the upper ends of the sidewalls of the trenches14near the leading portions18S of the gate electrodes18, reflecting the corner portions12C and12D of the N− type semiconductor layer12, the gate leakage current between the gate electrodes18and the N− type semiconductor layer12is reduced.

As a modification of the embodiment, as shown inFIG. 15, a drain leading portion26and a drain electrode27may be formed. In this case, before the interlayer insulation film24is formed, an opening12H is formed in the N− type semiconductor layer12, an insulation film28is formed in the opening12H, and the drain leading portion26is embedded therein. Then, the interlayer insulation film24is formed, a penetration hole H3is formed penetrating the interlayer insulation film24, and the drain electrode27is formed in the penetration hole H3, being connected to the drain leading portion26.

Furthermore, as other modification of the embodiment, the gate electrodes18may be formed separately and isolatedly in the ends of the trenches14respectively as shown in the plan view ofFIG. 16instead of being connected to each other in the ends of the trenches14as shown inFIG. 1. The other structure is the same as that ofFIG. 1. With this structure, when the plasma etching is performed to etch the polysilicon layer18P, since the area of the gate electrodes18made of the polysilicon layer18P is reduced, plasma damage to the gate electrodes18is minimized. Therefore, the reliability of the transistor is enhanced.

Second Embodiment

A second embodiment of the invention will be described referring to figures. The schematic plan structure of this transistor is the same as that ofFIG. 1.

Hereafter, a trench gate type transistor and a method of manufacturing the same of the embodiment will be described referring to figures.FIGS. 17(A) to 26(A)are cross-sectional views ofFIG. 1along line A-A, andFIGS. 17(B) to 26(B)are cross-sectional views ofFIG. 1along line B-B. InFIGS. 17 to 26, the same numerals are given to the same elements as those ofFIGS. 2 to 14.

First, in the similar manner to the processes shown inFIGS. 2 to 5in the first embodiment, an N+ type semiconductor layer11and an N− type semiconductor layer12are formed on a semiconductor substrate10, and trenches14are formed in the N− type semiconductor layer12. A silicon oxide film35A which corresponds to the silicon oxide film15A, and a photoresist reinforcement film36which corresponds to the photoresist reinforcement film16are formed on the N− type semiconductor layer12including in the trenches14.

When other high breakdown voltage MOS transistor is formed on the same N− type semiconductor layer12, the silicon oxide film35A is formed simultaneously with the gate oxide film of this transistor. The thickness of the silicon oxide film35A depends on the breakdown voltage characteristics of the MOS transistor.

Then, as shown inFIG. 17, a BARC (Bottom Anti-Reflection Coating)37which is an anti-reflection layer is formed on the photoresist reinforcement film36including in the trenches14. A photoresist layer R4is further formed on the BARC37including in the trenches14. The BARC37sets after it is formed as fluid and is not removed in a photolithography process of the photoresist layer R4in its properties. Due to these properties, the BARC37is formed to have a larger thickness on the bottoms of the trenches14than the thickness from the upper portions of the sidewalls onto the outside of the trenches14. Other material may be formed instead of the BARC37as long as it has such properties. For example, when the photoresist layer R4is of a positive type photoresist layer, a negative type photoresist layer may be formed instead of the BARC37.

Then, as shown inFIG. 18, an opening M4is provided in the photoresist layer R4by a photolithography process, i.e., exposure and development. The opening M4is located on a region of the N− type semiconductor layer12for the active region of the transistor. The active region of the transistor is a region including a region for forming a body layer19. Hereafter, the active region of the transistor is referred to as an active region simply.

Then, as shown inFIG. 19, the photoresist reinforcement film36and the BARC37are etched and removed using the photoresist layer R4as a mask. In this etching, the photoresist reinforcement film36and the BARC37are removed on the active region on the outside of the trenches14to expose the silicon oxide film35A. On the other hand, the photoresist reinforcement film36and the BARC37remain in the trenches14. This is because that since the thickness of the BARC37differs between inside the trenches14and on the outside of the trenches14, the BARC37on the outside of the trenches14is removed by etching before the BARC37on the bottoms of the trenches14, which is thicker than the BARC37on the outside.

In a case of the photoresist layer R4of a positive type, when the opening M4is provided by the photolithography process shown inFIG. 18, the BARC37as an anti-reflection layer prevents diffuse reflection of light on the bottoms of the trenches14, so that the photoresist layer R4is easily left on the BARC37in the desired region. Then, the etching of the BARC37in the trenches14is surely delayed compared with the etching of the BARC37on the outside of the trenches14.

Then, as shown inFIG. 20, the silicon oxide film35A is etched using the photoresist layer R4, and the photoresist reinforcement film36and the BARC37inside the trenches14as a mask. By this process, the silicon oxide film35A on the front surface of the N− type semiconductor layer12on the outside of the trenches14and on the upper portions of the sidewalls of the trenches14(i.e. the region near the opening portions of the trenches14) is removed. The region of the silicon oxide film35A removed in the trenches14is about 600 nm to 1 μm from the opening portions of the trenches14toward the bottoms. The photoresist layer R4, the photoresist reinforcement film36and the BARC37are then removed as shown inFIG. 21.

Then, as shown inFIG. 22, a silicon oxide film35B is formed on the active region from the upper portions of the sidewalls of the trenches14onto the outside of the trenches14along the long sides of the trenches14by a thermal oxidation treatment, which is thinner than the silicon oxide film35A on the bottoms of the trenches14. The silicon oxide film35A on the upper ends of the sidewalls of the trenches14along the short sides increases in thickness, and is formed to be round (i.e. curved), reflecting the round corner portions12C of the N− type semiconductor layer12. The silicon oxide film35A and the silicon oxide film35B function as a gate insulation film.

The thickness of the thin silicon oxide film35B (an example of the first thickness of the invention) is about 7 to 20 nm, and preferably about 15 nm. Furthermore, the thickness of the thick silicon oxide film35A (an example of the second thickness of the invention) is about 50 to 200 nm, and preferably about 100 nm.

Then, as shown inFIG. 23, a polysilicon layer38P is formed covering the silicon oxide film35A and the silicon oxide film35B, and impurities are doped therein. The impurities are preferably of an N type impurity.

Then, as shown inFIG. 24, a photoresist layer R5is formed on the polysilicon layer38P in a region partially overlapping the end portions of the trenches14. Then, the polysilicon layer38P is etched using the photoresist layer R5as a mask to form gate electrodes38extending from inside the trenches14onto the end portions of the trenches14on the outside. The leading portions38S of the gate electrodes38extending from inside the trenches14onto the outside thereof contact the thick silicon oxide film35A at the round corner portions12C. The gate electrodes38are connected to each other on the outside of the trenches14. This etching is plasma etching, for example. The photoresist layer R5is then removed.

Then, as shown inFIG. 25, in the similar manner to the first embodiment, the body layer19is formed in the N− type semiconductor layer12. Furthermore, a source layer21is formed in the front surface of the body layer19. It is preferable to perform a heat treatment for the activation and the modulation of the impurity distributions of the body layer19and the source layer21.

Then, as shown inFIG. 26, an interlayer insulation film24is formed covering the silicon oxide films35A and35B and the gate electrodes38. Wiring layers25are formed on the interlayer insulation film24, being connected to the gate electrodes38through contact holes H1provided in the interlayer insulation film24. Furthermore, source electrodes23are formed on the interlayer insulation film24, being connected to the source layer21through contact holes H2provided in the silicon oxide film35B and the interlayer insulation film24.

In the transistor thus completed, when a potential of the threshold or more is applied from the wiring layers25to the gate electrodes38, the surface of the body layer19on the sidewalls of the trenches14is inverted into the N type to form channels. Therefore, current flows between the source electrodes23and the N− type semiconductor layer12and the N+ type semiconductor layer11as a drain D.

Since the silicon oxide film35A is formed thick on the bottoms of the trenches14and the sidewalls near the bottoms, the gate capacitance (of the gate electrode38, the silicon oxide film35A and the N− type semiconductor layer12) is reduced.

Furthermore, since the corner portions12A and12B of the N− type semiconductor layer12are formed to be round, on the bottoms of the trenches14and the sidewalls near the bottoms, the N− type semiconductor layer12does not easily have crystal defects, and the thickness of the silicon oxide film35A becomes constant and the gate electric field is dispersed so that the reduction of the gate breakdown voltage is prevented.

On the other hand, since the thin silicon oxide film35B is formed as the gate insulation film on the active region (the region formed with the body layer19) of the transistor on the upper portions of the sidewalls of the trenches14, good transistor characteristics (low threshold, low on-resistance) are obtained.

Furthermore, since the silicon oxide film35A functions as the thick gate insulation film on the upper ends of the sidewalls of the trenches14near the leading portions38S of the gate electrodes38, a long distance is provided between the leading portion38S of the gate electrode38and the corner portion12C of the N− type semiconductor layer12. Furthermore, the silicon oxide film35A in this portion is formed to be round reflecting the corner portions12C of the N− type semiconductor layer12. Therefore, the gate leakage current between the gate electrode38and the corner portion12C of the N− type semiconductor layer12is reduced.

As a modification of the embodiment, a drain leading portion26and a drain electrode27may be formed as shown inFIG. 15of the first embodiment. In this case, before the interlayer insulation film24is formed, an opening12H is formed in the N− type semiconductor layer12, an insulation film28is formed in the opening12H, and the drain leading portion26is embedded therein. Then, the interlayer insulation film24is formed, a penetration hole H3is formed penetrating the interlayer insulation film24, and the drain electrode27is formed in the penetration hole H3, being connected to the drain leading portion26.

Furthermore, as other modification of the embodiment, the gate electrodes38may be formed separately and isolatedly for the trenches14respectively in the similar manner to the first embodiment shown inFIG. 16. In this case, too, the same effect as that of the first embodiment is obtained.

The invention is not limited to the above embodiments and modifications are possible within the scope of the invention. For example, although the description is given for an N-channel type transistor in the embodiments described above, the invention is also applicable to a P-channel type transistor by changing the conductive types of the source layer21, the body layer19and so on to the opposite conductive types.

Furthermore, the invention is also applicable to a device having an embedded gate electrode such as a trench gate type IGBT.