Device for synchronizing a power drive signal of a monitor and a method therefor

A device for synchronizing a power drive signal of a monitor, and a method therefor. The device comprises a central processing unit to receive a horizontal synchronization signal outputted from a video card and to judge whether a frequency of the horizontal synchronization signal is larger than a frequency preset in a memory; a frequency-division circuit to receive the horizontal synchronization signal from the video card and divide the frequency of the horizontal synchronization signal; and a frequency division signal selection circuit to output the frequency-divided horizontal synchronization signal, outputted from the frequency division circuit, to a high voltage drive circuit if the central processing unit judges that the frequency of the horizontal synchronization signal is larger than the preset frequency and to output the horizontal synchronization signal with the frequency thereof unchanged to the high voltage drive circuit if the central processing unit judges that the frequency of the horizontal synchronization signal is not larger than the frequency preset in the memory.

CROSS-REFERENCE TO RELATED APPLICATIONS
 This application claims the benefit of Korean Patent Application Nos.
 98-25754 filed Jun. 30, 1998, and 98-31319 filed Jul. 31, 1998 the
 disclosures of which are incorporated herein by reference.
 BACKGROUND OF THE INVENTION
 1. Field of the Invention
 The present invention relates to a device for synchronizing a power drive
 signal of a monitor and a method therefor, and more particularly, to a
 device for synchronizing a power drive signal of a monitor by selectively
 dividing a frequency of a horizontal synchronization signal and a method
 therefor.
 2. Description of the of Related Art
 A frequency division means that a signal with a divided frequency of 1/a
 (where "a" is positive number) of the original value of the frequency
 thereof is outputted from a device when the signal with the original value
 of the frequency is inputted into the device.
 For example, when a signal of 50 KHz is inputted into a device and a
 frequency division of 1/2 is carried out, a signal of 25 KHz is outputted
 from the device.
 FIG. 1 illustrates a control device of a conventional device for
 controlling a power drive synchronization signal of a monitor.
 A conventional device for controlling power drive synchronization signals
 of a monitor comprises a micro-computer 72 filtering horizontal / vertical
 signals (H/V_SYNC) to discern a polarity of signal and calculating a
 frequency exactly to output a horizontal frequency signal (Hout) and a
 vertical frequency signal (Vout), a horizontal deflection circuit 74
 performing a horizontal deflection function according to the horizontal
 frequency signal (Hout) outputted from the micro-computer 72, a vertical
 deflection circuit 76 performing a vertical deflection function according
 to the vertical frequency signal (Vout) outputted from the micro-computer
 72, and a high voltage drive circuit 78 receiving the horizontal frequency
 signal from the horizontal deflection 74 to output a driving signal
 driving a high voltage output circuit (not illustrated).
 In a monitor provided with the device for controlling the power drive
 synchronization signal, a power voltage provided to an inner circuit of
 the monitor is stabilized and a driving signal outputted from a high
 voltage circuit part to a flyback transformer is synchronized with a
 horizontal synchronization signal applied from a video card to a
 horizontal circuit part.
 However, in a conventional device for controlling power drive
 synchronization signal as described above, the flyback transformer should
 be operated by a period of high frequency when the horizontal
 synchronization signal has a high frequency. Accordingly, a lot of power
 loss occurs due to the flyback transformer. In addition, as electronic
 parts for high current are required, high power voltage should be
 connected to the flyback transformer to support the movement of said
 flyback transformer, cost for such devices are increased.
 SUMMARY OF THE INVENTION
 Accordingly, in order to overcome such drawbacks in the conventional art,
 it is therefore an object of the present invention to provide a device for
 synchronizing a power drive signal of a monitor by dividing a frequency of
 a horizontal synchronization signal so as to reduce a power loss of such a
 product and a cost of production and simplify a method therefor.
 Additional objects and advantages of the invention will be set forth in
 part in the description which follows and, in part, will be obvious from
 the description, or may be learned by practice of the invention.
 To achieve the above and other objects, in accordance with the present
 invention, there is provided a device for synchronizing a power drive
 signal of a monitor, the device comprising a central processing unit to
 receive a horizontal synchronization signal outputted from a video card
 and judge whether a frequency of the horizontal synchronization signal is
 larger than a frequency preset in a memory; a frequency-division circuit
 to receive the horizontal synchronization signal from the video card and
 divide the frequency of the horizontal synchronization signal; a high
 voltage driving circuit to generate the power drive signal; and a
 frequency division signal selection circuit to output the
 frequency-divided horizontal signal synchronization from the frequency
 division circuit to the high voltage driving circuit in response to the
 central processing unit judging that the frequency of the horizontal
 synchronization signal is larger than the preset frequency and outputting
 the horizontal synchronization signal with the frequency thereof unchanged
 to the high voltage drive circuit in response to the central processing
 unit judging that the frequency of the horizontal synchronization signal
 is not larger than the frequency preset in the memory.
 To further achieve the above and other objects of the present invention,
 there is provided a method of controlling a device for synchronizing a
 power drive signal of a monitor, the method comprising receiving a
 horizontal synchronization signal from a video card and determining a
 frequency of the horizontal synchronization signal; judging whether the
 frequency of the horizontal synchronization signal is larger than a
 frequency preset in a memory; dividing the frequency of the horizontal
 synchronization signal and driving a high voltage driving circuit by the
 frequency-divided horizontal synchronization signal in response to the
 judgement that the frequency of the horizontal synchronization signal is
 larger than the frequency preset in the memory in the judging step.

DESCRIPTION OF THE PREFERRED EMBODIMENT
 The embodiment of the present invention will be apparent from the following
 description in conjunction with the accompanying drawings.
 FIG. 2 is a block view of a control circuit of a monitor provided with a
 device for controlling a power drive synchronization signal according to
 an embodiment of the present invention.
 A micro-computer 2 controlling a device for controlling a power drive
 synchronization signal of a monitor according to the embodiment of the
 present invention comprises a memory 26 memorizing a setting frequency
 about a horizontal synchronization signal, a CPU (central processing unit)
 4 receiving the horizontal synchronization signal outputted from a video
 card 24 to discern whether a frequency of the horizontal synchronization
 signal is larger than the setting frequency preset in the memory 26, a
 synchronization signal processing circuit 6 receiving the horizontal
 synchronization signal and a vertical synchronization signal from the
 video card 24 to detect the horizontal synchronization signal and the
 vertical synchronization signal, respectively, and to discern a
 synchronous polarity of the horizontal synchronization signal and the
 vertical synchronization signal, a frequency division circuit 28 receiving
 the horizontal synchronization signal from the synchronization signal
 processing circuit 6 and dividing a frequency of the horizontal
 synchronization signal to output a horizontal synchronization signal
 having a divided frequency, and a frequency division signal selection
 circuit 30 selectively selecting the frequency-divided horizontal
 synchronization signal from the frequency division circuit 28.
 The frequency division signal selection circuit 30 is connected to the
 synchronization signal processing circuit 6 and the central processing
 unit 4, to output the frequency-divided horizontal synchronization signal,
 outputted from the frequency division circuit 28, to a high voltage drive
 circuit 16 when the central processing unit 4 judges that the frequency of
 the horizontal synchronization signal is larger than the preset setting
 frequency. The frequency division signal selection circuit 30 outputs the
 horizontal synchronization signal to the high voltage drive circuit 16 in
 such state that the frequency of the horizontal synchronization signal
 outputted from the video card 24 remains as it is when the central
 processing unit 4 judges that the frequency of the horizontal
 synchronization signal is not larger than the setting frequency preset in
 the memory 26.
 A horizontal circuit part 11 applying a horizontal voltage to a cathode ray
 tube 10 includes a horizontal drive circuit 8 receiving the horizontal
 synchronization signal from the synchronization signal processing circuit
 6, to output a first driving signal, and a horizontal output circuit 12
 outputting the horizontal voltage to the cathode ray tube 10 in response
 to receiving the first driving signal from the horizontal drive circuit 8,
 thereby deflecting an electron beam from the cathode ray tube 10 in a
 horizontal direction.
 A high voltage circuit part 14 receives the horizontal synchronization
 signal or the frequency-divided horizontal synchronization signal from the
 frequency-division signal selection circuit 30 to output a high voltage
 pulse synchronized with the horizontal synchronization signal. The high
 voltage circuit part 14 includes a high voltage drive circuit 16 receiving
 the horizontal synchronization signal or the frequency-divided horizontal
 synchronization signal from the frequency-division signal selection
 circuit 30 to output a second driving signal synchronized with the
 horizontal synchronization signal, a high voltage output circuit 20
 receiving a direct current voltage outputted from a direct current voltage
 output circuit (not shown) to output a high alternating current voltage by
 being switched according to the second driving signal outputted from the
 high voltage driving circuit 16, and a flyback transformer 22 receiving
 the high alternating current voltage outputted from the high voltage
 output circuit 20 to output a high voltage pulse to the cathode ray tube
 10.
 The frequency-division signal selection circuit 30 is a multiplexer
 receiving the horizontal synchronization signal with a normal frequency
 from the video card 24 and receiving the frequency-divided horizontal
 synchronization signal from the frequency-division circuit 28 to output
 one signal, formed of the horizontal synchronization signal with the
 normal frequency and the frequency-divided horizontal synchronization
 signal according to a selection signal outputted from the central
 processing unit 4, to the high voltage drive circuit 16.
 As shown in FIG. 3, the synchronization signal processing circuit 6
 includes a vertical synchronization signal detecting circuit 32 to receive
 the vertical synchronization signal outputted from the video card 24, a
 polarity discerning circuit of the vertical synchronization signal 34
 judging whether a polarity of the vertical synchronization signal
 outputted from the vertical synchronization signal detecting circuit 32 is
 active high or low, a vertical synchronization signal dividing circuit 36
 to divide the vertical synchronization signal and the horizontal
 synchronization signal from a complex signal when the complex signal of
 the vertical synchronization signal and the horizontal synchronization
 signal is outputted from the video card 24, a horizontal synchronization
 signal detecting circuit 38 to detect the horizontal synchronization
 signal outputted from the vertical synchronization signal dividing circuit
 36, and a polarity discerning circuit of the horizontal synchronization
 signal 40 judging whether a polarity of the horizontal synchronization
 signal outputted from the horizontal synchronization signal detecting
 circuit 38 is active high or low.
 As shown in FIG. 4, the frequency-division circuit 28 comprises a
 transistor Q2 being switched according to the horizontal synchronization
 signal outputted from the polarity discerning circuit of the horizontal
 synchronization signal 40 within the synchronization signal processing
 circuit 6 and a D-flip-flop 42 receiving the horizontal synchronization
 signal outputted from the transistor Q2 as a clock signal to output 1/2
 the frequency of the horizontal synchronization signal to the
 frequency-division signal selection circuit 30. A resistor R5 has one end
 which receives the horizontal synchronization signal from the polarity
 discerning circuit of the horizontal synchronization signal 40 and another
 end connected to a base of the transistor Q2. A resistor R6 has one end
 connected to the base of the transistor Q2 and the other end connected to
 ground. A resistor R3 has one end connected to a collector of the
 transistor Q2 and the other end connected to a 5V source. The emitter of
 the transistor Q2 is connected to ground.
 The method for controlling the device for controlling the power drive
 synchronization signal of a monitor according to the embodiment of the
 present invention will be apparent from the following description in
 conjunction with the device for controlling the power drive
 synchronization signal of the monitor according to the embodiment of the
 present invention.
 FIG. 5 is a flow chart of a method of controlling a device for controlling
 a power drive synchronization signal, wherein "S" stands for "an
 operation."
 First, a vertical synchronization signal is outputted from the video card
 24 to the central processing unit 4 and the vertical synchronization
 signal detecting circuit 32 of the synchronization signal processing
 circuit 6.
 At the same time, a horizontal synchronization signal is outputted from the
 video card 24 to the central processing unit 4 and the vertical
 synchronization signal dividing circuit 36.
 Next, the horizontal synchronization signal is outputted from the vertical
 synchronization signal dividing circuit 36 to the horizontal
 synchronization signal detecting circuit 38.
 Then, the horizontal synchronization signal is outputted from the
 horizontal synchronization signal detecting circuit 38 to the polarity
 discerning circuit of the horizontal synchronization signal 40.
 Next, the horizontal synchronization signal is outputted from the polarity
 discerning circuit of the horizontal synchronization signal 40 to the
 frequency-division circuit 28 at the same time that the horizontal
 synchronization signal is outputted from the polarity discerning circuit
 of the horizontal synchronization signal 40 to the horizontal drive
 circuit 8.
 Then, the horizontal synchronization signal is frequency-divided in the
 frequency-division circuit 28. The frequency-divided horizontal
 synchronization signal with 1/2 the frequency of the horizontal
 synchronization signal is outputted from the frequency-division circuit
 28. For example, the horizontal synchronization signal of 30 KHz is
 outputted from the frequency-division circuit 28 to the frequency-division
 signal selection circuit 30 when the horizontal synchronization signal of
 60 Khz is inputted from the polarity discerning circuit of the horizontal
 synchronization signal 40 to the frequency-division circuit 28.
 At the same time, the horizontal synchronization signal is outputted from
 the polarity discerning circuit of the horizontal synchronization signal
 40 to the frequency-division signal selection circuit 30.
 Meanwhile, the central processing unit 4 in operation S10 calculates a
 period of the horizontal synchronization signal inputted from the video
 card 24.
 Next, a reciprocal amount of the period of the horizontal synchronization
 signal is calculated in operation S20 to calculate the frequency of the
 horizontal synchronization signal.
 Then, the central processing unit 4 in operation S30 judges whether the
 frequency of the horizontal synchronization signal is larger than the
 frequency preset in the memory 26. For example, the frequency preset in
 the memory 26 is 50 Khz.
 Here, when it is judged that the frequency of the horizontal
 synchronization signal is larger than the frequency preset in the memory
 26 (in case of yes), the process goes to operation 40 as the frequency of
 the horizontal synchronization signal should be divided to prevent a noise
 on a picture.
 A frequency-division selection signal in operation S40 is outputted from
 the CPU 4 to the frequency-division signal selection circuit 30 to select
 the frequency-divided horizontal synchronization signal outputted from the
 frequency-division circuit 28.
 Then, the frequency-division signal selection circuit 30 selects the
 frequency-divided horizontal synchronization signal from the
 frequency-division circuit 28 instead of the horizontal synchronization
 signal inputted from the polarity discerning circuit of the horizontal
 synchronization signal 40.
 Next, the frequency-divided horizontal synchronization signal from the
 frequency-division signal selection circuit 30 is inputted to the high
 voltage drive circuit 16.
 Then, the high voltage drive circuit 16 is switched in accordance with the
 frequency synchronized with the horizontal synchronization frequency
 inputted from the frequency-division signal selection circuit 30, to
 output the second driving signal.
 Next, the second driving signal is outputted from the high voltage drive
 circuit 16 to the high voltage output circuit 20 and is synchronized with
 the horizontal synchronization frequency.
 Then, the high voltage of alternating current is outputted from the high
 voltage output circuit 20 to the flyback transformer 22.
 Next, a high voltage pulse synchronized with the horizontal synchronization
 signal is outputted from the flyback transformer 22 to the cathode ray
 tube 10.
 In the meantime, the horizontal synchronization signal is outputted from
 the polarity discerning circuit of the horizontal synchronization signal
 40 to the horizontal driving circuit 8 at the same time as the horizontal
 synchronization signal is outputted from the polarity discerning circuit
 of the horizontal synchronization signal 40 to the frequency-division
 circuit 28, to generate the first driving signal.
 Then, the first driving signal is outputted from the horizontal driving
 circuit 8 to the horizontal output circuit 12. Next, the horizontal
 voltage is applied from the horizontal output circuit 12 to the cathode
 ray tube.
 Meanwhile, when the vertical synchronization signal is outputted from the
 video card 24 to the vertical synchronization signal detecting circuit 32,
 the vertical synchronization signal is detected in the vertical
 synchronization signal detecting circuit 32.
 Then, the vertical synchronization signal is outputted from the vertical
 synchronization signal detecting circuit 32 to the polarity discerning
 circuit of the vertical synchronization signal 34.
 Next, the vertical synchronization signal is outputted from the polarity
 discerning circuit of the vertical synchronization signal 34 to a vertical
 drive circuit 44.
 In the meantime, when it is judged that the frequency of the horizontal
 synchronization signal in operation S30 is not larger than the frequency
 preset in the memory 26 (in case of no), the normal horizontal
 synchronization selection signal is outputted from the central processing
 unit 4 to the frequency-division signal selection circuit 30 in operation
 S50.
 Then, the frequency-division signal selection circuit 30 selects the
 horizontal synchronization signal inputted from the polarity discerning
 circuit of the horizontal synchronization signal 40 instead of the
 frequency-divided horizontal synchronization signal inputted from the
 frequency-division circuit 28.
 Then, the horizontal synchronization signal with the normal frequency is
 outputted from the frequency-division signal selection circuit 30 to the
 high voltage driving circuit 16. The high voltage drive circuit 16, the
 high voltage output circuit 20 and the flyback transformer 22 process the
 horizontal synchronization signal with the normal (unchanged) frequency in
 a same fashion as these elements process the frequency-divided horizontal
 synchronization signal output from the frequency-division signal selection
 circuit 30.
 As described above, the output circuit shown in FIG. 2 can output the high
 voltage synchronized with the horizontal synchronization signal having the
 high frequency from the flyback transformer using the frequency-division
 circuit and the frequency-division signal selection circuit 30 constructed
 within the micro-computer. In addition, the high voltage, synchronized
 with the horizontal synchronization signal having the high frequency, can
 be outputted from the flyback transformer by a simple construction.
 Further, when the horizontal synchronization signal has the high frequency,
 the horizontal synchronization signal is frequency-divided and the
 horizontal synchronization signal with this divided frequency synchronizes
 the driving signal of the high voltage drive circuit. Therefore, as
 auxiliary electronic parts for the high frequency are not required, the
 production cost can be reduced and the design of the products can be
 simply made.
 Meanwhile, the method of controlling the device for controlling a power
 drive synchronization signal according to the present invention makes a
 frequency-division of the horizontal synchronization signal when the
 horizontal synchronization signal has a high frequency, and synchronizes
 the driving signal of the high voltage drive circuit by the horizontal
 synchronization signal with this frequency-divided frequency.
 Accordingly, the noise on the picture can be prevented without using any
 auxiliary electronic parts for the high frequency.
 It will be apparent to those skilled in the art that various modifications
 can be made in the present invention, without departing from the spirit of
 the invention. Thus, it is intended that the present invention cover such
 modifications as well as variations thereof, within the scope of the
 appended claims and their equivalents.