Methods of manufacturing vertical memory devices at an edge region

A method of manufacturing a vertical memory device includes forming a preliminary first mold structure on a substrate, which includes main and edge regions, and the first preliminary mold structure including alternating insulation and sacrificial layers, forming a first mask on the preliminary first mold structure to expose the preliminary first mold structure between a boundary of the substrate and a first target position, partially etching the insulation and sacrificial layers using the first mask to form a preliminary second mold structure, forming a second mask on the preliminary second mold structure to expose the preliminary second mold structure between the boundary of the substrate and a second target position different from the first target position, and partially etching the insulation layers and the sacrificial layers using the second mask.

CROSS-REFERENCE TO RELATED APPLICATION

Korean Patent Application No. 10-2016-0056155, filed on May 9, 2016, in the Korean Intellectual Property Office, and entitled: “Methods of Manufacturing Vertical Memory Devices,” is incorporated by reference herein in its entirety.

BACKGROUND

Example embodiments relate to methods of manufacturing vertical memory devices. More particularly, example embodiments relate to methods of manufacturing vertical memory devices on an edge region of a substrate.

2. Description of the Related Art

A semiconductor substrate may include a main region, in which a main chip is formed, and an edge region, in which a main chip is not formed. In the fabrication of a memory device, when a plurality of layers and a plurality of structures are formed on the main region, the layers and the structures may be also formed on the edge region. Thus, an edge exposure wafer (EEW) process may be performed to remove portions of layers and structures from the edge region in order to prevent or minimize substrate contamination in subsequent manufacturing stages.

SUMMARY

According to example embodiments, there is provided a method of manufacturing a vertical memory device. In the method, a preliminary first mold structure may be formed on a substrate including a main region and an edge region. The first preliminary mold structure may include insulation layers and sacrificial layers alternately and repeatedly stacked. A first mask may be formed on the preliminary first mold structure. The first mask may expose an upper surface of the preliminary first mold structure on a region from a boundary of the substrate to a first target position. The insulation layers and the sacrificial layers may be partially etched using the first mask as an etching mask to form a preliminary second mold structure including a preliminary step structure. A second mask may be formed on the preliminary second mold structure. The second mask may expose an upper surface of the preliminary second mold structure on a region from the boundary of the substrate to a second target position, wherein the second target position is different from the first target position. The insulation layers and the sacrificial layers may be partially etched using the second mask as an etching mask to form a mold structure on the main region and the edge region of the substrate, wherein the mold structure on the edge region includes a first step portion formed by using the first mask and a second step portion formed by using the second mask.

According to example embodiments, there is provided a method of manufacturing a vertical memory device. In the method, a preliminary mold structure may be formed on a substrate including a main region and an edge region. The preliminary mold structure may include insulation layers and sacrificial layers alternately and repeatedly stacked. A first mask may be formed on the preliminary mold structure on the main region of the substrate. The first mask may serve as a mask for forming a step structure of the preliminary mold structure. A second mask may be formed on the preliminary mold structure on the edge region of the substrate. The second mask may expose an upper surface of the preliminary mold structure on a first region from a boundary of the substrate to a first target position. The insulation layers and the sacrificial layers may be partially etched using the first and second masks as an etching mask to form a first preliminary mold structure on the main region of the substrate and a second preliminary mold structure on the edge region of the substrate. A third mask may be formed on the preliminary first mold structure. The third mask may serve as a mask for forming a step structure of the preliminary first mold structure. A fourth mask may be formed on the preliminary second mold structure. The fourth mask may expose an upper surface of the preliminary second mold structure on a region from the boundary of the substrate to a second target position, wherein the second target position is different from the first target position. The insulation layers and the sacrificial layers using the third and fourth masks as an etching mask to form a second mold structure on the main region of the substrate and a first mold structure on the edge region of the substrate. A sidewall of the second mold structure includes a first step structure, and a sidewall of the first mold structure includes a second step structure different from the first step structure.

According to example embodiments, there is provided a method of manufacturing a vertical memory device, including forming a preliminary first mold structure on a substrate, the substrate including a main region and an edge region, and the first preliminary mold structure including insulation layers and sacrificial layers alternately and repeatedly stacked, forming a first mask on the preliminary first mold structure, the first mask exposing an upper surface of the preliminary first mold structure in a region between a boundary of the substrate and a first target position, partially etching the insulation layers and the sacrificial layers using the first mask as an etching mask to form a preliminary second mold structure including a preliminary step structure, forming a second mask on the preliminary second mold structure, the second mask exposing an upper surface of the preliminary second mold structure in a region between the boundary of the substrate and a second target position, wherein the second target position is farther from the boundary of the substrate than the first target position, and partially etching the insulation layers and the sacrificial layers using the second mask as an etching mask to form a mold structure on the main region and the edge region of the substrate.

DETAILED DESCRIPTION

Various example embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some example embodiments are shown.

FIGS. 1 and 2are plan views illustrating regions of a substrate, andFIGS. 3A and 3Bare cross-sectional views illustrating a vertical memory device formed on an edge region and on a main region, respectively, of the substrate in accordance with example embodiments.FIG. 2is an enlarged view of the main region and the edge region ofFIG. 1.

Referring toFIGS. 1, 2, 3A and 3B, a substrate10may include a main region1, i.e., a region in which a main chip is formed, and an edge region2, i.e., a region in which the main chip is not formed. The edge region2may include a bevel region3, i.e., a region which may be an annular area having a given width from a boundary of the substrate10.

The substrate10may include a semiconductor material, e.g., silicon and/or germanium. In example embodiments, the substrate10may include a notch portion4. Alternatively, the substrate10may include a flat zone.

A plurality of vertical memory cells may be formed on the main region1of the substrate10, as shown inFIG. 3B. The vertical memory cell may include a conductive pattern structure80, which may include a plurality of gates48and a plurality of first insulation layers14alternately and repeatedly stacked, and a vertical channel structure44through the conductive pattern structure80.

The vertical channel structure44may fill a channel hole that may extend through the conductive pattern structure80and expose an upper surface of the substrate10. The vertical channel structure44may include a channel38, a charge storage structure36including a tunnel insulation layer, a charge storage layer and a blocking dielectric layer, and a filling insulation pattern40. In example embodiments, a semiconductor pattern34may be formed between the upper surface of the substrate10and the vertical channel structure44. A pad pattern42may be formed on the vertical channel structure44in an upper portion of the channel hole.

Sidewalls of the conductive pattern structure80may have a step structure including a plurality of steps. An, e.g., exposed, upper surface of each of the steps included in the conductive pattern structure80may have a first width W1in a first direction, and thus the, e.g., exposed, upper surfaces of the steps may have substantially the same widths as each other. Wirings may be formed on the upper surfaces of the steps, respectively.

In example embodiments, the vertical memory cell may be a cell of a vertical NAND flash memory device.

Referring toFIG. 3A, a first mold structure60may be formed on the edge region2of the substrate10. The first mold structure60may include a plurality of first sacrificial layers12and a plurality of first insulation layers14alternately and repeatedly stacked. In example embodiments, the first sacrificial layer12may include a nitride, e.g., silicon nitride, and the first insulation layer14may include an oxide include, e.g., silicon oxide.

One of the sidewalls of the first mold structure60may have a step structure different from the step structure of the conductive pattern structure80. In detail, the first mold structure60may have a first sidewall adjacent to the bevel region3and second sidewalls different from the first sidewall. In example embodiments, the first sidewall of the first mold structure60may have the step structure different from the step structure of the conductive pattern structure80, and each of the second sidewalls may have the same step structure as the conductive pattern structure80.

Hereinafter, the first sidewall of the first mold structure60will be described. As illustrated inFIG. 3A, the first sidewall of the first mold structure60may include a first step portion70aand a second step portion70babove the first step portion70a. A step layer72may be formed between the first and second step portions70aand70b, so that the first and second step portions70aand70bmay be distinguished from each other by the step layer72. In example embodiments, an upper surface of the step layer72may have a width in the first direction greater than a width in the first direction of an upper surface of each step of the first and second step portions70aand70b.

The first sidewall of the first mold structure60may be formed by an edge exposure wafer (EEW) process. Thus, the first sidewall of the first mold structure60may be formed to have various shapes according to a target position of exposure.

The first step portion70aof the first mold structure60may be formed by the EEW process using a first target position T1, e.g., using the first target position T1as a point for performing exposure to remove material from the substrate10. The second step portion70bof the first mold structure60may be formed by the EEW process using a second target position T2, e.g. using the second target position T2as a point for performing exposure to remove material from the substrate10.

In example embodiments, the first target position T1may be spaced apart from the boundary of the substrate10by a second width W2in the first direction toward an inner portion of the substrate10. The second target position T2may be spaced apart from the boundary of the substrate10by a third width W3in the first direction toward the inner portion of the substrate10. The third width W3may be greater than the second width W2. In example embodiments, a difference between the second and third widths W2and W3may be greater than a range of a tolerance (or an error) in the EEW process.

In the step structure of the first sidewall of the first mold structure60, a width between a closest portion and a farthest portion from the boundary of the substrate10is referred to as a width in a horizontal direction. The width in the horizontal direction may be greater than a range of a tolerance of the target position in the EEW process. For example, when the tolerance of the target position in the EEW process is +/−0.1 mm, the range of a tolerance of the target position in the EEW process may be about 0.2 mm. The first and second step portions70aand70bmay be formed by EEW processes at the first and second target positions T1and T2, respectively, and thus the tolerance of the first target position T1may be in a range of about 0.2 mm, and the tolerance of the second target position T2may be in a range of about 0.2 mm. The width in the horizontal direction of the step structure of the first sidewall of the first mold structure60may be greater than about 0.2 mm

In example embodiments, an end of the first step portion70amay be located within the range of the tolerance from the first target position T1. An end of the second step portion70bmay be located within the range of the tolerance from the second target position T2. Thus, an area of the substrate10for forming the first and second step portions70aand70bmay increase, e.g., when compared to a mold structure formed by EEW processes using only one target position of exposure. Additionally, the first mold structure60may include a step structure having a gentle slope, e.g., when compared to a mold structure formed by an EEW process using only one target position of exposure to define a step structure with a single steep slope.

According to the tolerance in the EEW process, a plurality of steps included in the first and second step portions70aand70bmay have various shapes.

In some example embodiments, a portion of the first mold structure60may have a structure including conductive patterns and the first insulation layers14alternately and repeatedly stacked, and another portion of the first mold structure60may have a structure including the first sacrificial layers12and the first insulation layers14alternately and repeatedly stacked. The conductive pattern may include a material substantially the same as a material of the gate48in the conductive pattern structure80.

An insulating interlayer26may be formed on the substrate10to cover the conductive pattern structure80on the main region1and the first mold structure60on the edge region2. For example, the insulating interlayer26may not be formed on an edge portion of the substrate10, e.g., the insulating interlayer26may not be formed on a portion of the substrate10exposed by the first mold structure60and immediately adjacent to the boundary of the substrate10. That is, the edge portion of the substrate10may be exposed by the insulating interlayer26. A width in the first direction of the edge portion of the substrate10may have a fourth width W4less than the second width W2.

FIGS. 4A to 21Bare cross-sectional views illustrating stages of a method of manufacturing a vertical memory device in accordance with example embodiments. In detail,FIGS. 4A, 5A, 6A, 7A. . . and21A show a portion of the vertical memory device on the edge region2, andFIGS. 4B, 5B, 6B, 7B. . . and21B show a portion of the vertical memory device on the main region1.

Referring toFIGS. 4A and 4B, the first sacrificial layers12and the first insulation layers14may be alternately and repeatedly formed on the substrate10, so that a preliminary mold structure50may be formed on the substrate10.

The substrate10may include the main region and the edge region. The edge region may include a bevel region, which may be an annular area having a given width from the boundary of the substrate10. The substrate10may include a semiconductor material, e.g., silicon and/or germanium.

A portion of the preliminary mold structure50on the main region of the substrate10may be transformed into a second mold structure including a step structure by subsequent processes. A portion of the preliminary mold structure50on the edge region of the substrate10may be transformed into the first mold structure including a step structure different from the step structure of the second mold structure by subsequent processes. In example embodiments, the step structure of a first sidewall of the first mold structure adjacent the bevel region may be different from the step structure of the second mold structure.

In example embodiments, the first sacrificial layer12and the first insulation layer14may be formed by, e.g., a chemical vapor deposition (CVD) process, a plasma enhanced CVD (PE-CVD) process, or an atomic layer deposition (ALD) process. In example embodiments, a pad insulation layer may be further formed directly on the substrate10by a thermal oxidation process.

In example embodiments, the first insulation layer14may be formed of an oxide-based material, e.g., silicon oxide. The first sacrificial layer12may be formed of a material that may have an etching selectivity with respect to the first insulation layer14, and may be easily removed by a wet etching process. For example, the first sacrificial layer12may be formed of a nitride-based material, e.g., silicon nitride and/or silicon boronitride.

In example embodiments, the first sacrificial layers12may be replaced with gates48(refer toFIGS. 21A and 21B) by subsequent processes, respectively. Thus, the number of the first sacrificial layers12may be substantially the same as the number of the gates48. That is, the first sacrificial layers12may be replaced with one of a ground selection line (GSL), a word line and a string selection line (SSL).

Referring toFIGS. 5A and 5B, a first photoresist film may be coated on the preliminary mold structure50, and the first photoresist film may be exposed and developed to form a first photoresist pattern16a.

If a photoresist film on the main region and the edge region is exposed using the same exposure mask (or reticle), the photoresist film on the bevel region may be abnormally exposed, because an area of the edge region may be less than an area of the main region. Thus, after the exposure process of the photoresist film on the main region and the edge region, an EEW process for removing the photoresist film from the bevel region may be further performed.

In detail, a first photoresist film may be coated on the preliminary mold structure50, and may be exposed by a first exposure process. The first exposure process may be performed to form the second mold structure on the main region of the substrate10. Also, an EEW process may be performed to remove the first photoresist film on the edge region. Then, the first photoresist film may be developed.

Thus, the first photoresist pattern16amay be formed on the main region and the edge region. A portion of the first photoresist pattern16aon the main region may serve as an etching mask for forming the second mold structure, and a portion of the first photoresist pattern16aon the edge region may serve as an etching mask for forming the first mold structure.

As shown inFIG. 5A, a shape and a position of the first sidewall of the first mold structure may be determined by a target position of the EEW process. In the EEW process, the first target position T1may be used.

In example embodiments, the first target position T1may be spaced apart from the boundary of the substrate10by the second width W2in the first direction toward the inner portion of the substrate10. In example embodiments, the second width W2in the first direction may be in a range of about 0.5 mm to about 1.5 mm.

In the EEW process, a tolerance (or an error) between the target position of exposure and a real exposed position may be generated according to the ability of an exposure apparatus. Thus, a real end portion of the first photoresist pattern16amay be located at a first position P1, which may be located in a range R1of the tolerance from the first target position T1. For example, when the tolerance of the target position of exposure is +/−0.1 mm, the range of the tolerance of the target position of exposure may be about 0.2 mm. Thus, the first position P1may be located in a range of +/−0.1 mm from the first target position T1of exposure. A maximum difference between each of the first positions P1may be about 0.2 mm.

FIG. 5Ashows that the first position P1is exactly aligned with the first target position T1. However, the first position P1may not be exactly aligned with the first target position T1because an align key may not be used in the EEW process.

An uppermost one of the first insulation layers14and an uppermost one of the first sacrificial layers12in the preliminary mold structure50may be etched using the first photoresist pattern16aas an etching mask. Thus, one step may be formed at a sidewall of the preliminary mold structure50on the main region and the edge region.

Alternatively, at least two of the first insulation layers14and at least two of the first sacrificial layers12in the preliminary mold structure50may be etched using the first photoresist pattern16aas an etching mask. In this case, at least two of the first insulation layers14and at least two of the first sacrificial layers12in the preliminary mold structure50be removed in each subsequent etching process.

Referring toFIGS. 6A and 6B, a second photoresist pattern16bmay be formed by a trimming process of the first photoresist pattern16a.

In example embodiments, the first photoresist pattern16amay be removed by the first width W1in the first direction by the trimming process. The first width W1in the first direction may be less than the range of the tolerance of the target position of exposure in the EEW process. In example embodiments, the first width W1in the first direction may be in a range of about 100 nm to about 2000 nm. A width in the first direction of an upper surface of a step in the second mold structure subsequently formed may be determined by the first width W1.

In example embodiments, an end portion of the second photoresist pattern16bon the edge region may be located at a second position P2. The second position P2may be spaced apart from the boundary of the substrate10by the first width W1in the first direction toward an inner portion of the substrate10. Exposed upper ones of the first insulation layers14and respective upper ones of the first sacrificial layers12therebeneath in the preliminary mold structure50may be etched using the second photoresist pattern16bas an etching mask.

Referring toFIGS. 7A and 7B, a third photoresist pattern16cmay be formed by a trimming process of the second photoresist pattern16b. Exposed upper ones of the first insulation layers14and respective upper ones of the first sacrificial layers12therebeneath in the preliminary mold structure50may be etched using the third photoresist pattern16cas an etching mask.

In example embodiments, the second photoresist pattern16bmay be removed by the first width W1in the first direction by the trimming process. Thus, an end portion of the third photoresist pattern16con the edge region may be located at a third position P3spaced apart from the second position P2by the first width W1in the first direction.

In example embodiments, the trimming process may be repeatedly performed until the photoresist pattern may not have a thickness enough to be used as the etching mask. In the present embodiment, the trimming process may be performed twice per each photoresist pattern.

Referring toFIGS. 8A and 8B, a second photoresist film may be coated on the preliminary mold structure50, and the second photoresist film may be exposed and developed to form a fourth photoresist pattern18a.

In detail, a second photoresist film may be formed on the preliminary mold structure50on the main region and the edge region. The second photoresist film may be exposed by a first exposure process. The first exposure process may be performed to form the second mold structure on the main region. Also, an EEW process may be performed to remove the second photoresist film on the edge region. The second photoresist film may be developed to form the fourth photoresist pattern18aon the main region and the edge region.

Referring toFIG. 8A, in the EEW process, the first target position T1of exposure may be used. For example, when the first target position T1is exactly aligned with the first position P1without a tolerance, an end portion of the fourth photoresist pattern18amay be located at the first position P1substantially the same as the first target position T1. In another example, when the first target position T1is not aligned with the first position P1, e.g., due to tolerance of the target position of exposure, a shape of the step of the preliminary mold structure50may be changed, as will be described later.

Referring toFIG. 8B, the fourth photoresist pattern18aon the main region may be formed to form the second mold structure having a staircase shape. Thus, the fourth photoresist pattern18aon the main region may expose an edge portion of an uppermost layer in the preliminary mold structure50. In example embodiments, the exposed portion of the uppermost layer in the preliminary mold structure50may have the first width W1in the first direction.

Exposed upper ones of the first insulation layers14and respective upper ones of the first sacrificial layers12therebeneath in the preliminary mold structure50may be etched using the fourth photoresist pattern18aas an etching mask. Thus, a portion of a step structure may be formed at a sidewall of the preliminary mold structure50on the main region and the edge region.

Referring toFIGS. 9A and 9B, a fifth photoresist pattern18bmay be formed by a trimming process of the fourth photoresist pattern18a. Exposed upper ones of the first insulation layers14and upper ones of the first sacrificial layers12therebeneath in the preliminary mold structure50may be etched using the fifth photoresist pattern18bas an etching mask. In example embodiments, the fourth photoresist pattern18amay be partially removed by the first width W1in the first direction during the trimming process.

Referring toFIGS. 10A and 10B, a sixth photoresist pattern18cmay be formed by a trimming process of the fifth photoresist pattern18b. Exposed upper ones of the first insulation layers14and upper ones of the first sacrificial layers12therebeneath in the preliminary mold structure50may be etched using the sixth photoresist pattern18cas an etching mask. In example embodiments, the fifth photoresist pattern18bmay be partially removed by the first width W1in the first direction during the trimming process.

Thus, a portion of a step structure may be formed at a sidewall of the preliminary mold structure50on the main region and the edge region.

Referring toFIGS. 11A and 11B, a third photoresist film may be coated on the preliminary mold structure50, and the third photoresist film may be exposed and developed to form a seventh photoresist pattern20a.

In detail, the third photoresist film may be formed on the preliminary mold structure50on the main region and the edge region. The third photoresist film may be exposed by a first exposure process. The first exposure process may be performed to form the second mold structure on the main region of the substrate10. Also, an EEW process may be performed to remove the third photoresist film from the edge region. The third photoresist film may be developed to form the seventh photoresist pattern20aon the main region and the edge region.

Referring toFIG. 11A, in the EEW process, the second target position T2of exposure, which is different from the first target position T1of exposure, may be used. In example embodiments, the second target position T2may be spaced apart from the boundary of the substrate10by the third width W3in the first direction toward the inner portion of the substrate10. The third width W3may be greater than the second width W2.

In example embodiments, a difference between the second width W2and the third width W3may be in a range of about 0.01 mm to about 1.0 mm. In example embodiments, a difference between the second width W2and the third width W3may be greater than about ½ of the range R1of the tolerance of the target position of exposure in the EEW process.

In example embodiments, a real end portion of the seventh photoresist pattern20amay be located at a fourth position P4, and the fourth position P4may be located in the range R1of the tolerance from the second target position T2. For example, when the tolerance of the target position of exposure is +/−0.1 mm, the range of the tolerance of the target position of exposure may be about 0.2 mm. Thus, the fourth position P4may be positioned in a range of +/−0.1 mm from the second target position T2.

Referring toFIG. 11A, the fourth position P4may be exactly aligned with the second target position T2without the tolerance. In example embodiments, the seventh photoresist pattern20aon the edge region may be formed to expose an edge portion of an uppermost layer in the preliminary mold structure50.

Referring toFIG. 11B, the seventh photoresist pattern20aon the main region may be formed to form the second mold structure having a staircase shape. Exposed upper ones of the first insulation layers14and respective upper ones of the first sacrificial layers12therebeneath in the preliminary mold structure50may be etched using the seventh photoresist pattern20aas an etching mask.

That is, in the EEW processes for forming the first mold structure, at least two target positions may be used. Thus, the end portions of the photoresist patterns formed by the EEW processes may be located at different positions, so that a step structure of the first mold structure may have a gentle slope, e.g., as compared to a steep slope of a step structure formed by a single target position.

Referring toFIGS. 12A and 12B, an eighth photoresist pattern20bmay be formed by a trimming process of the seventh photoresist pattern20a. Exposed upper ones of the first insulation layers14and upper ones of the first sacrificial layers12therebeneath in the preliminary mold structure50may be etched using the eighth photoresist pattern20bas an etching mask.

Referring toFIGS. 13A and 13B, a ninth photoresist pattern20cmay be formed by a trimming process of the eighth photoresist pattern20b. Exposed upper ones of the first insulation layers14and respective upper ones of the first sacrificial layers12therebeneath in the preliminary mold structure50may be etched using the ninth photoresist pattern20cas an etching mask.

Referring toFIGS. 14A and 14B, a fourth photoresist film may be coated on the preliminary mold structure50, and the fourth photoresist film may be exposed and developed to form a tenth photoresist pattern22a.

In detail, the fourth photoresist film may be formed on the preliminary mold structure50on the main region and the edge region. The fourth photoresist film may be exposed by a first exposure process. The first exposure process may be performed to form the second mold structure on the main region of the substrate10. Also, an EEW process may be performed to remove the fourth photoresist film on the edge region. The fourth photoresist film may be developed to form the tenth photoresist pattern22aon the main region and the edge region.

Referring toFIG. 14A, in the EEW process, the second target position T2of exposure may be used. In example embodiments, when the second target position T2is exactly aligned with the fourth position P4without a tolerance, an end portion of the tenth photoresist pattern22amay be positioned at the fourth position P4substantially the same as the second target position T2. That is, end portions of the seventh photoresist pattern20aand the tenth photoresist pattern22amay be placed at the same position.

Alternatively, the second target position T2may not be aligned with the fourth position P4because of the tolerance. In this case, end portions of the seventh photoresist pattern20aand the tenth photoresist pattern22amay be located at different positions from each other. That is, the end portion of the tenth photoresist pattern22amay be located in the range of the tolerance from the second target position T2, and thus, a shape of the step structure of the preliminary mold structure50may be changed.

Referring toFIG. 14B, the tenth photoresist pattern22aon the main region may be formed to form the second mold structure having a staircase shape. Exposed upper ones of the first insulation layers14and respective upper ones of the first sacrificial layers12therebeneath in the preliminary mold structure50may be etched using the tenth photoresist pattern22aas an etching mask.

Referring toFIGS. 15A and 15B, an eleventh photoresist pattern22bmay be formed by a trimming process of the tenth photoresist pattern22a. Exposed upper ones of the first insulation layers14and respective upper ones of the first sacrificial layers12therebeneath in the preliminary mold structure50may be etched using the eleventh photoresist pattern22bas an etching mask.

Referring toFIGS. 16A and 16B, a twelfth photoresist pattern22cmay be formed by a trimming process of the eleventh photoresist pattern22b. Exposed upper ones of the first insulation layers14and respective upper ones of the first sacrificial layers12therebeneath in the preliminary mold structure50may be etched using the twelfth photoresist pattern22cas an etching mask. Thus, the second mold structure64may be formed on the main region, and the first mold structure60may be formed on the edge region.

Referring toFIG. 16A, the first sidewall adjacent to the bevel region of the first mold structure60may include the first step portion70aand the second step portion70babove the first step portion70a. The first step portion70amay be formed by the EEW process using the first target position T1of exposure. The second step portion70bmay be formed by the EEW process using the second target position T2of exposure.

In example embodiments, the step layer72may be formed between the first and second step portions70aand70b, so that the first and second step portions70aand70bmay be distinguished from each other by the step layer72. In example embodiments, an upper surface of the step layer72may have a width in the first direction greater than a width in the first direction of an upper surface of each step of the first and second step portions70aand70b, e.g., the width of an exposed upper surface of the step layer72may correspond to a difference between the second and third widths W2and W3.

The EEW processes may be performed using at least two of the target positions of exposures, respectively, so that a step structure of the first sidewall of the first mold structure60have a gentle slope. That is, performing the EEW processes with at least two different target positions of exposures, e.g., at least two different target positions with an increasing distance relative to an outermost edge of the substrate10, provides a step structure that has a gentler slope, e.g., a milder overall incline measured from an outermost edge of a lowermost step in the first step portion70ato an outermost edge of an uppermost step in the second step portion70b, as compared to a step structure formed by a single target position.

Referring toFIGS. 17A and 17B, the insulating interlayer26may be formed on the first and second mold structures60and64. The insulating interlayer26may be formed along the first sidewall of the first mold structure60on the edge region.

In example embodiments, an upper surface of the insulating interlayer26on the main region may be planarized. The insulating interlayer26on the bevel region may be partially removed to expose a surface of the bevel region. An end portion of the insulating interlayer26may be located at a position spaced apart from the boundary of the substrate10by the fourth width W4in the first direction toward the inner portion of the substrate10. The fourth width W4may be less than the second width W2. The insulating interlayer26may cover the first and second mold structures60and64.

Referring toFIGS. 18A and 18B, a hard mask layer30may be formed on the insulating interlayer26and the surface of the bevel region. The hard mask layer30on the bevel region may be partially removed to expose the bevel region of the substrate10. An end portion of the hard mask layer30may be located at a position spaced apart from the boundary of the substrate10by a fifth width W5in the first direction toward the inner portion of the substrate10. The fifth width W5may be less than the fourth width W4. Thus, an edge portion of the hard mask layer30may directly contact the surface of the substrate10.

In example embodiments, the hard mask layer30may include amorphous carbon. The hard mask layer30may include a conductive material. The hard mask layer30may be formed by a CVD process.

The hard mask layer30may serve as an etching mask for etching the second mold structure64by a subsequent etching process. Thus, as heights of the first and second mold structures60and64increase, a thickness of the hard mask layer30may be greater. In example embodiments, the hard mask layer30may have a thickness of about 0.5 μm to about 5 μm.

The hard mask layer30may contact the bevel region of the substrate10, so that the hard mask layer30and the substrate10may be electrically connected to each other. Thus, when the subsequent etching process is performed, a voltage may not be generated between the hard mask layer30and the substrate10.

The first sidewall of the first mold structure60may have a gentle slope. Thus, although the hard mask layer30is formed by a process having a poor step coverage characteristic, the hard mask layer30on the first sidewall of the first mold structure60may have uniform thickness. Also, failures, e.g., that the hard mask layer30is not formed or is formed to have a thin thickness on the first sidewall of the first mold structure60, may not be generated.

If the hard mask layer30is not formed or is formed to have a thin thickness on the first sidewall of the first mold structure60, e.g., when a first sidewall of a mold structure does not have a gentle slope, a disconnected portion between the hard mask layer30and the substrate10may be formed. Thus, when a subsequent etching process is performed, a voltage may be generated between the hard mask layer30and the substrate10, so that an arcing may be generated. Damages and particles of the substrate10may be generated due to the arcing, and thus failures may be generated in the vertical memory device on the substrate10.

Referring toFIGS. 19A and 19B, the hard mask layer30may be patterned by a photolithograph process to form a hard mask30a. The hard mask30amay include a hole therein. The second mold structure64may be etched using the hard mask30aas an etching mask to form the channel hole32exposing an upper surface of the substrate10. In example embodiments, a plurality of channel holes32may be formed.

In example embodiments, the channel hole32may be formed through the second mold structure64. That is, an actual vertical memory device may not be formed on the edge region of the substrate10, so that the channel hole32may not be formed at the first mold structure60.

Alternatively, the channel hole32may be formed through the first and second mold structures60and64. That is, the channel hole32may be also formed through the first mold structure60. In example embodiments, an arrangement of the channel holes32in the first mold structure60may be different from an arrangement of the channel holes32in the second mold structure64. For example, a distance between the channel holes32in the first mold structure60may be greater than a distance between the channel holes32in the second mold structure64.

The first and second mold structures60and64may include the first sacrificial layers12and the first insulation layers14alternately and repeatedly stacked. As the number of the first sacrificial layers12and the first insulation layer14increases, a thickness of each of the first and second mold structures60and64may increase. In example embodiments, each of the first and second mold structures60and64may have a thickness of about 1 μm to about 10 μm.

When the second mold structure64having the thickness of, e.g., about 1 μm to about 10 μm, is etched to form the channel hole32, a high power may be used in the etching process. Also, a high voltage may be supplied to a bottom of the substrate10.

During the etching process, the hard mask30aand the substrate10of the bevel region may contact to each other. The hard mask30amay be formed on the first sidewall of the first mold structure60having a uniform thickness. Thus, a voltage may not be generated between the hard mask30aand the bottom of substrate10, so that an arcing may not be generated.

After forming the channel hole32, the hard mask30amay be removed. Then, processes for manufacturing the vertical memory device on the main region may be performed. Hereinafter, a process for manufacturing the vertical memory device in accordance with an example embodiment may be described, but may not be limited to the below-illustrated one.

Referring toFIG. 20, the vertical channel structure44may be formed to fill the channel hole32. The vertical channel structure44may be formed to include the channel38, the charge storage structure36including a tunnel insulation layer, a charge storage layer, and a blocking dielectric layer, and the filling insulation pattern40. In example embodiments, the semiconductor pattern34may be formed between the upper surface of the substrate10exposed by the channel hole32and the vertical channel structure44.

In example embodiments, the semiconductor pattern34may be formed in a lower portion of the channel hole32. For example, the semiconductor pattern34may be formed by a selective epitaxial growth (SEG) process using the upper surface of the substrate10exposed by the channel hole32as a seed. Alternatively, an amorphous silicon layer filling the lower portion of the channel hole32may be formed, and a laser epitaxial growth (LEG) process or a solid phase epitaxy (SPE) process may be performed thereon to form the semiconductor pattern34.

The blocking dielectric layer, the charge storage layer, and the tunnel insulation layer may be sequentially formed on a sidewall of the channel hole32, and upper surfaces of the semiconductor pattern34and the insulating interlayer26. The blocking dielectric layer, the charge storage layer, and the tunnel insulation layer may be etched back to form the charge storage structure36including the blocking dielectric layer, the charge storage layer, and the tunnel insulation layer.

A channel layer may be formed on the tunnel insulation layer, the semiconductor pattern34, and the insulating interlayer26, and a filling insulation layer may be formed to fill a remaining portion of the channel hole32. Upper surfaces of the channel layer and the filling insulation layer may be planarized until the upper surface of the insulating interlayer26may be exposed to form the channel38and the filling insulation pattern40. Thus, the vertical channel structure44may be formed on the semiconductor pattern34. The blocking dielectric layer, the charge storage layer, and the tunnel insulation layer may be formed by a CVD process, a PE-CVD process and an ALD process.

In example embodiments, the channel layer may be formed of doped polysilicon or amorphous silicon. Alternatively, the channel layer may be formed of polysilicon or amorphous silicon, and then a heat treatment or a laser beam irradiation may be further performed on the channel layer. In this case, the channel layer may include single crystalline silicon. The filling insulation layer may be formed of, e.g., silicon oxide or silicon nitride. The channel layer and the filling insulation layer may be formed by a CVD process, a PECVD process, an ALD process, a PVD process, a sputtering process, etc. In example embodiments, the formation of the filling insulation layer may be omitted, and the channel38may have a pillar shape filling the channel hole32.

The pad pattern42may be formed in an upper portion of the channel hole32. In example embodiments, an upper portion of the vertical channel structure44may be partially removed by, e.g., an etch-back process to form a recess, and the pad pattern42may be formed to fill the recess. The pad pattern42may be formed of, e.g., polysilicon.

Referring toFIGS. 21A and 21B, the first sacrificial layer12of the second mold structure64may be replaced with a conductive pattern to form the gate48. In detail, the insulating interlayer26and the first and second mold structures60and64may be etched to form an opening exposing an upper surface of the substrate10. The first sacrificial layer12may be removed through the opening to form a gap. A conductive material may fill the gap, so that the conductive pattern may be formed.

In example embodiments, the first sacrificial layer12of the second mold structure64may be completely removed, and may be replaced with the conductive pattern. The conductive pattern may serve as the gate48. Thus, a conductive pattern structure80including the gates48and the first insulation layers14alternately and repeatedly stacked may be formed on the main region of the substrate10.

However, the first mold structure60may not be transformed into an actual vertical memory device, so that the first sacrificial layer12may not be replaced with the conductive pattern. That is, the first sacrificial layer12may remain on the edge region of the substrate10. Alternatively, some or all of the first sacrificial layers12of the first mold structure60may be replaced with the conductive pattern.

The conductive material may include a metal, e.g., tungsten, aluminum, copper, titanium or tantalum, or a nitride of the above metal. In example embodiments, the conductive material may include tungsten.

An impurity region may be formed at an upper portion of the substrate10exposed by the opening. An insulation pattern may be formed on the impurity region to fill the opening. A plurality of contact plugs contacting an edge portion of the gates48may be formed through the insulating interlayer26.

In example embodiments, an insulation pattern may be formed on a sidewall of the opening. A conductive material may fill the opening, so that a common source line (CSL) may be formed on the impurity region.

A bit line may be formed on the pad pattern42, and may be electrically connected with the pad pattern42. A wiring line may be formed on the contact plugs, and may be electrically connected with the contact plugs.

As described above, in the etching process for forming the channel hole, the arcing may be decreased. Thus, failures of the vertical memory device may decrease.

FIGS. 22 to 28are cross-sectional views illustrating stages of a method of manufacturing a vertical memory device in accordance with example embodiments. The method of manufacturing the vertical memory device may include same or similar processes to those illustrated with reference toFIGS. 5A to 21B. In example embodiments, the shape of the step structure of the first mold structure may be variously changed according to the tolerance of the target position of exposure.

First, processes substantially the same as or similar to those illustrated with reference toFIGS. 4A to 7Bare performed.

Next, referring toFIG. 22, a second photoresist film may be coated on the preliminary mold structure50, and the second photoresist film may be exposed and developed to form a fourth photoresist pattern19a. In an EEW process, the first target position T1of exposure may be used.

In example embodiments, when the first target position T1is aligned with a tolerance, an end portion of the fourth photoresist pattern19amay be located at a first position P1′ different from the first target position T1. That is, an end portion of the fourth photoresist pattern19amay be different from an end portion of the first photoresist pattern16a. The first position P1′ may be located in the range R1of the tolerance from the first target position T1.

Exposed upper ones of the first insulation layers14and respective upper ones of the first sacrificial layers12therebeneath in the preliminary mold structure50may be etched using the fourth photoresist pattern19aas an etching mask. Thus, a portion of a step structure may be formed at a sidewall of the preliminary mold structure50on the main region and the edge region.

The fourth photoresist pattern19amay have a shape different from a shape of the fourth photoresist pattern18ashown inFIG. 8A, due to the tolerance in the EEW process. Thus, a step structure of the preliminary mold structure50may have a shape different from a shape of the step structure of the preliminary mold structure50shown inFIG. 8A.

Referring toFIG. 23, a fifth photoresist pattern19bmay be formed by a trimming process of the fourth photoresist pattern19a. Exposed upper ones of the first insulation layers14and respective upper ones of the first sacrificial layers12therebeneath in the preliminary mold structure50may be etched using the fifth photoresist pattern19bas an etching mask.

Referring toFIG. 24, a sixth photoresist pattern19cmay be formed by a trimming process of the fifth photoresist pattern19b. Exposed upper ones of the first insulation layers14and respective upper ones of the first sacrificial layers12therebeneath in the preliminary mold structure50may be etched using the sixth photoresist pattern19cas an etching mask. Thus, a first step layer of the first mold structure60may be formed on the edge region.

Referring toFIG. 25, processes substantially the same as or similar to those illustrated with reference toFIGS. 11A to 13Bare performed. That is, in the EEW process, the second target position T2of exposure may be used. Thus, as shown inFIG. 25, a structure may be formed on the edge region.

Referring toFIG. 26, a fourth photoresist film may be coated on the preliminary mold structure50, and the fourth photoresist film may be exposed and developed to form a tenth photoresist pattern23a. In the EEW process, the second target position T2of exposure may be used.

In example embodiments, the second target position T2may be aligned with a tolerance, so that an end portion of the tenth photoresist pattern23amay be located at a fourth position P4′ different from the first target position T2. That is, an end portion of the tenth photoresist pattern23amay be different from an end portion of the seventh photoresist pattern20a(refer toFIG. 11A). The fourth position P4′ may be located in the range of the tolerance from the second target position T2.

Exposed upper ones of the first insulation layers14and respective upper ones of the first sacrificial layers12therebeneath in the preliminary mold structure50may be etched using the tenth photoresist pattern19aas an etching mask. Thus, a portion of a step structure may be formed at a sidewall of the preliminary mold structure50on the main region and the edge region.

The tenth photoresist pattern may have a shape different from a shape of the tenth photoresist pattern shown inFIG. 14A, due to the tolerance in the EEW process. Thus, a step structure of the preliminary mold structure50may have a shape different from a shape of the step structure of the preliminary mold structure50shown inFIG. 14A.

Referring toFIG. 27, an eleventh photoresist pattern23bmay be formed by a trimming process of the tenth photoresist pattern23a. Exposed upper ones of the first insulation layers14and respective upper ones of the first sacrificial layers12therebeneath in the preliminary mold structure50may be etched using the eleventh photoresist pattern23bas an etching mask.

Referring toFIG. 28, a twelfth photoresist pattern23cmay be formed by a trimming process of the eleventh photoresist pattern23b. Exposed upper ones of the first insulation layers14and respective upper ones of the first sacrificial layers12therebeneath in the preliminary mold structure50may be etched using the twelfth photoresist pattern23cas an etching mask. Thus, the second mold structure64may be formed on the main region, and the first mold structure60may be formed on the edge region.

The first sidewall adjacent to the bevel region of the first mold structure60may include the first step portion70aand the second step portion70babove the first step portion70a. The first step portion70amay be formed by the EEW process using the first target position T1of exposure. The second step portion70bmay be formed by the EEW process using the second target position T2of exposure.

In example embodiments, a step layer72may be formed between the first and second step portions70aand70a, so that the first and second step portions70aand70bmay be distinguished from each other by the step layer72. In example embodiments, an upper surface of the step layer structure72may have a width in the first direction greater than a width in the first direction of each step of the first and second step portions70aand70b.

As described above, shapes of the first step portion and the second step portion of the first mold structure may be variously changed according to the tolerance of the target position of exposure. That is, steps of the first and second step portions70aand70bof the first mold structure60may have various shapes according to the tolerance of the target position of exposure, and may not be limited to the above-illustrated one.

Then, processes substantially the same as or similar to those illustrated with reference toFIGS. 17A to 21Bare performed to form the vertical memory device.

FIGS. 29 to 35are cross-sectional views illustrating stages of a method of manufacturing a vertical memory device in accordance with example embodiments.

The method of manufacturing the vertical memory device may include processes the same as or similar to those illustrated with reference toFIGS. 5A to 21B, except for the EEW processes. That is, the EEW processes may be performed using the second target position of exposure, and then the EEW processes may be performed using the first target position of exposure. In this case, when all of the EEW processes are performed without a tolerance of the target position of exposure, a step structure of the first mold structure may have a shape substantially the same as a shape of the step structure of the first mold structure shown inFIG. 3A.

In detail, first, processes substantially the same as or similar to those illustrated with reference toFIGS. 4A and 4Bare performed, so that the preliminary mold structure50including the first sacrificial layers12and the first insulation layers14repeatedly and alternately stacked may be formed.

Referring toFIG. 29, a first photoresist film may be coated on the preliminary mold structure50, and the first photoresist film may be exposed and developed to form a first photoresist pattern116a. In an EEW process, the second target position T2of exposure may be used.

In example embodiments, when the second target position T2is exactly aligned without a tolerance, the end portion of the first photoresist pattern23amay be located at the second portion P2substantially the same as the second target position T2, as shown inFIG. 29.

Exposed upper ones of the first insulation layers14and respective upper ones of the first sacrificial layers12therebeneath in the preliminary mold structure50may be etched using the first photoresist pattern116aas an etching mask.

Referring toFIG. 30, a second photoresist pattern may be formed by a trimming process of the first photoresist pattern116a. Exposed upper ones of the first insulation layers14and respective upper ones of the first sacrificial layers12therebeneath in the preliminary mold structure50may be etched using the second photoresist pattern as an etching mask. A third photoresist pattern116cmay be formed by a trimming process of the second photoresist pattern. Exposed upper ones of the first insulation layers14and respective upper ones of the first sacrificial layers12therebeneath in the preliminary mold structure50may be etched using the third second photoresist pattern116cas an etching mask.

Referring toFIG. 31, a second photoresist film may be coated on the preliminary mold structure50, and the second photoresist film may be exposed and developed to form a fourth photoresist pattern118a. In an EEW process, the second target position T2of exposure may be used.

In example embodiments, the end portion of the fourth photoresist pattern118amay be exactly aligned with the second target position T2without the tolerance, as shown inFIG. 31. Alternatively, the end portion of the fourth photoresist pattern118amay not be exactly aligned with the second target position T2, due to the tolerance in the EEW process. That is, the end portion of the fourth photoresist pattern118amay be located in the range of the tolerance from the second target position T2.

Exposed upper ones of the first insulation layers14and respective upper ones of the first sacrificial layers12therebeneath in the preliminary mold structure50may be etched using the fourth photoresist pattern118aas an etching mask.

Referring toFIG. 32, a fifth photoresist pattern may be formed by a trimming process of the fourth photoresist pattern118a. Exposed upper ones of the first insulation layers14and respective upper ones of the first sacrificial layers12therebeneath in the preliminary mold structure50may be etched using the fifth photoresist pattern as an etching mask. A sixth photoresist pattern118cmay be formed by a trimming process of the fifth photoresist pattern. Exposed upper ones of the first insulation layers14and respective upper ones of the first sacrificial layers12therebeneath in the preliminary mold structure50may be etched using the sixth photoresist pattern118cas an etching mask. Thus, the second step layer70bof the first mold structures50may be formed on the edge region.

Referring toFIG. 33, a third photoresist film may be coated on the preliminary mold structure50, and the third photoresist film may be exposed and developed to form a seventh photoresist pattern120a.

In the EEW process, the first target position T1different from the second target position T2of exposure may be used. The second width W2in the first direction between the first target position T1and the boundary of the substrate10may be less than the third width W3in the first direction between the second target position T2and the boundary of the substrate10.

Exposed upper ones of the first insulation layers14and respective upper ones of the first sacrificial layers12therebeneath in the preliminary mold structure50may be etched using the seventh photoresist pattern120aas an etching mask.

Referring toFIG. 34, an eighth photoresist pattern may be formed by a trimming process of the seventh photoresist pattern120a. Exposed upper ones of the first insulation layers14and respective upper ones of the first sacrificial layers12therebeneath in the preliminary mold structure50may be etched using the eighth photoresist pattern as an etching mask. A ninth photoresist pattern120cmay be formed by a trimming process of the eighth photoresist pattern. Exposed upper ones of the first insulation layers14and respective upper ones of the first sacrificial layers12therebeneath in the preliminary mold structure50may be etched using the ninth photoresist pattern120cas an etching mask.

Referring toFIG. 35, forming a photoresist pattern, etching, trimming and etching may be sequentially performed to form the first step portion70a, as those illustrated with reference toFIGS. 33 and 34. Thus, the first mold structure60including the first and second step portions70aand70bmay be formed on the edge region. In the EEW process, the second target position T1of exposure may be used.

As described above, the EEW processes may be performed using at least two of the target positions of exposures, respectively, so that a step structure of the first sidewall of the first mold structure60have a gentle slope. Then, processes substantially the same as or similar to those illustrated with reference toFIGS. 17A to 21Bare performed to form the vertical memory device.

In the above, the EEW processes may be performed using two target positions of exposure. Alternatively, the EEW processes may be performed using three or more target position of exposure.

When the target positions are changed, the step portions may be distinguished from each other. Thus, the number of the target positions may be same as the number of the step portions. The step layers may be formed between the step portions, respectively, and an upper surface of each of the step layers may have a width in the first direction greater than a width in the first direction of an upper surface of each step of the step portions.

FIG. 36is a cross-sectional view illustrating vertical memory devices in accordance with example embodiments. In detail,FIG. 36shows a mold structure on the edge region of the substrate10.

Referring toFIG. 36, a first sidewall of the mold structure60amay include the first step portion70a, the second step portion70band a third step portion70c. Also, a first step layer72amay be formed between the first and second step portions70aand70b, and a second step layer72bmay be formed between the second and third step portions70band70c.

The first step portion70amay be formed by an EEW process using the first target position T1of exposure. The second step portion70bmay be formed by an EEW process using the second target position T2of exposure. The third step portion70cmay be formed by an EEW process using a third target position T3of exposure.

As the number of the target positions in the EEW processes increases, an area of the substrate10for forming the first, second and third step portions70a,70band70cin the mold structure60amay increase. Thus, the first sidewall of the mold structure60amay have a gentle slope.

By way of summation and review, example embodiments provide a method of manufacturing a vertical memory device on an edge region of a substrate. That is, as described above, the mold structure on the edge region may be formed by EEW processes using at least two target positions of exposure to have a sidewall of a gentle slope, and thus the hard mask, e.g., an amorphous carbon layer, having a uniform thickness may be formed on the mold structure. When the channel hole is formed by the etching process, damages to the mold structure, e.g., due to contaminating particles and arcing, may decrease. Thus, the vertical memory device may have high reliability.