Utilization of backside silicidation to form dual side contacted capacitor

An integrated circuit structure may include a capacitor having a semiconductor layer as a first plate and a gate layer as a second plate. A capacitor dielectric layer may separate the first plate and the second plate. A backside metallization may be coupled to the first plate of the capacitor. A front-side metallization may be coupled to the second plate of the capacitor. The front-side metallization may be arranged distal from the backside metallization.

TECHNICAL FIELD

The present disclosure generally relates to integrated circuits (ICs). More specifically, the present disclosure relates to a method and apparatus for backside silicidation for forming dual side contacted capacitors.

BACKGROUND

Mobile radio frequency (RF) chip designs (e.g., mobile RF transceivers), including high performance diplexers, have migrated to a deep sub-micron process node due to cost and power consumption considerations. The design of such mobile RF transceivers becomes complex at this deep sub-micron process node. The design complexity of these mobile RF transceivers is further complicated by added circuit functions to support communication enhancements, such as carrier aggregation. Further design challenges for mobile RF transceivers include analog/RF performance considerations, including mismatch, noise and other performance considerations. The design of these mobile RF transceivers includes the use of additional passive devices, for example, to suppress resonance, and/or to perform filtering, bypassing and coupling.

Passive on glass devices involve high performance inductor and capacitor components that have a variety of advantages over other technologies, such as surface mount technology or multi-layer ceramic chips that are commonly used in the fabrication of mobile radio frequency (RF) chip designs. The design complexity of mobile RF transceivers is complicated by the migration to a deep sub-micron process node due to cost and power consumption considerations. Spacing considerations also affect mobile RF transceiver design deep sub-micron process nodes, such as large capacitors, which may cause a performance bottle-neck during design integration of RF chip designs. For example, metal oxide semiconductor (MOS) capacitors may be used in RF applications to provide an increased capacitance density. Unfortunately, MOS capacitors that are used in advanced complementary MOS (CMOS) processing may occupy a large area to achieve a specified capacitance density.

SUMMARY

An integrated circuit structure may include a capacitor having a semiconductor layer as a first plate and a gate layer as a second plate. A capacitor dielectric layer may separate the first plate and the second plate. A backside metallization may be coupled to the first plate of the capacitor, and a front-side metallization may be coupled to the second plate of the capacitor. The front-side metallization may be arranged distal from the backside metallization.

A method of constructing an integrated circuit structure may include fabricating a device supported by an isolation layer and disposed on a sacrificial substrate. The method may further include depositing a front-side contact layer on a gate layer of the device. A front-side metallization in a front-side dielectric layer may be fabricated on the device and coupled to the front-side contact layer. A handle substrate may be bonded to the front-side dielectric layer on the device. The method may further include removing the sacrificial substrate. A backside contact layer may be deposited on a semiconductor layer of the device. A backside metallization may be fabricated in a backside dielectric layer supporting the isolation layer. The backside metallization may be coupled to the backside contact layer and may be arranged distal from the front-side metallization.

An integrated circuit structure may include a means for storing charge. The means for storing charge may be supported by an isolation layer and a backside dielectric layer. A backside metallization may be arranged in the backside dielectric layer and may be coupled to the charge storing means. A front-side metallization may be arranged in a front-side dielectric layer on the charge storing means. The front-side metallization may be coupled to the charge storing means. The front-side metallization may be arranged distal from the backside metallization.

A radio frequency (RF) front end module may include an integrated radio frequency (RF) circuit structure having a capacitor including a semiconductor layer as a first plate and a gate layer as a second plate. The first plate and the second plate may be separated by a capacitor dielectric layer. A backside metallization may be coupled to the first plate of the capacitor, and a front-side metallization may be coupled to the second plate of the capacitor. The front-side metallization may be arranged distal from the backside metallization. A switch transistor may be coupled to the capacitor. An antenna may be coupled to an output of the switch transistor.

DETAILED DESCRIPTION

Mobile radio frequency (RF) chip designs (e.g., mobile RF transceivers) have migrated to a deep sub-micron process node due to cost and power consumption considerations. The design complexity of mobile RF transceivers is further complicated by added circuit functions to support communication enhancements, such as carrier aggregation. Further design challenges for mobile RF transceivers include analog/RF performance considerations, including mismatch, noise and other performance considerations. The design of these mobile RF transceivers includes the use of passive devices, for example, to suppress resonance, and/or to perform filtering, bypassing and coupling.

Successful fabrication of modern semiconductor chip products involves interplay between the materials and the processes employed. In particular, the formation of passive devices during semiconductor fabrication in back-end-of-line (BEOL) processes is an increasingly challenging part of the process flow. This is particularly true in terms of maintaining a small feature size. The same challenge of maintaining a small feature size also applies to passive on glass (POG) technology, where high performance components such as inductors and capacitors are built upon a highly insulative substrate that may also have a very low loss to support mobile RF transceiver design.

The design of these mobile RF transceivers may include the use of silicon on insulator technology. Silicon on insulator (SOI) technology replaces conventional silicon substrates with a layered silicon-insulator-silicon substrate to reduce parasitic device capacitance and improve performance. SOI-based devices differ from conventional, silicon-built devices because the silicon junction is above an electrical isolator, typically a buried oxide (BOX) layer. A reduced thickness BOX layer, however, may not sufficiently reduce the parasitic capacitance caused by the proximity of a device on the silicon layer and a substrate supporting the BOX layer. In addition, thinning of a body within SOI-based devices results in a body resistance that has become a major limiting factor in SOI-based capacitors.

Capacitors are passive elements used in integrated circuits for storing an electrical charge. Capacitors are often made using plates or structures that are conductive with an insulating material between the plates. The amount of storage, or capacitance, for a given capacitor is contingent upon the materials used to make the plates and the insulator, the area of the plates, and the spacing between the plates. The insulating material is often a dielectric material. Metal oxide semiconductor capacitors (MOS) capacitors are one example of a parallel plate capacitor, in which the insulator is a gate oxide, and the plates are made of a body and a gate of a device.

MOS capacitors may be used in RF applications to provide an increased capacitance density. Unfortunately, MOS capacitors used in advanced complementary MOS (CMOS) processing may occupy a large area. Moreover, the thinning of the body in SOI devices yields a substantial body resistance that has become a limiting factor in MOS capacitor performance. As a result, instead of one large area capacitor, many small area capacitors are used to provide a desired capacitance density. This results in inefficient use of chip space, increased chip complexity, and lower chip performance.

Various aspects of the disclosure provide techniques for backside silicidation for forming dual side contacted capacitors in integrated RF circuit structures. The process flow for semiconductor fabrication of the integrated RF circuit structure may include front-end-of-line (FEOL) processes, middle-of-line (MOL) processes, and back-end-of-line (BEOL) processes. The front-end-of-line processes may include the set of process steps that form the devices, such as transistors, capacitors, diodes. The FEOL processes include ion implantation, anneals, oxidation, chemical vapor deposition (CVD) or atomic layer deposition (ALD), etching, chemical mechanical polishing (CMP), epitaxy. The middle-of-line processes may include the set of process steps that enable connection of the transistors to BEOL interconnects. These steps include silicidation and contact formation as well as stress introduction. The back-end-of-line processes may include the set of process steps that form the interconnects that tie the independent transistors and form circuits. Currently, copper and aluminum provide the interconnects, but with further development of the technology other conductive material may be used.

It will be understood that the term “layer” includes film and is not to be construed as indicating a vertical or horizontal thickness unless otherwise stated. As described herein, the term “substrate” may refer to a substrate of a diced wafer or may refer to a substrate of a wafer that is not diced. Similarly, the terms chip and die may be used interchangeably unless such interchanging would tax credulity.

Aspects of the present disclosure describe a post layer-transfer metallization for forming a dual side contacted capacitor (e.g., a MOS capacitor). The post transfer metallization process may form a backside metallization coupled to a first plate of the capacitor. In addition, a front-side metallization distal from the backside metallization may be coupled to a second plate of the capacitor. In this arrangement, the dual side contacted capacitor may provide a desired capacitance density by using a single capacitor without having to perform conventional capacitor subdivision to achieve a desired capacitance density.

One goal driving the wireless communication industry is providing consumers with increased bandwidth. The use of carrier aggregation in current generation communications provides one possible solution for achieving this goal. Carrier aggregation enables a wireless carrier, having licenses to two frequency bands (e.g., 700 MHz and 2 GHz) in a particular geographic area, to maximize bandwidth by simultaneously using both frequencies for a single communication stream. While an increased amount of data is provided to the end user, carrier aggregation implementation is complicated by noise created at the harmonic frequencies due to the frequencies used for data transmission. For example, 700 MHz transmissions may create harmonics at 2.1 GHz, which interfere with data broadcast at 2 GHz frequencies.

For wireless communication, passive devices are used to process signals in a carrier aggregation system. In carrier aggregation systems, signals are communicated with both high band and low band frequencies. In a chipset, a passive device (e.g., a diplexer) is usually inserted between an antenna and a tuner (or a radio frequency (RF) switch) to ensure high performance. Usually, a diplexer design includes inductors and capacitors. Diplexers can attain high performance by using inductors and capacitors that have a high quality (Q)-factor. High performance diplexers can also be attained by reducing the electromagnetic coupling between components, which may be achieved through an arrangement of the geometry and direction of the components.

FIG. 1Ais a schematic diagram of a radio frequency (RF) front end (RFFE) module100employing a diplexer200according to an aspect of the present disclosure. The RF front end module100includes power amplifiers102, duplexer/filters104, and a radio frequency (RF) switch module106. The power amplifiers102amplify signal(s) to a certain power level for transmission. The duplexer/filters104filter the input/output signals according to a variety of different parameters, including frequency, insertion loss, rejection or other like parameters. In addition, the RF switch module106may select certain portions of the input signals to pass on to the rest of the RF front end module100.

The RF front end module100also includes tuner circuitry112(e.g., first tuner circuitry112A and second tuner circuitry112B), the diplexer200, a capacitor116, an inductor118, a ground terminal115and an antenna114. The tuner circuitry112(e.g., the first tuner circuitry112A and the second tuner circuitry112B) includes components such as a tuner, a portable data entry terminal (PDET), and a house keeping analog to digital converter (HKADC). The tuner circuitry112may perform impedance tuning (e.g., a voltage standing wave ratio (VSWR) optimization) for the antenna114. The RF front end module100also includes a passive combiner108coupled to a wireless transceiver (WTR)120. The passive combiner108combines the detected power from the first tuner circuitry112A and the second tuner circuitry112B. The wireless transceiver120processes the information from the passive combiner108and provides this information to a modem130(e.g., a mobile station modem (MSM)). The modem130provides a digital signal to an application processor (AP)140.

As shown inFIG. 1A, the diplexer200is between the tuner component of the tuner circuitry112and the capacitor116, the inductor118, and the antenna114. The diplexer200may be placed between the antenna114and the tuner circuitry112to provide high system performance from the RF front end module100to a chipset including the wireless transceiver120, the modem130and the application processor140. The diplexer200also performs frequency domain multiplexing on both high band frequencies and low band frequencies. After the diplexer200performs its frequency multiplexing functions on the input signals, the output of the diplexer200is fed to an optional LC (inductor/capacitor) network including the capacitor116and the inductor118. The LC network may provide extra impedance matching components for the antenna114, when desired. Then a signal with the particular frequency is transmitted or received by the antenna114. Although a single capacitor and inductor are shown, multiple components are also contemplated.

FIG. 1Bis a schematic diagram of a wireless local area network (WLAN) (e.g., WiFi) module170including a first diplexer200-1and an RF front end module150including a second diplexer200-2for a chipset160to provide carrier aggregation according to an aspect of the present disclosure. The WiFi module170includes the first diplexer200-1communicably coupling an antenna192to a wireless local area network module (e.g., WLAN module172). The RF front end module150includes the second diplexer200-2communicably coupling an antenna194to the wireless transceiver (WTR)120through a duplexer180. The wireless transceiver120and the WLAN module172of the WiFi module170are coupled to a modem (MSM, e.g., baseband modem)130that is powered by a power supply152through a power management integrated circuit (PMIC)156. The chipset160also includes capacitors162and164, as well as an inductor(s)166to provide signal integrity. The PMIC156, the modem130, the wireless transceiver120, and the WLAN module172each include capacitors (e.g.,158,132,122, and174) and operate according to a clock154. The geometry and arrangement of the various inductor and capacitor components in the chipset160may reduce the electromagnetic coupling between the components.

FIG. 2Ais a diagram of a diplexer200according to an aspect of the present disclosure. The diplexer200includes a high band (HB) input port212, a low band (LB) input port214, and an antenna216. A high band path of the diplexer200includes a high band antenna switch210-1. A low band path of the diplexer200includes a low band antenna switch210-2. A wireless device including an RF front end module may use the antenna switches210and the diplexer200to enable a wide range band for an RF input and an RF output of the wireless device. In addition, the antenna216may be a multiple input, multiple output (MIMO) antenna. Multiple input, multiple output antennas will be widely used for the RF front end of wireless devices to support features such as carrier aggregation.

FIG. 2Bis a diagram of an RF front end module250according to an aspect of the present disclosure. The RF front end module250includes the antenna switch (ASW)210and diplexer200(or triplexer) to enable the wide range band noted inFIG. 2A. In addition, the RF front end module250includes filters230, an RF switch220and power amplifiers218supported by a substrate202. The filters230may include various LC filters, having inductors (L) and capacitors (C) arranged along the substrate202for forming a diplexer, a triplexer, low pass filters, balun filters, and/or notch filters to prevent high order harmonics in the RF front end module250. The diplexer200may be implemented as a surface mount device (SMD) on a system board201(e.g., printed circuit board (PCB) or package substrate). Alternatively, the diplexer200may be implemented on the substrate202.

In this arrangement, the RF front end module250is implemented using silicon on insulator (SOI) technology that includes capacitors, such as MOS capacitors. Unfortunately, the use of MOS capacitors in advanced complementary MOS (CMOS) processing results in the consumption of a large area to provide a specified capacitance density. Moreover, due to the thinning of the body in SOI devices, the body resistance is a limiting factor in MOS capacitor performance, in which the body is operated as one of the MOS capacitor plates. As a result, instead of one large area capacitor, many small area capacitors are used to provide a desired capacitance density. This results in inefficient use of chip space, increased chip complexity, and lower chip performance. As a result, aspects of the present disclosure include a layer transfer process to form a dual side contacted capacitor (e.g., a MOS capacitor), as shown inFIGS. 3A-3E and 4.

FIGS. 3A to 3Eshow cross-sectional views of an integrated radio frequency (RF) circuit structure300during a layer transfer process according to aspects of the present disclosure. As shown inFIG. 3A, an RF silicon on insulator (SOI) device includes a device310on a buried oxide (BOX) layer320supported by a sacrificial substrate301(e.g., a bulk wafer). The RF SOI device also includes interconnects350coupled to the device310within a first dielectric layer306. As shown inFIG. 3B, a handle substrate302is bonded to the first dielectric layer306of the RF SOI device. In addition, the sacrificial substrate301is removed. Removal of the sacrificial substrate301using the layer transfer process enables high-performance, low-parasitic RF devices by increasing the dielectric thickness. That is, a parasitic capacitance of the RF SOI device is proportional to the dielectric thickness, which determines the distance between the device310and the handle substrate302.

As shown inFIG. 3C, the RF SOI device is flipped once the handle substrate302is secured and the sacrificial substrate301is removed. As shown inFIG. 3D, a post layer transfer metallization process is performed using, for example, a regular complementary metal oxide semiconductor (CMOS) process. As shown inFIG. 3E, an integrated RF circuit structure300is completed by depositing a passivation layer, opening bond pads, depositing a redistribution layer, and forming conductive bumps/pillars to enable bonding of the integrated RF circuit structure300to a system board (e.g., a printed circuit board (PCB)).

Various aspects of the disclosure provide techniques for layer transfer and post transfer metallization to provide access to a backside of devices of an integrated radio frequency (RF) integrated structure. By contrast, access to devices, formed during a front-end-of line (FEOL) process, is conventionally provided during a middle-end-of-line (MEOL) processing that provides contacts between the gates and source/drain regions of the devices and back-end-of-line (BEOL) interconnect layers (e.g., M1, M2, etc.). Aspects of the present disclosure involve a post layer transfer metallization process for forming a dual side contacted capacitor (e.g., a MOS capacitor) for high quality (Q)-factor RF applications.

FIG. 4is a cross-sectional view of an integrated RF circuit structure400including a dual side contacted capacitor fabricated using a layer transfer process according to aspects of the present disclosure. Representatively, the integrated RF circuit structure400includes a passive device410(e.g., a MOS capacitor) having a semiconductor layer412(e.g., a silicon on insulator (SOI)) layer as a first plate and a gate layer408(e.g., a poly layer) as a second plate. In this arrangement, the first plate (e.g., the semiconductor layer412) and the second plate (e.g., the gate layer408) are separated by a capacitor dielectric layer426(e.g., a high-K dielectric) to form the passive device410. The semiconductor layer412, the gate layer408, and the capacitor dielectric layer426may all be formed on an isolation layer420. In SOI implementations, the isolation layer420is a buried oxide (BOX) layer, and the SOI layer may include shallow trench isolation (STI) regions422supported by the BOX layer (e.g., the isolation layer420).

As described herein, MOL/BEOL layers are referred to as front-side layers. By contrast, the layers supporting the isolation layer420may be referred to herein as backside layers. According to this nomenclature, the integrated RF circuit structure400also includes front-side metallization406including front-side metallization plugs418(e.g., front-side tungsten plugs) coupled together by a front-side metallization layer. The front-side metallization406may be coupled to the gate layer408through a front-side contact layer430(e.g., a front-side silicide layer). In this arrangement, the front-side metallization plugs418are coupled to the front-side contact layer430.

As shown inFIG. 4, a backside metallization414is coupled to the semiconductor layer412through a backside contact layer432(e.g., a backside silicide layer). The backside silicide reduces issues resulting from high resistivity. In this arrangement, the backside metallization414includes backside metallization plugs424(e.g., backside tungsten plugs) coupled together by a backside metallization layer (e.g., tungsten). The front-side metallization406and the backside metallization414may be arranged distal and directly opposite from each other. The front-side contact layer and the backside contact layer may be deposited on the gate layer408and the semiconductor layer412, respectively, through front-side silicidation and backside silicidation. In this arrangement, the backside metallization plugs424are coupled to the backside contact layer432and are joined together by a backside metallization material.

In related aspects of the present disclosure, the front-side metallization406may be arranged in a front-side dielectric layer404and proximate to the gate layer408of the passive device410. In addition, the backside metallization414may be a post-layer transfer metallization layer arranged in a backside dielectric layer416. In this arrangement, the backside dielectric layer416is adjacent to and possibly supports the isolation layer420. In addition, a handle substrate402may be coupled to the front-side dielectric layer404. An optional trap rich layer may be provided between the front-side dielectric layer404and the handle substrate402. The handle substrate402may be composed of a semiconductor material, such as silicon. In one aspect of the present disclosure, the handle substrate includes at least one other active/passive device, such as a switch transistor.

As shown inFIG. 4, aspects of the present disclosure describe a post layer-transfer metallization for forming a dual side contacted capacitor (e.g., a MOS capacitor), which is shown as the passive device410. The post transfer metallization process may form the backside metallization coupled to a first plate (e.g., the semiconductor layer412) of the dual side contacted capacitor. In addition, a front-side metallization406distal from the backside metallization414may be coupled to a second plate (e.g., the gate layer408) of the dual side contacted capacitor. In this arrangement, the dual side contacted capacitor may provide a desired capacitance density by using a single capacitor without having to perform conventional capacitor subdivision to achieve a desired capacitance density.

FIG. 5is a process flow diagram illustrating a method500of constructing an integrated radio frequency (RF) circuit structure according to an aspect of the present disclosure. In block502, a passive device (e.g., a MOS capacitor) is fabricated on a first surface of an isolation layer that is disposed on a sacrificial substrate. For example, as shown inFIG. 3A, a device310is fabricated on a buried oxide (BOX) layer. In the arrangement shown inFIG. 4, the passive device410(e.g., MOS capacitor) is arranged on a first surface of an isolation layer420. In one aspect of the present disclosure, a predetermined size diffusion region is formed within the semiconductor layer412to provide a first MOS capacitor plate. The size of the diffusion region within the semiconductor layer412is determined according to a desired capacitance density. The capacitor dielectric layer426is then deposited on the semiconductor layer412. Next, a gate layer408(e.g., a polysilicon layer or metal gate layer) is deposited on the capacitor dielectric layer426to complete formation of the MOS capacitor (e.g., the passive device410).

In block504, a front-side silicidation process is performed to deposit a front-side contact layer composed of silicide on a surface of a gate layer of the device. For example, as shown inFIG. 4, the front-side contact layer430is deposited on the gate layer408. In block506, a front-side metallization is fabricated in a front-side dielectric layer on the device. For example, as shown inFIG. 4, the front-side metallization406is fabricated in the front-side dielectric layer404and is coupled to the passive device410. The front-side metallization406may be coupled to the passive device410through the front-side contact layer430. The front-side metallization406may include the front-side metallization plugs418(e.g., front-side tungsten plugs) coupled to the front-side contact layer430and joined together by depositing a front-side metallization material in a patterned front-side dielectric layer. During fabrication of the front-side metallization406, the front-side dielectric layer404is patterned and etched to expose predetermined portions of the front-side contact layer430. Once exposed, a first front-side metallization material is deposited on the exposed, predetermined portions of the front-side contact layer430. Next, a second front-side metallization material is deposited on the front-side metallization plugs418.

Referring again toFIG. 5, in block508, a handle substrate is bonded to the front-side dielectric layer. For example, as shown inFIG. 4, the handle substrate402is bonded to the front-side dielectric layer404. In block510, the sacrificial substrate is removed. As shown inFIG. 3B, the layer-transfer process includes removal of the sacrificial substrate301. In block512, backside silicidation is performed to deposit a backside contact layer comprising silicide on a first side of a semiconductor layer of the device. For example, as shown inFIG. 4, the backside contact layer432is deposited on semiconductor layer412.

In block514, a backside metallization is fabricated on the isolation layer. As shown inFIG. 4, the passive device410is fabricated on the first surface of the isolation layer420, and the backside metallization414is fabricated on an opposing surface of the isolation layer420distal from the handle substrate402. In addition, the backside metallization414may be coupled to the semiconductor layer412through the backside contact layer432. During fabrication of the backside metallization414, the isolation layer420is patterned and etched to expose predetermined portions of the backside contact layer432. Once exposed, a first backside metallization material is deposited on the exposed, predetermined portions of the backside contact layer432to form the backside metallization plugs424(e.g., backside tungsten plugs). Next, a second backside metallization material is deposited on the backside metallization plugs424. The backside metallization414can be arranged distal and directly opposite to the front-side metallization406.

According to a further aspect of the present disclosure, integrated RF circuitry structures, including a dual side contacted capacitor, are described. The integrated RF circuit structure includes means for storing charge. The integrated RF circuit structure also includes an isolation layer and a backside dielectric layer. The charge storing means may be the semiconductor layer412and gate layer408, shown inFIG. 4. In another aspect, the aforementioned means may be any module or any apparatus configured to perform the functions recited by the aforementioned means.

Capacitors are passive elements used in integrated circuits for storing an electrical charge. Capacitors are often made using plates or structures that are conductive with an insulating material between the plates. The amount of storage, or capacitance, for a given capacitor is contingent upon the materials used to make the plates and the insulator, the area of the plates, and the spacing between the plates. The insulating material is often a dielectric material. Metal oxide semiconductor capacitors (MOS) capacitors are one example of a parallel plate capacitor, in which the insulator is a gate oxide, and the plates are made of a body and a gate of a device.

MOS capacitors may be used in RF applications to provide an increased capacitance density. Unfortunately, MOS capacitors used in advanced complementary MOS (CMOS) processing may occupy a large area. Moreover, the thinning of the body in SOI devices yields a substantial body resistance that has become a limiting factor in MOS capacitor performance. As a result, instead of one large area capacitor, many small area capacitors are used to provide a desired capacitance density. This results in inefficient use of chip space, increased chip complexity, and lower chip performance.

Aspects of the present disclosure describe using a post layer-transfer metallization to form a dual side contacted capacitor (e.g., a MOS capacitor). The post transfer metallization process may form a backside metallization coupled to a first plate of the capacitor. In addition, a front-side metallization distal from the backside metallization may be coupled to a second plate of the capacitor. In this arrangement, the dual side contacted capacitor may provide a desired capacitance density by using a single capacitor without having to perform conventional capacitor subdivision to achieve a desired capacitance density.

In this arrangement, a front-side metallization is coupled to a second plate of a capacitor and arranged distal from a backside metallization that is coupled to a first plate of the capacitor. In aspects of the present disclosure, the first plate is composed of a silicon on insulator (SOI) layer, and the second plate is composed of a gate layer. The backside metallization is coupled to the first plate of the capacitor through a backside contact layer. The front-side metallization is coupled to the second plate through a front-side contact layer. In this arrangement, the capacitor provides a desired capacitance density by using a single capacitor without having to perform conventional capacitor subdivision, which results in additional chip space, decreased chip complexity, and increased chip efficiency and performance.

FIG. 6is a block diagram showing an exemplary wireless communication system600in which an aspect of the disclosure may be advantageously employed. For purposes of illustration,FIG. 6shows three remote units620,630, and650and two base stations640. It will be recognized that wireless communication systems may have many more remote units and base stations. Remote units620,630, and650include IC devices625A,625C, and625B that include the disclosed dual side contacted capacitor. It will be recognized that other devices may also include the disclosed, dual side contacted capacitor, such as the base stations, switching devices, and network equipment.FIG. 6shows forward link signals680from the base station640to the remote units620,630, and650and reverse link signals690from the remote units620,630, and650to base stations640.

InFIG. 6, remote unit620is shown as a mobile telephone, remote unit630is shown as a portable computer, and remote unit650is shown as a fixed location remote unit in a wireless local loop system. For example, a remote units may be a mobile phone, a hand-held personal communication systems (PCS) unit, a portable data unit such as a personal digital assistant (PDA), a GPS enabled device, a navigation device, a set top box, a music player, a video player, an entertainment unit, a fixed location data unit such as a meter reading equipment, or other communications device that stores or retrieve data or computer instructions, or combinations thereof. AlthoughFIG. 6illustrates remote units according to the aspects of the disclosure, the disclosure is not limited to these exemplary illustrated units. Aspects of the disclosure may be suitably employed in many devices, which include the disclosed dual side contacted capacitor.

FIG. 7is a block diagram illustrating a design workstation used for circuit, layout, and logic design of a semiconductor component, such as the dual side contacted capacitor disclosed above. A design workstation700includes a hard disk701containing operating system software, support files, and design software such as Cadence or OrCAD. The design workstation700also includes a display702to facilitate design of a circuit710or a semiconductor component712such as a dual side contacted capacitor. A storage medium704is provided for tangibly storing the circuit design710or the semiconductor component712. The circuit design710or the semiconductor component712may be stored on the storage medium704in a file format such as GDSII or GERBER. The storage medium704may be a CD-ROM, DVD, hard disk, flash memory, or other appropriate device. Furthermore, the design workstation700includes a drive apparatus703for accepting input from or writing output to the storage medium704.

Data recorded on the storage medium704may specify logic circuit configurations, pattern data for photolithography masks, or mask pattern data for serial write tools such as electron beam lithography. The data may further include logic verification data such as timing diagrams or net circuits associated with logic simulations. Providing data on the storage medium704facilitates the design of the circuit design710or the semiconductor component712by decreasing the number of processes for designing semiconductor wafers.