Method of fabricating semiconductor device using epitaxial growth inhibiting layers

A semiconductor device according to one embodiment includes: a first transistor comprising a first gate electrode formed on a semiconductor substrate via a first gate insulating film, a first channel region formed in the substrate under the first film, and first epitaxial crystal layers formed on both sides of the first channel region in the substrate, the first layers comprising a first crystal; and a second transistor comprising a second gate electrode formed on the substrate via a second gate insulating film, a second channel region formed in the substrate under the second film, second epitaxial crystal layers formed on both sides of the second channel region in the substrate, and third epitaxial crystal layers formed on the second layers, the second layers comprising a second crystal, the third layers comprising the first crystal, the second transistor having a conductivity type different from that of the first transistor.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2008-247299, filed on Sep. 26, 2008, the entire contents of which are incorporated herein by reference.

BACKGROUND

As a fabrication technique of the semiconductor devices, a strained silicon technique, which strain is given a Si crystal in a channel region and operation speed of a transistor is improved, is known. This technique, for example, is disclosed in JP-A-2007-294780.

According to the technique disclosed in JP-A-2007-294780, etc., it is possible to generate a compressive strain in a channel region of a p-type transistor and then improve mobility of electric charges (positive holes) in the channel region by epitaxially growing a SiGe crystal, which has a lattice constant larger than that of a Si crystal, at a position that sandwiches the channel region of the p-type transistor.

In addition, it is possible to generate a tensile strain in the channel region of a n-type transistor and then improve mobility of electric charges (electrons) in the channel region by epitaxially growing a SiC crystal, which has a lattice constant smaller than that of a Si crystal, at a position that sandwiches the channel region of the n-type transistor.

However, according to a conventional method, when a semiconductor device mounting n-type MISFET and p-type MISFET together is fabricated, it is necessary to cover one transistor region with a cover film formed under a high temperature condition when a crystal is selectively epitaxially grown in the other transistor region.

Therefore, in the transistor region in which the crystal is grown first, a process to form the cover film on the epitaxial crystal is necessary, and thermal load on the epitaxial crystal increases at the time the cover film is formed.

As a result, a problem such as the deformation of the profile of the source/drain region by wide diffusion of conductivity type impurities in the epitaxial crystal may occur.

BRIEF SUMMARY

A semiconductor device according to one embodiment includes: a first transistor comprising a first gate electrode formed on a semiconductor substrate via a first gate insulating film, a first channel region formed in the semiconductor substrate under the first gate insulating film, and first epitaxial crystal layers formed on both sides of the first channel region in the semiconductor substrate, the first epitaxial crystal layers comprising a first crystal; and a second transistor comprising a second gate electrode formed on the semiconductor substrate via a second gate insulating film, a second channel region formed in the semiconductor substrate under the second gate insulating film, second epitaxial crystal layers formed on both sides of the second channel region in the semiconductor substrate, and third epitaxial crystal layers formed on the second epitaxial crystal layers, the second epitaxial crystal layers comprising a second crystal, the third epitaxial crystal layers comprising the first crystal, the second transistor having a conductivity type different from that of the first transistor.

A method of fabricating a semiconductor device according to another embodiment includes: forming first and second gate electrodes on first and second transistor regions in a semiconductor substrate via gate insulating films, respectively, the second transistor region having a conductivity type different from that of the first transistor region; forming first side walls and a cover film on side faces of the first gate electrode and on the second transistor region in the semiconductor substrate, respectively, the cover film comprising a material same as that of the first side walls; forming first trenches in the first transistor region by etching the semiconductor substrate using the cover film and the first side walls as masks; forming first epitaxial crystal layers by selectively epitaxially growing first Si system crystals in the first trenches; forming epitaxial growth inhibiting layers on the first epitaxial crystal layers; forming second trenches in the second transistor region by etching the semiconductor substrate using the first side walls, second side walls and the epitaxial growth inhibiting layers as masks after the cover film is shaped to the second side walls on side faces of the second gate electrode; and forming second epitaxial crystal layers by selectively epitaxially growing second Si system crystals in the second trenches.

A method of fabricating a semiconductor device according to another embodiment includes: forming first and second gate electrodes on first and second transistor regions in a semiconductor substrate via gate insulating films, respectively, the second transistor region having a conductivity type different from that of the first transistor region; forming first side walls and a cover film on side faces of the first gate electrode and on the second transistor region in the semiconductor substrate, respectively, the cover film comprising a material same as that of the first side walls; forming first trenches in the first transistor region by etching the semiconductor substrate using the cover film and the first side walls as masks; forming first epitaxial crystal layers by selectively epitaxially growing first Si system crystals in insides and upper regions of the first trenches; lowing a height of the upper surfaces of the first epitaxial crystal layers and forming second trenches in the second transistor region by etching the first epitaxial crystal layers the semiconductor substrate using the first side walls and second side walls as masks after the cover film is shaped to the second side walls on side faces of the second gate electrode; and forming second epitaxial crystal layers and third epitaxial crystal layers by selectively epitaxially growing second Si system crystals in the second trenches and on the first epitaxial crystal layers, respectively.

DETAILED DESCRIPTION

First Embodiment

FIG. 1is a cross section showing a semiconductor device1according to the first embodiment. The semiconductor device1has a n-type transistor10and a p-type transistor20on a semiconductor substrate2, and the n-type transistor10and the p-type transistor20are electrically isolated by element isolation region3.

The semiconductor substrate2is made of a Si system crystal such as a Si crystal, etc.

The element isolation region3is made of an insulating material such as SiO2, etc., and has a STI (Shallow Trench Isolation) structure.

The n-type transistor10includes a gate electrode12formed on the semiconductor substrate2via a gate insulating film11, gate sidewalls16formed on side faces of the gate electrode12, a silicide layer17formed on the gate electrode12, a channel region15formed in a region in the semiconductor substrate2below the gate insulating film11, extension regions13of source/drain regions formed on both sides of the channel region15in the semiconductor substrate2, epitaxial crystal layers14formed on both sides of the extension regions13, and silicide layers18formed on the epitaxial crystal layers14. Note that, although it is not illustrated, a p-type well may be formed in a region in the semiconductor substrate2under the n-type transistor10.

The p-type transistor20includes a gate electrode22formed on the semiconductor substrate2via a gate insulating film21, gate sidewalls26formed on side faces of the gate electrode22, a silicide layer27formed on the gate electrode22, a channel region25formed in a region in the semiconductor substrate2below the gate insulating film21, extension regions23of source/drain regions formed on both sides of the channel region25in the semiconductor substrate2, epitaxial crystal layers24formed on both sides of the extension regions23, and silicide layers28formed on the epitaxial crystal layers24. Note that, although it is not illustrated, a n-type well may be formed in a region in the semiconductor substrate2under the p-type transistor20.

The gate insulating films11and21are made of, e.g., an insulating material such as SiO2, SiN or SiON, etc., or a high-k material such as an Hf-based compound (HfSiON, HfSiO or HfO, etc.), a Zr-based compound (ZrSiON, ZrSiO or ZrO, etc.) or a Y-based compound (Y2O3, etc.).

The gate electrodes12and22are made of, e.g., Si-based polycrystalline such as polycrystalline silicon, etc., containing conductivity type impurity. Here, an n-type impurity such as As, P is included in the gate electrode12, and a P-type impurity such as B, BF2 is included in gate electrode22. In addition, the gate electrodes12and22may be metal gate electrodes made of W, Ta, Ti, Hf, Zr, Ru, Pt, Ir, Mo or Al, etc., or a compound thereof, etc. Furthermore, the gate electrodes12and22may have a laminated structure in which Si-based polycrystalline gate electrode is formed on the metal gate electrode.

The silicide layers17and27are made of, for example, a compound of a metal such as Ni, Pt, Co, Er, Y, Yb, Ti, Pd, NiPt, or CoNi, etc., with Si. Note that, although the silicide layers17and27are formed by siliciding upper portions of the gate electrodes12and22, fully silicided gate electrodes may be formed by siliciding the whole gate electrodes12and22. In addition, the silicide layers17and27are not formed when the upper portions of the gate electrodes12and22are metal gate electrodes.

The gate sidewalls16and26may have a single layer structure comprising, e.g., SiN, or a structure of two layers comprising, e.g., SiN and SiO2, furthermore, may have a structure of three or more layers.

The extension layers13are formed by implanting a n-type impurity such as As, P into a region of n-type transistor10in the semiconductor substrate2. In addition, the extension layers23are formed by implanting a p-type impurity such as B, BF2 into a region of the p-type transistor20in the semiconductor substrate2. Furthermore, silicide layers may be formed in upper portions of the extension layers13,23.

The epitaxial crystal layers14are made of a Si system crystal formed by epitaxial crystal growth technique. Specifically, the Si system crystal constituting the epitaxial crystal layers14is a crystal same as that constituting the semiconductor substrate2, or a Si system crystal having a lattice constant smaller than that of the crystal constituting the semiconductor substrate2. For example, in case that the semiconductor substrate2is made of a Si crystal, a Si crystal or a SiC crystal having a lattice constant smaller than that of a Si crystal may be used for the epitaxial crystal layers14.

Here, in case that the epitaxial crystal layers14are made of a crystal has a lattice constant smaller than that of the crystal constituting the semiconductor substrate2, it is possible that the epitaxial crystal layers14generate a tensile strain in the channel region15, thereby improving mobility of electrons in the channel region15.

Note that, when a SiC crystal is used for the epitaxial crystal layers14, it is preferable that a C concentration in the SiC crystal is 1-3 At % (atomic percentage). When a C concentration in the SiC crystal is less than 1 At %, a strain generated in the channel region15is insufficient. In addition, when a C concentration in the SiC crystal is more than 3 At %, crystal defects may be generated in a substrate, etc., which may cause a leak current.

The epitaxial crystal layers24are made of a Si system crystal formed by epitaxial crystal growth technique. Specifically, the Si system crystal constituting the epitaxial crystal layers24is a crystal same as that constituting the semiconductor substrate2, or a Si system crystal having a lattice constant larger than that of the crystal constituting the semiconductor substrate2. For example, in case that the semiconductor substrate2is made of a Si crystal, a Si crystal or a SiGe crystal having a lattice constant larger than that of a Si crystal may be used for the epitaxial crystal layers24.

Here, in case that the epitaxial crystal layers24are made of a crystal has a lattice constant larger than that of the crystal constituting the semiconductor substrate2, it is possible that the epitaxial crystal layers24generate a compressive strain in the channel region25, thereby improving mobility of positive holes in the channel region25.

Note that, when a SiGe crystal is used for the epitaxial crystal layers24, it is preferable that a Ge concentration in the SiGe crystal is 10-30 At %. When a Ge concentration in the SiGe crystal is less than 10 At %, a strain generated in the channel region25is insufficient. In addition, when that is more than 30 At %, crystal defects may be generated in a substrate, etc., which may cause a leak current.

An example of a method of fabricating a semiconductor device1according to this embodiment will be described hereinafter.

FIGS. 2A to 2Hare cross sectional views showing processes for fabricating the semiconductor device1according to the first embodiment.

Firstly, as shown inFIG. 2A, the gate insulating film11, the gate electrode12, a cap film101and the extension regions13are formed in a n-type transistor region100, and the gate insulating film21, the gate electrode22, a cap film201and the extension regions23are formed in a p-type transistor region200.

Here, the n-type transistor region100and the p-type transistor region200are a region in which the n-type transistor10is formed and a region in which the p-type transistor20is formed, respectively. In addition, the n-type transistor region100and the p-type transistor region200are isolated by element isolation region3each other.

The element isolation region3is formed by, e.g., following process. Firstly, a trench is formed in the semiconductor substrate2by photolithography method and RIE (Reactive Ion Etching) method. Next, a SiO2film is deposited in the trench by CVD (Chemical Vapor Deposition) method, and is substantially planarized by CMP (Chemical Mechanical Polishing) method, thereby processing into the element isolation region3.

The gate insulating films11and21, the gate electrodes12and22, and the cap films101and201are formed by, e.g., following process. Firstly, an oxide film is formed by oxidizing a surface of the semiconductor substrate2. Next, by CVD method, etc., a Si polycrystal film and a SiN film are laminated on the oxide film. Next, by photolithography method and RIE method, the SiN film, the Si polycrystal film and the oxide film are patterned and shaped into the cap films101and201, the gate electrodes12and22, and gate insulating films11and21, respectively.

Note that, though the cap films101and201have a function to prevent crystals from growing up on upper surfaces of the gate electrodes12and22in a posterior process, the cap films101and201may not be formed. In addition, the cap films101and201are not formed when the gate electrodes12and22are metal gate electrodes.

The extension layers13are formed by implanting an n-type impurity into the n-type transistor region100in the semiconductor substrate2using the cap film101and the gate electrode12as a mask, by an ion implantation procedure, etc. In addition, the extension layers23are formed by implanting a p-type impurity into the p-type transistor region200in the semiconductor substrate2using the cap films201and the gate electrode22as masks, by ion implantation procedure, etc.

Next, as shown inFIG. 2B, a cover film102is formed in the n-type transistor region100, and the gate sidewalls26are formed on side faces of the cap film201and the gate electrode22in the p-type transistor region200.

The cover film102and the gate sidewalls26are formed by, e.g., following process. Firstly, by CVD method, a SiN film which is material film of the cover film102and the gate sidewall26is formed on the n-type transistor region100and the p-type transistor region200in the semiconductor substrate2under a temperature condition of 700° C. Next, The SiN film is removed so as to leave portions thereof located on side faces of the cap film201and the gate electrode22by selectively applying anisotropic etching such as RIE to the SiN film on the n-type transistor region100, thereby forming the gate sidewalls26. The portions, which is left in p-type transistor region200without being etched, of the SiN film become the cover film102.

Next, as shown inFIG. 2C, the semiconductor substrate2is etched using the cover film102and the gate sidewalls26as masks, thereby forming trenches203in the p-type transistor region200.

The trenches203are formed using RIE method or wet etching method, etc. The etching does not reach the n-type transistor region100in the semiconductor substrate2since that is covered by the cover film102.

Next, as shown inFIG. 2D, the epitaxial crystal layers24are formed in the trenches203by epitaxially growing Si system crystals such as SiGe crystals, etc., using a surface of the semiconductor substrate2in the p-type transistor region200, i.e., inner surfaces of the trenches203as a base.

Here, it is preferable to implant p-type impurities into the Si system crystals at the same time the Si system crystals are grown (which is referred to as in-situ doping). In case that the in-situ doping method is used for implantation of p-type impurities, unlike in case that ion implantation procedure is used, thermal load on the epitaxial crystal layers24can be reduced since it is not necessary to activate the P-type impurities which is implanted by high temperature heat treatment such as spikes RTA (Rapid Thermal Annealing), etc.

In case that a SiGe crystal is used for the epitaxial crystal layers24, the SiGe crystal is epitaxially grown by, for example, SEG (Selective Epitaxial Growth) process under a temperature condition of 700-900° C. Here, the SEG process is a process in which a gas, which is for nonselectively growing a crystal on a Si crystal layer or an insulation film, and an etching gas, which is for removing the crystal on the insulation film having low-growth rate, are used at the same time. HCl gas, etc., is used as the etching gas.

In the SEG process, on a surface of the semiconductor substrate2, quantity that the crystals are grown is larger than quantity that the crystals are removed by the etching since growth rate of crystals is high. As a result, the crystals are grown on the surface of the semiconductor substrate2with time. On the other hand, on surfaces of the cover film102, the element isolation region3, the gate sidewalls26and the cap film201, quantity that the crystals are grown is small since only crystalline nucleus are dispersively grown. Therefore, quantity that the crystals are grown is smaller than quantity that the crystals are removed by the etching. As a result, no crystal is grown on these portions. For this reason, it is possible to selectively form the epitaxial crystal layers24in the trenches203.

Next, as shown inFIG. 2E, epitaxial growth inhibiting layers202are formed on the epitaxial crystal layers24.

Here, the epitaxial growth inhibiting layers202are made of a Si system crystal including crystal defects or a Si system amorphous material. Crystals are hardly epitaxially grown on the epitaxial growth inhibiting layers202.

By increasing concentration of Ge or the conductivity type impurity such as B, crystal defects are generated in the Si system crystal or the Si system crystal is transformed into amorphous material. In other words, as the process shown inFIG. 2D, the epitaxial crystal24is formed by growing the Si system crystals in a state in which density of Ge or the conductivity type impurity is kept normal until the trenches203are filled by the Si system crystals. After that, the Si system crystals are continuously grown in a state in which the density of Ge or the conductivity type impurity is increased, thereby forming the epitaxial growth inhibiting layers202.

Furthermore, by implanting relatively heavy elements such as Ge into the Si system crystals using ion implantation procedure, crystal defects are generated in the Si system crystal or the Si system crystal is transformed into amorphous material. Therefore, the epitaxial growth restraint layers202may be formed using the following method. Firstly, as the process shown inFIG. 2D, the epitaxial crystal24is formed by growing the Si system crystals until the trenches203are filled by the Si system crystals. Next, the Si system crystals are continuously grown to upper regions of the trenches203without changing a growth condition. After that, the epitaxial growth inhibiting layers202is formed by implanting element such as Ge into portions of the Si system crystals in upper regions of the trenches203(in other words, the portions are upper portions on lower portions which become the epitaxial crystal24of the Si system crystals).

Next, as shown inFIG. 2F, the cover film102in the n-type transistor region100is shaped to the gate sidewalls16.

The cover film102in the n-type transistor region100is removed so as to leave portions thereof located on side faces of the cap film201and the gate electrode22by selectively applying anisotropic etching such as RIE to the cover film102, thereby forming the gate sidewalls16.

Next, as shown inFIG. 2G, the semiconductor substrate2is etched using the gate sidewalls16and the epitaxial growth inhibiting layers202as masks, thereby forming trenches103in the n-type transistor region100.

The trenches103are formed using RIE method or wet etching method, etc. The etching does not reach the epitaxial crystal layers24since that is covered by the epitaxial growth inhibiting layers202.

Next, as shown inFIG. 2H, the epitaxial crystal layers14are formed in the trenches103by epitaxially growing Si system crystals such as SiC crystals, etc., using a surface of the semiconductor substrate2in the n-type transistor region100, i.e., inner surfaces of the trenches103as a base.

Here, it is preferable to implant n-type impurities into the Si system crystals at the same time the Si system crystals are grown (which is referred to as in-situ doping). In case that the in-situ doping method is used for implantation of n-type impurities, unlike in case that ion implantation procedure is used, thermal load on the epitaxial crystal layers14can be reduced since it is not necessary to activate then-type impurities which is implanted by high temperature heat treatment such as spikes RTA (Rapid Thermal Annealing), etc.

In case that a SiC crystal is used for the epitaxial crystal layers14, the SiC crystal is epitaxially grown by, for example, SEG process under a temperature condition of about 500° C. Here, on surfaces of the epitaxial growth inhibiting layers202, the element isolation region3, the gate sidewalls16and26, and the cap film101and201, quantity that the crystals are grown is small. Therefore, quantity that the crystals are grown is smaller than quantity that the crystals are removed by the etching. As a result, no crystal is grown on these portions. For this reason, it is possible to selectively form the epitaxial crystal layers14in the trenches103.

Next, as shown inFIG. 2I, the epitaxial growth inhibiting layers202are removed by, for example, wet etching method using HF/ozone water, etc., as an etchant.

Next, as shown inFIG. 2K, the silicide layers17and27are formed on the gate electrodes12and22, and the silicide layers18and28are formed on the epitaxial crystal layers14and24.

The silicide layers17,27,18and28are formed by, e.g., following process. Firstly, a metal film such as a Ni film is formed on the n-type transistor region100and the p-type transistor region200in the semiconductor substrate2by PVD method, etc. Next, the silicide layers17,27,18and28are formed by a silicidation reaction between upper surfaces of the gate electrodes12and22and the metal film and a silicidation reaction between upper surfaces of the epitaxial crystal layers14and24and the metal film generated by heat treatment. Note that, the unreacted metal film is removed by wet etching method, etc.

Effect of the First Embodiment

According to the first embodiment, the thermal load on the epitaxial crystal layers14and24can be reduced since a process in which a cover film formed under a high temperature condition is formed on the epitaxial crystal layers14and24is not included. Therefore, it is possible to avoid a problem such as the deformation of the profile of the source/drain region by wide diffusion of conductivity type impurities in the epitaxial crystal layers14and24.

Specifically, a process in which a cover film formed on the p-type transistor region200in the semiconductor substrate2can be omitted by using the epitaxial growth inhibiting layers202as etching masks when the trenches103are formed. As a result, the thermal load on the epitaxial crystal layers24can be reduced. In addition, the thermal load on the epitaxial crystal layers14also can be reduced since that is formed after the process in which the cover film102is formed.

Second Embodiment

The second embodiment is different from the first embodiment in that the epitaxial crystal layers24are formed higher and used as masks when the trenches103are formed, instead of forming the epitaxial growth inhibiting layers202. Note that, the explanation will be omitted or simplified for the same points as the first embodiment.

FIG. 3is a cross section showing a semiconductor device1according to the second embodiment. The semiconductor device1has a n-type transistor10and a p-type transistor20on a semiconductor substrate2, and the n-type transistor10and the p-type transistor20are electrically isolated by element isolation region3.

The n-type transistor10includes a gate electrode12formed on the semiconductor substrate2via a gate insulating film11, gate sidewalls16formed on side faces of the gate electrode12, a silicide layer17formed on the gate electrode12, a channel region15formed in a region in the semiconductor substrate2below the gate insulating film11, extension regions13of source/drain regions formed on both sides of the channel region15in the semiconductor substrate2, epitaxial crystal layers14formed on both sides of the extension regions13, and silicide layers18formed on the epitaxial crystal layers14. Note that, although it is not illustrated, a p-type well may be formed in a region in the semiconductor substrate2under the n-type transistor10.

The p-type transistor20includes a gate electrode22formed on the semiconductor substrate2via a gate insulating film21, gate sidewalls26formed on side faces of the gate electrode22, a silicide layer27formed on the gate electrode22, a channel region25formed in a region in the semiconductor substrate2below the gate insulating film21, extension regions23of source/drain regions formed on both sides of the channel region25in the semiconductor substrate2, epitaxial crystal layers24formed on both sides of the extension regions23, epitaxial crystal layers29formed on the epitaxial crystal layers24, and silicide layers30formed on the epitaxial crystal layers29. Note that, although it is not illustrated, a n-type well may be formed in a region in the semiconductor substrate2under the p-type transistor20.

The epitaxial crystal layers29are made of a Si system crystal, which is same as that constituting the epitaxial crystal layers14, formed by epitaxial crystal growth technique. Specifically, the Si system crystal constituting the epitaxial crystal layers14and29is a crystal same as that constituting the semiconductor substrate2, or a Si system crystal having a lattice constant smaller than that of the crystal constituting the semiconductor substrate2. For example, in case that the semiconductor substrate2is made of a Si crystal, a Si crystal or a SiC crystal having a lattice constant smaller than that of a Si crystal may be used for the epitaxial crystal layers14and29.

Note that, most of strain in the channel region25is generated by the epitaxial crystal layers24because of positional relationship between them. Therefore, the strain in the channel region25is little influenced by the epitaxial crystal layers29.

An example of a method of fabricating a semiconductor device1according to this embodiment will be described hereinafter.

FIGS. 4A to 4Fare cross sectional views showing processes for fabricating the semiconductor device1according to the second embodiment.

Firstly, the processes until the process, shown inFIG. 2C, for forming the trenches203in the p-type transistor region200are carried out in the same way as the first embodiment.

Next, as shown inFIG. 4A, the epitaxial crystal layers24are formed in the insides and upper regions of the trenches203by epitaxially growing Si system crystals such as SiGe crystals, etc., using a surface of the semiconductor substrate2in the p-type transistor region200(i.e., inner surfaces of the trenches203) as a base.

Although a formation method of the epitaxial crystal layers24is same as that in the first embodiment, the epitaxial crystal layers24is formed so that a height thereof is higher than that in the first embodiment.

Next, as shown inFIG. 4B, the cover film102in the n-type transistor region100is shaped to the gate sidewalls16.

Next, as shown inFIG. 4C, the semiconductor substrate2is etched using the gate sidewalls16and portions of the epitaxial crystal layers24which are mainly formed in the upper region of the trenches203as masks, thereby forming trenches103in the n-type transistor region100.

In this process, a surface of the semiconductor substrate2in the n-type transistor region100and the epitaxial crystal layers24are etched. Therefore, the height of the upper surfaces of the epitaxial crystal layers24is lowered, and the epitaxial crystal layers24reach size fitting into the insides of the trenches203.

Next, as shown inFIG. 4D, by the SEG process, etc., the epitaxial crystal layers14and29are formed in the trenches103and on the epitaxial crystal layers24by epitaxially growing Si system crystals such as SiC crystals, etc., using the surface of the semiconductor substrate2in the n-type transistor region100(i.e., inner surfaces of the trenches103) and upper surfaces of the epitaxial crystal layers24as a base.

Here, if an n-type impurity is implanted into a Si system crystal by in-situ doping method, performance of the p-type transistor20is decreased since the n-type impurity is also implanted into the epitaxial crystal layers29. Therefore, it is preferable to selectively implant the n-type impurity into the n-type transistor region100for implanting the n-type impurity into the epitaxial crystal layers14.

Next, as shown inFIG. 4F, the silicide layers17and27are formed on the gate electrodes12and22, and the silicide layers18and30are formed on the epitaxial crystal layers14and29.

The silicide layers17,27,18and30are formed by, e.g., following process. Firstly, a metal film such as a Ni film is formed on the n-type transistor region100and the p-type transistor region200in the semiconductor substrate2by PVD method, etc. Next, the silicide layers17,27,18and30are formed by a silicidation reaction between upper surfaces of the gate electrodes12and22and the metal film and a silicidation reaction between upper surfaces of the epitaxial crystal layers14and29and the metal film generated by heat treatment. Note that, the unreacted metal film is removed by wet etching method, etc.

Note that, a silicide of a metal such as Ni with SiGe is thermodynamically unstable. Therefore, when a SiGe crystal is used for the epitaxial crystal layers24, generation of a leak current caused by abnormal growth of a silicide, etc., can be suppressed in case that the silicide is formed on the epitaxial crystal layers29as compared with in case that the silicide is formed on the epitaxial crystal layers24similarly to the first embodiment.

Effect of the Second Embodiment

According to the second embodiment, the thermal load on the epitaxial crystal layers14,24and29can be reduced since a process in which a cover film formed under a high temperature condition is formed on the epitaxial crystal layers14,24and29is not included, similarly to the first embodiment. Therefore, it is possible to avoid a problem such as the deformation of the profile of the source/drain region by wide diffusion of conductivity type impurities in the epitaxial crystal layers14,24and29.

Specifically, a process in which a cover film formed on the p-type transistor region200in the semiconductor substrate2can be omitted by using the portions of the epitaxial crystal layers24which are mainly formed in the upper region of the trenches203as etching masks when the trenches103are formed. As a result, the thermal load on the epitaxial crystal layers24can be reduced.

Other Embodiments

It should be noted that embodiments are not intended to be limited to the above-mentioned first to third embodiments, and the various kinds of changes thereof can be implemented by those skilled in the art without departing from the gist of the invention.

In addition, the constituent elements of the above-mentioned embodiments can be arbitrarily combined with each other without departing from the gist of the invention.