Solder interconnect integrity monitor

An apparatus and method for non-destructive solder interconnect integrity monitoring that can detect existing fracture damage, identify new or incipient fractures, and be implemented across multiple component configurations. Said components can be implemented to detect, on a continuous basis, solder interconnect fractures as they occur during actual end-use, throughout the lifecycle of monitored components, rather than relying on a one-time electrical check prior to shipment.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates in general to the field of packaging integrated circuits, and more specifically, to detecting solder interconnect fractures as they occur during the lifecycle of monitored components.

2. Description of the Related Art

Integrated circuit technology continues to evolve, resulting in chips with increased clock speeds, higher power consumption, and larger numbers of inputs and outputs. Corresponding advances in integrated circuit fabrication technology have resulted in higher levels of integration, increased density, and growth in die sizes, any or all of which can pose additional challenges when packaging and mounting semiconductor devices.

A semiconductor device is an integrated circuit in packaged form, usually mounted to a printed wire board (PWB) or other type of carrier, operating as a processing unit, memory, controller or any other electronic device. Semiconductor package and packaging techniques are designed to protect the integrated circuit from mechanical and environmental damage, assist thermal dissipation during operation, and most relevant to the present invention, provide electrical connection between the integrated circuit and external electrical devices.

A fundamental problem in semiconductor package mounting is brittle solder joint fractures. Unlike fatigue failures, these fractures typically occur during a monotonic (non-reversing) stress event such as drop or high strain rate flexure. Monotonic stress events can occur during board assembly/test, shipment/handling operations, and/or actual end-use. For example, in-circuit test (ICT) and certain assembly operations, such as manual connector insertion and printed wire board (PWB) edge-guide snap-off, are often associated with high strain and strain-rate. Such operations can also result in high PWB flexural loading, depending upon system configuration, assembly location, and other factors. Because the method and apparatus of the present invention can be used with a wide variety of solder-based electrical connections and associated geometries, the terms “solder joint” and “solder interconnect” will be used interchangeably.

Although they occur infrequently, brittle solder interconnect fractures are nonetheless a major concern given the possibility of undetected failures. Some brittle solder joint fractures may be detected prior to shipment, while others may go undetected due to either incomplete fracture of the solder joint, or ohmic contact between fractured surfaces during electrical monitoring. The presence of undetected, yet damaged, solder joints compromises the potential functionality and reliability of the electronic device during end-use operation.

While brittle fractures have been documented for ball grid array (BGA) packages using electrolytic nickel/gold (Ni/Au)-plated and solder-over-copper (Cu) substrates, the majority of brittle fractures involve packages using electro-less nickel, immersion gold (ENIG) plated BGA substrates. Brittle fracture for BGA packages using ENIG plating occurs between the phosphorous (P) rich Ni surface and the nickel-tin/tin-copper/nickel (NiSn/SnCu/Ni) intermetallic layer. Approaches for the prevention of BGA brittle fracture can include improvement in solder joint fracture resistance, as well as reduction of applied strain.

Solder joint fracture resistance can also be dependent upon the characteristics of the solder used in assembly. For example, the strength characteristics of SnPb (tin-lead) and Pb-free solder alloys are highly strain-rate dependent, but Pb-free solder alloys, such as tin-gold-copper (SnAgCu), may prove more sensitive to brittle fracture than eutectic SnPb solder. Although solder strength typically improves with increased strain-rate, the higher plastic modulus at elevated strain levels can result in increased interfacial strain at the pad/solder region under flexural or impact loading conditions.

Currently, various destructive tests including drop, shock, vibration, twist, and high-speed monotonic bend, are used to correlate fracture resistance to force, deflection, and/or acceleration. When applied at the component and board level, these tests can be useful for assessing the integrity of solder joints resulting from different combinations of components and/or assembly processes. Other destructive solder joint integrity test methods approximate actual conditions associated with solder joint brittle fracture and can yield more accurate assessments of brittle fracture resistance. For example, solder interconnect brittle fracture resistance during drop conditions can be characterized using drop testing of production and/or test circuit board assemblies. A destructive industry test method used to assess BGA solder joint integrity, solder ball shear/pull testing, does not consistently detect microstructural weaknesses at the pad/solder interfaces where brittle failures occur. Furthermore, solder ball shear and/or pull testing is not applicable to BGA components assembled on a PWB.

While these destructive test methods provide useful tools for component manufacturers to optimize the brittle fracture resistance of their product, they are impractical for in-line solder joint integrity monitoring and/or end-use, either of which require a non-destructive testing approach. Furthermore, the results of these destructive tests are only applicable to the specific component and board configuration under test.

What is needed is a non-destructive solder joint integrity monitoring system that can detect existing damage, identify new or incipient fractures, and is capable of being implemented across multiple component configurations.

SUMMARY OF THE INVENTION

In accordance with the present invention, the method and apparatus for monitoring solder interconnect package connections is set forth, which provides a non-destructive method of detecting brittle solder joint fractures, as they occur, throughout the lifecycle of the monitored components. Skilled practitioners of the art are aware that brittle solder joint fractures typically occur at a device's outermost solder joints, which correspond to areas of maximum strain.

In one embodiment of the invention, corner solder joints of a device are implemented with printed wiring board (PWB) circuitry to provide a continuous, electrical, solder joint integrity monitor, allowing both detection of existing damage, as well as indicating new or incipient fractures. In different embodiments of the invention, the method of electrical monitoring can be implemented to perform predetermined continuity tests ranging from simple discontinuity to glitch detection. Any predetermined number of outer solder joints in the package can be used to monitor the integrity of the remaining solder joints. For example, one or more corner solder joints may be implemented as monitoring pins, assigned a voltage level, and monitored during device operation through associated PWB circuitry. In different embodiments of the invention, the number of solder joints implemented as monitoring pins can range from a single solder joint per device, to a plurality of solder joints.

In one embodiment of the invention, predetermined solder joints serving as monitoring pins may be constructed to fail at different loading conditions within a single device, allowing quantifiable measurement of the applied damaging load, while also providing notification of damaging events. For example, in different embodiments of the invention, the configuration of predetermined solder joints can range from an exact duplicate of surrounding functional package balls/pins/leads, to a highly modified geometry designed to provide more sensitivity or varied response levels. In other embodiments of the invention, these predetermined solder joints can be modified by altering their respective construction, (e.g., reducing the size of package pads and/or PWB lands at monitoring pin locations) so they fail sooner than the remaining functional solder joints.

Those skilled in the art will recognize that different embodiments of the invention may comprise multiple monitoring pin implementations. For example, in different embodiments of the invention, predetermined monitoring pins may be comprised of solder interconnects comprising solder of predetermined, but differing, compositions (e.g., various SnPb and Pb-free alloys), each of which will typically fracture at different strain rate levels. Similarly, it will be understood by those of skill in the art that monitoring pins may be comprised of solder attached leadframe, solder coated land pad, solder coated metallic or organic sphere, or other configurations. As will be apparent to those skilled in the art, the method and apparatus of the invention is not limited to grid array style semiconductor devices, but can also be implemented for peripheral leadframe, and other semiconductor package geometries.

DETAILED DESCRIPTION

The method and apparatus of the present invention provides significant improvements in the electronic devices such as those used in a computer system100shown inFIG. 1A. The computer system100includes a main system board102that comprises a plurality of integrated circuits, such as a processor104and integrated circuits used for various other subsystems106understood by those skilled in the art. Data is transferred between the various system components via various data buses illustrated generally by bus103. A hard drive110is controlled by a hard drive/disk interface108that is operably connected to the hard drive/disk110. Likewise, data transfer between the system components and other storage devices114is controlled by storage device interface112that is operably connected to the various other storage devices114, such as CD ROM drives, floppy drives, etc. An input/output (I/O) interface118controls the transfer of data between the various system components and a plurality of input/output (I/O) devices, such as a display122, a keyboard124, a mouse126.

For purposes of this disclosure, the present invention is described in the context of computer system100illustrated inFIG. 1A. However, the present invention can be used to improve electrical connections on any type of electronic device. Hence, the present invention is not limited to the computer system100illustrated inFIG. 1A.

FIG. 1Bis a generalized illustration of a printed circuit board such as system board (or motherboard)102discussed above in connection withFIG. 1A. Circuit boards, such as the circuit board102shown inFIG. 1B, generally have numerous integrated circuits130that are coupled to connectors on the board with solder connections, such as solder ball joints.

FIG. 2is a generalized illustration of a semiconductor device200mounted in a package202, comprising a ball grid array (BGA) of solder ball joints206, which provides physical and electrical connectivity between the pads204of package202, and the lands208of circuit board210.

FIG. 3is a generalized illustration of a BGA brittle solder joint fracture. More specifically, semiconductor package202is comprised of copper (Cu) pad204, which comprises a nickel-phosphorus (Ni—P) plated surface318, which comprises a phosphorus-rich (P+) layer316. Solder ball206is bonded to CU land208of circuit board210through copper-tin (CuSn) intermetallic layer320. As illustrated, BGA brittle solder joint fractures312typically occur between phosphorus-rich (P+) layer316and nickel-tin (NiSn) and/or tin-copper-nickel (SnCuNi) layer314of solder ball206. In some cases, BGA brittle solder joint fractures can occur between CuSn intermetallic layer320and Cu land208of circuit board210. As will be understood by those of skill in the art, different compositions of solder may also lead to brittle solder joint failure under certain mechanical stresses.

FIG. 4ashows one method of an embodiment of the invention where a single, predetermined corner solder joint402of a semiconductor package BGA400is used as a monitoring pin to detect brittle solder joint fractures.

FIG. 4bshows one method of an embodiment of the invention where a predetermined number of solder joints402in one corner of a semiconductor package BGA400are used as monitoring pins to detect brittle solder joint fractures.

FIG. 4cshows one method of an embodiment of the invention where a single, predetermined solder joint402in each corner of a semiconductor package BGA400is used as a monitoring pin to detect brittle solder joint fractures.

FIG. 4dshows one method of an embodiment of the invention where a predetermined number of solder joints402are used in each corner of a semiconductor package BGA400as monitoring pins to detect brittle solder joint fractures.

FIG. 4eis an illustration of a lead frame connector404comprising a plurality of peripheral solder interconnects406. Individual solder interconnects406can be monitored using the techniques described herein to detect brittle solder interconnect fractures. For example, solder interconnects406aon the corners of the lead frame connector can be monitored. Alternatively, various other combinations of the solder interconnects406can be monitored, as discussed hereinabove in connection withFIGS. 4a-d.

FIG. 5ais a generalized illustration of one method of an embodiment of the invention where a semiconductor package202, which comprises a ball grid array (BGA) of solder ball joints206, which provide physical and electrical connectivity between the pads204of package202and the lands208of circuit board210. Semiconductor package202comprises electrical trace504, which couples to package pad204, providing electrical circuit continuity through solder ball joint206, and circuit board pad208, to a single monitoring pin502. In this same embodiment, loss of circuit continuity through monitoring pin502can indicate a brittle fracture of solder joint206coupled to monitoring pin502, and the possibility of other brittle solder joint fractures.

FIG. 5bis a generalized illustration of one method of an embodiment of the invention where a semiconductor package202, which comprises a ball grid array (BGA) of solder ball joints206, which provide physical and electrical connectivity between the pads204of package202and the lands208of circuit board210. Semiconductor package202comprises electrical trace504, which couples to a plurality of package pads204, providing electrical circuit continuity through a plurality of solder ball joints206, and circuit board lands208, to a plurality of monitoring pins502. In this same embodiment, loss of circuit continuity through monitoring pins502can indicate a brittle fracture of one or more solder joints.

FIG. 5cis a generalized illustration of one method of an embodiment of the invention where a semiconductor package202, which comprises a ball grid array (BGA) of solder ball joints206, which provide physical and electrical connectivity between the pads204of package202and the lands208of circuit board210. Semiconductor package202comprises electrical trace504, which couples to a plurality of package pads204, providing electrical circuit continuity through a plurality of solder ball joints206, and circuit board lands208, to a plurality of monitoring pins502.

In this method of the embodiment of the invention, the configuration of predetermined solder joints506can range from an exact duplicate of surrounding functional solder joints506, to a highly modified geometry designed to provide more sensitivity or varied response levels. In this embodiment of the invention, these predetermined solder joints506can be modified by altering their respective construction, (e.g., reducing the size of package pads504and/or PWB lands508at monitoring pin locations502) so they fail sooner than the remaining functional solder joints. In this same embodiment, loss of circuit continuity through monitoring pins502can indicate a brittle fracture of one or more solder joints. Those with skill in the art will recognize that an early brittle fracture detection system can be implemented by coupling solder joints that fracture at lower strain levels to monitoring pins.

FIG. 5dis a generalized illustration of one method of an embodiment of the invention where a semiconductor package202, which comprises a ball grid array (BGA) of solder ball joints206, which provide physical and electrical connectivity between the pads204of package202and the lands208of circuit board210. Semiconductor package202comprises electrical trace504, which couples to a plurality of package pads204, providing electrical circuit continuity through a plurality of solder ball joints206, and circuit board lands208, to a plurality of monitoring pins502.

In this embodiment of the invention, predetermined monitoring pins502may be comprised of solder balls510comprising solder of predetermined, but differing, compositions (e.g., various SnPb and Pb-free alloys), each of which will typically fracture at different strain levels. Depending upon the specific strain and strain-rate conditions, common solder alloys like eutectic SnPb solder (63% Sn, 37% Pb) may be less susceptible to fracture than Pb-free solder alloys such as Sn3Ag0.5Cu (96.5% Sn, 3% Ag, 0.5% Cu). Additional solder alloy examples of differing brittle fracture resistance include SnPb10 (90% Sn, 10% Pb), SnAg3.4Bi4.8 (91.8% Sn, 3.4% Ag, 4.8% Bi), and SnAg2.5Bi1.0Cu0.5 (96% Sn, 2.5% Ag, 1% Bi, 0.5% Cu). Other embodiments of the invention can be implemented with tin coated copper balls or organic balls with metallic coatings.

In this embodiment, loss of circuit continuity through monitoring pins502can indicate a brittle fracture of one or more solder interconnections. In one embodiment of the present invention, an early brittle fracture detection system can be implemented by coupling solder joints that fracture at lower strain levels to monitoring pins.

FIG. 6is a generalized illustration of the functional components of a testing and monitoring system600that can be used to monitor solder interconnects in accordance with the present invention. The testing and monitoring system600comprises a test voltage source602that provides a voltage across the terminals of the solder interconnects502a,502b, . . . ,502n, of the device under test604. A current monitor606is operable to monitor the current through the various solder interconnects,502a,502b, . . . ,502nand to provide a “fault detected” signal to a fault indicator608. As will be appreciated by those of skill in the art, the various functional components illustrated inFIG. 6can be implemented as part of a computer system or other electronic device. Alternatively, the functional components illustrated inFIG. 6can be implemented in a stand-alone test system.

Those of skill in the art will recognize that different embodiments of the invention may comprise multiple monitoring pin implementations. Similarly, it will be understood by those skilled in the art, that monitoring pins may be comprised of solder attached leadframe, solder coated land pad, solder coated metallic or organic sphere, or other configurations. As will also be apparent to those skilled in the art, the method and apparatus of the invention is not limited to grid array style semiconductor devices, but can also be implemented for peripheral leadframe, and other semiconductor package geometries.

Those skilled in the art will understand that the integrity of device solder joints in end-use operation is generally unknown. Fractures may exist that manifest their existence by intermittent electrical events that are difficult to isolate, without physical de-construction of the assembly. Use of the invention will insure, at a minimum, that solder joint fractures can be detected as they occur throughout the lifecycle of monitored components. Further, the invention monitors solder joint integrity on a continuous basis during actual end-use, across a plurality of component combinations and system configurations, rather than relying on a one-time electrical check prior to shipment. In addition, the present invention provides a method to assess whether excessive mechanical strain has been imposed on a circuit board assembly.