Programmable logic circuit using three-dimensional stacking techniques

A configurable die stack arrangement including a first configurable integrated circuit die located on a first substrate. The first configurable integrated circuit die includes a first array and a first configuration memory management circuit that includes an interface to the first array. The first array includes a first logic element and a first configuration memory. The configurable die stack arrangement also includes a second configurable integrated circuit die located on a second substrate that is different than the first substrate. The second configurable integrated circuit die includes a second array and a second configuration memory management circuit that includes an interface to the second array. The second array includes a second logic element and a second configuration memory. A signal is coupled to the first configuration management circuit and to the second configuration management circuit, and the first configuration memory management circuit includes circuitry to control the signal.

BACKGROUND

The present invention relates to integrated circuits, and more specifically, to programmable logic circuits.

One example of a programmable logic circuit is a field programmable gate array (“FPGA”). FPGAs are integrated circuits having an array of configurable logic blocks embedded in a matrix of interconnecting conductors with configurable connections to each other and to the logic blocks. FPGAs and similar configurable/programmable logic circuits (e.g., complex programmable logic devices or “CPLDs”) can be modified and updated in order to change their behavior or to function in a system. Each programmable element is made up of two parts: a configurable memory and an associated logic. A factor in determining the size of the memory and the logic in each cell is the programmability of the logic.

Continued semiconductor scaling becomes increasingly difficult and costly due to device dimensions approaching atomic scale. Three-dimensional (3D) integrated circuit chip integration techniques provide a means of significant scaling by electrically coupling two or more integrated circuit chips together, usually coplanar.

Integrated circuit chips are typically built-up layer-by-layer, having the conducting metal, power, and signal interconnections on the face of the chip. One method of providing a two layer chip stack is by having electrical connections between two chips arranged face-to-face with electrical conducting solder structures bonding the signal connections between the two chips with some contacts exposed and connected to the external package for system signal connections.

Another method of providing electric connection between semiconductor chips employs through substrate “vias” (TSVs) that are formed through the substrate of a semiconductor chip. Like conventional vias that are conducting structures used to vertically couple conducting metal layers within a chip, the TSVs reach through to the backside of a die after special wafer thinning processes expose the TSVs. Then additional metal layers may be applied to the backside of the wafer to facilitate having signal connections on both that face and back side of a die that are connected through the die. Two or more die having TSVs may be stacked for very high integrated circuit density.

SUMMARY

An embodiment is a configurable die stack arrangement that includes a first configurable integrated circuit die located on a first substrate. The first configurable integrated circuit die includes a first array and a first configuration memory management circuit that includes an interface to the first array. The first array includes a first logic element and a first configuration memory. The configurable die stack arrangement also includes a second configurable integrated circuit die located on a second substrate. The second substrate is different than the first substrate. The second configurable integrated circuit die includes a second array and a second configuration memory management circuit that includes an interface to the second array. The second array includes a second logic element and a second configuration memory. A signal is coupled to both the first configuration memory management circuit and the second configuration memory management circuit, and the first configuration memory management circuit includes circuitry to control the signal.

The second configurable integrated circuit die includes a second logic element configuration module and a second configuration memory management circuit that includes an interface to the second logic element configuration module. Also included in the configurable integrated circuit die is a signal coupled to both the first configurable integrated circuit die and the second configurable integrated circuit die. The first configuration memory management circuit further includes circuitry to control the signal.

Another embodiment is a method of configuring a plurality of configurable integrated circuit die. The method includes receiving a configuration data stream at a die stack. The configuration data stream includes configuration memory data for logic devices located on dies in the die stack. At least two of the dies are located on different substrates. The method also includes, performing for each of the dies in the die stack: receiving the configuration memory data for the die; storing the configuration memory data for the die in a configuration memory on the die; determining whether the configuration data stream includes configuration memory data for an additional die in the die stack; and transmitting the configuration data stream to the additional die in the die stack in response to the configuration data stream including configuration memory data for the additional die in the die stack.

A further embodiment is a computer program product for configuring a plurality of configurable integrated circuit dies. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes receiving a configuration data stream at a die stack. The configuration data stream includes configuration memory data for logic devices located on dies in the die stack. At least two of the dies are located on different substrates. The method also includes, performing for each of the dies in the die stack: receiving the configuration memory data for the die; storing the configuration memory data for the die in a configuration memory on the die; determining whether the configuration data stream includes configuration memory data for an additional die in the die stack; and transmitting the configuration data stream to the additional die in the die stack in response to the configuration data stream including configuration memory data for the additional die in the die stack.

A further embodiment is a method of testing configuration data for configurable integrated circuit dies. The method includes receiving a test configuration data stream at a die stack. The test configuration data stream includes configuration memory data for logic devices located on dies in the die stack. At least two of the dies in the die stack are located on different substrates and the configuration memory data includes at least one faulty bit. The die stack is placed in a test mode that disables error detection and correction of the configuration data stream. The method further includes performing for each of the dies in the die stack: receiving the configuration memory data for the die; storing the configuration memory data for the die in a configuration memory on the die; determining whether the test configuration data stream includes configuration memory data for an additional die in the die stack; and transmitting the test configuration data stream to the additional die in the die stack responsive to the test configuration data stream including configuration memory data for the additional die in the die stack.

DETAILED DESCRIPTION

Field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs) are reconfigurable logic devices that include arrays of logic elements and associated configuration state memory stored, for example, in configuration random access memories (CRAMs). The CRAM is implemented by static RAM (SRAM), flash memory (FLASH), fuses and/or other types of memory. A common FPGA logic element is a configurable block of logic referred to as a look-up-table (LUT). A configuration state memory bit is output from the LUT based on user input signals. This output can be further configured for connection to a clocked register or to an interconnection fabric that can further be configured to route the output or registered output to other LUT user inputs. A basic LUT may be comprised of a 16-bit CRAM with bits individually selected by four user input signals, however variations are common.

A typical FPGA integrated circuit chip has thousands to hundreds of thousands of such LUTs. FPGA and CPLD device configuration data is loaded from outside the integrated circuit (also referred to herein has a “circuit chip” or “chip”), usually via device signal contacts or interfaces set aside for this purpose. Once loaded, a configuration data integrity checker circuit (also referred to herein as an integrity check circuit) is used to periodically validate, by reading and checking one block at a time for correctness using a cyclical redundancy code (CRC) and/or error correction code (ECC) scheme, the SRAM based CRAM content typically employed within FPGAs.

User control signals include a look-up address signal to select a CRAM state as an output for defining the configured logic function. For example, a 2-input logic “AND” function can be implemented using four CRAM bits where two user input signals select CRAM bits0through3having configured state 0, 0, 0, and 1 output respectively. Similarly, other Boolean logic functions can be implemented using other LUT combinations. FPGA CRAM states are highly under utilized, as many LUTs are unused or only partially used in applications. Many LUTs have similar or the same CRAM content when they are configured for the same Boolean logic functions. Significant reduction in CRAM can be achieved by having different CRAM structures employed on the chip, where some portion of the row and columns of LUTs employ compressed CRAM along with uncompressed CRAM LUTs. This will increase the efficiency of the FPGA circuits but reducing the total CRAM needed as well as the area, power, CRAM soft-error rate. This also reduces the amount of interconnections needed to transport CRAM state between chips within a chip stack when desired.

An embodiment of the programmable logic circuit described herein includes an array of programmable logic elements on one die and an array of memory elements on another die. In an embodiment, the programmable logic elements and memory elements are on different substrates and communicate with each other via through substrate vias (TSVs).

An embodiment includes a system to allow interchangeable use of configurable random access and non-volatile memories. Because the physical interface and logic configuration remains the same, the user may implement either version while maintaining identical physical and electrical properties. By keeping the physical and electrical properties identical between versions of the system, either version can be used interchangeably. Because the chip that directly interacts with the system is unchanged, the electrical characteristics are identical between the two implementations, and this greatly reduces variability between the versions.

In an embodiment, memory elements are implemented using random access memory (RAM), which can be both read from and written to in order to change the programming of the logic. In an embodiment, the RAM stores data referred to as configuration memory data, which is used to program the logic. A die containing the RAM is used during system test because the test may result in updates to the configuration memory. Once the programmable logic circuit has been tested and is functioning as expected, the contents of the RAM devices are copied to a non-volatile read-only-memory (ROM) on another die so that the programming is permanently retained, even when power is removed. The memory elements on the ROM die are then connected (e.g., via TSVs) to the programmable logic elements.

An embodiment uses TSV stacking to remove the configuration memory from the logic die by placing the configuration memory on a separate die (or substrate) of the stack. TSV, as known in the art, refers to a vertical electrical connection (via) passing completely through a silicon wafer or die. Also as known in the art, a three-dimensional (3D) integrated circuit is a single integrated circuit built by stacking silicon wafers and/or dies and interconnecting them vertically so that they behave as a single device.

In an embodiment, integrated circuit die stacking with packaging TSV and other packaging techniques provide the means to interconnect dies (e.g., located on different substrates) in ultra close proximity using the vertical dimension. Although these arrangements enable higher performance and packaging density, the constituent die and associated function are still designed and used as a collection of independent die as though they were packaged using conventional two-dimensional (2D) packaging techniques, despite being assembled in a unified inseparable module. Having the stacked arrangement take on the characteristics of a monolithic die has benefits for manufacturability, reliability, and extendable function. Therefore, it is beneficial to have a stacked die arrangement characteristically function like a monolithic die. It is further beneficial to be able to have stacked FPGA or CPLD devices load the configuration data through the stack.

In an embodiment, a plurality of independent FPGA or CPLD chips are stacked into a common device that includes a base die having a set of signal contacts that connect to a system through a board or substrate. Other chips within the stack are only in contact with adjacent chips and have no direct connection to the system. Each of the independent dies receives configuration memory data through the base die that has the system interface. In an embodiment, the configuration data stream is encoded to indicate which type of device is being configured, the beginning and the end of the die configuration memory data, fault detection and correction redundant data, data compression type and an indicator to indicate when the complete configuration sequence is complete for the stacked configuration.

An FPGA or CPLD device has an extensive interconnection fabric that includes a matrix of signal routing conductors arranged on the die along with periodic configurable couplings that permit the user logic outputs to be interconnected to user logic inputs. A TSV stacked die employs some of these configurable couplings to be able to couple signal routing conductors to TSV's that can reach adjacent die to extend the interconnection fabric between die.

In an embodiment, the CRAM state is accessed via a user logic interconnection fabric such as that described in United States Patent Publication Number US20100241900, entitled “System to Determine Fault Tolerance in an Integrated Circuit and Associated Methods.” Having the CRAM state transferrable between die using the configurable interconnection fabric permits CRAM state to be used on a different die for reliability, repair, redundancy or non-volatility when the CRAM state is transferred from a non-volatile or more reliable CRAM source from within the die stack.

An embodiment of the present invention is a programmable logic circuit arrangement having configuration memory associated and associated logic for one or more programmable elements on separate integrated circuit chips within a chip stack. In an embodiment, the memory and programmable logic are located on different substrates and are connected to each other using 3D stacking techniques. The use of 3D stacking techniques allows the memory and logic to be optimally segregated on separate integrated circuit chips that are assembled into a single heterogeneous integrated component. These chips may use different technologies best suited for cost, reliability, performance, voltage, power, or characteristic features. Moreover, combinations of configuration memory that are both local to a logic die as well as remote from a member die in the stack can provide unique reliability, fault tolerance, cost reduction opportunities for the heterogeneous stacked chip, particularly when the programmable circuit interconnect fabric is designed to permit configuration memory state to be selectively routed and used across the die in a stack.

As used herein, the terms “configurable integrated circuit die” or “die” refers to a block of semiconducting material on which a given functional circuit (e.g., a configuration memory management circuit, a programmable logic circuit) is fabricated on a substrate. Different die are located on different substrates. As used herein, the term “substrate” refers to an independent foundation, usually a thin planar structure, on which an integrated circuit chip can be coupled. Manufacturing packaging and applications may define a substrate as an organic laminate, a glass or glass ceramic package, or the substrate may be a semiconductor or another integrated circuit. In any case the substrate will have electrical or optical conductors for coupling signals to between the integrated circuit and substrate.

Die size, integrated circuit technology, processing and test steps are directly related to cost of the die. Creating a heterogeneous die stack carries specific costs associated with such a structure, but these costs are offset by the savings in having optimal constituent die and reparability achieved by having die in the stack used to repair or recover from faults inherent to a different die in the stack. Specific die within the stack may have regions where configuration state is derived locally and regions where the configuration state is derived from a remote die for reliability and fault tolerance to unique to the specified regions. The user may configure such regions based on application requirements by using design software mapping and design management tools typically used to develop a user application for a configurable logic circuit.

In an embodiment, a plurality of independent FPGA or CPLD dies are stacked into a common device that includes a base die having a set of signal contacts that connect to a system board or substrate. In this embodiment, the stacked dies other than the base die are only in contact with other dies in the stack. Each of the independent dies receives configuration memory data that is input to the stack via an input on the base die that is connected to a system interface for receiving a configuration data stream.

In an embodiment, each die has an identical configuration memory management circuit and identical interfaces. The configuration memory management circuit receives, decodes, verifies integrity and loads the configuration memory data from the configuration data stream using an associated clock. The base die receives the configuration data stream and self-configures, including selecting the configuration data stream and clock to be propagated to the interface on the adjacent die after the base die configuration is loaded, and so on until each successive die in the stack has received its configuration. This scheme benefits from having the configuration data used to identify each die in the stack without the need for external die address, select or identification signals since each die is configured in a prescribed order.

In an embodiment, integrity checker functions (e.g., CRC, ECC) on the configuration memory management circuit are disabled to facilitate loading the configuration memory with “bad” data for error injection testing user logic fault tolerance circuits. The configuration data stream includes specific bits and protocol to switch the CRAM and data stream integrity checking on and off as desired.

FIG. 1is a block diagram of a topology of FPGA programmable elements on a single die, in accordance with an embodiment. A single grouping of programmable elements, of which there may be many in a single FPGA chip, is illustrated inFIG. 1. The grouping's size will be determined by the physical characteristics of the architecture of the FPGA. The central structures inFIG. 1are the data access register arrangement100and the addressing function120that determine which of the programmable elements140-157are being acted upon. Each of these structures inFIG. 1are fed by a central CRAM loader circuit103that is designed to load one or more such structures and will feed to a central CRC checking structure104that can check many of these structures. The data access register arrangement100is fed from the central load mechanism by a scan connection101and feeds to the central CRC checking structure104by a scan connection102.

Each programmable element140-157includes two parts: the CRAM and the LUT. The size of the CRAM in each cell is determined by the extent of the programmability of the LUT (i.e., the programmable logic). The size of the CRAM and the desired speed to conduct the checking will determine the extent of the checking performed.

The addressing function120determines which programmable element or elements140-157will be loaded or read to the data access register arrangement100in any given cycle. The data access register arrangement100is connected to the programmable elements140-157by data buses110-115which are each as wide as the CRAM in a single programmable element140-157.

The control from the addressing function120to each programmable element is connected by address selection signals130-135. It is possible to load multiple programmable elements in a single column in this example such as140,146, and152.

In an embodiment, the FPGA integrated circuit shown inFIG. 1is part of a configurable die stack arrangement that includes at least two FPGA dies (or other configurable integrated circuit dies). In an embodiment, each of the dies is located on a different substrate. Each die in the die stack includes a configuration memory management circuit to load configuration data into the FPGAs (e.g., into the central CRAM loader circuit103ofFIG. 1). One of the configuration memory management circuits (e.g., the base die) receives configuration memory data from a source located outside of the die stack (e.g., from a test generator or a configuration generator). The rest of the configuration memory management circuits in the die stack receive configuration memory management data from another configuration memory management circuit in the die stack.

In an embodiment, the configuration memory management circuit located on the die at the bottom of the die stack receives memory management data from outside of the die stack, selects the memory management data applicable to the bottom die stack and sends memory management data to the next die in the stack. In an embodiment, the selecting and sending is performed by control circuitry located on the configuration memory management circuit. This process of receiving memory management data from a previous die and transmitting memory management data to a next die in the stack continues for each die in the stack that contains a configuration memory management circuit. Thus, only one die in the die stack is required to have an output pin (or other means) to communicate to an entity (e.g. a circuit) outside of the die stack.

FIG. 2depicts a process flow for testing logic circuits in accordance with an embodiment. The process flow depicted inFIG. 2may be used to modify features and/or functions of programmable logic circuit by using a RAM device when testing, fixing errors and/or updating features on the programmable logic circuit. The resulting RAM content is then copied into a ROM which is used in the programmable logic circuit during production.

As used herein, the term “test” or “test mode” refers to the programmable logic circuit being tested (e.g., design is verified) and debugged, prior to being used by a customer to perform business operations. This is contrasted with the term “production” or “production mode” which refers to the programmable logic circuit being used by a customer to perform business activities. Production mode generally occurs after design validation has been completed.

Referring toFIG. 2, at block202, logic devices containing the logic portions of programmable elements are placed on a first die, and at block204, RAM devices containing the memory portions of the programmable elements are placed on a second die. The logic devices are connected (e.g., via TSV) to the memory devices at block206, and at block208, the logic devices are programmed with contents of the RAM devices. The logic devices are tested and debugged at block210. In an embodiment, a controller performs the programming and the testing/debugging is performed by using the device in the system as it would be used in the finished product. During the testing (or test mode), contents of the RAM devices may be updated to reflect any changes required to the logic devices discovered during the testing and debugging process. Once testing and debugging are completed, the RAM devices on the second die are disconnected from the logic devices on the first die. At block212, the contents (e.g., configuration data) of the RAM devices are copied to ROM devices located on a third die. The logic devices on the first die are connected (e.g., via TSV) to the ROM devices on the third die at block214and used to program the logic devices. The programmable logic circuit formed by the first die and the third die is utilized in a production mode.

The process described in reference toFIG. 2allows a user to retain the logic element of the stack and choose between programmable memory (e.g., RAM) and ROM for another element of the stack. By choosing programmable memory, the user may develop and modify the configuration data, for example. Once the user is satisfied with the configuration data, a ROM, which contains the configuration data is created. The ROM then replaces the programmable memory in the stack, while retaining the logic element of the stack. The logical and signaling characteristics of the stack are retained, while the ROM does not require initialization from a state stored outside the stack and is therefore resistant to logic upsets from environmental radiation, removal of power, or the like.

The process depicted inFIG. 2allows the user to quickly go from a fully programmable environment (which also would require programming at power on time) to an environment that is ready and does not require programming at power on time. Thus, embodiments provide the ability to switch between these two environments easily using the common “first die”.

FIG. 3is a block diagram of a side view of a FPGA in a 3D stack in accordance with an embodiment. As shown inFIG. 3, a die302(or substrate) containing RAM memory elements is attached, using TSVs306, to a die304(or substrate) containing logic elements.

FIG. 4is a block diagram of a FPGA in a 3D stack in accordance with an embodiment. One die404(or substrate) of the stack carries the programmable logic of the FPGA, and another die402(or substrate) of the stack carries the configuration data for the logic in the first element of the stack. The memory is programmable and implemented by static RAM, dynamic RAM, or the like. In the embodiment shown inFIG. 4, the programmable logic is configured by the data contained in the memory attached in the stack. TSVs connect the two dies of the stack physically and electrically.

FIG. 5is a block diagram of a side view of a FPGA with ROM in a 3D stack in accordance with an embodiment. A first die506of the stack504(or substrate) carries the programmable logic of the FPGA, and another die502(or substrate) of the stack504carries the configuration data for the logic in the first die506of the stack504. The memory is not programmable and is implemented by ROM, or the like. In the embodiment shown inFIG. 5, the programmable logic is configured by the data contained in the memory attached in the stack504. TSVs508connect the two die of the stack physically and electrically.

FIG. 6is a block diagram of a FPGA with ROM in a 3D stack in accordance with an embodiment. As shown inFIG. 6, a die602(or substrate) containing ROM memory elements is attached, using TSV, to a die604(or substrate) containing logic elements.

In another embodiment, as shown inFIGS. 7 and 8, the programmable logic and the configuration memory remain in a programmable element (e.g., on the same die702) of the stack804. Another die704, carrying both memory and logic, is attached to the 3D stack using TSVs808. This embodiment allows for smaller FPGA integrated circuits to be aggregated, thereby creating a larger FPGA by increasing the available programmable logic that would be available from either die702704without stacking. This embodiment saves cost by reducing the size of the dies702704required. Smaller chip sizes are easier and cheaper to make. By being able to stack smaller chips to make a larger chip equivalent, the cost of making the module could be reduced, as well as the footprint of the device when compared to the larger chip.

Because the interconnects going from die to die in a TSV stack are finite, if configuration memory data that needs to be sent from one die to the other is more than can be accommodated by the available TSV connections, compression may be used. In an embodiment, compression techniques (e.g., such as those described in U.S. Pat. No. 4,891,643) are used. By using compression, fewer signal bits are required to deliver more data bits from the memory to the logic that requires the configuration bits. The compressed format is the data encoding determined by the compression algorithm.

FIG. 9is a block diagram of die stack having two configuration memory management circuits located on two configurable integrated circuit dies in accordance with an embodiment. In the embodiment shown inFIG. 9, a configuration memory management circuit is located on a base configurable integrated circuit die907and on an adjacent configurable integrated circuit die911. More than one configuration memory management circuit may be implemented and operated in parallel on a common die. In an embodiment, the configuration memory management circuits receive, decode, verify integrity, and load the configuration memory data from the configuration data stream and an associated clock.

As shown inFIG. 9, the configuration memory management circuits include: a system input902connected to an electrode on one side of the die908for receiving a configuration memory data stream; a circuit901to control the path of the configuration memory data stream (e.g., to a loader circuit on the die, such as central CRAM loader circuit103or to another die); an interface910to a loader circuit on the die for sending configuration memory data to configure the CRAM on the die; an interface903to send configuration memory data to a multiplexer906, a select signal905to allow data to flow through the multiplexer906; and a system output904connected to the output from the multiplexer906and to an electrode an another side909of the die for transmitting the portion of the configuration memory stream not used by the current die to an adjacent die.

The base configurable integrated circuit die907as shown inFIG. 9receives the configuration data stream via the system input902and self-configures, including decoding the configuration data stream to generate a select signal905to select the configuration data stream and clock to be propagated via a system output904to an adjacent configurable integrated circuit die911system input902and circuit901after the base configurable integrated circuit die907configuration is loaded, and so on until each successive die in the stack has received its configuration In an embodiment, the portion of the circuitry on the configurable integrated circuit die907that generates the select signal905along with the multiplexer906is referred to herein as the control circuit.

FIG. 10depicts a process flow for configuring programmable logic elements (e.g., FPGAs, CRAMs) in a die stack in accordance with an embodiment. At block1002, a configuration data stream, that includes configuration memory data, is received at a die (e.g., a base die) in a die stack. In an embodiment, the die is one of several dies in a die stack and the configuration data stream is received via a system input, such as system input902. At block1004, the configuration data stream is transmitted to a loader circuit, such as central CRAM loader circuit103, on the die. When all of the configuration data for the current die has been received, block1006is performed to determine if there is additional data in the configuration data stream. In an embodiment, at block1004, a circuit, such as circuit901counts the number of configuration data bits received and when the number of bits required for configuring the current die have been received, processing continues at block1006.

In another embodiment, once a buffer or other storage mechanism is full, processing continues at block1006. In an embodiment, once all of the configuration memory data is loaded into the loader circuit, the configuration of the die is automatically initiated. At block1006, it is determined if there are additional bits in the configuration data stream. If there are no additional bits, block1008is performed and the transmission of configuration data to the dies in the stack is complete. If there are additional bits, block1010is performed and the circuitry enables the next die in the stack to receive the configuration data stream. In the embodiment depicted inFIG. 9, this occurs when the circuit901generates a select signal905to the multiplexer906to open a gate to allow the configuration data stream to flow to the system output904and up to the next die.

A variety of manners of applying the configuration data stream to dies in the die stack may be implemented. In an embodiment, transmission of configuration data is complete when all of the dies in the stack have received bits in the configuration data stream. In another embodiment, transmission of configuration data is complete when selected dies in the stack have received bits from the configuration data stream. In this embodiment, a subset of the dies in the stack receive bits from the configuration data stream. For selected dies, the interface to the configuration data stream is disabled, thus allowing the die to ignore date received from the base die configuration management circuit. In one embodiment, a selected number of dies closest to the base die receive configuration data. In another embodiment, the configuration data stream specifies selected dies for receiving all or portions of the configuration data stream.

Embodiment described herein benefit from having the configuration data used to identify each die in the stack without the need for external die address, select or identification signals since each die is configured in a prescribed order. In an embodiment, the integrated circuit dies also include error detection and correction circuitry to detect and correct errors in configuration memory data received via the system inputs902. In an embodiment, the integrity checker in the circuit is configured to disable checking to facilitate loading the configuration memory with “bad” data (error injection) for testing user logic fault tolerance.

Another embodiment avoids using the conventional system input902for a non-base die, such as die911, and instead configures a connection directly to a programmable logic circuit data register complex, such as CRAM data access register arrangement900. These devices use a post decoded and generally wider on-die bus connection that is exposed only to the stacked die configuration having higher density micro contacts. This structure can benefit from sharing and remaining under control of the base die configuration management loader and or integrity circuits.

In another embodiment, certain configuration data is transmitted between die where it may be directly used as configuration data on the receiving die or as compare data by user logic or the configuration controller or integrity checker for detecting and correcting faults with the configuration data. Such configuration data is coupled between dies via the configurable interconnection matrix connections. All or part of this configuration data may be compressed at the source die by user logic before routing to the adjacent die to reduce interconnection signal contacts between die. In an embodiment, the configuration data is transmitted in time domain multiplexed high speed bursts to reduce the signal contacts between the die. The compressed and/or high-speed data is decompressed and re-constructed after being received for use as configuration data in the receiving die.

In another embodiment, the configuration data is mapped or allocated between the stacked die such that high reliability user logic is placed on one die and lower reliability user logic is located to another die such that the configuration data integrity checker may be configured by user logic or from the device configuration tools to check all or part of the configuration data RAM at an accelerated rate. Controlling the configuration data integrity checker rate may be further controlled by locality on a die as directed by user logic or by the device configuration tools.

In a further embodiment, the configuration memory includes embedded DRAM (EDRAM) and has a memory refresh synchronization circuit to align EDRAM refresh with the user logic clock period (also referred to herein as a user clock period) to avoid refresh that would cause the configuration memory state uncertainty during the user logic setup and hold stability time requirements at receiving clocked registers and constrained device outputs.

Technical effects and benefits include the ability to change the functionality of a programmable logic circuit by switching the ROM containing the configuration logic. Additional benefits include the ability to reduce the size of the programmable logic circuit and to operate more efficiently. A further benefit is the ability to configure the integrated circuit dies in a die stack using a single external interface to communicate outside of the stack.