Silicon carbide trench MOSFET having reduced on-resistance, increased dielectric withstand voltage, and reduced threshold voltage

A semiconductor device (A1) includes a first n-type semiconductor layer (11), a second n-type semiconductor layer (12), a p-type semiconductor layer (13), a trench (3), an insulating layer (5), a gate electrode (41), and an n-type semiconductor region (14). The p-type semiconductor layer (13) includes a channel region that is along the trench (3) and in contact with the second n-type semiconductor layer (12) and the n-type semiconductor region (14). The size of the channel region in the depth direction x is 0.1 to 0.5 μm. The channel region includes a high-concentration region where the peak impurity concentration is approximately 1×1018 cm−3. The semiconductor device A1 thus configured allows achieving desirable values of on-resistance, dielectric withstand voltage and threshold voltage.

TECHNICAL FIELD

The present invention relates to a semiconductor device having a trench structure.

BACKGROUND ART

FIG. 9shows an example of a conventional vertical insulated-gate semiconductor device having a trench structure. The semiconductor device9A shown in the FIGURE includes a first n-type semiconductor layer911, a second n-type semiconductor layer912, a p-type semiconductor layer913, an n-type semiconductor region914, a trench93, a gate electrode94and a gate insulating layer95.

The first n-type semiconductor layer911serves as a base of the semiconductor device9A. The second n-type semiconductor layer912, the p-type semiconductor layer913, and the n-type semiconductor region914are stacked on the first n-type semiconductor layer911.

The trench93is formed so as to penetrate through the p-type semiconductor layer913and the n-type semiconductor region914to reach the second n-type semiconductor layer912. Inside the trench93, the gate electrode94and the gate insulating layer95are provided. The gate insulating layer95insulates the gate electrode94from the second n-type semiconductor layer912, the p-type semiconductor layer913and the n-type semiconductor region914. The gate insulating layer95is formed along the inner surface of the trench93.

The p-type semiconductor layer913includes a channel region. The channel region is along the trench93and in contact with the second n-type semiconductor layer912and the n-type semiconductor region914.

Regarding the semiconductor device9A thus configured, it is preferable that the on-resistance is low from the viewpoint of reducing energy loss. To prevent dielectric breakdown, it is preferable that the dielectric withstand voltage is high. Also, there is a demand for a reduced threshold voltage so that the semiconductor device can be driven by applying a relatively low voltage to the gate electrode (see Patent Document 1, for example).

DISCLOSURE OF THE INVENTION

Problems To Be Solved By the Invention

The present invention has been proposed under the foregoing circumstances. It is an object of the present invention to provide a semiconductor device that allows reducing the on-resistance, increasing the dielectric withstand voltage and reducing the threshold voltage.

Means For Solving the Problems

A semiconductor device provided according to the present invention includes a first semiconductor layer having a first conductivity type, a second semiconductor layer provided on the first semiconductor layer and having a second conductivity type opposite to the first conductivity type, a trench penetrating through the second semiconductor layer to reach the first semiconductor layer, an insulating layer formed at a bottom and a side of the trench along an inner surface of the trench, a gate electrode which is insulated by the insulating layer from the first semiconductor layer and the second semiconductor layer and at least part of which is formed inside the trench, and a semiconductor region having the first conductivity type and formed around the trench on the second semiconductor layer. The second semiconductor layer includes a channel region that is along the trench and in contact with the first semiconductor layer and the semiconductor region. The size of the channel region in a depth direction of the trench is 0.1 to 0.5 μm, and the peak impurity concentration of the channel region is in a range of 4×1017cm−3to 2×1018cm−3.

In a preferred embodiment of the present invention, the channel region includes a high-concentration region where impurity concentration is equal to or higher than 5×1017cm−3. The high-concentration region is in the form of a layer that is in contact with the trench and that spreads in a direction perpendicular to the depth direction.

In a preferred embodiment of the present invention, the second semiconductor layer and the semiconductor region are made of silicon carbide.

Other features and advantages of the present invention will become more apparent from detailed description given below with reference to the accompanying drawings.

BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1depicts a semiconductor device according to a first embodiment of the present invention. The semiconductor device A1according to this embodiment includes a first n-type semiconductor layer11, a second n-type semiconductor layer12, a p-type semiconductor layer13, a high-concentration p-type semiconductor region13a, an n-type semiconductor region14, a trench3, a gate electrode41, a gate insulating layer5, a source electrode42, a drain electrode43and an interlayer insulating film6, and has what is known as trench MOSFET structure.

The first n-type semiconductor layer11is a substrate made of silicon carbide with high-concentration impurity added thereto, and serves as a base of the semiconductor device A1. The size of the first n-type semiconductor layer11in the depth direction x is approximately 300 μm. The impurity concentration in the first n-type semiconductor layer11is approximately 1×1019cm−3.

The second n-type semiconductor layer12is formed on the first n-type semiconductor layer11. The second n-type semiconductor layer12is made of silicon carbide with low-concentration impurity added thereto. The size of the second n-type semiconductor layer12in the depth direction x is approximately 10 μm. The impurity concentration of the second n-type semiconductor layer12is approximately 6×1015cm−3. However, the impurity concentration of the second n-type semiconductor layer12is not limited to this and may be in a range of approximately 1×1015to 2×1016cm−3.

The p-type semiconductor layer13is formed on the second n-type semiconductor layer12. The size of the p-type semiconductor layer13in the depth direction x is approximately 0.3 μm. It is preferable that the size of the p-type semiconductor layer13in the depth direction is in a range of 0.1 to 0.5 μm. The impurity concentration of the p-type semiconductor layer13is 1×1017cm−3or higher.

The p-type semiconductor layer13includes a channel region. The channel region is along the trench3and in contact with the second n-type semiconductor layer12and the n-type semiconductor region14. The size of the p-type semiconductor layer13in the depth direction x needs to be in a range that provides a short channel effect. The short channel effect refers to the phenomenon that a decrease in size of the channel region in the depth direction x leads to a lower threshold voltage of the semiconductor device A1. When the size of the p-type semiconductor layer13in the depth direction is smaller than 0.1 μm, the channel region may often fail to effectively perform its function.

FIG. 2shows the distribution of impurity concentration Ic in the depth direction x, in the p-type semiconductor layer13. With an increase in depth Dp, the impurity concentration Ic becomes higher. The impurity concentration Ic is highest at a certain depth Dp, and becomes lower with a further increase in depth Dp. Specifically, the impurity concentration Ic is highest at the depth Dp of approximately 0.5 μm, and the value at this point is approximately 1×1018cm−3. In order to attain a sufficient withstand voltage, it is preferable that the p-type semiconductor layer13includes a high-concentration region13′. In the figure, the portion where the impurity concentration is 5×1017cm−3or higher is the high-concentration region13′. When the size of the p-type semiconductor layer13exceeds 0.5 μm, it is difficult to create such impurity concentration distribution by e.g. impurity ion irradiation and to sufficiently exhibit the short channel effect.

The n-type semiconductor region14is formed on the p-type semiconductor layer13. The size of the n-type semiconductor region14in the depth direction x is approximately 0.3 μm. The impurity concentration of the n-type semiconductor region14is approximately 1×1020cm−3. However, the impurity concentration of the n-type semiconductor region14is not limited to this, and it is only required that the impurity concentration is not lower than 1×1018cm−3. The high-concentration p-type semiconductor region13ais formed on the p-type semiconductor layer13.

The trench3is formed so as to penetrate through the p-type semiconductor layer13and the n-type semiconductor region14to reach the second n-type semiconductor layer12. The size of the trench3in the depth direction x is equal to or greater than that of the p-type semiconductor layer13in the depth direction x. In this embodiment, the size of the trench3in the depth direction x is approximately 1 μm.

Inside the trench3, the gate electrode41and the gate insulating layer5are formed. The gate insulating layer5serves to insulate the gate electrode41from the second n-type semiconductor layer12, the p-type semiconductor layer13, and the n-type semiconductor region14. The gate insulating layer5is formed on the inner surface of the trench3at the bottom and sides of the trench3. In this embodiment, the gate insulating layer5is made of, for example, silicon dioxide.

The size of the side portion of the gate insulating layer5in the width direction y is approximately 0.1 μm. The size of the bottom portion of the gate insulating layer5in the direction x is approximately 0.08 μm.

The source electrode42is made of aluminum for example, and in contact with the n-type semiconductor region14and the high-concentration p-type semiconductor region13a.The drain electrode43is made of aluminum for example, and in contact with the first n-type semiconductor layer11. The drain electrode43is formed on the opposite side of the second n-type semiconductor layer12across the first n-type semiconductor layer11. The interlayer insulating film6is formed so as to cover the gate electrode41.

An example of a manufacturing method of the semiconductor device A1is described below with reference toFIGS. 3 and 4.

First, as shown inFIG. 3, a semiconductor substrate made of silicon carbide, which is to become the first n-type semiconductor layer11, is prepared. Then, the second n-type semiconductor layer12is formed on the obverse surface of the substrate by epitaxial crystal growth. Then, impurity ions (p-type) such as aluminum ion or boron ion are implanted into the upper surface of the second n-type semiconductor layer12to thereby form the p-type semiconductor layer13. The impurity ions implanted in the silicon carbide barely diffuses in the silicon carbide substrate. The location of the implanted impurity ion in the silicon carbide substrate in the depth direction exclusively depends on the irradiation energy. Accordingly, by adjusting the energy when implanting impurity ions, the impurity concentration distribution in the depth direction as that shown inFIG. 2is provided. Then the n-type semiconductor region14and the high-concentration p-type semiconductor region13aare formed, for example by implanting impurity ions (n-type or p-type).

Then, as shown inFIG. 4, the trench3, the gate insulating layer5and the gate electrode41are formed. Thereafter, the interlayer insulating film6, the source electrode42and the drain electrode43are formed. Through the foregoing process, the semiconductor device A1shown inFIG. 1is obtained.

A comparison is made below between the semiconductor device A1according to the present invention and the conventional semiconductor device.

FIG. 5shows the relationship between peak concentration of impurity in the p-type semiconductor layer (p-type semiconductor layer highest concentration Ch) and threshold voltage Vt in the conventional semiconductor device. In the conventional semiconductor device, the short channel effect is not provided and the threshold voltage is not affected by the size of the channel region in the depth direction x, which is the difference from the semiconductor device A1.FIG. 6Ashows the relationship of threshold voltage Vt and dielectric breakdown field Vb to p-type semiconductor layer highest concentration Ch in the semiconductor device A1according to this embodiment.FIG. 6Bshows the relationship of channel resistance Rc and dielectric breakdown field Vb to p-type semiconductor layer highest concentration Ch in the semiconductor device A1according to this embodiment.

According toFIG. 5, in the conventional semiconductor device9A, when the highest impurity concentration Ch in the p-type semiconductor layer913is 2×1017cm−3, the threshold voltage Vt is 9 V. In this state, the channel resistance is 3.8 mΩcm2provided that the channel length is 1 μm and the dielectric breakdown field Vb at a corner portion of the trench93is 1.5 MVcm−1. When the highest impurity concentration Ch in the p-type semiconductor layer913is 5×1017cm−3, the threshold voltage Vt is 13 V. In this state, the channel resistance is 5.9 mΩcm2under a condition similar to the above, i.e. provided that the channel length is 1 μm and the dielectric breakdown field Vb at the bottom portion of the trench93is 1.5 MVcm−1.

In contrast, according toFIG. 6A, the threshold voltage Vt is in a range of 4 V to 11 V when the p-type semiconductor layer highest concentration Ch is in a range of 4×1017cm−3to 2×1018cm−3. In this range of p-type semiconductor layer highest concentration Ch, the dielectric breakdown field Vb is in a range of 0.9 MVcm−1to 1.7 MVcm−1. According toFIG. 6B, in this range of p-type semiconductor layer highest concentration Ch, the channel resistance Rc is in a range of 0.5 mΩcm2to 2.9 mΩcm2.

Here, the values of threshold voltage Vt, dielectric breakdown field Vb and channel resistance Rc at several points in the above-described range of p-type semiconductor layer highest concentration Ch will be cited. According toFIGS. 6A and 6B, when the p-type semiconductor layer highest concentration Ch is 4×1017cm−3, the threshold voltage Vt is 4 V. In this state, the dielectric breakdown field Vb is approximately 0.9 MVcm−1, while the channel resistance Rc is 0.5 mΩcm2. When the p-type semiconductor layer highest concentration Ch is 2×1018cm−3, the threshold voltage Vt is 11 V. In this state, the dielectric breakdown field Vb is approximately 1.7 MVcm−1, and the channel resistance Rc is 2.9 mΩcm2. When the p-type semiconductor layer highest concentration Ch is 1×1018cm−3, which is within the range of 4×1017cm−3to 2×1018cm−3, the threshold voltage Vt is 7 V. In this state, the dielectric breakdown field Vb is approximately 1.5 MVcm−1, and the channel resistance Rc is 1 mΩcm2.

The foregoing values of threshold voltage Vt, dielectric breakdown field Vb and channel resistance Rc are compared with those of the conventional semiconductor device described above with reference toFIG. 5. In the semiconductor device A1, the threshold voltage Vt is maintained at a relatively low level. Presumably, this is because the short channel effect takes place despite that the impurity concentration in the p-type semiconductor layer13is set in the foregoing range. Also, the dielectric breakdown field Vb is maintained at a relatively high level. This can be construed as a result of the impurity concentration of the p-type semiconductor layer13remaining high. Further, the channel resistance Rc is relatively small. This can be construed as a result of the reduction in size of the channel region in the depth direction. In this way, the values of threshold voltage Vt, dielectric breakdown field Vb and channel resistance Rc of the semiconductor device A1are in a desirable range as a whole. Consequently, the semiconductor device A1allows achieving more desirable values of on-resistance, dielectric withstand voltage and threshold voltage than those of the conventional semiconductor device.

FIGS. 7 and 8each depict another example of the semiconductor device according to the present invention. In these figures, constituents similar to those of the foregoing embodiment are given the same reference signs, and the description thereof is appropriately omitted.

FIG. 7shows a semiconductor device according to a second embodiment of the present invention. The semiconductor device A2according to this embodiment is different from the semiconductor device A1in having a structure of what is known as an IGBT (Insulated Gate Bipolar Transistor). The semiconductor device A2is similar to the semiconductor device A1in the size of the channel region and impurity concentration, as well as in including the high-concentration region13′ shown inFIG. 2and being made of silicon carbide. In this embodiment, a p-type substrate15is provided on the back surface of the n-type semiconductor layer12. Also, a nickel layer16is provided between the p-type substrate15and the drain electrode43.

This structure also allows, as does the semiconductor device A1, achieving relatively desirable values of on-resistance, dielectric withstand voltage and threshold voltage. Further, the semiconductor device A2as an IGBT is advantageous for reducing the resistance, and hence more suitable for use under a high voltage than the semiconductor device A1.

FIG. 8shows the semiconductor device according to a third embodiment of the present invention. The semiconductor device A3according to this embodiment is different from the semiconductor device A1in having a structure of what is known as an SJ (Super Junction) MOSFET. The semiconductor device A2is similar to the semiconductor device A1in the size of the channel region and impurity concentration, as well as in including the high-concentration region13′ shown inFIG. 2and being made of silicon carbide.

In this embodiment, a p-type semiconductor layer17is formed to sandwich the n-type semiconductor layer12in the direction y. The p-type semiconductor layer17has generally the same thickness as the second n-type semiconductor layer12, and is in contact with the first n-type semiconductor layer11and the p-type semiconductor layer13. Between the first n-type semiconductor layer11and the drain electrode43, a nickel layer16is provided. However, the structure is not limited to this, and the p-type semiconductor layer17may be formed along only halfway of the second n-type semiconductor layer12from the p-type semiconductor layer13. In the semiconductor device A3of the SJMOSFET structure, the first n-type semiconductor layer11serves as what is known as a drift layer, and the p-type semiconductor layer17as a RESURF layer.

Such structure also allows, as does the semiconductor device A1, achieving relatively desirable values of on-resistance, dielectric withstand voltage and threshold voltage. Further, the semiconductor device A3as an SJMOSFET is advantageous for achieving both of a higher withstand voltage and a lower resistance.

The semiconductor device according to the present invention is in no way limited to the foregoing embodiments. Specific structure of the constituents of the semiconductor device according to the present invention may be varied in design in various manners.