Edge evaluation techniques for graphics hardware

The edge evaluation technique, in accordance with one embodiment of the present technology, includes determining a number of edges of a given primitive to be evaluated. The technique also includes sequencing evaluation of a first edge by a first edge evaluation circuit and a second edge by a second edge evaluation circuit during a first clock cycle. The technique further includes sequencing evaluation of a third edge by the first edge evaluation circuit and a fourth edge by the second edge evaluation circuit during a second clock cycle if three or more edges are to be evaluated.

BACKGROUND OF THE INVENTION

Recent advances in computer performance have enabled graphic systems to provide more realistic graphical images using personal computers, home video game computers, handheld devices, and the like. In such graphic systems, a number of procedures are executed to “render” or draw graphic primitives to the screen of the system. A “graphic primitive” is a basic component of a graphic picture, such as a point, line, polygon, or the like. Rendered images are formed with combinations of these graphic primitives. Many procedures may be utilized to perform 3-D graphics rendering.

Specialized graphics processing units (e.g., GPUs, etc.) have been developed to optimize the computations required in executing the graphics rendering procedures. The GPUs are configured for high-speed operation and typically incorporate one or more rendering pipelines. Each pipeline includes a number of hardware-based functional units that are optimized for high-speed execution of graphics instructions/data, where the instructions/data are fed into the front end of the pipeline and the computed results emerge at the back end of the pipeline. The hardware-based functional units, cache memories, firmware, and the like, of the GPU are optimized to operate on the low-level graphics primitives (e.g., comprising “points”, “lines”, “triangles”, etc.) and produce real-time rendered 3-D images.

The real-time rendered 3-D images are generated using raster display technology. Raster display technology is widely used in computer graphics systems, and generally refers to the mechanism by which the grid of multiple pixels comprising an image are influenced by the graphics primitives. For each primitive, a typical rasterization system determines whether or not to “render,” or write a given pixel into a frame buffer or pixel map, as per the contribution of the primitive. This, in turn, determines how to write the data to the display buffer representing each pixel.

Once the primitives are rasterized into their constituent pixels, these pixels are then processed in pipeline stages subsequent to the rasterization stage where the rendering operations are performed. Generally, these rendering operations assign a color to each of the pixels of a display in accordance with the degree of coverage of the primitives comprising a scene. The per pixel color is also determined in accordance with texture map information that is assigned to the primitives, lighting information, and the like.

FIG. 1shows an exemplary implementation of graphics processing unit (GPU)100. The process performed by the GPU generally includes setting up a polygon model (e.g., a plurality of primitives) of objects, applying linear transformation to each primitive, culling back facing primitives, clipping the primitives against a view volume, rasterizing the primitives to a pixel coordinate set, shading/lighting the individual pixels using interpolated or incremental shading techniques, and the like. Accordingly, the GPU100hardware includes a setup engine110, a raster pipeline120, a shading pipeline130, a data write unit140, and one or more other units.

The raster pipeline120typically includes a rasterizer122, an edge evaluator124and one or more other circuits. The edge evaluator124computes the edge equation, Ax+By+C>0, for all samples, x and y, and all edges of each primitive. The primitive may include any number of edges. In an exemplary implementation the primitives may have four edges. Therefore, the exemplary edge evaluator124includes four edge evaluation circuits210-240arranged in parallel, as illustrated inFIG. 2. The edge evaluation circuits210-240each evaluate a given edge by computing the edge equation for all samples of an evaluation tile. For a four edge primitive evaluated for a two-by-two tile, the conventional edge evaluator124evaluates 16 samples per clock, which amounts to a significant area.

SUMMARY OF THE INVENTION

As computers continue to advance there is a continuing need for improvements in the graphics processing unit. Embodiments of the present technology are directed toward edge evaluation techniques for graphics hardware. In one embodiment a graphics processing unit includes two edge evaluation circuits and a sequencer. The two edge evaluation circuits are coupled, in parallel with each other, to the sequencer. The sequencer inputs a first edge to a first of the two edge evaluation circuits and a second edge to a second of the two edge evaluation circuits, and if more than two edges are to be evaluated inputs a third edge to the first of the two edge evaluation circuits and a forth edge to the second of the two edge evaluation circuits.

In another embodiment, an edge evaluation method includes determining a number of edges of a given primitive to be evaluated. The method also includes evaluating the first edge by a first edge evaluation circuit and the second edge by a second edge evaluation circuit during a first clock cycle and the third edge by the first edge evaluation circuit and the fourth edge by the second edge evaluation circuit during a second clock cycle, if three or more edges are to be evaluated. The method further includes evaluating a first edge by a first edge evaluation circuit and a second edge by a second edge evaluation circuit during a first clock cycle, if two or less edges are to be evaluated.

Embodiments of the present technology advantageously reduce the number of edge evaluators by almost half while incurring substantially less than half the slow down. The edge evaluator containing two edge evaluation circuits in accordance with embodiment of the present technology also consumes less power than conventional edge evaluators containing four edge evaluation circuits.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 3shows an edge evaluator300, in accordance with one embodiment of the present technology. The edge evaluator includes sequencer logic305-355and two edge evaluation circuits360,365. The two edge evaluation circuits360,365are coupled, in parallel with each other, to the sequencer logic305-355. The sequencer logic305-355may include input buffers305-320, one or more multiplexers/demultiplexers325,330, output buffers335-350and other control logic355. Each edge evaluation circuit360,365includes a plurality of adder circuits, registers and shift logic, to implement the addition and multiplication functions of the edge equation. Thus, each edge evaluation circuit360,365is a relatively large circuit. In particular, the edge evaluation circuits360,365are substantially larger than the sequencer logic305-355.

When the primitive includes four edges, the sequencer logic305-355inputs a first edge to the first edge evaluation circuit360and a second edge to the second edge evaluation circuit365during a first clock cycle. The sequencer logic305-355then inputs a third edge to the first edge evaluation circuit360and a fourth edge to the second edge evaluation circuit365during a second clock cycle. When the primitive includes three edges, the sequencer logic305-355inputs the first edge to the first edge evaluation circuit360and the second edge to the second edge evaluation circuit365during the first clock cycle. The sequencer logic305-355then inputs the third edge to the first edge evaluation circuit360during the second clock cycle. When the primitive includes two edges or where all but two edges are trivially already known, the sequencer logic305-355inputs a first edge to the first edge evaluation circuit360and a second edge to the second edge evaluation circuit365during a first clock cycle. The second clock cycle may then be used to begin evaluating the next primitive.

The two edge evaluation circuits360,365used over two cycles do not appreciably reduce performance of the GPU because the evaluation of relatively small primitives is in fact limited in speed by other stages in the raster pipeline and/or other units in the GPU. For example, the setup unit requires two clock cycles to setup each primitive. Therefore, edge evaluation of the primitives over two clock cycles does not add to processing latency because of the bottleneck at the setup unit. Other units, such as the shader, are also similar processing bottlenecks.

Furthermore, a big primitive may not need all four edges evaluated. In the case of large primitives, some edges will be far away from the tile being evaluated and the result of the evaluation will be trivially already known. In such cases, evaluation of two edges will be sufficient.

It is appreciated that embodiments of the present technology are described with reference to primitives having four edges. However, embodiments of the present technology can be applied -to primitives having any number of edges. For example, primitives having six edges may be processed by two edge evaluator circuits in three clock cycles.

Referring now toFIG. 4, a hardware implemented technique for evaluating edges of a primitive is shown. The method includes determining the number of edges of a primitive to be evaluated, at410. For example, a rectangular primitive510, typically used to draw lines, has four edges512-518that may need to be evaluated for a given tile520, as illustrated inFIG. 5. A triangular primitive610has three edges612-616that may need to be evaluated for a given tile620, as illustrated inFIG. 6. However, if the primitive is relatively large compared to the evaluation tile620, one or more of the edges may be trivially known. Therefore, as shown inFIG. 6, only two of the three edges612,616of the triangle primitive6010need to be evaluated. The third edge614of the triangular primitive610inFIG. 6is trivially known not to be present in any of the pixels of the evaluation tile620.

If three or more edges of a primitive need to be evaluated, a first edge is evaluated by a first edge evaluation circuit and a second edge is evaluated by a second edge evaluation circuit during a first clock cycle, at420. A third edge is evaluated by the first edge evaluation circuit and a fourth edge is evaluated by second edge evaluation circuit during a second clock cycle, at430. The technique then continues at410for each primitive to be evaluated.

If two or less edges of the primitive need to be evaluated, a first edge is evaluated by a first edge evaluation circuit and a second edge is evaluated by a second edge evaluation circuit during a first clock cycle, at440. The technique then continues at410for each primitive to be evaluated.

Referring now toFIG. 7, an exemplary computing device700for implementing embodiments of the present invention is shown. The computing device700may be a personal computer, server computer, client computer, laptop computer, game console, hand-held device, minicomputer, mainframe computer, distributed computer system, embedded computer, system on a chip, or the like. In addition to standard computers, the computing device may be used to implement car dashboards, kiosks, pachinko machines, slot machines, television sets, industrial controls, medical devices, wearable devices embedded in clothing, eyeglasses or wristbands, and other such applications. The computing device700includes one or more central processing units (-CPU)710, one or more graphics processing units (GPU)720, an input/output hub730, one or more computing device-readable media740,750, a display device760, and one or more other input/output (I/O) devices (not shown). The additional I/O devices may include a network adapter (e.g., Ethernet card), CD drive, DVD drive a keyboard, a pointing device, a speaker, a printer, cameras, biosensors, proximity sensors, chemical substance detectors, haptic sensor/effectors (touch/feeling devices), and/or the like.

The computing device-readable media740,750may be characterized as primary memory and secondary memory. Generally, the secondary memory, such as a magnetic and/or optical storage, provides for non-volatile storage of computer-readable instructions and data for use by the computing device700. For instance, a disk drive may store the operating system (OS) and applications and data. The primary memory, such as system memory and/or graphics memory750, provides for volatile storage of computer-readable instructions and data for use by the computing device700. For instance, the system memory may temporarily store a portion of the operating system and a portion of one or more applications and associated data that are currently used by the CPU710, GPU720and the like.

The computing device-readable media740,750, I/O devices760, and GPU720may be communicatively coupled to the processor710by the input/output hub730and one or more busses. The input/output hub730may be a simple hub or a chip set, such as a northbridge and southbridge. The input/output hub730provides for communication of data and instructions between the processor710and the computing device-readable media740,750, I/O devices760, and GPU720. In the case of a northbridge/southbridge chip set, the northbridge170provides for communication with the processors710,720and interaction with the system memory. The southbridge175provides for general input/output functions.

The GPU720may include a setup engine, a raster pipeline, a shading pipeline, a data write unit, and one or more other units, as illustrated and described with reference toFIG. 1. The raster pipeline of the GPU270includes an edge evaluator, as illustrated and described with reference toFIGS. 3 and 4. The edge evaluator determines the number of edges of a given primitive to be evaluated. The edge evaluator evaluates the first edge by a first edge evaluation circuit and the second edge by a second edge evaluation circuit during a first clock cycle. If three or more edges are to be evaluated, the edge evaluator also sequences evaluation, during a second clock cycle, of the third edge by the first edge evaluation circuit and if necessary the fourth edge by the second edge evaluation circuit.

Embodiments of the present technology advantageously reduce the gate count of the edge evaluation portion of the graphics processing unit and thus consumes less area on the integrated circuit die. The edge evaluator containing two edge evaluation circuits in accordance with embodiment of the present technology also consumes less power than conventional edge evaluators containing four edge evaluation circuits. Embodiments of the present technology also do not appreciably reduce performance of the graphics processing circuit because one or more other circuits in the graphics processing unit are dominant performance bottlenecks.