Semiconductor integrated circuit

In one embodiment, a semiconductor integrated circuit includes a first resistive-change element, a second resistive-change element and a first switching element. The first resistive-change element includes one end having a first polarity connected to a first power source. The first resistive-change element includes another end having a second polarity connected to an output node. The second resistive-change element includes one end having the second polarity connected to the output node. The first switching element includes a first terminal connected to another end of the second resistive-change element. The first switching element includes a second terminal connected to a second power source.

CROSS REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2010-34952, filed on Feb. 19, 2010, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a reconfigurable semiconductor integrated circuit represented by a field programmable gate array (FPGA), and more particularly to a memory circuit to hold wiring connection information and logic information.

BACKGROUND

A fundamental construction of an FPGA is composed of a configurable logic block (CLB) to realize optional logic information, a connection block (CB) to input and output between the CLB and wiring, and a switch block (SB) to switch over the connection of the wiring. In each of the blocks, the logic information and the wiring connection information are changed by values stored in configuration memories.

Recently, several nonvolatile resistive-change memories are proposed as the configuration memory. As these are formed in a wiring layer, it is possible to reduce a silicon area compared with an SRAM. Several kinds of the resistive-change memories are proposed, a bipolar type memory to program conduction and non-conduction in a direction to apply a voltage has a merit to control easily compared with a unipolar type in that it is not necessary to control the value of the voltage more finely.

When two memory elements are arranged in series, it is necessary to insert a selecting transistor in series with the two memory elements so as to prevent the current from flowing into another memory cell.

In the method to use the bipolar type memory as the configuration memory of the FPGA, there is a problem that to provide four power source voltages is necessary. In addition, as the two memories are directly connected between the wirings, there is another problem that current happens to flow into the device which is not programmed and then false writing happens.

In a circuit constitution inserted selecting transistors in series with the two memory elements such as a magnetic tunnel junction element, for example, there is a problem that a magneto resistance ratio of conduction and non-conduction of the element is small and it is difficult to use the circuit constitution directly for the configuration memory of the FPGA. In addition, as a memory array is supposed and a plurality of the memories are connected to one bit line, there is a problem that current happens to flow into the memory element of another cell and then the operation becomes unstable.

DETAILED DESCRIPTION

In one embodiment, a semiconductor integrated circuit includes a first resistive-change element, a second resistive-change element and a first switching element. The first resistive-change element includes one end having a first polarity connected to a first power source. The first resistive-change element includes another end having a second polarity connected to an output node. The second resistive-change element includes one end having the second polarity connected to the output node and another end. The first switching element includes a first terminal connected to another end of the second resistive-change element. The first switching element includes a second terminal connected to a second power source.

In another embodiment, a semiconductor integrated circuit includes a first resistive-change element, a second resistive-change element, a first switching element, a fifth switching element, a third resistive-change element, a fourth resistive-change element, a sixth switching element, a seventh switching element and a second inverting circuit. The first resistive-change element includes one end having a first polarity connected to a first power source. The first resistive-change element includes another end having a second polarity connected to a first output node. The second resistive-change element includes one end having the second polarity connected to the first output node. The first switching element includes a first terminal connected to another end of the second resistive-change element. The first switching element includes a second terminal connected to a second power source. The fifth switching element includes a first terminal connected to the first output node. The fifth switching element includes a second terminal connected to an output terminal. The third resistive-change element includes one end having the first polarity connected to a third power source. The third resistive-change element includes another end having the second polarity connected to a second output node. The fourth resistive-change element includes one end having a second polarity connected to the second output node. The sixth switching element includes a first terminal connected to another end of the fourth resistive-change element. The sixth switching element includes a second terminal connected to a fourth power source. The seventh switching element includes a first terminal connected to the second output node. The seventh switching element includes a second terminal connected to the output terminal. The second inverting circuit is connected to a control terminal of the fifth switching element and a control terminal of the seventh switching element.

Further, multiple embodiments will be hereinafter described with reference to the drawings. In the drawings, the same reference numerals denote the same or similar portions.

The first embodiment will be explained with reference toFIG. 1.FIG. 1is a circuit diagram showing a fundamental construction of a semiconductor integrated circuit of the first embodiment. In the drawing, a first resistive-change element101and a second resistive-change element102indicate a bipolar type resistive-change memory, and + and − indicate a polarity. For example, in case that a programming voltage is applied in a direction from + to −, the memory is programmed in a low resistance state, and in case that a programming voltage is applied in a direction from − to +, the memory is programmed in a high resistance state. In the following description, it is assumed that the first resistive-change element101and the second resistive-change element102are of the above-described polarity.

In the fundamental construction ofFIG. 1, the first resistive-change element101, the second resistive-change element102and a first switching element103are connected in series between a first power source105and a second power source106. In addition, a gate electrode of a second switching element104is connected to an output (connection) node108of the first resistive-change element101and the second resistive-change element102. The second switching element104is used as a switch to change over the wiring in an FPGA. InFIG. 1, the first switching element103and the second switching element104are shown both as N channel IGFETs (insulated gate field effect transistors), but without being limited to this, P channel IGFETs or micro-electro-mechanical switches may be used. Here, it is thought that the first resistive-change element101, the second resistive-change element102and the first switching element103compose a memory cell of a resistive-change memory. An IGFET is also called a MOSFET (metal insulated semiconductor field effect transistor) or a MISFET (metal oxide semiconductor field effect transistor).

Resistance states of the first resistive-change element101and the second resistive-change element102are mutually programmed in a complementary manner in a steady state. That is, they are programmed such that if the first resistive-change element101is in the high resistance state, the second resistive-change element102is in the low resistance state (called as a state1), and if the first resistive-change element101is in the low resistance state, the second resistive-change element102is in the high resistance state (called as a state2). For the reason, the first resistive-change element101and the second resistive-change element102are connected so that the polarities become mutually reverse in a direction from the first power source105to the second power source106. For the reason, it is necessary that the first resistive-change element101and the second resistive-change element102are bipolar type memories. In addition, the directions of the polarities are not limited to the combination of the directions inFIG. 1, but they may be connected such that the polarity of the first resistive-change element101becomes − + and the polarity of the second resistive-change element102becomes + − in the direction from the first power source105to the second power source106, for example.

In the case of operating the FPGA, the FPGA is operated in the state that the first switching element103is made conducting and a voltage is applied between the first power source105and the second power source106. For example, when a higher voltage source voltage Vddis given to the first power source105and a lower voltage source voltage Vssis given to the second power source106, at the output node108, in the case of the state1a voltage near the lower voltage source voltage Vssappears and in the case of the state2a voltage near the higher voltage source voltage Vddappears, respectively. The conduction and non-conduction of the second switching element104is controlled by the voltage values. As the transistor is driven by the voltage values of the output node108, it is necessary to greatly swing the voltage values of the output node108in the state1and in the state2. Thus, a resistance ratio of approximately two digits is required as the resistance ratio of the first resistive-change element101and the second resistive-change element102. As specific examples of the memory with a resistance ratio of two digits, memories decided by material such as, an ReRAM, an ion memory, a fuse/anti-fuse memory and a field effect memory, and mechanical switches such as, an MEMS switch and an NEMS switch are quoted.

In the case of operating the FPGA, any of the voltages of the first power source105and the second power source106may be the higher voltage source voltage, but it is preferable that in case that the first switching element103is an N channel IGFET the first power source105is made at a higher potential and the second power source106is made at a lower potential, and it is preferable that in case that the first switching element103is a P channel IGFET the first power source105is made at a lower potential and the second power source106is made at a higher potential.

Next, a method for writing data into the semiconductor integrated circuit of the embodiment will be described usingFIGS. 2,3.

Writing into the first resistive-change element101and the second resistive-change element102is performed by making the first switching element103conducting and giving a writing voltage Vprgbetween the first power source105and the second power source106. In addition, the value of the writing voltage Vprgis higher than a writing voltage into a single body of a memory.

A case of programming the two resistive-change elements from the state1to the state2as shown inFIG. 2is assumed, for example. This example corresponds to that the writing voltage Vprgis applied in the direction from the first power source105to the second power source106. In an early stage of writing shown inFIG. 2A, a voltage approximate to the writing voltage Vprgis applied to the first resistive-change element101of the high resistance state. For the reason, the first resistive-change element101is programmed into the low resistance state. In this stage, both the first resistive-change element101and the second resistive-change element102become in the low resistance states as shown inFIG. 2B, and the output node108becomes at a voltage of about a half of the writing voltage Vprg. Though a voltage of about a half of the writing voltage Vprgis applied to the second resistive-change element102, if the value is sufficient to program the single body of the resistive-change element, the second resistive-change element102is programmed into the high resistance state. Though a voltage of about a half of the writing voltage Vprgis similarly applied to the first resistive-change element101in this time, as the polarity is a reverse direction in contrast to a direction to be programmed into the high resistance state, the first resistive-change element101is not programmed. Thus, finally, the two resistive-change elements are changed into the state2as shown inFIG. 2C.

In the case of programming from the state2to the state1, it is enough that the writing voltage Vprgis applied in the direction from the second power source106to the first power source105as shown inFIG. 3. In an early stage of writing shown inFIG. 3A, a voltage approximate to the writing voltage Vprgis applied to the second resistive-change element102of the high resistance state. For the reason, the second resistive-change element102is programmed into the low resistance state. In this stage, both the first resistive-change element101and the second resistive-change element102become in the low resistance states as shown inFIG. 3B, and the output node108becomes at a voltage of about a half of the writing voltage Vprg. Though a voltage of about a half of the writing voltage Vprgis applied to the first resistive-change element101, if the value is sufficient to program the single body of the resistive-change element, the first resistive-change element101is programmed into the high resistance state. In this time, a voltage of about a half of the writing voltage is similarly applied to the second resistive-change element102, as the polarity is a reverse direction to a direction in contrast to be programmed into the high resistance state, the second resistive-change element102is not programmed. Thus, finally, the two resistive-change elements are changed into the state1as shown inFIG. 3C.

In addition, in case that the first switching element103is an N channel IGFET, and in case that the writing voltage Vprgis applied in the direction from the second power source106to the first power source105, it is necessary to conduct the first switching element103with attention to that a voltage drop is generated in accordance with a threshold voltage of the first switching element103. There are methods, such as, giving a higher voltage as the gate voltage, lowering the threshold value by giving a substrate bias, using a device with short channel length and large channel width, and giving a higher voltage as the writing voltage Vprg.

In case that the writing voltage Vprgis applied to the memory already in the state2in the direction from the first power source105to the second power source106, most of the voltage is applied to the second resistive-change element102of the high resistance state, but as the polarity is a reverse direction to a direction in contrast to be programmed into the low resistance state, the second resistive-change element102is not programmed, and the state2is kept. Conversely, in case that the writing voltage Vprgis applied to the memory in the state1in the direction from the second power source106to the first power source105, most of the voltage is applied to the first resistive-change element101of the high resistance state, but as the polarity is a reverse direction in contrast to a direction to be programmed into the low resistance state, the first resistive-change element101is not programmed, and the state1is kept. That is, it is possible to change the state by the direction of the programming voltage without attention to the present state of the memory.

As described above, in the semiconductor integrated circuit of the embodiment, as the first switching element103is provided in series with the resistive-change elements, it is possible to eliminate that the current flow into and to avoid false writing in the case of writing to the other memory cell, by making the first switching element103non-conducting. In addition, as the memory with a large resistance ratio is used, it is possible to make the voltage amplitude of the output node108high, and it is possible to control directly the conduction or non-conduction of the second switching element104. In addition, as the output node108is directly connected to the gate of the second switching element104, current does not flow into from the memory reading wire, and it is possible to avoid false writing. In addition, at the time of writing operation, the writing voltage Vprg that is a comparatively high voltage may happen to be applied to the gate of the second switching element104, if the programming time is a short time, there is no problem in reliability.

In case that a resistance value of the first resistive-change element101or the second resistive-change element102in the high resistance state is large, it is necessary to give attention to an off-resistance of the first switching element103. It is because, in case that the off-resistance is small, in other words, the off-leak current is large, the non-selected memory cell may possibly be falsely written.

FIG. 4shows relations between the writing voltage Vprg to be applied in the direction from the first power source105to the second power source106and the voltage to be applied to the two resistive-change elements, for a few cases of the off-resistances of the first switching element103, assuming that the resistance value of the resistive-change element in the high resistance state is 10 GΩ. Actually, as the leak current itself is a function of the writing voltage Vprg, it is necessary to consider the detail in accordance with to the switching elements to be used and the programming voltage. But if roughly the off-resistance of the switching element is about 1 GΩ, the high voltage may be applied to the resistive-change element, and the switching element becomes of no use, and it is found that about 10 GΩ is necessary as the off-resistance. That is, it is necessary to make the off-leak current not more than 100 pA.

In the case of writing into the memory cell, the relation between the resistance value of the resistive-change element and the transistor property of the first switching element is obtained from the condition that both the selected cell and the non-selected cell operate stably. It is assumed that a resistance of the resistive-change element in the high resistance state is Roff, a resistance of the resistive-change element in the low resistance state is Ronand an off-leak current of the first switching element103is Ioff. As most of a voltage due to the leak is applied to the memory in the high resistance state, it is necessary that the state of the memory is not rewritten in this time. Assuming that there is no problem if the voltage can be suppressed not more than Vprg/n using an arbitrary positive number n of not less than 1, the condition in this time can be written as

Generally, as the voltage necessary for changing from the high resistance to the low resistance is higher, it is thought good that n is about 2 to 3.

On the other hand, the case where the current is needed most is a case where both the first resistive-change element101and the second resistive-change element102become in the low resistance states as described in the above-described rewriting operation, and in this time, a voltage of about a half of the writing voltage Vprg is applied to each of the resistive-change elements. Assuming that an on-current of the first switching element103is Ion,

Ion>Vprg2⁢Ron(2)
is given as a condition for Ion.

From (1), (2), it is necessary that an on-off ratio of the first switching element103is

In addition, assuming that a sub threshold factor (a gate voltage necessary to raise the current by one digit) of the first switching element103is S, it is necessary that a threshold voltage Vth of the first switching element103satisfies the condition

In case that n=2, a resistance ratio of the memory is 6 digits, and S=60 mV/dec, for example, it is necessary that the threshold voltage Vthis made larger than 0.36 V. If the threshold voltage which is required in (4) is not realized by only the device design, it may be good that the threshold voltage is satisfied by applying a substrate bias.

In addition, as a matter of course, it is necessary that the threshold voltage Vthis smaller than the higher voltage source voltage Vddand the writing voltage Vprg as shown in an expression (5) below.
Vprg>Vdd>Vth(5)

The first switching element103is designed so as to satisfy the expressions (1) to (5).

With respect to the leak current, the leak current is larger in the case that the second power source106is made at the high potential and the writing voltage Vprg is applied than in the case that the first power source105is made at the high potential and the writing voltage Vprg is applied. This is because in the former case, as there is the voltage drop due to the first resistive-change element101and the second resistive-change element102, the voltage applied to the switching element is made smaller, on the other hand, in the latter case, the writing voltage Vprg is applied directly to the switching element. In the FPGA, it is expected that the wiring to make the second switching element104non-conducting is more than the wiring to make conducting. Therefore, in case that the first power source105is made at the high potential and the writing voltage Vprg is applied, if the second switching element104is made non-conducting, which become advantageous in power consumption. Though made into the state1in this time, this is of course changed by the polarity of the memory and the kind of the second switching element104.

Next, a device construction of the semiconductor integrated circuit of the embodiment and its manufacturing method will be described usingFIG. 5 to 11.

FIG. 5is a top view of the first resistive-change elements101, the second resistive-change elements102and the first switching elements103. In the drawing, the first resistive-change element101and the second resistive-change element102are shown by circle marks. One end of the first resistive-change element101and one end of the second resistive-change element102are connected by a second connection wiring layer111. Another end of the first resistive-change element101is connected to a first bit line (BL1)109that is the first power source, and another end of the second resistive-change element102is connected to a first activation region112that is a drain of the first switching element (transistor)103via a first connection wiring layer113. The activation region112and a gate electrode107form the first switching element (transistor)103. An end of the first activation region112at an opposite side across the gate electrode107is a source region, and as shown in the drawing, the source region is mutually connected to a source region of another switching element. A second bit line (BL2)110that is the second power source is connected to a source of the first switching element103via a contact.

FIG. 6Ais a sectional view at A-A inFIG. 5, andFIG. 6Bis a sectional view at B-B inFIG. 5. InFIG. 6A, a drain region103aof the first switching element103is connected to the second resistive-change element102through the first connection wiring layer113via a contact plug. The first connection wiring layer113and the first bit line109are arranged adjacent to the second bit line110. The second bit line110, the first connection wiring layer113and the first bit line109are formed by patterning the same layer as described later. The first resistive-change element101is arranged on the first bit line109. The first resistive-change element101is composed of a lower electrode, an element main body and an upper electrode in this order from the lower layer. On the other hand, the second resistive-change element102is arranged on the first connection wiring layer113. The second resistive-change element102is also composed of a lower electrode, an element main body and an upper electrode in this order from the lower layer in the same way as the first resistive-change element101. The upper electrodes of the first resistive-change element101and the second resistive-change element102are connected to the second connection wiring layer111. Though not shown, the second connection wiring layer111is connected to a gate electrode of the second switching element104.

InFIG. 6B, a source region103bof the first switching element103is connected to the second bit line110via a contact plug. The first bit lien109is arranged in the same layer as the first connection wiring layer110.

InFIG. 5, the four memory cells are shown, by making two contacts of the first switching element103at the second power source106side common in the two cells by the first activation region112, it is possible to reduce the cell area. In addition, by forming the first bit line109, the second bit line110and the first connection wiring layer113in the same layer and by wiring in the same direction, it is possible to reduce the cell area. The two resistive-change elements are arranged parallel in the direction of the gate electrode107of the first switching element103, and it is possible to arrange the resistive-change elements at the lower portion of the second connection wiring layer111. Accordingly, it is possible to realize the memory cell with the two wiring layers by laying out as shown inFIG. 5, so that it is possible to save the wiring resource.

In addition, in the drawing, the first resistive-change element101and the second resistive-change element102are respectively formed between the first bit line109and the second connection wiring layer111, and between the first connection wiring layer113and the second connection wiring layer111, but the arrangement is not necessarily limited to this. By using an optional conductive layer of an n-th layer and a conductive layer of an upper m-th layer, it may be possible to arrange the memory cell between the layers. In addition, the first connection wiring layer113and the lower electrode of the second resistive-change element102may be made of the same construction. In addition, the second connection wiring layer111and the upper electrode of the first resistive-change element101may be made of the same construction.

Next, a method for manufacturing the semiconductor integrated circuit shown inFIGS. 5,6will be described usingFIGS. 7 to 11. InFIGS. 7 to 11, A shows a cross sectional view at A-A and B shows a cross sectional view at B-B, respectively.

To begin with, as shown inFIG. 7, the first switching element103is formed at an element region on a semiconductor substrate. Then the semiconductor substrate is coated with an interlayer insulating film, and contact holes are opened on the source and drain of the first switching element103. After opening, while forming contact plugs to embed the contact holes by a method such as damascene method, a conductive layer is formed on the interlayer insulating layer.

Then, as shown inFIG. 8, the first bit line109, the second bit line110and the first connection wiring layer113are formed by patterning the conductive layer with a method such as spatter etching. The interlayer insulating layer is formed to embed among the first bit line109, the second bit line110and the first connection wiring layer113.

Next, as shown inFIG. 9, by laminating layers which will respectively become the lower electrodes, the element main bodies and the upper electrodes of the resistive-change elements in this order, and by etching processing into the element sizes, the first resistive-change element101and the second resistive-change element102are formed. By this process, to form films of the memory cell can be done at one time, so that it is possible to reduce the number of processes.

Then as shown inFIGS. 10,11, the first resistive-change element101and the second resistive-change element102are covered by an interlayer insulating layer, and the contact holes are opened to expose respectively the surfaces of the upper electrodes of the first resistive-change element101and the second resistive-change element102. After opening, while forming contact plugs to embed the contact holes by a method such as damascene method, a conductive layer is formed on the interlayer insulating layer. Then, by patterning the conductive layer with a method such as spatter etching, the second connection wiring layer111is formed.

Then, by connecting the second connection wiring layer111to the gate electrode (not shown) of the second switching element104, the semiconductor integrated circuit of the embodiment is completed.

FIG. 12shows another example of a cross section at A-A and a cross section B-B inFIG. 5. The difference from the construction inFIG. 6is that the widths of the upper electrodes of the first resistive-change element101and the second resistive-change element102are respectively the same as the widths of the element main bodies and the lower electrodes of the first resistive-change element101and the second resistive-change element102in the construction ofFIG. 6, on the other hand, the widths of the upper electrodes in the construction ofFIG. 12are respectively smaller than those of the element main bodies and the lower electrodes. With the construction ofFIG. 12, it is possible to suppress the leak current at the side face of the resistive-change element.

In addition, in the construction ofFIG. 12, the first resistive-change element101and the second resistive-change element102are respectively formed between the first bit line109and the second connection wiring layer111, and between the first connection wiring layer113and the second connection wiring layer111, in the same way as the construction ofFIG. 6, but the arrangement is not necessarily limited to this. By using an optional conductive layer of an n-th layer and a conductive layer of an upper m-th layer, it may be possible to arrange the memory cell between the layers. In addition, the first connection wiring layer113and the lower electrode of the second resistive-change element102may be made of the same construction. In addition, the second connection wiring layer111and the upper electrode of the first resistive-change element101may be made of the same construction.

Next, a manufacturing process of the semiconductor integrated circuit ofFIG. 12will be described usingFIGS. 13 to 18. InFIGS. 13 to 18, A shows a cross sectional view at A-A and B shows a cross sectional view at B-B, respectively.

To begin with, as shown inFIG. 13, the first switching element103is formed at the device region on the semiconductor substrate. Then the semiconductor substrate is coated with an interlayer insulating film, and contact holes are opened on the source and drain of the first switching element103. After opening, while forming contact plugs to embed the contact holes by a method such as damascene method, a conductive layer is formed on the interlayer insulating layer. Then, by patterning the conductive layer with a method such as spatter etching, the first bit line109, the second bit line110and the first connection wiring layer113are formed. And the interlayer insulating layer is formed to embed among the first bit line109, the second bit line110and the first connection wiring layer113.

Next, as shown inFIG. 14, layers are laminated which will become respectively the lower electrodes and the element main bodies of the resistive-change elements in this order, and are etching processed into the device sizes.

After etching processing, the lower electrodes and the element main bodies of the first resistive-change element101and the second resistive-change element102are coated with an interlayer insulating layer, and openings are formed to expose respectively the surfaces of the element main bodies of the first resistive-change element101and the second resistive-change element102. After forming openings, the materials of the upper electrodes are respectively deposited in the openings with a method such as spattering as shown inFIG. 15.

Then as shown inFIGS. 16,17, the first resistive-change element101and the second resistive-change element102are covered by an interlayer insulating layer, and the contact holes are opened to expose respectively the surfaces of the upper electrodes of the first resistive-change element101and the second resistive-change element102. After opening, while forming contact plugs to embed the contact holes by a method such as damascene method, a conductive layer is formed on the interlayer insulating layer. Then, by patterning the conductive layer with a method such as spatter etching, the second connection wiring layer111is formed.

Then, by connecting the second connection wiring layer111to the gate electrode (not shown) of the second switching element104, the semiconductor integrated circuit of the embodiment is completed.

As described above, in the manufacturing process ofFIGS. 13 to 17, there is a merit that the adjustment of the element size can be made and controlled easily by the sizes of the resistive-change elements.

A construction ofFIG. 18is made possible, as a modification of the element construction of the semiconductor integrated circuit shown inFIG. 5, by devising applying method of the writing voltage.FIG. 18shows a top view of the first resistive-change elements101, the second resistive-change elements102and the first switching elements103in case that the eight memory cells are arrange. The difference fromFIG. 5is that the gate electrode107of the first switching elements103is shared and the second bit line110is also shared among the memory cells arranged in the up and down direction ofFIG. 18. As the other is the same as the construction ofFIG. 5, the description will be omitted. By making the construction as this, it is possible to reduce the cell area. In the case of this construction, as the second bit line110is shared, the writing operation is performed by setting a potential of the first bit line109. That is, at the time of writing operation, a potential of the second bit line110is made at a common potential V0, and the potential to be given to the first bit line109is made at +Vprgor −Vprg, and writing is performed by changing the direction of the voltage. It is possible to reduce the cell area by sharing the gate electrode107and the second bit line110.

InFIG. 18, the second bit line110is shared, it is also possible that the first bit line109is shared and writing is performed by setting the potential of the second bit line110. In addition, if the gate electrode107is shared and the bit lines are not shared, it is possible to reduce the cell area without changing for setting of the writing operation.

The second embodiment will be explained with reference toFIG. 19.FIG. 19is a circuit diagram showing a construction of a semiconductor integrated circuit. An embodiment of a semiconductor integrated circuit shown inFIG. 19has a configuration that, in the fundamental construction of the semiconductor integrated circuit shown inFIG. 1, a gate of a third switching element120is connected to the output node108and the gate of the second switching element104, and a plurality of switching elements are connected to the memory cell. It is possible that the third switching element120is used as a switch to change over the wiring in the FPGA in the same way as the second switching element104, for example. In case that there are places where the conduction or non-conduction state of the switching elements become surely the same in the FPGA, it is possible to reduce the number of memory cells and to reduce the area by using the third switching element120without increasing the memory cell.

As another utilization method, it is also possible to use the third switching element120to confirm the states of the first resistive-change element101and the second resistive-change element102. At the time of programming, for example, as there is a time when the two of the first resistive-change element101and the second resistive-change element102become both in the low resistance state, and a larger current flows than in the steady state, it is possible to judge whether or not the writing is performed by measuring a current flowing between the first power source105and the second power source106. However, with respect to the two of the first resistive-change element101and the second resistive-change element102in the steady state, if the resistance state of one memory cell is in the high resistance state, the resistance state of the other memory is in the low resistance state in any of the state1or the state2, so that it is impossible to judge in which state the resistive-change elements are by only reading the current amount. In addition, even in case that some sort of error occurs and to program is not made properly, it is not possible to judge only by the current amount. The state of the memory can be confirmed by the conduction or non-conduction state of the second switching element104by a signal flowing between a source and a drain. However as a source drain is used as a signal line of the FPGA, an increase in wiring capacity is generated and a time when the FPGA can not be operated occurs by adding and operating a circuit for confirmation use, and as a result, a trouble occurs in the actual circuit operation.

By flowing a test signal between the source and drain of the third switching element120and by confirming the conduction or non-conduction state of the third switching element120, it is possible to analogize the conduction or non-conduction state of the second switching element104connected in the same way and the states of the first resistive-change element101and the second resistive-change element102. As the source •drain of the third switching element120is used as a wiring for test use disconnectedly from the signal line of the FPGA, there is a merit that load is not given to the FPGA operation. In addition, though it is necessary for the second switching element104to take a large size so as to reduce the signal delay in an optional circuit construction, as the third switching element120can read only the test signal it is enough that third switching element120is a small size, and an overhead of the area can be suppressed to be small. In addition, N channel or P channel is good. Accordingly, the third switching element120can be used in all the above-described embodiments.

The third embodiment will be explained with reference toFIG. 20.FIG. 20is a circuit diagram showing a semiconductor integrated circuit.FIG. 20is one of modifications of the fundamental construction shown inFIG. 1. The construction of the first resistive-change element101, the second resistive-change element102and the first switching element103is the same, the output node108between the two resistive-change elements is connected to a first inverting circuit130. An output of the first inverting circuit130is connected to a gate of a fourth switching element131. As a driving force may happen to drop depending on the resistance values of the first resistive-change element101and the second resistive-change element102, the first inverting circuit130is inserted as a buffer so as to change over the conduction and non-conduction of the fourth switching element131. In addition, in this case, the semiconductor integrated circuit is programmed so that the logic of the output node108is inverted. That is, the first resistive-change element101and the second resistive-change element102are programmed so that the output node108becomes a voltage near the lower voltage source voltage VSSin the case of making the fourth switching element131conducting and the output node108becomes a voltage near the higher voltage source voltage VDDin the case of making the fourth switching element131non-conducting.

The fourth embodiment will be explained with reference toFIG. 21.FIG. 21is a circuit diagram showing a semiconductor integrated circuit.FIG. 21is an embodiment to realize a multiplexer with the fundamental construction of the semiconductor integrated circuit shown inFIG. 1. The construction of the first resistive-change element101, the second resistive-change element102and the first switching element103is the same, the output node108between the two resistive-change elements is connected to the gate of the second switching element104and the first inverting circuit130. The output of the first inverting circuit130is connected to the gate of the fourth switching element131. A first input terminal140is connected to a source of the second switching element104, and a second input terminal141is connected to a source of the fourth switching element131, and both drains of the second switching element104and the fourth switching element131are connected to an output terminal142. At the time of the FPGA operation, in case that the output node108is a voltage near the higher voltage source voltage VDD, for example, as the second switching element104is ON and the fourth switching element131becomes OFF, the state of the first input terminal140is outputted to the output terminal142. Conversely, in case that the output node108is a voltage near the lower voltage source voltage VSS, as the second switching element104is OFF and the fourth switching element131becomes ON, the state of the second input terminal141is outputted to the output terminal142. As this, in case that to realize the complementary logic is wanted, this is dealt with by adding an inverting circuit to one of the two inputs. In addition, an example of a multiplexer with 2 inputs, 1 output is shown here, it is possible to realize a multiplexer with the optional number of inputs by repeating this.

The fifth embodiment will be explained with reference toFIG. 22.FIG. 22is a circuit diagram showing a semiconductor integrated circuit.FIG. 22is an embodiment to realize a look-up table. The construction of the first resistive-change element101, the second resistive-change element102and the first switching element103and the construction of a third resistive-change element201, a fourth resistive-change element202and a sixth switching element203are the same, the output node108and an output node218between the resistive-change elements are respectively connected to sources of a fifth switching element208and a seventh switching element209. An input terminal211is connected to a gate of the fifth switching element208and a second inverting circuit210, and an output side of the second inverting circuit210is connected to a gate of the seventh switching element209. Drains of the fifth switching element208and the seventh switching element209are both connected to an output terminal212. At the time of the FPGA operation, in case that the higher voltage source voltage VDDis inputted to the input terminal211, for example, as the fifth switching element208becomes ON and the seventh switching element209becomes OFF, a value of the output node108decided by the states of the first resistive-change element101and the second resistive-change element102is outputted to the output terminal212. Conversely, in case that the lower voltage source voltage VSSis inputted to the input terminal211, as the fifth switching element208becomes OFF and the seventh switching element209becomes ON, a value of the output node218decided by the states of the third resistive-change element201and the fourth resistive-change element202is outputted to the output terminal212. By programming properly values of the first resistive-change element101, the second resistive-change element102, the third resistive-change element201and the fourth resistive-change element202, an optional truth table with 1 input, 1 output can be realized. In addition, an example of a look-up table with 1 input, 1 output is shown here, it is possible to realize a look-up table with the optional number of inputs by repeating this.

The sixth embodiment will be explained with reference toFIG. 23.FIG. 23is a circuit diagram showing a semiconductor integrated circuit.FIG. 23is one of the modifications ofFIG. 22which realizes a look-up table. The construction of the first resistive-change element101, the second resistive-change element102and the first switching element103and the construction of the third resistive-change element201, the fourth resistive-change element202and the sixth switching element203are the same, the output node108and the output node218are respectively connected to a third inverting circuit301and a fourth inverting circuit302. An output side of the third inverting circuit301is connected to the source of the fifth switching element208and an output side of the fourth inverting circuit302is connected to the source of the seventh switching element209. The input terminal211is connected to the gate of the fifth switching element208and the second inverting circuit210, an output side of the second inverting circuit210is connected to the gate of the seventh switching circuit209. The drains of the fifth switching element208and the seventh switching element209are both connected to the output terminal212. As driving forces may happen to drop depending on the resistance values of the first resistive-change element101and the second resistive-change element102, and the resistance values of the third resistive-change element201and the fourth resistive-change element202, the third inverting circuit301and the fourth inverting circuit302are inserted as buffers, respectively, and are used for the output of the look-up table. At the time of the FPGA operation, in case that the higher voltage source voltage VDDis inputted to the input terminal211, for example, as the fifth switching element208becomes ON and the seventh switching element209becomes OFF, an inverted value of the output node108decided by the states of the first resistive-change element101and the second resistive-change element102is outputted to the output terminal212. Conversely, in case that the lower voltage source voltage VSSis inputted to the input terminal211, as the fifth switching element208becomes OFF and the seventh switching element209becomes ON, an inverted value of the output node218decided by the states of the third resistive-change element201and the fourth resistive-change element202is outputted to the output terminal212. By programming properly values of the first resistive-change element101, the second resistive-change element102, the third resistive-change element201and the fourth resistive-change element202, an optional truth table with 1 input, 1 output can be realized. As the third inverting circuit301and the fourth inverting circuit302are inserted as the buffers, the values of the output nodes108,208are made so as to become reverse numbers in the case of programming the memory device.

Hereinbefore, in the embodiment, it is possible to apply a resistive-change bipolar type memory to an FPGA without causing false writing or false operation. The embodiments described above are shown as one example, and it is possible to use a construction combined with the embodiments or a different construction having the similar function.