Integrated oscillator circuitry

Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a comparator stage, a resistor, a capacitor, and active switches arranged to provide a clock signal having a time period that is independent of a first source voltage. Independence may be achieved by using a second source voltage derived from the first source voltage as a fixed ratio.

BACKGROUND

Relaxation oscillators are known in the art.FIG. 1Ashows a conventional relaxation oscillator scheme100A that uses a Schmitt inverter110A to serve as a high gain hysteretic comparator, and as known, VIL, VIH(Voltage Input Low and Voltage Input High) of the Schmitt inverter110A are typically used to set trip points. However, VIL/VIHmay vary significantly with PVT (Process, Voltage, and Temperature), and hence, the conventional oscillator is less stable.

FIG. 1Bshows another conventional relaxation oscillator scheme100B that uses a fixed reference voltage Vref and a precision comparator110B. In some cases, use of a low power comparator may result in significant delay that may affect oscillator stability. Thus, the scheme100B may employ a relatively higher power design with use of the precision comparator110B and a PVT independent reference generator112. In this instance, some form of feedback FB may be employed via a feedback transistor T to correct the fixed reference voltage Vref or tune the precision comparator110B so as to improve frequency stability. However, the fixed reference voltage Vref is non-ideal and does not typically perform well by design for stability when the supply voltage Vdd varies. Therefore, the scheme100B may further use the feedback FB to compensate for variations in the reference voltage Vref so as to achieve better stability.

Another scheme (not shown) may refer to a differential resistor-capacitor (RC) network based relaxation oscillator that may be used to circumvent voltage dependence in a correct-by-design fashion. In some cases, the supply voltage (Vdd) is differentially sampled to cancel out variations. Reference generators are typically avoided by using a comparator's virtual ground as a reference to set a trip point. However, in practice, the comparator's virtual ground may move away from an ideal zero due to internal offsets, and thus, chopping may be used to average out any impact of offset to thereby improve stability. However, in this scheme, using differential sampling, a high power comparator, and a ring-oscillator increases power consumption, which should be avoided.

DETAILED DESCRIPTION

Various implementations described herein are directed to integrated oscillator circuitry. For instance, in some implementations, the integrated oscillator circuitry may refer to a supply voltage (Vdd) independent integrated resistor-capacitor (RC) oscillator using a reference voltage (Vref), such as a fixed supply-ratio voltage reference and/or duty-cycling of a precision comparator for low power operation. In some scenarios, low voltage synchronous digital systems may be configured to utilize ultra-low power clock sources that run without a crystal reference. This means some form of on-chip oscillator may be used, such as an RC oscillator, and thus, the various implementations described herein refer to RC oscillator topology and circuit.

Various implementations of integrated oscillator circuitry provided herein will now be described in more detail with reference toFIGS. 2-8.

FIG. 2illustrates a schematic diagram of integrated oscillator circuitry200in accordance with various implementations described herein. The integrated oscillator circuitry200may be referred to as an oscillator or oscillator circuit.

The oscillator circuitry200may include a first bus202configured to provide a source voltage Vdd (i.e., Vsource, supply voltage, input voltage, etc.). The first bus202may be referred to as a first voltage rail for supplying power (i.e., source voltage Vdd) to the oscillator circuitry200from an input voltage source. In various implementations, the input voltage source may include a battery source (i.e., Vbat or Vbattery), such as, e.g., a NiMH battery source or various other types of battery sources. Further, the oscillator circuitry200may include a second bus204configured to provide a ground voltage Vss (i.e., Vground, ground voltage, ground (GND), etc.). As such, the second bus204may be referred to as a second voltage rail for providing the ground voltage Vss or GND to the oscillator circuitry200. In some cases, the supply voltage Vdd may refer to a first power supply voltage, and the ground voltage Vss may refer to a second power supply voltage having a different potential than the first power supply voltage.

The oscillator circuitry200may include multiple stages including a first stage210and a second stage220. As shown inFIG. 2, the first and second stages210,220may be coupled between the first and second buses202,204in a parallel manner. However, alternative implementations may be used to achieve similar results.

The first stage210may include a comparator stage interposed between the first bus202for connection to the source voltage Vdd and the second bus204for connection to the ground voltage Vss. The comparator stage210may be configured to provide a clock signal CLK based on the source voltage Vdd and a fixed ratio of the source voltage via node Vc. Further, as shown inFIG. 2, the comparator stage210may include a voltage comparator212and a voltage divider214arranged to receive the source voltage Vdd as a first input signal, receive the fixed ratio of the source voltage at node Vc as a second input signal, and provide the clock signal CLK as an output signal based on the source voltage Vdd and the fixed ratio of the source voltage at node Vc. In various implementations, the voltage comparator212may be referred to as a comparator or a clock comparator. Further, as described in reference toFIG. 6below, the voltage divider214may be referred to as a switched capacitor network, circuit, or stage.

In some implementations, the voltage comparator212may be implemented with an operational amplifier (op amp) configured to receive the source voltage Vdd via a positive power supply input Vs+ and receive the ground voltage Vss via a negative power supply input Vs−. The voltage comparator212may also be configured to receive a voltage reference signal Vref from the voltage divider214via a non-inverting input V+, and receive the fixed ratio of the voltage source at node Vc from the second stage220via an inverting input V−. Further, the voltage comparator212may also be configured to output the clock signal CLK via an output Vout. In some other implementations, the voltage comparator212may be implemented or referred to as a precision comparator.

In some implementations, during operation, the voltage comparator212may be configured to sense when a voltage level of the capacitor C1is near or equal to or at least greater than the fixed ratio of the source voltage at node Vc and use the voltage level of the clock signal CLK to switch transistors M1, M2so as to allow charging of the capacitor C1to the source voltage Vdd. Further, in some other implementations, during operation, the voltage comparator212may be configured to sense when a voltage level of the capacitor C1is near or equal to the source voltage Vdd and use the voltage level of the clock signal CLK to switch the transistors M1, M2so as to allow discharging of the capacitor C1to the fixed ratio of the source voltage at node Vc.

The voltage divider214may be configured to receive the source voltage Vdd as an input signal, divide the source voltage Vdd by a predetermined amount, and then provide a portion (or part thereof) of the source voltage Vdd as a reference voltage Vref to the voltage comparator212based on the divided source voltage. Further, in some other cases, the clock signal CLK may be implemented as a feedback signal FB from the voltage comparator212to the voltage divider214. Therefore, this feedback signal FB may be utilized by the voltage divider214to adjust, regulate, or maintain the reference voltage Vref to near or equal to the divided source voltage, such as, e.g., about one-third (⅓) of the source voltage Vdd.

The second stage220may include a resistor-capacitor (RC) stage interposed between the first bus202for connection to the source voltage Vdd and the second bus204for connection to the ground voltage Vss. The RC stage220may be referred to as a relaxation circuit or stage. The RC stage220may include a resistor R1, the capacitor C1, and the multiple transistors M1, M2arranged to provide the fixed ratio of the source voltage at node Vc by switching between charging and discharging of the capacitor C1through the resistor R1based on a voltage level of the clock signal CLK provided by the comparator stage210. In some implementations, the resistor R1and capacitor C1may be arranged in parallel. Further, the multiple transistors M1, M2may include a first transistor M1and a second transistor M2, and as shown inFIG. 2, the resistor R1and the capacitor C1may be disposed between the first and second transistors M1, M2.

In some cases, when the voltage level of the clock signal CLK is near or equal to the fixed ratio of the source voltage at node Vc, the transistors M1, M2may be configured to switch to charge the capacitor C1to the source voltage Vdd. In some other cases, when the voltage level of the clock signal CLK is near or equal to the source voltage Vdd, the transistors M1, M2may be configured to switch to discharge the capacitor C1to the fixed ratio of the source voltage at node Vc.

Further, in some implementations, the RC stage220may be configured to provide a resistor-capacitor relaxation phase during discharging of the capacitor C1. For instance, during the resistor-capacitor relaxation phase, the RC stage220may be configured to regulate discharging of the capacitor C1so as to assist the comparator stage210with providing the clock signal CLK as an output signal that is independent of the source voltage Vdd.

In various implementations, the first bus202may be configured to provide a source voltage Vdd, and the reference voltage Vref may be within a range of approximately one-third (⅓) of the source voltage Vdd, As described herein, each of the stages may utilize one or more circuit components that may be configured for operating with one or more of the first and second power supply voltages.

In some implementations, the first and second transistors M1, M2may include complementary transistors. For instance, the first and second transistors M1, M2may include metal-oxide-semiconductor (MOS) transistors, and the first transistor M1may include a p-type MOS (PMOS) transistor, and the second transistor M2may include an n-type MOS (NMOS) transistor. In other implementations, the placement of the first and second transistors M1, M2may be reversed, and the resistor R1, the capacitor C1, and the first and second transistors M1, M2may be arranged to perform similar functionality as described herein in reference to the RC stage220.

In accordance with various implementations described herein,FIG. 2refers to a Vdd independent RC oscillator configured to achieve Vdd independence by using a reference that is a fixed ratio of Vdd. Further, the fixed ratio of Vdd is obtained from the RC stage220and is PVT independent.

In some implementations, the oscillator circuitry200ofFIG. 2may operate in a manner as follows. With CLK=0 apriori, Vc charges rapidly to Vdd. The comparator210senses Vc>Vref, and CLK is pulled high. In some cases, the CLK (0→1) delay may be sufficient for Vc to charge to Vdd (when M1is sized accordingly). Once CLK is high, the RC relaxation phase may start. As Vc discharges and hits Vc=Vdd/3, CLK is pulled low by the comparator210. This process repeats. Further, the voltage divider or switched capacitor stage214may be self-clocked.

FIG. 3illustrates a schematic diagram of integrated oscillator circuitry300in accordance with various implementations described herein. As shown inFIG. 3, the integrated oscillator circuitry300may be implemented with multiple stages may be referred to as an oscillator or oscillator circuit.

In one implementation, the oscillator circuitry300ofFIG. 3may include the oscillator circuitry200ofFIG. 2with incorporation of one or more additional devices or components, including, e.g., a low-power, low-precision coarse comparator X1, a Schmitt trigger X2, and a third transistor M3provided in the comparator stage210. As shown inFIG. 3, the third transistor M3may be disposed between the first bus202and the positive power supply input Vs+ of the voltage comparator212(X0) so as to provide the voltage source Vdd to the positive power supply input Vs+ when activated. The third transistor M3may include a PMOS transistor. The coarse comparator X1may be disposed between the non-inverting input V+ of the voltage comparator212(X0) and a gate of the third transistor M3. The Schmitt trigger X2may be coupled to the output Vout of the voltage comparator212(X0). Further, an output of the coarse comparator X1may be coupled to the Schmitt trigger X2.

In some cases, the oscillator circuitry300ofFIG. 3may be configured to implement the precision voltage comparator212(X0) as a duty-cycled comparator for low power operation. For instance, observing that a comparison may only be necessary when Vc is near or close to Vref, duty-cycling may be applied to the voltage comparator212(X0) for providing improved precision and low-power operation. In contrast, a coarse low-power comparator may be used to activate the voltage comparator212(X0) just-in-time for precise comparison.

In some implementations, the oscillator circuitry300ofFIG. 3may operate in a manner as follows. The coarse comparator X1may be used to perform a coarse comparison. When Vc>VILof the first coarse comparator X1, the voltage comparator212(X0) may be power gated, e.g., with the third transistor M3. The voltage comparator212(X0) may only be turned on for VIL=>Vc=>Vref. In some cases, VILvariation with PVT may affect a duty-cycle ratio, and hence, only power may be affected and not stability of the oscillator circuit300. Further, VILof the coarse comparator X1may be designed to be greater than Vref across PVT. Still further, an output clamp may be provided for the duration when the voltage comparator212(X0) is power gated due to its output Vout being tri-stated. In this instance, the Schmitt trigger X2may be disposed in-line with the output Vout of the voltage comparator212(X0) to provide an output clamp.

As shown inFIG. 3, Vcdig refers to a power gating signal provided from the coarse comparator X1to the gate of the third transistor M3, and cmp refers to the output Vout of the voltage comparator212(X0). In some cases, cmp may be invalid for a duration when Vcdig is high. Further, CLK may be clamped to Vdd during this phase but allowed to transition when Vc=VDD/3. In this instance, the timing is independent of Vdd. Practically, however, a race may exist between cmp rising and Vcdig, and cmp may be clamped to a correct state before switching off the voltage comparator (X0).

FIG. 4illustrates a schematic diagram of integrated oscillator circuitry400in accordance with various implementations described herein. As shown inFIG. 4, the integrated oscillator circuitry400may be implemented with multiple stages may be referred to as an oscillator or oscillator circuit.

In one implementation, the oscillator circuitry400ofFIG. 4may include the oscillator circuitry300ofFIG. 3with incorporation of one or more additional devices or components, including, e.g., a fourth transistor M4and a plurality of logic devices440,442,444,446,448,450provided in the comparator stage210. As shown inFIG. 4, the fourth transistor M4may be disposed between the first bus202and the output Vout (Qcmp) of the voltage comparator212(X0) so as to provide the voltage source Vdd to the output Vout (Qcmp) when activated. The fourth transistor M4may include a PMOS transistor. In some cases, a second capacitor C2may be coupled between the inverting input Vs− of the voltage comparator212(X0) and the second bus204(Vss). In some cases, the coarse comparator X1may be implemented as a Schmitt trigger. As such, in some implementations, the oscillator circuitry400ofFIG. 4may include a first Schmitt trigger X1and a second Schmitt trigger X2.

Further, the oscillator circuitry400may include an RS latch416having NAND gates442,444. The output of the first Schmitt trigger X1may be coupled to a gate of the fourth transistor M4, an input of an inverter450, and an input of a first NAND gate442. The inverter450may be coupled and disposed between an output of the first Schmitt trigger X1and the gate of the third transistor M3. The output of the second Schmitt trigger X2may be coupled to an input of an inverter440, and an output of the inverter440may be coupled to an input of a second NAND gate444. The output of the first NAND gate442(Q) may be coupled to another input of the second NAND gate444, and similarly, the output of the second NAND gate444may be coupled to another input of the first NAND gate442. The output of the first NAND gate442(Q) may be coupled to an input of an inverter446, an output of the inverter446may be coupled to an input of an inverter448, and an output of the inverter448may be coupled to the gates of the first and second transistors M1, M2of the RC stage220. As shown, the output of the second NAND gate444may be configured to provide the clock signal CLK and the feedback signal FB to the voltage divider214.

In some implementations, the voltage divider214may use MOS capacitors (e.g., as shown inFIG. 6), and the second capacitor C2may be selected to avoid switched capacitor (SC) ripple that may affect stability. The RS latch416may be employed to ensure the CLK set and reset is dictated by Vc and cmp (Vout) respectively avoiding a race. The inverters446,448following the RS latch416may function to provide sufficient delay so that Vc reaches Vdd although the first Schmitt trigger X1initiates a reset of the RS latch416as soon as Vc hits VIHof the first Schmitt trigger X1.FIG. 5below shows one implementation of an internal circuitry of the first Schmitt trigger X1, which may be a low power variant of a conventional Schmitt trigger. The design of the first Schmitt trigger X1inFIG. 5may limit short-circuit current through the first Schmitt trigger X1, and the inverters446,448switch due to leakage currents through mp1or mn1.

FIG. 5illustrates a schematic diagram of circuitry500for implementing the first Schmitt trigger X1of the oscillator circuitry400ofFIG. 4in accordance with various implementations described herein.

As shown inFIG. 5, the circuitry500may include multiple PMOS and NMOS transistors mp1, mp2, mp3, mn1, mn2, mn3arranged to implement the first Schmitt trigger X1ofFIG. 4. For instance, a first PMOS transistor mp1may be coupled between Vdd and second and third PMOS transistors mp2, mp3, and a first NMOS transistor mn1may be coupled between second and third NMOS transistors mn2, mn3and Vss. An input Vin of the first Schmitt trigger X1may be coupled to a gate of the second PMOS transistor mp2and a gate of the second NMOS transistor mn2. An output Vf of the first Schmitt trigger X1may be coupled to a gate of the first PMOS transistor mp1and a gate of the first NMOS transistor mn1, and the output Vf may also be coupled between the third PMOS transistor mp3and the third NMOS transistor mn3. Further, gates of the third PMOS transistor mp3and the third NMOS transistor mn3may be coupled between the second PMOS transistor mp2and the second NMOS transistor mn2.

FIG. 6illustrates a schematic diagram of circuitry600for implementing the voltage divider214in the oscillator circuitry400ofFIG. 4in accordance with various implementations described herein.

As shown inFIG. 6, the circuitry600may refer to a switched capacitor stage and may include multiple switches Øp, Øn and multiple capacitors C11, C12arranged to implement the voltage divider214in the oscillator circuitry400ofFIGS. 2, 3, and/or4. The switched capacitor stage214may be referred to as a voltage divider, such as, e.g., in some implementations, a divide-by-3 (BY3) voltage divider. In some cases, the switches Øp, Øn may be implemented with PMOS and NMOS transistors. A first n-type switch Øn1may be coupled between Vdd and a first p-type switch Øp1. A first p-type switch Øp1may be coupled between the first n-type switch Øn1and a second p-type switch Øp2. A terminal of a first capacitor C11may be coupled to a node between the first n-type switch Øn1and the first p-type switch Øp1, and another terminal of the first capacitor C11may be coupled to a third p-type switch Øp3. A second n-type switch Øn2may be coupled to a node between the first and second p-types switches Øp1, Øp2and further to the third p-type switch Øp3. The second n-type switch Øn2is coupled in parallel with the first capacitor C11. The third p-type switch Øp3is coupled between the first capacitor C11and Vss. A terminal of a second capacitor C12may be coupled to the node between the first and second p-types switches Øp1, Øp2, and another terminal of the second capacitor C12may be coupled to a fourth p-type switch Øp4. A third n-type switch Øn3may be coupled between the second p-type switch Øp2and a node between the second capacitor C12and the fourth p-type switch Øp4. The fourth p-type switch Øp4may be coupled between the second capacitor C12and Vss.

FIG. 7illustrates a schematic diagram of integrated oscillator circuitry700in accordance with various implementations described herein. As shown inFIG. 7, the integrated oscillator circuitry700may be implemented with multiple stages may be referred to as an oscillator or oscillator circuit. In some cases, a common issue with chopping may refer to error introduced by clock-injection. This design is robust to clock-injection noise as the comparator212may be turned off when chopping switches fire.

In one implementation, the oscillator circuitry700ofFIG. 7may include the oscillator circuitry400ofFIG. 4with incorporation of one or more additional devices or components, including, e.g., another clock divider458and the logic devices440,446,448, which may be implemented as Schmitt triggers. The clock divider458may be a flip-flop that may be used as a clock signal divider configured to provide a clock signal divided by 2 (i.e., CLK/2). As shown inFIG. 7, the clock divider458may be disposed between the output of the second NAND gate444and the output Vout (Qcmp) of the comparator or clock comparator212(X0). Further, the clock divider458may be disposed between the output of the second NAND gate444and across the inputs Vs+, Vs− of the clock comparator212(X0). In some cases, as shown inFIG. 7, the fourth transistor M4may be removed.

In some implementations, the oscillator circuitry700may be configured with chopping to cancel comparator offset. InFIG. 7, chopping may be employed in the oscillator circuitry700to convert period jitter to duty-cycle jitter to improve stability. The absence of clock CLK for the SC reference may introduce start-up delay, which may be undesirable in certain applications. This may be overcome by having a coarse start-up oscillator that may be disabled after oscillations kick-in. Further, self-clocking may be achieved using a clock derived from a divided version of the main clock so as to trade-off frequency stability for power. In some cases, an extension to the scheme described here may implement Vref>Vdd/2.

FIG. 8illustrates a process flow diagram of a method for providing an oscillator in accordance with various implementations described herein.

It should be understood that while method800indicates a particular order of execution of operations, in some examples, certain portions of the operations might be executed in a different order, and on different systems. In some other examples, one or more additional operations and/or steps may be added to method800. Similarly, some operations and/or steps may be omitted. In one implementation, steps810-850below are described with reference toFIG. 2. However, in various other implementations, steps810-850below may be applied to any one ofFIGS. 3-7.

At block810, method800may provide a source voltage. The source voltage may refer to an input voltage, such as e.g., Vdd or Vsource. At block820, method800may provide a fixed ratio (or portion) of the source voltage based on switching between charging and discharging of a capacitor through a resistor. At block830, method800may generate or provide a clock signal based on the source voltage and the fixed ratio of the source voltage. Further, at block840, method800may use the clock signal to switch complementary transistors from a first state to a second state to charge the capacitor to the source voltage when a voltage level of the clock signal is near or equal to the fixed ratio of the source voltage. At block850, method800may use the clock signal to switch the complementary transistors from the second state to the first state to discharge the capacitor to the fixed ratio of the source voltage when the voltage level of the clock signal is near or equal to the input voltage.

In some implementations, method800may include dividing the source voltage by a predetermined amount, providing a reference voltage based on the divided source voltage, and generating the clock signal based on the source voltage, the reference voltage, and the fixed ratio of the source voltage. The predetermined amount may be three (3). Method800may include arranging the resistor and the capacitor in parallel, and method800may include disposing the resistor and capacitor between the complementary transistors. Further, method800may include arranging the resistor, the capacitor, and the complementary transistors to provide a resistor-capacitor relaxation phase during discharging of the capacitor. In some cases, during the resistor-capacitor relaxation phase, discharge of the capacitor is regulated so as to assist with providing the clock signal as an output that is independent of the input voltage.

FIGS. 9A-9Cillustrate various other diagrams of integrated oscillator circuitry in accordance with various implementations described herein. In particular,FIG. 9Aillustrates integrated oscillator circuitry900A having a control block or circuit902,FIG. 9Billustrates integrated oscillator circuitry900B having a delay block or circuit912, andFIG. 9Cillustrates integrated oscillator circuitry900C having a conditioning block or circuit922. As shown, the integrated oscillator circuitry900A,900B,900C may be variant implementations of the integrated oscillator circuitry300ofFIG. 3, where similar components have similar functionality.

As shown inFIG. 9A, the control block902may be configured to receive one or more input signals, such as, e.g., the clock signal CLK and the power gating signal Vcdig provided from the coarse comparator X1. Further, as shown inFIG. 9A, the control block902may be configured to provide control signals to the voltage comparator212(XO), the voltage divider214, and/or a resistor-capacitor (RC) block904. The RC block904may include the resistor R1and the capacitor C1.

The coarse comparator output from X1may be less independent of VDD and temperature when compared to the clock signal CLK. For instance, the output from X1may include a high-voltage Vcdig (VCDIG_HV) and a low-voltage Vcdig (VCDIG_LV) that are coarse comparator outputs having off-times Thvand Tlvat high and low voltages, respectively. The clock signal CLK, however, may have a VDD independent period. This relative variation may allow the power gating signal Vcdig to be used as a pulse-width-modulated signal with the pulse width representing a combination effect of voltage and temperature. Thus, in some cases, the control block902may be configured to use this information to improve stability or reduce power of the oscillator circuitry900A.

Therefore, in various implementations, the integrated oscillator circuitry900A ofFIG. 9Amay refer to a scheme to use the control block902to control the behaviour of one or more of the voltage comparator212(X0), the voltage divider214, and/or the second stage220(e.g., via RC block904) using the power gating signal Vcdig. In these instances, the power gating signal Vcdig may appear as a pulse-width-modulated signal with an oscillator frequency as a carrier and a supply voltage and/or temperature as a modulation source. Thus, the power gating signal Vcdig may be representative of supply and/or temperature, and the circuit behaviour may be modified using the power gating signal Vcdig to improve performance.

As shown inFIG. 9B, the delay block912may be implemented to replace the coarse comparator X1. In this instance, as shown, the delay block912may be disposed between the non-inverting input V+ of the voltage comparator212(X0) and the gate of the third transistor M3. The integrated oscillator circuitry900B may be configured to use a coarse delay line from the delay block912in lieu of the coarse comparator X1. In some implementations, the coarse delay line may be at a lower power than a coarse voltage comparator (e.g., leakage controlled delay). With use of the delay block912, delay across the voltage and temperature range of interest may be tuned, e.g., such that a period of timing delay Tdelayis less than a period of the clock signal CLK. In this instance, the delay may be initiated by a rising edge of the clock signal CLK. In some implementations, at low voltage, the timing delay Tdelaymay be longer, and at higher voltage, the timing delay Tdelaymay be shorter. However, in some other implementations, as long as the coarse comparator X1is able to power-up the precision comparator212(X0) in-time, the period of the clock signal CLK may remain unaffected.

Therefore, in various implementations, the integrated oscillator circuitry900B ofFIG. 9Bmay refer to a scheme where the coarse comparator X1inFIG. 3is replaced with a resettable delay element, such as e.g., the delay block912. In this instance, the delay block912may provide a delay time that is less than an oscillation time period, and the delay time may be reset by the rising edge of the clock signal CLK.

As shown inFIG. 9C, the conditioning block922may be disposed between the output of the Schmitt trigger X2and the voltage divider214. Thus, the conditioning block922may be configured to receive the clock signal CLK, e.g., as output from the Schmitt trigger X2. In this instance, as shown, the conditioning block922is disposed on the feedback path to ensure that the integrated oscillator circuitry900C remains functional across (PVT) corners. In various implementations, the conditioning block922may be configured as any of, but not limited to, non-overlapping clock generators, level-shifters, clock gating circuits, filters, dividers, and/or similar circuits.

Therefore, in various implementations, the integrated oscillator circuitry900C ofFIG. 9Cmay refer to using the conditioning block922on the clock signal CLK line provided to the voltage divider214. In various implementations, the conditioning block922may be configured to modify the nature of the clock signal CLK. For instance, one or more non-overlapping clock generators may be configured to split the feedback signal (i.e., the clock signal CLK) provided as output from the Schmitt trigger X2.

Described herein are various implementations of an integrated circuit. In some implementations, the integrated circuit may include a comparator stage, a resistor, a capacitor, and active switches arranged to provide a clock signal having a time period that is independent of a first source voltage. Independence may be achieved by using a second source voltage derived from the first source voltage as a fixed ratio.

Described herein are various implementations of an oscillator. In some implementations, the oscillator may include a voltage divider configured to divide a source voltage by a predetermined amount and provide a reference voltage based on the divided input voltage. The oscillator may include a capacitor relaxation circuit having a resistor, a capacitor, a first transistor, and a second transistor arranged to provide a fixed ratio of the input voltage by switching between charging and discharging of the capacitor through the resistor. The oscillator may include a voltage comparator configured to receive the reference voltage as a first input, receive the fixed ratio of the input voltage as a second input, and provide a clock signal as an output based on the first and second inputs.

Described herein are various implementations of a method for providing a source voltage, providing a fixed ratio of the source voltage based on switching between charging and discharging of a capacitor through a resistor, and generating a clock signal based on the source voltage and the fixed ratio of the source voltage. The method may include using the clock signal to switch complementary transistors from a first state to a second state to charge the capacitor to the source voltage when a voltage level of the clock signal is near or equal to the fixed ratio of the source voltage. The method may include using the clock signal to switch the complementary transistors from the second state to the first state to discharge the capacitor to the fixed ratio of the source voltage when the voltage level of the clock signal is near or equal to the input voltage.

The discussion provided herein is directed to certain specific implementations. It should be understood that the discussion provided herein is provided for the purpose of enabling a person with ordinary skill in the art to make and use any subject matter defined herein by the subject matter of the claims.

It should be intended that the subject matter of the claims not be limited to the implementations and illustrations provided herein, but include modified forms of those implementations including portions of implementations and combinations of elements of different implementations in accordance with the claims. It should be appreciated that in the development of any such implementation, as in any engineering or design project, numerous implementation-specific decisions should be made to achieve a developers' specific goals, such as compliance with system-related and business related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort may be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having benefit of this disclosure.

Reference has been made in detail to various implementations, examples of which are illustrated in the accompanying drawings and figures. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the disclosure provided herein. However, the disclosure provided herein may be practiced without these specific details. In some other instances, well-known methods, procedures, components, circuits and networks have not been described in detail so as not to unnecessarily obscure details of the embodiments.

While the foregoing is directed to implementations of various techniques described herein, other and further implementations may be devised in accordance with the disclosure herein, which may be determined by the claims that follow.