SEMICONDUCTOR DEVICE

A semiconductor device comprises a first semiconductor structure, a second semiconductor structure located on the first semiconductor structure, and an active layer located between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure has a first conductivity type, and includes a plurality of first layers and a plurality of second layers alternately stacked. The second semiconductor structure has a second conductivity type opposite to the first conductivity type. The plurality of first layers and the plurality of second layers include indium and phosphorus, and the plurality of first layers and the plurality of second layers respectively have a first indium atomic percentage and a second indium atomic percentage. The second indium atomic percentage is different from the first indium atomic percentage.

CROSS REFERENCE TO RELATED APPLICATION

This application claims the right of priority based on TW Application Serial No. 111133942, filed on Sep. 7, 2022, and the content of which is hereby incorporated by reference in its entirety.

TECHNICAL FIELD

The disclosure relates to a semiconductor device, and particularly to a semiconductor light-emitting device.

Description of Background Art

Semiconductor devices can be applied to a wide range of applications. Research and development of related materials have been continuously carried out. For example, a group III-V semiconductor material containing a group III element and a group V element may be applied to various optoelectronic semiconductor devices, such as light-emitting diodes (LEDs), laser diodes (LDs), photoelectric detectors, solar cells or power devices (such as switches or rectifiers). These optoelectronic semiconductor devices can be applied in various fields, such as illumination, medical care, display, communication, sensing, or power supply system. For example, in semiconductor light-emitting devices, LEDs have low energy consumption, rapid response, small volume and long operating lifetime, thus are widely used.

SUMMARY OF THE DISCLOSURE

The present disclosure provides a semiconductor device. The semiconductor device comprises a first semiconductor structure, a second semiconductor structure located on the first semiconductor structure, and an active layer located between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure has a first conductivity type, and includes a plurality of first layers and a plurality of second layers alternately stacked. The second semiconductor structure has a second conductivity type opposite to the first conductivity type. The plurality of first layers and the plurality of second layers include indium and phosphorus, and the plurality of first layers and the plurality of second layers respectively have a first indium atomic percentage and a second indium atomic percentage. The second indium atomic percentage is different from the first indium atomic percentage.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings hereafter. The following embodiments are given by way of illustration with Cartesian Coordinates (X, Y, Z axes) to help those skilled in the art fully understand the spirit of the present disclosure. Hence, it should be noted that the present disclosure is not limited to the embodiments herein and can be realized in various forms. Further, the drawings are not precise scale and components may be exaggerated in view of width, height, length, etc. Herein, the similar or identical reference numerals will denote the similar or identical components throughout the drawings. In the embodiments of the present disclosure, if not described otherwise, the term “horizontal” means any value or vector along X-axis, Y-axis or on X-Y plane. The term “vertical” means any value or vector along Z-axis, and terms such as “below”, “above”, “under”, “on”, “top” and “bottom” may be used to describe special relationships along Z-axis between different devices or elements. The term “corresponding” may be used to describe different elements are overlapped horizontally (on X-Y plane). The term “coplanar” may be used to describe surfaces of different elements are vertically on the same level.

The semiconductor device of the present disclosure can be light-emitting device (such as light-emitting diode or laser diode) or light absorption device (such as photo-detector). Qualitative or quantitative analysis of the composition and/or dopant contained in each layer of the semiconductor device of the present disclosure may be conducted by any suitable method, for example, a secondary ion mass spectrometer (SIMS). A thickness of each layer may be obtained by any suitable method, such as a transmission electron microscopy (TEM) or a scanning electron microscope (SEM).

In addition, if not otherwise specified, a description similar to “a first layer/structure is on or under a second layer/structure” may include an embodiment in which the first layer/structure directly (or physically) contacts the second layer/structure, and may also include an embodiment in which another structure is provided between the first layer/structure and the second layer/structure, such that the first layer/structure and the second layer/structure do not directly contact each other. Furthermore, it should be realized that a positional relationship of a layer/structure may be altered when being observed in different orientations.

FIG.1shows a schematic cross-sectional view of a semiconductor device10A according to one embodiment of the present disclosure. The semiconductor device10A includes a first semiconductor structure100, a second semiconductor structure102located on the first semiconductor structure100, and an active structure104located between the first semiconductor structure100and the second semiconductor structure102. The active structure104includes an active layer104a. In one embodiment, the active structure104can further include a first confinement layer104band a second confinement layer104crespectively located at two sides of the active layer104a. The first semiconductor structure100has a first conductivity type, and the second semiconductor structure102has a second conductivity type opposite to the first conductivity type. For example, the first semiconductor structure100and the second semiconductor structure102can respectively be n-type semiconductor and p-type semiconductor, or p-type semiconductor and n-type semiconductor. The n-type semiconductor and the p-type semiconductor can be formed by doping dopants into an intrinsic semiconductor. In one embodiment, the n-type semiconductor may be, for example, a semiconductor doped with tellurium (Te) or silicon (Si), and the p-type semiconductor may be, for example, a semiconductor doped with carbon (C), zinc (Zn) or magnesium (Mg). As shown inFIG.1, the semiconductor device10A can optionally include a base108under the first semiconductor structure100, the second semiconductor structure102and the active structure104. In one embodiment, the base108connects the first semiconductor structure100.

The base108can include conductive material or insulating material. The conductive material can include gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), gallium phosphide (GaP), zinc oxide (ZnO), gallium nitride (GaN), aluminum nitride (AlN), germanium (Ge) or silicon (Si). The insulating materials can include sapphire. In the embodiment shown inFIG.1, the base108is a growth substrate. In other embodiments, the base108can be a bonding substrate instead of the growth substrate, which is bonded to the first semiconductor structure100through a bonding structure (not shown).

The first semiconductor structure100, the second semiconductor structure102and the active structure104can include same group of III-V compound semiconductor material. The III-V compound semiconductor material can include binary, ternary or quaternary III-V compound semiconductors, such as AlInGaAs series, AlInGaP series, AlInGaN series or InGaAsP series. The AlInGaAs series can be represented by (Alx1In(1-x1))1-x2Gax2As, wherein 0≤x1, x2≤1. The AlInGaP series can be represented by (Aly1In(1-y1))1-y2Gay2P, wherein 0≤y1, y2≤1. The AlInGaN series can be represented by (Alz1In(1-z1))1-z2Gaz2N, wherein 0≤z1, z2≤1. The InGaAsP series can be represented by Inz3Ga1-z3Asz4P1-z4, wherein 0≤z3, z4≤1.

The semiconductor device10A can include double heterostructure (DH), double-side double heterostructure (DDH) or multiple quantum wells structure (MQW). For example, the active layer104acan include a plurality of barrier layers (not shown) and a plurality of well layers (not shown) that are alternately stacked with each other to form aforementioned multiple quantum wells structure. When the semiconductor device10A is in operation, the active structure104emits a light with a peak wavelength, and the light can include visible light and/or invisible light. The active layer104ahas a bandgap determined by the material composition of the active structure104, and the peak wavelength is corresponding to the bandgap. For example, when the material of the active structure104includes InGaN series, it can emit blue light or deep blue light with a peak wavelength of 400 nm to 490 nm, or green light with a peak wavelength of 490 nm to 550 nm; when the material of the active structure104includes AlGaN series, it can emit ultraviolet light with a peak wavelength of 250 nm to 400 nm; when the material of the active structure104includes InGaAs series, InGaAsP series, AlGaAs series or AlGaInAs series, it can emit infrared light with a peak wavelength of 700 to 1700 nm; when the material of the active structure104includes InGaP series or AlGaInP series, it can emit red light with a peak wavelength of 610 nm to 700 nm, or yellow light with a peak wavelength of 530 nm to 600 nm.

As shown inFIG.1, the first semiconductor structure100can include a plurality of first layers106aand a plurality of second layers106bthat are alternately stacked with each other, so as to form a first superlattice structure106. According to one embodiment, the first semiconductor structure100may have 20 to 70 pairs of the first layer106aand the second layer106b. The first layer106aof each pair can have same or different thicknesses, and the second layers106bof each pair can have same or different thicknesses. In one embodiment, the first layer106aand the second layer106brespectively have a first thickness t1 and a second thickness t2. The first thickness t1 and the second thickness t2 can be in a range of 30 Å to 300 Å. For each or one pair of the first layer106aand the second layer106b, the first thickness t1 and the second thickness t2 can be the same or different. In one embodiment, for each or one pair of the first layer106aand the second layer106b, the second thickness t2 can be equal to or smaller than the first thickness t1. The first superlattice structure106has a first total thickness t10. In one embodiment, the first total thickness t10 can be between 0.1 μm to 4.5 μm, for example, between 0.5 μm to 3 μm or between 1 μm to 2.5 μm. In each pair, the first layer106aand the second layer106bcan include ternary or quaternary III-V compound semiconductor, which is compound of at least three elements selected from aluminum (Al), gallium (Ga), indium (In), phosphorus (P), arsenic (As) or nitrogen (N). In one embodiment, the first layer106aand the second layer106bof each pair do not include nitrogen (N). In one embodiment, the first layer106aand/or the second layer106bof each or one pair includes (Ax3B1-x3)1-y3Iny3P, and elements A and B are selected from group III elements other than indium (In). According to one embodiment, elements A and B can be Al and Ga respectively, and 0≤x3≤1, 0<y3≤1. In one embodiment, the first layer106aincludes (Alx11Ga1-x11)1-y11Iny11P and the second layer106bincludes (Alx12Ga1-x12)1-y12Iny12P, and 0<x11, x12, y11, y12<1 and y11<y12.

According to some embodiments of the present disclosure, the first layer106aand the second layer106bof each pair can include the same material but with different composition ratios. In one embodiment, the first layer106aand the second layer106bin each pair include indium and phosphorus. The first layer106ahas a first indium atomic percentage and the second layer106bhas a second indium atomic percentage different from the first indium atomic percentage. According to one embodiment, when the first semiconductor structure100is the n-type semiconductor, concentration of two-dimensional electron gas (2DEG) within the first semiconductor structure100can be increased by differentiating the first indium atomic percentage of the first layer106afrom the second indium atomic percentage of the second layer106b, so as to increase speed of carrier recombination in the semiconductor device10A. Specifically, the first indium atomic percentage and the second indium atomic percentage are respectively corresponding to an indium atomic ratio of the first layer106aand an indium atomic ratio of the second layer106b, which can be obtained through suitable component analysis methods, such as Energy Dispersive Spectrometer (EDX) or SIMS. For example, when the first layer106aincludes (Alx4Ga1-x4)1y4Iny4P and the second layer106bincludes (Alx5Ga1-x5)1-y5Iny5P (0<x4, x5, y4, y5<1), through EDX analysis the indium atomic ratio of the first layer106ais obtained as y4 and the indium atomic ratio of the second layer106bis obtained as y5. Accordingly, the first indium atomic percentage can be defined as y4*100%, and the second indium atomic percentage can be defined as y5*100%. For example, when y4=0.5 and y5=0.6, the first indium atomic percentage is 50% and the second indium atomic percentage is 60%. Indium atomic percentage represents a percentage of the total number of indium elements to the total number of all group III elements. In some embodiments, the first indium atomic percentage and the second indium atomic percentage can respectively be in a range of 30% to 70%, for example, between 40% to 60%.

In each or one pair of the first layer106aand the second layer106b, a lattice constant of the first layer106aand a lattice constant of the second layer106bcan be the same or different. The “lattice constant” herein means a lattice constant a0 of a layer/structure without any substantial strain. In one embodiment, the first layer106aand the second layer106brespectively have a first lattice constant a1and a second lattice constant a2. In one embodiment, the first lattice constant a1and/or the second lattice constant a2can be in a range of 5.5 Å to 5.8 Å. In some embodiments, when the base108is a GaAs growth substrate and the first indium atomic percentage of the first layer106a(or the second indium atomic percentage of the second layer106b) is 50%, the base108and the first layer106a(or the second layer106b) are latticed-matched. When the first indium atomic percentage (or the second indium atomic percentage) is smaller than 50%, the lattice constant of the first layer106a(or of the second layer106b) is smaller than the lattice constant of the base108, so as to introduce tensile strain into the first layer106a(or the second layer106b). When the first indium atomic percentage (or the second indium atomic percentage) is larger than 50%, the lattice constant of the first layer106a(or of the second layer106b) is larger than the lattice constant of the base108, so as to introduce compressive strain into the first layer106a(or the second layer106b). In some embodiments, the second lattice constant a2of the second layer106bcan be larger than or smaller than the first lattice constant a1of the first layer106a. In other words, the second indium atomic percentage of the second layer106bcan be larger than or smaller than the first indium atomic percentage of the first layer106a.

In each or one pair, the first layer106aand the second layer106bcan include different materials. In some embodiments, the first layer106aor the second layer106bcan include compound semiconductor having antimony (Sb). In one embodiment, the first layer106aor the second layer106bincludes Iny0C1-y0Sbx0D1-x0, and element C is selected from group III elements other than indium and element D is selected from group V elements other than antimony (Sb). In one embodiment, element C and element D can respectively be aluminum (Al) and phosphorus (P), and 0≤x0≤1, 0<y0≤1. In one embodiment, the first layer106aincludes Al1-20Iny20P and the second layer106bincludes Iny23Al1-y23Sbx23P1-x23, and 0<x23, y20, y23<1. When the first semiconductor structure100is the p-type semiconductor, concentration of two-dimensional hole gas (2DHG) within the first semiconductor structure100can be increased by incorporating the compound semiconductor having Sb in the second layer106b. Thus, in the first semiconductor structure100, the serial resistance can be reduced and hole mobility can be increased, and carrier recombination speed of the semiconductor device10A can be improved.

In some embodiments, with respect to the base108(such as the GaAs growth substrate), the first superlattice structure106can have compressive strain, tensile strain or no strain. Besides, in some embodiments, when the first semiconductor structure100is the n-type semiconductor, electron mobility of the first semiconductor structure100can be improved by introducing tensile strain into the first superlattice structure106, for example, making the first layer106ahave tensile strain and the second layer106bhave no strain. Or, when the first semiconductor structure100is the p-type semiconductor, hole mobility of the first semiconductor structure100can be improved by introducing compressive strain into the first superlattice structure106, for example, making the first layer106ahave compressive strain and the second layer106bhave no strain. Through improving the electron mobility or the hole mobility of the first semiconductor structure100, carrier recombination speed of the semiconductor device10A can be increased.

In one embodiment, in each pair, the first layer106ahas a first valence band (Ev1), a first conduction band (Ec1) and a first bandgap (ΔE1=Ec1−Ev1), and the second layer106bhas a second valence band (Ev2), a second conduction band (Ec2) and a second bandgap (ΔE2=Ec2−Ev2). In one embodiment, when the first semiconductor structure100is the n-type semiconductor, a gap of conduction band (ΔEc) between the first conduction band (Ec1) and the second conduction band (Ec2) can be in a range of 0.05 eV to 1 eV, so as to form carrier-confinement effect. For instance, the second conduction band (Ec2) can be lower than the first conduction band (Ec1) by 0.05 eV to 1 eV. In one embodiment, the first bandgap (ΔE1) of the first layer106aand the second bandgap (ΔE2) of the second layer106bcan be larger than the bandgap of the active layer104a, and a wavelength corresponding to the first bandgap (ΔE1) of the first layer106aand a wavelength corresponding to the second bandgap (ΔE2) of the second layer106bare smaller than the peak wavelength of the light emitted from the active structure104. Thus, the first layer106aand the second layer106bdo not absorb the light. In some embodiments, a difference between the peak wavelength of the light and the wavelength corresponding to the first bandgap (ΔE1) (or the wavelength corresponding to the second bandgap (ΔE2)) is equal to or larger than 30 nm. For example, when the active structure104emits a red light with the peak wavelength of 660 nm, the wavelength corresponding to the first bandgap (ΔE1) and/or the wavelength corresponding to the second bandgap (ΔE2) can be equal to or smaller than 630 nm.

In some embodiments, the first layer106aand the second layer106bcan respectively have strains with respect to the base108, and the strain of the first layer106ais opposite to the strain of the second layer106b. For instance, with respect to the base108(such as the GaAs growth substrate), the first layer106aand the second layer106bcan respectively have the tensile strain and the compressive strain (or the compressive strain and the tensile strain), so that the strain of the first layer106acan be compensated by the strain of the second layer106b. In some embodiments, the base108has a third lattice constant a3, and the third lattice constant a3can be between the first lattice constant a1of the first layer106aand the second lattice constant a2of the second layer106b. In some embodiments, each pair of the first layer106aand the second layer106bhave an equivalent lattice constant aq1, and the equivalent lattice constant aq1can be substantially same as the third lattice constant a3so that the first superlattice structure106and the base108can keep latticed-matching. More specifically, as the first layer106ahas the first lattice constant a1and the first thickness t1 and the second layer106bhas the second lattice constant a2and the second thickness t2, the equivalent lattice constant aq1can be expressed as aq1=(a1*t1+a2*t2)/(t1+t2). There may be a lattice constant difference (Δa1) between the equivalent lattice constant aq1and the third lattice constant a3(Δa1=aq1−a3). In some embodiments, a ratio of the lattice constant difference (Δa1) to the third lattice constant a3can be equal to or smaller than ±2000 ppm, i.e., ±0.2%, so that the first superlattice structure106and the base108can keep latticed-matching and avoid delamination formed therebetween.

According to the embodiments in which the first layer106aand the second layer106bhave opposite strains, the first layer106aand the second layer106bcan include Al1-y6Iny6P, Ga1-y7Iny7P or (Alx8Ga(1-x8))1-y8Iny8P, and 0<x8<1, 0<y6, y7, y8<1. In one embodiment, the first layer106aand the second layer106bcan include same material but with different composition ratios. For example, the first layer106acan include Al1-y31Iny31P and the second layer106bcan include Al1-y32Iny32P while y31<y32, thus the first layer106aand the second layer106brespectively have the tensile strain and the compressive strain with respect to the base108. As the first layer106aand the second layer106bare AlInP, the electron mobilities thereof and the wavelengths corresponding to the first bandgap (ΔE1) and the second bandgap (ΔE2) increase with the indium atomic ratios (y31, y32). In one embodiment, when the base108is the GaAs substrate and the peak wavelength of the light emitted from the active structure104is between 580 nm to 620 nm, y31 can be between 0.3 to 0.4 and y32 can be between 0.59 to 0.69 so that the first bandgap (ΔE1) can have a corresponding wavelength between 515 nm to 525 nm and the second bandgap (ΔE2) can have a corresponding wavelength between 535 nm to 605 nm. As such, the second layer106bwith higher indium atomic ratio (y32) can have higher electron mobility to increase carrier recombination speed of the semiconductor device10A. In one embodiment, the first layer106aand the second layer106bcan include different materials. For example, the first layer106acan include Ga1-y33Iny33P and the second layer106bcan include Al1-y34Iny34P while y33<y34, thus the first layer106aand the second layer106brespectively have the tensile strain and the compressive strain with respect to the base108. When the first layer106ais GaInP, the electron mobility thereof and the wavelength corresponding to the first bandgap (ΔE1) increase with the indium atomic ratio (y33). In one embodiment, the indium atomic ratio (y33) of the first layer106ais equal to or larger than 0.3 to ensure the first layer106acan have high electron mobility, such as equal to or larger than 150 cm2/V sec. In one embodiment, when the base108is the GaAs substrate and the peak wavelength of the light emitted from the active structure104is between 580 nm to 620 nm, y33 can be between 0.3 to 0.4 and y34 can be between 0.59 to 0.69, so that the first bandgap (ΔE1) can have a corresponding wavelength between 560 nm to 605 nm and the second bandgap (ΔE2) to can have a corresponding wavelength between 535 nm to 605 nm.

In above two embodiments, through adjusting indium atomic ratios of the first layer106aand the second layer106b, the first layer106aand the second layer106brespectively have the tensile strain and the compressive strain with respect to the base108, and the wavelengths corresponding to the first bandgap (ΔE1) of the first layer106aand the second bandgap (ΔE2) of the second layer106bcan be smaller than the peak wavelength of the light. When the first semiconductor structure100is the n-type semiconductor, the first layer106awith the tensile strain can improve the electron mobility of the first semiconductor structure100. When the first semiconductor structure100is the p-type semiconductor, the second layer106bwith the compressive strain can improve the hole mobility of the first semiconductor structure100. In other words, the first layer106aand the second layer106bcan respectively improve the electron mobility and the hole mobility of the first semiconductor structure100since they have opposite strains, so that the carrier recombination speed of the semiconductor device10A can be increased.

Referring toFIG.1. the first semiconductor structure100can optionally include a first semiconductor layer110, a second semiconductor layer112and/or a first semiconductor contact layer114. The first semiconductor layer110can be disposed between the base108and the first superlattice structure106. The second semiconductor layer112can be disposed between the first superlattice structure106and the active structure104. The first semiconductor contact layer114can be disposed between the first semiconductor layer110and the base108. Besides, the second semiconductor structure102can optionally include a third semiconductor layer116, a fourth semiconductor layer118and/or a second semiconductor contact layer120. The third semiconductor layer116can be disposed on the active structure104. The fourth semiconductor layer118can be disposed on the third semiconductor layer116. The second semiconductor contact layer120can be disposed on the fourth semiconductor layer118. As shown inFIG.1, the second semiconductor layer112and the third semiconductor layer116are located at two sides of the active structure104respectively, and can be cladding layers to respectively provide electrons and holes (or holes and electrons) combined in the active structure104. The first semiconductor layer110and the fourth semiconductor layer118can be window layers to improve current spreading within the semiconductor device10A, or can be light extraction layers to enhance light extraction efficiency. In one embodiment, the first semiconductor structure100does not include the first semiconductor layer110and the second semiconductor structure102does not include the fourth semiconductor layer118, so as to reduce an overall thickness of the semiconductor device10A. The first semiconductor contact layer114and the second semiconductor contact layer120can have high doping concentration, for example, between 1×1018/cm3and 1×1019/cm3, so as to form low resistance interface with adjacent layers or components.

FIG.2shows a schematic cross-sectional view of a semiconductor device10B according to one embodiment of the present disclosure. The semiconductor device10B has similar structure as the semiconductor device10A, but the second semiconductor structure102of the semiconductor device10B further includes a plurality of third layers122aand a plurality of fourth layers122bthat are alternately stacked with each other, so as to form a second superlattice structure122. According to one embodiment, the second semiconductor structure102can have 20 to 50 pairs of the third layer122aand the fourth layer122b. Number of pair of the third layer122aand the fourth layer122bcan be larger than, equal to or small than number of pair of the first layer106aand the second layer106b. The third layer122aof each pair can have same or different thicknesses and the fourth layers122bof each pair can have same or different thicknesses. In one embodiment, the third layer122aand the fourth layer122brespectively have a third thickness t3 and a fourth thickness t4. The third thickness t3 and the fourth thickness t4 can be in a range of 30 Å to 300 Å. For each or one pair of the third layer122aand the fourth layer122b, the third thickness t3 and the fourth thickness t4 can be the same or different. In one embodiment, for each or one pair of the third layer122aand the fourth layer122b, the fourth thickness t4 can be equal to or smaller than the third thickness t3. The second superlattice structure122has a second total thickness t20, which is equal to or smaller than the first total thickness t10 of the first superlattice structure106. In one embodiment, the second total thickness t20 can be between 0.1 μm to 3 μm, for example, between 0.5 μm to 2 μm or between 1 μm to 1.5 μm.

In each pair, the third layer122aand the fourth layer122bcan include ternary or quaternary III-V compound semiconductor, which is compound of at least three elements selected from aluminum (Al), gallium (Ga), indium (In), phosphorus (P), arsenic (As) or nitrogen (N). In one embodiment, the third layer122aand the fourth layer122bof each pair do not include nitrogen (N).

According to some embodiments of the present disclosure, the third layer122aand the fourth layer122bof each pair can include the same material but with different composition ratios. In one embodiment, the third layer122aand the fourth layer122bin each pair include indium and phosphorus. The third layer122ahas a third indium atomic percentage and the fourth layer122bhas a fourth indium atomic percentage different from the third indium atomic percentage. According to one embodiment, when the second semiconductor structure102is the p-type semiconductor, concentration of the two-dimensional hole gas (2DHG) within the second semiconductor structure102can be increased by differentiating the third indium atomic percentage of the third layer122afrom the fourth indium atomic percentage of the fourth layer122b, so as to increase speed of carrier recombination in the semiconductor device10B. Specifically, the third indium atomic percentage and the fourth indium atomic percentage are respectively corresponding to an indium atomic ratio of the third layer122aand an indium atomic ratio of the fourth layer122b, which can be obtained through EDX or SIMS. In some embodiments, the third indium atomic percentage and the fourth indium atomic percentage can respectively be in a range of 30% to 70%, for example, between 40% to 60%.

In each or one pair of the third layer122aand the fourth layer122b, a lattice constant of the third layer122aand a lattice constant of the fourth layer122bcan be the same or different. In one embodiment, the third layer122aand the fourth layer122brespectively have a fourth lattice constant a4and a fifth lattice constant a5. In one embodiment, the fourth lattice constant a4and/or the fifth lattice constant a5can be in a range of 5.5 Å to 5.8 Å. In some embodiments, when the base108is the GaAs growth substrate and the third indium atomic percentage of the third layer122a(or the fourth indium atomic percentage of the fourth layer122b) is 50%, the base108and the third layer122a(or the fourth layer122b) are latticed-matched. When the third indium atomic percentage (or the fourth indium atomic percentage) is smaller than 50%, the lattice constant of the third layer122a(or of the fourth layer122b) is smaller than the lattice constant of the base108, so as to introduce tensile strain into the third layer122a(or the fourth layer122b). When the third indium atomic percentage (or the fourth indium atomic percentage) is larger than 50%, the lattice constant of the third layer122a(or of the fourth layer122b) is larger than the lattice constant of the base108, so as to introduce compressive strain into the third layer122a(or the fourth layer122b). In some embodiments, the fifth lattice constant a5of the fourth layer122bcan be larger than or smaller than the fourth lattice constant a4of the third layer122a. In other words, the fourth indium atomic percentage of the fourth layer122bcan be larger than or smaller than the third indium atomic percentage of the third layer122a.

In each or one pair, the third layer122aand the fourth layer122bcan include different materials. In some embodiments, the third layer122aor the fourth layer122bcan include compound semiconductor having antimony. In one embodiment, the third layer122aor the fourth layer122bincludes Iny2C1-y2Sbx2D1-x2, and element C is selected from group III elements other than indium (In) and element D is selected from group V elements other than antimony (Sb). In one embodiment, element C and element D can respectively be aluminum (Al) and phosphorus (P), and 0≤x2≤1, 0<y2≤1. In one embodiment, the third layer122aincludes Al1-y21Iny21P and the fourth layer122bincludes Iny2Al1-y22Sbx22P1-x22, and 0<x22, y21, y22<1. When the second semiconductor structure102is the p-type semiconductor, the concentration of two-dimensional hole gas (2DHG) within the second semiconductor structure102can be increased by incorporating the compound semiconductor having Sb in the fourth layer122b. Thus, in the second semiconductor structure102, the serial resistance can be reduced and the hole mobility can be increased, and the carrier recombination speed of the semiconductor device10B can be improved.

In some embodiments, with respect to the base108(such as the GaAs growth substrate), the second superlattice structure122can have compressive strain, tensile strain or no strain. Besides, in some embodiments, when the second semiconductor structure102is the n-type semiconductor, electron mobility of the second semiconductor structure102can be improved by introducing tensile strain into the second superlattice structure122, for example, making the third layer122ahave tensile strain and the fourth layer122bhave no strain. Or, when the second semiconductor structure102is the p-type semiconductor, hole mobility of the second semiconductor structure102can be improved by introducing compressive strain into the second superlattice structure122, for example, making the third layer122ahave compressive strain and the fourth layer122bhave no strain. Through improving the electron mobility or the hole mobility of the second semiconductor structure102, carrier recombination speed of the semiconductor device10B can be increased. In one embodiment, in each or one pair of the third layer122aand the fourth layer122b, the third layer122acan include Al1-y13Iny13P and the fourth layer122bcan include Al1-y14Iny14P, and 0<y13, y14<1 and y13<y14.

In one embodiment, in each pair, the third layer122ahas a third valence band (Ev3), a third conduction band (Ec3) and a third bandgap (ΔE3=Ec3−Ev3), and the fourth layer122bhas a fourth valence band (Ev4), a fourth conduction band (Ec4) and a fourth bandgap (ΔE4=Ec4-Ev4). In one embodiment, when the second semiconductor structure102is the p-type semiconductor, a gap of valence band (ΔEv) between the third valence band (Ev3) and fourth valence band (Ev4) can be in a range of 0.05 eV to 1 eV, so as to form carrier-confinement effect. For instance, the fourth valence band (Ev4) can be higher than the third valence band (Ev3) by 0.05 eV to 1 eV. In one embodiment, the third bandgap (ΔE3) of the third layer122aand the fourth bandgap (ΔE4) of the fourth layer122bcan be larger than the bandgap of the active layer104a, and a wavelength corresponding to the third bandgap (ΔE3) of the third layer122aand a wavelength corresponding to the fourth bandgap (ΔE4) of the fourth layer122bcan be smaller than the peak wavelength of the light emitted from the active structure104. Thus, the third layer122aand the fourth layer122bdo not absorb the light. In some embodiments, a difference between the peak wavelength of the light and the wavelength corresponding to the third bandgap (ΔE3) (or the wavelength corresponding to the fourth bandgap (ΔE4)) is equal to or larger than 30 nm. For example, when the active structure104emits a red light with the peak wavelength of 660 nm, the wavelength corresponding to the third bandgap (ΔE3) and the wavelength corresponding to the fourth bandgap (ΔE4) can be equal to or smaller than 630 nm.

In some embodiments, the third layer122aand the fourth layer122bcan respectively have strain with respect to the base108, and the strain of the third layer122ais opposite to the strain of the fourth layer122b. For instance, with respect to the base108(such as the GaAs growth substrate), the third layer122aand the fourth layer122bcan respectively have the tensile strain and the compressive strain (or the compressive strain and the tensile strain), so that the strain of the third layer122acan be compensated by the strain of the fourth layer122b. In some embodiments, the third lattice constant a3of the base108can be between the fourth lattice constant a4of the third layer122aand the fifth lattice constant a5of the fourth layer122b. In some embodiments, each pair of the third layer122aand the fourth layer122bhave an equivalent lattice constant aq2, and the equivalent lattice constant aq2can be substantially same as the third lattice constant a3so that the second superlattice structure122and the base108can keep latticed-matching. More specifically, as the third layer122ahas the fourth lattice constant a4and the third thickness t3 and the fourth layer122bhas the fifth lattice constant a5and the fourth thickness t4, the equivalent lattice constant aq2can be expressed as aq2=(a4*t3+a5*t4)/(t3+t3). There may be a lattice constant difference (Δa2) between the equivalent lattice constant aq2and the third lattice constant a3(Δa2=aq2−a3). In some embodiments, a ratio of the lattice constant difference (Δa2) to the third lattice constant a3can be equal to or smaller than ±2000 ppm, i.e., ±0.2%, so that the second superlattice structure122and the base108can keep latticed-matching and avoid delamination formed therebetween.

According to the embodiments in which the third layer122aand the fourth layer122bhave opposite strains, the third layer122aand the fourth layer122bcan include Al1-y6Iny6P, Ga1-y7Iny7P or (Alx8Ga(1-x8))1-y8Iny8P, and 0<x8<1, 0<y6, y7, y8<1. In one embodiment, the third layer122aand the fourth layer122bcan include same material but with different composition ratios. For example, the third layer122acan include Al1-y35Iny35P and the fourth layer122bcan include Al1-y36Iny36P while y35<y36, thus the third layer122aand the fourth layer122brespectively have the tensile strain and the compressive strain with respect to the base108. As the third layer122aand the fourth layer122bare AlInP, the wavelengths corresponding to the third bandgap (ΔE3) and the fourth bandgap (ΔE4) increase with the indium atomic ratios (y35, y36). In one embodiment, when the base108is the GaAs substrate and the peak wavelength of the light emitted from the active structure104is between 580 nm to 620 nm, y35 can be between 0.3 to 0.4 and y36 can be between 0.59 to 0.69 so that the third bandgap (ΔE3) can have a corresponding wavelength between 515 nm to 525 nm and the fourth bandgap (ΔE4) can have a corresponding wavelength between 535 nm to 605 nm. In one embodiment, the third layer122aand the fourth layer122bcan include different materials. For example, the third layer122acan include Ga1-y37Iny37P and the fourth layer122bcan include Al1-y38Iny38P while y37<y38, thus the third layer122aand the fourth layer122brespectively have the tensile strain and the compressive strain with respect to the base108. When the third layer122ais GaInP, the wavelength corresponding to the third bandgap (ΔE3) increases with the indium atomic ratio (y37). In one embodiment, when the base108is the GaAs substrate and the peak wavelength of the light emitted from the active structure104is between 580 nm to 620 nm, y37 can be between 0.3 to 0.4 and y38 can be between 0.59 to 0.69, so that the third bandgap (ΔE3) can have a corresponding wavelength between 560 nm to 605 nm and the fourth bandgap (ΔE4) can have a corresponding wavelength between 535 nm to 605 nm.

In above two embodiments, through adjusting indium atomic ratios of the third layer122aand the fourth layer122b, the third layer122aand the fourth layer122brespectively have the tensile strain and the compressive strain with respect to the base108, and the wavelengths corresponding to the third bandgap (ΔE3) of the third layer122aand the fourth bandgap (ΔE4) of the fourth layer122bcan be smaller than the peak wavelength of the light. When the second semiconductor structure102is the n-type semiconductor, the third layer122awith the tensile strain can improve the electron mobility of the second semiconductor structure102. When the second semiconductor structure102is the p-type semiconductor, the fourth layer122bwith the compressive strain can improve the hole mobility of the second semiconductor structure102. In other words, the third layer122aand the fourth layer122bcan respectively improve the electron mobility and the hole mobility of the second semiconductor structure102since they have opposite strains, so that the carrier recombination speed of the semiconductor device10B can be increased.

The positions, relative relationships, and material compositions of other layers or structures as well as structural variations in the semiconductor device10B have been described in detail in previous embodiments, and are not repeatedly described herein.

FIGS.3A to3Dshow schematic figures of band structure according to superlattice structures in different embodiments of the present disclosure. To facilitate explanation,FIGS.3A to3Dare illustrated by the second superlattice structures122. However, one having ordinary skills in this art should understand that either the first superlattice structure106or the second superlattice structure122can have the band structures shown inFIGS.3A,3B,3C or3D.

Referring toFIG.3A, the plurality of third layers122aand the plurality of fourth layers122bare alternately stacked with each other to form the second superlattice structure122. In this embodiment, the plurality of third layers122ahas the third valence band (Ev3) and the third conduction band (Ec3), and the plurality of fourth layers122bhas the fourth valence band (Ev4) and the fourth conduction band (Ec4). The maximum difference between the third valence band (Ev3) and the fourth valence band (Ev4) is defined as the gap of valence band (ΔEv), and the maximum difference between the third conduction band (Ec3) and the fourth conduction band (Ec4) is defined as a gap of conduction band (ΔEc). In this embodiment, the third conduction band (Ec3) is larger than the fourth conduction band (Ec4), and the fourth valence band (Ev4) is larger than the third valence band (Ev3). In one embodiment, the gap of valence band (ΔEv) can be larger than the gap of conduction band (ΔEc). In one embodiment, the gap of valence band (ΔEv) can be in a range of 0.05 eV to 1 eV. In one embodiment, the gap of conduction band (ΔEc) can be in a range of 0.05 eV to 1 eV. With respect to the base108, the second superlattice structure122can have no strain. For example, the third layer122acan include Al0.3Ga0.15In0.5P and the fourth layer112bcan include Al0.15Ga0.35In0.5P, and the gap of valence band (ΔEv) is about 0.13 eV and the gap of conduction band (ΔEc) is about 0.08 V. When the second semiconductor structure102is the n-type semiconductor, forming the gap of conduction band (ΔEc) mentioned above between the third conduction band (Ec3) and the fourth conduction band (Ec4) can provide good carrier confinement effect.

Referring toFIG.3B, in this embodiment, the plurality of third layers122ahas a third valence band (Ev3′) and a third conduction band (Ec3′), and the plurality of fourth layers122bhas a fourth valence band (Ev4′) and a fourth conduction band (Ec4′). Similarly, the maximum difference between the third valence band (Ev3′) and the fourth valence band (Ev4′) is defined as the gap of valence band (ΔEv′), and the maximum difference between the third conduction band (Ec3′) and the fourth conduction band (Ec4′) is defined as the gap of conduction band (ΔEc′). In this embodiment, the third conduction band (Ec3′) is larger than the fourth conduction band (Ec4′), and the fourth valence band (Ev4′) is smaller than the third valence band (Ev3′). In this embodiment, the gap of valence band (ΔEv′) can be smaller than the gap of conduction band (ΔEc′). For example, the gap of valence band (ΔEv′) can be smaller than 0.05 eV and the gap of conduction band (ΔEc′) can be between 0.05 eV to 1 eV. With respect to the base108, the second superlattice structure122can have strain. For example, the third layer122acan include Al0.7Ga0.3As0.9Sb0.1and the fourth layer122bcan include Al0.15Ga0.35In0.5P, and the gap of valence band (ΔEv′) is about 0.13 eV and the gap of conduction band (ΔEc′) is about 0.08 eV. When the second semiconductor structure102is the n-type semiconductor, forming the gap of conduction band (ΔEc′) between the third conduction band (Ec3′) and the fourth conduction band (Ec4′) can provide good carrier confinement effect.

Referring toFIG.3C, in this embodiment, the plurality of third layers122ahas a third valence band (Ev3″) and a third conduction band (Ec3″), and the plurality of fourth layers122bhas a fourth valence band (Ev4″) and a fourth conduction band (Ec4″). The maximum difference between the third valence band (Ev3″) and the fourth valence band (Ev4″) is defined as the gap of valence band (ΔEv″), and the maximum difference between the third conduction band (Ec3″) and the fourth conduction band (Ec4″) is defined as the gap of conduction band (ΔEc″). In this embodiment, the third conduction band (Ec3″) is smaller than the fourth conduction band (Ec4″) and the fourth valence band (Ev4″) is larger than the third valence band (Ev3″). In this embodiment, the gap of valence band (ΔEv″) can be between 0.05 eV to 1 eV and the gap of conduction band (ΔEc″) can be between 0.05 eV to 1 eV. With respect to the base108, the second superlattice structure122can have strain. For example, the third layer122acan include Al0.5In0.5P and the fourth layer122bcan include In0.5Al0.5P0.8Sb0.2, and the gap of valence band (ΔEv″) is about 0.1 eV and the gap of conduction band (ΔEc″) is about 0.05 eV. When the second semiconductor structure102is the p-type semiconductor, forming the gap of valence band (ΔEv″) between the third valence band (Ev3″) and the fourth valence band (Ev4″) can provide good carrier confinement effect. In this embodiment, since the fourth layer122bincludes antimony (Sb), concentration of the two-dimensional hole gas (2DHG) and hole mobility within the second semiconductor structure102can be increased, so as to reduce serial resistance and increase carrier recombination speed of the semiconductor device10A.

Referring toFIG.3D, in this embodiment, the plurality of third layers122ahas a third valence band (Ev3′″) and a third conduction band (Ec3′″), and the plurality of fourth layers122bhas a fourth valence band (Ev4′″) and a fourth conduction band (Ec4′″). The maximum difference between the third valence band (Ev3′″) and the fourth valence band (Ev4′″) is defined as the gap of valence band (ΔEv′″), and the maximum difference between the third conduction band (Ec3′″) and the fourth conduction band (Ec4′″) is defined as the gap of conduction band (ΔEc′″). In this embodiment, the third conduction band (Ec3′″) is larger than the fourth conduction band (Ec4′″) and the fourth valence band (Ev4′″) is larger than the third valence band (Ev3′″). In this embodiment, the gap of valence band (ΔEv′″) can be between 0.05 eV to 1 eV and the gap of conduction band (ΔEc′″) can be between 0.05 eV to 1 eV. With respect to the base108, the second superlattice structure122can have strain. For example, the third layer122acan include Al0.35Ga0.15In0.5P0.9Sb0.1and the fourth layer122bcan include Al0.15Ga0.35In0.5P, and the gap of valence band (ΔEv′″) is about 0.1 eV and the gap of conduction band (ΔEc′″) is about 0.11 eV. When the second semiconductor structure102is the n-type semiconductor, forming the gap of conduction band (ΔEc′″) between the third conduction band (Ec3′″) and the fourth conduction band (Ec4′″) can provide good carrier confinement effect.

FIG.4Ashows a top schematic view of a semiconductor device10C according to one embodiment of the present disclosure, andFIG.4Bis a schematic cross-sectional view of the semiconductor device10C along section line A-A′ inFIG.4A. In the embodiment shown inFIG.4A, the semiconductor device10C is formed by transferring the first semiconductor structure100, the second semiconductor structure102and the active structure104shown inFIG.2to the base108′ through a bonding process. That is to say, in this embodiment, the base108′ is the bonding substrate, and the second semiconductor structure102is located on the base108′ and closer to the base108′ than the first semiconductor structure100.

As shown inFIGS.4A and4B, the semiconductor device10C further includes a first electrode124and a second electrode126which are disposed at two opposite sides of the base108′ respectively. The first electrode124and the second electrode126electrically connect the semiconductor device10C to an external power source or other components for operating the semiconductor device10C. The first electrode124and the second electrode126can include metal oxide, metal or alloy. For example, the metal oxide can include, but not limited to, indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), zinc oxide (ZnO), indium tungsten oxide (IWO), or indium zinc oxide (IZO). The metal can include, but not limited to, germanium (Ge), beryllium (Be), zinc (Zn), gold (Au), platinum (Pt), titanium (Ti), aluminum (Al), nickel (Ni), or copper (Cu). The alloy can include two or more metals selected from the abovementioned metals, such as germanium-gold-nickel (GeAuNi), beryllium gold (BeAu), germanium gold (GeAu), or zinc gold (ZnAu).

As shown inFIG.4A, in this embodiment, the first electrode124includes a pad124a, a plurality of first extending portions124bconnecting the pad124a, and a plurality of second extending portions124cconnecting the plurality of first extending portions124b. In some embodiment, the first electrode124can include multiple pads124a, and the pads124can be connected by one of the plurality of second extending portions124c. In top view, the plurality of first extending portions124bextends along X-direction, and the plurality of second extending portions124cextends along Z-direction and are perpendicular to the plurality of first extending portions124b. Each of the first extending portions124bhas a first width W1 (along Z-direction), and each of the second extending portions124chas a second width W2 (along X-direction). The second width can be smaller than the first width W1. In this embodiment, the pad124aconnects the external power source or components through a wire, then currents flowed into the pad124acan spread into the semiconductor device10C uniformly through the plurality of first extending portions124band the plurality of second extending portions124c.

As shown inFIG.4B, the semiconductor device10C can optionally include an insulating structure128, a conductive structure130, a reflecting structure132and a bonding structure134. In this embodiment, the insulating structure128is located below the second semiconductor structure102and directly contact the second semiconductor contact layer120. As shown inFIG.4B, the insulating structure128can include a plurality of holes128a. The conductive structure130is located below the insulating structure128. In one embodiment, the conductive structure130fills in the plurality of holes128ato contact the second semiconductor contact layer120directly, so as to form a plurality of current passages136. As shown inFIGS.4A and4B, the plurality of current passages136is not overlapped with the first electrode124along Y-direction for spreading the currents uniformly. It should be noticed thatFIG.4Ais actually a top perspective view of the semiconductor device10C, so as to clearly show corresponding positions of the plurality of current passages136(or the plurality of holes128a) projected on an upper surface of the semiconductor device10C along the Y-direction. Since the insulating structure128and the conductive structure130are within the semiconductor device10C, the plurality of current passages136(or the plurality of holes128a) cannot be directly observed from appearance of the semiconductor device10C. In some embodiments, each of the current passages136(or each of the holes128a) has a top-view shape of circle, ellipse or polygon, for example, triangle, rectangle, pentagon or hexagon.

The insulating structure128can include electrically insulating materials, such as oxide or fluoride. The oxide is, for example, silicon dioxide (SiOx), and the fluoride is, for example, magnesium fluoride (MgFx). In some embodiments, the insulating structure128can include an electrically insulating material, such as a low-refractive-index electrical insulating material with a refractive index lower than 1.4, such as magnesium fluoride (MgFx). The conductive structure130can include transparent conductive oxides, such as indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), Al-doped ZnO (AZO), zinc tin oxide (ZTO), Ga-doped ZnO (GZO), zinc oxide (ZnO), indium cerium oxide (ICO), indium tungsten oxide (IWO), indium titanium oxide (ITiO), indium zinc oxide (IZO), indium gallium oxide (IGO) or gallium aluminum zinc oxide (GAZO).

As shown inFIG.4B, the reflecting structure132is located below the conductive structure130. In one embodiment the reflecting structure132can have high reflectivity to the light emitted from the active structure104, such as 80% or higher. The reflecting structure132can include conductive material, such as metal or alloy. The metal can include gold (Au), silver (Ag) or aluminum (Al). The bonding structure134is located between the reflecting structure132and the base108′. The bonding structure134can include conductive material, such as metal or alloy. In one embodiment, the bonding structure134can be formed by soldering, eutectic bonding or thermocompression bonding to bond the reflecting structure132to the base108′.

In one embodiment, the first semiconductor contact layer114can be patterned to locate below the plurality of first extending portions124band the plurality of second extending portions124cof the first electrode124. As shown inFIG.4B, along Y-direction, the first semiconductor contact layer114is overlapped with the second extending portions124cand not overlapped with the pad124a. More specifically, the first semiconductor contact layer114has an upper surface114sand a side surface114d, and each of the first extending portions124band/or each of the second extending portions124cdirectly contacts the upper surface114sand the side surface114dfor increasing electrical contact area.

Referring toFIG.4B, the semiconductor device10C can optionally include protecting layer138covering the first semiconductor structure100and the first electrode124, so as to protect the semiconductor device10C and prevent external pollutants or moisture from affecting photoelectric characteristics of the semiconductor device10C. More specifically, the protecting layer138covers on the plurality of first extending portions124b, the plurality of second extending portions124cand a part of a top surface124sof the pad124a. In other words, the top surface124sof the pad124ais partially exposed to connect with the external power source or components. The protecting layer138can include insulating material, such as SiNx or SiOx. The positions, relative relationships, and material compositions of other layers or structures as well as structural variations in the semiconductor device10C have been described in detail in previous embodiments, and are not repeatedly described herein. Furthermore, it should be realized that the semiconductor device10C shown inFIG.4Bis not limited to include both of the first superlattice structure106and the second superlattice structure122. In other embodiments, the semiconductor device10C can include only one of the first superlattice structure106and the second superlattice structure122.

FIG.5is a schematic cross-sectional view of a semiconductor device20according to one embodiment of the present disclosure, which has similar components as the semiconductor device10C. As shown inFIG.5, there is a difference between the semiconductor device20and the semiconductor device10C that the first electrode124and the second electrode126of the semiconductor device20are located at the same side of the base108′. In one embodiment, the semiconductor device20can further include a first metal contact layer140and a second metal contact layer142. The first metal contact layer140forms on the first semiconductor contact layer114and electrically connecting the first semiconductor contact layer114, and the second metal contact layer142forms on the fourth semiconductor layer118and electrically connecting the fourth semiconductor layer118. Furthermore, the protecting layer138can include a first opening138aand a second opening138brespectively corresponding to the first metal contact layer140and the second metal contact layer142, so as to expose a part of top surface of the first metal contact layer140and a part of top surface of the second metal contact layer142. The first electrode124fills in the first opening138aand directly contact the first metal contact layer140to form electrical connection with the first metal contact layer140, and the second electrode126fills in the second opening138band directly contact the second metal contact layer142to form electrical connection with the second metal contact layer142. As shown inFIG.5, side surfaces of the first semiconductor structure100, the second semiconductor102and the active structure104can be inclined, thus the protecting layer138can conformally attach to the first semiconductor structure100, the second semiconductor102and the active structure104easily. In this embodiment, for disposing the first electrode124and the second electrode126at the same side of the base108′, a width of the fourth semiconductor layer118can be larger than a width of the second superlattice structure122and a width of the third semiconductor structure116, so as to form the second metal contact layer142and the second electrode126on the upper surface of the fourth semiconductor layer118.

Materials of the first metal contact layer140and the second metal contact layer142can be determined respectively according to the material of the first semiconductor contact layer114and the material of the fourth semiconductor layer118, so as to form an electrical contact (such as an ohmic contact) between the first metal contact layer140and the first semiconductor contact layer114and between the second metal contact layer142and the fourth semiconductor layer118. The first metal contact layer140and the second metal contact layer142can respectively include conductive material, such as metal or alloy. The metal includes germanium (Ge), beryllium (Be), zinc (Zn), gold (Au), nickel (Ni), or copper (Cu). The alloy, for example, includes two or more metals selected from the above metals, such as germanium-gold-nickel (GeAuNi), beryllium gold (BeAu), germanium gold (GeAu), or zinc gold (ZnAu). The first metal contact layer140and the second metal contact layer142can include different materials. In one embodiment, the first metal contact layer140includes germanium gold (GeAu) and the second metal contact layer142includes beryllium gold (BeAu). As shown inFIG.5, the first metal contact layer140may directly contact an upper surface and a side surface of the first semiconductor contact layer114to increase contact area therebetween. In another embodiment, the first metal contact layer140can only contact the upper surface of the first semiconductor contact layer114.

In one embodiment, the protecting layer138can optionally include a distributed Bragg reflector (DBR). The distributed Bragg reflector can include a plurality of first dielectric layers and a plurality of second dielectric layers alternately stacked with each other, and the plurality of first dielectric layers and a plurality of second dielectric layers have different refractive indices. For the semiconductor device20, when the light emitted from the active structure104is extracted from the base108′, the protecting layer138with DBR helps to reflect the light towards the base108′ to facilitate light extraction. The positions, relative relationships, and material compositions of other layers or structures as well as structural variations in the semiconductor device20have been described in detail in previous embodiments, and are not repeatedly described herein. Furthermore, it should be realized that the semiconductor device20shown inFIG.5is not limited to include both of the first superlattice structure106and the second superlattice structure122. In other embodiments, the semiconductor device20can include one of the first superlattice structure106and the second superlattice structure122only.

FIG.6is a schematic cross-sectional view of a package structure200of a semiconductor device10in one embodiment in accordance with the present disclosure. The package structure200includes a semiconductor device10, a packaging mount21, a first electrical connection structure23, a bonding wire25, a second electrical connection structure26, and an encapsulating structure28. The packaging mount21can include ceramic or glass. The packaging mount21has multiple channels22, which can be filled with electrically conductive material such as metal for facilitating electrical conduction or/and heat dissipation. The first electrical connection structure23is located on the surface of one side of the packaging mount21and can include an electrically conductive material such as metal. The semiconductor device10is located on the first electrical connection structure23and can be applied to any of the embodiments in the present disclosure, such as aforementioned the semiconductor device10A, the semiconductor device10B, the semiconductor device10C or the semiconductor device20. In this embodiment, the first electrical connection structure23includes a first contact pad23aand the second contact pad23b, and the semiconductor device10can electrically connect to the second contact pad23bof the first electrical connection structure23by the bonding wire25. The bonding wire25can include metal, such as gold (Au), silver (Ag), copper (Cu), aluminum (Al), or the alloy including one of the aforementioned metals. The second electrical connection structure26is located on the surface of another side of the packaging mount21. In this embodiment, the second electrical connection structure26includes a third contact pad26aand a fourth contact pad26b. The third contact pad26aand the fourth contact pad26bcan connect to the first electrical connection structure23electrically through the channels22. In one embodiment, the second electrical connection structure26can additionally include a thermal pad (not shown) located, for example, between the third contact pad26aand the fourth contact pad26b. The encapsulating structure28can protect the semiconductor device10by covering the semiconductor device10. More specifically, the encapsulating structure28can include resin, such as epoxy, silicone. The encapsulating structure28can additionally include a plurality of wavelength conversion particles (not shown) to convert a first light emitted from the semiconductor device10into a second light.

Based on the above, the present disclosure can provide a semiconductor device and a package structure thereof, and the structural design of which helps to improve optoelectronic characteristics of the semiconductor device (for example, lowering the operating bias or improving speed of carrier recombination). The semiconductor device or the package structure disclosed in this disclosure can be applied to products in various fields, such as illumination, medical care, display, communication, sensing, or power supply system, for example, can be used in a light fixture, monitor, mobile phone, tablet, an automotive instrument panel, a television, computer, wearable device (such as watch, bracelet or necklace), traffic sign, outdoor display, or medical device.

The embodiments of the present disclosure will be described in detail below with reference to the drawings. In the descriptions of the specification, specific details are provided for a full understanding of the present disclosure. The same or similar components in the drawings will be denoted by the same or similar symbols. It is noted that the drawings are for illustrative purposes only and do not represent the actual dimensions or quantities of the components. Some of the details may not be fully sketched for the conciseness of the drawings.