Wiring substrate and semiconductor package

A wiring substrate for a semiconductor device includes a heat spreader; a polyimide layer provided with through holes and provided on the heat spreader via an adhesion layer; through wirings formed to fill the through holes of the polyimide layer; a thermal diffusion wiring provided on the polyimide layer and is configured not to be electrically connected to the semiconductor device; an electrical connection wiring provided on the polyimide layer at a same plane with the thermal diffusion wiring and is configured to be electrically connected to the semiconductor device; and an insulating layer provided on the polyimide layer with a first open portion and a second open portion that expose the electrical connection wiring and the thermal diffusion wiring, respectively, the thermal diffusion wiring being formed to extend at an outer side of the second open portion and have a larger area than the electrical connection wiring.

CROSS-REFERENCE TO RELATED APPLICATION

The present application is based on and claims the benefit of priority of Japanese Priority Application No. 2014-004630 filed on Jan. 14, 2014 and Japanese Priority Application No. 2014-092949 filed on Apr. 28, 2014, and the entire contents of which are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a wiring substrate and a semiconductor package.

2. Description of the Related Art

Recently, a wiring substrate has been provided for mounting a semiconductor device such as a light emitting device or the like. For example, a wiring substrate is known in which a wiring is formed on a heat spreader via an adhesion layer. In such a wiring substrate, when heat is generated by a semiconductor device that is mounted on the wiring, it is necessary to transfer the heat to the heat spreader. At this time, as the adhesion layer functions as a part of a radiation path, a material with a high coefficient of thermal conductivity such as insulating resin including alumina filler or the like is used as the adhesion layer.

However, as the wiring and the heat spreader are electrically-conductive materials, if the adhesion layer is made thin (about 50 μm, for example), there is a possibility that the wiring and the heat spreader are not sufficiently insulated. Thus, it is necessary to form the adhesion layer to have a thickness of about 100 to 200 μm. On the other hand, although the wiring and the heat spreader are sufficiently insulated by forming the adhesion layer to have the thickness of about 100 to 200 μm, in such a case, there is another problem that a thermal radiation property becomes lower due to the increase of heat resistance of the adhesion layer.

As described above, it is difficult for a conventional wiring substrate for mounting a heat generation semiconductor device such as a light emitting device or the like to ensure an insulation property and to improve a thermal radiation property at the same time.

Patent Document

SUMMARY OF THE INVENTION

The present invention is made in light of the above problems, and provides a wiring substrate or the like capable of ensuring an insulation property and improving a thermal radiation property at the same time.

According to an embodiment, there is provided a wiring substrate on which a semiconductor device is mounted, the wiring substrate including a heat spreader; a polyimide layer provided on the heat spreader via an adhesion layer that includes filler, the polyimide layer being provided with a plurality of through holes penetrating the polyimide layer in the thickness direction; a plurality of through wirings formed to fill the through holes provided at the polyimide layer, respectively; a thermal diffusion wiring provided on the polyimide layer so as to be connected to the through wirings, the thermal diffusion wiring being configured not to be electrically connected to the semiconductor device; an electrical connection wiring provided on the polyimide layer at a same plane with the thermal diffusion wiring, the electrical connection wiring being configured to be electrically connected to the semiconductor device; and an insulating layer provided on the polyimide layer and provided with a first open portion that exposes the electrical connection wiring and a second open portion that exposes the thermal diffusion wiring, the thermal diffusion wiring being formed to extend at an outer side of the second open portion and have a larger area than the electrical connection wiring, in a plan view.

Note that also arbitrary combinations of the above-described elements, and any changes of expressions in the present invention, made among methods, devices, systems and so forth, are valid as embodiments of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

It is to be noted that, in the explanation of the drawings, the same components are given the same reference numerals, and explanations are not repeated.

First Embodiment

Structure of Wiring Substrate of First Embodiment

First, a structure of a wiring substrate of a first embodiment is explained.FIG. 1AandFIG. 1Bare views illustrating a wiring substrate1of the first embodiment.FIG. 1Bis a plan view andFIG. 1Ais a cross-sectional view taken along an A-A line ofFIG. 1B.

With reference toFIG. 1AandFIG. 1B, the wiring substrate1basically includes a polyimide layer10, an adhesion layer20, wirings31to33, plating films41to45, through wirings50, an insulating layer60, an adhesion layer70and a heat spreader (heat sink)80. A portion of the wiring substrate1including the polyimide layer10, the adhesion layer20, the wirings31to33, the plating films41to45and the through wirings50is referred to as a “wiring portion Z” as well. This means that the wiring substrate1has a structure in which the wiring portion Z is placed on the heat spreader80via the adhesion layer70. Here, the adhesion layer20is an optional element and the wiring substrate1may not include the adhesion layer20.

In this embodiment, an insulating layer60side of the wiring substrate1is referred to as an upper side or one side, and a heat spreader80side of the wiring substrate1is referred to as a lower side or the other side. Further, a surface of each component at the insulating layer60side is referred to as an upper surface or one surface, and a surface at the heat spreader80side is referred to as a lower surface or the other surface. However, the wiring substrate1may be used in an opposite direction or may be used at an arbitrarily angle. Further, in this embodiment, “in a plan view” means that an object is seen in a direction that is normal to one surface of the polyimide layer10, and a “plan shape” means a shape of an object seen in the direction that is normal to the one surface of the polyimide layer10.

In the wiring substrate1, the polyimide layer10may be made of a flexible polyimide-based insulating resin film, for example. The thickness of the polyimide layer10may be about 25 to 75 μm, for example.

The adhesion layer20is adhered to the one surface of the polyimide layer10and adheres the wirings31to33to the polyimide layer10. For the adhesion layer20, a heat-resistant adhesive agent made of insulating resin such as an epoxy-based adhesive agent, a polyimide-based adhesive agent or the like may be used, for example. The thickness of the adhesion layer20may be about 5 to 15 μm, for example.

The wirings31to33are provided on the one surface of the polyimide layer10via the adhesion layer20, and are electrically insulated from each other. Although not illustrated inFIG. 1AandFIG. 1B, as will be explained later, a semiconductor device such as a light emitting device, a module including the semiconductor device, or the like is to be mounted on the wiring substrate1. The wirings31and32are electrical connection wirings that are electrically connected to terminals of the semiconductor device or the like. The wiring33is a thermal diffusion wiring that does not affect an operation of the semiconductor device or the like. In other words, the wiring33is not electrically connected to the semiconductor device or the like. Yet in other words, current does not flow through the wiring33. The electrical connection wirings and the thermal diffusion wiring are formed at a same plane on the polyimide layer10. Specifically, in this embodiment, the electrical connection wirings and the thermal diffusion wiring are formed at an upper surface of the adhesion layer20. The wiring33is connected to an end of each of the through wirings50that penetrate the polyimide layer10and the adhesion layer20. An embodiment in which the semiconductor device is mounted on the wirings31to33is explained later.

As illustrated inFIG. 1B, the insulating layer60is provided with an open portion60yfrom which the plating film43is exposed. As will be explained later, the semiconductor device or the like or a thermal radiation terminal of the semiconductor device or the like is mounted on the plating film43exposed from the open portion60y. The wiring33(thermal diffusion wiring) extends outside of the open portion60yand is formed to have a larger size than the open portion60y(in other words, the thermal radiation terminal of the semiconductor device or the like, for example) in a plan view. In other words, the wiring33is formed to have a larger size than the wiring31or32at the upper surface of the polyimide layer10(or the adhesion layer20) in a plan view.

For example, inFIG. 1B, the wiring33is formed to have an H-shape and to cover the upper surface of the adhesion layer20except the areas where the wirings31and32are formed. Here, the wiring31and the wiring32are formed at concave portions of the H-shaped wiring33such as to face with each other. As such, by extending the wiring33to have a larger size, the heat generated at the semiconductor device or the like can be diffused via the wiring33in a surface direction of the wiring33, in addition to via the through wirings50. Thus, thermal radiation efficiency can be improved.

The plan shape of the wiring33is not limited to the H-shape, and the wiring33may have various shapes such as a rectangular shape, a polygonal shape, a circular shape, a combined shape of them, or the like in accordance with the shapes or positions of the wirings31and32. In such a case, the wiring33may be provided such that a part of the wiring33exists between the wiring31and the wiring32that face with each other (seeFIG. 7B, for example).

For the material of the wirings31to33, copper (Cu) or the like may be used, for example. The thickness of the wirings31to33may be about 12 to 35 μm, for example.

The plating films41to43are formed at portions of the wirings31to33that are exposed from the upper surface of the insulating layer60. Although not illustrated inFIG. 1A, the wiring31includes an area that is one of external connection terminals and the plating film44is formed on that area. This means that the plating film41and the plating film44are electrically connected with each other. Similarly, the wiring32includes an area that is another of the external connection terminals and the plating film45is provided on that area. This means that the plating film42and the plating film45are electrically connected with each other. Each of the plating films41to45may be formed to have long narrow strip shape, for example, and the plating films41to45may be aligned to have a predetermined space therebetween.

For the material of the plating films41to45, a plating film in which Ni (or a Ni alloy film) and Au (or an Au alloy film) are stacked in this order may be used, for example. Alternatively, for the material of the plating films41to45, a plating film in which Ni (or a Ni alloy film), Pd (or a Pd alloy film) and Au (or an Au alloy film are stacked in this order; a plating film in which Ni (or a Ni alloy film), Pd (or a Pd alloy film), Ag (or an Ag alloy film) and Au (or an Au alloy film) are stacked in this order; a plating film of Ag (or an Ag alloy film); a plating film in which Ni (or a Ni alloy film) and Ag (or an Ag alloy film) are stacked in this order; a plating film in which Ni (or a Ni alloy film), Pd (or a Pd alloy film) and Ag (or an Ag alloy film) are stacked in this order; or the like may be used.

Among the plating films41to45, it is preferable that the thickness of each of Au (or the Au alloy film) and Ag (or the Ag alloy film) is more than or equal to 0.1 μm. Further, among the plating films41to45, it is preferable that the thickness of Pd (or the Pd alloy film) is more than or equal to 0.005 μm. Further, among the plating films41to45, it is preferable that the thickness of Ni (or the Ni alloy film) is more than or equal to 0.5 μm.

The through wirings50are wirings for thermal radiation and are referred to as thermal vias as well. This means that the through wirings50function as a part of a path that releases heat generated by the semiconductor device or the like mounted on the wiring substrate1when the semiconductor device or the like is operated, to the heat spreader80side.

The polyimide layer10and the adhesion layer20are provided with a plurality of through holes that penetrate the polyimide layer10and the adhesion layer20in the thickness direction. The plurality of through wirings50are provided to fill the through holes formed in the polyimide layer10and the adhesion layer20. The through wirings50are provided on the other surface of the wiring33(thermal diffusion wiring) at the polyimide layer10side. Thus, in this embodiment, the plurality of through wirings50(six through wirings, for example, in the example illustrated inFIG. 1B) are provided right below the wiring33. With this configuration, the thermal radiation property can be improved.

The through wirings50are integrally formed with the wiring33. One end of each of the through wirings50is connected to the wiring33and the other end of each of the through wirings50is exposed from the other surface of the polyimide layer10. Alternatively, the through wirings50may be configured such that the other end of each of the through wirings50protrudes from the other surface of the polyimide layer10. The plan shape of each of the through wirings50may be a circular shape with a diameter of about 0.5 to 1 mm, for example. However, the diameter of each of the through wirings50may be more than or equal to 1 mm when it is desired to specifically improve the thermal radiation property or the like. The plan shape of each of the through wirings50may be an ellipse shape, a rectangular shape or the like, for example. The thickness of the through wirings50may be about 25 to 75 μm, for example. For the material of the through wirings50, copper (Cu) or the like may be used, for example.

Here, the through wirings50are not provided right below the wirings31and32. This means that the wirings31and32(electrical connection wirings) are only formed to extend on a plane surface (the upper surface of the adhesion layer20). In other words, only the adhesion layer20, the polyimide layer10and the adhesion layer70exist between the wirings31and32and the heat spreader80, and any other wirings or the like for electrical connection do not exist in the adhesion layer20, the polyimide layer10and the adhesion layer70at areas overlapping with the wirings31and32, respectively, in a plan view. With this configuration, the insulating properties between the wirings31and32and the heat spreader80can be improved.

When the semiconductor device is a light emitting device, the insulating layer60may be a reflection film that is provided on the polyimide layer10in order to improve reflectivity of light emitted by the light emitting device and to improve thermal diffusivity. The insulating layer60is provided with open portions60xthat selectively expose the wirings31and32(electrical connection wirings) and the open portion60yas described above that selectively exposes the wiring33(thermal diffusion wiring). As described above, the plating films41to45are provided on the wirings31to33that are exposed from the insulating layer60. For the material of the insulating layer60, epoxy-based resin, silicone-based resin such as organo-polysiloxane or the like, including filler such as titanium oxide (TiO2), barium sulfate (BaSO4) or the like or dye may be used, for example. Alternatively, for the material of the insulating layer60, white ink made of such a material may be used.

It is preferable that the insulating layer60is formed to expose an outer edge portion20aof the adhesion layer20. With this configuration, as it is unnecessary to cut the insulating layer60when dicing (cutting) and dividing each of the areas, each of which finally becomes the wiring substrate1, in manufacturing the wiring substrate1, chipping or removal of an edge of the insulating layer60can be prevented. With this, decreasing of a surface area of the insulating layer60can be prevented and lowering of reflectivity of the insulating layer can be prevented.

The adhesion layer70is provided on the heat spreader80and contacts the other surface of the polyimide layer10to adhere the polyimide layer10and the heat spreader80. As the adhesion layer70becomes a part of the path that releases the heat transferred from the through wirings50to the heat spreader80, it is preferable that a material whose coefficient of thermal conductivity is high is used for the adhesion layer70. For the adhesion layer70, a heat-resistant adhesive agent made of insulating resin such as an epoxy-based adhesive agent, a polyimide-based adhesive agent or the like including filler such as alumina or the like may be used, for example. Here, the filler included in the adhesion layer70may be electrically-conductive filler. The thickness of the adhesion layer70may be about 20 to 50 μm, for example.

The heat spreader80is adhered to the other surface of the polyimide layer10by the adhesion layer70. For the material of the heat spreader80, a metal plate made of a material whose coefficient of thermal conductivity is high such as copper (Cu), aluminium (Al) or the like may be used, for example. Alternatively, an insulating plate made of an insulating material whose coefficient of thermal conductivity is high such as ceramics like alumina, aluminum nitride or the like, silicon or the like may be used as the heat spreader80. The thickness of the heat spreader80may be about 100 to 1000 μm, for example. However, the thickness of the heat spreader80may be about a few mm when a particularly high thermal radiation property is required.

An advantage of a structure of the embodiment in which the through wirings50are not provided right below the wirings31and32and the through wirings50are only provided right below the wiring33is explained. If the through wirings50are provided right below the wirings31and32, the other end of each of the through wirings50that exposes from the other surface of the polyimide layer10faces the heat spreader80via the adhesion layer70including filler such as alumina or the like. As the wirings31and32are the electrical connection wirings, in particular, when the thickness of the adhesion layer70is thin (about 20 to 50 μm, for example), leakage may occur from the through wirings50to the heat spreader80via the adhesion layer70to lower the insulating property.

Thus in order to provide the through wirings50right below the wirings31and32, it is necessary to make the adhesion layer70thick to a certain extent (about 100 to 150 μm, for example) to ensure the insulating property. However, the adhesion layer70functions as a part of a thermal radiation path between the through wirings50and the heat spreader80. Thus, if the adhesion layer70is made thick in order to ensure the insulating property, heat resistance increases and the thermal radiation property is lowered. Thus, it is difficult to ensure the insulating property and the thermal radiation property at the same time when the through wirings50are provided right below the wirings31and32.

On the other hand, according to the present embodiment, as the through wirings50are not provided right below the wirings31and32, there is no risk of lowering of the insulating property even when the adhesion layer70is made thin (about 50 μm, for example) to lower heat resistance. Further, although the through wirings50are provided right below the wiring33, the wiring33is the thermal diffusion wiring and is not electrically connected to the semiconductor device or the like that is mounted on the wiring substrate1and current does not flow through the wiring33. Thus, even when the other end of each of the through wirings50faces the heat spreader80via the relatively thin adhesion layer70(about 20 to 50 μm, for example), leakage does not occur.

For example, dielectric breakdown voltage (kV) and heat resistance (° C./W) become as illustrated in Table 1 when the thickness of the adhesion layer70whose coefficient of thermal conductivity is 3 W/m·K is varied. Conditions A and B are relative examples in which the through wirings50are not provided at all. Further, conditions C and D are examples of the embodiment in which the through wirings50are not provided right below the wirings31and32but the through wirings50are provided only right below the wiring33(seeFIG. 1AandFIG. 1B). Here, values of heat resistance express heat resistance of a portion at which the plating film43is formed, in a thickness direction inFIG. 1A.

With reference to Table 1, for the condition A (the thickness of the adhesion layer70is 100 μm), dielectric breakdown voltage is 4.6 kV and heat resistance is 0.4° C./W. Further, for the condition B (the thickness of the adhesion layer70is 150 μm), dielectric breakdown voltage is 5.8 kV and heat resistance is 0.58° C./W. As such, when the thickness of the adhesion layer70becomes thicker, dielectric breakdown voltage is improved but heat resistance also increases.

On the other hand, for the condition C (the thickness of the adhesion layer70is 20 μm and the thickness of the through wirings50is 50 μm), dielectric breakdown voltage is 6.1 kV and heat resistance is 0.15° C./W. Further, for the condition D (the thickness of the adhesion layer70is 50 μm and the thickness of the through wirings50is 50 μm), dielectric breakdown voltage is 6.9 kV and heat resistance is 0.25° C./W. For the conditions C and D, compared with the conditions A and B, heat resistance is largely improved. In particular, by comparing the conditions B and D, it can be understood that according to the embodiment, heat resistance can be reduced to less than half while ensuring the same amount of the dielectric breakdown voltage.

As such, with a structure in which the through wirings50are not provided right below the wirings31and32but the through wirings50are provided only right below the wiring33, which is the thermal diffusion wiring and current does not flow therethrough, the insulating property can be ensured and the thermal radiation property can also be improved at the same time even when the relatively thin adhesion layer70is used.

(Method of Manufacturing Wiring Substrate of First Embodiment)

Next, a method of manufacturing the wiring substrate1of the first embodiment is explained.FIG. 2AtoFIG. 6Dare views illustrating an example of a method of manufacturing the wiring substrate1of the first embodiment. The cross-sectional views used for explaining the method of manufacturing the wiring substrate1of the first embodiment correspond toFIG. 1A.

First, in a step illustrated inFIG. 2A, a polyimide film in a reel form (or tape form) is prepared as the polyimide layer10, for example. Then, the adhesion layer20is formed on the one surface of the polyimide layer10by coating an epoxy-based adhesive agent or the like. Alternatively, instead of coating the epoxy-based adhesive agent or the like, the adhesion layer20may be formed by adhering an epoxy-based adhesive film on the one surface of the polyimide layer10. Then, the polyimide layer10and the adhesion layer20are provided with through holes10xthat penetrate the polyimide layer10and the adhesion layer20. The through holes10xmay be formed by punching, for example. Here, although the polyimide layer10or the like has a plurality of areas of which each becomes the wiring substrate1, only one of the areas that becomes the wiring substrate1is explained in the following.

Next, in a step illustrated inFIG. 2B, a metal layer30A is formed on the adhesion layer20. The metal layer30A finally becomes the wirings31to33after being patterned. Then, the adhesion layer20is cured by heating to a predetermined temperature. The metal layer30A may be formed by laminating a copper film on the adhesion layer20, for example. The thickness of the metal layer30A may be about 18 to 35 μm, for example. Thereafter, an upper surface of the metal layer30A and a lower surface of the metal layer30A exposed in each of the through holes10xare etched (so-called soft etching) by immersing the structure illustrated inFIG. 2Bin wet etching solution (hydrogen peroxide-based solution, for example). By this etching process, rust-inhibitor that exists at the surfaces of the metal layer30A is removed and the surfaces of the metal layer30A are also slightly (about 0.5 to 1 μm, for example) removed. This etching process is not essentially performed and may be performed in accordance with necessity.

Next, in a step illustrated inFIG. 2C, the through wirings50that are integrally connected to the metal layer30A are formed in the through holes10x, respectively. Specifically, first, a masking tape is adhered to the upper surface of the metal layer30A. The masking tape is provided to cover the upper surface of the metal layer30A in order to prevent generation of a plating film at the upper surface of the metal layer30A when forming the through wirings50by electroplating.

After adhering the masking tape, the through wirings50are formed by electroplating using the metal layer30A as a power supply layer. Then, the masking tape is removed. The through wirings50are formed by depositing plating metal at the lower surface of the metal layer30A that is exposed in each of the through holes10xand filling the plating metal in each of the through holes10x. Each of the through wirings50is formed to have a columnar shape. Each of the through wirings50is formed such that one end (an upper end inFIG. 2C) is connected to the metal layer30A and the other end (a lower end inFIG. 2C) is exposed from the other surface of the polyimide layer10.

The other end of the through wiring50may be flush with the other surface of the polyimide layer10, or may be protruded from the other surface of the polyimide layer10. When the other end of the through wiring50is flush with the other surface of the polyimide layer10, the thickness of the wiring portion Z can be made thinner and evenness of the wiring portion Z when being bonded to the heat spreader80can be ensured. When the other end of the through wiring50is protruded from the other surface of the polyimide layer10, surface area can be increased due to the protrusion and thermal radiation property can be improved. For the material of the through wirings50, copper (Cu) or the like may be used, for example.

Next, in a step illustrated inFIG. 3AandFIG. 3B(FIG. 3Bis a plan view andFIG. 3Ais a cross-sectional view taken along an A-A line inFIG. 3B), the metal layer30A is patterned to be formed into the wirings31to33. Further, although not illustrated in the drawings, a bus line connected to the wirings31to33is also formed with the wirings31to33. The bus line is used for forming the plating films41to45by electroplating in the following process. Specifically, the wirings31to33are formed by coating resist (not illustrated in the drawings) on the metal layer30A and exposing and developing the resist to have a pattern corresponding to the wirings31to33and the bus line, for example. Then, the metal layer30A is etched (patterned) using the resist to be the wirings31to33and the bus line. Thereafter, the resist is removed.

At this time, if a space T between the wiring33and the wiring31or32is narrow, when voltage is applied to the wiring31or32, opposite voltage is induced on the wiring33, that is in the vicinity of the wiring31or32. In such a case, there is a possibility that insulation reliability between the wiring33and the heat spreader80is reduced. Thus, it is preferable that the space T between the wiring33and the wiring31or32is sufficiently wide so that voltage is not induced on the wiring33.

Next, in a step illustrated inFIG. 4AandFIG. 4B(FIG. 4Bis a plan view andFIG. 4Ais a cross-sectional view taken along an A-A line inFIG. 4B), the insulating layer60(reflection film) that selectively exposes the wirings31to33is formed. In other words, the insulating layer60is formed to expose portions where the plating films41to45are formed. Specifically, the insulating layer60is formed to be provided with the open portions60xthat selectively expose the wirings31and32(electrical connection wiring) and the open portion60ythat selectively exposes the wiring33(thermal diffusion wiring).

Further, the insulating layer60is formed to fill the space T between the wiring31and the wiring33, and the space T between the wiring32and the wiring33. By forming the insulating layer60between the wirings31and32(electrical connection wiring) and the wiring33(thermal diffusion wiring), the insulating property and reflection efficiency can be improved.

For the material of the insulating layer60, a white-based material may be used, as described above. The insulating layer60may be formed by screen printing or the like, for example. Alternatively, the insulating layer60may be formed by forming white ink or the like to cover the entirety of the wirings31to33, and then exposing portions where the plating films41to45are formed by photolithography, blasting, laser processing or the like.

Here, it is preferable that the insulating layer60is formed to expose the outer edge portion20aof the adhesion layer20in each of the areas that becomes the wiring substrate1. With this configuration, as it is unnecessary to cut the insulating layer60when dicing (cutting) and dividing each of the areas, each of which finally becomes the wiring substrate1, chipping or removal of an edge of the insulating layer60can be prevented. With this, decreasing of a surface area of the insulating layer60can be prevented and lowering of reflectivity of the insulating layer can be prevented. Alternatively, the insulating layer60may be provided not to expose the outer edge portion20ain accordance with necessity (seeFIG. 6D).

Next, in a step illustrated inFIG. 5AandFIG. 5B(FIG. 5Bis a plan view andFIG. 5Ais a cross-sectional view taken along an A-A line inFIG. 5B), the plating films41to45are formed on the wirings31to33by electroplating. Specifically, for example, a masking tape is adhered to the other surface of the polyimide layer10. Then, electroplating is performed using an electric power supply path including the bus line connected to the wirings31to33to form the plating films41to45at the upper surfaces of the wirings31to33that are exposed from the insulating layer60. Thereafter, the masking tape is removed. The material, the thickness and the like of each of the plating films41to45are as described above.

Next, an outer edge portion (parts of the polyimide layer10, the adhesion layer20or the like that are exposed from the insulating layer60) of the structure illustrated inFIG. 5AandFIG. 5Bis cut and divided by press working, numerical control machining, laser processing or the like to form a plurality of the wiring portions Z of the wiring substrates1. At this time, the bus line connected to the wirings31to33is cut at the same time.

Next, the divided wiring portion Z is bonded on the heat spreader80via the adhesion layer70. Specifically, the adhesion layer70is formed by adhering a thermosetting epoxy-based adhesive film or the like including filler such as alumina or the like on the heat spreader80, for example. Then, the divided wiring portion Z is placed on the adhesion layer70. Then, the divided wiring portion Z is pressed toward a heat spreader80side while heating at predetermined temperature to cure the adhesion layer70. Alternatively, the adhesion layer70may be formed by coating liquid or paste thermosetting epoxy-based resin including filler such as alumina or the like on the heat spreader80by spin coating, for example. With the above steps, a plurality of the wiring substrates1(seeFIG. 1AandFIG. 1B) are formed.

Although the divided structure (wiring portion Z) is bonded to the heat spreader80via the adhesion layer70in the above described method, this is not limited so. For example, the adhesion layer70may be formed on the structure (wiring portion Z) in which the bus line is cut, and then, the structure (wiring portion Z) and the adhesion layer70may be divided. Next, the divided structure (wiring portion Z and the adhesion layer70) may be stacked on the heat spreader80by applying pressure at predetermined temperature. Further, the wiring portion Z may be divided with the adhesion layer70and the heat spreader80after being bonded to the heat spreader80via the adhesion layer70, for example. In such a process, side surfaces of the wiring portion Z, the adhesion layer70and the heat spreader80become flush with each other, for example. Here, in this embodiment, although the wiring portion Z, the adhesion layer70and the heat spreader80are formed to have the same plan shape (side surfaces thereof are flush with each other), this is not limited so. The wiring portion Z and the adhesion layer70may be formed to have a plan shape smaller than that of the heat spreader80, for example.

Here, instead of the steps illustrated inFIG. 3AtoFIG. 5B, steps illustrated inFIG. 6AtoFIG. 6Dmay be used. First, in a step illustrated inFIG. 6A, similar to the step illustrated inFIG. 3AandFIG. 3B, the wirings31to33and the bus lines (not illustrated in the drawings) connected to the wirings31to33are formed by patterning the metal layer30A.

Next, in a step illustrated inFIG. 6B, the plating films41to45are formed on the wirings31to33by electroplating. Specifically, a resist film510that selectively exposes predetermined portions (portions where the plating films41to45are formed inFIG. 1AandFIG. 1B) of the upper surface of the wirings31to33is formed on the adhesion layer20, for example. Further, a masking tape520is adhered to the other surface of the polyimide layer10. Then, the plating films41to45are formed on the portions of the upper surface of the wirings31to33that are exposed from the resist film510by performing electroplating using an electric power supply path including the bus line connected to the wirings31to33. The material, the thickness and the like of the plating films41to45are as explained above. Next, in a step illustrated inFIG. 6Cthe resist film510and the masking tape520are removed.

Next, in a step illustrated inFIG. 6D, similar to the step illustrated inFIG. 4AandFIG. 4B, the insulating layer60is formed on the predetermined portions (such as to expose the portions of the plating films41to45except their outer edge portions, for example) of the wirings31to33. InFIG. 6D, an example is illustrated in which the insulating layer60is provided such that the outer edge portion20aof the adhesion layer20is not exposed.

Finally, the outer edge portion of the structure illustrated inFIG. 6Dis cut and divided by press working or the like. Then, the divided structure is adhered to the heat spreader80via the adhesion layer70. With the above steps, a plurality of the wiring substrates1are formed.

Alternative Example 1 of the First Embodiment

In an alternative example 1 of the first embodiment, an example of a wiring substrate is explained in which areas where the through wirings are formed are different from those of the first embodiment. In the alternative example 1 of the first embodiment, the components same as those explained above are given the same reference numerals, and explanations are not repeated.

FIG. 7AandFIG. 7Bare views illustrating an example of a wiring substrate1A of the alternative example 1 of the first embodiment.FIG. 7Bis a plan view andFIG. 7Ais a cross-sectional view taken along an A-A line inFIG. 7B.

In the wiring substrate1of the first embodiment, the through wirings50are formed right below the wiring33that is exposed from the open portion60yof the insulating layer60(where the plating film43is formed). However, different from the wiring substrate1, in the wiring substrate1A, the through wirings50are formed right below the area of the wiring33that is covered by the insulating layer60, in addition to right below the wiring33that is exposed from the open portion60y(where the plating film43is formed). In other words, the plurality of through wirings50are formed right below the entirety of the wiring33. For example, the plurality of through wirings50may be provided as illustrated inFIG. 9B.

As such, by providing the plurality of through wirings50at the entirety of the wiring33, thermal radiation efficiency can be further improved.

Although the explanation and drawings of the plurality of through wirings50may be omitted in some examples, the variation of the structure of the through wirings50may be adaptable to all of the examples.

Alternative Example 2 of First Embodiment

In an alternative example 2 of the first embodiment, an example of a wiring substrate is explained in which the plan shape of a wiring at which the through wirings are formed is different from the wiring33of the first embodiment. In the alternative example 2 of the first embodiment, the components same as those explained above are given the same reference numerals, and explanations are not repeated.

FIG. 8AandFIG. 8Bare views explaining an example of a wiring substrate1B of the alternative example 2 of the first embodiment.FIG. 8Bis a plan view andFIG. 8Ais a cross-sectional view taken along an A-A line inFIG. 8B.

With reference toFIG. 8AandFIG. 8B, the wiring substrate1B is different from the wiring substrate1(seeFIG. 1AandFIG. 1B) in that the wirings31to33are substituted by wirings31B to33B. The wirings31B to33B are formed on the adhesion layer20to be smaller than the wirings31to33, respectively. In other words, the wirings31B to33B are only provided in the vicinity of areas where the plating films41to43are formed (area where the semiconductor device or the like is mounted).

As such, the wirings31B to33B may be only provided in the vicinity of the areas where the plating films41to43are formed (area where the semiconductor device or the like is mounted). By making the plan shape of the wiring33B, that is the thermal diffusion wiring, smaller, the thermal radiation property is lowered. However, the size of the thermal diffusion wiring may be appropriately determined based on a required thermal radiation property.

Second Embodiment

In the second embodiment, an example of a semiconductor package is explained in which a semiconductor device (light emitting device) is mounted on the wiring substrate1of the first embodiment. In the second embodiment, the components same as those explained above are given the same reference numerals, and explanations are not repeated.

FIG. 9AandFIG. 9Bare views illustrating an example of a semiconductor package100of the second embodiment.FIG. 9Bis a plan view andFIG. 9Ais a cross-sectional view taken along an A-A line inFIG. 9B. Here, in order to facilitate understanding of a positional relationship of semiconductor devices120and the through wirings50, the semiconductor devices120are expressed by grey patterns and components formed on the wiring substrate1other than the semiconductor devices120are not illustrated inFIG. 9B.

With reference toFIG. 9AandFIG. 9B, the semiconductor package100includes the wiring substrate1(seeFIG. 1AandFIG. 1B), the semiconductor devices120, solder (not illustrated in the drawings) and sealing resin140. The semiconductor devices120are mounted on the plating films41and42above the wirings31and32(electrical connection wirings) at the open portions60xexposed from the insulating layer60and on the plating film43above the wiring33(diffusion wiring) at the open portion60yexposed from the insulating layer60, of the wiring substrate1. Specifically, each of the semiconductor devices120includes electrical connection terminals130and a thermal diffusion terminal135. The semiconductor devices120are flip-chip mounted on the wirings31and32(plating films41and42) that are the electrical connection wirings, and the wiring33(plating film43) that is the thermal diffusion wiring on the wiring substrate1via the solder (not illustrated in the drawings) in a face-down manner. Then, the semiconductor device120is sealed by the sealing resin140. For the sealing resin140, resin in which a fluorescent material is included in insulating resin such as epoxy-based resin, silicone-based resin or the like may be used, for example. Although an example in which the two semiconductor devices120are mounted on the wiring substrate1in parallel is illustrated inFIG. 9AandFIG. 9B, the number of the semiconductor devices120mounted on the wiring substrate1may be arbitrarily determined.

An anode terminal and a cathode terminal are provided at lower surfaces (surfaces facing the wiring substrate1) of the electrical connection terminals130of each of the semiconductor devices120, for example. For the semiconductor device120, a light emitting device such as a Light Emitting Diode (LED) may be used. However, the light emitting device is not limited to the LED and a surface-emitting laser or the like may be used, for example. Here, an example in which the semiconductor device120is the LED is explained in the following.

One of the electrical connection terminals130of the semiconductor device120is connected to the plating film41of the wiring substrate1via the solder (not illustrated in the drawings), for example. Further, the other of the electrical connection terminals130of the semiconductor device120is connected to the plating film42of the wiring substrate1via the solder (not illustrated in the drawings), for example. Further, the thermal diffusion terminal135is provided in the vicinity of a center portion of the lower surface of the semiconductor device120. The thermal diffusion terminal135is connected to the plating film43of the wiring substrate1via the solder (not illustrated in the drawings).

As described above in the first embodiment, in the wiring substrate1, the wiring33that is the thermal diffusion wiring is formed to have a larger area than that of the thermal diffusion terminal135of the semiconductor device120. Thus, the heat generated by the semiconductor device120can be efficiently diffused in a surface direction of the wiring33.

For example, by connecting the plating films44and45of the wiring substrate1to a power source, a drive circuit or the like provided outside of the semiconductor package100, and supplying a predetermined potential difference between the electrical connection terminals130of the semiconductor device120, the semiconductor device120emits light. The semiconductor device120generates heat when emitting light. The heat generated by the semiconductor device120is transferred to the through wirings50via the plating film43and the wiring33. Then, the heat is further transferred to the heat spreader80via the adhesion layer70so that the heat is radiated by the heat spreader80. As the plurality of through wirings50are provided at the lower side of the thermal diffusion terminal135of the semiconductor device120, the heat generated by the semiconductor device120can be efficiently transferred to the heat spreader80.

Alternative Example 1 of Second Embodiment

In an alternative example 1 of the second embodiment, another example of a semiconductor package in which a semiconductor device (light emitting device) is mounted on the wiring substrate1of the first embodiment is explained. In the alternative example 1 of the second embodiment, the components same as those explained above are given the same reference numerals, and explanations are not repeated.

FIG. 10AandFIG. 10Bare views illustrating an example of a semiconductor package100A of the alternative example 1 of the second embodiment.FIG. 10Bis a plan view andFIG. 10Ais a cross-sectional view taken along an A-A line inFIG. 10B. Here, in order to facilitate understanding of a positional relationship of the semiconductor devices120and the through wirings50, the semiconductor devices120are expressed by grey patterns and components formed on the wiring substrate1other than the semiconductor device120are not illustrated inFIG. 10B.

With reference toFIG. 10AandFIG. 10B, the semiconductor package100A includes the wiring substrate1(seeFIG. 1AandFIG. 1B) and semiconductor modules110. For the example illustrated inFIG. 10AandFIG. 10B, two of the semiconductor modules110are mounted on the plating films41and42above the wirings31and32(electrical connection wirings) at the open portions60xexposed from the insulating layer60and on the plating film43above the wiring33(diffusion wiring) at the open portion60yexposed from the insulating layer60, of the wiring substrate1. Although an example in which the two semiconductor modules110are mounted on the wiring substrate1in parallel is illustrated inFIG. 10AandFIG. 10B, the number of the semiconductor modules110mounted on the wiring substrate1may be arbitrarily determined.

In each of the semiconductor modules110, wirings161to163are formed in the substrate150. The wirings161and162are electrical connection terminals that are electrically connected to the semiconductor device120. Further, the wiring163is not electrically connected to the semiconductor device120. The wiring163is a thermal radiation terminal that functions as a semiconductor device mounting portion and has a thermal radiation function. The semiconductor device120(LED) is mounted on the upper surface of the wiring163in a face-up manner. Further, the wirings161and162are electrically connected to the anode terminal and the cathode terminal (not illustrated in the drawings) of the semiconductor device120via bonding wires180at upper surfaces, respectively. A reflector170that reflects light emitted by the semiconductor device120is mounted at an outer edge portion of an upper surface of the substrate150. Further, sealing resin140that seals the semiconductor device120is provided inside the reflector170.

Lower surfaces of the wirings161and162are exposed from a lower surface of the substrate150and are connected to the wirings31and32(plating films41and42), which are the electrical connection wirings, of the wiring substrate1via solder139, respectively. A lower surface of the wiring163is exposed from the lower surface of the substrate150and is connected to the wiring33(plating film43), which is the thermal diffusion wiring, of the wiring substrate1via the solder139. In the wiring substrate1, the wiring33is formed to have a larger area than that of the thermal radiation terminal (wiring163) of the semiconductor module110, as explained in the first embodiment. Thus, heat generated by the semiconductor device120can be effectively radiated.

For example, by connecting the plating films44and45of the wiring substrate1to a power source, a drive circuit or the like provided outside of the semiconductor package100A, and supplying a predetermined potential difference between the cathode terminal and the anode terminal of the semiconductor device120, the semiconductor device120emits light. The semiconductor device120generates heat when emitting light. The heat generated by the semiconductor device120is transferred to the through wirings50via the wiring163(thermal radiation terminal), the plating film43and the wiring33. Then, the heat is further transferred to the heat spreader80via the adhesion layer70so that the heat is radiated by the heat spreader80. As the plurality of through wirings50are provided at the lower side of the thermal radiation terminal of the semiconductor module110, the heat generated by the semiconductor device120can be efficiently transferred to the heat spreader80.

Alternative Example 2 of Second Embodiment

In an alternative example 2 of the second embodiment, another example of the semiconductor package in which the semiconductor device (light emitting device) is mounted on the wiring substrate1of the first embodiment is explained. In the alternative example 2 of the second embodiment, the components same as those explained above are given the same reference numerals, and explanations are not repeated.

FIG. 11AandFIG. 11Bare views illustrating an example of a semiconductor package100B of the alternative example 2 of the second embodiment.FIG. 11Bis a plan view andFIG. 11Ais a cross-sectional view taken along an A-A line inFIG. 11B. Here, in order to facilitate understanding of a positional relationship of the semiconductor devices120and the through wirings50, the semiconductor devices120are expressed by grey patterns and components formed on the wiring substrate1other than the semiconductor device120are not illustrated inFIG. 11B.

With reference toFIG. 11AandFIG. 11B, in the semiconductor package100B, the semiconductor devices120are mounted on the plating film43above the wiring33at the open portion60yof the insulating layer60exposed from the insulating layer60, of the wiring substrate1. Specifically, each of a plurality of the semiconductor devices120is mounted on the plating film43of the wiring substrate1via an adhesion layer190such as a die attach film or the like in a face-up manner. Each of the semiconductor devices120is sealed by the sealing resin140. Although an example in which the four semiconductor devices120are mounted on the wiring substrate1is illustrated inFIG. 11AandFIG. 11B, the number of the semiconductor devices120mounted on the wiring substrate1may be arbitrarily determined.

Two of the semiconductor devices120aligned in a shorter direction (in a direction in which the plating films41to45are aligned) are connected in series via the bonding wire180. For example, the anode terminal of one of the semiconductor devices120aligned in the shorter direction of the plating film43and the cathode terminal of the other of the semiconductor devices120aligned in the shorter direction of the plating film43are connected via the bonding wire180. Then, for example, the cathode terminal of the one of the semiconductor devices120is connected to the plating film41via another bonding wire180, and the anode terminal of the other of the semiconductor devices120is connected to the plating film42via another bonding wire180. Further, two combinations of the two semiconductor devices120aligned in the shorter direction of the plating film43and electrically connected in series are aligned in a longer direction of the plating film43and electrically connected in parallel.

In the wiring substrate1, the wiring33(thermal diffusion wiring) is formed to have a larger area than a plan shape of the semiconductor device120, which is to be mounted on the wiring substrate1. Thus, the heat generated by the semiconductor device120can be efficiently radiated.

For example, by connecting the plating films44and45of the wiring substrate1to a power source, a drive circuit or the like provided outside of the semiconductor package100B, and supplying a predetermined potential difference between the cathode terminal and the anode terminal of each of the semiconductor devices120, the semiconductor device120emits light. The semiconductor device120generates heat when emitting light. The heat generated by the semiconductor devices120is transferred to the through wirings50via the plating film43and the wiring33. Then, the heat is further transferred to the heat spreader80via the adhesion layer70so that the heat is radiated by the heat spreader80. As the plurality of through wirings50are provided at the lower side of the wiring33on which the semiconductor devices120are mounted, the heat generated by the semiconductor devices120can be efficiently transferred to the heat spreader80.

Although the semiconductor package is explained with reference toFIG. 9AtoFIG. 11B, preferable positional relationships between an outer shape of the semiconductor device120and the through wirings50in the semiconductor package are explained with reference toFIG. 12AtoFIG. 12D.

FIG. 12AtoFIG. 12Dare views for explaining a positional relationship between an outer shape of the semiconductor device120and the through wirings50. As illustrated inFIG. 12AtoFIG. 12D, it is preferable that at least a part of the through wiring50is placed within a range of an outer shape of the semiconductor device120in a plan view. Further, it is preferable that two or more of the through wirings50are placed within the range of the outer shape of the semiconductor device120in a plan view.

For example, as illustrated inFIG. 12A, all of the four through wirings50may be placed within the range of the outer shape of the semiconductor device120in a plan view. The number of the through wirings50placed within the range of the outer shape of the semiconductor device120may be one, two, three or more than four. As described above, it is preferable that the number of the through wirings50placed within the range of the outer shape of the semiconductor device120is two or more.

Further, as illustrated inFIG. 12BandFIG. 12C, a part of each of the through wirings50may not be placed within the range of the outer shape of the semiconductor device120provided that at least parts of two of the through wirings50are placed within the range of the outer shape of the semiconductor device120, in a plan view. Further, the through wirings50may be placed in various arrangements such as two of them are at a diagonal with each other with respect to a side of the outer shape of the semiconductor device120, or two of them are placed to face with each other with respect to a side of the outer shape of the semiconductor device120.

Further, as illustrated inFIG. 12D, the entirety of one of the through wirings50may be within the range of the outer shape of the semiconductor device120and a part of the other of the through wirings50may be within the range of the outer shape of the semiconductor device120provided that at least two through wirings50are placed to overlap the range of the outer shape of the semiconductor device120, in a plan view. Further, the through wirings50having different plan shapes may be placed to overlap the range of the outer shape of the semiconductor device120.

As illustrated inFIG. 12AtoFIG. 12D, the thermal radiation property can be further improved by providing the plurality of through wirings50such that at least a part of each of the through wirings50overlap the region within the outer shape of the semiconductor device120in a plan view.

In other words, for example, if only a single through wiring50is placed within the range of the outer shape of the semiconductor device120in a plan view, heat tends to be concentrated on the single through wiring50. Thus, thermal radiation effects may decrease. However, by providing the plurality (two or more) of through wirings50such that at least a part of each of them overlaps the region within the outer shape of the semiconductor device120, concentration of heat can be prevented and the thermal radiation property can be improved.

Third Embodiment

In the third embodiment, an example is illustrated in which the wiring substrate includes the through wiring that are protruded from the polyimide layer. In the third embodiment, the components same as those explained above are given the same reference numerals, and explanations are not repeated.

FIG. 13is a cross-sectional view illustrating an example of a wiring substrate1C of the third embodiment. The other ends of the through wirings50may have protruding portions that are protruded from the other surface of the polyimide layer10, respectively, as described above. In such a case, as the wiring substrate1C illustrated in FIG.13, the protruding portions of the adjacent through wirings50may contact with each other. Further, in the wiring substrate1C, the diameters of the through wirings50may be the same or may be different. Further, in the wiring substrate1C, the diameters or the protruding amounts of the protruding portions of the through wirings50may be the same or may be different.

By forming the through wirings50such that the other ends of the through wirings50are protruded from the other surface of the polyimide layer10to the extent that the protruding portions of the adjacent through wirings50contact with each other, surface areas of the other ends of the through wirings are greatly increased. Thus, the thermal radiation property can further be improved.

FIG. 14is a cross-sectional view illustrating an example of a semiconductor package200of the third embodiment. In the semiconductor package200illustrated inFIG. 14, a heat generation semiconductor device210, other than the light emitting device, is flip-chip mounted on the wiring substrate1C via solder220in a face-down manner.

Specifically, electrical connection terminals (not illustrated in the drawings) of the semiconductor device210are connected to the wirings31and32(plating films41and42), which are the electrical connection wirings, via the solder220on the wiring substrate1C. Further, a thermal diffusion terminal (not illustrated in the drawings) of the semiconductor device210is connected to the wiring33(plating film43), which is the thermal diffusion wiring, via the solder220on the wiring substrate1C. The number of the semiconductor devices210to be mounted on the wiring substrate1C may be arbitrarily determined.

For the semiconductor device210, a known heat generation semiconductor device that generates heat when being operated may be used. As an example of the semiconductor device210, a power semiconductor device or the like such as an Insulated Gate Bipolar Transistor (IGBT), a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) or the like may be used.

As such, the semiconductor device to be mounted on the wiring substrate1C is not limited to the light emitting device and a known heat generation semiconductor device that generates heat by current that flows when being operated may be mounted. As the wiring substrate1C has a good thermal radiation property, a thermal radiation property of the heat generation semiconductor device that is mounted on the wiring substrate1C can be improved and a problem caused by heat can be reduced. Similarly, the heat generation semiconductor device may be mounted on the wiring substrate1,1A or1B.

As described above, when the semiconductor device is the light emitting device, it is preferable that a reflection film made of white ink or the like is used as the insulating layer60in order to increase reflectivity of the light emitted by the light emitting device and to increase thermal diffusivity. However, when the heat generation semiconductor device other than the light emitting device is mounted, it is unnecessary to use the reflection film as the insulating layer60, and the insulating layer60may be formed to have a function different from the reflection film. For example, a solder resist layer may be used as the insulating layer60. Further, various insulating layers made of epoxy-based resin, polyimide-based resin or the like may be used as the insulating layer60. Further, the insulating layer60may not be formed, in accordance with necessity.

According to the embodiment, a wiring substrate or the like capable of ensuring an insulation property and improving a thermal radiation property at the same time can be provided.

Although a preferred embodiment of the wiring substrate or the like has been specifically illustrated and described, it is to be understood that minor modifications may be made therein without departing from the spirit and scope of the invention as defined by the claims.

The present invention is not limited to the specifically disclosed embodiments, and numerous variations and modifications may be made without departing from the spirit and scope of the present invention.

For example, as illustrated inFIG. 11AandFIG. 11B, when the semiconductor device120is mounted in a face-up manner, and the back surface of the semiconductor device120and the plating film43are connected via the adhesion layer190without being connected by solder or the like, the entirety of the wiring33may be covered by the insulating layer60without providing the plating film43. In other words, the insulating layer60may not be provided with the open portion that exposes the wiring33. In such a case, the semiconductor device120is mounted on the insulating layer60that covers the wiring33via the adhesion layer190. In other words, the insulating layer60exists right below the semiconductor device120.

Further, instead of adhering the metal layer30A to the polyimide layer10via the adhesion layer20, the following method may be used. That is, a method of repairing a polyimide layer10that is a polyimide-based resin film (polyimide tape) or the like, and forming a metal layer made of copper (Cu) or the like directly on the one surface of the polyimide layer10by electroless plating, sputtering, electroplating or the like (adhesion layer20is not provided) may be used. In such a case, the metal layer formed as such has the same function as the metal layer30A and functions as the metal layer30A. In such a case, the through holes10xare only formed in the polyimide layer10by laser processing or the like. In other words, one ends of the through holes10xare covered by the metal layer formed on the polyimide layer10. In this case, the adhesion layer20is not provided.

Further, as another example, the polyimide layer10may be formed by coating polyimide-based insulating resin on a metal film such as a copper film or the like. In such a case as well, the through holes10xare only formed in the polyimide layer10by laser processing or the like. In other words, one ends of the through holes10xare covered by the metal film formed on the polyimide layer10. In this case as well, the adhesion layer20is not provided.