I/Q demodulator device with three power detectors and two A/D converters

The present invention relates to a method and a device for the I/Q demodulation of modulated RF signals. The I/Q demodulator (60) has a first input for the RF signal (61) to be demodulated and a second input for a RF signal (62) originating from a local oscillator (20). The demodulator (60) combines the two RF signals (61,62) to generate three output signals supplied to three power detectors. In a combination unit (70) the three power signals of the power detectors are merged in two signal branches wherein after passing an A/D converting (72) and digital processing unit (73) one signal is the I component and the other one is the Q component of the received modulated RF signal (61).

The present invention relates to a method and a device for the I/Q demodulation of modulated RF signals. The invention furthermore relates to a telecommunications device comprising such a demodulating device.

A six-port receiver is known acting in a direct conversion manner and allowing conversion from millimeter wave range and microwave range directory to the base band. The six-port receiver detects the relative phase and relative magnitude of two incoming RF-signals by using the information of superimposed RF signals. At the same time a classic I/Q demodulation chip (digital or analog) can be avoided. By using suitable calibration procedures the influences of the non-ideal, linear RF-components including manufacturing tolerances can be minimized. The circuitry of the six-port receiver is realized using only passive components in combination with power sensors for the detection of the relative phase and the relative magnitude of the RF-signals as shown in EP-A-0896455.

In Bossisio, Wu “A six-port direct digital millimeter wave receiver”, Digest of 1994 IEEE MTT Symposium, vol. 3, page 1659–1662, San Diego, May 1994, a structure for a six-port receiver is proposed.

The six-port technique has been known for its ability to accurately measure the scattering parameters, both amplitude and phase, of microwave networks. Instead of using heterodyne receivers a six-port receiver accomplishes direct measurements at microwave and mm-wave frequencies by extracting power levels at at least three different ports. The imperfections of the hardware can be readily eliminated by an appropriate calibration procedure. Very accurate measurements can be made in a large dynamic range and wide frequency range. Six-port junction receivers consist of microwave components such as e.g. directional couplers and power dividers as well as power sensors. The circuit can be easily integrated as MHMIC or MMIC. The known receiver performs direct phase/amplitude demodulation at microwave and mm-wave frequencies.

By performing a calibration procedure the hardware imperfections can be readily eliminated. This significantly eases the requirement of the hardware implementation and enables the six-port receiver to operate over a wide band up to mm-wave frequencies.

According to the above cited document of Bossisio et. al. a six-port receiver concept with power dividers and 90 degrees hybrid circuits realized in distributed technology is used. The application of that known structure lies mainly in the frequency bands above 10 GHz, however, it suffers from an insufficient band width of the operation due to the inherently frequency selective nature of the 90 degree hybrid circuits.

From D. Maurin, Y. Xu, B. Huyart, K. Wu, M. Cuhaci, R. Bossisio “CPW Millimeter-Wave Six-Port Reflectometers using MHMIC and MMIC technologies”, European Microwave Conference 1994, pp. 911–915, a wide-band topology for reflectometer used is known which is based on a distributing element approach featuring coplanar wave guide applications in the frequency range from 11 to 25 GHz.

From V. Bilik, et al. “A new extremely wideband lumped six-port reflectometer” European Microwave Conference 1991, pp. 1473–1477 and the idea of using Wheatstone Bridges and resistive structures for reflectometer applications is known.

From Li, G. Bossisio, K. Wu, “Dual tone Calibration of Six-Port Junction and its application to the six-port direct digital receiver”, IEEE Transactions on Microwave Theory and Techniques, vol. 40, January 1996 a six-port reflectometer topology based on four 3 dB hybrid circuits, power dividers and attenuators is known.

From U.S. Pat. No. 5,498,969 an asymmetrical topology for a reflectometer structure featuring one matched detector and three unmatched detectors is known.

From U.S. Pat. No. 4,521,728 with the title “Method and six-port network for use in determining complex reflection coefficients of microwave networks” a reflectometer six-port topology is known comprising two different quadrate hybrids, phase shifter, two power dividers and one directional coupler for which the realization by a microstrip line technology is disclosed.

From EP-A-0 805 561 a method for implementing a direct conversion receiver with a six-port junction is known. According to this known technique, modulated transmitted modulation is received by a direct conversion receiver which comprises a six-port junction. The demodulation is carried out in an analog manner.

From EP-A-0 841 756 a correlator circuit for a six-port receiver is known. In this correlator circuit the received signal is summed up with a local oscillator signal at various phase angles, wherein the phase rotation between the local oscillator and RF signals is carried out separately from the summing of the correlator outputs.

From EP 0 957 573 A1 a five port junction device for processing (down conversion etc.) of RF signals is known. According toFIG. 5the device comprises one passive four-port means41being connected with a passive three-port means42by a phase-shifting element43. The passive four-port means41comprises a port44for the input of a first RF signal and two output ports. The passive three-port means42comprises a second port44for the input of a second RF signal and one output port. The output ports respectively provide output signals being linear combinations of the first and the second RF input signal. Power sensors P1, P2, P3are provided to detect the respective power levels of the output signals. Respectively one power sensor can be connected to one of said output ports and a signal processing unit45is provided to calculate the complex ratio of the first and second input RF signals on the basis of the power level values detected and output by the power sensors P1, P2, P3.

The disadvantage of this five port junction device is that three A/D converters are necessary.

From EP 0 957 614 A1 a n-port demodulator for PSK or QAM signals is known. In the case of n=5 the I/Q-demodulator thereby comprises a passive five-port junction device1as it is described above. According toFIGS. 6 and 7, three power detectors P1, P2, P3are then provided being supplied with analog signals output of the five-port junction device1. The analog circuitry2,3detects I/Q components of the signal to be demodulated based on an analog processing of the analog signals output of the power detectors P1, P2, P3. A local oscillator circuitry20is provided to supply a second input signal for the five-port junction device1. Filters4are provided for filtering the analog signals output of the power detectors P1, P2, P3before they are supplied to the analog circuitry2,3. The analog circuitry3comprises circuits7to supply the analog signals output of the power detectors P1, P2, P3respectively in two branches. Furthermore amplifiers8with individually adjustable gain (g1, g2, g3, g4, g5, g6, g7, g8) are provided to amplify the branches. Finally an adding/subtracting circuitry9,10is provided being supplied with the individually amplified branches to detect I/Q components of the RF signal to be demodulated (signal1). In the I/Q output circuit33, for example, an A/D conversion of the input I and Q components can be effected.

The disadvantage of this five-port demodulator is that the analog processing part2,3is more complex due to the high number of DC amplifiers and subtracting and adding circuitries. Furthermore this approach doesn't allow for calibration procedures to be easily applied.

It is the object of the present invention to provide an I/Q demodulator and a method for demodulating which utilizes a more simple analog processing and which reduce the number of A/D converters to two. This approach reduces and optimizes the complexity of the hardware as well as the power consumption. At the same time the calibration characteristics are left unchanged.

This object is achieved by means of the features of the independent claims. The dependent claims develop further the central idea of the invention.

According to the present invention an I/Q demodulator is provided. The demodulator has a first input for the RF signal to be demodulated and a second input for a RF signal originating from a local oscillator, wherein the two RF signals are combined to generate three output signals for three power detectors. A combination unit is provided for combining the three power signals of the power detectors to two signal branches.

One of the three power signals can be split in two subbranches.

The signals of the two subbranches can be adjustable.

Each subbranch can be combined with respectively one of the remaining two power signals by an adder.

Each of the signal branches can be supplied to an A/D converter.

The outputs of the A/D converter can be supplied to a digital processing unit.

Furthermore a mobile communication device comprising an I/Q demodulator as set forth is proposed.

According to the present invention furthermore a method for demodulating a high frequency signal is provided. Thereby three output signals for power detectors are generated by combining the RF signal to be demodulated with a second RF signal originating from a local oscillator. The three power signals of the power detectors are combined to two signal branches.

Further advantageous features of the method according to the present invention are defined in the subclaims.

InFIG. 1the new structure of the proposed I/Q demodulator60according to the invention is shown. It comprises three power detectors, two A/D converters, no additional mixing circuits (no nonlinear elements for providing mixing process ) and one digital processing unit. By combination of a modulated RF signal61with a RF signal62originating from a local oscillator the calculation of the I/Q values can be performed.

As it can be seen inFIG. 2the combination of the modulated RF signal61with the second RF signal62is made in a five-port structure63which outputs and supplies three signals, originating from the three power detectors, to an associated assembly64.

The assembly64is shown inFIG. 3comprising an analog circuit board2and an A/D conversion and digital processing unit53. The output signals of the power detectors P1, P2, P3are respectively input to an amplifier50with optionally adjustable gain G1, G2, G3. The gain of the amplifiers50with adjustable gain thereby can be optionally controlled by the control bus54. The output signals of the amplifiers50are input to a subboard containing analog circuitry51. The subboard51can also be optionally controlled by means of the control bus54. The subboard51is connected to an A/D conversion and digital processing unit53which outputs the I component and the Q component of the thus demodulated RF signal.

FIG. 4shows the internal structure of the subboard51comprised in the analog circuit board2. One of the input signals P1, is divided in two branches by means of a functional divider7. Optionally each of the thus generated branches is then respectively amplified and inverted by a DC amplifier8(by supplying it to the inverted input of the operational amplifier), wherein the gain g1, g2of the DC amplifier8can also be controllably adjusted by means of the control bus54. The amplified output signals are given to two adding circuits10where they are combined with the non amplified input signals P2, P3to generate output signals X1, X2of the combination processing unit70.

Note that alternatively to the DC amplifiers8attenuators with an adjustable attenuation rate can be provided depending on the application. If the signal P1is not inverted along with the amplification, additional inverters may be provided or the adders may be replaced by subtracting units subtracting the signal P1from the other output signals of the power amplifier.

Note that the combination processing unit70is operating in an analog manner and only comprises analog elements.

The functional dividers7, the DC amplifiers8and the adding circuits represent therefore a combination unit70for combining the three output signals of the power sensors to two signals X1, X2in a adjustable manner. The two output signals of the combination unit70can be optionally DC amplified71and then respectively supplied to an A/D converter72. The digital outputs of the A/D converters72are further provided to a digital processing unit73where after the calculation of the digitized signals the I component and the Q component of the received modulated RF signal are given to the outputs. The calculation of the I/Q values of the modulated RF signal61is therefore effected in a digital manner (in contrast to the analog processing of the combination unit70).

Considering the topology example of theFIG. 1andFIG. 2we can consider following relation in the case when Si presents the modulation of the RF signal and Signal S2presents the complex value of the local oscillator (In the following equations a reference phase of the local oscillator is considered to be zero).
s1=S0d eJφ(1)
s2=S0(2)

The I/Q demodulator actually detects the complex ratio of the signals S1and S2, or relative amplitude and phase related to the local oscillator. The amplitude ratio is d and φ presents phase difference.⁢s=s1s2=d⁢⁢ⅇJφI=d⁢⁢cos⁢⁢φQ=d⁢⁢sin⁢⁢φ(3)

The topology of theFIG. 1results in the following complex values (v1, v2 and v3) which are approaching the power sensors. Coefficients kmnare representing transfer functions from port n to the power sensor port m.
v1=k11s1, k12=0  (4)
v2=k21s1+k22e−jθs2(5)
v3=k31e−Jθs1+k32s2(6)
v1=k11S0d eJφ(7)
v2=k21S0d eJφ+k22S0e−jθ(8)
v3=k31S0d eJ(φ−θ)+k32S0(9)

We are assuming that signal S2has a constant value, meaning for example that the LO does not change its signal power level. In that case we can introduce the new variable VDC, like in (10).
VDC=C|s2|2=CS02−set DC voltage  (10)
P1=C|v1|2=Ck112S02d2(11)
P2=C|v2|2=CS02[k212d2+k22+2k21k22dcos(φ+θ)]  (12)
P3=C|v3|2=CS02[k312d2+k32+2k31k32dcos(φ−θ)]  (13)

P1, P2and P3are low frequency (quasi DC voltages) which exist after power detection by ideal diodes. The value of θ corresponds to the phase shift value from the five port structure and may considered as a constant.P2=k212k112⁢P1+k222⁢VDC+2⁢k21⁢k22⁢VDC⁢d⁢⁢cos⁢⁢(φ+θ)(14)P3=k312k112⁢P1+k322⁢VDC+2⁢k31⁢k32⁢VDC⁢d⁢⁢cos⁢⁢(φ-θ)(15)

After subcontracting power P1, multiplied with the related constant in equation (14) and (15) we may obtain two new equations with two unknown values:X1=P2-k212k112⁢P1=k222⁢VDC+2⁢k21⁢k22⁢VDC⁡(I⁢⁢cos⁢⁢θ-Q⁢⁢sin⁢⁢θ)(16)X2=P3-k312k112⁢P1=k322⁢VDC+2⁢k31⁢k32⁢VDC⁡(I⁢⁢cos⁢⁢θ-Q⁢⁢sin⁢⁢θ)(17)

The combination unit70implements the above equations (16) and (17). As it can be seen from (16) and (17) the multiplication coefficientsk212k112⁢⁢and⁢⁢k312k112
associated with P1are implemented by the gains g1, g2of the amplifiers8of the combination unit70. For most of the practical architectures they are less than one. An implementation may therefore be achieved by using an adjustable attenuator structure instead of an analog inverted amplifier as shown in the drawings.

The values of the output signals X1and X2are then sampled by two A/D converters and supplied to the digital processing unit. In order to calculate the I/Q values following calculations are performed in the digital domain:I=k21⁢k23+k22⁢k314⁢k21⁢k31⁢cos⁢⁢θ+14⁢k21⁢k22⁢VDC⁢cos⁢⁢θ⁢X1+14⁢k31⁢k32⁢VDC⁢cos⁢⁢θ⁢X2(18)Q=-k21⁢k23-k22⁢k314⁢k21⁢k31⁢sin⁢⁢θ-14⁢k21⁢k22⁢VDC⁢sin⁢⁢θ⁢X1+14⁢k31⁢k32⁢VDC⁢sin⁢⁢θ⁢X2(19)

In two special cases, when the phase shift is 45°, we obtain a simplified equations for I and Q outputs (20–23)Case⁢⁢1:⁢θ=45⁢°;⁢k11=12;⁢k12=0;⁢k21=14;⁢k22=14;⁢k31=18;⁢k32=12;I=-5⁢24+4⁢2VDC⁢(X2+X1)(20)Q=-3⁢24+4⁢2VDC⁢(X2-X1)(21)Case⁢⁢2:⁢θ=45⁢°;⁢k11=13;⁢k12=0;⁢k21=13;⁢k22=14;⁢k31=16;⁢k32=12;I=-15⁢216+3⁢2VDC⁢(X2+X1)(22)Q=-9⁢216+3⁢2VDC⁢(X2-X1)(23)