Method and apparatus for frequency compensation for multi-band VCO

A method and apparatus for frequency compensation for multi-band VCO have been disclosed where a VCO tank loading capacitance is adjusted slowly to allow VCO operation in a linear range.

FIELD OF THE INVENTION

The present invention pertains to current Voltage Controlled Oscillators (VCO). More particularly, the present invention relates to a method and apparatus for frequency compensation for multi-band VCO.

BACKGROUND OF THE INVENTION

In recent years, wideband high performance synthesizers have been widely employed in various applications, most of which are implemented with a multi-band VCO to cover a wide frequency range, as shown, for example, generally at300inFIG. 3. It is preferable to have a small gain for VCO to achieve better performance. Unfortunately, however, this gain must be able to cover the frequency deviations due to temperature change, and crystal wander, because it is undesirable to change the band control code (D<0:n>) once the synthesizer has been locked. This frequency deviation is generally at least several percentages around the center oscillation frequency. What's more, if the center frequency is very high, the issue is more severe. For instance, if the center frequency is 6 GHz, the frequency deviation is 20000 ppm, and the control voltage range is 1V, the corresponding VCO gain should be 240 MHz/V. This value is usually unacceptable in high performance synthesizer design. Thus, it is urgently desirable to find a technique to decouple this trade-off.

SUMMARY OF THE INVENTION

A method and apparatus for frequency compensation for multi-band VCO is disclosed. In one approach an apparatus using a state machine driven by comparing control voltages slowly adds or removes capacitance to the multi-band VCO are disclosed. These and other embodiments of the present invention are described in the writings and drawings herewith.

DETAILED DESCRIPTION

In one embodiment of the invention, a novel frequency compensation technique, which compensates for frequency offset caused by temperature changes, and crystal wandering operates in the background. The technique makes a VCO with very small tuning gain feasible.

FIG. 4illustrates, generally at400, one embodiment of the invention showing a circuit topology. InFIG. 4, the Multi-band VCO422with outputs424and426is, for example, as shown inFIG. 3generally at300, and outputs308and310respectively. Two varactor banks, which are shown in dashed box labeled I and II (416, and414) respectively, are added at the output nodes (424,426) of the multi-band VCO (422). Each varactor bank includes (m+1) varactor pairs with the same variable capacitance ΔC (shown representatively at428). VH408is input to comparator405, VLis input to comparator403, and VC402(such as at306inFIG. 3) is input to comparators at403and405. The output410of comparator405is fed into State Machine412. The output406of comparator403is fed into State Machine412. State Machine412has a series of outputs VCL<0 . . . m> and VCH<0 . . . m> represented respectively413and415entering414and416respectively. At420is a representative large capacitor Cbig.

FIG. 5illustrates, generally at500, one embodiment of the invention showing an example of the frequency compensation technique working. When the digital band selection mechanism (not shown) has selected an optimum working band in sub-bands of a multi-band VCO (the solid curve509inFIG. 5), and the synthesizer eventually is locked at point A (510), the synthesizer would operate at a fixed frequency corresponding to point A (labeled working frequency). And the synthesizer should lock at this frequency every time and its performance is kept stable, if no other operation is executed. However, as time passes, the temperature may change or the crystal reference clock may wander, which leads to a frequency deviation (Δf) (520) and the synthesizer may lock instead at point B (512). The point B (512) is located out of the linear region (shown inFIG. 5at522) of the synthesizer, and the synthesizer performance would degrade greatly. To avoid this, one could increase the gain of the tuning curve as the traditional way does mentioned in the background section, or use the technique presented herein to compensate this frequency offset. The present technique presented herein is aimed at compensating the frequency offset. We watch the control voltage (VC)502(such as402inFIG. 4) with two comparators (such as403, and405as shown inFIG. 4). Once the VC(502) goes out of the linear region522between VH508and VL504, the state machine (such as412inFIG. 4) will give control signals (such as413and415inFIG. 4) to add or remove one varactor pair to or from the VCO oscillation tank (as attached at Q424and QB at426via Group I416and Group II414inFIG. 4) This adding or removing action should be very slow to guarantee the time interval error (TIE) jitter is small enough not to affect performance desired. Thus the user will not be aware of this change.

We examine now in more detail one embodiment of the present invention in operation inFIG. 5.FIG. 5describes the process of adding a varactor in detail. At the beginning, the synthesizer is locked at point A510, the two comparators outputs ‘high’ and ‘low’ are ‘0’ and ‘1’ respectively (such as respectively inFIG. 4at405,403,410,406), and the VCH<0:m> (FIG. 4at415) are all biased at ‘0’ and the VCL<0:m> (FIG. 4at413) are all biased at ‘1’. Then after a long time period, for some reason, the synthesizer frequency decreases by Δf (520), and the VC502(FIG. 4at402) will be larger than VH508(FIG. 4at408). The signal ‘high’ (FIG. 4at410) changes from ‘0’ to ‘1’. Then the state machine (FIG. 4at412) drives the signal VCH<0> from ‘0’ to ‘1’ (FIG. 4bit0of415). As explained above, this change must be very slow. Thus a big capacitor Cbig(representatively shown at420inFIG. 4) is added to control how slow it is (i.e. changing from state ‘0’ to state ‘1’, and from state ‘1’ to state ‘0’). After this long period ends, if the state machine (FIG. 4at412) still receives a ‘1’ from ‘high’ signal (FIG. 4at410), the state machine (FIG. 4at412) will drive VCH<1> (FIG. 4bit1of415) from ‘0’ to ‘1’ slowly. This process continues unless the ‘high’ signal (FIG. 4at410) changes back to ‘0’. By then, N of (m+1) varactor pairs have been added to the oscillation tank (FIG. 4at Q and QB,424and426respectively) and the tuning curve is shifted from “o” dashed line511to the dashed line513as shown inFIG. 5where the synthesizer is locked at point C514which is now within the linear range522. Similarly, if the frequency is increased for some reason, the ‘low’ signal (such as406inFIG. 4) will control the state machine (FIG. 4at412) to drive several bits of VCL<0:m> (FIG. 4at413) from ‘1’ to ‘0’ slowly. The operation of one embodiment of a state machine (such as412inFIG. 4) is shown inFIG. 6, in which the ‘waiting’ state stands for the time period needed for driving VCH<n> from ‘0’ to ‘1’ or driving VCL<n> from ‘1’ to ‘0’ (where 0<n<m). In this way, the VC(such ad502inFIG. 5) will not be out of the linear region (FIG. 5at522), and the high performance of the synthesizer can be maintained.

FIG. 6illustrates, generally at600, one embodiment of the invention in flow chart form for a state machine such as illustrated inFIG. 4at412with its respective inputs high410, low406, and outputs VCH<0:m> and VCL<0:m>. At602the sequence starts with bits VCH<0:m> set at 0, and bits VCL<0:m> set at 1. At604a decision based on the high signal and the low signal. If high=0 and low=1 then the process continues at604. otherwise if low=0 then we proceed down path620, and if high=1 then we proceed down path640. At621we drive bit VCL<0> to 0. At622we enter waiting as noted above, the ‘waiting’ state stands for the time period needed for driving a bit in a slow fashion so as to not upset the VCO. After waiting622we check to see if low=1623and if so we continue at604otherwise we proceed to624and we drive bit VCL<1> to 0. We then enter waiting625. After waiting625we check to see if low=1626and if so we continue at604otherwise we proceed to repeat driving and waiting and checking as done above for bits0and1with increasingly higher bits2,3, . . . denoted as627, until at628we reach the most significant bit m which we drive bit VCL<m> to 0. We then enter waiting629. After waiting629we check to see if low=1630and if so we continue at604otherwise we have run out of bits to control and at631we end and report an error.

If at604a decision is made to proceed down path640, then at641we drive bit VCH<0> to 1. At642we enter waiting as noted above, the ‘waiting’ state stands for the time period needed for driving a bit in a slow fashion so as to not upset the VCO. After waiting642we check to see if high=0643and if so we continue at604otherwise we proceed to644and we drive bit VCH<1> to 1. We then enter waiting645. After waiting645we check to see if high=0646and if so we continue at604otherwise we proceed to repeat driving and waiting and checking as done above for bits0and1with increasingly higher bits2,3, . . . denoted as647, until at648we reach the most significant bit m which we drive bit VCH<m> to 1. We then enter waiting649. After waiting649we check to see if high=0650and if so we continue at604otherwise we have run out of bits to control and at651we end and report an error.

FIG. 7illustrates, generally at700, one embodiment of the invention showing TIE (time interval error) jitter. An example will be given to illustrate one embodiment of the invention. In practical applications, the maximum frequency offset due to temperature and crystal wander is mostly in the range of ±2% from the center frequency. Thus for a 6 GHz center frequency, the maximum offset is ±120 MHz. Set the VCO gain (KVCO) be 10 MHz/V (small enough gain for most applications), and ΔC/2=2.5 fF (divide by 2 because there are 2 capacitors in serial). For 6 GHz and a 0.5 pH inductance, AC/2=2.5 fF corresponds to a 5.3 MHz frequency offset. This frequency offset value should be chosen as close as possible to KVCO/2 to make the synthesizer locking point move back to the center of the tuning curve eventually. To cover a ±120 MHz frequency deviation, we need at least 46 pairs of compensation varactor banks with 23 pairs of them biased from ‘0’ (for example, dashed box I416inFIG. 4) and 23 pairs of them biased from ‘1’ (for example, dashed box II414inFIG. 4) at the initial state.

Next we decide how slow the varactors should be switched. If the loop bandwidth=300 kHz, Cbig=10 pF, and the driving capability of the state machine output stage is 10 nA (e.g. need a transistor with W/L<<1), then the slow rate of the VCH<n> or VCL<n> (0<n<m+1) should be 1000V/sec. And with this setting, we can get the TIE jitter due to this switching, which is shown inFIG. 7.

The big jump702shown inFIG. 7corresponds to the largest TIE introduced by the switching event. The TIE jitter due to the switching is in the range of ±1.5*10−14second, and this jitter is small enough, which will not cause synthesizer phase noise degradation. The whole procedure is completed in the range of several milliseconds. This time interval is fast enough to respond to a frequency deviation.

A novel frequency compensation technique has been presented here. By utilizing this technique, one can design a high performance synthesizer with a very small VCO tuning gain without considering frequency deviation due to temperature or reference crystal wandering. This technique compensates the frequency deviation with two extra arrays of compensating varactor banks, which are added to or removed from the oscillation tank very slowly. The compensation procedure completes in the background and is transparent to users.

Thus a method and apparatus for frequency compensation for multi-band VCO have been described.

FIG. 1illustrates a network environment100in which the techniques described may be applied. The network environment100has a network102that connects S servers104-1through104-S, and C clients108-1through108-C. More details are described below.

FIG. 2is a block diagram of a computer system200in which some embodiments of the invention may be used and which may be representative of use in any of the clients and/or servers shown inFIG. 1, as well as, devices, clients, and servers in other Figures. More details are described below.

Referring back toFIG. 1,FIG. 1illustrates a network environment100in which the techniques described may be applied. The network environment100has a network102that connects S servers104-1through104-S, and C clients108-1through108-C. As shown, several computer systems in the form of S servers104-1through104-S and C clients108-1through108-C are connected to each other via a network102, which may be, for example, a corporate based network. Note that alternatively the network102might be or include one or more of: the Internet, a Local Area Network (LAN), Wide Area Network (WAN), satellite link, fiber network, cable network, or a combination of these and/or others. The servers may represent, for example, disk storage systems alone or storage and computing resources. Likewise, the clients may have computing, storage, and viewing capabilities. The method and apparatus described herein may be applied to essentially any type of visual communicating means or device whether local or remote, such as a LAN, a WAN, a system bus, etc. Thus, the invention may find application at both the S servers104-1through104-S, and C clients108-1through108-C.

Referring back toFIG. 2,FIG. 2illustrates a computer system200in block diagram form, which may be representative of any of the clients and/or servers shown inFIG. 1. The block diagram is a high level conceptual representation and may be implemented in a variety of ways and by various architectures. Bus system202interconnects a Central Processing Unit (CPU)204, Read Only Memory (ROM)206, Random Access Memory (RAM)208, storage210, display220, audio,222, keyboard224, pointer226, miscellaneous input/output (I/O) devices228, and communications230. The bus system202may be for example, one or more of such buses as a system bus, Peripheral Component Interconnect (PCI), Advanced Graphics Port (AGP), Small Computer System Interface (SCSI), Institute of Electrical and Electronics Engineers (IEEE) standard number 1394 (FireWire), Universal Serial Bus (USB), etc. The CPU204may be a single, multiple, or even a distributed computing resource. Storage210, may be Compact Disc (CD), Digital Versatile Disk (DVD), hard disks (HD), optical disks, tape, flash, memory sticks, video recorders, etc. Display220might be, for example, an embodiment of the present invention. Note that depending upon the actual implementation of a computer system, the computer system may include some, all, more, or a rearrangement of components in the block diagram. For example, a thin client might consist of a wireless hand held device that lacks, for example, a traditional keyboard. Thus, many variations on the system ofFIG. 2are possible.

For purposes of discussing and understanding the invention, it is to be understood that various terms are used by those knowledgeable in the art to describe techniques and approaches. Furthermore, in the description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be evident, however, to one of ordinary skill in the art that the present invention may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that logical, mechanical, electrical, and other changes may be made without departing from the scope of the present invention.

An apparatus for performing the operations herein can implement the present invention. This apparatus may be specially constructed for the required purposes, or it may comprise a general-purpose computer, selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, hard disks, optical disks, compact disk-read only memories (CD-ROMs), and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), electrically programmable read-only memories (EPROM)s, electrically erasable programmable read-only memories (EEPROMs), FLASH memories, magnetic or optical cards, etc., or any type of media suitable for storing electronic instructions either local to the computer or remote to the computer.

The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general-purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the required method. For example, any of the methods according to the present invention can be implemented in hard-wired circuitry, by programming a general-purpose processor, or by any combination of hardware and software. One of ordinary skill in the art will immediately appreciate that the invention can be practiced with computer system configurations other than those described, including hand-held devices, multiprocessor systems, microprocessor-based or programmable consumer electronics, digital signal processing (DSP) devices, set top boxes, network PCs, minicomputers, mainframe computers, and the like. The invention can also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network.

The methods of the invention may be implemented using computer software. If written in a programming language conforming to a recognized standard, sequences of instructions designed to implement the methods can be compiled for execution on a variety of hardware platforms and for interface to a variety of operating systems. In addition, the present invention is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the invention as described herein. Furthermore, it is common in the art to speak of software, in one form or another (e.g., program, procedure, application, driver, . . . ), as taking an action or causing a result. Such expressions are merely a shorthand way of saying that execution of the software by a computer causes the processor of the computer to perform an action or produce a result.

It is to be understood that various terms and techniques are used by those knowledgeable in the art to describe communications, protocols, applications, implementations, mechanisms, etc. One such technique is the description of an implementation of a technique in terms of an algorithm or mathematical expression. That is, while the technique may be, for example, implemented as executing code on a computer, the expression of that technique may be more aptly and succinctly conveyed and communicated as a formula, algorithm, or mathematical expression. Thus, one of ordinary skill in the art would recognize a block denoting A+B=C as an additive function whose implementation in hardware and/or software would take two inputs (A and B) and produce a summation output (C). Thus, the use of formula, algorithm, or mathematical expression as descriptions is to be understood as having a physical embodiment in at least hardware and/or software (such as a computer system in which the techniques of the present invention may be practiced as well as implemented as an embodiment).

Various spellings may be used for terms used in the description. These variations are to be understood to relate to the same term unless denoted otherwise. For example: fail-safe is also spelled fail safe, and failsafe; start-up is also spelled startup, and start up; subthreshold is also spelled sub-threshold, and sub threshold; etc.

A machine-readable medium is understood to include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable medium includes read only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; electrical, optical, acoustical or other form of propagated signals which upon reception causes movement in matter (e.g. electrons, atoms, etc.) (e.g., carrier waves, infrared signals, digital signals, etc.); etc.

As used in this description, “one embodiment” or “an embodiment” or similar phrases means that the feature(s) being described are included in at least one embodiment of the invention. References to “one embodiment” in this description do not necessarily refer to the same embodiment; however, neither are such embodiments mutually exclusive. Nor does “one embodiment” imply that there is but a single embodiment of the invention. For example, a feature, structure, act, etc. described in “one embodiment” may also be included in other embodiments. Thus, the invention may include a variety of combinations and/or integrations of the embodiments described herein.

As used in this description, “substantially” or “substantially equal” or similar phrases are used to indicate that the items are very close or similar. Since two physical entities can never be exactly equal, a phrase such as “substantially equal” is used to indicate that they are for all practical purposes equal.

It is to be understood that in any one or more embodiments of the invention where alternative approaches or techniques are discussed that any and all such combinations as my be possible are hereby disclosed. For example, if there are five techniques discussed that are all possible, then denoting each technique as follows: A, B, C, D, E, each technique may be either present or not present with every other technique, thus yielding 2^5 or 32 combinations, in binary order ranging from not A and not B and not C and not D and not E to A and B and C and D and E. Applicant(s) hereby claims all such possible combinations. Applicant(s) hereby submit that the foregoing combinations comply with applicable EP (European Patent) standards. No preference is given any combination.

Thus a method and apparatus for frequency compensation for multi-band VCO have been described.