TRANSISTOR MANUFACTURING METHOD

A bipolar transistor is manufactured by: forming a collector region; forming a first layer made of a material of a base region and an insulating second layer; forming a cavity reaching the collector region; forming a portion of the collector region and a portion of the base region in the cavity; forming an insulating fourth layer made of a same material as the insulating second layer in the periphery of the bottom of the cavity, the insulating fourth layer having a same thickness as the insulating second layer; forming an emitter region; and simultaneously removing the insulating second and a portion of the insulating fourth layer not covered by the emitter region.

PRIORITY CLAIM

[1] This application claims the priority benefit of French Application for Patent No. 2211712, filed on Nov. 10, 2022, the content of which is hereby incorporated by reference in its entirety to the maximum extent allowable by law.

TECHNICAL FIELD

[2] The present disclosure generally concerns electronic devices and, in particular, electronic devices comprising doped regions and their manufacturing methods.

BACKGROUND

[3] A bipolar transistor is an electronic device based on a semiconductor of the family of transistors. Its operating principle is based on two PN junctions, one forward and the other reverse.

[4] The operation of bipolar transistors depends on a large number of characteristics of bipolar transistors. Such a characteristic of bipolar transistors is their maximum oscillation frequency.

[5] There is a need for bipolar transistors having a higher maximum oscillation frequency.

[6] There is a need to overcome all or part of the disadvantages of known semiconductor region manufacturing methods.

SUMMARY

[7] An embodiment provides a method of manufacturing a bipolar transistor comprising: a) manufacturing a first portion of a collector region in a substrate; b) forming a stack of layers comprising a first layer made of a material of a base region and a second insulating layer made of a first material; c) forming a cavity crossing the stack and the substrate to reach the first portion of the collector region; d) forming a second portion of the collector region and of a first portion of the base region in the cavity; e) forming a fourth layer made of the same material as the second layer, having the same thickness as the second layer in the periphery of the bottom of the cavity; f) forming an emitter region in front of the first portion of the base region, the fourth layer being partially exposed; and g) simultaneously removing the second and fourth layers.

[8] According to an embodiment, step a) comprises forming an insulating layer covering a portion of the first portion of the collector region, the cavity crossing the insulating layer.

[9] According to an embodiment, the stack of layers comprises a fifth insulating layer, the first layer, and the second layer located between two sixth insulating layers, the sixth layers being made of materials different from the material of the second layer.

According to an embodiment, the second portion of the collector region and the first portion of the base region are formed by epitaxial growth in the cavity.

According to an embodiment, step e) comprises forming the fourth layer over the entire structure, forming spacers on the fourth layer against the lateral walls of the cavity, where a central portion of the bottom of the cavity is not covered with the spacers, and etching the portions of the fourth layer which are not covered with the spacers.

According to an embodiment, the method comprises, between steps f) and g), a step f1) removing the spacers and the sixth layer covering the second layer.

According to an embodiment, step f) comprises forming a seventh layer made of the material of the emitter region and etching the seventh layer to partially expose the fourth layer around the emitter region.

According to an embodiment, the method comprises, after step g), a step h) epitaxially growing the first layer.

According to an embodiment, the method comprises, after step h), a step i) etching the first layer and the fifth layer, to partially expose the first portion of the collector region.

According to an embodiment, the method comprises, after step i), forming contact layers on the base, collector, and emitter regions.

According to an embodiment, the thickness of the second and fourth layers is in the range from 5 nm to 30 nm.

Another embodiment provides a device comprising a bipolar transistor wherein a contact layer of a base region of the transistor is separated from an emitter region by a portion of the base region and an insulating layer portion covered with the emitter region.

According to an embodiment, the base region rests on a portion of a collector region of the transistor, the horizontal dimensions of the emitter region being smaller than the horizontal dimensions of the portion of the collector region.

According to an embodiment, the horizontal dimensions of the emitter region are smaller by 180 nm than the horizontal dimensions of the portion of the collector region.

DETAILED DESCRIPTION

For the sake of clarity, only the steps and elements that are useful for the understanding of the described embodiments have been illustrated and described in detail.

Unless specified otherwise, the expressions “about”, “approximately”, “substantially”, and “in the order of” signify plus or minus 10%, preferably of plus or minus 5%.

Unless specified otherwise, the expressions “insulating” or “conductive” signify “electrically-insulating” or “electrically-conductive”.

FIG.1shows an embodiment of an electronic device10. More precisely,FIG.1shows an embodiment of an electronic device10comprising a bipolar transistor12.

Bipolar transistor12is formed in a substrate14. More precisely, transistor12is formed in the substrate and on an upper surface of substrate14. The substrate is made of a semiconductor material, for example of silicon. Transistor12comprises a region16of substrate14. Region16is a buried region of substrate14. In other word, region16does not extend all the way to the upper region of substrate14. Region16is preferably not doped.

Transistor12further comprises an insulating wall18. Wall16is made of an electrically-insulating material, for example of silicon oxide. Wall16extends in substrate14, for example from the upper surface. For example, wall18laterally surrounds region16. As a variant, the transistor may comprise a plurality of walls18, walls18laterally delimiting region16on at least certain sides.

Transistor12further comprises regions20of substrate14. Regions20are made of a material identical to region16. Preferably, regions20have the same doping as region16. For example, regions20are not doped. Regions20are partially separated from region16by wall(s)18. Regions20are physically and electrically coupled to region16under wall18. Thus, the biasing of region20causes the biasing of region16.

Transistor12comprises a conductive layer21. Layer21covers, preferably entirely, preferably only, the upper surface of region20. Layer21is made of an electrically-conductive material, for example of a metal. Layer21corresponds to the contact of the substrate of transistor12.

Transistor12further comprises a region22in substrate14. Region22is located inside of wall18. Region22extends from the upper surface of substrate14to region16. Region22preferably extends along the inner lateral surface of wall18. Region22is thus preferably in contact with wall18.

Region22is made of the semiconductor material of substrate14, for example of silicon. Region22is doped with a first conductivity type, preferably n-type doped. Region22corresponds to a portion of the collector of transistor12.

Transistor12comprises a conductive layer23. Layer23covers, preferably entirely, preferably only, the upper surface of region22. Layer23is made of an electrically-conductive material, for example of a metal. Layer23corresponds to the contact of the collector of transistor12.

Region22laterally surrounds a portion of region24of transistor12. Region24is located inside of wall18and inside of region22. Region24extends from the upper surface of region16and towards the upper surface of substrate14. Region24preferably extends along the inner lateral surface of region22. Region22is thus preferably in contact with region24. Region24preferably comprises a first portion extending in a plane parallel to the upper surface of region16. The first portion extends in the entire area surrounded with region22. The first portion extends on region16. The first portion is thus in contact with region16and with region22. Region24comprises a second portion extending from the upper surface of the first portion and extends towards the upper surface of substrate14. The second portion extends, for example, from the center of the first portion.

Region24is made of the semiconductor material of substrate14and of region22, for example of silicon. Region24is less heavily doped with the same conductivity type as region22, for example with the first conductivity type, preferably n-type doped. Region24corresponds to another portion of the collector of transistor12. Thus, the collector of transistor12comprises regions22and24.

Preferably, region24has a doping level, that is, a concentration of dopants of the first type, lighter than the doping level, that is, than the dopant concentration, of region22.

A region26laterally surrounds the second portion of region24. Region26is made of an electrically-insulating material, for example silicon oxide. Region26extends on the first portion of region24, around the second portion of region24. Region26extends from the upper surface of the first portion of region24at least all the way to the level of the upper surface of the second portion of region24. Thus, region26extends all along the height of the second portion of region24. Preferably, the second portion of region24and region26extend all the way to a level higher than the level of the upper surface of region22. The upper surface of the first portion of region24is preferably entirely covered with the second portion of region24and with region26.

Region26extends, on the external side, that is, the side most distant from the second portion of region24, along a height greater than on the inner side. Region26thus forms, at the level of its upper surface, a step. The assembly comprising region26and the second portion of region24thus comprises a cavity28, laterally delimited with region26, and more precisely the portion of region26having a height greater than the rest of region26. The bottom of cavity28is formed by region26, and more precisely by the portion of region26having the lowest height, and by the upper surface of the second portion of region24.

Transistor12further comprises a region30. Region30is located in cavity28. In other words, region30is located on a portion of region26and on the second portion of region24and is located inside of the wall formed by the portion of region26having a greater height. Region30preferably comprises a first portion corresponding to a layer and a second portion33extending from the first portion to form a cavity31in region30. The bottom of cavity31is formed by the first portion of region30and the lateral walls of cavity31are formed by the second portion33of region30. Preferably, second portion33is located in such a way that region30comprises an edge around portion33.

Region30covers, preferably entirely, the upper surface of the second portion of region24. Region30partially covers, for example, the upper surface of region26located in cavity28. Region30is preferably located at the center of cavity28. The portion of the bottom of cavity28covered with region30is surrounded with a portion of the bottom of cavity28which is not covered with region30.

Region30is, for example, made of the semiconductor material of substrate14, for example of silicon. Region30is doped with a second conductivity type, that is, the conductivity type opposite to the first conductivity type, preferably p-type doped. Region30corresponds to a portion of the base of transistor12.

Transistor12comprises a region32located in cavity28. Region32covers the bottom of cavity28which is not covered with region30. Thus, region28laterally surrounds the first portion of region30. The bottom of cavity38is thus preferably entirely covered with regions30and32. Region32preferably does not cover the upper surface of region24. Region32has, for example, the same height as the first portion of region30.

Region32is, for example, made of polysilicon. Region32is doped with the same conductivity type as region30, that is, the second conductivity type, that is, the conductivity type opposite to the first conductivity type, preferably p-type doped. Region32corresponds to a portion of the base of transistor12. Regions30and32thus form the base of transistor12.

Preferably, region30has a doping level, that is, a concentration of dopants of the second type, lighter than the doping level, that is, than the dopant concentration, of region32.

Transistor12comprises a conductive layer34. Layer34covers, preferably entirely, the upper surface of region32. Layer34partially covers, for example, region30. Thus, layer34rests on the edge of region30. Layer34is made of an electrically-conductive material, for example of a metal. Layer34corresponds to the contact of the base of transistor12.

Transistor12further comprises a layer36located in cavity31. In other words, layer36covers, preferably entirely, the bottom of cavity31. In other words, layer36extends on the first portion of region30, laterally surrounded with the second portion33of region30. The height of layer36is preferably lower than the height of portion33. Layer36is, for example, made of the same material as substrate14, for example of silicon. The material of layer36is preferably not doped.

Transistor12comprises an insulating layer38. Layer38is, for example, made of silicon oxide. Layer38extends over a portion of layer36. Layer38extends over the periphery of layer36. Layer38is preferably in contact with portion33all along the contour of cavity31and extends towards the center of layer36. Layer38does not entirely cover layer36. A central portion of layer36is not covered with layer38.

Transistor12further comprises a region40. Region40covers layer38and the central portion of layer36, that is, the portion not covered with layer38. Region40is thus in contact with layer36. The lateral walls of region40are coplanar with the lateral walls of layers36and38. Thus, the lateral walls of region40are coplanar with the inner lateral walls of portion33, that is, the lateral walls of portion33closest to layer38.

Region40is made of polysilicon. Region40is doped with the same conductivity type as regions22and24. Region40is, for example, n-type doped. Region40forms the emitter of transistor12.

The horizontal dimensions of the emitter region are smaller than the horizontal dimensions of the collector region portion. The horizontal dimensions of the emitter region are smaller by 180 nm than the horizontal dimensions of the second portion of the collector region.

Transistor12comprises a conductive layer42. Layer42covers, preferably entirely, preferably only, the upper surface of region40. Layer42is made of an electrically-conductive material, for example of a metal. Layer42corresponds to the contact of the emitter of transistor12.

Transistor12further comprises spacers44. Spacers44extend on the lateral walls of region40, preferably on all the lateral walls of region40. Spacers44extend, preferably vertically, from portion33to the upper level of region40. The spacers extend, preferably horizontally, from the lateral walls of region40to the level of the interface between portion33and layer34.

The extrinsic base resistance is a characteristic of bipolar transistors. The extrinsic base resistance is equal to the multiplication of a resistivity value by the distance between layer34and region40. Thus, in the embodiment ofFIG.1, the extrinsic base resistance is thus equal to the multiplication of a resistivity value by the sum of the width of portion33and the width of layer38.

The maximum oscillation frequency is such that the higher the extrinsic base resistance, the lower said frequency, and conversely. Thus, the maximum oscillation frequency of the transistor ofFIG.1is higher than that of a bipolar transistor comprising regions of additional materials between layer34and region40.

FIG.2A,FIG.2B,FIG.2C,FIG.2D,FIG.2E,FIG.2F,FIG.2G,FIG.2H,FIG.2I,FIG.2Jshow steps, preferably successive, of a method of manufacturing the embodiment ofFIG.1.

FIG.2Ashows a device resulting from a step of a method of manufacturing the embodiment ofFIG.1.

During this step, insulating walls18are formed in substrate14. Insulating walls18thus delimit an area where the base, the collector, and the emitter of transistor12are formed. The height of walls18is lower than the height of substrate14. Thus, a portion of substrate14, not shown, extends under walls18.

The step ofFIG.2Afurther comprises the forming of region22and of a region24acorresponding to the first portion of region24ofFIG.1. Regions22and24aare, for example, formed by doping of regions of substrate14. Regions22and24aare preferably doped to have the doping levels described in relation withFIG.1.

The step ofFIG.2Acomprises the forming of an insulating region46in substrate14. Region46is made of the material of region26, for example of silicon oxide. Region46covers, preferably entirely, preferably only, region24a. Thus, region46preferably extends from the upper surface of region24ato the upper level of substrate14. The height of region46is such that region24ahas the height of the first portion of region24.

FIG.2Bshows a device resulting from a step of the method of manufacturing the embodiment ofFIG.1.

During this step, elements48are formed. Elements48cover, preferably entirely, the locations of layers20. In other words, elements48cover the upper surface of the substrate14directly around walls18. Elements48cover, for example at least partially, walls18. Elements48preferably do not cover regions22and region46.

Elements48are, for example, made of a semiconductor material. Elements48are, for example, made of polysilicon. Elements48are, for example, made of a non-doped material.

The step ofFIG.2Bfurther comprises the forming of a stack50of layers. Stack50entirely covers, for example, the structure resulting from the forming of elements48. In particular, stack50covers, preferably entirely, elements48, the portions of walls18not covered with elements48, regions22, and region24a.

Stack50comprises a lower layer52. Layer52is thus the layer of the stack closest to substrate14. Layer52conformally covers the structure resulting from the forming of elements48. Layer52is made of an insulating material, for example the same material as region46, for example the same material as region26ofFIG.1. Layer52is, for example, made of silicon oxide.

Stack50comprises a layer56covering layer54. Layer56covers, preferably entirely, preferably conformally, layer54. Layer56is made of an insulating material. Layer56is made of an insulating material different from the material of layer52. Layer56is, for example, made of silicon nitride.

Stack50comprises a layer58covering layer56. Layer58covers, preferably entirely, preferably conformally, layer56. Layer58is made of an insulating material. Layer56is, for example, made of the same material as layer52. Layer56is made of a material different from the material of layer56. Layer56is, for example, made of silicon oxide. Layer58has a thickness d. The thickness of layer58is, for example, substantially constant, for example constant. In particular, the thickness of layer58is, for example, substantially constant, for example constant, at least in the area located in front of region46.

Stack50comprises a layer60covering layer58. Layer60covers, preferably entirely, preferably conformally, layer58. Layer60is made of an insulating material. Layer60is made of an insulating material different from the material of layer58. Layer60is, for example, made of the same material as layer56. Layer60is, for example, made of silicon nitride.

FIG.2Cshows a device resulting from a step of the method of manufacturing the embodiment ofFIG.1.

During this step, a cavity62is formed. Cavity62extends from the upper surface of layer60to the upper surface of layer24a. In other words, the cavity crosses the layers of stack50, that is, layers60,58,56,54,52, as well as region46.

Cavity62is located at the location of the second portion of region24. Thus, the lateral walls of cavity62partially correspond to the lateral walls of the second portion of region24.

The step ofFIG.2Cfurther comprises the forming of the second portion of region24. In other words, the second portion of region24is formed at the bottom of cavity62. More precisely, the step ofFIG.2Ccomprises the epitaxial growth of the second portion of region24from layer24a. The epitaxial growth is preferably maintained until the second portion of region24, that is, the portion formed during this epitaxial growth step, extends all the way to the level of the upper surface of layer52.

The epitaxial growth step causes the consumption of the material of layer54accessible from cavity62. Thus, layer54is partially etched from the lateral walls of cavity62. Cavities64are thus formed around cavity62, at the locations of a portion of layer54. The height of cavities64, for example corresponding to the height of layer54, is in the range, for example, from 5 nm to 20 nm. The depth of cavities54, that is, the distance between the lateral surface of layer54forming the bottom of cavity54and the opening of cavity54, is in the range from 5 nm to 50 nm.

FIG.2Dshows a device resulting from a step of the method of manufacturing the embodiment ofFIG.1.

During this step, a region66is formed in cavity62. Region66corresponds to a portion of the region30ofFIG.1. Region66is, for example, formed by epitaxial growth, from region24. Region66covers, preferably entirely, the upper surface of the portion of region24in cavity62. Region66thus fills the bottom of cavity62after the forming of the portion of region24. Region66preferably extends from the upper surface of region24all the way to the level of the upper surface of layer54. Region66preferably does not extend in cavities64so as to lead void areas at the location of cavities64which are closed off by the region66that partially fills cavity62.

Region66is made of the material of region30ofFIG.1. Thus, region66is preferably made of p-type doped silicon. The doping level of region66is for example substantially equal to the doping level of region30ofFIG.1.

The step ofFIG.2Dfurther comprises the forming of layer36. Layer36is formed on the upper surface of region66. Layer36covers, preferably entirely, preferably only, the upper surface of region66. Layer36is, for example, formed by epitaxial growth. The height of layer36is, for example, lower than the thickness of layer54.

Alternatively, region66and layer36are, for example, such that the upper surface of layer36is substantially coplanar with the upper surface of layer56.

The step ofFIG.2Dcomprises the forming of an insulating layer68. Layer68conformally covers the structure resulting from the forming of layer36. Thus, layer68covers the upper surface of layer60, the lateral walls of cavity62, that is, the lateral surfaces of layers60,58, and56located in cavity62, and the upper surface of layer36. Layer68is thus in contact with the lateral surfaces of layers60,58, and56.

Layer68is made of the same material as layer58, for example of silicon oxide. The material of layer68is different from the material of layer60. The thickness of layer68is substantially identical, preferably identical, to the thickness of layer58. The thickness of layers58and68is in the range from 5 nm to 30 nm.

The step ofFIG.2Dcomprises the forming of insulating layer70. Layer70conformally covers the structure resulting from the forming of layer68. Thus, layer68covers, preferably entirely, preferably only, the upper surface of layer68.

Layer70is made of a material different from the material of layer68. Layer70is, for example, made of the same material as layer60, for example of silicon nitride.

FIG.2Eshows a device resulting from a step of the method of manufacturing the embodiment ofFIG.1.

The step ofFIG.2Ecomprises a step of anisotropic etching of layer70. This etch step is preferably configured to only etch layer70(i.e., the etch is selective as to the material of layer70). This etch step is, for example, configured not to etch layer68. Layer70is entirely etched during this etch step, except for spacers72. Spacers72are located at the level of the lateral walls of cavity62. The spacers cover portions74of layer68having, in cross-section view, an L shape. Spacers72do not entirely fill cavity62. Thus, a central portion of cavity62is not covered with spacers72.

The step ofFIG.2Ethen comprises a step of etching of layer68. Layer68is preferably entirely etched except for the portions74covered with spacers72. Portions74comprise a horizontal portion extending, under spacers72, on the upper surface of layer36, from the lateral surfaces of cavity62to the center of cavity62. The horizontal portions of portions74are such that a portion, for example a substantially central portion, of the upper surface of layer36is not covered with portions74. Portions74further comprise a vertical portion extending on the lateral walls of cavity62, for example from the upper surface of layer36to the upper surface of layer60.

FIG.2Fshows a device resulting from a step of the method of manufacturing the embodiment ofFIG.1.

The step ofFIG.2Fcomprises a step of etching of layer60and of spacers72. Spacers72are made of the same material as layer60. Spacers72and layer60can thus be etched by the same etching. The etching is, for example, a wet etching.

During this etch step, the vertical portion of portions74is at least partially etched. For example, the vertical portion of portions74is etched all the way to the level of the upper surface of layer68. Layer58and the rest of portions74thus form a layer of constant thickness.

The step ofFIG.2Ffurther comprises the forming of a layer76on the structure resulting from the etching of layer60and of portions74. Layer76thus covers, preferably entirely, preferably only, layer58, portions74, and the portion of layer36which is not covered with portions74.

Layer76is made of the material of region40ofFIG.1, that is, for example of n-type doped polysilicon. The doping of layer76is, for example, substantially equal, for example equal, to the doping of region40ofFIG.1.

The step ofFIG.2Ffurther comprises the forming of an insulating layer78. Layer78covers, preferably entirely, preferably only, layer76. Layer78is made of an insulating material, preferably the same material as layer58, for example silicon oxide.

FIG.2Gshows a device resulting from a step of the method of manufacturing the embodiment ofFIG.1.

During this step, layers76and78are etched to form region40covered with a portion of layer78. Layers76and78are, for example, simultaneously etched. Layers76and78are etched in such a way that the remaining lateral walls of region40and of layer78are coplanar.

Further, layers76and78are etched in such a way that the remaining lateral walls of region40and of layer78are located in front of cavity62, that is, in front of the second portion of region24, of region66, and of layer36. More precisely, layers76and78are etched in such a way that the remaining lateral walls of region40and of layer78are located in front of portions74.

Thus, the portions of layers76and78located in front of layer58are removed. The portions of layers76and78located in front of the periphery of layer36, that is, located in front of the portions of portions74closest to layer58, are etched during this etch step. The portions of layers76and78located in front of the portion of layer36not covered with portions74and the portions of portions74most distant from layer58, are not etched during this etch step. Thus, region40and the rest of layer78entirely cover the portion of layer36not covered with portions74and partially covers portions74. For example, region40and the rest of layer78cover a central portion of the assembly comprising portions74and layer36.

FIG.2Hshows a device resulting from a step of the method of manufacturing the embodiment ofFIG.1.

During this step, layer58and portions74are etched. More precisely, the step ofFIG.2Hcomprises a step of etching of the material of layer58and of portions74. This etch step is, for example, a wet etching. This etching simultaneously removes layer58and the portions of portions74which are not located under region40. The etching is stopped to remove layer58and portions74without reaching layer56and layer36.

Layer58and portions74form a layer of constant thickness. Thus, the etching removes the material of layer58and of portions74substantially at the same rate. The etching of the entire layer58and of all the portions74thus substantially ends at the same time. The material of layer36is thus not etched during the etching of layer58and of portions74. It is thus not necessary to protect layer36with region40. It is possible to decrease the dimensions of region40without causing damage in layer36.

FIG.2Ishows a device resulting from a step of the method of manufacturing the embodiment ofFIG.1.

During this step, region40is encapsulated in a layer80of insulating material, preferably the material of layer78, for example silicon oxide.

Layer80encapsulating region40comprises layer78, portions74, and layers82covering the lateral walls of region40. Encapsulation layer80is preferably only located in front of layer36. Thus, the upper surface of layer56is not, preferably, covered, even partially, with layer80.

The step ofFIG.2Ifurther comprises the removal of layer56, for example by wet etching. Layer56is preferably entirely removed. Layer54is thus exposed. In particular, upper surface of layer54is exposed and the side edges of layer54at the cavities64are exposed.

FIG.2Jshows a device resulting from a step of the method of manufacturing the embodiment ofFIG.1.

The step ofFIG.2Jcomprises a step of epitaxial growth of layer54. The epitaxial growth is maintained so that cavities64are filled and so that layer54reaches at least the location of region32ofFIG.1.

Layer54and layer52are then etched to only keep the portions of layers52and54directly located around the assembly comprising region24, region66, layer36, layer80, and region40. Layers52and54are preferably etched to keep the portion of layer54located at the location of region32ofFIG.1and the portion of layer52located under said portion.

The method further comprises additional steps to obtain the device ofFIG.1. In particular, the method comprises: the removal of encapsulation layer80; the forming of spacers44on the lateral walls of region40; the growth of region66and the diffusion of the charges to form region30; and the forming of conductive layers21,23,34, and42.

An advantage of the described embodiments is that the extrinsic base resistance is lower than that of a known bipolar transistor. The maximum oscillation frequency is thus higher.

Another advantage of the described embodiments is that it is possible to form an emitter region smaller than in a known bipolar transistor.

Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variants may be combined, and other variants will occur to those skilled in the art.

Finally, the practical implementation of the described embodiments and variants is within the abilities of those skilled in the art based on the functional indications given hereabove.