ACCELERATION OF 1X1 CONVOLUTIONS IN CONVOLUTIONAL NEURAL NETWORKS

A convolutional accelerator includes a feature line buffer, a kernel buffer, a multiply-accumulate cluster, and mode control circuitry. In a first mode of operation, the mode control circuitry stores feature data in a feature line buffer and stores kernel data in a kernel buffer. The data stored in the buffers is transferred to the MAC cluster of the convolutional accelerator for processing. In a second mode of operation the mode control circuitry stores feature data in the kernel buffer and stores kernel data in the feature line buffer. The data stored in the buffers is transferred to the MAC cluster of the convolutional accelerator for processing. The second mode of operation may be employed to efficiently process 1×N kernels, where N is an integer greater than or equal to 1.

BACKGROUND

Technical Field

The present disclosure generally relates to convolutional accelerators, such as convolutional accelerators used in a learning/inference machine (e.g., an artificial neural network (ANN), such as a convolutional neural network (CNN)).

Description of the Related Art

Various computer vision, speech recognition, and signal processing applications may benefit from the use of learning/inference machines, which may quickly perform hundreds, thousands, or even millions of concurrent operations. Learning/inference machines, as discussed in this disclosure, may fall under the technological titles of machine learning, artificial intelligence, neural networks, probabilistic inference engines, accelerators, and the like. Conventional learning/inference machines can deliver hundreds of teraflops (e.g., one million millions (1012) floating-point operations per second) of computing power.

Such learning/inference machines may include or otherwise utilize CNNs, such as deep convolutional neural networks (DCNN). A DCNN is a computer-based tool that processes large quantities of data and adaptively “learns” by conflating proximally related features within the data, making broad predictions about the data, and refining the predictions based on reliable conclusions and new conflations. The DCNN is arranged in a plurality of “layers,” and different types of predictions are made at each layer. Hardware accelerators including convolutional accelerators are often employed to accelerate the processing of large amounts of data by a DCNN.

BRIEF SUMMARY

In an embodiment, a convolutional accelerator comprises a feature line buffer, a kernel buffer separate from the feature line buffer, a Multiply-ACcumulate (MAC) cluster, and mode control circuitry coupled to the feature line buffer, the kernel buffer and the MAC cluster. The mode control circuitry, in a first mode of operation of the convolutional accelerator, stores feature data in the feature line buffer, stores kernel data in the kernel buffer, transfers feature data from the feature line buffer to the MAC cluster, and transfers kernel data from the kernel buffer to the MAC cluster. In a second mode of operation of the convolutional accelerator, the mode control circuitry stores feature data in the kernel buffer, stores kernel data in the feature line buffer, transfers feature data from the kernel buffer to the MAC cluster, and transfers kernel data from the feature line buffer to the MAC cluster. The second mode of operation may be employed to efficiently process 1×N kernels, where N is an integer greater than or equal to 1.

In an embodiment, a system comprises a stream engine, which, in operation, streams feature and kernel data, and a convolutional accelerator coupled to the stream engine, wherein the convolutional accelerator, in operation, receives streams of feature and kernel data from the stream engine. The convolutional accelerator includes a feature line buffer, a kernel buffer, a multiply-accumulate cluster coupled to the feature line buffer and the kernel buffer, mode control circuitry coupled to the feature line buffer, the kernel buffer and the MAC cluster. The mode control circuitry, in a first mode of operation of the convolutional accelerator, stores feature data in the feature line buffer, stores kernel data in the kernel buffer, transfers feature data from the feature line buffer to the MAC cluster, and transfers kernel data from the kernel buffer to the MAC cluster. In a second mode of operation of the convolutional accelerator, the mode control circuitry stores feature data in the kernel buffer, stores kernel data in the feature line buffer, transfers feature data from the kernel buffer to the MAC cluster, and transfers kernel data from the feature line buffer to the MAC cluster. The second mode of operation may be employed to efficiently process 1×N kernels, where N is an integer greater than or equal to 1.

In an embodiment, a method comprises streaming feature data and kernel data to a convolutional accelerator, and convolving streamed kernel data with streamed feature data. The convolving includes, in a first mode of operation of the convolutional accelerator, storing feature data in a feature line buffer of the convolutional accelerator, storing kernel data in a kernel buffer of the convolutional accelerator, transferring feature data from the feature line buffer to a MAC cluster of the convolutional accelerator, and transferring kernel data from the kernel buffer to the MAC cluster. In a second mode of operation of the convolutional accelerator the convolving includes storing feature data in the kernel buffer, storing kernel data in the feature line buffer, transferring feature data from the kernel buffer to the MAC cluster, and transferring kernel data from the feature line buffer to the MAC cluster. The second mode of operation may be employed to efficiently process 1×N kernels, where N is an integer greater than or equal to 1.

In an embodiment, a non-transitory computer-readable medium's contents configure a convolutional accelerator having a plurality of modes of operation to convolve streamed kernel data with streamed feature data. The convolving includes, in a first mode of operation of the plurality of modes of operation of the convolutional accelerator, storing feature data in a feature line buffer of the convolutional accelerator, storing kernel data in a kernel buffer of the convolutional accelerator, transferring feature data from the feature line buffer to a MAC cluster of the convolutional accelerator, and transferring kernel data from the kernel buffer to the MAC cluster. In a second mode of operation of the plurality of modes of operation of the convolutional accelerator, the convolving includes storing feature data in the kernel buffer, storing kernel data in the feature line buffer, transferring feature data from the kernel buffer to the MAC cluster, and transferring kernel data from the feature line buffer to the MAC cluster. The second mode of operation may be employed to efficiently process 1×N kernels, where N is an integer greater than or equal to 1. In an embodiment, the contents comprise instructions executed by the convolutional accelerator.

DETAILED DESCRIPTION

CNNs are particularly suitable for recognition tasks, such as recognition of numbers or objects in images, and may provide highly accurate results.FIG.1is a conceptual diagram illustrating a digit recognition task andFIG.2is a conceptual diagram illustrating an image recognition task.

CNNs are specific types of deep neural networks (DNN) with one or multiple layers which perform a convolution on a three dimensional feature data tensor (width×height×depth). The first layer is an input layer and the last layer is an output layer. The intermediate layers may be referred to as hidden layers. The most used layers are convolutional layers, fully connected or dense layers, and pooling layers (max pooling, average pooling, etc). Data exchanged between layers are called features or activations. Each layer also has a set of learnable parameters typically referred to as weights or kernels.FIG.3is a conceptual diagram illustrating an example of an CNN, that is AlexNet. The illustrated CNN has a set of convolutional layers interleaved with max pooling layers, followed by a set of fully connected or dense layers.

The parameters of a convolutional layer include a set of learnable filters referred to as kernels. Each kernel has three dimensions, height, width and depth. The height and width are typically limited in range (e.g., [1, 11]). The depth typically extends to the full depth of an input feature data. Each kernel slides across the width and the height of the input features and a dot product is computed. At the end of the process a result is obtained as a set of two-dimensional feature maps. In a convolutional layer, many kernels are applied to an input feature map, each of which produces a different feature map as a result. The depth of the output feature tensors is also referred to the number of output channels.FIG.4is a conceptual diagram illustrating the application of a kernel to a feature map, producing a two-dimensional feature map having a height of 4 and a width of 4.

Convolutional layers also may have other parameters, which may be defined for the convolutional layer, rather than learned parameters. Such parameters may be referred to as hyper-parameters. For example, a convolutional layer may have hyper-parameters including stride and padding hyper-parameters.

The stride hyper-parameter indicates a step-size used to slide kernels across an input feature map.FIG.5is a conceptual diagram comparing a stride of 1 and a stride of 2. When the stride is greater than 1, the output feature map will be smaller than the input feature map.

The padding hyper-parameter indicate a number of zeros to be added along the height, the width or the height and width of the input feature map. The padding parameters may be used to control a size of an output feature map generated by the convolution.FIG.6is a conceptual diagram illustrating application of padding to an input feature map. The padding preserves the input feature size along the height and width of the feature map.

The feature data of a convolutional layer may have hundreds or even thousands of channels, with the number of channels corresponding to the depth of the feature data and of the kernel data. For this reason, feature and kernel data are often loaded into memory in batches.FIG.7is a conceptual diagram illustrating the concept of loading feature data in batches. The feature data is split along the depth dimension into batches, with each batch of feature data having the same height, width and depth. The kernel depth is generally the same as the depth of the input feature map, so similar issues are addressed by batching.

As illustrated, the batches have a height of 5, a width of 5, and a depth of 4. Batches are typically written into memory sequentially, with writing of a first batch being completed before beginning the writing of a second batch. The arrows inFIG.7illustrate an example order in which data of a batch is written into memory. A similar batching process is typically applied to the kernel data, with each batch of the kernel data having a same kernel height and kernel width, and the same depth as the batches of feature data. Each batch of feature data is convolved with a related batch of kernel data, and a feedback mechanism is employed to accumulate the results of the batches. The conceptual diagram ofFIG.8illustrates the concept of batch processing of a convolution.

As can be seen, the computations performed by a CNN, or by other neural networks, often include repetitive computations over large amounts of data. For this reason, computing systems having hardware accelerators may be employed to increase the efficiency of performing operations associated with the CNN.

FIG.9is a functional block diagram of an embodiment of an electronic device or system100of the type to which described embodiments may apply. The system100comprises one or more processing cores or circuits102. The processing cores102may comprise, for example, one or more processors, a state machine, a microprocessor, a programmable logic circuit, discrete circuitry, logic gates, registers, etc., and various combinations thereof. The processing cores may control overall operation of the system100, execution of application programs by the system100(e.g., programs which classify images using CNNs), etc.

The system100includes one or more memories104, such as one or more volatile and/or non-volatile memories which may store, for example, all or part of instructions and data related to control of the system100, applications and operations performed by the system100, etc. One or more of the memories104may include a memory array, which, in operation, may be shared by one or more processes executed by the system100.

The system100may include one or more sensors160(e.g., image sensors, audio sensors, accelerometers, pressure sensors, temperature sensors, etc.), one or more interfaces170(e.g., wireless communication interfaces, wired communication interfaces, etc.), and other circuits180, which may include antennas, power supplies, one or more built-in self-test (BIST) circuits, etc., and a main bus system190. The main bus system190may include one or more data, address, power and/or control buses coupled to the various components of the system100.

The system100also includes one or more hardware accelerators110which, in operation, accelerate the performance of one or more operations associated with implementing a CNN. The hardware accelerator110as illustrated includes one or more convolutional accelerators112to facilitate efficient performance of convolutions associated with convolutional layers of a CNN. The convolutional accelerators include a feature line buffer memory114, which, in operation, conventionally stores lines of feature data, a kernel buffer memory116, which, in operation, conventionally stores kernel data, and one or more clusters of Multiply-ACcumulate (MAC) units or circuits118, which in operation perform convolution operations using the buffered kernel and feature data. The hardware accelerator110as illustrated also includes a stream engine150and a stream switch155. The stream engine150, in operation, transmits data streams. For example, the stream engine150may stream data, such as feature data or kernel data stored in memory104, to a convolutional accelerator112via the stream switch155.

The kernel dimensions may vary between CNNs, and between convolutional layers of a single CNN. For example, inFIG.3convolutional layers with kernels having height and width dimensions of 11×11, 5×5 and 3×3 are illustrated. Historically, 3×3 kernels have been the most common. Thus, convolutional accelerators may typically be designed to efficiently support kernel computations within defined kernel height and width sizes, such as 3×3 kernels.

For example, the feature line buffer memory114may typically be a deep single port memory storing a few lines of feature data (e.g., three lines) and having a large number of storage elements per line (e.g., 1024 elements per line). Feature line data is often reused with multiple kernels, and a single port is generally sufficient for the feature line buffer memory114because the computations may typically be started once the feature line buffer is full.

The kernel buffer memory116may typically be a small, wide and shallow dual-port memory (e.g., 96 bits of width by 16 memory locations). Because the kernel buffer is wide, it is relatively expensive, and for this reason is often shallow to reduce the costs of the memory (e.g., to reduce the area costs). To provide for an efficient bandwidth in view of the shallow depth of the memory, the kernel buffer116may be a dual-port memory to facilitate simultaneous reading of stored kernel data for use in current convolutional operations and loading of kernel data into the kernel buffer for use in subsequent convolutional operations.

FIG.10is a conceptual diagram illustrating processing of convolutional operations having a 3×3 kernel using an embodiment of a convolutional accelerator, such as the convolutional accelerator112ofFIG.9. Feature data is stored in the feature line buffer114(e.g., three lines of feature data which may be processed together), and kernel data is stored in the kernel buffer116(e.g., supporting kernels of various sizes up to a threshold size, with the storage in the buffer optimized, for example, for 3×3 kernel data). Convolutional operations are performed using the MAC clusters118(e.g., 72 MACs organized into 6 clusters118of 12 MACs each (three sets of four MAC units120)) to operate on data received from the feature line buffer and the kernel buffer.FIG.10illustrates examples of other typical components of a convolutional accelerator (e.g., streaming interfaces142, streaming buffers144, an adder tree146, configuration registers148, etc.), which are not described in detail with reference toFIG.10. Larger size kernels (e.g., 4×4, 11×11, etc.) may typically be handled using, for example, software kernel decomposition techniques.

However, many CNNs have one or more layers with kernels having smaller height and width dimensions. For example, hidden or inner layers, especially dense or deep layers, may have a large number of channels of feature data and may frequently employ kernels having height and width dimensions smaller than 3×3, such as 1×1, 1×2, or 1×3, 1×N kernels. In particular, deep or dense convolutional layers having feature data with a larger number of channels convolved with deep 1×1 kernels are becoming increasingly popular in CNNs.FIG.11is a conceptual diagram illustrating convolutional layers having 3×3 and 1×1 kernels respectively.

Kernels having smaller height and width dimensions (e.g., 1×1 kernels) may be processed by switching off some of the components of a convolutional accelerator. This can be inefficient in a number of ways, as discussed with reference to the conceptual diagram ofFIG.12, which illustrates an example of processing a convolutional layer with a 1×1 kernel by switching off components of a convolutional accelerator optimized for use with larger size kernels. Feature data is stored in the feature line buffer114and kernel data is stored in the kernel buffer116.

To avoid congestion due to bandwidth saturation at the output, the number of input channels to the MAC units (which is limited by the depth of the kernel data that can be stored in the kernel buffer) is maintained to be greater than or equal to the number of output channels of the MAC units. Typical kernel buffer depth limitations may limit the number of input channels to the MAC clusters118to, for example, 24 channels for kernels having a height and width dimensions of 1×1. Thus, in the example considered the number of output channels of the MAC clusters would be limited to 24 channels, due to the bottleneck created by the size of kernel buffer memory, to avoid bandwidth saturation at the output.

In an example configuration of 72 MAC units organized into 6 clusters C0-C5of 12 MACs120each discussed above, only four MAC units120of the twelve MAC units of each cluster may be active, with the rest of the MAC units remaining idle, and only one output pixel per kernel may be processed per cycle. As illustrated, kernels1-4are provided to the first cluster of 12 MAC units with only 4 of the 12 MAC units being used, kernels5-8are provided to the second cluster of 12 MAC units with only 4 of the 12 MAC units of the second cluster being used, etc.

In addition, the ratio between fetched kernel data and the number of operations performed using the fetched kernel data drops dramatically as compared to processing of a 3×3 kernel, etc. using the same or a similar convolutional accelerator configuration. Thus, a significant number of additional fetch operations must be performed to process the convolutions of a convolutional layer having a 1×1 kernel when a solution of switching off components of the convolutional accelerator is employed.

Another alternative is to use fine-grained accelerator hardware. This approach, however, involves a substantial overhead in terms of control circuitry and software processing to process larger kernels using the fine-grained hardware. Using fine-grained hardware is not as efficient in processing larger kernels as coarse-grained accelerators. Such larger kernels, such as 3×3 kernels, also are frequently employed in CNNs as noted above.

The inventors have realized that hardware resources of a coarse-grained convolutional accelerator (e.g., a convolutional accelerator designed to efficiently process kernels having height and width dimensions of 3×3) may be reused or reconfigured to more efficiently perform convolutions using kernels having smaller height and width dimensions (e.g., 1×1, 1×2, 1×N dimensions) by employing two different modes of operation instead of switching off components.

When a convolutional layer having a 1×1 kernel is being processed, only one line of feature data needs to be stored at a time for convolving with kernels of the 1×1 kernels, so a deep three-line feature line buffer is not needed for the feature data. In addition, the size characteristics of the relatively deep feature line buffer114are more suited to storing kernel data associated with a deep 1×1 kernel than the size characteristics of the shallower kernel buffer116.

The inventors realized the types of data stored in the two buffers may be switched when convolutional layers having kernels with smaller height and width dimensions are being processed. A first mode of operation may be employed to process kernels having larger height and width dimensions (e.g., 3×3 kernels), and a second mode of operation may be employed to process kernels having smaller height and width dimensions (e.g., 1×1, 1×2, 1×N). Two example modes of operation are conceptually illustrated by the conceptual diagram ofFIG.13.

In a first mode of operation, labeled normal mode inFIG.13, feature data is stored in the feature line buffer114and kernel data is stored in the kernel buffer116. The first mode of operation may be employed, for example, to process typical 3×3 kernels in a generally conventional manner. See the discussion ofFIG.10, above.

In a second mode of operation, labeled deep mode inFIG.13, feature data is stored in the kernel buffer116instead of in the feature line buffer, and kernel data is stored in the feature line buffer114. For example, in the second mode of operation, two sets of 24 1×1×128 different kernels may be stored in the feature line buffer114, and 3 lines of feature data having a depth of 128 pixels may be stored in the kernel data buffer116. The second mode of operation may be employed, for example, to process 1×1 kernels, such as 1×1 kernels having a depth for which using the second mode of operation instead of the first mode of operation may provide increased efficiencies (e.g., a depth larger than a number of MAC units of the MAC cluster, in the example discussed, a kernel depth of 128, which is larger than 72).

To facilitate the first and second modes of operation, the system100as illustrated inFIG.9comprises mode control circuitry130. In the first mode of operation, the mode control circuitry130controls the storage of feature data in the feature line buffer114and the transfer of feature data from the feature line buffer114to the MAC clusters118, and the storage of kernel data in the kernel buffer116, and the transfer of kernel data from the kernel buffer116to the MAC clusters118. Operation of the mode control circuitry in the first mode of operation may be performed to control the storage and transfer of feature and kernel data in a generally conventional manner. For example, as illustrated in the conceptual diagram ofFIG.10. While the mode control circuitry130is illustrated as a block inFIGS.9and13, the mode control circuitry may be implemented, for example, using control logic and discrete components (e.g., multiplexers, existing buffers, etc.) distributed through the convolutional accelerator112.

In the second mode of operation, the mode control circuitry130controls the storage of kernel data in the feature line buffer114and transmission of kernel data from the feature line buffer114to the MAC clusters118, and the storage of feature data in the kernel buffer116, and the transfer of feature data from the kernel buffer116to the MAC clusters118. Examples of the operation and configurations of embodiments of the mode control circuitry130in the second mode of operation are discussed herein with reference toFIGS.14-23.

Embodiments of the system100ofFIG.9may include more components than illustrated, may include fewer components than illustrated, may combine components, may separate components into sub-components, and various combination thereof. For example, the hardware accelerator110may include DMA controllers, the mode control circuitry130may be split into input mode control circuitry to control the storage of input feature data and kernel data into the buffers114,116, and output mode control circuitry to control the transfer of stored input feature data from the buffers114,116to the MAC clusters118, all or part of the mode control circuitry130may be shared by one or more convolutional accelerators112, the mode control circuitry130may be integrated into other control circuitry of the convolutional accelerator, etc., and various combinations thereof.

FIG.14is a conceptual diagram illustrating an example of processing a convolutional layer with a 1×1 kernel by operating the convolutional accelerator in a second mode of operation in which kernel data is stored in a feature line buffer (e.g., feature line buffer114ofFIG.9) and pixels of feature data are stored in a kernel buffer (e.g., kernel buffer116ofFIG.9).

A large single-port feature line buffer114, which may normally be used to store 3 lines of feature data having a depth of 1024 elements, is instead controlled to store 24 kernels having a depth of up to 128 kernel values. Thus, 128 input channels are available, which is greater than the number of output channels of 72 available in the example configuration discussed above with reference toFIG.9. In the second mode of operation, the kernel buffer116is controlled to store three lines of feature data, and thus three lines of feature data may be fed to clusters of MAC units118.

As shown inFIG.14, kernels1-4are provided to a set of three clusters of four MAC units each. One of the three clusters of four MAC units computes the output for line1of the feature data and kernels1-4, a second one of the three clusters of 4 MAC units computes the output for line2of the feature data and kernels1-4, and a third one of the three clusters computes the output for line3of the feature data and kernels1-4. Similarly, kernels5-8are provided to another set of three clusters of four MAC units each, each cluster computing the output for a respective line of the feature data and kernels5-8. Kernels9-12,13-16,17-20and21-24are similarly provided to respective clusters of four MAC units each to compute outputs for respective lines of the feature data and the respective kernels.

The throughput is improved from 1 pixel depth per kernel in a cycle to 3 pixel depths per kernel in a cycle when a convolutional layer having a 1×1 kernel is processed using the deep mode of operation as compared to the normal mode of operation. In addition, each kernel value is used in three MAC operations in a cycle, significantly improving the ratio of the number of fetch operations to the number of MAC operations performed as compared to the use of each kernel value in one MAC operation per cycle when the normal mode of operation is employed to process a 1×1 kernel (seeFIG.12).

FIG.15is a conceptual diagram illustrating an embodiment of a configuration of a feature data path220and a kernel data path230of a convolutional accelerator112operating in a mode of operation, such as a deep mode of operation, in which feature line data is stored in a kernel buffer116, and kernel data is stored in a feature line buffer114. An embodiment of the feature data path220is shown in more detail inFIG.18, and an embodiment of the kernel data path230is shown in more detail inFIG.19.

The kernel buffer116in the embodiment ofFIG.15comprises six dual-port memories216, as illustrated six 16×96 bit dual-port buffers. In the normal mode of operation, the six dual port memories216of the kernel buffer116store kernel data, which may be done in a generally conventional manner. In the deep mode of operation, four of the six dual-port memories216are included in the feature data path220and controlled by feature load control circuitry130fof the mode control circuitry130to store feature line data.

As illustrated the four dual-port memories are organized into six virtual buffers116vof 128×8 bits in the feature line path220, each virtual buffer116vstoring a line of feature data. Three lines of feature data may be fed to the MAC clusters118at a time, each line being provided by the respective virtual buffer to two of the six clusters of MAC units118. While feature data from three of the virtual buffers116vis being fed to the MAC clusters118, feature data for a next set of computations may be loaded into the other three virtual buffers116v. Thus, three lines of feature data may be stored into the virtual buffers116vof the kernel buffer memory116at a time in a ping-pong fashion. The feature data load control circuitry130fof the mode control circuitry130is included in the feature data path220, and in operation the feature data load control circuitry130fcontrols the order in which pixels of feature data are stored into the virtual buffers116vof the kernel buffer116. As illustrated, the feature line path220includes a FIFO buffer and optional data manipulation circuitry.

In the second or deep mode of operation, the feature line buffer114is included in the kernel data path230and controlled to store kernel data by kernel load control circuitry130kof the mode control circuitry130. The two remaining dual-port buffers216of the kernel buffer116may advantageously be used in the kernel data path230to facilitate the storage in and retrieval from the feature line buffer114of kernel data stored therein. As illustrated, one of the dual-port buffers216amay be used to reduce the number of cycles needed to fill the feature line buffer114with kernel data, and one of the dual-port buffers216bmay be used to mirror the output of the feature line buffer114in order to emulate dual-port memory performance by the single port feature line buffer114(e.g., to facilitate use of kernel data stored in the dual-port buffer216bby the MAC clusters118while subsequent kernel data is being loaded into the feature line buffer114from the dual-port buffer216a).

As illustrated, the kernel load control circuitry130kincludes filtering circuitry130kfilt, which in operation selects kernels from kernel data path230to load into the feature line buffer114via the dual-port buffer216a, and multiplexer circuitry130km, which in operation, controls the transmission of kernel data from the dual port buffer216bto the MAC clusters118. The mode control circuitry130ofFIG.15as illustrated also includes serialization circuitry130s, which in operation serializes the outputs of the MAC clusters to account for the order in which the MAC operations are performed.

FIG.16is a conceptual diagram illustrating feature and kernel data flow paths in a deep mode of operation of a convolutional accelerator according to an embodiment. Features are streamed depth-wise and a whole pixel is stored in each virtual buffer116vof the kernel buffer116. Three pixels at a time are sent to the MAC clusters118, with each pixel being provided to a pair of the six MAC clusters118. For example, multiplexers130fmof the mode control circuitry130may be controlled to provide either pixels1-3or pixels4-6to respective pairs of MAC clusters of the MAC clusters118.

Kernels1-24are stored in the feature line buffer114, and all 24 kernels are sent to respective MAC clusters in a cycle (seeFIG.14), generating three lines of an output feature map.FIG.17is a conceptual diagram illustrating the transmission of three pixels per cycle for a given kernel value in the example configuration ofFIG.16. The same kernel is strided three times in a cycle, obtaining three output values for each kernel value, or 72 output values for 24 kernels in a cycle.

FIG.18is a conceptual diagram illustrating a data path220of the feature data in a convolutional accelerator operating in a deep mode of operation according to an embodiment. Streaming engine150may be capable of streaming, for example, 3 bytes of data or more in a transaction. As illustrated, the streaming engine streams pixel1, depth1of feature data (1.1inFIG.18), pixel1, depth2(1.2inFIG.18) and pixel1, depth3(1.3inFIG.18) in a first transaction, T1. Transaction T2sends the next three depths of pixel1, shown as1.4,1.5and1.6inFIG.18. The transmission continues in successive transmissions until the transmission of a set of pixels is complete, as illustrated until pixel W, depth128is transmitted. Other pixel depths may be employed. The pixels are stored in a FIFO buffer, and may be manipulated using data manipulation circuitry, before being stored in respective virtual buffers116vby the feature load control circuitry130f. As illustrated, three pixels at a time are provided by respective virtual buffers116vto respective pairs of clusters of four MAC units. The availability of three pixel values (e.g., pixel1, depth1, pixel2, depth1, and pixel3, depth1) for processing with each kernel value available (e.g., kernels1-24) in a cycle provides a three-to-one improvement in the throughput and improves the ratio of MAC calculations per retrieved kernel value. As mentioned above, while feature data from three of the virtual buffers116vis being fed to the MAC clusters118, feature data for a next set of computations may be loaded into the other three virtual buffers116v. Thus, three lines of feature data may be stored into the virtual buffers116vof the kernel buffer memory116at a time in a ping-pong fashion.

FIG.19is a conceptual diagram illustrating a data path of the kernel data230in a convolutional accelerator operating in a deep mode of operation according to an embodiment. The operation of the elements of the kernel data path is described above with reference toFIG.15. In each cycle, all 24 kernel values stored in the dual-port memory216bare supplied to respective MAC units of the 72 MAC units, with each kernel value being supplied to 3 MAC units.

FIG.20is a conceptual diagram illustrating the sharing of each kernel value, twenty-four in the illustrated embodiment, with three MAC units and the sharing of each pixel of feature data with a pair of MAC clusters in a convolutional accelerator operating in a deep mode of operation according to an embodiment, to produce 72 output pixels per cycle. As compared to the embodiment ofFIG.12in processing a convolutional layer having 1×1 deep kernel, the performance per cycle is tripled and each retrieved kernel value is used on three MAC operations instead of one MAC operation. The additional control logic employed may add a small amount of costs in terms of area (e.g., 2%).

FIGS.14-20illustrate an embodiment of a deep mode of operation in the context of convolutional processing using a 1×1 kernel.FIG.21is a conceptual diagram illustrating convolutional operations associated with a 1×2 kernel in a convolutional accelerator operating in a deep mode of operation according to an embodiment. The 1×2 kernel is decomposed into two 1×1 sub-kernels and the pixel values are strided. The first 1×1 sub-kernel is processed in a first deep mode cycle producing a first partial sum using pixel values 1-3, and the second 1×1 sub-kernel is processed in a second deep mode cycle using pixel values 2-4 producing an accumulated output for the 1×2 kernel.

FIG.22is a conceptual diagram illustrating convolutional operations associated with a 1×3 kernel in a convolutional accelerator operating in a deep mode of operation according to an embodiment. The 1×2 kernel is decomposed into three 1×1 sub-kernels and the pixel values are strided. The first 1×1 sub-kernel is processed in a first deep mode cycle producing a first partial sum using pixel values 1-3, the second 1×1 sub-kernel is processed in a second deep mode cycle using pixel values 2-4 producing a second partial sum, and the third 1×1 sub-kernel is processed in a third deep mode cycle using pixel values 3-5 producing an accumulated output for the 1×3 kernel. The concept may be extended to convolutional processing with 1×N kernels (e.g., up to the available memory in the feature line buffer114for storing kernel depths). Multiple convolutional accelerators may be employed in some embodiments, for example, to process the sub-kernels.

FIG.23is a conceptual diagram illustrating convolutional operations associated with a 1×2 kernel in a convolutional accelerator operating in a deep mode of operation using an adder tree according to an embodiment. As illustrated, two sub-kernels are each convolved with two pixel values in a cycle and the results are combined using an adder tree, which may reduce latency times associated with accumulating the results of processing of the sub-kernels in sequential cycles.

FIG.24illustrates a logical flow diagram generally showing an embodiment of a method2400for controlling a convolutional accelerator in multiple modes of operation, which may be performed, for example, by the convolutional accelerator112using the mode control circuitry130as discussed above with reference toFIGS.9-23. For convenience, the method2400will be described with reference toFIGS.1-23.

The method2400starts at2402, and proceeds to2404. At2404, the method2400determines or selects a mode of operation of a convolutional accelerator112in processing a convolutional layer. This may be done, for example, based on the size of a kernel to be processed by a convolutional accelerator112in the convolutional layer, the configuration of the convolutional accelerator112(e.g., the characteristics of the feature line buffer114, the kernel buffer116, etc.), and various combinations thereof. For example, if the convolutional accelerator112is optimized to process 3×3 kernels (e.g., based on the size and configuration of the kernel buffer116and the clusters of MAC circuits118), and the kernel to be processed is a 2×2 or larger kernel, a first mode of operation, such as a normal mode of operation, may be selected. On the other hand, if the convolutional accelerator112is optimized to process 3×3 kernels (e.g., based on the size and configuration of the kernel buffer116), and the kernel to be processed is a 1×1 to 1×N kernel, where N is an integer greater than or equal to 1, a second mode of operation may be selected, such as a deep mode of operation. Other factors may be considered as well, such as the depth of the kernel. The determination of the mode of operation may be made by a host processor, such as a process102ofFIG.9, and stored in a configuration register, such as the configuration register148ofFIG.10. The method2400proceeds from2404to2406.

At2406, the method2400determines whether the selected mode of operation is a first mode of operation or a second mode of operation, for example, a normal mode of operation or a deep mode of operation, based on the determination at2404. When it is determined at2406that the mode of operation is a first mode of operation, the method2400proceeds from2406to2408.

At2408, the method2400stores feature data in the feature line buffer114. This may be done in a generally conventional manner, such as discussed above with reference toFIGS.10and13. The method proceeds from2408to2410.

At2410, the method2400stores kernel data in the kernel buffer116. This may be done in a generally conventional manner, such as discussed above with reference toFIGS.10and13. The method proceeds from2410to2412.

At2412, the method2400transfers feature data from the feature line buffer114to the MAC clusters118, and transfers kernel data from the kernel buffer116to the MAC clusters118. This may be done in a generally conventional manner, such as discussed above with reference toFIGS.10and13. The method proceeds from2412to2414.

At2414, the method2400performs MAC operations using the MAC clusters118with the feature data and kernel data transferred at2412. This may be done in a generally conventional manner, such as discussed above with reference toFIGS.10and13. The method proceeds from2414to2416.

At2416, the method2400performs other processing operations associated with the convolutional layer, such as accumulating results of batches of data, serializing output data, returning to2408to process a subsequent batch of data of the convolutional layer, transferring data to and from external memory, etc., and various combinations thereof. This may be done in a generally conventional manner, such as discussed above with reference toFIGS.8,10and13. The method proceeds from2416to2418.

At2418, the method2400performs other processing operations associated with the CNN that includes the convolutional layer, such as returning to2404to determine a mode of operation for a next convolutional layer of the CNN, performing pooling operations of a next layer of the CNN, transferring data to and from external memory, etc., and various combinations thereof.

When it is determined at2406that the mode of operation is a second mode of operation, for example, a deep kernel mode of operation, the method2400proceeds from2406to2420.

At2420, the method2400stores feature data in the kernel buffer116. This may be done, for example, as discussed above with reference toFIGS.13-18and20. The method proceeds from2420to2422.

At2422, the method2400stores kernel data in the feature line buffer114. This may be done, for example, as discussed above with reference toFIGS.13-17,19and20. The method proceeds from2422to2424.

At2424, the method2400transfers feature data from the kernel buffer116to the MAC clusters118, and transfers kernel data from the feature line buffer114to the MAC clusters118. This may be done, for example, as discussed above with reference toFIGS.13-20. The method proceeds from2424to2426.

At2426, the method2400performs MAC operations using the MAC clusters118with the feature data and kernel data transferred at2424. This may be done in a generally conventional manner. The method proceeds from2414to2416.

At2428, the method2400performs other processing operations associated with the convolutional layer, such as accumulating results of batches of data, serializing output data (e.g., to account for the order in which feature line and kernel data are processed in2426), returning to2420to process a subsequent batch of data of the convolutional layer (seeFIG.8), transferring data to and from external memory, etc., and various combinations thereof. The method proceeds from2428to2418, where, as discussed above, other processing operations associated with the CNN may be performed.

Embodiments of the foregoing processes and methods may contain additional acts not shown inFIG.24, may not contain all of the acts shown inFIG.24, may perform acts shown inFIG.24in various orders, may combine acts, may split acts into separate acts, and may be otherwise modified in various respects. For example,FIG.24may be modified to combine acts2404and2406, to perform acts2408and2410in parallel, to perform acts2420and2422in parallel, to include processing acts to facilitate processing of 1×N kernels in the second mode of operation, where N is an integer greater than 1 (see, e.g.,FIGS.21-23), etc, and various combinations thereof.

In an embodiment, a convolutional accelerator comprises a feature line buffer, a kernel buffer separate from the feature line buffer, a Multiply-ACcumulate (MAC) cluster, and mode control circuitry coupled to the feature line buffer, the kernel buffer and the MAC cluster. The mode control circuitry, in a first mode of operation of the convolutional accelerator, stores feature data in the feature line buffer, stores kernel data in the kernel buffer, transfers feature data from the feature line buffer to the MAC cluster, and transfers kernel data from the kernel buffer to the MAC cluster. In a second mode of operation of the convolutional accelerator, the mode control circuitry stores feature data in the kernel buffer, stores kernel data in the feature line buffer, transfers feature data from the kernel buffer to the MAC cluster, and transfers kernel data from the feature line buffer to the MAC cluster. The second mode of operation may be employed to efficiently process 1×N kernels, where N is an integer greater than or equal to 1.

In an embodiment, the mode control circuitry, in the first mode of operation: stores three lines of feature line data having a depth of up to 1024 elements in the feature line buffer; and stores 3×3 kernels in the kernel buffer. In an embodiment, the mode control circuitry, in the second mode of operation: stores six lines of feature line data having a depth of up to 128 elements in the kernel buffer; and stores 1×1 kernels in the feature line buffer. In an embodiment, the mode control circuitry, in the second mode of operation: transfers three lines of feature line data from the kernel buffer to the MAC clusters in a cycle; and transfers twenty-four kernel data values to the MAC clusters in the cycle. In an embodiment, the MAC clusters, in operation, generate 72 output values in the cycle.

In an embodiment, the feature line buffer is a single-port memory, and the kernel buffer comprises a plurality of dual-port buffers. In an embodiment, the mode control circuitry, in the second mode of operation: stores feature line data in a first subset of the plurality of dual-port buffers; and buffers kernel data is a second subset of the plurality of dual-port buffers. In an embodiment, the buffering kernel data in the second subset of the plurality of dual-port buffers comprises: storing kernel data in a first dual-port buffer of the second subset; transferring kernel data from the first dual-port buffer of the second subset to the feature line buffer; transferring kernel data from the feature line buffer to a second dual-port buffer of the second subset; and transferring kernel data from the second dual-port buffer of the second subset to the MAC clusters. In an embodiment, the buffering kernel data in the second subset of the plurality of dual-port buffers comprises: transferring kernel data from the feature line buffer to a dual-port buffer of the second subset of dual-port buffers; and transferring kernel data from the dual-port buffer of the second subset of dual-port buffers to the MAC clusters. In an embodiment, the mode control circuitry, in the second mode of operation, serializes output values generated by the MAC clusters.

In an embodiment, the convolutional accelerator comprises a configuration register, and the mode control circuitry, in operation, determines whether to operate in the first mode of operation or the second mode of operation based on a configuration parameter stored in the configuration register. In an embodiment, in the second mode of operation, the kernel data has a size of 1×N, where N is an integer greater than or equal to 1.

In an embodiment, a system comprises a stream engine, which, in operation, streams feature and kernel data, and a convolutional accelerator coupled to the stream engine, wherein the convolutional accelerator, in operation, receives streams of feature and kernel data from the stream engine. The convolutional accelerator includes a feature line buffer, a kernel buffer, a multiply-accumulate cluster coupled to the feature line buffer and the kernel buffer, mode control circuitry coupled to the feature line buffer, the kernel buffer and the MAC cluster. The mode control circuitry, in a first mode of operation of the convolutional accelerator, stores feature data in the feature line buffer, stores kernel data in the kernel buffer, transfers feature data from the feature line buffer to the MAC cluster, and transfers kernel data from the kernel buffer to the MAC cluster. In a second mode of operation of the convolutional accelerator, the mode control circuitry stores feature data in the kernel buffer, stores kernel data in the feature line buffer, transfers feature data from the kernel buffer to the MAC cluster, and transfers kernel data from the feature line buffer to the MAC cluster. The second mode of operation may be employed to efficiently process 1×N kernels, where N is an integer greater than or equal to 1.

In an embodiment, the mode control circuitry: in the first mode of operation: stores three lines of feature line data having a depth of up to 1024 elements in the feature line buffer; and in the second mode of operation: stores six lines of feature line data having a depth of up to 128 elements in the kernel buffer; and stores 1×N kernels in the feature line buffer, where N is an integer greater than or equal to 1. In an embodiment, the mode control circuitry, in the second mode of operation: transfers three lines of feature line data from the kernel buffer to the MAC clusters in a cycle; and transfers twenty-four kernel data values to the MAC clusters in the cycle. In an embodiment, the feature line buffer is a single-port memory; and the kernel buffer comprises a plurality of dual-port buffers. In an embodiment, the mode control circuitry, in the second mode of operation: stores feature line data in a first subset of the plurality of dual-port buffers; and buffers kernel data is a second subset of the plurality of dual-port buffers.

In an embodiment, a method comprises streaming feature data and kernel data to a convolutional accelerator, and convolving streamed kernel data with streamed feature data. The convolving includes, in a first mode of operation of the convolutional accelerator, storing feature data in a feature line buffer of the convolutional accelerator, storing kernel data in a kernel buffer of the convolutional accelerator, transferring feature data from the feature line buffer to a MAC cluster of the convolutional accelerator, and transferring kernel data from the kernel buffer to the MAC cluster. In a second mode of operation of the convolutional accelerator the convolving includes storing feature data in the kernel buffer, storing kernel data in the feature line buffer, transferring feature data from the kernel buffer to the MAC cluster, and transferring kernel data from the feature line buffer to the MAC cluster. The second mode of operation may be employed to efficiently process 1×N kernels, where N is an integer greater than or equal to 1.

In an embodiment, the first mode of operation includes storing three lines of feature line data having a depth of up to 1024 elements in the feature line buffer, and storing 3×3 kernels in the kernel buffer; and the second mode of operation includes storing six lines of feature line data having a depth of up to 128 elements in the kernel buffer, and storing 1×N kernels in the feature line buffer, where N is an integer greater than or equal to 1. In an embodiment, the kernel buffer comprises a plurality of dual-port buffers; and in the second mode of operation: the storing feature data in the kernel buffer comprises storing feature data in a first subset of the plurality of dual-port buffers; and the storing kernel data in the feature line buffer comprising buffering kernel data is a second subset of the plurality of dual-port buffers.

In an embodiment, a non-transitory computer-readable medium's contents configure a convolutional accelerator having a plurality of modes of operation to convolve streamed kernel data with streamed feature data. The convolving includes, in a first mode of operation of the plurality of modes of operation of the convolutional accelerator, storing feature data in a feature line buffer of the convolutional accelerator, storing kernel data in a kernel buffer of the convolutional accelerator, transferring feature data from the feature line buffer to a MAC cluster of the convolutional accelerator, and transferring kernel data from the kernel buffer to the MAC cluster. In a second mode of operation of the plurality of modes of operation of the convolutional accelerator, the convolving includes storing feature data in the kernel buffer, storing kernel data in the feature line buffer, transferring feature data from the kernel buffer to the MAC cluster, and transferring kernel data from the feature line buffer to the MAC cluster. The second mode of operation may be employed to efficiently process 1×N kernels, where N is an integer greater than or equal to 1. In an embodiment, in the first mode of operation the convolving includes storing three lines of feature line data having a depth of up to 1024 elements in the feature line buffer, and storing 3×3 kernels in the kernel buffer; and in the second mode of operation the convolving includes storing six lines of feature line data having a depth of up to 128 elements in the kernel buffer, and storing 1×N kernels in the feature line buffer, where N is an integer greater than or equal to 1. In an embodiment, the kernel buffer comprises a plurality of dual-port buffers; and in the second mode of operation: the storing feature data in the kernel buffer comprises storing feature data in a first subset of the plurality of dual-port buffers; and the storing kernel data in the feature line buffer comprises buffering kernel data is a second subset of the plurality of dual-port buffers. In an embodiment, the contents comprise instructions executed by the convolutional accelerator.