THREE-DIMENSIONAL SEMICONDUCTOR STRUCTURE AND FORMATION METHOD THEREOF

Embodiments relate to a three-dimensional semiconductor structure and a formation method thereof. The three-dimensional semiconductor structure includes: a substrate; and a device structure positioned on a top surface of the substrate. The device structure includes memory rows arranged at intervals along a first direction, each of the memory rows includes memory cells arranged at intervals along a second direction and a gap between adjacent two of the memory cells, and each of the memory cells includes a first stacked layer and a word line structure. The word line structure includes a first part positioned in the first stacked layer and a second part extending out of the first stacked layer along the first direction. At least adjacent two of the memory rows exist, and the second part of the memory cell in one of the memory rows extends into the gap in another one of the memory rows.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to Chinese Patent Application No. 202210667646.X, titled “THREE-DIMENSIONAL SEMICONDUCTOR STRUCTURE AND FORMATION METHOD THEREOF” and filed to the State Patent Intellectual Property Office on Jun. 14, 2022, the entire contents of which are incorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates to the field of semiconductor manufacturing technology, and more particularly, to a three-dimensional semiconductor structure and a formation method thereof.

BACKGROUND

As a type of semiconductor apparatus commonly used in electronic devices such as computers, Dynamic Random Access Memory (DRAM) is constituted by a plurality of memory cells, where each of the plurality of memory cells generally includes a transistor and a capacitor. A gate electrode of the transistor is electrically connected to a word line, a source electrode of the transistor is electrically connected to a bit line, and a drain electrode of the transistor is electrically connected to the capacitor, where a word line voltage of the word line can control the transistor to be turned on or off, such that data information stored in the capacitor can be read or written into the capacitor through the bit line.

To increase storage capacity, semiconductor structures such as the DRAM have developed from vertical structures to horizontal structures, but an integration level of the DRAM with the horizontal structures still needs to be improved. Therefore, how to improve the integration level of the semiconductor structure to expand application fields of the semiconductor structures is a technical problem that needs to be solved urgently at present.

SUMMARY

A semiconductor structure and a method for forming a semiconductor structure provided by some embodiments of the present disclosure are used for solving a problem of lower integration level of the semiconductor structure, to expand application fields of the semiconductor structure.

According to some embodiments, the present disclosure provides a three-dimensional semiconductor structure, including:a substrate; anda device structure positioned on a top surface of the substrate. The device structure includes memory rows arranged at intervals along a first direction, each of the memory rows includes memory cells arranged at intervals along a second direction and a gap between adjacent two of the memory cells, and each of the memory cells includes a first stacked layer and a word line structure. The word line structure includes a first part positioned in the first stacked layer and a second part extending out of the first stacked layer along the first direction. At least adjacent two of the memory rows exist, and the second part of the memory cell in one of the memory rows extends into the gap in another one of the memory rows. Both the first direction and the second direction are directions parallel to the top surface of the substrate, and the first direction intersects with the second direction.

According to other embodiments, the present disclosure also provides a method for forming the three-dimensional semiconductor structure according to any one of the above embodiments. The method includes:providing a substrate; andforming a device structure on a top surface of the substrate. The device structure includes memory rows arranged at intervals along a first direction, each of the memory rows includes memory cells arranged at intervals along a second direction and a gap between adjacent two of the memory cells, and each of the memory cells includes a first stacked layer and a word line structure. The word line structure includes a first part positioned in the first stacked layer and a second part extending out of the first stacked layer along the first direction. At least adjacent two of the memory rows exist, and the second part of the memory cell in one of the memory rows extends into the gap in another one of the memory rows. Both the first direction and the second direction are directions parallel to the top surface of the substrate, and the first direction intersects with the second direction.

According to the three-dimensional semiconductor structure and a formation method thereof provided by some embodiments of the present disclosure, on a substrate there is provided a device structure including memory rows arranged at intervals in the first direction, where each of the memory rows includes memory cells arranged at intervals along a second direction and a gap between adjacent two of the memory cells, and word line structures in the memory cells in one of the memory rows extend into the gap in another one of the memory rows, such that word line signals can be led out from the gap between the two adjacent memory cells.

DETAILED DESCRIPTION

Embodiments of a three-dimensional semiconductor structure and a formation method thereof provided by the present disclosure will be described in detail below with reference to the accompanying drawings.

The present disclosure provides a three-dimensional semiconductor structure.FIG.1is a schematic top view of the three-dimensional semiconductor structure according to an embodiment of the present disclosure;FIG.2is a schematic top view of a memory cell according to an embodiment of the present disclosure;FIG.3is a schematic top view of the three-dimensional semiconductor structure according to another embodiment of the present disclosure;FIG.4is a schematic top view of the memory cell according to yet another embodiment of the present disclosure; andFIG.5is a schematic cross-sectional view of a second part of a word line structure according to an embodiment of the present disclosure. The three-dimensional semiconductor structure described in this embodiment may be, but is not limited to, a Dynamic Random Access Memory (DRAM). As shown inFIGS.1to5, the three-dimensional semiconductor structure includes:a substrate10; anda device structure positioned on a top surface of the substrate10. The device structure includes memory rows12arranged at intervals along a first direction D1, each of the memory rows12includes memory cells arranged at intervals along a second direction D2and a gap11between adjacent two of the memory cells, and each of the memory cells includes a first stacked layer29and a word line structure. The word line structure includes a first part201positioned in the first stacked layer29and a second part202extending out of the first stacked layer29along the first direction D1. At least adjacent two of the memory rows12exist, and the second part202of the memory cell in one of the memory rows12extends into the gap11in another one of the memory rows12. Both the first direction D1and the second direction D2are directions parallel to the top surface of the substrate10, and the first direction D1intersects with the second direction D2.

In some embodiments, the substrate10may be, but is not limited to, a silicon substrate, and this embodiment is described by taking an example where the substrate10as the silicon substrate. In other examples, the substrate10may be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or silicon on insulator (SOI). The substrate10is configured to support the device structure thereon. The top surface of the substrate10refers to a surface of the substrate10facing the device structure. The device structure includes a plurality of the memory rows12arranged at intervals along the first direction D1, and each of the memory rows12includes a plurality of memory cells arranged at intervals along the second direction D2intersecting with the first direction D1, such that the plurality of memory cells are regularly arranged on the top surface of the substrate10to fully utilize an area of the top surface of the substrate10, thereby improving the integration level of the three-dimensional semiconductor structure. The intersection mentioned in this embodiment may be a vertical intersection (i.e., orthogonal intersection) or an oblique intersection. In this embodiment, “a plurality of” refers to two or more.

The word line structure includes the first part201electrically connected to the memory cells in the first stacked layer29, and the second part202extending out of the first stacked layer29and configured to electrically connect external control signals. Both the first part201and the second part202may extend along the first direction D1, and the first part201is electrically connected to the second part202. In this embodiment, by extending the second part202of the memory cell in one of the memory rows12into the gap11in another one of the memory rows12, the space of the top surface of the substrate10can be more fully utilized, and thus arrangement of the plurality of memory cells in the device structure is more compact to reduce the size of the three-dimensional semiconductor structure, thereby improving the integration level of the three-dimensional semiconductor structure.

In some embodiments, the first stacked layer29includes first semiconductor layers arranged at intervals along a third direction D3, and each of the first semiconductor layers includes first semiconductor pillars28arranged at intervals along the first direction D1, where the third direction D3is a direction perpendicular to the top surface of the substrate10.

The word line structure includes word lines23arranged at intervals along the third direction D3, where the word lines23extend along the first direction D1. Each of the word lines23includes a first sub part521continuously wrapping the first semiconductor pillars28arranged at intervals along the first direction D1and a second sub part522extending out of the first semiconductor layer along the first direction D1and electrically connected to the first sub part521. In any adjacent two of the word lines along the third direction D3, the second sub part522of one of the two word lines23closer to the substrate10protrudes from the second sub part522of other one of the two word lines23along the first direction D1.

To support the second part202of the word line structure to improve structural stability of the memory cell, in some embodiments, the first semiconductor layer extends along the second direction D2. The device structure also includes:a second stacked layer including second semiconductor layers51arranged at intervals along the third direction D3, where the second semiconductor layers51extend along the first direction D1. In adjacent two of the second semiconductor layers51along the third direction D3, one of the two second semiconductor layers51closer to the substrate10protrudes from other one of the two second semiconductor layers51along the first direction D1, and a plurality of the second sub parts51respectively wrap a plurality of the second semiconductor layers522.

In some embodiments, the memory cell includes the first stacked layer29and the second stacked layer arranged along the first direction D1. The word line structure includes a plurality of the word lines23arranged at intervals along the third direction D3, the plurality of word lines23extend along the first direction D1, and each of the plurality of word lines23includes the first sub part521positioned in the first stacked layer29and the second sub part522positioned in the second stacked layer. A plurality of the first sub parts521arranged at intervals along the third direction D3constitute the first part201of the word line structure, and a plurality of the second sub parts522arranged at intervals along the third direction D3constitute the second part202of the word line structure. The first sub part521of the word line23continuously wraps the first semiconductor pillars28arranged at intervals along the first direction D1, and the second sub part522of the word line23wraps the second semiconductor layer51. The first sub part521and the second sub part522in the same word line23may be formed synchronously, such that there is no contact interface between the first sub part521and the second sub part522in the same word line23. In this way, fabrication processes of the three-dimensional semiconductor structure are simplified, and an internal resistance of the word line structure is reduced. In an embodiment, a first spacer531is further arranged between adjacent first sub parts521along the third direction D3for electrically isolating the adjacent first sub parts521; a second spacer532is further arranged between the adjacent second sub parts522along the third direction D3for electrically isolating the adjacent second sub parts522. The materials of the first spacer531and the second spacer532may be the same, for example, they are both oxide materials (such as silicon dioxide).

For the two second semiconductor layers51adjacent to each other along the third direction D3in the second semiconductor layer, one of the two second semiconductor layers51closer to the substrate10protrudes from the other one of the two second semiconductor layers51along the first direction D1, such that an end of the second stacked layer away from the first stacked layer29forms a step-shaped structure. Therefore, ends of the second sub parts522of the plurality of word lines23respectively wrapping the plurality of second semiconductor layers51also form a step-shaped structure, which facilitates a signal from each of the word lines23to be led out from the end of the second sub part522. It not only contributes to further improving the fabrication processes of the three-dimensional semiconductor structure, but also simplifying word line lead-out processes of the three-dimensional semiconductor structure, thereby reducing fabrication costs of the three-dimensional semiconductor structure.

In an embodiment, the memory cell further includes a first dielectric layer501between the first sub part521of the word line23and the first semiconductor pillar28, and a second dielectric layer502between the second sub part522of the word line23and the second semiconductor layer51. The first dielectric layer501may be used as a gate dielectric layer in the memory cell. In an embodiment, both a material of the first dielectric layer501and a material of the second dielectric layer502may be oxide material (such as silicon dioxide).

In an embodiment, the memory cell further includes a third spacer54, where the third spacer54at least wraps a step-shaped end of the side of the second stacked layer away from the first stacked layer29, to further prevent occurrence of a short circuit between adjacent two of the second sub parts522.

In some embodiments, both the material of the first semiconductor layer and the material of the second semiconductor layer51are silicon materials including doped ions, such that the first semiconductor layer and the second semiconductor layer51may be simultaneously formed, which contributes to simplifying the fabrication processes of the three-dimensional semiconductor structure. The first semiconductor layer and the second semiconductor layer51are formed by the silicon material with the doped ions, which can enhance conductivity of the first semiconductor layer and the second semiconductor layer51, thereby reducing the internal contact resistance of the memory cell.

In some embodiments, one of the memory cells further includes:a plug structure comprising word line plugs arranged at intervals along the first direction D1, where each of the word line plugs extends along the third direction D3and is electrically connected to the second sub part522of the word line23.

In some embodiments, the word line plug is electrically connected to the end of the second sub part522away from the first sub part521. That is, a plurality of the word line plugs are electrically connected to a plurality of step top surfaces of the second part202with a step-shaped structure. The word line plug includes a first conductive pillar552, and a first plug25positioned on a top surface of the first conductive pillar552. In an embodiment, the word line plug may further include a first diffusion barrier layer551wrapping the first conductive pillar552and electrically connected to the second sub part522, and a first conductive layer56wrapping the first plug25and electrically connected to the first conductive pillar552and the first diffusion barrier layer551, to reduce electric leakage between adjacent two of the word line plugs and an internal resistance of the word line plug. The external control signal (such as a read signal or write signal) is transmitted to the first sub part521in the first stacked layer29through the word line plug and the second sub part522.

In some embodiments, one of the memory cells further includes:a bit line structure21comprising bit lines27arranged at intervals along the first direction D1, where the bit lines27extend along the third direction D3.

The first semiconductor pillar28includes two first semiconductor sub pillar distributed on opposite two sides of the bit line27along the second direction D2and electrically connected to the bit line27, and the first sub part521of the word line23continuously wraps the two first semiconductor sub pillar arranged at intervals along the first direction D1.

In some embodiments, the semiconductor sub pillar includes a channel region, and a source region and a drain region distributed on opposite two sides of the channel region along the second direction D2, and the bit line27is adjacent to and is electrically connected to the source region. The memory cell further includes:a capacitor structure22positioned on the substrate10, where the capacitor structure22is adjacent to and is electrically connected to the drain region; anda support structure24positioned on the substrate10, where the support structure24includes a first sub support structure and a second sub support structure connected to each other, the first sub support structure is positioned in the first stacked layer29, and the second sub support structure is distributed around a periphery of the first stacked layer29and a periphery of the second part202.

In some embodiments, as shown inFIG.2andFIG.4, the first stacked layer29includes a bit line structure21, transistor structures distributed on opposite two sides of the bit line structure21along the second direction D2, and the capacitor structure positioned on the side of the transistor structure away from the bit line structure21along the second direction D2. The transistor structure includes a plurality of transistors arranged at intervals along the first direction D1. The first semiconductor sub pillar includes an active pillar in the transistor structure and a conductive pillar in the capacitor structure. The active pillar includes the channel region, and the source region and the drain region distributed on opposite two sides of the channel region along the second direction D2. The first sub part521of the word line23continuously wraps a plurality of the channel regions arranged at intervals along the first direction D1.

The bit line27extends along the third direction D3, and the top surface of the bit line27is electrically connected to the bit line plug26to lead out the bit line27through the bit line plug26. In this embodiment, two transistors arranged along the second direction D2share one bit line27, such that the size of the memory cell can be further reduced, and thus the integration level of the device structure can be improved. The support structure24is arranged around the periphery of the first stacked layer29and the periphery of the second stacked layer, and extends into the first stacked layer29and the second stacked layer. In one aspect, the support structure24is configured to support the memory cells; and in another aspect, the support structure24is configured to isolate adjacent two of the memory cells, thereby avoiding signal crosstalk between the adjacent memory cells.

In some embodiments, a length of the second part202along the first direction D1is smaller than that of the first stacked layer29along the first direction D1, to reduce the size of the memory cell and to reduce an internal parasitic capacitance effect of the device structure.

In some embodiments, a plurality of the memory rows12arranged at intervals along the first direction D1are sequentially ordered, where a plurality of the memory rows12at a first odd-numbered position are aligned and arranged along the first direction D1, and a plurality of the memory rows12at a first even-numbered position are aligned and arranged along the first direction D1, such that a plurality of the memory cells are regularly arranged, to improve the integration level of the three-dimensional semiconductor structure, and to further simplify the fabrication processes of the three-dimensional semiconductor structure.

In some embodiments, the memory cell further comprises a bit line structure21, two of the word line structures are distributed on opposite two sides of the bit line structure21along the second direction D2, and the second parts202of the two word line structures are positioned on opposite two sides of the first stacked layer29.

In some embodiments, two of the second parts202of the memory cells positioned in a given one of the plurality of memory rows12at the first even-numbered position respectively extend into the gaps11in two of the plurality of memory rows12at the first odd-numbered position adjacent to the given memory row12at the first even-numbered position, and two of the second parts202of the memory cells positioned in a given one of the plurality of memory rows12at the first odd-numbered position respectively extend into the gaps11in two of the plurality of memory rows12at the first even-numbered position adjacent to the given memory row12at the first odd-numbered position.

In some embodiments, in the plane jointly constituted by the first direction D1and the third direction D3, the projections of the two second parts202extending into the same gap11are partially overlapped, to reduce the distance between adjacent memory rows12at the first odd-numbered positions, and to reduce the distance between adjacent memory rows12at the first even-numbered positions, thereby further reducing the size of the device structure and improving the integration level of the three-dimensional semiconductor structure.

In some embodiments, as shown inFIG.2, extension directions of the second parts202of the two word line structures in the memory cell are opposite. For example, the second part202of one of the word line structures extends out of the first stacked layer29along a positive direction of the first direction D1, and the second part202of the other word line structure extends out of the first stacked layer29along a negative direction of the first direction D1. The two second parts202of the memory cell extend along the first direction D1into the two gaps11arranged at intervals along the first direction D1, as shown inFIG.1. By means of this structure, the distance between the two second parts202in the memory cell can be increased, thereby reducing the parasitic effect of capacitance between the word line plugs electrically connected to the two second parts202respectively, further reducing the internal electric leakage of the memory cell and improving the electrical performance of the three-dimensional semiconductor structure.

In some embodiments, the memory cell further includes a bit line structure21, two of the word line structures are distributed on opposite two sides of the bit line structure21along the second direction D2, and the second parts202of the two word line structures are positioned on opposite two sides of the first stacked layer29.

In some embodiments, an extension direction of the second part in a given one of the plurality of memory rows12at the first odd-numbered position is opposite to that of the second part202in a given one of the plurality of memory rows12at the first even-numbered position.

In some embodiments, as shown inFIG.4, the extension directions of the second parts202of the two word line structures in the memory cell are the same. For example, the second parts202of the two word line structures both extend out of the first stacked layer29along the positive direction of the first direction D1; or the second parts202of the two word line structures both extend out of the first stacked layer29along the negative direction of the first direction D1. For example, as shown inFIG.3, the second parts202in the memory rows12at the first odd-numbered positions all extend along the negative direction of the first direction D1, and the second parts202in the memory rows12at the first even-numbered positions all extend along the positive direction of the first direction D1. In this way, the area of the top surface of the substrate10is fully utilized, such that the integration level of the three-dimensional semiconductor structure is further improved.

This embodiment further provides a method for forming a three-dimensional semiconductor structure as described in any one of the embodiments.FIG.6is a flowchart of the method for forming a three-dimensional semiconductor structure according to an embodiment of the present disclosure; andFIGS.7A-7Fare schematic structural diagrams of main processes in the process of forming the three-dimensional semiconductor structure according to embodiments of the present disclosure. The schematic diagrams of the three-dimensional semiconductor structure formed in this embodiment may be seen inFIGS.1to5.FIG.7Ais a schematic top view of a memory cell in the three-dimensional semiconductor structure formed in this embodiment, andFIGS.7B-7Fare partial cross-sectional views from any one or more positions of a first position a-a, a second position b-b, a third position c-c, a fourth position d-d and a fifth position e-e inFIG.7Ain the process of forming the memory cell, to clearly show the processes for forming the memory cell. As shown inFIGS.1to6andFIGS.7A to7F, the method for forming a three-dimensional semiconductor structure includes the following steps:

Step S61, providing substrate10; and

Step S62, forming a device structure on a top surface of the substrate10. The device structure includes memory rows12arranged at intervals along a first direction12, each of the memory rows12includes memory cells arranged at intervals along a second direction D2and a gap11between adjacent two of the memory cells, and each of the memory cells includes a first stacked layer29and a word line structure. The word line structure includes a first part201positioned in the first stacked layer29and a second part202extending out of the first stacked layer29along the first direction D1. At least adjacent two of the memory rows12exist, and the second part202of the memory cell in one of the memory rows12extends into the gap11in another one of the memory rows12. Both the first direction D1and the second direction D2are directions parallel to the top surface of the substrate10, and the first direction D1intersects with the second direction D2.

For example, the first stacked layer29and the second stacked layer73, both of which have a superlattice stacked structure, are simultaneously formed on the top surface of the substrate10, as shown inFIG.7B. A bit line region, transistor regions positioned on opposite two sides of the bit line region along the second direction D2, and a capacitor region positioned on the side of the transistor region away from the bit line region along the second direction D2are defined in the first stacked layer29. The transistor region of the first stacked layer29and the second stacked layer73are arranged along the first direction D1and are in contact with each other. The first stacked layer29includes a first semiconductor layer74and a first sacrificial layer70alternately stacked along the third direction D3, and the second stacked layer73includes a second semiconductor layer51and a second sacrificial layer80alternately stacked along the third direction D3. The third direction D3is a direction perpendicular to the top surface of the substrate10. The first semiconductor layer74and the second semiconductor layer51are formed synchronously and are made of silicon materials including doped ions, where the doped ions may be, but are not limited to, N-type ions, to enhance conductivity between the first semiconductor layer74and the second semiconductor layer51.

Next, the first stacked layer29and the second stacked layer73are patterned, a first trench is formed in the first stacked layer29, and a second trench configured to disconnect the first stacked layer29from the second stacked layer73is formed simultaneously. The first semiconductor layer74in the first stacked layer29is separated, by the first trench, into a plurality of first semiconductor pillars28arranged at intervals along the first direction. The first semiconductor pillar28includes an active pillar positioned in the transistor region and a conductive pillar positioned in the capacitor region. The active pillar includes a channel region, and a source region and a drain region distributed on opposite two sides of the channel region along the second direction D2. Next, the first sacrificial layer70and the second sacrificial layer80are removed, and the support structure24embedded in the first stacked layer29and the second stacked layer73is formed. Next, a capacitor structure is formed in the capacitor region of the first stacked layer29, and an opening75exposing the channel region281is formed in the transistor region, as shown inFIG.7C. The capacitor structure includes capacitors arranged at intervals along the third direction D3, and the capacitor includes the conductive pillar, a conductive layer wrapping the surface of the conductive pillar, a dielectric layer wrapping the surface of the conductive layer, and an upper electrode layer wrapping the surface of the dielectric layer, where the conductive pillar and the conductive layer together serve as a lower electrode layer of the capacitor.

After the first dielectric layer501is formed on the surface of the channel region281and the second dielectric layer502is formed on the surface of the second semiconductor layer51, word line materials are deposited on the surface of the first dielectric layer501and on the surface of the second dielectric layer502to form a word line extending along the first direction D1. The word line includes a first sub part521positioned on the surface of the first dielectric layer501and wrapping the channel region281and a second sub part522positioned on the surface of the second dielectric layer502and wrapping the second semiconductor layer51, where the first sub part521is electrically connected to the second sub part522, as shown inFIG.7D. To facilitate the formation of the word line extending along the first direction D1, a thickness of the first sacrificial layer70along the third direction D3is greater than a gap width between adjacent two of the channel regions along the first direction D1. In an embodiment, the thickness of the first sacrificial layer70along the third direction D3is four times greater than the gap width between adjacent two of the channel regions along the first direction D1. The thickness of the second sacrificial layer80may be equal to that of the first sacrificial layer70, and the thickness of the second semiconductor layer51may be equal to that of the first semiconductor layer74.

Next, the second stacked layer73and the second sub part522of the word line are etched to form a step-shaped structure at the end of the second stacked layer73away from the first stacked layer29. The step-shaped structure includes multilayer steps stacked along the third direction D3, and each layer of the steps includes the second semiconductor layer51, a second dielectric layer52wrapping the surface of the second semiconductor layer51, and the second sub part522wrapping the surface of the second dielectric layer502. In the adjacent two layers of steps along the third direction D3, one of the two layers of steps closer to the substrate10protrudes from other one of the two layers of steps along the first direction D1, as shown inFIG.7E.

The third spacer54wrapping at least the step-shaped structure is formed, and a plug structure electrically connected to the word line structure is formed. The plug structure includes a plurality of word line plugs arranged at intervals along the first direction D1, and the plurality of word line plugs are electrically connected to the end of the second sub part522away from the first sub part521. That is, the plurality of word line plugs are electrically connected to the plurality of step top surfaces of the second sub part202having the step-shaped structure. Each of the plurality of word line plugs includes a first conductive pillar552, and a first plug25positioned on the top surface of the first conductive pillar552. In an embodiment, as shown inFIG.7F, the word line plug may further include a first diffusion barrier layer551wrapping the first conductive pillar552and electrically connected to the second sub part522, and a first conductive layer56wrapping the first plug25and electrically connected to the first conductive pillar552and the first diffusion barrier layer551, to reduce the electric leakage between adjacent two of the word line plugs and the internal resistance of the word line plug.

According to the three-dimensional semiconductor structure and a formation method thereof provided by some embodiments of the present disclosure, on a substrate there is provided a device structure including memory rows arranged at intervals in the first direction, where each of the memory rows includes memory cells arranged at intervals along the second direction and a gap between adjacent two of the memory cells, and word line structures in the memory cells in one of the memory rows extend into the gap in another one of the memory rows, such that word line signals can be led out from the gap between the two adjacent memory cells. In this way, space on the surface of the substrate can be fully utilized, and an integration level of the three-dimensional semiconductor structure can be improved. In addition, in the present disclosure, an end of the word line structure is formed into a step shape, such that a signal from each word line in the word line structure can be led out conveniently, and thus the integration level of the three-dimensional semiconductor structure can be further improved. Furthermore, two transistors in the memory cells of the present disclosure share one bit line, which contributes to further reducing the size of the three-dimensional semiconductor structure and thus further improving the integration level of the three-dimensional semiconductor structure.

The above merely are embodiments of the present disclosure. It is to be pointed out that to those of ordinary skill in the art, various improvements and embellishments may be made without departing from the principles of the present disclosure, and these improvements and embellishments are also deemed to be within the scope of protection of the present disclosure.