TECHNIQUES FOR ERROR DETECTION IN ANALOG COMPUTE-IN-MEMORY

Circuitry for a compute-in-memory (CiM) circuit or structure arranged to detect bit errors in a group of memory cells based on a summation of binary 1's included in at least one weight matrix stored to the group of memory cells, a parity value stored to another group of memory cells and a comparison of the summation or the parity value to an expected value.

TECHNICAL FIELD

Descriptions are generally related to error detection in analog compute-in-memory (CiM) circuit using a summation-based error correction code (ECC).

BACKGROUND

Computer artificial intelligence (AI) has been built on machine learning, particularly using deep learning techniques. With deep learning, a computing system organized as a neural network computes a statistical likelihood of a match of input data with prior computed data. A neural network refers to a plurality of interconnected processing nodes that enable the analysis of data to compare an input to “trained” data. Trained data refers to computational analysis of properties of known data to develop models to use to compare input data. An example of an application of AI and data training is found in object recognition, where a system analyzes the properties of many (e.g., thousands or more) of images to determine patterns that can be used to perform statistical analysis to identify an input object such as a person's face.

Neural networks compute “weights” to perform computations on new data (an input data “word”). Neural networks use multiple layers of computational nodes, where deeper layers perform computations based on results of computations performed by higher layers. Machine learning currently relies on the computation of dot-products and absolute difference of vectors, typically computed with multiply and accumulate (MAC) operations performed on the parameters, input data and weights. Because these large and deep neural networks may include many such data elements, these data elements are typically stored in a memory separate from processing elements that perform the MAC operations.

Due to the computation and comparison of many different data elements, machine learning is extremely compute intensive. Also, the computation of operations within a processor are typically orders of magnitude faster than the transfer of data between the processor and memory resources used to store the data. Placing all the data closer to the processor in caches is prohibitively expensive for the great majority of practical systems due to the need for large data capacities of close proximity caches. Thus, the transfer of data when the data is stored in a memory separate from processing elements becomes a major bottleneck for AI computations. As the data sets increase in size, the time and power/energy a computing system uses for moving data between separately located memory and processing elements can end up being multiples of the time and power used to actually perform AI computations.

Some architectures (e.g., non-Von Neumann computation architectures) may employ CiM techniques to bypass von Neumann bottleneck” data transfer issues and execute convolutional neural network (CNN) as well as deep neural network (DNN) applications. The development of such architectures may be challenging in digital domains since MAC operation units of such architectures are too large to be squeezed into high-density Manhattan style memory arrays. For example, the MAC operation units may be magnitudes of order larger than corresponding memory arrays. For example, in a 4-bit digital system, a digital MAC unit may include 800 transistors, while a 4-bit Static random-access memory (SRAM) cell typically contains 24 transistors. Such an unbalanced transistor ratio makes it difficult, if not impossible to efficiently fuse the SRAM with the MAC unit. Thus, von-Neumann architectures can be employed such that memory units are physically separated from processing units. The data is serially fetched from the storage layer by layer, which results in a great latency and energy overhead.

DETAILED DESCRIPTION

In an era of artificial intelligence, computation is more data-intensive, consumes high energy, demands a high level of performance and requires more storage. It can be extremely challenging to fulfill these requirements/demands using conventional architectures and technologies. Analog CiM is starting to gain momentum due to a potential for higher levels of energy to area efficiency compared to conventional digital counterparts. Advantages of analog computing have been demonstrated in many fields especially in the areas of neural networks, edge processing, Fast Fourier transform (FFT), etc.

Similar to conventional memory architectures, analog CiM architectures can also suffer from various run-time faults that are sometimes due to process, voltage, temperature (PVT) uncertainty. A majority of current analog CiM architecture designs focus on power and performance, but rarely give sufficient consideration for data reliability. Data reliability can be critical for analog CiM architectures deployed in multi-bit representation systems.

SRAM reliability can be seriously affected by space radiation. Error correction codes (ECCs) represent one method to detect and correct data values maintained in a CiM architecture or structure from soft errors that can be caused by space radiation. Current ECC solutions are a “near-memory” not truly “in-memory” solutions for error mitigation for an analog CiM architecture or structure. These current ECC solutions are a “near-memory solution because post-computation signals are processed after an analog-digital-converter (ADC) converts analog signals to digital signals. Errors in the data maintained in an SRAM memory cell may not be detected after ADC conversion. A traditional ECC decoder can be comprised of a large number of XOR gates.

There are many difficulties to put a conventional ECC logic block or circuitry for use with a CiM architecture or structure. Conventional ECC logic blocks can be too large and too slow for use in a CiM architecture or structure. Also, conventional ECC logic blocks are digitally based and not analog based and are typically designed for large chunks of data (e.g.,64bor256b). As a result, for at least some CiM architectures, error corrections have been intentionally neglected. Without error correction or detection in an analog CiM architecture or structure, increasing error rates are likely given that increasingly more bits are being stored in individual memory cells of analog CiM architectures or structures.

As described in more details below, this disclosure describes methods to enable error detection that is “in-memory” for an analog CiM architecture or structure to monitor for faults in an analog domain without digitalization. The methods include counting a total number of 1's in data stored to analog CiM memory cells (e.g., summation of individual digits) and store the summation in binary in a parallel capacitor structure. A summation value is then stored in parity bits in a C-2C capacitor ladder structure. Bit flips (e.g., caused by soft errors) could cause a sum comparison of the summation with the parity value to not match or fail and could trigger an error detection alarm.

FIG.1illustrates an example multiplier architecture100. In some examples, multiplier architecture100can represent a portion of a practical and efficient in-memory computing architecture that includes an integrated MAC unit and memory cell (which can be referred to as an arithmetic memory cell). The arithmetic memory cell employs analog computing methods so that a number of transistors of the integrated MAC unit is similar to a number of transistors of the memory cell (e.g., the transistors are a same order of magnitude) to reduce compute latency. For example, a neural network can be represented as a structure that is a graph of neuron layers flowing from one to the next. The outputs of one layer of neurons are the inputs of the next. To perform these calculations, a variety of matrix-vector, matrix-matrix, and tensor operations are required, which are themselves comprised of many MAC operations. Indeed, there are so many of these MAC operations in a neural network, that such operations may dominate other types of computations (e.g., the Rectified Linear Unit (ReLU) activation and pooling functions). Therefore, the MAC operation is enhanced by reducing data fetches from long term storage and distal memories separated from the MAC unit. Thus, examples described in this disclosure merge the MAC unit with the memory as shown in multiplier architecture100to reduce longer latency data movement and fetching (e.g., for neural network applications) Also, analog-based mixed-signal computing that is more efficient than digital (e.g., at low precision), can be employed to reduce data movement costs as compared to conventional digital processors and to also circumvent energy-hungry analog to digital conversions.

As shown inFIG.1, multiplier architecture100includes memory array102(which is coupled to one or more unillustrated substrates) and a C-2C based multiplier104(which can also be coupled to the one or more substrates) and the memory array102. C-2C based multiplier104shown inFIG.1can be configured as a C-2C ladder that includes a series of capacitors C segmented into 4 branches, each branch can be considered a separate multiple shown inFIG.1as304a,304b,304c,304d. As shown inFIG.1, respective branch/multipliers304a,304b,304cand304dinclude respective switches160,162,164and166. Also, as shown inFIG.1, respective branch/multipliers304a,304b,304cand304dinclude respective capacitors132,134,136and138that each have a one unit capacitance and include respective capacitors140,142,144and146that each have a two unit capacitance. In some examples, capacitors included in multiplier architecture100can be configured as an overlapping structure of passive metal-oxide-metal (MOM) capacitor situated above an SRAM cell active region.

In some examples, multipliers104a,104b,104c,104dcan be configured to receive digital signals from memory array102, execute a multibit computation operation with the plurality of capacitors132/140,134/142,136/144and138/146based on the digital signals and output a first analog signal OAnthat is sent towards an analog-digital-converter (ADC)182(via a CiM bit line (BL)181based on the multibit computation operation. OAncan also be referred to as a output voltage (V out) The multibit computation operation can be further based on an input analog signal IAnreceived via a CiM word line (WL)171that originated from a digital-analog-converter (DAC)172and can also be referred to as a reference voltage (V REF). Memory array102, as shown inFIG.1, includes first, second, third and fourth memory cells102a,102b,102c,102d. Input activation signal IAnoriginated from DAC172via CiM WL171can be provided from a first layer of the neural network, while in-memory multiplier architecture100can represent a second layer of the neural network. For example, the C-2C based multiplier104may be applied to any layer of a neural network. The superscript “n” indicates that it is applied to (operates on) the nth layer of the neural network. As such, the C-2C based multiplier104(e.g., an in-memory multiplier) represents the nth layer of the neural network. IAncan represent an input activation signal at the nth layer, and can be the output of the previous layer (layer n−1). OAncan be the output signal at the nth layer, and it will be fed into the next layer (layer n+1) which can be arranged in similar architecture as shown inFIG.1for multiplier architecture100. DAC172, CiM WL171, ADC182and CiM BL181are described in more detail below in relation to an example CiM structure.

According to some examples, as shown inFIG.1, each of the plurality of multipliers104a,104b,104c,104dcan be associated with a respective one of memory cells102a,102b,102c,102d. For example, a first arithmetic memory cell108includes multiplier104aand memory cell102asuch that multiplier104areceives digital signals (e.g., weights) from the memory cell102a. A second arithmetic memory cell110includes multiplier304band memory cell102bsuch that multiplier304breceives digital signals (e.g., weights) from memory cell102b. A third arithmetic memory cell112includes multiplier104cand memory cell102csuch that multiplier104creceives digital signals (e.g., weights) from memory cell102c. A fourth arithmetic memory cell114includes multiplier104dand memory cell302dsuch that multiplier104dreceives digital signals (e.g., weights) from memory cell102d.

In some examples, the weights W, obtained during a neural network training progress and can be preloaded in the network, can be stored in a digital format for information fidelity and storage robustness. With respect to the input activation (which is the analog input signal IAn) and the output activation (which is the analog output signal OAn), the priority can be shifted to the dynamic range and response latency. That is, analog scalars of analog signals, with an inherent unlimited number of bits and continuous time-step, outperforms other storage candidates Thus, multiplier architecture100(e.g., a neural network) receives the analog input signal IAn(e.g., an analog waveform) as an input and stores digital bits as its weight storage to enhance neural network application performance, design and power usage. In some examples, memory cells102a,102b,102c,102dcan be arranged to store different bits of a same multibit weight.

According to some examples, arithmetic memory cell108of arithmetic memory cell108,110,112,114is discussed below as an example for brevity, but it will be understood that arithmetic memory cells110,112,114are similarly configured to arithmetic memory cell108. For these examples, memory cell102astores a first digital bit of a weight in a digital format. That is, memory cell102aincludes first, second, third and fourth transistors120,122,124and126. The combination of the first, second, third and fourth transistors120,122,124and126store and output the first digital bit of the weight. For example, the first, second, third and fourth transistors120,122,124and126output weight signals Wn0(0)and Wbn0(0)which represent a digital bit of the weight. The conductors that transmit the signal weight Wn0(0)are represented inFIG.1as an unbroken line and the conductors that conduct the weight signal Wbn0(0)are represented inFIG.1as a broken line for clarity. The fifth and sixth transistors128,130can selectively conduct electrical signals from a cell bit line (BL) from among BL(0)and BLb(0)in response to an electrical signal of a cell word line (WL) meeting a threshold (e.g., voltage of cell WL exceeds a voltage threshold). That is, the electrical signal of the cell WL is applied to gates of the fifth and sixth transistors128,130and the electrical signals of BL(0)and BLb(0)are applied to sources of the fifth and sixth transistors128,130.

In some examples, signals Wn0(0)and Wbn0(0)from memory cell302acan be provided to multiplier304aand as shown schematically by the locations of the weight signals Wn0(0)and Wbn0(0)(which represent the digital bit). Multiplier304aincludes capacitors132,140, where capacitor132can include a capacitance 2C that is double a capacitance C of capacitor140. Switch160of multiplier304acan be formed by a first pair of transistors150and a second pair of transistors152. The first pair of transistors150can include transistors150a,150band selectively couple to input analog signal IAn(e.g., input activation) to capacitor132based on the weight signals Wn0(0), Wbn0(0). The second pair of transistors152can include transistors152a,152bthat selectively couple capacitor132to ground based on the weight signals Wn0(0), Wbn0(0). Thus, capacitor132can be selectively coupled between ground and input analog signal IAnbased on weight signals Wn0(0), Wbn0(0). That is, one of the first and second pairs of transistors150,152can be in an ON state to electrically conduct signals, while the other of the first and second pairs of transistors150,152can be in an OFF state to electrically disconnect terminals. For example in a first state, the first pair of transistors150can be in an ON state to electrically connect capacitor132to input analog signal IAnwhile the second pair of transistors152is in an OFF state to electrically disconnect capacitor132from ground. In a second state, the second pair of transistors152can be in an ON state to electrically connect capacitor132to the ground while the first pair of transistors150is in an OFF state to electrically disconnect the capacitor132from input analog signal IAn. Thus, capacitor132can be selectively electrically coupled to ground or input analog signal IAnbased on the weight signals Wn0(0)and Wbn0(0).

As mentioned above, arithmetic memory cells110,112,114can be formed similarly to arithmetic memory cell108. That is, a cell BL from among BL(1), BLb(1)and the cell WL can selectively control memory cell102bto generate and output the weight signals Wn0(1)and Wbn0(1)(which represents a second bit of the weight). Multiplier104bincludes capacitor134that can be selectively electrically coupled to ground or input analog signal IAnthrough switch162and based on the weight signals Wn0(1)and Wbn0(1)generated by memory cell102b.

Similarly, a cell BL from among BL(2), BLb(2)and the cell WL can selectively control the third memory cell102cto generate and output weight signals Wn0(2)and Wbn0(2)(which represents a second bit of the weight). Multiplier104cincludes capacitor136that can be selectively electrically coupled to ground or input analog signal IAnthrough switch164based on weight signals Wn0(2)and Wbn0(2)generated by memory cell102b. Likewise, a cell BL from among BL(3), BLb(3)and the cell WL can selectively control memory cell102dto generate and output weight signals Wn0(3)and Wbn0(3)(which represents a fourth bit of the weight). Multiplier104dincludes a capacitor138that can selectively electrically couple to ground or input analog signal IAnthrough switch166based on weight signals Wn0(3)and Wn0(3)generated by memory cell102b. Thus, each of the first-fourth arithmetic memory cells108,110,112,114provides an output based on the same input activation signal IAnbut also on a different bit of the same weight.

According to some examples, the first-fourth arithmetic memory cells108,110,112,114operate as a C-2C ladder multiplier. Connections between different branches of this C-2C ladder multiplier includes capacitors140,142,144. The second, third and fourth multipliers104b,104c,104dare respectively downstream of the first, second and third multipliers104a,104b,104c. Thus, outputs from the first, second and third multipliers104a,104b,104cand/or first, second and third arithmetic memory cells108,110,112are binary weighted through the capacitors140,142,144. As shown inFIG.1, the fourth arithmetic memory cell114does not include a capacitor at an output thereof since there is no arithmetic memory cell downstream of the fourth arithmetic memory cell114. The product is then obtained at the output node at the end of the C-2C ladder. Multiplier architecture100can generate output analog signal OAn, which corresponds to the below example equation 1. Example equation 1 is an example equation of an m-bit multiplier:

In example equation 1, m+1 is equal to the number of bits of the weight. In this particular example, m is equal to three (m iterates from 0-3) since there are 4 weight bits as noted above. The “i” in example equation 1 corresponds to a position of a weight bit (again ranging from 0-3) such that Wiis equal to the value of the bit at the position. It is worthwhile to note that example equation 1 can be applicable to any m-bit weight value. For example, if hypothetically the weight included more bits, more arithmetic memory cells may be added do the multiplier architecture100to process those added bits (in a 1-1 correspondence).

In some examples, multiplier architecture100employs a cell charge domain multiplication method by implementing a C-2C ladder for a type of digital-to-analog-conversion of bits of a weight maintained in memory cells. The C-2C ladder can be a capacitor network including capacitors132,134,136,138having capacitance C, and capacitors140,142,144that have capacitance 2C. The capacitors132,134,136,138,140,142,144are shown inFIG.1as being segmented into branches and can provide low power analog voltage outputs such as OAnto an ADC such as ADC182.

According to some examples, memory array102and the C-2C based multiplier104can be disposed proximate to each other. For example, memory array102and the C-2C based multiplier104may be part of a same semiconductor package and/or in direct contact with each other. Moreover, memory array102can be an SRAM structure, but memory array102can also be readily modified to be of various memory structures (e.g., dynamic random-access memory, magnetoresistive random-access memory, phase-change memory, etc.) without modifying operation of the C-2C based multiplier104mentioned above.

As described in more detail below, a multiplier architecture such as the above-described multiplier architecture100can be included in a CiM structure as a node among a plurality of nodes in an array.

FIG.2illustrates an example CiM structure200. According to some examples, as shown inFIG.2, CiM structure200include an array210having a plurality of nodes that represent a complete tile structure. For these examples, input data obtained from input data buffer260can be converted to an analog input signal IAa/VREFby a DAC from among DACs172-1to172-6and then multiplied by 4-bit weight elements maintained at each node (e.g., maintained at memory cell102) along a selected CiM WL from among CiM WLs171-1to171-6. Computed analog outputs OAn/VOUTfrom the nodes along a CiM BL from among CiM BLs181-181-6can be tied together for summation in a charge domain. An ADC from among ADCs182-1to182-6can then convert the summation into a digital signal/value that is then stored to output data buffer270.

For example CiM structure200, an expanded view of a single node is depicted inFIG.1that shows a simplified representation of multiplier architecture100. The simplified representation of multiplier architecture100indicates that an analog input signal IAncan be received via a CiM WL171-4that was generated by DAC172-4. A multiplication operation can be performed using 4-bit weight elements maintained in b0, b1, b2and b3to generate analog output OAn. OAncan then be sent via a CiM BL181-5for summation in a charge domain with other nodes along CiM BL181-5for eventual conversion of the summation by ADC182-5into a digital signal/value that can then be stored to output data buffer270.

Examples are not limited to an array that includes nodes arranged in a 6×6 matrix as shown inFIG.2. Also, examples are not limited to 4-bit weight elements maintained at each node. Also, examples are not limited to 6 DACs or 6 ADCs.

FIG.3illustrates an example summation check logic300. In some examples, as shown inFIG.3, data bits305can be encoded using data summation circuitry310and parity bits315can be encoded with parity value circuitry320. Data bits305includes Do to D15, where “D” represents a binary “1” or “0” for weight bits maintained in a group of SRAM memory cells such as memory cells102a-dof memory array102shown inFIG.1or2. Do to D15, for example, can represent individual weight bits maintained in a group of 4 memory arrays102that includes a total of 16 bits. Parity bits315includes P0to P4that represent a 5-bit parity value to indicate a number of 1's expected to be included in Do to Dis. Parity bits315can also be a memory array similar to memory array102, but includes an extra memory cell compared to the 4-bit memory arrays shown inFIG.1or2. For these examples, the total number of expected 1's is based on a fixed weight matrix that can be preloaded to the group of SRAM memory cells.

According to some examples, the 16-bits included in data bits305and the 5-bits included in parity bits315is to cover parity values from 0 to 16, where the lower two bits (P1and P0) are both least significant bits LSB (e.g., weight of 1). For example, a binary output of 11111=8+4+2+1+1=16 and a binary output of 11110=8+4+2+1+0=15. Since a total of 16 1's are possible in data bits305, the additional parity bit is needed to indicate up to a value of 16.

In some examples, as shown inFIG.3, data summation circuitry310is arranged as a parallel capacitor structure that outputs a VOUTindicative of a summation of 1's included in data bits305stored in SRAM memory cells. The summation can range from 0 to 16. Also, parity value circuitry320is arranged as a C-2C capacitor ladder that can operate in similar manner to C-2C based multiplier104shown inFIGS.1and2to output a VOUTindicative of a 5-bit parity value that has the lower two bits as LSB bits.

FIG.4illustrates a summation check scheme400. According to some examples, encoding405indicates an example encoding for the 5 parity bits included in parity bits315to implement summation check scheme400. For these examples, a total summation of data bits and a parity value equals an example fixed value of 16. So as shown inFIG.4for example encoding405, if data bits305includes 16 1's, then parity bits P4-P0included in parity bits315are encoded as 00000 having a binary value of 0. If 16 is added to 0 the total would equal 16. Also, the other 2 examples shown for encoding405depict an encoding based on 8 1's and 11 1's having respective parity values of 8 and 5 to both generate an expected summation of 16.

In some examples, as described more below, matching logic can include logic and/or circuitry to compare summation results to the fixed value of 16 to see if they match. If a match occurs than no errors are detected. If the summation results do not match the fixed value of 16, an error is detected. Detection of an error can cause mitigation actions to include, but not limited to reloading bit weights to the group of SRAM memory cells corresponding to Do to Dis of data bits305and/or reloading the encoded parity value to parity bits315.

FIG.5illustrates a summation check scheme500. According to some examples, encoding505indicates an example encoding for the 5 parity bits included in parity bits315to implement summation check scheme500. For these examples, the summation of data bits equals a corresponding parity value. So as shown inFIG.5for example encoding505, if data bits includes 16 1's, then parity bits P4-P0included in parity bits315are encoded as 11111 having a binary value of 16. Also, the other 2 examples shown for encoding505depict an encoding based on 8 1's and 11 1's having respective parity values of 8 and 11.

In some examples, as described more below, matching logic can include logic and/or circuitry to compare summation results of bits Do to Dis included in data bits305to the parity binary value maintained in P0to P4included in parity bits315to see if they match (e.g., same Vout). If a match occurs than no errors are detected. If the summation results of data bits305does not match (e.g., different V out) the parity value encoded in parity bits315, an error is detected. Detection of an error can cause mitigation actions to include, but not limited to reloading bit weights to the group of SRAM memory cells corresponding to Do to Dis of data bits305and/or reloading the encoded parity value to parity bits315.

FIG.6illustrates an example matching logic600. In some examples, as shown inFIG.6, matching logic includes a comparator circuit601, XOR logic602, or a difference (dff) logic603. For these example, dff logic603can determine a difference based on Vout− and Vout+ responsive to a sensing clock604. Matching logic600, in other words, serves as an analog comparator to compare a summation total (Vin−) with an expected value (Vin+). For examples, where the 16 data bits are protected with 5 parity bits, The expected value can depend on whether summation check scheme400(expected value of 16) or summation check scheme500(expected parity value matches number of 1's in data bits) is implemented.

According to some examples, as shown inFIG.6, a more detailed view of comparator circuit601is shown that includes 9 transistors609to617. Vin− activates transistor613and Vin+ activates614and Vout− can be sampled at node620and Vout+ can be sampled at node622to provide Vout− and Vout+.

In some examples, a 1-step comparison is implemented by matching logic600based on an equal-to-match method that outputs 1 or 0 if one input to comparator circuit601is greater or less that the other. For this 1-step comparison, a comparison time takes time to sense a difference and a Tdelaycan be inversely proportional to an input voltage difference. Tdelayis shorter when the two input voltages (Vin−, Vin+) have a larger difference and much longer if the two input voltages have a larger difference. A careful selection can be needed to select a clock cycle time for sensing clock604such that the output voltage (Vout−, Vou+) is not settled when a clock signal sense by sensing clock604causes an output of XOR602for two substantially identical input voltages.

According to some examples, due to possible difficulties in selection of a Tdelaydue to process variations in manufacturing a CiM structure that includes matching logic600, a 2-step comparison can be implemented. So instead of doing equal-to-match, the comparison is divided into two steps that provide two separate reference voltages for either matching logic600or summation check logic300(seeFIG.3).

A 2-step comparison method based on summation check scheme400(expected value of 16) includes a first step to check if all summations (e.g., Vin+) are greater than 15.5 via providing a first reference voltage (e.g., Vin−) to matching logic600and a second step to check if all summations are less than 16.5 via providing a second reference voltage to matching logic600. If all summations are found to be greater than 15.5 but less than 16.5, a match is found.

In some examples, a 2-step comparison method based on summation check scheme500(expected data bits1's equals parity value) includes adjusting a supply voltage at a parity side of summation check logic300(seeFIG.3). For these examples, instead of VDD, 15/16 VDDor 17/16VDDor simply VDD+and VDD−. The first step of this 2-step comparison method is to replace VDDshown inFIG.3for both data summation circuitry310and parity value circuitry320with VDD+and a left wing of summation check logic300(data) should be less than a right wing of summation check logic300(parity). The second step is to change the supply voltage to VDD−and the left wing should be greater than the right wing of summation check logic300. Each step of this two-step method detects part of a failure case. In order to monitor summation values of the SRAM array from which data bits305are obtained, a toggling between the two steps is needed for this two-step method based on summation check scheme500.

FIG.7illustrates various error examples710,720,730and740. According to some examples, the error examples shown inFIG.7are based on summation check scheme500, but a similar analysis could be applied to summation check scheme400as well. Error example710shows a single bit error that would be detected by a mismatch between sum of left wing and right wing due to a bit flip of the filled in circle of data bits305that can be a bit flip from a 0 to 1 or a 1 to 0 that causes the left wing to have a +/−1 summation value and the right wing having a +0 parity value change (no change). Error examples,720and730show 2-bit error examples. For error example720, the 2-bit error occurs in data bits305by two bits flipping from 0 to 1 and this causes the left wing to have a +2 summation value and the right wing having a +0 parity value change (no change). For example730, the 2-bit error occurs in both data bits305and parity bits315by a bit flipping from 0 to 1 in data bits305and another bit flipping from 0 to 1 in parity bits315. The bit flip in data bits305causes the left wing to a have a +1 summation value and cause the right wing to have a +4 parity value change.

In some examples, error examples740shown inFIG.7provides an examples of where bit flips could cancel each other out and result in a match or balance between the left and right wings. For example, if a first bit on the left wing flips from 0 to 1 and a second bit on the left flips from 1 to 0. Also, if a bit on the left wing flips from 0 to 1 and an LSB bit on the right wing flips from 0 to 1. Both these examples included in error examples740would not result in detection of the bit flip errors.

FIG.8illustrates an example coverage800. In some examples, as shown inFIG.8, coverage800includes a parity bit table810to indicate example number of parity bits needed to cover data bits of various lengths. For examples, as mentioned previously, 16 data bits would need 5 parity bits and the overhead needed to support would be about 15.6% greater than not providing any parity protection based on summation check schemes described above. 32 bits would need 6 with an added overhead of 18.8%. Since a higher ratio of parity bits to data bits is possible with 8 parity bits to cover80data bits, the added overhead of 10% is significantly less than the overhead needed to protect 16 or 32 bits.

According to some examples, coverage800also includes a coverage comparison table820. As shown inFIG.8, coverage comparison table820indicates a detection coverage of 16, 32 and 80 bits of data with 1/2/3b errors as compared to XOR-Parity ECC methods. As is shown in coverage comparison table820, an ability to detect 2b errors can result in summation check schemes providing a better coverage than XOR-Parity ECC methods.

According to some examples, a weight matrix loaded to SRAM cells of a CiM structure can be fixed and doesn't change during computation operations. Therefore, a summation check scheme can also be static. An ECC word organization can be chosen that is easiest or best fit to a given floorplan for a CiM structure or any other considerations.

FIG.9illustrates an ECC word configuration and floor plan900. ECC word configuration and floor plan900is an example of a horizontal ECC word organization that can apply a summation check along a horizontal word line where bits are logically related to at least one weight matrix. For example, as shown inFIG.9, two 8-bit words that are side-by-side are combined as one ECC word. The two 8-bit words can represent one weight matrix or two separate weight matrixes. In other words, the summation value to indicate a number of 1's included in these two 8-bit words is compared to the parity values encoded in corresponding parity bits of the one ECC word.

FIG.10illustrates an ECC word configuration and floor plan1000. ECC word configuration and floor plan1000is an example of a vertical ECC word organization that can apply a summation check along a vertical bit line where data bits with a same significance but from 16 different logical words are combined together for each ECC code word. For example, 16 MSB data bits form one ECC word, and 16 LSB data bits form another ECC word.

FIG.11illustrates an ECC word configuration and floor plan1100. ECC word configuration and floor plan1100is an example of a vertical ECC word organization as mentioned above for ECC word configuration and floor plant1000. However, data bits with higher significance (toward MSB) have a higher protection strength (more parity bits to protect fewer data bits). Also, data bits with lower significance (towards LSB) have a relatively lower protection strength (less parity bits to protect relatively more data bits). Overall, ECC word configuration and floor plan1100could be arranged such that a total number or check/parity bits needed to provide an acceptable level of error coverage can be less than ECC word configuration and floor plan900and/or1000.

FIG.12illustrates an example a memory-efficient computing system1258. The system1258may generally be part of an electronic device/platform having computing functionality (e.g., personal digital assistant/PDA, notebook computer, tablet computer, convertible tablet, server), communications functionality (e.g., smart phone), imaging functionality (e.g., camera, camcorder), media playing functionality (e.g., smart television/TV), wearable functionality (e.g., watch, eyewear, headwear, footwear, jewelry), vehicular functionality (e.g., car, truck, motorcycle), robotic functionality (e.g., autonomous robot), etc., or any combination thereof. In the illustrated example, the system1258includes a host processor1234(e.g., CPU) having an integrated memory controller (IMC)1254that is coupled to a system memory1244with instructions1256that implement some aspects of the embodiments herein when executed.

The illustrated system1258also includes an input output (TO) module1242implemented together with the host processor1234, a graphics processor1232(e.g., GPU), ROM1236and arithmetic memory cells1248on a semiconductor die1246as a system on chip (SoC). The illustrated IO module1242communicates with, for example, a display1272(e.g., touch screen, liquid crystal display/LCD, light emitting diode/LED display), a network controller1274(e.g., wired and/or wireless), FPGA1278and mass storage1276(e.g., hard disk drive/HDD, optical disk, solid state drive/SSD, flash memory) that may also include the instructions1256. Furthermore, the SoC1246may further include processors (not shown) and/or arithmetic memory cells1248dedicated to artificial intelligence (AI) and/or neural network (NN) processing. For example, the system SoC1246may include vision processing units (VPUs), tensor processing units (TPUs) and/or other AI/NN-specific processors such as arithmetic memory cells1248, etc. In some embodiments, any aspect of the embodiments described herein may be implemented in the processors and/or accelerators dedicated to AI and/or NN processing such as the arithmetic memory cells1248, the graphics processor1232and/or the host processor1234. The system1258may communicate with one or more edge nodes through the network controller1274to receive weight updates and activation signals.

It is worthwhile to note that the system1258and the arithmetic memory cells1248may implement in-memory multiplier architecture100(FIG.1), CiM structure200(FIG.2), summation check logic300(FIG.3) or matching logic600(FIG.6) already discussed. The illustrated computing system1258is therefore considered to implement new functionality and is performance-enhanced at least to the extent that it enables the computing system1258to execute operate on neural network data at a lower latency, reduced power and with greater area efficiency.

FIG.13illustrates an example semiconductor apparatus1386(e.g., chip, die, package). The illustrated apparatus1386includes one or more substrates1384(e.g., silicon, sapphire, gallium arsenide) and logic1382(e.g., transistor array and other integrated circuit/IC components) coupled to the substrate(s)1384. In an embodiment, the apparatus1386is operated in an application development stage and the logic1382performs one or more aspects of the embodiments described herein, for example, in-memory multiplier architecture100(FIG.1), CiM structure200(FIG.2), summation check logic300(FIG.3) or matching logic600(FIG.6) already discussed. Thus, the logic1382receives, with a first plurality of multipliers of a multiply-accumulator (MAC), first digital signals from a memory array, where the first plurality of multipliers includes a plurality capacitors. The logic1382executes, with the first plurality of multipliers, multibit computation operations with the plurality of capacitors based on the first digital signals. The logic1382generates, with the first plurality of multipliers, a first analog signal based on the multibit computation operations. The logic1382may be implemented at least partly in configurable logic or fixed-functionality hardware logic. In one example, the logic1382includes transistor channel regions that are positioned (e.g., embedded) within the substrate(s)1384. Thus, the interface between the logic1382and the substrate(s)1384may not be an abrupt junction. The logic1382may also be considered to include an epitaxial layer that is grown on an initial wafer of the substrate(s)1384.

FIG.14illustrates an example processor core1400according to one embodiment. The processor core1400may be the core for any type of processor, such as a micro-processor, an embedded processor, a digital signal processor (DSP), a network processor, or other device to execute code. Although only one processor core1400is illustrated inFIG.14, a processing element may alternatively include more than one of the processor core1400illustrated inFIG.14. The processor core1400may be a single-threaded core or, for at least one embodiment, the processor core1400may be multithreaded in that it may include more than one hardware thread context (or “logical processor”) per core.

FIG.14also illustrates a memory1470coupled to the processor core1400. The memory1470may be any of a wide variety of memories (including various layers of memory hierarchy) as are known or otherwise available to those of skill in the art. The memory1470may include one or more code1413instruction(s) to be executed by the processor core1400, wherein the code1413may implement one or more aspects of the embodiments such as, for example, in-memory multiplier architecture100(FIG.1), CiM structure200(FIG.2), summation check logic300(FIG.3) or matching logic600(FIG.6) already discussed. The processor core1400follows a program sequence of instructions indicated by the code1413. Each instruction may enter a front end portion1410and be processed by one or more decoders1420. The decoder1420may generate as its output a micro operation such as a fixed width micro operation in a predefined format, or may generate other instructions, microinstructions, or control signals which reflect the original code instruction. The illustrated front end portion1410also includes register renaming logic1425and scheduling logic1430, which generally allocate resources and queue the operation corresponding to the convert instruction for execution.

The processor core1400is shown including execution logic1450having a set of execution units1455-1through1455-N. Some embodiments may include a number of execution units dedicated to specific functions or sets of functions. Other embodiments may include only one execution unit or one execution unit that can perform a particular function. The illustrated execution logic1450performs the operations specified by code instructions.

After completion of execution of the operations specified by the code instructions, back end logic1460retires the instructions of the code1413. In one embodiment, the processor core1400allows out of order execution but requires in order retirement of instructions. Retirement logic1465may take a variety of forms as known to those of skill in the art (e.g., re-order buffers or the like). In this manner, the processor core1400is transformed during execution of the code1413, at least in terms of the output generated by the decoder, the hardware registers and tables utilized by the register renaming logic1425, and any registers (not shown) modified by the execution logic1450.

Although not illustrated inFIG.14, a processing element may include other elements on chip with the processor core1400. For example, a processing element may include memory control logic along with the processor core1400. The processing element may include I/O control logic and/or may include I/O control logic integrated with memory control logic. The processing element may also include one or more caches.

FIG.15illustrates an example computing system1500embodiment in accordance with an embodiment. Shown inFIG.15is a multiprocessor system1500that includes a first processing element1570and a second processing element1580. While two processing elements1570and1580are shown, it is to be understood that an embodiment of the system1500may also include only one such processing element.

The system1500is illustrated as a point-to-point interconnect system, wherein the first processing element1570and the second processing element1580are coupled via a point-to-point interconnect1550. It should be understood that any or all of the interconnects illustrated inFIG.15may be implemented as a multi-drop bus rather than point-to-point interconnect.

As shown inFIG.15, each of processing elements1570and1580may be multicore processors, including first and second processor cores (i.e., processor cores1574aand1574band processor cores1584aand1584b). Such cores1574a,1574b,1584a,1584bmay be configured to execute instruction code in a manner similar to that discussed above in connection withFIG.11.

Each processing element1570,1580may include at least one shared cache1596a,1596b. The shared cache1596a,1596bmay store data (e.g., instructions) that are utilized by one or more components of the processor, such as the cores1574a,1574band1584a,1584b, respectively. For example, the shared cache1596a,1596bmay locally cache data stored in a memory1532,1534for faster access by components of the processor. In one or more embodiments, the shared cache1596a,1596bmay include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, a last level cache (LLC), and/or combinations thereof.

While shown with only two processing elements1570,1580, it is to be understood that the scope of the embodiments are not so limited. In other embodiments, one or more additional processing elements may be present in a given processor. Alternatively, one or more of processing elements1570,1580may be an element other than a processor, such as an accelerator or a field programmable gate array. For example, additional processing element(s) may include additional processors(s) that are the same as a first processor1570, additional processor(s) that are heterogeneous or asymmetric to processor a first processor1570, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays, or any other processing element. There can be a variety of differences between the processing elements1570,1580in terms of a spectrum of metrics of merit including architectural, micro architectural, thermal, power consumption characteristics, and the like. These differences may effectively manifest themselves as asymmetry and heterogeneity amongst the processing elements1570,1580. For at least one embodiment, the various processing elements1570,1580may reside in the same die package.

The first processing element1570may further include memory controller logic (MC)1572and point-to-point (P-P) interfaces1576and1578. Similarly, the second processing element1580may include a MC1582and P-P interfaces1586and1588. As shown inFIG.15, MC's1572and1582couple the processors to respective memories, namely a memory1532and a memory1534, which may be portions of main memory locally attached to the respective processors. While the MC1572and1582is illustrated as integrated into the processing elements1570,1580, for alternative embodiments the MC logic may be discrete logic outside the processing elements1570,1580rather than integrated therein.

The first processing element1570and the second processing element1580may be coupled to an I/O subsystem1590via P-P interconnects1576,1586, respectively. As shown inFIG.15, the I/O subsystem1590includes P-P interfaces1594and1598. Furthermore, I/O subsystem1590includes an interface1592to couple I/O subsystem1590with a high performance graphics engine1538. In one embodiment, bus1549may be used to couple the graphics engine1538to the I/O subsystem1590. Alternately, a point-to-point interconnect may couple these components.

In turn, I/O subsystem1590may be coupled to a first bus1516via an interface1596. In one embodiment, the first bus1516may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I/O interconnect bus, although the scope of the embodiments are not so limited.

As shown inFIG.15, various I/O devices1514(e.g., biometric scanners, speakers, cameras, sensors) may be coupled to the first bus1516, along with a bus bridge1518which may couple the first bus1516to a second bus1520. In one embodiment, the second bus1520may be a low pin count (LPC) bus. Various devices may be coupled to the second bus1520including, for example, a keyboard/mouse1512, communication device(s)1526, and a data storage unit1519such as a disk drive or other mass storage device which may include code1530, in one embodiment. The illustrated code1530may implement the one or more aspects of such as, for example, in-memory multiplier architecture100(FIG.1), CiM structure200(FIG.2), summation check logic300(FIG.3) or matching logic600(FIG.6) already discussed. Further, an audio I/O1524may be coupled to second bus1520and a battery1510may supply power to the computing system1500.

Note that other embodiments are contemplated. For example, instead of the point-to-point architecture ofFIG.15, a system may implement a multi-drop bus or another such communication topology. Also, the elements ofFIG.15may alternatively be partitioned using more or fewer integrated chips than shown inFIG.15.

The following examples pertain to additional examples of technologies disclosed herein.

Example 1. An example apparatus can include first circuitry to generate a summation of binary 1's for a weight matrix stored in a first group of memory cells of a CiM structure. The apparatus can also include second circuitry to generate a parity value for parity bits stored to a second group of memory cells of the CiM structure. The apparatus can also include third circuitry to compare the summation of binary 1's and the parity value to an expected value and indicate whether one or more bit errors in the first or the second group of memory cells is detected based on the comparison.

Example 2. The apparatus of example 1, the first circuitry can be arranged as a parallel capacitor structure that outputs a first VOUTindicative of the summation of binary 1's and the second circuitry can be arranged as a capacitor to 2 capacitor (C-2C) ladder to output a second VOUTindicative of the parity value.

Example 3. The apparatus of example 2, the expected value can be based on a total number of memory cells included in the first group of memory cells. Each memory cell included in the first group of memory cell can be arranged to store a single bit. For this example, the third circuitry can include an analog comparator to compare a first input that includes a summation of the first VOUTand the second VOUTwith a second input that includes a voltage representative of the expected value. Also, the analog comparator can output an indication of whether the first and the second input match, a match indication to indicate no detectable bit errors in the first or the second group of memory cells.

Example 4. The apparatus of example 2, the expected value can be based on a total number of memory cells included in the first group of memory cells, each memory cell included in the first group of memory cell can be arranged to store a single bit. Also, the third circuitry can include an analog comparator to compare the first VOUTto the second VOUTand output an indication of whether the first VOUTand the second VOUTmatch, a match indication to indicate no detectable bit errors in the first or the second group of memory cells.

Example 5. The apparatus of example 1, the second group of memory cells can include a number of memory cells to store a parity value in n bits, where n can represent a number of binary bits capable of indicating a range of parity values from 0 to a value equal to all memory cells of the first group of memory cells storing binary 1's.

Example 6. The apparatus of example 1, the first group of memory cells and the second group of memory cells can include SRAM cells.

Example 7. An example method can include determining a total number of binary 1's for a weight matrix stored in a first group of memory cells of a CiM structure. The method can also include determining a parity value for parity bits stored to a second group of memory cells of the CiM structure. The method can also include comparing the determined total number of binary 1's and the determined parity value to an expected value and detecting one or more bit errors in the first or the second group of memory cells based on the comparison.

Example 8. The method of example 7, the expected value can be based on a total number of memory cells included in the first group of memory cells, each memory cell included in the first group of memory cell arranged to store a single bit.

Example 9. The method of example 8, the determined total number of binary 1's and the determined parity value to the expected value can include comparing the determined total number of binary 1's to the expected value and comparing the determined parity value to the expected value, individually, wherein the expected value is based on an expected total number of binary 1's stored to the first memory cells.

Example 10. The method of example 9, comparing the determined total number of binary 1's and the determined parity value to the expected value can include combining the determined total number of binary 1's and the determined parity value and comparing the combined value to the expected value.

Example 11. The method of example 7, the second group of memory cells can include a number of memory cells to store a parity value in n bits, where n can represent a number of binary bits capable of indicating a range of parity values from 0 to a value equal to all memory cells of the first group of memory cells storing binary 1's.

Example 12. The method of example 7, determining the total number of binary 1's and determining the parity value can be done in an analog domain.

Example 13. The method of example 7, the first group of memory cells and the second group of memory cells can be SRAM cells.

Example 14. The method of example 8, the computational nodes of the first group and the second group can individually include SRAM bits cells that are arranged to store weight bits.

Example 15. An example at least one machine readable medium can include a plurality of instructions that in response to being executed by a system can cause the system to carry out a method according to any one of examples 7 to 14.

Example 16. An example apparatus can include means for performing the methods of any one of examples 7 to 14.

Example 17. An example CiM structure can include a first group of memory cells to maintain at least a portion of at least one weight matrix for use in computations. The CiM structure can also include a second group of memory cells to maintain parity bits associated with the at least a portion of at least one weight matrix. The CiM structure can also include first circuitry to generate a summation of binary 1's for the at least a portion of at least one weight matrix. The CiM structure can also include second circuitry to generate a parity value based on the parity bits. The CiM structure can also include third circuitry to compare the summation of binary 1's and the parity value to an expected value and indicate whether one or more bit errors in the first or the second group of memory cells is detected based on the comparison.

Example 18. The CiM structure of example 17, the first circuitry can be arranged as a parallel capacitor structure that outputs a first VOUTindicative of the summation of binary 1's and the second circuitry can be arranged as a capacitor to 2 capacitor (C-2C) ladder to output a second VOUTindicative of the parity value.

Example 19. The CiM structure of example 18, the expected value can be based on a total number of memory cells included in the first group of memory cells, each memory cell included in the first group of memory cell arranged to store a single bit. For this example, the third circuitry can be an analog comparator to compare a first input that includes a summation of the first VOUTand the second VOUTwith a second input that includes a voltage representative of the expected value. The analog comparator can output an indication of whether the first and second inputs match, an indication to indicate no detectable bit errors in the first or the second group of memory cells.

Example 20. The CiM structure of example 18, the expected value can be based on a total number of memory cells included in the first group of memory cells, each memory cell included in the first group of memory cell arranged to store a single bit. The third circuitry can also include an analog comparator to compare the first VOUTto the second VOUTand output an indication of whether the first VOUTand the second VOUTmatch. A match indication can indicate no detectable bit errors in the first or the second group of memory cells.

Example 21. The CiM structure of example 17, the second group of memory cells can include a number of memory cells to store a parity value in n bits, where n can represent a number of binary bits capable of indicating a range of parity values from 0 to a value equal to all memory cells of the first group of memory cells storing binary 1's.

Example 22. The CiM structure of example 17, the first group of memory cells and the second group of memory cells can be SRAM cells.

Example 23. The CiM structure of example 17, the first group of memory cells can be situated along a same word line of the CiM structure and can be logically related to the at least one weight matrix.

Example 24. The CiM structure of example 17, the first group of memory cells can be situated along a same bit line and can have a same binary bit significance but are not logically related to the same at least one weight matrix.

Example 25. The CiM structure of example 25 can also include a third group of memory cells to maintain a second portion of the at least one weight matrix and also include a fourth group of memory cells to maintain parity bits associated with the second portion of the at least one weight matrix. The second portion can include least significant bits (LSBs) of the at least one weight matrix. The first group of memory cells can include most significant bits (MSBs) of the at least one weight matrix. For this example, the second group of memory cells can maintain a higher number of parity bits compared to parity bits maintained in the fourth group of memory cells.