Electrical energy storage capacitor power supply capable of shorting out defective capacitors

There is disclosed a power supply for storing electrical energy in capacitors connected in series, the power supply having a function of shorting out capacitors at fault. Shorting means are connected in parallel with the capacitors, respectively. If any one of the capacitors is charged abnormally, it is detected by detection means. The terminals of this detected capacitor are shorted out by the corresponding one of the shorting means. The shorting means can also act as bypass means ancillary to parallel monitors, respectively. By detecting temperature rises of the bypass means, abnormal charging of the capacitors can be judged.

FIELD OF THE INVENTION 
The present invention relates to a power supply for storing electrical 
energy in capacitors connected in series and, more particularly, to an 
electrical energy storage capacitor power supply having a function of 
shorting out capacitors at fault. 
BACKGROUND OF THE INVENTION 
An energy capacitor system (ECS) is an electrical power storage system 
consisting of capacitors, parallel monitors and a current pump, and has 
been already introduced in literature (e.g., "A Basic Study on Power 
Storage Capacitor Systems", Denki Gakkai Ronbunshi, Vol. 115-B, No. 5, May 
1995, pp. 504-510). In the ECS, electrical energy is stored in the plural 
capacitors connected in series. A charging control circuit known as a 
parallel monitor is connected across the terminals of each capacitor. 
During charging, the parallel monitor bypasses the charging current around 
the capacitor when the terminal voltage has reached a preset voltage, and 
thus prevents further charging of the capacitor. 
As a result, all the capacitors connected in series are uniformly charged 
up to the preset voltage. In consequence, it is possible to derive almost 
the full storage capacity of the capacitor assemblage. 
Today, manufacture of a large-sized energy capacitor system using thousands 
of electrical double layer capacitors is being discussed. Whenever a few 
capacitors of such a large-sized energy capacitor system are at fault, if 
the operation is stopped and the defective capacitors are replaced, the 
efficiency of the operation will not be high. If the operation is 
continued without replacing the defective capacitors, and if the whole 
system is serviced at regular intervals of time, then the efficiency of 
the operation of the system will be enhanced. This will save the cost of 
servicing the system. 
It is an object of the present invention to provide a power supply that 
acts to store electrical energy in capacitors and has a function of 
shorting out defective capacitors. 
SUMMARY OF THE INVENTION 
Briefly, in accordance with the teachings of the invention, a power supply 
for storing electrical energy in capacitors connected in series comprises 
shorting means connected in parallel with the capacitors, respectively, 
and detection means. If any one of the capacitors is charged abnormally, 
the corresponding detection means detects the abnormal charging. If any 
one of the capacitors is judged to be charged abnormally by the 
corresponding detection means, the corresponding shorting means shorts out 
the terminals of these capacitors.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
Referring to FIG. 1, there is shown a power supply for storing electrical 
energy in capacitors, the power supply having a function of shorting out 
defective capacitors in accordance with the present invention. The 
capacitors, C.sub.1 -C.sub.N, are connected in series to form a capacitor 
bank. These capacitors are charged by a charger 1. The electric power 
stored in the capacitor bank is supplied in the form of appropriate 
current and voltage to a load via a current pump 2. 
Parallel monitors 3.sub.1 -3.sub.N are connected with the capacitors 
C.sub.1 -C.sub.N, respectively. The parallel monitors 3.sub.1 -3.sub.N 
comprise diodes D.sub.1 -D.sub.N connected with the capacitors C.sub.1 
-C.sub.N, respectively, with a reverse polarity to the charging current, 
semiconductor switching devices (power transistors) Q.sub.1 -Q.sub.N, 
respectively, connected with the capacitors C.sub.1 -C.sub.N, 
respectively, so as to bypass the charging current, and monitor control 
circuits 4.sub.1 -4.sub.N respectively, for controlling the transistors 
Q.sub.1 -Q.sub.N, respectively. 
Each of the monitor control circuits 4.sub.1 -4.sub.N serves to control the 
charging and abnormality. With respect to the charging control function, 
the monitor control circuits 4.sub.1 -4.sub.N monitor the terminal 
voltages of the capacitors, respectively. When the terminal voltage of any 
one of the capacitors reaches a preset value, the corresponding control 
circuit turns on the corresponding one of the transistors Q.sub.1 -Q.sub.N 
to bypass the charging current. Consequently, this capacitor is stopped 
from being charged, and the terminal voltage is maintained at the preset 
value. The other capacitors are kept charged. This function is known and 
intrinsic to the parallel monitors. 
With respect to the abnormality control function, if any one of the 
capacitors is at fault and charged abnormally, the corresponding one of 
the monitor control circuits 4.sub.1 -4.sub.N turns on the corresponding 
one of the transistors Q.sub.1 -Q.sub.N, thus shorting out the defective 
capacitor. 
A first preferred method of judging whether the charging is abnormal due to 
failure in any one of the capacitors C.sub.1 -C.sub.N is to use detection 
of abnormal increase in temperature due to heat generation from the 
corresponding one of the transistors Q.sub.1 -Q.sub.N. 
A second preferred method is to monitor the terminal voltages for sensing 
whether any one of the terminal voltages is abnormally higher from the 
start of the charging. 
A third method is to detect the time between the instant of the start of 
the charging and the instant when a given terminal voltage is reached for 
judging whether the time duration is abnormal. 
These methods have been devised, taking account of phenomena occurring 
during charging, i.e., any capacitor is at fault and thus opened, whereby 
its capacitance is reduced dramatically. In particular, if the capacitance 
decreases down to an extremely low level, the terminal voltage rises at a 
higher rate than the terminal voltages of the other normal capacitors. As 
a result, the charging control function of the corresponding parallel 
monitor turns on the semiconductor control device in a short time from the 
start of charging. This conducting state is maintained for a long time 
until the other normal capacitors are charged fully. Prolonged bypassing 
of the charging current accumulates heat, making the semiconductor control 
device in charge of the defective capacitor hotter than in a normal state. 
Accordingly, if an abnormal temperature rise of the semiconductor control 
device is detected by the first method described above, then an abnormally 
charged state of the capacitor can be detected. For this purpose, 
temperature sensors for detecting the temperatures of the semiconductor 
control devices and means for comparing the detected temperatures with a 
reference temperature value are necessary. 
If the capacitance of any one capacitor has decreased almost to the zero 
level due to failure, the terminal voltage will quickly reach the full 
charge voltage after the charging. Accordingly, if the terminal voltages 
are monitored from the start of the charging by the second method, and if 
any one of the terminal voltages is higher, then the corresponding 
capacitor can be judged to be charged abnormally. In order to implement 
the second method, means (i) receiving a charge start signal from the 
charger and detecting the terminal voltages of the capacitors and 
comparison means (ii) for comparing the detected terminal voltages with a 
threshold value are necessary. 
If the capacitance of any one capacitor decreases, the terminal voltage 
rises at a higher rate than the terminals of the other normal capacitors. 
Therefore, if the third method described above is used to sense that the 
time elapsed until a given terminal voltage is reached from the start of 
charging is shorter than a threshold value, then the capacitor is judged 
to be at fault. To carry out the third method, time-measuring means and 
comparison means are necessary. The time-measuring means receives a 
charging start signal from the charger and counts time until the terminal 
voltages of the capacitors reach a preset value when the semiconductor 
switching devices Q.sub.1 -Q.sub.N are turned on. The comparison means 
compares the counted times with a threshold value. 
FIG. 2 shows an example of a circuit configuration for realizing an 
abnormality control function by the first method described above. FIG. 3 
shows an example of another circuit configuration for realizing an 
abnormality control function by the third method described above. 
In FIG. 2, a semiconductor switching device Q.sub.11 is a power transistor 
connected across the terminals of a capacitor C and acts to bypass the 
charging current. A heat-sensitive resistor is used as either resistor 
R.sub.11 or R.sub.12. These resistors R.sub.11 and R.sub.12 are connected 
in series between the terminals of the capacitor C and thermally coupled 
to the semiconductor switching device Q.sub.11. Where the resistor 
R.sub.11 is a heat-sensitive resistor, a device having a positive 
temperature coefficient, i.e., the resistance increases if the temperature 
rises excessively, is used. Where the resistor R.sub.12 is a 
heat-sensitive resistor, a device having a negative temperature 
coefficient, i.e., the resistance decreases if the temperature rises 
excessively, is employed. A semiconductor control device Q.sub.12 is a 
control transistor having a control input connected to the junction of the 
resistors R.sub.11 and R.sub.12 connected in series. This control device 
Q.sub.12 produces an output signal to control the conduction of the 
semiconductor switching device Q.sub.11. 
The operation of this circuit is as follows. During charging, if the 
capacitor C is charged to its preset full charge voltage, the 
semiconductor control device Q.sub.12 is biased into conduction. Then, a 
bypass current begins to flow into the semiconductor switching device 
Q.sub.11. Subsequently, excess current is bypassed while the voltage 
developed across the terminals of the capacitor C is maintained at the 
preset value. Every capacitor is charged close to the full charge voltage. 
However, if the temperature of the semiconductor switching device Q.sub.11 
rises excessively, the resistance of the resistor R.sub.11 or R.sub.12 
that is a heat-sensitive resistor varies greatly, causing the 
semiconductor device Q.sub.12 or Q.sub.11 to conduct into a saturated 
state. This lowers the terminal voltage of the capacitor C to less than 1 
V. 
FIGS. 4(a) and 4(b) show modifications of the configuration of FIG. 2. In 
FIG. 4(a), either resistor R.sub.11 or R.sub.12 is a heat-sensitive 
resistor in the same way as in FIG. 2. A transistor Q.sub.11 has a base to 
which a charging control signal is directly supplied to turn this 
transistor on and off. As the temperature of the transistor Q.sub.11 
rises, the transistor Q.sub.12 turns on. If the capacitor is charged 
abnormally, this transistor Q.sub.12 turns on the transistor Q.sub.11. 
In FIG. 4(b), resistors R.sub.1 l and R.sub.12 are not heat-sensitive 
resistors but are normal fixed resistors. A charging 
abnormality-indicating signal from other charging abnormality detection 
means is supplied to the junction of the resistors R.sub.11 and R.sub.12 
connected in series. A transistor Q.sub.11 has a base to which a charging 
control signal is directly supplied to turn on the transistor Q.sub.11. If 
the capacitor is charged abnormally, the transistor Q.sub.11 is turned on 
by a transistor Q.sub.21, which is turned on according to a charging 
abnormality signal from other charging abnormality detection means. 
FIG. 4(c) shows a modification of the configuration shown in FIG. 4(b). In 
FIG. 4(c), an OR logic B.sub.1 having input terminals 4, 5, and 6 is 
connected to the junction of resistors R.sub.1 and R.sub.2 connected in 
series. The state of each charged capacitor is detected and charging 
abnormality-indicating signals are supplied to the input terminals 4, 5, 
and 6, respectively, by the three methods described above, for example. 
Any capacitor at fault can be shorted out by any abnormality-indicating 
signal. This can enhance the safety. Terminals 4, 5, and 6 provide a 
negative logic gate. When any one of the signals supplied to these 
terminals 4, 5, and 6 goes low, transistors Q.sub.12 and Q.sub.11 are 
turned on. In consequence, a capacitor C.sub.1 is shorted out. 
Referring to FIG. 3, a monitor control circuit 11 compares the voltage 
developed across a capacitor C with a preset voltage V.sub.ref, and 
controls a semiconductor control device Q according to the terminal 
voltage of the capacitor C. In the circuit of FIG. 3, a signal indicating 
the start of charging is received as a charging signal from a charger. The 
time elapsing from the start of charging is measured. This circuit 
produces a signal to turn on the semiconductor control device Q provided 
that the terminal voltage of the capacitor C reaches the preset voltage 
V.sub.ref within a given time from the start of charging. 
It is to be noted that the invention is not limited to the foregoing 
embodiments and that various changes and modifications are possible. For 
instance, in some of the embodiments described above, the temperatures of 
the bypassing transistors for the parallel monitors are detected, and the 
transistors are automatically kept in conduction. In another embodiment, 
the voltage developed across the terminals of each capacitor is detected 
after the start of charging to automatically maintain the bypassing 
transistors for parallel monitors in conduction. It is also possible to 
place switching means in parallel with capacitors apart from the parallel 
monitors, the switching means being capable of shorting out these 
capacitors. Obviously, the switching means are not limited to 
semiconductor control devices. Mechanical switches having contacts may 
also be utilized. 
FIGS. 5 and 6 show examples of mounting the means for shorting out 
capacitors, apart from the means for bypassing parallel monitors. In FIGS. 
5 and 6, parallel monitor circuits (not shown) are connected in parallel 
with a capacitor C.sub.1, apart from parallel monitor-bypassing means. 
In FIG. 5, a shorting means Q.sub.3 is a thyristor. If a signal indicating 
abnormality is fed from any one of terminals 4, 5, and 6 through an OR 
gate B.sub.1 to the gate of the thyristor, this thyristor is turned on, 
shorting out the capacitor. Once turned on, the thyristor is kept on until 
the current flow ceases. Hence, the circuitry for providing control and 
maintaining the present state is simplified. If the state of each charged 
capacitor is detected and charging abnormality-indicating signals are 
supplied to the input terminals 4, 5, and 6, respectively, by the three 
methods described above, and if any capacitor at fault can be shorted out 
by any abnormality-indicating signal, the safety can be enhanced. 
FIG. 6 shows an example of using a device S.sub.1 having a mechanical 
contact, such as a switch or relay to short out a capacitor C1. The device 
S.sub.1 is turned on by an abnormality-indicating signal passed through an 
OR gate B.sub.1. In this case, it is necessary to hold the device S.sub.1 
in ON state and so a self-holding type relay or latching reed relay that 
needs limited holding current is used. 
Preferably, the means for shorting out any capacitors at fault are kept ON 
if charging is complete and the temperature drops after the shorting means 
are once turned ON. Such characteristics can be quite easily realized 
where mechanical switches are used. Where semiconductor control devices 
are used, these characteristics can be accomplished by setting the 
hysteresis loop of the ON operation wide or making other contrivances. 
In the novel power supply for storing electrical energy in capacitors, if 
any one of the capacitors connected in series is at fault, these defective 
capacitors are shorted out. Therefore, the capacitors not at fault can 
take over the charging and discharging operation without change. As the 
defective capacitors are shorted out in this way, the output voltage from 
the capacitor block may decrease, but this decrease can be circumvented by 
designing the power supply to the following tolerances. 
It is assumed that plural capacitors, each having a rated voltage of 3 V, 
are connected in series to produce an output voltage of 3,000 V. For 
example, 1020 capacitors are connected in series to form a capacitor 
block. The power supply is started to be operated with a charging voltage 
slightly less than 3 V for each capacitor. As time passes, defective 
capacitors occur. These defective capacitors are successively shorted out. 
Correspondingly, the charging voltage for each capacitor is successively 
increased. In this way, the output voltage from the capacitor block can be 
always maintained at 3,000 V. When 20 capacitors are at fault and shorted 
out, each capacitor is charged to the rated voltage of 3 V. This is the 
maximum number of defective capacitors allowable. 
In the above-mentioned embodiments, it is preferable to connect a current 
limiting resistor in series to shorting means for protecting the shorting 
means from destruction caused by a large shorting current. 
As described in detail thus far, the present invention makes it possible to 
short out defective capacitors. Therefore, the power supply can be 
operated for a long time without repair or exchange. Especially, where the 
invention is applied to a large-scale electric power storage system, the 
reliability can be enhanced effectively. Furthermore, the maintenance can 
be effectively facilitated. 
Having thus described my invention with the detail and particularity 
required by the Patent Laws, what is desired protected by Letters Patent 
is set forth in the following claims.