Transient response optimization for charge-pump-based two-stage power converter

A two-stage power converter includes a dual-level driver to control a current conducted by a switch transistor in a charge pump to control the charging of a flying capacitor in the charge pump.

TECHNICAL FIELD

This application relates to power converters, and more particularly to a two-stage converter in which one stage is a charge pump and a remaining stage is a DC-DC switching power converter

BACKGROUND

Wireless charging modes have been developed for the charging of portable devices in which the portable device includes a coil for receiving or transmitting power wirelessly to a coil in an external device. Due to the less-than-ideal coupling between such coils, the portable device requires a relatively high-power supply voltage such as 15 V to energize its coil when transmitting power to another device. But the battery voltage of a mobile device is typically substantially lower voltage such as 4 V. A mobile device thus needs a power converter to boost the battery voltage to the elevated power supply voltage necessary for wireless power transmission.

One choice for such power conversion is a two-stage power converter in which a boost converter boosts the battery voltage to an intermediate voltage that is then doubled by a flying-capacitor-based charge pump. The resulting two-stage power converter has advantageous efficiency and regulation. But during certain modes of operation such as startup and shutdown, the charge pump is not switched but instead has its input shorted to its output such that the charge pump is bypassed. This mode of operation is denoted herein as a bypass mode of operation. During the bypass mode of operation, it is only the boost converter that is driving the output voltage for the two-stage converter. There will thus be a first transition from the bypass mode to a normal mode of operation in which charge pump is active. Similarly, there is a second transition from the normal mode of operation to the bypass mode of operation. In both transitions, the output voltage may have significant overshoot and undershoot of the desired regulated value.

Accordingly, there is a need in the art for charge-pump-based two-stage converters having improved bypass mode transitions.

SUMMARY

A two-stage power converter is disclosed that includes a DC-DC switching power converter input stage (e.g., a boost converter) and a flying-capacitor-based charge pump output stage. In alternative embodiments, the arrangement may be reversed such that the flying-capacitor-based charge pump functions as the input stage and the DC-DC switching power converter functions as the output stage.

The switching power converter stage includes a controller for modulating the switching of the switching power converter to regulate an output voltage for the two-stage power converter. In contrast, the switching of the charge pump stage is open loop with respect to the output voltage. During normal operation, both stages cycle their switch transistors to assist in the power conversion. But in a bypass mode of operation, the charge pump is static such that only the switching power converter cycles its switch transistors to support the output voltage. To assist in the regulation of the output voltage during a transition from bypass mode to normal operation, a switch transistor in the charge pump is controlled to conduct a controlled amount of current to limit the charging of the flying capacitor voltage. For example, in a field-effect transistor (FET) embodiment, the switch transistor conducts the controlled amount of current in the saturation mode. During normal operation, the switch transistors in the charge pump conduct in the triode mode. The resulting control of the flying capacitor voltage improves the regulation of the output voltage during the transitions between the bypass mode and regular operation.

These advantageous features may be better appreciated through a consideration of the detailed description below.

DETAILED DESCRIPTION

A two-stage charge-pump-based power converter is disclosed having improved output voltage regulation during bypass mode transitions. The following discussion is directed to an embodiment in which the DC-DC switching power converter stage is a boost converter. However, it will be appreciated that other types of DC-DC switching power converters such as a buck converter may be readily substituted for the boost converter. The charge pump stage includes a flying capacitor. The following discussion will assume that the flying capacitor is driven by four field-effect switch transistors, but it will be appreciated that additional transistor switches may be utilized. As known in the charge-pump arts, the switch transistors are cycled so that the flying capacitor is alternatively charged and discharged. During normal operation, the switch transistors are driven to be fully-on in a triode mode of conduction. But during a transition from bypass mode to regulator operation, one of the switch transistors is controlled to conduct in a saturation mode instead of the triode mode. The current through the saturation-mode switch transistor is thus controlled to limit the overshoot and undershoot of the output voltage during the bypass mode transition. The same current control can be applied during a transition from normal operation to the bypass mode.

The following discussion will be directed to embodiments in which an input voltage is boosted by the boost converter stage into an intermediate voltage that serves as an input voltage to the charge pump. A controller controls the switching of the boost converter stage to regulate an output voltage from the charge pump. In contrast to the boost converter, the cycling of the switch transistors in the charge pump during normal operation is open loop. In other words, the on-time or period of the cycling for the charge pump switch transistors is not affected by the output voltage. This open-loop timing for the cycling of the switch transistors continues during the transition but the current is controlled for the saturation-mode operation of one of the switch transistors to limit the overshoot and undershoot of the output voltage. Although the following discussion is directed to embodiments in which the boost converter receives an input voltage, the inventive control discussed herein is readily applied to embodiments in which the charge pump receives the input voltage and steps it down to an intermediate voltage that is then further reduced by a buck converter.

An example two-stage power converter100is shown inFIG. 1. A boost converter105converts an input voltage V1into an intermediate voltage V2using an inductor L, an NMOS high-side switch transistor N5, and an NMOS low-side switch transistor N6. Depending upon an output voltage V3, a controller115regulates the switching of switch transistors N5and N6through a high-side (HS) driver and a low-side (LS) driver. Boost converter105also includes an output capacitor C2for supporting the intermediate voltage V2. Depending upon the output voltage V3, controller115may adjust a pulse-width modulation (PWM) or a pulse frequency modulation (PFM) of switch transistors N5and N6as known in the DC-DC switching power converter arts.

A charge pump110converts the intermediate voltage V2into the output voltage V3. Charge pump110includes a first NMOS switch transistor N1, a second NMOS switch transistor N2, a third NMOS switch transistor N3, and a fourth NMOS switch transistor N4all arranged in series. A flying capacitor CF connects between a drain of switch transistor N4to a drain of switch transistor N2. The intermediate voltage V2is received at the drain of switch transistor N3(as well as the source of switch transistor N2). During normal operation, the switch transistors are driven in a fifty percent duty cycle. In a first switching phase ϕ1, switch transistors N1and N3are closed whereas switch transistors N4and N2are open. During this phase ϕ1, the flying capacitor CF discharges to drive the output voltage V3. A second switching phase ϕ2is the complement of phase ϕ1such that switch transistors N1and N3are open whereas switch transistors N2and N4are closed. During this phase ϕ2, the flying capacitor CF is charged by the intermediate voltage V2. In normal operation, the 50:50 alternation between the switching phases drives the output voltage V3to be twice the intermediate voltage V2.

In normal operation, the switched-on switched transistors have their gate voltage driven such that the conduction occurs in the triode region of operation. For example, during the switching phase ϕ1, a driver120drives the gate voltage of switch transistor N1so that switch transistor N1is fully on in the triode mode (its least resistive conductive state). Similarly, during the switching phase ϕ2, a driver125drives the gate voltage of switch transistor N2so that switch transistor N2is fully on in the triode mode. During normal operation, the same drive occurs for switch transistor N4as controlled by a driver130. But during bypass transition mode for switch phase ϕ2, driver130does not drive switch transistor N4fully on in the triode mode but instead forces switch transistor N4to conduct in the saturation mode so that its current is controlled. Driver130may thus be designated as a dual-level driver since it will charge the gate voltage of switch transistor N4differently depending upon whether triode mode or saturation mode operation is desired. It is during switch phase ϕ2in which the flying capacitor CF is soft charged by dual-level driver130. In contrast, a conventional transition from bypass mode to regular operation produces a rapid, uncontrolled charging of the flying capacitor that causes a substantial perturbation of the output voltage V3. In contrast, the soft charging control of switch transistor N4inhibits this perturbation so that the output voltage V3is more tightly regulated during a transition from bypass mode to regular operation.

It will be appreciated that the soft-charge technique or control disclosed herein could alternatively be applied to switch transistor N2. During the transition from bypass mode to regular operation, the control of the soft charging of the flying capacitor may be conducted in an open-loop fashion. For example, driver130may drive switch transistor N4to mirror the current conducted by a current source. As the current source current is increased, so would the corresponding current conducted during switch phase ϕ2by switch transistor N4such that the flying capacitor CF would be charged in a controlled fashion. Alternatively, a quasi-closed-loop control may be implemented by driver130so that switch transistor N4conducts a current proportional to either the load current (or the inductor current) and/or the output voltage V3. In this fashion, as the output voltage and/or load current increases, the flying capacitor charging is increased accordingly. Alternatively, a closed-loop control may be implemented by driver130so that a feedback loop controls the current through switch transistor N4responsive to the flying capacitor voltage. In this fashion, the flying capacitor voltage is directly regulated and can be controlled to increase in a desired fashion.

The following discussion concerns the transition from bypass mode to regular operation. Analogous current control may be implemented during the transition from regular operation to the bypass mode. In addition, the following discussion will be directed to embodiments in which the flying capacitor is re-purposed during bypass mode so that it is in parallel with capacitors C2and C3. Such an arrangement advantageously increases the output capacitance for boost converter105during the bypass mode. However, it will be appreciated that the flying capacitor can instead simply float during the bypass mode.

FIG. 2illustrates some waveforms for the input voltage V1, the intermediate voltage V2, the output voltage V3, and the flying capacitor voltage during operation of two-stage converter100. During an initial phase of operation designated as region3, boost converter105begins boosting the output voltage V3from its starting state of being equal to the input voltage V1. Operation begins in bypass mode so that charge pump110is not boosting output voltage V3with respect to intermediate voltage V2. In this embodiment, the input voltage is approximately 4V. Depending upon the control of the low-side and high-side switch transistors N5and N6, the output voltage V3may be boosted solely by boost converter105to the regulation limits for boost converter105. For example, during a subsequent phase of operation designated as region4, the output voltage V3is maintained constant at 5 V. The output voltage V3is then increased linearly during another phase of operation designated as region5until it reaches 10 V. The output voltage V3is then maintained constant at 10 V during a phase of operation designated as region6.

Operation in regions3through6all occurs in bypass mode. During bypass mode, the switch configuration is as shown inFIG. 3. Switch transistors N1and N2are maintained fully on by their respective drivers120and125. Switch transistor N3is not shown for illustration clarity since it is maintained off. Dual-level driver130maintains switch transistor N4fully on. Flying capacitor CF1is thus arranged in parallel with capacitors C2and C3with respect to ground and an output node for the output voltage V3. Controller115is not shown for illustration clarity, but it would control the high-side (HS) and low-side drivers so that boost converter operation would drive the output voltage to the desired level (assuming that this desired level is within the capabilities of boost converter105).

But boost converter105alone can only drive the output voltage V3to10V in this example. To obtain greater output voltage levels requires regular operation in which charge pump110increase the intermediate voltage V2by a factor of two. Referring again toFIG. 2, the transition to regular operation begins in a phase of operation designated as region7. During this phase, the flying capacitor voltage drops from 10 V to some discharged state so that charge pump105may begin operation without substantially perturbing the output voltage V3. The resulting states for the transistors is shown inFIG. 4. To discharge the flying capacitor CF1; switch transistor N4is switched off (for illustration clarity, transistor N4is thus not shown inFIG. 4). Switch transistor N3is maintained off. Switch transistors N1and N2are maintained on as also shown inFIG. 3so that boost converter105can drive the output voltage V3in the bypass mode. To discharge the flying capacitor voltage, a transistor such as a PMOS transistor P1that is coupled in parallel with the flying capacitor CF1is switched on. Depending upon the duration of the region7operation, the flying capacitor voltage will discharge to ground. However, in other embodiments, it may instead be discharged to a some relatively-low voltage such as 0.5 V.

With the flying capacitor voltage discharged, charge pump110may commence operation during which the flying capacitor voltage is soft charged as controlled by dual-level driver130. Referring again toFIG. 2, the soft-charge phase is designated as region8. During this phase, the flying capacitor voltage rises from its discharged state to one-half of the output voltage V3, which in this embodiment is 10 V for region8operation. The flying capacitor voltage will thus rise to 5 V. It will be appreciated, however, that these voltage levels are arbitrary and can be altered as desired in alternative embodiments. Charge pump110is active during the soft-charge phase so that switch transistors N1and N3are on during switch phase ϕ1whereas switch transistors N2and N4are on during switch phase ϕ2. However, as noted earlier, dual-driver130does not drive switch transistor N4fully on into the triode mode of operation during the soft-charge phase. Instead, dual-driver130controls switch transistor N4during the phase ϕ2to only conduct a controlled amount of current in saturation mode.

As noted earlier, this control of the current conducted by switch transistor N4may be performed in an open-loop fashion or in a closed-loop fashion. An open-loop embodiment for dual-driver130is shown inFIG. 5. A current control circuit500drives a current Icontrol into the drain and gate of a diode-connected NMOS transistor M1having a source connected to ground. Depending upon the current Icontrol, transistor M1will develop a certain gate-to-source voltage Vgs. In a classic current mirror configuration, the gate of transistor M1could simply be tied to the gate of switch transistor N4so that current control circuit500could control the current conducted during the soft-charge phase. But switch transistor N4must also be driven by a conventional driver505during normal operation so current control circuit500replicates the gate voltage of transistor M1onto an output node A that is coupled to the gate of switch transistor N4. Since transistor M1and switch transistor N4will then have the same (or approximately the same) gate-to-source voltage, switch transistor N4will mirror the current Icontrol depending upon the relative sizes of transistor M1and switch transistor N4. If these transistors are matched, the current scaling is 1:1 whereas it would vary if the size ratio is varied.

As noted earlier, the open-loop control of the current conducted by switch transistor M4during the soft-charge phase may be proportional to the output current Iout (note that this proportionality may be implemented through a proportionality to the average current through inductor L in some embodiments). Current control circuit500may thus generate the current Icontrol responsive to the output current Iout. The relationship between Icontrol and the output current Iout may be linear or may be non-linear. Similarly, current control500may generate the output current responsive to the output voltage V3in either a linear or non-linear fashion. To provide additional assurance that the flying capacitor voltage will charge at a sufficiently fast yet controlled rate, current control circuit500may also generate the current Icontrol responsive to a current I1from a current source510. The control by current control circuit500may be to any one, two, or all three of these factors Iout, V3, and I1.

An embodiment in which current control circuit500responds to all three factors is shown inFIG. 6A. An NMOS transistor M2conducts a current into a resistor R1responsive to a voltage that is a function of the output current Iout. The current conducted by transistor M2will thus be a function of the output current Iout. Transistor M2is in series with a diode-connected PMOS transistor P2so transistor P2will conduct the same current. Transistor P2is in a current mirror configuration with a PMOS transistor P4. A gate voltage of transistor P4is selectively charged high to the power supply voltage VDD through the action of a PMOS transistor P3as controlled by a skip signal. Transistor P4is thus off if the skip signal is asserted. But during normal operation and the bypass mode of operation, the skip signal is grounded so that transistor P3is off. Transistor P4will thus conduct a current that is a function of the output current Iout during normal operation.

The output voltage V3couples through a voltage divider formed by a pair of resistors R2and R3to a non-inverting input of a differential amplifier600that drives a gate of an NMOS transistor M3having a source tied to ground through a resistor R4. The source of transistor M3connects to the negative input of differential amplifier600. Feedback through differential amplifier600will thus keep the source voltage for transistor M3equal to the divided version of the output voltage V3as divided through the voltage divider. Transistor M3will thus conduct an output-voltage-related current that is a function of the output voltage V3. The drain of transistor M3connects to a drain and gate of a diode-connected PMOS transistor P5that is in a current mirror configuration with a PMOS transistor P6. Transistor P6will thus conduct a mirrored version of the output-voltage-related current conducted by transistors M3and P5.

The drains of transistors P4and P6are connected to the gate and drain of a diode-connected NMOS transistor M5. Transistor M5will thus conduct a combined current that is a sum of the output-current-related current conducted by transistor P4and the output-voltage-related current conducted by transistor P6. The drain of transistor M5couples to ground through a capacitor Cramp. As transistor M5conducts during the soft-charge phase, a source voltage for transistor M5will thus increase as the capacitor Cramp is charged. Prior to the soft-charge phase, capacitor Cramp is discharged through the action of an NMOS transistor M4as controlled by a signal SS Start.

Transistor M5has its gate connected to the gate of an NMOS transistor M6having its source connected to ground. If the source of transistor M5were grounded, transistors M5and M6would form a conventional current mirror. But due to the capacitor Cramp, the gate voltage for transistor M5will increase during the soft-charge phase as capacitor Cramp charges. This increase in the gate voltage for transistor M5is replicated by an increase in the gate voltage for transistor M6. The current through transistor M6will thus equal a non-linear function (e.g., approximately a square) of the combined current through transistor M5. This non-linearity is helpful in increasing the rate of the charging of the flying capacitor voltage in a controlled fashion. However, it will be appreciated that a linear current mirror relationship may be used in alternative embodiments.

Transistor M6is in series with a diode-connected PMOS transistor P7that is in a current mirror configuration with a PMOS transistor P8. Transistor P8will thus conduct a mirrored version of the nonlinearly-increased combined current conducted by transistor M6. Transistor P8couples to ground through a diode-connected NMOS transistor M7and diode-connected transistor M1. Current source510also drives the gate and drain of transistor M7. Transistor M1will thus generate a gate-to-source voltage Vgs that is function of a sum of the nonlinearly-increased combined current conducted by transistor M6and the current I1conducted by current source510. The gate-to-source voltage for transistor M1is thus a function of all three factors discussed earlier: the output voltage V3, the output current Iout, and an additional current IL One of ordinary skill will readily appreciate that current control circuit500may be varied to use just one or two of these factors in alternative embodiments.

The gate voltage for transistor M7will be a threshold voltage above the gate-to-source voltage Vgs for transistor M1. The gate of transistor M7connects to an NMOS transistor M8having its drain tied to the power supply node for the power supply voltage VDD. Transistor M8is thus in a source-follower configuration such that its source voltage will follow its gate voltage minus the threshold voltage drop for transistor M8. The net effect of transistors M7and M8is thus to replicate the gate voltage (which in this case is the gate-to-source voltage Vgs) of transistor M1at a node A at the source of transistor M8.

The remainder of dual-level driver130is shown inFIG. 6B. Node A connects to the source of a PMOS transistor P9that has its drain connected to a source of a PMOS transistor P10. Conventional driver chain505drives the gate of transistor P10. During switch phase ϕ2, a gate on command is asserted to driver chain500. Transistor P10is thus on during switch phase ϕ2. The drain of transistor P10connects to ground through an NMOS transistor M9that also has its gate driven by the driver chain505. Transistor M9will thus be off during switch phase ϕ2. The drains of transistors M9and P10connect to the gate of switch transistor N4.

Driver chain505also drives the gate of a PMOS transistor P12that has its drain connected to the gate of switch transistor N4. Transistor P12will thus be switched on during phase ϕ2. The source of transistor P12connects to the power supply node through a PMOS transistor P11that is controlled by an inverted version of the SS done signal as inverted by an inverter605. The SS done signal is low during the soft-charge phase and asserted high to end this phase. Transistor P11will thus be off during the switch phase ϕ2. Since transistors P9and P10are on and transistor M9is off during switch phase ϕ2, the replicated gate-to-source voltage Vgs for transistor M1couples through node A to drive the gate of switch transistor N4. The flying capacitor CF will thus charge during the soft-charge mode responsive to current controlled by current control circuit500.

When the SS done signal is asserted at the end of the soft-charge phase, transistor P9is switched off to isolate node A from affecting the gate voltage for switch transistor N4. Transistor P11is switched on so that transistors P12and M9form a final inverter for driver chain505during normal operation. Switch transistor N4can thus be seamlessly controlled in either a conventional fashion during normal operation or as discussed herein for the soft-charge mode.

In an alternative embodiment, dual-driver130may implement feedback in a closed-loop fashion to control the flying capacitor voltage. An example closed-loop current control circuit500is shown inFIG. 7. A difference amplifier705outputs a divided version of the flying capacitor voltage (VCF_div5) responsive to the difference between a positive terminal voltage CP1for the flying capacitor CF1and its negative terminal voltage CM1. A transconductance amplifier710either sources or draws an output current responsive to a difference between the divided capacitor voltage and a reference voltage such as an analog voltage VDAC from a digital-to-analog converter (DAC)715. DAC715converts a digital control signal (not illustrated) that is varied so as to increase the analog voltage VDAC over the soft-charge phase. The output current from transconductance amplifier710drives the gate and drain of diode-connected transistor M1. Analogously as discussed with regard toFIG. 6A, current source510also drives a minimum current Imin into the data and drain of transistor M1. Transistor M1will thus develop a gate-to-source voltage Vgs that is a function of the difference between the desired flying capacitor voltage as represented by the analog voltage VDAC and the divided flying capacitor voltage. A transconductance amplifier720drives a current into a gate of a PMOS transistor P13responsive to a difference between the gate-to-source voltage Vgs for transistor M1and a drain voltage for transistor P13. The drain of transistor P13connects to node A that drives the remainder of dual-driver130as discussed with regard toFIG. 6B. Due to the feedback though transconductance amplifier720, the drain voltage for transistor P13(the voltage of node A) will equal the drain-to-source voltage Vgs for transistor M1. A capacitor C1may be used to support the node A voltage.

Referring again toFIG. 2, the soft-charge phase in region8ends with the flying capacitor voltage at one-half the output voltage V3, which in this example is 10 V so that the flying capacitor voltage rises to 5 V. With the soft-charge phase completed, the control of the switching in boost converter105can drive the output voltage to a desired value. InFIG. 2, the output voltage stays at 10 V across a region9and this increases linearly in a region10to reach a maximum of 15 V. The output voltage stays at 15 V in a region11. Note that the switching in charge pump110does not vary from region8through region11. It is just the pulse-width-modulation (or pulse-frequency modulation) of the switching in boost converter105that will be varied to produce the desired output voltage V3. The intermediate voltage V2is one-half of the output voltage V3during normal operation since charge pump110functions to double the intermediate voltage V2during its normal operation.

The control of the switching in boost converter105may also be used to drop the output voltage as beginning in a region12. In this example, the output voltage V3is dropped to 10 V. With the output voltage dropped sufficiently, the flying Capacitor voltage may be discharged as shown for a region13. It will be appreciated that the charge pump110may be duplicated in an interleaved fashion such that one flying capacitor drives the output voltage in switch phase ϕ1while the remaining flying capacitor is charged in switch phase ϕ2. To allow the flying capacitor voltage to discharge efficiently, switch phase ϕ2is altered during operation in region13so that the flying capacitor in switch phase ϕ2floats rather than being charged. The energy in the flying capacitor is thus not restored such that it continues to drop with each successive switch phase ϕ1until the energy is sufficiently depleted. As discussed previously, this discharge may go to ground or to some relatively small voltage such as 0.5 V.

Operation in region13ends once the flying capacitor voltage is depleted sufficiently. The transition to bypass mode may then occur starting in a region14. In one embodiment, the flying capacitor can simply float once the bypass mode begins following the discharge of the flying capacitor voltage. But as discussed earlier, it is advantageous to repurpose the flying capacitor to bolster the output capacitance for boost converter105. The flying capacitor cannot simply be placed in parallel with capacitors C2and C3as bypass operation begins because such a reconfiguration of the flying capacitor will perturb the output voltage V3undesirably. The flying capacitor voltage may thus be soft charged during operation in region14until the flying capacitor voltage is charged to the output voltage V3. This soft charging may occur using dual-driver130as discussed above in either an open-loop or a closed-loop embodiment. Alternatively, a relatively resistive transistor switch may be used to control the soft charging of the flying capacitor. An example switching configuration having such a resistive switch is shown inFIG. 8. Switch transistors N1and N2are on whereas switch transistors N3and N4are off A relatively-small NMOS transistor M10that couples between ground and the negative terminal for the flying capacitor CF1is switched fully-on so that the flying capacitor voltage may begin to be charged by the output voltage V3. But due to the relatively small size of transistor M10, the charging of the flying capacitor voltage is sufficiently controlled so that no undesirable perturbation of the output voltage V3is induced.

With the flying capacitor voltage charged to the output voltage V3, operation in a region15may begin. This bypass operation is as discussed with regard to regions3through6. The control of the switching in boost converter105may then be adjusted to further lower the output voltage as shown in region16.

Although the soft-charge discussed herein advantageously inhibits the perturbation of the output voltage V3, some minor disturbances may remain. Controller115may thus be configured to implement a transient reaction to address voltage undershoots and overshoots. The following discussion will focus on the reaction to voltage undershoots but it will be appreciated that a similar technique may be used to address voltage overshoots. An example controller115configured to implement a transient reaction to voltage undershoots is shown inFIG. 9. To obtain feedback on the output voltage V3, a voltage divider formed by a pair of resistors R1and R2divides the intermediate voltage V2. Alternatively, the output voltage V3itself may be divided but it is equivalent to divide the intermediate voltage V2since it and the output voltage V3are either equal (during the bypass mode) or have a 1:2 relationship (during normal operation). An undervoltage comparator905compares an undervoltage reference value (UV Vef) to the divided voltage. Should the divided voltage drop below the undervoltage reference value, comparator905triggers a one-shot circuit910.

As known in the one-shot circuit arts, one-shot circuit910pulses an output signal for a relatively short duration in response to the triggering by comparator905. The duration of the one-shot period may be used to alter the pulse-width modulation of the high and low-side switch transistors N5and N6in boost converter105. After the one-shot period is ended, controller115returns to its default modulation. There are several ways to boost the gain of controller115. For example, during default operation, controller115senses the intermediate voltage V2using a voltage divider formed by resistors R3, R4, and R5to obtain a feedback voltage VFB. A switch S1couples across resistor R5. During the one-shot period, switch S1may be closed to short out resistor R5and reduce the voltage division applied by the voltage divider. This reduces the feedback voltage VFB.

Controller115includes an error amplifier915that amplifies a difference between a reference voltage Vref and the feedback voltage VFB. The temporary reduction in the feedback voltage VFB thus temporarily increases an error voltage (VEA) produced by error amplifier915. Error amplifier915is frequency compensated by a loop filter920. A PWM comparator925compares the error voltage to a ramp signal (RAMP) to reset a set-reset (SR) latch930. A clock signal (CLOCK) that determines the period for the pulse-width modulation sets the SR latch. The Q output of SR latch930is processed by a gate driver935so that the high-side and low-side switch transistors N5and N6may be cycled accordingly. The temporary boosting of the error voltage thus provides a temporary boost to the duty cycle for the pulse-width modulation of the cycling of the high-side and low-side switch transistors N5and N6.

Alternatively (or in combination with the voltage division change), a digital word (not illustrated) that is converted by a digital-to-analog converter (DAC)940may be temporarily changed to boost the reference voltage VREF. This boosting of the reference voltage VREF increases the duty cycle for the pulse-width modulation to assist the recovery of the output voltage V3from the undervoltage condition.

As another alternative (or in combination with one or both of the voltage division and reference voltage changes), the frequency of the clock signal may be increased. Such a change in frequency increases the switching frequency of the high-side and low-side switch transistors N5and N6, which in turn allows the inductor L1to provide more current to the load while the boost is operating at the maximum duty cycle. Note that energy delivery to the load from boost converter105occurs only while the inductor L1demagnetizes. During maximum duty cycle operation, the demagnetizing interval is relatively short but has a minimum off-time requirement. The increase in switching frequency thus causes more energy delivery to the load since each switching cycle has a mandatory interval of demagnetization. In lieu of increasing the switching frequency, the minimum off-time for the switching of switch transistors N5and N6could be temporarily decreased.

Those of some skill in this art will by now appreciate that many modifications, substitutions and variations can be made in and to the materials, apparatus, configurations and methods of use of the devices of the present disclosure without departing from the scope thereof. In light of this, the scope of the present disclosure should not be limited to that of the particular embodiments illustrated and described herein, as they are merely by way of some examples thereof, but rather, should be fully commensurate with that of the claims appended hereafter and their functional equivalents.