BIASING AND READOUT METHODS FOR HIGH-SPEED RESISTIVE GATE SENSOR

Photon or electron detectors may include polycrystalline silicon resistive gates with voltage gradients applied to reduce lag and improve operating speeds. The polycrystalline silicon resistive gates may be doped polycrystalline silicon which is heavily doped with donor atoms or acceptor atoms and ion-implanted with an electrically inactive species. The electrically inactive species may be implanted in a pattern to form multiple ion-implanted regions with different resistivities. The ion-implanted regions are formed in select patterns to control the resistivity of the polycrystalline silicon resistive gates and to modify the lateral electric field across the differentially-biased polycrystalline silicon resistive gate. The X-ray detectors may also include a circuit element with a current-mode differential connection to improve clock feedthrough and power dissipation characteristics.

TECHNICAL FIELD

The present disclosure generally relates to imaging microscopy, and more particularly to electron and photon detectors for high-speed scanning in electron or optical microscopy applications.

BACKGROUND

Undoped thin films (a few microns or less) of polycrystalline silicon exhibit extremely high sheet resistance, at least as high as 10{circumflex over ( )}8 to 10{circumflex over ( )}10 ohms per square, because the conduction takes place across grain boundaries. The undoped thin films of polycrystalline silicon are temperature sensitive and highly resistive. Heavily-doped polycrystalline silicon films exhibit relatively low resistivity, and are often used as gates for capacitors and transistors in image sensors. The low resistivity limits effective use of polysilicon for gates with different voltage applied at different locations on the same gate, since the current and resulting power dissipation would be high in some cases. A higher resistivity polysilicon is desired for this purpose. Fabrication of relatively more resistive polycrystalline silicon films can be achieved by employing the use of lightly doped polycrystalline silicon. In the case that a specific resistivity range is desired, tuning of the p- or n-type implant dosage may result in sporadic resistivities. Reproducible sheet resistivities are difficult to obtain in lightly doped polycrystalline silicon. In the lightly doped condition, the resistivity is highly sensitive to both the action of charge carrier traps at grain boundaries and to the grain size, which together have a complex and unpredictable dependence on numerous processing variables (e.g., doping concentration, deposition temperature, contamination, and the like). In addition, the resistivity strongly depends on the doping level (the sheet resistance decreases non-linearly with the doping level). Therefore, it would be advantageous to provide a device, system, and method that cures the shortcomings described above.

SUMMARY

A polycrystalline silicon resistive gate is described, in accordance with one or more embodiments of the present disclosure. The polycrystalline silicon resistive gate may include: heavily doped polycrystalline silicon, wherein the heavily doped polycrystalline silicon is one of an n-type semiconductor or a p-type semiconductor, wherein the heavily doped polycrystalline silicon is heavily doped with a plurality of atoms, wherein the plurality of atoms include one of donor atoms or acceptor atoms, wherein the plurality of atoms saturate a plurality of carrier traps of the heavily doped polycrystalline silicon; wherein the heavily doped polycrystalline silicon is ion-implanted with an electrically inactive species, wherein the electrically inactive species includes one of carbon or nitrogen, wherein the electrically inactive species define a first ion-implanted region and a second ion-implanted region, wherein the first ion-implanted region is implanted with a higher concentration of the electrically inactive species than the second ion-implanted region, wherein a first resistivity of the first ion-implanted region is higher than a second resistivity of the second ion-implanted region.

An X-ray detector is described, in accordance with one or more embodiments of the present disclosure. The X-ray detector may include: a gate oxide layer; and a plurality of polycrystalline silicon resistive gates, wherein the plurality of polycrystalline silicon resistive gates are formed in the gate oxide layer, wherein the plurality of polycrystalline silicon resistive gates include: heavily doped polycrystalline silicon, wherein the heavily doped polycrystalline silicon is one of an n-type semiconductor or a p-type semiconductor, wherein the heavily doped polycrystalline silicon is heavily doped with a plurality of atoms, wherein the plurality of atoms include one of donor atoms or acceptor atoms, wherein the plurality of atoms saturate a plurality of carrier traps of the heavily doped polycrystalline silicon; wherein the heavily doped polycrystalline silicon is ion-implanted with an electrically inactive species, wherein the electrically inactive species includes one of carbon or nitrogen, wherein the electrically inactive species define a first ion-implanted region and a second ion-implanted region, wherein the first ion-implanted region is implanted with a higher concentration of the electrically inactive species than the second ion-implanted region, wherein a first resistivity of the first ion-implanted region is higher than a second resistivity of the second ion-implanted region; wherein the X-ray detector is configured to generate an image data signal in response to detecting at least one X-ray photon.

A scanning electron microscope is described, in accordance with one or more embodiments of the present disclosure. The scanning electron microscope may include: an electron source configured to generate an electron beam; an electron optical system configured to focus the electron beam and scan the electron beam over a sample; and at least one X-ray detector including: a gate oxide layer; and a plurality of polycrystalline silicon resistive gates, wherein the plurality of polycrystalline silicon resistive gates are formed in the gate oxide layer, wherein the plurality of polycrystalline silicon resistive gates include: heavily doped polycrystalline silicon, wherein the heavily doped polycrystalline silicon is one of an n-type semiconductor or a p-type semiconductor, wherein the heavily doped polycrystalline silicon is heavily doped with a plurality of atoms, wherein the plurality of atoms include one of donor atoms or acceptor atoms, wherein the plurality of atoms saturate a plurality of carrier traps of the heavily doped polycrystalline silicon; wherein the heavily doped polycrystalline silicon is ion-implanted with an electrically inactive species, wherein the electrically inactive species includes one of carbon or nitrogen, wherein the electrically inactive species define a first ion-implanted region and a second ion-implanted region, wherein the first ion-implanted region is implanted with a higher concentration of the electrically inactive species than the second ion-implanted region, wherein a first resistivity of the first ion-implanted region is higher than a second resistivity of the second ion-implanted region; wherein the at least one X-ray detector is configured to generate an image data signal in response to detecting at least one X-ray photon generated from the sample resulting from exposure to the electron beam.

A method is described, in accordance with one or more embodiments of the present disclosure. The method may include: depositing a polycrystalline silicon film on a gate oxide layer; heavily doping the polycrystalline silicon film with a plurality of atoms to form a heavily doped polycrystalline silicon, wherein the heavily doped polycrystalline silicon is one of an n-type semiconductor or a p-type semiconductor, wherein the plurality of atoms include one of donor atoms or acceptor atoms, wherein the plurality of atoms saturate a plurality of carrier traps of the heavily doped polycrystalline silicon; ion-implanting the heavily doped polycrystalline silicon with an electrically inactive species, wherein the electrically inactive species includes one of carbon or nitrogen; and annealing the heavily doped polycrystalline silicon after ion-implantation to form a polycrystalline silicon resistive gate, wherein the electrically inactive species define a first ion-implanted region and a second ion-implanted region, wherein the first ion-implanted region is implanted with a higher concentration of the electrically inactive species than the second ion-implanted region, wherein a first resistivity of the first ion-implanted region is higher than a second resistivity of the second ion-implanted region.

DETAILED DESCRIPTION

Embodiments of the present disclosure are directed to X-ray detectors of a scanning electron microscope. The X-ray detectors may include polycrystalline silicon resistive gates. The polycrystalline silicon resistive gates may be doped polycrystalline silicon which is heavily doped with donor atoms or acceptor atoms and ion-implanted with an electrically inactive species. The electrically inactive species may be implanted in a pattern to form multiple ion-implanted regions with different resistivities. The ion-implanted regions are formed in select patterns to control the resistivity of the polycrystalline silicon resistive gates and to modify the lateral electric field across the differentially-biased polycrystalline silicon resistive gate. The X-ray detectors may also include a circuit element with a current-mode differential connection to improve clock feedthrough and power dissipation characteristics.

Within regions of a CCD sensor, it is desirable to optimize charge transport for high-speed operation. Multiple gates may be employed that need to be isolated and operated over time with voltage changes to move charge from one location to another. Under a constant-voltage gate, the charge transport is limited by diffusion, which can result in low performance for large gates. For this reason, many small gates are typically used for high-speed operation. A single resistive gate may also be used, with different voltages at boundary or interior locations. This configuration results in lateral electric fields in the bulk of the sensor, which allows efficient charge transport without clock operation. Use of two or more different resistivities within a single polysilicon sheet can overcome the challenges of lag and reduced charge collection efficiency that can occur with devices employing large single polysilicon gates. Fabrication of such gates along with design patterns with performance advantages are described.

For achieving high signal-to-noise ratios within each resolution element of a CCD-like sensor array, careful control of the ground potential and the reset level of the output circuit floating diffusion region is necessary. High-speed operation is typically limited by clock feedthrough and other noise contributions generated on the sensor. A source-follower architecture is often used to provide an analog output voltage proportional to charge collected at the floating diffusion region. A circuit design is provided with reduced sensitivity to these noise sources.

European Patent Number 0116702A2, titled “Method for forming polycrystalline silicon reproducible and controllable resistivity”; U.S. Patent Number 2006/0060780, titled “Apparatus and method for E-beam dark field imaging”; U.S. Patent Publication Number 2011/0073982, titled “Inspection system using back side illuminated linear sensor”; U.S. Patent Publication Number 2013/0264481, titled “Back-illuminated Sensor With Boron Layer”; U.S. Patent Publication Number 2013/0176552, titled “Interposer based imaging sensor for high-speed image acquisition and inspection systems”; U.S. Patent Publication Number 2017/0338257, titled “Anti-Reflection Layer For Back-Illuminated Sensor”; U.S. Patent Publication Number 2017/0329025, titled “Scanning Electron Microscope And Methods Of Inspecting And Reviewing Samples”; U.S. Patent Publication Number 2018/0070040, titled “Sensor with electrically controllable aperture for inspection and metrology systems”; U.S. Patent Publication Number 2019/0253652, titled “Dual-Column-Parallel CCD Sensor And Inspection Systems Using A Sensor”; U.S. Patent Publication Number 2019/0386054, titled “Back-Illuminated Sensor And A Method Of Manufacturing A Sensor”; U.S. Patent Publication Number 2021/0066035, titled “Sensor module for scanning electron microscopy applications”; U.S. Patent Publication Number 2022/0399220, titled “Segmented multi-channel, backside illuminated, solid state detector with a through-hole for detecting secondary and backscattered electrons”; are each incorporated herein by reference in the entirety.

FIG.1depicts a scanning electron microscope100(SEM), in accordance with one or more embodiments of the present disclosure. The scanning electron microscope100may be an inspection or review system configured to inspect or review a sample128. The scanning electron microscope100may review and/or inspect the sample128for defects and to reveal the material composition of the sample128and/or defects. The scanning electron microscope100may include an electron source102, an electron optical system111, a stage130, and/or a controller140.

The electron source102may be a source of electrons. The electron source102may include any electron source suitable for generating an electron beam106. The electron source102may also be referred to as an electron gun. The electron beam106may also be referred to as a primary electron beam. The electron beam106may include a beam energy and a beam current.

The electron source102may include electron emitters101, extractors103, a magnetic lens (not depicted), and the like.

The electron source102may include any number of the electron emitters101. For example, the electron source102may include a single of the electron emitters101. By way of another example, the electron source102may include multiple of the electron emitters101.

The electron emitters101may be a cathode. For example, the cathode may include a thermal field-emitting or Schottky cathode, a single-crystal tungsten cathode, a LaB6 cathode, or the like.

The extractors103may be electrodes. The extractors103may be arranged in the path of the electron beam106.

The electron optical system111may include a set of electron optics arranged in an electron-optical column. The electron optical system111may include one or more focusing optics and/or deflecting optics.

The focusing optics may focus the electron beam106onto the sample128. The electron optical system111may include any focusing optics. For example, the one or more focusing optics may include, but are not limited to, condenser lens107and objective lens110.

The condenser lens107may de-magnify the electron beam106to create a small spot on the sample128. Spot sizes of about one or a few nm may generate high-resolution images for review of the sample128. Inspection of the sample128may use larger spot sizes to scan the sample128more quickly. The electron optical system111may include any number of the condenser lens107. A single of the condenser lens107may suffice when the spot size is of order of one-hundred nm or larger, but two or more of the condenser lens107may be needed for spot sizes of tens of nm or smaller. The condenser lens107may include a magnetic lens, an electrostatic lens, both a magnetic lens and an electrostatic lens, or the like.

The objective lens110may be a final lens within the electron optical system111before the electron beam106reaches the sample128. The objective lens110may focus the electron beam106to a small spot on the sample128. The objective lens110may include a magnetic lens, an electrostatic lens, a combination of a magnetic lens and an electrostatic lens, or the like. The objective lens110may be an immersion lens. To achieve a small spot size at the sample128, the objective lens110may be placed close to the sample128, so that the sample128is immersed in the magnetic field of the objective lens110. Immersing the sample in the magnetic field may reduce aberrations in the electron spot on the sample128.

The deflection optics may be configured to scan the electron beam106over the sample128. The electron optical system111may include any deflection optics. The one or more deflection optics may include, but are not limited to, one or more deflectors (e.g., scanning coils). For example, the electron optical system111may include deflectors105and deflectors109.

The deflectors105may scan the electron beam106over an area of the sample128. The deflectors105may be placed on either side of condenser lens107as shown, or within the condenser lens107(not shown), or after the condenser lens107. The deflectors105may include electrostatic deflectors or a combination of magnetic and electrostatic deflectors.

The deflectors109may work in combination with deflectors105to scan the electron beam106over an area of the sample128.

The electron beam106may be focused and deflected by the deflectors105, the condenser lens107, the deflectors109, and the objective lens110onto the sample128positioned on the stage130. The electron source102and electron optical system111may be arranged in a single-beam configuration or in a multi-beam configuration. For example, the electron source102may generate a single of the electron beam106that is deflected and focused onto the sample128. By way of another example, the electron source102may also generate multiple of the electron beams106that are deflected and focused onto the sample128. As depicted, the electron source102and electron optical system111are depicted in the single-beam configuration, although this is not intended to be limiting.

The sample128may include sample types typically reviewed by the scanning electron microscope100. For example, the sample128may include an un-patterned semiconductor wafer, a patterned semiconductor wafer, a reticle, a photomask, or the like.

The stage130may support and position the sample128. The sample128may be placed on the stage130. The stage130may facilitate movement of different regions of sample128underneath the electron optical system111. The stage130may include an X-Y stage or an R-6 stage. The stage130may adjust the height of sample128during inspection to maintain focus.

The electron optical system111may also include a focus sensor (not shown). The focus sensor may be an optical sensor. The focus sensor may also be referred to as a height sensor. The focus sensor may be mounted on or proximate to objective lens110. The focus sensor may provide a signal to adjust the height of sample128or to adjust the focus of the objective lens110.

The X-ray detectors122may not block the electron beam106on the way to the sample128. X-ray photons may be emitted from an area of the sample128when the electron beam106is scanned by the electron optical system111over the area. The X-ray photons may be generated from the sample128resulting from exposure to the electron beam106. The X-ray photons may be detected by the X-ray detectors122that is in direct line-of sight to the region of the sample128being exposed to the electron beam106.

The X-ray detectors122may be positioned at one or more selected locations in view of the sample128. The scanning electron microscope100may include any number of the X-ray detectors122.

The X-ray detectors122may include an application specific integrated circuit. The application specific integrated circuit may be used to digitize and preprocess the X-ray signals collected by the X-ray detectors122.

The X-ray detectors122may collect X-rays photons and/or auger electrons emanating from the sample128(e.g., emanating from the sample at a very high solid angle).

The X-ray detectors122may be adjacent to the sample128. For example, the X-ray detectors122may be placed between the objective lens110and the sample128. The gap between the sample128and the objective lens110may be small, such as about 2 mm or less, and clearance may be needed, for example, for a focus or height sensor, and so it may not be practical to place the X-ray detectors122between the objective lens110and the sample128.

The electron emitters101and the sample128may include a potential difference. The landing energy of the electron beam106on the sample128may depend on the potential difference between the electron emitters101and the sample128. The landing energy may be adjusted by changing the potential of the electron emitters101. Alternatively, the landing energy on the sample128may be adjusted by changing the potential of the stage130and sample128relative to ground. The landing energy on the sample128may be adjusted to allow X-rays with the energy range of interest to be generated from different sample materials. For example, the landing energy on the sample128may be between about 1 keV and 6 keV.

The X-ray detectors122may include a select sensitivity. The sensitivity may also be referred to as gain. The sensitivity may be the number of the electron-hole pairs formed from incident X-ray photons. The gain of the X-ray detectors122may allow the energy of the X-ray photons to be estimated by measuring the number of electrons detected for each X-ray detection. Each X-ray photon may generate multiple signal electrons in the X-ray detectors122, allowing the X-ray detectors122to measure the X-ray energy.

The X-ray detectors122may convert X-rays into measurable charges entirely within the structure of the X-ray detectors122.

The X-ray detectors122may be a solid-state X-ray detector. For example, the detecting medium of the X-ray detectors122may be silicon (e.g., a p-n junction). The X-ray detectors122may each include one or more solid-state sensors. For example, the X-ray detectors122may each include one or more multipixel solid-state sensors. An entire incident X-ray-to-readout conversion may take place entirely within the X-ray detectors122.

The X-ray detectors122may be configured to generate image data signals in response to detecting one or more X-ray photons. The X-ray detectors122may be configured to generate image data signal ID in response to detecting emitted X-ray photons. The X-ray image data signal ID may be transferred to controller140from the X-ray detectors122.

The controller140may utilize the X-ray detectors122to generate images of the scanned area of the sample128. For example, the controller140may utilize the X-ray image data signal ID to generate an image of the associated scanned sample area, whereby visual inspection of a defect including an unknown material is facilitated.

The controller140may also be configured to perform additional functions, such as determining the presence of a defect and/or the type of the defect based on incident X-ray energy values indicated by the image data signals. For example, the controller140may use the X-ray image data signal ID to determine the presence of the defect in the scanned area. The defect may include the presence of material (such as a particle) that is not supposed to be present in the scanned area, the absence of material that is supposed to be in the scanned area (such as may happen with an over-etched condition), or a malformed pattern. The controller140may also determine the defect type and/or material type of the defect.

The X-ray detectors122may include a select sensitivity for generating many electron-hole pairs from a single X-ray photon. The X-ray detectors122may include various improvements to improve the sensitivity, such as, but not limited to, polycrystalline silicon resistive gates which are patterned with a profile and/or a differential amplifier, as will be described further herein.

FIG.2depicts the X-ray detector122, in accordance with one or more embodiments of the present disclosure. The X-ray detector122may be a charge-coupled device (CCD). The X-ray detector122may include a boron layer202, a substrate204, an epitaxial layer206, a gate oxide layer208, a silicon nitride gate layer210, circuit elements212, a front side metal214, a buried channel layer216, polycrystalline silicon resistive gates218, electrical connections220, and the like.

The epitaxial layer206may be formed on the front side of the substrate204. The epitaxial layer206may be disposed between the substrate204and the gate oxide layer208. The epitaxial layer206may include a select thickness. For example, the epitaxial layer206may include a thickness of between 20 and 50 μm. The epitaxial layer206may be epitaxial silicon or the like.

The substrate204and/or the epitaxial layer206may be p-type semiconductors. The substrate204and/or the epitaxial layer206may be doped with any suitable acceptor atoms, such as, but not limited to boron, aluminum, gallium, or the like. The substrate204and/or the epitaxial layer206may include select concentrations of the acceptor atoms. The substrate204may be a p+ (i.e. highly p doped) substrate. For example, the substrate204may be a layer with a higher concentration of p dopant than the epitaxial layer206. The epitaxial layer206may be a p-epitaxial layer. For example, the epitaxial layer206may be a layer with a lower concentration of p dopant than the substrate204.

The gate oxide layer208may be formed on the epitaxial layer206. The gate oxide layer208may be disposed between the epitaxial layer206and the silicon nitride gate layer210. The gate oxide layer208may include silicon dioxide or the like.

The silicon nitride gate layer210may be formed on the gate oxide layer208. The silicon nitride gate layer210may be disposed between the gate oxide layer208and the circuit elements212. The silicon nitride gate layer210may include silicon nitride.

The silicon nitride gate layer210and the gate oxide layer208may form a gate dielectric layer. Although the X-ray detector122is depicted with one of the silicon nitride gate layer210and one of the gate oxide layer208, this is not intended as a limitation of the present disclosure. The X-ray detector122may include a multi-layer gate dielectric layer formed from repeating layers of the silicon nitride gate layer210and the gate oxide layer208. Depending on the type of image sensor technology, the gate dielectric layer may include one, two, or three layers.

The circuit elements212may be formed on the silicon nitride gate layer210. The circuit elements212may be disposed between the silicon nitride gate layer210and the front side metal214. Portions of the circuit elements212may also extend through the epitaxial layer206, the gate oxide layer208, and/or the silicon nitride gate layer210. For example, portions of the circuit elements212may couple to the epitaxial layer206, the gate oxide layer208, the buried channel layer216, the polycrystalline silicon resistive gate218, the electrical connections220, and the like.

The circuit elements212may include any one or more circuitry elements suitable for driving, receiving, processing, conditioning, controlling, and/or transmitting signals in the X-ray detector122. The circuit elements212may include one or more active circuit elements and/or passive elements, such as, but not limited to, transistors, diodes, resistors, capacitors, inductors, or the like. The circuit elements212may include a sensor circuit, a signal processing circuit, a readout circuit, a timing circuit, a driver circuit, an amplification circuit, a conversion circuit, or the like. The readout circuit may readout signals from the pixels217. The conversion circuit may include an analog-to-digital converter to convert an output signal to a digital form for transmission as X-ray image data signal ID to the controller140. The various circuits are described in a simplified form for brevity, and it is understood that these circuits may include additional features and perform additional functions.

The front side metal214may be formed on the front side of the circuit elements212. The front side metal214may be a metal interconnect. The metal interconnect may include a select metal, such as, but not limited to, aluminum or copper.

The buried channel layer216may be formed in the epitaxial layer206. The top sides of the epitaxial layer206and the buried channel layer216may coincide. The buried channel layer216may abut the gate oxide layer208. The buried channel layer216may be an n-type semiconductor. The buried channel layer216may be doped with any suitable donor atom, such as, but not limited to, phosphorous, arsenic, or the like.

The X-ray photons may pass through the boron layer202to the epitaxial layer206. The epitaxial layer206may be a photoactive region of the X-ray detectors122. The epitaxial layer206may be configured to generate multiple electron-hole pairs in response to receiving the X-ray photons. In this regard, the sensitivity of the epitaxial layer206may be relatively high. The buried channel layer216may collect the electrons generated by the epitaxial layer206. The electrons may be collected and read out as the X-ray image data signal ID.

The X-ray detector122may define pixels217. For example, the epitaxial layer206and the buried channel layer216may define the pixels217. The pixels217may be arranged in one-dimensional array or a two-dimensional array.

The one-dimensional array may include rows of the pixels217. The two-dimensional array may include rows and columns of the pixels217. The buried channel layer216may be segmented into the rows and/or columns. The columns may be orthogonal to the rows. The X-ray detector122may define any number of the pixels217in the rows and/or the columns (e.g., tens, hundreds, or thousands of the pixels217in the rows and/or the columns). The rows may or may not include a matching number of the pixels217as the columns.

The polycrystalline silicon resistive gates218may be formed in the gate oxide layer208. The polycrystalline silicon resistive gates218may be separated from the epitaxial layer206and/or the buried channel layer216by the gate oxide layer208. Each of the pixels217may include one or more of the polycrystalline silicon resistive gates218.

Electrical connections220may be made to the polycrystalline silicon resistive gates218. The electrical connections220may also be referred to as bias connections. The electrical connections220may be made to one or more locations on the polycrystalline silicon resistive gates218. The electrical connections220may bias the polycrystalline silicon resistive gates218with voltages. Voltage gradients may be created in the polycrystalline silicon resistive gates218by applying voltages to the electrical connections220. The polycrystalline silicon resistive gates218may conduct charge carriers and provide a continuous voltage potential between the electrical connections220.

The potential at the surface of the epitaxial layer206may vary with location according to the voltage at the corresponding location on the polycrystalline silicon resistive gates218. The varying potential creates an electric field in the epitaxial layer206that controls where the photoelectrons collect. Because the epitaxial layer206is lightly doped, there are few free carriers and the electric fields from charges near the surface will extend throughout all, or almost all, of the epitaxial layer206.

The buried channel layer216may be configured to transfer the charge carriers generated in the electron-hole pairs to a floating diffusion (not depicted). The floating diffusion may be disposed in the buried channel layer216to facilitate receiving the charge carriers. The circuit elements212may generate an output signal OS according to a charge (voltage) collected on the floating diffusion. The measured charge (voltage) may be made proportional to the number of charge carriers captured by the floating diffusion.

FIGS.3A-3Bdepict the polycrystalline silicon resistive gate218, in accordance with one or more embodiments of the present disclosure.

The polycrystalline silicon resistive gate218may be a thin film. The polycrystalline silicon resistive gate218may be planar and include a select thickness. For example, the polycrystalline silicon resistive gate218may include a thickness of between 50 and 1000 nm. For instance, the polycrystalline silicon resistive gate218may include a thickness of about 300 nm.

The polycrystalline silicon resistive gate218may be a select shape, such as, a rectangular shape. For example, the polycrystalline silicon resistive gate218may be a square shape. The polycrystalline silicon resistive gate218may include an aspect ratio. The aspect ratio may be defined by the shape of the polycrystalline silicon resistive gate218.

The polycrystalline silicon resistive gate218may be for a large-pixel. For example, the polycrystalline silicon resistive gate218may include a width and/or length on the between 100 and 1000 μm. For instance, the polycrystalline silicon resistive gate218may be about 250 μm.

The electrical connections220may be made around the perimeter and/or the center of the polycrystalline silicon resistive gate218. For example, the electrical connections220may include a source electrical connection220aand a drain electrical connection220b. The source electrical connection220aand the drain electrical connection220bmay be made around the perimeter of and to the center of, respectively, the polycrystalline silicon resistive gate218. The polycrystalline silicon resistive gate218may experience a voltage drop from the source electrical connection220ato the drain electrical connection220b. The source electrical connection220aand the drain electrical connection220bmay be biased with a select voltage. For example, the source electrical connection220aand the drain electrical connection220bmay be biased with 5V and 0V, respectively. The source electrical connection220aand the drain electrical connection220bmay generate an electric field. The electric field may sweep the charge carriers to the drain electrical connection220b. The charge carriers may be stored near the drain electrical connection220band/or collected into a readout circuit.

The polycrystalline silicon resistive gate218may include heavily doped polycrystalline silicon. The heavily doped polycrystalline silicon may be an n-type semiconductor or a p-type semiconductor. The heavily doped polycrystalline silicon may be heavily doped with atoms (e.g., donor atoms or acceptor atoms). For example, the heavily doped polycrystalline silicon may be heavily doped phosphorous. The atoms may saturate the carrier traps of the heavily doped polycrystalline silicon. The heavily doped polycrystalline silicon may be heavily doped with a select concentration of the atoms (e.g., the donor atoms or the acceptor atoms). For example, the heavily doped polycrystalline silicon may be doped with between 30 and 200 times the amount necessary to saturate the carrier traps of the polycrystalline silicon. In others words, the heavily doped polycrystalline silicon may be doped with between 30 and 200 times the ratio of the grain boundary trapping state density to the grain size. The concentration of the atoms at which the polycrystalline silicon resistive gate218is doped may be between 1×10{circumflex over ( )}19 and 6×10{circumflex over ( )}19 at/cm{circumflex over ( )}3. Particularly for phosphorus, the concentration may be between 1.6×10{circumflex over ( )}19 and 6×10{circumflex over ( )}19 at/cm{circumflex over ( )}3.

The doped polycrystalline silicon may be ion-implanted with an electrically inactive species. The electrically inactive species may not contribute electrically to the polycrystalline silicon resistive gate218. The electrically inactive species may also provide no charge carrier depletion within the polycrystalline silicon resistive gate218. The electrically inactive species may include carbon or nitrogen atoms. The concentration of the electrically inactive species at which the doped polycrystalline silicon is implanted may be between 3×10{circumflex over ( )}19 and 3×10{circumflex over ( )}21 at/cmA{circumflex over ( )}3.

The polycrystalline silicon resistive gate218may include a select resistivity. For example, the resistivity of the polycrystalline silicon resistive gate218may be between 1 and 10{circumflex over ( )}4 ohm-cm. The concentration of the electrically inactive species may control the resistivity of the polycrystalline silicon resistive gate218. The resistivity of the polycrystalline silicon resistive gate218may increase with an increase in the concentration of the electrically inactive species.

The resistivity of the polycrystalline silicon resistive gate218may be non-uniform along the polycrystalline silicon resistive gate218. For example, the resistivity of the polycrystalline silicon resistive gate218may be non-uniform along the polycrystalline silicon resistive gate218by changing the concentration of the electrically inactive species which are implanted along the polycrystalline silicon resistive gate218into multiple ion-implanted regions. The ion-implanted regions may define a spatial profile of the resistivity of the polycrystalline silicon resistive gate218.

The polycrystalline silicon resistive gate218may include ion-implanted region302and/or ion-implanted region304. The electrically inactive species may define the ion-implanted region302and/or ion-implanted region304. The ion-implanted region302and the ion-implanted region304may be referred to as first ion-implanted regions and second ion-implanted regions, respectively. The ion-implanted region302and/or ion-implanted region304may be implanted with the electrically inactive species. The ion-implanted region302may be implanted with a higher concentration of the electrically inactive species than the ion-implanted region304. The concentration of the electrically inactive species in the ion-implanted region302and/or the ion-implanted region304may control the resistivity of the ion-implanted region302and/or the ion-implanted region304.

The ion-implanted region302may include a resistivity which is higher than the ion-implanted region304. In this regard, the ion-implanted region302may be referred to as a high resistivity region and the ion-implanted region304may be referred to as a low resistivity region. For example, the resistivity of the ion-implanted region302may be between four and ten times higher than the resistivity of the ion-implanted region304.

The polycrystalline silicon resistive gate218may be a dual-resistivity resistive gate with the ion-implanted region302and the ion-implanted region304, where the polycrystalline silicon resistive gate218includes only two ion-implanted regions. Although the polycrystalline silicon resistive gate218is described as a dual-resistivity resistive gate, this is not intended as a limitation of the present disclosure. It is further contemplated that the polycrystalline silicon resistive gate218may be a multi-resistivity resistive gate with three or more ion-implanted regions (not depicted) with different resistivities. The polycrystalline silicon resistive gate218may include three or more ion-implanted regions, with one or more ion-implanted regions in addition to the ion-implanted region302and ion-implanted region304. The three or more ion-implanted regions may include different concentrations of the electrically inactive species and/or resistivities.

Without the ion-implanted region302and/or the ion-implanted region304, the voltage profile of the polycrystalline silicon resistive gate218may be a 2D distribution and is typically not linear. The polycrystalline silicon resistive gate218may form gradients to control the lateral fields. The voltage profile may become steeper near the center and results in larger lateral electric field. Near the edge, the voltage profile is less steep, and the resulting lateral electric field is weaker, resulting in slower pixel operation as the size of the polycrystalline silicon resistive gate218is increased. The corners of the polycrystalline silicon resistive gate218may have significantly weaker fields and may result in slower charge collection time and slower response time of the pixel127. The uncollected charge is collected on the next readout cycle, resulting in image blur, and is commonly known as image lag.

The ion-implanted region302and/or the ion-implanted region304may improve the voltage profile of the polycrystalline silicon resistive gate218. Controlling the resistivity of the polycrystalline silicon resistive gate218may allow for optimization of the charge collection and fine control of the electric field distribution. An electric field of the polycrystalline silicon resistive gate218may be tailored using the ion-implanted region302and/or the ion-implanted region304to reduce the worst-case field conditions and to improve a speed of the pixels217. The ion-implanted region302and/or the ion-implanted region304may improve the performance of the X-ray detectors122. For example, the ion-implanted region302and/or the ion-implanted region304may improve the charge collection efficiency and lag of the X-ray detectors122. Thus, the ion-implanted region302and/or the ion-implanted region304may allow for high-speed operation of a sensor using a polycrystalline silicon resistive gate218.

The ion-implanted region302and/or the ion-implanted region304may or may not be continuous. For example, the ion-implanted region302and/or the ion-implanted region304may include portions which are separated from additional portions by the other of the ion-implanted region302and/or the ion-implanted region304.

Specific patterns are described that increase the lateral electric field near the outer edge for the polycrystalline silicon resistive gate218using the ion-implanted region302and/or the ion-implanted region304, as compared to uniform implantation.

As depicted inFIG.3A, the ion-implanted region304may be a diagonal-striped ion-implanted region304a. The remainder of the polycrystalline silicon resistive gate218which is not the diagonal-striped ion-implanted region304amay be the ion-implanted region302.

The diagonal-striped ion-implanted region304amay include a pair of diagonal stripes306aand a pair of the diagonal stripes306b. The pair of diagonal stripes306aand the pair of the diagonal stripes306bmay be referred to as a first pair of diagonal stripes and a second pair of diagonal stripes.

The pair of diagonal stripes306amay be colinear. The pair of the diagonal stripes306bmay also be colinear. The pair of the diagonal stripes306bmay be orthogonal to the pair of diagonal stripes306a.

The pair of diagonal stripes306aand the pair of the diagonal stripes306bmay be aligned to the center of the polycrystalline silicon resistive gate218. The pair of diagonal stripes306aand the pair of the diagonal stripes306bmay also be aligned to the corners of the polycrystalline silicon resistive gate218. The pair of diagonal stripes306amay be aligned to first and third corners of the polycrystalline silicon resistive gate218. The pair of diagonal stripes306bmay be aligned to second and third corners of the polycrystalline silicon resistive gate218.

The pair of diagonal stripes306aand the pair of the diagonal stripes306bmay include a select width. The width of the pair of diagonal stripes306aand the pair of the diagonal stripes306bmay or may not be the same. As depicted, the width of the pair of diagonal stripes306aand the pair of the diagonal stripes306bis the same. The width of the pair of diagonal stripes306aand the pair of the diagonal stripes306bmay or may not change along the length of the pair of diagonal stripes306aand the pair of the diagonal stripes306b. As depicted, the width of the pair of diagonal stripes306aand the pair of the diagonal stripes306bdoes not change along the length of the pair of diagonal stripes306aand the pair of the diagonal stripes306b.

The pair of diagonal stripes306aand/or the pair of the diagonal stripes306bmay include a selected length. The length of the pair of diagonal stripes306aand/or the pair of the diagonal stripes306bmay be sufficiently small such that the pair of diagonal stripes306aand/or the pair of the diagonal stripes306bdo not intersect with the pair of diagonal stripes306a, the pair of the diagonal stripes306b, the source electrical connection220a, and/or the drain electrical connection220b. In this regard, the diagonal-striped ion-implanted region304amay form an X-shape with a center intersection removed. The ion-implanted region302may be disposed between and couple the pair of diagonal stripes306a, the pair of the diagonal stripes306b, the source electrical connection220a, and/or the drain electrical connection220b.

The pair of diagonal stripes306aand/or the pair of the diagonal stripes306bmay include a same resistivity. The pair of diagonal stripes306aand/or the pair of the diagonal stripes306bmay include a resistivity which is less than the ion-implanted region302. With the diagonal-striped ion-implanted region304a, the voltage profile of the polycrystalline silicon resistive gate218may be improved near the corners of the polycrystalline silicon resistive gate218. For example, the decrease in resistivity provided by the diagonal-striped ion-implanted region304amay reduce the voltage drop in the corners of the polycrystalline silicon resistive gate218.

As depicted inFIG.3B, the ion-implanted region304may be a polygonal-shaped ion-implanted region304b. The remainder of the polycrystalline silicon resistive gate218which is not the polygonal-shaped ion-implanted region304bmay be the ion-implanted region302.

The difference in voltage applied between the source electrical connection220aand the drain electrical connection220bresults in a voltage gradient in the polycrystalline silicon resistive gate218and a lateral electric field under the polycrystalline silicon resistive gate218and within the depleted bulk of the X-ray detector122. The source electrical connection220aand the drain electrical connection220bcarry identical average current due to Kirchhoff's junction law, which states that the current into a circuit node must equal the current going out of the circuit node. The source electrical connection220ahas a much larger perimeter compared to the drain electrical connection220b, which allows for many more electrical contacts to handle the current required to bias the ion-implanted region302and the ion-implanted region304. Also, the current in the polycrystalline silicon resistive gate218near the drain electrical connection220bhas a much higher current density than the outer regions, resulting in relatively high local heat generation. The resistivity level of the ion-implanted region302with ion-implantation of electrically inactive species may be further tuned so that the total current may be reduced, reducing the power dissipation near the drain electrical connection220bto acceptable levels. The doping ratio of the ion-implanted region302and the ion-implanted region304may be adjusted to retain previously described benefits.

The polygonal-shaped ion-implanted region304bmay be centered on the polycrystalline silicon resistive gate218. For example, a centroid of the polygonal-shaped ion-implanted region304bmay be centered on the polycrystalline silicon resistive gate218. The drain electrical connection220bmay also be centered on the polygonal-shaped ion-implanted region304band/or the polycrystalline silicon resistive gate218. The ion-implanted region302may be disposed between and couple the source electrical connection220aand the polygonal-shaped ion-implanted region304b.

The polygonal-shaped ion-implanted region304bmay include any n-agonal shape, where n is an integer. For example, the polygonal-shaped ion-implanted region304bmay be a triangle, a quadrilateral (e.g., a rectangle, trapezoid, parallelogram, rhombus, or the like), a pentagon, a hexagon, a heptagon, an octagon, or the like. As depicted, the polygonal-shaped ion-implanted region304bmay be an octagon, although this is not intended to be limiting.

The polygonal-shaped ion-implanted region304bmay or may not be a regular polygon. The polygonal-shaped ion-implanted region304bmay include reflective symmetry and/or rotational symmetry. As depicted, the polygonal-shaped ion-implanted region304bis the octagon which is not regular, which includes a reflective symmetry about four axes which are each offset by 45° and are each orthogonal to the center axis of the polygonal-shaped ion-implanted region304b, and which includes a rotational symmetry of 90°. The center axis of the polygonal-shaped ion-implanted region304bmay be coincident to the center and aligned through the thickness. In this example, the lengths of the sides of the octagon alternate between long sides and short sides. Pairs of the long sides may be parallel to each other. Similarly, pairs of the short sides may be parallel to each.

FIG.4depicts the circuit elements212, in accordance with one or more embodiments of the present disclosure. The circuit elements212may include one or more channels. For example, the circuit elements212may include a sensor channel402and/or a read-out integrated circuit channel404(ROIC channel). The circuit elements212may include one or more of a signal ground406, a current source (I), a signal capacitor (C_Sig), a transfer gate transistor (M_TG), a floating diffusion capacitor (C_FD), a reset transistor (M1R), a voltage source (VS), a gain transistor (M1), a gain transistor (M2), a reset transistor (M2R), a transfer gate pickup (T_gate), a reset control signal (R_gate), a reset voltage (R_drain), a resistive gate (RG1), a resistive gate (RG2), an amplifier408, an output signal (+Sig), and/or an output signal (−Sig).

The reset transistor (M1R) may also be referred to as a first reset transistor. The reset transistor (M2R) may also be referred to as a second reset transistor. The gain transistor (M1) may also be referred to as a first gain transistor. The gain transistor (M2) may also be referred to as a second gain. The resistive gate (RG1) may also be referred to as a first resistive gate. The resistive gate (RG2) may also be referred to as a second resistive gate. The output signal (+Sig) may also be referred to as a first output signal. The output signal (−Sig) may also be referred to as a second output signal.

The sensor channel402may include the current source (I), the signal capacitor (C_Sig), the transfer gate transistor (M_TG), the floating diffusion capacitor (C_FD), the reset transistor (M1R), the voltage source (VS), the gain transistor (M1), the gain transistor (M2), the reset transistor (M2R), the transfer gate pickup (T_gate), the reset control signal (R_gate), and/or the reset voltage (R_drain).

The read-out integrated circuit channel404may include the resistive gate (RG1), the resistive gate (RG2), the amplifier408, the output signal (+Sig), and/or the output signal (−Sig).

The current source (I) may provide a source of current for the sensor channel402. An output of the current source (I), a first side of the signal capacitor (C_Sig), and a drain of the transfer gate transistor (M_TG) may connect in parallel.

The signal capacitor (C_Sig) may collect charges from the current source (I) and/or the drain of the transfer gate transistor (M_TG). A second side of the signal capacitor (C_Sig) may connect to signal ground406.

A gate of the transfer gate transistor (M_TG) and the transfer gate pickup (T_gate) may be connected. The transfer gate pickup (T_gate) may control the flow of charges through the transfer gate pickup (T_gate).

A source of the transfer gate transistor (M_TG), a first side of the floating diffusion capacitor (C_FD), a drain of the reset transistor (M1R), and/or a gate of the gain transistor (M1) may be connected in parallel.

The floating diffusion capacitor (C_FD) may collect charge carriers that are generated within the pixels217(e.g., within the buried channel layer216). For example, the signal capacitor (C_Sig) may collect charge carriers from the drain of the reset transistor (M1R). A second side of the floating diffusion capacitor (C_FD) may be connected to the signal ground406.

A gate of the reset transistor (M1R), a gate of the reset transistor (M1R), and the reset control signal (R_gate) may be connected in parallel. The reset control signal (R_gate) may control the flow of charge carriers through the reset transistor (M1R) and/or the reset transistor (M1R). The reset control signal (R_gate) may provide a global signal which is common to each of the pixels217.

A source of the reset transistor (M1R), a source of the reset transistor (M2R), and the reset voltage (R_drain) may be connected in parallel. The reset voltage (R_drain) may provide a source of charge carriers for the reset transistor (M1R) and/or the reset transistor (M1R). The reset voltage (R_drain) may also provide a global signal which is common to each of the pixels217.

The reset transistor (M1R) and/or the reset transistor (M2R) may reset a voltage of the floating diffusion capacitor (C_FD). For example, the reset transistor (M1R) and/or the reset transistor (M2R) may reset a voltage of the floating diffusion capacitor (C_FD) after a readout operation. The reset transistor (M1R) and/or the reset transistor (M2R) may reset the voltage using the reset voltage (R_drain) in response to the reset control signal (R_gate). In this state, fluctuations in the common ground reference will not impact the difference between the drain currents of the gain transistor (M1) and the gain transistor (M1) measured at the amplifier408.

A source of the gain transistor (M1), a source of the gain transistor (M2), and/or the voltage source (VS) may be connected in parallel. The voltage source (VS) may provide a source of charge carriers for the gain transistor (M1) and/or the gain transistor (M2).

A gate of the gain transistor (M2) and the drain of the reset transistor (M2R) may be connected. The reset transistor (M2R) may control the flow of charge carriers through the gain transistor (M2).

A drain of the gain transistor (M1), an input (+) of the amplifier408, and/or a first side of the resistive gate (RG1) may be connected. The amplifier408may generate the output signal (+Sig) based on the input (+). The resistive gate (RG1) may provide the output signal (+Sig) as feedback to the input (+) of the amplifier408.

A drain of the gain transistor (M2), an input (−) of the amplifier408, and/or a first side of the resistive gate (RG2) may be connected in parallel. The amplifier408may generate the output signal (−Sig) based on the input (−). The resistive gate (RG2) may provide the output signal (−Sig) as feedback to the input (−) of the amplifier408.

The signal capacitor (C_Sig) and/or the floating diffusion capacitor (C_FD) may be formed by an n+ dopant diffused into the buried channel layer216.

The transfer gate transistor (M_TG), the reset transistor (M1R), the gain transistor (M1), the gain transistor (M2), and/or the reset transistor (M2R) may be N-channel transistors. For example, the transfer gate transistor (M_TG), the reset transistor (M1R), the gain transistor (M1), the gain transistor (M2), and/or the reset transistor (M2R) may be N-channel metal-oxide-semiconductor (NMOS) transistors.

The resistive gate (RG1) and/or the resistive gate (RG2) may be the polycrystalline silicon resistive gate218.

The circuit elements212may provide a readout method using the polycrystalline silicon resistive gate218. The polycrystalline silicon resistive gate218may be a highly-doped low-resistivity polycrystalline silicon gate. The circuit elements212may be configured to operate in a differential mode and/or a current mode. The differential readout in current mode may reduce feedthrough noise and power usage.

The circuit elements212may provide the differential mode for reading out the output signals from the pixels217. The difference between the output signal (+Sig) and the output signal (−Sig) may be based on the charge collected in the floating diffusion capacitor (C_FD) and/or the X-ray photons received by the X-ray detector122. The circuit elements212may determine the difference between the output signal (+Sig) and the output signal (−Sig) and/or convert the difference to the X-ray image data signal ID.

The circuit elements212may provide several advantages over circuit elements which do not include the differential mode. For example, the differential mode may provide common mode noise immunity from fluctuations in the reset control signal (R_gate). The output signal (+Sig) and the output signal (−Sig) may each change the same amount based on the fluctuations, thereby removing the fluctuations when the difference is determined. The circuit elements212may also reduce an offset mismatch between the pixels217. The circuit elements212may allow for low-power and high bandwidth operation to collect the image data signal from the pixel217with good noise immunity. The noise immunity may allow scaling the pixels217into one- and two-dimensional array formats.

The circuit elements212may also provide the current mode. The current mode may allow for high-bandwidth with reduced area and power requirements from the gain transistor (M1) and the gain transistor (M2). The current mode may mitigate the power penalty for differential mode operation. Use of current mode operation may also provide enhanced signal range without the severe saturation that might occur in a low-voltage semiconductor process. The large signals can be handled separately by the read-out integrated circuit channel404that may use a process technology optimized for low-noise signal processing.

FIG.5depicts a flow diagram of a method500, in accordance with one or more embodiments of the present disclosure. The method500is a method of forming the polycrystalline silicon resistive gates218. The method500may provide a controllable and repeatable process by which the resistivity of the polycrystalline silicon resistive gates218may be controlled. The embodiments and enabling technologies described previously herein in the context of the polycrystalline silicon resistive gates218should be interpreted to extend to method500. It is further noted, however, that the method is not limited to the architecture of the polycrystalline silicon resistive gates218.

In a step510, a polycrystalline silicon film may be deposited. For example, the polycrystalline silicon film may be deposited on the gate oxide layer208. The polycrystalline silicon film may be deposited using any suitable process, such as, but not limited to, chemical vapor deposition.

In a step520, the polycrystalline silicon film is heavily doped with atoms. The atoms may be an N-type impurity (e.g., donor atoms) or a P-type impurity (e.g., acceptor atoms). For example, the polycrystalline silicon film may be heavily doped with phosphorous when N-type polysilicon is desired or boron when a P-type polysilicon is desired. The polycrystalline silicon film may be heavily doped with the atoms to form heavily doped polycrystalline silicon. The polycrystalline silicon film may be heavily doped with the atoms to provide charge carriers well in excess to those necessary to fill the traps.

In a step530, the heavily doped polycrystalline silicon is ion-implanted with an electrically inactive species to form multiple ion-implanted regions with different resistivities. For example, the heavily doped polycrystalline silicon is ion-implanted with an electrically inactive species to form the ion-implanted region302and/or ion-implanted region304. The electrically inactive species may include nitrogen and carbon.

The heavily doped polycrystalline silicon may be ion-implanted with the electrically inactive species to form the ion-implanted regions using a beamline scan ion implantation technique or a plasma immersion ion implantation (Pill) technique. The beamline scan ion implantation technique may be used to reduce levels of unwanted species implantation into the polysilicon. The plasma immersion ion implantation may immerse the heavily doped polycrystalline silicon in a plasma containing the electrically inactive species. High voltage microsecond negative pulses may be applied to the heavily doped polycrystalline silicon. The pulses may accelerate and implant the plasma ions into the heavily doped polycrystalline silicon. An off time follows each implant pulse. The off time may allow the plasma electrons to neutralize the deposited positive charge.

Complex field patterns of the ion-implanted regions may be achieved via implant writing. The plasma immersion ion implantation may include a multi-step (2 or more) to form multiple of the ion-implanted regions. The plasma immersion ion implantation may also control a gain of the ion-implanted regions for achieving specific resistivity within the ion-implanted regions. The ion-implanting with the electrically inactive species may include one or more sub-steps by which the ion-implanted regions are formed.

In a sub-step532, a selected region of the polycrystalline silicon resistive gates may be masked. For example, the selected region may be masked on the polycrystalline silicon film. The mask may be deposited by any suitable process, such as, but not limited to photolithography, etching, or the like. The selected region may be regions which are masked and not currently to be ion-implanted. The mask may prevent the masked region from being ion-implanted when the unmasked region is ion-implanted. For example, the ion-implanted region304may be the masked region where the ion-implanted region302is the unmasked region to be ion-implanted. By way of another example, the ion-implanted region302may be the masked region where the ion-implanted region304is the unmasked region to be ion-implanted.

In a sub-step534, the unmasked region of the polycrystalline silicon resistive gates may be ion-implanted with the electrically inactive species. For example, the ion-implanted region302may be the unmasked region and may be ion-implanted with a first concentration of the electrically inactive species when the ion-implanted region304is masked. By way of another example, the ion-implanted region304may the unmasked region and may be ion-implanted with a second concentration of the electrically inactive species when the ion-implanted region302is masked. The concentrations of the electrically inactive species at which the ion-implanted region302and the ion-implanted region304are ion-implanted may be different by the masking preventing the masked region from being ion-implanted.

In a sub-step536, the selected region may be unmasked. The selected region may be unmasked via any suitable process, such as, but not limited to, etching. The selected region may be unmasked to unmask the polycrystalline silicon resistive film. For example, the ion-implanted region302and/or the ion-implanted region304may be unmasked.

The polycrystalline silicon film may be masked, ion-implanted, and unmasked to ion-implant each of the regions with the select concentration. Multiple separate regions of the higher- or lower-resistivity regions may be patterned onto a single of the polycrystalline silicon film by masking selected regions, the ion-implantation may be applied, and then the mask layer may be removed. Additional deposition steps may also be employed, to achieve finer control of lateral fields and charge transport within a two-dimensional region of the polycrystalline silicon film. For example, the polycrystalline silicon resistive gates218may be a multi-resistivity resistive gate, with three or more ion-implanted regions each with different resistivities which control the lateral fields.

The implantation may accurately and reproducibly control the resistivities within the ion-implanted regions using the electrically inactive species. Controlling the concentration of the electrically inactive species may provide reproducible and controllable resistivity values in the range of 1-10 k ohm-cm for the ion-implanted regions of the polycrystalline silicon film.

In a step540, the heavily doped polycrystalline silicon may be annealed after the implantation to form a polycrystalline silicon resistive gate. For example, the heavily doped polycrystalline silicon may be annealed to form the polycrystalline silicon resistive gate218. The annealing may cause the impurity (e.g., the donor atoms, the acceptor atoms) to form small and stable precipitates which will lower the mobility of charge carriers and increase resistivity.

The heavily doped polycrystalline silicon may be annealed at a select temperature, such as, but not limited to, 1000° C. The annealing may activate the dopant after ion-implantation and form an inter-layer dielectric (e.g., the gate oxide layer208and/or the silicon nitride gate layer210).

The heavily doped polycrystalline silicon may be annealed in an O2 atmosphere to form the gate oxide layer208. The gate oxide layer208may be formed over the ion-implanted regions to seal the ion-implanted regions. The duration of annealing in the O2 atmosphere may control the thickness of the gate oxide layer208. A thicker layer of the gate oxide layer208may provide better isolation due to high operation voltage between polysilicon layers. The heavily doped polycrystalline silicon may be annealed in O2 at the select temperature for a select duration, such as, but not limited to, 2 minutes.

The heavily doped polycrystalline silicon may be annealed in an N2 atmosphere to form the silicon nitride gate layer210. The remainder of the annealing may be carried out in the N2 atmosphere.

In embodiments, a controller may include one or more controllers housed in a common housing or within multiple housings. In this way, any controller or combination of controllers may be separately packaged as a module suitable for integration into a system. Further, the controllers may analyze data received from detectors and feed the data to additional components within the system or external to the system. The controller may also include one or more processors and/or a memory medium.

The one or more processors may include any processor or processing element known in the art. For the purposes of the present disclosure, the term “processor” or “processing element” may be broadly defined to encompass any device having one or more processing or logic elements (e.g., one or more micro-processor devices, one or more application specific integrated circuit (ASIC) devices, one or more field programmable gate arrays (FPGAs), or one or more digital signal processors (DSPs)). In this sense, the one or more processors may include any device configured to execute algorithms and/or instructions (e.g., program instructions stored in memory). In one embodiment, the one or more processors may be embodied as a desktop computer, mainframe computer system, workstation, image computer, parallel processor, networked computer, or any other computer system configured to execute a program. Moreover, different subsystems of the system may include a processor or logic elements suitable for carrying out at least a portion of the steps described in the present disclosure. Therefore, the above description should not be interpreted as a limitation on the embodiments of the present disclosure but merely as an illustration. Further, the steps described throughout the present disclosure may be carried out by a single controller or, alternatively, multiple controllers.

The memory medium may include any storage medium known in the art suitable for storing program instructions executable by the associated one or more processors. For example, the memory medium may include a non-transitory memory medium. By way of another example, the memory medium may include, but is not limited to, a read-only memory (ROM), a random-access memory (RAM), a magnetic or optical memory device (e.g., disk), a magnetic tape, a solid-state drive and the like. The memory medium may include flash memory cells, or other type memory, discrete EPROM or EEPROM, or the like. It is further noted that memory medium may be housed in a common controller housing with the one or more processors. In one embodiment, the memory medium may be located remotely with respect to the physical location of the one or more processors and controller. For instance, the one or more processors of controller may access a remote memory (e.g., server), accessible through a network (e.g., internet, intranet and the like).

As used throughout the present disclosure, the term “substrate” generally refers to a substrate formed of a semiconductor or non-semiconductor material (e.g., thin filmed glass, or the like). For example, a semiconductor or non-semiconductor material may include, but is not limited to, monocrystalline silicon, gallium arsenide, indium phosphide, or a glass material. A substrate may include one or more layers. For example, such layers may include, but are not limited to, a resist (including a photoresist), a dielectric material, a conductive material, and a semiconductive material. Many different types of such layers are known in the art, and the term sample as used herein is intended to encompass a substrate on which all types of such layers may be formed. One or more layers formed on a substrate may be patterned or un-patterned. For example, a substrate may include a plurality of dies, each having repeatable patterned features. Formation and processing of such layers of material may ultimately result in completed devices. Many different types of devices may be formed on a substrate, and the term substrate as used herein is intended to encompass a substrate on which any type of device known in the art is being fabricated. Further, for the purposes of the present disclosure, the term substrate and wafer should be interpreted as interchangeable. In addition, for the purposes of the present disclosure, the terms patterning device, mask, and reticle should be interpreted as interchangeable.

As used herein, directional terms such as “top,” “bottom,” “over,” “under,” “upper,” “upward,” “lower,” “down,” and “downward” are intended to provide relative positions for purposes of description, and are not intended to designate an absolute frame of reference. Various modifications to the described embodiments will be apparent to those with skill in the art, and the general principles defined herein may be applied to other embodiments.