Low dropout regulators

Low dropout regulators capable of preventing damage caused by a short circuit or a heavy load are provided, in which a pass transistor receives an unregulated power supply voltage to generate a regulated output voltage according to a control signal. Additionally, a constant overcurrent limiting circuit limits an output current through the pass transistor to below a predetermined current, and a foldback overcurrent limiting circuit enables the constant overcurrent limiting circuit to further decrease the output current, when the regulated output voltage is lower than a predetermined voltage.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to power regulation, and more particularly, to low dropout (LDO) regulators capable of preventing damage caused by a short circuit or a heavy load.

2. Description of the Related Art

A regulator converts an unstable power supply voltage into a stable power supply voltage. A low dropout (LDO) regulator has a low input-to-output voltage difference between an input terminal where an unstable power supply voltage is inputted and an output terminal where a stable power supply voltage is outputted. “Dropout voltage” refers to the input-to-output voltage difference, whereby the regulator ceases to regulate against further reductions in input voltage. Ideally, the dropout voltage should be as low as possible, to allow the input voltage to be relatively low, while still maintaining regulation. Thus, assuring that the input-to-output voltage difference is low and minimizing power dissipation and maximizing efficiency are important.

Generally, the conventional LDO regulator includes a protection circuit such as an over-current protection circuit so as to protect the circuit during abnormal operating conditions. For example, the over-current protection circuit maintains the output current (IOUT) of the LDO at a predetermined current value and controls the LDO to reduce the output current (IOUT) when an output voltage (VOUT) thereof is lower than a predetermined value caused by a heavy load (i.e. a short circuit occurs).

However, the foldback voltage of the conventional LDO is not accurate, the foldback voltage is affected by ambient temperature and adjustment range of the foldback voltage is limited. Further, after the output voltage is foldback, the output current correlates with the ambient temperature, other circuit parameters and process parameters, and thus, control of the output current is difficult.

BRIEF SUMMARY OF THE INVENTION

Embodiments of a low dropout regulator are provided, in which a pass transistor receives an unregulated power supply voltage to generate a regulated output voltage according to a control signal, a constant overcurrent limiting circuit limits an output current through the pass transistor to below a predetermined current, and a foldback overcurrent limiting circuit enables the constant overcurrent limiting circuit to further decrease the output current, when the regulated output voltage is lower than a predetermined voltage.

The invention provides an embodiment of an overcurrent protection circuit, in which a constant overcurrent limiting circuit limits an output current through a pass transistor below a predetermined current, and a foldback overcurrent limiting circuit enables the constant overcurrent limiting circuit to further decrease the output current, when the regulated output voltage is lower than a predetermined voltage.

The invention provides an embodiment of a method for providing overcurrent protection in a regulator, in which an output current through a pass transistor in the power regulator is limited to below a predetermined current by a constant overcurrent limiting circuit, and the predetermined current is decreased to enable the constant overcurrent limiting circuit to further decrease the output current according to the decreased predetermined current, when a regulated output voltage of the pass transistor is lower than a predetermined voltage.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1is a schematic diagram of an embodiment of a low dropout (LDO) regulator100mainly comprising a pass transistor PT, a driving circuit10, a feedback circuit11, and an overcurrent protection circuit12. The feedback circuit11comprises resistors R1and R2. An unregulated power supply voltage VIN is applied to a power line. The pass transistor PT receives the unregulated power supply voltage VIN and generates an output voltage that varies depending upon a control signal VG, and outputs to a load13. The feedback circuit11detects a current flowing through the pass transistor PT and generates a feedback signal VFB. The output voltage VOUT is divided by the resistors R1and R2, and the divided voltage of the output voltage VOUT becomes the feedback signal VFB.

The driving circuit10compares the feedback signal VFB with a reference voltage VREF1from a reference voltage generator and generates the control signal VG that varies depending upon the voltage difference between the reference signal VREF1and the feedback signal VFB. For example, the driving circuit10comprises an error amplifier, but is not limited thereto. In preferred embodiments, the reference voltage generator provides the reference voltage VREF1regardless of manufacturing process variations and/or temperature variations.

The overcurrent protection circuit12prevents the LDO regulator100from damage caused by overcurrent. The overcurrent protection circuit12comprises a constant overcurrent limiting circuit (COLC)20and a foldback overcurrent limiting circuit (FOLC)30. The COLC20detects an output current IOUT flowing through the pass transistor PT and limits the output current IOUT to below a predetermined current. For example, the COLC20detects the output current IOUT and pulls a voltage level of the gate terminal of the pass transistor PT high (i.e., increases the voltage level of the control signal VG) when the output current IOUT exceeds the predetermined current, thereby suppressing the increased output current IOUT.

Because the output current IOUT is limited by the COLC20, the output voltage VOUT decreases when a short circuit (i.e., a heavy load condition) occurs, such that the voltage across the pass transistor PT overly increases. In this example, the excessive voltage may burn out the pass transistor PT or some component in the LDO regulator100, such that the LDO regulator100fails to operate. However, the FOLC30enables the COLC20to further decrease the output current IOUT when the output voltage VOUT is lower than a predetermined voltage because of a short circuit (or a heavy load condition), thereby preventing damage caused by excessive voltage across the pass transistor PT. For example, the FOLC30decreases the predetermined current for limiting the output current IOUT when the output voltage VOUT is lower than the predetermined voltage, such that the COLC20further decreases the output current IOUT according to the decreased predetermined current. In some examples, the FOLC30can compare the output voltage VOUT with a reference voltage to determine whether the output voltage VOUT is higher than the predetermined voltage. Alternatively, the FOLC30can compare a division voltage of the output voltage VOUT with a reference voltage to determine whether the output voltage VOUT is higher than the predetermined voltage. The detailed operations of the overcurrent protection circuit12will be illustrated hereinafter.

FIG. 2shows an embodiment of the LDO regulator. As shown, the LDO regulator100A is similar to the LDO regulator100inFIG. 1, differing only, in that the COLC20A is implemented by a constant current source CS1, PMOS transistors MP1and MP2and NMOS transistors MN1and MN2, and the FOLC30A compares the output voltage VOUT with a reference voltage VREF2to determine whether a short circuit (a heavy load) has occurred. Operations of the components which are similar to that in the LDO regulator100are omitted for simplification.

The constant current source CS1is coupled between the unregulated power supply voltage VIN and a node ND1to provide a constant current I1. The NMOS transistor MN1comprises a drain terminal coupled to the node ND1, a source terminal coupled to a ground voltage, and a gate terminal coupled to the NMOS transistor MN2. The NMOS transistor MN2comprises a drain terminal coupled to a gate terminal thereof, and a source terminal coupled to the ground voltage, in which the size of the NMOS transistor MN1is in proportion to that of the NMOS transistor MN2. The NMOS transistors MN1and MN2form a current mirror, and a current I2A flowing through the NMOS transistor MN1is in proportion to a current I2B flowing through the NMOS transistor MN2. The current I2A can be regarded as a mirror current of the current I2B. The PMOS transistor MP1comprises a source terminal coupled to the unregulated power supply voltage VIN, a drain terminal coupled to a gate terminal of the PMOS transistor MP2, and a gate terminal coupled to the node ND1. The PMOS transistor MP2comprises a source terminal coupled to the unregulated power supply voltage VIN, a drain terminal coupled to the drain terminal of the NMOS transistor MN2, and a gate terminal coupled to the gate terminal of the pass transistor PT.

When the output voltage VOUT is higher than the reference voltage VREF2, the FOLC30A does not work. For example, the current I3can be zero, but is not limited thereto. Since the source terminals of the transistor MP2and pass transistor PT are both coupled to the unregulated power supply voltage VIN and the gate terminals are both coupled to the control signal VG from the driving circuit10, the current I2B through the PMOS transistor MP2is in proportion to the output current IOUT, and thus, the PMOS transistor MP2can be used to detect the output current IOUT flowing through the pass transistor PT. Because the current I2A is also in proportion to the current I2B, the current I2A is in proportion to the current IOUT. In this embodiment, the currents I2A and I2B increase as the output current increases, but is not limited thereto. In this case, the node ND1can be regarded as a current comparator comparing the current I1and the current I2A. When the current I2A is smaller than the current I1, the voltage level on the node ND1rises to high (close to the unregulated power supply voltage VIN). On the contrary, when the current I2B exceeds the current I1, the voltage on the node ND1falls (close to ground), such that the transistor MP1is turned on to pull high the gate terminal of the pass transistor PT, thereby overcurrent. In a steady condition, the current I2A is approximately equal to the current I1, and the output current IOUT can be limited below a predetermined current. Namely, the predetermined current is in direct proportion to the current I1provided by the constant current source CS1, and thus the predetermined current can be adjusted by increasing/decreasing the current I1.

In this embodiment, the FOLC30A drains out a current I3from the current I1to enable the COLC20A to further decrease the predetermined current, when the output voltage VOUT is lower than a predetermined voltage because of a short circuit (or a heavy load condition), the FOLC30A enables the COLC20A to further decrease the output current IOUT. For example, the current I3drained by the FOLC30A can be increased as the output voltage VOUT decreases, but is not limited thereto. At this time, the voltage on the node ND1falls when the current I1is smaller than the current (I2A+I3), and the voltage on the node ND1rises when the current I1exceeds the current (I2A+I3). Hence, the COLC20A further decrease the output current IOUT until the sum of the current I2A (which is proportion to the output current IOUT) and the current I3is approximately equal to the current I1provided by the constant current source CS1. Namely, it can be regarded as that the COLC20A limits the output current IOUT to below the decreased predetermined current. As a result, the output current IOUT decreases as the output voltage VOUT decreases, when a short circuit (or a heavy load condition) occurs. Thus, damage caused by a short circuit or a heavy load condition can be prevented.

FIG. 3shows another embodiment of the LDO regulator. As shown, the LDO regulator100B is similar to the LDO regulator100A inFIG. 2, differing only, in that constant current source CS1is replaced by a controllable current source CS2, the FOLC30A enables the current source CS2to decrease the predetermined current when the output voltage VOUT is lower than the predetermined voltage, such that the output current IOUT is further decreased as the output voltage VOUT decreases.

As mentioned inFIG. 2, the predetermined current is in direct proportion to the current I1provided by the constant current source CS1, and thus, in this embodiment, the current source CS2decreases the current IS to decrease the predetermined current. At this time, the voltage level on the node ND1falls when the current I2A decreased exceeds the decreased current IS, and the voltage level on the node ND1rises when the current I2A is smaller than the decreased current IS. Namely, the COLC20A further decrease the output current IOUT until the current I2A (which is proportion to the output current IOUT) is approximately equal to the current IS deceased by the current source CS2. It can be regarded as that the COLC20A limits the output current IOUT to below the decreased predetermined current. As a result, the output current IOUT decreases as the output voltage VOUT decreases, when a short circuit (or a heavy load condition) occurs. Thus, damage caused by a short circuit or a heavy load condition can be prevented.

FIG. 4shows another embodiment of the LDO regulator. As shown, the LDO regulator100C is similar to the LDO regulator100A inFIG. 2, differing only, in that the COLC20B is implemented by a constant current source CS3, NMOS transistors NM3˜MN6, PMOS transistors MP3˜MP7and resistors R3˜R4, and the FOLC30B is implemented by a constant current source CS4, PMOS transistors MP9˜MP9and NMOS transistors MN7˜MN9. Operations of the driving circuit10, the pass transistor PT and the resistors R1and R2are similar to that illustrated inFIG. 1and thus, are omitted for simplification.

The PMOS transistor MP3comprises a source terminal coupled to a node ND3, a drain terminal coupled to a node NOUT, and a gate terminal coupled to the gate terminal of the pass transistor PT. The resistor R3is coupled between the unregulated power supply voltage VIN and the node ND3, and the PMOS transistor MP4comprises a source terminal coupled to the node ND3, a drain terminal coupled to a node ND4and a gate terminal coupled to the node ND4and a gate terminal of the PMOS transistor MP5. The resistor R4is coupled between the unregulated power supply voltage VIN and a source terminal of the PMOS transistor MP5, and the PMOS transistor MP5comprises a source terminal coupled to the resistor R4, a drain terminal coupled to a node ND5and a gate terminal coupled to the PMOS transistor MP3. The constant current source CS3is coupled between the unregulated power supply voltage VIN and a node ND6, and the NMOS transistor MN3comprises a drain terminal coupled to the node ND6, a source terminal coupled to the ground voltage, and a gate terminal coupled to the node ND6and the NMOS transistor MN6.

The NMOS transistor MN4comprises a drain terminal coupled to the node ND4, a gate coupled to the NMOS transistor MN3, and a source terminal coupled to the ground voltage. The NMOS transistor MN5comprises a drain terminal coupled to the node ND5, a gate coupled to the NMOS transistors MN3and MN4, and a source terminal coupled to the ground voltage GND. The NMOS transistor MN6comprises a drain terminal coupled to a node ND7, a source terminal coupled to the ground voltage, and a gate terminal coupled to the node ND5. The PMOS transistor MP6comprises a source terminal coupled to the unregulated power supply voltage VIN, a drain terminal coupled to the node ND7, and a gate terminal coupled to the node ND7and the PMOS transistor MP7. The PMOS transistor MP7comprises a source terminal coupled to the unregulated power supply voltage VIN, a gate terminal coupled to the PMOS transistor MP6, and a drain terminal coupled to the gate terminals of the pass transistor PT and the PMOS transistor MP3.

The constant current source CS3and the PMOS transistors MN3˜MN5form a current source. In this embodiment, a current I5A flowing through the NMOS transistor MN3, is identical to a current I5B flowing through the NMOS transistor MN4and the PMOS transistor MP4, and a current I5C flowing through the NMOS MN5and the PMOS transistor MP5. Because a current I4provided by the constant current source CS3is equal to a sum of the current I5A (or I5B or I5C) and a current I6, the current I5A decreases as the current I6increases.

Since the gate terminals of the pass transistor PT and the PMOS transistor MP3are connected together and the drain terminals are connected to the node NOUT, a current I7flowing through the PMOS transistor MP3increases as the output current IOUT increases. Because the currents I5B and I5C flowing through the PMOS transistor MP4and MP5are limited by the NMOS transistors MN4and MN5, a current I6flowing through the resistor R3increases such that a voltage level at the node ND3accordingly decreases when the current I7increases.

Once the output current IOUT exceeds a predetermined current, the voltage level at the node ND4is decreased such that a voltage level at the node ND5is increased to turn on the NMOS transistor NM6. As the NMOS transistor MN6is turned on, a voltage level at the node ND7is pulled low, such that the PMOS transistors MP6and MP7are turned on. As a result, the voltage level at the gate terminals of the pass transistor PT and the PMOS transistor MP3is increased to decrease the output current IOUT, such that the output current IOUT can be limited to below the predetermined current. In this embodiment, the voltage level at the node ND5can be regarded as being more sensitive to that at the node ND3, as the current I5A decreases. Namely, the current I5A (which is identical to the currents I5B and I5C) is in direct ratio to the predetermined current. Thus, in this embodiment, the COLC20B can limit the output current IOUT to below a smaller predetermined current by decreasing the current I5A.

The NMOS transistor MN7comprises a drain terminal coupled to the node ND6, a gate coupled to the NMOS transistor MN8, and a source terminal coupled to the ground voltage. The constant current source CS4is coupled between the unregulated power supply voltage VIN and a node ND8. The PMOS transistor MN8comprises a source terminal coupled to the node ND8, a gate terminal coupled to a division voltage (i.e., A.VOUT) of the output voltage VOUT and a drain terminal coupled to the NMOS transistor MN8, in which the coefficient A is smaller than 1. The NMOS transistor MN8comprises a drain terminal coupled to the PMOS transistor MP8, a source terminal coupled to the ground voltage, and a gate terminal coupled to the drain terminal thereof and the gate terminal of the NMOS transistor MN7. The PMOS transistor MP9comprises a source terminal coupled to the node ND8, a gate terminal coupled to the reference voltage VREF2, and a drain terminal coupled to the NMOS transistor MN9. The NMOS transistor MN9comprises a drain terminal coupled to the PMOS transistor MP9, a gate terminal coupled to the drain terminal thereof, and a source terminal coupled to the ground voltage.

When the output voltage VOUT is lower than a predetermined voltage because of a short circuit (or a heavy load condition), the FOLC30B enables the COLC20B to further decrease the output current IOUT. For example, when the division voltage A.VOUT is higher than the reference voltage VREF2, the FOLC30B determines that the output voltage VOUT is not lower than a predetermined voltage and does not increase the current IX flowing through the NMOS transistor MN7. Namely, the FOLC30B does not drain out the current IX from the current I4to decrease the current I5A/I5B/I5C to further decrease the predetermined current.

On the contrary, once the division voltage A.VOUT is lower than the reference voltage VREF2, the FOLC30B determines that the output voltage VOUT is lower than the predetermined voltage, and thus, the current IX flowing through the NMOS transistor MN7is accordingly increased as the output voltage VOUT decreases. The current I5A decreases as the current IX is increased because the current I4is equal to the sum of the currents I5A and IX. Namely, when the output voltage VOUT is lower than the predetermined voltage, the FOLC30B decreases the current I5A, such that the predetermined current for limiting the output current OUT is decreased as the output voltage decreases. In this example, the COLC20B further decreases the output current IOUT according to the decreased predetermined current, i.e., the COLC20B limits the output current IOUT to below the decreased predetermined current. As a result, the output current IOUT decreases as the output voltage VOUT decreases, when a short circuit (or a heavy load condition) occurs. Thus, damage caused by a short circuit or a heavy load condition can be prevented.

FIG. 5shows another embodiment of the LDO regulator. As shown, the LDO regulator100D is similar to the LDO regulator100C inFIG. 4, differing only, in that the FOLC30C increases a ratio of the current I8to the output current IOUT to further decrease the predetermined current when the output voltage VOUT is smaller than the predetermined voltage, rather than changing the current I5A. Operations of the COLC20C are similar to that illustrated inFIG. 4and thus, are omitted for simplification.

The FOLC30C comprises a comparator31, two switching elements SW1˜SW2, and a PMOS transistor MP10. The PMOS transistor MP10comprises a source terminal coupled to the node ND3, a drain terminal coupled to the node NOUT, and a gate coupled to the switching elements SW1and SW2, in which the size of the PMOS transistor MP10is N times that of the PMOS transistor MP3. The switching element SW1comprises a first terminal coupled to the gate terminal of the PMOS transistor MP10and a second terminal coupled to the gate terminals of the pass transistor PT and the PMOS transistor MP3, and the switching element SW2is coupled between the unregulated power supply voltage VIN and the gate terminal of the PMOS transistor MP10. The comparator31comprises a first input terminal coupled to the reference voltage VREF2, a second input terminal coupled to the division voltage A.VOUT of the output voltage VOUT and an output terminal coupled to the switching elements SW1and SW2.

For example, when the division voltage A.VOUT is higher than the reference voltage VREF2, the FOLC30C determines that the output voltage VOUT is not lower than a predetermined voltage. As a result, the comparator31outputs a control signal VC to turn the switching element SW1and SW2off and on respectively, such that the PMOS transistor MP10is turned off. The FOLC30C detects whether the output current IOUT exceeds the predetermined current by the PMOS transistor MP3as illustrated inFIG. 4to limit the output current IOUT to below the predetermined current. At this time, a current I8is equal to the current I7flowing through the PMOS transistor MP3.

On the contrary, when the division voltage A.VOUT is lower that the reference voltage VREF2because of a short circuit (or a heavy load condition), the FOLC30C determines that the output voltage VOUT is lower than the predetermined voltage. As a result, the comparator31outputs the control signals VC to turn the switching element SW1and SW2on and off respectively, mad the PMOS transistor MP10is turned on to increase the current I8. In this embodiment, the currents I7and I9are both in direct ratio to the output current IOUT. The current I8can be equal to a sum of the current I7flowing through the PMOS transistor MP3and a current I9flowing through the PMOS transistor MP10. The ratio of the current I8to the output current IOUT is increased to (I7+I9):IOUT from I7:IOUT.

As such, the current I6flowing through resistor R3is greatly increased, the voltage level of the node ND3is accordingly decreased, and the voltage level at the node ND5is increased. As a result, the NMOS transistor MN6is turned on to pull the node ND7lower, such that the PMOS transistors MP6and MP7are turned on. Hence, the voltage level at the gate terminals of the pass transistor PT and the PMOS transistor MP3is increased to further decrease the output current IOUT. Hence, the COLC20C can limit the output current IOUT to below the decreased predetermined current.

Because the LDO regulators100and100A˜100D of the embodiments can further decrease the output current as the output voltage decreases when a short circuit or a heavy load occurs, damage caused by short circuit or a heavy load condition can be prevented.

Although the invention has been described in terms of preferred embodiment, it is not limited thereto. Those skilled in the art can make various alterations and modifications without departing from the scope and spirit of the invention. Therefore, the scope of the invention shall be defined and protected by the following claims and their equivalents.