Fast lock circuit for a phase lock loop

A fast lock circuit for phase lock loop comprising a frequency detector, a phase frequency detector, a logic unit and a corresponding charge pump for the frequency and the phase frequency detectors. Embodiments of the present invention use the logic unit to relay signals from the phase frequency detector circuit to the charge pump when the PLL is in lock. The logic circuit relay signals from the frequency detector circuit before the PLL is in lock. As a result, a constant current is supplied to a large loop filter capacitor before lock. In one embodiment, additional logic circuit may be used to maximize the output current. Therefore, using the logic circuit to supply constant current charges the large loop filter capacitor continuously and avoids a slow down in charging the large loop filter. Accordingly, current is no longer wasted and the lock time is improved.

TECHNICAL FIELD

Embodiments of the present invention relate to the field of electronics. More particularly, embodiments of the present invention relate to a fast lock circuit for a phase lock loop.

BACKGROUND ART

A phase-locked loop (PLL) is a closed-loop feedback control system that maintains a generated signal in a fixed phase relationship to a reference signal. More importantly, the PLL is used widely in radio, telecommunications, computers and other electronic applications where it is desired to stabilize a generated signal or to detect signals in the presence of noise. For example, the PLL is widely used for synchronization purposes, in communication for coherent carrier tracking, bit synchronization and symbol synchronization for instance.

FIG. 1shows a fast lock circuit100for a PLL circuit. The fast lock circuit100uses the normal PLL phase frequency detector110and normal PLL charge pump130combination in the primary loop. Before the PLL circuit has achieved lock, a separate frequency detector120and a secondary charge pump140quickly charge or discharge the large loop filter capacitor150.

Moreover, when the PLL approaches lock, a deliberate dead zone built into the frequency detector120disables the secondary circuit. As a result, the phase frequency detector110and the charge pump130bring the PLL to lock. However, as the PLL approaches lock, the phase frequency detector produces a pump down signal on every period of the reference clock. The pump down signal resets the pump up signal from the phase frequency detector which slows down the net charging of the loop filter as shown inFIG. 2. As a result, the lock time increases as shown by the discontinuity of the filter charging curve ofFIG. 2.

An H-bridge circuit is commonly used in charge pumps in order to maintain a constant voltage across both the current source and the current sink in the charge pump of a PLL. However, when an H-bridge is used and both phase frequency detector pulses have the same value, the current is shunted to ground. As a result, during the time that the current is not steered onto the loop filter, the current is shunted to ground and wasted because it is no longer used to charge the loop filter. As a result, the lock time increases.

SUMMARY

Accordingly, there is a need for a fast lock circuit for a PLL circuit that supplies constant current to a large loop filter capacitor in order to improve the lock time. It will become apparent to those skilled in the art in view of the detailed description of the present invention that the present invention remedies the above mentioned needs.

One embodiment of the present invention utilizes a logic circuit coupled to the phase frequency detector, frequency detector and two charge pumps. The logic circuit outputs signals from the phase frequency detector circuit when the PLL is locked. The logic circuit outputs signals from the frequency detector circuit before the PLL has achieved lock. As a result, a constant current is supplied to a large loop filter capacitor before the PLL has achieved lock. Therefore, using the novel logic circuit to supply constant current charges the large loop filter capacitor continuously and avoids a slow down in charging the large loop filter capacitor. Accordingly, current is no longer wasted and the lock time of the circuit is improved.

More specifically, an embodiment of the present invention pertains to a fast lock circuit for a phase locked loop where the circuit includes a phase frequency detection circuit operable to detect the phase and frequency of a signal and in response thereto operable to adjust first and second control output signals from the phase frequency detector for adjusting the phase and frequency of the signal; a frequency detection circuit, coupled to the phase frequency detection circuit, operable to detect a frequency of the signal and in response thereto operable to adjust a first and a second control output signals from the frequency detector for adjusting the frequency of the signal. This embodiment further includes a logic circuit coupled to the phase frequency detection circuit and further coupled to the frequency detection circuit, outputting the first and the second phase frequency detector control output signals and the first and the second frequency detector control output based on the lock status of the phase locked loop; a first charge pump coupled to the logic circuit for increasing and decreasing a first current output in response to the plurality of control signals; and a second charge pump coupled to the frequency detection circuit for increasing and decreasing a second current output in response to the frequency detection circuit.

In one embodiment, the logic circuit outputs the first and the second phase control output signals when the phase locked loop is in lock. According to one embodiment, the logic circuit outputs the first and the second frequency control output signals before the phase locked loop achieves lock.

According to one embodiment, the lock circuit further includes a second logic circuit coupled to the first charge pump for controlling the first current output before the PLL achieves lock. In one embodiment, the second logic circuit is a programmable charge pump bits. In one embodiment, the first current is maximized before the phase locked loop achieves lock.

According to one embodiment, the lock circuit further includes a second logic circuit coupled to the first charge pump for increasing the amount of the first current output before the phase locked loop achieves lock.

DETAILED DESCRIPTION

A Fast Lock Circuit for a Phase Lock Loop

The preferred embodiment of the present invention utilizes logic circuit to supply constant current to a large loop filter capacitor before lock. Accordingly, the large loop filter capacitor is constantly charged without slowing down and as a result improves the lock time.

Referring now toFIG. 3, one embodiment of the present invention is shown. Circuit300comprises a phase frequency detection circuit310coupled to a first logic circuit320and a second logic circuit330. It is appreciated that even though the first logic circuit320and the second logic circuit330are shown as separate units, they may be implemented and integrated as a single working unit. The two logic circuits320and330are further coupled to a first charge pump340. The circuit300further comprises a frequency detection circuit360which is coupled to the first320and the second logic circuit330. The frequency detection circuit360is further coupled to a third logic circuit350and a second charge pump370. It is appreciated that even though the third logic circuit350is shown as a separate unit, it may be integrated to a single working unit with the first charge pump340or alternatively form a single working unit with logic units320and330. The first charge pump340and the second charge pump370output a first current342and a second current372respectively. As a result, the two currents342and372charge the large loop filter capacitor380.

An important part of a PLL is the phase frequency detector310whereby the phase of the local oscillator is compared to that of the reference signal. The two input signals to the phase frequency detector310are signals302and304respectively. The phase frequency detection circuit310outputs two signals, a first signal312and a second signal314respectively. The first signal312is the difference between the two input signals to the phase frequency detection circuit310, if signal302arrives before304. The second signal314is the difference between the two input signals to the phase frequency detection circuit310, if signal304arrives before302. Whichever signal between312and314is asserted first, will be reset by the other. The reason the second signal is asserted is to avoid a dead zone in the PLL.

Another important part of a PLL is the frequency detector360whereby the frequency of the local oscillator is compared to that of the reference signal. The two input signals to the frequency detection circuit360are signals302and304respectively. The frequency detector360outputs two signals, a third signal362and a fourth signal364. By activating one signal and deactivating another, the frequency detector360adjusts the frequency of the local oscillator during the lock phase only. In other words, during the lock phase, the third and fourth signals362and364have opposing values. For example, before lock, if the third signal362is active, the fourth signal364is inactive. Conversely, before lock if the third signal362is inactive, the fourth signal364is active. When the circuit is locked, both the third and the fourth signals362and364become inactive. The second charge pump370is coupled to the frequency detector360which in response to the third and the fourth signals362and364provide a positive or negative current output signal372.

The phase frequency detector310is coupled to the two logic circuits,320and330respectively. The frequency detector circuit360is also coupled to the two logic circuits,320and330respectively. The two logic circuits,320and330in turn are coupled to the first charge pump340. The logic circuits320and330operate differently during the lock phase and when the PLL has locked.

During the lock phase, as discussed above, the frequency detection circuit360adjust its outputs, the third362and the fourth364signal in order to adjust its frequency and approach lock. Therefore, as discussed above during the lock phase, the third362and the fourth364signal have opposing values, thereby increasing or decreasing the frequency of signal304to achieve lock. The logic circuits320and330are coupled to the frequency detection circuit360and relay the third signal362and the fourth signal364from the frequency detector360to the first charge pump340during the lock phase. Consequently, the output signal322of the logic circuit320is the third signal362during the lock phase. Similarly, the output signal332of the logic circuit330is the fourth signal364during the lock phase.

In other words, during the lock phase, when the third signal362is active, the output signal322is active and the fourth signal364and the output signal332are inactive. Furthermore, during the lock phase the first312and the second314signal are no longer connected to the first charge pump340.

As a result of mapping the third362and the fourth364signal to the output signals of the logic circuit320and330respectively, the second signal314will no longer slow down the charging of the large loop filter capacitor380even when it is activated because the second signal314is not mapped to the first charge pump340during the lock phase. Accordingly, a constant current is supplied which is the addition of the two output currents342and372from the two charge pumps340and370respectively, thereby charging up the large loop filter capacitor380. Consequently, the lock time is reduced.

In one embodiment of the present invention, the output current342can be maximized during the lock phase. Maximizing output current342during the lock phase is achieved by coupling the logic unit350to the frequency detector360and further coupled to the first charge pump340. As a result, the current is maximized and a constant current acts on the large loop filter capacitor380, thereby reducing the lock time.

Referring now toFIG. 4, the timing diagrams for one embodiment of the present invention before lock are shown. As discussed above, the two input signals302and304are input signals to the phase frequency detector310and the frequency detector360. The first signal312is the output signal from the phase frequency detector310where its output is the difference between the two input signals. Moreover, the phase frequency detector310outputs the second signal314which is used to avoid a dead zone.

Referring still toFIG. 4, the output signals from the frequency detector360are the third362and the fourth364signal respectively. Since the circuit has not achieved lock, the third362and the fourth364signals have opposing values. For example, the third362signal is active while the fourth364signal is inactive. The logic circuits320and330map the third362and the fourth364signal to its output signals,322and332respectively. As a result, the signal322, is active while the signal332is inactive. Therefore, despite the fact that the second signal314becomes active at the end of each cycle, the net charging rate of the large loop filter capacitor380is not reduced because the third362signal is mapped to the first charge pump340instead of the second signal314. As a result, a constant current is supplied which is the addition of the two output currents342and372from the two charge pumps340and370respectively, thereby charging up the large loop filter capacitor380. Consequently, the lock time is advantageously reduced compared to the conventional method.

Referring back toFIG. 3, when the PLL has locked, as discussed above, the third362and the fourth364signals are inactive. When in lock, the logic units320and330relay signals from the phase frequency detector310to the first charge pump340. In other words, when in lock the output signal322of the logic circuit320is the first signal312from the phase frequency detector310. Similarly, when in lock the output signal332of the logic circuit330is the second signal314from the phase frequency detector310. In other words, the two logic circuits320and330gate the outputs of the phase frequency detector310.

Referring now toFIG. 5A, one embodiment in accordance with the present invention for implementing the logic unit320is shown. It is appreciated that the logic circuit shown is for illustration and not for limitation. It is further appreciated that other electronic devices such as multiplexers may be used to implement the logic unit320.

In this example, the fourth signal364is inverted by inverter505and inputted to NAND gate515. The first signal312is also inputted to NAND gate515. The output signal517of the NAND gate515is inverted by inverter535, outputting inverted signal537. The third362signal is coupled to the Reset input to a D-Type Flip-Flop. The D input is tied to VDD, and the clock input is coupled to the reference clock302. The output527of the D-type Flip Flop525and the output537of the inverter535are gated to NOR gate545. The output547of the NOR gate545is inverted by inverter555. The output signal322of the inverter555is the output signal of the logic unit320.

As discussed above, before lock the third362and the fourth364signals have opposing values. For example, the third362signal is active while the fourth364signal is inactive. Accordingly, the output507of the inverter505is an active signal.

As discussed above, the first signal312is active before the second signal314is active. Furthermore, when the first signal312is inactive, the second signal314can be inactive as well. For illustration purposes it is assumed that the first signal312is active and the314signal is inactive. Inputting active signal507and active signal312to NAND gate515, outputs inactive signal517. Inactive signal517is inverted by inverter535, outputting active signal537. As discussed above, for illustration purposes it is assumed that the third362signal is active and the fourth364signal is inactive. Therefore, D-type Flip Flop525will not reset, and on every edge of the reference clock302, VDD will be latched to the Q output thereby activating signal527. Furthermore, gating active signal527and active signal537with NOR gate545, outputs inactive signal547. Inactive signal547is further inverted by inverter555, resulting in active signal322. As a result, before lock the third signal362is mapped to the output322of the logic unit320.

Referring now toFIG. 5B, one embodiment in accordance with the present invention for implementing logic unit330is shown. It is appreciated that the logic circuit shown is for illustration and not for limitation. It is further appreciated that other electronic devices such as multiplexers may be used to implement the logic unit330.

In this example, the third362signal is inverted by inverter510and inputted to NAND gate520. The second signal314is also inputted to NAND gate520. The output signal522of the NAND gate520is inverted by inverter540, outputting inverted signal542. The fourth364signal is coupled to the Reset input of D-type Flip Flop530. The D input is tied to VDD, and the clock input is coupled to the reference clock302. The output532of the D-type Flip Flop gate530and the output542of the inverter540are gated to NOR gate550. The output552of the NOR gate550is inverted by inverter560. The output signal332of the inverter560is the output signal of the logic unit330.

As discussed above, before lock, the third362and the fourth364signals have opposing values. For example, the third362signal is active while the fourth364signal is inactive. Accordingly, the output512of the inverter510is an inactive signal.

As discussed above, the first signal312is active before the second signal314is active. Furthermore, when the first signal312is inactive, the second signal314can be inactive as well. For illustration purposes as discussed above, it is assumed that the first signal312is active and the second314signal is inactive. Inputting inactive signal512and inactive second signal314to NAND gate520, outputs active signal522. Active signal522is inverted by inverter540, outputting inactive signal542as a result. As discussed above, for illustration purposes it is assumed that the third362signal is active and the fourth364signal is inactive. Therefore, D-type Flip Flop530is reset and outputs inactive signal532. Furthermore, gating inactive signal532and inactive signal542with NOR gate550, outputs active signal552. Active signal552is further inverted by inverter560, resulting in an inactive signal332. As a result, before lock the fourth signal364is mapped to the output332of the logic unit330.

As discussed and shown inFIGS. 5A and 5B, before lock when the third362signal is active and the fourth364signal is inactive, the logic units320and330output active322and inactive332signals respectively. Similarly, if the third362signal is inactive and the fourth364signal is active, the logic units320and330output inactive322and active332signals respectively.

The operation of the logic circuits320and330can also be described when in lock. As discussed before, when a circuit is in lock, the third362and the fourth364signals are both inactive. Referring now toFIG. 5A, the operation of the logic320circuit after lock is described.

The output507of the inverter505is active because the fourth364signal is inactive. Moreover, as discussed above, for illustration purposes it is assumed that the first signal312is active and the second signal314is inactive. Accordingly, NAND515gate acts as an inverter and outputs inactive signal517which is inverted by inverter535. The third362signal is coupled to the Reset input of D-type Flip Flop525. As a result, D-type Flip Flop525outputs inactive signal527which is gated with signal537to NOR gate545. As a result, NOR gate545outputs inactive signal547which is inverted by inverter555. Accordingly, the output signal322of the logic circuit320is active. As such, the first312signal is mapped to the output signal322during lock.

When signal312is inactive, the output517of NAND gate515is active. The active signal517is inverted by inverter535to generate inactive signal537. Signal362is inactive thereby inactivating signal527. Inactive signal527is gated with inactive signal537to NOR gate545. As a result NOR gate545outputs an active signal547which is inverted by inverter555to generate inactive signal322. As such, the first312signal is mapped to the output signal322when in lock.

Referring now toFIG. 5B, the operation of the logic330circuit after lock is described. The output512of inverter510is active because the third362signal is inactive. Moreover, as discussed above, for illustration purposes it is assumed that the first signal312is active and the second signal314is inactive. Accordingly, NAND520gate outputs active signal522which is inverted by inverter540. The fourth364signal is coupled to the Reset input of D-type Flip Flop530. As a result, D-type Flip Flop530outputs inactive signal532which is gated with signal542to NOR gate550. As a result, NOR gate550outputs active signal552which is inverted by inverter560. Accordingly, the output signal332of the logic circuit330is inactive. As such, the second314signal is mapped to the output signal332during lock.

When signal314is active, the output522of NAND gate520is inactive. The inactive signal522is inverted by inverter540to generate active signal542. Signal364is inactive thereby inactivating signal532. Inactive signal532is gated with active signal542to the NOR gate550to generate inactive signal552. Inactive signal552is inverted by inverter560to generate active signal332. As such, the second314signal is mapped to the output signal332during lock.

Therefore, before lock the logic units320and330relay output signals form the frequency detector circuit to the first charge pump. Conversely, during lock the logic units320and330relay output signals from the phase frequency detector circuit to the first charge pump. Consequently, large loop filter capacitor is continuously charged during lock, thereby improving the lock time.

Referring now toFIG. 6, programmable charge pump bits in the primary charge pump are used to maintain flexibility in PLL loop parameters such as closed loop bandwidth and long term jitter. It is desirable to maximize the current output342during the lock phase. Programmable charge pump bits may be used to control and vary the current. For example, when in lock as discussed above the third362and the fourth364signals are inactive. As a result, the output of the OR gates610,620and630are controlled by the programmable charge pump bits, ICP_X0, ICP_X1and ICP_X2. Activating and deactivating programmable charge pump bits varies the output current342.

Moreover, as discussed above, before lock, either the third signal362is active and the fourth signal364is inactive or the third signal is inactive and the fourth signal is active. As a result, transistors640,650and660are on, thereby maximizing the output current342before lock. Consequently, before lock the current is maximized, thereby charging the large loop filter capacitor380and speeding up the lock time.

Referring now toFIG. 7, a flow diagram700for a fast lock PLL circuit in accordance with one embodiment of the present invention is shown. At step710, an input signal is compared to a reference signal. At step720, in response to the comparing, a first and a second control signal are output. The first and the second control signals are operable to control and adjust a phase of the input signal by increasing/decreasing an output current from a charge pump. At step730, in response to the comparing, a third and a fourth control signals are output. The third and the fourth control signals are operable to control and adjust a frequency of the input signal by increasing/decreasing an output current from a charge pump. It is appreciated that in one embodiment, the charge pump for controlling the phase and the charge pump for controlling the frequency may be the same or separate. Furthermore, it is appreciated that in one embodiment, more than two charge pumps may be used.

At step740, in response to the comparing it is determined whether the phase lock loop circuit is in lock or if it is out of lock. At step750, in response to the determining of whether the phase lock loop circuit is in lock, the first and the second control signals are relayed to a first charge pump when the phase lock loop circuit is in lock. At step760, in response to the determining of whether the phase lock loop circuit is in lock, the third and the fourth control signals are relayed to the first charge pump before the phase lock loop achieves lock. At step770, the third and the fourth signals are relayed to a second charge pump regardless of whether the phase lock loop is in lock.

According to one embodiment, at step780an output current of the first charge pump is controlled when the phase lock loop is not in lock (e.g., using programmable charge pump bits). According to one embodiment, at step790the output current of the first charge pump is maximized before the phase lock loop circuit achieves lock such that the time required to achieve lock is reduced.

Accordingly, embodiments of the present invention reduce or eliminate a slow down in the charging of the large loop filter capacitor before lock by gating the frequency detector and the phase frequency detector with logic circuits as described. As a result, a constant supply of current is provided to the large loop filter capacitor. Therefore, supplying constant current eliminates a slow down in charging, thereby improving the lock time.

In the foregoing specification, embodiments of the invention have been described with reference to numerous specific details that may vary from implementation to implementation. Thus, the sole and exclusive indicator of what is, and is intended by the applicants to be, the invention is the set of claims that issue from this application, in the specific form in which such claims issue, including any subsequent correction. Hence, no limitation, element, property, feature, advantage or attribute that is not expressly recited in a claim should limit the scope of such claim in any way. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.