Semiconductor component

A semiconductor component contains two semiconductor bodies, which are spatially separated from one another and electrically interconnected. A compensation MOS field effect transistor is provided as the first semiconductor body, and a silicon carbide Schottky diode is provided as the second semiconductor body. Consequently, the semiconductor component can advantageously be produced significantly more compactly and more cost-effectively, since both the compensation MOS field-effect transistor and the silicon carbide Schottky diode contribute to a significant reduction of power loss.

BACKGROUND OF THE INVENTION

Field of the Invention

The invention relates to a semiconductor component having at least two semiconductor bodies that are spatially separate from one another and electrically connected to one another.

By way of example, in switched-mode power supplies and, in particular, in power factor controllers, in asymmetrical half-bridges, in drive converters for switched reluctance motors, a semiconductor power switch such as, for example, a MOS field-effect transistor, an IGBT or a bipolar transistor is connected up in series with, for example, a PN diode or a Schottky diode in such a way that the drain contact of the switch is at the same potential as the anode contact of the diode. Semiconductor components required for this are intended to be cost-effective and compact and also have low parasitic inductances.

In this case, it is customary to construct the circuit with discrete components or using surface mounted device (SMD) technology on a circuit board or to populate a DCB substrate with solderable semiconductor chips. An insulating substrate is also used in devices with a housing encapsulated by molding (for example TO-220, TO-247 or the like). In addition, split base plates (lead frames) with mutually insulated metal islands are also used. What is often problematic in this case is the severe evolution of heat in the individual semiconductor bodies, so that a compact construction is not possible.

SUMMARY OF THE INVENTION

It is accordingly an object of the invention to provide a semiconductor component that overcomes the above-mentioned disadvantages of the prior art and devices of this general type, which has at least two semiconductor bodies that are spatially separate from one another and electrically connected to one another.

With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor component. The semiconductor component has a common housing and at least two semiconductor bodies disposed spatially separate from one another and electrically connected to one another in the common housing. The two semiconductor bodies include a first semiconductor body being a compensation MOS field-effect transistor for at least one of relatively high voltages and powers and a second semiconductor body being a silicon carbide Schottky diode.

The semiconductor component according to the invention has at least two semiconductor bodies that are spatially separate from one another and electrically connected to one another in a common housing. A compensation MOS field-effect transistor for relatively high voltages and/or powers (such as, for example, a CoolMOS transistor) is provided as the first semiconductor body and a silicon carbide Schottky diode is provided as the second semiconductor body.

Consequently, semiconductor components according to the invention can advantageously be produced significantly more compactly and more cost-effectively, since both the compensation MOS field-effect transistor and the silicon carbide Schottky diode contribute to a significant reduction of power loss.

Preferably, the two semiconductor bodies are constructed and connected up to one another in such a way that together they form a power switch.

In one development of the invention, a third semiconductor body is additionally provided, which is electrically connected at least to one of the other two semiconductor bodies, and the three semiconductor bodies are connected up to one another in a manner forming a step-down converter or a step-up converter function. The third semiconductor body can be mounted just like integrated circuits generally by known soldering or adhesive bonding processes on the base plate or chip-on-chip on one of the other two semiconductor bodies.

In another development of the invention, the semiconductor component has, in addition to two semiconductor bodies that are spatially separate from one another and electrically connected to one another, a base plate, to which the first semiconductor body is fixed, and an elevation disposed on the base plate, to which elevation the second semiconductor body is fixed. The edge termination which lies in a planar manner on or near to the top side and is optimized for the reverse voltage to be blocked inherently prevents an upside down construction, since either with or without a dielectric passivation layer on the top side of the component, the equipotential area of the conductive base plate adversely influences the field distribution in or above the edge termination. This effect does not occur, however, as a result of the height offset of the two semiconductor bodies.

A higher degree of compactness can be obtained by virtue of the fact that the elevation has a base area that is less than the base area of the second semiconductor body fixed to it. Consequently, by way of example, the first semiconductor body can be disposed at least partly below the second semiconductor body.

In order to facilitate contact-making, the elevation has an electrically conductive contact-making area in the region of the second semiconductor body. Correspondingly, the second semiconductor body has an electrically conductive contact-making area in the region of the elevation. For mounting and contact-making of the second semiconductor body, the contact-making areas of the elevation and the second semiconductor body are then soldered to one another or electrically conductively adhesively bonded to one another.

Further contact-making is preferably effected on a further contact-making area disposed at a side of the second semiconductor body that is remote from the elevation. For further contact-making, a bonding connection is advantageously provided.

The second semiconductor body may have a passivation layer on the side facing the elevation. In the case of uncovering the contact window, that is to say the opening for the contact-making area, the passivation layer may be configured in such a way that the second semiconductor body is reliably aligned on the elevation before the soldering (or adhesive bonding) of the contact-making area.

Preferably, both the base plate and the elevation are produced from metal, in order to be able to produce a conductive connection between the two semiconductor bodies in a simple manner. In the case of a base plate produced from metal, the elevation can be realized by virtue of the fact that the elevation is formed by embossing during the stamping of the base plate. Thus, both the base plate and the elevation can be produced in one work operation.

The elevation preferably has a height relative to the base plate that amounts to a multiple of the width of the edge termination of the second semiconductor body. This results in reliable insulation of the two semiconductor bodies. For a semiconductor component configured for 600 V, the height is greater than 1 mm, for example.

The silicon carbide diode used according to the invention preferably has a solderable or conductive-adhesive-bondable anode contact metallization and a bondable cathode metallization, that is to say exactly interchanged relative to the metallizations that are customary nowadays. A particular advantage in the case of such a configuration is that the thermal resistance is significantly improved by the upside down construction, since the location where the maximum power loss occurs is the PN or metal/semiconductor junction and the latter, in the case of the construction according to the invention, lies nearer to the power loss sink at the, for example, soldered junction between second semiconductor body and base plate.

In particular, the diodes whose cathode is connected to an active potential and whose anode is connected to a quiescent potential are suitable, the base plate being connected to the respective anodes. Diodes of this type are optimized with regard to their electromagnetic compatibility. Furthermore, in the case of diodes of this type, a considerable reduction of the interference currents can be achieved by a cooling lug at anode potential especially in the case of step-down converters.

In all applications of the semiconductor components according to the invention, incorporation of an additional insulating layer is not necessary, nor do any insulation problems arise for the user in the case of the direct mounting of the device on a heat sink, as is the case with the use of, for example, a split base plate (lead frame).

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now to the figures of the drawing in detail and first, particularly, toFIG. 1thereof, there is shown a semiconductor component according to the invention with a base plate1, on which an elevation2is formed by embossing, for example. An injection-molded encapsulated housing50is shown diagrammatically by dashed lines and heavily cut-away for the sake of better clarity. In the exemplary embodiment, the elevation2is rectangular, but it may also have, in the same way, other forms, for example round or oval forms. A first semiconductor body3, for example a MOS field-effect transistor3(such as, for instance, a CoolMOS transistor) for relatively high voltages and relatively high powers, is soldered on the base plate1in addition to the elevation2, thereby producing an electrical contact between the MOS field-effect transistor and a terminal of the MOS field-effect transistor3. The other two terminals of the MOS field-effect transistor3are connected to a respective terminal contact4and5by bonds. The terminal contacts4and5are fixed to the base plate1in a manner electrically insulated from the latter, just like terminal contact6. Finally, terminal contact7is electrically conductively connected to the base plate1and fixed thereto.

The contacts of the MOS field-effect transistor3that are not directly connected to the base plate1are electrically connected to the terminal contacts4and5by bonding wires8and9. In this case, the terminal contact6is also provided for bonding to a second semiconductor body (not illustrated inFIG. 1) which is applied to the elevation2. In this case, a bonding wire10passes from the terminal contact6to the top side of the second semiconductor body which is illustrated in more detail in FIG.2.

A diode11is provided as the second semiconductor body11, which diode11has, in addition to the actual semiconductor structure12, a bondable contact-making area13at the top side thereof and also a solderable contact-making area14on a side facing the elevation2. In this case, the contact-making area14is soldered to the elevation2on the one hand for the purpose of electrical connection and on the other hand for the purpose of mechanical fixing to the elevation2. A passivation layer15(for example 40 μm polyimide) is situated around the solderable contact-making area14and has a cutout in the region of the solderable contact-making area14, in such a configuration that a contact window is produced which reliably aligns the diode11on the elevation2prior to soldering.

In this case, a height h of the elevation2is dimensioned such that it amounts to a multiple of a width of the edge termination r (not shown true to scale in the drawing). In this case, the height h is dimensioned as the distance between the underside of the passivation layer15and the top side of the metal base plate1.

An exemplary application for a semiconductor component according to the invention is illustrated inFIG. 3, where the second semiconductor body is formed as a diode16being a silicon carbide diode, with a cathode K as a first terminal and an anode A as a second terminal. The diode1is connected in series with the controlled path of a MOS field-effect transistor17and serves as a freewheeling diode in the exemplary embodiment. In this case, a load20is connected in parallel with the diode16, the series circuit containing the diode16and the transistor17being fed by a high-voltage voltage source21. When the anode A is connected to the base plate (lead frame) and the cathode K lies on the top side, the anode A is at a quiescent potential. Thus, an interference current is no longer coupled into the ground circuit via the relatively large capacitance18. Only a very much smaller capacitance19of the cathode K relative to the base plate serving as heat sink is at a time-variable potential. However, since the capacitance19of the cathode K is very small, coupling of interference currents into the ground circuit is reliably suppressed.

In another exemplary embodiment, shown inFIG. 4, three semiconductor bodies are combined in a single semiconductor component according to the invention. In this case, an integrated circuit22, a compensation MOS field-effect transistor for high powers and voltages (CoolMOS)23and also a silicon carbide Schottky diode24are combined to form a single semiconductor component. In this case, the integrated circuit22and the compensation MOS field-effect transistor23are applied to a base plate25having an elevation26(in accordance with the configurations in FIG.1and FIG.2), on which the silicon carbide diode24(in accordance withFIG. 2) is mounted. However, the integrated circuit22can also be provided on the switch23using chip-on-chip mounting.

Internally, the integrated circuit22, the compensation MOS field-effect transistor23and the silicon carbide diode24are connected up to one another in such a way that the integrated circuit22drives a gate G of the compensation MOS field-effect transistor23, whose source S is connected to one terminal of a voltage source and whose drain D is connected, with interposition of an inductor27, to the other terminal of a voltage source. In this case, the voltage source is formed from a bridge rectifier28fed with an AC voltage29. The drain terminal of the compensation MOS field-effect transistor23is additionally connected to the anode A of the silicon carbide diode24, whose cathode K is coupled to one pole of the supply voltage source via a smoothing capacitor30. In this case, the anode of the silicon carbide diode24is connected to the drain terminal of the compensation MOS field-effect transistor23via the base plate25in conjunction with the elevation26. Overall, the exemplary embodiment exhibits a configuration for power factor correction.

Specifically, IEC/EN 61 000-3-2 defines the limit values for the harmonics content for the input current for loads with an input power of more than 75 W. This applies to all devices that are supplied by the public power supply system. In devices with a diode rectifier and downstream intermediate circuit capacitor, a poor power factor results (around 0.6). The input current is severely non-sinusoidal (distorted in pulsed fashion). Accordingly, power factor correction is necessary.

Although a purely passive solution with a large input inductor achieves a slightly improved input current profile with a power factor of about 0.75, the requirements with regard to the harmonics content are complied with only to a limited extent.

Better results are made possible by active power factor correction on the basis of a step-up converter as is shown for example inFIG. 4. Apower factor of above 0.98 can be achieved with this configuration. In the realization of a configuration for active power factor correction, generally three semiconductor components are required: a power switch (for example the power MOS field-effect transistor or IGBT), the power diode and an integrated control unit. Hitherto, these three semiconductor components have usually been constructed in discrete form on a circuit board, and each semiconductor component had its own housing. As a result, the space requirement was considerable.

The configuration for power factor correction as shown inFIG. 4uses a semiconductor component according to the invention with a silicon carbide Schottky diode and a compensation MOS field-effect transistor for high powers and voltages (CoolMOS) on the basis of a step-up converter topology. However, the individual elements are combined in a single housing with suitable heat loss dissipation such as, for example, TO-220 (also Fullpack) or TO-247.

Through the interaction of various measures, it is possible to achieve a housing size reduction even for very high powers and/or very high voltages.

Thus, by way of example, a lower power loss is achieved by using a silicon carbide Schottky diode for high voltages. The heat arising as a result of the lower power loss thereof can be dissipated more easily. Furthermore, the use of a compensation MOS field-effect transistor for high voltages and powers affords a smaller space requirement, since this type of transistor requires a much smaller chip area compared with other power transistors. As a result, it is possible for the integrated circuit provided for control also to be concomitantly integrated into the common housing. Furthermore, a compensation MOS field-effect transistor has smaller capacitances, which in turn leads to smaller switching losses and, as a result, likewise reduces the heat loss that arises.

Finally, by optimally coordinating the individual components with one another, it is possible to reduce the overall system costs, reduce the volume, reduce the weight, reduce the power loss (smaller heat sinks required), reduce the mounting outlay and to increase the efficiency.