Voltage controlled oscillators and phase-frequency locked loop circuit using the same

A voltage controlled oscillator comprising first and second differential delay cells. The first differential delay cell has a first control voltage input terminal. The second differential delay cell is coupled to the first differential delay cell in a loop and has a second control voltage input terminal. The second voltage input terminal is disconnected from the first voltage control input terminal. The first voltage control input terminal receives a first voltage signal, and the second voltage control input terminal receives a second voltage signal different from the first voltage signal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a voltage controlled oscillator, and more particularly to a voltage controlled oscillator and voltage controlled oscillator applied in a phase-frequency locked loop circuit.

2. Description of the Related Art

A conventional voltage control ring oscillator is formed by n-stages delay cells coupled serially in a ring loop. All the delay cells are controlled by the same adjustable control voltage through their voltage control input terminals, and the oscillation frequency of the voltage controlled ring oscillator is thus obtained.FIG. 1shows a voltage-to-frequency transfer curve of a conventional voltage control ring oscillator. The slope of the voltage-to-frequency transfer curve is calculated to serve as the gain of the voltage control ring oscillator, as the equation E1:
Kvco=dF/dVC(E1)

wherein Kvco represents the gain of the voltage control ring oscillator, dVC represents a control voltage difference, and dF represents a frequency difference corresponding to the control voltage difference.

When a voltage control ring oscillator is applied in a phase locked loop (PLL) circuit, a smaller Kvco is better for weak phase jitter. Thus, a voltage control ring oscillator with smaller Kvco is desired for a phase locked loop circuit.

With greater requirements from high-speed electronic devices, the center frequency (Fc) of a voltage control ring oscillator is increased by decreasing the number (n) of the stages of delay cells, decreasing node capacitance (Cp) of the voltage control ring oscillator, or increasing current (Iss) of each delay cell.FIG. 2shows transfer curves of a 4-stage voltage control ring oscillator in different conditions. Referring toFIG. 2, from curve A to curve C, as the arrow10indicates, the center frequency (Fc) increases when n is decreased, Cp is decreased, and Iss is increased. However, the consumption current is increased, and Kvco also increases, undesirably. As shown InFIG. 2, curve A with the lowest center frequency Fc_L has the smallest Kvco, curve C with the highest center frequency Fc_H has the highest Kvco, and curve B with the medium enter frequency Fc_M has a medium Kvco.

Thus, for high-speed devices, a voltage control ring oscillator with a high center frequency and a small gain (Kvco) is desirable.

BRIEF SUMMARY OF THE INVENTION

An exemplary embodiment of a voltage controlled oscillator comprises first and second differential delay cells. The first differential delay cell has a first control voltage input terminal. The second differential delay cell is coupled to the first differential delay cell in a loop and has a second control voltage input terminal. The second voltage input terminal is disconnected from the first voltage control input terminal. The first voltage control input terminal receives a first voltage signal, and the second voltage control input terminal receives a second voltage signal different from the first voltage signal.

Another exemplary embodiment of a voltage controlled oscillator comprises first and second differential delay cells. The first differential delay cell has a first control voltage input terminal. The second differential delay cell is coupled to the first differential delay cell in a loop and has a second control voltage input terminal. The second control voltage input terminal is disconnected from the first voltage control input terminal. The first voltage control input terminal receives a first voltage signal with an adjustable level, and the second voltage control input terminal receives a second voltage signal with a fixed level.

Another exemplary embodiment of a voltage controlled oscillator comprises first and second differential delay cells. The first differential delay cell has a control voltage input terminal. The second differential delay cell is coupled to the first differential delay cell in a loop. The control voltage input terminal receives a voltage signal with an adjustable level; the delay time of the second differential delay cell is fixed.

An exemplary embodiment of a phase-frequency locked loop circuit comprises a voltage controlled oscillator, a frequency locked circuit, and a phase locked circuit. The voltage controlled oscillator is controlled by a first voltage signal and a second voltage signal and generates an output clock at an output terminal according to the first and second voltage signals. The frequency locked circuit receives a reference clock and the output clock and adjusts the first voltage signal according to the reference clock and the output clock. The phase locked circuit receives a data input signal and the output clock and adjusts the second voltage signal according to the data input signal and the output clock.

Another exemplary embodiment of a phase-frequency locked loop circuit comprises, a phase-frequency detector, a charge pump, a voltage controlled oscillator, and a frequency divider. The phase-frequency detector receives a reference clock and a feedback clock and generates an indication signal according to the difference between the reference clock and the feedback clock. The charge pump receives the indication signal, generates a first voltage signal, and adjusts a level of the first voltage signal according to the indication signal. The voltage controlled oscillator is controlled by the first voltage signal and generates an output clock at an output terminal. The frequency divider divides the frequency of the output clock to serve as the feedback for the phase-frequency detector. The voltage controlled oscillator comprises first and second differential delay cells. The first differential delay cell has a first control voltage input terminal for receiving the first voltage signal. The delay time of the first differential delay cell is determined by the adjusted level of the first voltage signal. The second differential delay cell is coupled to the first differential delay cell in a loop, and the delay time of the second differential delay cell is fixed.

DETAILED DESCRIPTION OF THE INVENTION

Voltage controlled oscillators are provided. In an exemplary embodiment of a voltage controlled oscillator inFIG. 3, a voltage controlled oscillator comprises n differential delay cells, that is the voltage controlled oscillator is an n-stage voltage controlled oscillator, wherein n≧2. In the embodiment ofFIG. 3, a 2-stage voltage controlled oscillator3is given as an example and comprises differential delay cells31and32. The differential delay cells31and32are serially coupled in a loop. InFIG. 3, one ring connection of the differential delay cells31and32is given as an example. Referring toFIG. 3, positive and negative output terminals (OUT+ and OUT−) of the differential delay cell31are respectively coupled to positive and negative input terminals (IN+ and IN−) of the differential delay cell32. Positive and negative output terminals (OUT+ and OUT−) of the differential delay cell32are respectively coupled to negative and positive input terminals (IN− and IN+) of the differential delay cell31. The differential delay cell31has a control voltage input terminal VIN1, and the differential delay cell32has a control voltage input terminal VIN2. The control voltage input terminals VIN1and VIN2are disconnected. The differential delay cell31is controlled by a voltage signal VC1received through the control voltage input terminal VIN1, and the differential delay cell32is controlled by a voltage signal VC2received through the control voltage input terminal VIN2. The voltage signal VC2is different from the voltage VC2, in other words, the control voltage input terminals VIN1and VIN2are separate.

In some embodiments, each of the voltage signals VC1and VC2has an adjustable level, so that the delay time of the differential delay cells31and32are adjustable.

In other some embodiments, the voltage signal VC1is at an adjustable level, and the voltage signal VC2is at a fixed level, so that the delay time of the differential delay cell31is adjustable, and that of the differential delay cell32is fixed.

In the embodiment ofFIG. 3, when the delay time of the differential delay cell32is fixed, the differential delay cell32receives the voltage signal VC2with a fixed level through the control voltage input terminal VIN2. In some embodiments, the differential delay cell32has no control voltage input terminal to receive a voltage signal with a fixed level, so that the differential delay cell32is not controlled by a voltage signal, and the delay time of the differential delay cell32is fixed. As show inFIG. 4, a voltage controlled oscillator4comprises differential delay cells41and42of different types. The differential delay cells41and42are serially coupled in a loop. The differential delay cell41has a control voltage input terminal VIN1which receives a voltage signal with an adjustable level, while the differential delay cell42does not have a control voltage input terminal. In other words, the differential delay cell42is not controlled by any voltage signal, and the delay time of the differential delay cell42is fixed.

The voltage controlled oscillator3ofFIG. 3may comprise three or more differential delay cells. In the following description, a voltage controlled oscillator with four differential delay cells (n=4) is given as an example. Referring toFIG. 5, a voltage controlled oscillator5comprises four differential delay cells51-54, that is, the voltage controlled oscillator5is a 4-stage voltage controlled oscillator. The differential delay cells51-54are serially coupled in a loop. Each of the differential delay cells51-54has a control voltage input terminal. A control voltage input terminal VIN1of the differential delay cell51is disconnected from control voltage input terminals VIN2-VIN4of the differential delay cells52-54. The control voltage input terminal VIN1receives a voltage signal VC1with an adjustable level. Each of the control voltage input terminals VIN2-VIN4receive a voltage signal VC2with a fixed level. Thus, the delay time of the differential delay cell51is adjustable, and the delay time of the differential delay cells52-54are fixed.

According to the embodiment ofFIG. 5, in the 4-stage voltage controlled oscillator5, only one differential delay cell51(m=1) is controlled by a voltage signal with an adjustable level. The ratio of the adjustable delay time to the total delay time becomes less for the 4-stage voltage controlled oscillator5. Thus, the range of the adjustable frequency becomes less, so that the gain (Kvco) of the voltage controlled oscillator5is decreased, and the center frequency thereof is not changed. In the embodiment ofFIG. 5, because n=4 and m=1, compared with the Kvco of the transfer curve C, the Kvco of the voltage controlled oscillator5is decreased to one fourth of the Kvco of the transfer curve C, as shown by the transfer curve C-1inFIG. 6.

In some embodiments, the voltage controlled oscillator3ofFIG. 3may comprise two differential delay cells whose delay time is adjustable and at least one differential delay cell whose delay time is fixed. In the following description, a voltage controlled oscillator with two differential delay cells whose delay time is fixed among four differential delay cells (n=4) is given as an example. Referring toFIG. 7, a voltage controlled oscillator7comprises four differential delay cells71-74, that is, the voltage controlled oscillator7is a 4-stage voltage controlled oscillator. The differential delay cells71-74are serially coupled in a loop. In the embodiment ofFIG. 7, each of the differential delay cells71-74has a control voltage input terminal. Control voltage input terminals VIN1and VIN3of the differential delay cells71and73receive a voltage signal VC1with an adjustable level. Control voltage input terminals VIN2and VIN4of the differential delay cells72and74receive a voltage signal VC2with a fixed level. Thus, the delay time of the differential delay cells71and73is adjustable, and the delay time of the differential delay cells72and74are fixed.

According to the embodiment ofFIG. 7, in the 4-stage voltage controlled oscillator7, two differential delay cells71and73(m=2) are controlled by voltage signals with adjustable levels. Because n=4 and m=2, compared with the Kvco of the transfer curve C, the Kvco of the voltage controlled oscillator7is decreased to half ( 2/4=½) of the Kvco of the transfer curve C, as shown by the transfer curve C-2inFIG. 6.

In the embodiments, the voltage controlled oscillator7can provide balance I/Q phases from the outputs terminals of the differential delay cells71and73. According to the embodiment ofFIG. 7, in an n-stage voltage controlled oscillator (n>2, and n is an even number), when differential delay cells with adjusted delay time and differential delay cells with fixed delay time are alternately coupled, the n-stage voltage controlled oscillator can provide balance I/Q phases.

In some embodiments, the differential delay cells72and74may not have control voltage input terminals to receive a voltage signal with a fixed level, so that the differential delay cells72and74are not controlled by a voltage signal, and the delay time of the differential delay cells72and74is also fixed.

The above voltage controlled oscillator comprising two differential delay cells whose delay time is adjustable can be applied in a phase-frequency locked loop circuit. Referring toFIG. 8, a phase-frequency locked loop circuit8comprises a voltage controlled oscillator81, a frequency locked circuit82, and a phase locked circuit83. The voltage controlled oscillator81is controlled by a voltage signal VC1and a VC2. The voltage controlled oscillator81generates an output clock CKOUTat an output terminal POUTaccording to the voltage signals VC1and VC2. The frequency locked circuit82receives a reference clock CKREFand the output clock CKOUTand adjusts the voltage signal VC1according to the reference clock CKREFand the output clock CKOUT. The phase locked circuit83receives a data input signal DINand the output clock CKOUTand adjusts the voltage signal VC2according to the data input signal DINand the output clock CKOUT.

Referring toFIG. 9, the voltage controlled oscillator81comprises n differential delay cells. InFIG. 9, the voltage controlled oscillator81comprises four differential delay cells91-94, that is, the voltage controlled oscillator81is a 4-stage voltage controlled oscillator. The differential delay cells91-94are serially coupled in a loop. Each of differential delay cells91-94has a control voltage input terminal. A control voltage input terminal VIN1of the differential delay cell91receives a voltage signal VC1with an adjustable level. A control voltage input terminal VIN4of the differential delay cell94receives a voltage signal VC2with an adjustable level. Control voltage input terminals VIN2and VIN3of the differential delay cells92and93receive a voltage signal VC3with a fixed level. Thus, the delay time of the differential delay cells91and94is adjustable, and the delay time of the differential delay cells92and93are fixed.

In the voltage controlled oscillator81, the output terminals of the differential delay cell94correspond to the output terminal POUT, and the input terminals of the differential delay cell91correspond to the output terminal POUT. In other words, the differential delay cell94is the last stage to the output terminal POUT, while the differential delay cell91is the next stage to the output terminal POUT.

Referring toFIG. 8, the frequency locked circuit82comprises a frequency divider821, a frequency detector822, a charge pump823, and a capacitor824. The frequency divider821divides the frequency of the output clock CKOUT. The frequency detector822receives the reference clock CKREFand the divided output clock CKOUTand generates a indication signal SC1according to the difference between the reference clock CKREFand the divided output clock CKOUT. The charge pump823receives the indication signal SC1and adjusts the level of the voltage signal VC1of the differential delay cell91according to the indication signal SC1. The capacitor824is coupled to the charging pump823and stores the adjusted level of the voltage signal VC1.

Referring toFIG. 8, the phase locked circuit83comprises a phase detector831and a charge pump832. The phase detector831receives the data input signal DINand the output clock CKOUTand generates a indication signal SC2according to the difference between the data input signal DINand the output clock CKOUT. The charge pump832receives the indication signal SC2and adjusts the level of the voltage signal VC2of the differential delay cell94according to the indication signal SC2.

As described above, because the frequency loop requires a longer path for slow response, the voltage signal VC1of the next stage differential delay cell91to the output terminal POUTis adjusted for frequency locking. Moreover, because the phase loop requires a shorter path for fast response, the voltage signal VC2of the last stage differential delay cell94to the output terminal POUTis adjusted for phase locking.

The above voltage controlled oscillator comprising one differential delay cell whose delay time is adjustable and another differential delay cell whose delay time is fixed can be applied in a phase-frequency locked loop circuit as shown inFIGS. 10 and 11. Referring toFIG. 10, a phase-frequency locked loop circuit10with two loops comprises a voltage controlled oscillator11, a frequency locked circuit12, and a phase locked circuit13. The frequency locked circuit12may comprise a frequency divider121, a frequency detector122, a charge pump123, and a capacitor124. The frequency locked circuit12performs similar operations to those of the frequency locked circuit82inFIG. 8and generates a voltage signal. The phase locked circuit13comprises a phase detector131and a charge pump132. The phase locked circuit13performs similar operations to those of the phase locked circuit83inFIG. 8and generates a voltage signal VC1. The voltage signal generated by the frequency locked circuit12couples to the voltage signal VC1through a resistor14, and the coupled voltage signal VC1is provided to control the voltage controlled oscillator11.

In some embodiments, the voltage controlled oscillator11may comprises the differential delay cells31and32, as shown inFIG. 3, wherein the output terminals of the differential delay cell32correspond to a output terminal POUTof the voltage controlled oscillator11. The voltage signal VC1is used to control the differential delay cell31through the control voltage input terminal VIN1. The voltage signal VC1has an adjustable level, so that the delay time of the differential delay cell31is adjustable. The differential delay cell32receives a voltage signal VC2with a fixed level through the control voltage input terminal VIN2, and the delay time of the differential delay cell32is fixed.

In other some embodiments, the voltage controlled oscillator11may comprises the differential delay cells41and42, as shown inFIG. 4, wherein the output terminals of the differential delay cell42correspond to an output terminal POUTof the voltage controlled oscillator11. The voltage signal VC1is used to control the differential delay cell41. The voltage signal VC1has an adjustable level, so that the delay time of the differential delay cell41is adjustable. The differential delay cell42does not have a control voltage input terminal for receiving a voltage signal, and the delay time of the differential delay cell42is fixed.

Referring toFIG. 11, a phase-frequency locked loop circuit110with single loop comprises a voltage controlled oscillator111, a phase-frequency detector112, a charge pump113, and a frequency divider114. The phase-frequency detector112receives a reference clock CKREFand a feedback clock CKFBand generates an indication signal SC according to the difference between the reference clock CKREFand the feedback clock CKFB. The charge pump113receives the indication signal SC and generates a voltage signal VC1. The charge pump113adjusts a level of the voltage signal VC1according to the indication signal SC. The voltage controlled oscillator111is controlled by the voltage signal VC1and generates an output clock CKOUTat an output terminal POUT. The frequency divider114divides the frequency of the output clock CKOUTto serve as the feedback CKFBfor the phase-frequency detector112. The phase-frequency locked loop circuit110may further comprises a resistor115and a capacitor116. One terminal of the resistor115is coupled between the charge pump113and the voltage controlled oscillator111. The resistor is coupled between the other terminal of the resistor115and a ground. The resistor115and the capacitor116compose a low-pass filter.

In some embodiments, the voltage controlled oscillator111may comprises the differential delay cells31and32, as shown inFIG. 3, wherein the output terminals of the differential delay cell32correspond to the output terminal POUT. The voltage signal VC1is used to control the differential delay cell31through the control voltage input terminal VIN1. The voltage signal VC1has an adjustable level, so that the delay time of the differential delay cell31is adjustable. The differential delay cell32receiving a voltage signal VC2with a fixed level through the control voltage input terminal VIN2, and the delay time of the differential delay cell32is fixed.

In other some embodiments, the voltage controlled oscillator111may comprises the differential delay cells41and42, as shown inFIG. 4, wherein the output terminals of the differential delay cell42correspond to the output terminal POUT. The voltage signal VC1is used to control the differential delay cell41. The voltage signal VC1has an adjustable level, so that the delay time of the differential delay cell41is adjustable. The differential delay cell42does not have a control voltage input terminal for receiving a voltage signal, and the delay time of the differential delay cell42is fixed.

According to the embodiments, the voltage controlled oscillators provide a high center frequency and a small gain (Kvco). Moreover, the voltage controlled oscillators can be applied in a phase-frequency locked loop circuit. Through two differential delay cells with adjustable delay times, the frequency locked circuit and the phase locked circuit respectively operate.

In above embodiments, the connections between n differential delay cells in an n-stage voltage controlled oscillator are given as an example. According to different applications, n differential delay cells in an n-stage voltage controlled oscillator can be coupled serially in a loop by other types of connection.