Semiconductor package having through holes

Disclosed is a semiconductor package. The semiconductor package is configured to form a plurality of through holes for forming a through silicon via at once using a sawing device used for wafer sawing instead of a separate laser drilling equipment or a deep reactive ion etching (DRIE) equipment. Accordingly, the semiconductor package saves fabricating time and increases fabrication yield, saves costs for a laser drilling equipment or a DRIE equipment, and prevents various defects generated in an inner portion of a through hole in the case of using the laser drilling equipment or the DRIE equipment.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a semiconductor package and a fabricating method thereof.

2. Description of the Related Art

Recently, portable electronic devices such as a mobile phone, a PMP and others have been required to achieve high-functionality, miniaturization, light-weight and price reduction. According to the tendency, a semiconductor package mounted in portable electronic devices has been also developed in a type of a 3D semiconductor package to be more innovative and price-competitive. The 3D-semiconductor package has been used by a semiconductor stacking technology using a through silicon via (TSV). The semiconductor stacking technology using the TSV is a technology indicating that semiconductor dies or semiconductor packages are perpendicularly stacked. The semiconductor stacking technology leads to reduction of the length between the semiconductor die and the semiconductor package, and thus achieves high-functionality and miniaturization of semiconductor packages.

Now, the semiconductor package provided with the through silicon via is fabricated in a thin wafer level. The through silicon via is formed by filling through holes formed on a wafer with conductive materials. The through holes are formed by using a laser drilling method or a deep reactive ion etching (DRIE) method.

However, the laser drilling method performs laser drilling in proportion to the number of through holes and leads to long time for fabrication and high cost. Additionally, the laser drilling method also leads to formation of a through hole in an inaccurate position, because it is difficult for the laser drilling method to accurately form the through hole in a desired position. Side wall bowing, silicon debris or the like are caused by the laser drilling method when a through hole is formed on a wafer, resulting in generating defects of the through silicon via formed in an inner portion of the through hole afterwards. Accordingly, the laser drilling method results in the reduction of yield of semiconductor packages.

Further, a deep reactive ion etching (DRIE) method leads to slope angle indicating that a side wall of the through hole is sloped, side wall roughness indicating that the side wall becomes rough and step coverage indicating that the side wall of the through hole is stepped, resulting in generating defects of the through silicon via formed on the through hole afterwards. Accordingly, the DRIE method also results in the reduction of yield of semiconductor packages.

The present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings.

SUMMARY OF THE INVENTION

Disclosed is a semiconductor package. The semiconductor package is configured to form a plurality of through holes for forming a through silicon via at once using a sawing device used for wafer sawing instead of a separate laser drilling equipment or a deep reactive ion etching (DRIE) equipment. Accordingly, the semiconductor package saves fabricating time and increases fabrication yield, saves costs for a laser drilling equipment or a DRIE equipment, and prevents various defects generated in an inner portion of a through hole in the case of using the laser drilling equipment or the DRIE equipment.

DETAILED DESCRIPTION OF THE INVENTION

Referring toFIG. 1, a wafer on which a semiconductor package is formed according to an embodiment of the present invention is shown as a schematic plan view.

As shown inFIG. 1, a plurality of semiconductor packages10are formed on a wafer1made of a silicon material. The semiconductor packages10independently separated by a sawing process according to a scribing line5of the wafer1are used for various electric and electronic fields. The semiconductor packages10can be fabricated in a wafer level state. Hereinafter, the structure and fabricating method of one semiconductor package10of the semiconductor packages10in the wafer level state will be explained.

Referring toFIG. 2A, the semiconductor package10ofFIG. 1is shown as a plan view. Referring toFIG. 2B, a cross-sectional view is shown, taken along a2B-2B line ofFIG. 2. Referring to2C, a cross-sectional view is shown, taken along a2C-2C line ofFIG. 2A. Referring to2D, an enlarged cross-sectional view is shown, taken along a2D-2D line ofFIG. 2A. Referring toFIG. 2E, a bottom surface view of a semiconductor die is shown, prior to formation of a fourth electrode.

Referring toFIGS. 2A to 2E, a semiconductor package10according to the embodiment of the present invention includes a semiconductor die100and a photosensitive layer pattern200and a through silicon via300.

Referring toFIG. 2B, the semiconductor die100may include an approximately planar first surface100aand a second surface100bin opposite to the first surface100a. Further, the semiconductor die100includes a third surface100cconnecting the first surface100awith the second surface100band approximately perpendicular to the first and second surfaces100aand100b.

The semiconductor die100includes a plurality of bond pads110formed on the first surface100a. The bond pads110are arranged in a line along an approximately periphery of the first surface100a.

The semiconductor die100includes a passivation layer120formed on the first surface100a. The passivation layer120is formed to cover the first surface100aof the semiconductor die100and expose the bond pads110. The passivation layer120includes a lateral surface120aformed approximately on the same plane surface as the third surface100cof the semiconductor die100. The passivation layer120covers the first surface100aof the semiconductor die100. As a result thereof, the first surface100aof the semiconductor die100on which an active area (not shown) is formed can be protected. The passivation layer120may be made of any one material selected from an oxide film, a nitride film and a polyimide or equivalent materials, but not limited thereto. The passivation layer120may be formed by patterning or etching a portion of the bond pads110to be exposed after deposition to the first surface100aof the semiconductor die100.

Referring toFIGS. 2B to 2D, the semiconductor die100further includes a first through hole130perpendicularly penetrating the bond pads110and the first surface100aof the semiconductor die100. The semiconductor die100further includes a second through hole140penetrating the passivation layer120and the first surface100aof the semiconductor die100between adjacent bond pads110of the bond pads110. The first through hole130and the second through hole140are provided in a trench shape connected to each other. This is the reason that the first through hole130and the second through hole140, as shown inFIG. 2A, are formed by sawing the semiconductor die100at a predetermined depth in a direction from the first surface100ato the second surface100balong a straight sawing line (SL) formed to pass through respectively the bond pads110. More particularly, the first through holes130and second through holes140are portions of trenches formed in the first surface100aof the semiconductor die100by sawing along the sawing lines (SL). Accordingly, first through holes130and second through holes140are sometimes called first trench portions and second trench portions, respectively.

The sawing for forming the first and second through holes130and140may be formed using any one sawing device selected from blade, laser and bevel. The sawing device is advantageous to enable the first through hole130to have a wider width (for example, 2 mil) and a deeper depth (for example, 50 μm) in comparison with a laser drilling device. A through silicon via300, formed on the first through hole130having the width and the depth, to be explained below has a larger diameter and a longer length. As a result thereof, there can be increased a high aspect ratio of a semiconductor package defined by a ratio of the diameter and the length of the through silicon via300. Further, the sawing device may be used for the sawing of the wafer1. As a result thereof, there can be saved fabricating cost of the semiconductor package, in comparison with the use of a high-priced laser drilling equipment or a deep reactive ion etching (DRIE) equipment for forming through holes, alternatively a sawing device used for conventional sawing of a wafer. When the blade or the bevel is used as the sawing device, it is preferable for the blade or the bevel to have the width narrower than that of the bond pads110.

Meanwhile, the sawing using the sawing device is performed to pass through a plurality of bond pads110and thus an active area between adjacent bond pads110is not formed. In other words, the active area is formed in a central portion on the first surface100aof the semiconductor100. As a result thereof, the damage to active area can be prevented by sawing the semiconductor die100at a predetermined depth in a direction from the first surface100ato the second surface100b.

As described above, the first through hole130on which the through silicon via300to be explained below is formed by using the sawing device. Accordingly, a plurality of first through holes130can be formed at once. As a result thereof, there can saved time for forming a plurality of first through holes130, saved whole time for fabricating a semiconductor package and increased fabrication yield of the semiconductor package.

The photosensitive layer pattern200formed on an upper portion of the passivation layer120and an inner portion of the second through hole140includes a pattern hole220exposing the first through hole130and a portion110bof the bond pads110connecting with the first through hole130. The photosensitive layer pattern200reinforces the strength of the semiconductor die100having resistance to external force weakened by forming the first and second through holes130and140. As a result thereof, the damage to the semiconductor package100can be prevented in a semiconductor package fabricating process. Further, as shown inFIG. 2D, the photosensitive layer pattern200is formed on the second through hole140positioned close between the adjacent first through holes130, so as to mutually electrically insulate the adjacent through silicon vias300when the through silicon vias300are formed on the first through hole130. The photosensitive layer pattern200is formed by coating a photosensitive material on the first surface100aof the semiconductor die100, particularly an upper portion of the passivation layer120with any one method selected from spin coating, spray coating, radius coating, printing and laminating, and by patterning the photosensitive material through a photo process.

The through silicon via300can be formed by extending inside the first through hole130from the photosensitive layer pattern200via the pattern hole220. The through silicon via300is used as electrical connection wiring when other semiconductor packages or a plurality of semiconductor dies are stacked on the semiconductor package10. As a result thereof, there can be formed a thin and high-functionality semiconductor package. According to the embodiment of the present invention, the through silicon via300, sometimes called the through silicon hole300, is protruded on a surface of the photosensitive layer pattern200. However, the through silicon via300can be formed on the same planar surface as the photosensitive layer pattern200, and can be formed at the height lower than the surface of the photosensitive layer pattern200.

The through silicon via300may concretely include a first electrode300a, a second electrode300band a third electrode300c. The through silicon via300may further include a fourth electrode300dformed on the second surface100bof the semiconductor die100.

The first electrode300aformed on the surface of the photosensitive layer pattern200enables the semiconductor package10to electrically couple to other semiconductor packages when the other semiconductor packages are stacked on the semiconductor package10.

The second electrode300bformed in an inner portion of the pattern hole220of the photosensitive layer pattern200is electrically coupled to the first electrode300a. Further, the second electrode300bis electrically coupled to the bond pads110.

The third electrode300cformed in an inner portion of the first through hole130is electrically coupled to the second electrode300b. Further, the third electrode300cis electrically coupled to the bond pads110. The third electrode300c, as shown inFIG. 2E, may have a rectangular planar shape. This is the reason that the sawing for forming the first through hole130in which the third electrode300cis formed is performed along a straight sawing line (SL) formed to pass through the bond pads110respectively. As such, the third electrode300chas a rectangular planar shape and thus the third electrode300cmay have relatively larger planer size, in comparison with a circular planar shape of the third electrode300c, which is formed in the first through hole130formed by using a laser drilling method. Accordingly, when the fourth electrode300dcoupling with the third electrode300cis formed, a size of contacting the third and fourth electrodes300cand300dis increased. As a result thereof, there can be improved electrical conductivity. Further, the third electrode300cused as an align key for forming the fourth electrode300denables the fourth electrode300dto be easily aligned when the fourth electrode300dis formed on the third electrode300c, which has larger size of the rectangular planar shape, rather than that of a circular planar shape.

The first, second and third electrodes300a,300band300care integrally formed. Further, The first, second and third electrodes300a,300band300care formed by filling the first through hole130with a conductive material using any one method selected from physical vapor deposition, chemical vapor deposition, electroplating and electroless plating. The conductive material may be formed by any one material selected from copper (Cu), gold (Au), silver (Ag) and aluminum (Al) or equivalent materials, but not limited thereto.

The fourth electrode300dis formed on the second surface100bof the semiconductor die100to be electrically coupled to the third electrode300c, and thus the fourth electrode300denables the semiconductor package10to be electrically coupled to other semiconductor packages when the semiconductor package10is stacked on the other semiconductor packages. The fourth electrode300dmay be formed by depositing a conductive material on the second surface100bof the semiconductor die100using sputtering or plating. The conductive material may be the one used to form the first, second and third electrodes300a,300band300c.

The semiconductor package10according to the embodiment of the present invention is configured to form the first through hole130and the second through hole140, using a sawing device such as blade or bevel used for sawing the wafer1instead of a laser drilling equipment or a DRIE equipment. As a result thereof, there can be saved costs for the laser drilling equipment or the DRIE equipment and reduced various defects such as side wall bowing and step coverage generated in an inner portion of a through hole by means of the laser drilling equipment of the DRIE equipment.

Further, the semiconductor package10according to the embodiment of the present invention is configured to form the first through hole130, the second through hole140, specifically a plurality of first through holes in which the through silicon via300is formed at once using the sawing device. As a result thereof, there can be saved fabricating time for semiconductor packages and increased fabrication yield of the semiconductor package, rather than a case using the laser drilling equipment or the DRIE equipment.

Further, the semiconductor package10according to the embodiment of the present invention is configured to form a first through hole130having a wider width and a deeper depth using the sawing device and a through silicon via300in the first through hole130. As a result thereof, there can be increased a high aspect ratio of the semiconductor package defined by a ratio of a diameter and a length of the through silicon via300.

Further, the semiconductor package10according to the embodiment of the present invention is configured to form a photosensitive layer pattern200on a semiconductor die100to reinforce the strength of the semiconductor die100weakened by the first through hole130and the second through hole140. As a result thereof, there can be improved resistance of the semiconductor die100to external force. Particularly, the semiconductor package10according to the embodiment of the present invention is configured to form a photosensitive layer pattern200on the second through hole140positioned between the first through holes130adjacent to the photosensitive layer pattern200to electrically insulate adjacent through silicon vias300formed in the adjacent first through holes130. As a result thereof, electric short of the adjacent through silicon vias300can be prevented.

Referring toFIG. 3, a fabricating method of a semiconductor package according to an embodiment of the present invention is shown as a flow chart.

Referring toFIG. 3, the fabricating method of the semiconductor package according to the embodiment of the present invention includes a preparing semiconductor die operation (S1), a forming first and second through holes operation (S2), a forming photosensitive layer pattern operation (S3), a forming through silicon via operation (S4), a grinding semiconductor die operation (S5) and a forming fourth electrode operation (S6).

Referring toFIGS. 4A and 4B, the preparing semiconductor die operation (S1) is shown as a plan view and a cross-sectional view.

Referring toFIGS. 4A and 4B, the preparing semiconductor die operation (S1) includes preparing the semiconductor die100provided with a planar first surface100a, a planar second surface100b′ in opposite to the first surface100a, a plurality of bond pads110formed on the first surface100aand a passivation layer120exposing a plurality of bond pads110.

The semiconductor die100may include a third surface100cconnecting the first surface100awith the second surface100b′ and approximately perpendicular to the first surface100aand the second surface100b′. The bond pads110have rectangular planar shapes. The bond pads110may be arranged in a line along a periphery of the first surface100aof the semiconductor die100. The passivation layer120is formed by covering the first surface100aof the semiconductor die100and exposing a portion110aof the bond pads110. The passivation layer120includes a lateral surface120aapproximately formed in the same planar shape as the third surface100cof the semiconductor die100. The passivation layer120covers the first surface100aof the semiconductor die100. As a result thereof, the first surface100aof the semiconductor die100on which an active area (not shown) is formed can be protected. The passivation layer120may be made of any one material selected from an oxide film, a nitride film and a polyimide or equivalent materials, but not limited thereto. The passivation layer120may be formed by patterning or etching a portion of the bond pads110to be exposed after deposition to the first surface100aof the semiconductor die100.

Referring toFIGS. 5A and 5B, the forming first and second through holes operation (S2) ofFIG. 3is shown as a plan view and a cross-sectional view of a semiconductor die.

Referring toFIGS. 5A and 5B, the forming first and second through holes operation (S2) performs sawing of the semiconductor die100along a sawing line (SL) formed to respectively pass through the bond pads110at a predetermined depth in a direction from the first surface100ato the second surface100b′, to form the first and second through holes130and140.

The sawing for forming the first and second through holes130and140may be formed by using any one sawing device selected from blade, laser and bevel. The sawing device is advantageous to enable the first through hole130to have a wider width (for example, 2 mil) and a deeper depth (for example, sop) in comparison with a laser drilling device. A through silicon via300formed in the first through hole130having the width and the depth to be described below may have a larger diameter and a longer length. As a result thereof, there can be increased a high aspect ratio of a semiconductor package defined by a ratio of the diameter and the length of the through silicon via300. Further, the sawing device may be used for the sawing of the wafer1. As a result thereof, there can be saved fabricating costs of the semiconductor package, in comparison with a case of using a laser drilling equipment or a DRIE equipment used for forming a through hole, separately from the sawing device used for the conventional sawing of a wafer. When the sawing device is used as blade or bevel, it is preferable for the blade or the bevel to have a width narrower than that of the bond pads110.

The depth (D) of the first through hole130formed by the sawing of the semiconductor die100may be ⅓ or ⅔ of the thickness (T) of the semiconductor die100. When the depth (D) of the first through hole130is less than ⅓ of the thickness (T) of the semiconductor die100, the second surface100b′ of the semiconductor die100is mostly grinded so as to expose a third electrode300cof a through silicon via300formed in the first through hole130and thus the semiconductor die100becomes excessively thinner. As a result thereof, there can be spatially limited in forming elements on the semiconductor die100. Further, the depth (D) of the first through hole130is more than ⅔ of the thickness (T) of the semiconductor die100, the semiconductor can be damaged in a fabricating process of a semiconductor package because of resistance to external force of the semiconductor excessively weakened.

Meanwhile, the sawing using the sawing device is formed to pass through the bond pads110, and thus an active area is not formed between the adjacent bond pads110. In other words, the active area is formed in a central portion on the first surface100aof the semiconductor die100. As a result thereof, the damage of the active area generated by sawing the semiconductor die100at a predetermined depth in a direction from the first surface100ato the second surface100b′ of the semiconductor die100can be prevented.

As such, the forming first and second through holes operation (S2) can form the first through hole130and the second through hole140using the sawing device, specifically, a plurality of first through holes130in which the through silicon via300is formed, at once. As a result thereof, there can be saved fabricating time for semiconductor packages and increased fabrication yield of the semiconductor packages.

Referring toFIGS. 6A-6Band7A-7C, the forming photosensitive layer pattern operation (S3) ofFIG. 3is shown as a plan view and a cross-sectional view of a semiconductor die.

The forming photosensitive layer pattern operation (S3) includes forming a photosensitive layer200aon the whole first surface100aof the semiconductor die100provided with the first through hole130and the second through hole140, as shown inFIGS. 6A and 6B, and forming a photosensitive layer pattern200by patterning the photosensitive layer200aso as to expose the first through hole130and a portion110bof the bond pads110connecting with the first through hole130, as shown inFIGS. 7A and 7B.

Concretely, the photosensitive layer200ais formed by coating a photosensitive material with any one method selected from spin coating, spray coating, radius coating, printing and laminating on the whole first surface100aof the semiconductor die100provided with the first through hole130and the second through hole140.

The photosensitive layer pattern200is formed by patterning the photosensitive layer200athrough a photo process including exposure, developing and curing so as to expose the first through hole130and the portion110bof the bond pads110. Accordingly, the photosensitive layer pattern200is concretely formed on an upper portion of the passivation120and an inner portion of the second through hole140, and includes a pattern hole220exposing the first through hole130and the portion110bof the bond pads110connected with the first through hole130. The photosensitive layer pattern200reinforces the strength of the semiconductor die100having resistance to external force weakened by forming the first and second through holes130and140. As a result thereof, the damage of the semiconductor die100generated in the fabricating process of the semiconductor package can be prevented. Further, the photosensitive layer pattern200is formed on the second through hole140positioned between the adjacent first through holes130, so as to mutually electrically insulate the adjacent through silicon vias300when the through silicon via300is formed in the first through hole130.

Referring toFIGS. 8A and 8B, the forming through silicon via operation (S4) ofFIG. 3is shown as a plan view and a cross-sectional view of a semiconductor die.

Referring toFIGS. 8A and 8B, the forming through silicon via operation (S4) fills the first through hole130with a conductive material to form a through silicon via300.

The conductive material is filled by using any one method selected from physical vapor deposition, chemical vapor deposition, electroplating and electroless plating. The through silicon via300may be formed by extending inside the first through hole130from the photosensitive layer pattern200via the pattern hole220. The through silicon via300serves as electric coupling wiring when other semiconductor packages are stacked to the semiconductor package10or a plurality of semiconductor dies are stacked, and thus a thin and high-functionality semiconductor package can be formed. According to the embodiment of the present invention, the through silicon via300protruded on a surface of the photosensitive layer pattern200can be formed on the same surface as the photosensitive layer pattern200and can be formed at a height lower than the surface of the photosensitive layer pattern200.

The through hole300may concretely include a first electrode300a, a second electrode300band a third electrode300c. When the first electrode300aformed on the surface of the photosensitive layer pattern200stacks other semiconductor packages on the semiconductor package10, the first electrode300aelectrically couples the semiconductor package10to other semiconductor packages. The second electrode300bformed in an inner portion of the pattern hole220of the photosensitive layer pattern200is electrically coupled to the first electrode300a. Further, the second electrode300bis electrically coupled to the bond pads110. The second electrode300cformed in an inner portion of the first through hole130is electrically coupled to the second electrode300b. Further, the third electrode300cis electrically coupled to the bond pads110. The planar shape of the third electrode300cmay be rectangular (seeFIG. 9A). This is the reason that the sawing for forming the first through hole130provided with the third electrode300cis formed along a straight sawing line (SL) formed to respectively pass through the bond pads110. Accordingly, when a fourth electrode300dcoupled with the third electrode300cis formed, the size contacting the third electrode300cto the fourth electrode300dis increased, and thus electric conductivity between the vias can be improved. Further, as the third electrode300cserves as an align key forming the fourth electrode300d, an align process for the fourth electrode300dcan be facilitated when the third electrode300chaving larger size of the rectangular planar shape, in comparison with the circular planar shape, is formed on the fourth electrode300d. The first electrode300a, the second electrode300band the third electrode300cmay be integrally formed.

Referring toFIGS. 9A and 9B, the grinding semiconductor die operation (S5) ofFIG. 3is shown as a bottom view and a cross-sectional view of the semiconductor die.

Referring toFIGS. 9A and 9B, the grinding semiconductor die operation (S5) includes grinding the second surface100b′ of the semiconductor die100to expose the through silicon via300, concretely the third electrode300c.

The grinding of the second surface100b′ of the semiconductor die100may be performed by using chemical etching, mechanical etching, laser irradiating method or equivalent methods, but not limited thereto. The second surface100b′ of the semiconductor die100is grinded so as to form the planar second surface100bto which the third electrode300cis exposed.

Referring toFIGS. 10A and 10B, the forming fourth electrode operation (S6) ofFIG. 3is shown as a bottom view and a cross-sectional view of a semiconductor die.

Referring toFIGS. 10A and 10B, the forming fourth electrode operation (S6) includes forming the fourth electrode300delectrically coupled with the third electrode300cexposed to the second surface100bof the semiconductor die100.

The fourth electrode300dis formed by depositing a conductive material on the second surface100bof the semiconductor die100so as to electrically couple to the third electrode300c. The deposition of the conductive material may be performed by sputtering, plating or equivalent methods, but not limited thereto. The fourth electrode300denables the semiconductor package10to be electrically coupled to other semiconductor packages when the semiconductor package10is stacked to the other semiconductor packages.

As such, a fabricating method of a semiconductor package according to the embodiment of the present invention includes forming the first through hole130and the second through hole140using a sawing device such as blade or bevel used for the sawing of the wafer1instead of a laser drilling equipment or a DRIE equipment. As a result thereof, there can be saved cost for the laser drilling equipment or the DRIE equipment and reduced various defects such as side wall bowing and step coverage generated in an inner portion of a through hole when the through hole is formed by using the laser drilling equipment or the DRIE equipment.

Further, a fabricating method of a semiconductor package according to the embodiment of the present invention includes forming the first through hole130and the second through hole140using the sawing device, particularly a plurality of first through holes130in which the through silicon via300is formed, using the sawing device. As a result thereof, there can be saved fabricating cost of the semiconductor package and increased fabrication yield of the semiconductor package, rather than a case of using the laser drilling equipment or the DRIE equipment.

Further, the fabricating method of the semiconductor package according to the embodiment of the present invention forms the first through hole130having a wider width and a deeper depth using the sawing device to form the through silicon via300in the first through hole130. As a result thereof, there can be increased a high aspect ratio of the semiconductor package defined by a ratio of a diameter and a length of the through silicon via300.

Further, the fabricating method of the semiconductor package according to the embodiment of the present invention forms the photosensitive layer pattern200on the semiconductor die100to reinforce the strength of the semiconductor die100having a strength weakened by forming the first through hole130and the second through hole140, and thus the semiconductor die100has high resistance to external force. More particularly, the semiconductor package10according to the embodiment of the present invention is configured to form the photosensitive pattern200in the second through hole140positioned between the adjacent first through holes130and electrically insulate the adjacent through silicon vias300formed on the adjacent first through holes130. As a result thereof, electric short of the adjacent through silicon vias300can be prevented.

Then, the semiconductor package of another embodiment will be explained, wherein the semiconductor package according to one embodiment of the present invention is applied.

Referring toFIG. 11, the semiconductor package is shown as a cross-sectional view according to another embodiment of the present invention.

As shown inFIG. 11, the semiconductor package600according to another embodiment of the present invention includes a circuit board400, a stacked semiconductor package500including a plurality of first conductive bumps510, a plurality of second conductive bumps610and a plurality of solder balls620. The semiconductor package600may be formed by stacking the circuit board400and the stacked semiconductor package500on each other and by coupling the circuit board400to the stacked semiconductor package500electrically by means of the second conductive bump610. Additionally, the semiconductor package600may be electrically coupled to an external device by means of the solder ball620.

The circuit board400may include a first circuit pattern411formed on an upper surface of the board400, a second circuit pattern412formed on a lower surface thereof and a via hole413electrically coupling the first circuit pattern411to the second circuit pattern412.

Additionally, the circuit board400may further include a solder mask414covering a predetermined portion of the first and second circuit patterns411and412. The solder mask414covers the portion of the first and second circuit patterns411and412. As a result thereof, oxidation or corrosion of the first and second circuit patterns411and412can be prevented, due to excessive exposure to the outside. Additionally, the solder mask414is formed between the second conductive bumps610formed on the first circuit pattern411and between the solder balls620formed on the second circuit pattern412. As a result thereof, electric short can be prevented between the second conductive bump610and the solder ball620. The solder mask414may be formed through a process of exposing and then developing thermosetting resin or UV-curable resin, but not limited thereto.

The stacked semiconductor package500is formed by stacking a plurality of semiconductor packages10and by coupling the packages10electrically to each other by means of the first conductive bump510. Specifically, the stacked semiconductor package500is formed by enabling one semiconductor package10and the other semiconductor package10, being arranged in side by side, to be electrically coupled to each other through the first conductive bump510formed between through silicon vias300of the semiconductor packages10.

The semiconductor package10constituted in the stacked semiconductor package500is explained in detail in one embodiment of the present invention, thus the explanation will be omitted. Meanwhile,FIG. 11shows the stacked semiconductor package500is formed by stacking two semiconductor packages10, however, the semiconductor package500may be formed by stacking at least three semiconductor packages10. Accordingly, the number of semiconductor packages10is not limited thereto, which are stacked in the embodiment of the present invention.

The first conductive bump510constituted in the stacked semiconductor package500is formed between the through silicon vias300of one and the other semiconductor packages10. The first conductive bump510electrically couples a plurality of semiconductor packages10to each other. The first conductive bump510may be made of solder, gold, silver or an equivalent material, but not limited thereto.

The second conductive bump610, formed on the first circuit pattern411, is electrically coupled to the first circuit pattern411. The second conductive bump610is electrically coupled to the through silicon via300of one semiconductor package10faced to the circuit board400of the stacked semiconductor package500. Thus, the second conductive bump610couples the circuit board400to the stacked semiconductor package500electrically. The second conductive bump610may be made of the same material as that of the first conductive bump510.

The solder ball620, formed on the second circuit pattern412, is electrically coupled to the second circuit pattern412. The solder ball620is electrically coupled to an external device, and thus the circuit board400transmits/receives an electrical signal to/from the external device. The solder ball620may be made of Sn/Pb and Leadless Sn or an equivalent material, but not limited thereto.

As such, the semiconductor package600according to another embodiment of the present invention is formed by stacking the circuit board400and the stacked semiconductor package500to each other. As a result thereof, capacity and functionality of the semiconductor package can be increased due to various applications to a semiconductor package field.

Additionally, the semiconductor package600according to another embodiment of the present invention can reduce the mounted area, in comparison with the area mounted on an external device by separating the circuit board400and the stacked semiconductor package500respectively.

The semiconductor package of still another embodiment will be explained, wherein the semiconductor package is applied according to one embodiment of the present invention.

Referring toFIG. 12, the semiconductor package is shown as a cross-sectional view according to still another embodiment.

As shown inFIG. 12, the semiconductor package700according to still another embodiment of the present invention is formed by stacking the circuit board400and the stacked semiconductor package500to each other and by coupling the circuit board400to the stacked semiconductor package500electrically by means of the second conductive bump610. The semiconductor package700, having the same configuration as the semiconductor package600, is further equipped with an underfill710in comparison with the semiconductor package600shown inFIG. 11. Accordingly, the same numerals will be indicated for the same configuration and repetitive explanation will be omitted. Now, the underfill710will be explained in detail.

The underfill710may be formed between one semiconductor package10and the other semiconductor package10of the stacked semiconductor package500. In this time, the underfill710may surround the first conductive bump510. The underfill710maintains stable connection between the first conductive bump510and one semiconductor package10, and between the first conductive bump510and another semiconductor package10thermally or mechanically.

Additionally, the underfill710may be formed between one semiconductor package10faced to the circuit board400of the stacked semiconductor package500and the circuit board400. In this time, the underfill710may surround the second conductive bump610formed between one semiconductor package10and the circuit board400. The underfill710maintains stable connection between the second conductive bump610and one semiconductor package10, and between the second conductive bump610and the circuit board400thermally or mechanically.

The underfill710may be made of epoxy resin, thermosetting resin and polymer or an equivalent material, but not limited thereto.

As such, the semiconductor package700according to another embodiment of the present invention is equipped with the underfill710and formed by stacking the circuit board400and the stacked semiconductor package500to each other. As a result thereof, binding force between the stacked semiconductor package500and the circuit board400can be increased in comparison with the semiconductor package600shown inFIG. 11.

The semiconductor package of still another embodiment will be explained, wherein the semiconductor package is applied according to one embodiment of the present invention.

Referring toFIG. 13, the semiconductor package is shown as a cross-sectional view according to still another embodiment of the present invention.

As shown inFIG. 13, the semiconductor package800according to still another embodiment of the present invention is formed by stacking the circuit board400and the stacked semiconductor package500to each other and by coupling the circuit board400to the stacked semiconductor package500electrically by means of the second conductive bump610. The semiconductor package800, having the same configuration as the semiconductor700, is further equipped with an encapsulant810in comparison with the semiconductor package700shown inFIG. 12. Accordingly, the same numerals are indicated for the same configuration, and repetitive explanation will be omitted. Then, the encapsulant810will be explained in detail.

The encapsulant810surrounds completely the stacked semiconductor package500formed on the circuit board400. In other words, the encapsulant810surrounds completely one semiconductor package10and the other semiconductor package10of the stacked semiconductor package500. The encapsulant810protects the one semiconductor package10and the other semiconductor package10from the outside. As a result thereof, binding force between the circuit board400and the stacked semiconductor package500can be increased.

As such, the semiconductor package800according to another embodiment of the present invention is equipped with the encapsulant810and formed by stacking the circuit board400and the stacked semiconductor package500to each other. As a result thereof, binding force between the stacked semiconductor package500and the circuit board400can be increased and the stacked semiconductor package500can be protected from the outside simultaneously, in comparison with the semiconductor package700shown inFIG. 12.

The semiconductor package of still another embodiment will be explained, wherein the semiconductor package is applied according to one embodiment of the present invention.

Referring toFIG. 14, the semiconductor package is shown as a cross-sectional view according to another embodiment of the present invention.

As shown inFIG. 14, the semiconductor package900according to still another embodiment of the present invention is formed by stacking the circuit board400and the stacked semiconductor package500to each other and electrically coupling the circuit board400to the stacked semiconductor package500by means of the second conductive bump610. The semiconductor package900, having the same configuration as the semiconductor package800, is formed by enabling the encapsulant910to expose a portion of the semiconductor package10, in comparison with the semiconductor package800shown inFIG. 13. Accordingly, the same numerals are indicated for the same configuration and repetitive explanation is omitted. Then, the encapsulant910will be explained in detail.

The encapsulant910, surrounding one semiconductor package10and the other semiconductor package10of the stacked semiconductor package500, exposes one surface of the other semiconductor package10being outermost from the circuit board400in a vertical direction. The encapsulant910protects one semiconductor package10and the other semiconductor package10from the outside and increases binding force between the circuit board400and the stacked semiconductor package500. Additionally, the encapsulant910exposes one surface of the other semiconductor package10. As a result thereof, thermal performance of the semiconductor package900can be increased.

As such, the semiconductor package900, equipped with the encapsulant910exposing a portion of the stacked semiconductor package500, is formed by stacking the circuit board400and the stacked semiconductor package500to each other. As a result thereof, thermal performance can be increased in comparison with the semiconductor package800.

The semiconductor package of still another embodiment will be explained, wherein the semiconductor package is applied according to one embodiment of the present invention.

Referring toFIG. 15, the semiconductor package is shown as a cross-sectional view according to still another embodiment of the present invention.

As shown inFIG. 15, the semiconductor package1100according to still another embodiment of the present invention is formed by stacking the semiconductor die1000on the circuit board400and the stacked semiconductor package500, and by coupling the semiconductor die to the circuit board400and the stacked semiconductor package500electrically through a third conductive bump1110. The semiconductor package, having the same configuration as the semiconductor package900, is further equipped with the semiconductor die1000in comparison with the semiconductor package900shown inFIG. 14. Accordingly, the same numerals are indicated for the same configuration and repetitive explanation is omitted. Now, the semiconductor die1000will be explained in detail.

The semiconductor die1000is electrically coupled to the through silicon via300exposed to an upper portion of the stacked semiconductor package500through the third conductive bump1110. As a result thereof, the semiconductor die1000can be electrically coupled to the stacked semiconductor package500and the circuit board400.

As such, the semiconductor package1100is formed by stacking not only the circuit board400and the stacked semiconductor package500stacked to each other but the semiconductor die1000. As a result thereof, capacity and functionality of the semiconductor package can be increased, in comparison with the semiconductor packages600,700,800and900shown inFIGS. 11 to 14.

A fabricating method of the semiconductor package will be explained, wherein the semiconductor package is shown inFIG. 15.

Referring toFIG. 16, the fabricating method of the semiconductor package ofFIG. 15is shown as a flow chart.

As shown inFIG. 16, the fabricating method of the semiconductor package includes a preparing circuit board operation (S11), a connecting circuit board with stacked semiconductor package operation (S12), a dispensing underfill operation (S13), a performing encapsulation operation (S14) and a connecting semiconductor die operation (S15).

Referring toFIGS. 17A to 17E, the fabricating method of the semiconductor package ofFIG. 16is explained as cross-sectional views of the semiconductor packages.

Referring toFIG. 17A, the preparing circuit board operation (S11) includes preparing the circuit board400, which includes a first circuit pattern411formed on an upper surface of the circuit board, a second circuit pattern412formed on a lower surface thereof, a via hole413coupling the first and second circuit patterns411,412electrically to each other and a solder mask414covering a predetermined portion of the first and second circuit patterns411,412.

The circuit board400is explained in detail inFIG. 11, and thus it will be omitted.

Referring toFIG. 17B, the connecting circuit board with stacked semiconductor package operation (S12) includes preparing the stacked semiconductor package500and then coupling the package500to the circuit board400.

The stacked semiconductor package500is formed by stacking a plurality of semiconductor packages10and by coupling the semiconductor packages10electrically by means of the first conductive bump510. Specifically, the stacked semiconductor package500is formed by enabling one semiconductor package10and the other semiconductor package10, arranged in side by side to be electrically coupled to each other through the first conductive bump510formed between through silicon via300of one and the other semiconductor packages10. The semiconductor package10constituted in the stacked semiconductor package500is explained in detail in one embodiment of the present invention and thus the explanation will be omitted. Meanwhile,FIG. 17Bshows the stacked semiconductor package500is formed by stacking two semiconductor packages10, however, the stacked semiconductor package500may be formed by stacking at least three semiconductor packages10. Accordingly, the number of the semiconductor packages10is not limited thereto, which are stacked in the embodiment of the present invention.

The connecting circuit board with stacked semiconductor package operation (S12) includes stacking the above-constructed stacked semiconductor package500on the circuit board400, and electrically coupling the stacked semiconductor package500to the circuit board400by connecting the second conductive bump610between the through silicon via300of one semiconductor package10faced to the circuit board400of the stacked semiconductor package500and the first circuit pattern411of the circuit board400.

Referring toFIG. 17C, the dispensing underfill operation (S13) includes dispensing the underfill710to spaces positioned between a plurality of semiconductor packages10of the stacked semiconductor package500and between the stacked semiconductor package500and the circuit board400.

Specifically, the dispensing underfill operation (S13) includes dispensing the underfill710to surround the first conductive bump510positioned between the semiconductor packages10using a dispenser (not shown) and to surround the second conductive bump610positioned between one semiconductor package10faced to the circuit board400of the semiconductor packages10and the circuit board400. The underfill710maintains stable connection between the first conductive bump510and one semiconductor package10and between the first conductive bump510and the other semiconductor package10thermally or mechanically. Additionally, the underfill710maintains stable connection between the second conductive bump610and one semiconductor package and between the second conductive bump610and the circuit board400thermally or mechanically.

Referring toFIG. 17D, the performing encapsulation operation (S14) includes forming the encapsulant910by performing encapsulation to surround the stacked semiconductor package500on the circuit board400.

Specifically, the performing encapsulation operation (S14) includes forming the encapsulant910by performing encapsulation to surround the stacked semiconductor package500on the circuit board400, and to expose one surface of the other semiconductor package10being outermost from the circuit board400in a vertical direction. The encapsulant910protects one semiconductor package10and the other semiconductor package10from the outside and increases bonding force between the circuit board400and the stack semiconductor package500. Additionally, the encapsulant910exposes one surface of the other semiconductor package10. As a result thereof, thermal performance can be increased of the stacked semiconductor package500electrically coupled to the circuit board400.

Referring toFIG. 17E, the connecting semiconductor die operation (S15) includes stacking the semiconductor die1000on the circuit board400and the stacked semiconductor package500electrically coupled to each other and electrically coupling the semiconductor die1000to the circuit board400and the stacked semiconductor package500through the third conductive bump1110.

Specifically, the connecting semiconductor die operation (S15) includes stacking the semiconductor die1000on an upper portion of the other semiconductor package10, sometimes call the outermost semiconductor package, whose one surface is exposed, and electrically coupling the stacked semiconductor package500to the semiconductor die1000through the third conductive bump1110contacted to the through silicon via300of the other semiconductor package10, whose one surface is exposed.

Additionally, the connecting semiconductor die operation (S15) can include bonding the solder ball620on the second circuit pattern412of the circuit board400to connect the semiconductor die1000, the stacked semiconductor package500and the circuit board400, stacked and electrically coupled to each other, to external devices.

The semiconductor package1100fabricated by the above-described method is formed by stacking not only the circuit board400and the stacked semiconductor package500, stacked to each other, but also the semiconductor die1000. As a result thereof, capacity and functionality of the semiconductor package can be increased.

This disclosure provides embodiments of the present invention. The scope of the present invention is not limited by these embodiments. Numerous variations, whether explicitly provided for by the specification or implied by the specification, such as variations in structure, dimension, type of material and manufacturing process, may be implemented by one skilled in the art in view of this disclosure.