Electronic device compensating different characteristics of serially connected storage devices and storage device included therein

An electronic device includes an embedded storage device and an application processor. The embedded storage device is connected to directly communicate with a removable storage device which processes a packet having a first characteristic. The embedded storage device processes a packet having a second characteristic. The application processor is connected to directly communicate with the embedded storage device, but not directly connected to the removable storage device. The application processor processes a packet having a third characteristic. The embedded storage device compensates at least one of the first characteristic or the second characteristic, such that at least one of a first packet of the first characteristic received from the removable storage device or a second packet of the second characteristic in the embedded storage device is provided to the application processor according to the third characteristic.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2016-0121638, filed on Sep. 22, 2016, in Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

BACKGROUND

The example embodiments of the inventive concepts relate to communication between electronic circuits or devices, and more particularly, relate to configurations and operations that manage and/or process a packet and information for interface between electronic circuits and/or devices.

Various types of electronic devices are used. An electronic device performs a function(s) according to an operation of one or more electronic circuits included therein. The electronic device provides service(s) to a user by performing the function(s). The electronic device may operate solely to provide the service(s). Some electronic devices may communicate with other electronic device(s) or external electronic circuit(s) to provide the service(s).

An operation processor and a storage device are some examples of electronic devices. For example, the operation processor may communicate (e.g., interface) with the storage device to provide a data storage service to a user. The operation processor may exchange a data/information/signal/and/or packet with the storage device while interfacing with the storage device. The operation processor and the storage device may employ an interface protocol to communicate with each other.

Configurations and manners of interface of electronic devices have evolved. For example, various circuit configurations and various methods of operating circuits have been developed to implement storage devices having a large capacity. However, in some cases, changing circuit configurations and methods of operating a circuit to satisfy, or improve on, a user's demand or desirability may cause an increase in cost, configuration complexity, and/or circuit area.

SUMMARY

The example embodiments may provide an electronic device which is capable of satisfying a user's demand with low complexity. The electronic device according to the example embodiments may provide configurations and operations for compensating different characteristics of a plurality of devices.

In some example embodiments, an electronic device may include an embedded storage device and an application processor. The embedded storage device may be connected with and directly communicate with a removable storage device which may process a packet having a first characteristic. The embedded storage device may process a packet having a second characteristic. The application processor may be connected to and directly communicate with the embedded storage device, but may not be directly connected with the removable storage device. The application processor may process a packet having a third characteristic. The embedded storage device may compensate at least one of the first characteristic or the second characteristic such that at least one of a first packet of the first characteristic received from the removable storage device or a second packet of the second characteristic in the embedded storage device is provided to the application processor according to the third characteristic.

In some example embodiments, a storage device may include a controller, a nonvolatile memory, and a compensation circuit. The controller may directly communicate with each of, or at least one of a host device and an external storage device that are not directly connected with each other. The controller may process a packet having a first characteristic. The nonvolatile memory may store or output data according to control of the controller. The compensation circuit may compensate difference among the first characteristic, a second characteristic, and a third characteristic, such that a packet of the second characteristic received from the host device, which may process the packet having the second characteristic, is transferred to the external storage device according to the third characteristic of a packet, which may be processed by the external storage device, or is processed by the controller according to the first characteristic.

In some example embodiments, an electronic system may include a plurality of electronic devices, the plurality of electronic devices being configured to connect to one another and being configured to communicate with one another, the plurality of electronic devices including an interfacing electronic device, a designated electronic device, and a tail electronic device, the tail electronic device directly connected to one of the plurality of electronic devices and not directly connected to another of the plurality of electronic devices. The electronic system may include a processor directly connected to the tail electronic device and being configured to communicate with the interfacing electronic devices, the interfacing electronic device being configured to process a packet having a first characteristic, the designated electronic device configured to process a packet having a second characteristic, the processor being configured to process a packet having a third characteristic. The designated electronic device is further configured to compensate at least one of the first characteristic or the second characteristic, such that at least one of a first packet of the first characteristic received from the interfacing electronic device or a second packet of the second characteristic from the designated electronic device is provided to the processor according to the third characteristic.

According to the example embodiments, design/manufacturing costs and configuration complexity of the electronic device may decrease. Accordingly, the example embodiments may bring some economic benefit while satisfying some of a user's demand. In some example embodiments, different operation manners of a plurality of devices having different characteristics may be compensated. Accordingly, implementing one communication channel, instead of implementing a plurality of communication channels, for the plurality of devices may be possible. Design and/or manufacturing costs and/or configuration complexity of the electronic device may further decrease, or be improved.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Below, example embodiments of the inventive concepts will be described in detail and clearly with reference to accompanied drawings to such an extent that those (hereinafter referred to as “ordinary ones”) skilled in the art can readily implement the inventive concepts.

FIG. 1is a block diagram illustrating a storage system that includes storage devices serially connected according to some example embodiments. A storage system1000may include an operation processor device1100, a first storage device1300, and a second storage device1400.

The operation processor device1100may perform various arithmetic operations and/or logic operations to manage and process overall operations of the storage system1000. For example, the operation processor device1100may be implemented in a special-purpose circuit (e.g., field programmable gate arrays (FPGA), application specific integrated circuits (ASICs), and/or the like) including one or more processor cores, or may be implemented in a system on chip (SoC). For example, the operation processor device1100may include a general-purpose processor, a special-purpose processor, and/or an application processor. The operation processor device1100may be a processor itself, or may be an electronic device or system including a processor. Likewise, the term “processor” may include an operation processor, an application processor, and/or other electronic device.

The first storage device1300may include one or more nonvolatile memories1310and a controller1320. The second storage device1400may include one or more nonvolatile memories1410and a controller1420.

The nonvolatile memories1310and1410may include memory areas for storing data. For example, the nonvolatile memories1310and1410may include one or more of various nonvolatile memories such as a NAND-type flash memory, a phase-change random access memory (PRAM), a magneto-resistive RAM (MRAM), a resistive RAM (RRAM), a ferro-electric RAM (FRAM), and/or the like.

The controllers1320and1420may control overall operations of the storage devices1300and1400respectively. To this end, each of, or at least one of the controllers1320and1420may include one or more processor cores, and a buffer memory. For example, the controllers1320and1420may control the nonvolatile memories1310and1410respectively such that data is stored in the nonvolatile memories1310and1410or data stored in the nonvolatile memories1310and1410is output.

The operation processor device1100may provide a command, a query, and/or a request to the storage devices1300and1400. The operation processor device1100may exchange data with the storage devices1300and1400. In some example embodiments, a command, a query, a request, and data may be transferred in unit of packet, but this is not to limit the inventive concepts. A transfer unit may be variously changed or modified.

For example, when the operation processor device1100provides a write command and write data to the storage devices1300and1400, the storage devices1300and1400may store write data in the nonvolatile memories1310and1410. For example, when the operation processor device1100provides a read command to the storage devices1300and1400, the storage devices1300and1400may output read data, which is stored in the nonvolatile memories1310and1410, to the operation processor device1100.

The operation processor device1100may be a host device that receives a storage service from the storage devices1300and1400. The “host” may mean a device that receives a service from other device(s). A user of the storage system1000may receive a storage service according to an operation of the operation processor device1100.

According to the example embodiments, the operation processor device1100and the storage devices1300and1400may be serially connected. Referring toFIG. 1, the operation processor device1100may be connected to directly communicate with the first storage device1300through ports PORT0and PORT1a. Further, the first storage device1300may be connected to directly communicate with the second storage device1400through ports PORT1band PORT2. However, the operation processor device1100may not be directly connected with the second storage device1400. For example, such connection between the operation processor device1100and the storage devices1300and1400may be understood as the topology of a “chain” structure or a “daisy-chain” structure.

For example, the controller1320may be configured to directly communicate with the operation processor device1100to exchange read data and write data with the operation processor device1100. For example, the controllers1320and1420may be configured to directly communicate with each other to exchange read data and write data with each other. On the other hand, the controller1420may not be directly connected with the operation processor device1100.

Unlike a configuration illustrated inFIG. 1, in some cases, the operation processor device1100may be directly connected with both the storage devices1300and1400. For example, the storage devices1300and1400may be connected in parallel with the operation processor device1100. However, in this case, the operation processor device1100may include multiple ports that are connected with both the storage devices1300and1400. In addition, the operation processor device1100may include communication circuits to communicate with the storage devices1300and1400and peripheral circuits that control and drive the communication circuits.

On the other hand, according to the example embodiment illustrated inFIG. 1, the operation processor device1100may not directly communicate with the second storage device1400. Thus, the operation processor device1100may only include the port PORT0connected with the first storage device1300, a communication circuit for communicating with the first storage device1300, and a peripheral circuit that controls and drives the communication circuit. Instead, the first storage device1300may include the port PORT1bconnected with the second storage device1400, a communication circuit for communicating with the second storage device1400, and a peripheral circuit that controls and drives the communication circuit.

Thus, according to the example embodiment illustrated inFIG. 1, a configuration of the operation processor device1100may become simplified, and an area occupied by the operation processor device1100may be reduced. In addition, design/manufacturing costs of the operation processor device1100may decrease. In addition to such economic benefits, employing two storage devices1300and1400may provide larger storage capacity in comparison to employing one storage device. Thus, a user's demand may be satisfied.

In such the example embodiment, a configuration of the first storage device1300may become complicated somewhat. However, in many cases, the operation processor device1100may operate at a speed of several or tens of gigahertz (GHz), and the first storage device1300may operate at a speed of tens to hundreds of megahertz (MHz). In addition, a process for manufacturing the operation processor device1100may be more difficult and complex than a process for manufacturing the first storage device1300. Thus, it may be simpler and more economical to implement the port PORT1b, the communication circuit, and the peripheral circuit in the first storage device1300.

The operation processor device1100and the storage devices1300and1400may communicate with each other in compliance with one or more of various interface protocols. For example, the operation processor device1100and the storage devices1300and1400may employ each of, or at least one of interface protocols such as universal serial bus (USB), small computer system interface (SCSI), peripheral component interconnect express (PCIe), nonvolatile memory express (NVMe), serial advanced technology attachment (SATA), serial attachment SCSI (SAS), secure digital (SD) card, embedded multimedia card (eMMC), universal flash storage (UFS), and/or the like, to communicate with each other. However, this example is not to limit the inventive concepts.

FIGS. 2A to 2Dare conceptual diagrams illustrating example implementations of the storage system ofFIG. 1.

Referring toFIG. 2A, the storage system1000ofFIG. 1may be implemented in an electronic device2000(e.g., a smart phone, a tablet computer, and/or the like). The electronic device2000may include an application processor2100and an embedded storage device2300. The electronic device2000may include a slot2004to equip a removable storage device2400. For example, the removable storage device2400may be implemented in the form of a card, a stick, or a chip package, and may be equipped in the slot2004or be detached from the slot2004.

For example, the application processor2100may be connected to directly communicate with the embedded storage device2300through a conductive pattern W1. When the removable storage device2400is equipped in the slot2004, the embedded storage device2300may be connected to directly communicate with the removable storage device2400through a conductive pattern W2. On the other hand, the removable storage device2400may not be directly connected with the application processor2100.

Referring toFIGS. 2B through 2D, the storage system1000ofFIG. 1may be implemented in a computing system3000a,3000b, or3000c(e.g., a desktop computer, a laptop computer, a workstation, a server system, and/or the like). The computing system3000aofFIG. 2Bmay include a central processing unit (CPU)3100and storage devices3300aand3400a. The CPU3100may be equipped on a mainboard (or a motherboard)3001.

For example, each of, or at least one of the storage devices3300aand3400amay be a hard disk drive (HDD) or a solid state drive (SSD) implemented in a box module. The first storage device3300amay be connected with a connector3003aon the mainboard3001. The first storage device3300amay be connected to directly communicate with the CPU3100through a conductive pattern W3and a wire cable W4. The second storage device3400amay be connected to directly communicate with the first storage device3300athrough a wire cable W5. On the other hand, the second storage device3400amay not be directly connected with the CPU3100.

The computing system3000bofFIG. 2Cmay include the CPU3100and storage devices3300band3400b. For example, each of, or at least one of the storage devices3300band3400bmay be a memory module or a SSD implemented in a card module. The first storage device3300bmay be connected with a connector3003bon the mainboard3001, and may be connected to directly communicate with the CPU3100through a conductive pattern W6. The second storage device3400bmay be connected with a connector3004bon the mainboard3001, and may be connected to directly communicate with the first storage device3300bthrough a conductive pattern W7. On the other hand, the second storage device3400bmay not be directly connected with the CPU3100.

The computing system3000cofFIG. 2Dmay include the CPU3100and storage devices3300cand3400c. For example, each of, or at least one of the storage devices3300cand3400cmay be an on-board SSD or a ball grid array (BGA) SSD implemented in a chip or a chip package. The first storage device3300cmay be connected to directly communicate with the CPU3100through a conductive pattern W8, and may be connected to directly communicate with the second storage device3400cthrough a conductive pattern W9. On the other hand, the second storage device3400cmay not be directly connected to the CPU3100.

For example, when the first storage device3300cis a BGA SSD, the first storage device3300cmay include a nonvolatile memory/controller chip13mounted on a substrate12. The nonvolatile memory/controller chip13may be connected with the conductive patterns W8and W9through a bonding15, and may be covered with a mold compound14. The first storage device3300cmay be equipped on the mainboard3001through solder balls11.

In some example embodiments, each of, or at least one of the computing systems3000a,3000b, and3000cmay further include a working memory for temporarily storing data processed or to be processed by the CPU3100, a communication circuit for communicating with an external device/system, and a user interface for exchanging data/information with a user. The working memory, the communication circuit, and the user interface may be equipped or mounted on the mainboard3001, and may be connected with the CPU3100through conductive patterns and/or buses.

InFIG. 2A to 2D, each of, or at least one of the application processor2100and the CPU3100may correspond to the operation processor device1100ofFIG. 1. Each of, or at least one of the embedded storage device2300and the first storage devices3300a,3300b, and3300cmay correspond to the first storage device1300ofFIG. 1. Each of, or at least one of the removable storage device2400and the second storage devices3400a,3400b, and3400cmay correspond to the second storage device1400ofFIG. 1. As described with reference toFIG. 1, configurations ofFIGS. 2A to 2Dmay bring economic benefits while satisfying a user's demand.

For example, each of, or at least one of the conductive patterns W1, W2, W3, W6, W7, W8, and W9may be conductive material formed on a printed circuit board (PCB) or the mainboard3001. For example, each of, or at least one of the conductive patterns W1, W2, W3, W6, W7, W8, and W9may include a wire pattern, a trace pattern, and/or the like. For example, the conductive material may be implemented with a wire, a trace, a conductive plate, and/or the like.

FIG. 3is a block diagram illustrating example configurations of the storage devices ofFIG. 1.

In some example embodiments, the first storage device1300may further include interconnect layers1330aand1330b, an application layer1340, and a compensation circuit1350. The interconnect layer1330amay transmit and receive data/signal/packet through the port PORT1a, and the interconnect layer1330bmay transmit and receive data/signal/packet through the port PORT1b. The interconnect layers1330aand1330bmay include a physical layer and a link layer which are defined in an interface protocol employed by the first storage device1300. For example, the interconnect layers1330aand1330bmay include various hardware components such as a transmission/reception circuit, a modulation/demodulation circuit, a converter circuit, and/or the like.

The application layer1340may understand and process various commands and/or packets of the interface protocol employed by the first storage device1300. The application layer1340may provide a communication service on the first storage device1300by processing the interface protocol for the controller1320. For example, the application layer1340may include various hardware circuits to process the interface protocol. Additionally or alternatively, the application layer1340may be implemented with an instruction set of a program code that may be executed by a processor core.

In some example embodiments, the second storage device1400may further include an interconnect layer1430and an application layer1440. The interconnect layer1430may transmit and receive data/signal/packet through the port PORT2. The application layer1440may understand and process various commands/packets of the interface protocol employed by the second storage device1400. The interconnect layer1430and the application layer1440may be configured similarly to the interconnect layer1330aand the application layer1340respectively.

FIG. 3illustrates that the interconnect layers1330a,1330b, and1430and the application layers1340and1440are independent components. However, this configuration is to facilitate better understanding, and is not to limit the inventive concepts. In some example embodiments, the interconnect layers1330aand1330band/or the application layer1340may be included in the controller1320, and the interconnect layer1430and/or the application layer1440may be included in the controller1420.

For example, when the operation processor device1100intends to communicate with the first storage device1300(e.g., intends to store data in the first storage device1300or reads data from the first storage device1300), the operation processor device1100may provide a command and/or data to the application layer1340through the ports PORT0and PORT1aand the interconnect layer1330a. The controller1320may store data in the nonvolatile memories1310or read data from the nonvolatile memories1310, based on information processed by the application layer1340. The read data may be provided to the operation processor device1100through the interconnect layer1330aand the ports PORT1aand PORT0.

Meanwhile, the operation processor device1100may intend to communicate with the second storage device1400. However, since the operation processor device1100may not be directly connected with the second storage device1400, the operation processor device1100may provide a command and/or data configured for the second storage device1400to the first storage device1300through the ports PORT0and PORT1aand the interconnect layer1330a. The first storage device1300may transfer the provided command and/or data to the second storage device1400through the interconnect layer1330band the ports PORT1band PORT2.

The second storage device1400may receive command and/or data from the first storage device1300through the interconnect layer1430. The controller1420may store data in the nonvolatile memories1410or read data from the nonvolatile memories1410, based on information processed by the application layer1440. The read data may be provided to the first storage device1300through the interconnect layer1430and the ports PORT2and PORT1b.

The first storage device1300may receive data from the second storage device1400through the interconnect layer1330b. The first storage device1300may transfer the received data to the operation processor device1100through the interconnect layer1330aand the ports PORT1aand PORT0. Accordingly, the first storage device1300may process the command and/or data received from the operation processor device1100by itself, or may transfer the command and/or data to the second storage device1400.

In some cases, the operation processor device1100, the first storage device1300, and the second storage device1400may have different characteristics. This is because the operation processor device1100, the first storage device1300, and the second storage device1400may be designed based on different purposes, different performances, and different requirements. For example, the operation processor device1100may process a packet having a first characteristic. On the other hand, the first storage device1300may process a packet having a second characteristic, and the second storage device1400may process a packet having a third characteristic.

For example, the “characteristic” may be associated with unit size of a data portion included in a packet. For example, the operation processor device1100may process a packet including a data portion of 4 kilobytes (kB). On the other hand, the controller1320of the first storage device1300may process a packet including a data portion of 16 kB, and the controller1420of the second storage device1400may process a packet including a data portion of 2 kB.

However, the above example is provided to facilitate better understanding, and is not to limit the inventive concepts. The “characteristic” may include various other operation conditions, requirements, and/or the like, and various examples will be described with reference toFIGS. 4A to 9. Further, unit size of a data portion processed by each of, or at least one of the operation processor device1100, the first storage device1300, and the second storage device1400may be variously changed or modified depending on a purpose, performance, and/or a requirement or desirability.

The compensation circuit1350may compensate different characteristics between the operation processor device1100, the first storage device1300, and the second storage device1400. For example, the compensation circuit1350may compensate difference among a first characteristic of a packet which is processed by the operation processor device1100, a second characteristic of a packet which is processed by the first storage device1300, and a third characteristic of a packet which is processed by the second storage device1400.

In the inventive concepts, the “compensation” may mean operations of properly processing and managing packets such that packets having different characteristics are processed in multiple electronic devices. Various examples of the compensation operations will be described with reference toFIGS. 4A to 9.

For example, the first storage device1300may receive a packet of the third characteristic from the second storage device1400, for the operation processor device1100. Further, in the first storage device1300, the controller1320(and/or the application layer1340) may prepare a packet of the second characteristic, for the operation processor device1100. On the basis of the operation of the compensation circuit1350, at least one of the packet of the second characteristic or the packet of the third characteristic may be provided to the operation processor device1100according to the first characteristic. To this end, the compensation circuit1350may compensate at least one of the second characteristic or the third characteristic.

For example, the first storage device1300may receive a packet of the first characteristic from the operation processor device1100. When the received packet is configured for the first storage device1300, the first storage device1300may process the received packet by the controller1320(and/or the application layer1340) of the first storage device1300according to the second characteristic. On the other hand, when the received packet is configured for the second storage device1400, the first storage device1300may transfer the received packet to the second storage device1400according to the third characteristic. To this end, the compensation circuit1350may compensate the first characteristic. The second storage device1400may process the packet, which is received from the operation processor device1100through the first storage device1300, by the controller1420(and/or the application layer1440).

When the compensation circuit1350is not provided, the operation processor device1100may require both a communication channel (e.g., a transmission/reception line, a physical layer, and/or the like) for communicating with the first storage device1300and a communication channel for communicating with the second storage device1400. This is because a characteristic of a packet processed by the first storage device1300may be different from a characteristic of a packet processed by the second storage device1400. Thus, design/manufacturing costs and configuration complexity of the operation processor device may increase.

However, when the compensation circuit1350is provided, the compensation circuit1350may compensate different characteristics of packets processed by the operation processor device1100, the first storage device1300, and the second storage device1400. Thus, the operation processor device1100may require only a communication channel for communicating with the first storage device1300, and it may be possible to implement only one communication channel. As a result, design/manufacturing costs and configuration complexity of the operation processor device1100may decrease.

The compensation circuit1350may include various hardware circuits to perform compensation operations. Additionally or alternatively, the compensation circuit1350may be implemented with an instruction set of a program code that may be executed by a processor core, to perform compensation operations. Further,FIG. 3illustrates that the compensation circuit1350is an independent component, but in some example embodiments, the compensation circuit1350may be included in the interconnect layers1330aand1330band/or the application layer1340.

FIGS. 4A to 4Dare conceptual diagrams for describing example configuration and operation of the first storage device ofFIG. 3for managing transmission of data write request packets. In some example embodiments, the compensation circuit1350of the first storage device1300may include a characteristic manager1351a, a buffer1353a, and a transmission scheduler1355a.

Referring toFIG. 4A, the characteristic manager1351amay manage the first characteristic associated with the operation processor device1100, the second characteristic associated with the first storage device1300, and the third characteristic associated with the second storage device1400. For example, the characteristic manager1351amay collect information associated with the first characteristic, the second characteristic, and the third characteristic, during a booting operation of the first storage device1300and/or the storage system1000. For example, the characteristic manager1351amay collect information associated with the first characteristic, the second characteristic, and the third characteristic in real time while the first storage device1300is operating.

For example, a communication protocol for exchanging characteristic information between the operation processor device1100, the first storage device1300, and the second storage device1400may be newly defined to collect information associated with the first characteristic, the second characteristic, and the third characteristic. For example, the characteristic manager1351amay include a memory device or may use a memory area of the first storage device1300(e.g., an internal buffer, the nonvolatile memories1310, and/or the like) to store the collected information.

In an example ofFIGS. 4A to 4D, the first characteristic may be associated with the number of data write request packets which are supported, or maximally supported by the operation processor device1100. The second characteristic may be associated with the number of data write request packets which are generated by the first storage device1300, and the third characteristic may be associated with the number of data write request packets which are generated by the second storage device1400.

The data write request packet may be understood as a ready-to-transfer (RTT) packet. When the operation processor device1100transmits a write command or request to the storage devices1300and1400, the storage devices1300and1400may transmit a data write request packet to the operation processor device1100to inform the operation processor device1100of available resource information such as the remaining capacity of the internal buffer and/or the like. The operation processor device1100may transmit write data to the storage devices1300and1400suitably for the storage devices1300and1400, with reference to the data write request packet.

For example, to facilitate better understanding and not to limit the inventive concepts, the operation processor device1100may support up to two (2) data write request packets. Further, the first storage device1300may generate up to four (4) data write request packets, and the second storage device1400may generate up to two (2) data write request packets.

Since the operation processor device1100may support up to two data write request packets, the compensation circuit1350may allow up to two data write request packets to be exchanged with the operation processor device1100. To this end, the characteristic manager1351amay set the number, or maximum number, of the data write request packets to 2, in connection with the operation processor device1100and/or the compensation circuit1350. Such a setting may be based on a request of the operation processor device1100or characteristic information exchanged with the operation processor device1100.

The application layer1340may provide four data write request packets RTT1, RTT2, RTT3, and RTT4to the compensation circuit1350, based on information generated by an operation of the controller1320(operation {circle around (1)}). The application layer1440of the second storage device1400may provide two data write request packets RTT5and RTT6to the first storage device1300, based on information generated by an operation of the controller1420(operation {circle around (2)}).

The buffer1353amay buffer packets of the first storage device1300and packets received from the second storage device1400. For example, the buffer1353amay buffer six (6) data write request packets RTT1, RTT2, RTT3, RTT4, RTT5, and RTT6(operation {circle around (3)}). However, in an example ofFIGS. 4A to 4C, the operation processor device1100may support up to two data write request packets. Thus, the operation processor device1100may not process the buffered six data write request packets RTT1, RTT2, RTT3, RTT4, RTT5, and RTT6simultaneously, or concurrently.

Thus, the transmission scheduler1355amay manage (e.g., schedule) transmission of the data write request packets buffered in the buffer1353ato the operation processor device1100, such that the number of data write request packets provided to the operation processor device1100among the data write request packets buffered in the buffer1353ais not greater than the number of data write request packets supported by the operation processor device1100. For example, the transmission scheduler1355amay allow the buffer1353ato output up to two data write request packets among the data write request packets RTT1, RTT2, RTT3, RTT4, RTT5, and RTT6, with reference to information managed by the characteristic manager1351a.

Referring toFIG. 4B, for example, the first storage device1300may provide two data write request packets RTT1and RTT5to the operation processor device1100(operation {circle around (4)}). Thus, the operation processor device1100may process the data write request packets RTT1and RTT5, and the buffer1353amay buffer the remaining data write request packets RTT2, RTT3, RTT4, and RTT6(operation {circle around (5)}). That is, the buffer1353amay continuously buffer remaining data write request packets other than output data write request packets.

FIG. 4Billustrates that the data write request packets RTT1and RTT5are provided to the operation processor device1100. However, in another example, the first storage device1300may output the data write request packets RTT2and RTT6or the data write request packets RTT1and RTT2, instead of the data write request packets RTT11and RTT5. Outputting and buffering the data write request packets may be variously changed or modified.

For example, the transmission scheduler1355amay allow a data write request packet having high priority, a data write request packet that requires urgent transmission, or a data write request packet which allows performance improvement to be output prior to the other packets. That is, the transmission scheduler1355amay manage the number and the sequence of data write request packets which are provided to the operation processor device1100.

Referring toFIG. 4C, the operation processor device1100may output a write data packet DAT1corresponding to the data write request packet RTT1. The first storage device1300may process the write data packet DAT1by the controller1320and/or the application layer1340to store write data corresponding to the write data packet DAT1in the nonvolatile memories1310(operation {circle around (6)}).

As the operation processor device1100completes processing of the data write request packet RTT1, the operation processor device1100may be capable of additionally processing one data write request packet. Thus, in response to the write data packet DAT1, the transmission scheduler1355amay allow the data write request packet RTT2buffered in the buffer1353ato be output and then to be provided to the operation processor device1100(operation {circle around (7)}). Accordingly, the operation processor device1100, may process the additionally received data write request packet RTT2in addition to the data write request packet RTT5which is not processed yet. The buffer1353amay buffer the remaining data write request packets RTT3, RTT4, and RTT6(operation {circle around (8)}).

Accordingly, the compensation circuit1350of the first storage device1300may perform a compensation operation, such that the sum of the number of data write request packets provided from the first storage device1300to the operation processor device1100and the number of data write request packets provided from the second storage device1400to the operation processor device1100through the first storage device1300is not greater than the number of data write request packets supported, or maximally supported by the operation processor device1100. When the sum of the number of data write request packets of the first storage device1300and the number of data write request packets received from the second storage device1400is greater than the number of data write request packets supported, or maximally supported by the operation processor device1100, the first storage device1300may buffer remaining data write request packets other than data write request packets provided to the operation processor device1100. When the number of data write request packets which are currently being processed in the operation processor device1100is smaller than the number of data write request packets supported, or maximally supported by the operation processor device1100, the first storage device1300may additionally provide the buffered data write request packet to the operation processor device1100. When the buffer1353aoutputs all the data write request packets, a compensation operation may not be performed.

The number of data write request packets described with reference toFIGS. 4A to 4Cis provided to facilitate better understanding, and is not to limit the inventive concepts. The number of data write request packets may be variously changed or modified depending on a purpose, performance, and a requirement, or desirability, of at least one of the operation processor device1100, the first storage device1300, and the second storage device1400.

For another example, when the operation processor device1100supports up to three data write request packets, the transmission scheduler1355amay control the buffer1353asuch that up to three (3) data write request packets are output and remaining data write request packets are buffered. When the operation processor device1100is currently processing less than three data write request packets, the transmission scheduler1355amay control the buffer1353asuch that at least one of buffered data write request packets is additionally output.

Referring toFIG. 4D, in some non-limiting example embodiments, the characteristic manager1351amay further manage the limited number of data write request packets in addition to the allowable number of data write request packets. The allowable number of data write request packets may be associated with capacity which is physically allowed depending on hardware design and/or performance, and the limited number of data write request packets may be associated with an upper limit of the number of data write request packets which are allowed to be actually generated. Unlike the allowable number, the limited number may be arbitrarily set or selected depending on, for example, an operation policy, a user request, and/or the like. For example, the limited number may be set or selected according to a request of the operation processor device1100and/or a determination of the compensation circuit1350.

The limited number of data write request packets actually generated by the first storage device1300may be less than or equal to the maximum number of data write request packets that may be generated by the first storage device1300. The limited number of data write request packets actually generated by the second storage device1400may be less than or equal to the maximum number of data write request packets that may be generated by the second storage device1400. The limited number of data write request packets actually communicated with the operation processor device1100may be less than or equal to the maximum number of data write request packets that may be communicated with the operation processor device1100.

For example, referring toFIG. 4D, although the first storage device1300may generate up to four data write request packets, the characteristic manager1351amay manage the limited number such that the compensation circuit1350receives up to two data write request packets from the application layer1340. Meanwhile, for example, when the second storage device1400may generate up to two data write request packets, the characteristic manager1351amay manage the limited number such that the compensation circuit1350receives up to two data write request packets from the second storage device1400.

For example, although the operation processor device1100may support up to two data write request packets, the characteristic manager1351amay manage the limited number such that the compensation circuit1350exchanges one (1) data write request packet with the operation processor device1100. However, the above examples are provided to facilitate better understanding, and are not to limit the inventive concepts. The limited number of data write request packets and the maximum number of data write request packets may be variously changed or modified.

In regards to the above examples, the application layers1340may provide up to two data write request packets (e.g., RTT1and RTT2) to the compensation circuit1350based on information generated by an operation of the controller1320(operation {circle around (1)}). The application layers1440of the second storage device1400may provide up to two data write request packets (e.g., RTT3and RTT4) to the first storage device1300based on information generated by an operation of the controller1420(operation {circle around (2)}).

The buffer1353amay buffer packets of the first storage device1300and packets received from the second storage device1400. For example, the buffer1353amay buffer four data write request packets RTT1, RTT2, RTT3, and RTT4(operation {circle around (3)}). The transmission scheduler1355amay allow the buffer1353ato output up to one data write request packet among the data write request packets RTT1, RTT2, RTT3, and RTT4, with reference to information (e.g., the limited number) managed by the characteristic manager1351a. A data write request packet which is output from the buffer1353amay be transmitted to the operation processor device1100, and the operation processor device1100may process up to one data write request packet.

FIGS. 5A to 5Care conceptual diagrams for describing example configuration and operation of the first storage device ofFIG. 3for processing reconfiguration of a data portion of a packet. In some non-limiting example embodiments, the compensation circuit1350of the first storage device1300may include a characteristic manager1351b, a buffer1353b, and a packet reconfigurator1355b.

Referring toFIG. 5A, the characteristic manager1351bmay manage the first characteristic associated with the operation processor device1100, the second characteristic associated with the first storage device1300, and the third characteristic associated with the second storage device1400. The characteristic manager1351bmay be configured and may operate substantially the same as or similarly to the characteristic manager1351aofFIG. 4A.

In an example ofFIGS. 5A to 5C, the first characteristic may be associated with the unit size of a data portion which corresponds to one header portion in a packet processed by the operation processor device1100. The second characteristic may be associated with the unit size of a data portion which corresponds to one header portion in a packet processed by the first storage device1300, and the third characteristic may be associated with the unit size of a data portion which corresponds to a header portion in a packet processed by the second storage device1400.

A packet may include a data portion which includes information to be transferred. The packet may include a header portion that describes a size, a destination, a content, and/or like, of the data portion. One header portion may correspond to one data portion.

For example to facilitate better understanding but not to limit the inventive concepts, the operation processor device1100may process a packet which includes a data portion of 4 kB. Further, the first storage device1300may process a packet which includes a data portion of 16 kB, and the second storage device1400may process a packet which includes a data portion of 2 kB.

The application layer1340may provide a packet PCK1to the compensation circuit1350, based on information generated by an operation of the controller1320. The application layer1440of the second storage device1400may provide a packet PCK2to the first storage device1300, based on information generated by an operation of the controller1420.

The buffer1353bmay buffer a packet of the first storage device1300and a packet received from the second storage device1400. For example, the buffer1353bmay buffer the packets PCK1and PCK2. The packet PCK1may include the data portion of 16 kB and a header portion corresponding to the data portion of 16 kB, and the packet PCK2may include the data portion of 2 kB and a header portion corresponding to the data portion of 2 kB. However, since the operation processor device1100may process a packet which includes the data portion of 4 kB, the operation processor device1100may not process the packets PCK1and PCK2.

Accordingly, the packet reconfigurator1355bmay reconfigure a packet that may not be processed by the operation processor device1100, and thus may generate a packet that may be processed by the operation processor device1100. The packet reconfigurator1355bmay operate with reference to information managed by the characteristic manager1351b.

For example, the packet reconfigurator1355bmay reconfigure a data portion of at least one of the packets PCK1and/or PCK2and a header portion corresponding to the data portion, such that a data portion corresponding to one header portion in at least one of the packets PCK1and/or PCK2has unit size that may be processed by the operation processor device1100. According to an operation of the packet reconfigurator1355b, the operation processor device1100may receive a packet PCK3including a data portion having unit size that may be processed by the operation processor device1100and a header portion corresponding to the data portion.

For example, the unit size (e.g., 16 kB) of a data portion included in the packet PCK1may be greater than the unit size (e.g., 4 kB) for the packet PCK3. Referring toFIG. 5B, the packet PCK1may include a data portion D1and a header portion H1corresponding to the data portion D1. The packet reconfigurator1355bmay divide the data portion D1into a plurality of new data portions D3[1], D3[2], D3[3], and D3[4]. At least one of the new data portions D3[1], D3[2], D3[3], and D3[4] may have unit size for the packet PCK3.

The packet reconfigurator1355bmay generate a plurality of new header portions H3[1], H3[2], H3[3], and H3[4] which respectively correspond to the new data portions D3[1], D3[2], D3[3], and D3[4]. The packet reconfigurator1355bmay combine one of the new data portions D3[1], D3[2], D3[3], and D3[4] with a corresponding one of the new header portions H3[1], H3[2], H3[3], and H3[4] to generate a reconfigured packet. Thus, the packet configurator1355bmay generate a plurality of reconfigured packets. The buffer1353bmay temporarily buffer intermediate results while the reconfigured packets are generated.

According to such a compensation operation, the packet PCK3may be configured by reconfigured packets. At least one of the reconfigured packets may include a data portion having unit size that may be processed by the operation processor device1100. The packet PCK3may be provided to the operation processor device1100based on the reconfigured packets.

Referring toFIG. 5C, the packet PCK2may include a data portion D2[1] and a header portion H2[1] corresponding to the data portion D2[1]. However, unit size (e.g., 2 kB) of the data portion included in the packet PCK2may be smaller than unit size (e.g., 4 kB) for the packet PCK3. Thus, according to an operation of the packet reconfigurator1355b, the buffer1353bmay buffer the packet PCK2and one or more subsequent packets which follows the packet PCK2, until data portions of the packet PCK2and the subsequent packets are accumulated as much as the unit size of a data portion for the packet PCK3.

For example, the first storage device1300may receive a packet PCK2′ which follows the packet PCK2, from the second storage device1400. The packet PCK2′ may include a data portion D2[2] and a header portion H2[2] corresponding to the data portion D2[2]. Since the data portions D2[1] and D2[2] are accumulated as much as unit size of the data portion for the packet PCK3, the packet reconfigurator1355bmay combine the data portions D2[1] and D2[2] into one data portion D3. Further, the packet reconfigurator1355bmay generate a new header portion H3corresponding to the data portion D3.

According to such a compensation operation, the packet PCK3may be reconfigured to include the data portion D3and the new header portion H3. The data portion D3may have unit size for the packet PCK3. Thus, the packet PCK3may be provided to the operation processor device1100and thus may be processed in the operation processor device1100. The buffer1353bmay temporarily buffer intermediate results while the reconfigured packet PCK3is generated.

The unit sizes described with reference toFIGS. 5A to 5Care provided to facilitate better understanding, and are not to limit the inventive concepts. The unit size of the data portion may be variously changed or modified depending on a purpose, performance, and/or a requirement or desirability of at least one of the operation processor device1100, the first storage device1300, and the second storage device1400. In some cases, when unit size of a data portion associated with the first storage device1300or the second storage device1400is the same as the unit size of a data portion associated with the operation processor device1100, a compensation operation may not be performed.

Conversely, a data portion of a packet from the operation processor device1100may have a unit size that may not be processed in the first storage device1300or the second storage device1400. In this case, the compensation circuit1350may reconfigure the packet received from the operation processor device1100for the first storage device1300or the second storage device1400, according to an operation of the packet reconfigurator1355b.

FIG. 6is a conceptual diagram for describing example configuration and operation of the first storage device ofFIG. 3for managing a mapping of identifiers of memory areas included in storage devices ofFIG. 3. In some non-limiting example embodiments, the compensation circuit1350of the first storage device1300may include a characteristic manager1351cand a logical unit number (LUN) mapper1355c.

The nonvolatile memories1310of the first storage device1300and the nonvolatile memories1410of the second storage device1400may include a plurality of memory areas which is managed based on different identifiers (e.g., LUNs). For example, memory areas included in the nonvolatile memories1310may be distinguished and managed based on identifiers ELUN0, ELUN1, ELUN2, and ELUN3, and memory areas included in the nonvolatile memories1410may be distinguished and managed based on identifiers CLUN0and CLUN1. Memory areas may be distinguished according to various factors such as a policy of the storage system1000, a request of the operation processor device1100, and/or the like.

In some cases, the operation processor device1100may distinguish memory areas included in the first storage device1300and the second storage device1400based on identifiers LUN0, LUN1, LUN2, LUN3, LUN4, and LUN5. That is, the identifiers managed by the operation processor device1100may be different from the identifiers managed by the first storage device1300and the second storage device1400. Thus, the compensation circuit1350may compensate a difference between the identifiers managed by the operation processor device1100and the identifiers managed by the first storage device1300and the second storage device1400.

The characteristic manager1351cmay manage the first characteristic associated with the operation processor device1100, the second characteristic associated with the first storage device1300, and the third characteristic associated with the second storage device1400. The characteristic manager1351cmay be configured and may operate substantially the same as or similarly to the characteristic manager1351aofFIG. 4A.

In an example ofFIG. 6, the first characteristic may be associated with the identifiers LUN0, LUN1, LUN2, LUN3, LUN4, and LUN5which are managed by the operation processor device1100. The second characteristic may be associated with the identifiers ELUN0, ELUN1, ELUN2, and ELUN3which are managed by the first storage device1300, and the third characteristic may be associated with the identifiers CLUN0and CLUN1which are managed by the second storage device1400.

The characteristic manager1351cmay further manage a correspondence relationship CR between identifiers. The LUN mapper1355cmay map the identifiers LUN0, LUN1, LUN2, LUN3, LUN4, and LUN5with the identifiers ELUN0, ELUN1, ELUN2, ELUN3, CLUN0, and CLUN1respectively, based on the correspondence relationship CR which is managed by the characteristic manager1351c.

A packet communicated between the operation processor device1100, the first storage device1300, and the second storage device1400may include information of an identifier, e.g., in its header portion. The packet may be processed in connection with a memory area indicated by the identifier.

For example, when the first storage device1300receives a packet that indicates one of the identifiers LUN0, LUN1, LUN2, and LUN3from the operation processor device1100, the LUN mapper1355cmay map the identifier of the received packet to corresponding one among the identifiers ELUN0, ELUN1, ELUN2, and ELUN3, with reference to the correspondence relationship CR. According to such a compensation operation, the received packet may be processed in connection with a memory area having a mapped identifier in the nonvolatile memories1310of the first storage device1300.

For example, when the first storage device1300receives a packet that indicates one of the identifiers LUN4and LUN5from the operation processor device1100, the LUN mapper1355cmay map the identifier of the received packet to the corresponding one among the identifiers CLUN0and CLUN1, with reference to the correspondence relationship CR. According to such a compensation operation, the received packet may be transferred to the second storage device1400. The transferred packet may be processed in connection with a memory area having a mapped identifier in the nonvolatile memories1410.

Conversely, in some cases, the LUN mapper1355cmay map an identifier of a packet of the first storage device1300or a packet received from the second storage device1400to an identifier managed by the operation processor device1100, with reference to the correspondence relationship CR. A packet having the mapped identifier may be provided to the operation processor device1100. On the basis of the mapped identifier, the operation processor device1100may determine which memory area the packet is processed in connection with.

The identifiers described with reference toFIG. 6are provided to facilitate better understanding, and are not to limit the inventive concepts. The number of the identifiers (i.e., the number of memory areas) and the correspondence relationship CR may be variously changed or modified depending on a policy and a configuration.

FIGS. 7A and 7Bare conceptual diagrams for describing example configuration and operation of the first storage device ofFIG. 3for processing ordering of a data sequence of packets. In some non-limiting example embodiments, the compensation circuit1350of the first storage device1300may include a characteristic manager1351d, a buffer1353d, and a sequence aligner1355d.

Referring toFIG. 7A, the characteristic manager1351dmay manage the first characteristic associated with the operation processor device1100, the second characteristic associated with the first storage device1300, and the third characteristic associated with the second storage device1400. The characteristic manager1351dmay be configured and may operate substantially the same as or similarly to the characteristic manager1351aofFIG. 4A.

In an example ofFIGS. 7A and 7B, the first characteristic may indicate that the operation processor device1100may process packets arranged in in-order sequence data. The second characteristic may indicate that data sequence of packets output from the first storage device1300is out-of-order, and the third characteristic may indicate that data sequence of packets output from the second storage device1400is out-of-order.

For example, the first storage device1300may intend to output data A, B, C, and D stored in the nonvolatile memories1310to the operation processor device1100. For example, the data A, B, C, and D may have a sequence of “A-B-C-D”. The application layer1340may provide a packet PCK1to the compensation circuit1350based on the data A, B, C, and D read through the controller1320. The buffer1353dmay buffer the packet PCK1.

For example, the second storage device1400may intend to transfer data E, F, G, and H stored in the nonvolatile memories1410to the operation processor device1100. For example, the data E, F, G, and H may have sequence of “E-F-G-H”. The application layer1440may provide a packet PCK2to the first storage device1300based on the data E, F, G, and H read through the controller1420. The buffer1353dmay buffer the packet PCK2.

However, in some cases, data associated with the packets PCK1and PCK2may have out-of-order sequence. Referring toFIG. 7Btogether, for example, data associated with the packet PCK1may have sequence of “C-B-A-D”, and data associated with the packet PCK2may have sequence of “F-H-E-G”. In some cases, the storage devices1300and1400may generate the packets PCK1and PCK2according to an out-of-order sequence which is different from the originally arranged in-order sequence, considering various factors such as performance, efficiency, and/or the like, of data transmission.

Meanwhile, in some cases, the operation processor device1100may not process data of out-of-order sequence, e.g., because of a limitation on performance and/or design. In this case, the operation processor device1100may not process the packets PCK1and PCK2arranged in out-of-order sequence.

Thus, the sequence aligner1355dmay align an out-of-order sequence of data associated with the packets PCK1and PCK2to an in-order sequence, with reference to information managed by the characteristic manager1351d. For example, the sequence aligner1355dmay align data associated with the packet PCK1to sequence of “A-B-C-D”, with reference to header portion(s) of the packet PCK1. For example, the sequence aligner1355dmay align data associated with the packet PCK2to sequence of “E-F-G-H”, with reference to header portion(s) of the packet PCK2. The buffer1353dmay temporarily buffer intermediate results while data sequence is aligned.

According to such a compensation operation, the sequence aligner1355dmay generate the packet PCK3. Data associated with the packet PCK3may have in-order sequence. Thus, the packet PCK3may be provided to the operation processor device1100, and then may be processed in the operation processor device1100.

The data sequence, the in-order sequence, and the out-of-order sequence described with reference toFIGS. 7A and 7Bare provided to facilitate better understanding, and are not to limit the inventive concepts. In some other examples, the first storage device1300or the second storage device1400may output packets according to in-order sequence, and the operation processor device1100may process packets of out-of-order sequence. Conversely in such examples, the compensation circuit1350may align a data sequence of packets received from the operation processor device1100for the first storage device1300or the second storage device1400according to an operation of the sequence aligner1355d. In some cases, when data sequence is not conflicted between the operation processor device1100, the first storage device1300, and the second storage device, the compensation operation may not be performed.

FIG. 8is a conceptual diagram for describing an example configuration and operation of the first storage device ofFIG. 3for managing packet distribution according to a throughput of at least one of the storage devices ofFIG. 3. In some example embodiments, the compensation circuit1350of the first storage device1300may include a throughput manager1351e, a buffer1353e, and a distribution scheduler1355e.

In some cases, the first storage device1300and the second storage device1400may operate concurrently or simultaneously. For example, the operation processor device1100may intend to store data in both the first storage device1300and the second storage device1400.

Meanwhile, a throughput of the first storage device1300may be different from a throughput of the second storage device1400. For example, the first storage device1300may be requested to store a relatively large amount of data, and the second storage device1400may be requested to store a relatively small amount of data. For example, processing bandwidth of the first storage device1300may be higher than processing bandwidth of the second storage device1400. In these examples, referring toFIG. 8, the throughput of the first storage device1300may be higher than the throughput of the second storage device1400.

The throughput manager1351emay manage information associated with throughput of at least one of the first storage device1300and the second storage device1400. For example, the throughput manager1351emay collect throughput information based on device information of at least one of the first storage device1300and the second storage device1400. For example, the throughput manager1351emay collect throughput information by monitoring an amount of packets transferred through a communication line. However, these examples are to facilitate better understanding, and not to limit the inventive concepts.

The buffer1353emay buffer packets received from the operation processor device1100. The buffered packets may be processed in the first storage device1300or may be transferred to the second storage device1400.

Meanwhile, when throughput of the first storage device1300is higher than throughput of the second storage device1400, it may be efficient, or desirable, to process packets in the first storage device1300more frequently than transferring packets to the second storage device1400. Thus, the distribution scheduler1355emay manage (e.g., schedule) distribution of packets with reference to information managed by the throughput manager1351e, such that packets buffered in the buffer1353eare processed by the controller1320(and/or the application layer1340) more frequently than being transferred to the second storage device1400.

In some cases, unlike the illustration described inFIG. 8, throughput of the second storage device1400may be higher than throughput of the first storage device1300. In this case, according to an operation of the distribution scheduler1355e, packets buffered in the buffer1353emay be transferred to the second storage device1400more frequently than being processed in the first storage device1300. Performance of the storage system1000may be improved according to such a compensation operation.

Conversely, the operation processor device1100may intend to read data from both the first storage device1300and the second storage device1400. In this case, according to an operation of the distribution scheduler1355e, packets of the first storage device1300may be provided to the operation processor device1100more frequently than packets from the second storage device1400being provided to the operation processor device1100, or packets from the second storage device1400may be provided to the operation processor device1100more frequently than packets of the first storage device1300being provided to the operation processor device1100.

FIG. 9is a conceptual diagram for describing a non-limiting example configuration and operation of the first storage device ofFIG. 3for managing packet distribution according to priority associated with processing a packet. In some example embodiments, the compensation circuit1350of the first storage device1300may include a buffer1351f, a priority determinator1353f, and a distribution scheduler1355f.

The operation processor device1100may transmit a packet PCK1for the first storage device1300to the first storage device1300(operation {circle around (1)}). The operation processor device1100may transmit a packet PCK2for the second storage device1400to the first storage device1300(operation {circle around (2)}). For example, the packet PCK1may be transmitted before the packet PCK2.

The buffer1351fmay buffer packets received from the operation processor device1100. For example, the buffer1351fmay buffer the first received packet PCK1, and then may further buffer the second received packet PCK2(operation {circle around (3)}).

Meanwhile, in some cases, priority may be given to at least one of, for example, each of the packets PCK1and PCK2. For example, higher priority may be given to a packet requested to be urgently processed, a packet associated with metadata, a packet associated with a system management (e.g., performance, life), and/or the like. For example, information associated with priority may be included in a header portion of the packet.

The priority determinator1353fmay determine the priority of a packet buffered in the buffer1351f, with reference to a header portion of the packet buffered in the buffer1351f. The distribution scheduler1355fmay manage (e.g., schedule) distribution sequence of the packets, based on a determination result of the priority determinator1353f. The distribution scheduler1355fmay distribute a packet having higher priority earlier, regardless of received sequence of packets.

For example, lower priority may be given to the packet PCK1, and higher priority may be given to the packet PCK2. In this example, even though the packet PCK1is received before the packet PCK2, the distribution scheduler1355fmay control the buffer1351fsuch that the packet PCK2is distributed earlier than the packet PCK1. Thus, the packet PCK2having higher priority may be transferred to the second storage device1400first, and then the packet PCK1having lower priority may be processed by the controller1320(and/or the application layer1340).

In some cases, unlike as illustrated and described inFIG. 9, priority of the packet PCK1may be higher than priority of the packet PCK2. In this case, according to an operation of the distribution scheduler1355f, the packet PCK1may be processed in the first storage device1300first, and then the packet PCK2may be transferred to the second storage device1400. According to such a compensation operation, quality of service (QoS) of the storage system1000may be improved.

Conversely, the buffer1351fmay buffer a packet of the first storage device1300and a packet received from the second storage device1400, and the first storage device1300may intend to provide the buffered packets to the operation processor device1100. In this case, according to an operation of the distribution scheduler1355f, the first storage device1300may provide the operation processor device1100with a packet having higher priority, among the packet of the first storage device1300and the packet received from the second storage device1400, earlier.

The various compensation operations have been described with reference toFIGS. 4A to 9. However, the compensation circuit1350may further perform other kinds of compensation operations to compensate different characteristics of the operation processor device1100, the first storage device1300, and the second storage device1400.FIGS. 4A to 9are not to limit the inventive concepts.

In some cases, according to an operation of the compensation circuit1350, a packet may be exchanged between the first storage device1300and the second storage device1400. In some cases, the controller1320and/or the application layer1340may be involved in packet processing to exchange a packet between the first storage device1300and the second storage device1400.

FIG. 10is a block diagram illustrating an example configuration of the second storage device ofFIG. 3.

The storage system1000described with reference toFIGS. 1 to 9may include two storage devices1300and1400serially connected to each other. However, in some example embodiments, the storage system1000may include three or more storage devices serially connected to each other (refer toFIG. 11). In such example embodiments, the second storage device1400ofFIG. 3may include a second storage device1400bofFIG. 10.

The second storage device1400bmay include an interconnect layer1430band a compensation circuit1450in addition to the nonvolatile memories1410, the controller1420, the interconnect layer1430, and the application layer1440. The interconnect layer1430bmay transmit and receive data/signal/packet through a port PORT2b, similarly to the interconnect layer1330bofFIG. 3. The port PORT2bmay be directly connected to another storage device which is not directly connected to the operation processor device1100and the first storage device1300.

The compensation circuit1450may perform various compensation operations similarly to the compensation circuit1350ofFIG. 3. The compensation circuit1450may compensate different characteristics of the first storage device1300connected through the port PORT2, another storage device connected through the port PORT2b, and the second storage device1400. To this end, the compensation circuit1450may perform the compensation operations described with reference toFIGS. 4A to 9and other compensation operations.

FIG. 11is a block diagram illustrating an electronic system that includes electronic devices serially connected according to some example embodiments.FIGS. 12A and 12Bare conceptual diagrams for describing example processes of communicating with electronic devices which are not directly connected to an operation processor device in an electronic system ofFIG. 11.

Referring toFIG. 11, an electronic system4000may include an operation processor device4100and a plurality of electronic devices4300,4400,4800, and4900serially connected to the operation processor device4100. The operation processor device4100may correspond to one of the operation processor devices1100,2100, and3100described with reference toFIGS. 1 to 10.

The electronic system4000may be one of various types of electronic systems. The electronic system4000may correspond to the storage system1000, the electronic device2000, or the computing system3000a,3000b, or3000cdescribed with reference toFIGS. 1 to 10. For example, at least one of, or each of, the electronic devices4300,4400,4800, and4900may correspond to one of the storage devices1300,1400,1400b,2300,2400,3300a,3300b,3300c,3400a,3400b, and3400cdescribed with reference toFIGS. 1 to 10.

However, the inventive concepts are not limited to the above examples. For example, at least one of the electronic devices4300,4400,4800, and4900may include any type of electronic device such as a graphic processing device, a wired/wireless communication device, a display device, and/or the like. Use of the electronic system4000may be variously changed or modified depending on a type of at least one of the electronic devices4300,4400,4800, and4900.

The electronic devices4300,4400,4800, and4900may be serially connected to each other through respective input/output ports thereof. The first electronic device4300may be at a tail end of the serial connection. The second electronic device4400may be connected to directly communicate with the first electronic device4300. In this manner, the electronic devices4300,4400,4800, and4900may be connected in the topology of a chain structure or a daisy-chain structure.

The operation processor device4100may be connected to directly communicate with the first electronic device4300. However, the operation processor device4100may not be directly connected with other electronic devices4400,4800, and4900. When the operation processor device4100intends to communicate with a target electronic device which is not directly connected to the operation processor device4100, the operation processor device4100may communicate with the target electronic device through intermediate electronic device(s).

For example, referring toFIG. 12A, when the operation processor device4100intends to communicate with the second electronic device4400, the operation processor device4100may communicate with the second electronic device4400through the first electronic device4300. In this case, the first electronic device4300may perform various compensation operations to compensate different characteristics of the operation processor device4100, the first electronic device4300, and the second electronic device4400.

For example, referring toFIG. 12B, an Nthelectronic device may be an interfacing electronic device, wherein the operation processor device4100intends to communicate with the Nthelectronic device. Accordingly, when the operation processor device4100intends to communicate with the Nthelectronic device4900, the operation processor device4100may communicate with the Nthelectronic device4900through the first to (N−1)thelectronic devices4300to4800. In this case, at least one of the first to (N−1)thelectronic devices4300to4800may be a designated electronic device configured to perform various compensation operations between the operation processor device4100and the Nthelectronic device4900to compensate different characteristics of components of the electronic system4000.

To implement the electronic system4000ofFIGS. 11, 12A and 12B, the operation processor device4100and the electronic devices4300,4400,4800, and4900may employ at least one of the configurations, the operations, the processes, the methods, and/or the communications described with reference toFIGS. 1 to 10. The operation processor device4100and the electronic devices4300,4400,4800, and4900may employ at least one of various interface protocols such as USB, SCSI, PCIe, NVMe, SATA, SAS, SD card, eMMC, UFS, and/or the like, to communicate with each other, but this example is not to limit the inventive concepts.

FIG. 13is a block diagram illustrating an example configuration of an electronic device and interfaces thereof according to some example embodiments. An electronic device5000may be, for example, implemented with a data processing device which is capable of using or supporting an interface protocol proposed by mobile industry processor interface (MIPI) alliance. For example, the electronic device5000may be one of electronic devices such as a portable communication terminal, a personal digital assistant (PDA), a portable media player (PMP), a smart phone, a tablet computer, a wearable device, and/or the like.

The electronic device5000may include an application processor5100, displays5220and5221, and image sensors5230and5231. The application processor5100may include a DigRF master5110, a display serial interface (DSI) host5120, a camera serial interface (CSI) host5130, and/or a physical layer5140.

The DSI host5120may communicate with a DSI device5225of the display5220in compliance with DSI. For example, a serializer SER may be implemented in the DSI host5120, and a deserializer DES may be implemented in the DSI device5225. The display5220may communicate with a DSI device5226of the display5221in compliance with DSI. For example, a serializer SER may be further implemented in the DSI device5225, and a deserializer DES may be implemented in the DSI device5226.

Meanwhile, the display5221may not be directly connected with the application processor5100. Thus, the application processor5100may communicate with the DSI device5226of the display5221through the display5220. The display5220may perform various compensation operations to compensate different characteristics of the application processor5100, the display5220, and the display5221.

The CSI host5130may communicate with a CSI device5235of the image sensor5230in compliance with CSI. For example, a deserializer DES may be implemented in the CSI host5130, and a serializer SER may be implemented in the CSI device5235. The image sensor5230may communicate with a CSI device5236of the image sensor5231in compliance with CSI. A deserializer DES may be further implemented in the CSI device5235, and a serializer SER may be implemented in the CSI device5236.

Meanwhile, the image sensor5231may not be directly connected to the application processor5100. Thus, the application processor5100may communicate with the CSI device5236of the image sensor5231through the image sensor5230. The image sensor5230may perform various compensation operations to compensate different characteristics of the image sensor5231, the image sensor5230, and the application processor5100.

The electronic device5000may further include a radio frequency (RF) chip5240that communicates with the application processor5100. The RF chip5240may include a physical layer5242, a DiRF slave5244, and an antenna5246. For example, the physical layer5242of the RF chip5240and the physical layer5140of the application processor5100may exchange data with each other in compliance with DiRF interface proposed by the MIPI alliance.

The electronic device5000may further include a working memory5250, an embedded storage device5251, and card storage device5252. The working memory5250, the embedded storage device5251, and the card storage device5252may store or output data for the application processor5100.

The working memory5250may temporarily store data processed or to be processed by the application processor5100. The working memory5250may include a volatile memory such as a static random access memory (SRAM), a dynamic RAM (DRAM), a synchronous DRAM (SDRAM), and/or the like, and/or a nonvolatile memory such as a flash memory, a PRAM, a MRAM, a ReRAM, a FRAM, and/or the like.

The embedded storage device5251and the card storage device5252may store data regardless of whether power is supplied. For example, the embedded storage device5251and the card storage device5252may correspond to the embedded storage device2300and the removable storage device2400ofFIG. 2respectively.

The electronic device5000may communicate with an external device/system through a communication module such as worldwide interoperability for microwave access (Wimax)5260, wireless local area network (WLAN)5262, ultra-wideband (UWB)5264, and/or the like. Besides, the electronic device5000may communicate with an external device/system in compliance with at least one of various wireless communication protocols such as long term evolution (LTE), global system for mobile communication (GSM), code division multiple access (CDMA), Bluetooth, near field communication (NFC), wireless fidelity (WiFi), radio frequency identification (RFID), and/or the like, and/or at least one of various wired communication protocols such as transfer control protocol/Internet protocol (TCP/IP), USB, SCSI, mobile PCIe (M-PCIe), Firewire, and/or the like.

The electronic device5000may further include a speaker5270and a microphone5275for processing voice information. Further, the electronic device5000may further include a global positioning system (GPS) device5280for processing position information. The electronic device5000may further include a bridge chip5290for managing connection with peripheral devices.

The above descriptions are specific example embodiments for implementing the inventive concepts. The inventive concepts may include not only the above-described example embodiments but also other embodiments which may be obtained by simply modifying or easily changing a design. The inventive concepts may also include technologies that may be implemented by modification based on the above-described embodiments in the future.