Semiconductor memory device

A semiconductor memory device includes a substrate including a peripheral circuit, a stepped dummy stack overlapping the substrate and including a plurality of steps extending in a first direction, a plurality of contact groups passing through the stepped dummy stack, and upper lines respectively connected to the contact groups. The contact groups include a first contact group having two or more first contact plugs arranged in the first direction. The upper lines include a first upper line commonly connected to the first contact plugs.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean patent application number 10-2019-0140451, filed on Nov. 5, 2019, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

BACKGROUND

1. Technical Field

The present disclosure relates to a semiconductor memory device, and more particularly, to a semiconductor memory device including a stack overlapping a peripheral circuit.

2. Related Art

A semiconductor memory device includes a memory cell array and a peripheral circuit connected to the memory cell array. The memory cell array includes a plurality of memory cells capable of storing data, and the peripheral circuit is configured to perform various operations of the memory cells.

In order to improve a degree of integration of a semiconductor memory device, the memory cell array may overlap the peripheral circuit. In forming such a structure, various process defects may occur.

SUMMARY

A semiconductor memory device according to an embodiment of the present disclosure may include a substrate including a peripheral circuit, a stepped dummy stack overlapping the substrate and including a plurality of steps extending in a first direction, a plurality of contact groups passing through the stepped dummy stack, and upper lines respectively connected to the contact groups. The contact groups may include a first contact group having two or more first contact plugs arranged in the first direction. The upper lines may include a first upper line commonly connected to the first contact plugs.

A semiconductor memory device according to an embodiment of the present disclosure may include a substrate including a peripheral circuit; a stepped dummy stack overlapping the substrate and including a plurality of steps extending in a first direction; a first contact plug and a second contact plug that pass through the stepped dummy stack and are adjacent to each other in a diagonal direction with respect to the first direction, in a plane parallel to the steps; a first upper line connected to the first contact plug; and a second upper line connected to the second contact plug and spaced apart from the first upper line.

A semiconductor memory device according to an embodiment of the present disclosure may include a substrate including a peripheral circuit; a first gate stack overlapping the substrate, a second gate stack overlapping the substrate and substantially parallel to the first gate stack; a stepped dummy stack disposed between the first gate stack and the second gate stack and including a plurality of steps extending in a first direction; a plurality of contact groups overlapping steps of the plurality of steps that are different from each other, and extending to pass through the stepped dummy stack; a first gate contact plug connected to the first gate stack; a second gate contact plug connected to the second gate stack; a first upper line connecting a first contact group among the contact groups and the first gate contact plug to each other; and a second upper line connecting a second contact group among the contact groups and the second gate contact plug to each other.

DETAILED DESCRIPTION

Specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments according to the concept of the present disclosure. The embodiments may be implemented in various forms, and should not be construed as being limited to the specific embodiments set forth herein.

An embodiment of the present disclosure provides a semiconductor memory device capable of improving yield reduction of a semiconductor memory device due to a process defect.

FIG. 1is a block diagram illustrating a semiconductor memory device10according to an embodiment.

Referring toFIG. 1, the semiconductor memory device10includes a peripheral circuit30and a memory cell array40.

The peripheral circuit30may perform a program operation of storing data in the memory cell array40, a read operation of outputting data stored in the memory cell array40, and an erase operation of erasing data stored in the memory cell array40. In an embodiment, the peripheral circuit30may include control logic39, an operation voltage generator31, a row decoder33, and a page buffer group35.

The memory cell array40may include a plurality of memory blocks. Each of the memory blocks may be connected to one or more drain select lines DSLs, a plurality of word lines WLs, one or more source select lines SSLs, and a plurality of bit lines BLs.

The control logic39may control the peripheral circuit30in response to a command CMD and an address ADD.

The operation voltage generator31may generate various operation voltages VOPs used for the program operation, the read operation, and the erase operation in response to control of the control logic39. The operation voltages VOPs may include a program voltage, a verification voltage, a pass voltage, a select line voltage, and the like.

The row decoder33may select a memory block in response to the control of the control logic39. The row decoder33may apply operation voltages VOPs to the drain select lines DSLs, the word lines WLs, and the source select lines SSLs connected to the selected memory block.

The page buffer group35may be connected to the memory cell array40through the bit lines BLs. The page buffer group35may temporarily store data received from an input/output circuit (not shown) during the program operation in response to control of the control logic39. The page buffer group35may sense a voltage or a current of the bit lines BLs during the read operation or the verification operation in response to the control of the control logic39.

FIG. 2is a diagram schematically illustrating a disposition of the peripheral circuit30and the memory cell array40shown inFIG. 1.

Referring toFIG. 2, the memory cell array40may overlap the peripheral circuit30. Although not shown in the drawing, the peripheral circuit30and the memory cell array40may be disposed on a substrate. The substrate may include a first area overlapping the memory cell array40, and a second area extending laterally from the first area. In an embodiment, the substrate SUB may include a peripheral circuit30. In an embodiment, the memory cell array40may be on a lower structure including a substrate SUB and a peripheral circuit30, the peripheral circuit30may be located between the substrate and the memory cell array40. In an embodiment, the peripheral circuit30may be coupled to contact plugs.

The memory cell array40may include a plurality of memory blocks BLK1to BLKz. Each of the memory blocks BLK1to BLKz may include a plurality of memory cell strings.

FIGS. 3A and 3Bare circuit diagrams illustrating memory cell strings CSa and CSb according to various embodiments.

Referring toFIGS. 3A and 3B, each of the memory cell strings CSa and CSb may be connected to corresponding one of the bit lines BL and a common source line CSL. Each of the memory cell strings CSa and CSb may be connected to the common source line CSL under control of a source select transistor SST, and may be connected to the corresponding bit line BL under control of a drain select transistor DST.

Each of the memory cell strings CSa and CSb may include a plurality of memory cells MC connected in series between the source select transistor SST and the drain select transistor DST. One source select transistor SST may be disposed, or two or more source select transistors SST connected in series may be disposed, between the common source line CSL and the plurality of memory cells MC. One drain select transistor DST may be disposed, or two or more drain select transistors DST connected in series may be disposed, between the bit line BL and the plurality of memory cells MC.

The plurality of memory cells MC may be connected to the word lines WL, respectively. An operation of the plurality of memory cells MC may be controlled by cell gate signals applied to the word lines WL. The source select transistor SST may be connected to the source select line SSL. An operation of the source select transistor SST may be controlled by a source select gate signal applied to the source select line SSL. The drain select transistor DST may be connected to the drain select line DSL. An operation of the drain select transistor DST may be controlled by a drain select gate signal applied to the drain select line DSL.

Referring toFIG. 3A, the memory cells MC of the memory cell string CSa may be stacked in one column between the corresponding bit line BL and the common source line CSL.

Referring toFIG. 3B, the memory cells MC of the memory cell string CSb may be divided into a first column stacked between a pipe gate PG and the bit line BL, and a second column stacked between the pipe gate PG and the common source line CSL. The memory cells of the first column and the memory cells of the second column may be connected to each other by a pipe transistor Ptr operating under control of the pipe gate PG.

The source select line SSL, the word lines WL, and the drain select line DSL shown inFIGS. 3A and 3Bmay be implemented through a gate stack.

FIGS. 4A and 4Bare plan views illustrating the semiconductor memory device according to an embodiment.FIG. 4Ais a plan view illustrating a layout of first and second gate stacks GST_A and GST_B and a dummy stack DM, andFIG. 4Bis a plan view illustrating a layout of the bit line BL and upper lines La1, La2, Lb1, and Lb2.

Referring toFIGS. 4A and 4B, the semiconductor memory device may include a cell area CA and a contact area CTA.

The cell area CA is an area in which a plurality of memory cell strings are disposed. Each of the memory cell strings may be implemented as the memory cell string CSa shown inFIG. 3Aor the memory cell string CSb shown inFIG. 3B.

Referring toFIG. 4A, the first gate stack GST_A and the second gate stack GST_B may be disposed to be substantially parallel with each other. Each of the first gate stack GST_A and the second gate stack GST_B may extend along a first direction D1and a second direction D2. The first direction D1and the second direction D2may be parallel to an X-axis and a Y-axis intersecting each other in an XYZ coordinate system. Each of the first gate stack GST_A and the second gate stack GST_B may include conductive patterns. The conductive patterns may be used as the word lines WL, the drain select line DSL, and the source select line SSL described with reference toFIGS. 3A and 3B. The conductive patterns included in each of the first gate stack GST_A and the second gate stack GST_B may be connected to a memory cell string corresponding to the conductive patterns, and may be stacked to be spaced apart from each other in a third direction D3. The third direction D3may be parallel to a Z axis orthogonal to an XY plane in the XYZ coordinate system.

A plurality of channel structures CH may pass through each of the first gate stack GST_A and the second gate stack GST_B. The channel structures CH are disposed in the cell area CA. Each of the channel structures CH may be used as a channel region of the memory cell string. Each of the channel structures CH may be surrounded by a memory film ML. The memory film ML may be used as a data storage area of a memory cell corresponding to the memory film ML.

The channel structures CH may be connected to the bit lines BL through bit line contact plugs BCT as shown inFIG. 4B. One of the channel structures CH passing through the first gate stack GST_A shown inFIG. 4Aand one of the channel structures CH passing through the second gate stack GST_B shown inFIG. 4Amay be commonly connected to corresponding one of bit line among the bit lines BL shown inFIG. 4B.

Referring toFIGS. 4A and 4B, each of the first gate stack GST_A and the second gate stack GST_B may be formed in a stepped structure in the contact area CTA. The contact area CTA is an area in which connection structures for connecting the memory cell strings and the peripheral circuit30described with reference toFIG. 2to each other are disposed. The connection structures may include gate contact plugs GCTa1, GCTa2, GCTb1, and GCTb2, contact plugs CTa11, CTa12, CTb11, and CTb12, and upper lines La1, La2, Lb1, and Lb2.

The first gate stack GST_A and the second gate stack GST_B may be connected to the gate contact plugs GCTa1, GCTa2, GCTb1, and GCTb2through the stepped structure. The gate contact plugs GCTa1, GCTa2, GCTb1, and GCTb2may be divided into first gate contact plugs GCTa1and GCTa2connected to the first gate stack GST_A and second gate contact plugs GCTb1and GCTb2connected to the second gate stack GST_B.

The dummy stack DM may overlap the peripheral circuit30described with reference toFIG. 2, in the contact area CTA. The dummy stack DM may be disposed adjacent to the first gate stack GST_A and the second gate stack GST_B. In an embodiment, the dummy stack DM may be disposed between the first gate stack GST_A and the second gate stack GST_B. The present disclosure is not limited thereto, and a position of the dummy stack DM may be variously changed according to design of the semiconductor memory device.

The contact plugs CTa11, CTa12, CTb11, and CTb12may pass through the dummy stack DM. The contact plugs CTa11, CTa12, CTb11, and CTb12may extend toward the peripheral circuit30shown inFIG. 2. The contact plugs CTa11, CTa12, CTb11, and CTb12may be divided into a plurality of contact groups. The contact groups may be connected to the first and second gate contact plugs GCTa1, GCTa2, GCTb1, and GCTb2, respectively, through the upper lines La1, La2, Lb1, and Lb2. The contact plugs included in the same contact group may be electrically connected to corresponding one gate contact plug through corresponding one upper line.FIGS. 4A and 4Bshow a first contact group corresponding to the first gate contact plugs GCTa1and a second contact group corresponding to the second gate contact plugs GCTb1.

The dummy stack DM may be formed in a stepped structure including a plurality of steps. Each of the contact groups may include two or more contact plugs arranged along a direction in which a corresponding step extends. In an embodiment, the dummy stack DM may include steps Sa to Sc each extending in the first direction D1. The first contact group may include first contact plugs CTa11and CTa12arranged in the first direction D1, and the second contact group may include second contact plugs CTb11and CTb12arranged in the first direction D1.

The contact groups may overlap different steps. For example, the first contact plugs CTa11and CTa12of the first contact group may overlap a boundary between the step Sa and the step Sb adjacent to each other, and the second contact plugs CTb11and CTb12of the second contact group may overlap the step Sc. In an embodiment, the second contact plugs CTb11and CTb12may be spaced apart from sidewalls of the steps Sa to Sc.

The upper lines La1, La2, Lb1, and Lb2may be spaced apart from each other. The upper lines La1, La2, Lb1, and Lb2may be divided into first upper lines La1and La2respectively connected to the first gate contact plugs CTa11and CTa12, and second upper lines Lb1and Lb2respectively connected to the second gate contact plugs CTb11and CTb12. Each of the first upper lines La1and La2may be extended to overlap the first gate stack GST_A and the dummy stack DM. Each of the second upper lines Lb1and Lb2may be extended to overlap the second gate stack GST_B and the dummy stack DM.

Each of the upper lines La1, La2, Lb1, and Lb2may be commonly connected to contact plugs included in a corresponding contact group. For example, the first contact plugs CTa11and CTa12of the first contact group may be commonly connected to the first upper line La1, and the second contact plugs CTb11and CTb12of the second contact group may be commonly connected to the second upper line Lb1.

The first gate stack GST_A, the second gate stack GST_B, and the dummy stack DM may be spaced apart from each other through a slit SI. The slit SI may be extended to surround the dummy stack DM in the contact area CTA.

FIGS. 5A and 5Billustrate cross-sectional views taken along a line I-I′ and a line II-II′ shown inFIG. 4B, respectively.

Referring toFIG. 5A, each of the first and second gate stacks GST_A and GST_B may include alternately stacked interlayer insulating films ILD and conductive patterns CPk to CPn (k is a natural number and n is a natural number greater than k). Although not shown in the drawing, each of the first and second gate stacks GST_A and GST_B further includes alternately stacked lower conductive patterns and lower interlayer insulating films under the interlayer insulating films ILD and the conductive patterns CPk to CPn. The slit SI may separate the conductive patterns CPk to CPn and the lower conductive patterns (not shown) of the first gate stack GST_A from the conductive patterns CPk to CPn and the lower conductive patterns (not shown) of the second gate stack GST_B.

In an embodiment, the conductive patterns CPk to CPn of the first and second gate stacks GST_A and GST_B may be used as the word lines WL and the drain select line DSL described with reference toFIG. 3A. The source select line SSL shown inFIG. 3Amay be implemented by any one of lower conductive patterns that are not shown. In an embodiment, the conductive patterns CPk to CPn of the first gate stack GST_A may be used as the word lines WL and the drain select line DSL described with reference toFIG. 3B, and the conductive patterns CPk to CPn of the second gate stack GST_B may be used as the word lines WL and the source select line SSL described with reference toFIG. 3B.

The interlayer insulating films ILD and the conductive patterns CPk to CPn may surround the corresponding channel structure CH in the cell area. The channel structure CH may include a core insulating film CO and a capping pattern CAP disposed in a center area of the channel structure CH, and a channel film CL extending along a surface of the capping pattern CAP and the core insulating film CO. The channel film CL may be formed of a semiconductor film such as silicon. The capping pattern CAP may be formed of a doped semiconductor film. Although not shown in the drawing, in an embodiment, the core insulating film CO may be omitted, and the channel film CL may be formed to fill the center area of the channel structure CH.

The channel structure CH may be surrounded by the memory film ML. The memory film ML may include a tunnel insulating film, a data storage film, and a blocking insulating film sequentially stacked from the sidewalls of the channel structure CH toward the corresponding gate stack GST_A or GST_B. The data storage film may be formed of a material film capable of storing changed data using Fowler-Nordheim tunneling. To this end, the data storage film may be formed of various materials. In an embodiment, the data storage film may be formed of a nitride film capable of charge trapping. The present disclosure is not limited thereto, and the data storage film may include silicon, a phase change material, nano-dot, and the like. The blocking insulating film may include an oxide film capable of blocking a charge. The tunnel insulating film may be formed of a silicon oxide film capable of charge tunneling.

The first and second gate stacks GST_A and GST_B may be covered with a first upper insulating film UI1, and the channel structure CH and the memory film ML may be extended to pass through the first upper insulating film UI1. The first upper insulating film UI1may be covered with a second upper insulating film UI2.

The bit line contact plug BCT may pass through the second upper insulating film UI2and be connected to the channel structure CH. The bit line BL may be connected to the bit line contact plug BCT and may be extended to overlap the second upper insulating film UI2.

Referring toFIG. 5B, the conductive patterns CPk to CPn shown inFIG. 5Amay extend to the contact area and form a stepped structure.FIG. 5Bshows conductive patterns CPm−2 to CPm (m is a natural number satisfying k<m<n) included in a portion of the stepped structure, but the present disclosure is not limited thereto. In an embodiment, the stepped structure of each of the first gate stack GST_A and the second gate stack GST_B shown inFIG. 4Amay be defined as the conductive patterns CPk to CPn and the lower conductive patterns are etched to form each of the steps of the stepped structure.

The dummy stack DM may include dummy interlayer insulating films ILDd and sacrificial films SC separated from the interlayer insulating films ILD and the conductive patterns CPk to CPn through the slit SI. The dummy interlayer insulating films ILDd and the sacrificial films SC may be alternately stacked and form a stepped structure.

The dummy interlayer insulating films ILDd may be formed of the same material as the interlayer insulating films ILD, and the sacrificial films SC may be formed of a material having an etch rate different from that of the interlayer insulating films ILD. In an embodiment, each of the dummy interlayer insulating films ILDd may be formed of an oxide film, and each of the sacrificial films SC may be formed of a nitride film.

Each of the stepped structure defined by the conductive patterns CPk to CPm and the interlayer insulating films ILD and the stepped structure of the dummy stack DM may be covered with a gap fill insulating film GI. The gap fill insulating film GI may alleviate a step difference due to the stepped structures. The first and second upper insulating films UI1and UI2described above with reference toFIG. 5Amay be extended to overlap the gap fill insulating film GI.

Each of the dummy stack DM, the gap fill insulating film GI, and the first and second upper insulating films UI1and UI2may be passed through by the contact plugs CTa11, CTa12, CTb11, and CTb12divided into the plurality of contact groups as described with reference toFIGS. 4A and 4B. Some of the contact plugs CTa11, CTa12, CTb11, and CTb12may pass through a corner CN defined at the boundary between the steps forming the stepped structure of the dummy stack DM. In an embodiment, the first contact plugs CTa11and CTa12shown inFIGS. 4A and 4Bmay pass through the corner CN defined at the boundary between the steps.

In a process of manufacturing the semiconductor memory device, a void or a seam may be generated at the corner CN defined at the boundary between the steps. Therefore, a void or a seam may be generated inside the first contact plugs CTa11and CTa12shown inFIGS. 4A and 4Balong the corner CN. According to an embodiment of the present disclosure, the contact plugs of each contact group, which are arranged along a direction in which the steps extend, are connected to the same upper line. Accordingly, operation reliability of the semiconductor memory device may be secured even though a bridge phenomenon occurs in which the contact plugs of each contact group, which are arranged along the direction in which the steps extend, are connected to each other due to the void or the seam.

Each of the first upper lines La1and La2and the second upper lines Lb1and Lb2shown inFIG. 4Bmay be disposed on the second upper insulating film UI2, and may be connected to the contact plugs of the corresponding contact group. In an embodiment, the first upper line La1may be connected to the first contact plug CTa11of the first contact group, and may be extended to overlap the second upper insulating film UI2and the first gate contact plug GCTa1.

Each of the first gate contact plugs GCTa1and GCTa2and the second gate contact plugs GCTb1and GCTb2shown inFIG. 4Bmay connect corresponding one conductive pattern and corresponding one upper line to each other. In an embodiment, the first gate contact plug GCTa1may pass through the first and second upper insulating films UI1and UI2and the gap fill insulating film GI to connect the conductive pattern CPm among the conductive patterns of the first gate stack GST_A and the first upper line La1to each other.

FIG. 6is a perspective view illustrating the contact area CTA of the semiconductor memory device shown inFIGS. 4A and 4B.

Referring toFIG. 6, in the contact area CTA, the first gate stack GST_A, the second gate stack GST_B, and the dummy stack DM may overlap the substrate SUB including the peripheral circuit30described with reference toFIG. 1.

The first contact plugs CTa11and CTa12of the first contact group Ga and the second contact plugs CTb11and CTb12of the second contact group Gb may be connected to the row decoder33of the peripheral circuit30described with reference toFIG. 1. The row decoder33may be disposed on a portion of the substrate SUB. In an embodiment, the row decoder33may be include a plurality of pass transistors. The pass transistors may include junctions defined in the substrate SUB. The junctions are regions defined by injecting at least one of an n-type impurity and a p-type impurity into portions of the substrate SUB. Namely, the substrate SUB may include the junctions for the row decoder33. In an embodiment, the first contact plugs CTa11and CTa12of the first contact group Ga and the second contact plugs CTb11and CTb12of the second contact group Gb may be connected to the junctions for the row decoder33, which are defined in the portions of the substrate SUB. An interconnection structure for connecting the row decoder33and the contact plugs CTa11, CTa12, CTb11, and CTb12to each other may be variously changed according to the design of the semiconductor memory device.

According to an embodiment of the present disclosure, the first contact group Ga and the second contact group Gb overlap different steps of the dummy stack DM. In addition, the first contact plugs CTa11and CTa12included in the first contact group Ga and the second contact plugs CTb11and CTb12included in the second contact group Gb are arranged in the direction in which the corresponding step extends. In addition, the first contact plugs CTa11and CTa12included in the first contact group Ga may be connected to the first gate contact plug GCTa1through the first upper line La1corresponding to the first contact plugs CTa11and CTa12, and the first gate contact plug GCTa1may be connected to one of the conductive patterns of the first gate stack GST_A. The second contact plugs CTb11and CTb12included in the second contact group Gb may be connected to the second gate contact plug GCTb1through the second upper line Lb1corresponding to the second contact plugs CTb11and CTb12, and the second gate contact plug GCTb1may be connected to one of the conductive patterns of the second gate stack GST_B. According to such a structure, operation reliability of the semiconductor memory device may be secured even though the first contact plugs CTa11and CTa12are connected along an extension direction of the corner CN at the boundary of the steps as shown inFIG. 5Bby the bridge phenomenon.

FIGS. 7A and 7Bare plan views illustrating the semiconductor memory device according to an embodiment.FIG. 7Ais a plan view showing a layout of the first and second gate stacks GST_A and GST_B and a dummy stack DM′, andFIG. 7Bis a plan view illustrating a layout of the bit lines BL and upper lines La1′, La2′, Lb1′, and Lb2′.

Referring toFIGS. 7A and 7B, the semiconductor memory device may include a cell area CA and a contact area CTA′.

The cell area CA is the same as the cell area CA described with reference toFIGS. 4A and 4B. The first gate stack GST_A and the second gate stack GST_B may be formed as the first gate stack GST_A and the second gate stack GST_B described with reference toFIGS. 4A and 4BandFIGS. 5A and 5B.

The plurality of channel structures CH may pass through each of the first gate stack GST_A and the second gate stack GST_B as described with reference toFIG. 4A. Each of the channel structures CH is disposed in the cell area CA. Each of the channel structures CH may be surrounded by the memory film ML as described with reference toFIG. 4A.

The channel structures CH may be connected to the bit lines BL through the bit line contact plugs BCT as described with reference toFIGS. 4A and 4B.

The contact area CTA′ is an area in which connection structures are disposed as described with reference toFIGS. 4A and 4B. The connection structures may include the gate contact plugs GCTa1, GCTa2, GCTb1, and GCTb2, the upper line lines La1′, La2′, Lb1′, and Lb2′, and the contact plugs CTa1and CTb1.

The gate contact plugs GCTa1, GCTa2, GCTb1, and GCTb2may be divided into the first gate contact plugs GCTa1and GCTa2connected to the first gate stack GST_A and the second gate contact plugs GCTb1and GCTb2connected to the second gate stack GST_B as described with reference toFIG. 4B.

The upper lines La1′, La2′, Lb1′, and Lb2′ may be spaced apart from each other. The upper lines La1′, La2′, Lb1′, and Lb2′ may be divided into first upper lines La1′ and La2′ respectively connected to the first gate contact plugs CTa11and CTa12, and second upper lines Lb1′ and Lb2′ respectively connected to the second gate contact plugs CTb11and CTb12. Each of the first upper lines La1′ and La2′ may be extended to overlap the first gate stack GST_A, the slit SI, and the dummy stack DM′. Each of the second upper lines Lb1′ and Lb2′ may be extended to overlap the second gate stack GST_B, the slit SI, and the dummy stack DM′.

The dummy stack DM′ may overlap the peripheral circuit30described with reference toFIG. 2in the contact area CTA′. The dummy stack DM′ may be disposed adjacent to the first gate stack GST_A and the second gate stack GST_B as described with reference toFIGS. 4A and 4B.

The dummy stack DM′ may be formed in a stepped structure including a plurality of steps. The dummy stack DM′ may be passed through by a plurality of contact plugs overlapping different steps. The contact plugs may be connected to the first and second upper lines La1, La2, Lb1, and Lb2, respectively. The contact plugs may be adjacent to each other in a diagonal direction with respect to the extension direction of the steps, in a plane parallel to the steps. For example, the dummy stack DM′ may include steps Sa′ to Sc′ extending in the first direction D1. The contact plugs may include the first contact plug CTa1and the second contact plug CTb1adjacent to each other in a diagonal direction with respect to the first direction D1. The first contact plug CTa1may overlap a boundary between the step Sa′ and the step Sb′ adjacent to each other, and the second contact plug CTb1may overlap the step Sc′. In an embodiment, the second contact plug CTb1may be spaced apart from sidewalls of the steps Sa′ to Sc′.

Each of the above-described first and second contact plugs CTa1and CTb1may be connected to corresponding upper line. In the embodiment, the first contact plug CTa1is connected to the first upper line La1′ among the first upper lines La1′ and La2′, and the second contact plug CTb1is connected to the second upper line Lb′ among the second upper lines Lb1′ and Lb2′.

Each of the first gate stack GST_A and the second gate stack GST_B may be formed of the same stack structure as described with reference toFIG. 5A. The dummy stack DM′ may be formed of the same stack structure as the dummy stack DM described with reference toFIG. 5B.

FIG. 8is a perspective view illustrating a contact area CTA′ of the semiconductor memory device shown inFIGS. 7A and 7B.

Referring toFIG. 8, in the contact area CTA′, the first gate stack GST_A, the second gate stack GST_B, and the dummy stack DM′ may overlap the substrate SUB including the peripheral circuit30described with reference toFIG. 1.

The first contact plug CTa1and the second contact plug CTb1may be connected to the row decoder33of the peripheral circuit30described with reference toFIG. 1. The row decoder33may be disposed in a portion of the substrate SUB. The interconnection structure for connecting the row decoder33and the contact plugs CTa1and CTb1to each other may be variously changed according to the design of the semiconductor memory device.

According to an embodiment of the present disclosure, the first upper line La1′ and the second upper line Lb1′ are respectively connected to the first contact plug CTa1and the second contact plug CTb1arranged in a diagonal direction with respect to the extension direction of the steps. According to such a structure, a bridge defect due to the void or the seam generated along an extension direction of the corner at the boundary of the steps may be reduced.

FIG. 9is a flowchart schematically illustrating a method of manufacturing the semiconductor memory device according to an embodiment.

Referring toFIG. 9, the semiconductor memory device may include a step S1of forming a preliminary stack passed through by the channel structures, a step S3of forming the stepped structure, a step S5of forming the conductive patterns, a step S7of forming the contact plugs, and a step S9of forming the upper lines.

FIGS. 10A to 10Eare perspective views illustrating the method of manufacturing the semiconductor memory device according to an embodiment.FIGS. 10A to 10Eillustrate an embodiment of the method of manufacturing the semiconductor memory device shown inFIGS. 4A and 4B, 5A and 5B, and 6.

Referring toFIGS. 9 and 10A, the step S1of forming the preliminary stack110passed through by the channel structures115may be performed on the substrate SUB after the substrate SUB including the peripheral circuit described with reference toFIG. 6is provided.

The step S1of forming the preliminary stack110passed through by the channel structures115may include a step of forming alternately stacked sacrificial films101and interlayer insulating films103and a step of forming the channel structure115surrounded by a memory film113.

The sacrificial films101and the interlayer insulating films103of the preliminary stack110may be formed of different materials. For example, the interlayer insulating films103may be formed of an oxide such as a silicon oxide film. The sacrificial films101may be formed of a material having an etch rate different from that of the interlayer insulating films103. For example, the sacrificial films101may be formed of a nitride such as a silicon nitride film.

The step of forming the channel structure115surrounded by the memory film113may include a step of forming channel holes passing through the sacrificial films101and the interlayer insulating films103, a step of forming the memory film113on sidewalls of each of the channel holes, and a step of filling a center area of each of the channel holes defined by the memory film113with the channel structure115. The memory film113may be formed of the same materials as the memory film ML described above with reference toFIG. 5A. Each of the channel structures115may be configured of the same materials as the channel structure CH described above with reference toFIG. 5A.

The step S3of forming the stepped structure120may be performed by etching the sacrificial films101and the interlayer insulating films103so that the stepped structure120may be defined by the sacrificial films101and the interlayer insulating films103. Although not shown in the drawing, in an etching process for forming the stepped structure120, an undercut area may be defined in layers on which the sacrificial films101are disposed. The undercut area may extend along the extension direction of the steps of the stepped structure120, and a void may be formed in the undercut area in a subsequent step. In an embodiment, the steps of the stepped structure120may extend in the first direction D1, and the undercut area may be defined in the first direction D1on each of the layers on which the sacrificial films101are disposed.

According to the embodiments described with reference toFIGS. 4A, 4B and 6, an alignment direction of the contact plugs connected to the same upper line is designed in consideration of a direction of the void defined along the undercut area. According to the embodiments described with reference toFIGS. 7A, 7B, and 8, the alignment direction of the contact plugs connected to different upper lines is designed in consideration of the direction of the void defined along the undercut area. Therefore, according to embodiments of the present disclosure, even though the void is generated by the etching process for forming the stepped structure120, an operation defect of the semiconductor memory device may be improved.

Referring toFIGS. 9 and 10B, before performing the step S5of forming the conductive patterns, a first slit131passing through the preliminary stack110may be formed.

A forming of the first slit131may include a step of forming of a gap fill insulating film121, a step of forming a first upper insulating film123on the gap fill insulating film121, and a step of etching the first upper insulating film123, the gap fill insulating film121, and the preliminary stack110.

The gap fill insulating film121may alleviate a step difference due to a stepped structure120shown inFIG. 10A. The first upper insulating film123may be extended to cover the channel structures115shown inFIG. 10A.

The preliminary stack110may be divided into a preliminary gate stack110G and a dummy stack110D by the first slit131.

Referring toFIGS. 9 and 10C, before performing the step S5of forming conductive patterns, the first slit131shown inFIG. 10Bmay be filled with an insulating film133.

FIGS. 10D and 10Eshow an embodiment of the step S5of forming the conductive patterns145shown inFIG. 9.

Referring toFIG. 10D, the step S5of forming the conductive patterns145may include a step of forming a second slit141passing through the preliminary gate stack110G shown inFIG. 10C, and a step of removing the sacrificial films101shown inFIG. 10Cthrough the second slit141. Hereinafter, regions in which the sacrificial films101are removed are defined as horizontal spaces143.

The second slit141may be connected to the first slit filled with the insulating film133. During a process of removing the sacrificial films to form the horizontal spaces143, the insulating film133may protect the dummy stack110D.

Each of the horizontal spaces143may be defined between the interlayer insulating films103adjacent to each other in the third direction D3.

Referring toFIG. 10E, the step S5of forming the conductive patterns145may include a step of filling each of the horizontal spaces143shown inFIG. 10Dwith a conductive material. Therefore, a first gate stack110Ga and a second gate stack110Gb separated from each other by the second slit141shown inFIG. 10Dand each including the conductive patterns145and the interlayer insulating films103alternately stacked may be formed.

Subsequently, a second upper insulating film151may be formed on the first upper insulating film123.

Referring toFIGS. 9 and 10E, the step S7of forming contact plugs passing through at least one of the second upper insulating film151, the first upper insulating film123, the gap fill insulating film121, the interlayer insulating films103, and the dummy stack110D may be performed.

FIG. 10Eshows contact plugs153b1and153b2corresponding to the second contact plugs CTb11and CTb12shown inFIG. 6, but the gate contact plugs GCTa1and GCTb1shown inFIG. 6, and the first contact plugs CTa11and CTa12of the first contact group Ga may be further formed in the step S7of forming the contact plugs.

Referring toFIGS. 9 and 10E, the step S9of forming the upper lines155aand155bon the second upper insulating film151may be performed. The upper lines155aand155bmay include a first upper line155aand a second upper line155bconnected to the first gate stack110Ga and the second gate stack110Gb, respectively.

The semiconductor memory devices shown inFIGS. 7A, 7B, and8may be formed using processes described with reference toFIGS. 10A to 10E.

FIG. 11is a block diagram illustrating a configuration of a memory system1100according to an embodiment.

Referring toFIG. 11, the memory system1100includes a memory device1120and a memory controller1110.

The memory device1120may be a multi-chip package configured of a plurality of flash memory chips. The memory device1120may include a stepped dummy stack disposed on a substrate including a peripheral circuit, contact groups passing through the stepped dummy stack, and upper lines connected to the contact groups, respectively. Each of the contact groups may include one contact plug or two or more contact plugs. The contact groups different from each other may pass through different steps of the stepped dummy stack. When each of the contact groups includes two or more contact plugs, the contact plugs of each of the contact groups may be arranged in a direction in which the corresponding step extends. The contact plugs connected to different upper lines may be adjacent in a diagonal direction with respect to the direction in which the steps extend.

The memory controller1110may be configured to control the memory device1120, and may include a static random access memory (SRAM)1111, a central processing unit (CPU)1112, a host interface1113, and an error correction block1114, and a memory interface1115. The SRAM1111is used as an operation memory of the CPU1112, the CPU1112performs various control operations for exchanging data of the memory controller1110, and the host interface1113includes a data exchange protocol of a host that is connected to the memory system1100. The error correction block1114detects an error included in data read from the memory device1120and corrects the detected error. The memory interface1115performs an interfacing with the memory device1120. The memory controller1110may further include a read only memory (ROM) or the like for storing code data for interfacing with the host.

The memory system1100described above may be a memory card or a solid state drive (SSD) in which the memory device1120and the memory controller1110are combined to each other. For example, when the memory system1100is an SSD, the memory controller1110may communicate with the outside (for example, a host) through at least one of various interface protocols such as a universal serial bus (USB), a multimedia card (MMC), a peripheral component interconnection-express (PCI-E), a serial advanced technology attachment (SATA), a parallel advanced technology attachment (PATA), a small computer small interface (SCSI), an enhanced small disk interface (ESDI), and integrated drive electronics (IDE).

FIG. 12is a block diagram illustrating a configuration of a computing system1200according to an embodiment.

Referring toFIG. 12, the computing system1200may include a CPU1220, a random access memory (RAM)1230, a user interface1240, a modem1250, and a memory system1210, which are electrically connected to a system bus1260. When the computing system1200is a mobile device, a battery for supplying an operation voltage to the computing system1200may be further included, and an application chipset, an image processor, a mobile DRAM, and the like may be further included.

The memory system1210may be configured of a memory device1212and a memory controller1211. The memory device1212may be configured identically to the memory device1120described above with reference toFIG. 11. The memory controller1211may be configured identically to the memory controller1100described above with reference toFIG. 11.

Embodiments of the present disclosure connects the contact plugs arranged in a direction, in which the stepped structure step extends, to the same upper line, or arranges the contact plugs so that the contact plugs respectively connected to different upper lines arrange in a direction different from the direction in which the step extends. Therefore, the embodiments of the present disclosure may reduce a bridge defect due to a void or a seam generated in the contact plug in a process of manufacturing the semiconductor memory device. Thus, the embodiments of the present disclosure present may improve yield reduction of the semiconductor memory device due to a process defect.