Mixer for homodyne RF receiver

A mixer of a homodyne RF receiver made from a CMOS process is provided. The mixer comprises a gain stage, a switch stage and a load stage. The gain stage receives a differential-typed RF signal and generating a first gained signal. The switch stage mixes the first gained signal and a LO signal to direct down-convert into a modulated signal. The load stage comprises a first transistor, an impedance element and a second transistor. The first transistor provides a low impedance to permit the modulated signal entering the load stage. The second transistor provides a high impedance to resist signals. The load stage converts the modulated signal to a second gained signal according to a first gain coefficient of the impedance element. The first transistor is a parallel pnp BJT, and the second transistor is a vertical npn bipolar BJT.

BACKGROUND OF THE INVENTION

(1) Field of the Invention

The present invention generally relates to a direct conversion radio frequency (RF) receiver, or a homodyne RF receiver, and particularly relates to a mixer for the homodyne RF receiver.

(2) Description of the Prior Art

Traditional Radio Frequency (RF) products usually employ a heterodyne RF receiver to receiving RF signal. In conventional wireless communication products, receivers usually utilize heterodyne technique, which is remarkable for its performance. Other kinds of receivers, such as the direct conversion RF receiver, the wideband IF receiver or the low IF receiver may be referred to deformed techniques of the heterodyne RF receiver.

The heterodyne RF receiver requires not only costly discrete devices but also application of external signal conversion. Heterodyne receivers convert RF signals from all channels into intermediate frequency (IF) signals by means of an external signal filter, and apply the IF signals to a local OSC and an external Voltage Control Oscillator (VCO) for conversion to base band signals, raising costs and limiting yield.

Therefore, direct conversion techniques, with lower power consumption and better suitability for multimedia systems, are widely used in receivers, omitting the need for IF signals conversion. The direct conversion RF receiver, also called a homodyne RF receiver, has another advantage of the system on a chip (SoC) application. The homodyne RF receiver can be regarded as a simplified heterodyne RF receiver, which has a zero intermediate frequency. So it also called a Zero IF receiver.

Please refer toFIG. 1. It shows a functional block diagram according to typical homodyne RF receiver. A typical homodyne RF receiver10at least comprises a LNA14, a mixer (16aor16b), a baseband amplifier (22aor22b), a low pass filter (23aor23b), an analog/digital convertor24and a DSP26. The homodyne RF receiver10can be separated into a I channel and a Q channel. The mixer16a, the baseband amplifier22a, the low pass filter23aand the ADC24aare belonging to the I channel. The other set of the same elements (16b,22b,23band24b) is belonging to the Q channel.

In some prior arts, there could be a pre-selection filter12before the LNA14to filter signal from the antenna, here, predetermined out-of-band signals would be filtered out. Sometimes, the pre-selection filter12also has the function of eliminating the image frequencies. The output point of the pre-selection filter12is coupled with the LNA14. For example, according to the specification of IEEE 802.11b, the received RF signal, the pre-selection filter12and the LNA14are all operated in a frequency between 2.4 GHz to 2.48 GHz. The output point of LNA14is coupled with the mixers16aand16b, individually. A local oscillator18provides LO signals. A frequency divider15generates phase difference of the LO signal for the I channel and the Q channel. Take the wireless specification of IEEE 802.11b for example, the local oscillator18is operated under a frequency of 2.4 GHz, to convert the signal to a low frequency signal nearby DC level.

Since the homodyne RF receiver direct down-converts the signal to nearby DC, performance of the mixer (16aor16b) is more sensitive to LO self-mixing and low frequency performance. In the mixer (16aor16b), as the desired signal converts to nearby DC, a folding load stage is implemented to adjust DC level for subsequent stage (i.e. the baseband amplifier22a, the low pass filter23aand the ADC24a. . . etc.). Mentioned folding load stage is implemented after the gain stage and the switch stage of the mixer. However, it places additional challenges to IIP3 (third order input intercept point) performance and noise figure performance.

SUMMARY OF THE INVENTION

Under the tendency of system on a chip (SoC), therefore an objective of the present invention is to provide a mixer for homodyne RF receiver without forgoing drawbacks.

Another objective of the present invention is to provide a mixer for homodyne RF receiver, which has reduced noise figure.

Another objective of the present invention is to provide a mixer for homodyne RF receiver, which has improved IIP3 performance.

A mixer of a homodyne RF receiver made from a CMOS process is provided. The mixer comprises a gain stage, a switch stage and a load stage. The gain stage receives a differential-typed RF signal and generating a first gained signal. The switch stage mixes the first gained signal and a LO signal to direct down-convert into a modulated signal. The load stage comprises a first transistor pair, an impedance element and a second transistor pair. The first transistor pair provides a low impedance to permit the modulated signal entering the load stage. The second transistor pair provides a high impedance to resist signals. The load stage converts the modulated signal to a second gained signal according to a first gain coefficient of the impedance element.

In one embodiment, the first transistor pair can be implemented by parallel pnp BJTs, which are parasitically formed on a MOS structure. This parallel pnp BJT is capable of improving IIP3 performance. In one embodiment, the second transistor pair may be implemented by vertical npn BJTs, which are also formed on a MOS structure. This vertical npn BJT is capable of reducing total output noise of the homodyne RF receiver.

These and other objectives of the present invention will no doubt become understandable to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment which is illustrated in the various figures and drawings

DESCRIPTION OF THE PREFERRED EMBODIMENT

The present invention provides a mixer for a homodyne RF receiver, which is able to be made from a complimentary metal-oxide semiconductor (CMOS) process. The provided mixer comprises a gain stage, a switch stage and a load stage.

According to related prior arts, the present invention generally relates to the mixer16a(or16b) shown inFIG. 1. What is deserved to be mentioned is that although the implemented circuit of some typical LNA14is similar with the gain stage of the present invention, however, they belong to separated issues.

Please refer toFIG. 2. It is a circuit diagram according to one of the present embodiments. As mentioned above, the present mixer30comprises a gain stage32, a switch stage34and a load stage36. The gain stage32receives RF signal40of differential type and generates a first gained signal42. Before the RF signal40is transferred to the gain stage32, a pre-selection filter (shown as numeral12ofFIG. 1) may be used to filter out out-of-band signals. A LNA (shown as numeral14ofFIG. 1), which may couple with the mixer30at the input point301, may be employed to amplify the filtered RF signal32.

According to the differential RF signal40, thus, the mixer30is designed as a balanced circuit. As shown inFIG. 2, the gain stage32, the switch stage34and the load stage36are separately a balanced circuit. The load stage36comprises a balanced first portion36aand second portion36b.

The switch stage34is used for mixing the first gained signal42and a local oscillation (LO) signal331to direct down-convert into a modulated signal44. The LO signal331is provided by a local oscillator33. The frequency of the LO signal331is near the frequency of the RF signal40, or the first gained signal42. Because the frequency of the first gained signal42and LO signal331are close to each other, the frequency of the modulated signal44, which is equal to the difference between the first gained signal42and LO signal331, is near to the DC frequency. In practice, the balanced status of the switch stage34is very important, in case distortion to the differential signal occurs.

According toFIG. 1and the described prior art, a homodyne RF receiver may comprise not only one mixer. The present mixer30is able to be applied in both the I channel or the Q channel. Therefore, the local oscillator33is coupled with a frequency divider35to generate the phase difference.

Please continue withFIG. 2, the load stage36comprises a pair of first transistors361, a pair of second transistors362and an impedance element (a pair of resistances368in this embodiment). The pair of first transistors361separately belong to the first portion36aor the second portion36b. The pair of the second transistor362separately belong to the first portion36aor the second portion36b. In this embodiment, a pair of resistances368are implemented for the impedance element. The resistances368belong to one of the first portion36aor the second portion36brespectively. However, in other embodiments a pair of capacitances is used to replace the pair of resistances368as the impedance element. In another embodiments, the impedance element is able to be the combination of resistance pair and capacitance pair.

Because of the parallel property of the balanced circuit, please only refer to one of the first portion36aor the second portion36b. The first transistor361provides a low impedance, corresponding to the high impedance of the first current source37. Hence, the modulated signal44tends to enter the load stage36. The second transistor provides a high impedance to resist signals. In practice, the second transistor362is coupled with a second resistance367to provide high impedance. Therefore the signal is lead to the output point303through the impedance element, which may be implemented by one resistance368and one capacitance365. The impedance element has a first gain coefficient. As a result, the load stage36converts the modulated signal44to a second gained signal46according to the first gain coefficient (of the resistance368and the capacitance365). The second gained signal46will be further processed by the following circuit of the homodyne RF receiver.

In practice, the first current source37provides needed current for the switch stage34and the load stage36. The current flows to the first transistor361will be the difference between the first current source37and the second current source371, the second current source371being coupled with the gain stage32.

For balancing the first portion36aand the second portion36b, the pair of the first transistors361have gate terminals which are connected to a common node, in other words, common gate. The contact of the common gate of the first transistors361is coupled with a bias31. The pair of the second transistors362have common gate. The contact of the common gate of the pair of the second transistors362is coupled with a CMFB (common feedback)38for detecting unbalance of signals and for feedback. Or in another embodiment, the pair of the second transistor362form a current mirror, as shown inFIG. 4. These embodiments can efficiently eliminate the drawback of DC offset.

In the embodiment according toFIG. 2, the second transistor362is a vertical npn bipolar junction transistor (BJT), which is parasitically formed on a MOS structure.FIG. 3shows a cross section view of the vertical npn BJT.

Considering to that there is no npn in conventional digital CMOS process. The exemplary embodiment of the present invention adds a deep N-well mask in a conventional n-MOS module to form the needed vertical npn BJT. The original source or drain N+ doped area: (198′) forms a emitter region. P-well191from the n-MOS module forms a base region. The added deep N-well119forms a collector region. N-well192from p-MOS module and N+ doped area (198) form sinker implant to reduce resistance of the collector (the deep N-well119). P+ doped area (197) can reduce resistance of the base (P-well191). Thus, a vertical npn BJT is here provided by parasitically formation on a MOS structure.

Through the present vertical npn BJT for the second transistor362, the noise to signal ratio of homodyne RF receiver can be efficiently suppressed. Even though the fTof this vertical npn BJT can only achieve 2 GHz, which is not good enough for typical BJT. However, it is good enough for analog operation, which requires a fTsmaller than 50 Hz. Especially comparing with the n-MOS, the vertical npn BJT has a 1/f noise; which is 100 times less than the n-MOS. Obviously, the present invention has remarkable contribution in the noise issue of the homodyne RF receiver.

Please refer toFIG. 4. It is a circuit diagram according to another present embodiments. It has been found that IIP3 can be degraded due to the cascode p-MOS, as the first transistor361, in the folding load stage36. Hence, the present invention replaces the traditional p-MOS to a lateral pnp BJT. Higher gm from the lateral pnp BJT provides cleaner spectrum of the second gained signal46at the differential output point303.

Considering there is no high performance pnp in conventional CMOS process, and also considering to the poor performance of a vertical pnp BJT, which is parasitically formed on a MOS structure like the embodiment shown asFIG. 3, the mentioned lateral pnp BJT is employed for the first transistor361in the present invention. The vertical pnp BJT (not shown) has poor performance due to there is no isolated collector terminal existing in the parasitic structure, and also because of the much lower β value (only about 2.5).

Under these reasons, a parasitic pnp existing in p-MOS module is used. Please refer toFIG. 5AandFIG. 5B,FIG. 5Ashows a cross section view of a p-MOS module;FIG. 5Bshows a cross section view of the parasitic parallel pnp BJT. The p-MOS shown inFIG. 5Ahas to be turned off. In practice, turning off the p-MOS by setting the gate bias to VDD. As a result, the source or drain terminals (P+ doped area) in the p-MOS module can be used as the emitter298′ or the collector298. The N-well can be used as base contact.

From simulation, the IIP3 value can be degraded about 3˜4 dBm from the mixer's gain stage32and switch stage34because of using a p-MOS as the first transistor361. Using the lateral pnp BJT according to the described embodiment, the IIP3 can be maintained or even a little bit better. Depending on the cellular/wireless system's specification, less than 10 MHz operation is required from the load stage36. The fTvalue (the measure of “cut-off frequency”) of the lateral pnp BJT, which is parasitically formed from CMOS process, is only about 1 GHz or hundreds MHz. Obviously, in this aspect, the performance of the present invention have exceeded the requirement.

Please refer toFIG. 6. It is a circuit diagram according to another present embodiments. This embodiment combines the advantages of the embodiments according toFIG. 2andFIG. 4. The first transistor361is a lateral pnp BJT, which is parasitically formed on a p-MOS structure from CMOS process. The second transistor362is a vertical npn BJT, which is parasitically formed on a n-MOS structure from CMOS process. According to the foregoing embodiments, the present invention has provided a mixer for homodyne RF receiver having reduced noise to signal ratio. Besides, the present mixer also has improved IIP3 performance. The problem of DC offsets is well controlled by the present balanced circuit. Furthermore, the present invention utilizing CMOS process to provide a mixer for homodyne RF receiver, so the present invention can readily be utilized by using existed facilities and also meet the tendency of SoC.