Display control apparatus, display control method, and computer readable medium

A display image generation unit generates a first display image to be output to a display apparatus and a second display image to be output to a slave display control terminal. A first output unit outputs the first display image to the display apparatus. A second output unit outputs the second display image to the slave display control terminal. A frame progress computation unit controls a timing of the output of the first display image by the first output unit based on a synthesized image delay time being a delay time from the output of the second display image to the slave display control terminal by the second output unit to output of a synthesized image from the slave display control terminal to the display apparatus, the synthesized image being obtained by synthesizing a third display image with the second display image in the slave display control terminal.

TECHNICAL FIELD

The present invention relates to a display control apparatus, a display control method, and a display control program.

BACKGROUND ART

In multi-screen display systems, a display image is output to each of display apparatuses to which a plurality of display control terminals are respectively connected.

In a conventional multi-screen display system, a display control command transmission apparatus instructs the plurality of display control terminals that operate completely independently to perform contents reproduction. Each display control terminal cooperates with a time synchronization server apparatus and an offset time generation apparatus and performs display timing synchronization among the display control terminals, thereby synchronizing display images on all display apparatuses.

CITATION LIST

Patent Literature

Patent Literature 1: JP 2013-55597 A

SUMMARY OF INVENTION

Technical Problem

In the technology in Patent Literature 1, however, there is a problem that the display control command transmission apparatus, the time synchronization server apparatus, and the offset time generation apparatus are necessary, in addition to the display control terminals and the display apparatuses, so that the configuration and control are complex.

An object of the present invention is to solve the problem as mentioned above. That is, a main object of the present invention is to match output timings of display images to a plurality of display apparatuses by a simple configuration and simple control.

Solution to Problem

A display control apparatus according to the present invention, which is connected to a first display apparatus and a cooperation apparatus connected to a second display apparatus, includes:

a display image generation unit to generate a first display image to be output to the first display apparatus and a second display image to be output to the cooperation apparatus;

a first output unit to output the first display image to the first display apparatus;

a second output unit to output the second display image to the cooperation apparatus; and

an output timing control unit to control a timing of output of the first display image by the first output unit, based on a synthesized image delay time being a delay time from the output of the second display image to the cooperation apparatus by the second output unit to output of a synthesized image from the cooperation apparatus to the second display apparatus, the synthesized image being obtained by synthesizing a third display image with the second display image in the cooperation apparatus.

Advantageous Effects of Invention

According to the present invention, the output timing of the first image to the first display apparatus and an output timing of the synthesized image to the second display apparatus can be matched by a simple configuration and simple control.

DESCRIPTION OF EMBODIMENTS

Hereinbelow, embodiments of the present invention will be described with use of the drawings. In following description and the drawings on the embodiments, elements provided with identical reference characters represent identical elements or corresponding elements.

Description of Configuration

FIG. 1illustrates a configuration example of a multi-screen synthesizing display system according to this embodiment.

The multi-screen synthesizing display system according to this embodiment is configured with a master display control terminal100, a slave display control terminal200, a display apparatus10and a display apparatus20.

The master display control terminal100is connected to the display apparatus10. The slave display control terminal200is connected to the display apparatus20. Further, the master display control terminal100is connected to the slave display control terminal200.

The display apparatus10and the display apparatus20have a same display size in this embodiment. However, the display apparatus10and the display apparatus20may have different display sizes.

The master display control terminal100corresponds to a display control apparatus. The slave display control terminal200corresponds to a cooperation apparatus. The display apparatus10corresponds to a first display apparatus. The display apparatus20corresponds to a second display apparatus. Operations that are performed by the master display control terminal100correspond to a display control method.

The master display control terminal100is a computer that is implemented by a hardware configuration illustrated inFIG. 15, for example. The slave display control terminal200is a computer that is implemented by a hardware configuration illustrated inFIG. 16, for example.

The master display control terminal100includes a processor911, a storage device912, and an input/output interface913, as hardware.

Programs for implementing functions of a display image generation unit101, a second output unit102, a first output unit103, and a frame progress computation unit107illustrated inFIG. 1are stored in the storage device912.

Then, the processor911executes these programs, thereby performing the operations of the display image generation unit101, the second output unit102, the first output unit103, and the frame progress computation unit107that will be described later.

FIG. 15schematically illustrates a state where the processor911executes the programs to implement the functions of the display image generation unit101, the second output unit102, the first output unit103, and the frame progress computation unit107. The programs to implement the functions of the display image generation unit101, the second output unit102, the first output unit103, and the frame progress computation unit107correspond to a display control program.

The input/output interface913is an interface circuit between the slave display control terminal200and the display apparatus10.

The slave display control terminal200includes a processor921, a storage device922, and an input/output interface923, as hardware.

Programs for implementing functions of a display image generation unit201, an image acquisition unit204, an image synthesis unit205, a synthesized image output unit206, and a delay time measurement unit209illustrated inFIG. 1are stored in the storage device992.

Then, the processor921executes these programs, thereby performing operations of the display image generation unit201, the image acquisition unit204, the image synthesis unit205, the synthesized image output unit206, and the delay time measurement unit209that will be described later.

FIG. 16schematically illustrates a state where the processor921executes the programs to implement the functions of the display image generation unit201, the image acquisition unit204, the image synthesis unit205, the synthesized image output unit206, and the delay time measurement unit209.

The input/output interface923is an interface circuit between the master display control terminal100and the display apparatus20.

Subsequently, an outline of the operations of the master display control terminal100and the slave display control terminal200will be described before the components of the master display control terminal100and the slave display control terminal200illustrated inFIG. 1are described.

The master display control terminal100divides the master original display image110into a master display image111and a slave display image112. The master display image111is output to the display apparatus10from the master display control terminal100. The slave display image112is output to the slave display control terminal200from the master display control terminal100.

With the above arrangement, the master display image111is displayed on the display apparatus10, and the synthesized image250is displayed on the display apparatus20.

The master display image111is directly output from the master display control terminal100to the display apparatus10. On the other hand, the slave display image112is output from the master display control terminal100to the slave display control terminal200, is further synthesized with the slave original display image210in the slave display control terminal200, and is output from the slave display control terminal200to the display apparatus20, as the synthesized image250.

In order to display the master display image111and the synthesized image250without visual discomfort, it is necessary to adjust an output timing of the master display image111from the master display control terminal100to the display apparatus10. Specifically, the master display control terminal100needs to adjust the output timing of the master display image111, in association with a delay time (hereinafter referred to as a synthesized image delay time) from the output of the slave display image112to the slave display control terminal200to the output of the synthesized image250from the slave display control terminal200to the display apparatus20.

In this embodiment, the master display control terminal100adjusts the output timing of the master display image111, based on the synthesized image delay time, thereby causing the master display image111and the synthesized image250to be displayed without the visual discomfort.

The master display image111corresponds to a first display image, the slave display image112corresponds to a second display image, and the slave original display image210corresponds to a third display image.

Subsequently, details of the components of the master display control terminal100and the slave display control terminal200will be described.

Referring toFIG. 1, the display image generation unit101repeatedly generates the master original display image110at certain image generation intervals.

That is, the display image generation unit101repeatedly generates the master display image111to be output to the display apparatus10and the slave display image112to be output to the slave display control terminal200at the certain image generation intervals.

The process that is performed by the display image generation unit101corresponds to a display image generation process.

The first output unit103repeatedly outputs the master display image111to the display apparatus10at certain output intervals.

The first output unit103buffers each master display image111generated by the display image generation unit101. The first output unit103selects, from among each master display image111that has been buffered, an output target master display image and outputs the selected master display image111to the display apparatus10, based on a notification from the frame progress computation unit107that will be described later.

The process that is performed by the first output unit103corresponds to a first output process.

The second output unit102repeatedly outputs the slave display image112to the slave display control terminal200at the certain output intervals.

The process that is performed by the second output unit102corresponds to a second output process.

The frame progress computation unit107controls the timing of the output of the master display image111by the first output unit103, based on the synthesized image delay time. As described above, the synthesized image delay time is the delay time from the output of the slave display image112to the slave display control terminal200by the second output unit102to the output of the synthesized image250obtained by the synthesis of the slave original display image210with the slave display image112in the slave display control terminal200from the slave display control terminal200to the display apparatus20.

The frame progress computation unit107controls the timing of the output of the master display image111by the first output unit103so that the output of the synthesized image250to the display apparatus20by the slave display control terminal200and the output of the master display image111to the display apparatus10by the first output unit103are concurrently performed.

When there is no deviation between a cycle of the output of the master display image111by the first output unit103and a cycle of the output of the slave display image112by the second output unit102, the frame progress computation unit107controls the timing of the output of the master display image111as follows. That is, the frame progress computation unit107adjusts the timing of the output of the master display image111by the first output unit103, based on a division value that is obtained by dividing the synthesis delay time by the image generation interval of the display image generation unit101. Specifically, the frame progress computation unit107notifies the division value (with a portion after the decimal point thereof carried up) (hereinafter referred to as the number of frames that have progressed) to the first output unit103. The first output unit103specifies, among each master display image111that has been buffered, one or more master display images111corresponding to the division value, as an output target, and outputs the specified one or more master display images111of the output target.

When there is a deviation between the cycle of the output of the master display image111by the first output unit103and the cycle of the output of the slave display image112by the second output unit102, the frame progress computation unit107adjusts the timing of the output of the master display image111as follows. That is, the frame progress computation unit107adjusts the timing of the output of the master display image111by the first output unit103, based a division value (with a portion after the decimal point thereof carried up) (hereinafter referred to as the number of frames that have progressed) that is obtained by dividing a total time of the deviation and the synthesized image delay time by the image generation interval of the display image generation unit101. Specifically, the frame progress computation unit107notifies the division value to the first output unit103. The first output unit103specifies, among each master display image111that has been buffered, one or more master display images111corresponding to the division value, as an output target, and outputs the specified one or more master display images111of the output target.

The synthesized image delay time is notified from the delay time measurement unit209that will be described later.

The frame progress computation unit107corresponds to an output timing control unit. The process that is performed by the frame progress computation unit107corresponds to an output timing control process.

The display image generation unit201generates the slave original display image210at the certain image generation intervals.

The image acquisition unit204acquires the slave display image112from the second output unit102, in synchronization with the output cycle of the second output unit102.

The image synthesis unit205acquires the slave original display image210from the display image generation unit201and buffers the acquired slave original display image210. The image synthesis unit205acquires the slave display image112from the image acquisition unit204and buffers the acquired slave display image112. Then, the image synthesis unit205synthesizes the slave original display image210and the slave display image112at certain synthesis intervals, thereby generating the synthesized image250.

The synthesized image output unit206outputs the synthesized image250at the certain output intervals.

The delay time measurement unit209measures the synthesized image delay time. That is, the delay time measurement unit209measures the delay time from the acquisition of the slave display image112by the image acquisition unit204to the output of the synthesized image250to the display apparatus20by the synthesized image output unit206, as the synthesized image display time.

Then, the delay time measurement unit209notifies the measured synthesized image delay time to the frame progress computation unit107.

Description of Operations

Subsequently, the operations of the master display control terminal100and the slave display control terminal200according to this embodiment will be described. An example of displaying the display images illustrated inFIG. 2will be described below. In the following description, it is assumed that there is the deviation between the output cycle of the first output unit103and the output cycle of the second output unit102. Further, in the following description, it is assumed that the frame progress computation unit107holds the deviation between the output cycle of the first output unit103and the output cycle of the second output unit102, as a predetermined value. If the frame progress computation unit107does not hold the deviation between the output cycles as the predetermined value, the frame progress computation unit107computes a deviation for each frame, using a time when the first output unit103outputs the master display image111to the display apparatus10and a time when the second output unit102outputs the slave display image112to the slave display terminal200, when the frame progress computation unit107computes the number of frames that have progressed.

FIG. 3illustrates an operation example of the master display control terminal100.

In step ST1, the display image generation unit101generates the master original display image110and frame identification information. The frame identification information is identification information of the master original display image110, and it is assumed in this embodiment that the frame identification information is a sequence number set in the master original display image110.

In step ST2, the display image generation unit101generates the master display image111and the slave display image112from the master original display image110. Then, the display image generation unit101writes the master display image111into the frame buffer of the first output unit103and writes the slave display image112into the frame buffer of the second output unit102. The display image generation unit101notifies the frame identification information to the first output unit103and the second output unit102.

In step ST3, the second output unit102waits for a screen update timing. The second output unit102detects the screen update timing, using a vertical synchronization signal, for example.

In step ST4, the second output unit102selects an output target slave display image112.

In step ST5, the second output unit102outputs the selected slave display image112to the image acquisition unit204.

In the slave display control terminal200, the image acquisition unit204acquires the slave display image112and stores the slave display image112in a frame buffer, which will be described later. The image acquisition unit204notifies, to the delay time measurement unit209, a time when the image acquisition unit204has acquired the slave display image112.

In step ST6, the frame progress computation unit107computes the number of frames that have been progressed, using an image generation interval and a total time of a synthesized image delay time and the deviation between the output cycles of the first output unit103and the second output unit102. The method of computing the number of the frames that have progressed will be described later. The frame progress computation unit107notifies, to the first output unit103, the number of the frames that have been progressed.

In step ST7, the frame progress computation unit107is notified of the synthesized image delay time from the delay time measurement unit209and stores the notified synthesized image delay time in the storage device912.

In step ST8, the first output unit103waits for a screen update timing. The first output unit103detects the screen update timing, using a virtual synchronization signal, for example.

In step ST9, the first output unit103selects an output target master display image111from among each master display image111stored in the frame buffer, based on the number of the frames that have progressed notified from the frame progress communication unit108.

As illustrated inFIG. 2, the display image generation unit101may divide the master original display image110into the master display image111and the slave display image112. Alternatively, the display image generation unit101may directly generate the master display image111and the slave display image112without generating the master original display image110.

Referring toFIG. 3, ST3to ST5and ST6to ST10are set to concurrent processes. However, ST3to ST5and ST6to ST10may be sequentially executed. The order of each step inFIG. 3may be changed in a range in which no contradiction occurs.

FIG. 4illustrates operation examples of the display image generation unit201, the image synthesis unit205, and the synthesized image output unit206of the slave display control terminal200.

In step ST11, the display image generation unit201generates the slave original display image210.

In step ST12, the image synthesis unit205generates the synthesized image250by synthesizing the slave original display image210and the slave display image112acquired from the second output unit102by the image acquisition unit204. The image synthesis unit205writes the synthesized image250into the frame buffer of the synthesized image output unit206.

In step ST13, the synthesized image output unit206waits for an image update timing.

In step ST15, the synthesized image output unit206selects an output target synthesized image250.

In step ST16, the synthesized image output unit206outputs the selected synthesized image250to the display apparatus20.

Further, the synthesized image output unit206notifies, to the delay time measurement unit209, a time when the synthesized image output unit206has output the synthesized image250.

FIG. 5illustrates an operation example of each of the image acquisition unit204and the delay time measurement unit209of the slave display control terminal200.

In step ST17, the image acquisition unit204acquires the slave display image112and stores the slave display image112in the frame buffer.

In step ST18, the image acquisition unit204notifies, to the delay time measurement unit209, a time when the image acquisition unit204has acquired the slave display image112.

In step ST19, the delay time measurement unit209computes the synthesized image delay time, using the acquisition time of the slave display image112notified in step ST18and the output time of the synthesized image250notified in step ST16inFIG. 4. The delay time measurement unit209subtracts the acquisition time of the slave display image112from the output time of the synthesized image250, thereby obtaining the synthesized image delay time.

Then, the delay time measurement unit209notifies the synthesized image delay time to the frame progress computation unit107.

Subsequently, a description will be given about the process of computing a number F of frames that have progressed, by the frame progress computation unit107, illustrated in step ST6inFIG. 3.

The frame progress computation unit107computes the number F of the frames that have progressed, based on the following expressions:
F=ceil((D1+D2)/V)  Expression (1)
D2=T2−T1  Expression (2)
D1=T3−T2  Expression (3)

F is the number of the frames that have progressed, that is, a value (a buffered amount) obtained by conversion of a change in output times of the master display image111and the synthesized image250(a progress degree of one to the other) into the number of the frames for a period from a point of time of output of a previous frame to a point of time of output of a current frame. D1is a synthesized image delay time notified from the delay time measurement unit209. D2is a deviation time between the output cycle of the first output unit103and the output cycle of the second output unit102. V is the image generation interval of the display image generation unit101. ceil (x) indicates a process of rounding up digits after the decimal point of a numerical value. T1is a time of output of the master display image111by the first output unit103. T2is a time of output of the slave display image112by the second output unit102. T3is a time of output of the synthesized image by the synthesized image output unit206.

When there is no deviation between the output cycle of the first output unit103and the output cycle of the second output unit102, namely, when T1=T2, D2=0. Thus, the frame progress computation unit107can compute the number of frames that have progressed, using F=ceil (D1/V).

Subsequently, a description will be given about the process of selecting the output target master display image111by the first output unit103, illustrated in ST9inFIG. 3.

FIGS. 6, 7 and 8each illustrate display image output timings of the display image generation unit101, the first output unit103, the second output unit102, the image acquisition unit204, the image synthesis unit205, and the synthesized image output unit206.

D1, D2, and V are the same as those illustrated in Expression (1). It is assumed herein that an output interval of the first output unit103and an output interval of the second output unit102are equal to the image generation interval V of the display image generation unit101.

A(t) is the number of frames of the master display image111which are to be output by the first output unit103at time t and have waited in the buffer. A(t) can be obtained by the following expressions (4) and (5).

A(t−V) is the number of frames of the master display image111which are set to be output by the first output unit103at time (t−V) and have waited in the first output unit103.
A(t)=A(t−V)+F(t) ifF(t)≤0 Expression(4)
A(t)=A(t−V)+1 ifF(t)>0 Expression(5)

If F(t)=3 and A(t−v)=5, for example, A(t)=8. On the other hand, if F(t)=−1 and A(t−v)=5, A(t)=4.

FIG. 6illustrates states of the master display control terminal100and the slave display control terminal200immediately after activation. It is assumed that A(t) immediately after the activation is 0. In this case, until the delay time measurement unit209acquires D1and notifies D1to the frame progress computation unit107, an oldest master display images111that have been buffered is output, with A(t) regarded as 0. If a time when the frame progress computation unit107could acquire D1for the first time is t, the frame progress computation unit107obtains the number F(t) of frames that have progressed, using latest D1(t) and D2(t). In the case ofFIG. 6, F(t)=3 is obtained. If F(t) is positive, output of the master display image111by the first output unit103is advanced too much from output of the synthesized image250image synthesis unit205by the synthesized image output unit206. Thus, the first output unit103suspends the output for F(t). In the case ofFIG. 6, the output of the first output unit103is advanced by 3 frames. Thus, the first output unit103keeps on displaying the master display image111displayed at the time of time t for 3 frames. While the same master display image111is being displayed, the number F(t) of frames that have progressed and the number of frames of the master display image111that have waited change. At time t+V, F(t+V)=2 is obtained from Expression (1), and A(t+V)=1 is obtained from Expression (5) because the master display image111to be output has waited for 1 frame. Similarly, at time t+2V, F(t+2V)=1 and A(t+2V)=2 are obtained. Then, at a time when F(t+3V)=0 and A(t+3V)=3 are obtained, the master display image111and the synthesized image250are simultaneously displayed.

FIG. 7illustrates a case where at time t when the first output unit103and the synthesized image output unit206already display a same frame of the master original display image110, F(t)=0 is continued. In this case, A(t)=3 and D2+D1, that is, T3−T1is less than the V. Thus, F(t)=0 is obtained from Expression (1). A(t) does not need to be changed. Thus, the first output unit103selects an oldest one of the master display images111that are buffered.

FIG. 8illustrates a case where at time t when the first output unit103and the synthesized image output unit206already display a same frame of the master original display image110, as inFIG. 7, F(t)=−1. If F(t) is negative, the synthesized image output unit206is advanced by (−1×F(t)) frame(s). Thus, the first output unit103skips the (−1×F(t)) frame(s) sequentially, starting from an oldest one of the master display images111that are buffered, and selects the master display image111that is the oldest except for the skipped frame(s), thereby reducing a difference between the first output unit103and the synthesized image output unit206.

A(t) obtained inFIG. 6in the state where the master display image111and the slave display image112are simultaneously displayed may be acquired from an actual operation as in this embodiment or may be set by measurement in advance.

By disposing a mechanism for synchronizing output timings of the second output unit102, the first output unit103, and the synthesized image output unit206at each of the master display control terminal100and the slave display control terminal200, display timings of a same frame of the display apparatus10and the display apparatus20can be completely aligned.

The respective processes illustrated inFIGS. 3 to 5may be concurrently performed.

The above description has been given about an example where the image acquisition unit204notifies the acquisition timing of the slave display image112to the delay time measurement unit209, the synthesized image output unit206notifies the output timing of the synthesized image250to the delay time measurement unit209, and the delay time measurement unit209measures the synthesized image delay time. Instead of this, it is acceptable that the image acquisition unit204transfers the slave display image112to the delay time measurement unit209and the synthesized image output unit206transfers the synthesized image250to the delay time measurement unit209, concurrently with output of the synthesized image250to the display apparatus20. Then, it is also acceptable that the delay time measurement unit209measures the synthesized image delay time, based on the acquisition timing of the slave display image112and the acquisition timing of the synthesized image250.

Description of Effects of Embodiment

As described above, according to this embodiment, the multi-screen synthesizing display system can be formed with a simple configuration and simple control.

That is, according to this embodiment, the timing of displaying the synthesized image250on the display apparatus20and the timing of displaying the master display image111on the display apparatus10can be matched with the simple configuration and the simple control.

Further, according to this embodiment, the synthesized image250can be generated in the slave display control terminal200by synthesizing the slave display image112generated by the master display control terminal100and the slave original display image210generated by the slave display control terminal200. Then, the synthesized image250can be displayed on the display apparatus20and the master display image111can be displayed on the display apparatus10.

In this embodiment, a function of changing image contents of each of the master display image111, the slave display image112, and the slave original display image210is added to the multi-screen synthesizing display system in the Embodiment 1.

Description of Configuration

FIG. 9illustrates a configuration example of a multi-screen synthesizing display system according to this embodiment.

Referring toFIG. 9, an input unit400is used for inputting by a user or a different apparatus, event information based on a schedule, into a master display control terminal100. The input unit400is an input apparatus including a touch panel or the like, for example. The event information indicates an event such as clicking of a mouse or arrival of a display start time of subsequent contents in the schedule.

A reproduction data storage unit410stores moving picture data, image data, video data for reproducing an image of a program or the like, layout information indicating disposition and the drawing order of the image, the event information corresponding to the input from the input unit400, and so on.

A hardware configuration example of the master display control terminal100is as illustrated inFIG. 15, and a hardware configuration example of the slave display control terminal200is as illustrated inFIG. 16.

A difference from Embodiment 1 will be mainly described below. Matters that are not described below are the same as those in Embodiment 1.

Before components of the master display control terminal100and the slave display control terminal200illustrated inFIG. 9are described, an outline of operations of the master display control terminal100and the slave display control terminal200according to this embodiment will be described.

FIG. 10illustrates examples of display images according to this embodiment.

Since a master original display image110, a master display image111, a slave display image112, and a slave original display image210are the same as those illustrated inFIG. 2, description will be omitted.

In an altered master original display image113, contents130of the master original display image110is magnified.

An altered master display image114is a display image that has been divided from the altered master original display image113and is to be displayed on a display apparatus10.

An altered slave display image115is a display image that has been divided from the altered master original display image113and is to be output to the slave display control terminal200.

If dispositions of contents230and231of the slave original display image210are not changed, a part of the magnified contents130is hidden by the contents231due to the magnification of the contents130, as illustrated in the altered master display image114and an inappropriate synthesized image252.

In order to avoid this situation, in this embodiment, the dispositions of the contents230and231of the slave original display image210are altered as in an altered slave original display image211. Since the dispositions of the contents230and the contents231have been altered as in the altered slave original display image211, the situation where the part of the magnified contents130is hidden by the contents231can be avoided, even if an altered synthesized image251that is obtained by synthesizing the altered slave display image115and the altered slave original display image211is displayed on a display apparatus20and the altered master display image114is displayed on the display apparatus10.

In this embodiment, the altered master display image114corresponds to a first display image. The altered slave display image115corresponds to a second display image. The slave original display image210corresponds to a third display image, and the altered slave original display image211corresponds to a third display image after the image alteration process.

Subsequently, details of the components of the master display control terminal100and the slave display control terminal200will be described.

A layout instruction unit310instructs a display image generation unit101and a layout instruction relay unit320to alter, display, or delete a layout of contents according to the event information from the input unit400and based on event processing information obtained from the reproduction data storage unit410. The event processing information is information that describes processing contents when an event occurs. To take an example, a process of reproducing a specified movie when a mouse click event occurs or the like is described in the event processing information.

The display image generation unit101performs an image alteration process for the master original display image110, based on the instruction of the layout instruction unit310. In other words, as illustrated inFIG. 10, the display image generation unit101alters a position and a size of the contents130of the master original display image110, as in the altered master original display image113.

A frame progress computation unit107includes a function of computing a slave display image generation time that is a delay time from generation of the master original display image110by the display image generation unit101to output of the altered slave display image115by a second output unit102.

The layout instruction relay unit320instructs a display image generation unit201to alter a position of contents that is disposed on the slave original display image210, based on the instruction from the layout instruction unit310.

The display image generation unit201performs an image alteration process for the slave original display image210, according to the instruction from the layout instruction relay unit320. That is, as illustrated inFIG. 10, the display image generation unit201alters positions of the contents230and the contents231of the slave original display image210, as in the altered slave original display image211.

A delay time measurement unit209measures a synthesized image delay time, as in Embodiment 1. In this embodiment, however, the delay time measurement unit209measures, as the synthesized image delay time, a delay time from output of the altered slave display image115to the slave display control terminal200by the second output unit102to output of the altered synthesized image251from a synthesized image output unit206to the display apparatus20, the altered synthesized image251being obtained by synthesis of the altered slave original display image211after the image alteration process by the display image generation unit201with the display image of the altered slave display image115.

Further, the delay time measurement unit209measures a slave original display image generation time that is a delay time from generation of the altered slave original display image211after the image alteration process by the display image generation unit201to the output of the altered synthesized image251obtained by the synthesis of the altered slave original display image211with the display image of the altered slave display image115from the synthesized image output unit206to the display apparatus20. Further, the delay time measurement unit209computes a layout execution delay time being a delay time of generation of the master original display image110by the display image generation unit101and a delay time of generation of the slave original display image210by the display image generation unit201, using the slave display image generation time that is acquired from the frame progress computation unit107and the output time of the slave original display image.

After the layout instruction relay unit320has received the instruction from the layout instruction unit310, the layout instruction relay unit320instructs the display image generation unit201to alter the layout, with a delay corresponding to the layout execution delay time.

An image synthesis unit205acquires the altered slave original display image211from the display image generation unit201and buffers the altered slave original display image211. The image synthesis unit205acquires the altered slave display image115from an image acquisition unit204and buffers the acquired altered slave display image115. Then, the image synthesis unit205synthesizes the altered slave original display image211and the altered slave display image115, thereby generating the altered synthesized image251.

Since the components other than those mentioned above are the same as those in Embodiment 1, description will be omitted.

Description of Operations

FIG. 11illustrates an operation example of the master display control terminal100according to this embodiment.

In step ST20, the layout instruction unit310detects an input of event information.

In step ST21, the layout instruction unit310determines a layout alteration in each of the master original display image110and the slave original display image210, based on the input event information.

In step ST22, the layout instruction unit310notifies layout information notifying the determined layout alteration of the master original display image110to the display image generation unit101and outputs layout information notifying the determined layout alteration of the slave original display image210to the layout instruction relay unit320.

In step ST23, based on the layout information from the layout instruction unit310, the display image generation unit101magnifies the contents130of the master original display image110, as illustrated inFIG. 10, thereby generating the altered master original display image113.

Since processes after ST2are the same as those in Embodiment 1, description of the processes after ST2will be omitted.

FIG. 12illustrates an operation example of the slave display control terminal200according to this embodiment.

In step ST24, the layout instruction relay unit320acquires the layout information from the layout instruction unit310.

In step ST27, the delay time measurement unit209acquires the slave display image generation time and the output time of the slave original display image210from the frame progress computation unit107, acquires the output time of a synthesized image250from the synthesized image output unit206, and computes the layout execution delay time, using the slave display image generation time, the output time of the slave original display image210, and the output time of the synthesized image250.

In step ST25, the layout instruction relay unit320instructs the display image generation unit201to alter the layout of the slave original display image210with a delay corresponding to the layout execution delay time.

In step ST26, the display image generation unit201alters the positions of the contents230and the contents231of the slave original display image210, as illustrated inFIG. 10, based on the instruction from the layout instruction relay unit320, thereby generating the altered slave original display image211.

Further, the display image generation unit201notifies, to the delay time measurement unit209, the time when the slave original display image210has been output.

Since processes after ST12are the same as those in Embodiment 1, description will be omitted.

Description of Effect of Embodiment

As described above, according to this embodiment, the multi-screen synthesizing display system can be formed in which the layout of the contents on the display image to be displayed on the display apparatus20is altered according to the layout of the contents of the display image that is displayed on the display apparatus10.

In this embodiment, it is acceptable that the layout execution delay time is not used in ST25and the image synthesis unit205acquires the layout execution delay time in step S12and adjusts a buffering amount of the slave original display image210. However, in that case, a display delay time of the slave original display image210becomes longer.

In this embodiment, a description will be directed to a multi-screen synthesizing display system in which no distinction is made between a master display control terminal and a slave display control terminal.

FIG. 13illustrates a configuration example of the multi-screen synthesizing display system according to this embodiment.

A display control terminal1000and a display control terminal2000have a same internal configuration.

Each of the display control terminal1000and the display control terminal2000includes functional configurations of the master display control terminal100and the slave display control terminal200that are illustrated inFIG. 1. The display control terminal1000is connected to a display apparatus10.

The display control terminal2000is connected to a display apparatus20. Further, the display control terminal1000and the display control terminal2000are also connected.

The display control terminal1000, as in Embodiment 1, can output the master display image111illustrated inFIG. 2to the display apparatus10and can cause the synthesized image250illustrated inFIG. 2to be output from the display control terminal2000to the display apparatus20.

The display control terminal2000as well can output the master display image111illustrated inFIG. 2to the display apparatus20and can cause the synthesized image250illustrated inFIG. 2to be output from the display control terminal1000to the display apparatus10.

Each of the display control terminal1000and the display control terminal2000corresponds to a display control apparatus. The display control terminal2000corresponds to a cooperation apparatus for the display control terminal1000, and the display control terminal1000corresponds to a cooperation apparatus for the display control terminal2000.

The display apparatus10corresponds to a first display apparatus and the display apparatus20corresponds to a second display apparatus, for the display control terminal1000. The display apparatus20corresponds to a first display apparatus and the display apparatus10corresponds to a second display apparatus, for the display control terminal2000.

In the display control terminal1000, a display image generation unit101, a second output unit102, a first output unit103, and a frame progress computation unit107are the same as those illustrated inFIG. 1.

Further, an image acquisition unit104, an image synthesis unit105, and a delay time measurement unit109perform same operations as those of the image acquisition unit204, the image synthesis unit205, and the delay time measurement unit209illustrated inFIG. 1. The image acquisition unit204acquires a display image (cooperating display image) generated in the display control terminal2000that is the cooperation apparatus from the display control terminal2000. The image synthesis unit105synthesizes the cooperating display image and a display image generated by the display image generation unit101. The delay time measurement unit109measures a time from the acquisition of the cooperating display image by an image acquisition unit204to output of a synthesized image to the display apparatus10by the first output unit103.

In the display control terminal2000, a second output unit202, a first output unit203, and a frame progress computation unit207perform same operations as those of the second output unit102, the first output unit103, and the frame progress computation unit107illustrated inFIG. 1.

A display image generation unit201, an image acquisition unit204, an image synthesis unit205, and a synthesized image output unit206are the same as those illustrated inFIG. 1.

Each of the display control terminal1000and the display control terminal2000is configured with a processor, a storage device, and an input/output interface, as inFIGS. 15 and 16.

FIG. 14illustrates an operation example of the display control terminal1000.

Since each process step inFIG. 14is the same as the process step with a same number illustrated in Embodiment 1, description will be omitted.

The display control terminal2000as well performs operations inFIG. 14.

Each of the display control terminal1000and the display control terminal2000performs operations inFIG. 5illustrated in Embodiment 1, in addition to the operations inFIG. 14.

As described above, according to this embodiment, the multi-screen synthesizing display system can be formed in which the display images generated by both of the display control terminals are synthesized and displayed on the display apparatus10and the display apparatus20, with no distinction made between the master display control terminal and the slave display control terminal.

Description of Hardware Configuration

Finally, supplementary description of the hardware configuration of each of the master display control terminal100and the slave display control terminal200will be given.

Though the hardware configuration of the master display control terminal100will be described below, the following description is applied to the hardware configuration of the slave display control terminal200as well.

The processor911is a CPU (Central Processing Unit), a DSP (Digital Signal Processor), or the like.

The storage device912illustrated inFIG. 15is a RAM (Random Access Memory), a ROM (Read Only Memory), a flash memory, an HDD (Hard Disk Drive), or the like.

An OS (Operating System) is stored in the storage device912.

Then, at least part of the OS is executed by the processor911.

The processor911executes the programs to implement the functions of the display image generation unit101, the second output unit102, the first output unit103, and the frame progress computation unit107(hereinafter collectively referred to as “units”) while executing the at least part of the OS.

Though one processor is illustrated inFIG. 15, the master display control terminal100may include a plurality of the processors.

Information, data, signal values, and variable values representing results of processing performed by the “units” are stored in the storage device912, or a register or a cache memory in the processor911.

The programs to implement the functions of the “units” may be stored in a portable storage medium such as a magnetic disk, a flexible disk, an optical disk, a compact disk, a blue ray (registered trade mark) disk, or a DVD.

Each “unit” may be read as a “circuit”, a “step”, a “procedure”, or a “process”.

The master display control terminal100may be implemented by an electronic circuit such as a logic IC (Integrated Circuit), a GA (Gate Array), an ASIC (Application Specific Integrated Circuit), or an FPGA (Field-Programmable Gate Array).

In this case, each “unit” is implemented as a part of the electronic circuit.

The processor and the above-mentioned electronic circuit are also collectively referred to as processing circuitry.

While the above description has been given about the embodiments of the present invention, two or more of these embodiments may be carried out in combination.

Alternatively, one of these embodiments may be partially carried out.

Alternatively, two or more of these embodiments may be partially combined to be carried out.

The present invention is not limited to these embodiments, and various modifications are possible as necessary

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