Integrated circuit including a driver for a metal-semiconductor field-effect transistor

An integrated circuit including a metal-semiconductor field-effect transistor (MESFET) having a nominal intrinsic capacitance and requiring a negative voltage to bias the MESFET into a non-conduction state, a method of driving the MESFET and a power converter employing the integrated circuit and method. In one embodiment, the integrated circuit includes a driver including a bias capacitor integrated with the MESFET. The driver is configured to apply a positive voltage to bias the MESFET into a conduction state, and apply the negative voltage to bias the MESFET into the non-conduction state without employing an external negative bias source.

TECHNICAL FIELD OF THE INVENTION
 The present invention is directed, in general, to integrated circuits and,
 more specifically, to an integrated circuit including a driver for a
 metal-semiconductor field-effect transistor and a power converter
 employing the integrated circuit.
 BACKGROUND OF THE INVENTION
 A power converter is a power processing circuit that converts an input
 voltage waveform into a specified output voltage waveform. In many
 applications requiring a DC output, switched-mode DC-DC converters are
 frequently employed to advantage. DC-DC converters generally include an
 inverter, a transformer having a primary winding coupled to the inverter
 and a rectifier coupled to a secondary winding of the transformer. The
 inverter generally includes a switching device that converts the DC input
 voltage to an AC voltage. The transformer then transforms the AC voltage
 to another value and the rectifier generates the desired DC voltage at the
 output of the DC-DC converter.
 Conventionally, the switching device used in the inverter is a controllable
 switch such as a metal-oxide semiconductor field-effect transistor
 (MOSFET). The controllable switch in the inverter is modulated by
 periodically being driven into conduction and non-conduction states to
 maintain a required output voltage for the power converter. The rectifier
 may include passive rectifying devices that conduct the load current only
 when forward-biased in response to the input waveform to the rectifier.
 Passive rectifying devices, however, generally cannot achieve forward
 voltage drops that are low enough to provide a desired conversion
 efficiency of the DC-DC converter. To achieve a higher level of
 efficiency, DC-DC converters may therefore use synchronous rectifiers.
 A synchronous rectifier replaces the passive rectifying devices of the
 conventional rectifier with a controllable switch. This controllable
 switch is also periodically driven into conduction and non-conduction
 states in synchronism with the periodic waveform of the AC voltage. The
 rectifier switches typically exhibit resistive-conductive properties and
 may thereby avoid the higher forward voltage drops inherent in the passive
 rectifying devices.
 A metal-semiconductor field-effect transistor (MESFET) may be used as a
 controllable switch. The MESFET consists of a conducting channel
 positioned between a source and drain contact region. A carrier flowing
 from the source to the drain is controlled by a Schottky metal gate.
 Control of the channel is accomplished by varying the depletion layer
 width underneath the metal contact which modulates the thickness of the
 conducting channel and thereby the current.
 A key advantage of the MESFET is the higher mobility of the carriers in the
 channel as compared to a MOSFET. The higher mobility leads to a higher
 current, transconductance and transit frequency for the device. A higher
 transit frequency makes the MESFET of particular interest for higher
 frequency applications. The use of a Gallium-Arsenide metal-semiconductor
 field-effect transistor (GaAsMESFET) rather than a Silicon MESFET provides
 additional advantages in that the room temperature mobility is more than
 five times larger and the saturation velocity is about twice that of
 Silicon. These qualities make the GaAsMESFET particularly attractive for
 use as a switching device in high speed applications requiring low losses.
 For a better understanding of Gallium-Arsenide devices see "Optimum
 Silicon and GaAs Power Field-Effect Transistors for Advanced High-Density,
 High Frequency Power Supply Applications," by K. Shenai, C. Korman, and B.
 Baliga, HFPC 1989, and "10 MHz PWM Converters With GaAs VFETs", by R.
 Kollman, G. Collins, and D. Plumton, APEC 1996, both of which are
 incorporated herein by reference.
 Unlike the MOSFET in switching applications, however, the MESFET structure
 contains the Schottky metal gate. The Schottky metal gate limits the
 forward bias voltage on the gate to the turn-on voltage of a Schottky
 diode, which may be about 0.7 volts for Gallium-Arsenide. Therefore, the
 gate of a MESFET responds as a forward biased diode when the MESFET is
 used as a switch and in its conducting state. Additionally, the MESFET
 requires a bias voltage of an appropriate polarity to force it into a
 non-conducting state, since the MESFET conducts for a gate-to-source
 voltage of zero volts. As a result of these characteristics, it is
 difficult to use the MESFET as a controllable switch in many power
 converters since driver circuits and sources of appropriate bias supply
 voltages are often complex and more difficult to construct.
 Accordingly, what is needed in the art is a driver for a MESFET that
 resolves the deficiencies and reduces the complexity associated with the
 prior art driver circuits.
 SUMMARY OF THE INVENTION
 To address the above-discussed deficiencies of the prior art, the present
 invention provides an integrated circuit including a metal-semiconductor
 field-effect transistor (MESFET) having a nominal intrinsic capacitance
 and requiring a negative voltage to bias the MESFET into a non-conduction
 state, a method of driving the MESFET and a power converter employing the
 integrated circuit and method. In one embodiment, the integrated circuit
 includes a driver including a bias capacitor integrated with the MESFET.
 The driver is configured to apply a positive voltage to bias the MESFET
 into a conduction state, and apply the negative voltage to bias the MESFET
 into the non-conduction state without employing an external negative bias
 source.
 The present invention introduces, in one aspect, the concept of eliminating
 an external bias supply that would otherwise be required to drive the
 MESFET. Elimination of the external bias supply is highly beneficial in
 that the MESFET may be more advantageously employed in situations that
 would otherwise require complicated bias circuits. The driver including
 the bias capacitor to provide the required bias voltage on a "dynamic"
 basis resolves a long felt need in the application of MESFETs. Although
 the cited voltage polarities are directed toward an N-Channel MESFET
 device, the principles of the present invention may be applied to a
 P-Channel MESFET as well.
 In one embodiment of the present invention, the driver is coupled to a
 control terminal of the MESFET and further includes at least one diode. In
 a related, but alternative embodiment, the at least one diode is
 parallel-coupled to the bias capacitor. The quantity and placement of the
 diode(s) regulate the amount of bias voltage that the driver may supply to
 the MESFET and allow tailoring of the bias voltage to specific MESFET
 requirements.
 In one embodiment of the present invention, the MESFET is a
 Gallium-Arsenide metal-semiconductor field-effect transistor (GaAsMESFET).
 Use of the driver with a GaAsMESFET is particularly advantageous in that
 the switching speeds normally encountered in GaAsMESFET applications are
 very high. Since the driver provides a dynamic bias voltage to the
 GaAsMESFET that may otherwise deteriorate over an extended time period,
 high speed switching applications are particularly well suited for the
 application of GaAsMESFETs in accordance with the principles of the
 invention.
 In one embodiment of the present invention, the integrated circuit forms a
 portion of a power converter. In a related, but alternative embodiment,
 the power converter is selected from the group consisting of a boost power
 converter, a buck power converter and a buck-boost power converter. The
 present invention is equally applicable to isolated and non-isolated power
 converter topologies. Of course, use in or with other power converter
 topologies or other applications is well within the broad scope of the
 present invention.
 The foregoing has outlined, rather broadly, preferred and alternative
 features of the present invention so that those skilled in the art may
 better understand the detailed description of the invention that follows.
 Additional features of the invention will be described hereinafter that
 form the subject of the claims of the invention. Those skilled in the art
 should appreciate that they can readily use the disclosed conception and
 specific embodiment as a basis for designing or modifying other structures
 for carrying out the same purposes of the present invention. Those skilled
 in the art should also realize that such equivalent constructions do not
 depart from the spirit and scope of the invention in its broadest form.

DETAILED DESCRIPTION
 Referring initially to FIG. 1, illustrated is a schematic diagram of an
 embodiment of a power converter 100 constructed according to the
 principles of the present invention. The power converter 100 has an input
 couplable to a source of electrical power 105 having an input voltage Vin
 and an output that provides an output voltage Vout to a load 190. The
 power converter 100 includes an inverter with an integrated circuit (e.g.,
 a power switch integrated circuit) 115 coupled to the input. In the
 illustrated embodiment, the power switch integrated circuit 115 includes a
 power metal-semiconductor field-effect transistor (MESFET) 116 and a power
 MESFET driver 117 coupled to the input of the power converter 100.
 A transformer T1 of the power converter 100 includes a primary winding S1
 coupled to the power switch integrated circuit 115 and a secondary winding
 S2 coupled to a rectifier 130. The rectifier 130 includes first and second
 integrated circuits (e.g., first and second rectifier switch integrated
 circuits) 131, 135, which cooperate to perform together as a synchronous
 rectifier. The first rectifier switch integrated circuit 131 includes a
 first rectifier MESFET 132 and a first rectifier MESFET driver 133, and
 the second rectifier switch integrated circuit 135 includes a second
 rectifier MESFET 136 and a second rectifier MESFET driver 137.
 The rectifier 130 is coupled to the secondary winding S2 and rectifies a
 periodic waveform supplied by the secondary winding S2. The power
 converter 100 further includes an output filter 170 that is coupled
 between the rectifier 130 and the load 190. The output filter 170 has a
 filter inductor LF and a filter capacitor CF, that filters the rectified
 waveform to provide the output voltage Vout at the output of the power
 converter 100. The power converter 100 still further includes a control
 circuit 180, coupled to the power switch integrated circuit 115, that
 monitors the output voltage Vout and adjusts the switching cycles of the
 power MESFET 116 to regulate the output voltage Vout despite variations in
 the input voltage Vin or the load 190. The control circuit 180 is further
 coupled to the first and second rectifier switch integrated circuits 131,
 135 of the rectifier 130 and functions to controllably switch and rectify
 the periodic waveform supplied by the secondary winding S2. Of course, the
 control circuit 180 may monitor other control points within the power
 converter 100 as required.
 In operating the power converter 100, the control circuit 180 periodically
 switches the power MESFET 116 of the power switch integrated circuit 115
 to apply the input voltage Vin across the primary winding S1. During
 steady-state operation, the power MESFET 116 is ON (conducting) for a
 primary duty cycle D to apply the input voltage (e.g., a DC input voltage)
 Vin across the primary winding S1. The first rectifier MESFET 132 and the
 second rectifier MESFET 136 of the rectifier 130 are also periodically
 switched ON and OFF in a complementary manner to deliver an appropriate
 rectified voltage to the output filter 170.
 While the embodiment illustrated and described depicts a forward power
 converter topology, the principles of the present invention are equally
 applicable to other topologies such as a buck power converter or a
 buck-boost power converter, including but not limited to a full bridge,
 half bridge, push-pull, flyback, etc. Additionally, those skilled in the
 art will realize that the principles of the present invention may be
 employed with a wide variety of switching topologies, including those not
 specifically described herein.
 Turning now to FIG. 2, illustrated is a schematic diagram of an embodiment
 of an integrated circuit 200 constructed according to the principles of
 the present invention. The integrated circuit 200 includes a MESFET 210
 having a control terminal 220 and a driver 215 coupled between a driver
 supply voltage Vd and the control terminal 220. A gate-to-source voltage
 Vgs is illustrated at the control terminal 220 of the MESFET 210.
 The MESFET 210 is an N-channel device having a nominal gate-to-source
 intrinsic capacitance Cgs. Additionally, the MESFET 210 has an equivalent
 gate-to-source, intrinsic body diode Dgs. Both the intrinsic capacitance
 Cgs and the intrinsic body diode Dgs are drawn explicitly in FIG. 2 to
 facilitate a discussion of the operation of the integrated circuit 200.
 The driver 215 includes a bias capacitor Cbias having a bias voltage Vbias
 and first, second, third, fourth and fifth driver diodes D1, D2, D3, D4,
 D5, which are collectively designated as the driver diodes D1-D5. Both the
 bias capacitor Cbias and the driver diodes D1-D5 are preferably integrated
 with the MESFET 210. In the illustrated embodiment, the MESFET 210 is a
 Gallium Arsenide MESFET (GaAsMESFET).
 The MESFET 210, being an N-Channel device, requires a negative
 gate-to-source voltage Vgs to bias the MESFET 210 into a non-conduction
 state. Alternatively, the MESFET 210 requires a positive gate-to-source
 voltage Vgs to fully enhance the channel into a conduction state. The
 driver 215 cooperates with the intrinsic components of the MESFET 210 to
 provide both a negative bias for the non-conduction state and a positive
 bias for the conduction state. The driver 215 thereby eliminates the need
 for an external negative bias supply for the MESFET 210. Additionally, the
 driver 215 may be appropriately rearranged as to provide the same
 functionality for a MESFET having an opposite polarity (e.g., a P-Channel
 instead of an N-Channel as shown).
 When the MESFET 210 is in the conduction state, the intrinsic body diode
 Dgs limits the gate-to-source voltage Vgs to about 0.5-0.8 volts. During
 this period, the driver supply voltage Vd is in a HIGH state providing a
 positive voltage to the driver 215. A minimum condition for the difference
 in voltage between the HIGH state and the LOW state of the driver supply
 voltage Vd is partially determined by the number of diodes included in the
 driver diodes D1-D5. In the illustrated embodiment, five diodes are chosen
 to provide a value of about 3.4 volts (0.68 volts per diode times five
 diodes) for the bias voltage Vbias across the bias capacitor Cbias at the
 required forward current for the driver diodes D1-D5. Of course, other
 methods of providing the bias capacitor voltage could be used. For
 example, a reverse biased zener diode may be used in place of one or more
 of the driver diodes D1-D5. Additionally, a silicon band gap reference
 could be used, or perhaps a resistor. Alternative devices used in place of
 or in addition to driver diodes D1-D5 to generate the bias voltage Vbias
 are within the spirit and scope of the present invention. The minimum
 differential HIGH-to-LOW value of the driver supply voltage Vd may be
 computed to be the bias voltage Vbias (3.4 volts) plus the gate-to-source
 voltage Vgs (0.5 volts), which is about 3.9 volts. This value of the bias
 voltage vbias is chosen to assure that the MESFET 210 will be in the
 conducting state when the driver 215 is in the high condition, and in the
 non-conduction state when the driver supply voltage Vd traverses to its
 LOW condition.
 The value of the bias capacitor Cbias is dependent on the value of the
 intrinsic capacitance Cgs of the MESFET 210. In the illustrated
 embodiment, the intrinsic capacitance Cgs is about 5 picofarads and the
 bias capacitor Cbias is selected to be about 20 picofarads. Typically, the
 value of the bias capacitor Cbias is chosen to be several times the value
 of the intrinsic capacitance Cgs, up to perhaps ten times the value or
 more. Choosing the bias capacitor Cbias to be several times the value of
 the intrinsic capacitance Cgs allows the bias capacitor Cbias to maintain
 a substantially DC voltage throughout the switching action. The larger the
 ratio of the bias to intrinsic capacitance, the more stable the DC voltage
 on the bias capacitor Cbias. This value of bias capacitor Cbias along with
 the minimum differential HIGH-to-LOW value for the driver supply voltage
 Vd of 3.9 volts provides a negative bias value of about 3.4 volts for the
 gate-to-source voltage Vgs when the driver supply voltage Vd shifts from
 the HIGH to the LOW state. This assures that the MESFET 210 is in a
 non-conduction state, during this period.
 Turning now to FIG. 3, illustrated are voltage waveforms 300 of the
 integrated circuit 200 of FIG. 2 demonstrating the principles of the
 present invention. The voltage waveforms 300 include a first waveform 305
 and a second voltage waveform 310. The first voltage waveform 305
 corresponds to the driver supply voltage Vd and the second voltage
 waveform 310 corresponds to the gate-to-source voltage Vgs. The driver
 supply voltage Vd is seen to initially rise from a LOW state of about zero
 volts to a HIGH state of about 3.9 volts. This action causes the
 gate-to-source voltage Vgs also to rise from about --0.8 volts to about
 0.5 volts thereby placing the MESFET 210 of FIG. 2 into the conduction
 state. This state is maintained until the driver supply voltage Vd falls
 to its LOW state of about zero volts again, and the gate-to-source voltage
 Vgs again moves to a value of about --0.8 volts placing the MESFET 210
 into the non-conduction state. This sequence repeats on a periodic basis.
 Of course, the aforementioned values are submitted for illustrative
 purposes only.
 Turning now to FIG. 4, illustrated is a diagram of an embodiment of an
 integrated circuit (e.g., a power switch integrated circuit) 400
 constructed according to the principles of the present invention. The
 power switch integrated circuit 400 includes a Schottky diode 405, a
 Metal-Insulator-Metal (MIM) capacitor 410 and a power GaAsMESFET 415. In
 the illustrated embodiment, the Schottky diode 405 and the MIM capacitor
 410 are coupled to provide a driver circuit for the power GaAsMESFET 415,
 wherein only one exemplary Schottky diode is shown.
 The power switch integrated circuit 400 may be constructed according to the
 following process starting with providing a semi-insulating GaAs
 substrate. Implanted N+ contact regions are formed in the substrate to
 provide contacts for the Schottky diode 405 and the power GaAsMESFET 415.
 A channel implant region is constructed for the power GaAsMESFET 415.
 Isolation implant regions are provided to underlie all passive devices and
 surround all active devices. An ohmic metal (such as
 Germanium/Gold/Nickel) is evaporated over the N+ contact regions and the
 ohmic metal is alloyed, which melts the ohmic metal into the N+ contact
 region thereby creating a low contact resistance. A gate metal (such as
 Titanium/Platinum/Gold) is evaporated to form a gate of the power
 GaAsMESFET 415.
 A Metal 0 (such as Titanium/Platinum/Gold) is deposited and patterned by
 lift off on the ohmic contacts and the gate metal. The Metal 0 is also
 used as the bottom plate for the MIM capacitor. A MIM capacitor dielectric
 is formed and a MIM capacitor top plate metal (such as
 Titanium/Platinum/Gold) is deposited and patterned by lift-off. A second
 dielectric material is then deposited and cured. Vias are etched through
 to the MIM capacitor top metal and the Metal 0 layers. The vias are coated
 with a thin field metal (such as Titanium/Gold) to provide electrical
 contact for plating, and the vias are plated with gold (i.e., Metal 1).
 The Metal 1 provides a top side contact for the Metal 0 and the MIM
 capacitor top metal. A Metal 2 is formed to provide an interconnect from
 the Schottky diode 405 to the top plate of the MIM capacitor 410 and the
 gate of the power GaAsMESFET 415.
 Although the present invention and its advantages have been described in
 detail, those skilled in the art should understand that they can make
 various changes, substitutions and alterations herein without departing
 from the spirit and scope of the invention in its broadest form.