Semiconductor diode device

According to one embodiment, a semiconductor device includes first and second electrodes, and first, second, and third semiconductor regions. The first semiconductor region has a first conductivity type. The first electrode is provided above the first semiconductor region. The second semiconductor region has a second conductivity type and is provided between the first semiconductor region and the first electrode. The third semiconductor region is provided between the first semiconductor region and the first electrode, and has the second conductivity type. The third semiconductor region has an impurity concentration substantially equal to an impurity concentration of the second semiconductor region, and has first and second portions. The first and second portions constitute a concave-convex form on a side of the first semiconductor region of the third semiconductor region. The second electrode is provided above an opposite side of the first semiconductor region from the first electrode.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2013-188156, filed on Sep. 11, 2013; the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor device and a method for manufacturing the same.

BACKGROUND

As a semiconductor device having a rectifying function, a JBS (junction barrier Schottky) diode in which a Schottky barrier junction and a p-n junction coexist is known. The JBS diode includes a plurality of p-type semiconductor regions formed in an n-type semiconductor region and a Schottky barrier metal that is in contact with the n-type semiconductor region and the p-type semiconductor region. The JBS diode is a structure that relaxes the electric field at the interface between the n-type semiconductor region and the Schottky electrode during reverse bias and reduces leakage. For the semiconductor device, it is important to further improve the withstand capability to surge voltage etc.

DETAILED DESCRIPTION

In general, according to one embodiment, a semiconductor device includes a first semiconductor region, a first electrode, a second semiconductor region, a third semiconductor region, and a second electrode. The first semiconductor region has a first conductivity type. The first electrode is provided above the first semiconductor region. The second semiconductor region has a second conductivity type and is provided between the first semiconductor region and the first electrode. The third semiconductor region is provided between the first semiconductor region and the first electrode, and has the second conductivity type. The third semiconductor region has an impurity concentration substantially equal to an impurity concentration of the second semiconductor region, and has a first portion and a second portion with a depth shallower than the first portion. The first portion and the second portion constitute a concave-convex form on a side of the first semiconductor region of the third semiconductor region. The second electrode is provided above an opposite side of the first semiconductor region from the first electrode.

Various embodiments will be described hereinafter with reference to the accompanying drawings. In the following description, identical components are marked with the same reference numerals, and a description of components once described is omitted as appropriate. In the following description, the expressions of n+, n, and n−and p+, p, and p−indicate the relative level in the impurity concentration in the conductivity types. That is, the larger the number of “+” is, the higher the impurity concentration is; and the larger the number of “−” is, the lower the impurity concentration is. In the following description, specific examples in which the first conductivity type is the n-type and the second conductivity type is the p-type are given as examples.

First Embodiment

FIG. 1is a schematic cross-sectional view illustrating the configuration of a semiconductor device according to a first embodiment.

FIG. 2is a schematic plan view illustrating the configuration of the semiconductor device according to the first embodiment.

FIG. 1shows a schematic cross-sectional view taken along line A-A shown inFIG. 2. InFIG. 2, the configuration on the lower side of an anode electrode (a first electrode)81is shown by the broken lines.

As shown inFIG. 1, a semiconductor device110according to the embodiment includes an n−−-type semiconductor region (a first semiconductor region)11, an anode electrode (a first electrode)81, a first p-type semiconductor region (a second semiconductor region)20, a second p-type semiconductor region (a third semiconductor region)30, and a cathode electrode (a second electrode)82. The semiconductor device110includes a JBS diode and an avalanche diode. The semiconductor device110may further include at least one of an n−-type semiconductor region (a fourth semiconductor region)40, a p+-type semiconductor region (a fifth semiconductor region)50, and a p−-type semiconductor region (a sixth semiconductor region)60.

The n−−-type semiconductor region11is provided on an n+-type substrate10, for example. A silicon carbide (SiC) substrate is used as the substrate10, for example. SiC of a hexagonal crystal (for example, 4H—SiC) is included in the substrate10, for example. The substrate10is a bulk substrate of SiC fabricated by the sublimation method, for example. The substrate10is doped with an n-type impurity (for example, nitrogen (N)). The concentration of the impurity of the substrate10is approximately not less than 1×1018cm−3and not more than 5×1018cm−3, for example.

The n−−-type semiconductor region11is a region formed on a first surface10aof the substrate10by epitaxial growth, for example. The n−−-type semiconductor region11includes SiC, for example. An n-type impurity (for example, N) is included in the n−−-type semiconductor region11. The concentration of the impurity of the n−−-type semiconductor region11is approximately not less than 5×1014cm−3and not more than 5×1016cm−3, for example. The concentration of the impurity of the n−−-type semiconductor region11is lower than the concentration of the impurity of the substrate10. In the embodiment, the concentration of the impurity of the n−−-type semiconductor region11is approximately not less than 1×1015cm−3and not more than 2×1016cm−3.

The thickness of the n−−-type semiconductor region11is determined by the design of the breakdown voltage characteristics and other characteristics of the semiconductor device110. For example, when the breakdown voltage is 600 volts (V), the thickness of the n−−-type semiconductor region11is approximately not less than 3.5 micrometers (μm) and not more than 7 μm.

The anode electrode81is joined to the n−−-type semiconductor region11by Schottky junction. The anode electrode81is provided on the opposite side of the n−−-type semiconductor region11from the substrate10. In the embodiment, the direction connecting the n−−-type semiconductor region11and the anode electrode81is defined as the Z-direction, one direction orthogonal to the Z-direction is defined as the X-direction, and the direction orthogonal to the Z-direction and the X-direction is defined as the Y-direction. The direction from the n−−-type semiconductor region11toward the anode electrode81along the Z-direction is referred to as upward (the upward direction), and the opposite direction is referred to as downward (the downward direction).

The anode electrode81is provided on the n−−-type semiconductor region11. A Schottky barrier diode (SBD) is formed by the Schottky junction of the anode electrode81and the n−−-type semiconductor region11. Titanium (Ti) is used for the anode electrode81, for example.

The first p-type semiconductor region20is provided between the n−−-type semiconductor region11and the anode electrode81. The first p-type semiconductor region20is in contact with the anode electrode81. The first p-type semiconductor region20includes SiC, for example.

A p-type impurity (for example, aluminum (Al) or boron (B)) is included in the first p-type semiconductor region20. The concentration of the impurity of the first p-type semiconductor region20is approximately not less than 5×1017cm−3and not more than 1×1019cm−3, for example. In the embodiment, the concentration of the impurity of the first p-type semiconductor region20is approximately 1×1018cm−3. The thickness (the thickness in the Z-direction) of the first p-type semiconductor region20is approximately not less than 0.3 μm and not more than 1.2 μm, for example. A p-n junction is formed at the boundary between the first p-type semiconductor region20and the n−−-type semiconductor region11.

As shown inFIG. 2, the first p-type semiconductor region20is provided to extend in one direction, for example. In the embodiment, the first p-type semiconductor region20extends in the Y-direction. The first p-type semiconductor region20may be provided in plural. The plurality of first p-type semiconductor regions20may be provided parallel at prescribed intervals. Each of the plurality of first p-type semiconductor regions20may be provided in an island shape.

The second p-type semiconductor region30is provided between the n−−-type semiconductor region11and the anode electrode81. The second p-type semiconductor region30is joined to the anode electrode81by ohmic junction. The second p-type semiconductor region30includes SiC, for example.

A p-type impurity (for example, Al or B) is included in the second p-type semiconductor region30. The concentration of the impurity of the second p-type semiconductor region30is approximately not less than 5×1017cm−3and not more than 1×1019cm−3, for example. The concentration of the impurity of the second p-type semiconductor region30may be substantially the same as the concentration of the impurity of the first p-type semiconductor region20. In the embodiment, “substantially the same” refers to the case of being the same and the case of including errors in the manufacturing.

The second p-type semiconductor region30has a first portion301and a second portion302. The first portion301has a depth of D1 (a first depth). The depth D1 is the length in the Z-direction from the boundary between the n−−-type semiconductor region11and the anode electrode81toward the n−−-type semiconductor region11side.

The second portion302is adjacent to the first portion301. The second portion302has a depth of D2 (a second depth). The depth D2 is the length in the Z-direction from the boundary between the n−−-type semiconductor region11and the anode electrode81toward the n−−-type semiconductor region11side. The depth D2 is shallower than the depth D1.

The first portion301and the second portion302provide a convex form and a concave form on the interface on the n−−-type semiconductor region11side of the second p-type semiconductor region30. In the semiconductor device110, a plurality of first portions301and a plurality of second portions302are provided. Each first portion301and each second portion302are alternately provided in a direction orthogonal to the Z-direction. Thereby, a plurality of convex forms and a plurality of concave forms are provided on the interface on the n−−-type semiconductor region11side of the second p-type semiconductor region30.

Although the plurality of first portions301and the plurality of second portions302are alternately arranged in the X-direction in the example shown inFIG. 1, they may be alternately arranged in the Y-direction. A plurality of first portions301and a plurality of second portions302may be alternately arranged in each of the X-direction and the Y-direction.

The first depth D1 is approximately not less than 0.3 μm and not more than 1.2 μm, for example. The second depth D2 is approximately not less than 10% and not more than 90% of the first depth D1, for example. The second depth D2 is approximately not less than 50 nanometers (nm) and not more than 1000 nm, for example. The first depth D1 may be substantially the same as the depth of the first p-type semiconductor region20.

The second p-type semiconductor region30, the n−−-type semiconductor region11, and the substrate10constitute an avalanche diode. As shown inFIG. 2, the second p-type semiconductor region30may be provided so as to surround the periphery of the plurality of first p-type semiconductor regions20as viewed in the Z-direction. The second p-type semiconductor region30may be provided next to the plurality of first p-type semiconductor regions20as viewed in the Z-direction.

The n−-type semiconductor region40is provided between the n−−-type semiconductor region11and the second p-type semiconductor region30. The n−-type semiconductor region40is in contact with the second p-type semiconductor region30. That is, the n−-type semiconductor region40is in contact with the interface having a convex form and a concave form provided on the n−−-type semiconductor region11side of the second p-type semiconductor region30. The n−-type semiconductor region40includes SiC, for example.

An n-type impurity (for example, N) is included in the n−-type semiconductor region40. The concentration of the impurity of the n−-type semiconductor region40is approximately not less than 1×1017cm−3and not more than 1×1018cm−3, for example. The concentration of the impurity of the n−-type semiconductor region40is higher than the concentration of the impurity of the n−−-type semiconductor region11. In the embodiment, the concentration of the impurity of the n−-type semiconductor region40is approximately 2×1017cm−3.

The p+-type semiconductor region50is provided between the second p-type semiconductor region30and the anode electrode81. The p+-type semiconductor region50is provided between the first portion301of the second p-type semiconductor region30and the anode electrode81, for example. The p+-type semiconductor region50is in contact with the anode electrode81. The p+-type semiconductor region50includes SiC, for example.

A p-type impurity (for example, Al or B) is included in the p+-type semiconductor region50. The concentration of the impurity of the p+-type semiconductor region50is approximately not less than 2×1019cm−3and not more than 5×1020cm−3, for example. The concentration of the impurity of the p+-type semiconductor region50is higher than the concentration of the impurity of the second p-type semiconductor region30. The p+-type semiconductor region50is provided in order to join the second p-type semiconductor region30and the anode electrode81by ohmic junction surely. In the embodiment, the concentration of the impurity of the p+-type semiconductor region50is approximately 1×1020cm−3.

In the case where a plurality of first portions301are provided, the p+-type semiconductor region50may be provided between each of the plurality of first portions301and the anode electrode81. The p+-type semiconductor region50is preferably provided on the inside (in the interior) of the second p-type semiconductor region30. That is, the p+-type semiconductor region50is preferably surrounded by the second p-type semiconductor region30; in other words, the p+-type semiconductor region50is preferably not in contact with the n−−-type semiconductor region11. Thereby, a leakage current is suppressed.

An ohmic electrode (a third electrode)81afor making ohmic junction surely may be provided between the p+-type semiconductor region50and the anode electrode81. The resistivity of the ohmic electrode81ais lower than the resistivity of the anode electrode81. Nickel (Ni) or nickel silicide is used for the ohmic electrode81a, for example.

The cathode electrode82is provided on the opposite side of the n−−-type semiconductor region11from the anode electrode81. In the embodiment, the cathode electrode82is in contact with a second surface10bof the substrate10. The second surface10bis the surface on the opposite side to the first surface10aof the substrate10. The cathode electrode82is joined to the substrate10by ohmic junction. Ni is used for the cathode electrode82, for example.

The p−-type semiconductor region60is provided adjacent to the second p-type semiconductor region30. The p−-type semiconductor region60may be provided so as to surround an end30eof the second p-type semiconductor region30. The p−-type semiconductor region60includes a p-type impurity (for example, Al or B). The concentration of the impurity of the p−-type semiconductor region60is approximately not less than 1×1017cm−3and not more than 1×1018cm−3, for example. The concentration of the impurity of the p−-type semiconductor region60is lower than the concentration of the impurity of the second p-type semiconductor region30. The p−-type semiconductor region60is a terminal region of the semiconductor device110. In the embodiment, the concentration of the impurity of the p−-type semiconductor region60is approximately 5×1017cm−3.

In the semiconductor device110, as viewed in the Z-direction, the end30eof the second p-type semiconductor region30is provided between the outer periphery edge81eof the anode electrode81and the p−-type semiconductor region60. That is, the second p-type semiconductor region30is provided from the inside to the outside of the anode electrode81as viewed in the Z-direction.

The semiconductor device110like this includes a JBS diode composed of the anode electrode81, the cathode electrode82, the n−−-type semiconductor region11, and the first p-type semiconductor region20and an avalanche diode composed of the anode electrode81, the cathode electrode82, the n−−-type semiconductor region11, and the second p-type semiconductor region30. The avalanche diode is connected in parallel to the JBS diode.

Next, operations of the semiconductor device110are described.

When a (forward) voltage is applied so that the anode electrode81is positive with respect to the cathode electrode82of the semiconductor device110, electrons that have surmounted the Schottky barrier from the anode electrode81flow through the n−−-type semiconductor region11and the substrate10to the cathode electrode82. When the voltage exceeds a prescribed voltage (for example, 3 V), electrons and holes that have surmounted the built-in potential flow via the p-n junction surface existing at the interface between the second p-type semiconductor region30and the n−−-type semiconductor region11.

On the other hand, a (reverse) voltage is applied so that the anode electrode81is negative with respect to the cathode electrode82, electrons can hardly surmount the Schottky barrier between the anode electrode81and the n−−-type semiconductor region11, and the flow of electrons is suppressed. A depletion layer extends mainly to the n−−-type semiconductor region11side of the p-n junction surface, and little current flows through the semiconductor device110. When a reverse voltage is applied, the electric field at the interface between the anode electrode81and the n−−-type semiconductor region11is relaxed by the first p-type semiconductor region20. Thereby, the breakdown voltage is improved.

In the semiconductor device110, both a low ON voltage obtained by the SBD and a low ON resistance obtained by the P—N diode can be achieved.

Here, when a surge voltage whereby the anode electrode81becomes negative is applied to the semiconductor device110, the electric field is likely to be concentrated at the end30eof the second p-type semiconductor region30. In the semiconductor device110, a convex form and a concave form are formed on the interface on the n−−-type semiconductor region11side of the second p-type semiconductor region30by means of the depth difference between the first portion301and the second portion302of the second p-type semiconductor region30.

Due to the effect of the configuration of the second p-type semiconductor region30, the breakdown voltage in the p-n junction portion (the boundary portion between the second p-type semiconductor region30and the n−−-type semiconductor region11) is lowered as compared to the case where no concave-convex form is provided. Consequently, when a surge voltage is applied, breakdown is more likely to occur at the interface on the n−−-type semiconductor region11side of the second p-type semiconductor region30. In the semiconductor device110, the concentration of breakdown in the terminal region is suppressed, and element breaking in the terminal region is prevented.

The breakdown voltage in the second p-type semiconductor region30is preferably set lower than the breakdown voltage in the terminal region. Thereby, breakdown occurs earlier in the portion of the second p-type semiconductor region30than in the terminal region. Consequently, in the semiconductor device110, element breaking in the terminal region due to breakdown is prevented.

In the semiconductor device110, a leakage current is suppressed in the second p-type semiconductor region30by the second portion302provided shallower than the first portion301. By providing the second portion302, the electric field applied to the Schottky interface can be relaxed, and high voltage leakage is suppressed. Here, the Schottky portion relaxes the electric field using the JBS structure. Hence, if the second portion302is not provided, the dimensions of the second p-type semiconductor region30cannot deviate from the JBS dimensions. Since N is implanted into the second p-type semiconductor region30, the electric field applied to the Schottky interface is increased. By providing the second portion302, the period of the concave-convex of the second p-type semiconductor region30can be set independently of the JBS dimensions, and the concentration of implanted N of the second p-type semiconductor region30can be set to an optimum value independently of the trade-off with Schottky leakage.

FIG. 3is a diagram illustrating an electric field intensity distribution.

The horizontal axis ofFIG. 3represents the position in the X-direction, and the vertical axis represents the position in the Z-direction.FIG. 3shows the electric field intensity distribution in the first portion301of the second p-type semiconductor region30. The electric field intensity distribution is shown by electric field contour lines of electric field intensities E1 to E7. The value of the electric field intensity decreases in the order of from the electric field intensity E1 to the electric field intensity E7.

As shown inFIG. 3, it can be seen that the electric field intensity is high particularly in the corner portion of the first portion301. Thus, by providing the first portion301and the second portion302as the second p-type semiconductor region30, electric field concentration due to the effect of the configuration of the second p-type semiconductor region30is brought about, and the breakdown voltage is lowered. By providing a plurality of first portions301and a plurality of second portions302, the effect of electric field concentration due to the concave-convex form is enhanced.

Thus, in the semiconductor device110, by providing the second p-type semiconductor region30having the first portion301and the second portion302, it is made easier to cause breakdown in the second p-type semiconductor region30, and breakdown concentrated in the terminal region is suppressed. Consequently, element breaking in the terminal region is prevented. That is, in the semiconductor device110, the withstand capability to surge voltage etc. is improved.

Next, a method for manufacturing the semiconductor device110is described.

FIG. 4AtoFIG. 6Bare schematic cross-sectional views illustrating a method for manufacturing a semiconductor device.

First, as shown inFIG. 4A, the n−−-type semiconductor region11is formed on the first surface10aof the substrate10. A bulk substrate of SiC is used as the substrate10, for example. The substrate10is doped with an n-type impurity (for example, nitrogen (N)). The concentration of the impurity of the substrate10is approximately not less than 1×1018cm−3and not more than 5×1018cm−3, for example.

The n−−-type semiconductor region11is formed on the first surface10aof the substrate10by epitaxial growth. The n−−-type semiconductor region11includes SiC, for example. An n-type impurity (for example, N) is included in the n−−-type semiconductor region11. The concentration of the impurity of the n−−-type semiconductor region11is approximately not less than 5×1014cm−3and not more than 5×1016cm−3, for example. The concentration of the impurity of the n−−-type semiconductor region11is lower than the concentration of the impurity of the substrate10.

Next, as shown inFIG. 4B, a mask M1 is formed on the n−−-type semiconductor region11, and an opening h1 is provided. The position of the opening h1 is on the upper side of the position where the p−-type semiconductor region60will be formed. Then, ions of a p-type impurity such as Al are implanted via the opening h1 of the mask M1.

Thereby, an ion implantation region60P containing the p-type impurity is formed in the n−−-type semiconductor region11under the opening h1. After that, the mask M1 is removed.

Next, as shown inFIG. 4C, a mask M2 is formed on the n−−-type semiconductor region11, and openings h21 and h22 are provided. The position of the opening h21 is on the upper side of the position where the first p-type semiconductor region20will be formed. The position of the opening h22 is on the upper side of the position where the first portion301of the second p-type semiconductor region30will be formed.

The shape, size, and pitch of the first p-type semiconductor region20of a JBS diode are determined by the shape, size, and pitch of the opening h21. The shape, size, and pitch of the first portion301of the second p-type semiconductor region30of an avalanche diode are determined by the shape, size, and pitch of the opening h22.

Then, p-type impurity ions of Al or the like are implanted via the openings h21 and h22 of the mask M2. Thereby, an ion implantation region20P containing the p-type impurity is formed in the n−−-type semiconductor region11under the opening h21. Furthermore, an ion implantation region301P containing the p-type impurity is formed in the n−−-type semiconductor region11under the opening h22. After that, the mask M2 is removed.

Next, as shown inFIG. 5A, a mask M3 is formed on the n−−-type semiconductor region11, and openings h3 are provided. The position of the opening h3 is on the upper side of the ion implantation region301P. Then, ions of a p-type impurity such as Al are implanted via the opening h3 of the mask M3. Thereby, an ion implantation region50P containing the p-type impurity is formed on the surface side of the ion implantation region301P under the opening h3. After that, the mask M3 is removed.

Next, as shown inFIG. 5B, a mask M4 is formed on the n−−-type semiconductor region11, and an opening h4 is provided. The range of the opening h4 is a range on the inside of the second p-type semiconductor region30as viewed in the Z-direction. Then, ions of an n-type impurity such as N are implanted via the opening h4 of the mask M4. Thereby, an ion implantation region40N containing the n-type impurity is formed in the n−−-type semiconductor region11and on the lower side of the ion implantation region301P under the opening h4.

Next, as shown inFIG. 5C, the mask M4 used in the previous ion implantation is used to implant p-type impurity ions of Al or the like. Thereby, an ion implantation region302P containing the p-type impurity is formed under the opening h4. At this time, the ion implantation region302P is formed in a position shallower than the depth of the ion implantation region301P in accordance with the conditions of the ion implantation. After that, the mask M4 is removed.

Next, thermal diffusion is performed. Thereby, the ions of the ion implantation regions20P,301P,302P,40P,50P, and60P are activated to form the first p-type semiconductor region20, the second p-type semiconductor region30(the first portion301and the second portion302), the n−-type semiconductor region40, the p+-type semiconductor region50, and the p−-type semiconductor region60, as shown inFIG. 6A. On the n−−-type semiconductor region11side of the second p-type semiconductor region30, the first portion301and the second portion302constitute a concave-convex form.

Next, as shown inFIG. 6B, the anode electrode81and the cathode electrode82are formed. The anode electrode81is formed on the n−−-type semiconductor region11, the first p-type semiconductor region20, the second p-type semiconductor region30, and the p+-type semiconductor region50. It is also possible to form the ohmic electrode81aon the p+-type semiconductor region50and then form the anode electrode81. Ni is used for the anode electrode81, for example.

The cathode electrode82is formed in contact with the second surface10bof the substrate10. Ni is used for the cathode electrode82, for example. Thereby, the semiconductor device110is completed.

In the method for manufacturing the semiconductor device110like this, the mask M2 shown inFIG. 4Cis used to form the ion implantation region20P of the first p-type semiconductor region20and the ion implantation region301P of the first portion301of the second p-type semiconductor region30. Furthermore, the mask M4 shown inFIG. 5Bis used to form the ion implantation region40P of the n−-type semiconductor region40and the ion implantation region302P of the second portion302of the second p-type semiconductor region30. That is, since a plurality of ion implantation regions are formed using one mask, the photolithography process for forming masks can be simplified.

Second Embodiment

Next, a second embodiment is described.

FIG. 7is a schematic cross-sectional view illustrating the configuration of a semiconductor device according to the second embodiment.

FIG. 7shows a semiconductor device120according to the second embodiment.

In the semiconductor device120shown inFIG. 7, the size of the p+-type semiconductor region50is larger than the size of the p+-type semiconductor region50of the semiconductor device110according to the first embodiment. In the semiconductor device120, the first portion301has a depth of D11, and the second portion302has a depth of D21. The depth D11 is deeper than the depth D1 of the first portion301of the semiconductor device110, and the depth D21 is deeper than the depth D2 of the second portion302of the semiconductor device110. Otherwise, the configuration is similar to the semiconductor device110according to the first embodiment.

The depth D21 is shallower than the depth D11. The p+-type semiconductor region50is provided between the first portion301and the second portion302, and the anode electrode81. The p+-type semiconductor region50is provided to extend over the first portion301and the second portion302on the inside of the second p-type semiconductor region30. The depth of the p+-type semiconductor region50is shallower than the depth D21 of the second portion302.

In the semiconductor device120like this, similarly to the semiconductor device110, breakdown concentrated in the terminal region is suppressed by providing the second p-type semiconductor region30having the first portion301and the second portion302. Furthermore, a good ohmic contact between the anode electrode81and the second p-type semiconductor region30is obtained by means of the p+-type semiconductor region50with a large area.

In the semiconductor device120according to the second embodiment, the withstand capability to surge voltage etc. is improved.

Next, layouts of the semiconductor devices110and120are described.

In the example shown inFIG. 2, the second p-type semiconductor region30is provided so as to surround the periphery of the plurality of first p-type semiconductor regions20as viewed in the Z-direction. That is, in the example shown inFIG. 2, the region of the avalanche diode is provided so as to surround the periphery of the JBS diode. The layout of the semiconductor device may be other than this.

FIG. 8AandFIG. 8Bare schematic plan views illustrating layouts of the semiconductor device.

FIG. 8AandFIG. 8Bshow examples of the layout as viewed in the Z-direction of the JBS diode and the avalanche diode. For convenience of description, inFIG. 8AandFIG. 8B, the region of the JBS diode in the rectangle substrate10is schematically shown as S1, and the region of the avalanche diode is schematically shown as S2. The regions S1 and S2 may be collectively referred to as a region S. The region S1 of the JBS diode includes the first p-type semiconductor region20expressed by the broken line in the drawings. The region S2 of the avalanche diode includes the first portion301and the second portion302of the second p-type semiconductor region30expressed by the broken line in the drawings.

In the example shown inFIG. 8A, a plurality of regions S are arranged in one direction. In the example shown inFIG. 8A, four regions S are aligned in the X-direction. The four regions S include two regions S1 of the JBS diode and two regions S2 of the avalanche diode. The two regions S1 of the JBS diode and the two regions S2 of the avalanche diode are alternately arranged in the X-direction. The number of regions S is not limited to four. Also the direction in which the regions are alternately arranged is not limited to the X-direction.

In the example shown inFIG. 8B, a plurality of regions S are arranged in each of the X-direction and the Y-direction. In the example shown inFIG. 8B, eight regions S are arranged. Of the eight regions S, four regions S are aligned in the X-direction, and two regions S are aligned in the Y-direction. The four regions S aligned in the X-direction include two regions S1 of the JBS diode and two regions S2 of the avalanche diode. The two regions S1 of the JBS diode and the two regions S2 of the avalanche diode are alternately arranged in the X-direction. The two regions S aligned in the Y-direction include one region S1 of the JBS diode and one region S2 of the avalanche diode.

The layouts of regions S shown inFIG. 8AandFIG. 8Bare only examples, and layouts other than these are possible.

As described above, the semiconductor device according to the embodiment can improve the withstand capability to surge voltage etc.

Hereinabove, embodiments and variations thereof are described. However, the invention is not limited to these examples. For example, one skilled in the art may appropriately make additions, removals, and design modifications of components to the embodiments or the variations described above, and may appropriately combine features of the embodiments; such modifications also are included in the scope of the invention to the extent that the spirit of the invention is included.

For example, although the above embodiments and variations are described using the n-type as the first conductivity type and the p-type as the second conductivity type, the invention can be practiced also by using the p-type as the first conductivity type and the n-type as the second conductivity type. Furthermore, although the case where each semiconductor region includes SiC is used as an example, semiconductors other than SiC (for example, Si and GaN) may be used.

Furthermore, in the embodiments and the variations described above, various structures such as a RESURF structure, a guard ring structure, and a field plate structure may be used as the terminal structure, which is the p−-type semiconductor region60.

Moreover, although examples in which the structure of the second p-type semiconductor region30is applied to a JBS diode are described in the above embodiments and variations, the invention is not limited thereto. The structure of the second p-type semiconductor region30may be applied to elements such as MOSFETs (metal oxide semiconductor field effect transistors) and IGBTs (insulated gate bipolar transistors).