Current limit circuit apparatus

The present invention provides a current limit circuit apparatus, coupled with the gate of a GaN transistor. The current limit circuit comprises a diode, a first transistor, a second transistor, a first resistor, a second resistor, a third resistor and a fourth resistor. The source and the drain of the first transistor couple with the diode. The source of the second transistor couples with the gate of the first transistor. The source of the first transistor couples with the first transistor. The source of the second transistor couples with the second resistor. The third resistor couples with the fourth resistor and the gate of the first transistor. The first transistor turned off and the gate current is limited. When the current of the gate of the GaN transistor exceeds the predetermined value, the breakdown voltage is increased by limiting the gate current.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a current limit circuit apparatus, more particularly to a current limit circuit apparatus for limiting the gate current of the GaN transistor, in order to increase the breakdown voltage of the GaN transistor by limiting the gate current of the GaN transistor.

2. Description of the Prior Art

The GaN is a wide band gap semiconductor with quick switching capability. It is a high-frequency operated electronic device for bringing great change to the communication technology. Except this, it has high breakdown voltage, and it is also one of the best materials for manufacturing of the high-power transistor and will bring the revolutionary change to the high-power device.

The conventional way for increasing the breakdown voltage of GaN transistor is to use different process or change the material of device, the technical level is higher and the cost is also higher. How to increase the breakdown voltage of GaN transistor without changing the process and material has become one of the topics endeavored by the industry.

Please referring toFIG. 1, which shows the relation between the leaking current at the output/input end of AlGaN/GaN transistor and the voltage of drain-source. As shown inFIG. 1, when the AlGaN/GaN transistor is operated at the cut-off region, the leaking current is increased with the voltage difference (Vds) of the drain and the source. When the breakdown voltage is achieved, almost all leaking current of the drain flows to the gate. Upon using the abovementioned feature, when the AlGaN/GaN transistor is turned off and the current flown from the drain to the gate is limited, the breakdown voltage of GaN transistor will be increased.

Therefore, a current limit circuit apparatus coupled with the gate of a GaN transistor is required to limit the current flown out of the gate, in order to increase the breakdown voltage of GaN transistor.

SUMMARY OF THE INVENTION

In order to increase the breakdown voltage of GaN transistor without changing the process condition and device material, the present invention provides a current limit circuit apparatus for limiting the gate current of the GaN transistor, so as to increase its breakdown voltage.

In order to achieve the abovementioned purpose, the present invention provides a current limit circuit apparatus suitable for the GaN transistor. The process parameters need not to be changed, and the finished GaN transistor can be used directly. The circuit design is used to limit the gate current of the GaN transistor for increasing its breakdown voltage. The designer can have the flexible design, and reduce the manufacturing cost.

Based on the abovementioned purpose, the present invention provides a current limit circuit apparatus, coupled with the gate of a GaN transistor. The current limit circuit comprises a diode, a first transistor, a second transistor, a first resistor, a second resistor, a third resistor and a fourth resistor. The source and the drain of the first transistor couple with the diode. The drain of the second transistor couples with the gate of the first transistor. The first resistor couples with the diode and the source of the first transistor. One end of the second resistor couples with the source of the second transistor and a first power supply. One end of the third resistor couples with the fourth resistor and the gate of the first transistor. The other end of the third resistor couples with the gate of the second transistor and the other end of the second resistor. The drain of the first transistor couples with one end of the diode and the gate of the GaN transistor. The first transistor turned off and the gate current is limited. When the current of the gate of the GaN transistor exceeds the predetermined value, the breakdown voltage is increased by limiting the gate current.

Another purpose of the present invention is to provide a current limit circuit apparatus. The current limit circuit further comprises a fifth resistor, a sixth resistor, a third transistor and a fourth transistor. The fifth resistor couples with the third resistor and the gate of the first transistor. The drain of the third transistor couples with the fifth resistor. The source of the third transistor couples with a second power supply. The source of the fourth transistor couples with a second power supply. The drain of the fourth transistor couples with the sixth resistor.

The gate of the fourth transistor couples with the drain of the first transistor and the gate of the GaN transistor. After the GaN transistor is turned of through the switch of the third transistor and the fourth transistor, the first transistor is turned off to limit the leaking current flown out from the gate of the GaN transistor, so as to increase the breakdown voltage of the GaN transistor.

In order to further understand the abovementioned and other purposes, features and advantages of the present invention, the preferred embodiments and Figures are attached and described in detail as follows.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The present invention can be further understood through the following Figures and detailed description. The following embodiments are used for the detailed description, but the scope of the present invention is not limited by the following embodiments.

FIG. 2is a diagram illustrating the GaN circuit apparatus for an embodiment of the present invention. As shown inFIG. 2, the GaN circuit apparatus200comprises a transistor drive circuit202, a current limit circuit204and a GaN transistor MGaN. The current limit circuit204couples with the transistor drive circuit202and the GaN transistor MGaN, and the current limit circuit204couples with the gate of the GaN transistor MGaN. The transistor drive circuit202includes a P-type metal-oxide-semiconductor (PMOS) field transistor2022and an N-type metal-oxide-semiconductor (NMOS) field transistor2024. The P-type metal-oxide-semiconductor (PMOS) field transistor2022connects to a high voltage source VDDH. The N-type metal-oxide-semiconductor (NMOS) field transistor2024connects to a low voltage source VDDL(this low voltage source VDDLuses the same low voltage source as the transistor drive circuit202). In this embodiment, the high voltage source is VDDH=0V, and the low voltage source is VDDL=−7V. The transistor drive circuit202control to switch the P-type metal-oxide-semiconductor (PMOS) field transistor2022and the N-type metal-oxide-semiconductor (NMOS) field transistor2024in accordance with the input voltage Vs. In the Figure, the source and the drain of the first transistor M1couple with the diode D. The source of the second transistor M2couples with the gate of the first transistor M1.

FIG. 3is a diagram illustrating the current limit circuit apparatus for a preferred embodiment of the present invention. As shown in the Figure, the first resistor Ro couples with the diode D and the source of the first transistor M1. One end of the second resistor R2couples with the source of the second transistor M2and the first power supply VDDL. One end of the third resistor R3couples with the fourth resistor R4and the gate of the first transistor M1. The other end of the third resistor R3couples with the gate of the second transistor M2, and the other end of the second resistor R2. The drain of the first transistor M1couples with the other end of the diode D and the gate of the GaN transistor MGaN.

Please referring toFIG. 2andFIG. 3, when Vs=VDDLis inputted, the P-type metal-oxide-semiconductor (PMOS) field transistor2022will be conducted. The current will flow from the high voltage source VDDHto the GaN transistor MGaNthrough the diode for turning on the GaN transistor MGaN. When Vs=VDDHis inputted, the N-type metal-oxide-semiconductor (NMOS) field transistor will be conducted. The current will flow from the gate of the GaN transistor MGaNto the low voltage source VDDL. At this time, the voltage of the node N1is V1=VDDL+ΔV, where ΔV represents the voltage drop of the first resistor RG.

The voltage of the node N2is:

VREF=Vth⁡(R2+R3R2)+VDDL
where Vthrepresents the critical voltage of the first transistor M1and the second transistor M2, R2is the second resistor, and R3is the third resistor. The conducting condition of the first transistor can be represented as:
VREF−V1>Vth
where VREFis the voltage of the node N2. The above equation is substituted into this equation to get:

It is known that ΔV represents the voltage drop of the first resistor RG, therefore:
ΔV=iGRG

This equation is substituted into ΔV to obtain:

It means when the gate current flown from the gate of the GaN transistor MGaNis:

iG<Vth⁢R3R2⁢RG
(predetermined value), the first transistor M1will be turned on. On the contrary, when the gate current iGis too large (higher than the above predetermined value), the first transistor M1will be turned off and the gate current iGwill be limited, in order to increase the breakdown voltage of the GaN transistor MGaN. The first transistor M1and the second transistor M2are the N-type metal-oxide-semiconductor (NMOS) field transistors.

As for another embodiment, please referring toFIG. 2andFIG. 4.FIG. 4is a diagram illustrating the current limit circuit apparatus for another preferred embodiment of the present invention. The difference between this embodiment and the above embodiment is that the third transistor M3and the fourth transistor M4are added to modify the activating time of the current limit circuit. Because, when the GaN transistor MGaNis turned off quickly, the simultaneous current of the gate will be very large. If the current is limited at this time, the turn-off speed of the GaN transistor MGaNwill be reduced, even the current limit circuit shown inFIG. 4started to limit the current only after the GaN transistor MGaNis turned off. The fifth resistor R5couples with the third resistor R3and the gate of the first transistor M1. The drain of the third transistor M3couples with another end of the fifth resistor R5. The source of the third transistor M3couples with the second power supply VthG(i.e. the critical voltage of the GaN transistor MGaN).

As shown inFIG. 4, when the GaN transistor MGaNis turn on and off, the gate voltage is about 0V. At this time, the third transistor M3is conducted, the fourth transistor M4is not conducted, and the voltage V3of the node N3is almost equivalent to the critical voltage VthGof the GaN transistor MGaN. In this embodiment, the critical voltage VthG=−4V. Then the first transistor M1is conducted, the current flows from the gate of the GaN transistor MGaNsmoothly until the gate voltage reaches about the critical voltage VthG, in order to assure the GaN transistor MGaNis turned off. Then, the gate voltage of the GaN transistor MGaNis reduced continuously, so that the third transistor M3is not conducted, the fourth transistor M4is conducted, and the voltage V3of the node N3is equivalent to the voltage VREFof the node N2specified in the above embodiment shown inFIG. 3. This embodiment assures the turn-off of the GaN transistor MGaN, in order to modify the turn-on and turn-off time of the GaN transistor MGaN. Because, its simultaneous current closes to the breakdown current of the gate, the turn-off speed of the GaN transistor MGaNwill be reduced. The third transistor M3and the fourth transistor M4are the P-type metal-oxide-semiconductor (PMOS) field transistors.

A circuit design method is provided by the present invention for the above two embodiments. Under the normal switch of the GaN transistor is unaffected, a current limit circuit is coupled with the transistor drive circuit and the GaN transistor to limit the gate current of the GaN transistor, in order to increase the breakdown voltage (i.e. the drain-source voltage) at the turn-off of the GaN transistor. The prior art can be improved by process design, process parameters or device design, in order to solve the drawbacks of inflexible design and high cost.

It is understood that various other modifications will be apparent to and can be readily made by those skilled in the art without departing from the scope and spirit of this invention. Accordingly, it is not intended that the scope of the claims appended hereto be limited to the description as set forth herein, but rather that the claims be construed as encompassing all the features of patentable novelty that reside in the present invention, including all features that would be treated as equivalents thereof by those skilled in the art to which this invention pertains.