DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME

A display apparatus includes: a substrate; a pixel electrode over the substrate; a bank layer over the pixel electrode, and including a pixel opening exposing at least a portion of the pixel electrode; and a blocking layer to block ultraviolet rays, at least a portion of the blocking layer being located over the bank layer and spaced from the pixel electrode.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to and the benefit of Korean Patent Application No. 10-2022-0122875, filed on Sep. 27, 2022, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated by reference herein.

BACKGROUND

Aspects of one or more embodiments of the present disclosure relate to a display apparatus, and a method of manufacturing the display apparatus.

2. Description of the Related Art

Electronic apparatuses based on mobility have been widely used. Recently, in addition to small electronic apparatuses, such as mobile phones, tablet personal computers (PCs) have been widely used as mobile electronic apparatuses.

Such mobile electronic apparatuses include a display apparatus to provide visual information, such as images or videos, to a user in order to support various functions. Recently, as other components for driving a display apparatus have been miniaturized, a proportion of the display apparatus in an electronic apparatus has gradually increased, and a structure capable of being bent from a flat state to have a certain angle has been developed.

SUMMARY

One or more embodiments of the present disclosure are directed to a display apparatus in which ultraviolet rays transmitted through a bank layer and a spacer may be blocked to reduce an outgassing phenomenon in which gas may occur due to the bank layer and the spacer reacting with the ultraviolet rays.

However, the present disclosure is not limited to the above aspects and features.

Additional aspects and features will be set forth, in part, in the description that follows, and in part, will be apparent from the description, or may be learned by practicing one or more of the presented embodiments of the present disclosure.

According to one or more embodiments of the present disclosure, a display apparatus includes: a substrate; a pixel electrode over the substrate; a bank layer over the pixel electrode, and including a pixel opening exposing at least a portion of the pixel electrode; and a blocking layer configured to block ultraviolet rays, at least a portion of the blocking layer being located over the bank layer and spaced from the pixel electrode.

In an embodiment, the blocking layer may overlap with an upper surface of the bank layer.

In an embodiment, the blocking layer may include a first opening exposing at least a portion of an upper surface of the bank layer.

In an embodiment, an end of the blocking layer may be on a side surface of the bank layer.

In an embodiment, an end of the blocking layer may be on the upper surface of the bank layer.

In an embodiment, the display apparatus may further include a spacer over the bank layer, and at least a portion of the blocking layer may be located over the spacer.

In an embodiment, the blocking layer may include a second opening exposing an upper surface of the spacer.

In an embodiment, a height of an end of the blocking layer may be lower than a height of the upper surface of the spacer.

In an embodiment, an end of the blocking layer may be located on a side surface of the spacer.

In an embodiment, the display apparatus may further include: a planarization insulating layer located between the substrate and the pixel electrode; a first structure penetrating the planarization insulating layer; and an optical sensor overlapping with the first structure.

The above and other aspects and features will become more apparent from the detailed description, the accompanying drawings, and the appended claims.

DETAILED DESCRIPTION

In the figures, the x-axis, the y-axis, and the z-axis are not limited to three axes of the rectangular coordinate system, and may be interpreted in a broader sense. For example, the x-axis, the y-axis, and the z-axis may be perpendicular to or substantially perpendicular to one another, or may represent different directions from each other that are not perpendicular to one another.

FIG.1is a perspective view schematically illustrating a display apparatus according to an embodiment.

Referring toFIG.1, a display apparatus1may include a first area A1, and a second area A2surrounding (e.g., around a periphery of) the first area A1. A plurality of pixels, for example, such as an array of pixels, may be arranged at (e.g., in or on) the second area A2, and the second area A2may be configured to display an image through the array of pixels. The second area A2may correspond to an active area capable of displaying an image. The first area A1may be entirely surrounded (e.g., around a periphery thereof) by the second area A2. The first area A1may be an area in which an optical sensor capable of providing various suitable functions to the display apparatus1may be arranged. The first area A1may correspond to a transmission area through which light propagating to the optical sensor may be transmitted.

A third area A3may be provided between the first area A1and the second area A2. The third area A3may be a non-display area in which pixels are not arranged, and lines bypassing the first area A1may be arranged at (e.g., in or on) the third area A3. A fourth area A4surrounding (e.g., around a periphery of) the second area A2may be a non-display area in which pixels are not arranged, and various lines and internal circuits may be arranged at (e.g., in or on) the fourth area A4.

Each pixel provided in the display apparatus1may include a light emitting diode as a display element capable of emitting light of a suitable color (e.g., a certain or predetermined color). For example, the light emitting diode may include an organic light emitting diode including an organic material as an emission layer. As another example, the light emitting diode may include an inorganic light emitting diode. As another example, the light emitting diode may include a quantum dot as an emission layer. Hereinafter, for convenience, the light emitting diode may be described in more detail in the context of an organic light emitting diode, but the present disclosure is not limited thereto.

FIG.1illustrates that the first area A1is arranged at a center portion of the second area A2in a widthwise direction (e.g., the X-axis direction) of the display apparatus1. In other embodiments, the first area A1may be arranged to be offset to the left side or the right side in the widthwise direction of the display apparatus1. The first area A1may be arranged at various suitable positions, such as at the upper side, at the center, or at the lower side in a lengthwise direction (e.g., the Y-axis direction) of the display apparatus1.

FIG.1illustrates that the display apparatus1includes one first area A1, but in other embodiments, the display apparatus1may include a plurality of first areas A1.

FIG.2is a cross-sectional view schematically illustrating a display apparatus according to an embodiment. For example,FIG.2may be a schematic view corresponding to a cross-section taken along the line II-II′ ofFIG.1.

Referring toFIG.2, the display apparatus1may include a display panel10, an input sensing section (e.g., an input sensor or an input sensing layer)40arranged on the display panel10, and an optical functional section (e.g., an optical functional layer)50, which may be covered by a window60. The window60may be coupled to (e.g., connected to or attached to) a component thereunder, for example, such as the optical functional section50, through an adhesive layer, such as an optical clear adhesive OCA. The display apparatus1may be provided in various suitable electronic apparatuses, such as mobile phones, tablet PCs, notebook computers, smart watches, and/or the like.

The display panel10may include a plurality of diodes arranged at (e.g., in or on) the second area A2. The input sensing section40may be configured to obtain coordinate information according to an external input, for example, such as a touch event. The input sensing section40may include a sensing electrode (e.g., a touch electrode), and trace lines connected to the sensing electrode. The input sensing section40may be disposed over the display panel10. The input sensing section40may be configured to sense an external input by a mutual capacitance method or a self capacitance method.

The input sensing section40may be directly formed over the display panel10. As another example, the input sensing section40may be separately formed from the display panel10, and then coupled (e.g., connected to or attached to) the display panel10through an adhesive layer, such as an optical clear adhesive OCA. In an embodiment, as illustrated inFIG.2, the input sensing section40may be directly formed over the display panel10, and in this case, no adhesive layer may be located between the input sensing section40and the display panel10.

The optical functional section50may include an anti-reflection layer. The anti-reflection layer may be configured to reduce a reflectance of light (e.g., external light) incident from the outside through the window60toward the display panel10. The anti-reflection layer may include a suitable material, such as a phase retarder and a polarizer. The phase retarder may be a film type or a liquid crystal coating type, and may include a half-waveplate (λ/2) phase retarder and/or a quarter-waveplate (λ/4) phase retarder. The polarizer may also be a film type or a liquid crystal coating type. The film type may include a stretched synthetic resin film, and the liquid crystal coating type may include liquid crystals arranged in a suitable arrangement (e.g., a certain or predetermined arrangement). The phase retarder and the polarizer may further include a protection film.

In other embodiments, the anti-reflection layer may include a structure including color filters and a black matrix. The color filters may be arranged considering the color of light emitted from each of the pixels of the display panel10. In other embodiments, the anti-reflection layer may include a destructive interference structure. The destructive interference structure may include a first reflection layer and a second reflection layer arranged at (e.g., in or on) different layers from each other. First reflected light and second reflected light reflected by the first reflection layer and the second reflection layer, respectively, may destructively interfere with each other, and accordingly, the external light reflectance may be reduced.

The optical functional section50may include a lens layer. The lens layer may be configured to improve the light emission efficiency of light emitted from the display panel10, or may be configured to reduce a color deviation. The lens layer may include a layer having a concave or convex lens shape, and/or may include a plurality of layers having different refractive indexes from one another. The optical functional section50may include both the anti-reflection layer and the lens layer, or may include any one of the anti-reflection layer or the lens layer.

The input sensing section40and the optical functional section50may each include a hole. For example, the input sensing section40may include a hole40H passing through (e.g., penetrating) the top and bottom surfaces of the input sensing section40, and the optical functional section50may include a hole50H passing through (e.g., penetrating) the top and bottom surfaces of the optical functional section50. The hole40H of the input sensing section40and the hole50H of the optical functional section50may be arranged in the first area A1, and may be arranged to correspond to (e.g., overlap with) each other.

When the adhesive layer between the window60and the optical functional section50includes the optical clear adhesive OCA, the adhesive layer may not include a hole corresponding to the first area A1.

An optical sensor OPS may be arranged in the first area A1. The optical sensor OPS may be an infrared sensor that receives and uses light, a camera that receives visible light to obtain an image, or a sensor that outputs and senses light to measure a distance or recognize a fingerprint. The optical sensor OPS may use light of various suitable wavelength bands, such as visible light, infrared light, and/or ultraviolet light. The first area A1may be a transmission area through which light output from the optical sensor OPS to the outside or propagating from the outside toward the electronic element may be transmitted. The optical sensor OPS may include one or more suitable components capable of adding a desired function (e.g., a certain or predetermine function) to the display apparatus1as described above, or may include various suitable components, such as accessories, capable of increasing the beauty of the display panel10.

FIG.3is a plan view schematically illustrating a display panel according to an embodiment.FIG.4is an equivalent circuit diagram schematically illustrating a pixel of a display panel. For example, the pixel PX illustrated inFIG.4may be an example of a pixel applied to the display panel10.

The display panel10may include a first area A1, a second area A2surrounding (e.g., around a periphery of) the first area A1, a third area A3between the first area A1and the second area A2, and a fourth area A4surrounding (e.g., around a periphery of) the second area A2.

The display panel10may include a plurality of pixels PX arranged at (e.g., in or on) the second area A2. As illustrated inFIG.4, each pixel PX may include a pixel circuit PC, and a display element connected to the pixel circuit PC, for example, such as an organic light emitting diode OLED. The pixel circuit PC may include a first transistor T1, a second transistor T2, and a storage capacitor Cst. Each pixel PX may emit, for example, red, green, or blue light, or red, green, blue, or white light from the organic light emitting diode OLED. The first transistor T1and the second transistor T2may be implemented as a thin film transistor.

As a switching transistor, the second transistor T2may be connected to a scan line SL and a data line DL, and may be configured to transmit a data voltage input from the data line DL to the first transistor T1according to a switching voltage input from the scan line SL. The storage capacitor Cst may be connected to the second transistor T2and a driving voltage line PL, and may be configured to store a voltage corresponding to a difference between a voltage received from the second transistor T2and a first power voltage ELVDD supplied to the driving voltage line PL.

As a driving transistor, the first transistor T1may be connected to the driving voltage line PL and the storage capacitor Cst, and may be configured to control a driving current flowing from the driving voltage line PL through the organic light emitting diode OLED in response to a voltage value stored in the storage capacitor Cst. The organic light emitting diode OLED may emit light having a desired brightness (e.g., a certain or predetermined brightness) according to the driving current. An opposite electrode (e.g., a cathode) of the organic light emitting diode OLED may be supplied with a second power voltage ELVSS.

FIG.4illustrates that the pixel circuit PC includes two transistors and one storage capacitor, but the present disclosure is not limited thereto, and in other embodiments, the number of transistors and/or the number of storage capacitors may be variously modified according to a desired design of the pixel circuit PC.

Referring again toFIG.3, the third area A3may surround (e.g., around a periphery of) the first area A1. The third area A3may be an area in which a display element, such as an organic light emitting diode for emitting light, is not arranged. Signal lines for providing signals to the pixels PX provided around (e.g., adjacent to) the first area A1may pass through (e.g., may extend along) the third area A3. A first scan driver1100and a second scan driver1200for providing a scan signal to each of the pixels PX, a data driver1300for providing a data signal to each of the pixels PX, and a main power line for providing the first and second power voltages ELVDD and ELVSS may be arranged at (e.g., in or on) the fourth area A4. The first scan driver1100and the second scan driver1200may be arranged at (e.g., in or on) the fourth area A4, and may be arranged at opposite sides, respectively, of the second area A2, with the second area A2therebetween.

FIG.3illustrates that the data driver1300is arranged adjacent to one side of a substrate100, but in other embodiments, the data driver1300may be disposed over a flexible printed circuit board (FPCB) that is electrically connected to a pad arranged at one side of the display panel10.

FIG.5is a plan view illustrating an enlarged portion of a display panel according to an embodiment.

Referring toFIG.5, some pixels PX from among the pixels PX formed at (e.g., in or on) the second area A2may be spaced apart from each other with the first area A1therebetween. For example, the first area A1may be located between two pixels PX arranged along the X-axis direction ofFIG.5. Similarly, the first area A1may be located between two pixels PX arranged along the Y-axis direction ofFIG.5.

Two pixels PX arranged along the Y-axis direction with the first area A1therebetween may be electrically connected to the same data line DL, and the data line DL may be bent at (e.g., in or on) the third area A3. In other words, the data line DL may be arranged to bypass the first area A1. For example, a portion of the data line DL may be bent, and may extend along an edge of the first area A1at (e.g., in or on) the third area A3, for example, along an arc direction of the first area A1.

In other embodiments, the data line DL may be disconnected with the first area A1between disconnected portions of the data line DL. In other words, the data line DL may include a first data line DL-L1and a second data line DL-L2spaced apart from each other, with the first area A1therebetween. The first data line DL-L1and the second data line DL-L2may be connected to each other by a bypass line DWL. The bypass line DWL may be arranged at (e.g., in or on) a different layer from that of the data line DL, and may be connected to the data line DL through a contact hole. The bypass line DWL may be arranged at (e.g., in or on) the third area A3, and may extend to bypass the first area A1along the edge of the first area A1.

As used herein, the bypass line DWL may refer to a connection line for connecting the lines that are disconnected with the first area A1therebetween, as well as all the lines extending from the second area A2and passing through (e.g., extending along) the third area A3.

Two pixels PX arranged along the X-axis direction with the first area A1therebetween may be electrically connected to different scan lines SL. The scan lines SL arranged on the left side of the first area A1may be electrically connected to the first scan driver1100, and the scan lines SL arranged on the right side of the first area A1may be electrically connected to the second scan driver1200(e.g., seeFIG.3). When the display panel10includes two scan driving circuits as illustrated inFIG.3, the pixels PX arranged on opposite sides of the first area A1may be electrically connected to the scan lines SL that are spaced apart from each other. In other words, some of the scan lines SL may be spaced apart from each other, with the first area A1therebetween.

In other embodiments, when the second scan driver1200is omitted, two pixels PX arranged along the X-axis direction with the first area A1therebetween may be connected to the same scan line, and the scan line may include a bypass portion extending along the arc direction of the first area A1at (e.g., in or on) the third area A3, similar to that of the data line DL.

FIG.6is a cross-sectional view of a display apparatus according to an embodiment. For example,FIG.6may be a view corresponding to a cross-section taken along the line VI-VI′ ofFIG.5.

Referring toFIG.6, the display apparatus1may include a stacked structure of a substrate100, a pixel circuit layer PCL, a display element layer DEL, a blocking layer300, and an encapsulation layer400.

The substrate100may have a multilayered structure including a base layer including a polymer resin, and an inorganic layer. For example, the substrate100may include the base layer including the polymer resin, and a barrier layer including an inorganic insulating layer. For example, the substrate100may include a first base layer101, a first barrier layer102, a second base layer103, and a second barrier layer104, which are sequentially stacked. The first base layer101and the second base layer103may include polyimide (PI), polyethersulfone (PES), polyarylate, polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polycarbonate, cellulose triacetate (TAC), and/or cellulose acetate propionate (CAP). The first barrier layer102and the second barrier layer104may include an inorganic insulating material, such as silicon oxide, silicon oxynitride, and/or silicon nitride. The substrate100may be flexible.

The pixel circuit layer PCL may be disposed over the substrate100.FIG.6illustrates that the pixel circuit layer PCL includes a thin film transistor TFT, and a buffer layer111, a first gate insulating layer112, a second gate insulating layer113, an interlayer insulating layer114, a first planarization insulating layer115, and a second planarization insulating layer116, which may be disposed under and/or over the elements of the thin film transistor TFT.

The buffer layer111may reduce or block the penetration of foreign materials, moisture, and/or external air from under the substrate100, and may provide a flat or substantially flat surface over the substrate100. The buffer layer111may include an inorganic insulating material, such as silicon oxide, silicon oxynitride, or silicon nitride, and may be formed in a single-layer or multiple-layered structure including one or more of the above inorganic insulating materials.

The thin film transistor TFT may be disposed over the buffer layer111. The thin film transistor TFT may include a semiconductor layer Act, and the semiconductor layer Act may include polysilicon. As another example, the semiconductor layer Act may include amorphous silicon, an oxide semiconductor, an organic semiconductor, or the like. The semiconductor layer Act may include a channel area C, and a source area S and a drain area D arranged on opposite sides, respectively, of the channel area C. A gate electrode GE may overlap with the channel area C.

The gate electrode GE may include a low-resistance metal material. The gate electrode GE may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may include a single layer or multiple layers including one or more of the above conductive materials.

The first gate insulating layer112may be between the semiconductor layer Act and the gate electrode GE, and may include an inorganic insulating material, such as silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnOx). The zinc oxide (ZnOx) may include zinc oxide (ZnO) and/or zinc peroxide (ZnO2).

The second gate insulating layer113may be provided to cover the gate electrode GE. Like the first gate insulating layer112, the second gate insulating layer113may include an inorganic insulating material, such as silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnOx). The zinc oxide (ZnOx) may include zinc oxide (ZnO) and/or zinc peroxide (ZnO2).

An upper electrode Cst2of the storage capacitor Cst may be disposed over the second gate insulating layer113. The upper electrode Cst2may overlap with the gate electrode GE thereunder. In this case, the gate electrode GE and the upper electrode Cst2overlapping with each other with the second gate insulating layer113therebetween may form the storage capacitor Cst. In other words, the gate electrode GE may function as a lower electrode Cst1of the storage capacitor Cst.

As such, the storage capacitor Cst and the thin film transistor TFT may be formed to overlap with each other. In some embodiments, the storage capacitor Cst may be formed to not overlap with the thin film transistor TFT.

The upper electrode Cst2may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and/or copper (Cu), and may include a single layer or multiple layers of one or more of the above materials.

The interlayer insulating layer114may cover the upper electrode Cst2. The interlayer insulating layer114may include an inorganic insulating material, such as silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnOx). The zinc oxide (ZnOx) may include zinc oxide (ZnO) and/or zinc peroxide (ZnO2). The interlayer insulating layer114may include a single layer or multiple layers including one or more of the above inorganic insulating materials.

Each of a drain electrode DE and a source electrode SE may be located over the interlayer insulating layer114. The drain electrode DE and the source electrode SE may be connected to the drain area D and the source area S, respectively, through contact holes formed in (e.g., penetrating) the insulating layers thereunder. The drain electrode DE and the source electrode SE may include a suitable material having high conductivity. The drain electrode DE and the source electrode SE may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may include a single layer or multiple layers including one or more of the above conductive materials. In an embodiment, the drain electrode DE and the source electrode SE may have a multilayered structure of Ti/Al/Ti.

A planarization insulating layer may be disposed over the substrate100. The planarization insulating layer may be located between the substrate100and a pixel electrode210. The planarization insulating layer may include the first planarization insulating layer115disposed over the substrate100, and the second planarization insulating layer116disposed over the first planarization insulating layer115.

The first planarization insulating layer115may cover the drain electrode DE and the source electrode SE. The first planarization insulating layer115may include an organic insulating material, such as a general-purpose polymer such as polymethylmethacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or any suitable blend thereof.

The second planarization insulating layer116may include the same material as that of the first planarization insulating layer115. The second planarization insulating layer116may include an organic insulating material, such as a general-purpose polymer such as polymethylmethacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or any suitable blend thereof.

The pixel electrode210may be disposed over the substrate100. The pixel electrode210may be disposed over the planarization insulating layer. For example, the pixel electrode210may be disposed over the second planarization insulating layer116. The pixel electrode210of the organic light emitting diode OLED may be electrically connected to the thin film transistor TFT through contact holes formed in (e.g., penetrating) the second planarization insulating layer116and the first planarization insulating layer115, and a contact metal CM disposed over the first planarization insulating layer115.

The pixel electrode210may include a conductive oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). In another embodiment, the pixel electrode210may include a reflective layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or any suitable compound thereof. In another embodiment, the pixel electrode210may further include a layer formed of ITO, IZO, ZnO, or In2O3over/under the reflective layer.

A bank layer117including a pixel opening117OP exposing at least a portion of the pixel electrode210may be disposed over the pixel electrode210. The bank layer117may include an organic insulating material and/or an inorganic insulating material. The pixel opening117OP may define an emission area of light emitted from the organic light emitting diode OLED. For example, a size/width of the pixel opening117OP may correspond to a size/width of the emission area. Thus, the size and/or width of the pixel PX may depend on the size and/or width of the pixel opening117OP of the bank layer117corresponding thereto.

A spacer SPC may be disposed over the bank layer117. The spacer SPC may have an island-shaped insulating pattern. The spacer SPC may have a polygonal shape, such as a square shape, a circular shape, a triangular shape, or an elliptical shape. The spacer SPC may include an organic insulating material, such as polyimide. As another example, the spacer SPC may include an inorganic insulating material, such as silicon nitride or silicon oxide, or may include an organic insulating material and an inorganic insulating material. The spacer SPC may include a different material from that of the bank layer117. As another example, the spacer SPC may include the same material as that of one of the first planarization insulation layer115, the second planarization insulation layer116, and the bank layer117.

The intermediate layer220may include an emission layer222formed to correspond to the pixel electrode210. The emission layer222may include a high-molecular weight or a low-molecular weight organic material for emitting light of a desired color (e.g., a certain or predetermined color). As another example, the emission layer222may include an inorganic light emitting material, or may include quantum dots.

In an embodiment, the intermediate layer220may include a first functional layer221and a second functional layer223disposed under and over the emission layer222, respectively. The first functional layer221may include, for example, a hole transport layer (HTL), or may include an HTL and a hole injection layer (HIL). The second functional layer223may be disposed over the emission layer222, and may include an electron transport layer (ETL) and/or an electron injection layer (EIL). The first functional layer221and/or the second functional layer223may be a common layer formed to entirely or substantially entirely cover the substrate100.

The common electrode230may be disposed over the pixel electrode210, and may overlap with the pixel electrode210. The common electrode230may include a conductive material having a low work function. For example, the common electrode230may include a (semi)transparent layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or any suitable alloy thereof. As another example, the common electrode230may further include a layer such as ITO, IZO, ZnO, or In2O3over the (semi)transparent layer including one or more of the above materials. The common electrode230may be integrally formed to entirely or substantially entirely cover the substrate100.

The encapsulation layer400may be disposed over the display element layer DEL, and may cover the display element layer DEL. The encapsulation layer400may include at least one inorganic encapsulation layer, and at least one organic encapsulation layer. In an embodiment, as illustrated inFIG.6, the encapsulation layer400includes a first inorganic encapsulation layer410, an organic encapsulation layer420, and a second inorganic encapsulation layer430that are sequentially stacked.

The first inorganic encapsulation layer410and the second inorganic encapsulation layer430may include one or more inorganic materials from among aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The organic encapsulation layer420may include a polymer-based material. The polymer-based material may include an acryl-based resin, an epoxy-based resin, polyimide, polyethylene, and/or the like. In an embodiment, the organic encapsulation layer420may include acrylate. The organic encapsulation layer420may be formed by curing a monomer, or applying a polymer. The organic encapsulation layer420may be transparent.

In some embodiments, a touch sensor layer may be further disposed over the encapsulation layer400, and an optical functional layer may be further disposed over the touch sensor layer. The touch sensor layer may be configured to obtain coordinate information according to an external input, for example, such as a touch event. The optical functional layer may reduce a reflectance of light (e.g., external light) incident from the outside toward the display apparatus, and/or may improve the color purity of light emitted from the display apparatus. In an embodiment, the optical functional layer may include a phase retarder and/or a polarizer. The phase retarder may be a film type or a liquid crystal coating type and may include a λ/2 phase retarder and/or a λ/4 phase retarder. The polarizer may also be a film type or a liquid crystal coating type. The film type may include a stretched synthetic resin film, and the liquid crystal coating type may include liquid crystals arranged in a suitable arrangement (e.g., a certain or predetermined arrangement). The phase retarder and the polarizer may further include a protection film.

An adhesive member may be arranged between the touch electrode layer and the optical functional layer. The adhesive member may include any suitable adhesive known to those having ordinary skill in the art. The adhesive member may include a pressure sensitive adhesive (PSA).

The blocking layer300may be disposed over the bank layer117and the spacer SPC. The blocking layer300may block ultraviolet rays. For example, the blocking layer300may reflect or absorb incident ultraviolet light. In this structure, the blocking layer300may reduce a phenomenon in which ultraviolet rays are transmitted through the bank layer117, the spacer SPC, and the layers thereunder. Thus, a phenomenon in which the bank layer117, the spacer SPC, and the layers thereunder react with the ultraviolet rays to induce outgassing may be reduced.

At least a portion of the blocking layer300may be disposed over the bank layer117. The blocking layer300may overlap with an upper surface117S of the bank layer117. For example, the blocking layer300may overlap with the upper surface117S of the bank layer117and a side surface of the bank layer117. In this structure, a size of an overlapping area between the blocking layer300and the bank layer117may be increased. Thus, the blocking layer300may effectively reduce a phenomenon in which ultraviolet rays are transmitted through the bank layer117.

At least a portion of the blocking layer300may be disposed over the spacer SPC. The blocking layer300may overlap with the side surface of the bank layer117. The blocking layer300may overlap with at least one of the bank layer117or the spacer SPC disposed over the bank layer117. For example, as illustrated inFIG.6, the blocking layer300may overlap with both the bank layer117and the spacer SPC disposed over the bank layer117. In this structure, an end of the blocking layer300may be arranged on a side surface of the spacer SPC and the bank layer117. However, the present disclosure is not limited thereto, and the blocking layer300may overlap with one of the side surface of the bank layer117or the side surface of the spacer SPC.

The blocking layer300may include a second opening OP302exposing an upper surface SPCS of the spacer SPC. An end of the blocking layer300may be arranged on the side surface of the spacer SPC, and a height (e.g., in the Z-axis direction) of the end of the blocking layer300may be lower than a height (e.g., in the Z-axis direction) of the upper surface SPCS of the spacer SPC. In this structure, in a process of disposing a mask assembly over the spacer SPC to deposit an emission layer, the mask assembly may not contact the blocking layer300. Thus, a phenomenon in which the blocking layer300may be damaged due to a collision between the mask assembly and the blocking layer300may be prevented or substantially prevented.

The blocking layer300may be arranged to be spaced apart from the pixel electrode210. The blocking layer300may include a third opening OP303overlapping with the pixel electrode210. In this case, an end of the blocking layer300may be arranged on the side surface of the bank layer117. Thus, in a process of applying a voltage to the pixel electrode210, a phenomenon in which electricity is generated between the pixel electrode210and the blocking layer300may be prevented or substantially prevented.

A thickness of the blocking layer300may be adjusted for sufficient and effective absorption and reflection of ultraviolet light. For example, the blocking layer300may have a thickness of about 500 Å to about 1000 Å. Also, the blocking layer300may include an inorganic blocking layer having suitable ultraviolet light blocking properties (e.g., excellent ultraviolet blocking properties), for example, such as at least one of ZnOx, TiOx, SixNy, or TaxOy. The blocking layer300may be provided as a layer with a suitable thickness (e.g., a certain or predetermined thickness) to effectively reflect and absorb ultraviolet light. As another example, the blocking layer300may be provided as a stacked structure of a plurality of layers to effectively block light in the ultraviolet light range.

FIG.7is a plan view of a display apparatus according to an embodiment. For example,FIG.7may correspond to a view from a plane taken along the line VII-VII′ ofFIG.6, and illustrates the bank layer117, the spacer SPC, and the blocking layer300.

An end of the blocking layer300may be arranged along a periphery of the side surface of the spacer SPC. A shape of the second opening OP302of the blocking layer300may correspond to the shape of the spacer SPC. For example, as illustrated inFIG.7, when the sample (e.g., the planar shape) of the spacer SPC is rectangular, the shape (e.g., the planar shape) of the second opening OP302may be rectangular. However, the present disclosure is not limited thereto, and the blocking layer300and the spacer SPC may have any suitable shape (e.g., any suitable planar shape).

An end of the blocking layer300may be arranged along a periphery of the side surface of the bank layer117. A shape of the third opening OP303of the blocking layer300may correspond to a shape of the pixel opening117OP of the bank layer117. For example, as illustrated inFIG.7, when the shape (e.g., the planar shape) of the pixel opening117OP is rectangular, the shape (e.g., the planar shape) of the third opening OP303may be rectangular. However, the present disclosure is not limited thereto, and the blocking layer300and the pixel opening117OP may have any suitable shape (e.g., any suitable planar shape).

FIG.8is a cross-sectional view schematically illustrating a display apparatus according to an embodiment. For example,FIG.8may correspond to a view of a cross-section taken along the line VIII-VIII′ ofFIG.5. InFIG.8, the same reference numerals are used to denote the same or substantially the same elements and members as those described above with reference toFIG.6, and thus, redundant description thereof may not be repeated.

The buffer layer111, the first gate insulating layer112, the second gate insulating layer113, and the interlayer insulating layer114may include a fourth opening OP110. The fourth opening OP110may pass through (e.g., may penetrate) the buffer layer111, the first gate insulating layer112, the second gate insulating layer113, and the interlayer insulating layer114. The fourth opening OP110may be arranged at a position corresponding to the first area A1(e.g., seeFIGS.1through3). Accordingly, light transmittance of the first area A1may be increased. In some embodiments, when the first planarization insulating layer115is formed on the interlayer insulating layer114, the first planarization insulating layer115may be formed to fill the fourth opening OP110. A bypass line DWL may be located between the buffer layer111and the first gate insulating layer112, between the first gate insulating layer112and the second gate insulating layer113, and/or between the second gate insulating layer113and the interlayer insulating layer114.

A first structure STR1may be arranged in the planarization insulating layer. The first structure STR1may pass through (e.g., may penetrate) the planarization insulating layer. The first structure STR1may include a second hole115H arranged in (e.g., penetrating) the first planarization insulating layer115, and a first hole116H arranged in (e.g., penetrating) the second planarization insulating layer116.

The second hole115H may be arranged in (e.g., may penetrate) the first planarization insulating layer115. The second hole115H may overlap with the fourth opening OP110. The second hole115H may include a convex curved surface. For example, a shape of the second hole115H may include a hemispherical portion. The second hole115H may pass through (e.g., may penetrate) the first planarization insulating layer115, and thus, a portion of the upper surface of the substrate100may be exposed from the first planarization insulating layer115. The second hole115H may be arranged to contact (e.g., to expose) an edge of the interlayer insulating layer114.

A source-drain layer SD may be disposed over the first planarization insulating layer115. The source-drain layer SD may include a fifth opening OPSD. The fifth opening OPSD may overlap with the fourth opening OP110and the second hole115H. An area of a planar shape of the fifth opening OPSD may be smaller than an area of a planar shape of the second hole115H. An end of the source-drain layer SD may protrude from the first planarization insulating layer115toward a center axis CL.

The second planarization insulation layer116may be disposed over the first planarization insulation layer115. The first hole116H may be arranged in (e.g., may penetrate) the second planarization insulating layer116. The first hole116H may include a slanted or a convex curved surface. For example, a shape of the first hole116H may include a portion of a hemispherical portion. An edge of the second planarization insulating layer116may be arranged at the end of the source-drain layer SD.

The first functional layer221may include a (1-1)th functional layer221aarranged on the left side with respect to the center axis CL, and a (1-2)th functional layer221barranged on the right side with respect to the center axis CL. The first functional layer221may further include a (1-3)th functional layer221carranged between the (1-1)th functional layer221aand the (1-2)th functional layer221b.

The (1-1)th functional layer221aand the (1-2)th functional layer221bmay be disposed over the second planarization insulating layer116. The (1-1)th functional layer221aand the (1-2)th functional layer221bmay be arranged on the upper surface of the second planarization insulation layer116, the side surface of the second planarization insulation layer116, and the side surface of the source-drain layer SD. The (1-3)th functional layer221cmay be disposed over the substrate100. The (1-3)th functional layer221cmay be arranged on the upper surface of the substrate100, and a side surface of the first planarization insulating layer115. The (1-3)th functional layer221cmay overlap with the fifth opening OPSD. For example, an area of a planar shape of the (1-3)th functional layer221cmay be greater than the area of the planar shape of the fifth opening OPSD.

The second functional layer223may include a (2-1)th functional layer223aarranged on the left side with respect to the center axis CL, and a (2-2)th functional layer223barranged on the right side with respect to the center axis CL. The second functional layer223may further include a (2-3)th functional layer223carranged between the (2-1)th functional layer223aand the (2-2)th functional layer223b.

The (2-1)th functional layer223amay be disposed over the (1-1)th functional layer221a, the (2-2)th functional layer223bmay be disposed over the (1-2)th functional layer221b, and the (2-3)th functional layer223cmay be disposed over the (1-3)th functional layer221c. The (2-3)th functional layer223cmay overlap with the fifth opening OPSD. For example, an area of a planar shape of the (2-3)th functional layer223cmay be greater than the area of the planar shape of the fifth opening OPSD.

The common electrode230may include a first common electrode230aarranged on the left side with respect to the center axis CL, and a second common electrode230barranged on the right side with respect to the center axis CL. The common electrode230may further include a third common electrode230carranged between the first common electrode230aand the second common electrode230b.

The first common electrode230amay be disposed over the (2-1)th functional layer223a, the second common electrode230bmay be disposed over the (2-2)th functional layer223b, and the third common electrode230cmay be disposed over the (2-3)th functional layer223c. The third common electrode230cmay overlap with the fifth opening OPSD. For example, an area of a planar shape of the third common electrode230cmay be greater than the area of the planar shape of the fifth opening OPSD.

Because the end of the source-drain layer SD protrudes inward from the first planarization insulating layer115, in a process of depositing the first functional layer221, the second functional layer223, and the common electrode230, the (1-1)th functional layer221a, the (1-2)th functional layer221b, and the (1-3)th functional layer221cmay be arranged to be spaced apart from each other. Similarly, the (2-1)th functional layer223a, the (2-2)th functional layer223b, and the (2-3)th functional layer223cmay be arranged to be spaced apart from each other, and the first common electrode230a, the second common electrode230b, and the third common electrode230cmay be arranged to be spaced apart from each other. Thus, when moisture is injected into the (1-3)th functional layer221cand the (2-3)th functional layer223c, the moisture may be prevented or substantially prevented from being transmitted to the (1-1)th functional layer221aand the (1-3)th functional layer221c.

The first inorganic encapsulation layer410may be disposed over the second functional layer223. The first inorganic encapsulation layer410may overlap with the upper surface of the second functional layer223, the side surface of the first planarization insulating layer115, and the lower surface of the source-drain layer SD. The first inorganic encapsulation layer410may seal between the first functional layer221, the second functional layer223, and the common electrode230that are divided into three parts.

The optical sensor OPS may be arranged to overlap with the first structure STR1. The optical sensor OPS may overlap with the first hole116H, the fifth opening OPSD, and the second hole115H. The optical sensor OPS may be arranged at a position corresponding to the first area A1(e.g., seeFIGS.1to3).

FIGS.9through26are cross-sectional views illustrating various processes of a method of manufacturing a display apparatus according to an embodiment. InFIGS.9through26, the same reference symbols are used to denote the same or substantially the same elements and members as those described above with reference toFIGS.6to8, and thus, redundant description thereof may not be repeated.

FIG.9may correspond to a view of a cross-section taken along the line VIII-VIII′ ofFIG.5, andFIG.10may correspond to a view of a cross-section taken along the line VI-VI′ ofFIG.5.

Referring toFIG.9, a first hole116H may be arranged in the second planarization insulating layer116. For example, the first hole116H may be arranged in the second planarization insulation layer116by removing a portion of the second planarization insulation layer116. The first hole116H may pass through (e.g., may penetrate) the second planarization insulating layer116. A blocking layer300may be disposed over the second planarization insulating layer116. The blocking layer300may be arranged along surfaces of the second planarization insulating layer116and the first planarization insulating layer115. The blocking layer300may be arranged on the upper surface of the second planarization insulating layer116. Also, the blocking layer300may be arranged on the side surface of the second planarization insulation layer116and the upper surface of the first planarization insulation layer115, which are arranged in the first hole116H.

Referring toFIG.10, the blocking layer300may be disposed over the bank layer117. The blocking layer300may be arranged along surfaces of the pixel electrode210, the bank layer117, and the spacer SPC. The blocking layer300may be arranged on the upper surface of the pixel electrode210, the side and upper surfaces of the bank layer117, and the side and upper surfaces of the spacer SPC.

The process of arranging the blocking layer300as illustratedFIG.9and the process of arranging the blocking layer300as illustrated inFIG.10may be concurrently (e.g., simultaneously or substantially simultaneously) performed with each other.

FIG.11may correspond to a view of a cross-section taken along the line VIII-VIII′ ofFIG.5, andFIG.12may correspond to a view of a cross-section taken along the line VI-VI′ ofFIG.5.

Referring toFIG.11, a first photoresist layer PR1may be disposed over the blocking layer300. The first photoresist layer PR1may be arranged on the upper surface of the blocking layer300. The first photoresist layer PR1may include a first photo opening PROP1. The first photo opening PROP1may overlap with the first hole116H. The area of the planar shape of the first photo opening PROP1may be greater than the area of the planar shape of the first hole116H. Thus, the first photoresist layer PR1may not overlap with the first hole116H.

Referring toFIG.12, the first photoresist layer PR1may be disposed over the blocking layer300.

The process of arranging the first photoresist layer PR1as illustrated inFIG.11and the process of arranging the first photoresist layer PR1as illustrated inFIG.12may be concurrently (e.g., simultaneously or substantially simultaneously) performed with each other.

FIG.13may correspond to a view of a cross-section taken along the line VIII-VIII′ ofFIG.5, andFIG.14may correspond to a view of a cross-section taken along the line VI-VI′ ofFIG.5.

Referring toFIG.13, a first etchant EC1may be sprayed on the first photoresist layer PR1. The first etchant EC1may be sprayed through a first nozzle NOZ1. A portion of the blocking layer300may be removed by reacting with the first etchant EC1. The blocking layer300overlapping with the first photoresist layer PR1may not be exposed to the first etchant EC1. Thus, the blocking layer300overlapping with the first photoresist layer PR1may not be removed by the first etchant EC1. The portion of the blocking layer300overlapping with the first photo opening PROP1may be exposed to the first etchant EC1. Thus, the portion of the blocking layer300overlapping with the first photo opening PROP1may be removed by the first etchant EC1. In other words, the portion of the blocking layer300arranged on the side surface of the second planarization insulating layer116where the first hole116H is arranged, and the upper surface of the first planarization insulating layer115may be removed by reacting with the first etchant EC1.

Referring toFIG.14, the first etchant EC1may be sprayed on the first photoresist layer PR1. The first etchant EC1may be sprayed through the first nozzle NOZ1to remove the blocking layer300that reacts with the first etchant EC1. InFIG.14, the blocking layer300may overlap with the first photoresist layer PR1. Thus, the blocking layer300may not be exposed to the first etchant EC1, and may not be removed by the first etchant EC1.

The process of spraying the first etchant EC1by the first nozzle NOZ1as illustrated inFIG.13and the process of spraying the first etchant EC1by the first nozzle NOZ1as illustrated inFIG.14may be concurrently (e.g., simultaneously or substantially simultaneously) performed with each other.

FIG.15may correspond to a view of a cross-section taken along the line VIII-VIII′ ofFIG.5, andFIG.16may correspond to a view of a cross-section taken along the line VI-VI′ ofFIG.5.

Referring toFIGS.15and16, all of the first photoresist layer PR1may be removed. The process of removing the first photoresist layer PR1as illustrated inFIG.15and the process of removing the first photoresist layer PR1as illustrated inFIG.16may be concurrently (e.g., simultaneously or substantially simultaneously) performed with each other.

FIG.17may correspond to a view of a cross-section taken along the line VIII-VIII′ ofFIG.5, andFIG.18may correspond to a view of a cross-section taken along the line VI-VI′ ofFIG.5.

Referring toFIG.17, an etching gas may be sprayed onto the blocking layer300. The blocking layer300and the source-drain layer SD may not be removed even when contacting the etching gas. Portions of the first planarization insulation layer115and the second planarization insulation layer116exposed from the blocking layer300and the source-drain layer SD may be removed by reacting with the etching gas.

As the portion of the second planarization insulating layer116is removed, a volume of the first hole116H may increase. In other words, the area of the first hole116H may increase in a plan view. As the portion of the second planarization insulation layer116is removed, the end of the blocking layer300may protrude from the second planarization insulation layer116toward the center axis CL. The end of the second planarization insulating layer116may be arranged on the lower surface of the blocking layer300and the edge of the source-drain layer SD.

As the portion of the first planarization insulation layer115is removed, the second hole115H may be arranged in the first planarization insulation layer115. As the portion of the first planarization insulating layer115is removed, the upper surface of the substrate may be exposed from the first planarization insulating layer115. Also, the end of the source-drain layer SD may protrude from the first planarization insulating layer115toward the center axis CL. The end of the first planarization insulating layer115may be arranged on the upper surface of the substrate and the lower surface of the source-drain layer SD.

Referring toFIG.18, the etching gas may be sprayed onto the blocking layer300. The blocking layer300may not be removed even when contacting the etching gas. InFIG.18, the first planarization insulation layer115and the second planarization insulation layer116are not exposed by the blocking layer300, and thus, may not be removed by the etching gas.

The process of spraying the etching gas as illustrated inFIG.17and the process of spraying the etching gas as illustrated inFIG.18may be concurrently (e.g., simultaneously or substantially simultaneously) performed with each other.

FIG.19may correspond to a view of a cross-section taken along the line VIII-VIII′ ofFIG.5, andFIG.20may correspond to a view of a cross-section taken along the line VI-VI′ ofFIG.5.

Referring toFIG.19, a second photoresist layer PR2may be disposed over the blocking layer300. The second photoresist layer PR2may be arranged to overlap with the first hole116H and the second hole115H. The second photoresist layer PR2may be arranged on the upper surface of the blocking layer300, the side surface of the blocking layer300, the lower surface of the blocking layer300, the side surface of the second planarization insulating layer116, the side surface of the source-drain layer SD, the lower surface of the source-drain layer SD, the side surface of the first planarization insulating layer115, and the upper surface of the substrate.

Referring toFIG.20, the second photoresist layer PR2may be disposed over the blocking layer300.

The process of arranging the second photoresist layer PR2as illustrated inFIG.19and the process of arranging the second photoresist layer PR2as illustrated inFIG.20may be concurrently (e.g., simultaneously or substantially simultaneously) performed with each other. Also, the first photoresist layer PR1as illustrated inFIGS.11and12and the second photoresist layer PR2as illustrated inFIGS.19and20may include the same or substantially the same material as each other.

FIG.21may correspond to a view of a cross-section taken along the line VIII-VIII′ ofFIG.5, andFIG.22may correspond to a view of a cross-section taken along the line VI-VI′ ofFIG.5.

Referring toFIGS.21and22, a mask MA may be disposed over the second photoresist layer PR2, and light may be irradiated onto the mask MA. The mask MA may include a mask opening MAOP. The light irradiated onto the mask MA may pass through the mask opening MAOP. The light passing through the mask opening MAOP may be irradiated onto the second photoresist layer PR2to remove a portion of the second photoresist layer PR2. In other words, the portion of the second photoresist layer PR2overlapping with the mask opening MAOP may be removed.

Referring toFIG.21, the mask opening MAOP may overlap with the second photoresist layer PR2. Light may be irradiated onto the second photoresist layer PR2, and the second photoresist layer PR2may be removed.

Referring toFIG.22, the mask opening MAOP may overlap with a portion of the second photoresist layer PR2. The mask opening MAOP may overlap with the upper and side surfaces of the spacer SPC. The mask opening MAOP may overlap with the side surface of the bank layer117and the upper surface of the pixel electrode210. Only the portion of the second photoresist layer PR2overlapping with the mask opening MAOP may be removed. In this structure, the second photoresist layer PR2remaining after irradiation of the light may be arranged on the blocking layer300on the side surface of the bank layer117and the side surface of the spacer SPC. Also, the second photoresist layer PR2remaining after irradiation of the light may be arranged on the blocking layer300on the side surface of the bank layer117and the upper surface of the bank layer117.

The mask MA as illustrated inFIG.21and the mask MA as illustrated inFIG.22may be the same mask MA. Also, the process of irradiating the light as illustrated inFIG.21and the process of irradiating the light as illustrated inFIG.22may be concurrently (e.g., simultaneously or substantially simultaneously) performed with each other.

FIG.23may correspond to a view of a cross-section taken along the line VIII-VIII′ ofFIG.5, andFIG.24may correspond to a view of a cross-section taken along the line VI-VI′ ofFIG.5.

Referring toFIG.23, a second etchant EC2may be sprayed on the second photoresist layer PR2. The second etchant EC2may be sprayed through a second nozzle NOZ2. The blocking layer300may be removed by reacting with the second etchant EC2.

Referring toFIG.24, the second etchant EC2may be sprayed on the second photoresist layer PR2. The second etchant EC2may be sprayed through the second nozzle NOZ2. The blocking layer300may be removed by reacting with the second etchant EC2. The blocking layer300overlapping with the second photoresist layer PR2may not be exposed to the second etchant EC2. Thus, the blocking layer300overlapping with the second photoresist layer PR2may not be removed by the second etchant EC2. In other words, the blocking layer300arranged on the side surface of the spacer SPC and the side surface of the bank layer117may not be removed by the second etchant EC2. Also, the blocking layer300arranged on the side surface and the upper surface of the bank layer117may not be removed by the second etchant EC2.

As illustrated inFIG.24, a portion of the blocking layer300may be removed, such that the blocking layer300may be spaced apart from the pixel electrode210.

The process of spraying the second etchant EC2by the second nozzle NOZ2as illustrated inFIG.23and the process of spraying the second etchant EC2by the second nozzle NOZ2as illustrated inFIG.24may be concurrently (e.g., simultaneously or substantially simultaneously) performed with each other. The first nozzle NOZ1illustrated inFIGS.13and14may be the same or substantially the same as the second nozzle NOZ2illustrated inFIGS.23and24. Also, the first etchant EC1illustrated inFIGS.13and14may include the same or substantially the same material as that of the second etchant EC2illustrated inFIGS.23and24.

FIG.25may correspond to a view of a cross-section taken along the line VIII-VIII′ ofFIG.5, andFIG.26may correspond to a view of a cross-section taken along the line VI-VI′ ofFIG.5.

Referring toFIGS.25and26, all of the second photoresist layer PR2may be removed. The process of removing the second photoresist layer PR2as illustrated inFIG.25and the process of removing the second photoresist layer PR2as illustrated inFIG.26may be concurrently (e.g., simultaneously or substantially simultaneously) performed with each other.

FIG.27is a cross-sectional view of a display apparatus according to another embodiment. For example,FIG.27may correspond to a view of a cross-section taken along the line VI-VI′ ofFIG.5. InFIG.27, the same reference symbols are used to denote the same or substantially the same elements and members as those described above with reference toFIG.6, and thus, redundant description thereof may not be repeated.

Unlike the embodiment described above with reference toFIG.6, inFIG.27, the blocking layer300may not be arranged on the side surfaces of the bank layer117and the spacer SPC disposed over the bank layer117. In other words, the blocking layer300may be arranged only on the upper and side surfaces of the bank layer117.

FIG.28is a cross-sectional view of a display apparatus according to another embodiment. For example,FIG.28may correspond to a view of a cross-section taken along the line VI-VI′ ofFIG.5. InFIG.28, the same reference symbols are used to denote the same or substantially the same elements and members as those described above with reference toFIG.6, and thus, redundant description thereof may not be repeated.

Unlike the embodiment described above with reference toFIG.27, inFIG.28, the blocking layer300may include a first opening OP301exposing at least a portion of the upper surface of the bank layer117. The first opening OP301may overlap with the upper surface of the bank layer117. An end of the blocking layer300may be arranged on the side surface of the bank layer117. In this structure, the height (e.g., in the Z-direction) of the blocking layer300may be lower than the height (e.g., in the Z-direction) of the upper surface of the bank layer117. Also, the blocking layer300may be arranged to be spaced apart from the pixel electrode210.

FIG.29is a cross-sectional view of a display apparatus according to another embodiment. For example,FIG.29may correspond to a view of a cross-section taken along the line VI-VI′ ofFIG.5. InFIG.29, the same reference symbols are used to denote the same or substantially the same elements and members as those described above with reference toFIG.6, and thus, redundant description thereof may not be repeated.

Unlike in the embodiment described above with reference toFIG.6, inFIG.29, the blocking layer300may include a first opening OP301exposing at least a portion of the upper surface of the bank layer117. Also, unlike in the embodiment described above with reference toFIG.28, inFIG.29, the end of the blocking layer300may be arranged on the upper and side surfaces of the bank layer117. The blocking layer300may have a shape that is bent around the edge, or in other words, the boundary between the upper surface and the side surface of the bank layer117.

The display apparatus1described above with reference toFIGS.27through29may be manufactured by the same or substantially the same method as that of the display apparatus manufacturing method described above with reference toFIGS.9through26. In addition to the display apparatus1described above with reference toFIGS.27through29, the shape and arrangement of the blocking layer300may be various modified according to the shape and pattern of the mask opening of the mask (e.g., seeFIG.22).

According to one or more embodiments of the present disclosure, gas that may be generated by the outgassing phenomenon may react with the pixel electrode to oxidize the pixel electrode, thereby reducing a phenomenon in which a size of the pixel may decrease.