Semiconductor memory device amplifying data

A semiconductor memory device includes an I/O line, a first sense amplifier connected to the first I/O line to amplify a signal applied on the first I/O line in response to a first control signal, a second sense amplifier for amplifying an output signal of the first sense amplifier in response to a second control signal, and a disabling unit for disabling the first control signal in response to an output signal of the second sense amplifier.

FIELD OF THE INVENTION

The present invention relates to a semiconductor memory device; and, more particularly, to an I/O line sense amplifier for sensing and amplifying data of I/O line.

DESCRIPTION OF RELATED ARTS

Generally, semiconductor memory devices use input/output (I/O) lines to transfer data. I/O data lines for data transfer between data I/O pads and cell area or core area are called global data line (GIO). The global data lines (GIO) are globally arranged throughout a plurality of banks. An output of a bit line sense amplifier is transferred to the global data line through a local data line (LIO).

A circuit for transferring data between the global data line and the local data line is required. In the case of DRAM, in a read operation, an I/O sense amplifier (IOSA) is used to transfer data of the local data line to the global data line. In a write operation, a write driver is used to transfer the data of the global data line to the local data bus.

The read operation outputs data out of a chip. The read operation has great influence on the operating speed of the chip. To increase the speed of the read operation, a two-stage amplification scheme has been proposed.

FIG. 1is a block diagram of a conventional two-stage I/O sense amplifier amplifier.

Referring toFIG. 1, a bit line sense amplifier10senses and amplifies data of bit lines BL and BLB and transfers the amplified data to local I/O lines LIO and LIOB. A column decoder (Y DEC)20decodes a column address and a column pulse and outputs a column address pulse YI PULSE to the bit line sense amplifier10. A first-stage sense amplifier30primarily senses and amplifies the data of the local I/O lines LIO and LIOB. A second-stage sense amplifier40secondarily senses and amplifies output signals D0and D0B of the first-stage sense amplifier30. A GIO driver50outputs data to the global I/O lines in response to output signals D1and D1B of the second-stage sense amplifier40. A first control signal generator60receives the column pulse signal Y PULSE to output a control signal IOSTB1to the first-stage sense amplifier30. A second control signal generator70receives the column pulse signal Y PULSE to output a control signal IOSTB2to the second-stage sense amplifier40.

FIG. 2is a timing diagram of the two-stage sense amplifier ofFIG. 1.

Referring toFIG. 2, in a read operation, the column decoder20receives the column address and the column pulse and outputs the column address pulse YI to the corresponding bit line sense amplifier10. The bit line sense amplifier10senses and amplifies data of the bit lines BL and BLB and outputs the amplified data to the local I/O lines LIO and LIOB. Because the line loading of the local I/O lines LIO and LIOB is relatively large compared with the drivability of the bit line sense amplifier10, the level difference between the local I/O lines LIO and LIOB is very slight. The first-stage sense amplifier30amplifies the level difference between the local I/O lines LIO and LIOB by a predetermined gain. The first-stage sense amplifier30is generally configured with a differential type sense amplifier. Then, the amplified signal is amplified to a full swing or full logic level by the second-stage sense amplifier40. The second-stage sense amplifier is generally configured with a cross-coupled type sense amplifier. This amplified signal is finally transferred to the global I/O line GIO through the global I/O driver50.

InFIG. 1, the first-stage sense amplifier30and the second-stage sense amplifier40are controlled by the first control signal IOSTB1and the second control signal IOSTB2, respectively. The first control signal generator60delays the column pulse for a predetermined time and generates the first control signal IOSTB1. The delay time secures the time at which the first-stage sense amplifier can operate after the column address pulse YI is output and the level difference between the local I/O lines LIO and LIOB is relatively large. The second control signal generator70generates the second control signal IOSTB2while adjusting the output timing such that the second-stage sense amplifier40can operate after the first-stage sense amplifier performs the amplifying operation.

The conventional I/O line sense amplifier, however, has the following problems.

Referring toFIGS. 1 and 2, when the second-stage sense amplifier40is driven, the first-stage sense amplifier30need not operate. However, the two sense amplifiers may operate at the same time. Since the second-stage sense amplifier40is the cross-coupled type amplifier, a positive feedback occurs only if the amplifying operation begins. At this point, the first-stage sense amplifier may operate unnecessarily. Specifically, because pulse widths of the first and second control signals IOSTB1and IOSTB2are fixed, the first-stage sense amplifier30and the second-stage sense amplifier40are operated during these pulse widths. This can be seen from the timing diagram ofFIG. 2. Because the second-stage sense amplifier40is a cross-coupled type amplifier, it does not continue to dissipate power once it performs the sensing operation. However, because the first-stage sense amplifier is a differential type amplifier, power is continuously dissipated during the operation of the first-stage sense amplifier. Therefore, after the positive feedback occurs in the second-stage sense amplifier40, power is unnecessarily dissipated during the remaining period of the pulse width of the first control signal IOSTB1.

Consequently, this has a bad influence on power consumption, which presents a huge burden on mobile memory devices.

SUMMARY OF THE INVENTION

It is, therefore, an object of the present invention to provide a semiconductor memory device with low power consumption.

It is another object of the present invention to provide a semiconductor memory device that can suppress power consumption by stopping an unnecessary operation during a read operation.

It is a further another object of the present invention to provide a semiconductor memory device that can remarkably reduce power consumption by efficiently controlling the operations of I/O line sense amplifiers in a read operation.

It is a further object of the present invention to provide a semiconductor memory device that can minimize an overlap period in which sense amplifiers are driven together.

In accordance with an embodiment of the present invention, there is provided a semiconductor memory device including: a first input/output (I/O) line; a first sense amplifier connected to the first I/O line to amplify a signal applied on the first I/O line; a second sense amplifier for amplifying an output signal of the first sense amplifier; and a controller for controlling the first sense amplifier by feeding back an output signal of the second sense amplifier.

The controller stops an operation of the first sense amplifier in response to the output signal of the second sense amplifier.

The semiconductor memory device further includes a bias circuit between the first sense amplifier and the second amplifier, the bias circuit being configured to continuously drive the second sense amplifier when the operation of the first sense amplifier is stopped. The controller receives the output signal of the second sense amplifier not directly but via a driver. The first I/O line is a local I/O line.

In another aspect of the present invention, there is provided a semiconductor memory device including: a first I/O line; a first sense amplifier connected to the first I/O line to amplify a signal applied on the first I/O line; a second sense amplifier for amplifying an output signal of the first sense amplifier; and an enable timing controller for controlling a driving of the first sense amplifier in response to an output signal of the second sense amplifier. The enable timing controller stops an operation of the first sense amplifier in response to the output signal of the second sense amplifier. The semiconductor memory device further includes a bias circuit between the first sense amplifier and the second amplifier, the bias circuit being configured to continuously drive the second sense amplifier when the operation of the first sense amplifier is stopped. The enable timing controller receives the output signal of the second sense amplifier not directly but via a driver. The first I/O line is a local I/O line.

In accordance with a further embodiment of the present invention, there is provided a semiconductor memory device including: a first input/output (I/O) line; a first sense amplifier connected to the first I/O line to amplify a signal applied on the first I/O line in response to a first control signal; a second sense amplifier for amplifying an output signal of the first sense amplifier in response to a second control signal; and a disabling unit for disabling the first control signal in response to an output signal of the second sense amplifier. The disabling unit stops an operation of the first sense amplifier in response to the output signal of the second sense amplifier. The semiconductor memory device further includes a bias circuit between the first sense amplifier and the second amplifier, the bias circuit being configured to continuously drive the second sense amplifier when the operation of the first sense amplifier is stopped. The disabling unit receives the output signal of the second sense amplifier not directly but via a driver. The first I/O line is a local I/O line.

DETAILED DESCRIPTION OF THE INVENTION

A semiconductor memory device in accordance with exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3is a block diagram of an I/O line sense amplifier of a semiconductor memory device in accordance with an embodiment of the present invention.

Referring toFIG. 3, a first-stage sense amplifier130primarily senses and amplifies data of local I/O lines LIO and LIOB, and a second-stage sense amplifier140secondarily senses and amplifies output signals D0and D0B of the first-stage sense amplifier130. A global I/O driver150outputs data to the global I/O lines in response to output signals D1and D1B of the second-stage sense amplifier140. A first control signal generator160receives a column pulse signal Y and outputs a first control signal IOSTB1to the first-stage sense amplifier130. A second control signal generator170outputs a second control signal IOSTB2to the second-stage sense amplifier140in response to the column pulse signal Y. A driving controller180controls driving of the first-stage sense amplifier130in response to the output signals D1and D1B of the second-stage sense amplifier140.

Referring toFIG. 3, it should be noted that the output signals D1and D1B of the second-stage sense amplifier is fed back, and an enable period of the first-stage sense amplifier130is controlled by the feedback signal. Also, when controlling the enable period of the first-stage sense amplifier130, the pulse width of the control signal IOSTB1C for the first-stage sense amplifier130is simply controlled. Therefore, the present invention can easily be applied to the existing technologies.

Preferably, the driving controller180stops the operation of the first-stage sense amplifier130in response to the output signals D1and D1B of the second-stage sense amplifier140.

The driving controller180controls an enable timing of the first-stage sense amplifier by controlling the pulse width of the control signal IOSTB1C in response to the output signals D1and D1B of the second-stage sense amplifier140.

A bias circuit is provided between the first-stage sense amplifier130and the second-stage sense amplifier140such that the second-stage sense amplifier can be continuously driven when the operation of the first-stage sense amplifier is stopped.

It is preferable that the driving controller180receive the output signals of the second-stage sense amplifier140via a driver such as an inverter, not directly. This will be described later in detail.

An operation of the I/O sense amplifier in accordance with the present invention will be described with reference toFIG. 3.

Referring toFIG. 3, the present invention is different from the prior art in that the driving controller180is further included. The design of an additional circuit for receiving the output signals D1and D1B of the second-stage sense amplifier may be changed in various manners.

The driving controller180receives the output signals D1and D1B of the second-stage sense amplifier140and determines whether or not the second-stage sense amplifier140performs the sensing operation sufficiently. When the sensing operation is not performed sufficiently, the driving controller180transfers the first control signal IOSTB1as the final control signal IOSTB1C. Then, when the sensing operation is performed sufficiently, the driving controller180interrupts the first control signal IOSTB1so that the operation of the first-stage sense amplifier130is stopped.

By stopping the operation of the first-stage sense amplifier130using the output signals of the second-stage sense amplifier140, the time period when the first-stage sense amplifier130and the second-stage sense amplifier140are driven together can be reduced to the minimum within an allowable range.

FIG. 4is a circuit diagram of the I/O line sense amplifier ofFIG. 3.

Referring toFIG. 3, the first-stage sense amplifier130is configured with two differential amplifying type circuits. The differential amplifying type circuits are driven by NMOS transistors (four NMOS transistors inFIG. 4) receiving the output signal IOSTB1C of the driving controller180, and output the signals D0and D0B. Although the first-stage sense amplifier130may be configured with a single differential amplifying circuit, it is preferable that the first-stage sense amplifier130is configured with two differential amplifying circuits. In this case, the reliability of the output signals D1and D1B is improved.

The second-stage sense amplifier140is configured with a cross-coupled type amplifying circuit driven by the second control signal IOSTB2.

At the output terminals D1and D1B of the second-stage sense amplifier140, a first output path and a second output path are provided. The first output path is configured with inverters141and142, and the second output path is configured with an inverter143.

A reset circuit140A for resetting the output signals D0and D0B of the first-stage sense amplifier130is provided between the second-stage sense amplifier140and the first-stage sense amplifier130. The reset circuit140A includes three PMOS transistors configured to commonly receive the output signal IOSTB1C of the driving controller180. That is, a first PMOS transistor supplies a power supply voltage VDD to the D0line, a second PMOS transistor is connected between the D0line and the D0B line, and a third PMOS transistor supplies the power supply voltage VDD to the D0B line. An operation of the reset circuit140A will be described below.

The global I/O driver150is connected on a path where the output signals D1and D1B of the second-stage sense amplifier140are transferred, and outputs data to the global I/O lines GIO. The global I/O driver150includes a pull-up PMOS transistor and a pull-down NMOS transistor. The pull-up PMOS transistor is connected to a D2B signal passing through the first output path of the second-stage sense amplifier140, and the pull-down NMOS transistor is connected to a D2signal passing through the second output path of the second-stage sense amplifier140.

Although not shown inFIG. 4, the first control signal generator160can be implemented with the same structure as that of the prior art. It can be seen fromFIG. 4that the first control signal IOSTB1from the first control signal generator160is input to the driving controller180through an inverter160A.

Although not shown inFIG. 4, the second control signal generator170can be implemented with the same structure as that of the prior art. It can be seen fromFIG. 4that the second control signal IOSTB2is input to the second-stage sense amplifier through inverters170A and170B. The second control signal IOSTB2from the second-stage sense amplifier170may be directly input to the second-stage sense amplifier140, or may be input through the two inverters170A and170B. The two inverters170A and170B may be used as a delay circuit for adjusting the signal timing, or a driver for amplifying the signals.

The driving controller180includes a first inverter181, a second inverter182, a NAND gate183, and a NOR gate184. The first inverter181receives the output signal D2of the second-stage sense amplifier140, and the second inverter182receives the output signal D1DB of the second-stage sense amplifier140. The NAND gate183receives output signals of the first and second inverters181and182, and the NOR gate184receives an, output of the NAND gate183and the first control signal IOSTB1.

In order not to influence the operation characteristics of the second-stage sense amplifier140, the driving controller180does not directly receive the output signals D1and D1B of the second-stage sense amplifier140, but receives the signals D2and D1DB passing through the inverters141and143. That is, the output signals Dl and DiB are not directly fed back to the driving controller180, but the signals passing through at least one stage are input thereto. InFIG. 4, the signals D2and D1DB passing through one stage are input.

The output signals of the driving controller180are maintained at the same level before the second-stage sense amplifier140performs the sensing operation, but the output signals have different levels when the sensing operation is completed. That is, the driving controller180is designed to control the first-stage sense amplifier130after determining whether the second-stage sense amplifier140performs the sensing operation sufficiently.

More specifically, when the output signals D2and D1DB of the second-stage sense amplifier140are all in logic level LOW, it means that the second-stage sense amplifier140does not complete the sensing operation. In this case, the first control signal IOSTB1passes through the inverter160A and the NOR gate184and is then transferred as the control signal IOSTB1C for the first-stage sense amplifier130. On the contrary, when one of the output signals D2and D1DB of the second-stage sense amplifier140changes into logic level HIGH, it means that the second-stage sense amplifier140completes the sensing operation. Therefore, the driving controller180shifts the level of the control signal IOSTB1C, so that the first-stage sense amplifier130will cease operation. InFIG. 4, when the output signal of the NAND gate183of the driving controller180changes into logic level HIGH, the output signal of the NOR gate184is disabled. That is, the NOR gate184is disabled to logic level LOW, regardless of the pulse level of the first control signal IOSTB1. Then, the driving controller180turns off the four NMOS transistors of the first-stage sense amplifier130, thereby stopping the operation of the first-stage sense amplifier130.

When the operation of the first-stage sense amplifier130is stopped, the reset circuit140A allows the second-stage sense amplifier140to operate normally. That is, the reset circuit140A makes the input terminals D0and D0B of the second-stage sense amplifier have the VDD level. It can be seen fromFIG. 4that three PMOS transistors of the reset circuit140A are all turned on when the driving controller180outputs the control signal IOSTB1C of logic level LOW.

FIG. 5is a timing diagram of the I/O line sense amplifier illustrated inFIGS. 3 and 4. Compared with the timing diagram ofFIG. 2, although the first and second control signals IOSTB1and IOSTB2seem to be identical to each other, the pulse width of the control signal IOSTB1C for controlling the first-stage sense amplifier130is shorter and the operation period of the first-stage sense amplifier130is shorter. The operation characteristic of the second-stage sense amplifier140is identical to the waveform ofFIG. 2.

When the two-stage I/O line sense amplifier is controlled only using the first and second control signals IOSTB1and IOSTB2having the fixed pulse width, the power is wasted during the operation of the sense amplifiers because margin for the sensing operation must be given for the preparation of process/voltage/temperature (PVT) change. Because the first sense amplifier is controlled using the feedback output signal of the second sense amplifier in the present invention, the operation of the sense amplifiers can be secured without unnecessary power consumption.

Also, the unnecessary operation of the sense amplifier can be prevented by efficiently controlling the operation of the I/O line sense amplifiers in the read operation, thereby remarkably reducing the unnecessary power consumption. In addition, the time period when the two-stage sense amplifier is driven together can be reduced to the minimum within an allowable range.

The present application contains subject matter related to Korean patent application No. 2005-90863 and 2005-118918 filed in the Korea Patent Office on Sep. 28, 2005 and Dec. 7, 2005, respectively, the entire contents of which is incorporated herein by reference.