Transmitter with feedback control

An apparatus is provided, where the apparatus includes a transmitter comprising a first stage and a second stage, wherein the first stage is to receive an input voltage and generate bias for the second stage, and wherein the second stage comprises a driver circuitry to transmit data using the bias voltage; and a control circuitry to control generation of the bias, based on receiving a feedback of the input voltage.

BACKGROUND

High speed data transmitters may suffer Alternating Current (AC) timing loss, eye margin loss, etc., while operating at relatively higher data rates. Such losses may be, among other factors, in order to support long package or board traces, to support higher loading of the devices, etc. The losses may also result due to variation in process, voltage, temperature, product life cycle time, etc.

DETAILED DESCRIPTION

A transmitter may comprise a first stage to generate bias (e.g., a bias current), and a second stage to drive data to a receiver, where the second stage may operate using the bias generated by the first stage. In an example, performance of the transmitter may degrade due to variation of various factors, e.g., variations in supply voltage, load, temperature, noise in power supply, aging, etc. For example, due to such variations, a system including the transmitter may experience AC timing loss, decline in data eye quality at the receiver, etc.

In some embodiments, in order to mitigate or reduce effects of such variations of the various factors, the bias used in the second stage may be controlled. For example, a control circuitry may receive information on variations of such factors, and may proactively tune or control the bias generation, such that the effects of such variations of the various factors are eliminated or reduced. This may result in enhanced performance of the transmitter, relatively less AC timing loss, better data eye quality, etc. Other technical effects will be evident from the various embodiments and figures.

FIG. 1schematically illustrates a transmitter100that incorporates feedback control to tune bias generation in the transmitter100, e.g., to reduce or mitigate losses (e.g., AC timing losses, eye margin losses, etc.) due to variations of one or more factors, according to some embodiments. The transmitter100may be a high-speed transmitter, e.g., transmitting data at relatively high speed (such as higher than 2 Giga Hertz, merely as an example). The transmitter100may be used in any appropriate system that transmits data at a high speed. Merely as an example, the transmitter100may be used in conjunction with double data rate (DDR) memory (e.g., to transmit data to the memory, or transmit data from the memory), such as DDR4, DDR5, or any other high-speed transmitters.

The transmitter100may be used to transmit streams of one or more bits of data. For example, a section102of the transmitter100is used for one byte of data. The transmitter100also includes sections104a,104b, . . . ,104N, where N may be an integer, such as 8, 16, or the like. The section104amay be used to transmit a stream for a first bit of data, the section104bmay be used to transmit a stream for a second bit of data, and so on. If multiple bytes are to be transmitted in parallel, multiple instances of the transmitter100may be used. Thus, the section102corresponds to per-byte of data, and individual ones of the sections104a,104b, . . . ,104N corresponds to per-bit of data. Thus, the section102caters to a byte or 8 bits of data stream, and individual ones of the sections104a,104b, . . . ,104N caters to a corresponding bit of data stream.

In an example, the section102may be referred to as a first stage of the transmitter100, and individual ones of the section104a,104b, . . . ,104N may be referred to as a second stage of the transmitter100. Thus, the transmitter100comprises a single first stage102, and a plurality of second stages104a,104b, . . . ,104N.

In some embodiments, the section102comprises a bias ladder circuitry108(also referred to as circuitry108). The circuitry108comprises resistors120a,120bcoupled between a supply voltage Vcc and ground. A node121between the resistors120a,120boutputs a common mode voltage Vcm. A capacitor122is coupled between the node121and the ground terminal.

In some embodiments, the section102comprises a regulator circuitry110(also referred to as circuitry110) and a replica circuitry112(also referred to as circuitry112). The circuitry110includes a comparator128, which compares the voltage Vcm of the node121to a voltage of a node132of the circuitry112. An output of the comparator128is grounded via a capacitor130. The output of the comparator128is also used to control a switch134, which may be a transistor. The switch134is coupled between the node132and ground.

The circuitry112comprises a resistor136coupled between (i) the node132and (ii) a supply voltage via a switch138. In an example, the replica circuitry112may be used to replicate one or more resistors of a driver circuitry158of the section104a(or any other section104b, . . . ,104N), e.g., for purposes of impedance matching.

The section102also comprises a buffer114. The buffer114is also referred to as a “per-byte buffer” or as a global buffer, as the buffer114supplies bias current for individual ones of the per-bit sections104a,104b, . . . ,104N.

In some embodiments, an output of the comparator128acts a regulated current source. For example, if various variations in the transmitter100are ignored (e.g., PVT variations, variations in the supply voltage Vcc, etc.), then the output of the comparator128acts as a regulated constant current source.

The buffer114comprises a current mirror, which includes a first pair of switches (e.g., transistors)140,142, and a second pair of switches (e.g., transistors)144,146. The transistors144,140are coupled in series between a supply and ground terminal, and the transistors142,146are coupled in series between a supply and ground terminal. Gates of the transistors144,146are coupled, and are also coupled to a drain of the transistor144. A gate of the transistor140is coupled to the output of the comparator128. A gate and a source of the transistor142are coupled. The gate of the transistor142is grounded via a capacitor148. The gate of the transistor142also provides bias143(e.g., bias current143) to the sections104a,104b, . . . ,104N. The buffer114may be used to reduce kick-back noise in the transmitter100, while distributing the bias143(e.g., bias current143) to the sections104a,104b, . . . ,104N.

In an example, the sections104a,104b, . . . ,104N have substantially similar circuit elements, and merely the section104ais illustrated in details. In some embodiments, the section104acomprises a buffer150, which includes a current mirror. The buffer150is also referred to as a “per lane buffer,” or a “per bit buffer,” as the section104ais associated with transmission of a single bit sequence.

The current mirror of the buffer150is at least in part similar to the current mirror of the buffer114. For example, the current mirror of the buffer150comprises a first pair of transistors151,152, and a second pair of transistors154,156, arranged in a similar manner as in the buffer114.

The section140acomprises a driver circuitry158, which includes resistors, switches, etc., such as resistors164,165,166, switches161,163,167,168, etc. The driver circuitry158receives data160, which may be a sequence of 1-bit data, and which drives the switches162,163. The component169symbolically illustrates communication path (e.g., board traces, package traces, interconnect structures, and/or other routing structures) between the transmitter and a receiver. The transmitter output is also labelled. The receiver includes a resistor167.

In practice, the transmitter100may suffer from various variations, e.g., process, voltage, temperature (PVT) variations, variation in supply voltage Vcc, aging of the transmitter100, variation in power demand in other components outside the transmitter (e.g., which may result in ripples or spikes in the supply voltage Vcc), and/or other variations within or external to the transmitter100. In some embodiments, the transmitter100may communicate with a control circuitry180(also referred to as circuitry180) that is to reduce or mitigate effects of such variations. The control circuitry180may be external to the transmitter100, or may be included in and be part of the transmitter100.

Merely as an example and assuming that the circuitry180is absent, the supply voltage Vcc may vary between 1.05 volts (V) to 1.35 V (e.g., due to a variation in a loading of the transmitter100, due to inherent variation of the supply voltage Vcc, etc.), which may result in variations of the output current of the transmitter100by about 1.72 milli-Ampere (mA). Such a variation may result worst cases data eye height loss of 98 milli-volts (mV), worst case power loss per channel of 68.8 mA, worst case power loss per eight channel of 550.4 mA, and percentage of power loss at a System on a Chip (SOC) of 6.55%. Thus, variations of the supply voltage Vcc may result in reduced quality of data eye at the receiver, and may result in power loss.

Ideally (e.g., when process, voltage, temperature (PVT) variations, variation in voltage Vcc, aging of the transmitter, variation in power demand in other components outside the transmitter, and/or other variations within or external to the transmitter100are ignored), the voltage Vcm output by the bias ladder circuitry108may be maintained at a constant voltage, and the bias143from the section102to the sections104a,140b, . . . ,104N are to be constant, thus resulting in proper operation of the transmitter100. However, in practice, due to PVT variations, supply voltage variations, and/or variations of other factors discussed herein, the bias current143may not be maintained at a constant or ideal value, which may result in AC timing loss, eye margin loss, etc. at the receiver end of the transmitter100. In some embodiments, to mitigate or reduce such losses, the transmitter100comprises the control circuitry180, which may receive feedback of the voltage Vcm, may receive feedback for various factors184, and may tune or control the section102. Such tuning of the section102may result in tuning the bias143, which may reduce or mitigate the losses discussed herein above.

For example, the circuitry180may generate a control signal182, to control or tune one or more components of the section102. Merely as an example, the control signal182may be a bias control signal that controls the bias current143generated by the buffer114.

AlthoughFIG. 1illustrates a specific example implementation of the transmitter100, the internal structure of the transmitter may be different, as would be appreciated by those skilled in the art. For example, instead of generating the bias143in the form of a bias current via the current mirror within the buffer114, a bias voltage may be generated (e.g., which may be used to bias the sections104a,104b, . . . ,104N). Any other appropriate variations of the transmitter100may also be possible.

FIG. 2illustrates an example control of the transmitter100by the control circuitry180, according to some embodiments. For example, as discussed with respect toFIG. 1, the control signal182generated by the circuitry180may be used to control one or more components of the section102, such that the bias143generated by the section102may be controlled. In the example ofFIG. 2, the control signal182may be used to control the transistor142of the current mirror of the buffer114. For example, controlling the switching of the transistor142may result in controlling the bias143.

AlthoughFIG. 2illustrates the circuitry180controlling the transistor142, in other examples, the circuitry180may control one or more other appropriate components of the section102as well, e.g., to control the bias143. For example, instead of (or in addition to) controlling the transistor142, the circuitry180may also control the transistor140, control the supply voltage Vcc, control values of resistances of the resistors120aand/or120b, and/or the like.

FIG. 3illustrates the control circuitry180of the transmitter100in further details, according to some embodiments. In some embodiments, the circuitry180includes a finite state machine (FSM)201to control one or more operations of the circuitry180, although the FSM301may be replaced by other circuitry or logic in another example. In some embodiments, the FSM301outputs the control signal182, which may be used to control the section102of the transmitter, as discussed with respect toFIG. 1.

In some embodiments, the circuitry180comprises supply voltage tracking circuitry305(also referred to as circuitry305), which receives a feedback of the common mode voltage Vcm from the output of the bias ladder108, and tracks variations of the voltage Vcm. For example, an output of the circuitry305may be indicative of variations in the voltage Vcm, which the FSM301may use to generate the control signal182. For example, the FSM301may generate the control signal182, such that effects of variation of the voltage Vcm may be eliminated or reduced.

Variations of Vcm may result from variations of the supply voltage Vcc and/or may result from variations in loading of the transmitter100. Hence, the circuitry305in effect tracks variations of the supply voltage Vcc and/or variations in loading of the transmitter100, and the FSM301eliminates or reduces effects of such variations via the control signal182.

In some embodiments, the circuitry180comprises resource monitor circuitry309. In an example, the resource monitor circuitry309tracks various resources of a computing device in which the transmitter100is included, and provides feedback to the FSM301. Merely as an example, the resource monitor circuitry309tracks gradual aging of various components of the computing device, including aging of the transmitter100. The aging of various components may result in gradual deterioration or degradation of one or more of the components, which may result in variation of, for example, frequency, voltage, current, tuning, gain, bandwidth, frequency, etc. associated with the components. The resource monitor circuitry309monitors and tracks such aging related variations, and the FSM301aims to mitigate or reduce effects of such aging related issues via the control signal182. In such an example, the resource monitor circuitry309may also be referred to as aging monitor circuitry.

In an example, in addition to (or instead of) tracking and monitoring aging related issues, the resource monitor circuitry309may monitor other aspects of various components, e.g., addition of (or removal of) one or more components in the computing device, tuning or change in configuration of various components of the computing device, and/or any other change in the various components of the computing device, e.g., such that the FSM301may mitigate effects of such changes.

In some embodiments, the circuitry180comprises a power management circuitry313(also referred to as circuitry313), which may warn the FSM301about potential power supply noise. In an example, the circuitry313may communicate with a power management controller314. For example, assume that the transmitter100and one or more other components of a computing device share the same power supply, where the one or more other components may be a Universal Serial Bus (USB) device, a Peripheral Component Interconnect Express (PCIe) device, a memory, a transceiver, and/or any other appropriate component(s). Assume that one or more of these components are turned on, turned off, transitions to a low-power or high-power state, etc.—e.g., there is a change in power demand of one or more of these components. Any change in the power demand, and resultant power consumption of one or more of these components may result in noise in the power supply Vcc of the transmitter (e.g., due to overshoot or undershoot, droop, etc. in the supply voltage Vcc). The power management controller314may forewarn the circuitry313about a state change in one or more of these components, e.g., warn about possible changes in power demand of one or more of these components and/or resultant power supply noise. When the FSM301receives such warning about possible power supply noise, the FSM301may mitigate such effects of noise via the control signal182.

Merely as an example, the FSM301may temporarily cause the bias current143to be higher, e.g., such that the effects of the power supply noise are reduced or eliminated. Temporarily increasing the bias current143(e.g., until the noise in the power supply Vcc is reduced or eliminated) may temporarily increase power consumption, but may result in better performance (e.g., data eye in the receiver corresponding to the transmitter100has less loss).

In some embodiments, the FSM301may include look-up tables which stores various corrective actions to be taken, based on the output of the circuitry313. For example, if the circuitry313indicates that two USB devices (e.g., which are in the same power supply as the transmitter100) are to be activated, then the FSM301may take a first corrective step via the control signal182; and if the circuitry313indicates that one USB device is to be deactivated, then the FSM301may take a different corrective step via the control signal182. Such corrective steps may be based on the look-up table accessed by the FSM.

In some embodiments, the circuitry180may include a process and temperature monitor circuitry317(also referred to as circuitry317). The circuitry317may monitor process and/or temperature variations of various components of the computing devices (e.g., in which the transmitter100is included), and the FSM301may take corrective actions. For example, in response to a rise in temperature, the FSM301may change the bias, such that the increase in the temperature does not adversely affect the quality of the data eye at the receiver.

In some embodiments, the circuitry180may include, or receive signal from, a data control circuitry321(also referred to as circuitry321). The circuitry321may be external to the circuitry180, as illustrated inFIG. 3; or the circuitry321may be internal to the circuitry180.

In some embodiments, the circuitry321may track a density of data, frequency of data, etc. transmitted by the transmitter100. For example, the circuitry321may be a memory controller (or communicate with a memory controller). For example, if the transmitter100is transmitting data to a memory, the circuitry321may be the memory controller (or communicate with the memory controller), and keep track of data density. Based on the density of data to be transmitted by the transmitter100, the FSM301may tune or control the bias of the transmitter100, so as to mitigate effects of data dependent noise due to varying data density.

Merely as an example, the data density may refer to the number of 1's and 0's transmitted by the transmitter100. Merely as an example, the data density may refer to a frequency with which 1's and 0's are transmitted by the transmitter100. For example, a higher number of 1's in the data transmitted by the transmitter100may entail a first bias control of the transmitter100by the FSM301, and a higher number of 0's in the data transmitted by the transmitter may entail a second bias control of the transmitter100by the FSM301, where the first and second bias controls may be different. For example, the FSM301may get indication of frequency component of data to be transmitted, and generate compensation used to mitigate or reduce various data dependent noise.

In some embodiments, the FSM301may give different weightage to different ones of the circuitries305,309,313,317,321, when generating the control signal182to control the bias of the transmitter100. In an example, the output of the resource monitor or aging monitor circuitry305may be varying relatively slowly with time, and the FSM301may react relatively slowly to a change in the output of the circuitry305(e.g., as the transmitter100may not change suddenly due to aging). On the other hand, the FSM301may act relatively fast to changes to the output of the circuitry321, as the output of the circuitry321may change relatively fast and dynamically with changes in data transmitted by the transmitter100. In an example, the FSM301may provide higher weightage to the output of the circuitry305, as the output of the circuitry305may be indicative of variation in the supply voltage Vcc, which may have higher impact on the bias143supplied by the section102of the transmitter100.

AlthoughFIG. 3illustrates example circuitries305, . . . ,321(e.g., output of which may be used by the FSM301to generate the control signal182), in some embodiments, output of any other appropriate circuitry may be used by the FSM301to generate the control signal182. Thus, the FSM301may track any other appropriate type of parameter variation(s) in a computing device comprising the transmitter100, and generate the control signal182to mitigate or reduce effects of such parameter variation(s). Such parameter variation(s) may include, merely as examples, variations in frequency, gain, bandwidth, and/or the like.

InFIGS. 1-3, the FSM301is assumed to be used in conjunction with the transmitter100. However, the FSM301may be used for any other type of circuitries. For example,FIG. 4illustrates some example circuitries with which the control circuitry180may be used, according to some embodiments. For example, the control circuitry180, including the FSM301and the circuitries305, . . . ,321, may be used with the section102of the transmitter100, or with an appropriate section of any of: an analog/mixed signal circuitry; an analog Radio Frequency (RF) circuitry; a high-speed receiver circuitry; a high speed PHY; a high speed transceiver; or the like, as illustrated inFIG. 4.

FIG. 5illustrates an example implementation of the supply voltage tracking circuitry305of the control circuitry180of the transmitter100, according to some embodiments. The circuitry305comprises a tracking ladder501comprising resistors502a,502b, . . . ,502fThe tracking ladder501aims to track the bias ladder circuitry108.

The tracking ladder501is coupled between a voltage Vr and ground terminal. The voltage Vr may be a clean voltage or bandgap voltage (e.g., a reference voltage, or a regulated voltage), e.g., may be relatively more stable and may have a substantially same value over time (e.g., unlike the supply voltage Vcc, the voltage Vr may not fluctuate with time).

The circuitry305comprises four comparators504a,504b,504c, and504d. The comparator504areceives a voltage VH2(e.g., at a positive terminal of the comparator) from a node between the resistors502aand502b; receives the voltage Vcm from the section102; and outputs a signal U2.

The comparator504breceives a voltage VH1(e.g., at a positive terminal of the comparator) from a node between the resistors502band502c; receives the voltage Vcm from the section102; and outputs a signal U1.

The comparator504creceives a voltage VL1from a node between the resistors502dand502e; receives the voltage Vcm from the section102(e.g., at a positive terminal of the comparator); and outputs a signal D1.

The comparator504dreceives a voltage VL2from a node between the resistors502eand502f; receives the voltage Vcm from the section102(e.g., at a positive terminal of the comparator); and outputs a signal D2.

The voltages VH2, VH1, VL1, VL2may be based on the voltage Vr, and the values of the resistors502a,502b, . . . ,502fIn some embodiments, one or more of the resistors502a,502b, . . . ,502fmay be tuned by an offset correction logic504, e.g., to correct any possible offset in the tracking ladder501. In the tracking ladder501, VH2>VH1>VL1>VL2.

Individual ones of the signals U1, U2, D1, and D2may have a value of high or low (e.g., 1 or 0), e.g., based on the comparison in the corresponding comparator. The signals U1, U2, D1, and D2are received by the FSM301. The signals U1, U2, D1, and D2, in combination, may provide an indication of the value of the voltage Vcm. For example, in a way, the signals U1, U2, D1, and D2are a four-bit digital value for the common mode voltage Vcm.

For example, during an offset training stage (e.g., prior to an operation of the transmitter100, during a start-up of the transmitter100, and/or at any periodic or aperiodic intervals), the offset correction logic504may tune one or more of the resistors502a,502b, . . . ,502ffor possible offset correction. For example, ideally, it may be intended that an average or steady state value of Vcm is equal to a value of the voltage at a node between the resistors502c,502d. This may correspond to a scenario where U2=1, U1=1, D1=1, D2=1. Thus, the offset correction logic504may tune one or more of the resistors502a,502b, . . . ,502f, until U2=1, U1=1, D1=1, D2=1. AlthoughFIG. 5illustrates tuning of the resistors502aand502f, any of the resistors502a,502b, . . . ,502fmay be tuned. In an example, during offset training stage, the transmitter100may not transmit any data.

In some embodiments, an AND logic gate516receives an early write enable signal512(e.g., from a transmission logic510, which is aware of when the transmitter100is to transmit data) and a clock514. An output of the AND gate516is used to clock the comparators504a,504b,504c,504d. The early write enable signal512may un-gate the comparators504a,504b,504c,504d, e.g., few, such as one or two, clock cycles prior to the transmitter100transmitting data (or when the transmitter100is to transmit data), or during the above discussed training stage. In an example, the frequency of the clock512may be similar to, or higher than a write clock, e.g., for generating reasonable sampling rate of voltage Vcm

In some embodiments, based on the value of the Vcm, individual ones of the signals U1, U2, D1, D2may take values of either 0 or 1. The following example scenarios are discussed:

Scenario (A): consider a scenario where U2=1, U1=0, D1=1, D2=1. This may be the case when VH2is higher than Vcm, Vcm is higher than VH1, VH1is higher than VL1, and VL1is higher than VL2(e.g., VL2<VL1<VH1<Vcm<VH2). Thus, Vcm is higher than it's expected, ideal, or average value. In some embodiments, for such a situation, a corresponding binary bit in control signal182may be deselected to reduce the bias143. If the same samples keep on coming, thermal bits in the control signal182may be deselected till U1flips to 1.

Scenario (B): consider a scenario where U2=0, U1=0, D1=1, D2=1. This may be the case when Vcm is higher than VH2, VH2is higher than VH1, VH1is higher than VL1, and VL1is higher than VL2(e.g., VL2<VL1<VH1<VH2<Vcm). Thus, Vcm is higher than it's expected, ideal, or average value. In some embodiments, for such a situation, a corresponding binary bit in control signal182may be deselected to reduce the bias143. The reduction of the bias in scenario (B) may be higher than the reduction of bias in scenario (A) (e.g., because the voltage Vcm in scenario (B) is higher than that is scenario (A)). If the same samples keep on coming, the thermal bits in the control signal may be deselected till U2flips to 1.

Scenario (C): consider a scenario where U2=1, U1=1, D1=0, D2=1. This may be the case when VH2is higher than VH1, VH1is higher than VL1, VL1is higher than Vcm, and Vcm is higher than VL2(e.g., VL2<Vcm<VL1<VH1<VH2). Thus, Vcm is lower than it's expected, ideal, or average value. In some embodiments, for such a situation, a corresponding binary bit in control signal182may be selected to increase the bias143. If the same samples keep on coming, the thermal bits in the control signal may be selected till D2flips to 0.

Scenario (D): consider a scenario where U2=1, U1=1, D1=0, D2=0. This may be the case when VH2is higher than VH1, VH1is higher than VL1, VL1is higher than VL2, and VL2is higher than Vcm (e.g., Vcm<VL2<VL1<VH1<VH2). Thus, Vcm is lower than it's expected, ideal, or average value. In some embodiments, for such a situation, a corresponding binary bit in control signal182may be selected to reduce the bias143. The bias reduction in scenario (D) may be higher than that in the scenario (C), e.g., because the voltage Vcm in scenario (D) is lower than that is scenario (C). If the same samples keep on coming, the thermal bits in the control signal may be deselected till D2flips to 1.

Scenario (E): consider a scenario where U2=1, U1=1, D1=1, D2=1. This may be the case when VH2is higher than VH1, VH1is higher than Vcm, Vcm is higher than VL1, and VL1is higher than VL2(e.g., VL2<VL1<Vcm<VH1<VH2). Thus, Vcm is at or near it's expected, ideal, or average value. In some embodiments, for such a situation (e.g., which may be an ideal situation where Vcm is within an ideal range), no corrective action may be taken by the FSM301to change the bias143, based on the output of the supply voltage tracking circuitry305.

Although U1, U2, D1, D2are used by the FSM301to control the bias143, the FSM301may consider other factors as well (e.g., based on receiving outputs from circuitries309, . . . ,321) to control the bias143. Thus, the FSM301considers the U1, U2, D1, D2, in combination with outputs from circuitries309, . . . ,321, while controlling the bias143.

In some embodiments, the circuitry305, higher order harmonics of resonant frequencies of the voltage Vcm may be filtered out. The samplers in the circuitry305may be designed with smaller clock and wider input common range. In order to mitigate the kick back noise due to sampler switching, the samples may be taken in the order of U1, D2, U2, followed by D1, which may provide settling time of Vcm and setting time of the comparison operations.

Thus, the FSM301may be able to maintain the bias143of the transmitter100at an appropriate level (e.g., which may result in higher quality data eye at the receiver and/or low timing losses), in spite of variations of various factors, e.g., variations in supply voltage Vcc, variation in temperature, process, aging of components, turning on or off of various components of the computing device, data density of data transmitted by the transmitter, etc.

FIG. 6illustrates a flowchart depicting a method600for tuning a bias generation circuitry (e.g., section102) of the transmitter100, according to some embodiments. Although the blocks in the flowchart with reference toFIG. 6are shown in a particular order, the order of the actions can be modified. Thus, the illustrated embodiments can be performed in a different order, and some actions/blocks may be performed in parallel. Some of the blocks and/or operations listed inFIG. 6may be optional in accordance with certain embodiments. The numbering of the blocks presented is for the sake of clarity and is not intended to prescribe an order of operations in which the various blocks must occur.

The method600starts at604. At608, one or more of the resistors502a,502b,503c,502d,502e, or502fare tuned, if necessary. For example, as discussed herein previously, during the offset training stage (e.g., prior to an operation of the transmitter100, during a start-up of the transmitter100, and/or at any periodic or aperiodic intervals), the offset correction logic504may tune one or more of the resistors502a,502b, . . . ,502ffor possible offset correction. For example, ideally, it may be intended that an average or steady state value of Vcm is equal to a value of the voltage at a node between the resistors502c,502d. This may correspond to a scenario where U2=1, U1=1, D1=1, D2=1. Thus, the offset correction logic504may tune one or more of the resistors502a, . . . ,502f, until U2=1, U1=1, D1=1, D2=1.

The method600then proceeds to612, where default value of the control signal182may be set. The default value of the control signal182may be set assuming, merely as an example, that the voltage Vcm is substantially at its steady state or ideal voltage range.

The method600then proceeds to616, where it may be checked whether the early write enable512is enabled. For example, as discussed herein previously with respect toFIG. 5, the early write enable signal512may un-gate the comparators504a,504b,504c,504d(e.g., few, such as one or two, clock cycles prior to the transmitter100transmitting data, or when the transmitter100is to transmit data), or during the above discussed training stage. If the early write enable512is not enabled, then the transmitter100is not to transmit data, and the method600continues checking.

If the early write enable512is enabled, then the transmitter100is to transmit data, and the method600proceeds to620. At620, the FSM301track signals U1, U2, D1, D2, receives input from circuitries309,313,317,321, and tunes the control signal182accordingly, e.g., to increase the bias143, decrease the bias143, or keep the bias143unchanged. For example, the FSM301tunes the control signal182in accordance with one of the above discussed scenarios (A), (B), (C), (D), or (E), discussed with respect toFIG. 5herein previously.

Subsequently, the method600loops back to one of blocks620,616, or608. For example, the method600may keep on tracking and tuning, and loop back to620. Alternatively, the method600may loop back to616, to check if the early write enable512is still enabled. Alternatively, if tuning of the resistors502a,502b, . . . ,502fis desired (e.g., at periodic or aperiodic intervals, at startup, if an error condition is encountered, etc.), the method600may loop back to608.

FIG. 7illustrates a computer system, a computing device or a SoC (System-on-Chip)2100, where the control circuitry180uses feedback control to tune generation of bias in the transmitter100, e.g., to reduce or mitigate timing losses in the transmitter100due to variations of one or more factors, according to some embodiments. It is pointed out that those elements ofFIG. 7having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

In some embodiments, computing device2100represents an appropriate computing device, such as a computing tablet, a mobile phone or smart-phone, a laptop, a desktop, an IOT device, a server, a set-top box, a wireless-enabled e-reader, or the like. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device2100.

In some embodiments, computing device2100includes a first processor2110. The various embodiments of the present disclosure may also comprise a network interface within2170such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant.

In one embodiment, processor2110can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. The processing operations performed by processor2110include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device2100to another device. The processing operations may also include operations related to audio I/O and/or display I/O.

In one embodiment, computing device2100includes audio subsystem2120, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device2100, or connected to the computing device2100. In one embodiment, a user interacts with the computing device2100by providing audio commands that are received and processed by processor2110.

Display subsystem2130represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device2100. Display subsystem2130includes display interface2132, which includes the particular screen or hardware device used to provide a display to a user. In one embodiment, display interface2132includes logic separate from processor2110to perform at least some processing related to the display. In one embodiment, display subsystem2130includes a touch screen (or touch pad) device that provides both output and input to a user.

I/O controller2140represents hardware devices and software components related to interaction with a user. I/O controller2140is operable to manage hardware that is part of audio subsystem2120and/or display subsystem2130. Additionally, I/O controller2140illustrates a connection point for additional devices that connect to computing device2100through which a user might interact with the system. For example, devices that can be attached to the computing device2100might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.

As mentioned above, I/O controller2140can interact with audio subsystem2120and/or display subsystem2130. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device2100. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem2130includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller2140. There can also be additional buttons or switches on the computing device2100to provide I/O functions managed by I/O controller2140.

Connectivity2170includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device2100to communicate with external devices. The computing device2100could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.

Connectivity2170can include multiple different types of connectivity. To generalize, the computing device2100is illustrated with cellular connectivity2172and wireless connectivity2174. Cellular connectivity2172refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface)2174refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication.

Peripheral connections2180include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device2100could both be a peripheral device (“to”2182) to other computing devices, as well as have peripheral devices (“from”2184) connected to it. The computing device2100commonly has a “docking” connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device2100. Additionally, a docking connector can allow computing device2100to connect to certain peripherals that allow the computing device2100to control content output, for example, to audiovisual or other systems.

In some embodiments, the computing device2100may comprise the transmitter100ofFIGS. 1-5, and the control circuitry180. The control circuitry180may generate the control signal182, e.g., to tune the bias generation of the transmitter100. The transmitter100may be used for any appropriate transmission functionality of the computing device2100, e.g., to transmit data to or from a memory of the memory subsystem2160, or to transmit data to or from another appropriate component of the computing device100.

The following example clauses pertain to further embodiments. Specifics in the example clauses may be used anywhere in one or more embodiments. All optional features of the apparatus described herein may also be implemented with respect to a method or process.

An apparatus comprising: a transmitter comprising a first stage and a second stage, wherein the first stage is to receive an input voltage and generate bias for the second stage, and wherein the second stage comprises a driver circuitry to transmit data using the bias; and a control circuitry to control generation of the bias, based on a feedback of the input voltage.

The apparatus of example 1 or any other example, wherein the control circuitry comprises: a first circuitry to track the input voltage; and a second circuitry to control generation of the bias, based on tracking information from the first circuitry.

The apparatus of example 1 or any other example, wherein the control circuitry comprises: a first circuitry to track variation of one or more parameters of the apparatus, based on aging of the apparatus; and a second circuitry to control generation of the bias, based on information on the variation of the one or more parameters of the apparatus from the first circuitry.

The apparatus of example 1 or any other example, wherein the control circuitry comprises: a first circuitry to track of power demand of one or more components of the apparatus; and a second circuitry to control generation of the bias, based on information on the power demand of the one or more components of the apparatus from the first circuitry.

The apparatus of example 1 or any other example, wherein the control circuitry comprises: a first circuitry to monitor one or both of a voltage or a temperature of the apparatus; and a second circuitry to control generation of the bias, based on information on one or both of the voltage or the temperature of the apparatus from the second circuitry.

The apparatus of example 1 or any other example, wherein the control circuitry comprises: a circuitry to: receive information on a data density of data to be transmitted by the transmitter, and control generation of the bias, based on the data density of data to be transmitted by the transmitter.

The apparatus of example 1 or any other example, wherein the first stage comprises: a buffer including a current mirror, wherein the current mirror is to output the bias in a form of a bias current, wherein to control generation of the bias, the control circuitry is to control the current mirror.

The apparatus of example 7 or any other example, wherein the first stage comprises: a bias ladder to receive a supply voltage, and generate the input voltage; a comparator to compare the input voltage with a reference voltage, and generate a first current; and the current mirror to receive the first current at a first transistor, and to output the bias current at a second transistor, wherein to control generation of the bias, the control circuitry is to control the second transistor.

The apparatus of example 1 or any other example, wherein the control circuitry comprises: first, second, third, fourth, fifth, and sixth resistors coupled in series between a regulated voltage and ground terminal; a first comparator to receive: an input from a node between the first and second resistors, and the input voltage; a second comparator to receive: an input from a node between the second and third resistors, and the input voltage; a third comparator to receive: an input from a node between the fourth and fifth resistors, and the input voltage; a fourth comparator to receive: an input from a node between the fifth and sixth resistors, and the input voltage; and a Finite State Machine (FSM) to receive: a first comparator output from the first comparator, a second comparator output from the second comparator, a third comparator output from the third comparator, and a fourth comparator output from the fourth comparator.

The apparatus of example 9 or any other example, wherein the FSM is to control generation of the bias, based on receiving the first, second, third, and fourth comparator outputs.

The apparatus of example 9 or any other example, wherein the first, second, third, and fourth comparators are to be enabled while the transmitter is to transmit data.

The apparatus of example 9 or any other example, wherein the FSM is to one of: increase the bias, decrease the bias, or keep the bias unchanged, based on the first, second, third, and fourth comparator outputs.

A system comprising: a memory to store instructions; a processor coupled to the memory, the processor to execute the instructions; a wireless interface to facilitate communication between the processor and another system; a transmitter to transmit data to the memory, wherein the transmitter comprises: a driver circuitry to transmit the data to the memory, and a bias generation circuitry to receive an input voltage, and generate a bias current for the driver circuitry; and a bias control circuitry to control the bias current, to compensate for variations of one or more factors, wherein the one or more factors includes one or more of: the input voltage, temperature of one or more components of the apparatus, or the data density.

The system of example 13 or any other example, wherein the bias generation circuitry comprises a current mirror that is to receive an input current and generate the bias current, and wherein the input current is generated based on the input voltage.

The system of example 14 or any other example, wherein to control the bias current, the bias control circuitry is to control the current mirror.

The system of example 13 or any other example, wherein the one or more factors include one or more of: a degradation of the bias generation circuitry due to aging, a power demand of one or more components of the apparatus, or a noise in the input voltage.

The system of example 13 or any other example, wherein: the driver circuitry is a first driver circuitry; the transmitter comprises a plurality of driver circuitries, including the first driver circuitry; and the bias generation circuitry is to generate the bias current for the plurality of driver circuitries.

An apparatus comprising: a bias generation circuitry to receive an input voltage and generate a bias current; a driver circuitry is to receive the bias current, and to transmit or receive data based on being biased by the bias current; and a control circuitry to track the input voltage, and control generation of the bias current.

The apparatus of example 18 or any other example, wherein the control circuitry comprises: a supply tacking circuitry that is to receive the input voltage, and to generate a digital output indicative of the input voltage; and a finite state machine to receive the digital output indicative of the input voltage, and to generate a control signal that is to one of: increase the bias current, decrease the bias current, or retain the value of the bias current, based on the digital output.

The apparatus of example 18 or any other example, wherein the bias generation circuitry comprises a current mirror, and wherein the control circuitry is to control the current mirror to control generation of the bias current.