Semiconductor memory device and computer system including the same

A semiconductor memory device includes a first memory block of a first type of memory; and a second memory block of a second type of memory having a different type from the first type. A first address region of the first memory block and a second address region of the second memory block are included in the same address domain. Each of the first and second memory blocks is accessed by an address signal including an address of the address domain, and the second memory block is a nonvolatile memory.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2012-0131980 filed on Nov. 20, 2012, the disclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND

A computer system may typically be formed including a plurality of memories arranged in various hierarchical structures. The highest level memories feature the highest performance, the highest price and the lowest capacity, while the lowest level memories have the reverse characteristics to the highest level memories. The highest level memories correspond to a register, a cache, an SRAM, etc., and the lowest level memories correspond to a hard disk drive (HDD), an optical disk drive (ODD), etc.

As a central processing unit (CPU) is generally configured in pipeline architecture, managing such hierarchical memories with efficiency is thus regarded as important in determining the performance of a computer system.

SUMMARY

Exemplary embodiments are directed to provide a semiconductor memory device with different memories which are fabricated in a unitary die and controlled by address signals.

The embodiments are further directed to provide a computer system including such a semiconductor memory device.

In accordance with one embodiment, a semiconductor memory device may include a first memory block of a first type of memory and a second memory block of a second type of memory that is different from the first type. A first address region of the first memory block and a second address region of the second memory block may be included in the same address domain. Each of the first and second memory block may be accessed by an address signal including an address of the address domain. The second memory block may be a nonvolatile memory.

The same address domain may refer to a set of consecutive addresses, wherein the addresses of the second address region immediately follow the addresses of the first address region.

The first and second memory block may be each driven by different AC parameters.

The first and second memory block may be fabricated in a unitary die.

The first and second memory block may be each made by different memory fabrication processes.

The first memory block may be used as a system operating memory.

The first memory block may include a volatile memory, such as DRAM.

The second memory block may be used for storing data.

The nonvolatile memory may include one of a flash memory device, Ferroelectric Random Access Memory (FeRAM), Phase-change Random Access Memory (PRAM), and Magnetic Random Access Memory (MRAM).

In accordance with another embodiment, a computer system may include a semiconductor memory device having a first memory block and a second memory block that has different operational characteristics from the first memory block, a memory controller configured to access the first and second memory block by an address signal, and a central processing unit configured to, by way of the memory controller, allocate a memory space to the first memory for system management and a memory space to the second memory block for data storage.

An address region of the semiconductor memory device may include a first address region for accessing the first memory and a second address region for accessing the second memory.

The first and second memory block may be each driven by different AC parameters.

The first and second memory block are fabricated in a unitary die.

The first and second memory block may be each made by different memory fabrication processes.

The second memory block may be a nonvolatile memory.

The nonvolatile memory may include one of a flash memory device, Ferroelectric Random Access Memory (FeRAM), Phase-change Random Access Memory (PRAM), and Magnetic Random Access Memory (MRAM).

In another embodiment, a memory access method in a semiconductor memory device that includes a first memory block of a first type of memory on a die and a second memory block of a second type of memory having a different type from the first type on the same die is disclosed. The memory access method includes accessing a first address region of the first memory block by a first address signal including a first address, and accessing a second address region of the second memory block by a second address signal including a second address. The first address and second address may be part of the same address domain, and the second memory block may be a nonvolatile memory.

The first memory block may be a volatile memory.

The same address domain may include a set of consecutive addresses, wherein the addresses of the second address region immediately follow the addresses of the first address region.

The first memory block may be used as memory space for managing a computer system, and the second memory block may be used as memory space for storing data.

In one embodiment, first AC parameters are applied to the first address region, and second AC parameters are applied to the second address region. The second AC parameters are different from the first AC parameters.

DETAILED DESCRIPTION

Embodiments are described below in sufficient detail to enable those of ordinary skill in the art to embody and practice the inventive concept. It is important to understand that the inventive concept may be embodied in many alternate forms and should not be construed as limited to the embodiments set forth herein.

Accordingly, while the inventive concept is susceptible to various modifications and may take on various alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail.

The disclosure will now be described more fully with reference to the accompanying drawings, in which embodiments of the inventive concept are shown.

Disclosed embodiments relate to a semiconductor memory device, and more particularly, to a semiconductor memory device including different memories and accessing the memories by address signals and a computer system including the semiconductor memory device.

FIG. 1is a block diagram illustrating a semiconductor memory device100according to one exemplary embodiment.

Referring toFIG. 1, the semiconductor memory device100includes a first memory block110and a second memory block120. In one embodiment, the semiconductor memory device100includes different kinds of memories. For example, if the first memory block110is volatile like a dynamic random access memory (DRAM), the second memory block120may be nonvolatile. The second memory block120may include, for example, a Ferroelectric Random Access Memory (FeRAM), a Phase-change Random Access Memory (PRAM), a Magnetic Random Access Memory (MRAM), a flash memory device, etc.

The semiconductor memory device100may be formed including the different kinds of the first and second memory blocks110and120which are integrated in a unitary die. Therefore, the first and second memory blocks110and120can be on the same chip. Accordingly, different memory fabrication processes may be used in order to fabricate the first and second memory blocks110and120, which are different in kind, or type, in a unitary die. For example, if the first memory block110is a DRAM, a high integration DRAM process may be used to fabricate the first memory block110. As also, if the second memory block120is a flash memory, an embedded flash memory process may be used to fabricate the second memory block120.

The first and second memory devices110and120may be controlled by way of address signals. For example, in one embodiment, a first address region, also described as a range, AR1of the first memory block110is set as 0000′h to 1FFF′h (hexadecimal code). A second address region, also described as a range, AR2of the second memory block120is set as 2000′h to FFFF′h.

Depending on which address regions an address signal belongs to, the semiconductor memory device100may determine a memory block to be accessed (e.g., depending on which address region the address signal belongs to, the memory block to be accessed in the semiconductor memory device100may vary.) In one embodiment, the first address region AR1and the second address region AR2are included in the same address domain.

FIG. 2is a block diagram illustrating an exemplary semiconductor memory device100ofFIG. 1that is implemented as a DRAM100.

Referring toFIG. 1andFIG. 2, the first memory block110is implemented as the DRAM cell region110and the second memory block120is implemented as an OTP cell region120.

The DRAM100includes the DRAM cell region110and the OTP cell region120. The DRAM cell region110and the OTP cell region are each controlled by the same address domain. For example, in one embodiment, the first address region AR1of the DRAM cell region110is ranged from 0000′h to 0FFF′h. The second address region AR2of the OTP cell region120is ranged from 1000′h to 100F′h. Accordingly, the address domain may be set from 0000′h to 100F′h.

While the OTP cell region120is typically programmed during a fabrication process, the DRAM100according to an exemplary embodiment is programmed after the fabrication process.

FIGS. 3A and 3Bare block diagrams illustrating an exemplary semiconductor memory device100ofFIG. 2and a memory controller200.

FIG. 3Adepicts that the memory controller200sets a start address10and a offset20for the OTP cell region120, andFIG. 3Bdepicts that the memory controller200receives the start address10and the offset20from the OTP cell region120.

Referring toFIG. 2andFIG. 3A, the memory controller200includes the start address10and the offset20for accessing the OTP cell region120. The start address10is the first address of the OTP cell region120. The offset20is a difference between the start address10and the last address of the OTP cell region120. Namely, as shown inFIG. 2, the start address10at the OTP cell region120is 1000′h and the offset20at the OTP cell region120is F′h (i.e. ‘16’ in decimal code).

The memory controller200stores the start address10and the offset20in the OTP cell region120. The memory controller200can use a Mode Register Set (MRS) in order to transfer the start address10and the offset20to the OTP cell region120.

Generally, in the DRAM, an operation mode to be exploited by the memory controller200, which is calibrated by CAS (column address strobe) latency, a burst length, etc., is set in advance. And then, the DRAM may be accessed.

A exemplary place for setting and storing such an operation mode is a mode register. And the congregation of mode registers is called a mode register set (hereinafter referred to as “MRS”).

Referring toFIG. 2andFIG. 3B, the memory controller200is initialized after storing the start address10and the offset20in the OTP cell region120, or receives the start address10and the offset20from the OTP cell region120after power-off. The memory controller200can access the OTP cell region120by way of the start address10and the offset20.

An exemplary procedure for driving the memory controller200ofFIGS. 3A and 3Bwill be described with reference toFIG. 4throughFIG. 6in detail. And an exemplary procedure for setting an address at the OTP cell region120by the memory controller200will be detailed with reference toFIG. 4.

Additionally, a procedure for writing data into the OTP cell region120after the memory controller200sets an address to the OTP cell region120will be described in conjunction withFIG. 5. And a procedure for reading the OTP cell region120will be described referring toFIG. 6.

FIG. 4is a flowchart illustrating the procedure for setting an address to the OTP cell region120ofFIGS. 3A and 3B.

Referring first toFIG. 2throughFIG. 3A, a programmer (i.e. a user) accessing the OTP cell region120determines a start address and an offset of the OTP cell region120. Then the user (i.e., the programmer) stores the start address10and the offset20, which are to be used for accessing the OTP cell region120, in the memory controller200.

In step S11, the memory controller200transfers the start address10and the offset20, which are to be used for accessing the OTP cell region120, to the OTP cell region120. For example, the memory controller200transfers 1000′h as the start address10and F′h as the offset20.

In step S12, the OTP cell region120continually keeps the start address10and the offset20even during the power-off or an initializing step.

FIG. 5is a flowchart showing an exemplary procedure for writing data into the OTP cell region120ofFIGS. 3A and 3B.

Referring toFIG. 2,FIG. 3A,FIG. 3BandFIG. 5, the memory controller200usually applies normally operating AC parameters to the DRAM cell region110in order to access the DRAM cell region110.

Since the OTP cell region is different from the DRAM cell region in operation rate, the AC parameters are differently applied to the OTP cell region120, which may be called OTP operative AC parameters, dissimilar to the DRAM cell region110.

In step S21, the memory controller200applies the OTP operative AC parameters to the OTP cell region120in order to write data into the OTP cell region120.

In step S22, the memory controller200writes data into the OTP cell region120.

FIG. 6is a flowchart showing an exemplary procedure for reading data from the OTP cell region120ofFIGS. 3A and 3B.

Referring toFIG. 2,FIG. 3A,FIG. 3BandFIG. 6, in step S31, the memory controller200applies the OTP operative AC parameters to the OTP cell region120in order to read data from the OTP cell region120.

In step S32, the memory controller200receives data from the OTP cell region120.

FIG. 7is a block diagram illustrating an exemplary computer system1000with the semiconductor memory device100ofFIG. 2.

Referring toFIG. 2throughFIG. 7, the computer system1000includes the semiconductor memory device100ofFIG. 2, the memory controller200, a central processing unit300and a system bus400.

In one embodiment, the central processing unit300directly allocates a memory space (region) of the semiconductor memory device100by way of the memory controller200.

For example, the central processing unit300can allocate the first memory block110as a memory space for managing the computer system1000, and the second memory block120as a memory space for storing data. A computer system is generally complicated in a hierarchical memory structure and also has complex access layers for controlling the memories. However, the semiconductor memory device100according to various disclosed embodiments is configured to include different kinds of memories in a unitary die. Moreover, such different memories are assigned to the same memory domain. Thus, the computer system1000according to exemplary embodiments may have a simpler hierarchical memory structure. Therefore, the computer system1000can be accessed more easily.

FIG. 8is a flowchart showing an exemplary writing operation in the computer system1000ofFIG. 7.

Referring toFIG. 7andFIG. 8, first, the central processing unit300allocates the first memory block110as a memory space for managing the computer system1000, and the second memory block120as a memory space for storing data.

In step S41, the central processing unit300selects an address for storing data. If the data is to be used for operating the computer system, the data may be stored in the first address region AR1. If not, the data may be stored in the second address region AR2.

In step S42, if the selected address belongs to the first address region AR1, steps S43and S44are performed. If not, steps S45and S46steps are performed.

In step S43, the memory controller200transfers the data to the first memory block110in response to the operative AC parameters of the first memory block110.

In step S44, the first memory block110stores the data and the procedure terminates.

In step S45, the memory controller200transfers the data to the second memory block120in response to the operative AC parameters of the second memory block120.

In step S46, the second block120stores the data and the procedure terminates.

FIG. 9is a flowchart showing an exemplary reading operation in the computer system1000ofFIG. 7.

Referring toFIG. 7andFIG. 9, first, the central processing unit300allocates the first memory block110as a memory space for managing the computer system1000and the second memory block120as a memory space for storing data.

In step S51, the central processing unit300selects an address for reading data.

In step S52, if the selected address is the first address region AR1, step S53is performed. If not, step S54is performed.

In step S53, the first memory block110transfers the data, which accords to the selected address, to the memory controller200and the procedure terminates.

In step S54, the second memory block120transfers the data, which accords to the selected address, to the memory controller200and the procedure terminates.

FIG. 10is a block diagram illustrating an exemplary memory system2000with the semiconductor memory device100ofFIG. 1.

Referring toFIG. 10, the memory system2000includes a memory module2010having the semiconductor memory device100ofFIG. 1, and a memory controller2020controlling the memory module2010.

The memory module2010may be implemented to include more members in addition to the semiconductor memory devices100illustrated herein. And, the four semiconductor memory devices100attached to the memory module2010may be mounted on both surfaces of a substrate of the memory module2010.

The memory controller2020generates a command/address signal C/A and a data signal DQ. The memory module2010operates in response to the command/address signal C/A and the data signal DQ. The command/address signal C/A may be packet data in which a command signal is combined with an address signal in a packet type.

The memory system2000may further include a command/address bus2030and a data bus2040.

The command/address bus2030is configured in a fly-by structure and electrically connects the four semiconductor memory devices100with each other. The data signal DQ may be transferred between the memory controller2020and the memory module2010through the data bus2040.

FIGS. 11 through 13are diagrams illustrating memory modules2100to2300, each of which include the semiconductor memory devices100ofFIG. 1.

Referring toFIG. 11, the memory module2100includes the plurality of semiconductor memory devices100, a printed circuit board (PCB)2110, and a connector2120. The plurality of semiconductor memory devices100may be each bonded to the top and bottom surfaces of the PCB2110. The connector2120is electrically connected to the plurality of semiconductor memory devices100through conductive wires (not shown). The connector2120may be also coupled to a slot of an external host.

Referring toFIG. 12, the memory module2200includes the plurality of semiconductor memory devices100, a PCB2210, a connector2230, and a plurality of buffers2230. Each of the plurality of buffers2230may be disposed between the corresponding one of the semiconductor memory devices100and the connector2220.

The plurality of buffers2230connected each to the plurality of semiconductor memory devices100respectively may be provided on the top and bottom surfaces of the PCB2210. The semiconductor memory devices100and the plurality of buffers2230formed on the top and bottom surfaces of the PCB2210may be connected through a plurality of via holes, respectively.

Referring toFIG. 13, the memory module2300includes the plurality of semiconductor devices100, a PCB2310, a connector2320, a plurality of buffers2330, and a controller2340.

The plurality of buffers2330connected each to the plurality of semiconductor memory devices100may be provided on the top and bottom surfaces of the PCB2310. The plurality of semiconductor memory devices100and the plurality of buffers2340formed on the top and bottom surfaces of the PCB2310may be connected through a plurality of via holes, respectively. The controller2340transfers a control signal to the plurality of semiconductor memory devices100, and transceives data to and from the semiconductor memory devices100.

FIG. 14is a schematic diagram illustrating an exemplary stacked semiconductor device3000equipped with a plurality of semiconductor layers. In the module structures ofFIGS. 11 through 13, each of the semiconductor memory devices100may include a plurality of semiconductor layers LA1to LAn.

Referring toFIG. 14, in the stacked semiconductor device3000, the plurality of stacked semiconductor layers LA1to LAn may be interconnected with each other by way of through substrate vias, such as through silicon vias (TSVs)3010.

FIG. 15illustrates an exemplary embodiment relative to a computer system4100including the semiconductor memory device100ofFIG. 1.

Referring toFIG. 15, the computer system4100includes a semiconductor memory device100, a memory controller4110controlling the semiconductor memory device100, a wireless transceiver4120, an antenna4130, an application processor4140, an input device4150, and a display device4160.

The wireless transceiver4120may receive and transmit a wireless signal through the antenna4130. For example, the wireless transceiver4120may modulate a wireless signal, which is received through the antenna4130, into a signal that can be processed in the application processor4140.

Accordingly, the application processor4140may process a signal, which is output from the wireless transceiver4120, and transfer the processed signal to the display device4160. The wireless transceiver4120may modulate the signal, which is output from the application processor4140, into a wireless signal, and output the modulated wireless signal to an external device (e.g. a host) through the antenna4130.

The input device4150is used as a device capable of inputting control signals for controlling an operation of the application processor4140or data to be processed by the application processor4140, and may be implemented in a keypad, a keyboard, or a pointing device such as touch pad or a computer mouse.

According to an embodiment, the memory controller4110capable of controlling an operation of the semiconductor memory device100may be implemented as a part of the application processor4140or as another chip in addition to the application processor4140.

FIG. 16illustrates another exemplary embodiment of a computer system4200including the semiconductor memory device100ofFIG. 1.

Referring toFIG. 16, the computer system4200may be implemented in a personal computer (PC), a network server, a tablet PC, a net-book, an e-reader, personal digital assistant (PDA), a portable multimedia player (PMP), an MP3 player, an MP4 player, for example.

The computer system4200includes a semiconductor memory device100, a memory controller4210to control a data processing operation of the semiconductor memory device100, a central processing unit4220, a input device4230, and a display device4240.

The central processing unit4220may output data from the semiconductor memory device100through the display device4240. For example, the input device4230may be implemented in a keypad, a keyboard, or a pointing device such as a touch pad or a computer mouse. The central processing unit4220can control an overall operation of the computer system4200and an operation of the memory controller4210.

According to an embodiment, the memory controller4210capable of controlling an operation of the semiconductor memory device100may be implemented as a part of the central processing unit4220or as another chip in addition to the central processing unit4220.

FIG. 17illustrates still another exemplary embodiment of a computer system4300including the semiconductor memory device100ofFIG. 1.

Referring toFIG. 17, the computer system4300may be implemented in an image process device such as a digital camera, a mobile telephone equipped with a digital camera, a smart phone or a tablet PC.

The computer system4300includes a semiconductor memory device100, and a memory controller4310capable of controlling a data processing operation of the semiconductor memory device100. And the computer system4300further includes a central processing unit4320, an image sensor4330, and a display device4340.

The image sensor4330converts an optical image into a digital signal and transfer the converted digital signal to the central processing unit4320or the memory controller4310. Under control by the central processing unit4320, the converted digital signal may be displayed through the display device4340or stored in the semiconductor memory device100by the memory controller4310.

Data stored in the semiconductor memory device100may be outputted by way of the display device4340in response to the control by the central processing unit4320or the memory controller4310.

According to an embodiment, the memory controller4210capable of controlling an operation of the semiconductor memory device100may be implemented as a part of the central processing unit4320or as another chip in addition to the central processing unit4320.

As stated above, a computer system according to the disclosed embodiments is provided to include a semiconductor memory device having a first memory block and a second memory block that is different from the first memory, a memory controller accessing the first and second memory blocks respectively by address signals, and a central processing unit allocating a memory space to the first memory for system management and a memory space to the second memory block for data storage. Therefore the computer system is more facilitated in accessing the semiconductor memory device by way of address signals.