A configurable NAND/NOR logic element is used, in an exemplary embodiment, in an array of spare gates included in a processor or other integrated circuit. The NAND/NOR logic element (FIG. 3, 50) is configurable as either a NAND or a NOR gate by a C (configuration) input (that can be metal configurable as either asserted or deasserted). C inputs control p- and n-channel transistors. Depending on whether the C input is deasserted or asserted, respective internal nodes are shorted to effect the selected configuration. Specifically, deasserting C provides the NAND configuration, while asserting C provides the NOR configuration. In an alternative embodiment, the NAND/NOR logic element can be used in a full adder to provide the carry output.

CROSS REFERENCE TO RELATED APPLICATIONS 
This is related to a commonly assigned co-pending U.S. patent application 
Ser. No. 08/497,007, titled "Configurable XNOR/XOR Element", filed Jun. 
30, 1995. 
BACKGROUND 
1. Technical Field 
The invention relates generally to digital circuits, and more particularly 
relates to programmable/configurable logic arrays. In even greater 
particularity, the invention relates to NAND and NOR gates. 
In an exemplary embodiment, the invention is used in spare gate arrays of a 
processor to enable logic elements to be formed through metal 
interconnection only (i.e., without affecting transistor fabrication). 
2. Related Art 
Logic elements commonly used in the design of digital circuits in general, 
and processors in particular, include NAND, NOR, XNOR, XOR, and Inverter 
gates. In CMOS designs, these logic gates are fabricated from p- and 
n-channel transistors interconnected with metal lines. 
Without limiting the scope of the invention, this background information is 
provided in the context of a specific problem to which the invention has 
application: in a processor design, maximizing the flexibility of using 
spare gates for correcting design errors through changes in the 
interconnection of logic elements. 
Processors are fabricated from silicon wafers in a series of process steps 
that can be separated into (a) a base set of process steps that form 
transistors in the silicon substrate, and (b) a number of metal layers or 
levels (typically 2-4) that form metal interconnect lines. Approximately 
75% of the total fabrication time is devoted to the base set. 
Complex integrated circuits such as processors commonly include arrays of 
spare gates (NAND, NOR, Inverter, etc.) that can be used in fixing 
function and timing errors using only metal interconnections to and among 
a selected number of spare gates. Using this debugging approach, the base 
set transistors do not change--only the metal layers (of course, some 
functional errors can only be corrected by also changing the base set 
transistors). 
For example, a number of wafers can be started and held after base set 
fabrication is complete, with only a few risk wafers being fabricated to 
completion. Parts assembled from the risk wafers can then be tested and, 
if possible, fixes for functional and timing errors can be identified that 
involve only the use of spare gates interconnected to the affected logic 
circuits. Once these fixes are identified, one or more new metal masks can 
be made, and used in completing fabrication of the wafers held at the 
metal stage of the process. 
To facilitate the spare gate approach to debugging processors or other 
complex integrated circuits, it would be advantageous to maximize the 
flexibility of the design of spare gate arrays. 
SUMMARY 
An object of the invention is an improved design for logic elements used in 
fabricating logic gates. A more specific object of the invention is to 
maximize flexibility in the design of spare gate arrays, such as for use 
in making fixes to integrated circuits through metal interconnection of 
spare gates only. 
This and other objects of the invention is achieved by a configurable 
NAND/NOR logic element which receives A and B inputs and provides a Y 
output. The NAND/NOR logic element is configurable as either a NAND or a 
NOR gate by a C (configuration) input. 
In one aspect of the invention, the NAND/NOR logic element includes first 
and second p-channel transistor stacks (series coupled transistors), 
respectively coupled in series to third and fourth n-channel transistor 
stacks. The first transistor stack is formed by a B-input p-transistor in 
series with an A-input p-transistor, defining a first internal node. The 
second transistor stack is formed by an A-input p-transistor in series 
with a B-input p-transistor, defining a second internal node. The third 
transistor stack is formed by an A-input n-transistor in series with a 
B-input n-transistor, defining a third internal node. The fourth 
transistor stack is formed by a B-input n-transistor in series with an 
A-input n-transistor, defining a fourth internal node. 
The first transistor stack and the third transistor stack are coupled in 
series to define a first output node, and the second transistor stack and 
the fourth transistor stack are coupled in series to define a second 
output node. The first and second output nodes being coupled to provide 
the Y output. 
The NAND/NOR logic element includes two configuration transistors. A 
configuration p-transistor is coupled between the first and second 
internal nodes, and a configuration n-transistor is coupled between the 
third and fourth internal nodes. 
The configuration p- and n-transistors are gated by the C input. If the C 
input is deasserted, the configuration p-transistor shorts the first and 
second internal nodes, and configuring the NAND/NOR logic element as a 
NAND gate with a corresponding Y output. If the C input is asserted, the 
configuration n-transistor shorts the third and fourth internal nodes, and 
configuring the NAND/NOR logic element as a NOR gate with a corresponding 
Y output. 
In an exemplary embodiment, the NAND/NOR logic element is used in an array 
of spare gates included in a processor or other integrated circuit. The 
NAND/NOR logic element is metal configurable as either a NAND gate or a 
NOR gate by configuring the C input as either deasserted or asserted (such 
as by tying the input to ground or to VDD). 
In an alternative embodiment, the NAND/NOR logic element can be used in a 
full adder to provide the carry output. In particular, the full adder can 
be formed by a combination of the NAND/NOR logic element with an XNOR/XOR 
logic element which provides the sum output. 
Embodiments of the invention may be implemented to realize one or more of 
the following technical advantages. The NAND/NOR and XNOR/XOR logic 
elements are configurable respectively as NAND/NOR gates or as XNOR/XOR 
gates, such as by metal interconnection of the C (configuration) input. 
Such configurable logic elements can be used, as examples, to maximize 
flexibility in the design of spare gate arrays, such as for use in making 
fixes to integrated circuits through metal interconnection of spare gates 
only, or in programmable logic arrays. The NAND/NOR logic element uses one 
level of logic, while the XNOR/XOR logic element uses two levels of logic. 
One alternative embodiment of these logic elements is to form a full adder 
from a combination of one NAND/NOR and one XNOR/XOR logic element. 
For a more complete understanding of the invention, and for further 
features and advantages, reference is now made to the Detailed Description 
of an exemplary embodiment of the invention, together with the 
accompanying Drawings, it being understood that the invention encompasses 
any modifications or alternative embodiments that fall within the scope of 
the claims.

DETAILED DESCRIPTION 
The detailed description of an exemplary embodiment of the configurable 
NAND/NOR and XNOR/XOR logic element is organized as follows: 
1. Conventional Logic Elements 
1.1. NAND/NOR 
1.2. XNOR/XOR 
2. NAND/NOR Logic Element 
3. XNOR/XOR Logic Element 
4. Full Adder 
5. Conclusion 
This organizational outline, and the corresponding headings, are used in 
this Detailed Description for convenience of reference only. 
The exemplary NAND/NOR and XNOR/XOR logic elements is used in an in spare 
gate arrays of a processor or other complex integrated circuit to enable 
logic elements to be formed through metal interconnection only (i.e., 
without affecting the base set transistor fabrication). 
Detailed descriptions of conventional or known aspects of logic element 
design are omitted so as to not obscure the description of the invention. 
In the context of this Detailed Description of the exemplary embodiment, p- 
and n-transistors are respectively p-channel and n-channel CMOS 
transistors (p-channel transistors are active low). 
When used with a signal, the # symbol designates a signal that is active 
low, while the / symbol designates the complement (inverse) of a signal. 
1. Conventional Logic Elements 
Conventional CMOS NAND, NOR, XNOR, and XOR gates are formed by 
interconnections of parallel and stacked (series) p- and n-channel 
transistors. NAND and NOR gates receive A and B inputs and provide a Y 
output--they require one level of logic. XNOR and XOR gates receive 
inverted and noninverted A and B inputs, and provide a Y output--because 
of input signal inversion, they require two levels of logic. 
1.1. NAND/NOR 
FIGS. 1a and 1b respectively illustrate conventional CMOS NAND and NOR 
gates. 
Referring to FIG. 1a, a NAND gate 10 is formed by parallel p-transistors 
12, and stacked (series) n-transistors 14. The parallel and stacked 
transistors are coupled together at output nodes 13a and 13b, which form 
the Y output of the NAND gate. 
Parallel p-transistors 12a and 12b are coupled to VDD, and respectively 
receive the A and B inputs. Stacked n-transistors 14a and 14b respectively 
receive the A and B inputs. 
The truth table for the NAND gate is: 
______________________________________ 
A B Y 
______________________________________ 
0 0 1 
0 1 1 
1 0 1 
1 1 0 
______________________________________ 
Referring to FIG. 1b, a NOR gate 20 is formed by stacked p-transistors 22, 
and parallel n-transistors 24. The stacked and parallel transistors are 
coupled together at output nodes 23a and 23b, which form the Y output of 
the NOR gate. 
Stacked p-transistors 12a and 12b respectively receive the A and B inputs, 
with p-transistor 12b being coupled to VDD. Parallel n-transistors 14a and 
14b respectively receive the A and B inputs. 
The truth table for the NOR gate is: 
______________________________________ 
A B Y 
______________________________________ 
0 0 1 
0 1 0 
1 0 0 
1 1 0 
______________________________________ 
1.2. XNOR/XOR 
FIGS. 2a and 2b respectively illustrate conventional CMOS XNOR and XOR 
gates. 
Referring to FIG. 2a, an XNOR gate 30 is formed by parallel stacked 
p-transistors 31 and 32, and parallel stacked n-transistors 34 and 35. The 
parallel stacked p- and n-transistors are coupled together at output nodes 
33a and 33b, which provide the Y output of the XNOR gate. 
Stacked p-transistors 31a and 31b respectively receive noninverted A and 
noninverted B inputs, with p-transistor 31a being coupled to VDD. Stacked 
p-transistors 32a and 32b respectively receive inverted A and inverted B 
inputs, with p-transistor 32a being coupled to VDD. 
Stacked n-transistors 34a and 34b respectively receive inverted A and 
noninverted B inputs. Stacked n-transistors 35a and 35b respectively 
receive noninverted A and inverted B inputs. 
The truth table for the XNOR gate is: 
______________________________________ 
A B Y 
______________________________________ 
0 0 1 
0 1 0 
1 0 0 
1 1 1 
______________________________________ 
Referring to FIG. 2b, an XOR gate 40 is formed by parallel stacked 
p-transistors 41 and 42, and parallel stacked n-transistors 44 and 45. The 
parallel stacked p- and n-transistors are coupled together at output nodes 
43a and 43b, which provide the Y output of the XOR gate. 
Stacked p-transistors 31a and 31b respectively receive noninverted A and 
inverted B inputs, with p-transistor 31b being coupled to VDD. Stacked 
p-transistors 32a and 32b respectively receive inverted A and noninverted 
B inputs, with p-transistor 32a being coupled to VDD. 
Stacked n-transistors 34a and 34b respectively receive inverted A and 
inverted B inputs. Stacked n-transistors 35a and 35b respectively receive 
noninverted A and noninverted B inputs. 
The truth table for the XOR gate is: 
______________________________________ 
A B Y 
______________________________________ 
0 0 0 
0 1 1 
1 0 1 
1 1 0 
______________________________________ 
2. NAND/NOR Logic Element 
FIG. 3 illustrates a configurable NAND/NOR logic element 50 in accordance 
with one aspect of the invention. The configurable NAND/NOR logic element 
receives A and B inputs and provides a Y output 
The NAND/NOR logic element is configurable as either a NAND or a NOR gate 
by a C (configuration) input. The C input controls two configuration 
transistors: p-transistor C1 and n-transistor C2. Depending on whether the 
C input is deasserted or asserted, these configuration transistors short 
corresponding internal nodes to effect the selected configuration. 
The NAND/NOR logic element 50 includes parallel stacked p-transistors 51 
and 52, and parallel stacked n-transistors 56 and 57. The parallel stacked 
p- and n-transistors are coupled together at output nodes 55a and 55b, 
which provide the Y output of the logic element. 
The parallel stacked transistors 51 and 52 respectively define internal 
nodes 53a/53b. The parallel stacked transistors 56 and 57 respectively 
define internal nodes 58a/58b. 
The configuration p-transistor C1 is coupled between the internal nodes 
53a/53b, and the configuration n-transistor C2 is coupled between the 
internal nodes 58a/58b. 
If the C input is deasserted, the configuration p-transistor C1 turns on 
and shorts the internal nodes 53a/53b. As a result, the NAND/NOR logic 
element 50 is configured as a NAND gate with a corresponding Y output. 
If the C input is asserted, the configuration n-transistor C2 turns on and 
shorts the internal nodes 58a/58b. As a result, the NAND/NOR logic element 
50 is configured as a NOR gate with a corresponding Y output. 
The truth table for the NAND/NOR logic element is: 
______________________________________ 
C A B Y 
______________________________________ 
0 0 0 1 
0 0 1 1 
0 1 0 1 
0 1 1 0 
1 0 0 1 
1 0 1 0 
1 1 0 0 
1 1 1 0 
______________________________________ 
As indicated above, C deasserted [0] provides the NAND configuration, while 
C asserted [1] provides the NOR configuration. 
In an exemplary embodiment, the NAND/NOR logic element is used in an array 
of spare gates included in a processor or other integrated circuit. Each 
NAND/NOR logic element is metal configurable as either a NAND gate or a 
NOR gate by configuring the C input metal line to be either deasserted or 
asserted (such as by tying the C input to ground or to VDD). 
3. XNOR/XOR Logic Element 
FIG. 4 illustrates a configurable XNOR/XOR logic element 60 in accordance 
with one aspect of the invention. The configurable XNOR/XOR logic element 
which receives A and B inverted and noninverted inputs and provides a Y 
output. 
The XNOR/XOR logic element 60 is configurable as either an XNOR or an XOR 
gate by a C (configuration) input. Inverted and noninverted C inputs 
control two coupling circuits: (a) coupling circuit C10 which includes 
p-transistors C11, C12, C13, and C14, and (b) coupling circuit C20 which 
includes n-transistors C21, C22, C23, and C24. Depending on whether the C 
input is deasserted or asserted (and the/C input is correspondingly 
asserted or deasserted), these configuration transistors series or cross 
couple parallel stacked p- and n-transistors to effect the selected 
configuration. 
The XNOR/XOR logic element 60 includes (a) parallel stacked p-transistors 
61 and 62, intercoupled by coupling circuit C10, and (b) parallel stacked 
n-transistors 66 and 67, intercoupled by coupling circuit C20. The 
parallel stacked p- and n-transistors are coupled together at output nodes 
65a/65b, which provide the Y output of the logic element. 
The parallel p-transistors 61b and 62b respectively receive inverted B and 
noninverted B inputs, while the parallel p-transistors 61a and 62a 
respectively receive noninverted and inverted A inputs. The parallel 
n-transistors 66a and 67a respectively receive noninverted and inverted A 
inputs, while the parallel n-transistors 66b and 67b respectively receive 
noninverted and inverted B inputs. 
To configure the XNOR/XOR logic element, the inverted and noninverted 
configuration C inputs are used to selectively configure the coupling 
circuits C10 and C20. Specifically, based on the state of the C and/C 
inputs, (a) the coupling circuit C10 will either series or cross couple 
the/B and B input p-transistors 61a and 62a respectively to the A and/A 
input p-transistors 61a and 62a, and (b) the coupling circuit C20 will 
either series or cross couple the B and/B input n-transistors 66b and 67b 
respectively to the A and/A input n-transistors 66a and 66b. In effect, 
this configuration operation using the C and/C configuration inputs 
configures the XNOR/XOR logic element as either an XNOR or an XOR gate as 
illustrated respectively in FIGS. 2a and 2b. 
Specifically, if the C input is asserted (/C deasserted), then (a) the/B 
and B input p-transistors 61b and 62b are respectively cross-coupled to 
the/A and A input p-transistors 62a and 61a, and (b) the A and/A input 
n-transistors 66a and 67a are respectively cross-coupled to the/B and 
B-input n-transistors 67b and 66b, thereby configuring the XNOR/XOR logic 
element as an XNOR gate with a corresponding Y output. Or, if the C input 
is deasserted (/C asserted), then (a) the/B and B input p-transistors 61a 
and 62b are respectively series-coupled to the A and/A input p-transistors 
61a and 62a, and (b) the A and/A input n-transistors 66a and 67a are 
respectively series-coupled to the B and/B input n-transistors 66b and 
67b, thereby configuring the XNOR/XOR logic element as an XOR gate with a 
corresponding Y output. 
The truth table for the XNOR/XOR logic element is: 
______________________________________ 
C A B Y 
______________________________________ 
0 0 0 0 
0 0 1 1 
0 1 0 1 
0 1 1 0 
1 0 0 1 
1 0 1 0 
1 1 0 0 
1 1 1 1 
______________________________________ 
As indicated above, C deasserted [0] provides the XOR configuration, while 
C asserted [1] provides the XNOR configuration. 
In an exemplary embodiment, the XNOR/XOR logic element is used in an array 
of spare gates included in a processor or other integrated circuit. Each 
XNOR/XOR logic element is metal configurable as either an XNOR gate or an 
XOR gate by configuring the C input metal line to be either deasserted or 
asserted (such as by tying the C input to ground or to VDD). 
4. Full Adder 
In an alternative embodiment, the NAND/NOR and XNOR/XOR logic elements may 
be combined to implement a full adder. 
FIG. 5 illustrates a conventional full adder design. The full adder 80 
includes XOR gates 81 and 82, AND gates 83 and 84, and OR gate 85. The XOR 
81 and AND 83 receive the A and B inputs, while the XOR 82 and AND 84 
receive the Carry-in. The XOR 82 provides the Sum output, and the OR 85 
provides the Carry-out. 
Note that the truth table for the NAND/NOR logic element (Section 2) is the 
truth table for the Complement Carry-out of a full adder (Carry-out is 
available by inverting the inputs to the logic element). Note also that 
the truth table for the XNOR/XOR logic element (Section 3) is also the 
truth table for the Sum output of a full adder. 
FIG. 6 illustrates a full adder 90 formed by a combination of one NAND/NOR 
logic element 91 and one XNOR/XOR logic element 92. The full adder 
receives inverted and noninverted A and B inputs, along with the carry-in 
C from the next LSB adder. The XNOR/XOR logic element 91 provides the Sum 
output, while the NAND/NOR logic element 92 (which receives inverted A, B, 
and C inputs) provides the Carry-out. 
5. Conclusion 
Although the Detailed Description of the invention has been directed to 
certain exemplary embodiments, various modifications of these embodiments, 
as well as alternative embodiments, will be suggested to those skilled in 
the art. 
The invention encompasses any modifications or alternative embodiments that 
fall within the scope of the claims.