Programmable adapter between slow peripherals and network on-chip interfaces

A method and system for adapting communication between a low-speed interface and a high-speed interface is disclosed. The method includes retrieving configuration instructions in response to a power-up of a microcontroller, where the configuration instructions associated with a low-speed communication protocol. The method includes sending the configuration instructions to a low-speed interface module causing the low-speed interface module to configure an interface of the low-speed interface module based on the configuration instructions. The method includes receiving, by the interface of the low-speed interface module, data associated with the low-speed communication protocol. The method includes retrieving, by the microcontroller, mapping instructions associated with a high-speed communication protocol. The method also includes sending, by the microcontroller, the mapping instructions to the low-speed interface module, causing the low-speed interface module to convert the data associated with the low-speed communication protocol to data associated with the high-speed communication protocol.

BACKGROUND

Electronic equipment, such as personal computers, servers, and mobile devices include integrated circuits and system-on-chip devices. Interface protocols and communication standards establish a set of rules that allow the integrated circuits to communicate to one another through their interfaces.

SUMMARY

In the field of system-on-chip integrated circuits and FPGAs, microprocessor based peripheral devices connect to larger networks of digital devices. Such peripheral devices generally consist of digital circuitry performing a predetermined function, but requiring control from external smart logic, such as a microprocessor. For a peripheral device of this type to work autonomously requires a direct connection to dedicated smart logic. In conventional systems, a general purpose microprocessor is used to connect a low-speed peripheral device to the larger network. However, using a dedicated general purpose microprocessor to perform this interface function comes with the added cost of occupying more logic area and consuming more power. Furthermore, general purpose microprocessors are designed for much more complicated tasks and include capabilities that the interface may likely not use. Accordingly, the present disclosure is directed to systems and methods for adapting communication between a relatively low-speed interface and a relatively high-speed interface.

In general, the present disclosure describes an interface adapter that includes a programmable microcontroller surrounded by bus protocol interface logic. The microcontroller is specifically designed to control the interaction between interface modules using a microsequencer-controlled machine cycle. The interface adapter is capable of autonomously adapting the low-speed interface of a peripheral device to the high-speed interface of a network on-chip device.

The operations look-up-table of the microsequencer is used to implement the proprietary instruction operation (OP) code. An assembly language compiler is used to generate the contents of the instruction memory. The assembler outputs a source file (e.g., Verilog) containing the contents of the instruction read-only memory (ROM), which can be used both for simulation and synthesis of the logic. Consequently, the interface adapter's logic and the microcontroller provide a much smaller and much lower power solution for adapting an interface controller to a network-on-chip environment as compared to a general purpose, embedded microcontroller plus custom interface logic. In some implementations, the interface adapter adapts a high-speed network on-chip interface to a low-speed interface peripheral.

Aspects of the present disclosure relate generally to digital logic found in integrated circuits (IC) and Field Programmable Gate Arrays (FPGA), and more particularly to systems and methods for adapting a relatively low-speed interface of a microprocessor-based peripheral device to the relatively high-speed interface of a larger network. The present disclosure further relates to the autonomous operation of such digital logic whereby the larger network of devices operate independent of the peripheral and its connection to the greater network.

One implementation disclosed herein is a method for adapting communication between a low-speed interface and a high-speed interface. The method includes retrieving, by a microcontroller and via an instruction bus, configuration instructions in response to a power-up of the microcontroller. In one implementation, the configuration instructions are associated with a low-speed communication protocol and with a different higher speed communication interface. The method also includes sending, by the microcontroller and via an address/data bus, the configuration instructions to a low-speed interface module causing the low-speed interface module to configure an interface of the low-speed interface module based on the configuration instructions. The method also includes sending, by the microcontroller and via an address/data bus, the configuration instructions to a high-speed interface module causing the high-speed interface module to configure the high-speed interface based on the configuration instructions.

The method also includes entering, by the microcontroller, a low-power mode whereby the microcontroller can be instructed to wait for activity from either the low-speed interface module, the high-speed interface module or both. The method also includes receiving, by way of the interface of the low-speed interface module, data carried via the low-speed communication protocol. The method also includes changing, by way of the low-speed interface module and in response to receiving the data, the state of an interrupt signal causing the microcontroller to wake from the low-power mode. The method also includes receiving, by way of the interface of the high-speed interface module, data carried via the high-speed communication protocol. The method also includes changing, by way of the high-speed interface module and in response to receiving the data, the state of an interrupt signal causing the microcontroller to wake from the low-power mode.

In one implementation, retrieving configuration instructions includes executing, by the microcontroller and via the instruction bus, instructions stored at an initial address of an instruction memory, which is separate from the microcontroller and dedicated to the microcontroller. In one implementation, the address/data bus is separate from the instruction bus, the address/data bus is separate from the memory bus, and the memory bus is separate from the instruction bus.

One implementation enters the low-power mode when executing, by the microcontroller and via the instruction bus, a wait for interrupt (WFI) instruction. One implementation exits the low-power mode by when an interrupt is generated by the low-speed interface module or by when an interrupt is generated by the high-speed interface module. Upon exiting the low-power mode, a jump to another point in the instruction memory is made and the instruction at that address in the instruction memory is executed.

In one implementation, the program stored in the instruction memory can be used to execute one of many instruction subroutines based on information captured in the low-speed interface module after an interrupt from low-speed interface module has been generated to the microcontroller. In one embodiment, the subroutine may interrogate registers within the low-speed interface module via the Addr/Data bus and subsequently execute different sections of instruction code based on branch condition instructions. In another embodiment the subroutine may also interrogate memory locations on the memory bus and subsequently execute different sections of code based on branch condition instructions. In one implementation, the method further includes sending, by the microcontroller and via the address/data bus, new mapping instructions to the low-speed interface module causing the low-speed interface module to convert the data associated with the low-speed communication protocol to data associated with the new high-speed communication protocol.

One implementation disclosed herein is a method for adapting communication between a low-speed interface and a high-speed interface. The method includes retrieving, by a microcontroller and via a memory bus, configuration instructions in response to a power-up of the microcontroller. In some implementations, the configuration instructions are associated with a low-speed communication protocol. The method also includes sending, by the microcontroller and via an address/data bus, the configuration instructions to a low-speed interface module causing the low-speed interface module to configure an interface of the low-speed interface module based on the configuration instructions. The method also includes entering, by the microcontroller, a low-power mode. The method also includes receiving, by the interface of the low-speed interface module, data associated with the low-speed communication protocol. The method also includes changing, by the low-speed interface module and in response to receiving the data, a state of an interrupt signal causing the microcontroller to wake from the low-power mode. The method also includes retrieving, by the microcontroller via an instruction bus, mapping instructions associated with a high-speed communication protocol. The method also includes sending, by the microcontroller and via the address/data bus, the mapping instructions to the low-speed interface module, causing the low-speed interface module to convert the data associated with the low-speed communication protocol to data associated with the high-speed communication protocol.

In some implementations, retrieving configuration instructions from memory includes receiving, by the microcontroller and via the address/data bus, a request for the configuration instructions from the low-speed interface module. In some implementations, the request includes the low-speed communication protocol. In some implementations, retrieving configuration instructions includes executing, by the microcontroller and via the instruction bus, instructions stored at an initial address of an instruction memory. In some implementations, the instruction memory is separate from the microcontroller and dedicated to the microcontroller. In some implementations, the address/data bus is separate from the instruction bus, the address/data bus is separate from the memory bus, and the memory bus is separate from the instruction bus.

In some implementations, entering the low-power mode includes executing, by the microcontroller and via the instruction bus, a wait for interrupt (WFI) instruction stored at a first address of an instruction memory. In some implementations, the instruction memory is separate from the microcontroller and dedicated to the microcontroller. In some implementations, retrieving mapping instructions associated with the high-speed communication protocol includes executing, by the microcontroller and via the instruction bus, a jump to subroutine (JSR) instruction stored at a second address of the instruction memory, causing the microcontroller to execute a subroutine stored at a third address of the instruction memory, the third address stored after the second address.

In some implementations, the method further includes receiving, by the microcontroller and via the address/data bus, a request for new configuration instructions from the low-speed interface module. In some implementations, the request for new configuration instructions includes a new low-speed communication protocol. In some implementations, the low-speed communication protocol is different than the new low-speed communication protocol. In some implementations, the method further includes sending, by the microcontroller and via the address/data bus, new mapping instructions to the low-speed interface module causing the low-speed interface module to convert the data associated with the low-speed communication protocol to data associated with the new high-speed communication protocol. In some implementations, the high-speed communication protocol is different than the new high-speed communication protocol.

In some implementations, the low-speed communication protocol comprises at least one of Advanced Microcontroller Bus Architecture (AMBA) Advanced System Bus (ASB), AMBA Advanced Peripheral Bus (APB), AMBA High-Performance Bus (HPB), and AMBA AXI industry standard interfaces. In some implementations, the high-speed communication protocol comprises at least one of AMBA ASB, AMBA APB, AMBA HPB, and AMBA AXI industry standard interfaces. In some implementations, a data rate of the low-speed communication protocol is lower than a data rate of the high-speed communication protocol.

In some implementations, the method further includes receiving, by an interface of a high-speed interface module, data associated with the high-speed communication protocol. In some implementations, the method further includes sending, by the microcontroller and via the address/data bus, new mapping instructions to the high-speed interface module causing the high-speed interface module to convert the data associated with the high-speed communication protocol to data associated with the low-speed communication protocol.

In another aspect, the present disclosure is directed to an interface adapter for adapting communication between a low-speed interface and a high-speed interface. The interface adapter includes a microcontroller having a first input terminal, a second input terminal, a first bidirectional terminal, a second bidirectional terminal, and a third bidirectional terminal. The interface adapter a high-speed interface module having an output terminal, a first bidirectional terminal, a second bidirectional terminal, and a third bidirectional terminal, wherein the output terminal couples to the second input terminal of the microcontroller. The interface adapter includes a low-speed interface module having an output terminal coupled to the first input terminal of the microcontroller, a first bi-directional terminal, a second bidirectional terminal coupled to the third bidirectional terminal of the microcontroller and the second bidirectional terminal of the high-speed interface module, and a third bidirectional terminal coupled to a third bidirectional terminal of the high-speed interface module. The interface adapter includes an instruction memory having a bidirectional output terminal coupled to the second bidirectional terminal of the microcontroller.

In some implementations, the interface adapter includes a memory comprising a bidirectional terminal coupled to the first bidirectional terminal of the microcontroller. In some implementations, the interface adapter includes the microcontroller adapted to send, via the third bidirectional terminal of the microcontroller, configuration instructions associated with a low-speed communication protocol to the low-speed interface module causing the low-speed interface module to configure an interface associated with the first bidirectional terminal of the low-speed interface module based on the configuration instructions. In some implementations, the low-speed interface module adapted to change, in response to receiving data on the interface that is associated with a low-speed communication protocol, a state of an interrupt signal causing the microcontroller to wake from a low-power mode.

In some implementations, the microcontroller adapted to retrieve, via the first bidirectional terminal of the microcontroller, mapping instructions associated with a high-speed communication protocol. In some implementations, the microcontroller adapted to send, via the third bidirectional terminal of the microcontroller, the mapping instructions to the low-speed interface module, causing the low-speed interface module to convert the data associated with the low-speed communication protocol to data associated with the high-speed communication protocol. In some implementations, the microcontroller adapted to execute, via the second bidirectional terminal of the microcontroller, a jump to subroutine (JSR) instruction stored at a first address of the instruction memory, causing the microcontroller to execute a subroutine stored at a second address of the instruction memory. In some implementations, the second address is stored after the first address. In some implementations, the subroutine causes the microcontroller to retrieve mapping instructions associated with the high-speed communication protocol.

In some implementations, the high-speed interface module adapted to receive data associated with the high-speed communication protocol. In some implementations, the microcontroller adapted to send, via the third bidirectional terminal of the microcontroller, new mapping instructions to the high-speed interface module causing the high-speed interface module to convert the data associated with the high-speed communication protocol to data associated with the low-speed communication protocol.

In some implementations, the low-speed communication protocol comprises at least one of Advanced Microcontroller Bus Architecture (AMBA) Advanced System Bus (ASB), AMBA Advanced Peripheral Bus (APB), AMBA High-Performance Bus (HPB), and AMBA AXI industry standard interfaces. In some implementations, the high-speed communication protocol comprises at least one of AMBA ASB, AMBA APB, AMBA HPB, and AMBA AXI industry standard interfaces. In some implementations, a data rate of the low-speed communication protocol is lower than a data rate of the high-speed communication protocol.

In some implementations, the microcontroller adapted to enter a low-power mode by executing, via the second bidirectional terminal of the microcontroller, a wait for interrupt (WFI) instruction stored at a first address of the instruction memory. In some implementations, the instruction memory is separate from the microcontroller and dedicated to the microcontroller.

In another aspect, the present disclosure is directed a non-transitory computer readable storage medium to store a computer program configured to execute a method for adapting communication between a low-speed interface and a high-speed interface. The method includes retrieving, by a microcontroller and via a memory bus, configuration instructions in response to a power-up of the microcontroller. In some implementations, the configuration instructions are associated with a low-speed communication protocol. The method also includes sending, by the microcontroller and via an address/data bus, the configuration instructions to a low-speed interface module causing the low-speed interface module to configure an interface of the low-speed interface module based on the configuration instructions. The method also includes entering, by the microcontroller, a low-power mode.

The method also includes receiving, by the interface of the low-speed interface module, data associated with the low-speed communication protocol. The method also includes changing, by the low-speed interface module and in response to receiving the data, a state of an interrupt signal causing the microcontroller to wake from the low-power mode. The method also includes retrieving, by the microcontroller via an instruction bus, mapping instructions associated with a high-speed communication protocol. The method also includes sending, by the microcontroller and via the address/data bus, the mapping instructions to the low-speed interface module, causing the low-speed interface module to convert the data associated with the low-speed communication protocol to data associated with the high-speed communication protocol.

In some implementations, the method includes receiving, by an interface of a high-speed interface module, data associated with the high-speed communication protocol. In some implementations, the method includes sending, by the microcontroller and via the address/data bus, new mapping instructions to the high-speed interface module causing the high-speed interface module to convert the data associated with the high-speed communication protocol to data associated with the low-speed communication protocol.

In another aspect, the present disclosure is directed an interface adapter for adapting communication between two interfaces. The interface adapter includes a microcontroller comprising a first input terminal, a second input terminal, a first bidirectional terminal, a second bidirectional terminal, and a third bidirectional terminal. The interface adapter also includes a transmitting interface module comprising an output terminal, a first bidirectional terminal, a second bidirectional terminal, and a third bidirectional terminal. The output terminal couples to the second input terminal of the microcontroller.

The interface adapter includes a receiving interface module comprising an output terminal coupled to the first input terminal of the microcontroller, a first bi-directional terminal, a second bidirectional terminal coupled to the third bidirectional terminal of the microcontroller and the second bidirectional terminal of the high-speed interface module, and a third bidirectional terminal coupled to a third bidirectional terminal of the high-speed interface module. The interface adapter includes an instruction memory comprising a bidirectional output terminal coupled to the second bidirectional terminal of the microcontroller.

In some implementations, the transmitting interface module is associated with a low-speed communication protocol and the receiving interface module is associated with a high-speed communication protocol. In some implementations, the low-speed communication protocol comprises at least one of Advanced Microcontroller Bus Architecture (AMBA) Advanced System Bus (ASB), AMBA Advanced Peripheral Bus (APB), AMBA High-Performance Bus (HPB), and AMBA AXI industry standard interfaces. In some implementations, the high-speed communication protocol comprises at least one of AMBA ASB, AMBA APB, AMBA HPB, and AMBA AXI industry standard interfaces. In some implementations, a data rate of the low-speed communication protocol is lower than a data rate of the high-speed communication protocol.

DETAILED DESCRIPTION

Various implementations will be described in detail with reference to the accompanying drawings. Wherever possible, the same reference numbers may be used throughout the drawings to refer to the same or like parts. Different reference numbers may be used to refer to different, same, or similar parts. References made to particular examples and implementations are for illustrative purposes, and are not intended to limit the scope of the disclosure or the claims.

FIG. 1is a block diagram depicting an interface adapter100for adapting communication between a low-speed interface and a high-speed interface, in accordance with an illustrative implementation. In general, the interface adapter100includes a microcontroller (e.g., microcontroller104), housed within interface adapter100, for fetching instructions from memory (e.g., read-only memory (ROM)) when interrupted by either a low-speed interface module (e.g., low-speed interface module102) or high-speed interface module (e.g., high-speed interface module106). Using status information collected in the interface modules, the microcontroller provides operations to convert the information from one interface module to be used by the other interface module. The low-speed interface module may be connected to any type of interface module including, but not limited to, an Inter-Integrated Circuit (I2C) controller, Serial Peripheral Interface (SPI) controller, an Advanced Microcontroller Bus Architecture (AMBA) Advanced Peripheral Bus (APB) bridge, an AMBA High-Performance Bus (AHB) bridge, or a universal asynchronous receiver/transmitter (UART). Messages that arrive at the low-speed interface module are interpreted by the microcontroller and translated into memory or I/O transactions on the high-speed interface (e.g., network on-chip interface126) connected to the high-speed interface module. This can be performed by the Microcontroller via an address/data bus (e.g., addr/data bus114) or it can be performed directly between the interface adapters using the Transaction Bus (e.g., transaction bus112).

In greater detail, interface adapter100includes a low-speed interface module102(also referred to as receiving interface module102), memory108, a microcontroller104, a high-speed interface module106(also referred to as transmitting interface module106), and read-only memory (shown as ROM110). The interface adapter100also includes a low-speed interface124to support low-speed communication with a peripheral low-speed device and a network on-chip interface126to support high-speed communication with a peripheral network device. In some implementations, interface adapter100may omit memory108such that default settings for interface adapter100are stored in instruction ROM110, internal memory (not shown) of microcontroller104, and/or hardcoded into the assembly language. Interface adapter100may be implemented as an integrated circuit (IC), implemented using only discrete components, or implemented using any combination thereof. As will be discussed below, in another implementation, interface adapter100can include fewer, additional, and/or different components.

A first input terminal of microcontroller104connects to a first output terminal (e.g., interrupt116) of low-speed interface module102, whose first bi-directional terminal (e.g., low-speed interface124) connects to a low-speed peripheral device (not shown). A second input terminal of microcontroller104connects to a first output terminal (e.g., interrupt118) of high-speed interface module106, whose first bidirectional terminal (e.g., network on-chip interface126) connects to a high-speed network peripheral device (not shown). A first bi-directional terminal (e.g., memory bus120) of microcontroller104connects to a bi-directional terminal of memory108. A second bi-directional terminal (e.g., instruction bus122) of microcontroller104connects to a bi-directional terminal of instruction read-only memory (ROM)110. A third bi-directional terminal of microcontroller104(e.g., addr/data bus114) connects to a second bi-directional terminal of low-speed interface module102and to a second bi-directional terminal of high-speed interface module106. A third bi-directional terminal (e.g., transaction bus112) of low-speed interface module102connects to a third bi-directional terminal of high-speed interface module106.

Memory bus120is a bidirectional bus that supports communication between microcontroller104and memory108. In some implementations, memory108is configured for read-only access. In some implementations, memory108may be random-access memory (RAM). In some implementations, memory108is configured for read-write access. As shown inFIG. 1, addr/data bus114and memory bus120are physically separate from one another. For example, program instructions (e.g., configuration instructions and mapping instructions) sent across addr/data bus114from microcontroller104do not reach memory108and memory instructions sent across memory bus120from microcontroller104do not reach low-speed interface module102or high-speed interface module106. In some implementations, addr/data bus114and memory bus120may be a shared/combined bus. In this alternate configuration, address and data program instructions (e.g., configuration instructions and mapping instructions) sent from microcontroller104do reach memory108and memory instructions sent from microcontroller104do reach low-speed interface module102or high-speed interface module106. Memory bus120may be an interface of any number of bits, including for example, 1 bit, 2 bits, 4 bits, 8 bits, 16 bits, 32 bits, 64 bits, 128 bits, 192 bits, 256 bits, 512 bits, 1024 bits, or any other number of bits within 1 bit to 1024 bits.

Low-speed interface module102generates an interrupt signal (e.g., interrupt116) that ramps-up a voltage from a minimum voltage level to a maximum voltage level to cause microcontroller104to change state, such as waking from a power-saving mode (e.g., sleep mode) or transition from an idle state to an active state. In some implementations, low-speed interface module102generates an interrupt signal (e.g., interrupt116) that ramps down a voltage from a maximum voltage level to a minimum voltage level to cause microcontroller104to change state. In some implementations, low-speed interface module102may generate a digital voltage. For example, low-speed interface module102may increase the voltage of interrupt116in fixed step sizes and for a fixed number of steps until interrupt116reaches a maximum voltage step, at which point, low-speed interface module102holds the voltage of interrupt116at the maximum voltage for a predetermined duration (e.g., any time between 1 picosecond and 100 milliseconds) and then drops the voltage of interrupt116back to the minimum voltage level. In some implementations, low-speed interface module102toggles or inverts the voltage of interrupt116from a low-voltage to a high-voltage. In some implementations, low-speed interface module102toggles or inverts the voltage of interrupt116from a high-voltage to a low-voltage. Low-speed interface module102may step up or step down the voltage in any number of voltage steps, for example, any number of steps between 1 and 10. A voltage step may equal to any amount of increasing or decreasing voltage, for example, any voltage between 1 millivolt and 5.0 volt. Low-speed interface module102may generate a sawtooth wave, a triangular wave, a step, a pulse, or pulse train.

Low-speed interface module102generates interrupt116based on activity detected on low-speed interface124. For example, an increase in voltage above a predetermined voltage level on any of the clock and data lines of low-speed interface124may trigger low-speed interface module102to generate interrupt116. In some implementations, a decrease in voltage below a predetermined voltage level on any of the clock and data lines of low-speed interface124may trigger low-speed interface module102to generate interrupt116. In some implementations, low-speed interface module102may poll an internal register to determine if a flag is set, indicating activity on low-speed interface124. In some implementations, low-speed interface124generates an interrupt for activity detected on low-speed interface124occurring after low-speed interface124is configured for a particular low-speed data communication protocol. In some implementations, low-speed interface module102generates interrupt116based on determining that an instruction received on low-speed interface124is specific to the current interface type. For example, a peripheral device having its I2C interface connected to low-speed interface124may send a READ instruction to low-speed interface124. In response to determining that the READ instruction is a member of the instruction set supported by the I2C communication protocol, low-speed interface module102may transmit interrupt116to microcontroller104to cause microcontroller104to wake from its sleep and process the READ instruction. Conversely, if low-speed interface module102determines that the READ instruction is not a member of the I2C communication protocol, then low-speed interface module102does not send interrupt116to microcontroller104.

To support the low-speed data communication protocol indicated by the configuration instructions, low-speed interface module102may configure its low-speed interface124to include any number of clock and data pins. For example, low-speed interface module102may configure low-speed interface124to include a single data pin or multiple data pins that are each timed based on a single clock or multiple clocks. In some implementations, low-speed interface module102may configure low-speed interface124as a synchronous interface (i.e., timed based on a clock cycle). In some implementations, low-speed interface module102may configure low-speed interface124as an asynchronous interface (i.e., not timed based on a clock cycle); as such, low-speed interface124may include a clock data recovery unit (not shown) that generates a clock based on the incoming data. In some implementations, low-speed interface module102may configure low-speed interface124as a serial interface or a parallel interface.

Low-speed interface module102configures its low-speed interface124based on the received configuration instructions. Low-speed interface124may include an internal, dedicated resistor (not shown) having a first terminal connected to each clock and data pin of low-speed interface124. Low-speed interface module102may independently configure each resistor into one of three states. In the first state, low-speed interface module102connects the second terminal of any of the resistors to the positive power supply (e.g., VCC) of interface adapter100to form a “pull-up” resistor. A pull-up resistor holds the logic signal on the associated data pin at a high logic level. In the second state, low-speed interface module102connects the second terminal of any of the resistors to the negative power supply (e.g., VSS) of interface adapter100to form a “pull-down” resistor. This configuration holds the logic signal on the associated data pin at a low logic level. In the third state, low-speed interface module102disconnects the second terminal of any of the resistors to form a “floating” resistor. A floating resistor results in a high-impedance state for the associated data pin. Low-speed interface module102may configure low-speed interface124to support a particular communication protocol indicated by the configuration instructions by configuring each internal resistor into one of these three states. For example, low-speed interface module102may receive configuration instructions to configure low-speed interface124as an I2C interface. In response to receiving the configuration instructions, low-speed interface module102may configure a pin of low-speed interface124as serial data (SDA), configure a pin of low-speed interface124as serial clock (serial clock), and configure the resistors associated with the remaining pins of low-speed interface124into any of the three states described herein. In some implementations, low-speed interface124may disable a pin of low-speed interface124by, for example, disabling power to the pin, configuring the pin into one of the three states described here, or ignoring information received on the pin.

Low-speed interface module102receives configuration instructions from microcontroller104upon power-up of microcontroller104. For example, upon power-up, microcontroller104may send configuration instructions to low-speed interface module102to effectuate configuration of low-speed interface102for a particular low-speed data communication protocol. In some implementations, low-speed interface module102may receive configuration instructions from microcontroller104after a predetermined amount of time (e.g., any time value equal to or between 1 picosecond and 5 seconds) after power-up of microcontroller104. In some implementations, low-speed interface module102may receive configuration instructions from an external computing device (e.g., a microcontroller, a microprocessor, etc.) that resides outside of interface adapter100. In some implementations, low-speed interface module102may be configured based on reading default settings stored in memory. For example, low-speed interface module102may power-up and read default settings stored in internal memory (not shown) housed within low-speed interface module102and configure itself based on the default settings. The default settings may configure the interface for any one of the supported interface types described herein. In some implementations, low-speed interface module102may receive configuration instructions from microcontroller104in response to sending a request to microcontroller104for configuration instructions. For example, low-speed interface module102may determine the interface type of a low-speed peripheral device connected to its low-speed interface124and send a request to microcontroller104to request the interface instructions for the determined interface type. The request may include any information that microcontroller104may use to construct the configuration instructions, such as the interface type, characteristics about the data (e.g., data rate, amplitude, rise time, fall time, duty cycle, transition density, timing, etc.), and the number of clock and data pins.

Low-speed interface module102may send any number of requests for configuration instructions to microcontroller104. In some implementations, each request comprises the same information. For example, low-speed interface module102may send a first request for configuration instructions to configure low-speed interface124for I2C communication and a second request for the same configuration instructions to configure low-speed interface124for I2C communication. In some implementations, some or all of the requests comprise different information. For example, low-speed interface module102may send a first request for configuration instructions to configure low-speed interface124for I2C communication and a second request for configuration instructions to configure low-speed interface124for UART communication (i.e., a different low-speed communication protocol).

Low-speed interface module102may determine the interface type of the low-speed peripheral device connected to its low-speed interface124by capturing data from low-speed interface124and decoding the captured data to identify information unique to a particular interface type. In some implementations, low-speed interface module102may determine the interface type based the electrical characteristics (e.g., number of data signals, number of clock signals, minimum voltage level, maximum voltage level, amplitude, data rate, rise time, fall time, dc bias voltage, capacitive load, output impedance) of the low-speed peripheral device connected to low-speed interface124. In some implementations, low-speed interface module102may determine the interface type based on determining the circuit topology (e.g., open collector/open-drain, open-emitter/open-source) of the receiver and/or transmitter of the low-speed peripheral device connected to its low-speed interface124. For example, low-speed interface module102may determine that the low-speed interface124is connected to the open collector/open-drain of the low-speed peripheral device; in response, low-speed interface module102may determine the interface type as I2C.

Low-speed interface module102may determine the interface type in response to the occurrence of a triggering event, such as, the power-up of interface adapter100, the elapse of a predetermined amount of time (e.g., any time value equal to or between 1 picosecond and 5 seconds) after the power-up of microcontroller104, the receipt of a request from microcontroller104for the interface type, upon the detection of activity on low-speed interface124by low-speed interface module102.

In some implementations, microcontroller104may determine the interface type of low-speed interface124by using any of the same methods the low-speed module102may use to determine the interface type. For example, upon power-up, microcontroller104may determine that low-speed interface124is connected to an I2C interface by determining that low-speed interface124is connected to the open-collector of a low-speed peripheral device.

Low-speed interface module102receives mapping instructions from microcontroller104to effectuate a conversion or mapping of data from a low-speed data communication protocol to a high-speed communication protocol (described below). For example, low-speed interface module102may receive APB data on its low-speed interface124. In response, low-speed interface module102may toggling interrupt116causing microcontroller104to wake from a low-power sleep mode. Once awake, microcontroller104may send mapping instructions to low-speed interface module102specific to mapping APB data to AXI data. Low-speed interface module102may then generate AXI data on transaction bus112from the APB data on its low-speed interface124based on the received mapping instructions. In some implementations, low-speed interface module102may generate encoded data on transaction bus112that matches the same low-speed data communication protocol of the data on low-speed interface module102. For example, low-speed interface module102may receive I2C data on its low-speed interface124and toggle interrupt116to cause microcontroller104to send I2C to AXI mapping instructions to low-speed interface module102. Low-speed interface module102encodes the I2C data with the received mapping instructions to generate encoded I2C data and sends the encoded data to a high-speed interface module (e.g., high-speed interface module106) via transaction bus112. High-speed interface module106decodes the received data to extract the I2C data and the mapping instructions. High-speed interface module106uses the mapping instructions to convert the extracted I2C data to AXI data. High-speed interface module106then drives the receiver of any network on-chip device (not shown) connected to network on-chip interface126with the AXI data.

Low-speed interface module102receives mapping instructions from microcontroller104in response to microcontroller's104receipt of interrupt116. For example, low-speed interface module102sends interrupt116to microcontroller104and in response, microcontroller104sends mapping instructions to low-speed interface module102causing low-speed interface102to translate data on its low-speed interface124from one data communication protocol (e.g., APB) to another data communication protocol (e.g., AXI). Low-speed interface module102receives mapping instructions upon power-up of microcontroller104. For example, upon power-up, microcontroller104may send configuration instructions, mapping instructions, or both to low-speed interface102. In some implementations, low-speed interface module102may receive mapping instructions from microcontroller104after a predetermined amount of time (e.g., any time value equal to or between 1 picosecond and 5 seconds) after power-up of microcontroller104. In some implementations, low-speed interface module102may receive mapping instructions from an external computing device (e.g., a microcontroller, a microprocessor) that resides outside of interface adapter100. In some implementations, low-speed interface module102may be read default mapping instructions stored in memory. For example, low-speed interface module102may power-up and read default mapping settings stored in internal memory (not shown) housed within low-speed interface module102that describe the procedure for mapping I2C data to AXI data. In some implementations, low-speed interface module102may receive mapping instructions from microcontroller104in response to sending a request to microcontroller104for mapping instructions. The request may include any information that microcontroller104may use to construct the mapping instructions, such as the interface type, characteristics about the data (e.g., data rate, amplitude, rise time, fall time, duty cycle, transition density), the number of clock and data pins, a low-speed data communication protocol associated with low-speed interface124, and a high-speed data communication protocol associated with network on-chip interface126. In some implementation, low-speed interface module102receives mapping instructions from microcontroller104in response to microcontroller's104receipt of an interrupt (e.g., interrupt118) from a high speed interface module106. In some implementations, low-speed interface module102receives mapping instructions from microcontroller104without sending interrupt116to microcontroller104. In some implementations, low-speed interface module102sends a notification to an external computing device (e.g., a microcontroller, a microprocessor) that resides outside of interface adapter100to indicate that data has arrived on low-speed interface124. In turn, the external computing device toggles an interrupt signal (e.g., interrupt116) to microcontroller104causing microcontroller104to send mapping instructions to low-speed interface module102.

High-speed interface module106receives transaction data from low-speed interface module102via a transaction bus (e.g., transaction bus112) and drives the received transaction data to an external network on-chip device (not shown) connected to the network on-chip interface (e.g., network on-chip interface126) of interface adapter100. The data rate of the transaction data received by high-speed interface module106may be equal to or greater than the data rate of the data carried on low-speed interface124. For example, low-speed interface124may carry APB data, while transaction bus112may carry AXI data. In another example, low-speed interface124may carry APB data at a first data rate and transaction bus112may carry APB data at a second data rate, where first data rate is lower than second data rate. High-speed interface module106generates data on network on-chip interface126that operates at a higher data rate than the data carried on low-speed interface124. For example, low-speed interface124may carry APB data, while network on-chip interface126may carry AXI data. In some implementations, low-speed interface124may carry data associated with the same communication protocol as the data carried on network on-chip interface126, but at a lower data rate. For example, both low-speed interface124and network on-chip interface126may each carry APB data. However, low-speed interface124carries APB data at a data rate lower than the data rate of the APB data carried on network on-chip interface126. In some implementations, high-speed interface module106may boost the amplitude or power of the data received on transaction bus112via a fixed or variable gain setting. The gain setting may be any value, for example, between 1 dB and 50 dB. In some implementations, high-speed interface module106automatically adjusts the gain setting based on the electrical characteristics of the received data, such as its amplitude, rise time, fall time, timing (e.g., setup/hold), frequency, and low-speed data communication protocol.

In some implementations, messages that arrive at low-speed interface module102are interpreted by microcontroller104and translated into transactions on network on-chip interface126via addr/data bus114. For example, low-speed interface module102toggles interrupt116connected to microcontroller104in response to detecting activity on low-speed interface124. In response to interrupt's116toggled state, microcontroller104wakes from a low-powered state and waits to receive messages from low-speed interface module102via addr/data bus114. Low-speed interface module102sends the messages that it receives on low-speed interface124to microcontroller104via addr/data bus114. Microcontroller104translates the messages into transactions and sends to high-speed interface module106. In some implementations, microcontroller104converts the messages from a low-speed communication protocol to a high-speed communication protocol prior to sending the transactions to high-speed interface module106. In some implementations, microcontroller104may encode the received messages with mapping instructions prior to sending the encoded messages to high-speed interface module106. High-speed interface module106decodes the received data to extract the messages (at the low-speed data communication protocol) and the mapping instructions. High-speed interface module106uses the mapping instructions to convert the extracted messages to a high-speed data communication protocol. High-speed interface module106then drives the receiver of any network on-chip device (not shown) connected to network on-chip interface126with the high-speed data. In some implementations, messages that arrive at low-speed interface module102are interpreted by microcontroller104and translated into memory (e.g., memory108).

High-speed interface module106generates an interrupt signal (e.g., interrupt118) that ramps-up a voltage from a minimum voltage level to a maximum voltage level to cause microcontroller104to change state, such as waking from a power-saving mode (e.g., sleep mode) or transition from an idle state to an active state. In some implementations, high-speed interface module106generates an interrupt signal (e.g., interrupt118) that ramps down a voltage from a maximum voltage level to a minimum voltage level to cause microcontroller104to change state. In some implementations, high-speed interface module106may generate a digital voltage. For example, high-speed interface module106may increase the voltage of interrupt118in fixed step sizes and for a fixed number of steps until interrupt118reaches a maximum voltage step, at which point, high-speed interface module106holds the voltage of interrupt118at the maximum voltage for a predetermined duration (e.g., any time between 1 picosecond and 100 milliseconds) and then drops the voltage of interrupt118back to the minimum voltage level. In some implementations, high-speed interface module106toggles or inverts the voltage of interrupt118from a low-voltage to a high-voltage. In some implementations, high-speed interface module106toggles or inverts the voltage of interrupt118from a high-voltage to a low-voltage. High-speed interface module106may step up or step down the voltage in any number of voltage steps, for example, any number of steps between 1 and 10. A voltage step may equal to any amount of increasing or decreasing voltage, for example, any voltage between 1 millivolt and 5.0 Volt. High-speed interface module106may generate a sawtooth wave, a triangular wave, a step, a pulse, or pulse train.

High-speed interface module106generates interrupt118based on activity detected on network on-chip interface126. For example, an increase in voltage above a predetermined voltage level on any of the clock and data pins of network on-chip interface126may trigger high-speed interface module106to generate interrupt118. In some implementations, a decrease in voltage below a predetermined voltage level on any of the clock and data pins of network on-chip interface126may trigger high-speed interface module106to generate interrupt118. In some implementations, high-speed interface module106may poll an internal register to determine if a flag is set, indicating activity on network on-chip interface126. In some implementations, high-speed interface module106generates an interrupt for activity detected on network on-chip interface126occurring after high-speed interface module106is configured for a particular high-speed data communication protocol. In some implementations, high-speed interface module106generates interrupt118based on determining that an instruction received on network on-chip interface126is specific to the current interface type. For example, a peripheral device having its I2C interface connected to network on-chip interface126may send a READ instruction to network on-chip interface126. In response to determining that the READ instruction is a member of the instruction set supported by the I2C communication protocol, high-speed interface module106may transmit interrupt118to microcontroller104to cause microcontroller104to wake from its sleep and process the READ instruction. Conversely, if high-speed interface module106determines that the READ instruction is not a member of the instruction set supported by the I2C communication protocol, then high-speed interface module106does not send interrupt118to microcontroller104.

To support the high-speed data communication protocol indicated by the configuration instructions, high-speed interface module106may configure its network on-chip interface126to include any number of the clock and data pins. For example, high-speed interface module106may configure network on-chip interface126to include a single data pin or multiple data pins that are each timed based on a single clock or multiple clocks. In some implementations, high-speed interface module106may configure network on-chip interface126as a synchronous interface (i.e., timed based on clock cycle). In some implementations, high-speed interface module106may configure network on-chip interface126as an asynchronous interface (i.e., not timed based on a clock cycle); as such, network on-chip interface126may include a clock data recovery unit (not shown) that generates a clock based on the incoming data. In some implementations, high-speed interface module106may configure network on-chip interface126as a serial interface or a parallel interface.

High-speed interface module106configures its network on-chip interface126based on the received configuration instructions. Network on-chip interface126may include an internal, dedicated resistor (not shown) having a first terminal connected to each clock and data pin of network on-chip interface126. High-speed interface module106may independently configure each resistor into one of three states. In the first state, high-speed interface module106connects the second terminal of any of the resistors to the positive power supply (e.g., VCC) of interface adapter100to form a “pull-up” resistor. A pull-up resistor holds the logic signal on the associated data pin at a high logic level. In the second state, high-speed interface module106connects the second terminal of any of the resistors to the negative power supply (e.g., VSS) of interface adapter100to form a “pull-down” resistor. This configuration holds the logic signal on the associated data pin at a low logic level. In the third state, high-speed interface module106disconnects the second terminal of any of the resistors to form a “floating” resistor. A floating resistor results in a high-impedance state for the associated data pin. High-speed interface module106may configure network on-chip interface126to support a particular communication protocol indicated by the configuration instructions by configuring each internal resistor into one of these three states. For example, high-speed interface module106may receive configuration instructions to configure network on-chip interface126as an AXI interface. In response to receiving the configuration instructions, high-speed interface module106may configure 12 pins of network on-chip interface126as parallel data (e.g., TDATA[11:0]), configure one pin as a clock (e.g., ACLK), configure one pin as TVALID, and configure the resistors associated with the remaining pins of network on-chip interface126into any of the three states described herein. In some implementations, high-speed interface module106may disable a pin of network on-chip interface126by, for example, disabling power to the pin, configuring the pin into one of the three states described here, or ignoring information received on the pin.

High-speed interface module106receives configuration instructions from microcontroller104upon power-up of microcontroller104. For example, upon power-up, microcontroller104may send configuration instructions to high-speed interface module106to effectuate configuration of network on-chip interface126for a particular high-speed data communication protocol. In some implementations, high-speed interface module106may receive configuration instructions from microcontroller104after a predetermined amount of time (e.g., any time value equal to or between 1 picosecond and 5 seconds) after power-up of microcontroller104. In some implementations, high-speed interface module106may receive configuration instructions from an external computing device (e.g., a microcontroller, a microprocessor, etc.) that resides outside of interface adapter100. In some implementations, high-speed interface module106may be configured based on reading default settings stored in memory. For example, high-speed interface module106may power-up and read default settings stored in internal memory (not shown) housed within high-speed interface module106and configure itself based on the default settings. The default settings may configure the interface for any one of the supported interface types described herein. In some implementations, high-speed interface module106may receive configuration instructions from microcontroller104in response to sending a request to microcontroller104for configuration instructions. For example, high-speed interface module106may determine the interface type of a network on-chip device (not shown) connected to its network on-chip interface126and send a request to microcontroller104to request the interface instructions for the determined interface type. The request may include any information that microcontroller104may use to construct the configuration instructions, such as the interface type, characteristics about the data (e.g., data rate, amplitude, rise time, fall time, duty cycle, transition density, timing, etc.), and the number of clock and data pins.

High-speed interface module106may send any number of requests for configuration instructions to microcontroller104. In some implementations, each request comprises the same information. For example, high-speed interface module106may send a first request for configuration instructions to configure network on-chip interface126for AXI communication and a second request for the same configuration instructions to configure network on-chip interface126for AXI communication. In some implementations, some or all of the requests comprise different information. For example, high-speed interface module106may send a first request for configuration instructions to configure network on-chip interface126for AXI communication and a second request for configuration instructions to configure network on-chip interface126for AHB communication (i.e., a different high-speed communication protocol).

High-speed interface module106may determine the interface type of the high-speed peripheral device connected to its network on-chip interface126by capturing data from network on-chip interface126and decoding the captured data to identify information unique to a particular interface type. In some implementations, high-speed interface module106may determine the interface type based the electrical characteristics (e.g., number of data signals, number of clock signals, minimum voltage level, maximum voltage level, amplitude, data rate, rise time, fall time, dc bias voltage, capacitive load, output impedance) of the high-speed peripheral device connected to network on-chip interface126. In some implementations, high-speed interface module106may determine the interface type based on determining the circuit topology (e.g., open collector/open-drain, open-emitter/open-source) of the receiver and/or transmitter of the high-speed peripheral device connected to its network on-chip interface126. For example, high-speed interface module106may determine that the network on-chip interface126is connected to the open collector/open-drain of the high-speed peripheral device; in response, high-speed interface module106may determine the interface type as I2C.

High-speed interface module106may determine the interface type in response to the occurrence of a triggering event, such as, the power-up of interface adapter100, the elapse of a predetermined amount of time (e.g., any time value equal to or between 1 picosecond and 5 seconds) after the power-up of microcontroller104, the receipt of a request from microcontroller104for the interface type, upon the detection of activity on network on-chip interface126by high-speed interface module106.

In some implementations, microcontroller104may determine the interface type of network on-chip interface126by using any of the same methods high-speed module106may use to determine the interface type. For example, upon power-up, microcontroller104may determine that network on-chip interface126is connected to an I2C interface by determining that network on-chip interface126is connected to the open-collector of a high-speed peripheral device.

In some implementations, interface adapter100may translate data from a high-speed data communication protocol to a low-speed data communication protocol, such that the process, as described above, reverses. In this instance, high-speed interface module106receives mapping instructions from microcontroller104to effectuate a conversion or mapping of data from a high-speed data communication protocol to a low-speed communication protocol. For example, high-speed interface module106may receive AXI data on its network on-chip interface126. In response, high-speed interface module106may toggling interrupt118to wake microcontroller104from a low-power sleep mode. Once awake, microcontroller104may send mapping instructions to high-speed interface module106specific to mapping high-rate AXI data to low-rate APB data. High-speed interface module106may then generate APB data on transaction bus112from the AXI data on its network on-chip interface126based on the received mapping instructions. In some implementations, high-speed interface module106may generate encoded data on transaction bus112that matches the same high-speed data communication protocol of the data on high-speed interface module106. For example, high-speed interface module106may receive AXI data on its network on-chip interface126and toggle interrupt118to cause microcontroller104to send AXI to APB mapping instructions to high-speed interface module106. High-speed interface module106encodes the AXI data with the received mapping instructions to generate encoded AXI data and sends the encoded data to a low-speed interface module102via transaction bus112. Low-speed interface module102decodes the received data to extract the AXI data and the mapping instructions. Low-speed interface module102uses the mapping instructions to convert the extracted AXI data to APB data. Low-speed interface module102then drives the receiver of any low-speed peripheral device (not shown) connected to low-speed interface124with the APB data.

High-speed interface module106receives mapping instructions from microcontroller104in response to microcontroller's104receipt of interrupt118. For example, high-speed interface module106sends interrupt118to microcontroller104and in response, microcontroller104sends mapping instructions to high-speed interface module106causing high-speed interface module106to translate data on its network on-chip interface126from one data communication protocol (e.g., AXI) to another data communication protocol (e.g., APB). High-speed interface module106receives mapping instructions upon power-up of microcontroller104. For example, upon power-up, microcontroller104may send configuration instructions, mapping instructions, or both to high-speed interface module106. In some implementations, high-speed interface module106may receive mapping instructions from microcontroller104after a predetermined amount of time (e.g., any time value equal to or between 1 picosecond and 5 seconds) after power-up of microcontroller104. In some implementations, high-speed interface module106may receive mapping instructions from an external computing device (e.g., a microcontroller, a microprocessor) that resides outside of interface adapter100. In some implementations, high-speed interface module106may be read default mapping instructions stored in memory. For example, high-speed interface module106may power-up and read default mapping settings stored in internal memory (not shown) housed within high-speed interface module106that describe the procedure for mapping AXI to APB. In some implementations, high-speed interface module106may receive mapping instructions from microcontroller104in response to sending a request to microcontroller104for mapping instructions. The request may include any information that microcontroller104may use to construct the mapping instructions, such as the interface type, characteristics about the data (e.g., data rate, amplitude, rise time, fall time, duty cycle, transition density), the number of clock and data pins, a low-speed data communication protocol associated with low-speed interface124, and a high-speed data communication protocol associated with network on-chip interface126. In some implementation, high-speed interface module106receives mapping instructions from microcontroller104in response to microcontroller's104receipt of an interrupt (e.g., interrupt116) from low-speed interface module102.

In some implementations, high-speed interface module106receives mapping instructions from microcontroller104without sending interrupt118to microcontroller104. In some implementations, high-speed interface module106sends a notification to an external computing device (e.g., a microcontroller, a microprocessor) that resides outside of interface adapter100to indicate that data has arrived on network on-chip interface126. In turn, the external computing device toggles an interrupt signal (e.g., interrupt118) to microcontroller104causing microcontroller104to send mapping instructions to high-speed interface module106.

Low-speed interface module102receives transaction data from high-speed interface module106via a transaction bus (e.g., transaction bus112) and drives the received transaction data to an external low-speed peripheral device (not shown) connected to low-speed interface124of interface adapter100. The data rate of the transaction data received by low-speed interface module102may be equal to or less than the data rate of the data carried on network on-chip interface126. For example, network on-chip interface126may carry AXI data, while transaction bus112may carry APB data. In another example, network on-chip interface126may carry APB data at a first data rate and transaction bus112may carry APB data at a second data rate, where first data rate is higher than second data rate. Low-speed interface module102generates data on low-speed interface124that operates at a lower data rate than the data carried on network on-chip interface126. For example, network on-chip interface126may carry AXI data, while low-speed interface124may carry I2C data. In some implementations, low-speed interface module102may boost the amplitude or power of the data received on transaction bus112via a fixed or variable gain setting. The gain setting may be any value, for example, between 1 dB and 50 dB. In some implementations, low-speed interface module102automatically adjusts the gain setting based on the electrical characteristics of the received data, such as its amplitude, rise time, fall time, timing (e.g., setup/hold), frequency, and high-speed data communication protocol.

In some implementations, messages that arrive at high-speed interface module106are interpreted by microcontroller104and translated into transactions on low-speed interface124via addr/data bus114. For example, high-speed interface module106toggles interrupt118connected to microcontroller104in response to detecting activity on network on-chip interface126. In response to interrupt's118toggled state, microcontroller104wakes from a low-powered state and waits to receive messages from high-speed interface module106via addr/data bus114. High-speed interface module106sends the messages that it receives on network on-chip interface126to microcontroller104via addr/data bus114. Microcontroller104translates the messages into transactions and sends to low-speed interface module102. In some implementations, microcontroller104converts the messages from a high-speed communication protocol to a low-speed communication protocol prior to sending the transactions to low-speed interface module102. In some implementations, microcontroller104may encode the received messages with mapping instructions prior to sending the encoded messages to low-speed interface module102. Low-speed interface module102decodes the received data to extract the messages (at the high-speed data communication protocol) and the mapping instructions. Low-speed interface module102uses the mapping instructions to convert the extracted messages to a low-speed data communication protocol. Low-speed interface module102then drives the receiver of any low-speed peripheral device (not shown) connected to low-speed interface124with the low-speed data. In some implementations, messages that arrive at high-speed interface module106are interpreted by microcontroller104and translated into memory (e.g., memory108).

Microcontroller104may be a microcontroller of any bit size. In a non-limiting example, microcontroller104may be an 8-bit microcontroller, a 16 bit microcontroller, a 32 bit microcontroller, a 64 bit-microcontroller, or a 128 bit microcontroller. Microcontroller104may be a microcontroller of any memory type. In a non-limiting example, microcontroller104may be an external memory microcontroller, such that microcontroller104reads and writes instructions to memory external to microcontroller104. In another non-limiting example, microcontroller104may be an embedded memory microcontroller, such that microcontroller104reads and writes instructions to memory embedded or internal to microcontroller104. Microcontroller104may comprise any memory architecture. In a non-limiting example, microcontroller104may comprise a Harvard memory architecture or Princeton memory architecture. Microcontroller104may use any type of instruction set. In a non-limiting example, microcontroller104may use a complex instruction set computer (CISC) instruction set permitting the use of a single instruction as an alternative to many simple instructions. In another non-limiting example, microcontroller104may use a Reduced Instruction Set Computer (RISC) instruction set, which reduces the operation time by shortening the clock cycle per instruction. In some implementations, microcontroller104may be microprocessor.

Microcontroller104sends configuration instructions to low-speed interface module102to configure low-speed interface module102for any of the low-speed data communication protocols described herein. For example, upon power-up and/or exiting of a RESET state, microcontroller104fetches and executes program code (e.g., “default settings” as described herein) stored in memory at an initial address (e.g., 0x0) to configure low-speed interface module102for a particular communication protocol. After configuring low-speed interface module102with the default settings, microcontroller104may enter a reduced power state (e.g., sleep, deep sleep) or an IDLE state to wait for the occurrence of an interrupt (e.g., interrupt116). When interrupt116toggles state, microcontroller104wakes from the low power mode and executes the “next instruction” after the wait for interrupt (shown inFIG. 4Aas “WFI”) instruction. For example, if a wait for interrupt (WFI) instruction is stored at address 0x10 and WFI instruction is a two-byte instruction, then the program counter (e.g., program counter308inFIG. 3) of microcontroller104will start accessing the instructions located at address 0x12. In some implementations, microcontroller104fetches the default settings for low-speed interface module102from instruction ROM110. In some implementations, microcontroller104fetches the default settings for low-speed interface module102from memory108. In some implementations, microcontroller104fetches the default settings for low-speed interface module102from microcontroller's104internal memory (not shown). In some implementations, the default settings for high-speed interface module106are hardcoded into the assembly language. For example, if the assembly language supports direct variable access, then the default settings may include constants for microcontroller104to configure the low-speed peripheral interface.

The “next instruction” (as discussed above) after the WFI instruction is a Jump to Subroutine (shown inFIG. 4as “JSR”) instruction. The execution of this instruction by microcontroller104causes microcontroller104to jump to the address location for a subroutine and execute that subroutine. The execution of the subroutine by microcontroller104causes microcontroller104to send mapping instructions to low-speed interface module102to effectuate a conversion or mapping of data from a low-speed data communication protocol to a high-speed communication protocol. Accordingly, messages that arrive at low-speed interface module102via low-speed interface124are interpreted by the microcontroller104and translated into I/O transactions across transaction bus112. In some implementations, messages that arrive at low-speed interface module102via low-speed interface124are interpreted by the microcontroller104and translated into memory (e.g., memory108) via memory bus120.

In some implementations, the execution of the subroutine by microcontroller104causes microcontroller104to send mapping instructions to high-speed interface module106to effectuate a conversion or mapping of data from a high-speed data communication protocol to a low-speed communication protocol. Accordingly, messages that arrive at high-speed interface module106via network on-chip interface126are interpreted by the microcontroller104and translated into input/output (I/O) transactions across transaction bus112. In some implementations, messages that arrive at high-speed interface module106via network on-chip interface126are interpreted by the microcontroller104and translated into memory (e.g., memory108) via memory bus120.

Microcontroller104detects a toggled state on an interrupt when the interrupt transitions from a low-voltage state to a high-voltage state. For example, microcontroller104may detect that an interrupt (e.g., interrupt116, interrupt118) transitions from a low-voltage state to a high-voltage state when the voltage of the interrupt increases above a predetermined voltage threshold, such as, any particular voltage between the range of 1 millivolt and 5.0 volt. In some implementations, microcontroller104may detect a toggled state on an interrupt (e.g., interrupt116, interrupt118) when the interrupt transitions from a high-voltage state to a low-voltage state. For example, microcontroller104may detect that an interrupt (e.g., interrupt116, interrupt118) transitions from a high-voltage state to a low-voltage state when the voltage of the interrupt decreases below the predetermined voltage threshold.

Microcontroller104sends configuration instructions to high-speed interface module106to configure high-speed interface module106for any of the high-speed data communication protocols described herein. For example, upon power-up and/or exiting of a RESET state, microcontroller104fetches and executes program code (e.g., “default settings” as described herein) stored in memory at address 0x0 to configure high-speed interface module106for a particular communication protocol. After configuring high-speed interface module106with the default settings, microcontroller104may enter a reduced power state (e.g., sleep, deep sleep) or an IDLE state to wait for the occurrence of an interrupt (e.g., interrupt116). When interrupt116toggles state, microcontroller104wakes from the low power mode and executes the next instruction after the wait for interrupt (WFI) instruction (shown inFIG. 4). In some implementations, microcontroller104fetches the default settings for high-speed interface module106from instruction ROM110. In some implementations, microcontroller104fetches the default settings for high-speed interface module106from memory108. In some implementations, microcontroller104fetches the default settings for high-speed interface module106from microcontroller's104internal memory (not shown). In some implementations, the default settings for high-speed interface module106are hardcoded into the assembly language. For example, if the assembly language supports direct variable access, then the default settings may include constants for microcontroller104to configure the low-speed peripheral interface.

Microcontroller104may send configuration instructions to low-speed interface module102and/or high-speed interface module106in response to the occurrence of a triggering event, such as, the power-up of microcontroller104, microcontroller's104exit from a RESET state, the elapse of a predetermined amount of time (e.g., any time value equal to or between 1 picosecond and 5 seconds) after the power-up of microcontroller104, receipt of a request from low-speed interface module102for configuration instructions, receipt of a request from high-speed interface module106for configuration instructions, or receiving a notification message from a device directly or indirectly connected to interface adapter100, such as a low-speed peripheral device (not shown) and a network on-chip device (not shown). As discussed herein, microcontroller104may receive any number of requests for configuration instructions from low-speed interface module102and/or high-speed interface module106. In some implementations, microcontroller104may send a request to low-speed interface102requesting the interface type of low-speed interface124. In some implementations, microcontroller104may send a request to high-speed interface module106requesting the interface type of network on-chip interface126.

FIG. 2is a block diagram depicting a low-speed interface module102for adapting communication between a low-speed interface (e.g., low-speed interface124) and a high-speed interface (e.g., network on-chip interface126), in accordance with an illustrative implementation. Low-speed interface module102includes low-speed interface module registers202and a bus state machine208. In some implementations, low-speed interface module102may include fewer, additional, and/or different components. An input terminal of low-speed interface module registers202connects to an intellectual property (IP) core (not shown) to receive IP interrupt request204. A first bi-directional terminal (e.g., addr/data bus114) of low-speed interface module registers202connects to the IP Core to send and receive address/data instructions. A first output terminal of low-speed interface module registers202connects to an input terminal of bus state machine208, whose output terminal (e.g., control bus210) connects to the IP Core to send control bus instructions. A second bi-directional terminal (e.g., transaction bus112) of low-speed interface module registers202connects to a third bi-directional terminal of high-speed interface module106(as shown inFIG. 1) to send and receive transaction data. A third bi-directional terminal (e.g., addr/data bus114) of low-speed interface module registers202connects to a third bi-directional terminal of microcontroller104(as shown inFIG. 1) to send and receive address/data instructions.

Low-speed interface module registers202are a consistent set of registers that low-speed interface module102uses to hold transaction information. In some implementations, the transaction information is independent of the peripheral interface (e.g., low-speed interface124). In some implementations, the transaction information is dependent on the peripheral interface. Likewise, high speed interface module106ofFIG. 1contains control, address, and data registers (not shown) that high-speed interface module106may use to control network on-chip interface126as configured for a particular high-speed communication protocol. However, the functionality of the state machine (e.g., bus state machine208) within each module depends on the interface type or low-speed/high-speed communication protocol. In some implementations, the functionality of the state machine (e.g., bus state machine208) within each module does not depend on the interface type or low-speed/high-speed communication protocol. In some implementations, configuration instructions modify low-speed interface module registers202for a particular low-speed communication protocol. In some implementations, low-speed interface module registers202may be modified or updated by instructions (e.g., configuration instructions, mapping instructions) sent from microcontroller104to allow low-speed interface module102to control low-speed interface124for a particular low-speed communication protocol. In some implementations, high-speed interface module registers (not shown) may be modified or updated by instructions (e.g., configuration instructions, mapping instructions) sent from microcontroller104to allow high-speed interface module106to control network on-chip interface126for a particular high-speed communication protocol.

FIG. 3is a block diagram depicting a microcontroller104for adapting communication between a low-speed interface (e.g., low-speed interface124) and a high-speed interface (e.g., network on-chip interface126), in accordance with an illustrative implementation. Microcontroller104includes a micro-sequencer (shown as sequencer302), a timing generator304, a program counter308, branch logic310, an arithmetic-logic unit (shown as ALU314), a state register316, an accumulator318, an X register320, a Y register322, an operations look-up table (shown as OP LUT306), and an Input/Output block (shown as I/O312). As shown, instruction ROM110resides outside of microcontroller104. In some implementations, instruction ROM110is housed within microcontroller104. In another implementation, microcontroller104may include fewer, additional, and/or different components.

A first input terminal of sequencer302connects to an output terminal of timing generator304. A second input terminal of sequencer302connects to an output terminal of OP LUT306. A first bi-directional terminal of sequencer302connects to a first bidirectional terminal of program counter308. A second bi-directional terminal of sequencer302connects to a first bidirectional terminal of ALU314, which has connections (not shown) to state register316, accumulator318, X register320, and Y register322. A third bi-directional terminal of sequencer302connects to a first bidirectional terminal of I/O312. A second bidirectional terminal of program counter308connects to a first bidirectional terminal of instruction ROM110. An input terminal of program counter308connects to an output terminal of branch logic310. A second bi-directional terminal (e.g., memory bus120) of I/O312connects to a first bi-directional terminal of memory108(as shown inFIG. 1). A third bi-directional terminal (e.g., addr/data bus114) of I/O312connects to a second bi-directional terminal of low-speed interface module102(as shown inFIG. 1) and a second bi-directional terminal of high-speed interface module106(as shown inFIG. 1). A fourth bi-directional terminal of I/O312connects to a bi-directional terminal of accumulator318. A first input terminal of I/O312connects to a first output terminal of X register320and a second input terminal of I/O312connects to a first output terminal of Y register322.

As shown inFIG. 3, microcontroller104adapts communication between a low-speed interface (e.g., low-speed interface124) and a high-speed interface (network on-chip interface126) via instruction ROM110, memory bus120, and addr/data bus114. Program instructions (e.g., configuration instructions, mapping instructions) sent by microcontroller104across either of the buses may be any byte length, for example, 1 byte, 2 bytes, 4 bytes, 8 bytes, 16 bytes, 32 bytes, or 64 bytes. Program counter308maintains a pointer to the program instruction currently being executed by microcontroller104. All program instructions, regardless of their length, take 4 clock cycles to complete, which comprises one machine cycle. In some implementations, all program instructions may take any number of clock cycles to complete, for example, any clock cycle in the range of 1 to 10 clock cycles. All internal operations are synced to one of the clock cycles (e.g., to one of the 4 clock cycles) in the machine cycle as orchestrated by timing generator304and executed by the outputs of the OP LUT306. Timing generator304and OP LUT306form sequencer302. In some implementations, sequencer302may be a microsequencer. In some implementations, sequencer302generates the addresses used to step through the microprogram of a control store.

ALU314implements addition, subtraction, logical shift operations, and Boolean logic operations, and has three target outputs: X register320, Y register322, and accumulator318. State register316consists of a Zero Detected bit, which is set whenever accumulator318contains a value of zero as a result of executing an instruction. Branch instructions may test this bit to conditionally perform a jump (shown inFIG. 4as “JSR”) to another bit location (e.g., another 8 bit location) within instruction ROM110. In some implementations, unconditional absolute branch instructions are supported. A Wait for Interrupt instruction (shown inFIG. 4as “WFI”) provides the ability for microcontroller104to enter a low-power state when it is not performing its interface operations. In a non-limiting example, ALU314may be an 8-bit ALU, a 16-bit ALU, a 32-bit ALU, a 64-bit ALU, and a 128-bit ALU.

Microcontroller104is driven by sequencer302, which provides the control signals to drive most of microcontroller's104internal functions. These control outputs come directly from the OP LUT306. The operation (OP) code currently stored in the program counter308indexes OP LUT306. In a non-limiting example, the outputs of OP LUT306may include the following controls:

(1) address mode of the instruction

(2) branch mode of the instruction

(3) bytes per instruction

(4) ALU input source select

(5) ALU input register select

(6) ALU OP code

(7) ALU target register select

To program microcontroller104, an assembly language program file may be generated.FIG. 4is a table400depicting instructions and assembly language references that microcontroller104may execute when adapting communication between a low-speed interface and a high-speed interface, in accordance with an illustrative implementation. The OP Code (shown in the OP Code column ofFIG. 4) is the numeric value assigned to the instruction. Although shown as a specific value (e.g., 0x00, 0x01, 0x02, etc.), the value of the OP Code in each of the rows of the table inFIG. 4may be any hex value, for example, in the range of 0x00 and 0x15. The Z column represents how the “Zero Detect Bit” in State Register316is affected by the instruction.

Once generated, the assembly language program reads the assembly source file and produces a Verilog source file containing an implementation of the instruction ROM, which is stored in instruction ROM110. In some implementations, the assembly language program produces a source file using any hardware description language (e.g., very high-speed hardware description language (VHDL), Verilog, etc.) or programming language (e.g., C, C++, C#, Java, Perl, TCL, Python, etc.). When the program is properly implemented, the program begins its autonomous control of interface adapter100by executing the instruction at address 0.

FIG. 5Ais a flow diagram depicting a process500A for adapting communication from a low-speed interface to a high-speed interface, in accordance with an illustrative implementation. Additional, fewer, or different operations may be performed depending on the implementation of the process. The process500A may be implemented by a system such as interface adapter100ofFIG. 1. At operation502A, interface adapter100powers up and microcontroller104exits RESET. At operation504A, microcontroller104fetches and executes program code from instruction ROM110at an initial memory address location (e.g., 0x0) causing microcontroller104to proceed to operation506A. At operation506A, microcontroller104retrieves default configuration instructions for a particular low-speed communication protocol from memory (e.g., instruction ROM110, memory108, memory internal to microcontroller104, etc.). At operation508A, microcontroller104sends the default configuration instructions to low-speed interfaced module102to configure low-speed interface module102for the default low-speed communication protocol. At operation510A, microcontroller104enters a low-powered state. For example, microcontroller104may execute a Wait For Interrupt (WFI) instruction causing microcontroller104to enter a low-power mode. At operation512A, microcontroller104detects the status of interrupt116. At operation514A, microcontroller104determines if interrupt116changes or toggles state. If interrupt116does not change state, then microcontroller104proceeds back to operation512A; otherwise, microcontroller104proceeds to operation516A to wake from the low power mode and execute a Jump to Subroutine (JSR) instruction. At operation518A, microcontroller104sends mapping instructions to low-speed interface module102to effectuate a conversion or mapping of data from a low-speed data communication protocol to a high-speed communication protocol. At operation520A, microcontroller104checks if it receives an instruction on addr/data bus114. At operation522A, microcontroller determines if the received instruction is a request for configuration instructions and/or mapping instructions for a second type of low-speed communication protocol (i.e., different than the default low-speed communication protocol). If the instruction is not a request for a configuration instruction and/or mapping instruction of a different type, then microcontroller104proceeds back to operation520A. However, if microcontroller did receive such a request, then microcontroller104proceeds to operation524A to retrieve the requested configuration and/or mapping instructions from memory. At operation526A, microcontroller sends the requested configuration and/or mapping instructions to low-speed interface module102and proceeds back to operation520A.

FIG. 5Bis a flow diagram depicting a process500B for adapting communication from a high-speed interface to a low-speed interface, in accordance with an illustrative implementation. Additional, fewer, or different operations may be performed depending on the implementation of the process. The process500B may be implemented by a system such as interface adapter100ofFIG. 1. At operation502B, interface adapter100powers up and microcontroller104exits RESET. At operation504B, microcontroller104fetches and executes program code from instruction ROM110at an initial memory address location (e.g., 0x0) causing microcontroller104to proceed to operation506B. At operation506B, microcontroller104retrieves default configuration instructions for a particular high-speed communication protocol from memory (e.g., instruction ROM110, memory108, memory internal to microcontroller104, etc.). At operation508B, microcontroller104sends the default configuration instructions to high-speed interfaced module106to configure high-speed interface module106for the default high-speed communication protocol. At operation510B, microcontroller104enters a low-powered state. For example, microcontroller104may execute a Wait For Interrupt (WFI) instruction causing microcontroller104to enter a low-power mode. At operation512B, microcontroller104detects the status of interrupt118. At operation514B, microcontroller104determines if interrupt118changes or toggles state. If interrupt118does not change state, then microcontroller104proceeds back to operation512B; otherwise, microcontroller104proceeds to operation516B to wake from the low power mode and execute a Jump to Subroutine (JSR) instruction. At operation518B, microcontroller104sends mapping instructions to high-speed interface module106to effectuate a conversion or mapping of data from a high-speed data communication protocol to a low-speed communication protocol. At operation520B, microcontroller104checks if it receives an instruction on addr/data bus114. At operation522B, microcontroller determines if the received instruction is a request for configuration instructions and/or mapping instructions for a second type of high-speed communication protocol (i.e., different than the default high-speed communication protocol). If the instruction is not a request for a configuration instruction and/or mapping instruction of a different type, then microcontroller104proceeds back to operation520B. However, if microcontroller did receive such a request, then microcontroller104proceeds to operation524B to retrieve the requested configuration and/or mapping instructions from memory. At operation526B, microcontroller sends the requested configuration and/or mapping instructions to high-speed interface module106and proceeds back to operation520B.

FIG. 5Cis a flow diagram depicting a process500C for adapting communication from a high-speed interface to a low-speed interface, in accordance with an illustrative implementation. Additional, fewer, or different operations may be performed depending on the implementation of the process. The process500C may be implemented by a system such as interface adapter100ofFIG. 1. At operation502C, a microcontroller (e.g., microcontroller104) retrieves—via a memory bus (e.g., memory bus120)—configuration instructions in response to a power-up of the microcontroller. In some implementations, the configuration instructions are associated with a low-speed communication protocol. At operation504C, the microcontroller sends—via an address/data bus (e.g., addr/data bus114)—the configuration instructions to a low-speed interface module (e.g., low-speed interface module102) causing the low-speed interface module to configure an interface (e.g., low-speed interface124) of the low-speed interface module based on the configuration instructions. At operation506C, the microcontroller enters a low-power mode. In some implementations, the low-power mode may be a sleep mode, a deep sleep mode, or an IDLE mode that consumes less power than that consumed during an ACTIVE mode. At operation508C, the interface of the low-speed interface module receives data associated with the low-speed communication protocol. At operation510C, the low-speed interface module changes—in response to receiving the data—a state of an interrupt signal (e.g., interrupt116) causing the microcontroller to wake from the low-power mode. At operation512C, the microcontroller retrieves—via an instruction bus (e.g., instruction bus122)—mapping instructions associated with a high-speed communication protocol. At operation514C, the microcontroller sends—via the address/data bus—the mapping instructions to the low-speed interface module, causing the low-speed interface module to convert the data associated with the low-speed communication protocol to data associated with the high-speed communication protocol.

It should be understood that implementations of the present disclosure may be used in a variety of applications. Although the present disclosure is not limited in this respect, the circuits disclosed herein may be used in many apparatuses such as in internal and external hard drives, storage devices, transmitters, receivers, and modems of a communication system, a video codec, audio equipment such as music players and microphones, a television, camera equipment, test equipment such as an oscilloscope, and medical equipment. Communication systems intended to be included within the scope of the present disclosure include, by way of example only, cellular radiotelephone communication systems, satellite communication systems, two-way radio communication systems, one-way pagers, two-way pagers, personal communication systems (PCS), personal digital assistants (PDA's) and the like.

The various implementations illustrated and described are provided merely as examples to illustrate various features of the claims. However, features shown and described with respect to any given implementation are not necessarily limited to the associated implementation and may be used or combined with other implementations that are shown and described. Further, the claims are not intended to be limited by any one example implementation.

The term “coupled” disclosed in this description may encompass both direct and indirect coupling. Thus, first and second parts are said to be coupled together when they directly contact one another, as well as when the first part couples to an intermediate part which couples either directly or via one or more additional intermediate parts to the second part. The term “connects” or “connected” disclosed in this description encompasses a direct connection between components. The term “substantially” or “about” may encompass a range that is largely, but not necessarily wholly, that which is specified. It encompasses all but a significant amount. When devices or components of the delta sigma modulator are responsive to events, the actions and/or steps of devices, such as the operations that other devices are performing, necessarily occur as a direct or indirect result of the preceding events and/or actions. In other words, the operations occur as a result of the preceding operations. A device that is responsive to another requires more than an action (i.e., the device's response to) merely follow another action.

The preceding description of the disclosed implementations is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these implementations will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to some implementations without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the implementations shown herein but is to be accorded the widest scope consistent with the following claims and the principles and novel features disclosed herein.