THREE DIMENSIONAL CHIP ARCHITECTURE

Three-dimensional chip architecture is described herein. In one example aspect, an integrated circuit may include an interposer layer. The integrated circuit may further include a plurality of random access memory chiplets stacked atop the interposer layer, and a plurality of compute chiplets. The plurality of compute chiplets may be stacked atop a respective random access memory chip of the plurality of random access memory chiplets, such that the plurality of compute chiplets may be in electrical communication with the respective random access memory chip of the plurality of random access memory chiplets.

TECHNOLOGICAL FIELD

Examples of the present disclosure relate generally to methods, apparatuses and computer program products for providing three-dimensional architecture for computer chips.

BACKGROUND

For integrated circuits, electronic circuits may be fabricated on a semiconductor die, which may form a chip or chiplet. Each chip or chiplet may include one or more processing elements capable of performing specified functions on a given set of data or information.

Typically, the more processing elements a chip has, the more processing power the chip is capable of. However, conventional techniques to add processing power to a chip are limited. For example, in a two-dimensional approach, additional processing elements may be added along the width and length dimensions of the die. This two-dimensional approach is typically limited due to the size constraints (e.g., area) of a die, particularly for microelectronic technologies.

BRIEF SUMMARY

This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to limit the scope of the claimed subject matter. The foregoing needs are met, to a great extent, by the present application described in more detail below.

Three-dimensional application specific integrated circuit architecture is described herein. An integrated circuit may include computing chiplets, which may be stacked atop random access memory chiplets. In some cases, the stacking may include a compute die stacked atop another compute die. The stacking may provide the ability for the computing chiplets and random access memory chiplets to communicate via short, low-latency, and/or low attenuation. The stacking may also allow for minimizing the area footprint of the integrated circuit.

In this regard, examples of the present disclosure may provide higher memory per unit area and increased compute processing (e.g., Tera operations per second (TOPs)) for integrated circuits. For instance, in some examples, the integrated circuit architecture of the examples of the present disclosure may increase the TOPS by at least four times (for example by utilizing a three-dimensional (3D) topology/configuration) and in some examples may increase memory (e.g., static random-access memory (SRAM)) capacity between eight-ten times. Additionally, the examples of the present disclosure may improve integrated circuit system latency and power efficiency between chiplets or chips. For example, by introducing another dimension as a degree of freedom, the communication networks in such an architecture may deliver lower latency than a conventional 2D topology.

In one example aspect of the present disclosure, an integrated circuit (IC) is provided. The integrated circuit may include an interposer layer. The integrated circuit may further include a plurality of random access memory chiplets stacked atop the interposer layer, and a plurality of compute chiplets. The plurality of compute chiplets may be stacked atop a respective random access memory chip of the plurality of random access memory chiplets, such that the plurality of compute chiplets may be in electrical communication with the respective random access memory chip of the plurality of random access memory chiplets.

In another example aspect of the present disclosure, a method is provided. The method may include transmitting at least one electrical signal from a computing chiplet. The method may further include transferring the at least one electrical signal to a random access memory chiplet. The computing chiplet may be stacked atop the random access memory chiplet, thereby forming a three-dimensional stacked integrated circuit.

In yet another example aspect of the present disclosure, a computer program product is provided. The computer program product may include at least one non-transitory computer-readable medium including computer-executable program code instructions stored therein. The computer-executable program code instructions may include program code instructions configured to transmit at least one electrical signal from a computing chiplet. The computer program product may further include program code instructions configured to transfer the at least one electrical signal to a random access memory chiplet. The computing chiplet may be stacked atop the random access memory chiplet, thereby forming a three-dimensional stacked integrated circuit.

In some examples, the plurality of random access memory chiplets may comprise static random access memory (SRAM) chiplets. In some examples, the plurality of compute chiplets may comprise a plurality of processing elements (PEs). In some examples, the IC may include a plurality of high bandwidth memory (HBM) stacked atop the interposer layer. In some examples, the IC may include a set of chiplets (e.g., network chiplets) stacked atop the interposer layer. The chiplets may for example include functionality, including but not limited to, networking, input/output (I/O), a network interface card or a network interface controller (NIC) and/or the like.

In some examples, the plurality of random access memory chiplets are configured to electrically communicate with one another via the interposer layer. In some examples, more than one compute chiplet of the plurality of computer chiplets is stacked atop a random access memory chiplet of the plurality of random access memory chiplets. In some examples, one or more random access memory chiplets of the plurality of random access memory chiplets are configured to electrically communicate with other random access memory chiplets of the plurality of random access memory chiplets via the interposer layer.

In some examples, the IC may further include a substrate layer, wherein the interposer layer is stacked atop the substrate layer; and at least one host central processing unit (CPU) stacked atop the substrate layer, wherein the at least one host CPU is in electrical communication with the interposer layer via the substrate layer. In some examples, the at least one host CPU comprises two host CPUs.

In some examples, the IC may further include a set of network and CPU chiplets, wherein the set of network and CPU chiplets are stacked atop the interposer layer. In some examples, the IC may further include a CPU stacked atop the interposer layer. In some examples, the IC may further include another random access memory stacked atop the interposer layer; and a CPU stacked atop the another random access memory, wherein the host CPU is in electrical communication with the another random access memory. In some examples, the another random access memory is configured to be in electrical communication with the plurality of random access memory chiplets via the interposer layer.

There has thus been outlined, rather broadly, certain embodiments of the present disclosure in order that the detailed description thereof may be better understood, and in order that the present contribution to the art may be better appreciated.

DETAILED DESCRIPTION

A detailed description of the illustrative embodiments will be discussed in reference to various figures, embodiments, and aspects herein. Although this description provides detailed examples of possible implementations, it should be understood that the details are intended to be examples and thus do not limit the scope of the application.

Reference in this specification to “one embodiment,” “an embodiment,” “one or more embodiments,” “an aspect” or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. Moreover, the term “embodiment” in various places in the specification is not necessarily referring to the same embodiment. That is, various features are described which may be exhibited by some embodiments and not by the other.

It is understood that any or all of the systems, methods and processes described herein may be embodied in the form of computer executable instructions, e.g., program code, stored on a computer-readable storage medium which instructions, when executed by a machine, such as a computer, server, transit device or the like, perform and/or implement the systems, methods and processes described herein. Specifically, any of the steps, operations or functions described above may be implemented in the form of such computer executable instructions. Computer readable storage media includes volatile and nonvolatile, removable, and non-removable media implemented in any method or technology for storage of information, but such computer readable storage media do not include signals. Computer readable storage media may include, but are not limited to, random access memory (RAM), read only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD ROM), digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other physical medium which may be used to store the desired information and which may be accessed by a computer.

As defined herein a “computer-readable storage medium,” which refers to a non-transitory, physical or tangible storage medium (e.g., volatile or non-volatile memory device), may be differentiated from a “computer-readable transmission medium,” which refers to an electromagnetic signal.

Some manufacturers may attempt to maximize processing and storage capabilities of an application specific integrated circuit (ASIC) by including more processing/storage components onto a given chip. There may also be a cost advantage as well, as smaller chip sizes may provide for more dies to be cut or etched from a single wafer. However, ASIC dimensions are typically limited based on the reticle limit, which is the maximum area of chip that may be manufactured. Manufacturers may be unable to overcome the reticle limit by increasing the width and/or length dimensions of the chip. These large full reticle size chips may be prone to defects. This may result in poor yield and increasing chip cost. However, these issues may be addressed by using smaller chip size in particular technologies (e.g., microelectronics). According to the present disclosure, a chip may include a three-dimensional architecture. The chip may include computing chiplets configured to perform various processing functions. The computing chiplets may be stacked atop random access memory chiplets. Likewise, other components of the chip may either be stacked on an interposer, or may be stacked on memory as well, to enable communicating between non-stacked entities. This stacking may facilitate high speed, low latency communications between the memory and computing chiplets, which may enable for more powerful processing capabilities of the chip.

FIG.1depicts a conventional chip100. The chip100may include a compute chiplet105capable of performing various processes; network (NW) chiplets110capable of managing communications between entities internal and external to the chip100; and high bandwidth memory (HBM) chiplets115configured to store data (e.g., as bits). These components may be placed on an interposer120. The interposer120may facilitate electrical communications between the various components atop the interposer120. This configuration of various components in electrical communication with each other via an interposer is typically referred to as a 2.5-dimensional configuration (2.5D).

Chips including 2.5D configurations are typically limited in capabilities, in part due to the communication routes imposed by the configuration. Each component positioned on the interposer may transmit communications to other components on the interposer via the interposer. The communication route length and material of the interposer may cause communication delay as well as communication attenuation. This lag may also impose limitations on processing capabilities of the chip, particularly in examples where multiple components may require communicating or coordinating with one another to fulfill a task.

Further, in examples where the chip100is also an integrated circuit, a host CPU125may also be included in the chip100. However, host CPUs125are typically unable to be placed atop the interposer120, and thus an additional substrate layer130(e.g., a printed circuit board (PCB) layer) may be implemented, where the host CPU125and the interposer120are placed atop the substrate layer130. This may further cause communication delays, as the host CPU125communicates with the components of the interposer120by transmitting a communication to the substrate layer130, which travels to the interposer120, and then to the particular component (e.g., the compute chiplet105).

FIG.2depicts a chip200implementing a 3D configuration according to an example of the present disclosure. The chip200may in some examples be a chiplet that may be configured to operate with other chiplets (not shown) to form a chip. In some examples, the chip200may be an ASIC. In some examples, the chip200may be configured to perform machine learning (ML) processes and/or artificial intelligence (AI) processes. In some other examples, the chip200may be configured to perform other applications (e.g., video transcoding, etc.).

The chip200may include a substrate205. The substrate205may be a section of semiconducting material (e.g., layer) that may support other components of the chip200. For example, the substrate205may be composed of silicon. The substrate205may form a plane, where the substrate205may include a length and width that are substantially greater than a substrate thickness. The substrate205may be configured to house, include, or contain a circuitry component(s) along a given surface.

The chip200may also include an interposer210. The interposer210may be disposed atop the substrate205. The interposer210may facilitate electrical communications from the substrate205to components atop the interposer210, or between different components atop the interposer210. The interposer210may be composed of semiconducting material, such as for example silicon, and may include electrical connections (e.g., on a top surface) capable of carrying electrical connections to and from different components atop the interposer210. The interposer210may form a plane, where the interposer210may include a width and length that are substantially greater than an interposer thickness. Further, the interposer plane may be generally parallel to the substrate plane. In some examples, the interposer length, width, or both, may be smaller than the length and/or the respective width of the substrate205.

One or more bottom chiplets (e.g., random access memory chiplets215) may be disposed atop the interposer210. The random access memory chiplets215may be electrically connected to the interposer210(e.g., via the interposer top surface and the memory bottom surface), such that a random access memory chiplet215is configured to transmit and receive electrical communications via the interposer210to other components atop the interposer210, to other components atop the substrate205, or both. The random access memory chiplets215may in some examples be static random access memory (SRAM), such that the data stored by a SRAM is statically maintained. In some cases, the random access memory chiplets215may connect to DRAM, and may include In-memory compute, near memory, Network-On-Chip, and/or the like.

The chip200may also include one or more computing chiplets220. Computing chiplets220may be disposed atop a random access memory chiplet215. A computing chiplet220may be in electrical communication with the random access memory chiplet215the computing chiplet is disposed on. For example, a computing chiplet220may include electrical connections on its bottom surface, which may be coupled to electrical connection on a top surface of the respective random access memory chiplet215. Thus, a computing chiplet220may be configured to be in electrical communication with its respective random access memory chiplet215. In some examples, a computing chiplet220may be configured to electrically communicate with other components atop the interposer210, such as other computing chiplets220(e.g., an electrical communication travels from the computing chiplet220, to its respective random access memory chiplet215, to the interposer210, to another random access memory chiplet215, and to another computing chiplet220), other components atop the substrate205(e.g., a CPU), and/or the like. In some examples, the electrical connection between the computing chiplet220and the respective random access memory chiplet215may be direct, such as by bump bonds or electrical pins. In some examples, the electrical connection may be indirect, such as by implementing electrical leads between a computing chiplet220and a respective random access memory chiplet215.

Each computing chiplet220may be configured to include one or more processing elements221. The processing elements221may be configured to receive a data set(s) and perform distinct process operations on the data(s). For example, a processing element221may be configured to perform an arithmetic function (e.g., multiplier, derivation, additive, and/or the like) on the set of data(s). In some examples, a processing element221may be configured to perform a logical function (e.g., and, ors, nors, and/or the like) on a set of data(s). In some examples, the processing elements221may include functions specific to that processing element (e.g., the processing elements may be distinct from one another). In some examples, the processing elements221may receive the data set(s) from a particular circuitry component (e.g., another processing element), process the data, and output the processed results to another particular circuitry component (e.g., another particular circuitry element) to form a processing pipeline. In some examples, a computing chiplet220may include a predetermined quantity of processing elements221(e.g., 32 processing elements, 16 processing elements, etc.).

More than one computing chiplet220may be stacked atop a given random access memory chiplet215. For example, as shown inFIG.2, a random access memory chiplet215may include two or more computing chiplets220stacked atop the random access memory chiplet215. In some examples, each computing chiplet220on a respective random access memory chiplet215may electrically communicate with another computing chiplet220on the respective random access memory chiplet215directly via the random access memory chiplet215, such that the electrical communication may not travel through the interposer210.

The chip200may also include one or more high bandwidth memory (HBM) chiplets225. In some examples of the present disclosure, the HBM chiplets225may be referred to herein as HBMs225. The HBMs225may provide additional memory capacity of the chip200, for example, for AI model/inference training, and/or the like. The HBMs225may be disposed on the interposer210. For example, the HBMs225may be in direct contact with the interposer210, such that a bottom surface of the HBMs225may contact a top surface of the interposer210. The HBMs225may be in electrical communication with the interposer210. For example, the bottom surface of an HBM225may include electrical connections that may couple to respective electrical connections of the top surface of the interposer210. In some examples, the electrical connections may include bump bonds, electrical pins, and/or the like. The HBMs225may in some examples include second generation of high bandwidth memory (HBM2), second generation evolutionary high bandwidth memory (HBM2E), third generation of high bandwidth memory (HBM3), fourth generation of high bandwidth memory (HBM4), HBM with processing-in-memory, and/or the like.

The chip200may also include one or more chiplets230. The chiplets230may for example include functionality, including but not limited to, networking, input/output (I/O), a network interface card or a network interface controller (NIC) and/or the like. The chiplets230may be disposed on the interposer210. For example, the chiplets230may be in direct contact with the interposer210, such that a bottom surface of the chiplets230may contact a top surface of the interposer210. The chiplets230may be in electrical communication with the interposer210. For example, the bottom surface of a chiplet230may include electrical connections that may couple to respective electrical connections of the top surface of the interposer210. In some examples, the electrical connections may include bump bonds, electrical pins, and/or the like. The chiplets230may be configured to facilitate communications between the various components of the chip200. For example, in some examples the chiplets230may include network-on-chip logic. For example, the chiplets230may manage processing pipelines of processing elements either within or between computer chiplets220. In some examples, the chiplets230may be configured to facilitate communications between the chip200and external components.

The chip may also include one or more host CPUs235. The host CPUs235may be disposed on the substrate205. For example, the host CPUs235may be in direct contact with the substrate205, such that a bottom surface of the host CPUs235may contact a top surface of the substrate. The host CPUs235may be in electrical communication with the substrate205. For example, the bottom surface of a host CPU(s)235may include electrical connections that may couple to respective electrical connections of the top surface of the substrate205. In some examples, the electrical connections may include bump bonds, electrical pins, and/or the like. The host CPUs235may include logic to manage the various other components of the chip200. For example, the host CPUs235may be configured to execute artificial intelligence, machine learning, video processing, and/or the like.

The chip200may utilize 3D architecture, at least with respect to the computing chiplets220being stacked atop the random access memory chiplets215, and likewise the random access memory chiplets215being stacked atop the interposer210. The stacking of the computing chiplets220atop the random access memory chiplets215may allow for very low latency for communications between the computing chiplets220atop the random access memory chiplets215, which may enhance the processing capabilities of the chip200. Further, the implementation of various components on the interposer210(e.g., in a 2.5D architecture) may further enhance low latency across the chip200. For example, components may include an embedded silicon bridge, embedded metal connectors, passives, capacitors, chiplet-to-chiplet physical layer, and/or the like.

FIGS.3,4,5,6,7, and8depict various other examples of a chip implementing 3D architecture according to the present disclosure. For example,FIG.3depicts a chip with a similar 3D configuration as the chip200ofFIG.2, albeit with two host CPUs235positioned on the substrate205. Each host CPU235may be in electrical communication with the other entities of the chip300(e.g., via the substrate205). Thus, the host CPUs235may either share logic instructions (e.g., for a same program/application), or the host CPUs235may be distinct from one another (e.g., hosting different programs/applications for execution).

FIG.4depicts a chip400implementing a 3D architecture according to an example of the present disclosure. The chip400may have a similar 3D configuration as the chip200and chip300depicts inFIGS.2and3, respectively. The chip400includes network and host CPUs440. The chiplet and host CPUs440may be a combination of hardware and logic that is included in chiplets230and host CPUs235as described with reference toFIGS.2and3. The chiplet and host CPUs440may manage or facilitate communications between various entities of the chip400(e.g., managing processing pipelines within and between compute chiplets220), as well as communications between the chip400and external entities. The chiplet and host CPUs440may also include host processing logic (e.g., an executable program(s)/application(s)), and may instruct or manage the other entities of the chip400in executing the logic. The chiplet and host CPUs440may be positioned at the interposer210, and may be in electrical communication with the interposer210. Thus, the chiplet and host CPUs440may be in electrical communication with other entities of the chip400via the interposer210.

FIG.5depicts a chip500implementing a 3D architecture according to an example of the present disclosure. The chip500may have a similar configuration as chip200as described with reference toFIG.2. However, the chip500may include a host CPU chiplet235(also referred to herein as host CPU235) positioned on the interposer210, in lieu of a substrate layer as depicted inFIG.2. The host CPU235may be in electrical communication with the interposer210, such that the host CPU235may communicate with other entities of the chip500via the interposer210. The chip500may also include double data rate (DDR) memory545. The DDR memory545may be positioned atop the interposer210such that the DDR memory545is in electrical communication with the interposer210. The DDR memory545may be configured to electrically communicate with other entities of the chip500, such as for example the host CPU235. The DDR memory545may include volatile memory that may be configured to fetch data based on memory clock signals. In some examples, the DDR memory545may include Double Data Rate 2 (DDR2) memory, Double Data Rate 3 (DDR3) memory, Double Data Rate 4 (DDR4) memory, Double Data Rate 5 (DDR5) memory, Low-Power Double Data Rate (LPDDR), and/or the like. The DDR memory545may facilitate overall system memory of the chip500.

FIG.6depicts a chip600implementing a 3D architecture according to an example of the present disclosure. The chip600may have a configuration similar to the chip500as described with reference toFIG.5. However, the chip600may also include a host CPU235disposed atop a random access memory chiplet215. The host CPU235may be in electrical communication with the respective random access memory chiplet215(e.g., via a bottom surface of the host CPU235and a top surface of the random access memory chiplet215), and likewise the random access memory chiplet215may be in electrical communication with the interposer210(e.g., via a bottom surface of the random access memory chiplet215and a top surface of the interposer210). The host CPU235may thus be configured for electrical communication with other entities of the chip600(e.g., an electrical signal may be sent from the host CPU235, to the random access memory chiplet215, to the interposer210, and then to another entity of the chip600).

FIG.7depicts a chip700implementing a 3D architecture according to an example of the present disclosure. The chip700may have a configuration similar to chip500as described with reference toFIG.5. The chip may include two (or more) host CPUs235positioned on the interposer210. Each host CPU235may be electrical communication with the other entities of the chip700(e.g., via the interposer210). Thus, the host CPUs235may either share logic instructions (e.g., for a same program), or they may be distinct from one another (e.g., hosting different programs for execution).

FIG.8depicts a chip800implementing a 3D architecture according to an example of the present disclosure. The chip800may have a configuration similar to chip700as described with reference toFIG.7. The chip800may also include host CPUs235disposed atop respective random access memory chiplets215. The host CPUs235may be in electrical communication with the respective random access memory chiplet215(e.g., via a bottom surface of the host CPU235and a top surface of the random access memory chiplet215), and likewise the random access memory chiplet215may be in electrical communication with the interposer210(e.g., via a bottom surface of the random access memory chiplet215and a top surface of the interposer210). The host CPU235may thus be configured for electrical communication with other entities of the chip800(e.g., an electrical signal may be sent from the host CPU235, to the random access memory chiplet215, to the interposer210, and then to another entity of the chip800). Thus, the host CPUs235may either share logic instructions (e.g., for a same program/application), or they may be distinct from one another (e.g., hosting different programs/applications for execution).

While the chips described with reference toFIGS.2,3,4,5,6,7, and8provide particular examples, the disclosure provided herein is not limited to these examples. For example, whileFIGS.2,3,4,5,6,7, and8depict various numbers of chip components, in other examples a chip may include less or more of those components implementing the architecture described herein. For example, consideringFIG.2, the chip200may include less or more than the HBM3 chiplets225than the 12 HBM3 chiplets225depicted. The 3D stacking architecture may enable integration of different functionalities (e.g., cryptography, security input/output (IO), and/or the like) while achieving higher performance. The 3D stacking architecture may also increase memory and/or processing capacity for a chip. Additionally, in some examples, the various chip components of the chip may include different locations compared to those shown inFIGS.2,3,4,5,6,7, and8.

FIG.9depicts a process900according to an example of the present disclosure. The process900may be implemented by a chip, such as for example chip200, chip300, chip400, chip500, chip600, chip700, chip800ofFIGS.2-8, respectively. At Step905, at least one electrical signal from a computing chiplet (e.g., computing chiplet220) may be transmitted. At Step910, the at least one electrical signal may be transferred or transmitted from the computing chiplet to a random access memory chiplet (e.g., random access memory chiplet215), where the computing chiplet may be stacked atop the random access memory chiplet, thereby forming a three-dimensional stacked integrated circuit. In some examples, a bottom surface of the computing chiplet may contact a top surface of the random access memory chiplet. In some examples, the bottom surface of the computing chiplet may include electrical connections that couple to respective electrical connections on the top surface of the random access memory chiplet. In some examples, three-dimensional stacking may include placing the computing chiplet atop the random access memory chiplet, or vice versa, such that the width/length dimensions of the computing chiplet may be configured/run parallel to the width/length dimensions of the random access memory chiplet. In some other examples, the at least one electrical signal may be transferred or transmitted from the random access memory to another component of the integrated circuit via an interposer layer. For example, a bottom surface of the random access memory chiplet may include electrical connections that couple to respective electrical connections of a top surface of the interposer layer. In some examples, the another component may be stacked on the interposer layer. In some examples, the another component of the integrated circuit may be referred to herein as a second component of the integrated circuit. In some examples, the another component may include another random access memory chiplet, a host CPU, a networking chiplet, or a high bandwidth memory chiplet. In some examples, the another random access memory chiplet may be referred to herein as a second random access memory chiplet.

FIG.10is a block diagram of an exemplary computing device30which may incorporate a chip described herein, such as chip200, chip300, chip400, chip500, chip600, chip700, chip800ofFIGS.2,3,4,5,6,7, and8respectively. In an example, the computing device30may be a server or communication device configured to provide AI functions and/or ML functions.

As shown inFIG.10, the computing device30may include a chip32, non-removable memory44, removable memory46, a speaker/microphone38, a keypad40, a camera54, a display/touchpad/indicators42, a power source48, a global positioning system (GPS) chipset50, and other peripherals52. The computing device30may also include communication circuitry, such as a transceiver34and a transmit/receive element36. It will be appreciated the computing device30may include any sub-combination of the foregoing elements while remaining consistent with an embodiment.

The chip32may be an integrated circuit, and in particular, for example, an ASIC. The chip32may be an example of chip200, chip300, chip400, chip500, chip600, chip700, chip800ofFIGS.2,3,4,5,6,7, and8. The chip32may be capable of various functions designed for the computing device30. For example, the chip32may be configured to perform AI training and/or ML training, to process output from a AI/ML model, inference and video processing, and/or the like. In other examples, the chip32may perform other functions or tasks.

In some examples, the chip32may execute computer-executable instructions stored in the memory (e.g., memory44and/or memory46) of the computing device30in order to perform the various required functions of the computing device30. For example, the chip32may perform signal coding, data processing, power control, input/output processing, and/or any other functionality that enables the computing device30to operate in a wireless or wired environment. In some examples, the chip32may run application-layer programs (e.g., browsers) and/or radio access-layer (RAN) programs and/or other communications programs. In some examples, the chip32may also perform security operations such as authentication, security key agreement, and/or cryptographic operations, such as at the access-layer and/or application layer for example.

The chip32may be coupled to communication circuitry (e.g., transceiver34and transmit/receive element36). In some examples, the chip32, through the execution of computer executable instructions, may control the communication circuitry in order to cause the computing device30to communicate with other computing devices via the network to which it is connected.

The transmit/receive element36may be configured to transmit signals to, or receive signals from, other computing devices or networking equipment. For example, in an embodiment, the transmit/receive element36may be an antenna configured to transmit and/or receive radio frequency (RF) signals. The transmit/receive element36may support various networks and air interfaces, such as wireless local area network (WLAN), wireless personal area network (WPAN), cellular, and the like. In yet another embodiment, the transmit/receive element36may be configured to transmit and receive both RF and light signals. It will be appreciated that the transmit/receive element36may be configured to transmit and/or receive any combination of wireless or wired signals.

The transceiver34may be configured to modulate the signals that are to be transmitted by the transmit/receive element36and to demodulate the signals that are received by the transmit/receive element36. As noted above, the computing device30may have multi-mode capabilities. Thus, the transceiver34may include multiple transceivers for enabling the computing device30to communicate via multiple radio access technologies (RATs), such as universal terrestrial radio access (UTRA) and Institute of Electrical and Electronics Engineers (IEEE 802.11), for example.

The chip32may access information from, and store data in, any type of suitable memory, such as the non-removable memory44and/or the removable memory46. For example, the chip32may store session context in its memory, as described above. The non-removable memory44may include RAM, ROM, a hard disk, or any other type of memory storage device. The removable memory46may include a subscriber identity module (SIM) card, a memory stick, a secure digital (SD) memory card, and the like. In other embodiments, the chip32may access information from, and store data in, memory that is not physically located on the computing device30, such as on a server or a home computer.

The chip32may receive power from the power source48and may be configured to distribute and/or control the power to the other components in the computing device30. The power source48may be any suitable device for powering the computing device30. For example, the power source48may include one or more dry cell batteries (e.g., nickel-cadmium (NiCd), nickel-zinc (NiZn), nickel metal hydride (NiMH), lithium-ion (Li-ion), etc.), solar cells, fuel cells, and the like.

The chip32may also be coupled to the GPS chipset50, which may be configured to provide location information (e.g., longitude and latitude) regarding the current location of the computing device30. It will be appreciated that the computing device30may acquire location information by way of any suitable location-determination method while remaining consistent with an exemplary embodiment.

Some portions of this description describe the exemplary aspects of the present disclosure in terms of applications and/or symbolic representations of operations on information. These application descriptions and representations are commonly used by those skilled in the data processing arts to convey the substance of their work effectively to others skilled in the art. These operations, while described functionally, computationally, or logically, are understood to be implemented by computer programs or equivalent electrical circuits, microcode, or the like. Furthermore, it has also proven convenient at times, to refer to these arrangements of operations as components, without loss of generality. The described operations and their associated components may be embodied in software, firmware, hardware, or any combinations thereof.

Any of the steps, operations, or processes described herein may be performed or implemented with one or more hardware or software components, alone or in combination with other devices. In one exemplary aspect of the present disclosure, a software component may be implemented with a computer program product comprising a computer-readable medium containing computer program code, which may be executed by a computer processor for performing any or all of the steps, operations, or processes described.

Some exemplary aspects of the present disclosure also may relate to a product that is produced by a computing process described herein. Such a product may comprise information resulting from a computing process, where the information is stored on a non-transitory, tangible computer readable storage medium and may include any example aspect of a computer program product or other data combination described herein.

The language used in the specification has been principally selected for readability and instructional purposes, and it may not have been selected to delineate or circumscribe the inventive subject matter. It is therefore intended that the scope of the patent rights be limited not by this detailed description, but rather by any claims that issue on an application based hereon. Accordingly, the disclosure of the exemplary aspects is intended to be illustrative, but not limiting, of the scope of the patent rights, which is set forth in the following claims.