Semiconductor devices with through via electrodes, methods of fabricating the same, memory cards including the same, and electronic systems including the same

A semiconductor device includes a via electrode penetrating a substrate and a back-side molding layer covering a back-side surface of the substrate. The back-side molding layer contacts a sidewall of a back-side end portion of the via electrode, which is a portion of the via electrode that protrudes from the back-side surface of the substrate.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C 119(a) to Korean Application No. 10-2013-0097294, filed on Aug. 16, 2013, in the Korean intellectual property Office, which is incorporated herein by reference in its entirety as set forth in full.

BACKGROUND

1. Technical Field

Embodiments of the present disclosure relate to semiconductor devices and, more particularly, to semiconductor devices with through via electrodes, methods of fabricating the same, memory cards including the same and electronic systems including the same.

2. Related Art

Semiconductor devices employed in electronic systems may include various electronic circuit elements. Electronic circuit elements may be integrated in and/or on a semiconductor substrate to form a semiconductor device (also, referred to as a semiconductor chip or a semiconductor die). Semiconductor memory chips may also be employed in electronic systems. Before semiconductor devices, including semiconductor memory chips, are employed in an electronic system, the semiconductor devices may be encapsulated to form a package. These semiconductor packages may be employed in the electronic systems, for example, computers, mobile systems or data storage media.

As electronic systems such as mobile systems, which include smart phones, become lighter and smaller, the semiconductor packages employed in the mobile systems are increasingly scaled down. Thus, stack packages, each of which includes a plurality of stacked semiconductor chips, are increasingly in demand with the development of multi-functional and high capacity semiconductor packages. In this regard, there have been efforts to reduce the thickness and the size of the stack packages to provide thin and small stack packages. In addition, through silicon via (TSV) electrodes penetrating the semiconductor chips have been proposed to realize interconnection structures that electrically couple the semiconductor chips to an external device.

SUMMARY

Various embodiments are directed to semiconductor devices with through via electrodes, methods of fabricating the same, memory cards including the same, and electronic systems including the same.

According to some embodiments, a semiconductor device includes a first substrate, a first conductive via electrode extending from a front side surface of the first substrate toward a backside surface of the first substrate to penetrate the first substrate, and a first backside molding layer covering the backside surface of the first substrate and contacting sidewall of a backside end portion of the first conductive via electrode. The first backside molding layer exposes a top surface of the backside end portion of the first conductive via electrode.

According to further embodiments, a semiconductor device includes a first chip, a second chip, and a package molding layer. The first chip includes a first substrate, a first conductive via electrode extending from a front side surface of the first substrate toward a backside surface of the first substrate to penetrate the first substrate, and a first backside molding layer covering the backside surface of the first substrate and contacting a sidewall of a backside end portion of the first conductive via electrode. The second chip includes a second substrate, a second conductive via electrode extending from a front side surface of the second substrate toward a backside surface of the second substrate to penetrate the second substrate, and a second backside molding layer covering the backside surface of the second substrate and contacting a sidewall of a backside end portion of the second conductive via electrode. The second chip is stacked on the first chip such that the second conductive via electrode is electrically connected to the first conductive via electrode. The package molding layer covers sidewalls of the first and second chips and contacts the first and second backside molding layers.

According to further embodiments, a method of fabricating a semiconductor device includes forming a conductive via electrode extending from a front side surface of the substrate toward a backside surface of the substrate to penetrate the substrate. The conductive via electrode is formed to include a backside end portion that protrudes from the backside surface of the substrate. An initial backside molding layer is formed on the backside surface of the substrate to cover the protruded backside end portion of the conductive via electrode. The initial backside molding layer is ground to form a backside molding layer exposing the backside end portion of the conductive via electrode.

According to further embodiments, a memory card includes a semiconductor device. The semiconductor device includes a first substrate, a first conductive via electrode extending from a front side surface of the first substrate toward a backside surface of the first substrate to penetrate the first substrate, and a first backside molding layer covering the backside surface of the first substrate and contacting sidewall of a backside end portion of the first conductive via electrode. The first backside molding layer exposes a top surface of the backside end portion of the first conductive via electrode.

According to further embodiments, a memory card includes a semiconductor device. The semiconductor device includes a first chip, a second chip, and a package molding layer. The first chip includes a first substrate, a first conductive via electrode extending from a front side surface of the first substrate toward a backside surface of the first substrate to penetrate the first substrate, and a first backside molding layer covering the backside surface of the first substrate and contacting a sidewall of a backside end portion of the first conductive via electrode. The second chip includes a second substrate, a second conductive via electrode extending from a front side surface of the second substrate toward a backside surface of the second substrate to penetrate the second substrate, and a second backside molding layer covering the backside surface of the second substrate and contacting a sidewall of a backside end portion of the second conductive via electrode. The second chip is stacked on the first chip such that the second conductive via electrode is electrically connected to the first conductive via electrode. The package molding layer covers sidewalls of the first and second chips and contacts the first and second backside molding layers.

According to further embodiments, an electronic system includes a semiconductor device. The semiconductor device includes a first substrate, a first conductive via electrode extending from a front side surface of the first substrate toward a backside surface of the first substrate to penetrate the first substrate, and a first backside molding layer covering the backside surface of the first substrate and contacting sidewall of a backside end portion of the first conductive via electrode. The first backside molding layer exposes a top surface of the backside end portion of the first conductive via electrode.

According to further embodiments, an electronic system includes a semiconductor device. The semiconductor device includes a first chip, a second chip, and a package molding layer. The first chip includes a first substrate, a first conductive via electrode extending from a front side surface of the first substrate toward a backside surface of the first substrate to penetrate the first substrate, and a first backside molding layer covering the backside surface of the first substrate and contacting a sidewall of a backside end portion of the first conductive via electrode. The second chip includes a second substrate, a second conductive via electrode extending from a front side surface of the second substrate toward a backside surface of the second substrate to penetrate the second substrate, and a second backside molding layer covering the backside surface of the second substrate and contacting a sidewall of a backside end portion of the second conductive via electrode. The second chip is stacked on the first chip such that the second conductive via electrode is electrically connected to the first conductive via electrode. The package molding layer covers sidewalls of the first and second chips and contacts the first and second backside molding layers.

DETAILED DESCRIPTION OF EMBODIMENTS

Embodiments of the present invention provide semiconductor devices including via electrodes and methods of fabricating the same. A semiconductor device according to an embodiment may include a back-side molding layer disposed on a back-side surface of a semiconductor substrate, which is exposed together with back-side end portions of via electrodes penetrating the semiconductor substrate. Thus, the back-side molding layer may prevent the back-side end portions of the via electrodes on the back side of the substrate from being damaged. The back-side molding layer may include substantially the same material as a package molding layer that protects sidewalls of a semiconductor chip including the semiconductor substrate. Accordingly, the back-side molding layer may prevent the package molding layer from peeling off from the semiconductor chip. As a result, a package failure is avoided.

It will also be understood that when an element is referred to as being “on”, “above”, “below”, or “under” another element, it can be directly “on”, “above”, “below”, or “under” the other element, respectively, or intervening elements may also be present. Accordingly, the terms such as “on”, “above”, “below”, or “under” which are used herein are for the purpose of describing particular embodiments only and are not intended to be limiting.

It will be further understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements or layers should be interpreted in a similar fashion. The semiconductor substrate may have an active layer corresponding to a region where transistors and internal interconnection lines constituting electronic circuits are integrated, and semiconductor chips may be obtained by separating the semiconductor substrate into a plurality of pieces.

The semiconductor chips may correspond to memory chips or logic chips. The memory chips may include dynamic random access memory (DRAM) circuits, static random access memory (SRAM) circuits, flash memory circuits, magnetic random access memory (MRAM) circuits, resistive random access memory (ReRAM) circuits, ferroelectric random access memory (FeRAM) circuits, or phase change random access memory (PCRAM) circuits, which are integrated on and/or in the semiconductor substrate. The logic chips may include logic circuits which are integrated on and/or in the semiconductor substrate. In some cases, the term “semiconductor substrate” used herein may be construed as a semiconductor chip or a semiconductor die in which integrated circuits are formed.

FIG. 1illustrates a semiconductor device according to an embodiment. The semiconductor device includes via electrodes200that extend from a front-side surface101of a semiconductor substrate100toward a back-side surface104of the semiconductor substrate100. That is, the via electrodes200may vertically penetrate the semiconductor substrate100. The semiconductor substrate100may be a silicon substrate and may have a wafer form or a separate chip form. The front-side surface101of the semiconductor substrate100may correspond to a surface of an active layer where integrated circuits are formed. The back-side surface104of the semiconductor substrate100may be a surface opposite to the front-side surface101with respect to the body of the semiconductor substrate100. Circuit elements such as transistors110constituting an integrated circuit may be formed in and on the active layer, and a dielectric layer130and internal interconnection structures140formed in the dielectric layer130may be disposed over the front-side surface101.

Each of the internal interconnection structures140may include an interconnection line and a connection via to provide an electrical connection structure. The internal interconnection structures140electrically couple the via electrodes200to corresponding connection pads150. First conductive bumps160are disposed on corresponding connection pads150to act as outer connection terminals for connecting the semiconductor device to an external device. Thus, the first conductive bumps160are electrically coupled to the corresponding via electrodes200.

A passivation layer170is disposed on a surface of the dielectric layer130to expose the connection pads150. As illustrated inFIG. 1, the via electrodes200are electrically coupled to the first conductive bumps160through the internal interconnection structures140and the connection pads150.

In another embodiment, the via electrodes200are directly connected to the first conductive bumps160, or each via electrode200and its corresponding first conductive bump160may constitute a unitary body. The first conductive bumps160may be formed of a metal material such as a copper (Cu) material.

Conductive adhesive layers180are disposed on corresponding first conductive bumps160. The conductive adhesive layers180may be provided to improve an adhesive strength between the first conductive bumps160and external connection terminals. The conductive adhesive layers180may be formed of a solder layer. An interfacial layer may be disposed between the first conductive bumps160and the conductive adhesive layers180. The interfacial layer may include a wetting layer such as a nickel layer or an oxidation resistant material layer such as a gold layer.

The via electrodes200may correspond to through via electrodes such as through silicon vias (TSVs) or through electrodes. The via electrodes200may be formed of a metal material. The via electrodes200may be formed of a gallium (Ga) material, an indium (In) material, a tin (Sn) material, a silver (Ag) material, a copper (Cu) material, a mercury (Hg) material, a bismuth (Bi) material, a lead (Pb) material, a gold (Au) material, a zinc (Zn) material, an aluminum (Al) material, or an alloy thereof.

Back-side end portions210of the via electrodes200may protrude from the back-side surface104of the semiconductor substrate100. In an embodiment, the back-side end portions210of the via electrodes200penetrate a back-side molding layer301that is formed on the back-side surface104to protect the back-side surface104of the semiconductor substrate100. That is, the back-side molding layer301may surround sidewalls of the back-side end portions210of the via electrodes200to electrically insulate the back-side end portions210from each other.

The back-side molding layer301may be formed by performing a back-side molding process for covering the back-side surface104of the semiconductor substrate100with an epoxy molding compound (EMC) material. Thus, the back-side molding layer301can be formed at a low cost. Furthermore, the back-side molding layer301may be more solid and harder than an oxide layer or a polyimide layer that is used as a back-side passivation layer. Thus, the back-side molding layer301may prevent the back-side end portions210of the via electrodes200from being deformed during a grinding process for exposing the back-side end portions210of the via electrodes200.

The back-side end portions210of the via electrodes200are covered with second conductive bumps360acting as outer connection terminals. The second conductive bumps360may be formed of a metal material such as a copper material. The first conductive bumps160disposed on the front-side surface101of the semiconductor substrate100are electrically coupled to the second conductive bumps360disposed on the back-side surface104of the semiconductor substrate100through the via electrodes200.

FIGS. 2 to 5are cross-sectional views illustrating a method of fabricating the semiconductor device shown inFIG. 1according to an embodiment of the present invention.

Referring toFIG. 2, a plurality of transistors110are formed in an active layer which is adjacent to a front-side surface101of a semiconductor substrate100. An interlayer insulation layer120is formed on the front-side surface101of the semiconductor substrate100to cover the transistors110. After that, via electrodes200are formed to penetrate the interlayer insulation layer120and to extend into the semiconductor substrate100. That is, the via electrodes200are formed to extend from the front-side surface101of the semiconductor substrate100toward an initial back-side surface103of the semiconductor substrate100.

The via electrodes200may be formed using a process of forming through silicon vias (TSVs) at a wafer level. In particular, the interlayer insulation layer120and the semiconductor substrate100are etched to form via holes205that have openings at the front-side surface101and extend toward the initial back-side surface103. A conductive material such as a copper material then fills the via holes205. As a result, the via electrodes200are formed in each one of the via holes205.

The via holes205may be formed to have different depths from each other depending on their locations in the semiconductor substrate100. Thus, the via electrodes200may also be formed to have different vertical lengths according to their locations in the semiconductor substrate100. InFIG. 2, the via electrodes200include relatively short via electrodes201and relatively long via electrodes203. Although not shown in the drawings, an insulation liner may be formed between the via electrodes200and the semiconductor substrate100.

Subsequently, a dielectric layer130and internal interconnection structures140disposed in the dielectric layer130are formed on the interlayer insulation layer120and the via electrodes200. Connection pads150are formed in an upper portion of the dielectric layer130to be coupled to corresponding internal interconnection structures140.

A passivation layer170for exposing part of the connection pads150is formed on the dielectric layer130and the connection pads150. After that, first conductive bumps160are formed on each of the exposed connection pads150. Conductive adhesive layers180are formed on each of the first conductive bumps160. The processes described above may be performed while the semiconductor substrate100is oriented such that the initial back-side surface103is provided as the bottom surface of the substrate100and the front-side surface101is provided as the top surface of the substrate100. After forming the conductive adhesive layers180over the semiconductor substrate100, the semiconductor substrate100is turned over so that the initial back-side surface103of the semiconductor substrate100is provided as the top of the substrate100and the front-side surface101is provided as the bottom surface of the substrate100, as shown inFIG. 2.

Referring toFIG. 3, a process for removing a portion of the back side of the semiconductor substrate100by a predetermined thickness R is performed on the initial back-side surface103to expose back-side end portions210of the via electrodes200. The process for removing the portion of the back side of the semiconductor substrate100may be a dry etch process such that the back-side end portions210of the via electrodes200protrude from a back-side surface104of the etched semiconductor substrate100. In an embodiment, since the via electrodes200are formed to have different vertical lengths depending on their locations in the semiconductor substrate100, lengths of the back-side end portions210protruding from the back-side surface104may also be different from each other.

Referring toFIG. 4, an initial back-side molding layer300is formed to cover the back-side surface104of the semiconductor substrate100and the back-side end portions210of the via electrodes200. The initial back-side molding layer300may be formed at a wafer level using a molding apparatus. The initial back-side molding layer300may be formed of an epoxy molding compound (EMC) material. The initial back-side molding layer300may be formed to have a sufficient thickness to cover the back-side end portions210of the via electrodes200.

In an embodiment, the initial back-side molding layer300is formed to have a thickness of about 100 micrometers to about 150 micrometers. Since the initial back-side molding layer300is formed using the molding apparatus, a surface of the initial back-side molding layer300may have a flat, even profile rather than an uneven profile. The initial back-side molding layer300may be formed of an EMC material which is relatively harder than an oxide layer or a polyimide layer. Thus, the initial back-side molding layer300may reinforce the original shapes of the top surfaces of the back-side end portions210′ (seeFIG. 5) of the via electrodes200even though the initial back-side molding layer300and the vertical length of the back-side end portions210are ground in a subsequent process. That is, the initial back-side molding layer300may prevent the back-side end portions210of the via electrodes200from being deformed or broken during a grinding process that is performed to expose the back-side end portions210of the via electrodes200.

Referring toFIG. 5, the initial back-side molding layer300and the back-side end portions210are ground to form a back-side molding layer301that exposes top surfaces209of ground back-side end portions210′ of the via electrodes200. The grinding process is indicated by “G” inFIG. 5. After the initial back-side molding layer300is ground in the grinding process G, a top surface of the back-side molding layer301may be substantially flat. The back-side end portions210of the via electrodes200are partially removed during the back grinding process G. As a result, the via electrodes200have substantially the same length after the back grinding process G is performed.

As described above, since the initial back-side molding layer300may be formed of the EMC material, the initial back-side molding layer300may prevent the top surfaces of the back-side end portions210′ of the via electrodes200from being deformed or broken during the back grinding process G. In an embodiment, the initial back-side molding layer300and the back-side end portions210may be planarized using a chemical mechanical polishing (CMP) process instead of the grinding process G.

After performing the grinding process G, second conductive bumps (360ofFIG. 1) may be formed on each of the ground back-side end portions210′ of the via electrodes200.

After the via electrodes200penetrating the semiconductor substrate100are formed at a wafer level, the semiconductor substrate100may be separated into a plurality of semiconductor chips using a die sawing process. Then, at least two semiconductor chips may be stacked to form a stack package. Alternatively, after the via electrodes200penetrating the semiconductor substrate100are formed at a wafer level, a plurality of semiconductor substrates100may be stacked at a wafer level, and then the plurality of stacked semiconductor substrates100may be cut using a die sawing process to form a plurality of stack packages. As a result, semiconductor devices are formed as stack packages.

FIG. 6is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present invention.

Referring toFIG. 6, the semiconductor device has a stack package form in which a plurality of semiconductor chips1000,2000,3000,4000, and5000is stacked. An underfill layer (or an insulating layer or an adhesive layer) may be interposed between the stacked chips. At least one of the semiconductor chips1000,2000,3000,4000, and5000includes a semiconductor substrate100and via electrodes200penetrating the semiconductor substrate100. InFIG. 6, the same reference numerals as used inFIGS. 1 to 5are used to denote the same elements as inFIGS. 1 to 5.

The semiconductor device includes the first semiconductor chip1000, the second semiconductor chip2000stacked on the first semiconductor chip1000, and a package molding layer400covering sidewalls of the first and second semiconductor chips1000and2000. The package molding layer400may act as a protective layer. In an embodiment, the first and second semiconductor chips1000and2000are configured to have the same integrated circuit that executes substantially the same function. In another embodiment, the first and second semiconductor chips1000and2000are configured to have different integrated circuits that execute different functions.

The first semiconductor chip1000includes a first semiconductor substrate1100, a plurality of first via electrodes1200penetrating the first semiconductor substrate1100, and a first back-side molding layer1301covering a back-side surface of the first semiconductor substrate1100and surrounding external surfaces of sidewalls of back-side end portions of the first via electrodes1200. The first back-side molding layer1301may be formed to expose top surfaces of the back-side end portions of the first via electrodes1200. The first back-side molding layer1301may be formed by molding an epoxy molding compound (EMC) material.

The second semiconductor chip2000may have substantially the same configuration as the first semiconductor chip1000. That is, the second semiconductor chip2000includes a second semiconductor substrate2100, a plurality of second via electrodes2200penetrating the second semiconductor substrate2100, and a second back-side molding layer2301covering a back-side surface of the second semiconductor substrate2100and surrounding external surfaces of sidewalls of back-side end portions of the second via electrodes2200. The second back-side molding layer2301may be formed to expose top surfaces of the back-side end portions of the second via electrodes2200. The second back-side molding layer2301may be formed by molding the EMC material. The second semiconductor chip2000is stacked on the first semiconductor chip1000such that the second via electrodes2200are electrically coupled to the first via electrodes1200.

The package molding layer400may function as a protective layer that protects the first and second semiconductor chips1000and2000. The package molding layer400may be formed of substantially the same material as the first and second back-side molding layers1301and2301. The package molding layer400may be formed by molding the EMC material. Since the package molding layer400, the first back-side molding layer1301, and the second back-side molding layer2301are formed of substantially the same material, adhesion between the package molding layer400and the first and second back-side molding layers1301and2301may be improved.

The package molding layer may be attached to only sidewalls of a stacked structure including the first and second semiconductor substrates to constitute a conventional stacked package having a fan-out package form. In such a case, because the package molding layer is attached to only the sidewalls of the stacked structure, an adhesive strength between the stacked structure and the package molding layer may be degraded.

However, according to an embodiment, the first back-side molding layer1301formed of the same material as the package molding layer400is disposed between the first and second semiconductor chips1000and2000. In addition, a back-side surface of the second semiconductor chip2000is covered with the second back-side molding layer2301formed of the same material as the package molding layer400. Thus, the first and second back-side molding layers1301and2301may be strongly combined with the package molding layer400to prevent the package molding layer400from being delaminated from the sidewalls of the stacked structure.

The third semiconductor chip3000may be additionally disposed on a front-side surface of the first semiconductor chip1000. That is, the third semiconductor chip3000is disposed opposite to the second semiconductor chip2000with respect to the first semiconductor chip1000. The third semiconductor chip3000includes a third semiconductor substrate3100and a plurality of third via electrodes3200penetrating the third semiconductor substrate3100. The third via electrodes3200are electrically coupled to the first via electrodes1200.

Third conductive bumps3160are disposed on a front-side surface of the third semiconductor substrate3100that is opposite to the first semiconductor chip1000. The third conductive bumps3160act as outer connection terminals that electrically couple the stacked package to another substrate or a mother board.

The third semiconductor chip3000may have a greater width than the first semiconductor chip1000. Since the third semiconductor chip3000is wider than the first semiconductor chip1000, when the first semiconductor chip1000is mounted on a back-side surface of the third semiconductor chip3000, edges of the third semiconductor chip3000may laterally extend beyond the sidewalls of the first semiconductor chip1000. The package molding layer400on the sidewalls of the first semiconductor chip1000may be flush with the edges of the third semiconductor chip3000. That is, the package molding layer400may be molded such that outer sidewall surfaces of the package molding layer400are vertically aligned with sidewall surfaces of the third semiconductor chip3000. In an embodiment, the third semiconductor chip3000may be replaced with an interposer, a printed circuit board (PCB), or a dummy substrate, which provides only electrical interconnection without any functions of a semiconductor chip.

The fourth semiconductor chip4000having substantially the same configuration as the second semiconductor chip2000may be additionally stacked on a back-side surface of the second semiconductor chip2000. Furthermore, the fifth semiconductor chip5000may be stacked on the fourth semiconductor chip4000. The fifth semiconductor chip5000may have substantially the same function as the first or second semiconductor chip1000or2000. Alternatively, the fifth semiconductor chip5000may have a different function from the first and second semiconductor chips1000and2000.

In an embodiment, the fifth semiconductor chip5000corresponding to a topmost semiconductor chip may not include the via electrodes as illustrated inFIG. 6. In another embodiment, the fifth semiconductor chip5000may include via electrodes that are substantially the same as those of the first or second semiconductor chip1000or2000. The package molding layer400may extend to cover and protect sidewalls of the fourth and fifth semiconductor chips4000and5000. A top surface5001of the fifth semiconductor chip5000that is on an opposite side to a side attached to the fourth semiconductor chip4000may be exposed to enhance heat radiation efficiency of the stacked package.

FIG. 7is a block diagram illustrating an electronic system including a semiconductor device according to an embodiment of the present invention. The semiconductor device is provided in the form of a memory card1800. The memory card1800includes a memory1810and a memory controller1820.

The memory1810may include at least one of nonvolatile memory devices to which the packaging technology according to an embodiment of the present invention is applied. The memory controller1820may control operations for storing data in the memory1810and reading out data stored in the memory1810in response to a read/write request from a host1830.

FIG. 8is a block diagram illustrating another electronic system including a semiconductor device according to an embodiment of the present invention. The electronic system2710includes a controller2711, an input/output unit2712, and a memory2713. The controller2711, the input/output unit2712, and the memory2713are coupled with one another through a bus2715providing a path through which data moves.

The controller2711may include at least one of at least one microprocessor, at least one digital signal processor, at least one microcontroller, and logic devices capable of performing the same functions as these components. The controller2711or the memory2713may include at least one semiconductor device according to an embodiment of the present invention. The input/output unit2712may include at least one of a keypad, a keyboard, a display device, a touch screen, and so forth.

The memory2713may store data and/or commands to be executed by the controller2711. The memory2713may include a volatile memory device such as a DRAM and/or a nonvolatile memory device such as a flash memory. The flash memory may be mounted to an information processing system such as a mobile terminal or a desk top computer. The flash memory may constitute a solid state disk (SSD). In this case, the electronic system2710may stably store a large amount of data in a flash memory system.

The electronic system2710may further include an interface2714configured to transmit and receive data to and from a communication network. The interface2714may have a wired or wireless configuration. The interface2714may include an antenna or a wired or wireless transceiver.

The electronic system2710may be realized as a mobile system, a personal computer, an industrial computer or a logic system performing various functions. The mobile system may be any one of a personal digital assistant (PDA), a portable computer, a tablet computer, a mobile phone, a smart phone, a wireless phone, a laptop computer, a memory card, a digital music system, and an information transmission/reception system.

When the electronic system2710is used as equipment capable of performing wireless communication, the electronic system2710may be used in a communication system such as one of CDMA (code division multiple access), GSM (global system for mobile communications), NADC (north American digital cellular), E-TDMA (enhanced-time division multiple access), WCDAM (wideband code division multiple access), CDMA2000, LTE (long term evolution), and Wibro (wireless broadband Internet).

Embodiments of the present invention have been disclosed above for illustrative purposes. Those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the present invention as disclosed in the accompanying claims.