Common template for electronic article

One or more techniques or systems for incorporating a common template into a system on chip (SOC) design are provided herein. For example, a common template mask set is generated based on a first set of polygon positions from a first vendor and a second set of polygon positions from a second vendor. A third party creates a third party SOC design using a set of design rules generated based on the common template mask set. The common template is fabricated based on the third party SOC design using the common template mask set. Because the common template is formed using the common template mask set and because the common template mask set is based on polygon positions from both the first vendor and the second vendor, a part can be connected to the SOC regardless of whether the part is sourced from the first vendor or the second vendor.

BACKGROUND

Generally, an electronic article such as a system on chip (SOC) is associated with an interface that enables the SOC to electrically connect with a part, such as a dynamic random access memory (DRAM). Routinely, however, there are multiple vendors available to provide the part, where the part varies somewhat from vendor to vendor such that the manner or mechanism for electrically connecting the part to the SOC varies depending upon the vendor chosen to supply the part. Accordingly, different interfaces are generally required to electrically connect the part to the SOC when different vendors are used. That is, a first interface is needed to electrically connect the part to the SOC when the part is obtained from a first vendor and a second interface is need to electrically connect the part to the SOC where the part is obtained from a second vendor. Generally, an interface comprises one or more sets of features. A mask of a set of masks is typically used to form, on the SOC, a set of features of the sets of features. For example, where vendor A is selected to provide DRAM A, a first set of masks ‘A’ comprising a first mask A, a second mask A, and a third mask A is used to form an interface A compatible with the DRAM A. The first mask A is used to form a first set of features A within the interface A, the second mask A is used to form a second set of features A within the interface A, and the third mask A is used to form a third set of features A within the interface A. When a switch is made from DRAM A to DRAM B provided by vendor B, a second set of masks ‘B’ comprising a first mask B, a second mask B, and a third mask B is required to fabricate interface B on the SOC such that the SOC is compatible with the DRAM B. The first mask B is used to form a first set of features B within the interface B, the second mask B is used to form a second set of features B within the interface B, and the third mask B is used to form a third set of features B within the interface B. It will be appreciated that the first set of masks ‘A’ is specific to vendor A and cannot be used to fabricate interface B. Similarly, the second set of masks ‘B’ is specific to vendor B and cannot be used to fabricate interface A.

SUMMARY

This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to be an extensive overview of the claimed subject matter, identify key factors or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

One or more embodiments of techniques or systems for incorporating a common template into an electronic article design, such as a system on chip (SOC) design, are provided herein. It will be appreciated that while SOC and the like are substantially referred to herein, the instant application is not to be so limited. That is, the instant application, including the scope of the appended claims, is not necessarily limited to a SOC, a SOC design, etc. Rather, more than merely a SOC, a SOC design, etc. are within the contemplated scope of the present disclosure. Generally, a vendor specific interface is an interface that is formed on a SOC and that enables the SOC to mate or electrically connect with a part, such as a DRAM, from a particular vendor, where the vendor specific interface would not allow the SOC to electrically connect to the part if the part were obtained from a different vendor. The vendor specific interface is, for example, fabricated using a set of one or more masks and comprises one or more sets of corresponding features. According to some aspects provided herein, the SOC is designed such that at least a portion of the vendor specific interface fabricated on the SOC is standardized across one or more vendors. Because at least a portion of the vendor specific interface fabricated on the SOC is standardized across one or more vendors, the vendor specific interface is at time merely referred to as an interface, as opposed to a vendor specific interface.

The standardized portion of the interface is the same regardless of the vendor selected to provide the part, or rather is the same for at least two vendors. The standardized portion of the interface is standardized because a same set of masks is used to fabricate the standardized portion on the SOC. In some embodiments, the standardized portion of the interface is regarded as a common template. Similarly, the same set of masks used to fabricate the standardized portion on the SOC is regarded as a common template mask set. The common template mask set comprises one or more common template masks, where a common template mask is used to form a set of features of the common template. The common template meets design requirements for multiple vendors by comprising features, corresponding to polygon positions, for example, that allow the SOC to be electrically connected to the part regardless of the vendor that provided the part. It will be appreciated, however, that in some instances a vendor specific layer or set of features is required depending upon the vendor that is providing the part. The common template mask set similarly meets design requirements for multiple vendors by producing the features of the common template.

Given the common template mask set, or parameters thereof, a set of design rules is generated based on the common template mask set. The set of design rules is provided to a third party, such as a customer or any type of consuming entity interested in being able to connect a SOC to a part, such as DRAM. The third party generates a SOC design, and provided the third party complies with the set of design rules, the third party SOC design is compatible with the common template mask set. It will be appreciated that, where a mask set does not yet exist to establish an interface for a part from a particular vendor, the common template mask set obviates a requirement for a customer to produce such a mask set. It will be appreciated that this results in substantial savings where the customer desires to use the part from different vendors, and would thus otherwise be required to produce multiple mask sets, generally one per vendor from which the part is sourced. It will be appreciated that while vendor is substantially used herein that the instant application, including the scope of the appended claims, is not meant to be limited thereby. For example, vendor is to be synonymous with merely party, entity or the like.

The following description and annexed drawings set forth certain illustrative aspects and implementations. These are indicative of but a few of the various ways in which one or more aspects are employed. Other aspects, advantages, or novel features of the disclosure will become apparent from the following detailed description when considered in conjunction with the annexed drawings.

DETAILED DESCRIPTION

Embodiments or examples, illustrated in the drawings are disclosed below using specific language. It will nevertheless be understood that the embodiments or examples are not intended to be limiting. Any alterations and modifications in the disclosed embodiments, and any further applications of the principles disclosed in this document are contemplated as would normally occur to one of ordinary skill in the pertinent art.

It will be appreciated that ‘layer’, as used herein, contemplates a region, and does not necessarily comprise a uniform thickness. For example, a layer is a region, such as an area comprising arbitrary boundaries. A layer is also, for example, a region comprising a variation in thickness.

It will be appreciated that for some of the figures herein, one or more boundaries, such as boundary110A ofFIG. 2, for example, are drawn with different heights, widths, perimeters, aspect ratios, etc. relative to one another merely for illustrative purposes, and are not necessarily drawn to scale. For example, because dashed or dotted lines are used to represent different boundaries, if the dashed and dotted lines were drawn on top of one another they would not be distinguishable in the figures, and thus are drawn with different dimensions or slightly apart from one another, in some of the figures, so that they are distinguishable from one another. As another example, where a boundary is associated with an irregular shape, the boundary, such as a box drawn with a dashed line, dotted lined, etc., does not necessarily encompass an entire component in some instances. Conversely, a drawn box does not necessarily encompass merely an associated component, in some instances, but encompasses at least a portion of one or more other components as well.

FIG. 1is a table100illustrating an example common template mask set for an electronic article, such as a system on chip (SOC), according to some embodiments. Generally, a third party or any type of consuming entity formulates a SOC design and a first set of masks140is used to establish a first interface A (not shown) to connect the SOC to a first part from a first vendor, entity, party, etc. The first set of masks140is used to fabricate the first interface A comprising one or more sets of features on the SOC. The first interface A enables the SOC to electrically connect with the first part from the first vendor. As an example, the first set of masks140comprises a first mask A142, a second mask A144, a third mask A146, and a fourth mask A148. The first mask A142is used to form a first set of features A on the SOC. Similarly, the second mask A144, the third mask A146, and the fourth mask A148are used to form a second set of features A, a third set of features A, and a fourth set of features A on the SOC, respectively. Together, the first, second, third, and fourth set of features A form the first interface A on the SOC.

A second set of masks150are used to fabricate a second interface B (not shown) when a switch is made to a second part from a second vendor, entity, party, etc. It will be appreciated that the first part and the second part correspond to a same part, such as DRAM, for example, but where the first part is provided by the first vendor and the second part is provided by the second vendor. For example, the second set of masks150comprises a first mask B152, a second mask B154, a third mask B156, and a fourth mask B158. The first mask B152, the second mask B154, the third mask B156, and the fourth mask B158are used to form a first set of features B, a second set of features B, a third set of features B, and a fourth set of features B on the SOC, respectively. It will be appreciated that the second set of masks150is specific to the second vendor and that the first set of masks140is specific to the first vendor.

In some embodiments, a common template mask set160comprises a first mask U162, a second mask U164, and a third mask U166. The first mask U162is configured to form the first set of features A and the first set of features B on the SOC. Similarly, the second mask U164is configured to form the second set of features A and the second set of features B on the SOC. The third mask U166is configured to form the third set of features A and the third set of features B on the SOC. In other words, a ‘U’ mask is functionally equivalent to an ‘A’ mask counterpart and a ‘B’ mask counterpart, at least in part. For example, the first mask U162is functionally equivalent to the first mask A142and the first mask B152. In some embodiments, a common template comprises the respective features formed by masks162,164, and166. In other words, the common template comprises the first set of features A, the second set of features A, the third set of features A, the first set of features B, the second set of features B, and the third set of features B. Because masks162,164, and166of the common template mask set160are configured to form features similar to the features associated with masks142,152,144,154,146, and156, the common template mask set160is configured to fabricate a common template that is compatible with the first part from the first vendor and the second part from the second vendor. Because the first mask U162, the second mask U164, and the third mask U166provide features functionally equivalent to the first mask A142, the first mask B152, the second mask A144, the second mask B154, the third mask A146, and the third mask B156, the common template mask set160ofFIG. 1reduces a number of masks associated with interface fabrication.

A under bump metallization (UBM) mask is used to fabricate one or more vendor specific features on the SOC. For example, the fourth mask A148is used to fabricate a first set of UBM features on the SOC when the first vendor is selected. Similarly, the fourth mask B158is used to fabricate a second set of UBM features on the SOC when the second vendor is selected.

FIG. 2is a layout view200of an example common template mask130for an electronic article, such as a system on chip (SOC), according to some embodiments. A common template mask is a combination of a first set of features associated with a first vendor part and a second set of features associated with a second vendor part. For example,110is a first set of polygon positions associated with a first vendor part from a first vendor, entity, party, etc. and120is a second set of polygon positions associated with a second vendor part from a second vendor, entity, party, etc. Effectively, the sets of polygon positions are design requirements from respective vendors, where polygon positions correspond, for example, to features to be formed in an interface. Generally, a set of polygon positions comprises one or more subsets of polygon positions. A subset of polygon positions comprises one or more patterns.

In the example illustrated inFIG. 2, the first set of polygon positions110comprises a first subset of polygon positions114and a second subset of polygon positions116. The first subset of polygon positions114comprises pattern110A and pattern110B. The second subset of polygon positions116comprises pattern102. The second set of polygon positions120comprises a third subset of polygon positions118and a fourth subset of polygon positions124. The third subset of polygon positions118comprises pattern120A and pattern120B. The fourth subset of polygon positions124comprises pattern102.

In some embodiments, the first set of polygon positions110is functionally equivalent to the second set of polygon positions120. For example, one or more signals associated with the first set of polygon positions110, or features ultimately fabricated at the first set of polygon positions110, are the same as one or more signals associated with the second set of polygon positions120, or features ultimately fabricated at the second set of polygon positions120. Because the first set of polygon positions110comprises patterns110A and110B of the first subset114and the second set of polygon positions120does not comprise patterns110A and110B, the first subset114is exclusive to the first set of polygon positions110. Similarly, because the second set of polygon positions120comprises patterns120A and120B of the third subset118and the first set of polygon positions110does not comprise patterns120A and120B, the third subset118is exclusive to the second set of polygon positions120. Within the first set of polygon positions110and the second set of polygon positions120, however, the second subset116and the fourth subset124do overlap. In an example, the overlap occurs because polygons of the second subset116and polygons of the fourth subset124are positioned according to a commonality, such as an industry standard, for example. While a commonality is not limited to an industry standard, an example industry standard is nevertheless a Joint Electron Devices Engineering Council (JEDEC) standard.

The common template mask130ofFIG. 1is generated based on the first set of polygon positions110and the second set of polygon positions120, as illustrated by arrows pointing from110and120to130. For example, the common template mask130comprises the first subset114of the first set of polygon positions110, the third subset118of the second set of polygon positions120, and the second subset116of the first set of polygon positions110or the fourth subset124of the second set of polygon positions. Explained in another way, the common template mask130is generated based on a superset or a union of the first set of polygon positions110and the second set of polygon positions120. Because the second subset116and the fourth subset124share overlapping positions, the second subset116and the fourth subset124are merged in the common template mask130, illustrated as116. Since the common template mask130combines the first set of polygon positions110with the second set of polygon positions120, the common template mask130facilitates formation of features that satisfy design requirements for both the first vendor and the second vendor. Because of this, the common template formed by the common template mask130is compatible with parts from both the first vendor and the second vendor. In this way, the common template mask130comprises a vendor neutral design with regard to the first vendor and the second vendor. It will be appreciated that separate masks associated with the first set of polygon positions110, such as the first mask A142ofFIG. 1, and the second set of polygon positions120, such as the first mask B152ofFIG. 1, are not required when using the common template mask130. Accordingly, a number of masks associated with fabricating a SOC design, or an interface associated therewith, is mitigated. Accordingly, a number of manufacturing process variables associated with retooling for multiple masks is reduced as well.

FIG. 3is a flow diagram of an example method300for incorporating a common template into an electronic article design, such as a system on chip (SOC) design, according to some embodiments. A common template mask set is generated from a superset of design requirements received from multiple vendors, entities, parties, party, etc. Design requirements are generally expressed as polygon positions for a mask, or rather features of an interface fabricated using the mask. At302, a first set of polygon positions is received. The first set of polygon positions is a set of design requirements associated with a first part from a first vendor. At304, a second set of polygon positions is received from a second vendor. The second set of polygon positions is a set of design requirements associated with a second part from a second vendor. At306, a common template mask set comprising one or more common template masks is generated based on the first set of polygon positions and the second set of polygon positions. In some embodiments, a common template mask of the common template mask set is generated based on a superset or union of the first set of polygon positions and the second set of polygon positions. At a later stage, a common template mask of the common template mask set is used to fabricate a portion of a common template, such as a set of features on a SOC.

In some embodiments, one or more UBM masks are generated for the respective vendors. For example, in some instances, there are no common features among vendors and thus a vendor specific UBM mask is required for different vendors. Accordingly, at308, a first under bump metallization (UBM) mask or a second UBM mask is generated based on the first set of polygon positions or the second set of polygon positions, respectively. At a later stage, a UBM mask is used to fabricate micro-bumps on a SOC. The micro-bumps enable the SOC to be electrically connected to a first part from a first vendor or a second part from a second vendor, for example.

At310, a set of design rules is generated based on the common template mask set and provided to a third party, such as a customer. The set of design rules enables an SOC designer to create a design that can be fabricated utilizing the common template mask set. The set of design rules are indicative of suggested protocol to be followed during SOC design in order for the common template mask set to be used in conjunction with the SOC. For example, when a SOC or a SOC design in accordance with the set of design rules is received, the common template masks of the common template mask set are used to fabricate a common template on the SOC. Because the common template mask set is being used, the common template is compatible with the first part from the first vendor and the second part from the second vendor.

In some embodiments, a first design rule defines a position associated with an input-output (I/O) connection for the SOC. For example, an I/O connection is a micro-bump connection or a through silicon via (TSV) connection. A second design rule defines a number of I/O connections at a top layer of the SOC. Explained in another way, a design rule facilitates mating between a third party SOC and a common template mask of a common template mask set to fabricate a common template on the third party SOC. In other words, because the design rule is indicative of a suggested connection between third party logic of the third party SOC and an interface, such as a common template, a SOC designed according to the design rule enables one to fabricate the interface on the SOC using the common template mask set, rather than a custom mask set. It will be appreciated that some SOCs are fabricated active side up, while other SOCs are fabricated active side down, as will be described inFIG. 5andFIG. 6, respectively. A third design rule associated with an active side up SOC design defines a position associated with a micro-bump for the SOC. A fourth design rule associated with an active side down SOC design defines a position associated with a through silicon via (TSV) for the SOC.

FIG. 4is a flow diagram of an example method400for incorporating a common template into an electronic article design, such as a system on chip (SOC) design, according to some embodiments. When a set of design rules generated based on a common template mask set is provided to a third party, the third party generates a third party SOC design in accordance with the set of design rules. In some embodiments, the third party SOC design that is in accordance with the set of design rules is received at402. In some embodiments, a third party SOC is fabricated based on the third party SOC design at402. In other embodiments, a fabricated third party SOC is received at402. That is, rather than fabricating the SOC based upon the third part SOC design, the third party SOC is already fabricated, according to the third party SOC design, such as by a different entity, for example, and is merely received at402.

Because the set of design rules is based on the common template mask set, a third party following the set of design rules is not required to develop a custom set of masks to fabricate an interface on the SOC. Thus, having a third party use design rules that are in conformance with a common template mask set allows the third party to generate a third party SOC design that can be satisfied by multiple vendors, without requiring multiple mask sets specific to each vendor.

During an intermediate fabrication stage at404, a common template is fabricated on the third party SOC using the common template mask set. A third party SOC design often comprises a re-distribution layer (RDL) on a backside or a non-active region of the SOC. In some embodiments, the common template is fabricated on a backside of the third party SOC using the common template mask set. The common template mask set comprises one or more common template masks. For example, a common template mask of the common template mask set is configured to form a first set of features associated with a first part for a first vendor, such as a first set of features A associated with the first mask A142ofFIG. 1, and a second set of features associated with a second part for a second vendor, such as the first set of features B associated with the first mask B152ofFIG. 1. Together, the common template masks of the common template mask set form one or more sets of features associated with the first part from the first vendor and one or more sets of features associated with the second part from the second vendor. Effectively, the common template masks of the common template mask set form a common template that comprises the respective features. As discussed with regard toFIG. 2, a common template formed by a common template mask set comprising the common template mask130is compatible with a part from the first vendor as well when the part is sourced from the second vendor. In this way, the common template mask set is used to create a ‘standard’ interface on the SOC. In other words, the common template has a vendor neutral design.

At406, a under bump metallization (UBM) layer is fabricated on the SOC based on a vendor selection of a part, such as DRAM, for the SOC. For example, the vendor selection comprises a first vendor selection or a second vendor selection. Up to this stage, the SOC, the common template fabricated on the SOC, and associated fabrication processing, such as common template masks used, have been vendor independent. For example, with reference toFIG. 1, the common template mask set160comprising the first mask U162, the second mask U164, and the third mask U166are used to fabricate a common template comprising sets of features associated with the first mask A142, the second mask A144, the third mask A146, the first mask B152, the second mask B154, and the third mask B156. The UBM layer, however, is vendor specific. In other words, the fourth mask A148is used to fabricate a first UBM layer when a part from the first vendor is selected, while the fourth mask B158is used to fabricate a second UBM layer when a part from a second vendor is selected. In some embodiments, the UBM layer comprises micro-bumps that are used to electrically connect the SOC to a part from a vendor. For example, if the first vendor is selected, the fourth mask A148is used to fabricate a first UBM layer comprising one or more micro-bumps that are configured to connect the SOC to the part from the first vendor. Similarly, if the second vendor is selected, the fourth mask B158is used to fabricate a second UBM layer comprising one or more micro-bumps that are configured to connect the SOC to the part from the second vendor. Explained in another way, when a part from a vendor is integrated into a SOC design, a UBM mask corresponding to the vendor is used to fabricate a UBM layer to connect the part from the vendor to the SOC.

In this way, merely a UBM mask, such as the fourth mask A148or the fourth mask B158, is changed when a different vendor is selected to provide a part for a SOC. Because the common template mask set is compatible with parts from multiple vendors, vendor selection is not required at an earlier stage, such as fabrication of the common template. Since the common template mask set is adaptable to multiple vendors, no mask redesign is necessary for the common template when the third party changes a vendor selection. Further, if a third party switches vendors for a part, merely the UBM mask is changed, resulting in a reduced amount of re-tooling or setup when the third party changes vendors.

FIG. 5is a cross-sectional view500of a portion of an active side up electronic article design, such as an active side up system on chip (SOC) design, according to some embodiments. A common template582is fabricated on the SOC570based on a common template mask set. In some embodiments, such as with an active side up SOC design, the common template582comprises a first dielectric region410, a second dielectric region420, a first metal region412within the first dielectric region410, a second metal region422within the second dielectric region420, and an interconnect402. A design rule associated with a common template mask of the common template mask set defines a position associated with a micro-bump at430. When a third party SOC design follows this design rule by positioning a micro-bump at this position, a common template mask set can be used to fabricate the common template582on the SOC570. The common template582facilitates connecting the SOC570to a vendor part, such as DRAM590after a vendor specific UBM layer580is fabricated on the common template582.

FIG. 6is a cross-sectional view600of a portion of an active side down electronic article design, such as an active side down system on chip (SOC) design, according to some embodiments. A common template584is fabricated on the SOC570based on a common template mask set. The common template584comprises a first dielectric region410, a second dielectric region420, a first metal region412within the first dielectric region410, a second metal region422within the second dielectric region420, an interconnect402, a silicon region540, a through silicon via (TSV)502, a passivation region550, and a backside metal region552. A design rule associated with a common template mask defines a position associated with the TSV at530. When a third party SOC design follows this design rule by placing a TSV line at a predetermined or fixed position, such as at530, a common template mask set can be used to fabricate the common template584on the SOC570. The common template584connects the SOC570to a vendor part, such as DRAM590after a vendor specific UBM layer560is fabricated on the common template584.

Still another embodiment involves a computer-readable medium comprising processor-executable instructions configured to implement one or more of the techniques presented herein. An example embodiment of a computer-readable medium or a computer-readable device is illustrated inFIG. 7, wherein an implementation700comprises a computer-readable medium708, such as a CD-R, DVD-R, flash drive, a platter of a hard disk drive, etc., on which is encoded computer-readable data706. This computer-readable data706, such as binary data comprising a plurality of zero's and one's as shown in706, in turn comprises a set of computer instructions704configured to operate according to one or more of the principles set forth herein. In one such embodiment700, the processor-executable computer instructions704are configured to perform a method702, such as at least some of the exemplary method300ofFIG. 3or at least some of exemplary method400ofFIG. 4. In another embodiment, the processor-executable instructions704are configured to implement a system. Many such computer-readable media are devised by those of ordinary skill in the art that are configured to operate in accordance with the techniques presented herein.

Generally, embodiments are described in the general context of “computer readable instructions” being executed by one or more computing devices. Computer readable instructions are distributed via computer readable media as will be discussed below. Computer readable instructions are implemented as program modules, such as functions, objects, Application Programming Interfaces (APIs), data structures, and the like, that perform particular tasks or implement particular abstract data types. Typically, the functionality of the computer readable instructions are combined or distributed as desired in various environments.

FIG. 8illustrates an example of a system800comprising a computing device812configured to implement one or more embodiments provided herein. In one configuration, computing device812includes at least one processing unit816and memory818. Depending on the exact configuration and type of computing device, memory818may be volatile, such as RAM, non-volatile, such as ROM, flash memory, etc., or some combination of the two. This configuration is illustrated inFIG. 8by dashed line814.

In other embodiments, device812includes additional features or functionality. For example, device812also includes additional storage such as removable storage or non-removable storage, including, but not limited to, magnetic storage, optical storage, and the like. Such additional storage is illustrated inFIG. 8by storage820. In some embodiments, computer readable instructions to implement one or more embodiments provided herein are in storage820. Storage820also stores other computer readable instructions to implement an operating system, an application program, and the like. Computer readable instructions are loaded in memory818for execution by processing unit816.

Device812includes input device(s)824such as keyboard, mouse, pen, voice input device, touch input device, infrared cameras, video input devices, or any other input device. Output device(s)822such as one or more displays, speakers, printers, or any other output device are also included in device812. Input device(s)824and output device(s)822are connected to device812via a wired connection, wireless connection, or any combination thereof. In some embodiments, an input device or an output device from another computing device are used as input device(s)824or output device(s)822for computing device812. Device812also includes communication connection(s)826to facilitate communications with one or more other devices.

According to some aspects, a method for incorporating a common template into a system on chip (SOC) design is provided, comprising receiving a first set of polygon positions from a first vendor. Additionally, the method comprises receiving a second set of polygon positions from a second vendor. The method comprises generating a common template mask set based on the first set of polygon positions and the second set of polygon positions. The method comprises generating a first under bump metallization (UBM) mask for the first vendor or a second UBM mask for the second vendor based on the first set of polygon positions or the second set of polygon positions. The method comprises generating a set of design rules based on the common template mask set, a first design rule defining a position associated with an input-output (I/O) connection for a system on chip (SOC).

According to some aspects, a method for incorporating a common template into a system on chip (SOC) design is provided, comprising receiving a third party system on chip (SOC) design that is in accordance with a set of design rules based on a common template mask set. Additionally, the method comprises fabricating a common template in conjunction with the third party SOC design based on the common template mask set.

According to some aspects, common template mask for a system on chip (SOC) is provided, comprising a first pattern, a second pattern, and a third pattern. For example, the first pattern is associated with a first subset of a first set of polygon positions from a first vendor. For example, the second pattern is associated with a first subset of a second set of polygon positions from a second vendor. For example, the third pattern is associated with a second subset of the first set of polygon positions from the first vendor that overlaps with a second subset of the second set of polygon positions from the second vendor.

Further, unless specified otherwise, “first,” “second,” or the like are not intended to imply a temporal aspect, a spatial aspect, an ordering, etc. Rather, such terms are merely used as identifiers, names, etc. for features, elements, items, etc. For example, a first channel and a second channel generally correspond to channel A and channel B or two different or identical channels.

Also, although the disclosure has been shown and described with respect to one or more implementations, equivalent alterations and modifications will occur based on a reading and understanding of this specification and the annexed drawings. The disclosure includes all such modifications and alterations and is limited only by the scope of the following claims.