Multiple port resistive memory cell

A resistive type memory system provides improved read access with multiple ports. The resistive type memory system includes a plurality of resistive type memory cells arranged in an array. Each of the resistive type memory cells has a corresponding first port and a corresponding second port. Each first port enables both read access and write access to the corresponding resistive type memory cell. Additionally, each second port enables read access to the corresponding MRAM cell. Furthermore, the memory system enables overlapping read or write access, with another read access.

TECHNICAL FIELD

Disclosed embodiments herein relate generally to nonvolatile memory, and more particularly to multiple port resistive type memory cells, resistive type memory arrays with multiple ports, and a system using the same.

BACKGROUND

Resistive type memory has “0” and “1” logic states that are determined by a resistance difference of the memory rather than conventional charges stored in capacitors. Currently, there are several known resistive type memories: for example, magnetoresistive random access memory (MRAM) and phase change random access memory (PRAM). More recently, memory cells formed by nanotubes also provide a resist type of memory. MRAM is a type of non-volatile memory that uses magnetism rather than charge stored in capacitors to store data (e.g., both DRAM and FRAM are capacitor-type memories). Conventional MRAM cells are described in U.S. patent application Ser. No. 10/907,977, entitled “Magnetic Random Access Memory Device,” by Jhon Jhy Liaw, and are herein incorporated by reference.

Conventional resistive memory cells have several limitations. One limitation is that of speed in reading data from the cells. Currently, logic circuits are operating at frequencies in the GHz ranges. However, conventional resistive memory cell devices are constrained to operate at much slower rates, causing a significant performance gap between the logic and the memory. This performance gap results in a suboptimal performance of the logic circuits because supporting resistive memory devices cannot provide data and instructions fast enough. Thus, this results in a bottleneck effect at the resistive memory devices, particularly in System on Chip (SoC) designs, which combine memory with logic circuitry on a chip. It would therefore be desirable to improve the speed of data access in resistive memory devices.

SUMMARY

Disclosed herein is a resistive type memory that provides improved read access with multiple ports. In an embodiment, a memory system provides a plurality of resistive type memory cells arranged in an array. In the memory system, each of the resistive type cells has a corresponding first port and a corresponding second port. Additionally, each first port enables both read access and write access to the corresponding resistive type memory cell, and each second port enables read access to the corresponding resistive type memory cell. Further, the memory system enables overlapping read or write access, with another read access. In some embodiments, the resistive type memory cell is a magnetoresistive random access memory (MRAM), although it may alternatively be a phase change random access memory (PRAM), a memory cell formed by nanotubes, or the like.

In another aspect, a non-volatile memory cell includes a resistive type memory element having an electrode layer, a plurality of transistors with each transistor having a gate node connected to the electrode layer, and a reference transistor having a drain node and a source node, where one of the drain and the source nodes of the reference transistor is connected to the electrode layer. Each of the plurality of transistors provides a corresponding port to read data from the non-volatile memory cell.

In yet another aspect, a non-volatile memory cell includes a resistive type memory element having a first electrode conductor, a second electrode conductor, and a resistive memory device between the first and second electrode conductors. A first conductive line is electrically connected to the first electrode conductor. First and second transistors are provided, with each transistor having a gate node, a source node, and a drain node, in which the gate nodes of each transistor are electrically connected to the second electrode conductor. The non-volatile memory cell further includes a second conductive line and a third conductive line, in which the second conductive line is electrically connected to one of the drain node and the source node of the first transistor, and in which the third conductive line is electrically connected to one of the drain node and the source node of the second transistor.

DETAILED DESCRIPTION

A resistive type memory cell provides improved read access with multiple ports. In an embodiment, a memory system provides a plurality of MRAM cells arranged in an array. In the memory system, each of the MRAM cells has a corresponding first port and a corresponding second port. Additionally, each first port enables both read access and write access to the corresponding MRAM cell, and each second port enables read access to the corresponding MRAM cell. Further, the memory system enables overlapping read or write access, with another read access.

FIG. 1shows a schematic diagram of a portion100of an MRAM array, which includes a memory cell150. The memory cell150includes a magnetoresistive (MR) element300, a reference transistor124, a first amplifying transistor108, and a second amplifying transistor110. The MR element300can include layers302-312shown inFIG. 3and described below. It should be noted that the MR element300may alternatively be another resistive type memory cell type such as a phase-change random access memory (PRAM) cell, memory cells formed by nanotubes, or the like.

The reference transistor124has a gate node coupled to a bit line (BL)122, a source node coupled to either a predetermined voltage VDDor a signal ground VSSat115(depending on which of the read schemes described below is used), and a drain node coupled to the bottom electrode (312inFIG. 3) of the MR element300.

The first amplifying transistor108has a gate node connected to the drain node of the reference transistor124and to the bottom electrode (312inFIG. 3) of the MR element300, all of which are electrically connected to node112. The first amplifying transistor108also has a drain node connected to a first program line (PL-A)116and a source node connected to VSSat114. Similarly, the second amplifying transistor110has a gate node connected to the drain node of the reference transistor124and to the bottom electrode312of the MR element300. The second amplifying transistor110also has a drain node connected to a second program line (PL-B)118and a source node connected to VSSat114.

The top electrode (302inFIG. 3) of the MR element300is coupled to a word line (WL)120. The first program line (PL-A)116extends in the vicinity of the MR element300for write operations.

Components of the MRAM array100external to the memory cell150include a first sense amplifier130connected to the PL-A116, and a second sense amplifier134connected to the PL-B118. During a read operation, the first sense amplifier130and/or the second sense amplifier134can determine the logic state of the memory cell150based on whether the voltage (or current) on the PL-A116and PL-B118is higher or lower than a reference voltage (or current). In some embodiments, the reference voltage (or current) can come from optional reference cells132and136connected to the sense amplifiers130and134, respectively. The reference cells132and136can include an MR element fixed at a midpoint resistance level. In other embodiments, a fixed voltage (or current) can be supplied to the sense amplifiers130and134for use as a reference voltage (or reference current).

The MRAM array100can further include a column selector140and a row selector142. The column and row selectors140,142are used for addressing cells of the MRAM array. For this purpose, the column selector140controls the voltage level of the BL122and the row selector controls the voltage level of the WL120.

FIG. 2shows a perspective diagram of the exemplary MRAM cell150ofFIG. 1. Word line (WL)120provides a first conductive line electrically connected to the top electrode (302ofFIG. 3) of magnetoresistive element300. First and second program lines PL-A116& PL-B118provide conductive lines extending substantially orthogonal to WL120. Bit line (BL)122provides a conductive line, extending substantially parallel to PL-A116and PL-B118. The cells150may be arranged in an array as depicted in the plan view ofFIG. 5. Although PL-A116and PL-B118are shown at the same level of conductive layer, it should be appreciated that bit line122, PL-A116and PL-B118may alternatively be formed at different levels of conductive layers for cell size optimization. Furthermore, the width of PL-A116may be substantially the same as the width of magnetoresistive element300, and wider than the width of PL-B118for cell size optimization for read/write current optimization. Additionally, PL-A116, PL-B118and WL120may intersect at an acute angle depending on cell design.

During a write operation, electrical current flows through PL-A116and a current is passed through WL120. The magnitude of these currents is selected such that, ideally, the resulting magnetic fields are not strong enough to affect the memory state of other proximate MR elements in the array, yet the combination of the two magnetic fields (at MR element300) is sufficient for switching the memory state of MR element300(e.g., switching the magnetic moment of the free layer304shown inFIG. 3).

In another embodiment, described in more detail inFIG. 8, a dedicated write line may be used. For example, a write operation may be performed by passing electrical current through a bit write line (824ofFIG. 8), that extends in the same or different direction as program lines PL-A116& PL-B118. Such a bit write line is proximate to the bottom electrode (312ofFIG. 3).

In yet another embodiment, a write operation may be performed by passing electrical current through PL-A116as a bit write line, that extends in the same or different direction as program lines PL-B118. Such a bit write line is proximate to the bottom electrode (312ofFIG. 3). Accordingly, the first port conductive line can perform a dual function for write and read operations.

FIG. 3shows an example of a typical magnetoresistive element300. The magnetoresistive element300includes the following layers: a top electrode layer302, a ferromagnetic free layer304, a spacer306which serves as a tunneling barrier, a ferromagnetic pinned layer308, an antiferromagnetic pinning layer310, and a bottom electrode312. The ferromagnetic free layer304and the ferromagnetic pinned layer308are constructed of ferromagnetic material, for example cobalt-iron or nickel-cobalt-iron. The antiferromagnetic pinning layer310is constructed of antiferromagnetic material, for example platinum manganese. Magnetostatic coupling between the ferromagnetic pinned layer308and the antiferromagnetic pinning layer310causes the ferromagnetic pinned layer308to have a fixed magnetic moment. The ferromagnetic free layer304, on the other hand, has a magnetic moment that, by application of a magnetic field, can be switched between a first orientation, which is parallel to the magnetic moment of the ferromagnetic pinned layer308, and a second orientation, which is antiparallel to the magnetic moment of the ferromagnetic pinned layer308.

The spacer306interposes the ferromagnetic pinned layer308and the ferromagnetic free layer304. The spacer306is composed of insulating material, for example aluminum oxide, magnesium oxide, or tantalum oxide. The spacer306is formed thin enough to allow the transfer (tunneling) of spin-aligned electrons when the magnetic moments of the ferromagnetic free layer304and the ferromagnetic pinned layer308are parallel. On the other hand, when the magnetic moments of the ferromagnetic free layer304and the ferromagnetic pinned layer308are antiparallel, the probability of electrons tunneling through the spacer306is reduced. This phenomenon is commonly referred to as spin-dependent tunneling (SDT).

As shown inFIG. 4, the electrical resistance through the magnetoresistive element300(e.g., through layers302-312) increases as the moments of the pinned and free layers become more antiparallel and decreases as they become more parallel. In an MRAM memory cell, the electrical resistance of the magnetoresistive element300can therefore be switched between first and second resistance values representing first and second logic states. For example, a high resistance value can represent a logic state “1” and a low resistance value can represent a logic state “0”. The logic states thus stored in the memory cells can be read by passing a sense current through the MR element and sensing the resistance.

As mentioned above, there are multiple options for read schemes for the portion100of the MRAM array shown inFIG. 1.

A first read scheme can be used when the reference transistor124has its source node connected to signal ground VSS(e.g., where VSSis signal ground). In order to read the data bit stored in the MR element300, the column selector140sets the BL122to a predetermined voltage, for example, a voltage in a range of 0.3V to 1.8V. The row selector142sets the WL120to a predetermined voltage, for example, a voltage in a range of 0.3V to 1.5V. The voltage VINat input node112will depend on the resistance of the MR element300as follows:

where RREFis the resistance across the reference transistor124and RMRis the resistance across the MR element300. The current or voltage level of the PL-A116and PL-B118can then be detected by the sense amplifiers130and134respectively, in order to detect the logic state stored in the memory cell150. In embodiments that include a reference cell132, for example, the sense amplifier130can detect the logic state of the memory cell150based on a comparison of the voltage (or current) level of the PL-A116to a reference voltage (or current) level received from the reference cell132. Similarly, the sense amplifier134can detect the logic state of the memory cell150based on a comparison of the voltage (or current) level of the PL-B118to a reference voltage (or current) level received from the reference cell136.

Alternatively, the polarity across the reference transistor124and the MR element300can be reversed. Specifically, a second read scheme can have the WL120set to signal ground VSSand the source node of the reference transistor124connected to a predetermined voltage VDD, for example, a voltage in a range of 0.3V to 1.5V. The BL122is still set to a predetermined voltage, for example, a voltage in a range of 0.3V to 1.8V, in order to read the data bit stored in the MR element300. In order to read the data from PL-A116, a predetermined voltage level VDD, for example, a voltage in a range of 0.3V to 1.8V, is applied to the PL-A116. As in the first read scheme, the voltage VINat node112will depend on the resistance of the MR element300according to Equation (1) above. The current or voltage level of the PL-A116can then be detected by the sense amplifier130in order to detect the logic state stored in the memory cell150. In embodiments that include a reference cell132, for example, the sense amplifier130can detect the logic state of the memory cell150based on a comparison of the voltage (or current) level of the PL-A116to a reference voltage (or current) level received from the reference cell132. Similarly, in order to read the data from PL-B118, a predetermined voltage level of VDD, for example, a voltage in a range of 0.3V to 1.8V, is applied to the PL-B118. Sense amplifier134may detect the logic state of the memory cell150by comparison of the voltage (or current) on PL-B118with a reference voltage (or current) level received from the reference cell136.

As a result of including the amplifying transistors108and110in the memory cell150and using a read operation such as those described above, the logic state can be sensed by detecting current on the program lines116and/or118, which varies according to the voltage at the input node112. In this case, if the MR ratio is 30% and the resistance RREFacross the reference transistor124is close to the resistance RMRacross the MR element300, then the difference between the current on a program line IPL(PL-A116and PL-B118), for example, IPL“High” (e.g., representative of a logic state “0”) and IPL“Low” (e.g., representative of a logic state “1”) can provide for a read margin in a range of 50% to 200%.

The increased read margin is advantageous for embodiments that include reference cells132&136. In such embodiments, a read operation depends on the ability of the sense amplifier130to accurately determine a logic state based on whether the voltage from the memory cell150is higher or lower than the reference voltage received from the reference cell132. However, in a large array of memory cells150, slight differences between MR elements104can result in variations among the read voltages received from different memory cells150. If the read margin is too low, as in prior devices, such deviations in read voltages can result in false readings. On the other hand, by increasing the read margin according to the present application, the impact of differences among the MR elements104is greatly reduced if not eliminated. As a result, a more reliable memory device can be realized.

FIG. 5shows a simplified plan view of an exemplary layout according to the disclosed principles of an MRAM array composed of memory cells150. The memory cells150are arranged in rows and columns. Each memory cell150of a particular row is connected by a word line120, while each memory cell150of a particular column is connected by a bit line122, a first program line116and a second program line118.

FIG. 6shows a schematic diagram of an exemplary MRAM memory cell with additional program lines. Additional amplifying transistors from110bto110nmay have their respective gates connected to node112, where n−2 represents an integer number of amplifying transistors in the cell150. The amplifying transistors110bto110nhave a source node connected to VSSat114, and corresponding drain nodes118bto118n. The dotted and dashed lines in this figure indicate that there may be additional amplifying transistor cells and program lines added to this circuitry in accordance with the present disclosure, therefore the disclosure should not be limited to these illustrated embodiments.

FIG. 7shows a simplified plan view of a memory array including memory cells, such as the example shown inFIG. 6. The memory cells150are arranged in rows and columns. Each memory cell150of a particular row is connected by a word line120, while each memory cell150of a particular column is connected by a bit line122, a first program line116, a second program line118b, and n−2 additional program lines, where n represents the total number of program lines connected to each cell.

FIG. 8shows a perspective diagram of an alternative embodiment of an exemplary MRAM cell850, in which a bit write line824is used to write to the cell850(as an alternative to writing to the cell by passing a current through PL-A116ofFIG. 1). Word line (WL)820provides a first conductive line electrically connected to the top electrode (302ofFIG. 3) of magnetoresistive element300. First and second program lines PL-A816& PL-B818provide conductive lines extending substantially orthogonally to WL820. Bit line (BL)822provides a conductive line, extending parallel to PL-A816and PL-B818. The cell850includes a plurality of amplifying transistors808and810, with their respective drain nodes connected to corresponding program lines816and818(and optionally, additional amplifying transistors and program lines in accordance with the present disclosure). Additionally, the cell850includes reference transistor826, with a gate node connected to bit line822, and source and drain nodes connected as shown in the figure (in accordance with the selected read scheme previously disclosed). The top electrode (302inFIG. 3) of the MR element300is coupled to WL820. The bit write line824extends in the vicinity of the MR element300for write operations.

During a write operation, electrical current flows through bit write line824and a current is passed through WL820. The magnitude of these currents is selected such that, ideally, the resulting magnetic fields are not strong enough to affect the memory state of other proximate MR elements in the array, yet the combination of the two magnetic fields (at MR element300) is sufficient for switching the memory state of MR300(e.g., switching the magnetic moment of the free layer304shown inFIG. 3). In this exemplary embodiment, two read ports have been disclosed. However, in accordance with the principles of the present disclosure, in some embodiments, additional read ports may be added such that n read ports are enabled (similar to the example shown with reference toFIG. 6).

FIGS. 9A and 9Billustrate layout diagrams of another embodiment of an exemplary MRAM cell950.FIG. 9Ashows the MTJ portion of cell950, andFIG. 9Bshows the transistor and read port portions of cell950. With reference toFIG. 9A, the cell950includes a word line920, a write line924, a first program line916, a second program line918, and an MTJ cell300. The cell boundary is shown by line902. Via-x930provides a connection from the MTJ300bottom electrode912to a metal landing pad934. Via-y932provides a connection from the word line920to the MTJ300top electrode.

Referring now toFIG. 9B, which shows the transistor and read port portions of cell950, polysilicon942provides the gate junction for reference transistor926, and polysilicon944provides the gate junction for first amplifying transistor908and second amplifying transistor910. Metal landing pad934, which is electrically connected to the bottom electrode of MTJ300is also electrically connected to the polysilicon gate junction944and the drain of reference transistor926via metalized layer952. Metalized layer948connects the source (or alternatively the drain) junctions of first and second amplifying transistors908,910. Metalized layer946provides an electrical connection to word line920. Accordingly, The respective layers may be processed using conventional processing techniques that are known in the art.

While various embodiments in accordance with the principles disclosed herein have been described above, it should be understood that they have been presented by way of example only, and not limitation. For instance, the present disclosure can apply to not only MRAM cells, but also other resistive memory cells such as phase-change random access memory (PRAM) cells, resistive cells formed from nanotubes, or the like. Again, it should be noted that MTJ cell300is an exemplary type of resistive element for a resistive memory application. For example, other types of resistive elements such as multilayer-GMR (Giant Magnetoresistance Effect), spin-valve GMR and Granular GMR could alternatively be used as a resistive memory cell in accordance with the principles of the present disclosure. It should be noted that while exemplary circuitry and layouts have been presently disclosed, many other equivalent layouts and variations are possible that incorporate the teachings of the present disclosure. Thus, the breadth and scope of the invention(s) should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with any claims and their equivalents issuing from this disclosure. Furthermore, the above advantages and features are provided in described embodiments, but shall not limit the application of such issued claims to processes and structures accomplishing any or all of the above advantages.