SEMICONDUCTOR MEMORY DEVICE, METHOD OF FABRICATING THE SAME, AND ELECTRONIC SYSTEM INCLUDING THE SAME

Provided are a memory device, a method of fabricating the same, and an electronic system including the same. The memory device includes a peripheral circuit structure and a cell structure on the peripheral circuit structure. The cell structure comprises a cell substrate including a first surface facing the peripheral circuit structure and a second surface opposite to the first surface and having a first conductivity type, gate electrodes on the first surface of the cell substrate, a channel structure intersecting the gate electrodes and connected to the cell substrate, a first impurity region that is in the cell substrate adjacent to the second surface and has a second conductivity type, and a second impurity region that is in the cell substrate and is spaced apart from the first impurity region, the second impurity region having the first conductivity type with a higher impurity concentration than that of the cell substrate.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to Korean Patent Application No. 10-2022-0058190 filed on May 12, 2022, in the Korean Intellectual Property Office, and all the benefits accruing therefrom under 35 U.S.C. 119, the disclosure of which in its entirety is herein incorporated by reference.

BACKGROUND

The present disclosure relates to a semiconductor memory device, a method of fabricating the same, and an electronic system including the same. More specifically, the present disclosure relates to a semiconductor memory device including memory cells arranged in three dimensions, a method of fabricating the same, and an electronic system including the same.

Research is being conducted on a method of increasing the data storage capacity of a semiconductor memory device. For example, a semiconductor memory device including memory cells arranged in three dimensions has been proposed.

SUMMARY

Aspects of the present disclosure provide a semiconductor memory device with enhanced erase control performance.

Aspects of the present disclosure also provide an electronic system including a semiconductor memory device with enhanced erase control performance.

Aspects of the present disclosure also provide a method of fabricating a semiconductor memory device with enhanced erase control performance.

According to an aspect of the present disclosure, there is provided a semiconductor memory device comprising a peripheral circuit structure, and a cell structure stacked on the peripheral circuit structure, wherein the cell structure comprises a cell substrate that includes a first surface facing the peripheral circuit structure and a second surface opposite to the first surface, the cell substrate having a first conductivity type, a plurality of gate electrodes stacked on (e.g., sequentially stacked on) the first surface of the cell substrate, a channel structure that intersects the plurality of gate electrodes and is connected to (e.g., electrically connected to) the cell substrate, a first impurity region in the cell substrate adjacent to the second surface, the first impurity region having a second conductivity type different from the first conductivity type, and a second impurity region that is in the cell substrate and is spaced apart from the first impurity region, the second impurity region having the first conductivity type with a higher impurity concentration than that of the cell substrate. In some embodiments, the channel structure that comprises a portion in the plurality of gate electrodes.

According to another aspect of the present disclosure, there is provided a semiconductor memory device comprising a peripheral circuit structure and a cell structure stacked on the peripheral circuit structure, the peripheral circuit structure comprising a peripheral circuit board, a peripheral circuit element on the peripheral circuit board, and a peripheral circuit interconnection structure electrically connected to the peripheral circuit element, and the cell structure comprising a P-type cell substrate which includes a first surface facing the peripheral circuit structure and a second surface opposite to the first surface, a mold structure comprising a plurality of gate electrodes stacked on (e.g., sequentially stacked on) the first surface of the cell substrate, a plurality of channel structures, each of which extends in a vertical direction that is not parallel to the first surface of the cell substrate, penetrates through the mold structure, and is connected to (e.g., electrically connected to) the cell substrate, a bit line connected to (e.g., electrically connected to) the channel structures and is between the peripheral circuit structure and the mold structure, a plurality of gate contacts connected to (e.g., electrically connected to) the plurality of gate electrodes, respectively and are on the mold structure, a cell interconnection structure that is electrically connected to the bit line and the plurality of gate contacts, the cell interconnection structure contacting (e.g., bonded to) the peripheral circuit interconnection structure, an N-type first impurity region overlapping the plurality of channel structures in the vertical direction, in the cell substrate adjacent to the second surface, and a P-type second impurity region surrounding (e.g., extending around) at least a portion of the first impurity region in a plan view, in the cell substrate, the second impurity region having a higher impurity concentration than that of the cell substrate.

According to still another aspect of the present disclosure, there is provided an electronic system comprising a main substrate, a semiconductor memory device that is on the main substrate and comprises a peripheral circuit structure and a cell structure stacked on the peripheral circuit structure, and a controller that is electrically connected to the semiconductor memory device and is on the main substrate, wherein the cell structure comprises a cell substrate which includes a first surface facing the peripheral circuit structure and a second surface opposite to the first surface, the cell substrate having a first conductivity type, a plurality of gate electrodes stacked on (e.g., sequentially stacked on) the first surface of the cell substrate, a channel structure which intersects the plurality of gate electrodes and is connected to (e.g., electrically connected to) the cell substrate, a first impurity region in the cell substrate adjacent to the second surface of the cell substrate, the first impurity region having a second conductivity type different from the first conductivity type, and a second impurity region that is in the cell substrate and is spaced apart from the first impurity region, the second impurity region having the first conductivity type with a higher impurity concentration than that of the cell substrate. In some embodiments, the channel structure that comprises a portion in the plurality of gate electrodes.

According to still another aspect of the present disclosure, there is provided a method of fabricating a semiconductor memory device. The method comprises providing a cell substrate which has a first conductivity type and includes a first surface and a second surface that is opposite to the first surface, forming a mold structure comprising a plurality of gate electrodes stacked on (e.g., sequentially stacked on) the first surface of the cell substrate, forming a channel structure which intersects the plurality of gate electrodes and is connected to (e.g., electrically connected to) the cell substrate, forming a cell interconnection structure on the mold structure, providing (e.g., bonding) the cell interconnection structure on a peripheral circuit structure, forming a first impurity region in the cell substrate, wherein the first impurity region has a second conductivity type different from the first conductivity type and is adjacent to the second surface, and forming a second impurity region in the cell substrate, wherein the second impurity region has the first conductivity type with a higher impurity concentration than that of the cell substrate and is spaced apart from the first impurity region. In some embodiments, the channel structure that comprises a portion in the plurality of gate electrodes.

According to another aspect of the present disclosure, there is provided a method of fabricating a semiconductor memory device. The method comprises forming a mold structure comprising a plurality of gate electrodes stacked on (e.g., sequentially stacked on) a base substrate, forming a channel structure which intersects the plurality of gate electrodes and is connected to (e.g., electrically connected to) the base substrate, exposing an end of the channel structure by removing at least a portion of the base substrate, forming a cell substrate which is connected to (e.g., electrically connected to) the end of the channel structure and has a first conductivity type, wherein the cell substrate comprises a first surface on which the mold structure is disposed, and a second surface opposite to the first surface, forming a first impurity region in the cell substrate by performing a first ion-implanting process on the second surface of the cell substrate, wherein the first impurity region has a second conductivity type different from the first conductivity type and is adjacent to the second surface, forming a second impurity region in the cell substrate by performing a second ion-implanting process on the second surface of the cell substrate, wherein the second impurity region has the first conductivity type with a higher impurity concentration than that of the cell substrate and is adjacent to the second surface, and performing a laser annealing process on the second surface of the cell substrate. In some embodiments, the channel structure that comprises a portion in the plurality of gate electrodes.

It should be noted that the effects/aspects of the present disclosure are not limited to those described above, and other effects/aspects of the present disclosure will be apparent from the following description.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, example embodiments of the present invention will be described with reference to the attached drawings.

It will be understood that, although the terms first, second, and other terms may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first signal may be referred to as a second signal, and, similarly a second signal may be referred to as a first signal without departing from the teachings of the disclosure.

Hereinafter, a semiconductor memory device according to example embodiments will be described with reference toFIGS.1to18.

FIG.1is an example block diagram illustrating a semiconductor memory device according to some embodiments.

Referring toFIG.1, a semiconductor memory device10according to some embodiments includes a memory cell array20and a peripheral circuit30.

The memory cell array20may include a plurality of memory cell blocks BLK1to BLKn. Each of the memory cell blocks BLK1to BLKn may include a plurality of memory cells. The memory cell array20may be connected to the peripheral circuit30through bit lines BL, word lines WL, at least one string selection line SSL, and at least one ground selection line GSL. Specifically, the memory cell blocks BLK1to BLKn may be connected to a row decoder33via the word lines WL, the string selection lines SSL, and the ground selection lines GSL. In addition, the memory cell blocks BLK1to BLKn may be connected to a page buffer35via the bit lines BL. As used herein, “an element A connected to an element B” (or similar language) may mean that the element A is electrically connected to the element B and/or the element A contacts the element B.

The peripheral circuit30may receive an address ADDR, a command CMD, and a control signal CTRL from the outside of the semiconductor memory device10, and may transmit and receive data DATA from and to a device outside the semiconductor memory device10. The peripheral circuit30may include a control logic37, the row decoder33, and the page buffer35. In some embodiments, the peripheral circuit30may further include various sub-circuits. For example, the sub-circuits may include an input/output circuit, a voltage generation circuit configured to generate various types of voltages necessary for the operation of the semiconductor memory device10, an error correction circuit for correcting an error of data DATA read from the memory cell array20, and the like.

The control logic37may be connected to the row decoder33, the input/output circuit, and the voltage generation circuit. The control logic37may control overall operations of the semiconductor memory device10. The control logic37may generate various internal control signals to be used in the semiconductor memory device10in response to the control signal CTRL. For example, the control logic37may adjust a voltage level which is provided to the word lines WL and the bit lines BL when a memory operation such as a program operation or an erase operation is performed.

The row decoder33may select at least one of the plurality of memory cell blocks BLK1to BLKn in response to an address ADDR, and may select at least one word line WL of the selected memory cell block, at least one string selection line SSL, and at least one ground selection line GSL. In addition, the row decoder33may transmit a voltage for performing a memory operation to word lines of the selected memory block.

The page buffer35may be connected to the memory cell array20via the bit lines BL. The page buffer35may operate as a write driver or a sense amplifier. Specifically, when a program operation is performed, the page buffer35may operate as a write driver and apply a voltage according to data DATA to be stored in the memory cell array20to the bit lines BL. Meanwhile, when a read operation is performed, the page buffer35may operate as a sense amplifier and sense data DATA stored in the memory cell array20.

FIG.2is an example circuit diagram illustrating a semiconductor memory device according to some embodiments.

Referring toFIG.2, a memory cell array (e.g., the memory cell array20inFIG.1) of a semiconductor memory device according to some embodiments includes a common source line CSL, a plurality of bit lines BL, and a plurality of cell strings CSTR.

The plurality of bit lines BL may be arranged in two dimensions on a plane including a first direction X (also referred to as a first horizontal direction) and a second direction Y (also referred to as a second horizontal direction). For example, each of the bit lines BL may extend in the second direction Y and may be spaced apart from each other in the first direction X. The plurality of cell strings CSTR may be connected in parallel to each of the bit lines BL. The cell strings CSTR may be connected in common to the common source line CSL. That is, the plurality of cell strings CSTR may be disposed between the bit lines BL and the common source line CSL. As used herein, “an element A extends in a direction X” (or similar language) may mean that the element A extends longitudinally in the direction X.

Each of the cell strings CSTR may include a ground selection transistor GST connected to the common source line CSL, a string selection transistor SST connected to the bit line BL, and a plurality of memory cell transistors MCT disposed between the ground selection transistor GST and the string selection transistor SST. Each of the memory cell transistors MCT may include a data storage element. The ground selection transistor GST, the string selection transistor SST, and the memory cell transistors MCT may be connected in series.

The common source line CSL may be connected in common to sources of the ground selection transistors GST. Also, the ground selection lines GSL, a plurality of word lines WL11to WL1nand WL21to WL2n,and the string selection lines SSL may be disposed between the common source line CSL and the bit lines BL. The ground selection line GSL may be used as a gate electrode of the ground selection transistor GST, and the word lines WL11to WL1nand WL21to WL2nmay be used as gate electrodes of the memory cell transistors MCT. The string selection line SSL may be used as a gate electrode of the string selection transistor SST.

FIG.3is a schematic layout diagram of a semiconductor memory device according to some embodiments.FIG.4is a cross-sectional view taken along the line A-A ofFIG.3.FIG.5is an enlarged view of the portion R1ofFIG.4.FIG.6is a schematic layout diagram of a first impurity region and a second impurity region of the semiconductor memory device illustrated inFIGS.3to5.

Referring toFIGS.3to6, a semiconductor memory device according to some embodiments includes a cell structure CELL, a peripheral circuit structure PERI, and an input/output line structure380.

The cell structure CELL may include a cell substrate100, an insulating substrate101, mold structures MS1and MS2, interlayer insulation films140aand140b,channel structures CH, word line cut regions WC, bit lines BL, gate contacts162, a cell interconnection structure180, a first impurity region102, and a second impurity region104.

The cell substrate100may include a semiconductor substrate such as, for example, a silicon substrate (e.g., a portion of a silicon wafer), a germanium substrate, or a silicon-germanium substrate. In some embodiments, the cell substrate100may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. In some embodiments, the cell substrate100may include poly silicon (Si).

In some embodiments, the cell substrate100may include impurities and may have a first conductivity type. For example, the cell substrate100may include P-type impurities (e.g., boron (B), aluminum (Al), indium (In), gallium (Ga), or the like). In the following description, the first conductivity type may be a P-type, but is merely an example, and the first conductivity type may be an N-type.

The cell substrate100may include portions included in a cell array region CAR and an extension region EXT of the semiconductor memory device.

A memory cell array (e.g., the memory cell array20inFIG.1) including a plurality of memory cells may be formed in the cell array region CAR. For example, the channel structures CH, gate electrodes GSL, WL11to WL1n,WL21to WL2n,and SSL, bit lines BL, and the like, which will be described below, may be disposed in the cell array region CAR. In the following description, a surface of the cell substrate100on which the memory cell array is disposed may be referred to as a first surface100aor a front side. Meanwhile, a surface of the cell substrate100opposite to the first surface100a(or a front side) of the cell substrate100may be referred to as a second surface100bor a back side.

The extension region EXT may be defined around the cell array region CAR. For example, the extension region EXT may surround the cell array region CAR when viewed in a plan view. The gate electrodes GSL, WL11to WL1n,WL21to WL2n,and SSL, which will be described below, may be stacked on the extension region EXT in a stair shape.

The insulating substrate101may be formed around the cell substrate100. The insulating substrate101may form an insulating region around the cell substrate100. The insulating substrate101may include at least one of, for example, silicon oxide, silicon nitride, and silicon oxynitride, but is not limited thereto.

A bottom surface of the insulating substrate101may be coplanar with a bottom surface of the cell substrate100, but this is merely an example. In another example, the bottom surface of the insulating substrate101may be lower than the bottom surface of the cell substrate100.

In some embodiments, the cell substrate100and the insulating substrate101may also include portions included in a peripheral area PA of the semiconductor memory device. The peripheral area PA may be defined the outside of the extension region EXT. For example, the peripheral area PA may surround the extension region EXT when viewed in a plan view. A contact plug360, which will be described below, may be disposed in the peripheral area PA.

The mold structures MS1and MS2may be formed on the first surface100aof the cell substrate100. The mold structures MS1and MS2may include the plurality of gate electrodes GSL, WL11to WL1n,WL21to WL2n,and SSL stacked on the cell substrate100and a plurality of mold insulation films110and115. The gate electrodes GSL, WL11to WL1n,WL21to WL2n,and SSL and the mold insulating layers110and115may each have a layered structure that extends parallel to the first surface100aof the cell substrate100. The gate electrodes GSL, WL11to WL1n,WL21to WL2n,and SSL may be separated from one another by the mold insulation films110and115and sequentially stacked on the cell substrate100.

In some embodiments, the mold structures MS1and MS2may include a first mold structure MS1and a second mold structure MS2that are sequentially stacked on the cell substrate100.

The first mold structure MS1may include first gate electrodes GSL, and WL11to WL1nand mold insulation films110that are alternately stacked on the cell substrate100. In some embodiments, the first gate electrodes GSL and WL11to WL1nmay include a ground selection line GSL and a plurality of first word lines WL11to WL1nthat are sequentially stacked on the cell substrate100. The number and arrangement of the ground selection line GSL and the first word lines WL11to WL1nare merely examples, and those number and arrangement are not limited to that shown in the drawings.

The second mold structure MS2may include second gate electrodes WL21to WL2n,and SSL and second mold insulation films115that are alternately stacked on the first mold structure MS1. In some embodiments, the second gate electrodes WL21to WL2n,and SSL may include a plurality of second word lines WL21to WL2nand a string selection line SSL that are sequentially stacked on the first mold structure MS1. The number and arrangement of the second word lines WL21to WL2nand the string selection line SSL are merely examples, and those number and arrangement are not limited to that shown in the drawings.

The gate electrodes GSL, WL11to WL1n,WL21to WL2n,and SSL may each include a conductive material, for example, a metal such as tungsten (W), cobalt (Co), and nickel (Ni), or a semiconductor material, such as silicon, but are not limited thereto.

The mold insulation films110and115may each include an insulating material, for example, at least one of silicon oxide, silicon nitride, or silicon oxynitride, but are not limited thereto.

The interlayer insulation film140aand140bmay be formed on the first surface100aof the cell substrate100to cover the mold structures MS1and MS2. In some embodiments, the interlayer insulation films140aand140bmay include a first interlayer insulation film140aand a second interlayer insulation film140bthat are sequentially stacked on the cell substrate100. The first interlayer insulation film140amay cover the first mold structure MS1and the second interlayer insulation film140bmay cover the second mold structure MS2. The interlayer insulation films140aand140bmay include, for example, at least one of silicon oxide, silicon oxynitride, or a low dielectric constant (low-k) material having a lower dielectric constant than silicon oxide, but are not limited thereto.

A plurality of channel structures CH may be formed in the cell array region CAR of the cell substrate100. Each of the channel structures CH may extend in a vertical direction (also referred to as a third direction Z) intersecting the first surface100aof the cell substrate100to penetrate through the mold structures MS1and MS2. For example, the channel structure CH may have a pillar shape (e.g., a columnar shape) that extends in the third direction Z. Accordingly, the channel structure CH may intersect the plurality of gate electrodes GSL, WL11to WL1n,WL21to WL2n,and SSL. In some embodiments, each of the channel structures CH may have a bent portion between the first mold structure MS1and the second mold structure MS2. In some embodiments, the channel structure CH may extend through the plurality of gate electrodes GSL, WL11to WL1n,WL21to WL2n,and SSL.

As shown inFIG.5, each of the channel structures CH may include a semiconductor pattern130and a data storage film132.

The semiconductor pattern130may extend in the third direction Z to penetrate through the mold structures MS1and MS2. Although the semiconductor pattern130is shown as a cup shape, this is merely an example. In some embodiments, the semiconductor pattern130may have various shapes such as a cylindrical shape, a rectangular barrel shape, and a solid pillar shape. The semiconductor pattern130may include semiconductor materials, such as, for example, single crystal silicon, polycrystalline silicon, organic semiconductor matter and/or carbon nanostructures.

In some embodiments, the semiconductor pattern130may penetrate through the first surface100aof the cell substrate100. For example, as shown inFIG.5, one end of the semiconductor pattern130may be buried inside the cell substrate100. The semiconductor pattern130may improve contact resistance by increasing a contact area with the cell substrate100. In some embodiments, the data storage film132may extend from the first surface100aof the cell substrate100.

The data storage film132may be interposed between the semiconductor pattern130and the respective gate electrodes GSL, WL11to WL1n,WL21to WL2n,and SSL. For example, the data storage film132may extend along the outer side surfaces of the semiconductor pattern130. The data storage film132may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant material having a higher dielectric constant than that of silicon oxide. The high dielectric constant material may include, for example, at least one of aluminum oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, lanthanum hafnium oxide, lanthanum aluminum oxide, dysprosium scandium oxide, or a combination of these materials.

In some embodiments, the data storage film132may be formed by multi-films or a plurality of films. For example, as shown inFIG.5, the data storage film132may include a tunnel insulation film132a,a charge storage film132b,and a blocking insulation film132c,which are sequentially stacked on the outer side surface of the semiconductor pattern130.

The tunnel insulation film132amay include, for example, a silicon oxide or a high dielectric constant material (e.g., aluminum oxide (Al2O3) and/or hafnium oxide (HfO2)) having a higher dielectric constant than that of silicon oxide. The charge storage film132bmay include, for example, silicon nitride. The blocking insulation film132cmay include, for example, a silicon oxide or a high dielectric constant material (e.g., aluminum oxide (Al2O3) and/or hafnium oxide (HfO2)) having a higher dielectric constant than that of silicon oxide.

In some embodiments, the channel structure CH may further include a filling pattern134. The filling pattern134may be formed to fill the inside of the semiconductor pattern130which has a cup shape. The filling pattern134may include, for example, an insulating material such as silicon oxide, but is not limited thereto.

In some embodiments, the channel structure CH may further include a first channel pad136. The first channel pad136may be formed to be connected to the other end of the semiconductor pattern130. The first channel pad136may include, for example, impurity-doped polysilicon, but is not limited thereto.

In some embodiments, a plurality of channel structures CH may be arranged in a zigzag form. For example, as shown inFIG.3, a plurality of channel structures CH may be arranged to be offset from each other in the second direction X and the first direction Y. The plurality of channel structures CH arranged in the zigzag form may further improve the degree of integration of the semiconductor memory device. The number and arrangement of the channel structures CH are merely examples, and those number and arrangement are not limited to that shown in the drawings. In some embodiments, the plurality of channel structures CH may be arranged in a honeycomb shape.

A plurality of word line cut regions WC may be arranged in two dimensions on a plane including the first direction X and the second direction Y. For example, the word line cut regions WC may each extend in the first direction X and may be arranged apart from each other along the second direction Y.

The mold structures MS1and MS2may be divided by the word line cut regions WC to form a plurality of memory cell blocks (e.g., the memory cell blocks BLK1to BLKn ofFIG.1). The word line cut regions WC may include an insulating material, for example, at least one of silicon oxide, silicon nitride, or silicon oxynitride, but are not limited thereto.

The bit lines BL may be formed on the mold structures MS1and MS2. The bit lines BL may intersect the word line cut regions WC. For example, each of the bit lines BL may extend in the second direction Y and may be arranged apart from each other along the first direction X.

Each of the bit lines BL may be connected to the channel structures CH arranged along the second direction Y. For example, a bit line contact182to be connected to the first channel pad136may be formed inside the second interlayer insulation film140b.The bit line BL may be electrically connected to the channel structures CH through the bit line contact182.

A plurality of gate contacts162may be connected to the plurality of gate electrodes GSL, WL11to WL1n,WL21to WL2n,and SSL, respectively. For example, the gate contacts162may lie on the mold structures MS1and MS2, extend in the third direction Z, and may each be connected to the corresponding gate electrode.

The cell interconnection structure180may be formed on the mold structures MS1and MS2. For example, a first inter-wiring insulation film142may be formed on the second interlayer insulation film140b,and the cell interconnection structure180may be formed inside the first inter-wiring insulation film142. The cell interconnection structure180may be electrically connected to the bit lines BL and the gate contacts162. Accordingly, the cell interconnection structure180may be electrically connected to the channel structure CH and the gate electrodes GSL, WL11to WL1n,WL21to WL2n,and SSL. The number of layers and arrangement of the cell interconnection structure180are merely examples, and the present disclosure is not limited thereto.

The first impurity region102may be formed inside the cell substrate100adjacent to the second surface100b.For example, the first impurity region102may extend inward from the second surface100bof the cell substrate100. The first impurity region102may be of a second conductivity type that is different from the first conductivity type. For example, the first impurity region102may be formed by ion-implanting a high concentration of N-type impurities (e.g., phosphorus (P) or arsenic (As)) into the cell substrate100of the P-type. The first impurity region102may be provided as a common source line (e.g., the common source line CSL inFIG.2) of the semiconductor memory device according to some embodiments.

In some embodiments, a source plate310may be formed on the second surface100bof the cell substrate100. The source plate310may be connected to the first impurity region102. For example, the source plate310may cover the first impurity region102. The source plate310may include, for example, a metal such as tungsten (W), cobalt (Co), nickel (Ni), and the like, but is not limited thereto.

In some embodiments, the first impurity region102may overlap a plurality of channel structures CH in the third direction Z. For example, as shown inFIG.6, the first impurity region102may be formed in the cell array region CAR of the cell substrate100. In some embodiments, the first impurity region102may be a plate-shaped impurity region extending in a plane including the first direction X and the second direction Y. As used herein, “an element A overlapping an element B in a direction X” (or similar language) means that there is at least one line that extends in the direction X and intersects both the elements A and B.

The second impurity region104may be formed in the cell substrate100and may be spaced apart from the first impurity region102. The second impurity region104may have the first conductivity type with an impurity concentration higher than that of the cell substrate100. For example, the second impurity region104may be formed by ion-implanting a high concentration of P-type impurities (e.g., boron (B), aluminum (Al), indium (In), or gallium (Ga)) into the P-type cell substrate100.

In some embodiments, the second impurity region104may be adjacent to the second surface100bof the cell substrate100. For example, the second impurity region104may extend inward from the second surface100bof the cell substrate100.

In some embodiments, a depth D2of the second impurity region104may be greater than a depth D1of the first impurity region102with respect to the second surface100bof the cell substrate100.

In some embodiments, a conductive pad320may be formed on the second surface100bof the cell substrate100. The conductive pad320may be connected to the second impurity region104. For example, the conductive pad320may cover the second impurity region104. The conductive pad320may include, for example, a metal such as tungsten (W), cobalt (Co), nickel (Ni), and the like, but is not limited thereto.

In some embodiments, the source plate310and the conductive pad320may be formed on the same level (e.g., on the same level in the third direction Z). As used herein, “elements A and B formed on the same level” (or similar language) may mean that the elements A and B are formed by the same fabricating process.

In some embodiments, the second impurity region104may surround at least a part of the first impurity region102when viewed in a plan view. For example, as shown inFIG.6, the second impurity region104may extend along at least a part of a side surface of the first impurity region102.

In some embodiments, the second impurity region104may not overlap a plurality of channel structures CH in the third direction Z. For example, as shown inFIG.6, the second impurity region104may be formed in the extension region EXT of the cell substrate100.

In some embodiments, the second impurity region104may include a line-shaped impurity region extending along the side surface of the first impurity region102. For example, as shown inFIG.6, the second impurity region104may include first line-shaped impurity regions104xextending in the first direction X and second line-shaped impurity regions104yextending in the second direction Y. In some embodiments, the first line-shaped impurity regions104xand the second line-shaped impurity regions104ymay be connected to each other to completely surround the first impurity region102.

The peripheral circuit structure PERI may include a peripheral circuit board200, peripheral circuit elements PT, and peripheral circuit interconnection structures260.

The peripheral circuit board200may include a semiconductor substrate such as, for example, a silicon substrate (e.g., a portion of a silicon wafer), a germanium substrate, or a silicon-germanium substrate. Alternatively, the peripheral circuit board200may include an SOI substrate or a GOI substrate.

The peripheral circuit elements PT may be formed on the peripheral circuit board200. The peripheral circuit elements PT may constitute the peripheral circuit (e.g., the peripheral circuit30inFIG.1) that controls the operation of the semiconductor memory device. For example, the peripheral circuit elements PT may include a control logic (e.g., the control logic37inFIG.1), a row decoder (e.g., the row decoder33inFIG.1), a page buffer (e.g., the page buffer35inFIG.1), and the like. In the following description, the surface of the peripheral circuit board200on which the peripheral circuit elements PT are disposed may be referred to as a front side of the peripheral circuit board200, and, a surface of the peripheral circuit board200opposite to the front side of the peripheral circuit board200may be referred to as a back side of the peripheral circuit board200.

The peripheral circuit elements PT may include, for example, a transistor, but are not limited thereto. For example, the peripheral circuit elements PT may include various active elements, such as a transistor, as well as various passive elements, such as a capacitor, a register, an inductor, and the like.

The peripheral circuit interconnection structure260may be formed on the peripheral circuit element PT. For example, the second inter-wiring insulation film240may be formed on the front side of the peripheral circuit board200, and the peripheral circuit interconnection structure260may be formed in the second inter-wiring insulation film240. The peripheral circuit interconnection structure260may be electrically connected to the peripheral circuit element PT. The number of layers and arrangement of the peripheral circuit interconnection structure260are merely examples, and the present disclosure is not limited thereto.

In some embodiments, the cell structure CELL may be stacked on the peripheral circuit structure PERI. For example, the cell structure CELL may be stacked on the second inter-wiring insulation film240.

In some embodiments, the first surface100aof the cell substrate100may face the peripheral circuit structure PERI. For example, the front side (i.e., the first surface100a) of the cell substrate100may face the front side of the peripheral circuit board200.

In some embodiments, the semiconductor memory device may have a chip-to-chip (C2C) structure. The C2C structure may be a structure in which an upper semiconductor chip, including a cell structure CELL, is fabricated on a first wafer (e.g., the cell substrate100), a lower semiconductor chip, including a peripheral circuit structure PERI, is fabricated on a second wafer (e.g., the peripheral circuit board200), different from the first wafer, and then, the upper semiconductor chip and the lower semiconductor chip are connected to each other by, for example, a bonding method.

For example, the bonding method may refer to a method of electrically connecting a first bonding metal190formed in an uppermost metal layer of the upper semiconductor chip and a second bonding metal290formed in an uppermost metal layer of the lower semiconductor chip to each other. For example, when the bonding metal is formed of copper (Cu), the bonding method may be a Cu—Cu bonding method. However, this is merely an example, and the first bonding metal190and the second bonding metal290may be made of various other metals such as aluminum Al or tungsten (W).

When the first bonding metal190and the second bonding metal290are bonded to each other, the cell interconnection structure180may be connected to the peripheral circuit interconnection structure260. Accordingly, the bit line BL and/or each of the gate electrodes GSL, WL11to WL1n,WL21to WL2n,and SSL may be electrically connected to the peripheral circuit element PT.

The input/output line structure380may be formed on the second surface100bof the cell substrate100. For example, a third interlayer insulation film340that covers the cell substrate100and the insulating substrate101may be formed on the second surface100bof the cell substrate100. The input/output line structure380may be formed on the third interlayer insulation film340. The number of layers and arrangement of the input/output line structure380are merely examples, and the present disclosure is not limited thereto.

In some embodiments, the third interlayer insulation film340may cover the source plate310and/or the conductive pad320. The third interlayer insulation film340may include, for example, at least one of silicon oxide, silicon oxynitride, or a low dielectric constant (low-k) material having a lower dielectric constant than silicon oxide, but are not limited thereto.

The input/output line structure380may be electrically connected to the cell structure CELL and/or the peripheral circuit structure PERI.

In some embodiments, a source contact315that connects the input/output line structure380to the first impurity region102may be formed. For example, the source contact315may extend in the third direction Z in the third interlayer insulation film340and connect the source plate310to the input/output line structure380. The first impurity region102may be electrically connected to the input/output line structure380via the source plate310and the source contact315. The source contact315may include, for example, a metal such as tungsten (W), cobalt (Co), nickel (Ni), and the like, but is not limited thereto.

In some embodiments, an erase control contact325that connects the input/output line structure380to the second impurity region104may be formed. For example, the erase control contact325may extend in the third direction Z in the third interlayer insulation film340and connect the conductive pad320to the input/output line structure380. The second impurity region104may be electrically connected to the input/output line structure380via the conductive pad320and the erase control contact325. The erase control contact325may include, for example, a metal such as tungsten (W), cobalt (Co), nickel (Ni), and the like, but is not limited thereto.

In some embodiments, a width (e.g., a width in a horizontal direction) of the source contact315and a width (e.g., a width in a horizontal direction) of the erase control contact325may decrease in a direction toward the second surface100bof the cell substrate100. This may be due to the nature of the etching process for forming the source contact315and the erase control contact325. In some embodiments, the source contact315and the erase control contact325may be formed on the same level.

In some embodiments, a contact plug360that connects the input/output line structure380to the cell interconnection structure180may be formed. The contact plug360may be formed in the peripheral area PA. For example, the contact plug360may extend in the third direction Z and penetrate through the third interlayer insulation film340, the insulating substrate101, the first interlayer insulation film140a,and the second interlayer insulation film140b.The cell interconnection structure180may be electrically connected to the input/output line structure380via the contact plug360.

In some embodiments, a width (e.g., a width in a horizontal direction) of the contact plug360may decrease in a direction toward the cell interconnection structure180. This may be due to the nature of the etching process for forming the contact plug360. In some embodiments, the source contact315, the erase control contact325, and the contact plug360may be formed on the same level.

In some embodiments, a capping insulation film342that covers the input/output line structure380may be formed. For example, the capping insulation film342may include a pad opening OP that exposes a portion of the input/output line structure380. The portion of the input/output interconnection structure380exposed by the pad opening OP may function as an input/output pad.

FIG.7is a view for describing a read operation of a semiconductor memory device according to some embodiments.

Referring toFIG.7, a semiconductor memory device according to some embodiments performs a read operation through a first impurity region102.

For example, during a read operation of the semiconductor memory device according to some embodiments, electrons of the semiconductor pattern130may flow to the first impurity region102through the cell substrate100, and may exit through the source plate310and/or the source contact315connected to the first impurity region102.

FIG.8is a view for describing an erase operation of a semiconductor memory device according to some embodiments.

Referring toFIG.8, a semiconductor memory device according to some embodiments performs an erase operation through a second impurity region104.

For example, when a high voltage is applied to the second impurity region104through the erase control contact325and/or the conductive pad320, holes may be supplied to the semiconductor pattern130through the cell substrate100in which the second impurity region104is formed. Accordingly, electrons stored in the charge storage layer132bmay pass through a tunnel insulation film132aand be tunneled into the semiconductor pattern130, and an erase operation of the semiconductor memory device may be performed.

In order to secure a connection path between a cell string (e.g., the cell string CSTR inFIG.2) and a common source line (e.g., the common source line CSL inFIG.2) in a semiconductor memory device, a common source line (hereinafter also referred to as a side-connected source structure) connected to a side surface of a semiconductor pattern (e.g., the semiconductor pattern130inFIG.5) has been proposed. However, due to high process cost of the side-connected source structure, a semiconductor memory device having a C2C structure has been studied as an alternative to the side-connected source structure. As described above, in the C2C structure, an upper chip and a lower chip can be connected to each other by a bonding method, and accordingly, a semiconductor pattern may be simply exposed by performing a planarization process (e.g., a chemical mechanical polishing (CMP) process) or the like on a wafer (e.g., the first wafer) of the upper chip. That is, in the C2C structure, the common source line connected to the semiconductor pattern may be easily formed.

Meanwhile, the semiconductor memory device having a C2C structure may have degraded erase performance. For example, a cell string (e.g., the cell string CSTR inFIG.2) including an erase control transistor may be provided for an erase operation of the semiconductor memory device. The erase control transistor may perform an erase operation of the semiconductor memory device by using gate induced drain leakage (GIDL). However, if the side-connected source structure is omitted as described above, the distance between a gate and a drain of the erase control transistor increases, which may lead to the degradation of erase control performance using GIDL.

In contrast, as described with reference toFIGS.3to8, the semiconductor memory device according to some embodiments may perform an erase operation using the cell substrate100connected to the semiconductor pattern130and the second impurity region104formed in the cell substrate100. For example, an erase operation of the semiconductor memory device according to some embodiments may be performed as holes are supplied to the semiconductor pattern130by a high voltage applied to the second impurity region104. That is, since the semiconductor memory device according to some embodiments may perform an erase operation using the cell substrate100provided as a body, it may have enhanced erase control performance as compared to the semiconductor memory device using GIDL. Accordingly, even with the C2C structure, a semiconductor memory device having excellent erase control performance may be provided.

FIG.9is an enlarged view for describing a semiconductor memory device according to some embodiments.FIG.10is a schematic layout diagram of a first impurity region and a second impurity region of the semiconductor memory device illustrated inFIG.9. For convenience of description, the repeated parts described with reference toFIGS.1to8will be briefly described or omitted.

Referring toFIGS.9and10, in a semiconductor memory device according to some embodiments, a second impurity region104may include multiple impurity regions (e.g., island-shaped impurity regions) that are spaced apart from each other.

For example, as shown inFIG.10, the second impurity region104may include a plurality of impurity regions (also referred to as a plurality of island-shaped impurity regions)104ithat are spaced apart from each other. The island-shaped impurity regions104iare illustrated as being arranged along side surfaces of a first impurity region102extending in the second direction Y, but this is merely an example. In some embodiments, the island-shaped impurity regions104imay be arranged along side surfaces of the first impurity region102extending in the first direction X. In still some other embodiments, the island-shaped impurity regions104imay be arranged along the edge of the first impurity region102.

In some embodiments, an erase control contact325may be in contact with the second impurity region104. For example, the conductive pad320described with reference toFIGS.3to8may be omitted, and a plurality of erase control contacts in contact with the island-shaped second impurity regions104may be formed. However, this is merely an example, and a conductive pad320that covers the second impurity region104may be formed. For example, a plurality of conductive pads320that cover the island-shaped second impurity regions104may be formed.

FIG.11is a cross-sectional view illustrating a semiconductor memory device according to some embodiments.FIG.12is a schematic layout diagram of a first impurity region and a second impurity region of the semiconductor memory device illustrated inFIG.11. For convenience of description, the repeated parts described with reference toFIGS.1to8will be briefly described or omitted.

Referring toFIGS.11and12, in a semiconductor memory device according to some embodiments, a first impurity region102may be formed in a cell array region CAR and an extension region EXT. For example, the first impurity region102may be a plate-shaped impurity region that are provided in the cell array region CAR and the extension region EXT.

In some embodiments, the second impurity region104may surround at least a part of the first impurity region102when viewed in a plan view. For example, the second impurity region104may be formed in the cell substrate100of the peripheral region PA.

In some embodiments, the second impurity region104may include a line-shaped impurity region extending along the side surface of the first impurity region102. For example, the second impurity region104may include first line-shaped impurity regions104xextending in the first direction X and second line-shaped impurity regions104yextending in the second direction Y.

FIG.13is a cross-sectional view illustrating a semiconductor memory device according to some other embodiments.FIG.14is a schematic layout diagram of a first impurity region and a second impurity region of the semiconductor memory device illustrated inFIG.13. For convenience of description, the repeated parts described with reference toFIGS.1to12will be briefly described or omitted.

Referring toFIGS.13and14, in a semiconductor memory device according to some embodiments, a second impurity region104may be adjacent to a first surface100aof a cell substrate100. For example, the second impurity region104may extend inward from the first surface100aof the cell substrate100.

In some embodiments, the second impurity region104may be formed in a portion of the cell substrate100in the peripheral region PA. The second impurity region104may be exposed from mold structures MS1and MS2. That is, the second impurity region104may not overlap the mold structures MS1and MS2in the third direction Z.

In some embodiments, a conductive pad320may be formed on the first surface100aof the cell substrate100. The conductive pad320may be connected to the second impurity region104. For example, the conductive pad320may cover the second impurity region104.

In some embodiments, an erase control contact325may connect a cell interconnection structure180to the second impurity region104. For example, the erase control contact325may extend in the third direction Z in interlayer insulation films140aand140band connect the conductive pad320to the cell interconnection structure180. The second impurity region104may be electrically connected to the cell interconnection structure180via the conductive pad320and the erase control contact325. In some embodiments, the erase control contact325and gate contacts162may be formed on the same level.

FIG.15is a cross-sectional view illustrating a semiconductor memory device according to some embodiments.FIG.16is a schematic layout diagram of a first impurity region and a second impurity region of the semiconductor memory device illustrated inFIG.15. For convenience of description, the repeated parts described with reference toFIGS.1to14will be briefly described or omitted.

Referring toFIGS.15and16, in a semiconductor memory device according to some embodiments, a second impurity region104may include multiple impurity regions (e.g., island-shaped impurity regions) that are spaced apart from each other.

For example, as shown inFIG.16, the second impurity region104may include a plurality of impurity regions (also referred to as a plurality of island-shaped impurity regions)104ithat are spaced apart from each other.

In some embodiments, the second impurity region104may be adjacent to a first surface100aof the cell substrate100. In some embodiments, the second impurity region104may be formed in a portion of the cell substrate100in the peripheral region PA.

FIG.17is a cross-sectional view illustrating a semiconductor memory device according to some other embodiments.FIG.18is an enlarged view of the portion R2ofFIG.17. For convenience of description, the repeated parts described with reference toFIGS.1to16will be briefly described or omitted.

Referring toFIGS.17and18, in a semiconductor memory device according to some embodiments, a channel structure CH may further include a second channel pad138.

The second channel pad138may be formed to be connected to one end of a semiconductor pattern130. The second channel pad138may include, for example, impurity-doped polysilicon, but is not limited thereto. In some embodiments, the second channel pad138may be an epitaxial pattern formed by a selective epitaxial growth (SEG) process.

In some embodiments, the second channel pad138may penetrate through a first surface100aof a cell substrate100. For example, one end of the second channel pad138may be buried inside the cell substrate100. The second channel pad138may improve contact resistance by increasing a contact area with the cell substrate100.

In some embodiments, at least a portion of the second channel pad138may overlap a gate electrode adjacent to the cell substrate100among gate electrodes GSL, WL11to WL1n,WL21to WL2n,and SSL in a horizontal direction (e.g., the first direction X or the second direction Y). For example, the second channel pad138may overlap a ground selection line GSL in the horizontal direction (e.g., the first direction X or the second direction Y).

Hereinafter, a method of fabricating a semiconductor memory device according to example embodiments will be described with reference toFIGS.1to38.

FIGS.19to31are views illustrating methods of fabricating a semiconductor memory device according to some embodiments. For convenience of description, the repeated parts described with reference toFIGS.1to18will be briefly described or omitted.

Referring toFIG.19, a first preliminary mold pMS1and a first preliminary channel pCH1are formed on a base substrate100P.

The first preliminary mold pMS1may be formed on a front side of the base substrate100P. The first preliminary mold pMS1may include a plurality of first mold insulation films110and a plurality of first mold sacrificial films112that are alternately stacked on the base substrate100P. The first mold sacrificial films112may include a material having an etching selectivity with respect to the first mold insulation film110. For example, the first mold insulation film110may include a silicon oxide layer, and the first mold sacrificial film112may include a silicon nitride layer.

The first preliminary mold pMS1in an extension region EXT may be patterned in a stair shape. Accordingly, the first preliminary mold pMS1in the extension region EXT may be stacked in a stair shape.

The first preliminary channel pCH1may penetrate through the first preliminary mold pMS1in a cell array region CA. Also, the first preliminary channel pCH1may be connected to the base substrate100P. For example, a first interlayer insulation film140athat covers the first preliminary mold pMS1may be formed on the base substrate100P. The first preliminary channel pCH1may penetrate through the first interlayer insulation film140aand the first preliminary channel pCH1and may be connected to the base substrate100P.

The first preliminary channel pCH1may include a material having an etching selectivity with respect to a first mold insulation film110and a first mold sacrificial film112. For example, the first preliminary channel pCH1may include poly silicon (Si).

Referring toFIG.20, a second preliminary mold pMS2and a second preliminary channel pCH2are formed on the first preliminary mold pMS1.

The second preliminary mold pMS2may include a plurality of second mold insulation films115and a plurality of second mold sacrificial films117that are alternately stacked on the first preliminary mold pMS1. Since formation of the second preliminary mold pMS2is similar to formation of the first preliminary mold pMS1, a detailed description thereof will not be provided below.

The second preliminary channel pCH2may penetrate through the second preliminary mold pMS2in the cell array region CA. In addition, the second preliminary channel pCH2may be connected to the first preliminary channel pCH1. Since formation of the second preliminary channel pCH2is similar to formation of the first preliminary channel pCH1, a detailed description thereof will not be provided below.

Referring toFIG.21, a channel structure CH is formed.

For example, the first preliminary channel pCH1and the second preliminary channel pCH2may be selectively removed. Thereafter, the channel structure CH that replaces a region where the first preliminary channel pCH1and the second preliminary channel pCH2are removed may be formed. Accordingly, the channel structure CH may be formed on the cell array region CA.

Referring toFIG.22, a word line cut region WC is formed.

The word line cut region WC may extend in the first direction (e.g., the first direction X inFIG.3) and cut the first preliminary mold pMS1and the second preliminary mold pMS2.

For example, the mold sacrificial films112and117exposed by the word line cut region WC may be selectively removed. Thereafter, the gate electrodes GSL, WL11to WL1n, WL21to WL2n,and SSL that replace regions where the mold sacrificial films112and117are removed may be formed. Accordingly, a first mold structure MS1including a plurality of first gate electrodes GSL and WL11to WL1nand a second mold structure MS2including a plurality of second gate electrodes WL21to WL2nand SSL may be formed. After the first mold structure MS1and the second mold structure MS2are formed, the word line cut region WC may be filled with a filling material.

Referring toFIG.24, gate contacts162, a bit line contact182, a bit line BL, and a cell interconnection structure180are formed on the mold structures MS1and MS2.

A plurality of gate contacts162may be connected to the plurality of gate electrodes GSL, WL11to WL1n,WL21to WL2n,and SSL, respectively. The bit line BL may be formed on the second interlayer insulation film140b.The bit line BL may be electrically connected to the channel structures CH through the bit line contact182. The cell interconnection structure180may be electrically connected to the bit lines BL and the gate contacts162.

Referring toFIGS.25and26, the cell structure CELL is stacked on the peripheral circuit structure PERI.

In some embodiments, the cell structure CELL and the peripheral circuit structure PERI may be stacked such that the front side of the base substrate100P faces the front side of the peripheral circuit board200. For example, the cell interconnection structure180may be stacked on the peripheral circuit interconnection structure260.

For example, the first bonding metal190formed in the uppermost metal layer of the cell structure CELL and the second bonding metal290formed in the uppermost metal layer of the peripheral circuit structure PERI may be bonded to each other. When the first bonding metal190and the second bonding metal290are formed of copper (Cu), the bonding method may be a Cu-Cu bonding method. However, this is merely an example, and the first bonding metal190and the second bonding metal290may be made of various other metals such as aluminum Al or tungsten (W).

Referring toFIGS.26and27, one end of the semiconductor pattern130is exposed.

For example, a planarization process or a recess process may be performed on a back side of the base substrate100P. Accordingly, one end of the channel structure CH may be exposed by removing at least a portion of the base substrate100P. Also, a portion of the data storage film132of the exposed channel structure CH may be removed.

In some embodiments, one end of the semiconductor pattern130may protrude further than one end of the data storage film132. In some embodiments, one end of the data storage film132may be coplanar with the surface of the first mold insulation film110.

Referring toFIG.28, the cell substrate100connected to the semiconductor pattern130is formed.

For example, the cell substrate100may be deposited on the surface of the first mold insulation film110from which the base substrate100P is removed. The cell substrate100may include the first surface100aon which the channel structure CH and the gate electrodes GSL, WL11to WL1n,WL21to WL2n,and SSL are disposed and the second surface100bopposed to the first surface100a.

In some embodiments, the cell substrate100may include impurities and may be of a first conductivity type. For example, the cell substrate100may include P-type impurities (e.g., boron (B), aluminum (Al), indium (In), gallium (Ga), or the like).

Referring toFIG.29, a first impurity region102and a second impurity region104are formed in the cell substrate100.

For example, a first ion-implantation process may be performed on the second surface100bof the cell substrate100. Accordingly, the first impurity region102may be formed in the cell substrate100adjacent to the second surface100b.The first impurity region102may be of a second conductivity type that is different from the first conductivity type. For example, the first impurity region102may be formed by ion-implanting a high concentration of N-type impurities (e.g., phosphorus (P) or arsenic (As)) into the cell substrate100of the P-type.

In addition, for example, a second ion-implantation process may be performed on the second surface100bof the cell substrate100. Accordingly, the second impurity region104may be formed in the cell substrate100adjacent to the second surface100b.The second impurity region104may have the first conductivity type with an impurity concentration higher than that of the cell substrate100. For example, the second impurity region104may be formed by ion-implanting a high concentration of P-type impurities (e.g., boron (B), aluminum (Al), indium (In), or gallium (Ga)) into the P-type cell substrate100.

Referring toFIG.30, a dopant activation process is performed on the second surface100bof the cell substrate100.

As the dopant activation process is performed, the dopant of the first impurity region102and/or the second impurity region104may be activated. In some embodiments, the dopant activation process may include a laser annealing process. If the laser annealing process is used, even in a C2C structure (e.g., after the cell structure CELL is stacked on the peripheral circuit structure PERI), the dopant of the first impurity region102and/or the second impurity region104may be activated. If a general annealing process is performed, the semiconductor memory device having a C2C structure may be damaged due to the relatively low melting point of the cell interconnection structure180and/or the peripheral circuit interconnection structure260. In contrast, the laser annealing process can be performed locally on the second surface100bof the cell substrate100, and thus the dopant of the first impurity region102and/or the second impurity region104may be activated without damaging the cell interconnection structure180and/or the peripheral circuit interconnection structure260.

Referring toFIG.31, the source plate310, the conductive pad320, the source contact315, and the erase control contract325are formed on the second surface100bof the cell substrate100.

The source plate310may be connected to the first impurity region102. The conductive pad320may be connected to the second impurity region104. In addition, the third interlayer insulation film340that covers the source plate310and the conductive pad320may be formed. The source contact315may extend in the third direction Z in the third interlayer insulation film340and may be connected to the source plate310. The erase control contact325may extend in the third direction Z in the third interlayer insulation film340and may be connected to the conductive pad320.

In some embodiments, the contact plug360connected to the cell interconnection structure180may be formed. The contact plug360may be formed in the peripheral area PA. For example, the contact plug360may extend in the third direction Z and penetrate through the third interlayer insulation film340, the insulating substrate101, the first interlayer insulation film140a, and the second interlayer insulation film140b.

Referring back toFIG.4, the input/output line structure380and the capping insulation film342are formed on the third interlayer insulation film340. Accordingly, the semiconductor memory device described above with reference toFIGS.3to8may be fabricated.

FIGS.32to35are views illustrating methods of fabricating a semiconductor memory device according to some other embodiments. For convenience of description, the repeated parts described with reference toFIGS.1to31will be briefly described or omitted.

Referring toFIG.32, a second impurity region104is formed in a base substrate100P.

For example, a first ion-implantation process may be performed on the front side of the base substrate100P. Accordingly, the second impurity region104adjacent to the front side of the base substrate100P may be formed. The second impurity region104may have the first conductivity type with an impurity concentration higher than that of the base substrate100P. For example, the second impurity region104may be formed by ion-implanting a high concentration of P-type impurities (e.g., boron (B), aluminum (Al), indium (In), or gallium (Ga)) into the P-type base substrate100P.

In some embodiments, the second impurity region104may be formed in the cell substrate100of the peripheral region PA.

The second impurity region104may be formed before the first preliminary mold pMS1and the first preliminary channel pCH1are formed, or may be formed after the first preliminary mold pMS1and the first preliminary channel pCH1are formed.

In some embodiments, the conductive pad320may be formed on the front side of the base substrate100P. The conductive pad320may be connected to the second impurity region104.

Referring toFIG.33, the erase control contact325connected to the second impurity region104is formed.

For example, the processes described above with reference toFIGS.20to23may be performed. The gate electrode162and the erase control contact325may be formed. The erase control contact325may extend in the third direction Z in the interlayer insulation films140aand140band may be connected to the conductive pad320. In some embodiments, the erase control contact325and the gate contact162may be formed on the same level.

Thereafter, a bit line contact182, a bit line BL, and a cell interconnection structure180may be formed on the mold structures MS1and MS2. Since formation of the gate contact162, the bit line contact182, the bit line BL, and the cell interconnection structure180is similar to formation described above with reference toFIG.24, detailed descriptions thereof will not be provided below.

Referring toFIG.34, a cell structure CELL is stacked on a peripheral circuit structure PERI.

Since stacking of the cell structure CELL on the peripheral circuit structure PERI is similar to processes described above with reference toFIGS.25and26, a detailed description thereof will not be provided below. After the cell structure CELL is stacked on the peripheral circuit structure PERI, at least a portion of the base substrate100P may be removed to form the cell substrate100. For example, an insulating substrate101that replaces a portion of the base substrate100P may be formed. Accordingly, the cell substrate100in which the second impurity region104is formed may be provided.

Referring toFIG.35, a first impurity region102is formed in the cell substrate100.

Since formation of the first impurity region102is similar to processes described above with reference toFIG.29, a detailed description thereof will not be provided below.

Thereafter, the processes described above with reference toFIGS.31and4may be performed. Accordingly, the semiconductor memory device described above with reference toFIGS.11and12may be fabricated.

FIGS.36to38are views illustrating methods of fabricating a semiconductor memory device according to some other embodiments. For convenience of description, the repeated parts described with reference toFIGS.1to31will be briefly described or omitted. For reference,FIG.36is a view illustrating an intermediate stage of fabrication performed after the structure inFIG.20is formed.

Referring toFIG.36, a channel structure CH including a second channel pad138is formed.

For example, the first preliminary channel pCH1and the second preliminary channel pCH2may be selectively removed. Thereafter, a second channel pad138grown from the base substrate100P may be formed by a selective epitaxial growth (SEG) process. Accordingly, the channel structure CH including the second channel pad130connected to the base substrate100P may be formed.

Referring toFIG.37, a cell structure CELL is stacked on a peripheral circuit structure PERI.

For example, the processes described above with reference toFIGS.22to26may be performed. After the cell structure CELL is stacked on the peripheral circuit structure PERI, at least a portion of the base substrate100P may be removed to form the cell substrate100. For example, an insulating substrate101that replaces a portion of the base substrate100P may be formed. Accordingly, the cell substrate100connected to the second channel pad138may be provided.

Referring toFIG.38, a first impurity region102and a second impurity region104are formed in the cell substrate100.

Since formation of the first impurity region102and the second impurity region104is similar to processes described above with reference toFIGS.28to30, detailed descriptions thereof will not be provided below.

Thereafter, the stages described above with reference toFIGS.31and4may be performed. Accordingly, the semiconductor memory device described above with reference toFIGS.17and18may be fabricated.

Hereinafter, an electronic system including a semiconductor memory device according to example embodiments will be described with reference toFIGS.1to18andFIGS.39to41.

FIG.39is an example block diagram illustrating an electronic system according to some embodiments.FIG.40is an example perspective view of an electronic system according to some embodiments.FIG.41is a schematic cross-sectional view taken along the line I-I ofFIG.40. For convenience of description, the repeated parts described with reference toFIGS.1to18will be briefly described or omitted.

Referring toFIG.39, an electronic system1000according to some embodiments may include a semiconductor memory device1100and a controller1200electrically connected to the semiconductor memory device1100. The electronic system1000may be a storage device including one or a plurality of semiconductor memory devices1100, or may be an electronic device including a storage device. For example, the electronic system1000may be a solid state drive (SSD) device, a universal serial bus (USB) device, a computing system, a medical apparatus, or a communication apparatus, each of which includes a single or a plurality of semiconductor devices1100.

The semiconductor memory device1100may be a nonvolatile memory device (e.g., a NAND flash memory device). For example, the semiconductor memory device1100may be the semiconductor memory device described above with reference toFIGS.1to18. The semiconductor memory device1100may include a first structure1100F and a second structure1100S on the first structure1100F.

The first structure1100F may be a peripheral circuit structure that includes a decoder circuit1110(e.g., the row decoder33ofFIG.1), a page buffer1120(e.g., the page buffer35ofFIG.1), and a logic circuit1130(e.g., the control logic37ofFIG.1). The first structure1100F may correspond to, for example, the peripheral circuit structure PERI described above with reference toFIGS.1to18.

The second structure1100S may include the common source line CSL, a plurality of bit lines BL, and a plurality of cell strings CSTR, which are described above with reference toFIG.2. The cell strings CSTR may be connected to the decoder circuit1110through the word line WL, at least one string selection line SSL, and at least one ground selection line GSL. In addition, the cell strings CSTR may be connected to the page buffer1120through the bit lines BL. The second structure1100S may correspond to, for example, the cell structure CELL described above with reference toFIGS.1to18.

In some embodiments, the common source line CSL and the cell strings CSTR may be electrically connected to the decoder circuit1110through first connection lines1115that extend from the first structure1100F toward the second structure1100S. The first connection lines1115may correspond to, for example, the gate contacts162described above with reference toFIGS.1to18. That is, the gate contacts162may electrically connect gate electrodes GSL, WL, and SSL to the decoder circuit1110(e.g., the row decoder33ofFIG.1).

In some embodiments, the bit lines BL may be electrically connected to the page buffer1120through second connection lines1125. The second connection lines1125may correspond to, for example, the bit line contacts182described above with reference toFIGS.1to18. That is, the bit line contacts182may electrically connect the bit lines BL to the page buffer1120(e.g., the page buffer35ofFIG.1).

The semiconductor memory device1100may communicate with the controller1200through an input/output pad1101electrically connected to the logic circuit1130(e.g., the control logic37ofFIG.1.). The input/output pad1101may be electrically connected to the logic circuit1130through an input/output connection line1135that extends from the first structure1100F toward the second structure1100S. The connection line1135may correspond to, for example, the contact plug360described above with reference toFIGS.1to18.

The controller1200may include a processor1210, a NAND controller1220, and a host interface1230. In some embodiments, the electronic system1000may include a plurality of semiconductor devices1100, and in this case, the controller1200may control the plurality of semiconductor devices1100.

The processor1210may control overall operations of the electronic system1000including the controller1200. The processor1210may operate based on predetermined firmware, and may control the NAND controller1220to access the semiconductor device1100. The NAND controller1220may include a NAND interface1221that processes communication with the semiconductor device1100. The NAND interface1221may be used to transfer therethrough a control command to control the semiconductor memory device1100, data which is intended to be written on memory cell transistors MCT of the semiconductor memory device1100, and/or data which is intended to be read from the memory cell transistors MCT of the semiconductor device1100. The host interface1230may provide the electronic system1000with communication with an external host. When a control command is received through the host interface1230from an external host, the semiconductor memory device1100may be controlled by the processor1210in response to the control command.

Referring toFIGS.40and41, an electronic system according to some embodiments may include a main board2001, a controller2002mounted on the main board2001, one or more semiconductor packages2003, and a dynamic random access memory (DRAM)2004. The semiconductor package2003and the DRAM2004may be connected to the main controller2002through wiring patterns2005provided in the main board2001.

The main board2001may include a connector2006including a plurality of pins which have connection with an external host. The number and arrangement of the plurality of pins on the connector2006may be changed based on a communication interface between the electronic system2000and the external host. In some embodiments, the electronic system2000may communicate with the external host through one or more interfaces, e.g., USB, peripheral component interconnect express (PIC-Express), serial advanced technology attachment (SATA), and/or M-PHY for universal flash storage (UFS). In some embodiments, the electronic system2000may operate with power supplied through the connector2006from the external host. The electronic system2000may further include a power management integrated circuit (PMIC) that distributes the power supplied from the external host to the main controller2002and the semiconductor package2003.

The main controller2002may write data to the semiconductor package2003, may read data from the semiconductor package2003, or may increase an operating speed of the electronic system2000.

The DRAM2004may be a buffer memory that reduces a difference in speed between the external host and the semiconductor package2003that serves as a data storage space. The DRAM2004included in the electronic system2000may operate as a cache memory, and may provide a space for temporary data storage in a control operation of the semiconductor package2003. When the DRAM2004is included in the electronic system2000, the main controller2002may include not only a NAND controller for control of the semiconductor package2003, but also a DRAM controller for control of the DRAM2004.

The semiconductor package2003may include a first semiconductor package2003aand a second semiconductor package2003bthat are spaced apart from each other. Each of the first and second semiconductor packages2003aand2003bmay include a plurality of semiconductor chips2200. Each of the first and second semiconductor packages2003aand2003bmay include a package substrate2100, semiconductor chips2200on the package substrate2100, adhesive layers2300on bottom surfaces of the semiconductor chips2200, connection structures2400that electrically connect the semiconductor chips2200to the package substrate2100, and a molding layer2500that lies on the package substrate2100and covers the semiconductor chips2200and the connection structures2400.

The package substrate2100may be, for example, a printed circuit board including package upper pads2130. Each of the semiconductor chips2200may include one or more input/output pads2210. The input/output pad2210may correspond to the input/output pad1101ofFIG.39.

In some embodiments, the connection structures2400may be, for example, bonding wires that electrically connect the input/output pads2210to the package upper pads2130. Therefore, on each of the first and second semiconductor packages2003aand2003b,the semiconductor chips2200may be electrically connected to each other in a wire bonding manner, and may be electrically connected to the package upper pads2130of the package substrate2100. In some embodiments, on each of the first and second semiconductor packages2003aand2003b, the semiconductor chips2200may be electrically connected to each other using through-silicon vias (TSV) instead of the connection structures2400or the bonding wires.

In some embodiments, the main controller2002and the semiconductor chips2200may be included in a single package. In some embodiments, the main controller2002and the semiconductor chips2200may be mounted on a separate interposer substrate other than the main board2001, and may be connected to each other through wiring lines formed in the interposer substrate.

In some embodiments, the package substrate2100may be, for example, a printed circuit board. The package substrate2100may include a package substrate body2120, package upper pads2130on a top surface of the package substrate body2120, lower pads2125disposed or exposed on a bottom surface of the package substrate body2120, and internal wiring lines2135that lie in the package substrate body2120and electrically connect the upper pads2130to the lower pads2125. The upper pads2130may be electrically connected to connection structures2400. The lower pads2125may be connected through conductive connectors2800to the wiring patterns2005in the main board2001of the electronic system2000shown inFIG.40.

In the electronic system according to some embodiments, each of the semiconductor chips2200may include the semiconductor memory device described above with reference toFIGS.1to18. For example, each of the semiconductor chips2200may include a peripheral circuit structure PERI and a cell structure CELL stacked on the peripheral circuit structure PERI. In some embodiments, the peripheral circuit structure PERI may include the peripheral circuit board200and the peripheral circuit interconnection structure260which are described above with reference toFIGS.3to8. In addition, in an example, the cell structure CELL may include the cell substrate100, the mold structures MS1and MS2, the channel structures CH, the bit lines BL, the gate contacts162, the first impurity region102, the second impurity region104, the source plate310, the source contact, the conductive contact320, and the erase control contact325, which are described above with reference toFIGS.3to8. The peripheral circuit structure PERI and the cell structure CELL may be bonded to each other through a first bonding metal190and a second bonding metal290.

As used herein, an element or region that is “covering” or “surrounding” or “filling” another element or region may completely or partially cover or surround or fill the other element or region. Further, the term “and/or” includes any and all combinations of one or more of the associated listed items.

While the present inventive concept has been particularly shown and described with reference to example embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the scope of the present invention as defined by the following claims. It is therefore desired that the embodiments described herein be considered in all respects as illustrative and not restrictive, reference being made to the appended claims rather than the foregoing description to indicate the scope of the present invention.