Semiconductor structure with low defect and method for forming the same

A semiconductor structure and a method for forming the same are provided. The method for manufacturing a semiconductor structure includes forming a fin structure over a substrate and forming an insulating layer around the fin structure. The method for manufacturing a semiconductor structure further includes removing a portion of the fin structure to form a trench in the insulating layer and filling the trench with a semiconductor material. The method for manufacturing a semiconductor structure further includes reflowing the semiconductor material to form a nanowire structure and a cavity under the nanowire structure.

BACKGROUND

One of the important drivers for improving performance in semiconductor structures is the higher levels of integration of circuits. This is accomplished by miniaturizing or shrinking device sizes on a given chip. For example, FinFET structures and nanowire FET structures are formed to increase the integration density in the semiconductor structures. However, although existing processes for manufacturing FinFET structures and nanowire FET structures have generally been adequate for their intended purposes, as device scaling-down continues, they have not been entirely satisfactory in all respects.

DETAILED DESCRIPTION

Embodiments of semiconductor structures and methods for forming the same are provided. The method for forming a semiconductor structure may include reflowing a semiconductor material in a trench to form a cavity under the semiconductor material. The semiconductor material located over the cavity may be used as a nanowire structure and may have fewer defects.

FIGS. 1A to 1Pare perspective representations of various stages of forming a semiconductor structure100in accordance with some embodiments. As shown inFIG. 1A, a substrate102is received in accordance with some embodiments. The substrate102may be a semiconductor wafer such as a silicon wafer. Alternatively or additionally, the substrate102may include elementary semiconductor materials, compound semiconductor materials, and/or alloy semiconductor materials. Examples of the elementary semiconductor materials may be, but are not limited to, crystal silicon, polycrystalline silicon, amorphous silicon, germanium, and/or diamond. Examples of the compound semiconductor materials may be, but are not limited to, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide. Examples of the alloy semiconductor materials may be, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP.

In addition, the substrate102may include structures such as doped regions, interlayer dielectric (ILD) layers, conductive features, and/or isolation structures. Furthermore, the substrate102may further include single or multiple material layers to be patterned. For example, the material layers may include a silicon layer, a dielectric layer, and/or a doped poly-silicon layer. In some embodiments, the substrate102is a silicon substrate. In some embodiments, the substrate102is a silicon-on-insulator (SOI) substrate.

An oxide layer104and a nitride layer106are formed over the substrate102, as shown inFIG. 1Ain accordance with some embodiments. In some embodiments, the oxide layer104is made of silicon oxide. The oxide layer104may be formed by using a thermal oxidation process, although other deposition processes may be used in some other embodiments.

The nitride layer106may be used as a hard mask during subsequent photolithography processes. In some embodiments, the nitride layer106is made of silicon nitride. The nitride layer106may be formed by using low-pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD), although other deposition processes may also be used in some other embodiments.

Next, a fin structure108is formed from the nitride layer106, the oxide layer104, and the substrate102, as shown inFIG. 1Bin accordance with some embodiments. In some embodiments, the nitride layer106, the oxide layer104, and the substrate102are sequentially patterned to form the fin structure108. In some embodiments, the nitride layer106, the oxide layer104, and the substrate102are patterned by forming a photoresist layer over the nitride layer108, and etching the nitride layer106, the oxide layer104, and the substrate102through the photoresist layer.

After the fin structure108is formed, an insulating layer110is formed over the substrate102, as shown inFIG. 1Cin accordance with some embodiments. In addition, the insulating layer110is formed around the fin structure108and also covers the fin structure108. In some embodiments, the insulating layer110is made of silicon oxide. The insulating layer110may be formed by using a high-density-plasma (HDP) CVD process, although other deposition processes may be used in other embodiments.

After the insulating layer110is formed, a polishing process is performed to remove the top portion of the insulating layer110, as shown inFIG. 1Din accordance with some embodiments. In some embodiments, the polishing process is a chemical mechanical polishing (CMP) process. The polishing process may be performed until the top surface of the nitride layer106is exposed.

Afterwards, the nitride layer106is removed, as shown inFIG. 1Ein accordance with some embodiments. The nitride layer106may be removed by performing a wet etching process or a dry etching process.

After the nitride layer106is removed, a trench112is formed in the insulating layer110, as shown inFIG. 1Fin accordance with some embodiments. In some embodiments, the trench112is formed by removing the oxide layer104and some portions of the insulating layer110. In some embodiments, a hard mask structure having an opening may be formed over the insulating layer110, and an etching process is performed through the opening to remove the oxide layer104and the portions of the insulating layer110exposed by the opening.

As shown inFIG. 1F, the fin structure108has a first width W1and the trench112has a second width W2. In some embodiments, the second width W2is greater than the first width W1. In some embodiments, the first width W1is in a range from about 5 nm to about 10 nm. In some embodiments, the second width W2is in a range from about 10 nm to about 20 nm. The size of the nanowire structure formed in subsequent processes may be controlled by adjusting the second width W2of the trench112(Details will be described later.)

After the trench112is formed, the top portion of the fin structure108is removed to form a trench114, as shown inFIG. 1Gin accordance with some embodiments. In some embodiments, the trench114is formed by etching the top portion of the fin structure108through the trench112. As shown inFIG. 1G, although the top portion of the fin structure108is removed, the bottom portion of the fin structure108remains.

In some embodiments, the trench114has a depth D1, which is smaller than the thickness of the insulating layer110at this stage. In some embodiments, the depth D1is in a range from about 50 nm to about 300 nm. The depth D1of the trench114may determine the size of the cavity formed in subsequent processes and may be adjusted according to its application (Details will be described later.)

As described previously, the trench114may be formed through the trench112, and therefore the trench114connects to the trench112. That is, the trench112and the trench114may be seen as a trench116having a wider top portion (e.g. the trench112) and a narrower bottom portion (e.g. the trench114.)

After the trench116is formed, a semiconductor material118is formed in the trench116, as shown inFIG. 1Hin accordance with some embodiments. As shown inFIG. 1H, the trench116, including the trench112and the trench114, is completely filled with the semiconductor material118in accordance with some embodiments. In addition, the semiconductor material118is formed on the fin structure108and is in direct contact with the top surface of the fin structure108at this stage. It should be noted that the amount of semiconductor material118may be adjusted as required. For example, the trench116may only be partially filled with the semiconductor material118or may be over-filled with the semiconductor material118.

In some embodiments, the semiconductor material is Ge, Si, SiGe, or the like. In some embodiments, the semiconductor material118is formed by performing an epitaxial growth process.

Next, the semiconductor material118is reflowed by performing an annealing process120, as shown inFIG. 1Iin accordance with some embodiments. The condition of the annealing process120may be adjusted depending on the semiconductor material118which needs to be reflowed in the process. In some embodiments, the annealing process120is a laser annealing process and is performed at a temperature in a range from about 900° C. to about 1000° C. In some embodiments, the annealing process120is a rapid thermal annealing (RTA) process and is performed at a temperature in a range from about 700° C. to about 900° C. in N2or H2for few minutes.

During the annealing process120, the dislocation in the semiconductor material118will move to reach the surface and disappear because of the thermal budget, so that the reflowed semiconductor material119can have fewer defects. In addition, as shown inFIG. 1I, during the annealing process120, a portion of the semiconductor material118migrates from the bottom portion of the trench116to the top portion of the trench116. Accordingly, a cavity122is formed at the bottom portion of the trench116under the reflowed semiconductor material119, as shown inFIG. 1Iin accordance with some embodiments.

In some embodiments, the cavity122has a height H1, which is substantially equal to the depth D1of the trench114. That is, after the annealing process120is performed, the reflowed semiconductor material119is mainly located in the top portion of the trench116(e.g. the trench112), so that the cavity122is formed at the bottom portion of the trench116(e.g. the trench114.) However, it should be noted that the cavity122shown inFIG. 1Iis merely an example, and the size of the cavity122may be adjusted according to its application.

In some embodiments, the height H1of the cavity122is in a range of about 50 nm to about 300 nm. The size of the cavity122(e.g. the height H1of the cavity122) should be large enough so that a portion of the gate structure may be formed in a portion of the cavity122in subsequent processes. On the other hand, if the size of the cavity122is too large, a great amount of reflowed semiconductor material119may flow onto the top surface of the insulating layer110, such that there is not enough of the reflowed semiconductor material119left in the trench116(Details will be described later.)

The size of the cavity122may be controlled by adjusting the condition of the annealing process120. For example, the longer time and/or the higher temperature of the annealing process120, the greater the size of the cavity122. Therefore, the conditions of the annealing process120may be controlled to give sufficient energy to the semiconductor material118for the semiconductor material118to be reflowed to form the cavity122, while ensuring that there is enough of the reflowed semiconductor material119left in the trench116.

As shown inFIG. 1I, a portion of the reflowed semiconductor material119flows onto the top surface of the insulating layer110in accordance with some embodiments. Therefore, a polishing process124is performed to remove the portion of the reflowed semiconductor material119over the insulating layer110to form a nanowire structure126, as shown inFIG. 1Jin accordance with some embodiments.

More specifically, the polishing process124is performed to remove the portion of the reflowed semiconductor material119formed over the insulating layer110. The polishing process124may be performed until the top surface of the insulating layer110is exposed. It should be noted that, although the polishing process124is shown inFIG. 1J, it may be omitted in some other embodiments, and the scope of the disclosure is not intended to be limiting.

After the nanowire structure126is formed, the insulating layer110is recessed to expose the upper portion of the nanowire structure126, as shown inFIG. 1Kin accordance with some embodiments. In some embodiments, the insulating layer110is recessed by performing an etching process. In some embodiments, the insulating layer110is recessed until most, but not all, of the nanowire structure126is exposed.

As shown inFIG. 1K, the insulating layer110is recessed to form an isolation structure128, and a bottom portion of the nanowire structure126is embedded in the isolation structure128. In addition, the cavity122is located in the isolation structure128, and the nanowire structure126and the fin structure108are separated by the cavity122.

Afterwards, a dummy gate structure130is formed across the upper portion of the nanowire structure126and extends over the isolation structure128, as shown inFIG. 1Lin accordance with some embodiments. In some embodiments, the dummy gate structure includes a dummy gate dielectric layer132and a dummy gate electrode layer134formed over the dummy gate dielectric layer132. In some embodiments, the dummy gate dielectric layer132is made of silicon oxide. In some embodiments, the dummy gate electrode layer134is made of polysilicon.

Spacers136are formed on the sidewalls of the dummy gate structure130in accordance with some embodiments. In some embodiments, the spacers136are made of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, or other applicable dielectric materials.

After the dummy gate structure130is formed, source/drain regions138are formed in two ends of the nanowire structure126, although only one is shown inFIG. 1Min accordance with some embodiments. The source/drain regions138may be formed by doping n-type and/or p-type dopants in the nanowire structure126. As shown inFIG. 1M, the source/drain regions138are located over some portions of the cavity122.

After the source/drain regions138are formed, a material layer140is formed to cover the source/drain regions138, and a polishing process is performed on the material layer140to expose the top surface of the dummy gate structure130. In some embodiments, the material layer140is epitaxial growth of Si or SiGe or Ge, which is used as source and drain contact regions. In some embodiments, SiP is used for n-channel transistors, and SiGeB is used for p-channel transistors. In some embodiments, the material layer140is planarized by performing a chemical mechanical polishing (CMP) process until the top surface of the dummy gate structure130is exposed.

After the polishing process is performed, the dummy gate structure130is removed to form a gate trench142between the spacers136, as shown inFIG. 1Nin accordance with some embodiments. As shown inFIG. 1N, the upper portion of the nanowire structure126is exposed in the gate trench142after the dummy gate structure130is removed.

After the dummy gate structure130is removed, a portion of the isolation structure128is removed to expose a portion of the cavity122, as shown inFIG. 1Oin accordance with some embodiments. In some embodiments, the portion of the isolation structure128is removed by etching the isolation structure128through the gate trench142, such that the gate trench142has an extending portion144extending into the isolation structure128.

As shown inFIG. 1O, the extending portion144of the gate trench142has a height H2. In some embodiments, the height H2of the extending portion144is smaller than the height H1of the cavity122, such that only a portion of the cavity122is exposed in the extending portion144of the gate trench142. In some embodiments, the height H2of the extending portion144is substantially equal to, or larger than, than the height H1of the cavity122, such that the cavity122is completely exposed in the extending portion144of the gate trench142.

Afterwards, a gate structure146is formed in the gate trench142and the extending portion144, as shown inFIG. 1Pin accordance with some embodiments. In some embodiments, a portion of the gate structure146is formed in the cavity122located below the nanowire structure126, such that a portion of the nanowire structure126is surrounded by the gate structure146. In addition, a portion of the gate structure146is formed in the extending portion144of the gate trench142, such that the portion of the gate structure146extends into the isolation structure128.

In some embodiments, the gate structure146includes a gate dielectric layer148, a work function metal layer150, and a metal gate electrode layer152. In some embodiments, the gate dielectric layer128is made of metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, oxynitrides of metals, metal aluminates, or other high-k dielectric materials. Examples of the high-k dielectric material may include, but are not limited to, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO2), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO2), hafnium titanium oxide (HfTiO2), hafnium zirconium oxide (HfZrO2), zirconium silicate, zirconium aluminate, zirconium oxide, titanium oxide, aluminum oxide, or hafnium dioxide-alumina (HfO2—Al2O3) alloy.

The work function metal layer150is formed over the gate dielectric layer148in accordance with some embodiments. The work function metal layer150may be customized to have the proper work function. For example, if P-type work function metal (P-metal) for a PMOS device is desired, Pt, Ta, Re, N+-polysilicon, TiN, WN, or W may be used. On the other hand, if an N-type work function metal (N-metal) for NMOS devices is desired, Al, P+ polysilicon, Ti, V, Cr, Mn, TiAl, TiAlN, TaN, TaSiN or TaCN, may be used.

The metal gate electrode layer152is formed over the work function metal layer150in accordance with some embodiments. In some embodiments, the metal gate electrode layer152is made of a conductive material, such as aluminum, copper, tungsten, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN, or other applicable materials. The gate dielectric layer148, the work function metal layer150, and the metal gate electrode layer152may be formed by any applicable process and have any applicable thicknesses.

It should be noted that additional layers may be formed above and/or below the gate dielectric layer148, the work function metal layer150, and the metal gate electrode layer152, such as liner layers, interface layers, seed layers, adhesion layers, barrier layers, or the like. In addition, the gate dielectric layer148, the work function metal layer150, and the metal gate electrode layer152may include one or more materials and/or one or more layers.

FIGS. 2A to 2Hare cross-sectional representations of the semiconductor structures100ato100gshown along line A-A′ as shown inFIG. 1Pin accordance with various embodiments. More specifically,FIGS. 2A to 2Dshow possible cross-sectional representations of semiconductor structures100ato100d, in which the height H2of the extending portion144is smaller than the height H1of the cavity122shown inFIG. 1O.

As shown inFIG. 2A, since the height H2of the extending portion144is smaller than the height H1of the cavity122, the top surface of the isolation structure128under gate structures146ais higher than the top surface of the fin structure108. In addition, the nanowire structure126is surrounded by the gate structure146a, including the gate dielectric layer148, the work function metal layer150, and the gate electrode layer152.

Similar to that of the semiconductor structure100a, in the semiconductor structure100b, the top surface of the isolation structure128under gate structures146bis higher than the top surface of the fin structure108. However, the gate electrode layer152is not formed under the nanowire structure126. That is, when the gate structure146bis formed, only the gate dielectric layer148and the work function metal layer150are formed in the cavity122under the nanowire structure126but the gate electrode layer152is not formed in the cavity122.

The semiconductor structure100cmay be similar to the semiconductor structure100ashown inFIG. 2A, except a portion of the cavity122remains under a gate structure146c. That is, a portion of the gate structure146c, including the gate dielectric layer148, the work function metal layer150, and the gate electrode layer152, are formed in the cavity122under the nanowire structure126. However, the cavity122is not completely filled with the gate structure146c. Therefore, a portion of the cavity122is located under the gate structure146cin the semiconductor structure100c.

The semiconductor structure100dmay be similar to the semiconductor structure100bshown inFIG. 2B, except a portion of the cavity122is not filled. As shown inFIG. 2D, a portion of the gate structure146d, including the gate dielectric layer148and the work function metal layer150but not including the gate electrode layer152, is formed in the cavity122under the nanowire structure126. However, the cavity122is not completely filled with the gate structure146d. Therefore, a portion of the cavity122is located under the gate structure146din the semiconductor structure100d.

FIGS. 2E and 2Fshow possible cross-sectional representations of semiconductor structures100eand100f, in which the height H2of the extending portion144is greater than the height H1of the cavity122shown inFIG. 1O.

The semiconductor structure100emay be similar to the semiconductor structure100ashown inFIG. 2A, except that the top surface of the isolation structure128under gate structures146eis lower than the top surface of the fin structure108. That is, a portion of the fin structure108extends into the gate structure146e(e.g. a portion of the gate electrode layer152) in accordance with some embodiments.

The semiconductor structure100fmay be similar to the semiconductor structure100bshown inFIG. 2B, except that the top surface of the isolation structure128under gate structures146eis lower than the top surface of the fin structure108. That is, a portion of the fin structure108extends into the gate structure146f(e.g. a portion of the work function metal layer148) in accordance with some embodiments.

FIGS. 2G and 2Hshow possible cross-sectional representations of semiconductor structures100gand100h, in which the height H2of the extending portion144is substantially equal to the height H1of the cavity122shown inFIG. 1O.

The semiconductor structures100gand100hmay be similar to the semiconductor structures100aand100bshown inFIGS. 2A and 2B, except that the top surface of the isolation structure128under gate structures146eand146gare substantially level with the top surface of the fin structure108in accordance with some embodiments.

It should be noted that cross-sectional representations shown inFIGS. 2A to 2Hare merely examples for better understanding the concept of the disclosure, and the scope of the disclosure is not intended to be limiting.

FIGS. 3A to 3Dare perspective representations of various stages of forming a semiconductor structure100′ in accordance with some embodiments. The semiconductor structure100′ is similar to the semiconductor structure100described previously, except its nanowire structure126′ has a narrow bottom portion127′ in accordance with some embodiments. Some processes and materials used to form the semiconductor structure100′ may be similar to, or the same as, those used to form the semiconductor structure100shown inFIGS. 1A to 1Pand are not repeated herein.

More specifically, the processes shown inFIGS. 1A to 1Hmay be performed to form a semiconductor material (e.g. the semiconductor material118as shown inFIG. 1H) in a trench (e.g. the trench116as shown inFIG. 1G). After the trench, including a wide top portion (e.g. the trench112as shown inFIG. 1G) and a narrow bottom portion (e.g. the trench114as shown inFIG. 1G), is fully filled with the semiconductor material, an annealing process120′ is performed to reflow the semiconductor material.

The annealing process120′ may be similar to, or the same as, the annealing process120and is not repeated herein. As described previously, after the annealing process120′ is performed, the reflowed semiconductor material119will have fewer defects therein, and a cavity122′ is formed under the reflowed semiconductor material119, as shown inFIG. 3Ain accordance with some embodiments.

In addition, after the annealing process120′, the reflowed semiconductor material119′ is not only in the top portion of the trench but also in a portion of the bottom of the trench, such that the reflowed semiconductor material119′ has a narrower bottom portion127′ extending to the bottom portion of the trench. However, although the bottom portion127′ extends to a portion of the bottom portion of the trench, the reflowed semiconductor material119′ and the fin structure108are still separated by the cavity122′.

After the cavity122′ is formed, the processes shown inFIGS. 1J to 1Pmay be performed. For example, a polishing process may be performed to remove an additional portion of the reflowed semiconductor material119′ to form a nanowire structure126′, as shown inFIG. 3Bin accordance with some embodiments.

After the nanowire structure126′ is formed, the insulating layer110is recessed to form the isolation structure128, and the dummy gate structure130is formed across the nanowire structure126′, as shown inFIG. 3Cin accordance with some embodiments. The dummy gate structure130may also include the dummy gate dielectric layer132and the dummy gate electrode layer134, and the spacers136are formed on the sidewalls of the dummy gate structure130.

After the dummy gate structure130is formed, source/drain regions138′ are formed in two ends of the nanowire structure126′, although only one is shown inFIG. 3Din accordance with some embodiments. As shown inFIG. 3D, the source/drain regions138′ are located over some portions of the cavity122′ and have a narrow bottom portion over the cavity122′.

After the source/drain regions138′ are formed, the material layer140is formed to cover the source/drain regions138′, and a polishing process is performed on the material layer140to expose the top surface of the dummy gate structure130. After the polishing process is performed, the dummy gate structure130is removed to form a gate trench between the spacers136, and a portion of the isolation structure128is removed to form an extending portion of the gate trench, similar to those shown inFIG. 1O. In addition, a portion of the cavity122′ is exposed by the extending portion of the gate trench.

Afterwards, a gate structure146′ is formed in the gate trench and the extending portion, as shown inFIG. 3Din accordance with some embodiments. Similar to those shown in1P, a portion of the gate structure146′ is formed in the cavity122′ located below the nanowire structure126′, such that a portion of the nanowire structure126′ is surrounded by the gate structure146′. In addition, a portion of the gate structure146′ is formed in the extending portion of the trench formed by removing the dummy gate structure130and a portion of the isolation structure128, such that the portion of the gate structure146′ extends into the isolation structure128.

In some embodiments, the gate structure146′ includes the gate dielectric layer148, the work function metal layer150, and the metal gate electrode layer152, although additional layers may be formed above and/or below them.

FIG. 4is a cross-sectional representation of the semiconductor structures100′ shown along line B-B′ as shown inFIG. 3Din accordance with various embodiments. The cross-sectional representation shown inFIG. 4is similar to that shown inFIG. 2A, except that the shape of the nanowire structure126′ is different from that of the nanowire structure126.

As shown inFIG. 4, the nanowire structure126′ has an extending portion127′, making the bottom portion of the nanowire structure126′ narrower than the top portion of the nanowire structure126′. In addition, the gate structure146′, including the gate dielectric layer148, the work function metal layer150, and the gate electrode layer152are conformally formed around the nanowire structure126′, as shown inFIG. 4in accordance with some embodiments.

It should be noted that, although the cross-sectional representation shown inFIG. 4is similar to that shown inFIG. 2A, it is merely an example for better understanding the concept of the disclosure. In some other embodiments, the semiconductor structure100′ may have a cross-sectional representation that is different from the one shown inFIG. 4, and it may be similar to the ones shown inFIGS. 2B to 2H.

FIGS. 5A to 5Eare perspective representations of various stages of forming a semiconductor structure100″ in accordance with some embodiments. The semiconductor structure100″ is similar to the semiconductor structure100described previously, but the shapes of the fin structure, the cavity, and the nanowire structure are different from those shown inFIGS. 1A to 1Pin accordance with some embodiments. Some processes and materials used to form the semiconductor structure100″ may be similar to, or the same as, those used to form the semiconductor structure100and are not repeated herein.

More specifically, a fin structure108″ having curved sidewalls is formed over the substrate102, as shown inFIG. 5Ain accordance with some embodiments. After the fin structure108″ is formed, the insulating layer110is formed around the fin structure108″, and a trench116″ is formed in the insulating layer110by removing the top portion of the fin structure108″, similar to those shown inFIGS. 1C to 1Gand described previously.

Since the fin structure108″ has inwardly curving sidewalls, the trench116″ formed by removing the top portion of the fin structure108″ also has sidewalls that curve inwardly, as shown inFIG. 5Ain accordance with some embodiments. That is, the trench116″ has curved sidewalls, and the top portion of the trench116″ is greater than the bottom portion of the trench116″ in accordance with some embodiments.

After the trench116″ is formed, the processes shown inFIGS. 1H to 1Pmay be performed to form the semiconductor structure100″. More specifically, the trench116″ is filled with a semiconductor material118″, as shown inFIG. 5Bin accordance with some embodiments.

Next, an annealing process120″ is performed to reflow the semiconductor material118″, and a cavity122″ is formed under the reflowed semiconductor material119″, as shown inFIG. 5Cin accordance with some embodiments. After the cavity122″ is formed, a polishing process is performed to remove the additional portion of the reflowed semiconductor material119″, and the insulating layer110is recessed to form the isolation structure128. Accordingly, a nanowire structure126″ is formed to have a wide top surface, a narrow bottom surface, and sidewalls that curve inwardly, as shown inFIG. 5Din accordance with some embodiments. In addition, a portion of the nanowire structure126″ is embedded in the isolation structure128in accordance with some embodiments.

After the nanowire structure126″ is formed, a dummy gate structure may be formed and replaced by a gate structure146″ afterwards, as shown inFIG. 5Ein accordance with some embodiments. In addition, source/drain structures138″ are formed in the nanowire structure126″ and are located over the cavity122″.

FIG. 6is a cross-sectional representation of the semiconductor structures100″ shown along line C-C′ as shown inFIG. 5Ein accordance with various embodiments. The cross-sectional representation shown inFIG. 6is similar to that shown inFIG. 2A, except that the shape of the nanowire structure126′ is different from that of the nanowire structure126.

As shown inFIG. 6, the nanowire structure126″ has sidewalls that curve inwardly. In addition, the gate structure146′, including the gate dielectric layer148, the work function metal layer150, and the gate electrode layer152are conformally formed around the nanowire structure126″, as shown inFIG. 6in accordance with some embodiments. It should be noted that, although the cross-sectional representation shown inFIG. 6is similar to that shown inFIG. 2A, it is merely an example for better understanding the concept of the disclosure.

FIG. 7is a perspective representation of a semiconductor structure100′″ in accordance with some embodiments. The semiconductor structure100′″ is similar to the semiconductor structure100described previously, except an extending portion of a gate structure146′″ extends under the spacers136.

More specifically, the processes shown inFIGS. 1A to 1Nmay be performed. After the dummy gate structure is removed to form a gate trench, an extending portion of the gate trench is formed by removing a portion of the isolation structure128. In addition, a portion of the extending portion extends under a portion of the spacer136in accordance with some embodiments. Afterward, the gate structure146′″ is formed in the gate trench and the extending portion of the gate trench, such that an extending portion of the gate structure146′″ extends under a portion of the spacer136, as shown inFIG. 7in accordance with some embodiments.

FIG. 8Ais a perspective representation of a semiconductor structure200in accordance with some embodiments.FIG. 8Bis a cross-sectional representation of the semiconductor structure200shown along line D-D′ as shown inFIG. 8Ain accordance with some embodiments. The processes and materials used to form the semiconductor structure200are similar to those used to form the semiconductor structure100shown inFIGS. 1A to 1P, except that the isolation structure228is not etched after the dummy gate structure is removed. The processes and materials that are similar to, or the same as, those described previously are not repeated herein.

More specifically, the processes shown inFIGS. 1A to 1Nmay be performed. For example, a fin structure208may be formed over a substrate202, and an isolation structure228may be formed around the fin structure208. In addition, a nanowire structure226may be formed by filling a semiconductor material in a trench over the fin structure208and reflowing the semiconductor material. In addition, after the semiconductor material is reflowed, a cavity222is formed under the nanowire structure226. Afterwards, a dummy gate structure is formed across the nanowire structure226, and spacers236, source/drain structures236, a material layer240are formed.

Next, the dummy gate structure is removed, and a gate structure246is formed in the trench which is formed by removing the dummy gate structure, as shown inFIG. 7Ain accordance with some embodiments. Since the isolation structure228is not etched after the dummy gate structure is removed, the cavity222will not be exposed. Therefore, when the gate structure246is formed, it will only be formed over three sides of the nanowire structure226but will not be formed in the cavity222under the nanowire structure226.

Furthermore, since the isolation structure228is not etched after the dummy gate structure is removed, the gate structure246does not extend into the isolation structure228. As shown inFIG. 8B, the nanowire structure226, including the source/drain structures238and the portion under the gate structure246, is separated with the fin structure208by the cavity222in accordance with some embodiments. That is, a portion of the cavity222is located under the gate structure246, and portions of the cavity222are located under the source/drain structures238in accordance with some embodiments.

In the semiconductor structure200shown inFIG. 8B, although the gate structure246is not formed all around the nanowire structure226, the nanowire structure226formed by reflowing the semiconductor material can have a fewer defects therein. In addition, the nanowire structure226may have a better isolation with the substrate202. Therefore, the performance of the semiconductor structure200can be improved.

FIGS. 9A to 9Dare cross-sectional representations of various stages of forming a semiconductor structure300in accordance with some embodiments. Some processes shown inFIGS. 9A to 9Dmay be similar to, or the same as, those shown inFIGS. 1A to 1Jand may not repeated herein.

A first fin structure308a, a second fin structure308b, and a third fin structure308care formed over a substrate302, and an insulating layer310are formed around the first fin structure308a, the second fin structure308b, and the third fin structure308c, as shown inFIG. 9Ain accordance with some embodiments.

In addition, a trench316is formed in the insulating layer310and includes a top portion312, a first bottom portion314a, a second bottom portion314b, and a third bottom portion314cin accordance with some embodiments. The first bottom portion314ais located over the first fin structure308a, and the second bottom portion314bis located over the second fin structure308b. Furthermore, the third bottom portion314cis located over the third fin structure308c. The trench316may be formed by the processes similar to those shown inFIGS. 1A to 1G, except three, instead of one, fin structures are formed.

After the trench316is formed, a semiconductor material318is formed in the trench316, as shown inFIG. 9Bin accordance with some embodiments. The semiconductor material318may be similar to, or the same as, the semiconductor material118described previously. In some embodiments, the semiconductor material318is Ge. In some embodiments, the semiconductor material318is formed by performing an epitaxial growing process. In some embodiments, the top portion312, the first bottom portion314a, the second bottom portion314b, and the third bottom portion314care all completely filled with the semiconductor material318.

After the semiconductor material318is formed, an annealing process320is performed to reflow the semiconductor material318, as shown inFIG. 9Cin accordance with some embodiments. The annealing process320may be similar to, or the same as, the annealing process120described previously.

By performing the annealing process320, the semiconductor material318is reflowed to form a first cavity322a, a second cavity322b, and a third cavity322cunder the reflowed semiconductor material319, as shown inFIG. 9Cin accordance with some embodiments. Next, a polishing process is performed to remove the portion of the reflowed semiconductor material319formed over the insulating layer310to form a nanowire structure326, as shown inFIG. 9Din accordance with some embodiments.

As shown inFIG. 9D, the nanowire structure326is separated from the first fin structure308a, the second fin structure308b, and the third fin structure308cby the first cavity322a, the second cavity322b, and the third cavity322crespectively. It should be noted that, although three fin structures and three cavities are shown inFIGS. 9A to 9D, they are merely an example and the numbers of the fin structures and cavities under the nanowire structure326is not intended to be limiting.

As described previously, since the nanowire structure326is formed by reflowing the semiconductor material318, the defects in the nanowire structure326may be reduced by performing the annealing process320. In addition, the isolation of the nanowire structure326may also be improved. Furthermore, the nanowire structure326may be used in various applications, and the usage of the nanowire structure326is not intended to be limiting by the examples described above.

In accordance with some embodiments of the disclosure described previously, semiconductor structures (e.g. the semiconductor structure100,100′,100″,100′″,200, and300) including nanowire structures (e.g. the nanowire structures126,126′,126″,226, and326) are formed. The nanowire structure may be formed by reflowing a semiconductor material (e.g. the semiconductor material118,118″, and318) in a trench. In addition, a cavity (e.g. the cavities122,122′,122″,222, and322ato322c) may be formed under the nanowire structure due to the migration of the semiconductor material during the reflowing process (e.g. the annealing processes120,120′,120″, and320).

In addition, the size of the cavity and the size of the nanowire structure may be controlled by adjusting the size of the trench (e.g. the trench116,116″, and316) and/or adjusting the condition of the annealing process (e.g. the annealing processes120,120′,120″, and320.) The resulting semiconductor structure may be performed according to its application.

Moreover, when the semiconductor material is reflowed, the amounts of the defects, which are formed due to lattice mismatch between the semiconductor material and the substrate, can be reduced. Therefore, the resulting nanowire structure may have fewer defects inside its structure after the reflowing process. Accordingly, the performance of the semiconductor structure may be improved.

Furthermore, since the cavity is formed due to the migration of the semiconductor material during the reflowing process, additional material layers and etching processes are not required. More specifically, although a nanowire structure may be formed by forming a semiconductor material over a sacrificial layer and removing the sacrificial layer to form the nanowire structure, the processes for forming the sacrificial layer and etching the sacrificial layer are required. In addition, the fully removal of the sacrificial layer may be challenging. Therefore, the processes used in the embodiments described above, which includes forming the nanowire structure by reflowing the semiconductor material, are less complicated, and the resulting nanowire structure may have better isolation.

Embodiments of a semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a nanowire structure. The nanowire structure is formed by reflowing a semiconductor material formed in the trench, so that a cavity can be formed at the bottom of the trench under the reflowed semiconductor material. After the reflowing process, the amounts of defects in the semiconductor material can be reduced, and therefore the defects in the resulting nanowire structure can be reduced. Accordingly, the performance of the semiconductor structure may be improved.

In some embodiments, a method for manufacturing a semiconductor structure is provided. The method for manufacturing a semiconductor structure includes forming a fin structure over a substrate and forming an insulating layer around the fin structure. The method for manufacturing a semiconductor structure further includes removing a portion of the fin structure to form a trench in the insulating layer and filling the trench with a semiconductor material. The method for manufacturing a semiconductor structure further includes reflowing the semiconductor material to form a nanowire structure and a cavity under the nanowire structure.

In some embodiments, a method for manufacturing a semiconductor structure is provided. The method for manufacturing a semiconductor structure includes forming a first fin structure over a substrate and forming an insulating layer around the first fin structure. The method for manufacturing a semiconductor structure further includes removing a portion of the first fin structure to form a first trench in the insulating layer and filling the first trench with a semiconductor material. The method for manufacturing a semiconductor structure further includes reflowing the semiconductor material to form a first cavity at a bottom portion of the first trench by an annealing process.

In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a fin structure formed over a substrate and an isolation structure formed around the fin structure. The semiconductor structure further includes a nanowire structure formed over the fin structure and a gate structure formed around the nanowire structure. In addition, a portion of the nanowire structure is embedded in the isolation structure.