Variable length coding apparatus and variable length coding method

A variable length coding apparatus and a variable length coding method including a prepacking unit which processes two data items, each of which is formed with a code value and a code length and is received from a variable length code generator at each clock cycle, into one data item and outputs the processed data item to perform bitstream packing. With this structure, a variable length coding apparatus operating at a high speed without idling can be implemented.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under U.S.C § 119 from Korean Patent Application No. 2003-98231, filed on Dec. 27, 2003, the content of which is incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present general inventive concept relates to moving picture encoding, and more particularly, to a variable length coding apparatus and a variable length coding method.

2. Description of the Related Art

In order to encode moving pictures with high picture quality, a moving picture encoding apparatus operating at a high speed is needed. In order to operate the moving picture encoding apparatus, a discrete cosine transform (DCT) apparatus, a quantization/dequantization apparatus, and a variable length coding (VLC) coding apparatus are indispensable. In order to operate the DCT apparatus, the apparatus is usually designed to be able to process two data items at each clock cycle.

FIG. 1is a schematic block diagram of a conventional moving picture encoding apparatus.

Referring toFIG. 1, the moving picture encoding apparatus comprises a DCT/quantization unit110, a run length coding (RLC) unit120, a variable length code generation unit130, a VLC table140, a buffer150, and a bitstream packing unit160. The encoding apparatus performs DCT/quantization, RLC, and VLC in units of 8×8 blocks.

The DCT/quantization unit110performs DCT and quantization in units of 8×8 data blocks, and the RLC unit120performs the RLC of data output from the DCT/quantization unit110.

A variable length coding (VLC) apparatus100for performing the VLC comprises the variable length code generation unit130, the VLC table140, the buffer150, and the bitstream packing unit160.

The variable length code generation unit130refers to the VLC table140while taking output data of the RLC unit120as input symbols, and then outputs two data items, each formed with a code value and a code length corresponding to each input symbol, to the buffer150.

The buffer150stores the data items output from the variable length code generation unit130and then transfers the data items to the bitstream packing unit160.

The bitstream packing unit160generates a final bitstream and in doing so, reads the code value and code length information of each symbol from the buffer150and generates a continuous bitstream. Information for producing a bitstream includes a motion vector, a code mode, and a variety of header information, which are not shown inFIG. 1.

FIG. 2is a flowchart of the steps performed by a variable length coding process of the conventional moving picture encoding apparatus ofFIG. 1.

Referring toFIGS. 1 and 2, first, the DCT/quantization unit110receives 2N-bit data30formed with N-bit data010 and N-bit data120 at each clock cycle, performs the DCT and quantization for the data in units of 8×8 blocks, and then outputs two data items of the processed resulting data to the RLC unit120at each clock cycle in operation210. Accordingly, the DCT/quantization unit110processes 64 data items for 32 clock cycles when a data item is an 8×8 block.

Next, the RLC unit120receives two data items of the quantized data at each clock cycle and performs run length encoding in operation220, and outputs two data items, each formed with the length of continuous 0's and a level value. The output of the RLC unit120varies according to images and if there are no continuous 0's, 64 data items are output for 32 clock cycles when a data item is an 8×8 block. However, in an ordinary image, the output of the DCT/quantization unit110has many continuous 0's and therefore the RLC unit120outputs much less data items than 64 for 32 clock cycles when a data item is an 8×8 block.

The variable length code generation unit130receives and outputs two data items at each clock cycle in operation230. That is, the variable length code generation unit130refers to the VLC table140while taking the output data of the RLC unit120as input symbols, and then outputs the two data items, each formed with a code value and a code length corresponding to each input symbol. That is, the two data items are output at each clock cycle.

The two data items output from the variable length code generation unit130at each clock cycle are stored in the buffer150in operation240.

Then, the bitstream packing unit160receives one of the data items stored in the buffer150at each clock cycle and outputs a continuous bitstream in operation250. That is, since the bitstream packing unit160can process a maximum of one input data item at each clock cycle, and the data output rate of the variable length code generation unit130can be twice as high as the data input rate of the bitstream packing unit160at a maximum, the buffer150is placed between the variable length code generation unit130and the bitstream packing unit160as shown inFIG. 1.

It is a problem that the output rate of the variable length code generation unit130is twice as high as the input rate of the bitstream packing unit160in the worst case. As the quality of pictures being encoded is higher, the output rate of the variable code generation unit130approaches twice the input rate of the bitstream packing unit160. In such cases, processing two data items at each clock cycle before the bitstream packing unit160for high-speed processing is of no use. That is, when a data item is an 8×8 blocks, though processing data items before the front end of the bitstream packing unit160is finished in 32 clock cycles, 64 clock cycles are needed in the worst case in the bitstream packing unit160and a situation where data items are idling before the front end of the bitstream packing unit160for 32 clock cycles takes place.

SUMMARY OF THE INVENTION

The present general inventive concept provides a variable length coding apparatus and a variable length coding method by which idling of elements is minimized and a high speed operation is enabled.

The present general inventive concept makes two VLC symbols into one symbol in advance and then performs bitstream packing, and by doing so, in addition to the quantization apparatus, the variable length coding apparatus is also made to be able to process two data items at each clock cycle.

The foregoing and/or other aspects and advantages of the present general inventive concept may be achieved by providing a variable length coding apparatus comprising a prepacking unit which processes 2N(N=1, 2, . . . ) data items, each of which is formed with a code value and a code length and is received from a variable length code generation unit at each clock cycle, into one data item, and outputs the processed data item to perform bitstream packing.

The foregoing and/or other aspects and advantages of the present general inventive concept may also be achieved by providing a variable length coding apparatus comprising a variable length code generation unit to refer to a variable length code table corresponding to two input symbols received at each clock cycle to output two data items, a prepacking unit which receives the two data items output from the variable length code generation unit at each clock cycle, and processes the two data items into one data item, and a bitstream packing unit to receive the one data item output from the prepacking unit at each clock cycle and to perform bitstream packing of the data item.

Each of the two data items, a first data item and a second data item, output from the variable length code generation unit may be formed with a code value and a code length, and the prepacking unit may comprise an addition unit to add the code length of the first data item and the code length of the second data item, a shift unit to shift the code value of the first data item by the code length of the second data item, and an OR operation unit to perform an OR operation of the shifted code value of the first data item and the code value of the second data item, and the prepacking unit can output one data item formed with the code length output from the addition unit and the code value output from the OR operation unit at each clock cycle.

The foregoing and/or other aspects and advantages of the present general inventive concept may also be achieved by providing a variable length coding apparatus comprising a variable length code generation unit to refer to a variable length code table corresponding to 2N(N=1, 2, . . . ) input symbols received at each clock cycle to output 2Ndata items, a prepacking unit which receives the 2Ndata items output from the variable length code generation unit at each clock cycle, and processes the 2Ndata items into one data item, and a bitstream packing unit to receive the one data item output from the prepacking unit at each clock cycle and to perform bitstream packing of the data item.

The prepacking unit may comprise N stages, and each of M-th stage (M=1, . . . , N) may comprise 2N-Msubunits, and with the 2Ndata items output from the variable length coding unit, each of the subunits of M-th stage (M=1, . . . , N−1) can prepack two data items into one data item and transfer the data item to the subunits of (M+1)-th stage, and the subunit of N-th stage can prepack two data items into one data item and output the one data item.

Each of the subunits can receive two data items, a first data item and a second data item, each of which is formed with a code value and a code length, and may comprise an addition unit to add the code length of the first data item and the code length of the second data item, a shift unit to shift the code value of the first data item by the code length of the second data item, and an OR operation unit to perform an OR operation of the shifted code value of the first data item and the code value of the second data item, and each of the subunits can output one data item formed with the code length output from the addition unit and the code value output from the OR operation unit at each clock cycle.

The foregoing and/or other aspects and advantages of the present may also be achieved by providing a variable length coding method comprising processing 2N(N=1,2, . . . ) data items, each of which is formed with a code value and a code length and is received from a variable length code generator at each clock cycle, into one data item, and outputting the processed data item to perform bitstream packing.

The forgoing and/or other aspects and advantages of the present general inventive concept may also be achieved by providing a variable length coding method comprising forming two data items by referring to a variable length code table corresponding to two input symbols received at each clock cycle, processing the two data items formed at each clock cycle into one data item, and performing bitstream packing of the data item.

The foregoing and/or other aspect of the present general inventive concept may also be achieved by providing a variable length coding method comprising forming 2Ndata items by referring to a variable length code table corresponding to 2N(N=1,2, . . . ) input symbols received at each clock cycle, processing the 2Ndata items formed at each clock cycle into one data item, and receiving performing bitstream packing of the data item.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring toFIG. 3, a moving picture encoding apparatus may comprise a DCT/quantization unit310, an RLC unit320, a variable length code generation unit330, a VLC table340, a prepacking unit350, and a bitstream packing unit360. The moving picture encoding apparatus can perform DCT/quantization, RLC, and VLC in units of 8×8 blocks.

The DCT/quantization unit310can perform the DCT and quantization in units of 8×8 data blocks, and the RLC unit320performs the RLC of data output from the DCT/quantization unit310. A variable length coding (VLC) apparatus300may comprise the variable length code generation unit330, the VLC table340, the prepacking unit350, and the bitstream packing unit360.

The variable length code generation unit330refers to the VLC table340while taking the output data of the RLC unit320as input symbols, and then outputs data items, each having a code value and a code length, corresponding to each input symbol, to the prepacking unit350.

The prepacking unit350processes the data items output from the variable length code generation unit330, and transfers the processed data to the bitstream packing unit360. The prepacking unit350can receive two data items from the variable length code generation unit330at each clock cycle, process the two data items into one data item, and output one data item to the bitstream packing unit360at each clock cycle. By placing the prepacking unit350, which can process two data items at each clock cycle, between the variable length code generation unit330and the bitstream packing unit360instead of a buffer, which simply stores data, the variable length coding apparatus300and the moving picture encoding apparatus can process two data items at each clock cycle. The prepacking unit350will be explained in detail below.

The bitstream packing unit360generates a final bitstream and in doing so, reads information about the code value and the code length information of each data item output from the prepacking unit350and generates a continuous bitstream. Information corresponding to generation of the bitstream may include a motion vector, a coding mode, and a variety of header information, which are not shown inFIG. 3.

FIG. 4is a block diagram illustrating a detailed structure of the prepacking unit350ofFIG. 3.

Referring toFIG. 4, the prepacking unit350may comprise an addition unit351, a shift unit352, and an OR operation unit353.

The prepacking unit350can receive the two data items from the variable length code generation unit330at each clock cycle and each of the two data items comprises the code value and the code length. For example, as shown inFIG. 4, assuming that the two data items are a first data item and a second data item, the first data item comprises a code value0and a code length0, and the second data item comprises a code value1and a code length1.

The addition unit351adds the code lengths0and1of the two data items. That is, the addition unit351adds the code length0of the first data item and the code length1of the second data item. The shift unit352shifts the code value0of the first data item by the code length1of the second data item. A barrel shifter can be used as the shift unit352.

The OR operation unit353performs an OR operation of the output value of the shift unit352and the code value1of the second data item.

Thus, with the resulting value of the OR operation unit353as a code value2and the resulting value of the addition unit351as a code length2, the prepacking unit can output a data item of the code value2and the code length2.

FIG. 5is a flowchart illustrating operations performed by a moving picture encoding apparatus ofFIG. 3.

Referring toFIGS. 3 and 5, first, the DCT/quantization unit310receives 2N-bit data30formed with N-bit data010 and N-bit data120 at each clock cycle, performs DCT and quantization of the data, and then outputs two data items of the processed resulting data to the RLC unit320at each clock cycle in operation510. Accordingly, the DCT/quantization unit processes 64 data items for 32 clock cycles when a data item is an 8×8 block.

Next, the RLC unit320receives the two data items of the quantized data at each clock cycle and performs run length encoding (RLC) in operation520, and outputs two data items, each formed with a length of continuous 0's and a level value. The output of the RLC unit320can vary according to images, and if there is no continuous 0's, 64 data items are output over 32 clock cycles when a data item is an 8×8 block. However, in an ordinary image, the output of the DCT/quantization unit310can have many continuous 0's and therefore the RLC unit320can output much less data items than 64 over 32 clock cycles when a data item is an 8×8 block.

The variable length code generation unit330receives the two data items output from the RLC unit320, and outputs two data items at each clock cycle in operation530. That is, the variable length code generation unit330refers to the VLC table340while taking the output data items of the RLC unit320as input symbols, and then outputs the two data items, each formed with the code value and the code length corresponding to each input symbol. That is, the two (code value, code length) data items are output at each clock cycle.

The two data items output from the variable length code generation unit33are transferred to the prepacking unit and processed into one data item (prepacked data item) in operation540.

Next, the bitstream packing unit360receives the one data item (prepacked data item) output from the prepacking unit350, at each clock cycle, and outputs a continuous bitstream in operation550.

Referring toFIGS. 2 and 6, the detailed process of the processing operation ofFIG. 3will now be explained.

With respect to the first data item and the second data item, the addition unit351adds the code lengths0and1of the first data item and the second data item in operation541.

Then, the shift unit352shifts the code value0of the first data item by the code length1of the second data item in operation542.

Next, the OR operation unit353performs an OR operation of the shifted code value of the first data item and the code value1of the second data item in operation543.

In the processing operation540, by using a barrel shifter, the shifting operation542and the OR operation543can be performed within one clock cycle.

Thus, by placing the operation540of processing the two data items into the one data item before the bitstream packing operation550, the processing can be completed in 32 clock cycles when a data item is an 8×8 block. Accordingly, if a processed data item of an 8×8 block is completely processed in the bitstream packing operation in 32 clock cycles, the same result as processing two data items at each clock without actual idling can be obtained in the variable length coding apparatus300.

Though an example where two data items are processed at each clock cycle is described above for convenience of explanation, by extending the structure of the prepacking unit described above, a moving picture encoding apparatus and a variable length coding apparatus capable of processing 2Ndata items at each clock cycle can be implemented.

FIG. 7is a block diagram illustrating a detailed structure of a prepacking unit which receives four data items and prepacks the four data items into one data item according to another embodiment of the present general inventive concept.

Referring toFIGS. 3 and 7, the prepacking unit may comprise a subunit #1710, a subunit #2720and a subunit #3730. Each of the subunit #1710and the subunit #2720receives two of the four data items from the variable length code generation unit330at each clock cycle and prepacks the two received data items into one data item. The subunit #3receives the data items prepacked by the subunit #1710and the subunit #2720at each clock cycle and prepacks the received data items into one data item. According to the prepacking unit shown inFIG. 7with this structure, four data items can be received and prepacked into one data item at each clock cycle. Though the first prepacked data item can be obtained in two clock cycles, data items are processed in the form of a pipeline and after two initial clock cycles, one data item can be obtained at each clock cycle.

The subunit #1710may comprise an addition unit711, a shift unit712, and an OR operation unit713.

The subunit #1can receive output data0formed with a code value0and a code length0and output data1formed with a code value1and a code length1output from the variable length code generation unit330. The addition unit711adds the code length0of the output data0and the code length1of the output data1. The shift unit712shifts the code value0of the output data0by the code length1of the output data1. A barrel shifter can be used as the shift unit712. The OR operation unit713performs an OR operation of the output value of the shift unit712and the code value1of the output data1. Thus, with the resulting value of the OR operation unit713as a code value4, and the resulting value of the addition unit711as a code length4, the subunit #1outputs a data item formed with the code value4and the code length4to the subunit #3730.

The subunit #2may comprise an second addition unit721, a second shift unit722, and a second OR operation unit723.

The subunit #2720can receive output data2formed with a code value2and a code length2and output data3formed with a code value3and a code length3output from the variable length code generation unit.

The second addition unit721adds the code length2of the output data2and the code length3of the output data3. The second shift unit722shifts the code value2of the output data2by the code length3of the output data3. The second OR operation unit723performs an OR operation of the output value of the second shift unit722and the code value3of the output data3. Thus, with the resulting value of the second OR operation unit723as a code value 5, and the resulting value of the second addition unit721as a code length5, subunit #2720outputs a data item formed with the code value5and the code length5to the subunit #3730.

The subunit #3may comprise a third addition unit731, a third shift unit732, and a third OR operation unit733.

The subunit #3730can receive the data item4formed with the code value4and the code length4output from the subunit #1710and the data item5formed with the code value5and the code length5output from the subunit #2720.

The third addition unit731adds the code length4of the data item4and code length5of the data item5. The third shift unit732shifts the code value4of the data item4by the code length5of the data item5. The third OR operation unit733performs an OR operation of the output value of the third shift unit732and the code value5of the data item5. Thus, with the resulting value of the third OR operation unit733as a code value6, and the resulting value of the third addition unit731as a code length6, the subunit #3outputs a data item6formed with the code value6and the code length6to the bitstream packing unit360.

Though a prepacking unit which receives four data items and prepacks into one data item at each clock cycle is described above, the structure of this prepacking unit can be extended. For example, in a structure of a prepacking unit where 8 data items are received at each clock cycle, four subunits to prepack the 8 data items into 4 data items are placed in a first stage, two subunits to prepack the 4 data items into 2 data items are placed in a second stage, and one subunit to prepack the 2 data items into one data item is placed in a third stage. In this case, 8 data items can be input to the prepacking unit and, though 3 clock cycles are needed for the first prepacked data output, after the 3 clock cycles, one data item can be output at each clock cycle.

According to the present general inventive concept as described above, by placing a prepacking unit which combines two data items into one data item, between a variable length code generating unit and a bitstream packing unit, a buffer for compensating for the difference of the input rate and the output rate, as described in the prior art, is not needed, and processing two data items at each clock cycle for high-speed moving picture encoding can be performed seamlessly.