Manufacturing method of array substrate, array substrate, and display apparatus

The present disclosure relates to an array substrate and the manufacturing method thereof, and a display apparatus. The manufacturing method of the array substrate comprises following step. A gate insulating layer and an active layer is formed on the substrate with said gate electrode and said common electrode formed thereon. A source drain layer is formed on the substrate with said gate insulating layer and said active layer formed thereon. A passivation layer is formed on the substrate with said source drain layer formed thereon, and a through hole is formed in the passivation layer; a pixel electrode is formed on the substrate with said passivation layer formed thereon with said through hole. The pixel electrode is connected to the drain electrode in the source drain layer through said through hole. The process for forming the pixel electrode comprises first etching, ashing and second etching.

FIELD

The present disclosure generally relates to an array substrate, a manufacturing method thereof and a display apparatus.

BACKGROUND

There has been a rapid progress in thin film transistor liquid crystal display (TFT-LCD) in the past few years. Although picture quality of a LCD (liquid crystal display) from front view might be great, the color might change if viewed from the side. Therefore wide viewing angle technologies become popular for reducing the color change upon viewing from the side. Advanced super dimension switch (ADSDS) is one of the wide viewing angle technologies recently developed to meet the requirements of a large screen high definition LCD for desktop and TV. In ADSDS technology, a multi-dimensional field is formed using a field formed by edges of the slit electrodes within a same plane and the field formed between the slit electrode and a plate electrode, causing rotations of liquid crystal molecules in any orientations within the liquid crystal cells between the slit electrodes and right above the electrodes, thereby increasing operation efficiency of the liquid crystals as well as improving the light transmittance. By ADSDS technology, display quality of a TFT-LCD can be improved with various advantages including high resolution, high transmittance, low power consumption, wide view angle, high aperture ratio, low chromatism, and no push mura etc.

As shown inFIG. 1, an ADSDS LCD panel comprises a color filter substrate12and an array substrate including a lower transparent ITO common electrode3′ (Vcom, may be in the form of a plate electrode) formed on a substrate1and an upper strip electrode8′ (may be formed as slit electrodes) as pixel electrode on a passivation layer7. The strip electrode8′ is formed by processes such as exposure, development, etching and lifting off etc. Lights are allowed to pass through most part of a color filter substrate12and the array substrate with the multi-dimensional field formed therebetween, thereby achieving a wide viewing angle with high brightness. It is noted that the transmittance of the ADSDS LCD panel is associated with pitch a of strip electrode8′.

In the ADSDS LCD panel, the pitch a of the strip electrodes is equal to a sum of a width (CD) b of a strip electrode and a spacing c between adjacent strip electrodes. In order to ensure a good brightness of the LCD panel, if the pitch a of the strip electrode is 10 μm, the width b of the strip electrode is 4 μm, and the spacing c between the electrodes is 6 μm; and if the pitch a of the strip electrode is 8 μm, the width b of the strip electrode is 2.6 μm, and the spacing c between the strip electrodes is 5.4 μm. An excellent brightness of the LCD panel may be achieved in case that the pitch a of the strip electrode is 6 μm, the width b of the strip electrode is 2 μm, and the spacing c is 4 μm. However, since a width limit that a conventional exposure apparatus may expose is in a range of 3-5.0 μm, it may be difficult to achieve a width b of the strip electrode less than 3 μm in reality. In addition, defects including mura or spots might occur due to width variation of the strip electrodes, thus decreasing display quality of the LCD panel.

FIG. 2shows the relationship between the transmittance of the LCD panel and the width b of the strip electrode. As the pitch a decreases, the brightness (i.e., transmittance) of the LCD panel increases. Despite of the increased brightness, the process window for maintaining a uniform brightness is decreased.

FIG. 3shows a simulation of transmittance variation vs a variation of width b of the strip electrode. The two curves inFIG. 3represent a case with a pitch a of the strip electrode of 8 μm and a case with a pitch a of 10 μm, respectively. It can be seen that in case of identical increase percentage of the width b, the transmittance changes more in the case with the pitch a of 8 μm than that in the case with the pitch a of 10 μm, thereby the former is more likely to cause defects such as spots or mura.

It may be known fromFIG. 2andFIG. 3that the smaller the pitch a of the strip electrode, the better the brightness of the LCD panel is, and if the pitch a of the strip electrodes is the same for all strip electrodes, the smaller the width b of the strip electrode is, the better the brightness of the LCD panel is.

SUMMARY

The embodiments of the present disclosure provides a manufacturing method of an array substrate, comprising steps of: forming a gate electrode and a common electrode on a substrate; forming a gate insulating layer and an active layer on said substrate with said gate electrode and said common electrode; forming a source/drain layer comprising a source and a drain on said substrate with said gate insulating layer and said active layer; forming a passivation layer on said substrate with said source/drain layer, and forming a through hole on said passivation layer; and forming a pixel electrode on said substrate with said passivation layer formed with said through hole, the pixel electrode being connected to the drain of the source/drain layer through the through hole. Forming the pixel electrode comprises following steps of: first etching, ashing and second etching.

The embodiments of the present disclosure provides an array substrate comprising: a substrate, a gate electrode and a common electrode formed on the substrate; a gate insulated layer formed on the substrate and covering the gate electrode and the common electrode; an active layer and a source/drain layer comprising a source and a drain sequentially formed on the gate insulating layer and above the gate electrode; a passivation layer with a through hole formed thereon, said passivation layer formed on the substrate and covering the active layer, the source/drain layer, and the gate insulating layer; and a pixel electrode formed on the passivation layer and connected to the drain in the source/drain layer through the through hole.

A display apparatus according to still another embodiment of the present disclosure comprises the above-mentioned array substrate.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments will now be described with reference toFIGS. 1 through 7, which relate to a memory device having at least one pre-treated surface for better adhesion of ink on the surface. It is understood that the present invention may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the invention to those skilled in the art. Indeed, the invention is intended to cover alternatives, modifications and equivalents of these embodiments, which are included within the scope and spirit of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be clear to those of ordinary skill in the art that the present invention may be practiced without such specific details.

The terms “top,” “bottom,” “upper,” “lower,” “vertical” and/or “horizontal” as may be used herein are for convenience and illustrative purposes only, and are not meant to limit the description of the invention inasmuch as the referenced item can be exchanged in position.

The present disclosure provides a way to form a smaller strip electrode in order to improve the transmittance of the display device and reduce defects such as spots or mura.

An array substrate according to embodiments of the present disclosure comprises a plurality of gate lines and a plurality of data lines intersecting each other to define pixel units arranged in a matrix. Each pixel unit comprises a thin film transistor as a switch element, and a pixel electrode and a common electrode for controlling the arrangement of the liquid crystals. For example, in each pixel, the gate of the thin film transistor is electrically connected to or formed integrally with the corresponding gate line, the source of the thin film transistor is electrically connected to or formed integrally with the corresponding data line, the drain of the thin film transistor is electrically connected to or formed integrally with the corresponding pixel electrode. The following description is provided with respect to a single or a plurality of pixel units; however, other pixel units may be formed in the same manner.

First Embodiment

FIG. 4is a flow chart of a manufacturing method of an array substrate according to an embodiment of the present disclosure. As shown inFIG. 4with reference toFIG. 7, the method according to the present embodiment comprises following steps:

Step S1, a transparent electrode31, a gate electrode2, a gate line (not shown) and a common electrode line32are formed on a substrate1. The gate electrode2, the gate line and the common electrode32may be formed from a metal thin film by patterning, and the transparent electrode31and the common electrode line32are electrically connected to each other to form the common electrode3, ie. a plate electrode.

The metal film in Step S1may comprise Mo, Cu, Al, AlNi alloy or the combinations thereof; the substrate1may be a glass substrate or a resin substrate etc.

Step S2, a gate insulating layer4and an amorphous Si thin film layer are deposited sequentially on the substrate1after Step S1, and an active layer5is formed on the gate insulating layer4by patterning.

The material of the gate insulating layer4in Step S2may be selected from silicon nitride or silicon oxide, while the amorphous silicon thin film may includes a stack of a lower n+a-Si amorphous silicon film52, an a-Si amorphous silicon thin film51and an upper n+a-Si amorphous silicon thin film52, for example.

Step S3, a metal thin film is deposited on the substrate after step S2, then a source/drain layer6comprising a source61and a drain62is formed by patterning the metal thin film. The space between the source61and the drain62exposes a part of the upper n+a-St amorphous silicon thin film52. The exposed part of the upper n+a-Si amorphous silicon thin film52is then etched off completely, and then a part of the subsequently exposed a-Si amorphous silicon thin film51is etched off, thus forming a TFT channel.

Step S4, a passivation layer7is deposited on the substrate after step S3, and a through hole H is formed on the passivation layer7.

Step S5, a pixel electrode8is formed on the substrate1after step S4, with the pixel electrode8being connected to the drain62in the source/drain layer6through the through hole H. The pixel electrode8may for example comprise a plurality of strip electrodes81overlapping with the transparent electrode31with a spacing between two adjacent strip electrodes81. The strip electrode81may be in a zigzaged shape or a linear shape. The process for forming the pixel electrode8at least comprises: a first etching, an ashing and a second etching process.

The patterning process described in the above steps at least comprises: coating, mask exposure, developing, etching, and lifting off or like.

As shown inFIG. 5, the step S5for example comprises following steps.

Step S51, as shown inFIG. 6a, a transparent conductive film9and a photoresist (PR)10are deposited on the passivation layer7sequentially. The transparent conductive film9may be an indium tin oxide (ITO) conductive film or an indium zinc oxide (IZO) conductive film. The present embodiment is described with respect to the ITO conductive film9.

Step S52, a photoresist pattern10′ is formed by exposure and development of the photoresist10using a mask plate11, as shown inFIG. 6b.

Step S53, a first etching process is performed on the ITO conductive film9in order to form the ITO conductive pattern9′, as shown inFIG. 6c.

Step S54, an ashing process is performed on the photoresist pattern10′ in order to form the photoresist pattern10″, as shown inFIG. 6d.

Step S55, a second etching process is performed on the ITO conductive pattern9′ using the photoresist pattern10″ as an etching mask in order to form the ITO conductive pattern9″, as shown inFIG. 6e.

Step S56, a photoresist pattern10″ is removed such as by lifting off so as to form the ITO conductive pattern9″ as the strip electrode81, as shown inFIG. 6f.

Despite that only one strip electrode81is shown inFIG. 5by way of example, those skilled in the art may appreciate that all or part of the strip electrodes81included in the pixel electrode8in the present embodiment may be formed by the above processes.

Adding the ashing process and the second etching process after the first etching process, the pitch of strip electrodes81may be in a range of 4.5-6 μm and preferably 4.5 μm. The width of the strip electrode81may be in a range of 1.5-2 μm and preferably 1.5 μm. The spacing between two adjacent strip electrodes81may be in a range of 3-4 μm, and preferably 3 μm. In one embodiment of the present disclosure, the pitch of all strip electrodes81included in the pixel electrode8is in a range of 4.5-6 μm and preferably 4.5 μm; the width of each strip electrode8is in a range of 1.5-2 μm and preferably 1.5 μm; and the spacing between any two adjacent strip electrodes81may be in a range of 3-4 μm and preferably 3 μm. It can be verified by experiment that the brightness of the LCD panel according to the embodiment of the present disclosure is improved by 20-30%, and the transmittance is also increased, and the defects such as spots or mura are reduced.

Second Embodiment

As shown inFIG. 7, the embodiments of the present disclosure provide an array substrate comprising a substrate1, a gate electrode2formed on the substrate1, a gate line (not shown), a common electrode32, and a gate insulating layer4formed on the substrate1. The gate insulating layer4covers the gate electrode2, the gate line and the common electrode. An active layer5and a source/drain layer6comprising a source61and a drain62are sequentially formed on the gate insulating layer4and above the gate electrode2. And a passivation layer7is formed in the substrate1, and a through hole H is formed in the passivation layer7. A pixel electrode8is formed on the passivation layer7and connected to the drain electrode62in the source/drain layer6through the through hole H. The common electrode comprises a transparent electrode31and a common electrode32. The pixel electrode8for example comprises a plurality of strip electrodes81overlapping with the transparent electrode31, for example, with a slit gap present between two adjacent strip electrodes81. The strip electrode81may be in a zigzaged shape or a linear shape.

The pitch of strip electrodes81is in a range of 4.5-6 μm, and preferably 4.5 μm; the width of the strip electrode81may be in a range of 1.5-2 μm, and preferably 1.5 μm; the spacing between two adjacent strip electrodes81is in a range of 3-4 μm, and preferably 3 μm. In one embodiment of the present disclosure, the pitch of all strip electrodes81included in the pixel electrode8is in a range of 4.5-6 μm, and preferably 4.5 μm; the width of each strip electrodes8is in a range of 1.5-2 μm, and preferably 1.5 μm; the spacing between any two adjacent strip electrodes81may be in a range of 3-4 μm, and preferably 3 μM.

Third Embodiment

A display apparatus according to still another embodiment of the present disclosure comprises the array substrate according to any of the embodiments described as above. The display apparatus according to the embodiments of the present disclosure may be a LCD apparatus comprising a counter substrate. The display apparatus for example may be used in LCD TV, cell phones, LCD displays, GPS etc. The array substrate and the counter substrate are provided opposing each other so as to form a liquid crystal cell with liquid crystal material filled therein. The counter substrate may be a color filter substrate. The pixel electrode in each pixel unit of the array substrate is used to apply an electric field to control the rotation of the liquid crystal materials, thereby operating the display apparatus. In some of the exemplary embodiments, the LCD display apparatus further comprises a back-light unit to provide back lights for the array substrate.

The display apparatus according to the embodiments of the present disclosure may for example be a display apparatus of any other type without a color filter substrate such as an electronic paper display apparatus.

Each embodiment of the present disclosure may be applied to an ADSDS type LCD apparatus or an IPS type LCD apparatus.

According to the above embodiments, when the strip electrodes are formed, the aching and the second etching process are added following the first etching, which make the pattern of the strip electrodes is smaller, leading to an improvement of the brightness and transmittance of the display device, thereby reducing the defects such as spots and mura, and improving the display quality of the LCD panel.

According to the descriptions above, the embodiments of the present disclosure may at least provide apparatus and methods as below.

(1) A manufacturing method of an array substrate, comprising steps of: forming a gate electrode and a common electrode on a substrate; forming a gate insulating layer and an active layer on said substrate with said gate electrode and said common electrode; forming a source/drain layer comprising a source and a drain on said substrate with said gate insulating layer and said active layer; forming a passivation layer on said substrate with said source/drain layer, and forming a through hole on said passivation layer; and forming a pixel electrode on said substrate with said passivation layer formed with said through hole, the pixel electrode being connected to the drain of the source/drain layer through the through hole; wherein forming the pixel electrode comprises following steps of a first etching, an ashing and a second etching process.

(2) The method according to (1), wherein the process for forming the pixel electrode layer comprises: depositing a transparent conductive film and a photoresist sequentially on the passivation layer; exposing and developing said photoresist to form a first photoresist pattern; performing the first etching on the transparent conductive film using the first photoresist pattern as a mask to form a first transparent conductive pattern; performing the ashing on the first photoresist pattern to form a second photoresist pattern; performing the second etching on the first transparent conductive pattern using the second photoresist pattern as a mask to form a second transparent conductive pattern; and lifting off the second photoresist pattern.

(3). The method according to (1) or (2), wherein the pixel electrode is formed as at least two adjacent strip electrodes, said at least two adjacent strip electrodes has a pitch of 4.5-6 μm, and at least one of the said at least two adjacent strip electrodes has a width of 1.5-2 μm.

(4). The method according to (3), wherein said at least two adjacent strip electrodes has a pitch of 4.5 μm, and at least one of the said at least two adjacent strip electrodes has a width of 1.5 μm.

(5). The method according to (1), wherein the pixel electrode is formed to at least partially overlap with the common electrode.

(6). The method according to (1), wherein the common electrode is in the form of a plate.

(7). An array substrate manufactured according to claim1, comprising: a substrate, a gate electrode and a common electrode formed on the substrate; a gate insulated layer formed on the substrate and covering the gate electrode and the common electrode; an active layer and a source/drain layer comprising a source and a drain sequentially formed on the gate insulating layer and above the gate electrode; a passivation layer with a through hole formed thereon, said passivation layer formed on the substrate and covering the active layer, the source/drain layer, and the gate insulating layer; and a pixel electrode formed on the passivation layer and connected to the drain in the source/drain layer through the through hole.

(8). The array substrate according to (7), wherein the pixel electrode is formed as comprising at least two adjacent strip electrodes, said at least two adjacent strip electrodes has a pitch of 4.5-6 μm, and at least one of the said at least two adjacent strip electrodes has a width of 1.5-2 μm.

(9). The array substrate according to (7), wherein the pitch of said at least two adjacent strip electrodes is 4.5 μm, and at least one of the said at least two adjacent strip electrodes has a width of 1.5 μm.

(10) a display apparatus, comprising the array substrate according to (7).