PASSIVE PHASE INTERPOLATOR

A phase interpolator for generating a phase interpolated output signal between two phase separated input signals received at two phase separated input signal nodes may include a plurality of circuit elements. The plurality of circuit elements may include at least one of resistors or capacitors, in a series arrangement between the two phase separated input signal nodes, where respective connection points between respective ones of the plurality of circuit elements may provide at least one intermediate phase interpolated signal. The phase interpolator may also include selection circuitry, which may be configured to select the phase interpolated output signal from the at least one intermediate phase interpolated signal.

TECHNOLOGICAL FIELD

The present disclosure relates to electronics, and more particularly, but not by way of limitation, to a phase interpolator that can be constructed at least partially with passive components.

BACKGROUND

Electronic systems can use a phase interpolator to derive a signal with a new phase. For example, it may be beneficial for a system to generate a clock signal that is phase delayed from another clock signal. This phase delayed signal may be desired for one or more processes in a signal analysis circuit or integrated circuit. Phase interpolation may also be desired to obtain an intermediate phase between two phase separated signals.

SUMMARY

In an approach, a phase interpolator may be constructed using one or more current sources, such as may include one or more current mirrors. The current sources and current mirrors may need to be constructed and tuned with a specified level of precision. For example, the current sources and current mirrors may need to be stable over a range of process, voltage, and temperature (PVT) variation. This may result in a phase interpolator that is one or more of expensive to manufacture, inaccurate, unstable, or large in size.

The present inventors have recognized, among other things, that it may be desirable to construct a phase interpolator circuit at least in part using passive elements, such as may include capacitors and resistors. The passive circuit elements may be one or more of easier to manufacture, smaller in size, or more accurate than some approaches to phase interpolation. For example, the phase shift of the phase interpolator may be determined by selecting component values such as capacitance and resistance. The use of passive components may also help to alleviate the need for matching between active components, tuning of active components, or both. This document describes, among other things, a phase interpolator that can be constructed at least in part using passive components.

In an example a phase interpolator for generating a phase interpolated output signal between two phase separated input signals received at two phase separated input signal nodes may include a plurality of circuit elements. The plurality of circuit elements may include at least one of resistors or capacitors, in a series arrangement between the two phase separated input signal nodes, where respective connection points between respective ones of the plurality of circuit elements may provide at least one intermediate phase interpolated signal. The phase interpolator may also include selection circuitry, which may be configured to select the phase interpolated output signal from the at least one intermediate phase interpolated signal.

In an example, a system for generating a phase shifted output signal from at least three input signals may include signal selection circuitry, which may be configured to select a first intermediate signal and a second intermediate signal from the at least three input signals, where the first intermediate signal is phase shifted from the second intermediate signal. The system may also include a plurality of resistors, which may be in a series arrangement between a first intermediate signal node carrying the first intermediate signal and a second intermediate signal node carrying the second intermediate signal; where respective connection points between respective ones of the plurality of resistors form output nodes. The system may also include multiplexor circuitry, which may be configured to select the phase shifted output signal from a specified one of the output nodes.

In an example, a method of interpolating a phase between two phase separated input signals may include providing the two phase separated input signals to opposite ends of a plurality of resistors in a series arrangement, where respective connection points between respective ones of the plurality of resistors may define phase interpolated nodes. The method may also include selecting a phase interpolated node.

DETAILED DESCRIPTION

A signal that is periodic or otherwise recurrent may have a phase value. A time to complete an entire cycle of the signal may be called the period. The entire period may be assigned a phase value equivalent to one period, for example, 360 degrees. A signal of the same waveform that is phase shifted in time may be labelled with a phase shift value. For example, a signal that is one quarter of a period ahead may be assigned a phase of 90 degrees, and a signal that is one quarter of a period behind may be assigned of phase of negative 90 degrees. A phase shifted sinusoidal signal may be represented by equation 1.

In equation 1, ω is the frequency of the sinusoid, t is time, and θ is the phase shift.

A signal may be represented as a weighted sum of in-phase and quadrature-phase components, where the quadrature-phase components is shifted by 90 degrees from the in-phase component. For example, a sinusoidal signal may be represented by equation 2.

In equation 2, I is the in-phase weight and Q is the quadrature-phase weight. The sine function may be 90 degrees behind the cosine function, which may provide the 90 degree phase shift for the quadrature-phase weight.

Equation 1 may be expanded to show an equivalent representation of a phase shifted sinusoidal signal in terms of in-phase and quadrature-phase components as shown in equations 3-4.

In equation 4, I=sin(θ) and Q=cos(θ). Therefore, equation 4 shows how a phase shifted sinusoid may be constructed with a weighted sum of in-phase and quadrature-phase components. Equations 5 and 6 show the relationship between I, Q, and θ.

From equations 1-6, the in-phase and quadrature-phase weights for a given value of θ can be determined.

FIG.1is a schematic drawing of an example of portions of a phase interpolator circuit100.FIG.1shows that the phase interpolator circuit100may include a first input signal node112, a second input signal node114, an output selection signal node116, and an output signal node142. The phase interpolator circuit100may include a plurality of circuit elements120. The phase interpolator circuit100may also include selection circuitry140.

The first input signal node112and the second input signal node114may receive phase separated signals. For example, the second input signal node114may receive a second input signal having the same waveform as a first input signal received on the first input signal node112, but the second input signal may be shifted forward or backward in time. In an example, the signals received by the first input signal node112and the second input signal node114may be required to be phase separated for the phase interpolator circuit100to generate an interpolated signal. For example, if the signals received on the first input signal node112and the second input signal node114are not phase separated, the phase interpolator circuit100may generate an output signal on the output signal node142that has a phase equal to the first input signal node112and the second input signal node114. In an example, the phase interpolator circuit100may receive a first input signal on the first input signal node112and use phase shift circuitry to generate a phase shifted signal on the second input signal node114. This may help to allow the phase interpolator circuit100to generate a phase interpolated output signal without phase separated input signals.

The plurality of circuit elements120may include one or more resistors, such as may include a resistor one121, a resistor two122, a resistor three123, a resistor four124, a resistor five125, a resistor six126, a resistor seven127, and a resistor eight128. The resistors121-128may be connected in a series arrangement to form the plurality of circuit elements120. One end of the plurality of circuit elements120may be connected to the first input signal node112, and the other end of the plurality of circuit elements120may be connected to the second input signal node114. In an example, the plurality of circuit elements120may include one or more other types of circuit elements, such as may include capacitors, or inductors, or both.

The respective connection points between the resistors121-128may form intermediate phase interpolated nodes. For example, the phase interpolated node one131may be formed at the connection point of resistor one121and resistor two122. The plurality of circuit elements120may also include a phase interpolated node two132, a phase interpolated node three133, a phase interpolated node four134, a phase interpolated node five135, a phase interpolated node six136, and a phase interpolated node seven137.

In an example, the plurality of circuit elements120may include one or more circuit elements in parallel. For example, one or more of the resistors121-128may represent an equivalent resistance value of two or more resistors in parallel. In an example, one or more of the resistors121-128may represent an equivalent resistance value of two or more resistors in series. In an example, one or more of the resistors121-128may represent an equivalent resistance value of two or more resistors in one or more of a series or parallel combination. In an example, one or more of the resistors121-128may represent an equivalent resistance of a circuit, such as may include a switched capacitor circuit.

The selection circuitry140may be configured to select one of the phase interpolated nodes131-137for connection to the output signal node142. The selection circuitry140may include a multiplexor. The selection circuitry140may receive a signal on the output selection signal node116, such as may include a binary signal. The selection circuitry140may output the phase interpolated node indicated by the signal on the output selection signal node116. In an example, the output selection signal node116may carry a signal indicating more than one phase interpolated node for output, and the selection circuitry140may be configured to output more than one phase interpolated signal. For example, the selection circuitry140may include two or more multiplexors. The inputs of each multiplexor may be coupled in parallel to the phase interpolated nodes131-137. The output selection signal carried on the output selection signal node116may be a binary signal with a portion of the binary signal corresponding to a first multiplexor and a portion of the binary signal corresponding to a second multiplexor. In an example, the selection circuitry140may be able to select three or more phase interpolated signals for output.

The component values of the plurality of circuit elements120may determine a relative phase shift of the phase interpolated nodes131-137. The resistors121-128may act as a voltage divider between the signal on the first input signal node112and the signal on the second input signal node114. The voltage at a specified phase interpolated node may be a weighted sum of the voltage on the first input signal node112and the voltage on the second input signal node114, where a weight of each voltage is determined by the values of the resistors121-128. For example, the voltage at node one131may be calculated according to equation 7.

In equation 7, V131is the voltage on phase interpolated node one131, V112is the voltage on the first input signal node112, and V114is the voltage on the second input signal node114. When a phase of the signal on the first input signal node112is different from a phase of the signal on the second input signal node114, the voltage dividing effect of the plurality of circuit elements120may act as a phase interpolator.

A linear phase separation between respective ones of the phase separated nodes131-137may be desired. For example, it may be desirable to have an equal phase spacing between adjacent connection points. This may result in there being an equal phase spacing between phase interpolated node one131and phase interpolated node two132as there is between phase interpolated node two132and phase interpolated node three133. In an example, the signal on the first input signal node112may be a sine wave, and the signal on the second input signal node114may be a cosine wave. The signal on the second input signal node114may lead the signal on the first input signal node112by 90 degrees. This may result in a desired phase shift of 11.25 degrees between respective ones of the phase separated nodes131-137. The phase separation of 90 degrees between the signal on the first input signal node112and the signal on the second input signal node114may allow for the use of the trigonometric formulas in equations 1 through 6 for determining the weighted sums of in-phase and quadrature-phase components to achieve the desired phase shift. For example, the weight of the signal on the first input signal node112and the weight of the signal on the second input signal node114may be calculated as shown in Table 1.

TABLE 1Desired PhasePhaseshift with respectInterpolatedto node 112 − θWeight of SignalWeight of SignalNode(degrees)B − I = sin (θ)A − Q = cos (θ)13111.250.1950.98113222.50.3830.92413333.750.5560.831134450.7070.70713556.250.8310.55613667.50.9240.38313778.750.9810.195
It may be desirable to normalize the weights so that the sum of the weights for a given phase interpolated node is equal to a constant, such as may include one. This may allow for one or more of the generation of the phase interpolated signals with only passive elements in the plurality of circuit elements120, or the generation of multiple phase interpolated values with a the plurality of circuit elements120. Table 2 shows the normalization of weights and the calculation of values for resistors121-128.

TABLE 2PhaseNormalization Factor:NormalizedNormalizedinterpolated Node1/(I + Q)IQ1310.8500.1660.8341320.7650.2930.7071330.7210.4010.5991340.7070.5000.5001350.7210.5990.4011360.7650.7070.2931370.8500.8340.166
From the normalized weights shown in Table 2, the component values of the plurality of circuit elements120may be calculated. A total desired series resistance may be selected, such as 100 kiloohms. The total series resistance may be selected to one or more of minimize energy dissipation in the resistors, minimize circuit area, or increase accuracy when there is a current in the output signal node142. From the total desired series resistance, a total resistance between each of the respective phase interpolated nodes131-137and the first input signal node112may be calculated to obtain the normalized weighting values. From the total resistance values, a differential total resistance between each of the phase interpolated nodes131-137may be calculated as the resistance value. Table 3 shows an example.

TABLE 3Totalized Value of AllResistors Between Bottom ofValue ofResistorResistor and Node 112 (ohms)Resistor (ohms)1211659116591122292891269812340054107651245000099461255994699461267071110765127834091269812810000016591
Table 3 shows that the resistance values may differ between respective resistors. For example, it may be necessary to use differing resistor values to achieve a uniform phase spacing between respective ones of the phase interpolated nodes131-137.

In an example, a non-linear phase spacing may be desired. For example, one or more of a logarithmic, sinusoidal, exponential, quadratic, or a phase spacing following any other function may be desired. Resistor values may be selected to provide a specified phase spacing.

FIG.2is a schematic drawing of an example of portions of a phase interpolator circuit100and portions of an example of a system in which the phase interpolator circuit100can be used.FIG.2shows that the phase interpolator circuit may include a phase selection signal node216, a clock selector230, a plurality of circuit elements120, selection circuitry140, and an output signal node142.

The plurality of circuit elements120and the selection circuitry140may be configured similarly to the example ofFIG.1, or the configuration may differ in one or more ways.FIG.2shows that the plurality of circuit elements120may include 31 resistors, including a resistor29249, a resistor30250, and a resistor31251. The plurality of circuit elements120may also include 30 interpolated nodes including phase interpolated node29259and phase interpolated node30260. The selection circuitry140may include 30 inputs coupled to the 30 phase interpolated nodes, and an output signal node142. The resistance values of the plurality of circuit elements120may be determined similarly to the resistance values forFIG.1. The phase spacing adjacent ones of the phase interpolated nodes may be evenly spaced or spaced by a specified phase spacing, such as may include one or more of logarithmic, exponential, etc.

The phase selection signal node216may receive a multi-bit digital signal that may determine the output phase of the signal on the output signal node142.FIG.2shows that the two most significant bits may form a “coarse” selection, such as may determine the phase of the signals input to the plurality of circuit elements120. The remaining bits (i.e., the bits in the multi-bit control signal less the two most significant bits) may form a “fine” selection that forms the signal on the output selection signal node116and controls the selection circuitry140to select a specific one of the interpolated nodes. For example, the second decoder280may remove the two most significant bits from the signal received on the phase selection signal node216and pass the signal to the output selection signal node116. The signal input on the phase selection signal node216, through the “coarse” and “fine” selection, may be able to select an input spanning the full range of the phase interpolator circuit100. In an example, the “coarse” selection may include more of less than two bits, such as may include one bit, two bits, three bits, four bits, or five bits. In an example, the number of bits received on the phase selection signal node216may include six bits, eight bits, 10 bits, 12 bits, or 14 bits.

The first decoder220may receive the two most significant bits received on the phase selection signal node216and generate four control signals on respective ones of the first control node222, a second control node224, a third control node226, and a fourth control node228. The first decoder220may demultiplex the two most significant bits into a four-bit signal where only a single output is high at one time.

The clock selector230may accept as inputs four control signals on respective ones of the first control node222, the second control node224, the third control node226, and the fourth control node228. The clock selector230may also accept as inputs four signals on respective ones of a first signal node232, a second signal node234, a third signal node236, and a fourth signal node238. One or more of the signals on nodes232-238may be phase separated from one or more of the other signals. In an example, each of the signals may have a different phase. In an example, the signals received on the nodes232-238may be sinusoidal signals separated by 90 degrees. The signals received by nodes232-238may be generated by a an IQ-generator that receives a clock signal, such as may include a square wave signal, and generates four sinusoidal outputs each phase separated by 90 degrees (i.e., the first signal has a phase of zero degrees, the second signal has a relative phase of 90 degrees, the third signal has a relative phase of 180 degrees, and the fourth signal has a relative phase of 270 degrees).

The clock selector230may output one of the input signals to a first output node242and another one of the output signals to a second output node244. The signals output may depend upon the status of the four control signals. In an example, the clock selector230may output pairs of signals that are separated by 90 degrees, with the leading signal on the second output node244. Table 3 shows an example of the clock selector230functioning.

TABLE 3Control Node withPhase on Node 242Phase on Node 244High Signal(degrees)(degrees)222090224901802261802702282700
Table three shows that one of the control nodes222-228may receive a high signal at one time, and the remaining of the control nodes222-228may receive a low signal. The control node222-228with the high signal may determine which of the signals received on the signal nodes232-238are output to the first output node242and second output node244. A 0 degree phase may be equivalent to a 360 degree phase. Therefore, a signal with a 0 degree phase (e.g., a 360 degree phase signal) may lead a signal with a 270 degree phase by 90 degrees.

The signal on the first output node242may pass through an inverting buffer212before it reaches the first input signal node112. The inverting buffer212may be configured to one or more of increase an available signal voltage, increase an available signal current, or maintain the waveform of the signal. The inverting buffer212may also invert the signal on the first output node242before it is passed to the first input signal node112. In an example, the phase interpolator circuit100or another circuit may account for the inversion generated by the inverting buffer212. For example, an inversion may result in a 180 degree phase shift, and this may be accounted for in the circuit design or output selection.

The signal on the second output node244may pass through an inverting buffer212before it reaches the second input signal node114. The inverting buffer212connected between the second output node244and the second input signal node114may be configured similarly to the inverting buffer212connected between the first output node242and the first input signal node112, or the configuration may differ in one or more ways.

One or more optional output circuits144may be connected to the output signal node142. The output circuit144may receive the signal on the output signal node142as an input and generate an adjusted output146. In an example, the one or more optional output circuits144may be configured to convert a sine wave received on the output signal node142, to a clock signal, such as may include a square clock wave. For example, the output circuit144may convert a sinusoidal or other input signal into an output signal with at least one of a defined rising edge or a defined falling edge. The amplitude of the clock signal output to the adjusted output146may not be dependent upon the amplitude of the signal received on the output signal node142. The output circuit144may use a complimentary transistor inverter to generate the clock signal.

In an example, the one or more optional output circuits144may be a signal amplifier, such as may include an adjustable signal amplifier. The signal amplifier may amplify the signal received on the output signal node142while maintaining a shape of the waveform. The signal amplifier may help to correct a difference in amplitude between different selected output phases, such as may be due at least in part to the normalization factor in determining I and Q values. For example, a smaller normalization factor may result in a signal that has a smaller amplitude. The signal amplifier may amplify the signal received on the output signal node142towards at least one of a voltage or current level of the signal received on one or more of the first input signal node112or the second input signal node114.

In an example, the phase interpolator circuit100may be configured to output one of the outputs received on nodes232-238(i.e., output the received signal without phase shift). For example, the phase interpolator circuit100may directly connect the received signal to the output signal node142. In an example, the selection circuitry140may include one or more additional inputs connected to one or more of the first input signal node112or the second input signal node114, which may allow the selection circuitry140to output one of the input signals without interpolation. In an example, the phase interpolator circuit100ofFIG.2may operate at a frequency that is between 12 gigahertz and 16 gigahertz inclusive. In an example, the phase interpolator circuit100ofFIG.2may operate at a frequency that is above 16 gigahertz.

FIG.3is a schematic drawing of an example of portions of a phase interpolator circuit100and portions of an example of a system in which the phase interpolator circuit can be used. The phase interpolator circuit100shown inFIG.3may be configured similarly to the phase interpolator circuit100ofFIG.2except that the plurality of circuit elements120may include a series arrangement of 31 capacitors (i.e., capacitor one321, capacitor two322, capacitor three323. . . capacitor29349, capacitor30350, and capacitor31351).

The capacitance values of the capacitors included in the plurality of circuit elements120may be determined similarly to the resistance values ofFIG.1. For example, the plurality of circuit elements120may be considered a voltage divider, and equation for a capacitor voltage divider may be substituted for the equation of a resistor voltage divider. In an example, a phase interpolator circuit100implemented at least in part using capacitors may be desirable because it may be less noisy than a phase interpolator circuit100implemented using resistors. For example, capacitors may be less noisy than resistors due at least in part to their construction.

In the example ofFIG.3, one or more optional output circuits144may be connected to the output signal node142. The output circuit144may receive the signal on the output signal node142as an input and generate an adjusted output146. The one or more optional output circuits144may be configured similarly to the one or more optional output circuits144ofFIG.2, or may differ in one or more ways.

FIG.4is a simulated plot showing an example of operating portions of the phase interpolator circuit100ofFIG.2. The output phase of the circuit is shown on the x-axis in degrees, and the input code is shown on the y-axis.FIG.4shows that the input to output relationship is generally linear from −55 degrees to 30 degrees, for a total range of approximately 85 degrees. In the example ofFIG.4, the phase interpolator circuit100receives a 7 bit control signal and produces 128 levels.

FIG.5is a diagram showing an example of a method500for operating portions of a phase interpolator circuit100. At505two phase separated input signals may be provided to opposite ends of a plurality of resistors in a series arrangement, wherein respective connection points between respective ones of the plurality of resistors define phase interpolated nodes. At510, a phase interpolated node may be selected. The shown order of steps is not intended to be a limitation on the order the steps are performed in. In an example, two or more steps may be performed simultaneously or at least partially concurrently.

At step505, the resistance values for respective ones of the plurality of resistors may be selected so that respective ones of the phase interpolated nodes generate a specified phase shift. In an example, the resistance values may be selected so that the phase of the phase interpolated nodes are consistent, such as may include being evenly spaced.

At step510, the phase interpolated node may be selected using selection circuitry140, such as may include a multiplexor. The method500may include one or more additional steps, such as may include using a “coarse” selection to determine the two phase interpolated input signals that are provided to the plurality of resistors and “fine” selection to determine the phase interpolated node that is selected.

The machine (e.g., computer system)600may include a hardware processor602(e.g., a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof), a main memory604, a static memory (e.g., memory or storage for firmware, microcode, a basic-input-output (BIOS), unified extensible firmware interface (UEFI), etc.)606, and mass storage608(e.g., hard drives, tape drives, flash storage, or other block devices) some or all of which may communicate with each other via an interlink (e.g., bus)630. The machine600may further include a display unit610, an alphanumeric input device612(e.g., a keyboard), and a user interface (UI) navigation device614(e.g., a mouse). In an example, the display unit610, input device612and UI navigation device614may be a touch screen display. The machine600may additionally include a storage device (e.g., drive unit)608, a signal generation device618(e.g., a speaker), a network interface device620, and one or more sensors616, such as a global positioning system (GPS) sensor, compass, accelerometer, or other sensor. The machine600may include an output controller628, such as a serial (e.g., universal serial bus (USB), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection to communicate or control one or more peripheral devices (e.g., a printer, card reader, etc.).

Registers of the processor602, the main memory604, the static memory606, or the mass storage608may be, or include, a machine readable medium622on which is stored one or more sets of data structures or instructions624(e.g., software) embodying or utilized by any one or more of the techniques or functions described herein. The instructions624may also reside, completely or at least partially, within any of registers of the processor602, the main memory604, the static memory606, or the mass storage608during execution thereof by the machine600. In an example, one or any combination of the hardware processor602, the main memory604, the static memory606, or the mass storage608may constitute the machine readable media622. While the machine readable medium622is illustrated as a single medium, the term “machine readable medium” may include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) configured to store the one or more instructions624.

In an example, information stored or otherwise provided on the machine readable medium622may be representative of the instructions624, such as instructions624themselves or a format from which the instructions624may be derived. This format from which the instructions624may be derived may include source code, encoded instructions (e.g., in compressed or encrypted form), packaged instructions (e.g., split into multiple packages), or the like. The information representative of the instructions624in the machine readable medium622may be processed by processing circuitry into the instructions to implement any of the operations discussed herein. For example, deriving the instructions624from the information (e.g., processing by the processing circuitry) may include: compiling (e.g., from source code, object code, etc.), interpreting, loading, organizing (e.g., dynamically or statically linking), encoding, decoding, encrypting, unencrypting, packaging, unpackaging, or otherwise manipulating the information into the instructions624.

In an example, the derivation of the instructions624may include assembly, compilation, or interpretation of the information (e.g., by the processing circuitry) to create the instructions624from some intermediate or preprocessed format provided by the machine readable medium622. The information, when provided in multiple parts, may be combined, unpacked, and modified to create the instructions624. For example, the information may be in multiple compressed source code packages (or object code, or binary executable code, etc.) on one or several remote servers. The source code packages may be encrypted when in transit over a network and decrypted, uncompressed, assembled (e.g., linked) if necessary, and compiled or interpreted (e.g., into a library, stand-alone executable etc.) at a local machine, and executed by the local machine.

ADDITIONAL NOTES & EXAMPLES

Example 1 is a phase interpolator for generating a phase interpolated output signal between two phase separated input signals, the two phase separated input signals received at two phase separated input signal nodes, the phase interpolator comprising: a plurality of circuit elements, the plurality of circuit elements including at least one of resistors or capacitors, in a series arrangement between the two phase separated input signal nodes, wherein respective connection points between respective ones of the plurality of circuit elements provide at least one intermediate phase interpolated signal; and selection circuitry, configured to select the phase interpolated output signal from the at least one intermediate phase interpolated signal.

In Example 2, the subject matter of Example 1 optionally includes wherein component values differ between respective ones of a like type of the plurality of circuit elements.

In Example 3, the subject matter of Example 2 optionally includes wherein the component values of the respective ones of the plurality of circuit elements provide an equal phase spacing between adjacent connection points.

In Example 4, the subject matter of any one or more of Examples 1-3 optionally include wherein the selection circuitry includes a multiplexor with inputs connected to the at least one intermediate phase interpolated signal and an output providing the phase interpolated output signal.

In Example 5, the subject matter of Example 4 optionally includes amplifier circuitry configured to amplify at least one of a voltage or current level of the phase interpolated output signal towards at least one of a voltage or current level of the two phase separated input signals.

In Example 6, the subject matter of any one or more of Examples 1-5 optionally include wherein the two phase separated input signals are sinusoidal, and wherein the phase interpolated output signal is sinusoidal.

In Example 7, the subject matter of Example 6 optionally includes buffer circuitry to convert the phase interpolated output signal to a clock signal with at least one of a defined rising edge or a defined falling edge.

In Example 8, the subject matter of any one or more of Examples 1-7 optionally include wherein the plurality of circuit elements includes at least eight resistors connected in series.

In Example 9, the subject matter of any one or more of Examples 1-8 optionally include wherein the plurality of circuit elements includes at least eight capacitors connected in series.

Example 10 is a system for generating a phase shifted output signal from at least three input signals, the system comprising: signal selection circuitry, configured to select a first intermediate signal and a second intermediate signal from the at least three input signals, wherein the first intermediate signal is phase shifted from the second intermediate signal; a plurality of resistors, in a series arrangement between a first intermediate signal node carrying the first intermediate signal and a second intermediate signal node carrying the second intermediate signal; wherein respective connection points between respective ones of the plurality of resistors form output nodes; and multiplexor circuitry, configured to select the phase shifted output signal from a specified one of the output nodes.

In Example 11, the subject matter of Example 10 optionally includes wherein the at least three input signals are spaced across a specified phase range.

In Example 12, the subject matter of Example 11 optionally includes wherein the system includes four intermediate signals, wherein respective ones of the four intermediate signals are phase shifted by ninety degrees.

In Example 13, the subject matter of any one or more of Examples 10-12 optionally include a multi-bit control signal, wherein a specified number of most significant bits comprise a “coarse” selection and are configured to control the signal selection circuitry to select the first intermediate signal and the second intermediate signal, and a remaining number of least significant bits comprise a “fine” selection and are configured to control the multiplexor circuitry to select the specified one of the output nodes.

In Example 14, the subject matter of any one or more of Examples 10-13 optionally include wherein the multiplexor circuitry includes respective inputs connected to respective output nodes and an output connected to a phase shifted output signal node that carries the phase shifted output.

In Example 15, the subject matter of any one or more of Examples 10-14 optionally include wherein the multiplexor circuitry is configured to allow the selection of the first intermediate signal or the second intermediate signal as the phase shifted output signal.

In Example 16, the subject matter of any one or more of Examples 10-15 optionally include second multiplexor circuitry configured to select a second phase shifted output signal from a second specified output node.

In Example 17, the subject matter of any one or more of Examples 10-16 optionally include gigahertz inclusive.

Example 18 is a method of interpolating a phase between two phase separated input signals, the method comprising: providing the two phase separated input signals to opposite ends of a plurality of resistors in a series arrangement, wherein respective connection points between respective ones of the plurality of resistors define phase interpolated nodes; and selecting a phase interpolated node.

In Example 19, the subject matter of Example 18 optionally includes selecting resistance values for the respective ones of the plurality of resistors so that the respective ones of the phase interpolated nodes generate a specified phase shift.

In Example 20, the subject matter of any one or more of Examples 18-19 optionally include wherein the selecting resistance values includes selecting resistance values so that a phase shift between respective ones of the phase interpolated nodes is consistent.

Each of the non-limiting aspects above can stand on its own or can be combined in various permutations or combinations with one or more of the other aspects or other subject matter described in this document.

Method examples described herein can be machine or computer-implemented at least in part. Some examples can include a computer-readable medium or machine-readable medium encoded with instructions operable to configure an electronic device to perform methods as described in the above examples. An implementation of such methods can include code, such as microcode, assembly language code, a higher-level language code, or the like. Such code can include computer readable instructions for performing various methods. The code may form portions of computer program products. Such instructions can be read and executed by one or more processors to enable performance of operations comprising a method, for example. The instructions are in any suitable form, such as but not limited to source code, compiled code, interpreted code, executable code, static code, dynamic code, and the like.

Further, in an example, the code can be tangibly stored on one or more volatile, non-transitory, or non-volatile tangible computer-readable media, such as during execution or at other times. Examples of these tangible computer-readable media can include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact disks and digital video disks), magnetic cassettes, memory cards or sticks, random access memories (RAMs), read only memories (ROMs), and the like.