Ferroelectric memory device having ferroelectric induction layer and method of manufacturing the same

A ferroelectric memory device according to an aspect of the present disclosure includes a substrate having a channel layer, a first ferroelectric layer disposed on the channel layer, a ferroelectric induction layer disposed on the first ferroelectric layer, the ferroelectric induction layer including an insulator, a second ferroelectric layer disposed on the ferroelectric induction layer, and a gate electrode layer disposed on the second ferroelectric layer.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean Patent Application No. 10-2019-0095789, filed on Aug. 6, 2019, which is herein incorporated by reference in its entirety.

BACKGROUND

1. Technical Field

The present disclosure relates generally to a ferroelectric memory device and a method of manufacturing the same and, more particularly, to a ferroelectric memory device having a ferroelectric induction layer and a method of manufacturing the same.

2. Related Art

Generally, a ferroelectric material refers to a material having spontaneous electrical polarization in the absence of an external electric field. In addition, the electrical polarization of the ferroelectric material may exhibit a hysteresis behavior when an external electric field is applied. Accordingly, various polarization states can be recorded in the ferroelectric material along a hysteresis curve by controlling the applied electric field. The recorded polarization can be stored in the ferroelectric material in a nonvolatile manner after the applied electric field is removed. This characteristic can be applied to a memory device that stores signal information in a nonvolatile manner.

Recently, a ferroelectric memory device in the form of a field effect transistor applying a ferroelectric material as a gate dielectric layer has been studied. The write operation of the ferroelectric memory device may be performed by applying a predetermined write voltage to a gate electrode layer to record different remanent polarization states as logic information in a gate dielectric layer. The read operation of the ferroelectric memory device may be performed by reading channel currents having different magnitudes passing through a channel layer of the field effect transistor using the property that the channel resistance of the field effect transistor changes according to the different remanent polarization states recorded in the gate dielectric layer.

SUMMARY

A ferroelectric memory device according to an aspect of the present disclosure includes a substrate having a channel layer, a first ferroelectric layer disposed on the channel layer, a ferroelectric induction layer disposed on the first ferroelectric layer, the ferroelectric induction layer including an insulator, a second ferroelectric layer disposed on the ferroelectric induction layer, and a gate electrode layer disposed on the second ferroelectric layer.

A ferroelectric memory device according to another aspect of the present disclosure includes a substrate, a gate stack disposed on the substrate, the gate stack comprising at least one gate structure and at least one interlayer insulation layer, which are alternately stacked in a direction perpendicular to the substrate, a trench penetrating the gate stack to expose side surfaces of the gate structure and interlayer insulation layer, a first gate dielectric layer disposed on an inner surface of the trench, the first gate dielectric layer comprising a ferroelectric portion and a non-ferroelectric portion, and a channel layer disposed to cover the first gate dielectric layer. The gate structure includes a ferroelectric induction layer in contact with the interlayer insulation layer and the first gate dielectric layer, a second gate dielectric layer in contact with the ferroelectric induction layer, and a gate electrode layer in contact with the second gate dielectric layer.

A ferroelectric memory device according to yet another aspect of the present disclosure includes a substrate, a gate stack disposed on the substrate, the gate stack comprising at least one gate structure and at least one interlayer insulation layer, which are alternately stacked in a direction perpendicular to the substrate, a trench penetrating the gate stack to expose side surfaces of the gate structure and the at least one interlayer insulation layer, a first gate dielectric layer disposed on an inner surface of the trench, a ferroelectric induction layer disposed on the first gate dielectric layer along the inner surface of the trench, a second gate dielectric layer disposed on the ferroelectric induction layer along the inner surface of the trench, and a channel layer disposed to cover the second gate dielectric layer. The gate structure comprises an interlayer insulation layer and a gate electrode layer in contact with the first gate dielectric layer.

A method of manufacturing a ferroelectric memory device according to yet another aspect of the present disclosure is disclosed. In the method, a stack structure including interlayer sacrificial layers and interlayer insulation layers, alternately stacked is formed on a substrate. A trench penetrating the stack structure is formed. A first ferroelectric amorphous material layer and a channel layer are sequentially formed on an inner surface of the trench. The interlayer sacrificial layers are selectively removed to form recesses that expose the interlayer insulation layers and the first ferroelectric amorphous material layer. A ferroelectric induction layer is formed on the first ferroelectric amorphous material layer and the interlayer insulation layers, inside each of the recesses. A second ferroelectric amorphous material layer in contact with the ferroelectric induction layer, inside the recesses is formed. A gate electrode layer in contact with the second ferroelectric amorphous material layer, inside the recesses is formed. A crystallization heat treatment is performed to develop ferroelectric properties in portion of the first ferroelectric amorphous material layer and the second ferroelectric amorphous material layers using the ferroelectric induction layer.

A method of manufacturing a ferroelectric memory device according to still yet another aspect of the present disclosure is disclosed. In the method, a stack structure including interlayer sacrificial layers and interlayer insulation layers, which are sequentially stacked is formed on a substrate. A trench penetrating the stack structure is formed. A first ferroelectric amorphous material layer, a ferroelectric induction layer, a second ferroelectric amorphous material layer and a channel layer are sequentially formed on an inner surface of the trench. The interlayer sacrificial layers are selectively removed to form recesses that expose the interlayer insulation layers and the first ferroelectric amorphous material layer. A gate electrode layer is formed on the first ferroelectric amorphous material layer and the interlayer insulation layers, inside each of the recesses. A crystallization heat treatment is performed to develop ferroelectric properties in portion of the first ferroelectric amorphous material layer and the second ferroelectric amorphous material layers using the ferroelectric induction layer.

DETAILED DESCRIPTION

Various embodiments will now be described hereinafter with reference to the accompanying drawings. In the drawings, the dimensions of layers and regions may be exaggerated for clarity of illustration. As a whole, the drawings are described at an observer's viewpoint. If an element is referred to be located “on” or “under” another element, it may be understood that the element is directly located “on” or “under” the other element, or an additional element may be interposed between the element and the other element. The same reference numerals in the drawings refer to substantially the same elements as each other.

In addition, expression of a singular form of a word should be understood to include the plural forms of the word unless clearly used otherwise in the context. It will be understood that the terms “comprise” or “have” are intended to specify the presence of a feature, a number, a step, an operation, an element, a part, or combinations thereof, but not used to preclude the presence or possibility of addition one or more other features, numbers, steps, operations, components, parts, or combinations thereof. Further, in performing a method or a manufacturing method, each process constituting the method can take place differently from the stipulated order unless a specific sequence is described explicitly in the context. In other words, each process may be performed in the same manner as stated order, may be performed substantially at the same time, or may be performed in a reverse order.

FIG. 1Ais a hysteresis graph1000schematically illustrating a polarization characteristic of a ferroelectric layer under an applied electric field according to an embodiment of the present disclosure.FIG. 1Billustrates a ferroelectric device structure for measuring the polarization characteristic of the ferroelectric layer illustrated inFIG. 1A.

Referring toFIG. 1B, a ferroelectric device structure1000S may include a first electrode1001, a ferroelectric layer1002, and a second electrode1003. The ferroelectric layer1002may be applied to ferroelectric memory devices1,2,3and4according to embodiments of the present disclosure as first and second ferroelectric layers, respectively.

Referring toFIGS. 1A and 1B, when an electric field is applied between the first and second electrodes1001and1003of the ferroelectric device structure1000S, polarization of the ferroelectric layer1002may have a characteristic that follows the hysteresis graph1000with respect to the applied electric field. The hysteresis graph1000may represent a pair of first and second coercive electric fields Ec and −Ec, and a pair of first and second remanent polarization Pr and −Pr. At this time, the first remanent polarization Pr may have a first polarization orientation, and the second remanent polarization −Pr may have a second polarization orientation. In addition, the hysteresis graph1000may represent a pair of saturation polarization Ps and −Ps at a pair of respective saturation electric fields Es and −Es.

In an embodiment, for the ferroelectric layer1002having the second remanent polarization −Pr, while the second electrode1003is grounded, the polarization of the ferroelectric layer1002may be measured by sequentially applying an electric field having a positive polarity to the first electrode1001while increasing the electric field. When the applied electric field increases to a first coercive electric field Ec or higher, the polarization orientation of the ferroelectric layer1002can be changed from the second polarization orientation to the first polarization orientation. In addition, when the applied electric field increases to the first saturation electric field Es or higher, the ferroelectric layer1002may have the first saturation polarization Ps. After the applied electric field is removed, the ferroelectric layer1002may have the first remanent polarization Pr.

In another embodiment, for the ferroelectric layer1002having the first remanent polarization Pr, while the second electrode1003is grounded, the polarization of the ferroelectric layer1002may be measured by sequentially applying an electric field having a negative polarity to the first electrode1001while increasing an absolute value of the electric field. When the absolute value of the applied electric field increases to an absolute value of the second coercive electric field −Ec or higher, the polarization orientation of the ferroelectric layer1002may be changed from the first polarization orientation to the second polarization orientation. In addition, when the absolute value of the applied electric field increases to the second saturation electric field −Es or higher, the ferroelectric layer1002may have the second saturation polarization −Ps. After the applied electric field is removed, the ferroelectric layer1002may have the second remanent polarization −Pr.

In other embodiments, as a method of changing the second remanent polarization −Pr in ferroelectric layer1002to the first saturation polarization Ps, a method is used in which a predetermined first operation electric field Ep having a magnitude greater than or equal to the first coercive electric field Ec is applied to the ferroelectric layer1002for a predetermined first operation time period tp1. The predetermined first operation time period tp1may be a time sufficient to switch the second polarization orientation in the ferroelectric layer1002to the first polarization orientation. Thereafter, the ferroelectric layer1002may have the first remanent polarization Pr by removing the first operation electric field Ep. As an example, the electric field may be applied in a form of a pulse wave.

In yet other embodiments, multi-level polarization can be recorded in the ferroelectric layer1002by controlling the time during which the first operation electric field Ep is applied to the ferroelectric layer1002. For instance, the ferroelectric layer1002may be adjusted to have polarization between zero (0) and the first saturation polarization Ps by applying a first operation electric field Ep to the ferroelectric layer1002, having a second remanent polarization −Pr, for a time period shorter than the first operation time period tp1. Thereafter, when the first operation electric field Ep is removed, the ferroelectric layer1002may have predetermined remanent polarization between 0 and the first remanent polarization Pr. By the above-described method, the multilevel remanent polarization corresponding to signal information can be stored in the ferroelectric layer1002.

Likewise, a predetermined second operation electric field −Ep greater than or equal to the second coercive electric field −Ec in absolute value may be applied to the ferroelectric layer1002having the first remanent polarization Pr for a predetermined second operation time period tp2, thereby causing the ferroelectric layer1002to have the second saturation polarization −Ps. In this case, the predetermined second operation time period tp2may be a time sufficient to switch the first polarization orientation in the ferroelectric layer1002into the second polarization orientation. Thereafter, when the second operation electric field −Ep is removed, the ferroelectric layer1002may have the second remanent polarization −Pr. Accordingly, the multilevel polarization can be recorded in the ferroelectric layer1002by controlling the time during which the second operation electric field −Ep is applied to the ferroelectric layer1002.

For example, the ferroelectric layer1002may be adjusted to have polarization between 0 and the second saturation polarization −Ps by applying a second operation electric field −Ep to the ferroelectric layer1002, having a second remanent polarization −Pr, for a time period shorter than the second operation time period tp2. Thereafter, when the second operation electric field −Ep is removed, the ferroelectric layer1002may have a predetermined remanent polarization between 0 and the second remanent polarization −Pr. By the above-described methods, multilevel remanent polarization corresponding to different signal information can be stored in the ferroelectric layer1002.

When a plurality of operation voltages are actually applied to the ferroelectric layer1002to record multilevel polarization, a voltage gap between the plurality of operation voltages must be large enough to sufficiently identify polarization of adjacent levels among the multiple levels. In addition, in order to increase the number of the multilevels, it may be required to increase the number of different operation voltages that may be applied to the ferroelectric layer1002. For these reasons, larger absolute values of the first and second remanent polarization Pr and −Pr and the corresponding absolute values of the first and second saturation polarization Ps and −Ps may be advantageous.

As described above, the maximum range of the operation voltages applied to the ferroelectric layer1002to record the remanent polarization distinguished from each other may be defined as a memory window. The memory window may be determined by multiplying two (2)×absolute value of coercive electric field of the ferroelectric layer×thickness of the ferroelectric layer. In this case, the coercive electric field of the ferroelectric layer may be due to a material property of the ferroelectric layer. Accordingly, after the ferroelectric material used in the ferroelectric layer is determined, the memory window may become larger as the thickness of the ferroelectric layer increases.

Meanwhile, in an embodiment of the present disclosure, the ferroelectric layer of the ferroelectric memory device may include hafnium oxide, zirconium oxide, hafnium zirconium oxide, or a combination of two or more ferroelectric materials thereof. It has been reported that a ferroelectric material having a tetragonal crystal structure exhibits a ferroelectric property at a thickness of about fifteen nanometers (15 nm) or less, and a ferroelectric material having a monoclinic crystal structure exhibits a non-ferroelectric property at a thickness exceeding about 15 nm. Accordingly, when an above-described ferroelectric material is used in a ferroelectric layer disclosed herein, the thickness of the ferroelectric layer can be controlled to about 15 nm or less.

In an embodiment of the present disclosure, there is disclosed a structure of a ferroelectric memory device capable of increasing the effective thickness of the ferroelectric layer to a thickness exceeding about 15 nm, while maintaining ferroelectric properties of the ferroelectric layers, by including a ferroelectric induction layer. This can effectively increase the memory window of the ferroelectric memory device.

FIG. 2is a cross-sectional view schematically illustrating a ferroelectric memory device according to an embodiment of the present disclosure.

Referring toFIG. 2, a ferroelectric memory device1may include a substrate101and a gate structure1adisposed on the substrate101. The gate structure1amay include a first ferroelectric layer125, a ferroelectric induction layer130, a second ferroelectric layer145, and a gate electrode layer150. In addition, the ferroelectric memory device1may include a channel layer102positioned in a substrate10region under the first ferroelectric layer125. Further, the ferroelectric memory device1may include a source region112and a drain region114respectively positioned in regions of the substrate101at different ends of the channel layer102. In an embodiment, the ferroelectric memory device1may be a field effect transistor-type nonvolatile memory device.

The substrate101may include, for example, a semiconductor material. The substrate101may be a silicon (Si) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, a germanium (Ge) substrate, or a silicon germanium (SiGe) substrate, for example. In an embodiment, the substrate101may be doped to have conductivity. As an example, the substrate101may be doped with an n-type or p-type dopant. As another example, the substrate101may include a well region doped with an n-type or p-type dopant therein.

The source region112and the drain region114may be regions of the substrate101, doped into n-type or p-type. When the substrate101is doped into n-type or p-type, the source region112and the drain region114may be regions doped with a dopant of a type opposite to that used in the substrate101. The channel layer102may be a region of the substrate101in which a carrier with charge conducts when a voltage is applied between the source region112and the drain region114. For example, the channel layer102may refer to an area of the substrate101having high mobility of electrons or holes.

The first ferroelectric layer125may be disposed on the channel layer102. The first ferroelectric layer125may have substantially the same ferroelectric property as the ferroelectric layer1002described above with reference toFIGS. 1A and 1B. In an embodiment, the first ferroelectric layer125may include hafnium oxide, zirconium oxide, hafnium zirconium oxide, or a combination of two or more thereof. In an embodiment, the first ferroelectric layer125may include a dopant. The dopant may function to adjust the magnitude of the coercive electric field of a ferroelectric layer in the hysteresis graph ofFIG. 1A. For example, the first ferroelectric layer125may include silicon (Si), zirconium (Zr), yttrium (Y), aluminum (Al), gadolinium (Gd), strontium (Sr), lanthanum (La), or a combination of two or more thereof. In an embodiment, the first ferroelectric layer125may have a thickness of about 5 nm to about 15 nm. In this case, the first ferroelectric layer125may have an orthorhombic crystal structure.

The ferroelectric induction layer130and the second ferroelectric layer145may be sequentially disposed on the first ferroelectric layer125. The ferroelectric induction layer130may have a non-ferroelectric property. As an example, the ferroelectric induction layer130may have a paraelectric property. The ferroelectric induction layer130may have a crystalline phase. In addition, the ferroelectric induction layer130may include an insulator. In an embodiment, the ferroelectric induction layer130may include an insulative metal oxide. In an embodiment, when the first ferroelectric layer125includes hafnium oxide, zirconium oxide, hafnium zirconium oxide, or a combination of two or more thereof, the ferroelectric induction layer130may include magnesium oxide.

In an embodiment, the ferroelectric induction layer130may have a thickness of about 1 nm to about 5 nm. The ferroelectric induction layer130may function as a capacitor layer connected to the first and second ferroelectric layers125and145in series between the substrate101and the gate electrode layer150. As the thickness of the ferroelectric induction layer130increases, the total capacitance of the electrical circuit between the substrate101and the gate electrode layer150can decrease. Accordingly, in order to prevent excessive degradation of the total capacitance, the thickness of the ferroelectric induction layer130is maintained at 1 nm to 5 nm.

The second ferroelectric layer145may have substantially the same ferroelectric property as the ferroelectric layer1002described above with reference toFIGS. 1A and 1B. In an embodiment, the second ferroelectric layer145may include hafnium oxide, zirconium oxide, hafnium zirconium oxide, or a combination of two or more thereof. In an embodiment, the second ferroelectric layer145may include a dopant. The dopant may function to adjust the magnitude of a coercive electric field of a ferroelectric layer, in the hysteresis graph ofFIG. 1A. As an example, the second ferroelectric layer145may include silicon (Si), zirconium (Zr), yttrium (Y), aluminum (Al), gadolinium (Gd), strontium (Sr), lanthanum (La), or a combination of two or more thereof, as the dopant. In an embodiment, the second ferroelectric layer145may have a thickness of about 5 nm to about 15 nm. In this case, the second ferroelectric layer145may have an orthorhombic crystal structure.

In an embodiment, the first and second ferroelectric layers125and145may be formed of the same material. As an example, the first and second ferroelectric layers125and145may each be a hafnium oxide layer, zirconium oxide layer, or a hafnium zirconium oxide layer. In another embodiment, the first and second ferroelectric layers125and145may be formed of different materials. As an example, when the first ferroelectric layer125is a hafnium oxide layer, the second ferroelectric layer145may be a zirconium oxide layer. As another example, when the first ferroelectric layer125is a zirconium oxide layer, the second ferroelectric layer145may be a hafnium oxide layer.

Meanwhile, the ferroelectric induction layer130may have a lattice constant different from the lattice constants of the first and second ferroelectric layers125and145. As described below with reference toFIGS. 3 to 5, when a crystallization process transforms first and second ferroelectric amorphous material layers120and140into the first and second ferroelectric layers125and145, stress is induced at the respective interfaces of the ferroelectric induction layer130and the first and second ferroelectric layers125and145and applied to the interior of the first and second ferroelectric layers125and145. The stress is due to the lattice constant difference between the ferroelectric induction layer130and the first and second ferroelectric layers125and145. The stress may generate a lattice strain in the first and second ferroelectric layers125and145during the crystallization process. The lattice strain may form an electric field due to a flexoelectric effect in the first and second ferroelectric layers125and145. The electric field may induce each of the first and second ferroelectric layers125and145to be crystallized to have a crystal structure of a tetragonal system having a ferroelectric property. As a result, the crystallized first and second ferroelectric layers125and145can assist in stably securing a ferroelectric property in both layers.

The gate electrode layer150may be disposed on the second ferroelectric layer145. The gate electrode layer150may include a conductor. In an embodiment, the gate electrode layer150may have a lattice constant different from that of the second ferroelectric layer145. The gate electrode layer150may function as a ferroelectric induction layer with respect to the second ferroelectric layer145. In other words, in the above-described crystallization process for the first and second ferroelectric amorphous material layers120and140, the gate electrode layer150may apply stress to the second ferroelectric layer145. The stress may form a lattice strain in the crystallized second ferroelectric layer145. The lattice strain may form an electric field due to a flexoelectric effect in the second ferroelectric layer145, and the electric field may induce the second ferroelectric layer145to have a tetragonal crystal structure having ferroelectric property.

In some other embodiments, the gate electrode layer150may not function as a ferroelectric induction layer with respect to the second ferroelectric layer145. In this case, the second ferroelectric layer145may be induced to have a tetragonal crystal structure only by the ferroelectric induction layer130positioned thereunder.

The gate electrode layer150may include, for example, tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more thereof. When the gate electrode150functions as a ferroelectric induction layer with respect to the second ferroelectric layer145, the gate electrode layer150may include titanium nitride.

In an embodiment not illustrated, an interfacial insulation layer may be further disposed between the channel layer102and the first ferroelectric layer125. The interfacial insulation layer can prevent direct contact between the channel layer102and the first ferroelectric layer125to reduce the concentration of defect sites that may occur at an interface between the channel layer102and the first ferroelectric layer125. The interfacial insulation layer may include, for example, silicon oxide or aluminum oxide. The interfacial insulation layer may have an amorphous phase.

As described above, a ferroelectric memory device according to an embodiment of the present disclosure may include a first ferroelectric layer, a ferroelectric induction layer and a second ferroelectric layer that are sequentially disposed between a substrate and a gate electrode layer. The first ferroelectric layer, the ferroelectric induction layer and the second ferroelectric layer may constitute a gate dielectric layer structure of the ferroelectric memory device. In this case, the first and second ferroelectric layers may operate as memory functional layers that store remanent polarization.

A ferroelectric induction layer having a paraelectric property may be interposed between the first and second ferroelectric layers to help the first and second ferroelectric layers to stably secure the ferroelectric properties. That is, the ferroelectric induction layer may be used to substantially increase a thickness of a gate dielectric layer having ferroelectric property in the ferroelectric memory device. Accordingly, the memory window of the ferroelectric memory device can be effectively increased.

FIGS. 3 and 5are cross-sectional views schematically illustrating a method of manufacturing a ferroelectric memory device according to an embodiment of the present disclosure. In an embodiment, the method described herein may be used to manufacture the ferroelectric memory device1described above with reference toFIG. 2.

Referring toFIG. 3, a substrate101may be provided. The substrate101may be a silicon (Si) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, a germanium (Ge) substrate, or a silicon germanium (SiGe) substrate, for example. In an embodiment, the substrate101may be doped to have conductivity. As an example, the substrate101may be doped with an n-type or p-type dopant. As another example, the substrate101may include a well region doped with an n-type or p-type dopant therein.

A first ferroelectric amorphous material layer120, a ferroelectric induction layer130, a second ferroelectric amorphous material layer140, and a gate electrode layer150may be sequentially formed on the substrate101.

The first ferroelectric amorphous material layer120may include, for example, hafnium oxide, zirconium oxide, hafnium zirconium oxide, or a combination of two or more thereof. The first ferroelectric amorphous material layer120may be formed in an amorphous state. The first ferroelectric amorphous material layer120may not have sufficient ferroelectric property to store remanent polarization in an amorphous state. The first ferroelectric amorphous material layer120may be formed by a chemical vapor deposition method, a sputtering method, or an atomic layer deposition method, for example. The first ferroelectric amorphous material layer120may have, for example, a thickness of about 5 nm to about 15 nm.

The ferroelectric induction layer130may be formed in a crystalline state. The ferroelectric induction layer130may include an insulator. The ferroelectric induction layer130may include, for example, magnesium oxide, however the ferroelectric induction layer130is not necessarily limited to having magnesium oxide. The ferroelectric induction layer130may include a material having a lattice constant different from those of crystalline hafnium oxide, crystalline zirconium oxide, or crystalline hafnium zirconium oxide. The ferroelectric induction layer130may be formed, for example, by a chemical vapor deposition method, a sputtering method, or an atomic layer deposition method. The ferroelectric induction layer130may have, for example, a thickness of about 1 nm to about 5 nm.

The second ferroelectric amorphous material layer140may include, for example, hafnium oxide, zirconium oxide, hafnium zirconium oxide, or a combination of two or more thereof. The second ferroelectric amorphous material layer140may be formed in an amorphous state. The second ferroelectric amorphous material layer140may not have a sufficient ferroelectric property to store remanent polarization in an amorphous state. The second ferroelectric amorphous material layer140may be formed, for example, by a chemical vapor deposition method, a sputtering method, or an atomic layer deposition method. The second ferroelectric amorphous material layer140may have, for example, a thickness of about 5 nm to about 15 nm.

In an embodiment, the first and second ferroelectric amorphous material layers120and140may be formed of the same material. As an example, each of the first and second ferroelectric amorphous material layers120and140may be a hafnium oxide layer, a zirconium oxide layer, or a hafnium zirconium oxide layer. In another embodiment, the first and second ferroelectric amorphous material layers120and140may be formed of different materials. As an example, when the first ferroelectric amorphous material layer120is a hafnium oxide layer, the second ferroelectric amorphous material layer140may be a zirconium oxide layer. As another example, when the first ferroelectric amorphous material layer120is a zirconium oxide layer, the second ferroelectric amorphous material layer140may be a hafnium oxide layer.

The gate electrode layer150may include a conductor. The gate electrode layer150may include, for example, tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more thereof. In an embodiment, the gate electrode150may include a material having a lattice constant different from those of crystalline hafnium oxide, crystalline zirconium oxide, or crystalline hafnium zirconium oxide.

Referring toFIG. 4, crystallization heat treatment may be performed with respect to the first and second ferroelectric amorphous material layers120and140. In an embodiment, the crystallization heat treatment may be performed at a process temperature of 500° C. to 1000° C. At this time, the first and second ferroelectric amorphous material layers120and140may be converted into first and second ferroelectric layers125and145having tetragonal crystal structure having ferroelectricity due to stress applied from the ferroelectric induction layer130during the crystallization process. In some embodiments, when the gate electrode layer150has a different lattice constant from the second ferroelectric layer145, the gate electrode layer150may apply stress to the second ferroelectric amorphous layer140during the crystalline process.

Referring toFIG. 5, the first ferroelectric layer125, the ferroelectric induction layer130, the second ferroelectric layer145, and the gate electrode layer150may be patterned to form a gate structure1a. Then, regions of the substrate101positioned at both ends of the gate structure1amay be doped with a dopant to form a source region112and a drain region114. Through the above-described process, it is possible to manufacture a ferroelectric memory device according to an embodiment of the present disclosure.

FIG. 6is a circuit diagram schematically illustrating a ferroelectric memory device2according to an embodiment of the present disclosure. The technical idea of the present disclosure may be used in a NAND type device corresponding to the circuit diagram ofFIG. 6.

Referring toFIG. 6, the ferroelectric memory device2may include a string2ahaving an array of a plurality of transistors whose channels are connected in series. An end of the string2amay be connected to a source line SL and the other end of the string2amay be connected to a bit line BL. The string2amay have first to sixth memory cell transistors MC1, MC2, MC3, MC4, MC5and MC6connected to each other in series. In addition, the string2amay include a lower selection transistor LST disposed between the first memory cell transistor MC1and the source line SL, and an upper selection transistor UST disposed between the sixth memory cell transistor MC6and the bit line BL. InFIG. 6, for convenience of description, the string2ais illustrated to have six memory cell transistors, but the present disclosure is not necessarily limited thereto. The number of the memory cell transistors constituting the string2ais not limited. In addition, inFIG. 6, the string2ais illustrated to have one lower selection transistor LST and one upper selection transistor UST, but the present disclosure is not necessarily limited thereto. The lower selection transistor LST may include a plurality of lower selection transistors whose channels are connected in series to each other. Likewise, the upper selection transistor UST may include a plurality of upper selection transistors whose channels are connected in series to each other.

The first to sixth memory cell transistors MC1, MC2, MC3, MC4, MC5and MC6may have first to sixth channel layers ch1, ch2, ch3, ch4, ch5and ch6respectively between the source line SL and the bit line BL. The first to sixth memory cell transistors MC1, MC2, MC3, MC4, MC5and MC6may have ferroelectric gate dielectric layers adjacent to the first to sixth channel layers ch1, ch2, ch3, ch4, ch5and ch6, respectively. Gate electrode layers of the first to sixth memory cell transistors MC1, MC2, MC3, MC4, MC5and MC6may each be connected to different first to sixth word lines WL1, WL2, WL3, WL4, WL5and WL6. Each of the upper selection transistor UST and the lower selection transistor LST may be turned on or turned off, respectively, to apply a voltage between the bit line BL and the source line SL to the first to sixth channel layers ch1, ch2, ch3, ch4, ch5and ch6, or to remove the applied voltage from the first to sixth channel layers ch1, ch2, ch3, ch4, ch5and ch6. The gate electrode layers of the upper selection transistor UST and lower selection transistor LST may be connected to an upper selection line USL and a lower selection line LSL, respectively.

In an embodiment, a write operation on at least one of the first to sixth memory cell transistors MC1, MC2, MC3, MC4, MC5and MC6may be performed as follows. When the upper selection transistor UST and the lower selection transistor LST are turned on, a predetermined write voltage may be applied to gate electrodes of corresponding memory cell transistors MC1, MC2, MC3, MC4, MC5and MC6through the respective first to sixth word lines WL1, WL2, WL3, WL4, WL5and WL6. In the ferroelectric gate dielectric layers of the memory cell transistors MC1, MC2, MC3, MC4, MC5and MC6to which the write voltage is applied, predetermined electrical polarization may be recorded in a nonvolatile manner. The electrical signals recorded in the ferroelectric gate dielectric layers may vary depending on the polarization orientation and the magnitude of the polarization. Accordingly, the first to sixth the memory cell transistors MC1, MC2, MC3, MC4, MC5and MC6can perform an operation related to nonvolatile memory.

Likewise, a read operation on the string2aincluding the first to sixth the memory cell transistors MC1, MC2, MC3, MC4, MC5and MC6may be performed as follows. When the upper selection transistor UST and the lower selection transistor LST are turned on, a predetermined read voltage may be applied to the gate electrodes of the corresponding memory cell transistors MC1, MC2, MC3, MC4, MC5and MC6through the respective first to sixth word lines WL1, WL2, WL3, WL4, WL5and WL6.

At this time, the polarization recorded in the ferroelectric gate dielectric layer of each of the memory cell transistors MC1, MC2, MC3, MC4, MC5and MC6can control the magnitude of a current flowing through the channel of the corresponding memory cell transistors MC1, MC2, MC3, MC4, MC5and MC6. As a result, the polarization recorded in the ferroelectric gate dielectric layer of each of the memory cell transistors MC1, MC2, MC3, MC4, MC5and MC6can determine the electrical resistance of the string2athrough the resistances in first to sixth channel layers ch1, ch2, ch3, ch4, ch5and ch6. By determining the difference in the electrical resistances, it is possible to determine the electrical signal stored in the string2a.

FIG. 7Ais a cross-sectional view schematically illustrating a ferroelectric memory device3according to an embodiment of the present disclosure.FIG. 7Bis an enlarged view of the region ‘A’ ofFIG. 7A. The ferroelectric memory device3ofFIGS. 7A and 7Bmay be an exemplary implementation of the ferroelectric memory device2having a circuit diagram ofFIG. 6.

Referring toFIG. 7A, the ferroelectric memory device3may include a substrate201, and a gate stack500aon the substrate201. The substrate201may be substantially the same as the substrate101of the ferroelectric memory device1described above with reference toFIG. 2. The gate stack500amay include first to eighth gate structures520a,520b,520c,520d,520e,520f,520gand520hand first to eighth interlayer insulation layers220a,220b,220c,220d,220e,220f,220gand220h, which are alternately stacked in a direction perpendicular to the substrate201. In an embodiment, the eighth interlayer insulation layer220hmay be formed to be thicker than the first to seventh interlayer insulation layers220a,220b,220c,220d,220e,220fand220g. In an embodiment, the first to seventh interlayer insulation layers220a,220b,220c,220d,220e,220fand220gmay be formed to have the same thickness. Likewise, the first to eighth gate structures520a,520b,520c,520d,520e,520f,520gand520hmay be formed to have the same thickness.

The first to eighth gate structures520a,520b,520c,520d,520e,520f,520gand520hmay be electrically connected to the lower selection line (not shown), the word line (not shown), and the upper selection line (not shown) of the ferroelectric memory device2described above with reference toFIG. 6. The first to eighth gate structures520a,520b,520c,520d,520e,520f,520gand520hare briefly illustrated inFIG. 7Afor convenience of illustration and will be described in detail with reference toFIG. 7Bbelow.

The ferroelectric memory device3may include a trench10having a first portion10aand a second portion10b. The first portion10aof the trench10may be formed on the substrate201to penetrate the gate stack500a, and the second portion10bmay have a shape discontinuously extending below the first portion10aand may be formed or defined in the substrate201. The first portion10aof the trench10may expose side surfaces of the first to eighth gate structures520a,520b,520c,520d,520e,520f,520gand520hand side surfaces of the first to eighth interlayer insulation layers220a,220b,220c,220d,220e,220f,220gand220h.

In addition, the ferroelectric memory device3may include a source contact layer203disposed between the substrate201and the gate stack500a. The source contact layer203may separate the first portion10aand the second portion10bof the trench10in a direction perpendicular to the substrate201, that is, the z-direction. A source insulation layer205may be disposed between the source contact layer203and the first gate structure520a. The source insulation layer205may electrically insulate the source contact layer203and the first gate structure520a. The source insulation layer205may include insulative oxide, insulative nitride, insulative oxynitride, etc., for example.

The ferroelectric memory device3may include a first gate dielectric layer410C disposed along an inner surface of the trench10. The first gate dielectric layer410C may extend in a direction perpendicular to the substrate201, that is, the z-direction. Specifically, the first gate dielectric layer410C may be disposed to cover the first to eighth gate structures520a,520b,520c,520d,520e,520f,520gand520hand the first to eighth interlayer insulation layers220a,220b,220c,220d,220e,220f,220gand220halong an inner surface of the first portion10aof the trench10. In addition, the first gate dielectric layer410C may be disposed to cover the substrate201along an inner surface of the second portion10bof the trench10. That is, the first gate dielectric layer410C may cover portions of the substrate201along a sidewall and a bottom of the trench10under the source contact layer203.

Referring toFIG. 7A, the first gate dielectric layer410C may include ferroelectric portions412and non-ferroelectric portions414. The ferroelectric portions412may be disposed to contact the first to eighth gate structures520a,520b,520c,520d,520e,520f,520gand520h. The non-ferroelectric portions414may be disposed to contact the first to eighth interlayer insulation layers220a,220b,220c,220d,220e,220f,220gand220h.

The ferroelectric portions412and the non-ferroelectric portions414may be formed of the same material, but may have different crystal structures. As an example, each of the ferroelectric portions412may have a crystal structure with a ferroelectric property, while each of the non-ferroelectric portions414may have a crystal structure with a paraelectric property. As an example, the ferroelectric portions412may each have a crystal structure of an orthorhombic system, and the non-ferroelectric portions414may each have a crystal structure of a tetragonal system or a monoclinic system. Each of the ferroelectric portions412and each of the non-ferroelectric portions414may have a thickness of about 5 nm to about 15 nm in the lateral direction (i.e., x-direction).

The first gate dielectric layer410C may include hafnium oxide, zirconium oxide, hafnium zirconium oxide, or a combination of two or more thereof, for example. The first gate dielectric layer410C may include a dopant. The dopant may include silicon (Si), zirconium (Zr), yttrium (Y), aluminum (Al), gadolinium (Ga), strontium (Sr), lanthanum (La), or a combination of two or more thereof, for example.

Referring toFIG. 7A, a channel layer420may be disposed on the first gate dielectric layer410C and the source contact layer203. The channel layer420may be disposed to cover the first gate dielectric layer410C. In addition, the channel layer420may be disposed to contact side surfaces of the source contact layer203. Accordingly, the channel layer420can be electrically connected to the source contact layer203. The channel layer420may include a semiconductor material, for example. The semiconductor material may include silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), or a combination of two or more thereof. In an embodiment, the semiconductor material may be doped into n-type or p-type. The channel layer420may include conductive metal oxide, as another example. The conductive metal oxide may include indium gallium zinc oxide (IGZO), or indium tin oxide (ITO), etc., for example.

Referring toFIG. 7A, a filling material layer430may be disposed to fill the trench10, in open areas between the channel layers420common to first to seventh gate structures520a,520b,520c,520d,520e,520f, and520g. As an example, the filling material layer430may include oxide, nitride, or oxynitride.

A channel contact layer470may be disposed on the filling material layer430common to eighth interlayer insulation layer220h. The channel contact layer470may be electrically connected to a bit line (not shown) so that an end of the channel layer420can be electrically connected to the bit line. Meanwhile, as described above, the other end of the channel layer420may be connected to the source contact layer203, and may be electrically connected to a source line (not shown) through the source contact layer203.

Hereinafter, the first to eighth gate structures520a,520b,520c,520d,520e,520f,520gand520hwill be described with reference toFIG. 7B. Each of the first to eighth gate structures520a,520b,520c,520d,520e,520f,520gand520hmay include a ferroelectric induction layer501, a ferroelectric second gate dielectric layer512and a gate electrode layer503. In addition, each of the first to eighth gate structures520a,520b,520c,520d,520e,520f,520gand520hmay further include a conductive layer504in contact with the gate electrode layer503.

The ferroelectric induction layer501may be disposed to contact the first to eighth interlayer insulation layers220a,220b,220c,220d,220e,220f,220gand220hand the ferroelectric portion412of the first gate dielectric layer410C. The ferroelectric induction layer501may have a non-ferroelectric property. As an example, the ferroelectric induction layer501may have a paraelectric property. The ferroelectric induction layer501may have a crystalline phase. In addition, the ferroelectric induction layer501may include an insulator. In an embodiment, the ferroelectric induction layer501may include metal oxide. As an example, the ferroelectric induction layer501may include magnesium oxide.

In an embodiment, the ferroelectric induction layer501may have a thickness of about 1 nm to about 5 nm. Between the channel layer420and the gate electrode layer503, the ferroelectric induction layer501may function as a capacitor layer connected in series to the first gate dielectric layer410C and the ferroelectric second gate dielectric layer512. As the thickness of the ferroelectric induction layer501increases, the total capacitance of the electrical circuit between the channel layer420and the gate electrode layer503may decrease. Accordingly, the thickness of the ferroelectric induction layer501may be maintained at one nanometer (1 nm) to five nanometers (5 nm) in order to prevent excessive degradation of the total capacitance.

The ferroelectric second gate dielectric layer512may be disposed on the ferroelectric induction layer501. Specifically, the second gate dielectric layer512may contact the ferroelectric induction layer501. As an example, a top surface512t, a bottom surface512band one side surface512m1of the second gate dielectric layer512may contact the ferroelectric induction layer501.

The second gate dielectric layer512may have a crystalline phase having a ferroelectric property. As an example, the second gate dielectric layer512may have a crystal structure of an orthorhombic system. The second gate dielectric layer512may have a thickness of about 5 nm to about 15 nm in a direction perpendicular to a contact surface512tor512bcommon to the ferroelectric induction layer501. The second gate dielectric layer512may include hafnium oxide, zirconium oxide, hafnium zirconium oxide or a combination of two or more thereof, for example. The second gate dielectric layer512may include a dopant. The dopant may include silicon (Si), zirconium (Zr), yttrium (Y), aluminum (Al), gadolinium (Ga), strontium (Sr), lanthanum (La), or a combination of two or more thereof, for example.

In an embodiment, the first gate dielectric layer410C and the second gate dielectric layer512may be formed of the same material. In another embodiment, the first gate dielectric layer410C and the second gate dielectric layer512may be formed of different materials. As an example, when the first gate dielectric layer410C is a hafnium oxide layer, the second gate dielectric layer512may be a zirconium oxide layer. As another example, when the first gate dielectric layer410C is a zirconium oxide layer, the second gate dielectric layer512may be a hafnium oxide layer.

In an embodiment, the ferroelectric induction layer501may have a lattice constant different from those of the first gate dielectric layer410C and second gate dielectric layer512. The lattice constant difference between the ferroelectric induction layer501and the first gate dielectric layer410C and the lattice constant difference between the ferroelectric induction layer501and the second gate dielectric layer512may result in applied stress from the interfaces with the ferroelectric induction layer501into the first and second gate dielectric layers410C and512, during a crystallization process to be described with reference toFIGS. 13A and 13Bfor crystallizing the first and second ferroelectric amorphous material layers410and502into the first and second gate dielectric layers410C and512. The stress may cause a lattice strain inside the first and second gate dielectric layers410C and512when the first and second ferroelectric amorphous material layers410and502are crystallized into the first and second gate dielectric layers410C and512. The lattice strain may form an electric field due to a flexoelectric effect inside the first and second gate dielectric layers410C and512. The electric field may induce the first and second gate dielectric layers410C and512to have tetragonal crystal structures having ferroelectric properties. As a result, the first and second gate dielectric layers410C and512have more stable ferroelectric properties.

The gate electrode layer503may be disposed on a side surface512m2of the second gate dielectric layer512. The gate electrode layer503may contact the second gate dielectric layer512. The gate electrode layer503may include a conductor. In an embodiment, the gate electrode layer503may have a lattice constant different from that of the second gate dielectric layer512. The gate electrode layer503may function as a ferroelectric induction layer with respect to the second gate dielectric layer512. That is, in the above-described crystallization process for the first and second ferroelectric amorphous material layers410and502, in the same process, the gate electrode layer503may apply stress to the second ferroelectric amorphous material layer502. The stress may cause a lattice strain inside the second gate dielectric layer512when the second ferroelectric amorphous material layer502is crystallized to the second gate dielectric layer512. The lattice strain may form an electric field due to a flexoelectric effect inside the second gate dielectric layer512, and the electric field may induce the second gate dielectric layer512to have a tetragonal crystal structure having a ferroelectric property. The gate electrode layer503may have a thickness of about 5 nm to about 15 nm in the vertical direction, for example. In some other embodiments, the gate electrode layer503may not function as a ferroelectric induction layer with respect to the second gate dielectric layer512. In such embodiments, the second gate dielectric layer512may be induced to have a tetragonal crystal structure only by the ferroelectric induction layer501.

The gate electrode layer503may include tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more thereof. When the gate electrode layer503functions as a ferroelectric induction layer with respect to the second gate dielectric layer512, the gate electrode layer503may, for example, include titanium nitride.

Referring toFIG. 7B, a conductive layer504may be disposed on the gate electrode layer503. The conductive layer504may include a conductive material having a lower resistivity than the gate electrode layer503. The conductive layer504may be disposed to contact the gate electrode layer503and the ferroelectric induction layer501. In some other embodiments, the conductive layer504may be omitted by increasing a thickness of the gate electrode layer503in the lateral direction (i.e., the x-direction).

As described above, a ferroelectric memory device according to an embodiment of the present disclosure may have a ferroelectric first gate dielectric layer, a ferroelectric induction layer and a ferroelectric second gate dielectric layer that are sequentially disposed between a channel layer and a gate electrode layer. The first gate dielectric layer, the ferroelectric induction layer and the second gate dielectric layer may constitute a gate dielectric layer structure of the ferroelectric memory device. The first and second gate dielectric layers may operate as memory functional layers that store remanent polarization.

Meanwhile, the ferroelectric induction layer having a non-ferroelectric property may be interposed between the first and second gate dielectric layers to stabilize the ferroelectric property of the first and second gate dielectric layers. In other words, the ferroelectric induction layer can be used to substantially increase the thickness of the ferroelectric gate dielectric layer in the ferroelectric memory device. Accordingly, the memory window of the ferroelectric memory device can be effectively increased.

FIGS. 8 to 11,FIGS. 12A to 16A, andFIGS. 12B to 16Bare cross-sectional views schematically illustrating a method of manufacturing a ferroelectric memory device according to an embodiment of the present disclosure.FIGS. 12B to 16Bare enlarged views of the regions ‘A’ ofFIGS. 12A to 16A, respectively.FIGS. 12B to 16Billustrate all the components not shown for convenience inFIGS. 12A to 16A, respectively.

Referring toFIG. 8, a substrate201may be prepared. In an embodiment, the substrate201may be a semiconductor substrate. The substrate201may be a silicon (Si) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, a germanium (Ge) substrate, or a silicon germanium (SiGe) substrate, for example. In an embodiment, the substrate201may be doped to have conductivity. As an example, the substrate201may be doped with an n-type or p-type dopant. As another example, the substrate201may include a well region doped with an n-type or p-type dopant therein.

Then, a sacrificial layer202and a source insulation layer205may be formed on the substrate201. The sacrificial layer202may include a material having etching selectivity with respect to the substrate201and the source insulation layer205. The sacrificial layer202may be removed in a process with reference toFIGS. 15A, 15B, 16A and 16Bto be described later, and a source contact layer203may be formed in a space where the sacrificial layer202has been removed. That is, the sacrificial layer202may provide a space in which the source contact layer203is to be formed. The sacrificial layer202may include, for example, oxide, nitride or oxynitride. The source insulation layer205may include, for example, oxide, nitride or oxynitride. The sacrificial layer202and the source insulation layer205may each be formed by using a chemical vapor deposition method or an atomic layer deposition method, for example.

Next, a stack structure200amay be formed on the source insulation layer205. The stack structure200amay include interlayer sacrificial layers210a,210b,210c,210d,210e,210f,210gand210hand interlayer insulation layers220a,220b,220c,220d,220e,220f,220gand220h, which are alternately stacked with each other. As illustrated, a lowermost interlayer sacrificial layer210amay contact the source insulation layer205. An uppermost interlayer insulation layer220hmay have a thickness greater than those of the remaining interlayer insulation layers220a,220b,220c,220d,220e,220fand220g. The interlayer sacrificial layers210a,210b,210c,210d,210e,210f,210gand210hand the interlayer insulation layers220a,220b,220c,220d,220e,220f,220gand220hmay be formed by using a chemical vapor deposition method or an atomic layer deposition method, for example.

Referring toFIG. 9, a trench10′ may be formed to penetrate the stack structure200a, the source insulation layer205and the sacrificial layer202on the substrate201. The trench10′ may expose the substrate201. As a result of etching, side surfaces of the stack structure200a, the source insulation layer205and the sacrificial layer202may be exposed to a side surface of the trench10′. The trench10′ may be formed by an anisotropic etching method, for example.

Referring toFIG. 10, a first ferroelectric amorphous material layer410may be formed on an inner surface of the trench10′. The first ferroelectric amorphous material layer410may include, for example, hafnium oxide, zirconium oxide, hafnium zirconium oxide, or a combination of two or more thereof. The first ferroelectric amorphous material layer410may include a dopant. The dopant may include silicon (Si), zirconium (Zr), yttrium (Y), aluminum (Al), gadolinium (Ga), strontium (Sr), lanthanum (La), or a combination of two or more thereof, for example. The first ferroelectric amorphous material layer410may have a thickness of about 5 nm to about 15 nm, for example. The first ferroelectric amorphous material layer410may be formed by using a chemical vapor deposition method or an atomic layer deposition method, for example.

A channel layer420may be formed on the first ferroelectric amorphous material layer410. The channel layer420may include, for example, a semiconductor material. The semiconductor material may include silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), or a combination of two or more thereof. In an embodiment, the semiconductor material may be doped into n-type or p-type. The channel layer420may include conductive metal oxide, for another example. The conductive metal oxide may include indium gallium zinc oxide (IGZO), or indium tin oxide (ITO), etc., for example. The channel layer420may be formed by using a chemical vapor deposition method or an atomic layer deposition method, for example.

Then, the trench10′ in which the first ferroelectric amorphous material layer410and the channel layer420are formed may be filled with an insulation material to form a filling insulation layer430. The insulation material may include, for example, oxide, nitride or oxynitride.

A planarization process may be performed with respect to portions of the first ferroelectric amorphous material layer410, the channel layer420and the filling insulation layer430, which are formed outside the trench10′. As a result, as illustrated inFIG. 10, top surfaces of the ferroelectric amorphous material layer410, the channel layer420and the filling insulation layer430may be positioned on the same plane as the top surface of the uppermost interlayer insulation layer220h. For instance, the planarization process may be performed by a chemical mechanical polishing method.

Referring toFIG. 11, the interlayer sacrificial layers210a,210b,210c,210d,210e,210f,210gand210hof the stack structure200amay be selectively removed to form recesses20that selectively expose the interlayer insulation layers220a,220b,220c,220d,220e,220f,220gand220hand the first ferroelectric amorphous material layer410. In an embodiment, the interlayer sacrificial layers210a,210b,210c,210d,210e,210f,210gand210hmay be selectively removed by forming a separate trench (not shown) penetrating the stack structure200aand providing an etchant to the trench to selectively etch the interlayer sacrificial layers210a,210b,210c,210d,210e,210f,210gand210h.

Referring toFIGS. 12A and 12B, first to eighth preliminary gate structures510a,510b,510c,510d,510e,510f,510gand510may be formed inside the recesses20according to the following process. First, a ferroelectric induction layer501may be formed on the ferroelectric amorphous material layer410and the interlayer insulation layers220a,220b,220c,220d,220e,220f,220gand220hinside the recesses20. The ferroelectric induction layer501may have an amorphous phase. In addition, the ferroelectric induction layer501may have a non-ferroelectric property, for example, a paraelectric property. The ferroelectric induction layer501may include an insulator. For instance, the ferroelectric induction layer501may include insulative metal oxide. For instance, the ferroelectric induction layer501may include magnesium oxide. In an embodiment, the ferroelectric induction layer501may have a thickness of about 1 nm to about 5 nm. The ferroelectric induction layer501may be formed by using a chemical vapor deposition method or an atomic layer deposition method, for example.

Then, a second ferroelectric amorphous material layer502may be formed on the ferroelectric induction layer501inside the recesses20. Here, a top surface502t, a bottom surface502band a side surface502m1of the second ferroelectric amorphous material layer502may contact the ferroelectric induction layer501. The second ferroelectric amorphous material layer502may include hafnium oxide, zirconium oxide, hafnium zirconium oxide or a combination of two or more thereof, for example. The second ferroelectric amorphous material layer502may include a dopant. The dopant may include, for example, silicon (Si), zirconium (Zr), yttrium (Y), aluminum (Al), gadolinium (Gd), strontium (Sr), lanthanum (La), or a combination of two or more thereof. The second ferroelectric amorphous material layer502may be formed by using a chemical vapor deposition method or an atomic layer deposition method, for example. In an embodiment, the lattice constant of crystalline dielectric layers after each of the first and second ferroelectric amorphous material layers410and502are crystallized may differ from the lattice constant of the ferroelectric induction layer501. Accordingly, the ferroelectric induction layer501may apply stress to the first and second ferroelectric amorphous material layers410and502during a crystallization process ofFIGS. 13A and 13Bto be described later.

A gate electrode layer503may be formed on a side surface502m2of the second ferroelectric amorphous material layer502. The gate electrode layer503may include a conductor. In an embodiment, the lattice constant of the gate electrode layer503may differ from the lattice constant of a crystalline dielectric layer after the second ferroelectric amorphous material layer502is crystallized. Accordingly, the gate electrode layer503may function as a ferroelectric induction layer with respect to the second ferroelectric amorphous material layer502during the crystallization process ofFIGS. 13A and 13Bto be described later. The gate electrode layer503may have a thickness of about 5 nm to about 15 nm in the vertical direction. The gate electrode layer503may include, for example, tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more thereof. When the gate electrode503functions as a ferroelectric induction layer with respect to the second ferroelectric amorphous material layer502, the gate electrode layer503may include, for example, titanium nitride. The gate electrode layer503may be formed by using a chemical vapor deposition method or an atomic layer deposition method, for example.

A conductive layer504may be formed on the gate electrode layer503. The conductive layer504may include a conductive material having a lower resistivity than the gate electrode layer503. The conductive layer504may be formed to contact the gate electrode layer503and the ferroelectric induction layer501. The conductive layer504may be formed by using a chemical vapor deposition method or an atomic layer deposition method, for example. In some other embodiments, the conductive layer504may be omitted by increasing the thickness of the gate electrode layer503in the lateral direction (i.e., the x-direction). The first to eighth preliminary gate structures510a,510b,510c,510d,510e,510f,510gand510hillustrated inFIGS. 12A and 12Bcan be formed through the above-described process.

Referring toFIGS. 13A and 13B, crystallization heat treatment may be performed with respect to the first and second ferroelectric amorphous material layers410and502, using the ferroelectric induction layer501, to form a first to eighth gate structures520a,520b,520c,520d,520e,520f,520gand520h. The crystallization heat treatment may be performed at a process temperature of 500° C. to 1000° C., for example. In an embodiment, the crystallization heat treatment process may be performed by converting portions of the first and second ferroelectric amorphous material layers410and502in contact with the ferroelectric induction layer501into crystalline ferroelectric layers having ferroelectric properties. Accordingly, portions of the first ferroelectric amorphous material layer410in contact with the ferroelectric induction layer501may be converted into ferroelectric portions412of a first gate dielectric layer410C. In addition, portions of the first ferroelectric amorphous material layer410in contact with the first to eighth interlayer insulation layers220a,220b,220c,220d,220e,220f,220gand220hmay be converted into non-ferroelectric portions414of the first gate dielectric layer410C.

Meanwhile, as the second ferroelectric amorphous material layer502is disposed such that the top surface502t, the side surface502m1and the bottom surface502bthereof are surrounded by the ferroelectric induction layer501, as illustrated inFIG. 12B, the entire second ferroelectric amorphous material layer502may be converted into the ferroelectric second gate dielectric layer512during the crystallization heat treatment. In an embodiment, as described above, the gate electrode layer503may additionally function as a ferroelectric induction layer for the second ferroelectric amorphous material layer502.

In an embodiment, when the crystallization heat treatment is performed, the ferroelectric induction layer501may induce the first and second ferroelectric amorphous material layers410and502to transform into layers with a predetermined ferroelectric crystal structure. For instance, the ferroelectric portions412of the first gate dielectric layer410C and the second gate dielectric layer512may each have a crystal structure of an orthorhombic system, and the non-ferroelectric portions414of the first gate dielectric layer410C may each have a crystal structure of a tetragonal system or a monoclinic system.

Referring toFIGS. 14A and 14B, an upper portion of the filling insulation layer430may be selectively etched to form a recess. Then, the recess may be filled with a conductive material to form a channel contact layer470. The conductive material may include, for example, a semiconductor material doped into n-type or p-type. As a specific example, the conductive material may be n-type doped silicon. The channel contact layer470may be formed to contact the channel layer420in the lateral direction (i.e., the x-direction).

Referring toFIGS. 15A and 15B, a trench (not shown) may be formed to penetrate the first to eighth gate structures520a,520b,520c,520d,520e,520f,520gand520h, the first to eighth interlayer insulation layers220a,220b,220c,220d,220e,220f,220gand220h, and the source insulation layer205to expose the sacrificial layer202. Then, the sacrificial layer202may be etched and removed by providing an etchant to the trench. After removing the sacrificial layer202, the non-ferroelectric portions414of the first gate dielectric layer410C exposed in the lateral direction may be etched to form a side recess spaces30exposing the channel layer420. As the side recess spaces30are formed, the trench10′ may be converted into a trench10including a first portion10aand a second portion10bthat are separated from each other.

Referring toFIGS. 16A and 16B, the side recess space30may be filled with a conductive material to form a source contact layer203. The conductive material may include, for example, semiconductor doped into n-type or p-type. As a specific example, the conductive material may be n-type doped silicon. The source contact layer203may be formed to contact a portion of the channel layer420.

Through the above-described process, a ferroelectric memory device according to an embodiment of the present disclosure can be manufactured. As described above, crystallization heat treatment may be performed with respect to the first and second ferroelectric amorphous material layers while a ferroelectric induction layer including an insulator contacts the first and second ferroelectric amorphous material layers, respectively. Accordingly, a crystalline gate dielectric layer having a ferroelectric property can be effectively transformed from the first and second ferroelectric amorphous material layers.

FIG. 17Ais a cross-sectional view schematically illustrating a ferroelectric memory device4according to an embodiment of the present disclosure andFIG. 17Bis an enlarged view of the region ‘B’ ofFIG. 17A.FIG. 17Billustrates components not shown for convenience inFIG. 17A. The ferroelectric memory device4can be distinguished in the configuration of a first gate dielectric layer413C, a ferroelectric induction layer601, a second gate dielectric layer612and a gate electrode layer603in comparison with the ferroelectric memory device3described above with reference toFIGS. 7A and 7B.

Referring toFIG. 17A, the ferroelectric memory device4may include a substrate201, and a gate stack600aon the substrate201. The gate stack600amay include first to eighth gate structures620a,620b,620c,620d,620e,620f,620gand620hand first to eighth interlayer insulation layers220a,220b,220c,220d,220e,220f,220gand220h, which are alternately stacked in a direction perpendicular to the substrate201(the z-direction).

The first to eighth gate structures620a,620b,620c,620d,620e,620f,620gand620hmay be electrically connected to a lower selection line (not shown), a word line (not shown) and an upper selection line (not shown) of the ferroelectric memory device2described above with reference toFIG. 6. The first to eighth gate structures620a,620b,620c,620d,620e,620f,620gand620hwill be described in detail usingFIG. 17Bbelow.

The ferroelectric memory device4may include a trench40having a first portion40aand a second portion40b. The first portion40aof the trench40may be formed to penetrate the gate stack600aon the substrate201, and the second portion40bmay have a shape discontinuously extending below the first portion40aand may be formed in the substrate201. Specifically, the first portion40aof the trench40may expose side surfaces of the first to eighth gate structures620a,620b,620c,620d,620e,620f,620gand620hand side surfaces of the first to eighth interlayer insulation layers220a,220b,220c,220d,220e,220f,220gand220h.

The ferroelectric memory device4may include a first gate dielectric layer413C disposed along an inner surface of the trench40. The first gate dielectric layer413C may be disposed to cover the first to eighth gate structures620a,620b,620c,620d,620e,620f,620gand620hand first to eighth interlayer insulation layers220a,220b,220c,220d,220e,220f,220gand220halong the inner surface of the first portion40aof the trench40. In addition, the first gate dielectric layer413C may be disposed to cover the substrate201along an inner surface of the second portion40bof the trench40.

The first gate dielectric layer413C may include, for example, hafnium oxide, zirconium oxide, hafnium zirconium oxide, or a combination of two or more thereof. The first gate dielectric layer413C may have a crystalline phase as a whole. As an example, the first gate dielectric layer413C may have the same tetragonal crystal structure as a whole. The first gate dielectric layer413C may have a thickness of about 5 nm to about 15 nm in a direction perpendicular to an inner surface of the trench40.

The ferroelectric induction layer601may be disposed on the first gate dielectric layer413C in the trench40in first portion40aand second portion40b. The ferroelectric induction layer601may have a non-ferroelectric property. As an example, the ferroelectric induction layer601may have a paraelectric property. The ferroelectric induction layer601may have a crystalline phase. In addition, the ferroelectric induction layer601may include an insulator. In an embodiment, the ferroelectric induction layer601may include insulative metal oxide. As an example, the ferroelectric induction layer601may include magnesium oxide. In an embodiment, the ferroelectric induction layer601may have a thickness of about 1 nm to about 5 nm in a direction perpendicular to an inner surface of the trench40. The ferroelectric induction layer601does not cover a side surface of source contact layer203.

The second gate dielectric layer612may be disposed on the ferroelectric induction layer601in the trench40. The second gate dielectric layer612may include, for example, hafnium oxide, zirconium oxide, hafnium zirconium oxide, or a combination of two or more thereof. The second gate dielectric layer612may have a crystalline phase. As an example, the second gate dielectric layer612may have a crystal structure of a tetragonal system. The second gate dielectric layer612may have a thickness of about 5 nm to about 15 nm in a direction perpendicular to an inner surface of the trench40. The second gate dielectric layer612does not cover a side surface of source contact layer203.

The channel layer420may be disposed on the second gate dielectric layer612. The channel layer420may be disposed to cover the second gate dielectric layer612. In addition, the channel layer420may be disposed to contact a side surface of the source contact layer203. Accordingly, the channel layer420may be electrically connected to the source contact layer203. Meanwhile, a filling insulation layer430may be used to fill the trench40. A channel contact layer470may be disposed on the filling insulation layer430.

Referring toFIG. 17B, the first to eighth gate structures620a,620b,620c,620d,620e,620f,620gand620hmay each include a gate electrode layer603and a conductive layer604. The gate electrode layer603may contact the first to eighth interlayer insulation layers220a,220b,220c,220d,220e,220f,220gand220hand the first gate dielectric layer413C. The gate electrode layer603may include, for example, tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more thereof.

In an embodiment, the gate electrode layer603may have a lattice constant different from that of the first gate dielectric layer413C. Consequently, the gate electrode layer603may function as a ferroelectric induction layer during crystallization of the first gate dielectric layer413C in a manufacturing process to be described. The conductive layer604may include a conductive material having a lower resistivity than the gate electrode layer603. The conductive layer604may be disposed on the gate electrode layer603.

In the above-described embodiment, the first gate dielectric layer413C, the ferroelectric induction layer601and the second gate dielectric layer612may be sequentially disposed on the inner surface of the trench40. The ferroelectric induction layer601may induce stress into first and second gate dielectric layers413C and612at the same time in a crystallization process. Accordingly, each of the first and second gate dielectric layers413C and612can have a stable a ferroelectric property. In some embodiments, the gate electrode layer603may function as a ferroelectric induction layer with respect to the first gate dielectric layer413C, thereby also improving the stability of a ferroelectric property of the first gate dielectric layer413C.

FIGS. 18A to 22A, andFIGS. 18B to 22Bare cross-sectional views schematically illustrating a method of manufacturing a ferroelectric memory device according to an embodiment of the present disclosure. The method may be used to manufacture the ferroelectric memory device4described above with reference toFIGS. 17A and 17B.

First, a manufacturing process substantially the same as the manufacturing process described above with reference toFIGS. 8 and 9may be performed. A sacrificial layer202and a source insulation layer205may be formed on a substrate201. A stack structure including interlayer sacrificial layers210a,210b,210c,210d,210e,210f,210gand210hand interlayer insulation layers220a,220b,220c,220d,220e,220f,220gand220h, which are alternately stacked with each other, may be formed on the source insulation layer205. Then, a trench40′ penetrating the stack structure into the substrate201may be formed.

Referring toFIG. 18A, a first ferroelectric amorphous material layer410, a crystalline ferroelectric induction layer601, a second ferroelectric amorphous material layer602, and a channel layer420may be sequentially formed on an inner surface of the trench40′. The first ferroelectric amorphous material layer410, the crystalline ferroelectric induction layer601, the second ferroelectric amorphous material layer602, and the channel layer420may be formed using a chemical vapor deposition method, an atomic layer deposition method, etc., for example. The first and second ferroelectric amorphous material layers410and602may each be formed to have a thickness of about 5 nm to about 15 nm, and the ferroelectric induction layer601may be formed to have a thickness of about 1 nm to about 5 nm.

A filling insulation layer430may be formed thereafter, and portions of the first ferroelectric amorphous material layer410, crystalline ferroelectric induction layer601, second ferroelectric amorphous material layer602, channel layer420and filling insulation layer430formed outside the trench40′ may be planarized. This process may be substantially the same as the process described above with reference toFIG. 10.

Referring toFIGS. 19A and 19B, the interlayer sacrificial layers210a,210b,210c,210d,210e,210f,210gand210hmay be selectively removed to form recesses50selectively exposing the first to eighth interlayer insulation layers220a,220b,220c,220d,220e,220f,220gand220hand the first ferroelectric amorphous material layer410. This process may be substantially the same as the process described above with reference toFIG. 11.

Referring toFIGS. 20A and 20B, a gate electrode layer603may be formed on the first ferroelectric amorphous material layer410and the first to eighth interlayer insulation layers220a,220b,220c,220d,220e,220f,220gand220hinside the recesses50. In addition, a conductive layer604may be formed on the gate electrode layer603. The conductive layer604may be formed to fill each the recess50in which the gate electrode layer603is formed. As a result, first to eighth gate structures620a,620b,620c,620d,620e,620f,620gand620hmay be formed.

Referring toFIGS. 21A and 21B, crystallization heat treatment may be performed with respect to the first and second ferroelectric amorphous material layers410and602using the ferroelectric induction layer601. The crystallization heat treatment process may include the process of heat-treating the first and second ferroelectric amorphous material layers410and602in contact with the ferroelectric induction layer601to develop a ferroelectric property in the resulting layers. As a result, as illustrated inFIGS. 21A and 21B, the first and second ferroelectric amorphous material layers410and602can be converted into crystalline first and second gate dielectric layers413C and612having ferroelectric properties.

Referring toFIGS. 22A and 22B, the source insulation layer205may be selectively removed. And, the first gate dielectric layer413C, the ferroelectric induction layer601, and the second gate dielectric layer612may be additionally removed to form side recess spaces60. As the side recess spaces60are formed, the trench40′ may be converted into a trench40including a first portion40aand a second portion40bthat are separated from each other.

Then, the side recess spaces60may be filled with a conductive material to form a source contact layer203. The conductive material may include, for example, semiconductor doped into n-type or p-type. As a specific example, the conductive material may be n-type doped silicon. The source contact layer203may be formed to contact a portion of the channel layer420.

Referring toFIG. 22A, an upper portion of the filling insulation layer430may be selectively etched to form a recess. Then, the recess may be filled with a conductive material to form a channel contact layer470.

Through the above-described process, a ferroelectric memory device according to an embodiment of the present disclosure can be manufactured. As described above, crystallization heat treatment may be performed with respect to the first and second ferroelectric amorphous material layers while a ferroelectric induction layer including an insulator is in contact with the first and second ferroelectric amorphous material layers, respectively. Accordingly, a crystalline gate dielectric layer having a ferroelectric property can be effectively secured from the first and second ferroelectric amorphous material layers.

The embodiments of the inventive concept have been disclosed above for illustrative purposes. Those of ordinary skill in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the inventive concept as disclosed in the accompanying claims.