Switch circuit, analog-to-digital converter, and integrated circuit

A switch circuit includes: a sampling transistor including a source connected to an input node and a drain connected to an output node; a control circuit which is connected to a gate of the sampling transistor and configured to control turning on or off of the sampling transistor; a voltage holding circuit which is provided between the gate and the source of the sampling transistor and configured to maintain a voltage between the gate and the source of the sampling transistor constant when the sampling transistor is turned on; and a protection circuit which is provided in parallel to the control circuit and configured to lower a voltage that is applied to the gate of the sampling transistor when the sampling transistor makes a transition from on to off.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2015-016032, filed on Jan. 29, 2015, the entire contents of which are incorporated herein by reference.

FIELD

The technique disclosed herein relates to a switch circuit, an analog-to-digital converter, and an integrated circuit.

BACKGROUND

It is important for the characteristics of a switch that is used via an analog signal not to distort the analog signal through the on-resistance of the switch. An analog-to-digital converter (ADC) has a switch circuit and a sampling capacitor. In the ADC, in the case where a distortion occurs in a signal due to the switch circuit configured to sample an analog signal, the conversion characteristics of the ADC are worsened accordingly. A transistor that is used to sample an analog signal by a switch circuit of the ADC is referred to as a sampling transistor. Hereinafter, not limited to the ADC, a transistor that forms an analog switch turning on or off an analog signal is referred to as a sampling transistor here. In other words, what is referred to as a sampling transistor is not limited to the ADC, and whatever is used as a main switch of an analog switch circuit may be referred to as a sampling transistor.

As a switch circuit configured to sample an analog signal, a CMOS switch having an NMOS and a PMOS connected in parallel is used, but a gate-source voltage Vgs of the NMOS and PMOS changes in accordance with an input voltage. Because of this, in the CMOS switch, the on-resistance changes depending on the input voltage and a distortion occurs in an analog signal.

As a technique for improving accuracy of analog signal processing by reducing the distortion of a signal, which occurs due to a change in the on-resistance depending on the input voltage, a bootstrap switch (hereinafter, referred to as BSW) is known. It is possible for the BSW to maintain the gate-source voltage of a sampling transistor almost constant. By using the BSW in a switch circuit of an analog signal, it is possible to improve the accuracy of analog signal processing by reducing the distortion of a signal, which occurs due to a change in the on-resistance.

In recent years, the operation voltage is lowered remarkably in order to reduce power consumption and further, miniaturization of a circuit element is in progress, and therefore, the withstand voltage of a circuit element is lowered. The withstand voltage of the transistor forming the BSW is also lowered and the withstand voltage of the transistor of the BSW has lowered below a value twice the power source voltage. In the above-described BSW, if the input signal swings fully between 0 V and a power source voltage VDD, a case may occur where a voltage about twice the power source voltage is applied to a transistor, which is a part of the circuit, when the sampling transistor makes a transition from on to off.

In order to avoid this problem of withstand voltage, the control circuit configured to reduce the gate voltage of the sampling transistor to a low potential when the sampling transistor is turned off is formed by transistors in two stages connected in series, and the voltage that is applied to each transistor is reduced.

RELATED DOCUMENTS

SUMMARY

According to an aspect of the embodiments, a switch circuit includes: a sampling transistor having a source connected to an input node and a drain connected to an output node; a control circuit which is connected to a gate of the sampling transistor and configured to control turning on or off of the sampling transistor; a voltage holding circuit which is provided between the gate and the source of the sampling transistor and configured to maintain a voltage between the gate and the source of the sampling transistor constant when the sampling transistor is turned on; and a protection circuit which is provided in parallel to the control circuit and configured to lower a voltage that is applied to the gate of the sampling transistor when the sampling transistor makes a transition from on to off.

The object and advantages of the embodiments will be realized and attained by means of the elements and combination particularly pointed out in the claims.

DESCRIPTION OF EMBODIMENTS

Before explaining the switch circuit of an embodiment, a general switch circuit is explained.

FIG. 1Aillustrates a circuit configuration of a CMOS switch.FIG. 1Bis a diagram for explaining the operation of the circuit inFIG. 1A.FIG. 1Cillustrates a change in the gate-source voltage Vgs of a transistor.

The CMOS switch is used widely as a switch that samples an analog signal. The CMOS switch has an NMOS and a PMOS connected in parallel between an input node and an output node, a switch SWX that switches the gate of the NOMS between 0 V and VDD, and a switch SWY that switches the gate of the PMOS between VDD and 0 V.

As illustrated inFIG. 1A, when the switch SWX is connected to 0 V and the switch SWY to VDD, the NMOS and the PMOS turn off and the CMOS switch enters the cutoff state. As illustrated inFIG. 1B, when the switch SWX is connected to VDD and the switch SWY to 0 V, the NMOS and the PMOS turn on, and the CMOS switch enters the pass-through state and outputs an analog input signal Vi at the input node as an analog output signal Vo at the output node. In this case, as illustrated inFIG. 1C, the voltage Vgs of the NMOS and the PMOS changes in accordance with the voltage of the input signal Vi, and therefore, in the CMOS switch, the on-resistance changes depending on the input voltage and a distortion occurs in the analog signal.

As a technique for improving the accuracy of analog signal processing by reducing the distortion of the signal, which occurs accompanying the change in the on-resistance depending on the input voltage in the CMOS switch, a bootstrap switch (hereinafter, referred to as BSW) is known.

FIG. 2Aillustrates a circuit configuration of a bootstrap switch (BSW).FIG. 2Bis a diagram explaining the operation of the circuit inFIG. 2A.FIG. 2Cillustrates a change in the gate-source voltage Vgs of the sampling transistor.

The BSW has an NMOS transistor M0corresponding to the sampling transistor, a power storage capacitor element C0, and three switches SW1to SW3. The M0is connected between the input node and the output node and serves as a main transistor that transmits the analog input signal Vi as the analog output signal Vo. The SW1, C0, and SW2are connected in series between a 0V power source (second potential power source) and a VDD power source (first potential power source). The voltage of the VDD power source (first potential power source) is, for example, 1.0 to 1.2 V, and is higher than the voltage (0 V) of the 0V power source (second potential power source). The SW2switches one of terminals of the C0so as to connect to the VDD power source or the gate of the M0. The SW1switches the other terminal of the Co so as to connect to the 0V power source or the input node (source of M0). The SW3switches between connecting the gate of the M0to the 0-V power source and not connecting.

As illustrated inFIG. 2A, when the SW1is connected to the 0V power source, the SW2to the VDD power source, and the SW3to the 0V power source, then, the M0turns off and the BSW enters the cutoff state. At this time, the C0is charged to VDD. As illustrated inFIG. 2B, when the SW1is connected to the input node, the SW2to the gate of the M0, and the SW3is opened, then, a voltage Vi+VDD, which is the sum of the voltage Vi of the input signal and the charged voltage VDD of the C0, is applied to the gate of the M0, and therefore, the M0turns on. Due to this, the analog input signal at the input node is output to the output node as the analog output signal Vo. As described above, the gate voltage of the M0is Vi+VDD and the gate-source voltage Vgs of the M0is kept almost constant as illustrated inFIG. 2C.

By using the BSW as a sampling switch of an analog signal, it is possible to reduce a distortion of the signal, which occurs when the on-resistance changes, and thereby, to improve the accuracy of analog signal processing.

However, the withstand voltage of the transistor forming the BSW is a value lower than twice the power source voltage and in the case where the BSW is implemented actually by the transistor, when the BSW makes a transition from on to off, there occurs a case where the withstand voltage is exceeded in part of transistors. If the withstand voltage is exceeded, the transistor will be destroyed.

FIG. 3AandFIG. 3Bare circuit diagrams, in which the switch whose withstand voltage may be exceeded is replaced with a transistor in the BSW inFIG. 2A, andFIG. 3illustrates a state where the sampling transistor is off andFIG. 3Billustrates a state where the sampling transistor is on.

As illustrated inFIG. 3AandFIG. 3B, the SW3is implemented by an NMOS transistor M5connected between the gate of the M0and the 0V power source. To the gate of the M5, a control signal Φ is applied.

As illustrate inFIG. 3A, when Φ=VDD (high level), the SW1is connected to the 0V power source, the SW2is connected to the VDD power source, and the SW3is connected to the 0V power source and the M5turns on, and the gate of the M0(node G) becomes 0 V, and therefore, the M0turns off and the BSW enters the cutoff state. At this time, the C0is charged to VDD. The terminal at the high side of the C0is denoted by H and the terminal at the low side by L.

As illustrate inFIG. 3B, when c=0 V (low level), the SW1is connected to the input node, the SW2is connected to the gate of the M0, and the gate of the M5becomes 0 V and the M5turns off, and to the gate of the M0(node G), the input signal Vi+VDD is applied, and therefore, the M0turns on and the BSW enters the conduction state.

For example, a case is considered where Vi fully swings between 0 V and VDD. When Vi=VDD, the node G becomes 2×VDD and the drain-source voltage of the M5becomes 2×VDD, and therefore, the withstand voltage is exceeded.

FIG. 4AandFIG. 4Bare diagrams of the BSW that has been modified so as to avoid the problem of withstand voltage.FIG. 4Aillustrates the state where the sampling transistor is off andFIG. 4Billustrates the state where the sampling transistor is on.

The circuits inFIG. 4AandFIG. 4Bare each the circuit inFIG. 3Ain which an NMOS transistor M4is inserted between the drain of the M5and the node G. To the gate of the M4, VDD is applied. As illustrated inFIG. 4A, when Φ=VDD, the M5turns on and a connection node D2of the M4and the M5becomes 0 V, and therefore, the M4turns on, the node G becomes 0 V, and the M0turns off.

As illustrated inFIG. 4B, when Φ=0 V, the node G becomes Vi+VDD, the M5turns off, and the M0turns on. At this time, because the node D2becomes VDD, the M4turns off, the drain-source voltage of the M5becomes VDD, and the drain-source voltage of the M4becomes Vi (VDD at the maximum), and therefore, the drain-source voltage of the M5does not exceed the withstand voltage.

As described previously, in the state where the M0is off (FIG. 4A), the power storage capacitor C0is charged to the power source voltage VDD and the gate voltage of the M0is controlled to be 0 V. On the other hand, in the state where the M0is on (FIG. 4B), the gate-source voltage of the M0is VDD and is almost constant. As described above, in the constant state, it is unlikely that Vgs of the transistors M4and M5exceeds the withstand voltage in the BSW inFIGS. 4A and 4B. However, transiently, there may occur a case where a voltage exceeding the withstand voltage is applied to the M4. In the following, a transient state where the M0changes from off to on and from on to off is explained.

FIG. 5is a diagram illustrating an operation sequence of the BSW inFIG. 4AandFIG. 4B.

When the M0makes a transition from off to on, the control signal Φ changes from VDD to 0 V. At this time, by the M5turning off, the node D2changes from 0 V to VDD. Next, by the M4turning off, the node H connecting to the node G (SW2), and the node L connecting to the input node (Vi), the node L, the node H, and the node G increase in voltage in accordance with the analog signal Vi. InFIG. 5, Vi=VDD, and therefore, the node L increases in voltage up to VDD, and the node H and the node G increase in voltage up to 2×VDD.

When the M0makes a transition from on to off, the control signal Φ changes from 0 V to VDD. At this time, by the M5turning on, the node D2changes from VDD to 0 V. Next, the M4turns on, the node G is connected to 0 V (changed from VDD+Vi to 0 V), the node L is connected to 0 V (SW1), and the node H is connected to VDD (SW2).

When the M0makes a transition from on to off, the M4and M5are in charge of dropping the node G to 0 V. When the M5turns on and the node D2changes from VDD to 0 V, if the threshold value of the M4is taken to be Vth (M4), the drain-source voltage of the M4increases until the voltage of the node D2becomes equal to or less than VDD-Vth (M4).

The voltage of the ideal node G is VDD+Vi, and therefore, a drain-source voltage VDS of the M4increases up to Vi+Vth (M4). As described above, when the M0makes a transition from on to off, there occurs a case where the drain-source voltage of the M4exceeds the transistor withstand voltage.

When the M0makes a transition from on to off, in the circuit configuration of the BSW illustrated inFIG. 4, it is unavoidable that the drain-source voltage of the M4increases up to Vi+Vth (M4). Because of this, in the BSW of the embodiment that is explained in the following, an increase in the drain-source voltage VDS is avoided so that the transistor (M4) does not exceed the withstand voltage when the M0makes a transition from on to off.

FIG. 6is a circuit diagram of the bootstrap switch (BSW) of the embodiment, illustrating the state where the sampling transistor is off.

FIG. 7is a circuit diagram of the bootstrap switch (BSW) of the embodiment, illustrating the state where the sampling transistor is on.

InFIG. 6, reference symbol10denotes a control signal generation circuit configured to generate control signals Φ2and Φ3from a control signal Φ1. The control signal Φ2is a signal obtained by delaying the control signal Φ1and the control signal Φ3is a signal obtained by further delaying the control signal Φ1.

The BSW of the embodiment has the sampling transistor M0that is connected between the input node to which the analog input signal Vi is input and the output node from which the analog output signal Vo is output. The M0is a main transistor that transmits the analog input signal Vi as the analog output signal Vo.

The BSW of the embodiment further has a PMOS transistor M3, the power storage capacitor C0, and an NMOS transistor M6that are connected in series between the VDD power source and the 0V power source. The high-side terminal of the power storage capacitor C0is represented by the node H and the low-side terminal by the node L. The gate of the M3is connected to the gate of the M0(node G) and to the gate of the M6, the control signal Φ3is applied. The BSW of the embodiment further has an NMOS transistor M1that is connected between the input node and the node L of the power storage capacitor C0, and a PMOS transistor M2that is connected between the gate of the M0(node G) and the node H of the power storage capacitor C0. The gate of the M1is connected to the gate of the M0(node G) and to the gate of the M2, the control signal Φ3is applied. The M1and M6form the SW1inFIG. 4AandFIG. 4B. The M2and M3form the SW2inFIG. 4AandFIG. 4B.

The BSW of the embodiment further has the NMOS transistors M4and M5that are connected in series between the gate of the M0(node G) and the 0V power source. To the gate of the M4, VDD is applied and to the gate of the M5, the control signal Φ2is applied. The M4and M5in the embodiment correspond to the M4and M5inFIG. 4AandFIG. 4B.

The above configuration is the same as that of the BSW inFIGS. 4A and 4B.

The BSW of the embodiment further has a damping capacitor CVD1and a damping capacitor CVD2that are connected in series between the gate of the M0(node G) and the 0V power source, and an NMOS transistor M11that is connected between a connection the node D1of the CVD1and CVD2, and the 0V power source. To the gate of the M11, the control signal Φ1is applied. Here, the circuit formed by the CVD1, CVD2, and M11is referred to as a protection circuit. In other words, the BSW of the embodiment differs from the circuit inFIG. 4AandFIG. 4Bin that the protection circuit is added.

The damping capacitor CVD1is provided in order to protect the M11so that the withstand voltage of the M11is achieved and to lower the voltage of the node G when the M0makes a transition from on to off. The control signal Φ1of the M11is applied in order to reduce the drain-source voltage of the M4in advance before the M5turns on and the drain-source voltage of the M4increases. The damping capacitor CVD2is provided in order to prevent the voltage of the node G from being damped by reducing the serial capacitance of the damping capacitor CVD1and the damping capacitor CVD2in the constant state where the M0is on. The reason is that if the voltage of the node G is damped when the M0is on, the gate-source voltage of the M0is reduced and the on-resistance increases. Other basic operations are the same as those of the circuit inFIGS. 4A and 4B, and the circuit operation is explained with the added protection circuit being included.

As illustrated inFIG. 6, when Φ=VDD and the M0is in the off state, as in the circuit inFIG. 4AandFIG. 4B, the power storage capacitor C0is charged to the power source voltage VDD, the M5and M4turn on, and the gate voltage of the M0is controlled to be 0 V. At this time, the gate of the M11is VDD, and therefore, the M11turns on and the node D1is also controlled to be 0 V.

On the other hand, as illustrated inFIG. 7, when Φ=0 V and the M0is in the on state, as in the circuit inFIGS. 4A and 4B, the M5and M4turn off, the gate voltage of the M0becomes Vi+VDD, and the gate-source voltage Vgs of the M0becomes VDD and is almost constant.

At this time, the gate of the M11is 0 V, and therefore, the M11turns off and the voltage of the node D1becomes a voltage obtained by dividing the voltage of the node G in a ratio between the capacitances of the damping capacitor CVD1and the damping capacitor CVD2.

Next, the transient state where the M0makes a transition from off to on and from on to off is explained.

FIG. 8is a diagram illustrating the operation sequence of the BSW of the embodiment.FIG. 8illustrates the case where Vi=VDD.

First, the case where the M0makes a transition from off to on is explained.

The control signal Φ1changed from VDD to 0 V. The M11that is added to the BSW of the embodiment turns off, and therefore, to the node G, the damping capacitor CVD1and the damping capacitor CVD2connected in series is connected between the node G and the 0V power source. The D1becomes a voltage obtained by dividing the voltage of the node G in a ratio between the capacitances of the damping capacitor CVD1and the damping capacitor CVD2.

Next, when the control signal Φ2changes from VDD to 0 V, the M5turns off. In response to this, the node D2changes from 0 V to VDD and the M4turns off.

Finally, by the control signal Φ3, the node H of the power storage capacitor C0is connected to the node G, and the node L is connected to the input node and Vi is applied. Due to this, the node L, the node H, and the node G enter the state of fluctuating in accordance with the analog signal Vi.

InFIG. 8, Vi=VDD, and therefore, the node L of the power storage capacitor C0becomes VDD and the node H of the power storage capacitor C0and the node G increase in voltage up to 2×VDD.

The voltage of the node G when the M0is on is found from expression (1) below.
G=(VDD+Vi)×C0/(C0+C)  (1)

Next, the case where the M0makes a transition from on to off is explained.

The control signal Φ1changes from 0 V to VDD. The M11that is added to the BSW of the embodiment turns on, and therefore, a state is brought about where only the damping capacitor CVD1is connected to the node G between the node G and the 0V power source.

Next, when the control signal Φ2changes from 0 V to VDD, the M5turns on and the node D2changes from VDD to 0 V. In response to this, the M4turns on and the node G is connected to 0 V (changed from VDD+Vi to 0 V).

Finally, by the control signal Φ3, the node L of the power storage capacitor C0is connected to 0 V and the node H of the power storage capacitor C0is connected to VDD.

When the M0makes a transition from on to off, the M4and M5are in charge of dropping the node G to 0 V. However, unlike the circuit inFIGS. 4A and 4B, in the BSW of the embodiment, before the node G is dropped to 0 V by the M4and M5, the voltage of the node G is divided in a ratio between the capacitances of the power storage capacitor C0and the damping capacitor CVD1by connecting the damping capacitor CVD1to the node G.

By lowering the voltage of the node G by dividing the voltage in a ratio between the capacitances of the power storage capacitor C0and the damping capacitor CVD1, it is possible to reduce the drain-source voltage Vgs of the M4.

The voltage of the node G at this time is found from expression (2) below (see “DAMPING BY CVD1” inFIG. 8).
G=(VDD+Vi)×C0/(C0+CVD1)  (2)

After this, when the M5turns on and the node D2changes from VDD to 0 V, the drain-source voltage VDS of the M4increases until VDS reaches a voltage exceeding the threshold value of the M4.

However, it is possible to create a design so that the withstand voltage is not exceeded because the drain-source voltage of the M4can be reduced in advance by the damping capacitor CVD1.

As explained above, in the circuit illustrated inFIGS. 4A and 4B, it is unavoidable that the drain-source voltage of the M4increases up to Vi+Vth when the M0makes a transition from on to off. The reason is that in order to cause the M0to make a transition from on to off, it is necessary to reduce the voltage of the node D2until a voltage exceeding the threshold value is reached.

In contrast to this, in the circuit of the BSW of the embodiment, at the timing before the node G is changed from VDD+Vi to 0 V by the M4and M5, the M11is turned on and the voltage of the node G is dropped. It is possible to arbitrarily design the voltage of the node G when the M11turned by determining the power storage capacitor C0and the damping capacitor CVD1in accordance with expression (2). Due to this, the problem in that the drain-source voltage VDS of the M4exceeds the withstand voltage can be solved. Consequently, the capacitance value of the damping capacitor CVD1becomes a value comparatively close to the capacitance value of the power storage capacitor C0.

Further, the damping capacitor CVD2is used in order to reduce the serial capacitance of the damping capacitor CVD1and the damping capacitor CVD2in the constant state where the M0is on. It is possible to arbitrarily design the voltage of the node G at this time by determining the power storage capacitor C0, the damping capacitor CVD1, and the damping capacitor CVD2in accordance with expression (1).

The on-resistance of the switch does not become worse because it is possible to suppress the damping of the node G when the M0is on by reducing the serial capacitance of the damping capacitor CVD1and the damping capacitor CVD2. Consequently, the capacitance value of the damping capacitor CVD2becomes a value sufficiently small compared to the capacitance value of the damping capacitor CVD1.

Next, an example of a circuit and a system to which the switch circuit of the embodiment is applied is explained.

FIG. 9Ais a diagram illustrating a configuration example of a circuit to which the switch circuit of the embodiment is applied.FIG. 9Bis a diagram illustrating a configuration example of a reception system to which the switch circuit of the embodiment is applied.FIG. 9Cillustrates an ultrasonic reception system to which the switch circuit of the embodiment is applied.

As illustrated inFIG. 9A, an ADC circuit20has a sampling circuit21configured to sample an analog signal that is input and an ADC unit22configured to converted a sampled analog signal into a digital signal. The conversion method of the ADC unit22may be any method. The sampling circuit21has a switch circuit23and a sampling capacitor24. By applying the switch circuit of the embodiment as the switch circuit23, it is possible to form an ADC circuit whose accuracy of analog signal processing (here, AD conversion processing) is improved by a low withstand voltage circuit element. The ADC circuit20may be formed as a single semiconductor integrated circuit device or as part of a semiconductor integrated circuit device.

As illustrated inFIG. 9B, the reception system of radio communication equipment has an antenna31, a low noise amplifier (LNA)32, a filter33, a frequency conversion unit34, a PLL35, an ADC circuit36, and a digital baseband signal processing circuit unit37. By applying the ADC circuit inFIG. 9Aas the ADC circuit36, it is possible to form a reception system whose accuracy of analog signal processing (reception processing) is improved by a low withstand voltage circuit element. For example, each of the ADC circuit36and the digital baseband signal processing unit37may be formed as a single semiconductor integrated circuit device.

As illustrated inFIG. 9C, the ultrasonic reception system has an ultrasonic transducer41, a low noise amplifier (LNA)43, a time gain correction circuit43, a filter44, an ADC circuit45, and a digital calculation processing circuit unit46. By applying the ADC circuit inFIG. 9Aas the ADC circuit45, it is possible to form an ultrasonic reception system whose accuracy of analog signal processing (here, ultrasonic reception processing) is improved by a low withstand voltage circuit element. For example, each of the ADC circuit45and the digital calculation processing circuit unit46may be formed as a single semiconductor integrated circuit device.

All examples and conditional language provided herein are intended for pedagogical purposes of aiding the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as limitations to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a illustrating of the superiority and inferiority of the invention. Although one or more embodiments of the present invention have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.