Semiconductor device and memory

Embodiments relate to the field of semiconductor technology, and proposes a semiconductor device and a memory. The semiconductor device includes a pull-up circuit integration region, a pull-down circuit integration region and a compensation circuit integration region not overlapped with one another. The semiconductor device further includes an output circuit, and the output circuit includes: a pull-up circuit, a pull-down circuit, and a compensation circuit. The pull-up circuit is connected to a signal output line, and the pull-up circuit is positioned in the pull-up circuit integration region. The pull-down circuit is connected to the signal output line, and the pull-down circuit is positioned in the pull-down circuit integration region. The compensation circuit is configured to enhance a drive capability of an output signal from the signal output line, and the compensation circuit is positioned in the compensation circuit integration region.

TECHNICAL FIELD

The present disclosure relates to the field of semiconductor technology, and more particularly, to a semiconductor device and a memory.

BACKGROUND

In related technologies, an output circuit of a memory includes a pull-up circuit, a pull-down circuit, and a compensation circuit configured to improve a drive capability of an output signal from the output circuit. The compensation circuit is generally integrated in an integration region where the pull-up circuit and the pull-down circuit are positioned.

However, it is found that a larger parasitic capacitance may be formed between a control line connected to the compensation circuit and the pull-up circuit or pull-down circuit, which is not conducive to optimization of a signal from the control line connected to the compensation circuit.

It should be noted that information disclosed in the above background section is used merely for enhancement of understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to those of ordinary skill in the art.

SUMMARY

According to one aspect of the present disclosure, there is provided a semiconductor device, wherein the semiconductor device includes a pull-up circuit integration region, a pull-down circuit integration region and a compensation circuit integration region not overlapped with one another. The semiconductor device further includes an output circuit, which includes: a pull-up circuit, a pull-down circuit, and a compensation circuit. The pull-up circuit is connected to a signal output line, and the pull-up circuit is positioned in the pull-up circuit integration region. The pull-down circuit is connected to the signal output line, and the pull-down circuit is positioned in the pull-down circuit integration region. The compensation circuit is configured to enhance a drive capability of an output signal from the signal output line, and the compensation circuit is positioned in the compensation circuit integration region.

According to one aspect of the present disclosure, there is provided a memory, which includes the above-described semiconductor device.

It is to be understood that the above general description and the detailed description below are merely exemplary and explanatory, and do not limit the present disclosure.

DETAILED DESCRIPTION

The exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be implemented in a variety of forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided such that the present disclosure will be thorough and complete and will fully convey the concepts of exemplary embodiments to those skilled in the art. Throughout the drawings, similar reference signs indicate the same or similar structures, and their detailed description will be omitted.

Although this specification employs relativity terms such as “above” and “below” to describe a relative relation between one component and another component of icons, these terms are merely for convenience of this specification, for example, the directions of the examples in the accompanying drawings. It is to be understood that when the apparatus of the icon are turned upside down, components described as “above” will become components described as “below”. Other relative terms such as “high”, “low”, “top”, “bottom”, “left”, “right” and so on also have similar meanings. When a certain structure is “above” other structures, it likely means that the certain structure is integrally formed on the other structures, or the certain structure is “directly” arranged on the other structures, or the certain structure is “indirectly” arranged on the other structures by means of another structure.

The terms “one”, “a” and “the” are intended to mean that there exists one or more elements/constituent parts/etc. The terms “comprising” and “having” are intended to be inclusive and mean that there may be additional elements/constituent parts/etc. other than the listed elements/constituent parts/etc.

As shown inFIGS.1,2, and3,FIG.1is a schematic structural diagram of an output circuit in an exemplary embodiment,FIG.2is an equivalent circuit diagram of part of structures of the output circuit shown inFIG.1, andFIG.3is a structural layout of the output circuit shown inFIG.1. The output circuit includes a pull-up circuit, a pull-down circuit, a switch circuit3, a pull-up compensation circuit, and a pull-down compensation circuit. The pull-up circuit includes a plurality of pull-up subcircuits11, the pull-down circuit includes a plurality of pull-down subcircuits21, the switch circuit3includes a plurality of switch subcircuits31, the pull-up compensation circuit includes a plurality of pull-up compensation subcircuits411, and the pull-down compensation circuit includes a plurality of pull-down compensation subcircuits421. As shown inFIGS.1,2, and3, the pull-up subcircuit11may include a first transistor T1, the pull-down subcircuit21may include a third transistor T3, the pull-up compensation subcircuit411may include a second transistor T2, the pull-down compensation circuit may include a fourth transistor T4, and the switch subcircuit31may include a fifth transistor T5. As shown inFIG.2, a pull-up subcircuit11, a pull-down subcircuit21, a switch subcircuit31, a pull-up compensation subcircuit411, and a pull-down compensation subcircuit421may form an output unit. In the same output unit, a first electrode of the first transistor T1is connected to a signal output line LDQ, a second electrode of the first transistor T1is connected to a second electrode of the fifth transistor T5, and a gate of the first transistor T1is connected to a pull-up control signal line MPU. A first electrode of the fifth transistor T5is connected to a first high-level power supply terminal VDD1. A first electrode of the third transistor T3is connected to a signal output line LDQ, a second electrode of the third transistor T3is connected to a first low-level power supply terminal VSS1, and a gate of the third transistor T3is connected to a pull-down control signal line MPD. A first electrode of the second transistor T2is connected to the signal output line LDQ, a second electrode of the second transistor T2is connected to a second high-level power supply terminal VDD2, and a gate of the second transistor T2is connected to a pull-up compensation control line BPU. A first electrode of the fourth transistor T4is connected to the signal output line LDQ, a second electrode of the fourth transistor T4is connected to a second low-level power supply terminal VSS2, and a gate of the fourth transistor T4is connected to a pull-down compensation control line BPD.

In this exemplary embodiment, when the switch subcircuit31is turned on, a valid level signal is inputted into the pull-up control signal line MPU or the pull-down control signal line MPD to turn on one of the transistors connected thereto. When the valid level signal is inputted into the pull-up control signal line MPU to turn on the pull-up subcircuit11, the pull-down subcircuit21is turned off, and the signal output line LDQ outputs a high-level signal. When the valid level signal is inputted into the pull-down control signal line MPD to turn on the pull-down subcircuit21, the pull-up subcircuit11is turned off, and the signal output line LDQ outputs a low-level signal, such that the output circuit may controllably output the high-level signal or the low-level signal.

In addition, the pull-up compensation control line BPU may output a valid level signal to turn on the pull-up compensation subcircuit411when the valid level signal is inputted into the pull-up control signal line MPU, and the pull-up compensation subcircuit411transmits a high-level signal of the second high-level power supply terminal VDD2to the signal output line LDQ, such that a pull-up drive capability of an input signal from the signal output line LDQ may be enhanced. The pull-down compensation control line BPD may output a valid level signal to turn on the pull-down compensation subcircuit421when the pull-down control signal line MPD outputs the valid level signal, and the pull-down compensation subcircuit421may transmit a low-level signal of the second low-level power supply terminal VSS2to the signal output line LDQ, such that a pull-down drive capability of an output signal from the signal output line LDQ may be enhanced. The stronger the pull-up drive capability of the output signal is, the steeper a rising edge of the output signal is; the stronger the pull-down drive capability of the output signal is, the steeper a falling edge of the output signal is; and correspondingly, the stronger the pull-up drive capability and the pull-down drive capability of the output signal are, the higher a maximum frequency the output signal can reach.

The first high-level power supply terminal VDD1and the second high-level power supply terminal VDD2may share the same high-level power supply terminal, and the first low-level power supply terminal VSS1and the second low-level power supply terminal VSS2may share the same low-level power supply terminal. The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5may be N-type transistors or P-type transistors. The valid level signal may be understood as an on-level signal of a target circuit. For example, when the target circuit is an N-type transistor, the valid level signal is a high-level signal; and when the target circuit is a P-type transistor, the valid level signal is a low-level signal. In one embodiment, the transistors T3and T4are P-Channel Metal Oxide Semiconductor (PMOS) transistors, and the transistors T1, T2and T5are N-Channel Metal Oxide Semiconductor (NMOS) transistors.

As shown inFIG.3, in the same output circuit, number of the pull-up compensation subcircuits411may be equal to that of the pull-up subcircuits11, and the pull-up compensation subcircuits411may be scattered in a pull-up subcircuit integration region01where the pull-up subcircuits11are positioned. Number of the pull-down compensation subcircuits421may be equal to that of the pull-down subcircuits21, and the pull-down compensation subcircuits421may be scattered in a pull-down subcircuit integration region02where the pull-down subcircuits21are positioned. In the same output circuit, the number of the pull-up subcircuits11may be equal to that of the pull-down subcircuits21. For example, the number of the pull-up subcircuits11and the number of the pull-down subcircuits21may be six. However, because the pull-up compensation subcircuits411are scattered in the pull-up subcircuit integration region01where the pull-up subcircuits11are positioned, winding of the pull-up compensation control line BPU is longer, and a larger parasitic capacitance may be generated between the longer pull-up compensation control line BPU and other structures, which is not conducive to optimization of timing sequence of a signal from the pull-up compensation control line BPU. Similarly, because the pull-down compensation subcircuits421are scattered in the pull-down subcircuit integration region02where the pull-down subcircuits21are position, winding of the pull-down compensation control line BPD is longer, and a larger parasitic capacitance may be generated between the longer pull-down compensation control line BPD and other structures, which is not conducive to optimization of timing sequence of a signal from the pull-down compensation control line BPD.

On this basis, this exemplary embodiment provides a semiconductor device, as shown inFIG.4andFIG.5,FIG.4is a schematic structural diagram of a semiconductor device in the present disclosure, andFIG.5is a structural layout of the semiconductor device shown inFIG.4. The semiconductor device includes a pull-up circuit integration region61, a pull-down circuit integration region62, and a compensation circuit integration region63that do not overlap each other, and the semiconductor device further includes an output circuit, where the output circuit may include: a pull-up circuit1, a pull-down circuit2, and a compensation circuit4. The pull-up circuit1is connected to the signal output line LDQ, and the pull-up circuit1is positioned in the pull-up circuit integration region61. The pull-down circuit2is connected to the signal output line LDQ, and the pull-down circuit2is positioned in the pull-down circuit integration region62. The compensation circuit4is configured to enhance the drive capability of the output signal from the signal output line LDQ, and the compensation circuit4is positioned in the compensation circuit integration region63.

In this exemplary embodiment, in the semiconductor device, the compensation circuit4is arranged in the compensation circuit integration region63in a centralized manner, such that capacity of a parasitic capacitance formed between a compensation control line connected to the compensation circuit4and other structures may be reduced, which may be advantageous to reducing optimization of timing sequence of a signal from the compensation control line connected to the compensation circuit4.

In this exemplary embodiment, as shown inFIG.5, the signal output line LDQ extends along a first direction X and is configured to transmit a signal along the first direction X. The compensation circuit integration region63may be positioned on a side of the pull-up circuit integration region61in the first direction X, and the compensation circuit integration region63may be positioned on a side of the pull-down circuit integration region62in the first direction X. As shown inFIG.5, the semiconductor device may further include an output pad integration region64, and the output pad integration region64may be positioned on a side of the compensation circuit integration region63away from the pull-up circuit integration region61. The output pad integration region64may be provided with an output pad DQpad, the output pad DQpad may be connected to the signal output line LDQ, and the output pad Dqpad is configured to output an output signal to outside of the semiconductor device.

In this exemplary embodiment, as shown inFIG.5, the compensation circuit4may include at least one first pull-up compensation subcircuit411, and the first pull-up compensation subcircuit411is configured to pull up the output signal. The compensation circuit integration region63may include a first integration region631, the first pull-up compensation subcircuit411may be positioned in the first integration region631, and the first integration region631may be positioned on a side of the pull-up circuit integration region61in the first direction X.

In this exemplary embodiment, as shown inFIG.5, the compensation circuit4may further include at least one first pull-down compensation subcircuit421, and the first pull-down compensation subcircuit421is configured to pull down the output signal. The compensation circuit integration region63may further include a second integration region632, the first pull-down compensation subcircuit421may be positioned in the second integration region632, and the second integration region632is positioned on a side of the pull-down circuit integration region62in the first direction X.

In this exemplary embodiment, as shown inFIG.6, an equivalent circuit diagram of part of structures of the output circuit in the semiconductor device shown inFIG.4is illustrated. The first pull-up compensation subcircuit411is connected to the signal output line LDQ and a first control signal line BPU1, and the first pull-up compensation subcircuit411is configured to pull up the output signal in response to an enable signal from the first control signal line BPU1. The pull-up circuit1may include a plurality of pull-up subcircuits11, and each of the plurality of pull-up subcircuits11includes a first transistor T1, where a first electrode of the first transistor T1is connected to the signal output line LDQ, a second electrode of the first transistor T1is connected to the first high-level power supply terminal VDD1, and a gate of the first transistor T1is connected to the pull-up control signal line MPU.

In this exemplary embodiment, as shown inFIG.6, the first pull-up compensation subcircuit411may include a second transistor T2, where a first electrode of the second transistor T2is connected to the signal output line LDQ, a second electrode the second transistor T2may be connected to the second high-level power supply terminal VDD2, and a gate the second transistor T2may be connected to the first control signal line BPU1. The first control signal line BPU1may output a valid level signal to turn on the first pull-up compensation subcircuit411when the pull-up control signal line MPU outputs the valid level signal, and the turned-on first pull-up compensation subcircuit411transmits a high-level signal from the second high-level power supply terminal VDD2to the signal output line LDQ, to perform pull-up compensation for a signal from the signal output line LDQ. The first control signal line BPU1may output the valid level signal at a starting moment when the pull-up control signal line MPU outputs the valid level signal. For example, when the first transistor T1is a P-type transistor, the first control signal line BPU1may output the valid level signal on a falling edge of a signal from the control signal line MPU, to implement the pull-up compensation for the signal from the signal output line LDQ.

The first control signal line BPU1is connected to the first pull-up compensation subcircuit411by means of a contact hole, and a smaller distance is provided between this contact hole and other conductive structure or other contact hole in an extension direction of a film layer, such that a larger parasitic capacitance is easily formed between a hole structure connected to the first control signal line BPU1and other structures. In this exemplary embodiment, in the same output circuit, the number of the pull-up subcircuits11in the pull-up circuit1may be greater than that of the first pull-up compensation subcircuits411in the compensation circuit4. For example, in this exemplary embodiment, the number of the pull-up subcircuits11in the pull-up circuit1may be six, and the number of the first pull-up compensation subcircuits411in the compensation circuit4may be two. In this exemplary embodiment, by reducing the number of the first pull-up compensation subcircuit411, number of holes between the first control signal line BPU1and the first pull-up compensation subcircuit411may be reduced, such that the parasitic capacitance of the first control signal line BPU1may be effectively reduced.

An arrangement direction of the first pull-up compensation subcircuits411may be perpendicular or parallel to that of the pull-up subcircuits11in the pull-up circuit. That is, the arrangement direction of the second transistors T2may be perpendicular or parallel to that of the first transistors T1. It should be noted that limitation of the arrangement direction does not limit a gate length direction. For example, when the arrangement direction of the second transistor T2is perpendicular to that of the first transistor T1, the gate length direction of the second transistor T2may be parallel or perpendicular to that of the first transistor T1.

In this exemplary embodiment, the number of the first pull-up compensation subcircuits411is reduced. To ensure the pull-up capability of the first pull-up compensation subcircuits411to the output signal, a size of the second transistor T2may be correspondingly increased in this exemplary embodiment, such that a single first pull-up compensation subcircuits411has a stronger drive capability. Because the compensation circuit integration region63is positioned on a side of a whole formed by the pull-up circuit integration region61and the pull-down circuit integration region62, increasing the size of the second transistor T2having a slightly negative effect on the first transistor T1in the pull-up circuit1, that is, a layout area of a certain first transistor T1is not occupied too much. Therefore, the solution of increasing the size of the second transistor T2and reducing the number of the first pull-up compensation subcircuits411may be achieved. In this exemplary embodiment, the size of the second transistor T2may be greater than that of the first transistor T1.

In this exemplary embodiment, as shown inFIG.4,FIG.5andFIG.6, the first pull-down compensation subcircuit421may be connected to the signal output line LDQ and the second control signal line BPD2, and the first pull-down compensation subcircuit421may be configured to pull down the output signal in response to an enable signal from the second control signal line BPD2. The pull-down circuit2may include a plurality of pull-down subcircuits21, and each of the pull-down subcircuits21may include a third transistor T3, where a first electrode of the third transistor T3is connected to the signal output line LDQ, a second electrode of the third transistor T3is connected to the first low-level power supply terminal VSS1, and a gate of the third transistor T3is connected to the pull-down control signal line MPD.

In this exemplary embodiment, as shown inFIG.4,FIG.5andFIG.6, the first pull-down compensation subcircuit421may include a fourth transistor T4, where a first electrode of the fourth transistor T4is connected to the signal output line LDQ, and a second electrode of the fourth transistor T4is connected to the second low-level power supply terminal VSS2. The second control signal line BPD2may output a valid level signal at a starting moment when the pull-down control signal line MPD outputs the valid level signal, to turn on the first pull-down compensation subcircuit421, and the turned-on first pull-down compensation subcircuit421may transmit a low-level signal from the second low-level power supply terminal VSS2to the signal output line LDQ, to pull down the signal from the signal output line LDQ.

In this exemplary embodiment, the second control signal line BPD2is connected to a first pull-down compensation subcircuit421by means of a contact hole, and a smaller distance is provided between this contact hole connected to the second control signal line BPD2and other conductive structure or other contact hole in an extension direction of a film layer, such that a larger parasitic capacitance is easily formed between a hole structure connected to the second control signal line BPD2and other structure. In this exemplary embodiment, in the same output circuit, the number of the pull-up subcircuits21in the pull-up circuit2may be greater than that of the first pull-up compensation subcircuits421in the compensation circuit4. For example, in this exemplary embodiment, the number of the pull-down subcircuits21in the pull-down circuit2may be six, and the number of the first pull-down compensation subcircuits421in the compensation circuit4may be two. In this exemplary embodiment, by reducing the number of the first pull-down compensation subcircuits421, the number of holes between the second control signal line BPD2and the first pull-down compensation subcircuits421may be reduced, such that the parasitic capacitance of the second control signal line BPD2may be effectively reduced.

In this exemplary embodiment, the number of the first pull-down compensation subcircuits421is reduced. To ensure the pull-down capability of the first pull-down compensation subcircuits421to the output signal, a size of the fourth transistor T4may be correspondingly increased in this exemplary embodiment, such that a single first pull-down compensation subcircuits421has a stronger drive capability. For example, in this exemplary embodiment, the size of the fourth transistor T4may be larger than that of the third transistor T3, and reference may be made to the second transistor T2for feasibility principles of increasing the size of the fourth transistor T4.

As shown inFIGS.4and6, the output circuit may further include a switch circuit3, the switch circuit3may include a plurality of switch subcircuits31, and each of the switch subcircuits31may include a fifth transistor T5, where a first electrode of the fifth transistor T5may be connected to the first high-level power supply terminal VDD1, and a second electrode of the fifth transistor T5is connected to the second electrode of the first transistor T1.

It should be noted that in this exemplary embodiment, the first high-level power supply terminal VDD1and the second high-level power supply terminal VDD2may share the same high-level power supply terminal, and the first low-level power supply terminal VSS1and the second low-level power supply terminal VSS2may share the same low-level power supply terminal.

In this exemplary embodiment, as shown inFIG.5, the plurality of pull-up subcircuits11may be distributed along the first direction X, the plurality of pull-down subcircuits21may be distributed along the first direction X, and a region where the signal output line LDQ is positioned may be positioned between the pull-up circuit integration region61and the pull-down circuit integration region62. The first control signal line BPU1, the pull-up control signal line MPU, the second control signal line BPD2, and the pull-down control signal line MPD may extend along the first direction X, where a region where the first control signal line BPU1is positioned may be positioned between a region where the pull-up control signal line MPU is positioned and the region where the signal output line LDQ is positioned, and a region where the second control signal line BPD2is positioned may be positioned between a region where the pull-down control signal line MPD is positioned and the region where the signal output line LDQ is positioned. The first control signal line BPU1may be configured to shield noise interference between the pull-up control signal line MPU and the signal output line LDQ. The second control signal line BPD2may be configured to shield noise interference between the pull-down control signal line MPD and the signal output line LDQ.

It should be understood that in other exemplary embodiments, an integration region of the first pull-up compensation subcircuit411inFIG.5may also be positioned on a side of the pull-up circuit integration region61in a second direction, where the second direction is opposite to the first direction X. This setting can increase a distance between the first control signal line BPU1and the output pad Dqpad, such that the parasitic capacitance between the first control signal line BPU1and the output pad Dqpad may be reduced. Similarly, an integration region of the first pull-down compensation subcircuit421may also be positioned on a side of the pull-down circuit integration region62in the second direction. As shown inFIG.7, a structural layout of the semiconductor device in another exemplary embodiment of the present disclosure is illustrated. In this exemplary embodiment, the signal output line LDQ extends along the first direction X and is configured to transmit a signal along the first direction X. The compensation circuit integration region63may positioned on a side of the pull-up circuit integration region61in the second direction, and the compensation circuit integration region63may be positioned on a side of the pull-down circuit integration region62in the second direction, where the second direction is opposite to the first direction X.

In this exemplary embodiment, the compensation circuit4may include at least one second pull-up compensation subcircuit412; the compensation circuit integration region63may further include a third integration region633, and the second pull-up compensation subcircuit412may be positioned in the third integration region633; and the third integration region633may be positioned on a side of the pull-up circuit integration region61in the second direction.

In this exemplary embodiment, the compensation circuit4may further include at least one second pull-down compensation subcircuit422; the compensation circuit integration region63may further include a fourth integration region634, and the second pull-down compensation subcircuit422may be positioned in the fourth integration region634; and the fourth integration region634may be positioned on a side of the pull-down circuit integration region62in the second direction.

It should be noted that although in the structural layout shown inFIG.7, the arrangement direction of the second pull-up compensation subcircuit412and the second pull-down compensation subcircuit422is parallel to the arrangement direction of the pull-up subcircuit11and the pull-down subcircuit21, this merely serve as an example. In fact, the arrangement direction of the second pull-up compensation subcircuit412and the second pull-down compensation subcircuit422may also be perpendicular to the arrangement direction of the pull-up subcircuit11and the pull-down subcircuit21.

In this exemplary embodiment, as shown inFIG.8, an equivalent circuit diagram of part of structures of the output circuit in the semiconductor device shown inFIG.7is illustrated. The second pull-up compensation subcircuit412may be connected to the pull-up control signal lines MPU, and the second pull-up compensation subcircuit412may be configured to synchronously compensate for a signal from the pull-up control signal lines MPU. The second pull-up compensation subcircuits412may be arranged in one-to-one correspondence with the pull-up control signal lines MPU, and the second pull-up compensation subcircuit412may be configured to synchronously compensate for a signal from the corresponding pull-up control signal lines MPU. Number of transistors included in each of the second pull-up compensation subcircuits412may be set according to actual needs. In the embodiment as shown inFIG.8, two transistors are included, i.e., a sixth transistor T6and a seventh transistor T7.

In this exemplary embodiment, the second pull-down compensation subcircuit422is connected to the pull-down control signal line MPD, and the second pull-down compensation subcircuit422may be configured to synchronously compensate for a signal from the pull-down control signal line MPD. The second pull-down compensation subcircuits422may be arranged in one-to-one correspondence with the pull-down control signal lines MPU, and the second pull-down compensation subcircuits422may be configured to synchronously compensate for a signal from the corresponding pull-down control signal line MPU. Number of transistors included in each of the second pull-down compensation subcircuits422may be set according to actual needs.

FIG.8only shows one of the second pull-up compensation subcircuits412and one of the second pull-down compensation subcircuits422. In this exemplary embodiment, “synchronous compensation” may be understood as: pulling up a compensated signal on a rising edge of the compensated signal, and pulling down the compensated signal on a falling edge of the compensated signal, such that the rising edge and the falling edge of the compensated signal are steeper.

As shown inFIG.8, the second pull-up compensation subcircuit412may include a sixth transistor T6and a seventh transistor T7. A first electrode of the sixth transistor T6may be connected to the pull-up control signal line MPU, and a second electrode of the sixth transistor T6may be configured to receive a high-level power supply signal. A first electrode of the seventh transistor T7may be connected to the pull-up control signal line MPU, and a second electrode of the seventh transistor T7may be configured to receive a low-level power supply signal. The sixth transistor T6may be turned on on the rising edge of the signal from the pull-up control signal line MPU, to pull up the signal from the pull-up control signal line MPU by means of the high-level power supply signal. The seventh transistor T7may be turned on on the falling edge of the signal from the pull-up control signal line MPU, to pull down the signal from the pull-up control signal line MPU by means of the low-level power supply signal.

Similarly, the second pull-down compensation subcircuit422may include an eighth transistor T8and a ninth transistor T9, where a first electrode of the eighth transistor T8may be connected to the pull-down control signal line MPD, and a second electrode of the eighth transistor T8may be configured to receive the high-level power supply signal. A first electrode of the ninth transistor T9may be connected to the pull-down control signal line MPD, and a second electrode of the ninth transistor T9may be configured to receive the low-level power supply signal. The eighth transistor T8may be turned on on the rising edge of a signal from the pull-down control signal line MPD, to pull up the signal from the pull-down control signal line MPD by means of the high-level power supply signal. The ninth transistor T9may be turned on the falling edge of the signal from the pull-down control signal line MPD, to pull down the signal from the pull-down control signal line MPD by means of the low-level power supply signal.

It is to be understood that this exemplary embodiment only shows that the second pull-up compensation subcircuit412and the second pull-down compensation subcircuit422both include two transistors, and one of the two transistors is configured to pull up a signal, and the other one is configured to pull down a signal. In other embodiments, the second pull-up compensation subcircuit412and the second pull-down compensation subcircuit422may both include one transistor, where the transistor in the second pull-up compensation subcircuit412is configured to pull up a signal, and the transistor in the second pull-down compensation subcircuit422is configured to pull down a signal. In parallel, the second pull-up compensation subcircuit412and the second pull-down compensation subcircuit422may both include a plurality of transistors (more than or equal to two), and the plurality of transistors in the second pull-up compensation subcircuit412are configured to pull up signals, and the plurality of transistors in the second pull-down compensation subcircuit422are configured to pull down signals.

As shown inFIG.7, part of structures of the pull-up control signal line MPU may be positioned in the third integration region633, and the pull-up control signal line MPU may be connected to the sixth transistor T6and the seventh transistor T7through a hole H, respectively. Part of structures of the pull-down control signal line MPD may be positioned in the fourth integration region634, and the pull-down control signal line MPD may be connected to the eighth transistor T8and the ninth transistor T9through the hole H, respectively. This setting can improve the integration level of the output circuit and reduce the layout space of the output circuit.

It should be understood that in other exemplary embodiments, the pull-up control signal line MPU may also be positioned outside the third integration region633, and the pull-down control signal line MPD may also be positioned outside the fourth integration region634. For example, in a direction perpendicular to the first direction X, the third integration region633may be positioned between the pull-up circuit integration region61and the pull-down circuit integration region62, and the fourth integration region634may also be positioned between the pull-up circuit integration region61and the pull-down circuit integration region62. In addition, in other exemplary embodiments, the semiconductor device may be provided with the first integration region631and the second integration region632, and may also be provided with the third integration region633and the fourth integration region634.

Correspondingly, the output circuit may include the first pull-up compensation subcircuit411positioned in the first integration region631and the first pull-down compensation subcircuit421positioned in the second integration region632, and may also include the second pull-up compensation subcircuit412positioned in the third integration region633and the second pull-down compensation subcircuit422positioned in the fourth integrated region634. In addition, the second pull-up compensation subcircuit412positioned in the third integration region633and the second pull-down compensation subcircuit422positioned in the fourth integration region634may also directly perform pull-up compensation and pull-down compensation for the output signal line LDQ. That is, one electrode of the transistor in the second pull-up compensation subcircuits412or second pull-down compensation subcircuit422is directly connected to the output signal line LDQ, and other electrode of the transistor is connected to a high-level power supply or a low-level power supply to achieve pull-up or pull-down.

This exemplary embodiment also provides a memory, which may include the above-mentioned semiconductor device. For example, the memory may be a dynamic random access memory.