Various implementations described herein are directed to an integrated circuit having first dummy bitline circuitry with a first charge storage element and second dummy bitline circuitry coupled to the first dummy bitline circuitry, and the second dummy bitline circuitry has a second charge storage element. The integrate circuit may include decoupling circuitry coupled to the first dummy bitline circuitry and the second dummy bitline circuitry between the first charge storage element and the second charge storage element. The decoupling circuitry may operate to decouple the second charge storage element from the first charge storage element based on an enable signal.

BACKGROUND

To reduce local variation on a self-timing path, multiple active pulldown devices may be used for a dummy bitline (DBL). However, using multiple pulldown devices may cause a faster self-timing path (STP), which may result in problems that modify a sense amplifier differential pulse width and write margin. To assist with fixing those problems, an extra capacitor may be added to the dummy bitline (DBL) to optimize the self-timing path (STP). Unfortunately, using additional capacitors on the dummy bitline (DBL) may result in a DBL precharge component operating similar to a cycle-time component, and hence, overall frequency of an operating clock (CLK) may become slower, and in some situations, the memory may thus operate slower.

DETAILED DESCRIPTION

Various implementations described herein are directed to dummy bitline (DBL) circuitry for memory applications. For instance, various implementations are directed to schemes and techniques that optimize dummy bitline (DBL) precharge without impacting access time. As described herein, some implementations refer to a scheme or technique that splits (or decouples from each other) a dummy bitline capacitor (dbl cap) and another dummy bitline capacitor (dbl_extra cap) with use of decoupling circuitry. Further, some implementations refer to a scheme or technique that splits (or decouples from each other) a dummy bitline capacitor (dbl cap) and another dummy bitline capacitor (dbl_extra cap) with use of a transmission gate, which may open when a global timing pulse (gtp) goes high and close when gtp goes low. Hence, the dbl_extra capacitor may start precharging right after the gtp goes low, and when an activation signal (e.g., dwl_turn) fall occurs, the dbl capacitor may be precharged to only half of its charging potential. Still further, some implementations refer to a scheme or technique that utilizes a faster dbl precharge component, wherein the dbl capacitor and the dbl_extra capacitor are shorted, and by disposing the decoupling circuitry after the short, the dummy bitline may be precharged right after the gtp fall. This may result in a faster activation signal (dwl_turn) fall.

Various implementations of dummy bitline (DBL) circuitry will now be described in greater detail herein with reference toFIGS. 1A-5.

FIG. 1Aillustrates a schematic diagram of memory circuitry100with dummy bitline (DBL) circuitry102A,102B in accordance with various implementations described herein. The memory circuitry100may include an N×M memory array of bitcells118that is arranged with N rows and M columns, wherein each bitcell in the array of bitcells118is accessible via wordlines WL0, WL1, WL2, . . . WLN and bitlines BL0, BL1, . . . BLM. The memory circuitry100may include wordline (WL) drivers and decoders116that are used to access each of the bitcells in the array of bitcells118. The memory circuitry100may include self-timed clock generator circuitry112that may receive a clock signal CLK and provide a global timing signal gtp. The gtp signal is provided to an inverter in1that inverts the gtp signal and provides a dummy wordline signal dwl. The dwl signal may be referred to as dwl_turn signal, which is provided to one or more dummy bitcells104and pulldown logic circuitry110.

Further, as shown inFIG. 1A, first dummy bitline (DBL) circuitry102A may include a first charge storage element Cdbl coupled to a first dummy bitline dbl. The first dummy bitline dbl may be coupled to a second dummy bitline dbl_extra at node n1. In addition, second dummy bitline (DBL) circuitry102B may include second charge storage element Cdbl_extra coupled to the second dummy bitline dbl_extra. The second dummy bitline (DBL) circuitry102B may include a precharge transistor T1, decoupling circuitry106, and the logic pulldown circuitry110that are coupled to the second dummy bitline dbl_extra. The second dummy bitline (DBL) circuitry102B may be coupled to the self-timed clock generator circuitry112, and the second dummy bitline dbl_extra may be used to provide a dbl signal via node n1to another inverter in2that inverts the dbl signal and provides a sense amp signal sae to a sense amplifier (not shown).

In some implementations, the dummy bitline (dbl) precharging may be affected by operating improvements with respect to the dummy bitline (DBL) circuitry described herein. For instance, in reference to the decoupling circuitry106, the dbl precharge happening on the dbl_extra bitline may begin right after the gtp fall, while the dbl prechrage happens after the dwl_turn fall. Hence, these operating instances may improve cycle time of the dummy bitline (DBL) circuitry.

FIGS. 1B-2illustrate various schematic diagrams of dummy bitline (DBL) circuitry in accordance with various implementations described herein. In particular,FIG. 1Bshows a schematic diagram of dummy bitline (DBL) circuitry120, andFIG. 2shows a schematic diagram of dummy bitline (DBL) circuitry200.

As shown inFIG. 1B, the dummy bitline (DBL) circuitry120may include the first dummy bitline circuitry102A having the first charge storage element Cdbl. The dummy bitline (DBL) circuitry120may include the first dummy bitline dbl, and the first charge storage element Cdbl may be coupled to the first dummy bitline dbl, e.g., at node n1. In some instances, as shown, the first charge storage element Cdbl may be coupled between the first dummy bitline dbl and ground. Further, the first charge storage element Cdbl may be embodied as a first bitline capacitor.

The dummy bitline (DBL) circuitry120may include the second dummy bitline circuitry102B coupled to the first dummy bitline circuitry102A, and the second dummy bitline circuitry102B may include the second charge storage element Cdbl_extra. The dummy bitline (DBL) circuitry120may include the second dummy bitline dbl_extra, and the second charge storage element Cdbl_extra may be coupled to the second dummy bitline dbl_extra, e.g., at node n2. In some instances, as shown, the second charge storage element Cdbl_extra may be coupled between the second dummy bitline dbl_extra and ground. Further, the second charge storage element Cdbl_extra may be embodied as a second bitline capacitor.

The dummy bitline (DBL) circuitry120may include the decoupling circuitry106that is coupled to the first dummy bitline circuitry102A and the second dummy bitline circuitry102B between the first charge storage element Cdbl and the second charge storage element Cdbl_extra. The decoupling circuitry106may operate to decouple the second charge storage element Cdbl_extra from the first charge storage element Cdbl based on an enable signal, such as, e.g., one or more of gtp and ngtp.

The enable signal may include multiple enable signals including a first enable signal gtp and a second enable signal ngtp that is a complement of the first enable signal gtp. In this instance, the decoupling circuitry106may operate to decouple the second charge storage element Cdbl_extra from the first charge storage element Cdbl based on the first enable signal gtp and the second enable signal ngtp.

In some implementations, the precharge transistor T1may be referred to as a first transistor T1that is activated based on the first enable signal gtp. The first transistor T1may be coupled to the second dummy bitline dbl_extra, e.g., at node n2. In addition, the first transistor T1may be coupled between a source voltage VDD and the second dummy bitline dbl_extra, e.g., at node n2. Further, the first transistor T1may be a P-type metal-oxide-semiconductor (PMOS) transistor. However, in some scenarios, other types of transistors, such as, e.g., an N-type transistor, may be used.

The decoupling circuitry106may include a second transistor T2that is activated based on the first enable signal gtp. The second transistor T2may be coupled to the second dummy bitline dbl_extra, e.g., between node n2and node n3. Node n3may be the same as node n1. The second transistor T2may be an N-type MOS (NMOS) transistor. However, in some scenarios, other types of transistors, such as, e.g., a P-type transistor, may be used.

The decoupling circuitry106may include a third transistor T3that is activated based on the second enable signal ngtp that is the complement of the first enable signal gtp. The third transistor T3may be coupled to the second dummy bitline dbl_extra, e.g., between node n2and node n3. The third transistor T3may be a P-type MOS (PMOS) transistor. However, in some scenarios, other types of transistors, such as, e.g., an N-type transistor, may be used.

As shown inFIG. 1B, the second transistor T2and the third transistor T3may be coupled together and arranged to operate in parallel as a pass gate pair based on the first enable signal gtp and the second enable signal ngtp, respectively. The second transistor T2and the third transistor T3may be disposed between the first transistor T1and the first dummy bitline circuitry102A. The pass gate pair of the second transistor T2and the third transistor T3may be coupled between the first transistor T1and the first dummy bitline circuitry102A.

The dummy bitline (DBL) circuitry120may use one or more dummy bitline loads104that are coupled to the first dummy bitline circuitry102A. In some instances, as shown, one or more of the dummy bitline loads104may be referred to as active pulldown devices104A, such as, e.g., as shown with a shaded block. In other instances, as shown, one or more of the dummy bitline loads104may be referred to as non-active pulldown devices, such as, e.g., as shown with a white block. Further, at least one of the dummy bitline loads104may be referred to as an edge cell for the dummy load104B.

The dummy bitline (DBL) circuitry120may include dummy wordline driver circuitry108that is coupled to the first dummy bitline circuitry102A at node n1and the second dummy bitline circuitry102B at node n1. The dummy wordline driver circuitry108may be coupled to the multiple dummy bitline loads104via the first dummy bitline circuitry102A at node n1, and the dummy wordline driver circuitry108may be coupled to the decoupling circuitry106via the second dummy bitline circuitry102B at node n1.

In some implementations, the dummy wordline driver circuitry108may include one or more transistors, such as, e.g., a fourth transistor T4(PMOS) and a fifth transistor T5(NMOS) that may be coupled together and arranged to operate in series as an inverter or buffer to drive the first dummy bitline dbl based on an activation signal dwl_turn. In some instances, as shown, the transistors T4, T5may be referred to as logic pulldown devices as part of the logic pulldown circuitry110.

As shown inFIG. 2, the dummy bitline (DBL) circuitry200represents modified dummy bitline (DBL) circuitry120that removes node n1and re-routes the coupling of the dummy wordline driver circuitry108to the first and second dummy bitline circuitry102A,102B via the pass gate pair of the second and third transistors T2, T3. As shown, the first dummy bitline circuitry102A may be coupled to the second dummy bitline circuitry102B at node n2, and in this instance, the dummy bitline loads104may also be coupled to the decoupling circuitry106at node n2. Further, the dummy wordline driver circuitry108may be coupled to the decoupling circuitry106at node n3.

As shown, the node n2is disposed between the first transistor T1and the pass gate pair of the second transistor T2and the third transistor T3. In addition, the dummy wordline driver circuitry108may be coupled to the multiple dummy bitline loads104via the decoupling circuitry106at node n3and the first dummy bitline circuitry102A at node n2. Further, the dummy wordline driver circuitry108may be coupled to the decoupling circuitry106at node n3via the second dummy bitline circuitry102B.

FIGS. 3A-3Billustrate various other schematic diagrams of dummy bitline (DBL) circuitry in accordance with implementations described herein. In particular,FIG. 3Ashows a schematic diagram of dummy bitline (DBL) circuitry300A, andFIG. 3Bshows a schematic diagram of dummy bitline (DBL) circuitry300B.

As shown inFIG. 3A, the dummy bitline (DBL) circuitry300A may include the first dummy bitline circuitry102A having the charge storage element Cdbl and the one or more dummy bitline loads104. In some instances, the charge storage element Cdbl may be embodied as a bitline capacitor.

The dummy bitline (DBL) circuitry300A may include the second dummy bitline circuitry102B with the dummy wordline driver circuitry108. The dummy bitline (DBL) circuitry300A may include the decoupling circuitry106, which is coupled between the first dummy bitline circuitry102A and the second dummy bitline circuitry102B.

The decoupling circuitry106may operate to decouple the charge storage element Cdbl from the second dummy bitline circuitry102B based on the one or more enable signals gtp, ngtp. In some instances, the decoupling circuitry106may operate to decouple the charge storage element Cdbl from the dummy wordline driver circuitry108based on the one or more enable signals gtp, ngtp. As described herein, the one or more enable signals may include multiple enable signals including the first enable signal gtp and the second enable signal ngtp that is a complement of the first enable signal gtp. The decoupling circuitry106may operate to decouple the charge storage element Cdbl from the second dummy bitline circuitry102B (and/or the dummy wordline driver circuitry108) based on the first enable signal gtp and the second enable signal ngtp.

As further shown inFIG. 3A, the first transistor T1may be activated based on the first enable signal gtp. The decoupling circuitry106may include the second transistor T2that may be activated based on the first enable signal gtp. The decoupling circuitry106may also include the third transistor T3that is activated based on the second enable signal ngtp, which is the complement of the first enable signal gtp. The second transistor T2and the third transistor T3may be coupled together and arranged to operate in parallel as a pass gate pair based on the first enable signal gtp and the second enable signal ngtp, respectively.

In some instances, as shown inFIG. 3A, the first transistor T1may be disposed between the multiple dummy bitline loads104and the pass gate pair of the second transistor T2and the third transistor T3. Further, as shown inFIG. 3A, the first transistor T1is coupled to the first dummy bitline circuitry102A between the multiple dummy bitline loads104and the pass gate pair of the second transistor T2and the third transistor T3. In some instances, as shown, one or more of the dummy bitline loads104may be referred to as active pulldown devices104A, such as, e.g., as shown with a shaded block. In other instances, as shown, one or more of the dummy bitline loads104may be referred to as non-active pulldown devices, such as, e.g., as shown with a white block. Further, at least one of the dummy bitline loads104may be referred to as an edge cell for the dummy load104B.

In other instances, as shown inFIG. 3B, the multiple dummy bitline loads104may be disposed between the first transistor T1and the pass gate pair of the second transistor T2and the third transistor T3. Further, as shown inFIG. 3B, the one or more dummy bitline loads104are coupled to the first dummy bitline circuitry102A between the first transistor T1and the pass gate pair of the second transistor T2and the third transistor T3. In some instances, as shown, one or more of the dummy bitline loads104may be referred to as active pulldown devices104A, such as, e.g., as shown with a shaded block. In other instances, as shown, one or more of the dummy bitline loads104may be referred to as non-active pulldown devices, such as, e.g., as shown with a white block. Further, at least one of the dummy bitline loads104may be referred to as an edge cell for the dummy load104B.

Some advantages achieved with the various implementations described herein may include optimizing the dummy bitline (dbl) precharge cycle-time component without impacting the operating clock (CLK). Another advantage may include providing a generic scheme and/or technique that may be implemented in any configuration. Further, another advantage may include matching the dbl capacitor with the main bitline by decoupling the additional dbl_extra capacitor from the dummy bitline (dbl).

FIG. 4illustrates a process flow diagram of a method400for fabricating DBL circuitry in accordance with implementations described herein.

It should be understood that even though method400may indicate a particular order of operation execution, in some cases, various certain portions of the operations may be executed in a different order, and on different systems. In other cases, additional operations and/or steps may be added to and/or omitted from method400. Also, method400may be implemented in hardware and/or software. If implemented in hardware, the method400may be implemented with various circuit elements, such as described herein above in reference toFIGS. 1A-2. If implemented in software, method400may be implemented as a program or software instruction process that may be configured for dummy bitline (DBL) circuitry as described herein. Further, if implemented in software, instructions related to implementing the method400may be stored in memory and/or a database. For instance, a computer or various other types of computing devices having a processor and memory may be configured to perform method400.

As described and shown in reference toFIG. 4, method400may be utilized for manufacturing an IC that implements dummy bitline (DBL) circuitry in various types of memory applications. For instance, method400may be utilized for manufacturing DBL circuitry for memory applications, wherein the DBL circuitry may be adaptive to pressure, voltage and temperature (PVT).

At block410, method400may fabricate first dummy bitline circuitry having a first charge storage element, such as, e.g., a first bitline capacitor. At block420, method400may fabricate second dummy bitline circuitry coupled to the first dummy bitline circuitry, wherein the second dummy bitline circuitry includes a second charge storage element, such as, e.g., a second bitline capacitor.

At block430, method400may fabricate fabricating decoupling circuitry coupled to the first dummy bitline circuitry and the second dummy bitline circuitry between the first charge storage element (e.g., the first capacitor) and the second charge storage element (e.g., the second capacitor). The decoupling circuitry may operate to decouple the second charge storage element (e.g., the second capacitor) from the first charge storage element (e.g., the first capacitor) based on one or more enable signals.

FIG. 5illustrates a process flow diagram of another method500for fabricating DBL circuitry in accordance with implementations described herein.

It should be understood that even though method500may indicate a particular order of operation execution, in some cases, various certain portions of the operations may be executed in a different order, and on different systems. In other cases, additional operations and/or steps may be added to and/or omitted from method500. Also, method500may be implemented in hardware and/or software. If implemented in hardware, the method500may be implemented with various circuit elements, such as described herein above in reference toFIGS. 3A-3B. If implemented in software, method500may be implemented as a program or software instruction process that may be configured for dummy bitline (DBL) circuitry as described herein. Further, if implemented in software, instructions related to implementing the method500may be stored in memory and/or a database. For instance, a computer or various other types of computing devices having a processor and memory may be configured to perform method500.

As described and shown in reference toFIG. 5, method500may be utilized for manufacturing an IC that implements dummy bitline (DBL) circuitry in various types of memory applications. For instance, method500may be utilized for manufacturing DBL circuitry for memory applications, wherein the DBL circuitry may be adaptive to pressure, voltage and temperature (PVT).

At block510, method500may fabricate first dummy bitline circuitry having a charge storage element (e.g., a bitline capacitor) and multiple dummy bitline loads. At block520, method500may fabricate second dummy bitline circuitry having dummy wordline driver circuitry.

At block530, method500may fabricate decoupling circuitry coupled between the first dummy bitline circuitry and the second dummy bitline circuitry. The decoupling circuitry may operate to decouple the charge storage element (e.g., the bitline capacitor) from the second dummy bitline circuitry based on one or more enable signals.

Described herein are various implementations of an integrated circuit. The integrated circuit may include first dummy bitline circuitry having a first charge storage element. The integrated circuit may include second dummy bitline circuitry coupled to the first dummy bitline circuitry, and the second dummy bitline circuitry has a second charge storage element. The integrated circuit may include decoupling circuitry coupled to the first dummy bitline circuitry and the second dummy bitline circuitry between the first charge storage element and the second charge storage element. The decoupling circuitry may operate to decouple the second charge storage element from the first charge storage element based on an enable signal.

Described herein are various implementations of an integrated circuit. The integrated circuit may include first dummy bitline circuitry with a charge storage element and multiple dummy bitline loads. The integrated circuit may include second dummy bitline circuitry having dummy wordline driver circuitry. The integrated circuit may include decoupling circuitry coupled between the first dummy bitline circuitry and the second dummy bitline circuitry. The decoupling circuitry may operate to decouple the charge storage element from the second dummy bitline circuitry based on an enable signal.

Described herein are various implementations of a method for manufacturing an integrated circuit. The method may include fabricating first dummy bitline circuitry with a first capacitor. The method may include fabricating second dummy bitline circuitry coupled to the first dummy bitline circuitry, and the second dummy bitline circuitry has a second capacitor. The method may include fabricating decoupling circuitry coupled to the first dummy bitline circuitry and the second dummy bitline circuitry between the first charge storage element and the second charge storage element. The decoupling circuitry may operate to decouple the second charge storage element from the first charge storage element based on one or more enable signals.

It should be intended that the subject matter of the claims not be limited to the implementations and illustrations provided herein, but include modified forms of those implementations including portions of implementations and combinations of elements of different implementations in accordance with the claims. It should be appreciated that in the development of any such implementation, as in any engineering or design project, numerous implementation-specific decisions should be made to achieve developers' specific goals, such as compliance with system-related and business related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort may be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having benefit of this disclosure.

Reference has been made in detail to various implementations, examples of which are illustrated in the accompanying drawings and figures. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the disclosure provided herein. However, the disclosure provided herein may be practiced without these specific details. In some other instances, well-known methods, procedures, components, circuits and networks have not been described in detail so as not to unnecessarily obscure details of the embodiments.

While the foregoing is directed to implementations of various techniques described herein, other and further implementations may be devised in accordance with the disclosure herein, which may be determined by the claims that follow.