In-memory arithmetic processors for the “n-bit” by “n-bit” multiplication, the “n-bit” by “n-bit” addition, and the “n-bit” by “n-bit” subtraction operations are disclosed. The in-memory arithmetic processors of the invention can obtain the operational resultant integer in the binary format for two inputted integers represented by two “n-bit” binary codes in one-step processing with no sequential multiple-step operations as for the conventional arithmetic binary processors. The in-memory arithmetic processors are implemented by a 2-dimensional memory array with X and Y decoding for the two inputted operational integers in the arithmetic binary operations.

BACKGROUND OF THE INVENTION

Field of the Invention

The invention is related to innovative arithmetic memory processors with no computing iterations. In particular, the in-memory arithmetic processors process binary numbers in one-step with the built-in arithmetical tables with no multiple-steps of binary code manipulations. The processing efficiencies of the in-memory arithmetic processors are dramatically improved in terms of data traffics and power consumptions. The in-memory arithmetic processors can be implemented by semiconductor memory arrays for the compactness in IC (Integrated Circuit) chip.

Description of the Related Art

In the modern Von Neumann computing architecture as shown inFIG.1, the Central Process Unit (CPU)10executes logic operations according to the instructions and data from the main memory. The CPU10includes a main memory11, an arithmetic and logic unit12, input/output equipment13and a program control unit14. Prior to the computation process, the CPU10is set by the program control unit12to point to the initial address code for the initial instruction in the main memory. The digital data are then processed with the arithmetic and logic unit12according to the sequential instructions in the main memory11accessed by the clock-synchronized address pointer in the program control unit12. In general, the digital logic computation process for the CPU10is synchronously executed and driven by a set of pre-written sequential instructions stored in the memory.

In Von Neumann computer systems, the numbers are represented in the binary formats. For example, an integer number I in the n-bit format is given by
I=bn−12n−1+bn−22n−2+ . . . +b121+b0:=(bn−1bn−2. . . b1b0),
where bi=[0, 1] for i=0, . . . , (n−1).

The arithmetic operations such as multiplication, addition, subtraction, and division for integer numbers require manipulating the binary strings of the operant binary integer numbers to obtain the correct representation of the resultant binary integer number. The manipulations of the binary strings include feeding into the various combinational logic gates and placing bits in the correct positions of the registers in IC chips. The binary codes for the integer numbers stored in data memory units moving in and out of the various logic units and binary registers are controlled by the sequential instructions also in the format of binary codes stored in instruction memory unit for the whole arithmetic computation process. Usually the more manipulation steps to move the inputted binary data strings in-out of various memory units and registers, and combinational logic units through their connecting bus-lines for the resultant binary string the more computing power is consumed. Specially, when the computing processor comes down to the single-bit level of manipulations of data strings, the power consumptions from the charging and discharging the capacitances of bus-lines, logic gates, and the gates of registers and memories will significantly increase with the increasing steps of operations as the power P˜f*C*VDD2, where f is a clock cycle, C is the total charging/discharging capacitances for the computing process, and VDDis the high voltage supply. For example, the multiplication for two n-bit strings are usually done by the so-called bit multiply-accumulation sequence: starting with each single-bit of one n-bit operand multiplying (AND operation) the other n-bit operand to obtain the “n” n-bit strings; shifting the “n” n-bit strings into the correct positions of the “n” rows of 2n-bit long registers; filling the empty registers in the 2n-bit long registers with zeros; operating the “n” steps of additions (2n-bit string additions) for the “n” 2n-bit long strings to obtain the resultant binary 2n-bit string. The tedious steps of bit-level manipulations increase the loading of computing processors. The heavy traffics of the data strings moving in and out of the memory units, logic gates, and registers may also create the bus-line congestions for the computation-intensive processors. The so-called Von-Neumann bottle-neck due to the bus-line congestions of heavy data traffics is the main reason for slowing down the computation efficiency. Meanwhile, due to the more operational steps to complete the computations, the more memory storage spaces for the instruction codes are required for the computing process.

In this invention, we apply the arithmetic tables to eliminate the tedious bit-level manipulation steps into one-step bit-string processing to improve the computation efficiency and to save the computing power. It is similar to a human to improve his/her arithmetic capability by memorizing the multiplication table, the addition table, and the subtraction table in the familiar decimal format as respectively shown inFIGS.2,3, and4. To implement the arithmetic tables in silicon hardware, we store the resultant binary codes from the arithmetic tables in memory arrays according to the arithmetic table values. For performing the block computations from the memory arrays, we apply the two-dimensional array operations for the two-variable inputs by pointing to the correspondent row and column cell in the memory array to output the resultant binary code in response to the row and column cell of the arithmetic tables.

SUMMARY OF THE INVENTION

FIG.5shows the n-bit by n-bit multiplication table with 2n*2ntable cells. Each cell in the table contains an integer number in the decimal format (upper) and the binary format (lower). The cells in first row from the top of the n-bit by n-bit multiplication table are filled with the sequential integer number indexes starting from 0, 1, 2, . . . , (2n−1−1), . . . , (2n−2), to (2n−1), that is, A: 0/(00..00..00b), 1/(00..00..01b), 2/(00..00..10b), . . . , (2n−1−1)/(01..11..11 b), . . . , (2n−2)/(11..11..10b), (2n−1)/(11..11..11b) for the first row of cells. The cells in first column from the left of the n-bit by n-bit multiplication table are filled with the sequential integer number indexes starting from 0, 1, 2, . . . , (2n−1−1), . . . , (2n−2), to (2n−1), that is, B: 0/(00..00..00b), 1/(00..00..01b), 2/(00..00..10b), . . . , (2n−1−1)/(01..11..11b), . . . , (2n−2)/(11..11..10b), (2n−1)/(11..11..11b) for the first column of cells. The multiplication number C=A*B=(p−2)*(q−2), as written in the decimal format/binary format: (p*q−2*p−2*q+4)/(xx..xx..xx xx..xx..xxb), are filled in the pth-column and qth-row cell, for p, q=[2, 3, 4, . . . , 2n+1]. Note that the multiplication of two “n-bit” integers obtains the resultant integer number with 2n-bit long. For example, for the second column A=0 and the third row B=1, the multiplication number C=A*B=0*1=0 with its 2n-bit representation: (00..00..00 00..00..00b), as written in 0/(00..00..00 00..00..00b), are filled in the second column and third row cell. For the A=(2n−1) and B=(2n−1−1), the multiplication number C=A*B=(2n−1)*(2n−1−1)=(22n−2n−2n−1+1) and its 2n-bit representation: (01..11..10 10..00..01b), as written in (22n−2n−2n−1+1)/(01..11..10 10..00..01b), are filled in the (2n+1)th-column and (2n−1+1)th-row cell, and so forth for the rest of other cells in the table.

FIG.6shows the n-bit by n-bit addition table with 2n*2ntable cells. Each cell in the table contains an integer number in the decimal format (upper) and the binary format (lower). The cells in first row from the top of the n-bit by n-bit addition table are filled with the sequential integer number indexes starting from 0, 1, 2, . . . , (2n−1−1), . . . , (2n−2), to (2n−1), that is, A: 0/(00..00..00b), 1/(00..00..01b), 2/(00..00..10b), . . . , (2n−1−1)/(01..11..11b), . . . , (2n−2)/(11..11..10b), (2n−1)/(11..11..11b) for the first row of cells. The cells in first column from the left of the n-bit by n-bit addition table are filled with the sequential integer number indexes starting from 0, 1, 2, . . . , (2n−1−1), . . . , (2n−2), to (2n−1), that is, B: 0/(00..00..00b), 1/(00..00..01b), 2/(00..00..10b), . . . , 2n−1−1/(01..11..11b), . . . , (2n−2)/(11..11..10b), (2n−1)/(11..11..11b) for the first column of cells. The addition number C=A+B=(p−2)+(q−2) as written in the decimal format/binary format: (p+q−4)/(x xx..xx..xxb), are filled in the pth-column and qth-row cell, for p, q=[2, 3, 4, . . . , 2n+1]. Note that the “n+1”-bit representation includes an extra carry-over bit on the left for the two “n-bit” integer addition. For example, for the second column A=0 and the third row B=1, the addition number C=A+B=0+1=1 with its “n+1”-bit representation: 1/(0 00..00..01b) are filled in the second-column and third-row cell. For the A=(2n−1) and B=(2n−1−1), the addition number C=A+B=(2n−1)+(2n−1−1)=(2n−2n−1−2) with its “n+1”-bit representation: (2n−2n−1−2)/(1 01..11..10b), are filled in the (2n+1)th-column and (2n−1+1)th-row cell, and so forth for the rest of other cells in the table.

FIG.7shows the n-bit by n-bit subtraction table with 2n*2ntable cells. Each cell in the table contains an integer number (upper) in the decimal format and the binary format (lower). The cells in first row from the top of the n-bit by n-bit subtraction table are filled with the sequential integer number indexes starting from 0, 1, 2, . . . , (2n−1−1), . . . , (2n−2), to (2n−1), that is, A: 0/(00..00..00b), 1/(00..00..01b), 2/(00..00..10b), . . . , (2n−1−1)/(01..11..11b), . . . , (2n−2)/(11..11..10b), (2n−1)/(11..11..11b) for the first row of cells. The cells in first column from the left of the n-bit by n-bit subtraction table are filled with the sequential integer number indexes starting from 0, 1, 2, . . . , (2n−1−1), . . . , (2n−2), (2n−1), that is, B: 0/(00..00..00b), 1/(00..00..01b), 2/(00..00..10b), . . . , (2n−1−1)/(01..11..11b), . . . , (2n−2)/(11..11..10b), (2n−1)/(11..11..11b) for the first column of cells. The subtraction number C=A−B=(p−2)−(q−2) as written in the decimal format/binary format: (p−q)/(x xx..xx..xxb), are filled in the pth-column and qth-row cell, for p, q=[2, 3, 4, . . . , 2n+1]. Note that a “n+1”-bit representation includes a “sign” bit on the left defined as “1” negative and “0” positive for the two “n-bit” integer subtraction. For example, for the second column A=0 and the third row B=1, the subtraction number C=A−B=0−1=−1 with its “n+1”-bit representation: (−1)/(1 00..00..01b) are filled in the second-column and third-row cell. For the A=2n−1 and B=2n−1−1, the subtraction number C=A−B=(2n−1)−(2n−1−1)=(2n−2n−1) with its “n+1”-bit representation: (2n−2n−1)/(0 10..00..00b), are filled in the (2n+1)th-column and (2n−1+1)th-row cell, and so forth for the rest of other cells in the table.

To implement the binary arithmetic tables (multiplication, addition, and subtraction inFIGS.5,6, and7) in silicon hardware, an in-memory arithmetic processor800of the invention includes an n-bit “B” register810, an n-bit “A” register820, two n-bit decoders811and821, a Wordline Driver812, a Y-Switch Driver822, a memory array850, a Y-Switch830, and an m-bit Output “C” register840as the schematics shown inFIG.8.

For any two n-bit inputted integers A=an−1an−2..ai..a1a0b (binary) and B=bn−1bn−2..bi..b1b0b (binary), for each ai, bj=[0,1] the voltage signals, VDDfor “1” and VSSfor “0”, from the n-bit “A” register820and the n-bit “B” register810are simultaneously fed into the n-bit decoder821and the n-bit decoder811, respectively. The n-bit decoders821and811decode to activate the high voltage signal VDDon the only selected YSinode and the only selected XSjnode for i, j=[0,1, . . . , 2n−1] according to the inputted codes A and B. The voltage signal VDDon the selected YSinode and the voltage signal VDDon the selected XSjnode through the Y-Switch Driver822and the Wordline Driver812are respectively applied to drive the selected Y-switch BSiand the selected wordline Wj. The activated wordline Wjis then applied to jthrow so as to turn on the entire jthrow of 2ncells for accessing the codes stored in the entire jthrow of 2ncells in the memory array850; since the other wordlines are deactivated, the cells in the other rows of the memory array850are turned off. Meanwhile by connecting bitlines85BL to the Y-Switch830, the selected bitline switch BSiis only activated to pass the voltage signals of the ithcolumn cell in the entire jthrow cells in the memory array850through the cell bus-lines83BL to the m-bit Output “C” register840; since the other bitline switches are deactivated, the voltage signals of the cells in other columns in the jthrow of the memory array850are forbidden to pass. The m-bit Output “C” register840is used to temporarily store a m-bit code pre-stored in the ithcolumn cell in the jthrow cells in the memory array850.

For the case of two n-bit multiplication, we apply the n-bit by n-bit multiplication table inFIG.5for the resultant codes stored in each memory cell85ij. Each memory cell85ijfor the n-bit by n-bit multiplication stores the 2n-bit long resultant code according to the binary code of the correspondent (i+2)th-column and (j+2)th-row cell in the n-bit by n-bit multiplication table inFIG.5. Note that the number m=2*n for the two n-bit multiplication in the m-bit Output “C” register840is shown inFIG.8.

For the case of two n-bit addition, we apply the n-bit by n-bit addition table inFIG.6for the resultant codes stored in the memory cell85ij. Each memory cell85ijfor the n-bit by n-bit addition stores the (n+1)-bit long resultant code (including a carry-over bit) according to the binary code of the correspondent (i+2)th-column and (j+2)th-row cell in the n-bit by n-bit addition table inFIG.6. Note that the number m=n+1 for the two n-bit addition in the m-bit Output “C” register840is shown inFIG.8.

For the case of two n-bit subtraction, we apply the n-bit by n-bit subtraction table inFIG.7for the resultant codes stored in the memory cell85ij. Each memory cell85ijfor the n-bit by n-bit subtraction stores an (n+1)-bit long resultant codes (including a “sign” bit) according to the binary code of the correspondent (i+2)th-column and (j+2)th-row cell in the n-bit by n-bit subtraction table inFIG.7. Note that the number m=n+1 for the two n-bit subtraction in the m-bit Output “C” register840is shown inFIG.8.

DETAILED DESCRIPTION OF THE INVENTION

The following detailed description is meant to be illustrative only and not limiting. It is to be understood that other embodiment may be utilized and element changes may be made without departing from the scope of the present invention. Also, it is to be understood that the phraseology and terminology used herein are for the purpose of description and should not be regarded as limiting. Those of ordinary skill in the art will immediately realize that the embodiments of the present invention described herein in the context of methods and schematics are illustrative only and are not intended to be in any way limiting. Other embodiments of the present invention will readily suggest themselves to such skilled persons having the benefits of this disclosure.

To illustrate the main idea of the in-memory arithmetic processors800, we apply a Read Only Memory (ROM) array for implementing the arithmetic tables in IC chips. Although the embodiment of the memory array850is described in terms of a ROM array, it should be understood that embodiments of the memory array850are not so limited, but are applicable to other types of memory arrays such as SRAM arrays, DRAM arrays, and Non-volatile RAM arrays.

In the embodiment, the schematic of the ROM array850including the cells900of the arithmetic table is shown inFIG.9. The ROM array850includes 2n-column by 2n-row arithmetic table cells900. Each arithmetic table cell900is represented by a row of “m” ROM cells910for storing the “m-bit” of resultant codes. Each ROM cell910comprises an N-type Metal Oxide Semiconductor Field Effect Transistor (NMOSFET) device915, and two vertical metal lines920and930for applying digital voltages VSSand VDD, and one vertical output metal bitline940. The source electrodes903of “m” NMOSFET devices915in the row are connected to their vertical bitlines940, respectively. The gates901of the row of the NMOSFET devices915are connected to form a horizontal wordline Wj950. The drain electrode902of NMOSFET device915is connected to either cell's VSSline920for “0” or Cell's VDDline930for “1” in each ROM cell910by a metal contact911. For example, the row of the “m-bit” ROM cells910represents the binary code of (01 . . . 00 . . . 11 b) as illustrated inFIG.9. When a wordline Wj950of the ROM cells910is activated “high”, the voltage signals of the entire row j of binary codes for 2nsets of m-bit codes pass to the 2nsets of “m” bitlines in the memory cell850.

Meanwhile the Y-Switch830comprises “2n” sets of switches110as shown inFIG.10. InFIG.10, each set of switches110comprises “m” NMOSFET devices. The gates of the “m” NMOSFET devices of each switch set110are connected to form a bitline switch BSi, which is connected to the Y-Switch Driver822for i=0, 1, . . . , (2n−1) as shown inFIG.8. When one of the bitline switches BSiis activated, a corresponding set of the “m” NMOSFET devices is turned on to connect a corresponding set of bitlines85BL to the output bitlines83BL to pass the resultant “m-bit” code Cijstored in the (i+1)thcolumn and (j+1)throw cell of the memory array850for i, j=0, 1, 2, . . . , (2n−1). Since the schematics and the operations of the registers810/820for bit-storage, the bit decoders811/821, the wordline driver812and the Y-switch driver822are well known to the people skilled in the art, we will not address in many details.

For the illustration purpose of using the conventional hexadecimal format, we will apply the 4-bit by 4-bit arithmetic operations for the embodiments (n=4). However, the numbers of bits for the arithmetic operation can be any integer number greater than 1. For the 4-bit by 4-bit multiplication, the resultant integer in the decimal format (upper) and its 8-bit representation in the hexadecimal format (lower) in each arithmetic table cell are shown inFIG.11. According to the schematic inFIG.8, we have the 4-bit decoder821decoding the 4-bit code A for the bitline switches of sixteen columns in the Y-switch830and the 4-bit decoder811decoding 4-bit code B for switching the wordlines of sixteen rows in the ROM array850, and 16*16*8 ROM cells910of the ROM array850. Every eight ROM cells910(m=8) in a row as illustrated inFIG.9stores the resultant 8-bit code C for the correspondent table cell of the 4-bit by 4-bit multiplication table inFIG.11. Note the 8-bit code C represented in the hexadecimal format in the memory cell85ijis implemented by connecting one of VDDfor “1 s” and VSSfor “0s” to the drain electrode902of NMOSFET device915by a metal contact911in each individual ROM cell910shown inFIG.9. For example, 2*3=6=(06h)=(0000 0110b) connects the voltage biases (VSSVSSVSSVSSVSSVDDVDDVSS) to the drain electrodes902of each NMOSFET devices915by metal contacts911in the eight ROM cells910from the left to right for the correspondent memory cell85ijfor i, j=2, 3 (according to the binary code of the correspondent 4th-column and 5th-row cell in the 4-bit by 4-bit multiplication table inFIG.11); 7*15=105=(69h)=(0110 1001 b) connects the voltage biases (VSSVDDVDDVSSVDDVSSVSSVDD) to the drain electrodes902of each NMOSFET devices915by metal contacts911in the 8 ROM cells910from the left to right for the correspondent memory cell85ijfor i, j=7, 15 (according to the binary code of the correspondent 9th-column and 17th-row cell in the 4-bit by 4-bit multiplication table inFIG.11); 15*15=225=(e1h)=(1110 0001b) connects the voltage biases (VDDVDDVDDVSSVSSVSSVSSVDD) to the drain electrodes902of NMOSFET devices915by metal contacts911in the eight ROM cells910from the left to right for the correspondent memory cell85ijfor i, j=15, 15 (according to the binary code of the correspondent 17th-column and 17th-row cell in the 4-bit by 4-bit multiplication table inFIG.11), and so forth for the rest of ROM cells910.

For the 4-bit by 4-bit addition, the resultant integer in the decimal format (upper) and its 5-bit representation (m=5) in the binary format (lower) in each table cell are shown inFIG.12. According to the schematic inFIG.8, we have the 4-bit decoder821decoding the 4-bit code A for the bitline switches of sixteen columns in the Y-switch830and the 4-bit decoder811decoding the 4-bit code B for switching the wordlines of sixteen rows in the ROM array850and 16*16*5 ROM cells910of the ROM array850. Every five ROM cells910in a row as illustrated inFIG.9stores the resultant 5-bit code C including a “carry-over bit” for the correspondent table cell of the 4-bit by 4-bit addition table inFIG.12. Note the 5-bit code C represented in the binary format in the memory cell85ijis implemented by connecting either VDDfor “1 s” or VSSfor “0s” to the drain electrodes902of NMOSFET devices915by metal contacts911in the ROM cells910shown inFIG.9. For example, 2+3=5=(0 0101b) connects the voltage biases (VSSVSSVDDVSSVDD) to the electrodes902of NMOSFET devices915by metal contacts911in the five ROM cells from the left to right for the correspondent memory cell85ijfor i, j=2, 3 (according to the binary code of the correspondent 4th-column and 5th-row cell in the 4-bit by 4-bit addition table inFIG.12); 7+15=12=(0 1100b) connects the voltage biases (VSSVDDVDDVSSVSS) to the drain electrodes902of NMOSFET devices915in the five ROM cells from the left to right for the correspondent memory cell85ijfor i, j=7, 15 (according to the binary code of the correspondent 9th-column and 17th-row cell in the 4-bit by 4-bit addition table inFIG.12); 15+15=30=(1 1110b) connects the voltage biases (VSSVDDVDDVSSVSS) to the drain electrodes902of NMOSFET devices915by metal contacts911in the five ROM cells910from the left to right for the correspondent memory cell85ijfor i, j=15, 15 (according to the binary code of the correspondent 17th-column and 17th-row cell in the 4-bit by 4-bit addition table inFIG.12), and so forth for the rest of ROM cells910.

For the 4-bit by 4-bit subtraction, the resultant integer in the decimal format (upper) and its 5-bit representation (m=5) in the binary format in each table cell are shown inFIG.13. According to the schematic inFIG.8, we have the 4-bit decoder821decoding the 4-bit code A for the bitline switches of sixteen columns in the Y-switch830and the 4-bit decoder811decoding 4-bit code B for switching the wordlines of sixteen rows in the ROM array850, and 16*16*5 ROM cells910of the ROM array850. Every five ROM cells910in a row as illustrated inFIG.9stores the resultant 5-bit code C including a “sign” bit for the correspondent table cell of the 4-bit by 4-bit addition table inFIG.13. Note the 5-bit code C represented in the binary format in the memory cell85ijis implemented by connecting either VDDfor “1 s” or VSSfor “0s” to the drain electrodes902of NMOSFET devices915by metal contacts911in the ROM cells910shown inFIG.9. For example, 2−3=−1=(1 0001b) connects the voltage biases (VDDVSSVSSVSSVDD) to the electrodes902of NMOSFET devices915by metal contacts911in the five ROM cells from the left to right for the correspondent memory cell85ijfor i, j=2, 3 (according to the binary code of the correspondent 4th-column and 5th-row cell in the 4-bit by 4-bit subtraction table inFIG.13); 15-7=8=(0 1000b) connects the voltage biases (VSSVDDVSSVSSVSS) to the electrodes902of NMOSFET devices915by metal contacts911in the five ROM memory cells from the left to right for the correspondent memory cell85ijfor i, j=15, 7 (according to the binary code of the correspondent 17th-column and 9th-row cell in the 4-bit by 4-bit subtraction table inFIG.13); 15-15=30=(0 0000b) connects the voltage biases (VSSVSSVSSVSSVSS) to the electrodes902of NMOSFET devices915by metal contacts911in the five ROM memory cells from the left to right for the correspondent memory cell85ijfor i, j=15, 15 (according to the binary code of the correspondent 17th-column and 17th-row cell in the 4-bit by 4-bit subtraction table inFIG.13).

The aforementioned description of the preferred embodiments of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form or to exemplary embodiment disclosed. Accordingly, the description should be regarded as illustrative rather than restrictive. The embodiment is chosen and described in order to best explain the principles of the invention and its best mode practical application, thereby to enable persons skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use or implementation contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents in which all terms are meant in their broadest reasonable sense unless otherwise indicated. The abstract of the disclosure is provided to comply with the rules requiring an abstract, which will allow a searcher to quickly ascertain the subject matter of the technical disclosure of any patent issued from this disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Any advantages and benefits described may not apply to all embodiments of the invention. It should be appreciated that variations may be made in the embodiments described by persons skilled in the art without departing from the scope of the present invention as defined by the following claims. Moreover, no element and component in the present disclosure is intended to be dedicated to the public regardless of whether the element or component is explicitly recited in the following claims.