METHODS OF MANUFACTURING SEMICONDUCTOR STRUCTURE

Disclosed is a method of manufacturing a semiconductor structure, including: providing a silicon substrate (10), epitaxially growing a functional layer (11) on an upper surface of the silicon substrate, where a material of the functional layer includes a group-III-nitride-based material; implanting ions into an interface between the upper surface of silicon substrate and the functional layer to introduce defects to the interface; or implanting, before epitaxially growing the functional layer, ions to the upper surface of the silicon substrate to introduce defects to the interface.

TECHNICAL FIELD

The present disclosure relates to the field of semiconductor, and in particular, to methods of manufacturing a semiconductor structure.

BACKGROUND

Wide-bandgap semiconductor materials, group III nitrides, as a typical representative of the third-generation semiconductor materials, have excellent characteristics of large wide-bandgap, high pressure resistance, high temperature resistance, high electron saturation velocity and drift velocity, and easy formation of high-quality heterostructures. The wide-bandgap semiconductor materials are ideal for manufacturing high temperature, high frequency, high power electronic devices.

For example, AlGaN/GaN heterojunction has a high concentration of two-dimensional electron gas (2 DEG) at an interface between AlGaN and GaN due to its strong spontaneous polarization and piezoelectric polarization, and AlGaN/GaN heterojunction is widely applied in semiconductor structures such as high electron mobility transistors (HEMTs).

Resistance at an interface between silicon substrate and GaN epitaxial layer is very low due to ions diffusion. The interface forms a conductive layer, which causes electric leakage of a device. For radio frequency device, the conductive layer also causes radio frequency loss, thereby reducing device performance. In view of this, it is necessary to provide a new method of manufacturing a semiconductor structure to solve the above technical problems.

SUMMARY

According to the analysis of the inventor, the reason why channel current of the silicon-substrate-based semiconductor device is small and substrate heating is serious is that: at an interface between a silicon substrate and a group-III-nitride-based material, silicon atoms in the silicon substrate will diffuse to the group-III-nitride-based material, and group III atoms in the group-III-nitride-based material will diffuse to the silicon substrate, resulting in formation of a conductive layer at the interface between the silicon substrate and the group-III-nitride-based material, and the resistance of the conductive layer is very low; and the conductive layer will cause electric leakage of group-III-nitride-based material to the silicon substrate, thereby causing problems such as high radio frequency loss and low device performance of radio frequency devices.

Based on the above analysis, the purpose of the present disclosure is to improve electric leakage problem of the substrate.

In order to achieve the above purpose, the present disclosure provides a method of manufacturing a semiconductor structure, including:

providing a silicon substrate, and epitaxially growing a functional layer on an upper surface of the silicon substrate, where a material of the functional layer is a group-III-nitride-based material;

implanting ions into an interface between the silicon substrate and the functional layer to introduce defects to the interface; or implanting, before epitaxially growing the functional layer, ions into the upper surface of the silicon substrate to introduce defects to the interface.

In some embodiments, the implanted ions are group IV ions, group V ions, or group VI ions.

In some embodiments, the functional layer is a nucleation layer or a buffer layer.

In some embodiments, the functional layer includes a nucleation layer, a buffer layer and a heterojunction from bottom to top.

In some embodiments, the heterojunction includes a gate region, a source region and a drain region, where the source region and the drain region are located on both sides of the gate region, and the method further includes: forming a gate structure in the gate region, forming a source electrode in the source region, and forming a drain electrode in the drain region.

In some embodiments, the heterojunction includes a channel layer and a barrier layer from bottom to top.

In some embodiments, the heterojunction includes a gate region, a source region and a drain region, where the source region and the drain region are located on both sides of the gate region, and the method further includes: forming a gate structure in the gate region; forming a source electrode in the source region, the source electrode contacting the channel layer or the barrier layer; and forming a drain electrode in the drain region, the drain electrode contacting the channel layer or the barrier layer.

In some embodiments, the group V ions include at least one of nitrogen (N) ions, phosphorus (P) ions, arsenic (As) ions or antimony (Sb) ions.

In some embodiments, a material of the functional layer includes at least one of GaN, AlGaN, InGaN or AlInGaN.

In some embodiments, after ions implantation, annealing process is performed.

In some embodiments, a temperature of the annealing is greater than 300° C.

To facilitate the understanding of the present disclosure, all reference signs present in the present disclosure are listed below.

DETAILED DESCRIPTION OF THE EMBODIMENTS

In order to make the above-mentioned objects, features and advantages of the present disclosure more obvious and understandable, embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

FIG.1is a flowchart of a method of manufacturing a semiconductor structure according to a first embodiment of the present disclosure; andFIG.2is a schematic view illustrating an intermediate structure corresponding to the processes ofFIG.1.

First, referring to step S1inFIG.1and as shown inFIG.2, a silicon substrate10is provided, and a functional layer11is epitaxially grown on an upper surface of the silicon substrate10. A material of the functional layer11includes a group-III-nitride-based material.

A material of the silicon substrate10is monocrystalline silicon.

In this embodiment, as shown inFIG.2, the functional layer11includes a nucleation layer11a, a buffer layer11band a heterojunction13from bottom to top.

The heterojunction13can include a channel layer11cand a barrier layer11dfrom bottom to top. Two-dimensional electron gas or two-dimensional hole gas can be formed at an interface between the channel layer11cand the barrier layer11d. In some embodiments, the channel layer11cis an intrinsic GaN layer, and the barrier layer11dis an N-type AlGaN layer. In some embodiments, a material combination of the channel layer11cand the barrier layer11dcan include GaN/AlN, GaN/InN, GaN/InAlGaN, GaAs/AlGaAs, GaN/InAlN or InN/InAlN. In addition to one channel layer11cand one barrier layer11dshown inFIG.2, the channel layer11cand the barrier layer11dcan also have a plurality of layers respectively, which are alternately distributed; or there are one channel layer11cand two or more barrier layers11dto form a multi-barrier structure.

It should be noted that, in the present disclosure, a certain material is represented by a chemical element, but molar ratios of respective chemical elements in the material are not limited. For example, in GaN material, gallium (Ga) element and nitrogen (N) element are included, but molar ratios of gallium element and nitrogen element are not limited; in AlGaN material, aluminum (Al) element, gallium (Ga) element and nitrogen (N) element are included, but respective molar ratios of aluminum element, gallium element and nitrogen element are not limited.

A source region13bof the heterojunction13is used to form a source electrode14bthereon, a drain region13cof the heterojunction13is used to form a drain electrode14cthereon, and a gate region13aof the heterojunction13is used to form a gate structure14athereon.

A nucleation layer11aand a buffer layer11bare arranged from bottom to top between the heterojunction13and the substrate10.

A material of the nucleation layer11acan include, for example, AlGaN or the like. A material of the buffer layer11bincludes at least one of GaN, AlGaN, or AlInGaN. The nucleation layer11acan alleviate problems of lattice mismatch and thermal mismatch between the substrate10and the epitaxially grown semiconductor layer, such as the channel layer11cin the heterojunction13, and the buffer layer11bcan reduce a dislocation density and defect density of the epitaxially grown semiconductor layer, and improve a crystal quality.

At the interface12between the silicon substrate10and the functional layer11of the group-III-nitride-based material, silicon atoms in the silicon substrate10will diffuse to the functional layer11of the group-III-nitride-based material, and group III atoms in the functional layer11of the group-III-nitride-based material will diffuse to the silicon substrate10, resulting in the formation of a conductive layer at the interface12between the silicon substrate10and the functional layer11of the group-III-nitride-based material. When the channel of the semiconductor structure is turned on, due to the low resistance of the conductive layer, the functional layer11of the group-III-nitride-based material will electric leak electricity to the silicon substrate10.

After that, referring to step S2inFIG.1and as shown inFIG.2, ions are implanted into the interface12between the silicon substrate10and the functional layer11to introduce defects to the interface12.

The defects can capture free carriers in the conductive layer, reduce conductivity of the conductive layer, and increase resistance of the conductive layer, thereby alleviating the problem of electric leakage of functional layer11of the group-III-nitride-based material to the silicon substrate10.

The implanted ions can include group IV ions, group V ions, or group VI ions. The group V ions can include at least one of nitrogen (N) ions, phosphorus (P) ions, arsenic (As) ions, or antimony (Sb) ions. The group IV ions can include at least one of carbon (C) ions, silicon (Si) ions, germanium (Ge) ions, or tin (Sn) ions. The group VI ions can include at least one of oxygen (O) ions, sulfur (S) ions, selenium (Se) ions, or tellurium (Te) ions.

In some embodiments, after ions implantation, an annealing process can also be performed. A temperature of the annealing is greater than 300° C. Annealing can make the defect distribution uniform, which is beneficial to capture free carriers in the conductive layer.

FIG.3is a flowchart of a method of manufacturing a semiconductor structure according to a second embodiment of the present disclosure; andFIG.4toFIG.5are schematic views illustrating intermediate structures corresponding to processes ofFIG.3.

Referring toFIG.3, the method of manufacturing the semiconductor structure of the second embodiment is substantially the same as the method of manufacturing the semiconductor structure of the first embodiment, except that: at step S1′, as shown inFIG.4, a silicon substrate10is provided, and ions are implanted into an upper surface of the silicon substrate10to introduce defects to the upper surface of the silicon substrate10; at step S2′, referring toFIG.5, a functional layer11is epitaxially grown on the upper surface of the silicon substrate10, and a material of the functional layer11includes a group-III-nitrogen-based material. In other words, before epitaxially growing the functional layer11, ions are implanted into the upper surface of the silicon substrate10to introduce defects to the upper surface.

For types and functions of implanted ions, reference can be made to the types and functions of implanted ions in the first embodiment.

FIG.6is a schematic view illustrating an intermediate structure corresponding to a method of manufacturing a semiconductor structure according to a third embodiment of the present disclosure. Referring toFIG.6, the method of manufacturing the semiconductor structure of the third embodiment is substantially the same as the method of manufacturing the semiconductor structures of the first and second embodiments, except that: the method further includes: forming a gate structure14ain a gate region13a; forming a source electrode14bin the source region13b, and forming a drain electrode14cin the drain region13c.

The gate structure14aincludes a gate insulating layer and a gate electrode from bottom to top.

InFIG.6, the source electrode14band the drain electrode14care in contact with the barrier layer11d, and ohmic contacts are formed between the source electrode14band the barrier layer11d, and between the drain electrode14cand the barrier layer11d; Schottky contact is formed between the gate electrode and the barrier layer11dthrough the gate insulating layer. The source electrode14b, the drain electrode14c, and the gate electrode can include metal, such as conductive materials, for example titanium (Ti)/aluminum (Al)/nickel (Ni)/aurum (Au), nickel (Ni)/aurum (Au), and the like.

In some embodiments, ohmic contacts can be formed between the source electrode14band the barrier layer11d, and/or between the drain electrode14cand the barrier layer11dby using an N-type ion heavily doped layer. The N-type ion heavily doped layer enables the source electrode14band the source region13aof the heterojunction13, the drain electrode14cand the drain region13bof the heterojunction13to directly form an ohmic contact layer without high temperature annealing, and avoids a high temperature during the annealing process causing a performance of the heterojunction13to degrade and the electron mobility rate to decrease.

In some embodiments, at least one of the source region13bor the drain region13cof the heterojunction13can have an N-type ion heavily doped layer located thereon. The source region13bof the heterojunction13without the N-type ion heavily doped layer and the source electrode14b, or the drain region13cof the heterojunction13without the N-type ion heavily doped layer and the drain electrode14c, are annealed at high temperature to form an ohmic contact layer.

In the N-type ion heavily doped layer, the N-type ions can include at least one of silicon (Si) ions, germanium (Ge) ions, tin (Sn) ions, selenium (Se) ions or tellurium (Te) ions. For different N-type ions, a doping concentration can be greater than 1E19/cm3. The N-type ion heavily doped layer can be a group-III-nitride-based material, such as at least one of GaN, AlGaN, or AlInGaN.

In some embodiments, the gate insulating layer can also be replaced with a P-type semiconductor layer to form an enhancement mode HEMT.

FIG.7is a schematic view illustrating an intermediate structure corresponding to a method of manufacturing a semiconductor structure according to a fourth embodiment of the present disclosure. Referring toFIG.7, the method of manufacturing the semiconductor structure of the fourth embodiment is substantially the same as the method of manufacturing the semiconductor structure of the third embodiment, except that: the source electrode14band the drain electrode14care in contact with the channel layer11c, and ohmic contacts are formed between the source electrode14band the channel layer11cand between the drain electrode14cand the channel layer11c.

In some embodiments, ohmic contact can be formed between the source electrode14band the channel layer11cand between the drain electrode14cand the channel layer11cby using an N-type ion heavily doped layer.

FIG.8is a schematic view illustrating an intermediate structure corresponding to a method of manufacturing a semiconductor structure according to a fifth embodiment of the present disclosure. Referring toFIG.8, the method of manufacturing the semiconductor structure of the fifth embodiment is substantially the same as the method of manufacturing the semiconductor structure of first, second, third and fourth embodiments, except that: the functional layer11includes a nucleation layer11aand a buffer layer11bfrom bottom to top. In other words, ions implantation is performed after the buffer layer11bis formed.

In some embodiments, after ions are implanted into the upper surface of the silicon substrate10, the nucleation layer11aand the buffer layer11bcan be epitaxially grown on the upper surface of the silicon substrate10in sequence.

After that, the heterojunction13can be formed on the buffer layer11b, and the gate structure14a, the source electrode14band the drain electrode14ccan be further formed on the heterojunction13.

In some embodiments, the functional layer11can include only the buffer layer11b. In other words, the nucleation layer11ais omitted.

In some embodiments, the functional layer11can include only the nucleation layer11a. In other words, after the nucleation layer11ais formed, the ions implantation is preformed; or after ions are implanted into the upper surface of the silicon substrate10, the nucleation layer11ais epitaxially grown on the upper surface of the silicon substrate10.

After that, the buffer layer11bcan be formed on the nucleation layer11a, the heterojunction13can be formed on the buffer layer11b, and the gate structure14a, the source electrode14band the drain electrode14ccan be formed on the heterojunction13.

Compared with the related art, the present disclosure has the following beneficial effects.

1) In the method of manufacturing the semiconductor structure according to the present disclosure, ions are implanted into the interface between the silicon substrate and the group-III-nitride-based material to introduce defects into the conductive layer of the interface; or before epitaxially growing the functional layer, ions are implanted into the upper surface of the silicon substrate to introduce defects into the conductive layer of the interface, such that free carriers in the conductive layer are captured by the defects, the conductivity of the conductive layer is reduced, and the resistance of the conductive layer is increased, thereby alleviating the problem of electric leakage of substrate.

2) In an alternative solution, the functional layer of the group-III-nitride-based material includes a) a nucleation layer or a buffer layer, or b) a nucleation layer, a buffer layer and a heterojunction from bottom to top. In other words, the ions can be implanted after the nucleation layer or the buffer layer is formed, or the ions can be implanted after the heterojunction is formed.

3) In an alternative solution, an annealing step is also performed after the ions implantation. Annealing can make the defect distribution uniform, which is beneficial to capture free carriers in the conductive layer.

Although the present disclosure discloses the above contents, the present disclosure is not limited thereto. Any one of ordinary skill in the art can make various variants and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure should be set forth by the appended claims.