Operational amplifier circuit

An operational amplifier circuit has a differential input circuit including a first transistor, which receives a first input signal and generates a first voltage, and a second transistor, which receives a second input signal and generates a second voltage. An output stage circuit includes a third transistor responsive to the second voltage, a fourth transistor connected to the third transistor, a fifth transistor responsive to the first voltage, and a sixth transistor connected to the fifth transistor. The output stage circuit generates an output signal of the amplifier circuit at a first node between the fifth and sixth transistors. A seventh transistor connected between the third and fourth transistors controls the potential at a second node between the third and seventh transistors to be the same as the potential of the first input signal in correspondence with the first input signal.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2006-147469, filed on May 26, 2006, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

The present invention relates to an operational amplifier circuit.

An operational amplifier circuit is often used as a basic operation circuit in a semiconductor integrated circuit device. There is a demand for further improvement in various properties of the basic operation circuit due to the higher integration and lower power consumption of semiconductor integrated circuit devices.

Japanese Laid-Open Patent Publication No. 9-219636 discloses one example of an operational amplifier circuit. This conventional operational amplifier circuit will be described with reference toFIG. 1.

The operational amplifier circuit10includes a constant current source11, a current mirror circuit12, a differential input circuit20, and an output stage circuit30. The constant current source11supplies constant current I1to the current mirror circuit12. The current mirror circuit12includes N-channel MOS transistors N1and N2. The drain of the transistor N1is connected to the constant current source11. The sources of the transistors N1and N2are connected to a low potential power supply VS. The drain of the transistor N1is connected to the gates of the transistors N1and N2, and the drain of the transistor N2is connected to the differential input circuit20.

The differential input circuit20includes a differential pair21and a current mirror circuit22. The differential pair21includes N-channel MOS transistors N3and N4. A connection node between the sources of the two transistors N3and N4is connected to the drain of the transistor N2. The drains of the transistors N3and N4are respectively connected to the drains of P-channel MOS transistors P1and P2configuring the current mirror circuit22. The sources of the transistors P1and P2are connected to a high potential power supply VD, and the drain of the transistor P2is connected to the gates of the transistors P1and P2.

The gates of the transistors N3and N4configuring the differential pair21are respectively connected to first and second input terminals T1and T2and receive first and second input signals IP and IM, respectively. Therefore, the differential input circuit20, which is operated based on the bias current I2supplied from the transistor N2, changes the potential V1at node A between the transistors N3and P1and the potential V2at node B between the transistors N4and P2in a complementary manner by having current flow in accordance with the potential difference between the first and second input signals IP and IM.

The nodes A and B of the differential input circuit20are connected to the output stage circuit30.

The output stage circuit30includes P-channel MOS transistors P3and P4and a current mirror circuit31. The current mirror circuit31includes N-channel MOS transistors N5and N6. The gates of the transistors P3and P4are connected to the nodes B and A, respectively. Further, the node B is connected to the drain and the gate of the transistor P2. Therefore, the transistor P3and the transistor P2operate as a current mirror.

The source of the transistor P3is connected to the high potential power supply VD, and the drain is connected to the drain of the transistor N5. The transistor P4, which functions as a former transistor of a final output stage, has a source is connected to the high potential power supply VD and a drain connected to an output terminal To. Therefore, drain current I6corresponding to the gate voltage of the transistor P4is supplied to the output terminal To.

The transistor N5has the same element size as the transistor N1of the current mirror circuit12. Further, the transistor N5has a source connected to the low potential power supply VS and a drain connected to the transistor P3and the gates of the two transistors N5and N6. The transistor N6functions as a latter transistor in the final output stage. The transistor N6has a source connected to the low potential power supply VS and a drain connected to the output terminal To. The drain voltages of the two transistors P4and N6are output from the output terminal To as an output signal Vout. The transistor N6draws in drain current I7corresponding to the element size ratio of the transistor N5and the transistor N6from the output terminal To.

The operational amplifier circuit10receives the output signal Vout as the second input signal IM. That is, the second input terminal T2is connected to the output terminal To, and the operational amplifier circuit10operates as a voltage follower. The first input signal IP and the second input signal IM thus become equal when the gate voltage of the transistor P3and the gate voltage of the output transistor P4are the same, that is, when the same current is output to the nodes A and B of the current mirror circuit22configured by the transistors P1and P2.

SUMMARY OF THE INVENTION

The problems described below arise when the first input signal IP varies in the operational amplifier circuit10ofFIG. 1.

When the first input signal IP increases and becomes higher than the second input signal IM, the potential V1at the node A decreases. Decrease in the potential V1at the node A, that is, decrease in the gate voltage of the transistor P4increases the output signal Vout. As a result, the potential of the output signal Vout becomes equal to the potential of the first input signal IP. In this manner, the operational amplifier circuit10operates to shift to a state in which the first input signal IP is equal to the output signal Vout (second input signal IM).

When the output signal Vout, or the second input signal IM, increases in a manner following the first input signal IP as described above, the potential V2at the node B also decreases in the same manner as the potential V1at the node A. The drain current I5of the transistor P3varies as the potential V2at node B varies, that is, as the gate voltage of the transistor P3varies. However, the drain voltage of the transistor P3(potential V3at node C) is dependent on the drain voltage of the transistor N5that operates as a diode. The drain voltage of the transistor N5is substantially constant irrespective of the current value of the drain current I5. The drain voltage of the transistor P3thus becomes substantially constant. This results in the drain current I5being substantially constant (see single-dashed line inFIG. 4).

The drain current I6of the transistor P4decreases as the output signal Vout increases. The ratio between the drain current I5of the transistor P3and the drain current I6of the transistor P4changes from the ideal element size ratio. The transistor N6causes the flow of drain current I7having a current value corresponding to the element size ratio of the transistor N5and the transistor N6with the current mirror circuit31. The drain current I6of the transistor P4decreases as the output signal Vout increases. Thus, the supply current of the drain current I6of the transistor P4with respect to the required current value of the drain current I7of the transistor N6becomes insufficient and decreases the output signal Vout of the operational amplifier circuit10. As a result, a difference is created between the first input signal IP and the output signal Vout (second input signal IM). This generates an offset voltage. The drain current I6increases as the output signal Vout decreases. Thus, the drain current I6consequently becomes substantially constant (see single-dashed line inFIG. 4) irrespective of the variation of the first input signal IP in the same manner as the drain current I5.

FIG. 2is a graph showing the input and output characteristic of the first input signal IP and the output signal Vout in the operational amplifier circuit10ofFIG. 1. The single-dashed line shows the ideal input and output characteristics of an operational amplifier circuit, and the solid line indicates the actual input and output characteristics of the operational amplifier circuit10shown inFIG. 1. As the first input signal IP becomes closer to the high potential power supply VD, the potential of the output signal Vout becomes lower than the ideal potential, that is, the first input signal IP. This increases the difference between the output signal Vout and the first input signal IP. In other words, the offset voltage increases as the first input signal IP becomes closer to the high potential power supply VD.

The present invention provides an operational amplifier circuit capable of suppressing the generation of the offset voltage.

One aspect of the present invention is an operational amplifier circuit for generating an output signal from a first input signal and a second input signal. The operational amplifier circuit has a differential input circuit including a first transistor for receiving the first input signal and generating a first voltage and a second transistor for receiving the output signal as the second input signal and generating a second voltage. An output stage circuit is connected to the differential input circuit and includes a third transistor responsive to the second voltage. A fourth transistor is operatively connected to the third transistor. A first node is formed between the third transistor and the fourth transistor. A fifth transistor is responsive to the first voltage. A sixth transistor is connected in series to the fifth transistor. The fourth transistor and the sixth transistor form a first current mirror. A second node is formed between the fifth transistor and the sixth transistor. The output signal is generated at the second node. A control circuit, connected to the differential input circuit and the output stage circuit, controls the potential at the first node using the first input signal.

Another aspect of the present invention is an operational amplifier circuit for generating an output signal from a first input signal and a second input signal. The operational amplifier circuit has a differential input circuit including a first transistor of a first conduction type for receiving the first input signal and generating a first voltage and a second transistor of the first conduction type for receiving the output signal as the second input signal and generating a second voltage. An output stage circuit is connected to the differential input circuit. The output stage circuit includes a third transistor of a second conduction type differing from the first conduction type and being responsive to the second voltage. A fourth transistor of the first conduction type is operatively connected to the third transistor. A fifth transistor of the second conduction type is responsive to the first voltage. A sixth transistor of the first conduction type is connected in series to the fifth transistor. The fourth transistor and the sixth transistor form a first current mirror. A first node is formed between the fifth transistor and the sixth transistor. The output signal is generated at the first node. A seventh transistor of the second conduction type is connected between the third transistor and the fourth transistor and is responsive to a control voltage corresponding to the first input signal.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

An operational amplifier circuit1according to a preferred embodiment of the present invention will now be described with reference toFIGS. 3 and 4.FIG. 3is a schematic circuit diagram of an operational amplifier circuit1according to a preferred embodiment of the present invention.

The operational amplifier circuit1includes a constant current source11, a current mirror circuit12, a differential input circuit20, an output stage circuit30, and a control circuit40. The constant current source11supplies constant current I1to the current mirror circuit12. The current mirror circuit12includes N-channel MOS transistors N1and N2. The drain of the transistor N1is connected to the constant current source11. The sources of the transistors N1and N2are connected to the low potential power supply VS, the drain of the transistor N1is connected to the gates of the transistors N1and N2, and the drain of the transistor N2is connected to the differential input circuit20. The transistor N2has an element size that is two times greater than that of the input transistor N1. Therefore, the current mirror circuit12supplies the differential input circuit20with bias current I2that is two times greater than the drain current of the transistor N1, that is, the constant current I1of the constant current source11.

The differential input circuit20includes a differential pair21configured by N-channel MOS transistors N3and N4, and a current mirror circuit22configured by a pair of P-channel MOS transistors P1and P2. The gate of the transistor N3, which is connected to the first input terminal T1, receives the first input signal IP provided to the first input terminal T1. The gate of the transistor N4, which is connected to the second input terminal T2, receives the second input signal IM provided to the second input terminal T2. The transistors P1and P2are of the same size. Thus, the transistor P1causes the flow of drain current having a current value that is the same as the drain current of the transistor P2.

A node A between the transistors N3and P1and a node B between the transistors N4and P2are connected to the gate of the transistor P4and the gate of the transistors P3of the output stage circuit30, respectively. The transistor P3has a source connected to the high potential power supply VD and a gate connected to the drain and the gate of the transistor P2. Therefore, the transistor P3and the transistor P2operate as a current mirror. The transistor P3has an element size that is the same as the transistor P2and causes the flows of drain current I5corresponding to the gate voltage of the transistor P2(potential V2at the node B). The transistor P4, which functions as a former transistor in the final output stage, has a source connected to the high potential power supply VD and a drain connected to the output terminal To. The transistor P4, which has an element size that is ten times greater than that of the transistor P1, supplies drain current I6, which corresponds to the element size and the gate voltage (potential V1of node A) of the transistor P4, to the output terminal To.

The drain and the gate of the transistor N1are connected to the gate of an N-channel MOS transistor N11(first constant current source) in the control circuit40. The transistor N11has a source connected to the low potential power supply VS and a drain connected to the source of an N-channel MOS transistor N12. That is, the transistor N11and the transistor N1operate as a current mirror. Therefore, the transistor N11supplies drain current I11, which corresponds to the element size ratio of the transistor N1and the transistor N11, to the transistor N12.

The source of the transistor N12is connected to the drain of the transistor N11and to the gate of a P-channel MOS transistor P11. The drain of the transistor N12is connected to the drain and gate of a P-channel MOS transistor P12that operates as a diode. The gate of the transistor N12is connected to the gate of the N-channel MOS transistor N3configuring the differential pair21. That is, the gate of the transistor N12receives the first input signal IP.

The drain of the transistor P12is connected to the gate of the transistor P12and to the drain of the transistor N12. The source of the transistor P12is connected to the high potential power supply VD.

The transistor P11has a gate, which is connected to a node D (the source of transistor N12) between the transistor N12and the transistor N11, and a source, which is connected to the drain of the P-channel MOS transistor P3. The drain of the transistor P11is connected to the drain of the transistor N5of the current mirror circuit31. A connection point between the transistor P11and the transistor P3is defined as node C. In the preferred embodiment, the element size of the transistor N12and the transistor P11and the element size of the transistors N11and P12relative to the transistors P3and N5are set so that the gate-source voltage Vgs1of the transistor N12and the gate-source voltage Vgs2of the transistor P11are substantially equal. In the preferred embodiment, the control circuit40is configured by transistors N11, N12, P1, and P12.

The current mirror circuit31includes a pair of N-channel MOS transistors N5and N6. The transistor N5has the same element size as the transistor N1of the current mirror circuit12. The transistor N5has a source connected to the low potential power supply VS and a drain connected to the drain of the transistor P11and the gates of the two transistors N5and N6. The transistor N6functions as the latter transistor in the final output stage. The transistor N6has a source connected to the low potential power supply VS and a drain connected to the output terminal To. The drain voltages of the two transistors P4and N6are output from the output terminal To as the output signal Vout. The transistor N6, which has an element size that is ten times greater than that of the transistor N5, draws in drain current I7that is ten times greater than that of the drain current of the transistor N5from the output terminal To.

The operational amplifier circuit1receives the output signal Vout as the second input signal IM. Thus, the second input terminal T2is connected to the output terminal To, and the operational amplifier circuit1operates as a voltage follower.

The operation of the operational amplifier circuit1will now be discussed.

When the potentials at the first and second input signals IP and IM are substantially equal (IP=IM), the current mirror circuit12supplies the differential pair21with bias current I2having a current value that is two times greater than that of the constant current I1of the constant current source11.

The bias current I2is equally distributed to the transistors N3and N4. Thus, the drain currents I3and I4are substantially equal (I3=I4) and have a current value that is one half the bias current I2(I3=I4=I2×½=I1).

The drain current I5of the transistor P3is substantially equal to the drain current I4of the transistor N4(I5=I4=I1) due to the current mirror circuit22and the current mirror of the transistors P2and P3. The current mirror circuit31generates the drain current I7having a current value that is ten times greater than that of the drain current I5of the transistor N5(I7=I5×10).

If the drain currents I3and I4are substantially equal, the potentials V1and V2at the nodes A and B, that is, the gate voltages of the transistors P3and P4are substantially equal. Thus, the drain currents I5and I6of the transistors P3and P4are determined by the element size ratio. In other words, the element size of the transistor P4is ten times greater than that of the transistor P3(transistors P1and P2). Thus, the drain current I6of the transistor P4has a current value that is ten times greater than the drain current I5of the transistor P3(I6=I5×10).

The drain current I6of the transistor P4and the drain current I7of the transistor N6are substantially equal (I6=I7=I5×10). This stabilizes the potential at the output signal Vout. The second input signal IM is thus held at a potential that is substantially equal to the potential at the first input signal IP (IP=IM).

When the first input signal IP is higher than the second input signal IM (output signal Vout) (IP>IM), the current mirror circuit12supplies the differential pair21with the bias current I2having a current value that is two times greater than the constant current I1of the constant current source I1.

The first input signal IP is higher than the second input signal IM. Thus, the differential pair21distributes the bias current I2to the transistors N3and N4such that a greater amount of current is distributed to the transistor N3. Therefore, the drain current I3of the transistor N3is greater than one half the bias current I2of the transistor N2(I3>I2×½=I1).

When the drain current I3of the transistor N3increases and the drain current I4of the transistor N4decreases, the potential V1at the node A decreases and the potential V2at the node B increases (V1<V2). When the potential V1of the node A decreases, the gate voltage of the transistor P4decreases. Thus, the output signal Vout increases. Specifically, the output signal Vout increases in response to the voltage difference between the first input signal IP and the second input signal IM. The increase in the output signal Vout decreases the drain current I6of the transistor P4.

The drain current I5of the transistor P3at this point is as follows. First, the node D between the transistors N11and N12has a potential V11obtained by subtracting the gate-source voltage Vgs1of the transistor N12from the gate voltage of the transistor N12(potential at first input signal IP) (V11=IP−Vgs1). The potential V11at the node D is supplied to the transistor P11as a gate voltage. Therefore, the node C has a potential V3obtained by adding the gate-source voltage Vgs2of the transistor P11to the gate voltage of the transistor P11(potential V11of the node D) (V3=V11+Vgs2=IP−Vgs1+Vgs2). In the preferred embodiment, the gate-source voltage Vgs1of the transistor N12is set to be substantially the same as the gate-source voltage Vgs2of the transistor P11due to element size of each of the transistors N5, N11, N12, P3, P11, and P12, as described above. Therefore, the potential V3at the node C becomes substantially the same as the first input signal as shown by the following equation.

The gate-source voltage Vgs1of the transistor N12is determined by the drain voltage and the drain current of the transistor N12. In other words, the gate-source voltage Vgs1of the transistor N12is determined by the drain voltage of the transistor P12and the drain current I11of the transistor N11. The gate-source voltage Vgs2of the transistor P11is determined by the drain voltage and the drain current of the transistor P11. In other words, the gate-source voltage Vgs2of the transistor P11is determined by the drain voltage of the transistor N5and the drain current I5of the transistor P3.

The potential V3at the node C, that is, the drain voltage of the transistor P3increases as the first input signal IP increases. In other words, the potential V3at the node C (drain voltage of the transistor P3) becomes substantially equal to the voltage of the first input signal IP in a manner following the variation of the first input signal IP. This decreases the drain current I5.

The drain current I5and the drain current I6in this case will now be described in detail. The output signal Vout increases and the potential V3at the node C increases as the first input signal IP increases. Therefore, the drain voltage of the transistor P3and the drain voltage of the transistor P4become substantially equal. That is, the drain voltages of the transistors P3and P4both have the first input signal IP. The drain currents I5and I6of the transistors P3and P4thus have current values corresponding to their element sizes. That is, both drain currents I5and I6decrease as the first input signal IP increases while maintaining the current values at an ideal ratio of 1:10 (I6=I5×10), as shown by the solid line inFIG. 4. More specifically, if the current value of the drain current I5is “E” when the first input signal IP is equal to the low potential power supply VS, the current value of the drain current I6becomes “10×E”. As the first input signal IP varies to the high potential power supply VD, the current value of the drain current I5decreases from “E” to “F”, and the current value of the drain current I6decreases from “10×E” to “10×F”. Thus, the drain currents I5and I6of the transistors P3and P4have small current values in the operational amplifier circuit1of the preferred embodiment as compared to the conventional operational amplifier circuit10(see single-dashed line inFIG. 4) when the first input signal IP increases. This decreases the power consumption.

The current mirror circuit31generates the drain current I7with a current value that is ten time greater than the drain current I5of the transistor N5(I7=I5×10). Therefore, the drain current I6of the transistor P4and the drain current I7of the transistor N6become equal (I6=I7=I5×10) even if the first input signal IP increases. This stabilizes the potential of the output signal Vout, and the second input signal IM is held at a potential substantially equal to the first input signal IP (IP=IM).

When the first input signal IP is lower than the second input signal IM (potential of output signal Vout) (IP<IM), the current mirror12supplies the differential pair21with bias current I2having a current value that is two times greater than the constant current I1of the constant current source11.

The first input signal IP is lower than the second input signal IM. Thus, the differential pair21distributes the bias current I2to the transistors N3and N4such that a greater amount of current is distributed to the transistor N4. Accordingly, the drain current I3of the transistor N3is less than one half the bias current I2of the transistor N2(I3<I2×1/2=I1).

When the drain current I3of the transistor N3decreases, and the drain current I4of the transistor N4increases, the potential V1at the node A increases and the potential V2of the node B decreases (V1>V2). The gate voltage of the transistor P4increases when the potential V1at the node A increases. Therefore, the output signal Vout decreases. Specifically, the output signal Vout decreases in correspondence with the voltage difference between the first input signal IP and the second input signal IM. The decrease in the output signal Vout increases the drain current I6of the transistor P4.

The potential V3at the node C between the transistors P3and P11becomes substantially equal to the voltage of the first input signal IP (V3=IP) in a manner following the variation of the first input signal IP, as described above. Therefore, the potential V3at the node C, that is, the drain voltage of the transistor P3decreases as the first input signal IP decreases. This increases the drain current I5.

In this manner, the output signal Vout and the potential V3at the node C decreases as the first input signal IP decreases. Therefore, the drain voltage of the transistor P3and the drain voltage of the transistor P4become substantially equal, that is, the drain voltages of the transistors P3and P4both have the first input signal IP. For this reason, the drain currents I5and I6of the transistors P3and P4have current values corresponding to their element size. That is, the drain currents I5and I6both increase as the first input signal IP decreases while maintaining the ideal current value ratio of 1:10 (I6=I5×10).

The current mirror circuit31generates the drain current I7having a current value that is ten times greater than that of the drain current IS of the transistor N5(I7=I5×10). Therefore, the drain current I6of the transistor P4and the drain current I7of the transistor N6become equal (I6=I7=I5×10) even if the first input signal IP decreases. This stabilizes the potential of the output signal Vout and holds the second input signal IM at a potential substantially equal to the first input signal IP (IP=IM).

FIG. 5is a graph showing a simulation result regarding the frequency characteristic of the operational amplifier circuit1shown inFIG. 3and the operational amplifier circuit10shown inFIG. 1. The simulation was performed with the operational amplifier circuits1and10having the same power consumption. InFIG. 5, the horizontal axis represents the first input signal IP, and the vertical axis represents the unit gain frequency.

As apparent fromFIG. 5, the unit gain frequency of each of the operational amplifier circuits1and10varies so as to increase when the first input signal IP approaches the high potential power supply VD. However, the frequency of the operational amplifier circuit1varies more gradually than the operational amplifier circuit10. More specifically, the range of unit gain frequency variation caused by the variation of the first input signal IP is small in the operational amplifier circuit1of the present invention compared to the conventional operational amplifier circuit10. That is, the difference between the unit gain frequency when the first input signal IP reaches the high potential power supply VD and the unit gain frequency of when the first input signal IP reaches the low potential power supply VS is small in the operational amplifier circuit1. Therefore, the change in responding speed caused by variation of the first input signal IP is small in the operational amplifier circuit1. This stabilizes the responding speed.

Furthermore, the unit gain frequency when the first input signal IP reaches the low potential power supply VS is largely increased in the operational amplifier circuit1of the present invention compared to the conventional operational amplifier circuit10. Therefore, the responding speed of the operational amplifier circuit1is significantly increased by adding the transistors N11, N12, P1, and P12, that is, the control circuit40.

The operational amplifier circuit1of the embodiment has the following advantages.

(1) The P-channel MOS transistor P11is arranged between the transistor P3and the transistor N5, and the first input signal IP is provided to the gate of the transistor P11via the N-channel MOS transistor N12. Thus, the potential V3at the node C varies in a manner following the variation of the first input signal IP. Furthermore, the element size of each of the transistors N5, N11, N12, P3, P11, and P12is determined so that the gate-source voltages Vgs1and Vgs2of the transistors N12and P11are substantially equal. The potential at the output signal Vout thus stabilizes even if the first input signal IP varies, in particular, even if the first input signal IP approaches the high potential power supply VD due to increase in the first input signal IP. Therefore, the first input signal IP and the second input signal IM are maintained at substantially the same potential (IP≈IM). Thus the operational amplifier circuit1suppresses the generation of offset voltage caused by variation of the first input signal IP.

The P-channel MOS transistor P12in the above embodiment may be omitted. That is, the drain of the N-channel MOS transistor N12may be directly connected to the high potential power supply VD.

The P-channel MOS transistor P11in the above embodiment may be changed to an N-channel MOS transistor, and the N-channel MOS transistor N12may be changed to a P-channel MOS transistor.

The N-channel MOS transistors N11and N12and the P-channel MOS transistor P12in the above embodiment may be omitted. That is, the first input terminal T1may be directly connected to the gate of the P-channel MOS transistor P11. In this case, the P-channel MOS transistor P11may be changed to the N-channel MOS transistor.

The transistors P3, P4, N5, and N6configuring the output stage circuit30in the above embodiment may be configured by the P-channel MOS transistor or the N-channel MOS transistor.

In the above embodiment, the P-channel MOS transistors configuring the operational amplifier circuit1may each be changed to an N-channel MOS transistor, and the N-channel MOS transistors configuring the operational amplifier circuit1may each be changed to a P-channel MOS transistor. Needless to say, in this case, the high potential power supply VD and the low potential power supply VS are exchanged with each other.

The control circuit of the present invention is not limited to the control circuit40shown inFIG. 3. In a further embodiment, the control circuit may be formed, for example, by a variable resistor connected between the transistor P3and the transistor N5. In such control circuit, the resistance value of the variable resistor changes in accordance with the variation of the first input signal IP. More specifically, the control circuit increases the resistance value of the variable resistor as the first input signal IP increases and decreases the resistance value of the variable resistor as the first input signal IP decreases. Thus, the drain voltage of the transistor P3varies as the first input signal IP varies without being dependent on the voltage of the diode connected transistor N5. As a result, the same advantages as the above embodiment are obtained.

Each transistor in the above embodiment is not limited to a MOS transistor and may be a bipolar transistor.