Balancing charge pump circuits

Methods and systems of controlling a switched capacitor converter are provided. Upon determining that a voltage across a flying capacitor is above a first threshold, a first current is drawn from a first terminal of the flying capacitor by a first current source, and a second current is provided to a second terminal of the flying capacitor by a second current source. Upon determining that the voltage across the flying capacitor is below a second threshold, the first current is provided to the first terminal of the flying capacitor by the first current source, and the second current is drawn from the second terminal of the flying capacitor by the second current source. Upon determining that the voltage across the flying capacitor is above the second threshold and below the first threshold from the reference voltage, the first and second current sources are turned OFF.

BACKGROUND

Technical Field

This disclosure generally relates to voltage converters. More particularly, the present disclosure relates to switched capacitor converter circuits that are more reliable.

Description of Related Art

A charge pump circuit is a type of switched capacitor circuit that may be used to convert a direct current (DC) input voltage to another DC voltage. A charge pump can be configured to generate an output voltage that is a multiple (e.g., 2, 3 . . . N times) the input voltage or it can set an output voltage that is a fraction thereof (e.g., ½, ⅓ . . . 1/N times of the input voltage). In some implementations, such circuit can also generate a negative output voltage from a positive input voltage. Since the charge pump circuit does not require inductors to do the voltage conversion, it is sometimes referred as an inductor-less DC/DC converter.

FIG. 1Aillustrates a conventional switched capacitor converter circuit100. In the example ofFIG. 1A, the input voltage approximately equals 2 times the output voltage at steady state. In the example ofFIG. 1A, the transistors, which by way of example only and not by way of limitation, are illustrated to be metal oxide semiconductor field effect transistors (MOSFETs) Q1and Q3(106and110), are turned ON and OFF in a way that is complimentary to transistors Q2and Q4(108and112), as illustrated inFIG. 1B. The transistors are shown to switch at around 50% duty cycle. As illustrated inFIG. 1B, during steady state operation, the transistors Q1-Q4(106to112) are switched to cyclically charge and discharge capacitor104, sometimes referred to as a flying capacitor CFLY. By adding feedback to the circuit100, transistors Q1and Q4(106and112) can be driven differently to generate an output voltage VOUTother than VIN/2. For example, different duty ratios may be used to provide the flexibility of providing output voltages that are different factors (e.g., 0.75, 0.5, 0.25, etc.) of the input voltage. Also, by swapping the input and output nodes VINand VOUT, respectively, the output voltage may be a multiple of the input voltage. For simplicity, as used herein, the term “factor” includes the meaning of fraction and multiple.

In the example ofFIG. 1A, when transistors Q1106and Q3110are ON, capacitors CFLY104and COUT114are effectively connected in series, thereby charging CFLY104and COUT114to approximately VIN/2. The capacitors CFLY104and COUT114are initially charged by the input voltage VINat start-up, where the voltage across the nodes of CFLY104and COUT114is at VIN/2. Typically, capacitors are connected external to any controller package due to their large size. The switches Q1-Q4(106to112) may also be external to the package to accommodate higher currents. The input voltage VIN102is directly connected to the top terminal of the transistor Q1(106), where capacitor—CFLY104is connected to VIN102via transistor Q1(106) when it is ON.

When the transistors Q2108and Q4112are ON, the capacitors CFLY104and COUT114are in parallel. This arrangement forces the voltages across capacitors CFLY104and COUT114to be substantially similar at approximately VIN/2.

Charge pump circuits, similar to the switched capacitor converter circuit100, may be subject to a large inrush current to sensitive circuit elements, such as transistors Q1to Q4(106to112). For example, the initial voltage across the capacitors, CFLY104and COUT114may not be equal to VIN/2 during startup or due to the presence of a fault condition during operation, collectively referred to herein as a transient state. In various scenarios, a fault condition may arise, for example, when a capacitor, such as COUT114, becomes a short circuit. Since there is no inductor in the switched capacitor converter circuit100to limit current, the input inrush current can rise quickly to a high level. In high current applications, this huge inrush current is exacerbated since very low ON-resistance MOSFETs may be used to implement transistors Q1to Q4(106to112) to achieve high power efficiency.

FIG. 1Cis an example scenario that illustrates how, upon the VINpower supply powering up at time T0(e.g., when the capacitors CFLY104-COUT114have a zero initial voltage), the in-rush current130may exceed 1000 A, depending on parasitic resistances in the path. The high current may last for a short time (e.g., less than 1 microsecond) but can nonetheless exceed the transistors'106to112safe operating current, thereby affecting the reliability of the switched capacitor converter circuit100in general, and the transistors106to112in particular. The output voltage VOUTreaches its steady state voltage after the capacitors CFLY104and COUT114are fully charged and the switches Q1-Q4(106to112) are controlled, as illustrated in the context ofFIG. 1B. Further, there may be ringing132at the output voltage node VOUTafter the inrush current, as illustrated inFIG. 1C, which may affect the load116. During transient state (e.g., power-up or a fault condition), the voltages on the chip are not predictable because the voltages may not have been fully developed.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

In the following detailed description, numerous specific details are set forth by way of examples in order to provide a thorough understanding of the relevant teachings. However, it should be apparent that the present teachings may be practiced without such details. In other instances, well-known methods, procedures, components, and/or circuitry have been described at a relatively high-level, without detail, in order to avoid unnecessarily obscuring aspects of the present teachings. Some embodiments may be practiced with additional components or steps and/or without all of the components or steps that are described.

The various methods and circuits disclosed herein generally relate to methods and circuits of providing fault protection for switched capacitor voltage converters. Both multiplying and dividing switched capacitor voltage converters are controlled by various pre-balance circuits such that large inrush currents are prevented, thereby providing a reliable operation of the switched capacitor voltage converters.

FIG. 2illustrates a switched capacitor converter circuit201that is coupled to a pre-balance circuit230, consistent with an illustrative embodiment. The components of the switched capacitor converter circuit201are similar to those ofFIG. 1Aand are therefore not repeated here for brevity. The current through the transistors Q1to Q4(206to212) when the transistors Q1to Q4operates in the triode region and the capacitors CFLY204and COUT214can be approximated by the equations below for both phases of operation:
Phase 1,I=(VIN−VCFLY(t)−VCOUT(t))/(RON_Q1+RON_Q3)  (EQ. 1)
Phase 2,I=(VCFLY(t)−VCOUT(t))/RON_Q2+RON_Q4)  (EQ. 2)

Where:Phase 1 is when transistors Q1and Q3are ON, and Q2and Q4are OFF,Phase 2 is when transistors Q2and Q4are ON, and Q1and Q3are OFF,I is the current through a transistor that is ON,RONis the drain to source resistance of a transistor when it is ON,VCFLY(t) is the voltage across the CFLYat time t, andVCOUT(t) is the voltage across the COUTat time t.

The drain to source resistance RONof each transistor Q1to Q4(206to212) may have a very low ON resistance for better power efficiency. The lower the RONof the corresponding transistor, the larger the inrush current may be, thereby providing a potential threat to the reliability of the switched capacitor converter circuit.

Applicants have identified that in view of equations 1 and 2 above, that if the voltages of capacitors CFLY204and COUT214are controlled by the manner disclosed herein, the inrush current can be minimized. For example, if the following two conditions of equations 3 and 4 are met, then the inrush current is zero:
Condition 1:VCFLY(t=0)=VCOUT(t=0)  (EQ. 3)
Condition 2:VIN=VCFLY(t=0)VCOUT(t=0)  (EQ. 4)

In various embodiments, the inrush current can be limited to different pre-determined values based on the transistors' Q1to Q4(206to212) safety operation range. For example, different types of transistors have different tolerances for proper operation that does not lead to a premature reliability degradation of the transistor.

In one embodiment, assuming that the ON-resistance RONof the transistors Q1to Q4(206to212) is the same and if the transistor (e.g., MOSFET) maximum safety current is IIMAX, equations 5 and 6 can provide conditions for safe operation of the capacitor converter circuit201.
VIN/2−2RON*Imax<VCFLY(t=0)<VIN/2+2RON*Imax(EQ. 5)
VIN/2−2RON*Imax<VCOUT(t=0)<VIN/2+2RON*Imax(EQ. 6)

Hysteresis and the corresponding offset voltage is discussed in more detail later. The pre-balance circuit230is configured to pre-balance the voltage across capacitors CFLY204and COUT214such that the conditions of equations 5 and 6 above are met when the switched capacitor converter circuit201is operative as a voltage divider charge pump. The pre-balancing of the pre-balancing circuit230may be performed during power-up or re-startup of the switched capacitor converter circuit201.

In the example ofFIG. 2, the pre-balance circuit includes three current sources260,262, and264, which are able to sink or source current to nodes SW1, −VOUT228, and SW2, respectively. The pre-balance circuit230includes a voltage divider, comprising a first resistance element242and a second resistance element246connected in series. The ratio of the first resistance element242to the second resistance element246may differ based on the voltage division to be achieved by the switched capacitor converter circuit201. For example, for a divide by two charge pump configuration, the first resistance element242and the second resistance element246may be equal in resistance such that a voltage of VIN/2 is provided at the voltage divider node244. The voltage divider is configured to sample the input voltage VIN202and provide a scaled version thereof at node244. The voltage at node244is used as a reference voltage for various components of the pre-balance circuit230.

The pre-balance circuit includes a pair of comparators232and238configured to compare the voltage across the capacitor CFLY204with the reference voltage of node244. In various embodiments, hysteresis may be added in order to provide a tolerance range for the comparators232and238. To that end, a first hysteresis voltage source VHYS234provides a first hysteresis voltage VHYSto an input terminal of the first comparator234. Similarly, a second hysteresis voltage source VHYS236is added to an input terminal of the second comparator238. In various embodiments, the first hysteresis voltage may be equal in magnitude to the second hysteresis voltage or may be different, depending on the desired hysteresis tolerance range to be implemented for the pre-balance circuit230. Put differently, the hysteresis voltage sources234and236provide threshold levels that, when exceeded, may trigger corrective action to pre-balance a switched capacitor converter circuit201.

If the VCFLYvoltage is out of a predetermined tolerance defined by the hysteresis voltage sources234and236, then the pair of comparators232and238activate the first current source to provide a current to charge or sink the capacitor CFLY204and activate the second current source to draw current or source to the capacitor CFLY204such that the voltage across the capacitor CFLY204is controlled to be within the tolerance range discussed above.

The pre-balance circuit may also include a second pair of comparators252and258together providing a second comparator circuit that is configured to compare the voltage across capacitor COUT214(i.e., the output voltage VOUTat node228) with the reference voltage of node244. Similar to the first pair of comparators232and238(i.e., the first comparator circuit), hysteresis may be added in order to provide a tolerance range for the comparators252and258. To that end, a third hysteresis voltage source VHYS254provides a third hysteresis voltage VHYSto an input terminal of the first comparator VHYS252. Similarly, a fourth hysteresis voltage source VHYS256provides a hysteresis voltage to a terminal of the comparator258. In various embodiments, the third hysteresis voltage may be equal in magnitude to the fourth hysteresis voltage or may be different, depending on the desired hysteresis tolerance range to be implemented for the voltage across the output capacitance COUT214of the pre-balance circuit230.

If the VOUTvoltage is out of a predetermined tolerance defined by the hysteresis voltage sources254and256, then the second pair of comparators252and258activate the second current source to provide or sink current to adjust (e.g., charge/discharge) the output capacitor COUT214such that the voltage across the output capacitor COUT214is controlled to be within the tolerance range defined by the hysteresis voltage sources254and256.

In one embodiment, during a capacitor voltage pre-balance phase, the transistors Q1to Q4(206to212) remain OFF and each current source260,262, and or264draws or sources current to nodes sw1, sw2, and VOUTbased on the sensed voltage across the capacitors CFLY204and COUT214. The following equations provide conditions and polarity of each current source, respectively.

Reference now is made toFIG. 3A, which is a switched capacitor converter circuit301that is coupled to a pre-balance circuit330, consistent with another illustrative embodiment. The components of the switched capacitor converter circuit301are similar to those of the switched capacitor converter circuit201and are therefore not discussed in substantial detail. In one embodiment, the switched capacitor converter circuit301may include an additional output capacitor COPT370coupled between a terminal of the input voltage VIN302and the output capacitor COUT314for better charge sharing and efficiency. As used herein, the term efficiency relates to the amount of input power is used to get a certain amount of power. For example, for a 100% efficient system, there are no losses and the input power used is the same as the output power. The capacitor COPT370provides an additional path in transferring charge to the output capacitor COUT, thereby reducing the amount of current flowing through the transistors. As a capacitor has lower effective resistance than the power transistors, it therefore has lower losses.

When the switched capacitor converter circuit301is configured to be operated as a voltage divider charge pump, as illustrated inFIG. 3A, the pre-balance circuit can be further simplified. For example, pre-balance circuit330may use a single current source360to charge or discharge the two capacitors CFLY304and COUT328at the same time.

The pre-balance circuit330includes a voltage divider comprising a first resistance element342and a second resistance element346connected in series. The ratio of the first resistance element342to the second resistance element346may differ based on the voltage division to be achieved by the switched capacitor converter circuit301. The voltage divider is configured to sample the input voltage VIN302and provide a scaled version thereof at node344.

The pre-balance circuit330also includes a pair of comparators332and338that are configured to compare the voltage across the capacitor COUT314with the reference voltage of the node344. The operation of the pair of comparators332and338is similar to that of comparators252and258ofFIG. 2and is therefore not discussed in detail for brevity.

The pre-balance circuit330is able to perform the pre-balancing without the use of the additional circuitry of the pre-balance circuit230ofFIG. 2, by virtue of a specific timing of activation and deactivation of the transistors Q1to Q4(306to312) during a capacitor (COUT) voltage pre-balance phase. For example, during such phase, transistors Q2and Q4(308and312) are turned ON (represented by shorted wires) while transistors Q1and Q3(306and310) are turned OFF (represented by gaps and a drain to source diode connection), as illustrated inFIG. 3A.

Before turning ON transistors Q2308and Q4312, the node SW1is pulled to a level substantially similar to VOUT328, and the node SW2is pulled down to a level substantially similar to GND. In one embodiment, two current sources may be used to pull the node SW1to GND and the node SW2to GND separately, or two resistance elements may be connected from node SW1to GND and node SW2to GND separately to pull these two nodes down. When transistors Q2308and Q4312are then turned ON, capacitors CFLY304and COUT314are connected in parallel and the voltage across them is the same. The pre-balance circuit330charges or discharges the capacitors CFLY304and COUT314simultaneously if the voltage sensed across the output capacitor COUT314is not within a predetermined tolerance, as defined by the hysteresis voltage sources334and336. Alternately, if CFLY304is not required to be balanced as precise as capacitor COUT314, the pre-balance may be done with only transistor Q4312being ON (while transistor Q2308is OFF) for simplicity. In such a scenario, the capacitor CFLY304may be charged up by the pre-balance circuit330through the body diode of Q2. The voltage on the CFLYcapacitor304is one diode voltage drop (e.g., approximately 0.7V) lower than the voltage on the output capacitor COUT314.

FIG. 3Bis a switched capacitor converter circuit that is coupled to another pre-balance circuit, consistent with illustrative embodiment. The components of switched capacitor converter circuit301and some of the components of the pre-balance circuit330B are similar to those ofFIG. 3Aand are therefore not repeated here for brevity.

The pre-balance circuit330B can perform pre-balancing with load current on the output of the switched capacitor converter301. If the load current through RLOAD358is much less than the current source360(e.g., at least 10 time smaller), the current source360over-drives the small load current and performs balancing as normal. However, if the load current is comparable or larger than the current source360, a disconnect FET DQ356is used to disconnect the load current during pre-balancing. In the example ofFIG. 3B, the outputs of the two comparators332338are connected to an logic gate350, (which, in one embodiment may be an AND gate). The output of the logic gate350controls the gate of the disconnect FET QD356through an optional RC filter. For example, there is a series resistance element Rg352coupled in series between the logic gate350and the gate of the disconnect FET QD356. There is also a capacitance element Cg354coupled between the gate of the disconnect FET QD356and ground. The RC filter provided by Rg352and Cg354may be selected based on the desired delay and speed of turning ON the Disconnect FET QD356to meet the requirements of different applications.

The output of the logic gate350is high only when the outputs of both comparators332and328are high. Accordingly, VOUTis within the predetermined tolerance defined by the hysteresis voltage sources334and336. The logic gate350is supplied by a voltage source high enough to turn ON the disconnect FET QD. With the disconnect FET QD356, the pre-balancing may be performed in the same way as no load conditions and the load current is applied only after pre-balancing is finished.

Still further, the concepts discussed herein can be used together with various types of DC to DC voltage converters, such as buck, boost, and buck-boost. To that end,FIG. 4illustrates by way of illustrative example a switched capacitor converter circuit401with a buck topology that is coupled to a pre-balance circuit430, consistent with an exemplary embodiment. The pre-balance circuit430is substantially similar to the pre-balance circuit230ofFIG. 2. Similarly, the switched capacitor converter circuit401is substantially similar to the switched capacitor converter circuit201ofFIG. 2. These blocks are therefore not repeated here for brevity.

The architecture400includes an output capacitor COUT464that is coupled between node480and GND. There is an inductor L468coupled between node SW2and the output node VOUT. There is a second capacitor COUT2470coupled between VOUTand GND. There are two resistance elements472and474coupled in series between VOUTand GND. There is a feedback and control circuit462coupled to the interface between the first resistance element472and the second resistance element474.

In one embodiment, by setting the amplitude of current sources Isw1260and Isw2264to be substantially similar, the hybrid buck converter is allowed to startup into a pre-biased output condition without charging or discharging the output voltage VOUT.

CONCLUSION

For example, any signal discussed herein may be scaled, buffered, scaled and buffered, converted to another mode (e.g., voltage, current, charge, time, etc.,), or converted to another state (e.g., from HIGH to LOW and LOW to HIGH) without materially changing the underlying control method.

The components, steps, features, objects, benefits and advantages that have been discussed are merely illustrative. None of them, nor the discussions relating to them, are intended to limit the scope of protection in any way. Numerous other embodiments are also contemplated. These include embodiments that have fewer, additional, and/or different components, steps, features, objects, benefits and advantages. These also include embodiments in which the components and/or steps are arranged and/or ordered differently. For example, bipolar transistors (e.g., PNP or NPN) or junction gate field-effect transistors (JFET) can be used instead of MOS transistors. A PNP may be used instead of NPN, and a PMOS may be used instead of NMOS.

All articles, patents, patent applications, and other publications that have been cited in this disclosure are incorporated herein by reference.

It will be understood that the terms and expressions used herein have the ordinary meaning as is accorded to such terms and expressions with respect to their corresponding respective areas of inquiry and study except where specific meanings have otherwise been set forth herein. Relational terms such as “first” and “second” and the like may be used solely to distinguish one entity or action from another, without necessarily requiring or implying any actual relationship or order between them. The terms “comprises,” “comprising,” and any other variation thereof when used in connection with a list of elements in the specification or claims are intended to indicate that the list is not exclusive and that other elements may be included. Similarly, an element preceded by an “a” or an “an” does not, without further constraints, preclude the existence of additional elements of the identical type.