Selective segment via plating process and structure

A selective segment via plating process for manufacturing a circuit board selectively interconnects inner conductive layers as separate segments within the same via. Plating resist is plugged into an inner core through hole and then stripped off after an electroless plating process. Stripping of the electroless plating on the plating resist results in a plating discontinuity on the via wall. In a subsequent electroplating process, the inner core layer can not be plated due to the plating discontinuity. The resulting circuit board structure has separate electrically interconnected segments within the via.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims priority under 35 U.S.C. §119(a)-(d) of the Chinese Patent Application No: 201510127856.X, filed Mar. 23, 2015 and titled, “SELECTIVE SEGMENT VIA PLATING PROCESS AND STRUCTURE,” and the Chinese Patent Application No: 201510121886.X, filed Mar. 19, 2015 and titled, “SELECTIVE SEGMENT VIA PLATING PROCESS AND STRUCTURE,” which are both hereby incorporated by reference in their entireties for all purposes.

FIELD OF THE INVENTION

The present invention is generally directed to printed circuit boards. More specifically, the present invention is directed to printed circuit boards having selective segment via plating.

BACKGROUND OF THE INVENTION

A printed circuit board (PCB) mechanically supports and electrically connects electronic components using conductive traces, pads and other features etched from electrically conductive sheets, such as copper sheets, laminated onto a non-conductive substrate. Multi-layered printed circuit boards are formed by stacking and laminating multiple such etched conductive sheet/non-conductive substrate laminations. Conductors on different layers are interconnected with plated-through holes called vias.

FIG. 1illustrates a cut out side view of a portion of a conventional printed circuit board. The printed circuit board2includes a plurality of stacked layers, the layers made of non-conductive layers4,6and conductive layers8. The non-conductive layers can be made of prepreg or base material that is part of a core structure, or simply core. Prepreg is a fibrous reinforcement material impregnated or coated with a thermosetting resin binder, and consolidated and cured to an intermediate stage semi-solid product. Prepreg is used as an adhesive layer to bond discrete layers of multilayer PCB construction, where a multilayer PCB consists of alternative layers of conductors and base materials bonded together, including at least one internal conductive layer. A base material is an organic or inorganic material used to support a pattern of conductor material. A core is a metal clad base material where the base material has integral metal conductor material on one or both sides. A laminated stack is formed by stacking multiple core structures with intervening prepreg and then laminating the stack. A via10is then formed by drilling a hole through the laminated stack and plating the wall of the hole with electrically conductive material, such as copper. The resulting plating12interconnects the conductive layers8.

In the exemplary application shown inFIG. 1, the plating12extends uninterrupted through the entire thickness of the via10, thereby providing a common interconnection with each and every conductive layer8. In other applications, it may be desired that only certain conductive layers be commonly interconnected by the plating within the via. The commonly interconnected layers are referred to as segments. Formation of segments requires a break in the via wall plating, however, the plating process that forms the plating on the via walls is commonly applied to the entire wall surface. Therefore, to form the necessary plating breaks, the printed circuit board is formed as separate sub-assembly stacks that are laminated together. Each sub-assembly laminated stack has the desired plated via, but when laminated together the plated vias from each sub-assembly laminated stack are separated by a non-conductive material that forms a break in the overall via wall plating.FIG. 2illustrates a cut out side view of a portion of two conventional sub-assembly stacks that are to be subsequently used to form a printed circuit board. A sub-assembly laminated stack20includes non-conductive layers24,26and conductive layers28. The non-conductive layers24and the conductive layers28form core structures, which are laminated together with intervening non-conductive layer26, such as prepreg. A via22is formed by drilling a hole through the laminated stack and plating the wall of the hole with electrically conductive material. The resulting plating interconnects the conductive layers28. A second subassembly laminated stack30is similarly formed and includes a laminated stack of non-conductive layers34,36and conductive layers38, and plated via32. To form the completed printed circuit board, the two subassemblies20and30are stacked such that the corresponding vias22and32are aligned, and laminated together with intervening non-conductive layer40, as shown inFIG. 3. The non-conductive layer40provides a break in the conductive plating of via22and the conductive plating of via32, thereby forming two separate segments in the printed circuit board ofFIG. 3.

The process shown inFIGS. 2 and 3is referred to as sequential lamination. A problem with sequential lamination is that it is difficult to exactly align the vias of the stacked subassemblies. As shown inFIG. 3, a via center line42of the via22in subassembly20is not exactly aligned with a via center line44of the via32in subassembly30. This is known as layer to layer mis-registration and can lead to performance issues.

In some applications, one or more of the conductive layers closest to the top or bottom surface of the printed circuit board are not designed to be interconnected to the via plating. To sever this connection for these one or more conductive layers, a back drill process is performed where the hole is drilled into the printed circuit board at the via. The hole diameter is wider than the via diameter such that the drilled hole removes the wall plating thereby removing the interconnect plating between conductive layers.FIG. 4illustrates a cut out side view of a portion of a conventional circuit board having the via back drilled. The printed circuit board52is similar to the printed circuit board2ofFIG. 1except that a hole64has been back drilled into the printed circuit board52. The back drilled hole64removes the corresponding portion of the plating62in the via60co-located with the bottom few layers of the printed circuit board52. The remaining plating62provides an interconnect for the conductive layers58, however, the bottom most conductive layers58′ are no longer interconnected to the conductive layers58since the interconnect plating62is removed in the hole64. It is important that the back drilling process leaves intact the conductive layers58, which results in a via stubs66extending from the last interconnected conductive layer58. A via stub is a conductive portion of the via that is not connected in series with the electrical circuit. The longer the via stub, the greater the signal reflection and degradation. As such, it is desirable to minimize the length of the via stub. However, conventional back drilling processes have high variability and are difficult to control the length of the via stub. Additionally, back drilling is time consuming and expensive.

SUMMARY OF THE INVENTION

Embodiments are directed to a selective segment via plating process for manufacturing a circuit board having select inner layer connections as separate segments within the same via. Plating resist is plugged into an inner core through hole and then stripped off after an electroless plating process. Stripping of the electroless plating on the plating resist results in a plating discontinuity on the via wall. In a subsequent electroplating process, the inner core layer can not be plated due to the plating discontinuity. The resulting circuit board structure has separate electrically interconnected segments within the via. The selective segment via plating process uses a single lamination step.

In an aspect, a circuit board is disclosed. The circuit board includes a laminated stack comprising a plurality of non-conducting layers and a plurality of conductive layers. The laminated stack further comprises an inner plug layer having a plating resist layer. A via is formed through the laminated stack, wherein walls of the via are plated with conductive material except where the via passes through the inner plug layer, thereby forming a via wall plating discontinuity. In some embodiments, each of the conductive layers is pattern etched. In some embodiments, the via is a single drill hole through an entirety of the laminated stack. In some embodiments, the via wall plating forms electrical interconnections with conductive layers intersecting the via, and the via wall plating discontinuity electrically isolates a first segment of electrically interconnected conductive layers from a second segment of electrically interconnected conductive layers. In some embodiments, the via wall plating comprises a first plating stub extending from the first segment and a second plating stub extending from the second segment. In some embodiments, the first plating stub has a defined stub length equal to a thickness of a non-conductive layer between the first segment and a most proximate surface of the plating resist layer. In some embodiments, the second plating stub has a defined stub length equal to a thickness of a non-conductive layer between the second segment and a most proximate surface of the plating resist layer. In some embodiments, the inner plug layer further comprises a non-conducting layer coupled to the plating resist layers In some embodiments, the circuit board further comprises a cavity extending from the via in the inner plug layer.

In another aspect, another circuit board is disclosed. The circuit board includes a laminated stack comprising a plurality of non-conducting layers and a plurality of conductive layers. The laminated stack further comprises an inner plug layer having a plating resist layer. A via is formed through the laminated stack, wherein walls of the via are plated with conductive material except where the via passes through the inner plug layer. A cavity extends from the via in the inner plug layer, wherein the cavity forms a via wall plating discontinuity. The via wall plating forms electrical interconnections with conductive layers intersecting the via, and the via wall plating discontinuity electrically isolates a first segment of electrically interconnected conductive layers from a second segment of electrically interconnected conductive layers. The via wall plating includes a first plating stub extending from the first segment to the cavity and a second plating stub extending from the second segment to the cavity. In some embodiments, each of the conductive layers is pattern etched. In some embodiments, the via is a single drill hole through an entirety of the laminated stack. In some embodiments, the first plating stub has a defined stub length equal to a thickness of a non-conductive layer between the first segment and a most proximate surface of the plating resist layer. In some embodiments, the second plating stub has a defined stub length equal to a thickness of a non-conductive layer between the second segment and a most proximate surface of the plating resist layer. In some embodiments, the inner plug layer also includes a non-conducting layer coupled to the plating resist layer.

In yet another aspect, a multiple networked structure is disclosed. The structure includes a circuit board and a pin inserted in a via of the circuit board. The circuit board includes a laminated stack comprising a plurality of non-conducting layers and a plurality of conductive layers. The laminated stack further comprises an inner plug layer having a plating resist layer. The via is formed through the laminated stack, wherein walls of the via are plated with conductive material except where the via passes through the inner plug layer, thereby forming a via wall plating discontinuity. The via wall plating forms electrical interconnections with conductive layers intersecting the via, and the via wall plating discontinuity electrically isolates a first segment of electrically interconnected conductive layers from a second segment of electrically interconnected conductive layers. The pin is inserted in the via, wherein the pin is electrically coupled to each of the first and second segments to provide an independent electrical connection from each of the first and second segments to the pin.

In still yet another aspect, a method of manufacturing a circuit board is disclosed. The method includes forming a first via through a non-conductive layer and plugging the first via with a plating resist, thereby forming a plug subassembly. The method also includes laminating a plurality of alternating non-conductive layers and conductive layers to a first surface and a second surface of the plug subassembly, thereby forming a laminated stack. The method also includes forming a second via through the laminated stack, wherein the second via passes through plating resist in the first via such that a portion of a second via wall comprises plating resist at a layer coincident with the plug subassembly within the laminated stack. The method also includes performing an electroless plating process to plate the second via wall such that a portion of the plating is formed on the portion of the second via wall comprising plating resist. The method also includes stripping the portion of the plating formed on the portion of the second via wall comprising plating resist and stripping a portion of the plating resist to form a second via wall plating discontinuity on the second via wall coincident with the plug subassembly within the laminated stack. The method also includes performing an electroplating process to further plate remaining portions of the plating on the second via wall while the second via wall plating discontinuity is maintained. In some embodiments, forming the plug subassembly further comprises applying a first conductive layer on a first surface of the non-conductive layer and applying a second conductive layer on a second surface of the non-conductive layer. In some embodiments, the first conductive layer is pattern etched and the second conductive layer is pattern etched. In some embodiments, forming the plug subassembly further comprises plating the first via prior to plugging the first via with the plating resist thereby forming an electrical interconnect between the first conductive layer and the second conductive layer. In some embodiments, the method also includes pattern etching the conductive layers in the laminated stack. In some embodiments, a diameter of the first via is larger than a diameter of the second via. In some embodiments, stripping the portion of the plating and stripping the portion of the plating resist to form the second via wall plating discontinuity forms a cavity extending from the second via, wherein the cavity is coincident with the plug assembly in the laminated stack. In some embodiments, the second via wall plating forms electrical interconnections with conductive layers intersecting the second via, and the second via wall plating discontinuity electrically isolates a first segment of electrically interconnected conductive layers from a second segment of electrically interconnected conductive layers. In some embodiments, the second via wall plating comprises a first plating stub extending from the first segment and a second plating stub extending from the second segment. In some embodiments, the first plating stub has a defined stub length equal to a thickness of a non-conductive layer between the first segment and the first surface of the plug subassembly, and the second plating stub has a defined stub length equal to a thickness of a non-conductive layer between the second segment and the second surface of the plug subassembly. In some embodiments, performing the electroplating process comprises applying electricity to the first segment and to the second segment. In some embodiments, forming the second via comprises drilling a single drill hole through an entirety of the laminated stack.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Embodiments of the present application are directed to a printed circuit board. Those of ordinary skill in the art will realize that the following detailed description of the printed circuit board is illustrative only and is not intended to be in any way limiting. Other embodiments of the printed circuit board will readily suggest themselves to such skilled persons having the benefit of this disclosure.

Reference will now be made in detail to implementations of the printed circuit board as illustrated in the accompanying drawings. The same reference indicators will be used throughout the drawings and the following detailed description to refer to the same or like parts. In the interest of clarity, not all of the routine features of the implementations described herein are shown and described. It will, of course, be appreciated that in the development of any such actual implementation, numerous implementation-specific decisions must be made in order to achieve the developer's specific goals, such as compliance with application and business related constraints, and that these specific goals will vary from one implementation to another and from one developer to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking of engineering for those of ordinary skill in the art having the benefit of this disclosure.

FIG. 5illustrates a cut out side view of a portion of a printed circuit board according to an embodiment. The printed circuit board102is manufactured using a selective segment via plating process, an embodiment of which is described in relation toFIGS. 6-13. The printed circuit board102includes a plurality of stacked layers, the layers made of non-conductive layers104,106and conductive layers108. The non-conductive layers can be made of prepreg or base material that is part of a core structure. Each exemplary core structure shown in the laminated stack ofFIG. 5includes a non-conductive layer104, such as a base material, and a conductive layer108on each surface of the non-conductive layer104. It is understood that alternative core structures can be used which include a conductive layer on only one surface of the non-conductive layer. A plug subassembly140is a core structure plugged with a plating resist material. A laminated stack is formed by stacking multiple core structures and the plug subassembly with intervening prepreg and then laminating the stack. Any conventional lamination technique can be used. The exemplary laminated stack shown inFIG. 5has two core structures. It is understood that the laminated stack can be made having more or less than two core structures. A via110is formed by drilling a hole through the laminated stack and plating the wall of the hole with electrically conductive material, such as copper. The resulting plating112interconnects select conductive layers108. A plug subassembly140is selectively positioned during formation of the laminated stack to divide the printed circuit board102into segments120and130. The plug140includes plating resist118that prohibits formation of the plating112in cavity or void114during the plating process. As a result, the plating112in the segment120is disconnected from the plating112in the segment130. This results in the via110have two electrically isolated segments120and130. A segment can also be referred to as a net, which is an electrical sub-circuit. Each segment provides an independent electrical connection to a pin inserted into the via. As such, the printed circuit board having multiple segments is a multi-net structure.

In this embodiment, portions of the plating112, referred to as stubs116, are left extending from the conducting layers most proximate the void114. The stubs116have a well defined and short stub length SL which is defined as the distance between the conductive layer108most proximate the void114and the remaining plating resist118.

The number of layers in the PCB102and the position of the plug140within the laminated stack shown inFIG. 5is for exemplary purposes only. The selective segment via plating process allows freedom in interconnecting various sequential inner conductive layers as separate segments within the same via. In the exemplary configuration shown inFIG. 5, the top three conductive layers are interconnected as one segment, and the bottom three conductive layers are interconnected as another segment. It is understood that not all segments need have the same number of interconnected conductive layers. It is also understood that a segment can have more or less than three interconnected conductive segments. In the exemplary configuration shown inFIG. 5, a single plug140is interspersed within the printed circuit board102. Alternatively, multiple such plugs can be interspersed within the printed circuit board. Inclusion of additional plugs results in additional segments being formed.

FIGS. 6-13illustrate various steps in the selective segment via plating process used to manufacture the printed circuit board102inFIG. 5. Each of theFIGS. 6-13illustrates a cut out side view of the printed circuit board according to the various process steps. InFIG. 6, an exemplary core structure is shown. The core structure is a metal clad base material including a non-conductive base material layer104and conductive layers108formed on both opposing surfaces. It is understood that an alternative core structure can be used which includes a conductive layer on only one surface of the non-conductive layer.

InFIG. 7, a hole is drilled through the conductive layers108and the core layer104to form a via122. In some embodiments, the walls of the via122are plated, such as with copper. InFIG. 8, the conductive layers108are pattern etched to form conductive interconnects as desired. Alternatively, the conductive layers108are already pattern etched during fabrication of the core structure inFIG. 6. The via122is then plugged with plating resist118, such as liquid photoimageable plating resist. It is understood that other types of plating resist can be used that are resistant to a subsequent via wall plating step. In some embodiments, a portion of the plating resist118overlaps a portion of the conductive layers108surrounding the via122. The resulting structure forms the basis for the plug140.

InFIG. 9, multiple core structures are fabricated, and the core structures and the plug subassembly are stacked with intervening non-conductive layers106. In the exemplary configuration shown inFIG. 9, additional conductive layers108and intervening non-conductive layers106are added to the top and bottom of the stack. A single lamination step results in the laminated stack shown inFIG. 9. The additional conductive layers108on the top and bottom of the laminated stack are pattern etched.

InFIG. 10, a hole is drilled through the laminated stack ofFIG. 9to form via110. A diameter of the via110is smaller than a diameter of the via122(FIG. 7) that is plugged with plating resist118. As a result, formation of the via110leaves a layer of plating resist118on the side wall of the via110in the area of the plug140.

InFIG. 11, a desmear process is performed to remove residue, such as residual particles from the drilling of via110. Next, an electroless plating process is performed to form plating112′ on the side walls of the via110. In some embodiments, copper is used as the plating material. It is understood that other plating materials can be used. The plating112′ forms an interconnect with the various conductive layers108, except within the area of the plug140where the plating resist118provides a barrier. In the area of the plug140, the plating112′ is formed on the plating resist118.

InFIG. 12, a plating resist stripping process is performed. During the plating resist stripping process, both the plating112′ in the area of the plug140and a portion of the plating resist material118is removed. The plating112′ deposited during the electroless plating process inFIG. 11does not deposit well onto the plating resist118and therefore the plating resist118is not completely covered by the plating112′. Also, the adhesion bond between the plating112′ and the plating resist118is not as strong as the adhesion bond between the plating112′ and the other layers exposed in the via. As such, during the plating resist stripping process, the stripping chemistry attacks the plating resist118at locations lacking coverage by the plating112′. As the plating resist118dissolves, there is no support for the portion of the plating112′ deposited on the plating resist118and this portion of the plating112′ is removed. A residual amount of plating resist118remains after the plating resist stripping step. Stripping of the portion of the plating112′ in the plug area140results in a cavity surrounding the via and a void114in the plating112′. This discontinuity in the plating112′ results in the formation of plating stubs116′. However, the stubs116′ are disconnected from the conductive layers108in the plug area140, as shown inFIG. 12. The conductive layers108within the plug area140are recessed from the via110.

InFIG. 13, an electroplating process is performed resulting in a thicker plating112on the side walls of the via110. In some embodiments, copper is used as the plating material. As the exposed surfaces in the void114are not electrically connected, there is no plating on the exposed surfaces during the electroplating process, resulting in electrically isolated segments120and130.

In some embodiments, the plug is formed without conductive layers. In this case, a via is drilled into a layer of the core structure non-conductive layer, and the via is plugged with the plating resist. A portion of the plating resist may or may not overlap the core structure non-conductive layer surrounding the via.FIG. 14illustrates a cut out side view of a portion of a printed circuit board according to another embodiment. The printed circuit board202includes a plurality of stacked layers, the layers made of non-conductive layers204,206and conductive layers208laminated to a plug240to form a laminated stack with plated via210in a similar manner as previously described. In contrast to the previous embodiments, the plug240is formed without conductive layers coupled to either opposing surface of a core structure non-conductive layer. The plug240is formed similarly as the plug140inFIGS. 6-8but without the inclusion of the conductive layers. The resulting plug240is a core structure non-conductive layer having a plating resist filled via. In the exemplary embodiment shown inFIG. 14, the plating resist stripping step does not entirely remove all of the plating resist218, only enough to form voids214. As a result, plating212does not form in the recessed area of the void214during the subsequent electroplating step.

FIG. 14also illustrates an additional functionality where the plug is selectively positioned toward the “back” of the printed circuit board, thereby effectively isolating a select number of conductive layers at the back side, for example segment230, from the segment220in a manner similar to back drilling. However, in the case of the selective segment via plating process, the lengths of the resulting stubs216are well defined and are greatly minimized in length relative to the back drilling process.

As mentioned above, the plug subassembly can be configured to include plating on the side wall of the via. In this embodiment, the plug can function as a separate segment.FIG. 15illustrates a cut out side view of a portion of a printed circuit board according to yet another embodiment. The printed circuit board302includes a plurality of stacked layers, the layers made of non-conductive layers304,306and conductive layers308laminated to a plug340to form a laminated stack with plated via310in a similar manner as previously described. In this embodiment, the plug340is formed similarly as the plug140inFIGS. 6-8except that the via in the plug is first plated before being plugged with plating resist. The resulting plug340includes plating313that forms an interconnect with the conductive layers308of the plug340. The plating resist stripping step does not entirely remove all of the plating resist318, only enough to form voids314. As a result, plating312does not form in the recessed area of the void314during the subsequent eletroplating step, and as such electrically isolated segments320and330are formed. Also, since the conductive layers308in the area of the plug340are electrically interconnected by plating313, the conductive layers in the plug340form an electrically isolated segment.

It is understood that the various structural configurations and the position of the plugs shown in the embodiments ofFIGS. 6-15can be interchanged according to a specific application and application requirement.

The selective segment via plating process allows freedom in connecting innerlayers as separate segments within a via. The selective segment via plating process can replace back drill and sequential lamination processes while achieving the same design as these two processes. This saves running cost and shortens PCB processing time. Compared to uncontrollable stub length in the conventional back drill process, the selective segment via plating process provides for controlled and reproducible stub length which is important in signal transfer integrity. A plating stub is a conductive portion of the via plating not connected in series with the circuit. By making it shorter, signal reflection and degradation can be minimized as signal travels along the via. Elimination of a back drilling step also conserves useable real estate on the printed circuit board as the physical size of the drill bit requires additional spacing of adjacently drilled holes. Compared to sequential lamination, the selective segment via plating process requires a single assembly lamination which gives exact via alignment through the entire thickness of the printed circuit board, which provides better overall layer to layer registration and hence more room for circuitry routing. The selective segment via plating process also enables a one-time drilling step.