Nonvolatile memory device and method of fabricating the same

Provided are a nonvolatile memory device having a vertical folding structure and a method of manufacturing the nonvolatile memory device. A semiconductor structure includes first and second portions that are substantially vertical. A plurality of memory cells are arranged along the first and second portions of the semiconductor structure and are serially connected.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to Korean Patent Application No. 10-2009-0011207, filed on Feb. 11, 2009, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

BACKGROUND

Example embodiments relate to a semiconductor device, and more particularly, to a nonvolatile memory device.

2. Description of the Related Art

Electronic appliances are being reduced in size, but require high capacity data processing at the same time. Accordingly, a nonvolatile memory device used in the electronic appliances is reduced in volume. Thus, a nonvolatile memory device having a vertical structure instead of a planar structure may be considered to be used in the electronic appliances.

However, manufacturing a nonvolatile memory device having a vertical structure is complicated and, thus, price competitiveness and reliability thereof may be decreased.

SUMMARY

At least one example embodiment includes a nonvolatile memory device, with increased reliability and economic efficiency, and a method of manufacturing the nonvolatile memory device.

According to one or more example embodiment, a nonvolatile memory device includes a substrate, a semiconductor structure on the substrate, the semiconductor structure including first and second portions that are substantially vertical. A plurality of memory cells are arranged separately from each other along the first and second portions of the semiconductor structure and are serially connected to one another.

The nonvolatile memory device may further include a buried insulation layer disposed between the first and second portions of the semiconductor structure, and the plurality of memory cells are disposed on the first and second portions of the semiconductor structure on the opposite side of the buried insulation layer.

The nonvolatile memory device may further include a plurality of interlayer insulation layers formed between the plurality of memory cells. The semiconductor structure may further include first and second peak portions that are extended from an upper end of the first and second portions on uppermost portions on the plurality of the interlayer insulation layers.

The nonvolatile memory device may further include a string selection transistor on the first peak portion of the semiconductor structures and a grounding selection transistor on the second peak portion of the semiconductor structure.

The plurality of memory cells may have a vertical channel structure that extends along the first and second portions of the semiconductor structure, and the string selection transistor and the grounding selection transistor may include a planar channel structure that extends along the first and second peak portions of the semiconductor structure.

According to at least one example embodiment a method of manufacturing a nonvolatile memory device includes forming a semiconductor structure on the substrate, the semiconductor portion includes first and second portions that are vertical, and forming a plurality of memory cells that are separately arranged along the first and second portions of the semiconductor structure and are serially connected to one another.

A plurality of interlayer insulation layers and a plurality of sacrificial layers may be alternately stacked on the substrate and at least one trench is formed by etching the plurality of the interlayer insulation layers and the plurality of sacrificial layers. An amorphous semiconductor layer may be formed on an inner surface of the at least one trench. In addition, the semiconductor structure may be formed by crystallizing the amorphous semiconductor layer.

The amorphous semiconductor layer may be crystallized by electron beam annealing.

DETAILED DESCRIPTION

Example embodiments will now be described more fully with reference to the accompanying drawings. Many alternate forms may be embodied and example embodiments should not be construed as limited to example embodiments set forth herein. In the drawings, the thicknesses of layers and regions may be exaggerated for clarity, and like reference numerals refer to like elements.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof. Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein to describe one element or a relationship between a feature and another element or feature as illustrated in the figures. It will be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the Figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, for example, the term “below” can encompass both an orientation which is above as well as below. The device may be otherwise oriented (rotated 90 degrees or viewed or referenced at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

It should also be noted that in some alternative implementations, the functions/operations noted may occur out of the order noted in the figures. For example, two figures shown in succession may in fact be executed substantially concurrently, or may sometimes be executed in reverse order, depending upon the functions/operations involved.

FIG. 1is a cross-sectional view illustrating a nonvolatile memory device according to an example embodiment, andFIG. 2is a circuit diagram illustrating the nonvolatile memory device ofFIG. 1according to an example embodiment.

Referring toFIG. 1, a substrate105may be provided. The substrate105may include a semiconductor material such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI oxide semiconductor. Examples of Group IV semiconductor include silicon, germanium, and silicon-germanium. The substrate105may be a bulk wafer or an epitaxial layer.

At least one semiconductor structure130amay be formed to have a folding structure that is vertically extended on the substrate105. For example, the semiconductor structure130amay include a bottom portion31, a first portion32, a second portion33, a first peak portion34, and a second peak portion35. The bottom portion31is disposed on the substrate105, and the first and second portions32and33may be vertically extended from both end portions of the bottom portion31above the substrate105. A buried insulation layer132may be formed on the bottom portion31so as to fill a space between the first and second portions32and33.

The first peak portion34may be extended substantially horizontally from an upper end of the first portion32, and the second peak portion35may be extended substantially horizontally from an upper end of the second portion33. The first and second peak portions34and35may be extended away from the first and second portions32and33, respectively. The first and second peak portions34and35may be connected to a bit line BL and a common source line CSL, respectively, as illustrated inFIG. 2.

A plurality of control gate electrodes165may be disposed separately from each other along the first and second portions32and33. For example, the control gate electrodes165may be symmetrically arranged on sides of the first and second portions32and33opposite where the buried insulation layer132is located. A number of the control gate electrodes165may be appropriately selected according to the capacity of the nonvolatile memory device, and is not limited to the number of the control gate electrodes165shown inFIG. 1.

A plurality of storage media150may be provided between the control gate electrodes165and the first and second portions32and33. Each of the plurality of storage media150may include a tunneling insulation layer142on the first and second portions32and33, a charge storage layer144on the tunneling insulation layer142, and a blocking insulation layer146on the charge storage layer144.

A plurality of interlayer insulation layers115may be provided between the stacked control gate electrodes165. Moreover, each of the plurality of storage media150may be between a corresponding one of the plurality of control gate electrodes165and one of the plurality of interlayer insulation layers115. The first and second peak portions34and35may be disposed on an uppermost portion of the interlayer insulation layers115. Meanwhile, control gate electrodes165disposed on the same layer may be separated from one another by a device isolation layer168.

Referring toFIGS. 1 and 2, the control gate electrodes165and the storage media150may form memory cells MC0-MCn. Accordingly, the memory cells MC0-MCn may be separately arranged along the first and second portions32and33and serially connected to one another. The control gate electrodes165may be coupled to words lines WL0-WLn.

The storage media150may be connected to one another along the first and second portions32and33. For example, the storage media150may be extended so as to surround the control gate electrodes165from surfaces of the first and second portions32and33, and then be extended along the first and second portions32and33and the interlayer insulation layers115. That is, the storage media150may be curved over the first and second portions32and33.

A PN type junction source/drain area which is formed by impurity doping may not be formed near surfaces of the first and second portions31and32between the control gate electrodes165. Accordingly, the semiconductor structure130amay be continuously doped with identical conductive impurities in order to form a well or a channel. In this case, the memory cells MC0-MCn may be connected to each other during a programming/reading operation by using a field effect type source/drain. A surface of the semiconductor structure130abetween the memory cells MC0-MCn may be turned on by a lateral electric field of the control gate electrodes165, that is, a fringing field.

The charge storage layers144may have charge storage capability. For example, the charge storage layers144may be a trap type, and include, for example, a silicon nitride layer, quantum dots, or nanocrystals. The quantum dots or nanocrystals may be formed of a conductor, such as, fine particles of a metal or a semiconductor. Alternatively, the charge storage layers144may be a floating type, and include a doped polysilicon. When the charge storage layers144are the floating type, they are separated from each other. The tunneling insulation layers142and the blocking insulation layers146may include an oxide layer, a nitride layer, or a high-k dielectric layer. The high-k dielectric layer may refer to a dielectric layer having higher dielectric constant than that of an oxide layer or a nitride layer.

A string selection gate electrode180may be provided on the first peak portion34, and a grounding selection gate electrode185may be provided on the second peak portion35. A gate insulation layer170may be provided between the string selection gate electrode180and the first peak portion34and between the grounding selection gate electrode185and the second peak portion35.

Referring toFIGS. 1 and 2, a stack structure of the string selection gate electrode180and the gate insulation layer170may form a string selection transistor TS, and a stack structure of the grounding selection gate electrode180and the gate insulation layer170may form a grounding selection transistor TG. The string selection gate electrode180may be coupled to a string selection line SSL, and the grounding selection gate electrode185may be coupled to a grounding selection line GSL.

As described above, the memory cells MC0-MCn may have a vertical channel structure extending vertically along the first and second portions32and33. On the other hand, the string selection transistor TS and the grounding selection transistor TG may have a horizontal channel structure extending in a direction parallel to the substrate105.

The string selection transistor TS, the memory cells MC0-MCn, and the grounding selection transistor TG may be serially connected, thereby forming a NAND string NS. According to example embodiments, a plurality of NAND strings may be arranged in a matrix.

Referring toFIG. 2, for a programming operation, 0 V is applied to the bit line BL, an on voltage is applied to the string selection line SSL, and an off voltage is applied to the grounding selection line GSL. An on voltage may be larger than or equal to a threshold voltage of the string selection transistor TS in order to turn on the string selection transistor TS, and an off voltage may be smaller than a threshold voltage of the grounding selection transistor TG in order to turn off the grounding selection transistor TG. Among the memory cells MC0-MCn, a programming voltage may be applied to selected memory cells MC0-MCn, and a pass voltage may be applied to the rest of the memory cells MC0-MCn. Charges may be injected into the memory cells MC0-MCn by F-N tunneling through the programming voltage. The pass voltage may be higher than a threshold voltage of the memory cells MC0-MCn.

For a reading operation, a reading voltage may be applied to the bit line BL, and an on voltage may be applied to the string selection line SSL and the grounding selection line GSL. Among the memory cells MC0-MCn, a reference voltage may be applied to selected memory cells MC0-MCn, and a pass voltage may be applied to the rest of the memory cells MC0-MCn.

For an erasing operation, an erasing voltage may be applied to bodies of the memory cells MC0-MCn, and 0 V may be applied to word lines WL0, WL1WLn−1, and WLn. Accordingly, data of the memory cells MC0-MCn may be erased at once.

As the memory cells MC0-MCn are arranged in a folding structure, a vertical height of the NAND string may be reduced. Accordingly, the nonvolatile memory device may have a vertical structure with an adjusted height. Thus, reliability of the nonvolatile memory device may be increased.

FIGS. 3 through 12are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device according to an example embodiment. The method illustrated inFIGS. 3 through 12may be used to form the nonvolatile memory device ofFIG. 1.

Referring toFIG. 3, interlayer insulation layers115and sacrificial layers120may be alternately stacked on the substrate105. The sacrificial layers120may have an etching selectivity with respect to the interlayer insulation layers115. For example, the interlayer insulation layers115may be an oxide, and the sacrificial layers120may be a nitride.

Referring toFIG. 4, the interlayer insulation layers115and the sacrificial layers120may be etched to form a plurality of first trenches125. For example, the first trenches125may be formed by using photolithography and etching.

Referring toFIG. 5, an amorphous semiconductor layer130may be formed on an inner surface of the first trenches125and an uppermost portion of the interlayer insulation layers115. Next, a buried insulation layer132may be formed on the amorphous semiconductor layer130so as to fill the first trenches125. For example, the amorphous semiconductor layer130and the buried insulation layer132may be formed using a chemical vapor deposition (CVD) method.

Referring toFIG. 6, at least one second trench135may be formed by etching the interlayer insulating layers115and the sacrificial layers120that are interposed between portions of the amorphous semiconductor layer130, the amorphous semiconductor layer130and the buried insulation layer132. For example, the second trench135may be formed by using photolithography and etching.

Referring toFIG. 7, while maintaining the interlayer insulation layers115and the buried insulation layers132, the sacrificial layers120may be selectively removed. For example, by using an isotropic etching method, an etchant may be penetrated from the second trench135, between the interlayer insulation layers115. For example, the isotropic etching method may include a wet etching process or a chemical dry etching process. Accordingly, the sacrificial layers120between the interlayer insulation layers115are removed and, thus, a plurality of tunnels140that are connected to the second trench135may be formed. Sidewalls of the amorphous semiconductor layers130may be exposed by the tunnels140.

Referring toFIG. 8, the plurality of storage media150may be formed on the interlayer insulation layers115and the sidewalls of the amorphous semiconductor layer130that are exposed by the second trench135(seeFIG. 7) and the tunnels140(seeFIG. 7). The plurality of storage media150may be formed by sequentially depositing a tunneling insulation layer142, the charge storage layer144, and the blocking insulation layer146. Next, a conductive layer155may be formed to fill the second trench135(seeFIG. 7) and the tunnels140. For example, the plurality of storage media150and the conductive layer155may be formed by using a CVD method or a plating method with high step coverage.

Accordingly, the height of the second trench135is lowered by half than that of a non-folding structure and, thus, an aspect ratio thereof is reduced. Accordingly, filling efficiency of the plurality of storage media150and the conductive layer155may be increased.

Referring toFIG. 9, the plurality of control gate electrodes165may be formed by, selectively etching the conductive layer155(seeFIG. 8) exposed by the second trench135(seeFIG. 7). Accordingly, the control gate electrodes165may be separated from one another.

Referring toFIG. 10, the semiconductor structure130amay be formed by crystallizing the amorphous semiconductor layer130ofFIG. 9by using electron beam annealing. The semiconductor structure130amay include the bottom portion31, the first and second portions32and33, and the first and second peak portions34and35.

FIG. 13is a schematic view illustrating an example embodiment of an electron beam extracting apparatus that is used in an operation illustrated inFIG. 10of the manufacturing method of the nonvolatile memory device. The electron beam annealing may be performed by using the electron beam extracting apparatus illustrated inFIG. 13. Plasma may be formed on a substrate under an appropriate power condition and then an electron beam may be extracted through a grid.

By annealing the amorphous semiconductor layer130(seeFIG. 9) by using the electron beam, heat may be transmitted from an upper portion of the amorphous semiconductor layer130. Consequently, a semiconductor structure130ahaving a uniform crystalline structure may be formed by reducing a size of nucleation on the amorphous semiconductor layer130.

Referring toFIG. 11, the device isolation layer168may be formed between the separated control gate electrodes165to separate them from one another. Next, the gate insulation layer170and a second conductive layer175may be formed on the first peak portion34and the second peak portion35.

Referring toFIG. 12, the string selection gate electrode180and the grounding selection gate electrode185may be formed by patterning the second conductive layer175. The second conductive layer175may be patterned by using photolithography and etching.

FIG. 14is a block diagram illustrating a nonvolatile memory200according to an example embodiment.

Referring toFIG. 14, a NAND cell array250may be coupled to a core circuit unit270. For example, the NAND cell array250may include the nonvolatile memory device shown inFIG. 1. The core circuit unit270may include a control logic271, a row decoder272, a column decoder273, a sense amplifier274, and a page buffer275.

The control logic271may communicate with the row decoder272, the column decoder273, and the page buffer275. The row decoder272may communicate with the NAND cell array250having a stack structure, via string selection lines SSL, word lines WL, and grounding selection lines GSL. The column decoder273may communicate with the NAND cell array250via bit lines BL. The sense amplifier274may be connected to receive an output from the column decoder273when a signal is output from the NAND cell array250.

For example, the control logic271may transmit a row address signal to the row decoder272, and the row decoder272may decode the row address signal and transmit the same to the string selection lines SSL, the word lines WL, and the grounding selection lines GSL. The control logic271may transmit a column address signal to the column decoder273or the page buffer275, and the column decoder273may decode the column address signal and transmits the same to the NAND cell array250via the bit lines BL. Signals of the stack type NAND cell array250may be transmitted to the sense amplifier274via the column decoder273, and be amplified and transmitted through the page buffer275to the control logic271.

FIG. 15is a schematic view illustrating a memory card400according to an example embodiment.

Referring toFIG. 15, the memory card400may include a controller410and a memory unit420in a housing430. The controller410and the memory unit420may exchange electrical signals with each other. For example, the memory unit420and the controller410may transmit and receive data to/from each other according to a command of the controller410. Accordingly, the memory card400may store data in the memory unit420or output data from the memory unit420to the outside.

For example, the memory unit420may include the nonvolatile memory device200ofFIG. 14. The memory card400may be used as a data storage medium of various types of portable appliances. For example, the memory card400may include a multi media card (MMC) or a secure digital (SD) card.

FIG. 16is a block diagram illustrating an electronic system500according to an example embodiment.

Referring toFIG. 16, the electronic system500may include a processor510, an input/output unit530, and a memory unit520. The processor510, the input/output unit530and the memory unit520may process data communication with one another via a bus540. The processor510may execute programs and control the electronic system500. The input/output unit530may be used to input or output data of the electronic system500. The electronic system500may be connected to an external device (e.g., a personal computer or a network) by using the input/output unit530and exchange data with the external device. The memory unit520may store codes and data for operating the processor510. For example, the memory unit520may include the nonvolatile memory device200ofFIG. 14.

For example, the electronic system500may constitute various types of electronic controllers that require the memory unit520. For example, the electronic system500may be used in a mobile phone, an MP3 player, a navigation device, a solid state disk (SSD), or other household appliances.

It should be understood that example embodiments described therein should be considered in a descriptive sense only and not for purposes of limitation. While example embodiments have been shown and described, it will be understood that various changes in form and details may be made without departing from the spirit and scope of the following claims.