Voltage level shifter circuit

A voltage level shifter circuit is provided. A high power voltage is input to a first power voltage terminal, an enable signal is input to an enable terminal, and an intermediate voltage level between the first power voltage and a high enable signal voltage is input to a second power voltage terminal. First and second inverters are connected to the enable terminal. A first transistor has a source connected to the second inverter. A second transistor has a drain connected to a drain of the first transistor, a source connected to the second power voltage terminal, and a gate connected to an output terminal of the first inverter. Third and fourth transistors have gates connected to the outputs of the first and second transistors, the fourth transistor having a source connected to the first power voltage terminal.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims the benefit of priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2007-0090757, filed on Sep. 7, 2007, the entire contents of which are incorporated herein by reference.

BACKGROUND

Embodiments of the invention relate to voltage level shifter circuits.

Semiconductor memory devices are widely used, a typical example of which is an electrically erasable programmable read-only memory (EEPROM) that can perform write/read/erase operations using different control voltages. Such a memory device has three voltage terminals CG, RBL and TG for data write/read/erase operations, and is connected to a control circuit that transfers control signals to the voltage terminals. To this end, a voltage level shifter circuit is used to receive the control signals from the control circuit, to selectively shift the voltage of the control signal into a high-voltage level, and to transfer the same to the memory device.

FIG. 1is a circuit diagram of a voltage level shifter circuit10.

Referring toFIG. 1, the voltage level shifter circuit10includes a power voltage terminal VPP to which a power voltage is applied; an output terminal OUT for transferring an output signal to the outside; an enable terminal ENb; and four transistors11,12,13and14for controlling the voltage of the output signal.

The sources of the first and second transistors11and12are connected to the power voltage terminal VPP, and the gate of the first transistor11is connected to the drain of the second transistor12. Also, the gate of the second transistor12is connected to the drain of the first transistor11to form a coupling circuit, and the drain of the second transistor12is connected to the output terminal OUT and the drain of the fourth transistor14.

The drain of the first transistor11is connected to the drain of the third transistor13, and the sources of the third and fourth transistors13and14are connected to a ground terminal. The gate of the third transistor13is connected to the enable terminal ENb and the gate of the fourth transistor14, and an inverter15is connected between the gate of the third transistor13and the gate of the fourth transistor14.

The first and second transistors11and12are PMOS transistors, and the third and fourth transistors13and14are NMOS transistors.

The voltage level shifter circuit10operates as follows.

First, when a low-voltage (VSS) signal is input to the enable terminal ENb, the low-voltage signal is applied to the gate of the third transistor13to turn off the third transistor13. Also, the low-voltage signal applied to the enable terminal ENb is inverted by the inverter15into a high-voltage (VDD) signal, and the high-voltage signal is input to the gate of the fourth transistor14. Thus, the fourth transistor14is turned on, and a low-voltage signal is transferred through the fourth transistor14to the output terminal OUT. At this point, the low-voltage signal transferred to the output terminal OUT is also input to the gate of the first transistor11connected to the output terminal OUT, and the first transistor11is turned on. Thus, a high-voltage signal is input to the gate of the second transistor12connected to the drain of the first transistor11. When the high-voltage signal is input to the gate, the second transistor12is turned off.

Second, when a high-voltage signal is input to the enable terminal ENb, a high-voltage signal is applied to the gate of the third transistor130to turn on the third transistor13. When the third transistor13is turned on, a low-voltage signal is input to the gate of the second transistor12connected to the drain of the third transistor13. Thus, the second transistor12is turned on and a high-voltage signal (VPP) is applied to the output terminal OUT connected to the drain of the second transistor12. Also, the high-voltage signal is input to the gate of the first transistor11which is connected to the output terminal OUT, and the first transistor11is turned off. Thus, the high-voltage signal applied to the enable terminal ENb is inverted by the inverter15into a low-voltage signal, and the fourth transistor14is turned off.

However, an enable signal of a lower voltage level is used according to the trend of the low power and the high integration of a semiconductor device. In this case, even when a high-voltage enable signal is applied, because its voltage level is relatively low, it can be difficult to satisfy a threshold voltage that enables a turn-on operation of a transistor.

For example, if an enable signal of about 5 V is compared with an enable signal of about 1.5 V, when 1.5 V signal is input to the enable terminal ENb, the third transistor13(that is, an NMOS transistor) may fail to properly turn on.

FIG. 2is a simulation graph of signals of the voltage level shifter circuit10when an enable signal a2of a high level (about 5 V) is applied thereto.FIG. 3is a simulation graph of signals of the voltage level shifter circuit10when an enable signal c2of a relatively low level (about 1.5 V) is applied thereto.

In the graphs ofFIGS. 2 and 3, the X (horizontal) axis represents a time axis and the Y (vertical) axis represents a voltage axis. Also, from the tops ofFIGS. 2 and 3, the first graphs (a1and c1) represent power voltage signals, the second graphs (a2and c2) represent enable signals, the third graphs (b1and d1) represent drain signals of the first transistor11, and the fourth graphs (b2and d2) represent output signals.

Referring toFIG. 2, when an enable signal a2of a high level (about 5 V) is applied, it can be seen that each signal is normally processed as described above. For example, if the enable signal a2is of high voltage, a drain signal b1of the first transistor11is of low voltage and an output signal b2is of high voltage.

However, referring toFIG. 3, when an enable signal c2of a relatively low level (about 1.5 V) is applied, the first transistor11does not necessarily operate normally. Thus, it can be seen that the voltage of the output signal d2is not necessarily a desired value (e.g., it may be unstable and/or may not be controlled). This causes a degradation in the operational reliability of the voltage level shifter circuit10.

SUMMARY

Embodiments of the invention provide a voltage level shifter circuit that enables transistors to be stably turned on/off according to the voltage states of an enable signal even when an enable signal of a relatively low voltage level is used, in accordance with high integration and low power trends in semiconductor devices.

In one embodiment, a voltage level shifter circuit may comprise a first power voltage terminal providing a first power voltage; an enable terminal receiving an enable signal; a second power voltage terminal providing an intermediate voltage level less than the first power voltage; first and second inverters connected to the enable terminal; a first transistor having a source connected to the second inverter; a second transistor having a drain connected to a drain of the first transistor, a source connected to the second power voltage terminal, and a gate connected to an output terminal of the first inverter; a third transistor having a gate connected to the drain of the first transistor; and a fourth transistor having a gate connected to the drain of the first transistor, a drain connected to a drain of the third transistor, and a source connected to the first power voltage terminal.

DETAILED DESCRIPTION OF THE EMBODIMENTS

An exemplary voltage level shifter circuit according to one or more embodiments will be described in detail with reference to the accompanying drawings.

FIG. 4is a circuit diagram of an exemplary voltage level shifter circuit100.

Referring toFIG. 4, the exemplary voltage level shifter circuit100includes a first power voltage terminal VPP, an output terminal OUT, an enable terminal ENb, a second power voltage terminal VCC1, a first inverter110, a second inverter120, a first transistor130, a second transistor140, a third transistor150, and a fourth transistor160.

A first power voltage having a relatively high voltage level (e.g., about 5 V or more, about 9 V or more, or about 12 V or more) is applied to the first power voltage terminal VPP. The output terminal OUT transfers an output signal (e.g., a power supply) to the outside (e.g., a programming and/or erasing circuit in a non-volatile memory such as an EEPROM or flash memory).

An enable signal for controlling the voltage of the output signal is input to the enable terminal ENb. A second power voltage with an intermediate voltage between the first power voltage and the high-voltage (Logic High, or binary “1”) enable signal is applied to the second power voltage terminal VCC1. The high voltage enable signal may have a value of from about 1.2 V to about 3 V (e.g., any value in that range, such as about 1.2 V, about 1.5 V, about 1.8 V, etc.). The intermediate voltage (e.g., VCC1) may have a value between the levels of the high voltage enable signal and the first power voltage, for example of from about 1.8 V to about 9 V (e.g., any value in that range, such as about 1.8 V, about 2.5 V, about 3.3 V, about 5 V, etc.).

Also, the first transistor130and the third transistor150are NMOS transistors and the second transistor140and the fourth transistor160are PMOS transistors.

The exemplary voltage level shifter circuit100according to various embodiments may be configured as follows.

The enable terminal ENb is connected through the first inverter110and the second inverter120to the source of the first transistor130. The drain of the first transistor130is connected to the drain of the second transistor140, and the source of the second transistor140is connected to the second power voltage terminal VCC1. Also, the gate of the first transistor130is connected to the second power voltage terminal VCC1and the substrate of the first transistor130is grounded. Alternatively, the gate of the first transistor130can be connected to the output of the first inverter110. In this alternative embodiment, the second inverter120may be eliminated, and the source of the first transistor130can be connected to ground (e.g., 0 V, or an actual or virtual ground potential).

The gate of the second transistor140is connected to the output of the first inverter110(e.g., between the first inverter110and the second inverter120).

A line connecting the first transistor130and the second transistor140(e.g., the drains or outputs of the first and second transistors130and140) may be branched and connected to the gate of the third transistor150and the gate of the fourth transistor160, and the drain of the third transistor150and the drain of the fourth transistor160are connected to the output terminal OUT.

The source of the third transistor150is grounded, and the source of the fourth transistor160is connected to the first power voltage terminal VPP.

In various embodiments, the first through fourth transistors generally have a size and/or one or more other characteristics (such as a gate oxide thickness) configured for operations at the voltages that are generally applied to them. For example, the first and second transistors130and140may have a gate oxide thickness configured for transistor operations at the intermediate voltage level (e.g., VCC1), and the third and fourth transistors150and160may have a gate oxide thickness configured for transistor operations at the first voltage level (e.g., VPP)

The exemplary voltage level shifter circuit100according to the various embodiments generally operates as follows.

First, when a low-voltage (VSS) signal (e.g., a binary logic “0”) is input to the enable terminal ENb, the first inverter110inverts the low-voltage signal into a high-voltage signal. Also, the second inverter120inverts the inverted high-voltage signal into a low-voltage signal and transfers the low-voltage signal to the source of the first transistor130.

The high-voltage signal inverted by the first inverter110is input to the gate of the second transistor140, and the second transistor140is turned off.

The signal inverted into a low-voltage state by the second inverter120is input to the source of the first transistor130, and the first transistor130transfers the low-voltage signal from the second inverter120to the gates of the third and fourth transistors150and160. Thus, a low-voltage signal is applied to a drain line of the first transistor130because the second transistor140is turned off.

Similarly, when the gate of the first transistor130is connected to the output of the first inverter110, a high-voltage logic signal from the first inverter110turns on the first transistor130, and the low-voltage logic signal from either the second inverter120or a ground potential can pass through the first transistor130to the drain or output of the first transistor130, in the alternative embodiment(s).

Because a branch line between the first transistor130and the second transistor140(e.g., the common output node of the first and second transistors130and140) is in a low-voltage state, the third transistor150(i.e., the NMOS transistor) is turned off and the fourth transistor160(i.e., the PMOS transistor) is turned on. Thus, a high-voltage signal (e.g., the first voltage level, or VPP) is output to the output terminal OUT branched between the third transistor150and the fourth transistor160(i.e., the CMOS inverter). That is, when a low-voltage enable signal is input to the voltage level shifter circuit100, a high-voltage output signal is generated therefrom, thereby making it possible to selectively increase a control voltage or power supply of a semiconductor memory device (e.g., for programming and/or erasing operations in an EEPROM or a flash memory).

Second, when a high-voltage signal is input to the enable terminal ENb, the high-voltage signal is inverted into a low-voltage state by the first inverter110and a low-voltage signal is input to the gate of the second transistor140. Also, the signal inverted into a low-voltage state by the first inverter110is inverted into a high-voltage signal by the second inverter120, and the inverted high-voltage signal is input to the source of the first transistor130. Meanwhile, the high-voltage signal inverted by the second inverter120is input to the source of the first transistor130, and the first transistor130outputs the high-voltage signal inverted by the second inverter120. Because the second transistor140is turned on and the second power voltage is applied to the branch line between the first transistor130and the second transistor140, it does not matter that the first transistor130is on. The second inverter120presents a high-impedance node that has essentially no effect when both the first and second transistors130and140are on.

Similarly, when the gate of the first transistor130is connected to the output of the first inverter110, a low-voltage logic signal from the first inverter110turns off the first transistor130, and the low-voltage logic signal from either the second inverter120or the ground potential does not pass through the first transistor130to the drain or output of the first transistor130, in the alternative embodiment(s).

Thus, the second power voltage is applied to the gates of the third transistor150and the fourth transistor160, and the third transistor150is turned on while the fourth transistor160is turned off. The output terminal OUT outputs a low-voltage signal (e.g., a ground potential, or 0 V) by the third transistor150.

That is, when a high-voltage enable signal is input to the exemplary voltage level shifter circuit100, a low-voltage output signal is generated therefrom, thereby making it possible to selectively pass a control voltage or power supply to circuits in a semiconductor memory device requiring such voltage (e.g., a circuit for programming and/or erasing operations in an EEPROM or flash memory). In this way, the voltage level shifter circuit100according to the embodiments uses the first power voltage and the second power voltage, and may remove the ground connected to the source of the first transistor130, thereby making it possible to apply an intermediate-voltage concept. Thus, even when an enable signal of a relatively low voltage level is used in accordance with the trends towards higher integration and lower power in semiconductor devices, the voltage level shifter circuit100according to the embodiments can maintain the output signal stably. For example, even when the signal level is lowered from about 5 V to 1.5 V, the enable signal enables a turn-on operation of the NMOS transistor.

FIG. 5is a simulation graph of signals of the exemplary voltage level shifter circuit100when an enable signal e2of a low level (about 1.5 V) is applied thereto. In the graph ofFIG. 5, the X (horizontal) axis represents a time axis, and the Y (vertical) axis represents a voltage axis. Also, from the top ofFIG. 5, the first graph (e1) represents a power voltage signal, the second graph (e2) represents an enable signal, the third graph (f1) represents a drain signal of the first transistor130, and the fourth graph (f2) represents an output signal.

Referring toFIG. 5, as described with reference toFIG. 2, when an enable signal e2of a low level (about 1.5 V) is applied, it can be seen that each signal is normally processed. For example, if the enable signal e2is of high voltage, a drain signal f1of the first transistor130is of low voltage and an output signal f2is of high voltage.

According to the embodiments, because the transistor can be stably turned on/off according to the voltage states of the enable signal even when an enable signal of a low voltage level is used, it is possible to enhance the operational reliability of the voltage level shifter circuit.

Also, because the transistor can be operated even when a high-voltage enable signal with a voltage level lower than the threshold voltage of one or more of the transistors in the voltage level shifter circuit is applied, it is possible to implement a voltage level shifter circuit on a high-integration and low-power semiconductor device.