Level width based dynamic program step characteristic adjustment

A level width corresponding to a group of memory cells of a memory component is determined. The determined level width and a target level width is compared. In response to the determined level width being different than the target level width, one or more program step characteristics are adjusted to adjust the determined level width to the target level width.

TECHNICAL FIELD

Embodiments of the disclosure relate generally to memory sub-systems, and more specifically, relate to level width based program step characteristic adjustment.

BACKGROUND

A memory sub-system can be a storage system, such as a solid-state drive (SSD), and can include one or more memory components that store data. The memory components can be, for example, non-volatile memory components and volatile memory components. In general, a host system can utilize a memory sub-system to store data at the memory components and to retrieve data from the memory components.

DETAILED DESCRIPTION

Aspects of the present disclosure are directed to managing level width within a memory sub-system. A memory sub-system is also hereinafter referred to as a “memory device.” An example of a memory sub-system is a storage system, such as a solid-state drive (SSD). In some embodiments, the memory sub-system is a hybrid memory/storage sub-system. In general, a host system can utilize a memory sub-system that includes one or more memory components. The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system.

In various memory sub-systems, programming cells can involve providing a programming signal to a group of cells (e.g., a page) to place them in target states, which correspond to respective stored data patterns. For example, the cells can be non-volatile flash memory cells configured to store one or more bits of data per cell. As an example, a programming signal used to program the cells can comprise a stepped voltage signal (e.g., voltage ramp) with each step having an associated step size and duration. The programming signal can be applied (e.g., to a word line) as a series of voltage pulses, for instance. The voltage pulses have various characteristics which can affect a level width associated with the programmed cells. Such characteristics include pulse magnitude, step size between pulses, and pulse duration, among various other characteristics.

As described further herein, a level width refers to a width (e.g., in voltage) of a threshold voltage (Vt) distribution corresponding to a state to which a number of memory cells are programmed. As such, a level width may be referred to herein as a distribution level width. The memory cells can be multilevel memory cell (MLCs) each programmable to multiple voltage levels (e.g., 4 levels, 8 levels, 16 levels, etc.) such that the cells can store multiple bits of data per cell (e.g., 2 bits, 3 bits, 4 bits, etc.). A level width for a group of programmed cells can refer to the width of a particular Vt distribution among multiple Vt distributions or can refer to a sum of level widths for up to all of the multiple Vt distributions corresponding to respective program states (e.g., voltage levels corresponding to respective program states) for a group of cells. As described further below, a level width can be determined (e.g., measured) at a particular bit error rate (BER), for example. The level width corresponding to a group of memory cells can be affected by various factors such as temperature, wear cycling (e.g., program/erase cycles), etc. Therefore, the level width(s) of a system can vary over time, which can affect system quality of service (QoS), reliability, and/or performance. In various instances, it can be beneficial to maintain a specified level width in order to maintain a particular system characteristic (e.g., QoS, error rate, etc.) across various environmental conditions and/or user workloads. However, it can also be beneficial to provide the ability to dynamically adjust a level width (e.g., to a target level width value) in order to change one or more system characteristics. For instance, it may be beneficial to provide one system, or components thereof, with a relatively high level width associated with low reliability (e.g., high bit error rate) and another system, or components thereof, with a relatively low level width associated with higher speed. It can also be beneficial to adjust the level width of a particular system or component thereof such that the system operates at different reliability levels and speed at different times.

Conventional memory sub-systems do not dynamically adjust level widths and/or are not be capable of adjusting the level widths in a predictable and/or controllable manner. Therefore, various conventional systems are not able to, for example, maintain a target level width with changing temperature and/or program/erase cycling.

In contrast, embodiments of the present disclosure address the above and other deficiencies by providing a memory sub-system capable of finely controlling (e.g., tuning) a level width in a more efficient manner as compared to previous approaches. For example, embodiments are capable of to achieving and maintaining a target level width by modifying one or more characteristics of voltage signals (e.g., pulses) used to program memory cells. Such a memory sub-system can provide various benefits such as those described above. For instance, embodiments can control a level width to maintain a particular level of quality, reliability, and/or performance of the system in various environmental conditions and/or user workloads.

FIG. 1illustrates an example computing environment101that includes a memory sub-system104in accordance with some embodiments of the present disclosure. The memory sub-system104can include media, such as memory components110. The memory components110can be volatile memory components, non-volatile memory components, or a combination of such. In some embodiments, the memory sub-system is a storage system. An example of a storage system is a SSD. In some embodiments, the memory sub-system104is a hybrid memory/storage sub-system. In general, the computing environment100can include a host system102that uses the memory sub-system104. For example, the host system102can write data to the memory sub-system104and read data from the memory sub-system104.

Host102can be a host system such as a personal laptop computer, a desktop computer, a digital camera, a mobile telephone, or a memory card reader, among various other types of hosts. Host102can include a system motherboard and/or backplane and can include a number of processors. Host102can also be a processing resource, such as where memory sub-system104is a memory device having an on-die controller (e.g.,108).

The host system102can be coupled to the memory sub-system104via a physical host interface106. As used herein, “coupled to” generally refers to a connection between components, which can be an indirect communicative connection or direct communicative connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc. Examples of a physical host interface include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, universal serial bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), etc. The physical host interface can be used to transmit data between the host system120and the memory104. The host system102can further utilize an NVM Express (NVMe) interface to access the memory components110when the memory sub-system104is coupled with the host system102by a PCIe interface. The physical host interface can provide an interface for passing control, address, data, and other signals between the memory sub-system104and the host system102. The memory components110can include a number of arrays of memory cells (e.g., non-volatile memory cells). The arrays can be flash arrays with a NAND architecture, for example. However, embodiments are not limited to a particular type of memory array or array architecture. Although floating-gate type flash memory cells in a NAND architecture are generally referred to herein, embodiments are not so limited. The memory cells can be grouped, for instance, into a number of blocks including a number of physical pages. A number of blocks can be included in a plane of memory cells and an array can include a number of planes. As one example, a memory device can be configured to store 8 KB (kilobytes) of user data per page, 128 pages of user data per block, 2048 blocks per plane, and 16 planes per device. The memory components110can also include additionally circuitry (not illustrated), such as control circuitry, buffers, address circuitry, etc.

In operation, data can be written to and/or read from memory (e.g., memory components110of system104) as a page of data, for example. As such, a page of data can be referred to as a data transfer size of the memory system. Data can be sent to/from a host (e.g., host102) in data segments referred to as sectors (e.g., host sectors). As such, a sector of data can be referred to as a data transfer size of the host.

The memory components110can include any combination of the different types of non-volatile memory components and/or volatile memory components. An example of non-volatile memory components includes a negative- and (NAND) type flash memory. The memory components110can include one or more arrays of memory cells such as single level cells (SLCs) or multi-level cells (MLCs) (e.g., triple level cells (TLCs) or quad-level cells (QLCs)). In some embodiments, a particular memory component can include both an SLC portion and a MLC portion of memory cells. Each of the memory cells can store one or more bits of data (e.g., data blocks) used by the host system102. Although non-volatile memory components such as NAND type flash memory are described, the memory components110can be based on various other types of memory such as a volatile memory. In some embodiments, the memory components110can be, but are not limited to, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase change memory (PCM), magneto random access memory (MRAM), negative- or (NOR) flash memory, electrically erasable programmable read-only memory (EEPROM), and a cross-point array of non-volatile memory cells. A cross-point array of non-volatile memory can perform bit storage based on a change of bulk resistance, in conjunction with a stackable cross-gridded data access array. Additionally, in contrast to many flash-based memories, cross-point non-volatile memory can perform a write in-place operation, where a non-volatile memory cell can be programmed without the non-volatile memory cell being previously erased. Furthermore, the memory cells of the memory components110can be grouped as memory pages or data blocks that can refer to a unit of the memory component used to store data.

As illustrated inFIG. 1, the memory sub-system104can include a controller108coupled to the host interface106and to the memory components110via a memory interface111. The controller108can be used to send data between the memory sub-system104and the host102. The memory interface111can be one of various interface types compliant with a particular standard such as Open NAND Flash interface (ONFi).

The controller108can communicate with the memory components110to perform operations such as reading data, writing data, or erasing data at the memory components110and other such operations. The controller108can include hardware such as one or more integrated circuits and/or discrete components, a buffer memory, or a combination thereof. The controller108can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor. The controller108can include a processor (e.g., processing device112) configured to execute instructions stored in local memory109. In the illustrated example, the local memory109of the controller108includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control operation of the memory sub-system104, including handling communications between the memory sub-system104and the host system102. In some embodiments, the local memory109can include memory registers storing memory pointers, fetched data, etc. The local memory109can also include read-only memory (ROM) for storing micro-code. While the example memory sub-system104inFIG. 1has been illustrated as including the controller108, in another embodiment of the present disclosure, a memory sub-system104may not include a controller108, and may instead rely upon external control (e.g., provided by an external host, such as by a processing device separate from the memory sub-system104).

The controller108can use and/or store various operating parameters associated with operating (e.g., programming and/or reading) the memory cells. Such operating parameters may be referred to as trim values and can include programming pulse magnitude, step size, pulse duration, program verify voltages, read voltages, etc. for various different operating processes. The different processes can include processes to program cells to store different quantities of bits, and different multiple pass programming process types (e.g., 2-pass, 3-pass, etc.). The controller108can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and/or correction (e.g., error-correcting code (ECC)) operations, encryption operations, caching operations, and address translations between a logical block address and a physical block address that are associated with the memory components110.

The memory sub-system104can also include additional circuitry or components that are not illustrated. For instance, the memory components110can include control circuitry, address circuitry (e.g., row and column decode circuitry), and/or input/output (I/O) circuitry by which they can communicate with controller108and/or host102. As an example, in some embodiments, the address circuitry can receive an address from the controller108and decode the address to access the memory components110.

In various embodiments, the controller108can include a level width adjustment component113that controls and/or communicates with a program step characteristic component115to determine and/or control one or more program step characteristics used to program cells. The program step characteristics can include, for example, various characteristics of voltage pulses used to program memory cells of the memory components110. The characteristic can be, for example, a voltage difference between (e.g., two consecutive) voltage pulses used to program memory cells. In another example, the characteristic can be a duration for which voltage pulse(s) are applied to program memory cells. As used herein, the voltage difference between voltage pulses can be referred to as a program step size, and the duration for which voltage pulse(s) are applied can be referred to as a program step duration.

The memory components110can include memory cells for the write or program operation, such as for incremental step pulse programming (ISPP). The memory cells can be programmed (via controller) via an ISPP process in which a series of pulses of increasing magnitude are applied to the cells (to their gates) to increase the stored charge by a particular amount until the target stored charge (Vt) is reached.

For example,FIG. 2illustrates threshold voltage (Vt) distributions of cells, which correspond to the charge stored on the charge storage structures of the memory cells, at various stages of one such incremental programming operation. Time214can represent a time at which the programming operation begins. Accordingly, as shown by Vt distribution216at time214, the Vt of all the cells is below the target Vt level (Vtarget)250. To program the memory cells to the desired target Vtarget250, a series of programming steps (e.g., voltage pulses) can be used at each of a number of subsequent times220,230, and240to increase the cell Vt levels as shown by distributions222,232, and242, respectively. After each programming step, a program verify operation can be performed to verify whether the cells being programmed have reached Vtarget250. As shown inFIG. 2, programming of the cells is completed at time240, as the Vt levels of all the cells have been increased to at or above the desired target Vt level250, the programming operation is completed.The amount by which the Vt distributions216,222,232, and242increase responsive to an applied programming pulse can depend on various factors such as the magnitude of the pulse and the duration for which the pulse is applied to the cells. Accordingly, the time to program a group of cells to desired states can vary depending upon the programming signal characteristics as well as the quantity of pulses. Additionally, as described further below, multiple programming passes can be used to program multiple logical page data to cells. For example, a first pass, which can be referred to as a lower page programming process, can be used to program one or more lower pages of data to a group of cells, and one or more subsequent programming passes can be used to program additional pages of data to the group of cells.

The diagram shown inFIG. 3illustrates threshold voltage (Vt) distributions associated with a programming process in accordance with embodiments of the present disclosure. In this example, the process is a two-pass programming process in which a lower page (e.g., lease significant bit) of a group of memory cells is programmed in a first programming pass and an upper page (e.g., middle bit) and extra page (e.g., most significant bit) of the group are programmed in a second programming pass. The first programming pass can be referred to as a lower page programming (LPP) process325, and the second programming pass can be referred to as an upper page programming and extra page programming process (UPP/EPP)329.

As described further below, each of the LPP process325and UPP/EPP process329can involve application of a series of programming pulses to a selected word line corresponding to the group of cells being programmed. As part of the LPP process325, the Vt of the memory cells are adjusted (e.g., from an erased Vt level) to one of two levels represented by Vt distributions330-1and330-2. The voltage levels are represented by Vt distributions, which can reflect a statistical average Vt level of cells programmed to a particular level. In this example, cells whose lower page is to store a bit value of “1” (e.g., LP=1) are programmed to distribution330-1during LPP process325, and cells whose lower page is to store a bit value of “0” (e.g., LP=0) are programmed to distribution330-2during LPP process325. A lower page is a lower order page and is programmed in the array of memory cells before higher order pages are programmed.

As part of the UPP/EPP process329, the Vt of the memory cells are adjusted to one of eight levels represented by Vt distributions334-1to334-8, which correspond to data states E1to E8, respectively, with each one of the data states E1to E8representing a different 3-bit stored data pattern. In this example, cells programmed to data state E1store data “111,” cells programmed to data state E2store data “011,” cells programmed to data state E3store data “001,” cells programmed to data state E4store data “101,” cells programmed to data state E5store data “100,” cells programmed to data state E6store data “000,” cells programmed to data state E7store data “010,” and cells programmed to data state E8store data “110.” While the example illustration includes a 2-pass programming, this is but one example. Additional quantities of program passes can be used.

FIG. 3also illustrates a level width336corresponding to data E1(e.g., respective voltage distribution334-1), and likewise, while not illustrated, additional level widths correspond to E2through E8(e.g., respective Vt distributions334-2through334-8). The level widths for cells programmed to one of states E1to E8can refer to the sum of the level widths. As described below in association withFIG. 4C, respective level widths can be measured at a particular (e.g., target) BER (e.g., BER443shown inFIG. 4C).

Particular level widths (such as level width336) can be determined for a group of memory cells. The group of cells can be, for example one or more pages of cells of the memory components110. The group of cells can also be one or more blocks of memory cells, such as blocks of cells erased together in a particular erase operation. The one or more pages and/or the one or more blocks can be from a particular memory component (e.g., die) or from multiple dies. The group of memory cells for which a level width is determined can be randomly selected or can be all of the pages of a memory component (e.g.,110) or system (e.g.,104), for instance; however, embodiments are not so limited. As described further herein, in a number of embodiments, a determined level width can be adjusted (e.g., increased or decreased) by adjusting one or more programming pulse characteristics to achieve a target level width for the group of memory cells. For example, the determined level width can be compared to the target level width, and at least one of a program step size and a program step duration can be adjusted in order to move the measured level width toward the target level width. In response to determining that the determined level width satisfies a threshold pertaining to the target level width, the step size and the program step duration can each be increased by a respective particular amount. In response to determining that the determined level width satisfies a threshold pertaining to the target level width, the step size and the program step duration can each be decreased by a respective particular amount.

Further details of measuring and adjusting the level width is described below in connection withFIG. 4-10.

FIG. 4A-Beach illustrate example programming signals in accordance with embodiments of the present disclosure. The example illustrations represent programming pulses applied to memory cells (e.g., to their gates) to increase the cell threshold voltages (Vts) to target levels.FIG. 4Aillustrates a number of pulses P1, P2, and P3associated with a programming operation having a particular PET464. As shown inFIG. 4A, each pulse has a pulse duration459, which may be referred to as a program step duration, and a program step size462between consecutive pulses.

The PET464can be associated with a series of pulses (e.g., P1, P2, P3) applied to a group of cells to place the cells of the group in respective target states. For example, the PET464can correspond for the amount of time to program each of a group of cells to one of the states E1to E8shown inFIG. 3. Memory systems in accordance with embodiments described herein can dynamically adjust (e.g., increase or decrease) the programming step size462and/or step duration459in order to achieve a desired level width adjustment (e.g., to maintain a desired level width). In at least one example, this dynamic increase or decrease can be performed by the program step characteristic component115to dynamically adjust or calibrate the programming step size462and/or duration459

FIG. 4Billustrates the programming operation shown inFIG. 4Aafter implementing a programming step adjustment. For comparison, the previous program step size and program step durations, such as462and459, respectively, inFIG. 4A, are illustrated. The adjusted program step size466is a calibrated or changed instance of the program step size462for replacing the program step size462. The adjusted program step size466is illustrated as being greater than the program step size462, however, adjustments can be an increase or a decrease in the program step size. Likewise, the adjusted program step duration467is a calibrated or changed instance of the program step duration459for replacing the program step duration459. The adjusted program step duration467is illustrated as being greater than the program step duration459, however, adjustments can be an increase or a decrease in the program step duration depending on a desired change in the level width. In the example shown inFIGS. 5A and 5B, the adjustments to the program step size466and the program step duration467result in a reduction in the PET464; however, embodiments are not so limited.

As described further below, a relationship exists between the adjustment of a program step size and the adjustment of the program step duration. For instance, the adjustment of the program step size can be in a particular proportion to the adjustment of the program step duration based on a relationship between the program step size and the program step duration. As a result, level width can be adjusted by a particular amount by adjusting the program step size and/or duration by particular amounts based on the determined proportional relationship between step size and step duration and therefore respective effects on level width.

In various embodiments, the level width can be used as a feedback measure within the system, with the adjustment of one or more program step characteristics being used to adjust the level width toward a target level width responsive to a determination that the measured level width is above or below the target level width. As an example, as a level width goes above a threshold level width, a program step size and/or a program step duration can be adjusted to decrease the level width corresponding to a group of cells. Vice versa, as a level width goes below a threshold level width, a program step size and/or a program step duration can be adjusted to increase the level width. Dynamically adjusting or calibrating the programming step size462, duration459to affect the level width is described further in association withFIGS. 5-8below.

FIG. 4Cillustrates a level width455between threshold voltage (Vt) distributions450-1and450-2of memory cells programmed in accordance with some embodiments of the present disclosure. The example Vt distributions450-1and450-2(collectively referred to as Vt distributions450) can be analogous to the Vt distributions shown inFIG. 3(e.g., Vt distributions334-1334-8) and can correspond to a particular page of memory cells.

As illustrated inFIG. 4C, the level width455can be a distance between adjacent edges of the Vt distributions450-1450-2. The level width between Vt distributions can be calculated, for example, by determining a location of the Vt distribution edges (e.g., on x-axis) by performing multiple read operations on a page of programmed cells using different read voltages and monitoring the bit error rate to determine the read voltage at which a minimum BER occurs for the page. In a number of embodiments, and as described inFIG. 4C, a level width (e.g.,455) can be determined based on a particular (e.g., target) BER for a page of cells. The target BER for purposes of level width determination can be user selected and can be 1E-3 or 1E-4, for instance. As an example, determining the level width455can include reading the page of cells using a first read voltage453(shown as “sample 1”). The first read voltage453can be a trim value used to distinguish between cells programmed to state450-1and state450-2. In this example, the read using read voltage453results in a BER below the target BER. A subsequent read of the page of cells using a different (e.g., lower) read voltage451(shown as “sample 2”) is performed. In this example, the read at451results in a BER above the target BER. Since the read at read voltage451corresponds to a BER above the target BER and the read at read voltage453corresponds to a BER below the target BER, the x-axis location (e.g., voltage) corresponding to the target BER443can be determined by interpolating between sample 1 and sample 2.

For the above example, the interpolation between sample 1 and sample 2 to determine the relative x-axis location corresponding to the target BER (e.g., “TargetBERx”) can be demonstrated by the formula:
TargetBERx=Sample1+[(TargetBER−Sample1BER)/(Sample2BER−TargetBER)]
where “Sample1” is the read voltage453used for sample 1, “Sample1BER” is the BER determined for the read using read voltage453and “Sample2BER” is the BER determined for the read using read voltage451.

A similar method can be employed to determine the x-axis location corresponding to the target BER for Vt distribution450-2. Therefore, the level width455can be determined based on the difference between adjacent edges of Vt distributions450-1and450-2at the target BER443. As described herein, the level width such as level width455can be summed with other level widths corresponding to a group (e.g., page) of cells to constitute an overall level width. In various embodiments of the present disclosure, a determined (e.g., measured) level width can be compared to a target level wdith, and programming signal characteristics such as step size and/or step duration can be adjusted in order to achieve the target level width.

FIG. 5illustrates a graph505of at least a portion of a level width among example threshold voltage distributions of a particular page of memory cells in accordance with some embodiments of the present disclosure. The diagram illustrates a plurality of threshold voltage distributions546-1,546-1,546-3,546-4,546-5,546-6,546-7(hereinafter referred to collectively as546), each representing a threshold voltage distribution that corresponds to a voltage programming level. Each of the threshold voltage distributions546corresponds to a voltage, illustrated as volts542along the x-axis. For example, a first threshold voltage distribution546-1corresponds to a voltage range of 0.5V to approximately 1.3V.

Each of the voltages corresponds to a register value544. A rate540of the threshold voltage distributions546is illustrated along the y-axis. For example, as illustrated, each of the threshold voltage distributions covers a rate540ranging from 10° to 104. Each of the threshold voltage distributions include a level width that indicates a width spanning a voltage range. For example, a particular threshold voltage distribution546-7has a level width548that spans from approximately 4.75V to approximately 5.25V (or approximately 500 millivolts), as illustrated inFIG. 5.

FIG. 6is a graph607illustrating how adjusting one or more program step characteristics affects the level width in accordance with some embodiments of the present disclosure. The graph607illustrates a linear relationship between level widths656-1to656-7and program step size corresponding to a group of cells each programmed to one of eight Vt distributions (e.g., respective level widths across Vt distributions334-1to334-8shown inFIG. 3). The x-axis of graph607represents a program step size offset. As an example, an offset of “0” can correspond to a default program step size, with each increment or decrement to the offset representing a respective increase or decrease to the program step size (e.g., 10 mV, 100 mV, 1V, etc.). As shown in graph607, the level widths656-1to656-7generally increase linearly with increased program step size. Accordingly, the level width can be adjusted by a known amount by adjusting (incrementing/decrementing) the program step size by a particular offset amount, which can allow the level width to be used as a feedback metric in order to maintain a target level width, for example. As is illustrated, there are only 7 level widths illustrated as the level width associated with L0is not shown as it is the lowermost level (erase state).

FIG. 7is a graph703illustrating how adjusting one or more program step characteristics affects the level width in accordance with some embodiments of the present disclosure. The graph703illustrates a program step size update770and a corresponding change in level width772(in millivolts (mV) at each particular programming level774-1(level one programming, L1),774-2(L2),774-3(L3),774-4(L4),774-5(L5),774-6(L6), and774-7(L7, hereinafter referred to collectively as774). A program step size update770refers to adjusting a program step size in order to fine-tune the corresponding level widths of each programming level. As an example, A fourth (“4”) program step update770adjusts a level width772of a particular programming level774-7from approximately 375 mV (at program step update “3”) to approximately 400 mV (at program step update “4”), adjusting (e.g., increasing) the level width of programming level774-7about 25 mV.

As is illustrated inFIG. 7, the level widths772of the corresponding program levels774are adjusted upward in one program step size update (e.g., such as level widths subsequent to program step size update “3”) and then downward in the next program step size update (e.g., such as level widths subsequent to program step size update “4”). In this way, each program step size update770is adjusting a level width toward a target level width. In this example, programming level774-7is being adjusted toward a target level width772of approximately 390 mV as each increase and decrease is fine-tuning the level width towards this target level width. Likewise, programming level774-1is being adjusted towards a target level width of 460 mV, and so forth for each programming level and its corresponding level width illustrated inFIG. 7.

FIG. 8is a graph817of an example level width distribution corresponding to adjusting one or more program step characteristics for programming memory cells in accordance with some embodiments of the present disclosure. The graph817illustrates a total level width888at corresponding program step characteristic(s) updates882. A total level width888refers to a summation of level widths across a number of programming levels (such as programming levels1through7, illustrated inFIGS. 6-7, or programming levels of an entire page(s) of data). The total level width values (along the y-axis, in millivolts (mV)) 886 range from approximately 3000 mV to 3425 mV, as is illustrated. Each of the program step characteristic update(s)882can include adjusting a program step size, adjusting a program step duration, and/or adjusting a program step size and a program step duration concurrently, simultaneously, and/or in succession. In this way, each of the program step characteristic(s) updates882is adjusting the total level width888toward a target total level width, which in this example is approximately 3425 mV. In this way, one or more program step characteristic(s) can be adjusted to adjust a level width to a target level width. A prior adjustment of a level width toward a target level width can be used as a feedback loop in a subsequent adjustment of the level width until the level width is equal to or within a threshold proximity to the target level width.

FIG. 9is a flow diagram of an example method990corresponding to adjusting one or more program step characteristics for programming memory cells in accordance with some embodiments of the present disclosure. The method990can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method990is performed by the program step characteristic component115ofFIG. 1. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

At block991, the processing device (e.g., processing device112) determines a level width (LW) among a plurality of threshold voltage distributions of a particular page of at least a portion of a plurality of memory cells of a memory component based on one or more program step characteristics. In some embodiments, program step characteristics can include at least one of a program step size or a program step duration, as described herein. In relation to program step duration, in at least one example, program step duration can be measured by counting clock cycles of a known frequency between a time a program command was issued to a memory (e.g., a NAND) and when the memory programming operation is complete. In another example, the program step duration can be measured by using a number of program pulses used to complete the memory program operation and apply a known amount of time for each pulse.

In some embodiments, determining the LW as illustrated at block991can be performed on a periodic basis, in response to a number of drive fills, a number of program/erase counts, a number of input/output (I/O) operations, and/or a temperature change exceeding a threshold value.

At block993, the processing device compares the determined LW to a target LW. The target LW can be provided by an input to the memory system. The target LW can be provided based on an error threshold and/or other parameters or thresholds that can limit an LW value. At block995, the processing device, in response to the determined LW being different than the target LW, adjusts the one or more program step characteristics. The processing device can adjust the one or more program step characteristics to adjust the determined LW to an adjusted LW. For example, the memory system can increase or decrease one or more program step characteristics (e.g., one or more of the program step size and/or program step duration), which will correspondingly increase or decrease the LW by a particular amount based on determined relationships. Either of these parameters can be adjusted, or both can be adjusted, to achieve a particular LW that can be adjusted toward the target LW.

A relationship can exist between a program step size (e.g., program gate step size) and a level width (LW). A relationship can exist between a program step duration (e.g., a program pulse duration time) and the LW. These relationships can be combined and used to correspond (e.g., in a linear or nonlinear relationship) to the change in LW with a particular resolution (e.g., a higher resolution). In this example, the change in the LW (“DeltaLW”) can be equal to a change in program step size (“DeltaProgramStep”) plus a change in program step duration (“DeltaProgramTime”), as demonstrated by the formula:
DeltaLW=DeltaProgramStep+DeltaProgramTime
where a known delta of a program step duration can be equivalent to one increment of a program step size. As an example, if one increment of a program step size results in a 5% change in LW and “n” number of increments of delta program step duration also results in a 5% change in LW, then changing the LW time by 5% can be accomplished by either changing the program step size by one increment or changing the program step duration by n number of increments. To change the LW by only 2%, the program step size can remain the same and the program step duration delta could be adjusted by (2%/5%)*n. To change the LW by 13%, the program step size delta could be 2, resulting in 2*5%=10% plus a change in the program step duration of (3%/5%)*n.

In one example, the two relationships can be treated as linear relationships. In one example, the two relationships that affect LW and/or programming time can be represented by a formula which can include dependencies and non-linear effects. In another example, the relationships can be represented as tables which are indexed in a linear fashion but output differing amounts based on their index. In this example where the delta program step size and the delta program step duration are used as a function, the combination of the two parameters can be computed for a given change in LW. As an example:
[Program Step,ProgramTime]=funcProgramStep_ProgramTime(LWdelta)
In the example where the delta program step size and the delta program step duration is used as a table lookup, the combination of the two parameters can be pre-computed for a given change in LW, such as in Table 1 below.

TABLE 1TableIndexProgramStepProgramTimeLWdelta0−20−2.002−27−1.503−10−1.005−110−0.506000.0080100.509101.00111101.5012202.00142122.50
Note that the program step duration for the table index of 2 is 7 and the program step duration for the table index of 14 is 12, illustrating a non-linear relationship.

At block997, the processing device compares the adjusted LW to the target LW. At block999, in response to the adjusted LW being different than the target LW, the processing device further adjusts one or more program step characteristics to adjust the adjusted LW to the target LW.

The example computer system1000includes a processing device1063, a main memory1065(e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory1067(e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system1078, which communicate with each other via a bus1091.

Processing device1063represents one or more general-purpose processing devices such as a microprocessor, a central processing unit, or the like. More particularly, the processing device can be a complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processing device1063can also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. The processing device1063is configured to execute instructions1087for performing the adjustment operations using an adjustment component1073(including either or both of the program step size component and the program step duration component previously described) and steps discussed herein. The computer system1000can further include a network interface device1068to communicate over the network1080.

The data storage system1078can include a machine-readable storage medium1084(also known as a computer-readable medium) on which is stored one or more sets of instructions1087or software embodying any one or more of the methodologies or functions described herein. The instructions1087can also reside, completely or at least partially, within the main memory1065and/or within the processing device1063during execution thereof by the computer system1000, the main memory1065and the processing device1063also constituting machine-readable storage media. The machine-readable storage medium784, data storage system1078, and/or main memory1065can correspond to the memory sub-system104ofFIG. 1.

In one embodiment, the instructions1087include instructions to implement functionality corresponding to a program step characteristic component (e.g., program step characteristic component115ofFIG. 1). While the machine-readable storage medium1084is shown in an example embodiment to be a single medium, the term “machine-readable storage medium” should be taken to include a single medium or multiple media that store the one or more sets of instructions. The term “machine-readable storage medium” shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term “machine-readable storage medium” shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.