Semiconductor device with improved design freedom of external terminal

A semiconductor device comprises a base frame having a first surface and a second surface which opposes the first surface, and having an opening portion a semiconductor chip 30 which includes a first main surface on which a plurality of electrode pads is provided and a second main surface, and which is disposed within the opening portion; an insulating film formed on the first surface and first main surface; a plurality of wiring patterns which extend from the electrode pads, respectively to the upper side of the first surface of the base frame, respectively; a sealing portion formed on the wiring patterns and insulating film; and a plurality of external terminals provided on the wiring patterns in a region including the upper side of the base frame.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a semiconductor device, and more particularly to a semiconductor device in which the degree of design freedom of an external terminal is increased in accordance with further increases in the number of external terminals.

2. Description of Related Art

Demands have been made in recent years for further reductions in the size and thickness of packaged semiconductor devices. In response to such demands, a packaging form known as a Wafer Level Chip Size Package (to be referred to simply as WCSP hereinafter), in which the external size of the packaging is substantially equal to the external size of the semiconductor chip, has been proposed.

A WCSP comprises a semiconductor chip. The semiconductor chip comprises a circuit element having a predetermined function and a plurality of electrode pads electrically connected to each other on the circuit element. An insulating film is formed on the surface of the semiconductor chip such that the plurality of electrode pads is exposed.

A plurality of wiring patterns connected to the exposed electrode pads is formed on the surface of the insulating film.

Electrode posts are formed on these wiring patterns. A sealing portion is then formed so as to cover the insulating film and wiring patterns and such that the top surface of the electrode posts is exposed.

A plurality of external terminals provided as solder balls used in BGA packaging, for example, is provided on the top surface of the electrode posts.

This type of WCSP has a so-called fan-in configuration in which the multiple external terminals are provided in a lattice formation, for example, in a region corresponding to a circuit-forming surface of the semiconductor chip.

As regards the mounting of the semiconductor chip comprising the external terminals in a fan-in configuration onto a printed board, Japanese Patent Application Laid-Open Publication No. 2000-208556 discloses a semiconductor device having the aim of preventing the breakage of a connecting portion between the printed board and external electrodes and comprising a semiconductor chip having electrode pads, wiring which is formed in a predetermined position on the semiconductor chip and connected to the electrode pads, external electrodes which are formed in a predetermined position on the wiring and connected to the wiring, a printed board connected to the external electrodes, and a substrate which is formed on the semiconductor chip. A resin layer is provided on the substrate for aligning the thermal expansion of the substrate and printed board, and in particular the external electrodes are provided on the resin layer.

Further, a semiconductor device having a constitution in which the back surfaces of two WCSP-type semiconductor devices having a so-called fan-in configuration are joined to each other via an adhesive layer is known as a device for increasing compactness and integration while preventing warping of the semiconductor chip.

According to the constitution of the semiconductor device disclosed in Japanese Patent Application Laid-Open Publication No.2000-277682, for example, a sealing resin layer is formed on the outer surface of two joined semiconductor chips, or in other words an electronic circuit forming surface. Conductive posts are formed vertically through the sealing resin layer. These conductive posts are electrically connected to an electronic circuit via a rewiring circuit. Solder bumps are formed on the top surface of the conductive posts:

As semiconductor devices become increasingly sophisticated, the number of external terminals formed on a single packaged semiconductor device is gradually increasing. Conventionally, such demands for increases in the number of external terminals have been met by providing constitutions in which the spacing between adjacent external terminals is narrowed. As shall be described below, however, design freedom is severely restricted by the disposal pitch and disposal positions of external terminals.

In the conventional WCSP described above, the minimum gap between adjacent external terminals is set at a concrete level of approximately 0.5 mm. In the case of a 7 mm×7 mm WCSP, the number of external terminals provided is approximately 160.

In accordance with demands for further increases in the number of external terminals on a packaged semiconductor device, it is desirable that approximately 300 external terminals be provided on a 7 mm×7 mm WCSP.

It is not technically impossible in the aforementioned WCSP to form an even larger number of external terminals on the surface of the WCSP by further narrowing the gap between adjacent external terminals.

However, it is extremely difficult to form 300 external terminals on the surface area of a 7 mm×7 mm WCSP. Moreover, if the intervals between the external terminals are narrowed, an extremely high degree of technology is required to mount the WCSP onto a mounting substrate.

For example, the intervals between the plurality of external terminals may have to be formed in alignment with the mounting pitch of the mounting substrate within a range of approximately 0.3 mm to 0.7 mm.

In a conventional packaging constitution in such a case, a semiconductor chip is connected to the substrate by means of a so-called flip chip connection and the semiconductor chip is connected to the external electrodes via the substrate. Alternatively, the substrate and semiconductor chip are connected by wire bonding and the semiconductor chip is connected to the external electrode via the substrate. Since both of these connection methods utilize a substrate, and since additional sealing material is required in accordance with the height of the wire loop, the package becomes thick. Moreover, the package becomes expensive due to the cost of the substrate. The package becomes particularly expensive when a flip chip connection is used since an expensive buildup substrate is required.

When connection is performed by means of wire bonding, the inductance of the wire part increases.

An object of this invention is therefore to provide a semiconductor device having a constitution in which design freedom in the disposal pitch and disposal positions of external terminals is increased and the package itself can be made compact.

SUMMARY OF THE INVENTION

In order to achieve this object, a semiconductor device of this invention has a constitution such as the following. That is, the semiconductor device of this invention comprises a base frame having a first surface, and a second surface which opposes the first surface, and having an opening portion formed through the base frame.

The semiconductor device of this invention also comprises a semiconductor chip which has a first main surface on which a plurality of electrode pads are provided and a second main surface opposing the first main surface. The semiconductor chip is disposed within the opening portion such that the level (i.e. height, same hereinafter) of the first main surface is substantially equal to the level of the first surface.

Further, an insulating film is formed on the first surface and first main surface such that a part of each of the plurality of electrode pads is exposed.

A plurality of wiring patterns are electrically connected to the plurality of electrode pads, respectively and extended from the electrode pads to the upper side of the first surface of the base frame, respectively.

A sealing portion is formed on the wiring patterns and insulating film such that a part of the wiring patterns is exposed.

The semiconductor device of this invention further comprises a plurality of external terminals provided on the wiring patterns in a region including the upper side of the base frame.

According to the constitution of the semiconductor device of this invention, external electrodes may also be provided in a region including the upper side of (directly above) the base frame which is provided so as to surround the semiconductor chip, and thus a semiconductor device having increased design freedom in the disposal pitch, disposal positions, and so on of the external electrodes can be provided.

Further, the semiconductor device of this invention may be constructed without the use of an interposer such as a substrate by applying a so-called WCSP manufacturing process, as a result of which increases in operating speed, functional sophistication, number of functions, and compactness can be achieved in comparison with a wire bonding connection.

Moreover, an identical electrical characteristic can be obtained at a lower cost than a device in which a flip chip connection is used.

The manufacturing process for implementing this invention preferably comprises the following manufacturing steps.

A manufacturing method of the semiconductor device comprises:

(1) providing abase frame having a plurality of opening portions on a lower base such that a semiconductor chip disposal region on the lower base is exposed;

(2) preparing a semiconductor chip having a first main surface on which a plurality of electrode pads are provided and a second main surface which opposes the first main surface;

(3) disposing the semiconductor chip in the opening portion such that the level of the first main surface is substantially equal to the level of a first surface of the base frame and such that the second main surface faces the semiconductor chip disposal region;

(4) forming an insulating film on the first surface of the base frame and the first main surface such that a part of each of the electrode pads is exposed;

(5) forming a plurality of wiring patterns on the insulating film so as to be electrically connected to the electrode pads, respectively and extended from the electrode pads to the upper side of the first surface of the base frame, respectively;

(6) forming a sealing portion on the wiring patterns and insulating film such that a part of each of the wiring patterns positioned on the first surface is exposed;

(7) forming a plurality of external terminals on the wiring patterns in a region including the upper side of the base frame and connecting the external terminals to the wiring patterns; and

(8) forming individual semiconductor devices comprising the semiconductor chip by cutting the base frame between the plurality of semiconductor chips.

The manufacturing method of the semiconductor device also comprises:

(1) providing abase frame having a plurality of opening portions on a lower base such that a semiconductor chip disposal region on the lower base is exposed;

(2) preparing a semiconductor chip having a first main surface on which a plurality of electrode pads is provided and a second main surface which opposes the first main surface;

(3) disposing the semiconductor chip in the opening portion such that the level of the first main surface is substantially equal to the level of a first surface of the base frame and such that the second main surface faces the semiconductor chip disposal region;

(4) forming an insulating film on the first surface of the base frame and the first main surface such that a part of the electrode pads is exposed;

(5) forming a plurality of wiring patterns on the insulating film so as to be electrically connected to the electrode pads, respectively and extended from the electrode pads to the upper side of the first surface of the base frame, respectively;

(6) forming a plurality of electrode posts on a part of each of the wiring patterns positioned on the upper side of the base frame;

(7) forming a sealing portion through which the top surface of the electrode posts is exposed on the wiring patterns and insulating film;

(8) forming external terminals on the top surface of the exposed electrode posts; and

(9) forming individual semiconductor devices comprising the semiconductor chip by cutting the base frame between the plurality of semiconductor chips.

Here, a further step of removing the lower base from the second surface of the extension portion and the second main surface may be added following the step of forming the external terminals.

The manufacturing method of the semiconductor device further comprises:

(1) preparing a jig comprising a plurality of convex portions and concave portions positioned between these convex portions;

(2) preparing a base frame in which a plurality of opening portions is formed and which comprises a first surface, a second surface opposing the first surface, and the plurality of opening portions which pass through the first surface to the second surface;

(3) preparing a semiconductor chip having a first main surface on which a plurality of electrode pads is provided and a second main surface which opposes the first main surface;

(4) placing the base frame on the jig such that the second surface faces the concave portion and the convex portion is positioned within the opening portion;

(5) disposing the semiconductor chip on the convex portion within the opening portion such that the level of the first main surface is substantially equal to the level of the first surface of the base frame and such that the second main surface faces the surface of the convex portion;

(6) forming an insulating film on the first surface and first main surface such that a part of each of the electrode pads is exposed;

(7) forming a plurality of wiring patterns on the insulating film so as to be electrically connected to the electrode pads, respectively and extended from the electrode pads to the upper side of the first surface of the base frame, respectively;

(8) forming a sealing portion on the wiring patterns and insulating film such that a part of the wiring patterns positioned on the first surface is exposed;

(9) forming a plurality of external terminals on the wiring patterns in a region including the upper side of the base frame and connecting the external terminals to the wiring patterns; and

(10) forming individual semiconductor devices comprising the semiconductor chip by cutting the base frame between the plurality of semiconductor chips.

The manufacturing method of the semiconductor device further comprises:

(1) preparing a jig comprising a plurality of convex portions and concave portions positioned between these convex portions;

(2) preparing a base frame in which a plurality of opening portions are formed and which comprises a first surface, a second surface opposing the first surface, and the plurality of opening portions which pass through the first surface to the second surface;

(3) preparing a semiconductor chip having a first main surface on which a plurality of electrode pads are provided and a second main surface which opposes the first main surface;

(4) placing the base frame on the jig such that the second surface faces the surface of the concave portion and the convex portion is positioned within the opening portion;

(5) disposing the semiconductor chip on the convex portion within the opening portion such that the level of the first main surface is substantially equal to the level of the first surface of the base frame and such that the second main surface faces the surface of the convex portion;

(6) forming an insulating film on the first surface and first main surface such that a part of each of the electrode pads is exposed;

(7) forming a plurality of wiring patterns on the insulating film so as to be electrically connected to the electrode pads, respectively and extended from the electrode pads to the upper side of the first surface of the base frame, respectively;

(8) forming a plurality of electrode posts on a part of each of the wiring patterns positioned on the upper side of the base frame;

(9) forming a sealing portion through which the top surface of the electrode posts is exposed on the wiring patterns and insulating film;

(10) forming external terminals on the top surface of the exposed electrode posts; and

(11) forming individual semiconductor devices comprising the semiconductor chip by cutting the base frame between the plurality of semiconductor chips.

The manufacturing method of the semiconductor device further comprises:

(1) preparing a jig having a plurality of convex portions and concave portions positioned between these convex portions;

(2) preparing a base frame having a first surface, a second surface which opposes the first surface, a plurality of opening portions which pass through the first surface to the second surface, a plurality of through holes which pass through the first surface to the second surface, and an inter-layer wiring which is formed within the through hole;

(3) preparing a first semiconductor chip having a first main surface on which a plurality of electrode pads are provided and a second main surface which opposes the first main surface, and a second semiconductor chip having a third main surface on which a plurality of electrode pads are provided and a fourth main surface which opposes the third main surface;

(4) placing the base frame on the jig such that the second surface faces the surface of the concave portion and the convex portion is positioned within the opening portion;

(5) disposing the first semiconductor chip on the convex portion within the opening portion such that the level of the first main surface is substantially equal to the level of the first surface of the base frame and the second main surface faces the surface of the convex portion;

(6) forming a first insulating film on the first surface and first main surface such that a part of each of the first electrode pads and one end of the inter-layer wiring are exposed;

(7) forming a plurality of first wiring patterns on the first insulating film so as to be connected to the first electrode pads, respectively and one end of the inter-layer wiring and extended from the first electrode pads to the upper side of the first surface of the base frame, respectively;

(8) forming a first sealing portion on the first wiring patterns and first insulating film such that a part of each of the first wiring patterns positioned on the first surface is exposed;

(9) removing the base frame having the first semiconductor chip from the jig and turning the base frame over;

(10) disposing the second semiconductor chip within the opening portion such that the level of the third main surface is substantially equal to the level of the second surface and such that the fourth main surface faces the surface of the convex portion;

(11) forming a second insulating film on the second surface and third main surface such that a part of each of the second electrode pads and the other end of the inter-layer wiring are exposed;

(12) forming a plurality of second wiring patterns on the second insulating film so as to be connected to the second electrode pads, respectively and the other end of the inter-layer wiring and extended from the second electrode pads to the upper side of the second surface of the base frame;

(13) forming a second sealing portion on the second wiring patterns and second insulating film such that a part of each of the second wiring patterns positioned on the second surface is exposed;

(14) forming first and second external terminals on the top surfaces of the exposed first and second wiring patterns respectively; and

(15) forming individual semiconductor devices comprising a stacked body of the first and second semiconductor chips by cutting the base frame between the plurality of opening portions.

The manufacturing method of the semiconductor device further comprises:

(1) preparing a jig having a plurality of convex portions and concave portions positioned between these convex portions;

(2) preparing a base frame having a first surface, a second surface which opposes the first surface, a plurality of opening portions which pass through the first surface to the second surface, a plurality of through holes which pass through the first surface to the second surface, and an inter-layer wiring which is formed within the through hole;

(3) preparing a first semiconductor chip having a first main surface on which a plurality of electrode pads are provided and a second main surface which opposes the first main surface, and a second semiconductor chip having a third main surface on which a plurality of electrode pads are provided and a fourth main surface which opposes the third main surface;

(4) placing the base frame on the jig such that the second surface faces the surface of the concave portion and the convex portion is positioned within the opening portion;

(5) disposing the first semiconductor chip on the convex portion within the opening portion such that the level of the first main surface is substantially equal to the level of the first surface of the base frame and the second main surface faces the surface of the convex portion;

(6) forming a first insulating film on the first surface and first main surface such that a part of each of the first electrode pads and one end of the inter-layer wiring are exposed;

(7) forming a plurality of first wiring patterns on the first insulating film so as to be connected to the first electrode pads and one end of the inter-layer wiring, respectively and extended from the first electrode pads to the upper side of the first surface of the base frame, respectively;

(8) forming a plurality of first electrode posts on a part of each of the wiring patterns positioned on the upper side of the base frame;

(9) forming a first sealing portion through which the top surface of the first electrode posts is exposed on the first wiring patterns and first insulating film;

(10) removing the base frame comprising the first semiconductor chip from the jig and turning the base frame over;

(11) disposing the second semiconductor chip within the opening portion such that the level of the third main surface is substantially equal to the level of the second surface and such that the fourth main surface faces the surface of the convex portion;

(12) forming a second insulating film on the second surface and third main surface such that a part of the second electrode pads and the other end of the inter-layer wire connection are exposed;

(13) forming a plurality of second wiring patterns on the second insulating film so as to be connected to the second electrode pads, respectively and the other end of the inter-layer wiring and extended from the second electrode pads to the upper side of the second surface of the base frame, respectively;

(14) forming a plurality of second electrode posts on a part of each of the second wiring patterns positioned on the upper side of the base frame;

(15) forming a second sealing portion through which the top surface of the second electrode posts is exposed on the second wiring patterns and second insulating film;

(16) forming first and second external terminals on the top surfaces of the exposed first and second electrode posts respectively; and

(17) forming individual semiconductor devices having a stacked body of the first and second semiconductor chips by cutting the base frame between the plurality of opening portions.

In the manufacturing process described above, the base frame is preferably suction-held on the surface of the concave portion by a first suction and exhaust system provided on the concave portion, and the first semiconductor chip is preferably suction-held on the surface of the convex portion by a second suction and exhaust system provided on the convex portion.

According to this manufacturing method for the semiconductor device of this invention, a semiconductor device with increased functional sophistication, number of functions, and compactness can be provided by means of a comparatively easy process. In particular, design freedom in the disposal pitch, disposal positions, and so on of the external electrodes can be greatly increased.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of this invention will be described below with reference to the drawings. Note that in the drawings, the form, magnitude, and positional relationships of each constitutional component are merely illustrated schematically in order to facilitate understanding of this invention and no particular limitations are placed on this invention thereby. Further, although specific materials, conditions, numerical value conditions, and so on are used in the following description, these are merely one preferred example thereof and therefore do not place any limitations on this invention. It is to be understood that similar constitutional components in the drawings used in the following description are allocated and illustrated with identical reference symbols, and that duplicate description thereof has occasionally been omitted.

First Embodiment

A semiconductor device according to a first embodiment of this invention will be described with reference toFIGS. 1 and 2.FIG. 1(A)is a plan view seen from above showing in outline the constitution of the semiconductor device of the first embodiment, andFIG. 1(B)is a plan view showing an expanded outline of the main parts of the region ofFIG. 1(A)which is surrounded by a solid line11in order to illustrate the connection relationship between a wiring pattern and electrode posts.FIGS. 2(A) and 2(B)are schematic sectional views showing cross sections severed along a broken line I—I inFIG. 1(A). Note thatFIG. 2(A)shows a constitutional example in which the semiconductor device10of this invention is provided with a lower base12on its bottom surface.FIG. 2(B)shows a constitutional example in which the lower base12is not provided.

The semiconductor device10of the first embodiment of this invention comprises on the lower base12a base frame20having an opening portion22which is a through hole (seeFIG. 2(A)). This base frame20is, for example, a square frame-shaped portion which preferably comprises a first surface20aserving as the surface thereof and a second surface20bserving as the rear surface thereof. The square opening portion22which passes through the first surface20ato the second surface20bis formed in the center thereof.

The base frame20may be formed from a plate-form body or a sheet-form body made of an organic material such as a glass epoxy or a polyimide. The base frame20may also be formed from a substrate appropriately selected from a substrate group comprising a ceramic substrate, a metallic substrate, and an Si substrate. A Si substrate is preferably used as the base frame20. In so doing, the heat resistant stress characteristic of subsequently formed wiring patterns can be improved.

The above-mentioned opening portion22may be appropriately formed in accordance with the material constituting the base frame20using a well-known method such as laser processing, a mechanical process such as punching, or metalworking. The magnitude of the opening portion22is set to be substantially identical to or slightly larger than the magnitude of a semiconductor chip30so that the semiconductor chip30can be provided inside the opening portion22. A plurality of opening portions22is disposed in a lattice formation in the base frame20, preferably at equal intervals from each other. These intervals are determined in consideration of the desired number of external terminals, the spacing between the external terminals, the surface area of an extension portion21, and so on.

The semiconductor chip30is disposed inside the opening portion22by being fitted therein or the like. Thus side surfaces37of the semiconductor chip30are surrounded by the base frame20and the surface region of the base frame20is formed adjacent to and apart from the surface region of the semiconductor chip30. The semiconductor chip30comprises a first main surface36, a second main surface38which opposes the first main surface36, and one or two or more side surfaces37which exist between the first main surface36and second main surface38. The level of the first main surface36is set to be substantially equal to the level of the first surface20a. The first main surface36comprises electrode pads34. The electrode pads34are formed in a plurality around the peripheral edge of the first main surface36.

The semiconductor chip30is provided inside the opening portion22such that the first main surface36becomes the upper surface, or in other words such that the second main surface38faces a semiconductor chip disposal region14of the lower base12.

An insulating film40is formed on the first surface20aof the base frame20and the first main surface36such that a part of each of the plurality of electrode pads34is exposed.

A plurality of wiring patterns42are formed on the surface of the insulating film40and electrically connected to the exposed electrode pads34.

A sealing portion44is provided on the respective surface regions of the semiconductor chip30and base frame20so as to cover the wiring patterns42and insulating film40. The insulating film40and sealing portion44may also be referred to collectively as an insulation layer48. Electrode posts46are provided on each wiring pattern42so as to pass through the sealing portion44and reach the surface of the sealing portion44. Some of the electrode posts46are provided on the upper side of (directly above) the semiconductor chip30, and the remaining electrode posts46are provided on the upper side of (directly above) the base frame20. These electrode posts46are normally arranged at constant intervals. Further, the top surface of each electrode post46is exposed on the surface of the sealing portion44. The electrode posts46are also known as post electrodes, and external terminals47are provided on the exposed top surfaces thereof. Solder balls47aare normally used as the external terminals47. The external terminals47are arranged at a first pitch wider than a second pitch at which the electrode pads34is arranged.

Here, usingFIG. 1(B), the connection relationships between the electrode pads34and wiring patterns42will be described. A partial region (the region surrounded by the solid line)11ofFIG. 1(A)has been expanded and illustrated in order to facilitate understanding of these connection relationships. The wiring patterns42are constituted such that each of the electrode posts (shown as46inFIG. 2) connected to the lower portion of the external terminals47is regularly and electrically connected to a corresponding electrode pad34. A long wire42a, a medium wire42b, and a short wire42c, for example, are provided as the wires which constitute each wiring pattern42. These wires42a,42b, and42care respectively connected in that order to the corresponding electrode pad34in a one-on-one connection relationship of one wire to one electrode pad.

The wiring patterns42include wiring patterns that provided on the upper side of (directly above) the semiconductor chip30and on the upper side of (directly above) the base frame20, or in other words so as to straddle the boundary (22) of the extension portion21region.

Hence the portions42X of the wiring patterns42having a certain length on or in the vicinity of this boundary is preferably comprised of thicker and/or wider wire. In other word, The portions42X of the wiring patterns42on a boundary and vicinity thereof between a region on the upper side of said semiconductor chip30and the base flame20are formed wider or more thickly than other portions of said wiring patterns42. As an example, a rectangular thicker and wider wiring portion42X is illustrated in detailedFIGS. 1(C) and 1(D). The other features illustrated inFIGS. 1(C) and 1(D)are labeled by the same reference numerals as in the other figures.

By forming the portions42X of the patterns42at which stress is considered more likely, due to such phenomena as thermal stress and particularly an edge effect, to be thicker and/or wider in this manner, operational reliability in the semiconductor device10is improved.

The region on the upper side of (directly above) the base frame20is referred to as the extension portion21due to the fact that the external terminal forming region extends beyond the surface region of the semiconductor chip30. In this constitutional example, electrode posts46are also formed on the extension portion21.

The sealing portion44is formed so as to cover the wiring patterns42and electrode posts46. The sealing portion44is formed such that a part of the electrode posts46is exposed.

The external terminals47are formed via the electrode posts46. A constitution is also possible in which the external terminals are directly connected to the wiring patterns42without passing through the electrode posts by exposing a part of the wiring patterns42through the sealing portion44.

In this constitutional example, the external terminals47are formed from solder balls47a, for example. These solder balls47aare provided in contact with the top surface of the electrode posts46and connected to the wiring patterns42via the electrode posts46. The arrangement and spacing of adjacent electrode posts46may be set as desired in consideration of mounting onto a printed board or the like, for example.

As described above, the electrode posts46are provided not only within a surface area range corresponding to the upper side of the semiconductor chip30, but also on the upper side of the base frame20, or in other words on the extension portion21. As a result, design freedom in the disposal positions and disposal pitch of the electrode posts46is increased. In other words, restrictions on the disposal pitch of the electrode posts46, that is the external terminals47, are eased such that mounting is facilitated, and thus the electrode posts46can be formed at wider intervals in accordance with the constitutional requirements on the mounting substrate side, for example. More specifically, external electrodes can be formed at an appropriate disposal pitch and in a desired number by appropriately adjusting the surface area of the base frame20.

According to the constitution of the semiconductor device10of this invention, the external terminals47are provided in the region of the extension portion21apart from the region directly above the semiconductor chip30, and thus the semiconductor device10may be constructed with a so-called fan-out configuration or a fan-in/fan-out configuration in which the external terminals47are also formed in the region on the first main surface36. Hence design freedom in the disposal pitch, disposal positions, and so on of the external terminals47can be increased.

Further, the semiconductor device10of this invention is constituted using a so-called WCSP manufacturing process such that the semiconductor chip30and external electrodes47are directly connected without the use of an interposer such as a substrate, and thus in addition to the aforementioned effect, the operational speed, functional sophistication, number of functions, and compactness of the semiconductor device10can be increased in comparison with a device in which a wire bonding connection, for example, is used. The semiconductor device10can also be obtained with an identical electrical characteristic to and at a lower cost than a device in which a flip chip connection, for example, is used.

Modified Example of the First Embodiment

Next, a modified example of the semiconductor device of the first embodiment will be described with reference toFIG. 3. Note that the plan view seen from above of this example is substantially identical toFIG. 1(A), and hence diagrammatic representation and detailed description thereof have been omitted.

FIGS. 3(A) and 3(B)are schematic sectional views of a semiconductor device10′ of the modified example and correspond toFIGS. 2(A) and 2(B)respectively.FIG. 3(A)shows a constitutional example in which the semiconductor device10′ is provided with the lower base12on its bottom surface.FIG. 3(B)shows a constitutional example in which the lower base12is not provided.

The semiconductor10′ of this modified example differs in the form of peripheral inside walls24which define the opening portion22of the base frame20. Accordingly, other similar constitutional components to the first embodiment are allocated and illustrated with identical reference symbols and duplicate description thereof has been omitted.

In the semiconductor device10′ of this modified example, the inside walls24which define the opening portion22of the base frame20, of which there are four in this example, are each provided in an inclined form such that each of the four inside walls24decreases in thickness from the base frame20side toward the opening portion22side, or in other words toward the semiconductor chip30. That is, the inside walls24have a so-called wedge-form.

By constituting the inside walls24in such a manner, an identical working effect to that of the semiconductor device described in the first embodiment can be obtained, and moreover, as will be understood from the following description, a particularly favorable effect can be obtained in the manufacturing process of this semiconductor device10′.

A stacked semiconductor device can be formed by stacking a plurality of the semiconductor devices10and/or10′ of the first embodiment and/or modified example described above. In this case, a terminal for-connecting stacked individual semiconductor devices to each other may be formed by forming a through hole in the base frame using a well-known method, for example, such that an inter-layer wire connection is formed.

First Manufacturing Method of the First Embodiment

Next, a first manufacturing method for the semiconductor device of the first embodiment will be described with reference toFIGS. 4(A) to 10(B).

As a rule, each Fig. (A) is a partial schematic plan view for illustrating the constitution of the semiconductor device of this invention, and each Fig. (B) is a schematic sectional view showing a cross section severed along a broken line I—I of the corresponding Fig. (A). Note thatFIGS. 6(B) and 7are exceptions to the rule, showing an expanded view of the part surrounded by a solid line11inFIG. 6(A)and a sectional view severed along the I—I line inFIG. 6(A)respectively.

First, semiconductor chip disposal regions14on which a plurality of semiconductor chips30is to be placed are set on a prepared lower base12. Naturally, the profile of the semiconductor chip disposal region14substantially matches the profile of the opening portion22provided in the base frame20. The intervals between adjacent semiconductor chip disposal regions14, and thus the intervals between adjacent opening portions22, are set to be equal. This interval is preferably set to a sufficient value in consideration of the surface area of the lower base margin required when the semiconductor devices are divided into individual units, or in other words, when singularization processing is implemented, in a subsequent process, of the surface area of the surface region of the extension portion which is formed in accordance with the desired number of external terminals, and so on.

First, as shown inFIGS. 4(A) and 4(B), the set semiconductor chip disposal regions14and opening portions22are positionally aligned, and the base frame20is placed on the lower base12.

Here, the lower base12may be formed from a plate-form or sheet-form body made of an organic material such as a glass epoxy or a polyimide, for example. Alternatively, the lower base12may be formed from a substrate appropriately selected from a ceramic substrate, a metallic substrate, a Si substrate, or similar. The surface of the lower base12preferably comprises adhesion means (not shown in the drawings) in at least the region on which the base frame20is placed which are easily peeled away by heating, ultraviolet radiation, or another type of processing, for example.

Particularly if the semiconductor device of this invention is to be formed without a lower base, a lower base which can be removed in a subsequent step using a method such as peeling away from the base frame should be selected. Specifically, a thermal release sheet “Revalpha” (product name), manufactured by Nitto Denko Corporation, heat-resistant “Icros Tape” (product name) or the “SP Series” (product name), manufactured by Mitsui Chemicals Inc., or similar may be used as a peelable lower base. A glass substrate or the like on whose surface an ultraviolet curable adhesive, for example, is painted to serve as adhesion means may also be favorably applied as a lower base.

The base frame20which is placed on the lower base12is adhered to and held by the adhesion means provided on the surface of the lower base12.

Thus the semiconductor chip disposal regions14which are set in advance on the lower base12are exposed from the opening portions22formed in the base frame20.

Next, as shown inFIGS. 5(A) and 5(B), semiconductor chips30are disposed on the semiconductor chip disposal regions14exposed within the opening portions22.

Adhesion means are preferably provided on the semiconductor chip disposal regions14. The semiconductor chips30may then be adhered to and held on the semiconductor chip disposal regions14by these adhesion means.

Here, the height of the first surface20aof the base frame20, that is a thickness d2, and the height of the surface of the semiconductor chip30provided inside the opening portion22, that is a thickness d1, preferably match. However, a slight height difference may exist between the two surfaces as long as this difference is within the range of a difference of elevation at which the wiring patterns may be formed on the upper surfaces of the first surface20aof the base frame20and the first main surface36of the semiconductor chip30without the danger of the wires becoming disconnected or the like.

When the cross sections of the inside walls24of the opening portions22in the base frame20have an inclined so-called wedge-form as described above usingFIG. 3, the incline of the surface of the inside walls24allows the semiconductor chip30to be disposed in a desired position inside the opening portion22more easily and smoothly by sliding the surface thereof along the incline of the inside walls24.

The semiconductor chip30is provided with a second main surface38which faces the first main surface36. A circuit element (not shown) having a predetermined function is formed on the semiconductor chip30. Electrode pads34which are electrically connected to the circuit element are provided on the first main surface36. The electrode pads34are provided in an array around the peripheral edge of the first main surface36.

The semiconductor chip30described above is, for example, fitted into the opening portion22such that the second main surface38thereof faces the lower base12in the semiconductor chip disposal region14. If adhesion means are provided on the surface of the semiconductor chip disposal region14at this time, then the second main surface38is adhered thereto and held thereby.

Next, the insulating film40is formed on the first surface20aof the base frame20and the first main surface36. The insulating film40is formed such that at least a part of each of the electrode pads34on the semiconductor chip30is exposed. Here, the insulating film40is formed so as to cover the electrode pads34, whereupon the top surface of the electrode pads34may be exposed using a photolithography method or the like.

As noted above, a height difference may exist between the surface of the base frame20and the first main surface36of the semiconductor chip30, or the surface of the inside walls24of the base frame20may be inclined as described above. In such cases, the height difference may be reduced to a degree which allows the formation of wiring patterns in a subsequent step using the insulating material of the insulating film40, or the surface of the insulating film40may be formed substantially flat.

Formation of the insulating film40may be performed using an appropriate insulating material and by means of a method which is suited to the material of the base frame20, for example a well-known method such as spin coating, printing, or direct application.

If, at this time, a gap appears between the base frame20and semiconductor chip30, insulating material is inserted into the gap to fix together and integrate the base frame20and semiconductor chip30.

Then, as shown inFIGS. 6 and 7, a plurality of wiring patterns42are formed on the surface of the insulating film40. Formation of these wiring patterns42is performed following setting such that each wiring pattern42is electrically connected to a corresponding electrode pad34on the surface of the insulating film40and in consideration of the disposal of external terminals to be formed at a later stage.

More specifically, the wire width, wire spacing, optimum angles, and so on are determined in accordance with applicable wiring process rules such that connections can be made at the shortest possible distances. As shown in the drawings, for example, a plurality of wiring pattern groups, each comprising a long wire42a, a medium wire42b, and a short wire42c, is formed in respect of the plurality of electrode pads34formed around the peripheral edge of the semiconductor chip30at the shortest possible distances, and one end portion of each wire is connected to the corresponding electrode pad34. An electrode post mounting pad is formed on the other end portion so that an external terminal47(solder ball47a) can be connected thereto via an electrode post.

Note that in the constitutional example shown inFIGS. 5(A) and 6(A), the number of illustrated disposed electrode pads34is smaller than the actual number.

The wiring patterns42may be formed by performing a wiring pattern formation process such as sputtering and photolithography in a well-known WCSP manufacturing process on a region corresponding to the upper side of (directly above) the base frame20on the surface region of the insulating film40, or in other words a desired region on the insulating film40which includes the extension portion21.

As for the material for forming the wiring pattern42, a favorable material may be selected at will, but the wiring pattern42is preferably formed from a material such as aluminum, copper, or a metal alloy.

If it is assumed that in the wiring pattern42forming step, stress becomes concentrated due to a height difference as described above, the region of the wiring patterns42which substantially includes the part of the wiring pattern42at which stress is concentrated may be made slightly thicker and/or wider. For example, the portions of the wiring patterns on or in the vicinity of the boundary between the upper side region of the semiconductor chip and the extension portion region may be formed thicker and/or wider.

Next, as shown inFIGS. 8(A) and 8(B), electrode posts are formed on the surface of each wiring pattern42so as to be electrically connected thereto. The electrode posts46are provided on the surface region of the extension portion21on the upper side of (directly above) the base frame20and on the region near the extension portion21on the upper side of (directly above) the semiconductor chip30. The electrode posts46are formed in a lattice formation and arranged at predetermined intervals. As described above, these intervals may be set in consideration of mounting, or in other words as either constant or irregular intervals.

After an appropriate material has been selected, the electrode posts46may be formed by means of an electrode post46forming process such as plating and photolithography in a well-known WCSP manufacturing process.

A sealing portion44is also formed so as to cover the surface of the insulating film40on which the wiring patterns42and electrode posts46are formed. When external terminals are formed without electrode posts46, the sealing portion44is preferably formed such that the parts of each of the wiring pattern42at which external terminals are to be formed are exposed.

This sealing process may be implemented by means of a well-known method using a well-known sealing material.

Next, as shown inFIGS. 9(A) and 9(B), the surface side of the sealing portion44is trimmed such that the top surface (also referred to as the upper surface) of the electrode posts46is exposed.

This process is performed using a well-known grinding or polishing process.

A method such as film formation may also be applied to the formation of the sealing portion44. In this case, substantially no load is placed on the electrode posts46. Also in this case, the sealing portion44can be formed such that the top surface of the electrode posts46is directly exposed on the surface of the sealing portion44without the need for a grinding process on the sealing portion44as described above. Any suitable processing required from a design point of view may be performed on the exposed top surface of the electrode posts46. If copper is used as the material for the electrode posts46, for example, a thin Ni (nickel) film may be formed on the top surface of the electrode posts46as a barrier metal layer.

Next, solder balls47a, for example, are formed as the external terminals47on the upper surface of the electrode posts46which is exposed from the surface of the sealing portion44.

Next, as shown inFIGS. 10(A) and 10(B), the plurality of semiconductor chips are severed along a cutting line shown in the drawings by a dot/dash line a to provide individual constitutional bodies comprising a single semiconductor device having a predetermined function.

This singularization process is preferably performed by cutting using a blade which rotates at high speed. The lower base12which is held by adhesion to the second surface20bof the base frame20and second main surface38of the semiconductor chip30of each divided constitutional body is then removed by being peeled away therefrom.

When the lower base12is constituted by peelable adhesion means such as those described above or peelable adhesion means are applied to the lower base12in the manufacturing process, the lower base12should be peeled away using processing corresponding to the adhesion means such as heating, processing using heated water, or ultraviolet radiation. More specifically, when a thermal release sheet is applied as the lower base12, for example, the lower base12may be peeled away by heating the adhesion means to a predetermined temperature. If ultraviolet curable adhesive is applied as the adhesion means, for example, the lower base12maybe removed by curing the adhesive using ultraviolet radiation.

This peeling process may be executed either following the electrode post46forming step, following the sealing step, or following the singularization step. Considering the mechanical strength and so on of the extension portion21, however, peeling is preferably performed at the end of the sealing step.

In the constitutional example described above, a semiconductor device is manufactured by arranging the semiconductor chips30in a 2 row×X column (X being a positive number not less than two) lattice formation. This invention is not limited to such an array, however, and a large-number of semiconductor devices may be manufactured simultaneously by providing semiconductor chips in any appropriate array which accords with design specifications.

Since a so-called WCSP manufacturing process can be applied to the first manufacturing method, the semiconductor device of this embodiment can be manufactured by a simple process and without the need for any special semiconductor device manufacturing processes.

Second Manufacturing Method of the First Embodiment

Next, a second manufacturing method for the semiconductor device of the first embodiment will be described with reference toFIGS. 11(A) through 13(B). Note that in the following manufacturing method, the applied materials, process implementation conditions, and so on are similar to those in the first method and hence detailed description thereof has been omitted.

The second manufacturing method differs in that a jig is used to implement each process in place of the lower base12described in the first manufacturing method.

First the constitution of a preferred jig to be applied to the second manufacturing method will be described with reference toFIG. 11.

FIG. 11(A)is a partial schematic plan view illustrating the constitution of a preferred jig to be applied to a manufacturing method of the semiconductor device of this invention, andFIG. 11(B)is a view showing in outline a cross section severed along the I—I broken line inFIG. 11(A).

A jig50is a tool used in the manufacturing process for supporting or aligning constitutional elements. In this constitutional example, the jig50is a pedestal comprising a plurality of convex portions52and concave portions54positioned in the gaps between the convex portions52. In this example, the form of each convex portion52is a rectangular parallelepiped. The profile and surface area of the surface (also referred to as “top surface” hereinafter) of the convex portion52are set to be substantially identical to the surface area of the second main surface38of the semiconductor chip30. The height of the convex portion52, or in other words a height h of a side wall portion52a, is preferably set such that when the base frame20is fixed on the jig50and the semiconductor chip30is placed on the surface of the convex portion52, the first main surface36of the semiconductor chip30and the first surface20aof the base frame20form a flat plane with no height difference. As noted above, even if a slight height difference exists between the semiconductor chip30and base frame20, this is not problematic as long as the step is within a magnitude range at which there is no danger of a wire disconnection occurring in the subsequently formed wiring patterns.

The jig50is preferably appropriately constituted by a material such as a metal or ceramic which has a low adhesiveness in respect of the base frame20and/or the semiconductor chip30, or a material coated with Teflon (registered trademark) or the like which has a low adhesiveness in respect thereof. In so doing, the semiconductor device or unfinished constitutional body may be easily peeled away from the jig50.

A first throughhole56is preferably formed in the concave portion54of the jig50. A first suction and exhaust system58for suction-holding the base frame20on the concave portion54is preferably connected to the first through hole56. In the drawing, this suction and exhaust system is illustrated as a block.

A second through hole57is preferably formed in a similar manner in the convex portion52. A second suction and exhaust system59for suction-holding the semiconductor chip30on the convex portion52is preferably connected to the second through hole57. In the drawing, this suction and exhaust system is illustrated by a block.

The first and second suction and exhaust systems58and59may be constituted by a well-known evacuation system comprising a vacuum pump, piping, and so on, for example. Next, the second manufacturing method using the jig50for the semiconductor device of the first embodiment will be described with reference toFIGS. 12 and 13.

Note that in this second manufacturing method, the arrangement constitution of the semiconductor chips in respect of the base frame is similar to that in the first manufacturing method.

First, the jig50is prepared as shown inFIG. 11and as described above.

Then, as shown inFIG. 12(A), the base frame20is placed on the bottom surface of the concave portion54of the jig50so as to envelop the side wall portions52aof the convex portion52and such that the surface of the convex portion52is exposed in the opening portion22.

Here, when the first through hole56is provided in the concave portion54of the jig50and the first suction and exhaust system58is connected to the first through hole56as described above, air is evacuated from the contact surface (gap) between the second surface20bof the base frame20and the surface of the concave portion54, whereby the base frame20is suction-held on the jig50.

Next, as shown inFIG. 12(B), the second main surface38of the semiconductor chip30is disposed on the convex portion52which is in the opening portion22of the base frame20so as to surface the surface of the convex portion52.

At this time, if the inside walls24of the opening portion22in the base frame20have an inclined plane which tapers, or grows thinner, toward the semiconductor chip30as has already been explained with reference toFIG. 3, the semiconductor chip30can be disposed by sliding the chip along this inclined plane.

When the second through hole57is provided in the convex portion52and the second suction and exhaust system59is connected to this through hole57as described above, air is evacuated from the contact surface between the second main surface38of the semiconductor chip30and the surface of the convex portion52such that the semiconductor chip30is suction-held on the jig50.

The degree of evacuation required for suction-holding the base frame20or semiconductor chip30on the jig50should be sufficient to enable the base frame20or semiconductor chip30to be held with stability.

Next, the insulating film40is formed on the surface of the base frame20and the first main surface36of the semiconductor chip30, which are disposed on the jig50, such that the top surface of the electrode pads34provided on the semiconductor chip30is exposed (seeFIG. 12(B)).

Here, a process similar to that described in the first method may be employed such that the insulating film40is formed so as to cover the electrode pads34, whereupon the top surface of the electrode pads34is exposed. As in the first method, the insulating film40is preferably formed flat.

If a slight gap exists between the base frame20and semiconductor chip30, the insulating film40is formed by inserting the insulating material used to form the insulating film40into the gap such that the base frame20and semiconductor chip30are integrally fixed.

Next, as shown inFIG. 12(C), a plurality of wiring patterns42are formed on the surface of the insulating film40so as to form an electrical connection with the top surface of each electrode pad34. In this case, as in the first manufacturing method, one-on-one connection relationships of one wiring pattern to one electrode pad34are established. Next, one electrode post46is formed on and connected to each wiring pattern42. The electrode posts46are provided in the region of the extension portion21on the upper side of (directly above) the base frame20and in the region on the upper side of (directly above) the semiconductor chip30in the vicinity of the extension portion21.

Next, as shown inFIG. 13(A), the sealing portion44is formed so as to cover the surface of the insulating film40on which the wiring patterns42and electrode posts46are formed.

As shown inFIG. 13(B), the top surface of the electrode posts46is exposed on the surface of the sealing portion44by grinding away the surface of the sealing portion44.

Solder balls47aare then formed as external terminals47on the top surface of the exposed electrode posts46.

Next, as shown inFIG. 13(C), the jig50is peeled away from the second surface20bof the base frame20and the second main surface38of the semiconductor chip30following release of the vacuum when vacuum suction means are employed.

The base frame20and sealing portion44are then severed between a plurality of semiconductor chips30to form individual semiconductor devices.

By means of such a process, a semiconductor device having a similar constitution to that described in the first manufacturing method is manufactured.

Note that in the semiconductor device manufactured according to the second manufacturing method, a step is produced by the convex portion52of the jig50on the bottom surface side of the semiconductor device, or more specifically between the second surface20bof the base frame20and the second main surface38. If not desired, however, no further processing is necessary.

According to the second manufacturing method, the jig can be used repeatedly. Since there is no need to use a lower base as in the first manufacturing method, the number of members required in the manufacturing process can be reduced. As a result, a reduction in manufacturing costs can be expected. Further, when the base frame and/or semiconductor chip are suction-held by a suction and exhaust system via a through hole, holding the base frame and semiconductor chip on the jig and removing them therefrom can be performed easily and speedily such that an increase in throughput can be expected.

Second Embodiment

A semiconductor device according to a second embodiment of this invention will now be described with reference toFIGS. 14(A),14(B), and15(A). Note that since the plan views seen from above in the description of the second embodiment are substantially identical to the plan views already described in the first embodiment, description thereof has been omitted and the second embodiment will be described using sectional views only. Further, applied materials, process implementation conditions, and so on are similar to those of the first embodiment, and hence detailed description thereof has also been omitted.

FIG. 14(A)is a schematic plan view showing the constitution of the semiconductor device of the second embodiment, andFIG. 14(B)is a plan view showing an expanded outline of the main parts of the region in14(A) which is surrounded by a solid line11in order to illustrate the connection relationship between a wiring pattern, electrode pads, and an inter-layer wire connection (through hole).

FIG. 15(A)is a sectional view for illustrating the constitution of the semiconductor device of the second embodiment, and is a schematic sectional view showing a cross section severed along the I—I broken line inFIG. 14(A).

A semiconductor device10according to the second embodiment of this invention comprises a base frame20having an opening portion22which is a through hole passing from a first surface20ato a second surface20bin a similar fashion to the first embodiment. A region corresponding to the upper side of the first surface20aand the upper side of the second surface20bof the base frame20is an extension portion21.

The opening portion22is formed as a through hole in the base frame20. The magnitude of this opening portion22is set to be identical to or slightly larger than the space required by a stacked body comprising a first semiconductor chip30and a second semiconductor chip60. The height of the opening portion22, that is the thickness of the base frame20, is preferably set to be substantially equal to the total thickness of the stacked first and second semiconductor chips30and60. If, for example, the first and second semiconductor chips30and60are adhered to each other using an adhesive or the like, the thickness of the first semiconductor chip30and/or the second semiconductor chip60is preferably adjusted by polishing, grinding, or a similar process. If the thickness of the base frame20may be adjusted, however, the height of the opening portion22can be set equal to the total thickness of the first semiconductor chip30and second semiconductor chip60to be disposed within the opening portion22at a later stage. If the first semiconductor chip30and second semiconductor chip60are adhered to each other using an adhesive, the height of the opening portion22, or in other words the thickness of the base frame20, should be set in consideration of the thickness of the adhesive.

A through hole26other than the opening portion22may be formed as desired in the base frame20. This through hole26is provided to produce electrical continuity between the surface side and rear surface side of the base frame20. In this constitutional example, a plurality of through holes26is formed around the peripheral edge of the base frame20.

An inter-layer wiring28is formed from an appropriate conductive material such as an aluminum alloy or tungsten alloy, for example, in the interior of the through holes26for attaining electrical continuity according to a commonplace method.

The first semiconductor chip30and second semiconductor chip60are provided within the opening portion22such that a second main surface38of the former and a fourth main surface68of the latter contact each other.

The first semiconductor chip30comprises a first circuit element (not shown) having a predetermined function and a first main surface36provided with a plurality of first electrode pads34which are electrically connected to the first circuit element. The first electrode pads34are provided in a plurality around the peripheral edge of the first main surface36. The first semiconductor chip30comprises the first main surface36, the second main surface38which opposes the first main surface36, and one, two, or more side surfaces37existing between the first main surface36and second main surface38. The first semiconductor chip30is provided within the opening portion22such that the first main surface36becomes the upper surface. Similarly to the first embodiment, the first semiconductor chip30is preferably provided within the opening portion22such that the level of the first surface20aof the base frame20is substantially equal to the level of the first main surface36of the first semiconductor chip30.

Likewise, the second semiconductor chip60comprises a second circuit element (not shown) having a predetermined function, a third main surface66, the fourth main surface68which opposes the third main surface66, and one, two, or more side surfaces67which exist between the third main surface66and fourth main surface68. The second semiconductor chip60is also provided with a plurality of second electrode pads64which are electrically connected to the second circuit element. The second electrode pads64are provided in a plurality around the peripheral edge of the third main surface66.

The second semiconductor chip60is provided within the opening portion22such that the third main surface66thereof faces downward and the level of the second surface20bof the base frame20is substantially equal to the level of the third main surface66of the second semiconductor chip60. Here, the second main surface38of the first semiconductor chip30and the fourth main surface68of the second semiconductor chip60are preferably adhered to each other and fixed using an adhesive or the like.

A first insulating film40is formed on the first surface20aof the base frame20and the first main surface36of the first semiconductor chip30such that a part of the first electrode pads34and one end portion of the inter-layer wiring28are exposed.

A second insulating film70is similarly formed on the second surface20bof the base frame20and the third main surface66of the second semiconductor chip60such that a part of each of the second electrode pads64and the other end portion of the inter-layer wiring28are exposed.

A plurality of first wiring patterns42is formed on the surface of the first insulating film40and electrically connected to the exposed part of the first electrode pads34and/or the exposed one end portion of the inter-layer wiring28.

Similarly, a plurality of second wiring patterns72is formed on the surface of the second insulating film70and electrically connected to the exposed part of the second electrode pads64and/or the exposed other end portion of the inter-layer wiring28.

The first wiring patterns42include wiring patterns that provided so as to straddle the boundary between a region on the first semiconductor chip30and a region on the first surface20aof the base frame20.

Similarly, the second wiring patterns72are provided so as to straddle the boundary between a region on the second semiconductor chip60and a region on the second surface20bof the base frame20.

Since the first and second wiring patterns42and72are formed so as to straddle the boundary between the region on the upper side of (directly above) the first surface20aof the base frame20or the second surface20bof the base frame20and on the upper side of (directly above) the first semiconductor chip30or the second semiconductor chip60respectively, the portions42X (and72X (not shown)) of the first and second wiring patterns42and72on or in the vicinity of these boundaries (22) are preferably formed over a certain length and of thicker wire. In other word, The portions42X of the wiring patterns42on a boundary and vicinity thereof between a region on the upper side of said semiconductor chip30and the base flame20are formed wider or more thickly than other portions of said wiring patterns42.

Here, when the inter-layer wire connection28exists, one end portion thereof is electrically connected to the first wiring pattern42and the other end portion thereof is electrically connected to the second wiring pattern72. Thus an output signal of the first semiconductor chip30and an output signal of the second semiconductor chip60can be outputted to the rear surface (lower surface) side of the semiconductor device10and the surface (upper surface) of the semiconductor device10respectively. For example, an output signal of the second semiconductor chip60can be inputted into the first semiconductor chip30via the first wiring pattern42.

First and second sealing portions44and74are formed on the surface of first and second insulating films40and70on which the first and second wiring patterns42and72are formed such that a part of each of the first and second wiring patterns42and72is exposed. The first insulating film40and first sealing portion44may be referred to collectively as a first insulation layer48and the second insulating film70and second sealing portion74may be referred to collectively as a second insulation layer78. Here, the part of the first and second wiring patterns42and72which is connected to the inter-layer wiring28may also be exposed.

Then, first and second external terminals47and77are connected on the upper side of (directly above) the first surface20aand second surface20bof the base frame20above the exposed first and second wiring patterns42and72, or in other words in a region including the extension portion21.

For example, a plurality of first and second external terminals47and77are formed using first and second solder balls47aand77avia first and second electrode posts46and76respectively.

Here, external terminals may also be connected to the first and second wiring patterns42and72which are connected to the inter-layer wiring28. For example, the first wiring pattern42which is connected to the first electrode pads34is connected to the inter-layer wiring28instead of an external terminal, and through the inter-layer wiring28and the second wiring pattern72which is not connected to the second electrode pads64, an external terminal can be formed on the second wiring pattern72. An external terminal can also be directly connected to the inter-layer wiring (through hole)28.

The spacing between adjacent first electrode posts46and adjacent second electrode posts76may be determined appropriately as desired in consideration of mounting onto a printed board or the like.

The first and second electrode posts46and76may be provided not only within a surface area range corresponding to the first and third main surfaces36and66of the first and second semiconductor chips30and60, but also in the region including the first surface20aand second surface20bof the base frame20, or in other words the extension portion21. As a result, the design freedom of the disposal positions and disposal pitch of the first and second electrode posts46and76increases. More specifically, restrictions on the disposal pitch of the first and second electrode posts46and76, or in other words the first and second external terminals47and77, are eased such that the external terminals can be formed at wider intervals in accordance with requirements on the mounting substrate side, for example. As a result, the semiconductor device10can be more easily mounted on a mounting substrate.

According to the semiconductor device of the second embodiment, in addition to similar effects to the first embodiment, two semiconductor chips can be directly stacked such that the semiconductor device can be made thinner. Also, two semiconductor chips can be connected via a through hole, for example, and thus an input signal to one of the semiconductor chips or an output signal from one of the semiconductor chips, for example, can be inputted or outputted directly to or from the semiconductor device on the opposite side without passing through conventionally used and highly problematic metal wires. As a result, a further increase in the operating speed and number of functions of the semiconductor device can be realized.

A further increase in the operating speed and number of functions can be easily realized when a plurality of the semiconductor devices of the second embodiment are stacked by connecting the external terminals thereof to form stacking terminals. Since these stacking terminals can also be disposed in the so-called fan-in portion, the package may be further reduced in size and thickness.

Modified Example of the Semiconductor Device of the Second Embodiment

A modified example of the semiconductor device of the second embodiment will now be described with reference toFIG. 15(B). Note that the plan view seen from above thereof is similar toFIG. 14(A)and hence detailed description has been omitted.

FIG. 15(B)is a schematic sectional view showing a transverse section of a semiconductor device10′ according to a modified example of the second embodiment.

The semiconductor device10′ of this modified example differs in the form of inner walls24of the opening portion22in the base frame20. Accordingly, other similar constitutional components to the first and second embodiments are allocated and illustrated with identical reference symbols and duplicate description thereof has been omitted.

In the semiconductor device10′ of this modified example, the cross-sectional form of the inner walls24which define the opening portion22of the base frame20tapers, or grows thinner, toward the distal end of the walls24from both surface sides of the base frame20to the semiconductor chip side. More specifically, the thickness of the inner walls24decreases from both the first surface20aand second surface20bsides of the base frame20toward the side surface of the first and second semiconductor chips30and60provided within the opening portion22.

By forming the inner walls24in this manner, in addition to the working effects of the semiconductor device described in the second embodiment, advantageous effects (to be described hereinafter) can be obtained particularly in the manufacturing process.

Manufacturing Method of the Second Embodiment

Next, a manufacturing method for the semiconductor device of the second embodiment will be described with reference toFIGS. 16(A) through 18(C). Note that in these drawings, the plan views are substantially identical to those used in the first embodiment and hence illustration and detailed description thereof have been omitted. Applied materials, process implementation conditions, and so on are also similar to those of the first embodiment and hence detailed description thereof has also been omitted.

Each drawing is a schematic sectional view showing a transverse section of a constitutional body which is a semiconductor device during manufacture. Note that in each of the following manufacturing processes, applied materials, process implementation conditions, and so on are similar to those of the manufacturing methods of the first embodiment and hence detailed description thereof has been omitted.

In the manufacturing method for the semiconductor device of the second embodiment, as in the second manufacturing method of the first embodiment described above, a jig is used to implement a part of the manufacturing processes.

First, a preferable jig for application to the manufacturing method of the second embodiment will be described. Note, however, that this jig has a substantially identical constitution to and is constituted by the same materials as the jig50already described with reference toFIG. 11and hence detailed description thereof has been omitted. This identical constitution will be described using identical reference symbols with reference toFIGS. 11(A) and 11(B).

The jig50which is preferably applied to the manufacturing method of the second embodiment is similar to that of the first embodiment in that it comprises a plurality of convex portions52and concave portions54which are positioned in the gaps between these convex portions52. The jig50is also similar in that the profile and surface area of the surface region of each convex portion52at least matches, or in other words is identical to, the profile and surface area of the second main surface38of the semiconductor chip30. The jig50which is preferably applied to the manufacturing method for the semiconductor device of the second embodiment differs in the height of the convex portion52, that is a height h of side wall portions52a.

Specifically, the height h of the side wall portions52ais set such that when the base frame20is placed on the concave portion54of the jig50and the first semiconductor chip30is placed on the surface of the convex portion52in a manufacturing process, the level of the first main surface36of the first semiconductor chip30is substantially equal to the level of the first surface20aof the base frame20.

As noted above, there is no particular problem even if a slight height difference exists at this time between the first semiconductor chip30and the base frame20as long as problems such as wire pattern disconnection do not occur as a result of this height difference.

Similarly to that of the jig described in the first embodiment, the first through hole56is preferably formed in the concave portion54and/or the second through hole57is preferably formed in the convex portion52. Also, the first and second suction and exhaust systems58and59are preferably connected to the first through hole56and second through hole57respectively for suction-holding the base frame20on the concave portion54and the semiconductor chip30on the convex portion52.

Next, the manufacturing method using the jig50for the semiconductor device of the second embodiment will be described.

First, the jig50having the constitution described above is prepared.

Then, as shown inFIG. 16(A), the base frame20having a plurality of opening portions22, which are through holes for exposing the surface of the convex portion52, is placed on the concave portion54of the jig50so as to envelop the side wall portions52aof the convex portion52.

When the through hole26is formed in the base frame20as described with reference toFIGS. 15(A) and 15(B), the interior of the through hole26is formed as the inter-layer wiring28from a conductive material such as an aluminum alloy or tungsten alloy, for example, for attaining electrical continuity according to a commonplace method.

As noted above, when the first throughhole56is provided in the concave portion54and the first suction and exhaust system58is connected thereto, air is evacuated from the contact surface (gap) between the second surface20bof the base frame20and the surface of the concave portion54such that the base frame20is suction-held thereon.

Next, as shown inFIG. 16(B), the second main surface38of the first semiconductor chip30is disposed on the convex portion52inside the opening portion22of the base frame20so as to face the convex portion52.

Here, when the inner walls24of the opening portion22in the base frame20are inclined as described with reference toFIG. 15(B), the first semiconductor chip30is disposed by sliding the chip along the inclined surface.

When the second through hole57is provided in the convex portion52and the second suction and exhaust system59is connected thereto as described above, air is evacuated from the contact surface between the second main surface38of the first semiconductor chip30and the surface of the convex portion52such that the first semiconductor chip30is suction-held thereon.

Next, the first insulating film40is formed on the first surface20aof the base frame20disposed on the jig50and the first main surface36of the first semiconductor chip30such that a part of the first electrode pads34is exposed. Here, if the inter-layer wiring28is formed (seeFIGS. 15(A),15(B)), the first insulating film40is formed such that the inter-layer wiring28is exposed.

As described in relation to the first embodiment, the first insulating film40may be initially formed to cover the first electrode pads34and inter-layer wiring28, whereupon the first electrode pads34and inter-layer wiring28are exposed. As in the first embodiment, the first insulating film40is preferably formed flat.

If a slight gap exists between the base frame20and first semiconductor chip30, the insulating material used to form the first insulating film40is inserted into the gap, whereby the first insulating film40is formed such that the base frame20and first semiconductor chip30are integrally fixed.

Next, as shown inFIG. 16(C), the first wiring pattern42comprising a plurality of wiring patterns is formed on the surface of the first insulating film40. Some of the wiring patterns are electrically connected to a part of the exposed first electrode pads34. If the inter-layer wiring28exists, the first electrode pads34and inter-layer wiring28may also be electrically connected via the first wiring pattern42at this time.

Next, as shown inFIG. 17(A), electrode posts46are formed on the first wiring pattern42. As in the first embodiment, as a rule one electrode post is provided for one wiring pattern. These electrode posts46are formed not only on the wiring patterns on the upper side of the semiconductor chip30, but a plurality of electrode posts46is also formed in a region corresponding to the upper side of (directly above) the first surface20aof the base frame20, or in other words in the region which functions as the extension portion21.

Next, the first sealing portion44is formed to cover the surface of the first insulating film40on which the first wiring pattern42and first electrode posts46are formed.

A sealing portion is then formed by a similar process on the third main surface66side of the second semiconductor chip60. That is, the base frame20having the first semiconductor chip30provided inside the opening portion22thereof is removed from the jig50and the constitutional body is turned over such that the third main surface66of the second semiconductor chip60becomes the upper surface.

As shown inFIG. 17(B), the second semiconductor chip60is disposed on the second main surface38of the first semiconductor chip30inside the opening portion22such that the fourth main surface68of the second semiconductor chip60faces the second main surface38.

Here, the second main surface38of the first semiconductor chip30and the fourth main surface68of the second semiconductor chip60are preferably adhered together by an adhesive or the like.

If the level of the third main surface66of the second semiconductor chip60and the level of the second surface20bof the base frame20do not align, the level of the third main surface66of the second semiconductor chip60and the level of the second surface20bof the base frame20may be adjusted to become substantially equal by inserting a type of spacer member between the first semiconductor chip30and the fourth main surface68of the second semiconductor chip60or by adjusting the thickness of the adhesive or the like.

As noted above, the semiconductor device according to the second embodiment of this invention is also applicable when there is a difference in the planar sizes of the first semiconductor chip30and second semiconductor chip60, or in other words between the first and third main surfaces and the second and fourth main surfaces. Here, the size of the gap between the base frame20and first semiconductor chip30or second semiconductor chip60is set in a magnitude range within which the subsequently formed second wiring pattern72may be formed.

Hence, as long as a height difference or gap which forms between the base frame20and the first semiconductor chip30or second semiconductor chip60is within a range at which the subsequently formed second wiring pattern72can be formed without problems, no adjustment thereof by means of further processing is necessary.

Next, the second insulating film70, second electrode pads64, and if required the inter-layer wire connection28are formed so as to be exposed on the second surface20bof the base frame20and the third main surface66of the semiconductor chip60.

Then, as shown inFIG. 17(C), a plurality of second wiring patterns72is formed on the surface of the second insulating film70and electrically connected to the exposed part of the second electrode pads64. Here, if the inter-layer wire connection28exists, the second electrode pads64and inter-layer wiring28may also be electrically connected via the second wiring patterns72.

The second wiring patterns72are also formed on the upper side of (directly above) the second semiconductor chip60and the upper side of (directly above) the second surface20bof the base frame20.

Next, as shown inFIG. 18(A), the second electrode posts76are formed on the second wiring patterns72. The second electrode posts76are also provided one-to-one with the second wiring patterns72. The second electrode posts76are formed not only on the second wiring patterns72on the upper side of the second semiconductor chip60but also on the wiring patterns72in the region on the upper side of (directly above) the second surface20bof the base frame20.

Next, the second sealing portion74is formed to cover the surface of the second insulating film70on which the second wiring patterns72and second electrode posts76are formed. Then, as shown inFIG. 18(B), the surfaces of the first and second sealing portions44and74are trimmed such that the end portions, for example the top surfaces, of the first and second electrode posts46and76are exposed.

The first and second solder balls47a,77aare then formed on the top surfaces of the exposed first and second electrode posts46and76to serve as first and second external terminals47and77.

Alternatively, the external terminals may be formed with differing shapes, for example constituting the first external terminals47with solder balls and the second external terminals77as so-called lands.

The first and second external terminals47and77may be used not only for mounting the semiconductor device on a mounting substrate as described above, but also as terminals for stacking a plurality of the semiconductor devices according to the second embodiment of this invention or other semiconductor devices.

Next, as shown inFIG. 18(C), the plurality of adjacent opening portions22are severed to produce individual semiconductor devices comprising the first and second semiconductor chips30and60.

By means of such a process, the semiconductor device10of the second embodiment is manufactured.

In this manufacturing method for the semiconductor device of the second embodiment, an example was described in which the processes on the second semiconductor chip60side are implemented following the first sealing portion forming step on the first semiconductor chip30side. This invention is not limited thereto, however, and the second external terminals77may be formed on the second semiconductor chip60side following the first external terminal47forming step on the first main surface36side of the first semiconductor chip30, for example.

According to the manufacturing method of the second embodiment, a functionally sophisticated, high-speed semiconductor device having two stacked chips can be manufactured by an easy process. Since the jig can be used repeatedly, a reduction in manufacturing costs can be expected. Further, when the base frame and semiconductor chip are suction-held by a suction and exhaust system via a through hole, holding the base frame and semiconductor chip on the jig and removing them therefrom can be performed easily and speedily such that an increase in the throughput of the manufactured semiconductor devices can be expected.

The wiring pattern in the semiconductor device of this invention may be formed in a desired pattern in consideration of the output signals of the semiconductor chips and the disposal positions and so on of the external terminals required in the semiconductor device.

In all embodiments of this invention, the electrode posts46are preferably formed from a conductive material. This material is preferably copper. A thin oxidation layer is preferably formed on the surface of the electrode posts46. In so doing, the adhesive property between the electrode posts46and the sealing portion44is improved, thereby improving resistance to moisture.

In all embodiments of this invention the solder balls47aare formed on the electrode posts46as the external terminals47. A so-called BGA (Ball Grid Array) has been described, but this invention is not limited thereto. For example, a so-called LGA (Land Grid Array) may be formed by applying and reflow soldering solder paste to the top surface of the exposed electrode posts46or implementing Ni/Au processing by means of electroless plating.

More specifically, either the solder layer is formed directly on the top surface of the electrode posts46, or a barrier metal layer is formed on the top surface of the electrode posts46and then a metal (Au) plating layer is formed on the barrier metal layer. Alternatively, the external terminals may be constituted by forming an Sn (tin) layer directly onto the top surface of the electrode posts46as a land.

The external terminals47may also be directly connected to the wiring pattern42without passing through the electrode posts.

In all embodiments of this invention, the sealing portion may be formed not only in a so-called saw-cut form, but may also be formed not matching the profile of the base frame and/or the extension portion as long as the extent of this mismatch is within a range which does not impair the object of this invention.