Image display apparatus and control method thereof

An image display apparatus includes a memory 1 having a first mode and a second mode in which image data are sequentially written and read per frame and per sub-frame area respectively, a compressor 10 capable of switching a compression output state and an uncompressed output state in which a compression image data and an uncompressed image data are outputted respectively, and a decompressor 20 capable of switching a decompression output state and a non-decompression output state. A controller 6 switches the compressor from the uncompressed output state to the compression output state during a first input vertical blanking period, switches the decompressor from the non-decompression output state to the decompression output state during a first output vertical blanking period immediately after the first input vertical blanking period, and switches the memory from the second mode to the first mode during a first output vertical blanking period.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an image display apparatus such as a projector or a monitor.

2. Description of the Related Art

An image signal (image data) having a high resolution may be inputted to an image display apparatus. In this case, the capacity of the image data is enlarged. If the capacity of a frame buffer provided in the image display apparatus increases or the access speed for the frame buffer speeds up in order to cope with the image data having the large amount of capacity, the cost is increased. Therefore, the technology of reducing the capacity of the image data written in the frame buffer by compressing the image data is widely used.

The compression processing is preferably performed by using a simple method such as a bit shift method in view of costs, but such a compression method causes a deterioration of an image quality since it is a lossy color (gradation) compression processing. Therefore, a case where the lossy color compression processing is applied needs to be limited.

For example, Japanese Patent Laid-Open No. 2007-72360 discloses an image display apparatus that switches the application and the non-application of the lossy color compression processing in accordance with whether a keystone adjustment is effective or ineffective in order to limit the case where the lossy color compression processing is applied.

However, in the image display apparatus disclosed in Japanese Patent Laid-Open No. 2007-72360, the disturbance of the image generated at the time of switching the application and the non-application of the lossy color compression processing such as a bit shift needs to be concealed. Therefore, it cannot be used in a case where the switching the application and the non-application of the lossy color compression processing is frequently performed.

SUMMARY OF THE INVENTION

The present invention provides an image display apparatus capable of reducing a disturbance or a discontinuity of an image at the time of switching the application and the non-application of a lossy compression processing.

An image display apparatus as one aspect of the present invention includes a memory including a first mode in which an image data is sequentially written and read per frame and a second mode in which the image data is sequentially written and read per sub-frame area obtained by dividing the frame, a compressor capable of switching a compression output state in which a compression image data generated by compressing an input image data is outputted and an uncompressed output state in which an uncompressed image data without compressing the input image data is outputted as the image data written in the memory, a decompressor capable of switching a decompression output state in which the compression image data read from the memory is decompressed to be outputted and a non-decompression output state in which the uncompressed image data read from the memory is not decompressed to be outputted, and a controller configured to switch the compressor from the uncompressed output state to the compression output state during a first input vertical blanking period, switch the decompressor from the non-decompression output state to the decompression output state at the same time as the first input vertical blanking period or during a first output vertical blanking period immediately after the first input vertical blanking period, and switch the memory from the second mode to the first mode during the first output vertical blanking period or a second output vertical blanking period immediately after the first output vertical blanking period, where a vertical blanking period of an input image to the compressor is defined as an input vertical blanking period and a vertical blanking period of an output image from the decompressor is defined as an output vertical blanking period.

An image display apparatus as another aspect of the present invention includes a memory including a first mode in which an image data is sequentially written and read per frame and a second mode in which the image data is sequentially written and read per sub-frame area obtained by dividing the frame, a compressor capable of switching a compression output state in which a compression image data generated by compressing an input image data is outputted and an uncompressed output state in which an uncompressed image data without compressing the input image data is outputted as the image data written in the memory, a decompressor capable of switching a decompression output state in which the compression image data read from the memory is decompressed to be outputted and a non-decompression output state in which the uncompressed image data read from the memory is not decompressed to be outputted, and a controller configured to switch the memory from the first mode to the second mode during a first output vertical blanking period, switch the compressor from the compression output state to the uncompressed output state during a first input vertical blanking period immediately after the first output vertical blanking period, and switch the decompressor from the decompression output state to the non-decompression output state at the same time as the first input vertical blanking period or during a second output vertical blanking period immediately after the first input vertical blanking period, where a vertical blanking period of an input image to the compressor is defined as an input vertical blanking period and a vertical blanking period of an output image from the decompressor is defined as an output vertical blanking period.

An image display apparatus as another aspect of the present invention includes a memory including a first mode in which an image data is sequentially written and read per frame and a second mode in which the image data is sequentially written and read per sub-frame area obtained by dividing the frame, a compressor capable of switching a compression output state in which a compression image data generated by compressing an input image data is outputted and an uncompressed output state in which an uncompressed image data without compressing the input image data is outputted as the image data written in the memory, a decompressor capable of switching a decompression output state in which the compression image data read from the memory is decompressed to be outputted and a non-decompression output state in which the uncompressed image data read from the memory is not decompressed to be outputted, and a controller configured to switch the compressor from the uncompressed output state to the compression output state and also switch the decompressor from the non-decompression output state to the decompression output state during a first output vertical blanking period or a first input vertical blanking period, and switch the memory from the second mode to the first mode during the first output vertical blanking period and a second output vertical blanking period immediately after the first input vertical blanking period, where a vertical blanking period of an input image to the compressor is defined as an input vertical blanking period and a vertical blanking period of an output image from the decompressor is defined as an output vertical blanking period.

An image display apparatus as another aspect of the present invention includes a memory including a first mode in which an image data is sequentially written and read per frame and a second mode in which the image data is sequentially written and read per sub-frame area obtained by dividing the frame, a compressor capable of switching a compression output state in which a compression image data generated by compressing an input image data is outputted and an uncompressed output state in which an uncompressed image data without compressing the input image data is outputted as the image data written in the memory, a decompressor capable of switching a decompression output state in which the compression image data read from the memory is decompressed to be outputted and a non-decompression output state in which the uncompressed image data read from the memory is not decompressed to be outputted, and a controller configured to switch the memory from the first mode to the second mode during a first output vertical blanking period, and switch the compressor from the compression output state to the uncompressed output state and also switch the decompressor from the decompression output state to the non-decompression output state during a second output vertical blanking period immediately after the first output vertical blanking period or a first input vertical blanking period immediately after the second output vertical blanking period, where a vertical blanking period of an input image to the compressor is defined as an input vertical blanking period and a vertical blanking period of an output image from the decompressor is defined as an output vertical blanking period.

A method as another aspect of the present invention is a method of controlling an image display apparatus including a memory including a first mode in which an image data is sequentially written and read per frame and a second mode in which the image data is sequentially written and read per sub-frame area obtained by dividing the frame, a compressor capable of switching a compression output state in which a compression image data generated by compressing an input image data is outputted and an uncompressed output state in which an uncompressed image data without compressing the input image data is outputted as the image data written in the memory, and a decompressor capable of switching a decompression output state in which the compression image data read from the memory is decompressed to be outputted and a non-decompression output state in which the uncompressed image data read from the memory is not decompressed to be outputted. The method includes the steps of switching the compressor from the uncompressed output state to the compression output state during a first input vertical blanking period, switching the decompressor from the non-decompression output state to the decompression output state at the same time as the first input vertical blanking period or during a first output vertical blanking period immediately after the first input vertical blanking period, and switching the memory from the second mode to the first mode during the first output vertical blanking period or a second output vertical blanking period immediately after the first output vertical blanking period, where a vertical blanking period of an input image to the compressor is defined as an input vertical blanking period and a vertical blanking period of an output image from the decompressor is defined as an output vertical blanking period.

A method as another aspect of the present invention is a method of controlling an image display apparatus including a memory including a first mode in which an image data is sequentially written and read per frame and a second mode in which the image data is sequentially written and read per sub-frame area obtained by dividing the frame, a compressor capable of switching a compression output state in which a compression image data generated by compressing an input image data is outputted and an uncompressed output state in which an uncompressed image data without compressing the input image data is outputted as the image data written in the memory, and a decompressor capable of switching a decompression output state in which the compression image data read from the memory is decompressed to be outputted and a non-decompression output state in which the uncompressed image data read from the memory is not decompressed to be outputted. The method includes the steps of switching the memory from the first mode to the second mode during a first output vertical blanking period, switching the compressor from the compression output state to the uncompressed output state during a first input vertical blanking period immediately after the first output vertical blanking period, and switching the decompressor from the decompression output state to the non-decompression output state at the same time as the first input vertical blanking period or during a second output vertical blanking period immediately after the first input vertical blanking period, where a vertical blanking period of an input image to the compressor is defined as an input vertical blanking period and a vertical blanking period of an output image from the decompressor is defined as an output vertical blanking period.

A method as another aspect of the present invention includes a method of controlling an image display apparatus including a memory including a first mode in which an image data is sequentially written and read per frame and a second mode in which the image data is sequentially written and read per sub-frame area obtained by dividing the frame, a compressor capable of switching a compression output state in which a compression image data generated by compressing an input image data is outputted and an uncompressed output state in which an uncompressed image data without compressing the input image data is outputted as the image data written in the memory, and a decompressor capable of switching a decompression output state in which the compression image data read from the memory is decompressed to be outputted and a non-decompression output state in which the uncompressed image data read from the memory is not decompressed to be outputted. The method includes the steps of switching the compressor from the uncompressed output state to the compression output state and also switching the decompressor from the non-decompression output state to the decompression output state during a first output vertical blanking period or a first input vertical blanking period, and switching the memory from the second mode to the first mode during the first output vertical blanking period and a second output vertical blanking period immediately after the first input vertical blanking period, where a vertical blanking period of an input image to the compressor is defined as an input vertical blanking period and a vertical blanking period of an output image from the decompressor is defined as an output vertical blanking period.

A method as another aspect of the present invention is a method of controlling an image display apparatus including a memory including a first mode in which an image data is sequentially written and read per frame and a second mode in which the image data is sequentially written and read per sub-frame area obtained by dividing the frame, a compressor capable of switching a compression output state in which a compression image data generated by compressing an input image data is outputted and an uncompressed output state in which an uncompressed image data without compressing the input image data is outputted as the image data written in the memory, and a decompressor capable of switching a decompression output state in which the compression image data read from the memory is decompressed to be outputted and a non-decompression output state in which the uncompressed image data read from the memory is not decompressed to be outputted. The method includes the steps of switching the memory from the first mode to the second mode during a first output vertical blanking period, and switching the compressor from the compression output state to the uncompressed output state and also switching the decompressor from the decompression output state to the non-decompression output state during a second output vertical blanking period immediately after the first output vertical blanking period or a first input vertical blanking period immediately after the second output vertical blanking period, where a vertical blanking period of an input image to the compressor is defined as an input vertical blanking period and a vertical blanking period of an output image from the decompressor is defined as an output vertical blanking period.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Exemplary embodiments of the present invention will hereinafter be described with reference to the accompanying drawings.

FIG. 1illustrates a configuration of a part related to a processing of an image signal (image data) in an image display apparatus that is Embodiment 1 of the present invention. Various kinds of image display apparatuses such as an image projection apparatus of a liquid crystal projector, a DLP (Digital Light Processing) projector, or the like, and a direct-view liquid crystal monitor are included as the image display apparatus.

The image display apparatus includes a writing processor (a compressor)10, an image memory (a memory)1, a reading processor (a decompressor)20, an image processor2, a synchronization detector3, an output clock generator4, an operating portion5, and a switch timing controller (a controller)6.

The writing processor10, as indicated by a dashed line inFIG. 1, includes a compressor11, a compression application switch12, and a writing controller13. The writing processor10converts a format of the image data written in the image memory1and controls a writing mode and a writing address in the image memory1.

The compressor11compresses the image data (an input image data) inputted as an input image signal to generate a compression image data whose size is smaller than that of the input image data. The compression means a lossy compression processing such as a resolution conversion, a bit width reduction, or a color subtraction.

The compression application switch12can be switched between a state of selecting a compression route where the input image data is written in the image memory1via the compressor11and a state of selecting a detour route where it is written in the image memory1bypassing the compressor11. The state of selecting the compression route corresponds to a compression output state, and the state of selecting the detour route corresponds to an uncompressed output state. An output of the compression application switch12is a compression image data when the input image data is obtained via the compressor11, and on the other hand an output of the compression application switch12is an uncompressed image data when the input image data bypasses the compressor11.

The writing controller13controls the switching of the writing mode of the image memory1and the switching of the compression application switch12. The writing mode includes a first access mode (a first mode) and a second access mode (a second mode). In the first access mode, the image data is sequentially written at a writing address which is different per frame. The image data of each frame is stored only for one vertical synchronization period. In the second access mode, each frame of the image data is divided into a sub-frame area (for example, a half area of one frame) including a plurality of lines, and is sequentially written at a writing address which is different per sub-frame area. The image data of each sub-frame area is stored only for one sub-frame period.

The writing controller13appropriately controls the number of writing pixels per access to the image memory1in accordance with the difference of an amount of the image data depending on the route selected by the compression application switch12, and specifies the writing address to the image memory1in accordance with the number of the writing pixels. The timing of changing the writing mode is determined by the switch timing controller6based on the synchronization signal outputted from the synchronization detector3.

In the image memory1, the image data (the compression image data or the uncompressed image data) outputted from the compression application switch12is written at the writing address specified by the writing controller13. The image memory1outputs the image data at the address that the reading controller23described below specifies for the reading processor20.

The reading processor20, as indicated by a dashed line inFIG. 1, includes a decompressor21, a decompression application switch22, and a reading controller23. The reading processor20converts a format of the image data read from the image memory1and controls the reading mode and the address from the image memory1.

The decompressor21decompresses the image data (the compression image data) compressed by the compressor11to the image data of the original size (a decompression image data).

The decompression application switch22can be switched between a state of selecting the decompression route where the compression image data read from the image memory1is outputted via the decompressor21(a decompression output state) and a state of selecting a detour route where it is outputted bypassing the decompressor21(a non-decompression output state). The image data outputted from the decompression application switch22is inputted to the image processor2.

The reading controller23controls the switching of the reading mode of the image memory1and the switching of the decompression application switch22. The reading mode includes a first access mode (a first mode) and a second access mode (a second mode) that correspond to the first access mode and the second access mode as the writing mode described above, respectively. The image data is sequentially read from the image memory1per frame in the first access mode in the reading mode, and the image data is sequentially read per sub-frame in the second access mode.

The image data read from the image memory1corresponds to the image data of the image area required by the image processor2. The reading controller23appropriately controls the number of reading pixels per access to the image memory1in accordance with the difference of an amount of the image data depending on the route selected by the decompression application switch22, and specifies the reading address from the image memory1in accordance with the number of the reading pixels. The timing of changing the reading mode is determined by the switch timing controller6based on the synchronization signal outputted from the output clock generator4.

The switch timing controller6, as described above, controls the writing mode of the image memory1and the switching (the switch timing) of the compression application switch12via the writing controller13based on the synchronization signal outputted from the synchronization detector3. Moreover, the switch timing controller6, as described above, controls the reading mode of the image memory1and the switching of the decompression application switch22(the switch timing) via the reading controller23based on the synchronization signal outputted from the output clock generator4.

The image processor2performs a resolution conversion processing that coverts the image data outputted from the reading processor20into an image data having a magnification set by the switch timing controller6. The image data after the resolution conversion processing is outputted to a display that is not illustrated (for example, a liquid crystal projector or a liquid crystal panel if it is a liquid crystal monitor), and an image in accordance with the set magnification is displayed on the display.

When the extent of the reduction or the enlargement in the reduction conversion processing is enlarged, the time required for storing the image data from writing to reading times in the image memory1needs to be longer. Therefore, the first access mode that can store the image data for a longer time is more advantageous than the second access mode. In other words, when a larger amount of the reduction or enlargement ratio is achieved, the writing or the reading by the first access mode for the image memory1needs to be performed.

A synchronization component of the input image signal is inputted to the synchronization detector3. The synchronization detector3supplies horizontal and vertical synchronization signals to the writing controller13, and supplies the vertical synchronization signal to the switch timing controller6.

The output clock generator4outputs a pixel clock that is used for operating the image memory1and each latter part of it, the horizontal synchronization signal, and the vertical synchronization signal.

The operating portion5includes an operating member such as a button, a dial, a keyboard, or a pointing device to be operated by a user to set the magnification of the reduction or the enlargement of the image displayed on the display.

The switch timing controller6, regarding the input from the operating portion5as a trigger, instructs the selections (the switches) of the access mode of the image memory1and the routes of the compression application switch12and the decompression application switch22, and also performs the setting of the magnification of the reduction or enlargement for the image processor2. The selections of the access mode and the routes are divided into the following three cases, depending on the magnitude relation between the size of the input image data (an amount of the image data) and the size of the image memory1(a capacity) and a set magnification of the image processor2.

The first case is a case where the size of the input image data is smaller than the size of the image memory1. In this case, the first access mode that can store the image data of one frame only for one vertical period is selected, and both the compression application switch12and the decompression application switch22select the detour routes.

The second case is a case where the size of the input image data is larger than the size of the image memory1and the magnification in the image processor2is the same magnification or near the same magnification. In this case, the reduction of the image data size by the compression route is not necessary. Therefore, the second access mode in which the image data of the one sub-frame is stored only for one sub-frame period is selected, and both the compression application switch12and the decompression application switch22select the detour route.

The third case is a case where the size of the input image data is larger than the size of the image memory1and the magnification in the image processor2is significantly different from the same magnification. In this case, since the magnification is significantly different from the same magnification, the time required for storing the image data in the image memory1needs to be longer, the reduction of the image data size by the compression route is necessary. Therefore, the first access mode in which the image data of one frame can be stored only for one vertical period is selected, and the compression application switch12and the decompression application switch22select the compression route and the decompression route, respectively.

Thus, the selection of the access mode and the selection of the compression/decompression/detour route are appropriately performed to reduce a case where an image quality is deteriorated by the lossy compression processing performed by the compressor12.

Next, referring toFIGS. 2A and 2B, the timing (a control method) of performing the switches of the access mode and the compression/decompression/detour route by the switch timing controller6will be described. The switch timing controller6performs the following processing (step) in accordance with a computer program stored in an embedded memory.

When the magnification of the reduction or the enlargement is changed in a case where the size of the input image data is larger than the size of the image memory1, there is a case where the access mode and the route need to be switched in accordance with the magnification. The switching is instantly performed while the image is displayed, and also it is preferable that the discontinuity or the disturbance of the image is not generated or is small to be invisible.

FIG. 2Aillustrates operation timings of (D) the compression application switch12, (E) the writing controller13, (F) the decompression application switch22, and (G) the reading controller23, and (H) the image processor2when the operation of instructing the enlargement from the same magnification to a high magnification is performed by (A) the operating portion5. The processing ofFIG. 2Acorresponds to claims1and7.

Each operation timing needs to be performed during a vertical blanking period (an input vertical blanking period) of the input image signal inputted to the writing processor10and a vertical blanking period (an output vertical blanking period) of the output image signal outputted from the reading processor20. In the present embodiment, an interrupt by (B) the vertical synchronization signal outputted from the synchronization detector3is used as an indicator of an incoming timing of the input vertical blanking period. Moreover, an interrupt by (C) the vertical synchronization signal outputted from the output clock generator4is used as an indicator of an incoming timing of the output vertical blanking period.

After the enlargement instruction operation from the same magnification to the high magnification is performed by the operating portion5, (B) the vertical synchronization signal outputted from the synchronization detector3is sequentially defined as IV1, IV2, IV3, and the like, and (C) the vertical synchronization signal outputted from the output clock generator4is sequentially defined as OV1, OV2, OV3, and the like. OV1, OV2, and OV3are outputted next to (immediately after) IV1, IV2, and IV3, respectively. Instead of this, however, OV1, OV2, and OV3may be outputted at the same time as IV1, IV2, and IV3, respectively.

During IV1(the first input vertical blanking period), (D) the compression application switch12is switched from the detour route to the compression route via the writing controller13.

During OV1(the first output vertical blanking period immediately after the first input vertical blanking period), (F) the decompression application switch22is switched from the detour route to the decompression route via the reading controller23.

During IV2, the access mode (the writing mode) to the image memory1is switched from the second access mode to the first access mode via (E) the writing controller13.

During OV2(the second output vertical blanking period immediately after the first output vertical blanking period), the access mode (the reading mode) for the image memory1is switched from the second access mode to the first access mode via (G) the reading controller23.

During OV3, the set magnification in (H) the image processor2is switched from the same magnification to the high magnification.

The processings of switching the access mode and the compression/decompression/detour route described above are performed to be able to eliminate or reduce the disturbance or the discontinuity of the image in enlarging the image displayed on the display from the same magnification to the high magnification (in the switching where the lossy compression processing is applied).

If there is a room for the processing capacity, the processing that is to be performed during IV2is also performed during IV1and the processings that are to be performed during OV2and OV3are also performed during OV1to be able to shorten the time required for the total of the switch processings.

FIG. 2Billustrates operation timings of (D) the compression application switch12, (E) the writing controller13, (F) the decompression application switch22, (G) the reading controller23, and (H) the image processor2when the operation that instructs the reduction from the high magnification to the same magnification is performed by (A) the operating portion5. In this case, the switching may be performed in the order reverse of a case where the enlargement instruction operation from the same magnification to the high magnification is performed. The processing inFIG. 2Bcorresponds to claims2and8.

During OV1, a set magnification in (H) the image processor2is switched from the high magnification to the same magnification.

During IV2, the access mode for the image memory1is switched from the first access mode to the second access mode via (E) the writing controller13.

During OV2(the first output vertical blanking period), the access mode for the image memory1is switched from the first access mode to the second access mode via (G) the reading controller23.

During IV3(the first input vertical blanking period immediately after the first output vertical blanking period), (D) the compression application switch12is switched from the compression route to the detour route via the writing controller13.

During OV3(the second output vertical blanking period immediately after the first input vertical blanking period), (F) the decompression application switch22is switched from the decompression route to the detour route via the reading controller23.

The switch processings of the access mode and the compression/decompression/detour route described above are performed to be able to eliminate or reduce the discontinuity or the disturbance of the image in reducing the image displayed on the display from the high magnification to the same magnification (in the switching where the lossy compression processing is not applied).

If there is a room for the processing capacity, the processing that is to be performed during IV2is also performed during IV3and the processing that is to be performed during OV3is also performed during IV3when OV3is outputted at the same time as IV3to be able to shorten the time required for the total of the switch processings.

FIG. 3illustrates a configuration of a part related to a processing of an image signal (an image data) of an image display apparatus that is Embodiment 2 of the present invention. The image display apparatus includes an image memory processor (a memory, a compressor, and a decompressor)30, an image processor2, a synchronization detector3, an output clock generator4, an operating portion5, and a switch timing controller (a controller)7. The image processor2, the synchronization detector3, the output clock generator4, and the operating part5are the same as those of Embodiment 1.

The image memory processor30, as indicated by a dashed line inFIG. 3, includes a compressor31, a compression application switch32, an image memory33, a decompressor34, a decompression application switch35, and an address controller36. The image memory processor30stores the input image data in the image memory33, and outputs the image data required from the image processor2. The compressor31, the compression application switch32, the image memory33, the decompressor34, and the decompression application switch35have the same functions as those of the compressor11, the compression application switch12, the image memory1, the decompressor21, and the decompression application switch22described in Embodiment 1, respectively.

The address controller36has a combined function of the writing controller13and the reading controller23described in Embodiment 1 to control the writing address (the writing mode) and the reading address (the reading mode) for the image memory33. Each of the writing mode and the reading mode, similarly to Embodiment 1, includes a first access mode and a second access mode. The switching of the first access mode and the second access mode is controlled by the switch timing controller7.

The switch timing controller7, regarding the input from the operating portion5as a trigger, instructs the selections (the switches) of the access mode of the image memory33and the routes of the compression application switch32and the decompression application switch35, and also performs the setting of the magnification of the reduction or enlargement for the image processor2.

Next, referring toFIGS. 4A and 4B, the timing (a control method) of performing the switches of the access mode and the compression/decompression/detour route by the switch timing controller7will be described. The switch timing controller7performs the following processing (step) in accordance with a computer program stored in an embedded memory.

FIG. 4Aillustrates operation timings of (D) the compression application switch32, (F) the decompression application switch35, (I) the address controller36, and (H) the image processor2when the operation of instructing the enlargement from the same magnification to the high magnification is performed by (A) the operating portion5. The processing ofFIG. 4Acorresponds to claims1and7.

Each operation timing needs to be performed during a vertical blanking period (an input vertical blanking period) of the input image signal inputted to the image memory processor30and a vertical blanking period (an output vertical blanking period) of the output image signal outputted from the image memory processor30. Also in the present embodiment, an interrupt by (B) the vertical synchronization signal outputted from the synchronization detector3is used as an indicator of an incoming timing of the input vertical blanking period. Moreover, an interrupt by (C) the vertical synchronization signal outputted from the output clock generator4is used as an indicator of an incoming timing of the output vertical blanking period.

After the enlargement instruction operation from the same magnification to the high magnification is performed by the operating portion5, (B) the vertical synchronization signal outputted from the synchronization detector3is sequentially defined as IV1, IV2, IV3, and the like, and (C) the vertical synchronization signal outputted from the output clock generator4is sequentially defined as OV1, OV2, OV3, and the like. OV1, OV2, and OV3are outputted next to (immediately after) IV1, IV2, and IV3, respectively. Instead of this, however, OV1, OV2, and OV3may be outputted at the same time as IV1, IV2, and IV3, respectively.

During IV1(the first input vertical blanking period), (D) the compression application switch32is switched from the detour route to the compression route.

During OV1(the first output vertical blanking period immediately after the first input vertical blanking period), (F) the decompression application switch35is switched from the detour route to the decompression route.

During OV2(the second output vertical blanking period immediately after the first output vertical blanking period), the access mode (the writing/reading mode) for the image memory33is switched from the second access mode to the first access mode via (I) the address controller36.

During OV3, the set magnification in (H) the image processor2is switched from the same magnification to the high magnification.

The processings of switching the access mode and the compression/decompression/detour route described above are performed to be able to eliminate or reduce the discontinuity or the disturbance of the image in enlarging the image displayed on the display from the same magnification to the high magnification.

If there is a room for the processing capacity, the processings that are to be performed during OV2and OV3are also performed during OV1to be able to shorten the time required for the total of the switch processings.

FIG. 4Billustrates operation timings of (D) the compression application switch32, (F) the decompression application switch35, (I) the address controller36, and (H) the image processor2when the operation that instructs the reduction from the high magnification to the same magnification is performed by (A) the operating portion5. In this case, the switching may be performed in the order reverse of a case where the enlargement instruction operation from the same magnification to the high magnification is performed. The processing inFIG. 4Bcorresponds to claims2and8.

During OV1, a set magnification in (H) the image processor2is switched from the high magnification to the same magnification.

During OV2(the first output vertical blanking period), the access mode (the writing/reading mode) for the image memory33is switched from the first access mode to the second access mode via (I) the address controller36.

During IV3(the first input vertical blanking period immediately after the first output vertical blanking period), (D) the compression application switch32is switched from the compression route to the detour route.

During OV3(the second output vertical blanking period immediately after the first input vertical blanking period), (F) the decompression application switch35is switched from the decompression route to the detour route.

The switch processings of the access mode and the compression/decompression/detour route described above are performed to be able to eliminate or reduce the discontinuity or the disturbance of the image in reducing the image displayed on the display from the high magnification to the same magnification.

If there is a room for the processing capacity and OV3is outputted at the same time as IV3, the processing that is to be performed during OV3is also performed during IV3to be able to shorten the time required for the total of the switch processings.

FIG. 5illustrates a configuration of a part related to a processing of an image signal (an image data) of an image display apparatus that is Embodiments 3 of the present invention. The image display apparatus includes an image memory processor40, an image processor2, a synchronization detector3, an output clock50, an operating portion5, and a switch timing controller8. The image processor2, the synchronization detector3, and the operating part5are the same as those of Embodiments 1 and 2.

The image memory processor40, as indicated by a dashed line inFIG. 5, includes a compressor41, a compression application switch42, an image memory43, a decompressor44, a decompression application switch45, a route controller46, and an address controller47. The image memory processor40is different from the image memory processor30of Embodiment 2 in that the route controller46is provided.

The route controller46switches the compression/decompression route in which the compression application switch42is set to the compression route and the decompression application switch45is set to the decompression route and the detour route in which both the compression application switch42and the decompression application switch45are set to the detour route. The switching of the route is controlled by the switch timing controller8.

The output clock50, as indicated by a dashed line inFIG. 5, includes an output clock generator51and a delay adjustor52. The output clock50outputs a pixel clock that operates the image memory43and each latter part of it, a horizontal synchronization signal, and a vertical synchronization signal that is capable of arbitrarily setting a phase with the same cycle as that of the inputted vertical synchronization signal.

The output clock generator51outputs a pixel clock that operates the image memory43and each latter part of it, a horizontal synchronization signal, and a vertical synchronization signal generated with the cycle and the phase specified by the delay adjustor52.

The delay adjustor52tunes the cycle of the vertical synchronization signal outputted from the output clock generator51to the cycle of the vertical synchronization signal outputted from the synchronization detector3, and sets the phase arbitrarily. As for the phase, an appropriate amount is specified so as not to generate a tearing (a phenomenon in which images of frames different between the top and the bottom of a certain line as a boundary are displayed) by the switch timing controller8. In the present embodiment, a normal delay mode in which a delay time having a sufficient margin is set and a low delay mode in which a delay time shorter than the normal delay mode (for example, the minimum delay time that can be set) can be specified.

The switch timing controller8, regarding the input from the operating portion5as a trigger, instructs the selection (the switch) of the access mode of the image memory1and the routes of the compression application switch42and the decompression application switch45, and also sets the magnification of the reduction or the enlargement to the image processor2.

Next, referring toFIGS. 6A and 6B, the timing (a control method) of performing the switches of the access mode and the compression and decompression/detour route by the switch timing controller8will be described. The switch timing controller8performs the following processing (step) in accordance with a computer program stored in an embedded memory.

FIG. 6Aillustrates operation timings of (J) the delay adjustor52, (D) the compression application switch42, (F) the decompression application switch45, (I) the address controller47, and (H) the image processor2when the operation of instructing the enlargement from the same magnification to the high magnification is performed by (A) the operating portion5. The processing ofFIG. 6Acorresponds to claims3,4, and9.

Each operation timing needs to be performed during a vertical blanking period (an input vertical blanking period) of the input image signal inputted to the image memory processor40and a vertical blanking period (an output vertical blanking period) of the output image signal outputted from the image memory processor40. Also in the present embodiment, an interrupt by (B) the vertical synchronization signal outputted from the synchronization detector3is used as an indicator of an incoming timing of the input vertical blanking period. Moreover, an interrupt by (C) the vertical synchronization signal outputted from the output clock generator51is used as an indicator of an incoming timing of the output vertical blanking period.

After the enlargement instruction operation from the same magnification to the high magnification is performed by the operating portion5, (B) the vertical synchronization signal outputted from the synchronization detector3is sequentially defined as IV1, IV2, IV3, IV4, and the like. Furthermore, (C) the vertical synchronization signal outputted from the output clock generator51is sequentially defined as OV1, OV2, OV3, OV4, and the like. OV1, OV2, OV3, and OV4are outputted next to (immediately after) IV1, IV2, IV3, and IV4, respectively. Instead of this, however, OV1, OV2, OV3, and OV4may be outputted at the same time as IV1, IV2, IV3, and IV4, respectively.

During IV1, (J) the delay adjustor52is switched from the normal delay mode to the low delay mode. The switch of the delay mode is promptly applied, and the delay time of immediate OV1with respect to IV1is shorter than each of delay times of OV2, OV3, and OV4other than OV1(other than the first output vertical blanking period) with respect to each of IV2, IV3, and IV4just prior to them. In other words, OV1comes after IV1faster than OV2, OV3, and OV4coming after IV2, IV3, and IV4just prior to them.

During OV1(the first output vertical blanking period), the route controller46is switched from the detour route to the compression and decompression route, and (D) the compression application switch42is switched from the detour route to the compression route, and (F) the decompression application switch45is switched from the detour route to the decompression route.

During IV2(the first input vertical blanking period), (J) the delay adjustor52is switched from the low delay mode to the normal delay mode. The switch of the delay mode is promptly applied, and immediate OV2comes after the normal delay time with respect to IV2.

During OV2(the second output vertical blanking period immediately after the first output/input vertical blanking period), the access mode (the writing/reading mode) for the image memory43is switched from the second access mode to the first access mode via (I) the address controller47.

During OV3, the set magnification in (H) the image processor2is switched from the same magnification to the high magnification.

The switch processings of the access mode and the compression and decompression/detour route described above are performed to be able to eliminate or reduce the discontinuity or the disturbance of the image in enlarging the image displayed on the display from the same magnification to the high magnification.

If OV1comes during the vertical blanking period of the input image signal in the low delay mode, the disturbance of the displayed image is not generated. Even when OV1is contained in an effective area of the input image signal, the disturbance of the displayed image can be suppressed.

If there is a room for the processing capacity, the processings that are to be performed during OV2and OV3are also performed during OV1to be able to shorten the time required for the total of the switch processings. The processing that is to be performed during OV1may also be performed during IV2.

FIG. 6Billustrates operation timings of (J) the delay adjustor52, (D) the compression application switch42, (F) the decompression application switch45, (I) the address controller47, and (H) the image processor2when the operation that instructs the reduction from the high magnification to the same magnification is performed by (A) the operating portion5. In this case, the switching may be performed in the order reverse of a case where the enlargement instruction operation from the same magnification to the high magnification is performed. The processing inFIG. 6Bcorresponds to claims5,6, and10.

During OV1, the set magnification in (H) the image processor2is switched from the high magnification to the same magnification.

During OV2(the first output vertical blanking period), the access mode for the image memory43(the writing/reading mode) is switched from the first access mode to the second access mode via (I) the address controller47.

During IV3, (J) the delay adjustor52is switched from the normal delay mode to the low delay mode. The switch of the delay mode is promptly applied, and the delay time of immediate OV3with respect to IV3is shorter than each of delay times of OV1, OV2, and OV4other than OV3(other than the second output vertical blanking period) with respect to each of IV1, IV2, and IV4just prior to them. In other words, OV3comes after IV3earlier than OV1, OV2, and OV4coming after IV1, IV2, and IV4just prior to them.

During OV3(the second output vertical blanking period immediately after the first output vertical blanking period), the route controller46is switched from the compression and decompression route to the detour route. As a result, (D) the compression application switch42is switched from the compression route to the detour route, and (F) the decompression application switch45is switched from the decompression route to the detour route.

During IV4(the first input vertical blanking period immediately after the second output vertical blanking period), (J) the delay adjustor52is switched from the low delay mode to the normal delay mode. The switch of the delay mode is promptly applied, and immediate OV4comes after the normal delay time with respect to IV4.

The switch processings of the access mode and the compression and decompression/detour route described above are performed to be able to eliminate or reduce the discontinuity or the disturbance of the image in reducing the image displayed on the display from the high magnification to the same magnification.

If OV3comes during the vertical blanking period of the input image signal in the low delay mode, the disturbance of the displayed image is not generated. Even when OV3is contained in an effective area of the input image signal, the disturbance of the displayed image can be suppressed.

If there is a room for the processing capacity, the processing that is to be performed during OV2are also performed during OV1to be able to shorten the time required for the total of the switch processings. The processing that is to be performed during OV3may also be performed during IV4.

For example, each embodiment describes the case where the image processor2performs a resolution conversion processing, but the image processor2may also perform a keystone correction processing since the similar restriction can be provided to the access mode in accordance with a value of a correction angle in the keystone correction processing.

This application claims the benefit of Japanese Patent Application No. 2010-068009, filed on Mar. 24, 2010, which is hereby incorporated by reference herein in its entirety.