Power conversion apparatus

A power conversion apparatus with an arm fuse melting detector for detecting an arm fuse melting from a ripple current without using a micro switch. The power conversion apparatus includes an inverter for driving a motor, an arm fuse provided in each of U-phase, V-phase, and W-phase arms of the inverter, and a first arm fuse melting detector to detect the arm fuse melting. The first arm fuse melting detector includes a DQ conversion circuit that converts the inverter output current into the D-axis/Q-axis current, an absolute value calculation circuit for calculating the absolute value from the output of the DQ conversion circuit, a ripple current calculator for calculating a ripple current from the difference between the maximum value and the minimum value of the absolute value for each cycle period T of the fundamental wave of the inverter output.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from the prior PCT Patent Application No. PCT/JP2017/26514, filed on Jul. 21, 2017, the entire contents of which are incorporated herein by reference.

TECHNICAL FIELD

The embodiment of this invention is related with a power conversion apparatus with an arm fuse melting detector.

BACKGROUND ART

Conventionally, actions of micro switch has been used to detect the melting of an arm fuse in a three-phase inverter constituting a power converter.

PRIOR ART DOCUMENT

Patent Document

Patent Document 1: Japanese Patent Application Publication No. 2007-202299

SUMMARY OF THE INVENTION

Problem to be Solved by the Invention

However, the micro switch applied to the detection of melting of the high-voltage fuse does not have an automatic return function, and there was a problem that the switch may cause a malfunction such as stopping the power converter due to false detection when the switch operates by vibration or the like.

The present invention has been made in order to solve the above-described problems, and without using a micro switch, power conversion apparatus is provided with an arm fuse melting detection means for detecting an arm fuse melting from a ripple current at the time of the arm fuse melting.

Means for Solving the Problem

In order to achieve the above object, a power conversion apparatus with an arm fuse melting detector according to claim1of the present invention comprises, an inverter that drives an AC motor in variable speed by receiving a power from power supply, an arm fuse provided in each phase arm of the U-phase arm, V-phase arm and W-phase arm constituting the inverter, a first arm fuse melting detector for detecting melting of each arm fuse, and the first arm fuse melting detector involves a current detector for detecting the three-phase output current of the inverter, a conversion circuit for converting three-phase current detected by the current detector into two-axis current components orthogonal to each other, a first absolute value calculator for calculating the absolute value from the output of the conversion circuit, a first ripple current calculator for calculating a ripple current from the difference between the maximum value and the minimum value of the absolute value calculated by the first absolute value calculator for each cycle period T of the fundamental wave of the inverter output, a first comparator that compares the ripple current calculated by the first ripple current calculator with a set first threshold value, a first threshold value determining circuit for determining the first threshold value by multiplying a current command value of the inverter by a predetermined first coefficient, wherein, the first comparator operates when the ripple current is equal to or greater than the first threshold, and is determined that the arm fuse is melted.

Effects of the Invention

According to the present embodiment, since it is possible to detect the arm fuse melting of the inverter without depending on the macro switch, it is possible to prevent the false detection of the arm fuse melting due to the malfunction of the micro switch, and a malfunction such as a stop operation of the power conversion apparatus can be prevented.

EMBODIMENT TO PRACTICE THE INVENTION

FIG. 1is a schematic configuration diagram of the power conversion apparatus100including the arm fuse melting detector and a power conversion system including a motor M connected to the power conversion apparatus100according to the first embodiment.

The illustrated power conversion apparatus100includes a converter1, an inverter2, a current detector3, a controller4, and an arm fuse melting detector5.

The converter1converts a three-phase AC power source R (R phase), S (S phase), and T (T phase) into a DC power source composed of a P phase (positive electrode) and an N phase (negative electrode), and supply the DC power to the inverter2.

The inverter2consists of a three-phase arm includes a U-phase arm (generic name for U-phase upper arm and U-phase lower arm), a V-phase arm (generic name for V-phase upper arm and V-phase lower arm), and a W-phase arm (generic name for W-phase upper arm and W-phase lower arm). It converts the DC power supplied from the converter1into the three-phase AC power (U phase, V phase, and W phase) required to drive the motor M.

In the U-phase upper arm, an arm fuse Fu1is connected between the P-phase and the collector of the switching element Qu1, and in the U-phase lower arm, an arm fuse Fu2is connected between the N-phase and the emitter of the switching element Qu2. The emitter of the switching element Qu1and the collector of the switching element Qu2are connected, and the connection point is connected to the U-phase AC input terminal of the motor M via the current detector3. Diodes Du1and Du2are connected in antiparallel to the switching elements Qu1and Qu2, respectively. The gates G of the switching elements Qu1and Qu2are connected to the controller4. The switching elements Qu1and Qu2perform a switching operation by the gate signal output from the controller4and output the U phase of the three-phase AC power supply (U phase output of the inverter).

In the V-phase upper arm, an arm fuse Fv1is connected between the P-phase and the collector of the switching element Qv1, and in the V-phase lower arm, an arm fuse Fv2is connected between the N-phase and the emitter of the switching element Qv2. The emitter of the switching element Qv1and the collector of the switching element Qv2are connected, and the connection point is connected to the V-phase AC input terminal of the motor M via the current detector3. Diodes Dv1and Dv2are connected in antiparallel to the switching elements Qv1and Qv2, respectively. The gates G of the switching elements Qv1and Qv2are connected to the controller4. The switching elements Qv1and Qv2perform a switching operation by the gate signal output from the controller4and output the V phase of the three-phase AC power supply (V phase output of the inverter).

In the W-phase upper arm, an arm fuse Fw1is connected between the P-phase and the collector of the switching element Qw1, and in the W-phase lower arm, an arm fuse Fw2is connected between the N-phase and the emitter of the switching element Qw2. The emitter of the switching element Qw1and the collector of the switching element Qw2are connected, and the connection point is connected to the W-phase AC input terminal of the motor M via the current detector3. Diodes Dw1and Dw2are connected in antiparallel to the switching elements Qw1and Qw2, respectively. The gates G of the switching elements Qw1and Qw2are connected to the controller4. The switching elements Qw1and Qw2perform a switching operation by the gate signal output from the controller4and output the W phase of the three-phase AC power supply (W phase output of the inverter).

The current detector3detects a U-phase output current Iu_F, a V-phase output current Iv_F, and a W-phase output current Iw_F of the inverter and outputs them to the arm fuse melting detector5.

The controller4converts a speed command from a host controller (not shown) into a two-axis value composed of D-axis current command value and a Q-axis current command value that are orthogonal to each other. The controller4uses an U-phase output current Iu_F, a V-phase output current Iv_F, and a W-phase output current Iw_F of the inverter from the current detector3, and these are converted to a D-axis current feedback value and a Q-axis current feedback value in the current command calculation circuit in the controller. These two axes are orthogonal to each other. The controller4outputs gate signal to the gate G of the switching elements Qu1, Qu2, Qv1, Qv2, Qw1and Qw2of the inverter2so that the D-axis current feedback value and the Q-axis current feedback value follow the D-axis current command value and the Q-axis current command value, respectively.

In this way, the motor M is driven in variable speed.

Since the controller4is a main controller to control the switching elements Qu1and Qu2that constitute the U-phase upper arm and lower arm, switching elements Qv1and Qv2that constitute the V-phase upper arm and lower arm, and the switching elements Qw1and Qw2constituting a W-phase upper arm and lower arm, these constitute the inverter2,FIG. 1illustrates the case where the controller4is not included in the inverter2, but the same effect can be obtained when the controller4is included in the inverter2. Either case is included in the scope of the present invention.

Moreover, although the converter1illustrated the case where it was not controlled by the gate signal output from the controller4, like the gate control of the inverter2, when the converter1is comprised with a switching element, it may be controlled by a gate output signal from the controller4. Either case is included in the scope of the present invention. Based on the above, the following explanation will be given.

The arm fuse melting detector5receives the U phase output current Iu_F, V phase output current Iv_F, and W phase output current Iw_F of the inverter output from the current detector3, and detects the melting of the arm fuse.

FIG. 2is a diagram showing input/output current waveforms before and after melting when the U-phase arm fuse is melted at time t1.FIG. 2(1) is an example of the waveforms of the three-phase alternating currents Ir, Is, and It inputted to the converter1from the three-phase alternating current power sources R, S, T.FIG. 2(2) is an example of a U-phase output current Iu_F, a V-phase output current Iv_F, and a W-phase output current Iw_F.FIG. 2(3) is an example of the waveform of the inverter output current I1_F. With reference to these drawings, the arm fuse melting detection method according to the present embodiment will be described.

FIG. 3is a block diagram showing a configuration of the arm fuse melting detector5shown inFIG. 1. The arm fuse melting detector5includes a first arm fuse melting detector50, a second arm fuse melting detector60, and a switching unit70and an arm fuse melting detection output unit80.FIG. 4AandFIG. 4Bare detailed view for explaining the operation of each part constituting the arm fuse melting detector5shown inFIG. 3. The first arm fuse melting detector50detects the melting of the arm fuse connected to each arm described above during normal load. The detection result is inputted to a terminal A of an AND513as a first detection result signal (1: arm fuse melted, 0: arm fuse not melted).

The switching unit70includes a comparator703. The comparator703compares an inverter output current I1_F, which will be described later, and that is a value inputted to the terminal A of the comparator703via a filter701, and a light load setting value set in advance by a setting circuit702inputted to the terminal B. Thus, it is determined whether the load is a normal load or a light load, and the determination result is outputted from the terminal C of the comparator703as a switching signal (1: normal load, 0: light load). The output switching signal is inputted to a terminal B of a logical product513.

An output signal of the logical product513is inputted to a signal processing circuit including an OFF-delay515and an ON-delay517.

The first arm fuse melting detection according to the present embodiment is determined as the first arm fuse melting in the following cases as will be described later.

That is, the absolute ripple current obtained by converting the three-phase output current of the inverter2into two-axis components orthogonal to each other exceeds a predetermined threshold value, and is selected by the switching signal, and these are continuously detected for a predetermined number of cycles (for example, 5 cycles) with a cycle period T described later as one cycle.
By using such an arm fuse melting detection method, it is possible to prevent erroneous detection. For this purpose, signal processing including the OFF-delay515and the ON-delay517is performed (details will be described later).
The output signal of the ON-delay517is inputted to a terminal A of a logical sum801of the arm fuse melting detection output unit80, and the arm fuse melting detection signal (INV_PH_LOSS) is outputted from the terminal C of the logical sum801.

The second arm fuse melting detector60detects the melting of the arm fuse connected to each arm described above at light load. The detection result is inputted to a terminal B of a logical product622as a detection result signal (1: arm fuse melted, 0: arm fuse not melted).

The switching unit70inverts a signal outputted from the terminal C of a comparator703as a switching signal (1: normal load, 0: light load) by an inversion circuit704and inputs the inverted signal to the terminal A of a logical product622.

The output signal of the logical product622is inputted to a signal processing circuit including an OFF-delay624and an ON-delay626.

The second arm fuse melting detection according to the present embodiment is determined as the second arm fuse melting in the following cases as will be described later. That is, the phase imbalance of the values obtained by integrating the three-phase output current of the inverter unit2for each half cycle exceeds a predetermined threshold, and it is selected by the switching signal, and these are continuously detected for a predetermined number of cycles (for example, 5 cycles) with a cycle period T described later as one cycle. By using such an arm fuse melting detection method, it is possible to prevent erroneous detection. For this purpose, signal processing including the OFF-delay624and the ON delay-626is performed (details will be described later).

The output signal of the ON-delay626is inputted to the terminal B of the logical sum801of the arm fuse melting detection output unit80, and the arm fuse melting detection signal (INV_PH_LOSS) is outputted from the terminal C of the logical sum801.

When the arm fuse melting detection signal (INV_PH_LOSS) is outputted from the terminal C of the logical sum801, appropriate protection interlock is performed by a protection circuit (not shown).

FIG. 5is a diagram for explaining the maximum value and the minimum value in the cycle period T of the inverter output current.

The first arm fuse melting detector50detects a melting of the arm fuse connected to each arm at the time of normal load, and it includes a phase detection circuit501, a reset signal generation circuit502, a DQ conversion circuit503, an absolute value calculation circuit504, a maximum value holding circuit506, a minimum value holding circuit508, a comparator512, a logical product513, an OFF-delay515, an ON-delay517, and the like.

The phase detection circuit501is a circuit that detects the electrical angle phase θ of the output of the inverter2. It is possible to use an output of a phase synchronization circuit (PLL) used in a speed estimation circuit that uses the input terminal voltage of the motor M and the U-phase output current Iu_F, V-phase output current Iv_F, or W-phase output current Iw_F of the inverter unit2described above for detecting the electrical angle phase θ in the phase detection circuit501. Or it may be detected using a signal from a rotation angle detector or a position sensor mechanically attached to the motor M.

The phase detection circuit501outputs the cycle period T, which is the period of the fundamental wave of the output voltage or output current of the inverter unit2, and the phase signal θ by the method described above.

The phase signal θ is inputted to the reset signal generation circuit502and the DQ conversion circuit503.

The reset signal generation circuit502outputs a reset signal once per cycle of the fundamental wave of the output voltage of the inverter unit2from the phase signal θ, and It is connected to the reset signal input terminal of each of the maximum value holding circuit506, the minimum value holding circuit508, a positive side U-phase integral value calculation circuit601, a positive side V-phase integral value calculation circuit602, a positive side W-phase integral value calculation circuit603, a negative side U-phase integral value calculation circuit604, a negative side V-phase integral value calculation circuit605, and a negative side W-phase integral value calculation circuit606, these will be described later.

The DQ conversion circuit503(conversion circuit) uses the phase signal θ as a reference signal, and converts a three-phase current composed of the input U-phase output current Iu_F, V-phase output current Iv_F, and W-phase output current Iw_F of the inverter unit2into a biaxial vector current composed of a D-axis and a Q-axis orthogonal to each other, and generates D-axis current ID_FBK and a Q-axis current IQ_FBK.

The absolute value calculation circuit504(first absolute value calculation circuit) calculates an absolute value current I1_F from the D-axis current ID_FBK and the Q-axis current IQ_FBK generated by the DQ conversion circuit503. Since the absolute value current I1_F is an inverter output current (load current) outputted from the inverter2, it may be hereinafter referred to as an inverter output current. The inverter output current I1_F is calculated by the following equation (1).
I1_F=√{square root over ((ID_FBK)2+(IQ_FBK)2)}  (1)
The inverter output current I1_F is inputted to an A input terminal of the maximum value holding circuit506, an A input terminal of the minimum value holding circuit508, and an input terminal of the filter2.

The maximum value holding circuit506detects and holds a large inverter output current I_F when the inverter output current I1_F calculated by the absolute value calculation circuit504is larger than the current value set by a setting circuit505as the initial value 1. At the same time, the inverter output current I1_F is set as a new initial value. With this setting, the initial value is updated. When the inverter output current I1_F is larger than the updated initial value, the large inverter output current I1_F is detected and held, and the inverter output current I1_F is set as a new initial value. By repeating this process, the maximum value I1_Fmax of the inverter output current is detected and held (seeFIG. 5). The held maximum value I1_Fmax of the inverter output current is reset to the initial value 1 set by the setting circuit505, by the reset signal outputted from the reset signal generation circuit502every cycle period T.

The minimum value holding circuit508detects and holds the small inverter output current I1_F when the inverter output current I1_F calculated by the absolute value calculation circuit504is smaller than the current value set by a setting circuit507as the initial value 2. At the same time, the inverter output current I1_F is set as a new initial value. With this setting, the initial value is updated. When the inverter output current I1_F is smaller than the updated initial value, the small inverter output current I1_F is detected and held, and the inverter output current I1_F is set as a new initial value. By repeating this process, the minimum value I1_Fmin of the inverter output current is detected and held (seeFIG. 5). The held minimum value I1_Fmin of the inverter output current is reset to the initial value 2 set by the setting circuit507, by the reset signal outputted from the reset signal generation circuit502every cycle period T.

A subtraction circuit509calculates a difference obtained by subtracting the minimum value I1_Fmin of the inverter output current outputted from the minimum value holding circuit508from the maximum value I1_Fmax of the inverter output current outputted from the maximum value holding circuit506. Then a ripple current I1_Frpl at normal load is calculated (seeFIG. 5; first ripple current calculator). The difference obtained by subtracting the minimum value I1_Fmin from the maximum value I1_Fmax of the inverter output current indicates the ripple current I1_Frpl at the normal load, and as is apparent fromFIG. 2(3), the normal load ripple current I1_Frpl at the time shows a small value before the time t1when the arm fuse melted, but shows a large value after the time t1when the arm fuse melted. The calculated ripple current I1_Frpl at the normal load is inputted to a terminal A of the comparator512.

The comparator512(first comparator) compares whether the ripple current at the normal load inputted to a terminal A exceeds the threshold value (first threshold value) inputted to a terminal B. The threshold value is set by the following method.

The absolute value calculation circuit619calculates the absolute value of the current command value I_R (hereinafter referred to as the current command value) from the D-axis current command value ID_R and the Q-axis current command value ID_Q of the inverter output current converted into two-axis components orthogonal to each other by an inverter output current control circuit (not shown). The current command value I_R is calculated by a following equation (2).
I_R=√{square root over ((ID_R)2+(IQ_R)2)}  (2)
InFIG. 4, the absolute value calculation circuit619is shown in the second arm fuse melting detector60, however, since the output of the absolute value detection circuit619is also used by the first arm fuse melting detector50, the absolute value detection circuit619may be provided in the first arm fuse melting detector50. Alternatively, it may be provided in an inverter output current control circuit unit (not shown).

The current command value I_R is smoothed by a filter510, further multiplied by a proportional gain K1by a proportional circuit511, and inputted to the B terminal of the comparator512as a threshold value. That is, the threshold value of the comparator512is set to a value proportional to the current command value I_R. The filter510is a first-order lag element, and is used for the purpose of removing high-frequency noise.

The result of the comparison is inputted to a terminal A of the logical product513. A switching signal that is the output of the comparator703described inFIG. 3is inputted to a terminal B of the logical product513.

During normal load, the switching signal that is the output of the comparator703is 1 (High Level).

Therefore, when the arm fuse melting is detected, 1 (High Level) is outputted from the comparator512, and 1 (High Level) is also outputted from the logical product513.

The output signal of the logical product513is inputted to a signal processing circuit including an OFF-delay515and an ON-delay517.

The cycle period T of the fundamental wave of the inverter output outputted from the phase detection circuit501is inputted as a set value of the OFF-delay time of the OFF-delay515by multiplying a gain K2by a proportional circuit514. The OFF-delay515delays the OFF timing of the input signal for a period set by the output of the proportional circuit514. In the case of this embodiment, even when the arm fuse is melted, the output of the comparator512may be chattered during the fundamental wave cycle, so that the OFF-delay515generates a continuous signal. The value of the gain K2is set to about 1.2, for example. With this setting, the output signal becomes a continuous signal even if the input of the OFF-delay515is chattered during the fundamental wave cycle.

Further, the cycle period T of the fundamental wave of the inverter output outputted from the phase detection circuit501is inputted as a set value of the ON-delay time of the ON-delay517by multiplying a gain N1by a proportional circuit516.

The ON-delay517sets the output to 1 (High Level) when the input signal continues for the time set by the output of the proportional circuit516or more.

From a viewpoint of preventing unnecessary operation, it is desirable to detect an occurrence of the arm fuse melting when the ripple current I1_Frpl exceeds the threshold continuously for several cycles (first cycle) at the fundamental wave cycle period T, so the value to be used is a value corresponding to several cycles. For example, in the case of 5 cycles, the set gain N1of the proportional circuit516is set to 5. As a result, the ON-delay setting value becomes five times the cycle period T, and the ON-delay517sets the output to 1 (High Level) when the ripple current I1_Frpl exceeds the threshold value for five consecutive cycles.

This setting detects the occurrence of arm fuse melting when the ripple current at the normal load exceeding the predetermined threshold continues for the number of cycles. The output of this ON delay-517becomes the output of the first arm fuse melting detector50. InFIG. 4, the detection when the ripple current I1_Frpl exceeds the threshold value for several consecutive cycles at the fundamental wave period T is configured by the combination of the OFF-delay515and the ON-delay517, but the same function may be configured by combining the counter circuit.

The output signal of the ON delay-517is inputted to a terminal A of the logical sum801of the arm fuse melting detection output unit80, and the arm fuse melting detection signal (INV_PH_LOSS) is outputted from the terminal C of the logical sum801.

When an arm fuse melting detection signal (INV_PH_LOSS) is outputted from a terminal C of the logical sum801, appropriate protection interlock is performed by a protection circuit (not shown).

The second arm fuse melting detector60detects the melting of the arm fuse connected to each arm at the time of light load, and it includes the positive U phase integral value calculation circuit601, the positive V phase integral value calculation circuit602, the positive-side W-phase integral value calculation circuit603, the negative-side U-phase integral value calculation circuit604, the negative-side V-phase integral value calculation circuit605, the negative-side W-phase integral value calculation circuit606, subtraction circuits607,610,613,616, absolute value calculation circuits619,608,611,614,617, comparators609,612,615,618, a logical sum627, a logical product622, an OFF-delay624, an ON-delay626, and the like.

Before the arm fuse is melted, the U-phase output current Iu_F and the V-phase output current Iv_F are out of phase as shown before time t1inFIG. 2(2), since the values integrated over the cycle period T show substantially the same current value, the difference between the integrated values, that is, the unbalance, becomes a small value.

On the other hand, when the U-phase arm fuse is melted as shown after time t1inFIG. 2(2), the U-phase output current Iu_F is affected by the U-phase arm fuse melting after the arm fuse is melted. It fluctuates greatly compared to before the fuse is melted, the current component in the positive direction is small, and the current component in the negative direction is reduced. In addition to the U-phase output current Iu_F, the V-phase output current Iv_F and the W-phase output current Iw_F are also affected by the U-phase arm fuse melting, and fluctuate greatly compared to before the arm fuse melting.

Therefore, when the arm fuse is melted, the current value of each phase for one cycle is integrated in the forward or reverse unit, and compared with the integrated value of the current value in the same direction of the other phase, and when the difference (the unbalance) is large at this comparison, it can be determined that the arm fuse has melted.

An arm fuse melting detection circuit will be described by means for detecting current phase imbalance based on the above principle.

The U-phase output current Iu_F of the inverter is inputted to the positive side U-phase integral value calculation circuit601, and integration thereof is performed by an integration circuit601bvia a limiter circuit601ahaving a lower limit value of 0. The integral value calculated by the integration circuit601bis cleared by a reset signal output from the reset signal generating circuit502every cycle period T, and the initial value is set to zero. In this way, the integral value of the current in the positive direction during the cycle period T (one cycle) of the U-phase output of the inverter is calculated. This value is called a positive side U-phase integral value. The output of the integration circuit601bis the output of the positive side U-phase integration value calculation circuit601. The positive side U-phase integral value outputted from the positive side U-phase integral value calculation circuit601is outputted to a plus side terminal of the subtraction circuit607.

Similarly to the calculation method of the positive side U-phase integral value, the positive side V-phase integral value calculation circuit602calculates the integral value of the positive side current of the inverter V-phase output current Iv_F in the cycle period T. This value is called a positive side V-phase integral value. The calculated positive side V-phase integral value is outputted to the minus side terminals of the subtraction circuits607and610.

Further, similarly, the positive-side W-phase integral value calculation circuit603calculates the integral value of the positive-side current of the inverter W-phase output current Iw_F in the cycle period T. This value is called the positive side W-phase integral value. The calculated positive side W-phase integral value is outputted to the plus side terminal of the subtraction circuit610.

The U-phase output current Iu_F of the inverter is inputted to the negative-side U-phase integral value calculation circuit604, and integration thereof is performed by an integration circuit604bvia a limiter circuit604ahaving an upper limit value of 0. The integral value calculated by the integration circuit604bis cleared by a reset signal output every cycle period T from the reset signal502, and the initial value is set to zero. In this way, the integral value of the current in the negative direction during the cycle period T (one cycle) of the U-phase output of the inverter is calculated. This value is called a negative side U-phase integral value. The output of the integration circuit604bis the output of the negative side U-phase integration value calculation circuit604. The positive side U-phase integral value outputted from the negative side U-phase integral value calculation circuit604is outputted to the plus side terminal of the subtraction circuit613.

Similarly to the negative side U-phase integral value calculation method, the negative side V-phase integral value calculation circuit605calculates the integral value of the negative side current of the inverter V-phase output current Iv_F in the cycle period T. This value is called a negative side V-phase integral value. The calculated negative V-phase integral value is outputted to the minus side terminals of the subtraction circuits613and616.

Further, similarly, the negative side W-phase integral value calculation circuit606calculates the integral value of the negative side current of the W phase output current Iw_F of the inverter in the cycle period T. This value is referred to as a negative side W-phase integral value. The calculated negative side W-phase integral value is outputted to the plus side terminal of the subtraction circuit616.

The subtraction circuit607calculates a difference between the positive side U-phase integration value and the positive side V-phase integration value, and outputs the difference to the absolute value calculation circuit609. Since in the absolute value calculation circuit608, the positive side U-phase integral value and the positive side V-phase integral value are both positive values, but the subtraction result by the subtraction circuit607can take positive and negative values. The absolute value of the difference between the positive-side U-phase integral value and the positive-side V-phase integral value is calculated and outputted.

A comparator609compares whether the output of the absolute value calculation circuit608inputted to the terminal A (ripple current at light load) is equal to or higher than a threshold inputted to the terminal B. The comparison result is outputted from terminal C of the comparator609and inputted to a terminal A of the logical sum627.

The threshold is set by the following method. The current command value I_R outputted from the absolute value calculation circuit619is smoothed by a filter620, further multiplied by a proportional gain K3by a proportional circuit621, and inputted as a threshold value to the B terminal of the comparator609(second threshold value decision means). That is, the threshold value of the comparator609is set to a value proportional to the current command value I_R.

The filter620is a first-order lag element and is used for the purpose of removing high-frequency noise.

Since the frequency used is different between the first arm fuse melting part50used at normal load and the second arm fuse melting part60used at light load, an optimum time constant according to the load is preferably selected.

The comparator609(second comparator) outputs1(High Level) when the A terminal input (that is an output of the absolute value calculation circuit608) is equal to or higher than the B terminal input (second threshold) that is the output of the proportional circuit621.

In this way, the arm fuse melting detection result based on the difference between the positive side U-phase integral value and the positive side V-phase integral value is inputted to a terminal A of a logical sum627.

A subtraction circuit610calculates the difference between the positive W-phase integral value and the positive V-phase integral value. The absolute value of the difference of the subtraction circuit610is calculated by an absolute value calculation circuit611(second current imbalance calculation means) and inputted to the terminal A of the comparator612(third comparator). The signal is inputted from the terminal A of the comparator612to the terminal B of the logical sum627. Since the operations of the absolute value calculation circuit611and the comparator612are the same as the operations of the absolute value calculation circuit608and the comparator609described above, description thereof is omitted.

Similarly to the calculation method of the negative side U-phase integral value, a negative side V-phase integral value calculation circuit605calculate the integral value of the negative side (negative side not exceeding the upper limit limiter) current of the inverter V-phase output current Iv_F in a cycle period T. The calculated positive side V-phase integral value is outputted to the minus side terminals of the subtraction circuits613and616.

The subtraction circuit613calculates the difference between the negative side U-phase integral value and the negative side V-phase integral value. The absolute value of the difference of the subtraction circuit613is calculated by an absolute value calculation circuit614(third current imbalance calculator) and inputted to the terminal A of a comparator615(fourth comparator). The signal is inputted from the terminal C of the comparator615to a terminal C of the logical sum627.

The subtraction circuit616calculates the difference between the negative W-phase integral value and the negative V-phase integral value. The absolute value of the difference of the subtraction circuit616is calculated by an absolute value calculation circuit617(fourth current imbalance calculator) and inputted to a terminal A of a comparator618(fifth comparator). The signal is inputted from the terminal C of the comparator618to the terminal D of the logical sum627. Since the operations of the absolute value calculation circuit617and the comparator618are the same as the operations of the absolute value calculation circuit608and the comparator609described above, description thereof is omitted.

In addition, not only the combination of each phase integration value mentioned above, but from the difference of at least any two of the positive side U-phase integration value, the V-phase integration value, and the W-phase integration value, and also any two of the negative U-phase integration value, the negative-side V-phase integral value, and the negative-side W-phase integral value, the unbalance between the currents can be calculated. (First to fourth current imbalance calculator.) The switching signal (1: normal load, 0: light load) described inFIG. 3is inverted and input to a terminal A of a logical product622by an inverting circuit704. When detecting the arm fuse melted at light load, 0 (Low Level) is outputted from the comparator703(sixth comparator) as a switching signal, but is inverted by the inverting circuit704and inputted to the terminal A of the logical product622.

The output signal of the logical product622is inputted to the OFF-delay624, and the output is further inputted to the ON-delay626.

The cycle period T of the fundamental wave of the inverter output outputted from the phase detection circuit501is inputted as a set value of the OFF-delay time of the OFF-delay624by multiplying a gain K4by a proportional circuit623. Further, the cycle period T of the fundamental wave of the inverter output outputted from the phase detection circuit501is inputted as a set value of the ON-delay time of the ON-delay626by multiplying a gain N2by a proportional circuit625.

The setting of the gain K2is set so that the output of the logical product622becomes a continuous signal when the arm fuse is melted even when a direct output of the logical product622is chattering signal within the period of T1, in the same manner as setting of the gain K1described above. The gain N2is set so that the ON-delay626outputs an arm fuse melting signal when the signal continues for several cycles (second cycle) as setting of the gain N1.

Since the operations of the OFF-delay624and the ON-delay626are the same as the operations of the above-described OFF-delay515and the ON-delay517, description thereof will be omitted.

The output signal of the ON-delay626is inputted to the terminal B of the logical sum801of the arm fuse melting detection output unit80, and the arm fuse melting detection signal (INV_PH_LOSS) is outputted from the terminal C of the logical sum801.

When an arm fuse melting detection signal (INV_PH_LOSS) is outputted from the terminal C of the logical sum801, appropriate protection interlock is performed by a protection circuit (not shown).

As described above, according to the embodiment, it is possible to reliably detect the melting of the arm fuse during both normal load and light load.

As described above, according to the embodiment of the present invention, the arm fuse melting can be detected from the output current of the power conversion apparatus without using the micro switch. It is possible to provide a power conversion apparatus including an arm fuse melting detector that can prevent malfunctions such as stopping the operation.

For example, a power conversion apparatus using only the first arm fuse melting detector50is also effective. In this case, the detection accuracy is reduced when the load is light, but there is no problem as long as the operation region is only a normal load. Conversely, a power conversion apparatus using only the second arm fuse melting detector60is also effective. In this case, although the detection accuracy decreases as the load increases, there is a possibility that even when normal load, arm fuse melting can be detected by optimizing control constants of the detector.

DESCRIPTION OF THE SYMBOLS

1Converter2Inverter3Current detector4Controller5Arm fuse melting detector50First arm fuse melting detector501Phase detection circuit502Reset signal generation circuit503DQ conversion circuit504Absolute value calculation circuit506Maximum value holding circuit508Minimum value holding circuit509Subtraction circuit512Comparator160Second arm fuse melting detector601Positive side U-phase integral value calculation circuit602Positive side V-phase integral value calculation circuit603Positive side W-phase integral value calculation circuit604Negative side U phase integral value calculation circuit605negative side V-phase integral value calculation circuit606Negative side W-phase integral value calculation circuit608,611,614,617,619Absolute value calculation circuit609,612,615,618comparator70switching part703Comparator