TFT and reliability evaluation method thereof

In a method of evaluating the reliability of a thin film transistor (TFT), time coefficient .beta., voltage coefficient d and temperature coefficient .phi..sub.0 are experimentally produced from -BT stress tests, and the life of a TFT under -BT stress conditions is evaluated using the following expression: ##EQU1## where .tau. represents the life time of the TFT, .DELTA.V.sub.th.tau. the tolerant threshold voltage shift amount of the TFT, t.sub.0 (1/.DELTA.V.sub.th0) constant, q elementary electric charge, k Boltzmann constant, T temperature, V.sub.0 gate voltage, and t.sub.0X the thickness of the gate oxide film.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The present invention relates generally to thin film transistors (TFT) and 
methods of evaluating reliability thereof, and more specifically, to a TFT 
including a channel layer of a silicon thin film and a gate insulating 
film of a silicon oxide film, and a method of evaluating reliability 
thereof. 
2. Description of the Background Art 
TFTs are used for load transistors in the memory cells of a static random 
access memory (SRAM) or driver transistors for liquid crystal television 
pixels. When such products incorporated with TFTs are marketed, the 
reliability of TFTs should be evaluated. 
In FIG. 22, a typical top gate type P channel TFT is illustrated in a 
schematic cross section. In the TFT, an insulating film 2a is formed on a 
substrate 1. A polysilicon film 3 is formed on insulating film 2a. 
Polysilicon film 3 may be replaced with a monocrystalline silicon film or 
an amorphous silicon film. Source/drain regions 4 and a channel region 5 
are included in polysilicon layer 3. A gate electrode 7 is formed on 
polysilicon layer 3 with a gate insulating film 6 of a silicon oxide film 
therebetween. Polysilicon layer 3 and gate electrode 7 are covered with a 
silicon oxide film 2b. An aluminum interconnection 8 is connected to each 
of source/drain regions 4 through a contact hole provided in silicon oxide 
film 2b. More specifically, the TFT in FIG. 22 is an MOS (Metal Oxide 
Semiconductor) type FET (Field Effect Transistor) with polysilicon layer 3 
serving as an active region. 
For reliability evaluation tests for the TFT as illustrated in FIG. 22, a 
hot carrier stress test, a breakdown voltage test for gate insulating film 
6 or the like have been conducted. 
FIG. 23 sets forth one example of a bias condition in such a hot carrier 
stress test. In this example, source voltage V.sub.S applied to source S 
is 0V, gate voltage V.sub.G applied to gate G is -7V, drain voltage 
V.sub.D applied to drain D is -7V, and current continues to be passed 
between source S and drain D for a long period of time. It has been 
established that if polysilicon film 3 is sufficiently hydrogenated, the 
electrical characteristic of the TFT hardly changes before and after such 
a hot carrier stress test (see International Reliability Physics Society 
Proceedings, 1992, pp. 63-67). 
In FIG. 24, one example of a breakdown voltage evaluation test for a gate 
insulating film in a TFT is illustrated. In this example, for V.sub.S 
=V.sub.D =0V, gate voltage V.sub.G is gradually changed from 0V toward 
negative voltage. At the time, the gate voltage V.sub.G at which gate 
insulating film 6 is broken down is called gate breakdown voltage. When a 
silicon oxide film as thick as 250 .ANG. is used for a gate insulating 
film, the gate breakdown voltage is about 25V. For a power supply voltage 
of 5V a gate breakdown voltage of 25V would be enough. The insulation 
breakdown voltage of a silicon oxide film is generally about 10 MV/cm 
expressed in electric field, and a breakdown voltage for a gate insulating 
film having an arbitrary thickness can be estimated from the value of the 
electric field. 
It has been known that in a bulk silicon monocrystalline MOSFET the 
characteristic of the bulk MOSFET slightly degrades by a -BT (negative 
bias temperature) stress test by which the gate is supplied with constant 
voltage V.sub.G and maintained at an elevated constant temperature T. 
The influence of -BT stress however is not exactly known. TFTs are 
therefore incorporated in SRAMs and the like and marketed without 
reliability evaluation by -BT stress tests. 
SUMMARY OF THE INVENTION 
It is therefore an object of the invention to ascertain the influence of 
-BT stress upon a TFT and establish a method of evaluating reliability 
concerning the degradation of the characteristic of a TFT due to -BT 
stress. 
Another object of the invention is to provide a TFT satisfying reliability 
required in a -BT stress state based on thus established method of 
evaluating the reliability of a TFT due to -BT stress. 
A method of evaluating the reliability of a TFT according to a first aspect 
of the invention, in a TFT having a channel layer of a silicon thin film 
and a gate insulating film of a silicon oxide film, evaluates the 
reliability of the TFT in the -BT stress state in which the gate is 
supplied with an arbitrary negative constant voltage V.sub.G and 
maintained at an arbitrary constant temperature T based on the following 
expressions: 
EQU .DELTA.V.sub.th .varies.t.sup..alpha. (3a) 
##EQU2## 
where .DELTA.V.sub.th represents the threshold voltage shift amount of the 
TFT, t time, .alpha. time coefficient, q elementary electric charge, d 
voltage coefficient, k Boltzmann constant, t.sub.0X the thickness of the 
gate oxide film, .phi..sub.0 temperature coefficient, and 
.DELTA.V.sub.th.tau. tolerant threshold voltage shift amount for the TFT, 
and .beta.=1/.alpha.. The method includes a step of determining time 
coefficient .alpha. in expression (3a) based on the relation between 
threshold voltage shift amount .DELTA.V.sub.th obtained from at least one 
-BT stress test and time t, a step of determining voltage coefficient d in 
expression (4) based on the relation between threshold voltage shift 
amounts .DELTA.Vth obtained from at least two -BT stress tests and applied 
different gate voltages V.sub.G, a step of determining temperature 
coefficient .phi..sub.0 in expression (5a) based on the relation between 
threshold voltage shift amounts .DELTA.V.sub.th obtained from at least two 
-BT stress tests and applied different temperatures T, and a step of 
determining a constant of proportion given as follows using the determined 
time coefficient .alpha., voltage coefficient d, and temperature 
coefficient .phi..sub.0 determined in expression (6) obtained from the 
relation between expression (3a), (4a), and (5a), 
##EQU3## 
and is characterized in that the life of a TFT is produced from expression 
(8) obtained by modifying expression (6) from the determined constant 
proportion c.sub.2 and tolerant threshold voltage shift amount 
.DELTA.V.sub.th.tau.. 
A method of evaluating the reliability of a TFT according to a second 
aspect of the invention, in a TFT having a channel layer of a silicon thin 
film and a gate insulating film of a silicon oxide film, evaluates the 
reliability of the TFT in the -BT stress state in which the gate is 
supplied with an arbitrary constant voltage V.sub.G and held at a 
predetermined constant temperature T based on the following expressions: 
EQU .DELTA.V.sub.th .varies.t.sup..alpha. (3a) 
##EQU4## 
where .DELTA.V.sub.th represents the threshold voltage shift amount of the 
TFT, t time, .alpha. time coefficient, q elementary electric charge, k 
Boltzmann constant, t.sub.0X the thickness of the gate oxide film, 
.phi..sub.0 temperature coefficient, and .DELTA.V.sub.th.tau. tolerant 
threshold voltage shift amount for the TFT, and .beta.=1/.alpha.. The 
method includes a step of determining time coefficient .alpha. in 
expression (3a) based on the relation between threshold voltage shift 
amount .DELTA.V.sub.th obtained from at least one -BT stress test and time 
t, 
a step determining a constant of proportion given as follows using the 
determined time coefficient .alpha. and voltage coefficient d in 
expression (6b) obtained from the relation between expressions (3a) and 
(4a), 
##EQU5## 
and the method is characterized in that the life of the TFT is produced 
from expression (8b) obtained by modifying expression (6b) from the 
determined constant of proportion c.sub.2 and tolerant threshold voltage 
shift amount .DELTA.V.sub.th.tau. for the TFT. 
A method of evaluating the reliability of a TFT according to a third aspect 
of the invention in a TFT having a channel layer of a silicon thin film 
and a gate insulating film of a silicon oxide film evaluates the 
reliability of the TFT in the -BT stress state in which the gate is 
supplied with a predetermined negative constant voltage V.sub.G and 
maintained at an arbitrary constant temperature T using the following 
expressions: 
EQU .DELTA.V.sub.th .varies.t.sup..alpha. (3a) 
##EQU6## 
where .DELTA.V.sub.th represents a threshold voltage shift amount for the 
TFT, t time, .alpha. time coefficient, k Boltzmann constant, .phi..sub.E 
temperature coefficient, and .DELTA.V.sub.th.tau. tolerant threshold 
voltage shift amount for the TFT, and .beta.=1/.alpha.. The method 
includes a step of determining time coefficient .alpha. in expression (3a) 
based on the relation between threshold voltage shift amount 
.DELTA.V.sub.th obtained from at least one -BT stress test and time t, a 
step of determining temperature coefficient .phi..sub.E in expression (5b) 
based on the relation between threshold voltage shift amounts 
.DELTA.V.sub.th obtained from at least two -BT stress tests and applied 
different temperatures T, and a step of determining a constant of 
proportion given as follows using the determined time coefficient .alpha. 
and temperature coefficient .phi..sub.E in expression (6c) obtained from 
the relation between expressions (3a) and (5b), 
##EQU7## 
and the method is characterized in that the life of the TFT is produced 
from expression (8c) obtained by modifying expression (6c) from the 
determined constant of proportion c.sub.2 and tolerant threshold voltage 
shift amount .phi.V.sub.th.tau. for the TFT. 
A TFT according to a fourth aspect of the invention is used for an SRAM 
memory cell, includes a channel layer of a silicon thin film and a gate 
insulating film of a silicon oxide film, and is characterized in that the 
threshold voltage is shifted in advance toward positive voltage by the 
amount by which the threshold voltage is expected to shift toward negative 
voltage by a burn-in test. 
A TFT according to a fifth aspect of the invention is operated by gate 
voltage V.sub.G and used under the condition that the temperature at the 
time of operation is an absolute temperature T and includes a channel 
layer of a silicon thin film, and a gate insulating film of a silicon 
oxide film. The gate insulating film has a thickness of t.sub.0X 
=qd.vertline.V.sub.G .vertline./2kT, wherein t.sub.0X represents the 
thickness of the gate insulating film, q elementary electric charge, d 
voltage coefficient, and k Boltzmann constant, and voltage coefficient d 
is determined using the following expression (4a) based on the relation 
between threshold voltage shift amounts .DELTA.V.sub.th obtained from at 
least two -BT stress tests and applied different gate voltages V.sub.G, 
##EQU8## 
where q represents elementary electric charge, k Boltzmann constant, and 
t.sub.0X the thickness of the gate insulating film. 
In the method of evaluating the reliability of a TFT according to the first 
aspect of the invention, since life expected for the TFT is evaluated from 
expression (8) using time coefficient .alpha., voltage coefficient d and 
temperature coefficient .phi..sub.0 determined from -BT stress tests and 
expressions (3a), (4a), and (5a) the life expected for the TFT used with 
an arbitrary constant gate voltage V.sub.G at an arbitrary constant 
temperature T can readily and accurately be evaluated. 
In the method of evaluating the reliability of a TFT according to the 
second aspect of the invention, since the TFT is limited for use at a 
predetermined constant temperature, life expected for the TFT can be 
evaluated without requiring at least two -BT stress tests at different 
temperatures T. 
In the method of evaluating the reliability of a TFT according to the third 
aspect of the invention, since the TFT is limited for use at a 
predetermined constant gate voltage V.sub.G, life expected for the TFT can 
be evaluated without requiring at least two -BT stress tests at different 
gate voltages V.sub.G. 
In the TFT according to the fourth aspect of the invention, since the 
threshold voltage is previously shifted toward the side of positive 
voltage by the amount of shift of the threshold voltage toward the side of 
negative voltage due to a burn-in test, a TFT for SRAM having an optimum 
characteristic can be provided after the burn-in test. 
In the TFT according to the fifth aspect of the invention, since the gate 
insulating film has the thickness of T.sub.0X =qd.vertline.V.sub.G 
.vertline./2kT, a TFT having a maximum life in a -BT stress state at 
arbitrary constant gate voltage V.sub.G and at an arbitrary constant 
temperature T can be provided. 
The foregoing and other objects, features, aspects and advantages of the 
present invention will become more apparent from the following detailed 
description of the present invention when taken in conjunction with the 
accompanying drawings.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
The inventors have found for the first time that the degradation of the 
electric characteristic due to -BT stress causes a problem in a TFT. The 
-BT stress state is the state in which the gate of a TFT is supplied with 
a negative bias voltage and held at a relatively high temperature. 
In FIG. 1, one example of such a -BT stress state is illustrated. In this 
example, for V.sub.S =V.sub.D =0V, a TFT having its gate G supplied with 
gate voltage V.sub.G of -7V is held at 125.degree. C. for a long period of 
time. It has been found out that such -BT stress causes threshold voltage 
V.sub.th to shift toward negative voltage in the order of 0.1V for 
10.sup.4 sec. 
FIG. 2 is a graph showing the result of a test in the -BT stress state 
illustrated in FIG. 1. In the graph, the abscissa represents gate voltage 
V.sub.G (V), and the ordinate represents drain current I.sub.D (A). Curve 
2A represents the I.sub.D -V.sub.G characteristic of a TFT before the -BT 
stress test. Curve 2B represents the I.sub.D -V.sub.G characteristic after 
passage of 3.times.10.sup.4 sec since the initiation of -BT stress test. 
Dotted curve 2C represents for reference I.sub.D -V.sub.G characteristic 
after passage of 3.times.10.sup.4 sec since the initiation of +BT stress 
test for V.sub.G =+7V. As can be seen from a comparison between curves 2A, 
2B, and 2C, in the +BT stress test, the I.sub.D -V.sub.G characteristic 
hardly changes, but in the -BT stress test, the threshold voltage V.sub.th 
changes by about -0.3V. Stated differently, after the -BT stress test, 
drain current I.sub.D drops. 
The amount of shift of threshold voltage .DELTA.V.sub.th due to the -BT 
stress is greater than the case of a hot carrier stress test illustrated 
in FIG. 23 using the same gate voltage V.sub.G. 
When TFTs operate as part of a CMOS (Complimentary MOS) circuit, a P 
channel TFT is put under the same bias condition as -BT stress at a higher 
time ratio, and therefore drain current does not continue to flow unlike 
the case of the hot carrier stress state. 
It can be understood from the above that the influence of -BT stress upon a 
TFT in terms of the reliability of the TFT is significant. 
As described above, degradation due to -BT stress has already been known in 
a bulk monocrystalline MOSFET. In a polysilicon TFT, however, since 
dangling bonds of silicon in grain boundaries are partly responsible for 
degradation due to -BT stress, the degradation of the polysilicon TFT due 
to the -BT stress is about ten times as large as the case of the 
monocrystalline MOSFET. 
FIG. 3 is a graph showing the results of -BT stress tests in a bulk 
monocrystalline MOSFET and a polysilicon TFT. In the graph, the abscissa 
represents time (sec), and the ordinate represents the amount of shift of 
threshold voltage -.DELTA.V.sub.th (V). Marks .circle-solid. and 
.largecircle. represent a polysilicon TFT and a bulk monocrystalline 
MOSFET, both of which have a gate insulating film formed by LPCVD (Low 
Pressure Chemical Vapor Deposition). Meanwhile .quadrature. represents a 
bulk monocrystalline MOSFET having an insulating oxide film formed by 
means of thermal oxidation. The -BT stress condition shown in FIG. 1 was 
used. It can be seen from FIG. 3 that the amount of shift of threshold 
voltage -.DELTA.V.sub.th of the TFT in the -BT stress test is far larger 
than the case of the monocrystalline MOSFET. More specifically, in the 
monocrystalline MOSFET, since the amount of shift of the threshold voltage 
due to -BT stress is small, degradation due to the -BT stress does not 
cause any serious problem, but for the polysilicon TFT, the -BT stress 
causes a significant problem. 
The inventors have ascertained the mechanism of threshold voltage shift due 
to -BT stress in a polysilicon TFT. 
FIG. 4 illustrates the mechanism of threshold voltage shift due to -BT 
stress in a polysilicon TFT. This mechanism is understood from FIG. 4 and 
the following expression (1). 
EQU .tbd.Si.sub.S --H+.tbd.Si.sub.0 --O--Si.sub.0 
.tbd..revreaction..tbd.Si.sub.S.sup..multidot. +.tbd.Si.sub.0.sup.+ 
+.tbd.Si.sub.0 --OH+e.sup.- (1) 
More specifically, in polysilicon grain boundaries and the interface of 
polysilicon and SiO.sub.2, hydrogenated dangling bonds of .tbd.Si.sub.S 
--H and SiO.sub.2 network of .tbd.Si.sub.0 --O--Si.sub.0 .tbd. cause the 
reaction given by expression (1), and interface trap of 
.tbd.Si.sub.S.sup..multidot. and positive fixed charge of 
.tbd.Si.sub.0.sup.+ are generated. By the influence of the positive fixed 
charge, the threshold voltage V.sub.th of the TFT shifts toward negative 
voltage. Herein, Si.sub.S represents silicon atoms in polysilicon and 
Si.sub.0 represents silicon atoms in silicon oxide. 
The inventors have found out that the amount of the shift of the threshold 
voltage can be expressed in a formula. The amount of shift .DELTA.V.sub.th 
of threshold voltage V.sub.th when a TFT is supplied with gate voltage 
V.sub.G and held at absolute temperature T for time t is given by the 
following expression (2). 
##EQU9## 
where .alpha. represents time coefficient, .phi..sub.0 temperature 
coefficient, d voltage coefficient, k Boltzmann constant, q elementary 
electric charge, and t.sub.0X the thickness of the gate insulating film. 
In the following, a method of estimating the amount of shift of the 
threshold voltage .DELTA.V.sub.th of a TFT due to -BT stress will be 
described using the above expression (2). 
First, the temperature of the TFT is for example set at 125.degree. C., a 
temperature in the -BT stress state. At the temperature, I.sub.D -V.sub.G 
characteristic is measured and the threshold voltage V.sub.th of the TFT 
is calculated. The threshold voltage at the time is called initial 
threshold voltage V.sub.th0. 
Then, as illustrated in FIG. 1, at temperature T=125.degree. C., source S 
and drain D are connected to a potential of 0V and gate G is supplied with 
a negative voltage of -7V. This state is the -BT stress state, and time 
for initiating application of the gate voltage is set as t=0. 
After passage of prescribed time t, the -BT stress state is released, and 
threshold voltage V.sub.th (t) at time t is measured. After the 
measurement of threshold voltage V.sub.th (t) is completed, the TFT is 
immediately returned to the -BT stress state. By repeating such 
measurement of threshold voltage V.sub.th (t), a graph as illustrated in 
FIG. 5 is obtained. 
In FIG. 5, the abscissa represents time (sec), and the ordinate the amount 
of shift of threshold voltage -.DELTA.V.sub.th (V). Herein, the amount of 
shift of threshold voltage .DELTA.V.sub.th =V.sub.th (t)-V.sub.th0 holds. 
Based on the graph in FIG. 5, time coefficient .alpha. in the following 
expression (3) can be determined. 
EQU .DELTA.V.sub.th V.sub.1 t.sup..alpha. (3) 
where V.sub.1 is a constant of proportion. Time coefficient .alpha. can be 
determined more accurately as the -BT stress time is longer, and in the 
case of FIG. 5, .alpha.=1/3 is obtained. Thereafter, a procedure of 
producing time coefficient .alpha. is called process A. 
Now, in a polysilicon TFT manufactured under the same condition, as 
illustrated in FIG. 6, a -BT stress test in which a different gate voltage 
from process A is applied. In the example in FIG. 6, V.sub.G =-12V, and 
the temperature is set to 125.degree. C. which is the same as the case of 
process A. According to the procedure described in conjunction with 
process A, the amount of shift of threshold voltage V.sub.th is measured. 
FIG. 7 is a graph showing results of a plurality of -BT stress tests using 
different gate voltages V.sub.G. The abscissa represents gate voltage 
V.sub.G (V), and the ordinate represents the amount of shift of threshold 
voltage -.DELTA.V.sub.th (V). Mark .largecircle. in the left of the graph 
represents a test result under the condition in FIG. 1 and mark 
.largecircle. in the right a test result under the condition of FIG. 6. 
The test results under these conditions both represent the states after 
passage of identical time t=t.sub.0 after initiation of the tests. In FIG. 
17, results at t.sub.0 =10.sup.4 sec are set forth. Based on the graph, 
voltage coefficient d=3.8 .ANG. in the following expression (4) can be 
obtained. 
##EQU10## 
where V.sub.2 is a constant of proportion. 
Note that the gate voltages V.sub.G of -7V and -12V were used in FIG. 7, 
but the value of voltage coefficient d can more accurately be produced by 
conducting more tests using more different gate voltages V.sub.G. In such 
a plurality of tests for producing voltage coefficient d, the temperature 
used for these tests must be constant, but needs not be the same as the 
temperature used in process A. 
Hereinafter, the procedure for producing voltage constant d is called 
process B. Since .vertline.V.sub.G .vertline./t.sub.0X in expression (4) 
represents electric field, voltage coefficient d can be considered as 
electric field coefficient. Alternatively, d'=qd/2k may be considered as 
electric field coefficient. 
In a polysilicon TFT manufactured under the same condition, as illustrated 
in FIG. 8, -BT stress test is conducted at a temperature different from 
the case of process A. In the example of FIG. 8, the temperature of 
25.degree. C. is used, and gate voltage is set to V.sub.G =-7V which is 
the same as process A. Under these conditions, change of the amount of 
shift of threshold voltage .DELTA.V.sub.th as a function of time is 
measured according to the procedure the same as that described in 
conjunction with process A. 
FIG. 9 is a graph showing measurement results by the conditions in FIG. 1 
and by the conditions in FIG. 8. In the graph, the abscissa represents the 
inverse number of temperature 1000/T (/K) and the ordinate the amount of 
shift of threshold voltage -.DELTA.V.sub.th (V). Also in the graph of FIG. 
9, a result after passage of t.sub.0 =10.sup.4 sec since the initiation of 
the test is set forth. .quadrature. in the left represents a result under 
the conditions in FIG. 1, and .quadrature. in the right represents a 
result under the conditions in FIG. 8. Based on voltage coefficient d 
obtained in process B and FIG. 9, temperature coefficient .phi..sub.0 in 
the following expression (5) can be obtained. 
##EQU11## 
In the example of FIG. 9, q.phi..sub.0 -0.23 eV is obtained. Hereinafter, 
such a procedure of producing temperature coefficient .phi..sub.0 is 
called process C. 
Also in process C, by conducting tests under various more temperature 
conditions, the value of temperature coefficient .phi..sub.0 can more 
accurately produced. In a plurality of tests in process C, as long as 
constant gate voltage is used, the voltage used in these tests may be 
different from the gate voltage in process A. 
By the above-described three processes A, B, and C, the amount of shift of 
threshold voltage .DELTA.V.sub.th due to -BT stress in a polysilicon TFT 
can be estimated based on the following expression (6). 
##EQU12## 
Herein, t.sub.0 was 10.sup.4 sec in the foregoing example, but it goes 
without saying that any arbitrary appropriate time can be set for t.sub.0. 
Furthermore, even if the value of t.sub.0 is different between processes B 
and C, since time coefficient .alpha. is known, the amount of shift of 
threshold voltage .DELTA.V.sub.th can be produced. 
Processes A, B, and C may be conducted in an arbitrary order. In the 
above-described examples, voltage coefficient d produced in process B is 
used in process C, but if process C is conducted first, .phi..sub.E 
defined by the following expression (7) is produced, 
##EQU13## 
and then .phi..sub.E needs only be transformed into .phi..sub.0 using 
voltage coefficient d produced in process B. 
Using expression (6), the amount of shift of threshold voltage 
.DELTA.V.sub.th after passage of some time t in a -BT stress state can be 
estimated. Conversely, time .tau. (the life of TFT) until the amount of 
shift of threshold voltage .DELTA.V.sub.th reaches ascertain tolerance 
value .DELTA.V.sub.th.tau. can be produced. Substitution of 
.DELTA.V.sub.th =.DELTA.V.sub.th.tau. and t=.tau. for expression (6) 
solves .tau. and the following expression (8) results. 
##EQU14## 
where .beta.=1/.alpha.. More specifically, in expression (8), substituting 
the amount of shift of threshold voltage .DELTA.V.sub.th.tau. which is 
tolerated as a range without causing malfunction of the TFT, gate voltage 
V.sub.G used, and the value of temperature T for expression (8) can 
produce the life .tau. of the TFT under the -BT stress. 
Note that the above-described method of evaluating reliability can be 
applied to a monocrystalline MOSFET. 
FIG. 10 is a flow chart showing a procedure in a method of evaluating the 
reliability of a TFT based on expression (8). In this figure, the 
procedure of the method of evaluating the reliability of the TFT using 
expression (8) can be understood visually more clearly. 
In the following, one example of a variation of the above-described 
reliability evaluation method will be described. If time coefficient 
.alpha., voltage coefficient d, temperature coefficient .phi..sub.0 and 
constant of proportion related to the life of a TFT given as follows; 
##EQU15## 
have been already produced for the TFT (a), for example, the life of 
another TFT (b) can be estimated as follows. 
For TFT (b), at least one -BT stress test is conducted, and the amount of 
shift of threshold voltage .DELTA.V.sub.thb at certain time t.sub.0 is 
obtained. The amount of shift of threshold voltage .DELTA.V.sub.tha for 
TFT (a) under the same condition is obtained as well. For TFT (a), 
expression (6) has already been established, .DELTA.V.sub.tha may be 
produced from expression (6) or produced by actually measuring it. 
Once .DELTA.V.sub.thb and .DELTA.V.sub.tha under the same condition are 
produced, using their ratio, the threshold voltage shift amount and life 
of TFT (b) under an arbitrary condition can be represented by expressions 
(6a) and (8a). Note that for coefficient .beta. (=1/.alpha.), d, and 
.phi..sub.0 in expressions (6a) and (8a), values related to TFT (a) are 
used. 
##EQU16## 
Since coefficients .beta., d and .phi..sub.0 depend on a method of 
manufacturing a TFT, if TFTs (a) and (b) are manufactured by significantly 
different manufacturing methods, it would be difficult to accurately 
estimate the life of TFT (b), while if there is not much difference 
between their manufacturing methods, the life of TFT (b) can readily be 
estimated from expression (8a) utilizing the expression obtained for TFT 
(a). Furthermore, since time coefficient .beta. can be obtained by a 
single -BT stress test, using time coefficient .beta. for TFT (b) itself 
in expression (8a), the life .tau. of TFT (b) can more accurately be 
estimated. 
FIG. 11 is a flow chart for use in illustration of a method of readily 
estimating the life of a TFT using expression (8a). In this figure, 
another method of readily estimating the life of TFT (b) using a result of 
a -BT stress test related to another TFT (a) can more visually clearly 
understood. 
If it is not necessary to estimate the life of the TFT at a temperature 
other than a certain predetermined temperature T.sub.0, it will not be 
necessary to obtain temperature coefficient .phi..sub.0 by the 
above-described process C. At the time, the amount of the threshold 
voltage shift amount .DELTA.V.sub.th and life .tau. of the TFT can be 
obtained by the following expressions (6b) and (8b). 
##EQU17## 
The procedure of estimation of the life of the TFT in this case is 
illustrated in the flow chart in FIG. 12. 
Using the result related to TFT (a) obtained by the procedure in FIG. 12, 
the procedure of another method of estimation for the life of TFT (b) is 
illustrated in the flow chart in FIG. 13. More specifically, using the 
threshold voltage shift amounts .DELTA.V.sub.tha and .DELTA.V.sub.thb for 
TFT (a) and TFT (b) under the same condition, substitution of 
.DELTA.V.sub.th0 .multidot..DELTA.V.sub.thb /.DELTA.V.sub.tha for 
.DELTA.V.sub.th0 in expression (8b) can produce the life .tau. of TFT (b). 
Furthermore, if it is not necessary to estimate the life of the TFT at 
voltage other than predetermined gate voltage V.sub.G0, it will not be 
necessary to obtain voltage coefficient d in the above-described process 
B. In this case, the amount of threshold voltage shift .DELTA.V.sub.th and 
life .tau. of the TFT are obtained by following expressions (6c) and (8c). 
##EQU18## 
The procedure in the method of evaluating the reliability of the TFT when 
it is not necessary to produce voltage coefficient d like this is 
illustrated in the flow chart in FIG. 14. 
FIG. 15 is a flow chart illustrating the procedure of another method of 
readily estimating the life of TFT (b) using the result for TFT (a) 
obtained by the procedure in FIG. 14. More specifically, using threshold 
voltage shift amounts .DELTA.V.sub.tha and .DELTA.V.sub.thb for TFT (a) 
and TFT (b) under the same condition, substituting .DELTA.V.sub.th0 
.multidot..DELTA.V.sub.thb /.DELTA.V.sub.tha for .DELTA.V.sub.th0 in 
expression (8c) can produce the life .tau. of TFT (b). 
In the following, a method of setting the tolerant amount of threshold 
voltage shift .DELTA.V.sub.th.tau. in expression (8) related to a TFT used 
particularly in a memory cell in an SRAM will be described. 
In FIG. 16, one example of a memory cell in an SRAM is illustrated in an 
equivalent circuit diagram. The memory cell in the SRAM stores data by a 
flipflop including two driver transistors 12a, 12b and two load 
transistors TFTs 11a, 11b. TFT 11a on the side of H (high level) node in 
the memory cell in FIG. 16 is in a voltage state shown in FIG. 17 at (A). 
The voltage state of TFT shown in FIG. 17 at (A) is equivalent to a 
voltage state shown in FIG. 17 at (B). More specifically, it is understood 
that TFT 11a in FIG. 16 is in a -BT stress state. More specifically, if 
data continues to be held at a relatively high temperature and at gate 
voltage V.sub.G having a relatively large absolute value, the threshold 
voltage V.sub.th of TFT 11a continues to shift toward negative voltage 
side with time. More specifically, the ON current of TFT 11a decreases 
with time. 
Such shift of threshold voltage V.sub.th and decreasing of ON current for 
the TFT due to the -BT stress will be disadvantageous when the SRAM is 
driven with low power consumption. When the SRAM is driven with low power 
consumption, in 1M-4M bit class SRAMs, for example, writing and reading 
are conducted for power supply voltage V.sub.CC =3-7V, but even for 
voltage as low as V.sub.CC =1.5, data must be at least held. In SRAMs 
having other bit numbers, data must be held at voltage lower than voltage 
permitting writing and reading. However, this may not be possible for the 
shift of threshold voltage V.sub.th due to -BT stress. 
Now, the operation of a memory cell when power supply voltage V.sub.CC is 
about as low as the threshold voltage of a driver transistor (0.6-1.0V) is 
considered. In FIG. 16, considering the load transistor on H node side TFT 
11a and driver transistors 12a, TFT 11a is in ON state, and driver 
transistor 12a is in OFF state, and current values for these transistors 
are very close to each other at low voltage. In this case, if the ON 
current of TFT 11a decreases due to -BT stress, it becomes close to the 
same level as the OFF current of driver transistor 12a. In such a case, 
the potential of H node in FIG. 16 decreases and the ON current of driver 
transistor 12b on the L (low level) node side which is in ON state 
decreases. Accordingly, the potential of L node rises. If the potential of 
L node rises, the ON current of TFT 11a on the H node side further 
decreases, and the OFF current of driver transistor 12a tends to increase. 
As a result, the potential of H node further decreases. If such change is 
repeated, finally inversion of held data results. 
Herein, the OFF current of driver transistor 12a increases about ten times 
as the potential of the above-described L node rises, because as 
illustrated in FIG. 18, the subthreshold coefficient S of I.sub.D -V.sub.G 
is about 100 mV/dec as the potential of L node rises by 0.1V. 
Driving of an SRAM at low voltage has been described by referring to the 
case in which power supply voltage V.sub.CC is about as low as the 
threshold voltage of the driver transistor, and since voltage drop is 
generated also due to wiring resistance in an actual memory cell, TFT 
degradation due to -BT stress can also be disadvantageous even if higher 
power supply voltage V.sub.CC is used. 
It is assumed that at a minimum voltage which guarantees data holding (1.5V 
in 1M-4M bit class SRAMs) increase of the OFF current of a driver 
transistor due to increase of the potential of L node is tolerated up to 
about ten times, and that data is not inverted unless the ON current of 
the TFT at the minimum voltage is at most ten times as large as the OFF 
current of the driver transistor. 
FIG. 19 is a graph showing shift in the I.sub.D -V.sub.G characteristic of 
a TFT due to -BT stress. The abscissa represents gate voltage V.sub.G (V), 
and the ordinate represents drain current I.sub.D in logarithmic scale. 
Lower and upper dotted horizontal lines represent the OFF current level of 
the driver transistor and a current level ten times as large, respectively 
when V.sub.CC is sufficiently high. Curve 19A represents a characteristic 
before -BT stress is applied, and curve 19B represents the state after -BT 
stress at certain time in which the current value at the minimum voltage 
of 1.5V to hold data matches the value ten times as large as the OFF 
current of the driver transistor when power supply voltage V.sub.CC is 
sufficiently large. More specifically, if the I.sub.D -V.sub.G 
characteristic of the TFT shifts to the left from curve 19B, data could be 
inverted. Accordingly, time until the characteristic of TFT shifts to 
curve 19B can be defined as the life of the TFT. 
In this case, if the threshold voltage V.sub.th of the TFT is defined by a 
constant current method by which current ten times as large as the OFF 
current of the driver transistor is used as a constant current value (a 
method by which gate voltage necessary to obtain a set certain constant 
current value is set to be threshold voltage V.sub.th), the amount of 
shift of threshold voltage tolerated .DELTA.V.sub.th.tau. is given by the 
following expression (9). 
EQU .DELTA.V.sub.th.tau. =V.sub.CCL -.vertline.V.sub.th0 .vertline.(9) 
Herein, V.sub.CCL indicates a lower limit for power supply voltage. In the 
case of FIG. 19, if .DELTA.V.sub.th.tau. 
=1.5-.vertline.-0.8.vertline.=0.7V, and the threshold voltage shift due to 
-BT stress is at most 0.7V, there will be no possibility of inversion of 
data. Accordingly, for an SRAM driven with low power consumption, the life 
of a TFT under -BT stress can be obtained by substituting the value of 
.DELTA.V.sub.th.tau. defined in expression (9) for expression (6). 
Now, a method of determining the tolerant amount of shift of threshold 
voltage .DELTA.V.sub.th.tau. for a TFT used in an SRAM memory cell driven 
at a high speed will be described. In FIG. 16, data writing will be 
considered. When data is written, access transistors 13a, 13b are turned 
on and a bit line connected to a node to be written with L among bit lines 
14a, 14b in H state is pulled to 0V. However, at the node on the other H 
side, voltage will not completely increase to the level of power supply 
voltage V.sub.CC and decreases by the amount corresponding to the 
threshold voltage V.sub.th of the access transistor. At the time, the 
portion corresponding to the decrease of the voltage is compensated for by 
the ON current of the TFT. Accordingly, if the ON current of the TFT is 
reduced due to -BT stress, time required for charging the node on the H 
side is prolonged. It is therefore necessary to previously set tolerant 
time required for charging the node and the ON current of the TFT must be 
maintained so as not to exceed the tolerant time. For example, for the 
capacity of the storage node=5 fF and the threshold voltage V.sub.th of 
the access transistor=1V, it is pointed out that 5 fF.times.1V/5 nano 
seconds=1 .mu.A or larger current is necessary in order to charge the node 
in 5 nano seconds. Such minimum necessary current value is hereinafter 
called standard current value I.sub.1. 
When an SRAM is driven at a high speed, it will not be operated with low 
voltage and therefore the graph in FIG. 19 is of no use. 
FIG. 20 is a graph showing change of the I.sub.D -V.sub.G characteristic of 
a TFT due to -BT stress. Curve 20A represents an initial characteristic 
and drain current at .vertline.V.sub.G .vertline.=operation V.sub.CC is 
identified as I.sub.D0. Curve 20B represents the characteristic when drain 
current I.sub.D at .vertline.V.sub.G .vertline.=operation V.sub.CC is 
equal to standard current value I.sub.1 after shifting toward negative 
voltage due to -BT stress. More specifically, if the I.sub.D -V.sub.G 
characteristic shifts further toward the negative voltage side from curve 
20B, it will not be possible to charge the storage node with the ON 
current of the TFT within a prescribed time period. 
Accordingly, if the threshold voltage V.sub.th of the TFT is determined by 
the constant current method with standard current value I.sub.1 being the 
constant current value, the tolerant amount of shift of threshold voltage 
.DELTA.V.sub.th.tau. is given by following expression (10). 
EQU .DELTA.V.sub.th.tau. =Operation V.sub.CC -.vertline.V.sub.th0 .vertline.(10 
) 
The tolerant amount of shift of threshold voltage .DELTA.V.sub.th.tau. can 
also be given by the following approximate expression. 
In FIG. 20, the intersection of initial characteristic 20A and standard 
current value I.sub.1 is X and the slope of curve 20A at point X is S. 
Herein, slop S is expressed in mV/dec as in the case of the subthreshold 
coefficient. If the initial current value of the drain is I.sub.D0, the 
following expression is given. 
EQU .DELTA.V.sub.th.tau. .apprxeq.(logI.sub.D0 -logI.sub.1).times.S(11) 
Substituting the value of tolerant threshold voltage shift amount 
.DELTA.V.sub.th.tau. produced from the above expression (10) or (11) in 
expression (6) makes it possible to evaluate the -BT stress life of the 
TFT in the DRAM driven at a high speed. 
SRAMs undergo burn-in tests before being marketed. The burn-in test is to 
generate defects in unstable semiconductor circuit chips by maintaining 
semiconductor circuit chips at a high temperature and high voltage, so 
that such semiconductor chips including the defects are avoided from being 
marketed. 
Burn-in tests include a static burn-in test and a dynamic burn-in test. In 
the dynamic burn-in test, data is periodically rewritten at a high 
temperature and under high voltage. On the other hand, in the static 
burn-in test, data may be maintained as constant. 
For ease of representation, in the case of the static burn-in test, TFT on 
the node side at which H is written attains a -BT stress state, and 
therefore its threshold voltage V.sub.th shifts toward negative voltage. 
FIG. 21 is a graph showing change of the I.sub.D -V.sub.G of a TFT by a 
burn-in test. Curve 21A represents an initial characteristic. Curve 21B 
shows the characteristic of the TFT on the H node side after a static 
burn-in test. When threshold voltage shift by the static burn-in test as 
in this graph is estimated from expression (6) and the threshold voltage 
V.sub.th of the TFT is previously set shifted toward positive voltage side 
by the amount of the estimated shift, the problem of the threshold voltage 
shift due to such a static burn-in test can be solved. Initial threshold 
voltage V.sub.th can be controlled by adjusting impurity concentration in 
the channel of the TFT. 
However, since only the TFT on the H node side attains a -BT stress state, 
the threshold voltage V.sub.th of the other TFT should be shifted by 
inverting the data of all the bits when the static burn-in test is half 
completed. More specifically, it has been found out that the 
characteristic of the TFT on the L node side hardly changes by a burn-in 
test. 
In addition, in the case of a dynamic burn-in test, since H and L sides are 
exchanged alternately, for one TFT, only time periods when it attains H 
needs to be multiplied to set initial threshold voltage V.sub.th taking 
into account threshold voltage shift amount .DELTA.V.sub.th by expression 
(6). 
Now, a TFT with a gate oxide film having a thickness permitting 
implementation of a maximum -BT stress life will be described. Under -BT 
stress, positive fixed charge .tbd.Si.sub.0.sup.+ is generated in the gate 
oxide film in the vicinity of the interface between gate oxide film and 
the channel. For the density of fixed charge N.sub.SC and gate capacitance 
C.sub.0X =.epsilon..sub.0X /t.sub.0X, threshold voltage shift amount 
.DELTA.V.sub.th0 is given by the following expression (12). 
##EQU19## 
where .epsilon..sub.0X represents the dielectric constant of SiO.sub.2. 
Accordingly, as the thickness t.sub.0X of the gate oxide film increases, 
threshold voltage shirt amount .DELTA.V.sub.th0 increases in proportion to 
the thickness t.sub.0X of the gate oxide film. However, it can be seen 
from expression (6) that as the thickness t.sub.0X of the gate oxide film 
increases, the influence of gate voltage V.sub.G decreases and therefore 
threshold voltage shift amount .DELTA.V.sub.th decreases. 
Using expression (12), expressions (6) and (8) are transformed into the 
following expressions (6d) and (8d), respectively. 
##EQU20## 
It can be seen that with temperature T and V.sub.G being constant, from 
expression (6d) threshold voltage shift amount .DELTA.V.sub.th is 
minimized for a certain thickness t.sub.0X of the gate oxide film. From 
expression (8d), the -BT stress life .tau. of the TFT is maximized for a 
certain thickness t.sub.0X of the gate oxide film provided that T, V.sub.G 
and .DELTA.V.sub.th.tau. are constant. 
More specifically, when expression (8d) is differentiated with t.sub.0X to 
produce [.sigma..tau./.sigma..tau..sub.ox ].sub.tox=tox-opt =0 the 
following expression is given. 
EQU t.sub.0X =qd.vertline.V.sub.G .vertline./2kT (13) 
This means that the -BT stress life .tau. is maximized when the gate 
insulating film has this thickness. 
For example, for a TFT at V.sub.G =-3.3V and operation temperature 
T=120.degree. C., from expression (13), its -BT stress life is maximized 
at t.sub.OX-opt. For a TFT used at V.sub.G =-3.3V and operation 
temperature T=77.degree. C., its -BT stress life is maximized when 
t.sub.0X =208 .ANG.. However, in practice, the life of a TFT is 
substantially maximized at a tolerance of .+-.10% for the thickness 
obtained from expression (13). 
In the above description, the operation temperature of the TFT means the 
temperature of the TFT itself. Stated differently, even for a TFT operated 
in a room temperature atmosphere, if the semiconductor chip generates heat 
and the temperature of the TFT itself is 77.degree. C., the operation 
temperature of the TFT is 77.degree. C. 
FIG. 25 shows apparatus for performing the calculations described in 
connection with the present invention. The apparatus includes a standard 
computer arrangement 85 having a conventional central processing unit 
(CPU) (not shown), a random access memory (not shown), and a hard disk 
drive (not shown) each installed within housing 76, a display 78, a 
keyboard 80, a modem 74 for transmitting signals to/from the computer 85 
over a telephone network (not shown), and a CD-ROM drive 72 into which a 
CD-ROM 70 can be inserted. CD-ROM 70 is one example of a machine-readable 
medium storing a machine executable software procedure for performing the 
calculations described in connection with the present invention. Other 
types of machine-readable media could be used for storing the machine 
executable software procedure such as the computer's floppy disk, a read 
only memory (ROM) chip, etc. Another medium for storing the machine 
executable software procedure is the computer's resident memory loaded 
from the hard disk of the floppy disk, a remote drive or ROM, or 
downloaded from a remote source over the telephone network via the modem 
74 or on an ISDN line. 
As described above, according to the present invention, the threshold 
voltage shift amount and life of a polysilicon TFT due to -BT stress are 
estimated using expressions based on the mechanism of threshold voltage 
shift, and therefore an accurate and efficient method of evaluating the 
reliability of a TFT can be provided. 
Furthermore, employing the method of reliability evaluation according to 
the present invention, a TFT with threshold voltage V.sub.th set taking 
into account burn-in conditions can be provided. 
Furthermore, employing the method of reliability evaluation according to 
the present invention, a TFT including a gate insulating film having a 
thickness achieving a maximum useful life for each -BT stress condition in 
which the TFT is used can be provided. 
Although the present invention has been described and illustrated in 
detail, it is clearly understood that the same is by way of illustration 
and example only and is not to be taken by way of limitation, the spirit 
and scope of the present invention being limited only by the terms of the 
appended claims.