Semiconductor device having trench top isolation layer and method for forming the same

A method for forming a semiconductor device having a trench top isolation layer. A collar insulating layer is formed over a lower portion of the sidewall of the trench formed in a substrate. A first conductive layer is formed in the lower portion of the trench and protrudes the collar insulating layer, and a second conductive layer is formed overlying the first conductive layer and covers the collar insulating layer. An insulating spacer is formed over an upper portion of the sidewall of the trench and separated from the second conductive layer by a gap. The second conductive layer is partially thermally oxidized to form an oxide layer thereon whereby the gap is filled. After the oxide layer is removed, a reverse T-shaped insulating layer is formed thereon by chemical vapor deposition to serve as a trench top isolation layer. Finally, the insulating spacer is removed.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates in general to a method for forming a trench top isolation layer. More particularly, it relates to a semiconductor device having a trench top oxide (TTO) and the method for forming the same.

2. Description of the Related Art

Semiconductor devices are used in a variety of electronic applications, such as personal computers and cellular phones. In order to increase integrity of integrated circuits, the semiconductor industry in general is being driven to decrease the size of the semiconductor devices located on integrated circuits.

Semiconductor memory devices are one of the semiconductor products widely applied in electronic systems for storing data, and one common type of semiconductor memory is dynamic random access memory (DRAM). Typically, a DRAM cell includes an access field effect transistor (FET) and a storage capacitor. The access FET allows the transfer of data charges to and from the storage capacitor during reading and writing operations.

In order to decrease the size of the semiconductor memory devices, a vertical access transistor technology is developed. In such a technology, the storage capacitor is formed in the lower portion of the trench, and the access transistor is formed in the upper portion of the trench. In addition, a thick dielectric layer called trench top oxide (TTO) is formed between the capacitor and the transistor for electrical isolation therebetween.

FIG. 1is a cross-section showing a conventional semiconductor device having a trench top isolation layer. The semiconductor device includes a substrate100, such as a silicon substrate, having a deep trench103formed by etching the substrate100using a masking layer105as a hard mask. The masking layer105includes a pad oxide layer102and an overlying nitride layer104. A trench capacitor (not shown) is disposed in the lower portion of the trench103. A collar insulating layer106, such as silicon oxide, is disposed overlying the trench capacitor and over the sidewall of the lower portion of the trench103.

A conductive layer108, such as a polysilicon layer, is disposed overlying the trench capacitor and protrudes the collar insulating layer106. Another conductive layer112, such as a polysilicon layer, is disposed on the conductive layer108and covers the collar insulating layer106.

A buried strap110is formed in the substrate100near the upper portion of the collar insulating layer106to serve as a drain region for the subsequent vertical transistor. The drain region electrically connects with the trench capacitor through the conductive layers108and112. In general, the buried strap110is formed by diffusing the dopant in a doped dielectric layer (not shown) into the substrate100by a drive-in process.

A TTO layer114, such as tetraethyl orthosilicate (TEOS) oxide, is disposed on the conductive layer112for electrical isolation between the trench capacitor and the subsequent vertical transistor. Typically, the formation of the TTO layer114includes the following steps. First, a conformable silicon oxide layer is formed on the masking layer105and the inner surface of the trench103(overlying the conductive layer112) by high-density plasma chemical vapor deposition (HDPCVD), wherein the bottom of the silicon oxide layer in the trench103is thicker than that over the sidewall of the trench103. Thereafter, the silicon oxide layer on the masking layer105is removed by polishing and then that over the sidewall of the trench103is removed by wet chemical etching to leave the bottom portion of the silicon oxide layer in the trench103. After wet chemical etching, however, the remaining silicon oxide layer serving as a TTO layer is dished at its middle portion, as shown in theFIG. 1, causing poor edge uniformity. The non-uniform TTO layer114degrades the insulating property and reduces reliability of the semiconductor device.

SUMMARY OF THE INVENTION

Accordingly, an object of the present invention is to provide a novel method for forming a semiconductor device having a trench top isolation layer, which employs a two step deposition method such as thermal oxidation and chemical vapor deposition instead of conventional single step deposition to form the trench top isolation layer, thereby precisely controlling its thickness.

Another object of the present invention is to provide a semiconductor device having a trench top isolation layer, which uses a reverse T-shaped trench top oxide layer to increase its edge uniformity, thereby preventing poor insulation due to the dishing effect of the trench top isolation layer.

According to the object of the invention, a method for forming a semiconductor device having a trench top isolation layer is provided. First, a collar insulating layer is formed over a lower portion of the sidewall of the trench formed in a substrate. Next, a first conductive layer is formed in the lower portion of the trench and protrudes the collar insulating layer. Thereafter, a second conductive layer is formed overlying the first conductive layer and covers the collar insulating layer. Next, an insulating spacer is formed over an upper portion of the sidewall of the trench and separated from the second conductive layer by a gap. Next, the second conductive layer is partially thermally oxidized to form an oxide layer thereon whereby the gap is filled. After the oxide layer is removed, a reverse T-shaped insulating layer is formed thereon by chemical vapor deposition to serve as a trench top isolation layer. Finally, the insulating spacer is removed.

The collar insulating layer can be a silicon oxide layer. The first conductive layer can be a polysilicon layer and the second conductive layer can be a doped polysilicon layer.

Moreover, the reverse T-shaped trench top insulating layer can be a tetraethyl orthosilicate (TEOS) oxide and formed by low pressure CVD (LPCVD).

Another aspect of the invention is a semiconductor device having a trench top isolation layer. The device includes a substrate, a first conductive layer a second conductive layer, and a reverse T-shaped insulating layer. The substrate has at least one trench and a collar insulating layer is disposed over a lower portion of the sidewall of the trench. The first conductive layer is disposed in the lower portion of the trench and protrudes the collar insulating layer. The second conductive layer is disposed overlying the first conductive layer and covers the collar insulating layer. The reverse T-shaped insulating layer is disposed overlying the second conductive layer to serve as a trench top isolation layer. A gate is disposed overlying the reverse T-shaped insulating layer and insulated from the substrate.

The collar insulating layer can be a silicon oxide layer. The first conductive layer can be a polysilicon layer and the second conductive layer can be a doped polysilicon layer.

Moreover, the reverse T-shaped trench top insulating layer can be a tetraethyl orthosilicate (TEOS) oxide and formed by low pressure CVD (LPCVD).

DETAILED DESCRIPTION OF THE INVENTION

InFIG. 2a, a substrate200, such as a silicon substrate, is provided. A mask layer205is formed on the substrate200. The mask layer205can be composed of a pad oxide layer202and a thicker overlying silicon nitride layer204. In this invention, the pad oxide layer202can be formed by thermal oxidation or conventional CVD, which has a thickness of about 100 Å. Moreover, the silicon nitride layer204overlying the pad oxide layer202can be formed by LPCVD using SiCl2H2and NH3as reaction sources. Next, a plurality of openings is formed in the masking layer205by lithography and etching. Thereafter, anisotropic etching, such as reactive ion etching (RIE), is performed on the substrate200using the masking layer205as an etch mask to form a plurality of trenches therein. In order to simplify the diagram, only one trench203is shown.

Next, a trench capacitor (not shown) is formed in the bottom of the trench203. The trench capacitor includes a buried plate (BP), a capacitor dielectric layer, and a top plate. The buried plate is a doping region formed in the substrate200near the bottom of the trench203. The capacitor dielectric layer can be a silicon oxide/silicon nitride (ON) layer or a silicon oxide/silicon nitride/silicon oxide (ONO) layer. The top plate can be a polysilicon layer.

Next, a collar insulating layer206, such as silicon oxide, is formed over a lower portion of the sidewall of the trench203and overlying the trench capacitor. Thereafter, a doping region210is formed in the substrate200near the upper portion of the collar insulating layer206to serve as a drain region for the subsequent vertical transistor. In the invention, the doping region210is formed in the substrate200by diffusing the dopant in a doped dielectric layer (not shown) into the substrate200by a drive-in process.

Next, a first conductive layer208, such as a polysilicon or doped polysilicon layer, is formed in the lower portion of the trench203(overlying the trench capacitor) and protrudes the collar insulating layer206. Thereafter, a second conductive layer212, such as a doped polysilicon layer, is formed overlying the first conductive layer208and covers the collar insulating layer206to form a substantially flat surface. Here, the trench capacitor electrically connects with the doping region210through the first and second conductive layers208and212.

Next, inFIG. 2b, a pad oxide layer214and a silicon nitride layer216are successively and conformably formed on the masking layer205and the inner surface of the trench203. In the invention, the pad oxide layer214can be a tetraethyl orthosilicate (TEOS) oxide layer formed by chemical vapor deposition (CVD), which has a thickness of about 50˜60 Å. Also, the silicon nitride layer216can be formed by CVD, which has a thickness of about 150˜240 Å.

Next, inFIG. 2c, the silicon nitride layer216and the pad oxide layer214on the masking layer205and on the second conductive layer212in the trench203are removed by anisotropic etching, such as RIE, to form insulating spacers214aand216aover an upper portion of the sidewall of the trench203, which has a thickness of about 200˜300 Å. Subsequently, the bottom of the insulating spacer214ais removed by hydrofluoric (HP) acid or other suitable solution using the insulating spacer216aas an etch mask to form a gap having a width d of about 50˜60 Å between the insulating spacers214aand216aand the second conductive layer212.

Next, inFIG. 2d, thermal oxidation is performed to oxidize a portion of the second conductive layer212to form a doped silicon oxide layer218thereon whereby the gap is filled. Here, since the insulating spacer216acomposed of silicon nitride suppresses oxygen reacting with the doped polysilicon layer212, the doped silicon oxide layer218stops growing when the gap is fully filled with the oxide layer218. The doped silicon oxide layer218formed by thermal oxidation have good uniformity.

Next, inFIG. 2e, since the doped silicon oxide layer218has a poor insulating property, it is not sufficient to serve as a trench top isolation layer. Accordingly, in the invention, the doped silicon oxide layer218. is removed by HF to expose the second conductive layer212and leave a space with better edge uniformity for forming a trench top isolation layer in the subsequent process. Moreover, the thickness of the trench top isolation layer can be precisely controlled through the space.

Next, inFIG. 2f, the space is filled with an insulating layer220formed by CVD to serve as a trench top isolation layer. In the invention, the insulating layer220is formed overlying the second conductive layer212by low pressure CVD (LPCVD) using tetraethyl orthosilicate (TEOS) as a reaction source to fill and protrude from the space, so as to form a reverse T-shaped trench top oxide (TTO) layer220.

Finally, inFIG. 2g, the insulating spacers216aand214aare removed to expose the sidewall of the upper portion of the trench203. Next, a vertical transistor is formed overlying the trench top isolation layer220by conventional method.

Still inFIG. 2g, a cross-section of a semiconductor device having a trench top isolation layer according to the invention is shown. In the invention, the semiconductor device can be a dynamic random access memory (DRAM) which includes a substrate200, a first conductive layer208, a second conductive layer212, a reverse T-shaped insulating layer220, and a vertical transistor. The substrate200has at least one trench203, and a collar insulating layer206, such as silicon oxide, is disposed over the sidewall of the lower portion of the trench203.

The first conductive layer208, such as polysilicon, is disposed in the lower portion of the trench203and protrudes the collar insulating layer206. The second conductive layer212, such as doped polysilicon, is disposed overlying the first conductive layer208and covers the collar insulating layer206. Moreover, the reverse T-shaped insulating layer220, such as TEOS oxide, is disposed overlying the second conductive layer212to serve as a trench top oxide layer.

The vertical transistor is disposed overlying the reverse T-shaped insulating layer220, which includes a gate226, a gate dielectric layer224, a drain region210, and a source region224. The source region224is formed in the substrate200near the upper portion of the trench203by ion implantation, and the drain region is formed in the substrate200near the upper portion of the collar insulating layer206by diffusing the dopant in a doped dielectric layer (not shown) into the substrate200by a drive-in process. The gate dielectric layer222can be a silicon oxide layer formed by thermal oxidation. The gate226can be a doped polysilicon layer which is insulated from the substrate200by the gate dielectric layer222.

Compared to the prior art, the trench top isolation layer of the invention is formed by LPCVD, but not high-density plasma CVD (HDPCVD). Accordingly, the trench top isolation layer can be formed without dishing. Moreover, the reverse T-shaped trench top isolation layer of the invention is formed by a two step deposition such as thermal oxidation and LPCVD. Accordingly, excellent edge uniformity of the trench top isolation layer can be achieved, thereby increasing its insulating property and improving device reliability.