Integrated circuit packaging system with package underfill and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a sacrificial carrier assembly having a stack interconnector thereover; mounting an integrated circuit having a connector over the sacrificial carrier assembly with the connector over the stack interconnector; dispensing an underfill material between the sacrificial carrier assembly and the integrated circuit with the underfill material substantially free of a void; encapsulating the integrated circuit over the sacrificial carrier assembly and the underfill material; exposing the stack interconnector by removing the sacrificial carrier assembly; and forming a base array over the underfill material and the stack interconnector.

TECHNICAL FIELD

The present invention relates generally to an integrated circuit packaging system, and more particularly to a stackable packaging system with underfill.

BACKGROUND ART

The integrated circuit package is the building block used in a high performance electronic system to provide applications for usage in products such as automotive vehicles, pocket personal computers, cell phone, intelligent portable military devices, aeronautical spacecraft payloads, and a vast line of other similar products that require small compact electronics supporting many complex functions.

A small product, such as a cell phone, can contain many integrated circuit packages, each having different sizes and shapes. Each of the integrated circuit packages within the cell phone can contain large amounts of complex circuitry. The circuitry within each of the integrated circuit packages work and communicate with other circuitry of other integrated circuit packages using electrical connections.

Products must compete in world markets and attract many consumers or buyers in order to be successful. It is very important for products to continue to improve in features, performance, and reliability while reducing product costs, product size, and equally important to be available quickly for purchase by the consumers or buyers.

Time to market, reliability, and the amount of circuitry and the amount of electrical connections inside a product are key to improving the features, performance, and reliability of any product. Furthermore, the ways the circuitry and electrical connections are implemented have a direct impact on the availability, reliability, and costs of products.

Attempts have failed to provide a complete solution addressing simplified manufacturing processing, time to market, reliability, and costs with smaller dimensions, lower costs due to design flexibility, increased functionality, leveragability, and increased IO connectivity capabilities.

In view of the ever-increasing commercial competitive pressures, along with growing consumer expectations and the diminishing opportunities for meaningful product differentiation in the marketplace, it is critical that answers be found for these problems.

Solutions to these problems have been long sought after but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.

DISCLOSURE OF THE INVENTION

The present invention provides a method of manufacture of an integrated circuit packaging system including: providing a sacrificial carrier assembly having a stack interconnector thereover; mounting an integrated circuit having a connector over the sacrificial carrier assembly with the connector over the stack interconnector; dispensing an underfill material between the sacrificial carrier assembly and the integrated circuit with the underfill material substantially free of a void; encapsulating the integrated circuit over the sacrificial carrier assembly and the underfill material; exposing the stack interconnector by removing the sacrificial carrier assembly; and forming a base array over the underfill material and the stack interconnector.

The present invention provides an integrated circuit packaging system including: a stack interconnector; an integrated circuit having a connector over the stack interconnector; a base, having a first side and a second side, attached to the stack interconnector with the first side facing the stack interconnector; an underfill substantially free of a void between the base and the integrated circuit; an encapsulation over the integrated circuit; and a system interconnector attached to the second side.

BEST MODE FOR CARRYING OUT THE INVENTION

The drawings showing embodiments of the system are semi-diagrammatic and not to scale and, particularly, some of the dimensions are for the clarity of presentation and are shown greatly exaggerated in the drawing FIGs. Similarly, although the views in the drawings shown for ease of description and generally show similar orientations, this depiction in the FIGs. is arbitrary for the most part. Generally, the invention can be operated in any orientation.

Referring now toFIG. 1, therein is shown a top view of an integrated circuit packaging system100in a first embodiment of the present invention. The top view depicts an encapsulation102, such as an enclosure formed from an epoxy molding compound, used to protect the contents of the integrated circuit packaging system100.

For purposes of illustration, the encapsulation102of the integrated circuit packaging system100is shown having encapsulation non-horizontal sides104forming a rectangular footprint shape, although it is understood that the integrated circuit packaging system100can have a different footprint shape. For example, footprint shape of the encapsulation102of the integrated circuit packaging system100could have any polygon footprint shape.

Referring now toFIG. 2, therein is shown a cross-sectional view of the integrated circuit packaging system100of the present invention taken along a line2-2ofFIG. 1. The integrated circuit packaging system100can preferably include an integrated circuit202, such as a flip chip, an integrated circuit die, or integrated circuit device, with connectors204, such as solder balls, stud bumps, copper pillars, copper bars, or combinations thereof, mounted over a base206, such as a non-laminated redistribution structure.

The integrated circuit202can be covered with the encapsulation102. An underfill208can be formed of a material having specific coefficient of thermal expansion (CTE) characteristics and used to compensate for any thermal expansion mismatch between the integrated circuit202, the encapsulation102, and the base206. The connectors204can provide a stress buffering layer between the integrated circuit202and the base206. The underfill208can preferably be between the integrated circuit202and the base206surrounding the connectors204.

The underfill208can surround the connectors204between the integrated circuit202and the base206to provide protection from moisture or contamination. The underfill208can also provide protection from thermal and physical related stress to the connectors204, the integrated circuit202, and the base206.

Underfill non-horizontal sides210of the underfill208, can be exposed from the encapsulation102. The underfill non-horizontal sides210can preferably be coplanar with the encapsulation non-horizontal sides104.

A side of the underfill208facing the integrated circuit202can be in direct physical contact with the integrated circuit202and the encapsulation102. A side of the underfill208opposite the side facing the integrated circuit202can be in direct physical contact with the base206. The underfill208can cover areas of the edges212of the integrated circuit202and completely cover a first side218of the base206. The first side218faces the integrated circuit202. The integrated circuit202can be partially within the underfill208.

The underfill208itself can be substantially free of voids607ofFIG. 6, such as cavities, crevices, holes, cracks, or regions absent of the underfill208. The absence of the voids607prevents or eliminates cracks in the stack interconnectors222. The underfill208being free of the voids607also reduces or eliminates cracks in the integrated circuit202. The underfill208being free of the voids607further reduces delamination from the integrated circuit202. The reduction or elimination of the voids607in the underfill208improves the reliability of the integrated circuit packaging system100.

The base206can preferably include a routing trace214and a film layer216. The routing trace214can be located between the first side218of the base206and a second side220opposite the first side218of the base206.

The routing trace214can be formed from a conductive material such as gold, copper, aluminum, or any combination of electrically conductive material. The routing trace214can be used to provide connection paths within the base206and between the base206and the first side218or the second side220.

The film layer216, such as a passivation film layer or similar layer providing no conductivity, can be applied over or surround the routing trace214in multiple successive layers of the base206. The film layer216can also include materials, such as a resistive material or a dielectric material, which can applied over or surround portions of one or more of the routing trace214within the base206. The base206can preferably be formed of multiple layers of the film layer216and of the routing trace214resulting in improved routing density capabilities.

The film layer216, the routing trace214, or a combination thereof can be selectively formed or configured in the base206to form a passive circuit226, such as a film resistor, a film capacitor, or a film inductor. As an example, the passive circuit226is shown as a portion of the base206with the portion of the film layer216and the routing trace214connecting two stack interconnects222. This example can show the passive circuit226as a film inductor.

It has been discovered that the present invention provides the integrated circuit packaging system100with the capability to build integrated passive circuit, such as a film resistor, a film capacitor, or a film inductor, within the base206by configuring selective locations of the film layer216, the routing trace214, or a combination thereof. The film layer216can be of a resistive film layer or a dielectric film layer.

For purposes of illustration, the integrated circuit packaging system100is shown having the routing trace214formed within a single horizontal plane located in the base206. It is understood that the integrated circuit packaging system100can have the routing trace214configured differently. For example the routing trace214could be distributed within several different horizontal planes, each coplanar with one another and each separated by the film layer216. Furthermore, the routing trace214within a horizontal plane can have different connective path attributes from another of the routing trace214within a different horizontal plane.

Stack interconnectors222, such as bump pads, pillars, stacked stud bumps, contact pads, or connective contacts having connective compatibility with the connectors204, can be attached to the routing trace214adjacent the first side218. The connectors204can be connected over the stack interconnectors222to provide connectivity between the integrated circuit202and the base206. System connectors224, such as conductive balls, columns, posts, or pins, can be coupled to the routing trace214from the second side220of the base206to provide connectivity between the integrated circuit packaging system100and a next level of integration.

Referring now toFIG. 3, therein is shown a cross-sectional view of an integrated circuit packaging system300in a second embodiment of the present invention. The integrated circuit packaging system300has structurally similarities to the integrated circuit packaging system300ofFIG. 2.

The integrated circuit packaging system300can preferably include an encapsulation302, such as an enclosure formed from an epoxy molding compound, used to protect the contents of the integrated circuit packaging system300. The encapsulation302has encapsulation non-horizontal sides304substantially surrounding an integrated circuit306.

The integrated circuit306, such as a flip chip, an integrated circuit die, or integrated circuit device, with connectors308, such as solder balls, stud bumps, copper pillars, copper bars, or combinations thereof, can preferably be mounted over a base310.

The base310can be a structure formed from layers of both conductive and non-conductive materials. The base310can have functional characteristics similar to a printed circuit board or a package substrate but without limitations associated with the printed circuit board or the package substrate such as restrictive routing rules, finite wiring planes, and separate assembly process step. The integrated circuit306can be covered and surrounded with the encapsulation302.

An underfill312can be formed of a material having specific coefficient of thermal expansion (CTE) characteristics and used to compensate for the thermal expansion mismatch with the integrated circuit306, the encapsulation302, and the base310. The underfill312can preferably be between the integrated circuit306and the base310and surround the connectors308. The underfill312protects the connectors308between the integrated circuit306and the base310from moisture or contamination and provides protection from thermal and physical related stress to the connectors308, the integrated circuit306, and the base310.

Underfill non-horizontal sides314of the underfill312can be surrounded by the encapsulation302. The underfill non-horizontal sides314can preferably be coplanar with edges316of the integrated circuit306.

A side of the underfill312facing the integrated circuit306can be in direct physical contact with the integrated circuit306. A side of the underfill312opposite the side facing the integrated circuit306can be in direct physical contact with the base310. The underfill non-horizontal sides314and the edges316of the integrated circuit306can preferably be covered by the encapsulation302. The underfill312can be substantially free of voids1308ofFIG. 13.

The base310can preferably include a routing trace318and a film layer320. The routing trace318can be formed from a conductive material such as gold, copper, aluminum, or any combination of electrically conductive material. The routing trace318can be used to provide connection paths within the base310and at a first side322or a second side324of the base310.

The film layer320, such as a passivation film layer or similar layer providing no conductivity, can be applied over or surround the routing trace318in multiple successive layers of the base310. The film layer320can also include materials, such as a resistive material or a dielectric material, which can applied over or surround portions of one or more of the routing trace318within the base310. The base310can preferably be formed of multiple layers of the film layer320and of the routing trace318resulting in improved routing density capabilities.

For purposes of illustration, the integrated circuit packaging system300is shown having the routing trace318formed within a single horizontal plane located in the base310. It is understood that the integrated circuit packaging system300can have the routing trace318configured differently. For example the routing trace318could be distributed within several different horizontal planes, each coplanar with one another and each separated by the film layer320. Furthermore, the routing trace318within a horizontal plane can have different connective path attributes from another of the routing trace318within a different horizontal plane.

The film layer320, the routing trace318, or a combination thereof can be selectively formed or configured in the base310to form a passive circuit330, such as a film resistor, a film capacitor, or a film inductor. As an example, the passive circuit330is shown as a portion of the base310with the portion of the film layer320and the routing trace318connecting two stack interconnects326. This example can show the passive circuit330as a film inductor.

Stack interconnectors326, such as bump pads, pillars, stacked stud bumps, contact pads, or connective contacts having connective compatibility with the connectors308, can be attached to the routing trace318adjacent the first side322. The connectors308can be connected over the stack interconnectors326to provide connectivity between the integrated circuit306and the base310. System connectors328, such as conductive balls, columns, posts, or pins, can be coupled to the routing trace318from the second side324of the base310.

Referring now toFIG. 4, therein is shown the cross-sectional view of a forming phase of a sacrificial carrier assembly for the manufacturing of the integrated circuit packaging system100ofFIG. 2. The stack interconnectors222can preferably be attached or formed along an attachment side402of the sacrificial carrier assembly404at predefined locations based on the positions of the connectors204ofFIG. 2. The sacrificial carrier assembly404can be a wafer, a board, a strip, or a substrate. Build sites406, located over the sacrificial carrier assembly404, can be used to assemble and produce the integrated circuit packaging system100.

For purposes of illustration, four of the build sites406are shown. It is understood that the sacrificial carrier assembly404can have a different configuration. For example, the sacrificial carrier assembly404can be configured to support one, two, five, twelve, or any number of the build sites406.

Furthermore, each of the build sites406can have different configurations of the stack interconnectors222. For example, one of the build sites406can have fewer of the stack interconnectors222when compared with another of the build sites406of the sacrificial carrier assembly404.

Referring now toFIG. 5, therein is shown the structure ofFIG. 4in a connecting phase of the integrated circuit202to the sacrificial carrier assembly404. The connectors204of the integrated circuit202can be located over and connected with the stack interconnectors222. This process can optionally be replicated over any of the build sites406populated with the stack interconnectors222as needed.

For purposes of illustration, the build sites406are shown each being assembled with one of many previously tested good units of the integrated circuit202. It is understood that the stack interconnectors222of any of the build sites406can be assembled and connected to components, such as active components, passive components, or combinations thereof having provisions capable of connecting with the stack interconnectors222.

Referring now toFIG. 6, therein is shown the structure ofFIG. 5in a dispensing and curing phase of an underfill material606. The side of the sacrificial carrier assembly404opposite the attachment side402of the sacrificial carrier assembly404can be vacuum mounted or mounted using a temporary adhesive onto a platform fixture602.

While drawings of underfill material for integrated circuits generally do not show voids in the underfill, voids are a universal problem. It has been discovered that by using spin deposition or providing release paths or vents for the underfill208, as will later be described, that the underfill208itself can be substantially free of the voids607, such as cavities, crevices, holes, cracks, or regions absent of the underfill208. This elimination of the voids607can be determined by the reduction or elimination of cracks in the integrated circuit202. The underfill208being free of the voids607further reduces or eliminates delamination of the underfill208from the integrated circuit202. Thus, it has been found that the reduction or elimination of the voids607in the underfill208improves the reliability of the integrated circuit packaging system100.

The platform fixture602can be rotated around a central axis604located centrally to and perpendicular with the attachment side402of the sacrificial carrier assembly404. The platform fixture602and the underfill material606, such as an adhesive, an epoxy, or an encapsulant, can optionally be heated using a method such as a contact, a convective, or an infrared heating method.

The underfill material606can be dispensed above the central axis604between the build sites406located closest to the central axis604. Centrifugal force from the rotation of the platform fixture602applied to the underfill material606is used to distribute the underfill material606horizontally along an interior area608of the integrated circuit202over each of the build sites406.

The rate of horizontal distribution of the underfill material606can be controlled by the speed of rotation of the platform fixture602. For example, increasing the speed of rotation of the platform fixture602will increase the rate of horizontal movement of the underfill material606and slowing the speed of rotation of the platform fixture602will decrease the horizontal movement of the underfill material606.

The interior area608, located between the integrated circuit202and the attachment side402of the sacrificial carrier assembly404, having the connectors204and the stack interconnectors222, can be filled with the underfill material606at a rate determined by the dispersal rate of the underfill material606. For example, increasing the dispersal rate of the underfill material606will increase the filling rate of the underfill material606into the interior area608and decreasing the dispersal rate of the underfill material606will decrease the filling rate of the underfill material606into the interior area608.

Varying the speed and duration of rotation of the platform fixture602, along with the dispersal rate of the underfill material606, applies the underfill material606uniformly and substantially free of the voids607such as cavities, crevices, holes, cracks, or regions absent of the underfill material606. The underfill material606in contact with the integrated circuit202, the conductors204, the stack interconnectors222, and the attachment side402are substantially free from the voids607.

It has been discovered that the present invention provides the integrated circuit packaging system substantially free of voids607in the underfill material. Moving the underfill process with rotational application substantially eliminates the voids607in the underfill material between the integrated circuit and the sacrificial carrier assembly.

It has also been discovered that the present invention provides the integrated circuit packaging system with a gap610between the integrated circuit and the sacrificial carrier assembly404. The elimination of the voids607allows the reduction of the size of the gap610. The reduction allows for finer pitch and higher input/output density of the system connectors308ofFIG. 3. The gap610can also represents the space between the integrated circuit and the base ofFIG. 2.

Further, it has been discovered that the present invention provides the integrated circuit packaging system with substantially increased functionality capabilities. The capability of accommodating the conductors204with finer pitches and increasing the quantity of the conductors204results in increased functionality as a result of the gains in connectivity capabilities. Substantial improvements in functionality are most pronounced with large die sizes.

It has been found that the present invention provides the integrated circuit packaging system with improved manufacturing productivity. Moving the underfill process earlier closer to the front end of the line, as is done with the present invention, can be much more efficient and cost effective over a back end of the line underfill processing, such as waiting until the package to board integration step before proceeding with the underfill process.

The rotations of the platform fixture602is suspended and the underfill material606is allowed to settle, spread, uniformly distribute, and adhere without the voids607to any surface in contact with the underfill material606as part of the curing phase. In at least one embodiment, the underfill material606can include a substantially uniform distribution over the entirety of the sacrificial carrier assembly404or across each of the integrated circuit packaging system100, ofFIG. 1.

Referring now toFIG. 7, therein is shown the structure ofFIG. 6in an encapsulating phase. The underfill material606and perimeter edges702of the underfill material606can optionally be conditioned, such as with a sanding, a sawing, or a grinding process, to have any dimensions or shape that may be required of a molding fixture used during the encapsulating phase.

An encapsulant704, such as an epoxy, silicone, or polymide based compound, can be applied over the underfill material606and over the integrated circuit202in the molding fixture (not shown). The molding fixture can be removed and the encapsulant704can be allowed to cure using a process such as a curing process.

Referring now toFIG. 8, therein is shown the structure ofFIG. 7in a removal phase of the sacrificial carrier assembly404ofFIG. 7. The structure ofFIG. 8is shown inverted and without the sacrificial carrier assembly404ofFIG. 7.

The sacrificial carrier assembly404was removed using a removal process, such as a grinding, a sanding, a cutting, an etching, or a mechanical peeling process, resulting in the stack interconnectors222substantially exposed from the underfill material606or the underfill material606formed having a substantially flat surface. The underfill material606and the encapsulant704can provide the integrated circuit202with the structural support previously provided using the sacrificial carrier assembly404

Referring now toFIG. 9, therein is shown the structure ofFIG. 8in a connecting phase of the system connector224. A base array902, such as a non-laminated redistribution structure, can be formed with the routing trace214and the film layer216. The routing trace214can preferably be layered over the stack interconnectors222of each of the build sites406with the film layer216formed over the routing trace214.

Portions of the film layer216can optionally include resistive materials or dielectric materials which can be applied between and surround portions of one or more of the routing trace214of each of the build sites406to form isolated film resistors or isolated film capacitors. The system connectors224can be attached to the routing trace214exposed adjacent the film layer216of each of the build sites406.

Referring now toFIG. 10, therein is shown the structure ofFIG. 9in a singulating phase. The structure ofFIG. 10is inverted relative to the structure ofFIG. 9and singulated, such as a cutting process or a sawing process, between each of the build sites406resulting in the formation of multiple units of the integrated circuit packaging system100ofFIG. 2and formation of the base206from the base array902ofFIG. 9.

Referring now toFIG. 11, therein is the cross-sectional view of a forming phase of a sacrificial carrier assembly for the manufacturing of the integrated circuit packaging system300ofFIG. 3. The sacrificial carrier assembly1102, such as a wafer, a board, a strip, or a substrate, can preferably include spacer sections1104and joiner sections1106. Each of the spacer sections1104include a spacer attach side1108and each of the joiner sections1106include a joiner attach side1110.

The spacer attach side1108of each of the spacer sections1104can be oriented within a common horizontal plane. The spacer sections1104can each be individually positioned adjacent one another to form a cluster group1112. The joiner attach side1110of each of the joiner sections1106can be oriented within the common horizontal plane and each of the joiner sections1106can positioned adjacent and between pairs of the cluster group1112. The spacer sections1104and the joiner sections1106of the sacrificial carrier assembly1102can be optionally held in their respective positions to prevent movement using a fixture (not shown), such as a vacuum platform or a mechanical jig assembly.

The stack interconnectors326can preferably be attached along the spacer attach side1108. The stack interconnectors326can also be attached to the joiner attach side1110next to each end of each of the joiner sections1106facing an end of the cluster group1112.

Build sites1114, having the stack interconnectors326of the cluster group1112and the stack interconnectors326from ends of the joiner sections1106closest to the cluster group1112, can be used to assemble and produce the integrated circuit packaging system300.

For purposes of illustration, four of the build sites1114are shown. It is understood that the sacrificial carrier assembly1102can have a different configuration. For example, the sacrificial carrier assembly1102can be configured to support one, two, five, twelve, or any number of the build sites1114. Furthermore, each of the build sites1114can have different configurations of the stack interconnectors326. For example, the quantity or spacing of the spacer sections1104can be increased, decreased, or variable within the cluster group1112of any of the build sites1114.

Referring now toFIG. 12, therein is shown the structure ofFIG. 11in a connecting phase of the integrated circuit to the sacrificial carrier assembly1102. The connectors308of the integrated circuit306can be located over and connected with the stack interconnectors326. This process can optionally be replicated over any of the build sites1114populated with the stack interconnectors326as needed.

For purposes of illustration, the build sites1114are shown each being assembled with one of many previously tested good units of the integrated circuit306. It is understood that the stack interconnectors326of any of the build sites1114can be assembled and connected to components, such as active components, passive components, or combinations thereof, having provisions capable of connecting with the stack interconnectors326.

Referring now toFIG. 13, therein is shown the structure ofFIG. 12a dispensing and curing phase of an underfill material1302. The structure ofFIG. 13is inverted from the orientation shown inFIG. 12and the build sites1114and the underfill material1302, such as an adhesive, an epoxy, or an encapsulant, can optionally be heated using a method such as a contact, a convective, or an infrared heating method.

At each of the build sites1114, the underfill material1302can be dispensed either between two of the spacer sections1104directly facing one another or between one of the spacer sections1104directly facing the joiner sections1106. The underfill material1302can be applied from the sides of the spacer sections1104and the joiner sections1106opposite the sides facing the integrated circuit306. The dispensing of the underfill material1302can be performed simultaneously over several of the build sites1114to reduce manufacturing assembly time.

The underfill material1302can be applied over the sacrificial carrier assembly1102to each of the build sites1114, to accumulate, and to fill an interior area1304of the integrated circuit306. The interior area1304is dimensionally bounded horizontally by a perimeter defined by spread of each of the build sites1114and bounded vertically by the integrated circuit306and the spacer attach side1108and the joiner attach side1110of the each of the build sites1114.

Non-dispensed areas1306, such as between the spacer sections1104and between the spacer sections1104facing the joiner sections1106, not used to dispense the underfill material1302into, can serve as release paths, such as an air releasing vent, an overflow for the underfill material1302, or as a port for a negative pressure source.

The non-dispensed areas1306can ensure an application of the underfill material1302surrounds the conductors308and the stack interconnectors326. The application of the underfill material1302results in substantially none of the voids1308within the underfill material1302and results in the underfill material1302in contact with the integrated circuit306, the spacer attach side1108, the joiner attach side1110, the conductors308, and the stack interconnectors326to be free from any of the voids1308.

The underfill material1302is allowed to settle, spread, uniformly distribute, and adhere without the voids1308to any surface in contact with the underfill material1302as part of the curing phase.

Referring now toFIG. 14, therein is shown the structure ofFIG. 13in an encapsulating phase. The structure ofFIG. 13is inverted and perimeter edges1402of the underfill material1302can optionally be conditioned, such as with a sanding, a sawing, etching, or a grinding process, to have any dimensions or shape that may be required of a molding fixture used during the encapsulating phase.

An encapsulant1404, such as an epoxy, silicone, or polymide based compound, can be applied over the integrated circuit306in the molding fixture and surround the perimeter edges1402. The molding fixture can be removed and the encapsulant1404can be allowed to cure using a process such as a curing process.

Referring now toFIG. 15, therein is shown the structure ofFIG. 14in a removal phase of the sacrificial carrier assembly1102ofFIG. 14. The structure ofFIG. 14is shown inverted and without the sacrificial carrier assembly1102. The sacrificial carrier assembly1102can be removed using a removal process such as a grinding, a sanding, a cutting, or an etching process, resulting in the stack interconnectors326substantially exposed of from the underfill material1302. The underfill material1302and the encapsulant1404can provide the integrated circuit306with the structural support previously provided using the sacrificial carrier assembly1102.

Referring now toFIG. 16, therein is shown the structure ofFIG. 15in a connecting phase of the system connector328. A base array1602, such as a non-laminated redistribution structure, can be formed using the routing trace318and the film layer320. The routing trace318can preferably be layered over the stack interconnectors326of each of the build sites1114with the film layer320formed over the routing trace318.

Portions of the film layer320can optionally be include resistive materials or dielectric materials which can be applied between and surround portions of one or more of the routing trace318of each of the build sites1114to form isolated film resistors or isolated film capacitors. The system connectors328can be attached to the routing trace318exposed adjacent the film layer320of each of the build sites1114.

Referring now toFIG. 17, therein is shown the structure ofFIG. 16in a singulating phase. The structure ofFIG. 16is inverted and singulated using a process such as a cutting process or a sawing process, between each of the build sites1114resulting in the formation of multiple units of the integrated circuit packaging system300and formation of the base310from the base array1602ofFIG. 12.

Referring now toFIG. 18, therein is shown a flow chart of a method1800of manufacture of an integrated circuit packaging system100in a further embodiment of the present invention. The method1800includes providing a sacrificial carrier assembly having a stack interconnector thereover in a block1802; mounting an integrated circuit having a connector over the sacrificial carrier assembly with the connector over the stack interconnector in a block1804; dispensing an underfill material between the sacrificial carrier assembly and the integrated circuit with the underfill material substantially free of a void in a block1806; encapsulating the integrated circuit over the sacrificial carrier assembly and the underfill material in a block1808; exposing the stack interconnector by removing the sacrificial carrier assembly in a block1810; and forming a base array over the underfill material and the stack interconnector in a block1812.

The resulting method, process, apparatus, device, product, and/or system is straightforward, cost-effective, uncomplicated, highly versatile and effective, can be surprisingly and unobviously implemented by adapting known technologies, and are thus readily suited for efficiently and economically manufacturing package on package systems/fully compatible with conventional manufacturing methods or processes and technologies.