Methods and apparatus for inductors with integrated passive and active elements

An integrated circuit is described. The integrated circuit includes an inductor that has a large empty area in the center of the inductor. The integrated circuit also includes additional circuitry. The additional circuitry is located within the large empty area in the center of the inductor. The additional circuitry may include a capacitor bank, transistors, electrostatic discharge (ESD) protection circuitry and other miscellaneous passive or active circuits.

TECHNICAL FIELD

The present disclosure relates generally to communication systems. More specifically, the present disclosure relates to methods and apparatus for inductors with integrated passive and active elements.

BACKGROUND

Wireless communication systems are widely deployed to provide various types of communication content such as voice, video, data, and so on. These systems may be multiple-access systems capable of supporting simultaneous communication of multiple terminals with one or more base stations.

A terminal or a base station may include one or more integrated circuits. These integrated circuits may include analog and digital circuitry necessary for wireless communication. Such circuitry may include inductors. As the technology used to build integrated circuits progresses, active elements on the integrated circuit such as transistors continue to decrease in size. Passive elements on the integrated circuit may not decrease in size relative to the active elements. Therefore, integrated circuits built with progressive technology may require increasing percentages of area on the integrated circuit for passive elements. To decrease production costs and save area, active elements may be built under the passive elements on an integrated circuit.

SUMMARY

An integrated circuit is described. The integrated circuit includes an inductor and additional circuitry. The inductor has an empty area in the center of the inductor. The additional circuitry is located within the empty area in the center of the inductor.

In various configurations, the additional circuitry may include a capacitor bank, a tuning capacitor, a supply voltage pad, a resistor capacitor (RC) clamp, a ground pad, an electrostatic discharge (ESD) pad or electrostatic discharge (ESD) protection circuitry. Furthermore, the additional circuitry may include at least one of transistors, memory, switches, additional inductors, active circuit blocks and passive circuit blocks.

The inductor may be part of any circuit that requires an inductor. As one possible example, the inductor may be a tank inductor that is part of a voltage controlled oscillator (VCO) or a low noise amplifier (LNA). In a further example, the inductor may be a degeneration inductor that is part of a low noise amplifier (LNA).

In another configuration, the inductor may be a balun. The additional circuitry may include at least one of input tuning capacitors, output tuning capacitors, a ground pad, a supply pad, and electrostatic discharge (ESD) protection structures for the supply pad.

The inductance and quality factor (Q) of the inductor may not be negatively affected by the additional circuitry. The inductor and the additional circuitry may be located on the same layer of the integrated circuit.

A method for providing circuitry within an inductor is also described. An inductor on an integrated circuit is provided. Additional circuitry is provided within the inductor. Interaction between the inductor and the circuitry is optimized.

An apparatus for providing circuitry within an inductor is also disclosed. The apparatus includes means for providing an inductor on an integrated circuit and means for providing additional circuitry within the inductor. The apparatus also includes means for optimizing interaction between the inductor and the circuitry.

Another integrated circuit is also disclosed. The integrated circuit includes an inductor and additional circuitry. The additional circuitry is located underneath the inductor, and the inductor may be a choke inductor.

The choke inductor may be part of a voltage controlled oscillator (VCO). The inductor may have minimal capacitive coupling. The additional circuitry may include transistors or capacitors. Additionally, the additional circuitry may include a mid voltage generator for voltage controlled oscillator (VCO) calibration.

DETAILED DESCRIPTION

FIG. 1shows an integrated circuit102with multiple components including an inductor104and additional circuitry106. The integrated circuit102may be designed for use in a wireless device such as a base station, a mobile device, or the like. A base station may also be referred to as, and may include some or all of the functionality of, an access point, a broadcast transmitter, a Node B, an evolved Node B, etc. Each base station provides communication coverage for a particular geographic area. The term “cell” can refer to a base station and/or its coverage area depending on the context in which the term is used.

A mobile device may also be referred to as, and may include some or all of the functionality of, a terminal, an access terminal, a user equipment (UE), a subscriber unit, a station, etc. A mobile device may be a cellular phone, a personal digital assistant (PDA), a wireless device, a wireless modem, a handheld device, a laptop computer, etc. A mobile device may communicate with zero, one, or multiple base stations on the downlink (DL) and/or uplink (UL) at any given moment. The downlink (or forward link) refers to the communication link from a base station to the mobile device, and the uplink (or reverse link) refers to the communication link from the mobile device to the base station.

The integrated circuit102may include an inductor104. Many different designs for the inductor104may be used. In one configuration, the inductor104may use a symmetric design. Alternatively, as shown inFIG. 4below, the inductor104may use an asymmetric spiraling design. As illustrated inFIG. 7below, the inductor104may be designed using multiple loops. Inductors104may help low-voltage designed circuits for deep sub-micron technology. Examples of deep sub-micron technology include 65 nanometer (nm), 45 nm, 32 nm and 28 nm technology. However, in deep sub-micron technology, an inductor104may become very expensive, due to the large area used by such an inductor104. Because an inductor104is a passive circuit, the size of the inductor104may not scale with the technology size used. Thus, in deep sub-micron technology, an inductor104will occupy larger chip area on an integrated circuit102.

An inductor104on an integrated circuit102may have a large empty area in the center of the inductor104due to design constraints. For example, a voltage controlled oscillator (VCO) tank inductor104may only have a few turns (or revolutions) to maximize the quality factor (Q) of the inductor, thereby leaving an empty space in the center of the inductor104large enough for additional circuitry106. The large empty area may be suitable for placing additional circuitry106on the integrated circuit102. The additional circuitry106may include passive elements (such as inductors, capacitors, and resistors). The additional circuitry106may also include active elements (such as transistors). The additional circuitry106may create inductive coupling through inductors104and lines. The additional circuitry106may also create capacitive coupling through parasitic capacitance. The additional circuitry106may reduce resistive (substrate) coupling from an inductor104because the inductor104does not see the substrate due to the circuit in between. To reduce this substrate coupling, the doping profile for certain substrate regions may be changed. The substrate coupling may also be reduced by adding guard rings and other substrate ground connections.

The additional circuitry106within the inductor may be arranged such that the inductance and Q of the inductor104are not significantly impacted. For example, the additional circuitry106may need to be placed in the center of the inductor104where the magnetic field is the weakest. Enough distance between the additional circuitry106and inductor104may be required to allow the magnetic field to pass through. Closed loop routings may be avoided in the additional circuitry106placed within the inductor104. The interaction between the inductor104and the additional circuitry106may be optimized. For example, the lines that route across the inductor104may be perpendicular to the inductor104to minimize the coupling.

FIG. 2illustrates an integrated circuit layout202for a capacitor bank206within an inductor204. A large empty space within the inductor204may be available for additional circuitry106. InFIG. 2, the large empty space within the inductor204has been filled with a capacitor bank206. A capacitor bank206may be useful in circuitry such as that for a VCO. A VCO inductor204may require an accurate inductance value (L) and Q.

The linearity of the capacitor bank206within the inductor204may be very similar to the linearity of the capacitor bank206outside of the inductor204. Thus, placing the capacitor bank206on the inside of the inductor204does not affect the linearity of the capacitor bank206. Production for an integrated circuit202with a capacitor bank206within an inductor204may thus be realized because the capacitor bank206linearity is not affected by the location of the capacitor bank206. If the inductor204with an internal capacitor bank206is used in a VCO, the VCO phase noise at 900 kilohertz (kHz) may be degraded by ˜2 decibels (dB).

The layout design of the inductor204may be optimized based on three dimensional (3D) electromagnetic simulation results. In one configuration, the optimization may result in a stretched coil design, wherein the inductor204coils are stretched out. For example, the inductor204coils parallel to the corners of the capacitor bank206may each be stretched outward from the capacitor bank206. The stretched coil design may create an inductor204with a higher Q factor when circuitry106is placed within the inductor204. The capacitor bank206may have a control bus209. For example, the control bus209may include the serial bus interface (SBI) signals that are used to turn on and off the switches to control the total capacitance of the capacitor bank206.

FIG. 3illustrates an alternative integrated circuit layout302for a capacitor bank306within an inductor304. The inductor204design ofFIG. 2may suffer from negative coupling due to the inductor204geometry. In the inductor204design ofFIG. 2, interaction between the inductor204coil and the capacitor bank206may result in current crowding. The inductor304design ofFIG. 3may minimize the negative coupling between the inductor304line. Furthermore, the inductor304design ofFIG. 3may have a larger keep out between the inductor304coil and the capacitor bank306. The inductor304design ofFIG. 3may use a capacitor bank306without a dense layout. The capacitor bank306may have a control bus309.

FIG. 4illustrates an integrated circuit402layout for additional circuitry412placed underneath an inductor410. The inductor410and additional circuitry412may be part of a VCO. In one configuration, the inductor410may be a choke inductor410. A choke inductor410may tolerate a lower Q and a larger L variation. A choke inductor410may have a large L such as between 2 and 20 nanoHenry (nH). A choke inductor410may also have a small L such as less than 2 nH. The additional circuitry412may include transistors, capacitors, etc. on different layers of the integrated circuit402than the inductor410coil. In one configuration, the additional circuitry412placed underneath the inductor410may be a mid voltage generator for VCO calibration. The mid voltage generator is powered down after VCO calibration.

The goal of putting the inductor410over the blocks of additional circuitry412is to save area on the integrated circuit402while minimizing the Q degradation due to the coupling to other blocks. The integrated circuit402layout ofFIG. 4may be used for a VCO choke inductor410. A VCO choke inductor410is smaller and less sensitive to inductance and Q than other inductors (such as the VCO tank inductor). Thus, the VCO choke inductor410is suitable to be placed on top of other blocks. Placing additional circuitry412underneath the choke inductor410may not affect VCO performance. The choke inductor410may be placed over active circuitry412without a keep out and ground ring. Capacitive coupling may also be minimized.

FIG. 5illustrates an integrated circuit502layout for portions of a receiving (RX) voltage controlled oscillator (VCO). The RX VCO may include a tank inductor504. The RX VCO may also include a capacitor bank506located within the tank inductor504. The RX VCO may also include a choke inductor510. The RX VCO may further include a mid voltage generator512for VCO calibration located underneath the choke inductor510.

FIG. 6is a circuit diagram illustrating a low noise amplifier (LNA)600. The LNA600may include a tank inductor portion614. In one configuration, the tank inductor portion614may include a first inductor620aand a second inductor620b. Each of the two inductors620may be attached to VDD638and to each side of a capacitor Ctune622. The tank inductor portion614may include a VDD638pad.

The LNA600may also include an LNA core portion616attached to inputs InP628aand InM628bof the LNA600. The input InP628amay be connected to a resistor630aconnected to a first bias voltage Vb1632. The input InP628amay also be connected to the gate of a first negative metal-oxide-semiconductor (NMOS) field-effect transistor626a. The substrate of the first NMOS transistor626amay be connected to the source of the first NMOS transistor626a. The drain of the first NMOS transistor626amay be connected to the source of a second NMOS transistor626b. The gate of the second NMOS transistor626bmay be connected to a second bias voltage Vb2634. The drain of the second NMOS transistor626bmay be connected to an output624of the LNA600, the first inductor620a, and the capacitor622.

The input InM628bmay be connected to a resistor630bconnected to Vb1632. The input InM628bmay also be connected to the gate of a third NMOS transistor626c. The substrate of the third NMOS transistor626cmay be connected to the source of the third NMOS transistor626c. The drain of the third NMOS transistor626cmay be connected to the source of a fourth NMOS transistor626d. The gate of the fourth NMOS transistor626dmay be connected to Vb2634. The drain of the fourth NMOS transistor626dmay be connected to an output624of the LNA600, the second inductor620b, and the capacitor622.

The LNA600may further include a Degeneration inductor portion618. In one configuration, the Degeneration inductor portion618of the LNA600may include a third inductor636aand a fourth inductor636b. The LNA Degeneration inductors636may need an accurate L and Q. Thus, a keep out may be placed under the coil of an LNA Degeneration inductor636. The keep out may keep current crowding to a minimum. The third inductor636amay be connected to the source of the first NMOS transistor626aand to ground (GND)640. The fourth inductor636bmay be connected to the source of the third NMOS transistor626band to GND640. The Degeneration inductor portion618may also include a resistor-capacitor (RC) clamp642. The RC clamp642may be ESD protection circuitry used to protect the circuitry from electrostatic charge damage. Additional ESD protection circuitry/devices and other non-critical circuits may be used under inductors636. The additional ESD protection circuitry/devices and other non-critical circuits may be powered off when critical RF circuits are operating. The Degeneration inductor portion618may include ground640pads.

FIG. 7illustrates an integrated circuit702layout for a tank inductor portion614of an LNA600. The integrated circuit702layout ofFIG. 7may be one layout for the tank inductor portion614ofFIG. 6. The integrated circuit702layout may include an inductor720with a large empty space inside of the inductor720. A guard ring721may be placed around the inductor720. A VDD pad738may be placed inside the large empty space of the inductor720. A center tap723may be connected to the VDD pad738. The inductor720may have a plus terminal and a minus terminal in addition to the center tap723. Routing lines722may be used to cross the inductor720and connect to the VDD pad738.

FIG. 8illustrates an integrated circuit802layout for a tank inductor820with a capacitor bank839as part of an LNA600. The integrated circuit802layout ofFIG. 8may be one spatial layout for the tank inductor portion614of the LNA600ofFIG. 6. The capacitor bank839may be placed within the tank inductor820. A VDD pad838may also be placed within the tank inductor820. A center tap823may be connected to the VDD pad838. The inductor820may have a plus terminal and a minus terminal in addition to the center tap823. Routing lines822may be used to cross the inductor820to provide a connection to the LNA600while routing across the inductor to reach the mixer.

FIG. 9illustrates an integrated circuit902layout for a Degeneration inductor portion618of an LNA600. The integrated circuit902layout ofFIG. 9may be one layout for the Degeneration inductor portion618ofFIG. 6. The integrated circuit602layout may include an inductor936with a large empty space inside the inductor936. A ground (GND) pad951may be placed inside the large empty space of the inductor936. Other package pads (not shown) such as an ESD pad or a supply pad may also be placed inside the large empty space of the inductor936. A center tap923may be connected to the ground pad951.

FIG. 10illustrates another integrated circuit1002layout for a Degeneration inductor portion618of an LNA600. The integrated circuit1002layout may include one or more Degeneration inductors1041. In one configuration, a first Degeneration inductor1041amay include a second Degeneration inductor1041bwithin a large empty space inside of the first Degeneration inductor1041a. An empty space may be included within the second Degeneration inductor1041b. Within the empty space of the second Degeneration inductor1041b, an electrostatic discharge (ESD) pad1040may be placed. ESD lines1042may also be placed on the integrated circuit1002layout.

FIG. 11is a circuit diagram of an upconverter1100for use in a radio frequency (RF) chip. The upconverter1100may include an upconverter core1152. The upconverter core1152may receive baseband I/Q inputs1144and LO I/Q inputs1150. The upconverter1100in an RF chip may require a balun1156to convert differential signals to a single ended output1162. The upconverter1100may also require several tuning elements. Typically, the tuning elements may include tunable input capacitors1146and tunable output capacitors1160. Practical RF chips may need to accommodate pad structures that deliver power from outside the die to the upconverter1100circuit (supply pad1154) and also provide a ground connection (ground pad1158) to the die.

The balun1156is an electromagnetic structure constructed by having coils of metal wound around a periphery. The center of the coil winding may be left empty. This empty area is wasteful, particularly for the finer complementary metal-oxide-semiconductor (CMOS) technologies, where the die cost is much higher. By using the empty area, the cost of RF chips constructed in fine CMOS technologies may be lowered. The empty area may be filled with elements such as the input tuning capacitors1146, the output tuning capacitors1160, a ground pad1158, a supply pad1154, and ESD protection structures1148for the supply pad1154.

FIG. 12illustrates the spatial location1200of a balun1256with tunable input capacitors1246within the balun1256. The balun1256may be created by winding metal coils1264. The tunable input capacitors1246may be placed in the empty space at the center of the balun1256metal coils1264. The balun1256may receive an input1266from the upconverter core1152. The balun1256may also be connected to a supply pad1254and to a ground pad1258. The balun1256may further be connected to an output1262. The placement of the tunable input capacitors1246within the balun1256may be such that the tunable input capacitors1246and the balun1256do not negatively affect each other.

FIG. 13illustrates another spatial layout1302of a balun1356with tunable input capacitors1346within the balun1356. The tunable input capacitors1356may be located on the same layer as the balun1356. Because the balun1356is constructed using coils of metal wound around a periphery, the tunable input capacitors1346may be placed within the balun1356. As discussed above, other circuitry in addition to or in place of tunable input capacitors1346may be placed within the balun1356. For example, tunable output capacitors1146, a ground pad1158, a supply pad1154, or an ESD protection structure1148for the supply pad1154may be placed within the balun1356. The circuitry within the balun1356may be arranged such that the inductance and Q of the balun1356are not negatively impacted.

A 3-D EM solver indicates that the balun1356performance including inductance, Q, resonance, and coupling factor are almost unchanged with the addition of the circuitry. A 3-D EM solver setup of the balun1356on an integrated circuit with a capacitor bank placed within the balun1356indicates that a capacitor bank may be placed within the balun1356without negatively affecting the performance of the balun1356or the capacitor bank. The capacitor bank may be placed on the same layer as the balun1356.

FIG. 14is a flow diagram of a method1400for providing circuitry106within an inductor104on an integrated circuit102. An inductor104may be provided1402on an integrated circuit102. Circuitry106may be provided1404within the inductor104. The interaction between the inductor104and the circuitry106may then be optimized1406.

FIG. 16illustrates certain components that may be included within a wireless device1601. The wireless device1601may be a mobile device or a base station and may implement the present systems and methods as disclosed herein.

The wireless device1601includes a processor1603. The processor1603may be a general purpose single- or multi-chip microprocessor (e.g., an ARM), a special purpose microprocessor (e.g., a digital signal processor (DSP)), a microcontroller, a programmable gate array, etc. The processor1603may be referred to as a central processing unit (CPU). Although just a single processor1603is shown in the wireless device1601ofFIG. 16, in an alternative configuration, a combination of processors (e.g., an ARM and DSP) could be used.

The wireless device1601also includes memory1605. The memory1605may be any electronic component capable of storing electronic information. The memory1605may be embodied as random access memory (RAM), read only memory (ROM), magnetic disk storage media, optical storage media, flash memory devices in RAM, on-board memory included with the processor, EPROM memory, EEPROM memory, registers, and so forth, including combinations thereof.

Data1607and instructions1609may be stored in the memory1605. The instructions1609may be executable by the processor1603to implement the methods disclosed herein. Executing the instructions1609may involve the use of the data1607that is stored in the memory1605. When the processor1603executes the instructions1607, various portions of the instructions1607amay be loaded onto the processor1603, and various pieces of data1609amay be loaded onto the processor1603.

The wireless device1601may also include a transmitter1611and a receiver1613to allow transmission and reception of signals to and from the wireless device1601. The transmitter1611and receiver1613may be collectively referred to as a transceiver1615. An antenna1617may be electrically coupled to the transceiver1615. The wireless device1601may also include multiple transmitters, multiple receivers, multiple transceivers and/or multiple antennas (not shown).

The various components of the wireless device1601may be coupled together by one or more buses, which may include a power bus, a control signal bus, a status signal bus, a data bus, etc. For the sake of clarity, the various buses are illustrated inFIG. 16as a bus system1619.