Electrostatic discharge protection circuits

An electrostatic discharge (ESD) protection circuit is provided. A transistor is coupled between a node and a ground, and has a gate coupled to the ground. A diode chain is coupled between the node and a pad, and comprises a plurality of first diodes connected in series, wherein the first diode is coupled in a forward conduction direction from the pad to the node. A second diode is coupled between the node and the pad, and the second diode is coupled in a forward conduction direction from the node to the pad.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to an electrostatic discharge (ESD) protection, and more particularly to an ESD protection of a high voltage pin for a low voltage process.

2. Description of the Related Art

Electrostatic discharge phenomenon will cause damage to semiconductor devices and affect normal functioning of integrate circuits (IC). Thus, it is necessary goal for IC designers during the design stage to enhance ESD protection of an IC to increase ESD sensitivity.

Recently, more and more ICs can operate with lower operating voltages, such as operating voltages of typical logic circuits, i.e. 5V, 3.3V, 2.5V and 1.8V etc., due to rapid advancement of low voltage (LV) manufacturing technology. However, for certain products which have particular application requirements, certain pins for an IC require operating at higher voltages, i.e. 7V, 8V, 9V and so on. Voltage substantially greater than 5V but not belonging to a typical high voltage (HV) range, is medium voltage (MV).

For ICs, malfunction will occur in LV devices when an MV is applied to the LV devices. In this situation, the LV device functions will be false since the LV ESD protection circuit is unable to protect pins operated at MV. Therefore, an MV ESD protection circuit for LV processes is needed.

BRIEF SUMMARY OF THE INVENTION

The invention discloses an electrostatic discharge (ESD) protection circuit comprising: a transistor coupled between a node and a ground, having a gate coupled to the ground; a diode chain coupled between the node and a pad, comprising a plurality of first diodes connected in series, and the first diode is coupled in a forward conduction direction from the pad to the node; and a second diode coupled between the node and the pad, and the second diode is coupled in a forward conduction direction from the node to the pad.

In addition, the invention discloses an electrostatic discharge (ESD) protection circuit comprising: an N-type transistor coupled between a node and a ground, having a gate coupled to the ground; a first diode having a first anode and a first cathode, the first anode is coupled to a pad; a second diode having a second anode and a second cathode, the second anode is coupled to the first cathode and the second cathode is coupled to the node; and a third diode having a third anode and a third cathode, the third anode is coupled to the node and the third cathode is coupled to the pad.

Moreover, the invention discloses an electrostatic discharge (ESD) protection circuit comprising: a transistor coupled between a node and a ground, having a gate coupled to the ground; a diode chain coupled between the node and a pad, comprising a plurality of first diodes connected in series; and a second diode coupled between the node and the pad. The first diode is conducted in a forward direction from the pad to the node when a first voltage of the pad is greater than a second voltage of the node, and the second diode is conducted in a forward direction from the node to the pad when the second voltage is greater than the first voltage.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1shows an ESD protection circuit100according to an embodiment of the invention. The ESD protection circuit100comprises a pad10, a diode chain20, a diode30, and a transistor40. The pad10is coupled to a pin which receives a medium voltage signal. The diode chain20is composed of four diodes22,24,26and28connected in series, wherein an anode of the diode22is coupled to the pad10, a cathode of the diode22is coupled to an anode of the diode24, a cathode of the diode24is coupled to an anode of the diode26, a cathode of the diode26is coupled to an anode of the diode28, and a cathode of the diode28is coupled to a node50. Thus, each diode of the diode chain20is coupled in a forward conduction direction from the pad10to the node50. The diode30is coupled between the pad10and the node50, and the diode30is coupled in a forward conduction direction from the node50to the pad10, i.e. an anode of the diode30is coupled to the node50and a cathode of the diode30is coupled to the pad10. The transistor40is coupled between the node50and a ground VSS, wherein a gate of the transistor40is coupled to the ground VSS. In this embodiment, the transistor40is an N-type metal oxide semiconductor (NMOS) transistor. The diodes of the diode chain20are conducted in a forward direction from the pad10to the node50when a voltage of the pad10is greater than a voltage of the node50during an ESD event. On the other hand, the diode30is conducted in a forward direction from the node50to the pad10when the voltage of the node50is greater than the voltage of the pad10.

FIG. 2shows a sectional view of a diode according to an embodiment of the invention. As shown inFIG. 2, an N-well220is disposed in a P-substrate210and a P-type doped region230is disposed in the N-well220, wherein a P-type diode250is formed with the P-type doped region230and the N-well220. As shown inFIG. 2, the P-type diode250is surrounded with the N-well220. Thus, the P-type diode250can be used to be stacked due to a breakdown voltage from the N-well220to the P-substrate210being higher. Therefore, in an embodiment of the invention, the diodes of the diode chain20and the diode30are the P-type diode250.

Referring toFIG. 1, an amount of the diodes for the diode chain20is determined according to an operating voltage of the medium voltage signal and a breakdown voltage of the transistor40. For typical logic circuits, common operating voltages are 5V, 3.3V, 2.5V and 1.8V etc. However, certain pins of logic circuits require operating at higher voltages, such as a voltage which is greater than 5V, i.e. medium voltage. For example, assume that the breakdown voltage of the transistor40is 8V and the operating voltage of the medium voltage signal is 9V. Then, if a guard band of ESD protection is 20%, a maximum voltage operated in the pad10is 10.8V. Then, a voltage difference between the maximum voltage of the pad10and the breakdown voltage of the transistor40is 2.8V. Thus, four diodes are needed for the diode chain20if the voltage difference is 2.8V, because a forward bias of a diode is about 0.7V. In this embodiment, the 9V medium voltage is intended to be illustrative, and not to limit the scope of the invention. Users can select a suitable amount of the diodes according to various medium voltages and breakdown voltage of low voltage devices.

The ESD protection circuit described in the embodiment of the invention can provide medium voltage ESD protection in low voltage circuits formed by low voltage processes. Furthermore, the ESD protection circuit described in the embodiment of the invention can provide ESD protection for higher voltages in present low voltage processes without additional manufacturing cost.