DYNAMIC ALGORITHM SELECTION

Dynamic selection of a multiplication algorithm by receiving operands A and B, determining a difference between A and B, selecting a first multiplication algorithm if the difference falls below a threshold, selecting a second multiplication algorithm if the difference equals or exceeds the threshold, pre-scaling the operands, calculating a quotient for the scaled operands, back multiplying the quotient using the selected algorithm, yielding a product, subtracting the product from operand A, yielding a remainder, and providing the remainder as an output.

FIELD OF THE INVENTION

The disclosure relates generally to the dynamic selection of processor algorithms. The disclosure relates particularly to the dynamic selection of processor multiplication algorithms according to input data.

BACKGROUND

Common Business Oriented Language (COBOL) is a computer programming language having a vast established base of legacy programs in use around the world. Many customer information control system (CICS®) transaction are supported through COBOL code. Millions of CICS transaction are processed each second of the day. COBOL supports a wide range of arithmetic functions for decimal number operations, including the vector remainder decimal function VRP, which receives inputs (A, B) and calculates a quotient and remainder such that A=quotient *B with a remainder, the absolute value of the remainder<the absolute value of B, the sign of the remainder is the sign of A. The VRP function outputs the remainder. (Note: the term(s) “CICS” may be subject to trademark rights in various jurisdictions throughout the world and are used here only in reference to the products or services properly denominated by the marks to the extent that such trademark rights may exist.)

The calculation of the remainder is split into a division part where the quotient is calculated and a remainder part where the quotient is multiplied by the divisor and the result is subtracted from the dividend. Depending upon the value of the quotient, the algorithm utilized in multiplying the quotient by the divisor may require more or fewer computing cycles to complete. As millions of operations occur per second, selecting the more efficient multiplication algorithm for each such operation yield benefits in terms of millions of fewer computing cycles utilized in completing the processing of the VRP functions.

SUMMARY

Aspects of the invention disclose methods, systems and computer readable media associated with dynamic selection of a multiplication algorithm by receiving operands A and B, determining a difference between A and B, selecting a first multiplication algorithm if the difference falls below a threshold, selecting a second multiplication algorithm if the difference equals or exceeds the threshold, pre-scaling the operands, calculating a quotient for the scaled operands, back multiplying the quotient using the selected algorithm, yielding a product, subtracting the product from operand A, yielding a remainder, and providing the remainder as an output.

DETAILED DESCRIPTION

Calculation of a remainder output for a function such as VRP (A, B), includes a division calculation, wherein a quotient of A divided by B is determined, and a remainder part where the quotient*B is subtracted from A, leaving the remainder, as the final output. The selection of the algorithms used for the quotient calculation and for the algorithm used for the back multiplication part are based on data type, area requirements, cycle time requirements, performance, etc. For a decimal divide, operand prescaling followed by a digit wise loop over 4 cycles yields the quotient. For the multiplication, the system may have a choice, either digit wise multiplication and continuous summing of the partial products, or multi-digit multiplication in combination with a decimal reduction tree. Each algorithm has advantages and disadvantages, depending upon the operands. For instances where at least one operand is short, the digit wise multiplication requires fewer computing cycles to complete. For longer operands, the multi-digit multiplication takes fewer computing cycles.

In an embodiment, the method determines the relative size of the operands and makes an algorithm selection according to the relative operand size. In an embodiment, the method selects digit wise multiplication for operands having a number of quotient digits estimation based upon leading-zero difference of less than four and selecting multi-digit multiplication for those operands having a number of quotient digits estimation based upon leading zero difference of four or more. In this embodiment, the method determines as an estimation of the number of digits of the quotient according to the leading zero of the inputs, by the formula: #quotient digits=(leading_zero_digits B−leading_zero_digits A, leading_zero_digits B−leading_zero_digits A+1).

Aspects of the present invention relate generally to improving processing efficiency through the dynamic selection of a multiplication algorithm according to input values. In embodiments, computing system receives a computation (division) request, scales the operands for efficiency, estimates the number of digits in the quotient while concurrently determining the quotient, selects a back-multiplication algorithm according to the number of estimated quotient digits, back multiplies the quotient using the selected algorithm, and subtracts the product of the back multiplication from the dividend to determine the remainder as the final output. Selection of the algorithm according to a defined threshold for the estimated number of quotient digits enables the computing system to more efficiently process the division operation and saves computing cycles.

In accordance with aspects of the invention there is a method for dynamically selecting the appropriate back multiplication algorithm for a division computations. The method estimates the number of digits in a quotient and selects an algorithm based upon the relationship of the estimated number of quotient digits to a defined threshold of four estimated quotient digits. A first algorithm, digit wise multiplication with continuous summing of the partial products is selected for quotient digit estimations less than four, while a multi-digit multiplication in combination with a decimal reduction tree is selected for quotient digit estimations of four or more digits. As the number of quotient digits deviates further from four, the number of computing cycles saved through the dynamic algorithm selection method increases.

Aspects of the invention provide an improvement in the technical field of central processor computing instruction execution. For quotients having three digits, the method saves about three computing cycles by selecting digit wise multiplication, for five-digit quotients, the method saves one cycle by selecting the multi-digit multiplication. Greater cycle savings are achieved for quotients having more digits. Reduced cycles saves processing time and the energy necessary to complete the processing, resulting in more efficient overall computing operation.

Aspects of the invention also provide an improvement to computer functionality. In particular, implementations of the invention are directed to a specific improvement to the way processor compute division calculations. Disclosed method reduce the number of cycles necessary for such calculations resulting in time and energy savings for the operators of such systems.

In an embodiment, one or more components of the system can employ hardware and/or software to solve problems that are highly technical in nature (e.g., receiving operands, scaling the operands, calculating the quotient of the operands, estimating the number of digits in the quotient, selecting a back multiplication algorithm according to the quotient digit estimation, back multiplying the quotient using the selected algorithm, determining the remainder output by subtracting the product of the back multiplication from the dividend, etc.). These solutions are not abstract and cannot be performed as a set of mental acts by a human due to the processing capabilities needed to facilitate dynamic algorithm selection, for example. Further, some of the processes performed may be performed by a specialized computer for carrying out defined tasks related to mathematical computation. For example, a specialized computer can be employed to carry out tasks related to mathematical computations including dynamic algorithm selection, or the like.

In an embodiment, disclosed methods relate to the processing of instructions by a computing system including one or more processors. As part of the normal operations of the computing system, two operands (A, B) are passed to the processor for a division/remainder computation such as VRP, which provides as its output, the remainder of the operation A/B. Initially, the processor normalizes the two input operands, performs padding of the operands with trailing zero digits to fill the format and performs a scaling operation on the divisor B. The pre-scaling of the operands for the division calculation requires around eighteen cycles for completion. Following scaling, the method determines the quotient A/B, requiring a number of cycles which varies according to the number of digits in the quotient. In this embodiment, as the method performs the division operation, the method concurrently estimates the number of digits in the quotient. In an embodiment, the method estimates the number of digits in the quotient as the difference between the number of leading zeros in input B and the number of lead zeros in input A as well as the difference between the number of leading zeros in input B and the number of leading zeros in input A, plus 1, prior to normalization of the inputs. The estimation of the number of quotient digits occurs during the same cycles utilized to calculate the actual quotient A/B, therefore no latency is added to the overall calculation through the addition of the estimation and subsequent algorithm selection.

In an embodiment, the number of quotient digits relates to the number of cycles necessary for differing multiplication algorithms to calculate the product of quotient and B, for the purpose of determining the remainder as A minus that product. For the two algorithms, digit wise multiplication with continuous summing of partial products, and multi-digit multiplication with a decimal reduction tree, the number of necessary cycles for the back multiplication is roughly equal for four-digit quotients, while less than four digits favors the digit wise multiplication and more than four digits favors the multi-digit multiplication algorithm.

Following the calculation of the quotient and the concurrent estimation of quotient digits with the accompanying selection of a multiplication algorithm, the method applies the selected multiplication algorithm to the operand B and quotient to yield the product quotient * B. This operation requires differing computing cycles depending upon the number of digits in the quotient and the multiplication algorithm selected for use.

Following determining of the product, the method subtracts the product from operand to determine the remainder which is provided as the output of the function. The calculation of the remainder requires the same number of cycles regardless of the selected multiplication algorithm.

For the overall system, efficiency gains are achieved by selection of the more efficient multiplication algorithm for each iteration of the remainder function by the system. With each such selection, the system saves computing cycles.

FIG.1provides a schematic illustration of exemplary network resources associated with practicing the disclosed inventions. The inventions may be practiced in the processors of any of the disclosed elements which process an instruction stream. As shown in the figure, a networked Client device110connects wirelessly to server sub-system102. Client device104connects wirelessly to server sub-system102via network114. Client devices104and110comprise timeseries data set selection program (not shown) together with sufficient computing resource (processor, memory, network communications hardware) to execute the algorithm selection program. As shown inFIG.1, server sub-system102comprises a server computer150.FIG.1depicts a block diagram of components of server computer150within a networked computer system1000, in accordance with an embodiment of the present invention. It should be appreciated thatFIG.1provides only an illustration of one implementation and does not imply any limitations with regard to the environments in which different embodiments can be implemented. Many modifications to the depicted environment can be made.

Server computer150can include processor(s)154, memory158, persistent storage170, communications unit152, input/output (I/O) interface(s)156and communications fabric140. Communications fabric140provides communications between cache162, memory158, persistent storage170, communications unit152, and input/output (I/O) interface(s)156. Communications fabric140can be implemented with any architecture designed for passing data and/or control information between processors (such as microprocessors, communications and network processors, etc.), system memory, peripheral devices, and any other hardware components within a system. For example, communications fabric140can be implemented with one or more buses.

Memory158and persistent storage170are computer readable storage media. In this embodiment, memory158includes random access memory (RAM)160. In general, memory158can include any suitable volatile or non-volatile computer readable storage media. Cache162is a fast memory that enhances the performance of processor(s)154by holding recently accessed data, and data near recently accessed data, from memory158.

Program instructions and data used to practice embodiments of the present invention, e.g., the multiplication algorithm selection program175, are stored in persistent storage170for execution and/or access by one or more of the respective processor(s)154of server computer150via cache162. In this embodiment, persistent storage170includes a magnetic hard disk drive. Alternatively, or in addition to a magnetic hard disk drive, persistent storage170can include a solid-state hard drive, a semiconductor storage device, a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, or any other computer readable storage media that is capable of storing program instructions or digital information.

The media used by persistent storage170may also be removable. For example, a removable hard drive may be used for persistent storage170. Other examples include optical and magnetic disks, thumb drives, and smart cards that are inserted into a drive for transfer onto another computer readable storage medium that is also part of persistent storage170.

Communications unit152, in these examples, provides for communications with other data processing systems or devices, including resources of client computing devices104, and110. In these examples, communications unit152includes one or more network interface cards. Communications unit152may provide communications through the use of either or both physical and wireless communications links. Software distribution programs, and other programs and data used for implementation of the present invention, may be downloaded to persistent storage170of server computer150through communications unit152.

I/O interface(s)156allows for input and output of data with other devices that may be connected to server computer150. For example, I/O interface(s)156may provide a connection to external device(s)190such as a keyboard, a keypad, a touch screen, a microphone, a digital camera, and/or some other suitable input device. External device(s)190can also include portable computer readable storage media such as, for example, thumb drives, portable optical or magnetic disks, and memory cards. Software and data used to practice embodiments of the present invention, e.g., multiplication algorithm selection program175on server computer150, can be stored on such portable computer readable storage media and can be loaded onto persistent storage170via I/O interface(s)156. I/O interface(s)156also connect to a display180.

Display180provides a mechanism to display data to a user and may be, for example, a computer monitor. Display180can also function as a touch screen, such as a display of a tablet computer.

FIG.2provides a flowchart200, illustrating exemplary activities associated with the practice of the disclosure. After program start, at block210, the method receives two operands (A, B) for processing as part of a mathematical operation such as VRP, for the computation and return of the remainder of the operation A/B. The operands may be passed as normal function of any underlying application program.

At block220, the method determines a difference between the operands in support of estimating the number of digits in the quotient A/B. In an embodiment, the number of leading zero digits of each operand is determined and the difference of the number of leading_zero_digits is calculated. The method then concurrently calculates the quotient A/B and the quotient digit estimation: #quotient digits=(leading_zero_digits B−leading_zero_digits A, leading_zero_digits B−leading_zero_digits A+1).

At block230, the method utilizes the value of #quotient digits to select among different multiplication algorithms for the back multiply step of the determination of the remainder portion of A/B. In this step, the method compares the value of #quotient digits to a threshold, such as four and selects a multiplication algorithm according to that comparison. In an embodiment, the method selects digit wise multiplication with continuous summing of partial products for #quotient digits results less than four and selects multi-digit multiplication with a decimal reduction tree, for #quotient digit estimation values equal to, or greater than four.

At block240, the method applies the selected multiplication algorithm in performing the back multiplication of quotient * B, yielding a product P. At block250, the method computes the difference A−P, yielding the remainder R, which is provided, at block260, as the output of the function such as VRP.

In an embodiment, all processing of the disclosed function may occur as part of a single processor computing environment, or the processing my occur in the operations of a system of networked processors including a system for networked processor incorporating cloud infrastructure processors and other resources.

The present invention may be a system, a method, and/or a computer program product at any possible technical detail level of integration. The invention may be beneficially practiced in any system, single or parallel, which processes an instruction stream. The computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present invention.