A comparator includes a sampling capacitor, a first switching unit which is connected to an input end of the sampling capacitor and which applies an input signal to the input end of the sampling capacitor, a second switching unit which is connected to the input end of the sampling capacitor and which applies a reference signal to the input end of the sampling capacitor, an output transistor connected to an output end of the sampling capacitor in a source follower connection manner or an emitter follower connection manner, and a third switching unit which is connected to an output end of the sampling capacitor and which maintains maintaining a voltage at the output end of the sampling capacitor to be constant. The input signal is compared with the reference signal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

2. Description of the Related Art

A comparator that compares an input signal and a reference signal has been widely used in various electronic circuits.

As this comparator, a comparator101having the structure shown inFIG. 12is known. In the comparator101, an input signal Vinand a reference signal Vrefare applied to the input end of a sampling capacitor102through a first switch103and a second switch104. The output end of the sampling capacitor102connects to an inverter circuit107formed by connecting two transistors105and106between a power supply VCC and the ground GND, and a third switch108is provided between the input and output terminals of the inverter circuit107(See, for example, Japanese Unexamined Patent Application Publication No. 10-145195).

In the comparator101, the voltage of the input signal Vinis applied to the input end of the sampling capacitor102and a threshold voltage of the inverter circuit107is applied to the output end of the sampling capacitor102in such a manner that the first and third switches103and108are initially set to be on and the second switch104is set to be off. After that, by setting the first and third switches103and108to be off and the second switch104to be on, the voltage of the reference signal Vrefis applied to the input end of the sampling capacitor102.

When the voltage of the input signal Vinis greater than the voltage of the reference signal Vref, a voltage at the output end of the sampling capacitor102is less than the threshold voltage of the inverter circuit107, and the inverter circuit107outputs a high level (H-level) signal. Alternatively, when the voltage of the input signal Vinis less than the voltage of the reference signal Vref, the voltage at the output end of the sampling capacitor102is greater than the threshold voltage of the inverter circuit107, and the inverter circuit107outputs a low level (H-level) signal.

In the comparator101, a range of the input signal Vinin which the comparator101is operable cannot be widened because the inverter circuit107is connected to the output end of the sampling capacitor102.

This is because, in the comparator101, widening the range of the input signal Vinin which the comparator101is operable greatly increases power consumption of the comparator101and deteriorates characteristics of the comparator101since a cutoff frequency of the input signal Vinis determined by two transistors105and106which constitute the inverter circuit107.

In other words, in the comparator101, in order to improve frequency characteristics of the transistors105and106, transconductances of the transistors105and106must be increased. For the purpose, a direct current supplied to the transistors105and106must be increased, and the power consumption accordingly increases.

Also, in the comparator101, in order that a large direct current may flow in each transistor105or106, the transistors105and106must be enlarged. The enlarged transistors105and106increase their parasitic capacitances, and characteristics of the comparator101accordingly deteriorate.

As described above, since, in the comparator101, the inverter circuit107is connected to the output end of the sampling capacitor102, an increase in power consumption and deterioration in characteristic occur due to widening of the range of the input signal Vin. As a result, a range of the input signal Vinin which the comparator101is operable cannot be widened.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to enable signal range widening for a comparator by employing a configuration that connects an inverter circuit to an output end of a sampling capacitor, and to enable signal range widening for a differential amplifier and analog-to-digital converter by applying the comparator to the differential amplifier and the analog-to-digital converter.

According to an aspect of the present invention, a comparator is provided which includes a sampling capacitor, a first switching unit which is connected to an input end of the sampling capacitor which applies an input signal to the input end of the sampling capacitor, a second switching unit which is connected to the input end of the sampling capacitor and which applies a reference signal to the input end of the sampling capacitor, an output transistor connected to an output end of the sampling capacitor in a source follower connection manner or an emitter follower connection manner, and a third switching unit which is connected to an output end of the sampling capacitor and which maintains a voltage at the output end of the sampling capacitor to be constant. In the comparator, the input signal is compared with the reference signal.

According to another aspect of the present invention, a sample-and-hold circuit is provided which includes a sampling capacitor, a first switching unit which is connected to an input end of the sampling capacitor which applies an input signal to the input end of the sampling capacitor, a second switching unit which is connected to the input end of the sampling capacitor and which applies a reference signal to the input end of the sampling capacitor, an output transistor connected to an output end of the sampling capacitor in a source follower connection manner or an emitter follower connection manner, and a third switching unit which is connected to an output end of the sampling capacitor and which maintains a voltage at the output end of the sampling capacitor to be constant, and in which the input signal is sampled.

According to another aspect of the present invention, a differential amplifier including a pair of comparators differentially connected to each other is provided. Each of the comparators includes a sampling capacitor, a first switching unit which is connected to an input end of the sampling capacitor which applies an input signal to the input end of the sampling capacitor, a second switching unit which is connected to the input end of the sampling capacitor and which applies a reference signal to the input end of the sampling capacitor, an output transistor connected to an output end of the sampling capacitor in a source follower connection manner or an emitter follower connection manner, and a third switching unit which is connected to an output end of the sampling capacitor and which maintains a voltage at the output end of the sampling capacitor to be constant. In each of the comparators, the input signal is compared with the reference signal.

According to another aspect of the present invention, a two-stage amplifier including prestage and poststage amplifiers connected in series to each other is provided. The two-stage amplifier has an offset compressing function for compressing an offset voltage of the prestage amplifier by increasing the gain of the postage amplifier. The prestage amplifier includes a pair of comparators differentially connected to each other. Each of the comparators includes a sampling capacitor, a first switching unit which is connected to an input end of the sampling capacitor which applies an input signal to the input end of the sampling capacitor, a second switching unit which is connected to the input end of the sampling capacitor and which applies a reference signal to the input end of the sampling capacitor, an output transistor connected to an output end of the sampling capacitor in a source follower connection manner or an emitter follower connection manner, and a third switching unit which is connected to an output end of the sampling capacitor and which maintains a voltage at the output end of the sampling capacitor to be constant. In each of the comparators, the input signal is compared with the reference signal.

According to another aspect of the present invention, an analog-to-digital converter including a plurality of comparators is provided. In the analog-to-digital converter, an input signal is converted into digital form after each of the comparators compares the input signal with one reference signal of different reference signals. Each of the comparators includes a sampling capacitor, a first switching unit which is connected to an input end of the sampling capacitor which applies the input signal to the input end of the sampling capacitor, a second switching unit which is connected to the input end of the sampling capacitor and which applies the reference signal to the input end of the sampling capacitor, an output transistor connected to an output end of the sampling capacitor in a source follower connection manner or an emitter follower connection manner, and a third switching unit which is connected to an output end of the sampling capacitor and which maintains a voltage at the output end of the sampling capacitor to be constant. In each of the comparators, the input signal is compared with the reference signal.

According to another aspect of the present invention, a two-stage amplifier including prestage and poststage amplifiers connected in series to each other is provided. The two-stage amplifier has an offset compressing function for compressing an offset voltage of the prestage amplifier by increasing the gain of the postage amplifier. The prestage amplifier includes a pair of comparators differentially connected to each other. Each of the comparators includes a sampling capacitor, a first switching unit which is connected to an input end of the sampling capacitor which applies an input signal to the input end of the sampling capacitor, a second switching unit which is connected to the input end of the sampling capacitor and which applies a reference signal to the input end of the sampling capacitor, an output transistor connected to an output end of the sampling capacitor in a source follower connection manner or an emitter follower connection manner, and a third switching unit which is connected to an output end of the sampling capacitor and which maintains a voltage at the output end of the sampling capacitor to be constant, and the input signal is compared with the reference signal. The comparators include an input-impedance lowering unit provided between the output ends of the sampling capacitors of the comparators.

According to another aspect of the present invention, an analog-to-digital converter including a plurality of comparators is provided. In the analog-to-digital converter, an input signal is converted into digital form after each of the comparators compares the input signal with one reference signal of different reference signals. Each of the comparators includes a sampling capacitor, a first switching unit which is connected to an input end of the sampling capacitor which applies an input signal to the input end of the sampling capacitor, a second switching unit which is connected to the input end of the sampling capacitor and which applies a reference signal to the input end of the sampling capacitor, an output transistor connected to an output end of the sampling capacitor in a source follower connection manner or an emitter follower connection manner, and a third switching unit which is connected to an output end of the sampling capacitor and which maintains a voltage at the output end of the sampling capacitor to be constant, and the input signal is compared with the reference signal. The comparators include an input-impedance lowering unit provided between the output ends of the sampling capacitors of the comparators.

A comparator of the present invention is usable in various electronic circuits. For example, it can be used in an analog-to-digital converter.

According to the present invention, a comparator has a wideband. By using the comparator in a differential amplifier or an analog-to-digital converter, the differential amplifier or analog-to-digital converter can have a wideband.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

AsFIG. 1shows, in a comparator A according to an embodiment of the present invention, an input signal Vinis applied to the input end of a sampling capacitor C1through an N-type switching transistor T1used as a first switching unit, and a reference signal Vrefis applied to the input end of the sampling capacitor C1through an N-type switching transistor T2used as a second switching unit.

A first control signal CLK1is applied to the gate terminal of the switching transistor T1, and a second control signal CLK2is applied to the gate terminal of the switching transistor T2.

Also, in the comparator A, the gate terminal of a P-type output transistor T4is connected in a source follower connection manner to the output end of the sampling capacitor C1, and a switching transistor T3used as a third switching unit is connected to the output end of the sampling capacitor C1in order to set a voltage at the output end of the sampling capacitor C1to be constant (ground voltage).

A third control signal CLK3is applied to the gate terminal of the switching transistor T3.

An output transistor T4has a source terminal connected to a power supply VCC, with a constant current generator I1provided therebetween, and a drain terminal connected to the ground GND. An output signal can be extracted from the source terminal.

The comparator A is controlled by the first to third control signals CLK1, CLK2, and CLK3, which change with the timing shown inFIG. 2. The voltage of the input signal Vinis applied to the input end of the sampling capacitor C1by using the first and third control signals CLK1and CLK3to set the transistors T1and T3to be on, and using the second control signal CLK2to set the switching transistor T2to be off. The input signal Vinis sampled with a constant voltage (ground voltage) applied to the output end of the sampling capacitor C1. After that, the switching transistors T1and T3are set to be off by using the first and third control signals CLK1and CLK3, and the switching transistor T2is set to be on by using the second control signal CLK2, whereby the voltage of the reference signal Vrefis applied to the input end of the sampling capacitor C1. In this state, the input signal Vinand the reference signal Vref, which are obtained at the time the third control signal CLK3changes from its ON state to OFF state, are compared in voltage.

When the input signal Vinis greater than the reference signal Vrefin voltage, the voltage at the output end of the sampling capacitor C1drops and a low level (L-level) signal is output. Alternatively, when the input signal Vinis less than the reference signal Vref, the voltage at the output end of the sampling capacitor C1rises and an high level (H-level) signal is output.

Accordingly, the comparator A has a sample-and-hold function because the comparator A operates to sample the input signal Vinwhen the third control signal CLK3is on and to compare the voltages of the input signal Vinand the reference signal Vrefwhen the third control signal CLK3changes into the OFF state.

As described above, in the comparator A according to the embodiment, instead of connecting an inverter circuit to the output end of the sampling capacitor C1, the output transistor T4is connected in a source follower connection manner or connected in an emitter follower connection manner, whereby frequency characteristics caused by characteristics of the output transistor T4can be improved and a range of the input signal Vinwhich can be sampled can be determined by the first and third switching units.

Therefore, by reducing an ON resistance of the third switching unit, the sampling range of the comparator A can be widened.

When the switching transistor T3is used as the third switching unit, by simply enlarging the switching transistor T3, the ON resistance can be easily reduced without increasing a direct current following in the switching transistor T3.

The switching units are not limited to switching transistors, but various switching transistors may be used. Also, the transistors are not field effect transistors, but bipolar transistors may be used. In particular, when a bipolar transistor is used as the output transistor T4, it needs to be connected in an emitter follower connection manner to the sampling capacitor C1.

The third switching unit can be constituted by connecting a plurality of switching transistors in series to one another.

In other words, the comparator B shown inFIG. 3includes two N-type switching transistors T3and T5connected in series to each other, as the third switching unit. A second control signal CLK2is applied to the gate terminals of the switching transistors T3and T5.

In the present invention, as described above, in the comparator B, also parasitic diodes of the switching transistors T3and T5are connected in series since the switching transistors T3and T5are connected in series. Accordingly, an opposite current can be prevented from flowing in the third switching unit through the parasitic diodes. This can prevent the comparator B from malfunctioning.

By differentially connecting the above comparators A and B, both (in pair) can be used as a differential amplifier.

Specifically, the differential amplifier C shown inFIG. 4is formed by differentially connecting a pair of comparators A and A′. Since the comparator A′ is similar in structure to the comparator A, primes are put on the reference numerals of elements having identical functions.

In the differential amplifier C, an N-type switching transistor T6which is controlled to be on and off by a second control signal is provided between a pair of sampling capacitors C1and C1, whereby a decrease in input impedance is achieved.

The comparator D shown inFIG. 5is formed by differentially connecting a pair of comparators B and B′. Since the comparator B′ is similar in structure to the comparator B, primes are put on the reference numerals of elements having identical functions.

In addition, the above comparators A and B can be built into an analog-to-digital converter.

An embodiment of the present invention in which the above comparators A and B are applied to an analog-to-digital converter is described below.

By way of example, a sub-ranging analog-to-digital converter which has a total of four bits and which converts an analog signal into upper two bits of digital signals and subsequently converts lower two bits of the digital signals is described, but specific embodiments of the present invention are not limited to the sub-ranging analog-to-digital converter.

AsFIG. 6shows, an analog-to-digital converter1according to an embodiment of the present invention includes a reference voltage generating unit3for generating a plurality of different reference voltages, a comparing unit4for comparing the voltage of the analog signal with the different reference voltages, and a logic processing unit5for outputting a digital signal corresponding to the analog signal by performing logic processing on outputs from the comparing unit4. In the analog-to-digital converter1, the comparators A and B having the above sample-and-hold function are applied to the comparing unit4. Thus, a sample-and-hold unit for sampling and holding the analog signal is not provided between an input terminal Tinand the hold line6.

The reference voltage generating unit3generates a plurality of reference voltages by using sixteen resistors R1to R16which have equal resistances and which are connected in series between a high-side reference power supply Trtfor supplying a high side reference potential and a low-side reference power supply Trbfor generating a low side reference potential, and dividing the voltage between the high side reference potential and the low side reference potential by using the sixteen resistors R1to R16. The reference voltages are output from upper-bit reference-signal lines7and8, or from lower-bit reference-signal lines9and10.

Specifically, in the reference voltage generating unit3, the upper-bit reference-signal lines7and8, which output upper bit reference voltages, are respectively connected to the point between the fourth resistor R4and fifth resistor R5from the high-side reference power supply Trtand the point between the fourth resistor R13and fifth resistor R12from the low-side reference power supply Trb. Switches SW1and SW2which cooperatively link the lower-bit reference-signal lines9and10are respectively connected to the point between the first resistor R1and second resistor R2from the high-side reference power supply Trtand to the point between the third resistor R3and fourth resistor R4from the high-side reference power supply Trt. The lower-bit reference-signal lines9and10are respectively connected to the point between the seventh resistor R7and eighth resistor R8from the high-side reference power supply Trtand to the fifth resistor R5and sixth resistor R6from the high-side reference power supply Trtby interlock switches SW3and SW4. The lower-bit reference-signal lines9and10are respectively connected to the point between the ninth resistor R9and tenth resistor R10from the high-side reference power supply Trtand the point between the eleventh resistor R11and twelfth resistor R12from the high-side reference power supply Trtby interlock switches SW5and SW6. Also, the lower-bit reference-signal lines9and10are respectively connected to the fifteenth resistor R15and sixteenth resistor R16from the high-side reference power supply Trtand to the point between the thirteenth resistor R13and fourteenth resistor R14from the high-side reference power supply Trtby interlock switches SW7and SW8.

When converting the analog signal into upper bit digital signals, the reference voltage generating unit3outputs the reference voltages from the upper-bit reference-signal lines7and8, with all the switches SW1to SW8turned off. Also, when converting the analog signal into lower bit digital signals, the reference voltage generating unit3outputs the reference voltages from the lower-bit reference-signal lines9and10, with any one pair of switches, among pairs of switches SW1and SW2, SW3and SW4, SW5and SW6, and SW7and SW8, set to be on.

The comparing unit4includes an upper bit comparing unit11for comparing the voltage of the analog signal with the reference voltages for the upper bits, and a lower bit comparing unit12for comparing the voltage of the analog signal with the reference voltages for the lower bits. Since the upper bit comparing unit11and the lower bit comparing unit12are identical in configuration, the upper bit comparing unit11is described below.

The upper bit comparing unit11includes an amplification unit13for amplifying a difference between the voltage of the analog signal and each reference voltage, and a compare-and-hold unit14for comparing and holding the output of the amplification unit13.

The amplification unit13includes two two-stage amplifiers17formed by two differential amplifiers15and16which are connected in series to each other, and a complementary amplifier18which is connected to two differential amplifiers15before the stage of the two-stage amplifiers17, which are adjacent to each other, and which differentially amplifies the outputs of the differential amplifiers15. The two-stage amplifiers17are not limited to a case in which the two differential amplifiers15and16are connected in series to each other, but can be also formed by three or more differential amplifiers which are connected in series to one another.

AsFIGS. 7 and 8schematically show, ach two-stage amplifier17is formed by connecting the differential amplifiers15and16. The differential amplifier15in the prestage is similar in configuration to each of the differential amplifiers C and D, into which the above comparators A and B are built. The differential amplifier15has an in-phase input terminal19to which the hold line6is connected, and an anti-phase input terminal20to which the upper-bit reference-signal line7(8) is connected.

The differential amplifier16in the poststage connects a load circuit22to a differential amplification circuit21and connects a load switching unit23to the load circuit22. The differential amplifier16uses the load switching unit23to increase or reduce the gain of the differential amplification circuit21by switching between an entire load in which the entirety of the load circuit22is used as a load on the differential amplification circuit21, and a partial load in which part of the load circuit22is used as a load on the differential amplification circuit21.

Each two-stage amplifier17has an offset compressing function that superficially compresses an offset voltage of the differential amplifier15in the prestage by increasing the gain of the differential amplifier16in the poststage.

The specific structure of each two-stage amplifier17is described below with reference toFIG. 9.

The differential amplifier15is similar in configuration to each of the differential amplifiers C and D in which the above comparators A and B are built. The transistors T21and T22are cascode-connected to the output transistors T4and T4′. In other words, the source terminals of the transistors T21and T22are respectively connected to the drain terminals of the transistors T4and T4′, and a predetermined bias voltage Vb1 is applied to the gate terminals of the transistors T21and T22. This extracts the output of the differential amplifier15in the prestage from the drain terminals of the transistors T21and T22.

An amplitude limiting unit24for limiting the amplitude of the output of the differential amplifier15is provided between the differential amplifier15in the prestage and the differential amplifier16in the poststage.

The steering sensor24includes load resistors R21and R22which are connected to the drain terminals of the transistors T21and T22, respectively, and a resistor R30connected between each of the resistors R21and R22and the ground GND. The load resistors R21and R22limit the amplitude of the output of the differential amplifier15in the prestage, and the resistor R30adjusts a DC operating point of an input signal to the differential amplifier16in the poststage to an optimal voltage.

The differential amplifier16in the poststage includes cascode-connected P-type transistors T31, T41, T32, and T42which are differentially connected to one another. The transistors T31and T32have gate terminals connected to the outputs (the drain terminals of the transistors T21and T22) of the differential amplifier15in the prestage. A current supply I4is connected between each source terminal of the transistors T31and T32, and the source terminals of the transistors T41and T42are connected to the drain terminals of the transistors T31and T32. A predetermined bias voltage Vb2 is applied to each gate terminal of the transistors T41and T42, and an identical phase output terminal25and an opposite phase output terminal26are connected to the drain terminals of the transistors T41and T42.

In the differential amplifier16in the poststage, cascode-connected N-type transistors T61, T71, T62, and T72are connected to the cascode-connected P-type transistors, which form differential pairs, and switching transistors T51and T52are connected in parallel to one pair of the transistors T61and T62among the cascode-connected transistors T61, T71, T62, and T72, and the switching transistors T51and T52are connected in series to the other pair of the transistors T71and T72.

In other words, the drain terminals of the transistors T61and T62are respectively connected to the drain terminals of the transistors T41and T42. The transistors T61and T62have gate terminals, to which a predetermined bias voltage Vb3is applied, and source terminals respectively connected to the drain terminals of the transistors T71and T72. The transistors T71and T72have source terminals connected to the ground. The drain terminals of the transistors T51and T52are connected to the drain terminals of the transistors T41and T42in parallel to the transistors T61and T62. The transistors T51and T52have gate terminals to which the clock signal CLK is applied, and source terminals to which the gate terminals of the transistors T71and T72are connected in series.

In the differential amplifier16in the poststage, the cascode-connected transistors T61, T71, T62, and T72constitute the load circuit22, and the switching transistors T51and T52as switching elements constitute the load switching unit23.

When the switching transistors T51and T52are off, in the differential amplifier16in the poststage, the entirety of the load circuit22is used as a load (entire load). In this case, the load is a cascode load formed by the cascode-connected transistors T61, T71, T62, and T72, and decreases, thus increasing the gain of the differential amplifier16in the poststage. Also, when the switching transistors T51and T52are on, part of the load circuit22is a load (partial load). In this case, the load is a diode load formed by the transistors T71and T72, and increases, thus reducing the gain of the differential amplifier16in the poststage.

In the differential amplifier16in the poststage, among the cascode-connected transistors T61, T71, T62, and T72, the transistors T71and T72, which form the diode load, connect to capacitors C11and C12(as a voltage holding unit27) which hold voltages applied in the case of the diode load. Specifically, the capacitor C11is connected between the gate terminal of the transistor T71and the ground GND and the capacitor C12is connected between the gate terminal of the transistor T72and the ground GND.

Next, the operation of the two-stage amplifier17is described below.

The two-stage amplifier17alternately repeats a reset mode in which the voltage of the analog signal is applied to the in-phase input terminal19and the anti-phase input terminal20in the differential amplifier15in the prestage by using the control signals CLK1and CLK3to set the first and third switching units to be on and using the second control signal CLK2to set the second switching unit to be off, and a comparison mode in which the voltage of the analog signal is applied to the anti-phase input terminal20in the differential amplifier15in the prestage by using the first and third control signals CLK1and CLK3to set the first and third switches to be off and using the second control signal CLK2to the second switching unit to be on.

In the reset mode, the load switching unit23(the switching transistors T51and T52) is set to be on, causing the load on the differential amplifier16in the poststage to be formed by the diode load, whereby the gain of the differential amplifier16in the poststage can be reduced. In the comparison mode, the load switching unit23(the switching transistors T51and T52) is set to be off, causing the load on the differential amplifier16in the poststage to be formed by the cascode load, whereby the gain of the differential amplifier16in the poststage can be increased. In other words, in the two-stage amplifier17, the gain of the differential amplifier16in the poststage is greater in the comparison mode than in the reset mode.

As described above, by increasing the gain of the differential amplifier16in the poststage, the two-stage amplifier17can superficially compress the offset voltage of the differential amplifier15in the prestage.

In other words, when the offset voltage of the differential amplifier15in the prestage is represented by Vos, the gain of the differential amplifier15in the reset mode (diode load mode) is represented by Gr, the gain of the differential amplifier15in the comparison mode (cascode load mode) is represented by Gc, the output voltage of the differential amplifier15is represented by Vout, and an input voltage in the comparison mode is represented by Vin, the output voltage Voutin the reset mode is represented by
Vout=Gr·Vos
Also, the output voltage Voutin the comparison mode is represented by
Vout=Gc·Vin
Therefore, an equivalent input offset of the two-stage amplifier17can be represented by
Vos·Gr/Gc
From the equivalent input offset, it is found that, in the two-stage amplifier17, the offset voltage of the differential amplifier15is compressed Gr/Gctimes.

Accordingly, by reducing a gain ratio (Gr/Gc) by reducing the gain Grin the reset mode and increasing the gain Gcin the comparison mode, an offset compressing effect of the two-stage amplifier17can be enhanced, thus increasing the accuracy of the comparison mode.

In the two-stage amplifier17shown inFIG. 9, the gain Grin the reset mode is represented by
Gr=A·gm1/gm2
where A represents the gain of the differential amplifier15in the prestage, gm1represents the transconductance of the transistors T31and T32, and gm2represents the transconductance of the transistors T71and T72. Thus, to further reduce the gain Grin the reset mode, the transconductance gm2of the transistors T71and T72may be increased while reducing the transconductance of the transistors T31and T32. Accordingly, in the two-stage amplifier17shown inFIG. 9, based on physical properties, P-channel transistors having a small transconductance are used as the transistors T31and T32, and N-channel transistors having a large transconductance are used as the transistors T71and T72. The operating speed in the reset mode and the comparison mode is dominantly determined by the transconductance gm2of the transistors T71and T72. Thus, an increase in the transconductance gm2of the transistors T71and T72enables a high speed operation.

Next, the operation of the analog-to-digital converter1is described below with reference toFIG. 10.

The analog-to-digital converter1can operate in synchronization with the clock signal CLK.

The sample-and-hold unit2samples the analog signal within a predetermined period (T) in synchronization with a rise of the clock signal CLK, and subsequently holds the sampled analog signal within a predetermined period (H) until the clock signal CLK rises next.

The amplification unit13for the upper bits is switched from the reset mode to the comparison mode after a predetermined time (t1) from the rise of the clock signal CLK and amplifies the voltage difference between the voltage of the analog signal held by the sample-and-hold unit2and the reference voltage, and is switched again from the comparison mode to the reset mode in synchronization with a rise of the clock signal CLK.

The compare-and-hold unit14for the upper bits is reset in synchronization with the rise of the clock signal CLK, and holds the output of the amplification unit13in synchronization with a fall of the clock signal CLK.

The logic processing unit5generates upper bit digital signals by performing logic processing on the output held by the compare-and-hold unit14for the upper bits, and the reference voltage generating unit3generates the reference voltages for the lower bits.

Also, the amplification unit13is switched from the reset mode to the comparison mode after a predetermined time (t2) from a rise of the clock signal CLK and amplifies the voltage difference between the voltage of the analog signal held by the sample-and-hold unit2and the reference voltage, and is switched again from the comparison mode to the reset mode in synchronization with the rise of the clock signal CLK.

The compare-and-hold unit14is reset in synchronization with a fall of the clock signal CLK, and holds the output of the amplification unit13in synchronization with a rise of the clock signal CLK.

The logic processing unit5generates lower bit digital signals by performing logic processing on the output held by the compare-and-hold unit14, and outputs digital signals, which corresponds the analog signal, after one clock of the clock signal CLK.

As shown inFIG. 6, in the analog-to-digital converter1, the comparing unit4includes one upper bit comparing unit11and one lower bit comparing unit12. As shown inFIG. 11, the comparing unit4can achieve an increase in the speed of the analog-to-digital converter1by using a plurality of upper bit comparing units11each including one or more sample-and-hold units and a plurality of lower bit comparing units12each including a sample-and-hold unit which are connected in parallel to the hold signal line6from the sample-and-hold unit2by switches, and sequentially operating the upper bit comparing units11and the lower bit comparing units12. For example, by alternately operating comparing units that operate at two sampling frequencies of 100 mega-samplings/second (MS/s), the analog-to-digital converter1can operate at 200 MS/s.

As described above, the differential amplifier16can increase or reduce the gain of the differential amplification circuit21by connecting the load circuit22to the differential amplification circuit21and connecting the load switching unit23to the load circuit22, and using the load switching unit23to switch between the entire load in which the entirety of the load circuit22is used as the load on the differential amplification circuit21and the partial load in which part of the load circuit22is used as the load on the differential amplification circuit21.

Accordingly, the circuit size of the load circuit22in the differential amplifier16, whose gain is variable, can be reduced as much as possible.

Also, the load circuit22includes the cascode-connected transistors T61, T71, T62, and T72, and has the cascode load as the entire load and the diode load as the partial load. Thus, the load circuit22has a simplified configuration causing inexpensiveness, and has reduced size.

In particular, the load circuit22is constituted by the cascode-connected transistors T61, T71, T62, and T72, and the load switching unit23is formed by a switching element having connection in parallel to one pair of the transistors T61and T62among the cascode-connected transistors T61, T71, T62, and T72, and connection in series to the other pair of the transistors T71and T72, whereby the switching element is set to be on, thus setting the load on the differential amplification circuit21to be a diode load. Also, by setting the switching element to be off, the load on the differential amplification circuit21is set to be a cascode load. Thus, the differential amplifier16has a simplified configuration causing inexpensiveness, and the circuit size of the differential amplifier16can be reduced as much as possible.

Since, among the cascode-connected transistors T61, T71, T62, and T72, the transistors T71and T72, which form the diode load, connect to voltage holding units27for holding a voltage applied in the case of the diode load. Even an increase or decrease in the differential amplifier16does not change the DC operating point of the differential amplification circuit21, and the differential amplifier16can be stably operated at high speed.

In addition, as described above, the two-stage amplifier17includes two differential amplifiers15and16which are connected in series to each other, and can increase the gain of the differential amplifier16in the poststage.

Accordingly, the two-stage amplifier17has an offset compressing function that compresses the offset voltage of the differential amplifier15in the prestage. The offset compressing function can increase the accuracy of the two-stage amplifier17.

In addition, the two-stage amplifier17has a further improved offset compressing function because the differential amplifier16in the poststage is constituted by P-channel transistors, and the cascode-connected transistors T61, T71, T62, and T72are formed by N-channel transistors.

Also, the amplitude limiting unit24for limiting the amplitude of the output of the differential amplifier15is provided between the differential amplifier15in the prestage and the differential amplifier16in the poststage. Thus, the amplitude limiting unit24can prevent a large amplitude signal from being input to the differential amplifier16in the poststage. This enables an increase in response speed.

As described above, the analog-to-digital converter1includes the amplification unit13having a sample-and-hold function, and uses the amplification unit13to convert the analog signal into a digital signal by amplifying a difference between the voltage of the analog signal and each of different reference voltages.

The analog-to-digital converter1is formed as a sub-ranging analog-to-digital converter that converts an analog signal in order from upper bits of digital signals by amplifying the difference between the voltage of the analog signal and each reference voltage while gradually narrowing the range of the reference voltages. Thus, the number of the amplification units13can be reduced. This enables an increase in the processing speed of the analog-to-digital converter1and a reduction in power consumption of the analog-to-digital converter1.

Also, each amplification unit13includes a plurality of two-stage amplifiers17each formed by two differential amplifiers which are connected in series to each other, and complementary amplifiers18which are connected to the differential amplifiers15before the stage of adjacent two-stage amplifiers17and which differentially amplify the outputs of the differential amplifiers15in the prestage, whereby the amplification unit13is formed as a complementary analog-to-digital converter. Thus, the number of amplification units13. This enables an increase in the processing speed of the analog-to-digital converter1and a reduction in power consumption of the analog-to-digital converter1.

In addition, since each two-stage amplifier17has an offset compressing function that compresses the offset voltage of the differential amplifier15in the prestage by increasing the gain of the differential amplifier16in the poststage, the accuracy of the two-stage amplifier17can be increased. This can increase a resolution of the analog-to-digital converter1. The transistors T11and T12on the input side of the differential amplifier15in the prestage are reduced in size, thus reducing the parasitic capacitances of the transistors T11and T12, which are directly connected to the sample-and-hold unit2. Thus, also this can increase the processing speed of the analog-to-digital converter1, and can reduce the power consumption of the analog-to-digital converter1.

In particular, when an amplifier having an offset compressing function is used as an amplifier for an apparatus requiring a plurality of amplifiers as in the case of the analog-to-digital converter1, not only the offset voltage of each amplifier can be compressed, but also individual difference in offset voltage of the amplifiers can be decreased as much as possible, thus increasing the apparatus accuracy.

Since the differential amplifier15in the prestage includes a differential amplification circuit composed of the transistors T11, T21, T12, and T22, gate-drain mirror capacitance and drain-ground parasitic capacitance can be eliminated. Also this can increase the processing speed of the analog-to-digital converter1, and can reduce the power consumption of the analog-to-digital converter1.

The differential amplifier16can increase or reduce the gain of the differential amplification circuit21by connecting the load circuit22to the differential amplification circuit21and connecting the load switching unit23to the load circuit22, and using the load switching unit23to switch between the entire load in which the entirety of the load circuit22is used as the load on the differential amplification circuit21and the partial load in which part of the load circuit22is used as the load on the differential amplification circuit21. Thus, the load circuit22in the differential amplifier16, whose gain is variable, has circuit size reduced as much as possible. Also this can reduce the power consumption of the analog-to-digital converter1.

Although the above embodiment describes an example of a sub-ranging analog-to-digital converter which has a total of four bits and which performs conversion two separate times, the embodiment is not limited to the example of the sub-ranging analog-to-digital converter, but may be an analog-to-digital converter having a configuration for performing conversion in a plurality of stages. The analog-to-digital converter1is not limited to a single input analog-to-digital converter, but may be a differential input analog-to-digital converter. In addition, specific circuits are not limited to those having only positive supplies, but may be those having positive and negative supplies and those having only negative supplies. Also, specific elements constituting the circuits may be selected as required.