Electrostatic discharge protection device with silicon controlled rectifier protection circuit

An electrostatic discharge (ESD) protection device, incudes an N-type well and a P-type well formed in a semiconductor substrate; a first N-type diffusion region and a first P-type diffusion region formed in the N-type well, separated by a first separation film, and each connected to an Anode terminal; a second N-type diffusion region and a second P-type diffusion region formed in the P-type well, separated by a second separation film, and each connected to a Cathode terminal; a P-type floating region, formed in the P-type well, spaced apart from the second N-type diffusion region and the second P-type diffusion region; and a non-sal layer covering the P-type floating region.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit under 35 U.S.C. § 119 to Korean Patent Application No. 10-2021-0054864 filed on Apr. 28, 2021, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes.

BACKGROUND

The following description related to an electrostatic discharge protection device with silicon controlled rectifier.

2. Description of Related Art

As the size of semiconductor devices is becoming smaller and components per chip are becoming denser, the importance of ESD protection device, which is to protect the inner circuit of a chip from Electro Static Discharge (ESD), is getting higher.

Diodes, resistors, transistors, etc., are mainly used as a protection device in a protection circuit, and thyristor or silicon controlled rectifier (SCR) may also be used.

As a typical non-sal layer oxide of a MOSFET (Metal-Oxide-Semiconductor Field Effects Transistor) is becoming thinner and weaker, a protection device is needed to protect the non-sal layer oxide from external factors such as ESD that may exist in an input buffer of an input/output circuit.

Damage of an inner circuit such as an input buffer occurs because of junction spiking or oxide rupture, etc., caused by Joule heat generated by stress current caused by ESD being input through an input pad and discharges to another device throughout the inner circuit.

To solve this problem, before the stress current caused by ESD evades throughout an inner circuit, an ESD protect circuit is inserted to immediately discharge the electric charge injected in an input terminal toward a power supply terminal to prevent damage to the semiconductor terminal by ESD. Accordingly, thyristor or Silicon controlled rectifier (SCR) may be used for ESD protection.

However, parasitic transistors have high voltage to cause a breakdown. Accordingly, a trigger voltage of SCR 100 is very high more than 20V, and a holding voltage is low. So, it is hard to apply to an actual product because of the possibility of a Latch-up.

Moreover, when electricity lower than a trigger voltage of SCR is applied, an inner circuit is highly likely to be damaged.

Also, it is hard to use it as a protection device between power terminals because there is always a possibility of a Latch-up, as a holding voltage becomes lower than an actual operating voltage because of a low impedance.

SUMMARY

In one general aspect, an electrostatic discharge (ESD) protection device, incudes an N-type well and a P-type well formed in a semiconductor substrate; a first N-type diffusion region and a first P-type diffusion region formed in the N-type well, separated by a first separation film, and each connected to an Anode terminal; a second N-type diffusion region and a second P-type diffusion region formed in the P-type well, separated by a second separation film, and each connected to a Cathode terminal; a P-type floating region, formed in the P-type well, spaced apart from the second N-type diffusion region and the second P-type diffusion region; and a non-sal layer covering the P-type floating region.

A width of the first N-type diffusion region may be formed wider than a width of the second N-type diffusion region.

The first P-type diffusion region may be formed on opposite sides of the first N-type diffusion region.

The ESD protection device may further include a silicide film formed on the first N-type diffusion region. The non-sal layer may be formed on the first N-type diffusion region.

The first N-type diffusion region, the first P-type diffusion region, the second N-type diffusion region, and the second P-type diffusion region may be each formed shallower than the first and the second separation films.

A width of the P-type floating region may be configured to control a holding voltage.

The ESD protection device may further include a deep P-type well in the substrate, an N-type drift region, overlapped with the N-type well, and a P-type body region, overlapped with the P-type well.

The ESD protection device may further include a resistor connected in the second P-type diffusion region. The resistor may be formed of poly-silicon.

The non-sal layer may cover portions of the first N-type diffusion region and the first P-type diffusion region.

The non-sal layer may cover a portion of the second N-type diffusion region.

In another general aspect, an ESD protection device includes a N-type well formed in a semiconductor substrate, a P-type well formed on opposite sides of the N-type well, a first N-type diffusion region formed in the N-type well, first P-type diffusion regions each formed on opposite sides of the first N-type diffusion region, a second N-type diffusion region and a second P-type diffusion region formed in the P-type well, and a floated P-type floating region formed in the P-type well. A width of the first N-type diffusion region is formed wider than a width of the second N-type region.

The width of the first N-type diffusion region may be formed wider than a width of the second P-type diffusion region.

The first N-type diffusion region and the first P-type diffusion region, connected with an Anode terminal, may be separated by a first separation film.

The second N-type diffusion region and the second P-type diffusion region, connected with a Cathode terminal, may be separated by a second separation film.

The ESD protection device may further include a deep P-type well in the substrate, and a N-type drift region and a P-type body region formed in the deep P-type well. The N-type well and the N-type drift region may overlap, and the P-type well and a P-type body region may overlap.

The ESD protection device may further include a resistor connected in the second P-type diffusion region. The resistor may be formed of poly-silicon.

In another general aspect, an electrostatic discharge (ESD) protection device, incudes an N-type well and a P-type well in a semiconductor substrate; a first N-type diffusion region and a first P-type diffusion region spaced apart in the N-type well, and each connected to an Anode terminal; a second N-type diffusion region and a second P-type diffusion region spaced apart in the P-type well, and each connected to a Cathode terminal; a P-type floating region in the P-type well, spaced apart from the second N-type diffusion region and the second P-type diffusion region; and a first non-sal layer disposed on the P-type floating region and a portion of the second N-type diffusion region, and a second non-sal layer disposed on portions of the first N-type diffusion region and the first P-type diffusion region.

A width of the first N-type diffusion region may be different from a width of the second N-type region.

The ESD protection device may further include a first separation film between the first N-type diffusion region and the first P-type diffusion region; and a second separation film between the second N-type diffusion region and the second P-type diffusion region.

The ESD protection device may further include an N-type drift region formed below the N-type well; and a P-type body region formed below the P-type well.

DETAILED DESCRIPTION

This disclosure solves the above problems, providing an ESD protection device based on a silicon controlling rectifier that is resistant to Latch-up by increasing a holding voltage.

Moreover, an ESD protection device based on a silicon controlling rectifier is provided to quickly turn on a diode by decreasing a trigger voltage.

A targeted problem of the disclosure is not limited by the problems mentioned above, and other problems may be understood by a person skilled in the relevant field of technology from the following description.

The detailed description about the disclosure is given below, according to attached drawings.

FIG.1is a cross-sectional view of SCR, one of the ESD devices based on a normal silicon controlled rectifier.

Moreover, a terminal called Anode is connected with an N-type diffusion region (112, N-type) and a P-type diffusion region (113, P-type), which are included in N-type well111. Another terminal called Cathode is connected with an N-type diffusion region (122, N-type) and a P-type diffusion region (123, P-type) included in P-type well121.

A parasitic PNP transistor operates that is composed of an emitter, a collector, and a base. An N-type diffusion region122included in a P-type well121, an N-type diffusion region112included in an N-type well, and a P-type well121are operated as a parasitic NPN transistor composed of an emitter, a collector, and a base and discharge an ESD current. There is an advantage that this SCR 100 may release a large current with a small area.

FIG.2AandFIG.2Bare plan views of an ESD protection device based on a silicon controlled rectifier according to one or more embodiments of the disclosure.

With reference toFIG.2, an ESD protection device200, according to one or more embodiments of the disclosure, may include an N-type well212and two P-type wells222in a top view. A first N-type diffusion region213and two of first P-type diffusion regions214are formed in an N-type well212. A P-type floating region225, a second N-type diffusion region227, a second P-type diffusion region224are formed in each of two P-type wells222. The reason why an area or a width of a first N-type diffusion region213in an N-type well212is bigger than a width of two of first P-type diffusion regions214, a P-type floating region225, a second N-type diffusion227, and a second P-type diffusion region224is to ensure the current capacity. Because an anode terminal shares a first N-type diffusion region213, a current capacity of a first N-type diffusion region213is easily ensured. Herein, it is noted that use of the term ‘may’ with respect to an example or embodiment, e.g., as to what an example or embodiment may include or implement, means that at least one example or embodiment exists where such a feature is included or implemented while all examples and embodiments are not limited thereto.

And two of the first P-type diffusion regions214are each placed on opposite sides of a first N-type diffusion region213. An embodiment ofFIG.2Ais two-finger type composition, which enables the operation of two SCRs (PNPN). Thus, two of first P-type diffusion regions214plays the role of an emitter of PNP of each SCR.

A P-type floating region225in two P-type wells222may be considered that it is doped without connecting with a terminal such as Anode, Cathode, etc. By controlling a width of P-type floating region225, a base current may be controlled. The longer the width is, the more a base current increases, and because a current gain is diminished by increasing a base current, the holding voltage increases. Thus, an ESD protection device200may form a current path and discharge an ESD current inside a substrate through a positive feedback of a PNP and NPN transistor.

With reference toFIG.2B, a non-sal layer215is formed on an N-type well212. The non-sal layer215is a deposited insulating film to prevent the creation of silicide. It may be formed as an oxide, an oxide-nitride, or a nitride. A silicide film228is formed in areas that the non-sal layer215may not cover. A contact resistance may be diminished by forming a silicide film.

As shown inFIG.2B, the non-sal layer215may cover a part of a first N-type diffusion region213and a part of two of first P-type diffusion regions214. A silicide film228is formed in a remaining portion of the first N-type diffusion region213that the non-sal layer may not cover. Thus, a non-sal layer and a silicide film may be formed simultaneously on the first N-type diffusion region213. Likewise, a silicide film228is formed in a remaining area of two of first P-type diffusion regions214that the non-sal layer215may not cover.

Also, a non-sal layer is formed on two P-type wells222too. The non-sal layer215may cover a part of a second N-type diffusion region227. As an option, the non-sal layer215may cover a part of a second P-type diffusion region224(not shown). A silicide film228is formed in a rest area of a second N-type diffusion region227that a non-sal layer may not cover. Likewise, a silicide film228is formed on a rest area of a second P-type diffusion region224that the non-sal layer215may not cover.

And the non-sal layer215may cover a P-type floating region225completely. Thus, no contact plug is formed on the P-type floating region225.

FIG.3is a cross-sectional view of A-A′ ofFIG.2B, a section of an ESD protection device based on a silicon controlled rectifier, according to one or more embodiments of the disclosure.

With reference toFIG.3, with an ESD protection device200, according to one or more embodiments of the disclosure, an N-type well212and two P-type wells222are formed in a semiconductor substrate201. An ESD protection device200may include a first N-type diffusion region213and two of first P-type diffusion regions214in the N-type well212that are separated by a first separation film203. Each of the first N-type diffusion region213and two of first P-type diffusion regions214is connected to an Anode terminal. A second N-type diffusion region227and a second P-type diffusion region224in each of the two P-type well222are separated by a second separation film204and each connected to a Cathode terminal. Herein, a deep P-type well229doped as P-type may be formed in a semiconductor substrate201.

The reason why a width or an area of a first N-type diffusion region213is bigger than that of two of first P-type diffusion regions214, a second N-type diffusion region227, and a second P-type diffusion region224is to ensure the current capacity, and for that, a first N-type diffusion region213may be enlarged. Because an anode terminal shares a first N-type diffusion region213, a current capacity of a first N-type diffusion region213is easily ensured.

Each of the two P-type wells222may further include a P-type floating region225that is separately formed from a second N-type diffusion region227and a second P-type diffusion region224. A P-type floating region225may be considered doped without connecting with a terminal such as Anode, Cathode, etc. A P-type floating region225is doped as a P-type with a higher concentration than each of the two P-type wells222.

The P-type floating region225may increase a concentration of each of the two P-type well222, which is a base of a parasitic PNP bipolar transistor.

Hence, a holding voltage increases as a current gain of a parasitic NPN bipolar transistor decreases. Also, as a holding voltage increases, resistance to Latch-up is reinforced.

The P-type floating region225may be located between the second N-type diffusion region227and the first P-type diffusion regions214. Also, a length of a P-type floating region225may be controlled. Controlling a length of the P-type floating region225may be executed in a doping process using a mask.

A holding voltage may be controlled by adjusting a width of a P-type floating region225. As explained, an ESD protection device200has a high holding voltage by a P-type floating region225formed in each of the two P-type wells222. The P-type floating region225increases a hole's movement, increasing a base current of an NPN transistor. The increased base current decreases a current gain, making an ESD protection device200have a higher holding voltage.

An N-type well212and two P-type wells222may be separated by a third separation film205formed in the semiconductor substrate201or in a deep P-type well229formed in the semiconductor substrate201. Herein, an N-type well212and two P-type wells222may have a separation space240. Moreover, two P-type wells222may be doped with a higher concentration than a deep P-type well229.

A trigger voltage may be controlled by adjusting a separation space240between an N-type well212and two P-type wells222. For example, by diminishing the width of the separation space240, it may be possible to increase a current gain and have a low trigger voltage. That is, a trigger voltage may be controlled, and the bigger the width of a separation space240between an N-type well212and P-type well222is, the higher a trigger voltage becomes.

The first N-type diffusion region213and the second N-type diffusion regions227may be doped with a higher concentration than the N-type well212. Moreover, the first P-type diffusion regions214and the second P-type diffusion regions224formed may be doped with a higher concentration than the P-type well222.

The first N-type diffusion region213, the second N-type diffusion regions227, the first P-type diffusion regions214and the second P-type diffusion regions224may be respectively formed in the N-type well212and the P-type wells222with a predetermined depth. Thus, for example, the first N-type diffusion region213, the second N-type diffusion regions227, the first P-type diffusion regions214and the second P-type diffusion regions224may be formed shallower than a first and a second separation203,204.

The non-sal layer215is formed on an N-type well212. The non-sal layer215is a deposited insulating film to prevent the creation of a silicide. It may be formed as an oxide, an oxide-nitride, or a nitride. Thus, the non-sal layer215partially covers the first N-type diffusion region213and the two of first P-type diffusion regions214.

Likewise, the non-sal layer215is formed on two P-type wells222. The non-sal layer215partially covers a second N-type diffusion region227. Also, the non-sal layer215fully covers a P-type floating region225. Thus, no contact plug is connected to the P-type floating region225.

FIG.4AandFIG.4Bare plan views of an ESD protection device based on a silicon controlled rectifier according to another one or more embodiments of the disclosure.

With reference toFIG.4A, an N-type drift region211and a P-type body region221may be further included in the explained ESD protection device200. Herein, other composition elements except for an N-type drift region of211and a P-type body region221are the same as the explained ESD protection device200. Therefore, a detailed description is abridged.

An N-type drift region211and a P-type body region221raises a holding voltage to resist Latch-up. An N-type drift region211and an N-type well212are formed to be overlapped, wherein the N-type drift region211is disposed below the N-type well212. Also, a P-type body region221and a P-type well222are formed to be overlapped, wherein the P-type body region221is disposed below the P-type well222.

With reference toFIG.4B, the non-sal layer215is formed on an N-type well212. Herein, other composition elements except for an N-type drift region211and a P-type body region221are the same as the explained ESD protection device200, and therefore, detailed description is abridged.

As described inFIG.4B, the non-sal layer215covers a part of an N-type drift region211and a part of a P-type body region221. A silicide film228is formed in a rest area of an N-type drift region of211and a P-type body region221that a non-sal layer may not cover.

FIG.5is a cross-sectional view of B-B′ ofFIG.4B, a section of an ESD protection device based on a silicon controlled rectifier, according to another one or more embodiments of the disclosure.

With reference toFIG.5, an N-type drift region of211and a P-type body region221may be further included in the explained ESD protection device200. Although other composition elements, except for an N-type drift region211and a P-type body region221, are the same as the explained ESD protection device200, a detailed description is abridged.

An N-type drift region211and a P-type body region221raises a holding voltage to resist Latch-up.

An N-type well212is formed in an N-type drift region211. An N-type drift region may be doped with a lower concentration than an N-type well212. An effect of increasing a junction area may be achieved through that.

By forming an N-type well212in an N-type drift region211, a base concentration of a parasitic PNP bipolar transistor increases, and a holding voltage rises as a current gain of a parasitic PNP bipolar transistor decreases.

Moreover, a P-type well222is formed in a P-type body region221. A P-type body region221may be doped with a lower concentration than a P-type well222. An effect of increasing a junction area may be achieved through that.

By forming a P-type well222in a P-type body region221, a parasitic NPN bipolar transistor's base concentration increases, and a holding voltage rises as a current gain of a parasitic NPN bipolar transistor decreases.

As an ESD current increases, a voltage flows into an Anode terminal, a junction between an N-type drift region211and a P-type body region221becomes reverse biased. Herein, a junction between an N-type drift region211and a P-type body region221is executed in the space240between an N-type drift region211and a P-type body region221.

When an electric field of a junction between an N-type drift region211and a P-type body region221, which is in a state of reverse bias, reaches a threshold value that creates Avalanche breakdown, an EHP (Electron-Hole Pair) is created by avalanche breakdown. Hence, through an N-type drift region211and a P-type body region221, a junction area of two P-type wells222and an N-type well212may be widened.

A created hole current may move to a P-type body region221and raise the potential of a P-type body region221. With a junction of a second N-type diffusion region227connected with a Cathode, when an increased potential of a P-type body region221is higher than 0.7V, which is a Built-in Potential, a parasitic NPN bipolar transistor may turn on.

A current of a turned-on parasitic NPN bipolar transistor may form a drop of voltage in an N-type drift region211, and a parasitic PNP bipolar transistor may turn on. A turned-on parasitic PNP bipolar transistor may form a drop of voltage in a P-type body region221, and, by making a parasitic NPN bipolar transistor turned-on, an ESD protection device may be triggered, and that voltage may become a trigger voltage.

When an ESD protection device is triggered, an anode voltage may be diminished to a minimum value and become a holding voltage because there is no need to provide a bias to a parasitic NPN bipolar transistor by a current of a parasitic PNP bipolar transistor. Moreover, with a Positive Feedback of an ESD protection device, an ESD current flowed into an Anode terminal may be effectively discharged.

FIG.6is a cross-sectional view of an ESD protection device based on a silicon controlled rectifier according to another one or more embodiments of the disclosure.

With reference toFIG.6, a resistor226may be further included in the explained ESD protection device200, connected in a second P-type diffusion region224. Herein, other composition elements except for a resistor226are the same as the explained ESD protection device200; a detailed description is abridged.

A resistor226is connected in a second P-type diffusion region224and diminishes a trigger voltage. For example, the resistor may be an updoped Poly-Si resistor that has a high resistance. Thus, a resistor226may be formed as a poly-silicon form.

By connecting a resistor226in a second P-type diffusion region224, a hole may be formed by Avalanche breakdown in a separation space240of an N-type well212and two P-type wells222. To prevent the hole from leaking to a second P-type diffusion region224, the concentration of a hole in two P-type wells222may be increased, and Built-in Potential 0.7V may be rapidly induced in a junction of a second N-type diffusion region227connected with a Cathode. Through that, a turn-on of a diode may be more rapidly created.

FIG.7is a graph illustrating a feature of the current-voltage of an ESD protection device based on a normal silicon controlled rectifier.

With reference toFIG.7, when an ESD surge flows into an SCR, likeFIG.1, static electricity may be discharged by earthing. An SCR remains off state until reaching a trigger point11, and when it rises above a trigger voltage11, a feature moves, following a curve of a holding voltage12. When an SCR feature moves following a curve of a holding voltage12, an ESD current path may be formed.

As described inFIG.7, it can be seen that a trigger voltage of an SCR is considerably high at 20V, and a holding voltage is relatively low at 3V.

FIG.8a graph illustrating a feature of current-voltage of an ESD protection device based on a silicon controlled rectifier according to one or more embodiments of the disclosure.

With reference toFIG.8, in an ESD protection device based on silicon controlled rectifier likeFIG.2orFIG.6, a parasitic NPN bipolar transistor turns on, a voltage is dropped by N-type drift region, and a parasitic PNP bipolar transistor turns on. Thus, a turned-on parasitic PNP bipolar transistor makes a voltage dropped in P-type body region and a parasitic NPN bipolar transistor turned-on, which may decrease the trigger voltage from 21 to 16V.

Moreover, because there is no need to provide a bias to a parasitic NPN bipolar transistor by a current of a parasitic PNP bipolar transistor, an anode voltage may be diminished to a minimum value, and a holding voltage22may be increased up to 15V.

As explained above, by forming an N-type drift region211and a P-type body region221in an N-type well212and two P-type wells222, respectively, and by having a high current capacity, a holding voltage may be increased. Resistance is added between a Cathode, a P-type body region221, and a second P-type diffusion region224included in two P-type wells222, and through that, a trigger voltage is diminished.

An N-type drift region211and a P-type body region221may be doped with a lower concentration than an N-type well212and two P-type wells222, and a holding voltage of an ESD protection device based on silicon controlled rectifier is increased. An N-type drift region211may increase the base concentration of a parasitic PNP bipolar transistor, which diminishes the current gain of a parasitic PNP transistor. A P-type body region221may increase a base concentration of parasitic NPN bipolar transistor, which diminishes the current gain of a parasitic NPN transistor. Herein, an N-type drift region211and a P-type body region221may be formed separately.

According to the disclosure, it is possible to enhance the current capacity of an ESD protection device based on silicon controlled rectifier that increases a holding voltage and decreases a trigger voltage to be resistant to Latch-up.

With that, an excellent current capacity may be gained, which is better than that of the formerly used ESD protection device, and productivity may be enhanced by diminishing a device's size.

As explained, an ESD protection device of the subject disclosure based on silicon controlled rectifier may ensure the device's reliability and stability by increasing a holding voltage and inducing a low trigger voltage. Moreover, as the current capacity is increased, a micronization of a device size may be possible.