Switching device having a non-linear element

Method for a memory including a first, second, third and fourth cells include applying a read, program, or erase voltage, the first and second cells coupled to a first top interconnect, the third and fourth cells coupled to a second top interconnect, the first and third cells coupled to a first bottom interconnect, the second and fourth cells are to a second bottom interconnect, each cell includes a switching material overlying a non-linear element (NLE), the resistive switching material is associated with a first conductive threshold voltage, the NLE is associated with a lower, second conductive threshold voltage, comprising applying the read voltage between the first top and the first bottom electrode to switch the NLE of the first cell to conductive, while the NLEs of the second, third, and the fourth cells remain non-conductive, and detecting a read current across the first cell in response to the read voltage.

JOINT RESEARCH AGREEMENT

The presently claimed invention was made by or on behalf of the below listed parties to a joint university-corporation research agreement. The joint research agreement was in effect on or before the date the claimed invention was made and the claimed invention was made as a result of activities undertaken within the scope of the joint research agreement. The parties to the joint research agreement are The University of Michigan and Crossbar, Incorporated.

BACKGROUND

The present invention is related to switching devices. More particularly, the present invention provides a structure and a method for forming non-volatile resistive switching memory devices characterized by a suppression of current at low bias and a high measured ON/OFF resistance ratio.

The success of semiconductor devices has been mainly driven by an intensive transistor down-scaling process. However, as field effect transistors (FET) approach sizes less than 100 nm, problems such as short channel effect start to prevent proper device operation. Moreover, such sub 100 nm device size can lead to sub-threshold slope non-scaling and increased power dissipation. It is generally believed that transistor based memories such as those commonly known as Flash memory may approach an end to scaling within a decade. Flash memory is one type of non-volatile memory device.

Other non-volatile random access memory (RAM) devices such as ferroelectric RAM (Fe RAM), magneto-resistive RAM (MRAM), organic RAM (ORAM), and phase change RAM (PCRAM), among others, have been explored as next generation memory devices. These devices often require new materials and device structures to couple with silicon based devices to form a memory cell, which lack one or more key attributes. For example, Fe-RAM and MRAM devices have fast switching characteristics and good programming endurance, but their fabrication is not CMOS compatible and size is usually large. Switching for a PCRAM device uses Joules heating, which inherently has high power consumption. Organic RAM or ORAM is incompatible with large volume silicon based fabrication and device reliability is usually poor.

As integration of memory devices increases, the size of elements is reduced while the density of elements in a given area is increased. As a result, dark current or leakage current becomes more of a problem, where leakage current can return a false result for a read operation or cause an unintentional state change in a cell. The problem of leakage current is particularly acute in two-terminal devices, in which multiple memory cells can form leakage paths through interconnecting top and bottom electrodes.

Conventional approaches to suppressing leakage current in switching devices include coupling a vertical diode to a memory element. However, the external diode approach has several disadvantages. In general, the diode fabrication process is a high temperature process, typically conducted above 500 degrees Celsius. Because most diodes rely on a P/N junction, it is difficult to scale the diode height to achieve a memory and diode structure with a desirable aspect ratio. And finally, a conventional diode is only compatible with a unipolar switching device, and not a two-way bipolar device. It is therefore desirable to have a robust and scalable method and structure for a highly integrated memory that is not adversely affected by leak currents.

BRIEF SUMMARY OF THE INVENTION

The present invention is generally related to switching devices. More particularly, the present invention provides a structure and a method for forming a non-volatile memory cell using resistive switching. It should be recognized that embodiments according the present invention have a much broader range of applicability.

In a specific embodiment, a switching device includes a substrate; a first electrode formed over the substrate; a second electrode formed over the first electrode; a switching medium disposed between the first and second electrode; and a nonlinear element disposed between the first and second electrodes and electrically coupled in series to the first electrode and the switching medium. The nonlinear element is configured to change from a first resistance state to a second resistance state on application of a voltage greater than a threshold.

The switching device includes a RRAM in an embodiment.

The switching device include a PCRAM in an embodiment.

The present invention has a number of advantages over conventional techniques. For example, embodiments of the present invention allow for a high density non-volatile memory characterized by high switching speed, low leakage current characteristic, and high device yield. Depending on the embodiment, one or more of these may be achieved. These and other advantages will be described below in more detail in the present specification.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

The present invention is generally directed to a memory device. More particularly, the present invention provides a structure and a method for a resistive switching cell having a nonlinear element. The switching cell may be used in a Resistive Random Access Memory (RRAM) or any highly integrated device. It should be recognized that embodiments of the present invention can have a broader range of applicability. Although the present invention is described with respect to specific embodiments, the embodiments are only used for illustrative purposes and should not be considered limiting.

RRAM is typically a two terminal device in which a switching element is sandwiched between a top electrode and a bottom electrode. The resistance of the switching element is varied by applying a voltage to the electrodes or a current through the switching element. Resistive switching can be bipolar or unipolar. In bipolar switching, the change in resistance of the switching element depends on polarity and a magnitude of a current or voltage based applied electrical signal. In the case of unipolar switching, the change in resistance of the switching element depends only on the magnitude of the applied voltage or current and typically is a result of Joule heating within the switching element. Embodiments of the present invention are explained with respect to a two-terminal RRAM device using bipolar switching, but are not limited thereto. As used herein, the terms “RRAM” or “resistive memory cell” refer to a memory cell or memory device that uses a switching medium whose resistance can be controlled by applying an electrical signal without ferroelectricity, magnetization, and phase change of the switching medium. The present invention is not limited to implementation in RRAM, e.g., the invention may be implemented using the phase change RAM.

FIG. 1illustrates a resistive memory cell100in a non-volatile memory device, e.g., a semiconductor memory chip. The memory cell includes a bottom electrode102, a switching medium104, and a top electrode106according an embodiment of the present invention. The switching medium104exhibits a resistance that can be selectively set to various values and reset using appropriate control circuitry. The memory cell100is a two-terminal resistive memory device, e.g., RRAM, in the present embodiment. Terms such as “top” or “bottom” are used for illustrative purpose only and should not construe to be limiting.

In the present embodiment, the memory cell100is an amorphous-silicon-based resistive memory cell and uses amorphous silicon (a-Si) as the switching medium104. The resistance of the switching medium104changes according to formation or retrieval of a conductive filament inside the switching medium104according to a voltage applied to the electrodes. In an embodiment, the switching medium104is substantially free of dopants. In another embodiment, the switching medium104is a-Si doped with boron. In some embodiments, the resistive switching layer includes a silicon oxide, e.g. a silicon sub oxide, (e.g SixOy, where x 0<y<=1, 0<x<2,) or sub-oxide material such as Ge, SixGey, and SixGeyOz. It should be understood that any such sub-oxide refers to a non-stoichiometric oxide. An example of this is silicon oxide: stoichiometric silicon oxide is SiO2, and non-stoichiometric oxide may be SiOx where 0<x<2. In various embodiments, other forms of non-stoichiometric oxide may be formed or grown using various fabrication techniques.

The top electrode106is a conductive layer containing silver (Ag) and acts as the source of filament-forming ions in the a-Si structure. Although silver is used in the present embodiment, it will be understood that the top electrode106can be formed from various other suitable metals, such as gold (Au), nickel (Ni), aluminum (Al), chromium (Cr), iron (Fe), manganese (Mn), tungsten (W), vanadium (V), and cobalt (Co). In certain embodiments, the bottom electrode102is pure metal, a boron-doped electrode, or other p-type polysilicon or silicon-germanium, which is in contact with a lower-end face of the a-Si structure. In an embodiment, the memory cell100is configured to store more than a single bit of information, e.g., by adjusting the external circuit resistance, as explained in application Ser. No. 12/575,921, filed on Oct. 9, 2009, which is entitled “Silicon-Based Nanoscale Resistive Device with Adjustable Resistance” and is incorporated by reference in its entirety.

FIG. 2illustrates resistance switching characteristics of the memory cell100according to an embodiment of the present invention. The switching medium104displays a bipolar switching effect. The resistance of the switching medium104changes depending on the polarity and magnitude of the voltage signal applied to the switching medium104via the top electrode106and the bottom electrodes102. The memory cell100is changed into an ON state (low resistance state) when a positive voltage equal to or greater than a threshold program voltage (also referred to as a “program voltage”) VPROGRAMis applied. In an embodiment, the program voltage ranges between 1 volt to 5 volts depending on the materials used for the switching medium104and the top electrode106. In another embodiment, the program voltage ranges between 1 volt and 3 volts. The memory cell100is switched back to an OFF state (high resistance state) when a negative voltage equal to or greater than a threshold erase voltage (also referred to as “erase voltage”) VERASEis applied. In an embodiment, the erase voltage ranges from −2 volts to −5 volts. The cell state is not affected if the voltage applied is between two threshold voltages VPROGRAMand VERASE, which enables a low-voltage read process. Once the memory cell100is set to a specific resistance state, the memory cell100retains the information for a certain period (or retention time) without electrical power.

FIG. 2illustrates a current-voltage (I-V) relationship through a switching operation of a non-rectifying memory cell100. Electrical current flows from the top electrode106to the bottom electrode102when the potential applied to the top electrode106is positive potential with respect to the bottom electrode102. On the other hand, current flows in the reverse direction if the potential applied to the top electrode106is negative with respect to the bottom electrode102.

FIGS. 3A and 39illustrate a switching mechanism of the memory cell100during the ON and OFF states according to an embodiment of the present invention. The switching in the switching medium104is based on formation and retrieval of a conductive filament, or a plurality of filaments, in a filament region in the switching medium104according to the program and the erase voltages applied to the bottom electrode102and the top electrode106of the memory cell100.

FIG. 3Aillustrates the memory cell100that is placed in an ON state by applying the program voltage VPROGRAMto the top electrode106. The switching medium104, made of a-Si, is provided between the bottom electrode102and the top electrode106. An upper portion of the switching medium104includes a metallic region (or conductive path)302that extends from the top electrode106to approximately 10 nm above the bottom electrode102. The metallic region302is formed during an electroforming process when a slightly larger voltage than a subsequent switching voltage, e.g., 3˜5 V, is applied to the top electrode106. This large voltage causes the electric field-induced diffusion of the metal ions from the top electrode106toward the bottom electrode102, thereby forming a continuous conductive path312. A lower portion of the switching medium104defines a filament region304, wherein the filament310is formed when the program voltage VPROGRAMis applied after the electroforming process. The continuous conductive path312and the filament310can also be formed together during the electroforming process. The filament310comprises a series of metal particles, which are trapped in defect sites in a lower portion of the switching medium104when the program voltage VPROGRAMapplied provides sufficient activation energy to push a number of metal ions from the metallic region302toward the bottom electrode102.

The filament310is believed to be comprised of a collection of metal particles that are separated from each other by the non-conducting switching medium104and that do not define a continuous conductive path, unlike the continuous conductive path312in the metallic region302. The filament310extends about 2 to 10 nm depending on implementation. The conduction mechanism in an ON state is electrons tunneling through the metal particles in the filament310. The cell resistance is dominated by the tunneling resistance between the metal particle306and the bottom electrode102. The metal particle306is a metal particle in the filament region304that is closest to the bottom electrode102and that is the last metal particle in the filament region304in an ON state.

FIG. 3Billustrates the memory cell100that is placed in an OFF state by applying an erase voltage VERASEto the top electrode106. The erase voltage exerts sufficient electromagnetic force to dislodge the metal particles trapped in the defects sites of the a-Si and retrieves at least part of the filament310from the filament region304. The metal particle308that is closest to the bottom electrode102in an OFF state is separated from the bottom electrode102by a distance greater than the metal particle306during an ON state. This increased distance between the metal particle308and the bottom electrode102places the memory cell100in a high resistance state compared to an ON state. In an embodiment, the resistance ratio between ON/OFF states ranges from 10E3 to 10E7. Memory cell100behaves like a resistor in an ON state and a capacitor in an OFF state (i.e., the switching medium104does not conduct a current in any meaningful amount and behaves as a dielectric in an OFF state). In an implementation, the resistance is 10E5 Ohm in an ON state and 10E10 Ohm in an OFF state. In another implementation, the resistance is 10E4 Ohm in an ON state and 10E9 Ohm in an OFF state. In yet another implementation, the resistance is at least 10E7 Ohm in an OFF state.

FIG. 4illustrates a portion of an array400that is in a crossbar configuration in which the (common) top electrodes and the (common) bottom electrodes are arranged in an orthogonal manner according to an embodiment of the present invention. An array of such crossbar structures includes a plurality of parallel (common) top electrodes and a plurality of parallel (common) bottom electrodes with switching elements disposed between the intersection regions of the (common) top electrodes and the (common) bottom electrodes. Certain limitations may exist in such a configuration, as described below.

Four memory cells402,404,406, and408are shown. Memory cells404and406share a common first top electrode410, while cells402and408share a common second top electrode418. The first top electrode410and the second top electrode418are arranged parallel to each other. Memory cells402and404share a common first bottom electrode412and cells406and408share a common second bottom electrode420. The first bottom electrode412and the second bottom electrode420are spatially arranged parallel to each other. In addition, each of the top electrodes is configured to be non-parallel to each of the bottom electrodes.

To determine a state of a target cell which has a high resistance state, a voltage is applied and a current flowing through the target cell is measured. If some cells in the crossbar array are in low resistance states, the voltage applied to the target cell can cause a leakage current to flow through the untargeted cells instead. In this case the cells causing the leakage, including the target cell, are interconnected through shared electrodes. The leakage current can form a current path, commonly known as a sneak current or a sneak current path, through these untargeted cells. Such a sneak current can cause undesirable behavior in a switching array.

For example, in an exemplary array, cells402,404, and406are at a low resistance ON state, and cell408is at a high resistance OFF state. Because the ON state is characterized by a low resistance, a sneak path416may be formed allowing current to flow through cells402,404, and406. Thus, when a read voltage is applied to target cell408, leakage current flowing along sneak path416may cause an erroneous reading of an ON state result.

In some embodiments, a sneak path can be very short, existing in as few as two forward biased cells and one reverse biased cell. In addition, once started, a sneak path can propagate throughout the array through cells in the ON state. The most common conductive path in a switching array is the shared top and bottom electrodes. Sneak path416is only one example of a sneak path passing leakage current through an array.

To mitigate problems caused by leakage current in a switching array, a nonlinear element (NLE) may be included in a resistive switching device. NLEs can be generally divided into two categories: an NLE that exhibits digital-like behavior, or “digital NLE,” and an NLE that exhibits analog-like behavior, or an “analog NLE,” both of which are described in detail separately below. The categories of digital and analog behavior are not strictly defined, so it is possible for a particular NLE to have properties that are characteristic of both digital and analog behavior, or somewhere in between. In its most basic form, an NLE is an element that has a nonlinear response with respect to voltage, for instance, with a nonlinear I-V relationship. In most embodiments, the relationship is characterized by a high resistance state at low amplitude voltages and a lower resistance state at higher amplitude voltages, with a nonlinear transition from the high resistance state to the low resistance state. Unlike a switching medium, an NLE does not have a memory characteristic; an NLE returns to an original state when a voltage is no longer applied. An NLE that is suitable for suppressing leak currents is characterized by a high resistance state at a low bias, a lower resistance state at a higher bias, and a threshold between the states.

In an embodiment, an NLE is a two terminal device which shows an apparent threshold effect such that the resistance measured below a first voltage is significantly higher than the resistance measured above a second voltage. In a typical embodiment, the resistance below the first voltage is more than 100 times greater than the resistance above the second voltage. In other embodiments, the ratio may be in the range of about 100 to about 500 times, in the range of about 500 times to about 1000 times, in the range of about 1000 times to about 10,000 times, or the like, depending upon specific engineering requirements of the NLE material. In some embodiments, the first and second voltages are different, and are typically referred to as a hold voltage VHOLDand threshold voltage VTH, respectively. In other embodiments, the first voltage and second voltage may be the same. In various embodiments, these relationships may exist in both polarities of voltage, or only in one polarity, and the NLE can be a single material or multiple layers of different materials.

As shown inFIG. 5, to mitigate the effects of leakage current in a memory cell500, an NLE504is electrically coupled in series to the top electrode508, bottom electrode502, and switching medium506. An NLE504may be disposed between the bottom electrode502and switching medium506. In other embodiments, the NLE is disposed between the top electrode508and the switching medium506. Higher temperatures may be experienced by the lower portions of a semiconductor device during various semiconductor processes, so an NLE that is located lower in a stack structure may be designed to withstand higher temperatures than an NLE located further from the substrate.

The behavior of a digital NLE is characterized by abrupt changes in current at certain voltages, which may be referred to as threshold voltages. Such behavior is illustrated inFIG. 6A, which shows the results of a voltage sweep in an embodiment with respect to current on an NLE that is not coupled to a resistive switching device. As positive bias voltage is applied to the NLE, the NLE is in a resistive state characterized by high resistance until it reaches the threshold voltage VTH1. After this threshold has been reached, the NLE will retain its conductive state until the applied voltage drops below a hold voltage VHOLD1. Thus a NLE that is in a conductive state by having a voltage applied above VTH1will continue to have a low resistance so long as a voltage above VHOLD1is supplied to the NLE, after which it reverts to the original high-resistance state. An NLE does not have a memory characteristic, so the same I-V relationship is experienced every time a voltage is applied from an original state.

Referring back toFIG. 6A, when a negative bias voltage is applied that is more negative than a threshold voltage VTH2, an abrupt transition is experienced, and the resistance in the NLE is significantly reduced. The NLE retains its low resistance state until the voltage becomes less negative than a value VHOLD2, at which point the NLE reverts to an original high resistance state. AlthoughFIG. 6Ashows an embodiment with symmetrical I-V behavior between positive and negative bias performance, in other embodiments the relationship is not symmetrical.

FIGS. 6B to 6Eshow I-V relationships of an embodiment where an NLE is coupled to a memory cell (“combined device”), in this case a digital NLE. Memory cell500is an example of such a combined device. If the memory cell depicted in those figures was not coupled to the NLE, it would have an I-V response according toFIG. 2. Turning toFIG. 6B, an I-V curve showing a program operation switching a cell from an initially OFF state to an ON state is shown. To establish a conductive ON state in a cell, a voltage above VPROGRAMCis applied. VPROGRAMCis the program voltage for the combined device, which switches the combined device from an OFF state to an ON state. VHOLDC1is the hold voltage of a combined device, which performs in essentially the same way as VHOLDC1described above. In a preferred embodiment, VHOLD1is less than VTH1, which is less than VPROGRAM.

The relationships between I-V performance in a memory cell, an NLE, and a combined device can also be explained through equations. The equations assume that both the NLE and the switching medium switch instantly (e.g., a few ns˜a few hundreds of ns) when experiencing a threshold voltage. In addition to the definitions given above, the following variables are designated:

RMOFF=The OFF state resistance of a memory element

RMON=The ON state resistance of a memory element

RNOFF=The OFF state resistance of an NLE

RNON=The ON state resistance of an NLE

Using these variables, the relationship between the hold voltage of a combined device and the hold voltage of an NLE can be expressed as:
VHOLDC1=((RMON+RNON)/RNON)VHOLD1

The value for the program voltage of the combined device can be expressed as:
VPROGRAMC≃small{large((RMOFF+RNOFF)/RNOFF)VTH1,VPROGRAM),large(VTH1,((RMOFF+RNOFF)/RMOFF)VPROGRAM)}
Where “small” indicates the smaller of two values in a set, and “large” indicates the larger of two values in a set. In most embodiments, the VPROGRAMis significantly higher than VTH1, and VPROGRAMCis thus similar to VPROGRAM.

FIG. 6Cshows the result of a negative voltage sweep of the same switch in an OFF state. Because it is already in the OFF state, a negative voltage does not cause an erase operation, and the cell remains in a high resistance OFF state.

FIGS. 6D and 6Eshow I-V relationships of a combined device (e.g. memory cell500) where the memory cell is initially in a low-resistance ON state.FIG. 6Dshows a read operation, where the read voltage must be greater than threshold voltage VTHC1to return an accurate read value. As the read voltage drops below the hold voltage VHOLDC1, the resistance in the cell increases substantially. The threshold voltage of the combined device is related to the threshold voltage of the NLE through the following equation:
VTHC1=((RMON+RNOFF)/RNOFF)VTH1≃VTH1
Thus, the read threshold voltage of the combined device is approximately the same as the threshold voltage of the NLE, or VTHC1≅VTH1.

Similarly, as seen inFIG. 6E, an erase operation must overcome a second threshold value VTHC2to allow current to start flowing through the cell, and the switch is changed to a high-resistance OFF state at voltage VERASECLike the positive threshold voltage, the negative threshold voltage of the combined device is about the same as the negative threshold voltage of the NILE. The value of the erase voltage VERASECin a combined device can be expressed as:
VERASEC≃large((RMON+RNON)/RMON)VERASE,VTH2)
The relationship between the negative threshold voltages of a discrete and combined device can be expressed as:
VTHC2=((RMON+RNOFF)/RNOFF)VTH2≃VTH2.
So that in most embodiments, VTHC2≅VTH2.

Various embodiments of a digital NLE can be made of many different materials. For example, a digital NLE can be a threshold device such as a film that experiences a field-driven metal-insulating (Mott) transition. Such materials are known in the art, and include VO2and doped semiconductors. Other threshold devices include material that experiences resistance switching due to electronic mechanisms observed in metal oxides and other amorphous films, or other volatile resistive switching devices such as devices based on anion or cation motion in oxides, oxide heterostructures, or amorphous films. A digital NLE can also be in the form of a breakdown element exhibiting soft breakdown behavior such as SiO2, HfO2, and other dielectrics. Examples of such breakdown elements are described in further detail by application Ser. No. 12/826,653, filed on Jun. 29, 2010, which is entitled “Rectification Element for Resistive Switching for Non-volatile Memory Device and Method,” and is incorporated by reference in its entirety. In other embodiments, the NLE may be a solid electrolyte material. The solid electrolyte material can include be chalcogenide based such as GexSy, GexSey, SbxTey, AgxSey, and CuxSy, or can be metal oxide based such as WOx, TiOx, AlOx, HfOx, CuOx, and TaOx, where 0<x<appropriate stoichiometric value (e.g. 2, 3, etc.) (e.g. GeS, GeSe, WO3, or SbTe, and the like).

As is known in the art, the precise values of threshold, hold, program and erase can be adjusted for different embodiments by changing the form of and materials used for the NLE and the memory cell. In various embodiments the threshold voltage for the NLE can be about the same as the hold voltage, the program voltage, or both. In other embodiments the threshold voltage for the NLE can exceed the program and erase voltages of a resistive switching device.

An analog NLE differs from a digital NLE in that its I-V relationship is characterized by a more gradual transition when current starts to flow through the element. As shown inFIG. 7A, which illustrates the response of an analog NLE to a voltage sweep, the current transition follows an exponential-like curve. The transition or threshold is therefore less abrupt than a digital NLE. Threshold voltage values where substantial current starts to flow through an analog NLE are designated as VAand VBfor positive and negative bias values, respectively. Another significant difference between an analog and digital NLE is that an analog NLE does not experience the hysteretic hold voltage characteristic of a digital NLE.

FIGS. 7B to 7Eshow I-V characteristics of a combined device with an analog NLE. As shown inFIG. 7B, when a program voltage VPROGRAMCis applied to a combined device where the switch is initially in an OFF state, the switch changes to a low resistance ON state. The VPROGRAMCis approximately the sum of the VAof the NLE and the VPROGRAMof the switch as shown inFIG. 2, or VPROGRAMC≈VA+VPROGRAM. As a result, the programming voltage of a combined device with an analog NLE is typically higher than the programming voltage of a switching element alone.

Turning now toFIG. 7C, a negative voltage sweep of a combined device in an OFF state is shown. Because the switch is already in an OFF state, the negative voltage does not induce a state change, and the switch remains in a high resistance state.

FIG. 7Dshows the result of a read operation in a combined switch that is in an ON state. In the present embodiment, VAC<VREAD<VPROGRAMC. Because the switch is already in a low-resistance ON state, current flow above the threshold voltage VACis characterized by low resistance. Circuitry can detect the current flow, resulting in a positive read result. The value tier VAis not affected by the switching apparatus in most embodiments, so typically VAC≈VA.

FIG. 7Eshows an I-V curve for an erase operation in a combined device. To change the switch from the ON state to the OFF state, a voltage of VERASECis applied to the combined device, thereby increasing the resistance of the switch. The voltage required to complete an erase operation in a combined device is normally the sum of the erase value of the discrete switch and the threshold value of the analog NLE, or VERASEC≈VERASE+VB.

An analog NLE can be any element that exhibits the above described behavior. Examples of suitable materials include a punch-through diode, a Zener diode, an impact ionization (or avalanche) element, and a tunneling element such as a tunneling barrier layer. Such elements can be fabricated using standard fabrication techniques.

In most embodiments, |VA, VB|<|VPROGRAM, VERASE|. As is known in the art, the precise threshold values of VA, VB, program, and erase can be adjusted for different embodiments by changing the form of and materials used for the NLE and the memory cell. In various embodiments the threshold voltage for the NLE can be about the same as the program voltage. In other embodiments the threshold voltage can exceed the program and erase voltages.

In other embodiments, a resistive switching cell may be configured to retain multiple resistive states. That is, rather than being configured to have binary states of ON and OFF, a cell can retain a plurality of resistance states. An array of such switches has the same limitations regarding leakage current, and would similarly benefit from the inclusion of an NLE.

FIGS. 8A-Billustrate examples according to various embodiments of the present invention. In various embodiments of the present invention, as discussed inFIG. 4, when a program (or read or erase) voltage is applied to a target cell408, e.g. across second top electrode418and second bottom electrode420, a sneak path416may allow a sneak path current to flow through cells402,404and406. To reduce this, a non-linear element, described above (e.g. NLE504inFIG. 5), was incorporated in each memory cell. The characteristics of an example NLE was illustrated inFIG. 6A. More particularly, when a voltage across the NLE exceeded VTH1 the resistance for the NLE switched from a relatively non-conductive state to a relatively conductive state. Accordingly, in an example, to program target cell408, a program voltage would be applied to target cell408that would exceed VTH1 and exceed the programming voltage of target cell408(VProgram,FIG. 8A). In another example, to read target cell408, a read (or program) voltage would be applied to target cell408that would exceed VTH1, but would be less than the programming voltage of target cell408(VProgram,FIG. 8A).

In an example described in co-pending application Ser. No. 13/290,024, filed Nov. 4, 2011, incorporated by reference above, the read voltage to the target cell was limited to be no greater than three times the threshold voltage of the non-linear element. This three times number assumed that unselected top electrodes and unselected bottom electrodes in the memory array were allowed to float. By way of explanation, using the numbering ofFIG. 4above, inFIG. 8B, the read voltage would not only be applied across target cell408, but also across sneak path416through cells402,404and406. In such a configuration, if the read (or program) voltage exceeded three times the voltage threshold (e.g. 3×VTH1) of the non-linear element, the voltage across non-linear element of402, for example, would also exceed VTH1. Accordingly, the NLE of402would switch to a relatively-conductive state, and significant current could flow through the sneak path416. It was recognized in the above incorporated patent application, that to reduce sneak path current, unselected cells, e.g.402,404and406had to have voltages applied that were lower than the threshold voltage (e.g. VTH1) of the non-linear elements. For example, when the read (or program) voltage (V408) is applied across target cell408, the resultant relationships should be met: voltage across cell(s) V402<VTH1, voltage across cell(s) V404<VTH1, and voltage across cell(s)406<VVTH1. Additionally, the voltages across these unselected cells should be greater than VTH2 (FIG. 8A). By observing such conditions, it is understood that NLEs of unselected cells (along sneak paths) should have voltages across hem such that they remained non-conductive, see suppressed region800inFIG. 8A.

In various embodiments of the present invention, in the example ofFIG. 4, during a read operation (for example), when the read voltage Vread is applied to target cell408, the voltage Vread (e.g. VTH1<Vread (V408)<Vprogram, e.g. Vread=2 volts) is applied to second top electrode418and ground (e.g. Vg, e.g. Vg=0 volts) is applied to the second bottom electrode420. In the case of a program operation V408>Vprogram. To reduce power consumption/requirements of the memory, the inventors have recognized that it is advantageous to set unselected bit lines (e.g. top electrodes/conductors) and unselected word lines (e.g. bottom conductors/electrodes) to voltages other than floating during a read operation. The specific voltages may vary, and are generally guided by the following concepts.

For a read (or program or erase) operation, for memory cells, e.g. memory cells402, that share second top electrode418(e.g. selected bit line), the difference (V402) between the voltage across second top electrode418(VSBL) and unselected word lines, (e.g. first bottom electrode412) (VUSWL) should be less than the voltage threshold of the NLE of memory cells such as memory cell402. In variable format: VSBL−VUSWL<VTH1 or V402<VTH1 (FIG. 8A). This condition would inhibit the NLE memory cells such as memory cell402from entering into relatively non-conductive states. It should be noted that, depending upon the polarity of V402, to inhibit the NLE of memory cells, such as memory cell402from become relatively non-conductive in a reverse-bias condition, the relationship maybe VTH2<V402<VTH1. This was graphically illustrated by the flat region inFIG. 6D(0 to VTHC1), and the flat region inFIG. 6E(VTHC2 to 0), illustrated together in region800inFIG. 8A. These restrictions are desirable also in program or erase operations upon memory cell408. In other memory configurations, these specific relationships and polarities may be changed.

For a read (or program or erase) operation, for memory cells, e.g. memory cells406, that share second bottom electrode420(e.g. selected word line), the difference V406between the voltage across unselected bit lines (e.g. first top electrode410) (VUSBL) and second bottom electrode420(e.g. selected word line) (VSWL) should be less than the voltage threshold of the NLE of memory cells such as memory cell406. In variable format: VUSBL−VSWL<VTH1 V406<VTH1. This condition would inhibit the NLE of memory cells such as memory cell406from entering into relatively non-conductive states. It should be noted that, depending upon the polarity of V406, to inhibit the NLE of memory cells, such as memory cell406from become relatively non-conductive in a reverse-bias, the relationship maybe VTH2<V406<VTH1. This was graphically illustrated by the flat region inFIG. 6D(0 to VTHC1), and the flat region inFIG. 6E(VTHC2 to 0), illustrated together in region800inFIG. 8A. These restrictions are desirable also in program or erase operations upon memory cells404. In various embodiments, VTH1 and |VTH2| may be different, or similar. In other memory configurations, these specific relationships and polarities may be changed.

For a read (or program or erase) operation, for memory cells, e.g. memory cells404, that share unselected word lines (e.g. first bottom electrode412), the difference (V404) between the voltage across unselected bit lines (e.g. first top electrode410) (VUSBL) and unselected word lines (e.g. first bottom electrode412) (VUSWL) should be less than the voltage threshold of the NLE of memory cells such as memory cells404. In variable format: VUSBL−VUSWL<VTH1 or V404<VTH1. This condition would inhibit the NLE of memory cell404from entering into a relatively non-conductive state. It should be noted that depending upon the polarity of V404, to inhibit the NLE of memory cells, such as memory cell404from become relatively non-conductive in a reverse-bias, the relationship maybe VTH2<V404<VTH1. This was graphically illustrated by the flat region inFIG. 6D(0 to VTHC1), and the flat region inFIG. 6E(VTHC2 to 0), illustrated together in region800inFIG. 8A. These restrictions are desirable also in program or erase operations upon memory cells404. In other memory configurations, these specific relationships and polarities may be changed.

FIGS. 8A-Billustrate an example according to various embodiments of the present invention. In one example of the above, the programming voltage Vprogram=2 volts, the positive threshold voltage (VTH1) of the NLE=1 volt, and the negative threshold voltage (VTH2) of the NLE=−2 volts. In such a configuration, to perform a program operation, the selected word line (e.g. second bottom electrode420) is grounded (VSWL=0 volts), and selected bit line (e.g. second top electrode418) (VSBL) is greater than the positive threshold voltage (e.g. VTH1 (1 volt)<VSBL, Vprogram (2 volts)). Thus, Vprogram=V408. Additionally, the unselected word lines (e.g. first bottom electrode412) are set to about 1.5 volts (VUSWL=1.5 volts), accordingly, the voltage across memory cells such as memory cells402are less than the NLE switching voltage (e.g. VTH2 (˜2 volts)<V402(2 volts−1.5 volts=0.5 volts)<VTH1 (1 volts). Further, the unselected bit lines (e.g. first top electrode410) (VUSBL) are set to about 0.5 volts, accordingly, the voltage across memory cells such as memory cells406are thus less than the NLE switching voltage (e.g. VTH2 (−2 volts)<V406(0.5 volts−0 volts=0.5 volts)<VTH1 (1 volts). Still further, from above the unselected bit lines (e.g. first top electrode410) are set to about 0.5 volts (VUSBL=0.5 volts), and the unselected word lines (e.g. first bottom electrode412.) (VUSWL) are set to about 1.5 volts (VUSWL=1.5 volts). In such a configuration, because the bottom electrodes (e.g.412) have a higher voltage than the top electrodes (e.g.410), memory cells, such as memory cells404are in a reverse bias voltage region. Accordingly, the voltage across memory cells such as memory cell404are less than the NLE switching voltage VTH1, but also need to be greater than VTH2: (e.g. VTH2 (−2 volts)<V404(0.5 volts−1.5 volts=−1.0 volts)<VTH1 (1 volts). As mentioned above, these restrictions are also desirable in write and erase operations. For example in a read case VTH1<Vread (V408)<Vprogram; and in an erase case Verase (V408)<VTH2.

In various embodiments, based upon the voltages V408, V402, V406, V404, and the like, the current requirements of memory cells may be computed during read, program, or erase operations. For example, power consumption for memory cells such as memory cells402(along the selected bit line second top electrode418) is the number of cells times the current across memory cells (V402(e.g. 0.5 volts)/resistance of NLE in relatively non-conductive state); plus power consumption for memory cells such as memory cells406(along unselected bit lines, first top electrode410) is the number of cells times the current across memory cells (V406(e.g. 0.5 volts)/resistance of NLE in relatively non-conductive state); plus power consumption for memory cells such as memory cells404(along unselected bit lines, first top electrode410, and along unselected word lines, first bottom electrode412) is the number of cells times the current across the memory cells (V404(e.g. −1 volt)/resistance of NLE in relatively non-conductive state). In some embodiments, setting of the bias voltages of unselected bit lines410(VUSBL) and unselected word lines may412(VUSWL) be made considering the power consumption described above.

In one example, using a large array (e.g. 100×100) of memory cells, if the voltage of the unselected bit lines (e.g. first top electrode410) (VUSBL) and the unselected word lines (e.g. first bottom electrode412) (VUSWL) are substantially the same the voltages, V404is small (e.g. about 0). Accordingly, the power consumption of these memory cells (99 cells×99 cells=9801 cells) is small (e.g. about 0), and power consumed/required is computed, consumed, mainly from the memory cells along the selected bit line418(99 cells along the second top electrode418) and from the memory cells along the selected word line420(99 cells along the second bottom electrode420). In one example of this VSBL=4V, VSWL=0V, VUSBL=2V, VUSWL=2V.

Although certain of the above passages have been described with respect to a read operation, it should be understood that the above also apply to other operations, such as programming operations and erase operations. In each of these situations, embodiments of the present invention incorporating NLE elements within a memory cell help to reduce sneak paths/currents through unselected memory cells. More particularly, for memory cells402,404and406along sneak path416, the voltages across these cells should be within a NLE non-conductive (suppressed) region800, illustrated inFIG. 8A, to reduce sneak path current. This is in comparison with the graph illustrated inFIG. 2, for embodiments without NLE-type elements.

In other embodiments, NLEs with different threshold voltages may be used, resistive switching material having different program and erase voltages may be used, different voltages may be applied to bias unselected word lines and/or unselected bit lines, different polarity materials may be used, and the like. Still other embodiments may be applied to unipolar-type memory cells.

In light of the present patent disclosure, one of ordinary skill in the art will recognize that in other embodiments, the voltages for selected bit lines, unselected bit lines, selected word lines, unselected word lines, NLE threshold voltages, read voltages, and the like may vary from those illustrated above, depending upon specific engineering requirements, e.g. power consumption, performance, and the like

The examples and embodiments described herein are for illustrative purposes only and are not intended to be limiting. Various modifications or alternatives in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this application and scope of the appended claims.