Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device including a plurality of hole patterns is disclosed. The method includes: forming a plurality of first line patterns and a plurality of first space patterns extending in a first direction; forming a plurality of second line patterns and a plurality of second space patterns extending in a second direction, on the plurality of first line patterns and the plurality of first space patterns; forming a plurality of first hole patterns where the plurality of first space patterns and the plurality of second space patterns cross each other; and forming a plurality of second hole patterns where the plurality of first line patterns and the plurality of second line patterns cross each other.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of priority to Korean Patent Application No. 10-2010-0118102, filed on Nov. 25, 2010, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND

The disclosed embodiments relate to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device having a plurality of hole patterns.

As a degree of integration of a semiconductor device increases, the design rule of components of the semiconductor device is decreased. Accordingly, there are several issues involved during a method of manufacturing a minute semiconductor device.

SUMMARY

The disclosed embodiments provide a method of manufacturing a semiconductor device, which effectively forms a semiconductor device having a plurality of hole patterns.

According to one embodiment, there is provided a method of manufacturing a semiconductor device, the method comprising: forming a plurality of first line patterns and a plurality of first space patterns extending in a first direction; forming a plurality of second line patterns and a plurality of second space patterns extending in a second direction, on the plurality of first line patterns and the plurality of first space patterns; forming a plurality of first hole patterns where the plurality of first space patterns and the plurality of second space patterns cross each other; and forming a plurality of second hole patterns where the plurality of first line patterns and the plurality of second line patterns cross each other.

The first and second directions may be not parallel to each other.

The first and second directions may be perpendicular to each other.

The plurality of first line patterns and the plurality of first space patterns may be alternately disposed and each line pattern of the plurality of first line patterns may be immediately adjacent to a space pattern of the plurality of first space patterns, and the plurality of first line patterns and the plurality of first space patterns may be connected as continuous steps, wherein the plurality of first line patterns may be higher than the plurality of first space patterns.

The plurality of second line patterns and the plurality of second space patterns may be alternately disposed and each line pattern of the plurality of first line patterns may be immediately adjacent to a space pattern of the plurality of first space patterns, and the plurality of second line patterns and the plurality of second space patterns may be connected as continuous steps, wherein the plurality of second line patterns may be higher than the plurality of second space patterns.

The forming of the plurality of first line patterns and the plurality of first space patterns may comprise: sequentially stacking a first material layer, a second material layer having a different etching rate from the first material layer, a third material layer having a different etching rate from the second material layer, a fourth material layer having a different etching rate from the third material layer, and a fifth material layer having a different etching rate from the fourth material layer; forming a pattern of the fifth material layer by removing portions corresponding to the plurality of first space patterns from the fifth material layer; and forming a pattern of the fourth material layer by removing part of thickness of the fourth material layer that is exposed by the pattern of the fifth material layer.

The forming of the plurality of second line patterns and the plurality of second space patterns may comprises: forming a sixth material layer that fills all of the plurality of first space patterns, covers all of the plurality of first line patterns, and has a different etching rate from the fifth material layer; forming a seventh material layer having a different etching rate from the sixth material layer on the sixth material layer; forming a pattern of the seventh material layer by removing portions corresponding to the plurality of second space patterns from the seventh material layer; and forming a pattern of the sixth material layer by removing the sixth material layer that is exposed by the pattern of the seventh material layer.

The forming of the pattern of the sixth material layer may comprise forming a second pattern of the fourth material layer by removing portions exposed by the pattern of the fifth material layer from the pattern of the fourth material layer.

The forming of the plurality of first hole patterns may comprise: forming a second pattern of the fifth material layer by removing portions corresponding to the plurality of second space patterns from the pattern of the fifth material layer; forming a pattern of the third material layer by removing the third material layer that is exposed by the second pattern of the fourth material layer; and forming a third pattern of the fourth material layer by removing the second pattern of the fourth material layer exposed by the second pattern of the fifth material layer.

The forming of the plurality of second hole patterns may comprise: filling a pattern of an eighth material layer in portions corresponding to the plurality of first and second space patterns; removing the second pattern of the fifth material layer; removing the third pattern of the fourth material layer; and forming a second pattern of the third material layer by removing the pattern of the third material layer exposed by the pattern of the eighth material layer.

The forming of the plurality of second hole patterns may comprise: forming a third pattern of the third material layer by removing part of a thickness of the pattern of the third material layer exposed by the third pattern of the fourth material layer; removing the third pattern of the fourth material layer; covering the second material layer and the third pattern of the third material layer with a ninth material layer, and forming a pattern of the ninth material layer by planarizing the ninth material layer until an upper surface of the third pattern of the third material layer is exposed; and forming a fourth pattern of the third material layer by removing the third pattern of the third material layer exposed by the pattern of the ninth material layer.

The second material layer may comprise polysilicon, a third material layer may comprise silicon oxide (SiO2), the fourth material layer may comprise an amorphous carbon layer (ACL), and the fifth material layer may comprise silicon oxynitride (SiON).

Each line pattern of the plurality of first line patterns may be spaced a distance of D from the next adjacent line pattern, each line pattern of the plurality of second line patterns may spaced a distance of D from the next adjacent line pattern, and a center of each hole may be spaced a distance less than D away from a center of the closest adjacent hole.

In another embodiment, a method of manufacturing a semiconductor device is disclosed. The method includes sequentially forming a first hard mask layer, a second hard mask layer, and a sacrificial layer; forming a plurality of first space patterns that extend in a first direction on the sacrificial layer, and is are repeatedly disposed separately spaced apart from each other; forming a plurality of second space patterns that extend in a second direction on the plurality of first space patterns, and is are repeatedly disposed separately spaced apart from each other, wherein the second direction is not parallel to the first direction; forming a plurality of first hole patterns penetrating through the second hard mask layer and the first hard mask layer, correspondingly to portions where the plurality of first space patterns and the plurality of second space patterns cross each other; and forming a plurality of second hole patterns penetrating through the second hard mask layer and the first hard mask layer, correspondingly to portions where none of the plurality of first space patterns and the plurality of second space patterns are disposed.

In another embodiment, a method of manufacturing a semiconductor device is disclosed. The method comprises forming a plurality of material layers; forming a first space pattern in a first layer of the material layers, the first space pattern including a plurality of consecutive spaces, each space extending in first direction; forming a second space pattern in a second layer of the material layers, the second space pattern including a plurality of consecutive spaces, each space extending in second direction different from the first direction; forming a first plurality of holes in at least a third layer of the plurality of material layers at locations where spaces of the first space pattern cross spaces of the second space pattern; and forming a second plurality of holes in at least the third layer at locations where areas between spaces of the first space pattern cross areas between spaces of the second space pattern.

The method may include using a first mask pattern to form the first space pattern and to form a first line pattern, wherein lines of the first line pattern occupy areas between spaces of the first space pattern; and using a second mask pattern to form the second space pattern and to form a second line pattern, wherein lines of the second line pattern occupy areas between spaces of the second space pattern.

The method may further comprising filling the first plurality of holes and second plurality of holes with a conductive material.

Each hole of the first plurality of holes may be in closer proximity to a hole of the second plurality of holes than it is to a space adjacent to the space to which its location coincides.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, the exemplary embodiments will be described in detail with reference to the attached drawings.

The embodiments may, however, have many different forms and should not be construed as being limited to those set forth herein. In the drawings, the sizes and thicknesses of layers and regions are exaggerated for clarity.

It will be understood that when an element, such as a layer, a region, or a substrate, is referred to as being “on”, “adjacent to”, “connected to”, or “coupled to” another element, it may be directly on, adjacent to, connected to, or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly on”, “directly connected to” or “directly coupled to” another element, or “contacting” another element, there are no intervening elements present. Like reference numerals refer to like elements throughout. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

The terms “first,” “second,” and the like are used to describe various members, elements, regions, layers and/or parts, but these members, elements, regions, layers and/or parts are not limited by these terms. Unless indicated otherwise, these terms are used only to distinguish one member, element, region, layer, or part from another member, element, region, layer, or part. Accordingly, a first member, element, region, layer, or part may denote a second member, element, region, layer, or part without deviating from the scope of the inventive concept.

Also, relative terms such as “top” or “upper” and “bottom” or “lower” may be used herein to describe a relationship between elements as illustrated in drawings. The relative terms may include other directions in additional to a direction shown in the drawings. For example, when a device is turned over in the drawings, elements that are described to exist on upper surfaces of other elements now exist on lower surfaces of the other elements. Accordingly, the term “upper” used as the example may include “lower” and “upper” directions based on a certain direction of the drawings. If a device faces another direction (90° rotation), the relative terms may be interpreted accordingly.

Embodiments described herein will be described referring to plan views and/or cross-sectional views by way of ideal schematic views. Accordingly, the exemplary views may be modified depending on manufacturing technologies and/or tolerances. Therefore, the disclosed embodiments are not limited to those shown in the views, but include modifications in configuration formed on the basis of manufacturing processes. Therefore, regions exemplified in figures have schematic properties, and shapes of regions shown in figures exemplify specific shapes of regions of elements, and the specific properties and shapes do not limit aspects of the invention.

The terms used herein are to describe embodiments of the disclosure, and not to limit the scope of the inventive concept. As used herein, unless clearly defined otherwise, a singular form may include a plural form. Also, the terms “comprise” and/or “comprising” specify existence of mentioned shapes, numbers, steps, operations, members, elements and/or groups, but do not exclude existence or addition of one or more other shapes, numbers, steps, operations, members, elements and/or groups.

FIG. 1Ais a flowchart illustrating a method of manufacturing a semiconductor device, according to one exemplary embodiment, andFIG. 2Ais a plan view of a semiconductor device manufactured according to the method.

Referring toFIGS. 1A and 2A, the method includes forming a plurality of first line patterns L1and a plurality of first space patterns S1, which extend in a first direction (operation S100), forming a plurality of second line patterns L2and a plurality of second space patterns S2, which extend in a second direction (operation S200), forming a first hole pattern 1STHOLE where the first space pattern S1and the second space pattern S2cross each other (operation S300), and forming a second hole pattern 2NDHOLE where the first line pattern L1and the second line pattern L2cross each other (operation S400). As used herein, a “line pattern” may refer to a single line or a plurality of lines formed in one or more layers, and though depicted as including straight lines, the line patterns are not limited as such. Similarly, a “space pattern” may refer to a single space or a plurality of spaces formed in one or more layers, and though depicted as including straight space patterns, the space patterns are not limited as such. In addition, a “hole pattern” may refer to a single hole, or a plurality of holes that together form a pattern of holes.

The first and second directions are not parallel to each other, and for example, may be perpendicular to each other. However, an angle of the first and second directions is not limited to a right angle, and the first and second directions may form a predetermined angle and be unparallel to each other.

The first line patterns L1and the first space patterns S1are alternately disposed while contacting each other (e.g., each line pattern of the plurality of first line patterns may be immediately adjacent to a space pattern of the plurality of first space patterns), and are connected as continuous steps, wherein the first line pattern L1is higher than the first space pattern S1.

Also, the second line patterns L2and second space patterns S2are alternately disposed while contacting each other (e.g., each line pattern of the plurality of second line patterns may be immediately adjacent to a space pattern of the plurality of second space patterns), and are connected as continuous steps, wherein the second line pattern L2is higher than the second space pattern S2. The line patterns may include, for example, a metal or other conductive material, which may be disposed at a vertical level different from (e.g., higher than) the top surface of the space patterns.

FIG. 1Bis a flowchart illustrating processes of operation S100ofFIG. 1A, andFIG. 2Bis a cross-sectional view of an initial stacked structure100on which the method is to be performed. Also,FIG. 3is a plan view for describing operation S100, andFIGS. 3A,3B, and3C are cross-sectional views respectively taken along lines A-A′, B-B′, and C-C′.

Referring toFIGS. 1B,2B,3,3A,3B, and3C, operation S100, involving the forming of the first line patterns L1and the first space patterns S1, which extend in the first direction, for example, an X-direction inFIG. 3, includes sequentially stacking a first material layer110, a second material layer120having a different etching rate from the first material layer110on the first material layer110, a third material layer130having a different etching rate from the second material layer120on the second material layer120, a fourth material layer140having a different etching rate from the third material layer130on the third material layer130, and a fifth material layer150having a different etching rate from the fourth material layer140on the fourth material layer140(operation S110), forming a pattern150aon the fifth material layer150by removing portions corresponding to the first space pattern S1from the fifth material layer150(operation S120), and forming a pattern140aon the fourth material layer140by removing a part D2of a thickness D1of the fourth material layer140that is exposed by the pattern150aon the fifth material layer150(operation S130).

The initial stacked structure100ofFIG. 2Bis formed via operation S110.

For example, the second material layer120may include polysilicon or silicon nitride, the third material layer130may include silicon oxide (SiO2), the fourth material layer140may include an amorphous carbon layer (ACL), and the fifth material layer150may include silicon oxynitride (SiON). The first material layer110may be a predetermined lower layer, and for example, may be any one of an active region of a semiconductor substrate, a conductive pad, a transistor structure, a word line, a bit line, a lower electrode of a capacitor, an upper electrode of a capacitor, an interlayer wiring layer, an insulation layer pattern, and a rewiring pattern. The first material layer110is not limited to a single layer, and may include various structures therein or thereon.

Thicknesses of the second material layer120, the third material layer130, and the fourth material layer140may be respectively, for example, P1, H1, and D1.

An expression “a B material layer having a different etching rate from an A material layer” used herein contains a meaning that a difference between a speed of etching the A material layer and a speed of etching the B material layer is relatively large under the same etching process conditions, so that significantly different thicknesses of material for the two layers are etched during an etching process.

A structure shown inFIG. 3is formed from the structure shown inFIG. 2B, via operations S120and S130.

In one embodiment, in order to remove a portion corresponding to the first space pattern S1from the fifth material layer150, a mask pattern (not shown), for example, a photoresist pattern, is formed on a portion corresponding to the first line pattern L1on the fifth material layer150, and the pattern150ais formed by etching the fifth material layer150by using the mask pattern as an etch mask. Here, the fifth material layer150corresponding to the first space pattern S1is exposed by the mask pattern and thus may be removed, whereas the fifth material layer150corresponding to the first line pattern L1is covered by the mask pattern, and thus may remain.

Next, the pattern140ais formed by etching the fourth material layer140, by using the mask pattern and/or the pattern150aas an etch mask. Here, since the etching rates of the fourth and fifth material layers140and150are different, the pattern150amay be used as the etch mask while etching the fourth material layer140.

Thicknesses of the pattern140aare different in portions corresponding to the first line pattern L1and the first space pattern S1. For example, the thickness of the pattern140ain the portion corresponding to the first line pattern L1(portion directly below the pattern150a) may be D1, and the thickness of the pattern140ain the portion corresponding to the first space pattern S1may be D3(=D1−D2).

Referring toFIGS. 1C,4,5,4A through4C, and5A through5D, operation S200, involving the forming of the plurality of second line patterns L2and the plurality of second space patterns S2, which extend in the second direction, for example, Y-direction inFIG. 5, includes forming a sixth material layer160, which fills all of the first space patterns S1, covers all of the first line patterns L1, and has a different etching rate from the fifth material layer150(operation S210), forming a seventh material layer170having a different etching rate from the sixth material layer160on the sixth material layer160(operation S220), forming a pattern170aon the seventh material layer170by removing a portion corresponding to the second space pattern S2from the seventh material layer170(operation S230), and forming a pattern160aon the sixth material layer160by removing part of the sixth material layer160exposed by the pattern170a(operation S240).

A structure shown inFIG. 4is formed from the structure shown inFIG. 3, via operations S210and S220.

For example, the sixth material layer160may include a spin-on hard mask (SOH) material, and the seventh material layer170may include SiON.

A thickness of a portion corresponding to the first space pattern S1in the sixth material layer160may be T2, and a thickness of a portion corresponding to the first line pattern L1in the sixth material layer160may be T1. Since a surface of the pattern140ais uneven, the sixth material layer160may flow so as to fill the unevenness of the surface of the pattern140a. Accordingly, the sixth material layer160may include SOH material that has a reflow characteristic, rather than, for example, ACL material that is formed via deposition. Next, the seventh material layer170having the different etching rate from the sixth material layer160may be formed on the entire surface of the sixth material layer160.

A structure shown inFIG. 5is formed from the structure shown inFIG. 4, via operations S230and S240.

Dashed circles inFIG. 5show locations of the first hole pattern 1STHOLE and second hole pattern 2NDHOLE, which are to be formed on a semiconductor device that is finally formed according to the method of one exemplary embodiment.

A mask pattern (not shown), for example, a photoresist pattern, may be formed on a portion corresponding to the second line pattern L2on the seventh material layer170, and then the pattern170amay be formed by removing the seventh material layer170exposed by the mask pattern by using the mask pattern as an etch mask. Accordingly, the pattern170amay be formed only on the portion corresponding to the second line pattern L2.

Next, the pattern160ais formed on the sixth material layer160by etching the sixth material layer160by using the mask pattern and/or the pattern170aas an etch mask. Since an upper surface of the pattern150aof the exposed fifth material layer150may be somewhat etched while forming the pattern160a, a pattern of the fifth material layer150is indicated with a reference numeral150binFIG. 5.

Also, a second pattern140bmay be formed on the fourth material layer140by removing the pattern140aexposed by the pattern150bwhile forming the pattern160aof the sixth material layer160. In other words, since the etching rates of the fifth material layer150and the sixth material layer160are different from each other, the pattern150bmay operate as an etch mask with respect to a predetermined pattern of the fourth material layer140while the pattern160ais formed by etching the sixth material layer160.

For example, while forming the pattern160aon the sixth material layer160including SOH material, the second pattern140bof the fourth material layer140including ACL material may be formed by removing the pattern140aexposed by the pattern150bof the fifth material layer150including SiON.

Since the mask pattern is formed in the portion corresponding to the second line pattern L2, the seventh material layer170and the sixth material layer160are completely removed in the portion corresponding to the second space pattern S2, and at the same time, the pattern140aof the fourth material layer140exposed by the pattern150ais removed, and thus the structure shown inFIG. 5Cis formed from the structure shown inFIG. 4C.

Also, since the mask pattern is formed in the portion corresponding to the second line pattern L2, the seventh material layer170and the sixth material layer160are not entirely removed using the mask pattern in the portion corresponding to the second line pattern L2, and at the same time, the pattern140aexposed by the pattern150ais also not removed, and thus the structure shown inFIG. 5Dis formed from the structure shown inFIG. 4C.

FIG. 5Eis a plan view showing the fourth material layer140of inFIG. 5, in detail, the second pattern140bof the fourth material layer140with a thickness. Dashed circles inFIG. 5Eshow locations of the first hole pattern 1STHOLE and second hole pattern 2NDHOLE, which are to be formed on a semiconductor device that is finally formed according to the method of the current embodiment, for convenience.

Referring toFIG. 5E, a thickness of the second pattern140bis 0 in the portion where the first space pattern S1and the second space pattern S2cross each other (portion where the first hole pattern 1STHOLE is formed via a following process), and is D1in the portion where the first line pattern L1and the second line pattern L2cross each other (portion where the second hole pattern 2NDHOLE is formed via a following process). Also, a thickness of the second pattern140bis D3in the portion where the first space pattern S1and the second line pattern L2cross each other, and is D1in the portion where the second space pattern S2and the first line pattern L1cross each other. In one embodiment, D3is a smaller thickness than D1.

Referring toFIG. 1D,6,7,6A through6D, and7A through7D, operation S300, involving the forming of the first hole pattern 1STHOLE where the first space pattern S1and the second space pattern S2cross each other, includes forming a second pattern150con the fifth material layer150by removing a portion corresponding to the second space pattern S2from the pattern150b(operation S310), forming a pattern130aon the third material layer130by removing the third material layer130exposed by the second pattern140bof the fourth material layer140(operation S320), and forming a third pattern140dof the fourth material layer140by removing a second pattern140cof the fourth material layer140exposed by the second pattern150c(operation S330).

A structure shown inFIG. 6is formed from the structure shown inFIG. 5, via operations S310and S320.

The pattern170aof the seventh material layer170is removed while etching the third material layer130. Also, since a thickness of the sixth material layer160may decrease from T1to T4since the pattern160ais partially removed while etching the third material layer130, a pattern of the sixth material layer160is indicated with a reference numeral160binFIG. 6.

Also, the second pattern150cis formed on the fifth material layer150as an exposed portion (portion corresponding to the second space pattern S2) of the pattern150bis removed while etching the third material layer130. Also, as occasion commands, a thickness of the fourth material layer140may be additionally decreased from D1to D4as the second pattern140bis partially removed, and thus a second pattern of the fourth material layer140is indicated with a reference numeral140cinFIG. 6.

Since the etching rates of the third material layer130and the fourth material layer140are different from each other, the second pattern140cmay operate as an etch mask while the pattern130ais formed by etching the third material layer130.

FIG. 6Eis a plan view showing the fourth material layer140, in detail, the second pattern140cof the fourth material layer140inFIG. 6with its thickness. Dashed circles inFIG. 6Eshow locations of the first hole pattern 1STHOLE and second hole pattern 2NDHOLE, which are to be formed on a semiconductor device that is finally formed according to the method of the current embodiment, for convenience.

Referring toFIG. 6E, a thickness of the second pattern140cis 0 in the portion where the first space pattern S1and the second space pattern S2cross each other (the portion where the first hole pattern 1STHOLE is formed via a following process), and is D1in the portion where the first line pattern L1and the second line pattern L2cross each other (the portion where the second hole pattern 2NDHOLE is formed via a following process). Also, a thickness of the second pattern140cis D3in the portion where the first space pattern S1and the second line pattern L2cross each other, and is D4in the portion where the second space pattern S2and the first line pattern L1cross each other.

Accordingly inFIG. 6, the second pattern140cis not only formed in a portion where the second hole pattern 2NDHOLE is to be formed, but also has a predetermined thickness, such as D3or D4in other portions. According to one exemplary embodiment, a predetermined pattern of the fourth material layer140needs to be formed in the portion where the second hole pattern 2NDHOLE is to be formed, and thus, following processes are performed.

FIG. 6Fis a plan view showing the third material layer130, in detail, the pattern130aof the third material layer130inFIG. 6with its thickness. Dashed circles inFIG. 6Fshow locations of the first hole pattern 1STHOLE and second hole pattern 2NDHOLE, which are to be formed on a semiconductor device that is finally formed according to the method of the current embodiment, for convenience.

Referring toFIG. 6F, a thickness of the pattern130aof the third material layer130is 0 in the portion where the first space pattern S1and the second space pattern S2cross each other (portion where the first hole pattern 1STHOLE is formed via a following process), and is H1in the portion where the first line pattern L1and the second line pattern L2cross each other (portion where the second hole pattern 2NDHOLE is formed via a following process). Also, the thickness of the pattern130ais H1in the portion where the first space pattern S1and the second line pattern L2cross each other, and is H1in the portion where the second space pattern S2and the first line pattern L1cross each other.

Accordingly, the pattern130ais opened in the portion where the first hole pattern 1STHOLE is formed, and has a uniform thickness H1in other portions, inFIG. 6.

A structure shown inFIG. 7is formed from the structure shown inFIG. 6, via operations S330.

Since the etching rates of the fourth material layer140and the fifth material layer150are different from each other, the second pattern150coperates as an etch mask of the second pattern140cwhile the third pattern140dis formed by etching the second pattern140c. Here, the pattern160bmay be pre-removed or removed while etching the second pattern140c.

Also, since an upper surface of the pattern130amay be partially removed when the second pattern140cin the portion corresponding to the first space pattern S1is removed, a pattern of the third material layer130is indicated with a reference numeral130binFIG. 7. Also, since an upper surface of the second pattern150cmay be partially removed while etching the second pattern140c, a second pattern of the fifth material layer150is indicated with a reference numeral150dinFIG. 7.

FIG. 7Eis a plan view showing the fourth material layer140, in detail, the third pattern140dof the fourth material layer140inFIG. 7with its thickness. Dashed circles inFIG. 7Eshow locations of the first hole pattern 1STHOLE and second hole pattern 2NDHOLE, which are to be formed on a semiconductor device that is finally formed according to the method of the current embodiment.

Referring toFIG. 7E, a thickness of the third pattern140dis 0 in the portion where the first space pattern S1and the second space pattern S2cross each other (the portion where the first hole pattern 1STHOLE is formed via a following process), and is D1in the portion where the first line pattern L1and the second line pattern L2cross each other (the portion where the second hole pattern 2NDHOLE is formed via a following process). Also, the thickness of the third pattern140dis 0 in the portion where the first space pattern S1and the second line pattern L2cross each other, and is 0 in the portion where the second space pattern S2and the first line pattern L1cross each other.

Accordingly, the third pattern140dis formed only in a portion where the second hole pattern 2NDHOLE is to be formed inFIG. 7. In other words, a predetermined pattern of the fourth material layer140is formed in a cylinder shape only in a portion where the second hole pattern 2NDHOLE is formed. According to one embodiment, since the predetermined pattern of the fourth material layer140is formed only in the portion where the second hole pattern 2NDHOLE is to be formed in an intermediate process, the structure shown inFIG. 7satisfies such a condition.

FIG. 7Fis a plan view showing the third material layer130, in detail, the pattern130bof the third material layer130inFIG. 7with its thickness. Dashed circles inFIG. 7Fshow locations of the first hole pattern 1STHOLE and second hole pattern 2NDHOLE, which are to be formed on a semiconductor device that is finally formed according to the method of the current embodiment.

Referring toFIG. 7F, a thickness of the pattern130bis 0 in the portion where the first space pattern S1and the second space pattern S2cross each other (the portion where the first hole pattern 1STHOLE is formed via a following process), and is H1in the portion where the first line pattern L1and the second line pattern L2cross each other (the portion where the second hole pattern 2NDHOLE is formed via a following process). Also, a thickness of the pattern130bis H1in the portion where the first space pattern S1and the second line pattern L2cross each other, and is H1in the portion where the second space pattern S2and the first line pattern L1cross each other.

Accordingly, the pattern130bis opened in the portion where the first hole pattern 1STHOLE is to be formed and has uniform thickness H1in other portions inFIG. 7.

Referring toFIGS. 1E,8through11,8A through8D,9A through9D,10A through10D, and11A through11D, operation S400, involving the forming of the second hole pattern 2NDHOLE where the first line pattern L1and the second line pattern L2cross each other, includes filling a pattern180of an eighth material layer (not shown) in a portion corresponding to the first space pattern S1or the second space pattern S2(operation S411), removing the second pattern150d(operation S412), removing the third pattern140d(operation S413), forming a second pattern130con the third material layer130by removing the pattern130bexposed by the pattern180(operation S414), and forming a pattern120aon the second material layer120by removing the second material layer120exposed by the second pattern130c(operation S415).

A structure shown inFIG. 8is formed from the structure shown inFIG. 7, via operation S411.

The eighth material layer is formed on the entire surface of the structure ofFIG. 7, and then is planarized until an upper surface of the second pattern150dis exposed, thereby forming the pattern180. Here, the pattern180is formed in portions corresponding to the first space pattern S1and the second space pattern S2, and fills a space between the second patterns150d, between the third patterns140d, and between the patterns130b.

A thickness of the pattern180contacting an upper surface of the pattern130bmay be J1, and a thickness of the pattern180contacting an upper surface of the second material layer120may be J2.

The eighth material layer may include, for example, polysilicon.

FIG. 8Eis a plan view showing the fourth material layer140, in detail, the third pattern140dof the fourth material layer140inFIG. 8with its thickness. Dashed circles inFIG. 8Eshow locations of the first hole pattern 1STHOLE and second hole pattern 2NDHOLE, which are to be formed on a semiconductor device that is finally formed according to the method of the current embodiment.

Referring toFIG. 8E, a thickness of the third pattern140dis 0 in the portion where the first space pattern S1and the second space pattern S2cross each other (the portion where the first hole pattern 1STHOLE is formed via a following process), and is D1in the portion where the first line pattern L1and the second line pattern L2cross each other (the portion where the second hole pattern 2NDHOLE is formed via a following process). Also, the thickness of the third pattern140dis 0 in the portion where the first space pattern S1and the second line pattern L2cross each other, and is 0 in the portion where the second space pattern S2and the first line pattern L1cross each other.

Accordingly, a predetermined pattern of the fourth material layer140is formed only in the portion where the second hole pattern 2NDHOLE is to be formed inFIG. 8, likeFIG. 7.

FIG. 8Fis a plan view showing the third material layer130, in detail, the pattern130bof the third material layer130inFIG. 8with its thickness. Dashed circles inFIG. 8Fshow locations of the first hole pattern 1STHOLE and second hole pattern 2NDHOLE, which are to be formed on a semiconductor device that is finally formed according to the method of the current embodiment, for convenience.

Referring toFIG. 8F, a thickness of the pattern130bis 0 in the portion where the first space pattern S1and the second space pattern S2cross each other (the portion where the first hole pattern 1STHOLE is formed via a following process), and is H1in the portion where the first line pattern L1and the second line pattern L2cross each other (the portion where the second hole pattern 2NDHOLE is formed via a following process). Also, the thickness of the pattern130bis H1in the portion where the first space pattern S1and the second line pattern L2cross each other, and is H1in the portion where the second space pattern S2and the first line pattern L1cross each other.

Accordingly, the pattern130bis opened in the portion where the first hole pattern 1STHOLE is formed and has a uniform thickness H1in other portions inFIG. 8, likeFIG. 7.

FIG. 8Gis a plan view showing the eighth material layer, in detail, the pattern180of the eighth material layer inFIG. 8with its thickness. Dashed circles inFIG. 8Gshow locations of the first hole pattern 1STHOLE and second hole pattern 2NDHOLE, which are to be formed on a semiconductor device that is finally formed according to the method of the current embodiment, for convenience.

Referring toFIG. 8G, a thickness of the pattern180is J2in the portion where the first space pattern S1and the second space pattern S2cross each other (the portion where the first hole pattern 1STHOLE is formed via a following process), and is 0 in the portion where the first line pattern L1and the second line pattern L2cross each other (the portion where the second hole pattern 2NDHOLE is formed via a following process). Also, the thickness of the pattern180is J1in the portion where the first space pattern S1and the second line pattern L2cross each other, and is J1in the portion where the second space pattern S2and the first line pattern L1cross each other.

Accordingly, the thickness of the pattern180is J2in the portion where the first hole pattern 1STHOLE is to be formed, is 0 in the portion where the second hole pattern 2NDHOLE is to be formed, and is J1in other portions inFIG. 8. Here, J2has a larger value than J1.

A structure shown inFIG. 9is formed from the structure shown inFIG. 8, via operations S412and S413.

First, the third pattern140dis exposed when the second pattern150dis removed. The exposed third pattern140dis etched.

FIG. 9Eis a plan view showing the fourth material layer140, in detail, the third pattern140dof the fourth material layer140inFIG. 9with its thickness. Dashed circles inFIG. 9Eshow locations of the first hole pattern 1STHOLE and second hole pattern 2NDHOLE, which are to be formed on a semiconductor device that is finally formed according to the method of the current embodiment, for convenience.

Referring toFIG. 9E, a thickness of the third pattern140dis 0 in the portion where the first space pattern S1and the second space pattern S2cross each other (the portion where the first hole pattern 1STHOLE is formed via a following process), and is 0 in the portion where the first line pattern L1and the second line pattern L2cross each other (the portion where the second hole pattern 2NDHOLE is formed via a following process). Also, the thickness of the third pattern140dis 0 in the portion where the first space pattern S1and the second line pattern L2cross each other, and is 0 in the portion where the second space pattern S2and the first line pattern L1cross each other.

Accordingly, a predetermined pattern of the fourth material layer140is completely removed inFIG. 9. However, by removing the third pattern140dofFIG. 8that is disposed in the portion corresponding to the second hole pattern 2NDHOLE, the portion that is exposed and opened by the pattern180becomes identical to the portion where the second hole pattern 2NDHOLE is to be formed.

FIG. 9Fis a plan view showing the third material layer130, in detail, the pattern130bof the third material layer130inFIG. 9with its thickness. Dashed circles inFIG. 9Fshow locations of the first hole pattern 1STHOLE and second hole pattern 2NDHOLE, which are to be formed on a semiconductor device that is finally formed according to the method of the current embodiment.

Referring toFIG. 9F, a thickness of the pattern130bis 0 in the portion where the first space pattern S1and the second space pattern S2cross each other (the portion where the first hole pattern 1STHOLE is formed via a following process), and is H1in the portion where the first line pattern L1and the second line pattern L2cross each other (the portion where the second hole pattern 2NDHOLE is formed via a following process). The thickness of the pattern130bis H1in the portion where the first space pattern S1and the second line pattern L2cross each other, and is H1in the portion where the second space pattern S2and the first line pattern L1cross each other.

Accordingly, the pattern130bis opened in the portion where the first hole pattern 1STHOLE is formed, and has a uniform thickness H1in other portions inFIG. 9.

A structure shown inFIG. 10is formed from the structure shown inFIG. 9, via operation S414.

The second pattern130cis formed by removing the pattern130bexposed by the pattern180. Since the etching rates of the third material layer130and the eighth material layer are different from each other, for example, the etching rates may be significantly different such that an etching selectivity between silicon oxide and polysilicon is higher than 1, the pattern180of the eighth material layer may operate as an etch mask while etching the pattern130b.

FIG. 10Eis a plan view showing the third material layer130, in detail, the second pattern130cof the third material layer130inFIG. 10with its thickness. Dashed circles inFIG. 10Eshow locations of the first hole pattern 1STHOLE and second hole pattern 2NDHOLE, which are to be formed on a semiconductor device that is finally formed according to the method of the current embodiment.

Referring toFIG. 10E, a thickness of the second pattern130cis 0 in the portion where the first space pattern S1and the second space pattern S2cross each other (the portion where the first hole pattern 1STHOLE is formed via a following process), and is 0 in the portion where the first line pattern L1and the second line pattern L2cross each other (the portion where the second hole pattern 2NDHOLE is formed via a following process). Also, the thickness of the second pattern130cis H1in the portion where the first space pattern S1and the second line pattern L2cross each other, and is H1in the portion where the second space pattern S2and the first line pattern L1cross each other.

The second pattern130cis opened in both portions corresponding to the first hole pattern 1STHOLE and the second hole pattern 2NDHOLE, and has a uniform thickness of H1in the other portions. Accordingly, the first and second hole patterns 1STHOLE and 2NDHOLE are formed inFIG. 10.

A structure shown inFIG. 11is formed from the structure shown inFIG. 10, via operation S415.

The first and second hole patterns 1STHOLE and 2NDHOLE are already formed on the second pattern130cinFIG. 10. If the first and second hole patterns 1STHOLE and 2NDHOLE are to be continuously formed on the second material layer120constituting a lower layer, the pattern120ais formed by removing the second material layer120exposed by the second pattern130c. Here, the pattern120aalso includes the first and second hole patterns 1STHOLE and 2NDHOLE.

When a cover layer (not shown) formed of the same material as the eighth material layer is formed to cover the entire surface of the structure shown inFIG. 10and an etch back process is performed on the cover layer, the cover layer and the pattern180are removed, and the second material layer120exposed by the second pattern130cis continuously removed, thereby forming the pattern120a.

An upper surface of the second pattern130cmay be partially removed while forming the pattern120a, and thus, a second pattern of the third material layer130is indicated with a reference numeral130dinFIG. 11.

FIG. 11Eis a plan view showing the third material layer130, in detail, the second pattern130dof the third material layer130inFIG. 11with its thickness, andFIG. 11Fis a plan view showing the second material layer120, in detail, the pattern120aof the second material layer120ofFIG. 11with its thickness.

Referring toFIGS. 11E and 11F, a predetermined pattern of the second material layer120and a predetermined pattern of the third material layer130exist in both portions where the first space pattern S1and the second line pattern L2cross each other and where the second space pattern S2and the first line pattern L1cross each other, are opened in the portion where the first space pattern S1and the second space pattern S2cross each other to form the first hole pattern 1STHOLE, and are opened in the portion where the first line pattern L1and the second line pattern L2cross each other to form the second hole pattern 2NDHOLE.

Next, operation S400according to another embodiment is described.

Referring toFIGS. 1F,12through15,12A through12D,13A through13D,14A through14D, and15A through15D, operation S400, involving forming of the second hole pattern 2NDHOLE where the first line pattern L1and the second line pattern L2cross each other, includes forming a third pattern130eby removing the pattern130bexposed by the third pattern140dup to a part H3of thickness of the pattern130b(operation S421), removing a third pattern140eof the fourth material layer140(operation S422), forming a pattern190of a ninth material layer (not shown) by covering a second material layer120eand the third pattern130ewith the ninth material layer and planarizing the ninth material layer until an upper surface of the third pattern130eis exposed (operation S423), forming a fourth pattern130fof the third material layer130by removing the third pattern130eexposed by the pattern190(operation S424), and forming a second pattern120gof the second material layer120by removing the second material layer120exposed by the fourth pattern130f(operation S425).

A structure shown inFIG. 12is formed from the structure shown inFIG. 7, via operation S421.

The third pattern130eis formed by removing the pattern130bexposed by the third pattern140donly up to the part H3of the thickness H1of the pattern130b. Also, since the upper surface of the second material layer120exposed in the portion corresponding to the second space pattern S2may be partially removed while forming the third pattern130e, the second material layer120is indicated as the second material layer120einFIG. 12.

FIG. 12Eis a plan view showing the third material layer130of inFIG. 12, in detail, the third pattern130eof the third material layer130with its thickness. Dashed circles inFIG. 12Eshow locations of the first hole pattern 1STHOLE and second hole pattern 2NDHOLE, which are to be formed on a semiconductor device that is finally formed according to the method of the current embodiment.

Referring toFIG. 12E, a thickness of the third pattern130eis 0 in the portion where the first space pattern S1and the second space pattern S2cross each other (the portion where the first hole pattern 1STHOLE is formed via a following process), and is H1in the portion where the first line pattern L1and the second line pattern L2cross each other (the portion where the second hole pattern 2NDHOLE is formed via a following process). Also, the thickness of the third pattern130eis H2in the portion where the first space pattern S1and the second line pattern L2cross each other, and is H2in the portion where the second space pattern S2and the first line pattern L1cross each other.

Accordingly, the third pattern130eis opened only in the portion corresponding to the first hole pattern 1STHOLE, and has a predetermined thickness H1or H2in other portions inFIG. 12. Specifically, the third pattern130ehas the thickness H1that is higher than the thickness H2so that the portion corresponding to the second hole pattern 2NDHOLE is higher than other portions.

A structure shown inFIG. 13is formed from the structure shown inFIG. 12, via operations S422and S423.

The third pattern140eis entirely removed. InFIG. 12, the third pattern140eonly exists in the portion corresponding to the second hole pattern 2NDHOLE.

Next, the second material layer120eand the third pattern130eare covered by the ninth material layer, and the ninth material layer is planarized until the upper surface of the third pattern130eis exposed, thereby forming the pattern190. Since the upper surface of the third pattern130eis higher in the portion corresponding to the second space pattern S2than the portion corresponding to the first space pattern S1(H1>H2), the upper surface of the pattern190in the portion corresponding to the first space pattern S1is higher than the upper surface of the third pattern130e, and the upper surface of the pattern190in the portion corresponding to the first line pattern L1has the same height as the upper surface of the third pattern130e.

FIG. 13Eis a plan view showing the third material layer130ofFIG. 13, in detail, the third pattern130eof the third material layer130with its thickness. Dashed circles inFIG. 13Eshow locations of the first hole pattern 1STHOLE and second hole pattern 2NDHOLE, which are to be formed on a semiconductor device that is finally formed according to the method of the current embodiment.

Referring toFIG. 13E, a thickness of the third pattern130eis 0 in the portion where the first space pattern S1and the second space pattern S2cross each other (the portion where the first hole pattern 1STHOLE is formed via a following process), and is H1in the portion where the first line pattern L1and the second line pattern L2cross each other (the portion where the second hole pattern 2NDHOLE is formed via a following process). Also, the thickness of the third pattern130eis H2in the portion where the first space pattern S1and the second line pattern L2cross each other, and is H2in the portion where the second space pattern S2and the first line pattern L1cross each other.

Accordingly, the third pattern130eis opened only in the portion corresponding to the first hole pattern 1STHOLE, and has a predetermined thickness H1or H2in other portions inFIG. 13. Specifically, the pattern130ehas the thickness H1that is higher than the thickness H2so that the portion corresponding to the second hole pattern 2NDHOLE is higher than other portions.

A structure shown inFIG. 14is formed from the structure shown inFIG. 13, via operation SS424.

The third pattern130eexposed by the pattern190is disposed in the portion corresponding to the second hole pattern 2NDHOLE. Accordingly, the fourth pattern130fincludes a structure in which the second hole pattern 2NDHOLE is opened.

Since an upper surface of the second material layer120eexposed in the portion corresponding to the first line pattern L1may be partially removed while forming the fourth pattern130f, the second material layer120eis indicated as a second material layer120finFIG. 14.

FIG. 14Eis a plan view showing the third material layer130, in detail, the fourth pattern130fof the third material layer130inFIG. 14Ewith its thickness. Dashed circles inFIG. 14Eshow locations of the first hole pattern 1STHOLE and second hole pattern 2NDHOLE, which are to be formed on a semiconductor device that is finally formed according to the method of the current embodiment.

Referring toFIG. 14E, a thickness of the fourth pattern130fis 0 in the portion where the first space pattern S1and the second space pattern S2cross each other (the portion where the first hole pattern 1STHOLE is formed via a following process), and is 0 in the portion where the first line pattern L1and the second line pattern L2cross each other (the portion where the second hole pattern 2NDHOLE is formed via a following process). Also, the thickness of the fourth pattern130fis H2in the portion where the first space pattern S1and the second line pattern L2cross each other, and is H2in the portion where the second space pattern S2and the first line pattern L2cross each other.

Accordingly, the fourth pattern130fis opened in both portions corresponding to the first and second hole patterns 1STHOLE and 2NDHOLE, and has a uniform thickness H2in other portions inFIG. 14. Thus, the first and second hole patterns 1STHOLE and 2NDHOLE are formed inFIG. 14.

A structure shown inFIG. 15is formed from the structure shown inFIG. 14, via operation S425.

The first and second hole patterns 1STHOLE and 2NDHOLE are already formed in the fourth pattern130finFIG. 14. If the first and second hole patterns 1STHOLE and 2NDHOLE are to be continuously formed on the second material layer120fconstituting a lower layer, the second pattern120gis formed by removing the second material layer120fexposed by the fourth pattern130f. Here, the first and second hole patterns 1STHOLE and 2NDHOLE are also formed in the second pattern120g.

Since an upper surface of the fourth pattern130fmay be partially removed while forming the second pattern120g, a fourth pattern of the third material layer130is indicated as a fourth pattern130ginFIG. 15.

FIG. 15Eis a plan view showing the third material layer130, in detail, the fourth pattern130gof the third material layer130inFIG. 15with its thickness.FIG. 15Fis a plan view showing the second material layer120, in detail, the second pattern120gof the second material layer120inFIG. 15with its thickness.

Referring toFIGS. 15E and 15F, a predetermined pattern of the second material layer120and a predetermined pattern of the third material layer130exist in both portions where the first space pattern S1and the second line pattern L2cross each other and where the second space pattern S2and the first line pattern L1cross each other, are opened in the portion where the first space pattern S1and the second space pattern S2cross each other to form the first hole pattern 1STHOLE, and are opened in the portion where the first line pattern L1and the second line pattern L2cross each to form the second hole pattern 2NDHOLE. As such, an array of holes including holes extending in two directions (when viewed from a plan view) and having a tightly compact configuration are created in two layers disposed on a substrate, by using two mask etching processes that occur at different times—e.g., a first etch mask process that uses a line pattern in a first direction, and a second etch mask process that uses a line pattern in a second direction. As a result, in one embodiment, groups of 4 adjacent holes are formed in a diamond shaped pattern with respect to the first direction and the second direction.

The embodiments of one exemplary method have been described above. Hereinafter, the embodiments will be described in a different perspective.

FIG. 1Gis a flowchart illustrating a method of manufacturing a semiconductor device, according to another exemplary embodiment,FIG. 1His a flowchart illustrating processes of operation S400′ of the method ofFIG. 1G, according to an embodiment of the present invention, andFIG. 1Iis a flowchart illustrating processes of operation S400′ of the method ofFIG. 1G, according to another embodiment of the present invention.

Referring toFIGS. 1G,1H, and1I, the method includes forming the plurality of first space patterns S1ofFIG. 3, which extend in the first direction on the sacrificial layer140ofFIG. 2Band are repeatedly disposed separately apart from each other, for example, in a parallel line arrangement, after sequentially forming the first hard mask layer120ofFIG. 2B, the second hard mask layer130ofFIG. 2B, and the sacrificial layer140ofFIG. 2B(operation S100′), forming the plurality of second space patterns S2ofFIG. 5, which extend in the second direction that is not parallel to the first direction on the plurality of first space patterns S1and are repeatedly disposed separately apart from each other (operation S200′), for example, in a parallel line arrangement, forming the first hole pattern 1STHOLE ofFIGS. 6 and 7that penetrates the second hard mask layer130and the first hard mask layer120correspondingly to the portion where the first space pattern S1and the second space pattern S2cross each other (operation S300′), and forming the second hole pattern 2NDHOLE ofFIGS. 10 and 11that penetrates the second hard mask layer130and the first hard mask layer120correspondingly to portions where none of the first and second space patterns S1and S2are disposed (operation S400′).

Operations S100′ through S400′ ofFIG. 1Grespectively have the same structures as operations S100through S400ofFIG. 1A. However, the second material layer120, the third material layer130, and the fourth material layer140ofFIG. 1Amay be respectively a first hard mask layer120, the second hard mask layer130, and the sacrificial layer140. Accordingly, descriptions about each operation of the method ofFIG. 1Gmay be replaced by those ofFIG. 1A, since technical aspects of the methods ofFIGS. 1A and 1Gare the same.

Referring toFIG. 1H, operation S400′ according to an embodiment may include forming the second hard mask layer pattern130aofFIG. 6having a uniform thickness H1ofFIG. 6Fcorrespondingly to the portion where the first hole pattern is not formed (operation S431), forming the pillar pattern140dofFIGS. 7B and 7Dof the sacrificial layer140on the second hard mask layer pattern130acorrespondingly to the portion where the second hole pattern is formed (operation S432), forming the third hard mask layer pattern180ofFIG. 8on the entire surface so that the upper surface of the pillar pattern140dis exposed (operation S433), removing the pillar pattern140d(operation S434), and removing an exposed part of the second hard mask layer pattern130aby removing the pillar pattern140dfrom the second hard mask layer pattern130a(operation S435).

The structure shown inFIG. 6is formed from the structure shown inFIG. 5, via operation S431.

The structure shown inFIG. 7is formed from the structure shown inFIG. 6, via operation S432.

The structure shown inFIG. 8is formed from the structure shown inFIG. 7, via operation S433.

The structure shown inFIG. 9is formed from the structure shown inFIG. 8, via operation S434.

Also, the structure shown inFIG. 10is formed from the structure shown inFIG. 9, via operation S435.

Descriptions about each operation are identical to those that have been described above with reference to the same diagrams, and thus, will not be repeated herein.

Referring toFIG. 11, operation S400′ according to another embodiment may include forming the second hard mask layer pattern130aofFIG. 6having the uniform thickness H1ofFIG. 6Fcorrespondingly to the portion where the first hole pattern is not formed (operation S441), forming the pillar pattern140dofFIGS. 7B and 7Dof the sacrificial layer140on the second hard mask layer pattern130acorrespondingly to the portion where the second hole pattern is formed (operation S442), forming the second pattern130eofFIG. 12of the second hard mask layer130aby removing the second hard mask layer pattern130aexposed by the pillar pattern140donly up to the part H3ofFIGS. 12B and 12Dof the thickness of the second hard mask layer pattern130a(operation S443), removing the pillar pattern140eofFIG. 12(operation S444), forming the fourth hard mask layer pattern190ofFIG. 13on the entire surface so that the upper surface of the second pattern130eof the second hard mask layer pattern130ais exposed (operation S445), and removing the second pattern130eexposed by the fourth hard mask layer pattern190from the second pattern130e(operation S446).

The structure shown inFIG. 6is formed from the structure shown inFIG. 5, via operation S441.

The structure shown inFIG. 7is formed from the structure shown inFIG. 6, via operation S442.

The structure shown inFIG. 12is formed from the structure shown inFIG. 7, via operation S443.

The structure shown inFIG. 13is formed from the structure shown inFIG. 12, via operations S444and S445.

The structure shown inFIG. 14is formed from the structure shown inFIG. 13, via operation S446.

Descriptions about each operation are identical to those that have been described above with reference to the same diagrams, and thus, will not be repeated herein.

A method of forming a hole pattern by using a layout including a line pattern and a space pattern has been described above. The hole pattern may be used variously in a semiconductor device. For example, the hole pattern may be used as a contact pattern of a semiconductor device by filling the hole pattern with a conductive material. The contact pattern may electrically connect an upper structure above the hole pattern and a lower structure below the hole pattern. In the semiconductor device, the upper structure and the lower structure may each be at least one of an active region of a semiconductor substrate, a conductive pad, a transistor structure (e.g., a source, drain, or gate of a transistor, such as a MOSFET), a word line, a bit line, a lower electrode of a capacitor, an upper electrode of a capacitor, an interlayer wiring layer, and a rewiring pattern (e.g., to connect, in one embodiment, chip pads of a first chip to package substrate terminals of a package). In other embodiments, the holes may be filled with different materials to form part of a PRAM, 3-d NAND flash memory, RRAM, or other types of semiconductor memory devices.

FIGS. 16A and 16Bare cross-sectional views of a contact pattern formed by filling a hole pattern with a conductive material, which is formed according to a method of manufacturing a semiconductor device, according to one exemplary embodiment.

FIG. 16Ais a cross-sectional view taken along a line A-A′ ofFIG. 2Athat illustrates a semiconductor device manufactured by using the method according to one exemplary embodiment, andFIG. 16Bis a cross-sectional view taken along a line B-B′ ofFIG. 2A.

Referring toFIGS. 16A and 16B, a hole pattern including a first hole pattern and a second hole pattern is defined as a predetermined pattern120mof a second material layer and a predetermined pattern130mof a third material layer.

The predetermined patterns120mand130mmay respectively be the pattern120aand the second pattern130dshown inFIGS. 11A through 11D.

Alternatively, the predetermined patterns120mand130mmay respectively be the second pattern120gand the fourth pattern130gshown inFIGS. 15A through 15D.

The hole pattern (the first and second hole patterns) defined as the predetermined patterns120mand130mare filled with a conductive material, and thus, a contact pattern210is formed.

Also, first material layers110aand110bformed below the hole pattern may be at least one of an active region of a semiconductor substrate, a conductive pad, a transistor structure, a word line, a bit line, a lower electrode of a capacitor, an upper electrode of a capacitor, an interlayer wiring layer, an insulation layer pattern, and a rewiring pattern. The first material layer110is not limited to a single layer, and may include various structures therein or thereon. For example, the first material layer110bmay be a conductive structure as it contacts the contact pattern210, and the first material layer110amay be an insulation structure separating the conductive structures.

FIGS. 17A and 17Bare cross-sectional views of a contact pattern formed by filling a hole pattern with a conductive material, which is formed according to a method of manufacturing a semiconductor device, according to another exemplary embodiment.

FIG. 17Ais a cross-sectional view taken along a line A-A′ ofFIG. 2Athat illustrates a semiconductor device manufactured by using the method according to another exemplary embodiment, andFIG. 17Bis a cross-sectional view taken along a line B-B′ ofFIG. 2A.

Referring toFIGS. 17A and 17B, the hole pattern including a first hole pattern and a second hole pattern is defined as a predetermined pattern120nof a second material layer.

The predetermined pattern120nmay be the pattern120afrom which the second pattern130dshown inFIGS. 11A through 11Dis removed.

Alternatively, the predetermined pattern120nmay be the second pattern120gfrom which the fourth pattern130gshown inFIGS. 15A through 15Dis removed.

The hole pattern (the first and second hole patterns) defined as the predetermined pattern120nis filled with a conductive material, thereby forming a contact pattern220.

Also, the first material layers110aand110bformed below the hole pattern may be at least one of an active region of a semiconductor substrate, a conductive pad, a transistor structure, a word line, a bit line, a lower electrode of a capacitor, an upper electrode of a capacitor, an interlayer wiring layer, an insulation layer pattern, and a rewiring pattern. Also, the first material layer110is not limited to a single layer, and may include various structures therein or thereon. For example, the first material layer110bmay be a conductive structure as it contacts the contact pattern220, and the first material layer110amay be an insulation structure separating the conductive structures.

FIGS. 18A and 18Bare cross-sectional views of a contact pattern formed by filling a hole pattern with a conductive material, which is formed according to a method of manufacturing a semiconductor device, according to another exemplary embodiment.

FIG. 18Ais a cross-sectional view taken along a line A-A′ ofFIG. 2Athat illustrates a semiconductor device manufactured by using the method according to another exemplary embodiment, andFIG. 18Bis a cross-sectional view taken along a line B-B′ ofFIG. 2A.

Referring toFIGS. 18A and 18B, the hole pattern including first and second hole patterns is defined as a predetermined pattern130pof a third material layer.

A structure shown inFIGS. 18A and 18Bis formed from the initial stacked structure100ofFIG. 2B, wherein the first, third, fourth, and fifth material layers110,130,140, and150are sequentially stacked in the initial stacked structure100, but the second material layer120is not stacked. Operations afterward are identical to those described with reference toFIGS. 3 through 15, except the description about the second material layer120, and thus, descriptions about the operations afterward will not be repeated.

The predetermined pattern130pmay be the second pattern130dof the third material layer130shown inFIGS. 11A through 11D.

Alternatively, the predetermined pattern130pmay be the fourth pattern130gof the third material layer shown inFIGS. 15A through 15D.

A contact pattern230is formed by filling the hole pattern (the first and second hole patterns) defined as the predetermined pattern130pwith a conductive material.

Also, the first material layers110aand110bformed below the hole pattern may be at least one of an active region of a semiconductor substrate, a conductive pad, a transistor structure, a word line, a bit line, a lower electrode of a capacitor, an upper electrode of a capacitor, an interlayer wiring layer, an insulation layer pattern, and a rewiring pattern. Also, the first material layer110is not limited to a single layer, and may include various structures therein or thereon. For example, the first material layer110bmay be a conductive structure as it contacts the contact pattern230, and the first material layer110amay be an insulation structure separating the conductive structures.

As described above, a hole pattern is formed by using a layout including a line pattern and a space pattern. In other words, a photomask is manufactured by using the layout including the line pattern and the space pattern, and a plurality of hole patterns may be formed on a semiconductor substrate by performing a developing process and an etching process. A photomask that specifically uses an arrangement including the hole layout to be formed need not be used.

Referring toFIG. 2A, the first line patterns L1extending in the first direction, the first space patterns S1extending in the first direction, the second line patterns L2extending in the second direction, and the second space patterns S2extending in the second direction may each be spaced apart from each other by a first distance, such as 2F. However, the first and second hole patterns 1STHOLE and 2NDHOLE formed accordingly are spaced apart from each other by a second distance, such as 1F, which may is smaller than 2F (e.g., in one embodiment, half of 2F). Accordingly, a minute, tightly compact hole pattern may be formed while obtaining an acceptable process margin.

InFIG. 19, it is assumed that a plurality of the hole patterns are formed by manufacturing a photomask by using a layout including the hole pattern and performing a developing process and an etching process.

FIG. 19is a plan view for describing forming a hole pattern on a semiconductor substrate by using a layout including a hole pattern, according to one exemplary embodiment.

Referring toFIG. 19, when a hole pattern is formed by using a layout on which a pattern320corresponding to a first hole pattern and a pattern310corresponding to a second hole pattern are simultaneously disposed, a distance between the plurality of hole patterns is 1F. Accordingly, it is not convenient to form a hole pattern as a process margin is small.

FIGS. 20A and 20Bare plan views for describing forming a hole pattern on a semiconductor substrate by using a layout including a hole pattern, according to another exemplary embodiment.

InFIG. 20A, a hole pattern is formed on a semiconductor substrate by using a layout including the pattern310corresponding to the second hole pattern, and inFIG. 20B, a hole pattern is formed on a semiconductor substrate by using a layout including the pattern320corresponding to the first hole pattern.

First, when the hole pattern is formed by using the layout shown inFIG. 20A, the pattern310forms the second hole pattern according to the semiconductor substrate. Subsequently, when the hole pattern is formed by using the layout shown inFIG. 20B, the pattern320forms the first hole pattern according to the semiconductor substrate.

Here, patterns corresponding to the hole patterns that are spaced apart from each other in each layout are spaced apart from each other by 2F, but the hole patterns formed on the semiconductor substrate are spaced apart from each other by 1F, and thus, a process margin is improved.

However, since the pattern320ofFIG. 20Bneeds to be accurately placed on a certain part indicated by x on the layout ofFIG. 20A, an accurate alignment is required, which may be difficult to obtain.

Consequently, referring toFIGS. 19,20A, and20B, a more stable and improved process margin may be obtained when a plurality of hole patterns are formed by using a layout including a line pattern and a space pattern, for example, according to the above-described exemplary embodiment, compared to when a plurality of hole patterns are formed by manufacturing a photomask by using a layout including a hole pattern and performing a developing process and an etching process. Therefore, according to one embodiment, a plurality of hole patterns having a minute pitch may be formed by using a layout including line and space patterns having a relatively large pitch, without having to use a layout of hole patterns having a minute pitch.

FIG. 21is a schematic plan view of a memory module1000including a semiconductor device manufactured according to one exemplary embodiment.

The memory module1000may include a printed circuit board1100and a plurality of semiconductor packages1200.

The semiconductor packages1200may include a semiconductor device manufactured by using the method according to one of the above embodiments.

The memory module1000may be, for example, a single in-lined memory module (SIMM) on which the semiconductor packages1200are installed only on one surface of the printed circuit board1100, or a dual in-lined memory module DIMM on which the semiconductor packages1200are installed on both surfaces of the printed circuit board1100. In one embodiment, one or more chips or stacks of chips that are part of the semiconductor package1200may comprise a semiconductor device formed using the methods described herein. Alternatively, the memory module1000may be a fully buffered DIMM (FBDIMM) including an advanced memory buffer (AMB) that provides external signals respectively to the semiconductor packages1200.

FIG. 22is a schematic view of a memory card2000including a semiconductor device manufactured according to one exemplary embodiment.

The memory card2000may include a controller2100and a memory2200, which exchange electric signals. For example, when the controller2100transmits a command, the memory2200transmits data.

The memory2200may include the semiconductor device manufactured by using the method according to one of the above embodiments.

The memory card2000may be one of various memory cards, such as a memory stick card, a smart media (SM) card, a secure digital (SD) card, a mini SD card, and a multimedia card (MMC).

FIG. 23is a schematic view of a system3000including a semiconductor device manufactured according to one exemplary embodiment.

In the system3000, a processor3100, a memory3200, and an input/output device3300may transmit and receive data via a bus3400.

The memory3200of the system3000may include a random access memory (RAM) or a read only memory (ROM). Also, the system3000may include a peripheral device3500, such as a floppy disk drive and a compact disk (CD) ROM drive.

The memory3200may include the semiconductor device manufactured by using the method of any one of the above embodiments.

The memory3200may store codes and data for operating the processor3100.

The system3000may be used for a mobile phone, an MP3 player, a navigation device, a portable multimedia player (PMP), a solid state disk (SSD), or household appliances.