Oscillator method and apparatus for a test chip

A method and apparatus for modifying a frequency of an oscillating signal comprises generating an oscillating signal of a predetermined frequency on a semiconductor device used as an evaluation test chip by connecting a predetermine number of circuit elements in a ring oscillator configuration. A delay element operably coupled into the ring oscillator configuration modifies the predetermined frequency of the ring oscillator configuration. The operable coupling may occur on a semiconductor package containing the semiconductor device or a circuit board containing the semiconductor device. A ring oscillator is also described.

BACKGROUND

Oscillators are well known in the art and important in providing clock signals in digital logic circuits. Clock generation for semiconductor devices can take many forms including ring oscillators, crystal controlled oscillators, external clock devices, Phase Locked Loops (PLL) on a semiconductor device, Delay Locked Loops (DLL) on a semiconductor device, and various combinations of the above. Crystal controlled oscillators are generally useful for precisely creating a desired frequency, but cannot directly produce the very high frequencies required in a test chip designed to evaluate high performance circuitry. Similarly, external clock generators vary greatly in precision and frequency, but they are generally designed to maintain a precise fixed frequency and create global clocks for distribution within a system. As a result, external clock generators tend to be expensive.

Generally high frequency clocks on a system board are generated by expensive clock generators and maintaining a clean clock signal at high frequencies is problematic. To overcome this problem, many semiconductor devices use PLL's, which create internal clocks at higher frequencies, generally multiples of a lower frequency external reference clock. To be accurate, yet flexible enough to generate a large variety of frequencies, PLL's can be difficult to design. PLL's generally require analog circuit design techniques, and may still not provide the flexibility required for a test chip where varying the frequency of the clock is valuable in analyzing various performance parameters of a test chip.

DLL's may also be used to create clock multiples for an internal clock signal from a lower frequency clock reference. Some DLL's do not require analog circuitry but generally have the same problems of design complexity and lack of flexibility as a PLL solution when used for a test chip. However, DLLs are also often used to create phase shifts in an internal clock on a semiconductor device relative to a reference clock. When used as a phase-shifting device, DLL's may be quite useful in a test chip.

For a test chip, there is a need for a low cost high frequency oscillator solution that is flexible both in creating a desired frequency and in the ability to easily modify the created frequency.

SUMMARY

One embodiment of the present invention for generating a signal with a ring oscillator may comprise a semiconductor device used as an evaluation test chip physically attached to a semiconductor device package. The semiconductor device comprises at least an input pad circuit, a buffering circuit, and an output pad circuit. These elements on the semiconductor device form a serial chain by connecting an output signal of the input pad to an input signal of the buffering circuit and connecting an output signal of the buffering circuit to an input signal of the output pad. A delay circuit completes the ring oscillator by connecting an output terminal on the output pad to an input terminal on the delay element and connecting an output pad of the delay circuit to an input signal on the input pad. The frequency of the ring oscillator is modified due to the delay circuit altering the signal arrival time at the input signal of the input pad. To ensure oscillation, the completed ring comprises an odd number of logic inversions.

Another embodiment may comprise a semiconductor device used as an evaluation test chip physically attached to a semiconductor device package and the semiconductor package is physically attached to a circuit board. Once again, the semiconductor device comprises at least an input pad circuit, a buffering circuit, and an output pad circuit. These elements on the semiconductor device form a serial chain by connecting an output signal of the input pad to an input signal of the buffering circuit and connecting an output signal of the buffering circuit to an input signal of the output pad. A delay circuit completes the ring oscillator by connecting an output terminal on the output pad to an input terminal on the delay element and connecting an output pad of the delay circuit to an input signal on the input pad. The frequency of the ring oscillator is modified due to the delay circuit altering the signal arrival time at the input signal of the input pad. To ensure oscillation, the completed ring comprises an odd number of logic inversions.

In another embodiment, a method for modifying a frequency of an oscillating signal may comprise generating an oscillating signal of a predetermined frequency on a semiconductor device used as an evaluation test chip by connecting a predetermine number of circuit elements in a ring oscillator configuration. A delay element operably coupled into the ring oscillator configuration modifies the predetermined frequency of the ring oscillator. The operable coupling, in this embodiment, occurs on a semiconductor device package containing the semiconductor device.

In yet another embodiment, a method for modifying a frequency of an oscillating signal may comprise generating an oscillating signal of a predetermined frequency on a semiconductor device used as an evaluation test chip by connecting a predetermine number of circuit elements in a ring oscillator configuration. A delay clement operably coupled into the ring oscillator configuration modifies the predetermined frequency of the ring oscillator configuration. In this embodiment, the operable coupling occurs on a circuit board containing the semiconductor device.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1is a diagram illustrating an evaluation test chip, also referred to as a semiconductor device100. The semiconductor device100is physically mounted on a semiconductor device package150. An input pad102connects to a buffer108, which in turn drives a clock tree or other circuitry (not shown) within the semiconductor device100. The input pad102also drives an inverting circuit104, which in turn drives a typical output pad106. The circuitry configuration of input pad102, inverting circuit104, and output pad106comprise portions of a ring oscillator circuit112implemented on the semiconductor device100. While shown as a logical inverter, the inverting circuit104may be comprised of other logic gates, such as, for example, NAND gates and NOR gates (not shown). These types of gates are typically used to enable and disable a ring oscillator circuit. Even more complex logic implementations are possible in which, as in this implementation, a final ring implementation results in an odd number of logic inversions in a chain of inversions when the chain is in an oscillating mode.

A number of different optional configurations are also contemplated as within the scope of the present invention to close the ring configuration creating ring oscillator circuit112.FIG. 1illustrates an embodiment of the present invention. In this embodiment, input pad102and output pad104connect to a substrate of the semiconductor device package150using any bonding technology known by those of ordinary skill in the art, such as, for example; wire bonding, solder balls, and tape automated bonding. An input connection point110connects to input pad102and an output connection point120connects to the output pad106. To close ring oscillator circuit112, input connection point110connects to output connection point120by circuit trace130on the semiconductor device package150. The frequency at which the ring oscillator circuit112oscillates may be tuned within a certain range by varying the length and width of the circuit trace130, thereby varying the characteristic impedance driven by the output pad106. A larger characteristic impedance causes a signal on the output pad106to transition more slowly thereby reducing the frequency of the ring oscillator circuit112. A combination of minimal resistance and minimal capacitance for the circuit trace130between the output connection point120and the input connection point110represents the highest oscillating frequency of the ring oscillator circuit112.

Another exemplary embodiment of the present invention, shown inFIG. 2, includes a ring oscillator circuit114which includes similar circuitry on the semiconductor device100, with an additional delay element300physically attached to a semiconductor device package152. An input terminal302of the delay element300connects to an output connection point122of the semiconductor device100. The output terminal304of the delay element300connects to an input connection point116of the semiconductor device100. The delay element is more fully described below.

FIG. 3illustrates a circuit board implementation, in accordance with another embodiment of the present invention. A circuit board200includes a semiconductor device package154, further including semiconductor device100. In this embodiment, the output pad106connects to an output connection point124on the semiconductor device package154, which connects to an output connection trace220on the circuit board200. Similarly, the input pad102connects to an input connection point118on the semiconductor device package154, which connects to an input connection trace210on the circuit board200. To close ring oscillator circuit126, the input connection trace210connects with output connection trace220via a circuit trace230. Coupling input connection trace210with output connection trace220creates a high operating frequency for the ring oscillator circuit126when closed on the circuit board200. Due to the increased characteristic impedance of circuit board traces, this frequency typically will be slightly lower than the frequency possible with a connection on the semiconductor device package150as shown in FIG.1. In addition, the frequency at which ring oscillator circuits may be tuned varies according to the length and width of the circuit trace230, which causes the characteristic impedance driven by the output pad106to vary.

FIG. 4illustrates a circuit board implementation of a ring oscillator circuit128, in accordance with yet another embodiment of the present invention. InFIG. 4, a delay element300is connected on a circuit board202by an input terminal312of the delay element300connecting to an output connection trace222on the circuit board202. An output terminal314of the delay element300connects to an input connection trace212on the circuit board202.

The delay element may be configured in many optional ways, and implemented in many physical locations, creating a predetermined time delay between the input terminal312and the output terminal314. Some exemplary delay elements300are shown inFIG. 5,FIG. 6, and FIG.7.

FIG. 5illustrates a delay element300using passive electrical elements, in accordance with an embodiment of the present invention. In the present embodiment, a resistor310connects in series between an input terminal302,312and an output terminal304,314. In addition, a capacitor306connects between ground and the output terminal304,314. This configuration is an example of many possible configurations of passive elements connected in a manner that will cause the output terminal to transition at a slower rate or delayed in time relative to the input terminal. Different amounts of delay, resulting in different oscillating frequencies, are possible and within the scope of the present invention, using the series resistor310, the parallel capacitor306, or additional passive elements (not shown).

FIG. 6illustrates an embodiment of the delay element300′ using active electrical elements. In this exemplary embodiment, a non-inverting buffer320, an additional non-inverting buffer322, and an AND gate324connect in series between the input terminal302′,312′ and the output terminal304′,314′. An additional enabling signal326connects to the second input terminal of the AND gate324. The enabling signal326allows the ring oscillator circuit to oscillate when the enabling signal326is high, and prevents the ring oscillator circuit from oscillating when the enabling signal326is low.

The depicted configuration is one example, and many possible configurations of active elements connected in a manner that cause the output terminal to be delayed in time relative to the input terminal are possible. A different amount of delay, and as a result a different oscillating frequency, is possible by using a single non-inverting buffer320, using the AND gate324, or using a larger number of logic gates in the chain which are considered within the scope of the present invention. Many different logic gates may be used to create a long delay chain, including the input pad102, the output pad104, and the inverting circuit104on the semiconductor device100, as long as the sum of elements contains an odd number of logic inversions. Additionally, delay lines are available that create fixed delays between the input and multiple delay taps on the output. Connecting a delay line (not shown) with a multiplexer (not shown) connected to the multiple delay taps, results in a method for creating precise delays, and a resulting precise frequency.

FIG. 7illustrates an embodiment of the delay element300″ using a combination of active electrical elements and passive electrical elements. In this exemplary embodiment, a non-inverting buffer330connects to the input terminal302″,312″. To create a delay on the intermediate node340, a series resistor332followed by a parallel capacitor334connects to the output terminal of the non-inverting buffer330. In addition, an AND gate336connects between the intermediate node340and the output terminal304″,314″. An additional enabling signal338connects to the second input terminal of the AND gate336. The enabling signal338allows the ring oscillator circuit to oscillate when the enabling signal338is high, and prevents the ring oscillator circuit from oscillating when the enabling signal338is low. The output of the AND gate connects to the output terminal304″,314″ of the delay element300″. As with the embodiment inFIG. 6, the integration of many combinations of passive devices, active devices, complex logic gates, and delay lines is also contemplated.

Additionally, the delay element300, or various pieces of the delay element300, may actually be configured in many physical locations. Portions of the delay element300may be on the semiconductor device package150-154and wired together by circuit traces on the semiconductor device package150-154as shown inFIGS. 2-4. Portions of the delay element300may be on the circuit board202and wired together by circuit traces on the circuit board as shown in FIG.4. In addition, portions of the delay element may be on the semiconductor device and wired together through input/output (IO) pads and bonding elements connecting the IO pads to the semiconductor device package150-154, and the circuit board200-202.

Additionally, the portion of the ring oscillator circuit located on the semiconductor device100may contain the odd number of logic inversions, which enables the ring oscillator circuit to operate. Such an approach results in a very high oscillation frequency by connecting the output pad106to the input pad102on the semiconductor device package150-154. However, it is also contemplated within the scope of the present invention that an odd number of logic inversions may be implemented in the delay element300, rather the semiconductor device100.

Specific embodiments have been shown by way of example in the drawings and have been described in detail herein, however the invention may be susceptible to additional various modifications and alternative forms. It should be understood that the invention is not intended to be limited to the particular forms disclosed. Rather, the invention includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the following appended claims.