CONTROL DEVICE AND OPERATION METHOD THEREOF

A control device includes a first area, a second area and a third area. The first area includes a peripheral unit, a storage unit and a control unit. The second area includes a peripheral unit, an access unit, a storage unit and a control unit. The third area includes an operating unit, a peripheral unit, an access unit, a storage unit and a control unit. In an ultra-low-power mode, a low-power mode and a high-speed mode, a first working voltage and a first clock signal are provided to the first area. In the low-power mode or the high-speed mode, the first working voltage and a second clock signal are provided to the second area. In the high-speed mode, the first working voltage and a third clock signal are provided to the third area.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority of Taiwan Patent Application No. 111126509, filed on Jul. 14, 2022, the entirety of which is incorporated by reference herein.

TECHNICAL FIELD

The present invention relates to a control device, and in particular it relates to a control device with high speed and low power consumption and an operation method thereof.

BACKGROUND

In general, control devices (such as micro controllers) are designed to have several internal elements. They provide the working voltages required by these internal elements, so that the control device operates at high speed. However, since control devices are not always operating in a high-speed state, and the control device still provides the working voltages required by the internal elements in the high-speed state, the power consumption of the control device may be increased.

Therefore, how to effectively design a control device with high speed and low power consumption has become a focus of technical improvements.

SUMMARY

An embodiment of the present invention provides a control device and an operation method thereof, thereby achieving high speed and low power consumption.

An embodiment of the present invention provides a control device, which includes a first area, a second area and a third area. The first area includes a first peripheral unit, a first storage unit and a first control unit. The second area includes a second peripheral unit, a first access unit, a second storage unit and a second control unit. The third area includes an operating unit, a third peripheral unit, a second access unit, a third storage unit and a third control unit. In an ultra-low-power mode, a first working voltage and a first clock signal are provided to the first area. In a low-power mode, the first working voltage and the first clock signal are provided to the first area, and the first working voltage and a second clock signal are provided to the second area. In a high-speed mode, the first working voltage and the first clock signal are provided to the first area, and the first working voltage and a third clock signal are provided to the third area, or the first working voltage and the first clock signal are provided to the first area, the first working voltage and the second clock signal are provided to the second area, and the first working voltage and the third clock signal are provided to the third area.

An embodiment of the present invention provides an operation method of a control device, which includes the following steps. A first area including a first peripheral unit, a first storage unit and a first control unit is provided. A second area including a second peripheral unit, a first access unit, a second storage unit and a second control unit is provided. A third area including an operating unit, a third peripheral unit, a second access unit, a third storage unit and a third control unit is provided. In an ultra-low-power mode, a first working voltage and a first clock signal are provided to the first area. In a low-power mode, the first working voltage and the first clock signal are provided to the first area, and the first working voltage and a second clock signal are provided to the second area. In a high-speed mode, the first working voltage and the first clock signal are provided to the first area, and the first working voltage and a third clock signal are provided to the third area, or the first working voltage and the first clock signal are provided to the first area, the first working voltage and the second clock signal are provided to the second area, and the first working voltage and the third clock signal are provided to the third area.

According to the control device and the operation method thereof disclosed by the present invention, the first area, the second area and the third area are configured. The number of elements of the first area is less than the number of elements of the second area. The number of elements of the second area is less than the number of elements of the third area. The corresponding working voltages and clock signals are provided to the first area, the second area and/or the third area according to the different modes (i.e., the ultra-low-power mode, the low-power mode and the high-speed mode). Therefore, high speed and low power consumption may be achieved.

DETAILED DESCRIPTION OF DISCLOSED EMBODIMENTS

It should be acknowledged that although the terms “first”, “second”, “third”, and so on, may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only for the purpose of distinguishing one component from another component. Thus, a first element discussed herein could be termed a second element without altering the description of the present disclosure. As used herein, the term “or” includes any and all combinations of one or more of the associated listed items.

In addition, unless explicitly described to the contrary, the word “comprise” and variations such as “comprises” or “comprising”, will be acknowledged to imply the inclusion of stated elements but not the exclusion of any other elements.

In each of the following embodiments, the same reference number represents an element or component that is the same or similar.

FIG.1is a schematic view of a control device according an embodiment of the present invention. In the embodiment, the control device100may be a micro controller unit (MCU), a microprocessor or another suitable controller, but the embodiment of the present invention is not limited thereto. Please refer toFIG.1. The control device100may include a first area110, a second area120and a third area130.

The first area110may include a first peripheral unit111, a first storage unit112and a first control unit113. The second area120may include a second peripheral unit121, a first access unit122, a second storage unit123and a second control unit124. The third area130may include an operating unit131, a third peripheral unit132, a second access unit133, a third storage unit134and a third control unit135.

In the embodiment, a number of elements of the first peripheral unit111is, for example, is less than a number of elements of the second peripheral unit121, and the number of elements of the second peripheral unit121is, for example, less than a number of elements of the third peripheral unit132.

As shown inFIG.2, in some embodiments, the first peripheral unit111may include a low power analog-to-digital converter (LPADC)202, a pulse width modulator (PWM)204and a low-power timer (LPTimer)206. As shown inFIG.2, in some embodiments, the second peripheral unit121may include a digital-to-analog converter (DAC)208, an operation amplifier (OPA)210, a timer212, an inter-integrated circuit (I2C)214, a universal asynchronous receiver/transmitter (UART)216and a serial peripheral interface (SPI)218.

As shown inFIG.2, in some embodiments, the third peripheral unit132may include a digital-to-analog converter (DAC)220, an analog-to-digital converter (ADC)222, a timer224, an inter-integrated circuit (I2C)226, a universal series bus (USB)228, a universal asynchronous receiver/transmitter (UART)230, an analog comparator (ACMP)232, a serial peripheral interface (SPI)234, a pulse width modulator (PWM)236, a quadrature encoder interface (QEI)238, a watch dog timer (WDT)240, a USB Type-C connector system software interface (UCSI)242, a real time clock (RTC)244, a high speed internal RC oscillator (HIRC)246, a medium speed internal RC oscillator (MIRC)248, a general-purpose input/output (GPIO) port250and a global miscellaneous control register (GMISC)252.

In addition, a size of the first storage unit112is, for example, smaller than a size of the second storage unit123, and the size of the second storage unit122is, for example, smaller than a size of the third storage unit134. As shown inFIG.2, in some embodiments, the first storage unit112may include a register254. As shown inFIG.2, in some embodiments, the second storage unit123may include a low-power memory256, such as a low power static random access memory (LPSRAM). As shown inFIG.2, in some embodiments, the third storage unit134may include a first memory258, a second memory260, a cache memory262and a flash memory264. In the embodiment, each of the first memory258and the second memory260is, for example, a static random access memory (SRAM).

As shown inFIG.2, in some embodiments, the first control unit113may include a power and clock management controller (PCMC)266and a wake-up and interrupt controller (WIC)268. As shown inFIG.2, in some embodiments, the first access unit122may include a low power direct memory access (LPDMA) controller270. As shown inFIG.2, in some embodiments, the second control unit124may include a power and clock management controller272and a wake-up and interrupt controller274.

As shown inFIG.2, in some embodiments, the operation unit131may include a central processing unit (CPU)276. As shown inFIG.2, in some embodiments, the second access unit133may include a first memory controller278, a second memory controller280, a peripheral direct memory access (PDMA) controller282, a cache controller284and a flash memory controller (FMC)286. In the embodiment, each of the first memory controller278and the second memory controller280is, for example, a SRAM controller. In addition, the first memory controller278is electrically connected to the first memory258. The second memory controller280is electrically connected to the second memory260. The cache controller284is electrically connected to the cache memory262and the central processing unit276. The flash memory controller286is electrically connected to the flash memory264.

As shown inFIG.2, in some embodiments, the third control unit135may include a power and clock management controller288and a wake-up and interrupt controller290.

In the embodiment, the low power analog-to-digital converter202, the pulse width modulator204, the low-power timer206, the digital-to-analog converter208, the operation amplifier210, the timer212, the inter-integrated circuit214, the universal asynchronous receiver/transmitter216, the serial peripheral interface218, the digital-to-analog converter220, the analog-to-digital converter222, the timer224, the inter-integrated circuit226, the universal series bus228, the universal asynchronous receiver/transmitter230, the analog comparator232, the serial peripheral interface234, the pulse width modulator236, the quadrature encoder interface238, the watch dog timer240, the USB Type-C connector system software interface242, the real time clock244, the general-purpose input/output port250, the global miscellaneous control register252, the low power direct memory access controller270, the central processing unit276, the first memory controller278, the second memory controller280, the peripheral direct memory access controller282, the cache controller284and the flash memory controller286are electrically connected to a bus292for communication through the bus292. In the embodiment, the bus292may include an advanced peripheral bus (APB) and an advanced high-performance bus (AHB), but the embodiment of the present invention is not limited thereto.

In the embodiment, the control device100further includes a power management controller140, a first voltage converter150, a first switch unit SW1, a second switch unit SW2and a third switch unit SW3.

The power management controller140is configured to receive a power voltage VIN, generate a first control signal, and generate a second control signal to the first control unit113. The first voltage converter150is configured to receive the power voltage VIN to generate the first working voltage V1.

The first switch unit SW1is electrically connected to the first voltage converter150, the power management controller140and the first area110(i.e., the first peripheral unit111, the first storage unit112and the first control unit113). The first switch unit SW1may be configured to determine whether to provide the first working voltage V1to the first area110according to the first control signal. For example, when the first switch unit SW1receives the first control signal having, for example, a high logic level, the first switch unit SW1may be turned on to provide the first working voltage V1to the first area110. Furthermore, the first working voltage V1may be provided to the first peripheral unit111, the first storage unit112and the first control unit113of the first area110, so that the first peripheral unit111, the first storage unit112and the first control unit113operate normally. When the first switch unit SW1receives the first control signal having, for example, a low logic level, the first switch unit SW1may not be turned on, and may not provide the first working voltage V1to the first area110.

The second switch unit SW2is electrically connected to the first voltage converter150, the first control unit113and the second control unit124. In addition, the second switch unit120is further electrically connected to the second peripheral unit121, the first access unit122and the second storage unit123. The second switch unit SW2may be configured to determine whether to provide the first working voltage V1to the second area120according to a control of the first control unit113and/or the second control unit124. For example, when the second switch unit SW2receives the control signal having, for example, a high logic level provided by the first control unit113and/or the second control unit124, the second switch unit SW2may be turned on to provide the first working voltage V1to the second area120. Furthermore, the first working voltage V1may be provided to the second peripheral unit121, the first access unit122, the second storage unit123and the second control unit124of the second area120, so that the second peripheral unit121, the first access unit122, the second storage unit123and the second control unit124operate normally. When the second switch unit SW2receives the control signal having, for example, a low logic level provided by the first control unit113and/or the second control unit124, the second switch unit SW2may not be turned on, and may not provide the first working voltage V1to the second area120.

The third switch unit SW3is electrically connected to the first voltage converter150, the second control unit124and the third control unit135. In addition, the third switch unit SW3is further electrically connected to the operation unit131, the third peripheral unit132, the second access unit133and the third storage unit134. The third switch unit SW3may be configured to determine whether to provide the first working voltage V1to the third area130according to a control of the second control unit124and/or the third control unit135. For example, when the third switch unit SW3receives the control signal having, for example, a high logic level provided by the second control unit124and/or the third control unit135, the third switch unit SW3may be turned on to provide the first working voltage V1to the third area130.

Furthermore, the first working voltage V1may be provided to the operation unit131, the third peripheral unit132, the second access unit133, the third storage unit134and the third control unit135of the third area130, so that the operation unit131, the third peripheral unit132, the second access unit133, the third storage unit134and the third control unit135operate normally. When the third switch unit SW3receives the control signal having, for example, a low logic level provided by the second control unit124and/or the third control unit135, the third switch unit SW3may not be turned on, and may not provide the first working voltage V1to the third area130.

In the operation of the control device100, in an ultra-low-power mode, the power management controller140generates a first control signal having a high logic level to the first switch unit SW1, so that the first switch unit SW1is turned on to provide the first working voltage V1to the first area110. In addition, the power management controller140provides a second control signal with the high logic level to the first control unit113of the first area110, so that the power and clock management controller266of the first control unit113may provide the first clock signal to the first area110to provide the working clock required by the first peripheral unit111.

In a low-power mode, the first control unit113(such as the power and clock management controller266) may generate the control signal having, for example, the high logic level to the second switch unit SW2, so that the second switch unit SW2is turned on to provide the first working voltage V1to the second area120. In addition, the first control unit113(such as the wake-up and interrupt controller268) may provide a wake-up signal to the second control unit124(such as the power and clock management controller272), so as to wake up the second area120. Then, the second control unit124(such as the power and clock management controller272) may generate the second clock signal to the second area120according to the wake-up signal, so as to provide the working clock required by the second peripheral unit121and the first access unit122, so that the second area120may complete the required task. For example, the first access unit122(i.e., the low power direct memory access controller270) assists in moving the data to the second storage unit123(i.e., the low-power memory256).

Then, after the second area120completes the required task, the first control unit113and/or the second control unit124may generate the control signal having, for example, the low logic level to the second switch unit SW2, so that the second switch unit SW2is not turned on, so as to turn off the operation of the second area120. Therefore, the power consumption of the control device100may be effectively saved.

In a high-speed mode, the second control unit124(such as the power and clock management controller272) may generate the control signal having, for example, the high logic level to the third switch unit SW3, so that the third switch unit SW3is turned on to provide the first working voltage V1to the third area130. In addition, the second control unit124(such as the wake-up and interrupt controller274) may provide a wake-up signal to the third control unit135, so as to wake up the third area130. Then, the third control unit135may generate the third clock signal to the third area130according to the wake-up signal, so as to provide the working clock required by the operation unit131, the third second peripheral unit132and the second access unit133, so that the third area130may complete the required task. For example, the computing operation is performed using the operation unit131(i.e., the central processing unit276).

Then, after the third area130completes the required task, the second control unit124and/or the third control unit135may generate the control signal having, for example, the low logic level to the third switch unit SW3, so that the third switch unit SW3is not turned on, so as to turn off the operation of the third area130. Therefore, the power consumption of the control device100may be effectively saved.

In addition, in some embodiments the control device100further includes a second voltage converter160, a fourth switch unit SW4, a third voltage converter170and a fifth switch unit SW5.

The second voltage converter160is electrically connected to the first voltage converter150. The second voltage converter160may receive be configured to receive the first working voltage V1to generate a second working voltage V2. The fourth switch unit SW4is electrically connected to the second voltage converter160, the first control unit113and the second control unit124. In addition, the fourth switch unit SW4is further electrically connected to the second storage unit123. The fourth switch unit SW4may be configured to determine whether to provide the second working voltage V2to the second storage unit123and the second control unit124of the second120according to the control of the first control unit113and/or the second control unit124.

For example, when the fourth switch unit SW4receives the control signal having, for example, a high logic level provided by the first control unit113and/or the second control unit124, the fourth switch unit SW4may be turned on to provide the second working voltage V2to the second storage unit123and the second control unit124of the second area120, so that the second storage unit123and the second control unit124operate normally. When the fourth switch unit SW4receives the control signal having, for example, a low logic level provided by the first control unit113and/or the second control unit124, the fourth switch unit SW4may not be turned on, and may not provide the second working voltage V2to the second storage unit123and the second control unit124of the second area120.

The third voltage converter170is electrically connected to the first voltage converter150. The third voltage converter170may be configured to receive the first working voltage V1to generate a third working voltage V3. The fifth switch unit SW5is electrically connected to the third voltage converter170, the second control unit124and the third control unit135. In addition, the fifth switch unit SW5is further electrically connected to the third storage unit134. The fifth switch unit SW5may be configured to determine whether to provide the third working voltage V3to the third storage unit134and the third control unit135of the third area130according to the control of the second control unit124and/or the third control unit135.

For example, when the fifth switch unit SW5receives the control signal having, for example, a high logic level provided by the second control unit124and/or the third control unit135, the fifth switch unit SW5may be turned on to provide the third working voltage V3to the third storage unit134and the third control unit135of the third area130, so that the third storage unit134and the third control unit135operate normally. When the fifth switch unit SW5receives the control signal having, for example, a low logic level provided by the second control unit124and/or the third control unit135, the fifth switch unit SW5may not be turned on, and may not provide the third working voltage V3to the third storage unit134and the third control unit135of the third area130.

In the embodiment, the second working voltage V2and the third working voltage V3are, for example, smaller than the first working voltage V1. In addition, the second working voltage V2and the third working voltage V3may be the same or different. Furthermore, each of the second voltage converter160and the third voltage converter170is, for example, a low dropout regulator (LDO).

In the operation of the control device100, in the ultra-low-power mode, the power management controller140generates the first control signal having the high logic level to the first switch unit SW1, so that the first switch unit SW1is turned on to provide the first working voltage V1to the first area. In addition, the power management controller140provides the second control signal with the high logic level to the first control unit113of the first area110, so that the power and clock management controller266of the first control unit113may provide the first clock signal to the first area110to provide the working clock required by the first peripheral unit111.

Then, the first control unit113(such as the power and clock management controller266) may provide the control signal to the fourth switch unit SW4, so that the fourth switch unit SW2is turned on to provide the second working voltage V2to the second storage unit123and the second control unit124of the second area120. In addition, the first control unit113(such as the wake-up and interrupt controller268) may provide the wake-up signal to the second control unit124, so as to wake up the second control unit124, so that the second area120is in a standby state.

Afterward, the second control unit124(such as the power and clock management controller272) may provide the control single to the fifth switch unit SW5, so that the fifth switch unit SW5is turned on to provide the third working voltage V3to the third storage unit134and the third control unit135of the third area130. In addition, the second control unit124(such as the wake-up and interrupt controller274) may provide the wake-up signal to the third control unit135, so as to wake up the third control unit135, so that the third area130is in the standby state. Therefore, the wakeup time of the second area120and/or the third area130may be effectively saved, and the power consumption of the control device100may be saved.

In the low-power mode, the first control unit113(such as the power and clock management controller266) and/or the second control unit124(such as the power and clock management controller272) may generate the control signal having, for example, the high logic level to the second switch unit SW2and generate the control signal having, for example, the low logic level to the fourth switch unit SW4, so that the second switch unit SW2is turned on and the fourth switch unit SW4is not turned on, so as to provide the first working voltage V1to the second area120. In addition, the first control unit113(such as the wake-up and interrupt controller268) and/or the second control unit124(such as the wake-up and interrupt controller274) may provide the wake-up signal to the second control unit124(such as the power and clock management controller272) Then, the second control unit124(such as the power and clock management controller272) may generate the second clock signal to the second area120according to the wake-up signal, so as to provide the working clock required by the second peripheral unit121and the first access unit122, so that the second area120may complete the required task.

Then, after the second area120completes the required task, the first control unit113and/or the second control unit124may generate the control signal having, for example, the low logic level to the second switch unit SW2and generate the control signal having, for example, the high logic level to the fourth switch unit SW4, so that the second switch unit SW2is not turned on and the fourth switch unit SW4is turned on, so as to provide the second working voltage V2to the second storage unit123and the second control unit124of the second area120, thereby maintaining the operations of the second storage unit123and the second control unit124. Therefore, the power consumption of the control device100may be effectively saved.

In the high-speed mode, the second control unit124(such as the power and clock management controller272) and/or the third control unit135(such as the power and clock management controller288) may generate the control signal having, for example, the high logic level to the third switch unit SW3and generate the control signal having, for example, the low logic level to the fifth switch unit SW5, so that the third switch unit SW3is turned on and the fifth switch unit SW5is not turned on, so as to provide the first working voltage V1to the third area130. In addition, the second control unit124(such as the wake-up and interrupt controller274) and/or the third control unit135(such as the wake-up and interrupt controller290) may provide the wake-up signal to the third control unit135(such as the power and clock management controller290). Then, the third control unit135(such as the power and clock management controller290) may generate the third clock signal to the third area130according to the wake-up signal, so as to provide the working clock required by the operation unit131, the third second peripheral unit132and the second access unit133, so that the third area130may complete the required task. At this time, the first area110, the second area120and the third area130are all in operation.

Then, after the third area130completes the required task, the second control unit124and/or the third control unit135may generate the control signal having, for example, the low logic level to the third switch unit SW3and generate the control signal having, for example, the high logic level to the fifth switch unit SW5, so that the third switch unit SW3is not turned on and the fifth switch unit SW5is turned on, so as to provide the third working voltage V3to the third storage unit134and the third control unit135of the third area130, thereby maintaining the operations of the third storage unit134and the third control unit135. At this time, the first area110and the second area120still operate. Therefore, the power consumption of the control device100may be effectively saved.

In the high-speed mode, in an embodiment, the first control unit113may communicate with the second control unit124, or the first control unit113may communicate with the third control unit135through the second control unit124, so that the second control unit124(such as the power and clock management controller272) and/or the third control unit135(such as the power and clock management controller288) may generate the control signal having, for example, the high logic level to the third switch unit SW3and generate the control signal having, for example, the low logic level to the fifth switch unit SW5, then the third switch unit SW3is turned on and the fifth switch unit SW5is not turned on, so as to provide the first working voltage V1to the third area130. In addition, the second control unit124(such as the wake-up and interrupt controller274) and/or the third control unit135(such as the wake-up and interrupt controller290) may provide the wake-up signal to the third control unit135(such as the power and clock management controller290). Then, the third control unit135(such as the power and clock management controller290) may generate the third clock signal to the third area130according to the wake-up signal, so as to provide the working clock required by the operation unit131, the third second peripheral unit132and the second access unit133, so that the third area130may complete the required task. At this time, the first area110and the third area130operate, but the second area120does not operate.

Then, after the third area130completes the required task, the second control unit124and/or the third control unit135may generate the control signal having, for example, the low logic level to the third switch unit SW3and generate the control signal having, for example, the high logic level to the fifth switch unit SW5, so that the third switch unit SW3is not turned on and the fifth switch unit SW5is turned on, so as to provide the third working voltage V3to the third storage unit134and the third control unit135of the third area130, thereby maintaining the operation of the third storage unit134and the third control unit135. At this time, the first area110still continues to operate. Therefore, the power consumption of the control device100may be effectively saved.

In some embodiments, the logic in the third area130may use a multiple threshold voltage (multi-vth) design technique, and the operation voltage thereof is between the overdrive voltage and the normal voltage. The logic in the second area120may use a high threshold voltage (high-vth) design technique, and the operation voltage thereof is between the normal voltage and the low voltage. The logic in the first area110may use an extreme high threshold voltage (extreme high-vth) design technique, and the operation voltage thereof is between the low voltage and the extreme low voltage.

In addition, in the embodiment, the elements in the first area110(i.e., the first peripheral unit,111, the first storage unit112and the first control unit113), the elements in the area120(i.e., the second peripheral unit121, the first access unit122, the second storage unit123and the second control unit124) and the elements in the third area130(i.e., the operation unit131, the third peripheral unit132, the second access unit133, the third storage unit134and the third control unit135) use the same voltage (i.e., the first working voltage V1), so as avoid the need for installing the voltage lever converter, thereby saving the increase of the operation time caused by the voltage lever converter.

FIG.3is a flowchart of an operation method of a control electronic device according an embodiment of the present invention. In step S302, the method involves providing a first area including a first peripheral unit, a first storage unit and a first control unit. In step S304, the method involves providing a second area including a second peripheral unit, a first access unit, a second storage unit and a second control unit. In step S306, the method involves providing a third area including an operating unit, a third peripheral unit, a second access unit, a third storage unit and a third control unit. In step S308, the method involves in an ultra-low-power mode, providing a first working voltage and a first clock signal to the first area.

In step S310, the method involves in a low-power mode, providing the first working voltage and the first clock signal to the first area, and providing the first working voltage and a second clock signal to the second area. In step S312, the method involves in a high-speed mode, providing the first working voltage and the first clock signal to the first area, and providing the first working voltage and a third clock signal to the third area, or providing the first working voltage and the first clock signal to the first area, providing the first working voltage and the second clock signal to the second area, and providing the first working voltage and the third clock signal to the third area. In the embodiment, a number of elements of the first peripheral unit is, for example, less than a number of elements of the second peripheral unit, and the number of elements of the second peripheral unit is, for example, less than a number of elements of the third peripheral unit. In addition, a size of the first storage unit is, for example, smaller than a size of the second storage unit, and the size of the second storage unit is, for example, smaller than a size of the third storage unit.

FIG.4is a flowchart of an operation method of a control device according another embodiment of the present invention. In the embodiment, steps S302-S312inFIG.4are the same as or similar to steps S302-S312inFIG.3. Accordingly, steps S302-S312inFIG.4may refer to the description of the embodiment inFIG.3, and the description thereof is not repeated herein. In step S402, the method involves using a power management controller to receive a power voltage, generate a first control signal, and generate a second control signal to the first control unit. In step S404, the method involves using a first voltage converter to receive the power voltage to generate the first working voltage.

In the embodiment, step S308further includes in the ultra-low-power mode, using a first switch unit to provide the first working voltage to the first area and using the first control unit to provide the first clock signal to the first area according to the first control signal and the second control signal. Step S310further includes in the low-power mode, using the first switch unit to provide the first working voltage to the first area and using the first control unit to provide the first clock signal to the first area according to the first control signal and the second control signal, and using a second switch to provide the first working voltage to the second area and using the second control unit to provide the second clock signal to the second area according to a control of the first control unit and/or the second control unit.

Step S312further includes in the high-speed mode, using the first switch unit to provide the first working voltage to the first area and using the first control unit to provide the first clock signal to the first area according to the first control signal and the second control signal, using the second switch unit to provide the first working voltage to the second area and using the second control unit to provide the second clock signal to the second area according to the control of the first control unit and/or the second control unit, and using a third switch unit to provide the first working voltage to the third area and using the third control unit to provide the third clock signal to the third area according to a control of the second control unit and/or the third control unit.

FIG.5is a flowchart of an operation method of a control device according another embodiment of the present invention. In the embodiment, steps S302-S312and S402-S404inFIG.5are the same as or similar to steps S302-S312and S402-S404inFIG.4. Accordingly, steps S302-S312and S402-S404inFIG.5may refer to the description of the embodiment inFIG.4, and the description thereof is not repeated herein. In step S502, the method involves using a second voltage converter to receive the first working voltage to generate the second working voltage. In step S504, the method involves using a third voltage converter to receive the first working voltage to generate the third working voltage. In step S506, the method involves in the ultra-low-power mode, providing a second working voltage to the second storage unit and the second control unit of the second area, and providing a third working voltage to the third storage unit and the third control unit of the third area, wherein the second working voltage and the third working voltage are lower than the first working voltage.

In addition, step S506further includes in the ultra-low-power mode, using a fourth switch unit to provide the second working voltage to the second storage unit and the second control unit of the second area according to the control of the first control unit and/or the second control unit, and using a fifth switch unit to provide the third working voltage to the third storage unit and the third control unit of the third area according to the control of the second control unit and/or the third control unit. Step S312further includes in the high-speed mode, using the first switch unit to provide the first working voltage to the first area and using the first control unit to provide the first clock signal to the first area according to the first control signal and the second control signal, and using the third switch unit to provide the first working voltage to the third area and using the third control unit to provide the third clock signal to the third area according to the control of the second control unit and/or the third control unit.

In summary, according to the control device and the operation method thereof disclosed by the embodiment of the present invention, the first area, the second area and the third area are configured. The number of elements of the first area is less than the number of elements of the second area. The number of elements of the second area is less than the number of elements of the third area. The corresponding working voltages and clock signals are provided to the first area, the second area and/or the third area according to the different modes (i.e., the ultra-low-power mode, the low-power mode and the high-speed mode). Therefore, high speed and low power consumption may be achieved.