Semiconductor device and semiconductor device measuring system

A semiconductor device includes: a well of a second conductive type formed on or above a semiconductor substrate of a first conductive type; a first diffusion layer of the second conductive type formed in a surface portion of the well; a second diffusion layer of the first conductive type formed separately from the first diffusion layer in the surface portion of the well; first to third first-layer conductive layers formed above the well; and first to third second-layer conductive layers formed above the first to third first-layer conductive layers. The first second-layer conductive layer, the first first-layer conductive layer, the first diffusion layer and the well are conductively connected as a first conductive path. The second second-layer conductive layer, the second first-layer conductive layer, and the second diffusion layer are conductively connected as a second conductive path. The third second-layer conductive layer, and the third first-layer conductive layer are conductively connected as a third conductive path.

INCORPORATION BY REFERENCE

This patent application claims a priority on convention based on Japanese Patent Application No. 2009-105588. The disclosure thereof is incorporated herein by reference.

TECHNICAL FIELD

The present invention relates to a semiconductor device and, in particular, to a semiconductor device measuring system for evaluating the semiconductor device.

BACKGROUND ART

In a process of developing and manufacturing a semiconductor device, the semiconductor device is evaluated by measuring a PN junction capacitance between a well of a first conductive type and a diffusion layer of a second conductive type in the semiconductor device. Here, a case where a conventional technique described in Japanese Patent Publication (JP-A-Heisei 9-74122: patent literature 1) is applied to measurement of a capacitance of a semiconductor device will be described. In this case, two kinds of measurement patterns of a DUT (Device Under Test) pattern semiconductor device and a calibration pattern semiconductor device are used.

FIG. 1Ashows a plan view of the DUT pattern semiconductor device, andFIG. 1Bis a diagram showing a sectional of the semiconductor device along on a line X-X′ ofFIG. 1Aand a semiconductor device measuring system applied to the DUT pattern semiconductor device.

The DUT pattern semiconductor device includes a semiconductor substrate400of a first conductive type; a well406of a second conductive type; insulating films405-1to405-3; a diffusion layer407of the first conductive type; a diffusion layer408of the second conductive type; an insulating film413; via-contacts403-1,403-2; first-layer metal wiring layers401-1and401-2; an insulating film414; via-contacts404-1and404-2; and second-layer metal wiring layers402-1and402-2. Here, the first conductive type and the second conductive type are assumed to be an N-type and a P-type, respectively.

The semiconductor substrate400of the N-type has the well406of the P-type formed on the surface portion thereof. The well406of the P-type has the insulating films405-1to405-3formed in its surface portion thereof. The diffusion layer407of the N-type is formed between the insulating film405-1and the insulating film405-2in the surface portion of the well406of the P-type. The diffusion layer408of the P-type is formed between the insulating film405-2and the insulating film405-3in the surface portion of well406of the P-type. The well406of the P-type, the insulating films405-1to405-3, the diffusion layer407of the N-type, and the diffusion layer408of the P-type are covered with the insulating film413. The via-contact403-1is formed on the diffusion layer407of the N-type to pass through the insulating film413. The via-contact403-2is formed on the diffusion layer408of the P-type to pass through the insulating film413. The first-layer metal wiring layers401-1and401-2are formed on the via-contacts403-1and403-2, respectively.

The first-layer meal wiring layers401-1and401-2are covered with the insulating film414. The via-contacts404-1are formed on the first-layer meal wiring layer401-1to pass through the insulating film414. The via-contacts404-2are formed on the first-layer meal wiring layer401-2to pass through the insulating film414. The second-layer metal wiring layers402-1and402-2are formed on the via-contacts404-1and404-2, respectively.

An LCR meter is usually used for measurement of the DUT pattern semiconductor device. The LCR meter410has a power supply and an ammeter. The power supply is connected between a ground terminal GND grounded and a high-voltage terminal High for supplying a first voltage. The ammeter is connected between a low-voltage terminal Low for supplying a second voltage lower than the first voltage, and the ground terminal GND. In the LCR meter410, a voltage, in which a small AC voltage is superimposed on a DC bias voltage, is applied between the high voltage terminal High and the low voltage terminal Low from the power supply to a target member, and an AC current (absolute value and phase) is measured by the ammeter. Thus, the capacitance of the target member (the PN junction capacitance in this example) is calculated.

The low voltage terminal Low and the high voltage terminal High of the LCR meter410are respectively connected to the second-layer metal wiring layers402-1and402-2so as to measure the PN junction capacitance409between the diffusion layer407of the N-type and the well406of the P-type by this LCR meter410.

There are two parasitic capacitances to be removed from the measurement in the DUT pattern semiconductor device: a parasitic capacitance411formed between the first-layer metal wiring layer401-1and the well406of the P-type; and a parasitic capacitance412formed between the first-layer metal wiring layer401-2and the well406of the P-type.

Next, an operation of a conventional semiconductor device measuring system will be described. The voltage in which a small AC voltage is superimposed on a DC bias voltage is applied to the second-layer metal wiring layer402-2from the high voltage terminal High of the LCR meter410. At this time, a charging/discharging current due to the PN junction capacitance409flows from the high voltage terminal High to the second-layer metal wiring layer402-2, the via-contacts404-2, the first-layer metal wiring layer401-2, the via-contact403-2, the diffusion layer408of the P-type, the well406of the P-type, the PN junction capacitance409, the diffusion layer407of the N-type, the via-contact403-1, the first-layer metal wiring layer401-1, the via-contacts404-1, the second-layer metal wiring layer402-1, and the low voltage terminal Low.

At the same time, a charging/discharging current due to the parasitic capacitance411flows from the high voltage terminal High to the second-layer metal wiring layer402-2, the via-contacts404-2, the first-layer metal wiring layer401-2, the via-contact403-2, the diffusion layer408of the P-type, the well406of the P-type, the parasitic capacitance411, the first-layer metal wiring layer401-1, the via-contacts404-1, the second-layer metal wiring layer402-1, and the low voltage terminal Low. Both ends of the parasitic capacitance412are electrically short-circuited by the first-layer metal wiring layer401-2, the via-contact403-2, the diffusion layer408of the P-type, and the well406of the P-type. Thus, the charging/discharging current by the parasitic capacitance412does not flow.

Here, the charging/discharging current due to the parasitic capacitance411flows to the low voltage terminal Low of the LCR meter410, so that the value of the parasitic capacitance411is included in the measured value of the LCR meter410. In this case, a total value of the PN junction capacitance409and the parasitic capacitance411is measured as the measured value of the LCR meter410.

FIG. 2Ashows a plan view of the calibration pattern semiconductor device.FIG. 2Bis a diagram showing the section of the semiconductor device along a line X-X′ ofFIG. 2Aand the semiconductor device measuring system applied to the calibration pattern semiconductor device. In the calibration pattern semiconductor device, the via-contact403-1is removed from the DUT pattern semiconductor device.

In the calibration pattern semiconductor device, because there is not the via-contact403-1, the charging/discharging current due to the PN junction capacitance409does not flow but only the charging/discharging current due to the parasitic capacitance411flows through the LCR410. In this case, the parasitic capacitance411is measured as the measured value of the LCR meter410.

In this manner, in the conventional semiconductor device measuring system, the value of only the PN junction capacitance409can be obtained by subtracting the measured value of the calibration pattern semiconductor device from the measured value of the DUT pattern semiconductor device.

CITATION LIST

SUMMARY OF THE INVENTION

In a conventional semiconductor device measuring system, two kinds of measurement patterns of a DUT pattern semiconductor device and a calibration pattern semiconductor device are required to correctly measure a semiconductor capacitance (here, PN junction capacitance), that is, to measure a semiconductor capacitance excluding a parasitic capacitance.

As described above, in the conventional semiconductor device measuring system, the DUT pattern semiconductor device and the calibration pattern semiconductor device need a nearly equal area. Thus, the area of the measurement pattern increases in the calibration pattern semiconductor device.

Further, in the conventional semiconductor device measuring system, two kinds of measurement patterns of the DUT pattern semiconductor device and the calibration pattern semiconductor device need to be prepared. AS a result, the number of man-hours required for designing increases.

Still further, in the conventional semiconductor device measuring system, the semiconductor capacitance needs to be measured in the DUT pattern semiconductor device and the calibration pattern semiconductor device. As a result, the number of man-hours required for measurement increases.

In an aspect of the present invention, a semiconductor device includes: a well of a second conductive type formed on or above a semiconductor substrate of a first conductive type; a first diffusion layer of the second conductive type formed in a surface portion of the well; a second diffusion layer of the first conductive type formed separately from the first diffusion layer in the surface portion of the well; first to third first-layer conductive layers formed above the well; and first to third second-layer conductive layers formed above the first to third first-layer conductive layers. The first second-layer conductive layer, the first first-layer conductive layer, the first diffusion layer and the well are conductively connected as a first conductive path. The second second-layer conductive layer, the second first-layer conductive layer, and the second diffusion layer are conductively connected as a second conductive path. The third second-layer conductive layer, and the third first-layer conductive layer are conductively connected as a third conductive path. In measurement of a capacitance between the well and the second diffusion layer, the first second-layer conductive layer is configured to be applied with a voltage, in which a small-amplitude AC voltage is superimposed on a DC bias voltage, from a measuring apparatus, the second second-layer conductive layer is configured to be connected to a ground terminal of the measuring apparatus through an ammeter, and the third second-layer conductive layer is configured to be connected to the ground terminal.

In another aspect of the present invention, a measuring method of a semiconductor device, is achieved by providing a semiconductor device which comprises:

a well of a second conductive type formed on or above a semiconductor substrate of a first conductive type,

a first diffusion layer of the second conductive type formed in a surface portion of the well,

a second diffusion layer of the first conductive type formed separately from the first diffusion layer in the surface portion of the well,

first to third first-layer conductive layers formed above the well, and

first to third second-layer conductive layers formed above the first to third first-layer conductive layers, wherein the first second-layer conductive layer, the first first-layer conductive layer, the first diffusion layer and the well are conductively connected as a first conductive path; wherein the second second-layer conductive layer, the second first-layer conductive layer, and the second diffusion layer are conductively connected as a second conductive path; wherein the third second-layer conductive layer, and the third first-layer conductive layer are conductively connected as a third conductive path. The measuring method is achieved by further applying the first second-layer conductive layer with a voltage, in which a small-amplitude AC voltage is superimposed on a DC bias voltage, from a power supply of a measuring apparatus; by further connecting the third second-layer conductive layer to the ground terminal; by further connecting the second second-layer conductive layer to a ground terminal of the measuring apparatus through the ammeter; and by further measuring a current flowing through the second second-layer conductive layer by an ammeter of the measuring apparatus.

As described above, according to the semiconductor device of the present invention, it is possible to measure the semiconductor capacitance excluding the parasitic capacitances, in other words, to correctly measure the semiconductor capacitance. Further, according to the semiconductor device of the present invention, it is possible to reduce the space of the measurement pattern and to shorten the measurement time as compared with the conventional semiconductor device measuring system.

DESCRIPTION OF EMBODIMENTS

Hereinafter, a semiconductor device according to the present invention will be described in detail with reference to the attached drawings.

First Embodiment

FIG. 3Ais a plan view of a semiconductor device according to a first embodiment of the present invention.FIG. 3Bis a diagram showing the section of the semiconductor device in the first embodiment along a line X-X′ ofFIG. 3Aand a semiconductor device measuring system applied to the semiconductor device.

The semiconductor device according to the first embodiment includes a semiconductor substrate100of a first conductive type; a well106of a second conductive type; first to fourth insulating films105-1to105-4; first and second diffusion layers107-1and107-2of the first conductive type; a diffusion layer108of the second conductive type; a fifth insulating film115; first to third via-contacts103-1to103-3; first to third first-layer conductive wiring layers101-1to101-3; a sixth insulating film116; first to third via-contacts104-1to104-3; and first to third second-layer conductive wiring layers102-1to102-3. Here, the first conductive type and the second conductive type are assumed to be an N-type and a P-type, respectively.

A P-type well106is formed on or above an N-type semiconductor substrate100. The insulating films105-1to105-4are formed in the surface portion of the P-type well106. An N-type diffusion layer107-1is formed between the insulating films105-1and105-2in the surface portion of the well106. An N-type diffusion layer107-2is formed between the insulating films105-2and105-3in the surface portion of the well106. A P-type diffusion layer108is formed between the insulating films105-3and105-4in the surface portion of the well106.

The P-type well106, the insulating films105-1to105-4, the N-type diffusion layers107-1and107-2, and the P-type diffusion layer108are covered with the insulating film115. The via-contact103-1is formed on the N-type diffusion layer107-1to pass through the insulating film115. The via-contact103-2is formed on the N-type diffusion layer107-2to pass through the insulating film115. The via-contact103-3is formed on the P-type diffusion layer108to pass through the insulating film115. The via-contacts103-1to103-3connect the diffusion layers107-1,107-2and108and first-layer conductive wiring layers101-1to101-3formed on the insulating film115, respectively.

The first-layer conductive wiring layers101-1to101-3are covered with the insulating film116. The via-contacts104-1are formed on the first-layer conductive wiring layer101-1to pass through the insulating film116. The via-contacts104-2are formed on the first-layer conductive wiring layer101-2to pass through the insulating film116. The via-contacts104-3are formed on the first-layer conductive wiring layer101-3to pass through the insulating film116. The via-contacts104-1to104-3connect the first-layer conductive wiring layers101-1to101-3and the second-layer conductive wiring layers102-1to102-3formed on the insulating film116, respectively.

The conductive wiring layers may be metal wiring layers. Also, a metal layer may be formed on the N-type diffusion layer107-1.

An LCR meter is usually used for measurement of the semiconductor device. The LCR meter110has a power supply and an ammeter. The power supply is connected between a high voltage terminal High for supplying a first voltage, and a ground terminal GND grounded. The ammeter is connected between a low voltage terminal Low for supplying a second voltage lower than the first voltage, and the ground terminal GND. In the LCR meter110, a voltage, in which a small AC voltage is superimposed on a DC bias voltage, is applied from the power supply to a target semiconductor device between the high voltage terminal High and the low voltage terminal Low, and an AC current (absolute value and phase) is measured by the ammeter. Thus, a capacitance of the target semiconductor device (PN junction capacitance in this example) is calculated. Also, a coaxial cable is usually used for wiring from the LCR meter110to the target semiconductor device. To block noise from the outside, the shield side of the coaxial cable is connected to the ground terminal GND.

In order to measure the PN junction capacitance109between the N-type diffusion layer107-2and the P-type well106by this LCR meter110, the ground terminal GND, the low voltage terminal Low, and the high voltage terminal High of the LCR meter110are respectively connected to the second-layer conductive wiring layers102-1to102-3.

However, in the structure of the semiconductor device according to the first embodiment of the present invention, there are the following four kinds of parasitic capacitances to be removed from the calculation of the PN junction capacitance: a parasitic capacitance111formed between the first-layer conductive wiring layer101-1and the P-type well106; a parasitic capacitance112formed between the first-layer conductive wiring layer101-2and the N-type diffusion layer107-1beneath the layer101-2; a parasitic capacitance113formed between the N-type diffusion layer107-1and the P-type well106; and a parasitic capacitance114caused between the first-layer conductive wiring layer101-3and the P-type well106.

Next, an operation of a semiconductor device measuring system will be described.

The voltage in which the small AC voltage is superimposed on the DC bias voltage is applied to the second-layer conductive wiring layers102-3from the high voltage terminal High of the LCR meter110. At this time, a charging/discharging current due to the PN junction109flows through two paths: a first path is from the high voltage terminal High to the second-layer conductive wiring layer102-3, the via-contacts104-3, the first-layer conductive wiring layer101-3, the via-contact103-3, the P-type diffusion layer108, and the P-type well106, and a second path is from the P-type well106to the PN junction capacitance109, the N-type diffusion layer107-2, the via-contact103-2, the first-layer conductive wiring layer101-2, the via-contacts104-2, the second-layer metal layer102-2, and the low voltage terminal Low.

At the same time, a charging/discharging current due to the parasitic capacitance113flows through the first path from the high voltage terminal High to the second-layer conductive wiring layer102-3, the via-contacts104-3, the first-layer conductive wiring layer101-3, the via-contact103-3, the P-type diffusion layer108, and the P-type well106, and a third path from the P-type well106to the parasitic capacitance113, the N-type diffusion layer107-1, the via-contact103-1, the first-layer conductive wiring layer101-1, the via-contacts104-1, the second-layer conductive wiring layer102-1, and the ground terminal GND.

Further, also a charging/discharging current due to the parasitic capacitance111flows through the first path from the high voltage terminal High to the second-layer conductive wiring layer102-3, the via-contacts104-3, the first-layer conductive wiring layer101-3, the via-contact103-3, the P-type diffusion layer108, and the P-type well106, and a fourth path from the P-type well to the parasitic capacitance111, the first-layer conductive wiring layer101-1, the via-contacts104-1, the second-layer conductive wiring layer102-1, and the ground terminal GND. Thus, the fourth path is a part of the third path.

Here, the charging/discharging currents by the parasitic capacitance111and the parasitic capacitance113do not flow through the low voltage terminal Low of the LCR meter110but flow to the ground terminal GND. Thus, the values of the parasitic capacitance111and the parasitic capacitance113are not included in the measured value of the LCR meter110.

Also, regarding a charging/discharging current due to the parasitic capacitance112, the low voltage terminal Low of the LCR meter110is grounded together with the ground terminal GND, so that the second-layer conductive wiring layers102-1and102-2have the same voltage, and therefore both ends of the parasitic capacitance112are the same voltage. Thus, the charging/discharging current due to the parasitic capacitance112does not flow.

Also, regarding a charging/discharging current due to the parasitic capacitance114, both ends of the parasitic capacitance114are electrically shorted by the second-layer conductive wiring layer102-3, the via-contacts104-3, the first-layer conductive wiring layer101-3, the via-contact103-3, the P-type diffusion layer108, and the P-type well106. Thus, the charging/discharging current due to the parasitic capacitance114does not flow.

In this case, only the value of the PN junction capacitance109is measured as a measured value of the LCR meter110.

As described above, according to the semiconductor device according to the first embodiment of the present invention, the diffusion layer of the first conductive type107-1is grounded. Therefore, it is possible to measure the semiconductor capacitance other than the parasitic capacitances111to114, in other words, to correctly measure the semiconductor capacitance.

Further, according to the semiconductor device according to the first embodiment of the present invention, a calibration pattern for cancelling the parasitic capacitances111to114(or a calibration pattern semiconductor device) is not required and thus it is possible to reduce a chip area of the measurement pattern and to shorten the measurement time, as compared with the conventional semiconductor device measuring system.

FIG. 3Cis a plan view of a plane Y-Y′ plane inFIG. 3B, andFIG. 3Dis a plan view of a plane Z-Z′ inFIG. 3B. The first-layer conductive wiring layer101-1includes a first planar shape corresponding wiring portion101-1aand a first support wiring portion101-1b. The planar shape of the planar shape corresponding wiring portion101-1acorresponds to the planer shape of the second-layer conductive wiring layer102-1. In a plane, the support wiring portion101-1bextends in parallel to the N-type semiconductor substrate100and has its one end connected to the via-contact103-1and the other end connected to the planar shape corresponding wiring portion101-1a.

The first-layer conductive wiring layer101-2includes a second planar shape corresponding wiring portion101-2aand a second support wiring portion101-2b. The planar shape of the planar shape corresponding wiring portion101-2acorresponds to the planer shape of the second-layer conductive wiring layer102-2. In the plane, the support wiring portion101-2bextends in parallel to the N-type semiconductor substrate100and has its one end connected to the via-contact103-2and the other end connected to the planar shape corresponding wiring portion101-2a.

The first-layer conductive wiring layer101-1further includes first and second first-layer surrounding wiring portions101-1cand101-1d. In the plane, the first-layer surrounding wiring portions101-1cis connected to the support wiring portion101-1bto surround the planar shape corresponding wiring portion101-2a. The first-layer surrounding wiring portions101-1dis connected to the first-layer surrounding wiring portion101-1cto surround the support wiring portion101-2b.

The first-layer conductive wiring layer101-3includes a third planar shape corresponding wiring portion101-3aand a third support wiring portion101-3b. The planar shape of the planar shape corresponding wiring portion101-3acorresponds to the planar shape of the second-layer conductive wiring layer102-3. In the plane, the support wiring portion101-3bextends parallel to the N-type semiconductor substrate100and has its one end connected to the via-contact103-3and the other end connected to the planar shape corresponding wiring portion101-3a.

As described above, according to the semiconductor device according to the first embodiment of the present invention, the first-layer conductive wiring layer101-2is surrounded in the plane by the first-layer conductive wiring layer101-1. With this, the first-layer conductive wiring layer101-1is shielded by the first-layer conductive wiring layer101-2in such a manner that the first-layer conductive wiring layer101-1does not receive influence of noise from the outside.

Further, according to the semiconductor device according to the first embodiment of the present invention, the N-type diffusion layer107-1is formed directly below the planar shape corresponding wiring portion101-2aand the first-layer surrounding wiring layer101-1cthrough the insulating film116. With this, a portion below the first-layer conductive wiring layers101-1and101-2is shielded by the N-type diffusion layer107-1, in such a manner that the first-layer conductive wiring layers101-1and101-2do not receive influence of noise from the outside.

In the semiconductor device according to the first embodiment of the present invention, the first conductive type and the second conductive type are not limited to the N-type and the P-type, but may be the P-type and the N-type. In this case, in the semiconductor device according to the first embodiment of the present invention, the semiconductor capacitance can be measured in the same manner as described above. However, the polarity of the DC bias voltage in the LCR meter110needs to be reversed.

Further, in the semiconductor device according to the first embodiment of the present invention, the semiconductor capacitance is not limited to the PN junction capacitance109, but may be an oxide film capacitance and a wiring-to-wiring capacitance. Even in such a case, the semiconductor capacitance other than the parasitic capacitances can be measured. Moreover, when there are a plurality of capacitance patterns, the shield terminal corresponding to the second-layer conductive wiring layer102-1can be commonly used.

Second Embodiment

FIG. 4Ais a plan view of the semiconductor device according to a second embodiment of the present invention.FIG. 4Bis a diagram showing the section of the semiconductor device along a line X-X′ ofFIG. 4Aand a semiconductor device measuring system applied to the semiconductor device according to the second embodiment of the present invention.

In the semiconductor device according to the second embodiment of the present invention, second-layer conductive wiring layers202-1and202-2are formed in place of the second-layer conductive wiring layers102-1and102-2. In the description of the second embodiment, same descriptions as those of the first embodiment will be omitted.

FIG. 4Cis a plan view of the semiconductor device along a plane Y-Y′ ofFIG. 4BandFIG. 4Dis a plan view of the semiconductor device along a plane Z-Z′ ofFIG. 4B. The second-layer conductive wiring layers202-1includes a second-layer planar shape corresponding wiring portion202-1aand first and second second-layer surrounding wiring portions202-1band202-1c. In the plane, the second-layer planar shape corresponding wiring portion202-1acorresponds to the planar shape of the planar shape corresponding wiring portion101-1aand has the same planar shape as that of the second-layer conductive wiring layer202-2. The second-layer surrounding wiring portion202-1bsurrounds the second-layer planar shape corresponding wiring portion202-1a. The second-layer surrounding wiring portion202-1cis connected to the second-layer surrounding wiring portion202-1band surrounds the second-layer conductive wiring layer202-2.

As described above, according to the semiconductor device according to the second embodiment of the present invention, the second-layer conductive wiring layer202-2is surrounded in the plane by the second-layer conductive wiring layer202-1. With this, the second-layer conductive wiring layer202-1is shielded by the second-layer conductive wiring layer202-2, in such a manner that the second-layer conductive wiring layer202-1can reduce the influence of noise from the outside more than in the first embodiment.

Third Embodiment

In the first embodiment, a portion below the first-layer conductive wiring layers101-1and101-2is shielded by the diffusion layer107-1of the first conductive type, but in a third embodiment, a portion below a conductive wiring layer is shielded by another conductive wiring layer.

FIG. 5Ais a plan view of a semiconductor device according to a third embodiment of the present invention.FIG. 5Bis a diagram showing a section of the semiconductor device along a line X-X′ ofFIG. 5Aand a semiconductor device measuring system applied to the semiconductor device.

The semiconductor device according to the third embodiment of the present invention includes: a semiconductor substrate300of the first conductive type; a well308of the second conductive type; first to third insulating films307-1to307-3; a diffusion layer309of the first conductive type; a diffusion layer310of the second conductive type; a fourth insulating film316; first and second first-layer via-contacts304-1and304-2; first to third first-layer conductive wiring layers301-1to301-3; a fifth insulating layer317; first to third second-layer via-contacts305-1to305-3; first to third second-layer conductive wiring layers302-1to302-3; a sixth insulating film318; first to third via-contacts306-1to306-3; and first to third third-layer conductive wiring layers303-1to303-3. Here, the first conductive type and the second conductive type are assumed to be the N-type and the P-type, respectively.

The P-type well308is formed on the N-type semiconductor substrate300. The insulating films307-1to307-3are formed in the surface portion of the P-type well308. The N-type diffusion layer309is formed between the insulating film307-1and the insulating film307-2in the surface portion of the P-type well308. The diffusion layer310of the P-type is formed between the insulating film307-2and the insulating film307-3in the surface portion of the P-type well308.

The P-type well308, the insulating films307-1to307-3, the N-type diffusion layer309, and the P-type diffusion layer310are covered with the insulating film316. The first-layer via-contact304-1is formed on the N-type diffusion layer309to pass through the insulating film316. The first-layer via-contact304-2is formed on the P-type diffusion layer310to pass through the insulating film316. The first-layer conductive wiring layers301-1,301-2, and301-3are formed on the insulating layer316and the first-layer via-contacts304-1and304-2.

The first-layer conductive wiring layers301-1to301-3are covered with the insulating film317. The second-layer via-contact305-1is formed on the first-layer conductive wiring layer301-1to pass through the insulating film317. The second-layer via-contact305-2is formed on the first-layer conductive wiring layer301-2to pass through the insulating film317. The second-layer via-contact305-3is formed on the first-layer conductive wiring layer301-3to pass through the insulating film317. The second-layer conductive wiring layers302-1to302-3are formed on the second-layer via-contacts305-1to305-3, respectively.

The second-layer conductive wiring layers302-1to302-3are covered with the insulating film318. The via-contacts306-1are formed on the second-layer conductive wiring layer302-1to pass through the insulating film318. The via-contacts306-2are formed on the second-layer conductive wiring layer302-2to pass through the insulating film318. The via-contacts306-3formed on the second-layer conductive wiring layer302-3to pass through the insulating film318. The third-layer conductive wiring layers303-1to303-3are formed on the via-contacts306-1to306-3, respectively.

The conductive wiring layers may be metal wiring layers.

An LCR meter110is connected to the semiconductor device according to the third embodiment of the present invention. The LCR meter is usually used for measurement of the semiconductor. The LCR meter110has a power supply and an ammeter. The power supply is connected between a high voltage terminal High for supplying a first voltage, and a ground terminal GND grounded. The ammeter is connected between a low voltage terminal Low for supplying a second voltage lower than the first voltage, and the ground terminal GND. In the LCR meter110, the voltage, in which a small AC voltage is superimposed on a DC bias voltage, is applied between the high voltage terminal High and the low voltage terminal Low from the power supply to a target semiconductor device, and an AC current (absolute value and phase) is measured by the ammeter. Thus, a capacitance (a PN junction capacitance in this example) of the target semiconductor device is calculated. Further, a coaxial cable is usually used as a wiring from the LCR meter110to the target semiconductor device. To shield noise from the outside, the shield side of the coaxial cable is connected to the ground terminal GND.

In order to measure the PN junction capacitance314between the N-type diffusion layer309and the P-type well308by this LCR meter110, the third-layer conductive wiring layers303-1to303-3are connected to the ground terminal GND, the low voltage terminal Low, and the high voltage terminal High of the LCR meter110, respectively. However, parasitic capacitances to be removed from the measurement result in the semiconductor device according to the third embodiment of the present invention are of the following three kinds: a parasitic capacitance311formed between the first-layer conductive wiring layer301-1and the P-type well308; a parasitic capacitance312formed between the first-layer conductive wiring layer302-2and the first-layer conductive wiring layer301-1beneath the layer302-2; and a parasitic capacitance313formed between the first-layer conductive wiring layer302-3and the P-type well308.

Next, an operation of the system of measuring the semiconductor device will be described. The voltage obtained by superimposing the small-amplitude AC voltage signal on the DC bias voltage signal is applied to the third-layer conductive wiring layer303-3from the high voltage terminal High of the LCR meter315.

At this time, a charging/discharging current due to the PN junction capacitance314flows through a first path from the high voltage terminal High to the third-layer conductive wiring layer303-3, the via-contacts306-3, the second-layer conductive wiring layer302-3, the second-layer via-contact305-3, the first-layer conductive wiring layer301-3, the first-layer via-contact304-3, the P-type diffusion layer310, and the P-type well308, and through a second path from the P-type well308, to the PN junction capacitance314, the N-type diffusion layer309, the first-layer via-contact304-1, the first-layer conductive wiring layer301-2, the second-layer via-contact305-2, the second-layer conductive wiring layer302-2, the via-contacts306-2, the third-layer conductive wiring layer303-2, and the low voltage terminal Low in this order.

At the same time, a charging/discharging current due to the parasitic capacitance311flows through the first path from the high voltage terminal High to the third-layer conductive wiring layer303-3, the via-contacts306-3, the second-layer conductive wiring layer302-3, the second-layer via-contact305-3, the first-layer conductive wiring layer301-3, the first-layer via-contact304-3, the P-type diffusion layer310, and the P-type well308, and a third path from the P-type well308to the parasitic capacitance311, the first-layer conductive wiring layer301-1, the second-layer via-contact305-1, the second-layer conductive wiring layer302-1, the via-contacts306-1, the third-layer conductive wiring layer303-1, and the ground terminal GND in this order.

Here, since the charging/discharging currents due to the parasitic capacitance311does not flow through the low voltage terminal Low of the LCR meter110but flows to the ground terminal GND, the value of the parasitic capacitance311is not included in the measured value of the LCR meter315.

Also, regarding the charging/discharging current due to the parasitic capacitance312, the low voltage terminal Low of the LCR meter110is grounded together with the ground terminal GND. Therefore, the third-layer conductive wiring layers303-1and303-2are set to the same voltage. Thus, both ends of the parasitic capacitance312are set to the same voltage and accordingly the charging/discharging current by the parasitic capacitance312does not flow.

Also, regarding the charging/discharging current due to the parasitic capacitance313, both end of the parasitic capacitance313is electrically short-circuited by the third-layer conductive wiring layer303-3, the via-contacts306-3, the second-layer conductive wiring layer302-3, the second-layer via-contact305-3, the first-layer conductive wiring layer301-3, the first-layer via-contact304-3, the P-type diffusion layer310, and the P-type well308. Thus, the charging/discharging current due to the parasitic capacitance313does not flow.

In this case, only the value of the PN junction capacitance314is measured as the measured value of the LCR meter315.

As described above, according to the semiconductor device according to the third embodiment of the present invention, the first-layer conductive wiring layer301-1is formed and the first-layer conductive wiring layer301-1is grounded, so that it is possible to measure the semiconductor capacitance (the PN junction capacitance314) other than the parasitic capacitances311to313, in other words, to correctly measure the semiconductor capacitance.

Further, according to the semiconductor device according to the third embodiment of the present invention, a measurement pattern for calibration (calibration pattern semiconductor device) for cancelling the parasitic capacitances311to313is not required and thus it is possible to reduce the chip area of the measurement pattern and to shorten the measurement time as compared with the conventional semiconductor device measuring system.

FIG. 5Cis a plan view of the semiconductor device along a plane V-V′ ofFIG. 5B, andFIG. 5Dis a plan view of the semiconductor device along a plane Y-Y′ ofFIG. 5B, andFIG. 5Eis a plan view of the semiconductor device along a plane Z-Z′ ofFIG. 5B.

The second-layer conductive wiring layer302-1includes a first planar shape corresponding wiring portion302-1aand a first support wiring portion302-1b. The planar shape of the planar shape corresponding wiring portion302-1acorresponds to the planer shape of the third-layer conductive wiring layer303-1. In the plane, the support wiring portion302-1bextends in parallel to the N-type semiconductor substrate300and has its one end connected to the second-layer via-contact305-1and the other end connected to the planar shape corresponding wiring portion302-1a.

The second-layer conductive wiring layer302-2includes a second planar shape corresponding wiring portion302-2aand a second support wiring portion302-2b. The planar shape of the planar shape corresponding wiring portion302-2acorresponds to the planer shape of the third-layer conductive wiring layer303-2. In the plane, the support wiring portion302-2bextends in parallel to the N-type semiconductor substrate300and has its one end connected to the second-layer via-contact305-2and the other end connected to the planar shape corresponding wiring portion302-2a.

The second-layer conductive wiring layer302-1further includes first and second second-layer surrounding wiring portions302-1cand302-1d. In the plane, the second-layer surrounding wiring portion302-1cis connected to the support wiring portion302-1bto surround the planar shape corresponding wiring portion302-2a. The second-layer surrounding wiring portion302-1dis connected to the second-layer surrounding wiring portion302-1cto surround the support wiring portion302-2b.

The second-layer conductive wiring layer302-3includes a third planar shape corresponding wiring portion302-3aand a third support wiring portion302-3b. In the plane, the planar shape of the planar shape corresponding wiring portion302-3acorresponds to the planar shape of the third-layer conductive wiring layer303-3. The support wiring portion302-3bextends in parallel to the N-type semiconductor substrate300and has its one end connected to the second-layer via-contact305-3and the other end connected to the planar shape corresponding wiring portion302-3a.

The first-layer conductive wiring layer301-1includes first and second first-layer planar shape corresponding wiring portions301-1aand301-1band a first-layer surrounding wiring portion301-1c. In the plane, the planar shape of the first-layer planar shape corresponding wiring portion301-1acorresponds to the planar shape of the planar shape corresponding wiring portion302-1aor the planar shape of the third-layer conductive wiring layer303-3. The first-layer planar shape corresponding wiring portion301-1bis connected to the first-layer planar shape corresponding wiring portion301-1a. The first-layer surrounding wiring portion301-1cis connected to the first-layer planar shape corresponding wiring portion301-1bto surround the first-layer conductive wiring layer301-2.

As described above, according to the semiconductor device according to the third embodiment of the present invention, the second-layer conductive wiring layer302-2is surrounded in the plane by the second-layer conductive wiring layer302-1. With this, the second-layer conductive wiring layer302-1is shielded by the second-layer conductive wiring layer302-2, and the second-layer conductive wiring layer302-1do not receive the influence of noise from the outside.

Further, according to the semiconductor device according to the third embodiment of the present invention, the first-layer conductive wiring layer301-1is formed below the second-layer conductive wiring layers302-1and302-2via the insulating film317. With this, the first-layer conductive wiring layer301-1shields a portion below the second-layer conductive wiring layers302-1and302-2, and therefore, the second-layer conductive wiring layers302-1and302-2do not receive the influence of noise from the outside.

In the semiconductor device according to the third embodiment of present invention, the first conductive type and the second conductive type are not limited to the N-type and the P-type but may be the P-type and the N-type. In this case, in the semiconductor device according to the third embodiment of the present invention, the semiconductor capacitance can be measured in the same manner. However, the polarity of the DC bias in the LCR meter315needs to be reversed.

Further, in the semiconductor device according to the third embodiment of present invention, the semiconductor capacitance is not limited to the PN junction capacitance314but may be an oxide film capacitance and a wiring-to-wiring capacitance. Even in this case, the semiconductor capacitance other than the parasitic capacitances can be measured. Moreover, when there are a plurality of capacitance patterns, the shield terminal corresponding to the third conductive wiring layer303-1can be commonly used.