Nonvolatile memory device having a ferroelectric layer

A nonvolatile memory device according to an embodiment includes a substrate having an upper surface, and a gate structure disposed over the substrate. The gate structure includes at least one gate electrode layer pattern and at least one gate insulation layer pattern, which are alternately stacked along a first direction perpendicular to the upper surface. The gate structure extends in a second direction perpendicular to the first direction. The nonvolatile memory device includes a ferroelectric layer disposed on at least a portion of one sidewall surface of the gate structure. The one sidewall surface of the gate structure forms a plane substantially parallel to the first and second directions. The nonvolatile memory device includes a channel layer disposed on the ferroelectric layer, and a source electrode structure and a drain electrode structure disposed to contact the channel layer and spaced apart from each other in the second direction.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean Patent Application No. 10-2019-0163139, filed on Dec. 9, 2019, which is herein incorporated by reference in its entirety.

BACKGROUND

1. Technical Field

The present disclosure relates generally to a nonvolatile memory device and, more particularly, to a nonvolatile memory device having a ferroelectric layer.

2. Related Art

As the design rule decreases and the degree of integration increases, research has continued on the structures of semiconductor devices that can guarantee both structural stability and reliability of signal storage operations. Currently, a flash memory device with a charge storage scheme using a three-layer stacked structure of a charge tunneling layer, a charge trap layer, and a charge barrier layer has been widely utilized.

Recently, various nonvolatile memory devices having different structures from existing flash memory devices have been proposed. An example of a nonvolatile memory device is a ferroelectric memory device of a transistor structure. The ferroelectric memory device can non-volatilely store any one of remanent polarization having different sizes and orientations as signal information in a gate ferroelectric layer. In addition, the signal information may be read out by using a feature in which the magnitude of the operation current flowing through a channel layer between source and drain electrodes changes according to the stored remanent polarization.

SUMMARY

A nonvolatile memory device according to an aspect of the present disclosure includes a substrate having an upper surface, and a gate structure disposed over the substrate. The gate structure includes at least one gate electrode layer pattern and at least one gate insulation layer pattern, which are alternately stacked along a first direction perpendicular to the upper surface. The gate structure extends in a second direction perpendicular to the first direction. In addition, the nonvolatile memory device includes a ferroelectric layer disposed on at least a portion of one sidewall surface of the gate structure over the substrate. The one sidewall surface of the gate structure is a plane defined by the first and second directions. The nonvolatile memory device includes a channel layer disposed over the substrate and disposed on the ferroelectric layer, and a source electrode structure and a drain electrode structure each disposed over the substrate and disposed to contact the channel layer. The source electrode structure and the drain electrode structure are spaced apart from each other in the second direction.

A nonvolatile memory device according to another aspect of the present disclosure includes a substrate having an upper surface, and a gate structure disposed over the substrate. The gate structure includes at least one gate electrode layer pattern and at least one gate insulation layer pattern, which are alternately stacked along a first direction perpendicular to the upper surface. The gate structure extends in a second direction perpendicular to the first direction. The nonvolatile memory device includes a ferroelectric layer disposed on at least a portion of one sidewall surface of the gate structure, over the substrate. The one sidewall surface of the gate structure forms a plane substantially parallel to the first and second directions. The nonvolatile memory device includes a source electrode structure and a drain electrode structure disposed on the ferroelectric layer spaced apart from each other in the second direction, and a channel structure disposed over the substrate and disposed between the source electrode structure and the drain electrode structure. Each of the source electrode structure and the drain electrode structure is disposed on the ferroelectric layer.

A nonvolatile memory device according to another aspect of the present disclosure includes a substrate, and a gate structure disposed over the substrate having an upper surface. The gate structure includes at least one gate functional layer pattern and at least one gate insulation layer pattern, which are alternately stacked along a first direction perpendicular to the upper surface. The gate structure extends in a second direction perpendicular to the first direction. The nonvolatile memory device includes an interfacial insulation layer and a channel layer, which are sequentially disposed on one sidewall surface of the gate structure. The one sidewall surface of the gate structure is a plane defined by the first and second directions. The nonvolatile memory device includes a source electrode structure and a drain electrode structure spaced apart from each other in the second direction. Each of the source electrode structure and the drain electrode structure contacts the channel layer. The gate functional layer pattern includes a floating electrode layer part disposed on the interfacial insulation layer and the gate insulation layer pattern, a ferroelectric layer part disposed on the floating electrode layer part, and the interfacial insulation layer, and a gate electrode layer part disposed to contact the ferroelectric layer part.

DETAILED DESCRIPTION

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the drawings, in order to clearly express the components of each device, the sizes of the components, such as width and thickness of the components, are enlarged. The terms used herein may correspond to words selected in consideration of their functions in the embodiments, and the meanings of the terms may be construed to be different according to the ordinary skill in the art to which the embodiments belong. If expressly defined in detail, the terms may be construed according to the definitions. Unless otherwise defined, the terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments belong.

In addition, expression of a singular form of a word should be understood to include the plural forms of the word unless clearly used otherwise in the context. It will be understood that the terms “comprise” or “have” are intended to specify the presence of a feature, a number, a step, an operation, a component, an element, a part, or combinations thereof, but not used to preclude the presence or possibility of addition one or more other features, numbers, steps, operations, components, elements, parts, or combinations thereof.

In this specification, the term “a predetermined direction” may mean a direction encompassing one direction determined in a coordinate system and a direction opposite to the one direction. As an example, in the x-y-z coordinate system, the z-direction may mean all of a direction in which an absolute value of the z-axis increases in a positive direction along the z-axis from the origin0and a direction in which an absolute value of the z-axis increases in a negative direction along the z-axis from the origin0. The x-direction and the y-direction may each be interpreted in substantially the same way in the x-y-z coordinate system.

FIG. 1is a perspective view schematically illustrating a nonvolatile memory device1according to an embodiment of the present disclosure.FIG. 2is a plan view of the nonvolatile memory device ofFIG. 1.FIG. 3is a cross-sectional view taken along a line A-A′ of the nonvolatile memory device ofFIG. 1.

Referring toFIGS. 1 to 3, the nonvolatile memory device1may include a substrate101, first and second gate structures12and14, a source electrode structure22, a drain electrode structure24, first and second ferroelectric layers312and314, and first and second channel layers322and324. In addition, the nonvolatile memory device1may further include a base insulation layer110disposed on the substrate101and an insulation structure26extending in a first direction (i.e., the z-direction) perpendicular to the substrate101. A memory device structure including the first gate structure12, the first ferroelectric layer312and the first channel layer322may share the source electrode structure22, the drain electrode structure24and the insulation structure26with a memory device structure including the second gate structure14, the second ferroelectric layer314and the second channel layer324.

The substrate101may include a semiconductor material. Specifically, the semiconductor material may include silicon (Si), germanium (Ge), gallium arsenide (GaAs), and the like. The substrate101may be doped with an n-type dopant or a p-type dopant. As an example, the substrate101may include a well region doped with an n-type dopant or a p-type dopant.

The base insulation layer110may be disposed on the substrate101. The base insulation layer110may electrically insulate the first and second gate structures12and14, the first and second ferroelectric layers312and314, the first and second channel layers322and324, the source electrode structure22, and the drain electrode structure24from the substrate101, respectively.

Although not illustrated inFIG. 1, at least one conductive layer and at least one insulation layer may be disposed between the substrate101and the base insulation layer110. The conductive layer and the insulation layer may form various circuit patterns. That is, the conductive layer and the insulation layer may form a plurality of wirings or may constitute a passive element such as a capacitor or a resistor, or an active element such as a diode or a transistor, by way of non-limiting examples.

Referring toFIG. 1, the first gate electrode structure12may be disposed on the base insulation layer110. The first gate electrode structure12may include first to fourth gate electrode layer patterns122a,122b,122cand122dand first to fifth gate insulation layer patterns132a,132b,132c,132dand132e, which are alternately stacked along the first direction (i.e., the z-direction) perpendicular to the substrate101, on the base insulation layer110. The first gate insulation layer pattern132amay be disposed to contact the base insulation layer110. The fifth gate insulation layer pattern132emay be disposed as an uppermost layer of the first gate electrode structure12.

The first gate electrode structure12may extend in a second direction (i.e., the y-direction) perpendicular to the first direction. The first to fourth gate electrode layer patterns122a,122b,122cand122dmay be electrically insulated from each other by the first to fifth gate insulation layer patterns132a,132b,132c,132dand132e. The first to fourth gate electrode layer patterns122a,122b,122cand122dmay be conductive lines extending in the second direction (i.e., the y-direction). The first to fourth gate electrode layer patterns122a,122b,122cand122dmay each maintain a predetermined potential.

In an embodiment, the first to fourth gate electrode layer patterns122a,122b,122cand122dmay each include a conductive material. The conductive material may, for example, include a doped semiconductor material, metal, conductive metal silicide, conductive metal nitride, or conductive metal oxide. The conductive material may, for example, include n-type doped silicon, tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more thereof. The first to fifth gate insulation layer patterns132a,132b,132c,132dand132emay each include an insulative material. The insulative material may, for example, include oxide, nitride, oxynitride, and the like.

In some other embodiments, the number of the gate electrode layer patterns of the first gate electrode structure12may not necessarily be limited to four. The gate electrode layer patterns may be disposed in different various numbers, and the gate insulation layer patterns may insulate the various numbers of source electrode layer patterns along the first direction (i.e., the z-direction).

Referring toFIGS. 1 to 3, the first ferroelectric layer312may be disposed on the base insulation layer110and on one sidewall surface S1of the first gate structure12. Here, the one sidewall surface S1may form a plane substantially parallel to the first and second directions (i.e., a y-z plane to the z-direction and y-direction). The first ferroelectric layer312may have a predetermined thickness t1along a third direction (i.e., the x-direction) perpendicular to the first and second directions. The thickness t1may, for example, be 1 nanometers (nm) to 50 nanometers (nm), inclusive.

The first ferroelectric layer312may include a ferroelectric material. The ferroelectric material may have electrical remanent polarization in a state where no external electric field is applied. In addition, in the ferroelectric material, when an external electric field is applied, the electrical polarization may exhibit a hysteresis behavior. By controlling the external electric field, one of a plurality of stable polarization states on the polarization hysteresis curve can be written in the ferroelectric material. After the external electric field is removed from the ferroelectric material, the written polarization can be stored in the ferroelectric material in a form of remanent polarization. The remanent polarization may be used in nonvolatile storage for a plurality of pieces of signal information. The first ferroelectric layer312may, for example, include hafnium oxide, zirconium oxide, hafnium zirconium oxide, and the like. The first ferroelectric layer312may have a crystal structure of an orthorhombic system.

The first channel layer322may be disposed on the base insulation layer110and contact the first ferroelectric layer312. Specifically, the first channel layer322may be disposed on one surface S2of the first ferroelectric layer312defined by the first and second directions (i.e., the z-direction and y-direction). The first channel layer322may have a predetermined thickness t2along the third direction (i.e., the x-direction). The thickness t2may, for example, be 1 nanometers (nm) to 50 nanometers (nm), inclusive. Although the thickness of the first ferroelectric layer312is illustrated to be greater than the thickness of the first channel layer322inFIG. 3, the thickness of the first ferroelectric layer312is not limited thereto, and in other embodiments the thickness of the first ferroelectric layer312may be less than or equal to the thickness of the first channel layer322.

The first channel layer322may provide a path through which electrical carriers such as electrons or holes move between the source electrode structure22and the drain electrode structure24. The electrical resistance of the first channel layer322may be reduced when a conductive channel is formed in the first channel layer322, as described later. However, the electrical resistance of the conductive channel may also vary depending on the size and direction of the remanent polarization stored in the first ferroelectric layer312.

The first channel layer322may include, for example, a doped semiconductor material or metal oxide. The semiconductor material may, for example, include silicon (Si), germanium (Ge), gallium arsenide (GaAs), and the like. The metal oxide may include indium-gallium-zinc (In—Ga—Zn) oxide. In an embodiment, the first channel layer322may include silicon (Si) doped with an n-type dopant. Alternatively, the first channel layer322may include c-axis aligned indium-gallium-zinc (In—Ga—Zn) oxide. The first channel layer322may have a single crystal structure or a polycrystalline structure.

Referring toFIGS. 1 to 3again, the source electrode structure22and the drain electrode structure24may each be disposed on the base insulation layer110to contact surface S3of the first channel layer322, while being spaced apart from each other in the second direction (i.e., the y-direction). The source electrode structure22and the drain electrode structure24may each have a pillar-like shape extending along the first direction (i.e., the z-direction). The source electrode structure22and the drain electrode structure24may each be disposed to contact the first channel layer322and the second channel layer324.

The insulation structure26may be disposed between the source electrode structure22and the drain electrode structure24. The insulation structure26may be disposed to contact the first channel layer322and the second channel layer324. The insulation structure26may have a pillar-like shape extending in the first direction (i.e., z-direction) from the base insulation layer110. The insulation structure26may play a role in inhibiting the movement of the electrical carriers between the source electrode structure22and the drain electrode structure24through paths other than the first channel layer322or the second channel layer324.

The source electrode structure22and the drain electrode structure24may each maintain a predetermined electric potential. The electric potential of each of the source electrode structure22and the drain electrode structure24may be the same or different from each other. In an embodiment, during an operation of the nonvolatile memory device, if a conductive channel is formed in the first channel layer322or the second channel layer324and a predetermined potential difference occurs between the source electrode structure22and the drain electrode structure24, the electrical carriers may move through the conductive channel.

The source electrode structure22and the drain electrode structure24may each include a conductive material. The conductive material may, for example, include a doped semiconductor material, metal, conductive metal nitride, conductive metal oxide, conductive metal carbide, conductive metal silicide, and the like. The conductive material may, for example, include doped silicon, tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more thereof. The insulation structure26may include oxide, nitride, or oxynitride. As an example, the insulation structure26may include silicon oxide, silicon nitride, or silicon oxynitride.

Referring toFIGS. 1 to 3, the second channel layer324may be disposed on the base insulation layer110and may contact sidewalls of the source electrode structure22, drain electrode structure24and insulation structure26. Sidewalls of the source electrode structure22, drain electrode structure24and insulation structure26may be positioned on the same plane S4. The plane S4may form a plane substantially parallel to the first and second directions (i.e., a y-z plane parallel to the z-direction and y-direction). The second channel layer324may have a predetermined thickness t2along the third direction (i.e., the x-direction). The configuration of the second channel layer324may be substantially the same as the configuration of the first channel layer322.

The second ferroelectric layer314may be disposed on the base insulation layer110and on one surface S5of the second channel layer324. The one surface S5may be a plane defined by the first and second directions (i.e., a y-z plane parallel to the z-direction and y-direction). The second ferroelectric layer314may have a predetermined thickness t1along the third direction (i.e., the x-direction). The configuration of the second ferroelectric layer314may be substantially the same as the configuration of the first ferroelectric layer312.

The second gate structure14may be disposed on the base insulation layer110and contact one surface S6of the second ferroelectric layer314. The plane S6may form a plane substantially parallel to the first and second directions (i.e., a y-z plane parallel to the z-direction and y-direction). The second gate structure14may include first to fourth gate electrode layer patterns124a,124b,124cand124dand first to fifth gate insulation layer patterns134a,134b,134c,134dand134e, which are alternately stacked along the first direction (i.e., the z-direction). The first gate insulation layer pattern134amay be disposed to contact the base insulation layer110. The fifth gate insulation layer pattern134emay be disposed as the uppermost layer of the second gate structure14. The second gate structure14may extend in the second direction (i.e., the y-direction). The configurations of the first to fourth gate electrode layer patterns124a,124b,124cand124dand the first to fifth gate insulation layer patterns134a,134b,134c,134dand134eof the second gate structure14may be substantially the same as the configurations of the first to fourth gate electrode layer patterns122a,122b,122cand122dand the first to fifth gate insulation layer patterns132a,132b,132c,132dand132eof the first gate structure12.

As described above, in the nonvolatile memory device1according to an embodiment of the present disclosure, the first gate structure12and the second gate structure14may be disposed symmetrically with respect to each other across a y-z plane centered on the source electrode structure22, the insulation structure26, and the drain electrode structure24. Similarly, the first ferroelectric layer312and the second ferroelectric layer314may be disposed symmetrically with respect to each other, and the first channel layer322and the second channel layer324may be disposed symmetrically with respect to each other.

In an embodiment, the first gate structure12, the first ferroelectric layer312, the first channel layer322, the source electrode structure22and the drain electrode structure24may constitute one operation unit of the nonvolatile memory device1, and the second gate structure14, the second ferroelectric layer314, the second channel layer324, the source electrode structure22and the drain electrode structure24may constitute another operation unit of the nonvolatile memory device1. The source electrode structure22and the drain electrode structure24may be shared by the different operation units. That is, the first to fourth gate electrode layer patterns122a,122b,122cand122dof the first gate structure12, the first ferroelectric layer312and the first channel layer322may operate together with the source electrode structure22and the drain electrode structure24. In addition, the first to fourth gate electrode layer patterns124a,124b,124cand124dof the second gate structure14, the second ferroelectric layer314and the second channel layer324may operate together with the source electrode structure22and the drain electrode structure24.

FIGS. 4A to 4Eare views schematically illustrating an operation of a nonvolatile memory device according to an embodiment of the present disclosure.FIG. 4Ais a circuit diagram of a nonvolatile memory device according to an embodiment of the present disclosure.FIG. 4Bis a plan view of a portion of the nonvolatile memory device corresponding to the circuit diagram ofFIG. 4A.FIGS. 4C and 4Dare views schematically illustrating different remanent polarization stored in a ferroelectric layer of a nonvolatile memory device according to an embodiment of the present disclosure.FIG. 4Eis a cross-sectional view taken along a line B-B′ ofFIG. 4B.

Specifically,FIG. 4Bis a plan view schematically illustrating one operation unit1aof the nonvolatile memory device1described above with reference toFIGS. 1 to 3. The one operation unit1amay, for example, include a first gate structure12, a first ferroelectric layer312, a first channel layer322, a source electrode structure22, a drain electrode structure24and an insulation structure26. For the convenience of explanation related to the operation of the one operation unit1a, the uppermost gate insulation layer pattern134eof the first gate structure12is omitted inFIG. 4B.

Referring toFIG. 4A, first to fourth memory cells MC1, MC2, MC3and MC4are disclosed. The first to fourth memory cells MC1, MC2, MC3and MC4may each have a form of a transistor and include first to fourth ferroelectric layers FD1, FD2, FD3and FD4functioning as memory layers, respectively.

A source and a drain of each of the first to fourth memory cells MC1, MC2, MC3and MC4may be electrically connected to a global source line (GSL) and a global drain line (GDL). Gate electrodes of the first to fourth memory cells MC1, MC2, MC3and MC4may be electrically connected to first to fourth word lines GL1, GL2, GL3and GL4, respectively.

In relation to a write operation for at least one memory cell of the first to fourth memory cells MC1, MC2, MC3and MC4, first, at least one of the first to fourth word lines GL1, GL2, GL3and GL4may be selected. A polarization switching voltage having a magnitude greater than or equal to a predetermined threshold voltage may be applied to both ends of each of the first to fourth ferroelectric layers FD1, FD2, FD3and FD4of the corresponding first to fourth memory cells MC1, MC2, MC3and MC4, through the at least one selected word line. At this time, the global source line GSL and the global drain line GDL may be grounded. By applying a polarization switching voltage, the polarization of the first to fourth ferroelectric layers FD1, FD2, FD3and FD4may be switched and then aligned in a predetermined direction. After the polarization switching voltage is removed, the switched polarization may be stored in the corresponding first to fourth ferroelectric layers FD1, FD2, FD3and FD4in the form of remanent polarization. As a result, as described above, the polarization switching voltage is applied through at least one word line of the first to fourth word lines GL1, GL2, GL3and GL4, so that a write operation may be performed on at least one of the first to fourth memory cells MC1, MC2, MC3and MC4. After the write operation is completed, a predetermined signal may be stored in the corresponding memory cell in a nonvolatile manner.

Meanwhile, an operation of reading the signal non-volatilely stored in the first to fourth memory cells MC1, MC2, MC3and MC4may be performed. As an exemplary example, a process of reading a signal stored in the fourth memory cell MC4will be described. First, the fourth word line GL4corresponding to the fourth memory cell MC4is selected. Subsequently, a read voltage greater than or equal to a predetermined threshold voltage may be applied to a gate electrode of the fourth memory cell MC4through the fourth word line GL4. An absolute value of the read voltage may be smaller than an absolute value of the polarization switching voltage. That is, the polarization inside the fourth ferroelectric layer FD4may not be switched by the read voltage. The transistor of the fourth memory cell MC4is tuned on by the read voltage, and a conductive channel may be formed in the channel layer of the transistor. As a result, when a source-drain potential difference is formed between the global source line GSL and the global drain line GDL, a source-drain current may flow through the conductive channel.

The source-drain current may vary according to the orientation and size of the remanent polarization stored in the fourth ferroelectric layer FD4. As an example, when the remanent polarization is oriented from the gate electrode toward the channel layer (corresponding to a first polarization DP1inFIG. 4C), positive charges are accumulated inside the fourth ferroelectric layer FD4adjacent to the channel layer, thereby increasing the electron density of the conductive channel. Accordingly, the magnitude of the current flowing along the conductive channel may be increased. As another example, when the remanent polarization is oriented from the channel layer toward the gate electrode (corresponding to a second polarization DP2inFIG. 4D), negative charges are accumulated inside the fourth ferroelectric layer FD4adjacent to the channel layer, thereby reducing the electron density of the conductive channel. Accordingly, the magnitude of the current flowing along the conductive channel may be reduced. As described above, the signal stored in the memory cell can be read by turning on the transistor of the memory cell to be read and measuring the current flowing through the channel layer.

In other embodiments, the number of the memory cells disposed between the global source line GSL and the global drain line GDL is not necessarily limited to four, and other various numbers are possible. Similarly, the number of the word lines is not necessarily limited to four, and various other numbers are possible.

Referring toFIG. 4B, the global source line GSL described above with reference toFIG. 4Amay correspond to the source electrode structure22, and the global drain line GDL may correspond to the drain electrode structure24. Also, the first to fourth word lines GLS, GL2, GL3and GL4may correspond to the first to fourth gate electrode layer patterns122a,122b,122cand122dof the first gate structure12inFIGS. 1-3. Accordingly, the fourth word line GL4and the fourth ferroelectric layer FD4of the fourth memory cell MC4illustrated inFIG. 4Amay correspond to the fourth gate electrode layer pattern122dand a region of the first ferroelectric layer312covered by the fourth gate electrode layer pattern122dillustrated inFIG. 4B. Referring toFIGS. 4B and 4E, a channel layer of the fourth memory cell MC4illustrated inFIG. 4Amay correspond to an eight region322-hof the first channel layer322, between source electrode structure22and drain electrode structure24, covered by the fourth gate electrode layer pattern122d. Referring toFIGS. 1 to 3andFIG. 4E, the first channel layer322may include first to ninth regions322-a,322-b,322-c,322-d,322-e,322-f,322-g,322-hand322-ithat correspond to regions overlapping, between source electrode structure22and drain electrode structure24, the first to fourth gate electrode layer patterns122a,122b,122cand122dand the first to fifth gate insulation layer patterns132a,132b,132c,132dand132ealong the third direction (i.e., the x-direction). As an example, the channel layers of the first to third memory cells MC1, MC2and MC3illustrated inFIG. 4Amay correspond to the second region322-b, the fourth region322-dand the sixth region322-fof the first channel layer322inFIG. 4E.

Hereinafter, as an example, a write operation and a read operation for the memory cell structure including the fourth gate electrode layer pattern122d, the first ferroelectric layer312, the eighth portion322-hof the first channel layer322illustrated inFIGS. 4B to 4Ecorresponding to the fourth memory cell MC4of the nonvolatile memory device illustrated inFIG. 4Awill be described. Substantially the same write and read operations may be applied to the memory cell structures ofFIGS. 4B to 4Ecorresponding to the first to third memory cells MC1, MC2and MC3.

The write operation for the fourth memory cell MC4may be described usingFIGS. 4B to 4D. Referring toFIG. 4B, the fourth gate electrode layer pattern122dis selected from the first to fourth gate electrode layer patterns122a,122b,122cand122dof the first gate structure12. Subsequently, the source electrode structure22and the drain electrode structure24are grounded, and a first polarization switching voltage having a positive polarity is applied to the fourth gate electrode layer pattern122d. The first polarization switching voltage may be a voltage having an absolute value equal to or greater than a predetermined threshold voltage, such that the polarization orientation of the first ferroelectric layer312can be switched. When the first polarization switching voltage is applied, as illustrated inFIG. 4C, a first polarization DP1may be formed in a region of the first ferroelectric layer312covered by or common to the fourth gate electrode layer pattern122d. The first polarization DP1may be oriented from an interface region of the first ferroelectric layer312contacting the fourth gate electrode layer pattern122dtowards an interface region of the first ferroelectric layer312contacting the first channel layer322. Subsequently, the first polarization switching voltage is removed. Even after the first polarization switching voltage is removed, the first polarization DP1may be stored in the form of remanent polarization. In addition, the first polarization DP1is formed, so that positive charges CP and negative charges CN may be generated in the inner region of the first ferroelectric layer312. Even after the first polarization switching voltage is removed, the positive charges CP may be distributed in the interface region of the first ferroelectric layer312in contact with the first channel layer322, and the negative charges CN may be distributed in the interface region of the first ferroelectric layer312in contact with the fourth gate electrode layer pattern122d.

As another embodiment, inFIG. 4B, the fourth gate electrode layer pattern122dis selected from the first to fourth gate electrode layer patterns122a,122b,122cand122d. Subsequently, after the source electrode structure22and the drain electrode structure24are grounded, a second polarization switching voltage having a negative polarity is applied to the fourth gate electrode layer pattern122d. The second polarization switching voltage may be a voltage having an absolute value equal to or greater than a predetermined threshold voltage to switch the polarization orientation of the first ferroelectric layer312. When the second polarization switching voltage is applied, as described inFIG. 4D, a second polarization DP2may be formed in an inner region of the first ferroelectric layer312covered by the fourth gate electrode layer pattern122d. The second polarization DP2may be oriented from the interface region of the first ferroelectric layer312contacting the first channel layer322towards the interface region of the first ferroelectric layer312contacting the fourth gate electrode layer pattern122d. Subsequently, the second polarization switching voltage is removed. Even after the second polarization switching voltage is removed, the second polarization DP2may be stored in the form of remanent polarization. In addition, the second polarization DP2is formed, so that positive charges CP and negative charges CN may be generated in the inner region of the first ferroelectric layer312. Even after the second polarization switching voltage is removed, the positive charges CP may be distributed in the interface region of the first ferroelectric layer312contacting the fourth gate electrode layer pattern122d, and the negative charges CN may be distributed in the interface region of the first ferroelectric layer312contacting the first channel layer322. As described above, the write operation can be performed through the switching operation of the polarization orientation of the first ferroelectric layer312described above with reference toFIGS. 4B to 4D. As an example, the first polarization DP1forming operation related toFIG. 4Cmay be referred to as a program operation, and the second polarization DP2forming operation related toFIG. 4Dmay be referred to as an erase program.

Meanwhile, a read operation on the signal information stored in the fourth memory cell MC4will be described with reference toFIGS. 4B and 4E. First, a read voltage having an absolute value equal to or greater than a predetermined threshold voltage is applied to the fourth gate electrode layer pattern122d. The absolute value of the read voltage may be smaller than the absolute value of the first and second polarization switching voltages. That is, the polarization of the first ferroelectric layer312covered by the fourth gate electrode layer pattern122dmay not be switched by the read voltage.

Instead, a conductive channel CH4may be formed in the eighth region322-hof the first channel layer322adjacent to the first ferroelectric layer312by the read voltage. Referring toFIG. 4E, the conductive channel CH4may electrically connect the source electrode structure22to the drain electrode structure24. The electron density inside the conductive channel CH4may be higher than the electron density of the first channel layer322outside the conductive channel CH4.

After the conductive channel CH4is formed, a source-drain potential difference is formed between the source electrode structure22and the drain electrode structure24. As an example, after the source electrode structure22is grounded, a drain voltage having a positive polarity may be applied to the drain electrode structure24. Accordingly, electrons may flow from the source electrode structure22to the drain electrode structure24through the conductive channel CH4. At this time, the current density generated by the flow of the electrons may be influenced by the orientation of the remanent polarization stored in the adjacent first ferroelectric layer312. When the orientation of the remanent polarization is the same as that of the first polarization DP1ofFIG. 4C, the electron density inside the conductive channel CH4increases, so that the current density flowing along the conductive channel CH4may increase. Conversely, when the orientation of the remanent polarization is the same as that of the second polarization DP2inFIG. 4D, the electron density inside the conductive channel CH4decreases, so that the current density flowing along the conductive channel CH4may decrease. As described above, by forming a conductive channel in a channel layer of a memory cell to be read, and by measuring the current flowing through the conductive channel, the signal stored in the memory cell can be read.

According to an embodiment of the present disclosure, a nonvolatile memory device may include a gate structure, a source electrode structure and a drain electrode structure disposed in a direction perpendicular to a substrate. In addition, the nonvolatile memory device may include a ferroelectric layer and a channel layer disposed adjacent to the gate structure, the source electrode structure and the drain electrode structure. In the nonvolatile memory device, a plurality of memory cells may be randomly accessed through independently selectable gate electrode layer patterns. Through this, the nonvolatile memory device can independently perform write and read operations on the accessed memory cell.

FIG. 5is a perspective view schematically illustrating a nonvolatile memory device2according to another embodiment of the present disclosure.FIG. 6Ais a circuit diagram schematically illustrating the nonvolatile memory device ofFIG. 5.FIG. 6Bis a partial plan view of the nonvolatile memory device, corresponding to the circuit diagram ofFIG. 6A, andFIG. 6Cis a cross-sectional view taken along a line C-C′ ofFIG. 6B.FIGS. 6A and 6Bmay be views schematically illustrating one operation unit2aof the nonvolatile memory device2ofFIG. 5.

Referring toFIG. 5, the nonvolatile memory device2may include a plurality of source electrode structures22aand22b, a plurality of drain electrode structures24aand24b, and insulation structures26a,26band27disposed on a base insulation layer110along a second direction (i.e., the y-direction), as compared to the nonvolatile memory device1described above with reference to FIGS.1to3. As an embodiment, as illustrated, a first source electrode structure22a, a first insulation structure26a, a first drain electrode structure24a, an inter-element insulation structure27, a second source electrode structure22b, a second insulation structure26b, and a second drain electrode structure24bmay be sequentially disposed along the second direction (i.e., the y-direction). Although the numbers of the source electrode structures, the drain electrode structures, and the insulation structures are shown as two inFIG. 5, devices contemplated by the disclosure are not necessarily limited thereto. In other embodiments, the numbers of the source electrode structures, the drain electrode structures, and the insulation structures may vary along the second direction (i.e., the y-direction).

Meanwhile, referring toFIG. 5, the first and second gate structures12and14, the first and second ferroelectric layers312and314, and the first and second channel layers322and324may extend along the second direction (i.e., the y-direction) on the base insulation layer110, and cover the plurality of source electrode structures22aand22b, the plurality of drain electrode structures24aand24b, and the insulation structures26a,26band27. A first operation unit2aillustrated inFIGS. 6B and 6Cmay correspond to a portion of the nonvolatile memory device2ofFIG. 5. As an example, the first operation unit2amay include the first gate structure12, the first ferroelectric layer312, the first channel layer322, the first and second source electrode structures22aand22b, the first and second drain electrode structures24aand24b, and the insulation structures26a,26band27. Referring toFIG. 5, a second operation unit2bmay correspond to another portion of the nonvolatile memory device2. As an example, the second operation unit2bmay include the second gate structure14, the second ferroelectric layer314, the second channel layer324, the first and second source electrode structures22aand22b, the first and second drain electrode structures24aand24b, and the insulation structures26a,26band27. Hereinafter, a method of operating the nonvolatile memory device2will be described using the first operation unit2aas an example, but the method may be substantially equally applied to second operation unit2b, as well as to operation units in other embodiments.

Referring toFIGS. 5, 6A to 6C, a first global source line GSL1and a first global drain line GDL1ofFIG. 6Amay correspond to the first source electrode structure22aand the first drain electrode structure24a, respectively, of the first operation unit2aillustrated inFIGS. 5, 6B and 6C. A second global source line GSL2and a second global drain line GDL2ofFIG. 6Amay correspond to the second source electrode structure22band the second drain electrode structure24b, respectively, of the first operation unit2aillustrated inFIGS. 5, 6B and 6C. A first global gate line GGL1ofFIG. 6Amay correspond to the first gate electrode layer pattern122aof the first operation unit2aillustrated inFIGS. 5, 6B and 6C. Likewise, second to fourth global gate lines GGL2, GGL3and GGL4ofFIG. 6Amay correspond to the second to fourth gate electrode layer patterns122b,122cand122d, respectively, of the first operation unit2aillustrated inFIGS. 5, 6B and 6C.

Referring toFIG. 6A, the first to fourth memory cells MC1, MC2, MC3and MC4may each be connected to the first global source line GSL1and the first global drain line GDL1. Likewise, the fifth to eighth memory cells MC5, MC6, MC7and MC8may each be connected to the second global source line GSL2and the second global drain line GDL2. The first and fifth memory cells MC1and MC5may be connected to the first global gate line GGL1and may have first and fifth ferroelectric layers FD1and FDS, respectively. Likewise, the second and sixth memory cells MC2and MC6may be connected to the second global gate line GGL2and may have second and sixth ferroelectric layers FD2and FD6, respectively. The third and seventh memory cell MC3and MC7may be connected to a third global gate line GGL3and may have third and seventh ferroelectric layers FD3and FD7, respectively. The fourth and eighth memory cells MC4and MC8may be connected to a fourth global gate line GGL4and may have fourth and eighth ferroelectric layers FD4and FD8, respectively.

Hereinafter, as examples of an embodiment, a write operation and a read operation will be described for a memory cell structure including the fourth gate electrode layer pattern122d, the first ferroelectric layer312, and the eighth portion322a-8of the first channel part322aof the first operation unit2ashown inFIGS. 5, 6B and 6C. These structures correspond to components of the fourth memory cell MC4of the nonvolatile memory device illustrated inFIG. 6A. Similarly, substantially same write operation and read operation may be performed with structures corresponding to the first to third and fifth to eighth memory cells MC1, MC2, MC3, MC5, MC6, MC7and MC8.

Referring toFIG. 6C, the first channel layer322may include, along the second direction (i.e., the y-direction), a first channel part322adisposed between the first source electrode structure22aand the first drain electrode structure24a, a second channel part322bdisposed between the second source electrode structure22band the second drain electrode structure24b, and a third channel part322cdisposed between the first drain electrode structure24aand the second source electrode structure22b. The first to third channel parts322a,322band322cmay include second portions322a-2,322b-2and322c-2overlapping the first gate electrode layer pattern122a; fourth portions322a-4,322b-4and322c-4overlapping the second gate electrode layer pattern122b; sixth portions322a-6,322b-6and322c-6overlapping the third gate electrode layer pattern122c; and eighth portions322a-8,322b-8and322c-8overlapping the fourth gate electrode layer pattern122d. Similarly, the first to third channel parts322a,322band322cmay include first portions322a-1,322b-1and322c-1overlapping the first gate insulation layer pattern132a; third portions322a-3,322b-3and322c-3overlapping the second gate insulation layer pattern132b; fifth portions322a-5,322b-5and322c-5overlapping the third gate insulation layer pattern132c; and seventh portions322a-7,322b-7and322c-7overlapping the fourth gate insulation layer pattern132d; and ninth portions322a-9,322b-9and322c-9overlapping the fifth gate insulation layer pattern132e.

Meanwhile, in relation to a write operation for the fourth memory cell MC4inFIG. 6A, the fourth global word line GGL4is selected from the first to fourth global word lines GGL1, GGL2, GGL3and GGL4. A polarization switching voltage Vs having a magnitude equal to or greater than a predetermined threshold voltage may be applied to the fourth global word line GGL4, and the polarization switching voltage Vs may be applied to gate electrodes of the fourth memory cell MC4and the eighth memory cell MC8. The polarization switching voltage Vs is a voltage capable of switching the polarization of the fourth ferroelectric layer FD4of the fourth memory cell MC4and the eighth ferroelectric layer FD8of the eighth memory cell MC8. However, in order to perform the write operation only on the fourth memory cell MC4, the first global source line GSL1and the first global drain line GDL1may be grounded, and a predetermined voltage Vp having an absolute value smaller than an absolute value of the polarization switching voltage Vs may be separately applied to the second global source line GSL2and the second global drain line GDL2. In this manner, the polarization switching voltage Vs is only applied to the fourth ferroelectric layer FD4of the fourth memory cell MC4, and a voltage corresponding to a difference between the polarization switching voltage Vs and the predetermined voltage Vp may be applied to the eighth ferroelectric layer FD8of the eighth memory cell MC8. Accordingly, when the polarization switching voltage Vs is applied to the global gate line GGL4, the polarization of the fourth ferroelectric layer FD4of the fourth memory cell MC4is switched, and the polarization of the eighth ferroelectric layer FD8of the eighth memory cell MC8is not switched.

The write operation for storing the switched polarization in the form of remanent polarization in the fourth ferroelectric layer FD4is substantially the same as the write operation of the first ferroelectric layer312described above with reference toFIGS. 4A to 4Dand will not be repeated here, however through such a similar method, the write operation may be performed on the fourth memory cell MC4.

The above-described write operation for the fourth memory cell MC4can also be explained using the corresponding structures2and2ashown inFIGS. 5 and 6B. First, a polarization switching voltage Vs is applied to the fourth gate electrode layer pattern122dcorresponding to the fourth global word line GGL4. At this time, the first source electrode structure22aand the first drain electrode structure24arespectively corresponding to the first global source line GSL1and the first global drain line GDL1may be grounded. On the other hand, a predetermined voltage Vp having a magnitude smaller than the polarization switching voltage Vs may be applied to the second source electrode structure22band the second drain electrode structure24brespectively corresponding to the second global source line GSL2and the second global drain line GDL2. By doing so, polarization within a first region of the first ferroelectric layer312, positioned between the first source electrode structure22aand the first drain electrode structure24aalong the second direction, and in contact with the fourth gate electrode layer pattern122d, may be switched. Meanwhile, a voltage substantially smaller than the polarization switching voltage Vs is applied to a second region of the first ferroelectric layer312, positioned between the second source electrode structure22band the second drain electrode structure24balong the second direction while in contact with the fourth gate electrode layer pattern122d. Consequently, the polarization in this second region of the first ferroelectric layer312is not switched.

After the polarization switching voltage Vs is removed, the switched polarization may be stored in the form of remanent polarization. The first region of the first ferroelectric layer312with the switched polarization may be a region overlapping the eighth portion322a-8of the first channel part322aofFIG. 6C. The second region of the first ferroelectric layer312without a switched polarization may be a region overlapping the eighth portion322b-8of the second channel part322bofFIG. 6C.

Meanwhile, a read operation for remanent polarization stored in the fourth memory cell MC4will be explained. First, inFIG. 6A, the fourth global word line GGL4is selected. Subsequently, a read voltage Vr equal to or greater than a predetermined threshold voltage may be applied to the gate electrodes of the fourth memory cell MC4and the eighth memory cell MC8through the fourth global word line GGL4. An absolute value of the read voltage Vr may be smaller than an absolute value of the polarization switching voltage Vs. That is, polarization inside the fourth ferroelectric layer FD4and the eighth ferroelectric layer FD8may not be switched by the read voltage Vr. Transistors of the fourth memory cell MC4and the eighth memory cell MC8are turned on by the read voltage Vr, and conductive channels may be formed in the channel layers of the transistors. When a source-drain potential difference is formed between the first global source line GSL1and the first global drain line GDL1, a source-drain current may flow only through the conductive channel of the fourth memory cell MC4. The signal information of the remanent polarization stored in the fourth memory cell MC4can be read by measuring the magnitude of the source-drain current because the magnitude of the source-drain current changes according to the orientation of the remanent polarization stored in the fourth ferroelectric layer FD4of the fourth memory cell MC4. On the other hand, when a potential difference is not formed between the second global source line GSL2and the second global drain line GDL2, the operation current may not flow through the conductive channel of the eighth memory cell MC8.

The above-described read operation for the fourth memory cell MC4may also be explained in the same manner referring toFIGS. 5, 6B and 6C. First, the read voltage Vr is applied to the fourth gate electrode layer pattern122dcorresponding to the fourth global word line GGL4. A conductive channel CH100may be formed in the channel layer322overlapping the fourth gate electrode layer pattern122dby the read voltage Vr. Subsequently, a source-drain voltage is applied between the first source electrode structure22aand the first drain electrode structure24arespectively corresponding to the first global source line GSL1and the first global drain line GDL1to form a potential difference. The potential difference is not formed between the second global source line GSL2and the second global drain line GDL2. As a result, a source-drain current may flow only through the conductive channel CH100between the first source electrode structure22aand the first drain electrode structure24a. The read operation for the fourth memory cell MC4may be performed by measuring the source-drain current.

Through the above-described methods, it is possible to perform a write operation and a read operation through random access to the memory cells of the first operation unit2aof the nonvolatile memory device2ofFIGS. 5, 6B and 6C. The write operation and the read operation for the first operation unit2aof the nonvolatile memory device2ofFIGS. 5, 6B and 6Cmay be equally applied to the second operation unit2bof the nonvolatile memory device2.

FIG. 7is a perspective view schematically illustrating a nonvolatile memory device3according to another embodiment of the present disclosure.FIG. 8is a plan view of the nonvolatile memory device ofFIG. 7.FIG. 9is a cross-sectional view taken along a line D-D′ of the nonvolatile memory device ofFIG. 7.

Referring toFIGS. 7 to 9, a nonvolatile memory device3may further include first and second interfacial insulation layers332and334, as compared to the nonvolatile memory device1ofFIGS. 1 to 3.

The first interfacial insulation layer332may be disposed between a first ferroelectric layer312and a first channel layer322. One surface of the first interfacial insulation layer322may contact a first ferroelectric layer312and another surface of the first interfacial insulation layer332may contact the first channel layer322. In an embodiment, the first interfacial insulation layer332may be disposed on a plane formed substantially parallel to the first and second directions (i.e., a y-z plane parallel to the z-direction and y-direction). The first interfacial insulation layer332may have a predetermined thickness t3along a third direction (i.e., the x-direction). In an embodiment, the thickness t3of the first interfacial insulation layer332may be smaller than the thickness t1of the first ferroelectric layer312.

The first interfacial insulation layer332can prevent the first ferroelectric layer from directly contacting the first channel layer322. That is, the first interfacial insulation layer332can prevent defect sites such as oxygen vacancies from being generated at an interface between the first ferroelectric layer312and the first channel layer322. The first interfacial insulation layer332may have an amorphous structure. The first interfacial insulation layer332may have a lower dielectric constant than the first ferroelectric layer312. The first interfacial insulation layer332may be non-ferroelectric. The first interfacial insulation layer332may, for example, include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and the like.

The second interfacial insulation layer334may be disposed between a second ferroelectric layer314and a second channel layer324. One surface of the second interfacial insulation layer334may contact the second ferroelectric layer314and another surface of the second interfacial insulation layer334may contact the second channel layer324. The second interfacial insulation layer334can prevent the second ferroelectric layer314from directly contacting the second channel layer324.

The second interfacial insulation layer334may have substantially the same configuration as the first interfacial insulation layer332. The second interfacial insulation layer334may have a predetermined thickness t3along a third direction (i.e., the x-direction).

FIG. 10is a perspective view schematically illustrating a nonvolatile memory device4according to yet another embodiment of the present disclosure.FIG. 11is a plan view of the nonvolatile memory device ofFIG. 10.FIG. 12is a cross-sectional view taken along the line E-E′ of the nonvolatile memory device ofFIG. 10.

Referring toFIGS. 10 to 12, the nonvolatile memory device4may further include first and second floating electrode layers342and344, as compared to the nonvolatile memory device3ofFIGS. 7 to 9. The first and second floating electrode layers342and344may be formed of a conductive material.

The first floating electrode layer342may be disposed between a ferroelectric layer312and a first interfacial insulation layer332. One surface of the first floating electrode layer342may contact the first ferroelectric layer312and another surface of the first floating electrode layer342may contact the first interfacial insulation layer332. In an embodiment, the first floating electrode layer342may be disposed on a plane defined by first and second directions (i.e., the z-direction and y-direction). The first floating electrode layer342may have a predetermined thickness t4along a third direction (i.e., the x-direction).

The first floating electrode layer342may maintain an electrical floating state. As an example, the first floating electrode layer342is not electrically connected to first to fourth gate electrode layer patterns122a,122b,122cand122dand a first channel layer322of a first gate structure12. The first floating electrode layer342may charge positive charges or negative charges therein according to the polarity of the voltage applied to the first to fourth gate electrode layer patterns122a,122b,122cand122d. The charged positive charges or negative charges may function to stabilize the remanent polarization stored in the first ferroelectric layer312. Thus, the presence of the floating electrode layer improves the endurance and stability of the remanent polarization of the nonvolatile memory device4.

In addition, in an embodiment, a structure of a nonvolatile memory device includes the first ferroelectric layer312, having a relatively high dielectric constant, which is electrically connected in series to the first interfacial insulation layer332having a relatively low dielectric constant. When the polarization switching voltage or the read voltage is applied to the series connection structure, if the first floating electrode layer342is not present, a relatively high voltage may be applied to the first interfacial insulation layer332having a relatively low dielectric constant. Due to the thinness of the first ferroelectric layer312and the first interfacial insulation layer332, the first interfacial insulation layer332may be in effect electrically destroyed. Conversely, when the first floating electrode layer342is interposed between the first ferroelectric layer312and the first interfacial insulation layer332, the first floating electrode layer342can suppress the application of a relatively high voltage to the first interfacial insulation layer332thereby improving the endurance and reliability of the nonvolatile memory device4.

Likewise, the second floating electrode layer344may be disposed between the second ferroelectric layer314and the second interfacial insulation layer334. As an example, the second floating electrode layer344is not electrically connected to the first to fourth gate electrode layer patterns124a,124b,124cand124dof the second gate structure14and the second channel layer324. One surface of the second floating electrode layer344may contact the second ferroelectric layer314and another surface of the second floating electrode layer344may contact the second interfacial insulation layer334. In an embodiment, the second floating electrode layer344may be disposed on a plane formed substantially parallel to the first and second directions (i.e., a y-z plane parallel to the z-direction and y-direction). The second floating electrode layer344may have a predetermined thickness t4along the third direction (i.e., the x-direction). The configuration and function of the second floating electrode layer344may be substantially the same as the configuration and function of the first floating electrode layer342. That is, the second floating electrode layer344can improve the retention of the remanent polarization stored in the second ferroelectric layer314and the endurance of the second interfacial insulation layer334.

FIG. 13is a perspective view schematically illustrating a nonvolatile memory device5according to still yet another embodiment of the present disclosure.FIG. 14is a plan view of the nonvolatile memory device ofFIG. 13.FIG. 15is a cross-sectional view taken along a line F-F′ of the nonvolatile memory device ofFIG. 13.

Referring toFIGS. 13 to 15, the nonvolatile memory device5may further include third and fourth interfacial insulation layers352and354, as compared to the nonvolatile memory device3ofFIGS. 7 to 9.

The third interfacial insulation layer352may be disposed between a first gate structure12and a first ferroelectric layer312. As an example, one surface of the third interfacial insulation layer352may contact the first gate structure12and another surface of the third interfacial insulation layer352may contact the first ferroelectric layer312. In an embodiment, the third interfacial insulation layer352may be disposed on a plane formed substantially parallel to the first and second directions (i.e., a y-z plane parallel to the z-direction and y-direction). The third interfacial insulation layer352may have a predetermined thickness t5along the third direction (i.e., the x-direction). In an embodiment, the thickness t5of the third interfacial insulation layer352may be smaller than the thickness t1of the first ferroelectric layer312.

The third interfacial insulation layer352can prevent the first ferroelectric layer312from directly contacting the first gate structure12. The third interfacial insulation layer352can prevent defect sites from being generated at interfaces between the first ferroelectric layer312and the first to fourth gate electrode layer patterns122a,122b,122cand122dof the first gate structure12. The third interfacial insulation layer352may have an amorphous structure. The third interfacial insulation layer352may have a lower dielectric constant than the first ferroelectric layer312. The third interfacial insulation layer352may be non-ferroelectric. As an example, the third interfacial insulation layer352may have a paraelectric property. The third interfacial insulation layer352may, for example, include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and the like.

The third interfacial insulation layer352may be formed of substantially the same material as the first interfacial insulation layer332. The thickness t5of the third interfacial insulation layer352may be substantially the same as the thickness t3of the first interfacial insulation layer332.

Likewise, the fourth interfacial insulation layer354may be disposed between the second gate structure14and the second ferroelectric layer314. As an example, one surface of the fourth interfacial insulation layer354may contact the second gate structure14and another surface of the fourth interfacial insulation layer354may contact the second ferroelectric layer314. In an embodiment, the fourth interfacial insulation layer354may be disposed on a plane formed substantially parallel to the first and second directions (i.e., a y-z plane parallel to the z-direction and y-direction). The fourth interfacial insulation layer354may have a thickness t5along the third direction (i.e., the x-direction). In an embodiment, the thickness t5of the fourth interfacial insulation layer354may be smaller than the thickness t1of the second ferroelectric layer314.

The fourth interfacial insulation layer354can prevent the second ferroelectric layer314from directly contacting the second gate structure14. The fourth interfacial insulation layer354can prevent defect sites from being generated at interfaces between the second ferroelectric layer314and the first to fourth gate electrode patterns124a,124b,124cand124dof the second gate structure14. The fourth interfacial insulation layer354may have an amorphous structure. The fourth interfacial insulation layer354may have a lower dielectric constant than the second ferroelectric layer314. The fourth interfacial insulation layer354may be non-ferroelectric. As an example, the fourth interfacial insulation layer354may have a paraelectric property. The fourth interfacial insulation layer354may, for example, include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and the like.

The fourth interfacial insulation layer354may be formed of substantially the same material as the second interfacial insulation layer334. The thickness t5of the fourth interfacial insulation layer354may be substantially the same as the thickness t3of the second interfacial insulation layer334.

FIG. 16is a perspective view schematically illustrating a nonvolatile memory device6according to still yet another embodiment of the present disclosure.FIG. 17is a plan view of the nonvolatile memory device ofFIG. 16.FIG. 18is a cross-sectional view taken along a line G-G′ of the nonvolatile memory device ofFIG. 16.

Referring toFIGS. 16 to 18, the nonvolatile memory device6may be differentiated, as compared to the nonvolatile memory device3ofFIGS. 7 to 9, by configurations of first and second gate structures1012and1014.

In this embodiment, the first gate structure1012may include first to fourth gate electrode layer patterns1122a,1122b,1122cand1122dand first to fifth gate insulation layer patterns1132a,1132b,1132c,1132dand1132e, which are alternately stacked along a first direction (i.e., the z-direction). The second gate structure1014may include first to fourth gate electrode layer patterns1124a,1124b,1124cand1124dand first to fifth gate insulation layer patterns1134a,1134b,1134c,1134dand1134e, which are alternately stacked along the first direction (i.e., the z-direction).

Referring toFIGS. 16 and 18, the first to fifth gate insulation layer patterns1132a,1132b,1132c,1132dand1132eof the first gate structure1012may separate a first ferroelectric layer1312, a first interfacial insulation layer1332and a first channel layer1322with respect to the second and third direction (i.e., the y-direction and x-direction). Accordingly, the first ferroelectric layer1312, the first interfacial insulation layer1332and the first channel layer1322may be discontinuously disposed in the first direction. In comparison with an embodiment described above with reference toFIGS. 7 to 9, the first ferroelectric layer1312of this embodiment may be disposed to contact portions of one sidewall surface of the first gate structure1012, that is, only sidewall surfaces of the first to fourth gate electrode layer patterns1122a,1122b,1122cand1122d, in a lateral direction (i.e., the x-direction). In other words, the first ferroelectric layer1312does not contact the first to fifth gate insulation layer patterns1132a,1132b,1132c,1132dand1132ein the lateral direction (i.e., the x-direction). In addition, the first interfacial insulating layer1332and the first channel layer1322may be sequentially arranged in a lateral direction from the first ferroelectric layer1312, and between the first to fifth gate insulation layer patterns1132a,1132b,1132c,1132dand1132e.

Referring toFIGS. 16 and 18, in comparison with the first to fifth gate insulation layer patterns132a,132b,132c,132dand132eof an embodiment described above with reference toFIGS. 7 to 9, the first to fifth gate insulation layer patterns1132a,1132b,1132c,1132dand1132emay be disposed to directly contact a source electrode structure22, a drain electrode structure24and an insulation structure26. In this embodiment, the first to fifth gate insulation layer patterns1132a,1132b,1132c,1132dand1132ecan more effectively implement electrical insulation between the first to fourth gate electrode layer patterns1122a,1122b,1122cand1122din the first direction (i.e., the z-direction).

Likewise, referring toFIGS. 16 and 18, the first to fifth gate insulation layer patterns1134a,1134b,1134c,1134dand1134eof the second gate structure1014can separate a second ferroelectric layer1314, a second interfacial insulation layer1334, and a second channel layer1324from each other with respect to the second and third direction (i.e., the y-direction and x-direction). Accordingly, the second ferroelectric layer1314, the second interfacial insulation layer1334, and the second channel layer1324may be discontinuously disposed in the first direction (i.e., the z-direction). Accordingly, in comparison with an embodiment described above with reference toFIGS. 7 to 9, the second ferroelectric layer1314of this embodiment may be disposed to contact portions of one sidewall surface of the second gate structure1014, that is, only sidewall surfaces of the first to fourth gate electrode layer patterns1124a,1124b,1124cand1124d, in a lateral direction (i.e., the x-direction). In other words, the second ferroelectric layer1314does not contact the first to fifth gate insulation layer patterns1134a,1134b,1134c,1134dand1134ein the lateral direction (i.e., the x-direction).

Referring toFIGS. 16 and 18, in comparison with the first to fifth gate insulation layer patterns134a,134b,134c,134dand134eof an embodiment described above with reference toFIGS. 7 to 9, the first to fifth gate insulation layer patterns1134a,1134b,1134c,1134dand1134emay be disposed to directly contact the source electrode structure22, the drain electrode structure24and the insulation structure26. In this embodiment, the first to fifth gate insulation layer patterns1134a,1134b,1134c,1134dand1134ecan more effectively implement electrical insulation between the first to fourth gate electrode layer patterns1124a,1124b,1124cand1124din the first direction (i.e., the z-direction).

Meanwhile, the material properties and functions of the first to fourth gate electrode layer patterns1122a,1122b,1122c,1122d,1124a,1124b,1124cand1124dof the first and second gate structures1012and1014, the first and second ferroelectric layers1312and1314, the first and second interfacial insulation layers1332and1334, the first and second channel layers1322and1324, and the first to fifth gate insulation layer patterns1132a,1132b,1132c,1132d,1132e,1134a,1134b,1134c,1134dand1134eare substantially the same as the material properties and functions of the first to fourth gate electrode layer patterns122a,122b,122c,122d,124a,124b,124cand124dof the first and second gate structures12and14, the first and second ferroelectric layers312and314, the first and second interfacial insulation layers332and334, the first and second channel layers322and324, and the first to fifth gate insulation layer patterns132a,132b,132c,132d,1132e,134a,134b,1134c,134dand134e, respectively.

FIG. 19is a perspective view schematically illustrating a nonvolatile memory device7according to a further embodiment of the present disclosure.FIG. 20is a plan view of the nonvolatile memory device ofFIG. 19.FIG. 21is a cross-sectional view taken along a line H-H′ of the nonvolatile memory device ofFIG. 19.

Referring toFIGS. 19 to 21, a nonvolatile memory device7may be differentiated, as compared to the nonvolatile memory device4ofFIGS. 10 to 12, by configurations of first and second ferroelectric layer parts2312and2314, first and second floating electrode layer parts2342and2344, and first and second gate structures2012and2014.

The first gate structure2012may include first to fourth gate functional layer patterns2112a,2112b,2112cand2112dand first to fifth gate insulation layer patterns2132a,2132b,2132c,2132dand2132e, which are alternately stacked along a first direction (i.e., the z-direction) on the base insulation layer110. The first gate structure2012may extend in a second direction (i.e., the y-direction).

A first interfacial insulation layer332may be disposed on one sidewall surface S7of the first gate structure2012. That is, the first interfacial insulation layer332may be disposed to cover the one sidewall surface S7of the first gate structure2012. The one sidewall surface S7is a plane formed substantially parallel to the first and second directions (i.e., a y-z plane parallel to the z-direction and y-direction). In a specific embodiment, the first interfacial insulation layer332may be disposed to contact the first to fifth gate insulation layer patterns2132a,2132b,2132c,2132dand2132eand the first floating electrode layer part2342.

In addition, the first channel layer322may be disposed to contact the first interfacial insulation layer332. The first channel layer322may be disposed on a plane formed substantially parallel to the first and second directions (i.e., a y-z plane parallel to the z-direction and y-direction).

Referring toFIG. 21, the first to fourth gate functional layer patterns2112a,2112b,2112cand2112dof the first gate structure2012may each have a first floating electrode layer part2342, a first ferroelectric layer part2312, and a first gate electrode layer part2122. As an example, in the first gate functional layer pattern2112a, the first floating electrode layer part2342may be disposed on the first interfacial insulation layer332, and the first and second gate insulation layer patterns2132aand2132b. The first floating electrode layer part2342may have a predetermined thickness t6in the x-direction from the first interfacial insulation layer332, and in the z-direction from the first and second gate insulation layer patterns2132aand2132b. The first ferroelectric layer part2312may be disposed on the first floating electrode layer part2342, and the first and second gate insulation layer patterns2132aand2132b. The first ferroelectric layer part2312may have a predetermined thickness t7common to the first floating electrode layer part2342. The first gate electrode layer part2122may be disposed to contact or cover the first ferroelectric layer part2312between the first and second gate insulation layer patterns2132aand2132b.

With respect to the second gate functional layer pattern2112b, the first floating electrode layer part2342, the first ferroelectric layer part2312, and the first gate electrode layer part2122may be disposed between second and third gate insulation layer patterns2132band2312cand contact the first interfacial insulation layer332in substantially the same manner. As another example, with the third gate functional layer pattern2112c, the first floating electrode layer part2342, the first ferroelectric layer part2312, and the first gate electrode layer part2122may be disposed between the third and fourth gate insulation layer patterns2132cand2132dand contact the first interfacial insulation layer332in substantially the same manner. In the case of the fourth gate functional layer pattern2112d, the first floating electrode layer part2342, the first ferroelectric layer part2312, and the first gate electrode layer part2122may be disposed between the fourth and fifth gate insulation layer patterns2132dand2132eand the contact first interfacial insulation layer332in substantially the same manner.

Referring toFIGS. 19 to 21, a source electrode structure22, a drain electrode structure24and an insulation structure26may be disposed on the base insulation layer110to contact a first channel layer322. In addition, a second channel layer324may be disposed, on the base insulation layer110to contact one sidewall surface of each of the source electrode structure22, the drain electrode structure24and the insulation structure26. In addition, a second interfacial insulation layer334may be disposed to contact the second channel layer324.

On the base insulation layer110, the second gate structure2014may be disposed to contact the second interfacial insulation layer334. The second gate structure2014may include first to fourth gate functional layer patterns2114a,2114b,2114cand2114dand first to fifth gate insulation layer patterns2134a,2134b,2134c,2134dand2134e, which are alternately stacked on the base insulation layer110along the first direction (i.e., the z-direction). The second gate structure2014may extend in the second direction (i.e., the y-direction).

The first to fourth gate functional layer patterns2114a,2114b,2114cand2114dof the second gate structure2014may each have a second floating electrode layer part2344, a second ferroelectric layer part2314and a second gate electrode layer part2124. The configurations of the second floating electrode layer part2344, the second ferroelectric layer part2314and the second gate electrode layer part2124of the second gate structure2014may be substantially the same as the configurations of the first floating electrode layer part2342, the first ferroelectric layer part2312, and the first gate electrode layer part2122of the first gate structure2012.

When comparing the nonvolatile memory device7according to the above-described embodiment with the nonvolatile memory device4ofFIGS. 10 to 12, in the first to fourth gate functional layer patterns2112a,2112b,2112cand2112dof first gate structure2012and the first to fourth gate functional layer patterns2114a,2114b,2114cand2114dof second gate structure2014, the areas of the first and second ferroelectric layer parts2312and2314that respectively contact the first and second gate electrode layer parts2122and2124can be increased. In addition, the areas of the first and second floating electrode layer parts2342and2344contacting the first and second ferroelectric layer parts2312and2314can be increased. As a result, by increasing the areas of the first and second ferroelectric layer parts2312and2314functioning as memory layers, the density of the remanent polarization stored in the ferroelectric layer parts2313and2314can be increased. As a result, the reliability of the memory operation can be improved.

Meanwhile, the material properties and functions of the first and second gate electrode layer parts2122and2144, the first and second ferroelectric layer parts2312and2314, the first and second floating electrode layer parts2342and2344, the first to fifth gate insulations layer patterns2132a,2132b,2132c,2132d,2132e,2134a,2134b,2134c,2134dand2134eof the first and second gate structures2012and2014are substantially the same as the material properties and functions of the first to fourth gate electrode layer patterns122a,122b,122c,122d,124a,124b,124cand124dof the first and second gate structures12and14, the first and second ferroelectric layers312and314, the first and second floating electrode layers342and344, and the first to fifth gate insulation layer patterns132a,132b,132c,132d,132e,134a,134b,134c,134dand134eof the first and second gate structures12and14, respectively, of embodiments described above with reference toFIGS. 10 to 12.

FIG. 22is a perspective view schematically illustrating a nonvolatile memory device8according to a still further embodiment of the present disclosure.FIG. 23is a plan view of the nonvolatile memory device ofFIG. 22.FIG. 24is a cross-sectional view taken along a line I-I′ of the nonvolatile memory device ofFIG. 22.

Referring toFIGS. 22 to 24, a nonvolatile memory device8is differentiated, as compared to a nonvolatile memory device1ofFIGS. 1 to 3, in a configuration of a channel structure28.

In this embodiment, a channel structure28replaces an insulation structure26in the nonvolatile memory device1ofFIGS. 1 to 3. That is, the channel structure28may be disposed to contact a source electrode structure22and a drain electrode structure24in a second direction (i.e., the y-direction). Further, the channel structure28may be disposed to contact first and second ferroelectric layers312and314in a third direction (i.e., the x-direction). Accordingly, the first and second channel layers322and324of the nonvolatile memory device1ofFIGS. 1 to 3are omitted from the nonvolatile memory device8of this embodiment.

The channel structure28may have a pillar-like shape extending in a first direction (i.e., the z-direction) from a base insulation layer110. When a read voltage is applied to at least one of first to fourth gate electrode layer patterns122a,122b,122cand122dof a first gate structure12, a conductive channel may be formed in a region of the channel structure28, overlapping the at least one gate electrode layer pattern. Likewise, when the read voltage is applied to at least one of first to fourth gate electrode layer patterns124a,124b,124cand124dof a second gate structure14, a conductive channel may be formed in a region of the channel structure28, overlapping the at least one gate electrode layer pattern.

The channel structure28may, for example, include a doped semiconductor material or metal oxide. The semiconductor material may, for example, include silicon (Si), germanium (Ge), gallium arsenide (GaAs), and the like. The metal oxide may include indium-gallium-zinc (In-Ga—Zn) oxide. In an embodiment, the channel structure28may include silicon (Si) doped with an n-type dopant. Alternatively, the channel structure28may include c-axis aligned indium-gallium-zinc (In-Ga—Zn) oxide. The channel structure28may have a single crystal structure or a polycrystalline structure.

As described above, the nonvolatile memory device8of the present embodiment may include a pillar-shaped channel structure28. The device structure and manufacturing process can be simplified by using the channel structure28, at the same location, instead of the insulating structure26of the nonvolatile memory device1ofFIGS. 1 to 3.

In other embodiments, in a nonvolatile memory device2ofFIG. 5, a nonvolatile memory device in which the insulation structures26aand26bare replaced with channel structures28of the present embodiment may be implemented, while omitting the first and second channel layers322and324. Likewise, in a nonvolatile memory device3ofFIGS. 7 to 9, a nonvolatile memory device4ofFIGS. 10 to 12, a nonvolatile memory device5ofFIGS. 13 to 15, and a nonvolatile memory device7ofFIGS. 19 to 21, nonvolatile memory devices in which the insulating structures26are replaced with channel structures28of the present embodiment can be implemented. In such embodiments, the first and second channel layers322and324may be omitted. In addition, in a nonvolatile memory device6ofFIGS. 16 to 18, a nonvolatile memory device in which an insulating structure26is replaced with a channel structure28of the present embodiment may be implemented, while omitting the first and second channel layers1322and1324of the nonvolatile memory device6ofFIGS. 16 to 18.

The embodiments of the inventive concept have been disclosed above for illustrative purposes. Those of ordinary skill in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the inventive concept as disclosed in the accompanying claims.