Gate Structure Fabrication Techniques for Reducing Gate Structure Warpage

Gate fabrication techniques are disclosed herein for providing gate stacks and/or gate structures (e.g., high-k/metal gates) with improved profiles (e.g., minimal to no warping, bending, bowing, and necking and/or substantially vertical sidewalls), which may be implemented in various device types. For example, gate fabrication techniques disclosed herein provide gate stacks with stress-treated glue layers having a residual stress that is less than about 1.0 gigapascals (GPa) (e.g., about -2.5 GPa to about 0.8 GPa). In some embodiments, a stress-treated glue layer is provided by depositing a glue layer over a work function layer and performing a stress reduction treatment, such as an ion implantation process and/or an annealing process in a gas ambient, on the glue layer. In some embodiments, a stress-treated glue layer is provided by forming at least one glue sublayer/metal layer pair over a work function layer, performing a poisoning process, and forming a glue sublayer over the pair.

BACKGROUND

Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. For example, gate replacement processes, which typically involve replacing polysilicon gate electrodes with metal gate electrodes, have been implemented to improve device performance, where work function values of the metal gate electrodes are tuned during the gate replacement process to provide devices having different threshold (operating) voltages. Although existing gate fabrication techniques and/or gate replacement processes have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects as IC technologies and/or IC feature dimensions shrink.

DETAILED DESCRIPTION

The present disclosure relates generally to gate stacks of electronic devices, and more particularly, to gate stacks (e.g., high-k/metal gates) having improved profiles (e.g., minimal to no bowing and/or necking) and methods of fabricating such gate stacks.

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, spatially relative terms, for example, “lower,” “upper,” “horizontal,” “vertical,” “above,” “over,” “below,” “beneath,” “up,” “down,” “top,” “bottom,” etc. as well as derivatives thereof (e.g., “horizontally,” “downwardly,” “upwardly,” etc.) are used for ease of the present disclosure of one features relationship to another feature. The spatially relative terms are intended to cover different orientations of the device including the features. The present disclosure may also repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, when a number or a range of numbers is described with “about,” “approximate,” and the like, the term is intended to encompass numbers that are within a reasonable range considering variations that inherently arise during manufacturing as understood by one of ordinary skill in the art. For example, the number or range of numbers encompasses a reasonable range including the number described, such as within +/−10% of the number described, based on known manufacturing tolerances associated with manufacturing a feature having a characteristic associated with the number. For example, a material layer having a thickness of “about 5 nm” can encompass a dimension range from 4.5 nm to 5.5 nm where manufacturing tolerances associated with depositing the material layer are known to be +/−10% by one of ordinary skill in the art. Furthermore, given the variances inherent in any manufacturing process, when device features are described as having “substantial” properties and/or characteristics, such term is intended to capture properties and/or characteristics that are within tolerances of manufacturing processes. For example, “substantially vertical” or “substantially horizontal” features are intended to capture features that are approximately vertical and horizontal within given tolerances of the manufacturing processes used to fabricate such features—but not mathematically or perfectly vertical and horizontal.

For advanced IC technology nodes, non-planar transistors, such as fin-like field effect transistors (FinFETs) and gate-all-around (GAA) transistors (collectively referred to as multigate devices), have become a popular and promising candidate for high performance and low leakage applications.FIG.1is a fragmentary perspective view of an exemplary multigate device10, in portion or entirety, according to various aspects of the present disclosure. Multigate device10is a FinFET that includes a fin15extending from a substrate20. Fin15has a length along a y-direction, a width along an x-direction (Wfin), and a height along a z-direction. InFIG.1, fin15has a non-recessed portion disposed between recessed portions, and the FinFET further includes a gate stack25that wraps and engages the non-recessed portion of fin15(e.g., gate stack25is disposed on a top and opposing sidewalls of the non-recessed portion of fin15) and epitaxial source/drains30disposed over the recessed portions of fin15(e.g., epitaxial source/drains30are disposed on tops of the recessed portions of fin15). The FinFET has a channel region (C) disposed between source/drain regions (S/D), where the channel region is provided by the non-recessed portion of fin15and the source/drain regions are provided by epitaxial source/drains30and underlying recessed portions of fin15. During operation of the FinFET, current can flow through the channel region (e.g., non-recessed portion of fin15) and between the source/drain regions (e.g., epitaxial source/drains30). Gate stack25has a gate length (LG) along the y-direction, and in the depicted embodiment, gate stack25includes a gate dielectric25A and a gate electrode25B. Gate spacers (not shown inFIG.1) are disposed along sidewalls of gate stack25, and the gate spacers also wrap the non-recessed portion of fin15. A substrate isolation feature40, such as shallow trench isolation (STI) structure, electrically isolates the FinFET from other devices and/or regions of multigate device10. Substate isolation feature40is disposed over substrate20, along sidewalls of the recessed portions of fin15, and along sidewalls of lower portions of the non-recessed portion of fin15. Gate stack25extends over the top of substrate isolation feature40. In some embodiments, substrate isolation feature40surrounds a lower portion of fin15. In some embodiments, fin15is not recessed in the source/drain regions of the FinFET, and epitaxial source/drains30wrap fin15(e.g., epitaxial source/drains30are disposed on tops and opposing sidewalls of fin15).FIG.1has been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Additional features can be added in multigate device10, and some of the features described below can be replaced, modified, or eliminated in other embodiments of multigate device10.

Gate stack25may be formed by a gate replacement process, which typically involves removing a dummy gate (e.g., a polysilicon gate) of a gate structure to form a gate opening (having, for example, sidewalls formed by gate spacers of the gate structure) and forming gate stack25in the gate opening. As IC feature sizes continue to shrink with advanced IC technology nodes, dimensions of the FinFET, such as fin width Wfinand gate length LG, are correspondingly decreasing, which has led to a significantly smaller gate opening during the gate replacement process. Gate replacement processes having smaller gate openings are more susceptible to forming voids and/or seams in gate stack25. In particular, it has been observed that the gate replacement process is especially sensitive to residual stress in various layers of gate stack25as FinFET dimensions, and thus dimensions of gate openings, shrink. For example, residual stress in a glue layer of gate stack25has been observed to deform and/or warp gate stack25during the gate replacement process and prevent complete filling of the gate opening, which has led to undesired voids and/or seams forming in gate stack25. Such voids and/or seams provide a path for chemicals and/or other impurities to reach and damage channel region C during subsequent processing, thereby significantly degrading performance and/or reliability of the FinFET.

The present disclosure addresses such challenges by providing gate stacks with stress-treated glue layers, which are formed between work function layers of the gate stacks and metal fill layers of the gate stacks. The stress reduction treatment is configured to modify properties and/or characteristics of the glue layer, such that the glue layer has a compressive residual stress or a negligible tensile residual stress (i.e., a residual stress that is less than about 0.8 GPa). Various stress reduction treatments disclosed herein have been observed to reduce residual stress and/or other characteristics (e.g., d-spacing) in a glue layer, reduce warping of a gate structure that includes the glue layer (e.g., a gate stack and/or the gate spacers), and significantly reduce (and even eliminate) void and/or seam formation in a gate stack that includes the glue layer. Various characteristics of a gate structure and/or a glue layer thereof that result from implementing the proposed stress reduction treatments, and corresponding gate replacement processes are disclosed herein. Details of the proposed stress reduction techniques and/or gate fabrication techniques are described herein in the following pages.

FIG.2is a flow chart of a method50for fabricating a device having a gate structure with an improved profile (e.g., minimal to no warping, bending, bowing, and necking and/or substantially vertical sidewalls) according to various aspects of the present disclosure. At block52, method50includes forming a gate dielectric layer over a channel region. At block54, method50includes forming a work function layer over the gate dielectric layer. At block56, method50includes forming a stress-treated glue layer over the work function layer. In some embodiments, the stress-treated glue layer is formed by depositing a glue layer over the work function layer and performing a stress reduction treatment on the glue layer (e.g., an ion implantation process and/or a thermal process). In some embodiments, the stress-treated glue layer is formed by depositing glue sublayers, depositing metal layers between the glue sublayers, and performing a hydrogen poisoning process (or other suitable poisoning process) on the glue sublayers and/or the metal layers. At block58, method50includes forming a metal fill layer over the stress-treated glue layer. In some embodiments, method50is implemented in a gate last process (i.e., a gate replacement process). In such embodiments, a dummy gate (e.g., a polysilicon gate) is removed to form a gate opening, which is defined between gate spacers of the gate structure, and the gate dielectric layer, the work function layer, the stress-treated glue layer, and the metal fill layer are formed in and fill the gate opening. A planarization process may be performed that removes excess gate materials from over a top of a dielectric layer (e.g., an interlevel dielectric (ILD) layer), where a remainder of the gate materials fill the gate opening and form the gate stack of the gate structure, which includes the gate dielectric layer, the work function layer, the stress-treated glue layer, and the metal fill layer. In some embodiments, method50is implemented in a gate first process. In such embodiments, the gate dielectric layer, the work function layer, the stress-treated glue layer, and the metal fill layer are formed over a substrate that includes the channel region and then subsequently patterned to form the gate stack of the gate structure, which includes the gate dielectric layer, the work function layer, the stress-treated glue layer, and the metal fill layer. A dielectric layer (e.g., ILD layer) may be formed after patterning the various gate layers to form the gate stack. In some embodiments, method50is implemented in a hybrid gate first-gate last process. Additional steps can be provided before, during, and after method50, and some of the steps described can be moved, replaced, or eliminated for additional embodiments of method50.

FIGS.3A-3Iare fragmentary cross-sectional views of a device100, in portion or entirety, at various fabrication stages (such as those associated with method50inFIG.2) according to various aspects of the present disclosure. The cross-sectional views ofFIGS.3A-3Iare obtained by “cutting” a device along the y-direction shown inFIG.1, and thus, the cross-sectional views inFIGS.3A-3Imay be referred to as y-cut views. It is noted that the y-cut views are taken through a portion of the device that includes a channel region disposed between source/drain regions and where a gate structure is disposed over a top of the channel region, instead of a portion of the device where the gate structure wraps the channel region (i.e., the y-cut views are through the Y-Z plane instead of the X-Z plane of a multigate device). Device100may be included in a microprocessor, a memory, and/or IC. Device100may be a portion of an IC chip, a system on chip (SoC), or portion thereof, that includes various passive and active microelectronic devices, such as transistors, resistors, capacitors, inductors, diodes, p-type FETs (PFETs), n-type FETs (NFETs), metal-oxide semiconductor FETs (MOSFETs), complementary metal-oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, other suitable components and/or devices, or combinations thereof.FIGS.3A-3Ihave been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Additional features can be added in device100, and some of the features described below can be replaced, modified, or eliminated in other embodiments of device100.

Turning toFIG.3A, device100includes a substrate (wafer)105. Substrate105includes an elementary semiconductor, such as silicon and/or germanium; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or combinations thereof; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, GaInAsP, or combinations thereof; or combinations thereof. In the depicted embodiment, substrate105is a silicon substrate. In some embodiments, substrate105is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. Substrate105can include various doped regions, such as p-type doped regions (e.g., p-wells), n-type doped regions (e.g., n-wells), or combinations thereof. N-type doped regions include n-type dopants, such as phosphorus, arsenic, other n-type dopant, or combinations thereof. P-type doped regions include p-type dopants, such as boron, indium, other p-type dopant, or combinations thereof. In some embodiments, the doped regions include a combination of p-type dopants and n-type dopants. The doped regions can be formed directly on and/or in substrate105, for example, providing a p-well structure, an n-well structure, a dual-well structure, a raised structure, other suitable structure, or combinations thereof.

Device100includes a channel region110disposed between epitaxial source/drains120, and a gate structure125disposed over channel region110. Channel region110(also referred to as a channel layer) extends lengthwise along the y-direction, having a length along the y-direction, a width along the x-direction, and a height along the z-direction. Channel region110includes an elementary semiconductor, such as silicon and/or germanium; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or combinations thereof; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, GaInAsP, or combinations thereof; or combinations thereof. In the depicted embodiment, channel region110includes silicon, germanium, silicon germanium, other suitable semiconductor material, or combinations thereof. When device100is a FinFET, such as in the depicted embodiment, channel region110is a portion of a semiconductor fin extending from substrate105and can be referred to as a fin or a fin structure. In some embodiments, channel region110is a portion of substrate105, such as a portion of a material layer of substrate105. For example, where substrate105includes silicon, channel region110includes silicon (i.e., channel region110is a silicon fin). In some embodiments, channel region110is a semiconductor layer extending from substrate105(e.g., channel region110is a silicon germanium fin). When device100is a GAA transistor, channel region110may be a semiconductor layer stack (e.g., silicon germanium layers and silicon layers stacked along the z-direction in an interleaving, alternating configuration over substrate105) that is subsequently processed to form one or more semiconductor layers suspended over substrate105(e.g., silicon nanowire(s), which will be at least partially surrounded by a gate).

Epitaxial source/drains120include a semiconductor material and may be doped with n-type dopants and/or p-type dopants. In embodiments where device100is an n-type transistor, epitaxial source/drains120can include silicon doped with carbon, phosphorous, arsenic, other n-type dopant, or combinations thereof (for example, Si:C epitaxial source/drains, Si:P epitaxial source/drains, or Si:C:P epitaxial source/drains). In embodiments where device100is a p-type transistor, epitaxial source/drains120can include silicon germanium or germanium doped with boron, other p-type dopant, or combinations thereof (for example, Si:Ge:B epitaxial source/drains). In some embodiments, epitaxial source/drains120include more than one epitaxial semiconductor layer, where the epitaxial semiconductor layers can include the same or different materials and/or the same or different dopant concentrations. In some embodiments, epitaxial source/drains120include materials and/or dopants that achieve desired tensile stress and/or compressive stress in channel region110. In some embodiments, doped regions, such as heavily doped source/drain (HDD) regions, lightly doped source/drain (LDD) regions, other doped regions, or combinations thereof, are disposed in epitaxial source/drains120. In such embodiments, doped regions (e.g., LDD regions) may extend into channel region110. As used herein, source/drain region and/or epitaxial source/drain may refer to a source of device100, a drain of device100, or a source and/or a drain of multiple devices (including device100).

Gate structure125includes a dummy gate130disposed over a channel region of device100(e.g., channel region110) and between source/drain regions of device100(e.g., epitaxial source/drains120). Dummy gate130extends lengthwise in a direction that is different than (e.g., orthogonal to) the lengthwise direction of channel region110. For example, dummy gate130extends lengthwise along the x-direction, having a length along the x-direction, a width along the y-direction, and a height along the z-direction. In the Y-Z plane (FIG.3A), dummy gate130is disposed on a top of channel region110. A width of dummy gate130along the y-direction defines a critical dimension (CD) of gate structure125, which is a desired gate length (LG) of a gate stack of gate structure125. In some embodiments, critical dimension CD is about 14 nm to about 20 nm. In the X-Z plane, when channel region110is formed in a portion of a semiconductor fin extending from substrate105such as depicted, dummy gate130is disposed over a top and sidewalls of channel region110, such that dummy gate130wraps channel region110. In some embodiments, dummy gate130includes a dummy gate electrode and a hard mask over the dummy gate electrode. The dummy gate electrode includes a suitable dummy gate material, and the hard mask includes a suitable hard mask material. For example, the dummy gate electrode includes a polysilicon layer, and the hard mask includes a silicon nitride layer. In such embodiments, dummy gate130may be referred to as a poly gate. Dummy gate130can include other layers, such as capping layers, interface layers, diffusion layers, barrier layers, or combinations thereof. In some embodiments, dummy gate130includes a dielectric layer between the dummy gate electrode and channel region110, such as a dummy gate dielectric and/or an interfacial layer (including, for example, silicon oxide).

Gate structure125also includes gate spacers135disposed adjacent to (for example, along sidewalls of) dummy gate130. Gate spacers135include a dielectric material, which can include silicon, oxygen, carbon, nitrogen, other suitable material, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, silicon oxycarbide, silicon oxycarbonitride, or combinations thereof). In some embodiments, gate spacers135include a multi-layer structure, such as a first dielectric layer (e.g., a silicon oxide layer) and a second dielectric layer (e.g., a silicon nitride layer). In some embodiments, gate spacers135include more than one set of spacers, such as seal spacers, offset spacers, sacrificial spacers, dummy spacers, main spacers, or combinations thereof. In such embodiments, the different spacers can include different materials having different etch rates.

Dielectric layer140is disposed over substrate105, channel region110, epitaxial source/drains120, and gate structure125. Dielectric layer140may be a portion of a multilayer interconnect (MLI) feature that electrically couples various devices (for example, transistors, resistors, capacitors, and/or inductors) and/or components (for example, gate stacks and/or source/drains) of device100, such that the various devices and/or components can operate as needed. Dielectric layer140can have a multi-layer structure, such as an interlayer dielectric (ILD) layer over a contact etch stop layer (CESL). The ILD layer includes a dielectric material including, for example, silicon oxide, carbon doped silicon oxide, silicon nitride, silicon oxynitride, tetraethyl orthosilicate (TEOS)-formed oxide, boron silicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), Black Diamond® (Applied Materials of Santa Clara, Calif.), xerogel, aerogel, amorphous fluorinated carbon, parylene, benzocyclobutene-based (BCB) dielectric material, SiLK (Dow Chemical, Midland, Mich.), polyimide, other suitable dielectric material, or combinations thereof. In some embodiments, the ILD layer includes a dielectric material having a dielectric constant that is less than a dielectric constant of silicon dioxide (e.g., k<3.9). In some embodiments, the ILD layer includes a dielectric material having a dielectric constant that is less than about 2.5 (i.e., an extreme low-k (ELK) dielectric material), such as porous silicon oxide, silicon carbide (SiC), and/or carbon-doped oxide (for example, an SiCOH-based material (having, for example, Si—CH3bonds)), each of which is tuned/configured to exhibit a dielectric constant less than about 2.5. The CESL includes a dielectric material that is different than the dielectric material of the ILD layer. For example, where the ILD layer includes a low-k dielectric material (e.g., porous silicon oxide), the CESL can include silicon and nitrogen, such as silicon nitride, silicon carbonitride, or silicon oxycarbonitride.

Turning toFIGS.3B-31, processing continues with performing a gate replacement process, for example, by removing dummy gate130from gate structure125to form a gate opening145that exposes channel region110(FIG.3B) and filling gate opening145with a gate stack150(FIGS.3C-3I) (i.e., dummy gate130is replaced with gate stack150). InFIG.3B, gate opening145has sidewalls formed by gate spacers135and a bottom formed by channel region110. A width of gate opening145along the lengthwise direction of the channel (e.g., the y-direction) is about equal to critical dimension CD. In the depicted embodiment, gate spacers135have substantially vertical sidewalls that extend along the z-direction, which provide gate opening145with a width that is substantially uniform from top to bottom. In other words, critical dimension CD is substantially the same from a top of gate opening145that is proximate to a top surface of dielectric layer140to a bottom of gate opening145that is proximate to a top surface of channel region110. In some embodiments, an etching process selectively removes dummy gate130with respect to gate spacers135and/or dielectric layer140. For example, the etching process substantially removes dummy gate130but does not remove, or does not substantially remove, gate spacers135and/or dielectric layer140. In some embodiments, an etchant is selected for the etching process that etches polysilicon (i.e., dummy gate130) at a higher rate than dielectric materials (i.e., gate spacers135and/or dielectric layer140) (i.e., the etchant has a high etch selectivity with respect to polysilicon). The etching process is a dry etch, a wet etch, other suitable etching process, or combinations thereof. The etching process may also be tuned to remove dummy gate130without (or minimally) removing channel region110. In some embodiments, the etching process uses a patterned mask layer (i.e., an etch mask) that covers dielectric layer140and/or gate spacers135but exposes dummy gate130.

InFIG.3C, a gate dielectric layer152is formed over substrate105. Gate dielectric layer152has a substantially uniform thickness and partially fills gate opening145. Gate dielectric layer152is disposed on gate spacers135(which form the sidewalls of gate opening145), channel region110(which forms the bottom of gate opening145), and dielectric layer140. In some embodiments, gate dielectric layer152has a thickness of about10A to about200A. Gate dielectric layer152includes a high-k dielectric material, such as HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfSiO, HfZrO, HfAlOx, ZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, LaO3, La2O3, Ta2O3, Ta2O5, Y2O3, SrTiO3, Ba7rO, BaTiO3(BTO), (Ba,Sr)TiO3(BST), Si3N4, HfO2-Al2O3, other suitable high-k dielectric material, or combinations thereof. High-k dielectric material generally refers to dielectric materials having a high dielectric constant, for example, greater than that of silicon dioxide (k≈3.9). In some embodiments, gate dielectric layer152includes another suitable dielectric material, such as SiO2or other suitable dielectric material. Gate dielectric layer152can have a multilayer structure. Gate dielectric layer152is formed by atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), high density plasma CVD (HDPCVD), metal organic CVD (MOCVD), remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), low-pressure CVD (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), thermal oxidation, chemical oxidation, other suitable methods, or combinations thereof.

An interfacial layer152A may be formed between channel region110and gate dielectric layer152. Interfacial layer152A includes a dielectric material, such as SiO2, SiGeOx, HfSiO, SiON, other silicon-comprising dielectric material, other suitable material, or combinations thereof. Interfacial layer152A is formed by thermal oxidation, chemical oxidation, ALD, CVD, other suitable process (such as those described herein), or combinations thereof. A thickness of interfacial layer152A is less than a thickness of gate dielectric layer152. In some embodiments, a thickness of interfacial layer152A is about5A to about50A.

InFIG.3D, a metal gate layer154is formed over substrate105. Metal gate layer154has a substantially uniform thickness and partially fills gate opening145. Metal gate layer154is disposed on gate dielectric layer152. In some embodiments, a thickness of metal gate layer154is about20A to about800A. Metal gate layer154is formed by ALD, PVD, CVD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, plating, other suitable methods, or combinations thereof. In the depicted embodiment, metal gate layer154has a multilayer structure, such as a metal layer154A, a metal layer154B, a metal layer154C, and a metal layer154D from bottom to top. Metal layer154A physically contacts gate dielectric layer152, metal layer154B physically contacts metal layer154A, metal layer154C physically contacts metal layer154B, and metal layer154D physically contacts metal layer154C. A thickness of metal layer154B may be greater than each of a thickness of metal layer154A, a thickness of metal layer154B, and a thickness of metal layer154D. In some embodiments, a thickness of each of metal layer154A, metal layer154C, and metal layer154D is about 10 Å to about 200 Å. In some embodiments, a thickness of metal layer154B is about 10 Å to about 500 Å. In some embodiments, a thickness of metal layer154D is about 10 Å to about 20 Å (e.g., 14 Å).

In some embodiments, metal layer154B is a work function layer, and metal layer154A, metal layer154B, and metal layer154D are capping (cap) layers, blocking layers, barrier layers, or combinations thereof. For example, metal layer154A, metal layer154B, and metal layer154D each include a material that prevents or eliminates diffusion and/or reaction of constituents between adjacent layers and/or promotes adhesion between adjacent layers, such as between gate dielectric layer152and metal layer154B or between metal layer154B and a subsequently formed metal fill layer. In some embodiments, metal layer154A, metal layer154C, metal layer154D, or combinations thereof each include metal and nitrogen, such as titanium nitride, tantalum nitride, tungsten nitride (e.g., W2N), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), other suitable metal nitride, or combinations thereof. In some embodiments, metal layer154A, metal layer154B, metal layer154D, or combinations thereof include an amorphous material, such as amorphous silicon, amorphous carbon, amorphous germanium, other amorphous material, or combinations thereof. In the depicted embodiment, metal layer154A and metal layer154C are metal nitride layers (e.g., titanium nitride (TiN) layers (e.g., TiN layers) or tantalum nitride (TaN) layers, and metal layer154D is an amorphous material layer (e.g., an amorphous silicon layer). The present disclosure contemplates any suitable materials for metal layer154A, metal layer154B, and metal layer154D.

Metal layer154B includes a metal material with a proper work function. In the depicted embodiment, metal layer154B includes an n-type work function metal (nWFM), which generally refers to a metal material or a metal-containing material with a work function value closer to a conduction band energy than a valence band energy of a material of channel region110. In some embodiments, metal layer154B is an nWFM layer that includes an aluminum-based material, such as titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), titanium silicon aluminum carbide (TiSiAlC), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), Al-doped Ti, Al-doped TiN, Al-doped Ta, Al-doped TaN, other suitable aluminum-based nWFM, or combinations thereof. For example, metal layer154B is a TiAlC layer. In another example, metal layer154B is a TiSiAlC layer. In yet another example, metal layer154B is a TaA1C layer. In some embodiments, metal layer154B includes a p-type work function metal (pWFM), which generally refers to a metal material or a metal-containing material with a work function value closer to a valence band energy than a conduction band energy of a material of channel region110. In some embodiments, metal layer154B is a pWFM layer that is substantially aluminum free, such as a titanium-based nitride (e.g., TiN and/or TiSiN), a tantalum-based nitride (e.g., TaN and/or TaSiN), a titanium-based alloy (including, for example, titanium and gold, copper, chromium, cobalt, molybdenum, nickel, other suitable constituent, or combinations thereof), a tantalum-based alloy (including, for example, tantalum and gold, copper, tungsten, platinum, tungsten, molybdenum, other suitable constituent, or combinations thereof), other aluminum-free pWFM, or combinations thereof. In some embodiments, nWFM has a work function value that is less than about 4.5 electron volts (eV), and pWFM has a work function value that is greater than or equal to about 4.5 eV. For example, nWFM has a work function value that is about 3.5 eV to about 4.4 eV, where such work function values are closer to a conduction band energy (e.g., 4.1 eV of Si or 3.8 eV of SiGe) of a semiconductor channel region than a valence band energy (e.g., 5.2 eV of Si or 4.8 eV of SiGe) of the semiconductor channel region, while pWFM has a work function value that is about 4.5 eV to about 5.5 eV, where such work function values are closer to the valence band energy of the semiconductor channel region than the conduction band energy of the semiconductor channel region. The present disclosure contemplates metal layer154B including any material that exhibits a desired work function. In some embodiments, metal layer154A and/or metal layer154C include a material that exhibits a desired work function. For example, metal layer154A and/or metal layer154C include pWFM. In some embodiments, materials of metal layer154A, metal layer154B, metal layer154C, and metal layer154D are configured to provide metal layer154with a desired work function, and metal layer154can be referred to as a work function layer.

InFIG.3E, a glue layer156is formed over substrate105. Glue layer156has a substantially uniform thickness, such as a thickness T, and partially fills gate opening145. Glue layer156is disposed on metal gate layer154, and in the depicted embodiment, physically contacts metal layer154D. In some embodiments, thickness T is about 20 Å to about 100 Å. Glue layer156includes a material that promotes adhesion between metal gate layer154(e.g., metal layer154D) and a metal fill layer158of gate stack150, which is subsequently formed and described below. In some embodiments, the material of glue layer156includes metal (for example, W, Al, Ta, Ti, Ni, Cu, Co, other suitable metal, or combinations thereof), metal oxides, metal nitrides, metal alloys, or combinations thereof. Glue layer156is formed by ALD, PVD, CVD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, plating, other suitable methods, or combinations thereof. In an example, glue layer156is a titanium nitride layer (e.g., a TiN layer) formed by ALD or CVD. In another example, glue layer156is a tantalum nitride layer (e.g., a TaN layer) formed by ALD or CVD. In yet another example, glue layer156is a cobalt layer (e.g., a Co layer) formed by ALD or CVD. In yet another example, glue layer156is a titanium silicon nitride layer (e.g., a TSN layer) formed by ALD or CVD. In some embodiments, the TSN layer may include alternatingly deposited TiN layers and silicon nitride layers (e.g., SiN layers), where the TiN layers and the SiN layers are so thin that the TiN layers and the SiN layers are indistinguishable and thus referred to as a TSN layer.

Glue layer156has residual tensile stress that causes glue layer156to warp, bend, neck, and/or bow as depicted, which correspondingly warps metal gate layer154, gate dielectric layer152, gate spacers135, other layers of gate structure125, or combinations thereof. For example, glue layer156, as deposited, has a residual stress of about 1.0 Gigapascals (GPa) to about 3.0 GPa (i.e., a large residual tensile stress), which alters a profile of gate structure125and critical dimension of gate structure125. InFIG.3E, a line A and a line A′ represent substantially vertical sidewalls of gate stack150(which interface with gate spacers135) before forming glue layer156and having critical dimension CD defined therebetween. The residual tensile stress in glue layer156causes necking in a top portion of gate structure125, which decreases its critical dimension, and bowing in a middle portion and/or a bottom portion of gate structure125, which increases its critical dimension. For example, sidewalls of the top portion of gate structure125curve/bend inward and narrow gate opening145(i.e., a distance between sidewalls of gate stack150decreases, thereby decreasing a width of gate opening145), and the sidewalls of the middle portion and/or the bottom portion of gate structure125curve/bend outward and widen gate opening145(i.e., a distance between sidewalls of gate stack150increases, thereby increasing the width of gate opening145). In such embodiment, in response to the residual tensile stress of glue layer156, sidewalls of gate stack150are curvilinear and have outwardly curving portions (i.e., those that curve/bend away from gate opening145) and inwardly curving portions (i.e., those that curve/bend to gate opening145). In some embodiments, gate structure125has a convex cross-sectional profile (i.e., a portion having a middle and ends, where a width of the middle is greater than widths of the ends).

In such embodiments, gate stack150has a non-uniform critical dimension. For example, gate stack150has a necking critical dimension CDNthat that is less than critical dimension CD and a bowing critical dimension CDBthat is greater than critical dimension CD. As deposited, glue layer156has been observed to cause necking critical dimensions CDNin gate stack150that are about 85% to about 90% less than critical dimension CD and bowing critical dimensions CDBin gate stack150that are about 30% to about 35% greater than critical dimension CD. In some embodiments, necking critical dimension CDNis about 20 Å to about 35 Å less than critical dimension CD. In some embodiments, bowing critical dimension CDBis about 20 Å to about 35 Å greater than critical dimension CD. Necking portions of gate stack150have a necking angle θ with respect to line A or line A′ (i.e., an axis along the z-direction that represents a substantially vertical sidewall of gate stack150and/or gate structure125before depositing glue layer156) and bowing portions of gate stack150have a bowing angle φ with respect to line A or line A′. As deposited, glue layer156has been observed to cause necking angles θ that are greater than about 5° and bowing angles φ that are greater than about 5°. In some embodiments, each layer of gate structure125(e.g., gate dielectric152, metal gate layer154, glue layer156, gate spacers135, or combinations thereof) can have necking portions (segments) with respective necking angles and/or bowing portions (segments) with respective bowing angles. As IC devices scale and device dimensions shrink, the warpage of gate structure125and/or gate stack150caused by stressed glue layer156and resulting critical dimension variances can significantly narrow gate opening145and prevent subsequently formed metal fill layer158from completely filling gate opening145. This can lead to formation of seams and/or voids in gate stack150that can significantly degrade device performance and/or device integrity. For example, voids or seams in gate stack150may result in device100having performance characteristics that are different than prescribed by design specifications. In some embodiments, voids or seams in gate stack150may result in device100having performance characteristics that are unacceptable, which can lead to discarding of device100.

FIG.4A,FIG.4B, andFIG.5illustrate seams and/or voids that may arise when a narrower width of gate opening145caused by warping, bending, necking, and/or bowing of gate structure125results in metal fill layer158plugging gate opening145.FIG.4Ais a fragmentary cross-sectional view of device100, in portion or entirety, after depositing metal fill layer158,FIG.4Bis a fragmentary cross-sectional view of device100, in portion or entirety, after a planarization process, andFIG.5is a top view of device100that corresponds withFIG.4Baccording to various aspects of the present disclosure.FIG.4Bis taken along B—B ofFIG.5. InFIG.4A, metal fill layer158fills a top of gate opening145before reaching and/or filling a middle and/or a bottom of gate opening145, and a void160A is formed in gate structure125between glue layer156and metal fill layer158. InFIG.4BandFIG.5, the planarization process removes excess gate material from over a top surface of dielectric layer140to form gate stack150. The planarization process also reduces a thickness of dielectric layer140and a height of gate structure125along the z-direction. In such embodiments, the planarization process may remove metal fill layer158and reach void160A, thereby forming a seam160A′ in gate stack150that exposes glue layer156. Seam160A′ is an unfilled portion of gate opening145and forms a gap or opening in gate stack150. Seam160A′ has a width WA along the y-direction. In some embodiments, width WA is about20A to about110A.

FIG.6A,FIG.6B, andFIG.7illustrate seams and/or voids that may arise when a narrower width of gate opening145caused by warping, bending, necking, and/or bowing of gate structure125results in pinching off of metal fill layer158in gate opening145.FIG.6Ais a fragmentary cross-sectional view of device100, in portion or entirety, after depositing metal fill layer158,FIG.6Bis a fragmentary cross-sectional view of device100, in portion or entirety, after a planarization process, andFIG.7is a top view of device100that corresponds withFIG.6Baccording to various aspects of the present disclosure.FIG.6Bis taken along B—B ofFIG.7. InFIG.6A, metal fill layer158fills or closes (pinches) off a top of gate opening145before completely filling gate opening145, and a void160B is formed in gate structure125. Void160B is an unfilled portion of gate opening145that is within metal fill layer158. InFIG.6BandFIG.7, the planarization process removes excess gate material from over a top surface of dielectric layer140to form gate stack150. The planarization process also reduces a thickness of dielectric layer140and a height of gate structure125along the z-direction. In such embodiments, the planarization process may remove metal fill layer158and reach void160B, thereby forming a seam160B′ in gate stack150. Seam160B′ is an unfilled portion of gate opening145and forms a gap or opening in gate stack150. Seam160B′ has a width WBalong the y-direction. In some embodiments, width WBis about 20 Å to about 110 Å. In the depicted embodiment, width WBof seam160B′ (between sidewall portions of metal fill layer158) is less than width WAof seam160A′ (between sidewall portions of glue layer156).

As device100undergoes further processing, seam160A′ and/or seam160B′ have been observed to provide paths for chemicals and/or impurities to damage gate stack150and/or channel region110. For example, chemicals and/or impurities entering seam160A′ and/or seam160B′ during subsequent processing may alter physical and/or electrical characteristics of metal fill layer158, glue layer156, metal gate layer154, gate dielectric layer152, interfacial layer152A, or combinations thereof. In another example, during a subsequent etching process, etchant may enter seam160A′ and/or seam160B′ and undesirably remove portions of gate stack150and, in some embodiments, expose channel region110. In another example, chemicals and/or impurities entering seam160A′ and/or seam160B′ during subsequent processing may alter physical and/or electrical characteristics of channel region110, particularly when channel region110is exposed by unintentional removal of portions of gate stack150. In some embodiments, damage to gate stack150and/or channel region110caused by chemicals and/or impurities entering seam160A′ and/or seam160B′ may render device100inoperable.

The present disclosure addresses these challenges and eliminates or significantly reduces voids and/or seams in gate stack150by reducing stress in glue layer156and correspondingly eliminating or reducing warpage of gate structure125that may cause such voids and/or seams. For example, returning toFIGS.3A-3I, inFIG.3FandFIG.3G, a stress reduction treatment170is performed on glue layer156(FIG.3F), thereby providing stress-treated glue layer156′ (FIG.3G). Stress reduction treatment170alters properties and/or characteristics of glue layer156to reduce its residual stress, such that stress-treated glue layer156′ has a residual stress that is less than a residual stress of glue layer156. For example, stress reduction treatment170converts residual tensile stress (e.g., greater than 0 GPa) to residual compressive stress (e.g., less than 0 Pa), where a residual stress of 0 GPa indicates a neutralized stress or stress-free metal layer. In some embodiments, glue layer156has a residual stress of about 1.0 GPa to about 3 GPa (i.e., a residual tensile stress), and stress-treated glue layer156′ has a residual stress of about −2.5 GPa to about 0.8 GPa (i.e., a residual compressive stress, a neutralized stress, or a negligible residual tensile stress). Stress-treated glue layer156′ having a residual stress of about −2.5 GPa to about 0.8 GPa exhibits minimal to no warping, bending, necking, and/or bowing, which correspondingly eliminates or significantly reduces warping of gate structure125and formation of voids and/or seams in gate stack150. In contrast, glue layers having a residual stress greater than about 0.8 GPa or less than about −2.5 GPa may still exhibit undesired warping, bending, necking, and/or bowing, which can cause warping of gate structure125that can lead to formation of voids and/or seams in gate stack150.

Stress reduction treatment170reduces bowing, necking, and/or other profile variations in gate structure125and/or gate stack150. For example, gate stack150and gate spacers135have substantially vertical sidewalls after stress reduction treatment170, and minimal (to no) bowing and/or necking is observed in gate structure125and/or gate stack150after stress reduction treatment170. In embodiments where necking portions and/or bowing are observed in gate structure125and/or gate stack150after stress reduction treatment170, necking critical dimensions CDNare about 0% to about 15% less than critical dimension CD and bowing critical dimensions CDBare about 0% to about 5% greater than critical dimension CD. In other words, differences between critical dimension CD and necking critical dimensions CDNand/or bowing critical dimensions CDBin gate stack150are significantly smaller after stress reduction treatment170. In some embodiments, any observable difference between necking critical dimension CDNand critical dimension CD is less than about10A. In some embodiments, any observable difference between bowing critical dimension CDBand critical dimension CD is less than about 10 Å. Further, any observed necking angles θ are less than about 5° and any observed bowing angles φ are less than about 5°. In some embodiments, observed necking angles θ are about 2° to about 4° (e.g., 3.5°). In some embodiments, observed bowing angles φ are about 2° to about 4° (e.g., 3.5°). Accordingly, gate stack150having stress-treated glue layer156′ has critical dimension CD that is substantially the same from top to bottom (i.e., a substantially uniform critical dimension). In such embodiments, gate structure125and/or gate stack150has a rectangular cross-sectional profile. In some embodiments, where gate structure125and/or gate stack150exhibit slight necking and/or bowing, gate structure125and/or gate stack150may have a concave cross-sectional profile (i.e., a portion having a middle and ends, where a width of the middle is less than widths of the ends). However, it is noted that residual stress in stress-treated glue layer156′ that is less than about −2.5 GPa (i.e., larger compressive residual stress) may induce necking that narrows gate opening145sufficiently to cause undesired void and/or seam formation. Further, gate structures and/or gate stacks having necking critical dimensions CDNmore than 15% less than critical dimension CD, bowing critical dimensions CDBmore than 5% greater than critical dimension CD, critical dimension differences that are greater than 10 Å, necking angles θ that are greater than about 5°, bowing angles φ that are greater than about 5°, or combinations thereof may still exhibit undesired warping, bending, necking, and/or bowing.

In some embodiments, stress reduction treatment170decreases a d-spacing (i.e., a distance between parallel crystal planes in a material) in glue layer156to reduce its residual stress. For example, glue layer156has a d-spacing that is greater than about 2.105 Å, stress-treated glue layer156′ has a d-spacing that is less than or equal to about 2.105 Å, and stress-treated glue layer156′ has a residual stress that is less than a residual stress of glue layer156(i.e., reducing d-spacing reduces residual stress). In some embodiments, stress reduction treatment170increases a ratio of titanium to nitrogen (i.e., a Ti/N ratio) in glue layer156to reduce its residual stress. For example, glue layer156has a Ti/N ratio that is less than about 1.0 (e.g., about 0.8 to about 1.0), stress-treated glue layer156′ has an Ti/N ratio that is greater than about 1.0 (e.g., about 1.3 to about 2.0), and stress-treated glue layer156′ has a residual stress that is less than a residual stress of glue layer156. In some embodiments, stress reduction treatment170incorporates and/or increases an amount of non-metal species in glue layer156to reduce its residual stress. For example, glue layer156is substantially free of a non-metal species (e.g., argon (Ar), oxygen (O), fluorine (F), hydrogen (H), other suitable non-metal species, or combinations thereof), stress-treated glue layer156′ includes the non-metal species (e.g., Ar, O, F, H, other non-metal species, or combinations thereof), and stress-treated glue layer156′ has a residual stress that is less than a residual stress of glue layer156(i.e., increasing an amount of non-metal species reduces residual stress). In another example, glue layer156includes a first concentration (e.g., a negligible amount) of a non-metal species, stress-treated glue layer156′ includes a second concentration of the non-metal species that is greater than the first concentration, and stress-treated glue layer156′ has a residual stress that is less than a residual stress of glue layer156.

In some embodiments, stress reduction treatment170is an ion implantation process that bombards glue layer156with a dopant species (also referred to as implant species and/or ions) to alter its stress properties. For example, Ar, N, O, F, other suitable dopant species, or combinations thereof are implanted in glue layer156using an implant energy of about 0.5 kiloelectronvolts (keV) to about 5 keV and an implant dose of about 1×1014cm−3to about 1×1016cm3. A tilt angle of about 5° to about 15° can be implemented to implant the dopant species in glue layer156, where the tilt angle is between an incident ion beam direction and a normal direction of substrate105. To ensure that stress-treated glue layer156′ has a sufficiently low residual stress (e.g., less than about 0.8 GPa) to eliminate (or significantly reduce) bowing and/or necking of gate structure125and/or gate stack150, the ion implantation process is configured to provide stress-treated glue layer156′ with a concentration of non-metal dopant species (e.g., Ar, N, O, F, other non-metal dopant species, or combinations thereof) that is greater than about9x1016cm3. The dopant species penetrate glue layer156to a depth D in stress-treated glue layer156′ (FIG.3G). The ion implantation process is configured to implant dopant species deep enough in glue layer156to adequately alter properties and/or characteristics of glue layer156and reduce its residual stress while ensuring that dopant species do not reach (or only negligible amounts of dopant species reach) underlying gate layers, such as metal gate layer154and/or gate dielectric layer152. Depth D is thus less than or equal to thickness T. In some embodiments, depth D is about 20 Å to about 100 Å. In some embodiments, bombarding glue layer156with dopant species breaks and/or modifies a lattice structure of glue layer156in a manner that can reduce strain/stress. In such embodiments, glue layer156and stress-treated glue layer156′ have different lattice structures (e.g., stress-treated glue layer156′ has a more relaxed lattice structure and/or smaller d-spacing) and different residual stress properties (e.g., stress-treated glue layer156′ exhibits less residual stress).

In some embodiments, stress reduction treatment170is an argon ion implantation process that introduces argon into glue layer156. In such embodiments, a flow rate of an argon-containing gas (e.g., Ar) into the process chamber during the ion implantation process is about 1,000 standard cubic centimeters per minute (sccm) to about 5,000 sccm. In some embodiments, stress reduction treatment170is a nitrogen ion implantation process that introduces nitrogen into glue layer156. In such embodiments, a flow rate of a nitrogen-containing gas (e.g., N2) into the process chamber during the ion implantation process is about 1,000 sccm to about 2,000 sccm. In some embodiments, stress reduction treatment170is an oxygen ion implantation process that introduces oxygen into glue layer156. In such embodiments a flow rate of an oxygen-containing gas (e.g., O2) into the process chamber during the ion implantation process is about 1,000 sccm to about 2,000 sccm. In some embodiments, stress reduction treatment170is a fluorine ion implantation process that introduces fluorine into glue layer156. In such embodiments, a flow rate of a fluorine-containing gas (e.g., F2) into the process chamber during the ion implantation process is about 500 sccm to about 1,500 sccm. Various ion implantation parameters can be tuned to alter stress properties of glue layer156and provide stress-treated glue layer156′ with desired stress properties (e.g., residual stress less than about 0.8 GPa), such as implant dopant species, implant energy (e.g., ion beam energy), implant dose, implant angle (e.g., tilt angle), implant gas composition (e.g., type of dopant source gas and/or type of carrier gas), dopant gas flow rate, carrier gas flow rate, implant temperature, implant time, other suitable ion implantation parameters, or combinations thereof. For example, implant energies, implant doses, tilt angles, and dopant gas flow rates that are greater than upper ends of the examples provided may cause defects (e.g., physical defects, such as pit defects, and/or electrical defects) in and/or undesirably alter properties/characteristics (e.g., undesired threshold voltage shifts) of stress-treated glue layer156′, metal gate layer154, gate dielectric layer152, interfacial layer152A, or combinations thereof, while those that are less than lower ends of the examples provided will not reduce residual stress enough in glue layer156to eliminate or significantly reduce warping of gate structure125(i.e., stress-treated glue layer156′ may still have a residual tensile stress that is too high (e.g., greater than 0.8 GPa)). In some embodiments, values of implant energies, implant doses, tilt angles, and dopant gas flow rates depend on a thickness of glue layer156.

In some embodiments, stress reduction treatment170is a thermal process, such as an annealing process, that heats glue layer156in a gas atmosphere to alter its stress properties. For example, glue layer156is annealed at a temperature of about 300° C. to about 500° C. in a process chamber that includes an oxygen-containing gas (e.g., O2) and/or a hydrogen-containing gas (e.g., H2). In such embodiments, oxygen and/or hydrogen are introduced into glue layer156during stress reduction treatment170and stress-treated glue layer156′ includes oxygen and/or hydrogen. In other words, glue layer156undergoes an oxidation process and/or a hydrogenation process. In some embodiments, an oxygen concentration in stress-treated glue layer156′ after an O2anneal is greater than about b9×1016cm3. In some embodiments, a hydrogen concentration in stress-treated glue layer156′ after an H2anneal is greater than about 9×1016cm−3. In some embodiments, a flow rate of the gas (e.g., O2and/or H2) into the process chamber during the annealing process is about 100 sccm to about 200 sccm. In some embodiments, the annealing process is performed at a pressure of about 3 Torr to about 50 Torr. In some embodiments, the annealing process is a rapid thermal anneal (RTA). Various annealing parameters can be tuned to alter stress properties of glue layer156and provide stress-treated glue layer156′ with desired stress properties (e.g., residual stress less than about 0.8 GPa), such as anneal temperature, anneal pressure, anneal time, anneal gas composition, anneal gas flow rate, other suitable anneal parameters, or combinations thereof. For example, anneal temperatures, anneal gas flow rates, and anneal pressures that are greater than upper ends of the examples provided may alter properties of glue layer156, metal gate layer154, gate dielectric layer152, interfacial layer152A, or combinations thereof in ways that cause undesired threshold voltage shifts in device100, while those that are less than lower ends of the examples provided will not reduce residual stress enough to eliminate or significantly reduce warping of gate structure125. The present disclosure also contemplates annealing glue layer156in other gas environments, such that stress-treated glue layer156′ may include other constituents other than or in addition to oxygen and/or hydrogen depending on anneal gas composition.

In embodiments where glue layer156is subjected to an oxygen anneal (i.e., in a process chamber that includes an oxygen-containing gas), device100may be subjected to a wet clean process before the oxygen anneal. For example, an ozonated deionized water (DIO3) clean process may be performed on glue layer156before the oxygen anneal. In such embodiments, a DIO3solution having an ozone concentration of about 30 ppm to about 100 ppm may be applied to glue layer156while a wafer having device100formed thereon is spun at a speed of about 240 rotations per minute (rpm) to about 500 rpm.

InFIG.3H, metal fill (or bulk) layer158is formed over substrate105. Metal fill layer158is disposed on stress-treated glue layer156′ and fills a remainder of gate opening145. In some embodiments, metal fill layer158has a thickness of about 1,500 Å to about 3,000 Å. Because stress reduction treatment170provides stress-treated glue layer156′, gate structure125has minimal to no warpage, a width of gate opening145is substantially uniform along a height of gate structure125, and metal fill layer158can completely fill the remainder of gate opening145without a void forming in gate stack150. For example, the substantially uniform width of gate opening145reduces likelihood of metal fill layer158plugging or pinching off gate opening145before filling. Metal fill layer158includes a suitable conductive material, such as Al, W, Cu, other metals, metal oxide, metal nitride, other suitable conductive material, or combinations thereof. Metal fill layer158is formed by ALD, PVD, CVD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, plating, other suitable methods, or combinations thereof. In the depicted embodiment, metal fill layer158is a tungsten layer formed by PVD or CVD.

Turning toFIG.3I, a planarization process is performed to remove excess gate materials from device100. For example, a CMP process is performed until a top surface of dielectric layer140is reached (exposed). In some embodiments, CMP process is continued and reduces a thickness of dielectric layer140, and correspondingly, a height of gate structure125. In the depicted embodiment, a top of gate structure125is substantially planar with a top of dielectric layer140after the CMP process, and remainders of the gate materials, which fill gate opening145, form gate stack150of gate structure125. Gate stack150includes a gate dielectric (e.g., interfacial layer152A and gate dielectric layer152) and a gate electrode (e.g., metal gate layer154, stress-treated glue layer156′, and metal fill layer158). Where gate dielectric layer152is a high-k dielectric layer, gate stack150can be referred to as a high-k/metal gate. Because stress reduction treatment170is performed to provide stress-treated glue layer156′ before forming metal fill layer158, gate structure125has minimal to no warpage, and metal fill layer158can completely fill the remainder of gate opening145without forming a void in gate stack150. Consequently, gate stack150does not have any seams therein, such as seam160A′ and/or seam160B′ (which, as described above, occur when a void is formed in gate stack150because metal fill layer158insufficiently fills the remainder of gate opening145because of the warped profile of gate structure125caused by residual tensile stress of glue layer156). In some embodiments, a negligible seam may form in gate stack150, such as a seam having a width that is less than about 4 Å. Seams less than about 4 Å rarely result in damage to gate stack150and/or channel region110, such as that described above with respect to seam160A′ and/or seam160B′. Gate stacks, such as gate stack150, having negligible seams (i.e., seams having widths less than about 4 Å) are thus considered seam-free for purposes of the present disclosure.

In some embodiments, device100is a transistor that includes a channel (e.g., channel region110), source/drains (e.g., epitaxial source/drains120), and a gate (e.g., gate structure125having gate spacers135disposed along sidewalls of gate stack150). The gate engages the channel defined between the source/drains, and current can flow between the source/drains (e.g., between source and drain or vice versa) during operation. In some embodiments, device100is a FinFET, channel region110is a portion of a semiconductor fin extending from substrate105, gate stack150is on a top of the semiconductor fin (and thus channel region110) in the Y-Z plane, and gate stack150wraps the semiconductor fin (and thus channel region110) in the X-Z plane, such as inFIG.1(i.e., gate stack150is disposed on a top and sidewalls of the semiconductor fin). In some embodiments, device100is a GAA transistor, such as depicted inFIG.10. InFIG.10, channel region110is at least one semiconductor layer (i.e., a channel layer) suspended over substrate105, gate stack150is on a top and a bottom of the at least one semiconductor layer (and thus channel region110) in the Y-Z plane (i.e., gate stack150is also between channel region110and substrate105), and gate stack150surrounds the at least one semiconductor layer (and thus channel region110) in the X-Z plane (i.e., gate stack150is disposed on a top, a bottom, and sidewalls of the at least one semiconductor layer). In such embodiments, inner spacers180are disposed between gate stack150and epitaxial source/drains120. In such embodiments, before forming gate stack150in gate opening145, a channel release process is performed to provide channel region110with at least one semiconductor layer suspended over substrate105(i.e., the semiconductor layer does not physically contact substate105after the channel release process). For example, where gate opening145exposes a semiconductor layer stack having first semiconductor layers (e.g., silicon germanium layers) and second semiconductor layers (e.g., silicon layers), the first semiconductor layers are selectively removed to form air gaps between the second semiconductor layers and between the second semiconductor layers and substrate105, thereby suspending the second semiconductor layers over substrate105. The second semiconductor layers are vertically stacked along the z-direction and provide channel region110with one or more channels through which current can flow between epitaxial source/drains120. In some embodiments, an etching process is performed to selectively etch the first semiconductor layers with minimal (to no) etching of the second semiconductor layers, substrate105, gate spacers135, dielectric layer140, and/or inner spacers. In some embodiments, an etchant is selected for the etch process that etches silicon germanium (i.e., the first semiconductor layers) at a higher rate than silicon (i.e., the second semiconductor layers and substate105) and dielectric materials (i.e., gate spacers135, dielectric layer140, and/or inner spacers) (i.e., the etchant has a high etch selectivity with respect to silicon germanium). The etching process is a dry etch, a wet etch, other suitable etching process, or combinations thereof. In some embodiments, before performing the etching process, an oxidation process can be implemented to convert the first semiconductor layers into silicon germanium oxide features, where the etching process then removes the silicon germanium oxide features. In some embodiments, during and/or after removing the first semiconductor layers, an etching process is performed to modify a profile of the second semiconductor layers to achieve target dimensions and/or target shapes for channel region(s)110.

In some embodiments, fabrication of device100can proceed with forming various contacts to facilitate operation of device100. For example, one or more dielectric layers, similar to dielectric layer140, can be formed over gate structure125(including gate stack150) and dielectric layer140. Contacts can then be formed in dielectric layer140and/or dielectric layers disposed over dielectric layer140. For example, contacts are respectively formed that physically and/or electrically couple with gate stack150and one or both of epitaxial source/drains120of device100. Contacts include a conductive material, such as metal. Metals include aluminum, aluminum alloy (such as aluminum/silicon/copper alloy), copper, copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polysilicon, metal silicide, other suitable metals, or combinations thereof. The metal silicide may include nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, erbium silicide, palladium silicide, or combinations thereof. In some embodiments, dielectric layers disposed over dielectric layer140and the contacts (for example, the gate contact and the source/drain contacts extending through dielectric layer140and/or dielectric layers disposed thereof) are a portion of the MLI feature disposed over substrate105, as described above. The MLI feature can include a combination of metal layers and dielectric layers configured to form vertical interconnect features, such as contacts and/or vias, and/or horizontal interconnect features, such as lines. The various conductive features include materials similar to the contacts. In some embodiments, a damascene process and/or dual damascene process is used to form the MLI feature.

FIGS.8A-8Gare fragmentary diagrammatic views of a device200, in portion or entirety, at various fabrication stages (such as those associated with method50inFIG.2) according to various aspects of the present disclosure. Device200may be included in a microprocessor, a memory, and/or other integrated circuit device. Device200may be a portion of an IC chip, an SoC, or portion thereof, that includes various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, PFETs, NFETs, MOSFETs, CMOS transistors, BJTs, LDMOS transistors, high voltage transistors, high frequency transistors, other suitable components, or combinations thereof.FIGS.8A-8Ghave been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Additional features can be added in device200, and some of the features described below can be replaced, modified, or eliminated in other embodiments of device200.

Fabrication of device200inFIGS.8A-8Gis similar in many respects to fabrication of device200inFIGS.3A-3I, except fabrication of device200forms a stress-treated multilayer glue layer256′ instead of stress-treated glue layer156′. For example, fabrication begins with receiving a device precursor including, for example, substrate105, channel region110, epitaxial source/drains120, gate structure125(including dummy gate130and gate spacers135), and dielectric layer140(FIG.8A, fabrication of which is similar to that described with reference toFIG.3A), removing dummy gate130to form gate opening145(FIG.8B, fabrication of which is similar to that described with reference toFIG.3B), forming gate dielectric layer152that partially fills gate opening145(FIG.8C, fabrication of which is similar to that described with reference toFIG.3C), and forming metal gate layer154over gate dielectric layer152(FIG.8D, fabrication of which is similar to that described with reference toFIG.3D).

Then, turning toFIG.8E, instead of forming a single glue layer, such as glue layer156, and performing stress reduction treatment170to provide stress-treated glue layer156′, fabrication of device200proceeds with forming stress-treated multilayer glue layer256′ having thickness T. Stress-treated multilayer glue layer256′ partially fills gate opening145. Similar to stress-treated glue layer156′, stress-treated multilayer glue layer256′ has a residual stress of about −2.5 GPa to about 0.8 GPa (i.e., a residual compressive stress, a neutralized stress, or a negligible residual tensile stress) and thus exhibits minimal to no warping, bending, necking, and/or bowing, which correspondingly eliminates or significantly reduces warping of gate structure125as evident fromFIG.8E. Gate stack150having stress-treated multilayer glue layer256′ has a profile similar to that described above for gate stack150having stress-treated glue layer156′, such as a substantially uniform critical dimension and/or necking critical dimensions CDN, bowing critical dimensions CDB, critical dimension differences, necking angles θ, bowing angles φ, or combinations thereof as described above.

Stress-treated multilayer glue layer256′ includes glue sublayers256separated by metal layers260. In the depicted embodiment, stress-treated multilayer glue layer256′ includes three glue sublayers256and two metal layers260, where a first one of glue sublayers256physically contacts metal gate layer154, a first one of metal layers260is between the first one of glue sublayers256and a second one of glue sublayers256, and a second one of metal layers260is between the second one of glue sublayers256and a third one of glue sublayers256. Glue sublayers256have a thickness T1, and metal layers260have a thickness T2. In some embodiments, thickness T1is about 2 Å to about 5 Å. In some embodiments, thickness T2is about 2 Å to about 5 Å. Stress-treated multilayer glue layer256′ includes a material that promotes adhesion between metal gate layer154and metal fill layer158, such as a material that includes metal (for example, W, Al, Ta, Ti, Ni, Cu, Co, other suitable metal, or combinations thereof), metal oxides, metal nitrides, metal alloys, or combinations thereof. For example, glue sublayers256include a metal and nitrogen, and metal layers260include the metal. In the depicted embodiment, glue sublayers256are titanium nitride layers (e.g., TiN layers), and metal layers260are titanium layers (e.g., Ti layers). In some embodiments, glue sublayers256are tantalum nitride layers (e.g., TaN layers), and metal layers260are tantalum layers (e.g., Ta layers). As described further below, a hydrogen poisoning process is performed when forming stress-treated multilayer glue layer256′, such that glue sublayers256and/or metal layers260also include hydrogen. For example, glue sublayers256include titanium, nitrogen, and hydrogen, and/or metal layers260include titanium and hydrogen. Glue sublayers256and metal layers260are formed by ALD, PVD, CVD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, plating, other suitable methods, or combinations thereof.

In some embodiments, forming stress-treated multilayer glue layer256′ includes loading a wafer having device200fabricated thereon into a process chamber; heating the wafer to a desired temperature (e.g., a temperature that facilitates chemical reactions needed to form glue sublayers256and metal layers260); performing at least one glue sublayer/metal layer pair (i.e., a deposition cycle that includes depositing a glue sublayer (e.g., a titanium nitride layer), depositing a metal layer (e.g., a titanium layer) over the glue sublayer, and performing a hydrogen poisoning treatment (e.g., an H2soak); and depositing a top glue sublayer over the at least one glue sublayer/metal layer pair. Depositing glue sublayers256and metal layers160can include flowing one or more precursors and/or carriers (e.g., H2, N2, Ar, other suitable carrier gas, or combinations thereof) into the process chamber, where the precursors react and/or decompose to form glue sublayers256or metal layers260. In some embodiments, depositing glue sublayers256includes introducing a titanium-containing precursor gas (e.g., a titanium tetrachloride (TiCl4) gas), a nitrogen-containing precursor gas (e.g., ammonia (NH3) gas), and carrier gas (e.g., H2and/or Ar) into the process chamber for a duration that allows for depositing TiN material having thickness T1. In some embodiments, depositing metal layers260includes introducing a titanium-containing precursor gas (e.g., TiCl4) and a carrier gas (e.g., H2and/or Ar) into the process chamber for a duration (reaction time) that allows for depositing Ti material having thickness T2, such as about 10 seconds to about 120 seconds. In some embodiments, performing the hydrogen poisoning treatment includes introducing a hydrogen-containing gas (e.g., H2) into the process chamber for a duration that is sufficient to incorporate hydrogen into glue sublayers256and/or metal layers260, such as about 10 seconds to about 30 seconds. In some embodiments, a hydrogen concentration in stress-treated multilayer glue layer256′ is about 0.5 atomic percent (at %) to about 1 at %. In some embodiments, a temperature maintained in the process chamber when forming stress-treated multilayer glue layer256′ is about 400° C. to about 500° C. Forming stress-treated multilayer glue layer256′ can further include purging any remaining precursors (e.g., unreacted precursors), carriers, and/or byproducts from the process chamber. In some embodiments, the process chamber is purged after depositing each glue sublayer, for example, to remove nitrogen-containing byproducts before depositing the metal layer. In some embodiments, the process chamber is purged after depositing each metal sublayer. In some embodiments, the process chamber is purged after each hydrogen poisoning treatment. In some embodiments, the process chamber is purged after the last deposition cycle and before depositing the top glue sublayer.

Various deposition parameters and hydrogen poisoning treatment parameters can be tuned to alter stress properties of stress-treated multilayer glue layer256′, glue sublayers256, metal layers260, or combinations thereof and provide stress-treated multilayer glue layer256′ with desired stress properties (e.g., residual stress less than about 0.8 GPa), such as deposition precursor type, deposition precursor flow rate, carrier gas type, carrier gas flow rate, deposition pressure, deposition temperature, deposition power, deposition time, hydrogen poisoning treatment precursor type, hydrogen gas flow rate during the hydrogen poisoning treatment, hydrogen poisoning treatment time, hydrogen poisoning treatment temperature, other suitable deposition parameters, other hydrogen poisoning treatment parameters, or combinations thereof. For example, deposition temperatures, deposition times, and hydrogen treatment times that are greater than upper ends of the examples provided may alter properties of metal layers260, glue sublayers256, metal gate layer154, gate dielectric layer152, interfacial layer152A, or combinations thereof in ways that cause undesired threshold voltage shifts in device200, while those that are less than lower ends of the examples provided will not reduce residual stress enough to eliminate or significantly reduce warping of gate structure125. A flow rate of the titanium-containing precursor when depositing glue sublayers256can be the same or different than a flow rate of the titanium-containing precursor when depositing metal layers260. A flow rate of a hydrogen gas when depositing metal layers260can be the same or different than a flow rate of the hydrogen gas when performing the hydrogen poisoning treatment. A titanium-containing precursor used when depositing glue sublayers256can be the same or different than a titanium-containing precursor used when depositing metal layers260.

Fabrication of device200inFIG.8FandFIG.8Gthen proceeds similar to fabrication of device100inFIG.3HandFIG.31, respectively. For example, fabrication includes forming metal fill layer158over stress-treated multilayer glue layer256″ (FIG.8F, fabrication of which is similar to that described with reference toFIG.3H) and performing a planarization process to remove excess gate materials from device200, thereby forming gate stack150(FIG.8G, fabrication of which is similar to that described with reference toFIG.31). InFIG.8G, gate stack150includes a gate dielectric (e.g., interfacial layer152A and gate dielectric layer152) and a gate electrode (e.g., metal gate layer154, stress-treated multilayer glue layer256″, and metal fill layer158). Because stress-treated multilayer glue layer256″ has sufficiently low residual stress (e.g., less than about 0.8 GPa and greater than about −2.5 GPa), gate structure125has minimal to no warpage, and metal fill layer158can completely fill the remainder of gate opening145without forming a void in gate stack150. Consequently, gate stack150having stress-treated multilayer glue layer256″ does not have any seams therein, such as seam160A′ and/or seam160B′ (which, as described above, occur when a void is formed in gate stack150because metal fill layer158insufficiently fills the remainder of gate opening145because of the warped profile of gate structure125caused by residual tensile stress of a glue layer). The present disclosure also contemplates device200, which includes gate stack150having stress-treated multilayer glue layer256′, being configured as depicted inFIG.10.

FIG.9AandFIG.9Bprovide experimental data for wafers having devices fabricated thereon that include gate stacks having glue layers according to various aspects of the present disclosure.FIG.9Ais an exemplary plot310of defect counts obtained by electron beam inspection (EBI) as a function of d-spacing (in Å ) of glue layers. Defects detected by EBI can include voids and/or seams in the gate stacks. InFIG.9A, EBI and d-spacing of glue layers was evaluated for four wafers:A1, a wafer that includes devices with gate stacks having glue layers that were not subjected to a stress reduction treatment, such as described above with reference toFIG.4A,FIG.4B,FIG.5,FIG.6A,FIG.6B, andFIG.7;A2, a wafer that includes devices with gate stacks having stress-treated glue layers, where the stress reduction treatment was an ion implantation process, such as described above with reference toFIGS.3A-3I;A3, a wafer that includes devices with gate stacks having stress-treated glue layers, where the stress reduction treatment was a thermal process, such as described above with reference toFIGS.3A-3I; andA4, a wafer that includes devices with gate stacks having stress-treated multilayer glue layers, such as described above with reference toFIGS.8A-8G.

FIG.9Bis an exemplary plot320of defect counts obtained by EBI as a function of stress (in GPa) of glue layers. InFIG.9B, EBI and stress of glue layers was evaluated for six wafers:B1, a wafer that includes devices with gate stacks having glue layers that were not subjected to a stress reduction treatment, such as described above with reference toFIG.4A,FIG.4B,FIG.5,FIG.6A,FIG.6B, andFIG.7;B2, a wafer that includes devices with gate stacks having stress-treated glue layers, where the stress reduction treatment was an ion implantation process, such as described above with reference toFIGS.3A-3I;B3& B4, wafers that include devices with gate stacks having stress-treated glue layers, where the stress reduction treatment was a thermal process, such as described above with reference toFIGS.3A-3I; andB5& B6, wafers that include devices with gate stacks having stress-treated multilayer glue layers, such as described above with reference toFIGS.8A-8G.

FromFIG.9AandFIG.9B, it is evident that defects, such as voids and/or seams in gate stacks, are directly proportional to d-spacing of glue layers of the gate stacks and/or residual stress of glue layers of the gate stacks. In other words, defects decrease as d-spacing and/or residual stress of glue layers of the gate stacks decrease, and defects increase as d-spacing and/or residual stress of glue layers of the gate stacks increase. For example, wafers that include devices with gate stacks having glue layers subjected to stress reduction treatments (e.g., A2-A4and B2-B6) have less defects than wafers that include devices with gate stacks having glue layers that were not subjected to stress reduction treatments (e.g., Al and B1), and wafers having glue layers subjected to stress reduction treatments (e.g., A2-A4and B2-B6) have smaller d-spacing and less residual stress than wafers having glue layers that were not subjected to stress reduction treatments (e.g., A1and B1). In plot310ofFIG.9A, a line A fitted to the experimental data for wafers A1—A4indicates that defects decrease as d-spacing of glue layers of the gate stacks decrease. In plot320ofFIG.9B, a line B fitted to the experimental data for wafers Bl—B6indicates that defects decrease as residual stress of glue layers of the gate stacks decrease. Accordingly, providing gate stacks with stress-treated glue layers, such as stress-treated glue layer156′ and stress-treated multilayer glue layer256′, can significantly reduce and/or eliminate warping of the gate stacks, which correspondingly reduces and/or eliminates voids and/or seams in the gate stacks and reduces and/or eliminates damage to channel regions (over which the gate stacks are fabricated). Different embodiments may have different advantages, and no particular advantage is necessarily required of any embodiment.

The present disclosure provides for many different embodiments. Various methods for forming gate stacks (e.g., high-k/metal gates) with improved profiles (e.g., minimal to no warping, bending, bowing, and necking and/or substantially vertical sidewalls) and related gate structures are disclosed herein, which may be implemented in a variety of device types. For example, the gate stacks described herein are suitable for planar field-effect transistors (FETs), multigate transistors, such as fin-like FETs (FinFETs), gate-all-around (GAA) transistors, omega-gate (Ω-gate) devices, pi-gate (Π-gate) devices, or combinations thereof as well as strained-semiconductor devices, silicon-on-insulator (SOI) devices, partially-depleted SOI devices, fully-depleted SOI devices, other devices, or combinations thereof. The present disclosure contemplates that one of ordinary skill may recognize other IC devices that can benefit from the gate stacks and/or the gate formation techniques described herein.

An exemplary method includes for forming a gate stack includes depositing a gate dielectric layer on a channel region, depositing a work function layer on the gate dielectric layer, forming a stress-treated glue layer on the work function layer, and depositing a metal fill layer on the stress-treated glue layer. In some embodiments, forming the stress-treated glue layer over the work function layer includes depositing a metal nitride layer over the work function layer and introducing a non-metal species into the metal nitride layer. The non-metal species is argon, nitrogen, fluorine, oxygen, hydrogen, or a combination thereof. In some embodiments, the non-metal species is introduced into the metal nitride layer by an ion implantation process. In some embodiments, the non-metal species is introduced into the metal nitride layer by a thermal process performed in a gas atmosphere. In some embodiments, forming the stress-treated glue layer over the work function layer includes depositing a first glue sublayer over the work function layer, depositing a metal layer over the first glue sublayer, depositing a second glue sublayer over the metal layer, and performing a hydrogen poisoning treatment.

In some embodiments, the gate stack has a bowing critical dimension that is about 30% to about 35% greater than a pre-defined critical dimension of the gate stack and the introducing the non-metal species into the metal nitride layer is configured to reduce the bowing critical dimension, such that the bowing critical dimension is about 0% to about 5% greater than the pre-defined critical dimension. In some embodiments, the metal nitride layer has a first d-spacing and introducing the non-metal species into the metal nitride layer is configured to reduce the first d-spacing to a second d-spacing. In some embodiments, the metal nitride layer has a first nitrogen concentration and the introducing the non-metal species into the metal nitride layer is configured to increase the first nitrogen concentration to a second nitrogen concentration.

Another exemplary method includes forming a gate opening that exposes a channel region, forming a gate dielectric layer in the gate opening, forming a work function layer in the gate opening over the gate dielectric layer, forming a metal glue layer in the gate opening over the work function layer, performing a stress reduction treatment on the metal glue layer, and after the stress reduction treatment, forming a metal fill layer in the gate opening over the metal glue layer. The gate dielectric layer, the work function layer, the metal glue layer, and the metal fill layer form a gate stack of a gate structure that fills the gate opening. In some embodiments, the metal glue layer has residual tensile stress, and the performing the stress reduction treatment on the metal glue layer includes changing the residual tensile stress to residual compressive stress. In some embodiments, the metal glue layer has residual stress greater than about 1.0 GPa, and the performing the stress reduction treatment on the metal glue layer includes reducing the residual stress to less than about 1.0 GPa. In some embodiments, the gate structure has a first gate spacer and a second gate spacer, the gate opening is between the first gate spacer and the second gate spacer, a first distance is between the first gate spacer and the second gate spacer before forming the metal glue layer in the gate opening, a second distance is between the first gate spacer and the second gate spacer after forming the metal glue layer in the gate opening, and the stress reduction treatment is tuned to reduce the second distance to the first distance. In some embodiments, performing the stress reduction treatment on the metal glue layer includes performing an ion implantation process on the metal glue layer. In some embodiments, performing the stress reduction treatment on the metal glue layer includes annealing the metal glue layer in a gas atmosphere and, in some embodiment, performing a wet clean process before the annealing the metal glue layer in the gas atmosphere.

An exemplary device includes a channel region disposed between epitaxial source/drains and a gate stack disposed over the channel region. The gate stack includes a gate dielectric layer, a work function layer over the gate dielectric layer, a metal glue layer over the work function layer, and a metal fill layer over the metal glue layer. The metal glue layer has a residual stress of about −2.5 gigapascals (GPa) to about 0.8 GPa. In some embodiments, the metal glue layer includes a metal and a non-metal dopant and a concentration of the non-metal dopant is greater than about 9×1016cm3. In some embodiments, the metal glue layer includes a metal layer disposed between a first glue sublayer and a second glue sublayer, the first glue sublayer and the second glue sublayer include a metal and nitrogen, and the metal layer includes the metal. In some embodiments, the metal glue layer is a titanium nitride layer and a ratio of nitrogen to titanium in the titanium nitride layer is about 1.3 to about 2.