CMOS delay circuit with controllable delay

A variable delay circuit consists of a single-stage CMOS delay circuit having an associated time delay between its input and output. A first transistor connects a voltage supply node to other portions of the single-stage CMOS delay circuit. The impedance of the first transistor corresponds to an associated time delay. A second transistor, gated by a control signal, connects the voltage supply node and the other portions of the single-stage CMOS delay circuit in parallel with the first P-channel transistor. The delay circuit delays signals for a longer period of time when the second transistor is disabled by said control signal than when the second transistor is enabled. In a variation on this delay circuit, a plurality of delay control elements are coupled to the single-stage delay circuit, each accepting a distinct control signal and decreasing the delay circuits associated time delay to a corresponding shorter delay time when its control signal is enabled. This delay circuit delays signals by a multiplicity of distinct delay times in accordance with the control signals. Further variability in the delay time can be achieved by cascading a plurality of delay stages, with two or more of the said cascaded delay stages comprising a variable delay circuit with a delay time that is governed by one or more control signals. A multiplicity of different delay times can be selected via the control signals for the various variable delay stages.

The present invention relates generally to delay circuits, and particularly 
to a delay circuit in which the amount of delay generated is determined by 
the setting of one or more control signals. 
BACKGROUND OF THE INVENTION 
Many integrated circuits require delay circuits in certain signal paths. 
For instance, it may be important to delay the arrival of a signal until a 
particular circuit has prepared itself for the signal's arrival. A signal 
may be also be delayed to ensure that the circuit meets certain timing 
specifications. 
Conventional delay circuits produces a fixed amount of time delay, which 
may not be the optimal amount of delay under various conditions. In 
situtations where different amounts of delay would be optimal in different 
conditions, conventional delay circuits are designed either for a time 
delay amount that is a compromise value for all conditions, or a time 
delay that is best for one condition and acceptable for other conditions. 
It is therefore an object of the present invention to provide a delay 
circuit that creates different time delays under different conditions. 
SUMMARY OF THE INVENTION 
In summary, the present invention is a variable delay circuit consisting of 
a single-stage CMOS delay circuit having an associated time delay between 
its input and output. A first transistor connects a voltage supply node to 
other portions of the single-stage CMOS delay circuit. The impedance of 
the first transistor corresponds to an associated time delay. A second 
transistor, gated by a control signal, connects the voltage supply node 
and the other portions of the single-stage CMOS delay circuit in parallel 
with the first P-channel transistor. The delay circuit delays signals for 
a longer period of time when the second transistor is disabled by said 
control signal than when the second transistor is enabled. 
In a variation on this delay circuit, a plurality of delay control elements 
are coupled to the single-stage delay circuit, each accepting a distinct 
control signal and decreasing the delay circuits associated time delay to 
a corresponding shorter delay time when its control signal is enabled. 
This delay circuit delays signals by a multiplicity of distinct delay 
times in accordance with the control signals. 
Further variability in the delay time can be achieved by cascading a 
plurality of delay stages, with two or more of the said cascaded delay 
stages comprising a variable delay circuit with a delay time that is 
governed by one or more control signals. A multiplicity of different delay 
times can be selected via the control signals for the various variable 
delay stages.

DESCRIPTION OF THE PREFERRED EMBODIMENT 
Referring to FIG. 1, there is shown a single stage CMOS delay circuit 100, 
having three P-channel transistors M1, M2 and M3, and three N-channel 
transistors M4, M5 and M6. Transistors M1, M3, M4 and M5, all gated by the 
input signal IN, comprise a normal CMOS inverter. The circuit's 
transistors are serially coupled between VDD, the high voltage power 
supply node (typically 5 volts) for the circuit and VSS, the low voltage 
power supply node (typically 0 volts). The drain of transistor M1 is 
coupled to the source of transistor M3 at internal node 102, the drains 
transistors M3 and M4 are coupled at output node 104, and the drain of 
transistor M5 is coupled to the source of transistor M4 at internal node 
106. 
Forgetting about transistors M2 and M6 for the moment, the delay time 
associated with this inverter is government by the impedances of the 
transistors M1, M3, M4 and M5. In accordance with the present invention, 
transistors M3 and M4 will typically be fast devices with low impedance, 
while the M1 and M5 will be higher impedance devices that effective 
control the speed of the inverter. Thus, when transistors M2 and M6 are 
disabled, the delay time of the circuit 100 is governed primarily by 
transistors M1 and M5. 
Transistors M2 and M6 are connected in parallel with transistors M1 and M5, 
respectively, and are gated by complementary control signals CONTROL and 
CONTROL. Transistors M2 and M6 generally are much faster, lower impedance 
transistors than M1 and M5, with the exact impedances being selected so as 
to achieve a particular delay time when transistors M2 and M6 are enabled. 
When CONTROL=High, transistors M2 and M6 are disabled or off, and the 
delay circuit's delay time is governed by transistors M1 and M5. When 
CONTROL=Low, transistors M2 and M6 are enabled, and the delay circuit's 
delay time is governed by transistors M2 and M6. 
More specifically, when CONTROL=Low, the delay time of the circuit 100 is 
shorter than when CONTROL=High. A typical pair of delay times for circuit 
100 might be 1 nanosecond and 3 nanoseconds. The exact values of the two 
different delay times will depend on the particular sizes of the circuit's 
transistors. Delay times for a typical CMOS circuit 100 when CONTROL=Low 
can be, using current technology, as low as about 0.5 nanoseconds and as 
high as perhaps 5 nanoseconds or more. It is hard to put an upper limit on 
delay times when CONTROL=High, but a practical limit may be 50 nanoseconds 
or so. When even longer delays are needed, this will typically be achieved 
by cascading several delay stages, as will be discussed below with respect 
to FIG. 3. 
FIG. 2 shows a single-stage delay circuit 125 which is similar to that 
shown in FIG. 1, except that this circuit has N pairs of delay control 
elements connected in parallel with transistors M1 and M5. Each pair of 
delay control element accepts a distinct pair of complementary control 
signals CONTROL.sub.-- X and CONTROL.sub.-- X. Each pair of delay control 
elements has its own distinct impedance. Assuming that only one pair of 
complementary control signals is enabled at any one time, the circuit 125 
will have N+1 distinct and selectable delay times, with the impedance of 
each such pair of control elements determining the time delay of the 
circuit when its control signal is enabled. 
Alternately, all or several of the pairs or control elements could have 
identical impedances, with the delay of the circuit 125 being determined 
by the number of control signals which are enabled. 
FIG. 3 shows a delay circuit 150 having several cascaded delay stages 
152-158. Some of the stages of such a circuit, such as stage 158 have a 
fixed time delay while others have a variable delay controlled by a 
control signal C1, C2, C3. Using such a cascaded circuit provides an 
alternate mechanism for forming a delay circuit with multiple delay time 
values. It is also useful when the delay times needed are too long to be 
easily achieved with just a single stage delay circuit. 
FIG. 4 shows an example of a delay circuit 200 suitable for use in an 
integrated memory circuit. It has three simple inverter delay stages 
M11-M12, M13-M14 and M15-M16 followed by a variable delay stage. This 
delay circuit 200 is used to delay the DATA IN signal to meet the memory 
device's DATA SETUP TIME and DATA HOLD TIME specifications. Prior art 
delay circuits for such memory devices have a single associated delay time 
that is a compromise between these two timing specifications. In practice, 
the delay is preferred to be short when the WRITE ENABLE signal is 
asserted, and the delay is preferred to be long when the WRITE ENABLE 
signal is disabled. The following is a table of device sizes (given in 
terms of channel width and channel length) for one example this circuit: 
TABLE 
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EXAMPLE OF DEVICE SIZES FOR FIG. 4 
CHANNEL WIDTH/ 
DEVICE CHANNEL LENGTH (MICRONS) 
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M1 5.mu./10.mu. 
M2 40.mu./1.mu. 
M3 20.mu./1.mu. 
M4 10.mu./1.mu. 
M5 5.mu./10.mu. 
M6 20.mu./1.mu. 
M11 20.mu./1.mu. 
M12 10.mu./1.mu. 
M13 20.mu./1.mu. 
M14 10.mu./1.mu. 
M15 20.mu./1.mu. 
M16 10.mu./1.mu. 
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Using these device sizes, the last stage of circuit 200 has a fast delay 
time of about 1 nanosecond, when WRITE ENABLE is high, and a slow delay 
time of about 3 nanoseconds when WRITE ENABLE is low. These delay times 
can be changed by changing the transistor sizes. 
While the present invention has been described with reference to a few 
specific embodiments, the description is illustrative of the invention and 
is not to be construed as limiting the invention. Various modifications 
may occur to those skilled in the art without departing from the true 
spirit and scope of the invention as defined by the appended claims.