Graphene electronic device having channel layer including graphene islands and method of fabricating the same

A graphene electronic device includes a gate insulating layer on a conductive substrate, a channel layer on the gate insulating layer, and a source electrode on one end of the channel layer and a drain electrode on another end of the channel layer. The channel layer includes a semiconductor layer and a graphene layer in direct contact with the semiconductor layer, and the graphene layer includes a plurality of graphene islands spaced apart from each other.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of Korean Patent Application No. 10-2015-0116103, filed on Aug. 18, 2015, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND

Example embodiments relate to graphene electronic devices having a channel layer including graphene islands and methods of fabricating the graphene electronic devices.

2. Description of the Related Art

Graphene has relatively high charge mobility and relatively high electrical conductivity. Due to these characteristics, use of graphene in multifunctional devices using relatively low power has obtained attention. However, because graphene does not have a band gap despite its desirable electrical characteristics, it is difficult to use graphene as a channel of a transistor.

A field effect transistor (FET) having a channel formed of nano-ribbon graphene or graphene with a nano-hole may have a predetermined or given band gap, but the FET may have a relatively low on/off current ratio.

An amorphous oxide semiconductor has been researched as a material for a next-generation transparent device having improved transparency. When the amorphous oxide semiconductor is fabricated by a solution process, a fabrication process may be simple and fabrication costs may be reduced. For example, indium zinc oxide (IZO) fabricated by the solution process may have a relatively lower mobility than IZO fabricated by a RF-sputtering process according to device characteristics. A solution type may show a mobility of about 1 cm2V−1s−1to about 15 cm2V−1s−1, while a RF-Sputtering type may show the mobility of about 15 to about 60 cm2V−1s−1.

A graphene electronic device may be a FET, a sensor, a photo detector, etc.

SUMMARY

Example embodiments provide graphene electronic devices having a channel layer including a plurality of graphene islands on a semiconductor layer and methods of manufacturing the same.

According to example embodiments, a graphene electronic device includes a conductive substrate, a gate insulating layer on the conductive substrate, a channel layer on the gate insulating layer, and a source electrode on one end of the channel layer and a drain electrode on another end of the channel layer. The channel layer includes a semiconductor layer and a graphene layer in direct contact with the semiconductor layer, and the graphene layer includes a plurality of graphene islands spaced apart from each other.

The semiconductor layer may include one of silicon, an organic semiconductor, an amorphous oxide semiconductor, a two-dimensional transition metal chalcogenide, and a Group III/V compound semiconductor.

The semiconductor layer may include InZnO.

The semiconductor layer may have a thickness of about 1 to about 30 nm.

The plurality of graphene islands may be spaced apart from each other at a gap of about 1 nm to about 100 nm.

The plurality of graphene islands may include 1 to 3 layers of graphene.

The plurality of graphene islands may be between the gate insulating layer and the semiconductor layer.

According to example embodiments, a graphene electronic device includes a substrate, a channel layer on the substrate, a gate insulating layer on the channel layer, a gate electrode on the gate insulating layer, and a source electrode connected to one end of the channel layer and a drain electrode connected to another end of the channel layer. The channel layer includes a semiconductor layer and graphene layer in direct contact with the semiconductor layer, and the graphene layer includes a plurality of graphene islands spaced apart from each other.

According to example embodiments, a method of fabricating a graphene electronic device includes forming a gate insulating layer on a conductive substrate, placing a graphene sheet on the gate insulating layer, coating a semiconductor precursor solution onto the graphene sheet, heat-treating the substrate and the coated graphene sheet to form a graphene layer including a plurality of graphene islands, forming a semiconductor layer by oxidizing the semiconductor precursor solution, and forming a source electrode on one end of the semiconductor layer and the graphene layer and a drain electrode on another end of the semiconductor layer and the graphene layer.

DETAILED DESCRIPTION

FIG. 1is a cross-sectional view of a graphene electronic device100having a channel layer including graphene islands according to example embodiments.

Referring toFIG. 1, a gate insulating layer120may be on a conductive substrate110. One layer formed by a plurality of graphene islands132, hereinafter referred to as a graphene layer130, may be placed on the gate insulating layer120. A semiconductor layer140may be on the graphene layer130. A source electrode151and a drain electrode152may be placed at respective ends of the semiconductor layer140. The source electrode151and the drain electrode152may each be in contact with the semiconductor layer140.

The conductive substrate110may function as a gate electrode. The conductive substrate110may include silicon, electrode metal, indium tin oxide (ITO), etc.

The gate insulating layer120may include silicon oxide or silicon nitride. The gate insulating layer120may include a polymer, e.g., polydimethylsiloxane (PDMS) and polyurethane. The gate insulating layer120may have a thickness of about 100 nm to about 300 nm.

The plurality of graphene islands132may be spaced apart from each other by a predetermined or given gap G. The plurality of graphene islands132may be in contact with the semiconductor layer140. At least one gap G may be formed on the graphene layer130forming a current path between the source electrode151and the drain electrode152. The gap G may have a width of about 1 nm to about 100 nm. The plurality of graphene islands132may include 1 to 3 layers of graphene and have graphene characteristics. Graphene islands132may be placed between the gate insulating layer120and the semiconductor layer140.

FIG. 2is a plan view of graphene islands according to example embodiments.

Referring toFIG. 2, the plurality of graphene islands may be irregularly formed. When both sides of graphene islands are respectively connected to the source electrode and the drain electrode, the current path between the source electrode and the drain electrode may need to pass the gaps in the graphene islands.

Referring back toFIG. 1, the semiconductor layer140may include silicon, an organic semiconductor, an amorphous oxide semiconductor, a two-dimensional transition metal chalcogenide, and a Group III/V compound semiconductor.

The organic semiconductor may include pentacene.

The amorphous oxide semiconductor may be ZnO, ZnAlO, InZnO, or InGaZnO. The amorphous oxide semiconductor may be transparent and stable. Because the amorphous oxide semiconductor may form the semiconductor layer140by using a precursor in a solution state, a fabrication process of the graphene electronic device100may be relatively easy and a fabrication cost of the graphene electronic device may be reduced.

The graphene layer130and the semiconductor layer140may function as a channel layer of a field effect transistor (FET). The graphene layer130may have a relatively high mobility characteristic and the semiconductor layer140and the graphene layer130may form a Schottky barrier therebetween. Thus, a bandgap may be formed. Due to the bandgap, an on/off current ratio of the FET may increase.

The source electrode151and the drain electrode152may include materials well known in a semiconductor process and detailed descriptions thereof are omitted.

An operation of the graphene electronic device100is described below.

A predetermined or given voltage is applied between the source electrode151and the drain electrode152. Accordingly, an electron is generated at the source electrode151and moves towards the drain electrode152. The electron moves to an adjacent one of the graphene islands132through the semiconductor layer140in contact with the source electrode151. In order to pass the current path between the source electrode151and the drain electrode152, the electron that passed some of the graphene islands132needs to move to the semiconductor layer140and then, to other adjacent ones of the graphene islands132. However, the electron may not move from the graphene islands132to the semiconductor layer140due to the Schottky barrier between the graphene islands132and the semiconductor layer140.

When a predetermined or given turn-on voltage is applied to the conductive substrate110functioning as the gate electrode, the Schottky barrier is lowered and accordingly, the electron in the graphene islands132hops to the semiconductor layer140in contact with the graphene islands132. Then, the electron moves to other adjacent ones of the graphene islands132on the current path. When another, different graphene island of the graphene islands132exists on the current path, the electron repeats a movement described above and finally moves to the drain electrode152.

The graphene electronic device100according to example embodiments described above may function as a graphene transistor, however, example embodiments are not limited thereto. For example, the graphene electronic device100may be a sensor or a photo detector.

FIG. 3is a graph illustrating electrical characteristics of a graphene electronic device according to example embodiments. The channel layer of the graphene electronic device may include an InZnO (IZO) semiconductor layer formed by a solution process and graphene islands on the IZO semiconductor layer.

Referring toFIG. 3, the graphene electronic device may have a charge mobility of about 24.7 cm2V−1S−1, a conductivity of about 1.7×10−2mS, and an on/off current ratio of higher than about 106according to example embodiments.

FIG. 4is a graph illustrating electrical characteristics of a transistor having an IZO channel layer without a graphene layer, hereinafter referred to as a conventional transistor. The IZO channel layer may be fabricated by the solution process.

Referring toFIG. 4, the conventional transistor may have a charge mobility of about 3.7 cm2V−1S−1, a conductivity of about 2.1×10−3mS, and the on/off current ratio of higher than about 106.

According to example embodiments, a graphene electronic device may have charge mobility and conductivity about 10 times higher than those of the conventional transistor, and the on/off current ratio of the conventional transistor.

According to example embodiments, a graphene electronic device may have the on/off current ratio of the conventional transistor, but the charge mobility may increase by utilizing a graphene layer including a plurality of graphene islands. An increase in the charge mobility may result from using the graphene layer.

FIGS. 5A through 5Dare cross-sectional views illustrating a method of fabricating a graphene electronic device according to example embodiments. Like numerals are used to indicate like components as in the embodiment ofFIG. 1and detailed descriptions thereof are omitted.

Firstly, referring toFIG. 5A, a conductive substrate110including silicon may be prepared. A gate insulating layer120including silicon oxide may be formed on a surface of the conductive substrate110through a heat-treatment of the conductive substrate110.

Referring toFIG. 5B, a graphene sheet230may be transferred onto the gate insulating layer120. The graphene sheet230may include 1 to 3 layers of graphene. The graphene sheet230may be used by transferring graphene fabricated by a chemical vapor deposition (CVD) method. The graphene sheet230may be patterned to have a predetermined or given size.

An IZO precursor layer240may be fabricated on the graphene sheet230by coating a solution including IZO precursors onto the graphene sheet230using a spin coating method. An IZO precursor solution may be prepared by adding 0.03 mole of zinc acetate dihydrate [Zn(OAc)2.2H2O] and 0.03 mole of indium nitrate hydrate [In(NO3)3.4H2O] to 2-methoxyethanol [2ME, Aldrich, 98%] so that a molar ratio of indium (In) and zinc (Zn) is 1:1, and stirring the solution for about 1 hour. The IZO precursor layer240may have a thickness of about 30 nm to about 50 nm.

Referring toFIG. 5C, when the resulting structure may be under a heat-treatment at about 400° C. to about 500° C. for about 1 hour, oxygen may pass through the IZO precursor layer240to react with the graphene sheet230and a portion of the graphene sheet230may be removed. In other words, the graphene sheet230may be partially etched and graphene islands232may be formed as illustrated inFIG. 2. The graphene islands230may be spaced apart from each other by a predetermined or given gap G. The gap G may be about 1 nm to about 100 nm. The gap G may vary depending on a temperature of the heat-treatment, a duration of the heat-treatment, a material of the semiconductor layer and a thickness of the semiconductor layer.

During a process of the heat-treatment, the IZO precursor layer240may be oxidized to become an IZO semiconductor layer242. The IZO semiconductor layer242may have a thickness of about 20 nm.

Referring toFIG. 5D, the source electrode251and the drain electrode252may be formed at both ends of the IZO semiconductor layer242, after coating an electrode material (not shown) onto the substrate110and patterning the electrode material.

According to a method of fabricating a graphene electronic device of example embodiments, an IZO semiconductor layer may be fabricated by using a spin coating method and thus, the IZO semiconductor layer may be more easily fabricated, in comparison with fabricating the IZO semiconductor layer by using a conventional sputtering method.

In addition, when the IZO semiconductor layer is fabricated by an oxidation process, the graphene sheet may also be oxidized to form a plurality of graphene islands.

FIG. 6is a cross-sectional view illustrating a structure of a graphene electronic device having a channel layer including graphene islands according to example embodiments. Like numerals are used to indicate like components as in the embodiment ofFIG. 1and detailed descriptions thereof are omitted.

Referring toFIG. 6, a gate insulating layer120may be on a conductive substrate110. A semiconductor layer340may be on the gate insulating layer120. One layer including a plurality of graphene islands332, hereinafter referred to as a graphene layer330, may be placed on the semiconductor layer340. A source electrode351and a drain electrode352may be connected to both ends of the graphene layer330. A protective layer360may further be placed on the graphene layer330.

The plurality of graphene islands332may be spaced apart from each other by a predetermined or given gap G. The plurality of graphene islands332may be in contact with the semiconductor layer340. A width of the gap G may be about 1 nm to about 100 nm. The plurality of graphene islands332may include 1 to 3 layers of graphene and have characteristics of graphene.

The plurality of graphene islands332may be transferred onto the semiconductor layer340. However, example embodiments are not limited thereto. The plurality of graphene islands332may be fabricated by patterning a graphene sheet (not shown) after transferring the graphene sheet onto the semiconductor layer340. In addition, the plurality of graphene islands332may be fabricated by a heat-treatment of the graphene sheet.

The source electrode351and the drain electrode352may be in direct contact with the graphene islands332in the graphene electronic device300ofFIG. 6, and thus, a current path may be shorter than that of the graphene electronic device100of the example embodiment as illustrated inFIG. 1.

An operation of the graphene electronic device300inFIG. 6may be well known to one skilled in the art from the description of the graphene electronic device100inFIG. 1, and a detailed description is omitted.

FIG. 7is a cross-sectional view illustrating a structure of a graphene electronic device400having a channel layer including graphene islands according to example embodiments. Like numerals are used to indicate like components as in the embodiment ofFIG. 1and detailed descriptions are omitted.

Referring toFIG. 7, one layer including a plurality of graphene islands432, hereinafter referred to as a graphene layer430, may be placed on a substrate410. A semiconductor layer440may be on the graphene layer430. A source electrode451and a drain electrode452each connected to both ends of the semiconductor layer440may be placed on the substrate410. A gate insulating layer460and a gate electrode470may be sequentially placed on the semiconductor layer440.

The substrate410may be a non-conductive substrate. The substrate410may be formed of, for example, glass, plastic, polymer, etc. An insulating layer (not shown) may be further disposed between the substrate410and the graphene layer430. In this case, the substrate410may be a conductive substrate.

The plurality of graphene islands432may be spaced apart from each other by a predetermined or given gap G. The plurality of graphene islands432may be in contact with the semiconductor layer440. The gap G may have a width of about 1 nm to about 100 nm. The plurality of graphene islands432may include 1 to 3 layers of graphene and have characteristics of graphene.

The semiconductor layer440may include silicon, an organic semiconductor, an amorphous oxide semiconductor, a two-dimensional transition metal chalcogenide, or a III/V group compound semiconductor.

The organic semiconductor may include pentacene.

The amorphous oxide semiconductor may be ZnO, ZnAlO, InZnO, or InGaZnO. The amorphous oxide semiconductor may be transparent and stable. Since the amorphous oxide semiconductor may form the semiconductor layer440in a solution state, the fabrication cost may be reduced.

The graphene layer430and the semiconductor layer440may function as a channel layer of a FET. The graphene layer430may provide a characteristic of high mobility, and the semiconductor layer440and the graphene layer430may form a Schottky barrier therebetween and thus, provide a bandgap. Due to an existence of the bandgap, an on/off current ratio may increase.

The source electrode451and the drain electrode452may include materials well known in the semiconductor process, and a detailed description is omitted.

An operation of the graphene electronic device400inFIG. 7may be well known from the embodiments described above, and a detailed description is omitted.

FIG. 8is a cross-sectional view illustrating a structure of a graphene electronic device500having a channel layer including graphene islands according to example embodiments. Like numerals are used to indicate like components as in the embodiment ofFIG. 7and detailed descriptions are omitted.

Referring toFIG. 8, a semiconductor layer540may be on a substrate410. One layer including a plurality of graphene islands532, hereinafter referred to as a graphene layer530, may be placed on a semiconductor layer540. A source electrode451and a drain electrode452connected to both ends of the semiconductor layer540may be placed on the substrate410. A gate insulating layer460and a gate electrode470may be sequentially placed on the graphene layer530.

The substrate410may be a non-conductive substrate. The substrate410may be formed of, for example, glass, plastic, polymer, etc. An insulating layer (not shown) may be further disposed between the substrate410and the graphene layer530. In this case, the substrate410may be a conductive substrate.

Locations of the graphene layer530and the semiconductor layer540of the graphene electronic device500inFIG. 8are different from those of the graphene electronic device400inFIG. 7, however, operations of the graphene electronic device500may be well understood from the example embodiment described above, and a detailed description is omitted.