Clock stop detector

A clock stop detector for a memory comprises a first switch that closes in response to a first logic level of a clock signal to charge a capacitor, a second switch that closes in response to a second logic level of the clock signal to discharge the capacitor, and a logic circuit that outputs a control signal based on an inverted clock signal and a charge on the capacitor.

BACKGROUND

One type of memory known in the art is low power synchronous dynamic random access memory (SDRAM), which is also known as mobile random access memory (Mobile-RAM). Mobile-RAM is a low power synchronous DRAM designed especially for mobile applications, such as cellular telephones, personal digital assistants (PDAs), handheld computers, etc. Mobile-RAMs achieve high speed transfer rates by employing a chip architecture that pre-fetches multiple bits and then synchronizes the output data to a system clock.

Reducing the power consumption of portable electronic devices and thereby increasing the battery life of those portable electronic devices continues to be an area of focus in the development of portable electronic devices. Typically, the power consumption of portable electronic devices, including the power consumption of the memory utilized by those portable electronic devices, is a design concern since battery life is an important feature of portable electronic devices. In many portable electronic devices, the memory consumes power even when the memory is not being accessed by the portable electronic device.

SUMMARY

One embodiment of the invention provides a clock stop detector for a memory. The clock stop detector comprises a first switch that closes in response to a first logic level of a clock signal to charge a capacitor, a second switch that closes in response to a second logic level of the clock signal to discharge the capacitor, and a logic circuit that outputs a control signal based on an inverted clock signal and a charge on the capacitor.

DETAILED DESCRIPTION

FIG. 1is a block diagram illustrating one embodiment of a memory system30. Memory system30includes controller32and memory36. Controller32is electrically coupled to memory36through communication link34.

Controller32includes logic, firmware, and/or software for controlling the operation of memory36. In one embodiment, controller32is a microprocessor or other suitable device capable of passing a clock signal, address signals, command signals, and data signals to memory36through communication link34for reading data from and writing data to memory36. Controller32passes a clock signal, address signals, command signals, and data signals to memory36through communication link34to read data from and write data to memory36. Controller32starts and stops the clock signal passed to memory36to activate and deactivate portions of memory36, respectively. The clock is stopped to deactivate portions of memory36to conserve power when memory36is not being used.

Memory36includes circuits for communicating with controller32through communication link34and for reading and writing data in memory36. Memory36includes a random access memory (RAM), such as a dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), low power synchronous dynamic random access memory (Mobile-RAM), or other suitable memory. Memory36responds to memory read requests from controller32and passes the requested data to controller32. Memory36also responds to write requests from controller32and stores data in memory36passed from controller32.

To conserve power, controller32deactivates portions of memory36not being used by stopping the clock signal sent to memory36through communication link34. Memory36detects the stopped clock signal and deactivates portions of memory36. Controller32activates portions of memory36to be used by starting the clock signal sent to memory36through communication link34. Memory36detects the running clock signal and activates the previously deactivated portions of memory36.

FIG. 2is a block diagram illustrating one embodiment of memory36. Memory36includes a clock receiver40, an address receiver42, a command receiver44, a data receiver and driver46, a clock stop detector52, a peripheral circuit48, and an array of memory banks50.

Clock receiver40is electrically coupled to clock stop detector52and peripheral circuit48through signal path56. Address receiver42is electrically coupled to peripheral circuit48through signal path58. Command receiver44is electrically coupled to peripheral circuit48through signal path60. Data receiver and driver46is electrically coupled to peripheral circuit48through signal path62. Peripheral circuit48is electrically coupled to the array of memory banks50through address signal path64, control signal path66, and data signal path68. Clock stop detector52is electrically coupled to address receiver42, command receiver44, data receiver and driver46, and peripheral circuit48, through clock stop (CLKSTOP) signal path54.

Communication link34includes clock signal path34a,address signal path34b,command signal path34c,and data signal path34d.Clock signal path34ais electrically coupled to clock receiver40. Address signal path34bis electrically coupled to address receiver42. Command signal path34cis electrically coupled to command receiver44. Data signal path34dis electrically coupled to data receiver and driver46.

Clock receiver40receives a clock signal (CLK) and an inverted clock signal (/CLK) from controller32through signal path34a.In response to the CLK signal and /CLK signal, clock receiver40outputs an internal clock signal (iCLK) and an inverted internal clock signal (/iCLK) to clock stop detector52and peripheral circuit48through signal path56.

Clock stop detector52receives the iCLK signal and the /iCLK signal from clock receiver40. If the iCLK signal is active, i.e. the iCLK signal continues to transition between a logic high level and a logic low level at a specified frequency, clock stop detector52outputs a logic low on CLKSTOP signal path54. If the iCLK signal is not active, i.e. the iCLK signal remains at a logic high level or a logic low level, clock stop detector52outputs a logic high signal on CLKSTOP signal path54.

Address receiver42receives addresses from controller32through address signal path34bindicating the locations in the array of memory banks50into which data is to be stored or from which data is to be retrieved. Address receiver42also receives the CLKSTOP signal from clock stop detector52through CLKSTOP signal path54. If the CLKSTOP signal is at a logic high level, address receiver42is deactivated to conserve power by powering down its circuits. If the CLKSTOP signal is at a logic low level, address receiver42is activated for operation by powering up its circuits.

Command receiver44receives read and write commands for the array of memory banks50from controller32through command signal path34c.Command receiver44also receives the CLKSTOP signal from clock stop detector52through CLKSTOP signal path54. If the CLKSTOP signal is at a logic high level, command receiver44is deactivated to conserve power by powering down its circuits. If the CLKSTOP signal is at a logic low level, command receiver44is activated for operation by powering up its circuits.

Data receiver and driver46receives data signals for writing to the array of memory banks50from controller32through signal path34d.Data receiver and driver46also receives data for passing to controller32from the array of memory banks50through peripheral circuit48. In addition, data receiver and driver46receives the CLKSTOP signal from clock stop detector52through CLKSTOP signal path54. If the CLKSTOP signal is at a logic high level, data receiver and driver46is deactivated to conserve power by powering down its circuits. If the CLKSTOP signal is at a logic low level, data receiver and driver circuit46is activated for operation by powering up its circuits.

Peripheral circuit48receives the iCLK signal and /iCLK signal from clock receiver40through signal path56, memory addresses from address receiver42through signal path58, and memory read and memory write commands from command receiver44though signal path60. Peripheral circuit48sends and receives data signals from data receiver and driver46through signal path62. Peripheral circuit48sends and receives data from the array of memory banks50through data signal path68, sends memory addresses to the array of memory banks50through address signal path64, and sends control signals to the array of memory banks50through control signal path66.

Peripheral circuit48performs read and write operations to the array of memory banks50through address signal path64, control signal path66, and data signal path68. Peripheral circuit48also receives the CLKSTOP signal from clock stop detector52through CLKSTOP signal path54. If the CLKSTOP signal is at a logic high level, peripheral circuit48is deactivated to conserve power by powering down its circuits. If the CLKSTOP signal is at a logic low level, peripheral circuit48is activated for operation by powering up its circuits.

The array of memory banks50includes arrays of memory cells, sense amplifiers and decoders for reading and writing data to the memory cells in the array of memory banks50. Memory36can include RAM, DRAM, SDRAM, DDR SDRAM, Mobile-RAM, or other suitable memory.

The /iCLK signal path56bis electrically coupled to the active low gate of transistor104and the active high gate of transistor108. One side of the source-drain path of transistor104is electrically coupled to a power supply voltage (VDD)100through path102and the other side of the source-drain path of transistor104is electrically coupled to one side of the source-drain path of transistor108, capacitor120, and a first input of NOR gate126through Node A path118. The other side of the source-drain path of transistor108is electrically coupled to current source112through path110. Current source112is electrically coupled to a common or ground116through path114. Capacitor120is electrically coupled to common or ground116through path122. The iCLK signal path56ais electrically coupled to a second input of NOR gate126. The output of NOR gate126is electrically coupled to CLKSTOP signal path54.

Transistor104is a p-type metal oxide semi-conductor field effect transistor (MOSFET) or other suitable transistor or switch. Transistor108is an n-type MOSFET or other suitable transistor or switch.

In operation, with the /iCLK signal at a logic low level, transistor104is turned on (conducting) and transistor108is turned off (not conducting). With transistor104turned on, VDD100charges capacitor120through path102, transistor104, and Node A path118. With the /iCLK signal at a logic high level, transistor108is turned on (conducting) and transistor104is turned off (not conducting). With transistor108turned on, current source112discharges capacitor120through Node A path118, transistor108, and path110. The rate of charging and discharging of capacitor120is adjusted based on the iCLK signal frequency and by selecting different values for capacitor120and current source112. In one embodiment, capacitor120is charged in less than one cycle of the iCLK signal and discharged in more than one cycle of the iCLK signal.

NOR gate126outputs a logic high level on CLKSTOP signal path54if the iCLK signal on iCLK signal path56ais at a logic low level and the signal on Node A path118is also at a logic low level. In all other cases, NOR gate126outputs a logic low level on CLKSTOP signal path54. Therefore, a stopped clock is detected if the iCLK signal is at a logic low level and capacitor120discharges to the point where the signal on Node A transitions to a logic low level.

If the iCLK signal is active, capacitor120does not have enough time to discharge to the point where the signal on Node A path118transitions to a logic low level before capacitor120is charged again. The CLKSTOP signal on CLKSTOP signal path54remains at a logic low level. With the CLKSTOP signal at a logic low level, address receiver42, command receiver44, data receiver and driver46, and peripheral circuit48are activated.

If the iCLK signal is not active, however, then capacitor120can discharge to the point where the signal on Node A path118transitions to a logic low level. With the iCLK signal also at a logic low level, the CLKSTOP signal on CLKSTOP signal path54transitions to a logic high level. With the CLKSTOP signal at a logic high level, address receiver42, command receiver44, data receiver and driver46, and peripheral circuit48are deactivated.

FIG. 4is a timing diagram150illustrating one embodiment of the timing of signals of clock stop detector52. Timing diagram150includes the /iCLK signal on /iCLK signal path56b,the iCLK signal on iCLK signal path56a,the Node A signal on Node A path118, and the CLKSTOP signal on CLKSTOP signal path54. Timing diagram150is divided into sections152,154,156,158, and160.

In section152, the iCLK signal is active and transitions to a logic high level and the /iCLK signal transitions to a logic low level. Transistor108is turned off and transistor104is turned on by the logic low level of the /iCLK signal. Capacitor120is charged, resulting in a logic high level on Node A. With the iCLK signal at a logic high level and the signal on node A at a logic high level, the CLKSTOP signal is at a logic low level.

In section154, the iCLK signal remains active and transitions to a logic low level and the /iCLK signal transitions to a logic high level. Transistor104is turned off and transistor108is turned on by the logic high level of the /iCLK signal. Capacitor120begins to discharge, as indicated on the Node A signal at170. However, capacitor120does not discharge to the point where the node A signal transitions to a logic low level. Therefore, the CLKSTOP signal remains at a logic low level.

In section156, the iCLK signal remains active and returns to a logic high level and the /iCLK signal returns to a logic low level. Transistor108is turned off and transistor104is turned on by the logic low level of the /iCLK signal. Capacitor120is charged, resulting in a logic high level on Node A. With the iCLK signal at a logic high level and the signal on Node A at a logic high level, the CLKSTOP signal remains at a logic low level.

In section158, the iCLK signal becomes inactive at a logic low level and the /iCLK becomes inactive at a logic high level. Transistor104is turned off and transistor108is turned on by the logic high level of the /iCLK signal. Capacitor120discharges as indicated by the Node A signal at162. Capacitor120discharges to a point where the Node A signal transitions to a logic low level. At the point where the Node A signal transitions to a logic low level, the CLKSTOP signal transitions to a logic high level at164. The CLKSTOP signal164remains at a logic high level as long as the iCLK signal is inactive.

In section160, the iCLK signal returns to an active state. The iCLK signal transitions to a logic high level and the /iCLK signal transitions to a logic low level. Transistor108is turned off and transistor104is turned on by the logic low level of the /iCLK signal. Capacitor120is charged and the signal on Node A transitions to a logic high level at166. With the iCLK signal at a logic high level and the signal on Node A at a logic high level, the CLKSTOP signal transitions to a logic low level at168.

FIG. 5is a diagram illustrating one embodiment of a cellular telephone including controller32and memory36, according to the present invention. Cellular telephone200includes a housing202, an antenna206, a display204, buttons208, controller32, and memory36. Controller32is electrically coupled to memory36through communication link34. In other embodiments, cellular telephone200can be any portable electronic device, such as a personal digital assistant (PDA), handheld computer, music player, digital camera, portable game system, etc.

Cellular telephone200receives user commands and data through buttons208. Cellular telephone200stores data entered by a user and data used in the operation of cellular telephone200entered by other means, such as initial programming of cellular telephone200at the time of manufacture or through a computer or wireless interface, in memory36.

Cellular telephone200conserves power and thereby extends its battery life by deactivating portions of memory36when those portions are not being used. In one embodiment, controller32is configured to output a clock signal to memory36that starts and stops in response to user commands, such as user commands that turn off the cellular phone or place the cellular phone in a low power mode. Clock stop detector52of memory36deactivates portions of memory36to conserve power if the clock signal is inactive and activates portions of memory36for operation if the clock signal is active.