METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS

A method of forming a microelectronic device includes forming a first dielectric stack over a semiconductor base structure including pillar structures separated by filled isolation trenches. Digit line contacts are formed to partially vertically extend through the first dielectric stack and into digit line contact regions of the pillar structures. Digit lines are formed over and in contact with the digit line contacts, and partially vertically extend through the first dielectric stack. A second dielectric stack is formed over the digit lines and the first dielectric stack. Storage node contacts are formed to vertically extend partially through the second dielectric stack, completely through the first dielectric stack, and into storage node contact regions of the pillar structures. Redistribution layer structures are formed over and in contact with the storage node contacts, and partially vertically extend through the second dielectric stack. Microelectronic devices, memory devices, and electronic systems are also described.

TECHNICAL FIELD

The disclosure, in various embodiments, relates generally to the field of microelectronic device design and fabrication. More specifically, the disclosure relates to methods of forming microelectronic devices, and to related microelectronic devices, memory devices, and electronic systems.

BACKGROUND

Microelectronic device designers often desire to increase the level of integration or density of features within a microelectronic device by reducing the dimensions of the individual features and by reducing the separation distance between neighboring features. In addition, microelectronic device designers often desire to design architectures that are not only compact, but offer performance advantages, as well as simplified designs.

A relatively common microelectronic device is a memory device. A memory device may include a memory array having a number of memory cells arranged in a grid pattern. One type of memory cell is a dynamic random access memory (DRAM). In the simplest design configuration, a DRAM cell includes one access device, such as a transistor, and one storage device, such as a capacitor. Modern applications for memory devices can utilize vast numbers of DRAM unit cells, arranged in an array of rows and columns. The DRAM cells are electrically accessible through digit lines and word lines arranged along the rows and columns of the array.

Reducing the dimensions and spacing of memory device features places ever increasing demands on the methods used to form the memory device features. For example, DRAM device manufacturers face a tremendous challenge on reducing the DRAM cell area as feature spacing decreases to accommodate increased feature density. Conventional approaches to reducing spacing between neighboring digit lines often reduce margin for error (e.g., alignment errors), and can result in undesirable shorts and/or undesirable capacitive coupling effects without complex and time-consuming feature alignment methodologies.

DETAILED DESCRIPTION

The following description provides specific details, such as material compositions, shapes, and sizes, in order to provide a thorough description of embodiments of the disclosure. However, a person of ordinary skill in the art would understand that the embodiments of the disclosure may be practiced without employing these specific details. Indeed, the embodiments of the disclosure may be practiced in conjunction with conventional microelectronic device fabrication techniques employed in the industry. In addition, the description provided below does not form a complete process flow for manufacturing a microelectronic device (e.g., a memory device). The structures described below do not form a complete microelectronic device. Only those process acts and structures necessary to understand the embodiments of the disclosure are described in detail below. Additional acts to form a complete microelectronic device from the structures may be performed by conventional fabrication techniques.

As used herein, a “memory device” means and includes microelectronic devices exhibiting memory functionality, but not necessarily limited to memory functionality. Stated another way, and by way of non-limiting example only, the term “memory device” includes not only conventional memory (e.g., conventional non-volatile memory; conventional volatile memory), but also includes an application specific integrated circuit (ASIC) (e.g., a system on a chip (SoC)), a microelectronic device combining logic and memory, and a graphics processing unit (GPU) incorporating memory.

As used herein, the terms “configured” and “configuration” refers to a size, a shape, a material composition, a material distribution, orientation, and arrangement of at least one feature (e.g., one or more of at least one structure, at least one material, at least one region, at least one device) facilitating use of the at least one feature in a pre-determined way.

As used herein, the terms “vertical,” “longitudinal,” “horizontal,” and “lateral” are in reference to a major plane of a structure and are not necessarily defined by earth's gravitational field. A “horizontal” or “lateral” direction is a direction that is substantially parallel to the major plane of the structure, while a “vertical” or “longitudinal” direction is a direction that is substantially perpendicular to the major plane of the structure. The major plane of the structure is defined by a surface of the structure having a relatively large area compared to other surfaces of the structure. With reference to the drawings, a “horizontal” or “lateral” direction may be perpendicular to an indicated “Z” axis, and may be parallel to an indicated “X” axis and/or parallel to an indicated “Y” axis; and a “vertical” or “longitudinal” direction may be parallel to an indicated “Z” axis, may be perpendicular to an indicated “X” axis, and may be perpendicular to an indicated “Y” axis.

As used herein, features (e.g., structures, materials, regions, devices) described as “neighboring” one another means and includes features of the disclosed identity (or identities) that are located most proximate (e.g., closest to) one another. Additional features (e.g., additional regions, additional structures, additional devices) not matching the disclosed identity (or identities) of the “neighboring” features may be disposed between the “neighboring” features. Put another way, the “neighboring” features may be positioned directly adjacent one another, such that no other feature intervenes between the “neighboring” features; or the “neighboring” features may be positioned indirectly adjacent one another, such that at least one feature having an identity other than that associated with at least one the “neighboring” features is positioned between the “neighboring” features. Accordingly, features described as “vertically neighboring” one another means and includes features of the disclosed identity (or identities) that are located most vertically proximate (e.g., vertically closest to) one another. Moreover, features described as “horizontally neighboring” one another means and includes features of the disclosed identity (or identities) that are located most horizontally proximate (e.g., horizontally closest to) one another.

As used herein, the phrase “coupled to” refers to structures operatively connected with each other, such as electrically connected through a direct Ohmic connection or through an indirect connection (e.g., by way of another structure).

As used herein, “insulative material” means and includes electrically insulative material, such one or more of at least one dielectric oxide material (e.g., one or more of a silicon oxide (SiOx), phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, an aluminum oxide (AlOx), a hafnium oxide (HfOx), a niobium oxide (NbOx), a titanium oxide (TiOx), a zirconium oxide (ZrOx), a tantalum oxide (TaOx), and a magnesium oxide (MgOx)), at least one dielectric nitride material (e.g., a silicon nitride (SiNy)), at least one dielectric oxynitride material (e.g., a silicon oxynitride (SiOxNy)), at least one dielectric oxycarbide material (e.g., silicon oxycarbide (SiOxCy)), at least one hydrogenated dielectric oxycarbide material (e.g., hydrogenated silicon oxycarbide (SiCxOyHz)), and at least one dielectric carboxynitride material (e.g., a silicon carboxynitride (SiOxCzNy)). Formulae including one or more of “x,” “y,” and “z” herein (e.g., SiOx, AlOx, HfOx, NbOx, TiOx, SiNy, SiOxNy, SiOxCy, SiCxOyHz, SiOxCzNy) represent a material that contains an average ratio of “x” atoms of one element, “y” atoms of another element, and “z” atoms of an additional element (if any) for every one atom of another element (e.g., Si, Al, Hf, Nb, Ti). As the formulae are representative of relative atomic ratios and not strict chemical structure, an insulative material may comprise one or more stoichiometric compounds and/or one or more non-stoichiometric compounds, and values of “x,” “y,” and “z” (if any) may be integers or may be non-integers. As used herein, the term “non-stoichiometric compound” means and includes a chemical compound with an elemental composition that cannot be represented by a ratio of well-defined natural numbers and is in violation of the law of definite proportions. In addition, an “insulative structure” means and includes a structure formed of and including insulative material.

As used herein, the term “semiconductor material” refers to a material having an electrical conductivity between those of insulative materials and conductive materials. For example, a semiconductor material may have an electrical conductivity of between about 10-8 Siemens per centimeter (S/cm) and about 104S/cm (106S/m) at room temperature. Examples of semiconductor materials include elements found in column IV of the periodic table of elements such as silicon (Si), germanium (Ge), and carbon (C). Other examples of semiconductor materials include compound semiconductor materials such as binary compound semiconductor materials (e.g., gallium arsenide (GaAs)), ternary compound semiconductor materials (e.g., AlXGa1-XAs), and quaternary compound semiconductor materials (e.g., GaXIn1-XAsYP1-Y), without limitation. Compound semiconductor materials may include combinations of elements from columns III and V of the periodic table of elements (III-V semiconductor materials) or from columns II and VI of the periodic table of elements (II-VI semiconductor materials), without limitation. Further examples of semiconductor materials include oxide semiconductor materials such as zinc tin oxide (ZnxSnyO, commonly referred to as “ZTO”), indium zinc oxide (InxZnyO, commonly referred to as “IZO”), zinc oxide (ZnxO), indium gallium zinc oxide (InxGayZnyO, commonly referred to as “IGZO”), indium gallium silicon oxide (InxGaySizO, commonly referred to as “IGSO”), indium tungsten oxide (InxWyO, commonly referred to as “IWO”), indium oxide (InxO), tin oxide (SnxO), titanium oxide (TixO), zinc oxide nitride (ZnxONz), magnesium zinc oxide (MgxZnyO), zirconium indium zinc oxide (ZrxInyZnzO), hafnium indium zinc oxide (HfxInyZnzO), tin indium zinc oxide (SnxInyZnzO), aluminum tin indium zinc oxide (AlxSnyInzZnaO), silicon indium zinc oxide (SixInyZnzO), aluminum zinc tin oxide (AlxZnySnzO), gallium zinc tin oxide (GaxZnySnzO), zirconium zinc tin oxide (ZrxZnySnzO), and other similar materials.

As used herein, the term “homogeneous” means relative amounts of elements included in a feature (e.g., a material, a structure) do not vary throughout different portions (e.g., different horizontal portions, different vertical portions) of the feature. Conversely, as used herein, the term “heterogeneous” means relative amounts of elements included in a feature (e.g., a material, a structure) vary throughout different portions of the feature. If a feature is heterogeneous, amounts of one or more elements included in the feature may vary stepwise (e.g., change abruptly), or may vary continuously (e.g., change progressively, such as linearly, parabolically) throughout different portions of the feature. The feature may, for example, be formed of and include a stack of at least two different materials.

Unless the context indicates otherwise, the materials described herein may be formed by any suitable technique including, but not limited to, spin coating, blanket coating, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), plasma enhanced ALD (PEALD), physical vapor deposition (PVD) (e.g., sputtering), or epitaxial growth. Depending on the specific material to be formed, the technique for depositing or growing the material may be selected by a person of ordinary skill in the art. In addition, unless the context indicates otherwise, removal of materials described herein may be accomplished by any suitable technique including, but not limited to, etching (e.g., dry etching, wet etching, vapor etching), ion milling, abrasive planarization (e.g., chemical-mechanical planarization (CMP)), or other known methods.

FIGS.1A through11Bare simplified, partial longitudinal cross-sectional views (FIGS.1A,2A,3A,4A,5A,6A,7A,8A,9A,10A, and11A) and simplified, partial top-down views (FIGS.1B,2B,3B,4B,5B,6B,7B,8B,9B,10B, and11B) of a microelectronic device structure (e.g., a memory device structure, such as a DRAM structure) at different processing stages of a method of forming a microelectronic device (e.g., a memory device, such as a DRAM device), in accordance with embodiments of the disclosure. With the description provided below, it will be readily apparent to one of ordinary skill in the art that the methods described herein may be used to form various microelectronic devices, such as to form microelectronic devices where three-dimensional (3D) scaling is advantageous.

Referring toFIG.1A, a microelectronic device structure100may be formed to include a base semiconductor structure102, and filled trenches106vertically extending into the base semiconductor structure102. The filled trenches106horizontally surround and at least partially define pillar structures104of the base semiconductor structure102. The microelectronic device structure100may further include additional filled trenches107embedded within and horizontally extending through the pillar structures104and the filled trenches106, word line structures108(e.g., access line structures, word lines, access lines) within the additional filled trenches107, and insulative line structures110(e.g., word line capping structures, access line capping structures) within the additional filled trenches107and vertically overlying the word line structures108. In addition, the microelectronic device structure100may include a first dielectric material112vertically overlying the base semiconductor structure102, a second dielectric material114vertically overlying the first dielectric material112, and a third dielectric material116vertically overlying the second dielectric material114. The first dielectric material112, the second dielectric material114, and the third dielectric material116may together form a first dielectric stack (e.g., a first stack of dielectric materials, a first dielectric stack structure) over the pillar structures104, the filled trenches106, and the additional filled trenches107.FIG.1Bis a top-down view of microelectronic device structure100at the processing stage shown inFIG.1A, wherein a line A-A corresponds to the longitudinal cross-section of the microelectronic device structure100depicted inFIG.1A. For clarity in understanding the drawings and related description, some features (e.g., structures, materials, regions) of the microelectronic device structure100at the processing stage ofFIGS.1A and1Bthat are depicted inFIG.1Aare not depicted inFIG.1B, and vice versa. For example, to better illustrate the pillar structures104, the filled trenches106, and the word line structures108inFIG.1B, each of the insulative line structures110, the first dielectric material112, the second dielectric material114, and the third dielectric material116depicted inFIG.1Aare omitted from (i.e., are not depicted in)FIG.1B. However, it will be understood that any feature depicted in at least one ofFIGS.1A and1Bmay be included in the microelectronic device structure100at the processing stage ofFIGS.1A and1B.

The base semiconductor structure102comprises a base material or construction upon which additional features (e.g., materials, structures, devices) of the microelectronic device structure100are formed. The base semiconductor structure102may comprise a semiconductor structure (e.g., a semiconductor wafer), or a base semiconductor material on a supporting structure. For example, the base semiconductor structure102may comprise a conventional silicon substrate (e.g., a conventional silicon wafer), or another bulk substrate comprising a semiconductor material. In some embodiments, the base semiconductor structure102comprises a silicon wafer. The base semiconductor structure102may include one or more layers, structures, and/or regions formed therein and/or thereon.

The pillar structures104may individually vertically extend (e.g., project) from a relatively lower portion of the base semiconductor structure102that horizontally extends across and between the pillar structures104. The pillar structures104may be formed of and include semiconductor material (e.g., silicon, such as polycrystalline silicon) of the base semiconductor structure102, and may be considered so-called “active” regions of the base semiconductor structure102. The filled trenches106may be horizontally interposed between the pillar structures104of the base semiconductor structure102, as described in further detail below. In addition, the pillar structures104of the base semiconductor structure102may vertically extend beyond upper boundaries of the word line structures108, and at least to upper boundaries of the insulative line structures110, as also described in further detail below.

Referring collectively toFIGS.1A and1B, the pillar structures104may individually exhibit an elongate (e.g., non-circular, non-square) horizontal cross-sectional shape (seeFIG.1B) at least partially defined by the horizontal cross-sectional shapes of the filled trenches106horizontally adjacent thereto. The pillar structures104may individually include an upper surface, opposing horizontal ends, and opposing horizontal sides extending form and between the opposing ends. Intersections of the opposing horizontal ends of an individual pillar structure104with the opposing horizontal sides of the pillar structure104may define horizontal corners of the pillar structure104. As shown inFIG.1A, the upper surfaces of the pillar structures104may be substantially coplanar with one another. In addition, an individual pillar structure104may include a digit line contact region104A (e.g., bit line contact region) and storage node contact regions104B (e.g., cell contact regions). As shown inFIG.1B, the storage node contact regions104B of the pillar structure104may be located proximate the opposing horizontal ends of the pillar structure104, and the digit line contact region104A may be horizontally interposed between the storage node contact regions104B. The digit line contact region104A may be positioned at or proximate a horizontal center of the pillar structure104. In some embodiments, as depicted inFIG.1B, the digit line contact region104A of an individual pillar structure104is horizontally narrower (e.g., in the X-direction) than each of the storage node contact regions104B of the pillar structure104. The digit line contact region104A and the storage node contact regions104B of an individually pillar structure104may be separated from one another by a pair of the additional filled trenches107, as described in further detail below. Furthermore, as shown inFIG.1B, for two (2) of pillar structures104horizontally neighboring one another in the X-direction, the digit line contact region104A of one of the pillar structures104may horizontally overlap, in the Y-direction, one of the storage node contact regions104B of the other of the pillar structures104.

With continued reference toFIGS.1A and1B, the pillar structures104are separated from one another by the filled trenches106. The filled trenches106may, for example, be employed as shallow trench isolation (STI) structures within the base semiconductor structure102. A vertical height (e.g., in the Z-direction) of the pillar structures104may correspond to (e.g., be the same as) as vertical height (e.g., in the Z-direction) of the filled trenches106. As shown inFIG.1B, some of the filled trenches106may be positioned adjacent the opposing horizontal ends of the pillar structures104, and may horizontally extend in substantially linear paths; and others of the filled trenches106may be positioned adjacent the opposing horizontal sides of the pillar structures104, and may horizontally extend in substantially non-linear paths (e.g., wavy paths). The some of the filled trenches106may horizontally intersect the others of the filled trenches106at or proximate horizontal corners of the pillar structures104.

The filled trenches106may comprise trenches in the base semiconductor structure102filled, at least in part, with at least one insulative material, such as one or more of at least one dielectric oxide material (e.g., one or more of SiOx, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlOx, HfOx, NbOx, and TiOx), at least one dielectric nitride material (e.g., SiNy), at least one dielectric oxynitride material (e.g., SiOxNy), at least one dielectric carboxynitride material (e.g., SiOxCzNy), and amorphous carbon. In some embodiments, the insulative material of the filled trenches106comprises SiOx(e.g., SiO2). The insulative material of the filled trenches106may be substantially homogeneous, or the insulative material of the filled trenches106may be heterogeneous.

Still referring toFIGS.1A and1B, the additional filled trenches107may vertically overlap and horizontally extend through the pillar structures104and the filled trenches106. In some embodiments, the additional filled trenches107horizontally extend in substantially linear paths. For example, the referring toFIG.1B, the additional filled trenches107may horizontally extend in parallel with one another in the X-direction, as represented by the paths of the word line structures108depicted inFIG.1B(since the word line structures108are positioned within horizontal areas of the additional filled trenches107). As used herein, the term “parallel” means substantially parallel.

Within a horizontal area of an individual pillar structure104, portions of two (2) of the additional filled trenches107may be separate (e.g., isolate) the storage node contact regions104B of pillar structure104from the digit line contact region104A of the pillar structure104. The portions of the two (2) of the additional filled trenches107may be horizontally interposed between the digit line contact region104A and the storage node contact regions104B, and may partially define horizontal boundaries of the digit line contact region104A and the storage node contact regions104B.

As shown inFIG.1A, the additional filled trenches107may be formed to vertically extend to and terminate at different depths (e.g., vertical elevations) within the base semiconductor structure102than the filled trenches106. For example, the additional filled trenches107may vertically extend to and terminate at relatively shallower depths within the base semiconductor structure102than the filled trenches106. In addition, each of the additional filled trenches107may be formed to exhibit substantially the same horizontal dimension(s) and substantially the same horizontal cross-sectional shape(s) as each other of the additional filled trenches107; or at least one of the additional filled trenches107may be formed to exhibit one or more of different horizontal dimension(s) (e.g., relatively larger horizontal dimension(s), relatively smaller horizontal dimension(s)) and different horizontal cross-sectional shape(s) than at least one other of the additional filled trenches107.

The additional filled trenches107may comprise trenches in the pillar structures104and the filled trenches106filled, in part, with at least one additional insulative material, such as one or more of at least one dielectric oxide material (e.g., one or more of SiOx, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlOx, HfOx, NbOx, and TiOx), at least one dielectric nitride material (e.g., SiNy), at least one dielectric oxynitride material (e.g., SiOxNy), at least one dielectric carboxynitride material (e.g., SiOxCzNy), and amorphous carbon. A material composition of the additional insulative material of the additional filled trenches107may be substantially the same as a material composition of the insulative material of the filled trenches106, or the material composition of the additional insulative material of the additional filled trenches107may be different than the material composition of the insulative material of the filled trenches106. In some embodiments, the additional insulative material of the additional filled trenches107comprises SiOx(e.g., SiO2). The additional insulative material of the additional filled trenches107may be substantially homogeneous, or the additional insulative material of the additional filled trenches107may be heterogeneous.

With continued reference toFIGS.1A and1B, the word line structures108may be formed within the additional filled trenches107. In some embodiments, the word line structures108are employed as word line structures (e.g., access line structures) of the microelectronic device structure100. As shown inFIG.1B, the word line structures108may exhibit horizontally elongate shapes extending in parallel in the X-direction (FIG.1B). An individual word line structure108may continuously horizontally extend across (and be shared by) multiple of the pillar structures104. Within a horizontal area of an individual pillar structure104, portions of two (2) of the word line structures108may be horizontally interposed between the digit line contact region104A of the pillar structure104and the storage node contact regions104B of the pillar structure104. As shown inFIG.1A, uppermost surfaces of the word line structures108may vertically underlie uppermost surfaces of the pillar structures104.

The word line structures108may individually be formed of and include conductive material, such as one or more of at least one metal, at least one an alloy, at least one conductive metal-containing material, and at least one conductively doped semiconductor material. In some embodiments, the word line structures108are individually formed of and include tungsten (W). The word line structures108may each be substantially homogeneous, or more or more of the word line structures108may individually be heterogeneous.

As shown inFIG.1A, additional insulative material of the additional filled trenches107may be interposed between the word line structures108and the pillar structures104. The additional insulative material of the additional filled trenches107may substantially cover at least side surfaces and bottom surfaces of the word line structures108. The additional insulative material of the additional filled trenches107may intervene between the word line structures108and the digit line contact regions104A and the storage node contact regions104B of the pillar structures104. In some embodiments, the additional insulative material of the additional filled trenches107is employed as a gate dielectric material (e.g., a gate oxide material) for access devices (e.g., transistors) formed to include the pillar structures104and the word line structures108.

Referring toFIG.1A, the insulative line structures110may be formed within the additional filled trenches107, and may be vertically interposed between the word line structures108and the first dielectric material112. In some embodiments, the insulative line structures110are employed as word line capping structures (e.g., access line capping structures) of the microelectronic device structure100. The insulative line structures110may exhibit horizontally elongate shapes extending in parallel in the X-direction (FIG.1B) and corresponding to the horizontally elongate shapes of the word line structures108vertically thereunder. An individual insulative line structures110may continuously horizontally extend across multiple of the pillar structures104. Within a horizontal area of an individual pillar structure104, portions of two (2) of the insulative line structures110may be horizontally interposed between the digit line contact region104A of the pillar structure104and the storage node contact regions104B of the pillar structure104. As shown inFIG.1A, uppermost surfaces of the insulative line structures110may be substantially coplanar with uppermost surfaces of the pillar structures104.

The insulative line structures110may individually be formed of insulative material, such as one or more of a dielectric oxide material (e.g., silicon dioxide; phosphosilicate glass; borosilicate glass; borophosphosilicate glass; fluorosilicate glass; aluminum oxide; a combination thereof), a dielectric nitride material (e.g., SiNy), a dielectric an oxynitride material (e.g., SiOxNy), a dielectric carbonitride material (e.g., SiCxNy), and a dielectric carboxynitride material (e.g., SiOxCyNz), and amorphous carbon. In some embodiments, the insulative line structures110are individually formed of and include silicon nitride (e.g., SiNy, such as Si3N4). In additional embodiments, the insulative line structures110are individually formed of and include silicon oxide (e.g., SiOx, such as SiO2). The insulative line structures110may individually be substantially homogeneous, or one or more of the insulative line structures110may be heterogeneous.

Still referring toFIG.1A, the first dielectric material112may be formed on or over the pillar structures104, the filled trenches106, and the additional filled trenches107(including the insulative line structures110therein). The first dielectric material112may substantially cover uppermost surfaces of the pillar structures104, the filled trenches106, and the insulative line structures110within the additional filled trenches107. The first dielectric material112may be formed of and include one or more of at least one dielectric oxide material (e.g., one or more of SiOx, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlOx, HfOx, NbOx, and TiOx), at least one dielectric nitride material (e.g., SiNy), at least one dielectric oxynitride material (e.g., SiOxNy), and at least one dielectric carboxynitride material (e.g., SiOxCzNy). In some embodiments, the first dielectric material112is formed of and includes dielectric oxide material (e.g., SiOx, such as SiO2). The first dielectric material112may be formed to have a desirable vertical height (e.g., in the Z-direction), such as a vertical height within a range of from about 5 nanometers (nm) to about 15 nm, from about 7 nm to about 12 nm, or about 10 nm.

The second dielectric material114may be formed on or over the first dielectric material112. The second dielectric material114may substantially cover an uppermost surface of the first dielectric material112. A material composition of the second dielectric material114is different than a material composition of the first dielectric material112. The material composition of the second dielectric material114may be selected such that the second dielectric material114has etch selectivity relative to the first dielectric material112. For example, if the first dielectric material112is formed of and includes dielectric oxide material (e.g., SiOx, such as SiO2), the second dielectric material114may not be formed of and include dielectric oxide material. In some embodiments, the second dielectric material114is formed of and includes dielectric nitride material (e.g., SiNy, such as Si3N4). The second dielectric material114may be formed to have a desirable vertical height (e.g., in the Z-direction), such as a vertical height within a range of from about 1 nm to about 10 nm, from about 3 nm to about 7 nm, or about 5 nm.

The third dielectric material116may be formed on or over the second dielectric material114. The third dielectric material116may substantially cover an uppermost surface of the second dielectric material114. A material composition of the third dielectric material116is different than the material composition of the second dielectric material114. The material composition of the third dielectric material116may be substantially the same as or may be different than the material composition of the first dielectric material112. The material composition of the third dielectric material116may be selected such that the second dielectric material114has etch selectivity relative to the third dielectric material116. For example, if the second dielectric material114is formed of and includes dielectric nitride material (e.g., SiNy, such as Si3N4), the third dielectric material116may not be formed of and include dielectric nitride material. In some embodiments, the third dielectric material116is formed of and includes dielectric oxide material (e.g., SiOx, such as SiO2). The third dielectric material116may be formed to have a desirable vertical height (e.g., in the Z-direction), such as a vertical height within a range of from about 25 nm to about 35 nm, from about 27 nm to about 32 nm, or about 30 nm.

Referring next toFIG.2A, a first hardmask structure118may be formed on or over the third dielectric material116, and initial digit line contact openings128may be formed to vertically extend through the first hardmask structure118, the third dielectric material116, the second dielectric material114, and the first dielectric material112and into the pillar structures104of the base semiconductor structure102. As described in further detail below, the initial digit line contact openings128may be formed to horizontally overlap the digit line contact regions104A of the pillar structures104.FIG.2Bis a top-down view of the microelectronic device structure100at the processing stage shown inFIG.2A, wherein the line A-A corresponds to the longitudinal cross-section of the microelectronic device structure100depicted inFIG.2A. For clarity in understanding the drawings and related description, some features (e.g., structures, materials, regions) of the microelectronic device structure100at the processing stage ofFIGS.2A and2Bthat are depicted inFIG.2Aare not depicted inFIG.2B, and vice versa. However, it will be understood that any feature depicted in at least one ofFIGS.2A and2Bmay be included in the microelectronic device structure100at the processing stage ofFIGS.2A and2B.

The first hardmask structure118may be formed to comprise a multi-layered lithography stack. For example, as shown inFIG.2A, the first hardmask structure118may be formed to include a first underlayer (UL) material120on or over the third dielectric material116, a first developable anti-reflective coating (DARC) material122on or over the first UL material120, a first resist adhesion layer (RAL) material124on or over the first DARC material122, and a first extreme ultraviolet (EUV) resist material126on or over the first RAL material124. The foregoing features of the first hardmask structure118are described in further detail below.

The first UL material120of the first hardmask structure118may be formed of and include at least one material having desirable adhesion and planarization characteristics. A material composition of the first UL material120may be selected, at least in part, based on material compositions of the third dielectric material116and the first DARC material122. The first UL material120may, for example, be formed of and include one or more of an organic material (e.g., an organic spin-on material), an inorganic oxide material, and an inorganic nitride material. In some embodiments, the first UL material120is formed of and includes a carbon-containing material (e.g., amorphous carbon). The first UL material120may be formed to have a desirable vertical height (e.g., in the Z-direction), such as a vertical height within a range of from about 50 nm to about 100 nm, from about 60 nm to about 90 nm, from about 75 nm to about 85 nm, or about 80 nm.

The first DARC material122may be formed of and include at least one material formulated to reduce reflections and improve pattern transfer during lithography processes. In some embodiments, the first DARC material122is formed of and includes an Si-rich DARC material including a relatively high concentration of silicon. By way of non-limiting example, the first DARC material122may be formed of and include one or more of an SiOx-based DARC material including a relatively high concentration of SiOx; an SiNy-based DARC material including a relatively high concentration of SiNy; a SiCOH-based DARC material including a combination of silicon, carbon, oxygen, and hydrogen; and/or a SiCN-based DARC including a combination of silicon, carbon, and nitrogen. The first DARC material122may be formed to have a desirable vertical height (e.g., in the Z-direction), such as a vertical height within a range of from about 10 nm to about 25 nm, from about 10 nm to about 15 nm, or about 10 nm.

The first RAL material124may be formed of and include at least one material formulated to enhance adhesion of the first EUV resist material126to the first DARC material122. A material composition of the first RAL material124may be selected, at least in part, based on material compositions of the first EUV resist material126and the first DARC material122. The first RAL material124may, for example, be formed of and include one or more of ruthenium (Ru), zirconium (Zr), titanium (Ti), and a carbon-based material (e.g., amorphous carbon). The first RAL material124may be formed to have a desirable vertical height (e.g., in the Z-direction), such as a vertical height within a range of from about 5 nm to about 10 nm, from about 5 nm to about 7 nm, or about 5 nm.

The first EUV resist material126may be formed of and include at least one photoresist material formulated for EUV lithography (e.g., lithography utilizing EUV radiation having a wavelength of around 13.5 nm). The first EUV resist material126may, for example, be formed of and include one or more of a chemically amplified (CA) photoresist including a polymer matrix and a photoacid generator (PAG); a non-chemically amplified (NCA) photoresist substantially free of any PAGs; a hybrid photoresist including a combination of CA and NCA photoresist materials; and an inorganic photoresist including metal oxides or other inorganic materials. The first EUV resist material126may be formed to have a desirable vertical height (e.g., in the Z-direction), such as a vertical height within a range of from about 5 nm to about 10 nm, from about 5 nm to about 7 nm, or about 5 nm.

With continued reference toFIG.2A, the initial digit line contact openings128may be formed to individually vertically extend completely through the first EUV resist material126, the first RAL material124, the first DARC material122, the first UL material120, the third dielectric material116, the second dielectric material114, and the first dielectric material112; and partially through the pillar structures104of the base semiconductor structure102. An individual initial digit line contact opening128may expose (e.g., uncover) the digit line contact region104A of an individual pillar structure104of the base semiconductor structure102. A lower boundary (e.g., floor, bottom) of an individual initial digit line contact openings128may vertically underlie uppermost surfaces of the base semiconductor structure102and insulative line structures110(and, hence, a lowermost boundary of the first dielectric material112). For an individual pillar structure104of the base semiconductor structure102, after forming the initial digit line contact openings128, the digit line contact region104A of the pillar structure104may be vertically recessed relative to the storage node contact regions104B of the pillar structure104. An upper boundary (e.g., top) of the digit line contact region104A of the pillar structure104may vertically underlie the upper boundaries (e.g., tops) of the storage node contact regions104B of the pillar structure104.

Referring collectively toFIGS.2A and2B, the initial digit line contact openings128may be substantially horizontally centered about the digit line contact regions104A of the pillar structures104. As shown inFIG.2B, an individual initial digit line contact opening128may be horizontally interposed between two (2) of the word line structures108(and, hence, two (2) of the additional filled trenches107(FIG.2A)) neighboring one another in the Y-direction; may be horizontally interposed between two (2) of the filled trenches106neighboring one another in the X-direction; and may be horizontally interposed between two (2) of the storage node contact regions104B of an individual pillar structure104in an additional horizontal direction angled relative to the Y-direction and the X-direction. In addition, a pitch P1(FIG.2B) between initial digit line contact openings128neighboring one another in the Y-direction may be greater than an additional pitch P2(FIG.2B) between word line structures108neighboring one another in the Y-direction. In some embodiments, the pitch P1between initial digit line contact openings128is greater than or equal to (e.g., substantially equal to) about 1.5 times (1.5×) the additional pitch P2between the word line structures108. In some embodiments, the pitch P1between initial digit line contact openings128neighboring one another in the Y-direction is within a range of from about 20 nm to about 40 nm, such as from about 24 nm to about 36 nm.

The initial digit line contact openings128may individually be formed to have a desirable geometric configuration (e.g., dimensions, such as horizontal dimensions and vertical dimension(s); shape, such as horizontal cross-sectional shape(s) and vertical cross-sectional shape(s)). The geometric configuration of an individual initial digit line contact opening128may at least partially depend on the geometric configurations and spacing of other features (e.g., the pillar structures104, the filled trenches106, the word line structures108) of the microelectronic device structure100that neighbor the initial digit line contact opening128. In some embodiments, the initial digit line contact openings128are formed to individually exhibit a substantially cylindrical shape. A horizontal width (e.g., horizontal dimeter) of an individual initial digit line contact openings128may, for example, be within a range of from about 9 nm to about 30 (e.g., from about 9 nm to about 20 nm). In addition, the initial digit line contact openings128may individually vertically terminate at a desirable depth from an uppermost boundary (e.g., an uppermost surface) of the base semiconductor structure102, such as a vertical depth within a range of from about 30 nm to about 50 nm (e.g., from about 35 nm to about 45 nm, or about 40 nm) from the uppermost boundary of the base semiconductor structure102. The initial digit line contact openings128may individually vertically terminate (e.g., in the Z-direction) above uppermost boundaries of the word line structures108, such as between uppermost boundaries and lowermost boundaries of the insulative line structures110. Each of the initial digit line contact openings128may be formed to exhibit substantially the geometric configuration (e.g., substantially the same dimensions, and substantially same shape) as each other of the initial digit line contact openings128, or at least one of the initial digit line contact openings128may be formed to exhibit a different geometric configuration (e.g., different dimension(s) and/or a different shape) than at least one other of the initial digit line contact openings128.

The initial digit line contact openings128may be formed using a material removal process employing EUV lithography. A desirable pattern for the initial digit line contact openings128may be formed in the first EUV resist material126using EUV lithography, and then the resulting pattern in the first EUV resist material126may be transferred into a remainder of the first hardmask structure118and the pillar structures104using an etching (e.g., ion beam etching) process to form the initial digit line contact openings128. In some embodiments, patterning of the first EUV resist material126using EUV lithography includes a single exposure to EUV radiation (e.g., a single EUV print) to form a pattern for the initial digit line contact openings128. The single exposure to EUV radiation may, for example, form a pattern of features (e.g., photoexposed regions) in the first EUV resist material126with feature pitch corresponding to the pitch P1(e.g., within a range of from about 20 nm to about 40 nm, such as from about 24 nm to about 36 nm). In some embodiments, a critical dimension of an individual feature in the first EUV resist material126following exposure to the EUV radiation is within a range of from about 15 nm to about 20 nm, such as about 18 nm. Following the subsequent etching (e.g., ion beam etching) process, a critical dimension of an individual initial digit line contact opening128may be relatively smaller than the critical dimension of an individual feature in the first EUV resist material126. In some embodiments, the critical dimension of an individual initial digit line contact opening128is at least about two (2) nm smaller than (e.g., within a range of from about 2 nm to about 8 nm, from about 3 nm to about 7 nm, from about 4 nm to about 6 nm, or about 5 nm) the associated feature (e.g., photoexposed region) initially formed in the first EUV resist material126by way of EUV lithography.

Referring next toFIG.3A, first sacrificial structures130may be formed within the initial digit line contact openings128(FIGS.2A and2B), and the first hardmask structure118(FIG.2A) may be removed. Following the removal of the first hardmask structure118(FIG.2A), uppermost boundaries (e.g., uppermost surfaces) of the first sacrificial structures130may be substantially coplanar with an uppermost boundary (e.g., an uppermost surface) of the third dielectric material116.FIG.3Bis a top-down view of the microelectronic device structure100at the processing stage shown inFIG.3A, wherein the line A-A corresponds to the longitudinal cross-section of the microelectronic device structure100depicted inFIG.3A. For clarity in understanding the drawings and related description, some features (e.g., structures, materials, regions) of the microelectronic device structure100at the processing stage ofFIGS.3A and3Bthat are depicted inFIG.3Aare not depicted inFIG.3B, and vice versa. However, it will be understood that any feature depicted in at least one ofFIGS.3A and3Bmay be included in the microelectronic device structure100at the processing stage ofFIGS.3A and3B.

The first sacrificial structures130may be formed of and include a sacrificial material that is selectively etchable relative at least to the pillar structures104, insulative line structures110, the first dielectric material112, the second dielectric material114, and the third dielectric material116. In some embodiments, the first sacrificial structures130are formed of and include a carbon-containing material (e.g., a carbon-based material), such as amorphous carbon.

To form the first sacrificial structures130, sacrificial material (e.g., carbon-containing material) may be formed inside and outside of the initial digit line contact openings128(FIG.2A), and then portions of the first hardmask structure118(FIG.2A) and the sacrificial material may be removed (e.g., through a CMP process).

Referring next toFIG.4A, a second hardmask structure132may be formed on or over the third dielectric material116and the first sacrificial structures130, and linear mask openings142may be formed to vertically extend through the second hardmask structure132to expose (e.g., uncover) the first sacrificial structures130and portions of the third dielectric material116. As described in further detail below, the linear mask openings142may individually be formed to horizontally overlap multiple of the first sacrificial structures130.FIG.4Bis a top-down view of the microelectronic device structure100at the processing stage shown inFIG.4A, wherein the line A-A corresponds to the longitudinal cross-section of the microelectronic device structure100depicted inFIG.4A. For clarity in understanding the drawings and related description, some features (e.g., structures, materials, regions) of the microelectronic device structure100at the processing stage ofFIGS.4A and4Bthat are depicted inFIG.4Aare not depicted inFIG.4B, and vice versa. However, it will be understood that any feature depicted in at least one ofFIGS.4A and4Bmay be included in the microelectronic device structure100at the processing stage ofFIGS.4A and4B.

The second hardmask structure132may be formed to comprise an additional multi-layered lithography stack. For example, as shown inFIG.4A, the second hardmask structure132may be formed to include a second UL material134on or over the third dielectric material116, a second DARC material136on or over the second UL material134, a second RAL material138on or over the second DARC material136, and a second EUV resist material140on or over the second RAL material138. The foregoing features of the second hardmask structure132are described in further detail below.

The second UL material134of the second hardmask structure132may be formed of and include at least one material having desirable adhesion and planarization characteristics. A material composition of the second UL material134may be selected, at least in part, based on material compositions of the third dielectric material116and the second DARC material136. The material composition of the second UL material134may be substantially the same as or may be different than the material composition of the first UL material120(FIG.2A) of the first hardmask structure118(FIG.2A). In some embodiments, the second UL material134is formed of and includes a carbon-containing material (e.g., amorphous carbon). The second UL material134may be formed to have a desirable vertical height (e.g., in the Z-direction), such as a vertical height within a range of from about 20 nm to about 50 nm, from about 25 nm to about 35 nm, or about 30 nm.

The second DARC material136may be formed of and include at least one material formulated to reduce reflections and improve pattern transfer during lithography processes. A material composition of the second DARC material136may be substantially the same as or may be different than the material composition of the first DARC material122(FIG.2A) of the first hardmask structure118(FIG.2A). In some embodiments, the second DARC material136is formed of and includes an Si-rich DARC material including a relatively high concentration of silicon. The second DARC material136may be formed to have a desirable vertical height (e.g., in the Z-direction), such as a vertical height within a range of from about 10 nm to about 25 nm, from about 10 nm to about 15 nm, or about 10 nm.

The second RAL material138may be formed of and include at least one material formulated to enhance adhesion of the first EUV resist material126to the second DARC material136. A material composition of the second RAL material138may be selected, at least in part, based on material compositions of the second EUV resist material140and the second DARC material136. The material composition of the second RAL material138may be substantially the same as or may be different than the material composition of the first RAL material124(FIG.2A) of the first hardmask structure118(FIG.2A). The second RAL material138may be formed to have a desirable vertical height (e.g., in the Z-direction), such as a vertical height within a range of from about 5 nm to about 10 nm, from about 5 nm to about 7 nm, or about 5 nm.

The second EUV resist material140may be formed of and include at least one photoresist material formulated for EUV lithography (e.g., lithography utilizing EUV radiation having a wavelength of around 13.5 nm). A material composition of the second EUV resist material140may be substantially the same as or may be different than the material composition of the first EUV resist material126(FIG.2A) of the first hardmask structure118(FIG.2A). The second EUV resist material140may be formed to have a desirable vertical height (e.g., in the Z-direction), such as a vertical height within a range of from about 10 nm to about 60 nm, from about 20 nm to about 50 nm, or about 40 nm.

Referring collectively toFIGS.4A and4B, the linear mask openings142may individually be formed to vertically extend completely through the second hardmask structure132to upper boundaries (e.g., upper surfaces) of multiple first sacrificial structures130and portions of the third dielectric material116. As shown inFIG.4B, the linear mask openings142may horizontally extend in parallel with one another in the Y-direction, and may be separated from one another in the X-direction by remaining portions of the second hardmask structure132. As described in further detail below, the formation of the linear mask openings142may facilitate the subsequent formation of conductive contact structures (e.g., digit line contact structures) and conductive line structures (e.g., digit line structures) for the microelectronic device structure100by way of a damascene process.

A vertical height (e.g., in the Z-direction) of each of the linear mask openings142may correspond to (e.g., be substantially the same as) a vertical height of the second hardmask structure132. By way of non-limiting example, an individual linear mask opening142may have a vertical height be within a range from about 45 nm to about 150 nm, such as from about 50 nm to about 140 nm.

Referring toFIG.4B, horizontal widths and positions in the X-direction of the linear mask openings142may at least partially depend on horizontal widths and positions in the X-direction of the first sacrificial structures130(and, hence, of the digit line contact regions104A of the pillar structures104of the base semiconductor structure102). Each of the linear mask openings142may have a horizontal width and a horizontal position permitting a horizontal center, in the X-direction, of the linear mask opening142to be substantially horizontally aligned with a horizontal center, in the X-direction, of one or more (e.g., a column of) of the first sacrificial structures130. A ratio of the horizontal width, in the X-direction, of an individual linear mask opening142to the horizontal width, in the X-direction, of an individual first sacrificial structure130may be within range of from about 0.5:1 to about 3.0:1, such as from about 1:1 to about 2:1, about 1:1. Each of the linear mask openings142may, for example, be formed to have a horizontal width, in the X-direction, within a range of from about 5 nm to about 15, such as from about 7 nm to about 15 nm, from about 7 nm to about 12 nm, or from about 7 nm to about 10 nm. In addition, a pitch between two linear mask openings142horizontally neighboring one another in the X-direction may be within a range of from about 20 nm to about 40 nm, such as from about 20 nm to about 35 nm, or from about 25 nm to about 35 nm.

The linear mask openings142may be formed using a material removal process employing EUV lithography. A desirable pattern for the linear mask openings142may be formed in the second EUV resist material140using EUV lithography, and then the resulting pattern in the second EUV resist material140may be transferred into a remainder of the second hardmask structure132(including the second RAL material138, the second DARC material136, and the second UL material134thereof) using an etching (e.g., ion beam etching) process to form the linear mask openings142. In some embodiments, patterning of the second EUV resist material140using EUV lithography includes a single exposure to EUV radiation (e.g., a single EUV print) to form a pattern for the linear mask openings142. The single exposure to EUV radiation may, for example, form a pattern of features (e.g., photoexposed regions) in the second EUV resist material140with feature pitch within a range of from about 20 nm to about 40 nm, such as from about 24 nm to about 36 nm. In some embodiments, a critical dimension of an individual feature in the second EUV resist material140following exposure to the EUV radiation is within a range of from about 15 nm to about 20 nm, such as about 18 nm. Following the subsequent etching (e.g., ion beam etching) process, a critical dimension of an individual linear mask openings142may be relatively smaller than the critical dimension of an individual feature in the second EUV resist material140. In some embodiments, the critical dimension of an individual linear mask opening142is a least about 5 nm smaller than the associated feature (e.g., photoexposed region) initially formed in the second EUV resist material140by way of EUV lithography.

Referring next toFIG.5A, a pattern of the linear mask openings142(FIGS.4A and4B) may be extended into the third dielectric material116and upper portions of the first sacrificial structures130(FIGS.4A and4B) to form digit line trenches144(e.g., bit line trenches, data line trenches); remaining portions of the second hardmask structure132(FIGS.4A and4B) may be removed; and remaining portions (e.g., lower portions) of the first sacrificial structures130may be removed to from digit line contact openings146(e.g., bit line contact openings, data line contact openings) integral and continuous with the digit line trenches144. The digit line trenches144may vertically terminate at or within vertical boundaries of the second dielectric material114. The digit line contact openings146may vertically extend from the digit line trenches144to upper boundaries (e.g., upper surfaces) of the pillar structures104within horizontal areas of the digit line contact regions104A thereof. The digit line trenches144and the first contact openings146may, in combination, expose the digit line contact regions104A of the pillar structures104, as described in further detail below.FIG.5Bis a top-down view of the microelectronic device structure100at the processing stage shown inFIG.5A, wherein the line A-A corresponds to the longitudinal cross-section of the microelectronic device structure100depicted inFIG.5A. For clarity in understanding the drawings and related description, some features (e.g., structures, materials, regions) of the microelectronic device structure100at the processing stage ofFIGS.5A and5Bthat are depicted inFIG.5Aare not depicted inFIG.5B, and vice versa. However, it will be understood that any feature depicted in at least one ofFIGS.5A and5Bmay be included in the microelectronic device structure100at the processing stage ofFIGS.5A and5B.

Referring collectively toFIGS.5A and5B, the digit line trenches144may individually be formed to vertically extend completely through the third dielectric material116(FIG.5A) and to or into the second dielectric material114(FIG.5A). Horizontal dimensions and a pattern of the digit line trenches144may respectively correspond to (e.g., may be substantially the same as) the horizontal dimensions and the pattern of the linear mask openings142(FIGS.4A and4B) formed in the second hardmask structure132(FIGS.4A and4B) at the processing stage ofFIGS.4A and4B. As shown inFIG.5B, the digit line trenches144may horizontally extend in parallel with one another in the Y-direction.

Following the formation of the digit line trenches144, remaining portions of the second hardmask structure132(FIGS.4A and4B) and the first sacrificial structures130(FIGS.4A and4B) may be removed (e.g., through a stripping and cleaning process). The removal of the remaining portions of the first sacrificial structures130forms the digit line contact openings146. Horizontal dimensions and a pattern of the digit line contact openings146may respectively correspond to (e.g., may be substantially the same as) the horizontal dimensions and the pattern of the first sacrificial structures130(FIGS.4A and4B).

Referring next toFIG.6A, a first spacer material148may be formed (e.g., substantially conformally formed) to extend continuously on or over surfaces of the microelectronic device structure100defining the digit line trenches144and the digit line contact openings146, and then portions of at least the first spacer material148at bottoms of the digit line contact openings146(FIGS.5A and5B) may be removed (e.g., by way of so-called “punch through” etching) to expose the digit line contact regions104A of the pillar structures104. As shown inFIG.6A, the material removal process may also remove upper portions of the digit line contact regions104A of the pillar structures104, to form extended digit line contact openings150from the digit line contact openings146(FIGS.5A and5B).FIG.6Bis a top-down view of the microelectronic device structure100at the processing stage shown inFIG.6A, wherein the line A-A corresponds to the longitudinal cross-section of the microelectronic device structure100depicted inFIG.6A. For clarity in understanding the drawings and related description, some features (e.g., structures, materials, regions) of the microelectronic device structure100at the processing stage ofFIGS.6A and6Bthat are depicted inFIG.6Aare not depicted inFIG.6B, and vice versa. However, it will be understood that any feature depicted in at least one ofFIGS.6A and6Bmay be included in the microelectronic device structure100at the processing stage ofFIGS.6A and6B.

As shown inFIG.6A, the first spacer material148partially (e.g., less than completely) fills the digit line contact openings146(FIGS.5A and5B) and the digit line trenches144. The first spacer material148may substantially completely cover surfaces of the microelectronic device structure100defining the digit line trenches144and the digit line contact openings146. The first spacer material148may serve as an isolation material for conductive structures (e.g., digit line structures, digit line contact structures) subsequently formed in remaining (e.g., unfilled) portions of the digit line trenches144and the digit line contact openings146, as described in further detail below.

The first spacer material148may be formed of and include dielectric material. In some embodiments, the first spacer material148is formed of and includes a dielectric nitride material (e.g., SiNy, such as Si3N4). In additional embodiments, the first spacer material148is formed of and includes at least one low-K (low-dielectric constant) dielectric material, such as one or more of silicon oxycarbide (SiOxCy), silicon oxynitride (SiOxNy), hydrogenated silicon oxycarbide (SiCxOyHz), and silicon oxycarbonitride (SiOxCzNy). In addition, the first spacer material148may be formed to have a thickness within a range of from about 1 nm to about 5 nm, such as from about 2 nm to about 4 nm, or from about 2 nm to about 3 nm.

Following the formation of the first spacer material148, portions thereof at lower boundaries (e.g., bottoms) of the digit line contact openings146(FIGS.5A and5B) may be removed, while at least partially (e.g., substantially) maintaining additional portions thereof at side boundaries (e.g., sides) of the digit line contact openings146(FIGS.5A and5B). In some embodiments, the removal process also partially removes portions of the pillar structures104within horizontal areas of the digit line contact regions104A. As shown inFIG.6A, lowermost boundaries of the resulting extended digit line contact openings150may vertically overlie uppermost boundaries of the word line structures108. For example, the lowermost boundaries of the extended digit line contact openings150may be positioned within vertical boundaries (e.g., between uppermost boundaries and lowermost boundaries) of the insulative line structures110. In some embodiments, the lowermost boundaries of the extended digit line contact openings150are vertically offset from (e.g., vertically overlie) the uppermost boundaries of the word line structures108by greater than or equal to about 10 nm.

Referring next toFIG.7A, digit line contact structures152(e.g., bit line contact structures, data line contact structures) may be formed within the extended digit line contact openings150(FIGS.6A and6B), and digit line structures160(e.g., bit line structures, data line structures) may be formed over the digit line contact structures152and within the digit line trenches144(FIGS.6A and6B). An individual digit line structure160may be integral and continuous (e.g., unitary) with multiple (e.g., a column of) digit line contact structures152.FIG.7Bis a top-down view of the microelectronic device structure100at the processing stage shown inFIG.7A, wherein the line A-A corresponds to the longitudinal cross-section of the microelectronic device structure100depicted inFIG.7A. For clarity in understanding the drawings and related description, some features (e.g., structures, materials, regions) of the microelectronic device structure100at the processing stage ofFIGS.7A and7Bthat are depicted inFIG.7Aare not depicted inFIG.7B, and vice versa. However, it will be understood that any feature depicted in at least one ofFIGS.7A and7Bmay be included in the microelectronic device structure100at the processing stage ofFIGS.7A and7B.

Referring toFIG.7A, the digit line contact structures152may individually be formed to include a first portion154(e.g., a lower portion) vertically overlying the digit line contact region104A of an individual pillar structure104; a second portion156(e.g., a middle portion) vertically overlying the first portion154; and a third portion158(e.g., an upper portion) vertically overlying the second portion156. The first portion154may directly physically contact the digit line contact region104A of the pillar structure104, the third portion158may directly physically contact an individual digit line structure160, and the second portion156may vertically extend from and between the first portion154and the third portion158. A geometric configuration (e.g., shape, dimensions) of an individual digit line contact structure152may substantially correspond to (e.g., may be substantially the same as) a geometric configuration of the remainder (e.g., remaining portion following the formation of the first spacer material148) of the extended digit line contact opening150(FIGS.6A and6B) within which the digit line contact structure152is formed.

The first portion154of an individual digit line contact structure152may be formed of and include epitaxial semiconductor material, such as epitaxial polycrystalline silicon. The first portion154of the digit line contact structure152may be epitaxially grown from semiconductor material of the digit line contact region104A of the pillar structure104in contact therewith. For an individual digit line contact structure152, an upper boundary of the first portion154thereof may be vertically positioned below, at, or above the uppermost boundaries of the insulative line structures110. In some embodiments, upper boundaries of the first portions154of the digit line contact structures152are vertically positioned at or above the uppermost boundaries of the insulative line structures110.

The second portion156of an individual digit line contact structure152may be formed of and include metal silicide material, such as one or more of cobalt silicide (CoSix), tungsten silicide (WSix), tantalum silicide (TaSix), molybdenum silicide (MoSix), nickel silicide (NiSix), and titanium silicide (TiSix). For an individual digit line contact structure152, an upper boundary of the second portion156thereof may be vertically positioned below a lowermost boundary of the second dielectric material114, such as between the lowermost boundary of the second dielectric material114and the uppermost boundaries of the insulative line structures110.

The third portion158of an individual digit line contact structure152may be formed of and include conductive material, such as one or more of at least one elemental metal (e.g., W, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pd, Pt, Cu, Ag, Au, Al), at least one alloy (e.g., a Co-based alloy, an Fe-based alloy, an Ni-based alloy, an Fe- and Ni-based alloy, a Co- and Ni-based alloy, an Fe- and Co-based alloy, a Co- and Ni- and Fe-based alloy, an Al-based alloy, a Cu-based alloy, a magnesium (Mg)-based alloy, a Ti-based alloy, a steel, a low-carbon steel, a stainless steel), and a conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal carbide, a conductive metal oxide). In some embodiments, the third portion158is formed of and includes elemental metal, such as one or more of Ru, Mo, Ti, and W. For an individual digit line contact structure152, an upper boundary of the third portion158thereof may be vertically positioned above the lowermost boundary of the second dielectric material114and below, at, or above an uppermost boundary of the second dielectric material114.

Still referring toFIG.7A, the digit line structures160may substantially fill portions of the digit line trenches144(FIGS.6A and6B) remaining unfilled following formation of the first spacer material148. A geometric configuration (e.g., shape, dimensions) of an individual digit line structure160may substantially correspond to (e.g., may be substantially the same as) a geometric configuration of the remainder (e.g., remaining portion following the formation of the first spacer material148) of the digit line trenches144(FIGS.6A and6B) within which the digit line structures160is formed. As shown inFIG.7B, the digit line structures160may exhibit horizontally elongate shapes, and may horizontally extend in parallel with one another in the Y-direction (and, hence, orthogonal to the word line structures108horizontally extending in parallel with one another in the X-direction).

The digit line structures160may individually be formed of and include conductive material, such as one or more of at least one elemental metal (e.g., W, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pd, Pt, Cu, Ag, Au, Al), at least one alloy (e.g., a Co-based alloy, an Fe-based alloy, an Ni-based alloy, an Fe- and Ni-based alloy, a Co- and Ni-based alloy, an Fe- and Co-based alloy, a Co- and Ni- and Fe-based alloy, an Al-based alloy, a Cu-based alloy, a magnesium (Mg)-based alloy, a Ti-based alloy, a steel, a low-carbon steel, a stainless steel), and a conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal carbide, a conductive metal oxide). A material composition of the digit line structures160may be substantially the same as a material composition of the third portions158of the digit line contact structures152. In some embodiments, the digit line structures160are individually formed of and include elemental metal, such as one or more of Ru, Mo, Ti, and W. As shown inFIG.7A, for an individual digit line structure160, an upper boundary thereof may be formed to be substantially coplanar with an uppermost boundary of the third dielectric material116.

To form the digit line contact structures152and the digit line structures160, epitaxial semiconductor material (e.g., epitaxial polycrystalline silicon) may be epitaxially grown within the extended digit line contact openings150(FIGS.6A and6B) and then etched back to form the first portions154of the digit line contact structures152. Thereafter conductive material may be formed inside and outside of remainders of the extended digit line contact openings150(FIGS.6A and6B) and the digit line trenches144(FIGS.6A and6B), and subjected to thermal processing (e.g., rapid thermal processing (RTP)) to form the second portions156of the digit line contact structures152. A wet cleaning process may then be performed, followed by the formation of additional conductive material inside and outside of new remainders of the extended digit line contact openings150(FIGS.6A and6B) and the digit line trenches144(FIGS.6A and6B) to form the third portions158of the digit line contact structures152. Thereafter portions of the conductive material (if any) and the additional conductive material overlying an uppermost boundary (e.g., an uppermost surface) of the third dielectric material116may be removed (e.g., by way of a CMP process) to expose the third dielectric material116and form the digit line structures160.

Referring next toFIG.8A, an additional mask structure162(e.g., an additional hardmask structure) may be formed on or over the third dielectric material116and the digit line structures160; and storage node contact openings168(e.g., cell contact openings) may be formed to vertically extend through the additional mask structure162, the third dielectric material116, the second dielectric material114, and the first dielectric material112and into the pillar structures104of the base semiconductor structure102. As described in further detail below, the storage node contact openings168may be formed to horizontally overlap the storage node contact regions104B of the pillar structures104.FIG.8Bis a top-down view of the microelectronic device structure100at the processing stage shown inFIG.8A, wherein the line A-A corresponds to the longitudinal cross-section of the microelectronic device structure100depicted inFIG.8A. For clarity in understanding the drawings and related description, some features (e.g., structures, materials, regions) of the microelectronic device structure100at the processing stage ofFIGS.8A and8Bthat are depicted inFIG.8Aare not depicted inFIG.8B, and vice versa. However, it will be understood that any feature depicted in at least one ofFIGS.8A and8Bmay be included in the microelectronic device structure100at the processing stage ofFIGS.8A and8B.

Referring toFIG.8A, the additional mask structure162may be formed to include a fourth dielectric material164on or over the digit line structures160and the third dielectric material116; and a fifth dielectric material166on or over the fourth dielectric material164. The fourth dielectric material164and the fifth dielectric material166of the additional mask structure162may together form a second dielectric stack (e.g., a second stack of dielectric materials, a second dielectric stack structure). As described in further detail below, first portions of the additional mask structure162, including first portions of the fourth dielectric material164and the fifth dielectric material166thereof, may substantially horizontally extend over and cover the digit line structures160; and second portions of the additional mask structure162, including second portions of the fourth dielectric material164and the fifth dielectric material166thereof, may horizontally extend over and cover portions of the third dielectric material116within horizontal areas of the filled trenches106.

The fourth dielectric material164may be formed of and include at least one dielectric material that substantially mitigates oxidation of the digit line structures160. For example, the fourth dielectric material164may be formed of includes at least one dielectric nitride material (e.g., SiNy, such as Si3N4). In some embodiments, the fourth dielectric material164is formed of and includes dielectric nitride material formed at relatively lower temperatures (e.g., temperatures less than or equal to about 400° C., such as less than or equal to about 350° C.) than those employed to form the fifth dielectric material166. The fourth dielectric material164may be formed to have a desirable vertical height (e.g., in the Z-direction), such as a vertical height within a range of from about 5 nm to about 15 nm, from about 7 nm to about 12 nm, or about 10 nm.

The fifth dielectric material166may be formed to substantially cover an uppermost surface of the fourth dielectric material164. A material composition of the fifth dielectric material166may be substantially the same as or may be different than a material composition of the fourth dielectric material164. For example, the fifth dielectric material166may be formed of includes at least one dielectric nitride material (e.g., SiNy, such as Si3N4). In some embodiments, the fifth dielectric material166is formed of and includes dielectric nitride material formed at relatively higher temperatures (e.g., temperatures greater than about 400° C., such as greater than or equal to about 600° C.) than those employed to form the fourth dielectric material164. The fifth dielectric material166may be formed to have a desirable vertical height (e.g., in the Z-direction), such as a vertical height within a range of from about 15 nm to about 25 nm, from about 17 nm to about 22 nm, or about 20 nm.

Referring toFIG.8B, the additional mask structure162may be patterned (e.g., through a single pitch patterning process; or through a multiple pitch patterning process, such as a double pitch patterning process) to include first portions individually extending substantially linearly in the Y-direction, and second portions extending substantially linearly an additional horizontal direction angled relative to each of the Y-direction and the X-direction. The first portions of the additional mask structure162may substantially cover and protect the digit line structures160(FIG.8A), and may form first opposing horizontal boundaries (e.g., first opposing side boundaries) for individual storage node contact openings168. The second portions of the additional mask structure162may horizontally intersect the first portions of the additional mask structure162, and may form second opposing horizontal boundaries (e.g., second opposing side boundaries) for individual storage node contact openings168. In some embodiments, horizontal centers, in the X-direction, of the first portions of the additional mask structure162are substantially aligned with horizontal centers, in the X-direction, of the digit line structures160(FIG.8A); and horizontal centers, in the additional horizontal direction angled relative to the X-direction and the Y-direction, of the second portions of the additional mask structure162are substantially aligned with horizontal centers, in the additional horizontal direction, of some of the filled trenches106(FIG.8A). The first portions and the second portions of the additional mask structure162may together establish the horizontal boundaries and horizontal positions of the storage node contact openings168, to ensure the storage node contact openings168horizontally overlap the storage node contact regions104B of the pillar structures104but do not horizontally overlap the digit line contact regions104A of the pillar structures104.

With returned reference toFIG.8A, the storage node contact openings168may be formed to individually vertically extend completely through the fifth dielectric material166, the fourth dielectric material164, the third dielectric material116, the second dielectric material114, and the first dielectric material112; and partially through the pillar structures104of the base semiconductor structure102. An individual storage node contact opening168may expose (e.g., uncover) one of the storage node contact regions104B of an individual pillar structure104of the base semiconductor structure102. A lower boundary (e.g., floor, bottom) of an individual storage node contact opening168may vertically underlie uppermost surfaces of the insulative line structures110(and, hence, a lowermost boundary of the first dielectric material112). For an individual pillar structure104of the base semiconductor structure102, after forming the storage node contact openings168, the storage node contact region104B of the pillar structure104may each be vertically recessed relative to the insulative line structures110. Upper boundaries (e.g., tops) of the storage node contact regions104B of the pillar structure104may be vertically positioned below, at, or above the upper boundary (e.g., top) of the digit line contact region104A of the pillar structure104. In some embodiments, the upper boundaries of the storage node contact regions104B of the pillar structure104(and, hence, the lower boundaries of the storage node contact openings168) are vertically positioned at or above the upper boundary of the digit line contact region104A of the pillar structure104.

Referring collectively toFIGS.8A and8B, the storage node contact openings168horizontally overlap the storage node contact regions104B of the pillar structures104. As shown inFIG.8B, an individual storage node contact opening168may be horizontally interposed between two (2) of the word line structures108(and, hence, two (2) of the additional filled trenches107(FIG.8A)) neighboring one another in the Y-direction; may be horizontally interposed between two (2) of the filled trenches106neighboring one another in the X-direction; and may horizontally neighbor the digit line contact region104A of an individual pillar structure104in an additional horizontal direction angled relative to the Y-direction and the X-direction.

The storage node contact openings168may individually be formed to have a desirable geometric configuration (e.g., dimensions, such as horizontal dimensions and vertical dimension(s); shape, such as horizontal cross-sectional shape(s) and vertical cross-sectional shape(s)). The geometric configuration of an individual storage node contact opening168may at least partially depend on the geometric configuration of the additional mask structure162, as well as the geometric configurations and spacing of other features (e.g., the digit line structures160, the digit line contact structures152, the pillar structures104, the filled trenches106, the word line structures108) of the microelectronic device structure100that neighbor the storage node contact opening168. As shown inFIG.8B, the storage node contact openings168may be formed to individually exhibit an elongate horizontal cross-sectional shape, such as an elongate, quadrilateral horizontal cross-sectional shape. In some embodiments, the storage node contact openings168are formed to individually exhibit a parallelogram horizontal cross-sectional shape. The parallelogram horizontal cross-sectional shape may include two sides having different horizontal dimensions than two other sides, or may include four sides all having substantially the same horizontal dimensions as one another. In addition, angles defined by corners of the parallelogram horizontal cross-sectional shape individually be greater than or less than 90 degrees (e.g., may not be right angles). The elongate horizontal cross-sectional shape may facilitate desirable exposure (e.g., substantial exposure) of the storage node contact regions104B (FIG.8A) of the pillar structures104(FIG.8A). In addition, the storage node contact openings168may individually vertically terminate at a desirable depth from an uppermost boundaries (e.g., an uppermost surfaces) of the insulative line structures110, such as a vertical depth within a range of from about 30 nm to about 50 nm (e.g., from about 35 nm to about 45 nm, or about 40 nm) from the uppermost boundaries of the insulative line structures110. The storage node contact openings168may individually vertically terminate (e.g., in the Z-direction) above the uppermost boundaries of the word line structures108, such as between uppermost boundaries and lowermost boundaries of the insulative line structures110. Each of the storage node contact openings168may be formed to exhibit substantially the geometric configuration (e.g., substantially the same dimensions, and substantially same shape) as each other of the storage node contact openings168, or at least one of the storage node contact openings168may be formed to exhibit a different geometric configuration (e.g., different dimension(s) and/or a different shape) than at least one other of the storage node contact openings168.

The storage node contact openings168may be formed using a material removal process employing EUV lithography. EUV lithography may be used to form a desirable pattern for the storage node contact openings168in an additional EUV resist material initially formed over the additional mask structure162, and then the resulting pattern may be transferred into the additional mask structure162, the third dielectric material116, the second dielectric material114, the first dielectric material112, and the pillar structures104using an etching (e.g., ion beam etching) process to form the storage node contact openings168. Portions of the additional EUV resist material remaining (if any) following the etching process may subsequently be removed.

Referring next toFIG.9A, a second spacer material170may be formed (e.g., substantially conformally formed) to extend continuously on or over surfaces of the microelectronic device structure100defining the storage node contact openings168(FIG.8A), and portions of at least the second spacer material170at bottoms of the storage node contact openings168(FIG.8A) may be removed (e.g., by way of so-called “punch through” etching) to expose the storage node contact regions104B of the pillar structures104, and then additional semiconductor material172(e.g., additional epitaxial semiconductor material) may be formed to substantially fill remainders of the storage node contact openings168(FIG.8A).FIG.9Bis a top-down view of the microelectronic device structure100at the processing stage shown inFIG.9A, wherein the line A-A corresponds to the longitudinal cross-section of the microelectronic device structure100depicted inFIG.9A. For clarity in understanding the drawings and related description, some features (e.g., structures, materials, regions) of the microelectronic device structure100at the processing stage ofFIGS.9A and9Bthat are depicted inFIG.9Aare not depicted inFIG.9B, and vice versa. However, it will be understood that any feature depicted in at least one ofFIGS.9A and9Bmay be included in the microelectronic device structure100at the processing stage ofFIGS.9A and9B.

As shown inFIG.9A, the second spacer material170partially (e.g., less than completely) fills the storage node contact openings168(FIG.8A). The second spacer material170may substantially completely cover surfaces of the microelectronic device structure100defining the storage node contact openings168(FIG.8A). The second spacer material170may serve as an isolation material for conductive structures (e.g., storage node contact structures) subsequently formed within horizontal areas of the storage node contact openings168(FIG.8A), as described in further detail below.

The second spacer material170may be formed of and include dielectric material. In some embodiments, the second spacer material170is formed of and includes a dielectric nitride material (e.g., SiNy, such as Si3N4). In additional embodiments, the second spacer material170is formed of and includes at least one low-K (low-dielectric constant) dielectric material, such as one or more of silicon oxycarbide (SiOxCy), silicon oxynitride (SiOxNy), hydrogenated silicon oxycarbide (SiCxOyHz), and silicon oxycarbonitride (SiOxCzNy). In addition, the second spacer material170may be formed to have a thickness within a range of from about 1 nm to about 5 nm, such as from about 2 nm to about 4 nm, or from about 2 nm to about 3 nm.

Following the formation of the second spacer material170, portions thereof at lower boundaries (e.g., bottoms) of the storage node contact openings168(FIG.8A) may be removed, while at least partially (e.g., substantially) maintaining additional portions thereof at side boundaries (e.g., sides) of the storage node contact openings168(FIG.8A). In some embodiments, the removal process also partially removes portions of the pillar structures104within horizontal areas of the storage node contact regions104B. Lowermost boundaries of the resulting extended storage node contact openings may vertically overlie uppermost boundaries of the word line structures108. For example, the lowermost boundaries of the extended storage node contact openings may be positioned within vertical boundaries (e.g., between uppermost boundaries and lowermost boundaries) of the insulative line structures110. In some embodiments, the lowermost boundaries of the extended storage node contact openings are vertically offset from (e.g., vertically overlie) the uppermost boundaries of the word line structures108by greater than or equal to about 10 nm.

With continued reference toFIG.9A, the additional semiconductor material172may be formed to directly physically contact the storage node contact regions104B of the pillar structures104. The additional semiconductor material172may at least partially (e.g., substantially) fill portions of the storage node contact openings168(FIG.8A) (or extend storage node contact openings) remaining following the formation and processing (e.g., punch through etch) of the second spacer material170. In some embodiments, the additional semiconductor material172is formed of and includes additional epitaxial semiconductor material, such as additional epitaxial polycrystalline silicon. The additional semiconductor material172may be epitaxially grown from semiconductor material of the storage node contact regions104B of the pillar structures104in contact therewith.

Referring next toFIG.10A, the additional semiconductor material172within the storage node contact openings168(FIG.8A) may be vertically recessed; a third spacer material174may be formed (e.g., substantially conformally formed) to extend continuously on or over surfaces of the microelectronic device structure100defining newly unfilled portions the storage node contact openings168(FIG.8A); and then second sacrificial structures176may be formed over the third spacer material174and within the remainders of the storage node contact openings168(FIG.8A). Thereafter, portions of the fifth dielectric material166, the second sacrificial structures176, and the third spacer material174may be removed to form redistribution layer (RDL) openings178vertically extending through the fifth dielectric material166and exposing remaining (e.g., unremoved) portions of the second sacrificial structures176and the third spacer material174.FIG.10Bis a top-down view of the microelectronic device structure100at the processing stage shown inFIG.10A, wherein the line A-A corresponds to the longitudinal cross-section of the microelectronic device structure100depicted inFIG.10A. For clarity in understanding the drawings and related description, some features (e.g., structures, materials, regions) of the microelectronic device structure100at the processing stage ofFIGS.10A and10Bthat are depicted inFIG.10Aare not depicted inFIG.10B, and vice versa. However, it will be understood that any feature depicted in at least one ofFIGS.10A and10Bmay be included in the microelectronic device structure100at the processing stage ofFIGS.10A and10B.

Referring toFIG.10A, upper portions of the additional semiconductor material172formed at the processing stage ofFIGS.9A and9Bmay be removed (e.g., through an etching process) to vertically recess the additional semiconductor material172. Upper boundaries (e.g., upper surfaces) of the remaining portions of the additional semiconductor material172may vertically underlie lower boundaries of fourth dielectric material164. For example, the upper boundaries of the remaining portions of the additional semiconductor material172may be vertically positioned at or below lower boundaries of the third dielectric material116. In some embodiments, the upper boundaries of the remaining portions of the additional semiconductor material172are positioned at or below lower boundaries of the second dielectric material114.

The third spacer material174may be formed (e.g., substantially conformally formed) to partially (e.g., less than completely) fill the newly unfilled portions the storage node contact openings168(FIG.8A) resulting from the removal of the upper portions of the additional semiconductor material172. The third spacer material174may substantially cover upper surfaces of the remaining portions of the additional semiconductor material172within horizontal areas of the storage node contact openings168(FIG.8A), as well as side surfaces of the microelectronic device structure100(e.g., side surfaces of the fifth dielectric material166, the fourth dielectric material164, the third dielectric material116, the second dielectric material114) defining horizontal boundaries of the newly unfilled portions of the storage node contact openings168(FIG.8A). The third spacer material174may protect the remaining portions of the additional semiconductor material172and may ensure critical dimension (CD) control during subsequent processing acts (e.g., subsequent cleaning acts).

The third spacer material174may be formed of and include dielectric material. In some embodiments, the third spacer material174is formed of and includes a dielectric nitride material (e.g., SiNy, such as Si3N4). In additional embodiments, the third spacer material174is formed of and includes at least one low-K (low-dielectric constant) dielectric material, such as one or more of silicon oxycarbide (SiOxCy), silicon oxynitride (SiOxNy), hydrogenated silicon oxycarbide (SiCxOyHz), and silicon oxycarbonitride (SiOxCzNy). In addition, the third spacer material174may be formed to have a thickness within a range of from about 1 nm to about 5 nm, such as from about 2 nm to about 4 nm, or from about 2 nm to about 3 nm.

Still referring toFIG.10A, the second sacrificial structures176may be formed of and include a sacrificial material that is selectively etchable relative at least to the fifth dielectric material166, the fourth dielectric material164, and the third spacer material174. In some embodiments, the second sacrificial structures176are formed of and include a carbon-containing material (e.g., a carbon-based material), such as amorphous carbon. Prior to the formation of the RDL openings178, upper boundaries (e.g., upper surfaces) of the second sacrificial structures176may be formed to be substantially coplanar with an upper boundary (e.g., upper surface) of the fifth dielectric material166. For example, following the formation of the third spacer material174, sacrificial material may be formed inside and outside of remainders of the newly unfilled portions the storage node contact openings168(FIG.8A), and then portions of the sacrificial material and the third spacer material174overlying the upper boundary of the fifth dielectric material166may be removed (e.g., by way of a CMP process) to form the second sacrificial structures176and expose the fifth dielectric material166. Thereafter, the second sacrificial structures176may be vertically recessed as a result of the formation of the RDL openings178, as described in further detail below.

The RDL openings178may be formed to facilitate a horizontal pattern (e.g., a horizontal arrangement) for subsequently formed RDL structures and storage node structures (e.g., capacitors) than is different (e.g., at least partially horizontally offset from) a horizontal pattern of the storage node contact structures to subsequently be formed with horizontal areas of the storage node contact openings168(FIG.8A). The subsequently formed RDL structures (and the associated subsequently formed storage node structures) may be coupled to the subsequently formed storage node contact structures, as described in further detail below. The RDL openings178may at least partially horizontally overlap the second sacrificial structures176. However, horizontal centers of at least some of the RDL openings178may be offset from horizontal centers of at least some of the second sacrificial structures176exposed thereby.

As shown inFIG.10A, the RDL openings178may individually be formed to vertically extend at least through the fifth dielectric material166. In some embodiments, the lower boundaries (e.g., floors) of the RDL openings178may be defined, at least in part, by remaining portions of the fourth dielectric material164, the third spacer material174, and the second sacrificial structures176. In addition, in some embodiments, side boundaries (e.g., horizontal boundaries) of the RDL openings178may be defined, at least in part, by remaining portions of the fifth dielectric material166.

Referring toFIG.10B, the microelectronic device structure100may be formed to includes a hexagonal pattern (e.g., a hexagonal arrangement, a hexagonal grid, a hexagonal array) of the RDL openings178. The hexagonal pattern may exhibits a repeating horizontal arrangement of seven (7) RDL openings178, wherein one (1) of the seven (7) RDL openings178is substantially horizontally centered between six (6) other of the seven (7) RDL openings178. The hexagonal pattern exhibits different three (3) axes of symmetry (e.g., a first axis of symmetry, a second axis of symmetry, and a third axis of symmetry) in the same horizontal plane (e.g., the XY plane) about a center of the horizontally centered RDL opening178of the seven (7) RDL openings178. Different axes of symmetry directly radially adjacent to one another may be radially separated from one another by an angle of about 60 degrees. The hexagonal pattern of the RDL openings178exhibits a smaller horizontal area relative to a conventional square pattern having the same type and quantity of openings.

The geometric configurations (e.g., shapes, dimensions) and spacing of each of the RDL openings178may at least partially depend upon the geometric configurations (e.g., shapes, dimensions) and spacing of the second sacrificial structures176exposed thereby. For example, the RDL openings178may individually be formed to exhibit a generally columnar shape (e.g., a circular column shape, a rectangular column shape). In some embodiments, each of the RDL openings178is formed to exhibit a circular column shape having substantially circular horizontal cross-sectional shape.

Referring next toFIG.11A, remaining portions of the second sacrificial structures176(FIG.10A) may be removed (e.g., through a stripping and cleaning process), and portions of the third spacer material174on upper surfaces of the remaining portions of the additional semiconductor material172may be removed (e.g., by way of so-called “punch through” etching) to form storage node contact spacer structures180. Thereafter, the formation of storage node contact structures186may be completed within the horizontal areas of the storage node contact openings168(FIG.8A), and RDL structures188may be formed over the storage node contact structures186and within the RDL openings178(FIG.10A). An individual RDL structure188may be integral and continuous (e.g., unitary) with an individual storage node contact structure186.FIG.11Bis a top-down view of the microelectronic device structure100at the processing stage shown inFIG.11A, wherein the line A-A corresponds to the longitudinal cross-section of the microelectronic device structure100depicted inFIG.11A. For clarity in understanding the drawings and related description, some features (e.g., structures, materials, regions) of the microelectronic device structure100at the processing stage ofFIGS.11A and11Bthat are depicted inFIG.11Aare not depicted inFIG.11B, and vice versa. However, it will be understood that any feature depicted in at least one ofFIGS.11A and11Bmay be included in the microelectronic device structure100at the processing stage ofFIGS.11A and11B.

Referring toFIG.11A, the storage node contact structures186may individually be formed to include a first portion181(e.g., a lower portion) vertically overlying one of the storage node contact regions104B of an individual pillar structure104; a second portion182(e.g., a middle portion) vertically overlying the first portion181; and a third portion184(e.g., an upper portion) vertically overlying the second portion182. The first portion181may directly physically contact the storage node contact region104B of the pillar structure104, the third portion184may directly physically contact an individual RDL structure188, and the second portion182may vertically extend from and between the first portion181and the third portion184.

The first portion181of an individual storage node contact structure186may be formed of and include a remaining portion of the additional semiconductor material172(e.g., epitaxial semiconductor material, such as epitaxial polycrystalline silicon) within a horizontal area of an individual storage node contact opening168(FIG.8A). For an individual storage node contact structure186, an upper boundary of the first portion181thereof may be vertically positioned below, at, or above the uppermost boundaries of the insulative line structures110. In some embodiments, upper boundaries of the first portions181of the storage node contact structures186are vertically positioned at or above the uppermost boundaries of the insulative line structures110. For example, the upper boundaries of the first portions181of the storage node contact structure186may vertically positioned between a lowermost boundary and an uppermost boundary of the first dielectric material112.

The second portion182of an individual storage node contact structure186may be formed of and include metal silicide material, such as one or more of cobalt silicide (CoSix), tungsten silicide (WSix), tantalum silicide (TaSix), molybdenum silicide (MoSix), nickel silicide (NiSix), and titanium silicide (TiSix). For an individual storage node contact structure186, an upper boundary of the second portion182thereof may be vertically positioned below a lowermost boundary of the second dielectric material114, such as between the lowermost boundary of the second dielectric material114and the uppermost boundaries of the insulative line structures110.

The third portion184of an individual storage node contact structure186may be formed of and include conductive material, such as one or more of at least one elemental metal (e.g., W, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pd, Pt, Cu, Ag, Au, Al), at least one alloy (e.g., a Co-based alloy, an Fe-based alloy, an Ni-based alloy, an Fe- and Ni-based alloy, a Co- and Ni-based alloy, an Fe- and Co-based alloy, a Co- and Ni- and Fe-based alloy, an Al-based alloy, a Cu-based alloy, a magnesium (Mg)-based alloy, a Ti-based alloy, a steel, a low-carbon steel, a stainless steel), and a conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal carbide, a conductive metal oxide). In some embodiments, the third portion184is formed of and includes elemental metal, such as one or more of Ru, Mo, Ti, and W. For an individual storage node contact structure186, an upper boundary of the third portion184thereof may be vertically positioned above an uppermost boundary of the third dielectric material116and at or below a lowermost boundary of the fifth dielectric material166.

Still referring toFIG.11A, the RDL structures188may substantially fill portions of the RDL openings178(FIGS.10A and10B). A geometric configuration (e.g., shape, dimensions) of an individual RDL structure188may substantially correspond to a geometric configuration of the RDL opening178(FIGS.10A and10B) within which the RDL structure188is formed.

The RDL structures188may individually be formed of and include conductive material, such as one or more of at least one elemental metal (e.g., W, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pd, Pt, Cu, Ag, Au, Al), at least one alloy (e.g., a Co-based alloy, an Fe-based alloy, an Ni-based alloy, an Fe- and Ni-based alloy, a Co- and Ni-based alloy, an Fe- and Co-based alloy, a Co- and Ni- and Fe-based alloy, an Al-based alloy, a Cu-based alloy, a magnesium (Mg)-based alloy, a Ti-based alloy, a steel, a low-carbon steel, a stainless steel), and a conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal carbide, a conductive metal oxide). A material composition of the RDL structures188may be substantially the same as a material composition of the third portions184of the storage node contact structure186. In some embodiments, the RDL structures188are individually formed of and include elemental metal, such as one or more of Ru, Mo, Ti, and W. As shown inFIG.7A, for an individual RDL structure188, an upper boundary thereof may be formed to be substantially coplanar with an uppermost boundary of the fifth dielectric material166.

To form the storage node contact structures186and the RDL structures188, after forming the storage node contact spacer structures180, conductive material may be formed inside and outside of newly unfilled portions of the storage node contact openings168(FIG.8A) and the RDL openings178(FIGS.10A and10B), and subjected to thermal processing (e.g., rapid thermal processing (RTP)) to form the second portions182of the storage node contact structures186. A wet cleaning process may then be performed, followed by the formation of additional conductive material inside and outside of new remainders of the storage node contact openings168(FIG.8A) and the RDL openings178(FIGS.10A and10B) to form the third portions184of the storage node contact structures186. Thereafter portions of the conductive material (if any) and the additional conductive material overlying an uppermost boundary (e.g., an uppermost surface) of the fifth dielectric material166may be removed (e.g., by way of a CMP process) to expose the fifth dielectric material166and form the RDL structures188.

Following the processing stage described with reference toFIGS.11A and11B, the microelectronic device structure100may be subjected to additional processing, as desired. For example, storage node structures (e.g., capacitor structures) may be formed vertically over and in electrical communication with the RDL structures188. Such additional processing may employ conventional processes and conventional processing equipment, and therefore is not described in detail herein.

Thus, in accordance with embodiments of the disclosure, a method of forming a microelectronic device includes forming a first dielectric stack over a semiconductor base structure including pillar structures separated from one another by filled isolation trenches. Digit line contacts are formed to partially vertically extend through the first dielectric stack and into digit line contact regions of the pillar structures. Digit lines are formed over and in contact with the digit line contacts, the digit lines partially vertically extending through the first dielectric stack. A second dielectric stack is formed over the digit lines and the first dielectric stack. Storage node contacts are formed to vertically extend partially through the second dielectric stack, completely through the first dielectric stack, and into storage node contact regions of the pillar structures. RDL structures are formed over and in contact with the storage node contacts, the RDL structures partially vertically extending through the second dielectric stack.

Microelectronic device structures (e.g., the microelectronic device structure100at or following the processing stage previously described with reference toFIGS.11A and11B) of the disclosure may be included in microelectronic devices of the disclosure. As a non-limiting example,FIG.12illustrates a functional block diagram of a memory device200, in accordance with an embodiment of the disclosure. The memory device200may include, for example, an embodiment of the microelectronic device structure100at or following the processing stage previously described with reference toFIGS.11A and11B. As shown inFIG.12, the memory device200may include memory cells202, digit lines204, word lines206, a row decoder208, a column decoder210, a memory controller212, a sense device214, and an input/output device216.

The memory cells202of the memory device200are programmable to at least two different logic states (e.g., logic 0 and logic 1). Each memory cell202may individually include a capacitor and transistor (e.g., a pass transistor). The transistors may be defined, in part, by the pillar structures104(FIGS.11A and11B) and the word line structures108(FIGS.11Aand11B) (e.g., serving as gate electrodes) previously describe herein with reference toFIGS.1A through11B. The capacitor stores a charge representative of the programmable logic state (e.g., a charged capacitor may represent a first logic state, such as a logic 1; and an uncharged capacitor may represent a second logic state, such as a logic 0) of the memory cell202. The transistor grants access to the capacitor upon application (e.g., by way of one of the word lines206) of a minimum threshold voltage to a semiconductive channel thereof for operations (e.g., reading, writing, rewriting) on the capacitor.

The digit lines204(e.g., corresponding to the digit line structures160(FIGS.11A and11B)) are connected to the capacitors of the memory cells202by way of the transistors of the memory cells202. The word lines206(e.g., corresponding to the word line structures108(FIGS.11A and11B)) extend perpendicular to the digit lines204, and serve as gates of the transistors of the memory cells202. Operations may be performed on the memory cells202by activating appropriate digit lines204and word lines206. Activating a digit line204or a word line206may include applying a voltage potential to the digit line204or the word line206. Each column of memory cells202may individually be connected to one of the digit lines204, and each row of the memory cells202may individually be connected to one of the word lines206. Individual memory cells202may be addressed and accessed through the intersections (e.g., cross points) of the digit lines204and the word lines206.

The memory controller212may control the operations of memory cells202through various components, including the row decoder208, the column decoder210, and the sense device214(e.g., local I/O device). The memory controller212may generate row address signals that are directed to the row decoder208to activate (e.g., apply a voltage potential to) predetermined word lines206, and may generate column address signals that are directed to the column decoder210to activate (e.g., apply a voltage potential to) predetermined digit lines204. The sense device214may include sense amplifiers configured and operated to receive digit line inputs from the digit lines selected by the column decoder210and to generate digital data values during read operations. The memory controller212may also generate and control various voltage potentials employed during the operation of the memory device200. In general, the amplitude, shape, and/or duration of an applied voltage may be adjusted (e.g., varied), and may be different for various operations of the memory device200.

During use and operation of the memory device200, after being accessed, a memory cell202may be read (e.g., sensed) by the sense device214. The sense device214may compare a signal (e.g., a voltage) of an appropriate digit line204to a reference signal in order to determine the logic state of the memory cell202. If, for example, the digit line204has a higher voltage than the reference voltage, the sense device214may determine that the stored logic state of the memory cell202is a logic 1, and vice versa. The sense device214may include transistors and amplifiers to detect and amplify a difference in the signals (commonly referred to in the art as “latching”). The detected logic state of a memory cell202may be output through the column decoder210to the input/output device216. In addition, a memory cell202may be set (e.g., written) by similarly activating an appropriate word line206and an appropriate digit line204of the memory device200. By controlling the digit line204while the word line206is activated, the memory cell202may be set (e.g., a logic value may be stored in the memory cell202). The column decoder210may accept data from the input/output device216to be written to the memory cells202. Furthermore, a memory cell202may also be refreshed (e.g., recharged) by reading the memory cell202. The read operation will place the contents of the memory cell202on the appropriate digit line204, which is then pulled up to full level (e.g., full charge or discharge) by the sense device214. When the word line206associated with the memory cell202is deactivated, all of memory cells202in the row associated with the word line206are restored to full charge or discharge.

Thus, in accordance with embodiments of the disclosure, a microelectronic device includes semiconductor base structure, word lines, a first dielectric stack, digit line contacts, digit lines, a second dielectric stack, storage node contacts, and redistribution layer structures. The semiconductor base structure includes pillar structures horizontally separated from one another by filled isolation trenches. The word lines horizontally extend through the pillar structures and the filled isolation trenches in a first direction. The first dielectric stack vertically overlies the pillar structures, the filled isolation trenches, and the word lines. The digit line contacts partially vertically extend through the first dielectric stack and into digit line contact regions of the pillar structures. The digit lines are over and in contact with the digit line contacts and partially vertically extend through the first dielectric stack, the digit lines horizontally extend in a second direction orthogonal to the first direction. The second dielectric stack overlies the digit lines and the first dielectric stack. The storage node contacts vertically extend partially through the second dielectric stack, completely through the first dielectric stack, and into storage node contact regions of the pillar structures. The redistribution layer structures overlie and are in contact with the storage node contacts, the redistribution layer structures partially vertically extend through the second dielectric stack.

Microelectronic devices (e.g., the memory device200shown inFIG.12) including microelectronic device structures (e.g., the microelectronic device structure100shown inFIGS.11A and11B) in accordance with embodiments of the disclosure may be used in embodiments of electronic systems of the disclosure. For example,FIG.13is a block diagram of an illustrative electronic system300according to embodiments of disclosure. The electronic system300may comprise, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular telephone, a digital camera, a personal digital assistant (PDA), portable media (e.g., music) player, a Wi-Fi or cellular-enabled tablet such as, for example, an iPAD® or SURFACE® tablet, an electronic book, a navigation device, etc. The electronic system300includes at least one memory device302. The memory device302may comprise, for example, an embodiment of a microelectronic device (e.g., the memory device200shown inFIG.12) previously described herein. The electronic system300may further include at least one electronic signal processor device304(often referred to as a “microprocessor”). The electronic signal processor device304may, optionally, include an embodiment a microelectronic device (e.g., the memory device200shown inFIG.12) previously described herein. While the memory device302and the electronic signal processor device304are depicted as two (2) separate devices inFIG.13, in additional embodiments, a single (e.g., only one) memory/processor device having the functionalities of the memory device302and the electronic signal processor device304is included in the electronic system300. In such embodiments, the memory/processor device may include an embodiment of a microelectronic device structure (e.g., the microelectronic device structure100shown inFIGS.11A and11B) previously described herein, and/or an embodiment of a microelectronic device (e.g., the memory device200shown inFIG.12) previously described herein. The electronic system300may further include one or more input devices306for inputting information into the electronic system300by a user, such as, for example, a mouse or other pointing device, a keyboard, a touchpad, a button, or a control panel. The electronic system300may further include one or more output devices308for outputting information (e.g., visual or audio output) to a user such as, for example, a monitor, a display, a printer, an audio output jack, a speaker, etc. In some embodiments, the input device306and the output device308may comprise a single touchscreen device that can be used both to input information to the electronic system300and to output visual information to a user. The input device306and the output device308may communicate electrically with one or more of the memory device302and the electronic signal processor device304.

Thus, in accordance with embodiments of the disclosure, an electronic system includes an input device, an output device, a processor device operably coupled to the input device and the output device, and a memory device operably coupled to the processor device and including at least one microelectronic device structure. The at least one microelectronic device structure includes a base structure, word lines, dielectric materials, digit line contacts, digit lines, additional dielectric materials, storage node contacts, and redistribution layer structures. The base structure includes semiconductive pillar structures horizontally separated from one another by filled isolation trenches. The word lines extend through the semiconductive pillar structures and the filled isolation trenches in a first horizontal direction. The dielectric materials over the pillar structures, the filled isolation trenches, and the word lines. The digit line contacts extend through a lower portion of the dielectric materials and into digit line contact regions of the semiconductive pillar structures. The digit lines are over and in contact with the digit line contacts and vertically extend through an upper portion of the dielectric materials. The digit lines extend in a second horizontal direction orthogonal to the first horizontal direction. The additional dielectric materials overlie the digit lines and the dielectric materials. The storage node contacts vertically extend through a lower portion of the additional dielectric materials, completely through the dielectric materials, and into storage node contact regions of the semiconductive pillar structures. The redistribution layer structures are over and in contact with the storage node contacts. The redistribution layer structures vertically extend through an upper portion the additional dielectric materials.

The structures, devices, and methods of the disclosure advantageously facilitate one or more of improved microelectronic device performance, reduced costs (e.g., manufacturing costs, material costs), increased miniaturization of components, and greater packaging density as compared to conventional structures, conventional devices, and conventional methods. The structures, devices, and methods of the disclosure may also improve scalability, efficiency, and simplicity as compared to conventional structures, conventional devices, and conventional methods.

While the disclosure is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, the disclosure is not limited to the particular forms disclosed. Rather, the disclosure is to cover all modifications, equivalents, and alternatives falling within the scope of the following appended claims and their legal equivalent. For example, elements and features disclosed in relation to one embodiment may be combined with elements and features disclosed in relation to other embodiments of the disclosure.