Cryptographic device for implementing S-box

Provided is a cryptographic device implementing an S-Box of an encryption algorithm using a many-to-one binary function. The cryptographic device includes: arrays of first logic gates including I first logic gates which each receive 2 bits of an input signal; 2N second logic gates which each receive corresponding J bits from among I bits output from the arrays of the first logic gates; and L third logic gates which each receive K bits from among 2N bits output from the second logic gates, wherein there is a many-to-one correspondence between the N bits of the input signal and the K bits input to each of the third logic gates, and wherein the N, I, J, K, and L are positive integers. Because a signal output from each array includes only one active bit, current is always consumed constantly to prevent internal data from leaking out to a hacker.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority from Korean Patent Application No. 10-2009-0117881, filed on Dec. 1, 2009 in the Korean Intellectual Property Office, the entirety of which is hereby incorporated by reference.

BACKGROUND

Apparatuses and methods consistent with exemplary embodiments relate to a cryptographic device.

2. Description of Related Art

In recent years, information transmitted by a user in communications using a smart card or an integrated circuit (IC) card, Internet communications, wireless local area network (LAN) communications, and Internet banking include secret information. Secret information may be leaked by hacking. Therefore, hardware encryption/decryption devices are increasingly being used to prevent the leakage of secret information. Prior to transmission of secret information receiving a signature or passing an authentication procedure, the hardware encryption/decryption device transforms the secret information into a cryptogram.

Because speed of an encryption operation is typically low, most encryption operations are carried out using hardware to be applied to devices such as a smart card. Data encryption standard (DES) is a type of block encryption algorithm and a symmetric key encryption scheme using 56 bits of a key. A substitution box (hereinafter referred to as “S-Box”) for use in DES carries out a substitution operation to convert an m-bit input into an n-bit output.

When DES is embodied with hardware, an S-Box is designed using a lookup table. However, a data value of the S-Box may be exposed to a hacker according to a hardware design technique. Accordingly, there is a need for the hardware design for an S-Box that is capable of preventing exposure of internal data even when the S-Box is attacked by a hacker.

SUMMARY

Exemplary embodiments provide a cryptographic device.

According to an aspect of an exemplary embodiment, there is provided a cryptographic device including: arrays of first logic gates including I first logic gates each receiving 2 bits from among N bits of an input signal, where I and N are positive integers; 2Nsecond logic gates each receiving corresponding J bits from among I bits output from the arrays of first logic gates, where J is a positive integer; and L third logic gates each receiving K bits from among 2Nbits of signal output from the second logic gates, where L and K are positive integers, wherein the I bits, the 2Nbits, and L bits respectively output from the arrays of the first logic gates, the second logic gates, and the third logic gates each have only one active bit, and there is a many-to-one correspondence between the N bits of the input signal and the K bits input to each of the third logic gates.

According to an aspect of an exemplary embodiment, there is provided a cryptographic device including: an array of first logic gates receiving first 2 bits among 6 bits of an input signal and outputting first 4 bits; an array of second logic gates receiving second 2 bits among the 6 bits of the input signal and outputting second 4 bits; an array of third logic gates receiving third 2 bits among the 6 bits of the input signal and outputting third 4 bits; 64 forth logic gates each receiving corresponding 3 bits from among the 4 bits output from the arrays of the first, second, and third logic gates; and 16 fifth logic gates each receiving 4 bits from among the 64 bits output from the fourth logic gates, wherein the 4 bits, the 64 bits, and the 16 bits respectively output from the arrays of the first, second, and third logic gates, the fourth logic gates, and the fifth logic gates each have only one active bit, and there is a many-to-one correspondence between the 6 bits of the input signal and the 4 bits input to each of the fifth logic gates.

According to an aspect of another exemplary embodiment, there is provided a cryptographic device including: a first decoder which decodes an input signal of N bits into 2Nbits; and a second decoder which decodes the 2Nbits output from the first decoder into L bits, wherein the 2Nbits output from the first decoder and the L bits output from the second decoder each include only one active bit, and wherein N and L are positive integers.

According to an aspect of another exemplary embodiment, there is provided a cryptographic method including: receiving, at each of arrays of first logic gates comprising I first logic gates, 2 bits from among N bits of an input signal; receiving, at each of 2Nsecond logic gates, corresponding J bits from among I bits output from the arrays of the first logic gates; and receiving, at each of L third logic gates, K bits from among 2Nbits output from the second logic gates, wherein the I bits, the 2Nbits, and L bits respectively output from the arrays of the first logic gates, the second logic gates, and the third logic gates each have only one active bit, wherein there is a many-to-one correspondence between the N bits of the input signal and the K bits input to each of the third logic gates, and wherein the N, I, J, K, and L are positive integers, respectively.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Exemplary embodiments will now be described more fully hereinafter with reference to the accompanying drawings.

FIG. 1illustrates a cryptographic device100according to an exemplary embodiment. As illustrated, the cryptographic device100includes a first decoder110, a second decoder120, and an encoder130. The first decoder110receives an input signal IN which is 6 bits and outputs 64 bits. The 64 bit output from the first decoder110includes one active bit from among the 64 bits according to the 6 bits of the input signal IN.

The second decoder120decodes the 64 bits from the first decoder110into 16 bits. Irrespective of a value of the 6 bits of the input signal IN, power consumed in the first and second decoders110and120is constantly maintained. As a result, the cryptographic device100may be protected from a hacker's attack, such as a differential power attack (DPA) and an attack through electromagnetic (EM) detection.

The encoder130encodes the 16 bits output from the second decoder120into a 4 bit output signal OUT and outputs the output signal OUT. The cryptographic device100shown inFIG. 1may convert 6 bits of input signal IN into 4 bits of output signal OUT according to an S-Box many-to-one binary function.

FIG. 2illustrates a cryptographic device200according to another exemplary embodiment. As illustrated, the cryptographic device200includes arrays211,212, and213of first logic gates, an array220of second logic gates, an array230of third logic gates, and an encoder240. The array211of the first logic gates receives 2 bits A0and A1from among bits of an input signal IN and outputs 4 bits B0, B1, B2, and B3. The array211of the first logic gates includes a plurality of logic gates (not shown) each receiving 2 bits A0and A1. The other arrays212and213of the first logic gates are organized with the same or similar circuit structure as the array211of the first logic gates and perform the same or similar operations as the array211of the first logic gates. Each of the arrays211,212, and213receives different 2 bits from among the bits of the input signal IN and outputs 4 bits. That is, the arrays211,212, and213output a total of 12 bits B0˜B11.

The array220of the second logic gates receives the 12 bits from the arrays211,212, and213of the first logic gates and outputs 64 bits C0˜C63. The array220of the second logic gates includes a plurality of logic gates (not shown) each receiving 1 bit from each of the arrays211,212, and213of the first logic gates (i.e., each receiving a total of 3 bits).

The array230of the third logic gates receives the 64 bits C0˜C63from the array220of the second logic gates and outputs 16 bits D0˜D15corresponding to the 64 bits C0˜C63. The array230of the third logic gates includes a plurality of logic gates (not shown) each receiving 4 bits from among the 64 bits C0˜C64from the array220of the second logic gates. There is a many-to-one correspondence according to an S-Box binary function between 6 bits of the input signal IN and a K-bit signal input to the respective logic gates in the array230of the third logic gates.

The encoder240outputs the 16 bits D0˜D15output from the array230of the third logic gates, as a 4 bit signal OUT. The encoder240encodes the 16 bits D0˜D15into 4 bits of signal OUT. The encoder240may be designed to constantly consume current although the 16 bits of signals D0˜D15have any value. Thus, the cryptographic device200shown inFIG. 2may substitute 6 bits of input signal IN with 4 bits of output signal OUT according to an S-Box binary function.

In the respective arrays211,212,213,220, and230, one of respective logic gates constructed therein (i.e., a total five logic gates) outputs an active bit (or inactive bit) although an input signal IN has any value. Therefore, power is constantly consumed irrespective of the input signal IN.

FIG. 3illustrates a detailed circuit configuration of arrays of logic gates shown inFIG. 2according to an exemplary embodiment. Referring toFIG. 3, the array211of the first logic gates include two inverters301and302and four AND gates303˜306. The inverter301receives an input signal A0, and the inverter302receives an input signal A1. The AND gate303receives the input signals A0and A1. The AND gate304receives the input signal A0and an output of the inverter302. The AND gate305receives an output of the inverter301and the input signal A1. The AND gate306receives outputs of the inverters301and302. The array211of the first logic gates receive 2 bits A0and A1and outputs 4 bits through the AND gates303˜306. The arrays212and213of other first logic gates are organized with the same or similar structures as the array211of the first logic gates. The array212of the first logic gates receives input signals A2and A3and the array213of the first logic gates receives input signals A4and A5.

In the array211of the first logic gates, only one AND gate among the four AND gates303˜306is toggled according to the input signals A0and A1. That is, only one bit among four bits B0˜B3output from the four AND gates303˜306is an active bit that is a high level. Since the array211of the first logic gates always outputs one active bit for all cases of the input signals A0and A1, current consumed at the array211of the first logic gates is always constant. Similar to the array212of the first logic gates, each of the other arrays212and213of the first logic gates outputs only one active bit.

The array220of the second logic gates includes 64 AND gates311. Each of the AND gates311includes three input terminals and an output terminal. Furthermore, each of the AND gates311receives 1 bit from each of the arrays211,212, and213of the first logic gates (i.e., each of the AND gates311receives a total of 3 bits). More specifically, each of the AND gates311in the array220of the second logic gates receives 1 bit from among the 4 bits B0˜B3, 1 bit from among the 4 bits B4˜B7, and 1 bit from among the 4 bits B9˜B11. The 64 bits C0˜C63output from the array220of the second logic gates are decoding signals according to the number of cases (26) of A0, A1, A2, A3, A4, and A5. Only one of the 64 AND gates311in the array220of the second logic gates is toggled according to 12 bits B0˜B11output from the arrays211˜213of the first logic gates. That is, among the 64 bits C0˜C63output from the 64 AND gates311in the array220of the second logic gates, only one bit is an active bit.

The array230of the third logic gates includes 16 OR gates321. Each of the OR gates321includes four input terminals and one output terminal. Each of the OR gates321receives 4 bits from among the 64 bits C0˜C63output from the array230of the second logic gates. The 4 bits input to each of the OR gates321are determined according to an S-Box lookup table.

FIG. 4illustrates an S-Box lookup table according to an exemplary embodiment. Although a DES algorithm uses a total of eight S-Boxes,FIG. 4shows one S-Box. Referring toFIG. 4, the lookup table shows 4 output bits to 6 bits of input signal A0˜A5. Among the 6 bits A0˜A5, 2 bits A0and A5designate rows of the lookup table and four bits A1, A2, A3, and A4designate columns of the lookup table. For example, when the input signal A0˜A5is “110110”, “0111” of a position designated by a column “1011” of a row “10” designated by the 2 bits A0and A5is selected as an output signal. In this case, the output signal “0111” is designated by not only the row “10” and the column “1011” but also a row “00” and a column “1111,” a row “01” and a column “0010,” and a row “11” and a column “0111.” This is because the S-BOX uses a many-to-one binary function.

Returning toFIG. 3, the array230of the third logic gates always outputs the same 4 bits to four types of values of 6 bits of input signals A0˜A5according to the lookup table shown inFIG. 4. Thus, each of the OR gates321in the array230of the third logic gates receives 4 bits from among the 64 bits C0˜C63output from the AND gates311in the array220of the second logic gates. For example, when 6 bits of input signal A0˜A5are “011110,” “000101,” “110110,” and “101111,” an output signal is “0111.” Therefore, an OR gate corresponding to “0111” in the array230of the third logic gates is connected to receive output signals of an AND gate corresponding to “011110,” “000101,” “110110,” and “101111” in the array220of the second logic gates. Likewise, input terminals of the OR gates321in the array230of the third logic gates are connected to output signals of the AND gates311in the array220of the second logic gates according to the lookup table shown inFIG. 4. The 16 bits D0˜D15output from the array230of the third logic gates are provided to the encoder240shown inFIG. 2.

As illustrated inFIG. 3, AND gates in the arrays211,212, and213of the first logic gates and the array220of the second logic gates are toggled one by one. Further, any one of the OR gates in the array230of the third logic gates is toggled. Accordingly, a total of five logic gates are toggled at the arrays211,212,213,220, and230of the first to third logic gates although the input signals A0-A5have any value. For this reason, the amount of current consumed at the arrays211,212,213,220, and230of the first to third logic gates is always constant irrespective of values of the input signals A0˜A6. Accordingly, with a simple circuit configuration, an S-Box for DES algorithm is implemented using hardware, and a cryptographic device with security against a hacker's attack may be implemented.

The cryptographic device200shown inFIG. 3is a cryptographic device implementing one S-Box. Eight cryptographic devices200are used to implement eight S-Boxes. In that case, the AND gates311in the array220of the second logic gates are connected to the OR gates321in the array230of the third logic gates according to a many-to-one correspondence between input and output signals of the S-Box.

As set forth in the above-described exemplary embodiments, an input signal IN is 6 bits and an output signal OUT is 4 bits. However, bit widths of the input signal IN and the output signal OUT may be variously changed. With the change in bit widths of the input signal IN and the output signal OUT, the number of the arrays211,212, and213of the first logic gates, the number of the AND gates311in the array220of the second logic gates, and the number of the OR gates230in the third logic gates are changed. However, a many-to-one correspondence between the input signal IN and the output signal OUT is established.

FIG. 5illustrates an example of a cryptographic device500having a reset function according to an exemplary embodiment. Unlike the cryptographic device300illustrated inFIG. 3, the cryptographic device500further inputs a clock signal CK to AND gates in arrays511˜513of first logic gates. If a previous output signal is logic “1,” the AND gates invert the output signal into logic “0” at a low level of the clock signal CK. In this case, the amount of current consumption is not changed because only 1 bit transitions to an inactive state. Moreover, in the case that input bits A0˜A5have the same value during a previous cycle and a current cycle of the clock signal CK, it is possible to solve a problem that output bits of the arrays511˜513of the first logic gates do not turn to active/inactive bit.

FIG. 6illustrates another circuit configuration of arrays of logic gates shown inFIG. 2according to another exemplary embodiment. Referring toFIG. 6, unlikeFIG. 3, arrays611˜613of first logic gates include OR gates603˜606, an array620of second logic gates includes OR gates621, and an array630of third logic gates includes AND gates631.

Although input signals A0˜A5have any value like inFIG. 3, only five logic gates are toggled at arrays611,612,613,620, and630of first to third logic gates shown inFIG. 6. Signals output from the arrays611,612,613,620, and630of the first to third logic gates include five inactive bits with the other bits being active bits. Likewise even when the arrays211,212,213,220, and230of the first to third logic gates illustrated inFIG. 3are substituted with the arrays611,612,613,620, and630of the first to third logic gates, the amount of current consumed at the arrays611,612,613,620, and630of the first to third logic gates is always constant irrespective of values of the input signals A0˜A6.

To sum up, when an S-Box operation is carried out, constant current is always consumed to prevent internal data from leaking to hackers.

While exemplary embodiments have been described with reference to the accompanying drawings, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present inventive concept. Therefore, it should be understood that the above exemplary embodiments are not limiting, but illustrative. Thus, the scope of the inventive concept is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing description.