Segmented non-volatile memory array with multiple sources having improved source line decode circuitry

A flash memory array arrangement having a plurality of erase blocks which can be separately erased. The erase blocks have separate source lines, the state of which is controlled by a source line decoder. In array read, program and erase operations, the source lines of the deselected erase blocks, the blocks that are not being read, programmed or erased, are set to a high impedance level. If a cell in one of the deselected erase blocks is defective in some respect such that the cell is conducting leakage current, the high impedance source line associated with the cell will reduce the likelihood that the defective cell will prevent proper operation of the selected erase block.

BACKGROUND OF THE INVENTION

The present invention relates generally to semiconductor memory systems and in particular to a segmented non-volatile memory array having multiple sources so that blocks of the array can be erased separately and having improved source line decode circuitry.

BACKGROUND ART

Non-volatile semiconductor memory systems have become increasingly popular, including flash memory systems.FIG. 1is a simplified diagram of the cross-section of a typical flash memory cell10. Cell10is an N-channel device formed in a P-type substrate12. An N-type drain region14is formed in substrate12as is an N-type source region16. Source region16includes an N-type region16A formed in the substrate12having an N+-type region16B formed inside region16A so as to form a graded source region16.

The drain and regions source14and16are spaced apart from one another so as to form a channel region12A in the substrate intermediate the two regions. A floating gate18is disposed above the channel region12A and a control gate20is disposed above the floating gate18. The floating gate is separated from the channel region12A by a thin (100 Å) gate oxide layer22. The floating and control gates18and20are typically both formed from doped poly silicon. The control gate20is separated from the floating gate18by an interpoly dielectric layer24. Other than being capacitively coupled to other elements of cell10, the floating gate18is electrically isolated from the rest of the cell.

Table 1 below shows typical conditions for performing program, read and erase operations (two approaches) on flash cell10.

If cell10is in an erased state, the cell will have a threshold voltage, called an erased threshold voltage, which is typically approximately +2 volts. If the cell is in a programmed state, the cell will have a programmed threshold voltage of typically approximately +6 volts. In a read operation, the control-gate-to-source voltage of the cell is +5 volts as can be seen from Table 1, above. The drain14will be connected to a small positive voltage of typically +1.5 volts and the source16is grounded. Thus, if the cell10is in a programmed state, the cell will not conduct current in the read operation since the gate-to-source voltage of +5 volts is less than the programmed threshold voltage of +6 volts. If the cell is in an erased state, the gate to source voltage will exceed the erased threshold voltage so that the cell will conduct current. The presence or absence of cell current in a read operation is detected by a sense amplifier so that the state of the cell can be determined.

In order to program the flash cell10, Table 1 indicates that the source16is grounded and the drain14is connected to +6 volts. The control gate20is connected to a high voltage such as +12 volts. The combination of conditions will cause electrons to travel from the source16towards the drain14. Some of these electrons will possess sufficient energy to pass through the gate oxide22towards the positive voltage on the control gate20. Those electrons, sometimes referred to as hot electrons, will be deposited on the floating gate18and will remain there until the cell10is erased. The presence of electrons on the floating gate18will tend to increase the threshold voltage of the cell, as previously noted.

Table 1 depicts two approaches for erasing a cell. The first approach (Erase1), a cell is erased by floating the drain14and applying a large positive voltage, such as +12 volts, to the source16. The control gate20is grounded. This combination causes electrons stored on the floating gate18to pass through the thin gate oxide22and to be transferred to the source16. The physical mechanism for the transfer is commonly referred to as Fowler Nordheim tunneling.

The above conditions for erasing a cell (Erase1) have been viewed by others as disadvantageous in that the large positive voltage (+12 volts) applied to the source region is difficult to implement in an actual memory system. First, the primary supply voltage VCCin a typical integrated circuit memory system is +5 volts and is provided by an external power supply such as a battery. Thus, one approach would be to include a charge pump on the memory integrated circuit which is also powered by the primary supply voltage VCC. However, a typical integrated circuit memory system may include a million or more cells all or a very large group of which will be erased at the same time. Thus, the charge pump circuit must be capable of providing relatively large amounts of current on the order of 20 to 30 milliamperes. This has been viewed by others as impractical thus necessitating the use of an a second external supply voltage for producing the +12 volts applied to the source region. This would typically preclude battery powered operation where multiple batteries, such as a +5 volt primary supply battery and a +12 volts battery, is not practical.

The application of the relatively high voltage of +12 volts has also been viewed as disadvantageous in that there was believed to be a tendency to produce high energy holes (“hot” holes) at the surface of the source region16near the channel region12a. These positive charges were said to have a tendency to become trapped in the thin gate oxide20and eventually migrate to the floating gate and slowly neutralize any negative charge placed on the floating gate during programming. Thus, over time, the programmed state of the cell may be altered. Other deleterious effects due to the presence of holes have been noted, including the undesired tendency to program non-selected cells.

The above-described disadvantages of the erase conditions set forth in Table 1 (Erase1) have been noted in U.S. Pat. No. 5,077,691 entitled FLASH EEPROM ARRAY WITH NEGATIVE GATE VOLTAGE ERASE OPERATION. The solution in U.S. Pat. No. 5,077,691 is summarized in Table 1 (Erase2). A relatively large negative voltage ranging from −10 to −17 volts is applied to the gate22during an erase operation. In addition, the primary supply voltage VCCof +5 volts (or less) is applied to the source region16. The drain region14is left floating.

Although the source current remains relatively high, the voltage applied to the source is sufficiently low that the +5 volt primary supply voltage VCCcan be used directly or the source voltage may be derived from the primary supply voltage using a series regulator or a resistive divider in combination with a buffer circuit. In either event, since the source voltage is equal to or less than the primary supply voltage, the large source currents required in erase operations can be provided without the use of charge pump circuitry. The high impedance control gate20of the flash cell draws very little current. Accordingly, the large negative voltage applied to the control gate20in the erase operation can be provided by a charge pump circuit. Thus, according to U.S. Pat. No. 5,077,691, only a single external power supply, the +5 volt supply for VCC, need be used.

In a flash memory system, the flash cells10are arranged in a cell array which typically includes several rows and several columns of cells. Each of the rows has an associated word line connected to the control gate20of the cells10located in the row. Each of the columns has an associate bit line connected to the drain14of each cell located in the column. The sources16of all of the cells of the array are usually connected in common, but as will be explained, the sources may be separately connected.

FIG. 2Ais a simplified plan view of a conventional layout of a pair of flash cells10A and10B of a cell array.FIG. 2Bis a schematic diagram of cells10A and10B of FIG.2A. As can be seen inFIG. 2B, cells10A and10B have their respective sources connected in common. Typically, the two sources are actually a single source region shared by the two cells10A and10B. Cells10A and10B are located in a common array column and in separated rows. The column has an associated bit line BL0which is connected to the drains of cells10A and10B. Cell10A is in a row having an associated word line WL0connected to its control gate20and cell10B is in an adjacent row having its control gate20connected to an associated word line WL1.

The bit lines, including bit line BL0, extend vertically along the array and include an underlying diffusion component26A of doped semiconductor material and an overlying metal line component26B. The metal line component26B makes electrical contact with the diffusion component26A every two cells10by way of contacts28. The source lines have a horizontal segment SLD0which runs generally parallel to the word lines and is made of doped semiconductor material. The source lines also have a vertical segment SLM0which runs generally parallel to the bit lines and is formed from metal. The horizontal and vertical components SLD0and SLM0are electrically connected by way of a contact30located at the intersection of the two segments every two rows of the array.

Cell10A has its control gate20connected to horizontal word line WL0, a doped polysilicon line which extends across the array. Cell10B has its control gate20connected to horizontal word line WL1which also extends across the array. A flash cell (10A,10B) is formed at the intersection of each of the word lines and bit lines.

FIG. 3Ais a simplified plan view of the layout of a relatively small conventional flash cell array32andFIG. 3Bis a schematic diagram of theFIG. 3Aarray. Array32is comprised of twelve rows, each having an associated horizontal polysilicon word line WL0-WL11. The array also has twelve columns, with each column having an associated metal bit line BL0-BL11. Array32also includes four vertical metal source lines SLM0-SLM3which are connected in common to the six horizontal diffused source lines SLD0-SLD5. Each metal source line SLMN is connected to the diffused source lines SLDN every two rows. The metal source lines SLM are spaced every four columns. For example, adjacent metal source lines SLM0and SLM1are separated by four bit lines BL0-BL3.

The metal source lines SLM0-SLM3are electrically connected together by circuitry (not depicted) external to array32. Thus, all of the source lines of the array are nominally at the same electrical potential. However, the horizontal diffused source lines SLD0-SLD5have a relatively high resistance, in comparison to the metal source lines. This high resistance can have an adverse impact upon memory operations, particularly programming and reading operations. The use of multiple metal source lines functions to reduce the overall source line resistance. However, each metal line occupies a significant amount of integrated circuit area so that the use of multiple metal source lines will increase the die area and thereby effectively increase the cost of manufacturing the cell array.

Flash memory systems are typically erased in bulk. That means that either all or a large part of the array are erased at the same time. By way of example, the entire array32ofFIGS. 3A and 3Bwould be erased in a single operation. As indicated by Table 1, this can be accomplished by applying +12 volts to the common source lines SLM0-SLM3, grounding all of the word lines WLN0-WLN11and floating all of the bit lines BL0-BL11.

There exist conventional memory arrays which provide the capability of erasing less than the entire array. This feature is particularly useful in many memory applications where it is desirable to retain some data stored in the memory while erasing and then reprogramming other data in the memory. The capability of erasing less than the entire memory is typically accomplished by electrically isolating the source lines of individual blocks of the memory array. A particular block is erased by applying a high voltage, such as +12 volts (Table 1) to the source line associated with the block being erased. The word lines of the block to be erased are grounded and the bit lines of the block are left floating. As is known, the word lines and source lines of the erase blocks not being erased, the deselected erase blocks, are grounded so that the cells in the deselected erase blocks are not erased.

In large memory arrays, there is an increased likelihood that one or more cells will be defective. There exists various techniques to correct or otherwise compensate for such defective cells so that the memory will continue to be functional. However, there are certain cell failure mechanisms that interfere with the operation of the remainder of the memory and thereby effectively prevent proper memory operation. This is especially true in memory arrays having separate erase blocks where a cell failure in one block may prevent proper operation of the remaining erase blocks.

The present invention is particularly applicable to large memory arrays having separate erase blocks. The large arrays can contain cells with certain failure modes which would ordinarily prevent proper operation of conventional memories, but which do not prevent operation of a memory using an array in accordance with the present invention. These and other advantages of the present invention will become apparent to those skilled in the art upon a reading of the following Detailed Description of the Invention together with the drawings.

SUMMARY OF THE INVENTION

An arrangement of flash memory cells including a plurality of erase blocks is disclosed. The erase blocks each include flash memory cells arranged into an array of rows and columns, with the cells in a column connected to bit lines common to each erase block and with the cells in a row connected to a common word line. Each of the erase blocks has either a single common source line or a group of common source lines.

The arrangement further includes a source line decoder circuit comprising a separate control transistor associated with each of the common source lines, with the control transistor having an input terminal connected to the associated source line and an output terminal connected to a common global source line and a control terminal for receiving a control signal that causes the transistor to switch between a conductive and non-conductive state. When a cell of a selected erase block is being read, programmed or erased, the control transistors associated with the other or deselected erase blocks are switched to the non-conductive state so that the associated source line will be at a high impedance level. The high impedance level will reduce the possibility that a defective cell present in one of the deselected erase blocks will interfere with the operation of the selected erase block.

DETAILED DESCRIPTION OF THE INVENTION

Referring again to the drawings,FIG. 4is a plan view of the layout of a portion of a segmented flash cell array34suitable for use in the present invention. Array34is comprised of cells10as depicted inFIG. 1. Atypical array would be much larger than exemplary array34. The array is divided into rows and columns. The cells10located in a particular row have their control gates all connected to an associated word line. The cells10located in a particular column have their drain regions connected to a particular bit line.

Array34includes three erase blocks (sometimes referred to as erase segments), Blocks0-2, each of which has separate source lines that permit each of the erase blocks to be separately erased. Each erase block includes four separate rows of flash cells10. Byway of example, Blocks0-2includes four rows associated with word lines WL0-WL3, WL4-WL7and WL8-WL11, respectively. Further, all of the erase blocks include a set of twelve common columns of cells, namely, the twelve columns associated with bit lines BL0-BL11. Thus, each of the erase blocks can be viewed as including an array of flash cells. Bit lines BL0-BL11are common to all three erase blocks.

Array34is fabricated using a single metal layer process so as to simplify the fabrication process. As is well known, in a single metal layer process, it is not possible for two metal tracks to cross over one another. Typically, connections are made in one direction, such as the vertical direction, using metal tracks and in another direction, such as the horizontal direction, using non-metal tracks, such as doped semiconductor tracks.

The erase blocks each include a source line structure which is connected to all of the source regions of the cells located in the erase blocks. The source line structure includes a plurality of horizontal source lines which function to interconnect all of the source regions of cells located in one of the rows. The source line structure further includes vertical source lines and source straps which function to interconnect all of the source regions of cells located in one of the columns. The horizontal source lines are doped semiconductor source line segments intermediate two adjacent word lines. By way of example, Erase Block2includes a first horizontal doped semiconductor segment SD1intermediate word lines WL10and WL11and a second doped segment SD2intermediate word lines WL8and WL9. The two doped source line segments SD1and SD2of Erase Block2extend across the entire width of the array and contact the common source regions of cells10on either side of the source line segments. Thus, for example, source line segment SD1of erase Block2is connected to the common source regions of cell10A and10B in the rows associated with word lines WL11and WL10, respectively, and to all of the other cells located in those rows. Doped source line segment SD2is connected to the common source regions in the cell10located in the two rows associated with word lines WL8and WL9.

The two doped source line segments SD1and SD2of Erase Block2are connected to a vertical metal source line SL2by way of contacts36A and36B. Metal source line SL2extends over Erase Blocks0and1and out of the array34so that the sources of the cells in Erase Block2can be connected to a source line decoder circuit (not depicted) external to the array34. Line SL2does not make contact with either erase Block0and1.

FIG. 5is a schematic diagram showing the series resistances associated with the doped source lines SD1and SD2of Erase Block2. Source line SD1is represented by series-connected resistors R1A-R15A of equal value, with each resistor representing the source line resistance between adjacent cell columns. Similarly, resistors R1B-R15B represent the source line resistance of doped source lines SD2. In order to reduce the adverse effects of such resistance, the doped segments are periodically connected together a fixed number of bit lines by a vertical metal track. In theFIG. 4embodiment, the doped segments SD1and SD2of erase Block2are connected together at one location by metal source line SL2intermediate bit lines BL7and BL8. The diffused segments SD1and SD2are further connected together at a location intermediate bit lines BL3and BL4by a pair of metal source straps38A and38B. Preferably, the doped source lines are connected together by either a metal source line or a metal source strap every N number of bit lines, with N being equal to four in theFIG. 4embodiment. Although two straps may be used at one location to simplify fabrication, the two straps are electrically equivalent to a single strap so that the second strap may be deleted. Similarly, source strap38C is positioned adjacent metal source line SL2and thus also does not function to reduce the resistance, but is present to simplify the manufacturing process.

As can be seen inFIGS. 4 and 5, each erase block is provided with multiple source lines. The metal source lines extend out from the array34and are electrically connected together and to a source line decoder circuit (not depicted) which permits a selected erase block to be erased. As can be seen inFIGS. 4 and 5, Erase Block2includes the previously-described metal source line SL2and an edge metal source line SL2E which is electrically connected to the two doped source lines SD1and SD2at the edge of array34. The edge metal source lines SLE2is electrically connected to metal source line SL2outside the array, typically near the source line decoder circuit.

Erase Block1(FIG. 4) includes four rows of cells10associated with word lines WL4-WL7and a pair of doped source lines SD3and SD4. Lines SD3and SD4are connected together at one location intermediate bit lines BL3and BL4by a metal source line SL1. Metal source line SL1extends over, but does not make electrical contact with, erase Block0and extends out of the array34for connection to the source line decoder circuitry external to the array34.

Erase Block1further includes a metal source strap38D located four bit lines over from metal source line SL1and adjacent to bit line BL0. A further metal source strap38E is located four bit lines away in the opposite direction, intermediate bit lines BL7and BL8. Another metal source strap38F is located another four bit lines away adjacent bit line BL11. Finally, a second metal source line SL1E, located at the edge of the array, functions to connected the doped source lines SD4and SD5together and to the source line decoder external to the array.

Erase Block0includes a pair of doped source lines SD5and SD6which are associated with four rows of cells10. Each row has an associated word line WL0-WL3. Block0includes the same twelve columns as are present in Blocks1and2including the columns associated with bit lines BL0-BL11. A first metal source line SL0A is connected to the doped source line segments SD5and SD6at a location adjacent bit line BL0. A second metal source line SL0B located adjacent bit line SL0B is located at the other end of the array adjacent bit line BL11. Since the two metal bit lines SL0A and SL0B are located at the opposite ends of that array, it is not necessary to provide edge metal source lines, such as lines SL0E and SL1E used in connection with Blocks0and1. Erase Block0includes a first metal source strap38F located adjacent bit line BL3and a second metal source line38G, both interconnecting the diffused source lines SD5and SD6.

As previously noted, the metal lines of the array occupy a significant amount of chip area. Thus, in order to reduce the amount of area occupied by the metal source lines and the metal source straps, the two lines and straps are positioned in vertical alignment where possible. By way of example, metal source line SL1and metal source strap38B are in alignment so that the horizontal area occupied is reduced. As a further example, metal source line SL0A and metal source strap38D are aligned so as to conserve space.

TheFIG. 5diagram of Erase Block2illustrates that no cell is more than two bit lines BLN away from either metal source line going to the outside (as SL2E or SL2) or a strap (as38A or38B). This limits the maximum source line resistance for a worst case cell10, such as cell10C, to less three time R, where R is equal to the value of any of the individual source line resistances R1A-R15A. The metal source straps38interconnecting the doped source lines SD1and SD2function to further reduce the maximum source line resistance. The metal source straps and the metal source lines are located such that they alternate a fixed number of bit lines, such as four bit lines in theFIGS. 4 and 5embodiment.

It can be seen from examination of theFIG. 5array that cell10A will have a source line resistance not greater than the value of equivalent resistor R1A. Other cells10of the array will have a greater resistance, with the overall performance of the array being limited by the cell with the worst case resistance.FIG. 6is a schematic diagram of an equivalent circuit of a portion of erase Block2of theFIGS. 4 and 5array. Exemplary cell10C is shown since this cell is located such that it is among the cells which will have the largest source line resistance. Cell10C is disposed three equivalent resistances (R1A-R3A) away from metal source line SL2E hence the resistor value 3R is shown connected between the cell and the source line. Cell10C is further disposed two equivalent resistances (R4A-R5A) away from metal source strap38A/38B hence the value 2R shown connected to the cell. The strap38A/38B is shown connected to the metal source line SL2by way of parallel resistors 5R which represent equivalent resistors R6A-R10A and R6B-R10B, respectively. Finally, equivalent resistor 5R representing resistors R1B-R5B, is shown connected metal source line SL2E and metal strap38A/38B. The two metal source lines SL2E and SL2are connected together by a line40external to array34.

The total effective resistance between the source of cell10C and the source line SL for erase Block2can readily be calculated using simple arithmetic. The total effective resistance is equal to parallel combination of 3R∥(2R+5R/3). This gives an effective approximate equivalent source resistance of 1.6R. If the metal source strap were deleted, the worst case cell would be cell10E, with an equivalent source resistance of approximately 2.5R.

FIG. 7depicts a portion of another array42in suitable for use in the present invention. Only a corner portion of the array is depicted, including a portion of an Erase Block0and an Erase Block1. Erase Block1has one metal source line SLN depicted, with there being additional metal source lines also associated with Block1. Erase Block0has one metal source line SLN+1 depicted, with there being additional metal source lines associated with Block1. Those lines, which extend over Block0but do not make contact to Block0, are also not depicted in that portion of array42shown in FIG.7.

As was the case with theFIG. 4array, the doped source lines of each erase block are connected together every four bit lines by either a metal source line or by a metal source strap. By way of example, erase Block0has two associated doped source lines SDN and SDN+1 which are connected together by metal straps38and source lines SLN+1 every four bit lines.

In a typical flash cell array, cells located at the edge of the array are much more subject to processing variations than the cells not located at the edge. Because of this, it is common to refrain from using the cells at the array edge. Such cells, which extend around the perimeter of the array, are sometimes referred to as dummy cells. Array42is surrounded by dummy cells including the two columns of cells depicted inFIG. 7at one edge of the array and two columns not depicted at the opposite edge of the array. The depicted columns are associated with bit lines BLX and BLY. In addition, array42includes two rows of dummy cells located at opposite edges of the array, including two rows not depicted and two rows shown in FIG.7. The depicted rows are associated with word lines WLX and WLY.

The dummy cells have doped source lines which interconnect the source regions of the dummy cells. The doped source lines include lines SDZ1-SDZ5of the two dummy columns and lines SDX and SDY of the two dummy rows. Typically, the bit lines BLX and BLY are not accessed since the dummy cells are not supposed to be programmed. If the source lines of the dummy cells, such as source line SDZ5were to be connected to the source lines of the array, such as line SDN, the dummy cells would be erased when the array is erased. Since the dummy cells cannot be programmed but would otherwise be erased, the dummy cells are likely to become overerased so that they will conduct cell current even when the associated word line is grounded. The flow of current through an overerased cell will usually prevent proper operation of the array. In order to ensure proper operation of the array, the doped source lines of the dummy rows should not be in electrical contact with the doped source lines of the corresponding rows of the functional cells of the array. By way of example, diffused source line SDN of the rows associated with word lines WLN and WLN+1 does not extend to the diffused source line SDZ5. In addition, the dummy cells located in the dummy rows would have a tendency to be erased when functional cells located in the same column are repetitively programmed. This phenomenon is sometimes referred to as bit line disturb where the dummy cells sharing a bit line with functioning cells would have some tendency to become overerased and thus become leaky. In order to reduce the likelihood of this occurring, the length of the source lines of the dummy cells are made short so as to minimize the possibility of a leakage path between bit lines. By way of example, source lines SDX and SDY of the two dummy rows are not connected so as to minimize any adverse effects of bit line disturb.

FIG. 8show a further embodiment of an array44in showing essentially only the source line connections. Array44is comprised of eight erase Blocks0-7, with each of the erase blocks having 128 rows of flash cells. Thus, array44has a total of 1024 rows of cells. Array44also has 1024 columns of cells so that the total array capacity is one Megabit. Each erase block can be considered an array of cells having 128 rows and 1024 columns. As can be seen fromFIG. 8, erase Blocks0-3and erase Blocks4-7are mirror images of one another.

Each of the erase blocks has several vertical metal source lines SLN which are electrically connected to all of the horizontal doped source lines (not depicted) of the erase block. The metal source lines SLN are provided a minimum of every 64 bit lines for each erase block, with the variation being due to the presence of edge metal bit lines. By way of example, Erase Block4will have 16 metal source lines, including lines SL4A, SL4B, SL4C . . . and SL4O. Each of the erase blocks also includes several metal source straps which electrically connect all of the diffused source lines of the erase block together. Erase Block4includes, for example, metal straps46A-46I. The metal source straps are internal to the erase blocks and do not extend past the edges of the associated erase block. There are typically three metal source straps intermediate adjacent metal source lines so that there is either a metal source strap or a metal source line located every 16 bit lines of each erase block.

The metal source lines SL4A-SL4O of Erase Block4extend over Erase Blocks5-7and away from array44where they are connected together to form a common source line for Erase Block4. The metal source lines from Block4extend over the other blocks along a path which is parallel with the bit lines of the block and orthogonal to the word lines. As will be explained, the metal source lines from Erase Block4(and the other erase blocks) are coupled to a source lined decoder circuit external to array44(not depicted).

Erase Block5includes metal source lines SL5A-SL5which are also spaced apart about every 64 bit lines. The metal source lines of Erase Block5extend over Erase Blocks6and7and out of array44where they are electrically connected to the source line decoder. Erase Block5also includes metal source straps48A-48I. The straps, like the straps of Block4, interconnect all of the horizontal doped source lines of Block5. There are typically three metal source straps intermediate adjacent metal source lines, with there being either a metal source line or a metal source strap every sixteen bit lines.

Erase Blocks6and7include metal source lines (SL6A-SL6P and SL7A-SL7P, respectively) and metal source straps (50A-50I and52A-52I, respectively) which are positioned in the same manner as the lines and straps in Blocks4and5. Note that the location of the metal source straps are selected so that they generally align with the metal source lines of adjacent erase blocks. By way of example, metal source straps52B,50B, and46B of Erase Blocks7,6and4, respectively, are generally aligned with metal source line SL5B of Block5. As a further example, metal source straps46C,48C and50D are generally aligned with metal source line SL7B.

As previously noted, Blocks0-3and Blocks4-7are arranged so that they are mirror images of one another. The metal source lines of Blocks0-3all extend toward the lower edge of array44and the metal source lines of Blocks4-7all extend in the opposite direction towards the top edge of the array. By dividing the erase blocks into two groups of blocks with each group of blocks having metal source lines extending in the opposite direction, a reduction in the amount of chip area occupied by the metal source lines is reduced. By way of example, metal source line SL3C of Erase Block3and metal source line SL4C of Erase Block4can be made to occupy the same vertical path on array44since they extend in opposite directions.

FIG. 9is a schematic diagram of an exemplary section of one embodiment of an erase source decoder circuit54which can be used in connection with an array having a total of three erase blocks. Circuit54includes a set of N channel source line decode transistors56,58and60connected to the respective source lines of the array. The function of the decode transistors is to connect the source lines coming from a common selected erase block of the array to the same desired potential/condition and to connect the source lines from the deselected erase blocks to a desired potential/condition.

By way of example, the source lines from Erase Block0, including depicted lines SL0A and SL0B are connected to decode transistors56A and56B, respectively. Transistors56A and56B, and other decode transistors not depicted which are connected to any additional source lines of Erase Block0and have their gates connected to a common line which carries control signal S0. Source lines from Erase Block1, including depicted lines SL1A and SL1B, are connected to decode transistors58A and58B, respectively. Transistors58A and58B, and any other transistors not depicted which are connected to any additional source lines of Erase Block1, have their gates connected to a common line which carries control signal S1. Erase Block2has one source line SL2A depicted inFIG. 9which is connected to transistor60. A control line carrying signal S2is connected to the gate of transistors60and to the gate of any additional decode transistors which receive other source lines of Erase Block2. All of the transistors of source decoder circuit54controlled by control signals S0, S1and S2have their source electrodes connected to a common Global Source line.

Each of the source lines of Erase Blocks0,1and2are also connected to separate N channel transistors64,66and68which function to selectively connect the source lines to a common Deselected Source Bus. As will be explained, the Deselected Source Bus may be set to some voltage or may be grounded. By way of example, transistors64A and64B are connected to source lines SL0A and SL0B of Erase Block0. The gates of transistors64A and64B are controlled by signal {overscore (S)}0which is the complement of signal S0. Source lines SL1A and SL1B of Erase Block1are connected to transistors66A and66B, respectively, with transistors66A and66B having their gates connected to a common line which carries signal {overscore (S)}1, the complement of signal S1. Transistor68is controlled by signal {overscore (S)}2, the complement of signal S2, and is connected to source line SL2A of Erase Block2.

Table 2 below shows the manner in which the source decoder circuit54is controlled in basic memory operations. In a memory read operation, all of the source lines of all of the erase blocks are to be connected to ground. Thus, as can be seen from

Table 3 below shows the conditions for the other portions of the array, including word lines and bit lines, for carrying out memory read, program and erase operations. Although the erase mechanism described utilizes a grounded gate, negative gate erase could also be used as will be described. As can be seen from Tables 2 and 3, and as noted above, in memory read operations, the selected source line (the source lines of the erase block containing the cells to be read) are grounded as are the deselected source lines (the source lines of the other erase blocks). This is accomplished by setting signals S0, S1and S2to +5 volts which causes transistors56A,58A,60,56B and58A to be conductive thereby connecting all three source lines SL0, SL1and SL2to the Global Source line. The Global Source line is at ground potential so that all of the source lines are grounded. Signals {overscore (S)}0, {overscore (S)}1and {overscore (S)}2are all at ground potential during read operations so that transistors64A,66A,68,64B and66B are off.

In addition, the word line associated with the cells being read (the selected word line) is connected to +5 volts and all of the other word lines in the array are grounded. The bit lines of the cells being read (eight cells if the memory word length is eight bits) are connected to a small positive voltage such as +1 volt. All other bit lines of the array are left floating, as can also be seen from Table 3. This combination of conditions will cause the selected cells to either conduct or not conduct current based upon their programmed state.

In order to program a cell (or cells), a relatively large positive voltage of +11 volts is applied to the word line associated with the cell being programmed. All of the other word lines of the array, including those in the same erase block, are grounded. The bit line of the cell to be programmed is connected to +6 volts. If the cell is to be left in the erased state, the bit line is connected to +1 volt. As shown in Table 3, the deselected bit lines are all left floating during programming operations.

As previously noted, one feature of the present invention is to provide an array which contains separate erase blocks which can be independently erased. Table 2, above, shows the conditions of the erase source decoder when an exemplary erase block, Erase Block0, is being erased. The Global Source line is set to +10 volts. In addition, signal S0is set to +12 volts so that transistors56A and56B have sufficient gate voltage to apply the +10 volts present on the Global Source line to the source lines SL0A and SL0B associated with the selected erase block, Erase Block0. The deselected source lines, those associated with the other erase blocks, are all grounded by setting signals {overscore (S)}1and {overscore (S)}2to +12 volts thereby turning on transistors66A,68,66B. In addition, the Deselected Source Bus is grounded so that the deselected source lines SL1A, SL1B and SL2A are all at ground potential.

Table 3, above, shows the conditions of the remainder of the array in erase operations. All of the word lines, including those of the erase block being erased and the other erase blocks, are grounded. In addition, all of the bit lines of the array are left floating. Under these conditions, all of the cells in Erase Block0will be erased.

Table 3 illustrates one set of conditions for reading, programming and erasing a flash array. In that example, a cell is erased by connecting the selected source line to +10 volts, the selected word line to ground and floating the selected bit line. As previously noted, negative gate erase techniques could also be used where a negative voltage is applied to the word line of the cells being erased. That voltage is typically −10 volts to −17 volts as previously described. The bit line is left floating and a relatively small voltage VA, such as +5 volts, is applied to the source line of the erase block. As will be explained, the deselected source lines are left floating rather than being grounded as is done in conventional arrays having separate erase blocks. By floating the deselected source lines, certain defects can exist in one erase block which do not interfere with the operation of the remaining erase blocks.

FIG. 10depicts an alternative source line decoder in accordance with the present invention. Table 4

As can be seen from Table 4, when cells in Erase Block0are to be read, signal S0is set to +5 volts thereby turning on transistor70A (and any other transistors that may be connected to a source line of Erase Block0). Signals S1and S2remain at ground level so that the transistors connected to the remaining erase blocks, including transistors70B and70A, are left off. Thus, the source lines of all of the deselected erase blocks are floating. Conducting transistor70A will connect the source line SL0of Erase Block0to the Global Source line which is, in turn, connected to ground. A positive voltage of +5 volts is connected to the word line associated with the cells being read and the bit lines are connected to a small positive voltage of typically +1 volts. This will cause current to flow or not to flow in the cells being read depending upon whether the cells are in an erased or programmed state. Table 3, above, shows the conditions for the deselected word lines and bit lines during read operations.

In a programming operation where cells in Erase Block0are to be programmed, Table 4 indicates that transistor70A is turned on and transistors70B and70C are left off. The Global Source line is set to ground potential so that transistor70A will cause the source line SL0to be at ground potential. The deselected source lines SL1and SL2will be floating. The word line associated with the cells being programmed is set to a relatively large positive voltage of typically +11 volts. Since this voltage (+11 volts) is generated for programming, the voltage is available for generating signal S0used to on transistor70A. Signal S0could also be +5 volts since transistor70A is switching at a voltage near ground potential. Further, the bit line associated with the cells to be programmed will be set to a medium level voltage such as +6 volts. If the cell is to be left in the erased state, the associated bit line is grounded. This combination of conditions will permit the selected cells of Erase Block0to be programmed.

Continuing, Table 4 indicates that all the cells of Erase Block0are erased by setting signals S0, S1and S2such that transistor70A of theFIG. 10erase decoder is made conductive and the remaining transistors70B and70A are off. The Global Source line is set to a relatively low positive voltage VAwhich is typically approximately +5 volts or some other value which will not be so large as to result in cell voltage break down. Thus, source line SL0of Erase Block0will be at voltage VAand the source lines of the remaining erase blocks, lines SL1and SL2will be floating. The word lines of Erase Block0are all set to a relatively large negative voltage, such as −10 volts, and the bit lines of the array are all left floating. This will result in all of the cells of Erase Block0being erased by way of the previously-described negative gate erase technique.

It is possible that a failure of a cell in one erase block will adversely affect operation of the remaining erase blocks. Under certain conditions, a flash cell will conduct current when it should be non-conducting. By way of example, if a cell has been over erased, the cell will have a negative threshold voltage so that the cell will conduct even when the gate-source voltage is 0 volts. Other conditions may occur which will cause a cell to be “leaky” and conduct current when the cell should be non-conductive. When a cell of a deselected erase block is improperly conducting current, the cell has a tendency to clamp the bit line voltage to the source voltage. This can cause the bit line voltage to approach ground potential should the source lines of the deselected erase blocks be set to ground potential as is illustrated in Tables 2 and 3, above. Since the bit lines are common to all of the erase blocks in an array, a defective cell in one block will have a tendency to interfere with the reading, programming and erasure of the other blocks. By floating the source lines of deselected erase blocks during program or read, as shown in Table 4, the adverse effects of a leaky or over erased cell in the deselected blocks on the cells of selected erase blocks will be greatly reduced.

FIG. 11depicts a flash cell array arrangement using word line control circuitry for carrying out negative gate erase. Exemplary Erase Blocks0-1are depicted, with there being a total of eight erase blocks, including Erase Blocks2-7which are not shown. Each erase block has sixty-four word lines WL, a set of bit lines BL common to all of the erase blocks and separate source lines (not depicted). The word lines are grouped in eights, with each group of eight being connected to a separate X Decoder Stage72. The functionality provided by X Decoder Stages72is conventional. By way of example, FIG. 6 of the previously noted U.S. Pat. No. 5,077,091 discloses a decoder stage which provides the same output signals as provided by X Decoder Stages72. Exemplary X Decoder Stage72A is connected to word lines WL0-WL7. There are a total of 512 word lines WL0-WL511, with word lines WL0-WL63being associated with Erase Block0and word lines WL64-WL127being associated with Erase Block1and the remaining word lines WL12B-WL511being associated with the remaining six erase blocks that are not depicted.

Each of the word lines WL0-WL511also has a separate respective P channel erase transistor T0-T511connected to it, with the transistors associated with one of the erase blocks being controlled by a common control signal. Thus, erase transistors T0-T63of Erase Block0have their gates connected to a line that carries control signal G0and erase transistors T64-T127of Erase Block1have their gates connected to a common line that carries control signal G1. In addition, all of the erase transistors associated with an erase block have their sources connected to a common voltage line. Thus, for example, erase transistors T0-T63are all have their sources connected to a common line that carries a voltage V0.

The details of the X Decoder Stages72ofFIG. 11are shown in FIG.13. As will be explained in greater detail, the X Decoder Stages72provide outputs which are either at a positive voltage equal to the X Decoder Stage72supply voltage VP, ground potential or a high impedance (at least more than 10 kΩ). The high impedance state of the X Decoder Stages72is used when the erase transistors T0-T511function to apply a negative voltage to the word lines of an erase block during an erase operation, as will be explained in greater detail.

The conditions for carrying out read, program and erase operations on theFIG. 11array arrangement are set forth in Table 5, below. Erase Block0is

In order to select one of the 512 word lines, each of the X Decoder Stages72receives a total of twenty-four predecode signals. These predecode signals are developed by predecoding circuitry (not depicted) which receives the nine address bits supplied to the X Decoder and converts the nine address bits to twenty-four predecode signals, including signals XA0-XA7, XB0-XB7and XCH0-XCH7. Signals XA0-XA7and XB0-XB7, are used in combinations of two to select one of the sixty-four X Decoder Stages72. Signals XCH0-XCH7are provided to each of the sixty-four X Decode Stages72to select one of the eight word lines associated with each stage. By way of example, X Decode Stage72A ofFIG. 13receives predecode signals XA0and XB0which function to select that stage from the sixty-four stages. Stage72A also receives predecode signals XCH0-XCH7which are used to select one of the eight word lines WL0-WL7associated with Stage72A.

The construction and operation of exemplary X Decode Stage72A ofFIG. 13will now be described since such description is helpful in understanding Table 5. Predecode signals XA0and XB0are connected to the inputs of a NAND gate74, the output of which is connected to a level shifting pass transistor76which will pass any voltage having a magnitude which is below the supply voltage VCCconnected to its gate. Pass transistor76is, in turn, connected to a total of eight additional pass transistors, including N-channel transistor78A associated with decode circuitry for word line WL0and including N channel transistor78B associated with decode circuitry for word line WL7.

Transistor78A has its gate connected to receive predecode signal XCH0, with predecode signal XCH0also being connected to the gate of a P channel transistor80A. Transistor80A is connected between transistor78A and the X Decoder supply voltage VP. Transistors78A and80A are connected to a common node79A which is near ground potential when predecode signals XA0, XB0and XCH0are all at a high level, otherwise node79A is at a high level. Node79A is connected to the common gate connection of a P channel transistor84A and an N channel transistor88A. These transistors form an inverting stage, the output of which is connected to word line WL0. Transistor84A is connected between the X Decoder supply voltage VPand the inverting stage output and transistor88A is connected between the output, by way of a P channel transistor86A, and the circuit common. As will be explained, transistor86A functions to protect N channel transistor88A from the negative voltage which is present on the word line WL0during erase operations.

In addition to being connected to word line WL0, the output of the inverting stage is connected to the gate of a feedback P channel transistor82A, with transistor82A providing positive feedback which pulls the input of the inverting stage, node79A, towards supply voltage VPwhen the output of the inverting stage, WL0, goes low. This ensures that node79A will be pulled up to a sufficiently high voltage to turn off P channel transistor84A.

The remaining seven sections (only the last section is depicted) of X Decoder Stage72A for driving word lines WL1-WL7are also connected to the output of NAND gate74and pass transistor76. Otherwise, the construction of the sections is the same. The seven sections each receive respective ones of predecode signals XCH1-XCH7, SO that one of the eight word lines WL0-WL7can be selected.

Returning to the description of a read operation (Table 5 andFIG. 11) in connection with Erase Block0, the signals G0-G7applied to the gates of all of the P channel erase transistors T0-T127(and those not depicted) are set to +5 volts. Thus, the transistors will be non-conductive. In addition, the X Decoder supply voltage VPis set to +5 volts. A read address is decoded causing predetermined predecode signals to become active. Assuming, for example, that a cell associated with word line WL7is to be read, the predecode signals XA0and XB0will go high thereby selecting X Decoder Stage72A. This will cause the output of pass transistor76to go low (FIG.13). In addition, predecode signal XCH7will go high thereby turning on pass transistor78B and causing node79B to go low. The remaining predecode signals, XCH0-XCH6will remain low. Transistor84B will turn on so as to pull up selected word line WL7to voltage VP, which is set to +5 volts. Note that voltage VNISOis set to −2 volts (Table 5) thereby causing P channel transistor86B to be conductive. However, since transistor88B is off, the word line WL7voltage will still be +5 volts.

As indicated in Table 5, the deselected word lines in the selected Erase Block0are set to ground potential. This is accomplished by the nine bit address causing the X Decoder to set the predecode signals XCH0-XCH6to a low value, as previously noted. Thus, for example, signal XCH0will cause transistor78A to turn off thereby isolating node79A from the low output of NAND gate74. Signal XCH0will also cause transistor78A to become conductive and pull node79A up to voltage VCCless the threshold voltage of transistor79A. This will cause transistor88A to become conductive, thereby causing the voltage on word line WL0to drop. This, in turn, will cause transistor82A to turn on thereby pulling node79A up further to voltage VP. As previously noted, voltage VNISOis set to −2 volts so that transistor86A will also be conductive. Accordingly, transistors86A and86B will both be conductive and will pull word line WL0down to ground potential as will the corresponding transistors associated with deselected word lines WL1-WL6of Erase Block0.

With respect to the deselected word lines of the remaining erase blocks, Table 5 indicates that these word lines are also set to ground potential. For all of these deselected erase blocks, the predecode signals XA and XB will such that the output of the corresponding NAND gate74output will be at a high level. For those deselected word lines where predecode signal XCH7is used, that predecode will be at a high level in the present example so that transistor78will be on thereby connecting the high output of NAND gate74to node79. For those selected word lines where predecode signals XCH0-XCH6are used, those predecodes will be at a low level. This will cause the associated transistor78to be off thereby isolating node79from the output of the NAND gate74. In addition, associated transistor80will be turned on by the low level predecode so that node79will be pulled up to voltage VP. In either case, a high voltage at node79will cause the associated word line to be at ground potential.

As indicated by Table 5, in read operations, the selected source line, SL0for Erase Block0, is grounded. The source lines of the remaining Erase Blocks1-7, including source line SL1, can also be grounded as shown in Table 5. However, it is an objective of the present invention to cause the deselected source lines to be left floating, as also shown in Table 4. This can be accomplished, for example, using the source decoder circuit of FIG.9. With the array configured as described, a selected cell (or group of cells) associated with a word line (such as line WL7) of Erase Block0can be read.

Table 5 also shows the conditions for programming a cell or group of cells of theFIG. 11array arrangement. Again, all of the P channel erase transistors T0-T511are turned off since control signals G0and G1(and signals G2-G7not depicted) are all set to a positive voltage (+11 volts). The X Decoder72supply voltage V2is set to +11 volts and the decoding circuitry is caused to apply this voltage to the selected word line based upon the address being used in the programming operation. Thus, for example, if word line WL7is the selected word line, predecode signals XA0, XB0and XCH7(FIG. 13) are all at a high level so that transistor84B will pull word line WL7up to voltage VPset to +11 volts.

The deselected word lines WL0-WL6of selected Erase Block0are set to ground potential in the programming operation since the predecode signals XCH0-XCH6associated with the deselected word lines will be at a low level. Voltage VNISOis set to −2 volts according to Table 5 therefore both transistors86B and88B will be turned on connecting these deselected word lines to ground as was the case during read operations. In addition, the word lines of the deselected erase blocks will be at ground potential for the same reasons previously set forth in connection with the description of an exemplary read operation. However, it is again an object of the present invention to have the source line of the deselected erase blocks be left floating in programming operations as is the case of these source lines during read operations.

In erase operation, a single erase block of the array may be erased as previously described. As can be seen in Table 5, if Erase Block0is the selected block to be erased, signal G0is set to −12 volts thereby turning on erase transistors T0-T63(FIG.12). In addition, voltage V0is set to −10 volts so that all sixty-four word lines of Erase Block0are connected to −10 volts by the associated erase transistor T0-T63.

As can also be seen from Table 5, all sixty-four of the X Decoder Stages72of the array have their common supply voltage VPset to ground potential. In addition, voltage VNISOis set to ground potential so that the P channel transistor86(FIG. 13) in each of the X Decoder Stages72is turned off thereby isolating the N channel transistors88from the negative voltage which is applied to the word lines of Selected Erase Block0.

The erase transistors T64-T511of the deselected erase blocks are all turned off since the voltage applied to the gates, including G1, is at ground potential. In addition, the associated X Decoder Stage72output is isolated from the word lines so that the word lines of the deselected erase blocks will be at a high impedance level. The deselected word lines will assume a voltage ranging from ground potential to the threshold voltage VTof the P channel transistor84located in the associated X Decoder Stage72, as indicated in Table 5. This threshold voltage is typically +1 volt.

The source line of the selected Erase Block0, source line SL0, is set to voltage VAwhich is typically +5 volts. By way of example, the Global Source line of theFIG. 9source decoder circuit will be set to voltage Vaand signal S0is made to turn on transistors56A and56B. In addition, the voltage of the source lines associated with the deselected erase blocks, such as source line SL1, are set to a voltage VB. This is accomplished by setting the Deselected Source Bus of theFIG. 9decoder circuit to voltage VBand turning on the transistors66A,66B and68associated with the selected source lines. Voltage VBis selected to be intermediate threshold voltage VTand voltage VAapplied to the selected source line. Thus, if threshold voltage VTis +1 volt and voltage VAis +5 volts, VBmay be set to +3 volts. If voltage VBis set too high, there will be an increased tendency for the cells of the deselected erase blocks to be slightly erased each time one of the other erase blocks is erased. This phenomena is sometimes referred to as source erase disturb. If, on the other hand, voltage VB is too low, there will be a tendency to turn on the deselected flash cells, or to cause them to leak, since the control gate voltage of the flash cells will typically be at voltage VTdue to the previously described influence of the associated X Decoder Stage72. These conditions will cause the selected Erase Block0to become erased. As also indicated by Table 5, the deselected course lines can also be placed in a floating state in erase operations.

FIG. 12shows an alternative embodiment of an array arrangement for use in the subject invention. Those elements of the alternative embodiment that are similar to theFIG. 11embodiment have the same numerical designation. This array arrangement also utilizes negative gate erase during erase operations. However, rather than having a separate control signal G0-G7for each of the eight Erase Blocks0-7, there is single control signal G common to all eight blocks. Other aspects of theFIG. 12embodiment are the same as that ofFIG. 11with the exception of the differences noted in the following description. Thus, theFIG. 12array arrangement is somewhat simpler to implement than is theFIG. 11embodiment.

Table 6 shows the conditions for reading, programming and erasing theFIG. 12array arrangement. In read operations, signal G is set to +5 volts so that all of the erase transistors T0-T511are turned off. Similarly, in program operations, signal G is set to +11 volts so that all of the erase transistors are turned off. The X Decoders stages72used in theFIG. 12embodiment are the same used in the previously describedFIG. 11embodiment. Since the erase transistors T0-T511are in the same corresponding disabled state as in theFIG. 11embodiment, the conditions created by the X Decoder Stages72in read and program operations are the same and need not be further described.

In erase operations, assume that Erase Block0is to

As also indicated by Table 6, the selected source line SL0is set to voltage VAwhich, as previously noted, is typically +5 volts. The deselected source lines, including source line S1, are connected to voltage VBwhich, as also previously noted, is set to +3 volts, a voltage selected to be greater than the threshold voltage of the X Decoder Stage72P channel transistor86(FIG. 13) and lower than voltage VA. Again, voltage VNISOis set to 0 volts thereby turning off transistor86of the X Decoder Stages72and isolating the N channel transistors88from the negative voltage applied to the word lines WL0-WL63of Erase Block0. Although not set forth in Table 6, the bit lines common to all of the erase blocks are left floating. This combination of conditions will cause the cells of Erase Block0to be erased.

As indicated by Table 6, in erase operations, the deselected source lines can also be left floating. This approach is preferred since, as previously noted, a defect is a deselected erase block will not adversely affect the operation of the selected erase block.

Thus, a novel flash cell array arrangement divided into array segments having separate source lines and associated source line decode circuitry has been disclosed. Although a various embodiments of the subject invention have been described in some detail, it is to be understood that certain changes can be made by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.