Integrated circuit devices including a vertical field-effect transistor (VFET) and a fin field-effect transistor (FinFET) and methods of forming the same

Integrated circuit devices and methods of forming the same are provided. Integrated circuit devices may include a channel region protruding from a substrate in a vertical direction, a first source/drain region, and a second source/drain region. The first source/drain region may vertically overlap the channel region. The first and second source/drain regions may contact a first portion and a second portion of the channel region, respectively, and a third portion of the channel region between the first and second portions may include a first channel region extending longitudinally in a first horizontal direction that is perpendicular to the vertical direction and a second channel region extending longitudinally in a second horizontal direction that is perpendicular to the vertical direction and traverses the first horizontal direction. The integrated circuit devices may also include a gate structure on opposing vertical sides of the channel region.

FIELD

The present disclosure generally relates to the field of electronics and, more particularly, to vertical field-effect transistor (VFET) devices.

BACKGROUND

Various structures and manufacturing processes of VFET devices have been researched because of their high scalability. It, however, may be difficult to form VFETs having different channel lengths.

SUMMARY

According to some embodiments of the present inventive concept, integrated circuit devices may include a channel region protruding from a substrate in a vertical direction that is perpendicular to an upper surface of the substrate, a first source/drain region, and a second source/drain region. The first source/drain region may vertically overlap the channel region. The first and second source/drain regions may contact a first portion and a second portion of the channel region, respectively, and a third portion of the channel region between the first and second portions may include a first channel region extending longitudinally in a first horizontal direction that is perpendicular to the vertical direction and a second channel region extending longitudinally in a second horizontal direction that is perpendicular to the vertical direction and traverses the first horizontal direction. The integrated circuit devices may also include a gate structure on opposing vertical sides of the channel region.

According to some embodiments of the present inventive concept, integrated circuit devices may include a Fin field-effect transistor (FinFET). The FinFET may include a channel region protruding from a substrate in a vertical direction that is perpendicular to an upper surface of the substrate, a first source/drain region, and a second source/drain region. The first source/drain region may vertically overlap the channel region. The FinFET may also include a gate structure on opposing vertical sides of the channel region, and the gate structure may be curved in plan view.

According to some embodiments of the present inventive concept, integrated circuit devices may include a channel region protruding from a substrate in a vertical direction that is perpendicular to an upper surface of the substrate. The channel region may include first and second channel regions that are spaced apart from each other in a first horizontal direction and extend longitudinally in a second horizontal direction that is perpendicular to the vertical direction and traverses the first horizontal direction. The integrated circuit devices may also include a first source/drain region and a second source/drain region. The first source/drain region may vertically overlap the channel region. The integrated circuit devices may further include a gate structure extending on opposing vertical sides of the channel region and an insulating layer. The first source/drain region and the gate structure may be spaced apart from each other in the vertical direction by a gap between the first source/drain region and the gate structure, and the insulating layer may be in the gap.

DETAILED DESCRIPTION

According to some embodiments of the present inventive concept, a single integrated circuit device (e.g., an integrated circuit chip) may include both a VFET and a non-VFET (e.g., a planar transistor, a Fin field-effect transistor (FinFET)) such that transistors having different channel lengths can be provided.

FIG. 1Ais a perspective view of a FinFET device according to some embodiments of the present inventive concept.FIGS. 1B and 1Care perspective views of portions of the FinFET device ofFIG. 1Aaccording to some embodiments of the present inventive concept.FIGS. 2A and 2Bare cross-sectional views taken along the lines A-A′ and B-B′ ofFIG. 1A, respectively, according to some embodiments of the present inventive concept.

Referring toFIGS. 1A through 2B, the FinFET device may include a channel region22on a substrate100. The substrate100may include opposing surfaces, an upper surface100_U and a lower surface100_L. The upper surface100_U and the lower surface100_L of the substrate100may be parallel to each other. The substrate100may include one or more semiconductor materials, for example, Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC and/or InP. In some embodiments, the substrate100may be a bulk substrate (e.g., a bulk silicon substrate) or a semiconductor on insulator (SOI) substrate. The channel region22may include materials the same as the substrate100or may include materials different from the substrate100.

The channel region22may protrude from the substrate100in a vertical direction Z that may be perpendicular to the upper surface100_U of the substrate100. A lower insulating layer12may extend on the substrate100and on opposing vertical sides of the channel region22. In some embodiments, the lower insulating layer12may be only on lower portions of the opposing vertical sides of the channel region22, as illustrated inFIGS. 2A and 2B. The lower insulating layer12may include insulating material(s). For example, the lower insulating layer12may include silicon oxide, silicon nitride, and/or silicon oxynitride.

A gate structure24may be on the opposing vertical sides of the channel region22. Referring toFIGS. 1A and 1C, it will be understood that, in some embodiments, the gate structure24may enclose the channel region22in plan view. The gate structure24may include a contact portion24_C through which a gate voltage is applied to the gate structure24. In some embodiments, the gate structure24may be curved (e.g., bent) twice in plan view. It will be understood that “an element A being curved” (or similar language) means that the element A include two portions that are connected to each other and extend in different directions (e.g., directions perpendicular to each other). In some embodiments, an upper portion of the channel region22may protrude in the vertical direction Z beyond an upper surface of the gate structure24, and thus the gate structure24may expose upper portions of the opposing vertical sides of the channel region22and an upper surface of the channel region22. The gate structure24may be spaced apart from the substrate100in the vertical direction Z by a gap, and the lower insulating layer12may be in the gap and may extend between the gate structure24and the substrate100. The lower insulating layer12may separate the gate structure24from the substrate100and thus may electrically isolate the gate structure24from the substrate100.

An upper insulating layer32may be on the gate structure24and the opposing vertical sides of the channel region22. In some embodiments, the upper insulating layer32may be only on upper portions of the opposing vertical sides of the channel region22, as illustrated inFIGS. 2A and 2B. The upper insulating layer32may include insulating material(s). For example, the upper insulating layer32may include silicon oxide, silicon nitride, and/or silicon oxynitride. In some embodiments, the upper insulating layer32may include material(s) the same as the lower insulating layer12.

First and second source/drain regions42may be on the channel region22. In some embodiments, each of the first and second source/drain regions42may be on and may contact the upper surface of the channel region22, as illustrated inFIG. 2A, and may be referred to as a top source/drain region. Each of the first and second source/drain regions42may vertically overlap the channel region22. In some embodiments, the first and second source/drain regions42may be on end portions of the channel region22, respectively, as illustrated inFIG. 1B. The first and second source/drain regions42may include a semiconductor material and/or dopant atoms (e.g., boron atoms, phosphorous atoms, arsenic atoms). In some embodiments, the gate structure24may expose an entirety of a portion of the upper surface of the channel region22, which is not vertically overlapped by the first and second source/drain regions42.

Referring toFIGS. 1A, 1B, and 2A, the first and second source/drain regions42may contact a first portion and a second portion of the channel region22, respectively, and a third portion of the channel region22between the first and second portions may include a first channel region22_1extending longitudinally in a first horizontal direction X that may be perpendicular to the vertical direction Z, a second channel region22_2extending longitudinally in a second horizontal direction Y that may be perpendicular to the vertical direction Z and may traverse the first horizontal direction X, and a third channel region22_3extending longitudinally in the first horizontal direction X. In some embodiments, the first channel region22_1and the third channel region22_3may have an equal length in the first horizontal direction X.

In some embodiments, the gate structure24may extend from the first portion of the channel region22onto the second portion of the channel region22. The first and second source/drain regions42may be spaced apart from the gate structure24in the vertical direction Z by a gap, and the upper insulating layer32may be in the gap and may be between the first and second source/drain regions42and the gate structure24. The upper insulating layer32may separate the first and second source/drain regions42from the gate structure24and thus may electrically isolate the first and second source/drain regions42from the gate structure24.

FIG. 3Ais a perspective view of a FinFET device according to some embodiments of the present inventive concept.FIGS. 3B and 3Care perspective views of portions of the FinFET device ofFIG. 3Aaccording to some embodiments of the present inventive concept.FIGS. 4A and 4Bare cross-sectional views taken along the lines C-C′ and D-D′ ofFIG. 3A, respectively, according to some embodiments of the present inventive concept.

Referring toFIGS. 3A through 4B, the FinFET device may include a first source/drain region42on a channel region22and a second source/drain region44in a substrate100. As the second source/drain region44is under the channel region22, the second source/drain region44may be referred to as a bottom source/drain region. The channel region22may vertically overlap and may contact the second source/drain region44. The second source/drain region44may include a semiconductor material and/or dopant atoms (e.g., boron atoms, phosphorous atoms, arsenic atoms). The substrate100may include a trench14adjacent the second source/drain region44to electrically isolate the second source/drain region44from other elements. In some embodiments, a trench insulating layer16may be provided in the trench14. The trench insulating layer16may include insulating material(s). For example, the trench insulating layer16may include silicon oxide, silicon nitride, and/or silicon oxynitride.

In some embodiments, parallel portions of the channel region22extending longitudinally in the first horizontal direction X may have different lengths in the first horizontal direction X to make a distance between the first source/drain region42and the second source/drain region44in the first horizontal direction X long enough for electrical isolation between the first source/drain region42and the second source/drain region44. However, it will be understood that, in some embodiments, the parallel portions of the channel region22extending longitudinally in the first horizontal direction X may have an equal length in the first horizontal direction X.

FIGS. 5A and 5Bare enlarged views of the region S ofFIG. 4Baccording to some embodiments of the present inventive concept. Referring toFIGS. 5A and 5B, the gate structure24may include a gate insulator25and a gate electrode27. The gate insulator25may be between the channel region22and the gate electrode27to electrically isolate the channel region22from the gate electrode27. Each of the gate insulator25and the gate electrode27may include multiple layers therein. The gate insulator25may include, for example, a silicon oxide layer, a silicon oxynitride layer, and/or a high k material layer that has a dielectric constant greater than silicon dioxide. The gate electrode27may include a work function controlling layer (e.g., a titanium nitride layer, a tantalum nitride layer), a diffusion barrier layer, and/or a conductive layer (e.g., a semiconductor layer, a metal layer).

In some embodiments, the channel region22may vertically overlap the second source/drain region44, as illustrated inFIG. 5A. In some embodiments, the channel region22may be connected to the substrate100through a protruding portion100P of the substrate100, and the second source/drain region44may be on a side of the protruding portion100P of the substrate100.

FIGS. 6A, 6B, 6C, and 6Dshow configurations of a channel region and source/drain regions according to some embodiments of the present inventive concept. Referring toFIG. 6A, a channel region22may include a first channel region22_1extending longitudinally in the first horizontal direction X, a second channel region22_2extending longitudinally in the second horizontal direction Y, and a third channel region22_3extending longitudinally in the first horizontal direction X. The first channel region22_1and the third channel region22_3may have an equal length in the first horizontal direction X, as shown inFIG. 6A. Source/drain regions42or44may be on end portions of the channel region22, respectively. Each of the source/drain regions42or44may be a top source/drain region (e.g.,42inFIG. 2A) that is on the channel region22or a bottom source/drain region (e.g.,44inFIG. 4B) that is under the channel region22and is in the substrate100.

Referring toFIG. 6B, in some embodiments, one of the source/drain regions42or44may be on a portion of the channel region22that is between end portions of the channel region22, and thus the channel region22may include a dummy channel region22_D. The first channel region22_1may have a length in the first horizontal direction X shorter than that of the third channel region22_3.

Referring toFIG. 6C, in some embodiments, portions of the channel region22extending longitudinally in the first horizontal direction X may have different lengths in the first horizontal direction X, and source/drain regions42or44may be on end portions of the channel region22, respectively. The first channel region22_1may have a length in the first horizontal direction X shorter than that of the third channel region22_3.

Referring toFIG. 6D, in some embodiments, the channel region22may have a rectangle shape, and source/drain regions42or44may be on diagonally facing corners of the channel region22, respectively. The channel region22may include the first channel region22_1and the third channel region22_3, which extend longitudinally in the first horizontal direction X and may also include the second channel region22_2and a fourth channel region22_4extending longitudinally in the second horizontal direction Y.

FIG. 7is a flow chart of methods of forming a FinFET device according to some embodiments of the inventive concept, andFIG. 8is a flow chart of methods of forming a channel region of a FinFET device according to some embodiments of the inventive concept.FIGS. 9A, 10A, 11A, 12A, 13A, and 14Aare plan views illustrating the methods according to the flow chart ofFIG. 8, andFIGS. 9B, 10B, 11B, 12B, 13B, and 14Bare cross-sectional views taken along the line E-E′ inFIGS. 9A, 10A, 11A, 12A, 13A, and 14Arespectively.

Referring toFIG. 7, the methods may include forming a bottom source/drain region (e.g.,44inFIG. 4B) in a substrate and forming a channel region (e.g.,22inFIG. 4B) (Block S100). As shown inFIG. 1A, in some embodiments, the FinFET device may not include a bottom source/drain region, and thus forming the bottom source/drain region may be omitted.

Referring toFIGS. 8, 9A, and 9B, the methods of forming a channel region may include forming a supporting layer52on a substrate100, and forming a first mask layer54on a side of the supporting layer52(Block S110). In some embodiments, the first mask layer54may have an uniform and constant thickness along the side of the supporting layer52in plan view as illustrated inFIG. 9A. For example, a preliminary first mask layer (not shown) may be formed conformally on the substrate100and the supporting layer52, and an etching process (e.g., a blanket etching process) may be performed without an etch mask covering the supporting layer52and the first mask layer54. The supporting layer52may include material(s) having an etch selectivity with respect to the first mask layer54. For example, the supporting layer52may include silicon oxide, and the first mask layer54may include silicon nitride.

Referring toFIGS. 8, 10A, and 10B, the methods of forming a channel region may include forming a second mask layer56on the supporting layer52and the first mask layer54(Block S120). The second mask layer56may expose portions of the supporting layer52and the first mask layer54, as illustrated inFIG. 10A. The second mask layer56may include material(s) having an etch selectivity with respect to the supporting layer52and the first mask layer54. For example, the second mask layer56may include a photoresist (PR) layer.

Referring toFIGS. 8, 11A, and 11B, the methods of forming a channel region may include removing the portions of the supporting layer52and the first mask layer54exposed by the second mask layer56(Block S130). In some embodiments, a dry etch process and/or a wet etch process may be performed to remove the portions of the supporting layer52and the first mask layer54using the second mask layer56as an etch mask. In some embodiments, the second mask layer56may then be removed.

Referring toFIGS. 8, 12A, and 12B, the methods of forming a channel region may include removing the supporting layer52(Block S140). In some embodiments, a dry etch process and/or a wet etch process may be performed to remove the supporting layer52.

Referring toFIGS. 8, 13A, 13B, 14A, and 14B, the methods of forming a channel region may include forming a channel region22by etching the substrate100using the first mask layer54as an etch mask (Block S150). In some embodiments, a dry etch process and/or a wet etch process may be performed to etch the substrate100. After forming the channel region22, the first mask layer54may be removed, and an upper surface of the channel region22may be exposed as illustrated inFIGS. 14A and 14B.

It will be understood that the channel region22shown inFIG. 6Ccan be formed by modifying a shape of the second mask layer56. It will be also understood that the channel region22shown inFIG. 6Dcan be formed by omitting the processes of Block S120and Block S130.

FIG. 15is a flow chart of methods of forming a channel region of a FinFET device according to some embodiments of the inventive concept.FIGS. 16A and 17Aare plan views illustrating the methods according to the flow chart ofFIG. 15, andFIGS. 16B and 17Bare cross-sectional views taken along the line F-F′ inFIGS. 16A and 17A, respectively.

Referring toFIG. 15, the methods of forming a channel region may include forming a supporting layer52and a first mask layer54(Block S110) as shown inFIGS. 9A and 9B. Referring toFIGS. 15, 16A, and 16B, the methods of forming a channel region may include removing the supporting layer52(Block S125) and forming a preliminary channel region22_P (Block S135). In some embodiments, a dry etch process and/or a wet etch process may be performed to form the preliminary channel region22_P on the substrate100by etching the substrate100using the first mask layer54as an etch mask.

Referring toFIGS. 15, 17A, and 17B, the methods of forming a channel region may include forming a second mask layer56on the preliminary channel region22_P (Block S145) and removing a portion of the preliminary channel region22_P (Block S155). The second mask layer56may be formed to expose a portion of the preliminary channel region22_P as illustrated inFIG. 17A. In some embodiments, a dry etch process and/or a wet etch process may be performed to remove the portion of the preliminary channel region22_P by etching the preliminary channel region22_P using the second mask layer56as an etch mask such that the channel region (e.g.,22inFIGS. 14A and 14B) is formed. After forming the channel region22, the second mask layer56may be removed, and an upper surface of the channel region22may be exposed as illustrated inFIGS. 14A and 14B.

It will be understood that the channel region22shown inFIG. 6Ccan be formed by modifying a shape of the second mask layer56. It will be also understood that the channel region22shown inFIG. 6Dcan be formed by omitting the processes of Block S145and Block S155.

Referring back toFIG. 7, the methods of forming a FinFET device may include, after forming the channel region22, forming a lower insulating layer (e.g.,12inFIG. 2A) on the substrate100(Block S200), forming a gate structure (e.g.,24inFIG. 2A) on opposing vertical sides of the channel region22(Block S300), forming an upper insulating layer (e.g.,32inFIG. 2A) on the gate structure (Block S400), and forming a top source/drain region (e.g.,42inFIG. 2A) on the channel region22(Block S500).

FIGS. 18, 19, and 20are cross-sectional views illustrating methods of forming an integrated circuit device including a VFET and a FinFET according to some embodiments of the inventive concept. Referring toFIG. 18, the integrated circuit device may be formed on a substrate100including a first region100_A and a second region100_B. AlthoughFIG. 18shows that no intervening region is between the first region100_A and the second region100_B, it will be understood that an intervening region may exist between the first region100_A and the second region100_B.

The methods may include forming trench insulating layers16, a bottom source/drain region44_vof the VFET, and a bottom source/drain region44of the FinFET in the substrate100. In some embodiments, the bottom source/drain region44of the FinFET may not be formed. In some embodiments, the trench insulating layers16in the first region100_A and the second region100_B may be formed concurrently and may have an equal thickness in the vertical direction Z. It will be understood that “formed concurrently” refers to being formed in a same fabrication step, at approximately (but not necessarily exactly) the same time, or in parallel steps that at least partially overlap in time.

In some embodiments, the bottom source/drain regions44_vof the VFET and the bottom source/drain region44of the FinFET may be formed concurrently and may have an equal thickness in the vertical direction Z. In some embodiments, the bottom source/drain regions44_vof the VFET and the bottom source/drain region44of the FinFET may be formed by performing an epitaxial growth process using the substrate100as a seed layer. In some embodiments, the bottom source/drain regions44_vof the VFET and the bottom source/drain region44of the FinFET may be formed by implanting dopant atoms into the substrate100.

The methods may include forming a channel region22and a vertical channel region22_V. The vertical channel region22_V may protrude from the substrate100in the vertical direction Z. It will be understood that the channel region22and the vertical channel region22_V can be formed after the bottom source/drain regions44_vof the VFET and the bottom source/drain region44of the FinFET are formed or before the bottom source/drain regions44_vof the VFET and the bottom source/drain region44of the FinFET are formed. In some embodiments, the channel region22and the vertical channel region22_V may be formed concurrently and may have an equal thickness in the vertical direction Z. The methods may also include forming a lower insulating layer12on the substrate100. In some embodiments, the lower insulating layer12may continuously extend from the first region100_A onto the second region100_B.

Referring toFIG. 19, a gate structure24, a vertical gate structure24_V, a spacer layer36, and an interlayer insulating layer34may be formed. The gate structure24and the vertical gate structure24_V may be formed concurrently and may have an equal thickness in the vertical direction Z. In some embodiments, the gate structure24and the vertical gate structure24_V may include the same layers having the same thicknesses. The spacer layer36may extend on the lower insulating layer12, gate structure24, and the vertical gate structure24_V. The spacer layer36may include insulating material(s). For example, the spacer layer36may include silicon oxide, silicon nitride, and/or silicon oxynitride. The interlayer insulating layer34may include insulating material(s), for example, silicon oxide and/or low k material that has a dielectric constant lower than silicon dioxide. In some embodiments, the interlayer insulating layer34may include recesses34_R exposing upper portions of the channel region22and the vertical channel region22_V, as illustrated inFIG. 19.

Referring toFIG. 20, an upper insulating layer32, a top source/drain region42of the FinFET, and a top source/drain region42_V of the VFET may be formed. In some embodiments, the upper insulating layer32may be formed in the recesses34_R of the interlayer insulating layer34. For example, a preliminary upper insulating layer (not shown) may be formed in the recesses34_R of the interlayer insulating layer34and on the interlayer insulating layer34, and then the preliminary upper insulating layer may be partially removed to leave the upper insulating layer32in the recesses34_R. The top source/drain regions42_V of the VFET may vertically overlap the vertical channel regions22_V, respectively.

Example embodiments are described below with reference to the accompanying drawings. Many different forms and embodiments are possible without deviating from the spirit and teachings of this disclosure and so the disclosure should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete and will convey the scope of the disclosure to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. Like reference numbers refer to like elements throughout.

Example embodiments of the present inventive concept are described herein with reference to cross-sectional views or plan views that are schematic illustrations of idealized embodiments and intermediate structures of example embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments of the present inventive concept should not be construed as limited to the particular shapes illustrated herein but include deviations in shapes that result, for example, from manufacturing.

It will be understood that references herein to “an element A vertically overlapping an element B” (or similar language) means that a vertical line intersecting both the elements A and B exists. It will be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element could be termed a second element without departing from the teachings of the present inventive concept.

It should be noted that in some alternate implementations, the functions/acts noted in flowchart blocks herein may occur out of the order noted in the flowcharts. For example, two blocks shown in succession may in fact be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality/acts involved. Moreover, the functionality of a given block of the flowcharts and/or block diagrams may be separated into multiple blocks and/or the functionality of two or more blocks of the flowcharts and/or block diagrams may be at least partially integrated. Finally, other blocks may be added/inserted between the blocks that are illustrated, and/or blocks/operations may be omitted without departing from the scope of the present inventive concept.