Method for forming semiconductor structure and overlay error estimation

A method includes forming a first overlay feature in a first dielectric layer over a first wafer; forming a second dielectric layer over the first overlay feature and the first dielectric layer; forming an opening in the second dielectric layer by at least using an exposure tool; forming a second overlay feature in the opening of the second dielectric layer, such that a first edge of the first overlay feature is covered by the second dielectric layer; directing an electron beam to the first and second overlay features and the second dielectric layer; detecting the electron beam reflected from the first overlay feature through the second dielectric layer and from the second overlay feature by a detector; obtaining, by a controller, an overlay error between the first overlay feature and the second overlay feature according to the reflected electron beam electrically connected to the detector.

BACKGROUND

Semiconductor integrated circuit (IC) fabrication involves forming multiple material layers with designed patterns on a semiconductor wafer. Each layer has to be aligned with previous layers such that the formed circuit can function properly. Various marks are used for this purpose. For example, overlay marks are used to monitor overlay deviation between the layers on the wafer. As semiconductor technology continues progressing to circuit layouts having smaller feature sizes, the alignment requirement becomes more stringent and the overlay marks are expected to take less wafer area.

DETAILED DESCRIPTION

Moreover, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the first and second features, such that the first and second features may not be in direct contact.

FIG. 1is a schematic top view of a wafer100according to some embodiments of the present disclosure. The wafer100includes plural chip regions CR and plural scribe line regions SR separating the chip regions CR from each other. A device200(e.g., circuits or interconnect structures), optical overlay marks300, electron-based overlay marks400, and an electron-based reference mark600are located at various locations in the chip regions CR. In some embodiments, the device200may include various devices or elements, such as a static random-access memory (SRAM) cells, transistors, resistors, capacitors, diodes, fuses, etc., but is simplified for a better understanding of the concepts of the present disclosure. The optical overlay marks300and the electron-based overlay marks400are used for optical and electron-beam based overlay measurements, respectively. In some embodiments, test lines300′ are located in the scribe line region SR, and may be used in the optical based overlay measurement. The electron-based overlay marks400may be disposed adjacent to the optical overlay marks300or the test line300′, such that some of the marks300(or the test line300′) and the marks400may be used for indicating optical-based or electron-based overlay errors at the same position. With this configuration, the optical based overlay measurement result of the marks300or the test line300′ can be compared with and checked by the electron-beam based overlay measurement result of the corresponding marks400, such that one of the marks300or the test line300′ having similar measurement result with that of the corresponding mark400is believed to have less mark damage and selected for the process of next waters. The electron-based reference mark600is used for providing a model for determining overlay errors in the electron-beam based overlay measurement.

FIG. 2Ais a top view of an electron-based overlay mark400ofFIG. 1according to some embodiments of the present disclosure. A pre-layer structure110including fins112aand gate structures115is provided, and the electron-based overlay mark400may include first overlay features134(marked with cross pattern) and second overlay features154and164(mark with slash pattern) over the pre-layer structure110. In some embodiments, the first overlay feature134represents the pattern of a first layer, the second overlay features154and164represent the pattern of a second layer over the first layer. In some embodiments, the feature134,154, and164may serve as source/drain contacts, source/drain contact vias, and gate contacts, respectively. In some embodiments, as shown inFIG. 2A, the first overlay features134has the edges E1and E2extending along the directions X and Y, respectively. The edges E1and E2of the features134are not fully covered by the second overlay features154and164, such that the edges E1and E2may be inspected by suitable methods. For better illustration, in this context, the first overlay features134under the second overlay features154are denoted as the overlay features134a, while the first overlay features134not under the second overlay features154are denoted as the overlay features134b.

FIGS. 2B and 2Cshow cross-sectional views of the electron-based overlay mark400taken along lines2B-2B and2C-2C ofFIG. 2Aand the corresponding detected results, respectively. The pre-layer structure110includes a substrate112having the fins112a(referring toFIG. 2C), isolation dielectrics114(referring toFIG. 2B), the gate structures115, and epitaxial source/drain features116(referring toFIG. 2C). The fins112a, the gate structures115, and the epitaxial source/drain features116forms plural transistors T, in which for the electron-based overlay mark400, the transistors T are dummy. To be specific, the transistors T of the electron-based overlay mark400are not connected to an external circuit when Wafer Acceptance Test (WAT) is performed.

In some embodiments, the substrate112may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. The substrate112may be a wafer, such as a silicon wafer. In some embodiments, the semiconductor material of the substrate112may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof.

In some embodiments, the substrate112is etched to form at least one semiconductor fin112a(referring toFIG. 2C). In some embodiments, plural semiconductor fins112aare substantially parallel to each other. At least one isolation dielectric114(referring toFIG. 2B) are formed between the semiconductor fins112aso as to separate the semiconductor fins112afrom each other. In some embodiments, the isolation dielectric114is made of silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), or other low-K dielectric materials. In some embodiments, the isolation dielectric114can have a multi-layer structure, for example, a thermal oxide liner layer with silicon nitride formed over the liner. Herein, a top surface of the semiconductor fins112ais higher than a top surface of the isolation dielectrics114, such that the semiconductor fins112aprotrude above the isolation dielectrics114.

The gate structures115wrap the semiconductor fins112aand are respectively formed over channel regions in the substrate112(e.g., the fin112a). The gate structures115have substantially parallel longitudinal axes that are substantially perpendicular to longitudinal axes of the semiconductor fins112a. For example, herein, the fins112aextending along the direction X, and the gate structures115extending along the direction Y, which is not parallel with the direction X. For example, herein, the direction Y is orthogonal to the direction X.

Each of the gate structures115may include a gate dielectric115aand a gate electrode115b. In some embodiments, the gate dielectric115amay include an oxide layer and a high-k dielectric layer over the oxide layer. The high-k dielectric layer may include metal oxides, transition metal-oxides, or the like. Examples of the high-k dielectric material include, but are not limited to, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium tantalum oxide (HMO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide, titanium oxide, aluminum oxide, hafnium dioxide-alumina (HfO2—Al2O3) alloy, or other applicable dielectric materials.

The gate electrode115bmay be a metal gate, although it may also be formed of polysilicon, metal silicides, or the like. For example, the gate electrode115bmay include a work function metal layer and a fill metal. In some embodiments, the work function conductive layer of the gate electrode115bmay include one or more n-type work function metals (N-metal) for forming an n-type transistor on the substrate112. The n-type work function metals may exemplarily include, but are not limited to, titanium aluminide (TiAl), titanium aluminium nitride (TiAlN), carbo-nitride tantalum (TaCN), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), metal carbides (e.g., hafnium carbide (HfC), zirconium carbide (ZrC), titanium carbide (TiC), aluminum carbide (AlC)), aluminides, and/or other suitable materials. In alternative embodiments, the work function conductive layer may include one or more p-type work function metals (P-metal) for forming a p-type transistor on the substrate112. The p-type work function metals may exemplarily include, but are not limited to, titanium nitride (TiN), tungsten nitride (WN), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), conductive metal oxides, and/or other suitable materials. The conductive layer of the gate electrode115bmay exemplarily include, but are not limited to, tungsten, aluminum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN, or other suitable materials.

The epitaxial source/drain features116(referring toFIG. 2C) are over portions of the fins112auncovered by the gate structures115. The epitaxial source/drain features116may be Si features, SiGe features, silicon phosphate (SiP) features, silicon carbide (SiC) features and/or other suitable features, which can be formed in a crystalline state. In some embodiments, lattice constants of the epitaxial source/drain features116are different from that of the semiconductor fins112a, so that the channel region between the epitaxial source/drain features116can be strained or stressed by the epitaxial source/drain features116to improve carrier mobility of the semiconductor device and enhance the device performance.

An ILD layer120is formed over the pre-layer structure110, the gate structures115, and the epitaxial source/drain features116. In some embodiments, the ILD layer120is formed over the pre-layer structure110along a direction Z, which is defined in a direction perpendicular to both directions X and Y. The first overlay features134are in the ILD layer120and serve as source/drain contacts as aforementioned. In some embodiments, an ILD layer140is formed over the ILD layer120along the direction Z. In some embodiments, the ILD layer140may cover portions of the first overlay features134, e.g., edges E1and E2of the first overlay features134. The second overlay features154are in the ILD layer140and serve as conductive vias connected to the source/drain contacts as aforementioned. The overlay features164are in the ILD layers120and140and serve as gate contacts as aforementioned.

Herein, overlay conditions between the overlay features134aand164, between the overlay features134aand154, between the overlay features134band164, and between the overlay features134band154are measured by an electron-based system900inFIG. 7, and an electron-based image including position information of the overlay features134,154, and164may be obtained. To be specific, an electron beam (e.g., the electron beam B1generated by the electron-based system900inFIG. 7) is incident onto the wafer100, and an overlay signal (e.g., electron beam B1′) reflected by the wafer100is detected as shown inFIGS. 2B and 2C, thereby obtaining the electron-based image.

In some cases where the electron beam has a low landing energy, however, the ILD layer (e.g., the ILD layer140) covering the first overlay features134may obstruct the propagation of the electron beam, such that the electron beam attacks the first overlay features134with little intensity, and the intensity of the electron beam reflected by the first overlay features135may be too weak to be detected or recognized. In the cases, due to the coverage of the ILD layer, the pattern of first layer may not be detected by using the electron beam.

In the present embodiments, the electron beam B1is adjusted to have a high landing energy such that while a first portion of the electron beam B1may be reflected by the pattern of the second layer (e.g., the second overlay feature154and164of the mark400), and a second portion of the electron beam B1may penetrate the ILD layer140and be reflected by the pattern of the first layer (e.g., the first overlay features134of the mark400) through the ILD layer140. As shown inFIGS. 2B and 2C, a first portion of the reflected electron beam B1′ corresponding to the features154and164have a strong intensity, while a second portion of the reflected electron beam B1′ corresponding to the features134have an intensity less than that of the first portion of the reflected electron beam B1′, but detectable and recognizable. For example, in the present embodiments, the electron-based system900is adjusted to (referring toFIG. 7) operates at a landing voltage in a range from about 5 kV to about 45 kV, and the electron beam B1may have a landing energy in a range from about 5 keV to about 45 keV. The electron beam B1with the high landing energy may partially penetrate the ILD layer140and be reflected by the first overlay features134through the ILD layer140, rather than almost all shielded by the ILD layer140. In some embodiments, the electron-based system900inFIG. 7may use the electron beams B1to scan an area of the wafer100(referring toFIG. 1), such that a see-through electron-based image including information of the first overlay features134and the second overlay features154and164of a portion of the mark400is captured. For example, the area scanned by the electron beams B1may be several micrometers, such as about 1 micrometers, in which the scanned area may be less than an area of the electron-beam marks400.

In some embodiments, the electron beams B1can cause damages to the materials under inspection due to its relatively high energy. In some embodiments, it is arranged that the electron beams B1is directed to the electron-beam marks400but not to the device200inFIG. 1, such that the device200remains intact after the electron-based inspection, while the ILD layers in the region of the electron-beam marks400may be damaged.

Herein, the first portion of the electron beam B1′ reflected by the second overlay features154and164of the mark400(which does not pass through the ILD layer140) may have an intensity greater than that of the second portion of the electron beam B1′ reflected by the first overlay features134(which passes through the ILD layer140). The intensity difference reveals the positions of the overlay features of different layers, and the overlay condition thereof may be measured.

In some embodiments, as shown inFIG. 2A, the pattern of the first layer (e.g., the first overlay features134) and the pattern of the second layer (e.g., the second overlay features154and164) are designed such that a horizontal overlay condition and a vertical overlay condition can be measured using one electron-based image. To be specific, in some embodiments, for detecting the horizontal overlay condition, at least a portion of the pattern of the first layer (e.g., the first overlay features134) and at least a portion of the pattern of the second layer (e.g., the second overlay features154and164) are located on a horizontal line (e.g., one of the lines2B-2B and2C-2C). Furthermore, at least one edge of the pattern of the first layer (e.g., the edge E1of the first overlay features134) is not covered by the pattern of the second layer (e.g., the second overlay features154and164) in the horizontal direction X. Through the configuration, the horizontal overlay condition can be measured using one electron-based image. For example, referring toFIGS. 2B and 2C, the offset HV1′ of the electron beam Br in the electron-based image reveals a horizontal offset value HV1between the features134aand164. The offsets HV31′ and HV32′ of the electron beam Br in the electron-based image reveals horizontal offset values HV31and HV32between the features134aand154. The offset HV4′ of the electron beam B1′ in the electron-based image reveals a horizontal offset value HV4between the features134band154. Similarly, a horizontal offset value HV2between the features134band164may be inferred from the electron beam B1′ in the electron-based image.

Similarly, referring back toFIG. 2A, for detecting the vertical overlay condition, some of the first overlay features134and the second overlay features154are located on a vertical line (e.g., vertical line VL1), and at least one edge E2of the first overlay features134is not covered by the second overlay features154in the vertical direction Y. Through the configuration, the vertical overlay condition may be measured using the electron-based image. For example, vertical offset values VV1and VV2between the features134aand154may be obtained from the electron-based image.

In the present embodiments, some of the first overlay features134are in contact with the second overlay features154. However, it should not limit the scope of the present embodiments, and in some other embodiments, other dielectric layers may be interposed between the first overlay features134and the second overlay features154. Through the configuration, during the overlay measurements, the first portion of the electron beam B1may be reflected by the second overlay features154and164, the second portion of the electron beam B1may penetrate the ILD layer140and the other dielectric layers, and then be reflected by the first overlay features134through the ILD layer140and the other dielectric layers. It is noted that the electron-beam based overlay measurements may also be used in detecting the overlay conditions of other features. For example, the electron-beam based overlay measurements may also be used in detecting the overlay conditions between the fins112aand the gate structures115, the fins112aand the epitaxial source/drain features116, and the gate structures115and the epitaxial source/drain features116.

FIG. 3is a top view of an electron-based reference mark600ofFIG. 1according to some embodiments of the present disclosure. In some embodiments, the electron-based reference mark600includes plural sub-marks601-649arrayed in the chip region CR (referring toFIG. 1). The sub-marks601-649having various configurations and correspond with various overlay errors, respectively. For example, each of the sub-marks601-649includes a pattern of the first layer (e.g., the first reference features600A) and a pattern of the second layer (e.g., the second reference features600B). To be specific, the features600A is in the ILD layer120(referring toFIGS. 2B-2C), and the feature600B is in the ILD layer140or in both the ILD layers120and140(referring toFIGS. 2B-2C). The features600A may be formed by the formation process of the features134. The features600B may be formed by the formation process of the features154/164. The configurations of the sub-marks601-649may be different from each other, for example, in the sub-marks601-649, the distances between the features600A and600B are different from each other. Thus, the sub-marks601-649are associated with various and/or theoretical different overlay errors. In some embodiments, the respective theoretical overlay errors of the sub-marks601-649are determined and known in advanced. For example, a datasheet including plural reference theoretical overlay errors respectively corresponding to the sub-marks601-649may be obtained by a controller.

FIG. 4is a flow chart showing an overlay error estimation method M for obtaining overlay errors from electron-based images. The method M includes operations B1, B2, B31, and B32. The operation B1shows an e-based image of an e-beam overlay mark is obtained by a processor in a computer. The operations B31and B32show how an overlay error of the e-beam overlay mark is obtained. The operation B2shows a methodology for training a model for the overlay error estimation, in which the operation B2includes the operations B21-B23. A model for the overlay error estimation is trained by using artificial intelligence including machine learning, such as deep learning. For example, as shown in the operation B21, electron-based images associated with the sub-marks601-649of the reference mark600is obtained by the processor, and as shown in the operation B22, determined and known theoretical overlay errors associated with the sub-marks601-649of the reference mark600are received by the processor. An artificial neural network (ANN) may be used in the operation B23and may be trained based on inputs (i.e., the e-based image of reference mark600obtained from operation B21) and the ground truths (i.e., the theoretical overlay errors of the reference mark obtained from operation B22), thereby generating an inference model, which is an predicted relationship between the input and the ground truths.

The artificial neural network (ANN) is an interconnected group of artificial neurons that uses a mathematical or computational model for information processing based on a connectionist approach to computation. There are plural layers to a feedforward artificial neural network: an input layer, at least one hidden layer, and an output layer. The input layer is a data vector that is fed into the network. The input layer feeds into the hidden layer, which feeds into the output layer. The actual processing in the network occurs in the nodes of the hidden layer and the output layer. When enough neurons are connected together in the layers, the network can be trained to perform certain functions using a training algorithm. The fully connected layers connect every neuron in one layer to every neuron in another layer.

Convolutional neural network is a kind of ANN, in which hidden layers of a CNN may include convolutional layers, pooling layers, fully connected layers and normalization layer. The convolutional layers apply a convolution operation to the input, passing the result to the next layer. The convolution emulates the response of an individual neuron to visual stimuli. The pooling layers combine the outputs of neuron clusters at one layer into a single neuron in the next layer, in which a maximum value or an average value from each of a cluster of neurons may be used.

Using input (i.e., the e-based image of the reference mark600obtained from operation B21) and the ground truths (i.e., the theoretical overlay errors of the reference mark obtained from operation B22), the ANN may implement an iterative training process. Training may be based on a wide variety of learning rules or training algorithms. For example, the learning rules may include one or more of the following: back-propagation, real-time recurrent learning, pattern-by-pattern learning, supervised learning, interpolation, weighted sum, reinforced learning, temporal difference learning, unsupervised learning, and/or recording learning. As a result of the training, the ANN may learn to modify its behavior in response to its environment, and obtain an inference model for overlay measurement as shown in operation B213. The inference model shown in operation B213may represents a model upon which a machine may determine an appropriate response (e.g., overlay errors) to new data (e.g., new electron-based images). The inference model in operation B213may represent, for example, relationship information between electron-based images and the overlay errors. The inference model may be stored in any form at any convenient location, such as a memory in the computer, and may be used for forecast. In some embodiments, other learning methods may also be used to produce the inference model.

When the wafer is detected by the electron beam, the computer may receive detection results (e.g., the electron-based image) having information of the whole wafer. To be specific, the detection results (e.g., plural electron-based images) may include information of the electron-based reference mark600and information of the electron-based overlay marks400. The processor of the computer may generate the inference model (i.e., as shown in the operation B2) from the information of the electron-based reference mark600, for example, from some electron-based images associated with the electron-based reference mark600. Then, from the information of the electron-based overlay marks400, for example, from one or more electron-based images associated with the electron-based overlay marks400, through the inference model shown in operation B23, the machine may generate respective overlay errors of the electron electron-based overlay marks400as shown in the operation B31.

In some other embodiments, an algorithm for analyzing the electron-based image is used as shown in the operation B32, and the operations B2and B32may be omitted. When the electron-based image is received by the computer as shown in the operation B1, through the algorithm in the operation B32, some electron-based image associated with the electron-based overlay marks400is analyzed, and the overlay error between patterns of two layer is obtained as shown in the operation B32. In the present embodiments, from the electron-based image, the overlay error in the X direction between patterns of two layer can be correspondingly determined by offsets HV1′-HV4′ of the electron beam B1in the X direction. For example, the overlay error in the X direction (shift in the X direction or X_shift) between the features134aand154can be determined by HV31′ and HV32′ in a formula as X_shift=(HV31′-HV32′)/2. Similarly, the overlay error between the features134and154in the Y direction can be determined by the offset of the electron beam B1in Y direction correspondingly.

The configuration of the device200ofFIG. 1may be similar to that of the electron-based overlay mark400ofFIGS. 2A-2C. For example, the device200includes various transistors and conductive features of SRAM cells, and the transistors T under the mark400and the features134,154, and164of the mark400may have the same configuration with the transistors and the conductive features of the device200, such that the electron-based overlay mark400may be described as SRAM cell-like. For example, the device200may include conductive features similar to the features134,154, and164of the electron-based overlay marks400in the ILD layers120and140. The SRAM cell-like configuration of the mark400results in similar process behavior (e.g., etching behavior and polishing behavior) with the configuration of the device200, such that while the processes (e.g., etching process and polishing process) are optimized for better forming the SRAM configuration of the device200, the SRAM cell-like configuration of the mark400can be prevented from being damaged during etching or polishing process. The transistors of the device200are true and functional, while the transistors T under the mark400may be dummy. For example, the transistors T for the electron-based overlay mark400may be covered by a dielectric layer and electrically disconnected from a pad, which may connected to an external circuit for WAT. On the other hand, the transistor in the device region is connected to a conductive feature embedded the dielectric layer, and may be electrically connected to the pad connected to the external circuit for WAT. The top and cross-sectional views of the device200may be substantially the same as those shown inFIGS. 2A-2C, and not repeated herein.

FIG. 5Ais a top view of an optical overlay mark300ofFIG. 1according to some embodiments of the present disclosure. The optical overlay mark300includes plural sub-optical marks300S1-300S9. For example,FIGS. 5B and 5Care top views of sub-optical marks300S1and300S2ofFIG. 5Aaccording to some embodiments of the present disclosure. Each of the sub-optical mark300S1and300S2includes first overlay features132and second overlay features152over the pre-layer structure110. In some embodiments, the configuration of the sub-optical marks300S1-300S9are different. InFIG. 5B, the features132of the mark300S1has pitch P1therebetween, the features152of the mark300S1has pitch P1′ therebetween, the features132of the mark300S1has a width W1, and the features152of the mark300S1has a width W1′. InFIG. 5C, the features132of the mark300S2has pitch P2therebetween, the features152of the mark300S2has pitch P2′ therebetween, the features132of the mark300S2has a width W2, and the features152of the mark300S2has a width W2′. For example, the pitch P1of the mark300S1is less than the pitch P2of the mark300S2, and the pitch P1′ of the mark300S1is less than the pitch P2′ of the mark300S2. In some embodiments, the width W1of the mark300S1is different from the width W2of the mark300S2, and the width W1′ of the mark300S1is different from the width W2′ of the mark300S2.

For the purposes of horizontal and vertical overlay measurements, some of the first overlay features132/152may extend along the direction X, while the other of the first overlay features132/152may extend along the direction Y. Referring to bothFIG. 5BandFIG. 5D,FIG. 5Dis a cross sectional view taken along line5D-5D ofFIG. 5B. The first overlay features132are in the ILD layer120over the pre-layer structure110, and the second overlay features152are in the ILD layer140. The overlay features132and152may also be referred to the pattern of the first and second layers in an optical mark region, respectively.

Referring back toFIG. 1, in some embodiments, since an electron-based system provides a higher imaging resolution than that of an optical microscope, a critical dimension of the electron-based overlay marks400can be smaller than that of the optical overlay marks300. For example, a critical dimension of the optical overlay marks300(e.g., the pitches P1and P1′ shown inFIGS. 5B and 5C) may be in a range from about 200 nanometers to about 500 nanometers, and a critical dimension of the electron-based overlay marks400(e.g., the distance between neighboring features134shown inFIG. 2A) can be in a range from about 1 nanometer to about 100 nanometers. As such, when sizes of the marks300and400are expected to be as small as possible for saving areas in intra-field, the size of the electron-based overlay marks400can be smaller than the size of the optical overlay marks300. For example, the optical overlay marks300has a length300L (seeFIG. 1) in a range from about 10 micrometers to about 200 micrometers. To be specific, the sub-optical mark300S1-300S9(referring toFIG. 5A) may have a length300SL in a range from about 10 micrometers to about 20 micrometers. If the size of the sub-optical mark300S1-300S9is less than about 10 micrometers, the sub-optical mark300S1-300S9may not be detectable or identifiable by the optical microscope. If the size of the sub-optical mark300S1-300S9is greater than about 20 micrometers, the optical overlay marks300may occupy too much space. The size of the electron-based overlay marks400can be smaller than a size of the sub-optical mark300S1-300S9. The electron-based overlay marks400has a length400L (seeFIG. 1) in a range from about 1 micrometer to about 10 micrometers, for example, in a range from about 1 micrometer to about 5 micrometers, which is detectable by the electron-based system and does not occupy much space in the chip region CR. A size of electron-based reference mark600may be greater than that of the electron-based overlay marks400since the mark600includes more information and features than the electron-based overlay marks400.

Reference is made toFIG. 1. In some other embodiments, the marks300,400and600may be formed in chip frame regions NSR (e.g. frame regions of the chip regions CR near scribe line regions SR) of the chip regions CR, in which the device200is not in the chip frame regions NSR. Each of the regions NSR has an edge adjoining the scribe line regions SR and an opposite edge that is a certain distance (e.g., about 1 to about 2 millimeters) away from the scribe line regions SR. In some other embodiments, some of the marks300and400may be formed adjacent to the device200and out of the chip frame regions NSR. In some embodiments, some of the marks400may be formed in the region where the device200is formed. In some embodiments, some of the marks300and400may be formed in the scribe line regions SR.

FIG. 6is a top view of a test line300′ ofFIG. 1according to some embodiments of the present disclosure. The test line300′ is located in the scribe line region SR (referring toFIG. 1) and includes plural sub-optical marks300S. The configuration of the sub-optical marks300S may be similar to the sub-optical marks300S1-300S9illustrated inFIGS. 5B and 5C. In some embodiments, the configurations of the plural optical marks300S are different. For example, the pitch between the features of one of the marks300S is different from that of another of the marks300S. In some embodiments, the width of the features of one of the marks300S is different from that of another of the mark300S. The configuration of the sub-optical marks300S is similar to those aforementioned, and not repeated herein.

FIG. 7is a schematic view of an electron-based system900according to some embodiments of the present disclosure. The electron-based system900is an electron-based metrology technique that utilizes an electron-based imaging for various monitoring, measurement and/or analysis. In some embodiments, the electron-based system900includes an electron microscope, such as scanning electron microscope (SEM). The electron-based system900provides a higher imaging resolution than that of an optical microscope because an electron beam can be energized to have a shorter wavelength. The electron-based system900includes a particle source910, one or more lenses920, a scanner930, a wafer stage940, and a detector950.

The particle source910provides a particle beam. In some embodiments, the particle source910is an electron source and the particle beam is an electron beam B1. In some embodiments, the source910is an electron gun with a mechanism to generate electrons, such as by thermal electron emission. In some other embodiments, the electron gun includes a tungsten (or other suitable material) filament designed and biased to thermally emit electrons. InFIG. 7, an electron beam B1is illustrated as an incident electron beam from the source and directed toward the sample to be detected.

The lenses920impact the electron incident beam B1from the source910for imaging effect. In some embodiment, the lenses920includes a condenser lens to focus the electron beam B1into smaller diameter, and further includes an objective lens properly configured. Various lenses, such as magnets, are designed to provide force to the electrons for proper imaging effect, such as focusing.

The scanner930deflects the electron beam B1for scanning a certain region of the sample in a certain mode, such as raster mode. In some embodiments, the sample to be detected is a wafer100for integrated circuits. The scanner930is operable to direct the electron beam B1to the wafer100positioned on a wafer stage940. In one example, the scanner930may include one or more coils to deflect the electron beam B1in two orthogonal directions such that the electron beam B1is scanned over a surface area of the wafer100, particular along direction X and direction Y (referring toFIG. 2A). In some embodiments, the wafer stage940is operable to move such that the electron beam B1is directed to various electron-based overlay marks400and the reference mark600formed on the wafer100.

The detector950receives a signal (e.g., an overlay signal) from the wafer100. The overlay signal is an energy flow from the substrate and generated by the interaction between the incident electron beam B1and the wafer100. The overlay signal is from a certain area of the wafer100, such as the spot of the incident electron beam B1. In some examples, the detector950is designed operable to move and receive the intended overlay signal from the wafer100.

In some embodiments, the overlay signal includes reflected electrons that are the reflection of the incident electron beam B1from the substrate after interaction (such as elastic collision) with the atoms of the wafer100. In some other embodiments, the overlay signal includes electrons that are secondary electrons generated from the substrate by the inelastic collision between the incident electron beam B1and the atoms of the wafer100. In still some other embodiments, the overlay signal includes an electromagnetic radiation emitted from the substrate after the inelastic collision between the incident electron beam B1and the atoms of the wafer100. In some other embodiments, the overlay signal includes an electrical current in the wafer100. That electrical current is from the incident electron beam absorbed to the wafer100and therefore referred to as beam current.

The detector950is designed with a proper mechanism to effectively detect the overlay signal (backscattered electron, secondary electron, electromagnetic radiation, electrical current or combination of above mentioned). The detector950is further positioned and configured for proper detection. For example, if the overlay signal is the beam current, the detector950may be coupled to the wafer100for current detection.

The electron-based system900may further include other components and modules. In some examples, the electron-based system900includes an amplifier designed and configured to amplify the overlay signal to a higher level. In some other examples, the electron-based system900includes a display module to display the scanned image to be visualizable to human eyes. In some examples, the electron-based system900further includes a module for extraction and analysis based on the detected data and scanned images.

FIGS. 8A and 8Bare flow charts of a method500for forming a semiconductor device according to some embodiments of the present disclosure.FIGS. 9A-9Iillustrate plural intermediate stages of the method500for forming a semiconductor device according to some embodiments of the present disclosure. The illustration is merely exemplary and is not intended to limit beyond what is specifically recited in the claims that follow. It is understood that additional operations may be provided before, during, and after the operations shown byFIGS. 8A and 8B, and some of the operations described below can be replaced or eliminated for additional embodiments of the method. The order of the operations/processes may be interchangeable.

Referring toFIG. 8A, the method500begins at operation502where circuit features and overlay features are formed in device and mark regions respectively. For example, referring toFIG. 9A,FIG. 9Ais a cross-sectional view of a portion of the chip region CR of the wafer100(referring toFIG. 1) according to some embodiments of the present disclosure. A pre-layer structure110is provided. The pre-layer structure110has a device region DR where the device200(referring toFIG. 1) is to be formed, an optical mark region MR1where the optical overlay marks300(referring toFIG. 1) are to be formed, and an electron beam mark region MR2where the electron-based overlay mark400(referring toFIG. 1) is to be formed. In the present embodiments, the optical overlay marks300(referring toFIG. 1) in regions MR11and MR12of the optical mark region MR1are for overlay measurement of two different resist layers, respectively. In some embodiments, at least one of the regions MR11and MR12may be omitted.

The pre-layer structure110includes a semiconductor substrate and overlying layers such as contact etch stop layers, inter-layer dielectric, inter-metal dielectrics, vias, and metal lines formed therein. For example, the pre-layer structure110includes a semiconductor substrate112, isolation dielectrics114, gate structures115, epitaxial source/drain features (referring toFIG. 2C), which may form transistors of SRAM cells. The semiconductor substrate may additionally or alternatively include germanium, silicon germanium, gallium arsenic, or other proper semiconductor materials. Various doped regions, dielectric features, and/or a portion of multilevel interconnects are formed over the semiconductor substrate. In some embodiments, the semiconductor substrate112may further include various doped features for various microelectronic components, such as a complementary metal-oxide-semiconductor field-effect transistor (CMOSFET), an imaging sensor, a memory cell, and/or a capacitive element. In some embodiments, the semiconductor substrate includes conductive material features and dielectric material features configured for coupling and isolating various microelectronic components, respectively. In some embodiments, the pre-layer structure110includes one or more material layers formed on the semiconductor substrate.

In some embodiments, first overlay features132are formed in the ILD layer120in the optical mark regions MR11and MR12, first overlay features134are formed in the ILD layer120in the electron beam mark region MR2, first circuit features136are formed in the ILD layer120in the device region DR. The formation of the features132-136may include etching openings in the ILD layer120, overfilling the openings with a material layer, and removing excess portions of the material layer out of the openings, for example, by a planarization process. The material layer may be made of conductive materials, such as metal. The first circuit feature136can serve as a conductive line or conductive via of an interconnect structure, or a source/drain contact of a semiconductor device, such as a fin field effect transistor (FinFET). In some embodiments, the features132-136may include a conductive material such as copper, although other materials, such as tungsten, aluminum, gold, or the like, can alternatively be utilized. In some embodiments in which the features132-136are formed of copper, the features132-136may be deposited by electroplating techniques, although any method of formation can alternatively be used.

Referring toFIG. 8A, the method500proceeds to operation504where an interlayer dielectric (ILD) layer is formed over the circuit features and overlay features. Referring toFIG. 9B, the ILD layer140is formed over the ILD layer120and the features132-136. In some embodiments, the ILD layer140may include silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric material, and/or other suitable dielectric materials. Examples of low-k dielectric materials include, but are not limited to, fluorinated silica glass (FSG), carbon doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), or polyimide. The ILD layer140may be formed using, for example, CVD, ALD, spin-on-glass (SOG) or other suitable techniques.

In some embodiments, a contact etch stop layer (CESL) may be optionally blanket formed on the structure shown inFIG. 9A, and then the ILD layer140is formed over the CESL layer. That is, there is a CESL between the ILD layer120and the ILD layer140. The CESL may include a material different from the ILD layers120and140. The CESL includes silicon nitride, silicon oxynitride or other suitable materials. The CESL can be formed using, for example, plasma enhanced CVD, low pressure CVD, ALD or other suitable techniques.

Referring toFIG. 8A, the method500proceeds to operation506where a photoresist layer is formed over the ILD layer. Referring toFIG. 9C, a photoresist layer PR1is formed over the ILD layer140. The photoresist layer PR1may be made of suitable photo-sensitive organic materials. In some embodiments, a pad layer and a mask layer are formed on the ILD layer140before the formation of the photoresist layer PR1, and the photoresist layer PR1is formed on the mask layer. The pad layer may be a thin film comprising silicon oxide formed using, for example, a thermal oxidation process. The pad layer may act as an adhesion layer between the ILD layer140and mask layer. The pad layer may also act as an etch stop layer for etching the mask layer. In some embodiments, the mask layer is formed of silicon nitride, for example, using low-pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). The mask layer is used as a hard mask during subsequent photolithography processes.

Referring toFIG. 8A, the method500proceeds to operation508where the photoresist layer is exposed and developed. Referring toFIG. 9D, portions of the photoresist layer PR1is exposed and developed. Herein, an exposure tool (e.g., the exposure tool820inFIG. 12) may provide suitable light patterns to expose the photoresist layer PR1. The pattern in the exposed photoresist layer PR1is then chemically developed. After the exposure and development, portions of the photoresist layer PR1are removed, and other portions of the photoresist layer PR1remains and are referred to as photoresist PR1′ hereinafter. The photoresist PR1′ includes openings PO11, PO12, PO13in the optical mark region MR11, the electron beam mark region MR2, and the device region DR, respectively.

Referring toFIG. 8AandFIG. 9D, the method500proceeds to operation510where an after-development inspection (ADI) is performed for obtaining positions of the photoresist. In some embodiments, ADI may be performed with optical systems, such as an optical microscope, to inspect the position of the openings PO11of the photoresist PR1′ and the first overlay feature132in the region MR11. For example, an optical based image including information of the photoresist PR1′ and feature132is captured during the ADI. The optical microscope may not inspect the position of the openings PO12and PO13due to optical limitation.

An overlay analysis (i.e., high order overlay analysis) is performed to obtained overlay error from the optical based image in some embodiments. If the overlay error is within an acceptable range, the photoresist PR1′ may be hard baked, and the method500proceeds to operation512. If the overlay error is out of specification (e.g., greater than an acceptable range), the wafer may be sent to rework. To be specific, a rework process may be initiated, such as removing the overlying photoresist PR1′ from the ILD layer140and forming another photoresist over the ILD layer140with consequence that re-optimizes the exposure tool control algorithm for exposing photoresist. For example, the photoresist PR1′ may be removed, the method500goes back to operation506by forming the photoresist, and the exposure tool (e.g., the exposure tool820inFIG. 12) used at operation508is re-optimized based on the previous analyzed overlay error.

In some embodiments, a controller (e.g., a controller810inFIG. 13) may process the inspection result, perform the overlay analysis to determine the overlay error, and perform operations according to the result of the overlay analysis. For example, the controller may improve/optimize the exposure tool (e.g., the exposure tool820inFIGS. 12 and 13) and initiate a rework process. In some embodiments, the controller may send the wafer to the next operation in fabrication process.

In some other embodiments, the ADI may be performed with an electron-based system (e.g., the system900inFIG. 7) to inspect the position of the openings PO11of the photoresist PR1′ and the first overlay feature132in the region MR11and/or the positions of the openings PO12of the photoresist PR1′ and the first overlay feature134in the region MR2, and the positions of the openings PO13of the photoresist PR1′ and the feature136in the region DR. An overlay analysis as illustrated as the overlay error estimation method inFIG. 4is performed based on the inspection result of ADI, the overlay analysis may include determination of the overlay error between the photoresist PR1′ and the overlay features132-136. In some embodiments where the ADI is performed with an electron-based system, the controller may perform the method M inFIG. 4for the determination of overlay errors between the photoresist PR1′ and the first overlay feature132. In some other embodiments, the ADI may be omitted.

Referring toFIG. 8A, the method500proceeds to operation512where an the ILD layer is etched to form openings in the device region and mark regions. Referring toFIG. 9E, portions of the ILD layer140exposed by the openings PO11, PO12, and PO13of the patterned photoresist PR1′ (referring toFIG. 9D) are etched to form openings142,144, and146in the mark region MR11, MR2, and the device region DR, respectively. In some embodiments, the etching process may be a dry etching, wet etching and/or plasma etching process. For example, the etching process may employ a mixture of tetrafluoromethane (CF4), trifluoromethane (CHF3) and oxygen as the etching gases. After the etching process, the photoresist PR1′ may be removed, for example, by oxygen plasma ashing.

Still referring toFIG. 8A, the method500proceeds to operation514where an after-etching inspection (AEI) is performed for obtaining positions of the etched pattern of the ILD layer. In some embodiments, the AEI may be performed with optical systems, such as an optical microscope, to inspect the position of the etched pattern (e.g., the opening142) of the ILD layer140and the first overlay feature132in the region MR11. The optical microscope may not inspect the position of the opening144due to optical limitation. For example, an optical based image including information of the opening142of the ILD layer140and features132is captured during the AEI. Alternatively, in some other embodiments, the AEI may be performed with an electron-based system (e.g., the system900inFIG. 7) to inspect the position of the opening142of the ILD layer140and the first overlay feature132in the region MR11, the positions of the openings144of the ILD layer140and the first overlay feature134in the region MR2, and the positions of the openings146of the ILD layer140and the feature136in the region DR. For example, an optical or electron-based image including information of the ILD layer140and features132-136is captured during the AEI.

As the aforementioned ADI, in some embodiments, an overlay analysis is performed based on the inspection result of AEI, the overlay analysis includes determination of the overlay error between the etched ILD layer140and the first overlay feature132. The overlay analysis may further include perform high order overlay analysis. In some embodiments, the controller (e.g., the controller810inFIG. 13) may process the inspection result, perform the overlay analysis to determine the overlay error, and perform operations according to the result of the overlay analysis. For example, the controller may improve/optimize the exposure tool (e.g., the exposure tool820inFIGS. 12 and 13) used for exposing the photoresist (e.g., the operation508) based on the overlay error with consequence that correct the offset in the etch process for next coming wafer, in which the offset in the etch process may result from etching loading effect. In some embodiments where the AEI is performed with an electron-based system, the controller may perform the method M inFIG. 4for the determination of overlay errors between the etched ILD layer140and the first overlay feature132. In some other embodiments, the AEI may be omitted.

Referring toFIG. 8B, the method500proceeds to operation516where a photoresist layer is formed over the ILD layer and then be exposed and developed. Referring toFIG. 9F, the method500proceeds to operation516where a photoresist layer is formed over the structure ofFIG. 9E, and portions of the photoresist layer is exposed and developed. After the exposure and development, portions of the photoresist layer are removed, and the remaining portion of the photoresist layer is referred to as photoresist PR2′. The photoresist PR2′ includes openings PO21, PO22, and PO23in the mark regions MR12, MR2, and the device region DR, respectively.

Referring toFIG. 8B, the method500may proceeds to operation518where an ADI may be performed for obtaining positions of the photoresist PR2′. In some embodiments, ADI may be performed with optical systems, such as an optical microscope, to inspect the position of the openings PO21of the photoresist PR2′ and the first overlay feature132in the region MR11. In some other embodiments, the ADI may be performed with an electron-based system (e.g., the system900inFIG. 7) to inspect the position of the openings PO21of the photoresist PR2′ and the first overlay feature132in the region MR11, the positions of the openings PO22of the photoresist PR2′ and the first overlay feature134in the region MR2, and/or the positions of the openings PO23of the photoresist PR2′ and the feature136in the region DR. For example, an optical or electro-based image including information of the photoresist PR2′ and features132-136is captured during the ADI. An overlay analysis is performed based on the inspection result of ADI, the overlay analysis may include determination of the overlay error between two features (e.g., the photoresist PR2′ and the first overlay feature132), and a rework process may be initiated according to the overlay error. Other details of the ADI are similar to the ADI at operation510, and not repeated herein.

Referring toFIG. 8B, the method500proceeds to operation520where the ILD layer is etched to form openings in the device region and mark region. Referring toFIG. 9G, the method500proceeds to operation520where portions of the ILD layers120and140exposed by the openings PO21, PO22, and PO23of the patterned photoresist PR2′ (referring toFIG. 9F) are etched to form openings O1, O2and O3in the mark region MR12, MR2, and device region DR respectively. In some embodiments, the etching process may be a dry etching, wet etching and/or plasma etching process. For example, the etching process may employ a mixture of tetrafluoromethane (CF4), trifluoromethane (CHF3) and oxygen as the etching gases. After the etching process, the photoresist PR2′ (referring toFIG. 9F) may be removed, for example, by oxygen plasma ashing.

Referring toFIG. 8B, the method500may proceeds to operation522where an AEI may be performed for obtaining positions of the etched pattern of the ILD layers. In some embodiments, the AEI may be performed with optical systems, such as an optical microscope, to inspect the position of the openings O1and the first overlay feature132in the region MR21. Alternatively, in some other embodiments, the AEI may be performed with an electron-based system (e.g., the system900inFIG. 7) to inspect the position of the opening O1and the first overlay feature132in the region MR11, the positions of the openings O2and the features134and154in the region MR2, and/or the positions of the openings O3and the features136and156in the region DR. For example, an optical or electron-based image including information of the opening O1-O3and features132-136,154, and156is captured during the AEI. The exposure tool (e.g., the exposure tool820inFIGS. 13 and 14) used for exposing the photoresist may be optimized for next coming wafer according to a result of the AEI. Other details of the AEI are similar to the AEI at operation514, and not repeated herein.

Referring toFIG. 8B, the method500proceeds to operation524where the openings of the ILD layer are overfilled with a metal material. Referring toFIG. 9H, the method500may proceeds to operation524where the openings142-146and O1-O3are overfilled with a metal material ML. The metal material ML includes, for example, tungsten, aluminum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN, or other suitable materials, combinations thereof, or multi-layers thereof. The metal material ML may be deposited by CVD, physical vapor deposition (PVD), sputter deposition, or other techniques suitable for depositing conductive materials. The material of the metal material ML may be the same or different from that of the features132-136.

Referring toFIG. 8B, the method500proceeds to operation526where a planarization process is performed to form circuit features in the device region and overlay features in the mark regions. Referring toFIG. 9I, the method500may proceeds to operation526where a planarization process is performed to remove an excess portion of the metal material ML (referring toFIG. 9H) out of the openings142-146and O1-O3. The planarization process may be a chemical-mechanical polish (CMP) process that uses a slurry to chemically react with a target surface, and then removing the reacted target surface by polishing. After the planarization process, the remaining portions of the metal material ML forms second features152,154, and156in the openings142,144, and146, respectively and forms second overlay features162,164, and166in the openings O1, O2and O3, respectively. The second features152-156and162-166has top surfaces TS1and TS2coplanar with a top surface140T of the ILD layer140.

A combination of the overlay features132and152may be referred to as optical overlay marks300(referring toFIG. 1) in mark region MR11in this context, and a combination of the overlay features132and162may be referred to as another optical overlay marks300(referring toFIG. 1) in mark region MR12in this context. A combination of the overlay features134,154, and164may be referred to as electron-based overlay marks400(referring toFIG. 1) in this context. The first and second circuit features136,156and166may form source/drain contacts, contact vias, and gate contacts connected with a device200(e.g., SRAM cell/devices). The electron-based overlay marks400are integrally formed with the source/drain contacts, the contact vias, and the gate contacts and have similar pattern and appearance. It is noted that the optical overlay marks300and the electron-based overlay marks400(referring toFIG. 1) are dummy, and not tested by Wafer Acceptance Test (WAT).

In the present embodiments, referring toFIG. 8B, the method500proceeds to operation528where an after-planarization inspection (API) is performed with an electron-based system. The electron-based system provides a higher imaging resolution than that of an optical microscope, and is suitable for detecting the small overlay features134,154, and164. However, due to the coverage of the ILD layer140, in some cases, an electron-based system used for detecting surface topography may not detect the underlying pattern, such as the first overlay feature134. For example, an electron-based system using a low landing voltage (e.g., lower than 5 kilovolts (kV)) may be incapable of obtaining image information of the first overlay feature134.

In the present embodiments, as shown inFIGS. 2B-2C,FIG. 7, andFIG. 9I, an electron beams B1is incident onto a planar surface including the surfaces TS1, TS2, and140T. The landing energy of the electron beams B1is so high that while a portion of the electron beam may be reflected by the second overlay features154and164, another portion of the electron beam may penetrate the ILD layer140and be reflected by the first overlay features134, and the reflected electron beam may penetrate the ILD layer140. Through the configuration, a see-through electron-based image includes information of the first overlay features134and the second overlay features154and164of the mark400is captured. In some embodiments, the see-through electron-based image may also include information of the gate structures115, the source/drain features116(referring toFIG. 2C), and the fins112a(referring toFIGS. 2A and 2C).

In some embodiments, an overlay analysis is performed based on the inspection result of API, the overlay analysis includes determination of the overlay error between two overlay structures (e.g., the first and second overlay features134,154,164, the gate structures115, the source/drain features, and the fins). The determination of overlay errors is exemplarity illustrated as the overlay error estimation method inFIG. 4, and not repeated herein. The overlay analysis may further include perform high order overlay analysis. To be specific, the overlay analysis determines the overlay error between the first overlay feature134and the second overlay feature154, and the overlay error between the first overlay feature136and the second overlay feature164formed on the pre-layer structure110. In some embodiments, the overlay analysis may further determine the overlay error between the fins112a(referring toFIGS. 2A and 2C) and the gate structures115, the fins112a(referring toFIGS. 2A and 2C) and the epitaxial source/drain features116(referring toFIG. 2C), and the gate structures115and the epitaxial source/drain features116(referring toFIG. 2C).

In some cases, the CMP process may erode the top surfaces of the overlay features in the marks300and/or400, such that the overlay features may be damaged during the CMP process. The damaged overlay features may result in incorrect overlay errors in the following measurements.

In the present embodiments, the method500may proceed to operation530where the exposure tool820inFIG. 12is adjusted according to the overlay error obtained from the API, ADI, or AEI, and then used for exposing photoresists of subsequent wafers. In the present embodiments, the overlay error obtained from API may be sent back to a computer (as shown inFIG. 13) that controlling the exposure tool (e.g., the exposure tool820inFIG. 12as used in operations508and516inFIGS. 8A and 8B) with consequence that provide an offset to the overlay features, thereby improving CMP process for next coming wafer. For example, by adjusting a reticle of the exposure tool, the positions of the overlay features are compensated with an offset, thereby reducing the CMP erosion. For example, a compensation value is determined based on the overlay error, and the compensation value is implemented in the exposure tool820inFIG. 12to compensate settings of the exposure tool820and thereby improve overlay condition between the features. For example, a position of a reticle824of the exposure tool820(referring toFIG. 12) may be adjusted according to the compensation value. The exposure tool820with the implemented compensation value is then used for exposing photoresists of subsequent wafers.

Although the second features152-156and162-166are formed by the same metal overfilling operation and planarization process, it should not limit the scope of the present disclosure. In some other embodiments, prior to the formation of the openings O1-O3, a metal material may overfill the openings142-146, and a planarization process may be performed to remove excess metal material out of the openings142-146, thereby forming the features152-156. In such embodiments, an API may be performed after the formation of the features152-156and prior to the formation of the openings O1-O3. In some aspects, the openings O1-O3may be formed prior to the formation of the openings142-146. In such aspects, in some embodiments, the openings O1-O3and142-146may be filled with metal materials to form the features152-156and162-166. In such aspects, in some alternative embodiments, prior to the formation of the openings142-146, a metal material may overfill the openings O1-O3, and a planarization process may be performed to remove excess metal material out of the openings O1-O3, thereby forming the features162-166, in which an API may be performed after the formation of the features162-166and prior to the formation of the openings142-146. In some aspects, the openings O1-O3and the openings142-146may be formed by the same lithography and etching processes. In some embodiments, an additional API may be performed at the operation502. The API may be used in observing other features, such as gate structures, fins, source/drain regions, and not limited to the exemplary conductive features.

FIG. 10is a flow chart of a method700for selecting an optical overlay mark according to some embodiments of the present disclosure. The method700is performed for selecting one kinds of the sub-optical marks300S1-300S9(referring toFIG. 5A) that is less influenced by the photoresist shrinkage, the etch loading effect, mark damage, or other process effect for wafer, thereby determining the sub-selected optical mark as a standard optical mark in a fabrication process of next wafer. It is understood that additional operations may be provided before, during, and after the steps shown byFIG. 10, and some of the steps described below can be replaced or eliminated for additional embodiments of the method700. The order of the operations/processes may be interchangeable. In some embodiments, the method700may be performed after the method500ofFIGS. 8A and 8B. For example, the method700begins at step702where an electron-based image is obtained by the electron-based system900(referring toFIG. 7) as a result of the API, for example, in the operation528ofFIG. 8B.

Reference is made toFIG. 9IandFIG. 10. The method700proceeds to step704where both the pattern of the first layer (e.g., the first overlay features134) and the pattern of the second layer (e.g., the second overlay features154and/or164) of the electron-based overlay mark400in the electron-based image are recognized. In some embodiments, the ILD layer140that covers the pattern of first layer (e.g., the first overlay features134) may be too thick to transport the electrons, such that the detected pattern of the first layer (e.g., the first overlay features134) may be much less clear than the detected pattern of the second layer (e.g., the second overlay features154and/or164). If the pattern of the first layer (e.g., the first overlay features134) is not clear enough for the recognition, the method700repeats step702for obtaining another electron-based image by tuning the electron-based system900. For example, at least one of the condense degree, the landing voltage, and other parameters of the electron-based system900(referring toFIG. 7) is tuned, such that another electron-based image may be clearer than the previous electron-based image. If the pattern of first layer (e.g., the first overlay features134) is clear enough for the recognition, the method700proceeds to step706where an overlay error estimation is performed, so as to obtain plural overlay errors at plural regions. For example, the overlay error estimation is the overlay error estimation method M which has been illustrated inFIG. 4.

The method700further includes a step706where an optical-based image is obtained by the optical-based system830(referring toFIG. 13) as a result of the ADI or AEI, for example, in the operations510,514,518,522ofFIGS. 8A and 8B.

The overlay errors may be determined and estimated according to positions of selected point (e.g., the positions of the pattern of first layer, such as the first overlay features132-136) and position of the corresponding overlay structure (e.g., the pattern of the second layer such as the second overlay features152-156and/or162-166, the etched ILD layer140, or the photoresist PR1′/PR2′). Herein, for better description, the overlay errors obtained after developing/etching/planarization are referred to as ADI/AEI/API overlay errors, respectively. For example, referring toFIG. 1, each of the electron-based overlay marks400has an API overlay error obtained from the electron-based image, in which, for example, the method M shown inFIG. 4may be used for determining the overlay errors. Also, referring toFIGS. 5A-5C, each of the marks300S1and300S2has an ADI/AEI overlay error obtained from the optical-based image. In some embodiments, a distance between the marks400and the adjacent marks300S1/300S2is designed to be in a range from about 0 millimeter to about 0.5 millimeter.

Referring toFIGS. 10 and 11A-11C, the method700proceeds to step710where overlay correction maps are modeled and demonstrated.FIGS. 11A and 11Bare ADI overlay correction maps using the ADI overlay errors measured from the optical overlay marks300S1and300S2(referring toFIGS. 5A-5C) according to some embodiments of the present disclosure, respectively.FIG. 11Cis an API overlay correction map using the API overlay errors measured from an electron-based overlay mark400according to some embodiments of the present disclosure. The overlay errors may be determined by checking if the positions of the selected points match with the positions of the corresponding overlay marks. When there is a position difference between the selected points and the corresponding overlay structure, the overlay errors may be represented using the vectors V1illustrating the position difference and direction difference between the selected points and the corresponding overlay marks. It is noted that vectors V1inFIG. 11A-11Care exemplarily depicted. The overlay error vectors V1may be formed by comparing, on a point-to-point basis, the measured positions of the selected points and the positions of the corresponding overlay structure.

In some cases, the API overlay errors of the electron-based overlay marks400may be different from the ADI/AEI overlay error of the marks300S1and300S2adjacent to the electron-based overlay marks400due to the photoresist shrinkage, the etch loading effect, mark damage, or other process effect. The different configurations of the marks300S1and300S2may results in different ADI/AEI overlay errors of the marks300S1and300S2.

Still referring toFIGS. 10 and 11A-11C, the method700proceeds step712where the ADI overlay correction maps ofFIGS. 11A and 11Bare compared with the API overlay correction map ofFIG. 11C, and a target optical overlay mark is reselected based on the comparison result. For example, an API overlay error of one electron-based overlay mark400is respectively compared with the ADI/AEI overlay errors of the marks300S1and300S2proximate to the electron-based overlay mark400. In the comparison process, one of the ADI overlay correction maps ofFIGS. 11A and 11Bsimilar to the API overlay correction map ofFIG. 11C, is found, and the optical overlay mark corresponding to said one of the ADI overlay correction maps ofFIGS. 11A and 11Bis reselected for next wafer for enhancing the yield rates. For example, a correlation coefficient of the API overlay correction map ofFIG. 11Cand the ADI overlay correction maps ofFIGS. 11A and 11Bis calculated, and a relationship is built between the API overlay correction map ofFIG. 11Cand the ADI overlay correction maps ofFIGS. 11A and 11B. In some embodiments, the relationship may be linear.

In some embodiments, for example, the ADI overlay correction map ofFIG. 11Bhas higher correlation with the API overlay correction map than that ofFIG. 11A, therefore the optical mark300S2used inFIG. 11Bis reselected for next wafer, and vise versa. The selected mark300S2is believed to be less influenced by photoresist shrinkage, etch loading effect, and/or mark damage during plural fabrication processes (e.g., lithography, etching, CMP, or the like), than other sub-optical marks (e.g., the mark300S1), such that the selected mark300S2is beneficial for checking the overlay condition of next wafer.

In the present embodiments, one of the sub-optical marks300S1and300S2(referring toFIGS. 5A-5C) is reselected based on the ADI and API overlay correction maps. However, it should not limit the scope of the present disclosure. In some other embodiments, the optical overlay marks300S1/300S2(referring toFIGS. 5A-5C) is reselected based on the AEI and API overlay correction maps. For example, two AEI overlay correction maps (not shown) are compared with the API overlay correction as shown inFIG. 11C, and one of the AEI overlay correction maps has higher correlation with the API overlay correction map than that of the other one of the AEI overlay correction maps is determined, and the optical overlay mark corresponding to said one of the AEI overlay correction maps is reselected for next wafer.

To be specific, the method700proceeds step714where another wafer is optically inspected by the optical-based system830(referring toFIG. 12), and thereby obtaining another optical-based image. For example, a photoresist layer is formed over the another wafer, exposed by light pattern, and developed to form plural openings in the photoresist layer. The openings in the photoresist layer are inspected by the optical-based system830(referring toFIG. 12), after the development, as an ADI inspection. Herein, the another wafer may include first and second optical overlay marks corresponding to the optical overlay marks300S1and300S2. That is, the first and second optical overlay marks of the another wafer may have the same configuration as that of the marks300S1and300S2of the previous wafer. For clear illustration, herein, the marks300S1is reselected at step712, in which the first optical overlay mark of the another wafer has the same configuration as that of the mark300S1of the previous wafer

Herein, a portion of the another optical-based image of the first optical overlay mark corresponding to the selected optical mark300S1is analyzed to obtain overlay error. If the overlay error is within an acceptable range, the photoresist layer may be hard baked, and the method proceeds to following fabrication process, such as etch and planarization processes. If the overlay error is out of specification (e.g., greater than an acceptable range), the method700proceeds step716where the another wafer may be sent to rework with adjusting the exposure tool820(referring toFIG. 12) according to the overlay error. To be specific, a rework process may be initiated, such as removing the overlying photoresist layer from the another wafer and forming another photoresist over the another wafer with consequence that re-optimizes the exposure tool control algorithm for exposing photoresist. In some embodiments, a compensation value is determined based on the overlay error generated from the optical-based image, and the compensation is implemented in the exposure tool820inFIG. 12to compensate settings of the exposure tool820and thereby improve overlay condition between the overlay features. For example, a position of a reticle824of the exposure tool820(referring toFIG. 12) may be adjusted according to the compensation value. The exposure tool820with the implemented compensation is then used for exposing photoresists of subsequent wafers.

FIG. 12is a schematic view of a lithography system according to some embodiments of the present disclosure. The lithography system includes an exposure tool820, an optical-based system830, and a stage840. The exposure tool820is used to perform a lithography exposure process to a resist layer coated on the wafer100.

The exposure tool820includes a radiation source822, a reticle824, and an optical module826. The radiation source822is configured to provide a radiation energy to the wafer100. The reticle824is configured to provide the radiation energy from the radiation source822with a pattern. There may be plural different reticles824for providing patterns for different layers of the wafer100. The optical module826is configured to modulate and direct the radiation energy having the pattern to the wafer100.

In some embodiments, the radiation source822may be any radiation source suitable for exposing a resist layer. In various examples, the radiation source822may include a light source selected from the group consisting of ultraviolet (UV) source, deep UV (DUV) source, extreme UV (EUV) source, and X-ray source. In alternative embodiments, the radiation source822is an electron beam (e-beam) source for exposing a resist layer by a proper mode, such as direct writing. In such a case, the reticle824is not used during the exposing processes.

In some embodiments, the reticle824includes a transparent substrate and a patterned absorption layer. The transparent substrate may use fused silica (SiO2) relatively free of defects, such as borosilicate glass and soda-lime glass. The absorption layer may include a metal film such as chromium (Cr) for absorbing light directed thereon. The absorption layer is further patterned to have one or more openings in the metal film through which a light beam may travel without being completely absorbed. In some other embodiments where the radiation source822generates EUV radiation, the reticle824is designed to have reflective mechanism. For example, the reticle824may include a substrate coated with tens of alternating layers of silicon and molybdenum to act as a Bragg reflector that maximizes the reflection of EUV light.

The optical module826may be designed to have a refractive mechanism or reflective mechanism. In a refractive mechanism, the optical module826includes various refractive components, such as lenses. In a reflective mechanism, the optical module826includes various reflective components, such as mirrors.

The optical-based system830measures a position information of an overlay marks300on the wafer100. The overlay marks300herein may stand for the overlay marks300inFIG. 1. The stage840holding the wafer100or a stage holding the reticles824may move based on the aforementioned compensate values calculated and obtained from the measurement result (e.g., the aforementioned optical-based image or the aforementioned electron-based image) to reduce the overlay error in the future exposure process.

In some embodiments, referring toFIG. 12, the optical-based system830includes a light source832, an optical assembly834, and an optical detector836. The light source832is configured to emit a light beam. The light source832may be coherent or incoherent. In some embodiments, the light source832is capable of emitting a visual light, an infrared light, a near-infrared (NIR) light, a far-infrared (FIR) light, a violet light, an ultra-violet (UV) light, or a combination thereof. In some embodiments, the light source832is a laser source such as a solid state laser source, a dye laser source, or another suitable laser source. The light beam may have one or more wavelengths and at least one of the wavelengths is suitable for overlay measurement. For example, the light beam may have a wavelength of 532 nanometer (nm), 633 nm, 780 nm, 850 nm, or a combination thereof.

In some embodiments, the optical assembly834includes optical components such as polarizers, lens, mirrors, beam splitters, and/or fiber optics. The optical assembly834receives the light beam from the light source832and projects a modulated light beam onto a target device (such as a wafer100), positioned on a substrate stage840.

In some embodiments, the substrate stage840is operable to move such that the modulated light beam scans through one or more overlay marks300. The modulated light beam reflected off the overlay marks300, carries imaging information about the overlay marks300. The light beam is collected by the optical detector836for overlay analysis. In some embodiments, the optical detector836includes light sensors and other optical components such as lens, beam splitters, and/or cameras.

FIG. 13is a block diagram illustrating the system800for the overlay measurement and control according to some embodiments of the present disclosure. The system800includes the controller810(e.g., computer), the exposure tool820(also shown inFIG. 12), the optical based system830(also shown inFIG. 12), and the electron-based system900(also shown inFIG. 7). The controller810is coupled with the exposure tool820, the optical based system830, and the electron-based system900. For example, the controller810is electrically connected to the particle source910, the scanner930, the wafer stage940, and the detector950of the electron-based system900(referring toFIG. 7). The controller810is for calculating overlay measurements based on the optical images obtained from the system830, calculating overlay measurements based on the electron-based images obtained from the electron-based system900, and adjusting the exposure tool820based on these overlay measurements. In some embodiments, the controller810performs the method M for determining the overlay errors of the electron-based overlay marks as shown inFIG. 4. In some embodiments, the controller810performs the method700for selecting the overlay mark300for next wafer as shown inFIG. 10.

Based on the above discussions, it can be seen that the present disclosure offers advantages. It is understood, however, that other embodiments may offer additional advantages, and not all advantages are necessarily disclosed herein, and that no particular advantage is required for all embodiments. One advantage is that both underlying features and upper features are detected in one electron-based image by the electron-based system using a high landing voltage for the overlay measurements. Another advantage is that the electron-based overlay mark having underlying features and upper features for the overlay measurements has a small size for intra-field distribution. Another advantage is that the patterns of the electron-based overlay mark may be dummy and integrated formed with the circuit patterns. Another advantage is that the overlay measurements is performed at AEI/API stages for obtaining clear and complete view of overlay error and further offset corrections, which is directly related to yield enhancement. Still another advantage is that an overlay reference standard for inline overlay correction mapping and control is generated, for example, at ADI, and the overlay compensation is earlier than PFA (physical failure analysis), thereby preventing large loss due of PFA failure and saving times.

According to some embodiments of the present disclosure, a method includes forming at least one first overlay feature in a first dielectric layer over a first wafer; forming a second dielectric layer over the first overlay feature and the first dielectric layer; forming at least one opening in the second dielectric layer by at least using an exposure tool; forming at least one second overlay feature in the opening of the second dielectric layer, such that a first edge of the first overlay feature is covered by the second dielectric layer; directing an electron beam to the first and second overlay features and the second dielectric layer; detecting the electron beam reflected from the first overlay feature through the second dielectric layer and from the second overlay feature by a detector; obtaining, by a controller, at least one overlay error between the first overlay feature and the second overlay feature according to the reflected electron beam electrically connected to the detector

According to some embodiments of the present disclosure, a method includes capturing a plurality of reference electron-based images of a plurality of portions of a reference mark of a semiconductor structure by a detector; obtaining, by a controller, a plurality of reference overlay errors respectively corresponding to the portions of the reference mark connected to the detector; developing, by the controller, an inference model according to the reference electron-based images and the reference overlay errors; capturing an electron-based image of an overlay mark of the semiconductor structure; determining, by the controller, an estimated overlay error corresponding to the overlay mark from the electron-based image using the inference model.

According to some embodiments of the present disclosure, a method includes capturing, by an optical detector, an optical image of a first optical mark and a second optical mark on a first wafer; obtaining, by a controller, a first overlay error of the first optical mark and a second overlay error of the second optical mark from the optical image; capturing, by an electron beam detector, an electron-based image of an electron-based mark on the first wafer; obtaining, by the controller, a third overlay error of the electron-based mark from the electron-based image; determining, by the controller, the first optical mark as a standard optical mark by comparing the first overlay error and the second overlay error with the third overlay error, wherein a correlation between the first overlay error and the third overlay error is higher than a correlation between the second overlay error and the third overlay error; and using, by the controller, a third optical mark of a second wafer as a standard optical mark for a semiconductor process on the second wafer, wherein the third optical mark of the second wafer has the same configuration as the first optical mark of the first wafer. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.