Binary hysteresis equal comparator circuits and methods

Binary hysteresis equal comparator circuits and methods. An equal comparator does not indicate an equal condition until the two binary input values are exactly the same. However, after the two binary input values first become equal, a window of variation comes into effect, within which the first of the two values is allowed to vary while the circuit continues to report an equal condition. This window can extend only above the equal condition, only below the equal condition, or both above and below the equal condition. The width of the window is determined by providing one or two predetermined constant values, a first constant defining the amount of hysteresis provided above the second value, and a second constant defining the amount of hysteresis provided below the second value. Related methods are also described of performing equal comparisons while providing binary hysteresis.

FIELD OF THE INVENTION

The invention relates to digital circuits that provide hysteresis. More particularly, the invention relates to equal comparator circuits providing binary hysteresis.

BACKGROUND OF THE INVENTION

The term “hysteresis” generally refers to the process of compensating for variations (e.g., “noise”) in an input signal by adjusting the point at which a system reacts to the input signal. For example, in electrical circuits a rising signal can be detected at a first and higher voltage level (the “rising edge trip point”), while a falling signal can be detected at a second and lower voltage level (the “falling edge trip point”).FIGS. 1–3are waveform diagrams that can be used to describe this type of hysteresis, which is referred to herein as “level hysteresis”.

FIG. 1illustrates the process of an ideally clean input signal IN rising and falling, and its effect on an output signal OUT of inverter101. Input signal IN rises linearly from a low value (e.g., a ground value) to a high value (e.g., power high VDD). Half-way through the rising edge, at time Tr, the voltage level on signal IN reaches the trip point tp and inverter101is triggered. Thus, the output signal OUT from inverter101begins to fall. Signal OUT also falls linearly in this ideal circuit, from the high value to the low value. After a time, input signal IN changes state again, falling linearly from the high value to the low value. Half-way through the falling edge, at time Tf, the voltage level on signal IN reaches the trip point tp and inverter101is triggered. Thus, the output signal OUT from inverter101begins to rise. Signal OUT also rises linearly in this ideal circuit, from the low value to the high value. Thus, signal OUT is a noise-free output signal ideally suited to drive other circuitry.

FIG. 2illustrates what happens to the idealized signals ofFIG. 1in a noisy signal environment. Both the rising and falling edges of signal IN are subject to sudden alterations that can momentarily cause the signal to rise above, then fall below, the trip point tp. Each time input signal IN rises above the trip point (e.g., at times T1, T3, and T5), output signal OUT changes from the high value to the low value. Each time input signal IN falls below the trip point (e.g., at times T2, T4, and T6), output signal OUT changes from the low value to the high value. The result is a noisy output signal OUT, as shown inFIG. 2.

FIG. 3illustrates the resulting waveforms when inverter101is replaced by a Schmitt trigger301. Schmitt triggers are well known. For example, one Schmitt trigger is described by Hsieh in U.S. Reissue Patent No. Re. 34,808, “TTL/CMOS Compatible Input Buffer with Schmitt Trigger”, which is incorporated herein by reference. A Schmitt trigger provides level hysteresis in the manner previously described, by providing different trip points for the rising and falling edges of the input signal. The rising edge trip point tpr is higher than the falling edge trip point tpf. Thus, the brief and limited negative movements in voltage level during the rising edge of input signal IN do not cause the output signal OUT to rise to the high value. Similarly, the brief and limited positive movements in voltage level during the falling edge of input signal IN do not cause the output signal OUT to fall to the low value. Hence, the circuit ofFIG. 3is noise-immune, provided the extent of the noise does not exceed the protection provided by the difference in trip-points.

Schmitt triggers can be very useful, when they are available. However, they do have their drawbacks in some applications. For example, Schmitt triggers are analog circuits that cannot readily be implemented in the digital programmable logic generally available in programmable logic devices (PLDs). PLDs typically provide arrays of digital logic elements that can be programmed to assume various configurations performing desired digital functions. However, analog functions typically cannot be implemented in a PLD unless they are deliberately included in the fabric of the PLD by the PLD designer and manufacturer.

Therefore, it is desirable to provide digital circuits and methods of providing hysteresis, e.g., hysteresis circuits and methods that can be implemented in digital PLDs.

SUMMARY OF THE INVENTION

The invention provides binary hysteresis equal comparator circuits and methods. An equal comparator according to the present invention does not indicate an equal condition until the two binary input values are exactly the same. However, after the two binary input values first become exactly equal, a window of variation comes into effect, within which the first of the two values is allowed to vary while the circuit continues to report an equal condition. The window of allowable variation provides hysteresis to the first binary input value. This window can extend only above the equal condition, only below the equal condition, or both above and below the equal condition. The width of the window is determined by providing one or two predetermined constant values, a first predetermined constant defining the amount of hysteresis provided above the second value, and a second predetermined constant defining the amount of hysteresis provided below the second value. In some embodiments, the two constants are the same, e.g., a single constant is used to perform both functions. Further, because the equal comparator is evaluating the relationship between the first and second binary values, hysteresis is also provided to the second binary value.

Applications for these circuits include, for example, control circuits in situations subject to signal noise. Exemplary digital circuits are easily implemented using the digital programmable elements provided in programmable logic devices (PLDs), for example. These circuits can be used, for example, in clocking circuits to compensate for variations in temperature and power supply.

The invention also encompasses related methods of performing equal comparisons between first and second binary values while providing binary hysteresis.

DETAILED DESCRIPTION OF THE DRAWINGS

In the following description, numerous specific details are set forth to provide a more thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention can be practiced without these specific details.

FIG. 4illustrates a first equal comparator circuit having binary hysteresis, according to one embodiment of the present invention. “Binary hysteresis” differs from “level hysteresis” in that instead of providing two different voltage trip points for the rising and falling edges of an input signal, two different values are used when comparing increasing and decreasing binary values.

The circuit ofFIG. 4includes two registers401–402, two adder circuits403and405, two overflow prevention circuits404and406, three multiplexer circuits407–408and414, a NOR gate413, a D-type flip-flop415, and three comparator circuits410–412. Because the circuit compares two binary values, the two input signals AIN and BIN are each multi-bit signals. (In the present specification, the same reference characters are used to refer to terminals, signal lines, and their corresponding signals.) In the pictured embodiment, input signals AIN and BIN are each M bits wide, where M is an integer. Similarly, many of the elements inFIG. 4and the other figures herein represent M-bit-wide circuits, as will be clear to those of skill in the art on perusal of the figures.

M-bit register401registers data provided by M-bit input terminal AIN, and provides M-bit signal RAIN. Similarly, M-bit register402registers data provided by M-bit input terminal BIN, and provides M-bit signal RBIN. Registers401–402are both clocked by signal CLK and reset by signal RST.

“+w” (plus w) adder circuit403takes the value of signal RBIN and adds a constant w, providing the resulting value to the “0” data terminal of multiplexer circuit407. Signal RBIN is also provided to the “1” data terminal of multiplexer circuit407. Maximum overflow prevention circuit404is driven by signal RBIN and provides a single-bit output signal MAX to the select terminal of multiplexer circuit407. Multiplexer circuit407drives the B input terminal of A>B comparator411, while the A input terminal is driven by signal RAIN. The output terminal of A>B comparator411provides signal A—GT—B.

“−x” (minus x) adder circuit405(a subtractor) takes the value of signal RBIN and subtracts a constant x, providing the resulting value to the “0” data terminal of multiplexer circuit408. Signal RBIN is also provided to the “1” data terminal of multiplexer circuit408. Minimum overflow prevention circuit406is driven by signal RBIN and provides a single-bit output signal MIN to the select terminal of multiplexer circuit408. Multiplexer circuit408drives the B input terminal of A<B comparator412, while the A input terminal is driven by signal RAIN. The output terminal of A<B comparator412provides signal A—LT—B.

Signals A—GT—B and A—LT—B are combined in NOR gate413, which drives the “1” data terminal of multiplexer circuit414. Signal A—EQ—B is provided to the “0” data terminal of multiplexer circuit414. Multiplexer circuit414drives the data input terminal D of flip-flop415. Clock signal CLK is inverted by inverter409and provided to the clock input terminal CK of flip-flop415. Reset signal RST is provided to the reset terminal R of flip-flop415. The output terminal OUT—EQ of flip-flop415provides circuit output signal OUT—EQ and is coupled to the select terminal of multiplexer circuit414.

Broadly speaking, the circuit ofFIG. 4includes three comparator circuits. A first comparator circuit410checks for equal values between the registered versions (RAIN and RBIN) of signals AIN and BIN. When the two values of signals RAIN and RBIN are equal, signal A—EQ—B is high; otherwise, signal A—EQ—B is low. A second comparator circuit411utilizes a first hysteresis circuit (comprising elements403–404and407) to check for a condition in which signal RAIN is greater than signal RBIN by more than a predetermined constant w. When this condition is satisfied, signal A—GT—B is high; otherwise, signal A—GT—B is low. A third comparator circuit412utilizes a second hysteresis circuit (comprising elements405–406and408) to check for a condition in which signal RAIN is less than signal RBIN by more than a predetermined constant x. When this condition is satisfied, signal A—LT—B is high; otherwise, signal A—LT—B is low.

The circuit ofFIG. 4operates as follows. Initially, flip-flop415is reset. Thus, signal OUT—EQ is low, and the value of A—EQ—B is passed to the data input terminal D of flip-flop415. Thus, signal OUT—EQ does not go high until signals RAIN and RBIN are exactly equal (and, in the pictured embodiment, an active edge is received on clock signal CK).

Assume first that signal RAIN increases from the value of RBIN to a value greater than RBIN. Adder circuit403adds a value of w to signal RBIN. Therefore, the output of adder circuit403is RBIN+w. Signal MAX is high only when adding the constant w to signal RBIN causes adder circuit403to exceed the maximum value that can be represented by M bits. When signal MAX is low, multiplexer circuit407selects the signal RBIN+w and provides this value to the B input terminal of comparator411. Thus, signal A—GT—B will go high only when signal RAIN is greater than signal RBIN by a value greater than w.

When signal MAX is high, multiplexer circuit407selects the signal RBIN and provides this value to the B input terminal of comparator411. Thus, as the value of signal RBIN approaches within a value w of the maximum value that can be represented by M bits, signal A—GT—B represents the simple “greater-than” value, without hysteresis.

When signal A—GT—B goes high, NOR gate413provides a low value to the “1” data input terminal of multiplexer circuit414. Because signal OUT—EQ is high, this low value is passed to the data input terminal D of flip-flop415. At the next active edge of clock signal CK, signal OUT—EQ goes low again.

Secondly, assume that signal RAIN decreases from the value of RBIN to a value less than RBIN. Adder circuit405subtracts a value of x from signal RBIN. Therefore, the output of adder circuit405is RBIN−x. Signal MIN is high only when subtracting the constant x from signal RBIN causes adder circuit405to produce a negative result. When signal MIN is low, multiplexer circuit408selects the signal RBIN−x and provides this value to the B input terminal of comparator412. Thus, signal A—LT—B will go high only when signal RAIN is less than signal RBIN by a value greater than x.

When signal MIN is high, multiplexer circuit408selects the signal RBIN and provides this value to the B input terminal of comparator412. Thus, as the value of signal RBIN approaches within a value x of zero, signal A—LT—B represents the simple “less-than” value, without hysteresis.

When signal A—LT—B goes high, NOR gate413provides a low value to the “1” data input terminal of multiplexer circuit414. Because signal OUT—EQ is high, this low value is passed to the data input terminal D of flip-flop415. At the next active edge of clock signal CK, signal OUT—EQ goes low again.

FIG. 5illustrates an exemplary embodiment of overflow prevention circuit404that can be used, for example, in the binary hysteresis comparator circuit ofFIG. 4. In the embodiment ofFIG. 5, M is four and the constant w is a binary one (0 . . . 01). (In other embodiments, M and/or w have other values.) Thus, signal MAX needs to be high only when adding one to signal RBIN causes adder circuit403to roll over from all ones to all zeros. Thus, the circuit ofFIG. 5checks for a value of all ones on signal RBIN. In some embodiments, overflow prevention circuit404checks for a value of RBIN equal to a value of (“all ones”−w+1). In other embodiments, overflow prevention circuit404checks for a value of RBIN greater than or equal to a value of (“all ones”−w+1).

The circuit ofFIG. 5comprises a NAND gate501driving an inverter502, which provides signal MAX. Signals RBIN[3]–RBIN[0] are provided to the input terminals of NAND-gate501.

Clearly, the circuit ofFIG. 5can be implemented in many different ways. For example, in another embodiment in which M is four and w is one, the overflow prevention circuit is similar to the circuit ofFIG. 5, but with inverter502omitted. Signal MAX is replaced by signal MAX—B, which is low when signal RBIN is all ones. Thus, the “0” and “1” data input terminals of multiplexer circuit407are reversed.

FIG. 6illustrates an exemplary embodiment of overflow prevention circuit406that can be used, for example, in the binary hysteresis comparator circuit ofFIG. 4. In the embodiment ofFIG. 6, M is four and the constant x is one. (In other embodiments, M and/or x have other values.) Thus, signal MIN needs to be high only when subtracting one from signal RBIN causes adder circuit403to roll over from all zeros to all ones. Thus, the circuit ofFIG. 6checks for a value of all zeros on signal RBIN. In some embodiments, overflow prevention circuit406checks for a value of RBIN equal to a value of (“all zeros”+x−1), or (x−1). In other embodiments, overflow prevention circuit406checks for a value of RBIN less than or equal to a value of (“all zeros”+x−1), or (x−1).

The circuit ofFIG. 6comprises a NOR gate601that provides signal MIN. Signals RBIN[3]–RBIN[0] are provided to the input terminals of NOR-gate601.

FIG. 7illustrates an exemplary embodiment of A-equals-B comparator410that can be used, for example, in the binary hysteresis comparator circuit ofFIG. 4. Note that any appropriate equal comparator can be used to implement circuit410inFIG. 4; the implementation shown inFIG. 7is merely exemplary. In the embodiment ofFIG. 7, M is four. The circuit includes XNOR (exclusive NOR) gates701–704, NAND gate705, and inverter706.

Signal A—NEQ—B is provided by NAND gate705, which is driven by XNOR gates701–704. Each of XNOR gates701–704compares two corresponding bits from the two 4-bit input signals A and B. XNOR gate701is driven by signals B[3] and A[3], XNOR gate702is driven by signals B[2] and A[2], and so forth. If any pair of corresponding bits includes two different values, the associated XNOR gate provides a low signal to NAND gate705, and signal A—NEQ—B goes high. Signal A—NEQ—B is inverted by inverter706to provide output signal O3(A—EQ—B).

In another embodiment (not shown), the circuit ofFIG. 7implemented using four XOR gates instead of XNOR gates701–704. NAND gate705is replaced by a NOR gate, while node A—NEQ—B and inverter706are omitted.

FIG. 8illustrates an exemplary embodiment of A-greater-than-B comparator411that can be used, for example, in the binary hysteresis equal comparator circuit ofFIG. 4. Note that any appropriate greater-than comparator can be used to implement circuit411inFIG. 4; the implementation shown inFIG. 8is merely exemplary. In the embodiment ofFIG. 8, M is four. The circuit ofFIG. 8includes inverters801–808, NAND gates811–819, and NOR gate821.

NAND gate814is driven by signal A[3], the most significant bit of signal A, and by signal B[3], the most significant bit of signal B, inverted by inverter801. NAND gate814drives NAND gate819, which provides the comparator output signal O2. Signal O2(A—GT—B) is high whenever the binary value of signal A is greater than the binary value of signal B.

NAND gate811is driven by signal B[3] and by signal A[3] inverted by inverter805. NAND gate815is driven by NAND gate811, signal A[2], and signal B[2] inverted by inverter802. NAND gate815also drives NAND gate819.

NAND gate812is driven by signal B[2] and by signal A[2] inverted by inverter806. NAND gate816is driven by NAND gate811, NAND gate812, signal A[1], and signal B[1] inverted by inverter803. NAND gate816also drives NAND gate819.

NAND gate813is driven by signal B[1] and by signal A[1] inverted by inverter807. NAND gate817is driven by NAND gate811and NAND gate812. NAND gate818is driven by NAND gate813, signal A[0], and signal B[0] inverted by inverter804. NOR gate821is driven by NAND gates817and818, and drives inverter808, which also drives NAND gate819. Note that inverter808, NOR gate821, and NAND gates817and818together implement a 5-input NAND gate NAND5.

FIG. 9illustrates an exemplary embodiment of A-less-than-B comparator412that can be used, for example, in the binary hysteresis equal comparator circuit ofFIG. 4. Note that any appropriate less-than comparator can be used to implement circuit412inFIG. 4; the implementation shown inFIG. 9is merely exemplary. In the embodiment ofFIG. 9, M is four. The circuit ofFIG. 9is the same as the circuit ofFIG. 8, but with the A and B input signals reversed. Thus, the circuit is not described here. Signal O1(A—LT—B) is high whenever the binary value of signal A is less than the binary value of signal B.

The embodiment ofFIG. 4provides binary hysteresis to signal RAIN whenever RAIN is either increasing or decreasing in value. However, binary hysteresis can also be provided only for increasing values, or only for decreasing values.FIG. 10illustrates an equal comparator circuit providing binary hysteresis only for values of RAIN that are increasing in value. (Note that the circuit also provides hysteresis for values of RBIN that are decreasing in value.)

The circuit ofFIG. 10is the same as the circuit ofFIG. 4, except that adder circuit405, overflow prevention circuit406, and multiplexer circuit408are removed. Signal RBIN is provided directly to the B input terminal of A-less-than-B comparator412. Thus, circuit output signal OUT—EQ goes low as soon as signal RAIN decreases to a value less than RBIN. However, signal OUT—EQ does not go low in response to an increasing value for signal RAIN until signal RAIN is greater than signal RBIN by more than constant w.

FIG. 11illustrates an equal comparator circuit providing binary hysteresis only for values of RAIN that are decreasing in value. (Note that the circuit also provides hysteresis for values of RBIN that are increasing in value.) The circuit ofFIG. 11is the same as the circuit ofFIG. 4, except that adder circuit403, overflow prevention circuit404, and multiplexer circuit407are removed. Signal RBIN is provided directly to the B input terminal of A-greater-than-B comparator411. Thus, circuit output signal OUT—EQ goes low as soon as signal RAIN increases to a value greater than RBIN. However, signal OUT—EQ does not go low in response to an decreasing value for signal RAIN until signal RAIN is less than signal RBIN by more than constant x.

FIG. 12illustrates another binary hysteresis circuit according to another embodiment of the invention. The circuit ofFIG. 12is similar to the circuit ofFIG. 4, except that the hysteresis circuits are implemented in a different way. The first hysteresis circuit ofFIG. 4(comprising elements403–404and407), is replaced by a new hysteresis circuit comprising elements1203–1204and1207. The second hysteresis circuit ofFIG. 4(comprising elements405–406and408), is replaced by a new hysteresis circuit comprising elements1205–1206and1208.

The circuit ofFIG. 12operates as follows.

Assume first that signal RAIN increases from the value of RBIN to a value greater than RBIN. Signal MAX—B from overflow prevention circuit1204is low only when adding the constant w to signal RBIN causes the result to exceed the maximum value that can be represented by M bits. When signal MAX—B is high, multiplexer circuit1207passes the binary constant “w” to the s terminal of adder circuit1203. Thus, adder circuit1203adds “w” to the value of signal RBIN, and passes the resulting signal “RBIN+w” to the B input terminal of comparator411, as in the embodiment ofFIG. 4. When signal MAX—B is low, multiplexer circuit1207passes an all-zero value to the s terminal of adder circuit1203. Thus, adder circuit1203adds a “zero” to the value of signal RBIN, and passes the signal “RBIN” to the B input terminal of comparator411, as in the embodiment ofFIG. 4.

Secondly, assume that signal RAIN decreases from the value of RBIN to a value less than RBIN. Signal MIN from overflow prevention circuit1206is high only when subtracting the constant x from signal RBIN produces a negative result. When signal MIN is low, multiplexer circuit1208passes the binary constant “x” to the t terminal of adder circuit1205. Thus, adder circuit1205subtracts “x” from the value of signal RBIN, and passes the resulting signal “RBIN−x” to the B input terminal of comparator412, as in the embodiment ofFIG. 4. When signal MIN is high, multiplexer circuit1208passes an all-zero value to the t terminal of adder circuit1205. Thus, adder circuit1205subtracts a “zero” from the value of signal RBIN, and passes the signal “RBIN” to the B input terminal of comparator412, as in the embodiment ofFIG. 4.

In other embodiments (not shown), one or the other of the hysteresis circuits is omitted from the circuit ofFIG. 12.

The figures shown and described herein illustrate a variety of different equal comparator circuits providing binary hysteresis. It will be apparent to one skilled in the art after perusing the present specification and drawings that the present invention can be practiced within these and other architectural variations.

FIG. 13illustrates the steps of an exemplary method of performing an equal comparison between first and second binary values while providing binary hysteresis. These steps can be performed, for example, using the exemplary circuits illustrated in FIGS.4and10–12. However, other circuits can also be used.

In step1301, signal AIN (a first binary value) has an initial value of “init”. Signal BIN (a second binary value) has a different initial value. The circuit implementing the method reports that the first and second binary values are not equal (e.g., signal OUT—EQ is low). The initial value can be either greater than or less than the second binary value.

Signal AIN then assumes a new value, such that signals AIN and BIN are equal. In step1302, the circuit reports that the first and second binary values are equal (e.g., signal OUT—EQ goes high).

Signal AIN then assumes a first new value (“new1”), where the first new value differs from the second binary value by a value less than or equal to (i.e., not exceeding) a predetermined constant K (e.g., w or x in the exemplary circuits illustrated herein). The first new value can be either greater than or less than the second binary value. Instead of reporting that the two signals are not equal, in step1303the circuit continues to report that the first and second binary values are equal (e.g., signal OUT—EQ remains high).

Eventually, the first binary value assumes a second new value (“new2”) differing from the second binary value by a number exceeding the predetermined constant K. In step1304, the circuit reports that the first and second binary values are not equal, e.g., signal OUT—EQ goes low again.

FIG. 14illustrates the steps of another exemplary method of performing an equal comparison between first and second binary values while providing binary hysteresis. These steps can be performed, for example, using the exemplary circuits illustrated in FIGS.4and10–12. However, other circuits can also be used.

In step1401, signal AIN (a first binary value) has an initial value of “init”. Signal BIN (a second binary value) has a different initial value. The circuit implementing the method reports that the first and second binary values are not equal (e.g., signal OUT—EQ is low). The initial value can be either greater than or less than the second binary value.

Signal AIN then assumes a new value, such that signals AIN and BIN are equal. In step1402, the circuit reports that the first and second binary values are equal, (e.g., signal OUT—EQ goes high).

In a first scenario, signal AIN then assumes a first new value (“new1”). The first new value is greater than the second binary value by a value less than or equal to (i.e., not exceeding) a predetermined constant (e.g., w in the exemplary circuits illustrated herein). Instead of reporting that the two signals are not equal, in step1403the circuit continues to report that the first and second binary values are equal. Eventually, the first binary value assumes another new value (“new3”) greater than the second binary value by a number exceeding the constant w. In step1405, the circuit reports that the first and second binary values are not equal.

In a second scenario, after step1402signal AIN assumes a second new value (“new2”). The second new value is less than the second binary value by a value less than or equal to (i.e., not exceeding) a predetermined constant (e.g., x in the exemplary circuits illustrated herein). Instead of reporting that the two signals are not equal, in step1404the circuit continues to report that the first and second binary values are equal. Eventually, the first binary value assumes another new value (“new4”) less than the second binary value by a number exceeding the constant x. In step1406, the circuit reports that the first and second binary values are not equal.

Those having skill in the relevant arts of the invention will now perceive various modifications and additions that can be made as a result of the disclosure herein. For example, comparator circuits, comparators, A-equals-B comparators, A-greater-than-B comparators, A-less-than-B comparators, multiplexer circuits, adder circuits, adders, subtractors, overflow prevention circuits, registers, memory elements, flip-flops, inverters, NAND- and NOR-gates, and other components other than those described herein can be used to implement the invention. Active-high signals can be replaced with active-low signals by making straightforward alterations to the circuitry, such as are well known in the art of circuit design. Logical circuits can be replaced by their logical equivalents by appropriately inverting input and output signals, as is also well known.

Moreover, some components are shown directly connected to one another while others are shown connected via intermediate components. In each instance the method of interconnection establishes some desired electrical communication between two or more circuit nodes. Such communication can often be accomplished using a number of circuit configurations, as will be understood by those of skill in the art.

Accordingly, all such modifications and additions are deemed to be within the scope of the invention, which is to be limited only by the appended claims and their equivalents.