Systems and methods for synchronous, retimed analog to digital conversion

Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a latch based analog to digital converter is disclosed that includes a first interleave with a set of comparators, a selector circuit and a latch. The set of comparators is operable to compare an analog input with respective reference voltages, and is synchronized to a clock phase. The selector circuit is operable to select an output of one of the set of comparators based at least in part on a selector input. A first interleave output is derived from the selected output. The latch receives a second interleave output from a second interleave and is transparent when the clock phase is asserted. The selector input includes an output of the latch.

BACKGROUND OF THE INVENTION

The present inventions are related to systems and methods for processing digital signals, and more particularly to systems and methods for analog to digital conversion.

Analog to digital converters are used in a number of semiconductor devices to convert an analog electrical signal to a digital representation thereof. In the conversion process, a continuous analog signal is converted to a series of discrete or quantized digital values representing the analog signal at defined sample times. Simple analog to digital converters operate over a specified, static range of operation typically defined to encompass an expected analog input signal.FIG. 1depicts an exemplary prior art flash analog to digital converter100. Flash analog to digital converter100includes a comparator bank120including a number of comparators121,122,123,124,125that each receive a respective reference threshold (i.e., ref(n−1), ref(n−2), ref(3), ref(2) and ref(1)). In addition, each of comparators121,122,123,124,125receives an analog input105, and compares analog input105to the respective reference threshold. The reference thresholds are chosen such that the combined output of comparator bank120is a thermometer code indicated as a digital output170. When operating properly, digital output170includes an uninterrupted series of 0's followed by an uninterrupted series of is with the transition between 0s and is indicating the level of analog input105(i.e., a thermometer code without bubbles). In some cases, digital output170is provided to an encoder180that provides an encoded output190that may be more compact than a thermometer code.

In such a flash analog to digital converter, increased resolution is provided by reducing the level difference between successive reference voltages. Where the range of analog to digital converter100is to be maintained constant, increasing resolution requires a corresponding increase in the number of comparators. This has at least two disadvantages. First, additional comparators increase power and area consumption. Second, noise on analog input105and process differences in comparators121,122,123,124,125often results in production of an imperfect thermometer code (i.e., a thermometer code exhibiting bubbles) where the difference between successive reference voltages becomes small. Consequently, to compensate for the imperfections in the thermometer code, the complexity of encoder180increases substantially. This results in additional undesirable power and area costs.

Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for analog to digital conversion.

BRIEF SUMMARY OF THE INVENTION

The present inventions are related to systems and methods for processing digital signals, and more particularly to systems and methods for analog to digital conversion.

Various embodiments of the present invention provide latch based analog to digital converters. The latch based analog to digital converters include a first interleave with a set of comparators, a selector circuit and a latch. The set of comparators is operable to compare an analog input with respective reference voltages, and is synchronized to a clock phase. The selector circuit is operable to select an output of one of the set of comparators based at least in part on a selector input. A first interleave output is derived from the selected output. As used herein, the term “derived” is used in its broadest sense. Thus, as an example, the first interleave output derived from the selected output may be the same as the selected output. In other cases, the selected output may be buffered, registered or otherwise modified before becoming the first interleave output. The latch receives a second interleave output from a second interleave and is transparent when the clock phase is asserted. The selector input includes an output of the latch. In some instances of the aforementioned embodiments, the latch operates to mitigate inter symbol interference.

Other embodiments of the present invention provide methods for analog to digital conversion. The methods include providing a first interleave operable to generate a first output and a second interleave operable to generate a second output. Each of the first interleave and the second interleave includes a set of comparators, a selector circuit, and a latch. The methods include performing a set of analog to digital conversions using the set of comparators of the first interleave synchronous to a clock phase; selecting a result from the set of analog to digital conversions based at least in part on a latched result to provide the first output; and latching the second output using the latch of the first interleave. The latch is transparent when the clock phase is asserted, and the latched result includes an output of the latch.

Yet other embodiments of the present invention provide communication systems. Such communication systems include a receiver utilizing at least one latch based analog to digital converter. The latch based analog to digital converter includes a first interleave with a set of comparators, a selector circuit and a latch. The set of comparators is operable to compare an analog input with respective reference voltages, and is synchronized to a clock phase. The selector circuit is operable to select an output of one of the set of comparators based at least in part on a selector input. A first interleave output is derived from the selected output. The latch receives a second interleave output from a second interleave and is transparent when the clock phase is asserted. The selector input includes an output of the latch. In some instances of the aforementioned embodiments, the latch operates to mitigate inter symbol interference.

In some instances of the aforementioned embodiments, the systems include a transmitter and a medium. In such instances, information is provided from the transmitter to the receiver via the medium. In one particular case, the system is a storage system, and the medium is a storage medium. In another particular case, the system is a wireless communication system, and the medium is a wireless communication medium.

This summary provides only a general outline of some embodiments of the invention. Many other objects, features, advantages and other embodiments of the invention will become more fully apparent from the following detailed description, the appended claims and the accompanying drawings.

DETAILED DESCRIPTION OF THE INVENTION

The present inventions are related to systems and methods for processing digital signals, and more particularly to systems and methods for analog to digital conversion.

A dynamic range analog to digital converter is a special purpose analog to digital converter that may be used for detecting a bit sequence transmitted through a known channel. An example of a dynamic analog to digital converter is described in U.S. patent application Ser. No. 12/108,791 entitled “Analog-To-Digital Converter” and filed Apr. 24, 2008 by Chmelar et al. The aforementioned application is incorporated herein by reference for all purposes. Such a dynamic analog to digital converter employs one or more comparators that compare an input against a reference voltage. The output of the dynamic analog to digital converter may then be used to select an input range for comparison during a subsequent bit period.

As described in U.S. patent application Ser. No. 12/134,488 entitled “Systems and Methods for Analog to Digital Conversion” and filed on a date even herewith by Chmelar et al., an analog to digital converter may be unified with a modified Decision Feedback Equalization (DFE) circuit to yield an advantage in predicting a future range for a dynamic analog to digital converter. The aforementioned application is incorporated herein by reference for all purposes. In particular, the incorporated DFE may reduce or eliminate inter-symbol interference that occurs in relation to processing a serial bit sequence in a channel.FIG. 2aandFIG. 2bdepict two examples of analog to digital converters that are incorporated with a modified DFE. In such cases, the analog to digital converters use some level of pipelining implemented using a multiplexer tree and intervening registers.

Turning toFIG. 2a, a unified analog to digital converter200using a DFE for range selection is depicted. Analog to digital converter200utilizes a multiplexer tree similar to that disclosed in U.S. patent application Ser. No. 12/134,523 and filed on a date even herewith by Gribok et al. The aforementioned application is assigned to an entity common hereto, and is incorporated herein by reference for all purposes. Analog to digital converter200includes a bank of eight comparators210that each compare an analog input220against respective reference voltages (not shown). In particular, a distinct reference voltage is provided to each of comparators210with the reference voltages extending across the input range of analog to digital converter200. In some cases, the respective reference voltages are programmable such that the input range of analog to digital converter200can be adjusted. Each of comparators210is clocked by a respective gated clock that is generated by a bank of AND gates230. Each of AND gates230logically ANDs a clock input224with a combination of an enable bit282and an enable bit292. In particular, one quarter of comparators210(i.e., comparators a, e) are clocked whenever enable bit282and enable bit292are both asserted low, and a clock input224is asserted high. One quarter of comparators210(i.e., comparators d, h) are clocked whenever enable bit282and enable bit292are both asserted high, and clock input224is asserted high. One quarter of comparators210(i.e., comparators b,f) are clocked whenever enable bit282is asserted low, enable bit292is asserted high, and clock input224is asserted high. One quarter of comparators210(i.e., comparators c, g) are clocked whenever enable bit282is asserted high, enable bit292is asserted low, and clock input224is asserted high. In this way, power is only being dissipated by one quarter of comparators210during any given bit period. As more fully discussed in the above mentioned reference that is incorporated herein by reference for all purposes, more enable bits may be generated by saving additional history information which can result in enabling a smaller percentage of comparators210, or fewer enable bits may be generated in which case a larger percentage of comparators210may be clocked on any given clock cycle.

An output bit284is equivalent to the output of one of comparators210asserted one bit period prior, enable bit282is equivalent to the output of one of comparators210asserted two bit periods prior, and output bit292is equivalent to the output of one of comparators210asserted three bit periods prior, with all three being based on previous bit assertions as selected by a synchronized multiplexer tree comprising a first tier of multiplexers240, a first tier of flip-flops250, a second tier of multiplexers260, and a third tier multiplexer270. Enable bit282is stored in a flip-flop280, and output bit292is stored in a flip-flop290. Enable bits282,292are provided to AND gates230to enable clocking of a selected subset of comparators210. Further, enable bit292drives the selector input of the multiplexers in first tier multiplexers240and second tier multiplexers260. Enable bit282drives the selector input of third tier multiplexer280.

Turning toFIG. 2b, another analog to digital converter201using a multiplexer tree211implemented in synchronized combinatorial logic is depicted. Analog to digital converter201includes a number of comparators215that each compare an analog input291against respective reference voltages (not shown) that span the input range of analog to digital comparator201. In particular, a distinct reference voltage is provided to each of comparators215with the reference voltages extending across the input range of analog to digital converter201. In some cases, the respective reference voltages are programmable such that the input range of analog to digital converter201can be adjusted. An output bit285of one of comparators215is selected using multiplexer tree211. Output bit285is selected based on prior determined outputs such that inter symbol interference is reduced. In particular, output bit285is provided to a flip-flop295. A single enable bit297provided from flip-flop295is used as a selector input for the different tiers of multiplexer tree211. The outputs of each tier of multiplexer tree211are synchronized to clock signal225using flip-flops. In this way, enable bit297from flip-flop295receives three successive values of output bit285(i.e., the value of output bit285from three successive bit periods). The three successive values of output bit285are used to move a respective comparator output from one of comparators215through multiplexer tree211until the output is provided as output bit285.

Even with extremely fast comparators, the analog to digital converters discussed in relation toFIG. 2aandFIG. 2boffer a maximum data rate of approximately:
tcq+tmux+tsu<T,
where T is the period of the clock used to synchronize the analog to digital converter, tcqis the time required to stabilize a newly clocked flip-flop output, and tsuis a setup time for an intervening flip-flop. The maximum data rate is limited regardless of the levels of interleaving, pipelining depth, or speculation bits utilized. This is because flip-flops are used to transfer data between clock periods. Such flip-flops can be very slow circuit elements. For example, in some technologies, the combination of tcqand tsumay be 180 ps. Where a data rate of six giga bits per second is desired, the combination of tcqand tsuexceeds the clock period (T) making the above described circuits unable to achieve the desired result.

Turning toFIG. 3a, a latch based analog to digital converter300is depicted in accordance with some embodiments of the present invention. Latch based analog to digital converter300incorporates a one tap DFE with one bit of speculation and two levels of interleave. In particular, latch based analog to digital converter300includes two sub-level interleaves310,320. Sub-level interleave310includes two comparators312,314that each receive a respective reference voltage302,304that are compared against an analog input330. Comparators312,314are both synchronized to a clock phase c1. The output of either comparator312or comparator314is selected using a multiplexer340based on an output A2from sub-level interleave320. In particular, output A2is transferred to the select input of multiplexer340using a latch316that is synchronized to clock phase c1. An output A1is provided from multiplexer340.

Sub-level interleave320includes two comparators322,324that each receive a respective reference voltage302,304that are compared against analog input330. Comparators322,324are both synchronized to a clock phase c2. The output of either comparator322or comparator324is selected using a multiplexer350based on output A1from sub-level interleave310. In particular, output A1is transferred to the select input of multiplexer350using a latch326that is synchronized to a clock phase c2. Output A2is provided from multiplexer340.

Reference voltages302,304may be provided from respective one of digital to analog converters362,364. Digital to analog converters362,364may receive digital inputs from some programmable device (not shown) that allow for modification of reference voltages302,304. In other cases, reference voltages302,304may be provided from a resistor chain. Based on the disclosure provided herein, one of ordinary skill in the art will recognize other approaches for generating reference voltages.

Turning toFIG. 3b, a timing diagram301depicts an exemplary operation of the latch based analog to digital converter300. Clock phase c1and clock phase c2are generated based on a master clock311and are one-hundred, eighty degrees out of phase from one another. Each of latch316and latch326are transparent when its associated clock is asserted high. Thus, when clock phase c2asserts high at a time321, latch316becomes transparent. On the same clock edge, comparators322,324are clocked. The outputs of comparators322,324are stable after a period, tcomp323. The output of the selected comparator transitions through multiplexer350after a period, tmux325. At this point, output A2is stable. A2is provided to latch326which becomes transparent once clock phase c1asserts high at a time331. A2is available as the select input of multiplexer340after a period, tlatch337, and the outputs of comparators312,314are stable after a period, tcomp333. Where tlatch337plus the time when A2is available is less than tcomp333, tlatch337does not play an integral part in the critical timing path of latch based analog to digital converter300. It should be noted that latch based analog to digital converter300still operates correctly even where A2becomes available substantially after the rising edge of clock phase c1because to the operational characteristics of latch316. In particular, where A2becomes available before the end of period tcomp333, the delay on output A2does not have an impact on the critical timing path. Thus, use of latches316,326in place of a flip-flop yields an increase in throughput. In particular, in a two interleave design such as that depicted inFIG. 3a, the data from one interleave (i.e., A1or A2) launched from the rising edge of one clock phase (i.e., c1or c2) must be latched by a latch (i.e., latch316or latch326) before the falling edge of the other clock phase. This yields a time period 2T341for operation in comparison to a 1T period for a comparable flip-flop based design. In particular, the worse case timing path of latch based analog to digital converter300is defined by the following equation:
tcomp+tmux+tlatch<2T.
Thus, as an example, where tcompis 120 ps, tmuxis 60 ps and tlatchis 60 ps, an 8.3 GHz data rate can be supported. The output of the selected comparator transitions through multiplexer340after a period, tmux335. At this point, output A1is stable. The above mentioned process is repeated where A1is used to select the output from multiplexer350.

Latch based analog to digital converter300operates as an asynchronous circuit due to the transparent operation of latches316,326. However, latch based analog to digital converter300does not include any asynchronous loops and is capable of achieving a higher throughput rate than a corresponding circuit relying on flip-flops in place of latches316,326. Further, the data rate can be increased by increasing the number of interleaves.

Turning toFIG. 4a, another latch based analog to digital converter400including an increased level of interleaving in accordance with various embodiments of the present invention. In particular, latch based analog to digital converter400incorporates a one tap DFE with one bit of speculation and four levels of interleave. Latch based analog to digital converter400includes four sub-level interleaves410,420,430,440. Sub-level interleave410includes two comparators412,414that each receive a respective reference voltage402,404that are compared against an analog input490. Comparators412,414are both synchronized to a clock phase c1. The output of either comparator412or comparator414is selected using a multiplexer470based on an output A4from sub-level interleave440. In particular, output A4is transferred to the select input of multiplexer470using a latch416that is synchronized to clock phase c1. An output A1is provided from multiplexer470.

Sub-level interleave420includes two comparators422,424that each receive a respective reference voltage402,404that are compared against analog input490. Comparators422,424are both synchronized to a clock phase c2. The output of either comparator422or comparator424is selected using a multiplexer475based on output A1from sub-level interleave410. In particular, output A1is transferred to the select input of multiplexer475using a latch426that is synchronized to a clock phase c2. Output A2is provided from multiplexer475.

Sub-level interleave430includes two comparators432,434that each receive a respective reference voltage402,404that are compared against analog input490. Comparators432,434are both synchronized to a clock phase c3. The output of either comparator432or comparator434is selected using a multiplexer480based on output A2from sub-level interleave420. In particular, output A2is transferred to the select input of multiplexer480using a latch436that is synchronized to a clock phase c3. Output A3is provided from multiplexer480.

Sub-level interleave440includes two comparators442,444that each receive a respective reference voltage402,404that are compared against analog input490. Comparators442,444are both synchronized to a clock phase c4. The output of either comparator442or comparator444is selected using a multiplexer485based on output A3from sub-level interleave430. In particular, output A3is transferred to the select input of multiplexer485using a latch446that is synchronized to a clock phase c4. Output A4is provided from multiplexer485.

Reference voltages402,404may be provided from respective one of digital to analog converters462,464. Digital to analog converters462,464may receive digital inputs from some programmable device (not shown) that allow for modification of reference voltages402,404. In other cases, reference voltages402,404may be provided from a resistor chain. Based on the disclosure provided herein, one of ordinary skill in the art will recognize other approaches for generating reference voltages.

Turning toFIG. 4b, a timing diagram401depicts an exemplary operation of the latch based analog to digital converter400. Clock phase c1, clock phase c2, clock phase c3, and clock phase c4are generated based on a master clock411and are ninety degrees out of phase from one another. Each of latch416, latch426, latch436and latch446are transparent when its associated clock is asserted high. Thus, when clock phase c4asserts high at a time421, latch446becomes transparent. On the same clock edge, comparators442,444are clocked. The outputs of comparators442,444are stable after a period, tcomp423. The output of the selected comparator transitions through multiplexer485after a period, tmux425. At this point, output A4is stable. A4is provided to latch416which becomes transparent once clock phase c1asserts high at a time431. A4is available as the select input of multiplexer470after a period, tlatch437, and the outputs of comparators412,414are stable after a period, tcomp433. Where tlatch437plus the time when A4is available is less than tcomp433, tlatch437does not play an integral part in the critical timing path of latch based analog to digital converter400. It should be noted that latch based analog to digital converter400still operates correctly even where A4becomes available substantially after the rising edge of clock phase c1because to the operational characteristics of latch416. In particular, where A4becomes available before the end of period tcomp433, the delay on output A4does not have an impact on the critical timing path. Thus, use of latches416,426in place of a flip-flop yields an increase in throughput. In particular, in a four interleave design such as that depicted inFIG. 4a, the data from one interleave (i.e., A1, A2, A3or A4) launched from the rising edge of one clock phase (i.e., c1, c2, c3or c4) must be latched by a latch (i.e., one of latches416,426,436,446) before the falling edge of the clock phase associated with latching the particular output. This yields a time period 4T441for operation. The worse case timing path of latch based analog to digital converter300is defined by the following equation:
tcomp+tmux+tlatch<3T.
Thus, as an example, where tcompis 120 ps, tmuxis 60 ps and tlatchis 60 ps, a 12.5 GHz data rate can be supported. The output of the selected comparator transitions through multiplexer470after a period, tmux435. At this point, output A1is stable. The above mentioned process is repeated where A1is used to select the output from multiplexer475, A2is used to select the output from multiplexer480, and A3is used to select the output from multiplexer485.

Turning toFIG. 5a, yet another latch based analog to digital converter500including a further increased level of interleaving in accordance with various embodiments of the present invention. In particular, latch based analog to digital converter500incorporates a one tap DFE with one bit of speculation and eight levels of interleave. Latch based analog to digital converter500includes eight sub-level interleaves510,520,530,540,550,560,570,580. Sub-level interleave510includes two comparators512,514that each receive a respective reference voltage502,504that are compared against an analog input590. Comparators512,514are both synchronized to a clock phase c1. The output of either comparator512or comparator514is selected using a multiplexer418based on an output A8from sub-level interleave580. In particular, output A8is transferred to the select input of multiplexer518using a latch516that is synchronized to clock phase c1. An output A1is provided from multiplexer518.

Sub-level interleave520includes two comparators522,524that each receive a respective reference voltage502,504that are compared against analog input590. Comparators522,524are both synchronized to a clock phase c2. The output of either comparator522or comparator524is selected using a multiplexer528based on output A1from sub-level interleave510. In particular, output A1is transferred to the select input of multiplexer528using a latch526that is synchronized to a clock phase c2. Output A2is provided from multiplexer528.

Sub-level interleave530includes two comparators532,534that each receive a respective reference voltage502,504that are compared against analog input590. Comparators532,534are both synchronized to a clock phase c3. The output of either comparator532or comparator534is selected using a multiplexer538based on output A2from sub-level interleave520. In particular, output A2is transferred to the select input of multiplexer538using a latch536that is synchronized to a clock phase c3. Output A3is provided from multiplexer538.

Sub-level interleave540includes two comparators542,544that each receive a respective reference voltage502,504that are compared against analog input590. Comparators542,544are both synchronized to a clock phase c4. The output of either comparator542or comparator544is selected using a multiplexer548based on output A3from sub-level interleave530. In particular, output A3is transferred to the select input of multiplexer548using a latch546that is synchronized to a clock phase c4. Output A4is provided from multiplexer548.

Sub-level interleave550includes two comparators552,554that each receive a respective reference voltage502,504that are compared against analog input590. Comparators552,554are both synchronized to a clock phase c4. The output of either comparator552or comparator554is selected using a multiplexer558based on output A4from sub-level interleave540. In particular, output A4is transferred to the select input of multiplexer558using a latch556that is synchronized to a clock phase c5. Output A5is provided from multiplexer558.

Sub-level interleave560includes two comparators562,564that each receive a respective reference voltage502,504that are compared against analog input590. Comparators562,564are both synchronized to a clock phase c6. The output of either comparator562or comparator564is selected using a multiplexer568based on output A5from sub-level interleave550. In particular, output A5is transferred to the select input of multiplexer568using a latch566that is synchronized to a clock phase c6. Output A6is provided from multiplexer568.

Sub-level interleave570includes two comparators572,574that each receive a respective reference voltage502,504that are compared against analog input590. Comparators572,574are both synchronized to a clock phase c4. The output of either comparator572or comparator574is selected using a multiplexer578based on output A6from sub-level interleave560. In particular, output A6is transferred to the select input of multiplexer578using a latch576that is synchronized to a clock phase c7. Output A7is provided from multiplexer578.

Sub-level interleave580includes two comparators582,584that each receive a respective reference voltage502,504that are compared against analog input590. Comparators582,584are both synchronized to a clock phase c8. The output of either comparator582or comparator584is selected using a multiplexer588based on output A7from sub-level interleave570. In particular, output A7is transferred to the select input of multiplexer588using a latch586that is synchronized to a clock phase c8. Output A8is provided from multiplexer588.

Reference voltages502,504may be provided from respective one of digital to analog converters506,508. Digital to analog converters506,508may receive digital inputs from some programmable device (not shown) that allow for modification of reference voltages502,504. In other cases, reference voltages502,504may be provided from a resistor chain. Based on the disclosure provided herein, one of ordinary skill in the art will recognize other approaches for generating reference voltages.

Turning toFIG. 5b, a timing diagram501depicts an exemplary operation of the latch based analog to digital converter500. Clock phases c1, c2, c3, c4, c5, c6, c7and c8are generated based on a master clock511and are forty-five degrees out of phase from one another. Each of latch516, latch526, latch536, latch546, latch556, latch566, latch576and latch586are transparent when its associated clock is asserted high. Thus, when clock phase c8asserts high at a time521, latch586becomes transparent. On the same clock edge, comparators582,584are clocked. The outputs of comparators582,584are stable after a period, tcomp523. The output of the selected comparator transitions through multiplexer588after a period, tmux525. At this point, output A8is stable. A8is provided to latch516which becomes transparent once clock phase c1asserts high at a time531. A8is available as the select input of multiplexer518after a period, tlatch537, and the outputs of comparators512,514are stable after a period, tcomp533. Where tlatch537plus the time when A8is available is less than tcomp533, tlatch537does not play an integral part in the critical timing path of latch based analog to digital converter500. It should be noted that latch based analog to digital converter500still operates correctly even where A8becomes available substantially after the rising edge of clock phase c1because to the operational characteristics of latch516. In particular, where A8becomes available before the end of period tcomp533, the delay on output A8does not have an impact on the critical timing path. Thus, use of latches516,526in place of a flip-flop yields an increase in throughput. In particular, in a four interleave design such as that depicted inFIG. 5a, the data from one interleave (i.e., A1, A2, A3, A4, A5, A6, A7or A8) launched from the rising edge of one clock phase (i.e., c1, c2, c3, c4, c5, c6, c7or c8) must be latched by a latch (i.e., one of latches516,526,536,546,556,566,576,586) before the falling edge of the clock phase associated with latching the particular output. This yields a time period 5T541for operation. The worse case timing path of latch based analog to digital converter300is defined by the following equation:
tcomp+tmux+tlatch<5T.
Thus, as an example, where tcompis 120 ps, tmuxis 60 ps and tlatchis 60 ps, a 21 GHz data rate can be supported. The output of the selected comparator transitions through multiplexer518after a period, tmux535. At this point, output A1is stable. The above mentioned process is repeated where A1is used to select the output from multiplexer528, A2is used to select the output from multiplexer538, A3is used to select the output from multiplexer548, A4is used to select the output from multiplexer558, A5is used to select the output from multiplexer568, A6is used to select the output from multiplexer578, and A7is used to select the output from multiplexer588.

Further, it should be noted that while the latch based analog to digital converters ofFIGS. 3a,4aand5aabove utilize a single tap, that more than one tap may be utilized depending upon the level of inter symbol interference that is to be mitigated by the particular circuit. Turning toFIG. 6a, a latch based analog to digital converter600including two taps with two bits of speculation and two interleaves is depicted. In particular, latch based analog to digital converter600includes two sub-level interleaves610,630. Sub-level interleave610includes four comparators622,624,626,628that each receive a respective reference voltage602,604,606,608that are compared against an analog input690. The number of taps (tp) is directly related to the number of comparators utilized in accordance with the following equation:
Number of Comparators=2tp.
Comparators622,624,626,628are all synchronized to a clock phase c1. The output of one of comparators622,624,626,628is selected using a multiplexer tree consisting of a first tier multiplexer612and a second tier multiplexer614based on a combination of an output A2from sub-level interleave630and an output A1from second tier multiplexer614. In particular, output A2is transferred to the select input of second tier multiplexer614using a latch618, and output A1is transferred to the select input of first tier multiplexer612using a latch616. Latch616is synchronized to clock phase c2, and latch618is synchronized to clock phase c1. An output A1is provided from second tier multiplexer614.

Sub-level interleave630includes four comparators642,644,646,648that each receive a respective reference voltage602,604,606,608that are compared against an analog input690. Comparators642,644,646,648are all synchronized to a clock phase c2. The output of one of comparators642,644,646,648is selected using a multiplexer tree consisting of a first tier multiplexer632and a second tier multiplexer634based on a combination of an output A1from sub-level interleave610and an output A2from second tier multiplexer634. In particular, output A1is transferred to the select input of second tier multiplexer634using a latch638, and output A2is transferred to the select input of first tier multiplexer632using a latch636. Latch636is synchronized to clock phase c1, and latch638is synchronized to clock phase c2. An output A2is provided from second tier multiplexer634.

Reference voltages602,604,606,608may be provided from respective one of digital to analog converters652,654,656,658. Digital to analog converters652,654,656,658may receive digital inputs from some programmable device (not shown) that allow for modification of reference voltages602,604,606,608. In other cases, reference voltages602,604,606,608may be provided from a resistor chain. Based on the disclosure provided herein, one of ordinary skill in the art will recognize other approaches for generating reference voltages.

Turning toFIG. 6b, a timing diagram601depicts an exemplary operation of the latch based analog to digital converter600. Clock phase c1and clock phase c2are generated based on a master clock611and are one-hundred, eighty degrees out of phase from one another. Each of latches616,618,636,638are transparent when its associated clock is asserted high. Thus, when clock phase c2asserts high at a time621, latch616and latch638become transparent. On the same clock edge, comparators642,644,646,648are clocked. The outputs of comparators642,644,646,648are stable after a period, tcomp623. The output of the selected comparator transitions through the multiplexer tree after two multiplexer delays, tmux625and tmux626, corresponding to the delay through first tier multiplexer632and second tier multiplexer634. At this point, output A2is stable.

A2is provided to latch636and latch618which both become transparent once clock phase c1asserts high at a time631. A2is available as the select input of second tier multiplexer614after a period, tlatch637, and the outputs of comparators622,624,626,628are stable after a period, tcomp633. Where tlatch637plus the time when A2is available is less than tcomp633, tlatch637does not play an integral part in the critical timing path of latch based analog to digital converter600. It should be noted that latch based analog to digital converter600still operates correctly even where A2becomes available substantially after the rising edge of clock phase c1because to the operational characteristics of latch618and because the output of latch618drives the select input of second tier multiplexer614. In particular, where A2becomes available before the end of period tcomp633and tmux635, the delay on output A2does not have an impact on the critical timing path. Thus, use of latches616,618,636,638in place of a flip-flop yields an increase in throughput. In particular, in a two interleave design such as that depicted inFIG. 6a, the data from one interleave (i.e., A1or A2) launched from the rising edge of one clock phase (i.e., c1or c2) must be latched by a latch (i.e., latch316or latch326) before the falling edge of the other clock phase. In particular, the worse case timing path of latch based analog to digital converter600is defined by the following equation:
tcomp+(2)tmux+tlatch<2T.
Thus, as an example, where tcomp is 120 ps, tmux is 60 ps and tlatch is 60 ps, a 6.7 GHz data rate can be supported. The output of the selected comparator transitions through the multiplexer tree after a period, tmux635+tmux636. At this point, output A1is stable. The above mentioned process is repeated where A1is used to select the output from second tier multiplexer614.

Based on the disclosure provided herein, one of ordinary skill in the art will recognize that the architecture utilized in the above described analog to digital converters may be expanded to any number of interleaves to yield additional timing advantages. In general, with a defined number of taps (tp) using speculation on all tp history bits, and a defined number of interleaves (i), the following equation describes the critical timing path:
tcomp+(tp)tmux+tlatch<(i/2+1)/T.
In general, a DFE incorporated into an analog to digital converter consistent with that described in relation toFIGS. 3a,4a,5aand6aabove is described by the number of taps (i.e., tp) which corresponds to the amount of inter symbol interference that is mitigated. I large number of taps is able to detect a bit sequence transmitted through a poor channel with a significant amount of inter symbol interference. The above mentioned latch based analog to digital converters can operate at a very high data rate without expending excessive power. Where a large number of interleaves are used, it may be necessary to include a fanout buffer as is known in the art. Accounting for this fanout buffer, a generalized timing constraint for a latch based analog to digital converter in accordance with some embodiments of the present invention is described by the following equation:

T=tcomp+tlatch+(tp)⁢tmax+log4⁡(3*2tp4)⁢tbuf(i/2)+1,
where tcompis the delay through a comparator, tlatchis the delay through a latch, tbufis a delay through a fanout buffer, tp is the number of taps, i is the number of interleaves, 2tp is the number multiplexers, 3*2tpis the number of gates, and

log4⁡(3*2tp4)
is the number of fanout buffers. The power consumed by such a latch based analog to digital converter is described by:

P=2tp*edac+i*2tp*ecomp+i*tp*elatch+i*2tp*emax+i*∑k=0log4⁡(3*2⁢tp4)-1⁢2k*ebufi*T,
where edacis the energy of the digital to analog converter, ecompis the energy of the comparator, elatchis the energy of the latch, emuxis the energy of the multiplexer, ebufis the energy of the buffer, tp is the number of taps, i is the number of interleaves, 2tpis the number of digital to analog converters, i*tp is the number of latches, and the summation is the number of fanout buffers, each of which is exponentially larger than the previous.

Turning toFIG. 7, a communication system700including a receiver720with a latch based analog to digital converter is shown in accordance with some embodiments of the present invention. Communication system700includes a transmitter710that transmits a signal representing a data set to receiver720via a transfer medium730. Transfer medium730may be, but is not limited to, a wireless transfer medium, a electrically wired transfer medium, a magnetic storage medium, or an optical transfer medium. Based on the disclosure provided herein, one of ordinary skill in the art will recognize a variety of transfer media that may be used in relation to different embodiments of the present invention. Receiver720includes a latch based analog to digital converter similar to that described above in relation toFIGS. 3-6above. In some cases, communication system700may be a cellular telephone system with transmitter710and receiver720being cell phones and/or cell towers. Alternatively, communication system700may be a magnetic storage medium with transmitter710being a write function, transfer medium730being a magnetic storage medium, and receiver720being a read function. Based on the disclosure provided herein, one of ordinary skill in the art will recognize a variety of other systems that may be represented as communication system700in accordance with different embodiments of the present invention.

In conclusion, the invention provides novel systems, devices, methods and arrangements for analog to digital conversion. While detailed descriptions of one or more embodiments of the invention have been given above, various alternatives, modifications, and equivalents will be apparent to those skilled in the art without varying from the spirit of the invention. For example, while different embodiments of the present invention have been depicted with a particular number of taps and/or levels of interleaving, it will be understood that an arbitrary number of taps and/or interleaves may be supported in accordance with different embodiments of the present invention. Therefore, the above description should not be taken as limiting the scope of the invention, which is defined by the appended claims.