Envelope tracking active circulator

Several embodiments of an envelope tracking active circulator is disclosed with a method to cascade them. In an active transistor based circulator (active circulator), gate (base) and drain (collector) bias voltage can be adjusted by RF or microwave input envelop signal. This is called envelop tracking active circulator. In this concept, input RF signal is detected by detection circuit, such as detection diode or coupler and converted into low frequency envelop signal by the proper filtering circuitry. The generated envelop signal controls the supply voltage of the drain and gate with the proper function of the envelop signal to improve active circulator insertion loss, isolation and power handling capability. This concept can be applied to any type of solid-state FET (Field effect transistor) transistor based active circulator, as long as they have bias dependent trans-conductance and capacitances inside. For a BJT (bipolar junction transistor) based active circulator, base bias current supply modulator will be used instead of voltage supply modulator.

INCORPORATED BY REFERENCE

This non-provisional application incorporates by reference the contents of U.S. Ser. No. 14/554,995 filed on Nov. 26, 2014.

TECHNICAL FIELD

The present disclosure is directed in general to the field of circulators and in particular to active circulators.

BACKGROUND OF THE DISCLOSURE

A circulator is a device with three or more ports where a microwave or RF signal is transferred from one port to the next in a prescribed order. A variety of circulators are known. However, some of these include active circulators. Typical active circulator consists of active transistors and each source (or emitter) of the transistors are tied together (common node).

Prior arts suffer from DC power loss leading to less efficiency, significant insertion loss and port isolation issues.FIG. 1shows a prior art three port active circulator. The port numbers are labeled and as can be seen, the direction of transfer is clockwise. In this prior art circulator, the drain bias voltages (Vdd) are directly connected to three drain resistors and the drain currents flow thought these drain resistors. The common node, where the sources of the transistors are tied together, is grounded to Vssthrough common a ground resistor. There are significant voltage drops through these various resistors causing DC power consumption to occur making these circulators less energy efficient. If these drain resistors and common source resistors are not of high enough value, there can be significant RF power loss as well. The voltage drops across these resistors also limit the maximum RF voltage swing across each transistor, thus limiting the power handling capacity of these circulators.

Also inFIG. 1, there are three other resistors bypassed with the capacitors in parallel (R1-C1, R2-C2, R3-C3)) which form RF feedback networks. These RF feedback networks are typically used in an active circulator in order to adjust transconductance of the transistors. The active circulator operation is very sensitive to RF transconductance and it affects circulator loss and isolation parameters and the resulting performance.

An improved active circulator is disclosed in application Ser. No. 14/554,995 as shown inFIG. 2. In order to improve the power efficiency, and increase the power handling capacity of the circulator, drain resistors are eliminated inFIG. 2. In order to make a circulator operational, its common source node has to be connected to the ground through the resistor (Rc) or resistor and inductor in parallel (Rcand Lcin parallel) as shown inFIG. 2. Under the small signal operation, the common node voltage is almost a constant, since common node current flowing doesn't change that much. But, once a large signal is applied, common node current keep increasing over the power level and corresponding common node voltage keeps rising (DC or AC). In an active circulator, the control of various biases is critical. In this case, each transistor gate bias has to be set around unit current gain point to make closed loop circulator stable. Once this low gate bias point moves off from the original point by the power increase (common node voltage change), the active circulator will lose the circulation and isolation. Typically, large signal power increases the common node voltage and effective gate-source voltage (Vgs) of each transistor becomes lower than the original setting. Effective drain to source voltage (Vds) will also experience the same by the large signal. These changes in Vgsand Vdsworsen the circulator loss and isolation parameters, affecting the circulator performance.

Circulators have numerous uses. For example, one port of a three port circulator may be connected to an antenna, while a receiver is connected to a second port of the circulator to receive signals received by the antenna and with a transmitter connected to a third port of the circulator to supply transmit signals to the antenna (with the transmit signals being isolated by the circulator from the receiver which might otherwise be damaged by the transmit signals).

SUMMARY OF THE DISCLOSURE

To address one or more of the above-deficiencies of the prior art, one embodiment described in this disclosure provides for a bias controlled active circulator comprising, a plurality of transistors configured as an active circulator having three or more ports and having one or more common gate biases and one or more common drain biases; and one or more envelope bias controllers that generate the one or more common gate biases and the one or more common drain biases, wherein each of the common gate biases and each of the common drain biases is modulated by a power envelope of a signal input to one of the ports of the circulator.

Another embodiment described in this disclosure provides for a bias controlled active circulator comprising, a plurality of transistors configured as an active circulator having three or more ports and having one or more common gate biases or one or more common drain biases, and one or more envelope bias controllers that generate the one or more common gate biases or the one or more common drain biases, wherein each of the common gate biases or each of the common drain biases is modulated by a power envelope of a signal input to one of the ports of the circulator.

Another embodiment described in this disclosure provides for a bias controlled active circulator comprising, a plurality of bipolar junction transistors (BJTs) configured as an active circulator having three or more ports and one or more common base nodes, and one or more envelope base controllers that control base current supply to the one or more common base nodes, wherein the base current supply to each of the common base nodes is modulated by a power envelope of a signal input to one of the ports of the circulator.

A cascaded bias controlled active circulators is disclosed, comprising a plurality of active circulators, wherein each of the circulators plurality of ports and having a port connected to a port of another circulator forming a chain; each of the circulators having a plurality of transistors configured as an active circulator and the transistors in the plurality of active circulators forming groups where each group has a common gate bias and a common drain bias and one or more envelope bias controllers that generate the one or more common gate biases and the one or more drain common biases, wherein each of the common gate biases and each of the common drain biases are modulated by a power envelope of a signal input to one of the ports of the circulator.

Yet another embodiment described in this disclosure provides for a bias controlled multi port active circulator comprising, a plurality of FET transistors forming a plurality of ports, a plurality of first RF chokes and a plurality of second RF chokes, where each of FET transistor of said plurality having a gate connected to an associated port of said multi-port active circulator via a capacitor of an associated one of said first RF chokes, each of said first RF chokes being connected through a first inductor to a common gate bias; a source connected to a common point that is connected to a first resistor in parallel with a second inductor wherein both the first resistor and the second inductor are grounded and a drain connected to the gate of the same FET transistor by a feedback circuit and connected to the gate of a neighboring FET transistor via a capacitor of one of the second RF chokes, each of the second RF chokes coupling bases and drains of neighboring FET transistors via the capacitors thereof and each of the second RF chokes being connected to a common drain bias and one or more envelope bias controllers that supply the common gate bias and the common drain bias, wherein the common gate bias and the common drain bias are modulated by a power envelope of a signal input to one of the ports of the circulator.

Certain embodiments may provide various technical features depending on the implementation. For example, a technical feature of some embodiments may include the capability to provide low loss and high isolation. Other embodiments may provide for increased power handling capability. Some embodiments may provide for increased power efficiency.

Although specific features have been enumerated above, various embodiments may include some, none, or all of the enumerated features. Additionally, other technical features may become readily apparent to one of ordinary skill in the art after review of the following figures and description.

DETAILED DESCRIPTION

It should be understood at the outset that, although example embodiments are illustrated below, the present technology may be implemented using any number of techniques, whether currently known or not. The present technology should in no way be limited to the example implementations, drawings, and techniques illustrated below. Additionally, the drawings are not necessarily drawn to scale.

In order to overcome the deficiencies of the prior art and to increase the efficiency and the power handling capacity of active circulators while lowering the insertion loss and improving the port-to-port isolation, an envelope tracking isolator concept is proposed according to an embodiment of the present disclosure. In an active transistor based circulator (active circulator), gate (or base) and drain (or collector) bias voltage can be adjusted by RF input envelope signal. This is called envelope tracking active circulator. In this concept, input RF signal is detected by a detection circuit, such as a detection diode or a coupler and converted into low frequency envelope signal by the proper filtering circuitry. The generated envelope signal controls the supply voltage of the drain and gate with the proper function of the envelope signal to improve active circulator insertion loss, isolation and power handling capability. This concept can be applied to any type of solid-state FET (Field effect transistor) based active circulator, as long as they have bias dependent trans-conductance and capacitances inside the circulator. For a BJT (bipolar junction transistor) based active circulator, base bias current supply modulator will be used instead of voltage supply modulator to achieve this goal.

In active circulators, it is very important to hold proper Vgsand Vdsregardless of the power level to maintain the reasonable insertion loss and isolation. This proper bias over the power sweeping can be realized by applying the adjustable voltage source (Vgsand Vds) and the proposed concept of envelope tracking can be adopted to accomplish this goal.

System300inFIG. 3illustrates the concept of envelope tracking in active circulators, according to an embodiment of the present disclosure. The system comprises of each circulator port (port1, port2and port3) connected to one or more transistors (301,302and303respectively) and one or more envelope bias controllers305. ThoughFIG. 3illustrates Field Effect Transistors (FETs), any other type of transistors can be used such as bipolar Junction Transistors (BJT) as long as they are configured to provide similar functions. The envelope bias controller305comprises of a signal detector subsystem330, filtering subsystem320and a voltage supply modulator310. The gates of the transistors301,302and303are connected to a common node312and controlled by gate voltage Vgs312afrom the voltage supply modulator310inside the envelope bias controller305. Similarly, the Drains of these transistors are also connected to a common node311and controlled by drain voltage Vds311asupplied by the voltage supply modulator310. One or more of each port input power331is detected by a signal detector subsystem330. This detected signal can be properly transformed into low frequency envelope signal. The detection subsystem330can be of any type of detection circuit, such as reverse schottky diode, resistor sensing or direct power coupling. Envelope signal transformation from the detected signal can be done by using proper filtering circuit subsystem320. The most commonly used filtering subsystem320is a low pass filtering system, but other harmonic filtering can also be used depending on the system requirement. The filtered signal from the subsystem320is then sent to a voltage supply modulator subsystem310. The voltage supply modulator310will be controlled by the envelope signal information from the filtering subsystem320and is used to shape the proper voltage magnitude for the gate and drain bias over the input power level. When the voltage source modulator310modulates the bias voltages Vgsand Vds, it has to take proper modulation function of the envelope signal and has to be fast enough to follow the envelope signal frequency. Since the timing delay occurs through the detector330, filtering (320) and voltage modulator (310) subsystems, timing synchronizing technique has to be applied to synchronize the phases of the input signal331and modulated voltages311aand312aat the output of the envelope bias controller305.

For a BJT (bipolar junction transistor) based active circulator, base bias current supply modulator will be used instead of voltage supply modulator to achieve this goal. The envelope bias controller305will supply a modulated base bias current tracking the input power envelope. In the description that follows, it is implied that FET terminologies can be replaced by equivalent BJT terminologies and the envelope bias controller modulating the base current based on the input power envelope instead of the gate and drain bias voltages.

If the power of each port is not the same, such as transceiver with antenna for radar application, the highest power (i.e. Tx port) will be detected and supply modulator will be controlled by this envelope information. Typically, all the Vgs's are controlled by the same modulated voltage and all the Vds's are controlled by the same modulated voltage, each modulated by the envelope signal. But, if each transistor doesn't need to keep the same bias condition to improve any particular port's insertion loss compromising isolation or vice versa, each gate and drain can be controlled by separate envelope bias controller305with different voltage amplitudes.

To validate the envelope tracking active circulator concept, CMOS based active circulator design was designed and simulated using ADS (Advanced Design System). Basic circuit architectures ofFIGS. 2 and 3are modeled and simulation results are compared to analyze the benefit of the current inventive concept. Instead of designing specific envelope detector, filter and modulator, the input power level is read from the simulation setting, and gate and drain voltage (Vgsand Vds) on the simulation takes the function of the input power level, so Vgsand Vdsare emulated like real envelope tracking to have the same effect. Table 1 shows the basic design parameter of the designed active circulator used in the simulation.

The results of the simulation are illustrated inFIGS. 4a, 4band inFIG. 5.FIG. 4ashows the simulation comparison.FIG. 4aillustrates simulation results comparing loss performance characteristics over input power for both a fixed bias circulator and an envelope tracking circulator, according to an embodiment of the present disclosure.FIG. 4billustrates simulation results comparing isolation characteristics over input power for both a fixed bias circulator and an envelope tracking circulator, according to an embodiment of the present disclosure. For this simulation, frequency is swept from 0.1 GHz˜2.1 GHz with −10˜18 dBm sinusoidal input power. Under the fixed bias condition, 1 dB insertion loss compression point (˜3 dB loss) occurs around 4˜9 dBm input power (FIG. 4a). But, the envelope tracking circulator improves the 1 dB compression point by 14 dB, maintaining or improving isolation (FIG. 4b).

FIG. 5illustrates simulation results comparing the generated controlled gate and drain bias voltages over input power, according to an embodiment of the present disclosure. In this simulation, Vdsand Vgsare scaled and modulated by the relation
Vds=Vds0+8(Pin),
VgsVgs0+8(Pin),where Vds0and Vgs0are the initial drain and gate bias points respectively and Pinis the input power level. The results ofFIG. 5illustrate how the gate and drain bias voltages are modulated as a function of input power. The simulation tracks the power envelope dynamically.

As illustrated in system600inFIG. 6, circulators300using this envelope tracking concept can be cascaded. The circulators700and800described later can also be used instead of the circulator300in cascading to add additional ports.FIG. 6illustrates cascading of three circulators300to obtain a five port circulator. The cascading can be continued in a similar fashion to obtain any number of ports. Such cascading of envelope tracking circulators will provide for a large number of ports. The Vgsand Vdscontrols based on the input power envelope can be at the individual port level or at the circulator level or for any group of circulators, based on the needs of the application.

Active circulator700inFIG. 7is another embodiment of this technology. Here the gate and drain biases for the transistors T1, T2and T3are driven by one or more envelope bias controllers705. Though FETs are illustrated inFIG. 7, any other transistors including BJTs can be used as long as they are configured to provide similar functionality and the envelope bias controller modulates the base current based on the input power envelope.

Active circulator700consists of three (or more) transistors (T1, T2and T3) arranged in a ring, with RC feedback and common ground resistors. The gate bias Vgsof the each of the three transistors T1, T2and T3is provided by the envelope bias controller705through one of three choke inductors inside each of three RF chokes717, while the drain bias Vdsof the each of the three transistors T1, T2and T3is provided by the envelope bias controller705through one of three choke inductors inside each of three RF chokes717. The three transistors T1, T2and T3are depicted (according to the symbol used) as being HEMT devices, but the three transistors T1, T2and T3can be implemented as other types of transistors including Bipolar Junction Transistors, CMOS Field Effect Transistors, Laterally Diffused Metal Oxide Semiconductor (LDMOS) Transistors, to name a few. However, if a FET-type transistor (HEMT, LDMOS, CMOS, Etc) is utilized as transistors T1, T2and T3, then the three choke inductors inside each of three RF chokes717can be replaced with high resistance resistors, since FET type devices do not draw a bias current at their gates. And all three resistors would be easier to implement than would be a conventional inductor in717if new active circulator is implemented as monolithic microwave integrated circuit (MMIC). However, if bipolar transistors are used instead of FETs to implement this technology, then replacing the three choke inductors inside717with high resistance resistors would lead to some DC power loss. This will be a tradeoff between ease of implementation and power loss.

Each of the three RF signals for the circulator700are applied at the three ports (RF Port1, RF Port2, RF Port2) and are each introduced through a bypass capacitor in each of the RF chokes717. For a monolithic microwave integrated circuit (MMIC) embodiment, each choke inductor in717connected to Vgscan be replaced with a high resistance resistor (as mentioned above, particularly if FET-type transistors are used as transistors T1, T2and T3) and each bypass capacitor in717can be implemented as a highly capacitive capacitance (the capacitance of which is preferably sufficiently large to pass the signal with as little loss as reasonable, given the fact that impedance of inductor/resistor should be much greater than the impedance of the capacitor at the frequency of the RF signal at Port1, Port2or Port3). Alternatively, choke inductors717can be replaced with shorted λ/4 (quarter wave length) transmission line stub or with an active load. Similarly, choke inductors in717can be replaced with shorted λ/4 (quarter wave length) transmission line stub or with an impedance convertor.

The envelope bias controller705receives the selected RF input731. In the case of a single envelope bias controller705, this RF input731is the RF input of the highest power among the RF inputs to the various ports. If the envelope bias controller705is used for each transistor or for a group of transistors, the selected RF input731to the signal detector is the input RF that has the highest power among the selected group of ports.

The RF input to one of the ports is sent for detection and this detection signal can be properly transformed into low frequency envelope signal. The detection subsystem730can be of any type of detection circuit, such as reverse schottky diode, resistor sensing or direct power coupling. Envelope signal transformation from the detected signal can be done by using proper filtering circuit subsystem720. The most commonly used filtering subsystem720is a low pass filtering system, but other harmonic filtering can also be used depending on the system requirement. The filtered signal from the subsystem720is then sent to a voltage supply modulator subsystem710. The voltage supply modulator710will be controlled by the envelope signal information from the filtering subsystem720and is used to shape the proper voltage magnitude for the gate and drain bias over the input power level. When the voltage source modulator710modulates the bias voltages Vgsand Vds, it has to take proper modulation function of the envelope signal of the input power and has to be fast enough to follow the envelope signal frequency. Since the timing delay occurs through the detector730, filtering (720) and voltage modulator (710) subsystems, timing synchronizing technique has to be applied to synchronize the phases of the input signal731and modulated voltages Vgsand Vdsat the output of the envelope bias controller705.

The RF chokes717are depicted as a simple LC choke. More complex choke designs and even simpler choke designs may be substituted so long as (i) in the case of RF chokes717on the gate side, the gate bias voltage has a DC path to the gate of the particular transistor (T1, T2or T3) to which it applies a bias voltage or (ii) in the case of RF chokes717for the drain side, the bias voltage has a DC path to the drain of the particular transistor (T1, T2or T3) to which it applies a bias voltage. The internal inductor in the RF Choke717may be implemented as a resistor, stub or impedance convertor as mentioned above.

After the RF signal is applied at a port and the transistor whose gate (or control electrode in case a non-FET type transistor is utilized) is directly coupled to the output of the choke at the same gate, the RF signal is sent to the next gate as in the circulator art. With the envelope bias controller705controlling the gate and drain biases of all the transistors, the biases are shifted based on the RF input envelope by the envelope bias controller705and this in turn substantially increases the power handling capacity of the circulator700while increasing its efficiency, reducing the insertion loss and providing more isolation between the ports.

The RF signal paths are shown with elements715in those paths. Elements715merely denote that those paths are preferable either entirely or partially formed as a microstrip, so the depicted conductors in the RF signal path connecting the output of choke717(which is also connected to the gate of T1) to the drain of T2are preferably implemented as microstrips, particularly if the disclosed active circulator is embodied as a MMIC where these conductors would be spaced from an underlying ground plate (not shown) by a dielectric layer (also not shown) formed as a part of the MMIC.

The sources of the transistors T1, T2and T3are each connected by conductor to a central junction point714, each such conductor being preferably implemented as a microstrips. The central junction point714is coupled to DC ground preferably via a parallel arrangement of a resistor Rcand an inductor RL.

Resistors Rfand capacitors Cfprovide a feedback path. For normal values, they do not produce any DC loss or significant RF loss. In some embodiments it may be useful to arrange resistors Rfand capacitors Cfin a parallel arrangement as opposed to the series arrangement shown inFIG. 7. Nevertheless, the depicted series arrangement is believed to be superior in order to separate the drain bias voltage from the gate bias voltage.

As shown inFIG. 7, three small value resistors716(typically less than 5 ohms each) can be added between the sources of the transistors and the common junction714. This is for the circulator stability and corresponding DC and RF power loss through these resistors should be negligible.

Circulator system800inFIG. 8is another embodiment of the current technology. It augments the conventional circulator shown inFIG. 1with an envelope bias controller805to control the drain bias. This addition of the envelope bias controller805allows for shifting the drain bias based on the input power, thus allowing stable operations at high power as explained earlier, thus significantly increasing the power handling capacity of the circulator.

The envelope bias controller805receives the selected RF input831. In the case of a single envelope bias controller805, this RF input831is the RF input of the highest power among the RF inputs to the various ports. If the envelope bias controller805is used for each transistor or for a group of transistors, the selected RF input831to the signal detector is the input RF that has the highest power input among the selected group of ports.

The RF input is detected and this detection signal can be properly transformed into low frequency envelope signal. The detection subsystem830can be of any type of detection circuit, such as reverse schottky diode, resistor sensing or direct power coupling. Envelope signal transformation from the detected signal can be done by using proper filtering circuit subsystem820. The most commonly used filtering subsystem820is a low pass filtering system, but other harmonic filtering can also be used depending on the system requirement. The filtered signal from the subsystem820is then sent to a voltage supply modulator subsystem810. The voltage supply modulator810will be controlled by the envelope signal information from the filtering subsystem820and is used to shape the proper voltage magnitude for the gate and drain bias over the input power level. When the voltage source modulator810modulates the bias voltages Vds, it has to take proper modulation function of the envelope signal and has to be fast enough to follow the envelope signal frequency. Since the timing delay occurs through the detector830, filtering (820) and voltage modulator (810) subsystems, timing synchronizing technique has to be applied to synchronize the phases of the input signal831and modulated voltage Vdsat the output of the envelope bias controller705.

In particular configurations, it may be desirable to have individual detector circuits and modulator circuits to control the biases for each port separately. In other applications you can have a common detector, filter and modulating subsystems and have a common bias control for a group of ports and their associated Vdsand Vgs. In some applications, the ability to handle high power may be more important than the DC loss. Of the various embodiments presented, one can generate combination of selected features in the design of these embodiments to meet any given application needs.

Modifications, additions, or omissions may be made to the systems, apparatuses, and methods described herein without departing from the scope of the technology. The components of the systems and apparatuses may be integrated or separated. Moreover, the operations of the systems and apparatuses may be performed by more, fewer, or other components. The methods may include more, fewer, or other steps. Additionally, steps may be performed in any suitable order. As used in this document, “each” refers to each member of a set or each member of a subset of a set.

To aid the Patent Office, and any readers of any patent issued on this application in interpreting the claims appended hereto, applicants wish to note that they do not intend any of the appended claims or claim elements to invoke paragraph 6 of 35 U.S.C. Section 112 as it exists on the date of filing hereof unless the words “means for” or “step for” are explicitly used in the particular claim.