Transmitter for transmitting multi-bit data

A transmitter includes a driver circuit configured to drive a channel connected to a first node by controlling a turn-on impedance of a pull-up path, a turn on impedance of a pull-down path, or both according to a plurality of control signals; an encoder configured to generate the plurality of control signals according to a multi-bit data and a calibration signal; and a calibration circuit configured to generate the calibration signal including calibration information corresponding to the plurality of control signals, wherein the encoder determines activation and magnitude of each of the plurality of control signals according to the multi-bit data and the calibration information.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean Patent Application No. 10-2019-0063587, filed on May 30, 2019, which are incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

Various embodiments may relate to a transmitter for transmitting multi-bit data.

2. Related Art

In order to transmit data at high speed, multi-bit data is transmitted.

For example, a four-level pulse amplitude modulation (PAM-4) signal is a multi-level signal having four levels corresponding to 2-bit data.

FIG. 1includes eye diagrams showing a comparison of the PAM-2 signal and the PAM-4 signal.

The PAM-2 signal is a binary signal with a wide gap between the signals.

However, multi-level signals such as PAM-4 are vulnerable to noise because the gap between levels in the vertical direction (here, the differences in voltage levels) is narrower than for a PAM-2 signal.

FIG. 2illustrates a phenomenon in which the impedance of a termination resistor of the receiver (here, a resistor formed using an on resistance of a MOSFET) depends on the magnitude of the output voltage.

When transmitting multi-bit data, output voltage varies depending on the data, and as a result, the impedance of the termination resistor depends on the data.

As a result, the signal levels may not be evenly arranged in the eye diagram, thereby degrading the linearity of the transmitter.

SUMMARY

In accordance with an embodiment of the present disclosure, a transmitter may include a driver circuit configured to drive a channel connected to a first node by controlling a turn-on impedance of a pull-up path and/or a pull-down path according to a plurality of control signals; an encoder configured to generate the plurality of control signals according to a multi-bit data and a calibration signal; and a calibration circuit configured to generate the calibration signal including calibration information corresponding to the plurality of control signals, wherein the encoder determines activation and magnitude of each of the plurality of control signals according to the multi-bit data and the calibration information.

DETAILED DESCRIPTION

Various embodiments will be described below with reference to the accompanying figures. Embodiments are provided for illustrative purposes and other embodiments that are not explicitly illustrated or described are possible. Further, modifications can be made to embodiments of the present disclosure that will be described below in detail.

FIG. 3is a block diagram of a transmitter33according to an embodiment of the present disclosure.

Hereinafter, a transmitter33for transmitting 2-bit data will be described as an example. A most significant bit of the 2-bit data is represented as D1and a least significant bit of the 2-bit data is represented as D0.

The transmitter33according to an embodiment of the present disclosure includes a driver circuit100, an encoder200, and a calibration circuit300.

The driver circuit100drives a channel connected to the first node N1according to a plurality of control signals DU0, DU1, DU2, DD0, and DD1. The first node N1may also be referred to as an output node.

In the present embodiment, each of the plurality of control signals DU0, DU1, DU2, DD0, and DD1is a multi-bit digital signal, and hereinafter, each of the plurality of control signals DU0, DU1, DU2, DD0, and DD1may also be referred to as a multi-bit control signal.

Each of the multi-bit control signals DU0, DU1, and DU2are used to control a respective pull up driver circuit included in the driver circuit100, and each of the multi-bit signals DD0and DD1are used to control a respective a pull down driver circuit included in the driver circuit100.

The encoder200encodes the multi-bit data D1, D0according to the calibration signal ZQ provided from the calibration circuit300to produce the multi-bit control signals DU0, DU1, DU2, DD0, and DD1that control the driver circuit100.

The calibration circuit300performs a calibration operation to determine the calibration signal ZQ according to levels of the output signal.

The determined calibration signal ZQ is provided to the encoder100and used to determine the plurality of multi-bit control signals DU0, DU1, DU2, DD0, and DD1.

A calibration resistor may be connected to the second node N2of the calibration circuit300. The second node N2may be referred to as a calibration node.

Detailed configurations and operations of the driver circuit100, the encoder200, and the calibration circuit300will be described below.

The transmitter may further include a data conversion circuit10for converting the input data into multi-bit data.

The data conversion circuit10may be implemented by a person skilled in the art using a conventionally known technique such as a data serialization circuit, and a detailed description thereof will be omitted.

FIG. 4is a block diagram illustrating a driver circuit100according to an embodiment of the present disclosure.

The driver circuit100includes a plurality of pull-up driver circuits110,111, and112connected between the power supply VDDQ and the first node N1, and a plurality of pull-down driver circuits120and121connected between the ground GND and the first node N1.

Hereinafter, the power supply VDDQ may be referred to as a first power supply, and the ground GND may be referred to as a second power supply.

InFIG. 4, each pull-up driver circuit is briefly represented as a PU and each pull-down driver circuit is represented by a PD.

A respective multi-bit control signal among a plurality of multi-bit control signals DU0, DU1, DU2, DD0, and DD1is applied to the pull-up driver circuits PU and the pull-down drivers circuit PD.

For example, the multi-bit control signal DU0is applied to the pull-up driver circuit110, the multi-bit control signal DU1is applied to the pull-up driver circuit111, the multi-bit control signal DU2is applied to the pull-up driver circuit112, the multi-bit control signal DD0is applied to the pull-down driver circuit120, and the multi-bit control signal DD1is applied to the pull-down driver circuit121.

InFIG. 4, the voltage of the output node No of the receiver connected to the first node N1through the channel is represented as an output voltage VOUT, and the termination resistor20included in the receiver is connected between the output node No and ground. InFIG. 4, the termination resistor20of the receiver is represented by RT.

In the driver circuit100, the number of pull-up driver circuits and pull-down driver circuits may vary in various embodiments.

FIG. 5shows a driver circuit101according to another embodiment of the present disclosure.

In the embodiment ofFIG. 5, unlike the embodiment ofFIG. 4, the number of pull-up driver circuits110and111is two and the number of pull-down driver circuits120,121, and122is three.

In addition, the embodiment ofFIG. 5is different from the embodiment ofFIG. 4in that the termination resistor21of the receiver is connected between the power supply and the output node No.

In the embodiment ofFIG. 5, the multi-bit control signal DU0is applied to the pull-up driver circuit110, the multi-bit control signal DU1is applied to the pull-up driver circuit111, the multi-bit control signal DD0is applied to the pull-down driver circuit120, the multi-bit control signal DD1is applied to the pull-down driver circuit121, and the multi-bit control signal DD2is applied to the pull-down driver circuit122.

FIG. 6shows a driver circuit102according to another embodiment of the present disclosure.

The embodiment ofFIG. 6is a differential driver circuit102.

The driver circuit102includes a first driver circuit103for generating one of the differential output signals and a second driver circuit104for generating the other of the differential output signals.

Each of the first driver circuit103and the second driver circuit104has a configuration substantially as same as that of the driver circuit100ofFIG. 4.

The first driver circuit103includes pull-up driver circuits110,111, and112, and includes pull-down driver circuits120and121.

In the first driver circuit103, the multi-bit control signal DU0Pis input to the pull-up driver circuit110, and the multi-bit control signal DD0Pis input to the pull-down driver circuit120. Other corresponding multi-bit control signals are also applied to the remaining pull-up driver circuits111and112and the pull-down driver circuit121.

In the second driver circuit104, the multi-bit control signal DU0Nis input to the pull-up driver circuit130, and the multi-bit control signal DD0Nis input to the pull-down driver circuit140. Other corresponding multi-bit control signals are also applied to the remaining pull-up driver circuits131and132and the pull-down driver circuit141.

In the embodiment ofFIG. 6, the driver circuit102includes an eleventh node N11which is one of the differential output nodes and a twelfth node N12which is the other of the differential output nodes.

The eleventh node N11transfers output of the first driver circuit103to the first output node Nop of the receiver through a first channel, and the twelfth node N12transfers output of the second driver circuit104to the second output node Non of the receiver through a second channel.

In the receiver, the termination resistor22is connected between the first output node Nop and the second output node Non.

InFIG. 6, voltage output from the first output node Non is represented by VOUTP, and voltage output from the second output node Non is represented by VOUTN.

As described above, the detailed configuration of the driver circuit100may be variously changed.

Hereinafter, an embodiment will be described based on the driver circuit100illustrated inFIG. 4.

FIGS. 7A to 7Eare circuit diagrams each showing a pull-up driver circuit or a pull-down driver circuit according to an embodiment of the present disclosure.FIGS. 7A to 7Cshow pull-up driver circuits, andFIGS. 7D and 7Eshow pull-down driver circuits.

In each pull-up driver circuit, a number of circuits corresponding to the number of bits of the multi-bit control signal provided to the pull-up driver circuit are connected in parallel between the power supply VDDQ and the first node N1and each of them is controlled by a corresponding bit of a multi-bit control signal DU. An on resistance of each pull-up driver circuit is determined by how many of the parallel-connected circuits are turned on.

In each pull-down driver circuit, a number of circuits corresponding to the number of bits of the multi-bit control signal provided to the pull-down driver are connected in parallel between the ground GND and the first node N1and each of them is controlled by a corresponding bit of a multi-bit control signal DD. An on resistance of each pull-down driver circuit is determined by how many of the parallel-connected circuits are turned on.

In an embodiment, the pull-up driver circuit may include a plurality of PMOS transistors connected in parallel as shown inFIG. 7A. In another embodiment, the pull-up driver circuit may include a plurality of pairs connected in parallel, each pair including a PMOS transistor and a resistor connected in series as shown inFIG. 7B. In another embodiment, the pull-up driver circuit may include a plurality of N-channel MOS (NMOS) transistors connected in parallel as shown inFIG. 7C.

In an embodiment, the pull-down driver circuit may include a plurality of NMOS transistors connected in parallel as shown inFIG. 7D. In another embodiment, the pull-down driver circuit may include a plurality of pairs connected in parallel, each pair including a resistor and a NMOS transistor connected in series as shown inFIG. 7E.

In the illustrative embodiment presented herein, each of the pull-up driver circuits110to112has a structure as shown inFIG. 7C, and each of the pull-down driver circuits120and121has a structure as shown inFIG. 7D, but embodiments are not limited thereto.

FIG. 8is a circuit diagram illustrating a termination circuit20of a receiver and a driver circuit100in which both a pull-up driver circuit and a pull-down driver circuit are implemented with NMOS transistors.

For convenience, only one NMOS transistor is shown in each of the pull-up driver circuit and the pull-down driver circuit. However, it is apparent from the foregoing description that a plurality of NMOS transistors are connected in parallel, and corresponding bits of a multi-bit control signal are input to each gate.

A person skilled in the art can derive an embodiment in which the pull-up driver circuit and the pull-down driver circuit each include one NMOS transistor, and the control signal applied to each gate is variably adjusted as an analog signal. In the following, however, the embodiment in which the control signal is analog is omitted.

InFIG. 8, the pull-up driver circuit110includes NMOS transistors MU0each having a gate to which a bit of a control signal DU0is respectively applied and a source and a drain that are connected between a power supply VDDQ and a first node N1.

The pull-up driver circuit111includes an NMOS transistors MU1each having a gate to which a bit of a control signal DU1is respectively applied and a source and a drain that are connected between a power supply VDDQ and a first node N1.

The pull-up driver circuit112includes NMOS transistors MU2each having a gate to which a bit of a control signal DU2is respectively applied and a source and a drain that are connected between a power supply VDDQ and a first node N1.

The pull-down driver circuit120includes NMOS transistors MD0each having a gate to which a bit of a control signal DD0is respectively applied and a source and a drain that are connected between a first node N1and a ground.

The pull-down driver circuit121includes NMOS transistors MD1each having a gate to which a bit of a control signal DD1is respectively applied and a source and a drain that are connected between a first node N1and a ground.

InFIG. 8, the termination resistor20of the receiver includes an NMOS transistor MRXhaving a source and a drain connected between an output node No and a ground and a gate connected to a power supply.

FIGS. 9 to 12are diagrams for explaining the operation of the driver circuit100ofFIG. 8.

FIG. 9illustrates a case where the multi-bit data input to the encoder200are “11”.

When the multi-bit data is “11”, the driver circuit100produces the output voltage VOUT having a value of one half of the power supply voltage VDDQ.

When the multi-bit data is “11”, the pull-up driver circuits110to112are all turned on and the pull-down driver circuits120and121are all turned off.

In the figures, a pull-up driver circuit or a pull-down driver circuit in the turn-off state is indicated by a dotted line.

The number of NMOS transistors turned on in each of the pull-up drive circuits110to112is determined by a (previously performed) calibration operation.

An impedance of each of the pull-up driver circuits110to112may be adjusted according to the number of turned-on NMOS transistors.

The calibration operation will be described later in detail.

InFIG. 9, the impedance of the pull-up driver circuit110is represented by RMU0, the impedance of the pull-up driver circuit111is represented by RMU1, and the impedance of the pull-up driver circuit112is represented by RMU2.

In addition, when the multi-bit data is “11”, it is assumed that the impedance of the termination resistor20is Zoequal to the characteristic impedance of the channel.

InFIG. 9, the driver circuit100must satisfy two conditions as shown in the drawing.

First, the output impedance of the driver circuit100should be equal to the characteristic impedance Zoof the channel. This is a general requirement for maximum power delivery.

InFIG. 9, RPUrepresents impedance of the entire pull-up driver circuit and RPDrepresents impedance of the entire pull-down driver circuit.

Since the DC level VDDQ/2 of the output voltage VOUT of the receiver is a division of the power supply voltage VDDQ by pull-up impedance, pull-down impedance and termination resistance, the second condition must be satisfied.

Accordingly, total impedance RMU0∥RMU1∥RMU2(wherein “x∥y” is an impedance resulting from connecting impedances x and y in parallel) of the entire pull-up driver circuits110to112is controlled to be equal to Zo.

FIG. 10shows a case where the multi-bit data input to the encoder200is “10”.

When the multi-bit data is “10”, the driver circuit100produces the output voltage VOUT having a value of one third of the power supply voltage VDDQ.

In the present embodiment, when the multi-bit data is “10”, the pull-up driver circuits110and111and the pull-down driver circuit121are turned on, and the pull-up driver circuit112and the pull-down driver circuit120are turned off.

As described above, the number of NMOS transistors turned on in each of the pull-up driver circuits110and111and the pull-down driver circuit121is determined by a calibration operation.

InFIG. 10, impedance of the pull-down driver circuit121is represented by RMD1.

In addition, when the multi-bit data is “10”, it is assumed that impedance of the termination resistor20is changed to Zo+Δ0due to the change of the output voltage VOUT (as illustrated in the graph ofFIG. 2).

As inFIG. 9, the driver circuit100must satisfy two conditions.

First, the output impedance of the drive circuit100should be equal to the characteristic impedance Zoof the channel. This is a general requirement for maximum power delivery.

Since the DC level VDDQ/3 of the receiver's output voltage VOUT is a division of the supply voltage VDDQ by pull-up impedance, pull-down impedance and termination resistance, a second condition must be satisfied.

Given the above two conditions, the composite impedance of the pull-up driver circuit (RPU=RMU0∥RMU1) and the composite impedance of the pull-down driver circuit (RPD=RMD1) can be expressed using Zoand Δ0.

These expressions are shown inFIG. 10, and the expression development process is known by those skilled in the art, and thus descriptions thereof are omitted.

FIG. 11illustrates a case where the multi-bit data input to the encoder200is “01”.

When the multi-bit data is “01”, the driver circuit100produces the output voltage VOUT having a value of ⅙ of the power supply voltage VDDQ.

In the present embodiment, when the multi-bit data is “01”, the pull-up driver circuit110and the pull-down driver circuits120and121are turned on and the pull-up driver circuits111and112are turned off.

As described above, the number of NMOS transistors turned on in each of the pull-up driver circuit110and the pull-down driver circuits120and121turned on is determined by a calibration operation.

InFIG. 11, the impedance of the pull-down driver circuit120is represented as RMD0.

In addition, when the multi-bit data is “01”, it is assumed that the impedance of the termination resistor20is changed to Zo+Δ1due to the change of the output voltage.

As inFIG. 11, the driver circuit100must satisfy two conditions.

First, the output impedance of the drive circuit100should be equal to the characteristic impedance Zoof the channel. This is a general requirement for maximum power delivery.

Since the DC level VDDQ/6 of the output voltage VOUT of the receiver is a division of the power supply voltage VDDQ by the pull-up impedance, the pull-down impedance and the termination resistance, the second condition must be satisfied.

Given the above two conditions, the impedance of the entire pull-up driver circuit (RPU=RMU0) and the impedance of the entire pull-down driver circuit (RPD=RMD0∥RMD1) can be expressed using Zoand Δ1.

These expressions are shown inFIG. 11together, and the expression development process is known to a person skilled in the art, and thus descriptions thereof are omitted.

FIG. 12illustrates a case where the multi-bit data input to the encoder200is “00” respectively.

When the multi-bit data is “00”, the driver circuit100produces the output voltage VOUT having a value of a ground voltage.

In the present embodiment, when the multi-bit data is “00”, the pull-up driver circuits110to112are all turned off, and the pull-down driver circuits120and121are all turned on.

Since the output voltage VOUT is the ground voltage, the driver circuit100does not need to satisfy special conditions.

By using mathematical expressions shown inFIGS. 9 to 12, the impedances RMU0, RMU1and RMU2of the pull-up driver circuits110to112and the impedances RMD0and RMD1of the pull-down driver circuits120and121may be represented by Zo, Δ0, and Δ1respectively.

In the present embodiment, instead of determining the impedance of the pull-up driver circuit and the pull-down driver circuit in advance by measuring Δ0and Δ1, number of the NMOS transistors turned on in each of the pull-up driver circuit and the pull-down driver circuit is determined by performing a calibration operation.

FIG. 13is a circuit diagram illustrating an encoder200according to an embodiment of the present disclosure.

The encoder200includes an activation decision circuit210and a magnitude decision circuit220.

The activation decision circuit210determines whether to activate each of the multi-bit control signals according to the values of bits D1and D0of the multi-bit data, and thus turns on or off the pull-up driver circuit and the pull-down driver circuit.

For example, when all bits of the multi-bit control signal are ‘0’, the pull-up driver circuit or the pull-down driver circuit is turned off, and when at least one of the bits of the multi-bit control signal is ‘1’, the pull-up driver circuit or pull-down driver circuit is turned on.

Referring toFIGS. 9 to 12, the first pull-up driver circuit110is turned on when the multi-bit data is “11”, “10”, or “01”.

Accordingly, the multi-bit control signal DU0is a signal having a high level on one or more of its bits when D1or D0is “1”.

Therefore, the activation decision circuit210includes a NOR gate211that performs a NOR operation on the bits D1and D0of the multi-bit data and an inverter212that inverts the output of the NOR gate211.

The signal output from the inverter212is one of a plurality of logical combination signals obtained by logically combining bit D1and D0of the multi-bit data, and the multi-bit control signal DU0is provided by adjusting magnitude of the signal output from the inverter212at the magnitude decision circuit220.

A magnitude selection circuit221included in the magnitude decision circuit220selects 0 or the output of the inverter212as the a value for each bit of the multi-bit control signal DU0according to corresponding bits of the calibration signal ZQ.

As such, the magnitude determination circuit220determines magnitude of the activated multi-bit control signal according to the calibration signal ZQ.

The turn-on impedance of the corresponding pull-up driver circuit or the pull-down driver circuit may be adjusted differently according to the magnitude of the activated multi-bit control signal.

The calibration signal ZQ may be provided as a plurality of multi-bit control signals.

In the present embodiment, the calibration signal ZQ includes a plurality of count values CMU0, CMU1, CMU2, CMD0, and CMD1as calibration information for a plurality of multi-bit control signals.

For example, the count value CMU0is provided to the magnitude selection circuit221to determine the number of bits activated in the multi-bit control signal DU0. Thus, a first bit of the multi-bit control signal DU0will be equal to 0 when a first bit of the count value CMU0is 0 and equal to the output of the inverter212when the first bit of the count value CMU0is 1, a second bit of the multi-bit control signal DU0will be equal to 0 when a second bit of the count value CMU0is 0 and equal to the output of the inverter212when the second bit of the count value CMU0is 1, and so on. As a result, the multi-bit control signal DU0will have a value correspond to the count value CMU0when the output of the inverter212is 1 (that is, when the first pull-up driver circuit110is turned on), and will have a value of 0 otherwise.

The remaining multi-bit control signals may also be determined on the same principle as described above by count values corresponding to a value of multi-bit data.

FIG. 14is a circuit diagram illustrating a calibration circuit300according to an embodiment of the present disclosure.

The calibration circuit300includes a first counter311, a second counter312, a third counter313, a first comparator321, a second comparator322, a third comparator323and a replica circuit330.

The first comparator321increases or decreases the value of the first counter311by comparing the first reference voltage VREFUand the output voltage VOUT.

The second comparator322increases or decreases the value of the second counter312by comparing the second reference voltage VREFDand the output voltage VOUT.

The third comparator323increases or decreases the value of the third counter313by comparing the reference voltage VREFwith the calibration voltage VOUT2.

The calibration voltage VOUT2represents the voltage of the second node N2.

The output of the first counter311corresponds to a multi-bit control signal for controlling the pull-up driver circuit of the driver circuit100, and the output of the second counter312corresponds to a multi-bit control signal for controlling the pull-down driver circuit of the driver circuit100.

In the drawing, the pull-up driver circuit includes all of the pull-up driver circuits110to112ofFIG. 8, and these are collectively represented as an NMOS transistor MU.

In the calibration operation, the output value of the first counter311are equally applied to the turned-on pull-up driver circuits110to112.

In the drawing, the pull-down driver circuit includes all of the pull-down driver circuits120and121ofFIG. 8, and these are collectively represented as an NMOS transistor MD.

In the calibration operation, the output values of the second counter312are equally to the turned-on pull-down driver circuits120to121.

The output of the third counter313corresponds to the multi-bit control signal for controlling the replica driver circuit330.

In the present embodiment, wherein the calibration resistor30is a pull-down resistor, the replica driver circuit330includes a replica pull-up driver circuit that duplicates the pull-up driver circuits110to112ofFIG. 8and is turned on or turned off in the same manner as the pull-up driver circuit110according to the multi-bit data.

In another embodiment in which the calibration resistor30is a pull-up resistor, the replica driver circuit330may include a replica pull-down driver circuit.

For convenience, the replica pull-up driver circuit is represented as an NMOS transistor MRU.

In the calibration operation, the output values of the third counter313are applied to the turned on pull-up driver circuit.

A calibration resistor30having the same impedance as the characteristic impedance Zoof the channel is connected to the second node N2of the calibration circuit300. In an embodiment, unlike the termination resistor20, the impedance of the calibration resistor30does not vary in response to variations in the voltage across the calibration resistor30.

The calibration circuit300performs calibration operation for each level of the output voltage corresponding to a combination of the multi-bit data to correspond to a change in the resistance value of the termination resistor20with respect to the change in the output voltage.

This ensures that differences between adjacent levels of the output voltage are substantially the same, that is, that the levels of the output voltage are evenly distributed.

Hereinafter, a calibration operation for determining a count value corresponding to each of the plurality of multi-bit control signals of the calibration signal ZQ will be described.

FIGS. 15 to 19illustrate the operation of a calibration circuit according to an embodiment of the present disclosure.

As described above, the number of activated bits of the multi-bit control signal provided to the pull-up driver circuit and the pull-down driver circuit is determined through the calibration operation. Hereinafter, the number of activated bits of the multi-bit control signal corresponds to the count value.

FIGS. 15 and 16correspond to first and second steps of a calibration operation for the case where the multi-bit data is “01”.

To understand the calibration operation, reference is also made toFIG. 11which shows the driver circuit100in the case where the multi-bit data is “01”.

In this case, the pull-up and pull-down driver circuits in both the driver circuit100and the replica driver circuit330are turned on or turned off in the same manner as the pull-up driver circuit110ofFIG. 11(i.e., a pull-up driver circuit110in the driver circuit100and its replica in the replica driver circuit330are turned on, the other pull-up drivers are turned off, and all the pull-down driver circuits in the driver circuit100are turned on).

InFIG. 15, a count value CMU0corresponding to a multi-bit control signal to be provided to the pull-up driver circuit110is determined. As indicated by the dotted line, during the process illustrated byFIG. 15, the pull-down driver circuits in the driver circuit100are turned off.

InFIG. 15, the first reference voltage VREFUand the reference voltage VREFare fixed to VDDQ/6, and the value C0of the first counter311and the value C1of the third counter313are determined such that the output voltage VOUT and the calibration voltage VOUT2become VDDQ/6. The value C0of the first counter311may be determined by incrementing the first counter311while the output voltage VOUT is less than VDDQ/6 or by decrementing the first counter311while the output voltage VOUT is greater than VDDQ/6. The value C1of the third counter313may be determined by incrementing the third counter313while the calibration voltage VOUT2is less than VDDQ/6 or by decrementing the third counter313while the calibration voltage VOUT2is greater than VDDQ/6.

When the output voltage VOUT and the calibration voltage VOUT2become VDDQ/6, then because the output voltage VOUT is determined by the resistive voltage divider comprising MUand MRXand the calibration voltage VOUT2is determined by the resistive voltage divider comprising MRUand the calibration resistor30, the impedance of the pull-up driver circuit110in the driver circuit100is 5(Zo+Δ1) and the impedance of the replica driver circuit330is 5Zo.

The count value C0provided to the pull-up driver circuit110and the impedance of the pull-up driver circuit110are inversely related because a higher count value C0corresponds to more of the parallel circuits that make up the pull-up driver circuit110being turned on.

InFIG. 11, the impedance RMU0of the pull-up driver circuit110is equal to the parallel connection of a resistors having an impedance of 6(Zo+Δ1) and a resistor having an impedance of 6Zorespectively. i.e. to 6(Zo+Δ1)∥6Zo.

Accordingly, the impedance RMU0of the pull-up driver circuit110is 6/5 times greater than the resistance that would be obtained by placing the impedance of the pull-up driver circuit110in the driver circuit100ifFIG. 15, i.e., 5(Zo+Δ1), and the impedance of the replica driver circuit330inFIG. 15, i.e., 5Zo, in parallel. This is summarized in Equation 1 below.

Since the impedance of the pull-up driver circuit110is 5(Zo+Δ1) and the impedance of the replica driver circuit330is 5Zo, the count value CMU0corresponding to the impedance RMU0may be known by using Equation 1.

Because turning on another parallel circuit in the pull-up driver circuit110or the replica driver circuit330is equivalent to adding to their respective count value and the resistance therefore decreases when the count value increases, the count value CMU0may be determined as shown in Equation 2 below.

As shown inFIG. 11, since the pull-down driver circuits120and121are turned on when D1=0 and D0=1, count values to be input to the pull-down driver circuits120and121need to be determined.

Accordingly, as shown inFIG. 16, the first comparator321is deactivated, the value of the first counter311is fixed to CMU0, and VDDQ/6 is input as the second reference voltage VREFDand then the value of the second counter312is determined by incrementing the second counter312while the output voltage VOUT is greater than VDDQ/6 or by decrementing the second counter312while the output voltage VOUT is less than VDDQ/6.

The determined value C2of the second counter312corresponds to the total impedance RMD0∥RMD1of the pull-down driver circuits120and121inFIG. 11.

If the count value corresponding to the multi-bit control signal to be provided to the pull-down driver circuit120is CMD0, and the count value corresponding to the multi-bit control signal to be provided to the pull-down driver circuit121is CMD1, the following equation 3 holds since a parallel connection of the pull-down driver circuits corresponds to adding count values.
CMD0+CMD1=C2  [Equation 3]

FIGS. 17 and 18correspond to first and second steps of a calibration operation for the case where the multi-bit data is “10”.

To understand the calibration operation, reference is also made toFIG. 10which shows the driver circuit100in the case where the multi-bit data is “10”.

In this case, the driver circuit100and the replica driver circuit330are turned on or turned off in the same manner as the pull-up driver circuit110ofFIG. 10.

InFIG. 17, a count value CMU1corresponding to multi-bit control signals to be provided to the pull-up driver circuit111are determined using, inter alia, the count value CMU0determined inFIG. 15for the pull-up driver circuit110.

InFIG. 17, when the first reference voltage VREFUand the reference voltage VREFare fixed to VDDQ/3, the value C3of the first counter311and the value C4of the third counter313are determined such that the output voltage VOUT and the calibration voltage VOUT2become VDDQ/3. The values C3and C4are determined in much the same manner as the values C0and C1inFIG. 15, but using VDDQ/3 instead of VDDQ/6 as the target voltage for the output voltage VOUT and the calibration voltage VOUT2.

Because the output voltage VOUT and the calibration voltage VOUT2are generated using resistive voltage dividers, when those voltages are equal to VDDQ/3 the combined impedance of the pull-up driver circuits110and110in the driver circuit100is 2(Zo+Δ1) and the impedance of the replica driver circuit330is 2Zo.

The count value C3corresponding to the multi-bit control signal to be provided to the pull-up driver circuits110and111is inversely proportional to the combined impedance of the pull-up driver circuits110and111.

Total impedance RMU0∥RMU1of pull-up driver circuits110and111inFIG. 10is similar to a parallel connection of a resistor whose impedance is 2(Zo+Δ1) and a resistor whose impedance is 2Zo.

This is summarized in Equation 4 as below.

Equation 5 is derived based on the same principle as described above with respect toFIG. 15, and Equation 6 is derived by applying Equation 2 to Equation 5.

InFIG. 10, since the pull-down driver circuit121is turned on, a count value corresponding to the pull-down driver circuit121should be determined.

Accordingly, as shown inFIG. 18, the first comparator321is deactivated, the value of the first counter311is fixed to CMU0+CMU1, and VDDQ/3 is input as the second reference voltage VREFD, and then the value C5of the second counter312is determined in the manner that the value C2was determined inFIG. 16, but using VDDQ/3 instead of VDDQ/6 as the target voltage for the output voltage VOUT.

The determined value C5of the second counter312corresponds to the total impedance RMD1of the pull-down driver circuit121inFIG. 10.

Accordingly, the count value CMD1corresponding to the pull-down driver circuit121is equal to C5and the count value CMD0corresponding to the pull-down driver circuit120is derived as shown in Equation 7 by applying C5to Equation 3.
CMD1=C5,CMD0=C2−C5  [Equation 7]

FIG. 19corresponds to a calibration operation for the case where the multi-bit data is “11”.

To understand the calibration operation, reference is also made toFIG. 9which shows the driver circuit100in the case where the multi-bit data is “11”.

In this case, the driver circuit100is turned on or turned off in the same manner as shown inFIG. 9.

InFIG. 19, the first reference voltage VREFUis fixed to VDDQ/2, and the value C6of the first counter311is determined such that the output voltage VOUT and the calibration voltage VOUT2are VDDQ/2. The values C6is determined in much the same manner as the values C0inFIG. 15, but using VDDQ/2 instead of VDDQ/6 as the target voltage for the output voltage VOUT.

In addition, the impedance of the pull-up driver circuit110in the driver circuit100is Zo.

When the count value C6corresponding to the pull-up driver circuit110and Equation 5 are combined, a count value CMU2is obtained as shown in Equation 8.

As described above, a plurality of count values included in the calibration signal ZQ may be determined.

The encoder200generates a plurality of multi-bit control signals using the calibration signal ZQ generated as described above.

FIG. 20is a graph showing the effect of the present embodiment.

Unlike the prior art, it can be seen that the output voltage of the multilevel signal is evenly distributed in the present embodiment, thereby improving linearity of the transmitter.

Although various embodiments have been described for illustrative purposes, various changes and modifications may be possible.