Semiconductor device

In some embodiments, 3-dimensional semiconductor memory device includes a semiconductor substrate extending horizontally in a first direction and a second direction crossing the first direction. A stacked memory cell array is formed on the semiconductor substrate. The memory device further includes a separation pattern including a plurality of separation lines extending in the first direction and arranged in the second direction, and dividing the stacked memory cell array into a plurality of memory cell structures extending in the first direction and arranged in the second direction. An upper insulating layer is formed above the plurality of memory cell structures and separation lines, and a passivation layer is formed above the upper insulating layer. The passivation layer includes a plurality of first regions having a first vertical thickness. A plurality of gap regions in the passivation layer are formed between the plurality of first regions. The plurality of first regions vertically overlap the plurality of memory cell structures, and the plurality of gap regions vertically overlap the plurality of separation lines.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority and benefit of Korean Patent Application No. 10-2017-0166984, filed on Dec. 6, 2017, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

BACKGROUND

Semiconductor devices have gradually been reduced in size while simultaneously being required to be able to process large amounts of data. Accordingly, a degree of integration of semiconductor devices has been increasing. As one method of improving the degree of integration of semiconductor devices, semiconductor devices having a vertical transistor structure, instead of an existing planar transistor structure, have been proposed. These types of semiconductor devices often suffer from warpage that occurs due to heating during the manufacturing process, which can be undesirable and can result in reliability issues.

SUMMARY

An aspect of the present inventive concept may provide a semiconductor device having controlled warpage and improved reliability.

In some embodiments, 3-dimensional semiconductor memory device includes a semiconductor substrate extending horizontally in a first direction and a second direction crossing the first direction. A stacked memory cell array is formed on the semiconductor substrate. The memory device further includes a separation pattern including a plurality of separation lines extending in the first direction and arranged in the second direction, and dividing the stacked memory cell array into a plurality of memory cell structures extending in the first direction and arranged in the second direction. An upper insulating layer is formed above the plurality of memory cell structures and separation lines, and a passivation layer is formed above the upper insulating layer. The passivation layer includes a plurality of first regions having a first vertical thickness. A plurality of gap regions in the passivation layer are formed between the plurality of first regions. The plurality of first regions vertically overlap the plurality of memory cell structures, and the plurality of gap regions vertically overlap the plurality of separation lines.

In some embodiments, which may include the above embodiment, a vertical NAND (VNAND) semiconductor device includes a semiconductor substrate, a plurality of gate electrode layers alternately formed with a plurality of interlayer insulating layers on the substrate in a vertical stack, and forming a plurality of gate stack structures extending in a first horizontal direction and separated from each other in a second horizontal direction perpendicular to the first direction, a plurality of vertical channels passing through each of the plurality of gate stack structures, wherein the plurality of vertical channels form transistor strings, a plurality of separation areas extending in the first horizontal direction and arranged in the second horizontal direction between the plurality of gate stack structures to separate the gate stack structures from each other, an upper insulating layer formed above the plurality of gate electrode layers, and a passivation layer formed above the upper insulating layer. The passivation layer includes a plurality of first regions having a first vertical thickness. A plurality of gap regions in the passivation layer are formed between the plurality of first regions. In addition, the plurality of first regions vertically overlap the plurality of gate stack structures, and the plurality of gap regions vertically overlap the plurality of separation areas.

In some embodiments, which may include the above embodiments, a vertical NAND (VNAND) semiconductor device includes a semiconductor substrate, a plurality of gate stack structures formed on the semiconductor substrate, the plurality of gate stack structures extending lengthwise in a first direction and separated from each other in a second direction perpendicular to the first direction, a plurality of vertical channels passing through each of the plurality of gate stack structures, wherein the plurality of vertical channels form transistor strings, a plurality of separation areas extending lengthwise in the first direction and arranged in the second direction between the plurality of gate stack structures to separate the gate stack structures from each other, an upper insulating layer formed above the plurality of gate stack structures, and a passivation layer formed above the upper insulating layer. The passivation layer includes a plurality of first line patterns extending in the first direction and having a first vertical thickness and includes a plurality of second line patterns having a second vertical thickness smaller than the first vertical thickness and extending in the first direction. The first line patterns are arranged to reduce warpage of the semiconductor device in the first direction and the first line patterns combined with the second line patterns are arranged to reduce warpage of the semiconductor device in the second direction.

In some embodiments, which may include the above embodiments, a vertical NAND (VNAND) semiconductor device includes a semiconductor substrate, a plurality of gate electrode layers alternately formed with a plurality of interlayer insulating layers on the substrate in a vertical stack, and forming a plurality of gate stack structures extending lengthwise in a first direction and separated from each other in a second direction perpendicular to the first direction, a plurality of vertical channels passing through each of the plurality of gate stack structures, wherein the plurality of vertical channels form transistor strings, a plurality of separation areas extending in the first direction and arranged in the second direction between the plurality of gate stack structures to separate the gate stack structures from each other, an upper insulating layer formed above the plurality of gate electrode layers, and a passivation layer formed above the upper insulating layer. The passivation layer includes a plurality of first regions having a first vertical thickness and a plurality of second regions having a second vertical thickness different from the first vertical thickness. The plurality of first regions extend in the first direction to cover the plurality of gate stack structures, and the plurality of second regions extend in the first direction to cover the plurality of separation areas, such that the plurality of first regions are arranged alternately with the plurality of second regions in the second direction.

In some embodiments, which may include the above embodiments, a method of manufacturing a 3-dimensional semiconductor memory device includes providing a semiconductor substrate extending horizontally in a first direction and a second direction crossing the first direction, forming a stacked memory cell array on the semiconductor substrate, forming a separation pattern including separation lines extending in the first direction and arranged in the second direction, the separation lines dividing the stacked memory cell array into a plurality of memory cell structures extending in the first direction and arranged in the second direction, forming an upper insulating layer above the plurality of memory cell structures and separation lines, forming a passivation layer above the upper insulating layer. The passivation layer includes a plurality of first regions having a first vertical thickness, a plurality of gap regions are formed in the passivation layer between the plurality of first regions, and the plurality of first regions vertically overlap the plurality of memory cell structures, and the plurality of gap regions vertically overlap the plurality of separation lines.

DETAILED DESCRIPTION

Hereinafter, various embodiments of the present inventive concept will be described with reference to the accompanying drawings.

FIG. 1is a schematic block diagram illustrating a semiconductor device according to example embodiments of the present inventive concept.

Referring toFIG. 1, a semiconductor device10may include a memory cell array20and a control logic30.

The memory cell array20may include a plurality of memory blocks, and each of the memory blocks may include a plurality of memory cells. The plurality of memory cells may be connected to a row decoder32via a string select line SSL, a plurality of word lines WLs, and a ground select line GSL, and to a page buffer34via bit lines BLs. In some example embodiments, a plurality of memory cells arranged in the same row may be connected to the same word line WL, and a plurality of memory cells arranged in the same column may be connected to the same bit line BL.

The control logic30may include the row decoder32, the page buffer34, and a control circuit36.

The row decoder32may decode an input address, and generate and transmit driving signals of the word lines WL. The row decoder32may supply a word line voltage generated in a voltage generation circuit included in the control circuit36to a selected word line WL and unselected word lines WLs, in response to a control of the control circuit36.

The page buffer34may be connected to the memory cell array20via the bit lines BLs to read information stored in the memory cells. The page buffer34may temporarily store data to be stored in the memory cells or may sense the data stored in the memory cells, depending on an operation mode. The page buffer34may include a column decoder and a sensing amplifier. The column decoder may selectively activate the bit lines BLs of the memory cell array20. The sensing amplifier may sense a voltage of a bit line BL selected by the column decoder to read data stored in a selected memory cell, during a reading operation.

The control circuit36may control operations of the row decoder32and the page buffer34. The control circuit36may receive an external control signal and an external voltage and operate according to the received control signal. The control circuit36may include the voltage generation circuit generating voltages, such as a programming voltage, a reading voltage, and an erasing voltage, necessary for an internal operation, using the external voltage. The control circuit36may control reading, writing, and/or erasing operations in response to the control signals. In addition, the control circuit36may include an input/output circuit. The input/output circuit may receive data DATA to be transmitted to the page buffer34during a programming operation, and output data DATA received from the page buffer34during a reading operation.

FIG. 2is an equivalent circuit diagram illustrating a memory cell array of a semiconductor device according to example embodiments of the present inventive concept.FIG. 2is a conceptual circuit diagram provided to illustrate the memory cell array20ofFIG. 1.

Referring toFIG. 2, the memory cell array20may include a plurality of memory cell strings S, each of which includes memory cells MC connected to each other in series, and a ground select transistor GST and string select transistors SST1and SST2respectively connected to both ends of the memory cells MC in series. The memory cells MC connected to each other in series may be respectively connected to n word lines WL0to WLn for selecting the memory cells MC.

A gate terminal of the ground select transistor GST may be connected to a ground select line GSL, and a source terminal of the ground select transistor GST may be connected to a common source line CSL. Gate terminals of the string select transistors SST1and SST2may be respectively connected to string select lines SSL1and SSL2, and source terminals of the string select transistors SST1and SST2may be connected to drain terminals of the memory cells MC. InFIG. 2, one ground select transistor GST and two string select transistors SST1and SST2are connected to the plurality of memory cells MC, connected to each other in series. However, a plurality of ground select transistors GST or one string select transistor SST may be connected to the memory cells MC. In some example embodiments, one or more dummy lines DWL or buffer lines may further be arranged between the uppermost word line WLn among the word lines WL0to WLn and the string select line SSL.

Drain terminals of the string select transistors SST1and SST2may be connected to bit lines BL0to BL2. When a signal is applied to the gate terminals of the string select transistors SST1and SST2via the string select lines SSL1and SSL2, the signal applied via the bit lines BL0to BL2may be transmitted to the memory cells MC connected to each other in series, and thereby, a data reading or data writing operation may be performed. An erasing operation in which data written in the memory cells MC is removed may be performed by applying a predetermined erase voltage via a substrate. In some example embodiments, the semiconductor device may include at least one dummy string. The dummy string may be a string including dummy channels electrically isolated from the bit lines BL0to BL2.

FIGS. 3 and 4are a schematic plan view and a schematic perspective view illustrating a semiconductor device according to example embodiments of the present inventive concept. InFIG. 3, only main configurations of a semiconductor device100are illustrated, for ease of understanding the present inventive concept.

Referring toFIGS. 3 and 4, the semiconductor device100may include a substrate101, a stacked memory cell array including gate electrodes130stacked on the substrate101, and vertical channels CH passing through the gate electrodes130, separation areas SA extending through the gate electrodes130, interconnection layers170electrically connected to the channels CH and the gate electrodes130, and a passivation layer190arranged above the interconnection layers170. The semiconductor device100may further include interlayer insulating layers120alternately stacked with the gate electrodes130on the substrate101to form a gate stack structure GS, a conductive layer165and separation insulating layer160configuring the separation areas SA, channel areas140disposed in the channels CH, and first and second upper insulating layers182and184.

In the semiconductor device100, one memory cell string may be formed around each of the channels CH, and a plurality of memory cell strings may be arranged in rows and columns in an x-direction and a y-direction.

The substrate101may have an upper surface extending horizontally in the x-direction and the y-direction. The substrate101may include a semiconductor material, such as a Group IV semiconductor material, a Group III-V compound semiconductor material, or a Group II-VI oxide semiconductor material. For example, the Group IV semiconductor material may include silicon, germanium, or silicon-germanium. The substrate101may be provided in a form of a bulk wafer or an epitaxial layer.

The plurality of gate electrodes131to138:130may be arranged to be spaced apart from each other on a side surface of each of the channels CH in a direction perpendicular to the substrate101. The gate electrodes130may respectively comprise gate electrodes of the ground select transistor GST, the plurality of memory cells MC, and the string select transistors SST1and SST2, illustrated inFIG. 2. The gate electrodes130may extend to comprise the word lines WL0to WLn, the string select lines SSL1and SSL2, and the ground select line GSL, wherein the word lines WL0to WLn may be commonly connected in a predetermined unit of adjacent memory cell strings S arranged in the x-direction and the y-direction. The gate electrodes130configuring the string select lines SSL1and SSL2may be isolated from each other in the y-direction by a string insulating layer103. However, the number of gate electrodes130isolated by the string insulating layer103is not limited to that illustrated in the drawings.

In some example embodiments, the string select transistors SST1and SST2and the ground select transistor GST may include one or more the gate electrodes130, and have the same structure as or a different structure from the gate electrodes130of the memory cells MC. Some of the gate electrodes130, such as the gate electrodes130arranged to be adjacent to the gate electrodes130of the ground select transistor GST or the string select transistors SST1and SST2, may be dummy gate electrodes.

As illustrated inFIG. 3, the gate electrodes130may be arranged to be spaced apart from each other in the y-direction by the separation areas SA extending in the x-direction. The separation areas SA may have a line shape, and therefore may be referred to as separation lines, where a plurality of separation lines form a separation pattern. For example, the gate electrodes130disposed between two or three separation areas SA may form one memory block, but the scale of the memory block is not limited thereto. In some example embodiments, some of the separation areas SA may be isolated in the x-direction in a region not illustrated in the drawings and, accordingly, the plurality of separation areas SA may be spaced apart from each other in the x-direction and aligned in a straight line.

The gate electrodes130may include a metal, such as tungsten (W). In some example embodiments, the gate electrodes130may include polysilicon or a metal silicide material. In some example embodiments, the gate electrodes130may further include a diffusion barrier layer. For example, the diffusion barrier layer may include tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

The interlayer insulating layers120may be interposed between the gate electrodes130. The interlayer insulating layers120, like the gate electrodes130, may be arranged to be spaced apart in a direction perpendicular to an upper surface of the substrate101and may extend in the x-direction. The interlayer insulating layers120may include an insulating material, such as silicon oxide or silicon nitride. Side surfaces of the interlayer insulating layers120may be coplanar with side surfaces of the gate electrodes130, but are not limited thereto. In some example embodiments, the side surfaces of the interlayer insulating layers120may have a structure protruding from the side surfaces of the gate electrodes130toward the separation insulating layer160.

The channels CH may pass through the gate stack structure GS and may be arranged to be spaced apart from each other in rows and columns on the substrate101. The channels CH may be arranged to form a lattice pattern or a zigzag form in a certain direction. Each of the channels CH may have a side surface perpendicular to the substrate101. Alternatively, each of the channels CH may have an inclined side surface such that a width thereof decreases toward the substrate101depending on an aspect ratio thereof. The channel areas140may be disposed in the channels CH. The channel areas140may have an annular shape, surrounding channel insulating layers150disposed in the channels CH. In some example embodiments, the channel areas140may have a pillar shape, such as a cylindrical shape or a prismatic shape, without channel insulating layers150. The channel areas140may be connected to epitaxial layers107therebelow. The channel areas140may include a semiconductor material, such as polysilicon or single crystalline silicon, and the semiconductor material may be an undoped material or a material including p-type or n-type impurities. The channels CH, adjacently arranged in a straight line in the y-direction, may be respectively connected to different bit lines173by channel plugs172connected to channel pads155. In addition, some of the channels CH may be dummy channels, not electrically connected to the bit lines173.

The channel pads155may be disposed on the channel areas140of the channels CH. The channel pads155may be disposed to cover upper surfaces of the channel insulating layers150and electrically connected to the channel areas140. The channel pads155may include, for example, doped polysilicon.

A gate dielectric layer145may be interposed between the gate electrodes130and the channel areas140. The gate dielectric layer145may include a tunneling layer, a charge storage layer, and a blocking layer, sequentially stacked on the channel areas140. The tunneling layer may allow charges to move to the charge storage layer in an F-N tunneling mechanism. The tunneling layer may include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or a combination thereof. The charge storage layer may be a charge-trapping layer or a floating gate conductive layer. In some example embodiments, when the charge storage layer is the charge-trapping layer, the charge storage layer may be formed of silicon nitride. The blocking layer may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), a high-k dielectric material, or a combination thereof. In some example embodiments, at least a portion of the blocking layer may extend in parallel to the gate electrodes130, but are not limited thereto.

The epitaxial layer107may be disposed at lower ends of the channels CH on the substrate101. The epitaxial layer107may be disposed on a side surface of at least one gate electrode130. The epitaxial layer107may be disposed in a recessed area of the substrate101. An upper surface of the epitaxial layer107may be higher than an upper surface of the lowest gate electrode131and lower than a lower surface of the gate electrode132disposed on the lowest gate electrode131, but is not limited to that illustrated in the drawings. By virtue of the epitaxial layer107, even when an aspect ratio of the channels CH increases, the channel areas140may be stably electrically connected to the substrate101, and characteristics of the ground select transistor GST disposed between the memory cell strings may be uniform. However, in some example embodiments, the epitaxial layer107may be omitted. In this case, the channel areas140may be directly connected to the substrate101.

The separation areas SA may pass through the gate stack structure GS between the channels CH to be connected to the substrate101. The separation areas SA may be electrically insulated from the gate electrodes130by the separation insulating layer160. Accordingly, the gate electrodes130may be physically and electrically separated from each other at predetermined intervals in the y-direction, with the conductive layer165therebetween to form a plurality of vertical gate stack structures, also referred to as vertical memory cell structures. The conductive layer165may have a line shape extending in the x-direction and may correspond to the common source line CSL described above with reference toFIGS. 1 and 2. The conductive layer165may be arranged at predetermined intervals in the y-direction, for example, for every four to five columns of the channels CH, but the present inventive concept is not limited thereto. Although the conductive layer165is illustrated as having a side surface perpendicular to the upper surface of the substrate101in the drawings, the source conductive layer180may have a shape in which a width thereof decreases toward the substrate101due to a high aspect ratio.

The interconnection layers170may be electrically connected to the gate electrodes130, the channel areas140, and the conductive layer165, and may be arranged to electrically connect the memory cells MC to circuit devices not illustrated in the drawings. The interconnection layers170may be disposed in the first and second upper insulating layers182and184. The first and second upper insulating layers182and184may be formed of an insulating material. For example, the first and second upper insulating layers182and184may include silicon oxide or silicon nitride. Each of the first and second upper insulating layers182and184may be formed of a plurality of layers. The interconnection layers170may include channel plugs172, bit lines173, first plugs174, and first interconnection lines175, sequentially stacked on the channel pad155. The number of the plugs and interconnection lines configuring the interconnection layers170may be variously modified according to various example embodiments. The interconnection layers170may include a conductive material, such as tungsten (W), copper (Cu), or aluminum (Al).

The passivation layer190may be disposed on the interconnection layers170and may function to protect underlying devices from moisture and impurities. A polyimide layer may further be disposed on the passivation layer190for performing a subsequent packaging process.

The passivation layer190may include first regions and second regions that comprise first line patterns192and second line patterns194. The first and second line patterns192and194may have a line shape extending in the x-direction. The first and second line patterns192and194may have different vertical thicknesses from each other. The first and second line patterns192and194may have different widths from each other in the y-direction. Lower surfaces of the first and second line patterns192and194may be arranged to be continuously connected with no level difference. For example, a lower surface190B of the passivation layer190may form a continuous flat or curved surface, unlike an upper surface190A of the passivation layer190. Accordingly, the passivation layer190may have unevenness on the upper surface190A thereof (e.g., a step shape). The lower surface190B of the passivation layer190may have a flat surface or a surface curved according to a profile of the underlying interconnection layers170. It will be understood that, although the terms first, second, third etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. Unless the context indicates otherwise, these terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section, for example as a naming convention. Thus, a first element, component, region, layer or section discussed below in one section of the specification could be termed a second element, component, region, layer or section in another section of the specification or in the claims without departing from the teachings of the present invention. In addition, in certain cases, even if a term is not described using “first,” “second,” etc., in the specification, it may still be referred to as “first” or “second” in a claim in order to distinguish different claimed elements from each other.

The first line patterns192may have a first thickness T1, and the second line patterns194may have a second thickness T2smaller than the first thickness T1. The first line patterns192may have a first width W1, and the second line patterns194may have a second width W2smaller than first width W1. For example, the first thickness T1may be in a range between 5000 Å and 10000 Å, and the second thickness T2may be in a range between 3000 Å and 8000 Å. The difference (ΔT) between the first thickness T1and the second thickness T2may be in a range between 2000 Å and 7000 Å, and in one embodiment is about 2000 Å. In one embodiment, a ratio of the thickness of the entire passivation layer192(e.g., T2) to the thickness bottom portion of the passivation layer192L (e.g., T1) may be between about 5:3 and about 5:4. For example, the first width W1may be in a range between 1 μm to 3 μm, and the second width W2may be in a range between 10 nm to 300 nm. Compared to a thickness (e.g., height) of the semiconductor device100, the first thickness T1may be between about 4% and 16%, and in some optimal cases, about 10% of the thickness of the semiconductor device100(e.g., from a bottom of the substrate101to a top-most surface of the passivation layer190). Alternatively, or in addition, the first thickness T1may be between about 4% and 16%, and in some optimal cases, about 10% of the thickness (e.g., height) from a top of the substrate101to a top-most surface of the passivation layer190. Terms such as “about” or “approximately” may reflect amounts, sizes, orientations, or layouts that vary only in a small relative manner, and/or in a way that does not significantly alter the operation, functionality, or structure of certain elements. For example, a range from “about 0.1 to about 1” may encompass a range such as a 0%-5% deviation around 0.1 and a 0% to 5% deviation around 1, especially if such deviation maintains the same effect as the listed range.

The first line patterns192may be arranged above the gate electrodes130or the gate stack structure GS to be vertically aligned with the gate electrodes130and gate stack structures GS, and the second line patterns194may be arranged above the separation areas SA to be vertically aligned with the separation areas SA. However, the arrangement of the first and second line patterns192and194is not limited thereto. A width of one gate stack structure GS, that is, a third width W3of the gate electrodes130of one gate stack structure GS may be greater than a fourth width W4of the separation area SA. In some example embodiments, the first width W1may be substantially the same as the third width W3, and the second width W2may be substantially the same as the fourth width W4. In addition, a ratio (W3/W4) of the third width W3to the fourth width W4may be substantially the same as a ratio (W1/W2) of the first width W1to the second width W2, but the present inventive concept is not limited thereto. For example, the ratio (W3/W4) of the third width W3to the fourth width W4may be in a range between 80% and 120% of the ratio (W1/W2) of the first width W1to the second width W2. The ratio (W1/W2) of the first width W1to the second width W2may be, for example, greater than about 5 and smaller than about 50. When the ratio (W1/W2) is smaller than 5, a stress releasing effect may not be sufficient in the x-direction. When the ratio (W1/W2) is greater than 50, stress may increase in the y-direction. However, the ratio (W1/W2) may be adjusted in consideration of the thicknesses T1and T2of the first and second line patterns192and194, a total volume of the gate electrodes130, and a degree of warpage in the semiconductor device100to be described later.

Because a gap may be formed in the passivation layer190where the second line patterns194are formed, those patterns may be referred to as gap regions. As shown inFIG. 4and discussed above, at the gap regions, a vertical thickness of the passivation layer may be less than a vertical thickness of the passivation layer at regions where the first line patterns192are formed. However, in some embodiments (not shown inFIG. 4), instead of part of the thickness of the passivation layer being removed at the second line patterns194, the passivation layer may be absent, such that there is no passivation layer at the gap regions (e.g., all of the thickness of the passivation layer may be removed). Thus, in one embodiment, the passivation layer190is continuously formed in the Y direction to cover a plurality of gate stack structures separated by gap regions, such as separation lines, and has recess regions that form those separation lines where a thickness is smaller than full-thickness (e.g., non-recessed) regions. In another embodiment, the passivation layer190is not continuously formed in the Y direction (at least from a cross-sectional view) because there are gap regions where the passivation layer190is absent.

The passivation layer190may be formed of a material applying stress to the substrate101in a different direction from the gate electrodes130. The passivation layer190may be formed of silicon nitride, for example. In some example embodiments, the first and second line patterns192and194configuring the passivation layer190may be formed of different materials from each other. Alternatively, a lower layer192L of the first line patterns192having the same upper surface as the second line patterns194may be formed of the same material as the second line patterns194, and an upper layer192U of the first line patterns192may be formed of a different material from the second line patterns194.

Material layers formed on the substrate101may apply stress to the substrate101disposed therebelow and other material layers disposed thereabove. Due to this, warpage may occur in the semiconductor device100including the substrate101. In particular, stress applied by a material layer disposed on the entire upper surface of the substrate101or arranged at a large ratio to the entire upper surface of the substrate101, may be a main cause of the warpage. For example, the gate electrodes130may apply tensile stress to the substrate101. In this case, the semiconductor device100including the substrate101may be concavely warped. That is, an edge portion of the substrate101may be lifted up, and a center portion of the substrate101may protrude downwardly. In contrast, the passivation layer190may apply compressive stress to the substrate101. In this case, the semiconductor device100, including the substrate101, may be convexly warped.

In particular, the passivation layer190may be arranged such that the first and second line patterns192and194have different thicknesses and widths from each other in consideration of the gate electrodes130extending in the x-direction and arranged to be spaced apart from each other in the y-direction by the separation areas SA. Accordingly, the warpage of the semiconductor device100in certain directions may be effectively reduced. Accordingly, the passivation layer190according to the example embodiment of the present inventive concept may function as a stress releasing layer as well as a protection layer. This will be described in more detail with reference toFIGS. 5A to 5C.

FIGS. 5A to 5Care diagrams provided to illustrate warpage of a semiconductor device according to example embodiments of the present inventive concept.

Referring toFIG. 5A, a degree of warpage of a semiconductor device in one chip unit without accounting for the passivation layer190(refer toFIGS. 3 and 4) is exemplarily illustrated. Thus,FIG. 5Amay represent the amount of warpage that would occur if certain heating processes (e.g., solder reflow) were to take place without the passivation layer190in place. The semiconductor device may be subjected to anisotropic stress applied in the x-direction and the y-direction, and thereby a saddle-shaped warpage may occur. That is, the semiconductor device may have a shape protruding downwardly (concave) in the x-direction and protruding upwardly (convex) in the y-direction. Such anisotropic stress may be generated, for example, since the gate stack structure GS is arranged in a line shape extending in the x-direction. However, materials configuring other structures and process conditions may affect the warpage of the semiconductor device.

Referring toFIG. 5B, a degree of warpage of a semiconductor device according to a comparative example in which the passivation layer190is formed to have a uniform thickness is exemplarily illustrated. The passivation layer190may have a tendency to apply compressive stress to a semiconductor device and thereby convexly warp the semiconductor device, as described above. Accordingly, compared with the semiconductor device illustrated inFIG. 5A, bending of the semiconductor device may become more gentle in the x-direction but become more severe in the y-direction in which the semiconductor device already tends to have a convexly warped shape (e.g., due to heating processes such as a solder reflow process). Thus, when a semiconductor device is warped due to anisotropic stress, the stress may further increase in a certain direction even though a stress-releasing layer configured to apply one of the compressive stress and the tensile stress is deposited.

Referring toFIG. 5C, a degree of warpage of a semiconductor device in which the passivation layer190includes the first and second line patterns192and194having different thicknesses from each other as described above with reference toFIGS. 3 and 4, is exemplarily illustrated. Compared withFIG. 5B, the stress may further be released or reduced in the x-direction and the bending may become gentle or reversed, for example compared to a situation where no passivation layer is used. In the y-direction, the bending may be similar to that illustrated inFIG. 5A, and may be prevented from at least becoming severe like that illustrated inFIG. 5B. Thus, in the y-direction, an increase in warpage shown inFIG. 5Bmay be limited by using the passivation layer190described herein (e.g., compared to a situation where a passivation layer having a uniform thickness throughout is used). In this manner, warpage in the y-direction is reduced. Stated another way, the use of a passivation layer190such as described herein may increase warpage in the y-direction compared to a situation where no passivation layer is used, but limits the increase, and reduces warpage compared to when a flat, uniform thickness passivation layer is used.

Referring toFIGS. 3 and 4together, when the passivation layer190includes the first and second line patterns192and194having different thicknesses from each other, the stress may be released in the y-direction due to a space between the first line patterns192, for example, a region in which the passivation layer190is not arranged on the second line patterns194. The stress may increase in the x-direction since the first line patterns192has a larger volume than the second line patterns194due to thickness increment (ΔT). Accordingly, the existing stress releasing effect may be maximized in the x-direction, while the increase of the stress due to the thickness increment (ΔT) is minimized in the y-direction.

As discussed above, when first and second line patterns192and194are formed to have different vertical thicknesses from each other, as shown for example inFIG. 4, the first line patterns192are arranged to reduce warpage of the semiconductor device in the x-direction compared to a warpage that would exist without the passivation layer190(e.g., by applying a stress that counteracts the concave warpage in the x-direction caused by the differences in thermal expansion coefficients of the substrate101and the gate stack including layers120and130), and the first line patterns192combined with the second line patterns194are arranged to increase warpage of the semiconductor device in the y-direction compared to a warpage that would exist without the passivation layer190(e.g., by applying a stress that adds to the convex warpage in the y-direction caused by differences in thermal expansion coefficients of the substrate101and the different layers formed on the substrate101in the y-direction). However, because of the second line patterns194, the first line patterns192combined with the second line patterns194decrease warpage in the x-direction by a greater amount than the first line patterns192combined with the second line patterns194increase warpage in the y-direction, thereby having an overall beneficial effect on warpage of the semiconductor device100. For example, the passivation layer190with first line patterns192and second line patterns194may reduce the x-direction warpage effect caused by layers below the passivation by 70% to 100% while increasing the y-direction warpage effect by 5% to 30% (e.g., wherein warpages can be measured according to arc height at a maximum distance from a line connecting ends of the arc). In some embodiments, there may be no increase in y-direction warpage due to passivation layer190. As a result, the passivation layer190is patterned to reduce the amount of warpage of the semiconductor device in a first direction, such as the x-direction, without reducing the warpage of the semiconductor device in a second direction, such as the y-direction. It should be noted that based on the above patterning, the second regions of the passivation layer (e.g., second line patterns194) counteract warpage to the semiconductor device100caused by the conductive material (e.g., that forms the conductive layers165) of the separation areas SA.

FIGS. 6 and 7are schematic plan views illustrating a semiconductor device according to example embodiments.

Referring toFIG. 6, a passivation layer190aof a semiconductor device100amay include first line patterns192ahaving a relatively large width W1acovering two gate stack structures GS spaced apart from each other in the y-direction and second line patterns194ahaving a width W2the same as or similar to a width of a separation area SA, unlike the semiconductor device100according to the example embodiment described with reference toFIG. 3. The first line patterns192amay be arranged on two gate stack structures GS and one separation area SA, and the second line patterns194may be arranged on the separation areas SA on both sides of the first line patterns192a. As shown in this embodiment, the widths of the first and second line patterns192aand194aconfiguring the passivation layer190amay be variously modified according to various example embodiments of the present inventive concept.

Referring toFIG. 7, a passivation layer190bof a semiconductor device100bmay include first line patterns192bhaving a width W1covering one gate stack structure GS and second line patterns194bhaving a width W2asmaller than that of the separation area SA, unlike the semiconductor device100according to the example embodiment described with reference toFIG. 3. Accordingly, at least a portion of the first and second line patterns192band194bmay be arranged to be shifted from a top of the gate stack structure GS and the separation area SA. According to this embodiment, the first and second line patterns192band194bconfiguring the passivation layer190bmay not be exactly aligned with the gate stack structure GS and the separation area SA.

FIG. 13is a schematic plan view illustrating a semiconductor device according to example embodiments. Referring toFIG. 13, a passivation layer190eof a semiconductor device100emay include first line patterns192ehaving a relatively wide width covering portions of gate stack structures GS and second line patterns194e1and194e2, unlike the semiconductor device100according to the example embodiment described with reference toFIG. 3. The first line patterns192emay be arranged between the second line patterns194e1and194e2, and some of the second line patterns194e1may be arranged on a separation areas SA and some of the second line patterns194e2may be arranged on a string insulating layer103. The second line patterns194e2on the string insulating layer103may have a width W2athe same as or narrower than the second width W2of the second line patterns194e1. The width W2aof the second line patterns194e2may be the same as or larger than a width of the string insulating layer103.

FIG. 14is a schematic plan view illustrating a semiconductor device according to example embodiments. Referring toFIG. 14, a passivation layer190fof a semiconductor device100fmay include first line patterns192fhaving a rectangular shape and second line patterns194f1and194f2, unlike the semiconductor device100according to the example embodiment described with reference toFIG. 3. The first line patterns192fmay be arranged in a region bounded by the second line patterns194f1and194f2, and some of the second line patterns194f1may be arranged on a separation area SA and some of the second line patterns194f2may be arranged perpendicular to the second line patterns194f1between the second line patterns194f1. The second line patterns194f2may have a width W2bthe same as or similar to the second width W2of the second line patterns194f1. A width W1aof the first line patterns192fin the x-direction may be wider than the first width W1of the first line patterns192fin the y-direction to ensure a stress releasing effect in the x-direction.

FIG. 15is a schematic plan view illustrating a semiconductor device according to example embodiments. Referring toFIG. 15, a passivation layer190gof a semiconductor device100gmay include first line patterns192gand second line patterns194ghaving an elongated line shape, unlike the semiconductor device100according to the example embodiment described with reference toFIG. 3. The first line patterns192gmay be arranged surrounding the second line patterns194g, and the second line patterns194gmay be arranged to be spaced apart from each other in the x-direction. Shapes and sizes of the second line patterns194gmay be variously modified according to example embodiments and, for example, the second line patterns194gmay have circular, oval, or rectangular shapes. For example, a gap region between first line patterns192gin the y-direction may include a plurality of line patterns extending in the x-direction and arranged end-to-end in the x-direction

FIGS. 8 and 9are schematic cross-sectional views illustrating a semiconductor device according to example embodiments.

Referring toFIG. 8, a passivation layer190cof a semiconductor device100cmay have an upper surface190A having a continuous flat or curved surface and a lower surface190B having an uneven profile. For example, the first and second line patterns192cand194cmay be arranged in such a manner that upper surfaces thereof are continuously connected. Such relative arrangement of the first and second line patterns192cand194cmay be modified according to a preferred shape of upper surfaces and/or profiles of underlying interconnection layers170and second upper insulating layer184.

Referring toFIG. 9, a semiconductor device100dmay include a memory cell region CELL and a peripheral circuit region PERI. The memory cell region CELL may correspond to the memory cell array20illustrated inFIG. 1, and the peripheral circuit region PERI may correspond to the control logic30illustrated inFIG. 1. The peripheral circuit region PERI may be arranged in at least one end of the memory cell region CELL in at least one direction, for example, in the x-direction.

The gate electrodes130may extend from an edge area of the memory cell region CELL by different lengths. In the edge area, the gate electrodes130may extend in the x-direction by different lengths to provide contact areas CP having a step-wise structure. The gate electrodes130may be connected to contact plugs in the contact areas CP, and thereby be connected to upper interconnection layers170and/or external connection terminals for connecting the semiconductor device to an external device. In the contact areas CP, the gate electrodes130may be thickened so as to be stably connected to the contact plugs.

The circuit devices230may be arranged on an active region defined by device isolation layers210. The circuit devices230may include planar transistors. Each of the circuit devices230may include a circuit gate insulating layer232, a spacer layer234, and a circuit gate electrode235. Source/drain areas205may be arranged in a base substrate201on both sides of the circuit gate electrode235.

The interconnection layers170may include circuit contact plugs171, channel plugs172, bit lines173, first plugs174, a first interconnection line175, second plugs176, and a second interconnection layer177. The circuit contact plugs171may pass through a peripheral region insulating layer181and a first upper insulating layer182to connect the circuit devices230to the interconnection layers170. The number of plugs and interconnection lines configuring the interconnection layers170may be variously modified according to various example embodiments.

A passivation layer190dmay include first and second line patterns192and194alternately disposed in the y-direction, as that according to the example embodiment described above with reference toFIGS. 3 and 4. In an example embodiment, the passivation layer190dmay extend from the memory cell region CELL to the peripheral circuit region PERI. The passivation layer190dmay be arranged not to be limited on the gate electrodes130but to extend to the entire semiconductor device100dincluding the peripheral circuit region PERI. However, the arrangement of the passivation layer190dis not limited thereto. In some example embodiments, the passivation layer190dmay be arranged only on the memory cell region CELL.

The passivation layer190dmay have a lower surface curved according to a profile of underlying interconnection layers170and second upper insulating layer184. For example, as illustrated inFIG. 9, the second upper insulating layer184may have an upper surface curved according to the second interconnection layer177. In this case, the passivation layer190darranged on the second upper insulating layer184may be curved according to the upper surface of the second upper insulating layer184.

FIGS. 10A to 10Iare schematic drawings of main processes of a method of manufacturing a semiconductor device according to example embodiments of the present inventive concept. InFIGS. 10A to 10I, a region corresponding to a cross-sectional area in the y-z plane ofFIG. 4is illustrated.

The sacrificial layers110may be substituted by gate electrodes130in a subsequent process. The sacrificial layers110may be formed of a different material from the interlayer insulating layers120. For example, the interlayer insulating layers120may be formed of at least one of silicon oxide and silicon nitride, and the sacrificial layers110may be formed of a different material from the interlayer insulating layers120, selected from silicon, silicon oxide, silicon carbide, and silicon nitride. In some example embodiments, thicknesses of the interlayer insulating layers120may not be the same. For example, the lowest interlayer insulating layer121may be relatively thin, and the uppermost interlayer insulating layer129may be relatively thick. The thickness and the number of layers configuring the interlayer insulating layers120and the sacrificial layers110may be variously modified from those illustrated in the drawings.

Referring toFIG. 10B, the process may include forming a string insulating layer103, forming channel holes CHH extending perpendicularly to the substrate101, and forming an epitaxial layer107at lower portions of the channel holes CHH.

The string insulating layer103may be formed by removing a predetermined number of sacrificial layers110and interlayer insulating layers120from the top, using an additional mask layer. The string insulating layer103may be formed by depositing an insulating material on a portion from which the sacrificial layers110and the interlayer insulating layers120are removed. The string insulating layer103may be formed of a material having an etch selectivity with respect to the sacrificial layers110, together with the interlayer insulating layers120. For example, the string insulating layer103may be formed of the same material as the interlayer insulating layer120.

The channel holes CHH may be formed in a hole shape by anisotropically etching a stacked structure of the sacrificial layers110and the interlayer insulating layers120. Due to a height of the stacked structure, sidewalls of the channel holes CHH may not be perpendicular to an upper surface of the substrate101. The channel holes CHH may be formed to partially recess the substrate101. Next, the epitaxial layer107may be formed in the channel holes CHH. The epitaxial layer107may be formed in a selective epitaxial growth (SEG) process. The epitaxial layer107may be formed as a single layer or a plurality of layers. The epitaxial layer107may include, for example, polysilicon, single crystalline silicon, polycrystalline germanium, or single crystalline germanium, doped or undoped with impurities.

Referring toFIG. 10C, channels CH may be formed in the channel holes CHH by forming a gate dielectric layer145, a channel area140, a channel insulating layer150, and a channel pad155.

The gate dielectric layer145may be formed to have a uniform thickness using an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process. In the process, all or a portion of the gate dielectric layer145may be formed. For example, a portion extending perpendicularly to the substrate101along the channel holes CHH may be formed in the process.

The channel area140may be formed in the channel holes CHH disposed on the gate dielectric layer145. The channel insulating layer150may be formed to fill the channel holes CHH and formed of an insulating material. However, in some example embodiments, a conductive material may fill a space between the channel areas140in the channel holes CHH, instead of the channel insulating layer150. The channel pad155may be formed of a conductive material, such as polysilicon.

Referring toFIG. 10D, an opening area OP separating the stacked structure of the sacrificial layers110and the interlayer insulating layers120at predetermined intervals may be formed, and lateral openings LT may be formed by removing the sacrificial layers110exposed in the opening area OP.

In some example embodiments, damage of the channel pad155and the channel area140disposed below the channel pad155may be prevented by forming an additional insulating layer on the uppermost interlayer insulating layer129and the channel pad155before forming the opening area OP. The opening area OP may be formed by forming a mask layer using a photolithography process and anisotropically etching the stacked structure of the sacrificial layers110and the interlayer insulating layers120. The opening area OP may be formed in a trench shape extending in the x-direction (seeFIG. 4), and arranged in an area in which the conductive layer165and the separation insulating layer160illustrated inFIG. 4is to be formed.

The sacrificial layers110may be selectively removed with respect to the interlayer insulating layers120in a wet etching process, for example. Accordingly, a plurality of lateral openings LT may be formed between the interlayer insulating layers120, and portions of the gate dielectric layer145in the channels CH, for example, sidewalls extending perpendicularly to the substrate101along the channels CH, may be exposed through the lateral openings LT.

Referring toFIG. 10E, the gate electrodes130may be formed in the lateral openings LT.

The gate electrodes130may include, for example, a metal, polysilicon, or a metal silicide. After the gate electrodes130are formed, materials configuring the gate electrodes130, formed in the opening area OP, may be removed in an additional process so that the gate electrodes130are disposed only in the lateral openings LT. In some example embodiments, the interlayer insulating layer120may protrude toward the opening area OP further than the gate electrodes130protrude.

Referring toFIG. 10F, a separation area SA including a separation insulating layer160and a conductive layer165is formed in the opening area OP.

The separation insulating layer160may be formed to have a spacer shape by forming an insulating material and removing the insulating material on the substrate101until the upper surface of the substrate101is exposed. The conductive layer165may be formed by depositing a conductive material in the separation insulating layer160. The gate electrodes130may be spaced apart from each other at predetermined intervals in the y-direction by the separation area SA, and gate stack structures may be formed and separated by the separation area SA.

Referring toFIG. 10G, first and second upper insulating layers182and184and interconnection layers170may be formed on the channels CH.

Among the interconnection layers170, channel plugs172and first plugs174may be formed by partially forming the first and second upper insulating layers182and184, partially etching the first and second upper insulating layers182and184, and filling a conductive material in the etched portion of the first and second upper insulating layers182and184. Bit lines173and first interconnection line175may be formed by, for example, depositing a conductive material and patterning the conductive material. Additional interconnection structures connected to the channel pads155and the channel plugs172may be formed below the bit lines173, and the bit lines173may be extended in the y-direction above the additional structures.

Referring toFIG. 10H, a preliminary passivation layer190P is formed on the second upper insulating layer184.

The preliminary passivation layer190P may be formed to have the same thickness as one having a greater thickness among the first and second line patterns192and194configuring a passivation layer190in a subsequent process. The preliminary passivation layer190P may be formed of silicon nitride or plasma enhanced SiN (PE-SiN), for example.

Referring toFIG. 10I, first and second line patterns192and194may be formed by partially removing the preliminary passivation layer190P.

For example, a mask layer187may be formed on the preliminary passivation layer190P and then the preliminary passivation layer190P exposed by the mask layer187may be removed by a predetermined thickness. The preliminary passivation layer190P may be removed in a dry etching process, for example, and a thickness of the preliminary passivation layer190P etched in the process may be adjusted by controlling etching time.

The first line patterns192may be formed below the mask layer187where the preliminary passivation layer190P is not removed, and the second line patterns194may be formed in a region in which the preliminary passivation layer190P is partially removed. Thus, the passivation layer190may be formed.

The process of fabricating the passivation layer190described above with reference toFIGS. 10H and 10Imay be variously modified in various example embodiments. For example, in some example embodiments, the second line patterns194and a lower layer192L (seeFIG. 4) of the first line patterns192may be formed first, and an upper layer192U (seeFIG. 4) of the first line patterns192may be patterned thereon.

FIG. 10Jis a flowchart describing subsequent processes used to form a semiconductor device, such as a memory device. For example, step1001represents the above method10A to10I of forming a semiconductor device. External connection terminals may then be formed on the semiconductor device formed from the process shown inFIGS. 10A to 10I. For example, in step1002, contact plugs, also described as conductive plugs, may be formed through various insulating layers to have one end connected to an integrated circuit component, such as a contact area CP of a gate electrode shown inFIG. 9, and another end connected to an external connection pad, such as a connection pad formed at an upper surface of the semiconductor device (e.g., at a surface of the passivation layer). In step1003, external connection terminals, such as solder bumps or solder balls formed of a solder material, may be formed on the connection pads. Then, in step1004, a reflow process is performed, and the solder bumps or balls are heated in order to reflow the solder and connect the solder bumps or balls to another device. This heating may cause warpage of the semiconductor device, for example, according to the various embodiments described herein.

Therefore, in the manner described above, a method of manufacturing a 3-dimensional semiconductor memory device can include providing a semiconductor substrate extending horizontally in a first direction and a second direction crossing the first direction, forming a stacked memory cell array on the semiconductor substrate, and forming a separation pattern including separation lines extending in the first direction and arranged in the second direction. The separation lines divide the stacked memory cell array into a plurality of memory cell structures extending in the first direction and arranged in the second direction. An upper insulating layer may be formed above the plurality of memory cell structures and separation lines. In addition, a passivation layer may be formed above the upper insulating layer. The passivation layer includes a plurality of first regions having a first vertical thickness. A plurality of gap regions are formed between the plurality of first regions, and the plurality of first regions vertically overlap the plurality of memory cell structures, while the plurality of gap regions vertically overlap the plurality of separation lines.

In one embodiment, forming the passivation layer and the plurality of gap regions may include forming a continuous layer to cover the upper insulating layer, and removing portions of the continuous layer to form the gap regions. Furthermore, removing portions of the continuous layer may include removing portions of the continuous layer that include only part of the entire vertical thickness of the continuous layer to form line patterns in the passivation layer.

A plurality of external connection pads and external connection terminals that connect to various components, such as word lines of the 3-dimensional memory device, may be formed, for example at the passivation layer. For example, external connection pads may connect to various circuit elements through conductive plugs that pass through an insulating layer of the semiconductor device. Solder balls or bumps may be connected to the external connection pads.

As a result, a plurality of solder bumps or balls may be connected to a plurality of external connection pads at an external surface of the semiconductor device. A reflow process may be performed to heat and reflow the solder bumps, causing warpage of the 3-dimensional semiconductor device in both the first direction and the second direction. The warping may be controlled based on the pattern formed from the passivation layer, according to one or more of the various embodiments described herein.

FIG. 11is a schematic cross-sectional view illustrating a semiconductor device according to example embodiments of the present inventive concept.

Referring toFIG. 11, a semiconductor device200may include a memory cell region CELL and a peripheral circuit region PERI. The memory cell region CELL may be arranged on the peripheral circuit region PERI. In some example embodiments, the memory cell region CELL may be arranged above the peripheral circuit region PERI.

The memory cell region CELL may include a substrate101, gate electrodes130stacked on the substrate101, channels CH passing through the gate electrodes130, separation areas SA extending through the gate electrodes130, interconnection layers170electrically connected to the gate electrodes130and the channels CH, and a passivation layer190arranged on top, as described with reference toFIGS. 3 and 4. The memory cell region CELL of the semiconductor device200may further include interlayer insulating layers120stacked alternately with the gate electrodes130on the substrate101to form a gate stack structure GS, a conductive layer165and separation insulating layer160forming separation areas SA, channel areas140disposed in the channels CH, and first and second upper insulating layers182and184. The memory cell region CELL may have various structures described above with reference toFIGS. 3 to 9.

The peripheral circuit region PERI may include a base substrate201, circuit devices230arranged on the base substrate201, and circuit contact plugs250and interconnection lines260.

The base substrate201may include active regions defined by device isolation layers210. Source/drain areas205containing impurities may be formed in portions of the active regions. The base substrate201may include a semiconductor material, such as a Group IV semiconductor material, a Group III-V compound semiconductor material, or a Group II-VI oxide semiconductor material.

The circuit devices230may include planar transistors. Each of the circuit devices230may include a circuit gate insulating layer232, a spacer layer234, and a circuit gate electrode235. Source/drain areas205may be formed in the base substrate201disposed on both sides of the circuit gate electrode235.

A plurality of peripheral insulating layers240may be formed above the circuit devices230on the base substrate201. The circuit contact plugs250may pass through the peripheral insulating layers240to be connected to the source/drain areas205. By virtue of the circuit contact plugs250, an electrical signal may be applied to the circuit devices230. In a region not illustrated in the drawings, the circuit contact plugs250may also be connected to the circuit gate electrode235. The interconnection lines260may be connected to the circuit contact plugs250and may be arranged in a plurality of layers.

The semiconductor device200may be manufactured by forming the peripheral circuit region PERI first, then forming the substrate101of the memory cell region CELL on the peripheral circuit region PERI, and then forming the memory cell region CELL. The substrate101may have the same size as the base substrate201or a smaller size than the base substrate201.

FIG. 12is a schematic perspective view illustrating a semiconductor device according to example embodiments of the present inventive concept.

Referring toFIG. 12, a semiconductor device300may include a substrate301, patterns310arranged on the substrate301, an insulating layer320covering the patterns310, and a passivation layer330arranged on the insulating layer320.

The substrate301may be a semiconductor substrate or include a semiconductor substrate and circuit devices formed on the semiconductor substrate.

The patterns310may extend in the x-direction to be spaced apart from each other in the y-direction. The patterns310may configure an active region or a conductive line of the semiconductor device300. The conductive line may include, for example, a word line or a bit line. Sizes and arrangement of the patterns310may be variously modified according to the type of semiconductor device300. The patterns310may apply tensile stress or compressive stress to the substrate301. The patterns310may apply anisotropic stress to the substrate301. For example, since the patterns310are arranged to be spaced apart from each other in the y-direction, at least a portion of the stress applied in the y-direction may be released. However, since the patterns310are continuously extended in the x-direction, the stress in the x-direction may be applied to the substrate301. Accordingly, the amount and/or type of the stress applied to the substrate301in the x-direction by the patterns310may be different from those in the y-direction.

The insulating layer320may be arranged between the patterns310and the passivation layer330. Circuit devices and/or interconnection layers connected to the patterns310may further be arranged in the insulating layer320.

The passivation layer330may be arranged above the circuit devices of the semiconductor device300including the patterns310and interconnection layers connected to the circuit devices, and insulated from the circuit devices and the interconnection layers. The passivation layer330may apply tensile or compressive stress to the substrate301. The stress applied by the passivation layer330may be different from the stress applied by the patterns310. Accordingly, the passivation layer330may release the stress applied to the substrate301and/or upper layers by the patterns310. In particular, when the anisotropic stress is applied to the semiconductor device300by lower layers including the patterns310, the passivation layer330may also be arranged to apply anisotropic stress so as to reduce net stress. Accordingly, the passivation layer330may include first and second line patterns332and334extending and arranged alternately in the y-direction.

The first and second line patterns332and334may have a line shape extending in the same x-direction as the patterns310. The first and second line patterns332and334may have different thicknesses from each other. The first and second line patterns332and334may have different widths from each other in the y-direction. The first line patterns332may have a third thickness T3, and the second line patterns334may have a fourth thickness T4smaller than the third thickness T3. The first line patterns332may have a fifth width W5and the second line patterns334may have a sixth width W6the same as or different from the fifth width W5.

A seventh width W7of each of the patterns310may be the same as or different from an eighth width W8, a distance between the patterns310. A ratio (W7/W8) of the seventh width W7to the eighth width W8may be the same as or similar to a ratio (W5/W6) of the fifth width W5to the sixth width W6, but is not limited thereto. For example, even when ratio (W5/W6) of the fifth width W5to the sixth width W6is different from the ratio (W7/W8) of the seventh width W7to the eighth width W8, the stress applied to the semiconductor device300may be released by adjusting the difference between the third thickness T3and the fourth thickness T4. Accordingly, the occurrence of warpage of the semiconductor device300may be minimized by adjusting relative thicknesses and widths of the first and second line patterns332and334configuring the passivation layer330according to the amount and/or type of the stress applied by patterns310.

FIGS. 16 and 17are schematic layout diagrams of a semiconductor device, according to example embodiments.

Referring toFIGS. 16 and 17, semiconductor devices100hand100imay include at least two regions including a memory cell region CELL, a row decoder region DEC, a page buffer region PB, and another circuit region PERI, which form a peripheral circuit region.

The memory cell region CELL may be a region in which the memory cell array20described above with reference toFIG. 1is disposed. The row decoder region DEC may have the row decoder32ofFIG. 1disposed therein. The page buffer region PB may have the page buffer34ofFIG. 1disposed therein. The other circuit region PERI may have other circuits, including the control circuit36ofFIG. 1, disposed therein. The arrangement relationships of the respective regions illustrated inFIGS. 16 and 17are provided by way of example, but an arrangement of the respective regions is not limited thereto.

According to certain embodiments, the row decoder region DEC may be disposed on at least one side of the memory cell region CELL in one direction thereof, for example, an x direction. The page buffer region PB may be disposed on at least one side of the memory cell region CELL in one direction thereof, for example, in a y direction. Thus, the word lines WLs (refer toFIG. 1) may extend in the x direction from the memory cell region CELL toward the row decoder region DEC, and the bit lines BLs (refer toFIG. 1) may extend in the y direction from the memory cell region CELL toward the page buffer region PB. The other circuit region PERI may be disposed in the vicinity of the memory cell region CELL, the row decoder region DEC, and the page buffer region PB, and an I/O circuit, a high voltage generating circuit, a circuit for testing, or the like may be disposed in the other circuit region PERI.

Referring toFIG. 16, passivation layers190h1and190h2of a semiconductor device100hmay include first line patterns192h1and192h2and second line patterns194h1and194h2. The first line patterns192h1and192h2may be arranged on entire regions of the semiconductor device100hexcept regions in which the second line patterns194h1and194h2are arranged, and the second line patterns194h1and194h2may be arranged at different densities in at least two regions. The second line patterns194h1and194h2may have a smaller thickness in the vertical direction than the first line patterns192h1and192h2, similar to the patterns192and194discussed previously. Also, as can be seen inFIG. 16, the second line patterns194h1in the memory cell regions CELL may be disposed at a higher density than the second line patterns194h2disposed in other regions, including the row decoder region DEC, the page buffer region PB, and the other circuit region PERI. A distance D1between adjacent second line patterns194h1may be smaller than a distance D2between adjacent second line patterns194h2. In some embodiments, the second line patterns194h2may be omitted and the second line patterns194h1may be disposed in the memory cell regions CELL only. In some embodiments, widths of the second line patterns194h1and194h2may be different from each other.

Referring toFIG. 17, passivation layers190iof a semiconductor device100imay include first line patterns192i1and192i2and second line patterns194i2and194i2. The first line patterns192i1and192i2may be arranged on entire regions of the semiconductor device100iexcept regions in which the second line patterns194i2and194i2are arranged. The second line patterns194i2and194i2may have a smaller thickness in the vertical direction than the first line patterns192i1and192i2, similar to the patterns192and194discussed previously. Also, as can be seen inFIG. 17, the second line patterns194i2and194i2may be arranged at different densities in at least two regions including a center region CR and the other region except the center regions CR. The center region CR may be positioned on a center of the semiconductor device100i. For example, the second line patterns194i2in the center regions CR may be disposed in a higher density than the second line patterns194i2disposed in the other region. On the contrary, in some example embodiment, the second line patterns194i2in the center regions CR may be arranged in a lower density than the other region except the center region CR. A distance D3between adjacent second line patterns194i2may be smaller than a distance D4between adjacent second line patterns194i2. Such arrangements of the second line patterns194i2and194i2may be determined considering anisotropic stress applied to the semiconductor device100iand warpage type of the semiconductor device100i. In some embodiments, the second line patterns194i2may be omitted and the second line patterns194i2may be disposed in the center region CR only. In some embodiments, widths of the second line patterns194i2and194i2may be different from each other.

As described above with referring toFIGS. 16 and 17, the second line patterns194h1,194h2,194i2and194i2may be arranged at different densities in different regions of the semiconductor devices100hand100iaccording to structures and resulting warpage of the semiconductor devices100hand100i.

More specifically, inFIGS. 16 and 17, an example semiconductor device includes a control region (e.g., the row decoder region DEC, the page buffer region PB, and the other circuit region PERI) outside a stacked memory cell array (CELL). The control region may include the passivation layer. The passivation layer in at least part of the cell region includes a plurality of first regions (e.g.,192h1inFIG. 16 or 192i1inFIG. 17) having a first vertical thickness and a plurality of gap regions (e.g.,194h1inFIG. 16 or 194i1inFIG. 17) formed between the plurality of first regions. The passivation layer in at least part of the control region includes a second plurality of first regions (e.g.,192h2inFIG. 16 or 192i2inFIG. 17) having the first vertical thickness and a second plurality of gap regions (e.g.,194h2inFIG. 16 and 194i2inFIG. 17) formed between the second plurality of first regions. An additional stacked memory cell array (CELL) may be horizontally separate from the stacked memory cell array. A first portion of a control region (e.g., a central DEC region) may be between the stacked memory cell array and the additional stacked memory cell array. A second portion of the control region may be outside of the stacked memory cell array and the additional memory cell array and not between the stacked memory cell array and the additional memory cell array. As can be seen inFIGS. 16 and 17, a density of the second plurality of gap regions is smaller than a density of the plurality of gap regions that overlap the plurality of separation lines. In addition, as shown inFIG. 17, in one embodiment, the plurality of gap regions that overlap the plurality of separation lines is formed over the stacked memory cell array, the additional stacked memory cell array, and the first portion of the control region.

As set forth above, a semiconductor device according to the example embodiments of the present inventive concept may have improved reliability by providing a passivation layer patterned to correspond to gate electrodes.