Forming IV fins and III-V fins on insulator

A method of forming a semiconductor structure. The method may include; forming first fins in a pFET region and an nFET region using epitaxial growth, the first fins are a group IV semiconductor; forming a spacer layer on the first fins; removing the spacer layer from a top surface and a first side of the first fins in the nFET region, a portion of the first fins are exposed on the top surface and the first side of the first fins in the nFET region; and forming second fins on the exposed portion of the first fins using epitaxial growth, the second fins are a group IV semiconductor, the second fins have a second pitch between adjacent second fins, the first pitch is equal to the second pitch, the first fins and the second fins have a shared bottom surface.

BACKGROUND

The present invention generally relates to semiconductor device manufacturing, and more particularly to the fabrication of III-V fins and IV fins having a similar fin pitch and on a shared surface.

The downscaling of the physical dimensions of metal oxide semiconductor field effect transistors (MOSFETs) has led to performance improvements of integrated circuits and an increase in the number of transistors per chip. Multiple gate MOSFET structures, such as fin field effect transistor's (finFETs) and tri-gate structures, have been proposed as promising candidates for 14 nm technology nodes and beyond. In addition, high-mobility channel materials, such as III-V and germanium, have been proposed as technology boosters to further improve MOSFET scaling improvements.

Integration of lattice mismatched semiconductor materials is one path to high performance semiconductor devices such as complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FET) due to their high carrier mobility. For example, the heterointegration of lattice mismatched semiconductor materials with silicon will be useful for a wide variety of device applications. However, disadvantages associated with structural characteristics of lattice mismatched devices can decrease device performance, require additional processes or design constraints to counter-effect such structural characteristics or reduce manufacturing yield.

SUMMARY

According to one embodiment of the present invention, a method is provided. The method may include forming first fins on sidewalls of mandrels using epitaxial growth, the mandrels are on a buried insulator layer, the buried insulator layer is on a base substrate, the first fins have a first pitch between adjacent first fins, the first fins include a material of the IV semiconductor group, the first fins are grown in a pFET region and an nFET region; removing the mandrels; forming a conformal spacer layer directly on the first fins, the conformal spacer layer is in the nFET region and the pFET region; damaging the conformal spacer layer on a top surface and a first side surface of the first fins in the nFET region, a portion of the conformal spacer layer remains undamaged on a protected side of the first fins in the nFET region, the protected side of the first fins in the nFET region include surfaces opposite the first side surface, a mask protects the conformal spacer layer in the pFET region from damage; removing the damaged conformal spacer layer from the top surface and the first side surface of the first fins in the nFET region exposing a portion of the first fins in the nFET region; forming second fins on the exposed portion of the first fins using epitaxial growth, a bottom surface of the second fins is coplanar with a bottom surface of the first fins, the second fins have a second pitch between adjacent second fins, the second pitch is equal to the first pitch, the second fins include a material of the III-V semiconductor group, the second fins are grown in the nFET region; etching a top surface of the second fins to the top surface of the first fins, wherein the top surface of the second fins is coplanar with the top surface of the first fins; and removing the first fins from the nFET region.

According to another embodiment of the present invention, a method is provided. The method may include forming first fins on sidewalls of mandrels using epitaxial growth, the first fins have a first pitch between adjacent first fins, the first fins are in a pFET region and an nFET region; forming a spacer layer on the first fins in the pFET region and in the nFET region; removing the spacer layer from a top surface and a first side of the first fins in the nFET region, a portion of the spacer layer remains on a protected side of the first fins in the nFET region, a portion of the first fins are exposed on the top surface and the first side of the first fins in the nFET region, wherein the first fins remain covered by the spacer layer in the pFET region; forming second fins on the exposed portion of the first fins using epitaxial growth, the second fins have a second pitch between adjacent second fins, the first pitch is equal to the second pitch, the second fins are in the nFET region, the first fins and the second fins have a shared surface comprising a coplanar bottom surface of the first fins and a coplanar bottom surface of the second fins; and etching a top surface of the second fins to the top surface of the first fins, wherein the top surface of the second fins is coplanar with the top surface of the first fins.

According to another embodiment of the present invention, a structure is provided. The structure may include a set of first fins in a pFET region and a set of second fins in an nFET region, the first fins and the second fins are on a buried insulator layer, the first fins have a bottom surface coplanar with a bottom surface of the second fins, the first fins have a first pitch between adjacent first fins that is equal to a second pitch between adjacent second fins, the first fins include a group IV semiconductor material, the second fins include a group III-V semiconductor material.

DETAILED DESCRIPTION

The present invention generally relates to semiconductor device manufacturing, and more particularly to the fabrication of III-V fins and IV fins having a similar fin pitch and on a shared surface. Ideally, it may be desirable to form III-V fins and IV fins having a similar fin pitch and on a shared surface without the need for long epitaxial growth times and with low levels of defects. The purpose of forming III-V fins and IV fins having a similar fin pitch and on a shared surface may be to allow circuit designers to follow the design rule, as is known in the art.

One way to form III-V fins and IV fins having a similar fin pitch and on a shared surface is to form the IV fins in a pFET region and an nFET region, form a spacer layer on the IV fins, remove the spacer layer from a top surface and a side surface of the IV fins in the nFET region, form the III-V fins on the top surface and the side surface of the IV fins in the nFET region, remove the IV fins from the nFET region, and remove the spacer layer from both the pFET and nFET regions. One embodiment by which to form III-V fins and IV fins having a similar fin pitch and on a shared surface is described in detail below with reference to the accompanying drawingsFIGS. 1-11. It should be noted, the present embodiment utilizes the III-V group and IV group semiconductors but other materials may be used. Additionally, IV fins may be referred to as first fins and the III-V fins may be referred to as second fins.

Referring now toFIGS. 1 and 2, demonstrative illustrations of a structure100during an intermediate step of a method of fabricating III-V fins and IV fins having a similar fin pitch and on a shared surface are provided, according to an exemplary embodiment. More specifically, the method can start with fabricating mandrels106in a substrate.

The substrate may be any substrate known in the art, such as, for example, a semiconductor-on-insulator (SOI) substrate or a bulk substrate. In an embodiment, an SOI substrate is used. The SOI substrate includes a semiconductor layer105, a buried insulator layer104, and a base substrate102. The semiconductor layer105is on the buried insulator layer104and the buried insulator layer104is on the base substrate102. The SOI substrate may be formed using any technique known in the art, such as, for example, Separation by Ion Implantation of Oxygen (SIMOX) or a layer transfer process. When a layer transfer process is employed, an optional thinning step may follow the bonding of two semiconductor wafers together. The optional thinning step can reduce the thickness of a layer to a desirable thickness. In an alternative embodiment, if a bulk substrate is used, an insulating material (e.g., oxide) may be used to electrically isolate subsequently formed components (e.g., fins).

In some embodiments, the base substrate102and the semiconductor layer105may include a same or similar semiconductor material. In other embodiments, the base substrate102and the semiconductor layer105may include a different material. The term “semiconductor material” as used herein may denote any semiconducting material including, for example, silicon (Si), germanium (Ge), silicon-germanium (SiGe) or other semiconductors. Multi-layers of semiconductor materials can also be used for the base substrate102and/or the semiconductor layer105. In an embodiment, both the base substrate102and the semiconductor layer105include silicon. In another embodiment, the base substrate102is a non-semiconductor material, such as, for example, a dielectric material and/or a conductive material.

The base substrate102and the semiconductor layer105may have similar or may have different crystal orientations. For example, the crystal orientation of the base substrate102and/or the semiconductor layer105may be {100}, {110}, or {111}. Other crystallographic orientations besides those specifically mentioned can also be used. The base substrate102and/or the semiconductor layer105may be a single crystalline semiconductor material, a polycrystalline material, or an amorphous material. Typically, at least the semiconductor layer105is a single crystalline semiconductor material. In some embodiments, the semiconductor layer105, located above the buried insulator layer104, can be processed to include semiconductor regions having different crystal orientations.

The buried insulator layer104may be a crystalline or non-crystalline oxide or nitride. In an embodiment, the buried insulator layer104is an oxide, such as, for example, silicon dioxide. The buried insulator layer104may be continuous or discontinuous. The buried insulator layer104may typically have a thickness from about 1 nm to about 500 nm. In an embodiment, the buried insulator layer104may have a thickness ranging from about 10 nm to about 100 nm. In an alternative embodiment, the buried insulator layer104may include multiple dielectric layers or a stack of dielectric layers including a silicon oxide layer and/or a silicon nitride layer.

With reference toFIG. 2, the mandrels106may be formed in the semiconductor layer105using a hardmask108. The hardmask108may be formed on the semiconductor layer105using any deposition technique known in the art, such as, for example, chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, or physical vapor deposition. The hardmask108may include any masking material known in the art, such as, for example, silicon nitride (Si3N4), silicon carbide (SiC), silicon carbon nitride (SiCN), hydrogenated silicon carbide (SiCH), or any other masking material. In an embodiment, the hardmask108is a silicon nitride. A mandrel pattern may be formed in the hardmask108using any known patterning technique known in the art, such as, photolithography. The mandrels106may be formed by transferring the mandrel pattern into the semiconductor layer105. The mandrel pattern may be transferred into the semiconductor layer105by etching the semiconductor layer105selective to the hardmask108and the buried insulator layer104(i.e., etching the semiconductor layer105, where the hardmask108is a mask and the buried insulator layer104is an etch stop). There may be a mandrel pitch between any two adjacent mandrels. In an embodiment, a set of mandrels may be in a pFET region101and a set of mandrels may be in an nFET region103. It should be noted, a “set” may refer to any number of mandrels106, including a single mandrel. The mandrels106may have the same width as any adjacent mandrels.

Referring now toFIG. 3, a demonstrative illustration of a structure100during an intermediate step of a method of fabricating III-V fins and IV fins having a similar fin pitch and on a shared surface is provided, according to an exemplary embodiment. More specifically, the method can include growing IV fins110on sidewalls of the mandrels106.

The IV fins110may be grown on the sidewalls of the mandrels106in the pFET and nFET regions101,103using any formation technique known in the art, such as, for example, epitaxial growth. Epitaxy growth may be a layer of monocrystalline semiconductor material which grows outward from an exposed surface of an existing monocrystalline semiconductor region or layer. The epitaxial layer may have the same composition as the semiconductor region on which it is grown, the same impurities (e.g., dopants and their concentrations), or, alternatively, the compositions of the epitaxial layer and the underlying semiconductor region can be different. The IV fins110may have a thickness ranging from about 2 nm to about 10 nm. Defects may begin to occur in epitaxial growth if a critical thickness is exceeded, the critical thickness may range from about 2 nm to about 10 nm. In an embodiment, the IV fins110may be selectively grown on the sidewalls of the mandrels106and not on the hardmask108or the buried insulator layer104, as illustrated. The IV fins110may be germanium and have a thickness of about 8 nm.

The IV fins110may be any material known in the art, such as, for example, germanium, silicon germanium, or other good pFET materials. In an embodiment, the IV fins110may be germanium. There may be a fin pitch between any two adjacent IV fins110. A first pitch (p1) may be between adjacent IV fins110in the pFET region101and a second pitch (p2) may be between adjacent IV fins110in the nFET region103. The first pitch (p1) may be the same as the second pitch (p2). In an embodiment, both the first pitch (p1) and the second pitch (p2) are equal to about 42 nm.

Referring now toFIG. 4, a demonstrative illustration of a structure100during an intermediate step of a method of fabricating III-V fins and IV fins having a similar fin pitch and on a shared surface is provided, according to an exemplary embodiment. More specifically, the method can include removing the hardmask108and the mandrels106.

The hardmask108and the mandrels106may be removed using any mask removal technique as is known in the art, such as, for example, RIE. The etching technique used to remove the mandrels106may etch the mandrels106selective to the IV fins110and the buried insulator layer104(i.e., etching the mandrels106and using the IV fins110and the buried insulator layer104as an etch stop). An alternative method may include depositing a protective material on the buried insulator layer104and etching the mandrels106selective to the IV fins110.

Referring now toFIG. 5, a demonstrative illustration of a structure100during an intermediate step of a method of fabricating III-V fins and IV fins having a similar fin pitch and on a shared surface is provided, according to an exemplary embodiment. More specifically, the method can include forming a spacer layer112on the IV fins110.

The spacer layer112may be conformally formed on the IV fins110using any deposition technique known in the art, such as, for example, chemical vapor deposition, plasma enhanced chemical vapor deposition, or atomic layer deposition. The spacer layer112may have a thickness ranging from about 2 nm to about 15 nm. The spacer layer112may be any spacer material known in the art, such as, for example, an oxide or a nitride.

Referring now toFIGS. 6 and 7, demonstrative illustrations of a structure100during an intermediate step of a method of fabricating III-V fins and IV fins having a similar fin pitch and on a shared surface are provided, according to an exemplary embodiment. More specifically, the method can include removing the spacer layer112from a top surface and a side surface of the IV fins110in the nFET region103.

First, a mask113may be formed on the IV fins110in the pFET region101using any deposition and patterning technique known in the art, such as, for example, photolithography. The mask113may be any masking material known in the art, such as, for example, oxide, nitride, or oxynitrides.

Next, a portion of the spacer layer112may be removed from the top surface and the side surface of the IV fins110in the nFET region103by exposing the top surface and the side surface to an angled removal process150. A protected surface of the IV fins110may be a side opposite the side surface of the IV fins110in the nFET region103exposed to the angled removal process150. The angled removal process150may be any angled removal process known in the art, such as, for example, an angled ion implantation (damaging the spacer layer112on the top surface and the side surface of the IV fins110in the nFET region103and not damaging the spacer layer112on the protected surface) and a wet etch (removing the damaged spacer layer112) or an angled etch (e.g., gas cluster ion beam). The angled removal process150may expose a portion of the IV fins110on the top surface and the side surface of the IV fins110in the nFET region103(i.e., remove a covering portion of the spacer layer112from above the IV fins110in the nFET region103). The spacer layer112may remain on the protected surface of the IV fins110in the nFET region103. The mask113may be removed using any mask removal technique as is known in the art.

In an embodiment, a possible ion implantation for performing damage to the spacer layer112is Xenon ions at 5 keV to a concentration of 3×1014/cm2at an angle of 30°. More generally, it is preferred to use relatively massive ions both as a matter of delivering a suitable level of kinetic energy to target materials and damaging the targeted materials to cause the materials to etch more rapidly. The ion implantation angle chosen should also assure the implantation into the entire height of the spacer layer112and may need to be adjusted if the IV fins110are formed in particularly close proximity to each other. Depending on the thickness of the spacer layer112, the implant dose can range from 2×1013/cm2to 2×1015/cm2, the implant energy can range from about 0.5 KeV to about 100 KeV and the implant angle can range from 15° to 75°. Once the spacer layer112is damaged, a removal step may be performed to remove the damaged spacer layer112using any technique known in the art, such as, for example, a wet etch containing a solution of hydrofluoric acid as the etchant.

Referring now toFIGS. 8 and 9, demonstrative illustrations of a structure100during an intermediate step of a method of fabricating III-V fins and IV fins having a similar fin pitch and on a shared surface are provided, according to an exemplary embodiment. More specifically, the method can include forming the III-V fins114on the exposed portion of the IV fins110in the nFET region103.

The III-V fins114may be formed on the exposed portions of the IV fins110using any technique known in the art, such as, for example, epitaxial growth. The epitaxial growth of the III-V fins114may use the IV fins110as a seed layer. The spacer layer112may protect against the growth of III-V fins114on the IV fins110in the pFET region101and the protected surface of the IV fins110in the nFET region103. The III-V fins114may directly contact the buried insulator layer104; the III-V fins114and the IV fins110may share a bottom surface coplanar with a top surface of the buried insulator layer104. If the III-V fins114form on the top surface of the IV fins110, the III-V fins114may be removed from the top surface of the IV fins110using any removal technique known in the art, such as, for example, reactive ion etch (RIE) or any chemical mechanical polishing. The III-V fins114may be etched or polished to have a top surface coplanar with the top surface of the IV fins110. In an embodiment, the III-V fins114may be removed from the top surface of the IV fins110in the nFET region103using RIE, where the spacer layer112remains on the top surface of the IV fins110in the pFET region101. In an alternative embodiment, the III-V fins114may be polished and the spacer layer112may be removed from the top surface of the IV fins110in both the pFET and nFET regions101,103, this may subsequently require another masking step to protect the IV fins110in the pFET region101during subsequent processing steps.

The III-V fins114may have a similar thickness to the IV fins110(e.g., ranging from about 5 nm to about 100 nm). The III-V fins114may have a third pitch (p3) between any adjacent III-V fins114. The third pitch (p3) may be similar to the first pitch (p1).

Referring now toFIGS. 10 and 11, demonstrative illustrations of a structure100during an intermediate step of a method of fabricating III-V fins and IV fins having a similar fin pitch and on a shared surface are provided, according to an exemplary embodiment. More specifically, the method can include removing the IV fins110from the nFET region103and removing the spacer layer112from both the pFET and nFET regions101,103.

The spacer layer112may cover the IV fins110in the pFET region101, where the top surface of the IV fins110in the nFET region103are exposed. First, the IV fins110in the nFET region103may be removed using any etching technique known in the art, such as, for example, RIE selective to the spacer layer112, the III-V fins114, and the buried insulator layer104. In other words, the IV fins110in the nFET region103may be etched, where the spacer layer112and the III-V fins114are used as masks, and the buried insulator layer104is used as an etch stop. Next, the spacer layer112may be removed from both the pFET and nFET regions101,103using any etching technique known in the art, such as, for example, RIE selective to the III-V fins114and the buried insulator layer104.

After the IV fins110are removed from the nFET region103and the spacer layer112is removed from both the pFET and nFET regions101,103; a set of IV fins110may remain in the pFET region101and a set of III-V fins114may remain in the nFET region103. The third pitch (p3) may be equal to the first pitch (p1). The bottom surface of the III-V fins114may be coplanar with the bottom surface of the IV fins110, and both the III-V fins114and the IV fins110may be directly on the shared surface (e.g., the top surface of the buried insulator layer104). Circuit designers may prefer to follow a design rule for adjacent nFET and pFET regions (e.g., nFET fins and pFET fins having a similar thickness and pitch), as is known in the art. A benefit may include reducing cost and processing time by forming the III-V fins114with a thickness less than the critical thickness described above. The embodiment may avoid long growth times used in deep trench growth (i.e. aspect ratio trench growth), which may also avoids the defects that come with such growth.