Sense amplifier

A sense amplifier includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor form cross coupled sensing pairs. The third PMOS and the fourth PMOS transistors serve as compensation transistors. The third NMOS and the fourth NMOS transistors serve as sensing enabling transistors.

FIELD

The present disclosure is related to a sense amplifier with offset compensation.

BACKGROUND

A bit line sense amplifier in embedded Dynamic Random Access Memory (eDRAM) generally includes one or two cross-coupled transistor or device pairs. Ideally, each device parameter such as threshold voltage Vt, transconductance coefficient β, node capacitance, etc., of one transistor in the transistor pair is the same as that of the other transistor in the same transistor pair. Manufacturing process deviations, however, cause differences or offsets in parameters of different transistors. As a result, two transistors even though manufactured by the same process intrinsically have two threshold voltages Vt with two different values. Many techniques have been used to compensate for the difference in threshold voltages Vt. Most of the techniques, however, are not applicable for use in eDRAMs that are manufactured by advanced technology in the nano-scale and/or operate above 300 MHz.

DETAILED DESCRIPTION

Embodiments, or examples, illustrated in the drawings are disclosed below using specific language. It will nevertheless be understood that the embodiments and examples are not intended to be limiting. Any alterations and modifications in the disclosed embodiments, and any further applications of the principles disclosed in this document are contemplated as would normally occur to one of ordinary skill in the pertinent art. Reference numbers may be repeated throughout the embodiments, but they do not require that feature(s) of one embodiment apply to another embodiment, even if they share the same reference number.

Some embodiments have one or a combination of the following features and/or advantages. The disclosed compensation mechanisms allow minimum offset and steady operation of a sense amplifier in gigabit scale eDRAMs, and increased memory density and performance. However, only offset of the NMOS cross-coupled sensing pair is compensated. Because the bit lines in the memory array are pre-charged to ground, not to conventional level of ˜0.5×VDD, a special generator is not required. The pre-charge and equalizing transistors receive a gate voltage that does not exceed the operational voltage VDD. As a result, the transistors have high performance, are reliable, and can be regular logic thin-oxide transistors. Hence, a generator which provides the voltage level higher than VDD can have a lower generation capacity and occupy less area. Because of the compensation less bit line split is required and therefore enables a bit line to couple additional memory cells. Consequently, the memory is denser. The global bit lines are discharged through two instead of three NMOS transistor in a serial like manner. The read current is therefore larger that allows a faster data transfer from a (local) bit line to a global bit line, than circuits using three NMOS transistors. Only one signal is used to control the sense amplifier mode, which is advantageous over other approaches that use two signals.

Exemplary Circuit

FIG. 1is a diagram of a circuit100illustrating a sense amplifier105being used in conjunction with a memory cell195, in accordance with some embodiments. Transistor190allows access between sense amplifier105and memory cell195through bit lines BL and ZBL. Bit lines BL and ZBL are connected to an equal number of memory cells, but only one transistor190and one capacitor195are shown for illustration.

Signal EQ and transistors125,135, and145are used to pre-charge and equalize bit lines BL and ZBL. The term “pre-charge” instead of “charge” is commonly used to indicate that bit lines BL and ZBL are charged prior to sensing or reading. Transistor145is coupled between bit lines BL and ZBL. Transistors125and135are coupled in series between bit lines BL and ZBL. When signal EQ is applied with a high logic level (a High), transistors125,135, and145are turned on allowing bit lines BL and ZBL to be at the same ground level at the drains of transistors125and135. Stated differently, bit lines BL and ZBL are pre-charged and equalized to ground. In this aspect, various embodiments are different from other approaches in which bit lines BL and ZBL are pre-charged to a voltage level different from ground, such as 0.5×VDD. In some embodiments, the high logic level of signal EQ is operational voltage VDD readily available for use because voltage VDD is used by other transistors.

Word line WL turns on or off transistor190to allow access to memory cell195through transistor190. In the example ofFIG. 1, transistor190and memory cell195are electrically coupled to bit line BL for illustration. Depending on implementations in a memory array, some memory cells may be connected to bit line BL while some other memory cells may be connected to bit line ZBL. When word line WL at the gate of transistor190is applied with a low logic level (a Low), word line WL turns off transistor190and thus electrically disconnects memory cell195from bit line BL or from sense amplifier105. When word line WL is applied with a High, however, word line WL turns on transistor190and thus electrically connects memory cell195to a bit line BL. In some embodiments, the high voltage level of word line WL is about 1.3×VDD, and the low voltage level of word line WL is below ground.

In some embodiments, memory cell195is a capacitor storing charge. When memory cell195is connected to a bit line BL as shown inFIG. 1, memory cell195shares the same charge with bit line BL. Depending on the charge indicating the logic level of memory cell195, bit line BL is pulled one way or another. For example, if memory cell195stores a low logic level (e.g., a Low), bit line BL is pulled towards ground. Conversely, if memory cell195stores a high logic level, then bit line BL is pulled towards voltage VDD. After sharing the charge, the voltage difference between bit line BL and bit line ZBL, commonly called a bit line split, starts to develop. The amplitude of the bit line split depends on the charge transfer ratio or capacitance of memory cell195and bit line BL. If bit line BL is longer and connected to a lot of memory cells, the charge ratio becomes smaller and the bit line split is reduced. Conversely, if bit line BL is shorter and connected to a less memory cells, the charge ratio becomes higher and the bit line split is increased.

Bit lines BL and ZBL serve as both data input and output (TO) for sense amplifier105. Generally, except when being pre-charged and equalized, bit lines BL and ZBL are of the opposite level of one another. For example, if bit line BL is Low then bit line ZBL is High but if bit line BL is High, then bit line ZBL is Low. In a write cycle, applying a logic level to a first bit line, and the opposite level to the other bit line, enables writing the logic level at the first bit line to memory cell195. For example, applying a High to bit line BL and a Low to bit line ZBL, enables memory cell195to be written with a High. Conversely, applying a Low to bit line BL and a High to bit line ZBL, enables memory cell195to be written with a Low.

In a read cycle, sensing or reading the logic levels at bit lines BL and ZBL reveals the data stored in memory cell195. For example, if memory cell195stores a High, then sensing bit line BL reveals a High. Conversely, if memory cell195stores a Low then sensing bit line BL reveals a Low. When there is bit line split between bit lines BL and ZBL, then there is a difference in voltage VGS of transistors110and120as compared to VGS of transistors130and140. Sense amplifier105senses or amplifies this voltage difference. Voltage VGS is the voltage from a gate to a source of a transistor.

Signal CSL and transistors155and165enable the data transfer between bit lines BL and ZBL, and global bit lines GBL and ZGBL, respectively. For example, when signal CSL at the gates of NMOS transistors155and165is applied with a Low, transistors155and165are off, and act as open circuits. Global bit lines GBL and ZGBL are electrically disconnected from the respective bit lines BL and ZBL. When signal CSL, however, is applied with a High, transistors155and165are on and act as short circuits. Effectively, the data on bit lines BL and ZBL are transferred to respective global bit lines GBL and ZGBL.

Signals SP and SN are used to turn on or off sense amplifier105. Signal SP is commonly called the positive supply voltage while signal SN is commonly called the negative supply voltage (even though in many situations signal SN has a positive voltage). In general, when signals SP and SN are at a same level, amplifier105is off, and when signal SP is at VDD and signal SN is at ground level, sense amplifier105is on.

Sense amplifier105includes transistors110,120,130,140,150,160,170, and180. NMOS transistor160is coupled between the gates of transistors110and120. NMOS transistor180is coupled between the gates of transistors130and140. PMOS transistor150is coupled between the gate of transistor120and signal SN. PMOS transistor170is coupled between the gate of transistor140and signal SN. The pair of PMOS transistors110and130, and the pair of NMOS transistors120and140form the sensing pairs for sense amplifier105. Generally, because of the mismatch, such as the mismatch caused by manufacturing process variations, NMOS transistors120and140and/or PMOS transistors110and130have different characteristics, including, for example, differences in threshold voltages Vt, which lead to different drain-to-source currents, etc.

Signal SAE together with transistors150,160,170, and180are configured to compensate for the mismatch between transistors120and140. Transistors150and170are called compensation enable transistors. The drains of transistors150and170are coupled to the gates of respective transistors120and140, and to the sources of respective transistors160and180. The gates of transistors150and170are coupled together, to the gates of transistors160and180, and to signal SAE. The sources of transistors150and170are coupled to signal SN. Transistors160and180are called sensing enable transistors. The drain of transistor160is coupled to the gate of transistor110, the drains of transistors130and140, and bit line ZBL. The drain of transistor180is coupled to the gate of transistor130, the drains of transistors110and120, and bit line BL.

Signal SAE is coupled to the gates of transistors160,180,150, and170. Transistors150,160,170, and180act as switches and serve as open or short circuits depending on the need of the applications as appropriate. For example, when signal SAE is applied with a Low, signal SAE turns on PMOS transistors150and170, but turns off NMOS transistors160and180. Transistors160and180being off, act as open circuits. Transistors150and170being on, act as short circuits to compensate for the mismatch between transistors120and140.

In contrast, when signal SAE is applied with a High, signal SAE turns off PMOS transistors150and170, but turns on NMOS transistors160and180. Transistors150and170being off, act as open circuits. Transistors160and180being on, act as short circuits and enable sensing by transistors110,130,120, and140. In some embodiments, transistors150and170are turned on for compensation. In other words, sense amplifier105operates in the compensation mode. Transistors160and180are then turned on to enable sensing by sense amplifier105. In other words, sense amplifier105operates in the sensing mode.

Such explanation of operation of transistors150,160,170and180are simplified for explanation purposes. In reality whether each of transistors150,160,170and180is open or closed depends on the corresponding voltages VGS and VGD rather than on only gate voltage provided by signal SAE. Voltage VGS is the voltage dropped across a gate and a source, while voltage VGD is the voltage dropped across a gate and a drain, of a transistor.

Exemplary Compensation Mode

FIG. 2is a circuit200illustrating sense amplifier105operating in the compensation mode.

In circuit200, signal SAE is applied with a Low. As a result, because signal SAE at the gates of NMOS transistors160and180are Low, NMOS transistors160and180are turned off, and act as open circuits. For illustration, transistors160and180are not drawn. At the same time, signal SAE at the gate of PMOS transistors150and170are also Low. PMOS transistors150and170are turned on, and act as short circuits. Transistor150is shown as a line coupling the gate of transistor120with signal SN. Similarly, transistor170is shown as a line coupling the gate of transistor140with signal SN. Effectively, the gate and the source of transistor120are coupled together, and the gate and the source of transistors140are coupled together.

Because the gate and the source of transistor120are coupled together, transistor120functions as a MOS diode. Similarly, because the gate and the source of transistor140are coupled together, transistor140also functions as a MOS diode.

Exemplary Sensing Mode

FIG. 3is a circuit300illustrating sense amplifier105operating in the sensing mode, in accordance with some embodiments.

In circuit300, signal SAE is applied with a High. Because signal SAE at the gates of PMOS transistors150and170are High, PMOS transistors150and170are turned off, and act as open circuits. For illustration, transistors150and170are not drawn. At the same time, because signal SAE at the gate of NMOS transistors160and180are High, NMOS transistors160and180are turned on, and act as short circuits. Transistor160is shown as a line coupling the gate of transistor NMOS120with the gate of PMOS transistor110. Similarly, transistor180is shown as a line coupling the gate of NMOS transistor140with the gate of PMOS transistor130.

Persons of ordinary skill in the art will recognize that transistors110and120, and130and140as drawn inFIG. 3are commonly known cross-coupled. The gates of transistors110and120are coupled together, and coupled to the drains of transistors130and140, and bit line ZBL. Similarly, the gates of transistors130and140are coupled together, and coupled to the drains of transistors110and120, and bit line BL.

In some embodiments, sense amplifier105operates in the compensation mode as illustrated in circuit200before operates in the sensing mode as in circuit300.

Mathematical Calculations

For illustration, voltage VtN120is the threshold voltage of NMOS transistor120. Voltage VtN140is the threshold voltage of NMOS transistor140. Further, voltage VtN140is less than VtN120. Voltage ΔV is the voltage difference between voltage VtN120and VtN140. In other words, ΔV=VtN120−VtN140. Voltages VBL and VZBL are the voltages on respective bit lines BL and ZBL. Currents1120and1140are the saturation currents flowing through respective transistors120and140. Voltages VGS120and VGS140are the voltages across the gate and the source of transistors120and140, respectively. β is transconductance coefficient of each of transistors120and140.

Because voltage VtN140is less than voltage VtN120, current IDS140is greater than current IDS120.

After the compensation, i.e., after amplifier105operates as circuit200inFIG. 2:
VBL=VZBL+(VtN120−VtN140)
When sense amplifier105operates in the sensing mode as in circuit300inFIG. 3:

VGS⁢⁢120=VGS⁢⁢140+Δ⁢⁢V=VGS⁢⁢140+(VtN⁢⁢120-VtN⁢⁢140)
As a result,

In other words, the difference or mismatch between transistors120and140has been compensated.

Exemplary Method and Corresponding Waveforms

FIG. 4is a method400illustrating an operation of circuit100, in accordance with some embodiments.FIG. 5is a graph of waveforms corresponding to the steps of method400inFIG. 4.

InFIG. 5, unless otherwise stated, the Low and the High of the waveforms for the corresponding signals other than word line WL are respective voltages VSS and VDD. The Low and the High of word line WL are at respective −0.4 V and 1.3×VDD. Dashed lines of the waveforms denote that the corresponding nodes are not driven, but the corresponding signals react to the operation of other signals and/or circuits.

Before time t4and after time t7, word line WL is driven Low. Memory cell195is not accessed for reading. In between times t4and t7, word line WL is driven High. Memory cell195is accessed for reading.

In step405at time t1, sense amplifier105is put in the charging state. Word line WL is driven Low, electrically disconnecting memory cell195from bit line BL and sense amplifier105. Signal SAE is driven High. Signals SN and SP are driven Low to turn off sense amplifier105. Signal EQ is driven High to charge and equalize bit lines BL and ZBL to voltage VSS at the drains of transistors125and135.

In step410at time t2, signal EQ is driven Low to stop charging and equalizing bit lines BL and ZBL. In some embodiments, signal EQ being Low also turns off the drivers for signals SP and SN. As a result, signals SP and SN are floating. Signal EQ remains Low during until signal EQ is driven High after time t7.

A the same time t2, signal SAE is driven Low, causing circuit100to operate in the compensation mode as illustrated by circuit200. Transistors120and140function as MOS diodes.

Additionally, signal SN is driven High to voltage VDD. Signal SP thus follows signal SN. Bit line BL at the source of transistor120and bit line ZBL at the source of transistor140charge towards a High through respective transistors120and140functioning as MOS diodes. Because of the threshold voltage difference in transistors120and140, bit line BL and bit line ZBL are charged to different voltage levels. For illustration purposes, threshold voltage VtN140is less than threshold voltage VtN120. As a result, bit line ZBL is charged to a level higher than bit line BL.

In step415at time t3, after bit line BL and bit line ZBL are charged to about 0.5×VDD, driving signal SN is released. Between times t3and t4, bit lines BL and ZBL remain at about 0.5×VDD. Signals SN and SP, however, drift towards 0.5 xVDD level where bit lines BL and ZBL are at the moment.

In step420at time t4, after both signals SN and SP reach 0.5 xVDD, signal SAE is applied with a High. Circuit100operates in the sensing mode as shown inFIG. 3.

At this time,
VGS120=VGS140+(VtN120−VtN140)

In effect, transistor120having threshold voltage VtN120higher than threshold voltage VtN140of transistor140has voltage VGS120higher than voltage VGS140of transistor140. Further, currents IDS120and IDS140are equalized as explained above. As a result, the difference in threshold voltage of transistors120and140has been compensated.

In step425at about or soon after time t4, word line WL is applied with a High. Transistor190is turned on. Memory cell195is electrically coupled to bit line BL. Depending on the data stored in memory cell195, bit line BL is pulled up or down whereas bit line ZBL is not driven and remains at the previous level. Stated differently, a bit line split between bit line BL and bit line ZBL develops. For illustration purposes, bit line BL is pulled towards a High, while bit line ZBL remains at the level close to −0.5×VDD.

In step430at time t5, when the bit line split is sufficient for sense amplifier105to sense the bit line split or, alternatively stated, to sense the data, signal SN is driven with a Low and then signal SP is driven with a High to turn on sense amplifier105. The bit line split therefore further develops.

In step435at time t6, the bit line split has been developed to a full swing. In other words, bit line BL has reached voltage VDD, and bit line ZBL has reached voltage VSS. Detecting the voltage levels on bit lines BL and ZBL reveals the data stored in memory cell195.

In step440at time t7, word line WL is applied with a Low to electrically disconnect memory cell195from bit line BL. Soon after time t7, signal SP is driven Low, which, together with signal SN being Low, turns off sense amplifier105. Signal EQ is driven High, placing sense amplifier in a pre-charge mode similar to the time period between times t1and t2.

A number of embodiments have been described. It will nevertheless be understood that various modifications may be made without departing from the spirit and scope of the disclosure. For example, the various transistors being shown as a particular dopant type (e.g., N-type or P-type Metal Oxide Semiconductor (NMOS or PMOS)) are for illustration purposes, embodiments of the disclosure are not limited to a particular type. Selecting different dopant types for a particular transistor is within the scope of various embodiments. The low or high logic level (e.g., Low or High) of the various signals used in the above description is also for illustration purposes. Various embodiments are not limited to a particular level when a signal is activated and/or deactivated. Selecting different levels is within the scope of various embodiments.

Some embodiments regard a sense amplifier. The sense amplifier comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a control signal line, a first supply voltage node, a second supply voltage node, a first data line, and a second data line. The first PMOS transistor has a first PMOS drain, a first PMOS source, and a first PMOS gate. The second PMOS transistor has a second PMOS drain, a second PMOS source, and a second PMOS gate. The third PMOS transistor has a third PMOS drain, a third PMOS source, and a third PMOS gate. The fourth PMOS transistor has a fourth PMOS drain, a fourth PMOS source, and a fourth PMOS gate. The first NMOS transistor has a first NMOS drain, a first NMOS source, and a first NMOS gate. The second NMOS transistor has a second NMOS drain, a second NMOS source, and a second NMOS gate. The third NMOS transistor has a third NMOS drain, a third NMOS source, and a third NMOS gate. The fourth NMOS transistor has a fourth NMOS drain, a fourth NMOS source, and a fourth NMOS gate. The first PMOS source, the second PMOS source, and the second supply voltage node are coupled together. The first NMOS source, the third PMOS source, the fourth PMOS source, the second NMOS source, and the first supply voltage node are coupled together. The third NMOS gate, the fourth NMOS gate, the third PMOS gate, and the fourth PMOS gate are coupled together and to the control signal line. The first data line, the first PMOS drain, the first NMOS drain, the fourth NMOS drain, and the second PMOS gate are coupled together. The second data line, the second PMOS drain, the second NMOS drain, the third NMOS drain, and the first PMOS gate are coupled together. The first NMOS gate, the third NMOS source, and the third PMOS drain are coupled together. The second NMOS gate, the fourth NMOS source, and the fourth PMOS drain are coupled together

Some embodiments regard a method. The method drives a first data line, a second data line, a first supply signal, and a second supply signal to a low logic value. The method stops driving the first data line, the second data line, the first supply signal, and the second supply signal. The method drives the first supply signal to a high logic value. A first voltage value of the first data line and a second voltage value of the second data line thereby rise. The method stops driving the first supply signal after the first voltage value and/or the second voltage value rises to a predetermined value. The first supply signal and the second supply signal thereby change towards the predetermined voltage value. The method electrically couples a memory cell to the first data line or the second data line. The method drives the first supply signal to the data low logic value and the second supply signal to the high logic value. The method detects the data value stored in the memory cell based on voltage levels on the first and the second data line.

Some embodiments regard a method. The method drives high a first signal and a second signal. The method drives low the first signal and the second signal. The second signal being low turns off a first NMOS transistor and a second NMOS transistor and turns on a first PMOS transistor and a second PMOS transistor. The method drives high a first supply signal. The method stops driving high the first supply signal. The method drives high the second signal to turn on the first NMOS transistor and the second NMOS transistor, and turn off the first PMOS transistor and the second PMOS transistor. The method electrically couples a memory cell to a first data line or a second data line. The method drives low the first supply signal and drives high a second supply signal. The first NMOS transistor is coupled between gates of a third PMOS transistor and a third NMOS transistor. The second NMOS transistor is coupled between gates of a fourth PMOS transistor and a fourth NMOS transistor. The first PMOS transistor is coupled between a gate of the third NMOS transistor and the first supply signal. The second PMOS transistor is coupled between a gate of the fourth NMOS transistor and the first supply signal.

The above methods show exemplary steps, but they are not necessarily performed in the order shown. Steps may be added, replaced, changed order, and/or eliminated as appropriate, in accordance with the spirit and scope of disclosed embodiments.