Method and structure for enhancing both nMOSFET and pMOSFET performance with a stressed film

A structure and method for making includes adjacent pMOSFET and nMOSFET devices in which the gate stacks are each overlain by a stressing layer that provides compressive stress in the channel of the pMOSFET device and tensile stress in the channel of the nMOSFET device. One of the pMOSFET or nMOSFET device has a height shorter than that of the other adjacent device, and the shorter of the two devices is delineated by a discontinuity or opening in the stressing layer overlying the shorter device. In a preferred method for forming the devices a single stressing layer is formed over gate stacks having different heights to form a first type stress in the substrate under the gate stacks, and forming an opening in the stressing layer at a distance from the shorter gate stack so that a second type stress is formed under the shorter gate stack.

SUMMARY

The foregoing discussed drawbacks and deficiencies of the prior art are overcome or alleviated by a method for forming a single stress liner for a complementary metal oxide semiconductor (CMOS) device. In an exemplary embodiment, the method includes: 1) forming a CMOS structure having an nMOSFET and pMOSFET with different gate heights (for example, the nMOSFET gate may be lower than the gate of the pMOSFET, or vice versa), 2) depositing a single stress liner of a either compressive or tensile stress over both the nMOSFET and pMOSFET; and 3) etching part of the stress liner close to the shorter of the gates to form stress of the opposite type in the channel of the shorter gate. For example, if a compressive stress liner is first formed, and the shorter gate is the nMOSFET, then etching part of the compress stress liner in proximity to the nMOSFET will result in tensile stress in the channel of the nMOSFET. If the shorter gate is the pMOSFET, then according to the invention, a tensile stress liner is deposited over both gates, and part of the stress liner is removed around the shorter pMOSFET, resulting in compressive stress in the channel of the pMOSFET.

DETAILED DESCRIPTION

Disclosed herein is a method and structure for improving CMOS device performance and reliability by using single stress silicon nitride liner for both nMOSFET and pMOSFET. Briefly stated, the embodiments disclosed herein result in compressive stress in the pMOSFET channel and tensile stress in the nMOSFET channel on the same chip or integrated circuit (IC) by using the same stressed film to cover both the pMOSFET and the nMOSFET. This results in performance enhancement due to local stress for both nMOSFET and pMOSFET, without causing misalignment problems.

Referring initially toFIG. 1, there is shown a cross sectional view of a semiconductor substrate100having an nMOSFET device region102and a pMOSFET device region104separated by an isolation region105formed therein, such as a shallow trench isolation (STI).

Referring toFIG. 2, a gate dielectric layer106is formed over the substrate100including the isolation region105. The gate dielectric106may be any suitable dielectric material, such as silicon dioxide. The gate dielectric106may be formed, for example, by thermal oxidation or deposition of a high K material. The gate dielectric106typically has a thickness in the range of about 1-2 nm. In accordance with the invention, a first layer of a gate conductor108is formed atop the gate dielectric layer106. The first gate conductor layer108may be any suitable gate conductor material such as polysilicon, W, Ta or SiGe, more typically polysilicon. For gate lengths of 35-45 nm, the polysilicon layer108is preferably 10-30 nm thick. A second gate conductor layer110having an etch rate different than the first gate conductor layer108, such as polysilicon-germanium (poly-SiGe), if the first conductor layer is polysilicon, is deposited atop the first gate conductor (e.g. polysilicon) layer108. For gate lengths of 35-45 nm, the poly-SiGe layer110is preferably 70-90 nm thick. Preferably, the second gate conductor layer110is thicker than the first conductor layer108.

Referring toFIG. 3, devices102,104are formed by processes now known or developed in the future. For example, the gate stacks may be formed by patterned etching, formation of spacers including optional thin oxide liners112and nitride spacers114, and implantation to form source/drain halo regions and extensions116, followed by source/drain anneal, as will be recognized by one skilled in the art.

Referring toFIG. 4, the pMOSFET104is covered by a mask such as photo resist layer126. Then, the second gate conductor layer110, e.g. the poly-SiGe layer, is removed from the first gate conductor layer108in the nMOSFET102, for example, by an etch process selective to silicon, poly Is, oxide and nitride. Then the exposed oxide liner112above the first gate conductor108is removed from the sidewalls114of the nMOSFET102, for example, using a process such as buffered HF (BHF). Etch time will depend on the thickness of the oxide liner112. Since the oxide liner112is very thin, for example, on the order of about 5-10 nm, there will be no significant damage to the isolation region105.

Referring toFIG. 5, the photo resist126is removed. Then, a metal layer is deposited over the structure. For example, in a preferred embodiment, nickel is deposited at a thickness between about 3-20 nm, sufficient to fully silicide the polysilicon layer108in the nMOSFET gate stack102. After an anneal, for example, at 300-500° C. at 1-60 seconds, a semiconductor metal alloy is formed from the metal and the silicon of the nMOSFET gate stack102, the silicon of the substrate100, and the SiGe of the pMOSFET gate stack104. The resulting structure includes silicide regions120over the source/drain regions116, a fully silicided gate conductor122in the nMOSFET102, and a silicided top portion124of the pMOSFET104.

Next, referring toFIG. 6, the nitride spacers114are etched back, for example by a wet etch or dry etch process, so that the nitride spacers114have substantially the same height as the silicided gate conductor122and oxide liner112of the nMOSFET102, resulting in an nMOSFET gate stack102that is shorter in height than the pMOSFET gate stack104. Since a wet etch process is isotropic, the nitride spacers114on the pMOSFET104will be thinned. Preferably, the nitride spacers114are thinned no more than about half its original thickness.

Referring toFIG. 7, a compressive nitride film130is deposited over the structure. The thickness of the compressive nitride film is preferably in the range 40-100 nm. The compressive nitride material130may be formed by high density plasma (HDP) deposition or plasma enhanced CVD (PECVD), for example, SiH4/NH3/N2at about 200° C. to about 500° C. This results in compressive stress being generated in the channels182,184of the nMOSFET and pMOSFET regions102,104, respectively (seeFIG. 8).

Next, referring toFIG. 8, a thin etch stop layer132, such as an oxide, for example, about 50-100 angstroms thick, is formed atop the compressive nitride layer130. Then, a photo resist material146is formed over the structure and thereafter patterned so as to form openings148in the resist146that expose the surface of the thin oxide132on at least opposite sides of the nMOSFET102over the source/drain regions116, which will be used to pattern openings158in the compressive nitride layer130(seeFIG. 10). For a sufficiently narrow width device, forming the opening158completely around the perimeter of the gate122in the compressive layer130may enhance device performance. However, for a wide width device, the additional benefit caused by surrounding the device by openings158is small, and it would be sufficient to form openings158on opposite sides of the shorter device102. The exposed portion of the thin oxide layer132above the nMOSFET device102is removed to form openings151in the thin oxide132, using a process such as by RIE for example, stopping on the compressive nitride layer130. Then the resist layer146is removed. The resulting structure is illustrated inFIG. 9.

Next, the compressive nitride layer130is removed, for example, by an isotropic or wet etch, where the openings151in the thin oxide132has been formed over the source/drain regions116of the nMOSFET device102, to form openings158so that an inner edge159of the opening158is at a horizontal distance Lcut from the outer edge of the gate conductor122, so that the stress of the channel region182of the nMOSFET device102is modified to become tensile stress. The resulting structure is illustrated inFIG. 10. It is noted that the width of the opening158may be from about 30 nm to about 100 nm, but is not critical, and that the edge of the opening158away from the gate stack may extend as far as the isolation region105.

The preferred horizontal distance Lcut of the opening158from the gate conductor122is preferably selected so as to optimize the resulting stress in the channel region182. This optimal distance LMaxcan be determined, for example, by simulating the stress at the center183of the channel region182for a range of expected gate structures similar to that of nMOSFET device102, but varying the Lcut distance, and then determining the position of Lcut (i.e. LMax) to be such that the channel stress is the maximized, as illustrated inFIG. 11. For the case of a pMOSFET that is shorter than the nMOSFET, the initial stressing layer130is tensile, and the value of Lcut is preferably chosen at LMaxto maximize the compressive stress in the pMOSFET channel.

Next, a nitride film162having substantially neutral stress, or substantially without a large stress component is deposited over the structure, for example, by chemical vapor deposition (CVD) or high density plasma (HDP), so that the openings158are filled in the compressive nitride layer130, as illustrated inFIG. 12. Preferably the thickness of the neutral stress layer162should be greater than ½ of the width of the opening158. Then the neutral stress layer162is etched back to a surface that is substantially level with the surface of the thin oxide layer132, as illustrated inFIG. 13. Subsequently, the nMOSFET device102and pMOSFET device104may be completed as known by one skilled in the art.