CYCLIC REDUNDANCY CHECK COMPARISON FOR ERROR DETECTION

Methods, systems, and devices for cyclic redundancy check (CRC) comparison for error detection are described. A host system may determine an error cause associated with writing data to or reading data from a memory system. For writing data, the host system may transmit data and a CRC value to the memory system. The memory system may calculate another CRC value and indicate an error and the calculated CRC value based on the received and calculated CRC values being different. The host system may compare the calculated CRC value and the originally transmitted CRC value to determine an error cause. For reading data, the host system may receive data and an associated CRC value from the memory system, calculate a CRC value using the received data, and determine an error cause based on a comparison of the received CRC value, the calculated CRC, and an expected CRC value.

TECHNICAL FIELD

The following relates to one or more systems for memory, including cyclic redundancy check (CRC) comparison for error detection.

BACKGROUND

Memory devices are used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within a memory device to various states. For example, binary memory cells may be programmed to one of two supported states, often denoted by a logic 1 or a logic 0. In some examples, a single memory cell may support more than two states, any one of which may be stored by the memory cell. To store information, a memory device may write (e.g., program, set, assign) states to the memory cells. To access stored information, a memory device may read (e.g., sense, detect, retrieve, determine) states from the memory cells.

DETAILED DESCRIPTION

Some systems may utilize cyclic redundancy checks (CRCs) to detect errors in data. For example, CRC values may be calculated based on data, and CRC values calculated using the same data may be the same. Thus, a difference in CRC values may indicate an error in the data and that may result from the transmission, storage, or retrieval of the data and/or an error associated with the transmission of a CRC value. For example, a host system may calculate a CRC value associated with data and may transmit the data and the associated CRC value to a memory system. After receiving the data and the CRC value, the memory system may calculate another CRC value using the received data (e.g., before storage of the data, after storage and retrieval of the data). The memory system may compare the memory system-calculated CRC value to the CRC value received from the host system. In the case that the received CRC value and the memory system-calculated CRC value do not match, the memory system may transmit an error flag to the host system indicating an error, which may be referred to as a CRC error. However, while it may be beneficial for the memory system to indicate the detected error to the host system, neither the memory system nor the host system may determine where in the data transmission, storage, or retrieval, or in the CRC transmission, the error may have occurred, which may result in further errors and/or ineffective or inefficient error correction techniques.

In accordance with examples described herein, a memory system and a host system may support determination of one or more causes of a CRC error based on a comparison of CRC values associated with data, which may support the implementation of efficient and effect corrective actions. For example, the host system and the memory system may support determining the cause of errors associated with writing data to the memory system. To support such determination, the memory system may transmit the memory system-calculated CRC value to the host system in addition to the indication of the CRC error. The host system may utilize the CRC value originally transmitted to the memory system and the memory system-calculated CRC value received from the memory system to determine a cause of the error at a more granular level. For example, the originally transmitted CRC value and the memory system-calculated CRC value being different may indicate that the error is associated with at least the transmission, storage, or retrieval of the data. The originally transmitted CRC value and the memory system-calculated CRC value being different may indicate that the error is associated with the transmission of the original CRC value from the host system to the memory system.

Additionally, or alternatively, the host system may support determining the cause of errors associated with reading data from the memory system. For example, the host system may transmit a command to read data from the memory system. In accordance with the command, the memory system may calculate a CRC value associated with the requested data and transmit the data and the CRC value to the host system. The host system may receive the data and the CRC value, and may calculate another CRC value using the received data. The host system may compare the CRC value calculated from the received data to both the CRC value received from the memory system and an expected CRC value (e.g., a CRC value associated with data that the host system expects to receive from the memory system) to determine one or more causes of a CRC error. For example, as described herein, the comparison of the CRC values may indicate whether a CRC error is associated with the transmission of the CRC value by the memory system or associated with the data prior to or after the calculation of the CRC value. By implementing error cause determination techniques described herein, error causes may be determined at a more granular level, which may support relatively more efficient and effective error correction techniques to support improved performance of the memory system, among other benefits.

Features of the disclosure are illustrated and described in the context of systems and architectures. Features of the disclosure are further illustrated and described in the context of block diagrams and flowcharts.

FIG.1illustrates an example of a system100that supports CRC comparison for error detection in accordance with examples as disclosed herein. The system100may include portions of an electronic device, such as a computing device, a mobile computing device, a wireless communications device, a graphics processing device, a vehicle, a smartphone, a wearable device, an internet-connected device, a vehicle controller, a system on a chip (SoC), or other stationary or portable electronic system, among other examples. The system100includes a host system105, a memory system110, and one or more channels115coupling the host system105with the memory system110(e.g., to support a communicative coupling). The system100may include any quantity of one or more memory systems110coupled with the host system105.

The host system105may include one or more components (e.g., circuitry, processing circuitry, one or more processing components) that use memory to execute processes, any one or more of which may be referred to as or be included in a processor125. The processor125may include at least one of one or more processing elements that may be co-located or distributed, including a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, a controller, discrete gate or transistor logic, one or more discrete hardware components, or a combination thereof. The processor125may be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose GPU (GPGPU), or an SoC or a component thereof, among other examples.

The host system105may also include at least one of one or more components (e.g., circuitry, logic, instructions) that implement the functions of an external memory controller (e.g., a host system memory controller), which may be referred to as or be included in a host system controller120. For example, a host system controller120may issue commands or other signaling for operating the memory system110, such as write commands, read commands, configuration signaling or other operational signaling. In some examples, the host system controller120, or associated functions described herein, may be implemented by or be part of the processor125. For example, a host system controller120may be hardware, instructions (e.g., software, firmware), or some combination thereof implemented by the processor125or other component of the host system105. In various examples, a host system105or a host system controller120may be referred to as a host.

The memory system110provides physical memory locations (e.g., addresses) that may be used or referenced by the system100. The memory system110may include a memory system controller140and one or more memory devices145(e.g., memory packages, memory dies, memory chips) operable to store data. The memory system110may be configurable for operations with different types of host systems105, and may respond to commands from the host system105(e.g., from a host system controller120). For example, the memory system110(e.g., a memory system controller140) may receive a write command indicating that the memory system110is to store data received from the host system105, or receive a read command indicating that the memory system110is to provide data stored in a memory device145to the host system105, or receive a refresh command indicating that the memory system110is to refresh data stored in a memory device145, among other types of commands and operations.

A memory system controller140may include at least one of one or more components (e.g., circuitry, logic, instructions) operable to control operations of the memory system110. A memory system controller140may include hardware or instructions that support the memory system110performing various operations, and may be operable to receive, transmit, or respond to commands, data, or control information related to operations of the memory system110. A memory system controller140may be operable to communicate with one or more of a host system controller120, one or more memory devices145, or a processor125. In some examples, a memory system controller140may control operations of the memory system110in cooperation with the host system controller120, a local controller150of a memory device145, or any combination thereof. Although the example of memory system controller140is illustrated as a separate component of the memory system110, in some examples, aspects of the functionality of the memory system110may be implemented by a processor125, a host system controller120, at least one of one or more local controllers150, or any combination thereof.

Each memory device145may include a local controller150and one or more memory arrays155. A memory array155may be a collection of memory cells (e.g., a two-dimensional array, a three-dimensional array), with each memory cell being operable to store data (e.g., as one or more stored bits). Each memory array155may include memory cells of various architectures, such as random access memory (RAM) cells, dynamic RAM (DRAM) cells, synchronous dynamic RAM (SDRAM) cells, static RAM (SRAM) cells, ferroelectric RAM (FeRAM) cells, magnetic RAM (MRAM) cells, resistive RAM (RRAM) cells, phase change memory (PCM) cells, chalcogenide memory cells, not-or (NOR) memory cells, and not-and (NAND) memory cells, or any combination thereof.

A local controller150may include at least one of one or more components (e.g., circuitry, logic, instructions) operable to control operations of a memory device145. In some examples, a local controller150may be operable to communicate (e.g., receive or transmit data or commands or both) with a memory system controller140. In some examples, a memory system110may not include a memory system controller140, and a local controller150or a host system controller120may perform functions of a memory system controller140described herein. In some examples, a local controller150, or a memory system controller140, or both may include decoding components operable for accessing addresses of a memory array155, sense components for sensing states of memory cells of a memory array155, write components for writing states to memory cells of a memory array155, or various other components operable for supporting described operations of a memory system110.

A host system105(e.g., a host system controller120) and a memory system110(e.g., a memory system controller140) may communicate information (e.g., data, commands, control information, configuration information) using one or more channels115. Each channel115may be an example of a transmission medium that carries information, and each channel115may include one or more signal paths (e.g., a transmission medium, an electrical conductor, a conductive path) between terminals (e.g., nodes, pins, contacts) associated with the components of the system100. A terminal may be an example of a conductive input or output point of a device of the system100, and a terminal may be operable as part of a channel115. To support communications over channels115, a host system105(e.g., a host system controller120) and a memory system110(e.g., a memory system controller140) may include receivers (e.g., latches) for receiving signals, transmitters (e.g., drivers) for transmitting signals, decoders for decoding or demodulating received signals, or encoders for encoding or modulating signals to be transmitted, among other components that support signaling over channels115, which may be included in a respective interface portion of the respective system.

A channel115be dedicated to communicating one or more types of information, and channels115may include unidirectional channels, bidirectional channels, or both. For example, the channels115may include one or more command/address channels, one or more clock signal channels, one or more data channels, among other channels or combinations thereof. In some examples, a channel115may be configured to provide power from one system to another (e.g., from the host system105to the memory system110, in accordance with a regulated voltage). In some examples, at least a subset of channels115may be configured in accordance with a protocol (e.g., a logical protocol, a communications protocol, an operational protocol, an industry standard), which may support configured operations of and interactions between a host system105and a memory system110.

A command/address channel (e.g., a CA channel) may be operable to communicate commands between the host system105and the memory system110, including control information associated with the commands (e.g., address information, configuration information). Commands carried by a command/address channel may include a write command with an address for data to be written to the memory system110or a read command with an address of data to be read from the memory system110.

A clock signal channel may be operable to communicate one or more clock signals between the host system105and the memory system110. Clock signals may oscillate between a high state and a low state, and may support coordination (e.g., in time) between operations of the host system105and the memory system110. In some examples, a clock signal may provide a timing reference for operations of the memory system110. A clock signal may be referred to as a control clock signal, a command clock signal, or a system clock signal. A system clock signal may be generated by a system clock, which may include one or more hardware components (e.g., oscillators, crystals, logic gates, transistors).

A data channel160(e.g., a DQ channel) may be operable to communicate (e.g., bidirectionally) information (e.g., data170, control information) between the host system105and the memory system110. For example, a data channel may communicate information from the host system105to be written to the memory system110, or information read from the memory system110to the host system105. In some examples, channels115may include one or more error detection code (EDC) channels165. An EDC channel165may be operable to communicate error detection signals, such as one or more CRC values175, checksums, or parity bits, which may accompany information conveyed over a data channel. In some examples, an EDC channel165may be an example of a DQE channel, which may be operable to communicate error detection signals and may be additionally or alternatively operable to communicate one or more data symbols, severity (SEV) information, poison (PSN) information, or a combination thereof.

In accordance with examples described herein, the memory system110and the host system105may be configured to determine one or more causes of a CRC error based on the comparison of CRC values175associated with the data170, which may support the implementation of efficient and effect corrective actions. The host system105may be configured to determine the cause of CRC errors associated with writing data170to the memory system110. For example, the host system105may transmit data170and an associated CRC value175(e.g., via the data channel160and EDC channel165, respectively) to the memory system110. The memory system110may store the data170and may calculate another CRC value175using the data170received from the host system105(e.g., the stored data170). The memory system110may compare the CRC value175received from the host system105(e.g., which may be different than the CRC value175originally transmitted by the host system105, such as based on an error associated with the transmission of the CRC value175via the EDC channel165) and the calculated CRC value175. In the case that the two CRC values are not the same, the memory system110may transmit an indication of a CRC error to the host system105. Based on the CRC error, the memory system110may transmit the calculated CRC value175to the host system105. The host system105may compare the CRC value175originally transmitted to the memory system110and the calculated CRC value175received from the memory system110to determine a cause of the error at a more granular level. For example, the originally transmitted CRC value175and the calculated CRC value175being different may indicate that the error is associated with at least the transmission, storage, or retrieval of the data170. The originally transmitted CRC value175and the calculated CRC value175being different may indicate that the error is associated with the transmission of the original CRC value175via the EDC channel165.

Additionally, or alternatively, the host system105may be configured to determine the cause of errors associated with reading data from the memory system110. For example, the host system105may transmit a command to read data170from the memory system110. In accordance with the command, the memory system110may calculate a CRC value175associated with the requested data170and transmit the data170and the CRC value175to the host system105(e.g., via the data channel160and the EDC channel165, respectively). The host system105may receive the data170and the calculated CRC value175and may calculate another CRC value175using the received data170. The host system105may compare the CRC value175calculated from the received data170, the CRC value175received from the memory system110, and an expected CRC value175(e.g., a CRC value175associated with data170the host system105expects to receive from the memory system110) to determine one or more causes of a CRC error. For example, the comparison of the CRC values may indicate whether a CRC error is associated with the transmission of the CRC value by the memory system or associated with the data prior to or after the calculation of the CRC value. By implementing error cause determination techniques described herein, error causes may be determined at a more granular level, which may support relatively more efficient and effective error correction techniques to support improved performance of the memory system, among other benefits.

In addition to applicability in systems as described herein, techniques for error detection utilizing CRC comparisons may be generally implemented to improve the performance (including gaming) of various electronic devices and systems. Some electronic device applications, including gaming and other high-performance applications, may be associated with relatively high processing requirements while also benefitting from relatively quick response times to improve user experience. As such, increasing processing speed, decreasing response times, or otherwise improving the performance electronic devices may be desirable. Implementing the techniques described herein may improve the performance of electronic devices by improving error detection and correction techniques, which may reduce error occurrence, which may improve memory access speeds, decrease processing or latency times, improve response times, or otherwise improve user experience, among other benefits.

FIG.2illustrates an example of an architecture200(e.g., a memory architecture) that supports CRC comparison for error detection in accordance with examples as disclosed herein. The architecture200may be implemented in a memory system110or one or more components thereof (e.g., memory device145). Aspects of the architecture200may be referred to as or implemented in a semiconductor component, such as a memory die.

The architecture200includes memory cells205that are programmable to store information. In some examples, a memory cell205may be operable to store one bit of information at a time (e.g., a logic0or a logic1). In some examples, a memory cell205(e.g., a multi-level memory cell) may be operable to store more than one bit of information at a time (e.g., a logic 00, logic 01, logic 10, a logic 11). Memory cells205may be arranged in an array, such as in a memory array155.

In the example of architecture200, a memory cell205may include a storage component, such as capacitor230, and a selection component235(e.g., a cell selection component, a transistor). A capacitor230may be a dielectric capacitor or a ferroelectric capacitor. A node of the capacitor230may be coupled with a voltage source240, which may be a cell plate reference voltage, such as Vpl, or may be a ground voltage, such as Vss. A charge stored by a memory cell205(e.g., by a capacitor230) may be representative of a programmed state. Other memory architectures that support the techniques described herein may implement different types or arrangements of storage components and associated circuitry (e.g., with or without a selection component).

The architecture200may include various arrangements of access lines, such as word lines210and digit lines215. An access line may be a conductive line that is coupled with a memory cell205, and may be used to perform access operations on the memory cell205. Word lines210may be referred to as row lines, and digit lines215may be referred to as column lines or bit lines, among other nomenclature. Memory cells205may be positioned at intersections of access lines, and an intersection may be referred to as an address of a memory cell205.

In some architectures, a word line210may be coupled with a gate of a selection component235of a memory cell205, and may be operable to control (e.g., switch, modulate a conductivity of) the selection component235. A digit line215may be operable to couple a memory cell205with a sense component245. In some architectures, a memory cell205(e.g., a capacitor230) may be coupled with a digit line215during portions of an access operation. For example, a word line210and a selection component235of a memory cell205may be operable to couple or isolate a capacitor230of the memory cell205with a digit line215.

Operations such as reading and writing may be performed on memory cells205by activating (e.g., applying a voltage to) access lines such as a word line210or a digit line215. Accessing the memory cells205may be controlled through a row decoder220, or a column decoder225, or a combination thereof. For example, a row decoder220may receive a row address (e.g., from a local memory controller260) and activate a word line210based on a received row address, and a column decoder225may receive a column address and activate a digit line215based on a received column address. Selecting or deselecting a memory cell205may include activating or deactivating a selection component235using a word line210. For example, a capacitor230may be isolated from a digit line215when the selection component235is deactivated, and the capacitor230may be coupled with the digit line215when the selection component235is activated.

A sense component245may be operable to detect a state (e.g., a charge) stored by a capacitor230of a memory cell205and determine a logic state of the memory cell205based on the stored state. A sense component245may include one or more sense amplifiers to amplify or otherwise convert a signal resulting from accessing the memory cell205. The sense component245may compare a signal detected from the memory cell205with a reference250(e.g., a reference voltage). The detected logic state of the memory cell205may be provided as an output of the sense component245(e.g., via an input/output255), and may indicate the detected logic state to another component of a memory system110that implements the architecture200.

The local memory controller260may control the accessing of memory cells205through the various components (e.g., a row decoder220, a column decoder225, a sense component245), and may be an example of or otherwise included in a local controller150, or a memory system controller140, or both. In some examples, one or more of a row decoder220, a column decoder225, and a sense component245may be co-located with or included in the local memory controller260. The local memory controller260may be operable to receive commands or data from one or more different controllers (e.g., a host system controller120, a memory system controller140), translate the commands or the data into information that can be used by the architecture200, initiate or control one or more operations of the architecture200, and communicate data from the architecture200to a host (e.g., a host system105) based on performing the one or more operations.

The local memory controller260may be operable to perform one or more access operations on one or more memory cells205of the architecture200. Examples of an access operation may include a write operation, a read operation, a refresh operation, a precharge operation, or an activate operation, among others. In some examples, an access operation may be performed by or otherwise coordinated by the local memory controller260in response to one or more access commands (e.g., from a host system105). The local memory controller260may be operable to perform other access operations not listed here or other operations related to the operating of the architecture200that are not directly related to accessing the memory cells205.

In accordance with examples described herein, a memory system (e.g., that implements the architecture200) and a host system may be configured to determine one or more causes of CRC errors based on a comparison of CRC values270associated with data265, which may support the implementation of efficient and effect corrective actions. The host system may be configured to determine the cause of errors associated with writing the data265to the memory system. For example, the host system may transmit the data265and an associated CRC value270to the memory system. The memory system may store the data265and may calculate another CRC value270using the stored data265. The memory system may compare the received CRC value270and the calculated CRC value270and, in the case that the two CRC values are not the same, may transmit an indication of a CRC error and the calculated CRC value270to the host system. The host system may utilize the CRC value270originally transmitted to the memory system and the calculated CRC value270received from the memory system to determine a cause of the error at a more granular level, such as occurring on an EDC channel or resulting from the transmission, storage, or retrieval of the data265.

Additionally, or alternatively, the host system may be configured to determine the cause of errors associated with reading the data265from the memory system. For example, the memory system may calculate a CRC value270associated with data265requested by the host system and transmit the data265and the CRC value270to the host system. The host system may receive the data265and the CRC value270and may calculate another CRC value270using the received data265. The host system may compare the CRC value270calculated from the received data265with the CRC value received from the memory system and an expected CRC value (e.g., a CRC value that may be associated with data the host system may expect from the memory system) to determine one or more causes of a CRC error.

FIG.3shows an example of a system300that supports CRC comparison for error detection in accordance with examples as disclosed herein. The system300may be implemented by aspects of a system100, an architecture200, or one or more components thereof (e.g., a host system105, a memory system110, a local memory controller260) as described with reference toFIGS.1and2, respectively. The system300may support relatively more granular determination of CRC error causes associated with writing data to a memory system.

The system300may include a host system305and a memory system310, which may be example of the corresponding systems described herein, including with reference toFIGS.1and2. The host system305may communicate with the memory system310via one or more channels, such as a CA channel312, one or more data channels315(e.g., one or more DQ channels), and an EDC channel320(e.g., a DQE channel), which may be examples of the channels described with reference toFIG.1. Additionally, although non-limiting examples of the system300herein are generally described in terms of applicability to memory systems, memory sub-systems, memory devices, or a combination thereof, examples of the system300are not so limited. For example, aspects of the present disclosure may be applied as well to any computing system, computing sub-system, processing system, processing sub-system, component, device, structure, or other types of systems or sub-systems used for applications such as data collecting, data processing, data storage, networking, communication, power, artificial intelligence, system-on-a-chip, control, telemetry, sensing and monitoring, digital entertainment, or any combination thereof.

The host system305and the memory system310may include components to support improved error causation determination techniques. For example, the host system305may include an error detector365that may compare one or more CRC values to determine the cause of CRC errors. The memory system310may include a CRC calculator335. The memory system310may input data330received from the host system305via the data channels315into the CRC calculator335, and the CRC calculator335may generate (e.g., calculate) a calculated CRC value340associated with (e.g., based on) the data330. In some examples, the calculated CRC value340(e.g., and one or more other CRC values) may be used to support error detection associated with the data330(e.g., resulting from the transmission of the data330, storage of the data330, retrieval of the stored data330) or with communication of a CRC value associated with the data330. For example, the memory system310may include an error detector355that may receive the calculated CRC value340and a CRC value350received from the host system305via the EDC channel320as inputs and may compare the calculated CRC value340to the received CRC value350to detect errors. In the case that the error detector355determine that the calculated CRC value340and the CRC value350may not match, the error detector355may indicate (e.g., output an indication of) a CRC error to the host system305.

In accordance with examples described herein, the host system305may compare CRC values associated with the data330to determine where a detected error may have occurred as part of a write operation. For example, the host system305may transmit data (e.g., the data330) and an associated CRC value (e.g., a CRC value370calculated using the data) to the memory system310. The host system305may transmit the data via the data channels315(e.g., the DQ pins, the DQ channels) and may transmit the CRC value370via the EDC channel320. The memory system310may receive the data and the CRC value. The data330may be the same as the data transmitted by the host system305, such as if there is no error associated with the transmission of the data to the memory system310(e.g., and/or storage of the data to or retrieval of the data from a memory array of the memory system). The data330may be different from the data transmitted by the host system305, such as if there is an error associated with the transmission (e.g., storage, and/or retrieval) of the data. Similarly, the CRC value350received from the host system305may be the same as the CRC value370transmitted by the host system, such as if there is no error associated with the transmission of the CRC value370via the EDC channel320. Alternatively, the CRC value350may be different from the CRC value370, such as if there is an error associated with the transmission of the CRC value370via the EDC channel320. In some examples, the memory system310may store the data received from the host system305to a memory array of the memory system310(e.g., and temporarily store the received CRC value350).

The memory system310may calculate a CRC value340based on the data330(e.g., which may correspond to the data received from the host system305or the data stored to and retrieved from the memory array of the memory system310) and may compare the CRC value340to the CRC value350. For example, the memory system310may input the data330into the CRC calculator335. The CRC calculator335may utilize the data330to generate the CRC value340. For example, the CRC calculator335may use a function that outputs the CRC value340using the data330as the input to the function. The memory system310may input the CRC value340and the CRC value350into the error detector355, and the error detector355may compare the CRC value340to the CRC value350. In the case that the CRC value340is not the same as (e.g., does not match) the CRC value350, one or more errors may have occurred prior to the comparison of the CRC values340and350, such as during transmission of the data via the data channels315, during storage of the data330to the memory array of the memory system310, during retrieval of the data from the memory array, during the transmission of the CRC value370via the EDC channel320, or a combination thereof.

The host system305and the memory system310may support the determination of where the one or more errors occurred at a more granular level. For example, in response to detecting a CRC error (e.g., that the CRC values340and350are different), the memory system310(e.g., the error detector355) may store the CRC value340to storage345of the memory system310. In some examples, the storage345may be temporary storage of the memory system310, a register of the memory system310, a cache of the memory system310, among other possible types of storage of the memory system310. Additionally, the memory system310may indicate the error to the host system305. For example, in response to detecting the error, the error detector355may transmit a CRC error flag360to the host system305indicating that the CRC values340and350are different (e.g., do not match). In some examples, if no CRC error is detected (e.g., the error detector355determines that the CRC values340and350are the same), no CRC error flag360is transmitted and the CRC value340may be discarded (e.g., the memory system310may refrain from storing the CRC value340). In some other examples, the CRC value340may be initially stored to the storage345prior to the error determination by the error detector355and discarded (e.g., deleted from the storage345) if no CRC error is detected.

The memory system310may transmit the CRC value340(e.g., the calculated CRC value) to the host system305. For example, in response to receiving the CRC error flag360, the host system305may transmit a command325to the memory system310via the CA channel312. The command325may request that the memory system310transmit the CRC value340(e.g., the CRC value stored to the storage345, the calculated CRC value) to the host system305. The memory system310may receive the command325and may transmit the CRC value340to the error detector365of the host system305in response. For example, in response to receiving the command, the memory system310may read the CRC value340from the storage345and may transmit the CRC value340to the host system305(e.g., from the storage345). Alternatively, the memory system310may transmit the CRC value340to the host system305in response to detecting the CRC error (e.g., determining that the CRC values340and350are different). For example, the memory system310may transmit the CRC value340to the host system305without receiving a command325in response to detecting the CRC error. In some examples, if the memory system310transmits the CRC value340in response to detecting the CRC error, the memory system310may refrain from storing the CRC value340to the storage345.

In some examples, the memory system310(e.g., the error detector355) may transmit the CRC value340to the host system305via one or more of the data channels315. In some other examples, the memory system310may transmit the CRC value340to the host system305via the EDC channel320and may utilize an interface (e.g., a serial interface). The memory system310may transmit the CRC value340to the host system305at a rate that is slower than the rate of the data transmission from the host system305to the memory system310, which may decrease the likelihood of errors associated with the transmission of the CRC value340to the host system305. For example, the memory system310may transmit the CRC value340to the host system305at a first rate that is slower than a second rate at which the data is received from the host system305and/or slower than a third rate at which the CRC value370is transmitted by the host system305.

The host system305may receive the CRC value340from the memory system310and may determine a type of the CRC error indicated by the CRC error flag360(e.g., a cause of the CRC error) based on whether the CRC value340is different than the CRC value originally transmitted to the memory system310(e.g., the CRC value370). For example, the error detector365of the host system305may receive the CRC value340and may compare the CRC value340to the CRC value370(e.g., the CRC value originally transmitted to the memory system310). In the case that the error detector365determines that the CRC value340is not the same as the CRC value370, the host system305(e.g., the error detector365) may determine that one or more errors may have occurred at least along a path of the data from the host system305to the CRC calculator335, such as part of the transmission of the data from the host system305to the memory system310via the data channels315, part of the storing of the data330to the memory array of the memory system310, part of the retrieval of the data330from the memory array to the CRC calculator335, or a combination thereof. For example, if the CRC values340and370are different, the respective data used to calculate the CRC values340and370are different. As such, the CRC values340and370being different may indicate one or more errors associated with the path of the data that includes the data channels315, one or more circuits associated with storage of the data to the memory array, one or more circuits associated with reading the data from the memory array (e.g., column decoders225, row decoders220, input/output255, sense components245), or a combination thereof.

In the case that the error detector365determines that the CRC value340is not the same as the CRC value370, another error may have occurred as part of (e.g., during) the transmission of the CRC value370from the host system305to the memory system310via the EDC channel320. In some cases, it may be unclear as to whether such an error occurred, as it may be unknown whether the CRC values350and370are the same. However, the CRC values340and370being different may indicate that one or more errors occurred at least along the path of the data.

In some examples, if the host system305determines that the CRC values340and370are different, the host system305may determine which bits of the CRC value340are not the same as the bits of the CRC value370, how many bits of the CRC value340are different, or both, to determine a location of an error along the path of the data. For example, the host system305may compare each bit of the received CRC value340to each bit of the CRC value370and may record the quantity and/or location of bits of the CRC value340that are different from the bits of the CRC value370. The host system305may subsequently utilize the quantity and location of the bits to assist in determining where the error occurred. For example, if the same one or more bits of the CRC value340are always incorrect (e.g., different from the corresponding one or more bits of the CRC value370) when transmitting the same data to the memory system310(e.g., multiple transmissions of the same data and subsequent transmissions of the same incorrect CRC value340) and all the other bits of the CRC value340are correct, such a pattern of incorrect CRC bits may indicate a first location of the error along the path. Additionally, or alternatively, if all the bits of the CRC value340are incorrect, but always in the same way, such a pattern of incorrect CRC bits may indicate a second location of the error along the path. Additionally, or alternatively, if half of the bits of the CRC value340are incorrect, such a pattern of incorrect CRC bits may indicate a third location along the path (e.g., corresponding to a particular circuit used to store and/or retrieve the bits used to generate the incorrect half of bits).

Alternatively, the host system305may receive the CRC value340from the memory system310and may determine that the CRC value340is the same as the CRC value originally transmitted to the memory system310(e.g., the CRC value370). For example, the error detector365of the host system305may receive the CRC value340and may compare the CRC value340to the CRC value370(e.g., the CRC value originally transmitted to the memory system310). In the case that the error detector365may determine that the CRC value340is the same as the CRC value370, the host system305(e.g., the error detector365) may determine that the error may have occurred as part of (e.g., during) transmission of the CRC value370from the host system305to the memory system310via the EDC channel320, and that the error may not have occurred along the path of the data330. For example, if the CRC values340and370are the same, the respective data used to calculate the CRC values340and370are the same. Accordingly, there was no error that occurred along the path of the data from the host system305to the CRC calculator335. Instead, the host system305may determine that the error is associated with the transmission of the CRC value370such that the CRC value350received by the memory system310is different from the CRC value370.

FIG.4shows an example of a system400that supports CRC comparison for error detection in accordance with examples as disclosed herein. The system400may be implemented by aspects of a system100, an architecture200, a system300, or one or more components thereof (e.g., a host system105, a memory system110, a local memory controller260, a memory system310, and a host system305) as described with reference toFIGS.1-3, respectively. The system400may support relatively more granular determination of CRC error causes associated with reading data from a memory system.

In some examples, the system400may include a memory system410, which may be an example of a memory system described herein, including with reference toFIGS.1and3. The memory system410may include a CRC calculator420. The memory system410may input data415into the CRC calculator420, and the CRC calculator420may generate (e.g., calculate) a calculated CRC value425associated with (e.g., based on, using) the data415. In some examples, the system400may include a host system405, which may be an example of a host system described herein, including with reference toFIGS.1-3. The host system405may include a CRC calculator440. The host system405may input data received from the memory system410into the CRC calculator440, and the CRC calculator440may generate (e.g., calculate) a calculated CRC value445associated with (e.g., based on, using) the data415. The host system405may also include an error detector435. The error detector435may compare various CRC values (e.g., the CRC value425, the CRC value445, an expected CRC value430) to detect one or more errors and determine a cause of the one or more errors (e.g., a location of where the one or more errors may have occurred). Additionally, although non-limiting examples of the system400herein are generally described in terms of applicability to memory systems, memory sub-systems, memory devices, or a combination thereof, examples of the system400are not so limited. For example, aspects of the present disclosure may be applied as well to any computing system, computing sub-system, processing system, processing sub-system, component, device, structure, or other types of systems or sub-systems used for applications such as data collecting, data processing, data storage, networking, communication, power, artificial intelligence, system-on-a-chip, control, telemetry, sensing and monitoring, digital entertainment, or any combination thereof.

In accordance with examples described herein, the host system405may receive the CRC value425and may generate the CRC value445and the CRC value430to be utilized in determining where an error may have occurred as part of (e.g., during) a read operation. For example, the host system405may transmit a read command to the memory system410requesting the data415. The memory system410may receive the read command and may retrieve the data415associated with the read command from a memory array of the memory system410. The memory system410may input the data415into the CRC calculator420, and the CRC calculator420may generate the CRC value425. The memory system410may transmit the CRC value425(e.g., via an EDC channel) and the data415to the host system405(e.g., via one or more data channels). The host system405may receive the data415and the CRC value425. The host system405may calculate a CRC value445based on (e.g., using) the received data415. The host system405may generate (e.g., calculate) a CRC value430based on the data that the host system405expects to receive in response to transmitting the read command. As such, the CRC value430may be referred to as an expected CRC value430.

The host system405may compare CRC values associated with the data415to determine whether an error associated with reading the data occurred and where a detected error may have occurred as part of the reading of the data. For example, the host system405may input the CRC value425, the CRC value430, and the CRC value445into the error detector435to determine if there may be an error and to determine a type of the error (e.g., determine where an error may have occurred). If the CRC values425,430and445are the same, the host system405may determine that no error occurred.

In the case that the error detector435may determine, based on comparing the CRC values, that the CRC value430may not be the same as the CRC value425and the CRC value445, while the CRC value425and the CRC value445may be the same, the host system405(e.g., the error detector435) may determine that the error may have occurred on the path of the data415prior to the data415being input to the CRC calculator420(e.g., during retrieval of the data415from the memory array of the memory system410). For example, the CRC values425and445being the same may indicate that that no error occurred as part of the transmission of the CRC values425and445via the EDC channel and data channels, respectively. However, because the CRC values425and445are not the same as the expected CRC value430, the host system405may determine that an error occurred prior to the calculation of the CRC value425using the CRC calculator420, such as part of the retrieval of the data415from the memory array (e.g., at one or more locations along a path of the data415from the memory array to the CRC calculator420). Such an error may result in the data415being incorrect, thereby resulting in incorrect CRC values425and445that are calculated using the data415.

In the case that the error detector435may determine (e.g., based on comparing the CRC values) that the CRC value430may be the same as the CRC value425, while the CRC value445may not be the same as the CRC value425and the CRC value430, the host system405may determine that the error may have occurred as part of (e.g., during) the transmission of the data415to the host system405. For example, the CRC values425and430being the same may indicate that that no error occurred as part of the retrieval of the data415from the memory array, the calculation of the CRC value425using the data415, and the transmission of the CRC value425via the EDC channel. However, because the CRC value445is not the same as the CRC values425and430, the host system405may determine that an error occurred as part of the transmission of the data415via the one or more data channels. For example, such an error may result in incorrect data being input into the CRC calculator440at the host system405, thereby resulting the CRC value445being incorrect.

In the case that the error detector435may determine (e.g., based on comparing the CRC values) that the CRC value430may be the same as the CRC value445, while the CRC value425may not be the same as the CRC value430and the CRC value445, the host system405may determine that the error may have occurred during transmission of the CRC value425from the memory system410to the host system405(e.g., via the EDC channel). For example, the CRC values430and445being the same may indicate that that no error occurred as part of the retrieval of the data415from the memory array and the transmission of the data415via the one or more data channels, as the data415received at the host system405and used to calculate the CRC value445results in the correct CRC value (e.g., a CRC value that matches the expected CRC value430). However, because the CRC value425is not the same as the CRC values430and445, the host system405may determine that an error occurred as part of the transmission of the CRC value425via the EDC channel such that the CRC value425is incorrect.

In the case that the error detector435may determine (e.g., based on comparing the CRC values) that the CRC value430, the CRC value425, and the CRC value445are each different from each other (e.g., may not be the same), the host system405may determine that two or more errors (e.g., at least two errors) may have occurred as part of reading the data, such as: part of transmission of the CRC value425from the memory system410to the host system405; on the path of the data415prior to the data415being input to the CRC calculator420(e.g., during retrieval of the data415from the memory array of the memory system410to the CRC calculator420); part of the transmission of the data415to the host system405, or a combination thereof.

By determining the origin of an error, the host system405may be enabled to take more efficient and corrective actions to reduce the likelihood of (e.g., avoid) errors in the future.

FIG.5shows a block diagram500of a host system520that supports CRC comparison for error detection in accordance with examples as disclosed herein. The host system520may be an example of aspects of a host system as described with reference toFIGS.1through4. The host system520, or various components thereof, may be an example of means for performing various aspects of CRC comparison for error detection as described herein. For example, the host system520may include a transmission component525, an error indication component530, a receiver component535, a calculation component540, an error detection component545, a command component550, a storage component555, or any combination thereof. Each of these components, or components of subcomponents thereof (e.g., one or more processors, one or more memories), may communicate, directly or indirectly, with one another (e.g., via one or more buses).

The transmission component525may be configured as or otherwise support a means for transmitting data via a set of data channels and a first indication of a first CRC value corresponding to the data via an error detection channel. The error indication component530may be configured as or otherwise support a means for receiving a second indication of an error associated with the first CRC value. The receiver component535may be configured as or otherwise support a means for receiving a third indication of a second CRC value corresponding to the data based at least in part on receiving the second indication of the error.

In some examples, the error detection component545may be configured as or otherwise support a means for determining a type of the error based at least in part on a comparison of the first CRC value to the second CRC value.

In some examples, to support determining the type of error, the error detection component545may be configured as or otherwise support a means for determining, based at least in part on the first CRC value being different than the second CRC value, the error is at least associated with a path of the data including the set of data channels, one or more circuits associated with storage of the data to memory cells of the memory array, one or more circuits associated with reading the data from the memory cells, or a combination thereof.

In some examples, to support determining the type of error, the error detection component545may be configured as or otherwise support a means for determining a location of the error along the path of the data based at least in part on determining which bits of the first CRC value are different than corresponding bits of the second CRC value.

In some examples, to support determining the type of error, the error detection component545may be configured as or otherwise support a means for determining the error is associated with communication of the first indication of the first CRC value via the error detection channel based at least in part on the first CRC value being the same as the second CRC value.

In some examples, the command component550may be configured as or otherwise support a means for transmitting, based at least in part on receiving the second indication of the error, a command to transmit the third indication of the second CRC value, where the third indication is received based at least in part on the command.

In some examples, to support receiving the third indication of the second CRC value, the receiver component535may be configured as or otherwise support a means for receiving the third indication of the second CRC value via the error detection channel, where the third indication of the second CRC value is received at a first rate that is slower than a second rate at which the first indication of the first CRC value is transmitted.

In some examples, to support receiving the third indication of the second CRC value, the receiver component535may be configured as or otherwise support a means for receiving the third indication of the second CRC value via the set of data channels, where the third indication of the second CRC value is received at a first rate that is slower than a second rate at which the first indication of the first CRC value is transmitted.

Additionally, or alternatively, the command component550may be configured as or otherwise support a means for transmitting, to a memory system, a command to read data from the memory system. In some examples, the receiver component535may be configured as or otherwise support a means for receiving the data via a set of data channels and a first indication of a first CRC value associated with the data via an error detection channel. The calculation component540may be configured as or otherwise support a means for calculating, based at least in part on the data, a second CRC value. The error detection component545may be configured as or otherwise support a means for determining an error type associated with the data based at least in part on a comparison of the first CRC value, the second CRC value, and an expected CRC value associated with the data.

In some examples, to support determining the error type, the error detection component545may be configured as or otherwise support a means for determining, based at least in part on the first CRC value and the second CRC value being the same and the expected CRC value being different than the first CRC value and the second CRC value, an error associated with the data prior to a calculation of the first CRC value at the memory system using the data.

In some examples, to support determining the error type, the error detection component545may be configured as or otherwise support a means for determining an error is associated with communication of the data via the set of data channels based at least in part on the first CRC value and the expected CRC value being the same and the second CRC value being different than the first CRC value and the expected CRC value.

In some examples, to support determining the error type, the error detection component545may be configured as or otherwise support a means for determining an error associated with communication of the first indication of the first CRC value via the error detection channel based at least in part on the second CRC value and the expected CRC value being the same and the first CRC value being different than the second CRC value and the expected CRC value.

In some examples, to support determining the error type, the error detection component545may be configured as or otherwise support a means for determining, based at least in part on each of the first CRC value, the second CRC value, and the expected CRC value being different, at least two errors, each of the at least two errors associated with the data prior to a calculation of the first CRC value at the memory system, associated with communication of the data via the set of data channels, or associated with communication of the first indication of the first CRC value via the error detection channel.

In some examples, the storage component555may be configured as or otherwise support a means for storing a table of a set of error types, where determining the error type includes reading an entry of the table corresponding to the error type in accordance with one or more differences between the first CRC value, the second CRC value, the expected CRC value, or a combination thereof.

In some examples, the calculation component540may be configured as or otherwise support a means for calculating the expected CRC value based at least in part on expected data associated with the command.

In some examples, the described functionality of the host system520, or various components thereof, may be supported by or may refer to at least a portion of at least one processor, where such at least one processor may include one or more processing elements (e.g., a controller, a microprocessor, a microcontroller, a digital signal processor, a state machine, discrete gate logic, discrete transistor logic, discrete hardware components, or any combination of one or more of such elements). In some examples, the described functionality of the host system520, or various components thereof, may be implemented at least in part by instructions (e.g., stored in memory, non-transitory computer-readable medium) executable by such at least one processor.

FIG.6shows a block diagram600of a memory system620that supports CRC comparison for error detection in accordance with examples as disclosed herein. The memory system620may be an example of aspects of a memory system as described with reference toFIGS.1through4. The memory system620, or various components thereof, may be an example of means for performing various aspects of CRC comparison for error detection as described herein. For example, the memory system620may include a receiver component625, a calculation component630, an error indication component635, a transmission component640, a command component645, a storage component650, or any combination thereof. Each of these components, or components of subcomponents thereof (e.g., one or more processors, one or more memories), may communicate, directly or indirectly, with one another (e.g., via one or more buses).

The receiver component625may be configured as or otherwise support a means for receiving data via a set of data channels and a first indication of a first CRC value corresponding to the data via an error detection channel. The calculation component630may be configured as or otherwise support a means for calculating, based at least in part on the data, a second CRC value. The error indication component635may be configured as or otherwise support a means for transmitting a second indication of an error based at least in part on the first CRC value being different than the second CRC value. The transmission component640may be configured as or otherwise support a means for transmitting a third indication of the second CRC value based at least in part on transmitting the second indication of the error.

In some examples, the command component645may be configured as or otherwise support a means for receiving, based at least in part on transmitting the second indication of the error, a command to transmit the third indication of the second CRC value, where the third indication is transmitted based at least in part on the command.

In some examples, to support transmitting the third indication of the second CRC value, the transmission component640may be configured as or otherwise support a means for transmitting the third indication of the second CRC value via the error detection channel, where the third indication of the second CRC value is transmitted at a first rate that is slower than a second rate at which the first indication of the first CRC value is received.

In some examples, to support transmitting the third indication of the second CRC value, the transmission component640may be configured as or otherwise support a means for transmitting the third indication of the second CRC value via the set of data channels, where the third indication of the second CRC value is transmitted at a first rate that is slower than a second rate at which the first indication of the first CRC value is received.

In some examples, the storage component650may be configured as or otherwise support a means for storing the second CRC value based at least in part on the first CRC value being different than the second CRC value, where the third indication of the second CRC value is transmitted based at least in part on the storing.

In some examples, the receiver component625may be configured as or otherwise support a means for receiving second data via the set of data channels and a fourth indication of a third CRC value corresponding to the second data via the error detection channel. In some examples, the calculation component630may be configured as or otherwise support a means for calculating, based at least in part on the second data, a fourth CRC value. In some examples, the storage component650may be configured as or otherwise support a means for refraining from storing the fourth CRC value based at least in part on the third CRC value and the fourth CRC value being the same.

In some examples, the described functionality of the memory system620, or various components thereof, may be supported by or may refer to at least a portion of at least one processor, where such at least one processor may include one or more processing elements (e.g., a controller, a microprocessor, a microcontroller, a digital signal processor, a state machine, discrete gate logic, discrete transistor logic, discrete hardware components, or any combination of one or more of such elements). In some examples, the described functionality of the memory system620, or various components thereof, may be implemented at least in part by instructions (e.g., stored in memory, non-transitory computer-readable medium) executable by such at least one processor.

FIG.7shows a flowchart illustrating a method700that supports CRC comparison for error detection in accordance with examples as disclosed herein. The operations of method700may be implemented by a host system or its components as described herein. For example, the operations of method700may be performed by a host system as described with reference toFIGS.1through5. In some examples, a host system may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally, or alternatively, the host system may perform aspects of the described functions using special-purpose hardware.

At705, the method may include transmitting data via a set of data channels and a first indication of a first CRC value corresponding to the data via an error detection channel. In some examples, aspects of the operations of705may be performed by a transmission component525as described with reference toFIG.5.

At710, the method may include receiving a second indication of an error associated with the first CRC value. In some examples, aspects of the operations of710may be performed by an error indication component530as described with reference toFIG.5.

At715, the method may include receiving a third indication of a second CRC value corresponding to the data based at least in part on receiving the second indication of the error. In some examples, aspects of the operations of715may be performed by a receiver component535as described with reference toFIG.5.

Aspect 1: A method, apparatus, or non-transitory computer-readable medium including operations, features, circuitry, logic, means, or instructions, or any combination thereof for transmitting data via a set of data channels and a first indication of a first CRC value corresponding to the data via an error detection channel; receiving a second indication of an error associated with the first CRC value; and receiving a third indication of a second CRC value corresponding to the data based at least in part on receiving the second indication of the error.

Aspect 2: The method, apparatus, or non-transitory computer-readable medium of aspect 1, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for determining a type of the error based at least in part on a comparison of the first CRC value to the second CRC value.

Aspect 3: The method, apparatus, or non-transitory computer-readable medium of aspect 2, where determining the type of error includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for determining, based at least in part on the first CRC value being different than the second CRC value, the error is at least associated with a path of the data including the set of data channels, one or more circuits associated with storage of the data to memory cells of the memory array, one or more circuits associated with reading the data from the memory cells, or a combination thereof.

Aspect 4: The method, apparatus, or non-transitory computer-readable medium of aspect 3, where determining the type of error includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for determining a location of the error along the path of the data based at least in part on determining which bits of the first CRC value are different than corresponding bits of the second CRC value.

Aspect 5: The method, apparatus, or non-transitory computer-readable medium of aspect 2, where determining the type of error includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for determining the error is associated with communication of the first indication of the first CRC value via the error detection channel based at least in part on the first CRC value being the same as the second CRC value.

Aspect 6: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 5, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for transmitting, based at least in part on receiving the second indication of the error, a command to transmit the third indication of the second CRC value, where the third indication is received based at least in part on the command.

Aspect 7: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 6, where receiving the third indication of the second CRC value includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for receiving the third indication of the second CRC value via the error detection channel, where the third indication of the second CRC value is received at a first rate that is slower than a second rate at which the first indication of the first CRC value is transmitted.

Aspect 8: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 6, where receiving the third indication of the second CRC value includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for receiving the third indication of the second CRC value via the set of data channels, where the third indication of the second CRC value is received at a first rate that is slower than a second rate at which the first indication of the first CRC value is transmitted.

FIG.8shows a flowchart illustrating a method800that supports CRC comparison for error detection in accordance with examples as disclosed herein. The operations of method800may be implemented by a memory system or its components as described herein. For example, the operations of method800may be performed by a memory system as described with reference toFIGS.1through4and6. In some examples, a memory system may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally, or alternatively, the memory system may perform aspects of the described functions using special-purpose hardware.

At805, the method may include receiving data via a set of data channels and a first indication of a first CRC value corresponding to the data via an error detection channel. In some examples, aspects of the operations of805may be performed by a receiver component625as described with reference toFIG.6.

At810, the method may include calculating, based at least in part on the data, a second CRC value. In some examples, aspects of the operations of810may be performed by a calculation component630as described with reference toFIG.6.

At815, the method may include transmitting a second indication of an error based at least in part on the first CRC value being different than the second CRC value. In some examples, aspects of the operations of815may be performed by an error indication component635as described with reference toFIG.6.

At820, the method may include transmitting a third indication of the second CRC value based at least in part on transmitting the second indication of the error. In some examples, aspects of the operations of820may be performed by a transmission component640as described with reference toFIG.6.

Aspect 9: A method, apparatus, or non-transitory computer-readable medium including operations, features, circuitry, logic, means, or instructions, or any combination thereof for receiving data via a set of data channels and a first indication of a first CRC value corresponding to the data via an error detection channel; calculating, based at least in part on the data, a second CRC value; transmitting a second indication of an error based at least in part on the first CRC value being different than the second CRC value; and transmitting a third indication of the second CRC value based at least in part on transmitting the second indication of the error.

Aspect 10: The method, apparatus, or non-transitory computer-readable medium of aspect 9, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for receiving, based at least in part on transmitting the second indication of the error, a command to transmit the third indication of the second CRC value, where the third indication is transmitted based at least in part on the command.

Aspect 11: The method, apparatus, or non-transitory computer-readable medium of any of aspects 9 through 10, where transmitting the third indication of the second CRC value includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for transmitting the third indication of the second CRC value via the error detection channel, where the third indication of the second CRC value is transmitted at a first rate that is slower than a second rate at which the first indication of the first CRC value is received.

Aspect 12: The method, apparatus, or non-transitory computer-readable medium of any of aspects 9 through 10, where transmitting the third indication of the second CRC value includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for transmitting the third indication of the second CRC value via the set of data channels, where the third indication of the second CRC value is transmitted at a first rate that is slower than a second rate at which the first indication of the first CRC value is received.

Aspect 13: The method, apparatus, or non-transitory computer-readable medium of any of aspects 9 through 12, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for storing the second CRC value based at least in part on the first CRC value being different than the second CRC value, where the third indication of the second CRC value is transmitted based at least in part on the storing.

Aspect 14: The method, apparatus, or non-transitory computer-readable medium of any of aspects 9 through 13, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for receiving second data via the set of data channels and a fourth indication of a third CRC value corresponding to the second data via the error detection channel; calculating, based at least in part on the second data, a fourth CRC value; and refraining from storing the fourth CRC value based at least in part on the third CRC value and the fourth CRC value being the same.

FIG.9shows a flowchart illustrating a method900that supports CRC comparison for error detection in accordance with examples as disclosed herein. The operations of method900may be implemented by a host system or its components as described herein. For example, the operations of method900may be performed by a host system as described with reference toFIGS.1through5. In some examples, a host system may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally, or alternatively, the host system may perform aspects of the described functions using special-purpose hardware.

At905, the method may include transmitting, to a memory system, a command to read data from the memory system. In some examples, aspects of the operations of905may be performed by a transmission component525as described with reference toFIG.5.

At910, the method may include receiving the data via a set of data channels and a first indication of a first CRC value associated with the data via an error detection channel. In some examples, aspects of the operations of910may be performed by a receiver component535as described with reference toFIG.5.

At915, the method may include calculating, based at least in part on the data, a second CRC value. In some examples, aspects of the operations of915may be performed by a calculation component540as described with reference toFIG.5.

At920, the method may include determining an error type associated with the data based at least in part on a comparison of the first CRC value, the second CRC value, and an expected CRC value associated with the data. In some examples, aspects of the operations of920may be performed by an error detection component545as described with reference toFIG.5.

Aspect 15: A method, apparatus, or non-transitory computer-readable medium including operations, features, circuitry, logic, means, or instructions, or any combination thereof for transmitting, to a memory system, a command to read data from the memory system; receiving the data via a set of data channels and a first indication of a first CRC value associated with the data via an error detection channel; calculating, based at least in part on the data, a second CRC value; and determining an error type associated with the data based at least in part on a comparison of the first CRC value, the second CRC value, and an expected CRC value associated with the data.

Aspect 16: The method, apparatus, or non-transitory computer-readable medium of aspect 15, where determining the error type includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for determining, based at least in part on the first CRC value and the second CRC value being the same and the expected CRC value being different than the first CRC value and the second CRC value, an error associated with the data prior to a calculation of the first CRC value at the memory system using the data.

Aspect 17: The method, apparatus, or non-transitory computer-readable medium of aspect 15, where determining the error type includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for determining an error is associated with communication of the data via the set of data channels based at least in part on the first CRC value and the expected CRC value being the same and the second CRC value being different than the first CRC value and the expected CRC value.

Aspect 18: The method, apparatus, or non-transitory computer-readable medium of aspect 15, where determining the error type includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for determining an error associated with communication of the first indication of the first CRC value via the error detection channel based at least in part on the second CRC value and the expected CRC value being the same and the first CRC value being different than the second CRC value and the expected CRC value.

Aspect 19: The method, apparatus, or non-transitory computer-readable medium of aspect 15, where determining the error type includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for determining, based at least in part on each of the first CRC value, the second CRC value, and the expected CRC value being different, at least two errors, each of the at least two errors associated with the data prior to a calculation of the first CRC value at the memory system, associated with communication of the data via the set of data channels, or associated with communication of the first indication of the first CRC value via the error detection channel.

Aspect 20: The method, apparatus, or non-transitory computer-readable medium of any of aspects 15 through 19, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for storing a table of a set of error types, where determining the error type includes reading an entry of the table corresponding to the error type in accordance with one or more differences between the first CRC value, the second CRC value, the expected CRC value, or a combination thereof.

Aspect 21: The method, apparatus, or non-transitory computer-readable medium of any of aspects 15 through 20, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for calculating the expected CRC value based at least in part on expected data associated with the command.

A switching component (e.g., a transistor) discussed herein may be a field-effect transistor (FET), and may include a source (e.g., a source terminal), a drain (e.g., a drain terminal), a channel between the source and drain, and a gate (e.g., a gate terminal). A conductivity of the channel may be controlled (e.g., modulated) by applying a voltage to the gate which, in some examples, may result in the channel becoming conductive. A switching component may be an example of an n-type FET or a p-type FET.

The description set forth herein, in connection with the appended drawings, describes example configurations and does not represent all the examples that may be implemented or that are within the scope of the claims. The detailed description includes specific details to provide an understanding of the described techniques. These techniques, however, may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

In the appended figures, similar components or features may have the same reference label. Similar components may be distinguished by following the reference label by one or more dashes and additional labeling that distinguishes among the similar components. If just the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the additional reference labels.

The functions described herein may be implemented in hardware, software executed by a processing system (e.g., one or more processors, one or more controllers, control circuitry processing circuitry, logic circuitry), firmware, or any combination thereof. If implemented in software executed by a processing system, the functions may be stored on or transmitted over as one or more instructions (e.g., code) on a computer-readable medium. Due to the nature of software, functions described herein can be implemented using software executed by a processing system, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions may be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations.

Illustrative blocks and modules described herein may be implemented or performed with one or more processors, such as a DSP, an ASIC, an FPGA, discrete gate logic, discrete transistor logic, discrete hardware components, other programmable logic device, or any combination thereof designed to perform the functions described herein. A processor may be an example of a microprocessor, a controller, a microcontroller, a state machine, or other types of processor. A processor may also be implemented as at least one of one or more computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium may be any available medium, or combination of multiple media, that can be accessed by a computer. By way of example, and not limitation, non-transitory computer-readable media can comprise RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium or combination of media that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a computer, or a processor.

The descriptions and drawings are provided to enable a person having ordinary skill in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to the person having ordinary skill in the art, and the techniques disclosed herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not limited to the examples and designs described herein but is to be accorded the broadest scope consistent with the principles and novel features disclosed herein.