PHOTOELECTRIC CONVERSION APPARATUS, METHOD OF DRIVING THE APPARATUS, SEMICONDUCTOR SUBSTRATE, AND EQUIPMENT

A photoelectric conversion apparatus includes an output line and multiple unit pixels. Each of the multiple unit pixels includes a photoelectric conversion element that generates signal electric charge based on incident light, an amplifier transistor that has a gate into which the signal electric charge is input and that outputs a signal based on potential of the gate, a selection transistor with which the amplifier transistor is connected to the output line, and a reset transistor that resets the potential of the gate. The photoelectric conversion apparatus includes a first well on which the selection transistor is provided and a second well on which at least two transistors are provided. The first well is electrically separated from the second well.

BACKGROUND

Field of the Disclosure

The disclosure relates to a photoelectric conversion apparatus, a method of driving the photoelectric conversion apparatus, a semiconductor substrate, and equipment.

Description of the Related Art

Photoelectric conversion apparatuses each including multiple unit pixels are known. The multiple unit pixels each include a photoelectric conversion unit that performs photoelectric conversion of incident light to generate signal electric charge and an amplifier transistor that has a gate through which the signal electric charge is input. The unit pixel further includes a reset transistor that resets the potential of the gate. The gate of the amplifier transistor is electrically connected to the reset transistor. At least part of the transistors in the unit pixel forms one node into which the signal electric charge is input and which is electrically connected.

Japanese Patent Laid-Open No. 2001-160619 discloses a configuration in which a well having a transistor for amplification, which is an amplifier transistor, provided thereon is electrically separated from a well on which other transistors are provided.

The reset transistor into which the signal electric charge is input and which is part of the one node that is electrically connected is provided on the same well as that of a line selection transistor in the configuration disclosed in Japanese Patent Laid-Open No. 2001-160619.

In the configuration disclosed in Japanese Patent Laid-Open No. 2001-160619, the line selection transistor shares the well with the reset transistor, into which the signal electric charge is input and which is one of the transistors forming the one node that is electrically connected. Accordingly, it may sometime be difficult to appropriately set the potential of the well of the selection transistor.

SUMMARY

One aspect of the technology of the disclosure is a photoelectric conversion apparatus that includes an output line and multiple unit pixels. Each of the multiple unit pixels includes a photoelectric conversion element that generates signal electric charge based on incident light and multiple transistors. The multiple transistors at least include an amplifier transistor that has a gate into which the signal electric charge is input and that outputs a signal based on potential of the gate, a selection transistor with which the amplifier transistor is connected to the output line, and a reset transistor that resets the potential of the gate. The photoelectric conversion apparatus includes a first well on which the selection transistor is provided and a second well on which at least two transistors in the multiple transistors are provided. The first well is electrically separated from the second well.

Another aspect of the technology of the disclosure is a method of driving a photoelectric conversion apparatus including an output line and multiple unit pixels. Each of the multiple unit pixels includes a photoelectric conversion element that generates signal electric charge based on incident light and multiple transistors. The multiple transistors at least include an amplifier transistor that has a gate into which the signal electric charge is input and that outputs a signal based on potential of the gate, a selection transistor with which the amplifier transistor is connected to the output line, and a reset transistor that resets the potential of the gate. The photoelectric conversion apparatus includes a first well on which the selection transistor is provided and a second well on which at least two transistors in the multiple transistors are provided. The method includes setting potential of the second well to first potential during a period in which the selection transistor is in an off state and setting the potential of the second well to second potential different from the first potential during a period in which the selection transistor is in an on state.

Another aspect of the technology of the disclosure is a semiconductor substrate laminated on a component in which a photoelectric conversion element that generates signal electric charge based on incident light is provided. The semiconductor substrate includes an output line and multiple transistors. The multiple transistors at least include an amplifier transistor that has a gate into which the signal electric charge is input and that outputs a signal based on potential of the gate, a selection transistor with which the amplifier transistor is connected to the output line, and a reset transistor that resets the potential of the gate. The semiconductor substrate includes a first well on which the selection transistor is provided and a second well on which at least two transistors in the multiple transistors are provided. The first well is electrically separated from the second well.

DESCRIPTION OF THE EMBODIMENTS

The respective embodiments will herein be described with reference to the drawings.

Each embodiment described below focuses on an imaging apparatus as an example of a photoelectric conversion apparatus. However, each embodiment is not limited to the imaging apparatus and is applicable to another example of the photoelectric conversion apparatus. For example, each embodiment is applicable to, for example, a focusing apparatus (an apparatus for focus detection, distance measurement using Time Of Flight (TOF), or the like) or a photometric apparatus (an apparatus for measurement of the amount of incident light or the like).

Semiconductor regions, the conductivity types of wells, and dopant to be injected, which are described in the embodiments below, are only examples and are not limited to the semiconductor regions, the conductivity types of wells, and the dopant described in the embodiments. The conductivity types of wells and the dopant, which are described in the embodiments, may be appropriately changed and the semiconductor regions and the potentials of the wells may be appropriately changed in accordance with the change of the conductivity types of wells and the dopant.

The conductivity types of transistors described in the embodiments below are only examples and are not limited to the ones described in the embodiments. The conductivity types described in the embodiments may be appropriately changed and the potentials of the gates, the sources, and the drains of the transistors may be appropriately changed in accordance with the change of the conductivity types.

For example, in the case of a transistor that is operated as a switch, the low level and the high level of the potential to be supplied to the gate may be reversed with respect to the ones described in the embodiments in accordance with the change of the conductivity types. In addition, the conductivity types of the semiconductor regions described in the embodiments below are only examples and are not limited to the ones described in the embodiments. The conductivity types described in the embodiments may be appropriately changed and the potentials of the semiconductor regions may be appropriately changed in accordance with the change of the conductivity types.

First Embodiment

A photoelectric conversion apparatus and a method of driving the photoelectric conversion apparatus according to a first embodiment will now be described with reference toFIG.1toFIG.6.

FIG.1is a block diagram illustrating the photoelectric conversion apparatus according to the first embodiment. A photoelectric conversion apparatus1according to the first embodiment includes a pixel region13, a vertical drive circuit33, a column signal processor34, a horizontal drive circuit35, an output circuit36, and a system controller37.

Multiple rows and multiple columns are arrayed in the pixel region13. The pixel region13includes multiple unit pixels25that output pixel signals corresponding to the amounts of received light. Each unit pixel25includes a photoelectric conversion unit that generates and accumulates signal electric charge based on incident light. The unit pixels25of N-number lines and M-number columns, which are composed of an R1-st line to an RN-th line and a C1-st column to a CM-th column, are illustrated inFIG.1.

A control line23extends in the horizontal direction (the direction along the pixel lines) on each line of the pixel region13. Each control line23is connected to the multiple unit pixels25arranged on the same line and forms a signal line common to the multiple unit pixels25. Each control line23may include multiple signal lines. The control lines23are connected to the vertical drive circuit33.

An output line24extends in the vertical direction (the direction along the pixel columns) on each column of the pixel region13. Each output line24is connected to the multiple unit pixels25arranged on the corresponding column and forms a signal line common to the multiple unit pixels25. Each output line24may include multiple output lines.

The output lines24are connected to the column signal processor34.

The vertical drive circuit33is a control circuit having a function to receive a control signal supplied from the system controller37, to generate a control signal for driving the unit pixels25, and to supply the generated control signal to the unit pixels25via the control lines23. The signals read out from the unit pixels25in unit of lines are input into the column signal processor34via the output lines24.

The column signal processor34includes multiple column circuits (not illustrated) provided for the corresponding multiple output lines24. Each of the multiple column circuits includes a processing circuit and a signal holding circuit. The processing circuit has a function to perform certain signal processing to the pixel signal output through the corresponding output line24. The signal processing performed by the processing circuit includes, for example, amplification, correction through correlated double sampling (CDS), and analog-to-digital conversion (AD conversion). The signal holding circuit includes a memory for holding the pixel signal processed in the processing circuit.

The horizontal drive circuit35is a control circuit having a function to receive a control signal supplied from the system controller37, to generate a control signal for reading out the pixel signal from the column signal processor34, and to supply the pixel signal to the column signal processor34. The horizontal drive circuit35sequentially scans the column circuits of the respective columns in the column signal processor34and causes the column circuits to supply the pixel signals that are held in the column circuits to the output circuit36.

The output circuit36includes an external interface circuit and outputs the signal processed in the column signal processor34to the outside of the photoelectric conversion apparatus1. The external interface circuit in the output circuit36is not particularly limited.

The system controller37is a control circuit that generates control signals for controlling the operations of the vertical drive circuit33, the column signal processor34, and the horizontal drive circuit35and supplies the generated control signals to the respective functional blocks.

FIG.2is a first equivalent circuit diagram of the unit pixel25in the first embodiment. A unit pixel25A (m, n) arrayed on the m-th line and the n-th column is illustrated inFIG.2. Here, m denotes an integer from 1 to M and n denotes an integer from 1 to N. The other unit pixels25composing the pixel region13may include the same circuit configuration as that of the unit pixel25A (m, n).

The unit pixel25A (m, n) includes a photoelectric conversion element PD1, a transfer transistor M11, a reset transistor M2, an amplifier transistor M3, and a selection transistor M4.

The photoelectric conversion element PD1is, for example, a photodiode. The photoelectric conversion element PD1performs photoelectric conversion of the incident light and accumulates the electric charge. The number of the photoelectric conversion elements in each unit pixel25A is not limited to one. The photoelectric conversion element PD1may be a photoelectric conversion film including at least one of an organic thin film and an inorganic thin film.

The transfer transistor M11is provided to transfer the signal electric charge (may be sometimes simply referred to as electric charge) generated by the photoelectric conversion element PD1to a floating diffusion region on a semiconductor substrate.

The floating diffusion region, the gate of the amplifier transistor M3, and one of the source and the drain of the reset transistor M2compose a floating diffusion (FD) node. The FD node further includes metal lines with which the floating diffusion region is connected to the gate of the amplifier transistor M3. The FD node is an electrically common node including the amplifier transistor M3and the reset transistor M2. A control signal TX1mis supplied from the vertical drive circuit33to the gate of the transfer transistor M11via a control line23mof the m-th line. When the control signal TX1mis at the high level, the electric charge that is generated and accumulated in response to light incident on the photoelectric conversion element PD1is transferred to the FD node via the transfer transistor M11. The FD node is composed of lines and electrodes of the drain of the transfer transistor M11, the source of the reset transistor M2, and the gate of the amplifier transistor M3.

The electric charge transferred from the photoelectric conversion element PD1is held in the FD node. The electric charge held in the FD node is converted into voltage. In other words, the voltage at the FD node has a value corresponding to the amount of the electric charge transferred from the photoelectric conversion element PD1.

The reset transistor M2resets the potential of the FD node to voltage corresponding to power supply voltage VDD. In other words, the reset transistor M2resets the potential of the gate of the amplifier transistor M3to the voltage corresponding to the power supply voltage VDD. A control signal RESm is supplied from the vertical drive circuit33to the gate of the reset transistor M2via the control line23m.When the control signal RESm is at the high level, the potential of the FD node is reset to the voltage corresponding to the power supply voltage VDD. When the control signal RESm is at the high level and the control signal TX1mis at the high level, the voltage of the photoelectric conversion element PD1is capable of being reset to the voltage corresponding to the power supply voltage VDD. However, it is not necessary to set both the control signal RESm and the control signal TX1mto the high level. For example, the signal electric charge of the photoelectric conversion element PD1is transferred to the FD when the control signal TX1mis at the high level. Then, the signal electric charge of the photoelectric conversion element PD1is reset also when the control signal RESm is at the high level to reset the FD.

The amplifier transistor M3supplies the signal to an output line24nof the n-th column via the selection transistor M4. The power supply voltage VDD is applied to the drain of the amplifier transistor M3. The source of the amplifier transistor M3is connected to the drain of the selection transistor M4. The amplifier transistor M3composes a source follower along with a current source included in the column signal processor34. When the selection transistor M4is in a conductive state (an on state), the amplifier transistor M3outputs the signal corresponding to the voltage of the FD node. This sets the signal level of the output line24to the level of the signal output from the amplifier transistor M3.

The selection transistor M4is provided between the amplifier transistor M3and the output line24n.

A control signal SELm is supplied from the vertical drive circuit33to the gate of the selection transistor M4via the control line23m.When the control signal SELm makes the transition to the high level, the selection transistor M4supplies the output from the amplifier transistor M3to the output line24n.

The selection transistor M4has a resistance component (hereinafter referred to as on resistance) depending on voltage (VGS) between the gate and the source of the selection transistor M4in the conductive state. The on resistance is varied with the floating diffusion region of each unit pixel25and the potential of the FD node to reduce linearity of the signal. This will be described in detail below.

A well WSELon which the selection transistor M4is arranged is electrically connected to the control line23m.In other words, the potential set by a control signal SELBm is applied to the well WSELon which the selection transistor M4is arranged. A well (a second well) on which the reset transistor M2is arranged is connected to ground potential. In contrast, the potential of the well WSEL(a first well) of the selection transistor M4is controlled independently of well potential of the other pixel transistors. Specifically, the potential of the well WSELof the selection transistor M4has a period different from that of the potential of the well on which the reset transistor M2is arranged in the photoelectric conversion apparatus of the first embodiment.

While the photoelectric conversion apparatus is operating, the potential of the well WSELof the selection transistor M4may be constantly differentiated from the potential of the well on which the reset transistor M2is arranged. Alternatively, the potential of the well WSELof the selection transistor M4may be differentiated from the potential of the well on which the reset transistor M2is arranged only during a partial period. Other elements may be further arranged on the well on which the reset transistor M2is arranged. For example, the photoelectric conversion element PD1, the transfer transistor M11, and the amplifier transistor M3may be further arranged on the well on which the reset transistor M2is arranged.

The structure of the unit pixel25will now be described, focusing on the structure of the well WSEL. An example is described below in which the photoelectric conversion element PD1, the transfer transistor M11, and the amplifier transistor M3are further arranged on the well on which the reset transistor M2is arranged.

FIG.3illustrates the structure of the unit pixel25of the first embodiment.

The four unit pixels25A of two lines and two columns in a plan view are illustrated inFIG.3. Each of the four unit pixels25A illustrated inFIG.3corresponds to the equivalent circuit inFIG.2and the respective elements composing the unit pixel25A have the common configuration. Referring toFIG.3, the horizontal direction indicates the X or Y direction and the depth direction with respect to the page indicates the Z direction. In this specification, the “plan view” means viewing of a plane parallel to the plane at the side at which the gates of the transistors of the semiconductor substrate are arranged from the direction orthogonal to the parallel plane. In other words, the “plan view” means viewing of a plane parallel to a first surface of the semiconductor substrate from the Z direction or the −Z direction inFIG.3.

The unit pixel25A is separated into at least two regions by an insulating separator (deep trench isolation (DTI)) in a plan view. The selection transistor M4is arranged in one region and a photoelectric conversion element PD is arranged in the other region. The insulating separator DTI is arranged between the selection transistor M4and the photoelectric conversion element PD in a plan view. The insulating separator DTI is arranged so as to surround the selection transistor M4.

The insulating separator DTI has a function to separate the well WSELincluding a region serving as the channel of the selection transistor M4from a well WPDon which the reset transistor M2is arranged. The photoelectric conversion element PD is further arranged on the well WPD. Although the wells WPDon which the photoelectric conversion elements PD are arranged in the respective pixels are also separated with the insulating separator DTI inFIG.3, the wells WPDin the respective pixels may not be separated with the insulating separator DTI.

The well WSELis electrically connected to the control signal SELBm via a well contact WCSELof the well WSEL. The well WPDis electrically connected to the ground potential via a well contact WCPDarranged on the well WPD. The transfer transistor M11, the reset transistor M2, and the amplifier transistor M3are arranged on the well WPD. In other words, the insulating separator DTI is arranged between the selection transistor M4, and the reset transistor M2and the amplifier transistor M3. FD denotes a floating diffusion region to which the signal electric charge of the photoelectric conversion element PD is transferred and is part of the FD node.

FIG.4is a schematic cross-sectional view taken along the IV-IV line inFIG.3. Of a semiconductor substrate301, a surface at the side at which an electrode M3G serving as the gate of the amplifier transistor M3is arranged is referred to as a first surface S1and a surface opposed to the first surface S1is referred to as a second surface S2. The direction from the first surface S1to the second surface S2is the Z direction. Light is incident from the second surface S2inFIG.4. The second surface S2may be referred to as a rear face and the first surface S1may be referred to as a front face. The semiconductor substrate is, for example, a silicon substrate. The silicon substrate is typically a substrate mostly containing Si among the elements. Alternatively, a silicon on insulator (SOI) substrate may be used as another example of the semiconductor substrate. The light may be incident from the first surface S1.

The sources and the drains of the pixel transistors including the FD, the transfer transistor M11, the reset transistor M2, the amplifier transistor M3, and the selection transistor M4each include an N-type semiconductor region in which N-type impurities are diffused. The electrode M3G serving as the gate of the amplifier transistor M3, an electrode M11G serving as the gate of the transfer transistor M11, and an electrode M4G serving as the gate of the selection transistor M4are arranged on the first surface S1. The well contact WCSELof the well WSELand the well contact WCPDof the well WPDare arranged in the semiconductor substrate301.

The well contact WCSELand the well contact WCPDeach include a P-type semiconductor region in which P-type impurities are diffused. The well contact WCSELand the well contact WCPDcompose part of the first surface S1of the semiconductor substrate301. An element isolator305is arranged in each of the regions between the multiple pixels and the region between the photoelectric conversion element PD and the pixel transistor region of one pixel. The element isolator305has a shallow trench isolation (STI) structure or a local oxidation of Si (LOCOS) structure. As illustrated inFIG.4, the insulating separator DTI passes through the semiconductor substrate301in the Z direction. Specifically, the insulating separator DTI extends in the Z direction (the depth direction) from the first surface S1to the second surface S2of the semiconductor substrate301. In the semiconductor substrate301, the well WSELincluding the region serving as the channel of the selection transistor M4is electrically separated from the well WPDincluding the photoelectric conversion element PD with the insulating separator DTI.

According to the first embodiment, the well WSELis electrically separated from the photoelectric conversion element PD with the insulating separator DTI passing through the semiconductor substrate301. This electrical separation is considered as a substantially insulated state. In other words, the well WSELis electrically separated from the well WPB with the insulating separator DTI. This electrical separation is considered as a substantially insulated state. Although the electrical separation with the insulating separator DTI is described in the configuration illustrated inFIG.4, the well WSELmay be electrically separated from the well WPDusing electrical separation using PN junction. Accordingly, the electrical separation method of the wells is not limited to the separation method described in the first embodiment. However, the electrical separation with the insulating separator DTI is desirable because of greater electrical separation, compared with the electrical separation using the PN junction.

As described above, electrically separating the potential of the well WSELof the selection transistor M4from the well of the other pixel transistors enables the potential determined by the control signal SELBm through the control line23mto be supplied to the well WSEL.

The method of driving the photoelectric conversion apparatus in the first embodiment will now be describedFIG.5.

FIG.5is a driving timing chart for describing readout of signals in the unit pixel25in the first embodiment. The timing chart of control signals RES1to RES2, TX11to TX12, and SEL1to SEL2, which are supplied from the vertical drive circuit33to unit pixels25(1, n) to25(2, n) during horizontal scanning periods k to k+2 (k is an integer), is illustrated inFIG.5. The respective control signals are in an active state at the high level and are in a non-active state at the low level. Control signals SELB1to SELB2denote the potentials to be supplied to the well WSELof the selection transistor M4. The potential at the high level or the low level is supplied to the well WSELvia the well contact WCSEL.

No pixel signal is read out during a period from a time t0to a time t1. The control signals RES1to RES2are kept at the high level during this period. Accordingly, the on state of the reset transistor M2of each of the unit pixels25(1, n) to25(2, n) is kept and a reset operation of the FD node is continued. The control signals TX11to TX12, SEL1to SEL2, and SELB1to SELB2are kept at the low level. At this time, potential (first potential), such as negative potential, corresponding to the low level, is applied to the well WSELof the selection transistor M4.

A period from the time t1to a time t8corresponds to a readout period of the unit pixel25(1, n). The readout of the signals from the photoelectric conversion element PD in the unit pixel25(1, n) is performed during the period from the time t1to the time t8. At the time t2, the control signal SEL1makes the transition from the low level to the high level and the selection transistor M4in the unit pixel25(1, n) is in the on state. As a result, the unit pixel25(1, n) is electrically connected to the output line24n.

At the time t2, the control signal SELB1makes the transition from the low level to the high level and the potential, such as the ground potential, corresponding to the high level is applied to the well WSELof the selection transistor M4in the unit pixel25(1, n). The potential corresponding to the high level means potential (second potential) relatively higher than the potential applied to the well WSELduring the period from the time t0to the time t1.

At the time t3, the control signal RES1makes the transition from the high level to the low level and the reset transistor M2in the unit pixel25(1, n) is in the off state. As a result, the reset state of the FD node in the unit pixel25(1, n) is cleared. Then, the potential of the FD node is decreased to certain potential because of coupling with the gate of the reset transistor M2. The voltage of the FD node, which is statically determined after the reset transistor M2is in the off state, is used as reset voltage of the FD node in the unit pixel25(1, n).

The signal corresponding to the reset voltage of the FD node in the unit pixel25(1, n) is supplied to the output line24nvia the amplifier transistor M3and the selection transistor M4. Then, the signal is processed in the column signal processor34and is read out as an N signal of the unit pixel25(1, n).

At the time t4, the control signal TX11makes the transition from the low level to the high level and the transfer transistor M11in the unit pixel25(1, n) is in the on state. As a result, the electric charge accumulated in the photoelectric conversion element PD in the unit pixel25(1, n) during a certain exposure period is transferred to the FD node in the unit pixel25(1, n).

The signal corresponding to the amount of the electric charge transferred from the photoelectric conversion element PD to the FD node in the unit pixel25(1, n) is supplied to the output line24nvia the amplifier transistor M3and the selection transistor M4. The voltage of the output line24nis varied with the amount of the electric charge that has occurred in the photoelectric conversion element PD.

At the time t5, the control signal TX11makes the transition from the high level to the low level and the transfer transistor M11in the unit pixel25(1, n) is in the off state. As a result, the transfer period of the electric charge from the photoelectric conversion element PD to the FD node in the unit pixel25(1, n) is terminated. The signal supplied from the unit pixel25(1, n) to the output line24nis processed in the column signal processor34after the statical determination and is read out as an S signal of the photoelectric conversion element PD in the unit pixel25(1, n).

At the time t6, the control signal RES1makes the transition from the low level to the high level and the reset transistor M2in the unit pixel25(1, n) is in the on state. As a result, the reset operation of the FD node in the unit pixel25(1, n) is started.

At the time t7, the control signal SEL1makes the transition from the high level to the low level and the selection transistor M4in the unit pixel25(1, n) is in the off state. As a result, the unit pixel25(1, n) is not electrically connected to the output line24n.

At the time t7, the control signal SELB1makes the transition from the high level to the low level and the potential of the well WSELof the selection transistor M4in the unit pixel25(1, n) is set to the potential corresponding to the low level.

As described above, during the horizontal scanning period from the time t1to the time t8, the readout of the signals in the unit pixel25(1, n) is performed.

Then, a horizontal scanning period from the time t8to a time t15corresponds to a readout period of the unit pixel25(2, n). The readout of the signals from the photoelectric conversion element PD of the unit pixel25(2, n) is performed during the period from the time t8to the time t15. The respective control signals are driven in the same manner as in the previous horizontal scanning period described above. The scanning is sequentially performed to read out the signals from the entire pixel region.

The influence of the potential of the well WSELof the selection transistor M4on the linearity of the signal will now be described in detail with reference toFIG.6. The drain corresponding to the input of the selection transistor M4and the source corresponding to the output of the selection transistor M4will be described here, focusing on the linearity of the input and output signals.

The output signal from the selection transistor M4is generally calculated according to Equation (1):

Here, Vsdenotes the potential of the source of the selection transistor M4, VDdenotes the potential of the drain of the selection transistor M4, RONdenotes the on resistance of the selection transistor M4, and Iconstdenotes constant current determined by the current source included in the column signal processor34.

The on resistance RONof the selection transistor M4is generally calculated according to Equation (2):

Here, L denotes the gate length of the selection transistor M4, W denotes the gate width of the selection transistor M4, μ denotes the mobility of channeled electron of the selection transistor M4, COXdenotes the capacity per unit area of the selection transistor M4, and VTHdenotes threshold voltage of the selection transistor M4.

As indicated in Equation (1), voltage drop due to the constant current Iconstand the on resistance RONis desirably constant in order to keep the linearity with respect to the input and output of the selection transistor M4. However, as indicated in Equation (2), the on resistance RONhas a variable of voltage VGSbetween the gate and the source of the selection transistor M4. Accordingly, the on resistance RONof the selection transistor M4is varied with variation in the potential of the output line24nin response to the variation in the potential of the FD node. In other words, the on resistance RONis varied with the amount of signal occurring at the photoelectric conversion element PD to cause the reduction in the linearity.

For suppression of the reduction in the linearity in the readout of the signals (in the on state), the threshold voltage VTHof the selection transistor M4is desirably designed to be low in order to decrease the on resistance RONof the selection transistor M4. In contrast, the selection transistor M4has a function to electrically separate the amplifier transistor M3from the output line24nin the off state in which the signal in the low level is supplied from the control line23m.In other words, in consideration of the off state, the threshold voltage VTHis desirably designed to be high in order to suppress leakage current. Accordingly, it is effective to decrease the threshold voltage VTHin the on state while keeping the threshold voltage VTHin the off state in order to suppress the reduction in the linearity.

The threshold voltage VTHof the selection transistor M4is generally calculated according to Equation (3):

Here, VBSdenotes voltage between the well and the source of the selection transistor M4, VTH0denotes threshold voltage of the selection transistor M4when the voltage VBSis 0 V,2ΦFdenotes surface potential, and γ denotes a substrate effect parameter.

As indicated in Equation (3), the threshold voltage VTHof the selection transistor M4has a variable of the voltage VBSbetween the well and the source of the selection transistor M4. This is equivalent to the fact that well potential VBis a variable of the threshold voltage VTHwhen the potential of the source of the selection transistor M4is constant. Through the use of this, the unit pixel25of the first embodiment controls the well potential VBof the selection transistor M4in response to the control signal SELBm from the control line23mto vary the effective threshold voltage VTHbetween in the on state and in the off state. Accordingly, it is possible to suppress the leakage current of the selection transistor M4when the selection transistor M4is in the off state. In addition, it is possible to achieve the output of the pixel signal with the reduction in the linearity being suppressed when the selection transistor M4is in the on state.

More specifically, the well potential VBof the well WSEL, which is applied in the on state of the selection transistor M4, is set to a value relatively higher than that of the well potential VBapplied to the well WSELin the off state. For example, the ground potential may be set as the high level and the negative potential may be set as the low level. Under this condition, it is possible to decrease the threshold voltage VTHin the on state to keep the effective threshold voltage VTHin the off state, which is equivalent to that in a case in which the well potential VBof the well WSELis connected to the ground potential. The well potential VBof the well WSEL, which is applied in the on state of the selection transistor M4, may be equal to the potential of the well WPD. In other words, the well potential VBof the well WSELis lower than the potential of the well WPDduring the period in which the selection transistor M4is in the off state. The well potential VBof the well WSEL, which is applied in the on state of the selection transistor M4, may be higher than the potential of the well WPD.

The well potential VBof the well WSELis varied in the first embodiment. As another example, a configuration may be adopted in which the well potential VBof the well WSELis set to a value higher than the potential of the well WPDacross the entire period in which the photoelectric conversion apparatus is operating to suppress the reduction in the linearity of the pixel signal output from the selection transistor M4.

It is important in the first embodiment to realize the configuration in which the well WSELon which the selection transistor M4is provided is electrically separated from the well WPD. This enables the potential of the well WSELto be set independently of the well WPD. With this configuration, it is possible to achieve at least one of the suppression of the leakage current of the selection transistor M4and the acquisition of the pixel signal with the reduction in the linearity being suppressed.

Attention is focused here on the well potential VBin the on state of the selection transistor M4, which is relatively higher than the well potential VBin the off state. Since the effective threshold voltage VTHis decreased, as indicated in Equation (3), when the well potential VBis increased, the on resistance RONis decreased. Accordingly, as indicated in Equation (1), the decrease in the on resistance RONsuppresses the reduction in the linearity to enable the acquisition of the high-quality image.

The high level of the well potential VBof the selection transistor M4, supplied from the control signal SELBm, is set to the ground potential and the low level thereof is set to the negative potential in the first embodiment. However, the well potential VBis not limited to the above ones. As another example, the well potential VBmay be set to positive potential. In this case, it is desirable to set the well potential VBwithin a range in which the voltage between the well and the source and the voltage between the well and the drain are not directed to the forward direction.

The low level of the control signal SELm is desirably set to the potential equal to that of the low level of the control signal SELBm. More specifically, when the low level of the control signal SELBm is set to the negative potential, the low level of the control signal SELm is desirably set to the same negative potential.

The photoelectric conversion apparatus of the first embodiment is capable of deceasing the on resistance of the selection transistor M4to enable the acquisition of the high-quality image.

The relationship of the potentials is described in the first embodiment on the assumption that the selection transistor M4is the N-type transistor. As described above, the potentials may be appropriately changed in accordance with the change of the conductivity types of the transistors in the description of the specification. In other words, when the selection transistor M4is the P-type transistor, the well potential VBof the well WSEL, which is applied in the on state of the selection transistor M4, is set to a value relatively lower than the well potential VBapplied to the well WSELin the off state.

The configuration is exemplified in the first embodiment in which the well WPDon which the reset transistor M2is provided is electrically separated from the well WSELon which the selection transistor M4is provided. With this configuration, it is possible to achieve at least one of the suppression of the leakage current of the selection transistor M4and the acquisition of the pixel signal with the reduction in the linearity being suppressed.

The configuration of the unit pixel25may be appropriately varied. For example, the transfer transistor M11and the floating diffusion region may be omitted. In other words, the contact may be provided in a partial region of the photoelectric conversion element PD and the contact may be connected to the gate of the amplifier transistor M3. Also with this configuration, the potential of the well WSELmay be set independently of the well on which the reset transistor is provided. Although the multiple transistors composing the FD node in this case are the reset transistor M2and the amplifier transistor M3, a transistor to switch the capacitance value of the FD node may be further provided.

Second Embodiment

A second embodiment will now be described, focusing on the points different from the first embodiment.

FIG.7is a second equivalent circuit diagram of the unit pixel25in the second embodiment. A unit pixel25B (m, n) arrayed on the m-th line and the n-th column is illustrated inFIG.7. The unit pixel25B differs from the unit pixel25A in that a well WAMPon which the amplifier transistor M3is arranged is electrically separated from the well WSELand the well WPDand is electrically connected to the source of the amplifier transistor M3.

FIG.8illustrates a layout including the unit pixel25B corresponding to the equivalent circuit diagram inFIG.7and illustrates the four unit pixels25B of two lines and two columns in a plan view.

The second embodiment differs from the first embodiment in that the unit pixel25B is separated into at least three regions with the insulating separator DTI in a plan view. The selection transistor M4is arranged in a first region, the photoelectric conversion element PD is arranged in a second region, and the amplifier transistor M3is arranged in a third region. The insulating separator DTI is arranged so as to surround the selection transistor M4and the amplifier transistor M3. The insulating separator DTI has a function to separate the well WSELincluding the region serving as the channel of the selection transistor M4, the well WPDon which the photoelectric conversion element PD is arranged, and the well WAMPincluding a region serving as the channel of the amplifier transistor M3from each other.

The well WAMPis electrically connected to the source of the amplifier transistor M3via a well contact WCAMParranged on the well WAMP. The transfer transistor M11and the reset transistor M2are arranged on the well WPD. In other words, the insulating separator DTI is arranged between the selection transistor M4, the reset transistor M2, and the amplifier transistor M3.

FIG.9is a schematic cross-sectional view taken along the IX-IX line inFIG.8. The unit pixel25B differs from the unit pixel25A in that the insulating separator DTI separating the well WAMPof the amplifier transistor M3from the well WPDis added. The insulating separator DTI is configured so as to pass through the semiconductor substrate301. The well contact WCAMPof the well WAMPis arranged in the semiconductor substrate301and is composed of the P-type semiconductor region in which P-type impurities are diffused. The well contact WCAMPcomposes part of the first surface S1of the semiconductor substrate301.

In the unit pixel25B, the well WAMPis electrically separated from the well WSELand the well WPD. Since the source of the amplifier transistor M3is electrically connected to the well WAMP, the voltage VBSbetween the well and the source of the amplifier transistor is substantially fixed to 0 V. Accordingly, the threshold voltage VTHof the amplifier transistor M3due to a substrate bias effect is capable of being substantially kept constant. Consequently, the linear line of the pixel signal is less likely to be non-linear, compared with a case in which the well potential Vg of the amplifier transistor M3is connected to the ground potential.

As described above, in the unit pixel25B, it is possible to further suppress the reduction in the linearity of the signal due to the substrate bias effect of the amplifier transistor M3, in addition to the suppression of the reduction in the linearity by the selection transistor M4.

As described above, according to the second embodiment, the well WSELof the selection transistor M4is separated from the well WPDon which the photoelectric conversion element PD is arranged and the potential of the well WSELis controlled in the on state and the off state of the selection transistor M4to further suppress the reduction in the linearity of the signal.

Third Embodiment

A photoelectric conversion apparatus and a method of driving the photoelectric conversion apparatus according to a third embodiment will now be described with reference toFIG.10toFIG.20.FIG.10is a block diagram of the photoelectric conversion apparatus in the third embodiment.

As illustrated inFIG.10, a photoelectric conversion apparatus2includes three components: a first component10, a second component20, and a third component30. The photoelectric conversion apparatus2is a multilayer photoelectric conversion apparatus composed by bonding the three components. The first component10, the second component20, and the third component30are laminated in this order.

The first component10has a first semiconductor substrate11. Multiple sensor portions12performing the photoelectric conversion are provided on the first semiconductor substrate11. The multiple sensor portions12are arrayed in multiple lines and multiple columns in the pixel region13of the first component10. Each of the multiple sensor portions12includes the photoelectric conversion element PD and the transfer transistor M11. The multiple sensor portions12output the signal electric charge corresponding to the amount of incident light. The first component10includes various films, such as an insulating film, provided at the side of a second semiconductor substrate21, viewed from the first semiconductor substrate11.

The second component20has the second semiconductor substrate21. Read-out circuits22that output the pixel signals based on the electric charge output from the sensor portions12are provided on the second semiconductor substrate21. The read-out circuit22includes the pixel transistors. The second component20includes the multiple control lines23extending in the horizontal direction and the multiple output lines24extending in the vertical direction. The control lines23are connected to the vertical drive circuit33. Each of the output lines24is connected to the read-out circuits22arranged in the vertical direction to form a signal line common to the read-out circuits22. The output lines24are connected to the column signal processor34. The second component20includes various films, such as an insulating film, provided at at least one of the side of the first semiconductor substrate11and the side of a third semiconductor substrate31, viewed from the second semiconductor substrate21.

The third component30has the third semiconductor substrate31. A logic circuit32processing the pixel signals is provided on the third semiconductor substrate31. The logic circuit32includes, for example. the vertical drive circuit33, the column signal processor34, the horizontal drive circuit35, the output circuit36, and the system controller37. The third component30includes various films, such as an insulating film, provided at the side of the second semiconductor substrate21, viewed from the third semiconductor substrate31.

The first component10is laminated on the second component20by bonding the insulating film of the first component10to the insulating film of the second component20.

The second component20is laminated on the third component30by bonding the insulating film of the second component20to the insulating film of the third component30.

As described above, the photoelectric conversion apparatus of the third embodiment has the configuration in which the three components described above with reference toFIG.10are laminated. Among the components included in the unit pixel, the photoelectric conversion element PD is provided on the first semiconductor substrate11and the pixel transistors excluding the transfer transistor are provided on the second semiconductor substrate21in the third embodiment. This enables the space in which the pixel transistors are arranged to be easily ensured to further decrease the pixel pitch. Accordingly, it is possible to realize the photoelectric conversion apparatus appropriate for miniaturization.

FIG.11is a first equivalent circuit diagram of the unit pixel25in the third embodiment. A unit pixel25C (m, n) arrayed on the m-th line and the n-th column is illustrated inFIG.11. The unit pixel25C differs from the unit pixel25A on the equivalent circuit diagram in that the unit pixel25C has a configuration in which signals from four photodiodes PD1to PD4are transferred to FD1to FD4via transfer transistors M11to M14corresponding to the photodiodes PD1to PD4, respectively, and the signals are read out by the common read-out circuit22. Although the configuration is adopted inFIG.11in which the signals from the four photodiodes PD1to PD4are read out by one read-out circuit22, the photoelectric conversion elements PD of an arbitrary number may be connected to one read-out circuit22.

An FD capacitance switching transistor M5is arranged between the source of the reset transistor M2and the FD nodes in the configuration inFIG.11. A control signal FDGm is supplied from the vertical drive circuit33to the gate of the FD capacitance switching transistor M5. The capacitance value of the FD capacitance is capable of being varied by switching between the on state and the off state of the FD capacitance switching transistor M5to switch the conversion efficiency. In other words, the FD capacitance switching transistor M5is a transistor that switches between connection and non-connection of the capacitance to the gate of the amplifier transistor M3. This capacitance is of the FD capacitance switching transistor M5in the third embodiment. However, the capacitance is not limited to this example and, for example, a capacitance element may be provided on an electrical path between the reset transistor M2and the FD capacitance switching transistor M5. It is sufficient for this capacitance element to have the capacitance, such as a metal-insulator-metal (MIM) capacitance, a metal oxide metal (MOM) capacitance, a metal oxide silicon (MOS) capacitance, or a metal insulator silicon (MIS) capacitance. The MIM capacitance has a structure in which an insulating layer is sandwiched between multiple metal (including polysilicon) layers. The MOM capacitance has a structure in which an oxide film (including an oxynitride film), such as a silicon oxide film, is sandwiched between multiple metal (including polysilicon) layers. The MOS capacitance has a structure in which an oxide film (including an oxynitride film), such as a silicon oxide film, is sandwiched between a semiconductor layer and a metal (including polysilicon) layer in the silicon substrate. The MIS capacitance has a structure in which an insulating film is sandwiched between a semiconductor layer and a metal (including polysilicon) layer in the silicon substrate.

FIG.12is a cross-sectional view of the photoelectric conversion apparatus of the third embodiment. This cross-sectional view is taken along a line passing through the photoelectric conversion element PD and the gate of the transfer transistor M11in the first component10, the second component20, and the third component30. The photoelectric conversion element PD includes an N-type semiconductor region101. The two sensor portions12appearing on one cross section, among the four sensor portions12, are illustrated in the cross-sectional view inFIG.12.

The gate of the transfer transistor M11controls the conductive state between the photoelectric conversion element PD and a semiconductor region121, which is a region in the FD. The semiconductor region121is the N-type semiconductor region. A pixel separator201is provided between the multiple semiconductor regions101to electrically separate the multiple semiconductor regions101from each other. The pixel separator201may include an insulating portion made of silicon oxide or the like or may be a semiconductor region forming a potential barrier.

Typically, the pixel separator201is a semiconductor region using the electric charge having a polarity opposite to that of the signal electric charge accumulated in the photoelectric conversion element PD as a main carrier. A pixel serration layer211is provided between the pixel separator201and the semiconductor region101. The pixel serration layer211has a role of reducing dark current particularly when the pixel separator201is provided as the insulating portion. The semiconductor region121, which is the FD, is connected to the electrode M3G serving as the gate of the amplifier transistor M3via a conductor205. The conductor205mainly contains metal, such as tungsten or copper. The conductor205is formed so as to pass through an insulator251that separates the second semiconductor substrate21. The insulator251electrically separates the multiple read-out circuits22from each other. The insulator251is provided so as to pass through the semiconductor substrate21from a third surface F3, which one surface of the second semiconductor substrate21, to a fourth surface F4, which is the other surface thereof opposed to the third surface F3. The conductor205is a through electrode passing through the insulator251.

The first semiconductor substrate11has a first surface F1at the light incident surface side and a second surface F2opposed to the first surface F1. A semiconductor region221is the P-type semiconductor region provided in a region at the first surface F1side (the light incident surface side) of the semiconductor region101. A fixed electric charge film231is provided on the first surface F1of the first semiconductor substrate11. The dark current flowing into the semiconductor region101is reduced with the semiconductor region221and the fixed electric charge film231.

A microlens ML leads light to the semiconductor region101. A planarized layer241is provided between the microlens ML and the fixed electric charge film231. A color filter may be further provided for each of the multiple sensor portions12to perform color separation.

The first component10, the second component20, and the third component30are laminated. The second component20is provided between the first component10and the third component30. A transistor312is provided in the third semiconductor substrate31of the third component30. The second component20is electrically connected to the third component30via connection portions311. The connection portions311are made of metal. Typically, the connection portions311mainly contain copper. The connection portions311further contain barrier metal (for example, titanium or nickel) for suppressing the diffusion of copper.

The method of driving the photoelectric conversion apparatus in the third embodiment will be described below with reference toFIG.15. With the method of driving the photoelectric conversion apparatus in the third embodiment, the reduction in the linearity of the signal, which can be caused by the variation of the on resistance of the selection transistor M4in accordance with the potential of the floating diffusion region of each pixel, is capable of being suppressed.

FIG.13illustrates a layout including the unit pixel25C corresponding to the equivalent circuit diagram inFIG.11and illustrates the two unit pixels25C of one line and two columns in a plan view. The two unit pixels25C illustrated inFIG.13each correspond to the equivalent circuit diagram illustrated inFIG.11and the respective elements composing the unit pixel25C have the common configuration. An upper diagram inFIG.13illustrates the layout of the first component10inFIG.10in a plan view. A lower diagram inFIG.13illustrates the layout of the second component20inFIG.10in a plan view. The first component10is electrically connected to the second component20via multiple through electrodes47, multiple through electrodes48, and multiple through electrodes54. The through electrodes54illustrated inFIG.13are part of the conductor205illustrated inFIG.12.

As illustrated inFIG.13, the second component20is composed of the second semiconductor substrate21and the region of an insulating layer53including the through electrodes54and so on in a plan view. The pixel transistors included in the read-out circuit22are arranged in the region of the second semiconductor substrate21.

The amplifier transistor M3is arranged on the well common to the reset transistor M2and the FD capacitance switching transistor M5, which are arranged in the read-out circuit22adjacent to the amplifier transistor M3at the right side in a plan view.

The insulating separator DTI is arranged so as to surround the selection transistor M4. Accordingly, the well WSELof the selection transistor M4is electrically separated from the well WAMPincluding the other pixel transistors.

FIG.14is a schematic cross-sectional view taken along the XIV-XIV line inFIG.13. Referring toFIG.14, the well WSELon which the selection transistor M4is arranged is electrically separated from the well WAMPon which the amplifier transistor M3and so on are arranged with the insulating separator DTI.

FIG.16is a second equivalent circuit diagram of the unit pixel25in the third embodiment. A unit pixel25D (m, n) arrayed on the m-th line and the n-th column is illustrated inFIG.16. The unit pixel25D differs from the unit pixel25C in that the well WAMPon which the amplifier transistor M3is arranged is electrically separated from the well WSELand a well WRESand is electrically connected to the source of the amplifier transistor M3.

FIG.15is a driving timing chart for describing readout of signals in the unit pixel25in the third embodiment. The control signals RES1to RES2to be supplied from the vertical drive circuit33to the unit pixels25(1, n) to25(2, n) during horizontal scanning periods k to k+8(k is an integer) are illustrated inFIG.15. In addition, control signals TX11to TX42, the control signals SEL1to SEL2, and the control signals SELB1and SELB2, which are to be supplied from the vertical drive circuit33to the unit pixels25(1, n) to25(2, n), are illustrated inFIG.15.

A period from a time t21to a time t43corresponds to the readout period from the unit pixel25(1, n). The readout of the signals from the photoelectric conversion elements PD1to PD4in the unit pixel25(1, n) is performed during the period from the time t21to the time t43. The signal of one PD is read out during each horizontal scanning period and the signals of the four PDs are read out during the four horizontal scanning periods. A period from the time t22to the time t42is a period in which the unit pixels25in the line including the unit pixel25(1, n) are selected. The control signal SEL1and the control signal SELB1are fixed to the high level during the period from the time t22to the time t42.

A period from the time t43to a time t65corresponds to the readout period from the unit pixel25(2, n). The readout of the signals from the photoelectric conversion elements PD1to PD4in the unit pixel25(2, n) is performed during the period from the time t43to the time t65. A period from the time t44to the time t64is a period in which the unit pixels25in the line including the unit pixel25(2, n) are selected. The control signal SEL2and the control signal SELB2are fixed to the high level during the period from the time t44to the time t64.

The potential of the high level is applied to the well WSELof the selection transistor M4with the control signal SELBm at the timing when the selection transistor M4is in the on state also in the third embodiment. This makes the well potential VBin the on state of the selection transistor M4relatively higher than the well potential VBin the off state thereof. Since the effective threshold voltage VTHis decreased when the well potential VBis made high, the on resistance RONof the selection transistor M4is decreased.

The decrease in the on resistance of the selection transistor M4suppresses the reduction in the linearity to enable the acquisition of the high-quality image.

FIG.17illustrates a layout including the unit pixel25D corresponding to the equivalent circuit diagram inFIG.16and illustrates the two unit pixels25D of one line and two columns in a plan view. An upper diagram inFIG.17illustrates the layout of the first component10inFIG.10in a plan view. A lower diagram inFIG.17illustrates the layout of the second component20inFIG.10in a plan view.

The layout of the unit pixel25D differs from the layout of the unit pixel25C in that the amplifier transistor M3is also surrounded by the insulating separator DTI. This causes the well WSEL, the well WAMP, and the well WRESto be electrically separated from each other. The well WSELis a region including the region serving as the channel of the selection transistor M4. The well WAMPis a region including the region serving as the channel of the amplifier transistor M3. The well WRESis a region including regions serving as the channels of the reset transistor M2and the FD capacitance switching transistor M5.

FIG.18is a schematic cross-sectional view taken along the XVIII-XVIII line inFIG.17. The well WSELon which the selection transistor M4is arranged, the well WAMPon which the amplifier transistor M3and so on are arranged, and the well WRESon which the reset transistor M2and the FD capacitance switching transistor M5are arranged are electrically separated from each other with the insulating separator DTI.

Since the well WAMPis physically separated from the well WSELand the well WRESand the source of the amplifier transistor M3is electrically connected to the well WAMPin the unit pixel25D, the voltage VBSbetween the well and the source of the amplifier transistor is fixed to 0 V. Accordingly, the threshold voltage VTHof the amplifier transistor M3due to the substrate bias effect is capable of being kept constant. Consequently, the linear line of the signal is less likely to be non-linear, compared with a case in which the well potential VBis connected to the ground potential.

As described above, in the unit pixel25D, it is possible to suppress the reduction in the linearity of the signal due to the substrate bias effect of the amplifier transistor M3, in addition to the suppression of the reduction in the linearity by the selection transistor M4.

As described above, according to the third embodiment, the well WSELof the selection transistor M4is separated from the wells on which the other pixel transistors are arranged and the potential of the well WSELis controlled in the on state and the off state of the selection transistor. Accordingly, it is possible to suppress the reduction in the linearity of the signal output from the unit pixel. In addition, it is possible to reduce the leakage current of the selection transistor.

FIG.19illustrates the layout of the second component20including the unit pixel25C corresponding to the equivalent circuit diagram inFIG.11and illustrates the nine unit pixels25C of three lines and three columns in a plan view.

As illustrated inFIG.19, the pixel transistors arranged in the read-out circuits22have the layout configuration sharing the wells of the same potential, which are adjacent in the horizontal direction and the vertical direction. More specifically, the well WSELof the selection transistor M4and the well WAMPof the amplifier transistor M3are shared between the adjacent two lines and the adjacent two columns. The well WRESis shared between the reset transistors M2and the FD capacitance switching transistors M5in the read-out circuits22adjacent in the vertical direction.

Sharing the wells of the same potential, which are adjacent in the horizontal direction and the vertical direction, enables the number of the well contacts arranged on the wells to be decreased to improve the layout efficiency. More specifically, one well contact WCAMPis arranged for the well WAMPof the four sharing amplifier transistors M3and one well contact WCSELis arranged for the well WSELof the four sharing selection transistors M4. In addition, sharing the wells enables variation in the potential between the wells to be suppressed to realize the layout effective for the layout efficiency and the suppression of the variation in the potential.

FIG.20illustrates the layout of the second component20including the unit pixel25D corresponding to the equivalent circuit diagram inFIG.16and illustrates the nine unit pixels25D of three lines and three columns in a plan view.

Sharing the wells of the same potential, which are adjacent in the horizontal direction and the vertical direction, realizes the layout effective for the layout efficiency and the suppression of the variation in the potential also in the layout configuration illustrated inFIG.20, as in the layout configuration illustrated inFIG.19.

The above embodiments are only specific examples to embody the disclosure and the technical range of the disclosure is not limitedly interrupted by the above embodiments. In other words, the disclosure is capable of being realized in various modes without departing from the technical scope or the main features of the disclosures.

Fourth Embodiment

A fourth embodiment is applicable to the first to third embodiments.

FIG.21Ais a schematic diagram for describing equipment9191including a photoelectric conversion apparatus930of the fourth embodiment. The photoelectric conversion apparatus930may be any of the photoelectric conversion apparatuses described in the first to third embodiments or may be a photoelectric conversion apparatus resulting from combination of multiple embodiments. The equipment9191including the photoelectric conversion apparatus930will now be described in detail. The photoelectric conversion apparatus930may include a semiconductor device910including a semiconductor layer and a package920containing the semiconductor device910. The package920may include a base substrate to which the semiconductor device910is fixed and a cover body made of glass or the like, which is opposed to the semiconductor device910. The package920may further include a joint member, such as boding wire or bumps, with which terminals provided on the base substrate are connected to terminals provided on the semiconductor device910.

The equipment9191includes at least one of an optical apparatus940, a control apparatus950, a processing apparatus960, a display apparatus970, a storage apparatus980, and a mechanical apparatus990. The optical apparatus940corresponds to the photoelectric conversion apparatus930. The optical apparatus940includes, for example, a lens, a shutter, or a mirror. The control apparatus950controls the photoelectric conversion apparatus930. The control apparatus950is a control unit, such as an application specific integrated circuit (ASIC).

The processing apparatus960processes a signal output from the photoelectric conversion apparatus930. The processing apparatus960is a semiconductor unit, such as a central processing unit (CPU) or the ASIC, for composing an analog front end (AFE) or a digital front end (DFE). The display apparatus970is an electroluminescence (EL) display or a liquid crystal display that displays information (an image) acquired by the photoelectric conversion apparatus930.

The storage apparatus980is a magnetic device or a semiconductor device that stores the information (the image) acquired by the photoelectric conversion apparatus930. The storage apparatus980is a volatile memory, such as a static random access memory (SRAM) or a dynamic RAM (DRAM), or a non-volatile memory, such as a flash memory or a hard disk drive.

The mechanical apparatus990includes a movable portion, such as a motor and/or an engine, or a propulsion portion. In the equipment9191, the signal output from the photoelectric conversion apparatus930is displayed in the display apparatus970or is externally transmitted with a communication unit (not illustrated) provided in the equipment9191. Accordingly, the equipment9191desirably further includes the storage apparatus980and the processing apparatus960, in addition to a storage circuit and an operational circuit in the photoelectric conversion apparatus930. The mechanical apparatus990may be controlled based on the signal output from the photoelectric conversion apparatus930.

In addition, the equipment9191is appropriate for electronic equipment, such as an information terminal (for example, a smartphone or a wearable terminal) and a camera (for example, an interchangeable lens camera, a compact camera, a video camera, or a monitoring camera), which has an imaging function. The mechanical apparatus990in the camera is capable of driving components in the optical apparatus940for zooming, focusing, and a shutter operation. Alternatively, the mechanical apparatus990in the camera is capable of moving the photoelectric conversion apparatus930for an image stabilizing operation.

Furthermore, the equipment9191may be transport equipment, such as a vehicle, a ship, or a flight vehicle. The mechanical apparatus990in the transport equipment may be used as a moving apparatus. The equipment9191serving as the transport equipment is desirable for equipment that transports the photoelectric conversion apparatus930and equipment that performs assistance and/or automation of driving (steering) using the imaging function. The processing apparatus960for the assistance and/or the automation of driving (steering) is capable of performing a process to operate the mechanical apparatus990serving as the moving apparatus based on the information acquired by the photoelectric conversion apparatus930. Alternatively, the equipment9191may be medical equipment such as an endoscope, measuring equipment such as a focusing sensor, analysis equipment such as an electronic microscope, a business machine such as a copier, or industrial equipment such as a robot.

According to the fourth embodiment described above, it is possible to achieve excellent pixel features. Accordingly, it is possible to improve the value of the photoelectric conversion apparatus. The improvement of the value here corresponds to at least one of addition of a function, improvement of performance, improvement of features, improvement of reliability, improvement of manufacturing yield, reduction in environmental load, reduction of cost, reduction of size, and weight saving.

Accordingly, the use of the photoelectric conversion apparatus930according to the fourth embodiment in the equipment9191enables the value of the equipment to be also improved. For example, it is possible to achieve the excellent performance when the photoelectric conversion apparatus930is mounted in transport equipment to perform imaging of the outside of the transport equipment or measurement of external environment. Consequently, the mounting of the photoelectric conversion apparatus according to the fourth embodiment in the transport equipment has an advantage in improvement of the performance of the transport equipment itself in manufacturing and selling of the transport equipment. In particular, the photoelectric conversion apparatus930is desirable for the transport equipment that performs operation support and/or automated driving of the transport equipment using the information acquired by the photoelectric conversion apparatus.

A photoelectric conversion system and a moving body of the fourth embodiment will now be described with reference toFIG.21BandFIG.21C.

FIG.21Billustrates an example of the photoelectric conversion system concerning an in-vehicle camera. A photoelectric conversion system8includes a photoelectric conversion apparatus80. The photoelectric conversion apparatus80is the photoelectric conversion apparatus (the imaging apparatus) described in any of the above embodiments. The photoelectric conversion system8includes an image processor801and a parallax acquirer802. The image processor801performs image processing to multiple pieces of image data acquired by the photoelectric conversion apparatus80. The parallax acquirer802calculates the parallax (the phase difference in a parallax image) from the multiple pieces of image data acquired by the photoelectric conversion system8. The photoelectric conversion system8further includes a distance acquirer803and a collision determiner804. The distance acquirer803calculates the distance to a target object based on the calculated parallax. The collision determiner804determines whether the possibility of collision exists based on the calculated distance. The parallax acquirer802and the distance acquirer803are examples of a distance information acquirer that acquires distance information to the target object. In other words, the distance information is information about the parallax, the amount of de-focusing, the distance to the target object, and so on. The collision determiner804may determine the possibility of collision using any distance information. The distance information acquirer may be realized by hardware that is designed for exclusive use or may be realized by a software module. Alternatively, the distance information acquirer may be realized by a field programmable gate array (FPGA), the ASIC, or the like or may be realized by combination of the above ones.

The photoelectric conversion system8is connected to a vehicle information acquisition apparatus810and is capable of acquiring vehicle information, such as a vehicle speed, a yaw rate, and a rudder angle. In addition, the photoelectric conversion system8is connected to a control electronic control unit (ECU)820, which is a control unit that outputs a control signal to cause the vehicle to generate braking force based on the result of determination in the collision determiner804. The photoelectric conversion system8is also connected to a warming apparatus830that issues a warning to a driver based on the result of determination in the collision determiner804. For example, when the possibility of collision is high as the result of determination in the collision determiner804, the control ECU820performs vehicle control to avoid the collision and reduce the damage by, for example, applying the brake to the vehicle, releasing the accelerator, or suppressing the engine output. The warming apparatus830issues the warning to a user by, for example, sounding an alarm, displaying warning information on the screen of a car navigation system or the like, vibrating the sheet belt or the steering.

In the fourth embodiment, an image of the circumference of the vehicle, for example, a forward image or a backward image of the vehicle is captured by the photoelectric conversion system8.

FIG.21Cillustrates the photoelectric conversion system when a forward image of the vehicle (an image within an imaging range850ahead of the vehicle) is captured. The vehicle information acquisition apparatus810gives an instruction to the photoelectric conversion system8or the photoelectric conversion apparatus80. With such a configuration, it is possible to improve the accuracy of the focusing.

Although the example is described above in which the control is performed so as not to collide with another vehicle, the photoelectric conversion system is applicable to control in which the automated driving is performed while tracking another vehicle, control in which the automated driving is performed so as not to run over the traffic lane, and so on. In addition, the photoelectric conversion system is not limited to the vehicle, such as a vehicle to be applied, and is applicable to a movable body (the moving apparatus), such as a ship, an aircraft, or an industrial robot. In addition, the photoelectric conversion system is not limited to the moving body and is applicable to equipment, such as an intelligent transport system (ITS), that widely uses object recognition.

The embodiments described above may be appropriately modified without departing from the technical idea. The content disclosed in the specification is not limited to the one described in the specification and includes all the matters capable of being understood from the specification and the drawings appended to the specification. The content disclosed in the specification includes complements of the ideas described in the specification. Specifically, for example, when “A is greater than B” is described in the specification, the specification discloses “A is not greater than B” even if description of “A is not greater than B” is omitted. This is because it is assumed that the case in which “A is not greater than B” is considered when “A is greater than B” is described.

With the technique in the disclosure, it is possible to appropriately set the potential of the well of the selection transistor.

This application claims the benefit of priority from Japanese Patent Application No. 2022-165393, filed Oct. 14, 2022, which is hereby incorporated by reference herein in its entirety.