Display apparatus and method of manufacturing the same

In a display apparatus and a manufacturing method of the display apparatus, the display apparatus includes a display panel having signal lines and an insulating layer, and a signal generator electrically connected to the signal lines and adhering to the display panel. The signal lines include pads formed at ends thereof, respectively. The organic insulating layer is partially removed such that the via holes are formed between the pads of the signal lines to reduce a step-difference between an area in which the pads are formed and an area in which the pads are not formed. Thus, the display apparatus may enhance the coupling force between the signal generator and the display panel.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to Korean Patent Application No. 2005-12660, filed on Feb. 16, 2005, the content of which is hereby incorporated by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a display apparatus and a method of manufacturing the same. More particularly, the present invention relates to a display apparatus capable of improving production yield and a method of manufacturing the display apparatus.

2. Description of the Related Art

In general, a liquid crystal display apparatus displays an image using optical and electrical properties of liquid crystal, such as an anisotropic refractive index and an anisotropic dielectric constant. The liquid crystal display apparatus requires a backlight assembly since its display panel is not self-emissive. The backlight assembly supplies the light source for the liquid crystal display panel displaying the image thereon.

The liquid crystal display panel includes gate lines and data lines to transmit an image signal. The liquid crystal display panel receives the image signal from a driving chip and a flexible printed circuit board coupled thereto through the gate and data lines.

The gate and data lines include a pad formed at ends thereof and electrically connected to the driving chip and the flexible printed circuit board. The pad includes an insulating layer formed on an upper face thereof and a transparent electrode formed on the insulating layer. The insulating layer is partially removed to form a via hole such that the pad is exposed through the via hole. When removing the pad, the insulating layer remains between the pad and an adjacent pad. This occurs because the transparent electrode is easily separated from a lower layer thereunder when the insulating layer is completely removed from an area where the flexible printed circuit board is attached to the liquid crystal display panel.

The transparent electrode is electrically connected to the pad through the via hole. The driving chip and the flexible printed circuit board disposed on the transparent electrode and electrically connected thereto are attached to the liquid crystal display panel by means of an anisotropic conductive film.

However, the via hole of the insulating layer is formed using a slit mask, so that the insulating layer has a slit shape. Thus, the anisotropic conductive film is easily separated from the liquid crystal display panel due to a step-difference between the via hole area and a peripheral area adjacent to the via hole area. As a result, the driving chip and the flexible printed circuit board are electrically opened with the pad; therefore, the liquid crystal display apparatus displays the image abnormally.

SUMMARY OF THE INVENTION

In one exemplary embodiment of the present invention, a display apparatus includes a display panel and a signal generator. The display panel includes a substrate having a first area to display an image in response to an image signal, a second area adjacent to the first area, and a plurality of signal transmitting lines to transmit the image signal. The signal transmitting lines are formed on the substrate and include pads formed at ends thereof, respectively. The insulating layer is formed on the substrate to cover the signal transmitting lines. The insulating layer is partially removed from a corresponding area between the pads so as to form a first via hole. The signal generator applies the image signal to the signal transmitting lines and is formed in the second area and electrically connected to the pad.

In another exemplary embodiment of the present invention, a method of manufacturing a display apparatus is provided. According to the method, a plurality of signal transmitting lines is formed on a substrate to transmit an image signal. The substrate has a first area displaying an image in response to the image signal and a second area adjacent to the first area. An insulating layer is formed on the substrate to cover the signal transmitting lines. The insulating layer is partially removed from a corresponding area between the pads so as to form a first via hole. A signal generator is mounted on the substrate corresponding to the second area so as to transmit the image signal to the signal transmitting lines.

Accordingly, the step-difference between the areas in which the pads are formed and the areas in which the pads are not formed may be reduced due to the via hole. Thus, the display apparatus according to exemplary embodiments of the present invention may enhance the coupling force between the signal generator and the display panel and improve production yield thereof.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

FIG. 1is a plan view showing a liquid crystal display apparatus according to an exemplary embodiment of the present invention. Referring toFIG. 1, a liquid crystal display apparatus500includes a liquid crystal display panel300that displays an image using an image signal, a driving chip420that outputs data and gate control signals to drive the liquid crystal display panel300, a gate driving circuit440that outputs a gate signal in response to the gate control signal, and a flexible printed circuit board460that applies the image signal to the driving chip420.

The liquid crystal display panel300is divided into a display area DA on which an image is displayed and a peripheral area PA on which the image is not displayed that is adjacent to the display area DA. The liquid crystal display panel300includes a first substrate100, a second substrate facing the first substrate200, and a liquid crystal layer (not shown) disposed between the first and second substrates100and200.

The first substrate100includes a plurality of data lines DL to transmit a data signal, a plurality of gate lines GL substantially perpendicular to the data lines DL to transmit a gate signal, a plurality of thin film transistor (TFT) connected to the data and gate lines DL and GL, and a pixel electrode130connected to the TFT120. The data lines DL transmit the data signal applied from the driving chip420. Although not shown, each of the data lines DL includes a pad formed at an end thereof and each is electrically connected to the driving chip420. The gate lines GL are electrically connected to the gate driving circuit440and transmit the gate signal applied from the gate driving circuit440.

The TFT120that operates as a switching device is formed in the display area DA. The TFT120applies a signal voltage to pixel areas defined by the data lines and the gate lines. The pixel electrode130applies the signal voltage applied from the TFT120to the liquid crystal layer.

The second substrate200disposed on the first substrate100includes a color filter layer on which RGB pixels (not shown) are formed by a thin film process.

The driving chip420is mounted on the first substrate100corresponding to a data side of the peripheral area PA. The driving chip420may have two or more chips for the data lines and the gate lines, or the data lines and the gate lines can be integrated into one chip. The driving chip420is mounted on the first substrate111by a chip-on-glass (COG) process and electrically connected to the data lines DL and the gate driving circuit440.

The gate driving circuit440is formed on the first substrate100corresponding to a gate side of the peripheral area PA. The gate driving circuit440is formed in the peripheral area PA of the first substrate100when the TFT120is formed. The gate driving circuit440may be formed inside the driving chip420, or mounted on the peripheral area PA of the first substrate100as a separation chip type. In the case that the gate driving circuit440is formed inside the driving chip420, the driving chip420is electrically connected to the gate lines GL and outputs the gate signal to the gate lines GL.

The flexible printed circuit board460is formed on the first substrate100corresponding to the data side of the peripheral area PA. The flexible printed circuit board460is electrically connected to a plurality of output lines OL formed on the first substrate100. The output lines OL apply various signals outputted from the flexible printed circuit board460to the driving chip420.

FIG. 2is a cross-sectional view showing the first substrate illustrated inFIG. 1. Referring toFIG. 2, the first substrate100includes a transparent substrate110, the TFT120formed on the transparent substrate120, a passivation layer140formed on the transparent substrate110on which the TFT120is formed, an organic insulating layer150formed on the passivation layer140, and a pixel electrode130formed on the organic insulating layer150.

The TFT120includes a gate electrode121formed on the transparent substrate110, a gate insulating layer122formed on the transparent substrate110to cover the gate electrode121, an active layer123formed on the gate insulating layer122, an ohmic contact layer124formed on the active layer123, a source electrode125that is partially formed on the ohmic contact layer124, and a drain electrode126that is also partially formed on the ohmic contact layer124.

The gate electrode121is branched from one of the gate lines GL that transmits the gate signal. An example of the gate electrode121may include a conductive metal material, for example, such as an aluminum alloy like aluminum neodymium (AlNd), chrome (Cr), Molybdenum (Mo) and so on. In various exemplary embodiments of the present invention, the gate electrode121may be a single- or multi-layer structure such as a double-layer or a triple-layer structure.

The gate insulating layer122is formed on the transparent substrate110on which the gate electrode121is formed such that the gate insulating layer122also covers the gate electrode121. The gate insulating layer122includes an insulating material such as silicon oxide (SiO2), silicon nitride (SiNx) or the like.

The active layer123on the gate insulating layer122is formed on an area corresponding to the gate electrode121. The active layer123may include amorphous silicon to form an amorphous silicon TFT. The ohmic contact layer124on the active layer123includes n+amorphous silicon, and is partially removed so as to expose a center portion of the active layer123, thereby forming a channel region CA.

The source and drain electrodes125and126are formed on the ohmic contact layer124. The source and drain electrodes125and126may comprise a conductive metal material, for example, such as aluminum alloy like aluminum neodymium (AlNd), chrome (Cr), Molybdenum (Mo) and so on. In various exemplary embodiments of the present invention, each of the source and drain electrodes125and126may be a single- or multi-layer structure such as a double-layer or a triple-layer structure. The source electrode125is branched from one of the data lines DL that transmits the data signal. The source electrode125includes a first end disposed on the ohmic contact layer124and a second end disposed on the gate insulating layer122which is opposite to the first end. The drain electrode126is spaced apart from the source electrode125by the channel region CA. The drain electrode126includes a first end disposed on the ohmic contact layer124and a second end disposed on the gate insulating layer122which is opposite to the first end.

The passivation layer140on the TFT140protects the TFT120and various lines such as the gate lines GL, the data lines DL and the output lines OL. In an exemplary embodiment of the present invention, the passivation layer140includes an inorganic insulating layer such as silicon oxide (SiO2), silicon nitride (SiNx) or the like, and has a thickness of about 2000 angstroms.

The organic insulating layer150is formed on the passivation layer140. The organic insulating layer150is partially exposed to form a slit shape. The passivation layer140and the organic insulating layer150are partially removed to form a contact hole CH through which the drain electrode126is partially exposed. The pixel electrode130on the organic layer150is electrically connected to the drain electrode126through the contact hole CH. According to an exemplary embodiment of the present invention the pixel electrode130may comprise a transparent conductive material such as indium tin oxide ITO or indium zinc oxide IZO.

Although not shown inFIGS. 1 and 2, the liquid crystal display apparatus may further include a reflection electrode formed on the pixel electrode130so as to reflect a light externally provided.

FIG. 3is a cross-sectional view showing a first substrate according to another exemplary embodiment of the present invention. Referring toFIG. 3, a first substrate600has a same function and structure as that of the first substrate100shown inFIG. 2(except for a TFT610and a capacitor620), and thus further description will be omitted. InFIG. 3, the same reference numerals denote the same elements as illustrated inFIG. 1.

The first substrate600includes a transparent substrate110, the TFT610formed on the transparent substrate110, a capacitor620, a passivation layer140formed on the transparent substrate110and the capacitor620, an organic insulating layer150formed on the passivation layer140, and a pixel electrode130formed on the organic insulating layer150.

The TFT610includes first and second active layers611and612formed on the transparent substrate110, a gate insulating layer613formed on the transparent substrate110to cover the first and second active layers611and612, a gate electrode614formed on the gate insulating layer613, an interlayer dielectric (ILD) layer615formed on the gate insulating layer613to cover the gate electrode614, a source electrode616and a drain electrode617.

The first and second active layers611and612may include low-temperature polycrystalline silicon and are spaced from each other by a predetermined distance, thereby forming a low-temperature polycrystalline silicon TFT. The first active layer611includes a channel region611a, a source region611band a drain layer611c. The channel region611ais formed in an area overlapped with the gate electrode614, and the source and drain layer611band611care formed by implanting impurities in areas adjacent to both sides of the channel region611a. Impurity regions611dare formed between the channel region611aand the source region611band between the channel region611aand the drain region611c, respectively.

The gate insulating layer613is formed on the transparent substrate110to cover the first and second active layers611and612. According to an exemplary embodiment of the present invention, the gate insulating layer613has a thickness of about 1000 angstroms.

The gate lines GL, the gate electrode614and a first electrode621of the capacitor620are formed on the gate insulating layer613. The gate electrode614is formed on the gate insulating layer613corresponding to the first active layer611, and the first electrode621of the capacitor620is formed on the gate insulating layer613corresponding to the second active layer612.

The ILD layer615is formed on the gate insulating layer613on which the gate lines GL, the gate electrode614and the first electrode621are formed. The ILD layer615may be a single layer comprising silicon oxide (SiO2) or a double layer comprising silicon oxide (SiO2) and silicon nitride (SiNx). The gate insulating layer613and the ILD layer615are partially removed to expose the source and drain regions611band611cof the first active layer611.

The data lines DL, source electrode616branched from the data lines DL, drain electrode617and a second electrode622of the capacitor622are formed on the ILD layer615. The source electrode616is electrically connected to the source region611bof the first active layer611, and the drain electrode617is electrically connected to the drain region611cof the first active layer611. The second electrode622of the capacitor620is formed on the ILD layer615such that the second electrode622is overlapped with the first electrode621. Thus, the ILD layer615disposed between the first and second electrodes621and622acts as a dielectric layer of the capacitor620.

The passivation layer140and the organic insulating layer150are sequentially formed on the ILD layer615on which the source electrode616, the drain electrode617and the second electrode622are formed. The organic insulating layer150and the passivation layer140are sequentially partially removed to expose the second electrode622through a contact hole CH. In an embodiment of the present invention, the passivation layer140has a thickness of about 2000 angstroms and the organic insulating layer150has a thickness of about 3.6 micrometers.

The pixel electrode130is formed on the organic layer150. The pixel electrode130is electrically connected to the drain electrode126through the contact hole. Although not shown inFIG. 3, the liquid crystal display apparatus may further include a reflection electrode formed on the pixel electrode130so as to reflect a light externally provided.

FIG. 4is a plan view showing a peripheral area of the first substrate illustrated inFIG. 1. Referring toFIGS. 1 and 4, the peripheral area PA includes a first peripheral area PA1in which the output lines OL are formed and a second peripheral area PA2in which the output lines OL are not formed that is adjacent to the first peripheral area PA1. The flexible printed circuit board460is attached to the first and second peripheral area PA1and PA2.

The output lines OL are spaced apart from each other. Each of the output lines OL includes a pad formed at a first end thereof adjacent to the flexible printed circuit board460. The pad is electrically connected to the flexible printed circuit board460. Although not shown inFIG. 4, each of the output lines OL also includes a pad formed at a second end thereof adjacent to the driving chip420; the pads are electrically connected to the driving chip420.

The organic insulating layer150is formed on the output lines OL. The organic insulating layer150is formed in the first peripheral area PA1so as to protect the output lines OL. Although not shown inFIG. 4, the passivation layer140under the organic insulating layer150is formed in the first peripheral area PA1. The organic insulating layer150is partially removed to form a plurality of first via holes VH1between pads adjacent to each other. Thus, a portion of the organic insulating layer150between a first pad IP1and a second pad IP2is partially removed, so that the first vial holes VH1is formed between the first pad IP1and the second pad IP2.

The first output line OL1and the second output line OL2adjacent to the first output line OL1include the first pad IP1and the second pad IP2formed at ends thereof, respectively. When the organic insulating layer150is partially removed, a plurality of via holes VH1is formed between the first pad IP1of the first output line OL1and the second pad IP2of the output line OL2.

Although not shown inFIG. 5, the first via holes VH1are also formed at the second end of the output lines OL and ends of the data lines DL.

The organic insulating layer150is partially removed to expose the pads connected to first ends of the output lines OL through a plurality of second via holes VH2. Thus, the first and second pads IP1and IP2are exposed through the second via holes VH2.

A plurality of transparent electrodes160is formed on the organic insulating layer150and electrically connected to the pads formed at the first end of the output lines OL. The transparent electrodes160include a same material as the pixel electrode130and are in a one-to-one relation with the pads formed at the first end of the output lines OL.

FIG. 5is an enlarged plan view of a portion ‘A’ inFIG. 4. Referring toFIG. 5, two first via holes VH1_1and VH1_2adjacent to each other are spaced apart from each other by a predetermined distance. In case that the two first via holes VH1_1and VH1_2are so close to each other, the organic insulating layer150formed between the two first via holes VH1_1and VH1_2may be separated from a lower layer thereunder. In order to prevent the separation of the organic insulating layer150, an interval W1between the two first via holes VH1_1and VH1_2is equal to or greater than about 70% of a width W2of one of the first via holes VH1.

In case that the first via holes VH1and the second via hole VH2are so close to each other, the organic insulating layer150formed between the first via holes VH1and the second via holes VH2may be separated from the lower layer thereunder. To prevent the separation of the organic insulating layer150, according to an exemplary embodiment of the present invention, an interval W3between the first via holes VH1and the first pad IP1and between the first via holes VH1and the second pad IP2is equal to or greater than about 70% of the width W2of one of the first via holes VH1.

FIG. 6is a plan view showing another exemplary embodiment of a peripheral area of a first substrate inFIG. 4. Referring toFIG. 6, the first via hole VH1is disposed between two pads IP1and IP2adjacent to each other and extended along a longitudinal direction of the pads IP1and IP2. In the present embodiment, only one first via hole among the first via holes VH1is disposed between two pads, for example, first and second pads IP1and IP2adjacent to each other. The first via hole has a length substantially identical with that of the pads IP1and IP2.

FIG. 7is a cross-sectional view taken along a line I-I′ showing the peripheral area of the first substrate illustrated inFIG. 4. In the present embodiment, a first output line OL1among the output lines OL and the first pad IP1will be described since the output lines OL and the first pad IP1have same function and structure. Referring toFIGS. 4 and 7, the first output line OL1is formed on the gate insulating layer122on the transparent substrate110. The first pad IP1formed at the first end of the first output line OL1is formed in the first peripheral area PA1.

The passivation layer140and the organic insulating layer150are formed on the gate insulating layer122on which the first output line OL1is formed. The passivation layer140and the organic insulating layer150are partially removed to form the first and second via holes VH1and VH2.

The transparent electrode160formed on the organic insulating layer150is electrically connected to the first pad IP1.

FIG. 8is a cross-sectional view showing the first substrate coupled to a flexible printed circuit board illustrated inFIG. 1. Referring toFIG. 8, the flexible printed circuit board460is attached to the first and second peripheral areas PA1and PA2of the first substrate100. The flexible printed circuit board460includes a base substrate461and wires (not shown) formed on the base substrate461to transmit various signals. The wires include a plurality of output pads462electrically connected to the pads IP. The output pads462are in a one-to-one relationship with the pads IP.

An anisotropic conductive film ACF480is disposed between the first substrate100and the flexible printed circuit board460. The anisotropic conductive film480includes an adhesive material that allows the flexible printed circuit board460to adhere to the first substrate100. The anisotropic conductive film480includes conductive particles481, and the conductive particles481electrically connect the output pads and the transparent electrode160with each other.

When the first via hole VH1is formed between the pads IP as shown inFIG. 8, the anisotropic conductive film480may not be easily separated from the first substrate100since a step-difference between areas in which the pads are formed and areas between the pads IP is reduced due to the presence of the first via hole VH1. Thus, an area in which the second via hole VH2is formed has a thinner thickness than the area between the pads IP adjacent to the second via hole VH2because of the removal of the passivation layer140and the organic insulating layer150.

Thus, the anisotropic conductive film480on in the second via hole VH2may be separated from the first substrate110. Due to formation of the first via hole VH1, the step-difference between the areas in which the pads are formed and the areas between the pads IP may be reduced, thereby preventing the separation of the anisotropic conductive film480from the first substrate110. As a result, the liquid crystal display apparatus600may enhance the coupling force between the flexible printed circuit board460and the first substrate100and improve production yield thereof.

In the second peripheral area PA2, the passivation layer140and the organic insulating layer150are completely removed since the pads IP are not formed therein. Thus, the anisotropic conductive film480is directly adhered to the gate insulating layer122on the transparent substrate100. As a result, the liquid crystal display apparatus600may also enhance the coupling force between the flexible printed circuit board460and the first substrate100and improve production yield thereof.

FIGS. 9A to 9Eare views illustrating a method of manufacturing the liquid crystal display apparatus illustrated inFIG. 8. Referring toFIG. 9A, the gate insulating layer122and a conductive metal material are sequentially deposited on the transparent substrate110. The conductive metal material is patterned by a photolithography process to form the output lines OL (refer toFIG. 4) and the pads IP at the first end of the output lines OL corresponding to the first peripheral area PA. Although not shown in figures, the output lines OL are substantially simultaneously formed with the data lines DL (refer toFIG. 1), the source electrode125and the drain electrode126.

Referring toFIGS. 9B and 9C, the passivation layer140and the organic insulating layer150are sequentially deposited on the gate insulating layer122on which the pads IP are formed. The organic insulating layer150is exposed using a slit mask700having a slit portion SA through which ultraviolet lights are partially transmitted and a transmission portion TA through which the ultraviolet lights are substantially completely transmitted. The slit portion SA corresponds to areas in which the first and second via holes VH_1and VH_2are formed, and the transmission portion corresponds to the second peripheral area PA2.

The passivation layer140and the organic insulating layer150are patterned by a photolithography process using the slit mask700such that the passivation layer140corresponding to the second peripheral area PA are completely removed and the first and second via holes VH_1and VH_2are formed in the first peripheral area PA1.

Referring toFIG. 9D, a transparent conductive metal material is coated on the transparent substrate110on which the passivation layer140and the organic insulating layer150. When the conductive metal material is patterned, the transparent electrode160covering the second via hole VH2is formed. Although not shown in figures, the conductive metal material placed on an area corresponding to the display area DA is also patterned to form the pixel electrode130.

Referring toFIG. 9E, the anisotropic conductive film480is attached on the first and second peripheral areas PA1and PA2of the first substrate100on which the transparent electrode160is formed, and the flexible printed circuit board460is attached to the anisotropic conductive film480.

FIG. 10is a cross-sectional view showing the first substrate coupled to a driving chip illustrated inFIG. 1. Referring toFIG. 10, the output lines OL is formed on the gate insulating layer122formed on the transparent substrate110. The pads OP formed at the second end of the output lines OL are adjacent to the driving chip420.

The passivation layer140and the organic insulating layer150are formed on the gate insulating layer122on which the output lines OL are formed. The passivation layer140and the organic insulating layer150between two pads OP adjacent to each other are partially removed to form the first via holes VH1. The passivation layer140and the organic insulating layer150on the pads OP are partially removed such that the pads OP are partially exposed through the second via holes VH2.

The transparent electrode160on the organic insulating layer150is electrically connected to the pads OP through the second via hole VH2.

The driving chip420is attached to an area in which the pads OP are formed. The driving chip420includes output pads421electrically connected to the pads OP.

The anisotropic conductive film480is disposed between the first substrate100and the driving chip420. The anisotropic conductive film480allows the driving chip420to adhere to the first substrate100and electrically connects the output lines421and the transparent electrode160on the pads OP.

Due to formation of the first via hole VH1, the step-difference between the areas in which the pads OP are formed and the areas between the pads OP may be reduced, thereby preventing the separation of the anisotropic conductive film480from the first substrate100. As a result, the liquid crystal display apparatus600may enhance the coupling force between the driving circuit420and the first substrate100and improve production yield thereof.

According to the above, the organic insulating layer is partially removed to form the via holes between the pads of the output lines on the first substrate. The step-difference between the areas in which the pads are formed and the areas in which the pads are not formed may be reduced due to the presence of the via hole so that the anisotropic conductive film may be stably adhered to the first substrate. Thus, the liquid crystal display apparatus may enhance the coupling force between the flexible printed circuit board and the first substrate and between the driving chip and the first substrate.

Accordingly, due to enhancement of the coupling force between the flexible printed circuit board and the first substrate and between the driving chip and the first substrate, the first substrate may stably receive various signals needed to display the image. Therefore, the liquid crystal display apparatus may prevent the image from being displayed abnormally and improve production yield thereof.

Although the processes and apparatus of the present invention have been described in detail with reference to the accompanying drawings for the purpose of illustration, it is to be understood that the inventive processes and apparatus are not to be construed as limited thereby. It will be readily apparent to those of reasonable skill in the art that various modifications to the foregoing exemplary embodiments may be made without departing from the spirit and scope of the invention as defined by the appended claims.