SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

An embodiment comprises: a memory cell array that includes a plurality of memory cells arranged in a stacking direction on a semiconductor substrate, and a plurality of first conductive layers arranged in the stacking direction on the semiconductor substrate and connected to the memory cells; a cover layer that covers at least some of side surfaces of each of the plurality of first conductive layers; and a second conductive layer commonly connected to ends of some of the plurality of first conductive layers. Moreover, the commonly connected ends of some of the plurality of first conductive layers and the second conductive layer are connected without being interposed by the cover layer.

FIELD

Embodiments described herein relate to a semiconductor memory device and a method of manufacturing the same.

BACKGROUND

A flash memory that stores data by accumulating a charge in a charge accumulation layer or floating gate, is known. Such a flash memory is connected by a variety of systems such as NAND type or NOR type, and configures a semiconductor memory device. In recent years, increasing of capacity and raising of integration level of such a semiconductor memory device have been proceeding. Moreover, a semiconductor memory device in which memory cells are disposed three-dimensionally (three-dimensional type semiconductor memory device) has been proposed to raise the integration level of the memory.

DETAILED DESCRIPTION

A semiconductor memory device according to an embodiment comprises: a memory cell array that includes a plurality of memory cells arranged in a stacking direction on a semiconductor substrate, and a plurality of first conductive layers arranged in the stacking direction on the semiconductor substrate and connected to the memory cells; a cover layer that covers at least some of side surfaces of each of the plurality of first conductive layers; and a second conductive layer commonly connected to ends of some of the plurality of first conductive layers. Moreover, the commonly connected ends of some of the plurality of first conductive layers and the second conductive layer are connected without being interposed by the cover layer.

Next, semiconductor memory devices according to embodiments will be described in detail with reference to the drawings. Note that these embodiments are merely examples. For example, the semiconductor memory devices described below have a structure in which a memory string extends linearly in a perpendicular direction to a substrate, but a similar structure may be applied also to a U-shaped structure in which the memory string is doubled back on an opposite side midway. Moreover, each of the drawings of the semiconductor memory devices employed in the embodiments below is schematic, and thicknesses, widths, ratios, and so on, of layers are not necessarily identical to those of the actual semiconductor memory devices.

In addition, the embodiments described below relate to semiconductor memory devices having a structure in which a plurality of MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) type memory cells (transistors) are provided in a height direction, each of the MONOS type memory cells including: a semiconductor film acting as a channel provided in a column shape perpendicularly to a substrate; and a gate electrode film provided on a side surface of the semiconductor film via a charge accumulation layer. However, a similar structure may be applied also to a memory cell of another form, for example, a SONOS (Semiconductor-Oxide-Nitride-Oxide-Semiconductor) type memory cell or MANOS (Metal-Aluminum Oxide-Nitride-Oxide-Semiconductor) type memory cell, one employing hafnium oxide (HfOx) or tantalum oxide (TaOx) as an insulating layer, or a floating gate type memory cell.

First Embodiment

FIG. 1is a plan view showing a schematic configuration of a semiconductor memory device according to a first embodiment. The semiconductor memory device according to the first embodiment comprises a memory cell array1provided on a substrate101used as a memory chip. A periphery of the memory cell array may be provided with a peripheral circuit2and a dummy stepped portion22that surrounds the peripheral circuit2.

The memory cell array1comprises: a plurality of memory cells arranged three-dimensionally; and a stepped portion where wiring lines led out from the memory cells are formed in a stepped shape.

The peripheral circuit2is connected to the memory cell array1via a plurality of bit lines and a plurality of word lines. The peripheral circuit2is formed of a CMOS circuit provided on the substrate101, and functions as a decoder, a sense amplifier, a state machine, a voltage generating circuit, and so on.

Note that in the description below, a region on the substrate101provided with the memory cell array1will be called a memory cell array region R1, a region on the substrate101provided with the stepped wiring lines led out from the memory cells will be called a contact region CR, a region on the substrate101provided with the peripheral circuit2will be called a peripheral circuit region R2(transistor region), and a region on the substrate101provided with the dummy stepped portion22will be called a dummy region R3.

Next, a circuit configuration of part of the memory cell array1according to the present embodiment will be described with reference toFIG. 2.FIG. 2is an equivalent circuit diagram showing a configuration of part of the memory cell array1according to the present embodiment.

As shown inFIG. 2, the memory cell array1according to the present embodiment comprises a plurality of memory blocks MB. Moreover, a plurality of bit lines BL and a source line SL are commonly connected to these plurality of memory blocks MB. Each of the memory blocks MB is connected to the sense amplifier via the bit lines BL, and is connected to an unillustrated source line driver via the source line SL.

The memory block MB comprises a plurality of memory units MU that have their one ends connected to the bit lines BL and have their other ends connected to the source line SL via a source contact LI.

As shown inFIG. 2, the memory unit MU comprises a plurality of memory cells MC connected in series. As will be mentioned later, the memory cell MC comprises a semiconductor layer, a charge accumulation layer, and a control gate, and accumulates a charge in the charge accumulation layer based on a voltage applied to the control gate, thereby changing a threshold value of the memory cell MC. Note that hereafter, the plurality of memory cells MC connected in series will be called a “memory string MS”.

As shown inFIG. 2, the word lines WL are commonly connected to the control gates of pluralities of the memory cells MC configuring different memory strings MS, respectively. These pluralities of memory cells MC are connected to a row decoder via the word lines WL.

As shown inFIG. 2, the memory unit MU comprises a drain side select gate transistor STD connected between the memory string MS and the bit line BL. Drain side select gate line SGD is connected to a control gate of the drain side select gate transistor STD. The drain side select gate line SGD is connected to the row decoder, and selectively connects the memory string MS and the bit line BL based on an inputted signal.

As shown inFIG. 2, the memory unit MU comprises a source side select gate transistor STS connected between the memory string MS and the source contact LI. Source side select gate line SGS is connected to a control gate of the source side select gate transistor STS. The source side select gate line SGS is connected to the row decoder, and selectively connects the memory string MS and the source line SL based on an inputted signal.

Next, a schematic configuration of the memory cell array1according to the present embodiment will be described with reference toFIGS. 3 and 4.FIG. 3is a schematic perspective view showing a configuration of part of a memory finger MF (memory cell group).FIG. 4is a schematic plan view showing a configuration of a stepped portion12of the memory cell array1. Note that inFIGS. 3 and 4, part of the configuration is omitted.

As shown inFIG. 3, the memory finger MF according to the present embodiment comprises: the substrate101; and a plurality of conductive layers102stacked in a Z direction on the substrate101. In addition, the memory finger MF includes a plurality of memory columnar bodies105extending in the Z direction. As shown inFIG. 3, an intersection of the conductive layer102and the memory columnar body105functions as the source side select gate transistor STS, the memory cell MC, or the drain side select gate transistor STD. The conductive layer102is formed of a conductive layer of tungsten (W) or polysilicon, for example, and functions as the word line WL, the source side select gate line SGS, and the drain side select gate line SGD.

As shown inFIG. 3, the plurality of conductive layers102are formed in a stepped shape and configure the stepped portion12, at their ends in an X direction in the contact region CR.

The stepped portion12comprises a support111(HR) extending in the Z direction to penetrate the stepped portion12.

Moreover, disposed in the stepped portion12is a contact109for electrically connecting an upper wiring line10and each of layers configuring the stepped portion12. As shown inFIG. 3, the memory finger MF comprises a conductive layer108that faces side surfaces in a Y direction of the plurality of conductive layers102, and extends in the X direction. A lower surface of the conductive layer108contacts the substrate101. The conductive layer108is formed of a conductive layer of tungsten (W), for example, and functions as the source contact LI.

In addition, as shown inFIG. 3, disposed upwardly of the memory finger MF are a conductive layer106and a conductive layer107. The conductive layer106functions as the bit line BL, and the conductive layer107functions as the source line SL.

FIG. 4is a schematic plan view showing the configuration of the stepped portion12of the memory cell array1. In FIG.3described above, a plurality of the conductive layers102of the memory cell array1configure the stepped portion12at their ends in the X direction. However, as shown inFIG. 4, the conductive layers102of the memory cell array1are formed in a stepped shape and configure the stepped portion12also at their ends in the Y direction. That is, the semiconductor memory device according to the present embodiment includes the contact region CR comprising the stepped portion12in a periphery in each of the X and Y directions, of the memory cell array region R1.

FIG. 4shows a step boundary SBL where a level difference of the stepped portion12of the contact region CR changes. In other words, inFIG. 4, a region surrounded by the SBL has an identical height, and that height decreases with increasing distance from the memory cell array region R1(with increasing distance from a substrate center).

Note that the conductive layers102configuring the word lines WL may have a stepped structure expanding one-dimensionally only in the X direction as shown inFIG. 5A, or may have a two-dimensional stepped structure expanding in both of the X direction and the Y direction as shown inFIG. 5B.

Moreover, as will be mentioned later, the dummy region R3is also provided with the stepped portion22having a stepped structure. This stepped portion22may also adopt the stepped structures of the kinds shown inFIGS. 5A and 5B.

Next, a schematic configuration of the memory cell MC according to the present embodiment will be described with reference toFIG. 6.FIG. 6is a schematic perspective view showing the configuration of the memory cell MC. Note thatFIG. 6shows the configuration of the memory cell MC, but the source side select gate transistor STS and the drain side select gate transistor STD may also be configured similarly to the memory cell MC. Moreover, inFIG. 6, part of the configuration is omitted.

As shown inFIG. 6, the memory cell MC is provided at an intersection of the conductive layer102and the memory columnar body105. The memory columnar body105comprises: a core insulating layer121; and a semiconductor layer122that covers a sidewall of the core insulating layer121. Furthermore, a memory film126is provided between the semiconductor layer122and the conductive layer102. The memory film126includes a tunnel insulating layer123, a charge accumulation layer124, and a block insulating layer125.

The core insulating layer121is formed of an insulating layer of silicon oxide, for example. The semiconductor layer122is formed of a semiconductor layer of polysilicon, for example. Moreover, the semiconductor layer122functions as a channel of the memory cell MC, the source side select gate transistor STS, and the drain side select gate transistor STD. The tunnel insulating layer123is formed of an insulating layer of silicon oxide, for example. The charge accumulation layer124is formed of an insulating layer capable of accumulating a charge, of silicon nitride, for example. The block insulating layer125is formed of an insulating layer of silicon oxide, for example.

Next, a configuration of the semiconductor memory device according to the present embodiment will be described in more detail with reference toFIGS. 7, 8A, and 8B.FIG. 7is a plan view showing a configuration of part of the memory cell array1; andFIG. 8Ais a schematic cross-sectional view showing the configuration of the semiconductor memory device according to the present embodiment, and shows a cross-section taken along the line AA ofFIG. 1. Note that inFIG. 8A, illustration of the peripheral circuit2is omitted.FIG. 8Bis an enlarged cross-sectional view of the portion B ofFIG. 8A.

As shown inFIG. 7, the memory columnar bodies105are arranged so as to be lined up in an oblique direction to the X direction (word line direction) and the Y direction (bit line direction), whereby an array density of the memory columnar bodies105is increased, and an array density of the memory cells MC is raised. However, this is merely an example, and it is also possible to configure such that the memory columnar bodies105are aligned along the X direction and the Y direction. In addition, the source contact LI is formed in a striped shape having the X direction as its longitudinal direction.

The source contact LI is implanted, via an inter-layer insulating film127, in a trench Tb that divides the memory cell array1in block units. A lower end of the source contact LI contacts a diffusion layer formed in a surface of the substrate101, and an upper end of the source contact LI is connected to the source line SL via an upper layer wiring line.

FIG. 8Ais a schematic cross-sectional view in the Z-X directions showing a configuration of the above-mentioned stepped portion12of the memory cell array1. Note that inFIG. 8A, part of the configuration is omitted. Moreover, the configuration shown inFIG. 8Ais merely an example, and a detailed configuration, and so on, may be appropriately changed.

As shown inFIG. 8A, in the stepped portion12of the contact region CR, a plurality of conductive layers102aand102bare stacked on the substrate101via an insulating layer103. Of these conductive layers102aand102b, the plurality of layers (in the present embodiment, three layers) of conductive layers102afrom a lowermost layer function as the source side select gate line SGS connected to the source side select gate transistor STS. The conductive layer102bmore upward than the conductive layer102afunctions as the word line WL. The word line WL may include a dummy word line. Moreover, although not illustrated inFIG. 8A, a plurality of layers of conductive layers from an uppermost layer, of the stacked conductive layers102function as the drain side select gate line SGD connected to the drain side select gate transistor STD.

The insulating layer103is formed of silicon oxide, for example. The conductive layers102aand102bare formed of a metal such as tungsten or from polysilicon, as mentioned above. Moreover, although illustration thereof is omitted inFIG. 8A, a cover film CF is provided in a periphery of the conductive layers102aand102b, so as to cover at least some of side surfaces of the conductive layers102aand102b. The cover film CF includes a block insulating layer, a high permittivity film, and a barrier metal film.

As shown inFIG. 8A, the conductive layer102bis formed in a stepped shape in the stepped portion12. That is, an end in the X direction of the conductive layer102brecedes in a direction of increasing distance from the peripheral circuit region R2and the dummy region R3with increasing distance in the Z direction from the substrate101. In other words, the conductive layer102bhas a height that increases with increasing distance from the peripheral circuit region R2and the dummy region R3.

The stepped portion12is provided with the support111for maintaining a posture of the stepped structure during a later-mentioned insulating layer replacing step. A block layer114is provided on a surface of the stepped portion12. Moreover, an inter-layer insulating layer115is disposed so as to cover the stepped portion12.

The block layer114is formed of silicon nitride, for example. The inter-layer insulating layer115is formed of silicon oxide, for example.

In the present embodiment, only the contact region CR including the stepped portion12, of the memory cell array region R1, is illustrated, but provided on the inside of the contact region CR (in a direction of increasing distance from the end of the stepped portion12) is the memory cell array region R1where the memory columnar body105, and so on, are disposed.

Moreover, as shown inFIG. 8A, in the present embodiment, ends of some of the conductive layers102(in the present embodiment, the three stacked layers of conductive layers102afrom the lowermost layer) are provided with a conductive layer104commonly connected to the ends of these three layers of conductive layers102a.

FIG. 8Bshows an enlarged cross-sectional view of a portion including these three layers of conductive layers102aand the conductive layer104.

As shown inFIG. 8B, the conductive layers102aand102bare provided with the cover film CF such that at least some of their side surfaces are covered. The conductive layer104is disposed at ends of the conductive layers102aso as to extend in the Z direction to straddle the three layers of conductive layers102a. As a result, the three layers of conductive layers102aare electrically connected via the conductive layer104. Moreover, the three layers of conductive layers102afrom the lowermost layer and the conductive layer104are connected without being interposed by the cover film CF, at their boundary C. Note that hereafter, illustration of the cover film CF will sometimes be omitted.

The conductive layer104connected to the ends of the conductive layers102ahas a contact109aconnected thereto. In other words, the conductive layers102afunctioning as the source side select gate line SGS are electrically connected to an upper wiring line via the conductive layer104.

A contact109bis connected to close to an end of each of the conductive layers102bin higher layers than the three layers of conductive layers102afrom the lowermost layer. The conductive layer102bfunctioning as the word line WL and an upper wiring line, and so on, are electrically connected by the contact109b. The contacts109aand109bhave their periphery covered by a barrier metal BM.

Thus, in the present embodiment, there is only one contact109aconnected to the source side select gate line SGS formed of the plurality of conductive layers102a, and this is less than the number of conductive layers102aconfiguring the source side select gate line SGS. This makes it unnecessary for a contact to be provided to each of the plurality of conductive layers102a, hence enables area of the contact region CR to be reduced. That is, ends in the X direction (direction of increasing distance from the memory cell array region R1and increasing closeness to the peripheral circuit region R2and dummy region R3) of the plurality of conductive layers102aconfiguring the source side select gate line SGS are aligned and commonly connected by the conductive layer104at those ends. Moreover, the contact109ais connected to this conductive layer104. Therefore, it becomes unnecessary to configure the plurality of conductive layers102aas a stepped structure in order to connect a contact to each of the plurality of conductive layers102a, and area of the contact region CR can be reduced proportionately.

Note that in the present embodiment, the boundary where the conductive layer102aand the conductive layer104are connected substantially matches an end in the X direction of the conductive layer102bin a fourth layer from the lowermost layer, but a position of the above-described boundary is not limited to this.

In addition, as shown inFIG. 8A, the dummy stepped portion22is provided also in the dummy region R3. The dummy stepped portion22has a configuration of a plurality of insulating layers202and insulating layers203stacked alternately on the substrate101. Moreover, a portion facing the conductive layers102a, of the dummy stepped portion22, that is, the six layers of insulating layers202and insulating layers203counting from a substrate101side, do not have a stepped structure, and have their lengths in the X direction aligned. Moreover, a portion facing the conductive layers102bof the dummy stepped portion22, that is, the insulating layers202and insulating layers203in seventh and higher layers counting from the substrate101side, have a stepped structure.

Next, a method of manufacturing the semiconductor memory device according to the present embodiment will be described with reference toFIGS. 9 to 25.FIGS. 9 to 25are schematic cross-sectional views for explaining the same method of manufacturing.

As shown inFIG. 9, a plurality of the insulating layers103and sacrifice layers112aare stacked alternately on the substrate101. The insulating layer103is formed of silicon oxide, for example. The sacrifice layer112ais formed of silicon nitride, for example. This sacrifice layer112awill be replaced later by a conductive film to become the conductive layer102a.

As shown inFIG. 10, a resist300is disposed. This resist300is disposed opening a region where, as will be described later, a sacrifice layer112cwhich will later become the conductive layer104is disposed.

As shown inFIG. 11, the insulating layers103and sacrifice layers112adisposed in an opening portion of the resist300are removed, using the resist300as a mask. Thus, a gap113penetrating some of the insulating layers103and at least two layers of the sacrifice layers112a, is formed.

As shown inFIG. 12, a sacrifice layer112bis disposed so as to fill the gap113. This sacrifice layer112bmay be formed of the same material as the sacrifice layer112a. Specifically, the sacrifice layer112bmay be formed of silicon nitride, for example.

As shown inFIG. 13, part of the sacrifice layer112bis removed by etching employing RIE or by CMP, and so on, and a sacrifice layer112cis obtained. At this time, conditions of the etching or CMP, and so on, are adjusted such that an upper surface of the sacrifice layer112cand an uppermost surface of the stacked insulating layers103and sacrifice layers112asubstantially match.

As shown inFIG. 14, a plurality of the insulating layers103and sacrifice layers112dare stacked alternately on upper surfaces of the sacrifice layer112cand the uppermost layer sacrifice layer112aformed in the step described byFIG. 13. The sacrifice layer112dis formed of an identical material to the sacrifice layers112aand112c. The sacrifice layer112dwill be replaced by a conductive film in a later step to become the conductive layer102b.

As shown inFIG. 15, the stacked insulating layers103, sacrifice layers112a, and sacrifice layers112dare divided into a portion12′ which will later become the stepped portion12and a portion22′ which will later become the dummy stepped portion22, by etching using a resist301as a mask. In addition, part of the sacrifice layer112cis removed.

As shown inFIG. 16, a resist302is disposed. A position of this resist302will be a reference of a position of a leading edge of the stepped structure when the stepped portion12is formed, as will be mentioned later. That is, a leading edge of this resist302will be a position of a leading edge of a stepped structure portion of the stepped portion12that is formed.

As shown inFIG. 17, one layer each of the insulating layers103and sacrifice layers112dare etched using the resist302as a mask, whereby a first stage level difference is formed.

As shown inFIG. 18, the resist302is slimmed to the extent of a width in the X direction of the level difference of the stepped portion12.

As shown inFIG. 19, one layer each of the insulating layers103and sacrifice layers112dare again etched, whereby a second stage level difference is formed.

Slimming of the resist302and etching of the insulating layer103and sacrifice layer112dare repeated a desired number of times, and the configuration shown inFIG. 20is obtained. Thus, the stepped portion12is formed in the contact region CR. Moreover, in the dummy region R3, the dummy stepped portion22having a similar configuration to the stepped portion12, is formed.

In the present embodiment, the etching for forming the above-described stepped structure is performed to the fourth layer insulating layer103counting from the substrate101and the lowermost layer sacrifice layer112d. Therefore, the sacrifice layers112dwhich will later become the conductive layers102bare all etched, whereby the stepped structure is formed. The sacrifice layers112awhich will later become the conductive layers102aare not etched and do not undergo formation of the stepped structure.

As shown inFIG. 21, part of the sacrifice layer112cand part of the lowermost layer insulating layer103are removed by etching. Note that this step may be omitted.

As shown inFIG. 22, the block layer114is formed on a surface of the formed stepped portion12. The inter-layer insulating layer115is deposited on an entire surface of the unillustrated memory cell array region R1, the contact region CR, the peripheral circuit region R2, and the dummy region R3, so as to cover the block layer114.

This block layer114functions as an etching stopper when forming a contact of each stage of the stepped structure. However, in the present embodiment, as shown inFIG. 22, the sacrifice layer112cis disposed extending in the Z direction so as to commonly contact the ends of each of the plurality of sacrifice layers112a. In this case, in a step of removing the sacrifice layer112aand the sacrifice layer112cto be replaced by the conductive film, a gap of a portion where the sacrifice layer112cwas disposed becomes large. Thereupon, a load applied to the block layer114of that portion, that is, a portion disposed on an upper surface and side surface of the sacrifice layer112cbecomes larger than a load applied to the block layer114of another portion, and there is a risk that the stepped structure ends up collapsing. In such a case, it is also possible for all of the block layer114or the portion contacting the upper surface and side surface of the sacrifice layer112c, of the block layer114, to be thickened.

As shown inFIG. 23, the sacrifice layers112a,112c, and112dare removed using wet etching, and gaps116a,116b, and116care formed. Due to this step, the gaps116aformed by the sacrifice layers112abeing removed are communicated via the gap116bformed by the sacrifice layer112cbeing removed. When the sacrifice layers112a,112c, and112dare formed of silicon nitride, a phosphoric acid system solution may be used as a solution of the wet etching.

As shown inFIG. 24which is an enlarged cross-sectional view of part ofFIG. 23, the cover film CF is formed, by CVD, for example, inside the gaps116a,116b, and116ccaused by the wet etching. As mentioned above, this cover film CF is formed of a stacked structure of a block film, a high permittivity film, and a barrier metal, for example.

As shown inFIG. 25, the conductive film is deposited, by a CVD method, for example, inside the gaps116a,116b, and116c, and the conductive layers102a,102b, and104are formed. Due to this step, the ends of the plurality of conductive layers102aare electrically connected via the conductive layer104formed at those ends.

Moreover, the contact109aconnected to the conductive layer104and the plurality of contacts109bconnected to each layer of the conductive layers102b, are formed, and the configuration shown inFIG. 8Ais obtained.

Second Embodiment

A semiconductor memory device according to a second embodiment will be described usingFIGS. 26 to 36.

First, a configuration of the semiconductor memory device according to the second embodiment will be described usingFIG. 26. Note that the same configurations as in the first embodiment are assigned with the same reference symbols as those assigned in the first embodiment, and descriptions thereof will be omitted.

As shown inFIG. 26, the semiconductor memory device according to the second embodiment is similar to that of the first embodiment in having the conductive layer104provided at the ends of some of the stacked conductive layers, that is, the conductive layers102a. The second embodiment differs from the first embodiment in having a conductive layer102cdisposed between the conductive layers102aand conductive layer104and the semiconductor substrate101.

The conductive layer102cis disposed downwardly of the conductive layer102afunctioning as the source side select gate line SGS and has its end in the X direction protruding more to a peripheral circuit region R2and dummy region R3side than does the end in the X direction of the conductive layer104. A contact109cis connected to the end of the conductive layer102c. Moreover, the conductive layer102cfunctions as a bottom source side select gate line SGSB.

Such a configuration also results in there being a single contact109aas a contact for electrically connecting the plurality of conductive layers102aand an upper wiring line. Therefore, area of the contact region CR can be reduced similarly to in the first embodiment.

A method of manufacturing the semiconductor memory device according to the second embodiment will be described usingFIGS. 27 to 36.

As shown inFIG. 27, the insulating layer103and a sacrifice layer112eare stacked on the substrate101, and a plurality of the insulating layers103and sacrifice layers112aare stacked alternately on an upper surface of the sacrifice layer112e.

As shown inFIG. 28, a resist303is disposed. This step is similar to the step ofFIG. 10in the first embodiment.

As shown inFIG. 29, parts of the insulating layers103and sacrifice layers112aare removed by etching using the resist303as a mask. At this time, the sacrifice layer112eis not removed. This step results in a gap117being formed.

As shown inFIG. 30, the resist303is removed, and a sacrifice layer112fis deposited so as to fill the gap117. This step is similar to the step ofFIG. 12in the first embodiment.

As shown inFIG. 31, the sacrifice layer112fbesides a portion implanted in the gap117is removed by etching or CMP. This step results in a sacrifice layer112gbeing formed. This step is similar to the step ofFIG. 13in the first embodiment.

As shown inFIG. 32, a plurality of the insulating layers103and sacrifice layers112dare alternately stacked. This step is similar to the step ofFIG. 14in the first embodiment.

As shown inFIG. 33, the insulating layers103and the sacrifice layers112a,112d, and112eare divided by etching using a resist304as a mask. In addition, part of the sacrifice layer112gis removed.

As shown inFIG. 34, the resist304is removed and a resist305is disposed.

As shown inFIG. 35, parts of the insulating layers103and the sacrifice layers112aand112dare removed by etching using the resist305as a mask. In addition, part of the sacrifice layer112gis removed. During this etching, conditions of the etching are adjusted such that the sacrifice layer112eis not removed.

As shown inFIG. 36, etching and slimming of a resist306are repeated a desired number of times to form the stepped structure, similarly to in the first embodiment. During formation of this stepped structure, the sacrifice layers112dwhich will later become the conductive layers102bare all etched, whereby the stepped structure is formed, similarly to in the first embodiment. The sacrifice layers112awhich will later become the conductive layers102aare not etched and do not undergo formation of the stepped structure. Moreover, an end in the X direction of the sacrifice layer112eprotrudes more to the peripheral circuit region R2and dummy region R3side than does an end in the X direction of the sacrifice layer112c.

Hereafter, similarly to in the steps ofFIGS. 22 to 25in the first embodiment, replacement of each of the sacrifice layers by conductive layers or formation of contacts, and so on, are performed, and the configuration shown inFIG. 26is obtained.

As described above, in the present embodiment, by twice performing the etching by which the stacked insulating layers and sacrifice layers are divided, it is made possible for the conductive layer102cto be formed in a layer below the conductive layers102afunctioning as the select gate line SGS.

Modified Examples

Semiconductor memory devices according to several modified examples will be described usingFIGS. 37 to 39.

First Modified Example

In the above-described embodiments, the conductive layer104commonly connected to the plurality of conductive layers102awas provided only at ends of the conductive layers102afunctioning as the source side select gate line SGS.

However, as shown inFIG. 37, a conductive layer118commonly connected to side surfaces of a plurality of conductive layers102dfunctioning as the drain side select gate line SGD, may be provided.

In order to form the conductive layer118, as shown inFIG. 38, for example, the steps described byFIGS. 10 to 13of the first embodiment are repeated a plurality of times, and a sacrifice layer112his formed. In addition, similar steps to those for the sacrifice layer112care performed on this sacrifice layer112h, and the configuration shown inFIG. 37is obtained.

Second Modified Example

Moreover, in the above-described embodiments, the conductive layer104did not undergo etching for stepped structure formation, hence did not include the stepped structure.

However, as shown inFIG. 39, it is also possible for the conductive layer104to be formed in a stepped structure shape. In order to form the conductive layer104in a stepped shape, it is only required that, for example, in the steps of stepped structure formation described usingFIGS. 16 to 19in the first embodiment, etching is not completed at the lowermost layer sacrifice layer112d, and etching is performed to the sacrifice layer112cto form in the stepped shape.

Similar advantages to those of the embodiments are obtained also by either of the above-described modified examples. Moreover, the above-described modified examples are examples, and a shape or number, and arrangement position of the conductive layer commonly connecting the plurality of conductive layers, may be appropriately changed. For example, described above was a conductive layer commonly connected to a plurality of conductive layers functioning as a select gate line, but conductive layers functioning as a dummy word line may be commonly connected. Moreover, it is also possible for the several modified examples, or for each of the embodiments and the modified examples, to be combined.