INTEGRATED CIRCUIT PACKAGE FOR SCAN TESTING SEMICONDUCTOR CHIP, OPERATING METHOD OF INTEGRATED CIRCUIT PACKAGE, AND INTEGRATED CIRCUIT

An integrated circuit package for scan testing a semiconductor chip includes at least one first input pad configured to receive a first input signal, at least one chip connected to the first input pad, and at least one first output pad configured to receive a first output signal generated by the at least one chip, wherein each of the at least one chip includes at least one second input pad configured to receive a second input signal, a plurality of scan chains, a first test circuit and a second test circuit, which share the plurality of scan chains, and at least one second output pad configured to receive a second output signal from the first test circuit.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0102950, filed on Aug. 17, 2022, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

BACKGROUND

The inventive concepts relate to an integrated circuit package for scan testing semiconductor chips, an operating method of the integrated circuit package, and an integrated circuit, and for example, to an integrated circuit package that performs semiconductor package testing and electric die sorting (EDS) testing on a plurality of test circuits sharing a scan chain.

Methods using scan test for efficient testing of integrated circuits (ICs) are widely used. A scan test is a method of testing a typical flip-flop by replacing the typical flip-flop with a scan flip-flop and configuring the scan flip-flop into one or more shift scan chains.

A test pad that receives a signal for determining whether a semiconductor chip is defective may be ball-out to a single-chip. The ball-out means that the pad is exposed to the outside of a circuit to receive signals.

However, it may be physically limited to expose all test pads of chips to the outside in a multi-chip package. Accordingly, when a defective chip is included in a multi-chip package, there may be a problem that a test device cannot be connected to the pad exposed to the outside, so it may be necessary to separate each semiconductor chip and inspect the semiconductor chip for defects.

SUMMARY

The inventive concepts provide an integrated circuit package that can test semiconductor chips for defects even in a multi-chip package state using two test circuits sharing a scan chain and perform both an electric die sorting (EDS) test and a package test. According to an aspect of the inventive concepts, there is provided an integrated circuit package for scan testing a semiconductor chip including at least one first input pad configured to receive a first input signal, at least one chip connected to the first input pad, and at least one first output pad configured to receive a first output signal generated by the at least one chip, wherein each of the at least one chip includes at least one second input pad configured to receive a second input signal, a plurality of scan chains, a first test circuit and a second test circuit, which share the plurality of scan chains, and at least one second output pad configured to receive a second output signal from the first test circuit, wherein the integrated circuit package includes a signal selection circuit configured to receive a selection signal and determine whether the first input signal is used in the first test circuit or the second test circuit based on the selection signal.

According to another aspect of the inventive concepts, there is provided an operating method of an integrated circuit package for scan testing a semiconductor chip including receiving a first input signal through a first input pad, receiving a selection signal by a selection signal circuit, determining, based on the selection signal, whether the first input signal is provided to one of a first test circuit and a second test circuit of at least one chip exposed to the semiconductor chip, and outputting a first output signal generated by the first test circuit or a second output signal generated by the second test circuit, wherein the outputting the first output signal or the second output signal includes, when the first input signal is input to the first test circuit, outputting the first output signal to a first output pad exposed to the outside of the semiconductor chip.

According to another aspect of the inventive concepts, there is provided an integrated circuit for scan testing a semiconductor chip including a first test circuit configured to receive one of a first input signal and a second output signal, and generate a first output signal, a second test circuit configured to receive a first input signal and generate a second output signal, wherein the first test circuit includes a first decompressor configured to receive the first input signal or the second input signal, a first compressor configured to generate the first output signal, and a scan chain configured to connect the first decompressor with the first compressor, and the second test circuit includes a second decompressor configured to receive the first input signal, a second compressor configured to generate a second output signal, and the scan chain configured to connect the second decompressor with the second compressor, wherein the first test circuit and the second test circuit are configured to share the scan chain.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Terms used in the present disclosure will be briefly described and example embodiments will be described in detail.

FIG.1is a block diagram of an integrated circuit package100according to example embodiments.

Referring toFIG.1, the integrated circuit package100according to example embodiments may include a first test circuit110, a second test circuit120, and/or a scan chain block130shared by the first test circuit110and the second test circuit120. In addition, the integrated circuit package100may further include a signal selection circuit140and/or an output selection circuit150and may include a first input pad10that receives a first input signal IN_1, a first output pad11that outputs a first output signal OUT_1, a second input pad20that receives a second input signal IN_2, a second output pad21that receives a second output signal OUT_2, and a third input pad30that receives a selection signal Select_Sig.

The first input pad10may receive the first input signal IN_1. The first input pad10may be physically exposed to the outside of the integrated circuit package100. The first input signal IN_1may be a signal for package testing, the first input pad10may be connected to the signal selection circuit140, and the first input signal IN_1may be provided to the first test circuit110and the second test circuit120through the selection signal circuit140.

The second input pad20may receive the second input signal IN_2The second input pad20may be physically exposed to the outside of the first test circuit110in the inside of the integrated circuit package100. The second input signal IN_2may be a signal for electric die sorting (EDS) testing, and the second input pad20may be directly connected to the first test circuit110without passing through the signal selection circuit140. In addition, a plurality of second input pads20may be provided.

The third input pad30may receive the selection signal Select_Sig. The third input pad30may be physically exposed to the outside of the integrated circuit package100. The selection signal Select_Sig may have a logic value “0” or “1”, a state in which the logic value is “0” may be defined as a low state, and a state in which the logic value is “1” may be defined as a high state. The selection signal Select_Sig and the first input signal IN_1may be used to determine a test circuit to be used.

The first output pad11may receive the first output signal OUT_1generated by the first test circuit110. The first output pad11may be physically exposed to the outside of the integrated circuit package100. In addition, the second output pad21refers to an output pad that receives the second output signal OUT_2generated by the second test circuit120. The second output pad21may be physically exposed to the outside of the first test circuit110in the inside of the integrated circuit package100. According to example embodiments, a plurality of second output pads21may be provided.

Hereinafter, the output signal generated by the first test circuit110is defined as a first output signal OUT_1, and the output signal generated by the second test circuit120is defined as a second output signal OUT_2. According to example embodiments, the first output signal OUT_1may include one of a package test result and an EDS test result. In addition, the second output signal OUT_2may include a package test result.

The first test circuit110may be an integrated circuit for performing an EDS test and a package test on a semiconductor chip. For example, when the first input signal IN_1is received by the first test circuit110, the first test circuit110may operate in a package test mode. In addition, when the second input signal IN_2is received by the first test circuit110, the first test circuit110may operate in an EDS test mode. The operation of the first test circuit110will be described in detail with reference toFIGS.2and3.

The second test circuit120may be an integrated circuit for performing a package test on a semiconductor package. For example, the second test circuit120may receive the first input signal IN_1and process the first input signal IN_1to generate the second output signal OUT_2. According to example embodiments, the second output signal OUT_2may include information on a package test result. An operation of the second test circuit120will be described in detail with reference toFIG.4.

The scan chain block130may include a plurality of scan chains (not shown), and each of the scan chains (not shown) may include a plurality of flip-flops FFs. In addition, the first test circuit110and the second test circuit120may share the scan chain block130. The configuration of the scan chain block130will be described in detail with reference toFIG.5.

The signal selection circuit140receives a first input signal IN_1and a selection signal Select_Sig, and determines a test circuit in which the first input signal IN_1is utilized. For example, when the logic value of the selection signal Select_Sig is in a high state and the first input signal IN_1is received, the signal selection circuit140may input the first input signal IN_1to the first test circuit110. In addition, when the logic value of the selection signal Select_Sig is in a low state and the first input signal IN_1is received, the signal selection circuit140may input the first input signal IN_1to the second test circuit120. That is, when the first input signal IN_1is received, the signal selection circuit140may control whether the first input signal IN_1is transmitted to the first test circuit110based on the logic value of the selection signal Select_Sig received from the outside.

The output selection circuit150receives the output signal of the first test circuit110, the output signal of the second test circuit120, and the selection signal Select_Sig, and determines the signal to be output to the first output pad11. For example, when the logic value of the selection signal Select_Sig is “1”, the output selection circuit150determines that the package test has been performed in the first test circuit110and transmits the first output signal OUT_1to the first output pad11. In addition, when the second output signal OUT_2is input to the output selection circuit150and the logic value of the selection signal Select_Sig is “0”, the output selection circuit150determines that the package test has been performed in the second test circuit120and transmits the second output signal OUT_2to the second output pad21.

Hereinafter, various operations of an integrated circuit package according to example embodiments shown inFIGS.2to4will be described.

FIG.2is a circuit diagram when a first input signal IN_1is received in a first test circuit110according to example embodiments, andFIG.3is a circuit diagram when a second input signal IN_2is received in a first test circuit110according to example embodiments.

Referring toFIGS.2and3, the first test circuit110may perform a package test or an EDS test. When the first input signal IN_1is received, and the logic value of the selection signal Select_Sig is “1”, the first test circuit110performs a package test, and when the second input signal IN_2is input, and the logic value of the selection signal Select_Sig is “0”, the first test circuit110performs an EDS test.

The first test circuit110according to example embodiments includes a first decompressor111, a scan chain block130, and/or a first compressor112. In addition, the first test circuit110may be located or installed on the semiconductor chip200, and the semiconductor chip200may be located or installed on the semiconductor package300.

The first decompressor111decompresses the first input signal IN_1and transmits the decompressed first input signal IN_1ato the scan chain block130. When the decompressed first input signal IN_1ais received, a plurality of scan chains130_nin the scan chain block130store information of the decompressed first input signal IN_1aand transmit the signal-processed first input signal IN_1bto the first compressor112. When the signal-processed first input signal IN_1bis received, the first compressor112compresses the signals received from the scan chain block130and generates the first output signal OUT_1.

Referring toFIG.2, in order to perform a package test, the first test circuit110receives a first input signal IN_1. For example, when the signal selection circuit140receives the first input signal IN_1and the logic value of the selection signal is in a high state, the signal selection circuit140transmits the first input signal IN_1to the first decompressor111of the first test circuit110. When the first input signal IN_1is received, the first decompressor111decompresses the first input signal IN_1and transmits the decompressed first input signal IN_1ato the scan chain block130. When the decompressed first input signal IN_1ais received, the scan chain block130processes the decompressed first input signal IN_1aand transmits the processed result to the first compressor112. According to example embodiments, the processing of the first input signal IN_1may include a process of detecting whether the semiconductor chip package is defective. When the first input signal IN_1bfor which a predetermined or alternatively, desired processing has been completed is received, the first compressor112compresses the received signal and generates the first output signal OUT_1. The first output signal OUT_1is transmitted to the output selection circuit150. According to example embodiments, when the logic value of the selection signal Select_Sig is in the high state, the output selection circuit150transmits the first output signal OUT_1to the first output pad11. That is, when the first input signal IN_1is input to the first test circuit110, the first test circuit110performs a package test, wherein the first output signal OUT_1may be a signal including package test result information.

Referring toFIG.3, in order to perform an EDS test, the first test circuit110receives a second input signal IN_2. According to example embodiments, the second input signal IN_2may be received through a plurality of input pads20including TEST IN0, TEST IN1, . . . , and TEST IN n−1.

For example, when the second input signal IN_2is received, the first test circuit110may transmit the second input signal IN_2to the first decompressor111of the first test circuit110, regardless of the logic value of the selection signal. When the second input signal IN_2is received, the first decompressor111decompresses the second input signal IN_2and transmits the decompressed second input signal IN_2ato the scan chain block130. When the decompressed second input signal IN_2ais received, the scan chains of the scan chain block130process the decompressed second input signal IN_2aand transmit the processed result to the first compressor112. According to example embodiments, the processing of the second input signal IN_2may include a process of detecting whether the semiconductor chip is defective. When the second input signal IN_2bfor which a predetermined or alternatively, desired processing has been completed is received, the first compressor112compresses the received signal and transmits the second output signal OUT_2to the second output pads21. That is, when the second input signal IN_2is input to the first test circuit110, the first test circuit110performs an EDS test. According to example embodiments, the second output signal OUT_2may be a signal including EDS test result information.

FIG.4is a circuit diagram of a second test circuit120according to example embodiments.

Referring toFIG.4, the second test circuit120may include a second decompressor121, a scan chain block130, and/or a second compressor122, and/or a deserializer123including a plurality of input terminals TEST IN0, TEST IN1, . . . , and TEST IN n−1, in addition to a control signal terminal CTRL Signal, and an output pin block124including a plurality of output terminals TEST OUT0, TEST OUT1, . . . , and TEST OUT n−1.

The second test circuit120according to example embodiments receives the first input signal IN_1to perform a package test. For example, when the signal selection circuit140receives the first input signal IN_1and the logic value of the selection signal is in a low state, the signal selection circuit140transmits the first input signal IN_1to the deserializer123of the second test circuit120. The plurality of input terminals TEST IN0, TEST IN1, . . . , and TEST IN n−1 may be deserialized in the deserializer123and located or installed in the second test circuit120to thus disperse the first input signal IN_1, and transmit the dispersed first input signal IN_1cto the second decompressor121. According to example embodiments, the deserializer123may control the parallelization process of the first input signal IN_1and control the input speed of the first input signal IN_1by generating a control signal CTRL Signal through the control signal terminal CTRL Signal.

When the dispersed first input signal IN_1cis received, the second decompressor121decompresses the dispersed first input signal IN_1cand transmits the decompressed first input signal IN_1dto the scan chain block130. According to example embodiments, the scan chain block130may be shared with the first test circuit110described above. When the decompressed first input signal IN_1dis received, the scan chains of the scan chain block130process the decompressed first input signal IN_1dand transmit the processed result to the second compressor122. According to example embodiments, the processing of the first input signal IN_1may include a process of detecting whether the semiconductor chip package is defective. When the first input signal IN_1efor which a predetermined or alternatively, desired processing has been completed is received, the second compressor122compresses the received signal to generate a dispersed second output signal OUT_2′ and transmits the dispersed second output signal OUT_2′ to the serializer124. The serializer124includes a plurality of output terminals TEST OUT0, TEST OUT1, . . . , TEST OUT n−1, and is serialized and located or installed in the second test circuit120to merge the dispersed second output signal OUT_2′, and the merged second output signal OUT_2may be transmitted to the output selection circuit as shown atFIG.2.

When the second output signal OUT_2is received in the output selection circuit150and the logic value of the selection signal Select_Sig is in a low state, the second output signal OUT_2is transmitted to the first output pad11. That is, when the first input signal IN_1is input to the second test circuit120, the second test circuit120may perform a package test. According to example embodiments, the second output signal OUT_2may be a signal including package test result information. In addition, the second test circuit120includes the input pin block123including a plurality of input terminals and the output pin block124including a plurality of output terminals, thereby increasing the compression rate of the first input signal IN_1compared to the first test circuit110and performing a package test faster than the package test performed by the first test circuit110.

FIG.5illustrates a signal selection circuit140according to example embodiments.

Referring toFIG.5, the signal selection circuit140may include a NAND gate141and/or an AND gate142. In addition, each of the NAND gate141and the AND gate142may be connected to the first input pad10and the third input pad30. In addition, the NAND gate141may be connected to the second test circuit120, and the AND gate142may be connected to the first test circuit110. However, the logic circuit present in the signal selection circuit140is not limited thereto, and may include other configurations that derive the result values described below.

For example, when the first input signal IN_1is received and the logic value of the selection signal Select_Sig is in a high state, the signal selection circuit140may set the output of the AND gate142to high and transmit the first input signal IN_1to the first test circuit110. In addition, when the first input signal IN_1is received and the logic value of the selection signal Select_Sig is in a low state, the signal selection circuit140may set the output of the NAND gate141to high and transmit the first input signal IN_1to the second test circuit120.

FIG.6is a circuit diagram of an integrated circuit package100according to example embodiments.

Referring toFIG.6, the integrated circuit package100may include a first test circuit110and a second test circuit120, and the first test circuit110and the second test circuit120may share a scan chain block130. In addition, the integrated circuit package100may be a multi-chip package. For example, the integrated circuit package100may include a semiconductor chip200in which an EDS test is performed or a semiconductor package300in which a package test is performed. However, as described later inFIG.11, the number of example embodiments in which the integrated circuit package100may be exposed is not limited thereto, and a plurality of the integrated circuit packages may be exposed to test more semiconductor chips.

In addition, the first input pad10, the first output pad11, and the third input pad30may be physically balled out to the outside of the integrated circuit package100. The second input pad20and the second output pad21may be exposed inside the integrated circuit package100and may be exposed outside a chip for performing the EDS test.

The scan chain block130may include a plurality of scan chains (not shown) and may be shared by the first test circuit110and the second test circuit120. The scan chain block130stores information of the decompressed first input signal IN_1or the decompressed second input signal IN_2and enables the first compressor112and the second compressor122to efficiently generate an output signal.

The output selection circuit150may include a first terminal S1receiving a first output signal OUT_1and a second terminal S2receiving a second output signal OUT_2, and a third terminal C receiving a selection signal Select_Sig. In addition, the output selection circuit150may be connected to the first output pad11through an output terminal D. As described above, the output selection circuit150determines which one of the first output signal OUT_1and the second output signal OUT_2to be transmitted to the first output pad11.

For example, when the first output signal OUT_1is input and the logic value of the selection signal Select_Sig is in a high state, the output selection circuit150may transmit the first output signal OUT_1to the first output pad11. In addition, when the second output signal OUT_2is received and the logic value of the selection signal Select_Sig is in a low state, the output selection circuit150may transmit the second output signal OUT_2to the first output pad11.

FIG.7illustrates a scan chain block130according to example embodiments.

Referring toFIG.7, the scan chain block130includes a plurality of scan chains130_1,130_2,130_3, . . . , and130_n. In addition, the scan chain block130may include a plurality of logic blocks131and132, and may be shared by the first test circuit110and the second test circuit120through a plurality of ports PTs. According to example embodiments, the logic blocks131and132and a plurality of pods PTs may constitute an interface circuit. In addition, the first scan chain130_1, the second scan chain130_2, the third scan chain130_3, and the n-th scan chain130_nmay each include a plurality of flip-flops FFs.

Hereinafter, for convenience, scan chains provided in the scan chain block130are referred to as first scan chains130_1, second scan chains130_2, third scan chains130_3, and n-th scan chains130_n.

Each of the first scan chain130_1and the second scan chain130_2includes a plurality of flip-flops FFs. When a logic signal is input to the first scan chain130_1and the second scan chain130_2, one flip-flop FF of each of the first scan chain130_1and the second scan chain130_2stores the input logic signal until the next logic signal is input thereto, and when the next logic signal is input to the first scan chain130_1and the second scan chain130_2, the flip-flop FF stores the next input logic signal, and transfer the previous input logic signal to another flip-flop FF thereof. The first decompressor111may decompress the first input signal IN_1and transmit the decompressed first input signal to the first scan chain130_1and the second scan chain130_2. When the first input signal IN_1is received, the first compressor111may generate the first output signal OUT_1by compressing the output signals of the first scan chain130_1and the second scan chain130_2and outputting the compressed result. In addition, the logic blocks131and132and the plurality of ports PTs may be connected to the first decompressor111and the first compressor112of the first test circuit110to be tested through tests of the third scan chain130_3and the n-th scan chain130_n.

According to example embodiments, the first test circuit110and the second test circuit120may perform a test operation separately or may simultaneously perform a test operation.

FIG.8is a flowchart illustrating an operating method of an integrated circuit package100according to example embodiments.

Referring toFIG.8, a first input signal IN_1may be received by the first input pad10to perform a package test (S110). As described above, the first input pad10may be balled out outside the integrated circuit package. According to example embodiments, the first input signal IN_1is defined as a signal for a package test.

When the first input signal IN_1is received, the signal selection circuit140determines whether the logic value of the selection signal Select_Sig is “1” (S120). According to example embodiments, the meaning that the logic value is “1” means that the logic value is in a high state, and the meaning that the logic value is “0” means that the logic value is in a low state.

When it is determined that the logic value of the selection signal is “1”, the signal selection circuit140may transmit the first input signal IN_1to the first test circuit110, and the first test circuit110may receive the first input signal IN_1through the first decompressor111(S130).

When the first input signal IN_1is received by the first test circuit110, the first test circuit110processes the first input signal IN_1and outputs the first output signal OUT_1to the first output pad11(S140). According to example embodiments, the first output pad11may be balled out outside the integrated circuit package. In addition, the first test circuit110may process the first input signal IN_1by decompressing the first input signal IN_1and providing the decompressed first input signal IN_1ato the plurality of scan chains130_1,130_2, . . . , and130_n, and then compressing the received decompressed first input signal IN_1aagain.

When it is determined that the logic value of the selection signal is “0”, the signal selection circuit140may transmit the first input signal IN_1to the second test circuit120, and the second test circuit120may receive the first input signal IN_1through the second decompressor121(S150). According to example embodiments, the first input signal IN_1may be input in parallel through the input pin block123including a plurality of input terminals.

When the first input signal IN_1is received by the second test circuit120, the second test circuit120processes the first input signal IN_1and the second output signal OUT_2is output to the first output pad11(S160). According to example embodiments, the second output signal OUT_2may be transmitted to the first output pad111through the serializer124exposed inside the integrated circuit package and outside the multi-chip. Since the serializer124includes a plurality of serialized output terminals, the divided second output signal OUT_2′ may be merged into the second output signal OUT_2. In addition, the second test circuit120may process the first input signal IN_1through a process of decompressing the first input signal IN_1, providing the decompressed first input signal IN_1dthrough a plurality of scan chains130_1,130_2, . . . , and130_n, and compressing the decompressed first input signal IN_1dagain. According to example embodiments, the first output signal OUT_1may include package test result information of the semiconductor chip.

Through the above-described process, the integrated circuit package100may perform a test on whether the semiconductor package chip is defective in two modes. When performing a package test by the first test circuit110, an EDS test may also be performed by the first test circuit110so that spatial efficiency exists, and when a package test is performed by the second test circuit120, the compression rate of the first input signal IN_1may be increased, and thus efficiency exists in terms of signal processing speed.

FIG.9is a flowchart illustrating a case in which a second input signal IN_2is received in a first test circuit100in an integrated circuit package100according to example embodiments.

Referring toFIG.9, a second input signal IN_2is received by the first test circuit110to perform an EDS test on a semiconductor chip (S210). According to example embodiments, the second input signal IN_2is defined as a signal for performing an EDS test.

The second input signal IN_2may be received through the second input pad20. As described above, a plurality of second input pads20may exist. In addition, unlike the first input signal IN_1, the second input signal IN_2may be directly input to the first test circuit110without passing through the signal selection circuit140.

When the second input signal IN_2is received, the first test circuit110may process the second input signal IN_2(S220). For example, the first test circuit110may process the second input signal IN_2by decompressing the second input signal IN_2, providing the decompressed second input signal IN_2ato a plurality of scan chains130_1,130_2, . . . , and130_n, and compressing the decompressed second input signal IN_2aagain.

When the processing of the second input signal IN_2is completed, the first test circuit110outputs the second output signal OUT_2to the second output pad21(S230). The second output signal OUT_2may include EDS test result information of the semiconductor chip.

FIG.10is a flowchart illustrating a process of generating an output signal in an integrated circuit package100according to example embodiments.

Referring toFIG.10, when a package test is completed in the first test circuit110or the second test circuit120, a first output signal OUT_1and a second output signal OUT_2may be received in the output selection circuit150(S310).

When the first output signal OUT_1and the second output signal OUT_2are received, the output selection circuit150determines whether the logic value of the selection signal Select_Sig is “1” (S320). According to example embodiments, the meaning that the logic value is “1” means that the logic value is in a high state, and the meaning that the logic value is “0” means that the logic value is in a low state.

When the logic value of the selection signal is “1”, the output selection circuit150may output the first output signal OUT_1to the first output pad11(S330). However, when the logic value of the selection signal is “0”, the output selection circuit150may output the second output signal OUT_2to the first output pad11(S340).

FIG.11is a block diagram illustrating a case in which a plurality of integrated circuit packages100are exposed according to example embodiments.

Referring toFIG.11, a plurality of integrated circuit packages100may be exposed according to the number of semiconductor chips to be tested. For example, when a plurality of semiconductor chips200_1,200_2, . . . , and200nto be tested are exposed, a plurality of integrated circuit packages100_1,100_2, . . . , and100nmay be exposed on at least one chip, respectively.

One or more of the elements disclosed above may include or be implemented in one or more processing circuitries such as hardware including logic circuits; a hardware/software combination such as a processor executing software; or a combination thereof. For example, the processing circuitries more specifically may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc.