RECEIVER, OPERATION METHOD THEREOF, AND MEMORY DEVICE

A receiver includes a decoding circuit configured to convert a data signal into first and second signals having a time difference therebetween, which is a function of at least one parameter, and output decoded data based on the first signal and the second signal. A calibration circuit is provided, which is configured to calibrate a value of the at least one parameter based on one of the first signal and the second signal, and a reference timing signal, and provide a calibration signal including the calibrated value to the decoding circuit. The reference timing signal may have a reference timing that sets a ratio between a first probability and a second probability as an integer ratio.

REFERENCE TO PRIORITY APPLICATION

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2023-0075066, filed Jun. 12, 2023, the disclosure of which is hereby incorporated herein by reference.

BACKGROUND

The inventive concept relates to integrated circuit devices and, more particularly, to receivers that can be used in memory devices and methods of operating same.

High-speed transmission systems capable of high-speed data transmission are increasingly attracting attention. Demand for high-speed transmission systems is increasing in multimedia and other fields that require transmission of large amounts of data. Data transmission schemes can include a non-return to zero (NRZ) scheme and a pulse-amplitude modulation (PAM)-N scheme, for example. As will be understood by those skilled in the art, a NRZ scheme transmits 1 bit of data during 1 unit interval (UI), whereas the PAM-N scheme transmits k-bit (k satisfying 2k=N) data during 1 UI. For example, in the PAM-4 scheme, 2-bit data may be transmitted.

As the amount of data exchanged between devices and systems increases, communication circuits capable of transmitting and receiving signals at high speed are being adopted. Electronic devices can be connected through a communication channel, and the communication channel may transfer signals transmitted and received between the electronic devices. However, the bandwidth of the communication channel may be limited due to various factors, such as skin effect and dielectric loss. These factors may attenuate high-frequency components of signals transmitted through a communication channel and thus degrade the quality of signals transmitted at high speeds. As a method of improving signal quality, a method of calibrating characteristics of a receiver is being studied.

SUMMARY

The inventive concept provides a receiver for calibrating characteristics of the receiver using a probabilistic method, an operation method thereof, and a memory device including the receiver.

According to an aspect of the inventive concept, there is provided a receiver including a decoding circuit, which is configured to convert a data signal into a first signal and a second signal having a specific time difference based on at least one parameter. The decoding circuit is further configured to output decoded data based on the first signal and the second signal. A calibration circuit is provided, which is configured to: (i) calibrate a value of the at least one parameter based on one of the first signal and the second signal and a reference timing signal, and (ii) provide a calibration signal including the calibrated parameter to the decoding circuit. The reference timing signal may have a reference timing for setting a ratio between a first probability and a second probability as an integer ratio, with the first probability being a probability that the decoded data is decoded as a reference symbol among a plurality of symbols, and the second probability being a probability that the decoded data is decoded as any one symbol among the plurality of symbols.

The inventive concept also provides methods of operating a receiver including: converting a data signal into a first signal and a second signal having a specific time difference based on at least one parameter, calibrating a value of the at least one parameter based on one of the first signal and the second signal and a reference timing signal, and outputting decoded data based on the first signal and the second signal. The reference timing signal can have a reference timing for setting a ratio between a first probability and a second probability as an integer ratio. The first probability may be a probability that the decoded data is decoded as a reference symbol among a plurality of symbols, and the second probability may be a probability that the decoded data is decoded as any one symbol among the plurality of symbols.

The inventive concept also provides a memory device including a memory interface circuit configured to receive a data signal from a memory controller, and a control logic circuit configured to perform a control operation based on the data signal provided from the memory interface circuit. The memory interface circuit includes a decoding circuit that is configured to: (i) convert a data signal into a first signal and a second signal having a specific time difference based on at least one parameter, and (ii) output decoded data based on the first signal and the second signal. The memory interface circuit also includes a calibration circuit configured to: calibrate a value of the at least one parameter based on one of the first signal and the second signal and a reference timing signal, and provide a calibration signal including the calibrated parameters to the decoding circuit. The reference timing signal may have a reference timing for setting a ratio between a first probability and a second probability as an integer ratio, with the first probability being a probability that the decoded data is decoded as a reference symbol among a plurality of symbols, and the second probability being a probability that the decoded data is decoded as any one symbol among the plurality of symbols.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, embodiments of the inventive concept are described in detail with reference to the accompanying drawings.

FIG.1is a diagram for explaining a transceiver100according to embodiments of the inventive concept, which can include a transmitter110and a receiver130that are configured to communicate with each other through a channel120, as shown. The transmitter110may output a signal SIG for delivery to the receiver130via the channel120. In some embodiments, the transmitter110may convert parallel data into serial data and output the signal SIG as a serial data stream. In some other embodiments, in addition to data serialization, the transmitter110may also perform a signal equalization operation to compensate for channel loss. The signal SIG of the inventive concept may be referred to as a transmission signal.

In some embodiments, the transmitter110may transmit the signal SIG in a pulse-amplitude modulation (PAM)-N (where N is an integer greater than or equal to 3) scheme (e.g., PAM-N signaling scheme, PAM-N decoding scheme, or PAM-N mode, etc.) In this case, the signal SIG may have any one voltage level among N different voltage levels based on PAM-N. In the PAM-4 scheme, the transmitter110may transmit the signal SIG having one of four voltage levels. The four voltage levels may respectively correspond to first to fourth logic values (e.g., bit values) (e.g., ‘00’ (=00b), ‘01’ (=01b), ‘10’ (=10b), ‘11’ (=11b)). However, the voltage levels are not limited thereto. Based on various schemes, such as PAM-8 and PAM-16, the signal SIG may have one of 8 voltage levels or 16 voltage levels, for example. In some further embodiments, the signal SIG may be a single signal as a data signal. However, the signal SIG is not limited thereto, and in other embodiments, the signal SIG may include two differential signals having different polarities.

The channel120may be an electrical path connecting the transmitter110and the receiver130to each other. For example, the channel120may include a trace on a printed circuit board (PCB) or a coaxial cable. The channel120may degrade high-frequency contents of high-speed random data due to skin effect, dielectric loss, and the like. That is, channel loss may occur in the signal SIG transmitted through the channel120. In addition, the channel120may introduce impedance discontinuities (mismatches) due to connectors and other physical interfaces between boards and cables. In addition, each of the bits of data that have passed through the channel120may interfere with the next bit due to channel loss or bandwidth limitations, and intersymbol interference (ISI), a phenomenon in which a bit error rate (BER) increases as neighboring symbols overlap, may occur. Due to the phenomena caused by the channel120described above, the signal SIG′ that passes through the channel120may be partially distorted or partially deformed compared to the originally transmitted signal SIG. When the signal SIG according to some embodiments is a single signal, the signal SIG′ may also be a single signal as a data signal. The signal SIG′ of the inventive concept may be referred to as a received signal. The data signal may include, for example, a specific logical value (or bit value), such as a command, address, or data.

The receiver130may receive the signal SIG′ passing through the channel120. The receiver130may decode data based on the signal SIG′ and output decoded data. In some embodiments, the receiver130may convert the serial data received from the transmitter110into parallel data. In some other embodiments, the transmitter110may perform a signal equalization operation to compensate for channel loss in addition to a data parallelization operation.

In some embodiments, the receiver130may be implemented as a time-based receiver, and may include, among other circuits, a decoding circuit131, a calibration circuit132, and a clock generation circuit133. The decoding circuit131may convert the received signal SIG′ into a first signal and a second signal based on at least one parameter, and that parameter may be a value representing a characteristic necessary for the receiver130to decode the signal SIG′. A specific time difference may occur between the first signal and the second signal. For example, the first signal and the second signal may be sequentially output with a specific time difference. The decoding circuit131may output decoded data based on the first signal and the second signal. The decoded data may include a plurality of bit values corresponding to any one symbol among a plurality of symbols in the PAM-N scheme. For example, data decoded in the PAM-4 scheme may include 2 bits, and the 2 bits may correspond to any one symbol of ‘00’, ‘01’, ‘10’, and ‘11’.

The calibration circuit132may calibrate the value of at least one parameter based on any one of the first signal and the second signal and a reference timing signal. The calibration circuit132may provide a calibration signal including the calibrated parameters to the decoding circuit131. The reference timing signal may be a signal having reference timing for setting a ratio between a first probability and a second probability as an integer ratio. The first probability may be a probability that decoded data is decoded as a reference symbol among a plurality of symbols. The second probability may be a probability that the decoded data is decoded as any one symbol among a plurality of symbols. An integer ratio may mean, for example, 1:1, 1:2, 1:3, 2:3, and the like. For example, even if the ratio between the first probability and the second probability is 0.8:0.2, it is assumed that the ratio (e.g.,0.8:0.2) is an integer ratio.

The clock generation circuit133may generate a clock signal. The clock signal may be a signal providing timing necessary for the decoding circuit131and/or the calibration circuit132to operate. In some embodiments, the clock generation circuit133may be included inside the receiver130. However, it is not limited thereto, and in other embodiments, the clock generation circuit133may be provided external to the receiver130. According to other embodiments, the clock signal may be transmitted by the transmitter110to the receiver130. Although not wishing to be bound by any theory of operation, calibrating the parameters using a stochastic method has the effect of providing the receiver130and/or transceiver100that is insensitive to environmental changes (process, voltage, temperature (PVT) fluctuations), reducing BER, and improving ISI.

FIG.2Ais a diagram for explaining signals input to a receiver according to the inventive concept andFIG.2Bis a diagram for explaining a method of converting the voltage levels ofFIG.2Ato time. In detail,FIG.2Amay show an eye diagram for a signal generated by the PAM-4 scheme, that is, a PAM-4 signal.FIG.2Bis a graph in which the voltage level of the PAM-4 signal is converted based on time.

Referring toFIG.2A, waveforms in which bits of serially transmitted data are overlapped may resemble the shape of an eye. This waveform may be referred to as an eye diagram. The eye diagram may be used to indicate the quality of a signal SIG′ in high-speed transmission. For example, in PAM-4, the eye diagram may represent four symbols (e.g., ‘00’, ‘01’, ‘10’, and ‘11’) of the signal SIG′, and each of the four symbols may be represented by different first to fourth voltage levels VL1, VL2, VL3, and VL4. The eye diagram may be used to visually represent signal integrity and may represent the noise margin of the signal SIG′.

To generate the eye diagram, an oscilloscope or another computing device may sample signal SIG′ based on a unit interval UI (e.g., a sample period or a bit period). The unit interval UI may be defined by a clock associated with transmission of the signal SIG′. The oscilloscope or another computing device may form traces TRC by measuring the voltage level of the signal SIG′ during the unit interval UI. By overlapping the plurality of traces TRC, various characteristics of the measured signal SIG′ may be determined.

The eye diagrams may be used to identify a number of signal characteristics, such as jitter, crosstalk, signal loss, signal-to-noise ratio (SNR), and other characteristics. For example, the eye width W may be used to indicate timing synchronization of the measured signal SIG′ or jitter effects in the measured signal SIG′.

An eye opening OP represents the peak-to-peak voltage difference between various first to fourth voltage levels VL1, VL2, VL3, and VL4and may be related to a voltage margin for distinguishing the first to fourth voltage levels VL1, VL2, VL3, and VL4. In order to evaluate the performance of the transceiver100, the eye opening OP may be measured in the eye diagram. Rising time RT or falling time FT may represent the time required to transition from one voltage level to another voltage level and may be associated with a rising edge and a falling edge, respectively. The slope of the trace TRC during the rising time RT or falling time FT may represent the sensitivity of the signal SIG′ to timing errors. Jitter (JT) represents timing error due to misalignment of the rising time and the falling time, occurs when a rising or falling edge occurs at a different time than the ideal time defined by the data clock, and may be caused by signal reflections, ISI, crosstalk, PVT variations, random jitter, additive noise, or a combination thereof.

As shown inFIG.2A, the first voltage level VL1may be lower than the second voltage level VL2, the second voltage level VL2may be lower than the third voltage level VL3, and the third voltage level VL3may be lower than the fourth voltage level VL4. The receiver130may set the first to third reference levels VREF1, VREF2, and VREF3in PAM-4. The first reference level VREF1may be lower than the second reference level VREF2, and the second reference level VREF2may be lower than the third reference level VREF3. The receiver130may decode the symbol of the signal SIG′ by comparing the voltage level of the signal SIG′ with the first to third reference levels VREF1, VREF2, and VREF3.

A first eye may be located between the first and second voltage levels VL1and VL2, a second eye may be located between the second and third voltage levels VL2and VL3, and a third eye may be located between the third and fourth voltage levels VL3and VL4.

Some edges may affect characteristics of each of the eyes (e.g., the size or shape of the eye). For example, a falling edge from the fourth voltage level VL4to the first voltage level VL1(i.e., ‘11’->‘00’), a rising edge from the first voltage level VL1to the second voltage level VL2(i.e., ‘00’->‘01’), a rising edge from the first voltage level VL1to the fourth voltage level VL4(i.e., ‘00’->‘11’), and a falling edge (i.e., ‘01’->‘00’) from the second voltage level VL2to the first voltage level VL1may determine the characteristics of the first eye. In another example, a rising edge and a falling edge (i.e., ‘01’<->‘11’) between the second and fourth voltage levels VL2and VL4and a rising edge and a falling edge (i.e., ‘00’<->‘10’) between the first and third voltage levels VL1and VL3may determine the characteristics of the second eye. In another example, a rising edge and a falling edge (i.e., ‘10’<->‘11’) between the third and fourth voltage levels VL3and VL4and a rising edge and a falling edge (i.e., ‘00’<->‘11’) between the first and fourth voltage levels VL1and VL4may determine the characteristics of the third eye. Thus, an equalization or equalizing operation may be required for the edges that determine the characteristics of the eye.

Referring toFIGS.2A and2B, the receiver130according to some embodiments may be implemented as a time-based receiver. The circuit configuration included in the receiver130according to some embodiments is relatively simple, and the receiver130according to some embodiments may have a greater gain at a relatively low voltage. In the receiver130according to some embodiments, the first to fourth voltage levels VL1, VL2, VL3, and VL4ofFIG.2Amay correspond to signals having edges occurring at a specific time inFIG.2B. For example, the first voltage level VL1may correspond to a signal having an edge occurring at a first time T1, the second voltage level VL2may correspond to a signal having an edge occurring at a second time T2after the first time T1, the third voltage level VL3may correspond to a signal having an edge occurring at a third time T3after the second time T2, and the fourth voltage level VL4may correspond to a signal having an edge occurring at a fourth time T4after the third time T3. The first to fourth times T1, T2, T3, and T4may be referred to as edge timing (or “timing”, for convenience herein).

A first time difference TD1may occur between the first time T1and the second time T2, between the second time T1and the third time T3, or between the third time T1and the fourth time T4. A second time difference TD2may occur between the first time T1and the third time T3or between the second time T1and the fourth time T4. A third time difference TD3may occur between the first time T1and the fourth time T4. The first time difference TD1may be less than the second time difference TD2, and the second time difference TD2may be less than the third time difference TD3. In some embodiments, the second time difference TD2may be twice the first time difference TD1, and the third time difference TD3may be three times the first time difference TD1.

The first to third reference levels VREF1, VREF2, and VREF3ofFIG.2Amay correspond to the first to third reference times TREF1, TREF2, and TREF3, respectively. For example, the first reference level VREF1may correspond to the first reference time TREF1, the second reference level VREF2may correspond to the second reference time TREF2, and the third reference level VREF3may correspond to the third reference time TREF3. The first reference time TREF1may be shorter than the second reference time TREF2, and the second reference time TREF2may be shorter than the third reference time TREF3.

The receiver130according to the inventive concept may change the voltage level of the signal SIG′ to a signal having an edge signal occurring at a certain time and may decode the symbol of the signal SIG′ using the edge occurrence time (e.g., edge timing) and the first to third reference times TREF1, TREF2, and TREF3.

The embodiments shown inFIGS.2A and2Bhave been described based on the PAM-4 signal but are not limited thereto. For example, the number of different voltage levels and the number of edge timings in the PAM-8 signal may be 8, the number of reference levels for distinguishing the 8 voltage levels may be 7, and the number of reference times for classifying the 8 edge timings may be 7. In another example, in the PAM-16 signal, the number of voltage levels and the number of edge timings may be 16, and the number of reference levels and the number of reference times may be 15.

FIG.3is a block diagram illustrating a time-based receiver300, which may include a decoding circuit310, a calibration circuit320, and a clock generation circuit330, electrically coupled as illustrated. The decoding circuit310may receive a data signal DQ, a clock signal CK, and a calibration signal SIG_CAL from the outside. The data signal DQ may correspond to the received signal SIG′ ofFIG.1. The data signal DQ may be a PAM-N signal. The calibration signal SIG_CAL may include parameter values. When the number of parameters is two or more, the number of calibration signals SIG_CAL may be two or more. The decoding circuit310may convert the data signal DQ into a first signal SIG1and a second signal SIG2based on at least one parameter and may output the first signal SIG1and the second signal SIG2to the calibration circuit320. The decoding circuit310may output decoded data DDATA based on the first signal SIG1and the second signal SIG2.

A circuit configuration included in the decoding circuit310is relatively simple, and the decoding circuit310may have a greater gain at a relatively low voltage. However, because the decoding operation (or data processing operation) performed by the decoding circuit310is performed as a function of time, the decoding operation may be sensitive to the delay time conversion of the logic gate(s). In addition, the calibration circuit320may receive the first signal SIG1, the second signal SIG2, and the clock signal CK. The calibration circuit320may generate a reference timing signal (not shown) based on the clock signal CK. The calibration circuit320may output the calibration signal SIG_CAL including calibrated parameters to the decoding circuit310, based on any one selected from the first signal SIG1and the second signal SIG2and the reference timing signal. Finally, as shown, the clock generation circuit330may output the clock signal CK to the decoding circuit310and the calibration circuit320.

FIG.4is a diagram illustrating some embodiments of the receiver ofFIG.3. In particular, as shown byFIG.4, a receiver400may include a decoding circuit401and a calibration circuit402. The decoding circuit401may include a differential signal converter410, a voltage-to-time converter420, a decision feedback equalization (DFE)430, and a decoder440.

The differential signal converter410may receive a data signal DQ, a clock signal CK, and a first calibration signal V_REF. The first calibration signal V_REF may be a signal indicating a first parameter such as a reference voltage level. The voltage level of the first calibration signal V_REF may correspond to the value of the first parameter, that is, the reference voltage level. The differential signal converter410may be configured to convert the data signal DQ into a first differential signal DSIG1and a second differential signal DSIG2. For example, the differential signal converter410may compare the voltage level of the data signal DQ with the voltage level (e.g., a reference voltage level) of the first calibration signal V_REF in response to the clock signal CK and may output a first differential signal DSIG1and a second differential signal DSIG2each having a specific voltage level based on the comparison result. The first differential signal DSIG1and the second differential signal DSIG2may have polarities opposite to each other, and be treated herein as “differential” signals. For example, when the voltage level of the data signal DQ is equal to or greater than the reference voltage level, the differential signal converter410may output a first differential signal DSIG1having a positive polarity and a second differential signal DSIG2having a negative polarity. When the voltage level of the data signal DQ is lower than the reference voltage level, the differential signal converter410may output a first differential signal DSIG1having a negative polarity and a second differential signal DSIG2having a positive polarity. In another example, the voltage levels of the first differential signal DSIG1and the second differential signal DSIG2may be determined depending on the difference between the voltage level of the data signal DQ and the reference voltage level. The differential signal converter410of the inventive concept may be referred to as a signal to differential (S2D) amplifier. Because the receiver400is a time-based receiver, signal integrity may be affected by offsets in the magnitude of the reference voltage supplied to the differential signal converter410.

The voltage time converter420may receive a clock signal CK, a second calibration signal VTC_GAIN, a first differential signal DSIG1, and a second differential signal DSIG2. The second calibration signal VTC_GAIN may be a signal indicating a second parameter representing a voltage time gain. The voltage time gain may be the ratio of edge timing to unit voltage level. For example, when the unit voltage level is 1 [V] and the edge timing is 10 [ps], the voltage time gain may be 10 [ps/V]. That is, when the voltage difference between the first differential signal DSIG1and the second differential signal DSIG2is 1 V, a first conversion signal CSIG1and a second conversion signal CSIG2having a time difference of 10 [ps] may be output. The voltage level of the second calibration signal VTC_GAIN may correspond to the value of the first parameter, that is, the voltage time gain. The voltage time converter420may be configured to sequentially output the first conversion signal CSIG1and the second conversion signal CSIG2based on the first differential signal DSIG1and the second differential signal DSIG2. In some embodiments, the voltage time converter420may convert a level difference between the voltage level of the first conversion signal CSIG1and the voltage level of the second conversion signal CSIG2into a time difference by using the voltage time gain, and may sequentially output the first conversion signal CSIG1and the second conversion signal CSIG2with a time difference. A time difference between the first conversion signal CSIG1and the second conversion signal CSIG2may correspond to a voltage level difference between the first differential signal DSIG1and the second differential signal DSIG2. For example, the voltage time converter420may output the first conversion signal CSIG1having the first edge timing with respect to the first voltage level of the first differential signal DSIG1by using the voltage time gain. Also, the voltage time converter420may output the second conversion signal CSIG2having the second edge timing for the second voltage level of the second differential signal DSIG2by using the voltage time gain. A time difference between the first edge timing and the second edge timing may correspond to a voltage level difference between the first differential signal DSIG1and the second differential signal DSIG2.

The DFE430is a non-linear equalizer and may cancel or at least substantially reduce ISI of currently sampled data using previously sampled data. That is, the DFE430may restore the distorted signal to a signal having an original shape. The DFE430may receive the first conversion signal CSIG1, the second conversion signal CSIG2, and a third calibration signal DFE_TAP CODE. The third calibration signal DFE_TAP CODE may include a code for adjusting the DFE tap coefficient. The code for adjusting the DFE tap coefficient may be, for example, 4 bits (e.g., <3:0>) but is not limited thereto. The DFE430may output a first signal MP and a second signal MN having an adjusted time difference, based on the third calibration signal DFE_TAP CODE, the first conversion signal CSIG1, the second conversion signal CSIG2, and the previously decoded data MSB [n−1] and LSB [n−1]. In some embodiments, the DFE430may change the adjustment amount for adjusting the time difference, based on the code of the third calibration signal DFE_TAP CODE and the bit values of previously decoded data MSB [n−1] and LSB [n−1].

The decoder440may be configured to determine bit values of the decoded data MSB [n] and LSB [n], based on a first-input signal among the first signal MP and the second signal MN. The calibration circuit402may receive the clock signal CK, previously decoded data MSB [n−1] to LSB [n−1], the first signal MP, and the second signal MN. The calibration circuit402may output at least one of the first calibration signal V_REF and the second calibration signal VTC_GAIN, based on the clock signal CK, the first signal MP, and the second signal MN. The calibration circuit402may output the third calibration signal DFE_TAP CODE, based on the clock signal CK, previously decoded data MSB [n−1] and LSB [n−1], the first signal MP, and the second signal MN. The first calibration signal V_REF and the second calibration signal VTC_GAIN may be analog signals, and the third calibration signal DFE_TAP CODE may be a digital signal. In some embodiments, the calibration circuit402may calibrate the DFE tap coefficient of the DFE430using a positive signal aligned with the reference timing signal among the first signal MP and the second signal MN.

FIG.5is a diagram illustrating some embodiments of the decoder ofFIG.4. In particular, the decoder500ofFIG.5may include a first time comparator510, a first delay520, a second delay530, and a second time comparison circuit540. The first time comparator510may receive a first signal MP and a second signal MN. The first signal MP and the second signal MN may be sequentially input with a specific time difference therebetween. A time difference between the first signal MP and the second signal MN may correspond to a voltage level difference between the first differential signal DSIG1and the second differential signal DSIG2. As the voltage level difference increases, the time difference may also increase, and as the voltage level difference decreases, the time difference may also be decrease. The first signal MP may be input to the first delay unit520and the second signal MN may be input to the second delay unit530.

The first time comparator510may determine a first bit value depending on a first first-arrived signal among the first signal MP and the second signal MN. In some embodiments, the first bit value may be, for example, a most significant bit (MSB) of the PAM-4 signal. For example, when the first first-arrived signal is the first signal MP, the MSB value may be a first value, and when the first first-arrived signal is the second signal MN, the MSB value may be a second value. For example, the first value may be ‘1(=1b)’ and the second value may be ‘0(=0b)’. However, the first value and the second value are not limited thereto, and the first value may be ‘0’ and the second value may be ‘1’. The first time comparator510may output first data MSB [n] including the currently output MSB. In some embodiments, the first time comparator510may output flip data MSB [n] _BAR including a flip bit value obtained by bit flipping a currently output MSB. In other embodiments, the inverter may output the flip data MSB [n] _BAR by inverting the MSB of the first data MSB [n].

Each of the first data MSB [n] and the flip data MSB [n] _BAR may be an enable signal for further delay by the threshold delay time. InFIG.5, the first data MSB [n] may be input to the first delay unit520and flip data MSB [n] _BAR may be input to the second delay unit530. However, it is not limited thereto, and in other embodiments, the first data MSB [n] may be input to the second delay530and the flip data MSB [n] _BAR may be input to the first delay520. An operation of further delaying by the threshold delay time may be performed depending on the logic value of the enable signal. For example, a delay circuit receiving a first bit value among the first and second delayers520and530may be enabled. However, the operation of further delaying is not limited thereto.

The first delay520may receive the first signal MP and the first data MSB [n], may adjust the amount of delay to delay the first signal MP depending on the bit value of the first data MSB [n], and may output a first delay signal LP obtained by delaying the first signal MP. For example, when the MSB of the first data MSB [n] is the first value, the first signal MP may be delayed by the sum of the reference delay time and the threshold delay time. When the MSB of the first data MSB [n] is the second value, the first signal MP may be delayed by the reference delay time.

The second delay530may receive the second signal MN and the flip data MSB [n] _BAR, may adjust the amount of delay to delay the second signal MN depending on the bit value of the flip data MSB [n] _BAR, and may output a second delay signal LN obtained by delaying the second signal MN. For example, when the MSB of the first data MSB [n] is the first value, the bit value of the flip data MSB [n] _BAR is the second value, so the second signal MN may be delayed by the reference delay time. When the MSB of the first data MSB [n] is the second value, the first signal MP may be delayed by the sum of the reference delay time and the threshold delay time.

The second time comparator540may receive the first delayed signal LP and the second delayed signal LN. The second time comparator540may determine a second bit value depending on a second, first-arrived, signal among the first delayed signal LP and the second delayed signal LN. In some embodiments, when the first bit value is an MSB, the second bit value may be a least significant bit (LSB). For example, when the second first-arrived signal is the first delayed signal LP, the value of the LSB may be the first value, and when the second first-arrived signal is the second delayed signal LN, the value of the LSB may be the second value. The second time comparator540may output second data LSB [n] including the currently output LSB.

FIG.6is a diagram of some embodiments of the calibration circuit ofFIG.4. This calibration circuit600may include a selector610, a reference timing signal generator620, a time comparator630, a coefficient weight controller640, and a DFE controller650, a counter group660, a calibration control logic670, a first digital to analog converter (DAC,680), and a second DAC690.

The selector610may be configured to output a selection signal SEL selected from among a first signal MP and a second signal MN. In some embodiments, the selector610may select the first signal MP or the second signal MN depending on the logic level of a first control signal CTRL1. For example, when the logic level of the first control signal CTRL1is the first logic level, the selector610may output the first signal MP as the selection signal SEL. When the logic level of the first control signal CTRL1is the second logic level, the selector610may output the second signal MN as the selection signal SEL. In some embodiments, a positive signal of the first signal MP and the second signal MN may be used to calibrate the voltage time gain and a negative signal of the first signal MP and the second signal MN may be used to calibrate the reference voltage level.

The reference timing signal generator620may be configured to generate a reference timing signal SIG_TRTM based on a first clock signal CK1. In some embodiments, the first clock signal CK1may be the clock signal CK ofFIG.4. The reference timing signal SIG_TRTM may be a signal having reference timing. The reference timing is described below with reference toFIG.9. The time comparator630may be configured to output a first output signal OS1and an inverted comparison signal OSB based on the selection signal SEL and the reference timing signal SIG_TRTM. The inverted comparison signal OSB may be an inverted signal of the first output signal OS1. The time comparator630may determine the logic level of the first output signal OS1depending on a first-input signal among the selection signal SEL and the reference timing signal SIG_TRTM.

The coefficient weight controller640may be configured to receive the inverted comparison signal OSB. Whenever the inverted comparison signal OSB is input as many times as the number of inputs corresponding to an integer ratio, the coefficient weight controller640may be configured to output the second output signal OS2. For example, when the integer ratio is 1:4, the number of inputs is 4 times, and in this case, the coefficient weight controller640may output the second output signal OS2whenever the inverted comparison signal OSB is input four times.

The DFE controller650may be configured to output a third output signal OS3based on previously decoded data MSB [n−1] and LSB [n−1]. In some embodiments, the DFE controller650may output the third output signal OS3depending on the logic level of a third control signal CTRL3.

The counter group660may output at least one of the first and second digital signals V_REF_D and VTC_GAIN_D and a third calibration signal DFE_TAP CODE, based on the first output signal OS1, the second output signal OS2, and the third output signal OS3. The counter group660may include a plurality of counters. The counter group660may output at least one signal in response to a second clock signal CK2. In some embodiments, the period of the second clock signal CK2may be greater than that of the first clock signal CK1. That is, the frequency of the second clock signal CK2may be less than the frequency of the first clock signal CK1.

The first DAC670may convert a first digital signal V_REF_D into a first calibration signal V_REF. The second DAC680may convert the second digital signal VTC_GAIN_D into a second calibration signal VTC_GAIN.

FIG.7is a diagram illustrating some embodiments of the counter group ofFIG.6. This counter group700may include a first counter710, a second counter720, and a third counter730. The first counter710, the second counter720, and the third counter730may output signals in response to the second clock signal CK2. The first counter710may output a first digital signal V_REF_D based on the first output signal OS1and the second output signal OS2. In some embodiments, the first counter710may perform an operation or be idle depending on the logic level of a first sub control signal CTRL2_1.

The second counter720may output a second digital signal VTC_GAIN_D based on the first output signal OS1and the second output signal OS2. In some embodiments, the second counter720may perform an operation or be idle depending on the logic level of a second sub control signal CTRL2_2. The third counter730may output a third calibration signal DFE_TAP CODE based on the first output signal OS1, the second output signal OS2, and the third output signal OS3. In some embodiments, the third counter730may perform an operation or be idle depending on the logic level of a third sub control signal CTRL2_3. The first sub control signal CTRL2_1, the second sub control signal CTRL2_2, and the third sub control signal CTRL2_3may be included in the second control signal CTRL2ofFIG.6.

FIG.8is a diagram illustratively showing the probability that a signal input to a receiver is determined to be a specific symbol based on the voltage level of the signal. The eye diagram EYE-DIAGRAM ofFIG.8is based on a non-return to zero (NRZ) signal for convenience of description. However, an embodiment of the inventive concept may be applied to an eye diagram based on a PAM-N signal.

Referring toFIG.8, the probability that the NRZ signal is determined as a specific symbol in the eye diagram EYE-DIAGRAM may vary depending on the voltage level of the NRZ signal. An example of a probability density function (PDF) representing the probability that the symbol of the NRZ signal is ‘1’ and a PDF representing the probability that the symbol of the NRZ signal is ‘0’ are shown inFIG.8. Each PDF may be distributed in the form of a standard normal distribution. In detail, for example, based on a specific voltage level of the NRZ signal in each PDF, the probability value may decrease as the distance from the specific voltage level increases.

Because the symbol of the NRZ signal is ‘1’ or ‘0’, the total probability (e.g., the area of the PDF) of a PDF representing a probability that a symbol becomes ‘1’ or a PDF representing a probability that a symbol becomes ‘0’ may be 0.5. As shown in “B1” inFIG.8, when the voltage level of the NRZ signal with the highest probability that the symbol becomes ‘1’ is lowered by ‘D’, the voltage value for the probability that the symbol becomes ‘1’ in the PDF may be a value spaced apart by ‘σ’ from the voltage value that has the highest probability that the symbol becomes ‘1’.

As shown in “B0” inFIG.8, when the voltage level of the NRZ signal with the highest probability that the symbol becomes ‘0’ increases by ‘D’, the value of the voltage for the probability that the symbol becomes ‘0’ in the PDF may be a value spaced apart by ‘σ’ from the value of the voltage that has the highest probability that the symbol becomes ‘0’. In addition, as shown in “a” inFIG.8, at an intermediate voltage level between a voltage level corresponding to the highest probability that a symbol becomes ‘0’ and a voltage level corresponding to the highest probability that a symbol becomes ‘1’, the probability of the intermediate voltage level may be zero. A cumulative distribution function (CDF) of the NRZ signal may represent a distribution obtained by cumulatively summing a PDF representing a probability that a symbol becomes ‘1’ and a PDF representing a probability that a symbol becomes ‘0’. An example of the CDF of the NRZ signal may be shown as shown inFIG.8.

FIG.9is a diagram illustratively illustrating a probability that a PAM-4 signal input to a time-based receiver is determined to be a specific symbol based on edge timing;FIG.9is shown based on the PAM-4 signal for convenience of explanation. Referring toFIGS.1,2A,2B,8, and9, as described above with reference toFIGS.2A and2B, the PAM-4 signal may be changed into a signal having an edge occurring at a specific edge timing by the time-based receiver130. As described above with reference toFIG.8, because the symbol of the PAM-4 signal converted on a time basis is ‘00’, ‘01’, ‘10’, or ‘11’, the probability that the symbol of the PAM-4 signal is ‘00’, ‘01’, ‘10’, or ‘11’ may be 0.25 as the total probability of the PDF (e.g., the area of the PDF). An example of the CDF of the PAM-4 signal may be shown as shown inFIG.9.

In the PAM-4 signal, the reference symbol may be, for example, ‘11’. However, the reference symbol is not limited thereto. Based on the movement axis spaced by a certain shift amount from the PDF axis passing through the peak value of the PDF corresponding to the highest probability that the PAM-4 signal may be the reference symbol, that is, ‘11’, the first PDF area and the second PDF area may be distinguished from each other. The shift amount may be, for example, 0.84σ. In this case, a first PDF area may be an area of a PDF corresponding to ‘11’ having an edge timing greater than the edge timing of the movement axis. A second PDF area may be an area of a PDF having an edge timing less than the edge timing of the movement axis. For example, the second PDF area may include an area of the PDF corresponding to ‘00’, an area of the PDF corresponding to ‘01’, an area of the PDF corresponding to ‘10’, and a partial area of the PDF corresponding to ‘11’. The first PDF area and the second PDF area represent probabilities, and based on the shift amount of 0.84σ, the ratio of the first PDF area to the second PDF area may be 0.2:0.8. The shift amount may be determined to be 0.84σ so that the first probability to the second probability is set at a ratio of 1:4. In this case, a reference timing (TRTM) may be set so that the ratio of the first probability to the second probability is 1:4. However, it is not limited thereto, and a shift amount and a reference timing TRTM may be determined to set the first probability and the second probability as an integer ratio. That is, as shown in the example ofFIG.9, when the edge timing corresponding to a part spaced by 0.84σ from the center of the “11” symbol of the PAM-4 signal is set to the reference timing TRTM, the ratio of each PDF area is 1:4, so the calibration circuit401may calibrate parameters by comparing the reference timing signal SIG_TRTM with the first and second signals MP and MN using this characteristic.

FIGS.10A,10B,10C,10D,10E, and10Fare views for explaining embodiments of calibrating parameter values. InFIGS.10A,10B,10C,10D,10E, and10F, examples of graphs in which the horizontal axis represents the voltage level Tx[V] of the transmission signal and the vertical axis represents the delay time Delay[s] are shown. Also, examples of a graph in which the horizontal axis represents cycles and the vertical axis represents time difference MP-MN [ps] are shown.

The embodiment shown inFIG.10Ashows an initial state of the receiver130as an example. Referring toFIG.10A, the delay time of the first signal MP may increase as the voltage level Tx[V] of the transmission signal increases. The delay time of the second signal MN may decrease as the voltage level Tx[V] of the transmission signal increases. The delay time of the first signal MP and the delay time of the second signal MN may be different from each other based on the common mode transmission signal Tx,cm. Accordingly, graph lines representing the time difference between the first signal MP and the second signal MN may be displayed closer to ‘0 [ps]’ compared toFIG.10E.

The embodiment shown inFIG.10Bshows an example of cycles for calibrating the voltage time gain (VTC_GAIN). Referring toFIG.10B, as the voltage time gain is calibrated based on the positive first signal MP and the reference timing TRTM, the slope of the delay time of the first signal MP with respect to the voltage level Tx[V] of the transmission signal may increase. Also, the slope of the delay time of the second signal MN with respect to the voltage level Tx[V] of the transmission signal may decrease. That is, the absolute value of the slope of the delay time of the second signal MN may increase. The interval between the graph lines representing the time difference between the first signal MP and the second signal MN may be maintained after being spaced until the cycle progresses to a certain extent.

The embodiment shown inFIG.10Cillustratively shows cycles for calibrating the reference voltage level (V_REF). Referring toFIG.10C, as the reference voltage level is calibrated based on the negative second signal MN and the reference timing TRTM, a graph representing the delay time of the first signal MP with respect to the voltage level Tx[V] of the transmission signal may be translated in parallel as shown inFIG.10C. Also, a graph representing the delay time of the second signal MN with respect to the voltage level Tx[V] of the transmission signal may be moved in parallel as shown inFIG.10C. In the graph lines representing the time difference between the first signal MP and the second signal MN, the time difference may increase overall as the cycle progresses, and then the time difference may be maintained at a constant value.

The embodiment shown inFIG.10Dillustratively illustrates cycles of calibrating the voltage time gain (VTC_GAIN). Referring toFIG.10D, as the voltage time gain is calibrated based on the positive first signal MP and the reference timing TRTM, the slope of the delay time of the first signal MP with respect to the voltage level Tx[V] of the transmission signal may decrease. Also, the slope of the delay time of the second signal MN with respect to the voltage level Tx[V] of the transmission signal may increase. That is, the absolute value of the slope of the delay time of the second signal MN may decrease. The distance between the graph lines representing the time difference between the first signal MP and the second signal MN may be maintained after being close to each other until the cycle progresses to a certain extent.

The embodiment shown inFIG.10Eillustratively shows cycles of calibrating the reference voltage level (V_REF). Referring toFIG.10E, as the reference voltage level is calibrated based on the negative second signal MN and the reference timing TRTM, a graph showing the delay time of the first signal MP with respect to the voltage level Tx[V] of the transmission signal may be translated in parallel as shown inFIG.10E. Also, a graph representing the delay time of the second signal MN with respect to the voltage level Tx[V] of the transmission signal may be moved in parallel as shown inFIG.10E. In the graph lines representing the time difference between the first signal MP and the second signal MN, the time difference may decrease as a whole as the cycle progresses, and then the time difference may be maintained at a constant value.

In some embodiments, voltage time gain and reference voltage level may be calibrated alternately. Referring toFIGS.10B,10C,10D, and10E, for example, after the voltage time gain is calibrated as shown inFIG.10B, the voltage time gain may be calibrated as shown inFIG.10C, then the voltage time gain is calibrated as shown inFIG.10D, and finally the voltage time gain may be calibrated as shown inFIG.10E. However, the calibration sequence is not limited to the above. In other embodiments, because voltage time gain and reference voltage level may occur simultaneously, the voltage time gain and the reference voltage level may be repeatedly and simultaneously calibrated.

The embodiment shown inFIG.10Fillustratively shows the final state of the receiver130after calibration of the voltage time gain and reference voltage level is completed. When calibrating the voltage time gain, the first signal MP may be aligned with the reference timing signal SIG_TRTM. When calibrating the reference voltage level, the second signal MN may be aligned with the reference timing signal SIG_TRTM. A delay time of the first signal MP in the common mode transmission signal Tx,cm may be the same as that of the second signal MN. Accordingly, graph lines representing the time difference between the first signal MP and the second signal MN may be sufficiently spaced from the first to third reference times TREF1, TREF2, and TREF3ofFIGS.2B and10E. Accordingly, there is an effect of accurately decoding the transmission signal, the reception signal, or the data signal DQ.

In some embodiments, the logic to calibrate the DFE tap coefficients may be the same as the calibration logic for the voltage time gain and reference voltage level. For example, the delay time (or edge timing, timing) corresponding to symbol ‘11’ may be aligned with the reference timing TRTM through the voltage time gain and calibration logic for the reference voltage level. Then, the calibration circuit401detects the transition from symbol ‘00’ to symbol ‘11’, and compares the edge timing at the transition with the reference timing TRTM to determine whether under-equalization or over-equalization has occurred. The calibration circuit401may set the MSB coefficient to twice the LSB coefficient in the DFE tap coefficient.

is a diagram illustrating an example of a first digital signal and a second digital signal based on cycles. Referring toFIGS.6and11, a first digital signal V_REF_D may include a reference voltage level code. A second digital signal VTC_GAIN_D may include a voltage time gain code. As certain cycles progress, the reference voltage level code of the first digital signal V_REF_D gradually may increase and the voltage time gain code of the second digital signal VTC_GAIN_D may gradually decrease. After certain cycles, codes of the first digital signal V_REF_D and the second digital signal VTC_GAIN_D may be substantially constant or converge to a specific value. The root mean squared error (RMSE) for the reference voltage level code of the first digital signal V_REF_D may be about 2.65 LSB, and the RMSE of the voltage time gain code of the second digital signal VTC_GAIN_D may be about 2.35 LSB. As described above, there is an effect of implementing a time-based receiver that is insensitive to environmental changes.

FIG.12is a flowchart illustrating a method of operating a receiver, according to embodiments. Referring toFIG.12, operations S1210, S1220, and S1230may be performed by the receiver130. In operation S1210, the converting of the data signal DQ into a first signal MP and a second signal MN having a specific time difference based on at least one parameter is performed. Then, in operation S1220, calibrating the value of at least one parameter based on any one of the first signal MP and the second signal MN and a reference timing signal SIG_TRTM is performed. The reference timing signal SIG_TRTM may be a signal having reference timing TRTM. The reference timing TRTM may be set such that a ratio between a first probability and a second probability is an integer ratio. The first probability may be a probability that decoded data is decoded as a reference symbol among a plurality of symbols. The second probability may be a probability that decoded data is decoded into any one symbol among the remaining symbols other than the reference symbol in the plurality of symbols. Referring toFIG.9, for example, the reference timing TRTM may be set such that the reference symbol is ‘11’ and the ratio of the first probability and the second probability is ‘0.2:0.8 (=1:4)’. Finally, in operation S1230, the decoded data based on the first signal and the second signal is output.

FIG.13is a flowchart for describing some embodiments of calibrating the value of a parameter. Referring toFIG.13, operation S1300of calibrating the value of the parameter may correspond to operation S1220ofFIG.11. Operation S1300of calibrating the value of the parameter may be performed by the calibration circuit600ofFIG.6. Next, in operation S1310, an outputting of the selection signal SEL by selecting one of the first signal MP and the second signal MN is performed. Operation S1310may be performed by the selector610ofFIG.6. Then, in operation S1320, an operation of generating a reference timing signal SIG_TRTM based on the clock signal CK is performed; this operation S1320may be performed by the reference timing signal generator620ofFIG.6.

Then, in operation S1330, an operation of outputting the first output signal OS1and the inversion comparison signal OSB based on the first input signal among the selection signal SEL and the reference timing signal SIG_TRTM is performed. The inversion comparison signal OSB may be an inverted signal of the first output signal OS1; operation S1330may be performed by the time comparator630ofFIG.6.

In operation S1340, the second output signal OS2is output whenever the received inversion comparison signal OSB is input as many times as the number of inputs corresponding to the integer ratio. Operation S1340may be performed by the coefficient weight controller640ofFIG.6. In operation S1350, the third output signal OS3is output based on the previously decoded data MSB [n−1] and LSB [n−1]; operation S1350may be performed by the time comparator630ofFIG.6.

In operation S1360, at least one calibration signal among the first calibration signal V_REF, the second calibration signal VTC_GAIN, and the third calibration signal DFE_TAP CODE is output based on the first output signal OS1, the second output signal OS2, and the third output signal OS3; operation S1350may be performed by the counter group660ofFIG.6.

FIG.14is a flowchart for explaining additional embodiments of an operation of calibrating a value of a parameter. Referring toFIG.14, operation S1300′ of calibrating the value of the parameter may correspond to operation S1220shown inFIG.11, and may be performed by the calibration circuit402ofFIG.4. In operation S1300′ shown inFIG.14, the at least one parameter may include a first parameter representing a reference voltage level, a second parameter representing a voltage time gain, and a third parameter representing a code for adjusting a DFE tap coefficient.

In operation S1410, the first parameter and the second parameter are alternately calibrated every plurality of calibration cycles. In operation S1420, whether calibration of the first and second parameters is completed is checked. And, when calibration of the first and second parameters is not completed (No in operation S1420), operation S1410is performed. However, when the calibration of the first and second parameters is completed (Yes in operation S1420), after completing the calibration of each of the first and second parameters through a plurality of calibration cycles, in operation S1430, the third parameter is calibrated.

FIG.15is a flowchart for explaining some embodiments of operation S1410ofFIG.14. Referring toFIG.15, operation S1410may include operations S1510and S1520. In operation S1510, an operation of calibrating a first parameter based on the first signal MP and the reference timing signal SIG_TRTM is performed in a first calibration cycle. In some embodiments of operation S1510, the polarity of the first signal MP may be negative or the first signal MP may be a negative signal.

In operation S1520, the second parameter based on the second signal MN and the reference timing signal SIG_TRTM is calibrated in a second calibration cycle after the first calibration cycle. In some embodiments of operation S1510, the polarity of the second signal MN may be positive or the second signal MN may be a positive signal.

FIG.16is a block diagram illustrating a memory system according to embodiments. Referring toFIG.16, a memory system1300may include a memory controller1310and a memory device1320. The memory device1320may include first to eighth pins P11to P18, a memory interface circuit1321, a control logic circuit1322, and a memory cell array1323.

The memory interface circuit1321may receive a chip enable signal nCE from the memory controller1310through the first pin P11. The memory interface circuit1321may transmit and receive signals to and from the memory controller1310through the second to eighth pins P12to P18depending on the chip enable signal nCE. For example, when the chip enable signal nCE is in an enabled state (e.g., low level), the memory interface circuit1321may transmit and receive signals to and from the memory controller1310through the second to eighth pins P12to P18. In addition, the memory interface circuit1321may receive a command latch enable signal CLE, an address latch enable signal ALE, and a write enable signal nWE from the memory controller1310through the second to fourth pins P12to P14. The memory interface circuit1321may receive the data signal DQ from the memory controller1310or transmit the data signal DQ to the memory controller1310through the seventh pin P17. Command CMD, address ADDR, and data DATA may be transferred through the data signal DQ. For example, the data signal DQ may be transferred through a plurality of signal lines. In this case, the seventh pin P17may include a plurality of pins corresponding to a plurality of data input/output signals.

The memory interface circuit1321may obtain the command CMD from the data signal DQ received during the enable period (e.g., high level state) of the command latch enable signal CLE based on the toggle timings of the write enable signal nWE. The memory interface circuit1321may obtain the address ADDR from the data signal DQ received during the enable period (e.g., high level state) of the address latch enable signal ALE based on the toggle timings of the write enable signal nWE.

In an embodiment, the write enable signal nWE may toggle between a high level and a low level while maintaining a toggle off state (e.g., a high level or a low level). For example, the write enable signal nWE may toggle during a period in which the command CMD or address ADDR is transmitted. Accordingly, the memory interface circuit1321may obtain the command CMD or address ADDR based on the toggle timings of the write enable signal nWE.

The memory interface circuit1321may receive the read enable signal nRE from the memory controller1310through the fifth pin P15. The memory interface circuit1321may receive the data strobe signal DQS from the memory controller1310through the sixth pin P16or transmit the data strobe signal DQS to the memory controller1310. During the data output operation of the memory device1320, the memory interface circuit1321may receive the toggling read enable signal nRE through the fifth pin P15before outputting the data DATA. The memory interface circuit1321may generate a data strobe signal DQS that toggles in response to toggling of the read enable signal nRE. The memory interface circuit1321may transmit the data signal DQ including the data DATA based on the toggle timing of the data strobe signal DQS. Accordingly, the data DATA may be transmitted to the memory controller1310in alignment with the toggle timing of the data strobe signal DQS.

In a data input operation of the memory device1320, when a data signal DQ including data DATA is received from the memory controller1310, the memory interface circuit1321may receive a data strobe signal DQS that toggles along with the data DATA from the memory controller1310. The memory interface circuit1321may obtain data DATA from the data signal DQ based on the toggle timing of the data strobe signal DQS. For example, the memory interface circuit1321may obtain the data DATA by sampling the data signal DQ at the rising edge and the falling edge of the data strobe signal DQS.

The memory interface circuit1321may transmit a ready/busy output signal nR/B to the memory controller1310through the eighth pin P18. The memory interface circuit1321may transmit state information of the memory device1320to the memory controller1310through the ready/busy output signal nR/B. When the memory device1320is busy (i.e., when internal operations of the memory device1320are being performed), the memory interface circuit1321may transmit a ready/busy output signal nR/B indicating a busy state to the memory controller1310. In contrast, when the memory device1320is in the ready state (i.e., when internal operations of the memory device1320are not performed or have completed), the memory interface circuit1321may transmit a ready/busy output signal nR/B indicating a ready state to the memory controller1310.

In some embodiments, the memory interface circuit1321may include a decoding circuit401and a calibration circuit402. The control logic circuit1322may generally control various operations of the memory device1320. The control logic circuit1322may perform a control operation based on the data signal DQ provided from the memory interface circuit1321. The control logic circuit1322may generate control signals for controlling other elements of the memory device1320based on a command and/or an address CMD/ADDR obtained from the memory interface circuit1321. For example, the control logic circuit1322may generate various control signals for programming data DATA into the memory cell array1323or reading data DATA from the memory cell array1323.

The memory cell array1323may store data DATA obtained from the memory interface circuit1321under the control of the control logic circuit1322. The memory cell array1323may output stored data DATA to the memory interface circuit1321under the control of the control logic circuit1322. The memory cell array1323may include a plurality of memory cells. For example, the plurality of memory cells may be a resistive random access memory (RRAM) cell, a ferroelectric random access memory (FRAM) cell, a phase change random access memory (PRAM) cell, a thyristor random access memory (TRAM) cell, a magnetic random access memory (MRAM) cell, a dynamic random access memory (DRAM) cell, a flash memory cell, and the like.

The memory controller1310may include first to eighth pins P21to P28and a controller interface circuit1311. The first to eighth pins P21to P28may correspond to the first to eighth pins P11to P18of the memory device1320. The controller interface circuit1311may transmit the chip enable signal nCE to the memory device1320through the first pin P21. The controller interface circuit1311may transmit/receive signals with the memory device1320selected through the chip enable signal nCE through second to eighth pins P22to P28.

The controller interface circuit1311transmits the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE to a memory device1320through second to fourth pins P22to P24. The controller interface circuit1311may transmit the data signal DQ to the memory device1320or receive the data signal DQ from the memory device1320through the seventh pin P27.

The controller interface circuit1311may transmit the data signal DQ including the command CMD or address ADDR to the memory device1320together with the toggling write enable signal nWE. The controller interface circuit1311may transmit the data signal DQ including the command CMD to the memory device1320as the command latch enable signal CLE in the enabled state is transmitted, and may transmit the data signal DQ including the address ADDR to the memory device1320as the address latch enable signal ALE in the enabled state is transmitted.

The controller interface circuit1311may transmit the read enable signal nRE to the memory device1320through the fifth pin P25. The controller interface circuit1311may receive the data strobe signal DQS from the memory device1320through the sixth pin P26or transmit the data strobe signal DQS to the memory device1320.

In a data output operation of the memory device1320, the controller interface circuit1311may generate a toggling read enable signal nRE and transmit the read enable signal nRE to the memory device1320. For example, the controller interface circuit1311may generate a read enable signal nRE that changes from a toggle off state (e.g., high level or low level) to a toggle state before data DATA is output. Accordingly, the memory device1320may generate a data strobe signal DQS that toggles in response to the read enable signal nRE. The controller interface circuit1311may receive the toggling data strobe signal DQS and the data signal DQ including the data DATA from the memory device1320. The controller interface circuit1311may obtain data DATA from the data signal DQ based on the toggle timing of the data strobe signal DQS.

In a data input operation of the memory device1320, the controller interface circuit1311may generate a toggling data strobe signal DQS. For example, the controller interface circuit1311may generate a data strobe signal DQS that changes from a toggle off state (e.g., high level or low level) to a toggle state before transmitting data DATA. The controller interface circuit1311may transmit the data signal DQ including the data DATA to the memory device1320based on the toggle timings of the data strobe signal DQS. The controller interface circuit1311may receive the ready/busy output signal nR/B from the memory device1320through the eighth pin P28. The controller interface circuit1311may determine state information of the memory device1320based on the ready/busy output signal nR/B.

FIG.17is a diagram for explaining a communication operation in the memory system ofFIG.16. Referring toFIG.17, a memory device1320may include a DQ pin DQ_P, a first transmitter1421, and a first receiver1422. The DQ pin DQ_P may correspond to the seventh pin P17ofFIG.16. For example, when the seventh pin P17includes a plurality of pins, the DQ pin DQ_P may correspond to one of the plurality of pins.

The first transmitter1421may generate a data signal DQ based on data DATA and transmit the data signal DQ to a memory controller1310through the DQ pin DQ_P. The first transmitter1421may generate the data signal DQ using an N-level pulse amplitude modulation (e.g., PAM-N) scheme. For example, the first transmitter1421may use one of PAM-4, PAM-8, and PAM-16 schemes.

The first receiver1422may receive the data signal DQ from the memory controller1310through the DQ pin DQ_P and obtain the command CMD, address ADDR, or data DATA from the data signal DQ. In an embodiment, the first receiver1422may obtain a command CMD, an address ADDR, or data DATA by sampling the received data signal DQ in the PAM-N mode. For example, in the PAM-N mode, the first receiver1422may output a plurality of bits based on the voltage level of the data signal DQ received during a unit interval.

The memory controller1310may include a DQ pin DQ_P′, a second transmitter1411, and a second receiver1412. The DQ pin DQ_P′ may correspond to the DQ pin DQ_P of the memory device1320. When the seventh pin P27ofFIG.16includes a plurality of pins, the DQ pin DQ_P′ may correspond to one of the plurality of pins.

The second transmitter1411may generate a data signal DQ based on the command CMD, address ADDR, and data DATA and transmit the data signal DQ to the memory device1320through the DQ pin DQ_P′. In an embodiment, the second transmitter1411may generate the data signal DQ in the PAM-N scheme based on the command CMD, address ADDR, and data DATA. The second receiver1412may receive the data signal DQ from the memory device1320through the DQ pin DQ_P′ and obtain data DATA from the data signal DQ.

In an embodiment, a modulation method of the data signal DQ may be determined to conform to a predetermined rule. In this case, the modes of the first receiver1422and the second receiver1412for sampling the data signal DQ may be determined based on predetermined rules to correspond to modulation schemes of the first transmitter1421and the second transmitter1411. In other embodiment, the memory controller1310may transmit signaling information about a modulation method of the data signal DQ to the memory device1320. The memory device1320may determine a modulation method of the first transmitter1421and a mode of the first receiver1422based on signaling information received from the memory controller1310. In embodiments, the first receiver1422and the second receiver1412correspond to the receiver130ofFIG.1and may be implemented as time-based receivers.