Reducing leakage noise in directly sampled radio frequency signals

The present disclosure includes a system and method for reducing leakage noise in directly sampled radio frequency signals. In some implementations, a Radio Frequency IDentification (RFID) reader includes an antenna, an Analog-to-Digital Converter (ADC), a synthesizer module, and a Carrier Noise Reduction (CNR) module. The antenna is configured to receive Radio Frequency (RF) signals and pass the RF signals to a receive path. The ADC is configured to directly sample RF signals in the receive path in accordance with a clock signal and generate a digital signal. The synthesizer module is configured to generate the clock signal and a signal used to upconvert a transmitter signal. The clock signal and the upconversion signal are phase locked. The CNR module is configured to reduce leakage noise in the receive path.

TECHNICAL FIELD

This invention relates to detecting radio frequency signals and, more particularly, to reducing leakage noise in directly sampled radio frequency signals.

BACKGROUND

In some cases, an RFID reader operates in a dense reader environment, i.e., an area with many readers sharing fewer channels than the number of readers. Each RFID reader works to scan its interrogation zone for transponders, reading them when they are found. Because the transponder uses radar cross section (RCS) modulation to backscatter information to the readers, the RFID communications link can be very asymmetric. The readers typically transmit around 1 watt, while only about 0.1 milliwatt or less gets reflected back from the transponder. After propagation losses from the transponder to the reader the receive signal power at the reader can be 1 nanowatt for fully passive transponders, and as low as 1 picowatt for battery assisted transponders. At the same time other nearby readers also transmit 1 watt, sometimes on the same channel or nearby channels. Although the transponder backscatter signal is, in some cases, separated from the readers' transmission on a sub-carrier, the problem of filtering out unwanted adjacent reader transmissions is very difficult.

SUMMARY

The present disclosure includes a system and method for reducing leakage noise in directly sampled radio frequency signals. In some implementations, a Radio Frequency IDentification (RFID) reader includes an antenna, an Analog-to-Digital Converter (ADC), a synthesizer module, and a Carrier Noise Reduction (CNR) module. The antenna is configured to receive Radio Frequency (RF) signals and pass the RF signals to a receive path. The ADC is configured to directly sample RF signals in the receive path in accordance with a clock signal and generate a digital signal. The synthesizer module is configured to generate the clock signal and an RF carrier signal used to upconvert the transmitter signal to radio frequencies. The clock signal and the upconversion carrier signal are phase locked. The CNR module is configured to reduce leakage noise in the receive path.

DETAILED DESCRIPTION

FIG. 1is an example RFID reader100for reducing transmitter leakage signal in a directly sampled Radio Frequency (RF) signal in accordance with some implementations in the present invention. For example, the reader100may eliminate, minimize, and/or otherwise reduce transmitter leakage noise using a Carrier Reduction Noise (CNR) section. In some implementations, the reader100phase locks a clock signal for an analog-to-digital converter (ADC) that directly samples RF signals and a transmitter oscillator signal that upconverts the transmission signal to radio frequencies. By phase locking these signals, the reader100can substantially reduce frequency drift that can interfere with directly sampling RF signals in the receive path of the reader. In other words, the frequency in the receive path and the transmission path substantially match, and in some implementations, the reader100can generate substantially linear Direct Coupled (DC) control loops for reducing leakage noise in the receive path.

In general, the leakage signal of concern is interference typically generated from a transmit signal that is added to a receive path. Transmitter leakage into the receive path can be as much as 110 dB above the desired backscattered receive signal. Such a high leakage signal to receive signal ratio can leave the received baseband signals susceptible to typical nonlinearities associated with standard cost-effective analog signal processing components. In the case that a reader has perfect transmitter-to-receiver isolation, only the back-scattered signal from the transponder would make it into the receiver. Leakage associated with the transmit signal frequently generates interference in the receive path and may result from one or more sources such as reflections off other nearby objects in the vicinity, internal circuit reflections caused by non-ideal impedance matching, and/or other sources. In some implementations, the reader100offers approximately 40 dB (4 orders of magnitude) of isolation. In an effort to eliminate, minimize or otherwise reduce the leakage signal, the reader100may generate control signals that adjust an amplitude and/or phase of a portion of the transmission signal to generate a cancellation signal, i.e., a signal that when added to a receive path can reduce leakage signals. During the course of this description, the leakage current is described in rectangular coordinates but may also be described in other coordinate systems, such as polar. In some implementations, the leakage signal may be expressed as a portion of an in-phase signal and a quadrature signal, as discussed in more detail below.

In the illustrated implementation, the reader100includes a carrier-noise-reduction (CNR) module102, a receiver module104, a transmitter module106, and a frequency synthesizer module108. The CNR module102includes any software, hardware, and/or firmware operable to reduce leakage signals in the receive path. For example, the CNR module102may introduce signals into the receive path for canceling, minimizing, or otherwise reducing leakage signals. In the illustrated implementation, the CNR module102includes a directional coupler110, a vector modulator112, a power combiner or summer114, and a dual digital-to-analog converter (DAC)116. The directional coupler110splits or otherwise directs a portion of the transmit signal to the vector modulator112. In some implementations, the output of the power amplifier146can be represented by x(t) as:
x(t)=Acos(2πFct),
where A is the signal amplitude and Fcis the RF carrier frequency.

The coupled portion of the transmit signal may be expressed as:
u(t)=b1*Acos(2πFct+θ),
where b1is a fixed small constant (e.g., b1=0.2), θ is a fixed phase shift of the carrier through the coupler, and u(t) is the output of the directional coupler110directed to the vector modulator112.

Another representation of the RF output from the directional coupler110and input to the vector modulator is as follows:
u(t)=B(t)cos(2πFct+φ(t)),
where B(t) and φ(t) are slowly varying stochastic processes and Fcis again the RF carrier frequency.

In addition to receiving a portion of the transmit signal, u(t), the vector modulator112receives an in-phase control signal vi(t) and a quadrature control signal vq(t). In some implementations, the control signals may be polar controls, which may instead control a polar implementation of a vector modulator comprised of a voltage-variable attenuator function with many dB of dynamic range (i.e. greater than 20 dB) and a phase shifter function which may be capable of shifting the phase of the transmit signal over a range of greater than or equal to 360 degrees.

The vector modulator112can modulate the portion of the transmit signal (e.g., u(t)) with the baseband quadrature control signals vi(t) and vq(t) to generate a cancellation signal for the leakage signal. In some implementations, the vector modulator112may comprise a quadrature modulator.

In some implementations, the vector modulator112may produce the cancellation signal z(t) winch can be represented as:
z(t)=b2B(t(vi(t)cos(2πFct+φ(t))+vq(t)sin(2πFct+φ(t)))
where b2is a fixed small constant (e.g., b2=0.01), vi(j) and vq(t) are the modulation control signals, and B(t) and φ(t) comprise u(t) as explained above.

In some implementations, the constant b2accounts for the combined signal attenuation through the directional coupler (bq) and the vector modulator112. In the example expression for the cancellation signal, z(t), the vector modulator112splits the input u(t) into two signals, one version of which is represented by a cosine term, and the second is a 90 degree shifted version of the first, represented by a sine term, then modulates the control signals vi(t) and vq(t) onto these cosine and sine carriers, respectively, to produce the cancellation signal.

In some implementations, the CNR module102includes the dual DAC116for converting digital control signals to analog control signals and directing the analog control signals to the vector modulator112. In some implementations, the control signals are generated as a sampled data signal and each signal is passed through a digital-to-analog converter (DAC)116to create the analog control signals for the vector modulator112. In other words, the control signals vi(t) and vq(t) can comprise digital signals received by the dual DAC116. In some implementations, the control signals vi(t) and vq(t) may be generated from analog control circuitry.

After generating the cancellation signal, the vector modulator112directs the cancellation signal to the power combiner, or summer114. The summer114adds the cancellation signal to the signal received from the receive antenna, y(t), which includes the leakage signal plus the desired signal r(t). In the example, the summer114adds the vector modulator output signal z(t) to the receiver input y(t) to produce s(t), the output of the summer114. In this case, z(t) is substantially equal in amplitude and 180 degrees out of phase with the leakage signal to be cancelled. Those skilled in the art shall recognize that other power-combining implementations are possible which introduce non-equal phase shift and/or non-equal amplitude change to each of the two inputs, such as a 90-degree hybrid or a directional coupler. In these cases, the vector modulator output signal z(t) may be compensated by the inverse of this phase and/or amplitude difference such that when z(t) is combined with y(t), the transmitted leakage signal is substantially reduced or removed.

In some implementations, the residual signal s(t) substantially equals the desired receive signal r(t), i.e., substantially all of the transmitter leakage is cancelled. The residual signal s(t) exiting the CNR module102and entering the receiver104can be represented as:
s(t)=b2B(t)(c(t)·cos(2πFct+φ(t)+(t))+vi(t)cos(2πFct+φ(t))+vq(t)sin(2πFct+φ(t)))+r(t).

The receiver module104can include any software, hardware, and/or firmware operable to down convert the received signal to baseband signals for processing by the Digital Signal Processor (DSP)120. For example, the receiver module104may convert an RF signal to a baseband signal. In some implementations, the baseband signal is a low frequency signal (e.g., DC to 400 KHz). In addition, the receiver module104may perform other functions such as amplification, filtering, conversion between analog and digital signals, and/or others. The receiver module104may produce the baseband signals using a mixer and low pass filters. In the illustrated implementations, the receiver module104includes a bandpass filter (BPF)122and a low noise amplifier (LNA)124, an ADC126, a mixer128and a digital frequency synthesizer (DFS)130. The analog BPF122receives RF signals from the summer114and passes a band of the received RF signals to the LNA124while substantially rejecting frequencies out of band. The LNA124amplifies the residual signal in light of the relative weakness of the signal to the transmission signal. The ADC126converts the analog signal to a digital signal and, in this implementation, directly samples the RF signal in the receive path, in some implementations, the ADC126has sampling rates greater than or equal to 60 MHz (e.g., 244 MHz), which can reduce the required selectivity, shape factor and/or complexity of the analog BPF122. As discussed above, the ADC126receives a clock signal phase-locked with the transmitter oscillator signal (discussed in more detail below). The ADC126passes the digital signal to the mixer128. The mixer128mixes the digital signal with a signal received from a digital frequency synthesizer130to generate two component signals. In the illustrated implementation, the mixer128generates an in-phase signal and a quadrature signal. In other words, the mixer128mixes down the digital signal to baseband.

The frequency synthesizer module108(or more simply, synthesizer module) can include any software, hardware, and/or firmware operable to phase lock the ADC clock signal and the transmitter oscillator signal. In other words, the synthesizer module108passes a clock signal to the ADC126and a signal to the transmitter module106that are substantially phase-coherent. In some implementations, the synthesizer module108can eliminate, minimize, or otherwise reduce frequency drift between the receive path and the transmitter path by locking both the clock signal and the transmitter's oscillator signal to a highly-stable reference frequency signal source, such as a temperature-compensated crystal oscillator (TCXO), and thus, by a form of the transitive property, to each other. As mentioned above, the phase lock can, in some implementations, enable the generation of linear DC control loops for reducing transmitter leakage noise in the receive path. In the illustrated implementation, the synthesizer module108includes a temperature compensated crystal oscillator (TCXO)132, a 2 channel Phase-Locked Loop (PLL) synthesizer circuit134, a voltage controlled crystal oscillator (VCXO)136, and a voltage controlled oscillator (VCO)138. In some implementations, the TCXO132generates a substantially stable (e.g., within ±5 to ±10 parts-per-million (ppm) accuracy, or better) reference frequency signal and passes the signal to the 2 channel PLL synthesizer134.

The 2 channel PLL synthesizer134receives the oscillating signal from the TCXO132and in some implementations divides the frequency of the received signal, by an integer (e.g., 3 or larger) to create a lower comparison frequency for phase-locking the VCXO136using the Intermediate Frequency (IF) PLL channel of the 2 channel PLL synthesizer134. The synthesizer134also receives a fed-back portion of the VCXO136output signal into its IF channel input, which it frequency-divides down with a separate divisor, also generally an integer, to yield a signal at the same comparison frequency resulting from division of the TCXO132output signal described above. For example:

Fcomp,IF=FTCXORIF=FVCXONIF,
where RIFis the divisor for the reference (TCXO) frequency, NIFis the divisor for the Intermediate Frequency (IF), and FTCXOand FVCXO. are the frequencies of the TCXO132and VCXO136, respectively.

The two signals, both at approximately Fcomp,IFare input to a phase detector, the output of which is proportional to the phase difference between the two signals. The phase detector's output is then filtered and is used to control the VCXO's136frequency and phase such that the VCXO's136output signal is phase-locked to the TCXO's132output signal.

Similarly, the RF channel of the 2-channel PLL synthesizer may divide the TCXO132frequency by an integer RRFto generate a comparison frequency, Fcomp,RF, for phase-locking the RF PLL which includes the VCO138. The RF channel of the PLL synthesizer134also frequency-divides a fed-back portion of the VCO128output signal by a fourth divisor, NRF, to the same comparison frequency. NRFcan be an integer, but in some implementations may be a fractional number (such as 1830/5, for example):

These two signals at Fcomp,RFare input to a phase detector, the output of which varies proportionally to the phase difference between its input signals. The phase detector's output is then filtered, and is used to control the frequency and phase of the VCO138, thus phase-locking the VCO138to the signal received from the TCXO132.

In some implementations, the VCXO136generates an ADC clock signal based, at least in part, on the signal derived in the IF PLL channel of the 2 channel PLL synthesizer134and the VCO138generates the transmitter oscillator signal based, at least in part, on the signal derived in the RF PLL channel of the 2 channel PLL synthesizer134.

The receiver module104passes or otherwise directs the baseband signals to the digital signal processor (DSP)120. The DSP120can include any software, hardware, and/or firmware operable to process the filtered, amplified, sampled, and down-converted residual signal, s(t). For example, the DSP120may generate control signals for adjusting the cancellation signal used to compensate for leakage signal. In some implementations, the DSP120compensates the baseband signals for DC offset and/or phase offset. For example, the reader100may include elements that subtract DC offsets and/or de-rotate phase offsets in the baseband signals. Otherwise, these offsets can reduce the efficacy of the cancellation signal in reducing the leakage signal. In other words, the DSP120may eliminate, minimize, or otherwise reduce the DC offset and/or the phase offset to reduce error in the cancellation signal. In the case of DC offset, the DSP120can, in some implementations, subtract estimates of the DC offsets in the baseband signals such as the in-phase signal and the quadrature signal. For example, the DSP120may determine samples (e.g., hundreds of samples) of the DC offset for the baseband signals and generate an average for each baseband signal based, at least in part, on the samples. In this example, the DSP120may subtract the DC offset from the corresponding baseband signal during steady state. In regards to the phase offset, the DSP120may introduce a phase shift in the baseband, signals to minimize, eliminate, or otherwise reduce the phase shift generated by the elements in the reader100. In some cases, varying a control value on one baseband signal (e.g., in-phase signal) can produce a change on the other baseband signal (e.g., quadrature signal). This cross-coupling between the two baseband signals can, in some implementations, lead to a more complex control algorithm for compensating for the phase shift offset. In some implementations, the DSP120may apply some gain or attenuation to baseband residual signal after the DC/phase offset compensation has been done, then integrate the compensated baseband signal to estimate the CNR control signals vi(t) and vq(t). The control signals are passed to the DAC116.

The transmitter module106can include any software, hardware, and/or firmware operable to generate transmission signals for transponders. In the illustrated implementation, the transmitter module106includes a DAC140, a LPF142, a transmission mixer144and a power amplifier146. The DAC140receives a digital signal from the DSP120and converts the digital signal to analog signals. For example, the digital signal can encode queries for transponders to identify associated information. The DAC140passes the analog signal to the LPF142to attenuate higher frequencies than a cutoff frequency from the analog signals. The LPF142passes the analog signals to the transmission mixer144to upconvert the baseband signals to RF signals. In this case, the transmission mixer144receives a signal from the VCO138and mixes this signal with the analog signal to generate the RF signal. The power amplifier146amplifies the RF signal and directs the amplified signal to the power splitter110.

FIG. 2illustrates an example implementation of the DFS130ofFIG. 1in accordance with some implementations of the present disclosure. As discussed above, the DFS130generates a waveform for downconverting the in-phase component and quadrature component to baseband. In the illustrated implementation, the DFS130includes a phase accumulator202and a sine/cosine lookup table204. The phase accumulator202can include any software, hardware, and/or firmware configured to generate an output used to select waveforms from the sine/cosine lookup table204. For example, the phase accumulator202can, in some implementation, operate as a counter that increments a value based, at least in part, on a phase increment shown as the Channel Select input inFIG. 2. In the illustrated implementation, the phase accumulator202includes a summer206, modulo L phase wrapping logic208, and an accumulation register208. The summer206adds a stored accumulation value to an input value identifying a specific channel. The summer206passes the value to the modulo L phase wrapping logic208, which performs modulo L wrapping logic of the summer output between 0 and L-1. The accumulation register208stores the value until the next sample clock period. The accumulated value is passed to the sine/cosine lookup table204to map the value to a waveform. For example, the lookup table204identifies the accumulated value and maps the value to one or more waveform samples Identified in the table204. The sine/cosine lookup table204passes the two signals to the mixer128for downconversion to baseband.

In some implementations, the DFS130can be clocked at the sampling frequency Fs. In this implementation, the output of the accumulator202can be used as an index into the sine/cosine table L samples long. In some cases, the minimum frequency resolution can be expressed as follows:

Δ⁢⁢f=FsL,
which can be selected as the channel spacing (e.g., 25 KHz frequency resolution). Using this expression, L is as follows:

L=FsΔ⁢⁢f.
In the case that, the sampling frequency Fsis an integer multiple of the channel spacing Δf, the phase increment is an integer. As a result, the output frequency, in some implementations, can be represented exactly, which can lead to no distortion due to phase truncation. In some implementations, the output signals can include distortion due to amplitude quantization. In some implementations, a 16 bit table204can yield SNR of 96 dB and SFDR>110 dB.

FIG. 3is a flowchart illustrating example methods300for generating phase-locked ADC clock signal and transmitter oscillator signal in accordance with some implementations of the present disclosure. Generally, method300describes an example technique where an initial oscillating signal is divided down to produce two signals used to drive oscillators for the receiver and the transmitter. System100contemplates using any appropriate combination and arrangement of logical elements implementing some or all of the described functionality.

Method300begins at step302where a signal oscillating at a specific frequency is generated. For example, the TCXO132can generate an oscillating signal within 10 parts per million (ppm) of frequency accuracy. Next, at step304, the frequency of the oscillating signal is divided. As for the example, the 2 channel frequency synthesizer134divides the frequency of the oscillating signal by an integer. Two phase-locked signals are generated using fee divided frequency at step306. Again in the example, the 2 channel PLL synthesizer134generates a first component to adjust the frequency and phase of the VCXO136and a second component to adjust the frequency and phase of the VCO138, so as to phase-lock both the VCXO136and VCO138to the TCXO132, achieving for the entire system the relative frequency accuracy of the TCXO132and phase coherence. At step308, an ADC clock signal is generated based, at least in part, on one of the phase locked signals. Returning to the example, the VCXO136generates an ADC clock signal based, at least in part, on the phase locked control signal received from the RF PLL channel of the 2 channel PLL synthesizer134. Next, at step310, a transmitter oscillator signal is generated based, at least in part, on the other phase lock control signal. As for the example, the VCO138generates a transmitter oscillator signal based, at least in part, on the phase locked control signal received from the RF PLL channel of the 2 channel PLL synthesizer134.