SEMICONDUCTOR PACKAGE

A semiconductor package includes a first lower redistribution layer, a first upper redistribution layer over the first lower redistribution layer, a first semiconductor chip between the first lower redistribution layer and the first upper redistribution layer, a first connection post spaced apart from the first semiconductor chip and connecting the first lower redistribution layer to the first upper redistribution layer, a first interposition layer on the first upper redistribution layer, a second interposition layer on the first interposition layer, a second lower redistribution layer on the second interposition layer, a second upper redistribution layer over the second lower redistribution layer, a second semiconductor chip between the second lower redistribution layer and the second upper redistribution layer, and a second connection post spaced apart from each other and connecting the second lower redistribution layer to the second upper redistribution layer.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. nonprovisional application claims priority under 35 U.S.C § 119 to Korean Patent Application No. 10-2022-0084484 filed on Jul. 8, 2022 in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND

The present disclosure relates to a semiconductor package, and more particularly, to a semiconductor package including a connection post and an interposition layer.

In response to the rapid development of the electronic industry and user demands, electronic products have become smaller and increasingly multifunctional. There are also increased needs for miniaturization and multi-functionality of semiconductor devices used for electronic products.

Recently, packages have been developed in which semiconductor chips are stacked to increase storage capacity and data process speeds. Such packages are required to densely stack the semiconductor chips.

SUMMARY

It is an aspect to provide a semiconductor package with increased reliability and improved electrical properties.

According to an aspect of some embodiments, a semiconductor package may comprise: a first lower redistribution layer; a first upper redistribution layer over the first lower redistribution layer; a first semiconductor chip between the first lower redistribution layer and the first upper redistribution layer; a first connection post spaced apart from the first semiconductor chip and connecting the first lower redistribution layer to the first upper redistribution layer; a first interposition layer on the first upper redistribution layer; a second interposition layer on the first interposition layer; a second lower redistribution layer on the second interposition layer; a second upper redistribution layer over the second lower redistribution layer; a second semiconductor chip between the second lower redistribution layer and the second upper redistribution layer; and a second connection post spaced apart from each other and connecting the second lower redistribution layer to the second upper redistribution layer.

According to another aspect of some embodiments, a semiconductor package may comprise: a first lower redistribution layer; a first upper redistribution layer on the first lower redistribution layer; a first semiconductor chip between the first lower redistribution layer and the first upper redistribution layer; a first interposition layer on the first upper redistribution layer; a second interposition layer on the first interposition layer; a second lower redistribution layer on the second interposition layer; a second upper redistribution layer on the second lower redistribution layer; and a second semiconductor chip between the second lower redistribution layer and the second upper redistribution layer. Each of the first lower redistribution layer, the first upper redistribution layer, the second lower redistribution layer, and the second upper redistribution layer may include a redistribution pattern and a redistribution dielectric layer that surrounds the redistribution pattern. The redistribution dielectric layer may include a photosensitive dielectric material.

According to yet another aspect of some embodiments, a semiconductor package may comprise: a solder ball; a first lower redistribution layer on the solder ball; a first die attach film on the first lower redistribution layer; a first semiconductor chip on the first die attach film; a first molding layer on the first semiconductor chip; a first upper redistribution layer on the first molding layer; a first connection post that connects the first lower redistribution layer to the first upper redistribution layer; a first chip post that connects the first semiconductor chip to the first upper redistribution layer; a first interposition layer on the first upper redistribution layer; a second interposition layer on the first interposition layer; a second lower redistribution layer on the second interposition layer; a second molding layer on the second lower redistribution layer; a second semiconductor chip on the second molding layer; a second die attach film on the second semiconductor chip; a second upper redistribution layer on the second die attach film; a second connection post that connects the second lower redistribution layer to the second upper redistribution layer; and a second chip post that connects the second semiconductor chip to the second lower redistribution layer. The first connection post may vertically overlap the second semiconductor chip. The second connection post may vertically overlap the first semiconductor chip.

DETAILED DESCRIPTION

The following will describe in detail a semiconductor package according to the present inventive concepts with reference to the accompanying drawings.

FIG.1Aillustrates a cross-sectional view showing a semiconductor package according to some embodiments.FIG.1Billustrates an enlarged view showing section A ofFIG.1A.FIG.1Cillustrates a top view showing the semiconductor package depicted inFIG.1A.

Referring toFIGS.1A,1B, and1C, a semiconductor package may include a solder dielectric layer IL, solder balls SB, an under-bump metal (UBM)11on the solder ball SB, a first semiconductor structure100on the under-bump metal11, and a second semiconductor structure200on the first semiconductor structure100. The solder ball SB and the under-bump metal11may include a conductive material.

The first semiconductor structure100may include a first lower redistribution layer LRD1, a first die attach film (DAF)122, a first semiconductor chip110, a first connection post121, a first chip post123, a first molding layer130, a first upper redistribution layer URD1, and a first interposition layer IP1. The solder ball SB may be electrically connected to the first lower redistribution layer LRD1. The solder dielectric layer IL may surround a portion of the under-bump metal11.

The first lower redistribution layer LRD1may be positioned on the under-bump metal11. The first lower redistribution layer LRD1may have a plate shape that extends along a plane elongated in a first direction D1and a second direction D2. The first and second directions D1and D2may intersect each other. For example, the first and second directions D1and D2may be horizontal directions that are orthogonal to each other. The first lower redistribution layer LRD1may include a redistribution pattern103and a redistribution dielectric layer101that surrounds the redistribution pattern103. The first lower redistribution layer LRD1may be connected to the first attach film122used to attach the first semiconductor chip110to the first lower redistribution layer LRD1. The first lower redistribution layer LRD1may be electrically connected through the redistribution pattern103to the first connection post121. The redistribution dielectric layer101may include a photosensitive dielectric material. The photosensitive dielectric material may include a polymer resin material, for example, at least one of a photo-imageable dielectric (PID) or a photo-acrylic. The redistribution pattern103may include an upper portion and a lower portion. The upper and lower portions of the redistribution pattern103may have different widths from each other. The upper and lower portions of the redistribution pattern103may be connected to have a single unitary structure with no boundary therebetween. The redistribution pattern103may include a conductive material.

The first die attach film122may be provided to fix the first semiconductor chip110to the first lower redistribution layer LRD1. The first die attach film122may be disposed on the first lower redistribution layer LRD1. The first die attach film122may be positioned between the first semiconductor chip110and the first lower redistribution layer LRD1. The first die attach film122may be in contact with a bottom surface of the first semiconductor chip110and a top surface of the first lower redistribution layer LRD1. In an embodiment, the first die attach film122may include at least one of an epoxy resin or a rubber resin.

The first semiconductor chip110may be positioned between the first lower redistribution layer LRD1and the first upper redistribution layer URD1. The first semiconductor chip110may include an active layer113and a passivation layer114on the active layer113. The active layer113may include silicon. The passivation layer114may include a chip conductive structure116. In an embodiment, the chip conductive structure116may include a conductive material. The chip conductive structure116may include, for example, a conductive contact, a conductive line, or a conductive pad. In an embodiment, the first semiconductor chip110may include a plurality of first semiconductor chips.

The first chip post123may be positioned on the passivation layer114. The first chip post123may be disposed between the first semiconductor chip110and the first upper redistribution layer URD1. The first chip post123may connect the first upper redistribution layer URD1to the first semiconductor chip110. The first chip post123may include a metal, for example, copper. The first chip post123may have a width greater than that of the chip conductive structure116. In an embodiment, the first semiconductor chip110may include a plurality of first semiconductor chips110and the first chip post123may include a plurality of first chip posts123, and the first chip posts123may be provided on corresponding first semiconductor chips110. In an embodiment, a plurality of first chip posts123may be provided on a single first semiconductor chip110.

The first connection post121may be provided on the first lower redistribution layer LRD1. The first connection post121may be positioned spaced apart from the first semiconductor chip110. The first connection post121may be provided between the first lower redistribution layer LRD1and the first upper redistribution layer URD1. The first connection post121may electrically connect the first lower redistribution layer LRD1to the first upper redistribution layer URD1. In an embodiment, the first connection post121may include metal such as copper. In an embodiment, the first connection post121may include a plurality of first connection posts.

The first molding layer130may be provided on the first lower redistribution layer LRD1. The first molding layer130may be provided on the first semiconductor chip110. The first molding layer130may surround the first die attach film122, the first semiconductor chip110, the first chip post123, and the first connection post121. In an embodiment, the first molding layer130may include at least one of an epoxy resin or a phenolic resin.

The first upper redistribution layer URD1may be provided on the first lower redistribution layer LRD1. The first upper redistribution layer URD1may be provided on the first molding layer130. The first upper redistribution layer URD1may include a redistribution pattern104and a redistribution dielectric layer102that surrounds the redistribution pattern104. The first upper redistribution layer URD1may be provided on the first semiconductor chip110. The first upper redistribution layer URD1may be electrically connected through the redistribution pattern104to the first chip post123. The redistribution dielectric layer102may include a photosensitive dielectric material. The first lower redistribution layer LRD1and the first upper redistribution layer URD1may be connected to the first connection post121. The redistribution pattern104may include an upper portion and a lower portion. The upper and lower portions of the redistribution pattern104may have different widths from each other. The upper and lower portions of the redistribution pattern104may be connected to have a single unitary structure with no boundary therebetween.

The second semiconductor structure200may be disposed on the first semiconductor structure100. The second semiconductor structure200may include a second interposition layer IP2, a second lower redistribution layer LRD2, a second semiconductor chip210, a second die attach film222, a second connection post221, a second chip post223, a second molding layer230, and a second upper redistribution layer URD2.

The second interposition layer IP2may be provided on the first interposition layer IP1. The second interposition layer IP2may include a conductive structure206and an interposition dielectric layer205that surrounds the conductive structure206. The conductive structure206of the second interposition layer IP2may include a conductive contact, a conductive line, or a conductive pad. In an embodiment, the conductive structure206of the second interposition layer IP2may include a lower conductive structure and an upper conductive structure that are connected to each other.

In an embodiment, the interposition dielectric layers105and205may be inorganic dielectric layers. In an embodiment, the interposition dielectric layers105and205may include, for example, SiO2, Si3N4, or Al2O3. In an embodiment, the conductive structures106and206may include at least one of copper, tungsten, tantalum, titanium, or aluminum.

The first semiconductor structure100and the second semiconductor structure200may be physically connected through the first interposition layer IP1and the second interposition layer IP2. The first semiconductor structure100and the second semiconductor structure200may be electrically connected through the conductive structure106of the first interposition layer IP1and the conductive structure206of the second interposition layer IP2. In an embodiment, the first semiconductor structure100and the second semiconductor structure200may be connected due to metal-metal diffusion between the conductive structure106of the first interposition layer IP1and the conductive structure206of the second interposition layer IP2.

The second lower redistribution layer LRD2may be provided on the second interposition layer IP2. The second lower redistribution layer LRD2may have a plate shape that extends along a plane elongated in the first direction D1and the second direction D2. The second lower redistribution layer LRD2may include a redistribution pattern203and a redistribution dielectric layer201that surrounds the redistribution pattern203.

The second lower redistribution layer LRD2may be connected to the second chip post223. The second lower redistribution layer LRD2may be electrically connected through the redistribution pattern203to the second connection post221. The redistribution dielectric layer201may include a photosensitive dielectric material. The redistribution pattern203may include an upper portion and a lower portion. The upper and lower portions of the redistribution pattern203may have different widths from each other. The upper and lower portions of the redistribution pattern203may be connected to have a single unitary structure with no boundary therebetween.

The second die attach film222may be provided to fix the second semiconductor chip210to the second upper redistribution layer URD2. The second die attach film222may be positioned between the second semiconductor chip210and the second upper redistribution layer URD2. The second die attach film222may be in contact with a top surface of the second semiconductor chip210and a bottom surface of the second upper redistribution layer URD2. In an embodiment, the second die attach film222may include at least one of an epoxy resin or a rubber resin. In an embodiment, the second die attach film222may be provided to fix the second semiconductor chip210to the second lower redistribution layer LRD2. In this case, the second die attach film222may be positioned between the second semiconductor chip210and the second lower redistribution layer LRD2, and may be in contact with a bottom surface of the second semiconductor chip210and a top surface of the second lower redistribution layer LRD2.

The second semiconductor chip210may be positioned between the second lower redistribution layer LRD2and the second upper redistribution layer URD2. The second semiconductor chip210may include an active layer213and a passivation layer214on the active layer213. The active layer213may include silicon. The passivation layer214may include a chip conductive structure216. In an embodiment, the chip conductive structure216may include a conductive material. In an embodiment, the chip conductive structure216may include a conductive contact, a conductive line, or a conductive pad. In an embodiment, the second semiconductor chip210may include a plurality of second semiconductor chips.

The second chip post223may be positioned on the second lower redistribution layer LRD2. The second chip post223may include a metal, for example, copper. The second chip post223may have a width greater than that of the chip conductive structure216. The second semiconductor chip210may include a plurality of second semiconductor chips210and the second chip post223may include a plurality of second chip posts223. In an embodiment, the second chip posts223may be provided on corresponding redistribution patterns203of the second lower redistribution layer LRD2. In an embodiment, the second chip posts223may be correspondingly in contact with the chip conductive structures216of the second semiconductor chips210.

In an embodiment, the second chip post223may be disposed between the second semiconductor chip210and the second upper redistribution layer URD2. In an embodiment, the second chip post223may connect the second upper redistribution layer URD2to the second semiconductor chip210.

The second connection post221may be provided on the second lower redistribution layer LRD2. The second connection post221may be positioned spaced apart from the second semiconductor chip210. The second connection post221may be provided between the second lower redistribution layer LRD2and the second upper redistribution layer URD2. The second connection post221may electrically connect the second lower redistribution layer LRD2to the second upper redistribution layer URD2. In an embodiment, the second connection post221may include a metal such as copper. In an embodiment, the second connection post221may include a plurality of second connection posts.

The second molding layer230may be provided on the second lower redistribution layer LRD2. In an embodiment, the second semiconductor chip210may be provided on the second molding layer230. In an embodiment, the second molding layer230may be provided on the second semiconductor chip210. The second molding layer230may surround the second die attach film222, the second semiconductor chip210, the second chip post223, and the second connection post221. In an embodiment, the second molding layer230may include at least one of an epoxy resin or a phenolic resin.

The second upper redistribution layer URD2may be provided on the second lower redistribution layer LRD2. The second upper redistribution layer URD2may be provided on the second molding layer230. The second upper redistribution layer URD2may include a redistribution pattern204and a redistribution dielectric layer202that surrounds the redistribution pattern204. The second upper redistribution layer URD2may be provided on the second semiconductor chip210. The redistribution dielectric layer202may include a photosensitive dielectric material. The second lower redistribution layer LRD2and the second upper redistribution layer URD2may be connected to the second connection post221. In an embodiment, the second upper redistribution layer URD2may be configured such that the redistribution dielectric layer202may cover the redistribution pattern204so as not to expose the redistribution pattern204. The redistribution pattern204may include an upper portion and a lower portion. The upper and lower portions of the redistribution pattern204may have different widths from each other. The upper and lower portions of the redistribution pattern204may be connected to have a single unitary structure with no boundary therebetween.

In an embodiment, the first connection post121may overlap in the third direction D3with the second semiconductor chip210, and the second connection post221may overlap in the third direction D3with the first semiconductor chip110.

In an embodiment, two first semiconductor chips110may be disposed between two first connection posts121, and two second connection posts221may be disposed between two second semiconductor chips210. In an embodiment, an interval between the first connection posts121may range from about 0.001 mm to about 1 mm. In an embodiment, an interval between the first semiconductor chips110may range from about 0.001 mm to about 1 mm. In an embodiment, a value of 0.001 mm to about 1 mm may be given to an interval between the first connection post121and its adjacent first semiconductor chip110. In an embodiment, a value of about 0.001 mm to about 1 mm may be given to an interval between the first semiconductor chip110and the first upper redistribution layer URD1.

The semiconductor package according to some embodiments may include a memory semiconductor chip and a logic semiconductor chip. The logic semiconductor chip may be disposed in the first semiconductor structure100or the second semiconductor structure200. As the position of the logic semiconductor chip is changed, the semiconductor package may become optimized in terms of electrical connection distance.

In the semiconductor package according to some embodiments, the first connection post121may overlap the second semiconductor chip210, and the second connection post221may overlap the first semiconductor chip110. Accordingly, the semiconductor package may have a relatively large stacking density.

FIGS.2A,2B,2C,2D,2E, and2Fillustrate cross-sectional views showing a method of fabricating the semiconductor package depicted inFIGS.1A to1C, according to some embodiments.

Referring toFIG.2A, a first glue layer13may be provided on a first substrate12. A first lower redistribution layer LRD1may be formed on the first glue layer13. The first lower redistribution layer LRD1may include a redistribution dielectric layer101and a redistribution pattern103. The redistribution pattern103may be formed in the redistribution dielectric layer101. In an embodiment, the redistribution pattern103may be formed by etching lower and upper portions having different widths from each other, and then performing a plating process.

A first connection post121may be formed on the first lower redistribution layer LRD1. In an embodiment, the first connection post121may be formed by a photolithography process and a plating process. The first connection post121may be formed to electrically connect to the redistribution pattern103. In an embodiment, a plurality of first connection posts121may be formed on the first lower redistribution layer LRD1.

Referring toFIG.2B, a first semiconductor chip110may be formed, and a first die attach film122and a first chip post123may be formed to connect to the first semiconductor chip110. The first semiconductor chip110connected to the first chip post123may be disposed on the first lower redistribution layer LRD1. The first semiconductor chip110may be disposed spaced apart from the first connection post121.

Referring toFIG.2C, a first molding layer130may be formed on the first lower redistribution layer LRD1. The first molding layer130may surround the first connection post121, the first semiconductor chip110, the first die attach film122, and the first chip post123. The formation of the first molding layer130may include forming a molding material layer that covers the first connection post121, the first semiconductor chip110, the first die attach film122, and the first chip post123, and performing a grinding process to expose the first connection post121and the first chip post123.

Referring toFIG.2D, a first upper redistribution layer URD1may be formed in the first molding layer130. The first upper redistribution layer URD1may include a redistribution dielectric layer102and a redistribution pattern104. The redistribution pattern104may be formed in the redistribution dielectric layer102. In an embodiment, the redistribution pattern104may be formed by etching its lower and upper portions having different widths from each other, and then performing a plating process. The redistribution pattern104may be electrically connected to the first connection post121. The redistribution pattern104may be electrically connected to the first chip post123.

A first interposition layer IP1may be formed on the first upper redistribution layer URD1. The first interposition layer IP1may include an interposition dielectric layer105and conductive structures106. The interposition dielectric layer105may surround the conductive structures106. A first semiconductor structure may be formed to include the first lower redistribution layer LRD1, the first connection post121, the first semiconductor chip110, the first chip post123, the first upper redistribution layer URD1, and the first interposition layer IP1.

Referring toFIG.2E, similar to the formation of the first semiconductor structure100, a second semiconductor structure200may be formed on a second substrate14and a second glue layer15. The second semiconductor structure200may include a second lower redistribution layer LRD2, a second connection post221, a second chip post223, a second semiconductor chip210, a second upper redistribution layer URD2, and a second interposition layer IP2.

The second semiconductor structure200may be bonded to the first semiconductor structure100. The first interposition layer IP1of the first semiconductor structure100may be bonded to the second interposition layer IP2of the second semiconductor structure200. The conductive structure106of the first interposition layer IP1may be bonded to a conductive structure206of the second interposition layer IP2. In an embodiment, an annealing process may be performed after the bonding between the conductive structure106of the first interposition layer IP1and the conductive structure206of the second interposition layer IP2.

In an embodiment, the second semiconductor structure200and the first semiconductor structure100may be bonded to cause the first connection post121to overlap in a third direction D3with the second semiconductor chip210and the second connection post221to overlap in the third direction D3with the first semiconductor chip110.

Referring toFIG.2F, the first substrate12and the first glue layer13may be removed, and the second substrate14and the second glue layer15may be removed.

Referring toFIG.1A, a solder ball SB and an under-bump metal (UBM)11may be formed to connect to the first lower redistribution layer LRD1of the first semiconductor structure100. In an embodiment, a redistribution dielectric layer202may be additionally coated on the second upper redistribution layer URD so as not to expose a redistribution pattern204.

FIG.3illustrates a cross-sectional view showing a semiconductor package according to some embodiments.

Referring toFIG.3, a semiconductor package may include a solder ball SBa, an under-bump metal (UBM)11a, a first semiconductor structure100aon the under-bump metal11a, a second semiconductor structure200aon the first semiconductor structure100a, and a third semiconductor structure300aon the second semiconductor structure200a.

Similar to the first semiconductor structure100ofFIG.1A, the first semiconductor structure100amay include a first lower redistribution layer LRD1a, a first upper redistribution layer URD1aon the first lower redistribution layer LRD1a, a first semiconductor chip110abetween the first lower redistribution layer LRD1aand the first upper redistribution layer URD1a, and a first interposition layer IP1aon the first upper redistribution layer URD1a.

The second semiconductor structure200amay include a second interposition layer IP2aon the first interposition layer IP1a, a second lower redistribution layer LRD2aon the second interposition layer IP2a, a second upper redistribution layer URD2aon the second lower redistribution layer LRD2a, a second semiconductor chip210abetween the second lower redistribution layer LRD2aand the second upper redistribution layer URD2a, and a third interposition layer IP3aon the second upper redistribution layer URD2a.

Similar to the second semiconductor structure200ofFIG.1A, the third semiconductor structure300amay include a fourth interposition layer IP4aon the third interposition layer IP3a, a third lower redistribution layer LRD3aon the fourth interposition layer IP4a, a third upper redistribution layer URD3aon the third lower redistribution layer LRD3a, and a third semiconductor chip310abetween the third lower redistribution layer LRD3aand the third upper redistribution layer URD3a.

The first interposition layer IP1aof the first semiconductor structure100amay be bonded to the second interposition layer IP2aof the second semiconductor structure200a. The third interposition layer IP3aof the second semiconductor structure200amay be bonded to the fourth interposition layer IP4aof the third semiconductor structure300a.

FIGS.4A and4Billustrate cross-sectional views showing a method of fabricating the semiconductor package depicted inFIG.3.

Referring toFIG.4A, similar to that discussed with reference toFIGS.2A to2D, a first semiconductor structure100amay be formed. A second glue layer15amay be formed on a second substrate14a, and a second semiconductor structure200amay be formed on the second glue layer15a. In an embodiment, the formation of the second semiconductor structure200amay be followed by the formation of the first semiconductor structure100a.

Referring toFIG.4B, the second semiconductor structure200amay be bonded to the first semiconductor structure100a. Afterwards, the second substrate14aand the second glue layer15amay be removed.

Similar to that discussed with reference toFIGS.2A to2D, a third semiconductor structure300amay be formed on a third substrate16aand a third glue layer17a. Thereafter, the third semiconductor structure300amay be bonded to the second semiconductor structure200a.

Referring toFIG.3, the first and third substrates12aand16amay be removed, and the first and third glue layers13aand17amay also be removed. A solder ball SBa and an under-bump metal (UBM)11amay be formed to connect to the first lower redistribution layer LRD1aof the first semiconductor structure100a. In an embodiment, a redistribution dielectric layer may additionally be coated not to expose a redistribution pattern on a third upper redistribution layer URD3a. In an embodiment, a sawing process may be performed to obtain a semiconductor package that is separated to have a desired size.

FIG.5Aillustrates a conceptual view showing a wafer stacking process according to some embodiments.

Referring toFIG.5A, a first wafer WF1and a second wafer WF2may be provided. The second wafer WF2and the first wafer WF1may be computationally paired with each other. The first wafer WF1and the second wafer WF2may be bonded by a wafer-to-wafer process. The first wafer WF1and the second wafer WF2may be stacked by a wafer-to-wafer process. The first wafer WF1may be first fabricated. A normally operated semiconductor chip502may be mounted on the first wafer WF1. The first wafer WF1may include a reject position501. As used here, “normally operated” denotes a semiconductor chip502that does not have sufficient defects to prevent operation of the semiconductor chip502for the intended operation of the semiconductor chip502.

The fabrication of the first wafer WF1may be followed by the fabrication of the second wafer WF2. A normally operated semiconductor chip512may be mounted on the second wafer WF2. The second wafer WF2may include a non-mount position511on which no semiconductor chip is mounted. When stacking the first and second wafers WF1and WF2, the semiconductor chip512on the second wafer WF2may be mounted on a location on the second wafer WF2, which location corresponds to a position of the semiconductor chip502on the first wafer WF1. When stacking the first and second wafers WF1and WF2, the non-mount position511of the second wafer WF2may be a location on the second wafer WF2, which location corresponds to the reject position501of the first wafer WF1.

The reject position501of the first wafer WF1may be placed on the non-mount position511of the second wafer WF2, and a location where the semiconductor chip502is mounted on the first wafer WF1is mounted may be placed on a location where the semiconductor chip512is mounted on the second wafer WF2.

The second wafer WF2may be provided thereon with no semiconductor chip on its location that corresponds to the reject position501of the first wafer WF1(or, the second wafer WF2may be provided with the non-mount position511thereon), it may be possible to prevent yield loss and to achieve maximization of production.

FIG.5Billustrates a cross-sectional view showing stacked wafers fabricated by the process depicted inFIG.5A, according to some embodiments.

Referring toFIG.5B, a first wafer WF1aand a second wafer WF2amay be stacked as discussed with respect toFIG.5A. A normally operated semiconductor chip502amay be mounted on the first wafer WF1a. The first wafer WF1amay be provided thereon with a reject position501aon which no semiconductor chip is mounted. A wiring error may cause no semiconductor chip to reside on the reject position501a.

A normally operated semiconductor chip512amay be mounted on the second wafer WF2a. The second wafer WF2may include a non-mount position511aon which no semiconductor chip is mounted.

The first wafer WF1aand the second wafer WF2amay be in contact with each other through an interposition layer IP5bof the first wafer WF1aand an interposition layer IP5aof the second wafer WF2a.

When the first and second wafers WF1aand WF2aare in contact with each other, the reject position501aof the first wafer WF1amay be located on the non-mount position511aof the second wafer WF2a.

When the first and second wafers WF1aand WF2aare in contact with each other, a location where the semiconductor chip502ais mounted on the first wafer WF1amay be placed on a location where the semiconductor chip512ais mounted on the second wafer WF2a.

FIG.5Cillustrates a cross-sectional view showing stacked wafers fabricated by the process depicted inFIG.5A, according to some embodiments.

Referring toFIG.5C, a first wafer WF1band a second wafer WF2bmay be stacked as discussed inFIG.5A. A normally operated semiconductor chip502bmay be mounted on the first wafer WF1b. The first wafer WF1bmay be provided thereon with a reject position on which an abnormally operated semiconductor chip501bis mounted.

A normally operated semiconductor chip512bmay be mounted on the second wafer WF2b. The second wafer WF2bmay include a non-mount position511bon which no semiconductor chip is mounted.

When the first and second wafers WF1band WF2bare in contact with each other, the reject position on which the abnormally operated semiconductor chip501bis mounted on the first wafer WF1bmay be located on the non-mount position511bof the second wafer WF2b.

When the first and second wafers WF1band WF2bare in contact with each other, a location of the semiconductor chip502bon the first wafer WF1bmay be placed on a location where the semiconductor chip512bis mounted on the second wafer WF2b.

FIG.6illustrates a cross-sectional view showing a semiconductor package according to some embodiments.

Referring toFIG.6, a semiconductor package may include a solder ball SBb, an under-bump metal (UBM)11b, a first semiconductor structure100bon the under-bump metal11b, and a second semiconductor structure200bon the first semiconductor structure100b.

One of first connection posts121bmay overlap in the a third direction D3with one of the second connection posts221b, and another of first connection posts121bmay overlap in the third direction D3with a second semiconductor chip210. One of first semiconductor chips110bmay be positioned between adjacent ones of the first connection posts121b. A plurality of second semiconductor chips210bmay be positioned between adjacent ones of the second connection posts221b. The plurality of second semiconductor chips210bmay be positioned adjacent to each other.

FIG.7illustrates a cross-sectional view showing a semiconductor package according to some embodiments.

Referring toFIG.7, a semiconductor package may include a solder ball SBc, an under-bump metal (UBM)11c, a first semiconductor structure100cof the under-bump metal11c, and a second semiconductor structure200con the first semiconductor structure100c.

One of first connection posts121cmay overlap in a third direction D3with one of second semiconductor chips210c, and another of first connection posts121cmay overlap with and electrically connect to a portion of one of second connection post221c. A plurality of first connection posts121cmay be positioned between adjacent ones of first semiconductor chips110c. A plurality of first connection posts121cmay be positioned adjacent to each other. One of the second semiconductor chips210cmay be positioned between adjacent ones of the second connection posts221c.

FIG.8illustrates a cross-sectional view showing a semiconductor package according to some embodiments.

Referring toFIG.8, a semiconductor package may include a solder ball SBd, an under-bump metal (UBM)11d, a first semiconductor structure100don the under-bump metal11d, and a second semiconductor structure200don the first semiconductor structure100d.

A first connection post121dmay overlap in a third direction D3with a second semiconductor chip210d. A plurality of first connection posts121dmay be positioned between adjacent ones of first semiconductor chips110d. A plurality of first connection posts121dmay be positioned adjacent to each other. A plurality of second semiconductor chips210dmay be positioned between adjacent ones of second connection posts221d. A plurality of second semiconductor chips210dmay be positioned adjacent to each other.

FIG.9illustrates a cross-sectional view showing a semiconductor package according to some embodiments.

Referring toFIG.9, a semiconductor package may include a solder ball SBe, an under-bump metal (UBM)11e, a first semiconductor structure100e, and a second semiconductor structure200eon the first semiconductor structure100e.

A first semiconductor chip110emay be positioned between a plurality of first connection posts121e. A plurality of first connection posts121emay be positioned between adjacent ones of the first semiconductor chips110e. One of the plurality of first connection posts121emay overlap in a third direction D3with a second connection post221e. Each of others of the plurality of first connection posts121ebetween the first semiconductor chips110emay overlap in the third direction D3with a second semiconductor chip210e.

The second connection post221emay be positioned between adjacent ones of the second semiconductor chips210e. One of the second connection posts221emay overlap in the third direction D3with the first connection post121e. Each of others of the second connection posts221emay not overlap but may electrically connect to the first connection post121eor the first semiconductor chip110e.

In an embodiment, the first semiconductor chips110emay be memory chips, and the second semiconductor chips210emay be logic chips.

FIG.10illustrates a cross-sectional view showing a semiconductor package according to some embodiments.

Referring toFIG.10, a semiconductor package may include a solder ball SBf, an under-bump metal (UBM)11f, a first semiconductor structure100f, a second semiconductor structure200fon the first semiconductor structure100f, and a third semiconductor structure300fon the second semiconductor structure200f.

Second semiconductor chips210fmay include one or more through vias217f.

The second semiconductor chips210fmay include a passivation layer214fand an active layer215f. In some embodiments, the active layer215fmay be on the passivation layer214f. The through via217fmay penetrate the passivation layer214fand the active layer215f. The second semiconductor chip210fmay separately include no die attach film. The active layer215fof the second semiconductor chip210fmay have an active surface that faces the first semiconductor structure100f.

A first semiconductor chip110fmay be positioned between a plurality of first connection posts121f. A plurality of first connection posts121fmay be positioned between adjacent ones of the first semiconductor chips110f. The first connection posts121fmay overlap in a third direction D3with corresponding second connection posts221f. An active layer115fof the first semiconductor chip110fmay have an active surface that faces the second semiconductor structure200f.

Second connection posts221fmay be positioned between adjacent ones of the second semiconductor chips210f. One of the second connection posts221fbetween the adjacent ones of the second semiconductor chips210fmay overlap in the third direction D3with a third connection post321f. Another of the second connection posts221fbetween the adjacent ones of the second semiconductor chips210fmay overlap a third semiconductor chip310f.

Each of others of the second connection posts221fmay not overlap, but may electrically connect to the third connection post321for the third semiconductor chip310f.

FIG.11illustrates a cross-sectional view showing a semiconductor package according to some embodiments.

Referring toFIG.11, a semiconductor package may include a solder ball SBg, an under-bump metal (UBM)11g, a first semiconductor structure100g, and a second semiconductor structure200gon the first semiconductor structure100g. The first semiconductor structure100gmay include one semiconductor chip110g. The second semiconductor structure200gmay include one semiconductor chip210g.

FIG.12illustrates a cross-sectional view showing a semiconductor package according to some embodiments.

Referring toFIG.12, a semiconductor package may include a package substrate22. The package substrate22may be provided with first terminals21electrically connected thereto. The semiconductor package may be mounted through the first terminals21on an external apparatus (e.g., main board).

An interposer24may be provided on the package substrate22. Second terminals23may be provided to electrically connect the package substrate22and the interposer24to each other. The second terminals23may be provided between the package substrate22and the interposer24.

A processor chip26may be provided on the interposer24. For example, the processor chip26may be a graphic processing unit (GPU) or a central processing unit (CPU). Third terminals25may be provided to electrically connect the processor chip26and the interposer24to each other. The third terminals25may be provided between the processor chip26and the interposer24.

A semiconductor package structure1may be provided on the interposer24. The semiconductor package structure1may be configured identical or similar to the semiconductor package discussed with reference toFIGS.1A to1C. The semiconductor package structure1may be spaced apart in a first direction D1from the processor chip26. Solder balls may be provided to electrically connect the semiconductor package structure1and the interposer24to each other.

The package substrate22may be provided thereon with a molding layer27that surrounds the interposer24, the processor chip26, and the semiconductor package structure1.

A semiconductor package according to some embodiments may have a high stacking density and an optimum electrical connection length through an electrical connection between upper and lower portions thereof, which may result in an improvement in high-speed properties.

Although various embodiments have been described in connection with the some embodiments illustrated in the accompanying drawings, it will be understood by one of ordinary skill in the art that variations in form and detail may be made therein without departing from the spirit of the present disclosure. The above embodiments should thus be considered illustrative and not restrictive.