Method and apparatus for preventing inherent error propagation of successive approximation register analog-to-digital converter through digital correction

A method and apparatus for preventing inherent error propagation of a successive approximation register (SAR)-based analog-to-digital converter (ADC) through digital correction. A sample-and-hold circuit captures an input analog signal and generates a hold sample of the input analog signal. A digital-to-analog converter (DAC) generates an iterative sample corresponding to a digital code for each iteration. A comparator compares the hold sample and the iterative sample and generates a decision signal based on the comparison. A successive approximation register updates the digital code for each iteration based on the decision signal and supplies the updated digital code to the DAC. The SAR ADC includes an error detection circuit to detect an error condition. A controller ceases iteration operation if the error condition is detected and outputs the current digital code as a result.

FIELD

Examples relate to a successive approximation register (SAR)-based analog-to-digital converter (ADC), more particularly, to a method and apparatus for preventing inherent error propagation of an SAR ADC through digital correction.

BACKGROUND

An SAR ADC is a type of ADC that converts an analog input signal into a digital representation by implementing a binary search algorithm. Via the binary search through possible quantization levels, the SAR ADC converges upon a digital output. An SAR ADC has been used for medium-to-high-resolution applications.

While the internal circuitry of the SAR ADC may be running at high frequency, the ADC sample rate is a fraction of that frequency due to the successive approximation algorithm. The resolution of SAR ADCs most commonly ranges from 8 to 16 bits, and they provide low power consumption as well as a small form factor. These features make the SAR ADCs desirable for a wide variety of applications, including mobile phones, etc.

Due to its benefits of high performance (e.g. achievable resolution and precision), low power consumption as well as low footprint, SAR ADCs became more and more popular in a communication system. The main disadvantage of the SAR ADCs is the limitation of the sampling frequency. This is due to the iterative nature of the SAR ADCs that convert one bit per cycle. The SAR ADC architectures require a clock frequency as follows:
Fclock>R×Fsample,
where Fclockis the operational clock frequency, R is the resolution of the SAR ADC in bits, and Fsampleis the conversion or sampling frequency. In current deep submicron technologies, Fclockof 1 GHz is achievable, which means that for common precision requirements of 10 to 12 bits, a sampling frequency of 50 MHz is possible. Through time-interleaving this can be up-tuned by 2× or 4×, respectively, making this concept ideal for communication systems.

DETAILED DESCRIPTION

FIG. 1is a block diagram of an example SAR ADC100. An analog part of the SAR ADC100is shaded inFIG. 1. An input signal102enters a sample-and-hold circuit104. The sample-and-hold circuit104is clocked with a clock (A2D_ CLK) with a sampling frequency. The sample-and-hold circuit104provides a hold sample106of the analog input signal to a comparator108. The comparator108is an analog comparator that compares the hold sample106with an iterative sample110provided by an internal digital-to-analog converter (DAC)112. The comparator108generates a decision signal114, which is either logic 1 or logic 0 based on the comparison result, (e.g. generates a logic 0 signal if the instantaneous iterative sample116provided by the DAC112is lower than the hold sample106, and a logic 1 signal otherwise). The decision signal114from the comparator108selects an output of a multiplexer116, which determines the iteration value (a digital code) for the next iteration. For example, a look-up table118may provide a weight which is added to, and subtracted from, the current iteration value that is stored in the iteration register120to form two possible values (digital code candidates) to be selected at the multiplexer116. If the decision signal114indicates that the current value stored in the iteration register120is too low (logic 0) a larger value (i.e. the current iteration value plus the weight) will be selected, and if the decision signal114indicates that the current value stored in the iteration register120is too high (logic 1) a smaller value (i.e. the current iteration value minus the weight) will be selected. This new iteration value output from the multiplexer116may be held in a latch122before being sent to the DAC112for generating the instantaneous iterative sample110. The latch122is to keep the analog circuitry more stable for improved performance. The output register124holds the current value and outputs a final digital code.

A control block126is clocked by the operational clock (SAR_CLK). The frequency of the SAR_CLK is an integer multiple frequency of the A2D_CLK according to the above relationship f(SAR_CLK)>R×f(A2D_CLK), where R is the resolution in bits. The output register124and the sample-and-hold circuit104are clocked by the A2D_CLK and other sequential elements of the SAR ADC100and the controller126are clocked by the SAR_CLK. The controller126manages the reset of the sequential logic for each iteration of the A2D_CLK and the update into the output register124as well as the pointer logic (counter) into the look-up table118.

Besides all the benefits of power, performance, and area of the SAR ADC architecture, the example SAR ADC inFIG. 1has design constraints especially when getting closer to the technology limits, i.e. for higher resolutions at higher sampling clocks, e.g. for Fclock>1 GHz. The decision of the comparator108is improperly modeled if only logic 1 or logic 0 is assumed. In fact, the nature of the SAR ADC algorithm is to iteratively converge to the analog hold sample106with the DAC output110. As these two values get closer, the differential voltage for the comparator108becomes smaller. As the differential voltage for the comparator108becomes smaller, it takes longer for the comparator108to make a decision signal114which is firmly logic 1 or logic 0.

In that case, the comparator108may become metastable and float its decision. The decision signal114made by the comparator108in such cases can become neither logic 1 nor logic 0. Therefore, the logic level alphabet of the comparator108needs to be extended to model those cases. For example, additional states, such as logic U (for unknown) or logic M (for metastable), may be introduced.

With the decision signal114of the comparator108being fed back into a digital circuitry with multi-bit processing on the adders, subtractors, multiplexors and registers/latches, this can cause timing (setup and/or hold) violations which can lead to arbitrary (random in nature) values as feedback candidates into the iteration register120. Once the iteration register120intakes a random value the remaining conversion cycles may not be able to catch up with the amplitude error. In general, an SAR ADC100is dimensioned with the values in the look-up table118such that one of the decisions of the comparator108can be wrong using amplitude redundancy, as long as the decision is firmly wrong, e.g. logic 1 where it should have been logic 0, and vice versa. In more generalized cases, when considering decisions of logic U or logic M (though infrequent) happening, this does not hold true anymore and one can observe larger signal errors in the form of spikes.

For a properly dimensioned SAR ADC such error events occur very seldom in a general case. However, considering an error every 1 billion samples would lead to measurable bit error rates, depending on the throughput of the communication system this can be too frequent for practical cases and not all communication systems would be able to tolerate such errors.

This problem may be addressed by probabilistic means. For example, the comparator108may be heavily overdesigned using larger currents to shift the probability down. However, it can still be shown that this effect is frequent enough to be measurable. A communication system may not tolerate a bit error in a day to a week or so. Increasing the operating current further leads to commercially unattractive power, performance, and area metrics and thus may not be a good solution to the problem.

Other solutions may be to qualify the comparator decision114by introducing yet another signal which is defining if the decision is ready or not. However, this, in fact, moves the problem from the decision signal114to the qualifying signal. Additional timing margin should be reserved to cater for a solid overlap to make practical solutions possible. This can jeopardize the most crucial design element, i.e. the timing budget for the comparator, which in itself normally defines the performance metric for the SAR ADC.

The above problem may be circumvented by being asynchronous and waiting as long as the comparator108possibly might need. However, this leads to non-deterministic iteration timings which poses other side effects and much harder design and sign-off process.

The examples disclosed herein solve the problem discussed above by means of an error detection and correction which is holistic in nature and release design constraints from the comparator.

The example SAR ADCs disclosed herein utilize two facts to improve its operation. Firstly, once the comparator is indecisive, the current digital code in the iteration register is very close to the desired digital representation of the analog input signal. Therefore, in that situation, the operation of the SAR ADC may be ceased and the iteration may stop, and the digital code of the previous iteration cycle as stored in the iteration register120may be sent as an output value by latching it into the output register124.

Secondly, exploiting the above condition, if the comparator output is logic 1 or logic 0 (i.e. the two expected/desired comparator outputs) the iteration register would be updated to one of the two possible candidate values (as preset as inputs to the multiplexer116) in the next cycle which may be the iteration register value plus and minus the weight. If the iteration register was not updated in that subsequent cycle with one of these two values it can be said that the comparator decision took up a non-decisive logic value (e.g. logic M or logic U) as a cause and thus it can be decided to cease the iteration operation of the SAR ADC and the digital code in the iteration register may be sent as an output value.

In examples, the SAR ADC includes means for detecting such error conditions of the SAR ADC (e.g. if the comparator outputs an indecisive value, or if the iteration register is updated with a value that is not expected from the previous iteration value, etc.) and a controller may cease the iteration operation of the SAR ADC and may output the previous iteration register value as an output.

FIG. 2is a schematic block diagram of an example SAR ADC200. The SAR ADC200includes a sample-and-hold circuit210, a DAC220, a comparator230, a successive approximation register240, an error detection circuit250, and a controller260. The sample-and-hold circuit210is configured to capture an input analog signal and generate a hold sample of the input analog signal. The DAC220is configured to generate an iterative sample corresponding to a digital code. The comparator230is configured to compare the hold sample and the iterative sample and generate a decision signal based on the comparison. The successive approximation register240is configured to update the digital code for each iteration based on the decision signal and supply the updated digital code to the DAC220. The error detection circuit250is configured to detect an error condition (e.g. if the comparator outputs an indecisive value, or if the iteration register is updated with a value that is not expected from the previous iteration value, etc.) in the operation of the SAR ADC (e.g. based on digital codes before and after update). The controller260is configured to cease the iteration operation and output a digital code in a previous iteration as a result if the error condition is detected.

FIG. 3is a block diagram of an example SAR ADC300according to one aspect. An analog input signal302enters a sample-and-hold circuit304. The sample-and-hold circuit304is clocked with the A2D_CLK. The sample-and-hold circuit304provides a hold sample306of an analog input signal302to a comparator308. The comparator308compares the hold sample306with an iterative sample310provided by an internal DAC312. The comparator308makes a decision signal314, which is either logic 1 or logic 0 based on the comparison result, (e.g. logic 0 if the instantaneous iterative sample310provided by the DAC312is lower than the hold sample306, and logic 1 otherwise). The decision signal314from the comparator308is sent to a multiplexer316and a multiplexer output is selected based on the decision signal314. The multiplexer output may be stored in a latch322before being sent to the DAC312. The multiplexer output is sent to the DAC312for generating the iterative sample310. The multiplexer output is also sent the iteration register320to update the iteration register320.

In some examples, the SAR ADC300may include a look-up table318for providing a weight. The weight is added to, and subtracted from, the current iteration value by an adder328and a subtractor329, respectively. The current iteration value plus and minus the weight form the two update candidates to be selected by the multiplexer316for the next iteration. If the decision signal314indicates that the current value stored in the iteration register320is too low (logic 0), a larger value (i.e. the iteration value plus the weight) is selected, and if the decision signal314indicates that the current value stored in the iteration register320is too high (logic 1), a smaller value (i.e. the iteration value minus the weight) is selected. As explained above, this new iteration value is held in the latch322before being sent to the DAC312and to the iteration register320. The latch322is to keep the analog circuitry more stable for improved performance. The output register324holds a final digital code as an output.

In some examples, the SAR ADC300may include error detection circuits. The error detection circuits may include update candidate registers332,334, logic equivalence gates338,340, and a logic gate342(e.g. an exclusive OR (XOR) gate, an OR gate, etc.). The update candidate registers332,334are provided to store the positive and negative digital code update candidates (e.g. the iteration value plus and minus the weight provided by the look-up table318) for each iteration, respectively. The update candidate registers332,334are solely driven by signals which do not depend on the comparator decision signal314.

At each iteration, as the decision signal314is issued from the comparator308, the multiplexer316makes an output and the iteration register320is updated accordingly. It is determined whether the updated iteration register value is same as the values in the update candidate registers332,334, which were stored in the previous iteration, by logic equivalence gates338,340. The equivalence results are captured by the logic gate342(e.g. an XOR gate, an OR gate, etc.) and sent to the controller326.

If one of the logic equivalence (=) yields logic 1 (alternatively logic 0) (e.g. the updated iteration register value is same as one of the update candidate register values), the controller326may continue the iteration operation of the SAR ADC300. If none of the logic equivalence (=) yields logic 1 (alternatively logic 0) (e.g. the updated iteration register value is not same as one of the update candidate register values), the controller326may determine that the comparator308made a non-decisive value and cease the iteration operation of the SAR ADC300and may output the previous iteration value as a result to the output register. In order to store the previous iteration value, an additional result candidate register336may be provided, which feeds the SAR ADC output through the output register324.

With this scheme, the implementation of the SAR ADC remains purely digital and keeps the absolutely synchronous logic. There is no change to the analog circuitry in the conventional SAR ADC. The comparator may be down-dimensioned, which can lead less operating current and reduced power consumption. The error detection logic may detect that the SAR ADC iteration gets close to the target and may abort the remaining conversion cycles. This can save the power as well. With the same comparator it would be possible to achieve higher target frequencies for SAR_CLK since by means of the error detection/correction logic the timing requirements of the comparator can be relaxed. With the examples disclosed herein, error events are digitally countable for characterization and validation of the performance in the timing loop.

Another example is a computer program having a program code for performing at least one of the methods described herein, when the computer program is executed on a computer, a processor, or a programmable hardware component. Another example is a machine-readable storage including machine readable instructions, when executed, to implement a method or realize an apparatus as described herein. A further example is a machine-readable medium including code, when executed, to cause a machine to perform any of the methods described herein.

The SAR ADC disclosed herein may be included in any device including a wireless communication device. The device may be a user device or a network device.FIG. 4illustrates a user device400in accordance with an aspect. The user device400may be a mobile device (e.g. a smart phone, a laptop computer, a tablet computer, etc.) in some aspects and includes an application processor405, baseband processor410(also referred to as a baseband module), radio front end module (RFEM)415, memory420, connectivity module425, near field communication (NFC) controller430, audio driver435, camera driver440, touch screen445, display driver450, sensors455, removable memory460, power management integrated circuit (PMIC)465and smart battery470.

In some aspects, application processor405may include, for example, one or more CPU cores and one or more of cache memory, low drop-out voltage regulators (LDOs), interrupt controllers, serial interfaces such as serial peripheral interface (SPI), inter-integrated circuit (I2C) or universal programmable serial interface module, real time clock (RTC), timer-counters including interval and watchdog timers, general purpose input-output (TO), memory card controllers such as secure digital/multi-media card (SD/MMC) or similar, universal serial bus (USB) interfaces, mobile industry processor interface (MIPI) interfaces and Joint Test Access Group (JTAG) test access ports.

In some aspects, baseband module410may be implemented, for example, as a solder-down substrate including one or more integrated circuits, a single packaged integrated circuit soldered to a main circuit board, and/or a multi-chip module containing two or more integrated circuits.

The examples as described herein may be summarized as follows:Example 1 is an SAR ADC. The SAR ADC includes a sample-and-hold circuit configured to capture an input analog signal and generate a hold sample of the input analog signal, a DAC configured to generate an iterative sample corresponding to a digital code, a comparator configured to compare the hold sample and the iterative sample and generate a decision signal based on the comparison, a successive approximation register configured to update the digital code for each iteration based on the decision signal and supply an updated digital code to the DAC, an error detection circuit configured to detect an error condition, and a controller configured to cease iteration operation if the error condition is detected.Example 2 is the SAR ADC of example 1, wherein the error condition is detected if the comparator outputs an indecisive value.Example 3 is the SAR ADC as in any one of examples 1-2, wherein the error condition is detected if an iteration register in the successive approximation register is updated with a value that is not expected from a previous iteration value.Example 4 is the SAR ADC as in any one of examples 1-3, wherein the successive approximation register includes an iteration register for storing a digital code, a look-up table for generating a weight to be added to, and subtracted from, the digital code stored in the integration register to generate digital code candidates, and a multiplexer for outputting one of the digital code candidates to the DAC based on the decision signal, wherein the output from the multiplexer is sent to the iteration register.Example 5 is the SAR ADC of example 4, wherein the successive approximation register includes a latch for latching an output of the multiplexer.Example 6 is the SAR ADC as in any one of examples 4-5, wherein the error detection circuit includes candidate registers for storing the digital code candidates, and logic equivalence circuits for determining whether a digital code output from the iteration register is same as one of the digital code candidates for each iteration, wherein the controller ceases the iteration operation if the digital code output from the iteration register is not same as one of the digital code candidates.Example 7 is the SAR ADC of example 6, wherein the error detection circuit includes a result candidate register for storing a digital code output from the iteration register, wherein a value stored in the result candidate register is output as a result if the error condition is detected.Example 8 is a method for converting an analog signal to a digital signal. The method comprises capturing an input analog signal and generating a hold sample of the input analog signal, generating, by a DAC, an iterative sample corresponding to a digital code, comparing the hold sample and the iterative sample and generating a decision signal based on the comparison, updating the digital code for each iteration based on the decision signal, wherein the iterative sample is generated from the updated digital code in each iteration, detecting an error condition, and ceasing iteration operation if the error condition is detected.Example 9 is the method of example 8, wherein the error condition is detected if the comparator outputs an indecisive value.Example 10 is the method as in any one of examples 8-9, wherein the error condition is detected if an iteration register in the successive approximation register is updated with a value that is not expected from a previous iteration value.Example 11 is the method as in any one of examples 8-10, further comprising storing the digital code and the updated digital code in an iteration register, generating a weight to be added to, and subtracted from, the digital code stored in the iteration register to generate digital code candidates, and outputting one of the digital code candidates to the DAC based on the decision signal.Example 12 is the method of example 11, wherein the one of the digital code candidates is latched temporarily before being sent to the DAC.Example 13 is the method as in any one of examples 11-12, wherein the error condition is detected if an updated digital code for a current iteration is not same as one of the digital code candidates.Example 14 is the method as in any one of examples 11-13, wherein a digital code output from the iteration register is stored in a temporary register, and output as a result if the error condition is detected.Example 15 is a non-transitory computer-readable storage for storing a code, when executed, to implement a method as in any one of examples 8-14.Example 16 is an SAR ADC. The SAR ADC includes a capturing means for capturing an input analog signal and generating a hold sample of the input analog signal, a generating means for generating an iterative sample corresponding to a digital code, a comparing means for comparing the hold sample and the iterative sample and generating a decision signal based on the comparison, a updating means for updating the digital code for each iteration based on the decision signal and supplying an updated digital code to the means for generating, a detecting means for detecting an error condition, and a controlling means for ceasing iteration operation if the error condition is detected.Example 17 is the SAR ADC of example 16, wherein the error condition is detected if the comparing means outputs an indecisive value.Example 18 is the SAR ADC as in any one of examples 16-17, wherein the error condition is detected if an iteration register in the updating means is updated with a value that is not expected from a previous iteration value.Example 19 is the SAR ADC as in any one of examples 16-18, wherein the updating means includes an iteration register for storing a digital code, a look-up table for generating a weight to be added to, and subtracted from, the digital code stored in the integration register to generate digital code candidates, and a multiplexer for outputting one of the digital code candidates to the generating means based on the decision signal, wherein the output from the multiplexer is sent to the iteration register.Example 20 is the SAR ADC of example 19, wherein the updating means includes a latch for latching an output of the multiplexer.Example 21 is the SAR ADC as in any one of examples 19-20, wherein the detecting means includes candidate registers for storing the digital code candidates, and logic equivalence circuits for determining whether a digital code output from the iteration register is same as one of the digital code candidates for each iteration, wherein the controlling means ceases the iteration operation if the digital code output from the iteration register is not same as one of the digital code candidates.Example 22 is the SAR ADC of example 21, wherein the detecting means includes a result candidate register for storing a digital code output from the iteration register, wherein a value stored in the result candidate register is output as a result if the error condition is detected.

The description and drawings merely illustrate the principles of the disclosure. Furthermore, all examples recited herein are principally intended expressly to be only for pedagogical purposes to aid the reader in understanding the principles of the disclosure and the concepts contributed by the inventor(s) to furthering the art. All statements herein reciting principles, aspects, and examples of the disclosure, as well as specific examples thereof, are intended to encompass equivalents thereof.