Non-volatile static random access memory

A non-volatile static random access memory has an operating mode, a data backup mode and a data restore mode. The non-volatile static random access memory includes a memory cell and a power saving module. The memory cell includes a latch, a set of latch switch units, a set of backup memory units, a set of backup activation units, a backup setting unit and a driving signal transmission unit. The power saving module includes a control switch unit, a backup determination unit and a restore switch unit. When backup data is different from data stored in the latch, a backup driving signal is generated by a node voltage of the backup memory units and outputted to a backup determination unit, which drives the backup setting unit to turn on according to the backup driving signal, so as to change the backup data in the backup memory units and ensure correct backup.

TECHNICAL FIELD

The present invention relates to a non-volatile static random access memory, and more particularly to a non-volatile static random access memory which performs data backup only when backup data is different from stored data.

BACKGROUND

To conserve energy, today most of the portable, wearable, wireless sensor network and other electronic products are designed to be low in power consumption and compact in size. When the system end of a memory detects that the power supply is unstable or the system is about to enter a hibernation mode before the power is turned off, every piece of data in the memory must be backed up and stored in a backup memory element of a memory unit. However, data backup usually consumes a considerable amount of power. Therefore, unnecessary power waste may occur when backup data is already stored correctly in the backup memory element but is still being overwritten.

Moreover, when the power supply is unstable or the external power supply has a sudden power outage, the system would rely on the electric power pre-stored in the capacitor for system operations. Therefore, if backup data is already stored correctly in the backup memory element but is still overwritten, the remaining electric power would be wasted and the memory may store incorrect data once all the remaining power is run out before data backup is completed.

Therefore, there is a need to develop a non-volatile static random access memory capable of determining the need for data backup in advance. Thus, overwriting the same data is avoided when the backup data is up-to-date, and unnecessary power waste is minimized, so that the memory would contain sufficient power to perform data backup completely and correctly.

SUMMARY

One objective of the present invention is to provide a non-volatile static random access memory capable of determining whether the backup memory unit has stored correct data prior to data backup.

Another objective of the present invention is to provide a non-volatile static random access memory with minimized power consumption.

Still another objective of the present invention is to provide a non-volatile static random access memory capable of performing data backup completely and correctly.

The present invention provides a non-volatile static random access memory. The non-volatile static random access memory has an operating mode, a data backup mode and a data restore mode. The non-volatile static random access memory includes a memory cell and a power saving module. The memory cell is electrically coupled to a word line, a bit line, a complementary bit line, a backup signal line, a backup signal transmission line and a backup setting line. The memory cell includes a latch, a set of latch switch units, a set of backup memory units, a set of backup activation units, a backup setting unit and a driving signal transmission unit. When the latch switch unit is turned on by a signal transmitted by the word line under the operating mode and, the bit line and the complementary bit line are electrically coupled to the latch and data written by the bit line or the complementary bit line is received by and stored in the latch. The set of backup memory units have a node voltage. The backup memory units are electrically coupled to the backup signal transmission line and configured to store backup data. When the backup data is different from the data stored in the latch, a backup driving signal is generated by the node voltage of the backup memory units and outputted via the backup signal transmission line. The set of backup activation units are configured to electrically couple the backup memory unit to the latch when the backup activation units are turned on by a signal transmitted by the backup signal line under the data backup mode or the data restore mode. The backup memory units change the backup data according to a voltage level on the bit line and the data stored in the latch. The backup setting unit is configured to electrically couple the bit line to the backup memory units when the backup activation units are turned on under the data backup mode or the data restore mode. The driving signal transmission unit is electrically coupled between the backup signal transmission line and the backup memory unit and configured to enable the backup signal transmission line to transmit signals when the driving signal transmission unit is turned on under the data backup mode or the data restore mode. The power saving module is electrically coupled to the backup memory units via the backup signal transmission line and configured to receive the backup driving signal when the driving signal transmission unit is turned on. The power saving module includes a control switch unit, a backup determination unit and a restore switch unit. The control switch unit is configured to electrically couple the backup signal transmission line to a reference voltage when the control switch unit is turned on by the signal transmitted by the word line under the operating mode and configured to output the backup driving signal via the backup signal transmission line when being turned off under the data backup mode or in the data restore mode. The backup determination unit is configured to receive the backup driving signal transmitted by the backup signal transmission line and drive the backup setting unit to turn on according to the backup driving signal. The restore switch unit is configured to drive the backup setting unit to turn on under the data restore mode.

In summary, the present invention provides a non-volatile static random access memory. Prior to data backup, the backup determination unit determines whether the backup data stored in the backup memory units is correct. Specifically, data backup is performed only when the backup data is incorrect. Therefore, overwriting of the same data is prevented when the backup data is correct, so that unnecessary power waste is avoided and the memory would contain sufficient power to perform data backup completely and correctly.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

FIG. 1Ais a schematic circuit diagram of a non-volatile static random access memory in accordance with an embodiment of the present invention. The non-volatile static random access memory of the present embodiment has an operating mode, a data backup mode and a data restore mode. As shown inFIG. 1A, the non-volatile static random access memory of the present embodiment includes a memory cell1and a power saving module2. The memory cell1is electrically coupled to a word line WL, a bit line BL, a complementary bit line BLB, a backup signal line SWL, a backup signal transmission line3and a backup setting line4. The memory cell1includes a set of latch switch units11, a latch10, a set of backup activation units12, a set of backup memory units15, a backup setting unit13and a driving signal transmission unit16.

Under the operating mode, the latch switch unit11is turned on by the signal transmitted by the word line WL and configured to electrically connect the bit line BL and the complementary bit line BLB to the latch10; consequently, the latch10is configured to receive and store data written by the bit line BL or the complementary bit line BLB. The set of backup memory units15are electrically coupled to the backup signal transmission line3and configured to store backup data. When the backup data is different from the data stored in the latch10, the backup memory units15are configured to generate a backup driving signal and output the backup driving signal via the backup signal transmission line3. In the present embodiment, the backup memory units15include a first resistive memory element R1and a second resistive memory element R2. The backup driving signal is also referred to as the node voltage Tag between the first resistive memory element R1and the second resistive memory element R2. Both of the first resistive memory element R1and the second resistive memory element R2have a high resistance state and a low resistance state that are state switchable. When the setting terminals TE of the first resistive memory element R1and the second resistive memory element R2receive the data, the first resistive memory element R1and the second resistive memory element R2are in the low resistance state. Alternatively, when the resetting terminals BE of the first resistive memory element R1and the second resistive memory element R2receive the data, the first resistive memory element R1and the second resistive memory element R2are in the high resistance state.

The set of backup activation units12are turned on by the signal transmitted by the backup signal line SWL under the data backup mode or the data restore mode. The data written by the bit line BL is transmitted to the backup memory units15and the latch10via the backup activation units12in an ON-state. Consequently, the backup memory units15change the stored backup data according to the voltage level on the bit line BL and the data stored in the latch10. The driving signal transmission unit16is electrically coupled between the backup signal transmission line3and the backup memory unit15. When the driving signal transmission unit16is turned on under the data backup mode or the data restore mode, the backup signal transmission line3is enabled to transmit signals.

When the driving signal transmission unit16is turned on, the power saving module2is electrically connected to the backup memory units15via the backup signal transmission line3and configured to receive the backup driving signal. As shown inFIG. 1B, the power saving module2includes a control switch unit21, a backup determination unit22and a restore switch unit23. Under the operating mode, the control switch unit21is turned on by the signal transmitted by the word line WL and electrically connects the backup signal transmission line3to a reference voltage VSS; and therefore, the backup driving signal is discharged to the reference voltage VSS. Under the data backup mode or the data restore mode, the control switch unit21is turned off and the backup driving signal is outputted from the backup signal transmission line3to the backup determination unit22. When receiving the backup driving signal, the backup determination unit22is configured to turn the backup setting unit13on or off according to the backup driving signal. Under the data restore mode, the restore switch unit23is configured to turn on the backup setting unit13.

In the present embodiment, the latch switch unit11includes a first control transistor M1and a second control transistor M2. The backup activation units12include a third control transistor M3and a fourth control transistor M4. The driving signal transmission unit16includes a fifth control transistor M5. The backup setting unit13includes a sixth control transistor M6. Each of the transistors in the latch switch units11, the backup activation units12, the driving signal transmission unit16and the backup setting unit13has a first source/drain, a second source/drain and a gate. The latch10has a first transmission node Q and a second transmission node QB. Both of the first resistive memory element R1and the second resistive memory element R2have a setting terminal TE and a resetting terminal BE.

The gates M13and M23of the first control transistor M1and the second control transistor M2are electrically coupled to the word line WL. The first source/drain M11and the second source/drain M12of the first control transistor M1are electrically coupled to the bit line BL and the first transmission node Q, respectively. The first source/drain M21and the second source/drain M22of the second control transistor M2are electrically coupled to the second transmission node QB and the complementary bit line BLB, respectively.

The gates M33, M43and M53of the third control transistor M3, the fourth control transistor M4and the fifth control transistor M5are electrically coupled to the backup signal line SWL. The first source/drain M31and the second source/drain M32of the third control transistor M3are electrically coupled to the first transmission node Q and the resetting terminal BE of the first resistive memory element R1, respectively. The first source/drain M41and the second source/drain M42of the fourth control transistor M4are electrically coupled to the second transmission node QB and the resetting terminal BE of the second resistive memory element R2, respectively. The first source/drain M51and the second source/drain M52of the fifth control transistor M5are electrically coupled to the setting terminal TE of the second resistive memory element R2and the backup signal transmission line3, respectively. The gate M63of the sixth control transistor M6is electrically coupled to the backup determination unit22and the restore switch unit23of the power saving module2via the backup setting line4. The first source/drain M61and the second source/drain M62of the sixth control transistor M6are electrically coupled to the bit line BL and the setting terminal TE of the first resistive memory element R1, respectively. The setting terminal TE of the first resistive memory element R1and the setting terminal TE of the second resistive memory element R2are electrically coupled to each other.

As shown inFIG. 1B, the control switch unit21includes a first power saving transistor D1. The backup determination unit22includes a second power saving transistor D2, a third power saving transistor D3, a fourth power saving transistor D4, a fifth power saving transistor D5, a sixth power saving transistor D6, a seventh power saving transistor D7, an eighth power saving transistor D8, a ninth power saving transistor D9, a tenth power saving transistor D10and an eleventh power saving transistor D11. The restore switch unit23includes a twelfth power saving transistor D12. Each of the transistors in the control switch unit21, the backup determination unit22and the restore switch unit23has a first source/drain, a second source/drain and a gate. In the present embodiment, the second, fourth, sixth, eighth, eleventh and twelfth power saving transistors are P-type transistors; and the first, third, fifth, seventh, ninth and tenth power saving transistors are N-type transistors.

The second sources/drains D12, D32, D52, D72and D92of the first power saving transistor D1, the third power saving transistor D3, the fifth power saving transistor D5, the seventh power saving transistor D7and the ninth power saving transistor D9are electrically coupled to the reference voltage VSS, respectively. The first sources/drains D21and D41of the second power saving transistor D2and the fourth power saving transistor D4are electrically coupled to a first voltage source VDD1, respectively. The first sources/drains D61and D81of the sixth power saving transistor D6and the eighth power saving transistor D8are electrically coupled to a second voltage source VDD2, respectively. The gates D103and D123of the tenth power saving transistor D10and the twelfth power saving transistor D12are electrically coupled to the second voltage source VDD2, respectively. The gate D113of the eleventh power saving transistor D11is electrically coupled to a reversed voltage source VDD2_bar. The gates D23and D33of the second power saving transistor D2and the third power saving transistor D3are electrically coupled to the backup signal transmission line3, respectively. The second source/drain D22of the second power saving transistor D2and the first source/drain D31of the third power saving transistor D3are electrically coupled to the gate D43of the fourth power saving transistor D4and the gate D53of the fifth power saving transistor D5. The second source/drain D42of the fourth power saving transistor D4and the first source/drain D51of the fifth power saving transistor D5are electrically coupled to the gate D73of the seventh power saving transistor D7. The gate D63of the sixth power saving transistor D6is electrically coupled to a pre-charging signal PV. The second source/drain D62of the sixth power saving transistor D6and the first source/drain D71of the seventh power saving transistor D7are electrically coupled to the gate D83of the eighth power saving transistor D8and the gate D93of the ninth power saving transistor D9. The second source/drain D82of the eighth power saving transistor D8and the first source/drain D91of the ninth power saving transistor D9are electrically coupled to the first source/drain D101of the tenth power saving transistor D10and first source/drain D111of the eleventh power saving transistor D11. The second source/drain D102of the tenth power saving transistor D10and the second source/drain D112of the eleventh power saving transistor D11are electrically coupled to the gate M63of the sixth control transistor M6of the backup setting unit13. The first source/drain D121of the twelfth power saving transistor D12is electrically coupled to a third voltage source VDD3. The second source/drain D122of the twelfth power saving transistor D12is electrically coupled to the gate M63of the sixth control transistor M6of the backup setting unit13.

FIG. 2is a schematic circuit diagram of a non-volatile static random access memory in an operating mode in accordance with an embodiment of the present invention. Under the operating mode, the first control transistor M1, the second control transistor M2and the first power saving transistor D1are turned on by the signal transmitted by the word line WL; the third control transistor M3and the fourth control transistor M4are turned off. Before the data is written, the bit line BL and the complementary bit line BLB are pre-charged; either the bit line BL or the complementary bit line BLB selected by the writing path is discharged; and the data is written into the latch10. In addition, when reading data, the bit line BL and the complementary bit line BLB need to be pre-charged; the discharging path is determined according to the data stored in the latch10and is provided to the related sensing amplifier (not shown) for the data reading. When the write data is 1 as exemplified inFIG. 2, the first transmission node Q of the latch10is 1 and the second transmission node QB is 0. When the write data is 0 as exemplified inFIG. 3, the first transmission node Q of the latch10is 0 and the second transmission node QB is 1.

Before entering the data backup mode as shown inFIG. 4, a voltage signal of 0 V is provided by the pre-charging signal PV; the P-typed sixth power saving transistor D6is turned on; and the node N1between the sixth power saving transistor D6and the seventh power saving transistor D7is pre-charged to a charging voltage (3.3 V) by the second power source VDD2. Thereafter, under the data backup mode as shown inFIG. 5, the first power saving transistor D1is turned off; the electrical conduction between the backup signal transmission line3and the reference voltage VSS is released; the node voltage Tag between the first resistive memory element R1and the second resistive memory element R2is transmitted to the backup determination unit22; and the backup determination unit22determines whether data backup is necessary. The node voltage Tag has a high level and a low level. Specifically, the node voltage Tag has a high level when the data written into the latch10is different from the backup data stored in the backup memory unit15. Alternatively, the node voltage Tag has a low level when the data written into the latch10is identical to the backup data stored in the backup memory unit15. Therefore, the backup determination unit22can drive the sixth power saving transistor D6of the backup setting unit13to turn on according to the high level of the node voltage Tag and drive the sixth power saving transistor D6of the backup setting unit13to turn off according to the low level of the node voltage Tag.

In the present embodiment as shown inFIG. 5, the high level of the node voltage Tag is 2.17 V. Therefore, the third power saving transistor D3and the fourth power saving transistor D4are turned on; and the seventh power saving transistor D7is turned on by the first voltage source VDD1(e.g., 2.5 V). At this time, the original pre-charging signal PV is 3.3 V. As the P-typed sixth power saving transistor D6is turned off, the charging voltage of the node N1is discharged to the reference voltage VSS by the seventh power saving transistor D7and drops to 0 V. Since the discharge control of the node N1is determined by the low and high levels of the node voltage Tag, discharge of the node N1is represents that the write data is different from the backup data and data backup is required. Therefore, the third control transistor M3, the fourth control transistor M4, and the sixth power saving transistor D6of the backup activation units12are turned on; the write data (2.5 V) on the bit line BL is received by the setting terminal TE of the first resistive memory element R1and outputted to the first transmission node Q from the resetting terminal BE thereof; and the resistance state of the first resistive memory element R1is set. Thereafter, as shown inFIG. 6, the input voltage is decreased to 0 V by the bit line BL; data is transmitted from the second transmission node QB to the resetting terminal BE of the second resistive memory element R2; and the resistance state of the second resistive memory element R2is set.

A low level of the node voltage Tag indicates that data backup is not required. As shown inFIG. 7, the second power saving transistor D2and the fifth power saving transistor D5are turned on; the seventh power saving transistor D7is turned off; the charging voltage of the node N1is not discharged; the eighth power saving transistor D8is turned off and the ninth power saving transistor D9is turned on by the charging voltage of the node N1; the second voltage source VDD2stops being outputted to the sixth control transistor M6; the sixth control transistor M6is turned off; and the first resistive memory element R1and the second resistive memory element R2are maintained at the original state.

After the data backup mode is ended, the non-volatile static random access memory of the present embodiment is switched to a hibernation state and all of the switch units remain undriveable until the non-volatile static random access memory is switched back to the data backup mode from the hibernation state. In the data backup mode as shown inFIG. 8, the twelfth power saving transistor D12is turned on by the third voltage source VDD3; the third voltage source VDD3is transmitted to the sixth control transistor M6; and the sixth control transistor M6is turned on.

The non-volatile static random access memory of the present embodiment is exemplified by a resistive random access memory (RRAM). To allow normal functioning of the memory, the non-volatile resistive static random access memory further includes a forming mode and an initiating mode, before entering the operating mode. As shown inFIG. 9, in the forming mode, the first control transistor M1and the second control transistor M2are turned on by the signal transmitted by the word line WL; the sixth control transistor M6is turned on by the signal transmitted by the restore switch unit23; the latch10receives, from the second transmission node QB, the data written by the complementary bit line BLB; and the data is outputted from the bit line BL via the first transmission node Q. Thereafter, as shown inFIG. 10, the first control transistor M1and the second control transistor M2are turned off; the third control transistor M3, the fourth control transistor M4and the fifth control transistor M5are turned on by the signal transmitted by the backup signal line SWL; the data written by the bit line BL is transmitted via the sixth control transistor M6in an ON-state; the data is received by the setting terminal TE of the first resistive memory element R1and outputted by the resetting terminal BE; thereafter, the data is transmitted to the first transmission node Q of the latch10via the third control transistor M3in an ON-state. Thus, the forming of the first resistive memory element R1is completed. As shown inFIG. 11, which provides an opposite example ofFIG. 9, data of 2.5 V is written into the first transmission node Q and data of 0V is written into the second transmission node QB; the data written by the bit line BL is received by the setting terminal TE of the second control transistor M2, outputted by the resetting terminal BE, and transmitted to the second transmission node QB of the latch10via the fourth control transistor M4in an ON-state and written into the first transmission node Q. Thus, the forming of the second resistive memory element R2is completed, and both of the first resistive memory element R1and the second resistive memory element R2are in the low resistance state.

Next, the initiating mode is performed. As shown inFIG. 12, the voltage on the bit line BL drops to 0 V when the first resistive memory element R1and the second resistive memory element R2receive data via the setting terminals TE thereof and are in a low resistance state. Thus, the data written into the first transmission node Q of the latch10is transmitted to the resetting terminal BE of the first resistive memory element R1via the third transistor M3in an ON-state, outputted from the setting terminal TE, and discharged when transmitted to the bit line BL via the sixth control transistor M6in an ON-state. Therefore, the first resistive memory element R1is switched into the high resistance state, whereas the second resistive memory element R2is still in the low resistance state. As a result, the first resistive memory element R1and the second resistive memory element R2have complementary resistances and the memory of the present embodiment can operate normally.

FIG. 13is a schematic circuit diagram of a non-volatile static random access memory in accordance with another embodiment of the present invention. As shown, the backup determination unit22of the present embodiment further includes a feedback inverter220. The feedback inverter220includes an input terminal2201and an output terminal2202. The input terminal2201is electrically coupled to the first source/drain D91of the ninth power saving transistor D9. The output terminal2202is electrically coupled to the second source/drain D62of the sixth power saving transistor D6. When the backup determination unit22determines that the backup operation is not necessary according to the node voltage Tag, the feedback inverter220is configured to latch the charges of the second source/drain D62of the sixth power saving transistor D6. In the present embodiment, the driving capacity of the feedback inverter220is lower than that of the eighth power saving transistor D8and the ninth power saving transistor D9; therefore, the second source/drain D62of the sixth power saving transistor D6would not be affected and may discharge normally.

In summary, the present invention provides a non-volatile static random access memory. Prior to data backup, the backup determination unit determines whether the backup data stored in the backup memory unit is correct. Specifically, the data backup is performed only when the backup data is incorrect. Therefore, overwriting the same data is avoided when the backup data is correct, so that unnecessary power waste is minimized and the memory would contain sufficient power to perform data backup completely and correctly.