Logarithm and power (exponentiation) computations using modern computer architectures

Embodiments of the present invention may provide the capability to evaluate logarithm and power (exponentiation) functions using either hardware specific instructions, or a hardware specific implementation with reduced memory requirements. An input comprising a floating point representation of a real number may be received and a mantissa and an exponent may be extracted. A function of a logarithm of a mantissa of the real number may be approximated by utilizing a polynomial based on the mantissa. The approximated function of the logarithm may be combined with the exponent for calculating a value comprising a logarithm of the real number. Likewise, an input comprising a floating point representation of a real number and a representation of a second number may be received and an approximation of the real number to the power of the second number may be generated.

BACKGROUND

The present invention relates to techniques for computing logarithm and power (exponentiation) functions using hardware specific instructions.

Fast and energy efficient computation is important in many computing applications. The particular computations to be performed vary depending upon the application. For example, so-called “big data” applications and data in motion applications may compute logarithmic and power functions. Examples of such applications may include deep learning, neural network simulations, as well as the modeling of dynamic systems such as population growth, electrical circuits, cardiovascular networks, optimization problems, cryptography, and many others.

There are a number of well-known techniques for computing results using logarithm and power (exponentiation) functions. Such techniques may include Taylor series/expansions computations, look-up tables, manipulation in accordance with the IEEE-745 standards, combinations of these techniques, and others. Each of these techniques has advantages and disadvantages—some are quite complex and resource intensive, some are relatively inaccurate, etc. For example, computing logarithm and power (exponentiation) functions using general standardized or general purpose processors is usually relatively slow, and uses a relatively large amount of memory.

A need arises for a technique that provides the capability to evaluate logarithm and power (exponentiation) functions that provides improved speed and/or accuracy, and reduced memory usage.

SUMMARY

Embodiments of the present invention may provide the capability to evaluate logarithm and power (exponentiation) functions using hardware specific instructions. Likewise, embodiments of the present invention may provide the capability to evaluate logarithm and power (exponentiation) functions improved speed and/or accuracy, and reduced memory usage. The memory usage may be reduced sufficiently that embodiments may be implemented in specialized processing hardware.

According to an embodiment of the present invention, a system for performing mathematical function evaluation may comprise a processing unit comprising logic comprising a first set of hardware instructions configured to receive an input comprising a floating point representation of a real number and to extract a mantissa and an exponent, a second set of hardware instructions configured to approximate a function of a logarithm of a mantissa of the real number, wherein approximation may be performed by utilizing a polynomial, and wherein the polynomial is based on the mantissa, and a third set of hardware instructions configured to combine the approximate function of the logarithm of the mantissa of the real number and the exponent for calculating a value comprising an approximate logarithm of the real number.

The polynomial may be a Lagrange polynomial, an orthogonal polynomial, a Chebyshev polynomial, a Legendre polynomial, a trigonometric polynomial, a piecewise polynomial, a spline polynomial, a Hermite polynomial, or a Remez Polynomial. The input may further comprise a degree of the polynomial. Coefficients of the polynomial may be precomputed. The input may be a single scalar input value, a list of multiple scalar input values, or an input vector including multiple values. The system may further comprise a plurality of processing units, wherein each processing unit performs a same hardware instruction at a same time as the others of the plurality of processing units.

According to an embodiment of the present invention, a computer-implemented method for using hardware instructions to accelerate evaluation of mathematical functions, may comprise executing a first set of hardware instructions to receive an input comprising a floating point representation of a real number and to extract a mantissa and an exponent, executing a second set of hardware instructions to approximate a function of a logarithm of a mantissa of the real number, wherein approximation may be performed by utilizing a polynomial, and wherein the polynomial is based on the mantissa, and executing a third set of hardware instructions to combine the approximate function of the logarithm of the mantissa of the real number and the exponent for calculating a value comprising an approximate logarithm of the real number.

According to an embodiment of the present invention, a system for performing mathematical function evaluation may comprise a processing unit comprising logic comprising a first set of hardware instructions configured to receive an input comprising a floating point representation of a real number and a representation of a second number and to extract a mantissa and an exponent from the floating point representation of the real number, a second set of hardware instructions configured to approximate a function of a logarithm of a mantissa of the real number, wherein approximation is performed by utilizing a polynomial, and wherein the polynomial is based on the mantissa, a third set of hardware instructions configured to combine the approximate function of the logarithm of the mantissa of the real number and the exponent for calculating a value comprising an approximate logarithm of the real number, a fourth set of hardware instructions configured to multiply the approximate logarithm of the of the real number and the second number, and a fifth set of hardware instructions configured to exponentiate the product of the approximate logarithm of the of the real number and the second number for calculating a value comprising an approximation of the real number to the power of the second number.

According to an embodiment of the present invention, a computer-implemented method for using hardware instructions to accelerate evaluation of mathematical functions may comprise executing a first set of hardware instructions configured to receive an input comprising a floating point representation of a real number and a representation of a second number and to extract a mantissa and an exponent from the floating point representation of the real number, executing a second set of hardware instructions configured to approximate a function of a logarithm of a mantissa of the real number, wherein approximation is performed by utilizing a polynomial, and wherein the polynomial is based on the mantissa, executing a third set of hardware instructions configured to combine the approximate function of the logarithm of the mantissa of the real number and the exponent for calculating a value comprising an approximate logarithm of the real number, executing a fourth set of hardware instructions configured to multiply the approximate logarithm of the of the real number and the second number, and executing a fifth set of hardware instructions configured to exponentiate the product of the approximate function of the logarithm of the mantissa of the real number and the second number for calculating a value comprising an approximation of the real number to the power of the second number.

According to an embodiment of the present invention, an apparatus may comprise a first at least one specialized processing elements specifically adapted to receive an input comprising a representation of a real number X, a second at least one specialized processing elements specifically adapted to extract a mantissa M and an exponent Z, based on the real number X, wherein the extraction of M and Z is obtained from a floating point representation, a third at least one specialized processing elements specifically adapted to approximate a function of a logarithm of the mantissa M of the real number X, wherein the approximation is performed utilizing a polynomial, and wherein the polynomial is based on the mantissa M, and a fourth at least one specialized processing elements specifically adapted to combine the approximate function of the logarithm of the mantissa M and the exponent Z for calculating a value comprising an approximate logarithm of the real number X, wherein the processing performed by the first, second, third, and/or fourth specialized processing elements for calculating the value comprising the logarithm is executed while utilizing an amount of memory that is significantly less than an amount of memory that would be used by a general standardized at least one processors for calculating the value.

According to an embodiment of the present invention, an apparatus may comprise a first at least one specialized processing element specifically adapted to receive an input comprising a representation of a first real number X and a second number, a second at least one specialized processing element specifically adapted to extract a mantissa M and an exponent Z, based on the real number X, wherein the extraction of M and Z is obtained from a floating point representation, a third at least one specialized processing element specifically adapted to approximate a function of a logarithm of the mantissa M of the real number X, wherein the approximation is performed utilizing a polynomial, and wherein the polynomial is based on the mantissa M, a fourth at least one specialized processing element specifically adapted to combine the approximate function of the logarithm of the mantissa M of the real number X and the exponent Z for calculating a value comprising an approximate logarithm of the real number X, a fifth at least one specialized processing element specifically adapted to multiply the approximate logarithm of the real number X and the second number, and a sixth at least one specialized processing element specifically adapted to exponentiate the product of the of the real number X and the second number for calculating a value comprising an approximation of the real number X to the power of the second number, wherein the processing performed by the first, second, third, fourth, and/or fifth specialized processing elements for calculating the value comprising the logarithm is executed while utilizing an amount of memory that is significantly less than an amount of memory that would be used by a general standardized at least one processors for calculating the value.

DETAILED DESCRIPTION

Embodiments of the present invention may provide the capability to evaluate logarithm and power (exponentiation) functions using hardware specific instructions.

An example of a storage format100of a floating-point number is shown inFIG. 1. In this example, the format100includes a sign portion102, an exponent portion104, and a fraction or mantissa portion106. For simplicity, sign portion102may be termed “s”, exponent portion104may be termed “z”, and mantissa portion106may be termed “m”. As an example, in the IEEE 754 Standard double-precision binary floating-point format known as binary64, s is 1 bit, z is 11 bits and m is 52 bits. In the binary64 example, z is encoded using an offset-binary representation, with the zero offset (also known as exponent bias) being 1023.

The following notations are used herein: “*” is a multiplication, “^” is a power (exponentiation) evaluation, “&” is the bitwise AND operator, “|” is the bitwise OR operator, “≈” indicates an approximation, “Int” indicates a generic integer (no assumption on the specific machine representation, e.g., int, long int, unsigned long int.), “Real” indicates a generic real or floating-point number (no assumption on the specific machine representation is given, e.g., float, double, long double), “log2( )” is the base 2 logarithm, “log 10( )” is the base 10 logarithm, and “ln( )” is the natural logarithm (the base is the Euler number e≈2.71828).

An exemplary flow diagram of a process200of computing a logarithm of an input is shown inFIG. 2. Process200begins with202, in which an input, for which a logarithm is to be computed, is received. The input may be a single scalar input value, a list of multiple scalar input values, or an input vector including multiple values. For example, if the desired computation is to generate a result “y”, such that y=ln(x), the received input is “x”. Additionally, a degree of an interpolation polynomial, as discussed below, may be specified. Typically, x is a numeric value in a floating-point representation. For example, x may be represented in an IEEE 754 Standard double-precision binary floating-point format known as binary64, as shown inFIG. 1.

In204, the mantissa, m, and the exponent, z, are extracted from the floating-point representation of x. This corresponds to expanding ln(x) to form its equivalent: ln(x)=ln(2)*(log2(m+1)+z−z0). This expression includes four terms: ln(2) is a constant that can be computed a priori and stored for repeated use, log2(m+1) is a bounded analytical function, with both m and log2(m+1) defined in the range [0 1], z is a positive integer (the exponent of input x), and z0 is a positive integer, equal to the zero offset or exponent bias of the particular floating point representation being used. For example, for the IEEE 754 Standard double-precision binary floating-point format known as binary64, z0=1023.

The mantissa, m, and the exponent, z, may be extracted using software instructions, using hardware-specific instructions, or special purpose hardware. For example, in C++, z may be extracted using the instruction “reinterpret_cast<Int> (Real)” followed by a multiplication by a shift factor “S”. For the binary64 representation, “S=2^−52”. Thus, for example, z may be extracted by the C++ code: “unsigned long int z=S*reinterpret_cast<unsigned long int> (x);”. Likewise, for example, in C++, m may be extracted using the instruction “reinterpret_cast<Int> (Real)”, followed by two bitwise operations and a multiplication by a shift factor “S”. Thus, for example, m may be extracted by the C++ code: “double m=((reinterpret_cast<unsigned long int> (x) & 0x000fffffffffffffL)|0x0010000000000000L)*S−1.0;”. It is to be noted that, as later it is m+1 that is needed, and not m, m+1 may be directly computed by omitting the final “−1.0”.

In206, an interpolating polynomial for log2(m+1) may be evaluated. An interpolating polynomial or other technique may be used to compute or approximate log2(m+1) using polynomial interpolation. For example, “log2(m+1) Fn(m+1)=a*(m+1)^n+b*(m+1)^(n−1)+c*(m+1)^(n−2)+ . . . ”, where “n” is the order of the polynomial interpolation. Examples of polynomial interpolations that may be used include, but are not limited to, Lagrange polynomials, Orthogonal polynomials, such as Chebyshev and Legendre polynomials, Trigonometric polynomials, Piecewise polynomials, such as Spline and Hermite polynomials, and Remez Polynomials. However, it is to be noted that other suitable polynomials may be used, and that the present invention contemplates the use of any such polynomial. For example, the Chebyshev expansion of log(m+1)=Σn=0∞anTn(x). The polynomial coefficients {a, b, c, . . . } are typically pre-computed according to the chosen interpolation polynomial. The polynomial may implemented following Homer's method, leading to a complexity of a floating-point multiply-add for each degree of the polynomial.

In208, the logarithm of x, ln(x), may be computed according to “y=ln(2)*(Fn(m+1)+z−z0)”. The evaluation of y may be implemented as “y=ln(2)*(Fn(m+1)+floor(z)−z0)”. The floor function may be used to map a real number to the largest previous integer. The call to the floor function and the pre-multiplication by ln(2) (or log(2) for the base 10 logarithm) may be both omitted by the modified computation: “y=Gn(m+1)+w−w0”, where “Gn(m+1)=ln(2)*(log2(m+1)−(m+1))”, w=“static_cast<double>(ln(2)*S*reinterpret_cast<unsigned long int> (x));”, and w0=ln(2)*(z0+1). It is noted that typically one evaluation of Gn(m+1) costs the same computing resources as one evaluation of Fn(m+1). In addition “ln(2)*S” and “w0” may be pre-computed constants.

In210, the computed logarithm may be returned as the result. Depending upon the input, the result may be a single scalar result value, a list of multiple scalar result values, or a result vector including multiple values. Logarithms of other bases are easily computed. For example, the base 2 logarithm, log2(x), may be computed by omitting the multiplication by ln(2) and the base 10 logarithm, log(x), may be computed by replacing the multiplication by ln(2) with a multiplication by log(2). Typically, the factors needed for such other base computations are constants that may be pre-computed and stored for use.

When compiled, the exemplary code shown above may be implemented as software instructions, or as hardware-specific instructions. For example, each of202-210may be implemented in software or as a set of one or more hardware instructions that may be specific to the hardware being used for the computation. Further improvements may be obtained by implementing part or all of the instructions in assembly code. Although modern compilers do a good job in optimizing the code, an assembler version would allow more precise control of the instructions that are actually used.

An exemplary flow diagram of a process300of computing an exponentiation of an input is shown inFIG. 3. Process300begins with302, in which an input, for which an exponentiation is to be computed, may be received. The input may be a single scalar input value, a list of multiple scalar input values, or an input vector including multiple values. For example, if the desired computation is to generate a result “y”, such that “y=b^x”, the received input may include the base “b” and the exponent, “x” Additionally, a degree “n1” of a polynomial to approximate the natural logarithm and a degree “n2” of a polynomial to approximate the natural exponential, may be specified. Typically, b and x are numeric values in a floating-point representation. For example, b and x may be represented in an IEEE 754 Standard double-precision binary floating-point format known as binary64, as shown inFIG. 1.

In304, the logarithm of base b may be computed using process200, shown inFIG. 2. The input b, and any specified or default value of n1 may be used to compute “y1=log2(b)”. In order see the utility to the computation of “y=b^x”, a logarithm of base 2 may be applied to both side of the power equation: “log2(y)=log2(b^x)”. Using the logarithm power rule on the right side of the equation yields: “log2(y)=x*log2(b)”. Thus, the computation of “y1=log2(b)” may be performed. For example, process200may be used to compute the logarithm.

In306, an intermediate product “y2=x*y1” may be computed. As discussed above, this is equivalent to “y2=x*log2(b)”. In308, the final result (power or exponentiation) may be computed according to “y=2^y2”, which is equivalent to “y=2^(x*log2(b))”. This expression includes three operations: a logarithm of base 2, a multiplication, and an exponentiation of base 2. The logarithm and the exponentiation can be expressed with respect to other base values. For example, for base e: “y=2^(x*log2(b))=e^(x*ln(b))”. As base 2 is typically inherently implemented on modern computers, base 2 computation is typically advantageous.

The exponentiation308may be performed using, for example, the technique described in U.S. patent application Ser. No. 14/532,312, which is hereby incorporated by reference herein. For example, a first expression A*(y2−ln(2)*Kn2(y2f))+B may be evaluated. In this expression, y2 may be the input to the exponentiation method, Kn2(y2f) may be a polynomial function of the degree n2, y2fmay be a fractional part or mantissa of y2/ln(2), A may equal 252/ln(2), and B may equal 1023*252. It is to be noted that the present invention is not limited to this example, but rather contemplates any other suitable exponentiation method as well.

In310, the computed exponentiation may be returned as the result. Depending upon the input, the result may be a single scalar result value, a list of multiple scalar result values, or a result vector including multiple values.

When compiled, the code for performing the logarithm or exponentiation computations may be implemented as software instructions, or as hardware-specific instructions. For example, each of302-310may be implemented in software, as a set of one or more hardware instructions that may be specific to the hardware being used for the computation, or as specialized hardware dedicated to performing these computations. Further improvements may be obtained by implementing part or all of the instructions in assembly code. Although modern compilers do a good job in optimizing the code, an assembler version would allow more precise control of the instructions that are actually used.

FIG. 4is an exemplary block diagram of a computing architecture400in which the processes shown inFIGS. 2 and 3may be implemented. In this example, the IBM® POWER8 architecture is shown. This architecture includes support for single instruction, multiple data (SIMD) processing. In an SIMD architecture, multiple processing elements perform the same operation on multiple units of data simultaneously. There are simultaneous (parallel) computations, but only a single process (instruction) at a given moment. The inputs to and outputs from SIMD processing may be vectors of multiple values. For example, processes200and300may be implemented so as to make use of short vector instruction units using SIMD vector instructions using the SIMD processing circuitry in the Vector Scalar Extension (VSX) processing unit402. As another example, processes200and300may be implemented in hardware, such as using existing hardware, or in specialized hardware, such as Exponentiation/Power/Logarithm Accelerator Unit404. Examples of architectures on which SIMD implementations may be used may include the IBM® POWER7 and POWER8 architectures INTEL® Streaming SIMD Extensions (SSE) or Advanced Vector Extensions (AVX), etc.

When implemented on an SIMD architecture, the instructions, including the loads, the store, the floating-point multiply-add, the floor, and the long int to double conversion may be SIMD vectorized. This provides the capability to process multiple logarithm or exponentiation computations at the same time, i.e., during the same CPU cycles.

Specialized processing hardware to perform the described processes may be included in or added to existing processing architectures, or included in newly-designed processing architectures. An example of a specialized processing hardware system500is shown inFIG. 5. System500is a hardware implementation of the computation performed in process200, shown inFIG. 2. Specialized processing element501may be circuitry adapted to receive and store an input representation of a real number “x”. Specialized processing elements502and504may be circuitry adapted to extract and store a mantissa “m” and exponent “z”, respectively, based on the real number x, for example, as described for204above. Specialized processing element506may be circuitry adapted to approximate a function of a logarithm of the mantissa m of the real number x. The approximation may be performed utilizing a polynomial, which may be based on the mantissa m, for example, as described for206above, or using another technique. Component508may be circuitry adapted to combine the approximate function of the logarithm of the mantissa m and the exponent z, for example, as described for208above. Component510may be circuitry that may obtain and store a result of the computation, for example, as described for210above.

Likewise, an example of a specialized processing hardware system600is shown inFIG. 6. System600is a hardware implementation of the computation performed in process300, shown inFIG. 3. Specialized processing element602may be circuitry adapted to receive and store an input value, for example, as described for302above. Specialized processing element604may be circuitry adapted to perform evaluation of a logarithm according to process200, and/or system600, for example, as described for304above. Specialized processing element606may be a multiplier circuit that may perform multiplication of factors to obtain an intermediate product, for example, as described for306above. Specialized processing element608may be circuitry adapted to perform exponentiation using a polynomial function or other technique to generate a result, for example, as described for308above. Specialized processing element610may be circuitry adapted to obtain and store a result of the computation, for example, as described for310above.

Systems500and600may be implemented using any electronic technology, such as discrete circuitry, programmable logic circuitry, field-programmable gate arrays (FPGA), programmable logic arrays (PLA), semi-custom integrated circuits, application-specific integrated circuits (ASIC), or any other electronic technology, in order to perform aspects of the present invention.

Accordingly, embodiments of the present disclosure are directed to a system for performing mathematical function evaluation. The system comprises a processing unit comprising logic comprising: a first set of hardware instructions configured to receive an input comprising a floating point representation of a real number and to extract a mantissa and an exponent; a second set of hardware instructions configured to approximate a function of a logarithm of a mantissa of the real number, wherein approximation is performed by utilizing a polynomial, and wherein the polynomial is based on the mantissa; and a third set of hardware instructions configured to combine the approximate function of the logarithm of the mantissa of the real number and the exponent for calculating a value comprising an approximate logarithm of the real number.

In embodiments of the above-described system, the polynomial is a Lagrange polynomial, an orthogonal polynomial, a Chebyshev polynomial, a Legendre polynomial, a trigonometric polynomial, a piecewise polynomial, a spline polynomial, a Hermite polynomial, or a Remez Polynomial.

In embodiments of the above-described system, the input further comprises a degree of the polynomial.

In embodiments of the above-described system, coefficients of the polynomial are precomputed.

In embodiments of the above-described system, the input is a single scalar input value, a list of multiple scalar input values, or an input vector including multiple values.

Embodiments of the above-described system further comprise a plurality of processing units, wherein each processing unit performs a same hardware instruction at a same time as the others of the plurality of processing units.

In embodiments of the above-described system, the input is a list of multiple scalar input values, or is an input vector including multiple values.

Embodiments are further directed to a computer-implemented method for using hardware instructions to accelerate evaluation of mathematical functions. The method comprises: executing a first set of hardware instructions to receive an input comprising a floating point representation of a real number and to extract a mantissa and an exponent; executing a second set of hardware instructions to approximate a function of a logarithm of a mantissa of the real number, wherein approximation is performed by utilizing a polynomial, and wherein the polynomial is based on the mantissa; and executing a third set of hardware instructions to combine the approximate function of the logarithm of the mantissa of the real number and the exponent for calculating a value comprising an approximate logarithm of the real number.

In embodiments of the above-described method, the polynomial is a Lagrange polynomial, an orthogonal polynomial, a Chebyshev polynomial, a Legendre polynomial, a trigonometric polynomial, a piecewise polynomial, a spline polynomial, a Hermite polynomial, or a Remez Polynomial.

In embodiments of the above-described method, the input further comprises a degree of the polynomial.

In embodiments of the above-described method, coefficients of the polynomial are precomputed.

In embodiments of the above-described method, the input is a single scalar input value, a list of multiple scalar input values, or an input vector including multiple values.

Embodiments of the above-described method further includes providing a plurality of processing units, wherein each processing unit performs a same hardware instruction at a same time as the others of the plurality of processing units.

In embodiments of the above-described method, the input is a list of multiple scalar input values, or an input vector including multiple values.

Embodiments are further directed to a system for performing mathematical function evaluation. The system comprises a processing unit comprising logic comprising: a first set of hardware instructions configured to receive an input comprising a floating point representation of a real number and a representation of a second number and to extract a mantissa and an exponent from the floating point representation of the real number; a second set of hardware instructions configured to approximate a function of a logarithm of a mantissa of the real number, wherein approximation is performed by utilizing a polynomial, and wherein the polynomial is based on the mantissa; a third set of hardware instructions configured to combine the approximate function of the logarithm of the mantissa of the real number and the exponent for calculating a value comprising an approximate logarithm of the real number; a fourth set of hardware instructions configured to multiply the approximate logarithm of the of the real number and the second number; and a fifth set of hardware instructions configured to exponentiate the product of the approximate logarithm of the of the real number and the second number for calculating a value comprising an approximation of the real number to the power of the second number.

In embodiments of the above-described system, the polynomial is a Lagrange polynomial, an orthogonal polynomial, a Chebyshev polynomial, a Legendre polynomial, a trigonometric polynomial, a piecewise polynomial, a spline polynomial, a Hermite polynomial, or a Remez Polynomial.

In embodiments of the above-described system, the input further comprises a degree of the polynomial.

In embodiments of the above-described system, coefficients of the polynomial are precomputed.

In embodiments of the above-described system, the input is a single scalar input value, a list of multiple scalar input values, or an input vector including multiple values.

Embodiments of the above-described system further comprises a plurality of processing units, wherein each processing unit performs a same hardware instruction at a same time as the others of the plurality of processing units.

In embodiments of the above-described system, the input is a list of multiple scalar input values, or an input vector including multiple values.

Embodiments are further directed to a computer-implemented method for using hardware instructions to accelerate evaluation of mathematical functions. The method comprises: executing a first set of hardware instructions configured to receive an input comprising a floating point representation of a real number and a representation of a second number and to extract a mantissa and an exponent from the floating point representation of the real number; executing a second set of hardware instructions configured to approximate a function of a logarithm of a mantissa of the real number, wherein approximation is performed by utilizing a polynomial, and wherein the polynomial is based on the mantissa; executing a third set of hardware instructions configured to combine the approximate function of the logarithm of the mantissa of the real number and the exponent for calculating a value comprising an approximate logarithm of the real number; executing a fourth set of hardware instructions configured to multiply the approximate logarithm of the of the real number and the second number; and executing a fifth set of hardware instructions configured to exponentiate the product of the approximate function of the logarithm of the mantissa of the real number and the second number for calculating a value comprising an approximation of the real number to the power of the second number.

In embodiments of the above-described method, the polynomial is a Lagrange polynomial, an orthogonal polynomial, a Chebyshev polynomial, a Legendre polynomial, a trigonometric polynomial, a piecewise polynomial, a spline polynomial, a Hermite polynomial, or a Remez Polynomial.

In embodiments of the above-described method, the input further comprises a degree of the polynomial.

In embodiments of the above-described method, coefficients of the polynomial are precomputed.

In embodiments of the above-described method, the input is a single scalar input value, a list of multiple scalar input values, or an input vector including multiple values.

Embodiments of the above-described method further comprise a plurality of processing units, wherein each processing unit performs a same hardware instruction at a same time as the others of the plurality of processing units.

In embodiments of the above-described method, the input is a list of multiple scalar input values, or an input vector including multiple values.

Embodiments are further directed to an apparatus comprising: a first at least one specialized processing elements specifically adapted to receive an input comprising a representation of a real number X; a second at least one specialized processing elements specifically adapted to extract a mantissa M and an exponent Z, based on the real number X, wherein the extraction of M and Z is obtained from a floating point representation; a third at least one specialized processing elements specifically adapted to approximate a function of a logarithm of the mantissa M of the real number X, wherein the approximation is performed utilizing a polynomial, and wherein the polynomial is based on the mantissa M; and a fourth at least one specialized processing elements specifically adapted to combine the approximate function of the logarithm of the mantissa M and the exponent Z for calculating a value comprising an approximate logarithm of the real number X; wherein the processing performed by the first, second, third, and/or fourth specialized processing elements for calculating the value comprising the logarithm is executed while utilizing an amount of memory that is significantly less than an amount of memory that would be used by a general standardized at least one processors for calculating the value.

In embodiments of the above-described apparatus, the polynomial is a Lagrange polynomial, an orthogonal polynomial, a Chebyshev polynomial, a Legendre polynomial, a trigonometric polynomial, a piecewise polynomial, a spline polynomial, a Hermite polynomial, or a Remez Polynomial.

In embodiments of the above-described apparatus, the input further comprises a degree of the polynomial.

In embodiments of the above-described apparatus, coefficients of the polynomial are precomputed.

In embodiments of the above-described apparatus, the input is a single scalar input value, a list of multiple scalar input values, or an input vector including multiple values.

Embodiments are further directed to an apparatus comprising: a first at least one specialized processing element specifically adapted to receive an input comprising a representation of a first real number X and a second number; a second at least one specialized processing element specifically adapted to extract a mantissa M and an exponent Z, based on the real number X, wherein the extraction of M and Z is obtained from a floating point representation; a third at least one specialized processing element specifically adapted to approximate a function of a logarithm of the mantissa M of the real number X, wherein the approximation is performed utilizing a polynomial, and wherein the polynomial is based on the mantissa M; a fourth at least one specialized processing element specifically adapted to combine the approximate function of the logarithm of the mantissa M of the real number X and the exponent Z for calculating a value comprising an approximate logarithm of the real number X; a fifth at least one specialized processing element specifically adapted to multiply the approximate logarithm of the real number X and the second number; and a sixth at least one specialized processing element specifically adapted to exponentiate the product of the of the real number X and the second number for calculating a value comprising an approximation of the real number X to the power of the second number; wherein the processing performed by the first, second, third, fourth, and/or fifth specialized processing elements for calculating the value comprising the logarithm is executed while utilizing an amount of memory that is significantly less than an amount of memory that would be used by a general standardized at least one processors for calculating the value.

In embodiments of the above-described apparatus, the polynomial is a Lagrange polynomial, an orthogonal polynomial, a Chebyshev polynomial, a Legendre polynomial, a trigonometric polynomial, a piecewise polynomial, a spline polynomial, a Hermite polynomial, or a Remez Polynomial.

In embodiments of the above-described apparatus, the input further comprises a degree of the polynomial.

In embodiments of the above-described apparatus, coefficients of the polynomial are precomputed.

In embodiments of the above-described apparatus, the input is a single scalar input value, a list of multiple scalar input values, or an input vector including multiple values.

The present invention may be a system, a method, and/or a computer program product at any possible technical detail level of integration. The computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present invention. The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device.