ELECTRONIC DEVICE AND METHOD OF OPERATING THE SAME

Provided herein is an electronic device including: a host configured to judge a possibility of occurrence of an SPO based on driving information of a transportation device, and determine an operation mode of a storage device to be an SPO protection mode or a performance mode based on the possibility of an SPO occurrence; a buffer memory device configured to temporarily store user data received from the host; a memory device configured to store the user data output from the buffer memory device; and a memory controller configured to set a size of the buffer memory device depending on the determined operation mode and to control the buffer memory device to output at least a part of the user data temporarily stored in the buffer memory device to the memory device based on an amount of the buffer memory device used.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean patent application number 10-2022-0030922, filed on Mar. 11, 2022, the entire disclosure of which is incorporated herein by reference.

BACKGROUND

1. Field of Invention

Various embodiments of the present disclosure relate to an electronic device, and more particularly to an electronic device including a host and storage device.

2. Description of Related Art

A storage device is a device which stores data under the control of a host device, such as a computer or a smartphone. The storage device may include a memory device in which data is stored and a memory controller which controls the memory device. Such memory devices are classified into a volatile memory device and a nonvolatile memory device.

The volatile memory device is a memory device in which data is stored only when power is supplied and in which stored data is lost when the supply of power is interrupted. Examples of the volatile memory device include a static random access memory (SRAM) and a dynamic random access memory (DRAM).

The nonvolatile memory device is a memory device in which stored data is retained even when the supply of power is interrupted. Examples of the nonvolatile memory device include a read only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable and programmable ROM (EEPROM), and a flash memory.

SUMMARY

Various embodiments of the present disclosure are directed to an electronic device for preparing for a sudden power-off (SPO) based on driving information of a transportation device, and a method of operating the electronic device.

An embodiment of the present disclosure may provide for an electronic device. The electronic device may include a host configured to judge a possibility of occurrence of a sudden power-off (SPO) based on driving information of a transportation device, and determine an operation mode of a storage device to be an SPO protection mode or a performance mode based on the possibility of occurrence of an SPO, a buffer memory device configured to temporarily store user data received from the host, a memory device configured to store the user data output from the buffer memory device, and a memory controller configured to set a size of the buffer memory device depending on the operation mode, and control the buffer memory device to output at least a part of the user data temporarily stored in the buffer memory device to the memory device based on an amount of the buffer memory device that is used.

An embodiment of the present disclosure may provide for a method of operating an electronic device, the electronic device including a storage device and a host that are provided in a transportation device. The method may include evaluating a possibility of occurrence of a sudden power-off (SPO) based on driving information of the transportation device, determining an operation mode of the storage device including an SPO protection mode or a performance mode based on the possibility of occurrence of an SPO, setting a size of a buffer memory device depending on the determined operation mode, and outputting at least a part of user data temporarily stored in the buffer memory device to a memory device based on an amount of the buffer memory device that is used.

An embodiment of the present disclosure may provide for an operating method of an apparatus mounted on a vehicle and including a host and a memory system. The operating method may include sensing, by the host, one or more of a mobility status of the vehicle and a power status of the memory system; and limiting, by the memory system and based on a result of the sensing, a maximum storage capacity of a buffer memory while operating only in response to a request from the host, wherein the buffer memory is configured to provide a memory device with data buffered therein, wherein the memory device is configured to store therein the provided data, and wherein the buffer memory and the memory device are included in the memory system.

DETAILED DESCRIPTION

Specific structural or functional descriptions of the embodiments of the present disclosure introduced in this specification or application are exemplified to describe embodiments according to the concept of the present disclosure. The embodiments according to the concept of the present disclosure may be practiced in various forms, and should not be construed as being limited to the embodiments described in the specification or application.

FIG.1is a diagram illustrating an electronic device according to an embodiment of the present disclosure.

Referring toFIG.1, an electronic device10000may include a storage device1000and a host2000. Also, the storage device1000may include a memory device100, a memory controller200, and a buffer memory device300.

The electronic device10000may be a device provided in a transportation device. In detail, the transportation device may be defined as a transportation means running on a road or rails. For example, the electronic device10000may be a device provided in an internal combustion engine vehicle equipped with an engine as a power source, a device provided in a hybrid vehicle equipped with an engine and an electric motor as a power source, or a device provided in an electric vehicle equipped with an electric motor as a power source. Tile transportation device may include a transportation means that is capable of supplying power, such as a vehicle, a train, a motorcycle, or an airplane, and the electronic device10000may be a device provided in the transportation device. The electronic device10000may be disposed inside/outside the transportation device or disposed in an area within the transportation device.

In accordance with an embodiment of the present disclosure, the electronic device10000may receive driving information (i.e., travel information) of the transportation device from a sensor provided in the transportation device or from external devices. For example, the transportation device may include various types of sensors for detecting an object, such as a camera, a radar, a lidar, an infrared sensor, an ultrasonic sensor, an impact sensor, and an acceleration sensor, and the electronic device10000may receive raw data from various types of sensors and identify the driving information of the transportation device, or may receive the driving information of the transportation device in the form of processed secondary data from various types of sensors. Also, the electronic device10000may judge the possibility of occurrence of a sudden power-off (SPO) based on the driving information of the transportation device, and may determine the operation mode of the storage device1000based on the possibility of occurrence of an SPO.

Here, the storage device1000may be a device which stores data under the control of the host2000, such as a mobile phone, a smartphone, an MP3 player, a laptop computer, a desktop computer, a game console, a display device, a tablet PC, or an infotainment system for transportation devices (e.g., an in-vehicle infotainment system).

The storage device1000may be implemented as any one of various types of storage devices depending on a host interface that is a scheme for communication with the host2000. For example, the storage device1000may be implemented as any one of various types of storage devices, for example, a solid state disk (SSD), a multimedia card such as an MMC, an embedded MMC (eMMC), a reduced size MMC (RS-MMC), or a micro-MMC, a secure digital card such as an SD, a mini-SD, or a micro-SD, a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a personal computer memory card international association (PCMCIA) card-type storage device, a peripheral component interconnection (PCI)-card type storage device, a PCI express (PCI-E) card-type storage device, a compact flash (CF) card, a smart media card, and a memory stick.

The storage device1000may be implemented in any one of various types of package forms. For example, the storage device1000may be implemented in any one of various types of package forms, such as package on package (POP), system in package (SIP), system on chip (SOC), multi-chip package (MCP), chip on board (COB), wafer-level fabricated package (WFP), and wafer-level stack package (WSP).

In accordance with an embodiment of the present disclosure, the storage device1000may include the memory device100, the memory controller200, and tile buffer memory device300.

The memory device100may store data or use the stored data. In detail, the memory device100may be operated in response to the control of the memory controller200. Further, the memory device100may include a plurality of memory dies, each of which may include a memory cell array including a plurality of memory cells which store data.

The memory device100may be implemented as a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate fourth generation (LPDDR4) SDRAM, a graphics double data rate (GDDR) SDRAM, a low power DDR (LPDDR) SDRAM, a Rambus dynamic random access memory (RDRAM), a NAND flash memory, a vertical NAND flash memory, a NOR flash memory device, a resistive RAM (RRAM), a phase-change random access memory (PRAM), a magnetoresistive RAM (MRAM), a ferroelectric RAM (FRAM), or a spin transfer torque RAM (STT-RAM).

In accordance with an embodiment of the present disclosure, the memory device100may store data received from the buffer memory device300under the control of tile memory controller200. Alternatively, the memory device100may transmit data stored in the memory device100to the buffer memory device300or to the memory controller200under the control of the memory controller200,

The memory controller200may control the overall operation of the storage device1000. In detail, when power is applied to the storage device1000, the memory controller200may run firmware (FW). The firmware (FW) may include a host interface layer (HIL) which receives a request input from the host2000or outputs a response to the host2000, a flash translation layer (FTL) which manages an operation between the interface of the host2000and the interface of the memory device100, and a flash interface layer (FIL) which provides a command to the memory device100or receives a response from the memory device100.

The memory controller200may receive data and a logical address (LA) from the host2000, and may translate the logical address into a physical address (PA) indicating the address of memory cells which are included in the memory device100and in which data is to be stored. The logical address may be a logical block address (LBA), and the physical address may be a physical block address (PBA).

The memory controller200may control the memory device100so that a program operation, a read operation or an erase operation is performed in response to a request received from the host2000. During a program operation, the memory controller200may provide a program command, a physical block address, and data to the memory device100. During a read operation, the memory controller200may provide a read command and a physical block address to the memory device100. During an erase operation, the memory controller200may provide an erase command and a physical block address to the memory device100.

The memory controller200may control the memory device100so that a program operation, a read operation or an erase operation is internally performed regardless of a request received from the host2000. For example, the memory controller200may control the memory device100so that a background operation, such as wear leveling, garbage collection, or read reclaim operation, is performed.

In accordance with an embodiment of the present disclosure, the memory controller200may control the memory device100to operate in an SPO protection mode under the control of the host2000. In the SPO protection mode, the memory controller200may control the memory device100to suspend any background operation being performed.

The buffer memory device300may temporarily store data, and may use the temporarily stored data. In detail, the buffer memory device300may be a device that temporarily stores the data to be stored in the memory device100in response to a request received from the host2000. The buffer memory device300may temporarily store data received from the host2000under the control of the memory controller200. The buffer memory device300may include an area in which write data to be stored in the memory device100is temporarily stored and an area in which data read from the memory device100is temporarily stored.

Also, when the capacity of the buffer memory device300reaches a certain level or higher, the memory controller200may control the buffer memory device300so that the data temporarily stored in the buffer memory device300is flushed into the memory device100. Here, the term “flush” may be an operation of outputting the data temporarily stored in the buffer memory device300to the memory device100, and thereafter deleting the data stored in the buffer memory device300. The data temporarily stored in the buffer memory device300may include mapping data between physical addresses and logical addresses of the memory device100. Furthermore, the data temporarily stored in the buffer memory device300may include user data received from the host2000.

In accordance with an embodiment of the present disclosure, the size of the buffer memory device300may be changed depending on the operation mode determined by the host2000. For example, when the host2000determines the operation mode of the storage device1000to be an SPO protection mode, the size of the buffer memory device300may be set to a first size, whereas when the host2000determines the operation mode of the storage device1000to be a performance mode, the size of the buffer memory device300may be set to a second size, larger than the first size. That is, the capacity to be allocated to the buffer memory device300may be changed depending on the operation mode determined by the host2000.

The host2000may be electrically connected to tile storage device10000, and may then exchange signals with the storage device1000. In detail, the host2000may receive raw data from various types of sensors provided in the transportation device and identify the driving information of the transportation device, or may receive the driving information of the transportation device in the form of processed secondary data from various types of sensors. Also, the host2000may judge the possibility of occurrence of a sudden power-off (SPO) based on the driving information of the transportation device. The host2000may determine the operation mode of the storage device1000based on the possibility of occurrence of an SPO. For this, the host2000may be implemented using at least one of application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, and electrical units for performing other functions.

Tile host2000may communicate with the storage device1000using at least one of various communication methods such as universal serial bus (USB), serial AT attachment (SATA), serial attached SCSI (SAS), high speed interchip (HSIC), small computer system interface (SCSI), peripheral component interconnection (PCI), PCI express (PCIe), nonvolatile memory express (NVMe), universal flash storage (UFS), secure digital (SD), multimedia card (MMC), embedded MMC (eMMC), dual in-line memory module (DIMM), registered DIMM (RDIMM), and load reduced DIMM (LRDIMM) communication methods.

FIG.2is a diagram illustrating a memory device according to an embodiment of the present disclosure.

Referring toFIG.2, a memory device100may include a memory cell array110, a peripheral circuit120, and a control logic130.

The memory cell array110may include a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz may be coupled to a row decoder121through row lines RL. Here, the row lines RL may include at least one source select line, a plurality of word lines, and at least one drain select line. Each of the memory blocks BLK1 to BLKz may be coupled to a page buffer group123through bit lines BL1 to BLn.

The peripheral circuit120may perform a program operation, a read operation, or an erase operation on a selected area of the memory cell array110under the control of the control logic130. That is, the peripheral circuit120may drive the memory cell array110under the control of the control logic130. For example, the peripheral circuit120may apply various operating voltages to the row lines RL and the bit lines BL1 to BLn or discharge the applied voltages under the control of the control logic130.

The peripheral circuit120may include the row decoder121, a voltage generator122, the page buffer group123, a column decoder124, an input/output circuit125, and a sensing circuit126.

The row decoder121may be coupled to the memory cell array110through the row lines RL. The row lines RL may include the at least one source select line, the plurality of word lines, and the at least one drain select line. In an embodiment, the word lines may include normal word lines and dummy word lines. Further, the row lines RL may further include a pipe select line.

The row decoder121may be operated in response to control of the control logic130. The row decoder121may receive a row address RADD from the control logic130. In detail, the row decoder121may decode the row address RADD. The row decoder121may select at least one of the memory blocks BLK1 to BLKz according to the decoded address. Further, the row decoder121may select at least one word line WL of the selected memory block so that voltages generated by the voltage generator122are applied to the at least one word line WL according to the decoded address.

For example, during a program operation, the row decoder121may apply a program voltage to a selected word line and apply a program pass voltage having a level lower than that of the program voltage to unselected word lines. During a program verify operation, the row decoder121may apply a verify voltage to a selected word line and apply a verify pass voltage higher than the verify voltage to unselected word lines. During a read operation, the row decoder121may apply a read voltage to a selected word line and apply a read pass voltage higher than the read voltage to unselected word lines.

In an embodiment, the erase operation of the memory cell array110may be performed on a memory block basis. During an erase operation, the row decoder121may select one memory block according to the decoded address, and may apply a ground voltage to word lines coupled to the selected memory block.

The voltage generator122may be operated under the control of the control logic130. More specifically, the voltage generator122may generate a plurality of voltages using an external supply voltage supplied to the memory device100under the control of the control logic130. For example, the voltage generator122may generate a program voltage, a verify voltage, a pass voltage, a read voltage, an erase voltage, etc. under the control of the control logic130. That is, the voltage generator122may generate various operating voltages Vop that are used for program, read, and erase operations in response to an operation signal OPSIG.

The page buffer group123may include first to n-th page buffers PB1 to PBn. The first to n-th page buffers PB1 to PBn may be coupled to the memory cell array110through the first to n-th bit lines BL1 to BLn, respectively. Further, the first to n-th page buffers PB1 to PBn may be operated under the control of the control logic130. In detail, the first to n-th page buffers PB1 to PBn may be operated in response to page buffer control signals PBSIGNALS. For example, the first to n-th page buffers PB1 to PBn may temporarily store data received through the first to n-th bit lines BL1 to BLn or may sense voltages or currents of the bit lines BL1 to BLn during a read or verify operation.

The column decoder124may transfer data between the input/output circuit125and the page buffer group123in response to a column address CADD. For example, the column decoder124may exchange data with the first to n-th page buffers PB1 to PBn through data lines DL or may exchange data with the input/output circuit125through column lines CL.

The input/output circuit125may transfer a command CMD and an address ADDR, received from the memory controller200, to the control logic130, or may exchange the data DATA with the column decoder124.

During a read operation or a verify operation, the sensing circuit126may generate a reference current in response to an enable bit signal VRYBIT, and may compare a sensing voltage VPB received from the page buffer group123with a reference voltage generated by the reference current and then output a pass signal PASS or a fail signal FAIL.

The control logic130may control the peripheral circuit120by outputting the operation signal OPSIG, the row address RADD, the page buffer control signals PBSIGNALS, and the enable bit VRYBIT in response to the command CMD and the address ADDR.

Further, the control logic130may determine whether the verify operation has passed or failed in response to the pass or fail signal PASS or FAIL.

FIG.3is a diagram illustrating a memory controller according to an embodiment of the present disclosure.

Referring toFIG.3, the memory controller200may include a buffer memory controller210and a memory control component220.

The buffer memory controller210may control the operation of a buffer memory device300. In detail, the buffer memory controller210may set the size of the buffer memory device300depending on the operation mode determined by a host2000.

For example, when the operation mode determined by the host2000is an SPO protection mode, the buffer memory controller210may set the size of the buffer memory device300to a first size. Further, when the operation mode determined by the host2000is a performance mode, the buffer memory controller210may set the size of the buffer memory device300to a second size larger than the first size. That is, the buffer memory controller210may control the size of the buffer memory device300by adjusting the size of an area allocated to temporary storage of the write data.

Further, the buffer memory controller210may control the buffer memory device300by comparing the set size of the buffer memory device300with the amount of the buffer memory device300that is used. In detail, when the amount of the buffer memory device300that is used reaches a preset value, the buffer memory controller210may control the buffer memory device300so that the data temporarily stored in the buffer memory device300is output to the memory device100. For example, in the case where the operation mode is an SPO protection mode, if the amount of the buffer memory device300that is used reaches the first size, the buffer memory controller210may control the buffer memory device300so that the data temporarily stored in the buffer memory device300is flushed. Alternatively, in the case where the operation mode is a performance mode, if the amount of the buffer memory device300that is used reaches the second size, the buffer memory controller210may control the buffer memory device300so that the data temporarily stored in the buffer memory device300is flushed.

In accordance with an embodiment of the present disclosure, the buffer memory controller210may control the buffer memory device300so that, in the SPO protection mode, the data temporarily stored in the buffer memory device300is transmitted to the memory device100at intervals of a regular period.

The memory control component220may control the operation of the memory device100. More specifically, the memory control component220may control the read, write, erase, and background operations of the memory device100.

Also, the memory control component220may control the operation of the memory device100depending on the operation mode determined by the host2000. For example, when the operation mode determined by the host2000is an SPO protection mode, the memory control component220may control the memory device100so that any background operation being performed by the memory device100is suspended. Here, the background operation may be an operation such as wear leveling, read reclaim, or garbage collection, which is performed regardless of a request received from the host2000so as to enhance the lifetime of the memory device100. Therefore, the memory control component220may control the memory device100so that the background operation being performed regardless of the request from the host2000is suspended and only an operation corresponding to the request from the host2000is performed.

FIG.4is a diagram illustrating a buffer memory device according to an embodiment of the present disclosure.

Referring toFIG.4, an example in which the buffer memory controller210controls the size of the buffer memory device300to a size corresponding to a first area310or a second area320is illustrated.

The buffer memory controller210may control the size of the buffer memory device300. For example, when an operation mode is an SPO protection mode, the buffer memory controller210may set the size of the buffer memory device300to a first size corresponding to the first area310. Also, when data received from the host2000at the first size is temporarily stored in the buffer memory device300, the buffer memory controller210may control the buffer memory device300so that the temporarily stored data is output to the memory device100.

Meanwhile, when the operation mode determined by the host2000is a performance mode, the buffer memory controller210may set the size of the buffer memory device300to a second size corresponding to the second area320. Also, when data received from the host2000at the second size is temporarily stored in the buffer memory device300, the buffer memory controller210may control the buffer memory device300so that the temporarily stored data is output to the memory device100.

The buffer memory controller210may allocate a larger area to write data in the performance mode than in the SPO protection mode, and may operate the storage device1000more efficiently in the performance mode than in the SPO protection mode. Further, the buffer memory controller210may allocate a smaller area to write data in the SPO protection mode than in the performance mode, and may store user data faster in the SPO protection mode than in the performance mode.

FIG.5is a diagram illustrating a host according to an embodiment of the present disclosure.

Referring toFIG.5, an example in which the host2000determines the operation mode of the storage device1000based on driving information is illustrated. The host2000may receive raw data from various types of sensors provided in the transportation device and identify the driving information of the transportation device, or may receive the driving information of the transportation device in the form of processed secondary data from various types of sensors. Here, the driving information may include a travel time, indicating the time elapsed since the commencement of travel by the transportation device, and a travel state, indicating the speed of the transportation device. Here, the transportation device may be defined as a transportation means running on a road or on rails. The electronic device10000may be a device provided in an internal combustion engine vehicle equipped with an engine as a power source, a device provided in a hybrid vehicle equipped with an engine and an electric motor as a power source, or a device provided in an electric vehicle equipped with an electric motor as a power source.

Also, the host2000may judge the possibility of occurrence of a sudden power-off (SPO) based on the driving information of the transportation device. Further, when there is the possibility of occurrence of an SPO, tile host2000may determine the operation mode of the storage device1000to be an SPO protection mode, whereas when there is no possibility of occurrence of an SPO, the host2000may determine the operation mode of the storage device1000to be a performance mode. The host2000may determine the operation mode of the storage device1000based on the possibility of occurrence of an SPO.

Here, the performance mode may be a mode in which an operation corresponding to a request from the host2000and an operation for the lifetime and management of the storage device1000are optimized and performed. The SPO protection mode may be a mode in which the operation corresponding to the request from the host2000is prioritized. That is, the SPO protection mode may be a mode in which user data is preferentially stored.

In accordance with an embodiment of the present disclosure, when the travel time of the transportation device is shorter than or equal to a preset time, the host2000may determine that there is the possibility of occurrence of an SPO because power corresponding to traveling of the transportation device may not be sufficiently secured. Further, the host2000may determine the operation mode of the storage device1000to be the SPO protection mode.

Alternatively, when the transportation device is not traveling, the host2000may judge that there is the possibility of occurrence of an SPO because power corresponding to traveling of the transportation device may not be sufficiently secured. That is, when the transportation device is in a stopped state, the host2000may determine the operation mode of the storage device1000to be the SPO protection mode.

When the voltage level of power supplied to the storage device1000is less than or equal to a preset level, the host2000may judge that there is the possibility of occurrence of an SPO. Further, the host2000may determine the operation mode of the storage device1000to be the SPO protection mode.

In addition, when it is judged that there is the possibility of occurrence of an SPO, the host2000may determine the operation mode of the storage device1000to be the SPO protection mode. Then, the host2000may request the storage device1000to operate in the determined operation mode.

FIG.6is a flowchart illustrating a method of operating an electronic device according to an embodiment of the present disclosure.

Referring toFIG.6, a method of operating an electronic device10000including a storage device1000and a host2000, which are provided in a transportation device, is illustrated. Here, the electronic device10000may be a device provided in the transportation device. In detail, the transportation device may be defined as a transportation means running on a road or on rails. The electronic device10000may be a device provided in an internal combustion engine vehicle equipped with an engine as a power source, a device provided in a hybrid vehicle equipped with an engine and an electric motor as a power source, or a device provided in an electric vehicle equipped with an electric motor as a power source. For example, the transportation device may include a vehicle, a train, a motorcycle, an airplane, etc., and the electronic device10000may be a device provided in the transportation device. The electronic device10000may be disposed inside/outside the transportation device or disposed in an area within the transportation device.

The electronic device10000may judge the possibility of occurrence of a sudden power-off (SPO) based on the driving information of the transportation device at step S610. In particular, the host2000included in the electronic device10000may receive driving information of the transportation device from sensors disposed outside/inside the transportation device, and may judge the possibility of occurrence of an SPO based on the driving information. Here, the driving information may include a travel time, indicating the time elapsed since the commencement of travel by transportation device, and a travel state, indicating the speed of the transportation device.

Next, the electronic device10000may determine the operation mode of the storage device, including an SPO protection mode or a performance mode, based on the possibility of occurrence of an SPO at step S620. In detail, when there is the possibility of occurrence of an SPO, the electronic device10000may determine the operation mode of the storage device1000to be the SPO protection mode. In contrast, when there is no possibility of occurrence of an SPO, the electronic device10000may determine the operation mode of the storage device1000to be the performance mode.

For example, when the travel time of tile transportation device is shorter than or equal to a preset time, the electronic device10000may determine the operation mode of the storage device1000to be the SPO protection mode. Alternatively, when the travel state of the transportation device is a stopped state, the electronic device10000may determine the operation mode of the storage device1000to be the SPO protection mode.

The electronic device10000may determine the operation mode of the storage device1000using power supplied to the storage device1000. In detail, when the voltage level of power supplied to the storage device1000is less than or equal to a preset level, the electronic device10000may determine the operation mode of the storage device1000to be the SPO protection mode.

Further, the electronic device10000may set the size of the buffer memory device300depending on the operation mode determined by the host2000at step S630. In detail, the electronic device10000may set the size of the buffer memory device300to a first size in the SPO protection mode, and may set the size of the buffer memory device300to a second size, larger than the first size in the performance mode.

Further, the electronic device10000may output user data temporarily stored in the buffer memory device300to the memory device100based on the amount of the buffer memory device300that is used at step S640. When the amount of the buffer memory device300that is used reaches the set size of the buffer memory device300, the electronic device10000may flush the data stored in the buffer memory device300.

Meanwhile, the electronic device10000may control the storage device1000so that, in the SPO protection mode, a background operation being performed regardless of a request from the host2000is suspended and only an operation corresponding to the request from the host2000is performed.

Furthermore, the electronic device10000may control the storage device1000so that, in the SPO protection mode, data temporarily stored in the buffer memory device300is output to the memory device100at intervals of a preset period.

FIG.7is a diagram illustrating a memory controller according to an embodiment of the present disclosure.

Referring toFIG.7, a memory controller1300may include a processor1310, a RAM1320, an error correction circuit (ECC circuit)1330, a ROM1360, a host interface1370, and a flash interface1380. The memory controller1300illustrated inFIG.7may be an embodiment of the memory controller200illustrated inFIG.3.

The processor1310may communicate with a host2000using tile host interface1370, and may perform a logical operation so as to control the operation of the memory controller1300. For example, in response to requests received from the host2000or an external device, the processor1310may load a program command, a data file, a data structure, etc., and may perform various types of operations or generate commands and addresses. For example, the processor1310may generate various commands required for a program operation, a read operation, an erase operation, a suspend operation, and a parameter setting operation,

Also, the processor1310may perform a function of a flash translation layer (FTL). The processor1310may translate a logical block address (LBA), provided by the host2000, into a physical block address (PBA) through the FTL. The FTL may receive the LBA and translate the LBA into the PBA using a mapping table. Examples of an address mapping method performed through the FTL may include various methods according to a mapping unit. Representative address mapping methods include a page mapping method, a block mapping method, and a hybrid mapping method.

Further, the processor1310may generate commands without receiving a request from the host2000. For example, the processor1310may generate commands for background operations such as operations for wear leveling of the memory device100and operations for garbage collection of the memory device100.

The RAM1320may be used as a buffer memory, a working memory or a cache memory of the processor1310. The RAM1320may store codes and commands that are executed by the processor1310. The RAM1320may store data that is processed by the processor1310. Further, in implementation of the RAM1320, the RAM1320may be implemented to include a static RAM (SRAM) or a dynamic RAM (DRAM).

The error correction circuit1330may detect errors and correct the detected errors during a program operation or a read operation. In detail, the error correction circuit1330may perform an error correction operation based on error correction code (ECC). Also, the error correction circuit1330may perform error correction encoding (ECC encoding) based on data to be written to the memory device100. The ECC-encoded data may be transferred to the memory device100through the flash interface1380. Further, the error correction circuit1330may perform error correction decoding (ECC decoding) on data received from the memory device100through the flash interface1380.

Tile ROM1360may be used as a storage unit which stores various types of information required for the operation of the memory controller1300. In detail, the ROM1360may include a map table, in which physical-logical address information and logical-physical address information may be stored. Further, the ROM1360may be controlled by the processor1310.

The host interface1370may include a protocol for performing data exchange between the host2000and the memory controller1300. In an embodiment, the host interface1370may communicate with the host2000through at least one of various interface protocols such as a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial-ATA protocol, a parallel-ATA protocol, a small computer system interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, and a private protocol.

The flash interface1380may communicate with the memory device100using a communication protocol under the control of the processor1310. In detail, the flash interface1380may transmit/receive commands, addresses, and data to/from the memory device100through a channel. For example, the flash interface1380may include a NAND interface.

FIG.8is a diagram illustrating a solid state drive (SSD) system according to an embodiment of the present disclosure.

Referring toFIG.8, an SSD system4000may include a host4100and an SSD4200. The SSD4200may exchange a signal SIG with the host4100through a signal connector4001, and may be supplied with power PWR through a power connector4002. The SSD4200may include an SSD controller4210, a plurality of flash memories4221to422n, an auxiliary power supply4230, and a buffer memory4240.

In an embodiment, the SSD controller4210may perform a function of the memory controller200, described above with reference toFIG.1. The SSD controller4210may control the plurality of flash memories4221to422nin response to the signal SIG received from the host4100. In an embodiment, the signal SIG may indicate signals based on the interfaces of the host4100and the SSD4200. For example, the signal SIG may be a signal defined by at least one of various interfaces such as universal serial bus (USB), multimedia card (MMC), embedded MMC (eMMC), peripheral component interconnection (PCI), PCI-express (PCI-E), an advanced technology attachment (ATA), serial-ATA (SATA), parallel-ATA (PATA), small computer system interface (SCSI), enhanced small disk interface (ESDI), integrated drive electronics (IDE), Firewire, universal flash storage (UFS), Wi-Fi, Bluetooth, and nonvolatile memory express (NVMe) interfaces.

The auxiliary power supply4230may be coupled to the host4100through the power connector4002. The auxiliary power supply4230may be supplied with power PWR from the host4100, and may be charged. The auxiliary power supply4230may supply the power of the SSD4200when the supply of power from the host4100is not smoothly performed. In an embodiment, the auxiliary power supply4230may be located inside the SSD4200or located outside the SSD4200. For example, the auxiliary power supply4230may be located in a main board, and may also provide auxiliary power to the SSD4200.

The buffer memory4240may function as a buffer memory of the SSD4200. For example, the buffer memory4240may temporarily store data received from the host4100or data received from the plurality of flash memories4221to422n, or may temporarily store metadata (e.g., mapping tables) of the flash memories4221to422n. The buffer memory4240may include volatile memories, such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or nonvolatile memories, such as FRAM, ReRAM, STT-MRAM, and PRAM.

FIG.9is a diagram illustrating a user system according to an embodiment of the present disclosure.

Referring toFIG.9, a user system5000may include an application processor5100, a memory module5200, a network module5300, a storage module5400, and a user interface5500.

The application processor5100may execute components included in the user system5000, an operating system (OS), a user program or the like. In an embodiment, the application processor5100may include controllers, interfaces, graphic engines, etc. for controlling the components included in the user system5000. The application processor5100may be provided in the form of a system-on-chip (SoC).

The memory module5200may function as a main memory, a working memory, a buffer memory or a cache memory of the user system5000. The memory module5200may include volatile RAMs such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDARM, LPDDR2 SDRAM, and LPDDR3 SDRAM or nonvolatile RAMs such as PRAM, ReRAM, MRAM, and FRAM. In an embodiment, the application processor5100and the memory module5200may be packaged based on a package-on-package (POP), and may then be provided as a single semiconductor package.

The network module5300may communicate with external devices. In an embodiment, the network module5300may support wireless communication, such as code division multiple access (CDMA), global system for mobile communication (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution (LTE), Wimax, wireless LAN (WLAN), UWB, Bluetooth, or Wi-Fi. In an embodiment, the network module5300may be included in the application processor5100.

The storage module5400may store data. For example, the storage module5400may store data received from the application processor5100. Alternatively, the storage module5400may transmit the data stored in the storage module5400to the application processor5100. In an embodiment, the storage module5400may be implemented as a nonvolatile semiconductor memory device, such as a phase-change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a NAND flash memory, a NOR flash memory, or a NAND flash memory having a three-dimensional (3D) structure. In an embodiment, the storage module5400may be provided as a removable storage medium (removable drive), such as a memory card or an external drive of the user system5000.

In an embodiment, the storage module5400may include a plurality of nonvolatile memory devices, each of which may be operated in the same manner as the memory device, described above with reference toFIG.1. The storage module5400may be operated in the same manner as the storage device1000, described above with reference toFIG.1.

The user interface5500may include interfaces which input data or instructions to the application processor5100or output data to an external device. In an embodiment, the user interface5500may include user input interfaces such as a keyboard, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyroscope sensor, a vibration sensor, and a piezoelectric element. The user interface5500may include user output interfaces such as a liquid crystal display (LCD), an organic light-emitting diode (OLED) display device, an active matrix OLED (AMOLED) display device, an LED, a speaker, and a monitor.

In accordance with the present disclosure, there are provided an electronic device for preparing for a sudden power-off (SPO) based on driving information of a transportation device, and a method of operating the electronic device.