Semiconductor structure, an integrated circuit including a semiconductor structure and a method for manufacturing a semiconductor structure

A monolithic semiconductor structure includes a stack of layers. The stack includes a substrate; a first layer made from a first semiconductor material; and a second layer made from a second semiconductor material. The first layer is situated between the substrate and the second layer and at least one of the first semiconductor material and the second semiconductor material contains a III-nitride material. The structure includes a power transistor, including a body formed in the stack of layers; a first power terminal at a side of the first layer facing the second layer; a second power terminal at least partly formed in the substrate; and a gate structure for controlling the propagation through the body of electric signals between the first power terminal and the second power terminal. The structure further includes a vertical Schottky diode, including: an anode; a cathode including the substrate, and a Schottky barrier between the cathode and the anode, the Schottky barrier being situated between the substrate and a anode layer in the stack of layers.

FIELD OF THE INVENTION

This invention relates to a semiconductor structure, an integrated circuit including a semiconductor structure and a method for manufacturing a semiconductor structure.

BACKGROUND OF THE INVENTION

III-nitride based power transistors are known in the art. III-nitride power semiconductor devices are used for power applications, for example to supply power, due to their high breakdown voltage and low on-resistance. However, a disadvantage of the known III-nitride power semiconductor devices is that they are discrete devices which need to be connected to other electronic components in order to form an electronic circuit. Accordingly, the resulting circuit is composed of several dies connected to each other and therefore has a relatively large footprint and is relatively complex to manufacture.

United States Patent Application Publication US 2006/0175633 discloses a monolithic integrated III-nitride power device which includes a hetero-junction III-nitride body having a first III-nitride semiconductor layer and a second III-nitride semiconductor layer having a band gap different from that of the first III-nitride layer disposed over the first III-nitride layer. A first power electrode is electrically connected to the second III-nitride layer, as well as a second power electrode. A gate structure is disposed over the second III-nitride layer between the first power electrode and the second power electrode, and a Schottky electrode is present which is in Schottky contact with the second III-nitride layer.

However, it is implied in this publication that the second III-nitride semiconducting layer is undoped, and thus has the intrinsic electrical properties of the III-nitride used, since a high resistivity of the second III-nitride semiconducting layer is required for a hetero-junction. However, such an intrinsic layer is not suited for a Schottky diode, which requires a low current resistance in the forward bias condition.

Accordingly, to obtain a properly working power device, the monolithic integrated III-nitride power device disclosed in US 2006/0175633 has to be modified to provide a conducting region in the second III-nitride semiconducting layer in the region of the Schottky diode, i.e. by doping.

SUMMARY OF THE INVENTION

The present invention provides a semiconductor structure, an integrated circuit including a semiconductor structure and a method for manufacturing a semiconductor structure as described in the accompanying claims.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring toFIG. 1an example of a monolithic semiconductor structure is shown therein. The monolithic semiconductor structure includes a stack of layers. The shown stack of layers comprises a substrate1, a first layer3made from a first semiconductor material and a second layer4made from a second semiconductor material. One or more of the first semiconductor material and the second semiconductor material may contain a III-nitride material. The first layer3is situated between the substrate1and the second layer4and more in particular in this example is positioned directly adjacent and in direct contact with the second layer4at a second layer side301of the first layer3. Although the first layer3may be situated directly adjacent and in direct contact with the substrate1at a substrate side302of the first layer3, in the shown example the first layer3is separated from the substrate1by one or more intermediate layers2,11.

The structure includes a power transistor200. The power transistor200may be any suitable type of power transistor. The power transistor200may for example be a hetero-structure field effect transistor (HFET), which may also be referred to as a high electron mobility transistor (HEMT), as explained in more detail below. The HFET may for example be implemented as a high power switch which can control currents at high voltages, for example at voltages of 50 V or more and/or 1500 V of less.

As shown inFIG. 1, the power transistor200includes a body201formed in the stack of layers. A first power terminal5of the power transistor200is present at the second layer side301, which faces the second layer4, of the first layer3. A second power terminal7of the power transistor200is, at least partly, formed in the substrate1. The power transistor200further includes a gate structure6, for controlling the propagation, through the body, of electric signals between the first power terminal5and the second power terminal7.

In the shown example, the distance A between the gate structure6and the first power terminal5is (much) more than the distance B between the gate structure6and the second power terminal7. For example, the distance between the gate structure6and the first power terminal5, in this example the drain of the power transistor, may be more than 10 micrometer, such as 15 micrometer or more, for example between 15 and 20 micrometer and the distance between the gate structure6and the second power terminal7, e.g. in this example the source of the power transistor, may be 10 micrometer or less, such as about 2 micrometer or less. A higher voltage difference may be applied between the gate structure6and the first power terminal5than between the gate structure6and the second power terminal7. The voltage difference between the gate structure6and the first power terminal5may be 1500 V or less, for example several hundreds of volts or less, such as 600 V or less, whereas the voltage difference between the gate structure6and the second power terminal7, e.g. the source in this example, may be 30 V or less, such as 10 V or less.

The power terminals5,7and the gate structure may have any shape suitable for the specific specification. In the example shown inFIGS. 1 and 2, the first power terminal5is a loop which encloses the gate structure6and the second power terminal7, whereas the gate structure is a loop (enclosed by the first power terminal5) which encloses the second power terminal7. As shown inFIG. 2, the loops may be closed loops, however the loops may alternatively be open or be interrupted for instance for trace route conducting lines to pass through. Furthermore, in the example ofFIGS. 1 and 2, the loops are rectangular; however it will be apparent that other shapes, such as hexagonal, circular or elliptical may be used as well. Also, in the examples the loops and the second power terminal are concentric, and the configuration has a 180 degrees rotational symmetry. However it is also possible that the gate structure and/or the second power terminal are positioned eccentric with respect to the first power terminal and that the configuration is asymmetric or symmetric in another manner, e.g. mirror symmetric or otherwise.

As shown inFIG. 1, the monolithic semiconductor structure may further include a Schottky diode, in this example implemented as a vertical Schottky diode100. The vertical Schottky diode100includes an anode104and a cathode which includes the substrate.

A Schottky barrier103is present between the cathode and the anode104. The Schottky barrier103is situated between the substrate1and an anode layer in the stack of layers, in which the anode104is formed. In the example, the Schottky barrier103a metal-semiconductor interface extending in a lateral direction, i.e. parallel to the substrate layer1, between the anode layer and a part of a semiconductor layer101which is included in the cathode. In the example, the anode layer is a top layer of the stack of layers, formed from a metallic material and the Schottky barrier103is level with the exposed surface of a dielectric layer10, which in a vertical direction (from the substrate towards the top layer) lies below the anode layer. However, it will be apparent that the Schottky barrier may be situated at another position in the stack of layers, and for example be below the surface of the dielectric layer10, for example when the anode layer is partially recessed in the layers below the top layer.

The cathode may extend through at least a part of the first layer3and/or the second layer4, and, as shown inFIG. 1, may include a recess which extends through the layers3,4and is filled with one or more diode layers101,102of suitable materials. As shown, the recess may extend to an intermediate layer11situated between the substrate1and the second layer4, and be in direct contact with the intermediate layer11. The intermediate layer11may provide for an electrical path between the recess and the substrate1. As shown in the example, the intermediate layer11may for example be a conducting layer in direct contact with the substrate1. However, alternatively the recess may extend to the substrate1, e.g. through any intermediate layers between the layers3,4and the substrate1, and the material filling the recess may be in direct contact with the substrate1,

The cathode103includes the substrate1and the Schottky barrier is situated between the substrate and the anode layer in the stack of layers. Thus, the Schottky diode can be manufactured in the same steps as the parts of the transistor200situated in the stack of layers. More in particular, as explained below in more detail, the vertical Schottky diode100may for example be manufactured simultaneously with the second power terminal7.

As can be seen inFIGS. 1 and 2, an insulating region12may be present between the semiconductor region and the body which electrically isolates the semiconductor region of the cathode from the body of the transistor. In the insulating region12at least the second layer4may be made of a not intentionally doped semiconductor material, thereby obtaining a highly resistive area, whereas in areas where a good conductivity is desired the second layer4may be doped. As shown inFIG. 7, the insulting region12may be formed by an isolating trench120, for example by locally removing (in a part of the insulating region) the layer4completely and layer3partially and filling with a suitable dielectric the recess thus formed in the insulating region12. However, in addition or alternatively, the isolation between the power transistor and Schottky diode may be implemented using other suitable isolation techniques, such as a junction isolation, a dielectric isolation, or an impurity implanted isolation such as oxygen implantation.

Referring toFIGS. 3-6, the monolithic semiconductor structure may for example be manufactured with a method for manufacturing a monolithic semiconductor structure, which includes providing a stack of layers. As shown inFIG. 3, the stack may include: a substrate1; a first layer3made from a first semiconductor material; and a second layer4made from a second semiconductor material. The stack of layers may include additional layers, such as intermediate layers2,11, dielectric layer10, an anode layer or other suitable layers. The layers of the stack may be provided before the transistor and/or the Schottky diode are provided. However, alternatively one or more layers of the stack may be provided during or after providing the transistor200and/or the Schottky diode100.

The substrate1may be conductive and provide an electrical path, e.g. as shown inFIG. 1to the source of the transistor200(or as shown inFIG. 7to the drain of the transistor200) and/or to the cathode102of the Schottky diode100. The substrate1may for example be Ohmic. The substrate1may be made from a substrate semiconductor material containing mono-crystalline silicon or another suitable substrate material. The substrate1may for example be a semiconductor doped to enhance the substrate conductivity, e.g. in case of a (mono-crystalline) silicon layer the substrate1may be provided with a n-type doping, such as arsenic, phosphorus or another suitable type of dopant.

The first layer3and the second layer4may be implemented in any manner suitable for the specific implementation. One or more of the first semiconductor material and the second semiconductor material may contain a III-nitride material, such as (alloys, compounds or mixtures of) a nitride of Al and/or In and/or Ga. It has been found that III-nitride materials are suitable for both the power transistor and the Schottky diode, and as explained below in more detail allow the manufacturing of the Schottky diode without additional steps. The III-nitride material or materials used may for example be one or more materials in the group consisting of: binary III-nitride material, ternary III-nitride material, quaternary III-nitride material, GaN, AlGaN (for example having an Al concentration of 20% or more and/or 30% or less), InGaN, AIInN, AIInGaN, and epitaxial grown III-nitride material. A first layer3of GaN and a second layer4of AlGaN have been found to be a combination of materials suitable for both a HEMT and a Schottky diode. The first layer3may for example have a thickness of at least 1 micrometer, and as much as 6 micrometers.

The first layer3and the second layer4may for example be implemented in a manner suitable to form a hetero-junction. As shown inFIG. 3, the first layer3and the second layer4may be provided such that an interface8is obtained at which the first layer3and the second layer4are in contact with each other. Along the interface8, when the power transistor is in operation, a two dimensional electron gas (2DEG)9may be formed in a part of the first layer3directly adjacent to the interface8. It will be understood that the term ‘two dimensional electron gas’ as used in this application, this includes a gas of electrons able to move in two dimensions, but tightly confined in the third dimension, as well a similar gas of holes. As shown in the FIGs, the layers3,4and the interface8may be substantially planar and be oriented parallel to a top surface of a wafer (which in the shown FIGs. is formed by the top surface of the substrate1). The wafer may, as shown, be of a mono-layer substrate. However alternatively, the wafer may be of a multi-layer substrate.

The first semiconductor material and the second semiconductor material used may for example be selected from materials suitable for a hetero-junction. The second semiconductor material may for example have a band-gap different from a band-gap of the first semiconductor material. Thereby, the bandgaps at the interface8will bend, as is generally known in the art, and a potential well may be obtained in which the 2DEG9can be formed. The first layer3may for example be made from a not intentionally doped semiconductor material. Thereby, the first layer3can be provided with a high resistivity and the leakage current of the HFET in the off-state may be reduced. Without wishing to be bound to any theory, it is believed that the high resistivity confines the electrons of the 2DEG9within a sheet shaped region of the first layer3at the interface8thus inhibiting a leakage through parts of the first layer3which are remote from the interface8. In addition, the 2DEG can provide a high sheet carrier density (for example as high as 8.1012cm−2or more) and may have a high electron mobility (for example in the range of 103·cm2/V or more). Furthermore, the 2DEG can have a low on-state resistance, for example a resistance as low as 3 m·OhmCm2or less may be obtained. The first layer3may for example have a thickness of 1 micrometers or more, such as 2 micrometers or more, and/or 10 micrometers or less, such as between 2-6 μm. The second layer4may for example have a thickness of less than 0.1 micrometer, such as several tenths of nanometers, such as 20 nm to 30 nm.

The second layer4may for example be implemented as a tunnelling layer which, after manufacturing of the structure, separates the first power terminal5from the first layer3and which, when the transistor is operated after manufacturing of the semiconductor structure, allows a conduction between the first power terminal5and the 2DEG9via tunnelling of charge carriers through the second layer4. For example, the second layer4may be an AlGAN layer between the power terminal5and the first layer3which has a thickness of about 300 Angstrom. The AlGaN layer having aluminium composition for example between 20% and 30%. It should be apparent that other layers may be present. Alternatively, as shown in the examples, the first power terminal5may also be in direct contact with the 2DEG9and for example be provided in the second layer4which extends to at least the top surface of the first layer3or into the first layer3(for example by locally etching a recess in the second layer4to a desired depth and thereafter depositing the terminal layer(s) or/and by thermal diffusion of a suitable material, e.g. dopant, in the second layer4). Alternatively, the first power terminal5may also be in contact with the 2DEG9through a conductive path made by local thermal diffusion of metal and/or residual doping in the second layer4in order to make the second layer4electrically conducting in the area of the conductive path. The conductive path may also be provided in another way, such as by dopant implant followed by thermal diffusion in the area of the conductive path, for example by an implantation and subsequent activation.

It should be noted that the 2DEG9may also be formed using other mechanisms and that other (combinations of) materials may be used to form the heterojunction. The second semiconductor material may for example have a lattice constant different from a lattice constant of the first semiconductor material, and the first semiconductor material may exhibit a piezoelectric polarization in a transversal direction from the interface towards the substrate. Thereby, due to the different lattice constant, the first semiconductor material will be stressed or strained and the first layer3will be charged at the interface8. Thereby, the density of electrons at the interface8may be increased.

As shown in e.g.FIG. 3, the stack of layers may include additional layers such as a nucleation layer11. As shown, the nucleation layer11may be directly adjacent and in contact with the substrate1and act as a base layer for epitaxial layers grown on the nucleation layer and which e.g. may have a crystal structure and lattice constant which allows a growth of the epitaxial layers thereon. In addition, the nucleation layer11may serve to compensate for a mismatch between the crystal structure and/or lattice constant of the substrate1and the crystal structure and/or lattice constant of the layers grown on the nucleation layer11. For example, the first layer3and second layer4may be epitaxial layers grown using a suitable epitaxial process.

The nucleation layer11may e.g. be of a conductive material or provide otherwise an electrical connection to conductive parts (such as the anode101and/or the second power terminal7) above the nucleation layer11, e.g. via tunnelling of electrons through the nucleation layer. The nucleation layer11may for example be made electrically conducting by the diffusion of elements from the substrate1into the nucleation layer11during growth of the nucleation layer and/or due to a disordered orientation of the crystals of the nucleation layer11, e.g. the nucleation layer may be polycrystalline. The layers grown on the nucleation layer11, such as the transition layer2or the first semiconductor layer3may be mono-crystalline or less disordered and/or contain less or no elements from the substrate and accordingly be highly resistive.

The nucleation layer11may for example be less than 100 nm thick, such as for example be 50 nm or less. A suitable thickness, e.g. for an AlN nucleation layer on a substrate (such as on a monocrystalline substrate layer), is found to be between 35 nm and 45 nm, such as 40 nm.

The stack of layers as shown inFIG. 3may further include, for example, a transition layer2provided between the first layer3and the substrate1. The transition layer2serves to gradually improve the crystal quality of the material grown by epitaxy to enable the first layer3to be a monocrystal with a low dislocation density (as low a 5.109cm−2). In addition, the transition layer2may also participate to electrically isolate the layers above the transition layer2from the substrate1. In the shown example, the transition layer2is grown on the nucleation layer11. The transition layer2may for example be an epitaxial layer. A suitable composition for the transition layer2has been found to be alternate layers of GaN/AlN. Also, the transition layer may be made of AlGaN with a graded Al composition, for example from AlN (i.e. no Ga added) to GaN (i.e. no Al added) in a direction from the substrate to the second layer4. The transition layer2, or some sub-layers thereof, may be doped to increase their resistivity or create p-type regions, for example with Fe; Mg or C or components or alloys, compounds or mixtures thereof.

A power transistor200may be provided in the stack. The process of providing the power transistor may overlap for some parts with the process of providing the stack of layers. In the example illustrated inFIGS. 3-6, the power transistor200is provided after the first and second layers3,4have been provided, but overlaps with the provision of other layers, e.g. dielectric layer10, anode layer104. In this example, the transistor body201is defined in the stack of layers by the position of the power terminal5, and a channel70which is part of the second power terminal7and provides an electrically conducting path between a second power terminal side of the transistor body201and the substrate1. In this example, the body201includes a hetero-junction structure which includes the interface8at which the first layer3and the second layer4are in contact with each other and along which interface8, when in operation, the 2DEG is formed.

As illustrated inFIGS. 3 and 4, for example, a second power terminal7may be provided at least partly in the substrate1. The second power terminal7may for example include the channel70, for example a semiconducting or metallic channel. The channel70may for example be provided by locally removing a part of the stack of layers, in order to obtain an recess through at least the first and second layers3,4, for example using plasma etching. The recess may for example extend from an exposed surface of the stack to the nucleation layer11or to the substrate1.

As shown inFIG. 5, the recess may then be filled with a suitable material, such as a doped semiconductor material, in order to provide an electrical path between the body201and the substrate1. The recess may be completely filled with a suitably doped semiconductor layer, such as n-doped GaN. The recess may for instance be filled with a doped material, e.g. an n-type doping, to be highly conductive, while the second layer4may be non-intentionally doped. Thereby the leakage current when the gate terminal is biased e.g. at a negative voltage of for example −5V or less, may be reduced.

In the example ofFIG. 5, the recess is partially filled with a conducting layer72which is in direct contact with a surface of the stack of layers exposed in the recess in this phase of the processing is, e.g. in this example nucleation layer11. Alternatively, when the recess extends through the nucleation layer11or when the nucleation layer11is not present, the exposed surface may be of the substrate1. The layer72may for example be a doped semiconductor layer, for example a III-nitride material, such as n-doped GaN and for example be grown by epitaxial regrowth, for example using Molecular beam epitaxy (MBE), e.g. in case of vertical regrowth, or Metal-Organic-Chemical-Vaport-Epitaxy (MOCVD), e.g. in case of both vertical and lateral regrowth). After growing the first conducting layer72, the recess may then be filled completely by one or more additional layers. For example, the recess may then, as shown inFIG. 5, be filled completely by growing another layer71, made of a semiconductor material or of a metallic material. In case the layer71is made of a semiconductor material, the layer72may be made of the same type of material but with a different concentration of dopants. For instance, the layers72,71may both be made of n-type doped GaN, e.g. obtained by epitaxial regrowth, the lower layer72having a higher (N+) concentration than the concentration (N−) of the doping in the top layer71. For example, the lower layer may have a concentration which is several orders of magnitude higher than the concentration in the top layer. Suitable values have for example found to be a doping concentration of 1019Cm−3in the lower layer and a doping concentration of 1016Cm−3in the top layer71.

As illustrated inFIG. 6, e.g. after forming the second power terminal7, a first power terminal5may be formed at a side of the first layer3facing the second layer4. As explained above, the first power terminal5may for example be separated from the first layer3by the second layer4or be provided in direct contact with the first layer3, e.g. by etching the second layer4and subsequent growth of a suitable material in the thus formed recess. The first power terminal may for example be made of a metal or other suitable conducting material, such as a stack of layers of Al/Ti, Ni/Al/Ti, Mo/Al/Ti or the like. The first power terminal5may for example be provided by locally etching the second layer4to a suitable depth, e.g. to the first layer3, in order to obtain a recess which is in direct contact with the 2DEG9. Subsequently, a suitable material, e.g. a metal, may be grown in the recess. Alternatively, as shown inFIG. 6, the first power terminal5may be obtained by locally growing a conducting material on the second layer4, which is electrically, but indirectly, in contact with the 2DEG9, for example by a tunnelling path through the second layer4. Also, the first power terminal5may be obtained by locally diffusing, e.g. thermally, or otherwise insert elements in the first layer3and/or second layer4. Thereafter the intermediate product for the semiconductor structure may be subjected to a rapid thermal anneal to built ohmic terminals with low contact resistance.

Before, during or after the formation of the first power terminal, a gate structure6may be formed, which can control the propagation through the body of electric signals between the first power terminal5and the second power terminal7.

The gate structure6may be implemented in any manner suitable for the specific implementation. As shown, the gate structure may be provided at a side of the second layer4opposite to an interface side at which the second layer4is in contact with the first layer3. In the examples, the gate structure6includes a patterned gate layer60which is separated from the second layer4by a dielectric layer10. The gate layer60may for example be made of a conducting material, including for example a metal, such as a chemical compound or alloy including Au, Ti, Al, Ag, Cr, W, Pt, Ni, Pa or In, or a semiconductor material, such as poly-silicon, optionally provided with a suitable doping. The dielectric layer10may for example made from silicon nitride or silicon-oxide or tantalum oxide, for example be made of Si3N4, SiO2, Ta2O5or other suitable type of isolator.

The gate layer60may be in capacitive contact with the second layer4and/or the first layer3. Alternatively, the gate layer60may be in direct contact with the second layer4or the first layer3to form a Schottky type potential barrier. In such case, the gate layer60may be a multi-layer structure. The multi-layer structure may for example include two or more metal layers, such as a Ti/Au; Ti/Al or Ni/Au, Ni/Al or Pt/Ti/Au, Pt/Al, Ir/Au, Ir/Al or Pt/Au, Pt/Al multilayer.

The gate structure6may for example be provided by depositing a dielectric layer10on the exposed surface of the stack of layers and locally etching the dielectric layer10to a certain depth, e.g. to the second layer4in case of a direct contact gate structure, or to a depth less than the thickness of the dielectic layer10in case of a capacitive contact. As shown, in the thus obtained recess, the gate layer60may be deposited. As shown, the thickness of the gate layer60may exceed the depth of the recess. The dielectric layer may for example include a passivation layer and/or other elements or layers

Simultaneously with the power transistor200, a vertical Schottky diode100may be provided. As explained below in more detail, the forming of the vertical Schottky diode may include: forming an anode which extends through at least a part of the first layer and/or the second layer; forming a cathode including the substrate, and forming a Schottky barrier between the cathode and the anode.

As illustrated inFIGS. 3 and 4, for example, the vertical Schottky diode may for example be provided by removing, simultaneously with the formation of a recess for the second power terminal7, locally a part of the stack of layers to obtain a recess through at least the first and second layers3,4, for example using plasma etching. The recess may for example extend from a top surface of the stack to the nucleation layer11or to the substrate1. As shown inFIG. 5, the recess may then be filled with a suitable anode semiconductor material similar to, and at the same time as, that of the recess in which the second power terminal7is formed, such as a doped semiconductor material, in order to form (a part of) the cathode of the Schottky diode100. The recess may, for example, be completely filled with a suitably anode semiconductor material, such as a doped semiconductor layer, such as n-doped GaN, to extend the cathode into the recess. The top surface of the semiconductor layer may be covered with a metal layer which forms the anode104, in which case the Schottky barrier can be situated between the semiconductor layer and the metal layer.

InFIG. 5, the recess is partially filled with a semiconductor layer102which is in direct contact with an surface of the stack of layers exposed in the recess, e.g. in this example nucleation layer11. Alternatively, when the recess extends through the nucleation layer or when the nucleation layer is not present, in which case the exposed surface may be of the substrate1. The semiconductor layer conducting layer102may for example be a doped semiconductor layer, such as n-doped GaN and for example be grown by epitaxial regrowth using Molecular beam epitaxy (vertical regrowth) or Metal-Organic-Chemical-Vapor-Epitaxy (lateral and vertical regrowth).

After growing the semiconductor layer102, the recess may then be filled completely by one or more additional layers. For example, the recess may then, as shown inFIG. 5, be filled completely by growing another layer101, made of a semiconductor material or a metallic material, for example a III-nitride material, such as doped GaN. In case the layer101is metallic, the Schottky barrier will be situated between the layers101,102and the layer101is then part of the anode. As shown inFIG. 6, in case the layer101is a semiconductor layer, the Schottky barrier can be obtained by depositing on the exposed surface of layer101a metallic layer with a shape and size suitable to form the anode. The metallic layer may for example be the same as the gate layer60, and be patterned in the anode104above the recess.

In case the layer101is made of a semiconductor material, the layer102may be made of the same type of material but with a different concentration of dopants. For instance, the conducting layer101and the semiconductor layer102may both be made of n-type doped GaN, e.g. obtained by epitaxial regrowth, the conducting layer102having a higher (N+) concentration than the semiconductor layer101(indicated as N-). For example the lower layer may have a concentration which is several orders of magnitude higher than the concentration in the top layer101. Suitable values have for example found to be a doping concentration of 1019Cm−3in the lower layer102and a doping concentration of 1016Cm−3in the top layer101. The doping concentrations of layers102and101determine the vertical breakdown voltage and current resistance of the Schottky diode. For example a breakdown voltage of 600V or more, for example up to 1500V, and current resistance of few milli-Ohms or less may be obtained.

Referring toFIG. 8, an equivalent circuit of the example of a semiconductor structure is shown. As shown, the equivalent circuit includes a power transistor200connected in series with a diode100. More specific, the cathode of the diode is connected to the source of the power transistor. The drain of the power transistor100may for instance be connected to a ground or a positive potential, while the source may, e.g., be connected to a negative potential or to a ground. As shown inFIG. 7, an inductance L1may be connected, in parallel to the diode, to the source of the power transistor. The diode100may then be used as a flyback diode which inhibits the flyback current caused by the inductance when the power transistor200is switched off, i.e. the current flow through the power transistor200is interrupted. It will be apparent that the semiconductor structure may also be used in other applications, and that the shown circuit is just an example. The circuit may for example be implemented as an integrated circuit, for example by providing the inductance L1and the semiconductor structure in the same integrated circuit package or by providing the inductance L1and the semiconductor structure on the same die.

In the example ofFIGS. 3-6, the second power terminal may be the source of the transistor, and the first power terminal the drain and as explained above the distance between the second power terminal7and the gate6may be less than the distance between the first power terminal5and gate6.

Referring toFIGS. 7 and 9, alternatively, the first power terminal5may be the source, while the second power terminal7may be the drain. The distance A between the first power terminal5and the gate6may then be less than the distance B between the second power terminal7and gate6. The distance between the gate structure6and the first power terminal5may for example be 10 micrometer or less, such as about 2 micrometer or less and the distance between the gate structure6and the second power terminal7, e.g. in this example the source of the power transistor, may be more than 10 micrometer, such as 15 micrometer or more. The voltage difference between the gate structure6and the first power terminal5may then may be 30 V or less, such as 10 V or less, whereas the voltage difference between the gate structure6and the second power terminal7terminal may be several hundreds of volts, such as 1500 V or less, such as 600 V or less.

As shown, in case the second power terminal forms the drain, the anode of the Schottky diode100may be electrically connected to the source, i.e. the first power terminal5. Thereby, the Schottky diode100may be used as a clamp diode which clamps the drain and source of the transistor200. For example, a conducting path, e.g. a metal line, may be provided which connects the anode layer to the first power terminal5. The conducting path may for example be provided as a patterned layer50deposited on the dielectric layer10, which extends between, and is in direct contact with, the first power terminal5and the anode104.

Referring toFIG. 9, an equivalent circuit of the example ofFIG. 7is shown. As shown, the equivalent circuit includes a power transistor200connected in parallel with a diode100. More specific, the cathode of the diode is connected to the drain of the power transistor and the anode is connected to the source. The drain of the power transistor100may for instance be connected to a positive potential, while the source may, e.g., be connected to a ground. The diode100may then be used as a clamp diode to evacuate any voltage/current surge when the power transistor200is switched off, i.e. the current flow through the power transistor200is interrupted.

In the foregoing specification, the invention has been described with reference to specific examples of embodiments of the invention. It will, however, be evident that various modifications and changes may be made therein without departing from the broader spirit and scope of the invention as set forth in the appended claims. For example, the transistor may be part of an integrated circuit which includes one or more transistors. Also, although in the FIGs. cross-sectional views are shown, it will be apparent that the transistor may for example have a circular, hexagonal or rectangular shape. Also, for instance, the substrate isolation could also be performed using a pn junction isolation.

For example, the semiconductor substrate described herein can be any semiconductor material or combinations of materials, such as silicon carbide, gallium arsenide, silicon germanium, silicon-on-insulator (SOI), silicon, monocrystalline silicon, the like, and combinations of the above.

The connections as discussed herein may be any type of connection suitable to transfer signals from or to the respective nodes, units or devices, for example via intermediate devices. Accordingly, unless implied or stated otherwise, the connections may for example be direct connections or indirect connections.