Power supply system

A pseudo-resonant element (130) is disposed in series with respect to an inductive load (180) on the inductive load (180) side rather than an output end of an inverter unit (120) constituted of a magnetic energy recovery switch.

TECHNICAL FIELD

The present invention relates to a power supply system, and in particular is suitable for use for converting direct-current power into alternating-current power.

BACKGROUND ART

As a device which converts direct-current power into alternating-current power, there is a device using a magnetic energy recovery switch (refer to Patent Literature 1). The magnetic energy recovery switch mentioned in Patent Literature 1 has four switches and a capacitor. The four switches are connected so as to constitute a full-bridge circuit. The capacitor is connected between direct-current terminals of the full-bridge circuit. A load is connected between output terminals of the full-bridge circuit. The four switches each have a positive electrode terminal and a negative electrode terminal. A conduction state from the negative electrode terminal to the positive electrode terminal of the four switches is a state in which a current constantly flows. On the other hand, in a conduction state from the positive electrode terminal to the negative electrode terminal of the four switches, a state in which a current flows and a state in which a current does not flow are switched by a signal from the exterior. Such a magnetic energy recovery switch circuit allows a frequency of the alternating-current power converted from the direct-current power to be changed by changing a frequency at which on and off of the four switches are switched.

Further, Patent Literature 2 mentions that a capacitor improving a power factor on an input side of a magnetic energy recovery switch is provided on the input side of the magnetic energy recovery switch. Further, Patent Literature 2 mentions that a transformer is connected to both ends of a capacitor of the magnetic energy recovery switch and a capacitor is connected in series with the transformer and the capacitor of the magnetic energy recovery switch. This capacitor is the one for making an input voltage to the transformer large.

Further, Patent Literature 3 discloses that a DCDC converting device is constituted by using two magnetic energy recovery switches.

Further, Patent Literature 4 mentions that a capacitor is connected in parallel with an inductive load between alternating-current terminals of a magnetic energy recovery switch. Patent Literature 4 indicates that connecting the capacitor in parallel with the inductive load makes it possible to reduce a current flowing through the magnetic energy recovery switch.

CITATION LIST

Patent Literature

Patent Literature 1: International Publication Pamphlet No. WO 2011/74383

SUMMARY OF INVENTION

Technical Problem

As a magnetic energy recovery switch as described above, various ones have been proposed. However, when the magnetic energy recovery switch is utilized as an inverter and alternating-current power is supplied to an inductive load, an impedance of the inductive load seen from an output side of the inverter is determined by reactance and resistance due to an inductance of the inductive load. Therefore, the magnetic energy recovery switch is required to supply reactive power in addition to effective electric power to the inductive load. Therefore, a power supply capacity (rated output power) of the magnetic energy recovery switch increases.

In the technique mentioned in Patent Literature 4, a reactance of the inductive load seen from an output side of an inverter (magnetic energy recovery switch) decreases. However, the technique mentioned in Patent Literature 4 aims to reduce a current flowing through the magnetic energy recovery switch. In order to achieve the aim, a capacitor is connected in parallel with an inductive load between alternating-current terminals of the magnetic energy recovery switch. In that case, a closed circuit is formed by the inductive load and the capacitor connected to the inductive load. When the magnetic energy recovery switch is operated in the above state, an oscillating current flows through the closed circuit. As a result, a current obtained by superimposing a current outputted from the magnetic energy recovery switch and the oscillating current flowing through the closed circuit on each other flows through the inductive load. Accordingly, an unexpected current flows through the inductive load. Therefore, it is impossible to stabilize the current flowing through the inductive load. Hence, addition of a circuit for suppressing the oscillating current flowing through the closed circuit is considered. However, the addition of such a circuit causes an increase in cost.

In the present invention, which has been made in consideration of the above-described problems, it is an object to achieve stabilization of a current to be transmitted to a load without using a specific device and a reduction in a power supply capacity of a magnetic energy recovery switch.

Solution to Problem

One example of a power supply system of the present invention is a power supply system including: a magnetic energy recovery switch; a frequency setting device; a control device; and a pseudo-resonant element, converting direct-current power into alternating-current power, and supplying the alternating-current power to an inductive load, wherein the magnetic energy recovery switch includes: one or a plurality of first capacitors; and a plurality of switches, wherein the frequency setting device sets an output frequency of the magnetic energy recovery switch, wherein the control device controls an on and off operation of the plurality of switches based on an output frequency set by the frequency setting device, wherein the magnetic energy recovery switch recoveries magnetic energy stored in the inductive load and stores the magnetic energy as electrostatic energy in the first capacitor, and supplies the stored electrostatic energy to the inductive load, by on and off of the plurality of switches, wherein the pseudo-resonant element is constituted of at least one passive element including a second capacitor, wherein the first capacitor is disposed in series with respect to the inductive load, wherein the second capacitor is connected in series with respect to the inductive load on the inductive load side rather than an output end of the magnetic energy recovery switch, wherein a value of an inductive reactance on the inductive load side rather than an output end of the magnetic energy recovery switch exceeds a value of a capacitive reactance on the inductive load side rather than an output end of the magnetic energy recovery switch, and wherein the plurality of switches switch on and off when a voltage of both ends of the first capacitor is “0” (zero).

DESCRIPTION OF EMBODIMENTS

Hereinafter, embodiments of the present invention will be described referring to the drawings.

First Embodiment

First, a first embodiment is described.

FIG. 1is a view illustrating a configuration of a power supply system100according to the first embodiment. The power supply system100has a direct-current power supply unit110, an inverter unit120, a pseudo-resonant element130, a current transformer140, a switch control device150, a current control device160, and a frequency setting device170. Each of the components of the power supply system100may be disposed in a distributed manner by connecting them so as to be capable of communicating with one another via a communication unit, for example. Note that the power supply system100does not have a specific device (oscillation suppression circuit) for suppressing an oscillating current.

The direct-current power supply unit110supplies direct-current power to the inverter unit120. The direct-current power supply unit110has an alternating-current power supply111, a rectifier112, and a reactor113. The alternating-current power supply111outputs alternating-current power. The alternating-current power supply111is connected to an input end of the rectifier112. One end of the reactor113is connected to one end of an output side of the rectifier112. The rectifier112rectifies the alternating-current power supplied from the alternating-current power supply111to output the direct-current power. As the rectifier112, for example, a thyristor rectifier is used. However, the rectifier112is not limited to the one described above. For example, the rectifier112may be constituted using a diode rectifier, a voltage control circuit (a step-up/down chopper or the like), and the like. The reactor113is the one for smoothing a waveform of the direct-current power outputted from the rectifier112. In this embodiment, the direct-current power supply unit110is configured to convert the alternating-current power into the direct-current power. However the direct-current power supply unit110is not limited to the one described above. For example, the direct-current power supply unit110may be a power supply device which directly supplies a direct current. For example, the direct-current power supply unit110may be constituted using a battery, a current control circuit, and the like.

The inverter unit120converts the direct-current power outputted from the direct-current power supply unit110into alternating-current power with the same frequency as a switching frequency at which each switch of the inverter unit120is switched. Then, the inverter unit120supplies the alternating-current power with the frequency to an inductive load180. The inverter unit120has a magnetic energy recovery switch (MERS).

One example of a configuration of the inverter unit120(magnetic energy recovery switch) of this embodiment is described.

The inverter unit120has a first switch U, a second switch X, a third switch V, a fourth switch Y, a first alternating-current terminal121, a second alternating-current terminal122, a first direct-current terminal123, a second direct-current terminal124, and a first capacitor125.

First, the first switch U, the second switch X, the third switch V, and the fourth switch Y are described.

In this embodiment, the first switch U, the second switch X, the third switch V, and the fourth switch Y have the same configuration. A full-bridge circuit is constituted by the first switch U, the second switch X, the third switch V, and the fourth switch Y.

The first switch U has a self-arc-extinguishing element S1and a free-wheeling diode D1. The second switch X has a self-arc-extinguishing element S2and a free-wheeling diode D2. The third switch V has a self-arc-extinguishing element S3and a free-wheeling diode D3. The fourth switch Y has a self-arc-extinguishing element S4and a free-wheeling diode D4.

In the self-arc-extinguishing elements S1to S4, as a conduction state, either state of a state which allows a current to flow and a state which does not allow a current to flow can be switched by a signal from the exterior.

The free-wheeling diodes D1to D4each have a first end portion and a second end portion. The free-wheeling diodes D1to D4each have only a state of passing a current from the first end portion to the second end portion but not passing a current from the second portion to the first portion as a conduction state. A direction from the first end portion to the second end portion of each of the free-wheeling diodes D1to D4is set as a forward direction in each of the free-wheeling diodes D1to D4. The first end portion of each of the free-wheeling diodes D1to D4is set as an end portion on the forward direction side. The second end portion of each of the free-wheeling diodes D1to D4is set as an end portion on a backward side to the forward direction.

The self-arc-extinguishing elements S1to S4each have a first end portion and a second end portion. The self-arc-extinguishing elements S1to S4each pass a current from the first end portion to the second end portion in a case of a state in which a current can be passed. The self-arc-extinguishing elements S1to S4each do not pass a current from the first end portion to the second end portion in a case of a state in which a current cannot be passed. Further, The self-arc-extinguishing elements S1to S4each do not pass a current from the second end portion to the first end portion in any state. A direction from the first end portion to the second end portion of each of the self-arc-extinguishing elements S1to S4is set as a forward direction in each of the self-arc-extinguishing elements S1to S4. The first end portion of each of the self-arc-extinguishing elements S1to S4is set as an end portion on the forward direction side. The second end portion of each of the self-arc-extinguishing elements S1to S4is set as an end portion on a backward side to the forward direction. The self-arc-extinguishing elements S1to S4are not limited to a bipolar-type transistor. For example, the self-arc-extinguishing elements S1to S4can employ a field-effect transistor (FET), an insulated gate bipolar transistor (IGBT), an injection enhanced gate transistor (IEGT), a gate turn-off thyristor (GOT thyristor), or a gate commutated turn-off thyristor (GCT thyristor).

The self-arc-extinguishing element S1and the free-wheeling diode D1are connected in parallel so that their forward directions are backward to each other. Regarding the above, the self-arc-extinguishing element S2and the free-wheeling diode D2, the self-arc-extinguishing element S3and the free-wheeling diode D3, and the self-arc-extinguishing element S4and the free-wheeling diode D4are the same as the self-arc-extinguishing element S1and the free-wheeling diode D1.

A connection point of the end portion on the forward direction side of each of the free-wheeling diodes D1, D2, D3, and D4and the end portion on the backward side to the forward direction of each of the self-arc-extinguishing elements S1, S2, S3, and S4is set as a negative electrode terminal. A connection point of the end portion on the forward direction side of each of the self-arc-extinguishing elements S1, S2, S3, and S4and the end portion on the backward side to the forward direction of each of the free-wheeling diodes D1, D2, D3, and D4is set as a positive electrode terminal.

The negative electrode terminal of the first switch U and the positive electrode terminal of the second switch X are connected to each other. The positive electrode terminal of the first switch U and the positive electrode terminal of the third switch V are connected to each other. The negative electrode terminal of the fourth switch Y and the negative electrode terminal of the second switch X are connected to each other. The positive electrode terminal of the fourth switch Y and the negative electrode terminal of the third switch V are connected to each other.

The first alternating-current terminal121is connected to a connection point of the negative electrode terminal of the first switch U and the positive electrode terminal of the second switch X. The second alternating-current terminal122is connected to a connection point of the negative electrode terminal of the third switch V and the positive electrode terminal of the fourth switch Y. In this embodiment, the first alternating-current terminal121and the second alternating-current terminal122are output ends of the inverter unit120.

The first direct-current terminal123is connected to a connection point of the positive electrode terminal of the first switch U and the positive electrode terminal of the third switch V. To the first direct-current terminal123, the other end of the reactor113is connected. The second direct-current terminal124is connected to a connection point of the negative electrode terminal of the second switch X and the negative electrode terminal of the fourth switch Y. To the second direct-current terminal124, the other end on an output side of the rectifier112is connected. In this embodiment, the first direct-current terminal123and the second direct-current terminal124are input ends of the inverter unit120.

The direct-current power supply unit110is connected between the first direct-current terminal123and the second direct-current terminal124as described above.

As long as the first switch U, the second switch X, the third switch V, and the fourth switch Y have the above-described conduction state, they do not necessarily have the free-wheeling diodes D1, D2, D3, and D4, and the self-arc-extinguishing elements S1, S2, S3, and S4. For example, the first switch U, the second switch X, the third switch V, and the fourth switch Y may be a metal-oxide semiconductor field-effect transistor (MOS transistor) in which a parasitic diode is built.

The first capacitor125is connected between the first direct-current terminal123and the second direct-current terminal124. That is, one end of the first capacitor125and the first direct-current terminal123are connected to each other. The other end of the first capacitor125and the second direct-current terminal124are connected to each other. The first capacitor125is a capacitor having polarity.

The pseudo-resonant element130is utilized for apparently reducing an inductance of the inductive load180seen from the output ends of the inverter unit120. The pseudo-resonant element130is constituted of at least one passive element including a second capacitor. In this embodiment, the pseudo-resonant element130is constituted of the second capacitor. The second capacitor is a nonpolar capacitor.

The pseudo-resonant element130is connected in series with respect to the inductive load180between the first alternating-current terminal121and the second alternating-current terminal122of the inverter unit120. In an example illustrated inFIG. 1, one end of the pseudo-resonant element130and the second alternating-current terminal122of the inverter unit120are connected to each other.

The inductive load180is connected in series with respect to the first capacitor125between the first alternating-current terminal121and the second alternating-current terminal122of the inverter unit120. In the example illustrated inFIG. 1, one end of the inductive load180and the other end of the pseudo-resonant element130are connected to each other. The other end of the inductive load180and the first alternating-current terminal121of the inverter unit120are connected to each other. The inductive load100is connected between the first alternating-current terminal121and the second alternating-current terminal122as described above. Further, the pseudo-resonant element130is connected in series with respect to the inductive load180between the first alternating-current terminal121and the second alternating-current terminal122.

The inductive load180is a load having an inductance component. An inductive reactance of the inductive load180is larger than a capacitive reactance of the inductive load180. In order to simplify the description, in the following description, the capacitive reactance of the inductive load180is set to “0” (zero). The inductive load180is a coil for induction heating an object to be heated such as a steel plate and the object to be heated, for example. The coil which induction heats the object to be heated of the inductive load180generates magnetic flux lines when an alternating current is supplied from the inverter unit120. Owing to this magnetic flux lines, an eddy current flows through the object to be heated. The object to be heated is heated in a non-contact manner by this eddy current. Note that the inductive load180is not limited to the coil for induction heating the object to be heated. For example, the inductive load180may be a plurality of metal plates (for example, steel plates) to be subjected to resistance spot welding. In this case, the plurality of metal plates to become the inductive load180are current-heated. Further, in this embodiment, there is no load connected in parallel with respect to the first capacitor125.

The current transformer140measures a value of an alternating current flowing through the inductive load180.

The frequency setting device170sets a switching frequency at which the first switch U, the second switch X, the third switch V, and the fourth switch Y are switched. When the inductive load180is the coil for induction heating the object to be heated, a frequency suitable for induction heating the object to be heated is set as the switching frequency. The frequency suitable for induction heating the object to be heated is determined based on a condition including a specification of an induction heating device, and a shape, a width, a thickness, and a heating temperature of the object to be heated, for example. For example, an operator examines a switching frequency in a case of varying the specification of the induction heating device, and the shape, the width, the thickness, and the heating temperature of the object to be heated as the frequency suitable for induction heating the object to be heated, in advance. The frequency setting device170makes it possible to store the frequency examined in this manner in a storage device such as a ROM in advance. Further, the frequency setting device170also makes it possible to input information of the switching frequency based on an operation of the operator via an input interface such as a screen for inputting the frequency.

The switch control device150generates a switching signal for switching the first switch U, the second switch X, the third switch V, and the fourth switch Y at the switching frequency set by the frequency setting device170. Then, the switch control device150outputs the switching signal to the first switch U, the second switch X, the third switch V, and the fourth switch Y. Based on this switching signal, the conduction state of the self-arc-extinguishing elements S1, S2, S3, and S4of the first switch U, the second switch X, the third switch V, and the fourth switch Y is switched. Hereinafter, a state in which the self-arc-extinguishing elements S1, S2, S3, and S4can pass a current is referred to as on. Further, a state in which the self-arc-extinguishing elements S1, S2, S3, and S4cannot pass a current is referred to as off.

The switch control device150turns the second switch X and the third switch V to off when the first switch U and the fourth switch Y are on. Further, the switch control device150turns the second switch X and the third switch V to on when the first switch U and the fourth switch Y are off. Further, the switch control device150switches on and off of each of the first switch U, the second switch X, the third switch V, and the fourth switch Y at the switching frequency set by the frequency setting device170. Note that a frequency of a current Iinvwhich the inverter unit120outputs is set as the switching frequency (details of this point are described below). In this embodiment, the switching frequency at which the first switch U, the second switch X, the third switch V, and the fourth switch Y are switched is an output frequency of the magnetic energy recovery switch.

The switching frequency at which the switch control device150switches the first switch U, the second switch X, the third switch V, and the fourth switch Y is set as f. In this case, the inverter unit120supplies the current Iinvwith the frequency f to the inductive load180.

The current control device160monitors a current measured by the current transformer140. Then, the current control device160controls an operation of the rectifier112so that the current measured by the current transformer140becomes a target value. When the inductive load180is the coil for induction heating the object to be heated, the target value is determined based on a physical property value and a size of the object to be heated, and the like. When the object to be heated is a steel plate, the physical property value includes magnetic permeability and resistivity, for example.

Here, an inductive load having a reactance obtained by subtracting a capacitive reactance of the pseudo-resonant element130from the inductive reactance of the inductive load180is assumed to be an apparent inductive load seen from the inverter unit120. As described below, the inductive reactance of the inductive load180exceeds the capacitive reactance of the pseudo-resonant element130. Accordingly, the apparent inductive load has an inductance component.

An angular frequency ω [rad/s] is represented by 2 πf using the frequency f [Hz]. An inductance of the inductive load180is set as L. An inductance of the apparent inductive load is set as L′. Further, an electrostatic capacitance of the second capacitor of the pseudo-resonant element130is set as Cr. In that case, a reactance ωL′ of the apparent inductive load is as in the following (1) expression.

That is, a circuit configuration of the power supply system100is equivalent to a circuit in which an inductive load with an inductance L′ represented by (2) expression is connected between the first alternating-current terminal121and the second alternating-current terminal122of the inverter unit120.

FIG. 2is a view illustrating one example of a configuration of a power supply system equivalent to the power supply system100inFIG. 1.FIG. 2is a view in which an apparent inductive load210is disposed instead of the pseudo-resonant element130and the inductive load180illustrated inFIG. 1.

As illustrated inFIG. 2, a power supply system200does not have the pseudo-resonant element130, but has an apparent inductive load210whose inductance is L′. The power supply system200illustrated inFIG. 2is different from the power supply system100illustrated inFIG. 1in the elements constituting the circuit as described above. However, the power supply system200illustrated inFIG. 2is equivalent to the power supply system100illustrated inFIG. 1. That is, the power supply system100of this embodiment apparently reduces the inductance of the inductive load180by having the pseudo-resonant element130connected in series with respect to the inductive load180.

Next, one example of an operation of the inverter unit120is described.FIG. 3is a view explaining one example of a flow of a current in the inverter unit120.FIG. 4Ais a chart explaining a first example of a relationship among a switching signal V-Xgateof the second switch X and the third switch V, a voltage Vmerscapplied to the first capacitor125, and a current Iinvoutputted from the inverter unit120.FIG. 4Bis a chart explaining a second example of a relationship among a switching signal V-Xgateof the second switch X and the third switch V, a voltage Vmerscapplied to the first capacitor125, and a current Iinvoutputted from the inverter unit120.

First, one example of an operation of the inverter unit120when a time period T0in which the voltage Vmerscapplied to the first capacitor125remains “0” (zero) exceeds “0” (zero) is described referring toFIG. 3andFIG. 4A.

An initial state is set as a state in which the first capacitor125is charged, the first switch U and the fourth switch Y are off, and the second switch X and the third switch V are on.

As illustrated in a state A inFIG. 3, when the first capacitor125starts discharging, a current discharged from the first capacitor125goes to the first direct-current terminal123. Since the first switch U is off and the third switch V is on, the current flowing into the first direct-current terminal123flows via the third switch V toward the second alternating-current terminal122. Then, since the fourth switch Y is off, the current flowing into the second alternating-current terminal122cannot flow through the positive electrode terminal side of the fourth switch Y and flows toward the pseudo-resonant element130and the inductive load180. The current passing the inductive load180goes to the first alternating-current terminal121. The current flowing into the first alternating-current terminal121goes via the second switch X to the second direct-current terminal124since the second switch X is on. The current flowing into the second direct-current terminal124goes back to the first capacitor125.

A change of a voltage applied to the first capacitor125after the first capacitor125starts discharging and a change of a current outputted from the inverter unit120are described usingFIG. 4A. V-Xgateis a signal which the switch control device150transmits to the second switch X and the third switch V, and an on and off switching signal of the second switch X and the third switch V. Note that when the switching signal V-Xgateindicates an on value, the second switch X and the third switch V are in an on state, and when the switching signal V-Xgateindicates an off value, the second switch X and the third switch V are in an off state. Further, although an illustration is omitted here, the switch control device150also transmits a switching signal U-Ygateto the first switch U and the fourth switch Y. A value of the switching signal U-Ygateindicates a value opposite to the switching signal transmitted to the second switch X and the third switch V. That is, the value of the switching signal U-Ygateindicates an off value when the switching signal V-Xgateindicates the on value, and it indicates an on value when the switching signal V-Xgateindicates the off value. Vmerscindicates a voltage applied to the first capacitor125. Iinvindicates a current outputted from the inverter unit120. t0indicates a time at which the first capacitor125starts discharging. When the first capacitor125starts discharging, the current Iinvoutputted from the inverter unit120increases in a plus direction, and the voltage Vmerscapplied to the first capacitor125starts decreasing. When the first capacitor125finishes discharging, the voltage Vmerscapplied to the first capacitor125becomes “0” (zero). t1indicates a time at which the first capacitor125finishes discharging.

At the time t1, when the discharge of the first capacitor125finishes, the current Iinvoutputted from the inverter unit120reaches a peak, and the voltage Vmerscof the first capacitor125becomes “0” (zero). Since a voltage between the first direct-current terminal123and the second direct-current terminal124is “0” (zero), a current does not flow between the first direct-current terminal123and the second direct-current terminal124. In this case, as illustrated in a state B inFIG. 3, part of the current flowing into the first alternating-current terminal121goes via the free-wheeling diode D1of the first switch U to the first direct-current terminal123, and goes via the third switch V to the second alternating-current terminal122. The remainder of the current flowing into the first alternating-current terminal121goes via the second switch X to the second direct-current terminal124, and goes via the free-wheeling diode D4of the fourth switch Y to the second alternating-current terminal122. In this case, the voltage Vmerscapplied to the first capacitor125is “0” (zero). Accordingly, voltages applied to the first switch U, the second switch X, the third switch V, and the fourth switch Y also become “0” (zero). The time period in which the voltage Vmerscapplied to the first capacitor125is “0” (zero) is set as T0.

In a state B inFIG. 3, the current flowing through the inverter unit120and the inductive load180gradually decreases according to a time constant determined from the inductance and a resistance component of the inductive load180. As illustrated inFIG. 4A, the current Iinvoutputted from the inverter unit120decreases in the time period of the time t1to a time t2.

The switch control device150switches the first switch U and the fourth switch Y to on and the second switch X and the third switch V to off at the time t2at which the time period T0passes from the time t1at which the discharge of the first capacitor125finishes. At this time, the voltage Vmerscapplied to the first capacitor125is “0” (zero), thereby resulting in soft switching. Note that the soft switching indicates that when a voltage applied to a switch is theoretically “0” (zero), the switch is switched from on to off or from off to on.

When the first switch U and the fourth switch Y are switched to on and the second switch X and the third switch V are switched to off, the current flowing into the first alternating-current terminal121cannot flow through the second switch X and goes via the first switch U to the first direct-current terminal123since the second switch X is off as illustrated in a state C inFIG. 3. The current flowing into the first direct-current terminal123cannot flow through the third switch V and goes to the first capacitor125since the third switch V is off. The current flowing into the first capacitor125is utilized for a charge of the first capacitor125, and gradually decreases. This current flows as illustrated in the state C inFIG. 3until the first capacitor125finishes charging, and becomes “0” (zero) at a time point at which the charge of the first capacitor125finishes. InFIG. 4A, the first capacitor125finishes charging at a time t3.

As illustrated inFIG. 4A, the voltage Vmerscapplied to the first capacitor125rises between the time t2and the time t3. Further, in accordance with a rise in the voltage Vmerscapplied to the first capacitor125, the current Iinvoutputted from the inverter unit120decreases. When the charge of the first capacitor125finishes at the time t3, the voltage Vmerscapplied to the first capacitor125reaches a peak. At this time, the current Iinvoutputted from the inverter unit120becomes “0” (zero).

After the charge of the first capacitor125finishes, the first capacitor125starts discharging. As illustrated in a state D inFIG. 3, the current discharged from the first capacitor125goes to the first direct-current terminal123. Since the first switch U is on and the third switch V is off, this current goes via the first switch U to the first alternating-current terminal121, and flows into the inductive load180and the pseudo-resonant element130. The current flowing into the pseudo-resonant element130goes to the second alternating-current terminal122, and goes via the fourth switch Y and the second direct-current terminal124to the first capacitor125. Thus, the current flowing from the second alternating-current terminal122via the pseudo-resonant element130and the inductive load180toward the first alternating-current terminal121in the initial state flows from the first alternating-current terminal121via the inductive load180and the pseudo-resonant element130through the second alternating-current terminal122. That is, a direction of the current flowing into the pseudo-resonant element130and the inductive load180is opposite to that in the states A to C. Thus, by switching on and off of the first switch U, the second switch X, the third switch V, and the fourth switch Y at a switching frequency f set by the switch control device150, the inverter unit120outputs the current Iinvwith the same frequency as the switching frequency f.

InFIG. 4A, the first capacitor125finishes discharging at a time t4. As illustrated inFIG. 4A, the voltage Vmerscapplied to the first capacitor125continues decreasing from the time t3in accordance with the discharge of the first capacitor125, and becomes “0” (zero) at the time t4. Further, the current Iinvoutputted from the inverter unit120increases in a direction opposite to a direction in the time t0to the time t3in accordance with the discharge of the first capacitor125. Then, the current Iinvoutputted from the inverter unit120reaches a peak in a direction opposite to a direction in the time t0to the time t3at the time t4at which the discharge of the first capacitor125finishes. A direction of the current Iinvoutputted from the inverter unit120between the time t3and the time t4is opposite to a direction of the current Iinvoutputted from the inverter unit120between the time t0and the time t1. Therefore, in a graph inFIG. 4A, a value of the current Iinvoutputted from the inverter unit120between the time t3and the time t4is a minus value.

At the time t4, when the discharge of the first capacitor125finishes, the voltage Vmerscapplied to the first capacitor125becomes “0” (zero). Since a voltage between the first direct-current terminal123and the second direct-current terminal124is “0” (zero), a current does not flow between the first direct-current terminal123and the second direct-current terminal124as illustrated in a state E inFIG. 3. In this case, part of the current flowing into the second alternating-current terminal122goes via the free-wheeling diode D3of the third switch V to the first direct-current terminal123, and goes via the first switch U to the first alternating-current terminal121. The remainder of the current flowing into the second alternating-current terminal122goes via the fourth switch Y to the second direct-current terminal124, and goes via the free-wheeling diode D2of the second switch X to the first alternating-current terminal121.

In a state E inFIG. 3, the current flowing through the inverter unit120and the inductive load180gradually approaches “0” (zero) according to the time constant based on the inductance and the resistance component of the inductive load180. As illustrated inFIG. 4A, the current Iinvoutputted from the inverter unit120approaches “0” (zero) in the time period of the time t4to a time t5.

The switch control device150switches the first switch U and the fourth switch Y to off and the second switch X and the third switch V to on at the time t5at which the time period T0passes from the time t4at which the discharge of the first capacitor125finishes. At this time, the voltage Vmerscapplied to the first capacitor125is “0” (zero), thereby resulting in the soft switching.

When the first switch U and the fourth switch Y are switched to off and the second switch X and the third switch V are switched to on, the current flowing into the second alternating-current terminal122goes via the third switch V to the first direct-current terminal123since the fourth switch Y is off as illustrated in a state F inFIG. 3. The current flowing into the first direct-current terminal123goes to the first capacitor125since the first switch U is off. The current flowing into the first capacitor125approaches “0” (zero) further. This current flows as illustrated in the state F inFIG. 3until the first capacitor125finishes charging, and becomes “0” (zero) at the time point at which the charge of the first capacitor125finishes.

As illustrated inFIG. 4A, the voltage Vmerscapplied to the first capacitor125rises between the time t5and a time t6. Further, in accordance with a rise in the voltage Vmerscapplied to the first capacitor125, the current Iinvoutputted from the inverter unit120approaches “0” (zero). When the charge of the first capacitor125finishes at the time t6, the voltage Vmerscapplied to the first capacitor125reaches a peak. At this time, the current Iinvoutputted from the inverter unit120becomes “0” (zero).

At the time t6, when the charge of the first capacitor125finishes, the first switch U and the fourth switch Y are off and the second switch X and the third switch V are on, thereby returning to the state A which is the initial state. The inverter unit120repeats the above operation.

As illustrated in the state C and the state F inFIG. 3, at a time of the charge of the first capacitor125, the current flows from the first direct-current terminal123into the first capacitor125. That is, in the first capacitor125, necessarily, a positive electric charge accumulates on the first direct-current terminal123side and a negative electric charge accumulates on the second direct-current terminal124side. Therefore, as the first capacitor125, a capacitor having polarity can be used. Further, a direction of a current flowing into the second capacitor included in the pseudo-resonant element130is not fixed. Therefore, as the second capacitor, the capacitor having polarity cannot be used, but a nonpolar capacitor is used.

As illustrated inFIG. 4A, as the current Iinvoutputted from the inverter unit120, the current for one cycle of the alternating current is outputted. That is, the inverter unit120outputs the alternating current with the same frequency as the switching frequency f.

FIG. 4Aillustrates a case where the time period T0in which the voltage Vmerscapplied to the first capacitor125remains “0” (zero) exceeds “0” (zero). In contrast with this,FIG. 4Billustrates a case where the time period T0in which the voltage Vmerscapplied to the first capacitor125remains “0” (zero) is “0” (zero). Hereinafter, one example of an operation of the inverter unit120when the time period T0in which the voltage Vmerscapplied to the first capacitor125remains “0” (zero) is “0” (zero) is described referring toFIG. 3andFIG. 4B.

An initial state is set as a state in which the first capacitor125is charged, the first switch U and the fourth switch Y are off, and the second switch X and the third switch V are on.

When the time period T0in which the voltage Vmerscapplied to the first capacitor125remains “0” (zero) is “0” (zero), the first capacitor125performs the discharge between the time t0and the time t1as illustrated inFIG. 4B. Then, the voltage Vmerscapplied to the first capacitor125becomes “0” (zero) at the time t1. The operation of the inverter unit120between the time t0and the time t1illustrated inFIG. 4Bis the same as the operation of the inverter unit120between the time t0and the time t1illustrated inFIG. 4A.

In the example illustrated inFIG. 4A, the time period T0in which the voltage Vmerscapplied to the first capacitor125remains “0” (zero) is set after the time t1. In contrast with this, in the example illustrated inFIG. 4B, the time period T0in which the voltage Vmerscapplied to the first capacitor125remains “0” (zero) is “0” (zero). Accordingly, the switch control device150switches the first switch U and the fourth switch Y to on and switches the second switch X and the third switch V to off at the time t1at which the discharge of the first capacitor125finishes (namely, without keeping time from when the discharge of the first capacitor125finishes).

In that case, the first capacitor125performs the charge between the time t1and the time t2, and performs the discharge between the time t2and the time t3. Then, the voltage Vmerscapplied to the first capacitor125becomes “0” (zero) at the time t3. In the example illustrated inFIG. 4Bas described above, the first switch U, the second switch X, the third switch V, and the fourth switch Y change from the state A to the state C inFIG. 3, and do not change to the state B. The operation of the inverter unit120between the time t1and the time t3illustrated inFIG. 4Bis the same as the operation of the inverter unit120between the time t2and the time t4illustrated inFIG. 4A.

Thereafter, in the example illustrated inFIG. 4A, the time period T0in which the voltage Vmerscapplied to the first capacitor125remains “0” (zero) is set. In contrast with this, in the example illustrated inFIG. 4B, the time period T0in which the voltage Vmerscapplied to the first capacitor125remains “0” (zero) is “0” (zero). Accordingly, the switch control device150switches the first switch U and the fourth switch Y to off and switches the second switch X and the third switch V to on at the time t3at which the discharge of the first capacitor125finishes (namely, without keeping time from when the discharge of the first capacitor125finishes).

In that case, the first capacitor125performs the charge between the time t3and the time t4. In the example illustrated inFIG. 4Bas described above, the first switch U, the second switch X, the third switch V, and the fourth switch Y change from the state D to the state F inFIG. 3, and do not change to the state E. The operation of the inverter unit120between the time t3and the time t4illustrated inFIG. 4Bis the same as the operation of the inverter unit120between the time t5and the time t6illustrated inFIG. 4A.

As illustrated inFIG. 4B, from the time t0, the current Iinvoutputted from the inverter unit120increases in a plus direction with the discharge of the first capacitor125. Then, the current Iinvoutputted from the inverter unit120reaches a peak at the time t1at which the discharge of the first capacitor125finishes. From the time t1, the current Iinvoutputted from the inverter unit120approaches “0” (zero) with the charge of the first capacitor125. Then, the current Iinvoutputted from the inverter unit120becomes “0” (zero) at the time t2at which the charge of the first capacitor125finishes.

From the time t2, the direction of the current Iinvoutputted from the inverter unit120is opposite to the direction in the time t0to the time t2. From the time t2, the current Iinvoutputted from the inverter unit120increases in the direction opposite to the direction in the time t0to the time t2with the discharge of the first capacitor125. Then, the current Iinvoutputted from the inverter unit120reaches a peak in the direction opposite to the direction in the time t0to the time t2at the time t3at which the discharge of the first capacitor125finishes. From the time t3, The current Iinvoutputted from the inverter unit120approaches “0” (zero) with the charge of the first capacitor125. Then, the current Iinvoutputted from the inverter unit120becomes “0” (zero) at the time t4at which the charge of the first capacitor125finishes.

The switch control device150switches on and off between the first switch U and the fourth switch Y, and the second switch X and the third switch V at the time t1and the time t3at which the voltage Vmerscapplied to the first capacitor125becomes “0” (zero). This allows the switch control device150to achieve the soft switching even when the time period T0in which the voltage Vmerscapplied to the first capacitor125remains “0” (zero) is “0” (zero).

Further, the time periods taken to charge and discharge the first capacitor125are a half cycle of a resonance frequency determined from an electrostatic capacitance Cmof the first capacitor125and the inductance L′ of the apparent inductive load210. Therefore, as illustrated inFIG. 4B, when the time period T0in which the voltage Vmerscapplied to the first capacitor125remains “0” (zero) is “0” (zero), a frequency of the current Iinvoutputted from the inverter unit120is equal to the resonance frequency determined from the electrostatic capacitance Cmof the first capacitor125and the inductance L′ of the apparent inductive load210.

As is apparent from the above description, by switching on and off between the first switch U and the fourth switch Y, and the second switch X and the third switch V, the first capacitor125and the pseudo-resonant element130are disposed in series on a path of the alternating current flowing through all or part of the first switch U, the second switch X, the third switch V, and the fourth switch Y. Note that in this embodiment, this alternating current does not flow separately through the inverter unit120except when it is in states of the state B and the state E illustrated inFIG. 3.

Further, as illustrated inFIG. 1, in a state (state of performing charge and discharge) of applying a voltage to the first capacitor125, the inverter unit120, the pseudo-resonant element130, and the inductive load180can be regarded as a series resonant circuit in which the first capacitor125, the pseudo-resonant element130, and the inductive load180with an inductance L are connected in series. Further, the pseudo-resonant element130and the inductive load180are equivalent to the apparent inductive load210having the inductance L′. Accordingly, the series resonant circuit in which the inverter unit120, the pseudo-resonant element130, and the inductive load180are connected in series can be regarded as the series resonant circuit in which the first capacitor125and the apparent inductive load210are connected in series.

Therefore, the first capacitor125performs charge and discharge in a half cycle of a resonance frequency fres(=1/(2π×√(L′×Cm))) determined from the electrostatic capacitance Cmof the first capacitor125and the inductance L′ of the apparent inductive load210. That is, the voltage Vmerscapplied to the first capacitor125is “0” (zero) at a time of a start of the charge of the first capacitor125, rises with the charge of the first capacitor125, and drops with the discharge of the first capacitor125. Then, from timing at which the charge of the first capacitor125starts, at a time point at which the half cycle of the frequency frespasses, the voltage Vmerscapplied to the first capacitor125becomes “0” (zero) again.

That is, the first capacitor125and the apparent inductive load210resonate at the resonance frequency fresdetermined from the electrostatic capacitance Cmof the first capacitor125and the inductance L′ of the apparent inductive load210. In order that the first capacitor125and the apparent inductive load210resonate, it is necessary that the angular frequency ω at which a synthetic reactance (=ωL−1/(ω×Cm)) of the first capacitor125and the apparent inductive load210is “0” (zero) exists. In order that the angular frequency ω which is ω=1/√(L′×Cm) exists, it is necessary that L′×Cmis a positive real number. The electrostatic capacitance Cmof the first capacitor125is a positive value because it is a scalar value. Accordingly, in order that L′×Cmis the positive real number, the inductance L′ of the apparent inductive load210is required to be a positive value (namely a value exceeding “0” (zero)).

When the voltage Vmerscapplied to the first capacitor125becomes “0” (zero), a current does not flow through the first capacitor125until switching of on and off between the first switch U and the fourth switch Y, and the second switch X and the third switch V is performed. The switch control device150can achieve the soft switching by switching on and off between the first switch U and the fourth switch Y, and the second switch X and the third switch V at this timing.

Further, the switch control device150can adjust the frequency of a current IInvoutputted from the inverter unit120by adjusting the time period in which the voltage Vmerscapplied to the first capacitor125is “0” (zero). The time period from a time point at which the voltage Vmerscapplied to the first capacitor125becomes “0” (zero) to a time point at which the switching of on and off between the first switch U and the fourth switch Y, and the second switch X and the third switch V is performed is the same as the time period T0in which the voltage Vmerscapplied to the first capacitor125is “0” (zero). In that case, a relational expression of the next (3) expression is established.

According to the (3) expression, a time period of one cycle of the resonance frequency fresis represented by the next (4) expression.

The time period T0in which the voltage Vmerscapplied to the first capacitor125is “0” (zero) is a value of “0” (zero) or more. Accordingly, one cycle of the resonance frequency fresdetermined from the electrostatic capacitance Cmof the first capacitor125and the inductance L′ of the apparent inductive load210is one cycle or less of the switching frequency f of the inverter unit120. That is, the resonance frequency fresdetermined from the electrostatic capacitance Cmof the first capacitor125and the inductance L′ of the apparent inductive load210is required to be a value larger than the switching frequency f. Accordingly, the electrostatic capacitance Cmof the first capacitor125is required to be a value satisfying the next (5) expression.

When it is assumed that the resonance frequency fresis below the switching frequency f of the inverter unit120, in the inverter unit120, a case where the voltage Vmerscapplied to the first capacitor125is “0” (zero) does not occur, and the soft switching cannot be performed.

As described above, the switching frequency f of the inverter unit120is set to be equal to or less than the resonance frequency fresin the resonance circuit including the first capacitor125, the pseudo-resonant element130, and the inductive load180.

According to the above, the power supply system100is required to have the first capacitor125, the pseudo-resonant element130, and the inductive load180such as to satisfy L′>0 and the (5) expression when the switching frequency of the inverter unit120is f. When the (5) expression is satisfied, √(L′×Cm) is a positive value. The electrostatic capacitance Cmof the first capacitor125is a positive value. Accordingly, a relational expression of L′>0 is also satisfied.

Consequently, it is sufficient that the power supply system100has the first capacitor125, the pseudo-resonant element130, and the inductive load180such as to satisfy the (5) expression when the switching frequency of the inverter unit120is f.

As described above, the power supply system100can reduce an apparent reactance of the inductive load180and reduce the voltage Vinvoutputted from the inverter unit120by reducing the apparent inductance of the inductive load180seen from the inverter unit120. If the current outputted from the inverter unit120is the same, a power supply capacity of the inverter unit120is finally smaller in a case of having the pseudo-resonant element130than in a case of not having the pseudo-resonant element130.

Further, the power supply system100can generate the time period in which the voltage Vmerscapplied to the first capacitor125is “0” (zero) by making the first capacitor125and the apparent inductive load210resonate at a frequency equal to or more than the switching frequency f of the inverter unit120. Then, the power supply system100can achieve the soft switching by switching on and off between the first switch U and the fourth switch Y, and the second switch X and the third switch V during the time period.

Further, the power supply system100is set to have the first capacitor125, the pseudo-resonant element130, and the inductive load180such as to satisfy the (5) expression at all frequencies which can be taken as the switching frequency f of the inverter unit120. The power supply system100can achieve a reduction (namely, a reduction in the power supply capacity of the inverter unit120) in the voltage Vinvoutputted from the inverter unit120and the soft switching by performing as described above even when the switching frequency f of the inverter unit120is changed by the switch control device150.

Further, the pseudo-resonant element130is connected to the inductive load180not in parallel but in series. Further, there is no capacitor (passive element having a capacitive reactance) connected in parallel to the inductive load180on the inductive load180side rather than the inverter unit120. Accordingly, the pseudo-resonant element130and the inductive load180do not constitute a closed circuit. Consequently, an oscillating current is not generated. Therefore, it is possible to suppress that an unexpected current flows into the inductive load180. From the above, the inverter unit120can transmit a desired current whose oscillation is suppressed to the inductive load180without using a specific device such as an oscillation suppressing circuit.

The inverter unit120performs the switching of on and off between the first switch U and the fourth switch Y, and the second switch X and the third switch V as described above. Accordingly, the inverter unit120repeats recovering magnetic energy stored in the inductive load180and storing it as electrostatic energy to charge the first capacitor125, and supplying the electrostatic energy stored in the first capacitor125to the inductive load180. Accordingly, the voltage Vmerscapplied to the first capacitor125becomes an alternating voltage including the time period in which the voltage Vmerscapplied to the first capacitor125is “0” (zero) as illustrated inFIG. 4AandFIG. 4B. That is, the first capacitor125is not the one for smoothing a waveform of the direct-current power outputted from the rectifier112. When it is assumed that the first capacitor125is the one for smoothing the waveform of the direct-current power outputted from the rectifier112, although a variation due to a pulsating current occurs, the voltage applied to the first capacitor125is generally a fixed value Edand does not take on a value of “0” (zero) as illustrated inFIG. 5. Moreover, in this case, it is necessary to make only the pseudo-resonant element130and the inductive load180resonate. However, under a condition indicated in the (5) expression, only the pseudo-resonant element130and the inductive load180do not resonate.

(Method of Reducing Power Supply Capacity of Inverter Unit120)

A voltage outputted from the inverter unit120is set as Vinv, a current outputted from the inverter unit120is set as Iinv, a voltage applied to the pseudo-resonant element130is set as Vr, and a voltage applied to the inductive load180is set as Vload. A power supply capacity of the inverter unit120is Iinv×Vinv. Further, the voltage Vloadapplied to the inductive load180is the sum of a voltage Vinvsupplied from the inverter unit120and a voltage Vrapplied to the pseudo-resonant element130. Accordingly, the next (6) expression is established.
Vload=Vinv+Vr(6)

That is, the inverter unit120and the pseudo-resonant element130share the voltage applied to the inductive load180.

The current control device160controls an operation of the rectifier112so that a value of the current Iinvoutputted from the inverter unit120becomes a target value. Therefore, in order to reduce a value of the power supply capacity (=Iinv×Vinv)

of the inverter unit120, it is sufficient to reduce the voltage Vinvoutputted from the inverter unit120. The voltage Vinvoutputted from the inverter unit120is represented by the next (7) expression.

Therefore, the larger the electrostatic capacitance Cmof the first capacitor125is made, the smaller the voltage Vinvoutputted from the inverter unit120becomes.

In a state in which a voltage is applied to the first capacitor125, the first capacitor125, the pseudo-resonant element130, and the inductive load180resonate at the resonance frequency fres(refer to the (5) expression for the resonance frequency fres). In setting the resonance frequency fresnot to change, as the electrostatic capacitance Cmof the first capacitor125is made larger, the inductance L′ becomes smaller. Because the inductance L′ is represented by the next (8) expression, the smaller the electrostatic capacitance Crof the second capacitor of the pseudo-resonant element130becomes, the smaller the inductance L′ becomes.

Here, a specific example of a method of designing the electrostatic capacitance Cmof the first capacitor125is described. Here, the switch control device150switches the first switch U and the fourth switch Y, and the second switch X and the third switch V at the switching frequencies f of 9.9 [kHz] to 7.0 [kHz]. In this case, the frequency of the current Iinvoutputted from the inverter unit120is 9.9 [kHz] to 7.0 [kHz].

The electrostatic capacitance Crof the second capacitor of the pseudo-resonant element130is set to 30 [μF]. The inductance L of the inductive load180of each frequency of the current Iinvoutputted from the inverter unit120is measured in advance, and is as follows.

In this embodiment, resonance is generated by the apparent inductive load210having the synthetic reactance of the pseudo-resonant element130and the inductive load180, and the first capacitor125. However, this resonance can also be regarded as resonance of a capacitor having a synthetic capacitance of the first capacitor125and the pseudo-resonant element130as an electrostatic capacitance, and the inductive load180. Here, there is assumed a capacitor having a synthetic capacitance of the first capacitor125and the pseudo-resonant element130as an electrostatic capacitance. Further, this capacitor is referred to as a synthetic capacitor. Further, an electrostatic capacitance of the synthetic capacitor is set as Cres. In that case, because the electrostatic capacitance Cresof the synthetic capacitor resonates with the inductance L of the inductive load180, it is as represented by the next (9) expression.

The electrostatic capacitance Cresof the synthetic capacitor when the frequency of the current Iinvoutputted from the inverter unit120is 9.9 [kHz] is about 10 [μF] (≈1/((2π×9.9×103)2×23.7×10−6). Because the synthetic reactance (=ω×L′) of the pseudo-resonant element130and the inductive load180seen from the inverter unit120is represented by the next (10) expression, the following (11) expression is established.

Since the inductance L′ of the apparent inductive load210is required to be a value exceeding “0” (zero), according to the (11) expression, a relation of the next (12) expression is satisfied.

Under the above condition, it is sufficient to design the electrostatic capacitance Cmof the first capacitor125so that the switching of on and off between the first switch U and the fourth switch Y, and the second switch X and the third switch V is the soft switching.

When the frequency of the current Iinvoutputted from the inverter unit120is 9.9 [kHz], the time period T0in which the voltage Vmerscapplied to the first capacitor125remains “0” (zero) is set to 2.5 [μsec] (T0=2.5 [μsec]). The time period T0in which the voltage Vmerscapplied to the first capacitor125remains “0” (zero) can be represented by the next (13) expression according to the (3) expression.

Here, f is the switching frequency (=9.9 [kHz]) of the inverter unit120. fresis the resonance frequency determined from the electrostatic capacitance Cmof the first capacitor125and the inductance L′ of the apparent inductive load210.

According to this (13) expression, the resonance frequency fresis represented by the next (14) expression, and is about 10.4 [kHz] (≈1/(1/9.9×103−2×(2.5×10−6)).

Here, the angular frequency ωreswhen the frequency is the resonance frequency fresdetermined from the electrostatic capacitance Cmof the first capacitor125and the inductance L′ of the apparent inductive load210is represented by the next (15) expression.
ωres=2πfres(15)

The electrostatic capacitance Cmof the first capacitor125resonates with the inductance L′ of the apparent inductive load210, and therefore the next (16) expression is established.

Because of L=23.7 [μH] and Cr=30 [μF], Cm≈15 [μF] is found by the (16) expression. That is, as the first capacitor125, it is sufficient to utilize a capacitor having an electrostatic capacitance of 15 [μF]. Note that the (16) expression is the one in which the part of the equality of the (5) expression is deformed using the (8) expression. It is sufficient that the electrostatic capacitance Cmof the first capacitor125satisfies the next (17) expression according to the (5) expression.

Next, as Cm=15 [μF], a case where the switch control device150changes the switching frequency f of the inverter unit120to 7.0 [kHz] is described.

Because of L′>0, according to the (8) expression, a value of the electrostatic capacitance Crof the second capacitor of the pseudo-resonant element130is required to satisfy a relational expression of the next (18) expression. The (18) expression is deformed as is the next (19) expression.

The angular frequency ω when the frequency is the switching frequency f of the inverter unit120is 2π×7.0×103[rad/s]. The inductance L of the inductive load180in a case where the switching frequency f of the inverter unit120is 7.0 [kHz] is 24.2 [μH] as described above.

Accordingly, according to the (19) expression, the electrostatic capacitance Crof the second capacitor of the pseudo-resonant element130is required to exceed about 21.4 [μF] (≈1/((2π×7×103)2×24.2×10−6)). Here, since the electrostatic capacitance Crof the second capacitor of the pseudo-resonant element130is 30 [μF], the (19) expression is satisfied. That is, since the value of the inductance L′ of the apparent inductive load210is a positive value, the pseudo-resonant element130and the inductive load180resonate with the first capacitor125.

Further, the inductance L′ of the apparent inductive load210in a case where the switching frequency f of the inverter unit120is 7.0 [kHz] is about 7.0 [μH] (=24.2×10−6−1/((2π×7.0×103)2×30×10−6)) according to the (8) expression. The resonance frequency fresdetermined from the inductance L′ of the apparent inductive load210and the electrostatic capacitance Cmof the first capacitor125is about 15.5 [kHZ] (=1/(2π×√(7.0×10−6×15×10−6)) according to the (5) expression. Accordingly, the resonance frequency fresis higher than 7.0 [kHz]. Consequently, even in a case where the switching frequency f is 7.0 [kHz], the inverter unit120can achieve the soft switching.

The electrostatic capacitance Crof the second capacitor of the pseudo-resonant element130is determined so as to satisfy the (18) expression in accordance with the inductance L of the inductive load180and the switching frequency f. The electrostatic capacitance Cmof the first capacitor125is determined so as to satisfy the (17) expression using the electrostatic capacitance Crof the second capacitor of the pseudo-resonant element130determined as described above. For example, when the inductive load180is the coil for induction heating the object to be heated such as a steel plate and the object to be heated, in the electrostatic capacitance Crof the second capacitor of the pseudo-resonant element130, a proper value is selected from a range of, for example, 6.5 [μF] to 250 [μF], and in the electrostatic capacitance Cmof the first capacitor125, a proper value is selected from a range of, for example, 0.06 [μF] to 20 [μF].

FIG. 6AandFIG. 6Bare charts illustrating one example of operation simulation results of the power supply system100of this embodiment. Waveforms inFIG. 6Aare waveforms when the switching frequency f of the inverter unit120is 9.9 [kHz] and the inductance L of the inductive load180is 23.7 [μH]. Waveforms inFIG. 6Bare waveforms when the switching frequency f of the inverter unit120is 7.0 [kHz] and the inductance L of the inductive load180is 24.2 [μH]. Further, the waveforms illustrated inFIG. 6AandFIG. 6Bare waveforms when the electrostatic capacitance Cmof the first capacitor125is 15 [μF] and the electrostatic capacitance Crof the second capacitor of the pseudo-resonant element130is 30 [μF].

Iinvindicates a current outputted from the inverter unit120. Vinvindicates a voltage outputted from the inverter unit120. Vmerscindicates a voltage applied to the first capacitor125. Note that in FIG.6A andFIG. 6B, Arms denoted beside the waveform of the current Iinvoutputted from the inverter unit120indicates an effective value of the waveform (current Iinv). Further, Vrms denoted beside the waveforms of the voltage Vinvoutputted from the inverter unit120and the voltage Vmerscapplied to the first capacitor125indicates effective values of the waveforms (voltages Vinv, Vmersc).

U-Ygateindicates the switching signal transmitted from the switch control device150to the first switch U and the fourth switch Y. The switch control device150transmits the switching signal V-Xgateopposite to the switching signal indicated by U-Ygateto the second switch X and the third switch V.

InFIG. 6AandFIG. 6B, when the switching signal U-Ygateand the voltage Vmerscapplied to the first capacitor125are observed, it is found that at either switching frequency f, the switching of the the switching signal U-Ygateis performed when a value of the voltage Vmerscapplied to the first capacitor125is “0” (zero). That is, it is found that the first switch U, the second switch X, the third switch V, and the fourth switch Y are each switched between on and off in a state in which the voltage is not applied to the first capacitor125. Accordingly, it is found that the soft switching is achieved. Further, it is also found by the current Iinvoutputted from the inverter unit120that the oscillating current is not generated.

FIG. 7is a chart illustrating simulation results of a power supply system in the invention example and a power supply system in a comparative example in a tabular form. The power supply system in the invention example is the power supply system100of this embodiment. The power supply system in the comparative example is the one in which the pseudo-resonant element130is removed from the power supply system100of this embodiment. Except presence/absence of the pseudo-resonant element130, the power supply system in the invention example and the power supply system in the comparative example are not different from each other. Note that Arms and Vrms illustrated inFIG. 7present effective values similarly toFIG. 6AandFIG. 6B.

FIG. 7illustrates the results of two kinds of the simulations in which the switching frequency f of the inverter unit120is 9.9 [kHz] and 7.0 [kHz]. Further, the electrostatic capacitance Cmof the first capacitor125of each of the power supply systems is [μF]. The electrostatic capacitance Crof the pseudo-resonant element130(second capacitor) of the power supply system in the invention example is 30 [μF]. An electrostatic capacitance of the first capacitor125of the power supply system in the comparative example is 9.3 [μF]. Further, when the switching frequency f is 9.9 [kHz], the inductance L of the inductive load180is 23.7 [μH], and when it is 7.0 [kHz], it is 24.2 [μH]. Further, in the simulations, the inverter units120in the invention example and the comparative example output the same current.

As illustrated inFIG. 7, it is indicated that at either switching frequency f, the voltage Vinvoutputted from the inverter unit120is smaller in the power supply system100in the invention example. As a result, a power supply capacity of the inverter unit120of the power supply system100in the invention example is smaller than a power supply capacity of the inverter unit120of the power supply system in the comparative example. That is, using the pseudo-resonant element130makes it possible to reduce the power supply capacity of the inverter unit120of the power supply system.

Modified Example

In this embodiment, the description has been made by citing a case where the pseudo-resonant element130is constituted of the second capacitor as the example. However, it is sufficient that the pseudo-resonant element130includes the second capacitor. Further, the second capacitor may be one capacitor, or may be a plurality of capacitors connected to each other. The above plurality of capacitors may be connected to each other in series or connected to each other in parallel, or a portion connected in series and a portion connected in parallel may mix together. When the second capacitor is constituted by the plurality of capacitors connected to each other, the electrostatic capacitance Crof the second capacitor of the pseudo-resonant element130is a synthetic capacitance of the above plurality of capacitors in the description of this embodiment.

Further, when a capacitive reactance based on the electrostatic capacitance of the second capacitor included in the pseudo-resonant element130is larger than an inductive reactance of the inductive load180, the pseudo-resonant element130may have a reactor in addition to the second capacitor. However, similarly to the description of this embodiment, a value of the inductive reactance on the inductive load180side rather than an output end of the magnetic energy recovery switch is set to exceed a value of the capacitive reactance on the inductive load180side rather than the output end of the magnetic energy recovery switch.

In this case, in the description of this embodiment, for example, it is sufficient that the inductance L of the inductive load180is replaced with a synthetic inductance of the inductive load180and the reactor included in the pseudo-resonant element130. Accordingly, a value of a synthetic reactance of an inductive reactance of the pseudo-resonant element130and the inductive reactance of the inductive load180is set to exceed a value of the capacitive reactance of the pseudo-resonant element130. In that case, the electrostatic capacitance Crof the second capacitor becomes a value exceeding a reciprocal of a value obtained by multiplying a synthetic inductance of an inductance of the pseudo-resonant element130and an inductance of the inductive load180, and the square of the angular frequency ω (=2πf) corresponding to the switching frequency f at which the first switch U, the second switch X, the third switch V, and the fourth switch Y are switched. That is, the electrostatic capacitance Crof the second capacitor satisfies a condition that sets L in the (19) expression as the synthetic inductance of the inductance of the pseudo-resonant element130and the inductance of the inductive load180.

Further, in this embodiment, the description has been made by citing a case where the first capacitor125is constituted of one capacitor as the example. However, it is sufficient that the first capacitor125is constituted by using at least one capacitor. The one in which a plurality of capacitors are connected to each other may be used as the first capacitor125. The above plurality of capacitors may be connected to each other in series or connected to each other in parallel, or a portion connected in series and a portion connected in parallel may mix together. In this case, the electrostatic capacitance Cmof the first capacitor125is a synthetic capacitance of the above plurality of capacitors in the description of this embodiment.

Second Embodiment

Next, a second embodiment is described. In this embodiment, a power supply system capable of adjusting a current Iinvoutputted from the inverter unit120is described. Specifically, a transformer is disposed between an inverter unit120, and a pseudo-resonant element130and an inductive load180. In this embodiment as described above, the transformer is added to the power supply system of the first embodiment. Accordingly, in the description of this embodiment, the same parts as those of the first embodiment are denoted by the same reference signs as the reference signs denoted inFIG. 1toFIG. 7, or the like, thereby omitting a detailed description. Further, also in this embodiment, similarly to the first embodiment, the description is made by citing a case where the pseudo-resonant element130is constituted of a second capacitor as the example.

FIG. 8is a view illustrating one example of a configuration of a power supply system800. The power supply system800has a transformer810in addition to a direct-current power supply unit110, an inverter unit120, a pseudo-resonant element130, a current transformer140, a switch control device150, a current control device160, and a frequency setting device170. Note that the power supply system800does not have a specific device (oscillation suppression circuit) for suppressing an oscillating current.

The transformer810increases or decreases a voltage Vinvoutputted from the inverter unit120. One end of a primary winding (winding on an input side) of the transformer810and a second alternating-current terminal122are connected to each other. The other end of the primary winding of the transformer810and a first alternating-current terminal121are connected to each other. One end of a secondary winding (winding on an output side) of the transformer810and one end of the pseudo-resonant element130are connected to each other. The other end of the secondary winding of the transformer810and the other end of the inductive load180are connected to each other. Note that one end of the inductive load180is connected to the other end of the pseudo-resonant element130.

Here, a turns ratio of the transformer810is set as n. A turns ratio n is set as a value (n=the number of turns of the primary winding÷the number of turns of the secondary winding) obtained by dividing the number of turns of the primary winding of the transformer810by the number of turns of the secondary winding thereof. When the transformer810is a step-down transformer, the turns ratio n exceeds 1. When the transformer810is a step-up transformer, the turns ratio n is below 1.

Hereinafter, in order to simplify the description, the transformer810is set to be an ideal transformer. A primary voltage (voltage applied to the primary winding) of the transformer810is the voltage Vinvoutputted from the inverter unit120. A secondary voltage (voltage generated in the secondary winding) of the transformer810is represented by the product (=(1/n) Vinv) of the primary voltage and a reciprocal of the turns ratio n. Further, a primary current (current flowing through the primary winding) of the transformer810is a current Iinvoutputted from the inverter unit120. A secondary current (current flowing through the secondary winding) of the transformer810is represented by the product (=n Iinv) of the primary current and the turns ratio n. Accordingly, a current flowing through the inductive load180is n times the current Iinvoutputted from the inverter unit120.

When the step-down transformer is used as the transformer810, the current flowing through the inductive load180is larger than the current Iinvoutputted from the inverter unit120. On the other hand, when the step-up transformer is used as the transformer810, the current flowing through the inductive load180is smaller than the current Iinvoutputted from the inverter unit120. Accordingly, in the power supply system800of this embodiment, the current flowing through the inductive load180can be adjusted by the turns ratio n of the transformer810. When the step-down transformer is used as the transformer810, it is possible to pass a large current through the inductive load180without passing a large current through the inverter unit120. Consequently, for example, as a first switch U, a second switch X, a third switch V, a fourth switch Y, and a first capacitor125, elements for large current need not be used.

An impedance Z when the inductive load180side is seen from an output end of the inverter unit120is represented by the next (20) expression.

Here, R is a resistance [Ω] of the inductive load180. L is an inductance [H] of the inductive load180. Cris an electrostatic capacitance [F] of the second capacitor of the pseudo-resonant element130. n is the turns ratio of the transformer810. j is an imaginary unit.

As described in the first embodiment, the synthetic reactance (=ω×L′) of the pseudo-resonant element130and the inductive load180seen from the inverter unit120is represented by the (10) expression. Further, since the inductance L′ of the apparent inductive load210is required to exceed “0” (zero), according to the (11) expression, the (12) expression is established. On the other hand, in this embodiment, a synthetic reactance (=ω×L′) of the pseudo-resonant element130and the inductive load180seen from the inverter unit120is the one indicated in parentheses of the second term in the right-hand side of the (20) expression. Consequently, in order that an inductance L′ of the apparent inductive load210exceeds “0” (zero), it is necessary to satisfy the next (21) expression.

According to the (21) expression, the (12) expression is established. That is, even though the transformer810is present, the electrostatic capacitance Crof the second capacitor of the pseudo-resonant element130is determined in the same manner as that in the first embodiment.

Further, according to the (20) expression, in this embodiment, the inductance L′ of the apparent inductive load210is represented by the next (22) expression.

Accordingly, when the (22) expression is substituted for the (5) expression, the following (23) expression is established.

Consequently, in this embodiment, it is sufficient that an electrostatic capacitance Cmof the first capacitor125is designed so as to satisfy the (23) expression instead of the (17) expression.

Note that also in this embodiment, the modified example described in the first embodiment can be employed.

Third Embodiment

Next, a third embodiment is described. In the first embodiment and the second embodiment, the description has been made by citing a case where the magnetic energy recovery switch is constituted by the full-bridge circuit as the example. In contrast with this, in this embodiment, the description is made by citing a case where a magnetic energy recovery switch is constituted by a half-bridge circuit as an example. As described above, a configuration of the magnetic energy recovery switch of this embodiment is mainly different from those of the first embodiment and the second embodiment. Accordingly, in the description of this embodiment, the same parts as those of the first embodiment and the second embodiment are denoted by the same reference signs as the reference signs denoted inFIG. 1toFIG. 8, or the like, thereby omitting a detailed description.

FIG. 9is a view illustrating one example of a configuration of a power supply system900. The power supply system900has a direct-current power supply unit110, an inverter unit920, a pseudo-resonant element130, a current transformer140, a switch control device150, a current control device160, and a frequency setting device170. Note that the power supply system900does not have a specific device (oscillation suppression circuit) for suppressing an oscillating current.

The inverter unit920converts direct-current power outputted from the direct-current power supply unit110into alternating-current power with the same frequency as a switching frequency at which each switch of the inverter unit920is switched, similarly to the inverter units120of the first embodiment and the second embodiment. Then, the inverter unit920supplies the alternating-current power with the frequency to an inductive load180. The inverter unit920has a magnetic energy recovery switch.

One example of a configuration of the inverter unit920(magnetic energy recovery switch) of this embodiment is described.

The inverter unit920has a first switch U, a second switch X, a first diode D5, a second diode D6, a first alternating-current terminal921, second alternating-current terminals922,925, a first direct-current terminal923, a second direct-current terminal924, and a plurality of first capacitors. In this embodiment, the inverter unit920has a high-side capacitor926and a low-side capacitor927as the plurality of first capacitors.

The first switch U is the same as the first switch U described in the first embodiment. The second switch X is the same as the second switch X described in the first embodiment. Accordingly, here, a detailed description of the first switch U and the second switch X is omitted. Similarly to the first embodiment, a connection point of an end portion on a forward direction side of each of free-wheeling diodes D1and D2and an end portion on a backward side to a forward direction of each of self-arc-extinguishing elements S1and S2is set as a negative electrode terminal. A connection point of an end portion on a forward direction side of each of the self-arc-extinguishing elements S1and S2and an end portion on a backward side to a forward direction of each of the free-wheeling diodes D1and D2is set as a positive electrode terminal.

The diodes D5and D6each have a first end portion and a second end portion. The diodes D5and D6each have only a state of passing a current from the first end portion to the second end portion but not passing a current from the second end portion to the first end portion as a conduction state. A direction from the first end portion to the second end portion of each of the diodes D5and D6is set as a forward direction in each of the diodes D5and D6. The first end portion of each of the diodes D5and D6is set as a negative electrode terminal. The second end portion of each of the diodes D5and D6is set as a positive electrode terminal.

A connection configuration of each part of the inverter unit920is described.

The negative electrode terminal of the first switch U and the positive electrode terminal of the second switch X are connected to each other. The negative electrode terminal of the first diode D5and the positive electrode terminal of the second diode D6are connected to each other. The positive electrode terminal of the first switch U and the positive electrode terminal of the first diode D5are connected to each other. The negative electrode terminal of the second switch X and the negative electrode terminal of the second diode D6are connected to each other.

The first alternating-current terminal921is connected to a connection point of the negative electrode terminal of the first switch U and the positive electrode terminal of the second switch X. The second alternating-current terminals922and925are connected to a connection point of the negative electrode terminal of the first diode D5and the positive electrode terminal of the second diode D6. To the second alternating-current terminals922and925, one end of the pseudo-resonant element130is connected. In this embodiment, the first alternating-current terminal921and the second alternating-current terminals922and925are output ends of the inverter unit920. Note that inFIG. 9, the two second alternating-current terminals922and925are illustrated as a matter of convenience of a notation, but these can be regarded as one terminal.

The first direct-current terminal923is connected to a connection point of the positive electrode terminal of the first switch U and the positive electrode terminal of the first diode D5. To the first direct-current terminal923, the other end of a reactor113is connected. The second direct-current terminal924is connected to a connection point of the negative electrode terminal of the second switch X and the negative electrode terminal of the second diode D6. To the second direct-current terminal924, the other end on an output side of a rectifier112is connected. In this embodiment, the first direct-current terminal923and the second direct-current terminal924are input ends of the inverter unit920. The direct-current power supply unit110is connected between the first direct-current terminal923and the second direct-current terminal924as described above.

The high-side capacitor926is connected between the connection point of the positive electrode terminal of the first switch U and the positive electrode terminal of the first diode D5and the connection point of the negative electrode terminal of the first diode D5and the positive electrode terminal of the second diode D6. As described above, to the connection point of the positive electrode terminal of the first switch U and the positive electrode terminal of the first diode D5, the first direct-current terminal923is also connected. Further, to the connection point of the negative electrode terminal of the first diode D5and the positive electrode terminal of the second diode D6, the second alternating-current terminal922is also connected. The high-side capacitor926is a capacitor having polarity.

The low-side capacitor927is connected between the connection point of the negative electrode terminal of the second switch X and the negative electrode terminal of the second diode D6and the connection point of the negative electrode terminal of the first diode D5and the positive electrode terminal of the second diode D6. As described above, to the connection point of the negative electrode terminal of the second switch X and the negative electrode terminal of the second diode D6, the second direct-current terminal924is also connected. Further, to the connection point of the negative electrode terminal of the first diode D5and the positive electrode terminal of the second diode D6, one end of the high-side capacitor926is connected. That is, one end of the high-side capacitor926which is one first capacitor and one end of the low-side capacitor927which is the other first capacitor, of the high-side capacitor926and the low-side capacitor927constituting the plurality of first capacitors, are connected to each other. The low-side capacitor927is a capacitor having polarity.

An inductive load180is connected in series with respect to the high-side capacitor926and the low-side capacitor927between the first alternating-current terminal921and the second alternating-current terminals922and925of the inverter unit920. In the example illustrated inFIG. 9, one end of the inductive load180and the other end of the pseudo-resonant element130are connected to each other. The other end of the inductive load180and the first alternating-current terminal921of the inverter unit920are connected to each other. The inductive load180is connected between the first alternating-current terminal921and the second alternating-current terminals922and925as described above. Further, the pseudo-resonant element130is connected in series with respect to the inductive load180between the first alternating-current terminal921and the second alternating-current terminals922and925.

Next, one example of an operation of the inverter unit920is described.FIG. 10is a view explaining one example of a flow of a current in the inverter unit920.FIG. 11Ais a chart explaining a first example of a relationship among a switching signal Ugateof the first switch U, a voltage Vmersc1applied to the high-side capacitor926, a voltage Vmersc2applied to the low-side capacitor927, and a current Iinvoutputted from the inverter unit920.FIG. 11Bis a chart explaining a second example of a relationship among a switching signal Ugateof the first switch U, a voltage Vmersc1applied to the high-side capacitor926, a voltage Vmersc2applied to the low-side capacitor927, and a current Iinvoutputted from the inverter unit920.

First, one example of an operation of the inverter unit920when a time period T0in which the voltages Vmersc1and Vmersc2applied to the high-side capacitor926and the low-side capacitor927remain “0” (zero) exceeds “0” (zero) is described.

An initial state is set as a state in which the high-side capacitor926is charged, a discharge of the low-side capacitor927finishes, the first switch U is on, and the second switch X is off.

As illustrated in a state A inFIG. 10, when the high-side capacitor926starts discharging, a current discharged from the high-side capacitor926goes to the first direct-current terminal923. Since the first switch U is on, the current flowing into the first direct-current terminal923flows via the first switch U toward the first alternating-current terminal921. Then, since the second switch X is off, the current flowing into the first alternating-current terminal921cannot flow through the positive electrode terminal side of the second switch X and flows toward the inductive load180and the pseudo-resonant element130. The current passing the pseudo-resonant element130flows into the second alternating-current terminal922, and goes back to the high-side capacitor926.

Changes of voltages applied to the high-side capacitor926and the low-side capacitor927after the high-side capacitor926starts discharging and a change of a current outputted from the inverter unit920are described usingFIG. 11A. Ugateis a signal which the switch control device150transmits to the first switch U, and an on and off switching signal of the first switch U. Note that when the switching signal Ugateindicates an on value, the first switch U is in an on state, and when the switching signal Ugateindicates an off value, the first switch U is in an off state. Further, although an illustration is omitted here, the switch control device150also transmits a switching signal Xgateto the second switch X. A value of the switching signal Xgateindicates a value opposite to the switching signal transmitted to the first switch U. That is, the value of the switching signal Xgateindicates an off value when the switching signal Ugateindicates the on value, and it indicates an on value when the switching signal Ugateindicates the off value. Vmersc1indicates a voltage applied to the high-side capacitor926. Vmersc2indicates a voltage applied to the low-side capacitor927. Iinvindicates a current outputted from the inverter unit920. t0indicates a time at which the high-side capacitor926starts discharging.

When the high-side capacitor926starts discharging, the current Iinvoutputted from the inverter unit920increases in a minus direction, and the voltage Vmersc1applied to the high-side capacitor926starts decreasing. When the high-side capacitor926finishes discharging, the voltage Vmersc1applied to the high-side capacitor926becomes “0” (zero). t1indicates a time at which the high-side capacitor926finishes discharging. At the time t0, the discharge of the low-side capacitor927finishes. Further, in a time period of the time t0to a time t1, a current does not flow through the low-side capacitor927. Accordingly, the voltage Vmersc2applied to the low-side capacitor927in this time period is “0” (zero).

At the time t1, when the discharge of the high-side capacitor926finishes, the current Iinvoutputted from the inverter unit920reaches a peak value, and the voltage Vmersc1of the high-side capacitor926becomes “0” (zero). Accordingly, a voltage between the first direct-current terminal923and the second direct-current terminal924becomes “0” (zero). In this case, as illustrated in a state B inFIG. 10, the current flowing into the second alternating-current terminal922goes via the diode D5to the first direct-current terminal923, and goes via the first switch U to the first alternating-current terminal921. In this case, the voltages Vmersc1and Vmersc2applied to the high-side capacitor926and the low-side capacitor927are “0” (zero). Accordingly, voltages applied to the first switch U and the second switch X also are “0” (zero). The time period in which the voltages Vmersc1and Vmersc2applied to the high-side capacitor926and the low-side capacitor927are “0” (zero) is set as T0.

In a state B inFIG. 10, the current flowing through the inverter unit920and the inductive load180gradually decreases according to a time constant determined from an inductance and a resistance component of the inductive load180. As illustrated inFIG. 11A, the current Iinvoutputted from the inverter unit920decreases in the time period of the time t1to a time t2.

The switch control device150switches the first switch U to off and the second switch X to on at the time t2at which the time period T0passes from the time t1at which the discharge of the high-side capacitor926finishes. At this time, the voltages Vmersc1and Vmersc2applied to the high-side capacitor926and the low-side capacitor927are “0” (zero), thereby resulting in soft switching.

When the first switch U is switched to off and the second switch X is switched to on, the current flowing into the second alternating-current terminals922and925goes to the low-side capacitor927since the first switch U is off as illustrated in a state C inFIG. 10. The current flowing into the low-side capacitor927is utilized for a charge of the low-side capacitor927, and gradually decreases. This current flows as illustrated in the state C inFIG. 10until the low-side capacitor927finishes charging, and becomes “0” (zero) at a time point at which the charge of the low-side capacitor927finishes. InFIG. 11A, the low-side capacitor927finishes charging at a time t3.

As illustrated inFIG. 11A, the voltage Vmersc2applied to the low-side capacitor927rises between the time t2and the time t3. Further, in accordance with a rise in the voltage Vmersc2applied to the low-side capacitor927, the current Iinvoutputted from the inverter unit920decreases. When the charge of the low-side capacitor927finishes at the time t3, the voltage Vmersc2applied to the low-side capacitor927reaches a peak value. At this time, the current Iinvoutputted from the inverter unit920becomes “0” (zero). At the time t1, the discharge of the high-side capacitor926finishes. Further, in a time period of the time t1to the time t3, a current does not flow through the high-side capacitor926. Accordingly, the voltage Vmersc1applied to the high-side capacitor926in this time period is “0” (zero).

After the charge of the low-side capacitor927finishes, the low-side capacitor927starts discharging. As illustrated in a state D inFIG. 10, the current discharged from the low-side capacitor927goes to the second alternating-current terminals922and925. Since the first switch U is off, this current flows into the pseudo-resonant element130and the inductive load180. The current flowing into the inductive load180goes to the first alternating-current terminal921, and flows into the first alternating-current terminal921. The current flowing into the first alternating-current terminal921goes via the second switch X back to the low-side capacitor927since the first switch U is off and the second switch X is on. That is, a direction of the current flowing into the pseudo-resonant element130and the inductive load180is opposite to those in the states A to C. Thus, by switching on and off of the first switch U and the second switch X at a switching frequency f set by the switch control device150, the inverter unit920outputs the current Iinvwith the same frequency as the switching frequency f.

InFIG. 11A, the low-side capacitor927finishes discharging at a time t4. As illustrated inFIG. 11A, the voltage Vmersc2applied to the low-side capacitor927continues decreasing from the time t3in accordance with the discharge of the low-side capacitor927, and becomes “0” (zero) at the time t4. Further, the current Iinvoutputted from the inverter unit920increases in a direction opposite to a direction in the time t0to the time t3in accordance with the discharge of the low-side capacitor927. Then, the current Iinvoutputted from the inverter unit920reaches a peak value in a direction opposite to a direction in the time t0to the time t3at the time t4at which the discharge of the low-side capacitor921finishes.

A direction of the current Iinvoutputted from the inverter unit920between the time t3and the time t4is opposite compared with that of the current Iinvoutputted from the inverter unit920between the time t0and the time t1. Therefore, in a graph inFIG. 11A, a value of the current Iinvoutputted from the inverter unit920between the time t3and the time t4is a plus value. Note that also in a time period of the time t3to the time t4, because a current does not flow through the high-side capacitor926, the voltage Vmersc1applied to the high-side capacitor926is “0” (zero).

At the time t4, when the discharge of the low-side capacitor927finishes, the voltage Vmersc2applied to the low-side capacitor927becomes “0” (zero). Accordingly, a voltage between the first direct-current terminal923and the second direct-current terminal924becomes “0” (zero). In this case, as illustrated in a state E inFIG. 10, the current flowing into the first alternating-current terminal921goes via the second switch X to the second direct-current terminal924, and goes via the second diode D6to the second alternating-current terminal922.

In the state E inFIG. 10, the current flowing through the inverter unit920and the inductive load180gradually approaches “0” (zero) according to the time constant based on the inductance and the resistance component of the inductive load180. As illustrated inFIG. 11A, the current Iinvoutputted from the inverter unit920approaches “0” (zero) in the time period of the time t4to a time t5.

The switch control device150switches the first switch U to on and switches the second switch X to off at the time t5at which the time period T0passes from the time t4at which the discharge of the low-side capacitor927finishes. At this time, the voltages Vmersc1and Vmersc1applied to the high-side capacitor926and the low-side capacitor927are “0” (zero), thereby resulting in the soft switching.

When the first switch U is switched to on and the second switch X is switched to off, the current flowing into the first alternating-current terminal921goes via the first switch U to the first direct-current terminal923since the first switch U is on and the second switch X is off as illustrated in a state F inFIG. 10. The current flowing into the first direct-current terminal923goes to the high-side capacitor926. The current flowing into the high-side capacitor926approaches “0” (zero) further. This current flows as illustrated in the state F inFIG. 10until the charge of the high-side capacitor926finishes, and becomes “0” (zero) at the time point at which the charge of the high-side capacitor926finishes.

As illustrated inFIG. 11A, the voltage Vmersc1applied to the high-side capacitor926rises between the time t5and a time t6. Further, in accordance with a rise in the voltage Vmersc1applied to the high-side capacitor926, the current Iinvoutputted from the inverter unit920approaches “0” (zero). When the charge of the high-side capacitor926finishes at the time t6, the voltage Vmersc1applied to the high-side capacitor926reaches a peak value. At this time, the current Iinvoutputted from the inverter unit920becomes “0” (zero). At the time t4, the discharge of the low-side capacitor927finishes. Further, in a time period of the time t4to the time t6, a current does not flow through the low-side capacitor927. Accordingly, the voltage Vmersc2applied to the low-side capacitor927in this time period is “0” (zero).

At the time t6, when the charge of the high-side capacitor926finishes, the first switch U is on and the second switch X is off, thereby returning to the state A which is the initial state. The inverter unit920repeats the above operation.

As illustrated in the state C inFIG. 10, at a time of the charge of the low-side capacitor927, the current flows from the second alternating-current terminals922and925into the low-side capacitor927. Further, as illustrated in the state F inFIG. 10, at a time of the charge of the high-side capacitor926, the current flows from the first direct-current terminal923into the high-side capacitor926. That is, in the high-side capacitor926, necessarily, a positive electric charge accumulates on the first direct-current terminal923side and a negative electric charge accumulates on the second alternating-current terminal922and925sides. In the low-side capacitor927, necessarily, a positive electric charge accumulates on the second alternating-current terminal922and925sides and a negative electric charge accumulates on the second direct-current terminal924side. Therefore, as the high-side capacitor926and the low-side capacitor927, capacitors having polarity can be used. Further, a direction of a current flowing into a second capacitor included in the pseudo-resonant element130is not fixed. Therefore, as the second capacitor, the capacitor having polarity cannot be used, but a nonpolar capacitor is used.

As illustrated inFIG. 11A, as the current Iinvoutputted from the inverter unit920, the current for one cycle of the alternating current is outputted. That is, the inverter unit920outputs the alternating current with the same frequency as the switching frequency f. In this embodiment, the switching frequency at which the first switch U and the second switch X are switched is an output frequency of the magnetic energy recovery switch.

FIG. 11Aillustrates a case where the time period T0in which the voltages Vmersc1and Vmersc2applied to the high-side capacitor926and the low-side capacitor927remain “0” (zero) exceeds (zero). In contrast with this,FIG. 11Billustrates a case where the time period T0in which the voltages Vmersc1and Vmersc2applied to the high-side capacitor926and the low-side capacitor927remain “0” (zero) is “0” (zero). Hereinafter, one example of an operation of the inverter unit920when the time period T0in which the voltages Vmersc1and Vmersc2applied to the high-side capacitor926and the low-side capacitor927remain “0” (zero) is “0” (zero) is described.

An initial state is set as a state in which the high-side capacitor926is charged, the discharge of the low-side capacitor927finishes, the first switch U is on, and the second switch X is off.

When the time period T0in which the voltages Vmersc1and Vmersc2applied to the high-side capacitor926and the low-side capacitor927remain “0” (zero) is “0” (zero), the high-side capacitor926performs the discharge between the time t0and the time t1as illustrated inFIG. 11B. Then, the voltage Vmersc1applied to the high-side capacitor926becomes “0” (zero) at the time t1. The operation of the inverter unit920between the time t0and the time t1illustrated inFIG. 11Bis the same as the operation of the inverter unit920between the time t0and the time t1illustrated inFIG. 11A.

In the example illustrated inFIG. 11A, the time period T0in which the voltages Vmersc1and Vmersc2applied to the high-side capacitor926and the low-side capacitor927remain “0” (zero) is set after the time t1. In contrast with this, in the example illustrated inFIG. 11B, the time period T0in which the voltages Vmersc1and Vmersc2applied to the high-side capacitor926and the low-side capacitor927remain “0” (zero) is “0” (zero). Accordingly, the switch control device150switches the first switch U to off and switches the second switch X to on at the time t1at which the discharge of the high-side capacitor926finishes (namely, without keeping time from when the discharge of the high-side capacitor926finishes).

In that case, the low-side capacitor927performs the charge between the time t1and the time t2, and performs the discharge between the time t2and the time t3. Then, the voltage Vmersc2applied to the low-side capacitor927becomes “0” (zero) at the time t3. In the example illustrated inFIG. 11Bas described above, the first switch U and the second switch X change from the state A to the state C inFIG. 10, and do not change to the state B. The operation of the inverter unit920between the time t1and the time t3illustrated inFIG. 11Bis the same as the operation of the inverter unit920between the time t2and the time t4illustrated inFIG. 11A.

Thereafter, in the example illustrated inFIG. 11A, the time period T0in which the voltage Vmersc2applied to the low-side capacitor927remains “0” (zero) is set. In contrast with this, in the example illustrated inFIG. 11B, the time period T0in which the voltage Vmersc2applied to the low-side capacitor927remains “0” (zero) is “0” (zero). Accordingly, the switch control device150switches the first switch U to on and switches the second switch X to off at the time t3at which the discharge of the low-side capacitor927finishes (namely, without keeping time from when the discharge of the low-side capacitor927finishes).

In that case, the high-side capacitor926performs the charge between the time t3and the time t4. In the example illustrated inFIG. 11Bas described above, the first switch U and the second switch X change from the state D to the state F inFIG. 10, and do not change to the state E. The operation of the inverter unit920between the time t3and the time t4illustrated inFIG. 11Bis the same as the operation of the inverter unit920between the time t5and the time t6illustrated inFIG. 11A.

As illustrated inFIG. 11B, from the time t0, the current Iinvoutputted from the inverter unit920increases in a minus direction with the discharge of the high-side capacitor926. Then, the current Iinvoutputted from the inverter unit920reaches a peak value at the time t1at which the discharge of the high-side capacitor926finishes. From the time t1, the current Iinvoutputted from the inverter unit920approaches “0” (zero) with the charge of the low-side capacitor927. Then, the current Iinvoutputted from the inverter unit920becomes “0” (zero) at the time t2at which the charge of the low-side capacitor927finishes.

From the time t2, the direction of the current Iinvoutputted from the inverter unit920is opposite to the direction in the time t0to the time t2. From the time t2, the current Iinvoutputted from the inverter unit920increases in the direction opposite to the direction in the time t0to the time t2with the discharge of the low-side capacitor927. Then, the current Iinvoutputted from the inverter unit920reaches a peak value in the direction opposite to the direction in the time t0to the time t2at the time t3at which the discharge of the low-side capacitor927finishes. From the time t3, The current Iinvoutputted from the inverter unit920approaches “0” (zero) with the charge of the high-side capacitor926. Then, the current Iinvoutputted from the inverter unit920becomes “0” (zero) at the time t4at which the charge of the high-side capacitor926finishes.

The switch control device150switches on and off between the first switch U and the second switch X at the time t1and the time t3at which the voltages Vmersc1and Vmersc2applied to the high-side capacitor926and the low-side capacitor927become “0” (zero). This allows the switch control device150to achieve the soft switching even when the time period T0in which the voltages Vmersc1and Vmersc2applied to the high-side capacitor926and the low-side capacitor927remain “0” (zero) is “0” (zero).

Further, the time period taken to charge and the time period taken to discharge the high-side capacitor926and the low-side capacitor927are a half cycle of a resonance frequency determined from electrostatic capacitances Cm1and Cm2of the high-side capacitor926and the low-side capacitor927, and the inductance L′ of the apparent inductive load210. Therefore, as illustrated inFIG. 11B, when the time period T0in which the voltages Vmersc1and Vmersc2applied to the high-side capacitor926and the low-side capacitor927remain “0” (zero) is “0” (zero), a frequency of the current Iinvoutputted from the inverter unit920is equal to the resonance frequency determined from each of the electrostatic capacitances Cm1and Cm2of the high-side capacitor926and the low-side capacitor927, and the inductance L′ of the apparent inductive load210.

As is apparent from the above description, by switching on and off between the first switch U and the second switch X, the high-side capacitor926and the low-side capacitor927and the pseudo-resonant element130are disposed in series on a path of the alternating current flowing through part of the first switch U and the second switch X.

A design of the electrostatic capacitances Cm1and Cm2of the high-side capacitor926and the low-side capacitor927can be achieved by replacing the electrostatic capacitance Cmof the first capacitor125described in the first embodiment with each of the electrostatic capacitances Cm1and Cm2of the high-side capacitor926and the low-side capacitor927. For example, when both the electrostatic capacitances Cm1and Cm2of the high-side capacitor926and the low-side capacitor927are set as Cm, the electrostatic capacitances Cm1and Cm2of the high-side capacitor926and the low-side capacitor927are determined in the same manner as that in the electrostatic capacitance Cmof the first capacitor125described in the first embodiment.

That is, the electrostatic capacitances Cm1and Cm2of the high-side capacitor926and the low-side capacitor927are required to satisfy the following (24) expression and (25) expression. The power supply system900is required to have the high-side capacitor926and the low-side capacitor927, the pseudo-resonant element130, and the inductive load180such as to satisfy the (24) expression and the (25) expression when the switching frequency of the inverter unit920is f.

(Method of Reducing Power Supply Capacity of Inverter Unit920)

An electrostatic capacitance Crof the second capacitor of the pseudo-resonant element130and the electrostatic capacitances Cm1and Cm2of the high-side capacitor926and the low-side capacitor927are the ones in which the electrostatic capacitance Cmof the first capacitor125is replaced with each of the electrostatic capacitances Cm1and Cm2of the high-side capacitor926and the low-side capacitor927in the section (Method of reducing power supply capacity of inverter unit120) described in the first embodiment.

That is, it is sufficient that the electrostatic capacitances Cm1and Cm2of the high-side capacitor926and the low-side capacitor927satisfy the next (26) expression and (27) expression.

In other words, it is sufficient that each of the electrostatic capacitances Cm1and Cm2of the high-side capacitor926and the low-side capacitor927satisfies the (17) expression described in the first embodiment. Further, it is sufficient that the electrostatic capacitance Crof the second capacitor of the pseudo-resonant element130satisfies the (19) expression described in the first embodiment.

As described above, even though the magnetic energy recovery switch is constituted by the half-bridge circuit, the effect described in the first embodiment can be obtained.

Note that also in this embodiment, the modified example described in the first embodiment can be employed. Further, this embodiment may be applied to the second embodiment. In this case, each of the electrostatic capacitances Cm1and Cm2of the high-side capacitor926and the low-side capacitor927is set to satisfy the (23) expression described in the second embodiment.

It should be noted that the above embodiments merely illustrate concrete examples of implementing the present invention, and the technical scope of the present invention is not to be construed in a restrictive manner by these embodiments. That is, the present invention may be implemented in various forms without departing from the technical spirit or main features thereof.

INDUSTRIAL APPLICABILITY

The present invention can be utilized for energization, heating, or the like by alternating-current power.