High efficiency driving circuit

A high efficiency driving circuit includes a first P-type metal-oxide-semiconductor transistor, a second P-type metal-oxide-semiconductor transistor, a first N-type metal-oxide-semiconductor transistor, a second N-type metal-oxide-semiconductor transistor, a current source, a third N-type metal-oxide-semiconductor transistor, a fourth N-type metal-oxide-semiconductor transistor, a fifth N-type metal-oxide-semiconductor transistor, a first resistor, and a second resistor. The first P-type metal-oxide-semiconductor transistor charges a third terminal of the first P-type metal-oxide-semiconductor transistor according to a first control signal, and the first N-type metal-oxide-semiconductor transistor discharges the third terminal of the first P-type metal-oxide-semiconductor transistor according to a second control signal. A high voltage level of the first control signal is at a first voltage, and a low voltage level of the first control signal is at a third voltage; a high voltage level of the second control signal is at a fourth voltage, and a low voltage level of the second control signal is ground.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is related to a driving circuit, and particularly to a driving circuit that can be applied to a direct current voltage/direct current voltage converter of a partial high voltage complementary metal-oxide-semiconductor process.

2. Description of the Prior Art

Please refer toFIG. 1.FIG. 1is a diagram illustrating a direct current voltage/direct current voltage converter100according to the prior art. The direct current voltage/direct current voltage converter100includes a buffer102and a switch104, where the switch104is a P-type metal-oxide-semiconductor transistor. In a partial high voltage complementary metal-oxide-semiconductor process (that is, a process in which a drain of a metal-oxide-semiconductor transistor can endure a high voltage, but thickness of a gate of the metal-oxide-semiconductor transistor is not increased), because a gate of the switch104can not endure a high voltage, voltage levels of a control signal CS generated by the buffer102must be between a first voltage HV and a low voltage LV, where the low voltage LV is equal to the first voltage HV minus a source-to-gate voltage VSG of the switch104.

In the prior art, because size of the switch104is very large and the switch104is a metal-oxide-semiconductor transistor of the partial high voltage complementary metal-oxide-semiconductor process, the buffer102requires very large current to generate the control signal CS and switch the switch104rapidly, resulting in energy conversion efficiency of the direct current voltage/direct current voltage converter100being lower.

SUMMARY OF THE INVENTION

An embodiment provides a high efficiency driving circuit. The high efficiency driving circuit includes a first P-type metal-oxide-semiconductor transistor, a second P-type metal-oxide-semiconductor transistor, a first N-type metal-oxide-semiconductor transistor, a second N-type metal-oxide-semiconductor transistor, a current source, a third N-type metal-oxide-semiconductor transistor, a fourth N-type metal-oxide-semiconductor transistor, a fifth N-type metal-oxide-semiconductor transistor, a first resistor, and a second resistor. The first P-type metal-oxide-semiconductor transistor has a first terminal for receiving a first voltage, a second terminal for receiving a first control signal, and a third terminal for coupling to a third P-type metal-oxide-semiconductor transistor. The second P-type metal-oxide-semiconductor transistor has a first terminal for receiving the first voltage, a second terminal for coupling to the third P-type metal-oxide-semiconductor transistor, and a third terminal. The first N-type metal-oxide-semiconductor transistor has a first terminal coupled to the third terminal of the first P-type metal-oxide-semiconductor transistor, a second terminal for receiving a second control signal, and a third terminal. The second N-type metal-oxide-semiconductor transistor has a first terminal coupled to the third terminal of the first N-type metal-oxide-semiconductor transistor, a second terminal, and a third terminal coupled to ground. The current source has a first terminal for receiving a second voltage, and a second terminal, where the current source is used for providing first current. The third N-type metal-oxide-semiconductor transistor has a first terminal coupled to the second terminal of the current source, a second terminal coupled to the first terminal of the third N-type metal-oxide-semiconductor transistor and the second terminal of the second N-type metal-oxide-semiconductor transistor, and a third terminal coupled to the ground. The fourth N-type metal-oxide-semiconductor transistor has a first terminal coupled to the second terminal of the current source, a second terminal, and a third terminal. The fifth N-type metal-oxide-semiconductor transistor has a first terminal coupled to the third terminal of the second P-type metal-oxide-semiconductor transistor, a second terminal coupled to the first terminal of the fifth N-type metal-oxide-semiconductor transistor and the second terminal of the fourth N-type metal-oxide-semiconductor transistor, and a third terminal coupled to the ground. The first resistor has a first terminal for receiving the first voltage, and a second terminal for coupling to the third P-type metal-oxide-semiconductor transistor. The second resistor has a first terminal coupled to the third terminal of the fourth N-type metal-oxide-semiconductor transistor, and a second terminal for coupling to the ground.

Another embodiment provides a high efficiency driving circuit. The high efficiency driving circuit includes a third P-type metal-oxide-semiconductor transistor, a first P-type metal-oxide-semiconductor transistor, a second P-type metal-oxide-semiconductor transistor, a first N-type metal-oxide-semiconductor transistor, a second N-type metal-oxide-semiconductor transistor, a current source, a third N-type metal-oxide-semiconductor transistor, a fourth N-type metal-oxide-semiconductor transistor, a fifth N-type metal-oxide-semiconductor transistor, a first resistor, and a second resistor. The third P-type metal-oxide-semiconductor transistor has a first terminal for receiving a first voltage, a second terminal, and a third terminal for coupling to a load. The first P-type metal-oxide-semiconductor transistor has a first terminal for receiving the first voltage, a second terminal for receiving a first control signal, and a third terminal coupled to the second terminal of the third P-type metal-oxide-semiconductor transistor. The second P-type metal-oxide-semiconductor transistor has a first terminal for receiving the first voltage, a second terminal coupled to the second terminal of the third P-type metal-oxide-semiconductor transistor, and a third terminal. The first N-type metal-oxide-semiconductor transistor has a first terminal coupled to the third terminal of the first P-type metal-oxide-semiconductor transistor, a second terminal for receiving a second control signal, and a third terminal. The second N-type metal-oxide-semiconductor transistor has a first terminal coupled to the third terminal of the first N-type metal-oxide-semiconductor transistor, a second terminal, and a third terminal coupled to ground. The current source has a first terminal for receiving a second voltage, and a second terminal, where the current source is used for providing first current. The third N-type metal-oxide-semiconductor transistor has a first terminal coupled to the second terminal of the current source, a second terminal coupled to the first terminal of the third N-type metal-oxide-semiconductor transistor and the second terminal of the second N-type metal-oxide-semiconductor transistor, and a third terminal coupled to the ground. The fourth N-type metal-oxide-semiconductor transistor has a first terminal coupled to the second terminal of the current source, a second terminal, and a third terminal. The fifth N-type metal-oxide-semiconductor transistor has a first terminal coupled to the third terminal of the second P-type metal-oxide-semiconductor transistor, a second terminal coupled to the first terminal of the fifth N-type metal-oxide-semiconductor transistor and the second terminal of the fourth N-type metal-oxide-semiconductor transistor, and a third terminal coupled to the ground. The first resistor has a first terminal for receiving the first voltage, and a second terminal coupled to the second terminal of the third P-type metal-oxide-semiconductor transistor. The second resistor has a first terminal coupled to the third terminal of the fourth N-type metal-oxide-semiconductor transistor, and a second terminal for coupling to the ground.

The present invention provides a high efficiency driving circuit. The high efficiency driving circuit utilizes a first P-type metal-oxide-semiconductor transistor and a first N-type metal-oxide-semiconductor transistor of the high efficiency driving circuit to be turned on according to a first control signal and a second control signal respectively for a voltage of a third terminal of the first P-type metal-oxide-semiconductor transistor (that is, a voltage of a second terminal of a third P-type metal-oxide-semiconductor transistor) to be between the first voltage and the third voltage. Thus, the voltage of the third terminal of the first P-type metal-oxide-semiconductor transistor does not damage the third P-type metal-oxide-semiconductor transistor (because the second terminal of the third P-type metal-oxide-semiconductor transistor is not a gate terminal of a high voltage metal-oxide-semiconductor process). In addition, the voltage of the third terminal of the first P-type metal-oxide-semiconductor transistor is increased/decreased rapidly, and an absolute value of current is only increased at the beginning of turning-on of the first P-type metal-oxide-semiconductor transistor and the beginning of turning-on of the first N-type metal-oxide-semiconductor transistor (that is, an average value of the absolute value of the current is very small). Therefore, compared to the prior art, the high efficiency driving circuit can not only turn on and turn off the third P-type metal-oxide-semiconductor transistor rapidly, but also have higher efficiency.

DETAILED DESCRIPTION

Please refer toFIG. 2.FIG. 2is a diagram illustrating a high efficiency driving circuit200according to an embodiment. The high efficiency driving circuit200includes a first P-type metal-oxide-semiconductor transistor202, a second P-type metal-oxide-semiconductor transistor204, a first N-type metal-oxide-semiconductor transistor206, a second N-type metal-oxide-semiconductor transistor208, a current source210, a third N-type metal-oxide-semiconductor transistor212, a fourth N-type metal-oxide-semiconductor transistor214, a fifth N-type metal-oxide-semiconductor transistor216, a first resistor218, and a second resistor220. The first P-type metal-oxide-semiconductor transistor202has a first terminal for receiving a first voltage HV, a second terminal for receiving a first control signal FCS, and a third terminal for coupling to a third P-type metal-oxide-semiconductor transistor222, where the third P-type metal-oxide-semiconductor transistor222is a P-type metal-oxide-semiconductor transistor of a partial high voltage complementary metal-oxide-semiconductor process. That is to say, a third terminal of the third P-type metal-oxide-semiconductor transistor222is a drain terminal of a high voltage metal-oxide-semiconductor process, and a second terminal of the third P-type metal-oxide-semiconductor transistor222is not a gate terminal of the high voltage metal-oxide-semiconductor process. In addition, the first control signal FCS is provided by a level shifter224. The second P-type metal-oxide-semiconductor transistor204has a first terminal for receiving the first voltage HV, a second terminal for coupling to the third P-type metal-oxide-semiconductor transistor222, and a third terminal. The first N-type metal-oxide-semiconductor transistor206has a first terminal coupled to the third terminal of the first P-type metal-oxide-semiconductor transistor202, a second terminal for receiving a second control signal SCS, and a third terminal. The second N-type metal-oxide-semiconductor transistor208has a first terminal coupled to the third terminal of the first N-type metal-oxide-semiconductor transistor206, a second terminal, and a third terminal coupled to ground GND. The current source210has a first terminal for receiving a second voltage V2, and a second terminal, where the current source210is used for providing a first current I1. The third N-type metal-oxide-semiconductor transistor212has a first terminal coupled to the second terminal of the current source210, a second terminal coupled to the first terminal of the third N-type metal-oxide-semiconductor transistor212and the second terminal of the second N-type metal-oxide-semiconductor transistor208, and a third terminal coupled to the ground GND. A width over length ratio of the second N-type metal-oxide-semiconductor transistor208is N times a width over length ratio of the third N-type metal-oxide-semiconductor transistor212, and N>1. The fourth N-type metal-oxide-semiconductor transistor214has a first terminal coupled to the second terminal of the current source210, a second terminal, and a third terminal. The fifth N-type metal-oxide-semiconductor transistor216has a first terminal coupled to the third terminal of the second P-type metal-oxide-semiconductor transistor204, a second terminal coupled to the first terminal of the fifth N-type metal-oxide-semiconductor transistor216and the second terminal of the fourth N-type metal-oxide-semiconductor transistor214, and a third terminal coupled to the ground GND. The first resistor218has a first terminal for receiving the first voltage HV, and a second terminal for coupling to the third P-type metal-oxide-semiconductor transistor222, where the first resistor218is used for stabilizing a voltage of the third terminal of the first P-type metal-oxide-semiconductor transistor202. The second resistor220has a first terminal coupled to the third terminal of the fourth N-type metal-oxide-semiconductor transistor214, and a second terminal for coupling to the ground GND, where the second resistor220is used for reducing closed loop gain of the high efficiency driving circuit200to stabilize the high efficiency driving circuit200.

Please refer toFIG. 3.FIG. 3is a timing diagram illustrating the first control signal FCS, the second control signal SCS and current IA flowing through a node A. As shown inFIG. 3, a high voltage level of the first control signal FCS is the first voltage HV (such as 20V), and a low voltage level of the first control signal FCS is a third voltage V3(such as 17V). But, the present invention is not limited to the first voltage HV being 20V and the third voltage V3being 17V. As shown inFIG. 3, a high voltage level of the second control signal SCS is a fourth voltage V4(such as 3V), and a low voltage level of the second control signal SCS is the ground GND (0V). But, the present invention is not limited to the fourth voltage being 3V. In addition, because a frequency of the first control signal FCS is the same as a frequency of the second control signal SCS, the first P-type metal-oxide-semiconductor transistor202and the first N-type metal-oxide-semiconductor transistor206are not turned on and turned off simultaneously.

As shown inFIG. 2andFIG. 3, when the first P-type metal-oxide-semiconductor transistor202is turned on instantly according to the first control signal FCS (an interval T1), the current IA is increased rapidly, resulting in the voltage of the third terminal (node A) of the first P-type metal-oxide-semiconductor transistor202being also increased rapidly. When the voltage of the third terminal (node A) of the first P-type metal-oxide-semiconductor transistor202is increased to the first voltage HV and maintained at the first voltage HV, the current IA becomes very small. In addition, when the first N-type metal-oxide-semiconductor transistor206is turned on instantly according to the second control signal SCS (an interval T2), because the width over length ratio of the second N-type metal-oxide-semiconductor transistor208is N times the width over length ratio of the third N-type metal-oxide-semiconductor transistor212, and the second P-type metal-oxide-semiconductor transistor204is turned off (because a voltage of node A is at the first voltage HV), the first current I1totally flows through the third N-type metal-oxide-semiconductor transistor212, resulting in the current IA (the current IA is N times the first current I1) being decreased rapidly. Thus, the voltage of the third terminal (node A) of the first P-type metal-oxide-semiconductor transistor202is also decreased to the third voltage V3. In addition, during the voltage of the third terminal (node A) of the first P-type metal-oxide-semiconductor transistor202being decreased to the third voltage V3, the second P-type metal-oxide-semiconductor transistor204is turned on rapidly, so that the current IA is increased rapidly. Therefore, when the voltage of the third terminal (node A) of the first P-type metal-oxide-semiconductor transistor202(node A) is decreased to the third voltage V3and maintained at the third voltage V3, the current IA also becomes very small.

Please refer toFIG. 4.FIG. 4is a diagram illustrating a high efficiency driving circuit400according to another embodiment. As shown inFIG. 4, a difference between the high efficiency driving circuit400and the high efficiency driving circuit200is that the high efficiency driving circuit400further includes the third P-type metal-oxide-semiconductor transistor222. The third P-type metal-oxide-semiconductor transistor222has a first terminal for receiving the first voltage HV, a second terminal coupled to the third terminal of the first P-type metal-oxide-semiconductor transistor202, and a third terminal for coupling a load226. The third terminal of the third P-type metal-oxide-semiconductor transistor222is a drain terminal of the high voltage metal-oxide-semiconductor process, and the second terminal of the third P-type metal-oxide-semiconductor transistor222is not a gate terminal of the high voltage metal-oxide-semiconductor process. Further, subsequent operational principles of the high efficiency driving circuit400are the same as those of the high efficiency driving circuit100, so further description thereof is omitted for simplicity.

To sum up, the high efficiency driving circuit utilizes the first P-type metal-oxide-semiconductor transistor and the first N-type metal-oxide-semiconductor transistor of the high efficiency driving circuit to be turned on according to the first control signal and the second control signal respectively for the voltage of the third terminal of the first P-type metal-oxide-semiconductor transistor (that is, a voltage of the second terminal of the third P-type metal-oxide-semiconductor transistor) to be between the first voltage and the third voltage. Thus, the voltage of the third terminal of the first P-type metal-oxide-semiconductor transistor does not damage the third P-type metal-oxide-semiconductor transistor (because the second terminal of the third P-type metal-oxide-semiconductor transistor is not the gate terminal of the high voltage metal-oxide-semiconductor process). In addition, the voltage of the third terminal of the first P-type metal-oxide-semiconductor transistor is increased/decreased rapidly, and an absolute value of the current is only increased at the beginning of turning-on of the first P-type metal-oxide-semiconductor transistor and the beginning of turning-on of the first N-type metal-oxide-semiconductor transistor (that is, an average value of the absolute value of the current is very small). Therefore, compared to the prior art, the high efficiency driving circuit can not only turn on and turn off the third P-type metal-oxide-semiconductor transistor rapidly, but also have higher efficiency.