SEMICONDUCTOR PACKAGE

Provided is a semiconductor package including a first redistribution layer, a first semiconductor chip disposed on the first redistribution layer, a circuit board disposed between the first redistribution layer and the first semiconductor chip, bonding wires connecting the first semiconductor chip and the circuit board to each other, a second redistribution layer disposed on the first semiconductor chip, a second semiconductor chip disposed on the second redistribution layer, and conductive posts connecting the first redistribution layer and the second redistribution layer to each other.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2023-0108545, filed on Aug. 18, 2023, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

BACKGROUND

1. Technical Field

The inventive concept relates to a semiconductor package, and more particularly, to a semiconductor package including an upper chip and a lower chip having respective connections to a first redistribution layer.

2. Discussion of Related Art

In a semiconductor package, a redistribution layer may electrically connect a semiconductor chip to a device or a printed circuit board. The semiconductor chip may be packaged by using the redistribution layer. The packaging method can be used to manufacture the semiconductor package having a small planar area, a thin thickness, a fast speed, and a high bandwidth.

SUMMARY

The inventive concept provides a semiconductor package including an upper chip and a lower chip having respective connections to a first redistribution layer, wherein the semiconductor packages has improved performance and reliability.

According to an aspect of the inventive concept, there is provided a semiconductor package including a first redistribution layer, a first semiconductor chip disposed on the first redistribution layer, a circuit board disposed between the first redistribution layer and the first semiconductor chip, a plurality of bonding wires connecting the first semiconductor chip with the circuit board, a second redistribution layer disposed on the first semiconductor chip, a second semiconductor chip disposed on the second redistribution layer, and a plurality of conductive posts connecting the first redistribution layer with the second redistribution layer.

According to another aspect of the inventive concept, there is provided a semiconductor package including a lower structure, an upper structure stacked on the lower structure, and a plurality of external connection terminals disposed under the lower structure, wherein the lower structure comprises a first redistribution layer, a first semiconductor chip disposed on the first redistribution layer, a plurality of bonding wires connecting the first semiconductor chip with the first redistribution layer, and a plurality of conductive posts connecting the first redistribution layer with the upper structure, wherein the upper structure comprises a second redistribution layer disposed on the lower structure, a second semiconductor chip disposed on the second redistribution layer, and a plurality of bumps disposed between the second semiconductor chip and the second redistribution layer.

According to another aspect of the inventive concept, there is provided a semiconductor package including a first redistribution layer, a first semiconductor chip and a second semiconductor chip disposed on the first redistribution layer to be spaced apart from each other in a first direction, a first circuit board disposed between the first redistribution layer and the first semiconductor chip, a second circuit board disposed between the first redistribution layer and the second semiconductor chip, first bonding wires connecting the first semiconductor chip with the first circuit board, second bonding wires connecting the second semiconductor chip with the second circuit board, a plurality of first bumps disposed on the first redistribution layer, wherein the first circuit board is disposed on a first set of the plurality of first bumps and the second circuit board is disposed on a second set of the plurality of first bumps, a second redistribution layer disposed on the first semiconductor chip, a third semiconductor chip and a fourth semiconductor chip disposed on the second redistribution layer to be spaced apart from each other in the first direction, a plurality of second bumps disposed on the second redistribution layer, wherein the third semiconductor chip is disposed on a first set of the plurality of second bumps and the fourth semiconductor chip is disposed on a second set of the plurality of second bumps, a plurality of conductive posts connecting the first redistribution layer with the second redistribution layer, and a plurality of external connection terminals disposed under the first redistribution layer, wherein the first semiconductor chip is connected to the first redistribution layer through the first bonding wires and the first circuit board, and the third semiconductor chip is attached to the second redistribution layer in a flip-chip structure.

DETAILED DESCRIPTION

Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. However, the inventive concept is not intended to be limited to examples described below and may be embodied in various other forms. Embodiments are provided to sufficiently convey the scope of this inventive concept to those skilled in the art.

FIG.1is a cross-sectional view illustrating a first semiconductor package10according to an embodiment.

Referring toFIG.1, the first semiconductor package10may include a lower structure10_1and an upper structure10_2stacked vertically. Specifically, the upper structure10_2may be stacked on the lower structure10_1in the second direction D2. The lower structure10_1may include a first semiconductor chip110. The upper structure10_2may include a second semiconductor chip120.

In some embodiments, the lower structure10_1may include the first semiconductor chip110, a first redistribution layer111, a carrier such as a circuit board112or a lead frame, a plurality of bonding wires113, a plurality of first bumps115, and a plurality of conductive posts116.

In some embodiments, the first semiconductor chip110may be disposed on the first redistribution layer111. Specifically, the first semiconductor chip110may be disposed on the circuit board112and mounted on the first redistribution layer111.

In some embodiments, the first redistribution layer111may include a plurality of redistribution insulating layers111a,111b,and111c,a plurality of redistribution pads111p,and a plurality of redistribution vias111v.The plurality of redistribution pads111pmay be disposed in the plurality of redistribution insulating layers111a,111b,and111c.The plurality of redistribution vias111vmay contact the plurality of redistribution pads111pin the plurality of redistribution insulating layers111a,111b,and111c.The first redistribution layer111may include a redistribution layer.

In some embodiments, the first redistribution layer111may provide an electrical path connecting the first semiconductor chip110with a plurality of external connection terminals130. The first redistribution layer111may provide an electrical path connecting the circuit board112with the external connection terminals130.

In some embodiments, the circuit board112may be disposed between the first semiconductor chip110and the first redistribution layer111. The circuit board112may provide an electrical path connecting the first semiconductor chip110with the first redistribution layer111. The circuit board112may be a printed circuit board (PCB). The circuit board112may be a type of carrier. In an embodiment, the circuit board112may be replaced by another type of carrier, such as a lead frame.

In some embodiments, an adhesive layer119may be disposed between the first semiconductor chip110and the circuit board112. For example, the first semiconductor chip110may be attached to the circuit board112by the adhesive layer119. In some embodiments, the adhesive layer119may include a die attach film (DAF).

In some embodiments, the first semiconductor chip110may be connected to the circuit board112by bonding wires113. Specifically, the bonding wires113may provide an electrical path connecting the first semiconductor chip110with the circuit board112. For example, an electrical signal generated by the first semiconductor chip110may be transmitted to the circuit board112through the bonding wires113. The bonding wires113may be connected to an upper surface of the first semiconductor chip110and connected to an upper surface of the circuit board112.

In some embodiments, an intermediate molding layer114may be disposed on the circuit board112, and may encapsulate the first semiconductor chip110, the adhesive layer119, and the bonding wires113. Specifically, the intermediate molding layer114may surround the first semiconductor chip110, the adhesive layer119, and the bonding wires113in the first direction D1. For example, the intermediate molding layer114may include an epoxy resin, a silicone resin, or a combination thereof. For example, the intermediate molding layer114may include an epoxy mold compound (EMC).

In some embodiments, a plurality of first bumps115may be disposed between the circuit board112and the first redistribution layer111. In some embodiments, the plurality of first bumps115may be attached to a lower surface of the circuit board112. The first bumps115may provide an electrical path connecting the circuit board112with the first redistribution layer111. The first bumps115may provide an electrical path connecting the first semiconductor chip110with the first redistribution layer111. The plurality of first bumps115may include a conductive material. For example, the plurality of first bumps115may include tin (Sn), lead (Pb), silver (Ag), copper (Cu), or a combination thereof.

In some embodiments, the electrical signal generated by the first semiconductor chip110may be transmitted to the first redistribution layer111through the bonding wires113. Specifically, the electrical signal generated by the first semiconductor chip110may be transmitted to the circuit board112through the bonding wires113. Thereafter, the electrical signal transmitted to the circuit board112may be transmitted to the first redistribution layer111through the plurality of first bumps115. The electrical signal generated by the first semiconductor chip110and transmitted to the first redistribution layer111may be transmitted to the external connection terminals130through the plurality of redistribution pads111pand the plurality of redistribution vias111vdisposed in the first redistribution layer111.

In some embodiments, a plurality of conductive posts116may be disposed between the lower structure10_1and the upper structure10_2. Specifically, the conductive posts116may connect the lower structure10_1with the upper structure10_2. Specifically, the conductive posts116may be disposed between the first redistribution layer111and the second redistribution layer121. The conductive posts116may connect the first redistribution layer111with the second redistribution layer121. The conductive posts116may connect an upper surface of the first redistribution layer111with a lower surface of the second redistribution layer121. Specifically, the conductive posts116may provide an electrical path connecting the first redistribution layer111with the second redistribution layer121.

The conductive posts116may each include a conductive material. For example, the conductive posts116may include copper (Cu), gold (Au), silver (Ag), nickel (Ni), tungsten (W), aluminum (Al), or a combination thereof. In some embodiments, the conductive posts116may each further include a barrier material. The barrier material may prevent the conductive material from diffusing out of the conductive posts116. The barrier material may include, for example, titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or a combination thereof.

In some embodiments, the lower molding layer117may be disposed on the first redistribution layer111, and may encapsulate the first semiconductor chip110and the conductive posts116. Specifically, the lower molding layer117may encapsulate the intermediate molding layer114, the circuit board112, the plurality of first bumps115, the conductive posts116, and the first redistribution layer111. In some embodiments, the lower molding layer117may form the lower structure10_1by encapsulating the first semiconductor chip110, the adhesive layer119, the circuit board112, the bonding wires113, the plurality of first bumps115, and the conductive posts116, while being disposed on the first redistribution layer111. In some embodiments, the lower molding layer117may surround the intermediate molding layer114, the plurality of first bumps115, and the conductive posts116in a first direction D1.

In some embodiments, the lower molding layer117may include a portion for encapsulating the plurality of first bumps115disposed between the circuit board112and the first redistribution layer111. Specifically, the lower molding layer117may include a portion disposed between the plurality of first bumps115disposed between the circuit board112and the first redistribution layer111, thereby encapsulating the plurality of first bumps115.

The lower molding layer117may include, for example, an epoxy resin, a silicone resin, or a combination thereof. For example, the lower molding layer117may include an epoxy mold compound. In some embodiments, the lower molding layer117may include the same material as the intermediate molding layer114. In some embodiments, the lower molding layer117may include a material different from that of the intermediate molding layer114.

In some embodiments, the upper structure10_2may be disposed on the lower structure10_1. In some embodiments, the upper structure10_2may include a second semiconductor chip120, a second redistribution layer121, and a plurality of second bumps122.

In some embodiments, the second redistribution layer121may be disposed on the first redistribution layer111. Specifically, the second redistribution layer121may be disposed on the lower molding layer117that encapsulates the first semiconductor chip110, the circuit board112, and the like.

In some embodiments, the second redistribution layer121may include a plurality of redistribution insulating layers121a,121b,and121c,a plurality of redistribution pads121p,and a plurality of redistribution vias121v.The plurality of redistribution pads121pmay be disposed in the plurality of redistribution insulating layers121a,121b,and121c.The plurality of redistribution vias121vmay contact the plurality of redistribution pads121pin the plurality of redistribution insulating layers121a,121b,and121c.The second redistribution layer121may include a redistribution layer.

In some embodiments, the second semiconductor chip120may be disposed on the second redistribution layer121. The second semiconductor chip120may be mounted on the second redistribution layer121without a circuit board disposed therebetween.

In some embodiments, the second semiconductor chip120may be mounted on the second redistribution layer121in a flip-chip structure. For example, the second semiconductor chip120may have a first surface and a second surface. The first surface may be an active surface and the second surface may be an inactive surface opposite to the first surface. The active surface of the second semiconductor chip120may face the second redistribution layer121.

In some embodiments, the second redistribution layer121may provide an electrical path connecting the second semiconductor chip120with the external connection terminals130. The second redistribution layer121may provide an electrical path connecting the second semiconductor chip120with the first redistribution layer111.

In some embodiments, a plurality of second bumps122may be disposed between the second semiconductor chip120and the second redistribution layer121. In some embodiments, the plurality of second bumps122may be attached to the second semiconductor chip120. The plurality of second bumps122may provide an electrical path connecting the second semiconductor chip120with the second redistribution layer121. The plurality of second bumps122may include a conductive material. For example, the plurality of second bumps122may include tin (Sn), lead (Pb), silver (Ag), copper (Cu), or a combination thereof.

In some embodiments, the plurality of first bumps115and the plurality of second bumps122may be of different types. For example, as described above, the plurality of first bumps115may be attached to a lower surface of the circuit board112, and the plurality of second bumps122may be attached to a lower surface of the second semiconductor chip120. As described above, the lower surface of the second semiconductor chip120may be an active surface.

In some embodiments, sizes of the plurality of first bumps115may be different from sizes of the plurality of second bumps122. Specifically, the width W1of each of the plurality of first bumps115in the first direction D1may be greater than the width W2of each of the plurality of second bumps122in the first direction D1. Specifically, the height of each of the plurality of first bumps115in the second direction D2may be greater than the height of each of the plurality of second bumps122in the second direction D2. However, embodiments are not limited thereto, and other implementations are contemplated. For example, the width W1of each of the plurality of first bumps115in the first direction D1may be greater than the width W2of each of the plurality of second bumps122in the first direction D1, and the height of each of the plurality of first bumps115in the second direction D2and the height of each of the plurality of second bumps122in the second direction D2may be the same.

In some embodiments, a pitch between adjacent first bumps of the plurality of first bumps115and a pitch between adjacent second bumps of the plurality of second bumps122may be different from each other. Specifically, the pitch PI between the adjacent first bumps of the plurality of first bumps115in the first direction D1may be greater than the pitch P2between the adjacent second bumps of the plurality of second bumps122in the first direction D1. However, embodiments are not limited thereto, and other implementations are contemplated.

In some embodiments, the upper molding layer123may be disposed on the second redistribution layer121and encapsulate the second semiconductor chip120and the plurality of second bumps122. Specifically, the upper molding layer123may surround the second semiconductor chip120and the plurality of second bumps122in the first direction D1. In some embodiments, the upper molding layer123may include a portion for encapsulating the plurality of second bumps122between the second semiconductor chip120and the second redistribution layer121. Specifically, the upper molding layer123may include a portion disposed between the plurality of second bumps122between the second semiconductor chip120and the second redistribution layer121to thereby encapsulate the plurality of second bumps122.

The upper molding layer123may include, for example, an epoxy resin, a silicone resin, or a combination thereof. For example, the upper molding layer123may include an epoxy mold compound. In some embodiments, the upper molding layer123may include the same material as the intermediate molding layer114and/or the lower molding layer117. In some embodiments, the upper molding layer123may include a different material from the intermediate molding layer114and/or the lower molding layer117.

In some embodiments, the electrical signal of the second semiconductor chip120may be transmitted to the second redistribution layer121through the plurality of second bumps122. Thereafter, the electrical signal transmitted to the second redistribution layer121may be transmitted to the conductive posts116through the plurality of redistribution pads121pand the plurality of redistribution vias121vformed in the second redistribution layer121, and the electrical signal may be transmitted to the first redistribution layer111through the conductive posts116. The electrical signal of the second semiconductor chip120transmitted to the first redistribution layer111may be transmitted to the external connection terminals130.

In some embodiments, the external connection terminals130may be located on a bottom surface of the first redistribution layer111of the lower structure10_1. The external connection terminals130may include, for example, a conductive material such as tin (Sn), lead (Pb), silver (Ag), copper (Cu), or a combination thereof. The external connection terminals130may be formed using, for example, solder balls. The external connection terminals130may connect the first semiconductor package10to, for example, a circuit board, another semiconductor package, an interposer, or a combination thereof.

In some embodiments, the first semiconductor chip110and/or the second semiconductor chip120may include a graphics double data rate (GDDR) chip. In some embodiments, the first semiconductor chip110and the second semiconductor chip120may be the same type of semiconductor chips. In some embodiments, the first semiconductor chip110and the second semiconductor chip120may be different types of semiconductor chips.

According to embodiments of the inventive concept, since the first semiconductor chip110of the lower structure10_1may be connected to the first redistribution layer111through the bonding wires113and the circuit board112, defects that may occur due to bumps attached directly to the first semiconductor chip110may be avoided or eliminated.

According to embodiments of the inventive concept, the second semiconductor chip120of the upper structure10_2may be attached to the second redistribution layer121in a flip-chip structure, and the first semiconductor chip110of the lower structure10_1may be connected to the first redistribution layer111through the bonding wires113. Accordingly, in the first semiconductor package10according to embodiments of the inventive concept, a difference in length between a path of the second semiconductor chip120of the upper structure10_2to the external connection terminals130and a path of the first semiconductor chip110of the lower structure10_1to the external connection terminals130may be reduced or eliminated, thereby improving signal characteristics. For example, the path of the second semiconductor chip120of the upper structure10_2to the external connection terminals130and the path of the first semiconductor chip110of the lower structure10_1to the external connection terminals130may be equal. For example, a length of the bonding wires113, a height of plurality of first bumps115, a height of the plurality of second bumps122, etc., may be configured to reduce a difference in the lengths of electric paths of the first semiconductor package10.

That is, according to embodiments according to the inventive concept, the first semiconductor package10with improved performance and reliability may be provided.

FIG.2,FIG.3, andFIG.4are cross-sectional views illustrating a second semiconductor package11, a third semiconductor package12, and a fourth semiconductor package13, respectively, according to embodiments. In comparison with the first semiconductor package10described with reference toFIG.1, differences will be mainly described.

Referring toFIG.2, the second semiconductor package11may include a lower structure11_1and an upper structure11_2stacked vertically. Specifically, the upper structure11_2may be stacked on the lower structure11_1in the second direction D2. The lower structure11_1may include a first semiconductor chip110. The upper structure11_2may include a second semiconductor chip120.

In some embodiments, the second semiconductor package11may further include a first underfill layer118disposed between the circuit board112and the first redistribution layer111. Specifically, the second semiconductor package11may further include the first underfill layer118disposed between the circuit board112and the first redistribution layer111of the lower structure11_1.

In some embodiments, the first underfill layer118may encapsulate a plurality of first bumps115disposed between the circuit board112and the first redistribution layer111. Specifically, the first underfill layer118may include a portion disposed between the plurality of first bumps115between the circuit board112and the first redistribution layer111that encapsulates the plurality of first bumps115.

The lower molding layer117of the second semiconductor package11ofFIG.2may not be disposed between the circuit board112and the first redistribution layer111, and the first underfill layer118, separate from the lower molding layer117, may encapsulate a plurality of first bumps115. Even when the lower molding layer117may contact a portion of a lower surface of the circuit board112, for example, around a periphery of an area defined by the plurality of first bumps115, the first underfill layer118may encapsulate the plurality of first bumps115, and the lower molding layer117may be disposed on a side surface of the first underfill layer118.

The first underfill layer118may include, for example, a polymer, an epoxy resin, or a combination thereof. For example, the first underfill layer118may include a material different from that of the lower molding layer117.

Referring toFIG.3, the third semiconductor package12may include a lower structure12_1and an upper structure12_2stacked vertically. Specifically, the upper structure12_2may be stacked on the lower structure12_1in the second direction D2. The lower structure12_1may include a first semiconductor chip110. The upper structure12_2may include a second semiconductor chip120.

In some embodiments, the third semiconductor package12may further include a second underfill layer124. The second underfill layer124may be disposed between the second semiconductor chip120and the second redistribution layer121. Specifically, the third semiconductor package12may further include a second underfill layer124disposed between the second semiconductor chip120and the second redistribution layer121of the upper structure12_2.

In some embodiments, the second underfill layer124may encapsulate a plurality of second bumps122disposed between the second semiconductor chip120and the second redistribution layer121. Specifically, the second underfill layer124may include a portion disposed between the plurality of second bumps122between the second semiconductor chip120and the second redistribution layer121to encapsulate the plurality of second bumps122.

The upper molding layer123of the third semiconductor package12ofFIG.3may not be disposed between the second semiconductor chip120and the second redistribution layer121, and the second underfill layer124may be disposed to encapsulate the plurality of second bumps122. Even when the upper molding layer123may contact a portion of a lower surface of the second semiconductor chip120, for example, around a periphery of an area defined by the plurality of second bumps122, the second underfill layer124may encapsulate the plurality of second bumps122, and the upper molding layer123may be disposed on a side surface of the second underfill layer124.

The second underfill layer124may include, for example, a polymer, an epoxy resin, or a combination thereof. For example, the second underfill layer124may include a material different from that of the upper molding layer123.

Referring toFIG.4, the fourth semiconductor package13may include a lower structure13_1and an upper structure13_2stacked vertically. Specifically, the upper structure13_2may be stacked on the lower structure13_1in the second direction D2. The lower structure13_1may include a first semiconductor chip110. The upper structure13_2may include a second semiconductor chip120.

In some embodiments, the fourth semiconductor package13may further include the first underfill layer118disposed between the circuit board112and the first redistribution layer111, and the second underfill layer124disposed between the second semiconductor chip120and the second redistribution layer121. Specifically, the fourth semiconductor package13may further include the first underfill layer118disposed between the circuit board112and the first redistribution layer111of the lower structure13_1, and the second underfill layer124disposed between the second semiconductor chip120and the second redistribution layer121of the upper structure13_2. A description of the first underfill layer118may be further understood by referring toFIG.2and a description of the second underfill layer124may be further understood by referring toFIG.3.

FIG.5andFIG.6are cross-sectional views illustrating a fifth semiconductor package20and a sixth semiconductor package21, respectively, according to some embodiments.

Referring toFIG.5, the fifth semiconductor package20may include a lower structure20_1and an upper structure20_2stacked vertically. The upper structure20_2may be stacked on the lower structure20_1in the second direction D2. The lower structure20_1may include the first semiconductor chip210. The upper structure20_2may include the second semiconductor chip220. In comparison with the semiconductor package10described with reference toFIG.1, differences will be mainly described.

In some embodiments, the lower structure20_1may include a first semiconductor chip210, a first redistribution layer211, a plurality of bonding wires213, and a plurality of conductive posts216. The lower structure20_1of the fifth semiconductor package20may not have a circuit board or a plurality of bumps disposed between the first semiconductor chip210and the first redistribution layer211.

In some embodiments, the first semiconductor chip210may be disposed on the first redistribution layer211. The first semiconductor chip210of the fifth semiconductor package20may be directly mounted on the first redistribution layer211.

In some embodiments, the first redistribution layer211may be understood by referring to the description of the first redistribution layer111ofFIG.1. In some embodiments, the first redistribution layer211may provide an electrical path connecting the first semiconductor chip210with external connection terminals230.

In some embodiments, an adhesive layer219may be disposed between the first semiconductor chip210and the first redistribution layer211. For example, the first semiconductor chip210may be adhered to an upper surface of the first redistribution layer211by the adhesive layer219. In some embodiments, the adhesive layer219may include a DAF.

In some embodiments, the first semiconductor chip210may be connected to the first redistribution layer211by bonding wires213. Specifically, the bonding wires213may provide an electrical path connecting the first semiconductor chip210with the first redistribution layer211. For example, the electrical signal generated by the first semiconductor chip210may be transmitted to the first redistribution layer211through the bonding wires213. For example, the first semiconductor chip210may have a first surface and a second surface. The first surface may be an active surface and the second surface may be an inactive surface opposite to the first surface. For example, the inactive surface may face the first redistribution layer211and the bonding wires213may be connected on the active surface.

In some embodiments, the electrical signal of the first semiconductor chip210of the fifth semiconductor package20ofFIG.5may be directly transmitted to the first redistribution layer211through the bonding wires213. Subsequently, the electrical signal of the first semiconductor chip210transmitted to the first redistribution layer211may be transmitted to the external connection terminals230through a plurality of redistribution pads and a plurality of redistribution vias formed in the first redistribution layer211.

In some embodiments, conductive posts216may be disposed between the lower structure20_1and the upper structure20_2. Specifically, the conductive posts216may provide an electrical path connecting the first redistribution layer211with the second redistribution layer221. The conductive posts216may be understood by referring to the description of the conductive posts116ofFIG.1.

In some embodiments, the fifth semiconductor package20ofFIG.5may not include a molding layer, separate from the lower molding layer217, encapsulating the first semiconductor chip110and the bonding wires113.

In some embodiments, the lower molding layer217may be disposed on the first redistribution layer211and encapsulate the first semiconductor chip210and the conductive posts216. In some embodiments, the lower molding layer217disposed on the first redistribution layer211may form the lower structure20_1by encapsulating the first semiconductor chip210, the bonding wires213, and the conductive posts216. In some embodiments, the lower molding layer217may be disposed on the first redistribution layer211and surround the first semiconductor chip210and the bonding wires213in the first direction D1. For example, the lower molding layer217may include an epoxy resin, a silicone resin, or a combination thereof.

In some embodiments, the upper structure20_2may be disposed on the lower structure20_1. In some embodiments, the upper structure20_2may include a second semiconductor chip220, a second redistribution layer221, and a plurality of second bumps222.

In some embodiments, the second semiconductor chip220may be disposed on the second redistribution layer221. In some embodiments, the second semiconductor chip220may be mounted on the second redistribution layer221in a flip-chip structure. For example, the second semiconductor chip220may have a first surface and a second surface. The first surface may be an active surface and the second surface may be an inactive surface opposite to the first surface. The active surface of the second semiconductor chip220may face the second redistribution layer121.

In some embodiments, the second redistribution layer221may be disposed on the first redistribution layer211. Specifically, the second redistribution layer221may be disposed on the lower molding layer217disposed on the first redistribution layer211and that encapsulates the first semiconductor chip210, and the like. The second redistribution layer221may be further understood by referring to the description of the second redistribution layer121ofFIG.1.

In some embodiments, the second redistribution layer221may provide an electrical path connecting the second semiconductor chip220with the external connection terminals230. The second redistribution layer221may provide an electrical path connecting the second semiconductor chip220with the first redistribution layer211. In some embodiments, a plurality of second bumps222may be disposed between the second semiconductor chip220and the second redistribution layer221. The plurality of second bumps222may be further understood by referring to the description of the plurality of second bumps122ofFIG.1.

In some embodiments, the upper molding layer223may be disposed on the second redistribution layer221and encapsulate the second semiconductor chip220and the plurality of second bumps222. In some embodiments, the upper molding layer223may include a portion for encapsulating the plurality of second bumps222between the second semiconductor chip220and the second redistribution layer221. The upper molding layer223may be further understood by referring to the description of the upper molding layer123ofFIG.1. In some embodiments, the upper molding layer223may include the same material as the lower molding layer217. In some embodiments, the upper molding layer223may include a material different from that of the lower molding layer217.

In some embodiments, the electrical signal of the second semiconductor chip220may be transmitted to the second redistribution layer221through the plurality of second bumps222. Thereafter, the electrical signal transmitted to the second redistribution layer221may be transmitted to the conductive posts216through a plurality of redistribution pads and a plurality of redistribution vias formed in the second redistribution layer221, and the electrical signal may be transmitted to the first redistribution layer211through the conductive posts216. The electrical signal of the second semiconductor chip220transmitted to the first redistribution layer211may be transmitted to the external connection terminals230.

In some embodiments, the external connection terminals230may be located on a bottom surface of the first redistribution layer211of the lower structure20_1. The external connection terminals230may be further understood by referring to the description of the external connection terminals130ofFIG.1.

According to embodiments of the inventive concept, the second semiconductor chip220of the upper structure20_2may be attached to the second redistribution layer221in a flip-chip structure, and the first semiconductor chip210of the lower structure20_1may be connected to the first redistribution layer211through the bonding wires213. Accordingly, in the second semiconductor package20according to embodiments of the inventive concept, a difference in length between a path of the second semiconductor chip220of the upper structure20_2to the external connection terminals230and a path of the first semiconductor chip210of the lower structure20_1to the external connection terminals230may be reduced or eliminated, thereby improving signal characteristics. For example, the path of the second semiconductor chip220of the upper structure20_2to the external connection terminals230and the path of the first semiconductor chip210of the lower structure20_1to the external connection terminals230may be substantially equal. For example, a length of the bonding wires213, a height of the plurality of second bumps222, etc., may be configured to reduce a difference in the lengths of electric paths of the fifth semiconductor package20.

In some embodiments, the first semiconductor chip210and/or the second semiconductor chip220may include a GDDR (Graphics Double Data Rate) chip. In some embodiments, the first semiconductor chip210and the second semiconductor chip220may be the same type of semiconductor chip. In some embodiments, the first semiconductor chip210and the second semiconductor chip220may be different types of semiconductor chips.

Referring toFIG.6, the sixth semiconductor package21may include a lower structure21_1and an upper structure21_2stacked vertically. Specifically, the upper structure21_2may be stacked on the lower structure21_1in the second direction D2. The lower structure21_1may include the first semiconductor chip210. The upper structure21_2may include the second semiconductor chip220. Hereinafter, differences from the fifth semiconductor package20ofFIG.5will be mainly described.

In some embodiments, the sixth semiconductor package21may further include an underfill layer224. The underfill layer224may be disposed between the second semiconductor chip220and the second redistribution layer221. Specifically, the sixth semiconductor package21may further include the underfill layer224disposed between the second semiconductor chip220and the second redistribution layer221of the upper structure21_2.

In some embodiments, the underfill layer224may encapsulate a plurality of second bumps222disposed between the second semiconductor chip220and the second redistribution layer221. Specifically, the underfill layer224may include a portion disposed between the plurality of second bumps222disposed between the second semiconductor chip220and the second redistribution layer221to encapsulate the plurality of second bumps222.

The upper molding layer223of the sixth semiconductor package21ofFIG.6may not be disposed between the second semiconductor chip220and the second redistribution layer221, and a underfill layer224, separate from the upper molding layer223, may be disposed to encapsulate the plurality of second bumps222. Even when the upper molding layer223may contact a portion of a lower surface of the second semiconductor chip220, for example, around a periphery of an area defined by the plurality of second bumps222, the underfill layer224may encapsulate the plurality of second bumps222, and the upper molding layer223may be disposed on a side surface of the underfill layer224.

The under filter layer224may include, for example, a polymer, an epoxy resin, or a combination thereof. For example, the underfill layer224may include a material different from that of the upper molding layer223.

FIG.7is a cross-sectional view illustrating a seventh semiconductor package30according to an embodiment.

Referring toFIG.7, the seventh semiconductor package30may include a lower structure30_1and an upper structure30_2stacked vertically. Specifically, the upper structure30_2may be stacked on the lower structure30_1in the second direction D2. The lower structure30_1may include a first semiconductor chip310and a second semiconductor chip320spaced apart in the first direction D1. The upper structure30_2may include a third semiconductor chip340and a fourth semiconductor chip350spaced apart in the first direction D1.

In some embodiments, the lower structure30_1may include the first semiconductor chip310, the second semiconductor chip320, a first redistribution layer330, a first circuit board312, a second circuit board322, first bonding wires313, second bonding wires323, a plurality of first bumps331, and conductive posts332.

In some embodiments, the first semiconductor chip310and the second semiconductor chip320may be disposed on the first redistribution layer330. Specifically, the first semiconductor chip310may be disposed on the first circuit board312and mounted on the first redistribution layer330. The second semiconductor chip320may be disposed on the second circuit board322and mounted on the first redistribution layer330.

In some embodiments, the first redistribution layer330may provide an electrical path connecting the first semiconductor chip310with the external connection terminals370and an electrical path connecting and the second semiconductor chip320with the external connection terminals370. The first redistribution layer330may provide an electrical path connecting the first circuit board312with the external connection terminals370, and an electrical path connecting the second circuit board322with the external connection terminals370. The first redistribution layer330may be further understood by referring to the description of the first redistribution layer111ofFIG.1. The first redistribution layer330may include a redistribution layer.

In some embodiments, the first circuit board312may be disposed between the first semiconductor chip310and the first redistribution layer330. The first circuit board312may provide an electrical path connecting the first semiconductor chip310with the first redistribution layer330. The first circuit board312may be a printed circuit board (PCB).

In some embodiments, the second circuit board322may be disposed between the second semiconductor chip320and the first redistribution layer330. The second circuit board322may provide an electrical path connecting the second semiconductor chip320with the first redistribution layer330. The second circuit board322may be a printed circuit board (PCB).

In some embodiments, a first adhesive layer319may be disposed between the first semiconductor chip310and the circuit board312. For example, the first semiconductor chip310may be attached to the first circuit board312by the first adhesive layer319. In some embodiments, a second adhesive layer329may be disposed between the second semiconductor chip320and the second circuit board322. For example, the second semiconductor chip320may be attached to the second circuit board322by the second adhesive layer329. In some embodiments, the first adhesive layer319and the second adhesive layer329may include a die attach film (DAF).

In some embodiments, the first semiconductor chip310may be connected to the first circuit board312by the first bonding wires313. Specifically, the first bonding wires313may provide an electrical path connecting the first semiconductor chip310with the first circuit board312. For example, the electrical signal generated by the first semiconductor chip310may be transmitted to the first circuit board312through the first bonding wires313.

In some embodiments, the second semiconductor chip320may be connected to the second circuit board322by the second bonding wires323. Specifically, the second bonding wires323may provide an electrical path connecting the second semiconductor chip320with the second circuit board322. For example, the electrical signal generated by the second semiconductor chip320may be transmitted to the second circuit board322through the second bonding wires323.

In some embodiments, the first intermediate molding layer314may be disposed on the first circuit board312and encapsulate the first semiconductor chip310, the first adhesive layer319, and the first bonding wires313. For example, the first intermediate molding layer314may include an epoxy resin, a silicone resin, or a combination thereof. The first intermediate molding layer314may be further understood by referring to the description of the intermediate molding layer114ofFIG.1.

In some embodiments, the second intermediate molding layer324may be disposed on the second circuit board322and encapsulate the second semiconductor chip320, the second adhesive layer329, and the second bonding wires323. For example, the second intermediate molding layer324may include an epoxy resin, a silicone resin, or a combination thereof. The second intermediate molding layer324may be further understood by referring to the description of the intermediate molding layer114ofFIG.1.

In some embodiments, a first set of the plurality of first bumps331may be disposed between the first circuit board312and the first redistribution layer330, and a second set of the plurality of first bumps331may be disposed between the second circuit board322and the first redistribution layer330. The first and second sets of the plurality of first bumps331may include different bumps of the plurality of first bumps331. In some embodiments, the plurality of first bumps331may be attached to a lower surface of the first circuit board312and a lower surface of the second circuit board322. The plurality of first bumps331may provide an electrical path connecting the first circuit board312with the first redistribution layer330, and an electrical path connecting the second circuit board322with the first redistribution layer330. The plurality of first bumps331may provide an electrical path connecting the first semiconductor chip310with the first redistribution layer330, and an electrical path connecting the second semiconductor chip320with the first redistribution layer330. The plurality of first bumps331may be further understood by referring to the description of the plurality of first bumps115ofFIG.1.

In some embodiments, the electrical signal of the first semiconductor chip310may be transmitted to the first redistribution layer330through the bonding wires313. Specifically, the electrical signal of the first semiconductor chip310may be transmitted to the first circuit board312through the first bonding wires313. Thereafter, the electrical signal transmitted to the first circuit board312may be transmitted to the first redistribution layer330through the plurality of first bumps331. The electrical signal of the first semiconductor chip310transmitted to the first redistribution layer330may be transmitted to the external connection terminals370through a plurality of redistribution pads and a plurality of redistribution vias formed in the first redistribution layer330.

In some embodiments, the electrical signal of the second semiconductor chip320may be transmitted to the first redistribution layer330through the second bonding wires323. Specifically, the electrical signal of the second semiconductor chip320may be transmitted to the second circuit board322through the second bonding wires323. Thereafter, the electrical signal transmitted to the second circuit board322may be transmitted to the first redistribution layer330through the plurality of first bumps331. The electrical signal of the second semiconductor chip320transmitted to the first redistribution layer330may be transmitted to the external connection terminals370through the plurality of redistribution pads and the plurality of redistribution vias formed in the first redistribution layer330.

In some embodiments, the conductive posts332may be disposed between the lower structure30_1and the upper structure30_2. Specifically, the conductive posts332may electrically connect the first redistribution layer330with the second redistribution layer360. The conductive posts332may be further understood by referring to the description of the conductive posts116ofFIG.1.

In some embodiments, the lower molding layer333may be formed on the first redistribution layer330and encapsulate the first semiconductor chip310, the second semiconductor chip320, and the conductive posts332. Specifically, the lower molding layer333may be formed on the first redistribution layer330and encapsulate the first intermediate molding layer314encapsulating the first semiconductor chip310, the first adhesive layer319, the first circuit board312, and the first bonding wires313, and the second intermediate molding layer324encapsulating the second semiconductor chip320, the second adhesive layer329, the second circuit board322, and the second bonding wires323, together with the plurality of first bumps331, and the conductive posts332. In some embodiments, the lower molding layer333may form the lower structure30_1by being disposed on the first redistribution layer330and encapsulating the first semiconductor chip310, the first adhesive layer319, the first circuit board312, the first bonding wires313, the second semiconductor chip320, the second adhesive layer329, the second circuit board322, the second bonding wires323, the plurality of first bumps331, and the conductive posts332.

In some embodiments, the lower molding layer333may include a portion for encapsulating the plurality of first bumps331between the first circuit board312and the first redistribution layer330. Specifically, the lower molding layer333may include a portion disposed between each of the plurality of first bumps331between the first circuit board312and the first redistribution layer330, thereby encapsulating the plurality of first bumps331.

In some embodiments, likewise, the lower molding layer333may include a portion for encapsulating the plurality of first bumps331between the second circuit board322and the first redistribution layer330. Specifically, the lower molding layer333may include a portion disposed between the plurality of first bumps331between the second circuit board322and the first redistribution layer330, thereby encapsulating the plurality of first bumps331.

The lower molding layer333may include, for example, an epoxy resin, a silicone resin, or a combination thereof. The lower molding layer333may be further understood by referring to the description of the lower molding layer117ofFIG.1.

In some embodiments, the upper structure30_2may be disposed on the lower structure30_1. In some embodiments, the upper structure30_2may include a third semiconductor chip340and a fourth semiconductor chip350arranged in the first direction D1, a second redistribution layer360, and a plurality of second bumps361arranged in the first direction D1.

In some embodiments, the second redistribution layer360may be disposed on the first redistribution layer330. The second redistribution layer360may be further understood by referring to the description of the second redistribution layer121ofFIG.1.

In some embodiments, the third semiconductor chip340and the fourth semiconductor chip350may be disposed on the second redistribution layer360. In some embodiments, the third semiconductor chip340and the fourth semiconductor chip350may be mounted on the second redistribution layer360in a flip-chip structure.

In some embodiments, the second redistribution layer360may provide an electrical path connecting the third semiconductor chip340and the fourth semiconductor chip350with the external connection terminals370. The second redistribution layer360may provide an electrical path connecting the third semiconductor chip340and the fourth semiconductor chip350with the first redistribution layer330.

In some embodiments, a plurality of second bumps361may be disposed between the third semiconductor chip340and the second redistribution layer360, and between the fourth semiconductor chip350and the second redistribution layer360. In some embodiments, a first set of the plurality of second bumps361may be attached to a lower surface of the third semiconductor chip340and a second set of the plurality of second bumps361may be attached to a lower surface of the fourth semiconductor chip350. The first and second sets of the plurality of second bumps361may include different bumps of the plurality of second bumps361. The plurality of second bumps361may provide an electrical path connecting the third semiconductor chip340with the second redistribution layer360and an electrical path connecting the fourth semiconductor chip350with the second redistribution layer360. The plurality of second bumps361may be further understood by referring to the description of the plurality of second bumps122ofFIG.1.

In some embodiments, the plurality of first bumps331and the plurality of second bumps361may be of different types of bumps. For example, as described herein, the plurality of first bumps331may be attached under the first circuit board312and the second circuit board322, while the plurality of second bumps361may be attached under the third semiconductor chip340and the fourth semiconductor chip350.

In some embodiments, size of the plurality of first bumps331may be different from the size of the plurality of second bumps361. Specifically, the width of each of the plurality of first bumps331in the first direction D1may be greater than the width of each of the plurality of second bumps361in the first direction D1.

In some embodiments, a pitch between adjacent first bumps of the plurality of first bumps331and a pitch between adjacent second bumps of the plurality of second bumps361may be different from each other. Specifically, the pitch between adjacent first bumps of the plurality of first bumps331in the first direction D1may be greater than the pitch between adjacent second bumps of the plurality of second bumps361in the first direction D1.

In some embodiments, the upper molding layer362may be disposed on the second redistribution layer360and encapsulate the third semiconductor chip340, the fourth semiconductor chip350, and the plurality of second bumps361. In some embodiments, the upper molding layer362may include a portion encapsulating the plurality of second bumps361between the third semiconductor chip340and the second redistribution layer360and between the fourth semiconductor chip350and the second redistribution layer360. Specifically, the upper molding layer362may include a portion disposed between the plurality of second bumps361between the third semiconductor chip340and the second redistribution layer360, and between the fourth semiconductor chip350and the second redistribution layer360encapsulating the plurality of second bumps361. The upper molding layer362may be further understood by referring to the description of the upper molding layer123ofFIG.1.

In some embodiments, the electrical signal of the third semiconductor chip340may be transmitted to the second redistribution layer360through the plurality of second bumps361. Thereafter, the electrical signal transmitted to the second redistribution layer360may be transmitted to the conductive posts332, and may be transmitted to the first redistribution layer330. The electrical signal of the third semiconductor chip340transmitted to the first redistribution layer330may be transmitted to the external connection terminals370.

Likewise, the electrical signal of the fourth semiconductor chip350may be transmitted to the second redistribution layer360through the plurality of second bumps361. Thereafter, the electrical signal may be transmitted to the external connection terminals370through the conductive posts332and the first redistribution layer330.

In some embodiments, the external connection terminals370may be located on a bottom surface of the first redistribution layer330of the lower structure30_1. The external connection terminals370may be further understood by referring to the description of the external connection terminals130ofFIG.1.

In some embodiments, the first semiconductor chip310, the second semiconductor chip320, the third semiconductor chip340, and the fourth semiconductor chip350may include a GDDR chip. In some embodiments, the first semiconductor chip310and the second semiconductor chip320may be the same type of semiconductor chip. The third semiconductor chip340and the fourth semiconductor chip350may be the same type of semiconductor chip. In some embodiments, the first semiconductor chip310and the third semiconductor chip340may be the same type of semiconductor chip. The second semiconductor chip320and the fourth semiconductor chip350may be the same type of semiconductor chip. In some embodiments, the first semiconductor chip310and the third semiconductor chip340may be different types of semiconductor chips. The second semiconductor chip320and the fourth semiconductor chip350may be the different types of semiconductor chips.

FIGS.8A to8Hare cross-sectional views for explaining a method of manufacturing a semiconductor package10according to some embodiments. Specifically,FIGS.8A to8Hare cross-sectional views illustrating a method of manufacturing the semiconductor package10described with reference toFIG.1.

Referring toFIG.8A, the first semiconductor chip110may be provided. Specifically, the first semiconductor chip110may be attached to the circuit board112by using the adhesive layer119, and the bonding wires113connecting the first semiconductor chip110with the circuit board112may be formed. Subsequently, an intermediate molding layer114for encapsulating the first semiconductor chip110, the adhesive layer119, the circuit board112, and the bonding wires113may be formed. Thereafter, the plurality of first bumps115may be disposed on the bottom surface of the circuit board112.

Referring toFIG.8B, the first redistribution layer111may be disposed on a carrier substrate150. Subsequently, the conductive posts116may be disposed on the first redistribution layer111.

Referring toFIG.8C, the first semiconductor chip110provided with reference toFIG.8Amay be disposed on the carrier substrate150on which the first redistribution layer111and the conductive posts116are formed. Specifically, the first semiconductor chip110may be mounted such that the plurality of first bumps115are disposed on the first redistribution layer111. As a result, the first bumps115and the conductive posts116may be disposed on the first redistribution layer111, and the circuit board112and the first semiconductor chip110may be disposed on the first bumps115.

Referring toFIG.8D, a lower molding layer117may be disposed on the first redistribution layer111and may encapsulate the first semiconductor chip110and the conductive posts116. Specifically, the lower molding layer117may be disposed on the first redistribution layer111and encapsulate the intermediate molding layer114disposed on the circuit board112and encapsulating the first semiconductor chip110, the adhesive layer119, and the bonding wires113together with the plurality of first bumps115, and the conductive posts116. Here, the lower molding layer117may include a portion disposed between the circuit board112and the first redistribution layer111to encapsulate the plurality of first bumps115.

In some embodiments, a process of forming the lower molding layer117may include a process of planarizing a molding layer after forming the molding layer on the first redistribution layer111and encapsulating the first semiconductor chip110and the conductive posts116. Specifically, a portion of the molding layer formed on the conductive posts116may be removed and upper surfaces of the conductive posts116may be exposed. For example, a process of removing a portion of the molding layer may include a process of grinding a portion of the molding layer.

Referring toFIG.8E, the second redistribution layer121may be disposed on the lower molding layer117. Specifically, the second redistribution layer121may be disposed to be connected to the conductive posts116exposed by the lower molding layer117.

Referring toFIG.8F, the plurality of second bumps122and the second semiconductor chip120may be disposed on the second redistribution layer121. The second semiconductor chip120may be mounted on the second redistribution layer121by using the plurality of second bumps122. For example, the second semiconductor chip120may be mounted on the second redistribution layer121in a flip-chip structure. The second semiconductor chip120may be connected to the second redistribution layer121by the plurality of second bumps122.

Referring toFIG.8G, the upper molding layer123may be formed on the second redistribution layer121for encapsulating the second semiconductor chip120and the plurality of second bumps122. In some embodiments, a process of forming the upper molding layer123may include a process of planarizing a molding layer after forming the molding layer on the second redistribution layer121for encapsulating the second semiconductor chip120and the plurality of second bumps122. In this case, the upper molding layer123may include a portion disposed between the second semiconductor chip120and the second redistribution layer121to encapsulate the plurality of second bumps122.

Referring toFIG.8H, the carrier substrate150may be removed, and the plurality of external connection terminals130may be formed under the first redistribution layer111. As a result, the semiconductor package10may be manufactured.

FIG.9AandFIG.9Bare cross-sectional views for explaining a method of manufacturing a semiconductor package according to some embodiments. Specifically,FIG.9AandFIG.9Bare cross-sectional views showing a process followingFIG.8Cto explain a manufacturing method of the second semiconductor package11described with reference toFIG.2.

Referring toFIG.9A, the first underfill layer118for encapsulating the plurality of first bumps115may be formed between the circuit board112and the first redistribution layer111.

Referring toFIG.9B, the lower molding layer117may be disposed on the first redistribution layer111for encapsulating the first semiconductor chip110and the conductive posts116. Specifically, the lower molding layer117may be disposed on the first redistribution layer111to encapsulate the intermediate molding layer114molding the first semiconductor chip110, the adhesive layer119, the circuit board112, and the bonding wires113together with the first underfill layer118, and the conductive posts116. Here, the lower molding layer117may include a portion disposed between the circuit board112and the first redistribution layer111to encapsulate the plurality of first bumps115.

Subsequently, the second semiconductor package11ofFIG.2may be manufactured by performing a subsequent process.

FIG.10AandFIG.10Bare cross-sectional views for explaining a method of manufacturing semiconductor packages according to some embodiments. Specifically,FIG.10AandFIG.10Bare cross-sectional views showing a process followingFIG.8Fto explain a manufacturing method of the third semiconductor package12described with reference toFIG.3.

Referring toFIG.10A, the second underfill layer124for encapsulating the plurality of second bumps122may be formed between the second semiconductor chip120and the second redistribution layer121.

Referring toFIG.10B, the upper molding layer123disposed on the second redistribution layer121for encapsulating the second semiconductor chip120and the second underfill layer124. Specifically, the upper molding layer123may be formed to encapsulate the second underfill layer124encapsulating the plurality of second bumps122together with the second semiconductor chip120and the second redistribution layer121. In this case, the upper molding layer123may not include a portion disposed between the second semiconductor chip120and the second redistribution layer121to encapsulate the plurality of second bumps122.

Subsequently, the third semiconductor package12ofFIG.3may be manufactured by performing a subsequent process.

FIGS.11A to11Fare cross-sectional views for explaining a method of manufacturing the fifth semiconductor package20according to some embodiments. Specifically,FIGS.11A to11Fare cross-sectional views illustrating a method of manufacturing the fifth semiconductor package20described with reference toFIG.5.

Referring toFIG.11A, the first redistribution layer211may be disposed on the carrier substrate250. Subsequently, the conductive posts216may be formed on the first redistribution layer211.

Referring toFIG.11B, the first semiconductor chip210may be disposed on the carrier substrate150on which the first redistribution layer211and the conductive posts216are formed. Specifically, the first semiconductor chip210may be attached to the first redistribution layer211by using the adhesive layer219. For example, the first semiconductor chip210may be disposed between the plurality of conductive posts216.

Referring toFIG.11C, the bonding wires213connecting the first semiconductor chip210to the first redistribution layer211may be formed. The bonding wires213may be connected to an upper surface, which may be an active surface, of the first semiconductor chip210.

Referring toFIG.11D, the lower molding layer217may be disposed on the first redistribution layer211for encapsulating the first semiconductor chip210, the bonding wires213, and the conductive posts216.

In some embodiments, a process of forming the lower molding layer217may include a process of planarizing a molding layer after forming the molding layer for encapsulating the first semiconductor chip210, the bonding wires213, and the conductive posts216. Specifically, a portion of the molding layer formed on the conductive posts216may be removed to expose the upper surface of the conductive posts216. For example, a process of removing a portion of the molding layer may include a process of grinding a portion of the molding layer.

Referring toFIG.11E, the second redistribution layer221may be disposed on the lower molding layer217. Specifically, the second redistribution layer221may be disposed to be connected to the conductive posts116exposed by the lower molding layer217.

Subsequently, the plurality of second bumps222and the second semiconductor chip220may be disposed on the second redistribution layer221. The second semiconductor chip220may be disposed on the second redistribution layer221by using the plurality of second bumps222. For example, the second semiconductor chip220may be mounted on the second redistribution layer221in a flip-chip structure. The second semiconductor chip220may be connected to the second redistribution layer221by the plurality of second bumps222.

Referring toFIG.11F, the upper molding layer223may be disposed on the second redistribution layer221for encapsulating the second semiconductor chip220and the plurality of second bumps222. In some embodiments, a process of forming the upper molding layer223may include a process of planarizing a molding layer after forming the molding layer on the second redistribution layer221for encapsulating the second semiconductor chip220and the plurality of second bumps222. In this case, the upper molding layer223may include a portion disposed between the second semiconductor chip220and the second redistribution layer221to encapsulate the plurality of second bumps122.

Subsequently, the carrier substrate250may be removed, and the plurality of external connection terminals230may be formed under the first redistribution layer211. As a result, the fifth semiconductor package20may be manufactured.