SEMICONDUCTOR DEVICES AND METHODS FOR INCREASED CAPACITANCE

Semiconductor devices having increased capacitance without increased fin height or increased chip area are disclosed. Grooves are formed across a width of the fin(s) to increase the overlapping surface area with the gate terminal, in particular with a length of the groove being less than or equal to the fin width. Methods of forming such grooved fins and semiconductor capacitor devices are also described.

BACKGROUND

Integrated circuits are formed on a semiconductor wafer. Photolithographic patterning processes use ultraviolet light to transfer a desired mask pattern to a photoresist on a semiconductor wafer. Etching processes may then be used to transfer to the pattern to a layer below the photoresist. This process is repeated multiple times with different patterns to build different layers on the wafer substrate and make a semiconductor device.

DETAILED DESCRIPTION

The figures may provide views of fins across three different axes. The “plan view” is designated as being along the z-axis such that the length and width of the fin are visible, with the height extending into the page.

The “longitudinal side cross-sectional view” is arbitrarily designated as being along the x-axis such that the length and depth/height of the fin are visible, with the width extending into the page.

The “lateral side cross-sectional view” is arbitrarily designated as being along the y-axis such that the width and depth/height of the fin are visible, with the length extending into the page.

Numerical values in the specification and claims of this application should be understood to include numerical values which are the same when reduced to the same number of significant figures and numerical values which differ from the stated value by less than the experimental error of conventional measurement technique of the type described in the present application to determine the value. All ranges disclosed herein are inclusive of the recited endpoint.

The term “about” can be used to include any numerical value that can vary without changing the basic function of that value. When used with a range, “about” also discloses the range defined by the absolute values of the two endpoints, e.g. “about 2 to about 4” also discloses the range “from 2 to 4.” The term “about” may refer to plus or minus 10% of the indicated number.

The present disclosure relates to semiconductor devices and methods for improving the performance of such devices. One type of three-dimensional design for a semiconductor device is a fin field effect transistor (FinFET), which is illustrated in plan view inFIGS.1A and1ncross-sectional view inFIG.1B. Referring first toFIG.1A, the channel100between the source terminal102and the drain terminal104is in the form of thin vertical fins120. The source terminal102and the drain terminal104are illustrated as being in the same layer as the fins120, but can be located elsewhere (for example above the fins), depending on the three-dimensional design of the transistor/semiconductor device. It is common for a single FinFET to use several fins in parallel, covered by the same gate terminal. As better seen inFIG.1B, the fin(s)120are formed from the same material as the substrate110. A dielectric layer112is then applied to the surfaces of the fins, and a conductive gate terminal106is thus present on three sides of each fin120.

The structure of the gate terminal106being separated from the fin/channel120by the dielectric layer112creates a capacitor. The capacitance is proportional to the overlapping surface area between the gate terminal and the fins. Thus, the capacitance can be increased by increasing the surface area of the gate terminal, or by increasing the height of the fins. However, when increasing the surface area of the gate terminal, the total area of the overall semiconductor device/chip may be increased as well, which is not desirable. Simply increasing the height of the fins can decrease their stability, causing undesirable cracking.

The present disclosure thus relates to semiconductor capacitor devices with increased capacitance without increasing the total area of the overall semiconductor device or increasing the height of the fins, and to methods for making such devices. The increased capacitance is obtained by forming one or more grooves across the width of the fins, or in other words by cutting into the fins. This increases the total overlapping surface area between the fins and the gate terminal, without increasing the height of the fin. This structure thus has a high capacitance density. This also permits the capacitance to be independently controlled without changing the fin height.

FIGS.2A-12Cillustrate a first method for forming such a semiconductor device, in accordance with some embodiments. It is noted that for clarity, the plan views do not include the areas between fins, although those areas are included in the longitudinal side cross-sectional views and the lateral side cross-sectional views.FIG.13is a flowchart summarizing the various steps in the first method, and will be further discussed afterFIGS.2A-12C.

Referring first toFIGS.2A-2C, the fins120are illustrated here in an initial state. Each fin has an initial length LO, an initial width W0, and an initial depth or height DO. Although a rectangular shape is ideal for the fin, as can be seen inFIG.2BandFIG.2C, the fin may also have a generally trapezoidal cross-section, with potentially rounded sides and/or edges. The initial length LO and the initial width W0are measured at the top of the fin. The initial depth DO is also measured from the top of the fin.

In general embodiments, the initial fin length LO may range from about 20 nm to about 1200 nm. In general embodiments, the initial fin width W0may range from about 4 nm to about 20 nm. In general embodiments, the initial fin depth DO may range from about 10 nm to about 80 nm. Combinations of these ranges are contemplated.

The wafer substrate and the fins can be made of any semiconducting material. Such materials can include silicon, for example in the form of crystalline Si or polycrystalline Si. In alternative embodiments, the substrate and fins can be made of other elementary semiconductors such as germanium, or may include a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP).

The fins120may be formed by any appropriate process. For example, self-aligned double patterning (SADP) or self-aligned quadruple patterning (SAQP) can be used to form the fins. Briefly, a hard mask is deposited upon the substrate and then patterned to form a mandrel. Next, a spacer is formed by deposition upon the horizontal and vertical surfaces of the mandrel. The horizontal surfaces of the spacer are then etched, leaving only the spacer on the two vertical surfaces of the mandrel. The mandrel is then removed, leaving only the two vertical spacers. This doubles the line density upon the substrate (i.e. SADP) compared to the original pattern, or halves the line pitch. These SADP steps can be repeated using the two vertical spacers as a new mandrel to halve the pitch again (i.e. SAQP). The spacers are then used as a mask to perform etching of the substrate and obtain the fins.

Referring next toFIGS.3A-3C, a patterned mask130is applied to the fins120. The mask is typically formed using photoresist, although a hard mask material, such as a nitride, could also be used. As illustrated here by way of example, the fins are exposed in three areas132, which will correspond to grooves that are formed across the width of each fin. The fins are then etched to form the grooves. This may be done, for example, using wet etching processes, dry etching processes, or plasma etching.

Referring now toFIGS.4A-4C, the patterned mask has been removed, and the etched fin120with fin cuts or grooves is shown. In the plan view ofFIG.4A, dotted rectangles are used to indicate the location of the grooves140on the fins120.

As illustrated here, three grooves140are formed which extend across the width of the fin structure. The length, width, and depth of each groove is measured in the same direction as the length, width, and depth of the fin. The three grooves have the same depth, which is indicated as depth Dg. The initial fin depth D0is also shown. In particular embodiments, the groove depth Dg can be deeper or shallower than the initial fin depth D0. Put another way, Dg can be greater than or less than D0. In particular embodiments, and as illustrated here, Dg is less than D0.

The length and depth of the grooves can differ between each other, which is determined by the patterned mask. For illustrative purposes, the length of one groove at the top of the fin is indicated as length Lg. When Lg is less than or equal to W0, there are multiple combinations of groove length and groove depth for which the surface area within the new groove is greater than the surface area of the portion of the original fin which was removed to form the groove. As a result, then, the capacitance can be increased to a desired value by varying the total number of grooves and their groove length and groove depth.

As illustrated inFIG.4B, each groove140also has a trapezoidal shape, with two sides142,144and a floor146. The shape of the groove may vary depending on the etching method, and for example may be rectangular, or triangular (i.e. without a floor), or trapezoidal. An illustrative example of a fin120with rectangular grooves140is provided inFIG.4D, and an illustrative example of a fin120with triangular grooves140is provided inFIG.4E.

Referring now toFIGS.5A-5C, in an optional step, ion implantation is performed on the fin120(indicated with arrows). This may be done, for example, to set the threshold voltage to a desired value, or to modify other behavior or properties. Common p-type dopants may include boron or gallium. Common n-type dopants may include phosphorus or arsenic. The ion implantation is also illustrated inFIG.5Cas being performed in the areas between fins, but this is not required, and ion implantation can be performed solely on the fins using appropriate masking of the areas between fins.

Continuing inFIGS.6A-6C, a shallow trench isolation (STI) layer150is deposited over the fins120. The STI layer is formed from a dielectric material, commonly silicon dioxide, although other dielectric materials can also be used such as undoped polysilicon, silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass, or other low-k dielectric material. The deposition can be done using physical vapor deposition (PVD) or chemical vapor deposition (CVD) or spin-on processes known in the art, or can be grown via oxidation. As seen inFIG.5B, the STI layer also fills the grooves140.

Continuing withFIGS.7A-7C, the STI layer150is etched. This can be done, for example, using wet etching processes, dry etching processes, or plasma etching. As illustrated here, the STI layer is etched to a level below the grooves140, such that the STI layer is not present within the grooves, and fills only the areas between fins to form isolation regions152between adjacent fins. As will be seen further herein, in other embodiments, the STI layer can be present within the grooves.

Next, inFIGS.8A-8C, a first gate stack160is formed. As seen inFIG.8B, the gate stack160fills the grooves140. As seen inFIG.8C, the gate stack160also fills the areas between adjacent fins120. As illustrated here, the gate stack160includes a gate oxide layer162adjacent the fin120, and a gate layer164upon the gate oxide layer162. An optional cap layer166upon the gate layer164is also illustrated.

The gate oxide layer may be any dielectric material, for example silicon dioxide, hafnium silicate, zirconium silicate, hafnium dioxide, or zirconium dioxide. The gate oxide layer162may be very thin compared to the gate layer164. The gate oxide layer may be formed by a process that produces a thin film, such as atomic layer deposition (ALD). Alternatively, the gate oxide layer can be grown by thermal oxidation of the substrate, for example at a temperature of about 850° C. to about 950° C. in the presence of water or oxygen (O2). As yet another example, the gate oxide layer could be formed by a chemical vapor deposition (CVD) process, for example using 02 along with silane (SiH4) or dichlorosilane (SiH2Cl2), or using tetraethyl orthosilicate (TEOS) at elevated temperatures above about 600° C. As yet another example, the gate oxide layer could be formed by the decomposition of TEOS at temperatures of about 600° C. to about 650° C., or through plasma enhanced CVD at lower temperatures.

The gate layer may be any electrically conductive material, for example aluminum, polysilicon (doped or undoped), tungsten, a metal silicide such as TiSi or MoSi2or TaSi or WSi2, or material such as Ta, TaN, Nb, WN, or WN/RuO2. The cap layer166, when present, is used as a mask and can be made of appropriate materials such as silicon oxide, silicon nitride, silicon oxynitride, or other metal. The gate layer164and the optional cap layer166may be formed by PVD or CVD, or by other processes such as sputtering.

As will be seen further below, this gate stack may be a dummy gate stack which is subsequently removed and replaced, or may be used as the gate terminal in the final semiconductor device. The three layers may each be individually deposited upon the substrate, then a patterned mask is applied (e.g. photoresist) and the layers are etched to obtain the gate stack in the desired location. Wet etching processes, dry etching processes, or plasma etching may be used as desired for etching of each layer.

InFIGS.9A-9C, gate spacers170and a dielectric layer180are formed upon the exposed portions of the fins120and the STI layer150. The fins120are shown in dashed line outline. The gate spacers act as an electrical insulator, and can be made from any oxide, such as silicon dioxide (which may be doped with fluorine or carbon). The gate spacer can be formed by a deposition process (e.g. PVD or CVD) on the entire surface, then applying a patterned mask and etching to remove material from undesired locations. The dielectric layer180may be any suitable material, such as silicon dioxide (which may be doped with fluorine or carbon).

In some embodiments, the gate stack160acts as a dummy stack that provides support for forming the gate spacers170. InFIGS.10A-10C, the gate stack160is removed. For example, a patterned mask can be placed over the gate spacers170and the dielectric layer180, leaving the gate stack exposed, and the gate stack is then removed using an appropriate etching process.

InFIGS.11A-11C, a new gate stack190is then formed. As illustrated here, the new gate stack includes a gate oxide layer192and a gate layer194. Compared to the gate oxide layer162ofFIGS.8A-8C, the gate oxide layer also runs up the side of the gate spacers170, and can be formed using ALD. Again, the gate oxide layer may be any dielectric material, for example silicon dioxide, hafnium silicate, zirconium silicate, hafnium dioxide, or zirconium dioxide. The gate layer194can be, for example, a single-layer structure formed from a single metal, or can be a multi-layer structure containing different metals. The gate layer can be deposited using methods such as PVD or CVD or sputtering. Again, the steps shown inFIGS.10A-11Care optional, and the original gate stack formed inFIGS.8A-8Ccan be maintained in the final device if desired.

Finally, inFIGS.12A-12C, additional layers are formed to complete the semiconductor device/transistor200. An insulation layer210is deposited over the gate stack190and the dielectric layer180. As best seen inFIG.12B, vias212are etched through the insulation layer210and the dielectric layer180down to the fins120, and then filled with an electrically conductive material which is also used to form contacts214for the source terminal and the drain terminal. As best seen inFIG.12C, a via222is also etched through the insulation layer210down to the gate stack190, then filled with an electrically conductive material which is also used to form a contact224for the gate terminal. The insulation layer is electrically insulating, and can be made from any appropriate material.

FIG.13is a flowchart summarizing the various steps illustrated inFIGS.2A-12C.

In step300, a substrate with at least one fin is received. The substrate usually has a plurality of fins thereon. This is illustrated inFIGS.2A-2C.

In step305, a mask with a pattern is applied to the substrate. The pattern extends across the width of the fin(s), and exposes one or more portions of the fin. This is illustrated inFIGS.3A-3C.

In step310, the fin/substrate is etched. This forms a groove in the fin which extends across the entire width of the fin. Multiple grooves can be formed in this step if desired. In step315, the mask is removed. The result after this step is illustrated inFIGS.4A-4C.

In optional step317, ion implantation is performed on the fin(s). This is illustrated inFIGS.5A-5C.

In step320, an STI layer is applied to the substrate. The STI layer may cover the fins. This is illustrated inFIGS.6A-6C. In step325, the STI layer is etched to form isolation regions between fins. This is illustrated inFIGS.7A-7C.

In step330, a first gate stack is formed which fills the groove(s) within the fin(s). The layers within the gate stack include a gate oxide layer, a gate layer, and an optional cap layer. This is illustrated inFIGS.8A-8C.

In step335, gate spacers are formed adjacent the first gate stack. In step340, a dielectric layer is formed adjacent the gate spacers, such that the gate spacers separate the dielectric layer from the first gate stack. This is illustrated inFIGS.9A-9C.

In optional step341, the first gate stack is removed. This is illustrated inFIGS.10A-10C. In optional step343, a second or new gate stack is formed. The second gate stack may comprise a gate oxide layer and a metal gate layer. This is illustrated inFIGS.11A-11C. It is noted that these steps are optional, and the first gate stack may be maintained within the final semiconductor device if desired.

In step345, an insulation layer is formed over the gate stack and the dielectric layer. In step350, vias are etched through the insulation layer and the dielectric layer, exposing portions of the fin(s). In step355, the vias are filled with an electrically conductive material. In step360, a via is etched through the insulation layer, exposing a portion of the gate stack. In step365, the via is filled with an electrically conductive material. These vias form contacts for the source terminal, the drain terminal, and the gate terminal. It is noted that steps350,355,360,365can be performed in any desired order. The result is illustrated inFIGS.12A-12C.

FIGS.14A-16Cillustrate a second method for forming such a semiconductor device, in accordance with some embodiments. In this second embodiment, the grooves within the fins are formed at the same time as the fins. Put another way, the same photolithographic and etching steps are also used to form the grooves.

Initially,FIGS.14A-14Cillustrate the substrate110with a patterned mask400thereon. The substrate110is exposed in all areas except where the fins are desired to be placed or located. The entire substrate, including the areas between where the fins will be etched, are shown in all three views. The patterned mask400includes one or more spacer lines402; multiple spacer lines are shown here. Each spacer line402includes at least one gap404(indicated as a dotted box); three gaps are illustrated in each spacer line in this example. The length of each gap Lg is less than or equal to a width of the spacer line Sw. The spacer lines correspond to the areas on the substrate that will become fins. The spacer line gaps404correspond to the groove(s) that will be formed in the fins.

FIGS.15A-15Cillustrate the substrate110after etching, with the patterned mask400still applied thereon. The plan view ofFIG.15Ahas dotted rectangles indicating where the grooves140have been formed. The grooves are more visible inFIG.15B. The fins120are now visible inFIG.15C, along with the areas406between fins.

InFIGS.16A-16C, the patterned mask has been removed. In the plan view ofFIG.16A, the substrate is no longer shown between the fins120for clarity. Dotted rectangles are used again to indicate the location of the grooves140on the fins120. In this second embodiment, the groove depth Dg is substantially equal to the initial fin depth DO. The resulting structure is substantially similar to the structure depicted inFIGS.4A-4C.

Continuing then,FIGS.17A-20Cillustrate some alternative processing steps which can also be used to prepare a semiconductor device.

InFIGS.17A-17C, a shallow trench isolation (STI) layer150is deposited over the fins120. As seen inFIG.17B, the STI layer also fills the grooves140. The resulting structure is substantially similar to the structure depicted inFIGS.6A-6C.

InFIGS.18A-18C, the STI layer is then etched. However, in contrast to the structure ofFIGS.7A-7C, the STI layer is etched such that the STI layer is still present within the grooves (indicated with reference numeral154).

Next, as illustrated inFIGS.19A-19C, a patterned mask410(e.g. photoresist) can be applied to the ends of the fin(s)120, leaving the grooves140exposed. Further etching is then performed, such that the depth of the STI portions154within the grooves Sg and in the area where the gate stack will be formed is less than the depth of the STI portions in the area where the dielectric layer will be formed Sd.

FIGS.20A-20Cillustrate the resulting transistor200after the gate oxide layer192, gate layer194, gate spacers170, dielectric layer180, insulation layer210, vias212,222, and contacts214,216,224are applied as described inFIGS.8A-12Cand in the flowchart ofFIG.13. The presence of the STI layer between the fins and the gate oxide layer provides another way to control the capacitance, by changing the overlapping surface area between the gate stack and the fins.

FIG.21is a flowchart summarizing the various steps illustrated inFIGS.14A-20C.

In step505, a mask with a pattern is applied to the substrate. The pattern includes one or more spacer lines, corresponding to the number of fins to be formed. Each spacer line has one or more gaps which will correspond to the grooves. The length of each gap is less than or equal to the width of the spacer line This is illustrated inFIGS.14A-14C.

In step510, the substrate is etched. This forms one or more fins, which have one or more grooves that extend across the width of the fin. This is illustrated inFIGS.15A-15C.

In step515, the mask is removed. The result after this step is illustrated inFIGS.16A-16C.

In optional step517, ion implantation is performed on the fin(s). This step corresponds to that previously illustrated inFIGS.5A-5C, and is not illustrated again.

In step520, an STI layer is applied to the substrate. The STI layer may cover the fins. This is illustrated inFIGS.17A-17C. In step525, the STI layer is etched to form isolation regions between fins. Portions of the STI layer are still present within the grooves. This is illustrated inFIGS.18A-18C.

Next, in step530, a mask is applied to the ends of the fin(s), leaving the grooves exposed. In step535, the grooves are further etched so that the depth of the STI portions within the grooves is reduced compared to the depth of the STI portions in the area beyond the ends of the fins. The result after this step is illustrated inFIGS.19A-19C.

Next, in step540, a first gate stack is formed which fills the groove(s) within the fin(s). The layers within the gate stack include a gate oxide layer, a gate layer, and an optional cap layer. In step545, gate spacers are formed adjacent the first gate stack. In step550, a dielectric layer is formed adjacent the gate spacers, such that the gate spacers separate the dielectric layer from the first gate stack. These steps correspond to those previously illustrated inFIGS.8A-9C, and are not illustrated again.

In optional step551, the first gate stack is removed. In optional step553, a second or new gate stack is formed. The second gate stack may comprise a gate oxide layer and a metal gate layer. Again, these steps are optional, and the first gate stack may be maintained within the final semiconductor device if desired. These steps correspond to those previously illustrated inFIGS.10A-11C, and are not illustrated again.

In step555, an insulation layer is formed over the gate stack and the dielectric layer. In step560, vias are etched through the insulation layer and the dielectric layer, exposing portions of the fin(s). In step565, the vias are filled with an electrically conductive material. In step570, a via is etched through the insulation layer, exposing a portion of the gate stack. In step575, the via is filled with an electrically conductive material. These vias form contacts for the source terminal, the drain terminal, and the gate terminal. The steps for forming the contacts560,565,570,575can be performed in any order. The result is illustrated inFIGS.20A-20C.

FIGS.22A-28Eillustrate a third method and a fourth method for forming a semiconductor device, in accordance with some embodiments. In these two methods, the semiconductor device includes two separate transistors, which have different capacitances. The transistor with a higher capacitance is denoted as a “capacitor region”, and the transistor with a lower capacitance is denoted as a “normal region”. Again, for clarity, the plan views do not include the areas between fins.FIG.29is a flowchart summarizing the various steps in these two methods, and will be further discussed afterFIGS.21A-28E.

Beginning withFIGS.22A-22E, the fins120are shown. The fins extend across both the capacitor region600and the normal region610, as seen inFIG.22A. it is contemplated that the fin length, fin width, and fin height/depth are the same in both regions.

Grooves122are present in the capacitor region, and grooves124are also present in the normal region. The grooves in the capacitor region have depth Dc and length Lc. The grooves in the normal region have depth Dn and length Ln. As illustrated here, the two depths Dc, Dn are equal, and the two lengths Lc, Ln are also equal. The longitudinal side cross-sectional views and the lateral side cross-sectional views are the same for both regions, as seen inFIGS.22B-22E.

In other embodiments, it is contemplated that the depth Dc is greater than the depth Dn and/or the length Lc is greater than the depth Ln. As a result, the surface area of the grooves122in the capacitor region is greater than the surface area of the grooves124in the normal region. Again, it is noted that the two lengths Lc, Ln are also less than or equal to the fin width W0. The groove depth Dc of the grooves in the capacitor region can be made different from the groove depth Dn of the grooves in the capacitor region, for example, by applying a mask (e.g. photoresist) to expose one region and not the other region, so that only the grooves in the exposed region are etched. This permits the groove depth to be independently controlled.

Next, inFIGS.23A-23E, an STI layer150is deposited over the fins. The STI layer also fills the grooves122,124in both regions. The portion of the STI layer in the capacitor region is marked with reference numeral652, and the portion of the STI layer in the capacitor region is marked with reference numeral654.

Then, inFIGS.24A-24E, a mask620(for example, photoresist) is applied to only the normal region610and not the capacitor region600. The STI layer150is then etched. Due to the presence of the mask, only the STI layer in the capacitor region652is etched. As a result, the depth of the STI layer in the capacitor region652is less than the depth of the STI layer in the normal region654. This intermediate depth of the STI layer in the capacitor region is indicated as Sci, while the depth of the STI layer in the normal region is indicated as Sn.

The mask620is then removed, resulting in the structure shown inFIGS.25A-25E. InFIGS.26A-26E, the STI layer150is etched again, reducing the thickness of the STI layer in both regions652,654, so that the fins are exposed in both regions. The final depths of the STI layer in each region are now indicated as depths Scf, Snf.

FIGS.27A-27Eillustrate the two regions after the dielectric layer180, gate spacers170, gate oxide layer192, and gate layer194have been deposited and patterned to form a first gate stack660in the capacitor region and a second gate stack670in the normal region, thus forming two separate transistors, one in each region. As seen in the plan view ofFIG.27A, the dielectric layer180electrically isolates the two transistors from each other. The fins120are shown as dashed lines. As seen by comparingFIGS.27B-27CwithFIGS.27D-27E, the transistor in the capacitor region has a higher capacitance than the transistor in the normal region, due to the higher overlapping surface area between the fins120and the first gate stack660.

FIGS.28A-28Eillustrate the fourth method for forming a semiconductor device. The device ofFIGS.28A-28Ediffers from that ofFIGS.27A-27Ein that no grooves are present in the fins in the normal region610, as best seen inFIG.28D. Again, the result of this structure is that the transistor in the capacitor region has a higher capacitance than the transistor in the normal region. This device can be formed by omitting the creation of grooves in the portions of the fins located in the normal region.

The devices ofFIGS.27A-28E, having transistors with different capacitances, may act as a CMOS circuit. This may be useful for chips used in image processing or other applications.

In additional embodiments, other structures can be changed between the capacitor region and the normal region to change their capacitances. As already described, the grooves between the two regions could have different depths, or have STI layers with different depths. As another example, it is contemplated that the gate oxide layer in the capacitor region and the normal region can be different from each other. For example, the two gate oxide layers could be made from different materials that have a different dielectric constant, or the two gate oxide layers could have different thicknesses. As yet another example, the fins in the two regions could have different doping concentrations, and/or use different dopants.

FIG.29is a flowchart summarizing the various steps illustrated inFIGS.22A-28E.

In step705, a substrate with at least one fin is received. The substrate usually has a plurality of fins thereon. At least one groove is present in the fin, which extends across the entire width of the fin. As illustrated inFIGS.22A-22E, a plurality of grooves is present, with at least a first groove in a capacitor region and a second groove in a normal region.

In optional step707, ion implantation is performed on the fin(s). It is noted that the ions implanted in the capacitor region and the normal region may be the same, or may be different. In more particular embodiments, it is contemplated that one region is doped with a p-type dopant and the other region is doped with an n-type dopant. This step corresponds to that previously illustrated inFIGS.5A-5C, and is not illustrated again.

In step710, an STI layer is applied to the substrate. The STI layer may cover the fins, and is present in both the capacitor region and the normal region. This is illustrated inFIGS.23A-23E. In step715, a mask is applied to only the normal region. A mask is not applied to the capacitor region, so the STI layer in the capacitor region remains exposed. In step720, the STI layer in the capacitor region is etched to an intermediate depth. This is illustrated inFIGS.24A-24E.

In step725, the mask is removed. This is illustrated inFIGS.25A-25E. In step730, the STI layer is etched again. This etching reduces the depth of the STI layer in both the capacitor region and the normal region, so that the fins are exposed. This is illustrated inFIGS.26A-26E.

Next, in step735, a first gate stack is formed in the capacitor region, which fills the fin groove(s) present in the capacitor region. A second gate stack is also formed in the normal region, which fills any fin groove(s) present in the normal region (compareFIGS.27D-27EwithFIGS.28D-28E). In step740, gate spacers are formed adjacent the two gate stacks. In step745, a dielectric layer is formed adjacent the gate spacers, such that the gate spacers separate the dielectric layer from the two gate stacks. These steps correspond to those previously illustrated inFIGS.8A-9C, and are not illustrated again.

In optional step747, one or both gate stacks are removed. In optional step749, one or two new gate stacks are formed. The new gate stacks may comprise a gate oxide layer and a metal gate layer. Again, these steps are optional, and the original gate stacks may be maintained within the final semiconductor device if desired. These steps correspond to those previously illustrated inFIGS.10A-11C, and are not illustrated again.

In step750, an insulation layer is formed over the two gate stacks and the dielectric layer. In step755, vias are etched through the insulation layer and the dielectric layer in both the capacitor region and the normal region, exposing portions of the fin(s). In step760, vias are etched through the insulation layer, exposing a portion of the gate stack in both the capacitor region and the normal region. In step765, the vias are filled with an electrically conductive material to form contacts for the source terminal, the drain terminal, and the gate terminal. The steps for forming the contacts755,760,765can be performed in any order. These steps correspond to those previously illustrated inFIGS.12A-12C(suitably modified), and are not illustrated again.

The semiconductor devices described herein, having fins with grooves across the fin width, provide higher capacitance compared to fins without such grooves. This provides the advantage of being able to independently control the capacitance without having to change the fin height or change the overall chip area. In addition, the grooves can be made without needing to add extra processing steps to the overall chip manufacturing process. Additional parameters, such as by changing the presence or depth of an STI layer within the grooves, or by varying properties of the gate oxide layer, can also be used to provide further control over the capacitance.

Some embodiments of the present disclosure thus relate to semiconductor devices. The devices comprise a substrate that comprises at least one fin. The fin has at least a first groove across a width of the fin. A first gate stack is disposed over the at least one fin, and fills the first groove. A first source and a first drain are each electrically connected to the at least one fin.

Also disclosed in various embodiments are methods for forming a semiconductor capacitor device. A fin is formed on a substrate. A mask with a pattern across a width of the fin is then applied. The fin is etched to form at least a first groove across the width of the fin. The mask is removed. A first gate stack is formed in the first groove of the fin.

Other embodiments disclosed herein include other methods for forming a semiconductor capacitor device. A first mask with a pattern is applied to a substrate. The first mask pattern comprises a spacer line that includes at least one gap, wherein the length of each gap is less than or equal to the width of the spacer line. The substrate is then etched to form a fin with at least one groove across the width of the fin. The first mask is then removed.