SEMICONDUCTOR INTERCONNECTION STRUCTURES AND METHODS OF FORMING THE SAME

An interconnection structure includes a first dielectric layer, a first conductive feature, a first liner layer, a second conductive feature, a second liner layer, and an air gap. The first conductive feature is disposed in the first dielectric layer. The first liner layer is disposed between the first conductive feature and the first dielectric layer. The second conductive feature penetrates the first dielectric layer. The second liner layer is disposed between the second conductive feature and the first dielectric layer. The air gap is disposed in the first dielectric layer between the first liner layer and the second liner layer. The first liner layer and the second liner layer include metal oxide, metal nitride, or silicon oxide doped carbide.

BACKGROUND

As the semiconductor industry introduces new generations of integrated circuits (IC) having higher performance and more functionality, the density of the elements forming the ICs increases, while the dimensions, sizes and spacing between components or elements are reduced. The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area.

For manufacturing different conductive layers on the substrate, various structures and manufacturing methods are utilized to form the interconnection structures between the conductive layers. However, the integrated fabrication also brings out some issues, such as reliability, high capacitance, or high resistance. Therefore, there is a need in the art to provide improved devices or methods that can address the issues mentioned above.

DETAILED DESCRIPTION

FIG.1is a perspective view of one of the various stages of manufacturing a semiconductor device structure100, in accordance with some embodiments. As shown inFIG.1, the semiconductor device structure100includes a substrate101having at least a plurality of devices formed thereover. The devices, such as transistors, diodes, imaging sensors, resistors, capacitors, inductors, memory cells, a combination thereof, and/or other suitable devices, may be formed on the substrate101. In some embodiments, the interconnection structures may be formed on or below the devices.

FIGS.2A-2Bare cross-sectional side views of various stages of manufacturing the semiconductor device structure100, in accordance with some embodiments.FIG.2Ais a cross-sectional side view of the semiconductor device structure100taken along line A-A ofFIG.1, andFIG.2Bis a cross-sectional side view of the semiconductor device structure100taken along line B-B ofFIG.1. The line A-A ofFIG.1extends along a direction that is substantially perpendicular to the longitudinal direction of a gate stack106, and the line B-B ofFIG.1extends along the longitudinal direction of the gate stack106. As shown inFIGS.2A and2B, the semiconductor device structure100includes the substrate101, and one or more devices102are formed on the substrate101. The interconnection structures may be formed over the devices102.

The substrate101may be a semiconductor substrate. In some embodiments, the substrate101includes a crystalline semiconductor layer on at least the surface of the substrate101. The substrate101may include a crystalline semiconductor material such as, but not limited to silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium arsenic antimonide (GaAsSb), and indium phosphide (InP). In some embodiment, the substrate101is made of Si. In some embodiments, the substrate101is a silicon-on-insulator (SOI) substrate, which includes an insulating layer (not shown) disposed between two silicon layers. In one aspect, the insulating layer is an oxygen-containing material, such as an oxide.

The substrate101may include various regions that have been suitably doped with impurities (e.g., p-type or n-type impurities). The dopants are, for example phosphorus for an n-type fin field effect transistor (FinFET) and boron for a p-type FinFET.

As described above, the devices102may be any suitable devices, such as transistors, diodes, imaging sensors, resistors, capacitors, inductors, memory cells, or a combination thereof. In some embodiments, the devices102are transistors, such as planar field effect transistors (FETs), FinFETs, nanostructure transistors, or other suitable transistors. The nanostructure transistors may include nanosheet transistors, nanowire transistors, gate-all-around (GAA) transistors, multi-bridge channel (MBC) transistors, or any transistors having the gate electrode surrounding the channels. An example of the device102formed between the substrate101and the interconnection structures (such as the interconnection structure200shown inFIGS.3A-3L or4A-4D) may be a FinFET or a nanostructure, which is shown inFIGS.2A and2B. An exemplary device102may include source/drain (S/D) regions104and a gate stack106disposed between the S/D regions104serving as source regions and the S/D regions104serving as drain regions. While there is only one gate stack106formed on the substrate101, it is contemplated that two or more gate stacks106may also be formed on the substrate101. Channel regions108are formed between the S/D regions104serving as source regions and the S/D regions104serving as drain regions.

The S/D regions104may include a semiconductor material, such as Si or Ge, a III-V compound semiconductor, an II-VI compound semiconductor, or other suitable semiconductor material. Exemplary S/D region104may include, but are not limited to, Ge, SiGe, GaAs, AlGaAs, GaAsP, SiP, InAs, AlAs, InP, GaN, InGaAs, InAlAs, GaSb, AlP, GaP, and the like. The S/D regions104may include p-type dopants, such as boron; n-type dopants, such as phosphorus or arsenic; and/or other suitable dopants including combinations thereof. The S/D regions104may be formed by an epitaxial growth method using CVD, atomic layer deposition (ALD) or molecular beam epitaxy (MBE). The channel regions108may include one or more semiconductor materials, such as Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, or InP. In some embodiments, the channel regions108include the same semiconductor material as the substrate101. In some embodiments, the devices102are FinFETs, and the channel regions108are a plurality of fins each having at least three surfaces wrapped around by the gate stack106. In some other embodiments, the devices102are nanosheet transistors, and the channel regions108include two or more nanosheets surrounded by the gate stack106.

Each gate stack106includes a gate electrode layer110disposed over the channel region108or partially/fully surrounding the channel region108. The gate electrode layer110may be a metal-containing material such as tungsten, cobalt, aluminum, ruthenium, copper, multilayers thereof, or the like, and can be deposited by ALD, plasma enhanced chemical vapor deposition (PECVD), MBD, physical vapor deposition (PVD), or any suitable deposition technique. Each gate stack106may include an interfacial dielectric layer112, a gate dielectric layer114disposed on the interfacial dielectric layer112, and one or more conformal layers116disposed on the gate dielectric layer114. The gate electrode layer110may be disposed on the conformal layers116. The interfacial dielectric layer112may include a dielectric material, such as an oxygen-containing material or a nitrogen-containing material, or multilayers thereof, and may be formed by any suitable deposition method, such as CVD, PECVD, or ALD. The gate dielectric layer114may include a dielectric material such as an oxygen-containing material or a nitrogen-containing material, a high-k dielectric material having a k value greater than that of silicon dioxide, or multilayers thereof. The gate dielectric layer114may be formed by any suitable method, such as CVD, PECVD, or ALD. The conformal layers116may include one or more barrier layers and/or capping layers, such as a nitrogen-containing material, for example tantalum nitride (TaN), titanium nitride (TiN), or the like. The conformal layers116may further include one or more work-function layers, such as aluminum titanium carbide, aluminum titanium oxide, aluminum titanium nitride, or the like. The term “conformal” may be used herein for ease of description upon a layer having substantial same thickness over various regions. The conformal layers116may be deposited by ALD, PECVD, MBD, or any suitable deposition technique.

One or more gate spacers118are formed along sidewalls of the gate stack106(e.g., sidewalls of the gate dielectric layers114). The gate spacers118may include silicon oxycarbide, silicon nitride, silicon oxynitride, silicon carbon nitride, the like, multi-layers thereof, or a combination thereof, and may be deposited by CVD, PVD, ALD, or other suitable deposition technique.

Portions of the gate stacks106and the gate spacers118may be formed on isolation regions103. The isolation regions103are formed on the substrate101. The isolation regions103may include an insulating material such as an oxygen-containing material, a nitrogen-containing material, or a combination thereof. The insulating material may be formed by a high-density plasma chemical vapor deposition (HDP-CVD), a flowable chemical vapor deposition (FCVD), or other suitable deposition process. In one aspect, the isolation regions103includes silicon oxide that is formed by a FCVD process.

A contact etch stop layer (CESL)124is formed on a portion of the S/D regions104and the isolation region103, and a first interlayer dielectric (ILD)126is formed on the CESL124. The CESL124can provide a mechanism to stop an etch process when forming openings in the first ILD126. The CESL124may be conformally deposited on surfaces of the S/D regions104and the isolation regions103. The CESL124may include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbon nitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbon oxide, or the like, or a combination thereof, and may be deposited by CVD, PECVD, PVD, ALD, or any suitable deposition technique. The first ILD126may include an oxide formed by tetraethylorthosilicate (TEOS), un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), organosilicate glass (OSG), SiOC, and/or any suitable low-k dielectric materials (e.g., a material having a dielectric constant lower than silicon dioxide), and may be deposited by spin-on, CVD, FCVD, PECVD, PVD, or any suitable deposition technique.

A silicide layer120is formed on at least a portion of each S/D region104, as shown inFIGS.2A and2B. The silicide layer120may include a material having one or more of WSi, CoSi, NiSi, TiSi, MoSi and TaSi. In some embodiments, the silicide layer120includes a metal or metal alloy silicide, and the metal includes a noble metal, a refractory metal, a rare earth metal, alloys thereof, or combinations thereof. A conductive contact122is disposed on each silicide layer120. The conductive contact122may include a material having one or more of Ru, Mo, Co, Ni. W, Ti, Ta, Cu, Al, TiN or TaN, and the conductive contact122may be formed by any suitable method, such as electro-chemical plating (ECP), or PVD. The silicide layer120and the conductive contact122may be formed by first forming an opening in the first ILD126and the CESL124to expose at least a portion of the S/D region104, then forming the silicide layer120on the exposed portion of the S/D region104, and then forming conductive contact122on the silicide layer120.

FIGS.3A-3Lare cross-sectional side views of various stages of manufacturing a semiconductor structure300, including an interconnection structure301, in accordance with some embodiments. In some embodiments, the interconnection structure301may be formed on or below the semiconductor device structure100.FIG.5is a flow chart of a method500for manufacturing the interconnection structure301in accordance with some embodiments. For the purpose of better describing the present disclosure, the cross-sectional side view of the semiconductor structure300inFIGS.3A-3Land the method500inFIG.5will be discussed together. It is understood that the operations shown in the method500are not exhaustive and that other operations may be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown inFIGS.3A-3LandFIG.5.

As shown inFIG.3A, a semiconductor substrate302is provided. The semiconductor substrate302may be similar to substrate101discussed above. A plurality of devices304and a middle end of the line (MEOL) structure306may be formed on the semiconductor substrate302. In some embodiments, the plurality of devices304may be the devices102shown inFIGS.2A and2B.

In the MEOL structure306, low level interconnects (contacts), such as the conductive contacts122shown inFIGS.2A and2B, are formed over the S/D regions104and the gate electrode layer110. The MEOL structure306may have smaller critical dimensions and may be spaced closer together compared to a later formed back end of the line (BEOL) counterparts. A purpose of the contact layers of the MEOL structure306is to electrically connect the various regions of the transistors, i.e., the source/drain and metal gate electrode, to higher level interconnects in the BEOL.

As shown inFIG.3Aand operation502inFIG.5, a conductive layer308is formed over the MEOL structure306, an etch stop layer (ESL)310may be formed over the conductive layer308, and a dielectric layer312is formed over the ESL310. In some embodiments, the conductive layer308may be a conductive layer of other interconnection structures of the semiconductor structure300. In some embodiments, the conductive layer308may be a conductive layer above the MEOL structure306. In some embodiments, the conductive layer308may include Cu, Al, CuAl, Ru, Mo, W, and related alloys formed in a dielectric material (not shown). In some embodiments, the conductive layer308may be formed by ALD, CVD, PVD, electroless deposition (ELD), ECP, or other suitable processes.

In some embodiments, the ESL310may be used to control the etching depth in the dielectric layer312and serve as an etch stop when forming a later formed conductive feature in the dielectric layer312. In some embodiments, the ESL310may include SiNx, SiCxNy, AlNx, AlOx, AOxNy, SiOx, SiCx, SiOxCy, or other suitable materials. In some embodiments, the ESL310may be formed by CVD, PVD, ALD, spin coating, or other suitable processes. In some embodiments, the dielectric layer312may include or be made of porous SiCOH, dense SiCOH, BN, BC, or other suitable materials. In some embodiments, the dielectric layer312may formed by PECVD, ALD, PVD, or other suitable processes.

As shown inFIG.3Band operation504inFIG.5, a first opening314and a second opening316are formed in the dielectric layer312. The first opening314is formed in the dielectric layer312, and the second opening316penetrates the dielectric layer312to expose a portion of the conductive layer308. In some embodiments, the first opening314and the second opening316may be formed by dry etch, wet etch, or other suitable processes. In some embodiments, the first opening314may include a trench formed in the dielectric layer312. In some embodiments, the second opening316may include a via and a trench formed sequentially in the dielectric layer312to expose a portion of the conductive layer308. In some embodiments, the trench of the first opening314and the trench of the second opening316may be formed first, and then the via of the second opening316may be formed under the trench of the second opening316to expose a portion of the conductive layer308. In some embodiments, the via of the second opening316may be formed first penetrating the dielectric layer312and the ESL310to expose a portion of the conductive layer308, and the trench of the first opening314and the trench of the second opening316may be formed thereafter.

As shown inFIG.3Cand operation506inFIG.5, a liner layer318is conformally formed over the dielectric layer312. The liner layer318may cover the top surface of the dielectric layer312, the first opening314, and the second opening316including the exposed surface of the conductive layer308. In some embodiments, the liner layer318may include metal oxide, metal nitride, silicon oxide doped carbide (ODS), or other suitable materials. In some embodiments, the liner layer318may include AlOx, ZrOx, YOx, AlNx, TiNx, SiNx, SiCxNy, ODS, or other suitable materials. In some embodiments, the liner layer318may have a thickness between 5 Angstroms and 40 Angstroms. In some embodiments, the liner layer318may be formed by PECVD, ALD, PVD, or other suitable processes. The liner layer318may prevent the damage on sidewalls of the later formed barrier layer or conductive materials during a later etch process.

As shown inFIG.3Dand operation508inFIG.5, a portion of the liner layer318that covers the conductive layer308is removed. In other words, the liner layer318at the bottom of the opening316is removed to expose the conductive layer308. In some embodiments, the removal of the portion of the liner layer318may be performed by dry etch, or other suitable processes.

Then, as shown inFIG.3Eand operation510inFIG.5, a barrier layer320is deposited over the liner layer318and the exposed conductive layer308. In some embodiments, the barrier layer320may be conformally formed over the liner layer318. In other words, the barrier layer320may cover not only the liner layer318but also the exposed conductive layer308at the bottom of the second opening316. In some embodiments, the barrier layer320may include TaN, TiN, or other suitable materials. In some embodiments, the barrier layer320may have a thickness between 10 Angstroms and 30 Angstroms. In some embodiments, the barrier layer320may be formed by thermal ALD, or other suitable processes.

Then, as shown inFIG.3Eand operation512inFIG.5, a first conductive feature322is formed in the first opening314, and a second conductive feature326is formed in the second opening316. A conductive material may be deposited over the barrier layer320and fills the first opening314and the second opening316. Then, a planarization operation, e.g., chemical mechanical polishing (CMP), may be performed so that the first conductive feature322and the second conductive feature326are formed, as shown inFIG.3E.

In some embodiments, the first conductive feature322and the second conductive feature326may include Cu, Al, CuAl, Ru, Mo, W, and related alloys. In some embodiments, the first conductive feature322and the second conductive feature326may be formed by ALD, CVD, PVD, ELD, ECP, or other suitable processes. The liner layer318is disposed between the first conductive feature322and the dielectric layer312and between the second conductive feature326and the dielectric layer

Then, as shown inFIG.3F, a capping layer324is formed on the first conductive feature322and the second conductive feature326. In some embodiments, the capping layer324may include Cobalt (Co), or other suitable materials. In some embodiments, the capping layer324may be formed by CVD, ALD, or other suitable processes.

In some embodiments, the capping layer324is selectively formed on the first conductive feature322and the second conductive feature326but not on the dielectric layer312. In some embodiments, before the formation of the capping layer324, a pretreatment operation may be performed to clean the surfaces of the first conductive feature322and the second conductive feature326. For example, a wet clean process may be performed to remove copper oxide on top surfaces of the first conductive feature322and the second conductive feature326, some post CMP residue on the dielectric layer312, and/or organic contamination from the CMP on the dielectric layer312, the first conductive feature322and the second conductive feature326.

In some embodiments, the capping layer324may be formed by CVD process with Co precursor and H2. In some embodiments, the first conductive feature322and the second conductive feature326may include copper (Cu). For example, during the CVD process, H2strips the dicarbonyl groups from the Co precursor resulting in cobaltocene plus H2. The Cu surfaces of the first conductive feature322and the second conductive feature326then bond with the hydrogen. Then, the cobaltocene replaces the hydrogen on the surfaces of the first conductive feature322and the second conductive feature326and forms Co capping layer (the capping layer324) on the first conductive feature322and the second conductive feature326. In some embodiments, the capping layer324may be formed by CVD, ALD, or other suitable processes.

As shown inFIG.3Gand operation514inFIG.5, a blocking layer328is formed on the dielectric layer312. In some embodiments, the blocking layer328is formed by molecules with silicon-based function groups, and therefore the blocking layer328is formed on the dielectric layer312, e.g., low k materials, but not on the capping layer324, e.g., Co. For example, the blocking layer328may include a head group connected to a function group by way of a molecular chain. The head group is configured to adhere to preferred surfaces such as the surface of the dielectric layer312while not adhering to other surfaces such as the surfaces of the capping layer324. In some embodiments, the head group may include butyltriethoxysilane, cyclohexyltrimethoxysilane, cyclopentyltrimethoxysilane, dodecyltriethoxysilane, dodecyltrimethoxysilane, decyltriethoxysilane, dimethoxy(methyl)-n-octylsilane, triethoxyethylsilane, ethyltrimethoxysilane, hexyltrimethoxysilane, hexyltriethoxysilane, hexadecyltrimethoxysilane, hexadecyltriethoxysilane, triethoxymethylsilane, trimethoxy(methyl)silane, methoxy(dimethyl)octadecylsilane, methoxy(dimethyl)-n-octylsilane, octadecyltriethoxysilane, triethoxy-n-octylsilane, octadecyltrimethoxysilane, trimethoxy(propyl)silane, trimethoxy-n-octylsilane, triethoxy(propyl)silane, methane, ethane, propane, butane, pentane, hexane, heptane, octane, nonane, decane, undecane, dodecane, pentadecane, hexadecane, any combination of the foregoing, or the like. In some embodiments, the function group may include a hydrophobic interfacial property that repels dielectric material, thereby preventing dielectric material from adhering to the blocking layer328, in a later dielectric on metal (DoM) process. In some embodiments, the function group may include a methyl group, which provides the hydrophobic interfacial property. In some embodiments, the blocking layer328may be formed by a wet process, such as dip coating, spin coating, spraying coating, or other suitable processes.

As shown inFIG.3Hand operation516inFIG.5, a dielectric layer330is formed on the capping layer324. In some embodiments, the dielectric layer330may include metal oxide, metal nitride, or other suitable materials. In some embodiments, the dielectric layer330may be formed by thermal ALD, or other suitable processes. In some embodiments, the dielectric layer330may be formed by DoM selective deposition. As described above, because of the function group of the blocking layer328prevents dielectric material from adhering to the blocking layer328. The dielectric layer330is formed only on the capping layer324. In some embodiments, the dielectric layer330may prevent damage to the below layers, such as the capping layer324, the first conductive feature322, and the second conductive feature326, during subsequent processing steps.

As shown inFIG.31, the blocking layer328is removed and an ESL332is conformally formed over the dielectric layer312, the liner layer318, the barrier layer320, and the dielectric layer330. In some embodiments, the ESL332may be formed by PVD, CVD, PECVD, ALD, plasma enhanced ALD (PEALD), or other suitable processes. In some embodiments, the ESL332may include silicon oxycarbide, silicon carbon nitride, silicon nitride, silicon carbon oxynitride, silicon dioxide, silicon carbide, silicon oxynitride, aluminum nitride, aluminum oxynitride, aluminum oxide, another dielectric material, or other suitable materials. In some embodiments, the ESL332may have a thickness between 5 Angstroms and 200 Angstroms. Then, as shown inFIG.3J, a portion of the ESL332is removed to expose portions of the dielectric layer312.

As shown inFIG.3K, a third opening334is formed in the dielectric layer312between the first conductive feature322and the second conductive feature326. In some embodiments, an etch operation is performed on the ESL332, the dielectric layer312, the liner layer318, the barrier layer320, and the dielectric layer330. In some embodiments, the etch operation may include dry etch, wet etch, or other suitable processes. Because the sidewalls of the barrier layer320are covered and protected by the liner layer318, the liner layer318can prevent the damage on sidewalls of the barrier layer320during the etch operation.

As shown inFIG.3L, a dielectric layer336is formed over the third opening334and an air gap338is formed between the first conductive feature322and the second conductive feature326in the dielectric layer336. In some embodiment, the dielectric layer336may partially fill the third opening334resulting the air gaps338. In some embodiments, the dielectric layer336may be the same material as the dielectric layer312. In some embodiments, the dielectric layer336may include or be made of porous SiCOH, dense SiCOH, boron nitride (BN), boron carbide (BC), or other suitable materials. In some embodiments, the dielectric layer336may formed by PECVD, ALD, PVD, or other suitable processes.

In some embodiments, for forming the air gap338in the dielectric layer336, a non-conformal deposition process may be performed to form the dielectric layer336in the third opening334during operation516. For example, the PECVD process may be performed to form the dielectric layer336in the third opening334and form the air gap338in the dielectric layer336. In some embodiments, because of the deposition process is non-conformal, the air gap338may be triangle shaped or like triangle shaped, as shown in FIG.3L. As shown inFIG.3L, the air gap338is wider near a lower portion of the third opening334and narrower near an upper portion of the third opening334. In some embodiments, the air gap338is defined by the dielectric layer336and the dielectric layer312.

In some embodiments, the air gap338may reduce an effective dielectric constant of the dielectric layer336. In some embodiments, the effective dielectric constant of the dielectric layer336may be reduced to a range between 2 and 3.6. By reducing the effective dielectric constant of the dielectric layer336, the capacitance between the first conductive feature322and the second conductive feature326is reduced, and thereby the performance of the semiconductor structure300may be increased.

FIGS.4A-4Gare cross-sectional side views of various stages of manufacturing another semiconductor structure400, including an interconnection structure401, in accordance with some embodiments. In some embodiments, the interconnection structure401may be formed on or below the semiconductor device structure100.FIG.6is a flow chart of a method600for manufacturing the interconnection structure401in accordance with some embodiments. For the purpose of better describing the present disclosure, the cross-sectional side view of the semiconductor structure400inFIGS.4A-4Gand the method600inFIG.6will be discussed together. It is understood that the operations shown in the method600are not exhaustive and that other operations may be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown inFIGS.4A-4GandFIG.6.

As shown inFIG.4A, the structure and manufacturing process of the semiconductor structure400are similar to those of the semiconductor structure300inFIG.3D. In other words, the operations602,604,606, and608in the method600may be similar to the operations502,504,506, and508in the method500. However, as shown inFIG.4Aand operation610inFIG.6, after removing a portion of the liner layer318that covers the conductive layer308, a blocking layer402is formed at the bottom of the second opening316on the exposed conductive layer308.

In some embodiments, the blocking layer402is formed by molecules with sulfur (S) or phosphorus (P) function groups. For example, the blocking layer402may include a head group connected to a function group by way of a molecular chain. In some embodiments, the head group has a high affinity to the metal surface (e.g., the exposed conductive layer308), and thus adhere and/or anchor to the exposed conductive layer308rather than the liner layer318.

As shown inFIG.4Band operation612inFIG.6, a barrier layer404is formed over the liner layer318but not on the blocking layer402. In some embodiments, since the blocking layer402is formed by molecules with S or P function groups, the S or P function group may repel the deposition of the barrier layer404on the blocking layer402. In some embodiments, the barrier layer404may include TaN, TiN, or other suitable materials. In some embodiments, the barrier layer404may have a thickness between 10 Angstroms and 30 Angstroms. In some embodiments, the barrier layer404may be formed by thermal ALD, or other suitable processes.

As shown inFIG.4Cand operation614inFIG.6, the blocking layer402is removed. Then, as shown in operation616inFIG.6, a first conductive feature406, a second conductive feature408, and a capping layer410are formed in the first opening314and the second opening316over the barrier layer404. In some embodiments, the materials and the manufacturing processes of the first conductive feature406, the second conductive feature408, and the capping layer410may be similar to the materials and the manufacturing processes of the first conductive feature322, the second conductive feature326, and the capping layer324. Because the blocking layer402prevents the formation of the barrier layer404at the bottom of the second opening316, after forming the second conductive feature408, the second conductive feature408can in direct contact with the conductive layer308. Therefore, the resistance between the via structure (the second conductive feature408) and the conductive layer308may be reduced.

As shown inFIG.4D, a dielectric layer412is formed on the capping layer410. An ESL414is formed over the dielectric layer312, the liner layer318, the barrier layer404, and the dielectric layer412. A dielectric layer416is formed and an air gap418is formed between the first conductive feature406and the second conductive feature408in the dielectric layer416. In some embodiments, the materials and the manufacturing processes of the dielectric layer412, the ESL414, the dielectric layer416, and the air gap418may be similar to the materials and the manufacturing processes of the dielectric layer330, the ESL332, the dielectric layer336, and the air gap338shown inFIGS.3F-3L.

The air gap418may reduce an effective dielectric constant of the dielectric layer416. In some embodiments, the effective dielectric constant of the dielectric layer416may be reduced to a range between 2 and 3.6. By reducing the effective dielectric constant of the dielectric layer416, the capacitance between the first conductive feature406and the second conductive feature408is reduced, and thereby the performance of the semiconductor structure400may be increased.

In addition, the liner layer318may prevent the damage at the sidewalls of the barrier layer404, or the first conductive feature406and the second conductive feature408, during the etch process of forming the opening between the first conductive feature406and the second conductive feature408. The dielectric layer412may prevent top side damage of the first conductive feature406and the second conductive feature408during the etch process of forming the opening between the first conductive feature406and the second conductive feature408.

Furthermore, in the semiconductor structure400, because the blocking layer402prevents the formation of the barrier layer404at the bottom of the second opening316, the second conductive feature408can in direct contact with the conductive layer308. Therefore, the resistance of the via structure may be reduced. The resistance-capacitance (RC) delay of the semiconductor structure may be further reduced.

FIG.4Eillustrates an example of the semiconductor structure400. In some embodiments, the semiconductor structure400may include the semiconductor substrate302. The device304, such as a transistor shown inFIG.4E, may be formed on the semiconductor substrate302. The MEOL306may include one or more than one conductive structure, such as one or more than one conductive layer and via, in contact with the terminals of the device304. The interconnection structure401is formed on the MEOL306.

FIG.4Fillustrates another example of the semiconductor structure400. A conductive feature450may be formed above the interconnection structure401and in electric contact with the second conductive feature408.FIG.4Fillustrates a further example of the semiconductor structure400. Another interconnection structure452may be further formed on the interconnection structure401. Furthermore, the interconnection structure452may include the air gap, or without the air gap as shown inFIG.4G.

FIG.4His schematic cross-sectional side view of the semiconductor device structure100in accordance with some embodiments. The semiconductor device structure100may include the device layer102formed on and in the substrate302and an interconnection structure460formed over the device layer102. The interconnection structure460includes various conductive features, such as a first plurality of conductive features464and second plurality of conductive features466, and an intermetal dielectric (IMD) layer462to separate and isolate various conductive features464,466. In some embodiments, the first plurality of conductive features464are conductive lines and the second plurality of conductive features466are conductive vias. The interconnection structure460includes multiple levels of the conductive features464, and the conductive features464are arranged in each level to provide electrical paths to various devices layer102disposed below. The conductive features466provide vertical electrical routing from the device layer200to the conductive features464and between conductive features464. For example, the bottom-most conductive features466of the interconnection structure460may be electrically connected to the conductive contacts disposed over the S/D regions104(FIG.2A) and the gate electrode layer110(FIG.1B). The conductive features464and conductive features466may be made from one or more electrically conductive materials, such as metal, metal alloy, metal nitride, or silicide. For example, the conductive features464and the conductive features466are made from copper, aluminum, aluminum copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, titanium silicon nitride, zirconium, gold, silver, cobalt, nickel, tungsten, tungsten nitride, tungsten silicon nitride, platinum, chromium, molybdenum, hafnium, iridium, other suitable conductive material, or a combination thereof.

The IMD layer462includes one or more dielectric materials to provide isolation functions to various conductive features464,466. The IMD layer462may include multiple dielectric layers embedding multiple levels of conductive features464,466. The IMD layer462is made from a dielectric material, such as SiOx, SiOxCyHz, SiOCN, SiON, or SiOxCy, where x, y and z are integers or non-integers. In some embodiments, the IMD layer462includes a low-k dielectric material having a k value less than that of silicon dioxide.

In some embodiments, the conductive features464disposed in a level of the interconnection structure460are partially overlapping with respect to the x-axis, which is substantially parallel to a major surface of the substrate302, as shown inFIG.4H. A level of the interconnection structure460may be a layer of the IMD layer462. The layers are sometimes referred to as M1, M2, . . . M10, M11, et, with M1 being closest to the device layer102. The air gap418described above may be included in any layers in the interconnection structure460. Pitch of the conductive features464,466increases from a lower portion470to an upper portion472. In some embodiments, air gaps, such as the air gaps418, may be located in one or more metal layers in the lower portion470, for example M1, M2, but not presented in metal layers located in the upper portion472, for example M10, M11. In some embodiments, the top metal layer does not include air gap. The partially overlapping conductive features464are described in detail below. Additional materials, such as glue layers, etch stop layers, and barrier layers, may be included in the interconnection structure460but are not shown inFIG.4Hfor clarity.

An embodiment is an interconnection structure. The interconnection structure includes a first dielectric layer, a first conductive feature, a first liner layer, a second conductive feature, a second liner layer, and an air gap. The first conductive feature is disposed in the first dielectric layer. The first liner layer is disposed between the first conductive feature and the first dielectric layer. The second conductive feature penetrates the first dielectric layer. The second liner layer is disposed between the second conductive feature and the first dielectric layer. The air gap is disposed in the first dielectric layer between the first liner layer and the second liner layer. The first liner layer and the second liner layer include metal oxide, metal nitride, or silicon oxide doped carbide.

Another embodiment is a method for forming an interconnection structure. A first dielectric layer is deposited over a conductive layer. A first opening is formed in the first dielectric layer and a second opening penetrates the first dielectric layer to expose a portion of the conductive layer. A liner layer is formed over the first dielectric layer. A portion of the liner layer is removed to expose the conductive layer under the second opening. A barrier layer is deposited over the liner layer and the exposed conductive layer. A first conductive feature is formed in the first opening and a second conductive feature is formed in the second opening. A blocking layer is deposited on the first dielectric layer. A second dielectric layer is formed on the first conductive feature not covered by the blocking layer and a third dielectric layer is formed on the second conductive feature not covered by the blocking layer.

A further embodiment is a method for forming an interconnection structure. A first dielectric layer is formed over a conductive layer. A first opening is formed in the first dielectric layer and a second opening is formed penetrating the first dielectric layer to expose a portion of the conductive layer. A liner layer is formed over the first dielectric layer. A portion of the liner layer is removed to expose the conductive layer under the second opening. A blocking layer is deposited on the exposed conductive layer at the bottom of the second opening. A barrier layer is formed over the liner layer not covered by the blocking layer. The blocking layer is removed to expose the conductive layer at the bottom of the second opening. A first conductive feature is formed in the first opening over the barrier layer and a second conductive feature is formed in the second opening in direct contact with the conductive layer.