Isolation structures for preventing photons and carriers from reaching active areas and methods of formation

Regions of an integrated circuit are isolated by a structure that includes at least one isolating trench on the periphery of an active area. The trench is deep, extending at least about 0.5 μm into the substrate. The isolating structure prevents photons and electrons originating in peripheral circuitry from reaching the active area. Where the substrate has a heavily-doped lower layer and an upper layer on it, the trench can extend through the upper layer to the lower layer. A thermal oxide can be grown on the trench walls. A liner can also be deposited on the sidewalls of each trench. A fill material having a high-extinction coefficient is then deposited over the liner. The liner can also be light absorbent so that both the liner and fill material block photons.

FIELD OF THE INVENTION

The present invention relates generally to semiconductor devices, and more particularly, to trench isolation technology for isolating semiconductor devices, such as in image sensors.

BACKGROUND OF THE INVENTION

An image sensor generally includes an array of pixel cells, which include photo-conversion devices for converting light incident on the array into electrical signals, and peripheral circuitry, which includes circuitry for controlling devices of the array and circuitry for converting the electrical signals into a digital image.

In integrated circuit (IC) fabrication, it is often necessary to isolate semiconductor devices formed in the substrate. This is true for many types of ICs including, for example, DRAM, flash memory, SRAM, microprocessors, DSP and ASICs. The individual pixels of a Complementary Metal Oxide Semiconductor (CMOS) image sensor IC also need to be isolated from each other and from other devices.

A CMOS image sensor IC includes a focal plane array of pixel cells, each one of the cells including a photogate, photoconductor, or photodiode overlying a charge accumulation region within a substrate for accumulating photo-generated charge. Each pixel cell may include a transistor for transferring charge from the charge accumulation region to a floating diffusion node and a transistor, for resetting the diffusion node to a predetermined charge level prior to charge transfer. The pixel cell may also include a source follower transistor for receiving and amplifying a charge level from the diffusion node and an access transistor for controlling the readout of the cell contents from the source follower transistor.

In a CMOS image sensor, the active elements of a pixel cell perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) transfer of charge to the floating diffusion node accompanied by charge amplification; (4) resetting the floating diffusion node to a known state before the transfer of charge to it; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing pixel charge from the floating diffusion node. Photo charge may be amplified when it moves from the initial charge accumulation region to the floating diffusion node. The charge at the floating diffusion node is typically converted to a pixel output voltage by a source follower output transistor. The photosensitive element of a CMOS image sensor pixel is typically either a depleted p-n junction photodiode or a field induced depletion region beneath a photogate. A photon impinging on a particular pixel of a photosensitive device may diffuse to an adjacent pixel, resulting in detection of the photon by the wrong pixel, i.e. cross-talk. Therefore, CMOS image sensor pixels must be isolated from one another to avoid pixel cross talk. In the case of CMOS image sensors, which are intentionally fabricated to be sensitive to light, it is advantageous to provide both electrical and optical isolation between pixels.

CMOS image sensors of the type discussed above are generally known as discussed, for example, in Nixon et al., “256.times.256 CMOS Active Pixel Sensor Camera-on-a-Chip,” IEEE Journal of Solid-State Circuits, Vol. 31(12), pp. 2046–2050 (1996); and Mendis et al., “CMOS Active Pixel Image Sensors,” IEEE Transactions on Electron Devices, Vol. 41(3), pp. 452–453 (1994). See also U.S. Pat. Nos. 6,177,333 and 6,204,524, which describe operation of conventional CMOS image sensors, the contents of which are incorporated herein by reference.

FIG. 1is a block diagram of a typical CMOS image sensor IC100with circuitry formed at a surface of a substrate101. Image sensor100includes an array of pixel cells111. The pixel cells (not shown) are arranged in columns and rows. Each pixel cell includes a photo-conversion device. As is known in the art, a pixel cell functions by receiving photons of light and converting those photons into charge carried by, for example, electrons. In order to produce an accurate and higher quality image, a photo-conversion device of a pixel cell should receive only photons from an imaged scene. Further, a pixel cell should not receive electrons that do not result from photoconversion.

After pixel cells of array111generate charge in response to incident light, electrical signals indicating charge levels are read out and processed by circuitry peripheral to array111. Peripheral circuitry of image sensor100typically includes row select circuitry and column select circuitry (not shown) for activating particular rows and columns of array111. Image sensor100also includes analog signal processing circuitry112, analog-to-digital conversion circuitry113, and digital logic circuitry114. Circuitry112,113, and114can be on a same chip101as array111, as shown inFIG. 1, or on a different chip. The analog signal processing circuitry112samples data from array111and analog-to-digital conversion circuitry113converts the analog signals sampled by circuitry112into digital signals. Digital logic circuitry114processes the digital signals to output a digital image representative of the light incident on array111.

During operation, the peripheral circuitry, especially analog-to-digital conversion circuitry113, generates photons and charge carriers, e.g. electrons. Most photons generated by peripheral circuitry are in the red to near infrared region. As these photons have a long wavelength, they are able to travel far in the substrate101. If the peripheral circuitry is on the same chip101as array111, photons and electrons generated by the peripheral circuitry can travel to and interfere with pixel cells of array111, especially those pixel cells on the edges of array111adjacent to the peripheral circuitry.

FIG. 2is an image120sensed under dark conditions by an IC similar to image sensor100, discussed above in connection withFIG. 1. Typically, image sensor100includes a Bayer pattern color filter array such that image sensor100includes one subset of pixel cells for receiving blue light, one subset for receiving red light, and two subsets for receiving green light. Each quadrant121,122,123,124of the image120shows light intensity sensed by a respective one of the four subsets of pixel cells. As shown inFIG. 2, the pixel cells near the edges of the array111will appear brighter than the pixel cells in the middle of array111because of interference by photons and electrons from the peripheral circuitry.

One method to reduce interference provides, around the array111, a doped layer115(FIG. 1) in substrate101, typically a highly doped p-type layer. Layer115, however, still allows a majority of electrons to pass through. Additionally, at a typical width of 6 μm, few of the long wavelength (red and infrared) photons generated by the peripheral circuitry will be absorbed by layer115.

Accordingly, it would be advantageous to have improved techniques for isolating an array of pixel cells from peripheral circuitry.

BRIEF SUMMARY OF THE INVENTION

An exemplary embodiment of the invention provides a structure for isolating a pixel array of an image sensor IC from peripheral circuitry. The structure includes a deep trench formed around at least part of the perimeter of the array. In one embodiment, the trench extends through an epitaxial layer of substrate to a P+ layer. A thermal oxide is grown inside the trench to inhibit reaction between the substrate and trench fill material. The trench may be partially or completely filled with one or more layers of a high extinction coefficient material to attenuate or absorb photons generated in the periphery. The layers may include a liner and a fill layer, for example.

In another embodiment, an isolating structure includes several parallel trenches, with or without fill material.

These and other features and advantages of the invention will be more apparent from the following detailed description that is provided in connection with the accompanying drawings that illustrate exemplary embodiments of the invention.

DETAILED DESCRIPTION OF THE INVENTION

The terms “wafer” and “substrate” are to be understood as including silicon, silicon-on-insulator (SOI), or silicon-on-sapphire (SOS) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. Furthermore, when reference is made to a “wafer” or “substrate” in the following description, previous process steps may have been utilized to form regions or junctions in the base semiconductor structure or foundation. In addition, the semiconductor need not be silicon-based, but could be based on silicon-germanium, germanium, or gallium-arsenide.

The term “pixel” refers to a picture element unit cell containing a photo-conversion device and other devices for converting electromagnetic radiation to an electrical signal or for converting electrical signals to electromagnetic radiation. The term “peripheral circuitry” refers to the circuitry of an image sensor that is peripheral to an array of pixel cells.

Embodiments of the present invention provide trench isolation techniques for isolating an array of pixel cells from peripheral circuitry. The trenches are deep, extending to a depth of at least about 0.5 micrometers (μm). In exemplary embodiments, a trench is filled with a material that inhibits or prevents photons and electrons generated by the peripheral circuitry from interfering with pixel cells of an array. As a result, interference as inFIG. 2is reduced. Also, truer dark calibration is possible.

To better illustrate these techniques, a description of an exemplary CMOS image sensor is described below with reference toFIGS. 3–6. It should be noted, however, that the invention is not limited to CMOS image sensors and may be used in any suitable device, for example, a Charge Coupled Device (CCD) image sensor, DRAM, flash memory, SRAM, microprocessor, DSP or ASIC.

FIG. 3is a block diagram of an image sensor IC300according to an exemplary embodiment of the invention. Image sensor300is formed at a surface of a substrate301and includes an array333of pixel cells which may be referred to as an active area of the substrate301. Adjacent to the array333is peripheral circuitry, including row select circuitry and column select circuitry (not shown). Illustratively, the peripheral circuitry also includes analog signal processing circuitry312, analog-to-digital conversion circuitry313, and digital logic circuitry314. An isolation trench340is also provided in substrate301.

At least part of the trench340is located between the array and the peripheral circuitry. Illustratively, trench340extends around the perimeter of array333. However, trench340may alternatively extend only around the part of the perimeter that is between the array and the peripheral circuitry. Further, trench340may alternatively extend only around the part of the perimeter that is between the array and that portion of the peripheral circuitry that will interfere most with the pixel cells of the array. For example, trench340may extend only around the part of the perimeter that is between the array and analog-to-digital conversion circuitry313.

FIG. 4is a cross sectional diagram of trench340taken along line4–4′ shown inFIG. 3. Illustratively, substrate301includes an epitaxial layer303of a first conductivity type, e.g. p-type, which is over a base layer302, that is heavily doped to the first conductivity type, i.e., p-type. Layers302and303can both be silicon or other suitable semiconductor material. Trench340has a depth, D, and D is illustratively great enough that trench340contacts base layer302. Trench340may instead have a smaller depth and not contact base layer302, provided that trench340is sufficiently deep to prevent photons or charge carriers from reaching array333. Illustratively, trench340has a depth between approximately 4 micrometers (μm) to approximately 6 μm. The width W at the top of trench340may vary, with 6 μm being an exemplary width. Also, the width W at the top of trench340can be greater than the width at the bottom, so that trench340tapers as it extends into substrate301.

Isolation trench340is filled with at least one material that serves to prevent photons and electrons generated by the peripheral circuitry from interfering with pixel cells of the array333. As shown inFIG. 4, trench340is lined with material341, a high absorption material, and filled or partially filled with material342, which can be a high extinction coefficient material that attenuates light by absorbing photons. In addition, a thermal oxide (not shown) could be grown in trench340prior to deposition of material341, providing an additional barrier to electrons. Other trench fill configurations, however, are possible and are described below in more detail.

When photons and electrons are generated by the peripheral circuitry, they can travel from the peripheral circuitry toward the array333. Upon encountering trench340and the materials341,342therein, at least a portion of the photons and electrons are prevented from passing through trench340to reach array333.

The fabrication of the trench340of image sensor300is described below in connection withFIGS. 5A–5C. No particular order is required for any of the actions described herein, except for those logically requiring the results of prior actions. Accordingly, while the actions below are described as being performed in a general order, the order is exemplary only and may be altered.

Illustratively, trench340is formed prior to the formation of devices of the array and peripheral circuitry. As shown inFIG. 5A, a trench340is formed in epitaxial layer303, which is above base layer302. Trench340is formed having a depth such that trench340contacts base layer302. Trench340can be formed by techniques known in the art, such as an anisotropic etch through a mask (not shown) photolithographically formed on substrate301and having openings where trench340is to be formed.

Referring toFIG. 5B, an optional liner341is formed on the sidewalls and bottom of trench340. Illustratively, liner341is formed of, for example, a thin layer of high absorption material that could be deposited through the same mask used to form trench340. Exemplary high absorption materials include nitrides and amorphous carbons, such as B-doped carbon. In an exemplary embodiment, a thin layer of thermal oxide may be grown inside the trench340, prior to the deposition of liner341, to prevent reaction between the substrate silicon and the trench fill material. The thermal oxide material also acts as a physical barrier for carriers; an electron would require 3.2 eV to cross through the thermal oxide. Accordingly, the thermal oxide would help to isolate the array from peripheral noise. Since the trench is etched through to the P+ layer302, electrons crossing under the thermal oxide would have a tendency to quickly recombine; if layer302has a B concentration of ˜2E18, for example, the electron diffusion length would be only 1.1 μm.

As illustrated inFIG. 5C, trench340is then filled with material342. Illustratively, material342is a light attenuating material that prevents at least a portion of photons from the peripheral circuitry from entering the array333and also a material that prevents electrons from entering array333. Material342can be, for example, doped or undoped polysilicon or amorphous boron-doped carbon. If a high absorption material is used for optional liner341, the trench340could instead be filled with oxide or some other material that is easily planarized. Alternatively, the trench340could just include a thermal oxide and high absorption material342without liner341. A high extinction coefficient fill material attenuates or blocks photons generated in the periphery preventing them from being absorbed by photodiodes in the array. The fill material342could also be tied to ground through a connection344to prevent charge buildup.

For example, Table 1 below illustrates the percentage of light that is blocked when a thin film (of about 1000 Angstroms) of amorphous B-doped carbon is used as a liner compared to the percentage of light that is amorphous B-doped carbon is a used to completely fill the trench of about 6000 Angstroms).

Trench340can also be filled with more than two materials. For example,FIG. 6depicts trench340containing three materials643,644, and645. Materials643,644, and645have different refractive indices. Based on the refractive indices of materials643,644, and645, the layering structure of materials643,644, and645is configured such that photons entering the trench from peripheral circuitry (FIG. 3) will be reflected away from array333. Illustratively, material643has a greater refractive index than material644, which in turn has a greater refractive index than material645.

Conventional processing methods may be used to complete the image sensor IC300. For example, devices of the array333and of the peripheral circuitry can be formed. Insulating, shielding, and metallization layers can then be formed and gate lines and other connections to the array333may be formed. Conventional layers of conductors and insulators may also be used to interconnect the structures and to connect pixel cells of array300to peripheral circuitry.

An exemplary CMOS image sensor in accordance with the invention and having a pinned photodiode421as part of array333(FIG. 3) is shown inFIG. 7. The pinned photodiode421has a p-type surface layer424and an n-type photodiode region426within a p-type active layer420. A junction is formed around the entirety of the n-type region426. An impurity doped floating diffusion region422, preferably having n-type conductivity, is provided on one side of the channel region of transfer gate460, the other side of which has a portion of n-type region426. A trench isolation region340is formed adjacent to but spaced from n-type region421, to isolate the structures formed in the active layer420from peripheral circuitry444. An electrical connection region423for providing hole accumulation is formed adjacent the sidewalls of the trench isolation region340. The trench isolation region340is formed as described above with respect toFIGS. 4–6.

The gate stacks, for example transfer gate460, may be formed before or after the trench is etched. The order of these preliminary process steps may be varied as is required or convenient for a particular process flow, for example, if a photogate sensor which overlaps the transfer gate is desired, the gate stacks must be formed before the photogate, but if a non-overlapping photogate is desired, the gate stacks may be formed after photogate formation.

A translucent or transparent insulating layer430is formed over the CMOS image sensor400. Conventional processing methods are then carried out to form for example, contacts (not shown) in the insulating layer430to provide an electrical connection to the source/drain regions, the floating diffusion region422, and other wiring to connect gate lines and other connections in the sensor400. For example, the entire surface may then be covered with a passivation layer, of e.g., silicon dioxide, BSG, PSG, or BPSG, which is CMP planarized and etched to provide contact holes, which are then metallized to provide contacts to the photogate (if used), reset gate, and transfer gate.

An integrated circuit with a pixel array and an isolation trench as described with reference toFIGS. 4–6, may be further processed using techniques known in the art or other suitable techniques to arrive at a CMOS image sensor IC.

Under an alternate embodiment, multiple, substantially parallel trenches may be used in place of the single trench configuration shown inFIGS. 4–6. This embodiment improves blocking of red and infrared photons.FIG. 8illustrates a cross-sectional diagram of a 4-trench configuration. Substrate301includes an epitaxial layer303of a first conductivity type, e.g. p-type, which is over a base layer302, which is heavily doped to the first conductivity type. Trenches340A–D all have a depth D such that each trench contacts base layer302. Trenches340A–D may instead have smaller depths and not all contact layer302, provided that trenches340A–D are sufficiently deep to prevent photons or charge carriers from reaching array333. Illustratively, trenches340A–D have a depth between approximately 4 micrometers (μm) and approximately 6 μm. The widths W1–W4of trenches340A–D are each approximately 1 μm, with 500 nm of crystal silicon between adjacent trenches. It should be understood that, while a 4-trench configuration is illustrated, any number of trenches may be utilized to achieve the desired effect.

In addition to a thermal oxide as described above, isolation trenches340A–D contain at least one material that serves to prevent photons generated by the peripheral circuitry from interfering with pixel cells of the array333. As shown in the exemplary embodiment atFIG. 8, each trench340A–D is respectively lined with a material341A–D, a high absorption, light attenuating film, such as nitride or amorphous carbon. By lining the trenches with the film, the use of filler material becomes optional. Alternately, each trench340A–D may nevertheless be respectively filled, or partially filled, with material342A–D, which is also a high extinction coefficient material. Other trench fill configurations, however, are possible. In one embodiment, filler material342A–D is omitted during fabrication. Also, in a multiple trench configuration, the liner material341A–D may be omitted if the unlined trenches provide adequate protection from electrons and photons emitted by peripheral circuitry.

Table 2 below compares the amount of red and infrared light that passes through a single large trench compared to multiple smaller trenches (in the examples below, through 4 smaller trenches). Each trench set up uses a total of about 6 μm of space, and is about 4 μm deep. The smaller trenches are about 1 μm wide with about 500 nm of crystal silicon between them.

When photons and electrons are generated by the peripheral circuitry, they can travel from the peripheral circuitry toward the array333. Each interface they encounter results in some reflection, especially for photons, and absorption, especially for electrons. By using multiple trenches, the number of interfaces is increased, and light reflection and electron absorption is also increased. When liners are used, each additional trench will add two additional layers of liner for photons and electrons to pass through, causing further absorption and reflection.

FIG. 9is a block diagram of a processor based system600, which includes an image sensor642. Processor based system600is exemplary of a system having digital circuits, which could include an image sensor. Without being limiting, such a system could include a computer system, camera system, scanner, machine vision, vehicle navigation, video phone, surveillance system, auto focus system, star tracker system, motion detection system, image stabilization system and data compression system for high-definition television, all of which can utilize the present invention.

Processor based system600, such as a computer system, for example generally comprises a central processing unit (CPU)644, for example, a microprocessor, which communicates with an input/output (I/O) device646over a bus652. The image sensor642which includes an IC with a single or multiple isolation trench configuration as inFIGS. 3–6or8, also communicates with CPU644the system over bus652. The computer system600also includes random access memory (RAM)648, and, in the case of a computer system may include peripheral devices such as a flash memory card654, or a compact disk (CD) ROM drive656which also communicate with CPU644over the bus652. It may also be desirable to integrate the processor644, image sensor642and memory648on a single IC chip.

Although the above embodiments have been described above with reference to the formation of trenches formed around at least a part of the perimeter of the array and having a particular shape, it must be understood that the invention is not limited to the formation of trenches. Accordingly, the present invention has applicability to other isolation structures having various shapes and geometries, in accordance with design specifications and as desired. Thus, for example, the trenches need not have the trapezoidal cross-section shown above inFIGS. 4–8, and the trenches may have a rectangular or triangular cross-section or other desired cross-section. In addition, the isolation structures need not be trenches, as they may include any structure that is formed around at least a part of the perimeter of the array and that isolates the array from the periphery.

The above description and drawings are only to be considered illustrative of exemplary embodiments, that achieve the features and advantages of the invention. Modification and substitutions to specific process conditions and structures can be made without departing from the spirit and scope of the invention. While the above embodiments are described in connection with CMOS and CCD image sensor ICs, the invention is not limited to these embodiments. Accordingly, the invention is not to be considered as being limited by the foregoing description and drawings, but is only limited by the scope of the appended claims.