Semiconductor device and method of forming insulating layer in notches around conductive TSV for stress relief

A semiconductor device has a plurality of conductive vias formed into a semiconductor wafer. A portion of the semiconductor wafer is removed so the conductive vias extend above a surface of the semiconductor wafer. A notch is formed in the semiconductor wafer around each of the conductive vias. The notch around the conductive vias can be formed by wet etching, dry etching, or LDA. A first insulating layer is formed over a surface of the semiconductor wafer and conductive vias and into the notch to provide stress relief between the conductive vias and semiconductor wafer. A portion of the first insulating layer is removed to expose the conductive vias. A first conductive layer and second insulating layer can be formed around the conductive vias. A second conductive layer can be formed over the conductive vias. The notch can extend into the second insulating layer.

FIELD OF THE INVENTION

The present invention relates in general to semiconductor devices and, more particularly, to a semiconductor device and method of forming an insulating layer in notches around conductive TSV for stress relief.

BACKGROUND OF THE INVENTION

Semiconductor devices are generally manufactured using two complex manufacturing processes, i.e., front-end manufacturing, and back-end manufacturing, each involving potentially hundreds of steps. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each semiconductor die is typically identical and contains circuits formed by electrically connecting active and passive components. Back-end manufacturing involves singulating individual semiconductor die from the finished wafer and packaging the die to provide structural support and environmental isolation. The term “semiconductor die” as used herein refers to both the singular and plural form of the words, and accordingly can refer to both a single semiconductor device and multiple semiconductor devices.

One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products. A smaller semiconductor die size can be achieved by improvements in the front-end process resulting in semiconductor die with smaller, higher density active and passive components. Back-end processes may result in semiconductor device packages with a smaller footprint by improvements in electrical interconnection and packaging materials.

A conventional semiconductor wafer may contain conductive through silicon vias (TSV). A plurality of vias is formed through the semiconductor wafer. The vias are filled with conductive material to form the conductive TSV. The conductive TSV are susceptible to stress due to mismatches in the coefficient of thermal expansion (CTE), particular at the junction between the conductive TSV and base material of the semiconductor wafer. The stress can cause cracking, degraded electrical performance, and other defects in the semiconductor wafer.

SUMMARY OF THE INVENTION

A need exists to reduce stress between conductive TSV and the base material of the semiconductor wafer. Accordingly, in one embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a semiconductor wafer, forming a plurality of conductive vias into the semiconductor wafer, removing a first portion of the semiconductor wafer so the conductive vias extend above a surface of the semiconductor wafer, forming a notch in the semiconductor wafer around each of the conductive vias, forming an insulating layer over the surface of the semiconductor wafer and conductive vias and into the notch to provide stress relief between the conductive vias and semiconductor wafer, and removing a portion of the insulating layer to expose the conductive vias.

In another embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a semiconductor die having a conductive via formed through the semiconductor die, forming a notch in the semiconductor die around the conductive via, forming an insulating layer over a surface of the semiconductor die and conductive via and into the notch, and removing a portion of the insulating layer to expose the conductive via.

In another embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a semiconductor die having a conductive via formed through the semiconductor die, forming a notch in the semiconductor die around the conductive via, and forming an insulating layer over a surface of the semiconductor die and conductive via and into the notch.

In another embodiment, the present invention is a semiconductor device comprising a semiconductor die having a conductive via formed through the semiconductor die. A notch is formed in the semiconductor die around the conductive via. An insulating layer is formed over a surface of the semiconductor die and into the notch.

DETAILED DESCRIPTION OF THE DRAWINGS

The layers can be patterned using photolithography, which involves the deposition of light sensitive material, e.g., photoresist, over the layer to be patterned. A pattern is transferred from a photomask to the photoresist using light. In one embodiment, the portion of the photoresist pattern subjected to light is removed using a solvent, exposing portions of the underlying layer to be patterned. In another embodiment, the portion of the photoresist pattern not subjected to light, i.e., the negative photoresist, is removed using a solvent, exposing portions of the underlying layer to be patterned. The remainder of the photoresist is removed, leaving behind a patterned layer. Alternatively, some types of materials are patterned by directly depositing the material into the areas or voids formed by a previous deposition/etch process using techniques such as electroless and electrolytic plating.

Patterning is the basic operation by which portions of the top layers on the semiconductor wafer surface are removed. Portions of the semiconductor wafer can be removed using photolithography, photomasking, masking, oxide or metal removal, photography and stenciling, and microlithography. Photolithography includes forming a pattern in reticles or a photomask and transferring the pattern into the surface layers of the semiconductor wafer. Photolithography forms the horizontal dimensions of active and passive components on the surface of the semiconductor wafer in a two-step process. First, the pattern on the reticle or masks is transferred into a layer of photoresist. Photoresist is a light-sensitive material that undergoes changes in structure and properties when exposed to light. The process of changing the structure and properties of the photoresist occurs as either negative-acting photoresist or positive-acting photoresist. Second, the photoresist layer is transferred into the wafer surface. The transfer occurs when etching removes the portion of the top layers of semiconductor wafer not covered by the photoresist. The chemistry of photoresists is such that the photoresist remains substantially intact and resists removal by chemical etching solutions while the portion of the top layers of the semiconductor wafer not covered by the photoresist is removed. The process of forming, exposing, and removing the photoresist, as well as the process of removing a portion of the semiconductor wafer can be modified according to the particular resist used and the desired results.

In negative-acting photoresists, photoresist is exposed to light and is changed from a soluble condition to an insoluble condition in a process known as polymerization. In polymerization, unpolymerized material is exposed to a light or energy source and polymers form a cross-linked material that is etch-resistant. In most negative resists, the polymers are polyisopremes. Removing the soluble portions (i.e. the portions not exposed to light) with chemical solvents or developers leaves a hole in the resist layer that corresponds to the opaque pattern on the reticle. A mask whose pattern exists in the opaque regions is called a clear-field mask.

In positive-acting photoresists, photoresist is exposed to light and is changed from relatively nonsoluble condition to much more soluble condition in a process known as photosolubilization. In photosolubilization, the relatively insoluble resist is exposed to the proper light energy and is converted to a more soluble state. The photosolubilized part of the resist can be removed by a solvent in the development process. The basic positive photoresist polymer is the phenol-formaldehyde polymer, also called the phenol-formaldehyde novolak resin. Removing the soluble portions (i.e. the portions exposed to light) with chemical solvents or developers leaves a hole in the resist layer that corresponds to the transparent pattern on the reticle. A mask whose pattern exists in the transparent regions is called a dark-field mask.

After removal of the top portion of the semiconductor wafer not covered by the photoresist, the remainder of the photoresist is removed, leaving behind a patterned layer. Alternatively, some types of materials are patterned by directly depositing the material into the areas or voids formed by a previous deposition/etch process using techniques such as electroless and electrolytic plating.

FIG. 1illustrates electronic device50having a chip carrier substrate or printed circuit board (PCB)52with a plurality of semiconductor packages mounted on its surface. Electronic device50can have one type of semiconductor package, or multiple types of semiconductor packages, depending on the application. The different types of semiconductor packages are shown inFIG. 1for purposes of illustration.

Electronic device50can be a stand-alone system that uses the semiconductor packages to perform one or more electrical functions. Alternatively, electronic device50can be a subcomponent of a larger system. For example, electronic device50can be part of a cellular phone, personal digital assistant (PDA), digital video camera (DVC), or other electronic communication device. Alternatively, electronic device50can be a graphics card, network interface card, or other signal processing card that can be inserted into a computer. The semiconductor package can include microprocessors, memories, application specific integrated circuits (ASIC), logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor die or electrical components. Miniaturization and weight reduction are essential for these products to be accepted by the market. The distance between semiconductor devices must be decreased to achieve higher density.

For the purpose of illustration, several types of first level packaging, including bond wire package56and flipchip58, are shown on PCB52. Additionally, several types of second level packaging, including ball grid array (BGA)60, bump chip carrier (BCC)62, dual in-line package (DIP)64, land grid array (LGA)66, multi-chip module (MCM)68, quad flat non-leaded package (QFN)70, and quad flat package72, are shown mounted on PCB52. Depending upon the system requirements, any combination of semiconductor packages, configured with any combination of first and second level packaging styles, as well as other electronic components, can be connected to PCB52. In some embodiments, electronic device50includes a single attached semiconductor package, while other embodiments call for multiple interconnected packages. By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate pre-made components into electronic devices and systems. Because the semiconductor packages include sophisticated functionality, electronic devices can be manufactured using less expensive components and a streamlined manufacturing process. The resulting devices are less likely to fail and less expensive to manufacture resulting in a lower cost for consumers.

FIGS. 2a-2cshow exemplary semiconductor packages.FIG. 2aillustrates further detail of DIP64mounted on PCB52. Semiconductor die74includes an active region containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and are electrically interconnected according to the electrical design of the die. For example, the circuit can include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements formed within the active region of semiconductor die74. Contact pads76are one or more layers of conductive material, such as aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), or silver (Ag), and are electrically connected to the circuit elements formed within semiconductor die74. During assembly of DIP64, semiconductor die74is mounted to an intermediate carrier78using a gold-silicon eutectic layer or adhesive material such as thermal epoxy or epoxy resin. The package body includes an insulative packaging material such as polymer or ceramic. Conductor leads80and bond wires82provide electrical interconnect between semiconductor die74and PCB52. Encapsulant84is deposited over the package for environmental protection by preventing moisture and particles from entering the package and contaminating semiconductor die74or bond wires82.

FIG. 2billustrates further detail of BCC62mounted on PCB52. Semiconductor die88is mounted over carrier90using an underfill or epoxy-resin adhesive material92. Bond wires94provide first level packaging interconnect between contact pads96and98. Molding compound or encapsulant100is deposited over semiconductor die88and bond wires94to provide physical support and electrical isolation for the device. Contact pads102are formed over a surface of PCB52using a suitable metal deposition process such as electrolytic plating or electroless plating to prevent oxidation. Contact pads102are electrically connected to one or more conductive signal traces54in PCB52. Bumps104are formed between contact pads98of BCC62and contact pads102of PCB52.

InFIG. 2c, semiconductor die58is mounted face down to intermediate carrier106with a flipchip style first level packaging. Active region108of semiconductor die58contains analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed according to the electrical design of the die. For example, the circuit can include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements within active region108. Semiconductor die58is electrically and mechanically connected to carrier106through bumps110.

BGA60is electrically and mechanically connected to PCB52with a BGA style second level packaging using bumps112. Semiconductor die58is electrically connected to conductive signal traces54in PCB52through bumps110, signal lines114, and bumps112. A molding compound or encapsulant116is deposited over semiconductor die58and carrier106to provide physical support and electrical isolation for the device. The flipchip semiconductor device provides a short electrical conduction path from the active devices on semiconductor die58to conduction tracks on PCB52in order to reduce signal propagation distance, lower capacitance, and improve overall circuit performance. In another embodiment, the semiconductor die58can be mechanically and electrically connected directly to PCB52using flipchip style first level packaging without intermediate carrier106.

FIGS. 3a-3oillustrate, in relation toFIGS. 1 and 2a-2c, a process of forming an insulating layer in notches around conductive TSV for stress relief.FIG. 3ashows a semiconductor wafer120with a base substrate material122, such as silicon, germanium, gallium arsenide, indium phosphide, or silicon carbide, for structural support. A plurality of semiconductor die or components124is formed on wafer120separated by a non-active, inter-die wafer area or saw street126as described above. Saw street126provides cutting areas to singulate semiconductor wafer120into individual semiconductor die124.

FIG. 3bshows a cross-sectional view of a portion of semiconductor wafer120. Each semiconductor die124has a back surface128and active surface130containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface130to implement analog circuits or digital circuits, such as digital signal processor (DSP), ASIC, memory, or other signal processing circuit. Semiconductor die124may also contain integrated passive devices (IPDs), such as inductors, capacitors, and resistors, for RF signal processing.

InFIG. 3c, a plurality of blind vias133is formed into active surface130and partially but not completely through semiconductor wafer120using mechanical drilling, laser drilling, or deep reactive ion etching (DRIE).

An electrically conductive layer136is formed over insulating layer134within vias133using a patterning and metal deposition process such as printing, PVD, CVD, sputtering, electrolytic plating, and electroless plating. Conductive layer136can be one or more layers of Ni, tantalum nitride (TaN), nickel vanadium (NiV), platinum (Pt), palladium (Pd), chromium copper (CrCu), or other suitable barrier material.

InFIG. 3e, blind vias133are filled with Al, Cu, Sn, Ni, Au, Ag, titanium (Ti), tungsten (W), poly-silicon, or other suitable electrically conductive material using electrolytic plating, electroless plating process, or other suitable metal deposition process to form z-direction conductive TSV138lined with insulating layer134and conductive layer136and embedded within semiconductor wafer120. In one embodiment, conductive layer136operates as a barrier layer to inhibit diffusion of conductive TSV138, e.g. Cu, into insulating layer134and base substrate material122. Conductive TSV138are electrically connected to the circuits on active surface130. A portion of active surface130of semiconductor die124is optionally removed by grinder140or CMP to planarize the surface and expose conductive TSV138.

InFIG. 3f, an electrically conductive bump material is deposited over conductive TSV138using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive TSV138using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form spherical balls or bumps142. In some applications, bumps142are reflowed a second time to improve electrical contact to conductive TSV138. An optional under bump metallization (UBM) layer can be disposed between bumps142and conductive TSV138. Bumps142can also be compression bonded to conductive TSV138. Bumps142represent one type of interconnect structure that can be formed over conductive TSV138. The interconnect structure can also use stud bump, micro bump, or other electrical interconnect.

FIG. 3gshows a temporary substrate or carrier144containing sacrificial base material such as silicon, polymer, beryllium oxide, glass, or other suitable low-cost, rigid material for structural support. An interface layer or double-sided tape146is formed over carrier144as a temporary adhesive bonding film, etch-stop layer, or thermal release layer. Semiconductor wafer120is inverted, positioned over, and mounted to interface layer146over carrier144with active surface130and bumps142oriented toward the carrier.FIG. 3hshows semiconductor wafer120mounted to interface layer146over carrier144.

Semiconductor wafer120and carrier144are placed in a chase mold. A mold underfill (MUF) material148in a liquid state is injected into the chase mold between semiconductor wafer120and carrier144. MUF material148can be an encapsulant, molding compound, or polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler. MUF material148is cured.FIG. 3ishows MUF material148disposed between semiconductor wafer120and carrier144.

InFIG. 3j, a portion of back surface128is removed by a combination of backgrinding, CMP, and/or etching processes to expose conductive TSV138above surface150of semiconductor wafer120. Alternatively, a portion of back surface128is removed by laser direct ablation (LDA) using laser151so that conductive TSV138extends above surface150of semiconductor wafer120.

An electrically conductive layer152is formed over insulating layer134, conductive layer136, and conductive TSV138using a patterning and metal deposition process such as printing, PVD, CVD, sputtering, electrolytic plating, and electroless plating. Conductive layer152can be one or more layers of titanium tungsten (TiW), titanium copper (TiCu), titanium tungsten copper (TiWCu), tantalum nitrogen copper (TaNCu), or other suitable material. In one embodiment, conductive layer152operates as a seed layer for electrical interconnect to external devices. Conductive layer152can be formed prior to etching surface128so that conductive TSV138extends above surface150.

InFIG. 3k, a plurality of grooves or notches154is formed in surface150of semiconductor wafer120around insulating layer134, conductive layer136, and conductive TSV138by removing a portion of base substrate material122. In one embodiment, notches154can be formed by an angled isotropic dry etch using RF power to form sloped surface156. In another embodiment, notches154can be formed by a wet etch using a masking layer having a linear gradient contrast portion. Surface150of semiconductor wafer120is exposed to ultraviolet (UV) light. The linear gradient contrast portion of the masking layer passes the UV light with linearly varying intensity. The masking layer is removed and surface150is subjected to an etching process. A portion of surface150is removed according to its linear gradient cured state leaving notches154with sloped surface156. Alternatively, notches154are formed by LDA using laser157. In particular, the intensity or duration of laser157is controlled to create notches154having linear sloped surface156in surface150of semiconductor wafer120.FIG. 3lshows a plan view of notches154formed in surface150of semiconductor wafer120around insulating layer134, conductive layer136, and conductive TSV138. Notches154can be rectangular or circular.

InFIG. 3n, a portion of insulating layer158over conductive TSV138is removed by CMP or etching process to expose conductive layer152.FIG. 3oshows further detail of insulating layer158, insulating layer134, conductive layer136, and conductive TSV138in block160defined inFIG. 3n.

Semiconductor wafer120is singulated through insulating layer158, saw street126, and MUF material148using a saw blade or laser cutting tool162into individual semiconductor die124. Carrier144and interface layer146are removed by chemical etching, mechanical peeling, CMP, mechanical grinding, thermal bake, UV light, laser scanning, or wet stripping to expose bumps142.

FIG. 4shows semiconductor die124after singulation. The circuits on active surface130of semiconductor die124are electrically connected to conductive TSV138and bumps142. Notches154are formed in surface150of semiconductor wafer120. The insulating layer158is formed over surface150and conductive TSV138and into notches154. The insulating layer158disposed in notches154provide stress relief as well as electrical isolation between conductive TSV138and semiconductor die124to reduce current leakage between the conductive TSV and semiconductor die.

FIG. 5shows two stacked semiconductor die124a-124belectrically connected through conductive TSV138. The circuits on active surface130of semiconductor die124aare electrically connected through conductive TSV138and bumps142to the circuits on active surface130of semiconductor die124b. The insulating layer158disposed in notches154provide stress relief as well as electrical isolation between conductive TSV138and semiconductor die124to reduce current leakage between the conductive TSV and semiconductor die.

In another embodiment continuing fromFIG. 3j, a plurality of grooves or notches164is formed in surface150of semiconductor wafer120around conductive TSV138by removing a portion of base substrate material122and insulating layer134, as shown inFIG. 6a. In one embodiment, notches164can be formed by an angled isotropic dry etch using RF power to form sloped surface166. In another embodiment, notches164can be formed by a wet etch using a masking layer having a linear gradient contrast portion. Surface150of semiconductor wafer120is exposed to UV light. The linear gradient contrast portion of the masking layer passes the UV light with linearly varying intensity. The masking layer is removed and surface150is subjected to an etching process. A portion of surface150is removed according to its linear gradient cured state leaving notches164with sloped surface166. Notches164also remove a portion of insulating layer134. Alternatively, notches164are formed by LDA using laser168. In particular, the intensity or duration of laser168is controlled to create notches164having linear sloped surface166in surface150of semiconductor wafer120and insulating layer134.FIG. 6bshows a plan view of notches164formed in surface150of semiconductor wafer120and insulating layer134around conductive layer136and conductive TSV138. Notches164can be rectangular or circular.

InFIG. 6d, a portion of insulating layer170over conductive TSV138is removed by CMP or etching process to expose conductive layer152.FIG. 6eshows further detail of insulating layer158, insulating layer134, conductive layer136, and conductive TSV138in block172defined inFIG. 6d.

Semiconductor wafer120is singulated through insulating layer158, saw street126, and MUF material148using a saw blade or laser cutting tool174into individual semiconductor die124. Carrier144and interface layer146are removed by chemical etching, mechanical peeling, CMP, mechanical grinding, thermal bake, UV light, laser scanning, or wet stripping to expose bumps142.

FIG. 7shows semiconductor die124after singulation. The circuits on active surface130of semiconductor die124are electrically connected to conductive TSV138and bumps142. Notches164are formed in surface150of semiconductor wafer120. The insulating layer170is formed over surface150, conductive layer136, and conductive layer152and into notches164over insulating layer134. The insulating layer170disposed in notches164provide stress relief as well as electrical isolation between conductive TSV138and semiconductor die124to reduce current leakage between the conductive TSV and semiconductor die.