ARRAY SUBSTRATE, METHOD FOR PREPARING THE SAME, AND DISPLAY PANEL

The present application relates to the technical field of display panels, and provides an array substrate and a method for preparing the same, and a display panel. The array substrate includes a base substrate, a buffer layer, an active layer, a gate insulation layer, a first gate, an interlayer insulation layer, a source and a drain that are laminated. The active layer includes the first active layer and the two second active layers, and the first active layer forms the channel region.

CROSS REFERENCE TO RELATED APPLICATION

Pursuant to 35 U.S.C. § 119 and the Paris Convention Treaty, this application claims the benefit of Chinese Patent Application No. 202310836246.1 filed Jul. 10, 2023, the contents of which are incorporated herein by reference.

TECHNICAL FIELD

The present application relates to the technical field of display panels, and more particularly to an array substrate and a method for preparing the same, and a display panel.

BACKGROUND

As an important component of a flat panel display device, a thin film transistor (TFT) can be formed on a glass substrate or a plastic substrate. TFT is usually used as a switching device and a driving device in a display apparatus, such as a liquid crystal display device (LCD) and an organic light emitting display (OLED).

When fabricating thin film transistors on a glass substrate or a plastic substrate, a gate is usually used as a conductive mask of the active layer to form a corresponding channel region. However, due to the diffusion phenomenon in different conductive processes, an actual width of the channel region is smaller than a width of the gate. Due to the definition requirements of the display panel, the size of the thin film transistor needs to be reduced as much as possible. If a difference between the width of the channel region and the width of the gate is too large, short-channel thin film transistors may lose their switching characteristics, therefore, the difference needs to be as small as possible. However, due to the diffusion effect, the difference cannot be ensured, and ultimately the switching characteristics requirements cannot be taken into account.

SUMMARY

An object of the present application is to provide an array substrate, aimed at solving the problem that traditional array substrates cannot meet the requirements of switching characteristics while meeting the clarity requirements.

In a first aspect of an embodiment of the present application, an array substrate is provided, and the array substrate includes:a base substrate; anda buffer layer, an active layer, a gate insulation layer, and a first gate that are sequentially laminated on the base substrate along a first direction, and the active layer includes a first active layer and two second active layers respectively located on two sides of the first active layer;along the first direction, the two second active layers overlap with the two sides of the first active layer respectively, a channel region is formed on the first active layer, a conductive portion is formed on each of the two second active layers; and along a second direction, an extension width of the first active layer is greater than an extension width of the first gate, and the first direction intersects with the second direction;an interlayer insulation layer is provided on the buffer layer, the interlayer insulation layer covers the first gate, the two second active layers and the gate insulation layer, and the interlayer insulation layer is provided with two through holes respectively arranged above the two second active layers; anda source and a drain are respectively arranged on the interlayer insulation layer, and the source and the drain are respectively connected to the corresponding two conductive portions of the two second active layers through the two through holes.

In an embodiment, along the first direction, two sides of the first gate respectively coincide with one side of each of the two second active layers, the channel region is formed between parts of the second active layers coincided with the first gate and the first active layer, and the two conductive portions are formed at parts of the two second active layers that are not coincided with the first gate.

In an embodiment, along the second direction, the extension width of the first gate is less than an extension width of the gate insulation layer; andthe extension width of the first active layer is greater than the extension width of the gate insulation layer.

In an embodiment, the array substrate further includes:a second gate, located between the base substrate and the buffer layer, the buffer layer covers the second gate, and along the second direction, an extension width of the second gate is greater than the extension width of the first gate.

In an embodiment, the array substrate further includes:a passivation layer, covers the interlayer insulation layer, the source and the drain.

In a second aspect of an embodiment of the present application, a method for preparing an array substrate is provided, and the method includes steps as following:sequentially depositing a buffer layer, an active layer, a gate insulation layer and a first gate on a base substrate along a first direction; where the active layer comprises a first active layer and two second active layers respectively located on two sides of the first active layer; along the first direction, the two second active layers overlap with the two sides of the first active layer respectively, and along a second direction, an extension width of the first active layer is greater than an extension width of the first gate, and the first direction intersects with the second direction;conducting the two second active layers using the first gate as a mask; where a channel region is formed in the first active layer, and two conductive portions are respectively formed on the two second active layers;depositing an interlayer insulation layer to enable the interlayer insulation layer to cover the buffer layer, the first gate, the two second active layers and the gate insulation layer; and exposing and developing on the interlayer insulation layer to form two through holes directly reaching the two conductive portions of the two second active layers, respectively; anddepositing a source and a drain on the interlayer insulation layer and in the two through holes.

In an embodiment, along the first direction, two sides of the first gate respectively coincide with one side of each of the two second active layers; andthe channel region is formed between parts of the second active layers coincided with the first gate and the first active layer, and the two conductive portions are formed at parts of the two second active layers that are not coincided with the first gate.

In an embodiment, the step of depositing sequentially to form the buffer layer, the active layer, the gate insulation layer and the first gate on the base substrate specifically includes:sequentially depositing the buffer layer and the first active layer on the base substrate;sequentially depositing the two second active layers at two side of the first active layer respectively, where along the first direction, the two second active layers overlap with two sides of the first active layer respectively;etching the two second active layers along the second direction, such that a channel groove is formed by a part of the first active layer that is not overlapped with the two second active layers and edges of the two second active layers and configured for receiving the gate insulation layer; anddepositing the gate insulation layer in the channel groove, and depositing the first gate on the gate insulation layer.

In an embodiment, the method further includes:depositing a second gate on the base substrate; where the second gate is located between the base substrate and the buffer layer, the buffer layer covers the second gate, and along the second direction, an extension width of the second gate is greater than an extension width of the first gate; anddepositing a passivation layer on the interlayer insulation layer, the source and the drain.

A third aspect of an embodiment of the present application provides a display panel, and the display panel includes: an OLED device and an array substrate; the OLED device is stacked above the array substrate, and the array substrate is the array substrate provided in the first aspect or the array substrate prepared based on the preparation method in the second aspect.

The first aspect of the embodiment of the present application provides the array substrate including the base substrate, the buffer layer, the active layer, the gate insulation layer, the first gate, the interlayer insulation layer, the source and the drain that are laminated. The active layer includes the first active layer and the two second active layers, and the first active layer forms the channel region. By using the first gate as a conductive mask for the active layer, the second active layer is conductive, which will not affect the extension width of the channel region of the first active layer, so that the width difference between the channel region and the first gate is within the preset range, the problem of excessive width difference caused by the diffusion phenomenon of the channel region is reduced. Thus, the switching characteristics requirements of thin film transistors and the clarity requirements of display panels can be simultaneously satisfied.

It can be understood that the beneficial effects of the second and third aspects mentioned above can be found in the relevant description of the first aspect, and which will not be further repeated here.

DETAILED DESCRIPTION OF EMBODIMENTS

In order to make the technical problems, technical solutions, and beneficial effects to be solved by the present application clearer, the following is a further detailed explanation of present application in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only intended to explain the present application and are not intended to limit the present application.

It is noted that when a component is referred to as being “fixed to” or “disposed on” another component, it can be directly or indirectly on another component. When a component is referred to as being “connected to” another component, it can be directly or indirectly connected to another component.

It needs to be understood that, directions or location relationships indicated by terms such as “length”, “width”, “up”, “down”, “front”, “rear”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, and so on are the directions or location relationships shown in the accompanying figures, which are only intended to describe the present application conveniently and simplify the description, but not to indicate or imply that an indicated device or component must have specific locations or be constructed and manipulated according to specific locations; therefore, these terms shouldn't be considered as any limitation to the present application.

In addition, terms “the first” and “the second” are only used in describe purposes, and should not be considered as indicating or implying any relative importance, or impliedly indicating the number of indicated technical features. As such, technical feature(s) restricted by “the first” or “the second” can explicitly or impliedly comprise one or more such technical feature(s). In the description of the present application, “a plurality of” means two or more, unless there is additional explicit and specific limitation.

As shown inFIG.1, a first aspect of the embodiment of the present application provides an array substrate10, which includes:a base substrate11; anda buffer layer12, an active layer13, a gate insulation layer14, and a first gate15that are sequentially laminated on the base substrate11along a first direction, the active layer13includes a first active layer131and two second active layers132respectively located on two sides of the first active layer131;along the first direction, the two second active layers132overlap with the two sides of the first active layer131respectively, a channel region101is formed on the first active layer131, a conductive portion102is formed on each of the two second active layers132; and along a second direction, an extension width of the first active layer131is greater than an extension width of the first gate15, and the first direction intersects with the second direction;an interlayer insulation layer16is provided on the buffer layer12, the interlayer insulation layer16covers the first gate15, the two second active layers132and the gate insulation layer14, and the interlayer insulation layer16is provided with two through holes17respectively arranged above the two second active layers132; anda source18and a drain19are respectively arranged on the interlayer insulation layer16, and the source18and the drain19are respectively connected to the corresponding two conductive portions102of the two second active layers132through the two through holes17.

In the embodiment, when the thin film transistor is manufactured, the buffer layer12, the first active layer131, and the two second active layers132are laminated on the base substrate11along the first direction, and the two second active layer132are arranged on two sides of the first active layer131, respectively, and the first active layer131and the two second active layers132are oxidized semiconductors. The edges on two sides of the first active layer131overlap with the edges of two second active layers132respectively, that is, the two second active layers132cover part of the first active layer131respectively, and the middle position of the first active layer131is not covered by the two second active layers132. A gate insulation layer14is arranged on a part of the first active layer131which is not covered by the two second active layers132, and a first gate15is laminated on the first active layer14, and then a mask plate of preset size is used for exposing and developing directly above the first gate15to form a gate insulation layer14and a first gate15of the same size. Then the gate insulation layer14and the first gate15are etched to form the gate insulation layer14of the preset extension width and the first gate15of the preset extension width, so that the distance between widths of the gate insulation layer14and the first gate15is within the preset range.

Then, the first gate15is used as the conducting mask to carry out the conducting of the two second active layers132. Due to the overlapping portion between the first gate15and the two second active layers132respectively, and the first active layer131is covered by the gate insulation layer14and the two second active layers132respectively, the gate insulation layer14and the second active layer132can protect the first active layer131to prevent the first active layer131from being bombarded by plasma, which will shorten the width of the channel region101of the first active layer131, so as to further avoid the short channel effect of the thin film transistor. Therefore, as shown inFIG.2, the two second active layers132form the conductive material and constitute the two conductive portions102of the two second active layers132, while the first active layer131remains as the oxidized semiconductor and constitutes the channel region101of the thin film transistor, and the interlayer insulation layer16is laminated on top of the first gate15, the gate insulation layer14and the second active layer132. The through hole17is correspondingly formed on the interlayer insulation layer16, and the source18and the drain19are formed by depositing in the through hole17and on the interlayer insulation layer16, and the source18and the drain19are connected to the two second active layers132through two through holes17respectively. The drain19, the two second active layers132, the first active layer131, the first gate15and the source18form the current loop of the thin film transistor.

By adjusting the extension width of the first active layer131to be greater than the extension width of the first gate15, and covering the first active layer131with the two second active layers132and the gate insulator layer14, the length of the effective channel region101of the first active layer131will not be affected under the unchanged conducting process. The distance between the extension width of the effective channel region101and the extension width of the first gate15can still be within the preset range under the limited diffusion effect. On the premise that the size of the thin film transistor is small enough to meet the clarity of the display panel, the extension width of the channel region101is close to the extension width of the first gate15, so as to avoid the thin film transistor losing its switching characteristics due to short channels. It can meet both the switching characteristics of the thin film transistor and the clarity requirements of the display panel.

In the embodiment, along the first direction, two sides of the first gate15can overlap with parts of the two second active layers132, or without overlap with the two second active layers132, in order to ensure the length of the effective channel region101of the first active layer131and avoid the gap between the two second active layers132and the first gate15to bombard the first active layer131by the plasma through the gap during the conducting process. Optionally, as shown inFIG.2, along the first direction, the two sides of the first gate15respectively coincide with the two sides of the two second active layers132, and when conducting the second active layer132, the plasma cannot bombardment the part of the two second active layer132that coincide with the first gate15, and the parts of the two second active layers132that overlapped with the first gate15remain as the oxidized semiconductor, the parts of the two second active layers that overlapped with the first gate15form the channel region101with the first active layer131, while the parts of the two second active layers that did not overlap with the first gate15are conducted to form the conductive material, so as to form the conductor portions102of the two second active layers132.

In order to achieve effective coverage of the first active layer131, a channel groove is formed between the part of the first active layer131that is not overlapped with the two second active layers132and edge portions of the two second active layers132and configured for receiving the gate insulation layer14, the edge portions of the two second active layers132constitute the sides of the channel groove, and the middle portion of the first active layer131constitutes the bottom of the channel groove.

Correspondingly, along the second direction, the extension width of the first active layer131is greater than the extension width of the gate insulation layer14, and the gate insulation layer14and the second active layer132completely cover the first active layer131, which can avoid conducting the first active layer131under conducting. Thus, the distance between the extension width of the effective channel region101of the first active layer131and the extension width of the first gate15is within the preset range, which can simultaneously meet the switching characteristics of the thin film transistor and the clarity requirements of the display panel. At the same time, in order to improve the insulation effect between the two second active layers132and the first gate15, and improve the electrical characteristics of the thin film transistor, the extension width of the gate insulation layer14is greater than the extension width of the first gate15, and correspondingly, the edge portion of the gate insulation layer14also overlaps with the edge portions of the two second active layers132.

In the embodiment, the extension width of the first active layer131can be set according to the switching characteristics and the size of the thin film transistor. On the premise that the extension width of the first active layer131is greater than the extension width of the first gate15, the difference between the extension width of the first active layer131and the extension width of the first gate15can be set according to the diffusion effect and the switching characteristics of the thin film transistor.

Further, in order to increase the diversity of thin film transistors, as shown inFIG.3, the array substrate10optionally includes:a second gate20, located between the base substrate11and the buffer layer12, the second gate20covers the second gate20, and the extension width of the second gate20is greater than the extension width of the first gate15along the second direction.

In the embodiment, the source18, the drain19, the active layer13and the second gate20constitute a bottom-gate structure thin film transistor, and the source18, the drain19, the active layer13and the first gate15constitute a top-gate structure thin film transistor, and a dual-gate structure thin film transistor is formed by providing the first gate15and the second gate20. Under different electrical connection requirements, a corresponding gate structure can be selected for the connection and arrangement of the thin film transistor to improve the diversity of the thin film transistor.

Further, in order to improve the overall electrical characteristics of the thin film transistor, as shown inFIG.4, the array substrate10also includes a passivation layer21, in which the passivation layer21covers the interlayer insulation layer16, the source18and the drain19to achieve the overall insulation of the thin film transistor and improve the electrical insulation characteristics of the thin film transistor. The switching control of the thin film transistor is realized by providing a hole in the passivation layer21and connecting to the corresponding module by a lead wire.

The beneficial effects of the embodiment of the present application embodiment compared to the prior art are that the array substrate10includes the base substrate11, the buffer layer12, the active layer13, the gate insulation layer14, the first gate15, the interlayer insulation layer16, the source18and the drain19that are laminated. The active layer13includes the first active layer131and the two second active layers132, and the first active layer131forms the channel region101. By using the first gate15as a conductive mask for the active layer13, the second active layers132are conductive, which will not affect the extension width of the channel region101of the first active layer131, so that the width difference between the channel region101and the first gate15is within the preset range, the problem of excessive width difference caused by the diffusion phenomenon of the channel region101is reduced. Thus, the switching characteristics requirements of thin film transistors and the clarity requirements of display panels can be simultaneously satisfied.

In the second aspect of the embodiment of the present application, a method for preparing an array substrate10is proposed, as shown inFIG.5, the method includes:

Step S10: sequentially depositing a buffer layer12, an active layer13, a gate insulation layer14and a first gate15on a base substrate along a first direction; and the active layer13includes a first active layer131and two second active layers132respectively located on two sides of the first active layer131; along the first direction, the two second active layers132overlap with the two sides of the first active layer131respectively, and along a second direction, an extension width of the first active layer131is greater than an extension width of the first gate15, and the first direction intersects with the second direction.

In the embodiment, when the thin film transistor is manufactured, the buffer layer12, the first active layer131, and the two second active layers132are laminated and deposited on the base substrate11along the first direction, and the two second active layer132are arranged on two sides of the first active layer131, respectively, and the first active layer131and the two second active layers132are oxidized semiconductors. The edges on two sides of the first active layer131overlap with the edges of the two second active layers132respectively, that is, the two second active layers132cover part of the first active layer131respectively, and the middle position of the first active layer131is not covered by the two second active layers132. A gate insulation layer14is arranged on a part of the first active layer131which is not covered by the two second active layers132, and a first gate15is laminated on the first active layer14, and then a mask plate of preset size is used for exposing and developing directly above the first gate15to form a gate insulation layer14and a first gate15of the same size. Then the gate insulation layer14and the first gate15are etched to form the gate insulation layer14of the preset extension width and the first gate15of the preset extension width, so that the distance between widths of the gate insulation layer14and the first gate15is within the preset range.

In order to realize the setting mode of the first active layer131and the two second active layers132, optionally, as shown inFIG.6, step S10includes:

In step S11, as shown inFIG.7, sequentially depositing the buffer layer12and the first active layer131on the base substrate11; the buffer layer12and the first active layer131can be formed by chemical vapor deposition or physical vapor deposition. When initially formed, the extension width of the first active layer131is the same as that of the buffer layer12. In order to form the first active layer131of the corresponding size and shape, the first active layer131of the initial deposition is etched, exposed and developed, so as to form the first active layer131with extension width being greater than the extension width of the first gate15.

In step S12, as shown inFIG.8, depositing two second active layers132on two sides of the first active layer131respectively; and the two second active layers132overlap with two sides of the first active layer131respectively along the first direction. The second active layers132can be deposited in various ways, such as the second active layers132are deposited on two sides of the first active layer131respectively. Then the second active layers132on two sides are etched, exposed and developed to form the corresponding shape of the second active layers132, or the second active layer132is deposited on the buffer layer12and the first active layer131, and the second active layer132covers the first active layer131as a whole. Then, the second active layer132located above the first active layer131is removed by etching, exposing and developing, so as to form the two second active layers132located on two sides of the first active layer131.

In step S13, etching the two second active layers132along the second direction, such that a channel groove is formed by a part of the first active layer131that is not overlapped with the two second active layers132and edges of the two second active layers132and configured for receiving the gate insulation layer14;

In step S14, as shown inFIG.9, depositing the gate insulation layer14in the channel groove, and depositing the first gate15on the gate insulation layer14.

After the first active layer131and the second active layers132are formed, the second active layer132is etched or exposed and developed to form the channel groove, the edge parts of the second active layers132form the sides of the channel groove, the middle part of the first active layer131forms the bottom of the channel groove, and then the gate insulation layer14is deposited on the channel groove, and the first gate15is deposited on the gate insulation layer14. The sizes of the gate insulation layer14and the first gate15are the same as that of the active layer13at the initial deposition. In order to form the gate insulation layer14and the first gate15of the corresponding shape and size, a mask of the corresponding size is arranged above the first gate15. The gate insulation layer14and the first gate15of the same size are formed by exposing and developing, and further, the gate insulation layer14with a preset extension width and the first gate15with a preset extension width are formed along the second direction by improving the etching process.

In step S20, as shown inFIG.2, conducting the two second active layers132using the first gate15as a mask; and a channel region101is formed in the first active layer131, and two conductive portions102are respectively formed on the two second active layers132;

In step S30, as shown inFIG.10, depositing an interlayer insulation layer16covering the buffer layer12, the first gate15, the two second active layers132and the gate insulation layer14; and exposing and developing on the interlayer insulation layer16to form two through holes17directly corresponding to the two conductive portions102of the two second active layers132;

In step S40, as shown inFIG.1, depositing a source18and a drain19on the interlayer insulation layer16and in the two through holes17.

The first gate15is used as the conducting mask to carry out the conducting of the two second active layers132. Due to the overlapping portion between the first gate15and the two second active layers132respectively, and the first active layer131is covered by the gate insulation layer14and the two second active layers132respectively, the gate insulation layer14and the second active layer132can protect the first active layer131to prevent the first active layer131from being bombarded by plasma, which will shorten the width of the channel region101of the first active layer131, so as to further avoid the short channel effect of the thin film transistor. Therefore, as shown inFIG.2, the two second active layers132form the conductive material and constitute the two conductive portions102of the two second active layers132, while the first active layer131remains as the oxidized semiconductor and constitutes the channel region101of the thin film transistor.

Then the interlayer insulation layer16is laminated on top of the first gate15, the gate insulation layer14and the second active layer132, the through hole17is correspondingly formed on the interlayer insulation layer16, which directly reaches the conductive portions102of the two second active layers132; and the source18and the drain19are formed by depositing in the through hole17and on the interlayer insulation layer16, and the source18and the drain19are connected to the two second active layers132through two through holes17respectively. The drain19, the two second active layers132, the first active layer131, the first gate15and the source18form the current loop of the thin film transistor.

By adjusting the extension width of the first active layer131to be greater than the extension width of the first gate15, and covering the first active layer131with the two second active layers132and the gate insulator layer14, the length of the effective channel region101of the first active layer131will not be affected under the unchanged conducting process. The distance between the extension width of the effective channel region101and the extension width of the first gate15can still be within the preset range under the limited diffusion effect. On the premise that the size of the thin film transistor is small enough to meet the clarity of the display panel, the extension width of the channel region101is close to the extension width of the first gate15, so as to avoid the thin film transistor losing its switching characteristics due to short channels. It can meet both the switching characteristics of the thin film transistor and the clarity requirements of the display panel.

In the embodiment, along the first direction, two sides of the first gate15can overlap with parts of the two second active layers132, or without overlap with the two second active layers132, in order to ensure the length of the effective channel region101of the first active layer131and avoid the gap between the two second active layers132and the first gate15to bombard the first active layer131by the plasma through the gap during the conducting process. Optionally, as shown inFIG.2, along the first direction, the two sides of the first gate15respectively coincide with the two sides of the two second active layers132;

The parts of the two second active layers132that coincide with the first gate15and the first active layer131form the channel region101, and the parts of the two second active layers132that do not coincide with the first gate15forms the conductive portions102.

When conducting the second active layer132, the plasma cannot bombardment the part of the two second active layer132that coincide with the first gate15, and the parts of the two second active layers132that overlapped with the first gate15remain as the oxidized semiconductor, the parts of the two second active layers that overlapped with the first gate15form the channel region101with the first active layer131, while the parts of the two second active layers that did not overlap with the first gate15are conducted to form the conductive material, so as to form the conductor portions102of the two second active layers132.

The gate insulation layer14and the second active layer132completely cover the first active layer131, which can avoid conducting the first active layer131under conducting. Thus, the distance between the extension width of the effective channel region101of the first active layer131and the extension width of the first gate15is within the preset range, which can simultaneously meet the switching characteristics of the thin film transistor and the clarity requirements of the display panel. At the same time, in order to improve the insulation effect between the two second active layers132and the first gate15, and improve the electrical characteristics of the thin film transistor, the extension width of the gate insulation layer14is greater than the extension width of the first gate15, and correspondingly, the edge portion of the gate insulation layer14also overlaps with the edge portions of the two second active layers132.

In the embodiment, the extension width of the first active layer131can be set according to the switching characteristics and the size of the thin film transistor. On the premise that the extension width of the first active layer131is greater than the extension width of the first gate15, the difference between the extension width of the first active layer131and the extension width of the first gate15can be set according to the diffusion effect and the switching characteristics of the thin film transistor.

Further, in order to improve the diversity of the thin film transistor, as shown inFIGS.3and11, the method for preparing the array substrate10further optionally includes:

In step S50, depositing the second gate20on the base substrate11, and the second gate20is located between the base substrate11and the buffer layer12, the second gate20covers the second gate20, and the extension width of the second gate20is greater than the extension width of the first gate15along the second direction.

In the embodiment, the source18, the drain19, the active layer13and the second gate20constitute a bottom-gate structure thin film transistor, and the source18, the drain19, the active layer13and the first gate15constitute a top-gate structure thin film transistor, and a dual-gate structure thin film transistor is formed by providing the first gate15and the second gate20. Under different electrical connection requirements, a corresponding gate structure can be selected for the connection and arrangement of the thin film transistor to improve the diversity of the thin film transistor.

In the embodiment, the step of depositing the second gate20is performed before the step S10, that is, after depositing the second gate20, the buffer layer12is deposited, the buffer layer12covers the second gate20, and then the first active layer131, the second active layers132, the gate insulation layer14, the first gate15, the interlayer insulation layer16, the source18and the drain19are deposited sequentially.

Further, in order to improve the overall electrical characteristics of the thin film transistor, as shown inFIGS.4and11, the method for preparing the array substrate10further optionally includes:

In step S60, depositing a passivation layer21on the interlayer insulation layer16, the source18and the drain19.

In the embodiment, the passivation layer21covers the interlayer insulation layer16, the source18and the drain19to achieve the overall insulation of the thin film transistor and improve the electrical insulation characteristics of the thin film transistor. The switching control of the thin film transistor is realized by providing a hole in the passivation layer21and connecting to the corresponding module by a lead wire.

It should be understood that the sequence number of the steps in the above embodiments does not imply the order of execution, and that the order of execution of each process shall be determined by its function and internal logic, and shall not constitute any limitation on the implementation process of the embodiments the present application.

As shown inFIG.12, the third aspect of the embodiment the present application proposes a display panel, which includes an OLED device2and an array substrate10. The specific structure and preparation method of the array substrate10refer to the above embodiments. Since the display panel adopts all the technical schemes of all the above embodiments, Thus, all the beneficial effects of technical solutions with at least the above embodiments will not be described here. In the embodiment, the OLED device is stacked above the array substrate10.

The array substrate10includes a plurality of thin film transistors, and the plurality of thin film transistors constitute the corresponding unit drive circuit, which is connected with the OLED device2to form a single sub-pixel, and the OLED device2lights up according to the drive signal output by the unit drive circuit, and finally displays the corresponding image information.

Optionally, a simplified schematic diagram of the OLED display panel is shown inFIG.3, which also includes a first substrate3and a second substrate1;

The first substrate3, the OLED device2, the array substrate10and the second substrate1are laminated sequentially, the array substrate10includes a plurality of thin film transistors, the first substrate3and the second substrate1play a fixed role, the first substrate3and the second substrate1can choose to use the transparent material of the corresponding material, optionally, in order to ensure light transmission, optionally, the first substrate3and the second substrate1are glass substrates.

The above embodiments are used only to illustrate the technical solution of this application and not to limit the technical solutions of the present application. Although the present application has been explained in detail with reference to the above-described embodiments, it should be understood for the ordinary skilled one in the art that, the technical solutions described in each of the above-described embodiments can still be amended, or some technical features in the technical solutions can be replaced equivalently; these amendments or equivalent replacements, which won't make the essence of corresponding technical solution to be broken away from the spirit and the scope of the technical solution in various embodiments of the present application, should all be included in the protection scope of the present application.