Semiconductor package with connection substrate and method of manufacturing the same

A semiconductor package includes a lower substrate, a connection substrate coupled to the lower substrate, the connection substrate having a lateral portion surrounding a cavity, and a first conductive pattern on a top surface of the lateral portion, a lower semiconductor chip on the lower substrate, the lower semiconductor chip being in the cavity of the connection substrate, and the lower semiconductor chip including a second conductive pattern on a top surface of the lower semiconductor chip, a bonding member connecting the first conductive pattern and the second conductive pattern to each other, and a top package on the first conductive pattern and the second conductive pattern.

CROSS-REFERENCE TO RELATED APPLICATION

Korean Patent Application No. 10-2018-0066049 filed on Jun. 8, 2018, in the Korean Intellectual Property Office, and entitled: “Semiconductor Package and Method of Manufacturing the Same,” is incorporated by reference herein in its entirety.

BACKGROUND

The present disclosure relates to a semiconductor package and a method of manufacturing the same.

2. Description of the Related Art

A semiconductor package is provided to implement an integrated circuit chip to qualify for use in electronic products. In one type of a semiconductor package, a semiconductor chip is mounted on a printed circuit board and bonding wires or bumps are used to electrically connect the semiconductor chip to the printed circuit board. With the recent development of electronic industry, the semiconductor package is variously developed to reach the goal of compact size, small weight, and/or low manufacturing cost. In addition, many kinds of semiconductor packages also include, e.g., high-capacity mass storage devices.

SUMMARY

According to some example embodiments, a semiconductor package may include a lower substrate, a connection substrate coupled to the lower substrate, the connection substrate having a lateral portion surrounding a cavity, and a first conductive pattern on a top surface of the lateral portion, a lower semiconductor chip on the lower substrate, the lower semiconductor chip being in the cavity of the connection substrate, and the lower semiconductor chip including a second conductive pattern on a top surface of the lower semiconductor chip, a bonding member connecting the first conductive pattern and the second conductive pattern to each other, and a top package on the first conductive pattern and the second conductive pattern.

According to some example embodiments, a semiconductor package may include a connection substrate including a cavity in the connection substrate and a first conductive pattern on a top surface of the connection substrate, a semiconductor chip in the cavity and including a second conductive pattern, the semiconductor chip having an inactive surface on which the second conductive pattern is provided and an active surface facing the inactive surface, and a bonding member electrically connecting the first conductive pattern and the second conductive pattern to each other. The semiconductor chip and the second conductive pattern may be electrically insulated from each other. The connection substrate may further include a via that penetrates the connection substrate and is connected to the first conductive pattern.

According to some example embodiments, a method of manufacturing a semiconductor package may include providing a lower semiconductor chip including a first conductive pattern on an inactive surface of the lower semiconductor chip, providing a connection substrate including a cavity in the connection substrate and a second conductive pattern on a top surface of the connection substrate, providing the lower semiconductor chip and the connection substrate on a lower substrate to place the lower semiconductor chip in the cavity of the connection substrate, bonding the first conductive pattern and the second conductive pattern to each other, providing a top package including a plurality of connection terminals on a bottom surface of the top package, and mounting the top package on the lower semiconductor chip and the connection substrate to couple the connection terminals to the first conductive pattern and the second conductive pattern.

DETAILED DESCRIPTION

The following describes a semiconductor package according to example embodiments with reference to the accompanying drawings.FIG. 1illustrates a cross-sectional view of a semiconductor package according to some example embodiments.

Referring toFIG. 1, a bottom package P100may be provided. The bottom package P100may include a lower substrate100, a connection substrate200, a lower semiconductor chip300, and a lower mold member400.

For example, the lower substrate100may be or include a printed circuit board (PCB) provided on its top surface with signal patterns. In another example, the lower substrate100may have an alternating structure of a dielectric layer and a wiring line layer.

External terminals110may be disposed below the lower substrate100, e.g., on a bottom surface of the lower substrate100that faces away from the lower semiconductor chip300. The external terminals110may include solder balls or solder bumps, and based on type of the external terminals110, the bottom package P100may include one of a ball grid array (BGA) type, a fine ball-grid array (FBGA) type, and a land grid array (LGA) type.

The connection substrate200may be disposed on the lower substrate100. The connection substrate200may be mounted on a top surface of the lower substrate100, e.g., on a surface opposite the bottom surface of the lower substrate100. For example, the connection substrate200may be mounted on the lower substrate100through solder bumps or solder balls. The connection substrate200may be electrically connected through the lower substrate100to the external terminals110. In this description, the phrase “electrically connected/coupled” may include “directly or indirectly electrically connected/coupled.”

The connection substrate200may include an opening OP, i.e., a cavity OP, that penetrates the connection substrate200. For example, the opening OP may be shaped like an open hole, e.g., a cavity, that mutually connects bottom and top surfaces200band200aof the connection substrate200. For example, as illustrated inFIG. 1, the opening OP may penetrate through an entire thickness of the connection substrate200, so a lateral portion of the connection substrate200may surround the opening OP, e.g., to provide a space to accommodate the lower semiconductor chip300to be explained in more detail below.

The connection substrate200may include a base layer210and a conductive member220in the base layer210. The base layer210may include, e.g., silicon oxide. The conductive member220may occupy an outer, e.g., peripheral, side of the connection substrate200, and the opening OP may occupy an inner, e.g., central, side of the connection substrate200. For example, as illustrated inFIG. 1, the opening OP may penetrate through an entire thickness of the base layer210, and the conductive member220may be positioned within and on surfaces of portions of the base layer210surrounding the opening OP, e.g., a lateral portion of the base layer210may surround the opening OP. For example, the base layer210of the connection substrate200may surround an entire perimeter of the opening OP (FIG. 2). The conductive member220may include connection substrate pads222, connection substrate vias224, and a first conductive pattern226.

The connection substrate pads222may be disposed on a lower portion, e.g., on the bottom surface200b, of the connection substrate200. The connection substrate200may be electrically connected to the lower substrate100through solder balls or solder bumps that are disposed on the connection substrate pads222. The connection substrate vias224may penetrate the base layer210and have an electrical connection with the connection substrate pads222. The first conductive pattern226may be disposed on an upper portion, e.g., on the top surface200a, of the connection substrate200. The first conductive pattern226may include first pads CP1mounted thereon with a top package P200which will be discussed below, second pads CP2coupled to the connection substrate vias224, a first electrical line EL1, and a first bonding pad BP1. A circuit may be constituted by the first electrical line EL1, the first pads CP1, the second pads CP2, and the first bonding pad BP1. As shown inFIG. 1, the top package P200may be mounted also on the second pads CP2. For example, the bottom package P100may be configured such that the first pads CP1have the same function as that of the second pads CP2. Example embodiments of the present disclosure, however, are not limited thereto.

The lower semiconductor chip300may be disposed on the lower substrate100. As illustrated inFIG. 1, the lower semiconductor chip300may be positioned in, e.g., within, the opening OP of the connection substrate200. When viewed in a plan view, the lower semiconductor chip300may have a planar shape smaller than that of the opening OP. For example, the lower semiconductor chip300may be spaced apart from an inner sidewall of the opening OP, e.g., the connection substrate200may surround a perimeter of the lower semiconductor chip300(FIG. 2).

The lower semiconductor chip300may have a bottom surface300bfacing the lower substrate100and a top surface300aopposite to the bottom surface300b. The bottom surface300bof the lower semiconductor chip300may be an active surface, and the top surface300aof the lower semiconductor chip300may be an inactive surface. The lower semiconductor chip300may be mounted on the top surface of the lower substrate100. For example, the lower semiconductor chip300may be flip-chip bonded to the lower substrate100. The lower semiconductor chip300may have a first circuit EC1that is electrically connected to the lower substrate100through lower chip terminals310, e.g., solder balls or solder bumps, that are disposed on lower chip pads305. A flux340may fill a space between the lower semiconductor chip300and the lower substrate100. The lower semiconductor chip300may be, e.g., a logic chip or a memory chip. The logic chip may include a logic part and a memory part. The memory chip may be or include, e.g., one or more of dynamic random-access memory (DRAM), NAND flash, NOR flash, phase-change random-access memory (PRAM), resistive random-access memory (ReRAM), and magnetoresistive random-access memory (MRAM). The lower semiconductor chip300may be electrically connected to the external terminals110.FIG. 1shows only one lower semiconductor chip300, but the lower semiconductor chip300may be provided in plural.

The lower semiconductor chip300may include a second conductive pattern320on the top surface300aserving as an inactive surface of the lower semiconductor chip300. The top surface300aof the lower semiconductor chip300may be located at the same level as that of the top surface200aof the connection substrate200, e.g., the top surfaces300aand200amay be coplanar. The second conductive pattern320may include third pads CP3on which the top package P200is mounted, a second electrical line EL2, and a second bonding pad BP2. The second electrical line EL2may redistribute an electrical connection between the third pad CP3and the second bonding pad BP2. The second conductive pattern320may have no direct electrical connection with the lower semiconductor chip300, e.g., the lower semiconductor chip300and the second conductive pattern320may be electrically insulated from each other via the inactive top surface300a.

For example, the lower semiconductor chip300may include a chip via330penetrating therethrough. The chip via330may extend from the top surface300atoward the bottom surface300bof the lower semiconductor chip300. The chip via330may be coupled to one of the third pads CP3. The chip via330may also be coupled to the lower substrate100. In such cases, the chip via330may electrically connect the second conductive pattern320to the lower substrate100. In this configuration, the chip via330may not be coupled to, or may be electrically insulated from, the first circuit EC1of the lower semiconductor chip300. e.g., the first circuit EC1of the lower semiconductor chip300and the chip via330may extend through opposite ends of the lower semiconductor chip300. In another example, differently fromFIG. 1, the lower semiconductor chip300may not include the chip via330.

A bonding member BM may be provided. The bonding member BM may electrically connect the first bonding pad BP1on the connection substrate200and the second bonding pad BP2on the lower semiconductor chip300to each other. In some example embodiments, the bonding member BM may be or include a bonding wire. The second electrical line EL2and the third pads CP3may be electrically connected through the first and second bonding pads BP1and BP2and the bonding member BM to the connection substrate200and the lower substrate100.

FIG. 2is a plan view for explaining the first conductive pattern226, the second conductive pattern320, and the bonding member BM that are illustrated inFIG. 1, partially showing the lower semiconductor chip300and the connection substrate200. Referring toFIG. 2, the first pads CP1, the second pads CP2, and the bonding pads BP1of the connection substrate200may be electrically connected to each other by the first electrical line EL1. The third pads CP3and the second bonding pads BP2of the lower semiconductor chip300may be electrically connected to each other by the second electrical line EL2. The first and second bonding pads BP1and BP2may be electrically connected to each other by the bonding member BM. For convenience of description,FIG. 2arbitrarily shows an arrangement of the pads CP1, CP2, and CP3and of the bonding pads BP1and BP2, but the present disclosure not limited thereto, e.g., one additional second pad CP2may be positioned on the right side ofFIG. 2to be adjacent to the first pad CP1and connected thereto via the first electrical line EL1(as illustrated inFIG. 1).

Referring back toFIG. 1, the lower mold member400may be disposed on the lower substrate100. The lower mold member400may fill a space between the connection substrate200and the lower semiconductor chip300. The lower mold member400may cover the top surface300aof the lower semiconductor chip300and the top surface200aof the connection substrate200. The lower mold member400may cover the first electrical line EL1, the second electrical line EL2, the first bonding pad BP1, the second bonding pad BP2, and the bonding member BM. The lower mold member400may have therein a first recess RS1exposing the first and second pads CP1and CP2of the connection substrate200and the third pads CP3of the lower semiconductor chip300. The lower mold member400may include a polymer material, e.g., an Ajinomoto build-up film (ABF)®, an epoxy-based polymer, or a thermosetting resin.

In some example embodiments, the lower mold member400may expose the top surface300aof the lower semiconductor chip300.FIG. 3illustrates a cross-sectional view showing a semiconductor package according to some example embodiments. As shown inFIG. 3, the lower mold member400may expose the second electrical line EL2and the third pads CP3on the top surface300aof the lower semiconductor chip300. In this case, the lower mold member400may bury the bonding member BM and the second bonding pad BP2of the lower semiconductor chip300.

Referring back toFIG. 1, the top package P200may be provided on the bottom package P100. The top package P200may include an upper substrate500, an upper semiconductor chip600, an upper mold member700, and connection terminals510.

For example, the upper substrate500may be or include a printed circuit board (PCB) provided on its top surface with signal patterns. In another example, the upper substrate500may have an alternating structure of a dielectric layer and a wiring line layer. The upper substrate500may have a width greater than a width W1of the lower semiconductor chip300, as illustrated inFIG. 1. The width of the upper substrate500may be the same as or less than a width of the lower substrate100, but example embodiments are not limited thereto.

The upper semiconductor chip600may be disposed on the upper substrate500. The upper semiconductor chip600may have a width W2greater than the width W1of the lower semiconductor chip300. When viewed in a plan view, the upper semiconductor chip600may overlap the lower semiconductor chip300and also overlap a portion of the connection substrate200, e.g., the upper semiconductor chip600may completely overlap the lower semiconductor chip300and the lower mold member400in the opening OP around the lower semiconductor chip300. The upper semiconductor chip600may have a bottom surface600bfacing the upper substrate500and a top surface600aopposite to the bottom surface600b. The top surface600aof the upper semiconductor chip600may be an active surface. The upper semiconductor chip600may be mounted on a top surface of the upper substrate500. For example, the upper semiconductor chip600may be wire-bonded to the upper substrate500. The upper semiconductor chip600may be electrically connected to the upper substrate500through, e.g., one or more bonding wires610. The upper semiconductor chip600may be, e.g., a logic chip or a memory chip. The logic chip may include a logic part and a memory part.

The upper mold member700may be disposed on the upper substrate500. The upper mold member700may cover the top surface of the upper substrate500and the top surface600aof the upper semiconductor chip600. The upper mold member700may include a polymer material, e.g., an Ajinomoto build-up film (ABF)®, an epoxy-based polymer, or a thermosetting resin.

The connection terminals510may be disposed below the upper substrate500. The connection terminals510may include solder balls or solder bumps, and based on type of the connection terminals510, the top package P200may include one of a ball grid array (BGA) type, a fine ball-grid array (FBGA) type, and a land grid array (LGA) type. The upper semiconductor chip600may be electrically connected to the connection terminals510.

The connection terminals510may include first connection terminals512and second connection terminals514. The first connection terminals512may be provided on the connection substrate200. The first connection terminals512may be coupled to the first pads CP1of the connection substrate200. The second connection terminals514may be provided on the lower semiconductor chip300. The second connection terminals514may be coupled to the third pads CP3of the lower semiconductor chip300. The upper semiconductor chip600may be electrically connected through the upper substrate500to the first and second connection terminals512and514. The upper semiconductor chip600may include a second circuit EC2that is electrically connected to the external terminal110through the second connection terminal514, the second conductive pattern320, the bonding member BM, and the first conductive pattern226, and also include a third circuit EC3that is electrically connected to the external terminal110through the first connection terminal512and the first conductive pattern226. The second and third circuits EC2and EC3may have no electrical connection with, or may be electrically insulated from, the first circuit EC1of the lower semiconductor chip300, e.g., the first connection terminals512may be electrically insulated from the lower semiconductor chip300.

FIGS. 4 and 5illustrate cross-sectional views showing a semiconductor package according to some example embodiments. Descriptions of elements inFIGS. 4-5corresponding to reference numerals described previously with reference toFIGS. 1-3are omitted or abbreviated for convenience of description.

Referring toFIG. 4, the bonding member BM may be provided. The bonding member BM may electrically connect the first bonding pad BP1and the second bonding pad BP2to each other. In some example embodiments, the bonding member BM may be or include a third conductive pattern410. The third conductive pattern410may be disposed in a second recess RS2of the lower mold member400. The second recess RS2may lie between the first and second bonding pads BP1and BP2. For example, in the second recess RS2of the lower mold member400, the third conductive pattern410may have a shape extending from the first bonding pad BP1to the second bonding pad BP2.

Referring toFIG. 5, the bottom package P100may be a fan-out panel level package (PO-PLP). For example, the lower substrate100may be a redistribution substrate, i.e., a redistribution layer. The lower substrate100may include, e.g., dielectric layers102and conductive layers104. The conductive layers104may include one or more vias penetrating the dielectric layers102. For example, the dielectric layers102may include an inorganic insulating layer, e.g., a silicon oxide layer or a silicon nitride layer. In another example, the dielectric layers102may include a polymer material. The conductive layers104may be surrounded by or embedded in the dielectric layers102. The conductive layers104may redistribute electrical connections between the lower chip pads305of the lower semiconductor chip300and the external terminals110of the lower substrate100. The bottom package P100may have a fan-out structure by the lower substrate100. The conductive layers104may include metal. The conductive layers104may be connected to substrate pads106disposed on a bottom surface of the lower substrate100. A passivation layer108may be provided on the bottom surface of the lower substrate100. The passivation layer108may include an Ajinomoto build-up film (ABF)®, an organic material, an inorganic material, or an insulating polymer, e.g., an epoxy-based polymer. The external terminals110may be disposed on the bottom surface of the lower substrate100. The external terminals110may be placed on the substrate pads106. The external terminals110may be electrically connected through the substrate pads106to the conductive layer104.

The lower substrate100may directly contact the bottom surface200bof the connection substrate200and the bottom surface300bof the lower semiconductor chip300. For example, the lower substrate100may be in a direct contact with the lower chip pads305of the lower semiconductor chip300and with the connection substrate pads222of the connection substrate200.

In semiconductor packages according to some example embodiments, the conductive patterns226and320may be provided on the top surface200aof the connection substrate200and the top surface300aof the lower semiconductor chip300, and the top package P200may be mounted on the conductive patterns226and320. The connection terminals510of the top package P200may all be disposed on the connection substrate200and the lower semiconductor chip300. In such cases, the connection terminals510may be provided with an increased area for their locations, and as a result, the top package P200may increase in the number of output terminals (e.g., the connection terminals510) on the bottom package P100. The conductive patterns226and320may redistribute an electrical circuit of the top package P200, which may result in increasing the degree of freedom of wiring between the top package P200and the bottom package P100. Thus, it may be possible to improve electrical characteristics of a semiconductor package.

Further, no additional substrate may be required for redistribution between the bottom package P100and the top package P200, and accordingly, a semiconductor package may decrease in thickness. Even though no substrate is provided for redistribution, the top package P200may redistribute its electrical connection by using the conductive patterns226and320having small thicknesses. A semiconductor package may therefore be advantageous to reduction in size.

A reduction in total thickness of a semiconductor package may allow the lower semiconductor chip300to have an increased thickness, and thus, the lower semiconductor chip300may have an advantage of heat radiation. Furthermore, heat generated from the lower semiconductor chip300may be discharged out through the conductive patterns226and320. As a result, a semiconductor package may increase in heat radiation and operation stability.

FIGS. 6 to 12illustrate cross-sectional views of stages in a method of manufacturing a semiconductor package according to some example embodiments.

Referring toFIG. 6, the lower semiconductor chip300may be provided. The lower semiconductor chip300may have the bottom surface300band the top surface300afacing each other. The bottom surface300bof the lower semiconductor chip300may be an active surface, and the top surface300aof the lower semiconductor chip300may be an inactive surface. The lower semiconductor chip300may include the lower chip pads305disposed on the bottom surface300bthereof. The lower semiconductor chip300may include the chip via330penetrating therethrough. The chip via330may extend from the top surface300atoward the bottom surface300bof the lower semiconductor chip300. The lower chip terminals310may be attached to the lower chip pads305.

Referring toFIG. 7, the second conductive pattern320may be formed on the top surface300aof the lower semiconductor chip300. For example, a conductive layer may be formed on the top surface300aof the lower semiconductor chip300, and then the conductive layer may be patterned to form the second conductive pattern320. In another example, a shadow mask may be formed on the top surface300aof the lower semiconductor chip300, and then a conductive material may be deposited in a pattern of the shadow mask, which may result in the formation of the second conductive pattern320. The pattern of the shadow mask may partially expose the top surface300aof the lower semiconductor chip300and may define a zone where the second conductive pattern320is formed. The shadow mask may be removed after the second conductive pattern320is formed. The second conductive pattern320may include the third pad CP3, the second electrical line EL2, and the second bonding pad BP2.

Referring toFIG. 8, the lower semiconductor chip300may be mounted on the lower substrate100. The lower semiconductor chip300may be mounted in a flip-chip bonding manner. For example, the flux340may be coated on the bottom surface300bserving as an inactive surface of the lower semiconductor chip300, and then the lower semiconductor chip300may be positioned to cause the lower chip terminals310on the bottom surface300bto face a top surface of the lower substrate100. At this stage, the flux340may protrude onto a lateral surface of the lower semiconductor chip300. The flux340may include a resin, an activator, and a solvent. The solvent may include, e.g., a glycol ether ester compound, a glycol ether compound, an ester compound, a ketone compound, or a cyclic ester compound. A reflow process may be performed on the lower chip terminals310, and thus, the lower semiconductor chip300may be mounted on the lower substrate100.

Referring toFIG. 9, the connection substrate200may be provided. The connection substrate200may include the base layer210and the conductive member220in the base layer210. The conductive member220may include the connection substrate pads222, the connection substrate vias224, and the first conductive pattern226. The first conductive pattern226may include the first pad CP1, the second pad CP2, the first electrical line EL1, and the first bonding pad BP1. For example, the base layer210may be etched and then its inside may be filled with a conductive material to form the connection substrate pads222, the connection substrate vias224, and the first conductive pattern226.

The opening OP, also referred to as a cavity, may be formed in the connection substrate200. For example, a portion of the connection substrate200may be removed to form the opening OP that penetrates, e.g., the entire thickness of, the connection substrate200, e.g., a portion of the base layer210may be removed to provide the opening OP, i.e., a cavity, for accommodating the lower semiconductor chip300. The opening OP may be formed by, e.g., an etch process such as drilling, laser ablation, or laser cutting.

The connection substrate200may be mounted on the lower substrate100. At this stage, the connection substrate200may be disposed to place the lower semiconductor chip300in the opening OP, e.g., to have portions of the connection substrate200surround the lower semiconductor chip300in the opening OP. Solder balls or solder bumps on the connection substrate pads222may be reflowed to mount the connection substrate200on the lower substrate100.

Referring toFIG. 10, the bonding member BM may be formed. For example, the first bonding pad BP1of the connection substrate200and the second bonding pad BP2of the lower semiconductor chip300may be connected to each other in a wire bonding manner. In some example embodiments, it may be desirable that the connection substrate200have the top surface200aat the same level as that of the top surface300aof the lower semiconductor chip300, which configuration may easily achieve the wire bonding between the first bonding pad BP1and the second bonding pad BP2.

Referring back toFIG. 11, the lower mold member400may be formed on the lower substrate100. The lower mold member400may fill a space between the connection substrate200and the lower semiconductor chip300. For example, an insulating substance may be injected into a space between the connection substrate200and the lower semiconductor chip300, and then the insulating substance may be cured to form the lower mold member400. The insulating substance may cover the first conductive pattern226of the connection substrate200, the second conductive pattern320of the lower semiconductor chip300, and the bonding member BM. The insulating substance may include an insulating polymer or a thermosetting resin.

For example, the lower mold member400may be etched to form a first recess RS1that exposes the first pads CP1, the second pads CP2, and the third pads CP3. In another example, the lower mold member400may be etched to further expose the top surface300aof the lower semiconductor chip300. For example, the lower mold member400may expose the first pads CP1, the second pads CP2, the third pads CP3, and the second electrical line EL2that is on the top surface300aof the lower semiconductor chip300. When the lower mold member400is formed to further expose the top surface300aof the lower semiconductor chip300, the semiconductor package ofFIG. 3may be manufactured. The following describes an example in which the lower mold member400selectively exposes the first, second, and third pads CP1, CP2, and CP3.

Referring toFIG. 12, the external terminals110may be formed on the bottom surface of the lower substrate100. The external terminals110may include solder balls or solder bumps. The external terminals110may be electrically connected to the first and second conductive patterns226and320through the lower substrate100, the conductive member220of the connection substrate200, and the bonding member BM. The bottom package P100may be formed through the processes mentioned above.

Referring back toFIG. 1, the top package P200may be provided on the bottom package P100. The top package P200may include the upper substrate500, the upper semiconductor chip600, the upper mold member700, and the connection terminals510. The upper substrate500may be or include a printed circuit board (PCB) provided on its top surface with signal patterns. The upper semiconductor chip600may be mounted on the upper substrate500. The upper mold member700may cover a top surface of the upper substrate500and the top surface600aof the upper semiconductor chip600. The connection terminals510may be disposed below the upper substrate500. The connection terminals510may include the first connection terminals512and the second connection terminals514. The second connection terminals514may be farther away than the first connection terminals512from a location below an edge of the upper substrate500.

The bottom package P100and the top package P200may align with each other to place the first connection terminals512on the first conductive pattern226and to place the second connection terminals514on the second conductive pattern320. The first connection terminals512and the second connection terminals514may be in contact with the first conductive pattern226and the second conductive pattern320, respectively, and then may be reflowed to mount the top package P200on the bottom package P100. Through the processes mentioned above, the semiconductor package ofFIG. 1may be manufactured.

FIGS. 13 to 15illustrate cross-sectional views showing stages in a method of manufacturing a semiconductor package, according to some example embodiments.

Referring toFIG. 13, the lower mold member400may be formed on a resultant structure that is fabricated as described with reference toFIG. 8. The lower mold member400may fill a space between the connection substrate200and the lower semiconductor chip300. For example, an insulating substance may be injected into a space between the connection substrate200and the lower semiconductor chip300, and then may be cured to form the lower mold member400. The lower mold member400may cover the first and second conductive patterns226and320.

Referring toFIG. 14, the lower mold member400may be etched to form the first recess RS1and the second recess RS2. The first recess RS1may expose the first pads CP1, the second pads CP2, and the third pads CP3. When viewed in a plan view, the second recess RS2may be formed between the connection substrate200and the lower semiconductor chip300, or between the first bonding pad BP1of the connection substrate200and the second bonding pad BP2of the lower semiconductor chip300. The second recess RS2may expose a lateral surface of each of the first and second bonding pads BP1and BP2.

Referring toFIG. 15, the third conductive pattern410may be formed in the second recess RS2. The third conductive pattern410may be formed by filling the second recess RS2with a conductive material. For example, a plating process may be performed to fill the second recess RS2with a conductive material. In another example, a printing process, e.g., ink jet printing, may be performed to fill the second recess RS2with a conductive material. A bottom package P100may be formed through the processes mentioned above.

After that, the processes discussed with reference toFIG. 1may be performed. For example, the top package P200may be mounted on the bottom package P100to manufacture the semiconductor package ofFIG. 4.

FIGS. 16 to 23illustrate cross-sectional views of stages in a method of manufacturing a semiconductor package, according to some example embodiments.

Referring toFIG. 16, the connection substrate200may be provided. The connection substrate200may include the base layer210and the conductive member220in the base layer210. The conductive member220may include the connection substrate pads222, the connection substrate vias224, and the first conductive pattern226. For example, the base layer210may be etched, followed by filling the etched portion with a conductive material to form the connection substrate pads222, the connection substrate vias224, and the first conductive pattern226.

Referring toFIG. 17, the opening OP may be formed in the connection substrate200. A portion of the connection substrate200may be removed to form the opening OP penetrating the connection substrate200. The opening OP may be formed by, e.g., an etch process such as drilling, laser ablation, or laser cutting. The removed portion of the connection substrate200may be a zone in which a lower semiconductor chip300is provided in a subsequent process.

The connection substrate200may be attached onto a carrier substrate800. For example, the carrier substrate800may be an insulating substrate including glass or polymer or a conductive substrate including metal. The carrier substrate800may have a top surface that includes an adhesive member used to adhere the carrier substrate800to the bottom surface200bof the connection substrate200. The adhesive member may include, e.g., a glue tape.

Referring toFIG. 18, the lower semiconductor chip300may be provided on the carrier substrate800, e.g., within the opening OP of the connection substrate200. The lower semiconductor chip300may be the same as the lower semiconductor chip300fabricated as described with reference toFIGS. 5 and 6. The lower semiconductor chip300may be provided in the opening OP of the connection substrate200. At this stage, the lower semiconductor chip300may be adhered to the carrier substrate800. The lower semiconductor chip300may include the lower chip pads305on the lower portion thereof. For example, the lower semiconductor chip300may have the bottom surface300b, which corresponds to an inactive surface in contact with the carrier substrate800.

Referring toFIG. 19, the bonding member BM may be formed. For example, the first bonding pad BP1of the connection substrate200and the second bonding pad BP2of the lower semiconductor chip300may be connected to each other in a wire bonding manner.

Referring toFIG. 20, the lower mold member400may be formed on the carrier substrate800. The lower mold member400may fill a space between the connection substrate200and the lower semiconductor chip300. For example, an insulating substance may be injected into a space between the connection substrate200and the lower semiconductor chip300, and then may be cured to form the lower mold member400. The lower mold member400may cover the first conductive pattern226of the connection substrate200and the second conductive pattern320of the lower semiconductor chip300.

Referring toFIG. 21, a support substrate910may be provided on the connection substrate200. The support substrate910may be, e.g., an insulating substrate such as glass. A glue layer920may be used to adhere the support substrate910to a top surface of the lower mold member400. The glue layer920may be, e.g., a resin film.

The carrier substrate800may be removed. The carrier substrate800may be removed, as designated by a dotted line, to expose the bottom surface300bof the lower semiconductor chip300and the bottom surface200bof the connection substrate200. The carrier substrate800may be removed by applying a shear stress or by chemically treating the adhesive member.

Referring toFIG. 22, the lower substrate100may be formed on the bottom surface300bof the lower semiconductor chip300and the bottom surface200bof the connection substrate200. For example, a dielectric layer102, a conductive layer104, and substrate pads106may be formed on the bottom surface300bof the lower semiconductor chip300and on the bottom surface200bof the connection substrate200, with the result that the lower substrate100may be fabricated. A dielectric material layer, e.g., a silicon oxide layer, may be formed on the bottom surface300bof the lower semiconductor chip300and the bottom surface200bof the connection substrate200, and then patterned to form a portion of the dielectric layer102. The lower chip pads305and the connection substrate pads222may be exposed by the dielectric layer102. A conductive material layer may be formed on a bottom surface of the dielectric layer102, and then patterned to form the conductive layer104and the substrate pads106. The conductive layer104may be electrically connected to the lower semiconductor chip300and the connection substrate200. A dielectric material layer may be formed on a bottom surface of the conductive layer104, and then patterned to form other portion of the dielectric layer102. At this stage, the substrate pads106may be exposed by the dielectric layer102.

External terminals110may be formed on the exposed substrate pads106. The external terminals110may include solder balls or solder bumps.

Referring toFIG. 23, the support substrate910may be removed. For example, the support substrate910may be removed by applying a shear stress or by chemically treating the glue layer920. The support substrate910may be removed, as designated by a dotted line, to expose the top surface of the lower mold member400.

The lower mold member400may be etched to form a first recess RS1exposing the first pads CP1, the second pads CP2, and the third pads CP3. The bottom package P100may be fabricated through the processes mentioned above.

After that, the processes discussed with reference toFIG. 1may be performed. For example, the top package P200may be mounted on the bottom package P100to manufacture the semiconductor package ofFIG. 5.

By way of summation and review, some example embodiments provide a semiconductor package with increased electrical characteristics and a method of manufacturing the same. Some example embodiments also provide a compact-sized semiconductor package and a method of manufacturing the same. Some example embodiments also provide a semiconductor package with improved thermal stability and a method of manufacturing the same.

That is, a semiconductor package according to some example embodiments may be configured such that connection terminals of a top package may all be disposed on a connection substrate and a lower semiconductor chip. Therefore, conductive patterns may redistribute an electrical circuit of the top package and may increase the degree of freedom of wiring between the top package and a bottom package.

In addition, because an additional substrate is not required for redistribution between the bottom package and the top package, the semiconductor package may decrease in thickness. As a result, the semiconductor package may have an overall reduced size. Further, a reduction in total thickness of the semiconductor package may allow the lower semiconductor chip to have an increased thickness, and thus the lower semiconductor chip may advantageously radiate heat. Furthermore, heat generated from the lower semiconductor chip may be discharged out through the conductive patterns, thereby increasing heat radiation.