DISPLAY DEVICE AND METHOD OF MANUFACTURING DISPLAY DEVICE

The technology includes: a substrate; a semiconductor layer on the substrate; gate electrodes; an electrode layer including source electrodes and drain electrodes to form thin film transistors in combination with the semiconductor layer and the gate electrodes; first touch panel lines extending in a first direction; second touch panel lines in the same layer as the first touch panel lines, the second touch panel lines extending in a second direction intersecting the first direction; and connecting sections in a layer other than the layer containing the first touch panel lines and the second touch panel lines, the connecting sections connecting either the first touch panel lines or the second touch panel lines in intersection regions.

TECHNICAL FIELD

The disclosure relates to display devices and methods of manufacturing a display device.

BACKGROUND ART

Patent Literature 1, as an example, discloses a touch-sensor-integrated display device including a thin film transistor array in which a touch sensor is integrated into a thin film transistor (may be referred to as a “TFT”). Patent Literature 1 further discloses a structure of such a touch-sensor-integrated display device where touch panel lines are drawn out in the X- and Y-directions, those routing wires which are arranged in the X-direction overlap gate lines, and those routing wires which are arranged in the Y-direction overlap data lines, in order to increase the precision of touch sensors and prevent aperture ratio decreases.

CITATION LIST

Patent Literature

SUMMARY

Technical Problem

The display device disclosed in Patent Literature 1 however requires a vertical stack of wires and therefore imposes strenuous conditions on manufacturing steps.

The disclosure, in an embodiment thereof, has an object to provide technology, for a touch-sensor-integrated display device, capable of reducing the number of manufacturing steps and lowering manufacturing cost while enhancing touch recognition precision and suppressing aperture ratio decreases.

Solution to Problem

(1) The disclosure is directed to a display device including: a substrate; a semiconductor layer on the substrate; gate electrodes in either one or both of a layer on the semiconductor layer facing the substrate and a layer on the semiconductor layer opposite the substrate; an electrode layer including source electrodes and drain electrodes to form thin film transistors in combination with the semiconductor layer and the gate electrodes; first touch panel lines in a layer opposite the substrate with respect to the thin film transistors, the first touch panel lines extending in a first direction; second touch panel lines in the same layer as the first touch panel lines, the second touch panel lines extending in a second direction intersecting the first direction; and connecting sections in a layer other than the layer containing the first touch panel lines and the second touch panel lines, the connecting sections connecting either the first touch panel lines or the second touch panel lines in intersection regions including locations where the first touch panel lines would intersect the second touch panel lines.

(2) In the display device described in (1) above, the connecting sections are disposed in the same layer as the semiconductor layer.

(3) In the display device described in (2) above, the connecting sections include low-resistance semiconductor regions.

(4) The display device described in (1) above further includes common electrodes in a layer opposite the substrate with respect to the thin film transistors, wherein the connecting sections are disposed in the same layer as the common electrodes.

(5) In the display device described in (1) above, the connecting sections are disposed in the same layer as the gate electrodes.

(6) The display device described in (1) above further includes, in a layer on the semiconductor layer facing the substrate, a conductive light-blocking layer overlapping the semiconductor layer in a plan view, wherein the connecting sections are disposed in the same layer as the light-blocking layer.

(7) In the display device described in (1) above, the connecting sections are disposed in the same layer as the drain electrodes and the source electrodes.

(8) In the display device described in (1) above, either the first touch panel lines or the second touch panel lines include, in the intersection regions, first branch sections extending in a direction other than a direction in which either the first touch panel lines or the second touch panel lines that are connected to the connecting sections extend, and the connecting sections connect either the first touch panel lines or the second touch panel lines via the first branch sections.

(9) In the display device described in (1) above, the connecting sections include, in the intersection regions, second branch sections extending in a direction other than a direction in which either the first touch panel lines or the second touch panel lines that are connected to the connecting sections extend, and the connecting sections connect either the first touch panel lines or the second touch panel lines via the second branch sections.

(10) The display device described in (1) above further includes: gate lines connected to the gate electrodes and extending in the first direction; and source lines connected to the source electrodes and extending in the second direction, wherein the gate lines and the first touch panel lines at least partially overlap in a plan view, and the source lines and the second touch panel lines at least partially overlap in a plan view.

(11) The disclosure is directed also to a method of manufacturing a display device, the method including: forming thin film transistors on a substrate; forming first touch panel lines and second touch panel lines both in a single layer opposite the substrate with respect to the thin film transistors, the first touch panel lines extending in a first direction and the second touch panel lines extending in a second direction intersecting the first direction; and forming connecting sections in a layer other than the layer containing the first touch panel lines and the second touch panel lines, the connecting sections connecting either or both of the first touch panel lines and the second touch panel lines in intersection regions including locations where the first touch panel lines would intersect the second touch panel lines.

Advantageous Effects of Disclosure

The disclosure, in an embodiment thereof, is capable of reducing the number of manufacturing steps and lowering manufacturing cost while enhancing touch recognition precision and suppressing aperture ratio decreases in touch-sensor-integrated display devices.

DESCRIPTION OF EMBODIMENTS

The following will describe illustrative embodiments of the disclosure with reference to drawings. Some of the drawings, showing an X-axis and a Y-axis, are drawn to match the directions indicated by these axes.FIG. 1provides a reference for the vertical (up/down) directions: the top end ofFIG. 1indicates the upward direction whilst the bottom end ofFIG. 1indicates the downward direction. These definitions of directions are for convenience of description only and not intended to limit the orientation of the display device in accordance with the disclosure during the manufacture or use thereof. The same reference numerals in the drawings denote identical or equivalent members, and their description is omitted.

First Embodiment

FIG. 1is a schematic cross-sectional view of a structure of a display device100in accordance with the present embodiment. The display device100is, for example, a liquid crystal panel that has a touch panel function (position-dependent input function) as well as a display function. The display device100displays images using light projected by a backlight device (not shown). Referring toFIG. 1, the display device100includes a first substrate111, a second substrate112, a liquid crystal layer120, a driver130, a circuit board140, and a sealing section150.

The first substrate111is disposed above the backlight device (not shown). The first substrate111of the present embodiment is an array substrate111(wiring board, active matrix substrate) carrying TFTs and various wires (both described later in detail) formed on the top face thereof. The second substrate112of the present embodiment is disposed above the array substrate111, so as to face the array substrate111. The second substrate112is, for example, a CF substrate (opposite substrate) carrying color filters (not shown) and black matrices (not shown) formed on the top face thereof. The array substrate111and the CF substrate112are made of, for example, translucent glass. The array substrate111includes a first polarizer (not shown) on the bottom face thereof. The CF substrate112includes a second polarizer (not shown) on the top face thereof. The first and second polarizers are arranged in a crossed-Nicol position in which their polarization axes are orthogonal to each other.

The liquid crystal layer120is disposed between the array substrate111and the CF substrate112. The liquid crystal layer120contains liquid crystal molecules that change their optical properties under an electric field. The sealing section150is disposed surrounding the liquid crystal layer120between the array substrate111and the CF substrate112, to adhere the array substrate111and the CF substrate112together. The sealing section150is composed, for example, of photocuring resin such as ultraviolet curing resin.

A description will be given next of a structure of the array substrate111.FIG. 2is a top view of the display device100, schematically illustrating wiring on the array substrate111in accordance with the present embodiment.

Referring toFIG. 2, the array substrate111provides, at and around the center thereof, a display area DA where the display device100produces image displays. The array substrate111also provides, in a portion thereof that surrounds the display area DA, a non-display area (frame region NA) where the display device100does not produce image displays. The array substrate111of the present embodiment has larger dimensions than the CF substrate112. The driver130(panel driving component) and the circuit board140(signal transfer member) are provided in a part of the frame region NA outside the CF substrate112in a plan view, to supply various signals related to the display and touch panel functions.

The driver130is built around, for example, an LSI chip that includes a driver circuit therein. The driver130is mounted to the frame region NA by, for example, COG (chip-on-glass) technology, to process the various signals fed from the circuit board140. The driver130of the present embodiment includes first drivers131and second drivers132. The first drivers131are disposed in an end portion of the frame region NA of the array substrate111with respect to a first direction (X-direction) and connected to the circuit board140. The second drivers132are disposed in an end portion of the frame region NA of the array substrate111with respect to a second direction (Y-direction) and connected to the circuit board140.

The circuit board140includes: a base member composed of, for example, an insulating and flexible synthetic resin material such as polyimide resin; and numerous wiring patterns (not shown) formed on the base member. As shown inFIG. 2, the circuit board140of the present embodiment has an end thereof connected to an end portion of the frame region NA of the array substrate111with respect to the Y-direction. The circuit board140has the other end thereof connected to a control board (not shown) serving as a signal source. The various signals supplied from the control board is transferred to the array substrate111via the circuit board140and processed by the driver130in the frame region NA for subsequent output to the display area DA.

The array substrate111of the present embodiment includes on the top face thereof a plurality of gate lines211(scan lines) and a plurality of source lines212(signal lines, data lines). The gate lines211extend in the first direction (X-direction) so as to traverse the display area DA. The source lines212extend in the second direction (Y-direction), which is a direction intersecting the gate lines211, so as to traverse the display area DA. The gate lines211each have an end thereof connected to one of the first drivers131, whereas the source lines212each have an end thereof connected to one of the second drivers132.

Close to each intersection of the gate lines211and the source lines212are there provided a TFT220(switching element) and a pixel electrode230for applying a voltage across the liquid crystal layer120. On the pixel electrode230is provided there a common electrode240having a plurality of slits (openings) formed therethrough. One of the gate lines211is connected to a gate electrode520of the TFT220(described later in detail) in the display area DA. One of the source lines212is connected to a source electrode530of the TFT220(described later in detail) in the display area DA. The common electrodes240of the present embodiment double-function as touch electrodes in a touch panel.

Each pixel electrode230is placed at an electrical potential that is in accordance with a data signal supplied via an associated one of the TFTs220, to generate a fringe field causing rotation of the liquid crystal molecules between the pixel electrode230and the common electrode240. The fringe field changes the retardation caused by the liquid crystal layer120. This mechanism controls the liquid crystal layer120to transmit or block light. The display device100of the present embodiment works with, for example, liquid crystal of FFS (fringe field switching) mode as described here. The display device100may alternatively be a liquid crystal panel that works with a different type of liquid crystal such as liquid crystal of IPS (in-plane switching) mode.

The array substrate111of the present embodiment includes on the top face thereof a plurality of first touch panel lines251and a plurality of second touch panel lines252. The first touch panel lines251and the second touch panel lines252feed signals related to the touch function to the common electrodes240and the driver130. The first touch panel lines251extend in the first direction (X-direction) so as to traverse the display area DA. The second touch panel lines252extend in the second direction (Y-direction), which is a direction intersecting the first touch panel lines251, so as to traverse the display area DA. The first touch panel lines251each have an end thereof connected to one of the first drivers131and connected in the display area DA to one of the common electrodes240, whereas the second touch panel lines252each have an end thereof connected to one of the second drivers132and connected in the display area DA to one of the common electrodes240. Drawing out the first touch panel lines251and the second touch panel lines252in different directions as described here enables every one of the common electrodes240to be connected to a touch panel line, which can enhance the touch recognition precision of the display device100.

A description will be given next of a specific arrangement of the first touch panel lines251and the second touch panel lines252.FIG. 3is a partial top view of a structure, near a pixel region, of the array substrate111in accordance with the present embodiment.FIG. 4is a partial top view of a structure, near an intersection region CA, of the array substrate111in accordance with the present embodiment.

Referring toFIGS. 3 and 4, the first touch panel lines251at least partially overlaps the gate line211in a plan view, whereas the-second touch panel lines252at least partially overlaps the source line212in a plan view. This arrangement can prevent the first touch panel lines251and the second touch panel lines252from blocking the light coming from the backlight, thereby restraining the aperture ratio of the display device100from decreasing.

The first touch panel lines251and the second touch panel lines252of the present embodiment are disposed in the same layer. Each first touch panel line251is connected by a connecting section400in the intersection region CA which contains a location where the first touch panel line251would intersect one of the second touch panel lines252. Specifically, the first touch panel line251extends in the X-direction and terminates before intersecting the second touch panel line252. Across the second touch panel line252, the first touch panel line251extends again in the X-direction. These two parts of the discontinued first touch panel line251, separated by the second touch panel line252, are connected to each other by the connecting section400provided in a layer other than the layer containing the first touch panel lines251and the second touch panel lines252. The intersection region CA refers to a region including: the site (point) where the first touch panel line251, if continuing in the X-direction without terminating, would intersect the second touch panel line252; and an area proximate to the site (point) where there is actually provided no first touch panel line251.

The first touch panel lines251and the second touch panel lines252, when arranged as described here, can be provided in the same layer and still insulated from each other. Therefore, the first touch panel lines251and the second touch panel lines252can be formed simultaneously. The arrangement therefore can reduce the number of manufacturing steps required in the manufacture of the display device100, thereby lowering the manufacturing cost of the display device100.

The display device100of the present embodiment, as described earlier, has a display function of displaying images and a touch panel function of detecting the locations of user inputs on the basis of the displayed images. The array substrate111further includes an integrated touch panel pattern to realize the touch panel function (in-cell technology). The touch panel pattern includes a plurality of common electrodes240(position detecting electrodes) provided in the display area DA on the top face of the array substrate111. As the user moves a position input body (e.g., his/her finger) close to the display area DA of the display device100, the position input body and at least one of the common electrodes240form an electrostatic capacitance therebetween. The display device100then detects, based on the electrostatic capacitance, the positions of inputs made by the user using the position input body.

A description will be given next of a structure in and around the TFT220of the present embodiment.FIG. 5is a cross-sectional view of the structure taken along line V-V shown in FIG.4.

The array substrate111of the present embodiment includes: a semiconductor layer510on the array substrate111; the gate electrodes520in either a layer on the semiconductor layer510facing the array substrate111or a layer on the semiconductor layer510opposite the array substrate111or in both layers; and an electrode layer containing the source electrodes530and drain electrodes540forming the TFTs220when combined with the semiconductor layer510and the gate electrodes520. The array substrate111includes: the first touch panel lines251in a layer opposite the array substrate111with respect to the TFT220; and the second touch panel lines252in the same layer as the first touch panel lines251.

Specifically, as shown inFIG. 5, the array substrate111of the present embodiment includes first gate electrodes521, a first insulating layer551, the semiconductor layer510, a second insulating layer552, second gate electrodes522, a third insulating layer553, and a fourth insulating layer554, all stacked on the top face of the array substrate111in this sequence when viewed from the array substrate111. Each TFT220of the present embodiment is formed by the semiconductor layer510and an electrode layer that in turn includes one of the first gate electrodes521, one of the second gate electrodes522, one of the source electrodes530connected to the semiconductor layer510, and one of the drain electrodes540connected to the semiconductor layer510.

In other words, the TFT220of the present embodiment is a double-gate TFT including: one of the first gate electrodes521in a layer located on the array substrate111side of the semiconductor layer510(i.e., in a layer below the semiconductor layer510); and one of the second gate electrodes522in a layer located on the opposite side of the semiconductor layer510to the array substrate111(i.e., in a layer above the semiconductor layer510). The first gate electrodes521of the present embodiment serve as a light-blocking layer shielding the semiconductor layer510from the light coming from the backlight. A light-blocking layer other than the first gate electrodes521may be provided below the first gate electrodes521. The pattern formed by the first gate electrodes521in the present embodiment may not be necessarily connected to the gate lines211and the second gate electrodes522. Accordingly, the TFT220may be a top-gate TFT in which the second gate electrode522alone serves as a gate electrode, in which case the pattern formed by the first gate electrodes521in the present embodiment serves as a light-blocking layer. As another alternative, the TFT220may be a bottom-gate TFT.

The semiconductor layer510is disposed on the first insulating layer551so as to vertically overlap the first gate electrodes521in a plan view. The second gate electrodes522are disposed on the second insulating layer552so as to vertically overlap the semiconductor layer510in a plan view. The first insulating layer551and the second insulating layer552hence serve as gate insulating layers. The second gate electrodes522are formed by parts of the gate lines211. The gate lines211and the second gate electrodes522are mutually connected.

In the TFT220of the present embodiment, the semiconductor layer510, the source electrodes530, and the drain electrode540are integrally formed of the same semiconductor material. The source electrodes530and the drain electrodes540(at least the top faces thereof) are subjected to a resistance-reducing process. This process renders the source electrodes530and the drain electrodes540more electrically conductive than the semiconductor layer510serving as channel sections of the TFTs220. The semiconductor material processed for increased conductance as described here will be referred to as a low-resistance semiconductor, and the parts of an integrally fabricated semiconductor material that have a low resistance will be referred to as low-resistance semiconductor regions. The source electrodes530and the drain electrodes540may be provided separately from the semiconductor layer510. In other words, the source electrodes530and the drain electrodes540may be formed of a metal or like conductive material separately from the semiconductor layer510.

The array substrate111of the present embodiment includes the source lines212disposed in the same layer as the first gate electrodes521. The source lines212are connected to the source electrodes530via a first wiring layer561. The first wiring layer561is connected to the source lines212inside contact holes CH1formed through the first insulating layer551, the third insulating layer553, and the fourth insulating layer554on the source lines212and also connected to the source electrodes530inside contact holes CH2formed through the third insulating layer553and the fourth insulating layer554on the source electrodes530.

On the drain electrodes540of the present embodiment are there provided a second wiring layer562and the pixel electrodes230. The drain electrodes540are connected to the pixel electrodes230via the second wiring layer562. The second wiring layer562is connected to the drain electrodes540inside contact holes CH3formed through the third insulating layer553and the fourth insulating layer554on the drain electrodes540. The pixel electrodes230are provided on the second wiring layer562so as to cover the second wiring layer562. The pixel electrodes230may be connected directly to the drain electrodes540with no second wiring layer562intervening therebetween.

The first touch panel lines251and the second touch panel lines252of the present embodiment are at least partially disposed in the same layer. In other words, the first touch panel lines251and the second touch panel lines252are at least partially disposed on the fourth insulating layer554. The first touch panel lines251at least partially vertically overlap the gate lines211in a plan view. The second touch panel lines252at least partially vertically overlap the source lines212in a plan view.

The array substrate111of the present embodiment further includes the common electrodes240in a layer opposite the substrate with respect to the TFTs220. Specifically, as shown inFIG. 5, a fifth insulating layer555is disposed above the first touch panel lines251, the second touch panel lines252, the first wiring layer561, and the second wiring layer562. The common electrodes240are disposed above the fifth insulating layer555. This structure insulates the common electrodes240from the first touch panel lines251, the second touch panel lines252, the first wiring layer561, and the second wiring layer562.

A description will be given next of a structure of the connecting sections400.FIG. 6is a cross-sectional view of the structure taken along line VI-VI shown inFIG. 4.FIG. 7is a cross-sectional view of the structure taken along line VII-VII shown inFIG. 4.

Referring toFIGS. 6 and 7, the connecting sections400of the present embodiment are provided in a layer other than the layer containing the first touch panel lines251and the second touch panel lines252. The connecting sections400connect the first touch panel lines251in the intersection regions CA. Each connecting section400includes a first connecting section401and a second connecting section402.

Specifically, as shown inFIG. 6, the first connecting section401of the present embodiment is at least partially disposed in the same layer as the common electrodes240. In other words, the first connecting section401is at least partially disposed on the fifth insulating layer555. The first connecting section401connects the two parts of the first touch panel line251discontinued in the intersection region CA to each other inside contact holes CH4and CH5formed through the fifth insulating layer555.

The first connecting section401is formed simultaneously with the common electrodes240. The first connecting section401can therefore be formed with no additional manufacturing steps. As described earlier, the first connecting section401is provided in a layer other than the layer containing the first touch panel lines251and the second touch panel lines252. Therefore, the first touch panel lines251and the second touch panel lines252are insulated from each other even if the first touch panel lines251and the second touch panel lines252are disposed in the same layer.

The first touch panel lines251of the present embodiment is connected also by the second connecting section402in the intersection region CA as shown inFIGS. 4 and 7. Specifically, each first touch panel line251of the present embodiment includes, in the intersection region CA, a first branch section253extending in a direction other than the direction in which the first touch panel line251extends. The second connecting section402connects the discontinued first touch panel line251via these first branch sections253.

More specifically, as shown inFIG. 4, the first touch panel line251of the present embodiment includes a pair of first branch sections253extending in the second direction (Y-direction) in the intersection region CA where the first touch panel lines251would intersect the second touch panel line252. The second connecting section402, as shown inFIG. 7, is disposed in the same layer as the source electrode530and the drain electrode540. Specifically, the second connecting section402is disposed in the same layer as the source electrode530and the drain electrode540and in such a manner that the second connecting section402does not overlap the gate line211including the second gate electrode522. The pair of first branch sections253is connected to the second connecting section402inside contact holes CH6and CH7formed through the third insulating layer553and the fourth insulating layer554on the second connecting section402. This arrangement connects together the two parts of the first touch panel line251discontinued in the intersection region CA. The source electrodes530, the drain electrodes540, and the second connecting sections402are formed simultaneously. The second connecting sections402can therefore be formed with no additional manufacturing steps.

As described here, the first touch panel lines251of the present embodiment are connected in the intersection region CA by the two connecting sections400(i.e., the first connecting section401and the second connecting section402). This structure enables the connecting section400to more reliably connect the two parts of the first touch panel line251discontinued in the intersection region CA. In addition, the structure can suppress decreases in touch recognition precision because the electric resistance of the connecting section400can be reduced even if the first touch panel lines251are connected by the connecting section400in the intersection region CA.

The connecting section400may alternatively connect the second touch panel lines252in the intersection region CA. In other words, the second touch panel lines252may terminate in the intersection region CA where the second touch panel lines252would intersect the first touch panel lines251. The connecting section400may connect two parts of the second touch panel line252discontinued in the intersection region CA to each other. As another alternative, the connecting section400may include either one of the two connecting sections400(i.e., either one of the first connecting section401and the second connecting section402). For instance, in vary small pixels, it may be difficult to provide the first connecting section401and at the same time secure a sufficient area in the common electrodes240for the provision of slits (openings) for generating a fringe field. If the second connecting section402is formed by subjecting a semiconductor film to a resistance-reducing process using the second insulating layer552and the gate lines211including the second gate electrodes522as a mask as will be detailed later, the pattern of the second connecting section402, formed so as to overlap the gate lines211, has a resistance that cannot be reduced, and the connecting section400consequently has an increased resistance. In these cases, either one of the first connecting section401and the second connecting section402may entirely constitute the connecting section400. If the connecting section400includes only either one of the connecting sections400(i.e., either one of the first connecting section401and the second connecting section402), the connecting section400may have its width increased to reduce resistance thereof. For instance, if the connecting section400includes only the first connecting section401, the first connecting section401may have its width so increased that the first connecting section401would reach the region where the second connecting section402was formed (seeFIG. 3).

The semiconductor layer510, the source electrodes530, and the drain electrodes540are integrally formed in the present embodiment as described earlier. The second connecting sections402are therefore disposed in the same layer as the semiconductor layer510. Also as described earlier, the source electrodes530and the drain electrodes540of the present embodiment are formed of a low-resistance semiconductor. The second connecting section402therefore includes a low-resistance semiconductor region. Specifically, the second connecting section402, so disposed as not to overlap the gate lines211including the second gate electrodes522, has at least a low-resistance semiconductor region.

The connecting sections400may be disposed in the same layer as the gate electrodes520. The connecting sections400may alternatively be disposed in the same layer as the light-blocking layer. These structures also enable the connecting section400to connect the first touch panel lines251or the second touch panel lines252in the intersection region CA. The structures enable the formation of the connecting sections400with no additional manufacturing steps.

A description will be given next of a method of manufacturing the display device100in accordance with the present embodiment.FIG. 8is a diagram representing a flow of manufacturing of the display device100in accordance with the present embodiment.

A method of manufacturing a display device100in accordance with the present embodiment involves: forming TFTs220on a substrate; forming first touch panel lines251and second touch panel lines252both in a single layer on the TFTs220opposite the substrate such that the first touch panel lines251extend in a first direction and the second touch panel lines252extend in a second direction intersecting the first direction; and forming connecting sections400in a layer other than the layer containing the first touch panel lines251and the second touch panel lines252, the connecting sections400connecting either or both of the first touch panel lines251and the second touch panel lines252in intersection regions CA including locations where the first touch panel lines251would intersect the second touch panel lines252.

Specifically, a first conductive film is first formed on the first substrate (array substrate)111by, for example, sputtering and subjected to photolithography using a photomask to form a photoresist pattern. The first conductive film is then etched into a pattern using the photoresist pattern as a mask. The photoresist pattern is then removed, leaving the first gate electrodes521(light-blocking layer) and the source lines212(step S1).

Next, the first insulating layer551is formed on the first gate electrodes521(light-blocking layer) and the source lines212by, for example, CVD (chemical vapor deposition). A semiconductor film is then formed by sputtering and subsequently subjected to photolithography using a photomask to form a photoresist pattern. The semiconductor film is then etched into a pattern using the photoresist pattern as a mask. The photoresist pattern is removed, leaving the semiconductor layer510(step S2). The semiconductor layer510of the present embodiment is formed of, for example, an oxide semiconductor such as InGaZnO.

Next, the second insulating layer552is formed on the semiconductor layer510by CVD. A second conductive film is then formed by sputtering and subjected to photolithography using a photomask to form a photoresist pattern. The second conductive film is then etched into a pattern using the photoresist pattern as a mask to form the gate lines211including the second gate electrodes522(step S3). The second insulating layer552is subsequently etched into a pattern using the same photoresist pattern. Thereafter, the photoresist pattern is removed.

Next, a semiconductor film formed integrally with the semiconductor layer510is subjected to a resistance-reducing process using the second insulating layer552and the gate lines211including the second gate electrodes522as a mask, to form the drain electrodes540, the source electrodes530, and the second connecting sections402(step S4). A resistance-reducing process, for example, reduces oxygen in the surface of the semiconductor layer510by plasma processing in a hydrogen atmosphere, thereby lowering the resistivity of the surface, to improve conductance. These manufacturing steps form, on the array substrate111, the TFTs220including the semiconductor layer510, the gate electrodes520, the source electrodes530, and the drain electrodes540.

The semiconductor layer510may be formed of a different semiconductor material such as polysilicon. If the semiconductor layer510is formed of polysilicon, the drain electrodes540, the source electrodes530, and the second connecting sections402are formed by doping the polysilicon with, for example, an impurity such as phosphorus or boron to reduce the resistance of the polysilicon.

Next, the third insulating layer553is formed on the second gate electrodes522and the gate lines211by CVD. A photosensitive organic film material is then applied onto the third insulating layer553by, for example, spin- or slit-coating and patterned by photolithography using a photomask to form the fourth insulating layer554. This manufacturing step forms an insulating layer on the TFTs220(step S5). The third insulating layer553is then etched using the pattern of the fourth insulating layer554to form contact holes through the third insulating layer553. Thereafter, the first insulating layer551and the third insulating layer553are etched using the same pattern of the fourth insulating layer554, to form the contact holes CH1, CH2, CH3, CH6, and CH7.

Next, a third conductive film is formed on the fourth insulating layer554by sputtering and subjected to photolithography using a photomask to form a photoresist pattern. The third conductive film is then etched into a pattern using the photoresist pattern as a mask. The photoresist pattern is removed, simultaneously forming the second touch panel lines252, the first wiring layer561, the second wiring layer562, and the first touch panel lines251including the first branch sections253(step S6). The first touch panel lines251are formed so as to terminate in the intersection regions CA including locations where the first touch panel lines251would intersect the second touch panel lines252. The first touch panel lines251are however connected to the second connecting sections402inside the contact holes CH6and CH7. Therefore, the two parts of the first touch panel line251discontinued in the intersection region CA are connected to each other by the second connecting section402.

The source lines212, the gate lines211, the first touch panel lines251, the second touch panel lines252, the first wiring layer561, and the second wiring layer562may be formed of, for example, a metal such as copper, titanium, aluminum, molybdenum, or tungsten or an alloy of these metals.

Subsequently, a first transparent conductive film is formed on the second wiring layer562by sputtering and subjected to photolithography using a photomask to form a photoresist pattern. The first transparent conductive film is then etched into a pattern using the photoresist pattern as a mask. The photoresist pattern is removed, leaving the pixel electrodes230(step S7). The fifth insulating layer555is then formed on the first touch panel lines251, the second touch panel lines252, the first wiring layer561, and the pixel electrodes230by CVD.

Thereafter, the contact holes CH4and CH5are formed through the fifth insulating layer555. A second transparent conductive film is formed by sputtering and subjected to photolithography using a photomask to form a photoresist pattern. The second transparent conductive film is then etched into a pattern using the photoresist pattern as a mask. The photoresist pattern is removed, simultaneously forming the first connecting sections401and the common electrodes240. The two parts of the first touch panel line251discontinued in the intersection region CA are consequently connected to each other by the first connecting section401inside the contact holes CH4and CH5.

The first to fifth insulating layers551,552,553,554, and555may be formed of, for example, a film of an inorganic material such as silicon nitride (SiNX) or silicon oxide (SiO2) or a stack of such films. The first connecting sections401, the pixel electrodes230, and the common electrodes240may be formed of, for example, a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or tin oxide (SnO) or an alloy of these metals.

In the display device100of the present embodiment, the first touch panel lines251and the second touch panel lines252, arranged as described here, can be simultaneously formed without being connected to each other. The two parts of the first touch panel line251discontinued in the intersection region CA are connected to each other by the first connecting section401and the second connecting section402provided in a layer other than the layer containing the first touch panel lines251and the second touch panel lines252. The first connecting sections401are formed simultaneously with common electrodes. The second connecting sections402are formed simultaneously with the source electrodes530and the drain electrodes540. The connecting sections400can therefore be formed with no additional manufacturing steps. Hence, the number of manufacturing steps required for the manufacture of the display device100can be reduced, which in turn lowers the manufacturing cost of the display device100.

Second Embodiment

Next, a second embodiment will be described. The following description will focus on differences from the first embodiment and may not mention features that are common to both the first and second embodiments. The second embodiment differs from the first embodiment in the structure of the TFTs220and the connecting sections400.

FIG. 9is a partial top view of a structure, near an intersection region CA, of an array substrate111in accordance with the second embodiment.FIG. 10is a cross-sectional view, taken along line X-X shown inFIG. 9, of a structure of the TFTs220in accordance with the second embodiment.FIG. 11is a cross-sectional view taken along line XI-XI shown inFIG. 9.

Referring toFIG. 10, the array substrate111of the present embodiment includes gate electrodes520, a first insulating layer551, and a semiconductor layer510, all stacked on the top face of the array substrate111in this sequence when viewed from the array substrate111. The semiconductor layer510is connected to source electrodes530and drain electrodes540. The gate electrodes520are connected to gate lines211disposed in the same layer as the gate electrodes520. The TFTs220of the present embodiment are, as described here, bottom-gate TFTs including the gate electrodes520in a layer located on the array substrate111side of the semiconductor layer510(i.e., in a layer below the semiconductor layer510).

As shown inFIG. 9, each first touch panel line251is disposed so as to at least partially overlap one of the gate lines211in a plan view, whereas each second touch panel line252is disposed so as to at least partially overlap one of the source lines212in a plan view. The first touch panel line251terminates before intersecting the second touch panel line252. Across the second touch panel line252, the first touch panel line251extends again in the X-direction. These two parts of the discontinued first touch panel line251, separated by the second touch panel line252, are connected to each other by a first connecting section401and a third connecting section403provided in a layer other than the layer containing the first touch panel lines251and the second touch panel lines252. The first connecting section401has the same structure as in the first embodiment, and its description is omitted.

Referring toFIG. 9, the first touch panel line251of the present embodiment includes a pair of first branch sections253extending in the Y-direction. The third connecting section403is disposed in the same layer as the gate electrode520(gate line) as shown inFIG. 11. The pair of first branch sections253is connected to the third connecting section403inside contact holes CH6and CH7formed through the first insulating layer551, the third insulating layer553, and the fourth insulating layer554on the third connecting section403. This arrangement connects together the two parts of the first touch panel line251discontinued in the intersection region CA.

The first touch panel lines251and the second touch panel lines252, arranged as described here, can be provided in the same layer without being connected to each other even in a structure where the connecting sections400are provided in the same layer as the gate electrodes520(gate lines). The first touch panel lines251and the second touch panel lines252can therefore be simultaneously formed. In addition, the third connecting sections403can be formed simultaneously with the gate electrodes520. Hence, the number of manufacturing steps required for the manufacture of the display device100can be reduced, which in turn lowers the manufacturing cost.

Variation Examples

Main embodiments of the disclosure have been described so far. The disclosure is however not limited to these embodiments.

The first touch panel lines251are described in the foregoing embodiments as including the first branch sections253. The connecting sections400connect the first touch panel lines251in the intersection regions CA via the first branch sections253. Alternatively, the first touch panel lines251may include no first branch sections253, so that the first connecting sections401instead include second branch sections. Specifically, each first connecting section401may include on each X-direction end thereof a second branch section extending in the Y-direction, in which case the two parts of the first touch panel line251discontinued in the intersection region CA are connected together via the second branch section of the first connecting section401.

The first connecting sections401, each constituting a part of the connecting section400, are described in the foregoing first embodiment as being disposed in the same layer as the common electrodes. The second connecting sections402, each constituting a part of the connecting section400, are described in the first embodiment as being disposed in the same layer as the source electrodes530and the drain electrodes540. The third connecting sections403, each constituting a part of the connecting section400, are described in the foregoing second embodiment as being disposed in the same layer as the gate electrodes520(gate lines). The connecting sections400of the disclosure do not necessarily have such a structure. The connecting sections400may be disposed, for example, in the same layer as the source lines (signal lines, data lines).

The TFT220is described as being a double-gate TFT in the foregoing first embodiment and as being a bottom-gate TFT in the foregoing second embodiment. As a further alternative, the TFT220of the disclosure may be a top-gate TFT. In such cases, the TFT220may include a light-blocking layer shielding the semiconductor layer510from the light coming from the backlight, and the connecting sections400may be disposed in the same layer as the light-blocking layer.

The elements and devices described in the embodiments and variation examples above may be combined in a suitable manner.