Synchronverter power control during unbalanced grid conditions

Methods and systems for a synchronverter power control during unbalanced grid conditions is disclosed. The system includes a synchronverter coupled with a power supply grid, a power reference generator, configured to receive a terminal voltage measurement vector vt and a current measurement vector i from the synchronverter, and generate an active power Pf and a reactive power Qf, a synchronverter control unit connected to the power reference generator and configured to process the active power Pf and the reactive power Qf and generate an electromotive force (EMF) vector e, and an active and reactive power control unit, connected between the synchronverter control unit and the synchronverter, configured to receive the electromotive force (EMF) vector e and the terminal voltage measurement vector vt, and regulate the current measurement vector i to eliminate power oscillations and current harmonics in the synchronverter during unbalanced grid conditions.

TECHNICAL FIELD

The present disclosure relates to inverters and, more specifically, relates to a synchronverter power control during unbalanced grid conditions.

BACKGROUND

Standard inverters are known to be having low inertia. If there are faults or sudden changes in load leading to transient periods, the standard inverters follow changes rapidly. As a result, grids taking support of the standard inverters may experience a worser condition. To overcome the deficiencies of standard inverters, Synchronverters (SVs) are introduced. The SVs are inverters with defined control strategy to behave as synchronous generators (SGs) to avoid traditional inverters' unwanted low inertia behaviors. The SVs may operate in a connected mode or in an islanded mode from a hosting power grid. However, generic SVs are not capable of providing safe and reliable operation during unbalanced faults or grid conditions. Consequently, the SVs may generate currents that may exceed their nominal values, inject active and reactive power with oscillations at twice the grid's fundamental frequency.

SUMMARY

In one aspect of the present disclosure, a system for synchronverter power control during unbalanced grid conditions is disclosed. Methods and systems for a synchronverter power control during unbalanced grid conditions is disclosed. The system includes a synchronverter coupled with a power supply grid, a power reference generator, configured to receive a terminal voltage measurement vector vtand a current measurement vector i from the synchronverter, and generate an active power Pfand a reactive power Qf, a synchronverter control unit connected to the power reference generator and configured to process the active power Pfand the reactive power Qfand generate an electromotive force (EMF) vector e, and an active and reactive power control unit, connected between the synchronverter control unit and the synchronverter, configured to receive the electromotive force (EMF) vector e and the terminal voltage measurement vector vt, and regulate the current measurement vector i to eliminate power oscillations and current harmonics in the synchronverter during unbalanced grid conditions.

In another aspect, a method for synchronverter power control is disclosed. The method includes electrically coupling a synchronverter coupled with a power supply grid, generating an active power Pfand a reactive power Qfthrough a power reference generator based on a terminal voltage measurement vector vtand a current measurement vector i from the synchronverter, generating an electromotive force (EMF) vector e through a synchronverter control unit by processing an active power Pfand a reactive power Qf, and regulating the current measurement vector i to eliminate power oscillations and current harmonics in the synchronverter during unbalanced grid conditions through an active and reactive power control unit, based on the electromotive force (EMF) vector e and the terminal voltage measurement vector vt.

The foregoing as well as other features and advantages of the present disclosure will be more fully understood from the following description, examples, and claims.

It should be appreciated by those skilled in the art that any diagram herein represents conceptual views of illustrative systems embodying the principles of the present disclosure.

DETAILED DESCRIPTION

Reference will now be made in detail to specific embodiments or features, examples of which are illustrated in the accompanying drawings. A skilled artisan will appreciate that various alternate embodiments and forms may be prepared. Examples, therefore, given are only for illustration purposes without any intention to restrict the embodiments to a given set of examples. Specific functional aspects are provided merely to enable a person skilled in the art to perform the invention and should not be construed as limitations of the invention. Any method steps, and processes described herein are not to be construed as necessarily requiring their performance in the particular order discussed or illustrated, unless specifically identified as an order of performance. It is also to be understood that additional or alternative steps may be employed, unless otherwise indicated.

The use of the singular herein includes the plural (and vice versa) unless specifically stated otherwise. The use of the terms “include,” “includes”, “including,” “have,” “has,” or “having,” “comprise,” “comprises,” “comprising” or the like should be generally understood as open-ended and non-limiting unless specifically stated otherwise. It is understood that the order of steps or order for performing certain actions can be changed so long as the intended result is obtained. Moreover, two or more steps or actions may be conducted simultaneously. As used herein, the term “about” or “between” refers to a ±20% to ±10% variation from the nominal value unless otherwise indicated.

Embodiments of the present disclosure are directed to methods and systems for synchronverter power control during unbalanced grid conditions. The disclosure may equip the Synchronverters (SVs) with fault ride-through (FRT) units to avoid any adverse impact of unbalanced grid conditions and maintain a reliable SV operation. The FRT units are configured to eliminate active and reactive power oscillations problems and ensure current generation is within the defined inverter ratings. The FRT units maintain SVs' intrinsic features, guarantee a seamless transition during faults, and facilitate SVs integration in microgrids.

FIG.1(a)andFIG.1(b)illustrate a known Synchronverters (SVs) topology.FIG.1(a)is a three-phase inverter connected to a hosting grid at a point of common coupling (PCC). Elements shown inFIG.1(a): Rs, Lsand Csrepresent an interfacing filter's resistive, inductive, and capacitive components, respectively. Further, Vg, Rg, and Lgare an equivalent grid voltage magnitude, resistance, and inductance, respectively. SV control unit (illustrated inFIG.1(b)) is configured to receive a terminal voltage measurement vector vt, and a current measurement vector i to produce an electromotive force (EMF) vector ‘e’ that is normalized to generate a pulse width modulation (PWM) signals to operate the inverter switches102. In an example, a PWM circuit104may be used to generate the PWM signals. The vector e may have a magnitude ‘E’ that is regulated through a reactive power loop and an active power loop. E is represented by:
E=Mfif{dot over (θ)};  (1)
where Mfifis the virtual mutual field multiplied by the virtual field current. The Mfifis determined by following equation:

Mf⁢if=1K⁢s[Qs⁢e⁢t-Q+Dq(E*-Vt)];(2)
where Vtis vtmagnitude, K is a reactive power regulating coefficient, Qsetis a setpoint for a reactive power, Q is a produced reactive power by the SV, Dqis a voltage droop coefficient that regulates Q generation for a specific change in Vt, and E* is a voltage magnitude setpoint. The produced Q and Dqare provided by:

On the other hand, SV angular frequency {dot over (θ)} is regulated by the following equation:

θ˙=1J⁢s[Ps⁢e⁢tθ.*-Te-Dp(θ˙*-θ˙)];(5)
where Psetis an active power setpoint, {dot over (θ)}* is the angular frequency setpoint, J is a virtual inertia, Teis an electromagnetic torque, and Dpis a frequency droop coefficient. Dq, Dpstimulates the SV to generate a certain amount of Tedenoted as ΔTeand thus active power for each specific change in {dot over (θ)} denoted as Δ{dot over (θ)} as shown below as:

Te=Mf⁢if⁢〈i,θ〉(6)Dp=-Δ⁢TeΔ⁢θ.;(7)
whereθ is a balanced three-phase sinusoidal. The e vector is represented as:
e=Eθ(8)

The SV control unit as illustrated inFIG.1(b)includes a controller120which is implemented based at least in part on Equations (3), (6) and (8). It is apparent that the SV holds a controlled voltage source model with a magnitude E that and phase9that are dependent on Psetand Qsetvalues. Also, it can be seen fromFIG.1(b)that the current generation is not bounded by limits or controlled directly through a control loop to follow a pre-defined value. Thus, a positive sequence model is a controlled voltage source in series with an impedance, and a negative sequence is a same impedance used for the positive sequence, as illustrated inFIG.2(a).FIG.2(a)includes a controller220that is substantially similar to the controller120and implements the logic based at least in part upon Equations (3), (6) and (8). If the SV is under a fault condition, the periodic component of the current flowing in phase a is expressed:

ia=Ea⁢∠⁢θ-Vt⁢a⁢∠⁢θtZs⁢∠⁢θs(9)
where θt, Zs, and θsare a terminal voltage phase, a filter impedance magnitude, and an angle, respectively. From equation (9), it is apparent that the current depends on the voltage difference between SV and the measured Vta∠θtas well as the filter impedance Zs∠θs. Thus, the current may exceed the inverter's ratings and an interfacing filter during unbalanced conditions, which raises a requirement for limiting the current to avoid any damages.

According to instantaneous power theory, SVs generated P and Q are expressed as
P=vt·i
Q=vt⊥·i(10)
where the operator (.) may represent the dot product of vectors, and the subscript (⊥) may denote the orthogonal version of vt. Both vtand i may be redefined by applying symmetrical component theory as given by:
vt=vt+vt−
i=i++i−(11)
The superscripts (+) and (−) refer to positive and negative sequence components, respectively. By substituting (11) in (10), P and Q are rewritten as:
P=vt+·i++vt−·i−+vt+·i−+vt−·i+(12)
Q=vt⊥+·i++vt⊥−·i−+vt⊥+·i−+vt⊥−·i+(13)

Each of (12) and (13) include two terms, a constant term that is a result of vtand i interaction from a same sequence and an oscillatory term results from the v and i interaction from different sequences. The terms P and Q are defined as:
Ps=vt+·i++vt−·i−(14)
{tilde over (P)}=vt+·i−+vt−·i+(15)
P=Ps+{tilde over (P)}(16)
Qs=vt⊥+·i++vt⊥−·i−(17)
{tilde over (Q)}=vt⊥+·i−+vt⊥−·i+(18)
Q=Qs+{tilde over (Q)}(19)
where Psis a constant term of P which is usually equal to the active power setpoint, i.e., Pset. The Qsis a constant term of Q, which is equal to the reactive power setpoint Qset. The oscillatory terms of P and Q are {tilde over (P)} and {tilde over (Q)}, respectively, having a zero-mean value. During unbalanced conditions, the {tilde over (P)} and {tilde over (Q)} are not null since the negative sequence components of vtand i exist. As a result, it may be required to mitigate the effect of unbalanced grid conditions by reducing/eliminating {tilde over (P)} and {tilde over (Q)}.

The problem of power oscillations and overcurrent generation is resolved for SVs as described henceforth. To significantly eliminate {tilde over (P)} and {tilde over (Q)}, an instantaneous active and reactive power control (IARC) technique may be used. If i aligns with the vtleads to P generation. Conversely, the Q generation is performed when the i aligns with the vt⊥. This concept is used to form the reference current that is essential to achieve IARC as following:
i*=ip*+iq*(20)
where i* is the three-phase reference current that performs the IARC function. ip* is a three-phase component of i that is responsible for P generation. Similarly, ig* is responsible for Q generation. ip*, and iq* are expressed as:
ip*=g*vt(21)
ig*=b*vt⊥(22)

where g and b are the instantaneous conductance and susceptance, respectively. For SVs, g and b can be defined as:
g=Ps/|vt|2(23)
b=Qs/|vt|2(24)
|vt|2=|vt+|2+|vt−|2+2|vt+∥vt−|cos(2ωt+ϕ++ϕ−)  (25)
where ϕ+and ϕ−are the phases of vt+and vt−, respectively. Based on the equations (20)-(24), the reference current that achieves IARC for SVs can be written as

From the equation (26), i* depends on Psand Qsthat are generated internally in the SV unit, which is explained in the methodology section. Also, it is well known that the IARC has a trade-off between the oscillations and the generated current quality due to the existence of a cosine term in the denominator. Allowing the complete existence of the cosine term gives the highest degree of eliminating the oscillations. However, the corresponding generated current includes higher-order harmonic components, mainly the third harmonic component. This third harmonic component may be avoided by eliminating the cosine term, which leads to an average active and reactive power control (AARC) methods that ensures the delivery of Psand Qsequal to their corresponding setpoints, i.e., Psetand Qset, respectively. ip* and iq* for AARC are defined as:
ip*=G*vt(27)
iq*=B*vt⊥(28)
where G and B are the average value of the conductance and susceptance, respectively. The G and B are constant during unbalanced grid conditions since they do not exhibit oscillations as their instantaneous counterparts g and b. The G and B are given by:
G=Ps/vtΣ2(29)
B=Qs/vtΣ2(30)
vtΣ=√{square root over (|vt+|2+|vt−|2)}  (31)

With vtΣ, which is the collective RMS value of vt, the AARC reference current is expressed as:

The reference current provided in the equation (32) prevents the generation of higher-order components of the current; thus, resulting in a sinusoidal current generation. Also, the reference current in (32) is identical to (26) if the cosine term is removed.

The IARC and AARC may be concluded as a relation between the power oscillations that adversely affect the current quality. As described, the higher the oscillations are eliminated, the higher the current is distorted. Therefore, a comprehensive IARC (C-IARC) is described in the disclosure to eliminate the oscillations without affecting the current or its quality. The C-IARC as described herein is developed in an αβ frame. vtcan be represented in the αβ frame as follows:

[vαvβ]=23[1-1212032-32][vtavt⁢bvt⁢c](33)
where vta, vtb, and vtc, are the abc quantities of vt, respectively. vαand vβare the αβ frame quantities of vt, respectively. C-IARC involves the modification of the instantaneous power theory to avoid the drawbacks of IARC and AARC. The following expressions are express original instantaneous power theory and the modified instantaneous power theory, the active-power P and the reactive-power Q are defined by:

Equation (35) is the modified instantaneous power theory to estimate P and Q. Term {circumflex over (v)}ais a π/2 delayed version of vαwhile {circumflex over (v)}βis a π/2 advanced version of vβ. The aforementioned delay can be achieved by using a compensation filter with a transfer function defines as:

The quantity ωdrepresents the delayed quantity frequency and ωcis the filter cut-off frequency. ξ is the filter damping, which can be set as 1 to ensure good filter damping. The Fd(s) delays vαby π/2 and the same Fd(s) can advanced {circumflex over (v)}βby multiplying by (−1) as following:
{circumflex over (v)}α=vaFd(S)  (37)
{circumflex over (v)}62=−vβFd(S)  (38)

Consequently, the reference current αβ frame quantities {circumflex over (ι)}α* and {circumflex over (ι)}β* to perform the C-IARC can be derived as:

The {circumflex over (ι)}α(p)* and {circumflex over (ι)}β(p)* are responsible for generating Pswhile {circumflex over (ι)}α(q)* and {circumflex over (ι)}β(q)* are on the other hand, responsible for generating Qs. Each sub-component of {circumflex over (ι)}α* and {circumflex over (ι)}β* based in (39) are formulated as

The reference currents described in equations (26), (32), and (40) achieve different FRT strategies. The C-IARC outperforms both the IARC and AARC. However, all of the aforementioned strategies have a common drawback; the unlimited current generation may lead to inverter damages. This damages may be prevented by having a current limiter. The current limiter may be designed by modifying Psetand Qsetto a form that ensures active and reactive power delivery during normal conditions and limited current generation during unbalanced grid conditions. As described earlier the Psand the Qsare equal to the Psetand the Qsetduring normal and abnormal conditions. During unbalanced conditions, SVs generate high currents to compensate for the voltage drop. This high current ensures the generated P and Q are equal to Psetand Qset. Therefore, the inverter is subjected to damages due to the high current generation. In conclusion, changing Psetand Qsetto lower values may reduce the values of Psand Qslower, and thus the generated current may be lower since the Psand Qstracks the reference current of Equations (26), or (32), or (40), which all are affected by the value of Psand Qs. The new active power setpoint Pfand reactive power setpoint Qfare derived as:

Pf=32⁢Vd⁢Id(41)Qf=-32⁢Vd⁢Iq
where Vd, Id, and Iqare the d axis vtcomponent, and dq axis components of i, respectively. During faults, the quantity Vdis represented as:
Vd=(V+−V−)  (42)

Also, Id, and Iqmay be defined as a function of a maximum peak current Imaxas:
Id=Imaxcos(θi)
Iq=Imaxsin(θi)  (43)
where θiis the angle of a required power factor. This new set of power references ensures the current does not exceed the pre-defined limit Imaxas demonstrated in the results sections.

The IARC, AARC, and C-IARC may be added in series to the generic SVs control unit. This configuration allows SVs to maintain their intrinsic features and guarantee a seamless transition without any switching to achieve a fault ride-through (FRT). As explained, IARC and AARC may be formulated and designed jointly.

FIG.3a-FIG.3dshow the block diagram of a SV control unit designed with IARC and AARC strategies.FIG.3(a)is a power reference generator to limit current that generates Pfto replace Pset, and Qfto replace Qset. The current limiter ofFIG.3(a)includes a sequence extractor302filters the vtand computes a positive sequence component vt+and a negative sequence component vt−. A magnitude detector304coupled to the sequence extractor receives the positive sequence component vt+and the negative sequence component vt−to obtain a positive vtmagnitude (Vt+) and a negative vtmagnitude (Vt−). The positive vtmagnitude (Vt+) and a negative vtmagnitude (Vt−) are provided to an adder306to generate Vd. The Vdis input to a multiplier308that multiplies 1.5 (3/2) to the Vd.

Further, a maximum peak current reference input312is provided to a d axis vtcomponent generator314that generates Id, and Iqbased on Equation (43). The Idis provided to a multiplier310that multiplies Idwith product of the Vdand 1.5 to generate Pfas provided in Equation (41). Further, Iqis multiplied with −1 by a multiplier316and provided to a multiplier318. The multiplier318multiplies −Iqwith the product of the Vdand 1.5 to generate Qfas provided in Equation (41).

The power references replacement ensures the required power delivery during normal conditions is identical if Psetand Qsetare used. Also, Pfand Qfmaintain the peak current during faults below a specific limit. Thus, Pfand Qfmay lead to a safe current generation and a reliable operation during normal and unbalanced conditions.FIG.3(b)is a known generic SV control unit serially coupled to the current limiter and receives Pfand Qfto produce e. The generic SV control unit includes a controller320that is substantially similar to the controllers120and220, and implements the logic based at least in part upon Equations (3), (6) and (8). The generic SV control unit may be modified by adding a switch to disable the voltage droop relation since the SV operates in a grid-connected mode of operation. Also, leaving the added switch close may lead to unwanted reactive current generation during the faults.

For a traditional converter, IARC or AARC may be achieved by replacing Psand Qsin equations (26) and (32) by the active power and reactive power setpoints that deliver a required amount of power. For the SVs, Psetand Qsetare the power reference setpoints. However, it may not be possible to replace Psand Qsby Psetand Qsetsince it leads to cancelation of the SV generic control unit. On the other hand, e may depend on Psetand Qsetas described in equations (1)-(8). Thus, it may be possible to generate Psand Qsfrom e by generating a current isthat is obtained from e and vtdifference divided by the filter impedance as shown inFIG.3(c). Psand Qsmay be rewritten as
Ps=vt+·is++vt−·is−(44)
Qs=vt⊥+·is++vt⊥−·is−(45)

As seen in (44) and (45), and also inFIG.3(c), sequence extractors356and358and orthogonal creators360,362and366are used. The positive and negative sequence extractors356and358and the orthogonal creator360,362and366are defined by taking vtas example:

In an example implementation, the current ismay be generated based on e and vtthrough an adder352that combines e and subtracts vtwhich is then provided to a component354to generate the current is. The current isis input to the sequence extractor356to generate is+and is−. The is+and is−are input to an internal power reference generator364. Also using vt, the sequence extractor358generates vt+and vt−, that are input to the orthogonal creator360and the orthogonal creator362to generate vt⊥+and vt⊥−, respectively. The vt⊥+and vt⊥−are provided to the internal power reference generator364. The internal power reference generator364generates Psand Qsas described in Equations (44) and (45). The Psand Qsare input to an IARC and AARC reference current generator unit372. Since the Psand Qsare generic for both IARC and AARC, and switching between these FRT strategies is related to the cosine term, i* can be rewritten to switch flexibly between IARC and AARC as:

The IARC and AARC reference current generator unit372generates i* based on Psand Qs, vt, vt⊥(received from the orthogonal creator366), and D (received from component370based on vtand k input368). For the control purpose design, creating D when k=1 is relatively complicated since it involves phase estimation. Thus, a more straightforward approach is followed by using D when k=1 as
D=vta2+vtb2+vtc2(51)
where vta, vtb, and vtc, are the abc quantities of vt. The generated i* from IARC or IARC is tracked by i through subtractor374and proportional-resonant (PR) controller376along with feedforward vtto obtain through adder378the new EMF vector e* to create PWM signals through PWM382.FIG.3(d)is a power part that receives PWM signals to trigger the power electronic switches384.

The implementation of the proposed C-IARC is done similarly to the IARC and AARC implementation.FIG.4(a)-FIG.4(d)illustrate a block diagram of the implemented C-IARC.FIG.4(a)illustrates a substantially similar power reference generator ofFIG.3(a)used in providing a generic SV control unit (ofFIG.4(b)) with active and reactive power references that ensure safe and reliable current generation. The power reference generator ofFIG.4(a)includes a sequence extractor402filters the vtand computes a positive sequence component vt+and a negative sequence component vt−. A magnitude detector404coupled to the sequence extractor receives the positive sequence component vt+and the negative sequence component vt−to obtain a positive vtmagnitude (Vt+) and a negative vtmagnitude (Vt−). The positive vtmagnitude (Vt+) and a negative vtmagnitude (Vt−) are provided to an adder406to generate Vd. The Vdis input to a multiplier408that multiplies 1.5 (3/2) to the Vd. Further, a maximum peak current component reference412input is provided to a d axis vtcomponent generator414that generates Id, and Iqbased on Equation (43). The Idis provided to a multiplier410that multiplies Idwith product of the Vdand 1.5 to generate Pfas provided in Equation (41). Further, Iqis multiplied with −1 by a multiplier416and provided to a multiplier418. The multiplier418multiplies −Iqwith the product of the Vdand 1.5 to generate Qfas provided in Equation (41).

FIG.4(b)is a known generic SV control unit serially coupled to the current limiter and receives Pfand Qfto produce e. The generic SV control unit includes a controller420that is substantially similar to the controllers120,220and320, and implements the logic based at least in part upon Equations (3), (6) and (8). The generic SV control unit may be modified by adding a switch to disable the voltage droop relation since the SV operates in a grid-connected mode of operation.

In an example implementation, the current ismay be generated based on e and vtthrough an adder452that combines e and subtracts vtwhich is then provided to a component454to generate the current is. The current isis input to a sequence extractor456to generate is+and is−. The is+and is−are input to an internal power reference generator464. Also using vt, the sequence extractor458generates vt+and vt−, that are input to an orthogonal creator460and the orthogonal creator462to generate vt⊥+and vt⊥−, respectively. The vt⊥+and vt⊥−are provided to an internal power reference generator464. The internal power reference generator464generates Psand Qsas described in Equations (44) and (45). The Psand Qsare input to a reference current generator unit472.

The modifications made inFIG.4(c)are related to generation of i* that achieves C-IARC based on equation (40) and the modified power estimator of equation (26). The vtis transformed to the αβ frame to produce vαand vβthrough an αβ transform component468. Then, both of vαand vβare shifted by π/2 and 3π/2 respectively by a phase shifter component470based on the equation (37) and the equation (38) to create {circumflex over (v)}αand {circumflex over (v)}β. The C-IARC reference current generated by the reference current generator unit472from the equation (40) is in the αβ frame as {circumflex over (ι)}α* and {circumflex over (ι)}β* which are transformed to their equivalent abc quantities through an abc transform component476to produce i* that achieves C-IARC. A PR controller is used to regulate i and, using a feedforward of vtto produce e* through adder478to control the electronic switches484of the power part ofFIG.4(d)through PWM482.

Simulation results are described henceforth. In an example, using a MATLAB/SIMULINK, a simulation model is built to simulate the SV topology inFIG.1. Table I shows the simulation model parameters.

The simulated SV may be subjected to an unbalanced grid condition at its terminal.FIG.5(a)shows the measured vt. The nominal value of the peak current during normal conditions to track the active and reactive power setpoint is 0.667 p.u. During the unbalanced condition, the SV generates current higher than its nominal values to maintain P and Q tracking to Psetand Qset.FIG.5(b)shows the generated current with a peak of almost 1.5 p.u. which is about 250% of the rated peak current value. This overcurrent condition coincides with the current mathematical model derived in the equation (9) that indicates that the SV current is not limited. Also, during the same unbalanced grid condition, P and Q experience oscillations shown inFIG.6(a)andFIG.6(b), which demonstrate that P and Q have oscillations at (2ω) that agree with (12) and (13) since the time difference between any two adjacent peaks is 8.33 ms. Thus, the simulation demonstrates that SV is unprotected against high current generation, and its active power and reactive power oscillate at (2ω) during unbalanced conditions.

The generic SV simulation model described above is modified to include the IARC and AARC units to resolve a problem of the power oscillations demonstrated inFIG.6(a)andFIG.6(b). The proposed SV with the IARC may be tested under the same conditions that the generic SV is tested.FIG.7(a)shows the generated P andFIG.7(b)shows the generated Q during the unbalanced condition. As seen in theFIG.7(a)andFIG.7(a), the oscillations are significantly reduced as compared to the generic SV unit. The generated current due to the IARC method is depicted inFIG.8(a)andFIG.8(b)have a peak that exceeds the desired limit as well as the current waveform is not sinusoidal. By enabling the current limitation of the disclosure through the introduction of Pfand Qf, the peak current may be limited to the desired value, which is 0.8 p.u. as highlighted by the black dashed line ofFIG.8(b).

FIG.9(a)shows P,FIG.9(b)shows Q, andFIG.9(c)shows i of the SV-IARC with the current limitation that successfully limited the current. However, it is expected to have P and Q less than their corresponding setpoints, i.e., 0.9 p.u. and 0.435 p.u., due to the current limitation action. The AARC may be designed to avoid generating the distorted current of the IARC that is shown inFIG.8(b)andFIG.9(c). The active power generation and the reactive power generation of the AARC are shown inFIG.10(a)andFIG.10(b), respectively. Also, a SV measure terminal voltage and SV current generation with AARC during an unbalanced grid conditions are shown inFIG.11(a)andFIG.11(b), respectively. FromFIG.10(a),FIG.10(b),FIG.11(a)andFIG.11(b), it is concluded that the AARC restores the sinusoidal shape of the generated current. However, the active and reactive power may have oscillations. Also, the current may exceed the desired limit, i.e., 0.8 p.u. Engaging the current limitation of the disclosure by modifying the power references can limit the peak current to the desired value.FIG.12(a),FIG.12(b)andFIG.12(c)show the active power, reactive power, and current generation with the current limitation, respectively. As expected, the power generation drops due to the current limitation, but the peak successfully remains under the desired limit.

The results of the IARC and AARC show the advantages and disadvantages for both. C-IARC merges the advantages of IARC and AARC while discarding their disadvantages, that is, power oscillations and distorted current generation.FIG.13(a)andFIG.13(b)show an SV measured voltage and an SV generated current for C-IARC, respectively. As evident, the power oscillations may be significantly eliminated without affecting the terminal voltage and generated current waveform shown inFIG.14(a)andFIG.14(b), respectively. Also, C-IARC further removes the remaining small portion of the power oscillations that IARC could not remove. The overcurrent conditions inFIG.14(b)are avoided as shown inFIG.15(a),FIG.15(b)andFIG.15(c)by the current limitation of the disclosure that successfully limits the current to a value equal to the desired limit, which is 0.8 p.u. Also, the power generation, similar to the previous strategies, drops due to the current limitation.

The disclosure provides a seamless FRT strategies. The addition of the FRT to the SV control unit does not affect the normal operation of the SV control unit. Thus, the SV intrinsic features are unaffected. The current limitation of the disclosure may be suitable for a generic SV as well as SV with the FRT strategies. The activation of the current limitation and any proposed FRTs strategies is a seamless transition process without requiring any switching. Thus, the SV stability may not be affected by any switching action. The IARC and AARC are flexibly coupled to achieve power oscillation reduction or current harmonic elimination. The C-IARC eliminates the power oscillations and current harmonics simultaneously. Further, there is no requirement to control the sequence components and add complexity to the SV control unit with the FRT strategies. Further, no hardware modification may be required for the current SV control unit.

It is understood that the examples, embodiments and teachings presented in this application are described merely for illustrative purposes. Any variations or modifications thereof are to be included within the scope of the present application as discussed.