Non-volatile memory and the fabrication method

A non-volatile memory comprising: a first substrate (100) and a second substrate (110), the first substrate (100) having a plurality of switching elements (4) arranged in matrix, and a plurality of first electrodes (18) connected to the switching element (4), the second substrate (110) having a conductive film (32), and a recording layer (34) whose resistance value changes by application of an electric pulse, wherein the plurality of first electrodes (18) are integrally covered by the recording layer (34), the recording layer (34) thereby being held between the plurality of first electrodes (18) and the conductive film (32); the first substrate (100) further comprising a second electrode (22), the second electrode (22) being electrically connected to the conductive film (32), the voltage of which is maintained at a set level while applying current to the recording layer (34).This non-volatile memory achieves high integration at low cost.

TECHNICAL FIELD

The present invention relates to a non-volatile memory and a fabrication method thereof, and more particularly to a non-volatile memory in which data can be recorded (written) or deleted by using the application of current to control resistance value variations, and to the fabrication method thereof.

BACKGROUND ART

Ferroelectric memory is known as a conventional non-volatile memory. For example, Japanese Unexamined Patent Publication No. 1996-227980 (in particular,FIG. 9) discloses a structure in which a ferroelectric material is used as a material for a capacitor insulating film of a DRAM (Dynamic Random Access read write Memory). This ferroelectric memory is fabricated by attaching a substrate on which a capacitor is formed and a substrate on which a switching element is formed into a united body.

Specifically, as shown inFIG. 9(a) attached with the present specification, a transistor Tr is formed on a silicon substrate61, and a first substrate S1is then formed to which a titanium nitride film63exposed to the surface is connected to an n type region62.

As also shown inFIG. 9(a), by forming a BSTO (Ba0.5Sr0.5TiO3) film65on a monocrystalline Nb-doped STO (SrTiO3) substrate64and a platinum film66on the BSTO film65, a second substrate S2comprising a capacitor C is obtained.

The thus obtained first substrate S1and second substrate S2are joined to each other and made thinner until the thickness thereof reaches a predetermined value, an isolation region67as shown inFIG. 9(b) is then formed, obtaining a DRAM memory cell. The isolation region67is composed of a first isolation region67athat separates adjacent transistors Tr in the first substrate S1from each other and a second isolation region67bthat separates adjacent capacitors C in the second substrate S2to each other.

An equivalent circuit comprising such memory cells arranged in a matrix is shown inFIG. 10. As shown inFIG. 10, a gate of each switching element Tr is connected to a word line WL, and a drain of each switching element Tr is connected to a bit line BL. A source of each switching element Tr is connected to one of the electrodes of each capacitor C and a plate wire PL is connected to the other electrode of each capacitor C. Writing to each memory cell is conducted by applying voltage to either the bit line BL or plate wire PL while the word line WL is in an ON-state, and the data is read by detecting inversion of polarization of the ferroelectric while applying voltage to the capacitor C.

In the above-described conventional method for fabricating a semiconductor memory, it is possible to reduce the level of accuracy necessary for joining the first substrate S1having a switching element Tr to the second substrate S2having a capacitor C. However, in a ferroelectric memory having a structure as shown inFIG. 9(a), in addition to forming the first isolation region67ain the first substrate S1comprising the switching element Tr, it is necessary to form the second isolation region67bin the second substrate S2comprising the ferroelectric capacitor C. Therefore, in a conventional technique, as shown inFIG. 9(b), after attaching the first substrate S1to the second substrate S2, the isolation region67is formed, i.e., the first isolation region67aand the second isolation region67bare formed at the same time. However, even in such a fabrication method, a complicated fine processing step employing photolithography is still necessary for the second substrate S2. This problem has become more significant as the degree of integration has increased.

Furthermore, in the above-described method for fabricating a semiconductor memory, it is necessary to construct the memory so that the voltage applied from the plate wire PL to the capacitor C shown inFIG. 10can be controlled; however, a concrete structure for meeting this requirement has not been disclosed and there is a room for further improvement in terms of ease of fabrication.

As well as ferroelectric memories, a memory using the characteristic that the resistance value of a bulk changes depending on the condition of crystalline (so-called a phase-change memory) is known as a non-volatile memory. For example, Japanese Unexamined Patent Publication No. 1999-204742, U.S. Pat. No. 6,314,014, etc., disclose such memories; however, none of these publications discloses a means for solving the above problem.

DISCLOSURE OF THE INVENTION

The present invention aims at providing a non-volatile memory that achieves high integration at low cost and a method for fabricating such a non-volatile memory.

An object of the present invention can be achieved by a non-volatile memory comprising:

a first substrate and a second substrate,

the first substrate having a plurality of switching elements arranged in a matrix, and a plurality of first electrodes connected to the switching elements,

the second substrate having a conductive film, and a recording layer whose resistance value changes by application of an electric pulse, wherein

the plurality of first electrodes are integrally covered by the recording layer, the recording layer thereby being held between the plurality of first electrodes and the conductive film,

the first substrate further comprising a second electrode, and

the second electrode being electrically connected to the conductive film, the voltage of which is maintained at a certain level while applying current to the recording layer.

Another object of the present invention can be achieved by a method for fabricating a non-volatile memory comprising an alignment step for aligning and connecting a first substrate and a second substrate,

the first substrate having a plurality of switching elements arranged in a matrix, and a plurality of first electrodes connected to the switching elements,

the second substrate having a conductive film, and a recording layer whose resistance value changes by application of an electric pulse, wherein

the first substrate further comprises a second electrode the voltage of which is maintained at a certain level while applying current to the recording layer,

in the alignment step, a first electrode connecting step in which the recording layer is held between the plurality of first electrodes and the conductive film by covering the plurality of first electrodes with the recording layer in a united manner, and a second electrode connection step for electrically connecting the second electrode to the conductive film or the recording layer are conducted at the same time.

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiments of the present invention are explained below with reference to the drawings.FIG. 1is a cross-sectional view explaining steps for fabricating a non-volatile memory according to one embodiment of the present invention.

An isolation region2is first formed in a lower substrate100, which is a p-type semiconductor substrate, as shown inFIG. 1(a), employing, for example, an STI (Shallow Trench Isolation) technique, and a plurality of switching elements4each composed of an n-type transistor is then formed by a general silicon semiconductor fabrication process. Each switching element4comprises a gate electrode8formed above the lower substrate100via a gate insulating film6, a source region10aand a drain region10bformed in the lower substrate100, the source region10aand the drain region10bbeing formed on each side of the gate insulating film6and being composed of an n-type diffusion layer.

An interlayer insulating film12ais then formed on the lower substrate100in such a manner to cover the switching elements4. A plurality of contact holes extending through to the source region10aand the drain region10bare formed in the interlayer insulating film12a, and a plug14ais then formed therein by implanting tungsten and/or like metal materials in the contact holes by selective CVD (Chemical Vapor Deposition), etc. After depositing a metal layer on the interlayer insulating film12aby sputtering, etc., the metal layer is subjected to patterning by photolithography, forming a metal wire16aconnected to the plug14a. Thereafter, an interlayer insulating film12bis formed on the entire surface of the interlayer insulating film12aso as to cover the top surface of the metal wire16a; a contact hole is formed to extend through to the metal wire16a; and a plug14band a metal wire16bconnected to the plug14bare formed in the same manner as above. By selectively forming contact holes while repeating these processes, a multilayer interconnection structure is formed in which the heights of the metal wires connected to the source region10aand the drain region10bare different. In other words, an interlayer insulating film12c, a plug14cand a metal wire16care further formed on the interlayer insulating film12b. The metal wire16cexposed from the interlayer insulating film12cis connected to the source region10aof the switching element4as a source electrode (first electrode)18. Among the metal wires16bformed in the interlayer insulating film12b, those that do not have a contact with the plug14care made to contact with the drain region10bof the switching element4as a bit line20.

In a step for forming metal wires16bon the interlayer insulating film12b, by forming a metal wire16b, which is connected to neither the source region10anor the drain region10b, one of the metal wires16cformed on the interlayer insulating film12cis made into a constant-voltage electrode (second electrode)22. The constant-voltage electrode22is formed on the same layer on which a source electrode18is formed and maintained at a constant voltage. The lower substrate100comprising the switching element4, source electrode18and constant-voltage electrode22is thus obtained.

In contrast, as shown inFIG. 1(b), an upper substrate110is formed by forming a conductive film32composed of a metal thin film on the surface of the upper substrate by sputtering, etc., subjecting the conductive film32to patterning in a photolithography step, forming a recording layer34composed of a phase-change film on the surface of the conductive film32by sputtering, etc., and subjecting the recording layer34to patterning. The size of the recording layer34is such that the layer covers the entire memory cell and the conductive film32is formed over an area greater than that of the recording layer34. This makes a portion of the conductive film32be an exposed portion32a, which is not covered with the recording layer34.

The upper substrate110may be preferably formed, for example, by using polycarbonate (PC), polyethylene terephthalate (PET) and/or like organic materials having a high heat resistance; however, inorganic materials may be used as long as they have adequate elasticity. For example, it is possible to use a thin film silicon substrate, ceramic substrate, FRP substrate, etc., as the upper substrate110. It is preferable that the conductive film32be composed of a metal, in which diffusion hardly occurs, such as W, Pt, Pd, etc.

A phase-change material having at least two stable phases of differing resistance values and capable of being reversibly switched these between is preferably used as the material for the recording layer34. In the present embodiment, GeSbTe, which is a chalcogenide compound having Ge, Sb and Te as its main components, is used. It is also possible to use chalcogenide-based materials combining Ge, Sb and Te with Ag and/or In, etc., for example, AgInSbTe, AgInSbGeTe, GeInSbTe, etc. By appropriately selecting the types of elements and the ratios thereof, the melting point of the recording layer34can be controlled. For example, when a GeSbTe compound is used, in the phase diagram shown inFIG. 2, compounds between Sb2Te3and GeTe are preferable, for example, (225) in the figure, i.e., Ge2Sb2Te5and the like are preferably used.

Examples of materials for the recording layer34other than chalcogenide-based materials include (R1-x, Ax)MnO3, wherein R is a rare-earth metal, A is an alkaline-earth metal, and 0<x<1. Pr, Gd and/or La may be used as rare-earth metal R and Ca, Ba, Sr, etc., may be used as the alkaline-earth metal A. Among these, in particular, when (Pr0.7, Ca0.3)MnO3, (Gd1-x, Bax)MnO3, (La1-x, Srx)MnO3or the like is used, semiconductor elements having excellent characteristics can be obtained. It is also possible to use (R1-x, Ax)CoO3, wherein Mn in (R1-x,Ax)MnO3is replaced with Co.

The lower substrate100and the upper substrate110are then joined to each other after being aligned as shown inFIG. 1(c). Specifically, a plurality of source electrodes18are simultaneously attached to the recording layer34in a united manner and aligned so that the constant-voltage electrode22is connected to the exposed portion32aof the conductive film32, completing a non-volatile memory.

When the lower substrate100and the upper substrate110are joined to each other, by conducting a suitable heat treatment, it is possible to strengthen the attachment between the source electrode18and the recording layer34, and between the constant-voltage electrode22and the conductive film32. Specific examples of heat treatment include use of an electric furnace or hot plate, and use of a lamp annealer for a short time of period. It is also possible to conduct heat treatment by applying millimeterwave or microwave radiation from the main surface side (the side where the switching element4is formed) of the lower substrate100and blocking the release of the waves from the opposite side. In-this method, because the source electrode18and the constant-voltage electrode22are heated first, the portion of the recording layer34to be attached to the source electrode18and the portion of the conductive film32to be attached to the constant-voltage electrode22can be selectively heated, obtaining a strong attachment. The portions to be heated do not necessarily have to be the above-described portions and, for example, even when the lower substrate100is first heated by applying millimeterwave or microwave radiation from the direction opposite to that mentioned above, using a hotplate, etc., the heat can be effectively transmitted to the source electrode18and the constant-voltage electrode22that are formed of metal, and therefore it is still possible to obtain a strong attachment between the lower substrate100and the upper substrate110.

In addition to the methods described above, an adhesion layer may be laid between the lower substrate100and the upper substrate110to enhance the strength of the attachment therebetween. In other words, as shown inFIG. 3, after forming adhesion layers36on the top surfaces of the source electrode18and the constant-voltage electrode22, the lower substrate100and the upper substrate110are joined to each other, with adhesion layers36lying between the source electrode18and the recording layer34, and between the constant-voltage electrode22and the conductive film32. When the adhesion layer36is thin (for example, not more than 10 nm), the adhesion layer36may be formed on the entire surface of the lower substrate100not only the top surfaces of the source electrode18or the constant-voltage electrode22. InFIG. 3, the components the same as those shown inFIG. 1(c) have the same reference numbers.

Sn, In, Pb and like low melting point metals, Ge, conductive polymers, etc., are preferably used as materials for the adhesion layer36. It is preferable that such a conductive polymer have resistance anisotropy exhibiting high resistivity in the main plane direction and low resistivity in the direction perpendicular to the main plane. In this case, it is possible to form the adhesion layer36on the surface of the recording layer34instead of forming the adhesion layer36on the lower substrate100. Alternatively, low melting point phase-change materials composed of Ge, Sb, Te, etc., may be used as the adhesion layer36. In this case, it is preferable that the adhesion layer36be prevented from forming on top of the constant-voltage electrode22by using a suitable mask while forming the adhesion layer36.

To reduce the connection area between the source electrode18and the recording layer34, it is also possible to form metal fine particles having a diameter of not more than 100 nm or fine pits and projections by ion irradiation, etc., on the surface of the source electrode18and/or the recording layer34. This increases the current density while applying current to the recording layer34, reducing power consumption of the memory.

To decrease the connection area between the source electrode18and the recording layer34, it is also possible to pattern an insulating layer38on top of the source electrode18as shown inFIG. 4and then join the lower substrate100to the upper substrate110. InFIG. 4, the components the same as those shown inFIG. 1(c) have the same reference symbols.

In this structure, because the insulating layer38lies in a portion of the interface between the source electrode18and the recording layer34(i.e., on top of the source electrode18), the source electrode18connects to the recording layer34only at the side surfaces, reducing the connection area compared to the structure shown inFIG. 1(c). As a result, operation with saved energy becomes possible. In addition to formation of the insulating layer38, by laying fine metal particles or forming pits and projections in the connecting portion, energy consumption can be further reduced. InFIG. 4, the insulating layer38is also formed on the constant-voltage electrode22, and this may be removed in a separate step.

In the non-volatile memory of the present embodiment, the lower substrate100needs an isolation region as in conventional non-volatile memories; however, the isolation region can be formed by a standard silicon semiconductor fabrication process step and no additional steps are necessary. A complicated fine processing step becomes unnecessary in formation of the upper substrate110, simplifying the whole fabrication process.

In other words, the recording layer34formed on the upper substrate110has a size that can cover the entire memory region so as to be connected to all source electrodes18, and the recording layer34is generally formed to have a pattern width of not less than 100 μm. The portion of the conductive film32exposed to the lower substrate100may be formed in any location, for example, by forming the exposed portion around the periphery of the memory region and obtaining enough space for the region, the alignment margin of the lower substrate100and the upper substrate110can be increased. The alignment margin corresponds to the distance M (seeFIG. 1(c)) between the constant-voltage electrode22and the source electrode18that is adjacent to the constant-voltage electrode22, and may be set at within the range from 1 to 50 μm. As a result, with respect to the upper substrate110, the pattern layout requirements are eased. Furthermore, in the non-volatile memory of the present embodiment, in contrast to a conventional ferroelectric memory (seeFIG. 9(b)), it is not necessary to form an isolation region in the upper substrate110having the recording layer34. Therefore, the upper substrate110does not need a fine processing step before and after being joined to the lower substrate100. This makes the fabrication process easier compared to conventional non-volatile memories and thus highly integrated non-volatile memories can be fabricated at low cost.

In the non-volatile memory of the present embodiment, as shown inFIG. 11, an auxiliary electrode22aadjacent to the constant-voltage electrode22may be formed in the same layer in which the constant-voltage electrode22is formed. InFIG. 11, the components the same as those shown inFIG. 1(c) have the same reference numbers.

In this structure, even when the constant-voltage electrode22is connected to the recording layer34by being covered with the recording layer34due to misalignment between the lower substrate100and the upper substrate110, as shown inFIG. 11, by applying current across the constant-voltage electrode22and the auxiliary electrode22a, it is possible to make the energized region in the recording layer34crystalline so as to have a low resistivity. Therefore, the constant-voltage electrode22can function in the same manner as in the structure shown inFIG. 1(c). This makes the alignment between the lower substrate100and the upper substrate110even easier and decreases the alignment margin (distance M inFIG. 1(c)), miniaturizing the semiconductor. In the structure shown inFIG. 11, the auxiliary electrode22ais not covered by the recording layer34; however, even when both the constant-voltage electrode22and the auxiliary electrode22aare covered by the recording layer34(seeFIG. 8described later), no problems arise.

In such a structure, when, in a latter step, the energized region in the recording layer34is made to have high resistivity by being irradiated with laser light, etc., there is a possibility that the function of the constant-voltage electrode22may be impaired. Therefore, it is preferable that the portion above the energized region in the recording layer34is shielded from light by using a material having a low transparency for the upper substrate110, etc.

FIG. 5is an equivalent circuit diagram of the non-volatile memory shown inFIG. 1(c), whereinFIG. 5(a) shows a single cell andFIG. 5(b) shoes a plurality of cells arranged in matrix. A single cell comprises a switching element4and a recording layer34. The gate electrode8of the switching element4is a word line and the drain portion10bis connected to the bit line20. The source portion10aof the switching element4is connected to one side of the recording layer34and the other side of the recording layer34is connected to the constant-voltage electrode22. The constant-voltage electrode22is generally a grounding wire; however, as long as the voltage can be maintained at a certain level when current is applied to the recording layer34, grounding is not necessarily required. This constant-voltage electrode22functions differently from a plate wire PL (seeFIG. 10)as used in a conventional ferroelectric memory in which voltage is applied when data are written or read.

Chalcogenide compounds, which are used as materials for the recording layer34in the present embodiment, exhibit a low electrical resistance in the crystalline state and a high electrical resistance in the amorphous state, and the variance is approximately 1 to 3 digits. Therefore, data can be written or read by allocating crystalline states and amorphous states to the data of “0” and “1” respectively (or “1” and “0”) as in a non-volatile memory using a phase-change material.

InFIG. 5(b), when data are read, by applying a predetermined voltage to the bit line20and the gate electrode (word line)8, current is applied to the constant-voltage electrode22from the bit line20through the switching element4and the recording layer34. Because the volume of the applied current changes depending on the resistance value of the recording layer34, memory contents in the recording layer34can be read based on the amount of current.

To write data, an appropriate voltage is applied to the bit line20and the gate electrode (word line)8so as to change the crystalline condition of the recording layer34. To change the recording layer34from crystalline (low-resistive state) to amorphous (high-resistive state), after applying current to the recording layer34in such a manner that a portion of the recording layer34becomes hotter than the crystallization temperature (for example, 600° C.), current is quickly removed. In contrast, to change the recording layer34from amorphous (high-resistive state) to crystalline (low-resistive state), current is applied to the recording layer34in such a manner that the temperature does not exceed the crystallization temperature of the recording layer34and that the recording layer34is crystallized. The recording layer34generally does not change its resistive condition at a temperature of 200° C. or less and therefore it functions as a non-volatile memory.

The phase-change materials composing the recording layer34generally increase their volume by several % to 10% when changed from crystalline to amorphous; however, in the structure of the present embodiment, expansion and shrinkage of the phase-change material is alleviated by the adequate elasticity of the upper substrate110, preventing breakage of wires in the portion connecting the lower substrate100and the upper substrate110.

In the non-volatile memory of the present embodiment, data can be written or read not only electrically but also optically using laser light, etc. When data are read, the portion of the recording layer34corresponding to an objective memory cell is irradiated with incident laser light Ib as shown inFIG. 6, and the intensity or degree of polarization of the reflected laser light Rb are measured. Polarization of the recording layer34is different between the crystalline and amorphous states, and therefore memory can be read based on the difference of the polarization. To effectively transfer the incident laser light Ib, it is preferable that the material for the upper substrate110have a high transparency and the conductive film32be thin. Specifically, it is preferable that the thickness of the conductive film32be from 3 to 10 nm. By constructing each cell so that its weighting factor, etc., can be read optically, the circuit can be miniaturized compared to circuits in which data are read electrically. Such a structure is useful for, for example, constructing a neural network. When prevention of optical reading or writing of data is necessary, it is preferable that the transparency of the upper substrate110be low and/or the conductive film32be thicker than 10 nm.

In the present embodiment, data can be written by following the method employed in known DVD disc media. In other words, the recording layer34can be changed to an amorphous state by suddenly stopping irradiation after irradiating the portion of the recording layer34corresponding to an objective memory cell as shown inFIG. 6with highly intensive laser light Lb, and the recording layer34can be made crystalline by irradiating with a relatively low intensity laser light Lb such that the recording layer34does not melt. In this case, by setting the thickness of the conductive film32within 3 nm to 10 nm, it is also possible to effectively transmit the laser light Lb and prevent thermal interference to an adjacent memory cell by reducing heat transmission through the conductive film32. The smaller the memory cell, the shorter the wavelength of the laser light Lb should be. For example, when the wavelength of the laser light Lb is approximately 600 nm to 700 nm, the size of the source electrode18can be miniaturized to approximately a square of 0.2 μm per side. As described above, by constructing the cell to be optically writable, an electrical writing circuit becomes unnecessary. This makes it possible to readily fabricate a neural network, which performs optimizations by changing the weighting factor in a later step, at low cost.

The non-volatile memory of the present embodiment uses an n-channel-type MOSFET as a switching element4; however, it is also possible to use a p-channel-type MOSFET by forming an n-well region in the lower substrate100, etc. Alternatively, another FET, bipolar element, HEMT (High Electron Mobility Transistor) or like transistor having three or more terminals may be used as the switching element4.

The structure of the memory cell is not limited to that of the present embodiment and, for example, the present invention can be employed to an SRAM (Static Random Access Memory) composed of a flip-flop circuit of six transistors provided with a first n-type switching element41, a second n-type switching element42, a first p-type switching element43, a second p-type switching element44, a third n-type switching element45, and a third n-type switching element46as shown inFIG. 7(a). InFIG. 7(a), reference numbers8and20refer to a word line and a bit line, respectively.

In this case, the cell can be fabricated in the same manner as in the present embodiment by providing a first recording layer47and a second recording layer48on the lower substrate100, connecting one end of the first recording layer47and that of the second recording layer48to the source of the first n-type switching element41and that of the second n-type switching element42, respectively, and connecting the other end of the first recording layer47and that of the second recording layer48to the constant-voltage electrode22. In this structure, because the voltages of node A and node B are determined based on the resistance difference between the first recording layer47and the second recording layer48when power supply to the power wire49is turned on, memory can be read based on these voltages. The one end of the first recording layer47and that of the second recording layer48may be connected to the source of the first p-type transistor43and that of the second p-type transistor44as shown inFIG. 7(b). InFIG. 7, a plurality of switching elements are formed in which switching elements41-44are arranged in a matrix.

In the present embodiment, an exposed portion32aof the conductive film32is formed on the upper substrate110, and the constant-voltage electrode22of the lower substrate100is connected to the exposed portion32a; however, it is also possible to form the recording layer34over the entire surface of the conductive film32so that the conductive film32is not exposed, as shown inFIG. 8. In this case, in the lower substrate110, by forming the auxiliary electrode22aadjacent to the constant-voltage electrode22on the same layer as the constant-voltage electrode22, when the lower substrate100and the upper substrate110are joined to each other, the constant-voltage electrode22and the auxiliary electrode22aare attached to the recording layer34. InFIG. 8, the components the same as those shown inFIG. 1(c) have the same reference numbers.

In a non-volatile memory having such a structure, by making the energized region in the recording layer34crystalline to reduce the resistivity thereof by applying current across the constant-voltage electrode22and the auxiliary electrode22ain advance, it is possible to make the constant-voltage electrode22function in the same manner as the structure shown inFIG. 1(c). By structuring the non-volatile memory in such a manner, an alignment margin becomes unnecessary. This makes it possible to further miniaturize the non-volatile memory and fabrication thereof becomes easier. Furthermore, as shown inFIG. 11, it is preferable that the portion above the energized region in the recording layer34in this structure be shielded from light.

INDUSTRIAL APPLICABILITY

As described above, the present invention provides a non-volatile memory that can achieve high integration at low cost and a method for fabricating such a memory.