System and method for handling bad bit errors

A method and system for detecting and correcting a bad bit error in a solid-state nonvolatile memory device. The device includes a bad bit detection module that receives an old page from the memory device and determines whether a page has a bad bit. The device further includes a bad bit correction module that generates a new page, determines a location of the bad bit, determines a preferred value of the bad bit, determines a user value of the bad bit and inserts the preferred value into a string of bits corresponding to substantive data of the old page, recording the string of bits with the preferred value inserted therein and stores the new page at an address of the old page.

FIELD

The present disclosure relates to a system and method for handling errors in a page of memory. In particular, the present disclosure relates to a method and system for remapping the spare data area of a page of memory to handle permanent bit errors.

BACKGROUND

The vast majority of electronic devices include at least one microcontroller or microprocessor that controls the operation thereof. In order to perform the desired functionality a microcontroller will execute code or executable instructions for performing specific operations. The microcontroller may also retrieve data for performing these operations. The code and data are stored in the computer readable memory device. Increasingly, manufacturers are using solid-state nonvolatile memory devices such as flash memory devices, e.g. NAND flash memory devices or NOR flash memory devices, as the computer readable memory devices.

One issue that arises with flash memory devices, however, is that read-inability errors are more commonly observed in flash memory devices, and especially in NAND flash memory. Read-inability errors can be permanent such as a bad block error, e.g. a bit within the block has been physically damaged, or temporary such as a data retention error or a read disturb error. Manufacturers of devices having non-volatile memory, such as flash memory devices, utilize error correction codes (ECC) to correct bit errors that occur in the memory device. During normal operation of the device when data is written to a memory device, ECCs are generated for that data by the hardware of the memory device and automatically stored with the data. On subsequent reads, the ECC is read back and used by the hardware to correct errors in the data. ECC codes can be parameterized during the hardware design phase to correct a fixed number of errors while using a given amount of storage overhead. Once ECC parameters are selected and implemented in the hardware, the ECC circuitry cannot be modified to correct more errors than the ECC scheme was originally designed for. When a read error occurs during normal system operation, it may be determined that there are more errors in the data than the ECC algorithm can fix. In these situations, the data is not recoverable. Thus, if the system designer requires stronger ECC algorithms than are implemented in the hardware ECC, the hardware ECC can be disabled and a stronger ECC algorithm can be executed by the microcontroller of the device. However, these ECC algorithms may decrease the overall performance of the microcontroller when reading and writing to the flash memory device.

As mentioned above, some errors may be temporary errors. Temporary errors in the data stored in the flash memory device accumulate over time due to interference from internal and external events that occurred during the normal system operation. Temporary errors occur in memory cells that do not have any physical defects. Because the memory cells are not defective, the correct data can be restored by performing a refresh operation on the block or page of data, which will include ECC-based error corrections, followed by a rewrite of the corrected data.

Permanent errors, however, cannot be fixed by refresh operations. Unlike temporary errors, permanent errors are typically caused by physical defects in the memory. While the ECC can correct permanent errors, the amount of errors that the ECC can correct is limited. Thus, there is a need for a more efficient way to handle permanent errors, as well as temporary errors, in memory devices, such as a flash memory device.

SUMMARY

A device configured to correct bad bit errors is disclosed. The device includes a solid-state nonvolatile memory device divided into a plurality of blocks, each block containing a plurality of pages, each page having a main area that stores substantive data and a spare area, and each spare area having a validity bit field indicating whether a bit in the main area is in an error state, a bad bit location field indicating the bit in the main area that is in the error state, a preferred value field indicating a likely value of the bit in the main area that is in the error state, and a user value field indicating a correct value of the bit in the error state. The device further comprises a main controller that performs at least one function of the device including a bad bit detection module that receives an old page from the solid state nonvolatile memory device and determines whether a page has a detected bit in an error state and a bad bit correction module that a) generates a new page, b) determines a location of the detected bit in the error state and records the location of the detected bit in the error state in a bad bit field of the new page, c) determines a preferred value of the detected bit in the error state and records the preferred value of the detected bit in the error state in a preferred value field of the new page, d) determines a user value of the detected bit in the error state and records the user value of the detected bit in the error state in a user value field of the new page, e) inserts the preferred value into a string of bits corresponding to substantive data recorded in a main area of the old page, and recording the string of bits with the preferred value inserted therein in a main area of the new page, and f) stores the new page at an address of the old page.

In another aspect of the disclosure, a method for correcting bad bit errors in a solid-state nonvolatile memory device is disclosed. The solid-state nonvolatile memory device is divided into a plurality of blocks. Each block contains a plurality of pages and each page includes a main area that stores substantive data and a spare area. Each spare area includes a validity bit field indicating whether a bit in the main area is in an error state, a bad bit location field indicating the bit in the main area that is in the error state, a preferred value field indicating a likely value of the bit in the main area that is in the error state, and a user value field indicating a correct value of the bit in the error state. The method comprises receiving an old page from the solid state nonvolatile memory device and determining whether a page has a detected bit in an error state. When the detected bit is an error state, the method further comprises generating a new page and determining a location of the detected bit in the error state and recording the location of the detected bit in the error state in the bad bit field of the new page. The method further comprises determining a preferred value of the detected bit in the error state and recording the preferred value of the detected bit in the error state in the preferred value field of the new page. The method also includes determining a user value of the detected bit in the error state and recording the user value of the detected bit in the error state in the user value field of the new page. The method further comprises inserting the preferred value into a string of bits corresponding to substantive data of the old page, and recording the string of bits with the preferred value inserted therein in a main area of the new page. The method also includes storing the new page at an address of the old page.

DETAILED DESCRIPTION

FIG. 1illustrates components of an exemplary device100or a subsystem of the device100. The device100includes a main controller110for operating the device100and a flash memory device120that stores executable instructions for operating the device100. The memory device120further stores data that may be used by the main controller110. The main controller110includes, but is not limited to, a read module112, a write module114, a bad bit detection module116, a bad bit correction module118, and a bit forcing module122.

The read module112is configured to read data from the memory device120that has been previously mapped by the bad bit correction module118. The read module112will transmit an address to the memory device120and the memory device120will return a data block corresponding to the requested address.

The write module114is configured to write data to the memory device120using a remap operation such that a page with a bad bit can remapped to compensate for the bad bit error. The write module114will transmit an address to write the data, as well as the data to be written.

The bad bit correction module118is configured to determine if a page in the data block has a permanent bit error, and if the page has a permanent bit error, the bad bit correction module118will remap the page of memory such that a portion of a spare data area of the page of memory is used to store the value of the damaged bit. As will be discussed in greater detail below, the bad bit correction module118will determine the location of a bad bit in a page, a preferred value of the bad bit, and a user value for the bit and will use the spare data area of the page such that the correct data can be reconstructed upon a read operation. As will be described below, the bad bit correction module118will utilize the bad bit detection module116to execute a refresh operation of a page and to determine if the page has a bad bit contained therein.

The bad bit detection module116is configured to determine if a page has a bad bit contained therein. The bad bit detection module116performs an enhanced refresh operation such that the bad bit detection module116refreshes a page of memory and detects permanent bit errors in each page of a block in the memory device120. As will be discussed in greater detail below, the bad bit detection module116reads a page of data with ECC enabled, writes the corrected page back to the memory device120, reads the same data with the ECC disabled, and compares the data from each read to determine if a page contains a bad bit.

The bit forcing module122is configured to receive a chunk of data, a location of a bit in the chunk of data, and a value to be inserted in the chunk of data at the received bit location. The bit forcing module122is used by the read module112to reconstruct a page of data that has a bad bit error and by the write module114to force a preferred value at a bad bit location in the chunk of data to be written with a remap. Once the preferred value is written into the chunk of data, the bit forcing module122returns the updated chunk of data to the requesting component.

The memory device120is configured to receive read and write requests from the main controller110. It is appreciated that in some embodiments the memory device120is a solid-state, nonvolatile memory device, such as a flash memory device. Further, the flash memory device can be comprised of NAND flash memory or NOR flash memory. It is further noted that later developed memory devices120may also be used in the device100.

As mentioned, in some embodiments the memory device120is a solid-state nonvolatile memory device.FIGS. 2A and 2Billustrate an exemplary structure of the solid-state nonvolatile memory device200. For purposes of this example, the solid-state nonvolatile memory device200is a flash memory device. The flash memory device200is divided into a plurality of blocks210. For instance, an exemplary flash memory device200can be divided into 1,028 blocks. Further, a block is divided into a plurality of pages220. For instance, an exemplary block210can be divided into 64 pages. A page230is comprised of a plurality of bytes. For instance, an exemplary page230can be comprised of 2,112 bytes. Additionally each page230can be broken down into four read units of 528 bytes apiece (not shown). It is appreciated that the foregoing values are exemplary and other configurations of the flash memory device200are envisioned. For instance a block may be comprised of 32 pages and a page may be comprised of 4,048 bytes. Furthermore, the foregoing structure may be applied to different types of memory devices as well.

A page230is divided into a main data section240and a spare data area250. The main data section240contains the substantive data to be stored. For instance, if the block is in the program area, the main data section240of a particular page230could correspond to a particular instruction. It is appreciated that addresses and parameter values can also be stored in the main data area240of a page230. The spare data area250stores information relating to the page230. The spare data area250includes a plurality of bytes260for the ECC. As discussed flash memory devices will include a memory controller (not shown) that executes an error checking algorithm to determine if any of the bits in the page contain an error. If so, the ECC section260of the spare data area250will indicate which bit or bits contain an error. As will be discussed below, the spare data area250contains additional information.

FIG. 2Billustrates an exemplary spare data area250. The spare data area250is of pre-determined length, e.g., 128 bits. The spare data area250is further divided into a bad block area258of pre-determined length, e.g., 16 bits, an ECC field260of pre-determined length, e.g., 64 bits, and a user metadata section262of predetermined length, e.g., 32 bits. The user metadata section262in the spare data area250may or may not be protected by hardware ECC. It is appreciated if hardware ECC is not available then the main controller110will need to protect information in the user metadata section262using a checksum or a CRC.

The user metadata section262can be broken down into a first section264and a second section266. Each section264and266can be used for correcting a bad bit error in the corresponding main data section. For example, the first section264can correct a first bad bit error in a first location and the second section266can correct a second bad bit error in a second location of the main data section240. The first section264is divided into four sections. The first section is comprised of a first validity bit268, a first bad bit location field270, a first preferred value bit272and a first user bit274. It is appreciated that the validity bit268, the preferred value bit272and the user bit274are all one bit in length, while the bad bit location field is of sufficient length to store a bit location, e.g. 13 bits. Similarly, the second section will have a second invalidity bit276, a second bad bit location field278, a second preferred bit280and a second user bit282.

The validity bit268indicates if the remaining data items in the first section264have been programmed. If there is not a bad bit detected in the main data section240, then the validity bit is set to 0. If, however, a bad bit is detected, the remaining data in the first section must be initialized to valid values and the validity bit is set to 1.

The bad bit location field270indicates the location of the first bad bit error in the main data section240. It is appreciated that the bad bit location field270must be of sufficient length so as to be able to address any bit location in the main data section240. Thus, the number of bits required in the field is Log2N, where N is the bit-length of the main data area240. It is also appreciated that a bad bit location of 0 can either indicate a bad bit at the most significant or least significant bit in the main data section240. It is appreciated other addressing schemes may be utilized.

The preferred value bit272is the value for the bad bit that will result in the fewest ECC errors. For instance, if the bit is stuck at 0, that is the bit always reads 0 regardless of the value written to the particular bit location, the preferred value will be set to 0. Similarly, if a bit reads at 1 80% of the time, the preferred value will be set to 1.

The user value bit274is the value that main controller110expects to read at that location when a read occurs. For instance, if the bad bit always reads 0 but the bad bit should be set to 1, the user value will be 1.

It is appreciated that the number of bits that can be corrected by the foregoing fields is dependent on the amount of space available in the spare data area250. For example, if each page has 8,192 regular data bits per main data area, 16 bits will be required for each entry in the spare data area, one for the validity bit, 13 for the bad bit location, one for the preferred value and one for the user value. If the spare data area250has between 32 and 47 bits available, two bad bits in the data area can be handled. If 48 bits are available than three bits can be handled, etc.

As mentioned, the bad bit correction module118is configured to correct for a bad bit error in a page of memory. The bad bit correction module118communicates with the memory device120to write a corrected page of memory thereto and with the bad bit detection module116to determine if a page of memory includes a bad bit.

FIG. 3illustrates an exemplary method that may be executed by the bad bit correction module118. The bad bit correction module118may execute the following method after a refresh operation, during a refresh operation, or at predetermined intervals. The bad bit correction module118may receive up to a full block and correct each page that requires correction. Thus, the bad bit correction module118is configured to iterate through a plurality of pages of memory. Accordingly, a page counter indicating a current page or a page address is set to 0, as shown at step312. The bad bit correction module118will communicate the page counter to a bad bit detection module116to determine if the current page, i.e., the page located at page address, has a bad bit therein, as shown at step314. As will be further described below, the bad bit detection module316will compare expected data against actual data to determine if a bad bit is contained in a page.

The expected data is data that should be read from the page being analyzed, whereas the actual data is the data found in the main data section of the page being read. If a discrepancy arises between the expected data and the actual data of the page, the bad bit detection module116will notify the bad bit correction module118of the existence of a bad bit. Thus, as shown at step316, the bad bit correction module118will determine whether a bad bit was detected. If a bad bit is not detected, then the bad bit correction module118will determine if there are any pages remaining to be analyzed, as shown at step at330, and will increment the page address if there are pages to be analyzed remaining.

If a bad bit was detected, then the bad bit correction module118will determine the location of the bad bit, as shown at step318. As will be described below, the bad bit correction module can identify a bad bit using the expected data and the actual data. By performing an exclusive OR (XOR) operation on the expected data and the actual data and bit shifting the result, the location of the bad bit can be identified. It is noted that the bad bit correction module118can generate a data structure that will eventually be used to generate a page to be written to memory, the data structure containing fields for the main data, the bad bit location, the preferred bit value, and the user bit value. Thus, the bad bit correction module118can set the bad bit location field equal to the bad bit location.

Once the location of the bad bit is identified the bad bit correction module118will determine and set the preferred bit value of the bad bit, as shown at step320. As previously discussed, the preferred value is the value that is most likely to be read at the bad bit location in the main data section of the current page. The preferred value can be set equal to the value read from the actual data at the bad bit location. Once the bad bit correction module118has determined the preferred bit value, the preferred bit value field is set to the preferred bit value. The user bit value field is set to the desired value of the bit located at the bad bit location, as shown at step322. Once the bad bit location, the preferred bit value and the user bit value have all been set, the bad block correction module118will write to the main data section of a page, as shown at step324. The main data section of a page will be written as the expected data but the bit located at bad bit location will be forced to the preferred bit value. As will be described below, the bit forcing module122will receive the expected data, the bad bit location and the preferred value and will generate a string of bits that represents the expected data with the preferred value at the bad bit location.

The data correction module118will then set the values of the page to be written to memory, as shown at step326. The page to be written to memory is comprised of the main data area which has been manipulated by the bit forcing module122, the validity bit value that is set to 1, the bad bit location that is set to the value of the bad bit location, the preferred bit value that is set to the preferred value, and the user bit value that is set to the user value. As can be appreciated, other fields such as the ECC fields or the bad byte field of the spare data area may also be populated. The collection of data is merged into a single string of predetermined length, e.g. the length of a page of memory. At this point an entire page has been generated and the page can be written to memory as shown at step328. It is appreciated that the method will continue to analyze the remaining pages in the block being analyzed. Accordingly, the bad bit correction module118will determine if there are any pages remaining to be analyzed, as shown at step330. If so, the method continues to execute and the page address is incremented as shown at step334. Else, the bad bit correction module118stops executing, as shown at step332.

As was discussed above, the bad bit detection module116will receive an address of a page of a block and will determine if a bad bit error is contained in the page. The following method describes a process to detect bit errors during a refresh operation that is used to remove temporary errors from a flash memory device120. Specifically a refresh operation reads data from flash with ECC enabled and allows ECC to correct any errors and then writes the data back to flash. In the enhanced refresh operation described below, permanent bit errors are detected in the page.

FIG. 4illustrates a method that may be executed by the bad bit detection module116to determine whether a bad bit exists in the page and, if so, the location of the bad bit. Further, the illustrated method further performs a refresh of the page of memory. While the following method is shown as being executed with respect to a single page, it is appreciated that the method could continue to loop for each page in a block of memory.

The bad bit detection module116will receive a request from a component of the device100, e.g. the bad bit correction module118, indicating a page address to perform bad bit detection on, as shown at step412. The bad bit detection module116will read the page at the requested page address as shown at step414. It is appreciated that prior to the bad bit detection module116being called, the block containing the page address may have been loaded from the memory device120. Upon retrieving the page found at page address, the bad bit detection module116will read the main data portion of the page, as shown at step414. It is noted that the foregoing read is ECC corrected data.

The ECC corrected portion of the data is found in the main data area of the page of memory. This data is referred to as the expected data. The bad bit detection module116writes the expected data back to memory, as shown at step418. The bad bit detection module116will then disable error correction as shown in step420, and will read the page again but without having the error correction performed on the particular page, as shown at step422. It is noted that the data found in the main data area of the uncorrected page is referred to the actual data. The bad bit detection module will get the data found in the main data area of the uncorrected page of memory, as shown at step424, and reenable ECC, as shown at step426.

As mentioned, the expected data is the ECC corrected data that was retrieved from the page, while the actual data is the uncorrected data retrieved from the page. To determine if there is any permanent bit errors in the page, the bad bit detection module116will compare the expected data with the actual data, as shown at step428. If the expected data does not match the actual data, the bad bit detection module116will mark the page as having a bad bit error, as shown at step440. When a page is marked as having a bad bit, the validity bit in the spare data area of the page will be marked to 1. If the expected data matches the actual data, the bad bit detection module116will not mark the page having a bad bit error and will stop executing, as shown at step442.

It is appreciated that variations of the method may be implemented and are within the scope of this disclosure. For instance, the method may execute for an entire block of data, such that the method comprises a loop that executes until each page in the block has been analyzed in the manner described above. Further, it is noted that some of the steps shown with respect toFIG. 4may be combined into a single step while other steps may be performed in multiple steps. Furthermore, it is appreciated that the bad bit detection module116may execute different methods for determining whether a page has a bad bit error therein.

As was described the bad bit correction module118will determine the location of a bad bit in a main data area of a page.FIG. 5illustrates an exemplary method for determining the location of a bad bit in a page of memory. To determine the location of a bad bit, the bad bit correction module118will use the expected and actual values found in a page of memory, as shown at step512. The bad bit correction module118will perform an exclusive OR (XOR) operation on the expected value and the actual value and will keep track of the results of the exclusive or operation using a check value. The check value will have a “1” for every bit where a match was not found between the expected value and the actual value. To determine the location of the bad bit, a bit value counter is set to zero as shown at step516. The bad bit correction module118will then iterate through the check value to determine when a first instance of a “1” is found in the check value, as shown at step518. If the least significant bit does not equal 1, then the bit location counter is incremented as shown at step520. The check value is then shifted one bit to the right and the method steps back to checking the least significant bit, as shown at step518. It is appreciated that this method will continue to execute until the least significant bit is determined to be “1” at which point the bit location counter is returned. The bad bit location is then stored in the spare data area of the page of memory as was described with respect toFIG. 3.

It is appreciated that variations of the method may be implemented and are within the scope of this disclosure. For instance, the method may execute until 2 or more “1”s are found in the check value, such that multiple bad bit locations are determined for a single page of memory. Further, it is noted that some of the steps shown with respect toFIG. 5may be combined into a single step while other steps may be performed in multiple steps. Furthermore, it is appreciated that the bad bit detection module116may execute different methods for determining the location of a bad bit

As previously discussed, the bad bit correction module118will utilize the bit forcing module122to manipulate the data to be stored in the page of memory by forcing the bad bit to a particular value.FIG. 6illustrates an exemplary method that can be executed by the bit forcing module122. The bit forcing module will execute the following method when one of the write module114, read module112, or bit correction module118requires a bit to be forced to a particular value. To do so, the bit forcing module122will receive a chunk of data representing the data to be manipulated, a location of the bit to be forced, and the value to which the bit will be forced to, as shown at step612. The location is a value, N, such that the bit to be forced in the Nth bit from either the least significant bit or the most significant bit. To force a bit to a desired value, the bit forcing module122will use a bit mask. The bit mask is set to 1, e.g. 0X0001, as shown at step614. The mask is then bit shifted to the left by the value of location, as shown at step616. For instance, if the third bit is to be forced, the bit mask is shifted to three positions to the left, e.g. 0x0004. Next, the bit forcing module will analyze the value of the bit being forced. If the bit being forced has a value of one then the bit forcing module122will perform an OR operation on the mask and the chunk of data, as shown at step626. If the value of the bit being changed is zero then the bit mask is inverted, as shown at step622, and an AND operation is performed on the chunk of data and the mask, as shown at624. After either step626or624is performed, the new data resulting from either the OR operation or the AND operation is returned to the requesting module.

It is appreciated that variations of the method may be implemented and are within the scope of this disclosure. Further, it is noted that some of the steps shown with respect toFIG. 6may be combined into a single step while other steps may be performed in multiple steps. Furthermore, it is appreciated that the bit forcing module122may execute different methods for forcing a bit to a desired value.

When the main controller110requires to write to the memory device, the main controller110will utilize the write module114, which is configured to remap a page of memory when the validity bit of the page of memory indicates that the page contains a bad bit.FIG. 7illustrates an exemplary method that can be executed by the write module114when writing a page to the memory device120. The write module114receives an address of a page to be written to and a chunk of data indicating the data to be stored in the main data area of the page as shown at step712. Prior to writing the data, the write module114will read data from the retrieved page, as shown at step714, to determine if a bad bit exists in the page to be written to, i.e. the page at the received page address. The write module114will retrieve the validity bit of the page, as shown at step716, and will determine whether the bit indicates the page has a bit error, as shown at step718. If there is no bad bit error in the page, then the write module114will generate a page to write using the chunk of data, while keeping the validity bit set to zero. The write module114will then write the page to write to memory, as shown at step730.

It is appreciated that if a bad bit exists, then the chunk of data as well as the data in the spare data area must be manipulated so that the page is remapped. To ensure that the data is manipulated properly, the write module114will determine a bad bit location from the read data, as shown at step720. The write module114will read the value corresponding to the bad bit location from the spare data area of the retrieved page. Similarly, the write module114will read the preferred value of the bad bit from the spare data area of the retrieved page, as shown at step722. The write module114will determine a user value from the bit at the bad bit location in the received chunk of data, as shown at step724. It is noted that the received chunk of data does not have a bad bit, but the bit value at the bit corresponding to bad bit value will be entered into the user value field of the page to be written.

The write module114will then communicate the main data, the bad bit location and the preferred value to the bit forcing module122, such that the preferred value is inserted into the main data at the bad bit location, as shown as step726. The write module114will then generate a page to write, as shown at step728. The page to write is a data structure that corresponds to a page of memory that is to be written in a subsequent block write. The page to write will include the main data, the validity bit, a bad bit location, the preferred value and the user value. Once the page to write is generated, the write module114will write the page to write to memory.

It is noted that the main controller110may only be configured to write entire blocks at a time. Thus, the write module114may be configured to wait until the contents of an entire block are rewritten before writing the entire block back to the memory device120.

It is appreciated that variations of the method may be implemented and are within the scope of this disclosure. Further, it is noted that some of the steps shown with respect toFIG. 7may be combined into a single step while other steps may be performed in multiple steps. Furthermore, it is appreciated that the write module114may execute different methods for forcing a bit to a desired value.

When the main controller110requires to read to the memory device120, the main controller110will utilize the read module112, which is configured to reconfigure the main data from the main data area to compensate for a bad bit error.FIG. 8illustrates an exemplary method that can be executed by the read module112. The read module112receives an address of a page to be read from the memory device120, as shown at step812. The read module112will retrieve the requested page from the memory device120, as shown at step814. The read module112will then read the main data area of the read page, as shown at step816. It is noted that the read module112can initialize a variable, e.g. main data, to store the data contained in the main data area of the read page.

The read module112will check the validity bit of the read page, as shown at step818, and will determine whether the validity bit indicates a bad bit error in the read page, as shown at step820. If the validity bit is set to 0, i.e. there is no bad bit error, the read module114will return main data to the requesting module and the method will stop executing, as shown at step828.

If, however, the validity bit is set to 1, i.e., the page contains a bad bit, the read module112will read the bad bit location from bad bit field of the read page, as shown at step822. The read module will also determine the user value from the user value field of the read page, as shown at step824. For instance, if the user value field of the read page indicates that the bit located at the bad bit location is supposed to be a 1, then the user value will be set equal to 1.

The read module114will then communicate the variable main data, the bad bit location, and the user value to the bit forcing module122, as shown at step826. As previously discussed, the bit forcing module will manipulate the main data to include the user value at the bad bit location. The bit forcing module will return the main data variable with the user value included therein. The read module122will then communicate the main data to the requesting module, as shown at step828.

It is appreciated that variations of the method may be implemented and are within the scope of this disclosure. Further, it is noted that some of the steps shown with respect toFIG. 8may be combined into a single step while other steps may be performed in multiple steps. Furthermore, it is appreciated that the read module112may execute different methods for forcing a bit to a desired value.

It is noted that the write module114, the read module112, and the bad bit correction module118all require at some point to determine the value of a particular bit in a string of bits.FIG. 9illustrates an exemplary method for determining a bit value in a string of bits. The string of bits and the bit location are received, as shown in step912. The string of data is shifted to the right by the number of bits specified by the bit location, as shown at step914. The requested bit value is the least significant bit after the shift operation has been performed. The least significant bit can be obtained by performing an AND operation on the shifted string of bits and a mask having the value 1, i.e., 0X0001, as shown at step916. The bit value is returned to the requesting module, as shown at step918.

It is appreciated that variations of the method may be implemented and are within the scope of this disclosure. For instance, the mask can be shifted to the left by the number of bits specified by the bit location. Further, it is noted that some of the steps shown with respect toFIG. 9may be combined into a single step while other steps may be performed in multiple steps. Furthermore, it is appreciated that the read module112may execute different methods for forcing a bit to a desired value.