External interfaces for a 3D graphics system

An advantageous set of external interfaces for home video game platform provide modularity and expandability while maintaining and preserving the proprietary nature of the platform. A disk drive interface provides flexible communications with an internal disk drive. Various serial bus interfaces provide expandability and interconnectability with a variety of internal and external devices including, for example, flash memory, broadband adapters, modems, and various other devices. A 4-port game controller interface provides serial interconnectability with handheld game controllers and various other input/output device. Power supply, digital and analog audio/video connections, and parallel memory expansion connections are also provided.

FIELD OF THE INVENTION

The present invention relates to computer graphics, and more particularly to interactive graphics systems such as home video game platforms. Still more particularly, this invention relates to external system interfaces used to connect a graphics system to audio, video, mass media storage device, other storage device, communications, printing and other electronic devices.

BACKGROUND AND SUMMARY OF THE INVENTION

Many of us have seen films containing remarkably realistic dinosaurs, aliens, animated toys and other fanciful creatures. Such animations are made possible by computer graphics. Using such techniques, a computer graphics artist can specify how each object should look and how it should change in appearance over time, and a computer then models the objects and displays them on a display such as your television or a computer screen. The computer takes care of performing the many tasks required to make sure that each part of the displayed image is colored and shaped just right based on the position and orientation of each object in a scene, the direction in which light seems to strike each object, the surface texture of each object, and other factors.

Because computer graphics generation is complex, computer-generated three-dimensional graphics just a few years ago were mostly limited to expensive specialized flight simulators, high-end graphics workstations and supercomputers. The public saw some of the images generated by these computer systems in movies and expensive television advertisements, but most of us couldn't actually interact with the computers doing the graphics generation. All this has changed with the availability of relatively inexpensive 3D graphics platforms such as, for example, the Nintendo 64® and various 3D graphics cards now available for personal computers. It is now possible to interact with exciting 3D animations and simulations on relatively inexpensive computer graphics systems in your home or office.

A problem graphics system designers confronted in the past was how to efficiently couple system components together. A modern 3D graphics system is relatively complex, and requires a number of different connections between different aspects of the system. For example, it is often necessary to interface with a mass storage device such as an optical disk. In addition, in an interactive real time system such as a gaming platform, some means must be provided to interface with user-manipulable controls such as hand-held controllers or the like. Sound is typically required, so that interfaces with various sound-producing and sound-supporting components are required. It is also necessary to provide some interfacing means for interfacing the system with a display device of an appropriate configuration. Additionally, it is often desirable to interface the system with a number of other components such as, for example, read only memory, flash memory, various memory cards, modems or other network connections, and debugging facilities for game or other application development. Various solutions to this problem were offered.

One approach would be to use standardized interfaces. Computer equipment manufacturers have developed a number of standardized interfaces in the past to connect with mass storage devices, modems, and other peripheral devices. Using standardized interfaces tends to simplify design efforts and achieve component compatibility and interoperability. The typical personal computer has a number of standardized interfaces so it can be modular and compatible with hardware and peripherals designed by a number of different manufacturers. Designing a new personal computer does not require redesign of all of these interfaces.

While the standardized interface approach has certain advantages in the arena of general purpose computing, it may not be suitable for home video game platforms. Because a home video game system must be manufactured at low cost and yet achieve maximum performance, it is desirable to optimize each and every aspect of the system—including the system interfaces. The interfaces can be looked at as the highways over which information flows throughout the system. This information traffic should flow as rapidly and efficiently as possible. Using standard interfaces may be easier from a design standpoint, but a standardized interface may not provide the high performance that a customized interface might offer. “One size fits all” makes things easier, but doesn't always result in the best possible fit.

Another issue relates to hardware interoperability. Standardized interfaces provide the advantage that no one owns them, and everyone can design components that are compatible with them. For example, when you buy a personal computer having a standardized serial interface, parallel interface and expansion device interface, you know that you can go out and purchase any of a variety of different devices all of which will be compatible with those standardized interfaces. You can plug in any of a dozen different types of printers to either the serial or the parallel interface of your personal computer, and they will all work. Similarly, any of dozens of different modems or other network cards can be plugged into the PCMCIA card slot of a personal computer or laptop, and all of these different cards will work.

Open standards have the advantage that they achieve hardware interoperability between systems and a wide range of different accessories. This approach is helpful when the system manufacturer is selling a general purpose device that can be used for virtually any application, but makes less sense in the home video game arena where a given video game manufacturer is responsible for making or licensing all of the various special-purpose accessories for its brand of home video game platform.

For example, video game manufacturers in the past have expended substantial time, effort and resources to develop definitive new home video game platforms. They want to sell as many of these as possible, and therefore price them very competitively. Like the razor manufacturer who recoups his investment by selling razor blades as opposed to the razor itself, video game platform manufacturers rely on controlling access to the installed user base of home video game systems to achieve profits through licensing. If the home video game platform used open standards, then competing manufacturing could bypass the company that invested all the time, effort and resources to develop the platform to begin with, and could instead market directly to consumers. Accordingly, under this business model, it is important for the platform manufacturer to be able to control access to the platform.

One technique used successfully in the past to control access to home video game platforms was to incorporate security systems that control access to the platform. A security system can enable the platform to accept or reject things plugged into it. As one example, it is possible to include an integrated circuit chip authentication type device in home video game cartridges. Before the home video game platform interoperates with the cartridge or other accessory, it may first authenticate the cartridge or other accessory by use of the security chip. While this approach can be highly successful, it requires each accessory to include authentication type information and/or devices. This increases cost. In addition, no security system is impenetrable. Given enough time, effort and resources, any security system can be “cracked” to unlock access to the platform. Thus, further improvements are desirable.

The present invention provides an approach to solving these problems. It provides a variety of proprietary system interfaces that have been optimized to maximize system performance. Because these optimized system interfaces are non-standard and unusual, they provide uniqueness that can be used as a basis for excluding unlicensed and unauthorized people from manufacturing components that are compatible with the interfaces. This allows a home video game platform developer to protect its substantial investment in the development of the platform.

One aspect of the present invention provides a proprietary disk interface for mass storage devices such as optical disks. The disk interface can be used to interface with an optical disk drive using direct memory access with interrupt. The disk interface acts as a transport for command packets sent between a disk drive and a graphics and audio coprocessor. The interface need not interpret the packets. The disk interface provides a number of signal lines including a parallel data bus and various additional signaling lines to provide high speed data transfer and efficiently coordinate operations between the disk drive and the rest of the system.

Another aspect provided by this invention is a serial interface for interfacing an audio and graphics coprocessor with a variety of different types of accessory devices including but not limited to hand-held game controllers. The serial interface provides a single bit serial interface using a state-based interface protocol. The interface supports four separate serial interfaces to four hand-held controllers or associated devices. Each interface can be accessed in parallel. In a controller mode, the last state of the controller is stored in a double-buffered register to support simple main processor reads for determining state. The example embodiment automatically polls controller state using hardware circuitry with configurable polling periods. A bulk mode supports changeable data size. A pair of light gun signals can be used to control separate horizontal/vertical counters to support flash and shutter light guns. An LCD shutter can be supported through automatic polling and a serial control command. The system interface includes automatic control of presence detect to save effort on the part of the main processor.

In accordance with another aspect of this invention, an external accessory device interface(s) is provided for interfacing with a variety of different types of external devices such as, for example, read only memory, flash memory, memory cards, modems, debugging systems or a variety of other devices. The external interface provided in accordance with this invention can be used, for example, to interface with a single chip boot ROM and associated real time clock, as well as to on-board flash memory, an external modem, an external memory card, debugger hardware, or other external devices including but not limited to a voice recognition device. A preferred external interface provides four separate external interface channels. A channel0supports both expansion and on-board devices. The entire ROM is memory mapped onto the external interface, and ROM reads can be controlled entirely by hardware for boot support. Separate external interface chip selects can be used to control many different devices (e.g., ROM/RTC, flash memory, expansion modem, expansion backup memory card, debug, etc.). Maskable external interrupts can also be provided—one for each external expansion port. Maskable interrupts may provide transfer complete signaling for each channel. A pair of maskable interrupts can be provided for hot-plug status to detect insertion and removal of external devices. Direct memory access can be used to support general transfers on each channel.

In accordance with yet another aspect provided by this invention, an audio interface provides support for audio functions within a graphics system. The audio/video interface can provide support for an external digital-to-analog converter providing, for example, composite video and 16-bit stereo sound running at a desired sampling rate (e.g., fixed 48 kHz). The interface may also provide an interface for a digital audio and video output and/or input. The collection of audio interfaces may also include a mass storage device streaming audio input interface via, for example, a 16-bit serial bit interface running at a predetermined sampling rate (e.g., 32 kHz or 48 kHz). The sample rate conversion of mass storage device streaming audio can be provided “on the fly.” The collection of audio interfaces may also include an audio mixer interface for mixing two audio streams into a final output stream. The audio mixer interface can provide audio volume control, for example, for mixing the mass storage device streaming audio output with audio generated using an internal digital signal processor.

In accordance with yet another aspect of this invention, a video interface provides efficient interfacing between a graphics processor and an external video encoder. The video interface does much of the work required so as to reduce the amount of work the external encoder needs to perform. The video interface also provides a number of interesting additional features such as panning, windowing, light gun support, and color format conversion.

FIG. 1shows an example interactive 3D computer graphics system50. System50can be used to play interactive 3D video games with interesting stereo sound. It can also be used for a variety of other applications.

In this example, system50is capable of processing, interactively in real time, a digital representation or model of a three-dimensional world. System50can display some or all of the world from any arbitrary viewpoint. For example, system50can interactively change the viewpoint in response to real time inputs from handheld controllers52a,52bor other input devices. This allows the game player to see the world through the eyes of someone within or outside of the world. System50can be used for applications that do not require real time 3D interactive display (e.g., 2D display generation and/or non-interactive display), but the capability of displaying quality 3D images very quickly can be used to create very realistic and exciting game play or other graphical interactions.

To play a video game or other application using system50, the user first connects a main unit54to his or her color television set56or other display device by connecting a cable58between the two. Main unit54produces both video signals and audio signals for controlling color television set56. The video signals are what control the images displayed on the television screen59, and the audio signals are played back as sound through television stereo loudspeakers61L,61R.

The user also needs to connect main unit54to a power source. This power source may be a conventional AC adapter (not shown) that plugs into a standard home electrical wall socket and converts the house current into a lower DC voltage signal suitable for powering the main unit54. Batteries could be used in other implementations.

The user may use hand controllers52a,52bto control main unit54. Controls60can be used, for example, to specify the direction (up or down, left or right, closer or further away) that a character displayed on television56should move within a 3D world. Controls60also provide input for other applications (e.g., menu selection, pointer/cursor control, etc.). Controllers52can take a variety of forms. In this example, controllers52shown each include controls60such as joysticks, push buttons and/or directional switches. Controllers52may be connected to main unit54by cables or wirelessly via electromagnetic (e.g., radio or infrared) waves.

To play an application such as a game, the user selects an appropriate storage medium62storing the video game or other application he or she wants to play, and inserts that storage medium into a slot64in main unit54. Storage medium62may, for example, be a specially encoded and/or encrypted optical and/or magnetic disk. The user may operate a power switch66to turn on main unit54and cause the main unit to begin running the video game or other application based on the software stored in the storage medium62. The user may operate controllers52to provide inputs to main unit54. For example, operating a control60may cause the game or other application to start. Moving other controls60can cause animated characters to move in different directions or change the user's point of view in a 3D world. Depending upon the particular software stored within the storage medium62, the various controls60on the controller52can perform different functions at different times.

Example Electronics of Overall System

FIG. 2shows a block diagram of example components of system50. The primary components include:a main processor (CPU)110,a main memory112, anda graphics and audio processor114.

In this example, main processor110(e.g., an enhanced IBM Power PC 750) receives inputs from handheld controllers52(and/or other input devices) via graphics and audio processor114. Main processor110interactively responds to user inputs, and executes a video game or other program supplied, for example, by external storage media62via a mass storage access device106such as an optical disk drive. As one example, in the context of video game play, main processor110can perform collision detection and animation processing in addition to a variety of interactive and control functions.

In this example, main processor110generates 3D graphics and audio commands and sends them to graphics and audio processor114. The graphics and audio processor114processes these commands to generate interesting visual images on display59and interesting stereo sound on stereo loudspeakers61R,61L or other suitable sound-generating devices.

Example system50includes a video encoder120that receives image signals from graphics and audio processor114and converts the image signals into analog and/or digital video signals suitable for display on a standard display device such as a computer monitor or home color television set56. System100also includes an audio codec (compressor/decompressor)122that compresses and decompresses digitized audio signals and may also convert between digital and analog audio signaling formats as needed. Audio codec122can receive audio inputs via a buffer124and provide them to graphics and audio processor114for processing (e.g., mixing with other audio signals the processor generates and/or receives via a streaming audio output of mass storage access device106). Graphics and audio processor114in this example can store audio related information in an audio memory126that is available for audio tasks. Graphics and audio processor114provides the resulting audio output signals to audio codec122for decompression and conversion to analog signals (e.g., via buffer amplifiers128L,128R) so they can be reproduced by loudspeakers61L,61R.

Graphics and audio processor114has the ability to communicate with various additional devices that may be present within system100. For example, a parallel digital bus130may be used to communicate with mass storage access device106and/or other components. A serial peripheral bus132may communicate with a variety of peripheral or other devices including, for example:a programmable read-only memory (PROM) and/or real time clock (RTC)134,a modem136or other networking interface (which may in turn connect system100to a telecommunications network138such as the Internet or other digital network from/to which program instructions and/or data can be downloaded or uploaded), andflash memory140.
A further external serial bus142may be used to communicate with additional expansion memory144(e.g., a memory card) or other devices. Connectors may be used to connect various devices to busses130,132,142.
Example Graphics and Audio Processor

FIG. 3is a block diagram of an example graphics and audio processor114. Graphics and audio processor114in one example may be a single-chip ASIC (application specific integrated circuit). In this example, graphics and audio processor114includes:a processor interface150,a memory interface/controller152,a 3D graphics processor154,an audio digital signal processor (DSP)156,an audio memory interface158,an audio interface and mixer1300,a peripheral controller162, anda display controller164.

3D graphics processor154performs graphics processing tasks. Audio digital signal processor156performs audio processing tasks. Display controller164accesses image information from main memory112and provides it to video encoder120for display on display device56. Audio interface and mixer1300interfaces with audio codec122, and can also mix audio from different sources (e.g., streaming audio from mass storage access device106, the output of audio DSP156, and external audio input received via audio codec122). Processor interface150provides a data and control interface between main processor110and graphics and audio processor114.

Memory interface152provides a data and control interface between graphics and audio processor114and memory112. In this example, main processor110accesses main memory112via processor interface150and memory interface152that are part of graphics and audio processor114. Peripheral controller162provides a data and control interface between graphics and audio processor114and the various peripherals mentioned above. Audio memory interface158provides an interface with audio memory126.

Example Graphics Pipeline

FIG. 4shows a more detailed view of an example 3D graphics processor154. 3D graphics processor154includes, among other things, a command processor200and a 3D graphics pipeline180. Main processor110communicates streams of data (e.g., graphics command streams and display lists) to command processor200. Main processor110has a two-level cache115to minimize memory latency, and also has a write-gathering buffer111for uncached data streams targeted for the graphics and audio processor114. The write-gathering buffer111collects partial cache lines into full cache lines and sends the data out to the graphics and audio processor114one cache line at a time for maximum bus usage.

Command processor200receives display commands from main processor110and parses them—obtaining any additional data necessary to process them from shared memory112. The command processor200provides a stream of vertex commands to graphics pipeline180for 2D and/or 3D processing and rendering. Graphics pipeline180generates images based on these commands. The resulting image information may be transferred to main memory112for access by display controller/video interface unit164—which displays the frame buffer output of pipeline180on display56.

FIG. 5is a logical flow diagram of graphics processor154. Main processor110may store graphics command streams210, display lists212and vertex arrays214in main memory112, and pass pointers to command processor200via bus interface150. The main processor110stores graphics commands in one or more graphics first-in-first-out (FIFO) buffers210it allocates in main memory110. The command processor200fetches:command streams from main memory112via an on-chip FIFO memory buffer216that receives and buffers the graphics commands for synchronization/flow control and load balancing,display lists212from main memory112via an on-chip call FIFO memory buffer218, andvertex attributes from the command stream and/or from vertex arrays214in main memory112via a vertex cache220.

Command processor200performs command processing operations200athat convert attribute types to floating point format, and pass the resulting complete vertex polygon data to graphics pipeline180for rendering/rasterization. A programmable memory arbitration circuitry130(seeFIG. 4) arbitrates access to shared main memory112between graphics pipeline180, command processor200and display controller/video interface unit164.

Transform unit300performs a variety of 2D and 3D transform and other operations300a(seeFIG. 5). Transform unit300may include one or more matrix memories300bfor storing matrices used in transformation processing300a. Transform unit300transforms incoming geometry per vertex from object space to screen space; and transforms incoming texture coordinates and computes projective texture coordinates (300c). Transform unit300may also perform polygon clipping/culling300d. Lighting processing300ealso performed by transform unit300bprovides per vertex lighting computations for up to eight independent lights in one example embodiment. Transform unit300can also perform texture coordinate generation (300c) for embossed type bump mapping effects, as well as polygon clipping/culling operations (300d).

Setup/rasterizer400includes a setup unit which receives vertex data from transform unit300and sends triangle setup information to one or more rasterizer units (400b) performing edge rasterization, texture coordinate rasterization and color rasterization.

Texture unit500(which may include an on-chip texture memory (TMEM)502) performs various tasks related to texturing including for example:retrieving textures504from main memory112, texture processing (500a) including, for example, multi-texture handling, post-cache texture decompression, texture filtering, embossing, shadows and lighting through the use of projective textures, and BLIT with alpha transparency and depth,bump map processing for computing texture coordinate displacements for bump mapping, pseudo texture and texture tiling effects (500b), andindirect texture processing (500c).

Texture unit500outputs filtered texture values to the texture environment unit600for texture environment processing (600a). Texture environment unit600blends polygon and texture color/alpha/depth, and can also perform texture fog processing (600b) to achieve inverse range based fog effects. Texture environment unit600can provide multiple stages to perform a variety of other interesting environment-related functions based for example on color/alpha modulation, embossing, detail texturing, texture swapping, clamping, and depth blending.

Pixel engine700performs depth (z) compare (700a) and pixel blending (700b). In this example, pixel engine700stores data into an embedded (on-chip) frame buffer memory702. Graphics pipeline180may include one or more embedded DRAM memories702to store frame buffer and/or texture information locally. Z compares700a′ can also be performed at an earlier stage in the graphics pipeline180depending on the rendering mode currently in effect (e.g., z compares can be performed earlier if alpha blending is not required). The pixel engine700includes a copy operation700cthat periodically writes on-chip frame buffer702to memory portion113of main memory112for access by display/video interface unit164. This copy operation700ccan also be used to copy embedded frame buffer702contents to textures in the main memory112for dynamic texture synthesis effects. Anti-aliasing and other filtering can be performed during the copy-out operation. The frame buffer output of graphics pipeline180(which is ultimately stored in main memory112) is read each frame by display/video interface unit164. Display controller/video interface164provides digital RGB pixel values for display on display56.

Example Input/Output Subsystem

FIG. 6shows an example input/output subsystem. In this example, the input/output subsystem includes a serial interface1000, an external interface1100, a disk interface1200and an audio interface1300. Serial interface1000is used to communicate with controllers52or other devices that can be coupled to one of four serial ports of system50. External interface1100is used to communicate with a variety of devices such as PROM RTC134, modem136, flash memory140, memory card144, etc. via various SPI buses132,142. Disk interface1200is used to communicate with mass storage access device106via a parallel bus130. Audio interface1300is used to stream the audio output data from an audio buffer in main memory112to audio codec122.

In the example embodiment, the external interface1100and disk interface1200have direct access to memory controller152via a bus900. Details of the operation of memory controller152may be found in application Ser. No. 09/726,220, filed Nov. 28, 2000 entitled “Graphics Processing System with Enhanced Memory Controller” and application Ser. No. 09/722,665, filed Nov. 28, 2000 entitled “Method and Apparatus for Accessing Shared Resources.” The contents of each of these applications are incorporated herein by reference. In addition, each one of interfaces1000,1100,1200and1300as well as audio digital signal processor156share a common bus902used to communicate between these components and a bus interface904. The bus interface904, in turn, can be used to arbitrate access to graphics unit180including embedded DRAM702. In the example embodiment, there is also a connection906between DSP156and audio interface1300.

Briefly, disk interface1200provides an interface to mass storage access device106providing a direct memory access capability with interrupt. Serial interface1000provides a serial interface to hand controllers52or other serial devices using automatic controller polling and bulk data mode including a light gun interface. The external interface1100provides multiple serial peripheral interface (SPI) buses as well as a memory mapped area for boot PROM134. Audio interface1300provides an output to audio codec122as well as an input for streaming audio from mass storage access device106. These various interfaces1000,1100,1200,1300provide a shared memory port for direct memory access, with round robin arbitration for access to main memory.

Example Disk Interface

FIG. 7Ashows the external interface of disk interface1200. In the example embodiment, bus130to/from disk interface1200is connected directed to mass storage access device106(which in the example embodiment may comprise an optical disk drive). In the example embodiment, bus130is a parallel bus having a single device on it, with disk interface1200being the only master and the mass storage access device106being the only target device. Disk interface1200communicates with main processor110via a SPU interface1202and an interrupt line1204, and communicates with memory controller152via memory controller interface900.

FIG. 7Bshows a more detailed block diagram of an example disk interface1200. In this example, disk interface1200includes a CPU interface block1206, a memory controller interface block1208, and various buffers including a buffer1210, a buffer1212, a DMA FIFO1214, a direct memory access controller1216, and an interrupt register1218. In addition, disk interface1200includes a disk interface buffer1220for communicating with mass storage access device106via bus130.

In the example embodiment, disk interface1200works primarily on a command packet and direct memory access basis. The disk interface1200operates as a transport for command packets sent to mass storage access device106, and does not actually interpret the packets themselves. Operating on a packet basis allows the development of packet commands and the mechanism for mass storage access device106to be completed separately from the development of the actual physical interface provided by disk interface1200.

Disk interface1200distinguishes between packets that comprise direct memory access commands and packets that comprise immediate commands. Direct memory access commands in the example embodiment begin with a command packet and then cause data to be sent to/from main memory112using direct memory access under control of direct memory access controller1216. Immediate commands in the example embodiment begin with a command packet and result in data being transferred to/from the disk interface immediate data buffer1212. Disk interface1200in the example embodiment includes the following features:support for direct memory access mode commands,support for immediate mode access register command,direct memory access to/from main memory112on 32 byte boundaries/32 byte length,break signal to interrupt current command, maskable interrupt on transaction complete,maskable interrupt on error received from mass storage access device106,25 megabyte per second parallel interface to mask storage access device106,both read and write commands (including BMA supported),bulk data transfer for debug.

As shown inFIGS. 7A and 7B, parallel bus130from disk interface1200to mass storage access device106includes the following signals:a bi-directional, 8-bit wide parallel path DIDD,a signal DIDIR from disk interface1200to mass storage access device106,a DIHSTRBb signal from disk interface1200to mass storage access device106,a DIDSTRBb signal from mass storage access device106to disk interface1200,a DIERR signal from mass storage access device106to disk interface1200,a DIBRK bi-directional signal between disk interface1200and mass storage access device106,a DIRSTb signal from disk interface1200to mass storage access device106,a DICOVER signal from mass storage access device106to disk interface1200.

The following describes the various signals:

NameDirTypeDescriptionDIDD[7:0]I/OLVCMOSDI Data: DI Data bus. Depending upon theDIDR (Direction) signal, the data bus isdriven by main processor 110 or massstorage access device. When mainprocessor 110 is writing data the signalsare outputs and the data should belatched by the mass storage access device106 on the rising edge of the DIHISTRBnsignal. When main processor 110 is read-ing data from the mass storage accessdevice 106, the DIDD[7:0] signals areinputs and the data should be latched onthe rising edge of the DIDSTRBn signal.During reset, this bus can be used forlatching in the configuration. It isimplemented as 8 bit transparent latchescontrolled by sync reset and they samplethe reset state of the DIDD bus and holdthe state on the rising edge of the syncresetb. Currently, bit 0 is used for ROMscramble disable, bits 1–7 are reserved.DIDIROLVCMOSDI Direction: This signal controls thecurrent direction of the DIDD[7:0] databus.DIDRDirection0DI → mass storage accessdevice 106 (DIDD[7:0] areoutputs).1mass access storage device106 → DI (DIDD[7:0] areinputs).DIHSTRBbOLVCMOSDI Host Strobe: DIHSTRBb is an outputand has two different modes of operation,depending on whether the amin processorDI is writing data or reading data. Whenthe DI is writing data, the DIHSTRBnsignal is used to qualify the data output onthe DIDD[7:0] bus, DIDD[7:0] is validon the rising edge of DIHSTRBn. Whenthe DI is reading data, the DIHSTRBn isused as a ready signal, the assertion ofDIHSTRBn indicates that the DI is readyto complete the next data read from themass storage access device 106.DIDSTRBbILCVMOSDI Device Strobe: DIDSTRBb is an inputand has two different modes of operation,depending on whether the main processorDI is writing data or reading data. Whenthe DI is reading data, the DIDSTRBnsignal is used to qualify the data input onthe DIDD[7:0] bus, DIDD[7:0] is valid onthe rising edge of DIDSTRBn. When theDI is writing data, the DIDSTRBn is usedas a ready signal, the assertion ofDIDSTRBn indicates that the mass storageaccess device 106 is ready to complete thenext data write.DIERRbILVCMOSDL Error: DIERRb is an input. The asser-tion of DIERRb by the mass accessstorage device 106 indicates that an errorhas occurred on the mass storage accessdevice. The DI interface will immediatelyhalt the current command. Dependingupon the setting of the DIS[DEINT] bit,an interrupt will also be generated on theassertion of DIERRb. After the DIERRb isasserted, the mass access storage devicewill deassert DIERRb after the nextcommand is received from the host.Typically, the next command is requestsense to check the error status. DIERRb isan edge-triggered signal. The assertion ofDIERRb by the mass storage accessdevice 106 should only occur at the end ofthe command transfer or at the end of thedata transfer, in the case of DMA data, itcan occur in between any 32 Bytestransfer. After DIERRb is asserted,DICR[TSTART] will be cleared andDISR[TCINT] will not be generated forthe current transaction.DIBRKI/OLVCMOSDI Break: DIBRK is an input/output signalODand is an open drain output, externally apull-up resistor is required. Normally thissignal is driven low by the DI, inpreparation for a Break cycle. This signalis driven both by the DI and the massstorage access device 106. When the DIsends a break, it releases control of theDIBRK signal and the signal rises toactive level due to an external pull-up. Themass access storage device 106 is now themaster of the signal. To acknowledge thebreak signal, the mass access storagedevice 106 pulses the signal low. The DIrecognizes the rising edge of DIBRK as abreak acknowledge. After breakacknowledge, the DI drives DIBRK lowagain, in preparation for the next breakcycle. The DI controller will delay sendingthe break signal until the whole commandpacket has been transferred.DICOVERILVCMOSDI Cover: DICOVER is an input signal.This signal is connected to the Disk coverswitch. This signal high indicates thecover is open, this signal low indicates thecover is closed.DIRSTbOLVCMOSDI Reset: DIRSTb is an output signal.When DIRSTb is asserted the massstorage access device 106 will be reset.This signal is not controlled by the DI.This signal is controlled by the mainprocessor General Reset Register in thePI.

FIG. 7Cshows example registers within disk interface1200that are accessible by main processor110. TheFIG. 7Cregisters are each 32-bits wide and fall on 32-bit address boundaries. Main processor110can access these registers through 32-bit or 16-bit reads and writes. In the example embodiment, the base address of these disk interface registers is 0x0C006000.

The following sets forth definitions of example disk interface registers shown inFIG. 7C:

DISR: DI Status RegisterMnemonic: DISROffset: 0x00Size 32 bitsDISRBitsMnemonicTypeResetDescription31:7R0x0Reserved6BRKINTRWC0x0Break Complete Interrupt Statusand clear. On read this bitindicates the current status of thebreak complete interrupt. Thisinterrupt is asserted when a Breakcycle has completed (breakacknowledge received from massstorage access device 106). Whena ‘1’ is written to this register, theinterrupt is cleared.Write:0 = No effect1 = Clear Break Complete Inter-ruptRead:0 = Break Complete Interrupt hasnot been requested1 = Break Complete Interrupt hasbeen requested5BRKINTMSKRW0x0Break Complete Interrupt Mask:Interrupt masking prevents theinterrupt from being sent to themain processor, but does not affectthe assertion of DISR[BRKINT]0 = Interrupt masked1 = Interrupt enabled4TCINTRWC0x0Transfer Complete Interrupt Statusand clear. On read this bit indicatesthe current status of the transfercomplete interrupt. The TransferComplete interrupt is assertedunder the following conditions: aDMA mode transfer has completedtransfer has completed (DMAfinished) or an Immediate modetransfer has completed (transferto/from DIIMMBUF has complet-ed). When a ‘1  is written to thisregister, the interrupt is cleared.The assertion of TCIT is delayeduntil the DIDSTRBb (low) in orderto guarantee the error interruptoccurs before transfer completeinterrupt. If DIERRb is assertedduring the current transaction, thetransaction will be halted andTCINT will not be asserted.Write:0 = No effect1 = Clear Transfer CompleteInterruptRead:0 = Transfer Complete Interrupthas not been request1 = Transfer Complete Interrupthas been request3TCINTMSKRW0x0Transfer Complete Interrupt Mask:Interrupt masking prevents theinterrupt from being sent to themain processor, but does not affectthe assertion of DISR[TCINT]0 = Interrupt masked1 = Interrupt enabled2DEINTRWC0x0Mass Storage Access Device ErrorInterrupt Status: On read this bitindicates the current status of themass storage access device errorinterrupt. To clear this interrupt,two actions must occur. When a‘1’ is written to this register,the internal interrupt is cleared. Toreset the DIERRb signal, acommand must be issued to theexternal DI device. If error occursduring the command packet, thedrive has to delay the errorassertion until the completion ofthe 12 bytes command transfer. Inimmediate mode, if error occursduring the data packet, the errorassertion has to be delayed untilthe completion of the 4 bytes datatransfer. In DMA mode, it has tobe delayed until the completion ofany 32 bytes data transfer.Write:0 = No effect1 = Clear Mass Storage AccessDevice Error InterruptRead:0 = Mass Storage Access DeviceError Interrupt has not beenrequested1 = Mass Storage Access DeviceError Interrupt has been requested1DEINTMSKRW0x0Mass Storage Access Device ErrorInterrupt Mask: Interrupt maskingprevents the interrupt from beingto the main processor, but does notaffect the assertion ofDISR[DEINT]0 = Interrupt masked1 = Interrupt enabled0BRKRWC0x0DI Break: When a ‘1’ is written tothis bit, the DI controller interruptsthe current command and sends abreak signal to the mass storageaccess device. The break signalbreak signal interrupts the currentcommand on the mass storageaccess device. After the breaksequence is complete (see TCINT),a new command may be sent to themass storage access device. Thisbit is cleared after the breakcommand is complete. Note thatDI controller will delay the breaksignal assertion if it is in themiddle of the command transfer.Hence break can only occur duringthe data transfer or when it is idle.Write:0 = No effect1 = Request BreakRead:0 = Break not requested or breakcomplete1 = Break requested and pending

DICVR: DI Cover RegisterMnemonic: DICVROffset: 0x04Size 32 bitsDICVRBitsMnemonicTypeResetDescription31:3R0x0Reserved2CVRINTR0x0Mass Storage Device Cover Inter-rupt Status: On read this bitindicates the current status of theMass Storage Device Cover inter-rupt. When a ‘1’ is written to thisregister, the internal interrupt iscleared. The Mass Storage DeviceCover Interrupt is asserted whenthe status of the DICOVER signalchanges (e.g., when the cover isopened or closed).Write:0 = No effect1 = Clear Cover InterruptRead:0 = Cover Interrupt has not beenrequested1 = Cover Event Interrupt hasbeen requested1CVRINTMSKRW0x0Cover Interrupt Mask: Interruptmasking prevents the interruptfrom being sent to the mainprocessor, but does not affectnot affect the assertion ofDISR[DEINT]0 = Interrupt masked1 = Interrupt enabled0CVRR*Cover Status: This bit reflects thecurrent state of the DICOVERsignal.0 = Cover is closed1 = Cover is open*The reset state of DICVR[CVR] reflects the state of the DICOVER signal.

DICMDBUF0: DI Command Buffer 0Mnemonic: DICMDBUF0Offset: 0x08Size 32 bitsDICMDBUF0BitsMnemonicTypeResetDescription31:24CMDBYTE0RW0x0Command Byte 0: This is byte 0 ofthe command packet that will be sentto the mass storage access devicewhen the command is initiated. (TheDI command is initiated whenDICSR[CMDSTART] is written with‘1’.)23:16CMDBYTE1RW0x0Command Byte 1: SeeDPCMDBUF0[CMDBYTE0]description.15:8CMDBYTE2RW0x0Command Byte 2: SeeDPCMDBUF0[CMDBYTE0]description.7:0CMDBYTE3RW0x0Command Byte 3: SeeDPCMDBUF0[CMDBYTE0]description.

DI DMA Memory Address RegisterMnemonic: DIMAROffset: 0x14Size 32 bitsDIMARBitsMnemonicTypeResetDescription31:26R0x0Reserved.25:5DIMARRW0x0DI DMA Memory Address Register:This register indicates the starting mainmemory address used for teh currentDMA command. The memory addressis the destination address whenDICSR[RW] is set to ‘read’ and is thesource address when set to ‘write’.4:0R0x0These low address bits read back zerosince all DMA transfers are 32 bytealigned. Always write ‘0x0’.

DICR: DI Control RegisterMnemonic: DICROffset: 0x1CSize 32 bitsDICRBitsMnemonicTypeResetDescription31:3R0x0Reserved2RWRW0x0Transfer Read/Write: controls thetransfer direction, read or write to DI.Read indicates data flows from themass storage access device to themain processor. Write indicates datadata flows from main processor to themass storage access device.0 = Read Command1 = Write Command1DMARW0x0DMA Mode: controls whether thepacket data is transferred by usingDMA mode to/from main memory orif packet data is transferred directlyto/from the Immediate Data Buffer.The only mass storage device packetcommand which can use immediatemode is the ‘Register Access’command. When in immediate mode,the DIMAR and DILENGTHregisters are ignored.0 = Immediate Mode1 = DMA Mode0TSTARTRW0x0Transfer Start: When a ‘1’ is writtento this register, the current commandis executed (e.g., DMA command orimmediate command). When readthis bit represents the currentcommand status. This bit is alsocleared after the break completionand after DIERRb is asserted.Write:0 = No Effect1 = Start CommandRead:0 = Transfer Complete1 = Transfer Pending

DIIMMBUF DI Immediate Data BufferMnemonic: DIIMMBUFOffset: 0x20Size 32 bitsDIIMMBUFBitsMnemonicTypeResetDescription31:24REGVAL0RW0x0Register Value 0: This is the dataread/written when an immediatemode command packet is sent.REGVAL0 is the data of the registeraddress +0. When the command is aread command the mass storageaccess device transfers the data fromthe mass storage device register to theDIIMMBUF. When the command isa write command, the data is trans-ferred from the DIIMMBUF to themass storage device register.23:16REGVAL1RW0x0Register Value 1: register address +1. See DIIMMBUF[REGVAL0]description.15:8REGVAL2RW0x0Register Value 2: register address +2. See DIIMMBUF[REGVAL0]description.7:0REGVAL3RW0x0Register Value 3: register address +3. See DIIMMBUF[REGVAL0]description.

DICFG: DI Configuration RegisterMnemonic: DICFGOffset: 0x24Size 32 bitsDICFGBitsMnemonicTypeResetDescription31:8R0x0Reserved7:0CONFIGRDIDDDuring reset, this register latches inDIDD bus. This is a read only reg-ister containing the configurationvalue. Currently, only bit 0 is used.Refer to DIDD bus.
Example Serial Interface

FIGS. 8A and 8Bshow an example serial interface1000. In this particular example, serial interface1000is a single bit serial interface that runs at 250 kHz. This single bit serial interface is similar to the “joybus” control interface used in the prior art Nintendo 64® product manufactured by Nintendo, but there are some differences. Example serial interface1000provides the following features in the example embodiment:four separate 250 kHz serial interfaces for four controllers52,each interface can be accessed in parallel,in controller mode, the last state of the controller52is in a double-buffered processor input/output register so that main processor110can simply read the register to determine the controller state,the controller state is automatically polled by hardware with configurable polling periods,bulk mode (changeable data size),two light gun signals are used to control two separate horizontal/vertical counters to support both flash and shutter light guns,an LCD shutter is supported through automatic polling and serial control commands, andthe serial interface1000can automatically detect the presence of hand controllers52.

FIG. 8Ashows the external interface of serial interface1000. In this example, there are four separate controller ports1002on system50. Each port1002has a pair of input and output pins (shown by the “x” mark blocks inFIG. 8A). The input pin connects directly to an external game controller52in the example embodiment. The output pin in the example embodiment connects to an external open-drain driver (not shown) which in turn connects directly to the external game controller52. In the example embodiment, two of the ports1002have horizontal/vertical latch signals that can be used to latch horizontal/vertical counters within the video interface164. These signals combined with the functionality of serial interface1000provide support for flash and shutter type light guns. The vertical latch and control registers used for this functionality are located in the video interface164in the example embodiment.FIG. 8Ashows each of the four serial ports1002including an SIDI (bi-directional) line and an SIDO (uni-directional) controller output-to-serial interface1000line. The following shows example descriptions of these two signals:

NameDirTypeDescriptionSIDI[3:0]ILVCMOSSerial Interface Data Input: SIDI[3:0] areinput signals, each bit is a separate half-duplex, 250 kbit/s input serial channel. Theserial protocol is an asynchronous interfaceand is self timed, using a pulse widthmodulated signaling scheme.SIDO[3:0]OLVCMOSSerial Interface Data Output: SIDO[3:0] areoutput signals, each bit is a separate half-duplex, 250 kbit/s output serial channel. Theserial protocol is an asynchronous interfaceand is self timed, using a pulse widthmodulated signaling scheme.

FIG. 8Bis a more detailed block diagram of serial interface1000. As shown in this Figure, serial interface1000includes a main processor interface1010, a serial interface communication circuitry and registers1012, a small (128 byte) communication RAM1014, and an input/output buffer arrangement1016for each of the four serial ports1002.

FIG. 8Cshows an example set of registers (register map) used to control serial interface1000in the example embodiment. The base address for these serial interface registers in the example embodiment is 0x0C006400. The following describes each of these various example registers in the example embodiment:

SIC0OUTBUF SI Channel 0 Output BufferMnemonic: SIC0OUTBUFOffset: 0x00Size 32 bitsSIC0OUTBUFBitsMnemonicTypeResetDescription31:24R0x0Reserved23:16CMDRW0x0Command: This byte is the opcodefor the command sent to the control-ler during each command/responsepacket. This is the first data byte sentfrom the SI I/F to the game controllerin the command/response packet.15:8OUTPUT0RW0x0Output Byte 0: This is the first databyte of the command packet. It isthe second data byte sent from the SII/F to the game controller in thecommand/response packet.7:0OUTPUT1RW0x0Output Byte 1: This is the seconddata byte of the command packet. Itis the third data byte sent from theSI I/F to the game controller in thecommand/response packet.

This register is double buffered, so main processor writes to the SIC0OUTBUF will not interfere with the serial interface output transfer. Internally, a second buffer is used to hold the output data to be transferred across the serial interface. To check if SIC0OUTBUF has been transferred to the second buffer, main processor110polls the SISR[WRST0] register. When SIC0OUTBUF is transferred, SISR[WRST0] is cleared.

SIC0INBUF SI Channel 0 Input Buffer HighMnemonic: SIC0INBUFHOffset: 0x04Size 32 bitsSIC0INBUFHBitsMnemonicTypeResetDescription31ERRSTATR0x0Error Status: This bit represents thecurrent error status for the last SIpolling transfer on channel 0. Thisregister is updated after each pollingtransfer on this channel.0 = No error on last transfer1 = Error on last transfer30ERRLATCHR0x0Error Latch: This bit is an error statussummary of the SISR error bits forthis channel. If an error has occurredon a past SI transfer on channel 0(polling or Corn transfer), this bitwill be set. To determine the exacterror, read the SISR register. This bitis actually an ‘or’ of the latchederror status bits for channel 0 in theSISR. The bit is cleared by clearingthe appropriate error status bitslatched in the SISR. The no responseerror indicates that a controller is notpresent on this channel.0 = No errors latched1 = Error latched. Check SISR.29:24INPUT0R0x0Input Byte 0: This is the first databyte of the response packet sent fromthe game controller to the SI I/F forchannel 0. The top two bits of thebyte returning from the controller areassumed to be ‘0’, so they are notincluded.23:16INPUT1R0x0Input Byte 1: This is the second databyte of the response packet sent fromthe game controller to the SI I/F forchannel 0.15:8INPUT2R0x0Input Byte 2: This is the third databyte of the response packet sent fromthe game controllers to the SI I/F forchannel 0.7:0INPUT3R0x0Input Byte 3: This is the fourth databyte of the response packet sent fromthe game controller to the SI I/F forchannel 0.

SIC0INBUFH and SIC0INBUFL are double buffered to prevent inconsistent data reads due to main processor110conflicting with incoming serial interface data. To insure data read from SIC0INBUFH and SIC0INFUBL are consistent, a locking mechanism prevents the double buffer from copying new data to these registers. Once SIC0INBUFH is read, both SIC0INBUFH and SIC0INBUFL are ‘locked’ until SIC0INBUFL is read. While the buffers are ‘locked’, new data is not copied into the buffers. When SIC0INBUFL is read, the buffers become unlocked again.

SIPOLL SI Poll RegisterMnemonic: SIPOLLOffset: 0x30Size 32 bitsSIPOLLBitsMnemonicTypeResetDescription31:26R0x0Reserved25:16XRW0x07X lines register: determines the num-ber of horizontal video lines betweenpolling (the polling interval). Thepolling begins at vsync. 0x07 is theminimum setting (determined by thetime required to complete a singlepolling of the controller). The maxi-mum setting depends on the currentvideo mode (number of lines pervsync) and the SIPOLL[Y] register.This register takes affect after vsync.15:8YRW0x0Y times register: This register deter-mines the number of times the SIcontrollers are polled in a singleframe. This register takes affect aftervsync.7EN0RW0x0Enable channel 0: Enable polling ofchannel 0. When the channel is en-abled, polling begins at the nextvblank. When the channel is disabled,polling is stopped immediately afterthe current transaction. The status ofthis bit does not affect communica-tion RAM transfers on this channel.1 = Polling of channel 0 is enabled0 = Polling of channel 0 is disabled6EN1RW0x0Enable channel 1: See description forSIPOLL[EN0].5EN2RW0x0Enable channel 2: See Description forSIPOLL[EN0].4EN3RW0x0Enable channel 3: See Description forSIPOLL[EN0].3VBCPY0RW0x0Vblank copy output channel 0:Normally main processor writes tothe SIC0OUTBUF register are copiedimmediately to the channel 0 outputbuffer if a transfer is not currentlyin progress. When this bit is asserted,main processor writes to channel 0'sSIC0OUTBUF will only be copied tothe outbuffer on vblank. This is usedto control the timing of commands to3D LCD shutter glasses connected tothe VI.1 = Copy SIC0OUTBUF to outputbuffer only on vblank.0 = Copy SIC0OUTBUF to outputbuffer after writing.2VBCPY1RW0x0Vblank copy output channel 1: SeeDescription for SIPOLL[VBCPY0].1VBCPY2RW0x0Vblank copy output channel 2: SeeDescription for SIPOLL[VBCPY0].0VBCPY3RW0x0Vblank copy output channel 3: SeeDescription for SIPOLL[VBCPY0].

When programming the SICOMCSR after a SICOM transfers has already started (e.g., SICOMCSR[TSTART] is set), the example software reads the current value first, then and/or in the proper data and then write the new data back. The software should not modify any of the transfer parameters (OUTLNGTH, INLNGTH, CHANNEL) until the current transfer is complete. This is done to prevent a SICOM transfer already in progress from being disturbed. When writing the data back, the software should not set the TSTART bit again unless the current transfer is complete and another transfer is required.

FIG. 8Dis an even more detailed overall view of serial interface1000showing the details of serial interface communication circuitry and registers1012. Controllers52aand52b(and52cand52d, if present) are connected to game console54via connector ports1002. Modem1404modulates and demodulates data transferred between the controllers and the console. In the example system, communication between the console and the controllers uses duty-cycle (pulse-width) modulation and the data is communicated over one line. The communication is half-duplex. The byte transfer order is “big-endian” in which within a given multi-byte numeric representation, the most significant byte has the lowest address (i.e., the data is transferred “big-end” first). Controller input/output buffer1016is used for normal data transfers involving controllers52a–52d. As shown inFIG. 8D, input/output buffer1016is arranged as a double buffer. Communication RAM1014is provided for use in variable-size data transfers to and from controllers52a–52d. In the example system, the maximum data size of these variable-size data transfers is 32 words. Of course, the present invention is not limited in this respect. Channel selector circuit1408controls selectors1412a–1412dto selectively connect modem1404to either communication RAM1014or input/output buffer1016. An HV counter latch circuit1406latches the screen position of a flash signal when a trigger input is received from a light gun unit. In the example system shown inFIG. 8, triggers inputs to the HV counter latch circuit1406are provided for connectors1and2only. It will be apparent that trigger inputs may be provided for the other connectors if desired. HV counter latch circuit1406may also be used with light pens connected to connectors1and/or2.

Additional details of the serial interface may be found in application Ser. No. 09/722,664, filed Nov. 28, 2000 of Shimuzu et al. entitled “Controller Interface for a Graphics System”, the contents of which are incorporated herein by reference.

Example External Interfaces

FIG. 9Ais a block diagram of an example external interface logic1100. In the example embodiment, external interface block1100supports three separate external interface channels1102. In the example embodiment, external interface channel1102(0) has a somewhat different configuration than channels1102(1),1102(2). This enables external interface channel1102(0) to support both expansion and on-board devices and peripherals. Each of channels1102provides support for 8-bit word EXI operation. In the example embodiment, the entire ROM134is memory mapped on the external interface channel1102(0), and ROM reads are controlled entirely by hardware for boot support.

The external interface1100in the example embodiment was chosen based on current support by several manufacturers (e.g., Macronix) for the EXI interface on Macronix's CMOS serial flash EEPROM parts. The implemented EXI protocol is based on and compatible with MXIC's MX25L4004 EXI interface. The preferred embodiment example external interface1100includes five separate chip select signals to control five different devices (e.g., ROM/RTC134, flash memory140, expansion modem136, expansion backup memory card144, etc.). Different implementations could provide different numbers of chip selects. The example embodiment external interface1100includes three maskable external interrupts (one for each expansion port/channel1102) that are used to signal EXI transfer complete for each channel. An additional pair of maskable interrupts provided by channels1102(0) and1102(1) is used to provide hot-plug status for peripheral insertion and removal. Each of channels1102support general DMA (direct memory access) transfers in the example embodiment.

Referring toFIG. 9B, the portion1100(0) of external interface1100supporting external interface channel1102(0) includes a CPU interface1104, a memory controller interface1106, a direct memory access controller1108and associated FIFO buffer1110, a ROM control1112, an external interface data buffer/register1114, a bus transceiver1116, and an interrupt register1118.

Block diagrams for the example external channel one interface1100(1) and example external channel two interface1100(2) are shown inFIGS. 9C and 9D, respectively. As can be appreciated from comparingFIGS. 9B,9C and9D, the channel one and channel two structures1100(1),1100(2) are quite similar to one another and each differ from theFIG. 9Bstructure in omitting the ROM control1112(0).

The following table sets forth the various signal descriptions for the signals provided to/from example external interface ports1102:

NameDirTypeDescriptionEXI0DO0OLVCMOSEXI Data Out 0 Channel 0: EXI0DO0 is an outputsignal. EXI0DO0 transmits the serial data out to the slavedevice, the MSB is sent first. The slave should latch dataon the rising edge of the EXI0CLK0.EXI0DI0ILVCMOSEXI Data In 0 Channel 0: EXI0DI0 is an input signal.EXI0DI0 receives the serial data from the slave device, theMSB is received first. The data is latched on the risingedge of the EXI0CLK0.EXI0CLK0OLVCMOSEXI Clock 0 Channel 0: EXI0CLK0 is an output signal.EXI0CLK0 synchronizes the transfer of the EXI0DO0 andEXI0DI0 signals. Data is sent on a byte basis and 1 bytecan be sent in 8 clock cycles. The clock frequency is s/wprogrammable, see EXI0CPR[CLK].EXI0DO1OLVCMOSEXI Data Out 1 Channel 0: EXI0DO1 is an outputsignal. EXI0DO1 transmits the serial data out to the slavedevice, the MSB is sent first. The slave should latch dataon the rising edge of the EXI0CLK1.EXI0DI1ILVCMOSEXI Data In 1 Channel 0: EXI0DI1 is an input signal.EXI0DI1 receives the serial data from the slave device, theMSB is received first. The data is latched on the fallingedge of the EXI0CLK1.EXI0CLK1ILVCMOSEXI Clock 1 Channel 0: EXI0CLK1 is an output signal.EXI0CLK1 synchronizes the transfer of the EXI0DO1 andEXI0DI1 signals. Data is sent on a byte basis and 1 bytecan be sent in 8 clock cycles. The clock frequency is s/wprogrammable, see EXI0CPR[CLK].EXI0CS[2:0]BILVCMOSEXI Chip Select Channel 0 [2:0]B: EXI0CS[2:0]B areoutput signals, active low. The EXI0CS[2:0]B signalsdetermine which EXI device on channel 0 is currentlyselected.EXI0INTBILVCMOSEXI Interrupt Channel 1: EXI0INTB is an input signal,active low, edge triggered. When asserted, this signal willgenerate a main processor interrupt. The interrupt shouldbe cleared by accessing the interrupting device through theEXI interface.EXI0EXTINILVCMOSEXI External In Channel 0: EXI0EXTIN is an inputsignals, when asserted high, it indicates that a device hasbeen plugged into the EXI bus.EXI1DOOLVCMOSEXI Data Out Channel 1: EXI1DO is an output signal.EXI1DO transmits the serial data out to the slave device,the MSB is sent first. The slave should latch data on therising edge of the EXI1CLK.EXI1DIILVCMOSEXI Data In Channel 1: EXI1DI is an input signal.EXI1DI receives the serial data from the slave device, theMSB is received first. The data is latched on the fallingedge of the EXI1CLK.EXI1CLKILVCMOSEXI Clock Channel 1: EXI1CLK is an output signal.EXI1CLK synchronizes the transfer of the EXI1DO andEXI1DI signals. Data is sent on a byte basis and 1 bytecan be sent in 8 clock cycles. The clock frequency is s/wprogrammable, see EXI1CPR[CLK].EXI1CS0BILVCMOSEXI Chip Select Channel 1 0B: EXI1CS0B is an outputsignal, active low. The EXI1CS0B signals determinewhich EXI device on channel 1 is currently selected.EXI1INTBILVCMOSEXI Interrupt Channel 1: EXI1INTB is an input signal,active low, edge triggered. When asserted, this signal willgenerate a CPU interrupt. The interrupt should be clearedby accessing the interrupting device through the EXIinterface.EXI1EXTINILVCMOSEXI External In Channel 1: EXI1EXTIN is an inputsignals, when asserted high, it indicates that device hasbeen plugged into the EXI bus.EXI2DOOLVCMOSEXI Data Out Channel 2: EXI2DO is an output signal.EXI2DO transmits the serial data out to the slave device,the MSB is sent first. The slave should latch data on therising edge of the EXI2CLK.EXI2DIILVCMOSEXI Data In Channel 2: EXI2DO is an input signal.EXI2DI receives the serial data from the slave device, theMSB is received first. The data is latched on the fallingedge of the EXI2CLK.EXI2CLKILVCMOSEXI Clock Channel 2: EXI2CLK is an output signal.EXI2CLK synchronizes the transfer of the EXI2DO andEXI2DI signals. Data is sent on a byte basis and 1 bytecan be sent in 8 clock cycles. The clock frequency is s/wprogrammable, see EXI2CPR[CLK].EXI2INTBILVCMOSEXI Interrupt Channel 2: EXI2INTB is an input signal,active low, edge triggered. When asserted, this signal willgenerate a CPU interrupt. The interrupt should be clearedby accessing the interrupting device through the EXIinterface.EXI2CS0BOLVCMOSEXT Chip Select Channel 2 0B: EXI2CS0B are outputsignals, active low. The EXI2CS0B signals determinewhich EXI device on channel 2 is currently selected.
Serial Peripheral Interface

In one embodiment, main processor110can set the clock rates of these EXI channels to 32 MHz, 16 Mhz, 8 MHz, 4 MHz, 2 MHz and 1 MHz and these clocks rates may be set independently for the different channels. Chip select registers are used to identify the device to which the EXI bus is connected. For the example EXI0, CS0 (Chip Select 0) is set for a connection to an internal real time clock, CS1 is set for a connection to an internal IPL_ROM, and CS2 is set for an external device (modem, voice recognition system and the like). For the example EXI1, CS0 is set for a connection to an internal flash ROM and CS1 is set for an external device (modem, voice recognition system, and the like). Other configurations are possible.

Small size data as command is transferred between CPU registers immediately and large size data is transferred between main memory by direct memory access (DMA).

FIG. 9Eshows example external interface registers. In the example embodiment, the base address for these registers is 0x0C006800. The following show example register definitions:

EXI0MAR: EXI0 DMA Memory Address RegisterMnemonic:EXI0MAROffset:0x04Size32 bitsEXI0MARBitsMnemonicTypeResetDescription31:26R0x0Reserved25:5EXIMARRW0x0EXI DMA Memory Address Register: This registerindicates the starting main memory address used for thecurrent DMA command. The memory address is thedestination address when EXI0CR[RW] is set to ‘read’ andis the source address when set to ‘write’.4:0R0x0These low address bits read back zero since all DMAtransfers are 32B aligned. Always write ‘0x0’.

EXI0LENGTH: EXI0 DMA Transfer Length RegisterMnemonic:EXI0LENGTHOffset:0x08Size32 bitsEXI0LENGTHBitsMnemonicTypeResetDescription31:26R0x0Reserved25:5EXILENGTHRW0x0EXI0 DMA Length Register: This register indicates thelength of the data transfer in bytes for the current DMAcommand.4:0R0x0These low length bits read back zero since all DMAtransfers are multiples of 32B long. Always write ‘0x0’.

EXI0CR: EXI Control Register for channel 0Mnemonic:EXI0CROffset:0x0CSize32 bitsEXI0CRBitsMnemonicTypeResetDescription31:6R0x0Reserved5:4TLENRW0x0Transfer Length: These bits control the amount of datatransferred when an immediate mode transfer (either EXIread or write) is executed.00 = 1 Byte01 = 2 Bytes10 = 3 Bytes11 = 4 Bytes3:2RWRW0x0Read/Write: Controls the direction of the EXI transfer.00 = EXI Read (Transfer from EXI device to mainprocessor)01 = EXI Write (Transfer from main processor to EXIdevice)10 = EXI Read/Write (Transfer both to/from mainprocessor - Invalid for DMA1DMARW0x0Transfer DMA Mode: controls whether the EXI data istransferred by using DMA mode to/from main memory orif EXI data is transferred directly to/from the EXI DataRegister (EXI0DR). When in immediate mode, theEXIMAR and EXILENGTH registers are ignored andEXI0CR[TLEN]indicates the number of bytes to transfer.0 = Immediate Mode1 = DMA Mode0TSTARTRW0x0Transfer Start: When a ‘1’ is written to this register, thecurrent transfer is executed (e.g., DMA transfer orimmediate transfer). When read this bit represents thecurrent transfer status. This bit can be polled by s/w tocheck for transfer complete.Write:0 = No Effect1 = Start EXI0 TransferRead:0 = EXI0 Transfer Complete1 = EXI0 Transfer Pending

EXI0DATA: EXI Data Register for channel 0Mnemonic:EXI0DATAOffset:0x10Size32 bitsEXI0DATABitsMnemonicTypeResetDescription31:24DATA0RW0x0Data 0: This 8-bit register is used to read and write bytepackets directly to and from the EXI bus for channel 0.The EXI0CPR must be configured to assert one of thedevices CS, before the read or write operation can beperformed. The actual read/write operation is triggered bythe EXI0CR[TSTART] register and EXI0CR[DMA] set to‘0’. During an EXI write operation, this is the first bytewritten by the EXI interface. The MSB of the byte[31] isreceived first.23:16DATA1RW0x0Data 1: See description for EXI0DATA[DATA0]. Whenmultiple bytes are transferred this is the second bytetransferred.15:8DATA2RW0x0Data 2: See description for EXI0DATA[DATA0]. Whenmultiple bytes are transferred this is the third bytetransferred.7:0DATA3RW0x0Data 3: See description for EXI0DATA[DATA0]. Whenmultiple bytes are transferred this is the fourth bytetransferred.

EXI1MAR: EXI1 DMA Memory Address RegisterMnemonic:EXI1MAROffset:0x18Size32 bitsEXI1MARBitsMnemonicTypeResetDescription31:26R0x0Reserved25:5EXIMARRW0x0EXI1 DMA Memory Address Register: See descriptionfor EXI0MAR[EXIMAR], for channel 14:0R0x0These low address bits read back zero since all DMAtransfer are 32B aligned. Always write ‘0x0’.

EXI1LENGTH: EXI1 DMA Transfer Length RegisterMnemonic:EXI1LENGTHOffset:0x1CSize32 bitsEXI1LENGTHBitsMnemonicTypeResetDescription31:26R0x0Reserved25:5EXILENGTHRW0x0EXI1 DMA Length Register: See description forEXI0LENGTH[EXILENGTH], for channel 14:0R0x0These low length bits read back zero since all DMAtransfers are multiples of 32B long. Always write‘0x0’.

EXI2CPR: EXI Channel Parameter Register for channel 2Mnemonic:EXI2CPROffset:0x28Size32 bitsEXI2CPRBitsMnemonicTypeResetDescription31:18R0x0Reserved7CS0BRW0x0Chip Select 0: See description for EXI0CPR[CS2B], forchannel 06:4CLKRW0x0Clock Frequency: See description for EXI0CPR[CLK]3TCINTRWC0x0Transfer Complete Interrupt: See description forEXI0CPR[TCINT].2TCINTMSKRW0x0Transfer Complete Interrupt Mask: See description forEXI0CPR[TCINTMSK].1EXIINTRWC0x0EXI2 Interrupt Status: See description forEXI0CPR[EXIINT].0EXIINTMSKRW0x0EXI2 Interrupt Mask: See description forEXI0CPR[EXIINTMSK].

EXI2DATA: EXI Data Register for channel 2Mnemonic: EXI2DATAOffset: 0x38Size 32 bitsEXI2DATABitsMnemonicTYPEResetDescription31:24DATA0RW0x0Data 0: See description forEXI0DATA[DATA0]. This is thefirst byte transferred.23:16DATA1RW0x0Data 1: See description forEXI0DATA[DATA0]. Whenmultiple bytes are transferred thisis the15:8DATA2RW0x0Data 2: See description forEXI0DATA[DATA0]. Whenmultiple bytes are transferred thisis the third byte transferred.7:0DATA3RW0x0Data 3: See description forEXI0DATA[DATA0]. Whenmultiple bytes are transferred thisis the fourth byte transferred.
Example Audio Interfaces

FIG. 10Ashows an example collection of audio interfaces for system50. In the example embodiment, audio interfaces1300include a disk serial interface1302, a digital-to-analog converter interface1304, and an audio interface1306. Digital-to-analog converter (DAC) serial interface1304receives an output from mixer160and converts that output to a form suitable for processing by audio codec122for reproduction on speakers61. The disk serial interface1302receives the streaming audio input from mass storage access device106and provides it to a source block1308. The audio interface1306is capable of reading digital audio from buffers stored in main memory and providing left and right digital audio streams to mixer160.

The example embodiment audio interfaces1300provide support for external 16-bit stereo digital-to-analog converter interfaces running at a fixed 48 kHz sampling rate. The disk serial interface1302provides an optical disk streaming audio input interface providing 16-bit serial interface running at 32 kHz or 48 kHz sampling rate. This allows audio mixer160to mix the streaming audio input at programmable audio volume control. Disk serial interface1302provides sample rate conversion “on the fly” to, for example, change from a 32 kHz sampling rate provided by the mass storage access device106to a 48 kHz sampling rate.

FIG. 10Bshows the external interface of the digital-to-analog converter serial interface1304. This interface streams the audio output data from an audio input buffer to the final audio mixer160in DAC interface. The interface treats the AI buffer as a simple FIFO and expects that buffer to always have the next sample ready. Data is requested at the DAC sample rate (e.g., 48 kHz).

The following are example signal definitions for the various signals shown inFIG. 10B:

NameDirTypeDescriptionAIDOLVCMOSAudio Interface Data Out: AIDO is an output signal.AIDO drives the serial bit stream of the Left/Right Audiodata driven out to the stereo audio DAC, synchronized bythe rising edge of the bit clock AICLKO and AILROsignal which determines if the current word is a leftsample or a right sample.AILROLVCMOSAudio Interface Left Right Out: AILRO is an outputsignal. AILRO is a frame signal for the serial bit streamand determines the left/right channel of the current word.An edge of AILRO also acts as a sample conversionsignal to the DAC. AILRO toggles at the sample ratefrequency (48 kHz).AICLKOLVCMOSAudio Interface Clock Out: AICLKO is an outputsignal. AICLKO is the bit clock for the AIDO serial bitstream.AISDILVCMOSAudio Interface Streaming Data: AISD is an inputsignal AISD is the serial bit stream of the Left Right audiodata driven in from the Disk drive, synchronized by therising edge of the bit clock.AISLROLVCMOSAudio Interface Streaming Left Right: AISLR is anoutput signal. AISLR is a frame signal for the serial bitstream and determines the left/right channel of the currentword. AISLR toggles at the sample rate frequency (32kHz/48 kHz). This signal also controls the flow of theaudio data. After this current stereo sample is received, ifAISLR does not toggle, the Disk assumes that the streamis stopped/paused and sends 0′ as data. The Disk does notbegin sending data until it has received a high-low-highsequence.AISCLKOLCMOSAudio Interface Streaming Clock: AISCLK is anoutput signal. AISCLK is the bit clock for the AISDserial bit stream. The AISCLK is a free running clock.

FIG. 10Cshows example audio interface registers having a base address of 0x0C006C00. The following show example register descriptions:

AICR: Audio Interface Control RegisterMnemonic: AICROffset: 0x00Size 32 bitsAICRBitsMnemonicTypeResetDescription31:6R0x0Reserved5SCRESETRW0x0Sample Counter Reset: When a ‘1’ is written to thisbit the AISLRCNT register is rest to 0x00.Read:always 0Write:0 = No effect1 = Reset AISLRCNT register4AIINTVLDRW0x0Audio Interface Interrupt Valid. This bit controlswhether AIINT is affected by the AIIT registermatching AISLRCNT. Once set, AIINT will hold itslast value.0 = March affects AIINT.1 = AIINT hold last value.3AIINTRW0x0Audio Interface Interrupt Status and clear. On readthis bit indicates the current status of the audiointerface interrupt. When a ‘1’ is written to thisregister, the interrupt is cleared. This interruptindicates that the AIIT register matches theAISLRCNT. This bit asserts regardless of the settingof AICR[AIMSK].Write:0 = No effect1 = Clear Audio Interface InterruptRead:0 = Audio Interface Interrupt has not beenrequested1 = Audio Interface Interrupt has been requested.2AIINTMSKRW0x0Audio Interface Interrupt Mask:0 = Interrupt masked1 = Interrupt enabled1AFRRW0x0Auxiliary Frequency Register: Controls the samplerate of the streaming audio data. When set to 32 kHzsample rate, the SRC will convert the streamingaudio data to 48 kHz. This bit should only bechanged when Streaming Audio is stopped(AICR[PSTAT] set to 0).0 = 32 kHz sample rate1 = 48 kHz sample rate0PSTATRW0x0Playing Status: This bit enables the AISLR clockwhich controls the playing/stopping of audiostreaming. When this bit is AISLRCNT register willincrement for every stereo pair of samples output.0 = Stop or Pause streaming audio (AISLR clockdisabled)1 = Play streaming audio (AISLR clock enabled)

Video interface164in the example embodiment reads color information stored in main memory112and sends it to display56. In more detail, the example video interface164has the following functions:interfaces with an external video encoder (e.g., using a 10-pin—eight data pins plus one clock plus one phase—interface at 27 MHz,generates NTSC, PAL or M-PAL timing,requests pixels from the external frame buffer for display,allows panning and windowing of a display region,provides a video interrupt counter (resettable on field or frame basis),interrupts the main processor110using four programmable timing registers,captures raster position using a pair of light gun latches,performs 4:4:4 RGB to 4:2:2 YCrCb conversion,applies gamma correction to the RGB signal, andinterfaces to a 3D Liquid Crystal Display device.

Main processor110can write instructions to video interface164via a register interface. Video interface164can access main memory external frame buffer113via the graphics memory request arbitration130. Additionally, video interface164provides an output to an external video encoder comprising three sets of signals:video clock,video clock phase, andvideo data.
In the example embodiment, the video clock may be a single line having a 27 MHz rate. The video phase may provide a signal indicating YCb (low) or YCr (high) set on a single line. The video data bus may be eight bits wide, and contain YcrCb data during active display and video timing signals during blanking. An example timing diagram for this bus is shown inFIG. 11A.

Because the example embodiment clamps Y to 0×10 during active display, Y is set to 0×00 during the vertical blanking interval. During that time, CbCr are used for outputting video timing signals that may be encoded as follows:

Because the timing signals are output in the Cb and Cr data only in the example embodiment, they should be expanded back to 13.5 MHz inside of the video encoder. As a result, horizontal sync and burst may be shifted by one pixel. An example timing diagram is shown inFIG. 11B.

In the example embodiment, vertical blanking can end on an even pixel (HBE is even), or it can end on an odd pixel (HBE is odd). In cases where HBE is even, the first chroma sample will be Cb followed by Cr, etc. In cases where HBE is odd, the first chroma sample will be Cr followed by Cb, etc. The diagram ofFIG. 11Cillustrates this.

The video interface164also includes a gun trigger interface consisting of two pins. Each pin detects the instance of a screen flash when a light gun trigger is pulled. Latch circuitry is used to mark the value of a screen timer when a screen flash is registered.

In the example embodiment, in order to simplify the external video encoder, the video interface164generates most of the video timing required by the encoder. Video interface164supports the timing of NTSC, PAL and M-PAL. In the example embodiment, video interface164displays the top field only in a non-interlace mode. Video interface164includes a timing generator responsible for generating video timing, control signals and interrupts. Basically this timing generator consists of two counters: a vertical line counter and a horizontal pixel counter. Once enabled, these counters run continuously at a pixel clock rate of, e.g., 27 MHz. A programmable decoder decodes the outputs of these counters. The decoder operates in four modes: NTSC, PAL, M-PAL, and debug mode. The debug mode is used for testing and simulation.

Video interface164generates addresses required to access pixel data from external frame buffer113. It supports various addressing features including programmable picture size, windowing and pixel resolution pan and scan.

Video interface164also supports horizontal scaling such that a smaller frame buffer can be stretched horizontally to the desired display size. This is achieved by using a 6-tap sampling filter. Each filter tap has eight phases and a zero tap is added to have a total of forty-nine taps in the example embodiment. An output pixel is sampled to a 1/256 sub-pixel grid and is rounded to the nearest ⅛ sub-pixel in the example embodiment. This results in scan line being sampled up to eight times before it is down sampled to a target frequency. See exampleFIG. 11D.

The Y, Cr and Cb components are buffered in three separate shift registers in the example embodiment. Each register is responsible for replicating the first and last pixels for filtering at the boundaries. To ease implementation, Cb and Cr pixels are averaged to 4:4:4 before filtering. This prevents chroma words from reading ahead of luma words. It also allows luma and chroma to share the same control logic.

An internal stepper controls new sample position. The stepper is incremented by a step size every output pixel. The lowest eight bits of the stepper in the example embodiment are rounded to three bits for determining the phase of the filter. Only one bit to the left of the binary pointer is kept. If that bit is toggled, a new pixel is shifted into the pixel registers. The step size in the example embodiment for the stepper is determined by:
step size=floor (256×destination size/source size)/256.

FIG. 11Eshows example shifters, andFIG. 11Fshows an example filter data path. In the example embodiment, the video clock rate is twice the pixel rate (27 vs. 13.5), so the data path is time shared between the three components. The example data path shown inFIG. 11Fconsists of six multipliers, an adder and a set of lookup tables.

The step size and the filter coefficients are set up through the video interface164register interface in the example embodiment. The filter can be programmed to have different cut off frequencies, passband ripple and stopband attenuation. As the filter is symmetrical, only half of it is programmed. To conserve hardware in the filter, the filter coefficients are enveloped so that the center sixteen coefficients are in the range [0,2.0]. The outer32coefficients are in the range [−0.125, 0.125]. Eight times up-sampling is equivalent to a 0.5 Hz lowpass filter at an 8 Hz sampling rate. A conventional SINC filtering function can be used for windowing in the example embodiment.

Video interface164can support a 3D liquid crystal display by merging two frame buffer images (left and right) into a single stream of video. The output interleaves between the left and right pictures every two pixels.FIG. 11Gshows an example timing diagram.

The example embodiment video interface164provides a gun trigger control supporting three sampling modes: 1-field (gun trigger is sampled for one field), 2-field (gun trigger is sampled for two fields), and continuous. In the ½-field mode, the detection mechanism includes the event sequence shown inFIG. 11H. In continuous mode, the trigger is sampled continuously until it is disabled.

In the example embodiment, the first gun trigger in a field latches the value of the display counters and gun triggers occurring in the remainder of the field are ignored.

The following tables describe various control registers within example video interface164. The fourth column in each table shows the power-up reset values.

Display Configuration Register (R/W)

This register set ups and enables VI. Generally, VI should be reset before enabling it. This resets the states into some known values.

ENB0This bit enables the video timing generation and data0request.RST1This bit clears all data request and puts VI into its idle0state.NIN2To select interlace or non-interlace mode. NIN = 0:0interlace, NIN = 1: non-interlace. In non-interlace mode,the top field is drawn at field rate while the bottom fieldis not displayed.DLR3This bit selects the 3D display mode.0LE05:4Gun trigger mode. It enables the Display Latch Register00. When the mode is 1 or 2, it will clear itself (off)automatically when a gun trigger is detected or at timeout. This field is double buffered.0 off1 on for 1 field2 on for 2 fields3 always onLE17:6To enable Display Latch Register 1. See the description0of LE0.0FMT9:8Indicates current video format:00 NTSC1 PAL2 MPAL3 Debug (CCIR656)

This register setups the horizontal timing.

HLW9:0Half line width.—HCE22:16Horizontal sync start to color burst end.—HCS30:24Horizontal sync start to color burst start.—

This register setups the horizontal timing.

HSY6:0Horizontal sync width.—HBE16:7Horizontal sync start to horizontal blanking end.—HBS26:17Half line to horizontal blanking start.—

Vertical Timing Register (R/W)

This register setups the vertical timing. The value ACV is double buffered

EQU3:0Equalization pulse in half lines.—ACV13:4Active video in full lines.—

Odd Field Vertical Timing Register (R/W)

This register sets up the pre-blanking and post-blanking intervals of odd fields. The values PRB and PSB are double buffered.

PRB9:0Pre-blanking in half lines.—PSB25:16Post-blanking in half lines.—

Even Field Vertical Timing Register (R/W)

This register sets up the pre-blanking and post-blanking intervals of even fields. The values PRB and PSB are double buffered.

PRB9:0Pre-blanking in half lines.—PSB25:16Post-blanking in half lines.—

Odd Field Burst Blanking Interval Register (R/W)

This register sets up the burst blanking interval of odd fields.

BS14:0Field 1 start to burst blanking start in half lines.—BE115:5Field 1 start to burst blanking end in half lines.—BS320:16Field 3 start to burst blanking start in half lines.—BE331:21Field 3 start to burst blanking end in half lines.—

Even Field Burst Blanking Interval Register (R/W)

This register sets up the burst-blanking interval of even fields.

BS24:0Field 2 start to burst blanking start in half lines.—BE215:5Field 2 start to burst blanking end in half lines.—BS420:16Field 4 start to burst blanking start in half lines.—BE431:21Field 4 start to burst blanking end in half lines.—

Top Field Base Register L (R/W)

This register specifies the display origin of the top field of a picture in 2D display mode or for the left picture in 3D display mode.

FBB23:0External memory address of the frame buffer image.—XOF27:24Horizontal offset, in pixels, of the left-most pixel—within the first word of the fetched picture.

Top Field Base Register R (R/W)

This register specifies the base address of the top field for the right picture in the 3D display mode. It is not used in 2D display mode.

FBB23:0External memory address of the frame buffer image.—

Bottom Field Base Register L (R/W)

This register specifies the display origin of the bottom field of a picture in 2D display mode or for the left picture in 3D display mode.

FBB23:0External memory address of the frame buffer image.—

Bottom Field Base Register R(R/W)

This register specifies the base address of the bottom field for the right picture in the 3D display mode. It is not used in 2D display mode.

FBB23:0External memory address of the frame buffer image.—

Picture Configuration Register (R/W)

This register specifies the picture configuration.

STD7:0Stride per line in words.—WPL14:8Number of reads per line in words.—

Display Position Register (R)

This register contains the current raster position.

The Horizontal Count is in pixels and runs from 1 to # pixels per line. It is reset to 1 at the beginning of every line.

The Vertical Count is in lines (on a frame basis) and runs from 1 to # lines per frame. It is 1 at the beginning of pre-equalization. This is a frame line count. So for example: for NTSC vcount=264 is the first (full) line in the second field and vcount=525 is the last line in the frame (fields being numbered1–4). For non-interlaced modes vcount is on a field-by-field basis (for NTSC vcount ranges from 1–263).

This counting scheme applies the Display Postion, Display Interrupt, and Display Latch registers.

There are a total of four display interrupt registers (0–3). They are used to generate interrupts to the main processor at different positions within a field. Each register has a separate enable bit. The interrupt is cleared by writing a zero to the status flag (INT).

HCT10:0Horizontal count to generate interrupt.—VCT26:16Vertical count to generate interrupt.—ENB28Interrupt is enabled if this bit is set.0INT31Interrupt status. A “1” indicates that an interrupt is0active.

See the description of Display Interrupt Register 0.

See the description of Display Interrupt Register 0.

See the description of Display Interrupt Register 0.

The Display Latch Register 0 latches the value of the Display Position Register at the rising edge of the gt0 signal. The trigger flag is set if a gun trigger is detected. Writing a zero to the register clear the trigger flag.

See the description of Display Latch Register 0. This register is latched on the rising edge of the gt1 signal.

Output Polarity Register (R/W)

This register sets up the polarity of the out going control signals

Horizontal Scale Register (R/W)

This register sets up the step size of the horizontal stepper.

Scaling Width Register (R/W)

This register is the number of source pixels to be scaled. This is only used when the Horizontal Scaler is enabled. For example, if the image is to be scaled from 320×240 to 640×240, 320 would be written into this register.

This register (in conjunction with the border HBS) sets up a black border around the actual active pixels in debug mode. This was done in order to accommodate certain encoders that only support 720 active pixels. The border HBE and HBS can be programmed for 720 active pixels while the regular HBE and HBS can be programmed to the actual active width. This allows the frame buffer to be of any width without having to manually set up a border in memory. These registers will only take effect if enabled and in debug mode.

This register sets up part of the low pass filter. Taps 0 to 9 are in the reange [0.0, 2.0).

This register sets up part of the low pass filter.

This regisster sets up part of the low pass filter.

This register sets up part of the low pass filter. Taps 9 to tap 24 are in the range [−0.125, 0.125).

This register sets up part of the low pass filter.

This register sets up part of the low pass filter.

This register sets up part of the low pass filter.

VI Clock Select Register (R/W)

This register selects whether the VI will receive a 27 Mhz or a 54 Mhz clock. The 54 Mhz clock is used only with the progressive display modes.

VICLKSEL10−27 Mhz video clk01−54 Mhz video clk

VI DTV Status Register (R)

This register allows software to read the status of two I/O pins.

VISEL2Don't care—
Example Detailed Overall System Embodiment/Implementation

FIG. 12shows an example, detailed embodiment/implementation of system50shown inFIG. 2. In this example implementation:A clock generator1502provides clocking signals to both main microprocessor110and to graphics and audio processor114.A 32-bit address bus and a 64-bit data bus connect the graphics and audio processor114with the main microprocessor110.Main memory112is implemented as a pair of 96-megabit, 1TSRAM chips manufactured by MOSYS, Inc.A multi-pin modem connector1514is used to connect the graphics and audio processor114to an external or internal modem.The boot ROM/real time clock134is coupled to the modem connector1514and shares its bus for communication with the graphics and audio processor114.Three multi-pin EXI connectors1516,1518,1520are used to connect the graphics and audio processor114to various internal and/or external peripheral or other devices.A multi-pin serial connector1510is used to couple the graphics and audio processor114to four controller connectors1523a,1523b,1523c,1523deach of which is connected to a different hand controller52or other external input/output device.A multi-pin disk interface connector1521is used to couple the graphics and audio processor114to the optical disk drive106.The SDRAM126may be provided with a multi-pin expansion connector1549that can be used to expand the 128 MB capacity of SDRAM126with an additional SDRAM expansion module126a.An analog audio/video connector1550having multiple pins communicates analog audio and video information between the graphics and audio processor114and external devices such as, for example, television sets, external display monitors, external loudspeakers or other input/output devices.A digital audio/video connector1552having multiple pins makes the digital and audio interface provided by graphics and audio processor114available to the outside world for connection to any of a variety of different digital video and/or audio devices.

In the example shown, each of connectors1510,1514,1516,1518,1520,1523a–1523d,1549,1550,1552,1521comprises a mating male and female multi-pin connector that allows connections to be made, broken and remade without destructive or permanent processes such as soldering or permanent (non-deformable) crimping. Use of such connectors allows simple and easy connection and disconnection between different modular portions of system50to provide an east-to-manufacture system that can also be expanded, extended and reconfigured in the field without special equipment and involved processes.

Skipping ahead toFIGS. 22–27, those diagrams show an example external view of system50within a housing H. Referring specifically toFIG. 22, housing H includes a front side F, a back side B, a top surface T and a bottom surface Q. Disk drive106may be housed beneath a hinged, openable access cover C that allows the user to insert optical disks62into a housing H. Controller connectors1523a,1523b,1523c,1523cmay be disposed on front surface F (as best shown inFIG. 23). Example connectors1523may each comprise a 10-10 female connector configured to accept a mating 10-10 male connector of appropriate configuration. Such a connector may, for example, couple system50to a wire-connected handheld controller52, a light gun, or any other peripheral device.FIG. 24shows an example peripheral device PD (in this case a receiver for a wireless handheld controller52—but it could be any sort of device) connected to connector1523aand being supported by the connector configuration.

Referring now more particularly toFIG. 25, a digital audio/video connector1552and an analog audio/video connector1550may be disposed on rear surface B of housing H. Each of these connectors1550,1552can output sound and picture signals. However, the digital connector1552provides access to the internal video and audio buses described above—thereby providing additional flexibility in terms of interfacing system50with sophisticated digital audio and/or video equipment. A connector CH of an appropriate configuration can be connected to the digital connector1552, and the other end of such a connector/cable CH′ can be connected to any sort of compatible external equipment. Similarly, a connector (not shown) can be coupled to the analog audio/video connector1550to provide analog audio and video information to a home television set, display monitor or other such equipment. A two-pin power supply connector P may also be provided on rear panel B for inputting DC power to system50. For example, an external 12 volt DC power supply can provide 12 volts DC to connector P, and internal voltage regulation circuitry can regulate this 12 volt DC power supply level down to appropriate lower intermediate voltage levels.

Referring toFIG. 26, the bottom surface U of housing H may include a number of recesses normally covered by covers (not shown). Removal of such covers exposes recesses and associated connectors. For example, a recess R1may include a “high speed port” connector such as the EXI1 connector1518, a recess R2may expose and provide connection to a modem connector1514. Further recess R3may expose and provide connection to an additional serial port such as the EXI2 connector1520as best seen inFIG. 27, peripheral devices P1, P2, P3can be mechanically configured to fit dimensionally within corresponding recess R1, R2, R3so that such peripheral devices can be mounted flush within the generally cubic configuration of housing H. Such peripheral devices P1, P2, P3may include a broadband adapter, a modem, or any other sort of electronic or electrical device providing data inputs and/or outputs over a serial port. Each of the example preferred embodiment connectors provides power so that devices P1, P2, P3need not provide their own power sources. Devices P1, P2, P3can be modular and inserted or removed into corresponding recess R at will to provide different expansion and flush or other functionality for system50. Of course, a connecting cable or wireless communications device could be coupled to any of the serial port connectors1514,1518,1520to allow system50to be interconnected with a free-standing external system or device.

Referring toFIGS. 23,24and28B—28B, additional slots S on front panel F provide access to an additional internal serial bus (e.g., the EXI0 connector1516, not shown). Slots S may be used to insert portable memory devices such as flash memory for example. A “digicard” memory device M shown inFIG. 28Amay include 4 megabits (or 1 half megabit) of flash memory and fits snugly into slot S1underneath the controller port holes1523a,1523bmounted on front panel F. System52also supports SD-digicard adapter A shown inFIG. 28Bthat is compatible stamped-sized, large capacity recording media, SD-memory cards C made by Matsushita. Such SD cards C may offer 64 megabits or more of non-volatile storage. Other cartridge-based memory cards or other devices may also be received by slots S1, S2to interconnect system50with other types of internal or external peripheral or other devices.

Any of the various connectors described herein can be located in the various connector positions shown inFIGS. 22–28Bas desired.

Example Detailed Connection Diagram

FIGS. 12A–12Gshow an example overall detailed connection diagram of system50shown inFIG. 2.FIG. 12Gshows howFIGS. 12A–12Fcan be laid out together to provide an overall system50connection diagram. In this particular, non-limiting detailed implementation, the graphics and audio processor114is implemented on a single chip named “Flipper” that connects to a main processor110named “Gekko” via a 32-bit address bus and a 64-bit data bus. Various other connections as shown inFIG. 12Bare used to maintain coordination between main processor110and the graphics and audio processor114. A crystal-controlled 54 Mhz clock generator1502provides various clocking signals to the main microprocessor110and the graphics and audio processor114(seeFIG. 12A). A reset circuit1504provides a reset signal in response to power on that is applied to the graphics and audio processor114. The graphics and audio processor114supplies reset signals to the main microprocessor110(and other system components). The reset signal provided by reset circuit1504is also applied to a special initial program load (IPL) chip1506that includes an internal boot ROM and a real time clock. In the example embodiment shown, this IPL chip1506includes its own clock generator circuit, and is supplied with a battery signal VCC3 (through an RC time constant circuit1508coupled to a serial bus connector1508). Serial bus connector1508is also coupled to the graphics and audio processor114serial interface1000discussed above. The IPL chip1506upon power-on reset, serially provides boot program instructions to main processor110via graphics and audio processor114upon certain power-on conditions being fulfilled. In the example embodiment, this information is provided via a modem bus1512that is also coupled to a modem connector1514. After power-on reset has completed and the initial program load process is done, the boot ROM portion of chip1506becomes transparent and is no longer accessible by the graphics and audio processor114and/or the main microprocessor110but the real time clock function of chip1506(which battery B1ofFIG. 14and the clock generator coupled to chip1506maintains even during system50power off) allows continual real time tracking of current time and date.

As also shown inFIG. 12D, various external interface connectors1516,1518,1520are coupled to the graphics and audio processor114EXI interfaces132,142discussed above. Connectors1514,1516,1518,1520allow graphics and audio processor114and/or main microprocessor110to access external peripheral or other devices such as modems, broadband adapters, printers, or virtually any other sort of peripheral or other device.

As shown inFIGS. 12E and 12F, main memory112in this particular implementation is implemented as a pair of 1TSRAM chips112a,112bmanufactured by MOSYS, Inc. of Santa Clara, Calif. These high-speed memory chips112a,112bshare a common 21-bit address bus1530in the example embodiment. Each memory chip112a,112bhas its own dedicated 32-bit data bus1532and dedicated clocking and other signals as shown. The memory read/write line1534, the MEMADSOB, line1536, and the MEMREFSH line1538are also shared between these two chips112a,112bin this example embodiment. Additional expansion could be provided in another implementation if desired.

FIG. 12Cshows example connections with SDRAM126including a 13-bit address bus and an 8-bit data bus along with various read, write, clocking and other control signals. In the example embodiment, an expansion connection is provided to allow expansion of the SDRAM126to provide additional memory capacity.FIG. 12Calso shows example connections between the graphics and audio processor114and example analog audio/video connector1550and example digital video/audio connector1552. In the example embodiment, the video encoder and audio codec120,122are implemented in a common single chip package1554. An audio amplifier128amplifies the stereo left and right audio outputs for application to the analog audio/video connector1550.

Example Detailed Serial (Joybus) Hand Controller Connections

FIGS. 13A–13bshow an example detailed implementation of a connection between an example serial connector1510and the graphics and audio processor114, andFIG. 14shows an example detailed connection between the serial connector1510and controller connectors1523for hand controllers52or other devices. Referring toFIG. 13B, the example serial interface described above in connection withFIGS. 8A–8D(including the various serial data buses SIDO0–SIDO3, SIDI0–SIDI3, and the two gun trigger signals GUNTRG0, GUNTRG1) are coupled via transistor-based isolation buffers1602a–1602dto pins3,4,6,7,9and10of a multi-pin serial interface connector1510. A reset signal received by graphics and audio processor114is also coupled to this same serial interface connector1510at pin2in the example embodiment. In addition, connector1510includes a battery input at pin1that is applied to the boot ROM/RTC arrangement134discussed above. Example connector1510also makes available various supply voltages (e.g., 3.3 volts at pin8and 5 volts at pine12) as well as ground potential (e.g., at pins5and11). Referring toFIG. 12, a mating multi-pin connector1510ais used to connect connector1510to the various controller input port connectors1523a,1523b,1523c,1523d. A battery B1may be supplied for connection to pin1, and a reset switch SW1may be connected to pin2. The various controller connectors1523may be wired similarly with pin3carrying bi-directional serial data, pin4(if applicable—only two connectors1523a,1523b, provide this capability in the example embodiment) carrying the gun trigger signals, and with power supply and ground voltages being made available as shown.

Example External Interface Connections

FIGS. 15A–15Cshow example external interface connections for use in coupling the example external interfaces described above in connection withFIGS. 9A–9Eto external interface connectors1516,1518,1520, respectively. In the example embodiment, the external interface connections for EXI0 and EXI1 are virtually identical. As shown inFIGS. 15A and 15B, the external interface buses described above in connection withFIGS. 9A,9B and9C are isolated with various isolation circuitry and coupled to respective pins of a multi-pin connector (1516for the EXI0 bus,1518for the EXI1 bus) with pin assignments as follows:

FIG. 15Cshows an example connection between the external interface channel2shown inFIG. 9Dand an example 8-pin connector1520having the following pin assignments.

The connector arrangements shown inFIGS. 15A–15Callow the graphics and audio processor114to communicate with three different peripheral or other devices simultaneously over separate external interface buses. Such external devices can receive data from the graphics and audio processor114, provide data to the graphics and audio processor, or both. The main microprocessor110can access these devices via the graphics and audio processor114. Any sort of device may be coupled to system50via these connectors15126,1518and/or1520.

Example Modem Connection

In the example embodiment, system50further includes a modem connector1514intended to be coupled directly to an internal and/or external modem of conventional design. In the example embodiment, an additional (fourth) external interface bus and associated external interface is provided by graphics and audio processor114for communicating with a modem via connector1514. Devices other than a modem may also be coupled to the modem connector1514. In the example embodiment, this modem bus is bidirectional with three lines (EXID00, EXI0CLK0 and EXICSB2) being uni-directionally buffered as outputs to the modem connector1514and a further line EXI0D10 being uni-directionally buffered as an input to the graphics and audio processor114. In the example embodiment, the uni-directional buffer provided on the EXID10 line is controlled by the graphics and audio processor114via the EXI0CSB2 line (the latter line of which is also passed on as a signal to connector1514). The other buffers in the example embodiment are controlled by an EXTIN signal asserted by a device coupled to the modem connector1514. Modem connector1514may provide the following example pin assignments for a 12-pin connector:

As shown inFIG. 12, the modem bus and associated interface is shared with the initial program load/boot ROM/real time clock chip134. This sharing is not a problem since system50will generally not be trying to use a modem at the same time that it is booting up.

Example External Digital Video/Audio Connections

FIGS. 17A and 17Bshow example connections which connect the graphics and audio processor114digital audio and video interface (seeFIGS. 10A–11H) to a digital audio/video connector1552(FIGS. 17A,17B) and/or to an analog audio/video connector1550(seeFIG. 18). As shown inFIGS. 17A and 17B, in the example embodiment, system50provides external access to the digital video and audio bus via a digital video and audio connector1552. In the example embodiment, connector1552receives the 8-bit video bus (e.g., at pins7,9,10,12,13,15,16and18) and receives the digital audio serial bus (e.g., at pines19,21,22). In addition, connector1552may receive a video selection signal FSEL0 (at pin1), video clocking signals (e.g., a 27 Mhz signal at pin6and a 54 Mhz signal at pin2) and an additional VICR signal (e.g., at pine3). Connector1552may also make available two different power supply voltages (e.g., a 12 volt power supply voltage at pin5and a 3.3 volt power supply voltage at pin17) in addition to various ground potential connections (e.g., at pins4,8,11,14, and20).

The digital video/audio connector1552shown inFIGS. 17A and 17Ballows any sort of digital or digitized video and/or audio signal consumer and/or producer to be connected directly to the graphics and audio processor114digital video and/or audio buses. For simpler devices such as home television sets and other displays and/or audio output devices, it may be preferable just to connect isolated analog video and audio outputs to such external devices via the analog audio/video connector1550. In the example embodiment, this analog connector1550makes amplified, isolated left and right audio outputs available (e.g., at pins11and12) as well as composite and luminance/chrominance video signals in analog form available (e.g., at pines7,8and9).

Example SDRAM Expansion

FIGS. 19A–19Dshow an example connector1549that may be used to expand the capacity of SDRAM memory chip126by connecting one or more additional memory chips. In the example embodiment, connector1549may comprise a 36-pin connector having the following example pin out configuration:

FIGS. 20A–20Bshow an example disk connector1521used to connect the graphics and audio processor114to a optical disk drive106. The following pin outs may be used:

In the example embodiment, system50may also include a power supply connector1700used to connect power to power all of the components within the system. An example power supply connector is shown inFIG. 4including the following example pin outs:

In the example embodiment, a temperature compensation chip1702is connected to connector17pin19.

Other Example Compatible Implementations

Certain of the above-described system components50could be implemented as other than the home video game console configuration described above. For example, one could run graphics application or other software written for system50on a platform with a different configuration that emulates system50or is otherwise compatible with it. If the other platform can successfully emulate, simulate and/or provide some or all of the hardware and software resources of system50, then the other platform will be able to successfully execute the software.

As one example, an emulator may provide a hardware and/or software configuration (platform) that is different from the hardware and/or software configuration (platform) of system50. The emulator system might include software and/or hardware components that emulate or simulate some or all of hardware and/or software components of the system for which the application software was written. For example, the emulator system could comprise a general purpose digital computer such as a personal computer, which executes a software emulator program that simulates the hardware and/or firmware of system50.

Some general purpose digital computers (e.g., IBM or MacIntosh personal computers and compatibles) are now equipped with 3D graphics cards that provide 3D graphics pipelines compliant with DirectX or other standard 3D graphics command APIs. They may also be equipped with stereophonic sound cards that provide high quality stereophonic sound based on a standard set of sound commands. Such multimedia-hardware-equipped personal computers running emulator software may have sufficient performance to approximate the graphics and sound performance of system50. Emulator software controls the hardware resources on the personal computer platform to simulate the processing, 3D graphics, sound, peripheral and other capabilities of the home video game console platform for which the game programmer wrote the game software.

FIG. 29Aillustrates an example overall emulation process using a host platform1201, an emulator component1303, and a game software executable binary image provided on a storage medium62. Host1201may be a general or special purpose digital computing device such as, for example, a personal computer, a video game console, or any other platform with sufficient computing power. Emulator1303may be software and/or hardware that runs on host platform1201, and provides a real-time conversion of commands, data and other information from storage medium62into a form that can be processed by host1201. For example, emulator1303fetches “source” binary-image program instructions intended for execution by system50from storage medium62and converts these program instructions to a target format that can be executed or otherwise processed by host1201.

As one example, in the case where the software is written for execution on a platform using an IBM PowerPC or other specific processor and the host1201is a personal computer using a different (e.g., Intel) processor, emulator1203fetches one or a sequence of binary-image program instructions from storage medium1305and converts these program instructions to one or more equivalent Intel binary-image program instructions. The emulator1203also fetches and/or generates graphics commands and audio commands intended for processing by the graphics and audio processor114, and converts these commands into a format or formats that can be processed by hardware and/or software graphics and audio processing resources available on host1201. As one example, emulator1303may convert these commands into commands that can be processed by specific graphics and/or or sound hardware of the host1201(e.g., using standard DirectX, OpenGL and/or sound APIs).

An emulator1303used to provide some or all of the features of the video game system described above may also be provided with a graphic user interface (GUI) that simplifies or automates the selection of various options and screen modes for games run using the emulator. In one example, such an emulator1303may further include enhanced functionality as compared with the host platform for which the software was originally intended.

FIG. 29Billustrates an emulation host system1201suitable for use with emulator1303. System1201includes a processing unit1203and a system memory1205. A system bus1207couples various system components including system memory1205to processing unit1203. System bus1207may be any of several types of bus structures including a memory bus or memory controller, a peripheral bus, and a local bus using any of a variety of bus architectures. System memory1207includes read only memory (ROM)1252and random access memory (RAM)1254. A basic input/output system (BIOS)1256, containing the basic routines that help to transfer information between elements within personal computer system1201, such as during start-up, is stored in the ROM1252. System1201further includes various drives and associated computer-readable media. A hard disk drive1209reads from and writes to a (typically fixed) magnetic hard disk1211. An additional (possible optional) magnetic disk drive1213reads from and writes to a removable “floppy” or other magnetic disk1215. An optical disk drive1217reads from and, in some configurations, writes to a removable optical disk1219such as a CD ROM or other optical media. Hard disk drive1209and optical disk drive1217are connected to system bus1207by a hard disk drive interface1221and an optical drive interface1225, respectively. The drives and their associated computer-readable media provide nonvolatile storage of computer-readable instructions, data structures, program modules, game programs and other data for personal computer system1201. In other configurations, other types of computer-readable media that can store data that is accessible by a computer (e.g., magnetic cassettes, flash memory cards, digital video disks, Bernoulli cartridges, random access memories (RAMs), read only memories (ROMs) and the like) may also be used.

A number of program modules including emulator1303may be stored on the hard disk1211, removable magnetic disk1215, optical disk1219and/or the ROM1252and/or the RAM1254of system memory1205. Such program modules may include an operating system providing graphics and sound APIs, one or more application programs, other program modules, program data and game data. A user may enter commands and information into personal computer system1201through input devices such as a keyboard1227, pointing device1229, microphones, joysticks, game controllers, satellite dishes, scanners, or the like. These and other input devices can be connected to processing unit1203through a serial port interface1231that is coupled to system bus1207, but may be connected by other interfaces, such as a parallel port, game port Fire wire bus or a universal serial bus (USB). A monitor1233or other type of display device is also connected to system bus1207via an interface, such as a video adapter1235.

System1201may also include a modem1154or other network interface means for establishing communications over a network1152such as the Internet. Modem1154, which may be internal or external, is connected to system bus123via serial port interface1231. A network interface1156may also be provided for allowing system1201to communicate with a remote computing device1150(e.g., another system1201) via a local area network1158(or such communication may be via wide area network1152or other communications path such as dial-up or other communications means). System1201will typically include other peripheral output devices, such as printers and other standard peripheral devices.

In one example, video adapter1235may include a 3D graphics pipeline chip set providing fast 3D graphics rendering in response to 3D graphics commands issued based on a standard 3D graphics application programmer interface such as Microsoft's DirectX 7.0 or other version. A set of stereo loudspeakers1237is also connected to system bus1207via a sound generating interface such as a conventional “sound card” providing hardware and embedded software support for generating high quality stereophonic sound based on sound commands provided by bus1207. These hardware capabilities allow system1201to provide sufficient graphics and sound speed performance to play software stored in storage medium1305.