Digital detector for ATSC digital television signals

A Wireless Regional Area Network (WRAN) receiver comprises a transceiver for communicating with a wireless network over one of a number of channels, and an Advanced Television Systems Committee (ATSC) signal detector for use in forming a supported channel list comprising those ones of the number of channels upon which an ATSC signal was not detected, wherein the ATSC signal detector is a threshold-based detector and detects an ATSC signal as a function of at least one threshold, and wherein the ATSC signal detector is responsive to at least one of a carrier tracking loop lock signal, a symbol timing recovery lock signal and a synchronization (sync) lock signal.

BACKGROUND OF THE INVENTION

The present invention generally relates to communications systems and, more particularly, to wireless systems, e.g., terrestrial broadcast, cellular, Wireless-Fidelity (Wi-Fi), satellite, etc.

A Wireless Regional Area Network (WRAN) system is being studied in the IEEE 802.22 standard group. The WRAN system is intended to make use of unused television (TV) broadcast channels in the TV spectrum, on a non-interfering basis, to address, as a primary objective, rural and remote areas and low population density underserved markets with performance levels similar to those of broadband access technologies serving urban and suburban areas. In addition, the WRAN system may also be able to scale to serve denser population areas where spectrum is available. Since one goal of the WRAN system is not to interfere with TV broadcasts, a critical procedure is to robustly and accurately sense the licensed TV signals that exist in the area served by the WRAN (the WRAN area).

In the United States, the TV spectrum currently comprises ATSC (Advanced Television Systems Committee) broadcast signals that co-exist with NTSC (National Television Systems Committee) NTSC broadcast signals. The ATSC broadcast signals are also referred to as digital TV (DTV) signals. Currently, NTSC transmission will cease in 2009 and, at that time, the TV spectrum will comprise only ATSC broadcast signals.

Since, as noted above, one goal of the WRAN system is to not interfere with those TV signals that exist in a particular WRAN area, it is necessary to efficiently detect the presence of an ATSC DTV signal down to 20 dB (decibels) below threshold of visibility (TOV) for the ATSC DTV signal, in order to be able to avoid harmful interference to licensed ATSC DTV signals in a particular channel.

SUMMARY OF THE INVENTION

In accordance with the principles of the invention, an apparatus comprises a transceiver for communicating with a wireless network over one of a number of channels, and an Advanced Television Systems Committee (ATSC) signal detector for use in forming a supported channel list comprising those ones of the number of channels upon which an ATSC signal was not detected, wherein the ATSC signal detector is a threshold-based detector and detects an ATSC signal as a function of at least one threshold, and wherein the ATSC signal detector is responsive to at least one of a carrier tracking loop lock signal, a symbol timing recovery lock signal and a synchronization (sync) lock signal.

In an illustrative embodiment of the invention, the receiver is a Wireless Regional Area Network (WRAN) receiver.

In view of the above, and as will be apparent from reading the detailed description, other embodiments and features are also possible and fall within the principles of the invention.

DETAILED DESCRIPTION

Other than the inventive concept, the elements shown in the figures are well known and will not be described in detail. Also, familiarity with television broadcasting, receivers and video encoding is assumed and is not described in detail herein. For example, other than the inventive concept, familiarity with current and proposed recommendations for TV standards such as NTSC (National Television Systems Committee), PAL (Phase Alternation Lines), SECAM (SEquential Couleur Avec Memoire) and ATSC (Advanced Television Systems Committee) (ATSC) is assumed. Further information on ATSC broadcast signals can be found in the following ATSC standards: Digital Television Standard (A/53), Revision C, including Amendment No. 1 and Corrigendum No. 1, Doc. A/53C; andRecommended Practice: Guide to the Use of the ATSC Digital Television Standard(A/54). Likewise, other than the inventive concept, transmission concepts such as eight-level vestigial sideband (8-VSB), Quadrature Amplitude Modulation (QAM), orthogonal frequency division multiplexing (OFDM) or coded OFDM (COFDM)), and receiver components such as a radio-frequency (RF) front-end, or receiver section, such as a low noise block, tuners, and demodulators, correlators, leak integrators and squarers is assumed. Similarly, other than the inventive concept, formatting and encoding methods (such as Moving Picture Expert Group (MPEG)-2 Systems Standard (ISO/IEC 13818-1)) for generating transport bit streams are well-known and not described herein. It should also be noted that the inventive concept may be implemented using conventional programming techniques, which, as such, will not be described herein. Finally, like-numbers on the figures represent similar elements.

Before describing the inventive concept, a brief description of an ATSC DTV signal is provided in conjunction withFIGS. 1 and 2. DTV data is modulated using 8-VSB (vestigial sideband). In an ATSC DTV signal, besides the eight-level digital data stream, a two-level (binary) four-symbol data segment sync is inserted at the beginning of each data segment. An ATSC data segment is shown inFIG. 1. The ATSC data segment consists of 832 symbols: four symbols for data segment sync, and 828 data symbols. The data segment sync pattern is a binary 1001 pattern, as can be observed fromFIG. 1. Multiple data segments (313 segments) comprise an ATSC data field, which comprises a total of 260,416 symbols (832×313). The first data segment in a data field is called the field sync segment. The structure of the field sync segment is shown inFIG. 2, where each symbol represents one bit of data (two-level). In the field sync segment, a pseudo-random sequence of 511 bits (PN511) immediately follows the data segment sync. After the PN511 sequence, there are three identical pseudo-random sequences of 63 bits (PN63) concatenated together, with the second PN63 sequence being inverted every other data field.

Turning now toFIG. 3, an illustrative Wireless Regional Area Network (WRAN) system100incorporating the principles of the invention is shown. WRAN system100serves a geographical area (the WRAN area) (not shown inFIG. 3). In general terms, a WRAN system comprises at least one base station (BS)105that communicates with one, or more, customer premise equipment (CPE)150. The latter may be stationary or mobile. CPE150is a processor-based system and includes one, or more, processors and associated memory as represented by processor190and memory195shown in the form of dashed boxes inFIG. 3. In this context, computer programs, or software, are stored in memory195for execution by processor190. The latter is representative of one, or more, stored-program control processors and these do not have to be dedicated to the transmitter function, e.g., processor190may also control other functions of CPE150. Memory195is representative of any storage device, e.g., random-access memory (RAM), read-only memory (ROM), etc.; may be internal and/or external to CPE150; and is volatile and/or non-volatile as necessary. The physical layer of communication between BS105and CPE150, via antennas110and155, is illustratively OFDM-based, via transceiver185, and is represented by arrows111. To enter a WRAN network, CPE150may first “associate” with BS110. During this association, CPE150transmits information via transceiver185on the capability of CPE150to BS105via a control channel (not shown). The reported capability includes, e.g., minimum and maximum transmission power, and a supported channel list for transmission and receiving. In this regard, CPE150performs “channel sensing” in accordance with the principles of the invention to determine which TV channels are not active in the WRAN area. The resulting supported channel list for use in WRAN communications is then provided to BS105.

As noted earlier, a WRAN system makes use of unused television (TV) broadcast channels in the TV spectrum. In this regard, the WRAN system performs “channel sensing” to determine which of these TV channels are actually active (or “incumbent”) in the WRAN area in order to determine that portion of the TV spectrum that is actually available for use by the WRAN system. In particular, it is necessary for elements of the WRAN system to efficiently detect the presence of an ATSC DTV signal down to 20 dB (decibels) below threshold of visibility (TOV) for the ATSC DTV signal, in order to be able to avoid harmful interference to licensed ATSC DTV signals in a particular channel. In the description that follows, it is assumed that the ATSC DTV signal is embedded in noise or other interference with a D/U (Desired-to-Undesired) signal power ratio of at least −5 dB. In these extreme conditions, an ATSC receiver will not work. However, an ATSC signal detector conforming to the principles of the invention will be able to detect an ATSC DTV signal under such extreme conditions.

An illustrative portion of a receiver200for use in CPE150is shown inFIG. 4. Only that portion of receiver200relevant to the inventive concept is shown. In particular, receiver200includes analog-to-digital converter (ADC)205, automatic gain controller (AGC)210, demodulator225, sync detector230and decision device240. Receiver200is controlled by a processor, e.g., processor190ofFIG. 3. Input signal201represents a digital VSB modulated signal in accordance with the above-mentioned “ATSC Digital Television Standard” and is centered at a specific IF (Intermediate Frequency) of fIFHertz. Input signal201is provided by a tuner (not shown), which is tuned to a particular DTV channel. Input signal201is sampled by ADC205for conversion to a sampled signal, which is then gain controlled by AGC210. The latter is noncoherent and is a mixed mode (analog and digital) loop that provides a first level of gain control (prior to carrier tracking), symbol timing and sync detection of the VSB signal included within signal201. AGC210basically compares the absolute values of the sampled signal from ADC205against a predetermined threshold, accumulates the error and feeds that information, via signal212, back to the tuner for gain control prior to ADC205. As such, AGC210provides a gain controlled signal211to demodulator225. The latter demodulates gain controlled signal211to provide demodulated signal226, carrier tracking loop (CTL) lock signal227and symbol timing recovery (STR) lock signal228. In particular, demodulator225comprises a carrier tracking loop (CTL) and a symbol timing recovery (STR) loop (both described below) for performing carrier tracking and symbol timing recovery. In this regard, CTL lock signal227and STR lock signal228represent demodulator lock conditions for the CTL and STR loop, respectively, and, e.g., may be a function of the loop filter integrator outputs inside both the CTL and STR loop. CTL lock signal227and STR lock signal228are provided to decision device240. With regard to the remaining output signal of demodulator225, demodulated signal226, this signal is processed by sync detector230. Sync detector230detects either the ATSC data segment sync, ATSC field segment sync, or both of these syncs and, upon detection, provides sync lock signal231to decision device240. As described further below, decision device240monitors one, or more, of CTL lock signal227, STR lock signal228and sync lock signal231to determine whether or not an ATSC DTV signal has been detected in the DTV channel of interest. Decision device240provides information regarding the detection of an ATSC DTV signal via signal241.

An illustrative ATSC pilot carrier based CTL300for use in demodulator225is shown inFIG. 5. CTL300recovers a coherent carrier and downconverts the signal to baseband using a digital phase locked loop. CTL300includes delay/Hilbert filter element305, complex multiplier310, phase detector315, loop filter320, lock detector345, combiner (or adder)325, numerically controlled oscillator (NCO)330, sine/cosine (sin/cos) table335and DC remover340. It should be noted that other carrier tracking loop designs are possible, as long as they achieve the same performance. Delay/Hilbert filter element305includes a Hilbert filter and an equivalent delay line that matches the Hilbert filter processing delay. As known in the art, a Hilbert Filter is an all-pass filter that introduces a −90° phase shift to all input frequencies greater than 0 (and a +90° degree phase shift to negative frequencies). The Hilbert filter allows recovery of the quadrature component of the output signal211from AGC210. Recovery of the quadrature component is necessary because both the in-phase and quadrature components of the signal are needed in order for the CTL to correct the phase and lock to the ATSC pilot carrier signal. As such, the output signal306from delay/Hilbert filter element305is a complex sample stream comprising in-phase (I) and quadrature (Q) components. It should be noted that complex signal paths are shown as double lines in the figures. Following the Hilbert filter block, the signal is processed by a digital CTL (310,315,320,325,330and335), which processes the complex sample stream to down convert the IF signal (211) to baseband, and to correct for frequency offsets between the transmitter ATSC carrier and the receiver tuner Local Oscillator (LO) (not shown) (e.g., see, United States Advanced Television Systems Committee, “Guide to the Use of the ATSC Digital Television Standard”, Document A/54, Oct. 4, 1995; and U.S. Pat. No. 6,233,295 issued May 15, 2001 to Wang, entitled “Segment Sync Recovery Network for an HDTV Receiver”). The digital CTL is a second order loop, which in theory, allows for frequency offsets to be tracked with no phase error. In practice, phase error is a function of the loop bandwidth, input phase noise and implementation constraints like bit size of the data, integrators and gain multipliers.

Turning now to the particular components of the digital CTL, complex multiplier310receives the complex sample stream of signal306and performs de-rotation of the complex sample stream by a calculated phase angle. In particular, the in-phase and quadrature components of signal306are rotated by a phase. The latter is provided by signal336, which represents particular sine and cosine values provided by sin/cos table335. The output signal from complex multiplier310is down-converted received signal311, which represents a de-rotated complex sample stream. As can be observed fromFIG. 5, the down-converted received signal310is applied to DC remover340and phase detector315.

With respect to phase detector315, this element computes any phase offset still present in the down-converted signal311and provides a phase offset signal indicative thereof. This computation can be performed with a “I*Q” or a “sign(I)*Q” function. The phase offset signal provided by phase detector315is applied to loop filter320, which is a first order filter with proportional-plus-integral gains. Ignoring for the moment combiner325, the loop filtered output signal from loop filter320is applied to NCO330. The latter is an integrator, which takes as an input signal a frequency, and provides an output signal representative of phase angles associated with the input frequency. However, in order to increase the acquisition speed, the NCO is fed a frequency offset, FOFFSET, corresponding to FPILOT(where FPILOTis the pilot frequency), which is added to the loop filter output signal via combiner325to provide a combined signal to NCO330. NCO330provides an output phase angle signal331to sin/cos table335, which provides the associated sine and cosine values to complex multiplier310for de-rotation of signal306to provide down-converted received signal311. As noted above, down-converted received signal311is also provided to DC remover340. When CTL300is locked to a received ATSC DTV signal, the ATSC pilot carrier present in the received ATSC DTV signal creates a DC offset in the down-converted received signal311. DC remover340removes the DC offset to provide demodulated signal226. Also, as noted earlier, it should also be observed fromFIG. 5that loop filter320feeds lock detector345, which provides lock signal227, which is indicative of when demodulator225has acquired an ATSC DTV pilot carrier.

Referring now toFIG. 6, an illustrative STR loop400is shown. STR loop400comprises interpolator405, timing detector410, timing loop filter415, lock detector425and NCD420. STR400is used to re-sample the demodulated signal, lock to the incoming VSB symbol data and provide a symbol rate clock for all subsequent demodulator stages downstream (not shown). Other than the inventive concept, the elements of STR400are well-known and not described further herein. Demodulated signal226first enters interpolator filter405and gets re-sampled at the symbol data rate. This re-sampled data is then sent to the digital phase locked loop (410,415and420). This loop is comprised of timing detector410, a timing loop filter415and an numerically controlled delay (NCD)420. The timing detector410performs the phase detector function of the digital phase loop (e.g., see Floyd M. Gardner, “A BPSK/QPSK Timing-Error Detector for Sample Receivers”, IEEE Transactions on Communications, Vol. COM-34, no. 5, pp. 423-29, May 1986). The phase detector output from timing detector410is then sent, via timing loop filter415, to NCD420. The latter performs the digital voltage controlled oscillator (VCO) function and the output signal from NCD420is provided to the input of interpolator405to control the interpolator delay. Finally, it should also be observed fromFIG. 6that timing loop filter415feeds lock detector425, which provides lock signal228, which is indicative of when STR loop400has acquired an ATSC symbol stream.

As previously mentioned, the ATSC signal is transmitted with embedded sync information. The data is divided into segments and then groups of segments are divided into fields. The purpose of the sync detection circuitry230inFIG. 4is to locate these sync signals within the data and provide indicator signals231identifying a locked condition. There are two basic algorithms to choose from: segment and field detection. The field sync location can be more accurate, however, it may take longer to acquire sync, since field syncs are approximately 25 ms apart. The segment sync algorithm can be much faster since the segment syncs occur more often, however, it may not be as accurate. In an illustrative sync detector, both algorithms may be based on correlation against the known sync pattern and appropriate averaging to insure reliability (see the above noted U.S. Pat. No. 6,233,295).

Turning now toFIG. 7, an illustrative flow chart for channel sensing in accordance with the principles of the invention for use in receiver200is shown. In step605, receiver200tunes to one of a number of ATSC DTV channels. In step265, receiver200checks if an ATSC DTV signal is detected (described further below). If an ATSC DTV signal is detected, receiver200marks the ATSC DTV channel as occupied in step620. On the other hand, if an ATSC DTV signal is not detected, receiver200marks the ATSC DTV channel as clear in step615. In either case, receiver200checks if the scan, or channel sensing, of ATSC DTV channels is done in step625. If the scan is not done, then receiver200returns to step605and tunes to another ATSC DTV channel. However, if the scan is finished, receiver200forms the supported channel list in step630for communication to BS105ofFIG. 3.

In accordance with the principles of the invention, receiver200checks if an ATSC DTV signal is detected in step610ofFIG. 7. In particular, decision device240ofFIG. 4monitors one, or more, of CTL lock signal227, STR lock signal228and sync lock signal231to determine whether or not an ATSC DTV signal has been detected in the DTV channel of interest. Illustratively, the decision device240may comprise a combinatorial logic function, e.g., an AND or OR function of some or all of the lock indicators. Also illustratively, decision device240may declare an ATSC DTV signal has been detected in accordance with threshold-based rules, as illustrated in the state transition diagram shown inFIG. 8. In other words, decision device250is a state machine. As can be observed fromFIG. 8, there are four states:“check lock” state505;“lock” state510;“check out of lock” state515; and“out of lock” state520.
In addition, as shown inFIG. 8, there are a number of conditions for transiting from one state to another. Illustratively, inFIG. 8there are four conditions for state transitions, labeled “A”, “B”, “C” and “D”. These are defined as:A—one, or more, lock detector signals (227,228and/or231) are less than a threshold;B—one, or more, lock detector signals (227,228and/or231) are greater than a threshold;C—one, or more, lock detector signals (227,228and/or231) are greater than a threshold for a predefined interval, TC; andD—one, or more, lock detector signals (227,228and/or231) are less than a threshold for a predefined interval, TD;
The predefined intervals, TCand TDcan be determined empirically and/or can be related to, e.g., an ATSC data segment interval, PN511 interval, PN63 interval, etc. Although it is assumed that each lock detector signal has an associated threshold, the inventive concept is not so limited. In the “lock” state (510) and the “check out of lock” state (515), decision device240provides, via signal241, an ATSC signal detected indicator (e.g., a binary digit having a logical “1” value, i.e., “TRUE”). Otherwise, in the “out of lock” state (520) and the “check lock” state (505), decision device240provides, via signal241, an ATSC signal not detected indicator (e.g., a binary digit having a logical “0” value, i.e., “FALSE”).

As described above, the inventive concept proposes an efficient threshold-based ATSC DTV signal detector, which can be used to identify the presence of an ATSC signal buried in noise or other types of interference down to 20 dB below the ATSC threshold of visibility (TOV). It should be noted that the decision device may be designed to be solely based on the CTL lock indicator, STR lock indicator, sync detection information (data segment sync and/or field segment sync) or a combination of the various lock indicators. It should also be noted that although the receiver ofFIG. 4is described in the context of CPE150ofFIG. 3, the invention is not so limited and also applies to, e.g., a receiver of BS105that may perform channel sensing. Further, although the receiver ofFIG. 4is described in the context of a WRAN system, the invention is not so limited and applies to any receiver that performs channel sensing.

In view of the above, the foregoing merely illustrates the principles of the invention and it will thus be appreciated that those skilled in the art will be able to devise numerous alternative arrangements which, although not explicitly described herein, embody the principles of the invention and are within its spirit and scope. For example, although illustrated in the context of separate functional elements, these functional elements may be embodied in one, or more, integrated circuits (ICs). Similarly, although shown as separate elements, any or all of the elements may be implemented in a stored-program-controlled processor, e.g., a digital signal processor, which executes associated software, e.g., corresponding to one, or more, of the steps shown in, e.g.,FIG. 7, etc. Further, the principles of the invention are applicable to other types of communications systems, e.g., satellite, Wireless-Fidelity (Wi-Fi), cellular, etc. Indeed, the inventive concept is also applicable to stationary or mobile receivers. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims.