Semiconductor memory device

A semiconductor memory device includes: a semiconductor substrate; a semiconductor layer formed on the semiconductor substrate with an insulating film interposed therebetween, the semiconductor layer being in contact with the semiconductor substrate via an opening formed in the insulating film; and a NAND cell unit formed on the semiconductor layer with a plurality of electrically rewritable and non-volatile memory cells connected in series and first and second select gate transistors disposed at both ends thereof.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based on and claims the benefit of priority from the prior Japanese Patent Applications No. 2005-301906, filed on Oct. 17, 2005 and No. 2006-160500, filed on Jun. 9, 2006, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a semiconductor memory device with electrically rewritable and non-volatile memory cells, and more particularly relates to an EEPROM (Electrically Erasable and Programmable ROMs) with NAND cell units formed on a partial SOI substrate.

2. Description of the Related Art

A NAND-type flash memory is known as one of EEPROMs. The NAND-type flash memory has a unit cell area smaller than that of a NOR-type flash memory, and is easy to make the capacity large because a plurality of electrically rewritable and non-volatile memory cells are connected in series to constitute a NAND cell unit.

Since the NAND-type flash memory uses FN tunneling current for writing data, the consumption current is smaller than that of the NOR-type flash memory, which uses hot carrier injection. Therefore, a page capacity being defined by a cell area, in which data write is performed at a time, it is possible to make the page capacity large, thereby being possible to write data at a substantially high rate.

To make the cell size of the NAND-type flash memory further smaller than that of the currently used cells, it is in need of making the device insulating area small. However, it leads to reduction of the breakdown voltage between cells. To achieve the miniaturization of cells without reducing the breakdown voltage, it is effective to use such a technology that forms the NAND cell unit array on an SOI (Silicon On Insulator) substrate. Such a technology has already been provided (e.g., refer to Unexamined Japanese Patent Application Publication No. 2000-174241).

SUMMARY OF THE INVENTION

According to an aspect of the present invention, there is provided a semiconductor memory device including:

a semiconductor substrate;

a semiconductor layer formed on the semiconductor substrate with an insulating film interposed therebetween, the semiconductor layer being in contact with the semiconductor substrate via an opening formed in the insulating film; and

a NAND cell unit formed on the semiconductor layer with a plurality of electrically rewritable and non-volatile memory cells connected in series and first and second select gate transistors disposed at both ends thereof.

According to another aspect of the present invention, there is provided a semiconductor memory device including:

a semiconductor substrate;

a semiconductor layer formed on the semiconductor substrate with an insulating film interposed therebetween; and

a NAND cell unit formed on the semiconductor layer with a plurality of electrically rewritable and non-volatile memory cells connected in series, wherein

openings are formed in the insulating film at locations corresponding to source/drain regions of the memory cells, and the semiconductor layer is in contact with the semiconductor substrate via the openings.

According to still another aspect of the present invention, there is provided a method of fabricating a semiconductor memory device including:

forming an insulating film on a semiconductor substrate;

forming openings in the insulating film;

depositing an amorphous or polycrystalline semiconductor layer on the insulating film, the semiconductor layer being in contact with the semiconductor substrate via the openings formed in the insulating film;

annealing the semiconductor layer to crystallize it; and

forming a NAND cell unit on the semiconductor layer, the NAND cell unit including a plurality of electrically rewritable and non-volatile memory cells connected in series and first and second select gate transistors disposed at both ends thereof.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Illustrative embodiments of this invention will be explained with reference to the accompanying drawings below.

FIG. 1is a plan view of a memory cell array of a NAND-type flash memory;FIG. 2is its sectional view taken along a bit line (BL) (i.e., I-I′ sectional view ofFIG. 1);FIG. 3is its sectional view taken along a select gate line (SGD) (i.e., II-II′ sectional view ofFIG. 1); andFIG. 4is its sectional view taken along a word line (WL) (i.e., III-III′ sectional view ofFIG. 1).

The device body is an SOI (Silicon On Insulator) substrate, which has a single-crystalline silicon substrate1and a silicon layer3formed thereon. The silicon layer3is insulated from the substrate1with an insulating film, for example, a silicon oxide film2, interposed between the substrate1and the silicon layer3. The silicon layer3is not perfectly insulated from the substrate1, but is in contact with the substrate1via openings (or holes)4formed in the oxide film2. Including this meaning, the SOI substrate in accordance with this embodiment will be referred to as a “partial SOI substrate” hereinafter.

The silicon substrate1has such a well structure in the memory cell array area that an n-type of well1bis formed on a p-type of silicon substrate1a; and a p-type of well1con the n-type of well1b.

The silicon layer3is a crystallized or re-crystallized one in such a way that an n-type polycrystalline or amorphous silicon layer is deposited on the oxide film2and then subjected to crystallizing anneal. In this crystallizing anneal process, crystallization is progressed with such a solid-phase epitaxial growth that the substrate area exposed at the opening4serves as a seed crystal.

The thickness of the silicon layer3is, for example, 1 nm or more and 3 L or less, where L is the gate length of the memory cell. The thickness of the oxide film2is, for example, 1 nm or more and 4 L or less. Alternatively, there is a possibility that the total thickness of the silicon layer3and oxide film2is set to be about the gate length L.

Silicon layer3, on which p-type diffusion layers31are partially formed, is divided into stripe-shaped device formation areas14which are separated from each other with a device-isolating insulator film12as shown inFIGS. 3 and 4. Floating gates6are formed above the silicon layer3with tunnel insulating film5interposed therebetween, and control gates8are formed above the floating gates6with inter-gate insulating film7interposed therebetween.

Floating gates6are formed in the respective memory cells to be separated from each other; and control gates8are formed to be continued in one direction, thereby constituting word lines WL (WL0-WL15), each of which is a common one for multiple memory cells. Although, in this embodiment, the floating gate is formed of a polysilicon film, it may be formed as an insulating charge storage layer.

FIG. 5shows an equivalent circuit of the memory cell array. Select gate transistors SG1and SG2are disposed at both ends of the serially connected memory cells M0-M15to constitute a NAND cell unit. Gates of these select gate transistors SG1and SG2are formed of the same polysilicon films6d,8dand6s,8sas floating gate6and control gate8, which are stacked and in contact with each other, thereby constituting select gate lines SGD and SGS disposed in parallel with word lines WL.

The memory cell array is covered with an interlayer insulating film9, on which bit lines (BL)11are formed. Within the interlayer insulating film9, a common source line (CELSRC)10sis buried to connect sources of the NAND cell units in common, i.e., in contact with the common source region (n+-diffusion layer)32sof the select gate transistors SG2, and bit line contact plug10dis formed and buried with the same conductive material film as the common source line. The bit line11is connected to the common drain region (n+-diffusion layer)32dof the select gate transistors SG1via the contact plug10d.

The silicon layer3is n-type one, and this n-type silicon layer3is used as channel bodies and source/drain regions of multiple memory cells constituting a NAND cell unit as it is without forming source and drain diffusion layers, and adjacent two memory cells have a common source/drain region. Therefore, the memory cell is formed as a depletion(D)-type of n-channel transistor as formed.

In this embodiment, the select gate transistor areas disposed at both ends of the NAND cell unit are located above the openings4, which serve as seeds for epitaxial growth of the silicon layer3. p-type layers31are formed on these areas so that the select gate transistors SG1and SG2are formed as enhancement(E)-type of n-channel transistors, which are cut off with 0[volts] gate voltage. N+-type diffusion layers are formed under the bit line contact plug10dand source line10s(i.e., the drain region of select gate transistor SG1and the source region of select gate transistor SG2) for making these contacts good.

Next, the fabrication process of the flash memory in accordance with this embodiment will be explained with reference toFIGS. 6 to 17.FIGS. 6 to 9show the fabricating steps with I-I′ sectional views ofFIG. 1. As shown inFIG. 6, silicon oxide film2is formed on the silicon substrate1, and openings4are formed at the select gate transistor areas in the oxide film2. The openings4are stripe-shaped as being continued in the direction perpendicular to the sheet face ofFIG. 6.

Following it, as shown inFIG. 7, n-type silicon layer3is formed on the oxide film2. Explaining in detail, a polycrystalline silicon layer or an amorphous silicon layer is deposited, and it will be subjected to a crystallizing anneal process. As a result, solid-phase epitaxial growth is progressed from the substrate crystalline portion exposed at the opening4used as a seed, and a good crystalline silicon layer3is obtained. After this crystallizing anneal, it may be performed a planarization process for planarizing the silicon layer surface.

Next, as shown inFIG. 8, p-type diffusion layers31are formed by ion implantation at the portions of the openings4where select gate transistors are to be formed later.

As shown inFIG. 9, a tunnel oxide film5is formed on the silicon layer3and then a first polysilicon layer60is deposited thereon for forming floating gates.FIGS. 10 and 11show this state in the II-II′ and III-III′ sectional views ofFIG. 1.

Next, as shown inFIGS. 12 and 13(sectional views corresponding toFIGS. 10 and 11, respectively), a device isolation trench13is formed by RIE (Reactive Ion Etching) with such a depth that reaches at least the oxide film2from the polysilicon layer60(in practice, reaches the p-type well1c), and device isolation film12is buried in the trench13.

As a result of this device isolation process, n-type silicon layer3is patterned to have plural stripe-shaped device formation areas14, which are isolated from each other in the word line direction and elongated in the bit line direction. At this time, the floating gate-use polysilicon film60is patterned to plural stripe-shaped polysilicon films60aeach with the same pattern as the device formation area14.

Following it, as shown inFIGS. 14 to 16, after forming inter-gate insulating film7, second polysilicon film80is deposited for forming control gates. At this time, as shown inFIGS. 14 and 15, hole81is formed in the inter-gate insulating film7above the cell area on the select gate line, and the second polysilicon film80is contacted with the first polysilicon film60via the hole81.

Then, as shown inFIG. 17, the second and first polysilicon films80and60are etched by RIE, so that word line8, and select gate lines8dand8sare patterned. As a result, the first polysilicon film60is remained as floating gates6and the select gate portions8dand8sonly at the cell areas and transistor areas. Next, ion implantation is performed to form n+-type layer32at source line contact and bit line contact portions.

Then, as shown inFIGS. 2 to 4, first interlayer insulating film9ais deposited, in which contact holes are formed, and common source line10sand bit line contact plug10dare buried in these contact holes. Following it, second interlayer insulating film9bis deposited, in which bit line contact holes are formed, and then bit lines11are formed.

As apparent from the above-described fabrication process, to position the openings4formed in the oxide film2just under the select gate lines SGD, SGS, it is in need of aligning the p-type layer31, word lines WL and select gate lines SGD, SGS in relation with the openings4because these are not self-aligned.

An alignment mark fabricating process will be explained with reference toFIGS. 18 to 20.FIG. 18shows a process for forming the opening4in the oxide film2with a mask material film101on the cell array area. At this process time, a mark-use opening4ais formed in the oxide film2at a certain mark area on the wafer peripheral area.

Then, as shown inFIG. 19, the memory cell array area is covered with resist102, and the silicon substrate is etched via the mark-use opening4a. As a result, mark-use trench4bis formed on the substrate. Following it, the resist102and mask material film101are removed.

Forming the mark-use trench4bon the peripheral area as described above, mask alignments in the future processes will be made possible.

The operations of the flash memory in accordance with this embodiment will be explained below. As described above, each of as formed memory cells is in a depletion (D)-type state (i.e., erase state), and data write in the narrow sense is defined by: injecting electrons into the floating gate and making the memory cell enhancement (E)-type with a positive threshold voltage. This memory state with the positive threshold state is dealt with, for example, a “0” data state.

Data erase is defined by: discharging electrons in the floating gate, thereby setting the memory cell to be in the erased state (D-type state). The erased state is dealt with a “1” data state. With these states, binary data may be stored. Controlling the cell threshold distributions to have multiple write threshold states, multi-level data storage may be possible. Explained below is the binary data storage scheme.

FIG. 21shows a bias relationship in a NAND cell unit at an erase time. Data erase is performed for an erase unit, one block BLK, which is defined as a set of NAND cell units sharing word lines WL0-WL15in the equivalent circuit shown inFIG. 5.

As shown inFIG. 21, in a selected block, select gate lines SGD, SGS, bit lines BL and common source line CELSRC are set to be floating; the entire word lines WL0-WL15are set at 0V; and positive erase voltage Vera is applied to a well node CPWEL, which is in contact with the p-type well1cand n-type well1b. The erase voltage Vera is a boosted voltage generated from a boost circuit to be higher than the power supply voltage, for example, 15V to 24V.

Under this bias condition, the PN junction between the n-type layer3and the p-type layer31under the select gate line in the NAND cell unit is forward biased. Therefore, the n-type layer3is charged up to the erase voltage Vera via the p-type layer31at the opening4from the p-type well1c. As a result, a large electric field is applied between the floating gate and the cell channel in each memory cell, and electrons in the floating gate are discharged by FN tunneling, so that the erase state (i.e., “1” data state) with a negative threshold voltage may be obtained.

At this time, n-type layers3in the non-selected blocks are also charged up to Vera. However, word lines in the non-selected blocks are set to be floating, and the floating gates are boosted by capacitive coupling, so that the memory cells in the non-selected block are not erased.

FIG. 22shows a bias relationship at a data write time. Supposing that a set of memory cells arranged along a word line is defined as one page or two pages, data write is performed by a page.FIG. 22shows a case where word line WL1is selected.

Well node CPWEL is applied with 0V (or small and negative voltage); the selected word line WL1is applied with write voltage Vpgm, that is set at 15V to 20V; the remaining non-selected word lines are applied with positive medium voltage Vm lower than Vpgm; select gate line SGD on the bit line side is applied with Vdd; select gate line SGS on the source line side is applied with 0V; and common source line CELSRC is applied with 0V or a suitable positive voltage.

Prior to the above-described write bias application, 0V (“0” write data) and Vdd (“1” write data) are applied to bit lines BL in accordance with write data. When “0” write time, the NAND cell channel is applied with 0V. In case of “1” write, the select gate transistor SG1is turned off when source thereof is charged up to Vdd-Vth (Vth: threshold voltage of select gate transistors), so that the NAND cell channel is made floating.

The write voltage Vpgm and medium voltage Vm being applied under the above-described state, electrons are injected into the floating gate in the “0” write selected cell by FN tunneling. As a result, “0” data defined by a positive threshold voltage may be written into the selected cell. By contrast, the floating cell channel is boosted in potential by capacitive coupling in the “1” write cell, so that electron injection does not occur in it. Therefore, the “1” write cell is kept in the “1” data state.

FIG. 23shows a bias relationship at a data read time. Data read also is performed by a page.FIG. 23shows a case where word line WL1is selected.

The common source line CELSRC is set at 0V, and bit line BL is precharged to a positive voltage VBL, and kept in a floating state. Well node CPWEL is applied with 0V (or small positive voltage); the selected word line is applied with read voltage Vr (e.g., 0V); the remaining non-selected word lines are applied with pass voltage Vread, which is able to turn on cell without regard to cell data; and select gate lines SGD and SGS are applied with pass voltage Vread.

As a result, in case cell data is “0”, the selected cell is kept off, and the bit line BL will not be discharged. By contrast, in case the selected cell's data is “1”, the bit line will be discharged via the NAND cell unit including the selected cell, which is turned on. Therefore, detecting the bit line voltages with sense amplifiers after having performed bit line discharge operation for a certain period, one page data are read out.

The substrate used in this embodiment is not a perfect SOI substrate, which has a silicon layer perfectly isolated from the substrate, but a partial SOI substrate. While it is required of this partial SOI substrate to be subjected to crystallizing process, it may be obtained inexpensively in comparison with the ordinary SOI substrate. Selecting the thickness of the silicon layer, device isolation is easy. Further, it is possible to achieve such a miniaturized cell structure that is not obtained in case of an ordinary bulk type.

In addition, in case of a NAND-type flash memory with the ordinary SOI substrate, it is in need of specifically thinking for applying the erase voltage to the channel body of the NAND cell unit. By contrast, in this embodiment, the silicon layer serving as a channel body is in contact with the substrate via the opening formed in the oxide. Therefore, it is easy to apply the erase voltage to the channel bodies via the substrate for erasing NAND cell units in a lump, so that it is able to certainly perform data erase.

FIGS. 24 to 27show sectional views in other embodiments, which correspond toFIG. 2. InFIG. 2, openings4are formed in the oxide film2under both of the select gate line (SGD)8don the bit line side and the select gate line (SGS)8bon the source line side. By contrast,FIG. 24shows such an example that the openings4are formed only under the source line side select gate lines (SGS)8s, whileFIG. 25shows another example, in which the openings4are formed only under the bit line side select gate lines (SGD)8d.

InFIG. 26, the openings4are formed in the oxide2under the n+-type diffusion layers32dand32sserving as the bit line (BL) contact area and source line (CELSRC) contact area, respectively. In this case, when the erase voltage Vera is applied to p-type layer1con the substrate, the PN junctions between p-type layer1cand n+-type layers32s,32dare reversely biased. However, suitably setting the erase voltage value and impurity concentration of each diffusion layer, it becomes possible to apply a required and positive voltage to the channel body of the NAND cell unit.

In detail, having formed to cause breakdown of the PN junctions between p-type layer1cand n+-type layers32d,32s, impact ionization occurs in the p-type layer31, and holes in generated electron-hole pairs are carried to and stored in the n-type channel body of the NAND cell unit. As a result, the channel body will be boosted to such a positive voltage that is necessary for the erase operation.

While in the example shown inFIG. 26, the openings4are formed in the oxide2under the n+-type diffusion layers32dand32sat both of the bit line (BL) contact area and the source line (CELSRC) contact area, it is effective that the opening is formed under either one of the bit line (BL) contact area and the source line (CELSRC) contact area.

FIG. 27shows still another example, in which the opening4is formed in the oxide2under a certain memory cell in the NAND cell unit. In this example, the channel bodies in the NAND cell unit may be charged up in accordance with the erase voltage Vera applied to the p-type layer1c, so that the erase operation is made possible like the above-described embodiments.

FIG. 28shows still another example, in which the openings4are formed under a area extending from n+-type layer32d(i.e., common drain region of the select gate transistors SG1) to p-type layer31(i.e., channel bodies of the select gate transistors SG1), and under another area extending from n+-type layer32s(i.e., common source region of the select gate transistors SG2) to p-type layer31(i.e., channel bodies of the select gate transistors SG2). Having not shown in the drawings, it is useful that the opening4is formed to cover the area from p-type layer31to n-type silicon layer3.

Next, device simulation data will be explained below. Device conditions are as follows: the ratio of line L to space S of the stripe-shaped device formation area is L/S=80 nm/80 nm; word line width is W=80 nm; select gate line width is LSG=100 nm; impurity concentration of p-type well is PSUB=1E18 cm−3; and impurity concentration of p-type layer under the select gate line is PSGC=1E16 cm−3.

The thickness of the silicon layer in the partial SOI substrate is selected in the range of TSOI=10 nm to 80 nm, and the thickness of the device isolation film is selected in the range of TBOX=20 nm to 80 nm. The tunnel oxide thickness is TOX=8 nm. The number of memory cells in the NAND cell unit is 5.

Initially, with respect to such a structure that the openings are formed under the select gate lines (SG) and such a structure that the openings are formed under the source line/bit line contacts (CB), the simulation results of erase operations under the condition of: word line is set at 0V; and p-type well is applied with 20V will be explained.

FIGS. 29A and 29Bshow simulation conditions with respect to the respective structures. Here, source and drain voltages are those at n+-type layers32sand32d, to which the source line CELSRC and bit line BL are connected, respectively. In a practical erase operation, the source line CELSRC and bit line BL are set to be floating, so that each of the n+-type layers32sand32dhas a voltage level defined by the voltage applied to the p-type well1c. However, for the convenience of numerical calculation, the simulation is performed with the source and drain voltage applied as shown inFIGS. 29A and 29B.

In case of such the structure that the openings are formed under the select gate lines (SG), since the PN junction between p-type diffusion layer31under the select gate line SG and n+-type diffusion layer32s(or32d) is forward biased, source and drain voltages are set at the same voltage as that of p-type well, 20V. In case of such the structure that the opening is formed under the source line/bit line contact (CB), it is provided such an NPN structure that p-type diffusion layers31is sandwiched by n+-type layer32s(or32d) and n-type silicon layers3. Therefore, source and drain voltages are set at 19V that is lower than the p-type well voltage 20V with built-in-potential of a PN-junction.

Note here that the apply voltage is made linearly changed in accordance with time from timing 0 μsec to 10 μsec. That is, p-type well voltage is changed with 2V/μsec and finally boosted to 20V. The apply voltage is not changed from 10 μsec to 100 μsec.

FIGS. 30 and 31show the changes of potential distributions in the device under the condition of the above-described erase voltage application with respect to such structures that the openings are formed under the select gate line SG and under the source line/bit line contact CB, respectively. The potential distribution, which is shown by contour lines, is a result of calculating vacuum level. That is, taking account of the work function, p-type layer, which is externally applied with 0V, is set at about −5 eV. InFIGS. 30 and 31, the potential change of the p-type well and the channel body portion (n-type silicon) are depicted in relation with 0V of word line (control gate).

In detail, the channel body potentials are: about 4V after 2 μsec; about 12V after 6 μsec; and about 20V and 19V after 10 μsec. InFIG. 30, it appears that there is a level difference between the channel body and p-type well. This is because of that vacuum level is shown. In practice, both of the channel body and p-type well become 20V after 10 μsec. By contrast, inFIG. 31, it appears that there is not a level difference between the channel body and the p-type well. However, in practice, when the p-type well is set at 20V, the channel body is set at 19V that is the same as source and drain.

As a result of the above-described simulation data, in both cases where the openings are formed under the select gate line SG and under the source line/bit line contact CB, it will be confirmed that a certain level erase-use electric field is applied between the channel body and the floating gate, whereby the device may be erased.

FIG. 32shows read current characteristics of NAND cell unit in the case where the opening is formed under the select gate line SG. Here is provided the relationships between the read current (bit line current) ID of a selected cell and the impurity concentration NSOI of the n-type silicon layer with relation to the p-type well voltage VSUB used as parameters with respect to 3×3 combinations of: TSOI=10, 40 and 80 nm; and TBOX=20, 40 and 60 nm.

Here, the drain voltage is VD=0.7V; floating gate voltage of the non-selected cells is 2.5V; and floating gate voltage of the selected cell is 0V. Further, the impurity concentration of the p-type well is PSUB=1E18 cm−3.

FIG. 33shows read cell currents ID(−0.5V), ID(−0.2V), ID(0.0V), ID(0.2V) and ID(0.5V), which are obtained with the selected cell's floating gate voltages VFG=−0.5, −0.2, 0.0, 0.2 and 0.5V, respectively, and the selected cell's ON/OFF current ratios ID(0.2V)/ID(−0.2V) and ID(0.5V)/ID(−0.5V). Note here that the impurity concentration NSOI of the n-type silicon layer is adjusted to satisfy the following relationship: when the floating gate voltage of the selected cell is 0V, the drain current is ID=0.1 μA.

The simulation results shown inFIGS. 32 and 33teach that it is possible to read out cell data based on the cell's ON/OFF current ratio, and select an optimum condition of the read current characteristic with regard to the sizes and impurity concentrations of the respective portions of the device.

FIGS. 34 and 35show the simulation results in the case where the opening is formed under the bit line contact CB under about the same conditions as those inFIGS. 32 and 33. InFIG. 34, the relationships between the read current (bit line current) ID of a selected cell and the impurity concentration NSOI of the n-type silicon layer are shown with relation to the p-type well voltage VSUB used as parameters with respect to 3×3 combinations of: TSOI=10, 40 and 80 nm; and TBOX=20, 40 and 60 nm. Other conditions are the same as those inFIG. 32.

FIG. 35shows the results of the selected cell's ON/OFF current ratios ID(0.2V)/ID(−0.2V) and ID(0.5V)/ID(−0.5V) obtained under the conditions like those inFIG. 33.

FIG. 36shows a simulation result in the case where the opening is formed under the select gate line SG. That is, such a device condition is simulated that the drain current (i.e., bit line current) becomes ITH=0.1 μA in the cases of threshold voltage VTH=−0.5V, 0V and 0.5V. While each value of ITH is slightly shifted from 0.1 μA, it shows the error generated as a result of the condition searching calculation. It may be guessed that the similar result will be obtained in the case where the opening is formed under the source line/bit line contact CB.

InFIG. 36, “SF” is S factor in each threshold state (unit: mV/dec.); “ION” is the drain current when the floating gate voltage corresponds to the threshold voltage of +2.5V (unit: A); “TSOI/L” is the SOI film thickness normalized by the gate length L; and “TBOX/L” is the BOX film thickness normalized by the gate length L. Other items are the same as those inFIGS. 33 and 35.

FIGS. 37-41are graphs each showing the result inFIG. 36on an x-y coordinate, where TSOI/L and TBOX/L are plotted on x-axis and y-axis, respectively.

FIG. 37shows a case of: L=S=W=20 nm; and VTH=−0.5V. Symbols such as circle (ο), triangle (Δ) and so on are the calculation results inFIG. 36, and it is shown that the memory device is operable when TBOX and TSOI are defined by the combinations of the above-described symbols.

InFIG. 37, a curve of: y=8.7/x is shown. The calculation result teaches that there is an operable area defined by the combinations of TBOX and TSOI under the curve.

FIG. 38shows a case of: L=S=W=20 nm; and VTH=0V. In this case, the curve defining the operable area is expressed as follows: y=2.55/x.

FIG. 39shows a case of: L=S=W=80 nm; and VTH=−0.5V. In this case, the curve defining the operable area is expressed as follows: y=8.0/x.

FIG. 40shows a case of: L=S=W=80 nm; and VTH=0V. In this case, the curve defining the operable area is expressed as follows: y=0.74/x.

FIG. 41shows a case of: L=S=W=80 nm; and VTH=0.5V. In this case, the curve defining the operable area is expressed as follows: y=0.125/x.

The results ofFIGS. 37 to 41may be explained as follows: the negative substrate bias VSUB serves for suppressing the drain current via the BOX film and SOI film; as the BOX film becomes thicker, the capacitive coupling of VSUB to the SOI film becomes less, so that the drain current suppressing effect is reduced; and even if the BOX film is thin, as the SOI film becomes thick, the drain current suppressing effect is reduced.

FIGS. 37-41show that in the outside area of each approximate hyperbolic curve, the BOX film is too thick, or the SOI film is too thick, to obtain the preferable drain current in the suitable range of VSUB (i.e., 0V to 2V), i.e., to obtain the preferred threshold voltage.

As described above, it has been cleared from the simulation result that data read is made possible in both cases of: the opening is formed under the select gate line SG; and it is formed under the bit line contact CB. Comparing these read properties with each other, the property in case that the opening is formed under the select gate line SG is more highly dependent on the well voltage VSUB than that in the other case, so that the freedom of trimming and the like is also large.

The above-described embodiment may be variously modified as follows:

(a) It is effective to use a p-channel type of transistor as a memory cell, which is obtained by reversing p-type and n-type in the above-described embodiment.

(b) It is not always necessary that the opening4under the select gate line SG is, as shown inFIG. 2, aligned with the select gate line SG. As shown inFIG. 42, it is permitted that the opening4is shifted from the location just under the select gate line SG.

(c) In the above-described embodiment, n-type of silicon layer3is used, and the memory cell is formed as a D-type transistor. By contrast, as shown inFIG. 43, it is effective to use p-type silicon layer as the channel region of the memory cell, in which n-type layers3aare formed at source and drain regions. In this case, at an erase time when erase voltage Vera is applied to the p-type well1c, hole current may be supplied to the whole NAND cell channel via the p-type layer31under the select gate line SG from the opening4. Therefore, it is possible to perform data erase in a lump like the above-described embodiment.

(d) As a method of forming a crystalline silicon layer3, it is useful to add a vapor-phase growing process. As shown inFIG. 44, firstly, form the epitaxial layer40on the opening portion of the substrate1with the opening4formed by use of vapor-phase growth; then, as similar to the above-described embodiment, deposit the amorphous silicon or polysilicon layer3on it; and finally perform crystallizing anneal.

As a result, crystallization is progressed from the vapor-phase epitaxial layer40serving as a seed, it is possible to obtain a well-crystallized silicon layer3.

(e) As a method of forming a partial SOI substrate, SIMOX (Separation by Implanted Oxygen) may be used as follows. As shown inFIG. 45, thermal oxide film201is formed on the substrate1. Then, as shown inFIG. 46, resist mask202is patterned on the oxide film201, and oxygen ion (16o+) is implanted in this state under the condition of: dose amount of 4×1017cm−2; and acceleration voltage of 140 keV, so as to selectively form oxygen implanted layer203. Following it, anneal is performed in, for example, 1300° C., N2atmosphere for 6 hours. As a result, as shown inFIG. 47, oxide film2is formed in the substrate. Then, As- and B-ion implantations are performed under suitable conditions, respectively, so that as shown inFIG. 48, the partial SOI substrate may be obtained like the above-described embodiment, in which n-type silicon layer3is formed on the oxide film2.

(f) Other read conditions may be used, which are different from that explained with reference toFIG. 23. For example,FIG. 49shows another read condition, in which pass voltage Vread2applied to the word lines disposed on the both side of the selected cell (i.e., selected word line WL1inFIG. 49) is set to be lower than the pass voltage Vread applied to other non-selected word lines. For example, Vread is set at 5V while Vread2is set at 4V.

Additional Embodiments

Explained below are additional embodiments, in which multiple openings are formed at locations corresponding to the source/drain regions of memory cells in the NAND cell unit.

FIG. 50is a plan view of a memory cell array of a NAND-type flash memory in accordance with an additional embodiment;FIG. 51is its sectional view taken along a bit line (BL) (i.e., I-I′ sectional view ofFIG. 50);FIG. 52is its sectional view taken along a select gate line (SGD) (i.e., II-II′ sectional view ofFIG. 50); andFIG. 53is its sectional view taken along a word line (WL) (i.e., III-III′ sectional view ofFIG. 50).

Note here that, inFIGS. 50-53, the portions corresponding to those in the above-described embodiments are designated by the same reference symbols as in the above-described embodiments.

The device body is an SOI substrate, which has a single crystalline silicon substrate1and a silicon layer3formed thereabove. The silicon layer3is insulated from the substrate1with an insulating film, for example, a silicon oxide film2, interposed therebetween. The silicon layer3is not perfectly insulated from the substrate1, but is in contact with the substrate1via openings (or holes)4formed in the oxide film2. Including this meaning, the SOI substrate in accordance with this embodiment will be referred to as a “partial SOI substrate” hereinafter.

The silicon substrate1has such a well structure in the memory cell array area that an n-type of well1bis formed on a p-type of silicon substrate1a; and a p-type of well1con the n-type of well1b.

The silicon layer3is a crystallized or re-crystallized one in such a way that an n-type of polycrystalline or amorphous silicon layer is deposited on the oxide film2and annealed. In this crystallizing anneal process, crystallization is progressed as a solid-phase epitaxial growth, in which the substrate silicon crystal exposed at the openings4serve as seeds.

As shown inFIG. 51, n-type of diffusion layer31is formed by ion implantation on a cell formation area of the entire memory cells (i.e., on the channel body regions and source/drain regions) in an NAND cell unit (NAND string) in the silicon layer3. The diffusion layer31is not extended to the channel body regions of the select gate transistors disposed at the both ends of the NAND cell unit, and the p-type of layer3is remained under the select gate lines as it is.

Silicon layer3is divided into stripe-shaped device formation areas14which are separated from each other with a device-isolating insulator film12as shown inFIGS. 52 and 53. Floating gates6are formed above the silicon layer3with tunnel insulating film5interposed therebetween, and control gates8are formed above the floating gates6with inter-gate insulating film7interposed therebetween.

Floating gates6are formed at the respective memory cells to be separated from each other; and control gates8are formed to be continued in one direction, thereby constituting word lines WL (WL0-WL15), each of which is a common one for multiple memory cells. Although, in this embodiment, the floating gate is formed of a polysilicon film, it may be formed as an insulating charge storage layer.

The equivalent circuit of the memory cell array is the same as shown inFIG. 5. Select gate transistors SG1and SG2are disposed at both ends of the serially connected memory cells M0-M15, and these constitute a NAND cell unit. Gates of these select gate transistors SG1and SG2are formed of the same polysilicon films6d,8dand6s,8sas floating gate6and control gate8, which are stacked and in contact with each other, thereby constituting select gate lines SGD and SGS disposed in parallel with word lines WL.

The memory cell array is covered with an interlayer insulating film9(9a,9b), on which bit lines (BL)11are formed. On the interlayer insulating film9a, a common source line (CELSRC)10sare formed to be in contact with the source regions32sof the select gate transistors SG1in the NAND cell units, and bit line contact plug10dis formed of the same conductive material film as the common source line. The bit lines11are connected to the drain regions32dvia the contact plug10d.

n+-type of diffusion layers are formed at the source line and bit line contact portions (i.e., at the common drain region32dof the adjacent two select gate transistors SG1and at the common source region32sof the adjacent two select gate transistors SG2), so that contact resistances of these portions are made low.

The silicon layer3is n-type, and this n-type silicon layer3is used as channel bodies and source/drains of multiple memory cells constituting a NAND cell unit as it is without forming source and drain diffusion layers, so that adjacent two memory cells have a common source/drain. Therefore, the memory cell is formed as a depletion(D)-type of and n-channel type of transistor as formed. By contrast, the select gate transistors SG1and SG2are formed on the p-type of silicon layer3as enhancement (E) type of and n-channel type of transistors, which are cut off with 0V gate voltage.

In this embodiment, the openings4in the oxide film2are formed not only at the locations corresponding to all source/drain regions of memory cells in the NAND cell unit but also at other locations corresponding to the channel bodies and source/drain regions of the select gate transistors SG1and SG2.

The portions of the silicon substrate1, which are in contact with the p-type silicon layer3via the openings4, serve as seeds of the solid-phase epitaxial-growth when the silicon layer3is crystallized. That is, performing epitaxial growth with multiple seeds distributed, the silicon layer3will be reproduced as a good quality crystalline layer.

Next, the fabrication process of the flash memory in accordance with this embodiment will be explained with reference toFIGS. 54 to 57, which are sectional views corresponding toFIG. 51.

As shown inFIG. 54, silicon oxide film2is formed on the silicon substrate1. Then, as shown inFIG. 55, openings (i.e., holes)4are formed in the oxide film2at the locations corresponding to channel bodies and source/drain regions of the select gate transistors formed later and source/drain regions of the memory cells. At this step, each of the openings4is formed as stripe-shaped one extending continuously in perpendicular to the sheet surface ofFIG. 55.

Following it, as shown inFIG. 56, p-type of silicon layer3is formed. Explaining in detail, a polysilicon layer or an amorphous silicon layer is deposited and subjected to crystallizing anneal. The silicon layer3is made crystalline as a result of solid-phase epitaxial growth, in which the substrate portions exposed at the openings4serve as seeds.

Next, as shown inFIG. 57, ion implantation is performed to form n-type diffusion layer31on the area where memory cells are to be formed later, i.e., channel bodies and source/drain regions of all memory cells.

Thereafter, it will be followed by the same process as the conventional NAND-type flash memory. That is, tunnel oxide film5is formed on the silicon layer3; and then a first polysilicon film is deposited, which serves as floating gates. Next, the device isolating trench is formed with a depth at least reaching the oxide film2; and device isolating film12is buried in it.

As a result of this device isolating process, the silicon layer3is patterned to multiple stripe-shaped device formation areas14, which are isolated from each other and continued in the direction of the bit line. At this time, the first polysilicon film serving as floating gates is patterned to the same stripe-shaped patterns as the device formation areas14.

Then, inter-gate insulating film7is formed; and then a second polysilicon film is deposited, which serves as control gates. Patterning the second polysilicon film, word lines8and select gate lines8dand8sare formed. This polysilicon patterning process is performed to the extent of that the first polysilicon film is etched. As a result, floating gates6are formed to be separated from each other in the direction of cell channel length. Although the detail is not explained here, in the select gate lines8dand8s, the first and second polysilicon films are in contact with each other.

Then, ion implantation is performed for bit line and source line contact areas, drain regions32dand source regions32sare formed with n+-type of diffusion layers in these areas.

Thereafter, as shown inFIGS. 51 to 53, deposit the first interlayer insulating film9a; form contact holes in it; and form the common source line10sand bit line contact plug10d. Following it, deposit the second interlayer insulating film9b; form contact holes in it; and then form the bit lines11.

The operations of the flash memory in accordance with this embodiment will be explained below. As described above, each of as formed memory cells is in a depletion (D)-type state (i.e., erase state), and write in the narrow sense is defined by: injecting electrons into the floating gate and making the memory cell enhancement (E)-type with a positive threshold voltage. This memory state with the positive threshold state is dealt with, for example, a “0” data state.

Data erase is defined by: discharging electrons in the floating gate, thereby setting the memory cell to be in the erased state (D-type state). The erased state is dealt with a “1” data state. With these states, binary data may be stored. Controlling the cell threshold distributions to have multiple write threshold states, multi-level data storage may be possible. Explained below is the binary data storage.

Data erase is performed for an erase unit, one block BLK, which is defined as a set of NAND cell units sharing word lines WL0-WL15in the equivalent circuit shown inFIG. 5.

In a selected block, select gate lines SGD, SGS, bit lines BL and common source line CELSRC are set to be floating; the entire word lines WL0-WL15in the elected block are set at 0V; and positive erase voltage Vera is applied to a well node CPWEL, which is in contact with the p-type well1cand n-type well1b. The erase voltage Vera is a boosted voltage generated from a boost circuit, which is higher than the power supply voltage, for example, 15V to 24V.

Under this bias condition, the PN junction between p-type silicon layer3and n-type diffusion layer31under the cell array area is forward biased via the opening4. Therefore, the n-type layer31is charged up to the erase voltage Vera. As a result, a large electric field is applied between the floating gate and the cell channel in every memory cell, and electrons in floating gate are discharged by FN tunneling, so that the erase state (i.e., “1” data state) with a negative threshold voltage may be obtained.

Supposing that a set of memory cells arranged along a word line is defined as one page or two pages, data write is performed by a page. Well node CPWEL is applied with 0V (or small and negative voltage); the selected word line WL1is applied with write voltage Vpgm, that is set at 15V to 20V; the remaining non-selected word lines are applied with positive medium voltage Vm lower than Vpgm; select gate line SGD on the bit line side is applied with Vdd; select gate line SGS on the source line side is applied with 0V; and source line CELSRC is applied with 0V or a suitable positive voltage.

Prior to the above-described write bias application, 0V (“0” write data) and Vdd (“1” write data) are applied to bit lines BL in accordance with write data. As a result, when “0” write time, the NAND cell channel is applied with 0V. In case of “1” write, the select gate transistor SG1is turned off when source thereof is charged up to Vdd-Vth (Vth: threshold voltage of select gate transistors), so that the NAND cell channel becomes floating.

The write voltage Vpgm and medium voltage Vm being applied under the above-described state, electrons are injected into the floating gate in the “0” write selected cell by FN tunneling. As a result, “0” data defined by a positive threshold voltage may be written into the selected cell. By contrast, the floating cell channel is boosted in potential by capacitive coupling in the “1” write cell, so that electron injection does not occur in it. Therefore, the “1” write cell is kept in the “1” data state.

Data read also is performed by a page. The common source line CELSRC is set at 0V, and bit line BL is precharged to a positive voltage VBL, and kept in a floating state. A selected word line is applied with read voltage Vr (e.g., 0V); the remaining non-selected word lines are applied with pass voltage Vread, which is able to turn on cell without regard to cell data; and select gate lines SGD and SGS are applied with pass voltage Vread.

As a result, in case cell data is “0”, the selected cell is not turned on, and the corresponding bit line BL is little discharged. By contrast, in case the selected cell's data is “1”, the bit line will be discharged via the NAND cell unit including the selected cell. Therefore, detecting the bit line voltage with the sense amplifier after having performed bit line discharge operation for a certain period, data may be read out.

The substrate in this embodiment is not an SOI substrate, which has a silicon layer perfectly isolated from the substrate, but a partial SOI substrate. While it is required of this partial SOI substrate to be subjected to crystallizing anneal process, it may be obtained inexpensively in comparison with the ordinary SOI substrate. Selecting the thickness of the silicon layer, device isolation is easy. Further, it is possible to achieve such a miniaturized cell structure that is not achieved with an ordinary bulk type of cell array.

In addition, in case of NAND-type flash memory with the ordinary SOI substrate, it is difficult to apply the erase voltage to the channel bodies of all NAND cell units at a time. To improve this problem, it is in need of specifically thinking for example, burying back gates under every channel body.

By contrast, in this embodiment, the silicon layer3, on which the channel bodies of NAND cell units are formed, is in contact with the substrate1via the openings4formed in the oxide film2. Therefore, it is possible to apply the erase voltage to the channel bodies via the substrate1for erasing in a lump, so that it is able to certainly perform data erase.

Further, in this embodiment, openings4of the oxide2are formed under every source/drain region of the memory cells in the NAND cell unit, and the exposed portions of the substrate at these openings4serve as seeds for solid-phase epitaxy of the silicon layer3. As a result, the silicon layer3becomes a good quality crystal as a whole. This point will be explained in detail below.

Supposing that there is not opening in the memory cell formation region in the NAND cell unit, the crystallizing process of the silicon layer3is performed by use of the openings under the select gate transistors as seeds, so that it is necessary to do epitaxial growth for a long distance in the lateral direction. Therefore, there is such a possibility that the silicon portion far from the seed is not well made crystalline. If the memory cell's channel body is remained in an amorphous or poly-crystalline state, it is impossible to achieve a good cut-off property, so that some problems will be remained in the memory cell performance.

By contrast to this, in this embodiment, since there are provided openings at the locations corresponding to all source/drain regions of the memory cells, the distance of epitaxial growth from each seed portion in the crystallizing process becomes about as short as the memory cell's gate length. As a result, the silicon layer3in the NAND cell unit is made a good single-crystalline layer as a whole.

While, in the above-described additional embodiment, the openings4in the oxide film2have been formed at the locations corresponding to the source/drain regions of all memory cells, it is not always necessary to form openings at the locations corresponding to the entire source/drain regions. Forming at least one opening, preferably forming multiple openings, it is possible to obtain a good crystalline layer.

FIG. 58shows a sectional view of a NAND flash memory in accordance with another additional embodiment in correspondence withFIG. 51. The portions corresponding to those in the above-described embodiment are designated with the same reference symbols as in the above-described embodiment, and the detailed explanation will be omitted.

In this embodiment, the openings4are formed at intervals of two source/drain regions of memory cells in the NAND cell unit. Explaining in detail, the openings4are selectively formed under the common source/drain regions between even numbered memory cells (i.e., 2nd, 4th, . . . , 14th memory cells) in the NAND cell unit counted from the select gate transistor SG1(or SG2) side and the following ones. In other words, there are not formed openings at the locations under the common source/drains of the successive two memory cells (M0, M1), (M2, M3), . . . , (M14, M15).

It is the same as in the above-described embodiment that the openings4are formed under the channel bodies and source/drain regions of the select gate transistors.

According to the above-described opening arrangement, grain boundaries, which may be formed in the post-crystallized silicon layer, are not positioned at the channel bodies of memory cells. This situation will be explained in detail with reference toFIGS. 59A to 59F.

FIGS. 59A to 59Fshow schematically the progressive single-crystal growing situations in the silicon layer3of the partial SOI substrate in the crystallizing anneal process, where the silicon layer3is crystallized from the seed portions at the openings4. In these drawings, oblique line portions in the silicon layer3designate epitaxial growth areas.

At the beginning of the epitaxial growth, as shown inFIGS. 59A and 59B, the single-crystallization is limited within each opening4, and progressed only in the direction perpendicular to the substrate1. Thereafter, the epitaxial growth will be progressed in the horizontal direction (i.e., lateral direction), too. However, the epitaxial growth rate in the lateral direction is slower than that in the vertical direction. As a result, as shown inFIGS. 59C and 59D, the front of the single-crystal area will be sloped.

When epitaxital growth areas progressed from adjacent two openings4collide with each other on the oxide film2, crystal lattices thereof are aligned ideally with each other because two epitaxial growth areas are formed of the same crystal. However, as shown inFIG. 59E, as a result of delicate disturbances, grain boundaries are formed between every two epitaxital growth areas. The grain boundaries being not removed finally as shown inFIG. 59F, the silicon layer3may not be made single-crystalline as a whole.

Formed in the grain boundaries are fixed charges, interface states and electron-hole pair generation centers. However, in this embodiment, as apparent from the opening arrangement shown inFIG. 58, the locations where the grain boundaries are formed are not under the channel bodies of the memory cells but under the source/drain regions.

If crystal defects are not formed in the channel body, the memory cell shows a good ON/OFF property. If the crystalline property of the source/drain region is bad, it causes in general leakage current between source/drain region and the substrate. However, in this embodiment, the source/drain regions, crystalline property of which is bad, are insulated from the substrate1by the oxide film2. Therefore, the above-described leakage current between the source/drain regions and the substrate will not be carried. While there is a fear of leakage current flowing from the source/drain regions in the lateral direction based on the grain boundaries, it will hardly affect cell properties because the leakage current flows in the same direction as the cell current.

According to this embodiment, even if grain boundaries are formed in the solid-phase epitaxially grown layer, it affects little the memory cell, so that there will be provided a NAND-type flash memory with a good property.

The above-described embodiment will be generalized as follows: openings being formed at common source/drain regions between even numbered memory cells counted from the select gate transistor SG1(or SG2) and the following ones, the same effect will be obtained. For example, there is disposed the oxide film3without openings under the successive four memory cells (M0-M3), (M4-M7), (M8-M11), and (M12-M15), while openings are formed under the source/drain regions between the fourth memory cell M3and the following memory cell M4, between the eighth memory cell M7and the following memory cell M8, and between the twelfth memory cell M11and the following memory cell M12. By use of the above-described opening arrangement, there is not a fear of grain boundaries formed in the channel bodies of memory cells.

FIG. 60shows another example, the sectional view of which is in correspondence withFIG. 58. In this example, the openings4are selectively formed under the common source/drain regions between successive odd numbered memory cells and the following ones. In detail, the openings4are formed under the source/drain regions between the 1st, 3rd, 5th, . . . , 15th memory cells in the NAND cell unit counted from the select gate transistor SG1(or SG2) and the following ones.

In this case, there is not formed an opening under the source/drain region between memory cell M0and select gate transistor SG1on one end of the NAND cell unit, and under the source/drain region between memory cell M15and select gate transistor SG2on the other end. Therefore, the spaces between adjacent openings in the oxide film2in these areas are made the same as those at other locations in the NAND cell unit.

As a result, based on the same reason as the above-described example, even at the end portion of the memory cell string, the grain boundaries are located in the source/drain regions. In other words, no grain boundaries are formed in the channel bodies of the select gate transistors SG1and SG2. Therefore, the same effect will be obtained as the above-described example.

The opening arrangement is not limited to the above-described example, in which the openings are formed under the source/drain regions between every odd numbered memory cell and the flowing one. For example, in case the openings may be formed under the source/drain regions between every four odd numbered memory cell (i.e., 3rd, 7th, . . . , 15th memory cells) and the following ones, the same effect will be obtained.

The above-described additional embodiment may be variously modified as follows:

(a) It is effective to use a p-channel type of transistor as a memory cell, which is obtained by reversing p-type and n-type in the above-described embodiment.

(b) It is not always necessary that the openings4are aligned with the source/drain regions of memory cells. It is permitted that the openings4are slightly shifted from the location just under the source/drain regions.

(c) The opening shape under the select gate transistor area is not limited to the above-described example. For example, it is useful such a case that there are openings under the channel bodies of select gate transistors while no openings are formed under the source/drain regions at the bit line contact and source line contact portions. Alternatively, it is also useful such a case that there are openings under the source/drain regions at the bit line contact and source line contact portions while no openings are formed under the channel bodies of select gate transistors.

(d) As a method of forming a crystalline silicon layer3, it is useful to add a vapor-phase growing process. That is, firstly, form the epitaxial layer on the opening portion of the substrate with the openings formed by use of vapor-phase growth; then, as similar to the above-described embodiment, deposit the amorphous silicon or polysilicon layer on it; and finally perform crystallizing anneal.

As a result, crystallization is progressed from the vapor-phase epitaxial layer serving as a seed, it is possible to obtain a well-crystallized silicon layer.

(e) It is permitted that the silicon layer3is formed as an intrinsic semiconductor layer with impurities contained little, and then made a p-type (or n-type) one by ion implantation after crystallization.

(f) As a method of forming a partial SOI substrate, SIMOX (Separation by Implanted Oxygen) method may be used. That is, selective oxygen ion implantation is performed for the substrate; and then anneal is performed. As a result, it may be provided the same partial SOI substrate as in the above-described embodiment.