System and method for propagating operand availability prediction bits with instructions through a pipeline in an out-of-order processor

A processor core and a method for distributive scoreboard scheduling in an out-of-order processor pipeline are described herein. In an embodiment, control logic appends operand availability bits to each instruction. The appended operand availability bits form a distributive scoreboard for each instruction. The appended operand availability bits are propagated together with the instruction through multiple stages of the processor pipeline. An instruction dispatch buffer stores the instruction and the operand availability bits. A dispatch controller determines when an instruction is to be issued. The determination is based, at least in part, on the operand availability bits stored in the instruction dispatch buffer.

FIELD OF THE INVENTION

The present invention relates generally to microprocessors. More particularly, it relates to an out-of-order processor.

BACKGROUND OF THE INVENTION

Many microprocessors are relatively simple in-order machines. In an in-order processor instructions are fetched and if source operands of the instruction are available in a register file of the processor the instruction is issued to the appropriate functional unit. Instruction issue typically refers to sending an instruction to a functional unit, for example an execution unit, for processing. In an in-order processor, instructions are issued and executed in program order. In a pipelined in-order processor the pipeline is stalled until operands of an instruction are available.

In an out-of-order processor, instructions are fetched and dispatched to an instruction dispatch buffer. The instructions wait in the buffer until their operands are ready and are issued before earlier or older instructions, and out of program order. The results are then queued in a buffer, for example in a completion buffer. The completion buffer keeps track of the program order of instructions and after older instructions write their result into the register file, the younger instructions write their results into the register file. In an out-of-order processor, instructions are executed out of program order and their results are written into the register file in program order. Pipelined out-of-order processors allow execution of instructions to be scheduled around hazards that would stall a pipelined in-order processor.

Typically, instructions comprise one or more source operands and a destination operand. The destination operand of an instruction is usually modified based on, at least in part, the source operands. An instruction that modifies a destination operand is typically referred to as a producer of another instruction whose source operand it modifies. The instruction whose source operand is modified by a producer instruction is typically referred to as a consumer. The source operand of the consumer is typically the destination operand of the producer. Producers are processed by an execution unit of a processor before their corresponding consumers are processed. Producer instructions may be consumers of other producers and consumers may be producers of other consumer instructions. A consumer may have more than one producer that it depends upon for source operands. The source operands of a consumer instruction may be bypassed from a producer instruction.

Bypassing refers to the transfer of an operand value modified by a producer instruction to a consumer instruction before the producer instruction writes its results into a register file (i.e. before the producer updates the architectural state). A bypass policy of a processor determines when and from where one or more operand values modified by a producer instruction can be sent to a consumer instruction. An instruction can only be issued to an execution unit of a processor when all source operand values are available (e.g. in a register file or via bypass from a producer instruction). As a result, the bypass policy can determine the earliest time that an instruction can be issued.

Some out-of-order processors use a technique known as scoreboarding to allow instructions to execute out-of-order when there are sufficient computing resources available and no data dependencies for the source operands. A centralized scoreboard is used to check for operand availability of an instruction. A centralized scoreboard stores the status for each register in a processor and every instruction looks up the centralized scoreboard to determine if their operands are available. In an out-of-order processor that uses scoreboarding, every instruction goes through the centralized scoreboard where a record of data dependencies of the source operands of the instruction is created. The centralized scoreboard determines when the instruction can read its operands and begin execution. If the centralized scoreboard decides that an instruction cannot execute immediately due to unavailability of its source operands, it monitors changes in the system state and decides when the operands are ready. If the source operand values are ready to be read, the centralized scoreboard determines when the instruction can be issued. Thus all hazard detection and resolution is centralized in the scoreboard. The centralized scoreboard has to communicate with all functional units of the processor which represents a structural hazard since there are only a limited number of buses on which to communicate.

A centralized scoreboard implementation requires a large area on the chip. Furthermore, looking up a centralized scoreboard can be time consuming. A centralized scoreboard stores the status for each register. An instruction typically needs to access values for one or two operands and looks up the status for one or two registers. When a centralized scoreboard is accessed to determine availability of operands, one or two registers in the scoreboard are selected out of all the registers in the processor. This is equivalent to a time consuming lookup of a register file. Also, complicated routing is required if multiple instructions attempt to lookup a scoreboard at the same time. The size of the scoreboard and the number of buses to the scoreboard can be increased which consumes valuable chip real estate and also has timing implications. The complexity of looking up a centralized scoreboard also delays instruction issue.

What is needed is a new technique for reducing the complexity of a centralized scoreboard in an out-of-order microprocessor, which overcomes the deficiencies noted above.

BRIEF SUMMARY OF THE INVENTION

The present invention provides a processor core and a method for distributive scoreboard scheduling in an out-of-order processor. In an embodiment, control logic appends operand availability bits to each instruction. The appended operand availability bits form a distributive scoreboard for each instruction. The appended operand availability bits are propagated together with the instruction through multiple stages of a processor pipeline. An instruction dispatch buffer stores the instruction and the operand availability bits. A dispatch controller determines when an instruction is to be issued. The determination is based, at least in part, on the operand availability bits stored in the instruction dispatch buffer.

In an embodiment, the operand availability bits of an instruction include a counter value that is used to determine when an operand modified by a producer instruction can be bypassed to the consumer instruction. The operand availability bits include a bit to activate counters of consumer instructions when producer instructions are issued into an execution unit of the processor. Producer instructions are appended with a wakeup enable value that is used to activate the counters of consumer instructions when producer instructions are issued into the execution unit of the processor. When a producer instruction is issued into an execution unit of the processor, the counter of a consumer instruction starts to decrement. When the counter counts down to zero, the operand being modified by the producer instruction can be bypassed to the consumer instruction. Thus, the consumer instruction does not have to wait for the producer instruction to write the modified operand into a register file of the processor before it can be accessed. This speeds up instruction issue and thereby increases instruction throughput. In an embodiment, using a wakeup enable value, a producer instruction can delay the start of a counter thereby controlling when a consumer instruction is issued.

The operand availability bits include a value to indicate whether an operand is present in the register file of the processor. The operand availability bits also include a value to indicate whether an operand is predictably available in the processor.

In an embodiment of the present invention, a modified renaming map also stores operand availability bits.

In one embodiment of the present invention, the processor core includes a pipeline that includes multiple parallel processing paths where instructions in each parallel processing path include appended operand availability bits.

DETAILED DESCRIPTION OF THE INVENTION

The present invention provides a processor core and a method for implementing distributive scoreboard scheduling in an out-of-order processor. In the detailed description of the invention that follows, references to “one embodiment”, “an embodiment”, “an example embodiment”, etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described. Although embodiments are described with reference to pipelined out-of-order processors, it is within the knowledge of one skilled in the art to implement embodiments in a non-pipelined processor or a partially pipelined processor.

FIG. 1is a diagram of a processor100according to an embodiment of the present invention. Processor100includes a processor core102, instruction memory104, and a register file106. Processor core102has a pipeline that includes an instruction dispatch unit110.

As shown inFIG. 1, instruction dispatch unit110of processor core102includes a dispatch controller130, decoder132, renamer122and instruction dispatcher (ID)124. According to an embodiment, renamer122includes control logic (not shown) that appends operand availability bits to an instruction fetched from instruction fetch buffer116and decoded by decoder132. In an embodiment, processor core102may include multiple pipeline stages. The operand availability bits appended to an instruction by renamer122may be propagated together with the instruction through multiple pipeline stages. Instruction dispatcher124includes an instruction dispatch buffer (IDB)700(not shown here but described below) that stores the instruction and most of the appended operand availability bits. Dispatch controller130dynamically schedules instructions for execution by ALU126based on the appended operand availability bits stored in instruction dispatch buffer700.

In an embodiment, the operand availability bits of a consumer instruction include a counter value that is used to determine when an operand modified by a producer instruction can be bypassed to the consumer instruction. The operand availability bits include a bit to activate counters of consumer instructions when producer instructions are issued into ALU126of processor100. Producer instructions are appended with a wakeup enable value that is used to activate the counters of consumer instructions when producer instructions are issued into ALU126. When a producer instruction is issued into ALU126, the counter starts to decrement. When the counter counts down to zero, the consumer instruction can be issued so that it can receive bypassed operands from producer instructions. Thus, the consumer instruction does not have to wait for the producer instruction to write the modified operand into register file106before it can be accessed. The use of a counter to determine if one or more operand(s) of an instruction may be accessed before they are written to register file106results in faster instruction issue and increased instruction throughput.

In an embodiment, using a wakeup enable value, a producer instruction can delay the start of a counter thereby controlling when a consumer instruction is issued.

In an embodiment, operand availability bits include a value to indicate whether an operand is present in the register file of the processor. The operand availability bits also include a value to indicate whether an operand is predictably available in processor100. For example, if a load instruction has a cache miss, it has to access the data from main memory or hard disk. Data access times from main memory or hard disk are unpredictable. Once the data is accessed from main memory or hard disk and is available in one of the functional units of processor100, it is predictably available. Upon a load miss this bit is set to 0 and when the value to be loaded is predictably available in processor100, it is set to 1.

Use of a distributive scoreboard, in the form of operand availability bits appended to an instruction, eliminates the need to continually access a centralized scoreboard to determine if an instruction can be issued, as is done in conventional out-of-order processors.

Processor core102also includes a program counter (PC) selector112, an optional recoder114, a branch predictor118and pipeline control logic120.

Program counter selector112selects an address or program counter value to be used to fetch a program instruction from memory. In one embodiment, PC selector112can select a sequentially incremented program counter value, a redirect program counter value, or a program counter value for a new program thread.

Processor core102is preferably capable of executing both a standard width instruction (e.g., a 32-bit instruction) and a compressed-format width instruction (e.g., a 16-bit instruction). Accordingly, in one embodiment, processor core102includes optional recoder114. If a compressed-format instruction is fetched from instruction memory104, it is recoded by recoder114to a format width that can be decoded by decoder132and executed by arithmetic logic unit126. In one embodiment, both standard width instructions and compressed-format width instructions are recoded by recoder114to an instruction width having more bits than a standard width instruction. Instructions are passed from optional recoder114to instruction buffer116.

Instruction buffer116is capable of holding multiple instructions. In one embodiment, in which processor core102implements multithreading, instructions from different program threads are stored, for example, in separate portions of instruction buffer116. Multithreading refers to an ability of an operating system to execute different parts of a program, called threads, simultaneously. In another embodiment, in which processor core102implements multithreading, instructions from different program threads are stored in separate instruction buffers, for example, one instruction buffer for each program thread. Processor core102preferably fetches multiple instructions per fetch cycle.

In instances where a control transfer instruction, for example a branch instruction or a jump instruction, is fetched from instruction memory104, branch predictor118predicts whether a conditional branch associated with the control transfer instruction is taken or not taken. Any known branch prediction algorithm can be used.

Instructions are read from instruction buffer116and decoded by decoder132. Decoder132performs the functions of decoding instructions. Renamer122performs the functions of updating register renaming map600(not shown here but described below). During the decoding and renaming process, each instruction is associated with/assigned an instruction identification (IID) tag. An IID is a unique identifier assigned to each instruction. Source and destination operands of an instruction are each assigned a completion buffer identification (CBID) tag. The CBID for a destination operand determines the location in completion buffer128where arithmetic logic unit126can write calculated results for an instruction. The CBID for source operands are the locations in completion buffer128where source operand values can be located. In one embodiment, the instruction identification tags are sequentially generated multi-bit values. The number of bits that are generated is dependent on how many instructions are executed simultaneously. In one embodiment, in which processor core102performs multithreading, instruction identification tags are generated and assigned on a per thread basis.

Instructions are read from instruction dispatcher124and executed by arithmetic logic unit (ALU)126in accordance with a schedule determined by dispatch controller130. Dispatch controller130schedules instructions for execution once their operands are ready and preferably in accordance with their age. Age of an instruction is determined by the program. For example, an earlier instruction in program order is “older” than a later instruction in program order. In out-of-order processor100, if operands for both an older instruction and a younger instruction are available, then the older instruction is preferably issued before younger instruction. In an embodiment, instruction dispatch buffer124is stores instructions in the order that it receives instructions. Instructions at the top of the queue in instruction dispatch buffer124are older instructions. The older instructions that have available operands are dispatched by instruction dispatcher124before instructions lower in the instruction dispatch buffer124queue. In an embodiment, dispatch controller130may be part of ID124or pipeline control logic120.

Results in arithmetic logic unit126are written to completion buffer128and stored until instructions graduate and their results are written to register file106.

Instruction memory104is any memory accessible to processor core102, for example, an instruction cache, a scratch pad, a loop buffer, et cetera. In one embodiment, memory104includes multiple memories and/or multiple types of memories.

Register file106includes a plurality of general purpose registers (not shown), which are visible to a programmer.

FIG. 2is a diagram of a processor200according to another embodiment of the present invention. Processor200includes a processor core202, instruction memory104, and a register file106. Processor core202has a pipeline that includes instruction dispatch unit210.

As shown inFIG. 2, instruction dispatch unit210of processor core202includes a dispatch controller130, decoder132, renamer122. In the embodiment shown inFIG. 2there are two pipelines, one for ALU126band one for Address Generation (AGEN)126a. Microprocessor200operates similarly to microprocessor100except that microprocessor200includes two parallel instruction execution pipelines. These two instruction execution pipelines can be similar, or they can be specialized to execute selected instructions. In one embodiment, the pipeline represented by instruction dispatcher124a, AGEN126a, and completion buffer128ais used to execute control transfer instructions such as branch, jump and return instructions as well as load, store, prefetch, cache instructions. The pipeline represented by instruction dispatcher124b, ALU126band completion buffer128bis used to execute arithmetic instructions such as add, subtract etc.

Since there are two pipelines, instruction dispatch unit210has two instruction dispatchers i.e. instruction dispatcher124aand instruction dispatcher124b. According to an embodiment, renamer122, in instruction dispatch unit210, includes control logic (not shown) that appends operand availability bits to an instruction fetched from instruction fetch buffer116and decoded by decoder132. Instruction dispatchers124aand124beach include an instruction dispatch buffer (not shown), similar to IDB700, that stores the instruction and most of the appended operand availability bits. Dispatch controller130determines when an instruction is issued to ALU126bor AGEN126abased on operand availability bits appended to instructions stored in respective instruction buffer of instruction dispatchers124aand124b.

As shown inFIG. 2, processor core202includes a program counter (PC) selector112, an optional recoder114, an instruction buffer116, a branch predictor118and pipeline control logic220.

Processor core202includes two completion buffers128aand128bassociated with each of AGEN126aand ALU126b. Scheduler130dynamically schedules instructions for execution by the two parallel pipelines of processor core202.

In an embodiment, processor200may include multiple parallel pipeline stages. The operand availability bits appended to an instruction by renamer122may be propagated together with the instruction through multiple parallel pipeline stages. The operand availability bits may be modified to accommodate parallel pipeline stages. As will be understood by persons skilled in the relevant arts given the description herein, operand availability bits may be modified for parallel pipeline stages. It is also to be appreciated that although the examples presented herein use single pipelines, alternate embodiments are not limited to single pipelines. For example, in a processor that includes more than two pipelines, more than two instruction dispatchers and associated functional units may be used. In another example, a single instruction dispatcher may be used for multiple pipelines. As will be understood by persons skilled in the relevant arts given the description herein, the number of functional units in may vary depending on implementation.

FIG. 3is a diagram illustrating example pipeline stage partitions of a processor e.g. processor100or processor200. In the embodiment shown inFIG. 3, processor100is partitioned into four pipeline stages. These four pipeline stages are illustrative and not intended to limit the present invention. In other embodiments, processor100can have more or less than four pipeline stages. The number of pipeline stages that are implemented in any embodiment of the present invention is a design choice.

As shown inFIG. 3, the four pipeline stages of processor100are instruction fetch stage302, instruction rename and dispatch stage304, instruction execute stage306and write to register file stage308.

Stage302typically includes PC selector112, recoder114and instruction fetch buffer116. In stage302, PC selector112selects amongst a variety of program counter values to be used to fetch an instruction from instruction memory104. Instruction tags associated with an instruction to be fetched from instruction memory104are checked. One or more instructions are fetched from instruction memory104. Compressed-format instructions are recoded by recoder114into a format that can be decoded and executed. All instructions are written to instruction buffer116. In one multithreading embodiment, processor100includes one instruction buffer for each program thread. In one embodiment, instructions can be dispatched directly to decoder132.

Stage304typically includes decoder132, renamer122, instruction dispatcher124and dispatch controller130. Renamer122includes renaming map600and renaming control logic (not shown). Instruction dispatcher124includes an instruction dispatch buffer (IDB)700and instruction dispatch control logic (not shown). In an example, for a parallel pipeline, as in processor200, stage304includes instruction dispatchers124aand124b. In stage304, instructions are decoded, renamed and dispatched. In parallel with decoding using decoder132, renamer122updates register renaming map600. A register renaming map is a structure that holds the mapping information between programmer visible architectural registers and internal physical registers. According to an embodiment, renaming map600is modified to include availability bits for each register in processor100. Renaming map600also has CBIDs corresponding to the latest provider for each register in processor100. For each instruction, renamer122appends operand availability bits to the instruction. The instruction can then take the availability bits from renaming map600through the pipeline, thereby creating a distributive scoreboard that determines when operands are available. Use of renaming map600to obtain operand availability bits obviates the need for a centralized scoreboard and the need for an instruction to lookup a centralized scoreboard repeatedly to determine when operands are available.

According to an embodiment, renamer122, in instruction dispatch unit110, includes renaming control logic (not shown) that appends operand availability bits to an instruction fetched from instruction fetch buffer116and decoded by decoder132. Instruction dispatcher124includes an instruction dispatch buffer700that stores the instruction and most of the appended operand availability bits. Dispatch controller130determines when the instruction is issued to ALU126of processor core102based on the operand availability bits stored in the IDB700of instruction dispatcher124. In one embodiment, in which processor100includes accumulation registers (not shown), digital signal processor (DSP) registers (not shown) and co-processor registers (not shown), a separate renaming map is maintained for the different register types. These renaming maps are similar to the renaming map600maintained for general purpose registers. In another embodiment, renaming map600may be used for all registers.

As noted herein, register renaming is done for destination registers to remove output dependencies and to ensure there is a single producer of a given register in processor core102at any given time. The source registers are renamed so that data is obtained from a producer at the earliest opportunity instead of waiting for the processor's state to be updated. This also aids in reducing dependency check complexity in any coprocessor coupled, for example, to arithmetic logic unit126.

Instructions in stage304receive an instruction identification (IID) tag and a completion buffer identification (CBID) tag. The destination operand of an instruction has the same CBID as that assigned to its instruction. The CBID for a destination operand determines the location in completion buffer128where arithmetic logic unit126can write calculated results for an instruction. The source operands of an instruction are assigned the CBIDs of their corresponding producer instructions. The source operands lookup CBIDs of their corresponding producer instructions in renaming map600. In one embodiment, each instruction identification tag is a thread-specific sequentially generated value that uniquely determines the program order of instructions. At the end of stage304, decoded and renamed instructions are placed in instruction dispatch buffer700of instruction dispatcher124. Dispatch controller130selects instructions residing in instruction buffer for execution by arithmetic logic unit126.

Stage306typically comprises ALU126. In another example, stage306may have parallel pipeline stages such as AGEN126a. In stage306, instructions are executed by arithmetic logic unit126and control transfer instructions such as, for example, branch instructions and jump instructions are resolved. In one embodiment, selected instructions such as, for example, floating point instructions are processed by a coprocessor (not shown) coupled to arithmetic logic unit126.

In stage308, results generated by ALU126and/or a coprocessor are written to completion buffer128. As noted above, an instruction's destination operand is assigned a CBID number in stage304. As instructions complete execution, their corresponding completion buffer completion bits are set, thereby enabling the instructions to graduate and release their associated CBID numbers. Results from completion buffer128are written to register file106as instructions graduate and register renaming map(s) are updated. Each instruction preferably graduates according to program order.

FIG. 4is a diagram illustrating further pipeline stage partitions of some of the pipeline stages inFIG. 3. In the embodiment shown inFIG. 4, instruction decode stage is divided into N stages D1to DN. Instruction execute stage306is divided into parallel stages306aand306b. Stage306amay include AGEN126aand stage306amay include ALU126b. Instruction execute stage306ais divided into M stages A1to AMand instruction execute stage306bis divided into R stages E1to ER. Write back stage308is divided into K stages W1to WK. These pipeline stages are illustrative and not intended to limit the present invention. In other embodiments, processor core102can have more or less pipeline stages. The number of pipeline stages that are implemented in any embodiment of the present invention is a design choice. The pipeline stages shown inFIG. 4illustrate bypassing of operands between producer instructions and consumer instructions.

Typically, instructions comprise one or more source operands and a destination operand. The destination operand of an instruction is usually modified based on, at least in part, the source operands. An instruction that modifies a destination operand is typically referred to as a producer of another instruction whose source operand it modifies. The instruction whose source operand is modified by a producer instruction is typically referred to as a consumer. The source operand of the consumer is typically the destination operand of the producer. Producers are processed by an execution unit of a processor before their corresponding consumers are processed. Producer instructions may be consumers of other producers and consumers may be producers of other consumer instructions. A consumer may have more than one producer that it depends upon for source operands. The source operands of a consumer instruction may be bypassed from a producer instruction.

Bypassing refers to the transfer of an operand value modified by a producer instruction to a consumer instruction before the producer instruction writes its results into a register file (i.e. before the producer updates the architectural state). A bypass policy of a processor determines when and from where one or more operand values modified by a producer instruction can be sent to a consumer instruction. An instruction can only be issued to an execution unit of a processor when all source operand values are available. As a result, the bypass policy can determine the earliest time that an instruction can be issued.

Typically, a consumer instruction is issued when its operands are available in register file106. By passing a consumer instruction's source operand values, a consumer instruction can issue before its operand values are available in register file106. When a consumer instruction can be issued is determined by when its producer instruction is issued and from where in a processor the operands can be bypassed to a consumer. The minimum number of pipeline stages (i.e. pipeline stage difference) between a producer and a consumer, when a bypass of an operand value from the producer instruction to the consumer instruction can occur is used as an initial counter value. This counter value is stored in renaming map700by renamer122upon renaming a producer instruction. In an embodiment, the counter value may be the minimum number of clock cycles after issue of a producer instruction when a bypass from a producer to a consumer can occur. The counter value is propagated with a consumer instruction through multiple pipeline stages. In an embodiment, the counter value is propagated only through the rename and dispatch stage304. In this embodiment, execution stage306need not be pipelined since operand availability bits are propagated only till rename and dispatch stage304. The use of a counter value makes it possible for a consumer instruction to determine whether its operand is available without having to repeatedly look up a centralized scoreboard. The use of a counter value also eliminates the need to wait for an operand of a consumer instruction to be available in register file106before it can be issued to instruction execute stage306. Issuing the consumer instruction before operands are available in register file106increases instruction throughput.

In the example shown inFIG. 4, operand values may be bypassed from W1 stage to A3 stage. The number of stages between W1and A3may be 3 stages. In another example, operands may be bypassed from Am stage to A2 stage. The number of stages between Am and A2may be 2 stages. Operands may also be bypassed from one of the pipeline stages that are in parallel with pipeline stages A1to Am. For example, operands may be bypassed from stage306bthat is parallel with stage306a. Operands may be bypassed from pipeline stage E3to pipeline stage A3. The number of stages between E3and A3may be 0.

For a single operand that is to be modified by a producer instruction, multiple counter values may be stored in renaming map600by renamer124since the type of consumer instructions and bypass stage is unknown when the producer is processed by renamer124. For example, a producer load instruction may bypass a value from stage E3to a consumer add instruction in stage A2. In this case the count value is 2 because the difference between stage E3and stage A2is 2. If the same producer load instruction were to bypass an operand value from stage E4to a consumer instruction in stage E1, then the counter value is 3 because the distance between stages E4and E1is 3 clock cycles. The stage from which a producer can bypass is implementation dependent. The type of producer instruction determines the pipeline stage from which it can bypass and the type of consumer instruction determines the pipeline stage in which it can receive a bypassed value. The producer instruction type is known upon renaming, however the consumer instruction type is not know since it is yet to be renamed. In an embodiment, depending upon type of producer instruction, two counter values are stored in renaming map600. When a consumer instruction is renamed, its type is known and one of the two counter values is selected. In another embodiment, the type of consumer instruction may be irrelevant and the counter value is based solely on the type of producer instruction and where it can bypass a value from. In an embodiment, to limit the size of the counter that decrements a counter value, the counter values limited to two bits. A wakeup enable bit (described below) may be used by a producer instruction to delay the start of a counter thereby increasing the counter value indirectly. Table 1, below shows example counter values based on the stages that an operand is bypassed from and the stages that an operand is bypassed to. Table 1 may be stored in renamer122.

From table 1, the counter value is 3 to bypass an operand from stage W1to A3, is 3 to bypass from W1to E3and is 4 to bypass from W1to E2. Thus the two counter values, for a producer instruction that can bypass an operand value from stage W1, are 3 and 4. Depending upon implementation, a producer instruction may be able to bypass only after reaching a certain pipeline stage. After reaching that stage the producer may be able to bypass from any stage thereafter, depending upon implementation. In one embodiment, counter values are based upon the earliest stage that a producer instruction can bypass operand values from. In another embodiment, counter values are based on stages later than the earliest stage that a producer instruction can bypass operand values from. The values shown in table 1 are for example purposes and do not limit the embodiments presented herein.

When a producer instruction is issued to instruction execute stage306by instruction dispatcher124, the counter associated with an operand of a corresponding consumer instruction is activated. When the counter counts down to 0, and all other operands of a consumer instruction can be accessed or can be bypassed, the consumer instruction is ready for issue. For example, if a producer instruction can bypass an operand from stage Am to a consumer instruction in stage A2, and the difference between the pipeline stages Am and A2is 2 stages, then the counter value for corresponding operand of the consumer instruction is 2. When the producer is issued in stage DN, the counter for the consumer is activated and starts to decrement. When the producer reaches stage A2, the counter for the operand of the consumer is 0. If other operands for the consumer instruction are also predictably available, then the consumer instruction is issued. When the consumer instruction reaches stage A2, the producer instruction is in stage AMand the producer instruction bypasses the operand value to the consumer instruction in stage A2. As will be understood by persons skilled in the relevant arts given the description herein, the stages that an operand value may be bypassed from, the stages that an operand value may be bypassed to and the minimum pipeline stage difference between producer and consumer when bypass can occur may vary depending on implementation. The counter value, other operand availability bits and associated control logic are described in detail below.

FIG. 5is a diagram illustrating instruction rename and dispatch stage304according to an embodiment of the invention. For purposes of simplifying the explanation, all functional units of stage304are not shown inFIG. 5. In the present embodiment, stage304has been partitioned into four pipeline stages D1to D4including pipeline registers500-508. Stage D1includes renamer122, stage D2includes selection control logic510and stage D3includes instruction dispatcher124. In an embodiment, selection control logic510may be part of dispatch controller130, pipeline control logic120or other control logic in processor100.

Pipeline register500receives and stores an instruction512from instruction fetch buffer116in instruction fetch stage302. Renamer122appends operand availability bits to instruction512. In an embodiment, operand availability bits include a predictable availability (avail) bit, an in Register File (inRF) bit, a first counter value (CNT_1), a second counter value (CNT_2), a first bypass enable bit (BP_1) and a second bypass enable bit (BP_2) and an active bit for each operand of instruction512. Instruction512and the appended operand availability bits are passed onto register502.

The avail bit indicates whether an operand value is predictably available in processor100, i.e., whether an operand value can be immediately accessed in one of the functional units of processor100. By default, the avail bit is typically set to 1 by renamer122upon renaming an instruction512. In an embodiment, the avail bit is set to 0 if the producer is a load instruction that has a cache miss and must retrieve data from main memory or hard disk. Since the number of clock cycles required to retrieve data from main memory or hard disk is unpredictable, the avail bit is set to 0 until the data can be predictably available in the processor100. When the load instruction has a cache miss, the inRF bit may be set to 1 while the load instruction fetches data from main memory or hard disk.

The inRF bit is used to indicate availability of operand data in the register file106. inRF is set to 0 by renamer122in stage D1if operand data is not present in register file106and is set to 1 by renamer122in stage D1if operand data is present in register file106. In an embodiment, renamer122determines if the operand value for an instruction is in register file106when the producer for the desired operand value broadcasts the corresponding CBID upon writing to register file106. Renamer122compares the source operand CBID stored in renaming map600with the broadcast CBID, and if CBIDs match, renamer122sets inRF to 1. The term “broadcast” as used herein refers to a signal or multiple signals that indicate the occurrence of an event such as, an instruction being issued into execution stage304, an instruction writing to completion buffer128or an instruction writing to register file106. In an embodiment, a broadcast is transmitted to every pipeline stage in processor100. A broadcast typically includes information about the event such as the CBID of a register, or the IID of an instruction along with a wakeup enable value (if applicable).

BP—1 bit and BP—2 bit, corresponding to CNT_1and CNT_2, are used to indicate whether an operand of instruction512will be available by pass from a producer instruction if instruction512is issued. Typically, BP_1and BP_2are set to 0 by renamer122. BP_1is set to 1 when CNT_1counts down to 0 and BP_2is set to 1 when CNT_2counts down to 0. When the bypass enable bit (BP_1or BP_2) for an operand of instruction512is set to 1, then it indicates that the operand value will be available by pass if instruction512is issued.

The active bit is used to activate counters that decrement CNT—1 and CNT—2 values. Typically, active bit is set to 0 by renamer122upon renaming instruction512. When a producer for instruction512broadcasts a CBID and a wakeup_en bit upon being issued into instruction execution stage306, renamer122compares the broadcast CBID to those stored in its renaming map600and sets the active bit if there is a CBID match. When the active bit is set, the corresponding CNT—1 and CNT—2 values start to decrement. An example shift-register counter is illustrated inFIG. 10and is described below.

CNT_1and CNT_2are counter values determined by renamer122based on the pipeline stage difference between producer and consumer when bypass can occur. The type of producer instruction determines the pipeline stage from which it can bypass and the type of consumer instruction determines the pipeline stage in which it can receive a bypassed value. Since the type of consumer instruction is not known, when renamer122renames a producer instruction, two counters CNT_1and CNT_2are stored in renaming map600. When a consumer instruction is renamed by renamer122, the consumer instruction's type is known and only one of the counter values (CNT_1or CNT_2) may be selected. Timing constraints may prevent renamer122from selecting a counter value to append to an instruction. In this case, as shown inFIG. 5, both counter values CNT_1and CNT_2and bypass enable bits BP_1and BP_2are appended to an instruction. One of the two counter values (CNT_1or CNT_2) and one of the corresponding bypass enable bits (BP_1or BP_2) are selected in stage D2.

In an embodiment, in stage D1, renamer122selects and appends only one counter value (CNT_1or CNT_2) and one corresponding bypass enable bit (BP_1or BP_2) to an instruction received from pipeline register500. As will be understood by persons skilled in the relevant arts given the description herein, the number of counter values, the number bits for each counter value and the policy used to determine which counter value is appended to an instruction may vary depending on implementation. In an embodiment, counter values may be determined based on a predetermined look-up table as in Table 1.

It is to be appreciated that for ease of illustration,FIG. 5illustrates operand availability bits for only one operand of instruction512, although pipeline registers502-508include operand availability bits for both operands of instruction512.

In stage D2, selection control logic510receives operand availability bits avail, inRF, BP_1, BP_2, CNT_1, CNT_2and active from pipeline register502. Selection control logic510processes operand availability bits based on received broadcasts and transfers the processed operand availability bits to register504.

Selection control logic510monitors CBID broadcasts from producer instructions. If a producer instruction that modifies an operand of instruction512is issued into execution stage306, the producer instruction broadcasts a corresponding CBID and wakeup_en bit that causes selection control logic510to set the corresponding active bit to 1.

Selection control logic510selects CNT as one of the two counter values CNT_1and CNT_2and BP as one of the two corresponding bypass enable bits BP_1and BP_2. Selection control logic510appends CNT and BP to instruction512. In one embodiment, selection control logic510selects one of the two counter CNT—1 and CNT—2 values based on a look-up table as in Table 1. If the active bit is 1, then control logic decrements the selected counter value. If the active bit received from stage D1is already set as 1, selection control logic510continues to decrement a selected count value. If the selected counter value counts down to 0 in stage D2, then selection control logic510sets the corresponding BP bit as 1.

Selection control logic510sets inRF as 1 if it receives a broadcast that an operand value of instruction512has been written into register file106.

Selection control logic510also sets avail as 1 if it receives a broadcast that an operand value of instruction512is predictably available in processor100. The broadcast may also include the location of the operand in processor100.

After processing operand availability bits, selection control logic512passes them onto register504.

In stage D3, instruction dispatcher124receives instruction512and it's appended avail, inRF, BP, CNT and active bits from pipeline register504. Instruction dispatcher124stores instruction512and its corresponding avail, inRF, BP, CNT and active bits in instruction dispatch buffer700. When all operands of instruction512can be accessed, dispatch controller130sends instruction512into stage D4via pipeline register506.

In stage D3, ID124monitors CBID broadcasts from producer instructions. If a producer instruction that modifies an operand of instruction512is issued into execution stage306, the producer instruction broadcasts a corresponding CBID and wakeup_en bit that causes ID124to set the corresponding active bit to 1 in IDB700. If the active bit received from stage D2is already set as 1, ID124continues to decrement the corresponding count value. If the selected counter value counts down to 0 in stage D2, then ID124sets BP as 1. In stage D3, if the BP bit for an operand is 1 then it indicates that if the consumer is issued, it will be able to receive bypassed operands from the producer.

In stage D3, if ID124receives inRF bit as set to 1 from stage D2, then the operand value is available in register file106. If inRF is 0, ID124sets inRF as 1 only when it receives a broadcast that an operand value of instruction512has been written into register file106.

If the avail bit is 1 it indicates that an operand value for instruction512is predictably available in processor100. If, for example, the producer instruction is a load that has a cache miss and data has be to accessed from main memory or hard disk, then the avail bit is set to 0. When operand data is predictably available in processor100, for example when data is fetched from main memory or hard disk, a broadcast of corresponding register identification number causes ID124to set avail to 1. In embodiments, a CBID or IID may be broadcast to indicate predicable availability upon which avail is set to 1.

In an embodiment, instruction dispatcher124determines whether an operand of instruction512can be accessed based on the following equation:
Operand_ready=(inRF OR BP) AND avail  (1)

An instruction is ready for issue when all its operand values can be accessed. If instruction512has two operands, ID124determines whether the instruction is ready for issue according to equation 2 below:
Issue_ready=Operand_readyOperand 1AND Operand_readyOperand 2(2)

Example control logic to implement issue_ready is described below with reference toFIG. 8.

In an embodiment, for each operand of an instruction stored in IDB700of instruction dispatcher124, operand readiness and issue readiness are determined as:
Operand_ready=f1(inRF,BP,avail)  (4)

where f2is a second function.

Based on the equations above, when all the operands for instruction512are available, dispatch controller130issues instruction512. In one embodiment, if multiple instructions in instruction dispatch buffer700are ready for issue, instruction dispatcher124in conjunction with dispatch controller130issues an instruction based on program order or the age of the instruction i.e. the oldest instruction with available operands is issued first. In an embodiment, instruction dispatcher124and dispatch controller130may be combined into a single unit.

If instruction512is a producer for another instruction, instruction dispatcher124appends a wakeup enable (wakeup_en) bit to instruction512. The wakeup_en bit is broadcast by instruction512when it issues into execution stage306thereby causing the active bit for the corresponding consumer instruction to be set and thereby starting the consumer instruction's counter. When all operands of instruction512can be accessed, instruction512is sent by dispatch controller130along with an appended wakeup_en bit into stage D4via pipeline register506.

In stage D4, control logic (not shown) which may be part of dispatch controller130or pipeline control logic120broadcasts issue of instruction512into instruction execute stage306. The broadcast may include the instruction512's IID, CBID and wakeup_en bit. The broadcast by instruction512in stage D4is used to process the operand availability bits for corresponding consumer instructions in stages D1, D2and D3. In another embodiment, the broadcast by instruction512may take place when instruction512reaches a specific stage. Instruction512again broadcasts its CBIDs and IID if it writes to completion buffer128and also when it writes register file106.

FIG. 6is a diagram illustrating a renaming map600according to an embodiment of the invention. Renaming map600is part of renamer122. In the present embodiment, renaming map600includes fields CBID, register identification (ID), inRF, avail, BP_1, BP_2, active, CNT_1and CNT_2for each entry. Renaming map600may include H entries602ato602h(602a-h). In an embodiment, H is the number of registers in register file106. Registers are identified by register IDs. In an embodiment, register ID is the logical register number. Each register has a unique register ID. Each of entries600a-hin renaming map600has two associated counters, counters604a-hand counters606a-h. Counters600a-hand counters606a-hare part of renamer122and/or renaming control logic (not shown). CBID is 5 bits, register ID is 5 bits, inRF is 1 bit, avail is 1 bit, active is 1 bit, CNT_1is 2 bits, CNT_2is 2 bits and BP_1and BP_2are 1 bit each. As will be understood by persons skilled in the relevant arts given the description herein, the number of bits for each field in renaming map600is arbitrary and depends upon implementation. In an embodiment, counters604a-hand counters606a-hare part of renaming control logic (not shown). Renaming map600may include other fields (not shown).

Use of renaming map600helps in reducing the dependency check complexity of out-of-order processor100. Register renaming is done by renamer122to allow for avoid conflicts between different instructions attempting to write to the same register in register file106. Processors using register renaming typically have a set of internal registers, such as completion buffer128, to queue the results before they are written into a register file, such as register file106. Register renaming allows multiple accesses to the same register in register file106to be mapped to different internal registers in completion buffer128, thereby resolving the conflicts. Every renaming entry in renaming map600has the CBID of the latest provider for a register and thus every consumer knows from which producer its operands will come from. As described, herein, renaming map600is modified to store operand availability bits thereby obviating the need for a centralized scoreboard. Appropriate operand availability bits are appended to consumer instructions when they pass through stage D1.

When instruction512enters stage D1(shown inFIG. 5), renamer122extracts the destination register ID from instruction512. A CBID is also assigned to the destination register ID. Renamer122looks up the corresponding register ID in renaming map600and updates the entry with the CBID of the destination register, sets avail as 1 (assuming that the data will be predictably available), inRF as 0 (since instruction512has not written to the destination register in register file512), active as 0 (since instruction512has not yet been issued into execute stage306), BP_1and BP_2as 0, (since counters associated with the destination register have not started counting) and CNT_1and CNT_2are initialized from values in table 1.

For the source operands of instruction512, renamer122looks up corresponding register IDs in renaming map600and appends corresponding avail, inRF, active, BP, CNT—1 and CNT—2 values for each source operand of instruction512. In an embodiment, renamer122also appends corresponding CBIDs to instruction512. If an instruction does not have source operands, for example a store instruction with an immediate value, then no bits are appended to instruction512.

FIG. 7is a diagram illustrating instruction dispatch buffer (IDB)700according to an embodiment of the invention. IDB700is part of instruction dispatcher124. In the present embodiment, IDB700includes fields inRF1, avail1, active1, CNT1and BP1for a first operand of an instruction and inRF2, avail2, active2, CNT2and BP2for a second operand of the instruction, an instruction identification field (IID) and a wakeup enable (wakeup_en) field. IDB700may include J entries702ato702j(702a-j). In an embodiment, IDB700holds 6 instructions at a time and J is 6. Instructions are identified by IIDs. Each instruction has a unique IID that is assigned in, for example, stage D1(inFIG. 5). IDB700may also include fields for CBIDs (not shown) for each instruction's source and destination operands. Each instruction in IDB700is assigned one of entries702a-j. Each of entries702a-jin IDB700has a corresponding counter704a-jand combinational logic706a-j. Counters704a-jand combinational logic706a-jmay be part of instruction dispatcher124or instruction dispatch control logic (not shown). IID is 5 bits, inRF1, inRF2, avail1, avail2, BP1, BP2, active1and active2are 1 bit each, CNT1, CNT2and wakeup_en are 2 bits each. As will be understood by persons skilled in the relevant arts given the description herein, the number of bits for each field in IDB700is arbitrary and depends upon implementation. IDB700may include other fields (not shown).

When an instruction enters stage D3(shown inFIG. 5), ID124stores the instruction's corresponding operand availability bits in IDB700. IDB700is organized based on IIDs. ID124assigns a wakeup_en value to each instruction entry in IDB700based on whether the instruction is a producer and whether the instruction is the latest producer for an operand at that time. An instruction may not be a producer or an instruction may not be the latest producer for the operand that it modifies. Examples of wakeup_en are described below.

IDB700stores instructions that are waiting to be issued by dispatch controller130. The instructions in IDB700are stored until their operands are available and until dispatch controller130schedules them for issue. Table 2 below illustrates example status of an operand based on avail, inRF and BP bits.

TABLE 2OperandAvailinRFBPOperand Status DescriptionAvailability000Not possibleN/A001Producer may be a load missNo011Producer may be a load miss that isNofetching data from main memory orhard disk010Not PossibleN/A100Producer issued, counter has startedNobut producer has not yet reached abypassable stage101Producer issued and has reached aYesbypassable stage110Not possibleN/A111Producer has completed write toYesregister file

In the case of processor200, there are 2 IDBs, one each in ID124aand ID124b. In processor200, one IDB (not shown) is associated with the AGEN126apipeline and another IDB (not shown) is associated with the ALU126bpipeline.

The instructions waiting to be issued in IDB700are tested for operand availability on each clock cycle. In an embodiment, a logical combination of inRF, avail and BP bits using equation (2) determines whether the operands are available and whether the instruction is ready for issue. Example combinational logic implementing equation (2) to test operand and dispatch readiness is illustrated inFIG. 8. The oldest instruction in IDB700is selected by dispatch controller130from among all the instruction in IDB700which have available operands. Alternatively, dispatch controller130may schedule instruction issue based on a different scheme. In an embodiment dispatch controller130is part of ID124.

Upon issue into execution stage306, an instruction wakes up the counters of its consumer instructions in IDB700, renaming map700and stage D2(shown inFIG. 5). This is done by broadcasting the corresponding CBID(s) and the wakeup_en bit of the issued instruction. As a result of the broadcast, renamer122in stage D1, selection control logic510in stage D2and IDB700in stage D3, set the active bit to 1 if, in the respective pipeline stage, a consumer instruction's operand's corresponding CBID matches the broadcast CBID. When active is set to 1, the corresponding counter will start to count and when it reaches zero, the corresponding BP bit is set to 1, and the operand is available for bypass.

In write to register file stage308, destination operand data of producer instructions is written from CBID128into register file106. The write to register file308results in a broadcast of the CBID and register ID for the register written thereby changing operand availability bits for corresponding entries in IDB700in stage D1, renaming map600in stage D2and in stage D3. If there is a match between source operand CBIDs and broadcast CBIDs of registers written to register file106, then IDB700sets inRF bits for corresponding source operands as 1 since the operands are now available in register file106.

In an embodiment, IDB700, renamer124and selection control logic510compare source operand CBIDs in their respective pipeline stages against the CBIDs broadcast when an instruction writes to completion buffer128. If there is a match between source operand CBIDs and broadcast CBIDs then IDB700, renamer124and selection control logic510set inRF and avail bits for corresponding source operands as 1 since the operands are now predictably available (even though they have not yet been written to register file106).

For producer instructions with a long latency for completion (such as a multiply instruction) renamer122sets the avail bit as 0 in renaming map600for the operand to be modified by the long latency instruction. The avail bit is set to 1 in IDB700, renaming map600and in stage D2only when the operand modified by a long latency producer is predictably available in processor100and a broadcast by the long latency producer indicates predictable availability of an operand.

The wakeup_en value stored for each instruction in IDB700is appended to the instruction by ID124. When an instruction is issued from IDB700by dispatch controller130, the wakeup_en bit is propagated with the instruction. For example, inFIG. 5, instruction512is appended with a wakeup_en value and propagated into stage D4via register508.

Wakeup_en, along with a corresponding CBID, is broadcast by a producer instruction entering instruction execute stage306. Broadcast of wakeup_en sets active bits of corresponding source operands in IDB700, renaming map600and in stage D2, to 1. Depending on the value of wakeup_en, active bits may not be set at all or setting of the active bits may be delayed. For example, if wakeup_en is 00, then the counter is not started. If wakeup_en is 01, active bits are set to 1 in the same cycle and the counter is started. If wakeup_en is 10 then counters are started after a predetermined time period and active bits are also set to 1 after the predetermined time period (e.g. two clock cycles). If wakeup_en is 11, counters are started after another predetermined time and active bits are set to 1 after the predetermined time period (e.g. four clock cycles). Delaying the setting of active bits to 1 delays the activation of corresponding counters and consequently delays the issue of consumer instructions. In an embodiment, ID124looks up a table of wakeup_en values, as in Table 3 below, based on type of a producer instruction:

Wakeup_en values for an instruction may change after it is issued by ID124. For example, if a producer instruction is invalidated, its wakeup_en may be set to 00 by, for example, pipeline control logic120.

In an embodiment, long latency instructions broadcast a wakeup_en bit value to delay setting of the active bits of corresponding consumer source operands. Typically, a long latency instruction broadcasts its wakeup_en value and corresponding CBID upon issue into execution stage306.

In the case of unpredictable producer instructions, such as a load instructions that have a cache miss, a corresponding CBID broadcast causes the avail bits of corresponding consumer source operands in IDB700, renaming600and stage D2to be set to 0 to indicate that the load has missed and the operand value is unavailable.

IDB700is also updated due to instruction kills. Instruction kills may occur, for example if a branch mispredicts or an exception occurs. In multithreading cases, an instruction kill invalidates the instruction in that thread. For non-multithreading case, all the entries in IDB700are removed on a pipeline flush and renaming map600is reset. In multithreading cases, certain threads may be killed and their corresponding entries in IDB700and corresponding renaming maps are reset.

FIG. 8is a diagram illustrating a circuit800according to an embodiment of the invention. Circuit800is an example implementation of combinational logic706. Circuit800is used to test whether an instruction is ready for issue by ID124. Circuit800may be used to implement equation 2. Circuit800includes circuits802and804which are used to determine if source operands of an instruction are available. Each of circuits802and804may be used to implement equation 1.

Circuit802comprises OR gate806and AND gate808. OR gate806receives inputs inRF1and BP1of the first source operand of an instruction from IDB700. The result of OR gate806is fed as an input into AND gate808. AND gate808also receives avail1as an input from IDB700. Output816of AND gate808indicates availability of the first source operand of an instruction. In an example, if output816is 0 it indicates that the first source operand is not available and if output816is 1 it indicates that the first source operand is available.

Similar to circuit802, circuit804comprises OR gate810and AND gate812. OR gate810receives inputs inRF2and BP2of the second source operand of an instruction from IDB700. The result of OR gate810is fed as an input into AND gate812. AND gate812also receives avail2as an input from IDB700. Output820of AND gate812indicates availability of the second source operand of an instruction. In an example, if output820is 0 it indicates that the second source operand is not available and if output820is 1 it indicates that the second source operand is available.

Outputs816and820of circuits802and804respectively are fed as inputs to AND gate814. Output822of AND gate814indicates whether an instruction is ready for issue.

FIG. 9illustrates a state machine900used to control the active and BP bits of a consumer instruction according to an embodiment of the invention. State machine900may be part of ID124and is replicated for each entry in IDB700. State machine900may also be part of renamer700, and selection control logic510. State machine900comprises three states902,904and906.

In state902, active is 0 and BP is 0 while start is false. Start is a flag that is based upon the value of wakeup_en. By default start is false and is dependent on a wakeup_en broadcast of a producer instruction. For example, if a producer broadcasts wakeup_en as 00, start remains false. If wakeup_en is broadcast as 01, start is set as true in the same clock cycle. If wakeup_en is 10, start is set as true2clock cycles after receiving the broadcast. If wakeup_en is 11, start is set as true four cycles after receiving the broadcast. The number of cycles and example wakeup_en values are arbitrary and may change according to implementation. When start is set as true, control transitions to state904.

In state904, the active bit of the corresponding source operand is set as 1 and the corresponding counter is activated. The counter decrements the corresponding count value (CNT) every cycle. An example counter is described below with reference toFIG. 10. Control remains in state904while CNT is greater than 0. The bypass enable bit BP is also zero in state904. When CNT is 0, control transfers to state906.

In state906, since CNT is 0, BP is set as 1 and the corresponding consumer instruction can be issued so as to receive a bypassed operand value from the producer instruction before execution. Control stays in state906until it is reset back to state902for the next instruction.

State machine900may be implemented in hardware, software and firmware or any combination thereof.

FIG. 10is a diagram illustrating an example embodiment of a counter1000according to an embodiment of the invention. Counter1000may be used in renamer600, IDB700and selection control logic510to count down a count value of a consumer source operand upon receiving a broadcast from a corresponding producer instruction. Counter1000is initialized with an initial count value by renamer600or in stage D2by control logic510. Counter1000includes four shift registers1002a-d. Each shift register1002comprises a set input (S), a reset input (R), a clock input (CLK), data input (IN) and data output Q. In the present embodiment, each shift register1000receives the same clock signal CLK_IN1006. Each shift register may be initialized with the initial count value either via data input (IN) or via the set and reset inputs. Once counter1000is activated it decrements the count value by shifting a bit to the right each cycle. In an embodiment, when least significant shift-register1002dreceives a 1 and shift-registers1002a-care 0, the corresponding BP bit is set as 1.

In embodiments presented herein, example instructions have two source operands and one destination operand. In other embodiment, instructions have one or more source operands and multiple destination operands. Operand availability bits avail, inRF, active, BP and counter values are also referred to as a local or distributive scoreboard since they are appended to an instruction and propagated through multiple pipeline stages of processor100. Although not shown for simplifying explanation, it is to be appreciated that CBIDs for source operands and destination operand, IIDs and register IDs may also be propagated through multiple pipeline stages. In an embodiment, broadcasts by a producer instruction may include the instruction's CBID as well as the CBID of the operand being modified. In examples presented herein, the count value is 2 bits to limit size of counters and registers. It is to be appreciated that the size of count value is arbitrary and depends upon implementation.

While the foregoing is a complete description of exemplary embodiments of the invention, it should be evident that various modifications, alternatives, and equivalents may be made and used. It is also to be appreciated that the detailed description of the present invention provided herein, and not the summary and abstract sections, is intended to be used to interpret the claims. The summary and abstract sections may set forth one or more but not all exemplary embodiments of the present invention as contemplated by the inventors.

For example, in addition to implementations using hardware (e.g., within or coupled to a Central Processing Unit (“CPU”), microprocessor, microcontroller, digital signal processor, processor core, System on Chip (“SOC”), or any other programmable or electronic device), implementations may also be embodied in software (e.g., computer readable code, program code, instructions and/or data disposed in any form, such as source, object or machine language) disposed, for example, in a computer usable (e.g., readable) medium configured to store the software. Such software can enable, for example, the function, fabrication, modeling, simulation, description, and/or testing of the apparatus and methods described herein. For example, this can be accomplished through the use of general programming languages (e.g., C, C++), GDSII databases, hardware description languages (HDL) including Verilog HDL, VHDL, and so on, or other available programs, databases, and/or circuit (i.e., schematic) capture tools. Such software can be disposed in any known computer usable medium including semiconductor, magnetic disk, optical disk (e.g., CD-ROM, DVD-ROM, etc.) and as a computer data signal embodied in a computer usable (e.g., readable) transmission medium (e.g., carrier wave or any other medium including digital, optical, or analog-based medium). As such, the software can be transmitted over communication networks including the Internet and intranets.

It is understood that the apparatus and method embodiments described herein may be included in a semiconductor intellectual property core, such as a microprocessor core (e.g., embodied in HDL) and transformed to hardware in the production of integrated circuits. Additionally, the apparatus and methods described herein may be embodied as a combination of hardware and software. Thus, the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalence.