CYCLE ACCURATE TRACING OF VECTOR INSTRUCTIONS

Systems and methods are disclosed for cycle accurate tracing of vector instructions. For example, a system may include a vector unit in communication with a scalar core. The vector unit may include a vector instruction queue that receives vector instructions from the scalar core. The vector unit may also include a vector execution unit that executes vector instructions from the vector instruction queue. The system may also include checkpoints in the vector unit including a first checkpoint including circuitry that sets a first bit for a first clock cycle in which a first vector instruction exits the vector instruction queue, and a second checkpoint including circuitry that sets a second bit for a second clock cycle in which a second vector instruction exits the vector execution unit.

FIELD OF TECHNOLOGY

This disclosure relates generally to integrated circuits, and more specifically, to cycle accurate tracing of vector instructions.

BACKGROUND

Instruction tracing is a technique used to analyze the history of instructions executed by a processor. Information associated with one or more instructions may be collected from a processor executing the instructions. The information collected may be analyzed to determine system performance and to help identify possible optimizations for improving the system.

DETAILED DESCRIPTION OF THE INVENTION

A processor may be implemented with a scalar core (also referred to as an “integer unit”) and a vector unit connected to the scalar core. The scalar core may have one or more scalar execution units in instruction pipelines for executing scalar instructions which operate on one data element at a time. The vector unit may have a vector instruction queue and one or more vector execution units for executing vector instructions which operate on multiple data elements at the same time. In operation, the scalar core may fetch, decode, execute, and retire scalar instructions, and may fetch and dispatch vector instructions to the vector unit for execution by the vector unit. The vector unit, in turn, may receive the vector instructions from the scalar core and may queue, execute, and retire the vector instructions.

It may be useful to investigate the performance of scalar and vector instructions being executed, such as the timing in which instructions complete their execution. Understanding the timing in which instructions execute may allow an engineer to identify delays or stalls in the processor and/or other aspects of performance that may be utilized for improving the design of the processor. One technique for determining the timing of instructions is to implement circuitry in silicon which measures the clock cycles in which instructions complete through the scalar core. However, this technique may provide only limited information with regard to vector instructions, such as the timing in which the vector unit receives the instructions.

This technique may not provide information about instructions moving through the vector unit, such as delays associated with queuing vector instructions prior to their execution, or delays associated with completion of vector instructions through the vector unit. Further, this technique may utilize resources of the system under test, for example if the measurements being taken are routed and stored in hardware.

Another technique for determining the timing of instructions being executed is to simulate the movement of the instructions in a simulation environment. A simulation environment can measure the timing of instructions moving through the scalar core and/or the vector unit with less burden to the system by adding general purpose computing resources. However, while simulation may be useful, timing obtained from a simulation environment may have some differences when compared to timing obtained from an implementation in silicon-in other words true cycle accurate timing may not be available through simulation. Accordingly, there is a need for accurately determining the timing of vector instructions moving through a vector unit with minimal burden to the system.

Described herein are techniques for cycle accurate tracing of vector instructions in which the timing of instructions moving through various points of a vector unit may be accurately determined in silicon with a compact amount of data associated with the measurements being taken. A group of checkpoints, such as circuitry comprising latches or flip-flops, may be implemented in certain points of a processor including a vector unit implemented in silicon. The checkpoints may include: a first checkpoint including circuitry that sets a first bit for a first clock cycle in which a first vector instruction exits a vector instruction queue, and a second checkpoint including circuitry that sets a second bit for a second clock cycle in which a second vector instruction exits a vector execution unit (or retires from the vector unit). Another checkpoint may be implemented using circuitry that sets a third bit for a third clock cycle in which a third vector instruction is dispatched from the scalar core to the vector instruction queue. Depending on the situation, the first, second, and third clock cycles may refer to the same or two or three different clock cycles and the first, second, and third vector instructions may refer to the same instance of a vector instruction or two or three different instances of vector instructions. Each vector execution unit may be implemented by the vector core for a predetermined purpose, such as arithmetic, load, and store units implemented for arithmetic, load, and store operations associated with vector instructions, respectively. During a capture period, bits associated with the checkpoints may be captured for a number of clock cycles and stored in a trace buffer, such as a local storage buffer, static random access memory (SRAM), dynamic random access memory (DRAM), or other storage space. In some implementations, a trace control system may be used to associate a vector instruction obtained from a scalar core with a bit set by a checkpoint for a particular clock cycle in order to correlate the vector instruction with a particular clock cycle (also referred to as “de-queueing”). In some implementations, bits obtained from checkpoints may be compressed to further reduce routing and/or storage of data. Such an implementation may operate to provide an accurate determination of the timing of vector instructions moving through a vector unit implemented in silicon utilizing a compact amount of data for the measurements being taken.

In some implementations, one or more additional checkpoints may be configured to capture bits associated with multiple operations of an individual vector instruction (e.g., micro-operations associated with one vector instruction). For example, one or more additional checkpoints may be configured to capture bits associated with loads and/or stores associated with one or more data elements on which a vector instruction operates. In other words, bits may be captured to give greater visibility into the execution of one vector instruction over multiple clock cycles. In some implementations, one or more additional checkpoints may be configured to capture bits associated with memory accesses of vector instructions from a memory system, such as a private level 2 (L2) cache or a shared level 3 (L3) cache. For example, one or more additional checkpoints may be configured to capture bits that indicate a cache miss associated with a vector instruction.

FIG.1is a block diagram of an example of a system100for cycle accurate tracing of vector instructions. The system100includes a scalar core102, a vector unit104, and a cycle accurate trace buffer106. The scalar core102and the vector unit104may be implemented together in silicon, such as in an application specific integrated circuit (ASIC), a system-on-chip (SoC), or field-programmable gate array (FPGA). Additionally, the scalar core102and the vector unit104may communicate with one another synchronously via a clock generating clock cycles. The cycle accurate trace buffer106may be implemented in silicon by itself or with the scalar core102and the vector unit104, such in the ASIC, the SoC, or the FPGA. The cycle accurate trace buffer106may comprise data storage, such as a local storage buffer, SRAM, DRAM, or other storage space.

The scalar core102includes, among other things, one or more instruction pipelines for executing instructions in an instruction stream, such as instruction pipelines110A and110B. The instruction pipelines may fetch, decode, execute, and retire scalar instructions (which operate on one data element at a time) over multiple clock cycles. Additionally, the instruction pipelines may operate in parallel with respect to one another. For example, instruction pipeline110A may fetch, decode, execute, and retire scalar instructions while instruction pipeline110B also fetches, decodes, executes, and retires scalar instructions. Additionally, the instruction pipelines may fetch and dispatch vector instructions (which operate on multiple data elements at the same time) to the vector unit104for execution by the vector unit104. For example, instruction pipeline110A may fetch and dispatch vector instructions to the vector unit104while instruction pipeline110B also fetches and dispatches vector instructions to the vector unit104. Further, a combination of scalar and vector instructions may also move through the instruction pipelines110A and110B in parallel over multiple clock cycles. For example, instruction pipeline110A may fetch, decode, execute, and retire scalar instructions while instruction pipeline110B fetches and dispatches vector instructions to the vector unit104.

The vector unit104may include, among other things, a vector instruction queue120, and one or more vector instruction execution units (also referred to as “vector execution units” or “sequencers”), such as vector execution units130A through130C. The instruction serializer115may take vector instructions arriving in parallel from the scalar core102, on the same clock cycle, and serialize the vector instructions for entry into the vector instruction queue120one at a time. The vector instruction queue120may receive and queue the vector instructions one at a time. The vector instruction queue120may implement a first in, first out (FIFO) instruction storage architecture in which a first vector instruction queued is also a first vector instruction to be dispatched from the queue.

The vector instruction queue120dispatches vector instructions to specific vector execution units. For example, the vector instruction queue120may dispatch vector instructions to specific vector execution units depending on the opcode of the instruction. The “opcode” may refer to a portion of the instruction that specifies the operation to be performed. Each vector execution unit may be implemented by the vector unit104for a predetermined purpose, such as arithmetic, load, and store units implemented for arithmetic, load, and store operations with vector instructions, respectively. For example, vector execution unit130A may be an arithmetic unit, vector execution unit130B may be a load unit, and vector execution unit130C may be a store unit. Additionally, while the vector instruction queue120may receive vector instructions in parallel, the vector instruction queue120dispatches vector instructions serially to the vector execution units. For example, the vector instruction queue120may dispatch a first vector instruction to vector execution unit130A, followed by a second vector instruction to vector execution unit130B, followed by a third vector instruction to vector execution unit130C. The vector execution units, in turn, execute the vector instructions and retire them from the vector unit104.

For cycle accurate tracing of vector instructions in which the precise

timing of instructions moving through the vector unit104may be determined, a group of checkpoints may be implemented in the scalar core102and/or the vector unit104implemented in silicon, such as checkpoints140A through140F. The checkpoints may include circuitry including latches or flip-flops implemented in certain points of the scalar core102and/or the vector unit104. Arrival of an instruction at a checkpoint during a clock cycle may cause a signal to trigger the checkpoint to set a bit (e.g., “1”) indicating the arrival of the instruction. The bit may be cleared (e.g., “0”) on a next clock cycle (and subsequent clock cycles) unless another instruction arrives to set the bit again. By way of example, the checkpoints may include: checkpoint140A including circuitry that sets a bit for a clock cycle in which an instruction dispatches from an instruction pipeline of the scalar core102, such as from instruction pipeline110A (e.g., which may include a vector instruction dispatching from the instruction pipeline110A to the vector unit104); checkpoint140B including circuitry that sets a bit for a clock cycle in which an instruction dispatches from another instruction pipeline of the scalar core102, such as from instruction pipeline110B (e.g., which may include a vector instruction dispatching from the instruction pipeline110B to the vector unit104); checkpoint140C including circuitry that sets a bit for a clock cycle in which a vector instruction exits the vector instruction queue120; checkpoint140D including circuitry that sets a bit for a clock cycle in which a vector instruction exits a vector execution unit, such as vector execution unit130A; checkpoint140E including circuitry that sets a bit for a clock cycle in which a vector instruction exits another vector execution unit, such as vector execution unit130B; and checkpoint140F including circuitry that sets a bit for a clock cycle in which a vector instruction exits another vector execution unit, such as vector execution unit130C.

Accordingly, some checkpoints may be implemented in the scalar core102while other checkpoints may be implemented in the vector unit104. For example, checkpoints140A and140B may be implemented in the scalar core102while checkpoints140C through140F may be implemented in the vector unit104. Additionally, checkpoints may be implemented differently depending on the implementation-for example, in some implementations, checkpoints140A and140B may be implemented in the vector unit104or may be combined into a single checkpoint.

In operation, the presence of an instruction at a checkpoint may cause the checkpoint to set a bit during a clock cycle. For example, checkpoint140A may set a bit for a first clock cycle if a first instruction is present at the checkpoint140A, checkpoint140B may set a bit for a second clock cycle if a second instruction is present at the checkpoint140B, checkpoint140C may set a bit for a third clock cycle if a third instruction is present at the checkpoint140C, checkpoint140D may set a bit for a fourth clock cycle if a fourth instruction is present at the checkpoint140D, checkpoint140E may set a bit for a fifth clock cycle if a fifth instruction is present at the checkpoint140E, and checkpoint140F may set a bit for a sixth clock cycle if a sixth instruction is present at the checkpoint140F. Additionally, instructions may set bits at checkpoints during multiple clock cycles. For example, checkpoint140A may set a bit for a first clock cycle if a first instruction is present at the checkpoint140A, checkpoint140C may set a bit for a second clock cycle if the first instruction is present at the checkpoint140C, and checkpoint140D may set a bit for a third clock cycle if the first instruction is present at the checkpoint140D. In some implementations, checkpoints140A and140B, when implemented in the scalar core102, may set a bit when either a scalar instruction or a vector instruction is present at the checkpoint. In some implementations, checkpoints140C through140F, when implemented in the vector unit104, may set a bit when a vector instruction is present at the checkpoint. In some implementations, the checkpoints are configured to set a bit for instructions relating to one or more vector instructions. For example, instructions relating to one or more vector instructions may include branches or jumps following or preceding certain vector instructions.

The system100may store the captured bits at an address in the cycle accurate trace buffer106with the bits stored in predetermined positions for later decoding, such as bits in positions corresponding to an order of the checkpoints and an order of the clock cycles. For example, the system100may capture six bits, corresponding to checkpoints140A through140F, for five clock cycles, totaling 30 captured bits (six bits*five clock cycles). The system100may store the 30 captured bits, along with 2 bits for framing (e.g., sync bits), as a 32-bit word at an address in the cycle accurate trace buffer106. The captured bits may be stored in predetermined positions in the 32-bit word for later decoding and associating with vector instructions, such as a bit in a position corresponding to one of the checkpoints140A through140F and one of the five clock cycles. Continuing with this example, the system100may further capture another six bits, again corresponding to checkpoints140A through140F, for another five clock cycles, totaling another 30 captured bits (six bits*five clock cycles). The system100may store these 30 captured bits, along with 2 bits for framing (e.g., sync bits), as a next 32-bit word at a next address in the cycle accurate trace buffer106. The captured bits may again be stored in predetermined positions in the 32-bit word, and in an order of the address in the cycle accurate trace buffer106, for later decoding and associating with vector instructions. In this way, a trace control system may execute to decode the bits in the cycle accurate trace buffer106to associate the bits with vector instructions moving through the vector unit104for cycle accurate tracing of vector instructions. For example, the trace control system may be used with a trace encoder to trace the vector instructions from the scalar core and correlate the instructions with the bits. The number of bits captured per clock cycle and the format in which bits are stored may vary, for example, depending on the number of units for which there are associated checkpoints and the number of checkpoints (e.g., with respect to implementations where checkpoints may be consolidated).

In some implementations, the bits stored in the cycle accurate trace buffer106may be compressed to reduce bandwidth for routing the bits to the trace buffer and/or to reduce storage in the trace buffer. For example, a compression algorithm may be applied to compress multiple 32-bit words (each including six bits, corresponding to checkpoints140A through140F, captured for five clock cycles) into a single 32-bit word stored in the cycle accurate trace buffer106. For example, a run-length or differential coding compression algorithm could be utilized to reduce the storage space needed for the captured bits. The compressed 32-bit word may be decompressed to restore the positions of bits for correlating to vector instructions.

In some implementations, one or more additional checkpoints may be configured to capture bits associated with multiple operations of an individual vector instruction (e.g., micro-operations associated with one vector instruction). For example, one or more additional checkpoints may be configured to capture bits associated with loads and/or stores associated with one or more data elements on which a vector instruction operates. In other words, bits may be captured to give greater visibility into the execution of one vector instruction over multiple clock cycles. For example, one or more additional checkpoints may be implemented at points within the execution units (e.g., execution units130A through130C). In some implementations, one or more additional checkpoints may be configured to capture bits associated with memory accesses of vector instructions from a memory system, such as a private L2 cache or a shared L3 cache, such as at points between the execution units (e.g., execution units130A through130C) and a memory system. For example, one or more additional checkpoints may be configured to capture bits that indicate a cache miss associated with a vector instruction.

FIG.2is a block diagram of another example of a system200for cycle

accurate tracing of vector instructions. The system200includes a scalar core202and a cycle accurate trace buffer206like the scalar core102and the cycle accurate trace buffer106shown inFIG.1, respectively. The system200also includes a vector unit204like the vector unit104shown inFIG.1, with a hardware optimization to further reduce bandwidth and/or storage for cycle accurate tracing. A single checkpoint may be used to set a bit when a vector instruction exits one of multiple vector execution units. For example, a single checkpoint240E may be used to set a bit for a clock cycle in which a vector instruction exits any one of multiple vector execution units, such as vector execution units230B or230C. This may be achieved when a vector instruction may retire from one of the multiple vector execution units at a time. For example, vector execution unit230B may be a load unit, and vector execution unit230C may be a store unit. It is possible the architecture of the vector unit204may prevent a vector instruction from retiring from the load unit in parallel with a vector instruction retiring from the store unit. In this case, a single checkpoint may be used to set a bit for a clock cycle in which a vector instruction retires from either the load unit or the store unit. This may allow fewer bits to be captured per clock cycle, thereby reducing bandwidth and/or storage.

FIG.3is a block diagram of an example of a system300for

synchronizing vector instructions with cycle accurate trace circuitry. The system300includes cycle accurate trace circuitry304, a cycle accurate trace buffer306, a trace encoder308, an instruction trace buffer310, and a trace control system350. A scalar core, like the scalar core102shown inFIG.1or the scalar core202shown inFIG.2, may dispatch instructions in a stream, including vector instructions (e.g., to a vector unit, like the vector unit104shown inFIG.1or the vector unit204shown inFIG.2). For example, the scalar core may dispatch instructions one at a time or two at a time (in parallel) from one or more instruction pipelines of the scalar core, including vector instructions dispatching to the vector unit.

The cycle accurate trace circuitry304may receive signals from checkpoints in the scalar core and/or the vector unit via checkpoint ingress port(s)320. For example, the cycle accurate trace circuitry304may receive signals from checkpoints such as checkpoints140A through140F shown inFIG.1or checkpoints240A through240F shown inFIG.2. The cycle accurate trace circuitry304may also implement circuitry for capturing a program counter associated with the vector instructions (e.g., sync bits), circuitry for communicating with the trace control system350(e.g., a trace control interface), circuitry for communicating with the trace encoder308(e.g., a “SYNC” signal, an “ON” signal, and an “OFF”), and/or circuitry for moving captured bits (e.g., arriving via the checkpoint ingress port(s)320) to the cycle accurate trace buffer306(e.g., a 32-bit shift register). The cycle accurate trace circuitry304may start and stop the capture of bits associated with the arrival of instructions at the checkpoints and may store the captured bits in the cycle accurate trace buffer306(e.g., a cycle accurate trace). The cycle accurate trace buffer306may comprise data storage like the cycle accurate trace buffer106shown inFIG.1or the cycle accurate trace buffer206shown inFIG.2.

The trace encoder308may monitor instructions dispatched by the scalar core, including vector instructions, via an instruction trace port330. In some implementations, instruction trace port330may be specific to the vector unit and may provide for the monitoring of only vector instructions or instructions related thereto. The trace encoder308may be implemented in hardware, software, or a combination thereof. For example, in some implementations, the trace encoder308may include circuitry for communicating with the trace control system350and circuitry for communicating with the cycle accurate trace circuitry304(e.g., the “SYNC” signal, the “ON” signal, and the “OFF”), such as for syncing with the cycle accurate trace circuitry304and starting and stopping the capture of bits. The trace encoder308may trace instructions in the stream, including vector instructions, and store the instructions in the instruction trace buffer310(e.g., an instruction trace). For example, the trace encoder308may store addresses, opcodes, and/or arguments associated with instructions in the stream, decode specific types of the instructions (e.g., branches and jumps), and compress the instructions for storage in the instruction trace buffer310based on the decoding. In some implementations, the trace encoder308may store sync points for correlating vector instructions with captured bits in the cycle accurate trace buffer306.

The trace control system350may access the cycle accurate trace stored in the cycle accurate trace buffer306and the instruction trace stored in the instruction trace buffer310. The trace control system350may execute software (e.g., trace de-queueing software) to associate specific vector instructions in the instruction trace with cycle accurate tracing captured by the cycle accurate trace circuitry304. For example, the trace encoder308may monitor instructions in the stream, such as with respect to addresses, opcodes, and/or arguments, via the instruction trace port330, and the cycle accurate trace circuitry304may capture cycle accurate bits via the checkpoint ingress port(s)320. The trace control system350may then associate vector instructions monitored by the trace encoder308(e.g., in the stream) with bits captured by the cycle accurate trace circuitry304. For example, the trace encoder308and/or the trace control system350may be implemented on the system400ofFIG.4.

For example, the trace encoder308may monitor vector instructions in a stream (e.g., with respect to the RISC-V vector instruction set, “vle32.v” and “vfmacc.vf” instructions arriving in parallel) and the cycle accurate trace circuitry304may capture cycle accurate bits associated with the stream. The trace control system350may associate a first vector instruction (e.g., “vle32.v”) with a first bit set by a first checkpoint (e.g., checkpoint140A shown inFIG.1) during a first clock cycle and associate a second vector instruction (e.g., “vfmacc.vf”) with second a bit set by a second checkpoint (e.g., checkpoint140B shown inFIG.1) also during the first clock cycle (e.g., arriving in parallel). Additionally, the trace control system350may further associate the first vector instruction (e.g., “vle32.v”) with a third bit set by a third checkpoint (e.g., checkpoint140C shown inFIG.1) during a second clock cycle, and to a fourth bit set by a fourth checkpoint (e.g., checkpoint140D shown inFIG.1) during a third clock cycle. Similarly, the trace control system350may further associate the second vector instruction (e.g., “vfmacc.vf”) with a third bit set by the third checkpoint (e.g., checkpoint140C shown inFIG.1) during a fourth clock cycle, and to a fourth bit set by a fourth checkpoint (e.g., checkpoint140E shown inFIG.1) during a fifth clock cycle. In this way, the trace control system350may correlate the timing of vector instructions through the vector unit with specific vector instructions. While the foregoing description refers to RISC-V vector instructions as an example, implementations of this disclosure may also be utilized with vector instructions based on different vector instruction sets.

Additionally, the trace control system350may produce associations between vector instructions in the stream and bits captured by the cycle accurate trace circuitry304in order to associate vector instructions with checkpoints and clock cycles in the trace. The associations may be utilized by post-acquisition display software to permit a user to see the cycle accurate timing of a vector instruction as it is dispatched from the scalar core, queued, and executed in the vector unit as traces of vector instructions. For example, the foregoing software may be executed on a computer system such as the system400ofFIG.4.

In some implementations, to permit associations between a vector instruction in the instruction stream with a bit captured by the cycle accurate trace circuitry304, the trace encoder308and the cycle accurate trace circuitry304may synchronize with one another so that the trace encoder308and the cycle accurate trace circuitry304start and stop in concert. In some implementations, the trace encoder308and/or the cycle accurate trace circuitry304may be controlled by the trace control system350through a trace control interface configured as a TileLink slave node appearing in physical memory, including as described in the SiFive TileLink Specification, Version 1.8.1, Jan. 27, 2020. In some implementations, the trace control interface may be configured for use with a JTAG (Joint Test Action Group) probe. To begin collecting a trace, the trace control system350may command the cycle accurate trace circuitry304to start a capture period, such as by writing to a memory-mapped register instructing the cycle accurate trace circuitry304to begin. In response, the cycle accurate trace circuitry304may capture sync bits (e.g., serialized as two bits, which may be used for framing a 32-bit word). The sync bits may be associated with an address of a program counter that points to a vector instruction. The cycle accurate trace circuitry304may insert the sync bits in the cycle accurate trace stream (e.g., captured in the cycle accurate trace buffer306). The cycle accurate trace circuitry304may also send a “SYNC” message to the trace encoder308indicating the sync point. The trace encoder308may receive the SYNC message a number of clock cycles later (e.g., skew). Upon receipt of the SYNC message, the trace encoder308may capture an address of a program counter that points to an instruction in the instruction trace. The trace encoder308may insert the sync point (e.g., the address of the program counter) in the instruction trace stream (e.g., captured in the instruction trace buffer310). The sync bits in the cycle accurate trace stream and the sync point in the instruction trace stream may permit the trace control system350to correlate bits captured by the cycle accurate trace circuitry304with vector instructions traced by the trace encoder308. The control system350may adjust for the number of clock cycles between the sync bits in the cycle accurate trace stream and the sync point in the instruction trace stream (e.g., the skew) when determining the correlation. In some implementations, the trace encoder308may send the “ON” signal and the “OFF” signal to the cycle accurate trace circuitry304to control the range for capturing bits in the cycle accurate trace buffer306(e.g., to limit the capture period). This may permit saving storage space in the cycle accurate trace buffer306. In some implementations, the “ON” signal and the “OFF” signal may be generated by watchpoints comprising address comparators configured to match executed instruction addresses and/or data read and/or write addresses. Data stored in the cycle accurate trace buffer306and in the instruction trace buffer310may be accessed by the trace control system350. For example, the trace control system350may access the data to determine associations between vector instructions in the instruction stream and bits captured by the cycle accurate trace circuitry304. These associations may be used to determine the clock cycles at which a particular vector instruction is present at a particular checkpoint. Further, the trace control system350may execute post-acquisition display software to permit a user to see the cycle accurate timing of a vector instruction as it is dispatched from the scalar core, queued, and executed in the vector unit.

In some implementations, to associate specific vector instructions in the instruction stream with bits captured by the cycle accurate trace circuitry304, the vector instruction queue (such as the vector instruction queue120ofFIG.1) may be flushed. For example, a predetermined “fence” instruction (e.g., a type of barrier instruction that causes a processor to enforce an ordering constraint on memory operations issued before and after the barrier instruction) may dispatch from the scalar core to the vector unit to flush the vector instruction queue. The trace encoder308and/or the control system350may recognize the fence instruction in the stream and use the fence instruction as an event which triggers synchronization to begin with the next vector instruction in the stream.

In some implementations, to associate specific vector instructions in the instruction stream with bits captured by the cycle accurate trace circuitry304, the trace encoder308and/or the trace control system350may wait for the vector instruction queue to empty. For example, the trace encoder308and/or the trace control system350may receive an indication from the cycle accurate trace circuitry304that the vector instruction queue is empty via a trace control interface. For example, the indication may be generated by checkpoints not setting bits (which indicate arrival of vector instructions) for a number of clock cycles corresponding to a depth of the vector instruction queue. Accordingly, the trace encoder308and/or the trace control system350may receive an indication from the cycle accurate trace circuitry304that the vector instruction queue is empty and may use the indication as an event which triggers synchronization to begin with the next vector instruction.

In some implementations, to associate specific vector instructions in the instruction stream with bits captured by the cycle accurate trace circuitry304, the trace encoder308and/or the trace control system350may permit a user to manually adjust alignment of the start signal (“ON”) to vector instructions in the stream. The trace encoder308and/or the trace control system350may also permit a user to manually adjust alignment of the stop signal (“OFF”) to vector instructions in the stream. This adjustment may provide flexibility and control to a user to employ knowledge about the code being executed. Accordingly, vector instructions moving through a vector unit implemented in silicon may be correlated with precise timing.

FIG.4is block diagram of an example of a system400facilitating cycle accurate tracing of vector instructions. The system400is an example of an internal configuration of a computing device that may be used to implement the trace encoder308and/or the trace control system350shown inFIG.3. The system400can include components or units, such as a processor402, a bus404, a memory406, peripherals414, a power source416, a network communication interface418, a user interface420, other suitable components, or a combination thereof.

The processor402can be a central processing unit (CPU), such as a microprocessor, and can include single or multiple processors having single or multiple processing cores. Alternatively, the processor402can include another type of device, or multiple devices, now existing or hereafter developed, capable of manipulating or processing information. For example, the processor402can include multiple processors interconnected in any manner, including hardwired or networked, including wirelessly networked. In some implementations, the operations of the processor402can be distributed across multiple physical devices or units that can be coupled directly or across a local area or other suitable type of network. In some implementations, the processor402can include a cache, or cache memory, for local storage of operating data or instructions. The system400can include components or units, such as a processor402, a bus404, a memory406, peripherals414, a power source416, a network communication interface418, a user interface420, other suitable components, or a combination thereof.

The memory406can include volatile memory, non-volatile memory, or a combination thereof. For example, the memory406can include volatile memory, such as one or more DRAM modules such as double data rate (DDR) synchronous dynamic random access memory (SDRAM), and non-volatile memory, such as a disk drive, a solid state drive, flash memory, Phase-Change Memory (PCM), or any form of non-volatile memory capable of persistent electronic information storage, such as in the absence of an active power supply. The memory406can include another type of device, or multiple devices, now existing or hereafter developed, capable of storing data or instructions for processing by the processor402. The processor402can access or manipulate data in the memory406via the bus404. Although shown as a single block inFIG.4, the memory406can be implemented as multiple units. For example, a system400can include volatile memory, such as RAM, and persistent memory, such as a hard drive or other storage.

The memory406can include executable instructions408, data, such as application data410, an operating system412, or a combination thereof, for immediate access by the processor402. The executable instructions408can include, for example, one or more application programs, which can be loaded or copied, in whole or in part, from non-volatile memory to volatile memory to be executed by the processor402. The executable instructions408can be organized into programmable modules or algorithms, functional programs, codes, code segments, or combinations thereof to perform various functions described herein. For example, the executable instructions408can include instructions executable by the processor402to cause the system400to execute the trace de-queueing software and/or the post-acquisition display software of the trace control system350shown inFIG.3. The application data410can include, for example, user files, database catalogs or dictionaries, configuration information or functional programs, such as a web browser, a web server, a database server, or a combination thereof. The operating system412can be, for example, Microsoft Windows®, macOS®, or Linux®; an operating system for a small device, such as a smartphone or tablet device; or an operating system for a large device, such as a mainframe computer. The memory406can comprise one or more devices and can utilize one or more types of storage, such as solid state or magnetic storage.

The peripherals414can be coupled to the processor402via the bus404.

The peripherals414can be sensors or detectors, or devices containing any number of sensors or detectors, which can monitor the system400itself or the environment around the system400. For example, a system400can contain a temperature sensor for measuring temperatures of components of the system400, such as the processor402. Other sensors or detectors can be used with the system400, as can be contemplated. In some implementations, the power source416can be a battery, and the system400can operate independently of an external power distribution system. Any of the components of the system400, such as the peripherals414or the power source416, can communicate with the processor402via the bus404.

The network communication interface418can also be coupled to the processor402via the bus404. In some implementations, the network communication interface418can comprise one or more transceivers. The network communication interface418can, for example, provide a connection or link to a network, via a network interface, which can be a wired network interface, such as Ethernet, or a wireless network interface. For example, the system400can communicate with other devices via the network communication interface418and the network interface using one or more network protocols, such as Ethernet, transmission control protocol (TCP), Internet protocol (IP), power line communication (PLC), wireless fidelity (Wi-Fi), infrared, general packet radio service (GPRS), global system for mobile communications (GSM), code division multiple access (CDMA), or other suitable protocols.

A user interface420can include a display; a positional input device, such as a mouse, touchpad, touchscreen, or the like; a keyboard; or other suitable human or machine interface devices. The user interface420can be coupled to the processor402via the bus404. Other interface devices that permit a user to program or otherwise use the system400can be provided in addition to or as an alternative to a display. In some implementations, the user interface420can include a display, which can be a liquid crystal display (LCD), a cathode-ray tube (CRT), a light emitting diode (LED) display (e.g., an organic light emitting diode (OLED) display), or other suitable display. In some implementations, a client or server can omit the peripherals414. The operations of the processor402can be distributed across multiple clients or servers, which can be coupled directly or across a local area or other suitable type of network. The memory406can be distributed across multiple clients or servers, such as network-based memory or memory in multiple clients or servers performing the operations of clients or servers. Although depicted here as a single bus, the bus404can be composed of multiple buses, which can be connected to one another through various bridges, controllers, or adapters.

FIG.5is an example of a list view500associated with cycle accurate tracing of vector instructions. For example, the list view500may be prepared by post-acquisition display software executed by a trace control system, such as the trace control system350shown ofFIG.3. The list view500may be output to a display, such as to the user interface420ofFIG.4. The list view500illustrates vector instruction traces indicating cycle accurate timing of vector instructions moving between checkpoints of the processor. The timing is based on the associations between vector instructions monitored in a stream and bits captured by cycle accurate trace circuitry, such as the cycle accurate trace circuitry304shown inFIG.3. Accordingly, the list view500may comprise traces of vector instructions, with cycle accurate timing, displayed in a table format.

The list view500includes a number of rows502corresponding to clock cycles. The clock cycles may be sequential clock cycles during a capture period, such as clock cycles starting and stopping in synchronization with a trace encoder, such as the trace encoder308shown inFIG.3. The list view500also includes a number of columns504corresponding to checkpoints. For example, the columns504may correspond to checkpoints A through F, which represent checkpoints140A through140F shown inFIG.1, respectively. Each column504may show a cascade of instructions in time through its corresponding checkpoint. An entry with an instruction name indicates a bit being set (e.g., “1”) by a checkpoint for a clock cycle, corresponding to arrival of an instruction. Additionally, absence of an entry indicates a bit being clear (e.g., “0”) by a checkpoint for a clock cycle if a vector instruction is not present at the checkpoint during that clock cycle.

For example, for tracing the vector instruction “vle32.v,” checkpoint A (e.g., checkpoint140A shown inFIG.1) indicates arrival of the “vle32.v” instruction in a row corresponding to clock cycle 0001 as determined by a trace encoder (e.g., trace encoder308shown inFIG.3). This indicates the “vle32.v” instruction is dispatched to the vector unit (e.g., vector unit104shown inFIG.1) from the scalar core during clock cycle 0001. Next, checkpoint C (e.g., checkpoint140C shown inFIG.1) indicates arrival of the “vle32.v” instruction in a row corresponding to clock cycle 0002, as determined by the trace encoder. This indicates the “vle32.v” instruction exited the vector instruction queue of the vector unit during clock cycle 0002. This also indicates the “vle32.v” instruction moved from the first checkpoint to the second checkpoint in one clock cycle. Next, checkpoint E (e.g., checkpoint140E shown inFIG.1) indicates arrival of the “vle32.v” instruction in a row corresponding to clock cycle 0005, as determined by the trace encoder. This indicates the “vle32.v” instruction exited a vector execution unit (e.g., vector execution unit130B shown inFIG.1, which may be a load unit) during clock cycle 0005. This also indicates the “vle32.v” instruction moved from the second checkpoint to the third checkpoint in three clock cycles. Using this information, a user may analyze movement of vector instructions in the vector unit. Additionally, the user may identify delays or stalls in the vector unit, such as excessive clock cycles between checkpoints, for improving the integrated circuit design.

In some implementations, the columns504may include the clock cycle counts for instructions arriving from previous checkpoints. In some implementations, the columns504may also include addresses, opcodes, and/or arguments for the instructions.

FIG.6is an example of a waveform view600associated with cycle accurate tracing of vector instructions. For example, the waveform view600may be prepared by post-acquisition display software executed by a trace control system, such as the trace control system350ofFIG.3. The waveform view600may be output to a display, such as to the user interface420ofFIG.4. The waveform view600illustrates vector instruction traces indicating cycle accurate timing of vector instructions moving between checkpoints of the processor. The timing is based on the associations between vector instructions monitored in a stream and bits captured by cycle accurate trace circuitry, such as the cycle accurate trace circuitry304shown inFIG.3. Accordingly, the waveform view600may comprise traces of vector instructions, with cycle accurate timing, displayed in a pipeline timing diagram format.

The waveform view600may include a list of instructions602corresponding to rows604in a grid. Slots in the grid may represent clock cycles. The clock cycles may be sequential clock cycles during a capture period, such as clock cycles starting and stopping in synchronization with a trace encoder, such as the trace encoder308shown inFIG.3. A marker in a slot, such as a vertical bar, may indicate a bit being set (e.g., “1”) by a checkpoint for a clock cycle, corresponding to arrival of an instruction. Additionally, absence of the marker in a slot indicates a bit being clear (e.g., “0”) by a checkpoint for a clock cycle while the checkpoint awaits arrival of an instruction. A line between vertical bars indicates timing of the instruction through clock cycles. The waveform view600may scroll horizontally, e.g., left to right, to view multiple clock cycles for vector instructions.

For example, for tracing the vector instruction “vle32.v,” a vertical bar in slot one indicates arrival of the “vle32.v” instruction at a first checkpoint (e.g., checkpoint140A shown inFIG.1) as determined by a trace encoder (e.g., trace encoder308shown inFIG.3).

This indicates the “vle32.v” instruction dispatched to the vector unit (e.g., vector unit104shown inFIG.1) from the scalar core. Next, a vertical bar in slot two indicates arrival of the “vle32.v” instruction at a second checkpoint (e.g., checkpoint140C shown inFIG.1) as determined by the trace encoder. This indicates the “vle32.v” instruction exited the vector instruction queue. This also indicates the “vle32.v” instruction moved from the first checkpoint to the second checkpoint in one clock cycle. Next, a vertical bar in slot five indicates arrival of the “vle32.v” instruction at a third checkpoint (e.g., checkpoint140D, checkpoint140E, or checkpoint140F shown inFIG.1) as determined by the trace encoder. This indicates the “vle32.v” instruction exited a vector execution unit. This also indicates the “vle32.v” instruction moved from the second checkpoint to the third checkpoint in three clock cycles. In some implementations, the trace encoder may execute to determine the specific checkpoint, such as by analyzing the order, address, opcode, and/or arguments of the instruction. In this way, a user may analyze movement of vector instructions in the vector unit. Additionally, the user may identify delays or stalls in the vector unit, such as excessive clock cycles between checkpoints, for improving the integrated circuit design.

FIG.7is a flow chart of an example of a process700for associating vector instructions with bits captured by cycle accurate trace circuitry. The process700includes capturing702multiple bits at checkpoints; storing704the captured bits in a trace buffer; associating706vector instructions with the captured bits; and outputting708to a display the associations between the captured bits and the vector instructions. For example, the process700may be implemented using the system100shown inFIG.1, the system200shown inFIG.2, and/or the system300shown inFIG.3.

The process700includes capturing702bits at checkpoints implemented in a scalar core and/or a vector unit implemented in silicon, such as checkpoints140A through140F shown inFIG.1or checkpoints240A through240F shown inFIG.2. The checkpoints may include a first checkpoint including circuitry that sets a first bit for a clock cycle in which a vector instruction exits a vector instruction queue, and a second checkpoint including circuitry that sets a second bit for a clock cycle in which a vector instruction exits a vector execution unit. The bits may be captured during multiple clock cycles of a capture period. The bits may be captured in synchronization with a trace encoder, such as the trace encoder308shown inFIG.3.

The process700also includes storing704the captured bits in a trace buffer comprising data storage, such as the cycle accurate trace buffer106shown inFIG.1, the cycle accurate trace buffer206shown inFIG.2, or the cycle accurate trace buffer306shown inFIG.3. The bits may be stored in predetermined positions for later decoding, such as bits in positions corresponding to an order of the checkpoints and an order of the clock cycles. Additionally, the bits may be stored at predetermined addresses in the trace buffer for later decoding, such as storing captured bits in a 32-bit word of bits at a first address, followed by a 32-bit word of bits at a second address, and so forth.

The process700also includes associating706vector instructions being traced with the captured bits. For example, a trace control system may execute trace de-queueing software to associate specific vector instructions in an instruction stream (e.g., monitored by a trace encoder) with bits being captured by cycle accurate trace circuitry, such as the cycle accurate trace circuitry304show inFIG.3. Multiple vector instructions may be associated with various captured bits. For example, a first vector instruction may be associated with a first bit set by a first checkpoint during a clock cycle; a second vector instruction may be associated with a second bit set by a second checkpoint during a clock cycle; and a third vector instruction may be associated with a third bit set by a third checkpoint during a clock cycle. Additionally, a vector instruction may be associated with captured bits through multiple clock cycles. For example, a vector instruction may be associated with a first bit set by a first checkpoint during a first clock cycle, a second bit set by a second checkpoint during a second clock cycle, and a third bit set by a third checkpoint during a third clock cycle.

The process700also includes outputting708to a display, such as the user interface420ofFIG.4, vector instruction traces indicating cycle accurate timing of vector instructions moving between checkpoints of the processor. The timing is based on the associations between vector instructions monitored in a stream and bits captured by the cycle accurate trace circuitry. In some implementations, the traces of the vector instructions may be displayed in a list view, such as the list view500shown inFIG.5. In some implementations, the traces of the vector instructions may be displayed in a waveform view, such as the waveform view600shown inFIG.6. The traces may indicate numbers of clock cycles between vector instructions arriving at checkpoints. Displaying traces of the vector instructions may permit a user to analyze movement of vector instructions in a vector unit, such as to identify delays or stalls in the vector unit for improving the integrated circuit design.

FIG.8is a flow chart of an example of a process800for synchronizing cycle accurate trace circuitry with tracing of vector instructions. The process800includes starting802synchronization between a trace encoder and cycle accurate trace circuitry; capturing804bits at checkpoints; storing806the captured bits in a trace buffer; determining808whether the vector instruction tracing is complete; and stopping810synchronization between the trace encoder and the cycle accurate trace circuitry. For example, the process800may be implemented using the system100shown inFIG.1, system200shown inFIG.2, and/or the system300shown inFIG.3.

The process800includes starting802synchronization between a trace encoder and cycle accurate trace circuitry, such as the trace encoder308and the cycle accurate trace circuitry304shown in inFIG.3. The trace encoder and the cycle accurate trace circuitry may synchronize with one another so that the trace encoder and the cycle accurate trace circuitry start and stop simultaneously with one another. In some implementations, the trace encoder and the cycle accurate trace circuitry may synchronize with one another and begin vector instruction tracing using a trace control system like the trace control system350shown inFIG.3.

In some implementations, a predetermined fence instruction may be used

to effectively flush the vector instruction queue. In some implementations, before starting the trace, the trace encoder may wait for a vector instruction queue of the vector unit to empty. For example, the trace encoder may receive an indication from the cycle accurate trace circuitry that the vector instruction queue is empty via a trace control interface. For example, the indication may be generated by checkpoints not setting bits (indicating arrival of vector instructions) for a number of clock cycles corresponding to a depth of the vector instruction queue. In some implementations, the trace encoder may permit a user to manually adjust the alignment of the start signal (“ON”) to vector instructions in the stream to start.

The process800also includes capturing804bits at checkpoints implemented in a scalar core and/or a vector unit implemented in silicon, such as checkpoints140A through140F shown inFIG.1or checkpoints240A through240F shown inFIG.2. The checkpoints may include a first checkpoint including circuitry that sets a first bit for a clock cycle in which a vector instruction exits a vector instruction queue, and a second checkpoint including circuitry that sets a second bit for a clock cycle in which a vector instruction exits a vector execution unit. Accordingly, the cycle accurate trace circuitry may capture bits associated with the arrival of specific vector instructions in the stream during the capture period.

The process800also includes storing806the captured bits in a cycle accurate trace buffer comprising data storage, such as the cycle accurate trace buffer106shown inFIG.1, the cycle accurate trace buffer206shown inFIG.2, or the cycle accurate trace buffer306shown inFIG.3. Further, an instruction trace may be captured by the trace encoder in an instruction trace buffer, such as the instruction trace buffer310shown inFIG.3. The bits in the cycle accurate trace buffer may be stored in predetermined positions for later decoding, such as bits in positions corresponding to an order of the checkpoints and an order of the clock cycles. Additionally, the bits may be stored at predetermined addresses in the trace buffer for later decoding, such as storing captured bits in a 32-bit word of bits at a first address, followed by a 32-bit word of bits at a second address following the first address, and so forth.

The process800also includes determining808whether the vector instruction tracing is complete. In some implementations, the trace encoder and/or the trace control system may determine whether the vector instruction tracing is complete based on the instructions being monitored in the instruction stream. For example, the trace encoder and/or the trace control system may recognize an instruction in the instruction stream, such as a predetermined fence instruction, as an event which triggers the synchronization to stop. In some implementations, the trace encoder and/or the trace control system may permit a user to manually adjust the alignment of the stop signal (“OFF”) to vector instructions in the stream. If vector instruction tracing is not complete (“NO”), the process800may return to capturing804bits at checkpoints. If vector instruction tracing is complete (“YES”), the process800may continue with stopping810synchronization between the trace encoder and the cycle accurate trace circuitry and ending the vector instruction tracing. For example, to simultaneously stop tracing (e.g., stop the capture period), the trace encoder may assert a stop signal (“OFF”) sent to the cycle accurate trace circuitry.

FIG.9is a flow chart of an example of a process900for compressing bits captured by cycle accurate trace circuitry to reduce storage in a trace buffer. The process900includes capturing902multiple bits at checkpoints; compressing904the captured bits; and storing906the compressed bits in a trace buffer. For example, the process900may be implemented using the system100shown inFIG.1, the system200shown inFIG.2, and/or the system300shown inFIG.3.

The process900includes capturing902multiple bits at checkpoints implemented in a scalar core and/or a vector unit implemented in silicon, such as checkpoints140A through140F shown inFIG.1or checkpoints240A through240F shown inFIG.2. The checkpoints may include a first checkpoint including circuitry that sets a first bit for a clock cycle in which a vector instruction exits a vector instruction queue, and a second checkpoint including circuitry that sets a second bit for a clock cycle in which a vector instruction exits a vector execution unit. The bits may be captured during multiple clock cycles of a capture period. The bits may be captured in synchronization with a trace encoder, such as the trace encoder308shown inFIG.3.

The process900also includes compressing904the captured bits to reduce bandwidth for routing the bits to a trace buffer and/or to reduce storage in a trace buffer, such as the cycle accurate trace buffer106shown inFIG.1, the cycle accurate trace buffer206shown inFIG.2, or the cycle accurate trace buffer306shown inFIG.3. For example, a compression algorithm may be applied to compress multiple 32-bit words (each including six bits, corresponding to checkpoints140A through140F, captured for five clock cycles) into a single 32-bit word stored in a trace buffer. The compressed 32-bit word may be decompressed to restore the positions of bits for correlating to vector instructions.

The process900also includes storing906the compressed bits in a trace buffer. The compressed bits may be stored at predetermined addresses in the trace buffer for later decoding, such as a 32-bit word of a first set of compressed bits stored at a first address, followed by a 32-bit word of a second set of compressed bits stored at a second address following the first address, and so forth. The compressed bits may advantageously consume less storage in the trace buffer than non-compressed bits.

FIG.10is a block diagram of an example of a system1000for generation and manufacture of integrated circuits. The system1000includes a network1006, an integrated circuit design service infrastructure1010(e.g., integrated circuit generator), a field programmable gate array (FPGA)/emulator server1020, and a manufacturer server1030. For example, a user may utilize a web client or a scripting application program interface (API) client to command the integrated circuit design service infrastructure1010to automatically generate an integrated circuit design based on a set of design parameter values selected by the user for one or more template integrated circuit designs. In some implementations, the integrated circuit design service infrastructure1010may be configured to generate an integrated circuit design that includes the circuitry shown and described inFIGS.1-3.

The integrated circuit design service infrastructure1010may include a register-transfer level (RTL) service module configured to generate an RTL data structure for the integrated circuit based on a design parameters data structure. For example, the RTL service module may be implemented as Scala code. For example, the RTL service module may be implemented using Chisel. For example, the RTL service module may be implemented using flexible intermediate representation for register-transfer level (FIRRTL) and/or a FIRRTL compiler. For example, the RTL service module may be implemented using Diplomacy. For example, the RTL service module may enable a well-designed chip to be automatically developed from a high level set of configuration settings using a mix of Diplomacy, Chisel, and FIRRTL. The RTL service module may take the design parameters data structure (e.g., a java script object notation (JSON) file) as input and output an RTL data structure (e.g., a Verilog file) for the chip.

In some implementations, the integrated circuit design service infrastructure1010may invoke (e.g., via network communications over the network1006) testing of the resulting design that is performed by the FPGA/emulation server1020that is running one or more FPGAs or other types of hardware or software emulators. For example, the integrated circuit design service infrastructure1010may invoke a test using a field programmable gate array, programmed based on a field programmable gate array emulation data structure, to obtain an emulation result. The field programmable gate array may be operating on the FPGA/emulation server1020, which may be a cloud server. Test results may be returned by the FPGA/emulation server1020to the integrated circuit design service infrastructure1010and relayed in a useful format to the user (e.g., via a web client or a scripting API client).

The integrated circuit design service infrastructure1010may also facilitate the manufacture of integrated circuits using the integrated circuit design in a manufacturing facility associated with the manufacturer server1030. In some implementations, a physical design specification (e.g., a graphic data system (GDS) file, such as a GDSII file) based on a physical design data structure for the integrated circuit is transmitted to the manufacturer server1030to invoke manufacturing of the integrated circuit (e.g., using manufacturing equipment of the associated manufacturer). For example, the manufacturer server1030may host a foundry tape-out website that is configured to receive physical design specifications (e.g., such as a GDSII file or an open artwork system interchange standard (OASIS) file) to schedule or otherwise facilitate fabrication of integrated circuits. In some implementations, the integrated circuit design service infrastructure1010supports multi-tenancy to allow multiple integrated circuit designs (e.g., from one or more users) to share fixed costs of manufacturing (e.g., reticle/mask generation, and/or shuttles wafer tests). For example, the integrated circuit design service infrastructure1010may use a fixed package (e.g., a quasi-standardized packaging) that is defined to reduce fixed costs and facilitate sharing of reticle/mask, wafer test, and other fixed manufacturing costs. For example, the physical design specification may include one or more physical designs from one or more respective physical design data structures in order to facilitate multi-tenancy manufacturing.

In response to the transmission of the physical design specification, the manufacturer associated with the manufacturer server1030may fabricate and/or test integrated circuits based on the integrated circuit design. For example, the associated manufacturer (e.g., a foundry) may perform optical proximity correction (OPC) and similar post-tape-out/pre-production processing, fabricate the integrated circuit(s)1032, update the integrated circuit design service infrastructure1010(e.g., via communications with a controller or a web application server) periodically or asynchronously on the status of the manufacturing process, perform appropriate testing (e.g., wafer testing), and send to a packaging house for packaging. A packaging house may receive the finished wafers or dice from the manufacturer and test materials and update the integrated circuit design service infrastructure1010on the status of the packaging and delivery process periodically or asynchronously. In some implementations, status updates may be relayed to the user when the user checks in using the web interface, and/or the controller might email the user that updates are available.

In some implementations, the resulting integrated circuit(s)1032(e.g., physical chips) are delivered (e.g., via mail) to a silicon testing service provider associated with a silicon testing server1040. In some implementations, the resulting integrated circuit(s)1032(e.g., physical chips) are installed in a system controlled by the silicon testing server1040(e.g., a cloud server), making them quickly accessible to be run and tested remotely using network communications to control the operation of the integrated circuit(s)1032. For example, a login to the silicon testing server1040controlling a manufactured integrated circuit(s)1032may be sent to the integrated circuit design service infrastructure1010and relayed to a user (e.g., via a web client). For example, the integrated circuit design service infrastructure1010may be used to control testing of one or more integrated circuit(s)1032.

Referring again toFIG.4, the system400may be used to facilitate generation of integrated circuits, to facilitate generation of a circuit representation for an integrated circuit, and/or for programming or manufacturing an integrated circuit. The system400may be used to implement the integrated circuit design service infrastructure1010, and/or to generate a file that generates a circuit representation of an integrated circuit design that includes the circuitry shown and described inFIGS.1-3.

A non-transitory computer readable medium may store a circuit representation that, when processed by a computer, is used to program or manufacture an integrated circuit. For example, the circuit representation may describe the integrated circuit specified using a computer readable syntax. The computer readable syntax may specify the structure or function of the integrated circuit or a combination thereof. In some implementations, the circuit representation may take the form of a hardware description language (HDL) program, a register-transfer level (RTL) data structure, a flexible intermediate representation for register-transfer level (FIRRTL) data structure, a Graphic Design System II (GDSII) data structure, a netlist, or a combination thereof. In some implementations, the integrated circuit may take the form of a field programmable gate array (FPGA), application specific integrated circuit (ASIC), system-on-a-chip (SoC), or some combination thereof. A computer may process the circuit representation in order to program or manufacture an integrated circuit, which may include programming a field programmable gate array (FPGA) or manufacturing an application specific integrated circuit (ASIC) or a system on a chip (SoC). In some implementations, the circuit representation may comprise a file that, when processed by a computer, may generate a new description of the integrated circuit. For example, the circuit representation could be written in a language such as Chisel, an HDL embedded in Scala, a statically typed general purpose programming language that supports both object-oriented programming and functional programming.

In an example, a circuit representation may be a Chisel language program which may be executed by the computer to produce a circuit representation expressed in a FIRRTL data structure. In some implementations, a design flow of processing steps may be utilized to process the circuit representation into one or more intermediate circuit representations followed by a final circuit representation which is then used to program or manufacture an integrated circuit. In one example, a circuit representation in the form of a Chisel program may be stored on a non-transitory computer readable medium and may be processed by a computer to produce a FIRRTL circuit representation. The FIRRTL circuit representation may be processed by a computer to produce an RTL circuit representation. The RTL circuit representation may be processed by the computer to produce a netlist circuit representation. The netlist circuit representation may be processed by the computer to produce a GDSII circuit representation. The GDSII circuit representation may be processed by the computer to produce the integrated circuit.

In another example, a circuit representation in the form of Verilog or VHDL may be stored on a non-transitory computer readable medium and may be processed by a computer to produce an RTL circuit representation. The RTL circuit representation may be processed by the computer to produce a netlist circuit representation. The netlist circuit representation may be processed by the computer to produce a GDSII circuit representation. The GDSII circuit representation may be processed by the computer to produce the integrated circuit. The foregoing steps may be executed by the same computer, different computers, or some combination thereof, depending on the implementation.

In a first aspect, the subject matter described in this specification can be embodied in an apparatus that includes a scalar core; a vector unit in communication with the scalar core, the vector unit including a vector instruction queue that receives vector instructions from the scalar core, the vector unit further including a vector execution unit that executes vector instructions from the vector instruction queue; and a plurality of checkpoints in the vector unit including a first checkpoint including circuitry that sets a first bit for a first clock cycle in which a first vector instruction exits the vector instruction queue, and a second checkpoint including circuitry that sets a second bit for a second clock cycle in which a second vector instruction exits the vector execution unit. In some implementations, the apparatus includes a third checkpoint in the scalar core, wherein the third checkpoint includes circuitry that sets a third bit for a third clock cycle in which a third vector instruction dispatches to the vector unit. In some implementations, the apparatus includes checkpoints in the scalar core including a third checkpoint including circuitry that sets a third bit for a third clock cycle in which a third vector instruction dispatches to the vector unit, and a fourth checkpoint including circuitry that sets a fourth bit for the third clock cycle in which a fourth vector instruction dispatches to the vector unit. In some implementations, the first clock cycle and the second clock cycle correspond to a same clock cycle. In some implementations, the first vector instruction and the second vector instruction correspond to a same vector instruction. In some implementations, the apparatus includes a trace buffer that stores a plurality of bits corresponding to a clock cycle, the plurality of bits including a first bit captured at the first checkpoint and a second bit captured at the second checkpoint. In some implementations, the plurality of bits is compressed when stored in a trace buffer. In some implementations, the vector execution unit is a first vector execution unit that is a load unit, and further comprising a second vector execution unit that is a store unit, and wherein the second checkpoint includes circuitry that sets the second bit for the second clock cycle in which the second vector instruction exits the load unit or the store unit. In some implementations, the apparatus includes a third vector execution unit that is an arithmetic unit and a third checkpoint including circuitry that sets a third bit for a third clock cycle in which a third vector instruction exits the arithmetic unit.

In a second aspect, the subject matter described in this specification can be embodied in a method that includes capturing a plurality of bits at checkpoints implemented in a vector unit in communication with a scalar core, the vector unit including a vector instruction queue that receives vector instructions from the scalar core, the vector unit further including a vector execution unit that executes vector instructions from the vector instruction queue, the checkpoints including a first checkpoint including circuitry that sets a first bit for a first clock cycle in which a first vector instruction exits the vector instruction queue, and a second checkpoint including circuitry that sets a second bit for a second clock cycle in which a second vector instruction exits the vector execution unit. In some implementations, capturing the plurality of bits includes capturing a bit at a checkpoint implemented in the scalar core, wherein the checkpoints include a third checkpoint including circuitry that sets a third bit for a third clock cycle in which a third vector instruction dispatches to the vector unit. In some implementations, capturing the plurality of bits includes capturing bits at checkpoints implemented in the scalar core, wherein the checkpoints include a third checkpoint including circuitry that sets a third bit for a third clock cycle in which a third vector instruction dispatches to the vector unit, and a fourth checkpoint including circuitry that sets a fourth bit for the third clock cycle in which a fourth vector instruction dispatches to the vector unit. In some implementations, the method includes storing the plurality of bits in a trace buffer, wherein the plurality of bits corresponds to a same clock cycle. In some implementations, the method includes compressing the plurality of bits stored in the trace buffer. In some implementations, the method includes executing a trace encoder to associate a vector instruction obtained from a scalar core with a bit obtained from a checkpoint. In some implementations, the method includes outputting to a display a trace of the vector instruction, wherein the trace indicates a number of clock cycles between the first checkpoint and the second checkpoint.

In a third aspect, the subject matter described in this specification can be embodied, at least in part, in a non-transitory computer-readable storage medium that includes instructions that, when executed by a processor, causes the processor to associate a vector instruction obtained from a scalar core with a bit obtained from a checkpoint implemented in a vector unit in communication with a scalar core, wherein the vector unit includes a vector instruction queue that receives vector instructions from the scalar core, wherein the vector unit further includes a vector execution unit that executes vector instructions from the vector instruction queue, and wherein the checkpoints include a first checkpoint including circuitry that sets a first bit for a first clock cycle in which a first vector instruction exits the vector instruction queue, and a second checkpoint including circuitry that sets a second bit for a second clock cycle in which a second vector instruction exits the vector execution unit. In some implementations, the non-transitory computer-readable storage medium includes instructions that, when executed by the processor, causes the processor to associate the vector instruction with a bit obtained from a checkpoint implemented in the scalar core, wherein the checkpoints include a third checkpoint including circuitry that sets a second bit for a third clock cycle in which a third vector instruction dispatches to the vector unit. In some implementations, the non-transitory computer-readable storage medium includes instructions that, when executed by the processor, causes the processor to compress the bit with a plurality of bits stored in a trace buffer. In some implementations, the non-transitory computer-readable storage medium includes instructions that, when executed by the processor, causes the processor to display a trace of the vector instruction, wherein the trace indicates a number of clock cycles between the first checkpoint and the second checkpoint.