Synchronizing circuit provided with hysteresis phase comparator

A synchronizing circuit includes a phase comparator having hysteresis characteristics and a dead zone, and configured to generate a frequency division ratio control signal based on a phase difference between a first clock and a second clock. The circuit further includes a variable frequency divider configured to generate a fourth clock by subjecting a third clock to frequency division at a frequency division ratio set in accordance with the frequency division ratio control signal, and a clock generator configured to subject the fourth clock supplied from the variable frequency divider to frequency division at a predetermined frequency division ratio, and generate the second clock such that the second clock synchronizes with transfer data which is supplied from an outside of the synchronizing circuit.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-374709, filed Dec. 25, 2002, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a synchronizing circuit including a hysteresis phase comparator, more particularly, a PLL (Phase Locked Loop) circuit for generating a clock signal adapted for a system provided with a CODEC (Coder & Decoder) for a voice signal or an audio signal.

2. Description of the Related Art

When data is transmitted with a digital signal from a transmitting side to a receiving side, it is required that the data is correctly received by the receiving side, i.e., the data does not lack a data piece, or it does not contain duplicate data pieces. Furthermore, in a system wherein the received data is finally converted into an analog signal, it is also needed to sufficiently reduce the jitter of a clock on the receiving side which synchronizes with the received data. This need further increases, especially for a system incorporating an audio CODEC or a voice CODEC which handles a voice signal or an audio signal. This is because such a system uses the clock on the receiving side as a sampling clock for an AD converter (ADC) or a DA converter (DAC). That is, when jitter occurs in the clock of the receiving side, the S/N ratio (signal-to-noise ratio) of the ADC or DAC lowers. In general, it is required that the jitter of a clock to be obtained is reduced as the resolution of the ADC or DAC increases.

FIG. 8shows an example of the structure of a conventional system including a CODEC. The conventional system comprises a signal processing section10and a CODEC section20. The signal processing section10processes a digital signal, etc. The CODEC section20has a function of converting an analog input signal into a digital signal (first transfer data) and a function of converting a digital signal (second transfer data) output from the signal processing section10into an analog output signal. Such a system is used in transmission and reception of voice, etc. by a mobile telephone.

As shown inFIG. 8, the second transfer data is transferred from the signal processing section10to the CODEC section20, and the first transfer data is transferred from the CODEC section20to the signal processing section10. Also, a transfer clock (reference signal) which synchronizes with the first and second transfer data is supplied from the signal processing section10to the CODEC section20.

The CODEC section20comprises an I/F (interface) section21, a CODEC22and an analog PLL23. The analog PLL23fetches the transfer clock from the signal processing section10. The analog PLL23generates an I/F clock synchronizing with the transfer clock, and outputs the I/F clock to the I/F section21. Further, the analog PLL23generates a sampling clock having a frequency which is a rational number of times greater than that of the transfer clock, and outputs the sampling clock to the CODEC22.

The I/F section21receives the second transfer data from the signal processing section10, while synchronizing the second transfer data with the I/F clock from the analog PLL23. Then, the I/F section21generates a reception signal (digital signal) in accordance with the second transfer data, and outputs the reception signal to the CODEC22. Further, the I/F section21receives transmission data (digital signal) from the CODEC22, while synchronizing the transmission data with the I/F clock from the analog PLL23. The I/F section21then generates the first transfer data in accordance with the transmitted data, and outputs the first transfer data to the signal processing section10.

The CODEC22comprises a digital signal processing circuit and an ADC and DAC. The CODEC22converts the reception data from the I/F section21into an analog output signal by using the sampling clock from the analog PLL23.

In such a manner, in the conventional system shown inFIG. 8, A/D conversion is performed by the ADC, or D/A conversion is performed by the DAC, in addition to transmission and reception of data, based on the I/F clock and sampling clock which are generated by the analog PLL23. Therefore, the characteristics of the analog PLL23greatly influence those of the system.

FIG. 9shows an example of the structure of the analog PLL23shown inFIG. 8. The analog PLL23comprises a phase comparator23a, a loop filter23b, a VCO (Voltage Controlled Oscillator)23cand a frequency divider23d. The phase comparator23agenerates a signal in accordance with the phase difference between the I/F clock and the transfer clock from the signal processing section10, and then supplies the signal to the loop filter23b. The loop filter23bsmoothens the signal supplied from the phase comparator23a, and then supplies the signal to the VCO23c. The VCO23cgenerates a signal having a frequency which is determined in accordance with the signal supplied from the loop filter23b. The signal generated by the VCO23cis subjected to frequency division by the frequency divider23d(i.e., its frequency is divided by the frequency divider23d). The signal subjected to frequency division is then supplied as the I/F clock to the I/F section21and the phase comparator23a. In such a manner, regularly, the analog PLL23operates to equalize the transfer clock and the I/F clock, and also to make the phase difference therebetween constant.

FIG. 10shows another example of the structure of the conventional system including the CODEC. In this example, the system has the same elements as the system shown inFIG. 8, with the exception of the following: the analog PLL23is replaced by a digital PLL23A to which a master clock (MCLK) is input (see, e.g., Troha, James, D. “Digital Phase-Locked Loop Design using SN54/74LS297”, Texas Instruments Application Note, http://www-s.ti.com/sc/psheets/sdla005b/sdla005b.pdf, 1997, which discloses an example of the digital PLL).

The MCLK is a clock signal generated within a CODEC section20′ or a clock signal supplied from the outside of the CODEC section20′. The frequency of the MCLK is an integer number of times greater than the average frequency of the I/F clock.

FIG. 11shows an example of the structure of the digital PLL23A shown inFIG. 10. The digital PLL23A comprises a phase comparator23a, a frequency divider23d, a digital loop filter23eand a variable frequency divider23f. In the digital PLL23A, the digital loop filter23eand the variable frequency divider23fare used, instead of the loop filter23band VOC23cof the analog PLL23, respectively. To be more specific, the digital loop filter23eis a digital filter which operates in accordance with the MCLK. The digital loop filter23esmoothens the output signal of the phase comparator23aby using the MCLK, and then supplies the signal to the variable frequency divider23f. The digital loop filter23ecorresponds to the loop filter23bof the analog PLL23. The variable frequency divider23fis a frequency divider the frequency division ratio of which varies in accordance with the output signal of the digital loop filter23e. More specifically, the variable frequency divider23fdivides the frequency of the MCLK at the frequency division ratio which is controlled by the digital loop filter23e, and generates a sampling clock. The variable frequency divider23fthen outputs the sampling clock to the frequency divider23dand the CODEC22. The variable frequency divider23fcorresponds to the VCO23cof the analog PLL23. As can be seen from the above, the digital PLL23A is substantially equivalent to the analog PLL23.

As explained above, with respect to the system provided with the CODEC, the system using the digital PLL23A is substantially equivalent to that using the analog PLL23. Accordingly, with respect to those systems, the following explanation is given by referring to only the system using the analog PLL23shown inFIG. 8and the analog PLL23inFIG. 9. Needless to say, even if they are replaced by the system using the digital PLL23A shown inFIG. 10and the digital PLL23A inFIG. 11, the same explanation can be applied.

FIGS. 12A to 12Dshow examples of the waveforms of signals used in the system shown inFIG. 8. To be more specific,FIGS. 12A,12B,12C and12D disclose the transfer clock, the second transfer data, the I/F clock and the reception data, respectively. The signal level of the second transfer data varies in synchronism with the rising edge of the transfer clock. The rising edge of the I/F clock is synchronized with the falling edge of the transfer clock by the analog PLL23. It is shown in the above figures that the period from time t3to time t4of the transfer clock is longer than any of the other periods thereof. The I/F clock varies while following the transfer clock in period, and the period from time t3ito t4iof the I/F clock is longer than any of the other periods thereof. In such a manner, the system inFIG. 8generates an I/F clock, which varies while following variation of the transfer clock with respect to period, by using the analog PLL23, thereby achieving reliable data transfer.

As explained above, in the system inFIG. 8, the periods of the I/F clock are not constant. This means that the transfer clock has jitter, and the I/F clock thus also has jitter. This means that jitter also occurs in a sampling clock having a frequency which is a rational number of times greater than that of the transfer clock. Accordingly, as stated above, the S/N ratio of the ADC or DAC of the CODEC22lowers.

FIG. 13shows a relationship between the phase difference between two signals (the transfer clock and I/F clock) input to the phase comparator23aof the analog PLL23(which is referred to as an input signal phase difference in the figure) and the variation of the frequency of the output signal from the analog PLL23(which is referred to as an output frequency variation in the figure). As shown inFIG. 13, the analog PLL23is designed such that the output signal frequency increases in a monotonically increasing manner as the phase difference between the signals input to the phase comparator23aincreases. If the frequency of the output signal does not vary when the phase difference between the input signals is within a certain range, the range is referred to as a dead zone. Referring toFIG. 13, when the variation of the frequency of the output signal is “0”, the phase difference between the input signals is also “0”. However, generally, the above phenomenon is not limited to the case where the phase difference is “0” when the frequency variation is “0”. That is, generally, in this case the phase difference is not necessarily “0”, and it is constant.

As is clear fromFIG. 13, one of the features of a conventional PLL circuit resides in that the greater the phase difference between the input signals, the greater the variation of the frequency of the output signal. When this is explained with respect to the system inFIG. 8, it can be said that the frequency variation of each of the I/F clock and the sampling clock increases as the variation of the phase of the transfer clock increases. In other words, jitter occurs in the I/F clock and the sampling clock when the level of the jitter of the transfer clock increases. That is, it can be considered that use of the conventional analog PLL23easily causes lowering of the S/N ratio of the CODEC22.

The total characteristics of the analog PLL23also depend on transient response characteristics thereof.FIGS. 14 and 15show examples of the transient response characteristics when the output frequency of the analog PLL23changes from f1to f2.FIG. 14shows a case where a lock-up time is short, but relatively large overshoot and undershoot (ringing) occur.FIG. 15shows a case where the overshoot is small, but the lock-up time is long. Also, it should be noted that suppose the lock-up time is a time period required until the output frequency falls within an allowable error range as shown in, e.g.,FIGS. 14 and 15. It is known that the total characteristics of the analog PLL23depend on conversion characteristics of the phase comparator23a, characteristics of the oscillation frequency of the VCO23cto a control signal and characteristics of the loop filter23.

Generally, as shown inFIGS. 14 and 15, when the lock-up time is short, overshoot or undershoot easily occurs. On the other hand, when the overshoot or undershoot is small, the lock-up time tends to be long.

FIGS. 16A to 16Cshow examples of the frequency variation of the transfer clock, and examples of the frequency variation of the I/F clock to that of the transfer clock.FIG. 16Ais an example of the frequency variation of the transfer clock. “EXAMPLE 1 OF FREQUENCY VARIATION OF I/F CLOCK” inFIG. 16Bis an example of the case where an analog PLL having such transient response characteristics as shown inFIG. 14is used as the analog PLL23. “EXAMPLE 2 OF FREQUENCY VARIATION OF I/F CLOCK” inFIG. 16Cis an example of the case where an analog PLL having such transient response characteristics as shown inFIG. 15is used as the analog PLL23.

In “EXAMPLE 2 OF FREQUENCY VARIATION OF I/F CLOCK” inFIG. 16C, the frequency does not steeply or minutely vary, and the frequency variation is relatively smooth, as compared with “EXAMPLE 1 OF FREQUENCY VARIATION OF I/F CLOCK” inFIG. 16B. However, EXAMPLE 1 and EXAMPLE 2 have both the same problem. That is, in EXAMPLE 1 and EXAMPLE 2, the frequency of the I/F clock varies while following variation of the frequency of the transfer clock.

In the system inFIG. 8, it is preferable that the lock-up time be short, in order to ensure reliable data transfer. Thus, as the analog PLL23, the analog PLL having such transient response characteristics as shown inFIG. 14is more suitable than the analog PLL having such transient response characteristics as shown inFIG. 15. However, when the analog PLL having transient response characteristics shown inFIG. 14is used as the analog PLL23, the output frequency easily shows minute variation due to overshoot and undershoot as shown inFIG. 16B. Even if the frequency of the transfer clock varies by such a slight amount as not to affect the data transfer, the frequency of the analog output signal varies inevitably.

In such a manner, there is a case where as the function (characteristics) of the PLL circuit varies, the jitter increases, and the S/N ratio of the CODEC further lowers.

As explained above, in the above conventional method, the I/F clock reliably follows the transfer track, thus achieving reliable data transfer. However, when the conventional method is applied to a system provided with a voice CODEC or an audio CODEC, the S/N ratio lowers.

It should be noted that there is a method which can satisfy both the above two requirements in which reliable data transfer is achieved, and the S/N ratio is not lowered. However, if the method is applied, the circuit is complicated, as compared with the case where the above conventional method is applied. It is thus also inappropriate.

Namely, it is required to reduce the size of the circuit and the power consumption as much as possible, and provide a system which satisfies the above requirements and can be easily achieved.

BRIEF SUMMARY OF THE INVENTION

According to a first aspect of the present invention, there is provided a synchronizing circuit which comprising: a phase comparator having hysteresis characteristics and a dead zone, and configured to generate a frequency division ratio control signal based on a phase difference between a first clock and a second clock; a variable frequency divider configured to generate a fourth clock by subjecting a third clock to frequency division at a frequency division ratio set in accordance with the frequency division ratio control signal; and a clock generator configured to subject the fourth clock supplied from the variable frequency divider to frequency division at a predetermined frequency division ratio, and generate the second clock such that the second clock synchronizes with transfer data which is supplied from an outside of the synchronizing circuit.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1shows an example of the structure of a synchronizing circuit according to the embodiment of the present invention. The following explanation is given with respect to a case where in a digital PLL (see, e.g.,FIG. 9) which is to be applied to the system shown inFIG. 8which includes the CODEC, the phase comparator is replaced by a hysteresis phase comparator which has hysteresis characteristics and a relatively large dead zone.

As shown inFIG. 1, according to the embodiment of the present invention, a digital PLL24comprises a hysteresis comparator24a, a frequency divider (clock generator)24band a variable frequency divider24c. The digital PLL24receives a MCLK (third clock) and a transfer clock (first clock), and outputs an I/F clock (second clock) and a sampling clock (fourth clock). The hysteresis comparator24areceives the transfer clock, the I/F clock and the MCLK, and outputs a frequency division ratio control signal based on the phase difference between the transfer clock and the I/F clock. The variable frequency divider24creceives the MCLK and the frequency division ratio control signal, and performs frequency division on the MCLK (i.e., divides the frequency of the MCLK) in accordance with the frequency division ratio set based on the frequency division ratio control signal. Then, The variable frequency divider24coutputs a sampling clock obtained by dividing the frequency of the MCLK. The frequency divider24bdivides the frequency of the sampling clock in accordance with its frequency division ratio, and outputs an I/F clock obtained by dividing the frequency of the sampling clock.

FIG. 2shows an example of the structure of the hysteresis phase comparator24a. The hysteresis phase comparator24acomprises a counter24a—1, a comparator24a—2and a hysteresis circuit24a—3. The counter24a—1is a circuit for executing a counting operation, and detecting the phase difference between the transfer clock and the I/F clock. For example, the counter24a—1starts the counting operation in response to the rising edge (start signal) of the transfer clock, and stops the counting operation in response to the rising edge (stop signal) of the I/F clock. The count value of the counter24a—1is input to the comparator24a—2. The comparator24a—2compares the count value from the counter24a—1with phase difference judgment region reference values. A result obtained by the above comparison is input to the hysteresis circuit24a—3. The hysteresis circuit24a—3generates a control signal based on past operation hysteresis (which will be explained later) on the basis of the result of the comparison by the comparator24a—2. The hysteresis circuit24a—3outputs the control signal to the outside (i.e., to the variable frequency divider24c).

FIGS. 3A to 3Eare views for use in explaining the operation of the hysteresis phase comparator24a.FIGS. 3A,3B,3C,3D and3E show the transfer clock, second transfer data, MCLK, phase difference judgment region and phase difference judgment region reference value, respectively.

A period of the transfer clock, e.g., a rising edge period (from phase difference judgment region reference value “0” to phase difference judgment region reference value “12”), is divided into five periods. To the boundaries between the five periods, phase difference judgment region reference values (“2”, “5”, “7” and “10” in this case) are respectively assigned, which are obtained by standardizing the rising edge period in accordance with the periods of the MCLK. These reference values may be values which are fixed in accordance with the structure of the circuit, or values which are variable by a control signal or the like. In addition, the phase difference judgment region reference values shown inFIG. 3Eare examples. That is, they can be set to desired values.

By using the phase difference judgment region reference values, four phase difference judgment regions, i.e., a normal operation region (N), a phase shift start judgment region (F), a phase shift start judgment region (R) and a phase shift end judgment region (E), are defined as shown inFIG. 3D.

As explained above, when the counter24a—1determines a count value corresponding to the phase difference between the transfer clock and the I/F clock, the comparator24a—2compares the count value with each of the phase difference judgment region reference values with respect to whether the count value is greater or smaller than each phase difference judgment region reference value. Based on the result of this comparison, a phase difference judgment region in which the rising edge (or falling edge) of the I/F clock is located is detected. When passing through the hysteresis circuit24a—3, the output of the comparator24a—2is changed to a frequency division ratio control signal. The frequency division ratio control signal is output from the hysteresis comparator24ato the variable frequency divider24c.

The operation of the hysteresis operation of the digital PLL24according to the above embodiment will be explained by referring to the case of generating a control signal based on past operation hysteresis.

First of all, suppose that in the initial state, the rising edge (or falling edge) of the I/F clock is within the “normal operation region (N)” (see, e.g.,FIGS. 4A to 4F). In this case, the hysteresis phase comparator24aoutputs a frequency division ratio control signal indicating “no phase shift”. Thereby, in the variable frequency divider24c, the frequency division ratio is set to “n”. That is, the frequency (first frequency) of the sampling clock is 1/n of the MCLK. In this state, a PLL control is not applied. It corresponds to a state generally referred to as “VCO free-run”.

Next, if the rising edge (or falling edge) of the I/F clock is located within the “phase shift start judgment region (F)” due to variation of the periods of the transfer clock or the like (see, e.g.,FIGS. 5A to 5F), a frequency division control signal indicating “plus phase shift” is output from the hysteresis comparator24a. Thereby, the frequency division ratio of the variable frequency divider24cis set to “n+α (α>0)”. That is, the frequency of the sampling clock (the second frequency lower than the first frequency by the fourth frequency) is 1/(n+α) of the frequency of the MCLK. As a result, the period of the I/F clock is multiplied by (n+α)/n. Thereby, the phase of the I/F clock is shifted such that the rising edge (or falling edge) gradually increasingly lags with respect to the rising edge (or falling edge) of the transfer clock.

On the other hand, when the rising edge (or falling edge) of the I/F clock is within the range of the “phase shift start judgment region (R)”, a frequency division ratio control signal indicating “negative phase shift” is output from the hysteresis phase comparator24a. Thereby, the frequency division ratio of the variable frequency divider24cis set to “n−β(β>0)”. That is, the frequency (the third frequency higher than the first frequency by the fifth frequency) of the sampling clock is 1/(n−β) of the frequency of the MCLK. As a result, the period of the I/F clock is multiplied by (n−β)/n. Thereby, the phase of the I/F clock is shifted such that the rising edge (or falling edge) gradually increasingly leads with respect to the rising edge (or falling edge) of the transfer clock.

Suppose the hysteresis phase comparator24aonce outputs a frequency division ratio control signal indicating “positive phase shift” or “negative phase shift”. In this case, the hysteresis phase comparator24acontinues to output the above-frequency division ratio control signal until the rising edge (or falling edge) of the I/F clock falls within the “phase shift end judgment region (E)”. In such a manner, the hysteresis phase comparator24ais provided to have hysteresis characteristics and a dead zone indicated by the “normal operation region (N)”.

The above frequency division ratio control signal indicating “no phase shift”, “positive phase shift” or “negative phase shift” can be implemented with a two-bit digital signal. When the two-bit digital signal is applied to produce the frequency division ratio control signal, it can indicate “no phase shift”, “positive phase shift” and “negative phase shift” with, e.g., “00”, “01” and “10”, respectively. In such a manner, the two-bit digital signal can serve as the frequency division ratio control signal. Needless to say, the frequency division ratio control signal is not limited to a two-bit digital signal. That is, any kind of signal may be used as the frequency division ratio control signal as long as it can distinguishably indicate the above three states. Also, the values of n, α and β may be values fixed in accordance with the structure of the circuit or values variable by a control signal or the like. However, the values of α and β are set such that the phase shift is greater than the maximum value of cycle to cycle jitter of the transfer clock.

FIG. 6discloses a relationship between the phase difference between the signals (transfer clock and I/F clock) input to the hysteresis phase comparator24ain the digital PLL24according to the above embodiment of the present invention, and the variation of the frequency of the signal output from the digital PLL24. This relationship corresponds to that inFIG. 13(showing the prior art). As is clear from those figures, the hysteresis phase comparator24ais greatly different from that inFIG. 13, and has hysteresis characteristics, and provide a wide dead zone.

FIGS. 7A and 7Bshow an example of the frequency variation of the transfer clock and an example of the frequency variation of the I/F clock with respect to the frequency variation of the transfer clock, respectively, in the digital PLL24according to the embodiment of the present invention. As is clear from those figures, even if the frequency of the transfer clock varies, that of the I/F clock does not vary as long as the rising edge (or falling edge) of the I/F clock is within the “normal operation region (N)”. When the frequency of the transfer clock greatly varies, the rising edge (or falling edge) of the I/F clock falls within the “phase shift start judgment region (F) (or (R))”, and the phase of the I/F clock starts to shift. Then, the rising edge (or falling edge) of the I/F clock immediately shifts to exit the “phase shift start judgment region (F) (or (R))”. However, until the rising edge (or falling edge) of the I/F clock falls within the “phase shift end judgment region (E)”, the phase of the I/F clock continuously shifts, and thus the phase difference between the transfer clock and the I/F clock continuously varies. However, in this case, the frequency of the I/F clock is constant, since the frequency division ratio of the variable frequency divider24cis constant. Then, when the rising edge (or falling edge) of the I/F clock falls within the “phase shift end judgment region (E)”, the frequency of the I/F clock returns to that in a state “no phase shift”.

When the phase shifts, the frequency division ratio of the variable frequency divider24cvaries only by a certain value (α, β). Thus, at this time, the frequency is also a certain value (fmclk/(n+α), fmclk/(n−β), where fmclk is the frequency of the MCLK. Therefore, while the phase is shifting, the frequencies of the I/F clock and sampling clock do not vary in accordance with the phase difference between the transfer clock and the I/F clock, unlike the conventional PLL circuit. Accordingly, the S/N ratio of the CODEC does not lower.

Further, the phase shift is set to be greater than the maximum value of the cycle to cycle jitter of the transfer clock. Thereby, while the phase is shifting, the rising edge (or falling edge) of the I/F clock necessarily shifts toward the “phase shift end judgment region (E)”. Thus, the method according to the embodiment of the present invention can produce an I/F clock which reliably synchronizes with the second transfer data.

Furthermore, since the hysteresis phase comparator24ahas hysteresis characteristics, the dead zone can be set to be wide. In addition, the phase can also be continuously shifted until the time margin can be sufficiently ensured. Thus, once phase shifting ends, the time period required until phase shifting is needed again is long, and the number of times the phase shifts (the frequency variation) decreases, as compared with the conventional method employing a comparator which does not have hysteresis characteristics. This means that the jitter is small. That is, the method of the present invention can generate a clock signal in which the average value of jitter is smaller than that in the conventional method. As a result, the S/N ratio can be improved. Accordingly, the present invention is useful, especially for a system incorporating a CODEC for voice or audio.

Moreover, the digital PLL24according to the embodiment of the present invention can be implemented with a relatively simple logic circuit. Also, it can be easily designed.

The method for achieving the structure of the circuit (or the structure of the circuit) is not limited to that of the above embodiment shown inFIGS. 1 and 2, i.e., any method (any structure) may be applied as long as the same function can be achieved as in the embodiment of the present invention.

The above explanation of the embodiment of the present invention refers to the case where the invention is applied to the digital PLL. However, needless to say, the invention may be applied to the analog PLL.

For example, the counter24a—1may be formed to start the counting operation in response to the falling edge (start signal) of the transfer clock, and stop the counting operation in response to the falling edge (stop signal) of the I/F clock. Also, it may be formed to output, to the comparator24a—2, a signal indicating the difference between a count value obtained at the timing of the rising edge (or falling edge) of the transfer clock and a count value obtained at the timing of the rising edge (or falling edge) of the I/F clock.