Nonvolatile semiconductor memory device and method for manufacturing same

According to one embodiment, a nonvolatile semiconductor memory device includes: a first stacked body having a gate insulating film, a first charge storage layer, a first insulating film, a second charge storage layer, and a second insulating film, a second element isolation region, a bottom and at least part of a side portion of the second element isolation region being in contact with the semiconductor substrate in the peripheral portion; and a second stacked body, a third insulating film, a first layer, a fourth insulating film, a second layer, and the second insulating film are stacked in this order from the semiconductor substrate side between the semiconductor substrate and the control gate electrode in the second stacked body in the peripheral portion, a side portion of the second stacked body being covered with the second insulating film.

FIELD

Embodiments described herein relate generally to a nonvolatile semiconductor memory device and a method for manufacturing the same.

BACKGROUND

In the manufacturing process of a nonvolatile semiconductor memory device, the chemical mechanical polishing (CMP) method may be used in order to form an element isolation region. There are element isolation regions with a wide width and a narrow width. If an element isolation region with a particularly wide width is processed by CMP, an erosion effect in which the surface of the element isolation region is recessed may occur. The erosion effect may influence other layers formed at a periphery of the element isolation region.

DETAILED DESCRIPTION

In general, according to one embodiment, a nonvolatile semiconductor memory device includes: a semiconductor substrate provided in a memory cell portion and in a peripheral portion at a periphery of the memory cell portion; a control gate electrode provided on an upper side of the semiconductor substrate and the control gate electrode extending in a first direction; a first element isolation region, a bottom and part of a side portion of the first element isolation region being in contact with the semiconductor substrate, the first element isolation region extending in a second direction crossing the first direction, and the first element isolation region separating a surface layer of the semiconductor substrate into a plurality of semiconductor regions in the memory cell portion; a first stacked body, a gate insulating film, a first charge storage layer, a first insulating film, a second charge storage layer, and a second insulating film are stacked in this order from the semiconductor region side in the first stacked body, the first stacked body being positioned in a position, each of the plurality of semiconductor regions and the control gate electrode cross each other in the position in the memory cell portion; a second element isolation region, a bottom and at least part of a side portion of the second element isolation region being in contact with the semiconductor substrate in the peripheral portion; and a second stacked body, a third insulating film, a first layer, a fourth insulating film, a second layer, and the second insulating film are stacked in this order from the semiconductor substrate side between the semiconductor substrate and the control gate electrode in the second stacked body in the peripheral portion, a side portion of the second stacked body being covered with the second insulating film.

Hereinbelow, embodiments are described with reference to the drawings. In the following description, identical components are marked with the same reference numerals, and a description of components once described is omitted as appropriate.

First Embodiment

FIG. 1is a schematic cross-sectional view of a nonvolatile semiconductor memory device according to the embodiment.

The right side ofFIG. 1illustrates a memory cell portion100, and the left side illustrates a peripheral portion200provided at a periphery of the memory cell portion100.

A nonvolatile semiconductor memory device1according to the embodiment includes the memory cell portion100including NAND memory cells and the peripheral portion200provided at a periphery of the memory cell portion100.

In the nonvolatile semiconductor memory device1, a semiconductor substrate10is provided in the memory cell portion100and the peripheral portion200. A control gate electrode60extending in the X-direction (a first direction) is provided on the upper side of the semiconductor substrate10and on the upper side of an element isolation region51. The control gate electrode60functions as a gate electrode for controlling a transistor. The control gate electrode60may be referred to as a word line (WL).

In the memory cell portion100, element isolation regions50separating the surface layer of the semiconductor substrate10into a plurality of semiconductor regions11are provided. The semiconductor region11is an active area that the transistor of the nonvolatile semiconductor memory device1occupies. The bottom50bof the element isolation region50and part of the side portion50wthereof are in contact with the semiconductor substrate10. The element isolation region50extends in the Y-direction (a second direction) crossing (for example, orthogonal to) the X-direction.

In the memory cell portion100, in a position where each of the plurality of semiconductor regions11and the control gate electrode60cross each other, a gate insulating film20A, a charge storage layer30A (a first charge storage layer), an IFD (inter-floating gate dielectric) film35A (a first insulating film), a charge storage layer36A (a second charge storage layer) as a CT (charge trap) film or the like, and an insulating film37(a second insulating film) are stacked in this order from the semiconductor region11side. This stacked body15A (a first stacked body) in the memory cell portion100may be referred to as a memory cell.

The gate insulating film20A in the memory cell functions as a tunnel insulating film that allows a charge (e.g. electrons) to tunnel between the semiconductor region11and the charge storage layer30A. The charge storage layer30A can store a charge that has tunneled from the semiconductor region11via the gate insulating film20A. The charge storage layer36A can store a charge that has tunneled from the charge storage layer30A via the IFD film35A. The IFD film35A functions as a tunnel insulating film that allows a charge (e.g. electrons) to tunnel between the charge storage layer30A and the charge storage layer36A and as a reaction prevention film of the charge storage layer30A and the charge storage layer36A.

In the peripheral portion200, an element isolation region51is provided in the semiconductor substrate10. The bottom51bof the element isolation region51and at least part of the side portion51ware in contact with the semiconductor substrate10. The element isolation region51is an element isolation region for partitioning the memory cell portion100from a peripheral circuit, for example.

In the peripheral portion200, a stacked body15B (a second stacked body) in which an insulating film20B (a third insulating film), a layer30B, an insulating film35B (a fourth insulating film), a layer36B, and the insulating film37are stacked in this order from the semiconductor substrate10side is provided between the semiconductor substrate10and the control gate electrode60. Here, the material of the insulating film20B is the same as the material of the gate insulating film20A. The material of the layer30B is the same as the material of the charge storage layer30A. The material of the insulating film35B is the same as the material of the IFD film35A. The material of the layer36B is the same as the material of the charge storage layer36A.

Each of the insulating film20B, the layer30B, the insulating film35B, and the layer36B in the stacked body15B is not in contact with the element isolation region51.

In the peripheral portion200, the insulating film37extends up to the side portion15Bw of the stacked body15B and the surface10uof the semiconductor substrate10between the stacked body15B and the element isolation region51. The insulating film37is in contact with the element isolation region51.

In the memory cell portion100and the peripheral portion200, a block insulating film40(a fifth insulating film) is provided between the insulating film37and the element isolation region51, and the control gate electrode60. An insulating film70as a cap film is provided on the control gate electrode60.

The material of the semiconductor substrate10(or the semiconductor region11) is a semiconductor crystal doped with an impurity, for example. Silicon (Si) is given as the semiconductor, for example.

The material of the gate insulating film20A is silicon oxide (SiOx), silicon oxynitride (SiONx), silicon nitride (SiNx), or the like, for example.

The material of the charge storage layer30A may be a semiconductor material such as Si and a Si-based compound, a material other than this (e.g. a metal or an insulating film), or a stacked film of these, for example. For example, the material of the charge storage layer30A is a semiconductor containing an n-type (second conductivity type) impurity, a metal, a metal compound, or the like. As the material, for example, amorphous silicon (a-Si), polysilicon (poly-Si), silicon germanium (SiGe), silicon nitride (SixNy), hafnium oxide (HfOx), and the like are given.

The material of the IFD film35A is silicon nitride (SixNy), silicon oxide (SiOx), aluminum oxide (AlOx), hafnium oxide (HfOx), or the like, for example.

The material of the charge storage layer36A is hafnium oxide (HfOx), for example. Other than this, the charger storage layer36A may be a semiconductor material such as Si and a Si-based compound, a material other than this (e.g. a metal or an insulating film), or a stacked film of these, for example. For example, the material of the charge storage layer36A is a semiconductor containing an n-type (second conductivity type) impurity, a metal, a metal compound, or the like. As the material, for example, amorphous silicon (a-Si), polysilicon (poly-Si), silicon germanium (SiGe), silicon nitride (SixNy), and the like are given.

The material of the insulating film37is silicon oxide (SiOx), for example.

The material of the block insulating film40is hafnium oxide (HfOx), silicon nitride (SiNx), silicon nitride (SiNx), silicon oxide (SiOx), aluminum oxide (AlOx), zirconium oxide (ZrOx), lanthanum oxide (LaOx), or the like, for example.

The material of the control gate electrode60is polysilicon, a metal such as tungsten, or a metal silicide, for example.

The material of the element isolation regions50and51is silicon oxide (SiOx), for example.

The manufacturing process of the nonvolatile semiconductor memory device1will now be described.

FIG. 2AtoFIG. 5Bare schematic cross-sectional views showing a method for manufacturing a nonvolatile semiconductor memory device according to the embodiment.

FIG. 6Ais a schematic plan view showing the method for manufacturing a nonvolatile semiconductor memory device according to the embodiment, andFIGS. 6B and 6Care schematic cross-sectional views showing the method for manufacturing a nonvolatile semiconductor memory device according to the embodiment.

The right side of each ofFIG. 2AtoFIG. 6Cillustrates the formation process of the memory cell portion100, and the left side illustrates the formation process of the peripheral portion200.

As shown inFIG. 2A, a stacked body15is formed on the semiconductor substrate10. The stacked body15includes an gate insulating film20, a charge storage layer30, an IFD film35, and a charge storage layer36.

Next, as shown inFIG. 2B, the insulating film37is formed on the stacked body15.

Subsequently, a mask layer90(a first mask layer) that covers the stacked body15in the memory cell portion100and exposes part of the stacked body15in the peripheral portion200is formed.

Next, as shown inFIG. 2C, in the peripheral portion200, the stacked body15exposed from the mask layer90is etched (for example, by RIE (reactive ion etching)) to expose the semiconductor substrate10from the stacked body15. In the peripheral portion200, the side portion15Bw of the stacked body15is exposed by the RIE. After that, the mask layer90is removed.

Next, as shown inFIG. 3A, in the memory cell portion100, the insulating film37is formed to be superposed on the stacked body15. In the peripheral portion200, the insulating film37is formed on the exposed semiconductor substrate10, on the stacked body15, and on the side portion15Bw of the stacked body15.

Subsequently, in the memory cell portion100and the peripheral portion200, a stopper film55functioning as a stopper film in the CMP processing described later is formed on the insulating film37. The material of the stopper film55is the same as the IFD film35, and is silicon nitride (SixNy), for example.

Next, as shown inFIG. 3B, in the memory cell portion100, a mask layer91A (a second mask layer) extending in the Y-direction and aligned in the X-direction crossing the Y-direction is formed on the stopper film55.

In the peripheral portion200, a mask layer91B (a third mask layer) having an opening that exposes the stopper film55is formed. The side wall91Bw of the opening91Bh of the mask layer91B is located further to the outside of the stacked body15than the side portion15Bw of the stacked body15. In other words, the mask layer91B in the peripheral portion200is formed above the stacked body15, the side portion15Bw of the stacked body15, and a partial region10bof the semiconductor substrate10continuing from the side portion15Bw of the stacked body15.

Next, as shown inFIG. 3C, in the memory cell portion100, the stopper film55exposed from the mask layer91A, the insulating film37provided under this stopper layer55, the stacked body15under this insulating film37, and the semiconductor substrate10under this stacked body15are etched by RIE. Thereby, trenches91At (first trenches) extending in the Y-direction and aligned in the X-direction are formed on the lower side of the opening of the mask layer91A.

By the formation of the trenches91At, in the memory cell portion100, the surface layer of the semiconductor substrate10is divided in the X-direction to form semiconductor regions11. Furthermore, the stacked body15is divided in the X-direction. The stacked body after the stacked body15is divided in the X-direction, including the insulating film37, is referred to as the stacked body15A.

In the peripheral portion200, the stopper film55exposed from the mask layer91B, the insulating film37under this stopper film55, and the semiconductor substrate10under this insulating film37are etched by RIE. Thereby, a trench91Bt (a second trench) is formed on the lower side of the opening of the mask layer91B.

The stacked body after the trench91Bt is formed, including the insulating film37, is referred to as the stacked body15B. After that, the mask layers91A and91B are removed.

Next, as shown inFIG. 4A, an element isolation layer52is formed in the trench91At, in the trench91Bt, and on the stopper film55.

Next, as shown inFIG. 4B, the chemical mechanical polishing (CMP) method is performed on the surface of the element isolation layer52in the memory cell portion100and the peripheral portion200. For example, the surface of the element isolation layer52is lowered by the chemical mechanical polishing method until the stopper film55is exposed. Thereby, the element isolation region50is formed in the trench91At, and the element isolation region51is formed in the trench91Bt.

Here, the width in the X-direction of the element isolation region51is wider than the width in the X-direction of the element isolation region50. Therefore, the erosion effect of chemical mechanical polishing occurs in the element isolation region51, and the surface51uof the element isolation region51becomes lower than the upper surface55uof the stopper film55. Furthermore, also a region55aof the stopper film55at a periphery of the element isolation region51is influenced by the erosion effect, and the surface of the region55ais slightly polished.

Subsequently, in the memory cell portion100, the surface50uof the element isolation region50is etched back by RIE.FIG. 4Cshows the state after the etchback. Thereby, the height of the surface50uof the element isolation region50becomes the same as the height of the stacked body15A.

In the peripheral portion200, since the material of the element isolation region51is the same as the material of the element isolation region50, also the surface51uof the element isolation region51is etched back.

Next, as shown inFIG. 5A, in the memory cell portion100and the peripheral portion200, the stopper film55is removed by wet etching.

Here, the stopper film55contains silicon nitride, and the insulating film37existing under the stopper film55contains silicon oxide different from silicon nitride. Therefore, the insulating film37is not etched by the etchant for the stopper film55. In other words, in the wet etching, the etching rate of the stopper film55is higher than the etching rate of the insulating film37.

The insulating film37is the uppermost layer of the stacked body15B, and further covers the side portion15Bw of the stacked body15B. Therefore, even if the insulating film35B contains the same material as the stopper film55, the insulating film35B is protected by the insulating film37and is not etched.

Next, as shown inFIG. 5B, in the memory cell portion100, the block insulating film40is formed on the insulating film37and on the element isolation region50. Further, in the peripheral portion200, the block insulating film40is formed on the insulating film37and on the element isolation region51.

Subsequently, in the memory cell portion100and the peripheral portion200, a control gate electrode layer60L is formed on the block insulating film40. Further, the insulating film70is formed on the control gate electrode layer60L.

Next, as shown inFIG. 6AtoFIG. 6C, photolithography and RIE are performed to divide the control gate electrode layer60L in the Y-direction to form the control gate electrode60extending in the X-direction.

FIG. 7AtoFIG. 7Dare schematic cross-sectional views showing a method for manufacturing a nonvolatile semiconductor memory device according to a reference example.

FIG. 8Ais a schematic plan view showing the method for manufacturing a nonvolatile semiconductor memory device according to the reference example, andFIGS. 8B and 8Care schematic cross-sectional views showing the method for manufacturing a nonvolatile semiconductor memory device according to the reference example.

FIG. 7Ashows a state after the chemical mechanical polishing (CMP) method is performed on the surface of the element isolation layer52described above to form the element isolation region50in the memory cell portion100and the element isolation region51in the peripheral portion200.

In the manufacturing process of the reference example, the manufacturing process shown inFIG. 2BtoFIG. 3Adescribed above is not experienced. In other words, the peripheral portion200does not experience the process that forms the mask layer90exposing part of the stacked body15, performs etching on the stacked body15exposed from the mask layer90to expose the semiconductor substrate10and the side portion15Bw of the stacked body15from the stacked body15, and forms the insulating film37on the exposed semiconductor substrate10, on the stacked body15, and on the side portion15Bw of the stacked body15.

Next, as shown inFIG. 7B, in the memory cell portion100, the surface50uof the element isolation region50is etched back by RIE. Thereby, the height of the surface50uof the element isolation region50becomes the same as the height of the stacked body15A.

In the peripheral portion200, since the material of the element isolation region51is the same as the material of the element isolation region50, also the surface51uof the element isolation region51is etched back. By the etchback, in the peripheral portion200, the surface of the insulating film35B containing the same material as the stopper film55is exposed.

Next, as shown inFIG. 7C, in the memory cell portion100and the peripheral portion200, wet etching is performed to remove the stopper film55.

Here, both the stopper film55and the insulating film35B contain silicon nitride. Therefore, also the insulating film35B is etched by the etchant for the stopper film55. Thereby, a space95is formed in a portion of the stacked body15B where the insulating film35B has been dissolved away.

Next, as shown inFIG. 7D, in the memory cell portion100, the block insulating film40is formed on the insulating film37and on the element isolation region50. Further, in the peripheral portion200, the block insulating film40is formed on the insulating film37and on the element isolation region51.

Subsequently, in the memory cell portion100and the peripheral portion200, the control gate electrode layer60L is formed on the block insulating film40. Further, the insulating film70is formed on the control gate electrode layer60L. After that, as shown inFIG. 8AtoFIG. 8C, the control gate electrode layer60L is processed to form the control gate electrode60.

If the space95is formed like the reference example, the layer36B, the insulating film37, etc. on the upper side of the space95are likely to peel off. If the peeling of films like this occurs, defects like the following may occur.

For example, an element (e.g. a transistor, a resistance, a capacitor, etc.) disposed near the space95may be destroyed. Furthermore, flakes (foreign substances) produced by the peeling of films may fly to the memory cell portion100during manufacturing processes and be attached to the memory cell portion100as foreign substances. Furthermore, a chemical liquid may remain in the space95to corrode the element further. For example, the etching in the space95may proceed and erode the surface10uof the semiconductor substrate10, and a recess96may be formed (FIG. 8C).

In contrast, in the embodiment, when the stopper film55is removed by wet etching, the uppermost layer of the stacked body15B is the insulating film37of a material different from the stopper film55, and the side portion15Bw of the stacked body15B is covered with the insulating film37. Therefore, even if the insulating film35B contains the same material as the stopper film55, the insulating film35B is protected by the insulating film37and is not etched. Thus, the space95and the recess96are not formed. Thereby, the defects mentioned above are suppressed. Consequently, a nonvolatile semiconductor memory device in which the manufacturing yield is high and reliability is high is obtained.

Hereinabove, embodiments are described with reference to specific examples. However, the embodiment is not limited to these specific examples. That is, one skilled in the art may appropriately make design modifications to these specific examples, and such modifications also are included in the scope of the embodiment to the extent that the spirit of the embodiment is included. The components of the specific examples described above and the arrangement, material, conditions, shape, size, etc. thereof are not limited to those illustrated but may be appropriately altered.

Furthermore, the components included in the above embodiments can be combined as long as technically feasible. Such combinations are also encompassed within the scope of the embodiments as long as they include the features of the embodiments. In addition, those skilled in the art could conceive various modifications and variations within the spirit of the embodiments. It is understood that such modifications and variations are also encompassed within the scope of the embodiments.