Apparatus for dynamic range enhancement

An apparatus for dynamic range enhancement (DRE) which receives an input signal and provides a DRE output signal is presented. The apparatus has an error correction circuit to apply an error correction factor to the input signal such that the DRE output signal provided by the apparatus is dependent on the input signal and the error correction factor. The error correction factor is representative of an error generated by the apparatus.

The present disclosure relates to an apparatus for dynamic range enhancement. In particular, the disclosure relates to an apparatus for dynamic range enhancement comprising an error correction circuit.

BACKGROUND

Dynamic range enhancement (DRE) is a technique that is used to suppress errors in a signal path. DRE amplifies a signal prior to a processing step that introduces errors into the signal and then attenuates the signal after the processing step.

FIG. 1shows a schematic of a DRE system100comprising an amplifier circuit102, a processing circuit104and an attenuation circuit106. A signal path is formed from a signal path input108to a signal path output110. In the DRE system100, the signal path input108corresponds to an input of the amplifier circuit102and the signal path output110corresponds to an output of the attenuation circuit106. In the DRE system100ofFIG. 1, the amplifier circuit102may for example provide a gain of +12 dB and the attenuation circuit106may for example provide a gain of −12 dB.

In operation a signal is received at the input of the amplifier102. The signal is then amplified by a gain of +12 dB before being passed to the processing circuit104.

The processing circuit104comprises a processing block112and a summing circuit114. The processing block112is representative of a processing step carried out on the signal by the processing circuit104and the summing circuit114is representative of the addition of an error116to the signal as it passes through the processing circuit104. The processing circuit104outputs the signal to the attenuation circuit106which attenuates the signal by a gain of −12 dB before providing the signal at the output of the attenuation circuit106. The error116added to the signal as it passes through the processing circuit104is suppressed by 12 dB when referred to either the signal path input108or the signal path output110.

FIG. 2shows a DRE circuit200corresponding to an alternative schematic of the DRE system100shown inFIG. 1. Common features betweenFIGS. 1 and 2share common reference numerals and variables. The amplifier circuit102receives a digital input signal d[n] at the signal path input108. The amplifier circuit106applies a dynamic digital gain gd[n] to the digital input signal d[n]. The processing circuit104comprises a digital to analog converter (DAC)202for converting a digital signal to an analog signal.

The summing circuit114and the processing block112have been omitted inFIG. 2, however it will be appreciated that the DAC202incorporates these features, as the DAC202is susceptible to the error116and the DAC202provides a digital to analog conversion function, as may be represented by the processing block112. For the processing circuit104comprising the DAC202, the error116may, for example, result from random noise and/or supply interference.

The DAC202has an impulse response h[n]. The impulse response h[n] describes how the DAC202responds to receiving a signal over a short time frame. The attenuation circuit106applies a dynamic analog gain ga[n] and outputs an analog output signal a[n] at the signal path output110.

The signal path of the DRE circuit200may be referred to as a D/A signal path as the inclusion of the DAC202means that an input digital signal is converted to an output analog signal.

The DRE circuit200also shows a model for the signal path, which can be represented mathematically as shown in equation (1). The analog output signal a[n] is as follows:
a[n]=((d[n]·gd[n])*h[n])·ga[n]  (1)
where the symbols have their meanings as described previously. n is a time index and therefore equation (1) is in the time domain. The time index n has discrete values. Multiplication in the time domain of two time-varying sequences, namely the digital input signal d[n] and the digital gain gdd[n], makes the DRE circuit200non-linear such that the DRE circuit200may result in undesirable behaviour. The DRE circuit200may even exhibit non-linear behaviour for a relatively small digital input signal d[n].

FIG. 3AandFIG. 3Bshow simulation results for the DRE circuit200ofFIG. 2. The simulations were performed using parameters that are representative of a practical implementation of the DRE circuit200.

FIG. 3Ashows the dynamic digital gain gd[n]300, and the dynamic analog gain ga[n]302, as they vary with time.FIG. 3(b)shows the analog output signal a[n]304as it varies with time. Prior to a time t1, the gains gd[n]300, ga[n]302are equal to one and the analog output signal a[n]304is equal to 0.25V.

It should be noted that the units associated with the x axis ofFIG. 3Aare seconds (s), and the units associated with the x axis ofFIG. 3Bare microseconds (μs).

At the time t1, the gain gd[n]300increases to 2 and the gain ga[n]302decreases to 0.5. Because the processing circuit104has a finite bandwidth, the gain change at the time t1results in a transient output error in the analog output signal a[n]304that resembles a decaying impulse. The error is shown by the fall in the analog output signal a[n]304and its gradual rise as the analog output signal a[n]304decays back to its initial value.

It will be appreciated that if the processing circuit104was omitted, the gains gd[n], ga[n] would not introduce an error into the signal path.

FIG. 4shows a trace400of the Fourier transform of the analog output signal a[n]304with no gain change applied and a trace402of the Fourier transform of the analog output signal a[n] with a gain change applied. The trace402shows the Fourier transform of the analog output signal a[n] when a 6 dB step is applied to the input signal d[n] by the amplifier circuit102and a corresponding −6 dB is applied by the amplifier circuit106.

Since the Fourier transform of a decaying impulse is a low pass filter, the error is flat at low frequencies and rolls off at high frequencies, as can be observed by the trace400. By “flat” it is meant that the error maintains a substantially constant value at low frequencies and by “rolls off” it is meant that error decreases at high frequencies as the frequency increases.

It will be appreciated that the low pass filter characteristics shown by the trace400are a result of the impulse response h[n] of the DAC202being a low pass filter, however other filter types may be used.

For audio applications of DRE, the flat response of the error at low frequencies means that the gain change may result in a highly undesirable audible click.

SUMMARY

It is desirable to provide an apparatus for dynamic range enhancement that can reduce errors during dynamic range enhancement gain changes when compared with the prior art.

According to a first aspect of the disclosure there is provided an apparatus for dynamic range enhancement (DRE) which receives an input signal and provides a DRE output signal, comprising an error correction circuit configured to apply an error correction factor to the input signal such that the DRE output signal provided by the apparatus is dependent on the input signal and the error correction factor, wherein the error correction factor is representative of an error generated by the apparatus.

Optionally, the apparatus comprises a DRE circuit, wherein the error correction circuit is configured to receive the input signal and to provide a corrected signal based on the input signal and the error correction factor, and the DRE circuit is configured to receive the corrected signal and to provide the DRE output signal based on the received corrected signal.

Optionally, the DRE circuit comprises an amplifier circuit configured to amplify the corrected signal, a processing circuit configured to receive the corrected signal from the amplifier circuit and to process the corrected signal, and an attenuation circuit configured to receive the corrected signal from the processing circuit, to attenuate the corrected signal and to provide the corrected signal as an output of the attenuation circuit, wherein the DRE output signal corresponds to the corrected signal output by the attenuation circuit.

Optionally, the processing circuit comprises a digital to analog converter (DAC) configured to receive the corrected signal from the amplifier circuit, wherein processing the corrected signal comprises converting the corrected signal from digital to analog using the DAC.

Optionally, the error correction circuit comprises a summing circuit configured to generate the corrected signal by adding or subtracting the error correction factor from the input signal, the corrected signal being provided at an output of the error correction circuit.

Optionally, the apparatus comprises a sigma delta modulator comprising the error correction circuit, wherein the sigma delta modulator is configured to reduce the resolution of the corrected signal prior to the corrected signal being received by the processing circuit.

Optionally, the sigma delta modulator comprises a loop filter, and a quantiser configured to reduce the resolution of the corrected signal prior to the corrected signal being received by the processing circuit, wherein the loop filter comprises a first input for receiving the corrected signal and an output coupled to the quantiser, and the quantiser has an output coupled to the processing circuit and a second input of the loop filter.

Optionally, the output of the quantiser is coupled to the processing circuit via the amplifier circuit.

Optionally, the loop filter is coupled to the quantiser via the amplifier circuit and the output of the quantiser is coupled to the second input the loop filter via a second amplifier circuit.

Optionally, the apparatus comprises a sigma delta modulator comprising the error correction circuit, wherein the sigma delta modulator is configured to reduce the resolution of the corrected signal prior to the corrected signal being received by the processing circuit.

Optionally, the error correction circuit comprises a loop filter comprising a first input for receiving the input signal, and a summing circuit comprising a first input for receiving the error correction factor and an output coupled to the second input of the loop filter, and the sigma delta modulator comprises a quantiser, wherein the loop filter comprises an output coupled to the quantiser, wherein the corrected signal is provided at the output of the loop filter, and the quantiser has an output coupled to the processing circuit and a second input of the summing circuit.

Optionally, the output of the quantiser is coupled to the processing circuit via the amplifier circuit.

Optionally, the loop filter is coupled to the quantiser via the amplifier circuit and the output of the quantiser is coupled to the second input of the loop filter via a second amplifier circuit.

Optionally, the apparatus comprises a memory element configured to store the error correction factor and to provide the error correction factor to the error correction circuit.

Optionally, the error correction factor is derived by calculating the error generated by the apparatus.

Optionally, the apparatus comprises an error correction factor generator configured to detect the error generated by the apparatus, to generate the error correction factor using the detected error, and to provide the error correction factor to error correction circuit.

Optionally, the apparatus comprises a DRE circuit comprising the error correction circuit, an amplifier circuit configured to amplify the input signal, a processing circuit configured to receive the input signal from the amplifier circuit and to process the input signal, and an attenuation circuit configured to receive the input signal from the processing circuit, to attenuate the input signal and to provide the input signal as an output of the attenuation circuit, wherein the DRE output signal corresponds to the input signal output by the attenuation circuit, and the input signal is adjusted by the error correction circuit based on the error correction factor prior to being output by the attenuation circuit as the DRE output signal.

Optionally, the attenuation circuit comprises the error correction circuit, and the error correction circuit is configured to adjust the attenuation applied by the attenuation circuit based on the received error correction factor.

Optionally, the error generated by the apparatus results from at least one of a gain change or a delay.

Optionally, the error correction circuit is configured to receive the error correction factor.

According to a second aspect of the disclosure there is provided a method of dynamic range enhancement (DRE) using an apparatus comprising an error correction circuit, the method comprising receiving an input signal at the apparatus, applying an error correction factor to the input signal using the error correction circuit, and providing a DRE output signal, wherein the DRE output signal provided by the apparatus is dependent on the input signal and the error correction factor, and the error correction factor is representative of an error generated by the apparatus.

It will be appreciated that the method of the second aspect may include providing and/or using the features set out in the first aspects and can incorporate other features as described herein.

DESCRIPTION

The error116described forFIG. 1is reduced through the inclusion of a dynamic range enhancement (DRE) circuit, for example of the type shown inFIG. 2. The present disclosure provides an apparatus that can reduce errors that arise due to the inclusion of the DRE circuit itself. In particular, the disclosure relates to the reduction of errors that arise due to the gain change associated with the DRE circuit.

FIG. 5Ashows an apparatus500for dynamic range enhancement (DRE) in accordance with a first embodiment of this disclosure. The apparatus500is configured to receive an input signal d[n] and provides a DRE output signal a[n].

The apparatus500comprises an error correction circuit502. The error correction circuit502is configured to apply an error correction factor de[n] to the input signal d[n] such that the DRE output signal a[n] provided by the apparatus500is dependent on the input signal d[n] and the error correction factor de[n]. The error correction factor de[n] is representative of an error generated by the apparatus500.

FIG. 5Bshows an embodiment of the apparatus500for dynamic range enhancement (DRE) as shown inFIG. 5Ain accordance with a second embodiment of this disclosure. The apparatus500is configured to receive an input signal d[n] and to provide a DRE output signal a[n].

The apparatus500comprises the error correction circuit502and a DRE circuit504.

The error correction circuit502is configured to receive the input signal d[n] and the error correction factor de[n], and to provide a corrected signal510that is based on the input signal d[n] and the error correction factor de[n]. The DRE circuit504is configured to receive the corrected signal510and to provide the DRE output signal a[n] based on the received corrected signal510. The error correction factor de[n] is representative of an error generated by apparatus500, and in particular is representative of the error generated by the DRE circuit504.

The term “error correction signal de[n]” may be used to refer to the error correction factor de[n] when the error correction factor de[n] is received by the error correction circuit502.

The signal path is formed from an input of the error correction circuit502that receives the input signal d[n] to an output of the DRE circuit504that provides the DRE output signal a[n].

The input signal d[n] may correspond to the digital input signal d[n] as described forFIG. 2and the DRE output signal a[n] may correspond to the analog output signal a[n] as described forFIG. 2.

The error correction circuit502enables the error incurred due to the gain change of the DRE circuit504to be substantially removed from the signal path of the apparatus500. The error correction signal de[n] may be representative of the error incurred due to the gain change of the DRE circuit504.

The error correction signal de[n] may be derived by calculating the error generated by the apparatus500, and in particular by calculating the error generated by the DRE circuit504, for example by calculating the error that is expected from the gain change of the DRE circuit504. The expected error may be calculated by considering the circuit components of the DRE circuit504. Alternatively, the error correction signal de[n] may simply be estimated without any detailed derivation of the expected error.

FIG. 5Cshows an apparatus501in accordance with a third embodiment of this disclosure. The apparatus501corresponds to the apparatus500, however in this specific embodiment the apparatus501comprises a memory element503configured to store the error correction signal de[n] and to provide the error correction signal de[n] to the error correction circuit502. Common features between different Figures are represented by common reference numerals and common variables.

FIG. 5Dshows an apparatus505in accordance with a fourth embodiment of this disclosure. The apparatus505corresponds to the apparatus500, however in this specific embodiment the apparatus505comprises an error correction signal generator506. A feedback loop is formed from the DRE circuit504to the error correction circuit502via the error correction signal generator506. Using the error correction signal generator506, the error correction signal de[n] may be derived during operation of the DRE circuit504. The error correction signal generator506is configured to detect the error generated by the apparatus500(in particular, the error generated by the DRE circuit504) and to generate a suitable error correction signal de[n] using the detected error. The error correction signal generator506then provides the error correction signal de[n] to the error correction circuit502. Common features between different Figures are represented by common reference numerals and common variables.

It will be appreciated that there are other methods to determine the error correction signal de[n] in accordance with the understanding of the skilled person.

FIG. 6Ashows an apparatus600in accordance with a fifth embodiment of this disclosure. The apparatus600corresponds to the apparatus500but with specific implementations of the error correction circuit502and the DRE circuit504. The specific implementations share features with DRE system100and the DRE circuit200. Common features between different Figures are represented by common reference numerals and common variables.

The input signal d[n] is adjusted by the error correction circuit502, based on the error correction signal de[n], to provide the corrected signal510. Specifically, the error correction circuit502comprises a summing circuit602that is configured to generate the corrected signal510by adding or subtracting the error correction signal de[n] from the input signal d[n]. The corrected signal510generated by the error correction circuit502is provided at an output of the error correction circuit502to the DRE circuit504. In the present embodiment the corrected signal510is generated by subtracting the error correction signal de[n] from the input signal d[n].

The DRE circuit504comprises the amplifier circuit102, the processing circuit104which comprises the DAC202, and the attenuation circuit106. The amplifier circuit102is configured to amplify the corrected signal510by the dynamic digital gain gd[n]. The amplifier circuit102receives the corrected signal510from the error correction circuit502.

The processing circuit104is configured to receive the corrected signal510from the amplifier circuit102and to process the corrected signal510. In this specific embodiment, the DAC202is configured to receive the corrected signal510from the amplifier circuit102and the processing of the corrected signal510comprises converting the corrected signal510from digital to analog using the DAC202. The attenuation circuit106is configured to receive the corrected signal510from the processing circuit104, to attenuate the corrected signal510by the dynamic analog gain ga[n], and to provide the corrected signal510as an output of the attenuation circuit106. In this specific embodiment, the attenuation circuit106is configured to receive the corrected signal510from the DAC202. The DRE output signal a[n] corresponds to the corrected signal510output by the attenuation circuit106.

The apparatus600also shows a model for the signal path, which can be represented mathematically, and with reference to the relevant transfer functions, as shown in equation (2). The DRE output signal a[n] is as follows:
a[n]=(((d[n]−de[n])·gd[n])·h[n])·ga[n]  (2)

From equation (2) it is possible to derive an error correction signal de[n] that corresponds to the error generated during the gain change. The error correction signal de[n] can then be referred to the input of the signal path as a digital signal to compensate for the error incurred during the gain change. In the apparatus600, the error correction signal de[n] represents the input-referred, time-varying error sequence. Subtracting the error correction signal de[n] at the input of the signal path can reduce, and may substantially eliminate, the error from the DRE output signal a[n]. In this specific embodiment, the error correction signal de[n] is subtracted from the input signal d[n] using the summing circuit602. The corrected signal510output by the summing circuit602therefore corresponds to the input signal d[n] minus the error correction signal de[n].

An ideal DRE output signal a[n] is given by equation (3):
a[n]=d[n]*h[n]  (3)

The ideal DRE output signal a[n] is the DRE output signal a[n] in the event that no gain change occurs.

The error correction signal de[n] may be derived by combining equations (2) and (3), and is given by equation (4):

Therefore, by providing an error correction signal de[n] to the error correction circuit502, as derived using equation (4), it is possible to reduce the error resulting from a gain change in the signal path and therefore it is possible to reduce the error on the DRE output signal a[n].

It will be appreciated that the processing circuit104of the embodiments presented in this disclosure may alternatively comprise a circuit component, element or device that has an impulse response h[n], other than the DAC202, in accordance with the understanding of the skilled person. For example, the processing circuit104may comprise an analog to digital converter (ADC).

FIG. 6Bshows an apparatus604in accordance with a sixth embodiment of this disclosure. The apparatus604comprises the apparatus600and a sigma delta modulator606. The sigma delta modulator606comprises a loop filter608and a quantiser610. Common features between different Figures are represented by common reference numerals and common variables. The sigma delta modulator606is configured to reduce the resolution of the input signal d[n] prior to the input signal d[n] being received by the processing circuit104.

The loop filter608comprises a first input corresponding to the signal path input108. The first input of the loop filter608is configured to receive the input signal d[n]. The loop filter608comprises an output coupled to the quantiser610. The quantiser610has an output coupled to the processing circuit104and a second input of the loop filter608. The output of the quantiser610is coupled to the processing circuit104via the error correction circuit502and the amplifier circuit102.

The quantiser610is configured to reduce the resolution of the input signal d[n] prior to the input signal d[n] being received by the processing circuit104.

In operation, the quantiser610receives the input signal d[n], after it is filtered through the loop filter608and converts the input signal d[n] from a medium-to-high resolution digital signal, to a low resolution digital signal.

Reducing the resolution of the input signal d[n] enables easier processing of the corrected signal510by the DAC202. However, the decrease in resolution of the input signal d[n] results in the generation of an error, known as quantisation noise.

The loop filter608operates on the difference between the signals received at its inputs, namely the input signal d[n] received at the first input and the low resolution digital signal output by the quantiser610, The low resolution digital signal output by the quantiser610corresponds to the input signal d[n] after having passed through the loop filter608and the quantiser610.

The loop filter608operates on the difference between the input signal d[n] and the low resolution digital signal in such a way that the quantisation noise from the quantiser610is shaped out of band in accordance with standard sigma delta modulator operating principles, as will be clear to the person skilled in the art.

The spectral manipulation of quantisation noise by the loop filter608using this method is often referred to as “noise shaping.” The quantisation noise at low frequencies is substantially removed, as is desirable, and the quantisation noise at higher frequencies may simply be filtered out. The noise shaping features of sigma delta modulators mean that they are particularly useful in low-bandwidth applications, such as in audio applications.

FIG. 6Cshows an apparatus612in accordance with a seventh embodiment of this disclosure. The apparatus612comprises the apparatus604, with a specific implementation of the loop filter608shown. Common features between different Figures are represented by common reference numerals and common variables.

The loop filter608comprises a summing circuit614configured to subtract the output of the quantiser608(the low resolution digital signal) from the input signal d[n]. The loop filter608further comprises an integrator circuit616that is configured to operate on the difference between the input signal d[n] and the low resolution digital signal in such a way that the quantisation noise from the quantiser608is shaped out of band, as discussed previously.

It will be appreciated that other loop filter608implementations are available for sigma delta modulators which include, but are not limited to, multiple feedforward paths, multiple feedback paths, multiple integrators, and multiple modulators (as in MASH structures), in accordance with the understanding of the skilled person.

FIG. 7Ashows an apparatus700in accordance with an eighth embodiment of this disclosure. The apparatus700corresponds to the apparatus500but with specific implementations of the error correction circuit502and the DRE circuit504. The specific implementations share features with DRE system100and the DRE circuit200. Common features between different Figures are represented by common reference numerals and common variables.

The apparatus700comprises a sigma delta modulator702. The sigma delta modulator702comprises the error correction circuit502. The sigma delta modulator702is configured to reduce the resolution of the corrected signal510prior to the corrected signal510being received by the processing circuit104.

In this specific embodiment, the error correction circuit502comprises a loop filter704, a summing circuit706and the summing circuit602. The loop filter704comprises a first input corresponding to the signal path input108. The first input of the loop filter704is configured to receive the input signal d[n]. The summing circuit706comprises a first input for receiving the error correction signal de[n] and an output coupled to a second input of the loop filter704.

In this specific embodiment, the summing circuit706is configured to add the signal received from a quantiser708to the error correction signal de[n] and provide the resultant signal to the second input of the loop filter704. Alternatively, in a further embodiment, the summing circuit706may be configured to subtract the error correction signal de[n] from the signal received from the quantiser708in accordance with the understanding of the skilled person.

The sigma delta modulator702comprises the quantiser708. The loop filter704comprises an output coupled to the quantiser708. The corrected signal510is provided at the output of the loop filter704.

The quantiser708has an output coupled to the processing circuit104via the amplifier circuit102and the summing circuit602. The output of the quantiser608is coupled to the second input of the summing circuit706via the summing circuit602. The summing circuit602subtracts the error correction signal de[n] from the signal received from the output of the quantiser708.

The quantiser708is configured to reduce the resolution of the corrected signal510prior to the corrected signal510being received by the processing circuit104.

It will be appreciated that the apparatus700is mathematically equivalent to the apparatus604, as the summing circuit602has merely be moved within the feedback loop formed from the quantiser708to the second input of the loop filter704, with the further summing circuit706being used to remove the error correction signal de[n] from the feedback loop prior to being received by the loop filter704.

It will be appreciated that the summing circuits602,706may be located in another part of the apparatus700in accordance with the understanding of the skilled person.

As described previously for the apparatus600, by providing an error correction signal de[n] to the error correction circuit502of the apparatus700, as derived using equation (4), it is possible to reduce the error resulting from a gain change in the signal path and therefore it is possible to reduce the error on the DRE output signal a[n].

FIG. 7Bshows an apparatus710in accordance with an ninth embodiment of this disclosure. The apparatus710corresponds to the apparatus700but with the error correction term as part of the feedforward path of the sigma delta modulator200removed, as seen by the removal of the summing circuit602. Common features between different Figures are represented by common reference numerals and common variables.

For a D/A signal path comprising a sigma delta modulator, the input signal d[n] may be a high-speed, low resolution digital signal. In this case, subtracting a high resolution error correction signal de[n] from the signal output by the quantiser610,708, for example as shown in the apparatuses600,700, may be difficult and can result in further error in the signal path.

To resolve this issue, the summing circuit602is removed, such that subtraction of the error correction signal de[n] from the feedforward path of700is removed. Removal of the summing circuit602results in an additional error relative to the other apparatuses, however this additional error will be “shaped” by the sigma delta modulator702and its feedback loop comprising the loop filter704, as part of the noise shaping process as discussed previously.

For common sigma delta modulator designs, the additional error arising due to the removal of the summing circuit602will be negligible compared to the quantisation noise introduced by the quantiser708.

In operation, the quantiser708receives the corrected signal510and converts the corrected signal510from a medium-to-high resolution digital signal, to a low resolution digital signal. Reducing the resolution of the corrected signal510enables easier processing of the corrected signal510by the DAC202. However, the decrease in resolution of the corrected signal510results in the generation of an error, known as quantisation noise.

FIG. 8shows an apparatus800in accordance with a tenth embodiment of this disclosure. The apparatus800corresponds to the apparatus500but with specific implementations of the error correction circuit502and the DRE circuit504. The specific implementations share features with DRE system100, the DRE circuit200, the apparatus600and the apparatus710. Common features between different Figures are represented by common reference numerals and common variables.

The apparatus800, comprises the sigma delta modulator702. The sigma delta modulator702comprises the error correction circuit502. The sigma delta modulator702is configured to reduce the resolution of the corrected signal510prior to the corrected signal510being received by the processing circuit104, as discussed for the quantiser708for the apparatus710.

The sigma delta modulator702comprises the loop filter704and the quantiser708. The loop filter704comprises a first input for receiving the corrected signal510from the summing circuit602; and the loop filter704comprises an output coupled to the quantiser708. The quantiser708has an output coupled to the processing circuit104and a second input of the loop filter704. The output of the quantiser708is coupled to the processing circuit104via the amplifier circuit102.

For the purposes of deriving the error correction signals de[n], the transfer function of the sigma delta modulator, specifically the signal transfer function (STF), is preferably accounted for in the impulse response h[n] in equation (4).

FIG. 9shows an apparatus900in accordance with an eleventh embodiment of this disclosure. The apparatus900corresponds to the apparatus500but with specific implementations of the error correction circuit502and the DRE circuit504. The specific implementations share features with DRE system100, the DRE circuit200, the apparatus600and the apparatus710. Common features between different Figures are represented by common reference numerals and common variables.

In this specific embodiment, the loop filter704is coupled to the quantiser708via the amplifier circuit102. The output of the quantiser708is coupled to the second input of the loop filter704via an amplifier circuit902. The amplifier circuit902may have a gain equal to 1/gd[n], where gd[n] is the gain of the amplifier circuit102.

FIG. 10shows an apparatus1000in accordance with a twelfth embodiment of this disclosure. The apparatus1000corresponds to the apparatus500but with specific implementations of the error correction circuit502and the DRE circuit504. The specific implementations share features with DRE system100, the DRE circuit200, the apparatus600, the apparatus710and the apparatus900. Common features between different Figures are represented by common reference numerals and common variables.

In this specific embodiment, the loop filter704is coupled to the quantiser708via the amplifier circuit102. The output of the quantiser708is coupled to the second input of the loop filter via the amplifier circuit902.

The DAC202may function as a filter having an infinite impulse response (IIR) or finite impulse response (FIR). An IIR means that the impulse response h[n] does not reduce to zero after a sufficiently long time period, whereas a FIR means that the impulse response h[n] does reduce to zero after a sufficiently long time period. The DAC202can take on an IIR response or a FIR response if discrete-time modelled, or an IIR response if continuous-time modelled. The present disclosure may be applied to a DAC202having an IIR response or a FIR response. It will be appreciated that the present disclosure may be applied to any suitable circuit component, element or device that can be modelled as having an IIR response or a FIR response.

The appropriate error correction signal de[n] to reduce the error arising due to the gain change for a DAC202functioning as an IIR filter may be derived as follows.

An example IIR filter with impulse response, h[n], has a transfer function, H(z), given by equation (5). In this section z is the well-known variable representing the discrete-time frequency domain, and α is a function of the IIR filter pole frequency. Square brackets are used to indicate time indices, and parentheses are used to indicate frequency indices.

Using equation (5), an output y[n] of the IIR filter, for an input x[n], can be derived as equation (6).
y[n]=(1−α)×[n]+αy[n−1]  (6)

The inverse of equations (5) and (6), are given by equations (7) and (8), respectively. Equation (8) is necessary for the derivation of a suitable error correction signal de[n] as described previously with respect to equation (4).

The gains gd[n], ga[n] are modelled as changing from a first gain G1to a second gain G2when the time index n is equal to zero and with inverse magnitude step sizes with respect to each other, as shown by equations (9) and (10).

The dynamic digital gain gd[n] is equal to the first gain G1when the time index n is less than zero and the dynamic digital gain gd[n] is equal to the second digital gain G2when the time index n is greater than or equal to zero. The dynamic analog gain ga[n] is equal to one over the first gain G1when the time index n is less than zero and the dynamic analog gain ga[n] is equal to one over the second digital gain G2when the time index n is greater than or equal to zero.

With regards to equation (4), for the time index n being less than zero (n<0), the gains gd[n], ga[n] are both unity as the first gain G1is equal to one. The gains gd[n], ga[n] are modelled as being equal to one since the beginning of time. For the time index n being less than zero the input signal d[n] is simply passed through both the impulse response h[n] and its inverse h−1[n], and the error correction signal de[n] is equal to zero.

With regards to equation (4), for the time index n being much greater than zero (n>>0), the gain change has settled out such that de[n] is also equal to zero.

With regards to equation (4), for the time index n being equal to zero (n=0), the error correction signal de[n] is given by equation (11) as follows:

The inverse of the impulse response, h−1[n], is a first-order difference in this example meaning only the terms at n=−1 and n=−2 from (d*h) [n], ga[n] and gd[n] contribute to equation (11). Therefore, when the time index n=1, the history of the gain change is no longer a concern and de[1]=0; this means that for a single-pole IIR response only a single term is needed to correct for the effects of the gain change: de[0], as given by equation (11).

Providing the error correction signal de[0], given by equation (11) to the error correction circuit502of any of the embodiments of this disclosure will substantially cancel the effects of the gain change resulting from DRE, provided the impulse response h[n] of the DAC202and the gain changes match those used for the IIR filter analysis outlined using equations (5)-(11).

Provided the DAC IIR coefficients are optimised in accordance with the above discussion, a digital multiplier is not needed. Therefore, there may be a reduction in power requirements and costs when compared to prior art circuits.

The above analysis for an IIR filter has been performed for the impulse response h[n], where the impulse response h[n] is a transfer function having a single pole. It will be appreciated that the analysis can be repeated for an arbitrary transfer function with any number of poles. The resulting error correction signal de[n] will have a number of terms equal to the number of poles in the transfer function.

FIG. 11shows simulation results for the DRE circuit200where the DAC202functions as an IIR filter and no error correction signal de[n] is applied. The simulations were performed using parameters that are representative of a practical implementation of the DRE circuit200.

FIG. 11shows a trace1100of the Fourier transform of the output signal a[n] and a trace1102of the Fourier transform of the signal that is received at the DAC202from the amplifier circuit102.

The trace1102shows a 6 dB step applied to the input signal d[n] by the amplifier circuit102. The flat portion of the output signal a[n]1100at low frequencies is due to the error arising due to the gain change.

FIG. 12shows simulation results for the apparatus600where the DAC202functions as an IIR filter, and the error correction signal de[n] is applied. The simulations were performed using parameters that are representative of a practical implementation of the apparatus600. The error correction signal de[n] corresponds to the error correction signal de[0] that may be derived using equation (11).

FIG. 12shows a trace1200of the Fourier transform of the output signal a[n] and a trace1202of the Fourier transform of the corrected signal510that is received at the DAC202from the amplifier circuit102.

The flat portion of the corrected signal510that is received at the DAC202is because the error correction signal de[n] has been added to the input signal d[n] with equal magnitude and opposite sign to the error arising due to the gain change of the DRE circuit504. Therefore, the output signal a[n] is substantially free from errors that arise due to the gain change associated with the DRE circuit504.

The appropriate error correction signal de[n] to reduce the error arising due to the gain change for a DAC202functioning as an FIR filter is given by equation (12).

de⁡[n]=-(1-1G⁢1ga⁡[n-1])⁢∑i=n-M+1n-1⁢d⁡[i]+1G⁢1ga⁡[n-1]⁢d⁡[n-M]-1G⁢((d⁡[n]*h⁡[n])ga⁡[n]×h-1⁡[n-M])(12)
where G is a gain, i is an integer and M is an integer. The derivation of equation (12) will be clear to the skilled person.

FIG. 13shows an apparatus1300in accordance with a thirteenth embodiment of this disclosure. The apparatus1300corresponds to the apparatus600with an arbitrary delay1302(and represented by Δ) that may be introduced into the corrected signal510during processing by the processing circuit104. The delay1302may be constant with frequency and is characteristic of most practical implementations of a DRE circuit.

In the present embodiment, the delay1302can compensated by modifying the impulse response h[n] used to determine the error correction signal de[n] to account for the delay1302. Therefore, the corrected signal510accounts for both the error due to the gain change, and the error arising due to the delay1302. It will be appreciated that one or both of these errors may be compensated for using the present embodiment, in accordance with the understanding of the skilled person.

FIG. 14shows an apparatus1400in accordance with a fourteenth embodiment of this disclosure. The apparatus1400corresponds to the apparatus500but with specific implementations of the error correction circuit502and the DRE circuit504. Common features between different Figures are represented by common reference numerals and common variables. In the apparatus1400, the DRE circuit504comprises the error correction circuit502. The input signal d[n] is adjusted by the error correction circuit502based on an error correction factor prior to being output by the attenuation circuit106as the DRE output signal a[n].

In this specific embodiment, the attenuation circuit106comprises the error correction circuit502. The error correction circuit502is configured to adjust the attenuation applied by the attenuation circuit106based on the error correction factor, where the error correction factor comprises a transfer function ha[n]. The attenuation applied by the attenuation circuit is dependent on the dynamic analog gain ga[n]. In this specific embodiment, the error correction factor is representative of the error generated by the DRE circuit504, and in particular the error resulting from the delay1302.

The error correction circuit502applies the error correction factor to the input signal d[n] by applying the transfer function ha[n] to the dynamic analog gain ga[n] thereby adjusting the attenuation applied to the input signal d[n] received by the attenuation circuit106.

In effect, the error correction circuit502and the error correction factor comprising the transfer function ha[n] adds a delay (matching the delay1302) to the dynamic analog gain ga[n], thereby compensating for the delay1302.

In this embodiment the error correction circuit502may be implemented using analog or digital circuitry. The delay1302does not result in additional error when the gain is changed and the delay provided by the transfer function ha[n] may be made arbitrarily large within the confines of the apparatus1400.

It can be observed that the error is also compensated for in the apparatus1400using the summing circuit602and the error correction signal de[n]. It will be appreciated that one or both of these error correction techniques may be applied in a single embodiment. Additionally, the method of correcting the error due to the delay1302may be applied to any of the embodiments presented herein, in accordance with the understanding of the skilled person.

Generally speaking, the method of applying the error correction signal de[n] to the feedback loop of the sigma delta modulator (for example the sigma delta modulator702of the apparatus710) may be used for A/D or D/A signal paths, in accordance with the understanding of the skilled person. For example, for an A/D signal path, the processing circuit104may comprise an ADC.

When DRE is used, the input signal d[n] may be sufficiently small such that adding the error correction signal de[n] to the feedback loop of the sigma delta modulator (for example the sigma delta modulator702of the apparatus710) does not compromise stability of the apparatus.

The embodiments present herein can improve the dynamic range performance of a DRE circuit without the standard power penalty to lower thermal noise. The apparatus600described for the fifth embodiment may be used in any high-resolution signal path that employs a DRE circuit. The apparatuses comprising a sigma delta modulator can be used in any signal path that incorporates both a sigma delta modulator and a DRE circuit.

The embodiments disclosed herein may be generalised for use in both audio input and audio output signal paths, in accordance with the understanding of the skilled person. The embodiments of the present disclosure may be applied solely in the digital domain, particularly when DRE is applied to a D/A signal path. With a digital implementation, the circuit can be verified, production test screened and easily ported to different technologies.

The embodiments of the present disclosure do not rely on an analog-digital feedback loop for correction. By using a feedforward rather than feedback method, there are no concerns with the stability of large analog-digital feedback loop. Additionally, addition of the error correction signal de[n] to a sigma delta modulator loop does not compromise stability.

Various improvements and modifications may be made to the above without departing from the scope of the disclosure.