Voltage protection circuit for thin oxide transistors, and memory device and processor-based system using same

Devices, reference voltage generators, systems and methods are disclosed, including an embodiment of a voltage regulator output transistor using a thin gate insulator to provide a low output impedance despite having a semiconductor channel width that is relatively small. The output transistor is protected from damage by a clamping circuit provided to limit the gate-to-source voltage of the transistor such that damage to the output transistor should be reduced or prevented. One such clamping circuit includes a clamp transistor that receives a reference voltage at its gate. The magnitude of the reference voltage limits to voltage to which the gate of the transistor can be driven. A voltage reference circuit provides the reference voltage so that it compensates for process and temperature variations of the output transistor.

TECHNICAL FIELD

This invention relates generally to semiconductor drivers, and, more particularly, in one or more embodiments, to a circuit for protecting thin film transistors from being damaged by excessive drive voltages.

BACKGROUND OF THE INVENTION

Semiconductor devices, such as MOSFET transistors, are generally designed to have specific performance features. For example, MOSFET transistors used as output transistors for voltage regulators or MOSFET transistors used or in other high current applications should have a low output impedance. As a result, such transistors generally have a relatively large channel width to reduce the ON impedance of the transistors. Although a large channel width is effective in providing a low output impedance, a large channel width does impose certain disadvantages. A large channel width, for example, consumes a relatively large amount of area on a semiconductor die, thus increasing the cost of devices using such wide channel MOSFET transistors. A large channel width also results in a relatively large gate capacitance, which reduces the operating speed of such MOSFET transistors.

Another parameter that affects the design of MOSFET transistors is the voltage level with which they are capable of operating. For example, the gate-to-source voltage of a MOSFET transistor must be limited to a value that does not cause damage to an insulative layer between the gate and the channel. Such gate insulation is generally in the form of a layer of silicon dioxide, which can be damaged by excessive gate-to-source voltages. The gate-to-source voltage that a MOSFET transistor is capable of withstanding can be increased by increasing the thickness of the gate insulation. However, thicker layers of insulative material can adversely affect the performance of MOSFET transistors. For example, a thicker gate insulation layer reduces the driving ability and bias current of such transistors, and it requires an increase in the length of the channels. Yet, a large channel length again increases the size that MOSFET transistors consume on a semiconductor die.

There is therefore an inevitable trade-off between the size of MOSFET transistors and their ability to handle large currents and large drive voltages. A MOSFET having a relatively small length and width could be used if the thickness of the gate insulation layer could be reduced. But reducing the gate thickness limits the voltage with which such transistors can be used. As a result, it has heretofore been necessary for MOSFET transistors used as voltage regulator output transistors or in other applications handling a high current and a high voltage to be relatively large.

There is therefore a need for a MOSFET transistor that, for example, consumes a relatively small area, can provide good drive performance and a low gate capacitance, and can handle relatively high drive voltages.

DETAILED DESCRIPTION

An embodiment of a prior art voltage regulator output driver10is shown inFIG. 1. It will be understood, however, that the driver10may be used in devices other than voltage regulators. The output driver10includes a PMOS transistor12having a source connected to a supply voltage VCCX, which may be an externally-supplied, unregulated supply voltage. A drain of the transistor12is connected to an output terminal14, which provides a regulated supply voltage VCCR. The drain of the transistor12is also connected to ground through a pair of resistors16,18, which form a voltage divider20having an output node22. Thus, the voltage output by the voltage divider20is a fixed percentage of the voltage VCCR. The output node22is connected to the “+” input of a opamp26, which receives a reference voltage VREF at its “−” input. The output of the opamp26is connected to a gate of the transistor12to adjust the gate voltage as a function of a comparison of the voltage from the voltage divider20and the output voltage VCCR. The gate voltage is therefore adjusted to maintain the output voltage VCCR at a preset voltage.

In operation, if the output voltage VCCR falls below the preset voltage, the voltage output by the voltage divider20correspondingly decreases. As a result, the voltage output by the −opamp26increases to decrease the gate-to-source voltage of the transistor12. This decreased gate-to-source voltage causes the output voltage VCCR to decrease back to the preset voltage. Conversely, if the output voltage VCCR increases, the voltage output by the voltage divider20correspondingly increases. The opamp26then decreases to increase the gate-to-source voltage of the transistor12to causes the output voltage VCCR to increase back to the preset voltage.

Although the output driver10can adequately regulate a supply voltage, it suffers from a number of disadvantages. As explained above, insofar as the driver10is used as a voltage regulator, it may be required to supply a substantial current to circuitry (not shown) to which it is supplying the voltage VCCR. As a result, the transistor12must generally have a large channel width, which can consume a substantial amount of area of a semiconductor die. Additionally, the operating speed of the output driver10, i.e., its ability to respond to rapid changes in the load driven by the transistor12, may be unduly slow because of the relatively large gate capacitance resulting from the large channel width. While the channel width could be reduced by making the gate insulation of the transistor12thinner, doing so can over-stress the transistor if, for example, the opamp26is too slow to respond to changes in VCCR. For example, when the supply voltage VCCX is initially applied to the output driver10, the voltage at the output of the opamp26may be at zero volts. As a result, the full magnitude of VCCX will be applied between the source and gate of the transistor12until the opamp26becomes operational. This high gate-to-source voltage can easily damage the transistor12if it has a thin gate insulation layer.

Even if the output driver10can be designed to avoid over-stressing the transistor12on power-up, it can still be over-stressed during normal use as the load driven by the driver10increases, as shown inFIG. 2.FIG. 2shows the magnitude of the gate voltage Vg with several values of process and temperature corners at a supply voltage VCCX equal to 2.0V. With reference toFIG. 2, for a “no load” condition, the gate voltage Vg will be equal to VCCX less the threshold voltage Vth, which is shown inFIG. 2as being 1.4 volts. As the load increases, the gate voltage Vg will decrease to maintain the regulated voltage VCCR at the preset level. As the load continues to increase, the gate voltage Vg continues to decrease until it reaches 0 volts. At this point, the full magnitude of the supply voltage VCCX will be applied between the source and the gate of the transistor12.

A voltage regulator output driver30according to one embodiment of the invention is shown inFIG. 3. The output driver30uses the output driver10ofFIG. 1, but includes a limiting circuit32for limiting the magnitude of the gate-to-source voltage of the transistor12. Specifically, the limiting circuit32includes a second comparator34for comparing the gate voltage Vg to a reference voltage Vrly_ref. The output of the comparator34drives a control circuit38that affects the operation of the output driver10if the gate voltage Vg falls sufficiently below the reference voltage Vrly_ref, thereby causing the comparator34to output an increased voltage Vglow. For example, in response to an increased value Vglow, the control circuit38may drive the gate voltage Vg higher. Alternatively, the control circuit38may reduce the load on the output driver30. Other means of keeping the gate voltage Vg at an acceptable level responsive to the voltage Vglow may also be used.

Although the output driver30shown inFIG. 3is effective in preventing the gate-to-source voltage from increasing beyond a certain level, it is not without its limitations. One disadvantage is that the area of a semiconductor die occupied by the comparator34may undesirably increase the cost of devices using the output driver30. Additionally, the comparator34will consume bias current, thereby increasing the power consumption of a device using the output driver30. Minimizing the bias current may reduce the operating speed of the comparator34so it may fail to limit the gate-to-source voltage quickly enough to avoid damaging the output transistor12. Finally, when the gate voltage Vg is too low, the comparators26,34may counteract each other in an unstable manner so that the magnitude of the regulated output voltage VCCR may oscillate.

An output driver40according to another embodiment of the invention that avoids the potential problems with the output driver30is shown inFIG. 4. The output driver40again uses the prior art output driver10shown inFIG. 1. However, the output driver40includes a clamp circuit44that limits the gate voltage Vg relative to the unregulated supply voltage VCCX. In the embodiment shown inFIG. 4, the clamp circuit44includes an NMOS clamp transistor46receiving the unregulated supply voltage VCCX at its drain and a reference voltage VClampREF at its gate. A source of the transistor46is connected to the gate of the transistor12.

In operation, the clamp transistor46remains non-conductive as long as the gate voltage Vg is greater than the supply voltage VCCX less the threshold voltage VTH(46) of the transistor46. However, if the gate of the gate voltage Vg attempts to drop below that voltage, the transistor46starts to turn ON to supply current to the gate of the transistor12to prevent the gate voltage Vg from further decreasing. As a result, the minimum gate voltage Vgmin of the transistor12is VClampREF−VTH(46). In this manner, the gate-to-source voltage of the transistor12is limited to a level that avoids damaging the transistor12, as shown inFIG. 5.FIG. 5shows the magnitude of the gate voltage Vg with several values of process and temperature corners at a supply voltage VCCX equal to 2.0V. When the load increases, the gate voltage Vg decreases to maintain the regulated output voltage VCCR relatively constant. The decreasing gate voltage Vg causes the gate-to-source voltage Vgs to increase. When the gate voltage Vg reaches about 700 mv, corresponding to a gate-to-source voltage Vgs of about 1.3 v, the transistor46starts to turn ON to supply current to the gate of the transistor12. As a result, as shown inFIG. 5, the gate voltage Vg is limited to about 0.5 volt, and the gate-to-source voltage Vgs is limited to about 1.5 volts. As a result, the transistor12is protected from being over-stressed even though the transistor12may use a gate insulation layer that is relatively thin. The thin gate insulation allow the channel width to be small, such as a channel width-to-length ratio of 5,000/1.6, thereby minimizing the size of the area consumed by the output driver40and the gate capacitance of the transistor46.

The challenge to implementing the output driver40shown inFIG. 4is providing a clamp reference voltage VClampREF that is correct despite process variations and variations in the temperature of the output driver40. For example, if the VClampREF is held constant and the threshold voltage Vth of the clamp transistor46varies with process variations or temperature, the minimum gate voltage Vgmin of the output transistor12may vary accordingly. As a result, the gate-to-source voltage Vgs may become excessive, thereby damaging the transistor12.

One embodiment of a reference voltage generator circuit50for providing the correct clamp reference voltage VclampREF is shown inFIG. 6. The circuit50includes several current paths, the first of which includes a PMOS transistor54coupled in series with an NMOS transistor56between a supply voltage VCC and ground. The PMOS transistor54is biased ON by ground potential being applied to its gate, and the NMOS transistor56is diode-connected to pass a current I1. The transistor56is connected as a current mirror with a second NMOS transistor60that is connected in series with a PMOS transistor62between the unregulated supply voltage VCCX and ground. The transistor60therefore conducts a current I2that is equal to the current I1, and a voltage V2at the drain of the transistor60is equal to a voltage V1at the drain of the transistor56. As a result, the gate-to-source voltage Vgs of the transistor54is equal to the gate-to-source voltage Vgs of the transistor62, i.e., Vgs(54)=Vgs(62). Insofar as Vgs(54)=VCC and Vgs(62)=VCCX−V3. Therefore, VCC=VCCX−V3, which can be rewritten as:
V3=VCCX−VCC[Equation 1].

The voltages V1and V2are applied to the inputs of a opamp64, which generates the clamp reference voltage VClampREF at its output. The output of the opamp64is also applied to a gate of an NMOS transistor66, which is connected in series with a second NMOS transistor68between VCCX and ground to conduct a bias current Ibias. The transistor68, is, in turn, connected as a current mirror with an NMOS transistor70that is connected in series with a resistor72between VCC and ground. As a result, a bias current Ibias conducted by the transistor68is set by the resistor72and transistor70. The feedback loop formed by the opamp64and transistors66,62regulate VClampREF so that V3accurately tracks the threshold voltage VTH(46) of the clamp transistor46as it varies responsive to process and temperature variations. For example, if the threshold voltages increase, then V3will decrease, which will cause the PMOS transistor62to reduce V2. The opamp64will increase the magnitude VClampREF accordingly to maintain the transistors46,66at the same operation point as prior to the increase in the threshold voltages.

When the bias current Ibias is relatively small, the gate-to-source voltage Vgs(66) of the transistor66is substantially equal to the threshold voltage VTH(66) of the transistor66. As a result:
VClampREF=V3+VTH(66)  [Equation 3].

As also explained above, Vgmin of the transistor12is given by the equation:
Vgmin=VClampREF−VTH(46).  [Equation 5].

If the threshold voltage VTH(66) of the transistor66can be made equal to the threshold voltage VTH(46) of the clamp transistor46, then Equation 6 can be reduced to:
Vgmin=VCCX−VCC[Equation 7].

As a result, the maximum gate-to-source voltage Vgs of the transistor12will be VCC. Therefore, the maximum gate-to-source voltage Vgs of the transistor12should be insensitive to process and temperature variations as well as to variations in the magnitude of the unregulated supply voltage VCCX.

The operation performance of the output driver40using the reference voltage generator circuit50is shown inFIG. 7, which can be contrasted against the performance shown inFIG. 2of the prior art output driver10.FIG. 7shows the magnitude of the gate voltage Vg with several values of process and temperature corners at a supply voltage VCCX equal to 2.0V. As shown inFIG. 7, the gate voltage Vg of the transistor12is limited to about 0.5 volt. As a result, the gate-to-source voltage Vgs of the transistor12is limited to about 1.5 volts. Moreover, the variations in the gate voltage Vg of the transistor12is relatively insensitive to process and temperature variations, as shown by the close spacing between the graphs shown inFIG. 7.

The ability of the output driver40shown inFIG. 4using the reference voltage generator circuit50is shown inFIG. 7to regulate the output voltage VCCR compared to the prior art output driver10shown inFIG. 1is illustrated inFIG. 8.FIG. 8shows a substantial increase in load at about 200 ns, as shown in the bottom graph ofFIG. 8. As shown in the next to the bottom graph ofFIG. 8, the magnitude of the output voltage VCCR varies substantially in response to the load increase at each of several process and temperature variations shown inFIG. 8. In contrast, as shown by the upper graph inFIG. 8, the magnitude of the output voltage VCCR varies to a substantially smaller degree responsive to the load increase at the same process and temperature variations shown inFIG. 8. Therefore, the output driver40should provide superior performance by using the output transistor46having a thin gate insulation.

A flash memory device100that includes one or more of the supply voltage regulators shown inFIG. 3or4and6, or a voltage regulator according to some other embodiment of the invention, is shown inFIG. 9. Although a supply voltage regulator according to various embodiments of the invention is shown inFIG. 9and explained in the context of the flash memory device100, it should be understood that they can be used in other devices. Specifically, the supply voltage regulators shown inFIG. 3or4and6, or a voltage regulator according to some other embodiment of the invention, can be used in other types of integrated circuits such as dynamic random access memory devices or processors, to name just two. With reference toFIG. 9, the flash memory device100includes an array130of flash memory cells arranged in banks of rows and columns. Most command signals, the address signals and the write data signals are applied to the memory device100as sets of sequential input/output (“I/O”) signals transmitted through an I/O bus134. Similarly, read data signals are output from the flash memory device100through the I/O bus134. The I/O bus is connected to an I/O control unit140that routes the signals between the I/O bus134and an internal data bus142, an internal address bus144, and an internal command bus146. The flash memory device100also includes a control logic unit150that receives a number of control signals either externally or through the command bus146to control the operation of the memory device100. The address bus144applies row address signals to a row decoder160and column address signals to a column decoder164. Similarly, the column decoder164enables write data signals to be applied to bit lines for columns corresponding to the column address signals and allows read data signals to be coupled from bit lines for columns corresponding to the column address signals.

In response to the memory commands decoded by the control logic unit150, the flash memory cells in the array130are erased, programmed, or read. The memory array130is programmed on a row-by-row or page-by-page basis. After the row address signals have been applied to the address bus144, the I/O control unit140routes write data signals to a cache register170. The write data signals are stored in the cache register170in successive sets each having a size corresponding to the width of the I/O bus134. The cache register170sequentially stores the sets of write data signals for an entire row or page of flash memory cells in the array130. All of the stored write data signals are then used to program a row or page of memory cells in the array130selected by the row address coupled through the address bus144. In a similar manner, during a read operation, data signals from a row or page of memory cells selected by the row address coupled through the address bus144are stored in a data register180. Sets of data signals corresponding in size to the width of the I/O bus134are then sequentially transferred through the I/O control unit140from the data register180to the I/O bus134.

All of the components of the flash memory device100are powered by a voltage regulator190, which may be the supply voltage regulator shown inFIG. 3or4and6, or a voltage regulator according to some other embodiment of the invention. As explained above, the voltage regulator190receives an external supply voltage, which may be unregulated, and it outputs a regulated supply voltage VCCR. The regulated voltage VCCR may be used to power all of the components of the memory device100or it may be used to power only some of the components, such as programming circuits that must impart a specific charge to memory cells in the array130. Although the voltage regulator190is described herein in the context of a flash memory device, it will be understood that it may advantageously be used in other types of memory devices and in other types of integrated circuits other than memory devices.

FIG. 10is a block diagram of a processor-based system200including processor circuitry202having a volatile memory210ofFIG. 9. The processor circuitry202is coupled through address, data, and control buses to the volatile memory210to provide for writing data to and reading data from the volatile memory210. The processor circuitry202includes circuitry for performing various processing functions, such as executing specific software to perform specific calculations or tasks. The processor-based system200also includes one or more input devices204coupled to the processor circuitry202to allow an operator to interface with the processor-based system200. Examples of input devices204include keypads, touch screens, and scroll wheels. The processor-based system200also includes one or more output devices206coupled to the processor circuitry202to provide output information to the operator. In one example, the output device206is a visual display providing visual information to the operator. Data storage208is also coupled to the processor circuitry202to store data that is to be retained even when power is not supplied to the processor-based system200or to the data storage208. The flash memory device100, or a flash memory device according to some other example of the invention, can be used for the data storage208.