Flash memory device and controlling method thereof

A flash memory device and a controlling method are provided. The flash memory device includes a memory array, an in-place update module, an out-of-place update module and a latency-aware module. The in-place update module is used for performing a program procedure or a garbage collection procedure via a bit erase operation or a page erase operation on the memory array. The out-of-place update module is used for performing the program procedure or the garbage collection procedure via a block erase operation or a migration operation on the memory array. The latency-aware module is used for determining a relationship between a first overhead of the in-place update module and a second overhead of the out-of-place update module.

TECHNICAL FIELD

The disclosure relates in general to a memory device and a controlling method thereof, and more particularly to a flash memory device and a controlling method thereof.

BACKGROUND

Along with the development of the memory technology, various memories are invented. Flash memory device is an electronic (solid-state) non-volatile memory that can be electrically erased and reprogrammed. The limitation of the traditional flash memory device is that, although it can be read or programmed a page at a time in a random access fashion, it can be erased only a block at a time. This generally sets all bits in the block to 1. Starting with a freshly erased block, any location within that block can be programmed. However, once a bit has been set to 0, it can be changed back to 1 only by erasing the entire block, i.e. block erase operation.

Please refer toFIG. 1, which shows a garbage collection procedure of a traditional flash memory device. Due to the block erase operation, one invalid page (or called used page) in one block cannot be individually erased to be a free page. So, the valid pages in this block are needed to be migrated and then this entire block is erased to create free pages. Frequently migration and erase may cause latency and endurance issues.

SUMMARY

The disclosure is directed to a flash memory device and a controlling method thereof. A novel Flash Translation Layer (FTL) having a latency-aware program mechanism, a latency-aware garbage collection mechanism, a cyclic endurance spreading mechanism and a hot-data-aware fine-granularity mechanism is provided to exploit a bit erase operation or a page erase operation of a bit-alterable flash memory array for resolving the latency and endurance issues.

According to one embodiment, a flash memory device is provided. The flash memory device includes a memory array, an in-place update module, an out-of-place update module and a latency-aware module. The in-place update module is used for performing a program procedure or a garbage collection procedure via a bit erase operation or a page erase operation on the memory array. The out-of-place update module is used for performing the program procedure or the garbage collection procedure via a block erase operation or a migration operation on the memory array. The latency-aware module is used for determining a relationship between a first overhead of the in-place update module and a second overhead of the out-of-place update module.

According to another embodiment, a controlling method of a flash memory device is provided. The flash memory device includes a memory array, an in-place update module, an out-of-place update module and a latency-aware module. The controlling method includes the following steps. A relationship between a first overhead of the in-place update module and a second overhead of the out-of-place update module is determined by the latency-aware module.

DETAILED DESCRIPTION

Please refer toFIG. 2, which shows a flash memory device1000according to one embodiment. The flash memory device1000includes a file system100, a flash translation layer (FTL)200, a memory technology device (MTD)300and a memory array400. The memory array400is a bit-alterable flash memory array, which may be a NAND memory, a NOR memory, a 3D memory, a PCM or a ReRAM.

Please refer toFIGS. 3A to 3B, which illustrate operations of a bit-alterable flash memory array. In the bit-alterable flash memory array, +FN hole injection and −FN electron injection are used for programming and erasing. As shown inFIG. 3A, after programing some bits of the bit-alterable flash memory array and erasing some bits of the bit-alterable flash memory array, two different voltage distributions are formed. As shown inFIG. 3B, while the block is erased, all of the bits are “1.” Then, some of the bits in this block can be programed to be “0.” Next, some of the bits in this block can be erased to be “1.” That is to say, the bit-alterable flash memory array can perform a bit erase operation (or a page erase operation).

Please refer toFIG. 4, which illustrates a garbage collection procedure via the page erase operation. In the page erase operation, one invalid page (or called used page) in one block can be individually erased to be a free page. The valid pages in this block are not needed to be migrated and only part of this block is erased to create free pages. The migration operation is omitted and the overhead is reduced.

As illustrated above, the memory array400of the flash memory device1000shown inFIG. 2is a bit-alterable flash memory array. The program procedure and the garbage collection procedure can be performed via the bit erase operation, the page erase operation or the block erase operation. For efficiently executing the program procedure and the garbage collection procedure, a bit-alterable-aware management unit210is provided in the flash translation layer200. As shown inFIG. 2, the bit-alterable-aware management unit210includes a hot-data-aware module211, a latency-aware module212, an in-place update module213, an out-of-place update module214and a spreading module215. The bit-alterable-aware management unit210, the hot-data-aware module211, the latency-aware module212, the in-place update module213, the out-of-place update module214and the spreading module215may be a circuit, a chip, a circuit board, program codes, or storage device storing program codes. Those elements are illustrated as follows.

Please refer toFIG. 5, which shows a flowchart of a latency-aware program mechanism of the controlling method of the flash memory device1000. In step S510, the latency-aware module212determines whether a first overhead of the program procedure performed by the in-place update module213is less than a second overhead of the program procedure performed by the out-of-place update module214. If the first overhead is less than the second overhead, the process proceeds to step S520; if the first overhead is not less than the second overhead, the process proceeds to step S530.

In step S520, the in-place update module213performs the program procedure via the bit erase operation or the page erase operation on the memory array400. For example, please refer toFIG. 6, which illustrates the program procedure performed via the page erase operation. In this example, “LBA2” in page PN-1is needed to be replaced by “LBA2*.” Before performing the program procedure, pages P0, P2, P3, P4, . . . are invalid pages, and pages P1, PN-1, PN are valid pages. After performing the program procedure, the page PN-1in this block BKA is erased and then “LBA2*” is written in the page PN-1in this block BKA.

In step S530, the out-of-place update module214performs the program procedure via the block erase operation or the migration operation on the memory array400. Please refer toFIG. 7, which illustrates the program procedure performed via the migration operation. In this example, “LBA2” in page PN-1is needed to be replaced by “LBA2*.” Before performing the program procedure, pages P0, P2, P3, P4, . . . are invalid pages, pages P1, PN-1are valid pages and page PN is a free page. After performing the program procedure, the page PN-1in this block BKA is read out and then “LBA2*” is written in the page PN in this block BKA. The page PN-1becomes an invalid page and the page PN become a valid page.

Please refer toFIG. 8, which shows a flowchart of a latency-aware garbage collection mechanism of the controlling method of the flash memory device1000. In step S810, the latency-aware module212determines whether a first overhead of the garbage collection procedure performed by the in-place update module213is less than a second overhead of the garbage collection procedure performed by the out-of-place update module214. If the first overhead is less than the second overhead, the process proceeds to step S820; if the first overhead is not less than the second overhead, the process proceeds to step S830.

In step S820, the in-place update module213performs the garbage collection procedure via the bit erase operation or the page erase operation on the memory array400. For example, please refer toFIG. 9, which illustrates the garbage collection procedure performed via the page erase operation. In this example, the space of the invalid pages is needed to be released. Before performing the garbage collection procedure, pages P0, P2, P3, P4, . . . , PN are invalid pages, and pages P1, PN-1are valid pages. After performing the garbage collection procedure, the pages P0, P2, P3, P4, . . . , PN in this block BKA are erased to be free pages and the pages P1, PN-1are kept at the same block BKA.

In step S830, the out-of-place update module214performs the garbage collection procedure via the block erase operation or the migration operation on the memory array400. Please refer toFIG. 10, which illustrates the garbage collection procedure performed via the migration operation and the block erase operation. In this example, the space of the invalid pages is needed to be released. Before performing the garbage collection procedure, pages P0, P2, P3, P4, . . . , PN are invalid pages, and pages P1, PN-1are valid pages. After performing the garbage collection procedure, the pages P1, PN-1in this block BKA are migrated to another block BKB and whole of the block BKA is erased.

Please refer toFIGS. 11 and 12.FIG. 11shows a flowchart of a cyclic endurance spreading mechanism of the controlling method of the flash memory device1000.FIG. 12illustrates the steps inFIG. 11. In step S111, the spreading module215determines whether an access counter is larger than a threshold. If the access counter is larger than the threshold, the process proceeds to step S112; if the access counter is not larger than the threshold, the process returns to step S111.

In step S112, the spreading module215resets a base pointer BP. For example, as shown inFIG. 12, the pages P0includes cache lines CL0to CLN. The base pointer BP is moved from the first physical row to the second physical row.

In step S113, the spreading module215reallocates data according to the base pointer BP. For example, as shown inFIG. 12, the data in the cache line CL0is moved from the first physical row to the second physical row according to the base pointer BP.

As shown inFIG. 12, the base pointer BP is cyclically moved, such that the endurance is spread among all of the cache lines CL0to CLN.

Please refer to FIS.13and Table I.FIG. 13shows a flowchart of a hot-data-aware fine-granularity mechanism of the controlling method of the flash memory device1000. Table I is a Hash table whose data is searched by a hash function, such as mod4. In step S131, the hot-data-aware module211determines whether a page is recently accessed. If the page is recently accessed, the process proceeds to step S132; if the page is not recently accessed, the process proceeds to step S133.

In step S132, the hot-data-aware module211sets a hash bit of this page to 1. In step S132, the hot-data-aware module211sets the hash bit of this page to 0.

According to the embodiments descried above, a novel Flash Translation Layer (FTL) having the latency-aware program mechanism, the latency-aware garbage collection mechanism, the cyclic endurance spreading mechanism and the hot-data-aware fine-granularity mechanism is provided to exploit the bit erase operation or the page erase operation of the bit-alterable flash memory array for resolving the latency and endurance issues.