AMPLIFIER HAVING TRANSCONDUCTANCE ATTENUATION

An error amplifier includes a first transistor having a first error amplifier input and having first and second current terminals, a second transistor having a second error amplifier input and having third and fourth current terminals, a first resistor coupled between a supply voltage terminal and the first current terminal, and a second resistor coupled between the supply voltage terminal and the third current termina. The error amplifier has a second stage circuit coupled to the first and second resistors. The second stage circuit has an error amplifier output. The second stage circuit is configured to cause less current to flow through the second stage circuit than a current that flows through either of the first or second resistors or the first or second transistors.

CROSS REFERENCE TO RELATED APPLICATION

This application claims priority to India provisional patent application No. 202241053653 entitled “Ultra-Low Noise Amplifier With Tunable Unity-Gain Bandwidth Using Transconductance Attenuation,” incorporated herein by reference.

BACKGROUND

A voltage regulator is a circuit that produces an output voltage that is regulated to a target value (within a specified level of output voltage ripple). One type of voltage regulator is a “low drop-out” (LDO) voltage regulator in which an error amplifier amplifies the difference between the output voltage and a reference voltage to produce an error signal. The error signal is coupled to a gate of a field effect transistor (FET). The FET may be a p-channel FET (PFET). The source of the PFET may be coupled to the input voltage. By controlling the gate voltage of the PFET, the gate-to-source voltage (Vgs) of the PFET is controlled to maintain a current magnitude through the PFET to a load. If the output voltage increases, the error signal increases as well, thereby decreasing the PFET's Vgs, which in turn decreases the load current, and the output voltage decreases. Similarly, if the output voltage decreases, the error signal decreases, thereby increasing the PFET's Vgs, which in turn increases the load current, and the output voltage increases.

SUMMARY

An error amplifier includes a first transistor having a first error amplifier input and having first and second current terminals, a second transistor having a second error amplifier input and having third and fourth current terminals, a first resistor coupled between a supply voltage terminal and the first current terminal, and a second resistor coupled between the supply voltage terminal and the third current termina. The error amplifier has a second stage circuit coupled to the first and second resistors. The second stage circuit has an error amplifier output. The second stage circuit is configured to cause less current to flow through the second stage circuit than a current that flows through either of the first or second resistors or the first or second transistors.

DETAILED DESCRIPTION

The same reference numbers or other reference designators are used in the drawings to designate the same or similar (either by function and/or structure) features.

FIG.1is a schematic diagram of a voltage regulator100. In this example, the voltage regulator is an LDO voltage regulator including an error amplifier110, a buffer120, a transistor130, a capacitor CC, a current source circuit I_REF, resistor R_REF, and capacitor C_REF. A load150receives an output voltage VOUT form the voltage regulator100. The load150can be modeled as a resistance RLOAD in parallel with a capacitance CLOAD.

In this example, the transistor130is a PFET. The current, ILOAD, to the load150passes through the transistor130. The transistor130may be referred to as a “pass-FET,” and is referred to herein as pass-FET130. The source of the pass-FET130is coupled to the input supply voltage, Vdd. The drain of the pass-FET is coupled to the load150. The voltage on the drain of the pass-FET130is VOUT.

The error amplifier110includes a negative (inverting, −) input and a positive (non-inverting, +) input. The output voltage VOUT is coupled to the positive input of the error amplifier110. The current source circuit I_REF produces a fixed current (also called I_REF). The current source circuit I_REF is coupled to the parallel combination of resistor R_REF and capacitor C_REF. Current I_REF charges capacitor C_REF to a fixed voltage, VREF. The negative input of the error amplifier110receives the reference voltage VREF. The capacitor CC is coupled between the drain of pass-FET130and an internal terminal within the error amplifier110. Capacitor CC is a compensation capacitor.

The error amplifier110amplifies the difference between VOUT and VREF. The output signal from the error amplifier110is an error signal designated EAMPHIZ. Error signal EAMPHIZ is proportional to the difference between VOUT and VREF. Error signal EAMPHIZ is provided to an input of buffer120. Buffer120may convert EAMPHIZ to a voltage suitable for driving the gate of the pass-FET130. As VOUT increases, the magnitude of EAMPHIZ also increases. An increasing EAPHIZ causes the Vgs of the pass-FET to decrease, thereby causing the magnitude of ILOAD to decrease to the load150, and VOUT decreases in response. A decreasing EAPHIZ causes the Vgs of the pass-FET to increase, thereby causing the magnitude of ILOAD to increase to the load150, and VOUT increases in response.

In one embodiment, the error amplifier110, buffer120, pass-FET130, capacitor CC, and current source circuit I_REF are fabricated on a semiconductor die105, and resistor R_REF and capacitor C_REF are external to the semiconductor die105. The load150is external to the semiconductor die105as well. In other embodiments resistor R_REF and capacitor C_REF may be fabricated on the same semiconductor die105as the error amplifier110, buffer120, pass-FET130, capacitor CC, and current source circuit I_REF.

FIG.2is a schematic of an error amplifier210, which can be used to implement error amplifier110in the LDO100ofFIG.1. Error amplifier210includes multiple stages. A first stage includes a bias current source (BIAS and an input pair of transistors Q1and Q2. A second stage includes resistors RT1, RT2, RB1, and RB2, and transistors MP1, MP2, MP_CAS1, MP_CAS2, MN_CAS1, MN_CAS2, MN1, and MN2. In this example, transistors Q1and Q2are NPN bipolar junction transistors (BJTs), and the transistors of the second stage are field effect transistors (FETs). Transistors MP1, MP2, MP_CAS1, and MP_CAS2are p-channel FETs (PFETs), and transistors MN_CAS1, MN_CAS2, MN1, and MN2are n-channel FETs (NFETs).

The inputs to the first stage transistors are the bases of transistors Q1and Q2. The base of transistor Q1is coupled to VOUT. The base of transistor Q2is VREF. The emitters of transistors Q1and Q2are coupled together and to current source (BIAS. The current IBIAS (′IBIAS' refers both to the circuit that produces the current as well as the magnitude of that current) divides between transistors Q1and Q2based on the relative magnitude of the voltages on the bases (VOUT versus VREF). If the voltage VOUT is larger than the voltage VREF, then more of the bias current (BIAS flows through transistor Q1than through transistor Q2. Conversely, if the voltage VREF is larger than the voltage VOUT, then more of the bias current (BIAS flows through transistor Q2than through transistor Q1. Current I1represents the currents that flow through the transistors Q1and Q2.

In the second stage, resistor Rt1, transistors MP1, MP_CAS1, MN_CAS1, and MN1, and resistor RB1are coupled in series between Vdd and ground. Similarly, resistor Rt2, transistors MP2, MP_CAS2, MN_CAS2, and MN2, and resistor RB2are coupled in series between Vdd and ground. A bias voltage VBIAS3is coupled to the gates of transistors MP1and MP2. A bias voltage VBIAS2is coupled to the gates of transistors MP_CAS1and MP_CAS2. A bias voltage VBIAS1is coupled to the gates of transistors MN1and MMN2. The gates of transistors MN1and MN2are coupled together and to the drain of transistor MN_CAS1. Capacitor CC is coupled between VOUT and the drain of transistor MN2. The drains of transistors MP_CAS2and MN_CAS2are coupled together and provide the output voltage from the second stage to the input of buffer120.

The drain of transistor MP1is coupled to the source of transistor MP_CAS1and to the collector of transistor Q1. The drain of transistor MP2is coupled to the source of transistor MP_CAS2and to the collector of transistor Q2. The current that flows through the transistors of the second stage is identified as current I2. The configuration of the error amplifier210is such that current that flows through resistors RT1and RT2and transistors MP1and MP2is the sum of currents I1and I2. To decrease the noise produced by the first stage's input pair of transistors Q1and Q2, the IBIAS current can be increased. The increase in IBIAS increases11and thus also increases the sum of currents I1and I2. By increasing the current I1to decrease the noise of the first stage transistors Q1and Q2, the current through transistors MP1and MP2also increases. Transistors MP1and MP2are sized to accommodate the bias current IBIAS through transistors Q1and Q2. Further, to reduce flicker noise produced by transistors, MP1and MP2, their current densities should be reduced which means their size should be increased. Thus, transistors MP1and MP2are relatively large transistors to accommodate the bias current of the first stage as well as to reduce their own flicker noise.

Increasing bias current through the input pair of transistors Q1and Q2causes an increase in the transconductance (gm) of the input pair of transistors. Also, the unity gain bandwidth (UGB) of the amplifier210is proportional to gm/CC. Accordingly, increasing the bias current through the input pair of transistors Q1and Q2causes an increase in the amplifier's UGB. The UGB may increase to the point that a non-dominant pole may be within the UGB thereby adding a second pole to the system. Such an additional pole causes the phase to roll-off at an increased rate of 90 degrees per decade at the frequency of the second. A more rapidly falling phase may result in the phase margin (the phase angle at which the gain is at 0 dB (unity gain)) being negative. A positive phase margin renders the system stable, but a negative phase margin renders the system unstable. Thus, an increase in the bias current through the input pair of transistors Q1and Q2causes less noise in the input pair but may increase the UGB and undesirably resulting in the phase margin being negative (unstable system).

FIG.3is a schematic of an error amplifier310, which also can be used to implement error amplifier110in the LDO100ofFIG.1. Error amplifier310includes multiple stages. Like error amplifier210, error amplifier310includes a first stage that has a bias current source IBIAS31and an input pair of transistors Q31and Q32. The error amplifier310also includes second stage circuits320and340. Resistor R31is coupled between Vdd and the collector of transistor Q31. Resistor R32is coupled between Vdd and the collector of transistor Q32.

Second stage circuit340is a cascode circuit coupled between the second stage circuit320and ground. The second stage circuit340includes transistors (NFETs) MN_CAS31, MN_CAS32and MN31and MN32, and resistors RB31and RB32. Resistors RB31and RB32couple between the sources of the respective transistors MN31and MN32and ground, as shown. The gates of transistors MN_CAS31and MN_CAS32are coupled to a bias voltage VBIAS31. The gates of transistors MN31and MN32are coupled together and to the drain of transistor MN_CAS31.

The second stage circuit320includes resistors R33and R34, transistors (PFETs) MP31and MP32, and a transconductance attenuator circuit328. The transconductance attenuator circuit328includes a negative input321and a positive input322. The negative input of the transconductance attenuator circuit328is coupled to the collector of transistor Q1and to resistor RT31. The negative input of the transconductance attenuator circuit328is coupled to the collector of transistor Q2and to resistor RT32. Resistor R33is coupled between the negative input of the transconductance attenuator circuit328and the source of transistor MP31. Resistor R34is coupled between the positive input of the transconductance attenuator circuit328and the source of transistor MP32. The transconductance attenuator circuit has outputs331and332which are coupled to the respective gates of transistors MP31and MP32, as shown.

The bias current IBIAS31that flows through the combination of transistors Q31and Q32flows through resistors RT31and RT32but does not also flow through the second stage circuit320. Accordingly, increasing the bias current through the input pair of transistors Q1and Q2to reduce the noise of those transistors does not also result in an increase in the current through the second stage circuit320. In one example, the bias current through transistors MP31and MP32is 40 microamperes whereas the bias current IBIAS31is 3 mA. Advantageously, transistors MP31and MP32can be smaller than transistors than MP1and MP2for the same amount of flicker noise and the thermal noise of transistors MP31and MP32will also be lower than the thermal noise of transistors MP1and MP2due to the lower bias current in the second stage circuit320, all else being equal. To lower the noise, the current through transistors Q31and Q32can be increased without further loading the second stage circuit320and increasing the thermal and flicker noise of transistors MP31and MP32.

Further, the PFETs MP31and MP32function as a pseudo input pair, and the LDO's UGB is proportional to A*gm2/CC, where gm2 is the transconductance of transistors MP31and MP32, A is the gain of the first stage. The first stage gain A=gm1* RT31, where gm1 is the transconductance of transistors Q1and Q2. The transconductance of BJTs is proportional to the current through the BJT. The transconductance of a FET (e.g., MP31, MP32) is proportional to the square root of its drain current. The bias current through the transistors MP31and MP32is much smaller than the bias current through transistors Q31and Q32and thus gm2 is substantially smaller than gm1. Accordingly, the UGB of the error amplifier310is advantageously substantially smaller than the UGB of error amplifier210, and any non-dominant poles are not likely to be outside the UGB of error amplifier310. As a result, error amplifier310is more likely to be stable and have significantly less overall noise than for error amplifier210.

The transconductance attenuator328has a gain of Ap, which is a value greater than 1. The transconductance attenuator328causes the effective gm2 to be scaled by a factor of (1−Ap). Accordingly, the effective transconductance (gm2eff) of the second stage circuit320is gm2eff=gmp*(1−Ap), where gmp is the transconductance of the transistors MP31and MP32. Because the value Ap is less than 1, the effective transconductance, gm2eff, is less than the actual transconductance of the of transistors MP31and MP32. The transconductance attenuator328also helps to reduce of the LDO noise while increasing stability by having higher current in the first stage (transistors Q31and Q32) than in the second stage circuit and increasing the gain of the first stage. Increasing the gain of the first stage divides the noise resulting from the second stage circuit320while maintaining the UGB by tuning the gain Ap of the transconductance attenuator and lowering the value of gm2eff. The tunability of the gain Ap of the transconductance attenuator328is described below with respect toFIG.4.

The example error amplifier310ofFIG.3is more likely to be stable and have significantly less overall noise than for error amplifier210. In one example, the UGB of error amplifier is 2 MHz and has an overall noise value of 0.45 microvolts rms (root mean square).

FIG.4is a schematic of transconductance attenuator428, which can be used to implement the transconductance attenuator328ofFIG.3. In this example, transconductance attenuator428includes input transistors (NPN BJTs)041and Q42whose bases are the transconductance attenuator's inputs321and322. The transconductance attenuator428also includes transistors MN41and MN42(NFETs), resistors R41, R42, R43, R44, and RT41, and current sources IBIAS41, IBIAS42, and IBIAS43.

Resistor RT41couples to the source of transistor MP_B to form a bias voltage circuit435. Resistor R43, transistor MN41, and resistor R41are coupled in series between the bias voltage circuit435and current source IBIAS43. Similarly, resistor R44, transistor MN42, and resistor R42are coupled in series between the bias voltage circuit435and current source IBIAS43. Current sources IBIAS41and IBIAS42provide a bias current through the transistors Q41and Q42. The collectors of transistors Q41and Q42coupled to Vdd. The emitter of transistor Q41is coupled to the gate of transistor MN41, and the emitter of transistor Q42is coupled to the gate of transistor MN42. Transistors Q41and Q42function as emitter-followers in which their emitter voltage follows the magnitude of their base voltage (1*Vbe below the base voltage). The resistances of resistors R43and R44is approximately the same. Similarly, the resistances of resistors R41and R42is approximately the same. The outputs331and333are taken from the drains of transistors MN41and MN42as shown. The gain of the transconductance attenuator428(e.g., voltage on output331divided by voltage on input321) is proportional to product of the resistance of resistor R43and the transconductance of transistor MN41(which is degenerated by resistor R41).

The tunability of the gain of the transconductance attenuator428depends upon the effective transconductance of transistors MN41and MN42, which are degenerated by corresponding resistors R41and R42. The effective transconductance is a function of the resistance of resistors R41and R42and the resistance of resistors R43and R44. The gain Ap of the transconductance amplifier428is proportional to the ratio of the resistance of resistor R43(or R44) to the resistance of resistor R41(or R42). The gain Ap can be tuned by changing resistor R43(R44) and/or resistor R41(R42) so that the aforementioned ratio is changed. Accordingly, the UGB of the error amplifier310can be tuned. In one embodiment, resistors R43/R44and/or resistors R41/R42are trimmable (e.g., multiple resistors coupled in series with corresponding switches controlled by a trim code).

Resistor R55couples to the source of transistor MP51to form a bias voltage circuit535. Resistor R56couples to the source of transistor MP52to form a bias voltage circuit536. Current source IBIAS53provides a bias current through the bias voltage circuit535. Current source IBIAS54provides a bias current through the bias voltage circuit536. The outputs331and332are the drains of the respective transistors MP51and MP52.

Resistor R53, transistor MN51, and resistor R52are coupled in series between resistor RT51and current source IBIAS55. Similarly, resistor R54, transistor MN52, and resistor R52are coupled in series between resistor RT51and current source IBIAS55. Current sources IBIAS51and IBIAS52provide the bias current through the transistors Q51and Q52. The collectors of transistors Q51and Q52coupled to Vdd. The emitter of transistor Q51is coupled to the gate of transistor MN51, and the emitter of transistor Q52is coupled to the gate of transistor MN52. Transistors Q41and Q42function as emitter-followers in which their emitter voltage follows the magnitude of their base voltage (1*Vbe below the base voltage). The resistances of resistors R53and R54is approximately the same. Similarly, the resistances of resistors R51and R52is approximately the same. The gain of the transconductance attenuator528is proportional to the product of the resistance of resistor R53and the transconductance of transistor MN51(which is degenerated by resistor R51).

The value of Vdd for transconductance attenuator428is higher than for transconductance attenuator528due to the extra headroom required to accommodate the bias voltage circuit435. However, because transconductance attenuator528has an extra bias voltage circuit with respect to transconductance attenuator428, the total noise produced by transconductance attenuator428will be lower than the noise produced by transconductance attenuator528.

Also, in this description, the recitation “based on” means “based at least in part on.” Therefore, if X is based on Y, then X may be a function of Y and any number of other factors.

While the use of particular transistors are described herein, other transistors (or equivalent devices) may be used instead with little or no change to the remaining circuitry. For example, a field effect transistor (“FET”) (such as an n-channel FET (NFET) or a p-channel FET (PFET)), a bipolar junction transistor (BJT—e.g., NPN transistor or PNP transistor), insulated gate bipolar transistors (IGBTs), and/or junction field effect transistor (JFET) may be used in place of or in conjunction with the devices disclosed herein. The transistors may be depletion mode devices, drain-extended devices, enhancement mode devices, natural transistors or other types of device structure transistors. Furthermore, the devices may be implemented in/over a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN) or a gallium arsenide substrate (GaAs).

References may be made in the claims to a transistor's control input and its current terminals. In the context of a FET, the control input is the gate, and the current terminals are the drain and source. In the context of a BJT, the control input is the base, and the current terminals are the collector and emitter.

References herein to a FET being “on” means that the conduction channel of the FET is present and drain current may flow through the FET. References herein to a FET being “off” means that the conduction channel is not present and drain current does not flow through the FET. An “off” FET, however, may have current flowing through the transistor's body-diode.

Uses of the phrase “ground” in the foregoing description include a chassis ground, an Earth ground, a floating ground, a virtual ground, a digital ground, a common ground, and/or any other form of ground connection applicable to, or suitable for, the teachings of this description. In this description, unless otherwise stated, “about,” “approximately” or “substantially” preceding a parameter means being within +/−10 percent of that parameter.