System, circuit, and method for edge detection in a binary optical code

Systems better detect transitions in a binary optical code signal and thus better detect edges in binary optical codes, such as bar codes. The optical code signal imperfectly indicates perceived regions of relatively dark and light areas arranged in an alternating pattern as part of an optical code. That signal is differentiated to form a first derivative. Due to various non-ideal conditions, the first derivative may have a series of successive local peaks of the same polarity. Peaks in the series having a peak value less than a previous peak value in the series are ignored, thereby resulting in a set of unignored peaks. From the unignored peaks in the series is chosen the one peak occurring last in order. According to the chosen peak, there is generated a signal more reliably indicating the true edge position between light and dark areas in the pattern.

TECHNICAL FIELD

The field of this disclosure relates generally to optical code readers, such as, for example, bar code readers, and more particularly to signal processing techniques and circuitry for determining edge positions in a binary optical code.

BACKGROUND

Today bar codes are ubiquitously found on or associated with objects of various types, such as the packaging of retail, wholesale, and inventory goods; retail product presentation fixtures (e.g., shelves); goods undergoing manufacturing; personal or company assets; and documents. By encoding information, a bar code typically serves as an identifier of an object, whether the identification be to a class of objects (e.g., oranges) or a unique item (e.g., U.S. Pat. No. 6,012,639).FIG. 1Adepicts a segment of a typical bar code100, with alternating bars (i.e., dark areas)102and spaces (i.e., light areas)104. The positions of the bars102and spaces104encode particular information. More specifically, the widths of the bars102and spaces104are often set to encode a desired information sequence, as the pattern of bars and spaces represents a string of binary ones and zeros, wherein the width of any particular bar or space is an integer multiple of a specified minimum width, which is called a “module” or “unit.” Thus, to decode the information, a bar code reader must be able to reliably discern the edge locations of the bars102and the spaces104. The leading edge of a bar (i.e., a light-to-dark transition) is commonly denoted as an STV (set video), and the trailing edge of a bar (i.e., a dark-to-light transition) is commonly denoted as an RTV (reset video). The first several STVs and RTVs of the bar code100are labeled inFIG. 1A, assuming (arbitrarily) that the bar code is scanned from left to right.

Optical scanning equipment can be utilized to generate an electrical signal indicative of the positions of bars and spaces in a bar code. Such a signal, denoted x(t), is depicted in simplified form inFIG. 1Bfor the corresponding bar code100. Before describing the processing of the signal x(t), a brief description of the optical scanning equipment that generates that signal is helpful. A more complete introduction to the optical scanning of bar codes can be found in the background section of the above-noted U.S. Pat. No. 6,102,639, the entirety of which is incorporated by reference herein. Typical optical scanning equipment comprises one or more illumination sources and one or more photodetectors. The illumination source may be a laser producing a focused beam spot on a small area of the bar code100. As the laser spot and the bar code100move relative to each other, such that the spot is scanned across the bar code100, a photodetector detects the laser light reflected off the bar code100and produces an electrical signal whose magnitude is related to the optical power of the reflected signal. Thus, as the spot scans across the bar code100, the photodetector generates an electrical signal whose variations over time at least roughly correlate to the spatial pattern of bars102and spaces104in the bar code100. Alternatively, the illumination source may be diffuse across the entire bar code100, and the bar code may be imaged using a charge-coupled device (CCD) camera or a CMOS (complementary metal-oxide-semiconductor) imager, either of which forms an electronic image of the bar code100. That electronic image can be sampled in the forward direction of the bar code100to generate a virtual scan line signal, much like the scan line signal generated with a scanning laser spot. In any event, the result is an electronic signal, which, at least ideally, somehow relates to the spatial positions of the bars102and spaces104in the bar code100. The next step is to process that signal to determine with some reliability where the edges (STVs and RTVs) lie.

FIG. 2is schematic diagram of a conventional edge detection system200for processing the scan line signal x(t) illustrated inFIG. 1B. The system200performs edge detection using a typical gated peak detection scheme. In general functional terms, the system200operates by forming the first and second derivatives of the scan line signal x(t) and by detecting zero crossings of the second derivative, which ideally represent optical edges. Moreover, the system200qualifies zero crossings of the second derivative only if the first derivative exceeds a threshold. In terms of hardware, the system200includes a double differentiator220, an envelope detector230, three comparators240,242, and246, and two logical AND gates250and255. The hardware operates as follows: As a preliminary matter, a preamplifier (not shown) may amplify, buffer, invert and/or condition the scan line signal x(t), which is received at the input of the differentiator220. The differentiator220produces a first derivative signal x′(t) and second derivative signal x″(t), respectively. While it is also possible to generate the first and second derivative signals x′(t) and x″(t) using two separate single differentiators, it is preferable to use common hardware to produce both to ensure more easily that x′(t) are x″(t) are time-aligned, as described in U.S. Pat. No. 6,073,849, which is incorporated herein by reference. The envelope detector230processes the first derivative signal x′(t) to determine, based on the extreme maximum and minimum values of that signal, a threshold value T somewhat smaller in magnitude than those extreme values. One example of a suitable implementation of the envelope detector230is disclosed in U.S. Pat. No. 4,000,397, which is incorporated herein by reference. By comparing the first derivative signal x′(t) to that threshold value, the comparators240and242detect peaks in that signal and produce respective logical true-valued outputs yS(t) and yR(t) when the first derivative signal x′(t) exceeds the threshold value. Because sharp transitions in the value of the scan signal x(t) should produce peaks in the first derivative signal x′(t), either yS(t) and yR(t) should be a logical true value during such peaks (yS(t) being true during a minimum or negative peak, and yR(t) being true during a maximum or positive peak). Because the second derivative signal should cross zero at such peaks, the comparator246is configured to detect those zero crossings and enable the appropriate AND gate250or255, respectively, to generate the STV or RTV signal, such that only one of which is true at any given time.

Further insight into the operation of the system200can be gleaned by returning toFIG. 1, in whichFIGS. 1B–1Hare voltage-versus-time plots for various signals in the system200.FIG. 1B, as already noted, is a plot of the scan line signal x(t), which is derived from a photodetector current, which is generally at a higher value during the spaces104and a lower value during the bars102, as more light is reflected from the spaces104than the bars102. (Depending upon the optical scanning equipment, that relationship may be reversed.) However, the scan line signal x(t) is not a perfect representation of the bar code100for a variety of reasons discussed below.FIG. 1Cis a plot of the first derivative signal x′(t), including the threshold levels +T and −T.FIG. 1Dis the second derivative signal x″(t), which, as one can see, crosses zero whenever the x′(t) is at a peak.FIG. 1Eshows the signal yS(t), the output of the comparator240. As can be seen, assuming high-true logic levels, as utilized in this figure, yS(t) is high when x′(t)<−T. Similarly,FIG. 1Fshows the signal yR(t), the output of the comparator242, which is high when x′(t)>+T. Finally,FIGS. 1G and 1Hare plots of the RTV and STV signals, respectively, which are the logical AND combination of yR(t) and the condition that x″(t)<0, and yS(t) and the condition that x″(t)>0.

As the inventors have recognized, a shortcoming of the system200is that the STV and RTV signals may contain multiple pulses for a single transition in the bar code100and thus do not unambiguously indicate edge positions in the bar code100. This is due to the fact that more than one peak can occur in the first derivative signal x′(t) for a single real edge in the bar code100—a phenomenon that can be called “peak multiplication.” There are several reasons why more than one peak may appear in x′(t) for a given real transition edge. Some reasons are attributable to the optical scanner. For example, the spot profile of the laser beam may have multiple peaks. Another reason may be noise introduced by the optical scanner or the electronic circuitry. Other reasons are traceable to external factors, including poor bar code printing quality, poor substrate quality or roughness, inconsistent bar or space color, modulated lighting effects, etc. Regardless of the cause, each local first derivative peak is detected as a separate like edge by the system200. However, multiple adjacent edges of the same type (STV or RTV) cannot be legitimate, as adjacent edges must be of alternating types. Only one edge in such a group is the best estimate of the true edge position.

Other edge detection techniques suffer from the same problem. For example, multi-bit digitizers, such as the systems disclosed in U.S. Pat. Nos. 5,302,813, 5,449,893, and 5,734,152, which operate by digitizing the first derivative peaks for an entire scan line and then applying various thresholds to the entire digitized record until a decodable peak pattern results, perform poorly in the presence of ISI (inter-symbol interference) and do not inherently ensure that multiple adjacent edges are rejected.

Bar codes are just one example of the many types of optical codes in use today. In general, optical codes encode useful, optically-readable information about the items to which they are attached or otherwise associated. While bar codes generally encode information across one dimension, higher-dimensional optical codes are also possible, such as, two-dimensional matrix codes (e.g., MaxiCode) or stacked codes (e.g., PDF 417). Decoding binary optical codes in general poses the same challenges, such as peak multiplication, posed by bar codes in particular.

SUMMARY

The present invention is directed to methods, systems, and circuits for detecting transitions in a binary optical code signal, and thus detecting edges in a binary optical code.

One preferred method is directed to detecting edges in a binary optical code by processing a signal imperfectly indicating perceived regions of relatively dark and relatively light areas arranged in an alternating pattern as part of a binary optical code. The method differentiates the signal to form a first derivative of the signal. The first derivative may have a series of successive local peaks of the same polarity. The method ignores peaks in the series having a peak value less than a previous peak value in the series, thereby resulting in a set of unignored peaks. The method then chooses from the unignored peaks in the series the one peak occurring last in order. Finally, the method generates, according to the chosen peak, a signal indicative of an edge between a light area and a dark area in the pattern.

According to another preferred embodiment, a system processes a signal imperfectly indicating perceived regions of relatively light and dark areas arranged in an alternating pattern as part of a binary optical code. The system comprises a differentiator, two comparators, and a circuit. The differentiator generates a first derivative of the signal. A first comparator, which is connected to the differentiator, compares the first derivative to a positive threshold and produces an output when the first derivative exceeds the positive threshold. The second comparator, which is also connected to the differentiator, compares the first derivative to a negative threshold and produces an output when the first derivative is less than the negative threshold. The circuit receives as inputs the first derivative, the output of the first comparator, and the output of the second comparator. The circuit generates a first output representative of a largest magnitude positive peak in a series of consecutive positive local peaks in the first derivative and a second output representative of a largest magnitude negative peak in a series of consecutive negative local peaks in the first derivative.

According to another preferred embodiment, a circuit processes an input signal derived from a binary optical code. The input signal has a series of multiple successive local peaks of the same given polarity. The circuit comprises a peak rectifier, an output node, a current mirror, and a discharge path. The peak rectifier has an input receiving the input signal and produces an output that approximately tracks the input signal while the input signal is sloping in the direction of the given polarity and that approximately holds near those local peaks having successively larger magnitude. The current mirror, which is connected to the peak rectifier and the output node, charges the output node while the peak rectifier is tracking the input signal. The discharge path, which is connected to the output node, provides for discharge of the output node while the peak rectifier is holding near a local peak value of the signal.

According to another preferred embodiment, a method determines edge positions in a binary optical code by qualifying zero crossings of a second derivative of an input signal imperfectly indicating perceived regions of relatively dark and relatively light areas arranged in an alternating pattern as part of a binary optical code. The method computes first and second derivatives of the input signal, wherein the second derivative may have multiple zero crossings for a given edge in the binary optical code. The method detects zero crossings of the first and second derivative and utilizes a zero crossing of the second derivative as an indication of a possible edge position in the binary optical code, provided that the zero crossing of the second derivative is the first one occurring after the substantially simultaneous occurrence of (1) the second derivative exceeding a threshold and (2) the first derivative having a magnitude greater than at any previous time since the last zero crossing of the first derivative. The result is a set of one or more qualified second derivative crossings indicating possible positions for the given edge in the binary optical code.

Details concerning the construction and operation of particular embodiments are set forth in the following sections.

DETAILED DESCRIPTION OF EMBODIMENTS

With reference to the above-listed drawings, this section describes particular embodiments and their detailed construction and operation. Certain embodiments are capable of achieving certain advantages over the known prior art, including some or all of the following: (1) more reliable detection of the most likely of multiple peaks resulting from peak multiplication; (2) improved edge detection performance under challenging detection conditions in the presence of noise, inter-symbol interference (ISI) (which can result from the laser spot size being large compared to the unit width), poor laser spot quality, poor bar code print quality, and/or small bar code feature size; and (3) improved performance at a small price in terms of circuitry space, weight, and power. These and other advantages of various embodiments will be apparent upon reading the following.

FIG. 3is a block diagram of an edge detection system300, according to one embodiment. The system300, like the conventional system200, operates according to a gated peak detection scheme, whereby zero crossings of the second derivative signal x″(t) are detected and qualified based on the amplitude of the first derivative signal x′(t). Thus, the differentiator220; envelope detector230; comparators240,242, and246; and AND gates250and255can be the same hardware components as in the conventional system200. Moreover, the gated peak signals yS(t) and yR(t) represent in digital form the locations of local maxima and minima, respectively, in the first derivative signal x′(t), just as in the conventional system200. The system300differs from the conventional system200, however, in the way in which the gated peak signals yS(t) and yR(t) are processed. More specifically, the system300, unlike the conventional system200, includes a multiple peak processing circuit310, which functions to reject spurious peaks, as described in greater detail below. The outputs of the multiple peak processing circuit310are peak signals zS(t) and zR(t), which the system300processes just as yS(t) and yR(t) in the conventional system200—viz., to qualify zero crossings of the second derivative signal x″(t).

The functional operation of the multiple peak processing circuit310can be understood by examiningFIG. 4, which is a flowchart of a method400performed by, for example, the system300. The method400begins by generating (step410) a scan line signal x(t) and differentiating (step420) that signal. Next, the method400detects (step430) peaks in the first derivative signal x′(t). The output of the detecting step430is, in general, for each actual bar code edge, a series of successive like-polarity peaks, such as represented by the gated peak signals yS(t) and yR(t). One such series of peaks is labeled p1, p2, . . . , p6and another is formed by the peaks labeled p7, p8, . . . , p10inFIG. 5, which is a plot of the first derivative signal x′(t) in the vicinities of two edge transitions in a bar code. As shown, peak p4is the maximum peak in the first group and therefore the most likely one representing the true edge location. However, a number of spurious leading peaks (p1, p2, and p3) and trailing peaks (p5and p6) are also present in the first group. The method400ignores or discards the spurious peaks and chooses the maximum peak p4in two steps. The first step is ignoring (step440) any trailing peaks less than the maximum peak so far encountered. The second step is choosing (step450) the last remaining peak in the series.

More particularly, with reference toFIG. 5as an example, the ignoring step440first observes peak p1, which it does not discard. So far, peak p1is the maximum peak encountered. Next, the ignoring step440observes peak p2and does not discard it because, although it trails peak p1, it is not less than p1. Peak p2now becomes the maximum peak encountered. Next, the ignoring step440observes peak p3, which it discards as being less than the maximum at this point (which remains p2). Next, the ignoring step440observes peak p4, which it does not discard and which becomes the new maximum peak. Next, the ignoring step440observes peaks p5and p6, which it discards as being less than peak p4. The result of the ignoring step440is that peaks p3, p5, and p6are discarded, while only peaks p1, p2, and p4are passed to the choosing step450. The choosing step450then chooses peak p4as the last-in-time peak in the group of non-discarded peaks. The method400thus arrives at the peak in the series most likely to represent the true RTV edge.

The multiple peak processing circuit310performs either the ignoring step440or both the ignoring step440and the choosing step450. The choosing step450may be performed either before or after the AND gates250and255. A microcontroller implementation of the choosing step450is described fully in the above-referenced U.S. Pat. No. 6,012,639 (see, in particular, the microcontroller430). Other implementations are possible to achieve the same functionality.

The ignoring step440may be implemented in electronic hardware as set forth, for example, inFIG. 6, which is a schematic diagram of a circuit600representing one implementation of one half of the multiple peak processing circuit310in the edge detection system300. For ease of comprehension, the circuit600is presented as the circuitry for processing just the positive peaks. The circuit600can easily be modified to also operate with an input signal of the opposite polarity; alternatively, a circuit similar to the circuit600can easily be constructed to process just the negative peaks.

The circuit600operates as follows: The first derivative signal x′(t) is connected to the gate of a transistor M1. When x′(t) is positive and increasing, the transistor M1turns on and conducts across its source and drain. The turn-on of the transistor M1has two effects. First, the same currents flow across each of transistors M2and M3, which form a current mirror. Second, that current charges a capacitor C1, as the transistor M1and the capacitor C1form a simple peak rectifier, and the voltage at the node610is a peak-rectified version of x′(t). That charging continues until the voltage at the node610equals that of x′(t) minus the gate-to-source voltage drop across the transistor M1(VGSM1), and x′(t) stops increasing. During that time of charging, a mirror current flows through the transistor M3, thus pulling the output node620to a high voltage (approximately the positive supply voltage VDD). As long as x′(t) is increasing at a sufficient rate, the capacitor C1will continue to charge, and the voltage of the node620will remain high.

However, as x′(t) stops increasing, the voltage of the node620will begin to discharge. The transistor M4is set to have a drain-to-source current equal to IREF/3, while a transistor M5is connected between the node620and ground, which supplies a drain-to-source current equal to IREF. That is accomplished by use of a transistor M13, which forms a current mirror with the transistors M4an M5. To achieve the unequal currents, the transistors M5and M13are preferably designed to have a channel width-to-length ratio three times that of the transistor M4, so that the drain-to-source current through each of the transistor M5and M13is three times that of transistor M4. Thus, the current through transistor M5, which discharges the node620, is IREF. The precise condition under which the node620discharges is given by the following Equations (A)–(C):

When the condition stated in Equation (C) is met, then the voltage at the node620decays to ground at a rate determined by the parasitic capacitance at the node620and the difference between the currents in M3and M5, i.e., IREF−i(M3). When x′(t) stops charging the capacitor C1, such as after a local peak in x′(t), then no current flows through C1and as a result i(M1)=IREF/3. Due to the current mirror, i(M3)=IREF/3 as well. Thus, in that case, the greater current IREFthrough the transistor M5rather quickly pulls the voltage at the node620low, where it stays until a larger subsequent value of x′(t) causes the capacitor C1to charge further.

The initial decay rate of the voltage at the node620(after x″(t)<2IREF/3C1but before the capacitor C1stops charging) should be carefully selected. If the initial decay rate is too fast, then the voltage at the node620will decay to ground before x″(t) crosses zero, and no edges will be rendered. If the initial decay rate is too slow, then the gate will remain open and qualify trailing peaks which are near in time to the peak having maximum amplitude. For a given system, the reference current IREFis therefore ideally chosen to ensure that all legitimate edges are rendered while still rejecting as many trailing peaks as possible.

The transistor M4provides a small DC current to overcome whatever leakage current may flow in the transistors M1and M2. Without the current from M4, the leakage current from the transistors M1and M2would be integrated by the capacitor C1, causing the voltage at the node610to increase to near VDD. Thus, the current in M4should be chosen to be greater than the maximum possible leakage current through the transistors M1and M2. If the current through M4is too large, on the other hand, the gate-to-source voltage drop of M1could become large enough to limit dynamic range, especially if the supply voltage VDDis low. Further, i(M4) must be significantly smaller than i(M5) to ensure that the voltage at the node620drops quickly to ground after the first derivative slope drops below the threshold. By providing both currents from a common current mirror as shown, all of these conditions may be met. While a 3:1 ratio is used in this example, other ratios may be chosen which would also meet the above criteria.

In the absence of the first derivative signal x′(t), baseline noise can cause the voltage at the node620to qualify illegitimate edges. To counteract that problem, which could cause a downstream decoder to expend resources processing spurious edges, potentially overloading the decoder to the point where legitimate edges are ignored, the voltage at the node620is qualified by AND-ing it with the gated peak signal yR(t), which is true when x′(t) exceeds a threshold generated conventionally (as in U.S. Pat. No. 4,000,397). The logical AND-ing of these two signals occurs at an AND gate625, as shown inFIG. 6. In this way the positive features of the conventional threshold gating (such as noise immunity in the absence of signal) and the added benefit of rejection of trailing peaks are both achieved.

FIG. 7is a set of voltage-versus-time plots for various signals in the circuit600.FIG. 7Ais a plot of a portion of x′(t), just as inFIG. 5, and a plot of the voltage v610(t) across the capacitor C1at the node610. While x′(t) is initially rising, the capacitor C1is charging, and the voltage v610(t) tracks x′(t) except for a small voltage drop VGSM1across the transistor M1. However, when x′(t) reaches a peak and begins falling, then the capacitor no longer charges and in fact begins discharging slowly due to the current in M4, until x′(t) exceeds the voltage v610(t)+VGSM1again. Thus, the voltage v610(t) is a peak-rectified version of x′(t).FIG. 7Aalso shows the threshold +T, which is applied to the generation of the signal yR(t).FIG. 7Bis a plot of x″(t), the derivative of x′(t). Also shown onFIG. 7Bis the threshold level 2IREF/3C1.FIG. 7Cis a plot of the voltage v620(t) at the node620. As explained above, the voltage v620(t) is at a high value when x″(t) exceeds the threshold level 2IREF/3C1. Otherwise, the voltage V620decays as shown.FIG. 7Dis a plot of yR(t), assuming the threshold shown inFIG. 7A.FIG. 7Eis a plot of zR(t), which is the logical AND-ing of the voltage V620and yR(t). As can be seen, zR(t) contains pulses corresponding to the peaks p1, p2, and p4, but not the trailing sub-maximum peaks p3, p5, and p6.

FIG. 8is a schematic diagram of one circuit800implementing both halves (STV and RTV) of the multiple peak processing circuit310. In the circuit800, the first derivative signal x′(t) is a differential signal. The two signals making up the differential pair are x′P(t) and x′N(t), the positive and negative sides, respectively. The circuit800contains two separate circuits, each like the circuit600, one for each signal of the differential pair. The first circuit, which processes x′P(t) comprises the transistors M1–M5, capacitor C1, and the nodes610and620, just as in the circuit600. The other circuit, which processes x′N(t), comprises transistors M7–M11, a capacitor C2, and nodes630and640in the same configuration as the transistors M1–M5, the capacitor C1, and the nodes610and620, respectively.

In addition, the circuit800comprises additional circuitry to selectively enable and disable the two circuits such that only one operates at any given time. That additional circuitry comprises a comparator810, an inverter820, and two transistors M6and M12. The inputs of the comparator810are the differential pair x′P(t) and X′N(t). The output of the comparator810is a signal labeled RESETN, which is input to the inverter820to produce a signal labeled RESETP. The signal RESETNis high and the signal RESETPis low during a positive half cycle of x′(t), when x′P(t)>x′N(t). During that time, the signal RESETN, which is connected to the gate of the transistor M12, causes the transistor M12to turn on and thereby to short the capacitor C2. Also, during that time, the signal RESETP, which is connected to the gate of the transistor M6, causes the transistor M6to turn off, thus allowing the capacitor C1to charge in response to x′P(t) and the first circuit to operate normally. Conversely, during a negative half cycle of x′(t), when X′N(t)>x′P(t), the transistor M6turns on, shorting the capacitor C1, while the transistor M12turns off, allowing the second circuit to operate normally.

Finally, the circuit800comprises two similar circuits for combining the voltages at the nodes620and640with the gated peak signals yR(t) and yS(t), respectively. The first of those circuits comprises an inverter830with hysteresis, a negative-input AND gate840, and an inverter850. The second of those circuits comprises an inverter860with hysteresis, a negative-input AND gate870, and an inverter880in an identical configuration. The particular configuration of those elements in the circuit800is for the case when yS(t), yR(t), zS(t), and zR(t) are low-true signals.

The circuit800can be built using discrete components or as an integrated circuit (IC) alone or in combination with circuitry for other parts of an optical code reader. One advantage of the circuit800in IC form is that it requires relatively little die area. While the circuit800has been illustrated with transistors M1–M13as field-effect transistors (FETs), they may be of any type.

Moreover, the circuit800can be implemented digitally rather than in analog form. One way to do so is to convert the scan line signal x(t) to a digital form (with suitable pre-amplification and anti-alias filtering) and feed the digitized signal to a special-purpose digital logic circuit (e.g., a digital application specific integrated circuit (ASIC) or programmable logic array) or a processor (e.g., a general-purpose microprocessor or digital signal processor (DSP)), which is programmed to implement the steps420–450of the method400. Although the analog form of the circuit800is preferred at the present time because of its lower cost and power consumption, those factors may change in the future.

More generally, the method400and similar methods can be implemented in special-purpose digital hardware or programmed for execution on a processor. An alternative method900, which is also suitable for digital implementation, is illustrated inFIG. 9. The method900begins by generating (step910) a scan line signal x(t) and differentiating (step920) it twice to yield x′(t) and x″(t). Next, the method900detects (step930) zero crossings of x″(t). It is the zero crossings of x″(t) that indicate, albeit possibly ambiguously, locations of edges in the binary optical code that the scan line signal x(t) represents, albeit imperfectly. To resolve that possible ambiguity, the method900performs a qualifying step940and a choosing step950. The qualifying step940detects the substantially simultaneous occurrence of two conditions: (1) x″(t) having a magnitude greater than a threshold, i.e., |x″(t)|>T2, and (2) x′(t) having a maximum magnitude since its last zero crossing. The circuit600performs the qualifying step940in analog form, where the threshold T2=2IREF/3C1, and the voltage v610(t) at the node610approximately tracks the maximum magnitude of x′(t) over a half cycle. Referring toFIG. 7C, the voltage v620(t) at the node620represents substantially simultaneous occurrence of conditions (1) and (2) for a positive half cycle. Finally, the method900chooses (step950) the most likely one of the qualified zero crossings of x″(t). As explained above, that is the one occurring last in time in a half cycle of x′(t). Note that the steps of the method900can be performed in an order different from that illustrated, or in some cases simultaneously;FIG. 9is presented in a simplified, linear order of steps to most readily teach the concepts involved, not to imply a particular order of operations.

The methods and systems illustrated and described herein can exist in a variety of forms both active and inactive. For example, they can exist as one or more software programs comprised of program instructions in source code, object code, executable code or other formats. Any of the above can be embodied on a computer readable medium, which include storage devices and signals, in compressed or uncompressed form. Exemplary computer readable storage devices include conventional computer system RAM (random access memory), ROM (read only memory), EPROM (erasable, programmable ROM), EEPROM (electrically erasable, programmable ROM), flash memory and magnetic or optical disks or tapes. Exemplary computer readable signals, whether modulated using a carrier or not, are signals that a computer system hosting or running a computer program can be configured to access, including signals downloaded through the Internet or other networks. Concrete examples of the foregoing include distribution of software on a CD ROM or via Internet download. In a sense, the Internet itself, as an abstract entity, is a computer readable medium. The same is true of computer networks in general.

The terms and descriptions used herein are set forth by way of illustration only and are not meant as limitations. Those skilled in the art will recognize that many variations can be made to the details of the above-described embodiments without departing from the underlying principles of the invention. The scope of the invention should therefore be determined only by the following claims, and their equivalents, in which all terms are to be understood in their broadest reasonable sense unless otherwise indicated.