Placement, rebuffering and routing structure for PLD interface

A PLD comprises a substrate, an array of programmable logic elements formed in the substrate, a first columnar interface coupling to the array of logic elements and extending in the substrate substantially parallel to a first side of the substrate, and at least a second columnar interface coupling to the array of logic elements and extending in the substrate substantially parallel to the first columnar interface. The interfaces illustratively provide a plurality of interconnects, control circuits and one or more of driver circuits, rebuffering circuits, signal conditioning circuits, deskewing circuits, clock synchronization circuits, power management circuits, testing/debugging circuits, partial reconfiguration circuits, multi-plexing circuits, pipelining circuits and storage circuits. The PLD is mounted on an interposer so that its interfaces electrically couple to electrically conducting paths on the interposer.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation-in-part of application Ser. No. 13/350,662, filed Jan. 13, 2012 for “Apparatus for Flexible Electronic Interfaces and Associated Methods,” the entire contents of which are incorporated herein by reference.

BACKGROUND

The present invention relates generally to an electronic package. A particular application for this package is in the implementation of programmable logic devices (PLD) such as field programmable gate arrays (FPGA) and the invention will be described in that context.

A FPGA is a PLD containing a large number of small programmable logic elements, a number of input/output (I/O) terminals, and a method of specifying electrical connections between the logic elements through a distributed array of programmable switches. The programming of the logic elements and the switches is typically specified by configuration bits stored in a configuration random access memory (CRAM). A FPGA allows a design engineer to realize a design of a product by programming its connections in a specific manner without incurring the high cost of manufacturing a unique integrated circuit. A variety of FPGAs are described in S. D. Brown, R. J. Francis, J. Rose, and Z. G. Vranesic,Field-Programmable Gate Arrays, (Kluwer Academic Publishers 1992); J. H. Jenkins,Designing with FPGAs and CPLDs, (PTR Prentice-Hall 1994); J. V. Oldfield and R. C. Dorf,Field Programmable Gate Arrays, (Wiley-Interscience 1995).

SUMMARY

The present invention is an improved electronic package especially useful with a programmable logic device (PLD) such as a field programmable gate array (FPGA).

In a preferred embodiment of the invention, the PLD comprises a substrate, an array of programmable logic elements formed in the substrate, a first columnar interface coupling to the array of logic elements and extending in the substrate substantially parallel to a first side of the substrate, and at least a second columnar interface coupling to the array of logic elements and extending in the substrate substantially parallel to the first columnar interface but spaced apart therefrom. The first and second interfaces illustratively provide a plurality of interconnects, control circuits and one or more of driver circuits, rebuffering circuits, signal conditioning circuits, deskewing circuits, clock synchronization circuits, power management circuits, testing/debuggin circuits, multiplexing circuits, pipelining circuits, partial reconfiguration circuits, and storage circuits. Other embodiments of the invention may use more than two columnar interfaces all of which are parallel to one another but spaced apart from each other. Illustratively, the PLD is mounted on an interposer so that its interfaces electrically couple to electrically conducting paths on the interposer.

Numerous variations may be practiced in the preferred embodiment.

DETAILED DESCRIPTION

FIGS. 1 and 2illustrate the general layout of certain FPGAs supplied by Altera Corporation, the assignee of the present application.FIG. 1depicts a programmable logic device (PLD)20comprising logic array blocks (LABs)22. Device20is implemented as a single integrated circuit. Each logic array block22comprises a group of logic elements (LEs)24which is frequently referred to as core logic. Around the periphery of the PLD20are input/output elements (IOEs)26. Each LE24and IOE26can generate one or more signals that can be routed to other LEs24or IOEs26through vertical (or column) interconnect circuitry28and horizontal (or row) interconnect circuitry30. The interconnect circuitry (or bus) is located in one or more metallization layers of the integrated circuit. As shown inFIG. 1, the vertical and horizontal interconnect circuitry28,30extends across the full width of the integrated circuit in the vertical and horizontal directions, respectively. The interconnection circuits that extend the full width of the integrated circuit are often referred to as global circuits. The number of LABs22shown in PLD20ofFIG. 1is only illustrative. In practice, PLD20could have fewer LABs and often has more.

FIG. 2is a more detailed view of a logic array block (LAB)22. LAB22a set of logic elements (LE1-LE8). Local interconnect circuitry31routes signals generated within the LAB22(or signals generated externally to LAB22which have been routed to this LAB) to the LE24within that LAB. Multiplexers32provide for various connections between LAB22and the vertical and horizontal circuitry28,30. Various programmable switches (not shown), which may include multiplexers, provide a variety of interconnections among the LE.

The interface to PLD20conventionally is through IOEs26disposed on the periphery of the PLD on one or more sides. In some situations other arrangements might be desired.

FIGS. 3A and 3Bare a side view and a top view of an illustrative embodiment of the invention.FIGS. 3A and 3Bdepict an interposer310, a programmable logic device (PLD)340mounted on interposer310and an additional device370also mounted on the interposer. Illustratively, device370is a system on a chip (SOC); but it could be any number of other devices that might advantageously be connected to PLD340through interposer310.

Interposer310illustratively is a rectangular Silicon substrate having upper and lower major surfaces312,314. A plurality of electrically conducting paths316are defined on one or both surfaces312,314. Electrical connections between the electrically conducting paths on the two major surfaces are made by electrically conducting vias318that extend through interposer310. Electrical connections320to other devices are provided on lower surface314and are electrically connected to conducting paths316.

In other embodiments, interposer may be formed from a laminate of generally alternating layers of an insulating layer and an electrically conducting layer with electrically conducting paths defined in the electrically conducting layers as is well known in the art. Electrical connections between the electrically conducting layers are made by electrically conducting paths that extend between the electrically conducting layers through the insulating layers.

PLD340is an integrated circuit formed in a semiconductor material such as Silicon or Gallium Arsenide. The circuit typically is rectangular in shape and therefore has four sides, a first two of which are parallel to each other and a second two of which are parallel to each other and perpendicular to the first two sides. The PLD has a plurality of programmable logic elements such as those described above. The PLD also has a plurality of interface circuits350that are spaced apart from each other and extend in columns (or rows) substantially parallel to each other and to two sides of the PLD and substantially perpendicular to the other two sides of the PLD. As a result the interface circuits may be characterized as columnar or row interfaces. For purposes of illustration, four such interface circuits351,352,353,354are shown inFIGS. 3A and 3B; but it will be understand that as few as two such interface circuits and more than four such circuits may be used in the practice of the invention. Illustratively, the interface circuits are equally spaced but other arrangements may also be used in the practice of the invention.

PLD340is electrically and mechanically connected to interposer310by interconnects360that typically are solder balls, solder bumps or pins. Interconnects360connect the interface circuits350on PLD340to the electrical paths316on interposer310. More particularly, the interconnects immediately adjacent a specific interface circuit350connect that interface circuit to the electrical paths on interposer310. So, for example, interconnects361immediately adjacent interface351connect that interface to paths316.

FIG. 4is a schematic illustration of an interface circuit350useful in the practice of the invention. Circuit350comprises a controller410, buffer circuits440, routing interface470and interconnects360.

Controller410couples to buffer circuits440and routing interface470. Generally, controller410provides control and supervisory functions for interface circuits350. For example, controller410may determine the timing, direction and number of signals communicated between PLD340and interposer310. Controller410may also support one or more data or communication protocols. For example, controller may support protocols such as DDR, DDR2, DDR3, communication protocols, signaling protocols and the like.

Controller410may include a variety of circuitry ranging from hardened (fixed or non-programmable) to soft (fully programmable) or customizable circuitry. Thus, in some embodiments, controller410may include logic gates, registers, flip-flops, counters, finite state machines, hardened intellectual property (IP), memory, multiplexers, latches and the like. In some embodiments, controller410may include fully customizable or programmable logic, such as look-up tables, soft IP, and, generally, circuitry similar to the programmable fabric of a PLD. In yet other embodiments, controller410may include structured application specific integrated circuits (structured ASIC). In such embodiments, with one or more mask changes, the functionality of controller410may be configured, customized, or programmed, as persons of ordinary skill in the art understand. Regardless of the exact implementation, in some embodiments, controllers410in multiple interface circuits may be combined to provide additional flexibility, increased functionality, etc.

Buffer circuits440couple to some or all of the interconnects360. Buffer circuits440may provide one or more of the following output functions in exemplary embodiments: buffering, level shifting (e.g., to accommodate different voltage levels of the signal source and signal destination circuits) and/or signal conditioning for signals derived from PLD340. Buffer circuits440may also provide input buffer functionality by buffering, level shifting and/or conditioning signals from another device so as to provide those signals to circuitry on PLD340, Buffer circuits may also provide bi-directional buffer functionality by buffering, level shifting and/or conditioning signals from the circuitry so as to provide a transmit those signals to circuitry on other devices, Other circuits implemented in buffer circuits440may include driver circuits, deskewing circuits, clock synchronization circuits, testing/debugging circuits, multiplexing circuits, partial reconfiguration circuits, pipelining circuits and storage circuits.

Buffer circuit440may have various programmable of configurable features to provide flexibility. For example, in some embodiments, buffer circuits440may have tri-state functionality. As another example, buffer circuits440may have fixed or programmable drive strength and/or slew rate. As shown inFIG. 4, buffer circuit440includes output buffers442, input buffers444and bi-directional buffers446. Optionally, buffer circuit440may also include circuitry for conditioning or regulating power lines and for power management.

Routing interface470couples to controller110and to circuitry in PLD310. Interface470receives data signals and power from controller410and provides such signals and power to PLD340. Interface470also receives data signals from PLD340and provides such signals to controller410.

Interface470typically includes multiplexers472,474, buffers476,478, registers and similar circuitry. For example, as shown inFIG. 4, a multiplexer472under control of controller410is used to select one of several signals received from sources within the PLD340and provide the selected signal to controller410. As another example, multiplexer474under control of controller410is used to select one of several signals received from controller410and provide the selected signal to circuitry in the PLD340. Buffer (or driver)476may receive an input from circuitry within PLD340and provide an output signal to controller410. And buffer (or driver)478may receive an input from controller410and provide an output to circuitry in PLD340.

In some embodiments, routing interface470may include circuitry similar to the programmable interconnect of a PLD. In such embodiments, the functionality of the circuitry in routing interface470may be programmed or configured in much the same way as the routing fabric or resources of a PLD.

The multiple interface circuits350on PLD340make it possible to readily achieve various performance improvements on the PLD. For example, as shown schematically inFIGS. 5A and 5B, signals originating near one interface circuit350on PLD340may be routed to that interface rather than to a more remote interface or the side of the PLD and then conducted by the conducting paths316on the interposer to a second interface350on PLD340, thereby relieving the PLD of the bandwidth requirements for routing the signals for relatively long distances on the PLD alone. Similarly, to conserve PLD resources, outbound signals from the PLD to another device can be routed to the nearest interface350and then through the conducting paths316on the interposer rather than having to go through the entire PLD; and inbound signals to the PLD can be routed through the conducting paths316on the interposer to the interface nearest their destination on the PLD rather than routing them through the entire PLD.

Instead of using interfaces350to connect PLD340to an interposer, interfaces350may be used to connect PLD340to the interfaces of a second, substantially identical PLD that is oriented face-to-face with PLD340. Such an arrangement would make it possible for either PLD to couple through the interfaces to use the routing resources of the other PLD.

In still another variation, additional electrically conducting layers may be formed on the surface of the PLD and processed to form additional conducting paths on the surface of the PLD.

As depicted schematically inFIG. 6, the interface circuits may also be used for various signal processing functions. For example, the output and input buffers442,444in each of the interfaces may be used for rebuffering signals propagating through these interfaces, thereby improving the performance and bandwidth of these circuits.

As will be apparent to those skilled in the art, numerous variations may be practiced within the spirit and scope of the present invention.