Semiconductor memory device including an insulating portion adjacent to first and second pluralities of conductive layers

According to one embodiment, a semiconductor memory device includes a stacked body, first memory portions, and second memory portions. The stacked body includes conductive layers. The conductive layers are arranged in a first direction and extend in a second direction. The stacked body includes first and second regions. The second region is arranged with the first region in the second direction. The first memory portions extend in the first direction through the first region and are arranged at a first pitch along the second direction. The second memory portions extend in the first direction through the second region and are arranged at the first pitch along the second direction. A distance between a first center of one of the first memory portions and a second center of one of the second memory portions is longer than the first pitch and shorter than 2 times the first pitch.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2016-140142, filed on Jul. 15, 2016; the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to semiconductor memory device and a method for manufacturing the same.

BACKGROUND

It is desirable to increase the storage density of a semiconductor memory device.

DETAILED DESCRIPTION

According to one embodiment, a semiconductor memory device includes a stacked body, a plurality of first memory portions, and a plurality of second memory portions. The stacked body includes a plurality of conductive layers. The plurality of conductive layers are arranged in a first direction and extend in a second direction crossing the first direction. The stacked body includes a first region and a second region. The second region is arranged with the first region in the second direction. The plurality of first memory portions extend in the first direction through the first region and are arranged at a first pitch along the second direction. The plurality of second memory portions extend in the first direction through the second region and are arranged at the first pitch along the second direction. A distance along the second direction between a first center in the second direction of one of the plurality of first memory portions and a second center in the second direction of one of the plurality of second memory portions is longer than the first pitch and shorter than 2 times the first pitch.

According to one embodiment, a method for manufacturing a semiconductor memory device is disclosed. The method can include forming a stacked film on a surface of a base body. The stacked film includes a plurality of first films and a second film. The plurality of first films are arranged in a first direction. The first direction is perpendicular to the surface. The second film is provided between the plurality of first films. The method can include forming a plurality of first memory portions and a plurality of second memory portions. The plurality of first memory portions extend in the first direction through a first region of the stacked film and are arranged at a first pitch in a second direction crossing the first direction. The plurality of second memory portions extend in the first direction through a second region of the stacked film and are arranged at the first pitch in the second direction. The second region is arranged with the first region in the second direction. A distance along the second direction between a first center in the second direction of one of the plurality of first memory portions and a second center in the second direction of one of the plurality of second memory portions is longer than the first pitch and shorter than 2 times the first pitch. The method can include forming a hole in the stacked film and removing the plurality of first films via the hole. In addition, the method can include introducing a material into a space formed where the plurality of first films is removed. The material is used to form a conductive layer.

The drawings are schematic and conceptual; and the relationships between the thickness and width of portions, the proportions of sizes among portions, etc., are not necessarily the same as the actual values thereof. Further, the dimensions and proportions may be illustrated differently among drawings, even for identical portions.

In the specification and drawings, components similar to those described or illustrated in a drawing thereinabove are marked with like reference numerals, and a detailed description is omitted as appropriate.

First Embodiment

FIG. 1is a schematic cross-sectional view illustrating a semiconductor memory device according to a first embodiment.

FIG. 2AandFIG. 2Bare schematic cross-sectional views illustrating the semiconductor memory device according to the first embodiment.

As shown inFIG. 2A, the semiconductor memory device110according to the embodiment includes a stacked body SB, multiple first memory portions MP1, and multiple second memory portions MP2.

The stacked body SB includes multiple conductive layers21(a first conductive layer21a, a second conductive layer21b, etc.). The multiple conductive layers21are arranged in a first direction.

The first direction is taken as a Z-axis direction. One direction perpendicular to the first direction is taken as an X-axis direction. A direction perpendicular to the Z-axis direction and the X-axis direction is taken as a Y-axis direction.

The multiple conductive layers21extend in a second direction. The second direction crosses the first direction. In the example, the second direction is the X-axis direction.

An insulating layer22is provided between the multiple conductive layers21. The multiple conductive layers21include, for example, a metal, etc. The insulating layer22includes, for example, an oxide (silicon oxide or the like), etc.

The stacked body SB is provided on, for example, a base body10. The base body10may include, for example, at least a portion of a silicon substrate. For example, the first conductive layer21ais provided between the second conductive layer21band the base body10.

The stacked body SB includes multiple regions as shown inFIG. 2AandFIG. 1. The multiple regions are, for example, a first region Rx1, a second region Rx2, etc. The second region Rx2is arranged with the first region in the second direction (in the example, the X-axis direction).

The multiple first memory portions MP1extend in the first direction (the Z-axis direction) through the first region Rx1. The multiple first memory portions MP1are arranged at a first pitch p1along the second direction (the X-axis direction).

The multiple second memory portions MP2extend in the first direction (the Z-axis direction) through the second region Rx2. The multiple second memory portions MP2are arranged at the first pitch p1along the second direction (the X-axis direction).

The multiple first memory portions MP1and the multiple second memory portions MP2are included in multiple memory portions MP. A portion of the multiple memory portions MP is provided in the first region Rx1. This portion corresponds to the multiple first memory portions MP1. Another portion of the multiple memory portions MP is provided in the second region Rx2. This portion corresponds to the multiple second memory portions MP2.

As shown inFIG. 2A, one of the multiple memory portions MP includes a semiconductor body50and a memory layer54. The semiconductor body50extends in the Z-axis direction through the stacked body SB. The memory layer54is provided between the semiconductor body50and the multiple conductive layers21. Memory cells MC are formed at the portions where the multiple conductive layers21and the multiple memory portions MP cross. The memory cells MC correspond to memory transistors. The multiple conductive layers21correspond to, for example, gate electrodes of the memory transistors. The semiconductor body50is used as the channels of the memory transistors. The multiple conductive layers21function as, for example, word lines. One end (e.g., the lower end) of the semiconductor body50is electrically connected to the base body10. The one end of the semiconductor body50is electrically connected to, for example, a source line (not illustrated) via the base body10. On the other hand, the other end (e.g., the upper end) of the semiconductor body50is connected to a bit line (not illustrated). A selection gate (not illustrated) is further provided at the semiconductor body50. By the control of the word lines, the bit lines, and the selection gates, the multiple memory cells MC are selected; and the operations of programming, erasing, and reading are performed.

In the embodiment, the pitch of the multiple first memory portions MP1is the same as the pitch of the multiple second memory portions MP2. In other words, the spacing of the multiple first memory portions MP1is constant. Also, the spacing of the multiple second memory portions MP2is constant. In the embodiment, the spacing between the group of the multiple first memory portions MP1and the group of the multiple second memory portions MP2is longer than the spacing inside each group.

In the embodiment as shown inFIG. 1, one M1of the multiple first memory portions MP1has a center (a first center C1) in the second direction. One of the multiple second memory portions MP2has a center (a second center C2) in the second direction. A distance q1along the second direction between the first center C1and the second center C2is longer than the first pitch p1. The distance q1is shorter than 2 times the first pitch p1.

Among the multiple first memory portions MP1, the one M1of the multiple first memory portions MP1is most proximal to one M2of the multiple second memory portions MP2. Among the multiple second memory portions MP2, the one M2of the multiple second memory portions MP2is most proximal to the one M1of the multiple first memory portions MP1. For such a one M1and such a one M2, the distance between the centers is set to be longer than the first pitch p1.

For example, the spacing of the multiple memory portions MP is set to be as small as possible inside one group. Thereby, the density of the memory cells MC can be set to be high inside one group. In such a case, the resistance of the conductive layer21becomes excessively high if the number of the multiple memory portions MP provided inside one group is excessively large.

On the other hand, as shown inFIG. 1, regions that have stripe configurations extending in the X-axis direction are provided at the ends of the conductive layer21. The regions that have the stripe configurations are, for example, a sixth region Rx6, a seventh region Rx7, etc. In the example, a fifth region Rx5(e.g., a separation region) is provided in the central region of the conductive layer21. The fifth region Rx5also extends in the X-axis direction. The memory portions MP are not provided in the fifth to seventh regions Rx5to Rx7. Therefore, the resistance is low in these regions.

In the embodiment, the spacing between the group of the multiple first memory portions MP1and the group of the multiple second memory portions MP2is set to be longer than the spacing of the memory portions MP of each group. In other words, the distance q1along the second direction between the first center C1and the second center C2is longer than the first pitch p1. Thereby, a region where the spacing between the multiple memory portions MP is long is provided. This region is electrically connected to, for example, the fifth to seventh regions Rx5to Rx7recited above. Thereby, the increase of the resistance of the conductive layer21can be suppressed.

As described below, there are cases where the multiple conductive layers21are formed by a replacement method. A stacked body is formed in the replacement method. The stacked body includes multiple first films (e.g., sacrificial layers), and second films provided between the multiple first films. Memory portions that pierce such a stacked film are formed. Then, the multiple first films are removed; and a material that is used to form the conductive layers21is introduced to the space formed by the removal. The multiple conductive layers21are formed of a conductive material. The multiple second films are used to form the insulating layers22. By such a replacement method, the material that is used to form the conductive layers21is not easily introduced when forming the stacked body SB if the space between the multiple memory portions MP is excessively narrow. Thereby, for example, voids occur. If it is difficult to introduce the material, for example, the resistance of the conductive layer21increases.

In the embodiment, portions where the spacing of the multiple memory portions MP is wide are provided locally. Therefore, even in the case where the replacement method recited above is used, the material that is used to form the conductive layers21can be introduced via the portions where the spacing is locally wide. Because the spacing is wide, the material is introduced easily. For example, the occurrence of the voids can be suppressed locally.

Thus, in the embodiment, a special configuration is applied to the arrangement of the multiple memory portions MP. Thereby, for example, the increase of the resistance of the conductive layer21can be suppressed.

On the other hand, the density of the multiple memory portions MP decreases if the spacing of the portions where the spacing of the multiple memory portions MP is wide is set to be excessively large. In the embodiment, the distance q1recited above is set to be shorter than 2 times the first pitch p1. Thereby, the decrease of the density of the multiple memory portions MP can be suppressed.

Thus, in the embodiment, the density of the multiple memory portions MP can be increased while maintaining a low resistance of the conductive layer21. According to the embodiment, a semiconductor memory device can be provided in which the storage density can be increased.

In the embodiment, the number of the multiple first memory portions MP1is not less than 3 and not more than 100. Similarly, the number of the multiple second memory portions MP2is not less than 3 and not more than 100. In the example shown inFIG. 1, the numbers are 6. When the numbers are excessively small, the density of the multiple memory portions MP becomes excessively low. When the numbers exceed 100, for example, the resistance of the conductive layer21increases excessively. When the numbers exceed 100, for example, there are also cases where the resistance distribution along the Y-axis direction of the conductive layer21becomes excessively large.

As shown inFIG. 1andFIG. 2B, multiple third memory portions MP3and multiple fourth memory portions MP4are further provided in the semiconductor memory device110. The multiple third memory portions MP3extend in the first direction (the Z-axis direction) through the first region Rx1. The multiple third memory portions MP3are arranged at the first pitch p1along the second direction (the X-axis direction).

The multiple fourth memory portions MP4extend in the first direction (the Z-axis direction) through the second region Rx2. The multiple fourth memory portions MP4are arranged at the first pitch p1along the second direction (the X-axis direction).

One M3of the multiple third memory portions MP3has a center (a third center C3) in the second direction (the X-axis direction). One M4of the multiple fourth memory portions MP4has a center (a fourth center C4) in the second direction (the X-axis direction). A distance q2along the second direction (the X-axis direction) between the third center C3and the fourth center C4is longer than the first pitch p1and shorter than 2 times the first pitch p1.

Thereby, for example, even in the region where the multiple third memory portions MP3and the multiple fourth memory portions MP4are provided, the density of the memory portions MP can be increased while maintaining a low resistance of the conductive layer21.

In the example, the one M3of the multiple third memory portions MP3recited above is provided at a position along a direction from the one M1of the multiple first memory portions MP1recited above that is tilted with respect to the X-axis direction. The one M4of the multiple fourth memory portions MP4recited above is provided at a position along a direction from the one M2of the multiple second memory portions MP2recited above that is tilted with respect to the X-axis direction.

For example, the position in the second direction of the first center C1is between the position in the second direction of the third center C3and the position in the second direction of the fourth center C4. For example, the position in the second direction of the fourth center C4is between the position in the second direction of the first center C1and the position in the second direction of the second center C2.

For example, a direction that crosses the first direction and the second direction is taken as a third direction. The third direction is, for example, the Y-axis direction. A distance p2along the third direction between the position of the first center C1in the third direction and the position of the third center C3in the third direction is shorter than the first pitch p1. The density of the multiple memory portions MP can be increased further by setting the spacing of the multiple memory portions MP in the Y-axis direction to be small.

As shown inFIG. 1, multiple fifth memory portions MP5and multiple sixth memory portions MP6are further provided. The stacked body SB further includes a third region Rx3and a fourth region Rx4in addition to the fifth region Rx5described above. The third region Rx3is arranged with the first region Rx1in the third direction (e.g., the Y-axis direction) crossing the first direction and the second direction. The fourth region Rx4is arranged with the third region Rx3in the second direction (the X-axis direction) and arranged with the second region Rx2in the third direction (the Y-axis direction).

The fifth region Rx5is positioned between the first region Rx1and the third region Rx3and between the second region Rx2and the fourth region Rx4.

The multiple fifth memory portions MP5extend in the first direction through the third region Rx3and are arranged at the first pitch p1along the second direction. The multiple sixth memory portions MP6extend in the first direction through the fourth region Rx4and are arranged at the first pitch p1along the second direction.

The fifth region Rx5is continuous in the second direction (the X-axis direction). For example, the fifth region Rx5is continuous when cut by a plane (the Z-X plane) including the first direction and the second direction. On the other hand, the multiple memory portions MP are provided in the first to fourth regions Rx1to Rx4. Therefore, the first to fourth regions Rx1to Rx4are discontinuous in the second direction (the X-axis direction). For example, the first to fourth regions Rx1to Rx4are discontinuous when cut by the Z-X plane. The fifth region Rx5is a region (e.g., a separation region) where the memory portions MP are not provided.

For example, a width w5along the third direction (e.g., the Y-axis direction) of the fifth region Rx5is, for example, longer than the distance q1described above. For example, the width w5may be larger than, for example, the first pitch p1. In the embodiment, the width w5may be shorter than the distance q1. The width w5may be smaller than the first pitch p1.

By providing such a fifth region Rx5(the region where the memory portions MP are not provided), the resistance of the conductive layer21can be maintained to be low.

As shown inFIG. 1, the sixth region Rx6and the seventh region Rx7may be further provided in the stacked body SB. The first to fifth regions Rx1to Rx5are positioned between the sixth region Rx6and the seventh region Rx7.

The sixth region Rx6is continuous in the second direction. The sixth region Rx6is continuous when cut by the Z-X plane. The sixth region Rx6is a region where the memory portions MP are not provided. The seventh region Rx7is continuous in the second direction. The seventh region Rx7is continuous when cut by the Z-X plane. The seventh region Rx7is a region where the memory portions MP are not provided. By providing such a sixth region Rx6and such a seventh region Rx7, the resistance of the conductive layer21can be maintained to be low.

For example, the sixth region Rx6and the seventh region Rx7are electrically connected via the fifth region Rx5. The electrical connection is performed by, for example, a region between the first region Rx1and the second region Rx2(a region having a wide width where the memory portions MP are not provided). For example, the memory portions MP are provided at high density in the first region Rx1, the second region Rx2, the third region Rx3, and the fourth region Rx4. The fifth region Rx5, the sixth region Rx6, and the seventh region Rx7are provided around these regions. The resistance of the conductive layer21is low in these regions. The resistance of the conductive layer21can be maintained to be low by such a structure.

As shown inFIG. 1, a set of the multiple conductive layers21such as that recited above is arranged in the Y-axis direction. For example, the conductive layer21recited above is provided between another conductive layer21A and another conductive layer21B. The other conductive layer21A and the other conductive layer21B also extend in the X-axis direction. A first conductive portion57A is provided between the other conductive layer21A and the conductive layer21. An insulating portion57iis provided between the other conductive layer21A and the first conductive portion57A. Another insulating portion57iis provided between the conductive layer21and the first conductive portion57A. A second conductive portion57B is provided between the other conductive layer21B and the conductive layer21. Another insulating portion57iis provided between the other conductive layer21B and the first conductive portion57A. Another insulating portion57iis provided between the conductive layer21and the second conductive portion57B.

The first conductive portion57A and the second conductive portion57B extend in the X-axis direction. These conductive portions may spread, for example, along the X-axis direction and the Z-axis direction. For example, one end of each of these conductive portions is electrically connected to the base body10. For example, the other end of each of these conductive portions is electrically connected to the source line (not illustrated). These conductive portions are, for example, source line members.

An example of the memory portions MP will now be described.

FIG. 3is a schematic cross-sectional view illustrating the semiconductor memory device according to the first embodiment.

FIG. 3is a schematic cross-sectional view in which a portion ofFIG. 1is enlarged.

One of the multiple first memory portions MP1(the one M1recited above) includes the semiconductor body50(50A), a first memory insulating film54a, a second memory insulating film54b, and a memory film54c. The semiconductor body50(50A) extends in the first direction (the Z-axis direction) through the stacked body SB (referring toFIG. 2A). The first memory insulating film54ais provided between the semiconductor body50(50A) and the multiple conductive layers21(e.g., the first conductive layer21a). The second memory insulating film54bis provided between the semiconductor body50(50A) and the first memory insulating film54a. The memory film54cis provided between the first memory insulating film54aand the second memory insulating film54b. The first memory insulating film54a, the second memory insulating film54b, and the memory film54care included in the memory layer54(a memory layer54A). The first memory insulating film54acorresponds to, for example, a blocking insulating film. The second memory insulating film54bcorresponds to, for example, a tunneling insulating film. These insulating films include, for example, silicon oxide, etc. The memory film54cis, for example, a charge storage film. In such a case, the memory film54cincludes, for example, silicon nitride, etc. The memory film54cmay be a floating gate. In such a case, the memory film54cincludes, for example, polysilicon, etc.

One of the multiple second memory portions MP2(the one M2recited above) has a configuration similar to that of the one of the multiple first memory portions MP1(the one M1recited above). The one M2recited above includes, for example, the semiconductor body50(50B) and a memory layer54B.

As shown inFIG. 3, the semiconductor body50A and the semiconductor body50B may have pipe configurations. For example, core portions55A and55B that extend in the first direction (the Z-axis direction) are provided. The semiconductor body50A is provided between the core portion55A and the conductive layers21(the stacked body SB). The semiconductor body50B is provided between the core portion55B and the conductive layers21(the stacked body SB).

As described above, the multiple first memory portions MP1are arranged at a substantially constant pitch (the first pitch p1). A length Dx in the second direction of each of the multiple first memory portions MP1is substantially constant. In such a case, a distance wn (the spacing) between two of the multiple first memory portions MP1is substantially constant.

Similarly, the multiple second memory portions MP2are arranged at a substantially constant pitch (the first pitch p1). The length in the second direction of each of the multiple second memory portions MP2also is set to be the length Dx. In such a case, for the multiple second memory portions MP2as well, the distance (the spacing) is the distance wn and is substantially constant.

In the example, one size (the length Dx) of the multiple memory portions MP is longer than the distance wn. For example, the length Dx in the second direction of the one M1of the multiple first memory portions MP1recited above is longer than ½ of the first pitch p1. For example, the shortest distance along the second direction between two of the multiple first memory portions MP1is shorter than ½ of the first pitch p1. The shortest distance corresponds to the distance wn.

On the other hand, a distance ww along the second direction between the one M1of the multiple first memory portions MP1recited above and the one M2of the multiple second memory portions MP2recited above is longer than the distance wn recited above (the shortest distance along the second direction between two of the multiple first memory portions MP1). Thus, by setting the distance ww along the second direction between the one M1of the multiple first memory portions MP1recited above and the one M2of the multiple second memory portions MP2recited above to be longer than the distance wn of the other portions, the storage density can be increased while suppressing the increase of the resistance of the conductive layer21.

For example, the width w5along the third direction (e.g., the Y-axis direction) of the fifth region Rx5is greater than 2 times the distance wn (the distance along the second direction) between the two of the multiple first memory portions MP1. For example, the width w5may be longer than the length Dx in the second direction (the X-axis direction) of the one of the multiple first memory portions MP1. The width w5may be, for example, longer than the length in the Y-axis direction (the third direction crossing the first direction and the second direction) of the one of the multiple first memory portions MP1.

In the example, one of the multiple conductive layers21(e.g., the first conductive layer21a) includes a first portion21W and a second portion21R. The second portion21R is provided between the first portion21W and each of the multiple memory portions MP. The first portion21W includes, for example, tungsten. The second portion21R includes, for example, TiN. The second portion21R functions as, for example, a barrier metal.

An example of a method for manufacturing the semiconductor memory device110will now be described.

FIG. 4AtoFIG. 4EandFIG. 5AtoFIG. 5Eare schematic cross-sectional views illustrating the method for manufacturing the semiconductor memory device according to the first embodiment.

As shown inFIG. 4A, a stacked film SBf is formed on a surface10a(e.g., the upper surface) of the base body10. A direction that is perpendicular to the surface10aof the base body10corresponds to the first direction (the Z-axis direction). The stacked film SBf includes multiple first films61arranged in the Z-axis direction, and a second film62provided between the multiple first films61. The first films61are, for example, silicon nitride films. The second films62are, for example, silicon oxide films. As described below, the stacked body SB is formed from the stacked film SBf.

As shown inFIG. 4AandFIG. 4C, multiple memory holes MH are formed in the stacked film SBf. The multiple memory holes MH pierce the stacked film SBf in the Z-axis direction. For example, the multiple memory holes MH reach the base body10. As described below, the memory portions MP are formed at the positions of the multiple memory holes MH. Accordingly, the positions of the multiple memory holes MH are set to be, for example, the positions of the multiple memory portions MP described in reference toFIG. 1.

As shown inFIG. 4D, for example, a silicon oxide film, a silicon nitride film, and a silicon oxide film are sequentially formed in the multiple memory holes MH; and a silicon film is formed in the remaining space. The silicon oxide film, the silicon nitride film, and the silicon oxide film are used to form at least a portion of the memory layer54. One of the two silicon oxide films is used to form at least a portion of the first memory insulating film54a. The other one of the two silicon oxide films is used to form the second memory insulating film54b. The silicon nitride film is used to form the memory film54c. The silicon film is used to form the semiconductor body50. The insulating film may be formed in the remaining space after the formation of the silicon film. The insulating films are used to form the core portions55A and55B, etc.

Thus, the multiple first memory portions MP1and the multiple second memory portions MP2are formed (referring toFIG. 1). The multiple first memory portions MP1extend in the first direction (the Z-axis direction) through the first region Rx1of the stacked film SBf and are arranged at the first pitch p1in the second direction (the X-axis direction) crossing the first direction (referring toFIG. 1andFIG. 2A). The multiple second memory portions MP2extend in the first direction (the Z-axis direction) through the second region Rx2of the stacked film SBf and are arranged at the first pitch p1in the second direction (the X-axis direction) (referring toFIG. 1andFIG. 2A). The second region Rx2is arranged with the first region Rx1in the second direction. The distance q1along the second direction between the first center C1in the second direction of the one M1of the multiple first memory portions MP1and the second center C2in the second direction of the one M2of the multiple second memory portions MP2is longer than the first pitch p1(referring toFIG. 1). The distance q1is shorter than 2 times the first pitch p1(referring toFIG. 1).

A hole ST is formed in the stacked film SBf as shown inFIG. 4E. In the example, the hole ST is a slit. The hole ST spreads along the Z-Y plane. The hole ST reaches the base body10.

As shown inFIG. 5AandFIG. 5B, the multiple first films61are removed via the hole ST.

As shown inFIG. 5C, a material that is used to form the conductive layers21is introduced to a space SP1formed where the multiple first films61are removed. For example, a foundation film54d(e.g., an aluminum oxide film) is formed; the second portion21R of the conductive layer21(e.g., a TiN film) is formed; and the first portion21W of the conductive layer21(e.g., a tungsten film) is formed. The formations of these films include, for example, CVD (Chemical Vapor Deposition), etc. Thereby, the multiple conductive layers21are formed. The second films62are used to form the insulating layers22.

As shown inFIG. 5DandFIG. 5E, the TiN film and the tungsten film recited above that are formed at the portion of the hole ST are removed by etch-back. Subsequently, the insulating portion57iand the conductive portion (the first conductive portion57A, the second conductive portion57B, etc.) are formed on the surface of the hole ST. Further, the interconnects, etc., are formed; and the semiconductor memory device110is formed.

FIG. 6AandFIG. 6Bare schematic perspective views illustrating states partway through the manufacturing of the semiconductor memory device according to the first embodiment.

FIG. 6Aillustrates the state after the process ofFIG. 5Aand prior to the process ofFIG. 5C.FIG. 6Billustrates the state after the process ofFIG. 5D. InFIG. 6B, the second film62(the insulating layer22) is not illustrated for easier viewing of the drawing.

As shown inFIG. 6A, the multiple first films61are removed; and the space SP1is formed. As shown inFIG. 6B, the conductive layers21are formed by introducing, to the space SP1, a material used to form the conductive layers21. At this time, a film of this material is grown from the wall surface of the space SP1. There are cases where the space SP1is partially plugged by the film of this material. Thereby, there are cases where a void21vis formed. The plugging occurs easily at portions where the cross-sectional area is small where the material (the gas) passes through.

For example, in the conductive layer21illustrated inFIG. 1, the void21voccurs easily in the regions where the multiple memory portions MP are provided. On the other hand, the void21vdoes not occur easily in the regions (the fifth to seventh regions Rx5to Rx7, etc.) where the memory portions MP are not provided. The distance between the sixth region Rx6and the hole ST (the first conductive portion57A and the second conductive portion57B) and the distance between the seventh region Rx7and the hole ST are short. Therefore, the void21vdoes not occur easily particularly in the sixth region Rx6and the seventh region Rx7.

For example, one of the multiple conductive layers21(e.g., the first conductive layer21a) includes a portion included in the sixth region Rx6and a portion included in the first region Rx1. The density of the voids21vin the portion included in the sixth region Rx6is lower than the density of the voids21vin the portion included in the first region Rx1. Or, the portion included in the sixth region Rx6does not include the void21v. For example, the ratio of the volume of the void21vin the portion included in the sixth region Rx6to the volume of the portion included in the sixth region Rx6is lower than the ratio of the volume of the void21vin the portion included in the first region Rx1to the volume of the portion included in the first region Rx1.

For example, the one of the multiple conductive layers21(e.g., the first conductive layer21a) further includes a portion included in the fifth region Rx5. The density of the voids21vin the portion included in the fifth region Rx5is lower than the density of the voids21vin the portion included in the first region Rx1. Or, the portion included in the fifth region Rx5does not include the void21v. The ratio of the volume of the void21vin the portion included in the fifth region Rx5to the volume of the portion included in the fifth region Rx5is lower than the ratio of the volume of the void21vin the portion included in the first region Rx1to the volume of the portion included in the first region Rx1.

FIG. 7AandFIG. 7Bare schematic cross-sectional views illustrating the semiconductor memory device according to the first embodiment.

As shown inFIG. 7A, the distance q1between the first center C1of the one M1of the multiple first memory portions MP1and the second center C2of the one M2of the multiple second memory portions MP2is larger than the first pitch p1and smaller than 2 times the first pitch p1.

The distance ww along the second direction between the one M1of the multiple first memory portions MP1recited above and the one M2of the multiple second memory portions MP2recited above is longer than the shortest distance (the distance wn) along the second direction between two of the multiple first memory portions MP1. The shortest distance (the distance wn) is, for example, shorter than ½ of the first pitch p1.

On the other hand, as shown inFIG. 7B, the length (the thickness) along the first direction (the Z-axis direction) of one of the multiple conductive layers21is taken as a thickness H1. For example, in the case where the conductive layers21are formed by a replacement method such as that recited above, the height of an inflow path PG of the material (the gas) used to form the conductive layers21(referring toFIG. 7A) corresponds to the thickness H1recited above.

In the embodiment, the distance ww is longer than the thickness H1along the first direction (the Z-axis direction) of the one of the multiple conductive layers21. Thereby, the void21vis not formed easily. On the other hand, the shortest distance (the distance wn) along the second direction between two of the multiple first memory portions MP1is not more than the thickness H1. Thereby, the multiple first memory portions MP1can be arranged at high density. In such a case, there are cases where the void21vis formed in the conductive layer21between the multiple first memory portions MP1. The practical problem of the increase of the resistance of the conductive layer21due to the void21vcan be suppressed by setting the number of the multiple first memory portions MP1to an appropriate value.

In the embodiment, it is favorable for ww>H1. It is favorable for wn≤H1. In the embodiment, ww≥H1and wn<H1are possible. Considering the fluctuation of the processes, it is favorable for ww>(1.2×H1). It is favorable for wn (1.2×H1). In the embodiment, ww≥(1.2×H1) and wn<(1.2×H1) are possible. Thereby, the density of the multiple memory portions MP can be increased while suppressing the increase of the resistance of the multiple conductive layers21due to the void21vto be in a practical range.

On the other hand, a distance b1between the one M1of the multiple first memory portions MP1recited above and the one M4of the multiple fourth memory portions MP4recited above is longer than a distance b0between the one M1of the multiple first memory portions MP1recited above and the one M3of the multiple third memory portions MP3recited above. The distance b0corresponds to the distance between the one M2of the multiple second memory portions MP2recited above and the one M4of the multiple fourth memory portions MP4recited above.

For example, in the embodiment, it is favorable for b1>H1. It is favorable for b0≤H1. In the embodiment, b1≥H1and b0<H1are possible. For example, considering the fluctuation of the processes, it is favorable for b1>(1.2×H1). It is favorable for b0<(1.2×H1). In the embodiment, b1≥(1.2×H1) and b0<(1.2×H1) are possible. Thereby, the density of the multiple memory portions MP can be increased while suppressing the increase of the resistance of the multiple conductive layers21due to the void21vto be in a practical range.

For example, the first pitch p1is taken as P1. On the other hand, the distance along the third direction between the position of the first center C1in the third direction (a direction crossing the first direction and the second direction, e.g., the Y-axis direction) and the position of the third center C3in the third direction is taken as P2. The length in the second direction (the X-axis direction) of the one M1of the multiple first memory portions MP1recited above is taken as Dx.

In the embodiment, the distance b0recited above is represented by
b0=[((P1)/2)2+(P2)2]1/2−Dx.

In such a case, it is favorable for the distance b0to be less than 1.2 times the thickness H1along the first direction of the one of the multiple conductive layers21.

The difference between the distance (the distance ww) along the second direction between the one M1of the multiple first memory portions MP1recited above and the one M2of the multiple second memory portions MP2recited above and the shortest distance (the distance wn) along the second direction between two of the multiple first memory portions MP1is taken as Pd.

In the embodiment, the distance b1recited above is represented by
b1=[((P1+Pd)/2)2+(P2)2]1/2−Dx.

In the embodiment, it is favorable for the distance b1to be greater than 1.2 times the thickness H1recited above.

In the embodiment, for example, the relationship between the spacing (for example, the distance wn, and/or for example, the distance ww) between the multiple memory portions MP and the thickness H1of the conductive layer21is determined appropriately. For example, plugging of the space between the multiple memory portions MP before the filling of the fifth region Rx5is completed is suppressed. The occurrence of the void21vin the fifth region Rx5is suppressed. The increase of the resistance of the fifth region Rx5is suppressed.

FIG. 8is a schematic cross-sectional view illustrating another semiconductor memory device according to the first embodiment.

As shown inFIG. 8, in the other semiconductor memory device111according to the embodiment as well, the distance q1along the second direction between the first center C1in the second direction (the X-axis direction) of the one M1of the multiple first memory portions MP1and the second center C2in the second direction of the one M2of the multiple second memory portions MP2is longer than the first pitch p1and shorter than 2 times the first pitch p1. In the semiconductor memory device111, the distance p2along the third direction (a direction crossing the first direction and the second direction, e.g., the Y-axis direction) between the position of the first center C1in the third direction and the position of the third center C3in the third direction is the same as the first pitch p1. Otherwise, the semiconductor memory device111is similar to the semiconductor memory device110; and a description is therefore omitted. In the semiconductor memory device111as well, a semiconductor memory device can be provided in which the storage density can be increased.

Second Embodiment

The embodiment relates to a method for manufacturing the semiconductor memory device.

The manufacturing method includes, for example, at least a portion of the processing described in reference toFIG. 4AtoFIG. 4EandFIG. 5AtoFIG. 5E.

In the manufacturing method, for example, the stacked film SBf that includes the multiple first films61arranged in the first direction (the Z-axis direction) perpendicular to the surface10aof the base body10and the second film62provided between the multiple first films61is formed on the surface10a(referring toFIG. 4A).

The multiple first memory portions MP1and the multiple second memory portions MP2are formed (referring toFIG. 1andFIG. 4D). The multiple first memory portions MP1extend in the first direction (the Z-axis direction) through the first region Rx1of the stacked film SBf and are arranged at the first pitch p1in the second direction (the X-axis direction) crossing the first direction (referring toFIG. 1andFIG. 2A). The multiple second memory portions MP2extend in the first direction (the Z-axis direction) through the second region Rx2of the stacked film SBf and are arranged at the first pitch p1in the second direction (the X-axis direction) (referring toFIG. 1andFIG. 2A). The second region Rx2is arranged with the first region Rx1in the second direction. The distance q1along the second direction between the first center C1in the second direction of the one M1of the multiple first memory portions MP1and the second center C2in the second direction of the one M2of the multiple second memory portions MP2is longer than the first pitch p1(referring toFIG. 1). The distance q1is shorter than 2 times the first pitch p1(referring toFIG. 1).

The hole ST is formed in the stacked film SBf (referring toFIG. 4E). Further, the multiple first films61are removed via the hole ST (referring toFIG. 5A).

The material that is used to form the conductive layers21is introduced to the space SP1formed where the multiple first films61are removed (referring toFIG. 5C).

According to the manufacturing method, a method for manufacturing a semiconductor memory device can be provided in which the storage density can be increased.

The embodiment may include, for example, the following configurations.

A semiconductor memory device, including:

a stacked body including multiple conductive layers arranged in a first direction, the multiple conductive layers extending in a second direction crossing the first direction, the stacked body including a first region and a second region, the second region being arranged with the first region in the second direction;

multiple first memory portions extending in the first direction through the first region and being arranged at a first pitch along the second direction; and

multiple second memory portions extending in the first direction through the second region and being arranged at the first pitch along the second direction,

a distance along the second direction between a first center in the second direction of one of the multiple first memory portions and a second center in the second direction of one of the multiple second memory portions being longer than the first pitch and shorter than 2 times the first pitch.

The semiconductor memory device according to Configuration 1, wherein number of the multiple first memory portions is not less than 3 and not more than 100.

The semiconductor memory device according to Configuration 1 or 2, wherein a distance along the second direction between the one of the multiple first memory portions and the one of the multiple second memory portions is not less than 1.2 times a thickness along the first direction of one of the multiple conductive layers.

The semiconductor memory device according to Configuration 3, wherein a shortest distance along the second direction between two of the multiple first memory portions is shorter than 1.2 times the thickness.

The semiconductor memory device according to Configuration 1 or 2, wherein the distance along the second direction between the one of the multiple first memory portions and the one of the multiple second memory portions is longer than a shortest distance along the second direction between two of the multiple first memory portions.

The semiconductor memory device according to any one of Configurations 1 to 5, further including:

multiple third memory portions extending in the first direction through the first region and being arranged at the first pitch along the second direction; and

multiple fourth memory portions extending in the first direction through the second region and being arranged at the first pitch along the second direction,

a distance along the second direction between a third center in the second direction of one of the multiple third memory portions and a fourth center in the second direction of one of the multiple fourth memory portions being longer than the first pitch and shorter than 2 times the first pitch.

The semiconductor memory device according to Configuration 6, wherein a position in the second direction of the first center is between a position in the second direction of the third center and a position in the second direction of the fourth center.

The semiconductor memory device according to Configuration 7, wherein the position in the second direction of the fourth center is between the position in the second direction of the first center and a position in the second direction of the second center.

The semiconductor memory device according to any one of Configurations 6 to 8, wherein a distance along the third direction crossing the first direction and the second direction between the position of the first center in the third direction and the position of the third center in the third direction is shorter than the first pitch.

The semiconductor memory device according to any one of Configurations 6 to 9, wherein
b0=[((P1)/2)2+(P2)2]1/2−Dx, and

b0is less than 1.2 times the thickness along the first direction of one of the multiple conductive layers, where

P1is the first pitch,

P2is the distance along the third direction crossing the first direction and the second direction between the position of the first center in the third direction and the position of the third center in the third direction, and

Dx is the length in the second direction of the one of the multiple first memory portions.

The semiconductor memory device according to Configuration 10, wherein
b1=[((P1+Pd)/2)2+(P2)2]1/2−Dx, and

b1is not less than 1.2 times the thickness, where

Pd is the difference between the distance along the second direction between the one of the multiple first memory portions and the one of the multiple second memory portions and the shortest distance along the second direction between the two of the multiple first memory portions.

The semiconductor memory device according to any one of Configurations 1 to 11, further including:

multiple fifth memory portions; and

multiple sixth memory portions,

the stacked body further including a third region, a fourth region, and a fifth region,

the third region being arranged with the first region in the third direction crossing the first direction and the second direction,

the fourth region being arranged with the third region in the second direction and arranged with the second region in the third direction,

the fifth region being positioned between the first region and the third region and between the second region and the fourth region,

the multiple fifth memory portions extending in the first direction through the third region and being arranged at the first pitch along the second direction,

the multiple sixth memory portions extending in the first direction through the fourth region and being arranged at the first pitch along the second direction,

the fifth region being continuous in the second direction.

The semiconductor memory device according to Configuration 12, wherein a width along the third direction of the fifth region is greater than a distance between two of the multiple first memory portions.

The semiconductor memory device according to Configuration 12 or 13, wherein

the stacked body further includes a sixth region and a seventh region,

the first to fifth regions are positioned between the sixth region and the seventh region,

the sixth region is continuous in the second direction, and

the seventh region is continuous in the second direction.

The semiconductor memory device according to

one of the multiple conductive layers includes a portion included in the sixth region and a portion included in the first region, and

the ratio of a volume of a void in the portion included in the sixth region to a volume of the portion included in the sixth region is lower than the ratio of a volume of a void in the portion included in the first region to a volume of the portion included in the first region, or

the portion included in the sixth region does not include a void.

The semiconductor memory device according to Configuration 15, wherein

the one of the multiple conductive layers further includes a portion included in the fifth region, and

the ratio of a volume of a void in the portion included in the fifth region to a volume of the portion included in the fifth region is lower than the ratio of the volume of the void in the portion included in the first region to the volume of the portion included in the first region, or

the portion included in the fifth region does not include a void.

The semiconductor memory device according to any one of Configurations 1 to 16, wherein a length in the second direction of the one of the multiple first memory portions is longer than ½ of the first pitch.

The semiconductor memory device according to any one of Configurations 1 to 17, wherein the shortest distance along the second direction between the two of the multiple first memory portions is shorter than ½ of the first pitch.

The semiconductor memory device according to any one of Configurations 1 to 18, wherein

the one of the multiple first memory portions includes:a semiconductor body extending in the first direction through the stacked body;a first memory insulating film provided between the semiconductor body and the multiple conductive layers;a second memory insulating film provided between the semiconductor body and the first memory insulating film; anda memory film provided between the first memory insulating film and the second memory insulating film.
Configuration 20

A method for manufacturing a semiconductor memory device, including:

forming a stacked film on a surface of a base body, the stacked film including multiple first films and a second film, the multiple first films being arranged in a first direction perpendicular to the surface, the second film being provided between the multiple first films;

forming multiple first memory portions and multiple second memory portions, the multiple first memory portions extending in the first direction through a first region of the stacked film and being arranged at a first pitch in a second direction crossing the first direction, the multiple second memory portions extending in the first direction through a second region of the stacked film and being arranged at the first pitch in the second direction, the second region being arranged with the first region in the second direction, a distance along the second direction between a first center in the second direction of one of the multiple first memory portions and a second center in the second direction of one of the multiple second memory portions being longer than the first pitch and shorter than 2 times the first pitch;

forming a hole in the stacked film and removing the multiple first films via the hole; and

introducing a material to a space formed where the multiple first films are removed, the material being used to form a conductive layer.

According to the embodiments, a semiconductor memory device and a method for manufacturing the semiconductor memory device are provided in which the storage density can be increased.

Hereinabove, exemplary embodiments of the invention are described with reference to specific examples. However, the embodiments of the invention are not limited to these specific examples. For example, one skilled in the art may similarly practice the invention by appropriately selecting specific configurations of components included in semiconductor memory devices such as conductive layers, insulating layers, memory portions, semiconductor bodies, memory layers, memory insulating films, memory films, base bodies, etc., from known art. Such practice is included in the scope of the invention to the extent that similar effects thereto are obtained.

Moreover, all semiconductor memory devices and methods for manufacturing the same practicable by an appropriate design modification by one skilled in the art based on the semiconductor memory devices and the methods for manufacturing the same described above as embodiments of the invention also are within the scope of the invention to the extent that the purport of the invention is included.