Superconducting nanowire single photon detector and method of fabrication thereof

A superconductor device according to some embodiments comprises a superconductor stack, which includes a superconductor layer and a silicon cap layer over the superconductor layer, the cap layer including amorphous silicon. The superconductor device further comprises a metal contact over a portion of the silicon cap layer and electrically-coupled to the superconductor layer. The metal contact comprises a core including a first metal, and an outer layer around the core that includes a second metal. The portion of the silicon cap layer is converted from silicon to a conductive compound including the second metal to provide low-resistance electrical coupling between the superconductor layer and the metal contact. The superconductor device further comprises a waveguide, and the first portion of the cap layer under the metal contact is at a sufficient lateral distance from the waveguide to prevent optical coupling between the metal contact and the waveguide.

CROSS REFERENCE TO RELATED APPLICATIONS

The present application is a non-provisional of U.S. Provisional Application No. 62/834,924, filed Apr. 16, 2019, entitled “Superconducting Nanowire Single Photon Detector and Method of Fabrication Thereof,” which is incorporated herein in its entirety.

TECHNICAL FIELD

This relates generally to photonic devices and, more specifically, to a superconducting nanowire single photon detector and method of fabrication thereof.

BACKGROUND

A superconducting nanowire single photon detector (SNSPD) can have a high sensitivity to single photon events. During operation, a nanowire in the SNSPD can be cooled to, for example, 2.5 K, well below its superconducting critical temperature. Upon absorption of a photon in the nanowire, superconductivity is locally broken, and a change in current is detected as a voltage pulse by associated amplification electronics. In many configurations, the SNSPD's critical temperature depends on the quality of a thin film of material forming the nanowire, with lower quality films exhibiting lower critical temperatures. Therefore, significant research efforts have been devoted to improving the design and quality of thin films for SNSPDs in order to achieve higher operation temperatures.

SUMMARY

A superconductor device according to some embodiments comprises a superconductor stack, which includes a barrier layer (e.g., a layer including silicon and nitrogen), a seed layer over the barrier layer, a superconductor layer over the seed layer, and a silicon cap layer over the superconductor layer, the silicon cap layer including amorphous silicon, polysilicon, or single-crystal silicon. In some embodiments, the silicon cap layer includes amorphous silicon (or a-Si), as a-Si can be deposited at relative low temperature (e.g., ˜75 degrees Celsius) with little or no damage to the underlying superconductor layer. In some embodiments, the superconductor stack further comprises sidewalls adjacent to the barrier layer, the seed layer, the superconductor layer, and the silicon cap layer. In some embodiments, the seed layer includes aluminum and nitrogen (e.g., aluminum nitride), the superconductor layer includes niobium and one or more of nitrogen, titanium, aluminum, germanium, and tin (e.g., NbN, NbTi, NbAl, NbGe, NbSn, etc.), the sidewalls includes silicon and nitrogen (e.g., silicon nitride). In some embodiments, the superconductor layer includes niobium nitride. In some embodiments, the superconductor stack further comprises a protective layer between the superconductor layer and the silicon cap layer. The optional protective layer helps to prevent oxidation of the superconductor layer during fabrication of the superconductor stack. In some embodiments, the protective layer includes aluminum and nitrogen (e.g., aluminum nitride). In some embodiments, the superconductor stack is adjacent to one or more dielectric layers (e.g., silicon dioxide). The barrier layer and the sidewalls function as barriers between superconducting layer and the one or more dielectric layers, preventing or reducing oxidation of superconducting layer from any oxygen released from one or more dielectric layers during and/or after fabrication of the superconductor stack.

The superconductor device further comprises a metal contact over a portion of the silicon cap layer and electrically-coupled to a portion of the superconductor layer. In some embodiments, the portion of the silicon cap layer is converted from amorphous silicon to a conductive compound to provide electrical coupling between the superconductor layer and the metal contact. In some embodiments, the metal contact comprises a core including a first metal, and an outer layer around the core that includes a second metal. In some embodiments, the conductive compound is a metal compound (e.g., metal silicide) including the second metal.

In some embodiments, the superconductor device further comprises a waveguide, and the first portion of the silicon cap layer under the metal contact is at a distance from the waveguide. The distance is sufficiently great to prevent optical coupling (e.g., evanescent coupling) between the metal contact and the waveguide. In some embodiments, the distance is dependent on a range of wavelengths of photons to be transferred via the waveguide. In some embodiments, the distance is at least 800 nm. In some embodiments, the waveguide is formed by patterning a semiconductor layer of a semiconductor-on-insulator wafer.

The superconductor device further comprises dielectric layer over the superconductor stack and a metal routing layer over the dielectric layer. The dielectric layer has a thickness sufficient to prevent optical coupling (e.g., evanescent coupling) between the waveguide and the metal routing layer. The thickness is dependent on a range of wavelengths of photons to be transferred via the waveguide. In some embodiments, the thickness is at least 800 nm.

A method of fabricating a superconductor device comprises obtaining a substrate including a semiconductor, and forming a multilayer film on the substrate. In some embodiments, forming the multilayer film comprises depositing a barrier layer, depositing a seed layer, depositing a superconductor layer, and depositing a silicon cap layer over the superconductor layer. In some embodiments, forming the multilayer film further comprises depositing a first protective layer after depositing the superconductor layer and before depositing the silicon cap layer. In some embodiments, the silicon cap layer including amorphous silicon, polysilicon, or single-crystal silicon, the superconductor layer includes a niobium and one or more of nitrogen, titanium, aluminum, germanium, and tin (e.g., NbN, NbTi, Nb3Al, Nb3Ge, Nb3Sn, etc.), the seed layer includes aluminum and nitrogen (e.g., aluminum nitride), the barrier layer including silicon and nitrogen (e.g., silicon nitride).

In some embodiments, obtaining the substrate comprises patterning a semiconductor layer of a semiconductor-on-insulator wafer to form a waveguide, depositing a dielectric layer over the waveguide, and planarizing the dielectric layer.

The method of fabricating a superconductor device further comprises patterning the multilayer film to form a multilayer stack and, after forming the multilayer stack, depositing a protective layer over the multilayer stack, and anisotropically etching the second protective layer to form a plurality of sidewalls on the multilayer stack. In some embodiments, the protective layer includes silicon and nitrogen (e.g., silicon nitride). In some embodiments, after forming the sidewalls, a hydrogen anneal is applied to remove oxygen from the superconductor layer.

The method of fabricating a superconductor device further comprises, after forming the superconductor stack, depositing a dielectric layer, and forming an electrical contact through the dielectric layer to a portion of the superconductor layer. In some embodiments, forming the electrical contact comprises etching a cavity in the dielectric layer to expose a portion of the silicon cap layer, depositing a first metal to coat the portion of the silicon cap layer and exposed surfaces of the dielectric layer, converting the portion of the silicon cap layer into a conductive compound, and depositing a second metal to fill the cavity. In some embodiments, the materials for the silicon cap layer and the first metal are selected so as to enable silicide formation of the portion of the silicon cap layer at temperatures below 600 degrees Celsius. In some embodiment, the first metal is selected to be a metal capable of being deposited at temperatures below 600 degrees Celsius. In some embodiments, the material for the silicon cap layer and the dielectric layer are selected so as to allow etching the cavity through the dielectric layer without punching through the silicon cap layer.

In some embodiments, forming the electrical contact further comprises forming a metal pad or a metal line over the cavity, the metal pad or metal line being connected to the second metal.

Like reference numerals refer to corresponding parts throughout the several views of the drawings. For ease of illustration, the drawings may not be drawn to scale unless stated otherwise.

DETAILED DESCRIPTION

It will also be understood that, although the terms first, second, etc. are, in some instances, used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first dielectric layer could be termed a second dielectric layer, and, similarly, a second dielectric layer could be termed a first dielectric layer, without departing from the scope of the various described embodiments. The first dielectric layer and the second dielectric layer are both dielectric layers, but they are not the same dielectric layer.

A1. In some embodiments, a superconductor device comprises: a barrier layer including silicon and nitrogen; a seed layer over the barrier layer, the seed layer including aluminum and nitrogen; a superconductor layer over the seed layer, the superconductor layer including a layer of a superconductor material; and a cap layer including silicon over the superconductor layer.

A2. In some embodiments, the superconductor device of A1 further comprises a metal contact. The cap layer has a converted portion including a conductive compound to provide electrical coupling between the superconductor layer and a metal contact, and the metal contact is over the conductive compound and electrically-coupled to the superconductor layer via the conductive compound.

A3. In some embodiments, in the superconductor device of A2, the metal contact comprises a core including a first metal; and an outer layer around the core and including a second metal; the conductive compound includes a silicide of the second metal.

A4. In some embodiments, the superconductor device of any of A2-A3 further comprises a waveguide; and the metal contact is at a sufficient lateral distance from the waveguide to prevent optical coupling between the metal contact and the waveguide.

A5. In some embodiments, in the superconductor device of A4, the lateral distance is at least 800 nm.

A6. In some embodiments, the superconductor device of any of A1-A5 further comprises: a dielectric layer over the cap layer; and a metal routing layer over the dielectric layer, the dielectric layer has a thickness sufficient to prevent optical coupling between the waveguide and the metal routing layer.

A7. In some embodiments, in the superconductor device of A6, the thickness is at least 800 nm.

A8. In some embodiments, the superconductor device of any of A1-A7 further comprises: a substrate; a waveguide over the substrate; and a dielectric layer over the waveguide, the barrier layer is over the dielectric layer.

A9. In some embodiments, in the superconductor device of A8, the substrate is part of a semiconductor-on-insulator substrate having a semiconductor layer on an insulator layer, and the waveguide includes a portion of the semiconductor layer.

A10. In some embodiments, the superconductor device of any of A1-A9 further comprises: sidewalls adjacent to the barrier layer, the seed layer, the superconductor layer, and the cap layer, the sidewalls include silicon and nitrogen.

A11. In some embodiments, in the superconductor device of any of A1-A10, the superconductor material includes niobium and one or more of nitrogen, titanium, aluminum, germanium, and tin.

A12. In some embodiments, in the superconductor device of any of A1-A10, the superconductor material includes niobium nitride.

A13. In some embodiments, in the superconductor device of any of A1-A12, the cap layer includes one or more of amorphous silicon, polysilicon, and single-crystal silicon.

A14. In some embodiments, in the superconductor device of any of A1-A12, the cap layer includes amorphous silicon.

A15. In some embodiments, the superconductor device of any of A1-A14 further comprises a protective layer between the superconductor layer and the cap layer, the protective layer including aluminum and nitrogen.

A16. In some embodiments, in the superconductor device of A15, the protective layer is 5-10 nm thick.

A17. A method of manufacturing a superconductor device comprises depositing a barrier layer over a substrate including silicon, the barrier layer including silicon and nitrogen; depositing a seed layer over the barrier layer, the seed layer including aluminum and nitrogen; depositing a superconductor layer over the seed layer, the superconductor layer including a layer of a superconductor material; and depositing a silicon cap layer over the superconductor layer.

A18. In some embodiments, the method of A17 further comprises patterning the silicon cap layer, the superconductor layer, the seed layer and the barrier layer to form a multilayer stack.

A19. In some embodiments, the method of A18 further comprises, after forming the multilayer stack: depositing a layer of protective material over the multilayer stack; and anisotropically etching the layer of protective material to form a plurality of sidewalls on sides of the multilayer stack.

A20. In some embodiments, the method of A19 further comprises, after forming the sidewalls, applying a hydrogen anneal to remove oxygen from the superconductor layer.

A21. In some embodiments, the method of any of A18-A20 further comprises, after forming the multilayer stack: depositing a dielectric layer; and forming an electrical contact through the dielectric layer to a portion of the superconductor layer. In some embodiments, forming the electric contact comprises: etching a cavity in the dielectric layer to expose a portion of the silicon cap layer in the dielectric layer; depositing a first metal to coat the portion of the silicon cap layer and exposed surfaces of the dielectric layer; converting the portion of the silicon cap layer into a conductive compound; and depositing a second metal to fill the cavity.

A22. In some embodiments, in the method of A21, forming the electrical contact further comprises forming a metal pad or a metal line over the cavity, the metal pad or metal line being connected to the second metal.

A23. In some embodiments, in the method of any of A21-A22, the first metal is selected from the group consisting of titanium, nickel, and cobalt.

A24. In some embodiments, in the method of A23, the second metal is selected from the group consisting of tungsten, aluminum, and copper.

A25. In some embodiments, in the method of any of A21-A24, the substrate includes a waveguide, and the portion of the silicon cap layer is located at a sufficient lateral distance from the waveguide to prevent optical coupling between the waveguide and the electrical contact.

A26. In some embodiments, in the method of A25, the lateral distance is at least 800 nm.

A27. In some embodiments, the method of any of A17-A26 further comprises obtaining the substrate. In some embodiments, obtaining the substrate comprises: patterning a semiconductor layer of a semiconductor-on-insulator wafer to form a waveguide; depositing a dielectric layer over the waveguide; and planarizing the dielectric layer.

A28. The method of any of A17-A27, the superconductor material includes niobium and one or more of nitrogen, titanium, aluminum, germanium, and tin.

A29. The method of any of A17-A27, the superconductor material includes niobium nitride.

A30. The method of any of A17-A29, the silicon cap layer includes one or more of amorphous silicon, polysilicon, and single-crystal silicon.

A31. The method of any of A17-A29, the silicon cap layer includes amorphous silicon.

A32. In some embodiments, the method of any of A17-A31 further comprises depositing a first protective layer after depositing the superconductor layer and before depositing the silicon cap layer, the protective layer including aluminum and nitrogen.

A33. In some embodiments, in the method of A32, the protective layer is 5-10 nm thick.

FIG. 1Ais a plan view of an SNSPD100in an x-y plane according to some embodiments. As shown, SNSPD100includes a superconductor stack102including a nanowire portion110, connector portions121,122, and contact portions123,124. Nanowire portion110includes parallel line segments111and joining segments112together forming a meandering superconducting nanowire. In some embodiments, as shown in the inset inFIG. 1A, which provides a zoomed-in view of a joining segment112, the joining segment112can have a curved inner perimeter113between two neighboring line segments111joined by the joining segment112. In some embodiments, the curved inner perimeter provides a smooth transition between the two neighboring line segments to minimize current crowding effects. In some embodiments, nanowire portion110is fabricated over an optical waveguide structure (or waveguide)105to improve optical coupling efficiency. In some embodiments, as shown inFIG. 1A, nanowire portion110is wider than waveguide105to further improve the optical coupling efficiency.

As an example,FIG. 1Ashows an area occupied by nanowire portion110being somewhat rectangular in shape. In practice, the nanowire portion can have any of a variety of geometrical configurations. For example, the nanowire can form one or more U-shapes, as shown inFIG. 1F. In some embodiments, the nanowire portion110can have a geometry that is independent of that of waveguide105, as discussed below with respect toFIG. 2D. Most generally, one or more embodiment disclosed herein can have any geometry without departing from the scope of the present disclosure.

As shown inFIG. 1A, contact portion123is connected to a first end115of nanowire portion110via connector portion121, and contact portion124is connected to a second end116of nanowire portion110via connector portion122. In some embodiments, SNSPD100further includes metal contacts (not shown inFIG. 1A) over contact portions123,124. To prevent or reduce optical coupling (e.g., evanescent coupling) between the metal contacts and waveguide105, contact portions123,124are disposed (e.g., spaced apart) at a distance D (e.g., a lateral distance measured in the x-y plane) from waveguide105. Distance D is dependent on a wavelength of photons to be transferred via the waveguide105. In some embodiments, distance D can be at least 500 nm, e.g., 800 nm. Superconductor stack102and waveguide105are disposed on a substrate101.

FIG. 1Bis a cross-sectional view of SNSPD100in an y-z plane cut across line segments111of nanowire portion110(along line A-A′ inFIG. 1A), according to some embodiments. As shown, SNSPD100has a layered structure, including a first dielectric layer104over substrate101, waveguide105over first dielectric layer104, a second dielectric layer106over and around waveguide105and serving as cladding for waveguide105, superconductor stack102over second dielectric layer106, a third dielectric layer108encapsulating superconductor stack102, and additional layers and structures not shown inFIG. 1B. In other words, first dielectric layer104is located between substrate101and waveguide105, waveguide105is located between first dielectric layer104and a first portion of second dielectric layer106, a second portion of second dielectric layer106is located around waveguide105and over first dielectric layer104, and superconductor stack102is located between second dielectric layer106and a portion of third dielectric layer108. In some embodiments, first dielectric layer104functions as a buffer layer between substrate101and waveguide105and has a thickness of at least 20 nm.

FIG. 1Balso includes an inset showing a zoomed-in view of the cross-section of one of the line segments111and a corresponding portion of waveguide105, according to some embodiments. As shown, multi-layer stack102includes a barrier layer130, a seed layer132over the barrier layer130, a superconductor layer134over the seed layer132, and a silicon cap layer (or cap layer)136over the superconductor layer134. In other words, seed layer132is located between barrier layer130and superconductor layer134, and superconductor layer134is located between seed layer132and cap layer136). SNSPD100may further include sidewalls138-A and138-B flanking opposing sides of superconductor stack102. In some embodiments, barrier layer130includes silicon and nitrogen (e.g., silicon nitride), seed layer132includes aluminum and nitrogen (e.g., aluminum nitride), superconductor layer134includes niobium and one or more of nitrogen, titanium, aluminum, germanium, and tin (e.g., NbN, NbTi, NbAl, NbGe, NbSn, etc.), cap layer136includes silicon (e.g., amorphous silicon or a-Si, polysilicon or poly-Si, or single-crystal silicon or mono c-Si), and sidewalls138-A and138-B include silicon and nitrogen (e.g., silicon nitride).

As shown inFIG. 1B, a portion106A of second dielectric layer106is located between waveguide105and barrier layer130. Also, a portion of third dielectric layer108is located over the cap layer136, and a portion of first dielectric layer104is located between waveguide105and substrate101.FIGS. 1A and 1Billustrate some vertical and horizontal dimensions of SNSPD100, as listed below:L1: width of superconducting layer134in each line segment111of nanowire portion110;L2: width of space between two neighboring line segments111of nanowire portion110;L3: thickness of the portion106A of second dielectric layer106;L4: thickness of barrier layer130;L5: thickness of seed layer132;L6: thickness of superconductor layer134;L7: thickness of cap layer136;L8: thickness of sidewalls138-A and138-B;L9: thickness of waveguide105;L10: thickness of third dielectric layer108;
In some embodiments:L1is greater than 20 nanometers (nm) and less than 200 nm (i.e., 20 nm<L1<200 nm);L2is greater than 20 nm and less than 300 nm (i.e., 30 nm<L2<300 nm);L3is greater than 10 nm and less than 100 nm (i.e., 10 nm<L3<100 nm);L4, L5, L6and L7are each greater than 2 nm and less than 40 nm (i.e., 2 nm<L4, L5, L6, L7<40 nm);L8is greater than 1 nm and less than 20 nm (i.e., 1<L8<20 nm);L9is greater than 100 nm and less than 1 micrometer (1 μm) (i.e., 100 nm<L9<1 μm);L10is greater than 800 nm and less than 100 μm (e.g., 800 nm<L10<20 μm); and
In some embodiments:L1is greater than 45 nm and less than 100 nm (i.e., 45 nm<L1<100 nm);L2is greater than 45 nm and less than 200 nm (i.e., 45 nm<L2<200 nm);L3is greater than 20 nm and less than 50 nm (i.e., 20 nm<L3<50 nm);L4is greater than 5 nm and less than 20 nm (i.e., 5 nm<L4<20 nm);L5and L6are each greater than 5 nm and less than 20 nm (i.e., 5 nm<L5, L6<20 nm);L7is greater than 3 nm and less than 20 nm (i.e., 3 nm<L7<20 nm);L8is greater than 2 nm and less than 10 nm (i.e., 2<L8<10 nm);L9is greater than 150 nm and less than 500 nm (i.e., 150 nm<L9<500 nm);L10is greater than 1 μm and less than 10 μm (i.e., 1 μm<L10<10 μm).

In some embodiments, the width L1and thickness L6of superconductor layer134are selected based on the wavelength of the photons to be detected. In some embodiments, L10is designed to be sufficiently large to prevent any optic coupling (e.g., evanescent coupling) between metal lines (not shown) formed over dielectric layer108and waveguide105or superconductor stack102. In some embodiments, the sum of L3, L4, and L5is small enough to enable optical coupling (e.g., evanescent coupling) between superconductor layer134and the waveguide105(e.g., L3+L4+L5<200 nm).

FIG. 1Cis nearly identical toFIG. 1Bexcept that the inset inFIG. 1Cshows superconductor stack102further including an optional protective layer131between superconductor layer134and cap layer136, according to some embodiments. In some embodiments, protective layer131includes aluminum and nitrogen (e.g., aluminum nitride). In some embodiments, the protective layer has a thickness L11greater than 5 nm and less than 10 nm (e.g., 5 nm<L11<10 nm). In some embodiments, L11greater than 1 nm and less than 5 nm (e.g., 1 nm<L11<5 nm) In some embodiments, protective layer131can be included to prevent oxidation of superconductor layer134during fabrication of SNSPD100, if fabrication facilities used to fabricate SNSPD do not provide in-situ deposition of superconductor layer134and cap layer136.

FIG. 1Dis a cross-sectional view of SNSPD100cut across contact portions123(along line B-B′ inFIG. 1A), according to some embodiments. As shown, SNSPD100further includes a contact140above contact portion123of superconductor stack102. According to some embodiments, contact140includes a contact core141in a contact hole142formed in dielectric layer108. SNSPD100further includes a contact liner or outer layer143between contact core141and dielectric layer108. Contact140further includes a contact pad (or metal line)145above and electrically coupled with contact core141and contact liner143. Contact core141includes a metallic material, such as tungsten, aluminum, copper, etc. Contact liner143may include a same or different metallic material, such as titanium (Ti), nickel (Ni), cobalt (Co), etc. In some embodiments, as shown inFIG. 1D, contact hole142has a diameter (or horizontal dimension) d1of about 100 nm or more near bottom146and a diameter (or horizontal dimension) d2of about 100 nm or more near contact pad145, and contact liner143has a thickness t1of about 5 nm-100 nm.

FIG. 1Dalso includes an inset showing a zoomed in view of an area147near a bottom146of contact140. As shown, a region137of cap layer136under and adjacent bottom146of contact140is converted to a conductive compound138, which provides low-resistance electrical coupling between contact140and superconducting layer134. In some embodiments, contact hole lining143includes Ti, Ni or Co and conductive compound138includes titanium silicide, nickel silicide, or cobalt silicide respectively.

FIG. 1Eillustrates a cross-sectional view of SNSPD100cut across contact portions123(along line B-B′ inFIG. 1A), with an inset showing superconductor stack102further including a protective layer131between superconductor layer134and cap layer136, according to some embodiments, as discussed above with reference toFIG. 1C. In some embodiments, as shown in the inset inFIG. 1E, when protective layer131is provided, contact hole142extends through protective layer131.

FIGS. 2A through 2Q, together withFIG. 3, illustrate a method300of manufacturing SNSPD100, according to some embodiments. As shown inFIGS. 2A-2D and 3, method300includes obtaining a substrate (310). In some embodiment, as shown inFIG. 2A, obtaining a substrate (310) may start with a semiconductor-on-insulator (SOI) substrate201that includes a semiconductor (e.g., silicon, gallium arsenide, etc.) substrate101, an insulator layer (e.g., dielectric layer104) over the semiconductor substrate101, and a semiconductor (e.g., silicon, gallium arsenide, etc.) film205over the insulator layer104. As shown inFIG. 2B, obtaining a substrate (310) may further include patterning the semiconductor layer205(312) using, for example, photolithography and anisotropic etching (e.g., plasma or reactive ion etching), to form waveguide105on dielectric layer104. As shown inFIGS. 2C and 2D, obtaining a substrate (310) may further include forming a dielectric layer (314) over waveguide105and dielectric layer104, which may include, for example, depositing a dielectric (e.g., silicon dioxide) layer206over substrate201using, for example, chemical vapor deposition. Dielectric layer206is then planarized to form dielectric layer106using, for example, chemical mechanical polishing, resulting in a flat surface106a, on which a superconductor nanowire of any of various shapes and dimensions can be fabricated. For example, the superconductor nanowire to be formed over the cladding (e.g., dielectric layer106) of waveguide105can be wider than waveguide105. In some embodiments, the obtained substrate (e.g., substrate200) includes substrate101, dielectric layer104, waveguide105, and dielectric layer106, as shown inFIG. 2D.

As shown inFIG. 3, method300further includes fabricating a superconductor stack (320) over the obtained substrate (e.g., substrate200). In some embodiments, as shown inFIGS. 3 and 2E, fabricating the superconductor stack (320) includes forming322on substrate200a multilayer thin film210. In some embodiments, multilayer thin film210includes a layer of a first material230, a layer of a second material232formed over (e.g., on top of, on a surface of) the layer of the first material230, a layer of a third material234formed over (e.g., on top of, on a surface of) the layer of the second material232, and a layer of a fourth material236formed over (e.g., on top of, on a surface of) the layer of the third material234. In some embodiments, the layer of the first material230includes silicon and nitrogen (e.g., silicon nitride), the layer of the second material232includes aluminum and nitrogen (e.g., aluminum nitride), the layer of the third material234includes niobium and one or more of nitrogen, titanium, aluminum, germanium, and tin (e.g., NbN, NbTi, NbAl, NbGe, NbSn, etc.), and the layer of the fourth material236includes silicon (e.g., a-Si, poly-Si, or mono c-Si). In some embodiments, each layer in the multilayer thin film210has a thickness that is greater than 2 nm and less than 40 nm. In some embodiments, the layer of the first material230is greater than 10 nm and less than 20 nm, the layer of the second material232and the layer of the third material234are each greater than 5 nm and less than 10 nm, the layer of the fourth material236is greater than 3 nm and less than 10 nm.

In some embodiments, the layer of the first material230is deposited onto substrate200using a process suitable for depositing an ultrathin film (e.g., 10 nm-20 nm) including silicon and nitrogen (e.g., silicon nitride), such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), catalytic chemical vapor deposition (Cat-CVD), hot wire chemical vapor deposition (HWCVD), etc. In some embodiments, the layer of the second material232is deposited onto the first layer of material230using a process suitable for depositing an ultrathin film (e.g., 5 nm-10 nm) including aluminum and nitrogen (e.g., aluminum nitride), such as, for example, CVD, PECVD, PVD, magnetron sputtering (MS), molecular beam epitaxy (MBE), atomic layer deposition (ALD), Plasma-Enhanced Atomic Layer Deposition (or PEALD), etc. In some embodiments, the layer of the third material234is deposited onto the layer of the second material232using a process suitable for depositing an ultrathin (e.g., 2 nm-40 nm) film including a superconductor compound (e.g., NbN, NbTi, NbAl, NbGe, or NbSn), such as, for example, CVD, PVD, PECVD, MS, MBE, ALD, PEALD, etc. In some embodiments, the layer of the fourth material236is deposited onto the layer of the third material234using a process suitable for depositing an ultrathin (e.g., 2 nm-40 nm) film including silicon (e.g., a-Si, poly-Si, or mono c-Si), such as, for example, CVD, PECVD, MS, MBE, ALD, PEALD, etc. In some embodiment, the layer of the fourth material236includes a-Si because a-Si can be deposited at relative low temperature (e.g., ˜75 degrees Celsius) using a CVD process that causes little or no damage the underlying superconductor layer234.

In some embodiments, as shown inFIGS. 3 and 2F, fabricating the superconductor stack (320) further includes patterning324multilayer thin film210to form a patterned multilayer stack212using a plurality of fabrication processes including, for example, a high-resolution lithography process to form a mask on multilayer thin film210, and one or more anisotropic etching processes to successively etch away exposed portions of the layer of the fourth material236, the layer of the third material234, the layer of the second material232, and the layer of the first material230. At least the layer of the first material230is etched using an anisotropic process that is selective to dielectric layer106.FIG. 2Fshows a cross-sectional view of the resulting multilayer stack212, according to some embodiments.

After multilayer stack212is formed by patterning324multilayer thin film210, the remaining portion of the layer of the first material230becomes barrier layer130, the remaining portion of the layer of the second material232becomes seed layer132, the remaining portion of the layer of the third material234becomes superconducting layer134, and the remaining portion of the layer of the fourth material236becomes cap layer136. In some embodiments, the layer of the second material232acts as a seed layer for improved surface morphology during subsequent deposition of the layer of the third material234, resulting in enhanced qualities of superconducting layer134. Barrier layer130acts as a barrier between superconducting layer134and dielectric layer106, preventing or reducing oxidation of superconducting layer134from oxygen released from dielectric layer106during and/or after fabrication of SNSPD100.

In certain embodiments, as shown inFIG. 2G, multilayer thin film210further includes an optional layer of a fifth material231formed over the layer of the third material234and before forming the layer of the fourth material236. In some embodiments, the layer of the fifth material231includes aluminum and nitrogen (e.g., aluminum nitride), and has a thickness that is greater than 1 nm and less than 10 nm, or greater than 1 nm and less than 5 nm. When multilayer thin film210further includes the layer of a fifth material231, patterning324multilayer thin film210further includes etching the layer of the fifth material231after etching the layer of the fourth material236and before etching the other layers in the multilayer thin film210, to form protective layer131, as shown inFIG. 2H. In some embodiments, protective layer131can be used to protect superconductor layer134from exposure to atmosphere during fabrication of SNSPD100. For example, if the fabrication facility/process chamber used to form the layer of the fourth material236(e.g., a-silicon) must be isolated from one or more materials that are used to form the layer of the third material234(e.g., NbN), substrate101or200may first need to be brought up to atmosphere and transferred from one process chamber that is used to deposit the NbN to another process chamber that is used to deposit a-silicon.

In some embodiments, as shown inFIG. 3, fabricating the superconductor stack320further includes forming326sidewalls on two opposing sides241and242of multilayer stack212by depositing a layer of sidewall materials238that conforms to contours of multilayer stack212, as shown inFIG. 2I. In some embodiments, the layer of sidewall materials238can be deposited using, for example, chemical vapor deposition, to cover a top243and the two opposing sides241and242of multilayer stack212, as well as portions of dielectric layer106not under (or covered) multilayer stack212. Portions of the layer of sidewall material on top of multilayer stack212and on dielectric layer106are then removed in an anisotropic etching process, leaving sidewalls138-A and138-B on sides241and242of multilayer stack212, respectively. The sidewall material238can be including, for example, silicon and nitrogen (e.g., silicon nitride), and the remaining sidewalls138-A and138-B each has a thickness greater than 500 Angstrom and less than 2 nm.

In some embodiments, as shown inFIGS. 3 and 2K, fabricating the superconductor stack (320) further includes subjecting substrate200, along with the structures formed thereon, to an anneal process328to allow oxygen atoms or molecules250trapped in or near superconducting layer134to escape the multilayer stack212. After the annealing process328, the patterned multilayer stack212, together with sidewalls138-A and138-B, become the fabricated superconductor stack, such as either of the superconductor stacks102shown inFIGS. 1A through 1C, according to some embodiments.

In some embodiments, as shown inFIGS. 3 and 2L, method300of manufacturing SNSPD100further includes encapsulating the superconductor stack (330) with a dielectric layer by depositing a thick layer of dielectric material (e.g., silicon dioxide) over substrate200and superconductor stack102formed thereon, using, for example, a CVD process, and by planarizing the thick layer of dielectric material using, for example, chemical mechanical polishing, to form the encapsulating dielectric layer (e.g., dielectric layer108). In some embodiments, the encapsulating dielectric layer (e.g., dielectric layer108) has a thickness L10that is sufficiently large to prevent optical coupling (e.g., evanescent coupling) between metal lines (not shown) that are formed over dielectric layer108and waveguide105or superconductor stack102. In some embodiments, thickness L10is greater than 800 nm and less than 20 μm. In some embodiments, thickness L10is greater than 1 μm and less than 10 μm.

In some embodiments, as shown inFIGS. 3 and 2M-2Q, method300of manufacturing SNSPD100further includes metallization processes340to form contacts over contact portions123,124of superconductor stack102.FIG. 2Mis a cross-sectional view of contact portion123of superconductor stack102before the contacts are formed, showing contact portion123disposed over dielectric layer106and away from waveguide105, as illustrated inFIG. 1A, according to some embodiments. As shown inFIGS. 3 and 2N, metallization processes340include forming342contact holes (e.g., contact hole142over contact portion123) by etching dielectric layer108using one or more anisotropic etching process (e.g., plasma etching, or reactive ion etching or RIE) to allow bottoms of the contact holes to reach cap layer136, as shown inFIG. 2N. In some embodiments, the one or more etching processes includes a first etching process for removing portions of dielectric layer108occupying upper portions of the contact holes (e.g., portion142A of contact hole142) and a second etching process for removing portions of dielectric layer108occupying lower portions of the contact holes (e.g., portion142B of contact hole142). The first etching process is an anisotropic etching process for etching the dielectric material in dielectric layer108with a relatively high etch rate. The second etching process is an anisotropic etching process for etching the dielectric material in dielectric layer108with a relatively low etch rate but with a high selectivity over the layer under dielectric layer108(e.g., cap layer136). The etching process(es) with high selectivity is used to clear (e.g., remove) portions of dielectric layer108or portions of the optional protective layer131near the bottoms of the contact holes without punching through any part of cap layer136. In some embodiments, the one or more etching processes for forming342contact holes can be any reactive ion etching processes for etch silicon dioxide that is selective to amorphous silicon. Thus, the cap layer can function as an etch-stop layer for forming the contact holes for SNSPD100.

As shown inFIGS. 3 and 2O, metallization processes340further includes depositing344a film243including a metal, such as Ti, Ni, Co, etc., or one or more compound thereof, over substrate200and the structures formed thereon using, for example, a PVD process. In some embodiments, the metal in film243is selected such that film243can be deposited at temperatures below 600 degrees Celsius. Film243is deposited to coat exposed surfaces of dielectric layer108(including walls of the contact holes), and exposed portions of cap layer136at the bottoms of the contact holes (e.g., contact hole142). As shown inFIGS. 3 and 2P, metallization processes340further include silicide formation346, during which the metal in film243diffuses into portions of cap layer136in contact with the metal film243at the bottoms of the contact holes (e.g., portion137under contact hole142) resulting in such portions to be converted to silicide138. Silicide formation246may include subjecting substrate200, along with the structures formed thereon, to an annealing process, such as rapid thermal annealing (RTA). In some embodiments, the material in cap layer136and the metal(s) in film243are selected to enable formation of silicide138at temperatures below 600 degrees Celsius.

In some embodiments, when protective layer131is sufficiently thin (e.g., 5-10 nm in thickness), portions (e.g., portion131a) of protective layer131under the silicide138can become conductive, resulting in the formation of ohmic contact through the protective layer131and a resulting contact resistance less than 10 ohms, which is the same or nearly the same as the contact resistance without protective layer131.

Subsequent to silicide formation process346, substrate200with the structures formed thereon is then etched to remove portions of film243covering a top surface248of dielectric layer108. Portions of film243remaining on sidewalls of the contact holes become contact liners or outer layers for the metal contacts to be formed (e.g., contact liner or outer layer143in contact hole142), as shown inFIG. 2P. As shown inFIGS. 3 and 2Q, metallization processes240further includes contact core formation348, during which the contact holes (e.g., contact hole142) are filled with contact cores (e.g., contact core141). Contact pads (or metal line) (e.g., contact pad or metal line145) can then be formed over contact core141, using, for example, conventional processes for forming contact pads or metal line.

As used herein, the term “if” is, optionally, construed to mean “when” or “upon” or “in response to determining” or “in response to detecting” or “in accordance with a determination that,” depending on the context.