Method of forming a micro-pattern for semiconductor devices

Methods of forming integrated circuit devices utilize fine width patterning techniques to define conductive or insulating patterns having relatively narrow and relative wide lateral dimensions. A target material layer is formed on a substrate and first and second mask layers of different material are formed in sequence on the target material layer. The second mask layer is selectively etched to define a first pattern therein. Sidewall spacers are formed on opposing sidewalls of the first pattern. The first pattern and sidewall spacers are used collectively as an etching mask during a step to selectively etch the first mask layer to define a second pattern therein. The first pattern is removed to define an opening between the sidewall spacers. The first mask layer is selectively re-etched to convert the second pattern into at least a third pattern, using the sidewall spacers as an etching mask. The target material layer is selectively etched using the third pattern as an etching mask.

REFERENCE TO PRIORITY APPLICATION

This application claims the benefit of Korean Patent Application No. 10-2010-0062078, filed on Jun. 29, 2010, in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated herein in its entirety by reference.

BACKGROUND

The inventive concept relates to a method of forming semiconductor devices, and more particularly, to a method of forming a micro-pattern for semiconductor devices.

A double patterning method has been proposed to overcome the resolution limit of a photolithography process. However, there is room for improvement in applying the double patterning method.

SUMMARY OF THE INVENTION

Methods of forming integrated circuit devices according to embodiments of the invention utilize fine width patterning techniques to define conductive or insulating patterns having relatively narrow and relative wide lateral dimensions. According to some of these embodiments of the invention, a target material layer is formed on a substrate and first and second mask layers of different material are formed in sequence on the target material layer. The second mask layer is selectively etched to define a first pattern therein. Sidewall spacers are formed on opposing sidewalls of the first pattern. The first pattern and sidewall spacers are then used collectively as an etching mask during a step to selectively etch the first mask layer to define a second pattern therein. The first pattern is then removed to define an opening between the sidewall spacers. The first mask layer is then selectively re-etched to convert the second pattern into at least a third pattern, using the sidewall spacers as an etching mask. Thereafter, the target material layer is selectively etched using the third pattern as an etching mask.

According to some additional embodiments of the invention, the step of forming sidewall spacers may include depositing a silicon oxide layer on the first pattern using an atomic layer deposition (ALD) or chemical vapor deposition (CVD) technique and then etching back the deposited silicon oxide layer to define the sidewall spacers. The step of forming a target material layer may also include depositing an electrically conductive layer on the substrate. This electrically conductive layer may be formed of a material selected from a group consisting of metals, metal nitrides, metal silicides and doped or undoped polysilicon. Alternatively, the target material layer may be an electrically insulating layer. In addition, the first mask layer may be a silicon nitride layer having a thickness in a range from about 500 angstroms to about 3000 angstroms and the second mask layer may be an organic material layer having a thickness in a range from about 1000 angstroms to about 5000 angstroms.

Additional embodiments of the invention include methods of forming integrated circuit memory devices. According to some of these embodiments of the invention, an electrically conductive target material layer is formed on a substrate and first and second mask layers of different material are formed on the target material layer. The second mask layer is selectively etched to define a first pattern therein and then sidewall spacers are formed on opposing sidewalls of the first pattern. This first pattern and the sidewall spacers are then used collectively as an etching masked during a step of selectively etching the first mask layer to define a second pattern therein. Then, the first pattern is removed to thereby define an opening between the sidewall spacers. A first portion of the second pattern is then covered with a protective third mask layer prior to a step of selectively re-etching the first mask layer to convert a second portion of the second pattern into at least a third pattern, using the sidewall spacers (and third mask layer) as an etching mask. This third pattern is then covered with a protective fourth mask layer before selectively etching the first portion of the second pattern to thereby define a fourth pattern. Thereafter, the target material layer is selectively etched using the third pattern as an etching mask to define a plurality of word lines of the memory device and also using the fourth pattern as an etching mask to define a plurality of contact pads that are electrically connected to the plurality of word lines.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The present inventive concept will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the inventive concept are shown. The inventive concept may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the inventive concept to those skilled in the art. Like reference numerals in the drawings denote like elements. In the drawings, various elements and regions are schematically drawn. Therefore, the inventive concept is not limited to the relative sizes and gaps depicted in the accompanying drawings.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this inventive concept belongs. It will be further understood that terms, such as those defined in commonly used in dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal senses unless expressly so defined herein.

FIG. 1is a schematic block diagram showing a memory system50of a semiconductor device that can be formed using a method of forming a micro-pattern, according to an embodiment of the inventive concept. Referring toFIG. 1, the memory system50of a semiconductor device may include a host10, a memory controller20, and a flash memory30. The memory controller20performs as an interface between the host10and the flash memory30, and may include a buffer memory22. Although not shown, the memory controller20may further include a central processing unit (CPU), a read-only memory (ROM), a random-access memory (RAM), and interface blocks. The flash memory30may further include a cell array32, a decoder34, a page buffer36, a bit line selection circuit38, a data buffer42, and a control unit44. Data and a write command are input to the memory controller20from the host10, and the memory controller20controls the flash memory30to write the data in the cell array32in response to the input write command. Also, the memory controller20controls the flash memory30to read data stored in the cell array32in response to a read command input from the host10. The buffer memory22temporarily stores data transmitted between the host10and the flash memory30. The cell array32of the flash memory30includes a plurality of memory cells. The decoder34is connected to the cell array32through word lines WL0, WL1, . . . WLn. The decoder34generates a selection signal Yi in response to an address input from the memory controller20to select one of the word lines WL0, WL1, . . . WLnor bit lines BL0, BL1, . . . BLn. The page buffer36is connected to the cell array32through the bit lines BL0, BL1, . . . BLm.

FIG. 2is a circuit diagram for explaining an exemplary structure of the cell array32ofFIG. 1. Referring toFIG. 2, the cell array32may include a plurality of memory cell blocks32A including a plurality of memory cells92. The memory cell blocks32A each include a plurality of cell strings90formed between the bit line BL0, BL1, . . . BLmand a common source line CSL. Each of the cell strings90includes the plurality of memory cells92connected in a serial manner. Gate electrodes of the memory cells92included in one of the cell strings90that is connected to a string selection line SSL are respectively connected to word lines WL0, WL1, . . . WLn. A ground selection transistor94, which is connected to a ground selection line GSL, and a string selection transistor96are disposed on opposite ends of each of the cell strings90. The ground selection transistor94and the string selection transistor96control the electrical connection between the memory cells92and the bit line BL0, BL1, . . . BLnand the common source line CSL. The memory cells92each connected to word lines WL0, WL1, . . . WLnacross the cell strings90form a page unit or a bite unit.

In the word lines WL0, WL1, . . . WLnof a conventional NAND flash memory device, a contact pad for connecting the word lines WL0, WL1, . . . WLnto the decoder34is formed in one body with the word lines WL0, WL1, . . . WLn. In this way, it is necessary to form the contact pad connected to the word lines WL0, WL1, . . . WLntogether with the word lines WL0, WL1, . . . WLn. Also, in the case of a NAND flash memory device, relatively wider width and low density patterns such as a ground selection line GSL, a string selection line SSL, and a transistor for a peripheral circuit may be formed together with narrow width patterns such as word lines WL0, WL1, . . . WLn.

FIG. 3is a plan view of a part of the configuration of a semiconductor device formed using a method of forming a micro-pattern according to an embodiment of the inventive concept.FIG. 3shows a portion of a memory cell region300A of a NAND flash memory device, a plurality of conductive lines that constitute a cell array in the memory cell region300A, for example, a portion of a connection region300B for connecting word lines or bit lines to an external circuit (not shown) such as a decoder, and a portion of a peripheral circuit region300c.

Referring toFIG. 3, the memory cell region300A includes a plurality of memory cell blocks340. InFIG. 3, only one memory cell block340is depicted for convenience of explanation. In the memory cell block340, a plurality of conductive lines301through332that are required to form one cell string90(refer toFIG. 2) between a string selection line SSL and a ground selection line GSL extend parallel to one another in a first direction (in an x-direction inFIG. 3). Each of the conductive lines301through332extends across the memory cell region300A and the connection region300B.

In order to connect the conductive lines301through332to the external circuit (not shown) such as the decoder, a plurality of contact pads352, formed as one-body with the conductive lines301through332, are formed on one end of each of the conductive lines301through332in the connection region300B.

InFIG. 3, in the connection region300B, the end portions of the conductive lines301through332extend in a second direction (a y-direction inFIG. 3) which is perpendicular to the first direction. However, the current inventive concept is not limited to the concept ofFIG. 3. Within the scope of the inventive concept, various modifications and changes to the configurations of the conductive lines301through332and the contact pads352are possible. Conductive patterns372for peripheral circuits are formed in the peripheral circuit region300C.

InFIG. 3, all of the conductive lines301through332, the string selection line SSL, the ground selection line GSL, the contact pads352, and the conductive patterns372for peripheral circuits may be formed of an identical material. The conductive lines301through332respectively may be word lines that constitute a plurality of memory cells in the memory cell region300A. The conductive patterns372for peripheral circuits may constitute gate electrodes of transistors for peripheral circuits. The string selection line SSL and the ground selection line GSL respectively may have widths greater than that of the conductive lines301through332. As another example, the conductive lines301through332may be bit lines that constitute memory cells in the memory cell region300A. In this case, the string selection line SSL and the ground selection line GSL may be omitted.

InFIG. 3, it is depicted that a plurality of conductive lines301through332includes32conductive lines in one memory cell block340. However, the current inventive concept is not limited thereto, and one memory cell block340may include various numbers of conductive lines.

Next, a practical example of a method of forming a micro-pattern for semiconductor devices, according to an embodiment of the inventive concept, will now be described.FIGS. 4A,4B through14A, and14B are plan views and cross-sectional views illustrating a process sequence of a method of forming a micro-pattern for semiconductor devices, according to an embodiment of the inventive concept. In particular,FIGS. 4A through 14Arespectively are plan views of a rectangular portion “IV” inFIG. 3, andFIGS. 4B through 14Bare cross-sectional views taken along lines A-A′, B-B′, and C-C′ of the rectangular portion “IV” inFIG. 3.

Referring toFIGS. 4A and 4B, a substrate401having a memory cell region300A, a connection region300B, and a peripheral circuit region300C (refer toFIG. 3) is prepared. The substrate401may have a structure in which a target material film420is formed on a base substrate410. The base substrate410may be a semiconductor substrate such as a silicon substrate, a silicon-on-insulator (SOI) substrate, a silicon-germanium substrate, a gallium-arsenic substrate. Also, the base substrate410may have a predetermined thin film or a structure on the semiconductors described above.

The target material film420is a film of a material to be eventually patterned, for example, a conductive metal, a metal nitride, a metal silicide, or a doped or undoped polysilicon. Also, the target material film420may be an oxide of silicon, a nitride of silicon, or an oxynitride of silicon. When word lines are formed from the target material film420, the target material film420may include a conductive material selected from the group consisting of TaN, TiN, W, WN, HfN, WSi, and a combination of these materials. When bit lines are formed from the target material film420, the target material film420may be formed of a doped polysilicon or a metal.

Next, a first hard mask material layer430, a mold mask material film440, and a anti-reflection film442may sequentially be formed on the substrate401. If necessary, an additional hard mask material layer (not shown) may further be included between the first hard mask material layer430and the mold mask material film440or between the first hard mask material layer430and the substrate401. The first hard mask material layer430may be formed of a material that has an etch selectivity with respect to materials adjacent to an upper or a lower side thereof, and is not specifically limited. The first hard mask material layer430may be, for example, a silicon nitride material layer. The first hard mask material layer430may have a thickness in a range from about 500 Å to about 3,000 Å.

The mold mask material film440may be, for example, a carbon-based film, in particular, a spin-on hardmask (SOH) or an amorphous carbon layer (ACL). For example, in order to form the mold mask material film440, an organic compound layer is formed to a thickness in a range from about 1,000 Å to about 5,000 Å by spin coating. The organic compound may be formed of a hydrocarbon compound or a derivative thereof that includes an aromatic ring such as phenyl, benzene, or naphthalene. The organic compound may be formed of a material having relatively high carbon content in a range from about 85 wt % to about 99 wt % based on the total weight. The carbon-based film may be formed by primarily baking the organic compound layer at a temperature in a range from about 150° C. to about 350° C. for approximately 60 seconds. Afterwards, the carbon-based film is hardened by secondarily baking at a temperature in a range from about 300° C. to about 550° C. for approximately 30 to 300 seconds. In this way, when the carbon-based film is hardened through a second baking process, the carbon-based film is not adversely affected in a subsequent deposition process for forming another film on the carbon-based film although the deposition process is performed at a relatively high temperature of approximately 400° C. or above.

Referring toFIGS. 5A and 5B, narrow width mold mask patterns452are formed in a first region400A and wide width mold mask patterns454are formed in a second region400B of the substrate401from the mold mask material film440. The narrow width mold mask patterns452and the wide width mold mask patterns454respectively may be formed in plural numbers.

In the first region400A of the substrate401, micro patterns having a narrow width may be formed by doubling the pattern density through a double patterning process in one of the memory cell region300A and the connection region300B. The first region400A of the substrate401may correspond to a region where the conductive lines301through332shown inFIG. 3are to be formed. The second region400B of the substrate401may be a region where wide width patterns having a size or width larger than that in the first region400A or patterns having a relatively low density are formed. For example, the first region400A of the substrate401may be a region where the cell array32ofFIG. 1is formed, and the second region400B may be a peripheral circuit region on which peripheral circuits for driving unit memory devices formed in the first region400A, a core region, or a connection region.

Here, the wide width and the narrow width are relative concepts, and thus, have no practical numbers that can be a basis of division. The narrow width mold mask patterns452may have a first width W and may be arranged parallel to each other with a first distance D. The dimensions of the first width W and the first distance D are not specifically limited. For example, the first width W may be equal to the first distance D. Also, the first distance D may be three times larger than the first width W. Also, the first width W and the first distance D may be determined according to the size of one memory cell having a size determined by a design rule. The first width W and the first distance D respectively may have a 1F through a 3F size. Here, F denotes the minimum feature size in a memory cell. The wide width mold mask patterns454may have a size or a width greater than that of the narrow width mold mask patterns452.

The narrow width mold mask patterns452and the wide width mold mask patterns454may be formed by using a photolithography process. That is, a photoresist pattern may be formed on the anti-reflection film442by exposing and developing a photoresist film (not shown) using an exposure mask after forming the photoresist film on the anti-reflection film442. Afterwards, the narrow width mold mask patterns452and the wide width mold mask patterns454may be obtained by anisotropically etching the mold mask material film440and the anti-reflection film442using the photoresist pattern as an etch mask. Next, the photoresist pattern remaining on upper parts of the narrow width mold mask patterns452and the wide width mold mask patterns454may be readily removed by, for example, an ashing method.

As can be seen fromFIG. 5A, the narrow width mold mask patterns452and the wide width mold mask patterns454may be formed in one-body by being connected to each other. However, all of the wide width mold mask patterns454may not be connected to the narrow width mold mask patterns452, and some wide width mold mask patterns454may not be connected to the narrow width mold mask patterns452. For example, as shown inFIG. 3, in the cases for forming the string selection line SSL and/or the ground selection line GSL in the memory cell region300A, or for forming the conductive patterns372for peripheral circuits in the peripheral circuit region300C, the wide width mold mask patterns454may not be connected to the narrow width mold mask patterns452.

Referring toFIGS. 6A and 6B, a spacer mask layer460having a substantially uniform thickness is formed on side walls and upper parts of the narrow width mold mask patterns452and the wide width mold mask patterns454. The spacer mask layer460also covers an exposed surface of the first hard mask material layer430with a substantially uniform thickness. The spacer mask layer460may have an etch selectivity with respect to the narrow width mold mask patterns452, the wide width mold mask patterns454, and the first hard mask material layer430. The spacer mask layer460may be, for example, a silicon oxide film. In order to form the spacer mask layer460having a uniform thickness, the spacer mask layer460may be formed by using an atomic layer deposition (ALD) or chemical vapour deposition (CVD). However, the method is not limited thereto.

Referring toFIGS. 7A and 7B, a first spacer462and a second spacer464respectively are formed on side walls of the narrow width mold mask patterns452and the wide width mold mask patterns454by anisotropically etching the spacer mask layer460. As shown inFIG. 7A, the first spacer462and the second spacer464may be connected to each other to form a loop shape spacer460a. In order to form the first spacer462and the second spacer464, the anisotropical etching of the spacer mask layer460may be performed until the surface of the first hard mask material layer430is exposed. InFIGS. 7A and 7B, it is depicted that the anti-reflection film442aremains. However, in some cases, the anti-reflection film442amay be removed when the spacer mask layer460is anisotropically etched.

Referring toFIGS. 8A and 8B, the first hard mask material layer430is anisotropically etched using the first spacer462, the second spacer464, the narrow width mold mask patterns452, and the wide width mold mask patterns454as etch masks. Through the anisotropical etching, a patterned first hard mask430amay be obtained. At this point, any remaining anti-reflection film442amay also be removed.

As a result, the target material film420may be exposed. As described above, if there is an additional hard mask material film besides the first hard mask material layer430, the target material film420may be exposed by performing an additional anisotropical etching using the hard mask material film obtained by the anisotropical etching as shown inFIGS. 8A and 8B.

Referring toFIGS. 9A and 9B, the narrow width mold mask patterns452and the wide width mold mask patterns454are removed from the first region400A and the second region400B of the substrate401under a condition that the first spacer462, the second spacer464, the first hard mask430a, and the target material film420are prevented from being etched. If the narrow width mold mask patterns452and the wide width mold mask patterns454are formed of a carbon-based material, they can be readily removed by, for example, an aching method.

As a result, a loop shape spacer460aremains on the first hard mask430a. In the first region400A, the first hard mask430abetween the first spacers462will be removed; however, in the second region400B, the first hard mask430abetween the second spacers464will not be removed. Accordingly, in the second region400B, it is necessary to form a blocking material film for protecting the first hard mask430abetween the second spacers464from being removed while the first hard mask430abetween the first spacers462in the first region400A is removed.

Referring toFIGS. 10A and 10B, as described above, a blocking material film470is formed in the second region400B. The blocking material film470may be formed of any material that has an etch selectivity with respect to the first hard mask430a. The blocking material film470may be, for example, a photoresist.

FIG. 10Cis a lateral cross-sectional view showing a misalignment margin when the blocking material film470is formed, and consecutively shows the cross-sections of C-C′ and A-A′. Referring toFIG. 10C, an ideal point of a right side boundary of the blocking material film470may be the middle point between the first hard mask430aof the second region400B and a first spacer462athat is most adjacent to the second region400B. However, as long as the right-hand side boundary of the blocking material film470lies within the range of M shown inFIG. 10C, the purpose of protecting the first hard mask430abetween the second spacers464from being removed may be achieved. Accordingly, when it is assumed that all of widths between the spacers and distances between the spacers are F, M is 3Fs. Thus, the forming of the blocking material film470has a misalignment margin of 3F, in other words, a misalignment margin of ±1.5F.

Referring toFIG. 10Aagain, although the purpose of the blocking material film470is basically to protect the first hard mask430abetween the second spacers464in the second region400B, portions of the first hard mask430athat may be unnecessary in a subsequent process may be removed and may be exposed from the blocking material film470.

If the blocking material film470is a photoresist material film, the blocking material film470may be readily formed by performing a photolithography process after coating a photoresist on an entire surface of the resultant product. As described above, the formation of the blocking material film470may have a misalignment margin of 3F, and a micro-pattern having a resolution finer than the resolution limitation of the photolithography process may be formed.

Referring toFIGS. 11A and 11B, the exposed first hard mask430ais anisotropically etched using the blocking material film470, the first spacer462, and the second spacer464as etch masks. As a result, the first hard mask430alocated between the first spacers462may be removed. In particular, a portion of the first hard mask430alocated below the narrow width mold mask patterns452may be removed. As a result, a new second hard mask430bis obtained.

As described above, the first spacer462and the second spacer464are connected to each other, and thus, form a loop shape spacer460a. In this case, it is necessary to separate the first spacer462and the second spacer464from each other to form individual patterns.

Referring toFIGS. 12A and 12B, a separation etch mask480that exposes portions of the loop shape spacer460ato be removed for separating the loop shape spacer460ais formed. The separation etch mask480may be, for example, a photoresist.FIG. 12Ashows a case of separating the loop shape spacer460aby removing a portion of the second spacer464and a portion of the second hard mask430b. Although not directly shown inFIG. 12A, in order to separate the loop shape spacer460ainto two parts, another portion of the loop shape spacer460amay further be exposed. Also, referring toFIG. 12A, there is a portion P in which the second hard mask430bis not exposed by the separation etch mask480and not covered by the loop shape spacer460a. This portion P may be transferred to the target material film420in a subsequent process to be used as a connection pad for forming a contact.

Referring toFIGS. 13A and 13B, the exposed portion of the loop shape spacer460aand the exposed portion of the second hard mask430bare removed by etching using the separation etch mask480. Through the etching, one loop shape spacer460acan be divided into two parts. Also, a portion of the second hard mask430bis separated, and thus, a new third hard mask430cis formed. Next, the separation etch mask480may be removed.

Referring toFIGS. 14A and 14B, the target material film420is etched using the first spacer462, the second spacer464, and the third hard mask430cas etch masks. In the first region400A, a first pattern420ato which the width and the pitch of the first spacer462are transferred is formed, and, in the second region400B, a second pattern420band a third pattern420cto which the width and the pitch of the third hard mask430care transferred are formed. The second pattern420bmay be formed in one body with the first pattern420a. In the first region400A, the pattern density of the narrow width mold mask pattern452is doubled to form the first spacer462, and the pattern of the first spacer462is, in turn, transferred to form the second hard mask430band the first pattern420ain a narrow width. In the second region400B, the width of the pattern of the third hard mask430cformed from the wide width mold mask patterns454is transferred to the second pattern420band the third pattern420c.

The first pattern420amay correspond to the plurality of conductive lines301through332in the memory cell region300A shown inFIG. 3, and the second pattern420bmay correspond to the plurality of contact pads352respectively formed in one-body with the conductive lines301through332in the connection region300B shown inFIG. 3. Also, the third pattern420cmay correspond to the string selection line SSL and the ground selection line GSL in the memory cell region300A shown inFIG. 3.

If the target material film420is formed of a conductive material, a conductive pattern may be obtained. However, alternatively, if the target material film420is a hard mask material film, a new hard mask pattern may be obtained, and a film below the hard mask pattern may be additionally etched using the new hard mask pattern. For example, in order to define an active region on the base substrate410, a method described with reference toFIGS. 4A,4B through14A, and14B may be used. Those skilled in the art may define an active region by forming a plurality of trenches having various widths in a semiconductor substrate and by burying an insulating material in the trenches using the method described with reference toFIGS. 4A,4B through14A, and14B.

Also, as described above, the first pattern420a, the second pattern420b, and the third pattern420cmay be obtained by a single etching process. That is, an etching process required for forming the conductive lines301through332that constitute the memory cell region300A and an etching process for forming relatively large patterns such as the plurality of contact pads352for connecting peripheral circuits, the string selection line SSL and the ground selection line GSL formed in the memory cell region300A, and conductive patterns372for peripheral circuits formed in the peripheral circuit region300C are not separately performed, but are simultaneously performed. In this case, a misaligning problem that can occur between the etching processes may be basically removed.

In addition, since the first pattern420a, the second pattern420b, and the third pattern420care simultaneously obtained by a single photolithography process, a material having identical or similar etching characteristics may be used as an etch mask. Accordingly, different etching characteristics according to the material used to form the etch mask and the possibility of degradation of pattern uniformity may be removed. Also, when a narrow width pattern is formed adjacent to a wide width pattern, there is no height difference of surfaces of mold mask patterns for forming the narrow and wide width patterns, thereby remarkably reducing the cause of pattern failure.

DETAILED DESCRIPTION

Thus, as described hereinabove with respect toFIGS. 4A-14Aand4B-14B, a target material layer420is formed on a substrate410and first and second mask layers (430,440) of different material are formed in sequence on the target material layer420. (See, e.g.,FIG. 4B). The second mask layer440is selectively etched to define a first pattern therein, as illustrated byFIG. 5B. (See, e.g.,452,454). Sidewall spacers (462,464) are formed on opposing sidewalls of the first pattern, as illustrated byFIGS. 6B-7B. The first pattern and sidewall spacers are then used collectively as an etching mask during a step to selectively etch the first mask layer430to define a second pattern (430a) therein, as illustrated byFIG. 8B. The first pattern is then removed to define an opening between the sidewall spacers, as illustrated byFIG. 9B. The first mask layer is then selectively re-etched to convert the second pattern into at least a third pattern, using the sidewall spacers as an etching mask, as illustrated byFIGS. 10B-11B. Thereafter, the target material layer420is selectively etched using the third pattern as an etching mask, as illustrated byFIGS. 13B-14B.

Additional embodiments of the invention include methods of forming integrated circuit memory devices. According to some of these embodiments of the invention, an electrically conductive target material layer420is formed on a substrate and first and second mask layers (430,440) of different material are formed on the target material layer420. The second mask layer440is selectively etched to define a first pattern (452,454) therein and then sidewall spacers462,464are formed on opposing sidewalls of the first pattern, as illustrated byFIGS. 6B-7B. This first pattern and the sidewall spacers are then used collectively as an etching masked during a step of selectively etching the first mask layer430to define a second pattern430atherein, as illustrated byFIG. 8B. Then, as illustrated byFIG. 9B, the first pattern is removed to thereby define an opening between the sidewall spacers. A first portion of the second pattern is then covered with a protective third mask layer470prior to a step of selectively re-etching the first mask layer to convert a second portion of the second pattern430ainto at least a third pattern430b, using the sidewall spacers462(and third mask layer470) as an etching mask. (See, e.g.,FIGS. 10B-11B). This third pattern is then covered with a protective fourth mask layer480before selectively etching the first portion of the second pattern to thereby define a fourth pattern430c, as shown byFIG. 13B. Thereafter, the target material layer is selectively etched using the third pattern as an etching mask to define a plurality of word lines420aof the memory device and also using the fourth pattern as an etching mask to define a plurality of contact pads420bthat are electrically connected to the plurality of word lines420a, as illustrated byFIG. 14B.