Low power output driver

A low power output driver includes one of a regulated reduced voltage source that receives a supply voltage and outputs a regulated reduced voltage that is a lower voltage than the supply voltage. The driver also includes a first driver input that receives a first logic signal, a second driver input that receives a second logic signal, a first driver output that outputs a first output signal and a second driver output that outputs a second output signal. The driver includes first, second, third and fourth n-type metal oxide semiconductor (NMOS) that are cross-connected between the reduced voltage and the first and second driver outputs or ground. When the second input is high, the second NMOS and the third NMOS are gated on, the second driver output is raised to the reduced voltage and the first driver output is pulled down to the internal ground.

BACKGROUND OF THE INVENTION

The present invention relates generally to an output driver, and more particularly, to a low power output driver utilizing voltage lower than the supply voltage or rail voltage.

Integrated circuits which have output drivers for clock and data are known in the art. A typical prior art configuration is formed with two pairs of complementary metal oxide semiconductors (CMOS) such as the circuit depicted inFIG. 3(e.g., an inverted CML). The CMOS can be either n-type or p-type devices. The configuration shown includes a p-type CMOS over an n-type CMOS for each CMOS pair. The n-type CMOS are not really doing anything active, as shown, but are provided for ESD protection. The supply voltage (VDD) or rail voltage is applied to the supply of the drivers and to the CMOS pairs. Each CMOS pair is connected to a pad. A series resistor RSis connected between each of the pads and a respective transmission line to “decouple” the output capacitance of the driver from the transmission line itself, i.e., it makes the impedance at the source of the transmission line more purely resistive. A termination resistor RTis connected between the junction of the series resistor RSand transmission line TLand ground to create a fixed impedance. Typically, a current mirror circuit is connected between the rail voltage and the high side of the CMOS pairs. The current mirror is driven or controlled by a reference current IREF. The power consumption of this prior art circuit is primarily determined by the current constantly being sourced through one or the other terminating resistors RT. The power can be calculated as P=V*I=VDD*(N*IREF). A typical current draw through the current mirror is on the order of 14-15 mA. With about 50 ohm terminating resistors RT, the resulting voltage drop across each terminating resistor RTis on the order of 750 millivolts (mV). Thus, the power draw, independent of the load condition, is about 50 milliwatts (mW). Since one CMOS pair or the other is always connected to one of the pads, power is constantly dissipated using the conventional circuit due to the bleeding current through the respective terminating resistor RT.

It is desirable to provide a driver output that utilizes a reduced voltage supply and has lower power consumption. It is also desirable to provide an on-chip reduced voltage power supply or regulator in combination with a plurality of low power output drivers.

BRIEF SUMMARY OF THE INVENTION

Briefly stated, the present invention comprises a low power output driver that includes one of a series-regulated and a switching-mode-regulated reduced voltage source. The reduced voltage source receives a supply voltage and outputs a regulated reduced voltage that is a lower voltage than the supply voltage. The driver also includes a first driver input that receives a first logic signal, a second driver input that receives a second logic signal, a first driver output that outputs a first output signal and a second driver output that outputs a second output signal. The driver includes first, second, third and fourth n-type metal oxide semiconductor (NMOS). The source and the drain of the first NMOS are electrically coupled between the reduced voltage VLand the first driver output. The gate of the first NMOS is electrically coupled to the first driver input. The source and the drain of the second NMOS are electrically coupled between the first driver output and an internal ground. The gate of the second NMOS is electrically coupled to the second driver input. The source and the drain of the third NMOS are electrically coupled between the reduced voltage VLand the second driver output. The gate of the third NMOS is electrically coupled to the second driver input. The source and the drain of the fourth NMOS are electrically coupled between the second driver output and the internal ground. The gate of the fourth NMOS is electrically coupled to the first driver input. When the first driver input is high and the second driver input is low, the first NMOS and the fourth NMOS are gated on, the first driver output is raised to the reduced voltage and the second driver output is pulled down to the internal ground. When the second input is high and the first driver input is low, the second NMOS and the third NMOS are gated on, the second driver output is raised to the reduced voltage and the first driver output is pulled down to the internal ground.

In another aspect, the present invention comprises a low power output driver system that includes a reference voltage supply VREF, a first voltage regulator that receives reference voltage supply VREFand outputs a first regulated reduced voltage VL1that is a lower voltage than the reference voltage supply VREFand a second voltage regulator that receives reference voltage Supply VREFand outputs a second regulated reduced voltage VL2that is a lower voltage than the reference voltage supply VREF. The system also includes a first low power output driver and a second low power output driver. Each of the first and second low power output drivers includes a first driver input that receives a first logic signal, a second driver input that receives a second logic signal, a first driver output that outputs a first output signal, and a second driver output that outputs a second output signal. Each of the first and second low power output drivers includes first, second, third and fourth n-type metal oxide semiconductor (NMOS) that each have a gate, a source and a drain. The source and the drain of the first NMOS are electrically coupled between the respective first and second reduced voltage VL1, VL2and the first driver output. The gate of the first NMOS is electrically coupled to the first driver input. The source and the drain of the second NMOS are electrically coupled between the first driver output and an internal ground. The gate of the second NMOS is electrically coupled to the second driver input. The source and the drain of the third NMOS are electrically coupled between the respective first and second reduced voltage VL1, VL2and the second driver output. The gate of the third NMOS is electrically coupled to the second driver input. The source and the drain of the fourth NMOS are electrically coupled between the second driver output and the internal ground. The gate of the second NMOS is electrically coupled to the first driver input.

DETAILED DESCRIPTION OF THE INVENTION

Certain terminology is used in the following description for convenience only and is not limiting. The words “right,” and “left,” “lower,” and “upper” designate directions in the drawings to which reference is made. The words “inwardly” and “outwardly” refer to directions toward and away from, respectively, the geometric center of the object discussed and designated parts thereof. The terminology includes the words above specifically mentioned, derivatives thereof and words of similar import. Additionally, the word “a” is used in the claims and in the corresponding portions of the Specification, means “at least one.”

Referring to the drawings in detail, wherein like reference numerals indicate like elements throughout, there is shown inFIG. 1is an electrical schematic diagram of a low power output driver10and reduced voltage power supply30in accordance with a first preferred embodiment of the present invention. In the presently preferred embodiment, the reduced voltage power supply30is within the same integrated circuit (IC) (not shown) as the low power output driver10. Preferably, one reduced voltage power supply30will supply a plurality of low power output drivers10all on the same IC (i.e., on the same chip). The reduced voltage power supply30is one of a series-regulated power supply and a switching-mode-regulated power supply.

The reduced voltage power supply30receives power from an external power source such as an supply voltage (VDD) (i.e., the rail voltage). As shown, an operational amplifier (op-amp)130receives an internal reference current on its non-inverting input and outputs a signal to a field effect transistor (FET)132. The internal reference may be a bandgap reference, a resistance voltage divider, an external reference, an external bandgap and the like. The FET132then provides a reduced voltage output VLto a high-side of the low power output driver10and also as a feedback to the inverting input of op-amp130. For example, a VDDof 3.3 volts may be controlled down to about 750 mV. Of course, other voltage reducing configurations may be utilized without departing from the present invention. For example the FET132may instead be a bipolar transistor and the like. An external capacitor CEXTis coupled between the feedback voltage and ground to reduce line-noise, ripple and the like. Alternately, the external capacitor CEXTcan be formed internally without departing from the present invention.

The low power output driver10includes four n-type MOS (NMOS)100,102,110,112. The NMOS are configured in alternate pairs100,102and110,112that are coupled to PAD1and PAD2, respectively. One NMOS100of the first pair100,102is coupled between the reduced voltage source VLand the first pad PAD1and the other NMOS102of the first pair100,102is coupled between the first pad PAD1and an internal ground. Likewise, one NMOS110of the second pair110,112is coupled between the reduced voltage source VLand the second pad PAD2and the other NMOS112of the second pair110,112is coupled between the second pad PAD2and an internal ground.

Whenever NMOS100is on, PAD1is pulled up to the reduced voltage VLand NMOS112necessarily pulls PAD2to ground (i.e., a cross-wire configuration). Similarly, whenever NMOS110is on, PAD2is pulled up to the reduced voltage VLand NMOS102necessarily pulls PAD1to ground. When a particular pad PAD1, PAD2is pulled high, the reduced voltage VL, there is a current draw until the pad PAD1, PAD2reaches a quiescent voltage with reduced voltage VL. But, there is not a continuous draw of current to ground as in the case of a system with terminating resistors.

Thus, the low power output driver10includes one of a series-regulated and a switching-mode-regulated reduced voltage source30. There is a first supply voltage VDD1that provides power for devices such as operational amplifiers130and the like. The first supply voltage VDD1may be 1.2 VDC, 1.5 VDC, 3.3 VDC, 5 VDC or the like. The reduced voltage source30receives a second supply voltage VDD2and outputs a regulated reduced voltage VLthat is a lower voltage than the second supply voltage VDD2. The second supply voltage VDD2may be the same as the first supply voltage VDD1, may be derived from the first supply voltage VDD1or may be from a completely separate source. For example, the second supply voltage VDD2may be derived from a linear or switching power supply (not shown) that receives the first supply voltage VDD1and outputs a regulated voltage that is less than or greater than the first supply voltage VDD1. The driver10also includes a first driver input B that receives a first logic signal, a second driver input A that receives a second logic signal, a first driver output PAD1that outputs a first output signal and a second driver output PAD2that outputs a second output signal. The first and second driver inputs B, A may be applied through an amplifier, buffer or logic gate120,122, respectively. Supply power for the buffers120,122is provided by a third supply voltage VDD3. The third supply voltage VDD3may be the same as the first supply voltage VDD1, may be derived from the first supply voltage VDD1or may be from a completely separate source. Preferably, the third supply voltage VDD3is greater than the reduced voltage VL. The driver10includes first, second, third and fourth NMOS100,102,110, and112, respectively. The source and the drain of the first NMOS100are electrically coupled between the reduced voltage VLand the first driver output PAD1. The gate of the first NMOS100is electrically coupled to the first driver input B. The source and the drain of the second NMOS102are electrically coupled between the first driver output PAD1and an internal ground. The gate of the second NMOS102is electrically coupled to the second driver input A. The source and the drain of the third NMOS110are electrically coupled between the reduced voltage VLand the second driver output A. The gate of the third NMOS110is electrically coupled to the second driver input A. The source and the drain of the fourth NMOS112are electrically coupled between the second driver output A and the internal ground. The gate of the fourth NMOS112is electrically coupled to the first driver input B. When the first driver input B is high and the second driver input A is low, the first NMOS100and the fourth NMOS110are gated on, the first driver output PAD1is raised to the reduced voltage VLand the second driver output PAD2is pulled down to the internal ground. When the second driver input A is high and the first driver input B is low, the second NMOS102and the third NMOS110are gated on, the second driver output PAD2is raised to the reduced voltage VLand the first driver output PAD1is pulled down to the internal ground.

The first and second pads PAD1, PAD2are typically coupled to transmission lines TLthrough series resistors RS. The series resistance RSmay be internal (before the pads PAD1, PAD2) or external (after the pads PAD1, PAD2). The series resistance RSmay simply be the load of the wire depending on the application. The series resistance RSare normally used to increase the total impedance of the driver circuit10, including the transistor resistance plus the series resistance RSto match the impedance of the transmission lines TL1, TL2.

Driver inputs A and B may be clocks or data and the like. Each driver input A, B is connected to an NMOS pair100,102or110,112.

FIG. 2is an electrical schematic diagram of a low power output driver10′ with an external reduced voltage supply EXTERNAL VLin accordance with a second preferred embodiment of the present invention. The low power output driver10′ is substantially similar in functionality to that described above. The external reduced voltage supply EXTERNAL VLis from any reduced voltage source that is external to the driver IC such as an external series-regulated power supply or an external switching-mode-regulated power supply.

The resulting power consumption for the depicted system inFIG. 2is:
P=VL*IAVERAGE=VL2*CL*f(Eq. 1)where f is operating frequency.
For a reduced voltage of 0.75 volts and a VDD2of 3.3 volts, there is enough “enhancement” to pull the output pads PAD1, PAD2to the reduced voltage of VL.

An advantage of the present invention over a PMOS-NMOS (i.e., a complementary MOS pair or CMOS) output is that, although NMOS can be driven by 3.3 volts, PMOS would see only −0.7 volts, assuming that its gates cannot be driven below ground, which would result in minimal enhancement or possibly none at all. Therefore, an NMOS-NMOS with reduced voltage supply VLis more stable and makes reduced power consumption possible.

FIGS. 4A-4Bshow a low output power driver system200in accordance with a third preferred embodiment of the present invention. The low power output driver system200includes a reference voltage supply VREF, a first programmable current source214, a second programmable current source224and a third programmable current source234. The first programmable current source214receives the reference supply voltage VREFand outputs a first reference voltage VREF1. The second programmable current source224receives the reference supply voltage VREFand outputs a second reference voltage VREF2. The third programmable current source234receives the reference supply voltage VREFand outputs a third reference voltage VREF3. Each of the first, second and third programmable current sources214,224,234may have suitable bias components associated therewith such as resistors R213, R223and R233, respectively. The first, second and third programmable current sources214,224,234may include a simple resistor divider network and switch, amplifiers, transistors or the like.

FIG. 5shows one possible detailed circuit implementation of the first, second and third programmable current sources214,224,234. Each of the programmable current sources214,224,234include an op-amp252, a pass transistor T254, a drive transistor T256, a first selectable source transistor T261, a second selectable source transistor T262, a third selectable source transistor T263, a fourth selectable source transistor T264and four switches271-274. The op-amp252receives the reference supply voltage VREFand the output of the op-amp252drives the gate of the pass transistor T254. The op-amp252is configured as a buffer, but the op-amp252could be configured as an amplifier with the addition of feedback resistors. The drive transistor T256is coupled to the pass transistor T256and provides source and gate voltage to each of the first-fourth selectable source transistors T261-T264. The switches271-274are connected between the first-fourth selectable source transistors T261-T264and an output node258. The first, second or third reference voltage VREF1-VREF3is output from the output node258. The switches271-274can be controlled by external binary signals or can be programmed during manufacturing by jumpers or opening circuit paths, for example. Other detailed circuit implementation of the first, second and third programmable current sources214,224,234can be utilized without departing from the present invention.

Referring again toFIGS. 4A-4B, the low power output driver system200also includes a first voltage regulator210that receives reference voltage supply VREF1and outputs a first regulated voltage VL1that is derived from the reference voltage supply VREF1, a second voltage regulator220that receives reference voltage supply VREF2and outputs a second regulated voltage VL2that is derived from the reference voltage supply VREF2and a third voltage regulator230that receives reference voltage supply VREF3and outputs a third regulated voltage VL3that is derived from the reference voltage supply VREF3. The first, second and third regulated voltages VL1, VL2, VL3can be reduced, amplified or the same as the reference supply voltage VREF. Optionally, only the first programmable current source214provides the first reference voltage VREF1to each of the first, second and third voltage regulators210,220,230. Optionally, the reference supply voltage VREFis provided directly to each of the first, second and third voltage regulators210,220,230.

There can be any number of additional voltage regulators210,220,230as a design requires. Preferably, the plurality of voltage regulators210,220,230are provided on a single integrated circuit (IC) chip (on-chip voltage power supply or regulator).

Preferably, the voltage regulators210,220,230are configured to accept a relatively wide range of input voltage Vinwhile still outputting approximately the same desired regulated voltage VL1, VL2, VL3. The first, second and third regulated reduced voltages VL1, VL2, VL3may be the same or different voltage potentials depending on the application.

The low power output driver system200also includes first low power output driver1011, a second low power output driver1021and a third low power output driver1031. Each of the first, second and third low power output drivers1011,1021,1031includes a low output driver circuit10,10′ as described above with respect to the first preferred embodiment.

Preferably, the low power output driver system200includes a plurality of low output drivers1011-101n,1021-102n,1031-103nand each set of low output drivers1011-101n,1021-102nand1031-103nis connected to a separate voltage regulator210,220and230, respectively. Since each group of low output drivers1011-101n,1021-102nand1031-103nhas a dedicated voltage regulator210,220and230, there is better isolation, lower noise and less external coupling.

From the foregoing, it can be seen that the present invention comprises low power output driver that utilizes a reduced input voltage. It will be appreciated by those skilled in the art that changes could be made to the embodiments described above without departing from the broad inventive concept thereof. It is understood, therefore, that this invention is not limited to the particular embodiments disclosed, but it is intended to cover modifications within the spirit and scope of the present invention as defined by the appended claims.