Adaptive Interconnect Structure for Semiconductor Package

A package includes a first package component including a semiconductor die, wherein the semiconductor die includes conductive pads, wherein the semiconductor die is surrounded by an encapsulant; an adaptive interconnect structure on the semiconductor die, wherein the adaptive interconnect structure includes conductive lines, wherein each conductive line physically and electrically contacts a respective conductive pad; and first bond pads, wherein each first bond pad physically and electrically contacts a respective conductive line; and a second package component including an interconnect structure, wherein the interconnect structure includes second bond pads, wherein each second bond pad is directly bonded to a respective first bond pad, wherein each second bond pad is laterally offset from a corresponding conductive pad which is electrically coupled to that second bond pad.

BACKGROUND

The semiconductor industry has experienced rapid growth due to ongoing improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, improvement in integration density has resulted from iterative reduction of minimum feature size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices has grown, a need for smaller and more creative packaging techniques of semiconductor dies has emerged.

DETAILED DESCRIPTION

In accordance with some embodiments, an interconnect structure is formed to compensate for any lateral offset of bond pads. The interconnect structure may include conductive lines that connect the offset bond pads to overlying “corrected” bond pads that have little or no offset. The interconnect structure may be formed using adaptive techniques, such as using programmable photolithography techniques. In this manner, the interconnect structure may be formed to provide more precise bonding between the corrected bond pads and an overlying component without requiring significant process changes or additional process steps.

FIG.1illustrates a cross-sectional view of integrated circuit dies50attached to a carrier102, in accordance with some embodiments.FIG.1shows two integrated circuit dies50A-B attached to the carrier102, but in other embodiments only one integrated circuit die50or more than two integrated circuit dies50may be utilized. The integrated circuit dies50A-B are packaged in subsequent processing to form an integrated circuit component100(seeFIGS.9-10) that is incorporated into a package300(seeFIG.15), in accordance with some embodiments. An integrated circuit die50(e.g.,50A and/or50B) may comprise a logic die (e.g., central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC), application processor (AP), microcontroller, etc.), a memory die (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), a power management die (e.g., power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., digital signal processing (DSP) die), a front-end die (e.g., analog front-end (AFE) die), the like, or combinations thereof. The integrated circuit dies50of a integrated circuit component100may include similar types of dies or different types of dies.

An integrated circuit die50may be formed in a wafer, which may include different device regions that are singulated in subsequent steps to form a plurality of integrated circuit dies. An integrated circuit die50may be processed according to applicable manufacturing processes to form integrated circuits. An integrated circuit die50may include a semiconductor substrate52, examples of which are shown inFIG.1by semiconductor substrates52A and52B. For example, as shown inFIG.1, the integrated circuit die50A includes a semiconductor substrate52A and the integrated circuit die50B includes a semiconductor substrate52B. A semiconductor substrate52(e.g., the semiconductor substrate52A and/or the semiconductor substrate52B) may be silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. A semiconductor substrate52may include other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. Other substrates, such as multi-layered or gradient substrates, may also be used. A semiconductor substrate52may have an active surface (e.g., the surface facing upwards inFIG.1), sometimes called a front side or a top side, and an inactive surface (e.g., the surface facing downwards inFIG.1), sometimes called a back side.

Devices54may be formed at the front surface of a semiconductor substrate52, examples of which are shown inFIG.1by devices54A and devices54B. For example, the integrated circuit die50A includes devices54A, and the integrated circuit die50B includes devices54B. The devices54(e.g., the devices54A and/or the devices54B) may include active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc. An inter-layer dielectric (ILD) may surround and cover the devices54(not illustrated). An integrated circuit die50may include an interconnect structure60that interconnects the devices54to form an integrated circuit. For example, the integrated circuit die50A includes an interconnect structure60A, and the integrated circuit die50B includes an interconnect structure60B. The interconnect structure60may be formed by, for example, metallization patterns in dielectric layers (e.g., inter-metal dielectric (IMD) layers or the like). The metallization patterns may be redistribution layers, and may include metal lines and vias formed in one or more low-k dielectric layers, in some embodiments. The metallization patterns of the interconnect structure60are electrically coupled to the devices54.

In some embodiments, the interconnect structure60includes pads66at or near the top of the interconnect structure60, which may be exposed. For example, the interconnect structure60A of the integrated circuit die50A includes pads66A and the interconnect structure60B of the integrated circuit die50B includes pads66B. The pads66are electrically coupled to the metallization patterns of the interconnect structure60, and may be part of a metallization pattern (e.g., the topmost metallization pattern) of the interconnect structure60, in some embodiments. In some embodiments, an interconnect structure60may include alignment marks56used during placement of the integrated circuit die50or during subsequent processing. For example, the interconnect structure60A may include alignment marks56A and the interconnect structure60B may include alignment marks56B. The interconnect structures60A-B are examples, and interconnect structures60having other configurations or dimensions are possible.

The integrated circuit dies50A-B may be attached to a carrier102, in some embodiments. The carrier102may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier102may be a wafer, such that multiple packages can be formed on the carrier102simultaneously. In some embodiments, the carrier102includes alignment marks104. The integrated circuit dies50A-B may be attached to the carrier102with an adhesive (not illustrated) and may be placed using a pick-and-place method or the like. The alignment marks104of the carrier, the alignment marks56A of the integrated circuit die50A, and/or the alignment marks56B of the integrated circuit die50B may be utilized during placement of the integrated circuit dies50A-B, in some cases. In some embodiments, the carrier102is subsequently removed from the integrated circuit dies50A-B, and in such embodiments, the integrated circuit dies50A-B are attached using a release layer or the like. In some embodiments, the carrier102is not subsequently removed from the integrated circuit dies50A-B and is incorporated into the package300(seeFIG.15). In such embodiments, the carrier102may comprises a heat sink or another thermally dissipating structures.

After attaching the integrated circuit dies50A-B, an encapsulant106may be is formed on and around the integrated circuit dies50A-B, in some embodiments. The encapsulant106encapsulates the integrated circuit dies50A-B. The encapsulant106may be a molding compound, epoxy, or the like. The encapsulant106may be applied by compression molding, transfer molding, or the like, and may be formed over the carrier102such that the integrated circuit dies50A-B are buried or covered. The encapsulant106is further formed in gap regions between the integrated circuit dies50. The encapsulant106may be applied in liquid or semi-liquid form and then subsequently cured. In some embodiments, after forming the encapsulant106, a planarization process (e.g., a chemical-mechanical polish (CMP) process, a grinding process, an etching process, and/or the like) may be performed. In some embodiments, the pads66A of the integrated circuit die50A and the pads66B of the integrated circuit die50B are exposed after performing the planarization process. After performing the planarization process, top surfaces of the encapsulant106and the integrated circuit dies50A-B may be level.

FIG.2illustrates a top-down view (e.g., a plan view) of an integrated circuit die50, in accordance with some embodiments.FIG.2also illustrates a portion of the encapsulant106that surrounds the integrated circuit die50. The integrated circuit die50shown inFIG.2is an illustrative example, and may be similar to one or both of the integrated circuit dies50A-B, in some cases. As shown inFIG.2, the integrated circuit die50includes exposed pads66. However, in some cases, the pads66may be laterally offset from corresponding pads to which they are subsequently bonded. For example, the pads66may be laterally offset from corresponding bond pads212of a second package component200, described in greater detail below forFIGS.11-12. The lateral offset may be such that bonding the pads66to the corresponding bond pads212would result in poor or incomplete electrical coupling between the pads212and the bond pads212. The lateral offset of the pads66may be due to misalignment, process variations, or the like, or may be intentional. The locations of the pads66without lateral offset are indicated inFIG.2by corrected pads116. The locations of the corrected pads116correspond to the proper locations to be subsequently bonded to corresponding bond pads212, for example. In other words, the corrected pads116have little or no lateral offset. The locations, number, and arrangement of the pads66and the corrected pads116are an illustrated example, and may be different in other embodiments.

FIGS.3through10illustrate the formation of an adaptive interconnect structure120(seeFIG.9), in accordance with some embodiments. The adaptive interconnect structure120may be formed, for example, to correct any lateral offset of the pads66relative to the subsequently-bonded bond pads212. In some embodiments, the adaptive interconnect structure120includes corrected pads116(seeFIGS.9-10) that are electrically coupled to corresponding pads66. The corrected pads116may be formed in locations that have less lateral offset than the pads66, and thus the corrected pads116may allow for better quality bonding and better electrical coupling to the bond pads212than the uncorrected pads66. The process described inFIGS.3-10is an example, and other processes for forming an adaptive interconnect structure are possible. For example, the adaptive interconnect structure120may be formed using any suitable techniques such as damascene, dual damascene, or the like.

InFIG.3, a first dielectric layer108and a patterned photoresist110is formed, in accordance with some embodiments. The first dielectric layer108may cover top surfaces of the encapsulant106and the integrated circuit dies50A-B. In some embodiments, the first dielectric layer108is formed of a material such as silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, a glass, a polymer, the like, or a combination thereof. The first dielectric layer108may be formed by any acceptable deposition process, such as spin coating, CVD, laminating, the like, or a combination thereof. In some embodiments, the first dielectric layer108may be formed having a thickness in the range of about 0.07 μm to about 1 μm, though other thicknesses are possible. A photoresist110is then formed on the first dielectric layer108, in accordance with some embodiments. The photoresist110may be a single layer or may be a photoresist structure formed of multiple layers. The photoresist110may be formed using suitable techniques, such as spin coating or the like.

Openings112may then be patterned in the photoresist110, in accordance with some embodiments. The openings112correspond to the subsequently formed adaptive lines114(seeFIGS.7-8) that electrically couple the pads66to the subsequently formed corrected pads116. In some embodiments, the pattern of the openings112is determined prior to patterning the photoresist110. For example, the pattern corresponding to the openings112may be based on the locations of the pads66and the locations of the associated corrected pads116. After determining the pattern of the openings112, the photoresist110may then be adaptively patterned to form the openings112. For example, the photoresist110may be adaptively patterned using a programmable lithography tool or the like that allows selective exposure of a photoresist110by controlling the light according to a predetermined pattern rather than by using, for example, using a photomask or the like. The programmable lithography tool may be, for example, a laser-writing system, an electron beam-writing system, a maskless exposure system, or the like. Other programmable lithography tools or adaptive patterning techniques are possible. By using a programmable lithography tool, the lateral offsets of each manufactured structure may be compensated for without requiring the creation of additional photomasks. This can improve process flexibility and also allow for changes to the arrangement of pads66(e.g., by changing to a different integrated circuit die) or bonding pads212without significant changes to the manufacturing process.

In some embodiments, a pattern may be determined and then used for multiple subsequent process runs. In some embodiments, the pattern of the openings112may be determined based on historical data related to the manufacturing process. For example, if it has been observed that a particular lateral offset occurs frequently or consistently over multiple process runs, the pattern may be determined to compensate for this predictable offset. As another example, a different integrated circuit die having a different arrangement of pads66may be used in the structure, with the pattern determined based on the different arrangement of pads66.

In other embodiments, a separate pattern may be determined for each process run. In this manner, a pattern may be determined that more accurately corresponds to the lateral offsets of the pads66. For example, the locations of the pads66may be observed or measured, and then pattern may be determined based on these observations or measurements. In some embodiments, the locations of the alignment marks104,56A, or56B may be observed or measured and the pattern determined based on the locations or relative locations of the alignment marks104,56A, or56B. In some embodiments, the locations of the corresponding bond pads212may be observed or measured instead of or in addition to the locations of the pads66. In this manner, the pattern may be determined based at least partly on the locations of the bond pads212.

FIG.4illustrates a top-down view of an integrated circuit die50after formation of the patterned photoresist110, in accordance with some embodiments. As shown inFIG.4, each opening112may extend from a pad66to a corresponding corrected pad116. The openings112may partially or fully overlap the pads66and/or the corrected pads116. The openings112may have a width that is less than, greater than, or about the same as the width of the pads66or a width of the corrected pads116. The openings112may have different lengths and/or widths, in some embodiments. The length, width, orientation, and/or arrangement of the openings112may depend on the relative positions of the pads66and the corrected pads116.

InFIG.5, the openings112are extended through the first dielectric layer108, in accordance with some embodiments. The openings112may be extended through the first dielectric layer108by etching the first dielectric layer108using the patterned photoresist110as an etching mask, in accordance with some embodiments. For example, a suitable wet etching process and/or dry etching process may be used. After forming openings112in the first dielectric layer108, the photoresist110may be removed using a suitable process, such as an ashing process or the like.

FIG.6illustrates a top down view of an integrated circuit die, in accordance with some embodiments. As shown inFIG.6, the openings112in the first dielectric layer108at least partially expose the pads66. In other embodiments, the openings112fully expose the pads66.

InFIG.7, adaptive lines114are formed in the openings112, in accordance with some embodiments. Once the pads66have been exposed by the openings112, the adaptive lines114may be formed to make physical and electrical contact with the pads66. As shown inFIG.7, the adaptive lines114A make physical and electrical contact with the pads66A of the integrated circuit die50A, and the adaptive lines114A make physical and electrical contact with the pads66A of the integrated circuit die50A. In an embodiment, the adaptive lines114comprise a barrier layer, a seed layer, a fill metal, or a combination thereof. For example, the barrier layer may first be blanket deposited over the first dielectric layer108and within the openings112. The barrier layer may comprise titanium, titanium nitride, tantalum, tantalum nitride, the like, or a combination thereof. The seed layer may be a conductive material such as copper and may be blanket deposited over the barrier layer using a suitable process, such as sputtering, evaporation, plasma-enhanced chemical vapor deposition (PECVD), or the like. The fill metal may be a conductive material such as copper or a copper alloy and may be deposited using a suitable process, such as electroplating, electroless plating, or the like. The fill metal may fill or overfill the openings112, in some embodiments. Once the fill metal has been deposited, excess material of the fill metal, the seed layer, and the barrier layer may be removed using, for example, a planarization process such as a CMP process or the like After the planarization process, top surfaces of the first dielectric layer108and the adaptive lines114may be substantially level or coplanar, in some cases. Other materials or techniques are possible.

FIG.8illustrates a top-down view of an integrated circuit die50after formation of the adaptive lines114, in accordance with some embodiments. The adaptive lines114may have a width that is less than, greater than, or about the same as the width of the pads66or a width of the corrected pads116. The adaptive lines114may have different lengths and/or widths, in some embodiments. The length, width, orientation, and/or arrangement of the adaptive lines114may depend on the relative positions of the pads66and the corrected pads116. In some embodiments, the adaptive lines114may have a width in the range of about 0.032 μm to about 1 μm or a length in the range of about 0.01 μm to about 1 μm, though other widths or lengths are possible.

InFIG.9, corrected pads116are formed on the adaptive lines114, in accordance with some embodiments. In this manner, an adaptive interconnect structure120may be formed on the integrated circuit dies50A-B, forming an integrated circuit component100, in accordance with some embodiments. In some embodiments, a second dielectric layer118may be deposited over the first dielectric layer108and the adaptive lines114. The second dielectric layer118may be formed using materials or techniques similar to those described previously for the first dielectric layer108. In some embodiments, the material of the second dielectric layer118is chosen to allow bonding to other structures (e.g., the second package component200, described below forFIG.11). For example, the second dielectric layer118may be used for a bonding process such as direct bonding, fusion bonding, dielectric-to-dielectric bonding, oxide-to-oxide bonding, or the like. In accordance with some embodiments, the second dielectric layer118is formed of a silicon-containing dielectric material such as silicon oxide, silicon nitride, or the like. The second dielectric layer118may be deposited using any suitable technique. The second dielectric layer118may be deposited to a thickness in the range of about 70 nm to about 1000 nm. However, any suitable material, process, or thickness may be utilized.

The corrected pads116physically and electrically contact the adaptive lines114. For example, inFIG.9, a corrected pad116A contacts the adaptive line114A, and a corrected pad116B contacts the adaptive line114B. In some embodiments, the corrected pads116may be used for a bonding process such as direct bonding, fusion bonding, metal-to-metal bonding, or the like. The corrected pads116may be formed using techniques similar to those described previously for the adaptive lines114, in some embodiments. For example, a photoresist (not illustrated) may be formed on the second dielectric layer118and patterned, with the pattern having openings (not separately illustrated) corresponding to the corrected pads116. In some embodiments, the photoresist may be adaptively patterned using a programmable lithography tool. The openings may be extended into the second dielectric layer118by performing a suitable etching process using the patterned photoresist as an etching mask. Conductive material may then be deposited over the second dielectric layer118and in the openings to form the corrected pads116. The conductive material may be similar to the conductive material of the adaptive lines114, and may be formed using similar techniques. For example, the conductive material may comprise a barrier layer, a seed layer, a fill metal, or a combination thereof. A planarization process may be performed to remove excess conductive material. After performing the planarization process, top surfaces of the second dielectric layer118and the corrected pads116may be substantially level or coplanar, in some cases. Other materials or techniques are possible.

FIG.10illustrates a top-down view of an integrated circuit component100after formation of the corrected pads116, in accordance with some embodiments. The top-down view is similar to that ofFIGS.2,4,6, and8. The corrected pads116may have a width that is smaller than, about the same as, or greater than a width of the pads66.

FIG.11illustrates an integrated circuit component100and a second package component200and prior to bonding, in accordance with some embodiments. The integrated circuit component100and the second package component200are subsequently bonded to form a package300(seeFIG.15). The second package component200shown inFIG.11is an example, and other types of components or structures, interposers, wafers, dies, devices, or the like may be bonded to the integrated circuit component100in other embodiments. The second package component200may include a substrate202and an interconnect structure208formed thereon, in some embodiments.

In some embodiments, the substrate202includes a semiconductor substrate (e.g, a wafer or the like), such as silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The substrate202may include other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. Other substrates, such as multi-layered or gradient substrates, may also be used. In some embodiments, the substrate202has an active surface (e.g., the surface facing downwards inFIG.11), sometimes called a front side or a “top side”, and an inactive surface (e.g., the surface facing upwards inFIG.11), sometimes called a back side.

In some embodiments, circuit devices204may be formed at the front surface of the substrate202. The circuit devices204comprise a wide variety of active devices (e.g., transistors, diodes, or the like) and passive devices (e.g., capacitors, resistors, inductors, or the like) that may be used to generate the desired structural and functional requirements of the design for the package300. The circuit devices may be formed using any suitable methods. In other embodiments, the substrate202is free of active and/or passive devices.

The interconnect structure208may be formed over the substrate202to interconnect the various circuit devices and/or the through-substrate vias206(described below.) The interconnect structure208may be similar to the interconnect structure60of an integrated circuit die50, in some embodiments. In some embodiments, the interconnect structure208may include metallization layers formed of alternating layers of dielectric materials (e.g., low-k dielectric materials or the like) and conductive materials (e.g. metallization patterns, redistribution layers, or the like). The metallization layers may be formed using any suitable process, such as deposition, damascene, dual damascene, or the like. In some embodiments, an interconnect structure208may include alignment marks209used during bonding of the second package component200to the integrated circuit component100. The interconnect structure208shown inFIG.11is an example, and interconnect structures208having other configurations are possible.

In some embodiments, the interconnect structure208includes bond pads212at or near the top of the interconnect structure208, which may be exposed. The bond pads212are electrically coupled to the metallization layers of the interconnect structure208, and may be part of a metallization pattern (e.g., the topmost metallization pattern) of the interconnect structure208, in some embodiments. In some embodiments, the bond pads212are subsequently bonded to the corrected pads116to physically and electrically connect the integrated circuit component100to the second package component200. For example, the bond pads212may be used for a bonding process such as direct bonding, fusion bonding, metal-to-metal bonding, or the like. The bond pads212may comprise materials similar to that of the corrected pads116, though other materials are possible.

In some embodiments, the topmost dielectric layer of interconnect structure208is a material chosen to allow bonding of this topmost dielectric layer to the second dielectric layer118of the integrated circuit component100. For example, the topmost dielectric layer of the interconnect structure208may be used for a bonding process such as direct bonding, fusion bonding, dielectric-to-dielectric bonding, oxide-to-oxide bonding, or the like. For example, the topmost dielectric layer of the interconnect structure208may be formed of a silicon-containing dielectric material such as silicon oxide, silicon nitride, a material similar to that of the second dielectric layer118, or the like. The bond pads212may be formed in the topmost dielectric layer of the interconnect structure208, in some cases.

In some embodiments, through-substrate vias (TSVs)206are formed within the substrate202. The TSVs206may be formed within the substrate202and, if desired, within one or more layers of the interconnect structure208. The TSVs111may be formed in order to provide electrical connectivity from a front side of the substrate202to a back side of substrate202. In an embodiment, the TSVs206may be formed by initially forming TSV openings (not separately illustrated) into the substrate202and, if desired, any of the overlying metallization layers of the interconnect structure208. The openings may then be filled with a conductive material, such as copper or the like. Excess conductive material may then be removed using, for example, a planarization process. In some embodiments, a liner and/or a barrier layer may be deposited in the openings before depositing the conductive material.

InFIG.12, the integrated circuit component100and the second package component200are bonded together, in accordance with some embodiments.FIG.13illustrates a magnified view of the region80indicated inFIG.12. In some embodiments, the integrated circuit component100is bonded to the second package component200using, for example, dielectric-to-dielectric bonding, metal-to-metal bonding, or a combination thereof (e.g., “hybrid bonding”). In some embodiments, the bonding surfaces of the integrated circuit component100and/or the bonding surfaces of the second package component200may be activated prior to bonding. Activating the bonding surfaces may comprise a dry treatment, a wet treatment, a plasma treatment, exposure to an inert gas plasma, exposure to H2, exposure to N2, exposure to O2, the like, or combinations thereof. For embodiments in which a wet treatment is used, an RCA cleaning may be used, in some embodiments. In other embodiments, the activation process may comprise other types of treatments. The activation process facilitates bonding of the integrated circuit component100and the second package component200.

After the activation process, the integrated circuit component100may be placed into contact with the second package component200. In some embodiments, the corrected pads116of the integrated circuit component100is placed into physical contact with the bond pads212of the second package component200while the topmost dielectric layer of the interconnect structure208is placed into physical contact with the second dielectric layer118. In some cases, the bonding process between bonding surfaces begins as the bonding surfaces physically contact each other. The corrected pads116are bonded to the bond pads212to electrically couple the integrated circuit component100and the second package component200.

In some embodiments, a thermal treatment is performed after the bonding surfaces are in physical contact. The thermal treatment may strengthen the bonding between the integrated circuit component100and the second package component200, in some cases. The thermal treatment may include a process temperature in the range of about 200° C. to about 400° C., though other temperatures are possible. In some embodiments, the thermal treatment includes a process temperature that is at or above a eutectic point for a material of the corrected pads116and/or the bond pads212. In this manner, the integrated circuit component100and the second package component200are bonded together using dielectric-to-dielectric bonding and/or metal-to-metal bonding.

Additionally, while specific processes have been described to initiate and strengthen the bonds between the integrated circuit component100and the second package component200, these descriptions are intended to be illustrative and are not intended to be limiting upon the embodiments. Rather, any suitable combination of baking, annealing, pressing, or other bonding processes or combination of processes may be utilized. All such processes are fully intended to be included within the scope of the embodiments.

InFIG.14, a back-side redistribution structure302is formed on the second package component200, in accordance with some embodiments. In other embodiments, a back-side redistribution structure302is not formed. In some embodiments, before forming the back-side redistribution structure302, a planarization process (e.g., a CMP process, a grinding process, or the like) is performed to thin the substrate202and expose the TSVs206. The back-side redistribution structure302may then be formed over the substrate202and the TSVs206, and may make electrical contact to the TSVs206. The back-side redistribution structure302may comprise one or more redistribution layers304, which may comprise conductive lines, conductive vias, metallization layers, metallization patterns, or the like. The back-side redistribution structure302may be formed using a suitable process, such as damascene, dual damascene, or another process. For example, in some embodiments, a passivation layer may be deposited and patterned and then a seed layer may be deposited over the patterned passivation layer. A photoresist may then be deposited and patterned over the seed layer. A redistribution layer304may be formed by depositing conductive material on exposed regions of the seed layer, and then removing the photoresist and underlying regions of the seed layer. This process may be repeated to form a back-side redistribution structure302comprising one or more redistribution layers304. The back-side redistribution structure302may have a different number of layers than shown inFIG.14, which may be formed using any suitable materials or processes.

InFIG.15, conductive connectors310are formed on the back-side redistribution structure302, forming the package300, in accordance with some embodiments. The conductive connectors310allow for electrical connection to external components. In some embodiments, a passivation layer306is formed over the back-side redistribution structure302. The passivation layer306may be a dielectric material, such as polymer, silicon nitride, silicon oxide, or the like, and may be formed using any suitable techniques. In some embodiments, the passivation layer306is part of the back-side redistribution structure302.

Under-bump metallizations (UBMs)308may be formed on the back-side redistribution structure302, in some embodiments. The UBMs308may have bump portions on and extending along the major surface of the passivation layer306, and may have via portions extending through the passivation layer306to physically and electrically contact the top-most redistribution layer304of the back-side redistribution structure302. The UBMs303may be formed of the same material as the redistribution layers304of the back-side redistribution structure302, though other materials or combinations of materials are possible.

Conductive connectors310may then be formed on the UBMs308, in some embodiments. The conductive connectors310may be, for example, ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium-immersion gold technique (ENEPIG) formed bumps, or the like. The conductive connectors310may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connectors310are formed by initially forming a layer of solder through evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once a layer of solder has been formed on the structure, a reflow may be performed in order to shape the material into the desired bump shapes. In another embodiment, the conductive connectors310comprise metal pillars (such as a copper pillar) formed by sputtering, printing, electro plating, electroless plating, CVD, or the like. The metal pillars may be solder free and have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on the top of the metal pillars. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof and may be formed by a plating process.

In other embodiments, UBMs308and/or conductive connectors310are not formed, and the back-side redistribution structure302of the package300may be directly bonded to an external component. In other embodiments, the carrier102is removed after forming the conductive connectors310. In other embodiments, the carrier102may be removed at a prior process step, such as before bonding the integrated circuit component100to the second package component200. In some embodiments, the carrier102is removed and replaced with a heat sink or other heat dissipating structure. In some embodiments, the carrier102comprises a heat sink or other heat dissipating structure, and is not removed. These and other variations for a package300having an adaptive interconnect structure120are considered within the scope of the present disclosure.

FIGS.16through22illustrate cross-sectional views of intermediate steps in the formation of a package600(seeFIG.22), in accordance with some embodiments. The package600is similar to the package300shown inFIG.15, except that a first adaptive interconnect structure120is formed over the front sides of the integrated circuit dies50A-B (similar to the adaptive interconnect structure120of the package300) and a second adaptive interconnect structure420is formed over the back sides of the integrated circuit dies50A-B. Some of the formation steps and/or features of the package600are similar to those of the package300, and are not repeated.

FIG.16illustrates an integrated circuit component400, in accordance with some embodiments. The integrated circuit component400ofFIG.16is similar to the integrated circuit component100described previously forFIG.9, except for some or all of the differences described below. Accordingly, the integrated circuit component400may be formed using materials or techniques similar to those described previously inFIGS.1-9for the integrated circuit component100. The integrated circuit component400includes one or more integrated circuit dies50, which may be similar to those described previously, except that the integrated circuit dies50inFIG.16also include through-substrate vias (TSVs)58. For example, the integrated circuit die50A includes TSVs58A, and the integrated circuit die50B includes TSVs58B. The TSVs58of an integrated circuit die50may be electrically connected to the interconnect structure60of the integrated circuit die50, and may extend into the semiconductor substrate52of the interconnect circuit die50. The integrated circuit dies50may be encapsulated by an encapsulant106, in some embodiments.

The integrated circuit component400includes a first adaptive interconnect structure120formed over the interconnect structures60of the integrated circuit dies50. The first adaptive interconnect structure120may be similar to the adaptive interconnect structure120of the integrated circuit component100, and may be formed using similar techniques. For example, the first adaptive interconnect structure120of the integrated circuit component400may include adaptive lines114in a first dielectric layer108and corrected pads116in a second dielectric layer118. The adaptive lines114electrically connect the corrected pads116to corresponding pads66of the integrated circuit dies50. The adaptive lines114and the corrected pads116may be formed, for example, by determining a pattern, adaptively patterning the pattern into a photoresist using a programmable lithography tool or the like, using the patterned photoresist as an etching mask to etch openings in an underlying dielectric layer, and then filling the openings with a conductive material.

FIG.16illustrates an integrated circuit component400and a second package component500and prior to bonding, in accordance with some embodiments. The integrated circuit component400and the second package component500are subsequently bonded to form a package600(seeFIG.22). In some embodiments, the carrier102may be removed prior to bonding the integrated circuit component400and the second package component500. The second package component500is similar to the second package component200described previously (seeFIG.11), except that in some embodiments the second package component500may not include TSVs206. For example, the second package component500may include a substrate202, an interconnect structure208formed on the substrate202, and bond pads212formed in the interconnect structure208, in some embodiments. The second package component500shown inFIG.17is an example, and other types of components or structures may be bonded to the integrated circuit component400in other embodiments.

InFIG.18, the integrated circuit component400and the second package component500are bonded together, in accordance with some embodiments. In some embodiments, the integrated circuit component400is bonded to the second package component500using, for example, dielectric-to-dielectric bonding, metal-to-metal bonding, or a combination thereof (e.g., “hybrid bonding”). For example, the corrected pads116of the integrated circuit component400may be directly bonded to the bond pads212of the second package component500to electrically connect the integrated circuit component400and the second package component500. The bonding process may be similar to the bonding process described previously forFIG.12. For example, the bonding process may include an activation process and/or a thermal treatment.

FIGS.19and20illustrate intermediate steps in the formation of a second adaptive interconnect structure420on the integrated circuit component400, in accordance with some embodiments. The adaptive interconnect structure120may be formed, for example, to correct any lateral offset of the TSVs58. For example, the second adaptive interconnect structure420may comprise adaptive lines430(seeFIG.20) that make electrical connections between the TSVs58and an overlying structure, such as the back-side redistribution structure602(seeFIG.21) or another component. The adaptive lines426may extend from the TSVs58to locations that have less lateral offset than the TSVs58, and thus the adaptive lines426may allow for better quality bonding and better electrical coupling to subsequently-formed or subsequently-bonded structures. The second adaptive interconnect structure420may be formed using techniques similar to those used for the first adaptive interconnect structure120. In some embodiments, a planarization process (e.g., a CMP process, a grinding process, or the like) is performed to thin the back sides of the integrated circuit dies50and expose the TSVs58. After performing the planarization process, top surfaces of the encapsulant106, the semiconductor substrates52of the integrated circuit dies50, and the TSVs58of the integrated circuit dies50may be substantially level or coplanar.

InFIG.19, a dielectric layer422and a patterned photoresist424is formed, in accordance with some embodiments. The first dielectric layer422may cover top surfaces of the encapsulant106and the integrated circuit dies50A-B. The dielectric layer422may be formed using materials or techniques that are similar to those described previously for the first dielectric layer108or the second dielectric layer118, in some embodiments. A photoresist424is then formed on the dielectric layer422, and may be formed using materials or techniques that are similar to the photoresist110described previously. Openings428may then be patterned in the photoresist422that correspond to the subsequently formed adaptive lines430(seeFIG.20). The openings428may be formed, for example, by determining a pattern and adaptively patterning the pattern into the photoresist424using a programmable lithography tool or the like.

InFIG.20, adaptive lines430are formed in the dielectric layer422, in accordance with some embodiments. The adaptive lines430may be formed by etching the dielectric layer422using the patterned photoresist424as an etching mask. In this manner, the openings428are extended through the dielectric layer422to expose the TSVs58. The dielectric layer422may be etched using a suitable wet etching process and/or dry etching process. The photoresist424may be removed using a suitable process such as an ashing process. Conductive material may then be deposited on the dielectric layer422and within the openings428in the dielectric layer422. The conductive material may be similar to the material(s) of the first interconnect structure120and may be formed using similar techniques. A planarization process (e.g., a CMP process or a grinding process) may be performed to remove excess conductive material and form the adaptive lines430of the second adaptive interconnect structure420. Forming a second adaptive interconnect structure420may improve process flexibility and allow for improved connections to the TSVs58.

InFIG.21, a back-side redistribution structure602is formed on the second adaptive interconnect structure420, in accordance with some embodiments. In other embodiments, a package component or the like may be formed and bonded to the adaptive interconnect structure420. In other embodiments, a back-side redistribution structure602is not formed. The back-side redistribution structure602may be similar to the back-side redistribution structure302, and may be formed using similar techniques. For example, the back-side redistribution structure602may comprise one or more redistribution layers604, and may be formed using damascene, dual damascene, or another process. The back-side redistribution structure602is electrically coupled to the TSVs58of the integrated circuit dies50through the second adaptive interconnect structure420.

InFIG.22, conductive connectors610are formed on the back-side redistribution structure602, forming the package600, in accordance with some embodiments. In some embodiments, a passivation layer606is formed over the back-side redistribution structure602, which may be similar to the passivation layer306described previously. In some embodiments, under-bump metallizations (UBMs)608may be formed on the back-side redistribution structure602, which may be similar to the UBMs308described previously. Conductive connectors610may be formed on the UBMs608, which may be similar to the conductive connectors310described previously. The conductive connectors610allow for electrical connection to external components. In other embodiments, UBMs608and/or conductive connectors610are not formed. In some embodiments, the substrate202of the second package component500is thinned using a planarization process, such as a CMP process or a grinding process.

FIGS.23,24, and25illustrate intermediate steps in the formation of a package700(seeFIG.25), in accordance with some embodiments. The package700is similar to the package600ofFIG.22, except that the first adaptive interconnect structure120includes connecting lines115that connect pads66A of the integrated circuit die50A to pads66B of the integrated circuit die50B, and the second adaptive interconnect structure420includes connecting lines431(seeFIG.25) that connect TSVs58A of the integrated circuit die50A to TSVs58B of the integrated circuit die50B. Connecting lines115or143may be formed to connect more than two integrated circuit dies50in other embodiments. In other embodiments, one of the first adaptive interconnect structure120or the second adaptive interconnect structure420is not present. In other embodiments, the connecting lines115and/or the connecting lines431are not present. Forming connecting lines115or143as described herein can allow for additional interconnections to be formed within a package, which can allow for a more flexible layout and for interconnections of shorter lengths.

FIG.23illustrates the formation of adaptive lines114and connecting lines115of the first adaptive interconnect structure120, in accordance with some embodiments. The connecting lines115may be formed along with the adaptive lines114using techniques similar to those described inFIGS.3-7. For example, openings corresponding to the connecting lines115may be adaptively patterned in a photoresist (e.g., the photoresist110) using a programmable lithography tool or the like. The pattern of the openings may be etched into the first dielectric layer108using the patterned photoresist as an etching mask. The openings corresponding to the connecting lines115may expose pads66of multiple integrated circuit dies50. For example, an opening may extend from a pad66A of the integrated circuit die50A to a pad66B of the integrated circuit die50B. Conductive material may then be deposited into the openings, forming the adaptive lines114and the connecting lines115.

FIG.24illustrates a top-down view after the formation of the adaptive lines114and the connecting lines115, in accordance with some embodiments. The structure shown inFIG.24is an illustrative example, and other configurations or arrangements are possible in other embodiments. As shown inFIG.24, adaptive lines114A are formed over pads66A of the integrated circuit die50A and adaptive lines114B are formed over pads66B of the integrated circuit die50B. Additionally, a plurality of connecting lines115A-D are formed extending from pads66A of the integrated circuit die50A to pads66B of the integrated circuit die50B, which electrically couples the integrated circuit dies50A-B. Connecting line115A extends from a pad66A to a pad66B, but also extends into locations where corrected pads116A and116B are subsequently formed. Connecting line115B extends from a pad66A to a pad66B, but extends only into a location where a corrected pad116A is subsequently formed. Connecting line115C extends from a pad66A to a pad66B, but extends only into a location where a corrected pad116B is subsequently formed. Connecting line115D extends from a pad66A to a pad66B, but no corrected pads116are subsequently formed over connecting line115D. The connecting lines115A-D shown inFIG.24are illustrative examples, and other configurations, arrangements, numbers, or combinations of connecting lines115are possible.

FIG.25illustrates a package700formed after subsequently processing the structure ofFIG.24, in accordance with some embodiments. The package700may be formed using process steps similar to those described previously inFIGS.16-22for the package600. For example, corrected pads116may be formed to form the first adaptive interconnect structure120of an integrated circuit component400, and a second package component500may be bonded to the first adaptive interconnect structure120.

Similar to the package600, the package700may include a second adaptive interconnect structure420formed over the back side of the integrated circuit component400. The second adaptive interconnect structure420ofFIG.25may be similar to the second adaptive interconnect structure420described previously forFIGS.19-20, except for the presence of connecting lines431. The connecting lines431may extend over and electrically couple TSVs58of different integrated circuit dies50, in some embodiments. In some embodiments, one or more connecting lines431are electrically connected to one or more TSVs58and to the overlying back-side redistribution structure602. In some embodiments, one or more connecting lines431are not formed over and electrically connected to TSVs58, but are electrically connected to the overlying back-side redistribution structure602. The connecting lines431may be formed along with the adaptive lines430. Forming connecting lines431in this manner may improve process flexibility or design flexibility, and may allow for improved interconnection between features.

In some embodiments, a back-side redistribution structure602may be formed over the second adaptive interconnect structure420, which may be similar to the back-side redistribution structure602described forFIG.21. The redistribution layers604of the back-side redistribution structure602may physically and electrically contact the adaptive lines430and/or the connecting lines431of the second adaptive interconnect structure420. In some embodiments, a passivation layer606, UBMs608, and/or conductive connectors610may be formed, which may be similar to those described previously. The package700is an example, and other configurations or variations are possible.

Embodiments may achieve advantages. By forming an adaptive interconnect structure as described herein more precise bonding alignment may be achieved. Lateral offsets or misalignments may be compensated for, which can improve bonding, device performance, device reliability, and yield. The use of adaptive patterning techniques allow for corrected bonding pads to be formed without the use of costly photomasks or the like. In some cases, the adaptive interconnect structure may be used to compensate for design errors or process errors without the use of costly photomasks. The formation of the adaptive interconnect structure may utilize programmable photolithography tools and techniques, and thus pattern of the adaptive interconnect structure may be determined on a per-device basis or may be determined based on historical data or process data. In this manner, the manufacturing of a package may be adjusted without additional processing steps. Additionally, connections between adjacent devices such as integrated circuit dies may be formed within the adaptive interconnect structure.

In accordance with some embodiments of the present disclosure, a method includes forming a first adaptive interconnect structure on a first side of a first semiconductor device, including determining a first lateral offset between a first lateral location of a first conductive pad of the first semiconductor device and a second lateral location, wherein the second lateral location corresponds to a location of a bond pad of a package component; based on the first lateral offset, forming a first conductive line on the first conductive pad, wherein the first conductive line extends from the first lateral location to the second lateral location; and forming a second conductive pad on the first conductive line, wherein the second conductive pad is at the second lateral location; and bonding the second conductive pad to the bond pad. In an embodiment, the determining of the first lateral offset is performed after attaching the first semiconductor device to a carrier. In an embodiment, the method includes forming a second adaptive interconnect structure on a back side of a first semiconductor device, including determining a second lateral offset between a third lateral location of a first through-substrate via of the first semiconductor device and a fourth lateral location, wherein the fourth lateral location corresponds to a location of a conductive feature of a back-side redistribution structure; and based on the second lateral offset, forming a second conductive line on the first through-substrate via, wherein the second conductive line extends from the third lateral location to the fourth lateral location. In an embodiment, the second conductive line physically and electrically connects the first through-substrate via of the first semiconductor device and a second through-substrate via of a second semiconductor device. In an embodiment, the method includes forming a back-side redistribution structure over the back side of the first semiconductor device, wherein the back-side redistribution structure is electrically connected to the second conductive line. In an embodiment, the method includes forming the first adaptive interconnect structure on a first side of a third semiconductor device, wherein the first adaptive interconnect structure includes a third conductive line extending from a fifth lateral location of a third conductive pad of the first semiconductor device to a sixth lateral location of a fourth conductive pad of the third semiconductor device. In an embodiment, forming the first conductive line includes using a programmable photolithographic tool to form an opening in a mask corresponding to the first conductive line. In an embodiment, the programmable photolithographic tool is a laser writing system. In an embodiment, the package component includes through substrate vias, and the method includes forming a redistribution structure over and electrically connected to the through substrate vias.

In accordance with some embodiments of the present disclosure, a method includes attaching integrated circuit dies to a carrier, wherein each integrated conductive die includes conductive pads at a top surface of that integrated circuit die; determining a lateral offset for each conductive pad of each of the integrated circuit dies, wherein each lateral offset represents a difference between a measured location of the respective conductive pad and a desired location of the respective conductive pad; forming a first dielectric layer over the integrated circuit dies; patterning first openings in the first dielectric layer, wherein the pattern for each of the first openings is determined from the measured location, the lateral offset, and the desired location of a corresponding conductive pad; depositing a first conductive material in the first openings; forming a second dielectric layer over the first dielectric layer; patterning second openings in the second dielectric layer, wherein the pattern for each of the second openings is determined from the desired location of a corresponding conductive pad; and depositing a second conductive material in the second openings to form first bonding pads. In an embodiment, the method includes directly bonding a package component to the first bonding pads. In an embodiment, the package component includes second bonding pads, wherein the location of each second bonding pad corresponds to the desired location of a conductive pad. In an embodiment, directly bonding a package component to the first bonding pads includes bonding each first bonding pad to a corresponding second bonding pad using metal-to-metal bonding. In an embodiment, patterning the first openings includes depositing a photoresist over the first dielectric layer; using a programmable photolithography tool to pattern the photoresist; and etching the first dielectric layer using the patterned photoresist as an etching mask. In an embodiment, the programmable photolithography tool is a maskless photolithography system. In an embodiment, the method includes patterning third openings in the first dielectric layer, wherein the pattern for each of the third openings is determined from the measured location of a conductive pad of a first integrated circuit die of the integrated circuit dies and from the measured location of a conductive pad of a second integrated circuit die of the integrated circuit dies; and depositing the first conductive material in the third openings.

In accordance with some embodiments of the present disclosure, a package includes a first package component including a semiconductor die, wherein the semiconductor die includes conductive pads, wherein the semiconductor die is surrounded by an encapsulant; an adaptive interconnect structure on the semiconductor die, wherein the adaptive interconnect structure includes conductive lines, wherein each conductive line physically and electrically contacts a respective conductive pad; and first bond pads, wherein each first bond pad physically and electrically contacts a respective conductive line; and a second package component including an interconnect structure, wherein the interconnect structure includes second bond pads, wherein each second bond pad is directly bonded to a respective first bond pad, wherein each second bond pad is laterally offset from a corresponding conductive pad which is electrically coupled to that second bond pad. In an embodiment, the conductive lines are formed in a first dielectric layer, wherein the first dielectric layer extends over the semiconductor die and over the encapsulant. In an embodiment, the first bond pads are formed in a second dielectric layer, wherein the second dielectric layer extends over the semiconductor die and over the encapsulant. In an embodiment, each second bond pad has the same lateral offset from its corresponding conductive pad.