Diagnosable scan chain

A method and system for locating connector defects in a defective scan chain that has a parallel non-defective scan chain on a different wiring level, with both scan chains being laid out in a regular array pattern. A predetermined bit sequence is scanned into the defective scan chain. The contents of the defective scan chain are then parallel shifted into the non-defective scan chain. The contents of the non-defective scan chain is then scanned out and compared with the predetermined bit sequence. The comparison of the scanned out bits with the predetermined bit sequence facilitates locating both physically and logically where a connector defect has occurred in the defective scan chain.

BACKGROUND OF INVENTION

1. Technical Field

The present invention relates in general to the field of computers, and in particular to the testing of circuits, including integrated circuits. Still more particularly, the present invention relates to a method and system for locating a defect in a scan chain.

2. Description of the Related Art

A significant expense incurred during the manufacture of integrated circuit (IC) wafers is testing. Such testing generally entails inputting data into a logic circuit on the wafer at a first test access point, and then reading the output results at a second test access point. Often, finer granularity is required to determine whether the logic is functioning properly. That is, a known input data into a logic circuit may result in a desired (expected) output, but the desired output may be the result of multiple offsetting errors. For example, if a “1” is input into three inverters in series, a “0” will be output whether all three inverters are working properly or if only one of the inverters is functioning and the other two are straight shorts. To determine whether the complete logic circuit is functioning properly, data is read out at intermediate logic levels using scan chains, which allow probes to pull off intermediary ults from the logic circuit.

Referring toFIG. 1, there is depicted a prior art scan chain100, which includes combinational logic blocks102a,102b, and102c, which represent combinational logic that executes various predetermined logic functions. The combinational logic blocks are interconnected by a scan chain latch circuit104a, which interconnects combinational logic blocks102aand102b, and scan chain latch circuit104bwhich interconnects combinational logic blocks102band102c.

Data is written to the combinational logic blocks102a,102b, and102cin a parallel or broadside manner via respective primary input (PI) vectors106a,106b,106c. Data is read from the combinational logic blocks102a,102b,102cin a parallel fashion to the primary output (PO) vectors108a,108b,108c, respectively. The PO vectors108a,108bfunction as PI vectors to respective scan chain latch circuits104aand104b.

The scan chain latch circuits104aand104bmay also be loaded serially to enable testing of the scan chain latches104aand104b. In particular, shift register input (SRI) line120provides a serial input to scan chain latch104a. Similarly, shift register output (SRO) line122provides an output from scan chain latch104b. Scan chain latches104aand104bare interconnected by serial line124. Serial line124functions as a SRO for scan chain latch104aand as an SRI for scan chain latch104b. One or a plurality of system clocks126output timing signals to control timing operations of the combinational logic blocks102and scan chain latches104. One or a plurality of scan chain clocks128provide timing signals to scan chain latches104.

While scan chains are useful in determining whether a logic circuit is functioning properly, the scan chains themselves may also be defective. While such defects may be from defective latches in the scan chain, if the latches are robust (designed to ensure their integrity), then defects are primarily in the wiring connecting the latches. Such defects may be opens (a clean break in the wiring), shorts (the wiring touching another wire inadvertently), or stuck-at faults (the wiring touching either ground or voltage). The most problematic wiring defect is a stuck-at fault, since the latch otherwise appears to be functioning properly, albeit with a constant input value. That is, if a connector going into the input of the latch is shorted to ground, then that latch will only be able to latch a logical zero. Likewise, if the input is shorted to voltage, then that latch will only be able to latch a logical one.

Therefore, it would be beneficial to have a method and system that could locate exactly where in the scan chain the connector defect occurred. By finding the exact location of the defect, a more precise manufacture solution for correcting the defect can be determined for the defective scan chain, as well as the overall wiring layer of the IC. Preferably, such an method and system would detect the location of multiple connector defects.

SUMMARY OF INVENTION

The present invention is directed to a method and system for locating connector defects in a defective scan chain that has a parallel non-defective scan chain on a different wiring level, with both scan chains being laid out in a regular array pattern. A predetermined bit sequence is scanned into the defective scan chain. The contents of the defective scan chain are then parallel shifted into the non-defective scan chain. The contents of the non-defective scan chain is then scanned out and compared with the predetermined bit sequence. The comparison of the scanned out bits with the predetermined bit sequence facilitates locating both physically and logically where a connector defect has occurred in the defective scan chain.

DETAILED DESCRIPTION

With reference now toFIG. 2a, there is illustrated an exemplary scan chain matrix200as used in a preferred embodiment of the present invention. Scan chain matrix200includes three parallel scan chains202,204and206, each in parallel with another scan chain each and having associated latches222corresponding between the scan chains. Scan chains202and206have no defects, but scan chain204has one or more defects in the connectors250between at least one pair of latches222.

Latches222are preferably master/slave latch pairs, but may be any bit or state holding device known to those skilled in the art of integrated circuit (IC) design. In a preferred embodiment, each scan chain is physically wired on a different wiring level of an IC chip or wafer. These wiring levels are preferably on different metal levels, but may be on any different wiring level as understood by those skilled in the art of IC fabrication. Thus scan chain202is physically wired on wiring level1, scan chain204is on wiring level2, and scan chain206is on wiring level3. Latches222on different wiring levels are coupled via connectors224, including the depicted connectors224aand224b. Note further thatFIG. 2illustrates scan chain202as being contiguous with and parallel connected to scan chain204, which is contiguous with and parallel connected to scan chain206. However, in a preferred embodiment, scan chain202may be parallel connected to scan chain206, such that scan chain202can be defective and scan chain206non-defective for use with the present invention.

In a preferred embodiment, coupling of latches222is through a multiplexer (MUX)230, as shown inFIG. 2d. The outputs of the latch222-1bfrom wiring level1, latch222-2afrom wiring level2, and latch222-3bfrom wiring level3are input into MUX230. Note that latch222-1b, latch222-2band latch222-3bare in the same row and parallel coupled. Note further that each latch222in scan chain matrix has an associated dedicated single MUX230. The input bit to be latched by latch222-2bis determined by a signal on selector line232, which signal is produced by a selector logic234that controls whether data is serially shifted through a scan chain (e.g., from latch222-2ato latch222-2b) or parallel shifted from one scan chain to another scan chain (e.g., from latch222-3bor latch222-1bto latch222-2b).

Referring again toFIG. 2a, scan chain204has two stuck-at defects, a first upstream stuck-at defect208aand a last downstream stuck-at defect208b. A stuck-at defect is one in which the input to a latch is “stuck at” either a one (“stuck-at-high” defect in which the input is shorted to a logical high voltage source) or a zero (“stuck-at-low” defect in which the input is shorted to a logical low ground source). For purposes of illustration, all scan chain defects are illustrated as stuck-at-low defects. However, the present invention is also applicable for use with stuck-at-high defects by scanning and shifting alternate signals (ones instead of zeros and zeros instead of ones) as described below.

The first step in determining the location of the first upstream stuck-at failure208ain scan chain204is to scan a series of all ones into scan chain204. (Note that scan chain202is not used inFIGS. 2a–cand3a–c, but is used as described inFIGS. 4a–c. Note also that “x” denotes a “don't care” state in each latch222depicted in the figures.) When the scanned in series of ones reaches the first upstream stuck-at failure208a, then downstream latches222-2d–hall latch zeros instead of the scanned in ones. That is, latch222-2dlatches a zero since its input is stuck at (shorted to) ground, and thus all downstream latches222-2e–hare likewise latched to zero.

The contents of scan chain204in latches222-2a–hare then parallel shifted to scan chain206in level3, as illustrated inFIG. 2b. The parallel shifting is preferably performed using MUX230shown inFIG. 2d. The select signal, generated by parallel shifting logic234, on selector line232selects the input to latch222-3bas that coming from latch222-2b, thus resulting in a parallel shift of data from scan chain204to scan chain206. Each other latch222in scan chain206has its own dedicated MUX230, and thus parallel shifts all data at the same time. That is, scan chain206now has a copy of the defective contents of scan chain204, resulting in ones in the first three upstream latches222-3a–cand zeros in the last five downstream latches222-3d–h.

As depicted inFIG. 2c, the contents of scan chain206are then scanned out to counting logic220. Counting logic detects five zeros and then three ones. By counting backwards to the point where the data bits transition from zero to one, the location of first upstream stuck-at failure208ais identified as being at the connector250between latch222-2cand latch222-2d. While the steps illustrated inFIG. 2assume only stuck-at-low wiring defects, it is possible that there may be a combination of stuck-at-low and stuck-at-high wiring defects in the defective scan chain. If so, then identifying the last point where the data bits transition from zero to one will identify the location of the first upstream stuck-at failure.

Since first upstream stuck-at failure208amasks the inputs of all downstream latches222-2, a second operation, illustrated inFIGS. 3a–c, is necessary to locate last downstream stuck-at failure208b. As shown inFIG. 3a, all ones are serially shifted into non-defective scan chain206. As illustrated inFIG. 3b, the contents of scan chain206are then parallel shifted, in a similar manner described above in reference toFIGS. 3a–c, from scan chain206to scan chain204. As shown inFIG. 3c, the data in scan chain204is then serially scanned out to counting logic220, which counts the number of ones to determine the location of the last stuck-at failure208b. In the example described inFIGS. 3a–c, the counting logic220will count four ones, and only zeros thereafter, because of the stuck-at failure208blocated between latch222-2dand latch222-2e. That is, although latches222-2a–dwere loaded with ones from the parallel shift from scan chain206, when serially read out the contents of latches222-2a–dwill appear to be zeros (as indicated by the parenthetical zeros in these upstream latches).

FIGS. 2a–candFIGS. 3a–cutilize only two scan chains204and206in two scan/shift iterations to locate the defects208aand208b.FIGS. 4a–cillustrate the use of three scan chains in one iteration to accomplish the same result.FIGS. 4a–cdepict two non-defective scan chains202and206and one defective scan chain204. As shown inFIG. 4a(and still assuming that the defect in scan chain204is a stuck-at-low defect), scan chains202,204and206are initially serially scanned in with all ones (although latches222-2dthrough202-2hlatch zeros dues to stuck-at failure208a). Scan chain204is parallel shifted to scan chain206and scan chain202is subsequently parallel shifted to scan chain204in a manner described above using MUX230and selector234. Finally, as depicted inFIG. 4c, scan chains204and206are serially shifted out to counting logic220. The data scanned out of scan chain204identifies the location of the last downstream stuck-at failure208bin a manner described above forFIG. 3c, and the data scanned out of scan chain206identifies the location of the first upstream stuck-at failure208ain a manner described above forFIG. 2c.

For purposes of clarity,FIGS. 2–4show only three scan chains on different wiring levels. However, in a preferred embodiment of the present invention, more than three parallel scan chain wiring levels are used, such that a bad scan chain is not limited to using only good scan chains on contiguous levels. For example, inFIGS. 2a–c, scan chain204on wiring level2described as being parallel coupled, using the circuitry shown inFIG. 2d, to scan chain202and scan chain206. However, if both scan chains202and206are also defective, then scan chain204can continue to parallel shift past either scan chain202or206to another scan chain on another wiring level (not shown inFIGS. 2a–c,3a–cor4a–c). Referring then toFIG. 2e, if the scan chain206at level3is defective, then parallel shifting logic234parallel shifts the data in latch222-2bthrough MUX230aat level3and latch222-3b, and on, via connector240, to MUX230band latch222-4bin a level4wiring level. Thus, parallel shifting logic234associated with each MUX230allows data to continue to parallel shift until the data reaches a non-defective scan chain. Although not shown, it is understood that level4latch222-4bcan likewise parallel shift data to level2latch222-2bby shifting data through MUX230aand level3latch222-3bvia an analogous MUX230(not shown) associated with level2latch222-2b. Thus, even if a first defective scan chain is contiguous with another second defective scan chain, the data in the first defective scan chain can be parallel shifted to subsequent level scan chains until a non-defective scan chain is reached to receive the parallel shifted data from the first defective scan chain.

FIG. 5is a flow-chart describing the operations shown inFIGS. 2–3. The operations described within box502describe the steps taken to identify first upstream stuck-at failure208ain a manner shown inFIGS. 2a–c, and the operations shown within box503describe the steps taken to identify last downstream stuck-at failure208bin a manner illustrated inFIGS. 3a–c. Thus, after starting at initiator510, the defective scan chain204is identified (block512) utilizing any technique known and selected by the user. For example, the user can scan in a known string of bits, either a pattern of different ones and zeros or all ones or all zeros, into the scan chain, then scan out the contents of the scan chain, and then compare the known string of scanned in bits with the scanned out bits ensure that they are the same. If the strings of bits are not the same (assuming no intentional inversions or other intentional modifications of the bits), then there is a defect in the scan chain.

Next, the parallel shifting mechanism is checked (block513), described in a preferred embodiment in further detail inFIG. 7. The defective scan chain is then scanned with all ones (assuming the defect is a stuck-at-low defect), as described in block514. The data from the defective scan chain is then parallel shifted to a good scan chain (block516), which is then scanned out to a counter, which notes when the last zero transitions to a one (block518). This transition identifies the location of the first upstream stuck-at defect208a(block520).

The examples depicted inFIGS. 2a–c,3a–cand4a–call assumed that the scan chain defect was a stuck-at-low defect. However, such a defect could be a stuck-at-high defect, in which a connector240is shorted to a logical high voltage. If so, then the process described above still will identify the location of the stuck-at defect if the bits scanned in are opposite those described above for a stuck-at-low defect. If the scan/shift process has only searched for stuck-at-low defects through a first time search (decision block522), then the process is continued for the same scan chain using opposite data bits to search for stuck-at-high defects. Thus, the defective scan chain204is now scanned with all zeros (block514), the contents of the defective scan chain204are parallel shifted into non-defective scan chain206(block516), the contents of non-defective scan chain206are serially shifted out (block518), and the counting logic220notes the last transition from one to zero (block520) to identify the location of the first upstream stuck-at-high defect (analogous to the stuck-at-low defect208a). In the example illustrated, there is only one transition from one to zero. However, if there were multiple stuck-at-low and stuck-at-high defects in the scan chain, then the last transition from one-to-zero is the transition that identifies the location of the first upstream stuck-at-high defect.

Proceeding to blocks503, there are depicted exemplary steps taken using a preferred embodiment of the present invention to identify a last downstream stuck-at defect in a scan chain, as described above inFIGS. 3a–c. Assume first that the last downstream stuck-at defect is a stuck-at-low defect, such as stuck-at defect208b. Non-defective scan chain206is scanned with all ones (block526). The data in non-defective scan chain206is then parallel shifted into defective scan chain204(block528). The data bits in scan chain204are then serially shifted into counting logic220, noting the point at which the data transitions from one to zero (block530) to identify the location of the last stuck-at defect (block532). As in blocks502, a decision (block534) is made as to whether the data scan/shifting has been performed before. If not, then the data bits are inverted as in block502to locate a stuck-at-high last downstream defect. Thus, the good scan chain206is scanned in with zeros (block526), which are then parallel shifted to the defective scan chain204(block528). The contents of defective scan chain204are serially scanned out, noting the transition from zeros to ones (block530) to identify the location of the last downstream stuck-at-high defect (block532), which is analogous to the stuck-at-low defect208b. The process then terminates at terminator block538. In a manner analogous to that described above for blocks502, the first transition from one to zero will identify the last stuck-at-high defect if there are multiple stuck-at-high and stuck-at-low defects.

FIG. 6is a flow-chart describing the operations illustrated inFIGS. 4a–c. After starting at initiator block602, the defective scan chain is identified, as are two non-defective scan chains (block604). Ones are then scanned into all three scan chains (block606), and the contents of scan chain204in wiring level2are parallel shifted into scan chain206in wiring level3(block608), and the contents of non-defective scan chain202are parallel shifted into defective scan chain204(blocks608and610). The contents are then serially scanned out of scan chain206to identify the location of first upstream stuck-at-low defect208a(block612) and out of scan chain204to identify the location of last downstream stuck-at-low defect208b(block614). Note that in a preferred embodiment, the bits are inverted in the process shown inFIG. 6in a manner analogous to that shown in blocks524and536inFIG. 5to identify any stuck-at-high defects.

The described process and system assume that the parallel shifting system, shown in an exemplary embodiment inFIG. 2d, is functioning properly. To ensure this integrity, a preferred embodiment of the present invention includes the steps described inFIG. 7. After starting at initiator block702, the defect free scan chain and the defective scan chain are first identified (block704), utilizing any known process, such as scanning in a known string of bits, either as a pattern of different ones and zeros or all ones or all zeros, and then scanning out the known string of bits and comparing the scanned out bits with the scanned in bits to ensure that they are the same.

The good scan chain is scanned with all ones (block706). The ones in the good scan chain are then parallel shifted into the bad scan chain (block708), and then the good scan chain is scanned in with all zeros (block710). The contents of the bad scan chain (containing all ones if the parallel shifting mechanism is properly working) are then scanned into the good scan chain (block712), whose contents are then scanned out, noting the presence of any zeros (block714) which would indicate that the parallel shifting mechanism has a stuck-at defect somewhere between the latches in the bad scan chain and the good scan chain.

The process then tests for stuck-at-high defects in the parallel shifting mechanism. Thus at block718, the good scan chain is scanned with all zeros (block718), the contents of the good scan chain are parallel shifted into the bad scan chain (block720), all ones are scanned into the good scan chain (block722), the contents of the bad scan chain (should be all zeros) are scanned into the good scan chain (block724), and the contents of the good scan chain are then scanned out, noting any ones (indicating a stuck-at-high defect between the bad scan chain and the good scan chain). The process then terminates at block728.

In a preferred embodiment, each scan chain is wired on a precise wiring level. This means that all wires leading into and out of each latch of a scan chain are on a given wiring level. Thus if there is a fail in the scan chain, it is very likely that the fail occurred in the given wiring level. Very often in the early stages of technology development, certain manufacturing levels will have systematic defects, that once corrected allow for higher overall manufacturing yield. By identifying which wiring levels have abnormally high scan chain failures (or parallel shifting mechanism failures), the wafer fabricator can identify, during the wafer manufacturing process, which wiring layer(s) need corrective steps to be taken in the manufacturing process. For instance, if Level1had 28 non-defective scan chains out of 32, Level2had 29 non-defective scan chains out of 32, and Level3had 21 non-defective scan chains out of 32, then a manufacturing engineer could first spend time diagnosing fails on Level3to explain the significantly lower yield.FIG. 8depicts such an identification process. After starting at initiator block802, the wiring level and scan chain number are first identified (block804). The number of scan chain failures are initialized at zero (block806), and the first scan chain is flushed and scanned (block808). If there are any errors in the first scan chain (block810), the counter for the number of scan chain errors for the first wiring level is increased by one (block812), and the next scan chain in the wiring level is then examined (blocks814and816, continuing to block808et seq.). When all of the scan chains in a wiring level have been examined for any errors (block818), then the wiring level is incremented and the next level is examined for any scan chain errors (blocks820,822, and824) until all levels have been examined. While the evaluation of each wiring level is shown as the number of scan chains having at least one defect, alternatively the evaluation of each wiring level can evaluate how many total defects in the scan chains are identified using the process described above for locating first upstream stuck-at defects, last downstream stuck-at errors, parallel shifting mechanism errors, and other errors, such as opens (broken wires that are not shorted to any other wire). Further, in a preferred embodiment, the scan chains are laid out in a predetermined X-Y Cartesian coordinate matrix. By identifying the location of the defect in the defective scan chain, and identifying which wiring level the scan chain is on, the manufacturing engineer of the circuit can identify specific physical problem areas of the circuit. The engineer can then make correcting adjustments to the manufacturing process, such as changing masks, thicknesses of strata, etc.

While the present invention has been described as locating stuck-at-low and stuck-at-high connector defects, the present invention is also useful in locating defective latches. That is, if a latch itself is stuck at high or low, then the downstream bits latched will be similar to those described for a stuck-at connector defect, and the process for locating the defective latch is the same as that used to locate the defective connector.

The present invention thus provides a way to specifically locate a wiring defect in a circuit. While the present invention has been described in the context of integrated circuits being evaluated either at the wafer or chip level in manufacturing, the present invention is also useful in identifying any analogous wiring defect in a circuit having parallel registers, chains or other state or bit storing units. Thus, a wiring level is preferably first identified according to the number of failures on that level. To focus with more precision on where the errors are occurring on the level, good and bad scan chains are identified, their parallel shifting mechanism is tested, and the process then locates the stuck-at defect as described above. This process permits precise identification of defect spots, which can then be addressed by the manufacturing engineers.

It should be understood that at least some aspects of the present invention may alternatively be implemented in a program product. Programs defining functions on the present invention can be delivered to a data storage system or a computer system via a variety of signal-bearing media, which include, without limitation, non-writable storage media (e.g., CD-ROM), writable storage media (e.g., a floppy diskette, hard disk drive, read/write CD ROM, optical media), and communication media, such as computer and telephone networks including Ethernet. It should be understood, therefore in such single-bearing media when carrying or encoding computer readable instructions that direct method functions in the present invention, represent alternative embodiments of the present invention. Further, it is understood that the present invention may be implemented by a system having means in the form of hardware, software, or a combination of software and hardware as described herein or their equivalent.