Solder fatigue arrest for wafer level package

A wafer level package includes a wafer, a lead disposed of the wafer for connecting the wafer to an electrical circuit, and a core disposed of the lead. In some embodiments, the lead disposed of the wafer is a copper pillar, and the core is plated onto the copper pillar. In some embodiments, the core is polymer screen-plated onto the lead. In some embodiments, the core extends between at least approximately thirty-five micrometers (35 μm) and fifty micrometers (50 μm) from the lead. In some embodiments, the core covers between at least approximately one-third (⅓) and one-half (½) of the surface area of the lead. In some embodiments, the core comprises a stud-shape extending from the lead. In some embodiments, the core extends perpendicularly across the lead. In some embodiments, the core extends longitudinally along the lead. Further, a portion of the core can extend perpendicularly from a longitudinal core.

BACKGROUND

An ever present objective of semiconductor assembly is to provide packages for enclosing/encasing semiconductor components that are smaller, thinner, cooler, and less expensive to manufacture at a high rate of production. One type of semiconductor package is the Plastic Dual In-line Package (PDIP). Another type of semiconductor package is the gull-wing Small Outline (SO) package. These semiconductor packages generally include leads (connectors) extending from the sides of the package. Other types of semiconductor packages are flat lead-less packages, such as Dual Flat No-leads (DFN) and Quad Flat No-leads (QFN) packages. A DFN package has lead lands on only two sides of the perimeter of the package bottom, while a QFN package has lead lands on four sides of the package bottom.

Some DFN and QFN package sizes can range from one millimeter (1 mm) by two millimeter (2 mm) packages having three (3) lead lands, to ten millimeter (10 mm) by ten millimeter (10 mm) packages having sixty-eight (68) lead lands. Because the lead-frame is on the bottom of the package, flat no-lead packages can provide superior thermal performance when compared to leaded packages having similar body size and lead counts. Further, in a flat no-leads configuration, the die-attach-pad can be exposed on the bottom exterior of the package, allowing it to be soldered directly to a printed circuit board, and providing a direct route for heat to dissipate away from the package. The exposed die-attach-pad, often referred to as an exposed thermal pad, may greatly improve heat transfer out of the integrated circuit package and into the printed circuit board.

SUMMARY

A wafer level package includes a wafer, a lead disposed of the wafer for connecting the wafer to an electrical circuit, and a core disposed of the lead. In some embodiments, the lead disposed of the wafer is a copper pillar, and the core is plated onto the copper pillar. In some embodiments, the core is polymer screen-plated onto the lead. In some embodiments, the core extends between at least approximately thirty-five micrometers (35 μm) and fifty micrometers (50 μm) from the lead. In some embodiments, the core covers between at least approximately one-third (⅓) and one-half (½) of the surface area of the lead. In some embodiments, the core comprises a stud-shape extending from the lead. In some embodiments, the core extends perpendicularly across the lead. In some embodiments, the core extends longitudinally along the lead. Further, a portion of the core can extend perpendicularly from a longitudinal core.

DETAILED DESCRIPTION

Overview

Flat no-leads Integrated Circuit (IC) packages, such as DFN (Dual Flat No-leads) packages and QFN (Quad Flat No-leads) packages, are used to physically and electrically connect ICs to printed circuit boards. The term “flat no-leads” is used to describe surface-mount technology allowing an IC to be connected to the surface of a Printed Circuit Board (PCB) without through-holes, and so on. Leadless connections/terminals (lead lands) and an exposed thermal pad are typically provided on the bottom of a flat no-leads IC package for connecting the package to a PCB. The lead lands are generally positioned at the perimeter of the package bottom, while the exposed thermal pad is located in the center of the package bottom, between the lead lands. Individual flat no-leads packages may be formed together, molded, and plated in a block format on a panel, and then singulated into separate devices after fabrication (e.g., by sawing or punching the packages out of the panel).

Oftentimes, wafer level packages fail board-level reliability testing as a result of solder fatigue. For example, during temperature cycling tests (TCT), components may become open at less than five hundred (500) cycles when solder joints completely crack. A temperature cycle test can be performed by cycling the temperature of the wafer level package between approximately minus forty degrees Celsius (−40° C.) and one hundred and twenty five degrees Celsius (125° C.). A cause of solder fatigue is thermal stress resulting from differences in the coefficients of thermal expansion (CTE) between a wafer level package and a printed circuit board (PCB). As shown inFIGS. 1A through 2, solder cracks50can occur on the package side of the connection between a wafer level package52and a PCB54during a temperature cycling test. As a result, a solder joint56is fractured near the package side, the crack50grows with progression of the TCT, and eventually the solder joint50is completely broken.

The present disclosure is directed to techniques and systems for reducing or preventing solder fatigue failure for flat lead-less wafer level packages (e.g., Dual Flat No-leads (DFN) packages, Quad Flat No-leads (QFN) packages, and so forth). For example, solder joint cracks are reduced or prevented for wafer level QFN (WL-QFN) packages during temperature cycle testing. These techniques can be used to increase the reliability and robustness of, for instance, chip scale packages (CSP) for power products. As described, a non-fatigue core (e.g., formed of copper and/or one or more other metals) is introduced proximate to a solder joint (e.g., inside a solder joint) and acts as a crack arrest to reduce or prevent crack propagation through the solder joint. In embodiments of the disclosure, when a solder crack propagates to the wall of a non-fatigue core, the crack is arrested there. In this manner, solder fatigue is prevented from opening the connection.

Example Implementations

Referring now toFIGS. 3 through 9, wafer level packages100including one or more cores (e.g., non-fatigue cores102) are described. The wafer level packages100can be implemented as WL-QFNs, QFNs, DFNs, and so forth. For example, in some embodiments, a wafer level package100is implemented as a power product CSP having one or more leads106configured to carry current and/or heat. In some embodiments, a wafer level package100is formed using a molding process, and the leads106comprise thick copper pillar bars. As shown, the non-fatigue cores102can be positioned proximate to a solder joint104(e.g., inside a solder joint). In some embodiments, a copper non-fatigue core102is plated onto a lead106of a wafer level package100. For example, a copper non-fatigue core102is plated onto a copper pillar lead106on a WL-QFN. In other embodiments, a polymer non-fatigue core102can be screen-plated onto a lead106, cured on a lead106, and so forth. As shown inFIGS. 4 and 7, metal (e.g., copper) studs102are plated onto the leads106of a WL-QFN. However, this configuration is provided by way of example only and is not meant to limit the present disclosure. In other embodiments, the non-fatigue cores102can have other shapes. For instance, inFIGS. 5 and 8, non-fatigue cores102are plated perpendicularly across the leads106of a WL-QFN100, and inFIGS. 6 and 9, non-fatigue cores102are plated longitudinally along the leads106of a WL-QFN100with non-fatigue cores102periodically extending perpendicularly from the longitudinal non-fatigue cores102along the length of the leads106. Further, other variously shaped non-fatigue cores102can be used in addition to those illustrated inFIGS. 3 through 9, including, but not necessarily limited to: serpentine-shaped non-fatigue cores, zigzag-shaped non-fatigue cores, arc-shaped non-fatigue cores, grid-shaped non-fatigue cores, and so forth.

In embodiments of the disclosure, after a wafer level package100is connected to a printed circuit board108, solder104is reflowed onto the leads106and surrounds the walls of the non-fatigue cores102. In this manner, a non-fatigue core102becomes the core of a solder joint104after board mounting. A non-fatigue core102acts as a crack arrest to reduce or prevent crack propagation110through the solder joint104. In some embodiments, the height of a non-fatigue core102with respect to a lead106of a wafer level package100ranges from between approximately thirty-five micrometers (35 μm) to approximately fifty micrometers (50 μm). However, this range is provided by way of example only and is not meant to limit the present disclosure. In other embodiments, a non-fatigue core102can be less than approximately thirty-five micrometers (35 μm) in height with respect to a lead106or greater than approximately fifty micrometers (50 μm) in height with respect to a lead106. Further, in some embodiments, the area of a lead106covered by non-fatigue core102ranges from between approximately one-third (⅓) to one-half (½) of the exposed surface area of the lead106. However, this range is provided by way of example only and is not meant to limit the present disclosure. In other embodiments, a non-fatigue core102can cover less than approximately one-third (⅓) of the exposed surface area of a lead106or greater than approximately one-half (½) of the exposed surface area of the lead106.

Example Process

Referring now toFIG. 10, example techniques are described for fabricating a wafer level package, where the wafer level package includes a connection with a non-fatigue core in accordance with example embodiments of the present disclosure.FIG. 10depicts a process1000, in example implementations, for fabricating a wafer level package, such as the wafer level packages100illustrated inFIGS. 3 through 9and described above.

In the process1000illustrated, a lead is formed on a wafer. The lead is configured to connect the wafer to an electrical circuit (Block1010). For example, with reference toFIGS. 3 through 9, wafer level packages100are configured as flat no-leads packages, with one or more leads106(e.g., die-attach-pads) exposed on the bottom exterior of the packages100. The leads106allow packages100to be soldered directly to printed circuit board108, providing a direct route for heat transfer between the packages100and the PCB108. In some embodiments, a lead is formed on a wafer by forming a copper pillar on the wafer (Block1012). For instance, with continuing reference toFIGS. 3 through 9, a copper pillar lead106is formed on a wafer of wafer level package100.

Then, a core is formed on the lead (Block1020). For example, with continuing reference toFIGS. 3 through 9, one or more non-fatigue cores102are formed on leads106. In some embodiments, the core is plated onto a copper pillar (Block1022). For instance, with continuing reference toFIGS. 3 through 9, one or more non-fatigue cores102are plated onto a lead106comprising a copper pillar. In some embodiments, the core comprises a polymer screen-plated onto the lead (Block1024). For example, with continuing reference toFIGS. 3 through 9, one or more non-fatigue cores102comprise a polymer material screen-plated onto one or more leads106. In some embodiments, the core covers between approximately one-third (⅓) and one-half (½) of the surface area of the lead (Block1026). For instance, with continuing reference toFIGS. 3 through 9, non-fatigue cores102cover between approximately one-third (⅓) and one-half (½) of the surface area of leads106.

CONCLUSION