Circuit for selecting row to be refreshed

A circuit for selecting a row of memory cells of a memory device to be refreshed may include: a cold table suitable for storing as a cold row a row selected as a hammered row when the row selected as the hammered row is neither one of cold rows stored in the cold table nor one of hot rows stored in a hot table; and the hot table suitable for storing, as a hot row, the row selected as the hammered row when the row selected as the hammered row is one of the cold rows stored in the cold table.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2017-0064168 filed on May 24, 2017, the disclosure of which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

Exemplary embodiments relate to a memory device.

DISCUSSION OF THE RELATED ART

With an increase in the degree of integration of memories, the distance between a plurality of word lines included in a memory is gradually reduced. As the distance between the word lines is reduced, a coupling effect between adjacent word lines is increased.

Each time data is inputted into or outputted from a memory cell, the corresponding word line toggles between an enabled state and a disabled state. As described above, as the coupling effect between adjacent word lines is increased, there is generated a phenomenon in which data of memory cells coupled to a word line adjacent to a word line that is frequently enabled is damaged. This phenomenon is called “row hammering”, which is problematic in that data of a memory cell is damaged by disturbance of the word line before the memory cell is refreshed.

FIG. 1is a diagram illustrating a portion of a cell array included in a memory device to describe a row hammering phenomenon.

InFIG. 1, ‘WLL’ denotes a word line that has been enabled a large number of times, and ‘WLL−1’ and ‘WLL+1’ respectively denote word lines disposed adjacent to ‘WLL’, in other words, word lines disposed adjacent to the word line that has been enabled a large number of times. Furthermore, ‘CL’ denotes a memory cell coupled to ‘WLL’, ‘CL−1’ denotes a memory cell coupled to ‘WLL−1’, and ‘CL+1’ denotes a memory cell coupled to ‘WLL+1’. Each of the memory cells includes a cell transistor TL, TL−1, TL+1 and a cell capacitor CAPL, CAPL−1, CAPL+1.

Referring toFIG. 1, when ‘WLL’ is enabled or disabled, the voltages of ‘WLL−1’ and ‘WLL+1’ are increased or reduced by a coupling phenomenon caused between ‘WLL’, ‘WLL−1’ and ‘WLL+1’, thus affecting the amount of electric charge of the cell capacitors CAPL−1 and CAPL+1. Therefore, if ‘WLL’ is frequently enabled and thus toggles between the enabled state and the disabled state, a change in the amount of charge stored in the cell capacitors CAPL−1 and CAPL+1 included in ‘CL−1’ and ‘CL+1’ is increased. Thereby, data in these memory cells may deteriorate.

Furthermore, electromagnetic waves generated when the word line toggles between the enabled state and the disabled state cause inflow or outflow of electrons into or from cell capacitors of memory cells coupled to adjacent word lines, thus causing damage to the data.

As a method for solving the row hammering phenomenon, a method of finding a row that has been enabled several times and refreshing rows adjacent to the several-times-enabled row is mainly used. As a method of finding a row that has been enabled several times, a method of counting the number of enabled times of every row enabled for a predetermined time is mainly used. However, in this case, there is a problem in that overhead is excessively increased.

SUMMARY

Various embodiments are directed to a circuit and method for more efficiently selecting rows to be refreshed for preventing data loss due to a row hammering phenomenon.

In an embodiment, a circuit for selecting a row of memory cells of a memory device to be refreshed may include: a cold table suitable for storing as a cold row a row selected as a hammered row when the row selected as the hammered row is neither one of cold rows stored in the cold table nor one of hot rows stored in a hot table; and the hot table suitable for storing, as a hot row, the row selected as the hammered row when the row selected as the hammered row is one of the cold rows stored in the cold table.

In an embodiment, when the row selected as the hammered row is one of the cold rows, the row selected as the hammered row may be removed from the cold table.

In an embodiment, a rank may be applied to the hot row stored in the hot table based on the number of times each hot row has been selected as the hammered row, a lowest rank may be applied to a new hot row stored in the hot table for the first time, and when the row selected as the hammered row is one of the hot rows, the rank of the row selected as the hammered row may be raised to the next rank level.

In an embodiment, ranks may be applied to the cold rows stored in the cold table, and a highest rank may be applied to a new cold row stored in the cold table for the first time.

In an embodiment, when the new hot row is stored in the hot table, an existing hot row of the lowest rank may be removed from the hot table and may be stored as the cold row of the highest rank in the cold table.

In an embodiment, when the new cold row is stored in the cold table, a cold row of the lowest rank of the cold table may be removed from the cold table if the cold table is in a full state.

In an embodiment, a row adjacent to an enabled row may be selected as the hammered row.

In an embodiment, a row adjacent to a row selected with a predetermined probability among enabled rows may be selected as the hammered row.

In an embodiment, eviction probabilities may be applied, by respective ranks, to the cold rows of the cold table. When the new cold row is stored in the cold table, one cold row selected based on the eviction probabilities among the cold rows of the cold table may be removed from the cold table if the cold table is in a full state.

In an embodiment, during a refresh operation of a memory device for preventing data loss due to row hammering, a row of the memory device corresponding to a hot row of a highest rank may be refreshed.

In an embodiment, when the hot row of the highest rank is not present, the refresh operation of the memory device for preventing the data loss due to the row hammering may not be performed.

In an embodiment, during a refresh operation of a memory device for preventing data loss due to row hammering, a row of the memory device corresponding to a hot row having a highest rank among the hot rows stored in the hot table may be refreshed.

In an embodiment, a memory controller for controlling a memory device may include: a circuit for selecting a row of memory cells of the memory device to be refreshed, comprising: a cold table suitable for storing as a cold row a row selected as a hammered row when the row selected as the hammered row is neither one of cold rows stored in the cold table nor one of hot rows stored in a hot table; and the hot table suitable for storing, as a hot row, the row selected as the hammered row when the row selected as the hammered row is one of the cold rows stored in the cold table.

In an embodiment, a memory device may include: a plurality of rows of memory cells; and a circuit for selecting a row of memory cells of the memory device to be refreshed, comprising: a cold table suitable for storing as a cold row a row selected as a hammered row when the row selected as the hammered row is neither one of cold rows stored in the cold table nor one of hot rows stored in a hot table; and the hot table suitable for storing, as a hot row, the row selected as the hammered row when the row selected as the hammered row is one of the cold rows stored in the cold table.

In an embodiment, a circuit for selecting a row to be refreshed may include: a cold table suitable for storing a plurality of cold rows having respective ranks; a hot table suitable for storing a plurality of hot rows having respective ranks; an input unit suitable for storing, as a cold row of a highest rank of the cold table, a row selected as a hammered row when the row selected as the hammered row is neither one of the cold rows nor one of the hot rows; a promotion unit suitable for storing, as a hot row of a lowest rank of the hot table, the row selected as the hammered row when the row selected as the hammered row is one of the cold rows, and raising the rank of the hammered row when the row selected as the hammer row is one of the hot rows; and an eviction unit suitable for removing one of the cold rows of the cold table if the cold table is in a full state when a new cold row is stored in the cold table.

In an embodiment, when the row selected as the hammered row is one of the cold rows, the promotion unit may remove the hammered row from the cold table.

In an embodiment, the input unit may select a row adjacent to an enabled row as the hammered row.

In an embodiment, the input unit may select, as the hammered row, a row adjacent to a row selected with a predetermined probability among enabled rows.

In an embodiment, during the removing, the eviction unit may remove a cold row of a lowest rank.

In an embodiment, eviction probabilities may be applied, by respective ranks, to the cold rows of the cold table, and, during the removing, the eviction unit may remove one cold row selected based on the eviction probabilities among the cold rows.

In an embodiment, during a refresh operation of a memory device for preventing data loss due to row hammering, a row of the memory device corresponding to a hot row of a highest rank may be refreshed.

In an embodiment, when the hot row of the highest rank is not present, the refresh operation of the memory device for preventing the data loss due to the row hammering may not be performed.

In an embodiment, during a refresh operation of a memory device for preventing data loss due to row hammering, a row of the memory device corresponding to a hot row having a highest rank among the hot rows stored in the hot table may be refreshed.

In an embodiment, a memory controller for controlling a memory device may include: a circuit for selecting a row to be refreshed, comprising: a cold table suitable for storing a plurality of cold rows having respective ranks; a hot table suitable for storing a plurality of hot rows having respective ranks; an input unit suitable for storing, as a cold row of a highest rank of the cold table, a row selected as a hammered row when the row selected as the hammered row is neither one of the cold rows nor one of the hot rows; a promotion unit suitable for storing, as a hot row of a lowest rank of the hot table, the row selected as the hammered row when the row selected as the hammered row is one of the cold rows, and raising the rank of the hammered row when the row selected as the hammer row is one of the hot rows; and an eviction unit suitable for removing one of the cold rows of the cold table if the cold table is in a full state when a new cold row is stored in the cold table.

In an embodiment, a memory device may include: a plurality of rows of memory cells; and a circuit for selecting a row to be refreshed, comprising: a cold table suitable for storing a plurality of cold rows having respective ranks; a hot table suitable for storing a plurality of hot rows having respective ranks; an input unit suitable for storing, as a cold row of a highest rank of the cold table, a row selected as a hammered row when the row selected as the hammered row is neither one of the cold rows nor one of the hot rows; a promotion unit suitable for storing, as a hot row of a lowest rank of the hot table, the row selected as the hammered row when the row selected as the hammered row is one of the cold rows, and raising the rank of the hammered row when the row selected as the hammer row is one of the hot rows; and an eviction unit suitable for removing one of the cold rows of the cold table if the cold table is in a full state when a new cold row is stored in the cold table.

DETAILED DESCRIPTION

FIG. 2is a diagram illustrating a configuration of a memory system200in accordance with an embodiment.

Referring toFIG. 2, the memory system200may include a memory controller210and a memory device220.

The memory controller210may control an operation of operation of the memory device220in response to a request from a HOST. Examples of suitable host devices may include a central processing unit (CPU), a graphic processing unit (GPU), an application processor (AP), and the like. The memory controller210may include a host interface211, a scheduler212, a command generator213, a target row selecting circuit214for selecting a row to be refreshed, and a memory interface215.

The host interface211may provide an interface between the memory controller210and the host HOST. Requests of the host HOST may be received through the host interface211, and results of processing the requests may be transmitted to the host HOST through the host interface211.

The scheduler212may determine for a plurality of requests received from the host HOST, a sequence according to which the requests are to be applied to the memory device220. The scheduler212may select the sequence for enhancing the performance of the memory device220and thereby of the overall memory system. Hence, the scheduler determines the sequence according to which the operations corresponding to the received requests differ from the sequence of the requests received from the host HOST. Hence, the scheduler can determine a sequence of operations to be provided as instructions to the memory device220that differs from the sequence at which corresponding requests were received by the memory controller so that the performance of the memory device220may be enhanced. For example, even if the host HOST requests a read operation of the memory device220before requesting a write operation of the memory device220, the sequence of requests may be adjusted such that the write operation is performed earlier than the read operation in order to optimize the operation of the memory device220

The scheduler212may schedule refresh operations to be performed during intervals of the operations requested from the host HOST so as to prevent data of the memory device220from being lost. Each time a refresh command is applied from the memory controller210to the memory device220by scheduling of the scheduler212, the memory device220may sequentially enable internal rows (i.e., word lines).

The scheduler212may schedule not only a general refresh operation but also an additional refresh operation for preventing data being lost by row hammering. The additional refresh operation may be performed by enabling a row having a high possibility of data loss attributable to the row hammering to be refreshed earlier, rather than sequentially refreshing the rows of the memory device220. That is, during the additional refresh operation, an active command and an address of a row having a high possibility of data loss due to the row hammering may be applied from the memory controller210to the memory device220. The row having a high possibility of data loss due to the row hammering may be selected by the target row selecting circuit214. In an embodiment, the scheduler212may periodically schedule the additional refresh operation. For example, the additional refresh operation may be performed once each time the refresh operation is performed ten times. Alternatively, the additional refresh operation may be performed once each time the refresh operation is performed a hundred times.

The target row selecting circuit214may monitor an active command and an address to be applied from the memory controller210to the memory device220, select a row having a high possibility of data loss due to row hammering, and provide information of the selected row to the scheduler212so that an additional refresh operation on the row having a high possibility of data loss due to row hammering may be performed.

The command generator213may generate a command to be applied to the memory device220according to the sequence of operations determined by the scheduler212.

The memory interface215may provide an interface between the memory controller210and the memory device220. A command CMD and an address ADD may be transmitted from the memory controller210to the memory device220through the memory interface215, and data DATA may be exchanged therebetween through the memory interface215. The memory interface215may also be called a PHY interface.

The memory device220may perform an operation instructed by the memory controller210. The memory device220may be a memory device220that needs a refresh operation. For example, the memory device220may be a dynamic random access memory (DRAM) or may be another kind of memory device that requires a refresh operation.

FIG. 3is a diagram illustrating a configuration of an embodiment of the target row selecting circuit214.

Referring toFIG. 3, the target row selecting circuit214may include a cold table311, a hot table312, an input unit320, a promotion unit330, and an eviction unit340.

The cold table311may store a plurality of cold rows. The cold rows may refer to rows that have been stored neither in the cold table311nor the hot table312among rows selected as hammered rows. Ranks may be applied to the cold rows stored in the cold table311.

The hot table312may store a plurality of hot rows. The hot rows may refer to rows that have been stored in the cold table311or the hot table312among the rows selected as the hammered rows. Ranks may be applied to the hot rows stored in the hot table312. During an additional refresh operation, one of the hot rows may be refreshed. With regard to this, one of two methods including (1) and (2) may be used. In method (1), during the additional refresh operation, a hot row of a highest rank of the hot table312, i.e., a hot row of rank0, may be an additional refresh target. If the highest rank of the hot table312is empty, in other words, if rank0is empty, the additional refresh operation may not be performed. In method (2), during the additional refresh operation, a hot row of a highest rank among the hot rows of the hot table312may be an additional refresh target. For instance, if rank0is empty and a hot row of rank1is present, an additional refresh operation on the hot row of rank1may be performed. In the case where there is no hot row in the hot table312, an additional refresh operation may not be performed.

The input unit320may select a hammered row and insert information of the selected hammered row into the cold table311. One of two methods including (A) and (B) may be used as a method of selecting the hammered row by the input unit320. In method (A), the input unit320may select all rows adjacent to an enabled row as hammered rows. For example, if row3is enabled, row2may be selected as a hammered row, and row4may be selected as a hammered row. In method (B), the input unit320may select, as hammered rows, only rows randomly selected from among rows adjacent to an enabled row. For example, among the rows adjacent to the enabled row, only a row selected with a probability of 10% may be selected as a hammered row. In detail, when row3is enabled, if row3is selected with the probability of 10%, row2and row4that are rows adjacent to row3may be selected as hammered rows. If row3is not selected with the probability of 10%, row2and row4may not be selected as hammered rows. Here, the operation of selecting enabled row3with the probability of 10% may be performed, e.g., by a method in which a random number of numbers from 1 to 100 is generated by a random number generator and if the generated random number is within a range from 1 to 10, it is determined that the third row has been selected with the probability of 10%, and if not, it is determined that the third row has been unselected with the probability of 10%. The phenomenon of data loss due to the row hammering is generated when a certain row is enabled one thousand or more times for a short period of time. Therefore, even if only 10% of rows adjacent to the enabled row are selected as hammered rows, there is no problem with determining a row having a probability of data loss. Compared to the case, e.g., method (A), where all of the rows adjacent to the enabled rows are selected as hammered rows, in the case, e.g., method (B), where rows adjacent to a row randomly selected from among the enabled rows are selected as hammered rows, the sizes of the cold table and the hot table may be reduced.

In the case where a selected hammered row is a row that is stored neither in the cold table311nor in the hot table312, the input unit320may store the selected hammered row as a cold row in a highest rank, i.e., rank0, of the cold table311. In this case, the rank of each of the cold rows that have been already stored in the cold table311may be lowered by one level.

In the case where a hammered row selected by the input unit320is one of cold rows that have been stored in the cold table311, the promotion unit330may remove the corresponding row from the cold table311and promote it as a hot row of a lowest rank of the hot table312. In this case, an existing hot row that has been in the lowest rank of the hot table312may be transmitted to the highest rank of the cold table311.

In the case where a hammered row selected by the input unit320is one of the hot rows that haven been stored in the hot table312, the promotion unit330may raise the rank of the corresponding hot row by one level. As the rank of the hot row is raised by one level, the rank of a hot row that has been in a one-level higher rank may be lowered by one level. For example, if a hot row of rank2is raised to rank1, an existing hot row of rank1may be lowered to rank2.

The eviction unit340may remove, among the hot rows of the hot table312, a hot row, on which the additional refresh operation has been performed, from the hot table312. In the case where a new cold row is stored in the cold table311, the eviction unit340may remove one of the cold rows from the cold table311if the cold table311is in a full state. As a method of removing one of the cold rows from the cold table311by the eviction unit340, one of two methods including (I) and (II) may be used. In method (I), when a new cold row is stored in the cold table311, the eviction unit340may remove a cold row of the lowest rank from the cold table311if the cold table311is in a full state. In method (II), when a new cold row is stored in the cold table311, the eviction unit340may remove one cold row based on eviction probabilities given by ranks of cold rows. For example, in the case where four cold rows having ranks0to3are present in the cold table311, eviction probabilities of 10%, 20%, 20%, and 50% may be respectively given thereto, and one cold row selected based on these eviction probabilities may be removed. Here, the operation of selecting one cold row based on the eviction probabilities may be performed by a method including generating a random number of numbers from 1 to 100, removing a cold row of rank0if the generated random number ranges from 1 to 10 corresponding to the eviction probability of 10%, removing a cold row of rank1if the generated random number ranges from 11 to 30 corresponding to the eviction probability of 20%, removing a cold row of rank2if the generated random number ranges from 31 to 50 corresponding to the eviction probability of 20%, and removing a cold row of rank3if the generated random number ranges from 51 to 100 corresponding to the eviction probability of 50%. The use of a method such as method (II) by the eviction unit340is to give slight unexpectedness to the method of selecting a row to be refreshed.

The target row selecting circuit214may select a row having a high possibility of data loss due to row hammering, based on a history of an enabled row, using simple configuration and method.

FIG. 4is a diagram describing the operation of the target row selecting circuit214. For the sake of convenience in explanation, there will be described an example in which method (1) is used as a method of refreshing one of hot rows of the hot table312, method (A) is used as a method of selecting a hammered row by the input unit320, and method (I) is used as a method of removing a cold row by the eviction unit340. Furthermore, there will be described an example in which the cold table311stores four cold rows, and the hot table312stores three hot rows. In addition, there will be described an example in which there are 256 rows from row0to row255.

Referring toFIG. 4, in a state in which the hot table312and the cold table311are recorded as shown in (a), row11may be enabled. When row11is enabled, row10and row12that are adjacent to row11may be selected as hammered rows. Because row10is already stored as a hot row in the hot table312, the rank of row10is raised from1to0, so that the hot table312and the cold table311enter a state of (b). Because row12is in a state in which it is recorded neither in the hot table312nor in the cold table311, row12enters rank0that is the highest rank of the cold table311, row107and row4are lowered in rank, and row89is removed from the cold table311. As a result, the hot table312and the cold table311enter a state of (c).

If an additional refresh operation is performed when the hot table312and the cold table311are in the state of (c), the additional refresh operation may be performed to row10in rank0of the hot table312. In other words, the additional refresh operation may be performed to row10in the memory device220. After the additional refresh operation has been performed, row10is removed from the hot table312, so that the hot table312and the cold table311may enter a state of (d).

While the hot table312and the cold table311are in the state of (d), row25may be enabled. When row25is enabled, row24and row26that are adjacent to row25may be selected as hammered rows. Because row24is already stored in the cold table311, row24may be moved to rank2that is the lowest rank of the hot table312. Row216that has been in rank2of the hot table312may be moved to rank0of the cold table. Thereby, the hot table312and the cold table311may enter a state of (e). Because row26has been present neither in the hot table312nor in the cold table311, row26is stored in rank0of the cold table311. As a result, the hot table312and the cold table311may enter a state of (f).

While the hot table312and the cold table311are in the state of (f), row0may be enabled. When row0is enabled, row1that is adjacent to row0may be selected as a hammered row. Because row1is already stored in the hot table312, the rank of row1is raised from1to0, so that the hot table311and the cold table311enter a state of (g).

While the hot table312and the cold table311are in the state of (g), row25may be enabled. When row25is enabled, row24and row26that are adjacent to row25may be selected as hammered rows. Because row24is already stored in the hot table312, the rank of row24is raised from2to1, so that the hot table311and the cold table311may enter a state of (h). Since row26is already present in the cold table311, row26is moved to rank3of the hot table312and removed from the cold table311. Thus, the hot table and the cold table may enter a state of (i).

While the hot table312and the cold table311are in the state of (i), row255may be enabled. When row255is enabled, row254that is adjacent to row255may be selected as a hammered row. Because row254has been present neither in the hot table312nor in the cold table311, row254is stored in rank0of the cold table311. As a result, the hot table312and the cold table311may enter a state of (j).

Referring toFIG. 4, it may be understood that rows adjacent to a row enabled several times are stored in higher ranks in the hot table312, and rows adjacent to the enabled row after a long time has passed after it has been enabled are gradually lowered in ranks and eventually removed from the cold table311.

FIG. 5is a diagram illustrating a configuration of a memory system500in accordance with another embodiment.

Referring toFIG. 5, the memory system500may include a memory controller510and a memory device520. In the memory system500ofFIG. 5, a target row selecting circuit522for selecting a row to be refreshed may be included in the memory device520rather than in the memory controller510.

The memory controller510may control an operation of the memory device520in response to a request from a HOST. Examples of the host HOST may include a central processing unit (CPU), a graphic processing unit (GPU), an application processor (AP), etc. The memory controller510may include a host interface511, a scheduler512, a command generator513, and a memory interface515.

The host interface511may be provided for interface between the memory controller510and the host HOST. Requests of the host HOST may be received through the host interface511, and results of processing the requests may be transmitted to the host HOST through the host interface511.

The scheduler512may determine, among requests from the host HOST, a sequence of requests to be applied to the memory device520. The scheduler512may make a sequence of requests received from the host HOST and a sequence of operations to be provided as instructions to the memory device520differ from each other to enhance the performance of the memory device520. For example, even if the host HOST requests a read operation of the memory device520before requesting a write operation of the memory device520, the sequence of requests may be adjusted such that the write operation is performed earlier than the read operation.

The scheduler512may schedule refresh operations in intervals of the operations requested from the host HOST so as to prevent data of the memory device520from being lost. Each time a refresh command is applied from the memory controller510to the memory device520by scheduling of the scheduler510, the memory device520may sequentially enable internal rows (i.e., word lines).

The scheduler512may schedule not only a general refresh operation but also an additional refresh operation for preventing data being lost by row hammering. In the embodiment ofFIG. 5, since the target row selecting circuit522for selecting a row on which an additional refresh operation is to be performed is included in the memory device520, the memory controller510may instruct the memory device520to perform the additional refresh operation by applying an additional refresh command to the memory device520. The scheduler512may periodically schedule the additional refresh operation. For example, the additional refresh operation may be performed once each time the refresh operation is performed ten times. Alternatively, the additional refresh operation may be performed once each time the refresh operation is performed a hundred times.

The command generator513may generate a command to be applied to the memory device520according to the sequence of operations determined by the scheduler512.

The memory interface515may be provided for interface between the memory controller510and the memory device520. A command CMD and an address ADD may be transmitted from the memory controller510to the memory device520through the memory interface515, and data DATA may be exchanged therebetween through the memory interface515. The memory interface515may also be called a PHY interface.

The memory device520may perform an operation instructed by the memory controller510. The memory device520may include a command decoder521, the target row selecting circuit522, an address counter523, and a memory array524.

The command decoder521may generate internal command signals ACT, PCG, RD, WT, REF, and ADD_REF by decoding a command CMD transmitted from the memory controller510. The internal command signals may include an active signal ACT, a precharge signal PCG, a read signal RF, a write signal WT, a refresh signal REF, an additional refresh signal ADD_REF, and so forth.

The target row selecting circuit522may use an address ADD and an active signal ACT transmitted to the memory array524and select rows adjacent to a row enabled several times, i.e., rows on which an additional refresh operation should be performed. The target row selecting circuit522may have the same configuration and operation as those of the target row selecting circuit214described with reference toFIGS. 3 and 4. An additional refresh address ADD_REF_ADD to be outputted from the target row selecting circuit522is an address indicating a row on which the additional refresh operation should be performed, and may be an address indicating a row of the highest rank of the hot table312.

The address counter523may change the refresh address REF_ADD each time the refresh signal REF is enabled. The refresh address REF_ADD generated from the address counter523may be used during the normal refresh operation rather than during the additional refresh operation.

The memory array524may perform operations indicated by the internal command signals ACT, PCG, RD, WT, REF, and ADD_REF. During the additional refresh operation during which the additional refresh signal ADD_REF is enabled, the memory array524may perform a refresh operation on a row selected by the additional refresh address ADD_REF_ADD. Furthermore, during the refresh operation during which the refresh signal REF is enabled, the memory array524may perform a refresh operation on a row selected by the refresh address REF_ADD. In addition, during an active, read, or write operation of the memory array524, an address ADD transmitted from the memory controller510may be used. The memory array524may include elements such as a cell array, a row circuit for enabling/disabling rows of the cell array, and a column circuit for inputting/outputting data into/from the cell array, to perform operations such as active, precharge, read, write, refresh, and additional refresh operations.

In the embodiment ofFIG. 2, there has been illustrated the case where the target row selecting circuit214is included in the memory controller210, and in the embodiment ofFIG. 5, there has been illustrated the case where the target row selecting circuit522is included in the memory device520. However, these embodiments are only for illustrative purposes, and the target row selecting circuit may be disposed in other portions neither in the memory device nor in the memory controller. For example, the target row selecting circuit may be formed of a separate chip and disposed between the memory device and the memory controller.

In accordance with various embodiments, rows needed to be refreshed due to a row hammering phenomenon may be efficiently selected.