Organic light emitting diode display device

An organic light emitting diode display device includes a substrate, a driving transistor, and a sub-pixel structure. The substrate has a first trench. The driving transistor is inside the first trench of the substrate. The sub-pixel structure is on the driving transistor.

CROSS-REFERENCE TO RELATED APPLICATION

Korean Patent Application No. 10-2018-0019566, filed on Feb. 19, 2018, in the Korean Intellectual Property Office, and entitled: “Organic Light Emitting Diode Display Device,” is incorporated by reference herein in its entirety.

BACKGROUND

Example embodiments relate generally to an organic light emitting diode display device. More particularly, embodiments relate to a flexible organic light emitting diode display device.

2. Description of the Related Art

A flat panel display (“FPD”) device is widely used as a display device of an electronic device because the FPD device is lightweight and thin compared to a cathode-ray tube (“CRT”) display device. Typical examples of the FPD device are a liquid crystal display (“LCD”) device and an organic light emitting diode (“OLED”) display device.

The OLED display device may include a plurality of transistors (e.g., driving transistors and switching transistors), a plurality of capacitors, a plurality of wirings (e.g., scan signal wirings, data signal wirings, emission signal wirings, initialization signal wirings, power supply voltage wirings, etc.), a plurality of sub-pixel structures, etc, and a flexible OLED display device capable of bending or folding a portion of the OLED display device including lower and upper substrates having flexible materials may have been developed.

SUMMARY

According to some example embodiments, an OLED display device includes a substrate, a driving transistor, and a sub-pixel structure. The substrate has a first trench. The driving transistor is inside the first trench of the substrate. The sub-pixel structure is on the driving transistor.

In example embodiments, a width of the first trench may be greater than a width of the driving transistor.

In example embodiments, the OLED display device may further include a first lower block pattern under the driving transistor, and the first lower block pattern may be buried in the internal substrate.

In example embodiments, the OLED display device may further include a first switching transistor on the substrate, and the driving transistor may be at a lower level than the first switching transistor.

In example embodiments, the substrate may include a first organic film layer, a first barrier layer on the first organic film layer, a second organic film layer on the first barrier layer and having a first opening under the driving transistor, and a second barrier layer on the second organic film layer.

In example embodiments, the first trench of the substrate may be defined by the first opening of the second organic film layer.

In example embodiments, the second barrier layer may be in the first opening of the second organic film layer.

In example embodiments, the OLED display device may further include a first switching transistor on the substrate. The driving transistor may be at a lower level than the first switching transistor, and the first and second organic film layers of the substrate may be under the driving transistor.

In example embodiments, the OLED display device may further include a second switching transistor inside the first trench, and the second switching transistor may be spaced apart from the driving transistor.

In example embodiments, the OLED display device may further include a first lower block pattern and a second lower block pattern. The first lower block pattern may be inside the first trench under the driving transistor and between the first barrier layer and the second barrier layer. The second lower block pattern may be inside the first trench under the second transistor and between the first barrier layer and the second barrier layer.

In example embodiments, the first organic film layer may further include a first groove under the driving transistor.

In example embodiments, the first barrier layer may be in the first groove.

In example embodiments, the first trench of the substrate may be defined by the first groove of the first organic film layer and the first opening of the second organic film layer.

In example embodiments, the OLED display device may further include a first switching transistor and a first lower block pattern. The first switching transistor may be on the substrate at a higher level than the driving transistor. The first lower block pattern may be under the driving transistor and between the first barrier layer and the second barrier layer.

In example embodiments, the first organic film layer may further include a second groove spaced apart from the first groove in a first direction and a third groove spaced apart from the first groove in a second direction that is different from the first direction.

In example embodiments, the second organic film layer may further include a second opening that overlaps the second groove and a third opening that overlaps to the third groove, and the first barrier layer may be in the second and third grooves.

In example embodiments, a second trench of the substrate may be defined by the second groove of the first organic film layer and the second opening of the second organic film layer, and the third trench of the substrate may be defined by the third groove of the first organic film layer and the third opening of the second organic film layer.

In example embodiments, the OLED display device may further include a first signal wiring on the second trench and a second signal wiring the third trench, and a voltage level of the first signal may be less than a voltage level of the second signal wiring.

In example embodiments, the first organic film layer including the first, second, third grooves may be only under the driving transistor, the first signal wiring, and the second signal wiring.

In example embodiments, the OLED display device may further include a thin film encapsulation structure on the sub-pixel structure, and the substrate and the thin film encapsulation structure have flexibility.

DETAILED DESCRIPTION

FIG. 1is a plan view illustrating an organic light emitting diode (“OLED”) display device in accordance with example embodiments.FIG. 2is a plan view for describing a trench included in the OLED display device ofFIG. 1.

Referring toFIGS. 1 and 2, an OLED display device100may have a display region50including a plurality of sub-pixel regions10. Here, the sub-pixel regions10may be arranged in the entire display region50along first and second directions D1and D2. Here, the first direction D1may be perpendicular to the second direction D2, and both the first direction D and the second direction D2may be parallel to an upper surface of the OLED display device100.

Sub-pixel structures (e.g., a sub-pixel structure200ofFIG. 3) may be in the sub-pixel regions10, respectively. Wirings may be in a remaining portion of the display region50except for the sub-pixel regions10. For example, the wirings may include data signal wirings, scan signal wirings, emission signal wirings, initialization signal wirings, power supply voltage wirings, etc. Alternatively, the wirings may overlap the sub-pixel region10.

In addition, at least one driving transistor250and at least one first switching transistor255may be in each of the sub-pixel regions10. In example embodiments, a first trench305may be formed in each of the sub-pixel regions10, and the driving transistor250may be inside the first trench305. For example, as illustrated inFIG. 2, the driving transistor250may be inside of the first trench305in the sub-pixel region10, and a shape of the first trench305may be formed along an outer profile of the driving transistor250.

In example embodiments, a shape of each of the sub-pixel regions10, the display region50, the driving transistor250, the first switching transistor255, and the first trench305have a plan shape of a tetragon. Alternatively, a shape of each of the sub-pixel regions10, the display region50, the driving transistor250, the first switching transistor255, and the first trench305may have a plan shape of, e.g., a triangle, a diamond, a polygon, a circle, an athletic track, an elliptic, etc.

The first trench305in the sub-pixel region10may be formed by removing a second organic film layer of a substrate, which will be described below. As the second organic film layer under the driving transistor250is removed, electric charges included in the second organic film layers that may interfere with a drive of the driving transistor250maybe reduced. In example embodiments, as the OLED display device100includes the driving transistor250in the first trench305, a threshold voltage of the driving transistor250may not be changed by the electric charges. Accordingly, reliability of the driving transistor250may be relatively improved, and rapid deterioration of the driving transistor250due to the change of the threshold voltage may be reduced or prevented.

FIG. 3is a cross-sectional view taken along a line I-I′ ofFIG. 1. Referring toFIG. 3, the OLED display device100may include a substrate110, a buffer layer115, a gate insulation layer150, an insulating interlayer190, the driving transistor250, the first switching transistor255, the first trench305, a planarization layer270, a pixel defining layer310, a sub-pixel structure200, a thin film encapsulation (“TFE”) structure450, etc.

The driving transistor250may include a first active layer130, a first gate electrode170, a first source electrode210, and a first drain electrode230. The first switching transistor255may include a second active layer135, a second gate electrode175, a second source electrode215, and a second drain electrode235. The sub-pixel structure200may include a lower electrode290, a light emitting layer330, and an upper electrode340. The TFE structure450may include a first TFE layer451, a second TFE layer452, and a third TFE layer453. The substrate110may include a first organic film layer111, a first barrier layer112, a second organic film layer113, and a second barrier layer114. The second organic film layer113may have a first opening101that overlaps the driving transistor250along a third direction D3, perpendicular to the first and second directions D1and D2. In example embodiments, the first trench305of the substrate110may be defined by the first opening101of the second organic film layer113.

The substrate110may include transparent or opaque insulation materials. The substrate110may include a flexible transparent resin substrate. As described above, the substrate110may have the first organic film layer111, the first barrier layer112, the second organic film layer113, and the second barrier layer114are sequentially stacked along the third direction D3. The second organic film layer113may have the first opening101exposing an upper surface of the first barrier layer112. For example, the first barrier layer112may be on an entirety of the first organic film layer111, and the second organic film layer113having the first opening101may be on the first barrier layer112. In addition, the second barrier layer114may fill the first opening101of the second organic film layer113, and may be on an entirety of the second organic film layer113.

Each of the first barrier layer112and the second barrier layer114may include inorganic materials, e.g., a silicon compound, a metal oxide, etc. For example, each of the first barrier layer112and the second barrier layer114may include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), silicon oxycarbide (SiOxCy), silicon carbon nitride (SiCxNy), aluminum oxide (AlOx), aluminum nitride (AlNx), tantalum oxide (TaOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), titanium oxide (TiOx), etc. In addition, each of the first organic film layer111and the second organic film layer113may include polyimide, epoxy-based resin, acryl-based resin, polyester, photoresist, polyacryl-based resin, polyimide-based resin, a polyamide-based resin, a siloxane-based resin, etc.

In example embodiments, the first and second barrier layers112and114each may include SiOx, and may block moisture or water that is permeated through the first and second organic film layers111and113. Further, the first and second organic film layers111and113each may include a polyamide-based resin such that the OLED display device100has flexibility, and the polyimide-based resin may be random copolymer or block copolymer. The polyimide-based resin may have a high transparency, a low coefficient of thermal expansion, and a high glass transition temperature. Since the polyimide-based resin includes an imide radical, heat resistance, chemical resistance, durability, and an electrical characteristics thereof may be excellent.

Since the substrate110is relatively thin and flexible, the substrate110may be on a rigid glass substrate to help support the formation of the driving transistor250, the first switching transistor255, the sub-pixel structure200, and the TFE structure450. In a manufacturing the OLED display device100, after the buffer layer115is formed on the second barrier layer114, the driving transistor250, the first switching transistor255, the sub-pixel structure200, and the TFE structure450may be formed on the buffer layer115. After the driving transistor250, the first switching transistor255, the sub-pixel structure200, and the TFE structure450are formed on the buffer layer115, the rigid glass substrate on which the substrate110may be removed.

Formation of the driving transistor250, the first switching transistor255, the sub-pixel structure200, and the TFE structure450on the substrate110may be difficult when the substrate110is relatively thin and flexible. Accordingly, the driving transistor250, the first switching transistor255, the sub-pixel structure200, and the TFE structure450may be formed on the substrate110and the rigid glass substrate, and then the substrate110including the first organic film layer111, the first barrier layer112, the second organic film layer113, and the second barrier layer114may serve as the substrate110of the OLED display device100after removal of the rigid glass substrate. Alternatively, the substrate110may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluoride-doped quartz substrate, a sodalime glass substrate, a non-alkali glass substrate etc.

In example embodiments, the substrate110includes four-layers. Alternatively, in some example embodiments, the substrate110may include a single layer or a plurality of layers.

The buffer layer115may be on the substrate110. In example embodiments, the buffer layer115may fill the first trench305, and may be on an entirety of the second barrier layer114. The buffer layer115may have a substantially uniform thickness along the third direction D3along a profile of the second barrier layer114on the second barrier layer114. For example, the buffer layer115may include organic materials or inorganic materials. In example embodiments, the buffer layer115may include inorganic materials.

The buffer layer115may prevent the diffusion of metal atoms and/or impurities from the substrate110into the driving transistor250, the first switching transistor255, and the sub-pixel structure200. In addition, the buffer layer115may control a rate of a heat transfer in a crystallization process for forming the first active layer130and the second active layer135, thereby obtaining substantially uniform active layers. Further, the buffer layer115may improve a surface flatness of the substrate110when a surface of the substrate110is relatively irregular. According to a type of the substrate110, at least two buffer layers may be provided on the substrate110or the buffer layer may not be present.

The first active layer130and the second active layer135may be on the buffer layer115. The first active layer130and the second active layer135may be spaced apart from each other along the first direction D1. The first active layer130and the second active layer135may have a same thickness along the third direction D3. In example embodiments, the first active layer130may be inside the trench305, and the second active layer135may be outside the trench305. The first active layer130and the second active layer135may be on a same layer (e.g., on the buffer layer115), but the first active layer130may be in a relatively lower level along the third direction D3than the second active layer135due to the first trench305.

Each of the first and second active layers130and135may include an oxide semiconductor, an inorganic semiconductor (e.g., amorphous silicon, polysilicon, etc.), an organic semiconductor, etc. For example, the first active layer130and the second active layer135may be simultaneously formed using same materials.

The gate insulation layer150may be on the first and second active layers130and135, and the buffer layer115. The gate insulation layer150may cover the first and second active layers130and135on the buffer layer115, and may be on an entirety of the buffer layer115. For example, the gate insulation layer150may cover the first and second active layers130and135on the buffer layer115, and may have a substantially uniform thickness along the third direction D3along a profile of the first and second active layers130and135. Alternatively, the gate insulation layer150may sufficiently cover the first and second active layers130and135on the buffer layer115, to have a substantially flat upper surface without a step around the first and second active layers130and135. The gate insulation layer150may include, e.g., a silicon compound, a metal oxide, etc.

The first gate electrode170and the second gate electrode175may be on the gate insulation layer150, and may be spaced apart from each other along the first direction D1. In example embodiments, the first gate electrode170may be inside the trench305, and the second gate electrode175may be outside the trench305. In other words, the first gate electrode170may be on a portion of the gate insulation layer150over the first active layer130, and the second gate electrode175may be on a portion of the gate insulation layer150over the second active layer135. The first gate electrode170and the second gate electrode175may be on a same layer (e.g., on the gate insulation layer150), but the first gate electrode170may be at a relatively lower level along the third direction D3than the second gate electrode175due to the first trench305.

Each of the first and second gate electrodes170and175may include a metal, a metal alloy, metal nitride, conductive metal oxide, transparent conductive materials, etc. For example, each of the first and second gate electrodes170and175may include gold (Au), silver (Ag), aluminum (Al), tungsten (W), copper (Cu), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chrome (Cr), tantalum (Ta), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), an alloy of aluminum, aluminum nitride (AlNx), an alloy of silver, tungsten nitride (WNx), an alloy of copper, an alloy of molybdenum, titanium nitride (TiNx), chrome nitride (CrNx), tantalum nitride (TaNx), strontium ruthenium oxide (SRO), zinc oxide (ZnOx), indium tin oxide (ITO), stannum oxide (SnOx), indium oxide (InOx), gallium oxide (GaOx), indium zinc oxide (IZO), etc. These may be used alone or in a suitable combination thereof. Alternatively, each of the first and second gate electrodes170and175may have a multi-layered structure including a plurality of layers. For example, the first gate electrode170and the second gate electrode175may be simultaneously formed using same materials.

The insulating interlayer190may be on the first and second gate electrodes170and175, and the gate insulation layer150. The insulating interlayer190may cover the first and second gate electrodes170and175on the gate insulation layer150, and may be on an entirety of the gate insulation layer150. For example, the insulating interlayer190may cover the first and second gate electrodes170and175on the gate insulation layer150, and may have a substantially uniform thickness along the third direction D3along a profile of the first and second gate electrodes170and175. Alternatively, the insulating interlayer190may sufficiently cover the first and second gate electrodes170and175on the gate insulation layer150, to have a substantially flat upper surface without a step around the first and second gate electrodes170and175. The insulating interlayer190may include silicon compound, metal oxide, etc.

The first source electrode210, the first drain electrode230, the second source electrode215, and the second drain electrode235may be on the insulating interlayer190. In example embodiments, the first source electrode210and the first drain electrode230may be inside the trench305, and the second source electrode215and the second drain electrode235may be outside the trench305. The first source electrode210may be in contact with a source region of the first active layer130via a contact hole in a first portion of the gate insulation layer150and the insulating interlayer190. The first drain electrode230may be in contact with a drain region of the first active layer130via a contact hole in a second portion of the gate insulation layer150and the insulating interlayer190. In addition, the second source electrode215may be in contact with a source region of the second active layer135via a contact hole in a third portion of the gate insulation layer150and the insulating interlayer190, and the second drain electrode235may be in contact with a drain region of the second active layer135via a contact hole in fourth portion of the gate insulation layer150and the insulating interlayer190. The first and second source electrodes210and215and the first and second drain electrodes230and235may be on a same layer (e.g., on the insulating interlayer190), but the first and second source electrodes210and215may be at a relatively lower level along the third direction D3than the first and second drain electrodes230and235due to the first trench305.

Each of the first and second source electrodes210and215and the first and second drain electrodes230and235may include a metal, an alloy, metal nitride, conductive metal oxide, transparent conductive materials, etc. These may be used alone or in a suitable combination thereof. Alternatively, each of the first and second source electrodes210and215and the first and second drain electrodes230and235may have a multi-layered structure including a plurality of layers. For example, the first and second source electrodes210and215and the first and second drain electrodes230and235may be simultaneously formed using same materials. Accordingly, the driving transistor250including the first active layer130, the first gate electrode170, the first source electrode210, and the first drain electrode230may be constituted, and the first switching transistor255including the second active layer135, the second gate electrode175, the second source electrode215, and the second drain electrode235may be constituted.

In example embodiments, the driving transistor250may be inside the first trench305and, along the first direction, a width of the first trench305may be greater than a width of the driving transistor250. In other words, the first trench305may overlap, e.g., completely overlap, the driving transistor250along the third direction D3such that the driving transistor250is fully in the first trench. In addition, the driving transistor250may be at a lower level along the third direction D3than the first switching transistor255. For example, along the third direction D3, a height from an upper surface of the substrate110to an upper surface of the driving transistor250(e.g., an upper surface of the first source electrode210or an upper surface of the first drain electrode230) may be less than a height from an upper surface of the substrate110to an upper surface of the first switching transistor255(e.g., an upper surface of the second source electrode215or an upper surface of the second drain electrode235). Further, only the first organic film layer111may be under the driving transistor250, while both the first organic film layer111and the second organic film layer113may be under the first switching transistor255.

When the substrate110of the OLED display device100is a flexible substrate including a polyimide-based resin, the flexible substrate may have a relatively more electric charges than a glass substrate. When the OLED display device100is driven, an electric field between wirings included in the OLED display device100may be generated (e.g., the electric field is generated by a difference of a voltage level applied to a scan signal wiring and a voltage level applied to an emission signal wiring), such that the electric charges may be non-uniformly distributed under transistors by the electric field, such that the electric charges may interfere with driving the transistors. In other words, a threshold voltage of the transistors may be changed because of a non-uniform distribution of the electric charges, and a luminance of the sub-pixel structure200may be changed because of the changed amount of current. That is, reliability and lifetime of the transistors may be reduced. For example, when a relatively amount of current is continuously applied to the transistors because of the changed amount of current, the lifetime of the transistors may be relatively reduced.

The driving transistor250among the transistors may control a driving current according to a data signal, and the sub-pixel structure200may emit light according to the driving current. In other words, the driving transistor250may have a relatively greater effect on an emission of the sub-pixel structure200than the first switching transistor255. That is, when a threshold voltage of the driving transistor250is changed due to the non-uniformly distributed electric charges, a luminance change of the OLED display device100may be relatively greater than when a threshold voltage of the first switching transistor255is changed due to the non-uniformly distributed electric charges.

In example embodiments, when the second organic film layer113is removed under the driving transistor250(or the first opening101of the second organic film layer113is formed under the driving transistor250), an effect of the non-uniformly distributed electric charges on the driving transistor250may be reduced or prevented.

In example embodiments, the OLED display device100includes two transistors (e.g., the driving transistor250and the first switching transistor255). Alternatively, the OLED display device100may include at least three transistors and at least one capacitor. In addition, each of the driving transistor250and the first switching transistor255has a top gate structure. Alternatively, each of the driving transistor250and the first switching transistor255may have a bottom gate structure or a double gate structure.

In example embodiments, the first barrier layer112and the second barrier layer114are under the driving transistor250. Alternatively, the first barrier layer112, the second barrier layer114, or neither may be under the driving transistor250.

The planarization layer270may be on the insulating interlayer190, the first and second source electrodes210and215, and the first and second drain electrodes230and235. A contact hole275exposing a portion of the second drain electrode235of the first switching transistor255may be formed in the planarization layer270. The planarization layer270may have a thickness sufficient to cover the first and second source electrodes210and215, and the first and second drain electrodes230and235on the insulating interlayer190. In this case, the planarization layer270may have a substantially flat upper surface, and a planarization process may be further performed on the planarization layer270to realize a flat upper surface. The planarization layer270may include organic materials or inorganic materials. In example embodiments, the planarization layer270may include organic materials.

The lower electrode290may be on the planarization layer270. The lower electrode290may be in direct contact with the second drain electrode235via the contact hole275of the planarization layer270to be electrically connected to the first switching transistor255. The lower electrode290may include a metal, a metal alloy, metal nitride, conductive metal oxide, transparent conductive materials, etc., either alone or in a suitable combination thereof. Alternatively, the lower electrode290may have a multi-layered structure including a plurality of layers.

The pixel defining layer310may be on a portion of the lower electrode290and the planarization layer270. The pixel defining layer310may cover both lateral portions of the lower electrode290, and may have an opening315exposing a portion of an upper surface of the lower electrode290. The pixel defining layer310may include organic materials or inorganic materials. In example embodiments, the pixel defining layer310may include organic materials.

The light emitting layer330may be on the lower electrode290exposed by the pixel defining layer310. The light emitting layer330may be formed using at least one of light emitting materials capable of generating different colors of light (e.g., red light, blue light, green light, etc.) according to sub-pixels. Alternatively, the light emitting layer330may generate white light by stacking a plurality of light emitting materials capable of generating different colors of light, e.g., red light, green light, blue light, etc. In this case, a color filter may be on the light emitting layer330(e.g., to overlap the light emitting layer330on an upper surface of the TFE structure450) along the third direction D3. The color filter may include at least one selected from a red color filter, a green color filter, and a blue color filter. Alternatively, the color filter may include a yellow color filter, a cyan color filter, and a magenta color filter. The color filter may include a photosensitive resin, etc.

The upper electrode340may be on the pixel defining layer310and the light emitting layer330. The upper electrode340may cover the light emitting layer330and the pixel defining layer310, and may be on the entire substrate110. The upper electrode340may include a metal, a metal alloy, metal nitride, conductive metal oxide, transparent conductive materials, etc., alone or in a suitable combination thereof. Alternatively, the upper electrode340may have a multi-layered structure including a plurality of layers. Accordingly, the sub-pixel structure200may include the lower electrode290, the light emitting layer330, and the upper electrode340.

The first TFE layer451may be on the upper electrode340. The first TFE layer451may cover the upper electrode340, and may have a substantially uniform thickness along the third direction D3along a profile of the upper electrode340. The first TFE layer451may prevent the sub-pixel structure200from being deteriorated by the permeation of contaminants, e.g., moisture, water, oxygen, etc. In addition, the first TFE layer451may protect the sub-pixel structure200from external impacts. The first TFE layer451may include inorganic materials having flexibility.

The second TFE layer452may be on the first TFE layer451. The second TFE layer452may improve the flatness of the OLED display device100, and may protect the sub-pixel structure200. The second TFE layer452may include organic materials having flexibility.

The third TFE layer453may be on the second TFE layer452. The third TFE layer453may cover the second TFE layer452, and may have a substantially uniform thickness along the third direction D3along a profile of the second TFE layer452. The third TFE layer453together with the first TFE layer451and the second TFE layer452may prevent the sub-pixel structure200from being deteriorated by the permeation of contaminants, e.g., moisture, water, oxygen, etc. In addition, the third TFE layer453together with the first TFE layer451and the second TFE layer452may protect the sub-pixel structure200from external impacts. The third TFE layer453may include inorganic materials having flexibility. Accordingly, the TFE structure450may include the first TFE layer451, the second TFE layer452, and the third TFE layer453. Alternatively, the TFE structure450may have five layers structure where first through fifth TFE layers are stacked, a seven layer structure where the first through seventh TFE layers are stacked, and so forth.

In some example embodiments, an encapsulation substrate that substitutes for the TFE structure450may be on the upper electrode340. The encapsulation substrate may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluoride-doped quartz substrate, a sodalime glass substrate, a non-alkali glass substrate, etc.

As the OLED display device100in accordance with example embodiments includes the first opening101of the second organic film layer113under the driving transistor250, the driving transistor250may receive a relatively small effect on the non-uniformly distributed electric charges. Accordingly, reliability and lifetime of the driving transistor250included in the OLED display device100may be improved.

FIG. 4is a circuit diagram for describing an OLED and transistors included in the OLED display device ofFIG. 3. For example, the OLED display device100may include a plurality of sub-pixels, and each of the sub-pixels may correspond to a circuit illustrated inFIG. 4. Referring toFIG. 4, the OLED display device100may include an OLED (e.g., the sub-pixel structure200ofFIG. 3), transistors (e.g., the driving transistor250and the first switching transistor255ofFIG. 3), capacitors, etc.

The OLED may emit light based on a driving current ID. The OLED may include a first terminal and a second terminal. In example embodiments, the second terminal of the OLED receives a first power voltage ELVSS. For example, the first terminal of the OLED is an anode terminal and the second terminal of the OLED is a cathode terminal. Alternatively, the first terminal of the OLED may be a cathode terminal, and the second terminal of the OLED may be an anode terminal. In example embodiments, the anode terminal of the OLED may correspond to the lower electrode290ofFIG. 3and the cathode terminal of the OLED may correspond to the upper electrode340ofFIG. 3.

A first transistor TR1may include a gate terminal, a first terminal, and a second terminal. In example embodiments, the first terminal of the first transistor TR1is a source terminal, and the second terminal of the first transistor TR1is a drain terminal. Alternatively, the first terminal of the first transistor TR1may be a drain terminal, and the second terminal of the first transistor TR1may be a source terminal.

The driving current ID may be generated by the first transistor TR1. In example embodiments, the first transistor TR1operates in a saturation region. In this case, the first transistor TR1may generate the driving current ID based on a voltage difference of the gate terminal and the source terminal, and a gradation may be implemented based on the amount of the driving current ID generated by the first transistor TR1. Alternatively, the first transistor TR1operates in a linear region. In this case, a gradation may be implemented based on the amount of time during which the first transistor TR1provides the driving current ID to the OLED within one frame. In example embodiments, the first transistor TR1may correspond to the driving transistor250inside the first trench305ofFIG. 3.

A second transistor TR2may include a gate terminal, a first terminal, and a second terminal. A scan signal GW may be applied to the gate terminal of the second transistor TR2. The first terminal of the second transistor TR2may receive a data signal DATA. The second terminal of the second transistor TR2may be connected to the first terminal of the first transistor TR1. In example embodiments, the first terminal of the second transistor TR2is a source terminal and the second terminal of the second transistor TR2is a drain terminal. Alternatively, the first terminal of the second transistor TR2may be a drain terminal and the second terminal of the second transistor TR2may be a source terminal.

The second transistor TR2may provide the data signal DATA to the first terminal of the first transistor TR1while the scan signal GW is activated. In this case, the second transistor TR2operates in a linear region.

Third transistors TR3_1and TR3_2may include a gate terminal, a first terminal, and a second terminal. Here, the third transistor TR3_1and the third transistor TR3_2may be connected in series, and may serve as a dual transistor. For example, when the dual transistor is turned-off, a leakage current may be decreased. The gate terminals of the third transistors TR3_1and TR3_2may receive a scan signal GW. The first terminal of the third transistors TR3_1and TR3_2may be connected to the gate terminal of the first transistor TR1. The second terminal of the third transistors TR3_1and TR3_2may be connected to the second terminal of the first transistor TR1. In example embodiments, the first terminal of the third transistors TR3_1and TR3_2is a source terminal, and the second terminal of the third transistors TR3_1and TR3_2is a drain terminal. Alternatively, the first terminal of the third transistors TR3_1and TR3_2may be a drain terminal, and the second terminal of the third transistors TR3_1and TR3_2may be a source terminal.

The third transistors TR3_1and TR3_2may connect the gate terminal of the first transistor TR1to the second terminal of the first transistor TR1while the scan signal GW is activated. In this case, the third transistors TR3_1and TR3_2may operate in a linear region. That is, the third transistors TR3_1and TR3_2may form a diode connection of the first transistor TR1while the scan signal GW is activated. A voltage difference between the first terminal of the first transistor TR1and the gate terminal of the first transistor TR1, the voltage difference that corresponds to a threshold voltage of the first transistor TR1, may occur due to the diode connection. As a result, a sum voltage of the data signal DATA provided to the first terminal of the first transistor TR1and the voltage difference (i.e., the threshold voltage) may be applied to the gate terminal of the first transistor TR1while the scan signal GW is activated. Thus, the data signal DATA may be compensated as much as the threshold voltage of the first transistor TR1. The compensated data signal DATA may be applied to the gate terminal of the first transistor TR1. A uniformity of the driving current ID may be improved because of reducing an affect by the threshold voltage of the first transistor TR1.

A first node N1is between the third transistor TR3_1and the third transistor TR3_2. The OLED display device100may include the capacitor CL connected to the first node N1and a second power supply voltage ELVDD wiring. In this case, although a voltage level of the data signal DATA is changed, crosstalk in the first node N1that is adjacent to a data signal DATA wiring may be reduced.

An input terminal of an initialization voltage VINT is connected to a first terminal of fourth transistors TR4_1and TR4_2and a first terminal of a seventh transistor TR7, and an output terminal of an initialization voltage VINT is connected to a second terminal of the fourth transistors TR4_1and TR4_2and a first terminal of a storage capacitor CST.

The fourth transistors TR4_1and TR4_2may include a gate terminal, the first terminal, and the second terminal. Here, the fourth transistor TR4_1and the fourth transistor TR4_2may be connected in series, and may serve as a dual transistor. For example, when the dual transistor is turned-off, a leakage current may be decreased. The gate terminal of the fourth transistors TR4_1and TR4_2may receive a data initialization signal GI. The initialization voltage VINT may be applied to the first terminal of the fourth transistors TR4_1and TR4_2. The second terminal of the fourth transistors TR4_1and TR4_2may be connected to the gate terminal of the first transistor TR1. In example embodiments, the first terminal of the fourth transistors TR4_1and TR4_2is a source terminal, and the second terminal of the fourth transistors TR4_1and TR4_2is a drain terminal. Alternatively, the first terminal of the fourth transistors TR4_1and TR4_2may be a drain terminal and the second terminal of the fourth transistors TR4_1and TR4_2may be a source terminal.

The fourth transistors TR4_1and TR4_2may apply the initialization voltage VINT to the gate terminal of the first transistor TR1while the data initialization signal GI is activated. In this case, the fourth transistors TR4_1and TR4_2may operate in the linear region. Thus, the fourth transistor TR4_1and TR4_2may initialize the gate terminal of the first transistor TR1as the initialization voltage VINT while the data initialization signal GI is activated. In example embodiments, a voltage level of the initialization voltage VINT is sufficiently lower than a voltage level of the data signal DATA maintained by the storage capacitor CST in a previous frame. The initialization voltage VINT may be applied to the gate terminal of the first transistor TR1that is a P-channel metal oxide semiconductor (PMOS) type transistor. In some example embodiments, a voltage level of the initialization voltage VINT is sufficiently higher than the voltage level of the data signal DATA maintained by the storage capacitor CST in a previous frame. The initialization voltage VINT may be applied to the gate terminal of the first transistor TR1that is an N-channel metal oxide semiconductor (NMOS) type transistor.

In example embodiments, the data initialization signal GI is identical to the scan signal GW advanced by one horizontal time period. For example, the data initialization signal GI is applied to sub-pixels located in a (n)th row among a plurality of sub-pixels included in the OLED display device100(where n is an integer of 2 or more) is substantially a same as the scan signal GW applied to sub-pixels located in a (n−1)th row among a plurality of the sub-pixels. This is, the data initialization signal GI that is activated may be applied to the sub-pixels located in the (n)th row among the sub-pixels by applying the scan signal GW that is activated to the sub-pixels located in the (n−1)th row among the sub-pixels. As a result, the gate terminal of the first transistor TR1included in the sub-pixels located in the (n)th row among the sub-pixels may be initialized as the initialization voltage VINT when the data signal DATA is applied to sub-pixels located in the (n−1)th row among the sub-pixels.

A fifth transistor TR5may apply a second power voltage ELVDD to the first terminal of the first transistor TR1while an emission signal EM is activated. On the other hands, the fifth transistor TR5does not apply the second power voltage ELVDD while the emission signal EM is inactivated. In this case, the fifth transistor TR5may operate in the linear region. The fifth transistor TR5may apply the second power voltage ELVDD to the first terminal of the first transistor TR1while the emission signal EM is activated such that the first transistor TR1generates the driving current ID. In addition, the fifth transistor TR5does not apply the second power voltage ELVDD while the emission signal EM is inactivated such that the data signal DATA applied to the first terminal of the first transistor TR1is applied to the gate terminal of the first transistor TR1.

A sixth transistor TR6may include a gate terminal, a first terminal, and a second terminal. The emission signal EM may be applied to the gate terminal of the sixth transistor TR6. The first terminal of the sixth transistor TR6may be connected to the second terminal of the first transistor TR1. The second terminal of the sixth transistor TR6may be connected to the first terminal of the OLED. In example embodiments, the first terminal of the sixth transistor TR6is a source terminal and the second terminal of the sixth transistor TR6is a drain terminal. Alternatively, the first terminal of the sixth transistor TR6may be a drain terminal and the second terminal of the sixth transistor TR6may be a source terminal.

The sixth transistor TR6may provide the driving current ID generated by the first transistor TR1to the OLED while the emission signal EM is activated. In this case, the sixth transistor TR6may operate in the linear region. That is, the sixth transistor TR6may provide the driving current ID generated by the first transistor TR1to the OLED while the emission signal EM is activated such that the OLED emits light. In addition, the sixth transistor TR6may disconnect the first transistor TR1from the OLED while the emission signal EM is inactivated such that the compensated data signal DATA applied to the second terminal of the first transistor TR1is applied to the gate terminal of the first transistor TR1.

The seventh transistor TR7may include a gate terminal, a first terminal, and a second terminal. A diode initialization signal GB (e.g., the data initialization signal GI) may be applied to the gate terminal of the seventh transistor TR7. The initialization voltage VINT may be applied to the first terminal of the seventh transistor TR7. The second terminal of the seventh transistor TR7may be connected to the first terminal of the OLED. In example embodiments, the first terminal of the seventh transistor TR7is a source terminal and the second terminal of the seventh transistor TR7is a drain terminal. Alternatively, the first terminal of the seventh transistor TR7may be a drain terminal and the second terminal of the seventh transistor TR7may be a source terminal.

The seventh transistor TR7may apply the initialization voltage VINT to the first terminal of the OLED while the diode initialization signal GB is activated. In this case, the seventh transistor TR7may operate in the linear region. That is, the seventh transistor TR7may initialize the first terminal of the OLED as the initialization voltage VINT while the diode initialization signal GB is activated. In example embodiments, the seventh transistor TR7may correspond to the first switching transistor255illustrated inFIG. 3.

Alternatively, the data initialization signal GI and the diode initialization signal GB are a substantially same signal. An initialization operation of the gate terminal of the first transistor TR1may do not affect an initialization operation of the first terminal of the OLED. That is, the initialization operation of the gate terminal of the first transistor TR1and the initialization operation of the first terminal of the OLED may be independent to each other. Therefore, the data initialization signal GI is used as the diode initialization signal GB, thereby improving the manufacturing efficiency.

The storage capacitor CST may include the first terminal and the second terminal, and may be connected between a second power voltage ELVDD wiring and the gate terminal of the first transistor TR1. For example, the first terminal of the storage capacitor CST may be connected to the gate terminal of the first transistor TR1and the second terminal of the storage capacitor CST may be connected to the second power supply voltage ELVDD wiring. The storage capacitor CST may maintain a voltage level of the gate terminal of the first transistor TR1while the scan signal GW is inactivated. The emission signal EM may be activated while the scan signal GW is inactivated. The driving current ID generated by the first transistor TR1may be provided to the OLED while the emission signal EM is activated. Therefore, the driving current ID generated by the first transistor TR1may be provided to the OLED based on the voltage level maintained by the storage capacitor CST.

That is, in another cross-sectional view ofFIG. 1, the second through sixth transistors TR2, TR3_1, TR3_2, TR4_1, TR4_2, TR5, and TR6, as well as the first and seventh transistors TR1and TR7may be illustrated inFIG. 3.

FIGS. 5 through 10are cross-sectional views illustrating stages in a method of manufacturing an OLED display device in accordance with example embodiments.

Referring toFIG. 5, a rigid glass substrate105may be provided. The first organic film layer111may be formed on the entire rigid glass substrate105, and a first barrier layer112may be formed on the entire first organic film layer111. After the first barrier layer112is formed, a preliminary organic film layer may be formed on the first barrier layer112. After the preliminary organic film layer is formed, the first opening101may be formed by selectively etching the preliminary organic film layer. The preliminary organic film layer having the first opening101may be defined as a second organic film layer113.

Referring toFIG. 6, the second barrier layer114may fill the first opening101of the second organic film layer113and may be formed on the entire second organic film layer113. As the first organic film layer111, the first barrier layer112, the second organic film layer113, and the second barrier layer114are sequentially formed along the third direction D3, on the rigid glass substrate105, the substrate110may be formed. As the second organic film layer113has the first opening101, the first trench305may be formed in the substrate110.

Each of the first barrier layer112and the second barrier layer114may be formed using inorganic materials such as silicon compound, metal oxide, etc. For example, each of the first barrier layer112and the second barrier layer114may include, e.g., SiOx, SiNx, SiOxNy, SiOxCy, SiCxNy, AlOx, AlNx, TaOx, HfOx, ZrOx, TiOx, etc. In addition, each of the first organic film layer111and the second organic film layer113may be formed using polyimide, epoxy-based resin, acryl-based resin, polyester, photoresist, polyacryl-based resin, polyimide-based resin, a polyamide-based resin, a siloxane-based resin, etc. In example embodiments, the first and second barrier layers112and114each may include SiOx, and may block moisture or water that permeates through the first and second organic film layers111and113. Further, the first and second organic film layers111and113each may include a polyamide-based resin such that an OLED display device has flexibility, and the polyimide-based resin may be random copolymer or block copolymer. The polyimide-based resin may have a high transparency, a low coefficient of thermal expansion, and a high glass transition temperature. Since the polyimide-based resin includes an imide radical, heat resistance, chemical resistance, durability, and an electrical characteristics may be excellent.

Alternatively, the substrate110may be formed using a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluoride-doped quartz substrate, a sodalime glass substrate, a non-alkali glass substrate etc.

Referring toFIG. 7, the buffer layer115may be formed on the substrate110. In example embodiments, the buffer layer115may fill the first trench305and may be formed on the entire second barrier layer114. In other words, the buffer layer115may be formed as a substantially uniform thickness along a profile of the second barrier layer114on the second barrier layer114. The buffer layer115may prevent the diffusion of metal atoms and/or impurities from the substrate110. In addition, the buffer layer115may control a rate of a heat transfer in a crystallization process for forming active layers, thereby obtaining substantially uniform active layers. Further, the buffer layer115may improve a surface flatness of the substrate110when a surface of the substrate110is relatively irregular. According to a type of the substrate110, at least two buffer layers may be provided on the substrate110or the buffer layer may not be provided. For example, the buffer layer115may include organic materials or inorganic materials. In example embodiments, the buffer layer115may be formed using inorganic materials.

The first active layer130and the second active layer135may be formed on the buffer layer115. The first active layer130and the second active layer135may be spaced apart from each other. In example embodiments, the first active layer130may be inside the trench305and the second active layer135may be outside the trench305. Each of the first and second active layers130and135may include an oxide semiconductor, an inorganic semiconductor, an organic semiconductor, etc. In example embodiments, the first active layer130and the second active layer135may be simultaneously (or concurrently) formed using same materials. For example, after a preliminary active layer is formed on the entire buffer layer115, the first active layer130and the second active layer135may be simultaneously formed by selectively etching the preliminary active layer.

The gate insulation layer150may be formed on the first and second active layers130and135, and the buffer layer115. The gate insulation layer150may cover the first and second active layers130and135on the buffer layer115, and may be formed on the entire buffer layer115. For example, the gate insulation layer150may cover the first and second active layers130and135on the buffer layer115, and may be formed as a substantially uniform thickness along a profile of the first and second active layers130and135. Alternatively, the gate insulation layer150may sufficiently cover the first and second active layers130and135on the buffer layer115to have a substantially flat upper surface without a step around the first and second active layers130and135. The gate insulation layer150may be formed using silicon compound, metal oxide, etc.

A first gate electrode170and a second gate electrode175may be formed on the gate insulation layer150, and may be spaced apart from each other. In example embodiments, the first gate electrode170may be inside the trench305, and the second gate electrode175may be outside the trench305. In other words, the first gate electrode170may be formed on a portion of the gate insulation layer150under the first active layer130, and the second gate electrode175may be formed on a portion of the gate insulation layer150under the second active layer135.

Each of the first and second gate electrodes170and175may be formed using a metal, a metal alloy, metal nitride, conductive metal oxide, transparent conductive materials, etc. For example, each of the first and second gate electrodes170and175may include Au, Ag, Al, W, Cu, Pt, Ni, Ti, Pd, Mg, Ca, Li, Cr, Ta, Mo, Sc, Nd, Ir, an alloy of aluminum, AlNx, an alloy of silver, WNx, an alloy of copper, an alloy of molybdenum, TiNx, CrNx, TaNx, SRO, ZnOx, ITO, SnOx, InOx, GaOx, IZO, etc. These may be used alone or in a suitable combination thereof. Alternatively, each of the first and second gate electrodes170and175may have a multi-layered structure including a plurality of layers. In example embodiments, the first gate electrode170and the second gate electrode175may be simultaneously formed using same materials. For example, after a preliminary first electrode layer is formed on the entire gate insulation layer150, the first gate electrode170and the second gate electrode175may be simultaneously formed by selectively etching the preliminary first electrode layer.

Referring toFIG. 8, the insulating interlayer190may be formed on the first and second gate electrodes170and175and the gate insulation layer150. The insulating interlayer190may cover the first and second gate electrodes170and175on the gate insulation layer150, and may be formed on the entire gate insulation layer150. For example, the insulating interlayer190may cover the first and second gate electrodes170and175on the gate insulation layer150, and may have a substantially uniform thickness along a profile of the first and second gate electrodes170and175. Alternatively, the insulating interlayer190may sufficiently cover the first and second gate electrodes170and175on the gate insulation layer150to have a substantially flat upper surface without a step around the first and second gate electrodes170and175. The insulating interlayer190may be formed using silicon compound, metal oxide, etc.

The first source electrode210, the first drain electrode230, the second source electrode215, and the second drain electrode235may be formed on the insulating interlayer190. In example embodiments, the first source electrode210and the first drain electrode230may be formed inside the trench305, and the second source electrode215and the second drain electrode235may be formed outside the trench305. The first source electrode210may be in contact with a source region of the first active layer130via a contact hole formed by removing a first portion of the gate insulation layer150and the insulating interlayer190, and the first drain electrode230may be in contact with a drain region of the first active layer130via a contact hole formed by removing a second portion of the gate insulation layer150and the insulating interlayer190. In addition, the second source electrode215may be in contact with a source region of the second active layer135via a contact hole formed by removing a third portion of the gate insulation layer150and the insulating interlayer190, and the second drain electrode235may be in contact with a drain region of the second active layer135via a contact hole formed by removing fourth portion of the gate insulation layer150and the insulating interlayer190.

Each of the first and second source electrodes210and215and the first and second drain electrodes230and235may be formed using a metal, an alloy, metal nitride, conductive metal oxide, transparent conductive materials, etc. These may be used alone or in a suitable combination thereof. Alternatively, each of the first and second source electrodes210and215and the first and second drain electrodes230and235may have a multi-layered structure including a plurality of layers. In example embodiments, the first and second source electrodes210and215and the first and second drain electrodes230and235may be simultaneously formed using same materials. For example, after a preliminary second electrode layer is formed on the entire insulating interlayer190, the first and second source electrodes210and215and the first and second drain electrodes230and235may be simultaneously formed by selectively etching the preliminary second electrode layer.

Accordingly, the driving transistor250including the first active layer130, the first gate electrode170, the first source electrode210, and the first drain electrode230may be formed, and the first switching transistor255including the second active layer135, the second gate electrode175, the second source electrode215, and the second drain electrode235may be formed.

Referring toFIG. 9, the planarization layer270may be formed on the insulating interlayer190, the first and second source electrodes210and215, and the first and second drain electrodes230and235, and a contact hole exposing a portion of the second drain electrode235of the first switching transistor255may be formed in the planarization layer270. The planarization layer270may be formed sufficiently thick to cover the first and second source electrodes210and215and the first and second drain electrodes230and235on the insulating interlayer190. In this case, the planarization layer270may have a substantially flat upper surface, and a planarization process may be further performed on the planarization layer270to implement the flat upper surface of the planarization layer270. The planarization layer270may include organic materials or inorganic materials. In example embodiments, the planarization layer270may be formed using organic materials.

The lower electrode290may be formed on the planarization layer270. The lower electrode290may be in direct contact with the second drain electrode235via the contact hole275of the planarization layer270to be electrically connected to the first switching transistor255. The lower electrode290may be formed using a metal, a metal alloy, metal nitride, conductive metal oxide, transparent conductive materials, etc. These may be used alone or in a suitable combination thereof. Alternatively, the lower electrode290may have a multi-layered structure including a plurality of layers.

The pixel defining layer310may be on a portion of the lower electrode290and the planarization layer270. The pixel defining layer310may cover both lateral portions of the lower electrode290, and may have the opening315exposing a portion of an upper surface of the lower electrode290. The pixel defining layer310may include organic materials or inorganic materials. In example embodiments, the pixel defining layer310may be formed using organic materials.

Referring toFIG. 10, the light emitting layer330may be formed on the lower electrode290exposed by the opening315in the pixel defining layer310. The light emitting layer330may be formed using at least one of light emitting materials capable of generating different colors of light (e.g., red light, blue light, and green light, etc.) according to sub-pixels. Alternatively, the light emitting layer330may generally generate a white color of light by stacking a plurality of light emitting materials capable of generating different colors of light, e.g., red light, green light, blue light, etc. In this case, a color filter may be formed on the light emitting layer330. The color filter may include at least one selected from a red color filter, a green color filter, and a blue color filter. Alternatively, the color filter may include a yellow color filter, a cyan color filter, and a magenta color filter. The color filter may be formed using a photosensitive resin, etc.

The upper electrode340may be formed on the pixel defining layer310and the light emitting layer330. The upper electrode340may cover the light emitting layer330and the pixel defining layer310, and may be formed on the entire substrate110. The upper electrode340may be formed using a metal, a metal alloy, metal nitride, conductive metal oxide, transparent conductive materials, etc., alone or in a suitable combination thereof. Alternatively, the upper electrode340may have a multi-layered structure including a plurality of layers. Accordingly, a sub-pixel structure200may include the lower electrode290, the light emitting layer330, and the upper electrode340.

The first TFE layer451may be formed on the upper electrode340. The first TFE layer451may cover the upper electrode340, and may be formed as a substantially uniform thickness along a profile of the upper electrode340. The first TFE layer451may prevent the sub-pixel structure200from being deteriorated by the permeation of moisture, water, oxygen, etc. In addition, the first TFE layer451may protect the sub-pixel structure200from external impacts. The first TFE layer451may be formed using inorganic materials having flexibility.

The second TFE layer452may be formed on the first TFE layer451. The second TFE layer452may improve the flatness of the OLED display device, and may protect the sub-pixel structure200. The second TFE layer452may be formed using organic materials having flexibility.

The third TFE layer453may be formed on the second TFE layer452. The third TFE layer453may cover the second TFE layer452, and may have a substantially uniform thickness along a profile of the second TFE layer452. The third TFE layer453together with the first TFE layer451and the second TFE layer452may prevent the sub-pixel structure200from being deteriorated by the permeation of contaminants, e.g., moisture, water, oxygen, etc. In addition, the third TFE layer453together with the first TFE layer451and the second TFE layer452may protect the sub-pixel structure200from external impacts. The third TFE layer453may be formed using inorganic materials having flexibility. Accordingly, a TFE structure450including the first TFE layer451, the second TFE layer452, and the third TFE layer453may be formed. Alternatively, the TFE structure450may have five layers structure where first through fifth TFE layers are stacked or seven layers structure where the first through seventh TFE layers are stacked.

After the TFE structure450is formed, the rigid glass substrate105may be removed from the substrate110. Accordingly, the OLED display device100illustrated inFIG. 1may be manufactured.

FIG. 11is a cross-sectional view illustrating an OLED display device in accordance with example embodiments. An OLED display device500illustrated inFIG. 11may have a configuration substantially the same as or similar to that of an OLED display device100described with reference toFIGS. 1 through 4except for including a first lower block pattern350. InFIG. 11, detailed descriptions for elements that are substantially the same as or similar to elements described with reference toFIGS. 1 through 4may not be repeated.

Referring toFIG. 11, an OLED display device500may include the substrate110, a first lower block pattern350, the buffer layer115, the gate insulation layer150, the insulating interlayer190, the driving transistor250, the first switching transistor255, the first trench305, the planarization layer270, the pixel defining layer310, the sub-pixel structure200, the TFE structure450, etc. Here, the substrate110may include the first organic film layer111, the first barrier layer112, the second organic film layer113, and the second barrier layer114. The second organic film layer113may have the first opening101. In example embodiments, the first trench305of the substrate110may be defined by the first opening101of the second organic film layer113, and the first lower block pattern350may be buried in the internal substrate110under a the driving transistor250.

The first lower block pattern350may be on the first barrier layer112. In example embodiments, the first lower block pattern350may be in the first trench305between the first barrier layer112and the second barrier layer114. The second barrier layer114may have a thickness along the first direction D3on top of the first lower block pattern350than a remainder of the second barrier layer114. The first lower block pattern350may extend further along the first direction D1than the driving transistor250on both sides thereof.

A predetermined voltage may be applied to the first lower block pattern350. As the voltage is applied to the first lower block pattern350, the first lower block pattern350may relatively reduce that electric charges included in the substrate110interfere with driving the driving transistor250. Alternatively, the first lower block pattern350may be grounded in an outer portion of the OLED display device500. In this case, the electric charges included in the substrate110may be discharged to an outside through the first lower block pattern350. That is, as the first lower block pattern350is grounded, the first lower block pattern350may relatively reduce that the electric charges included in the substrate110interfere with driving the driving transistor250. The first lower block pattern350may include a metal, metal nitride, conductive metal oxide, transparent conductive materials, etc., alone or in a suitable combination thereof. Alternatively, the first lower block pattern350may have a multi-layered structure including a plurality of layers.

FIG. 12is a cross-sectional view illustrating an OLED display device in accordance with example embodiments. An OLED display device600illustrated inFIG. 12may have a configuration substantially the same as or similar to that of an OLED display device100described with reference toFIGS. 1 through 4except for a first groove106of a first organic film layer111. InFIG. 12, detailed descriptions for elements that are substantially the same as or similar to elements described with reference toFIGS. 1 through 4may not be repeated.

Referring toFIG. 12, an OLED display device600may include the substrate110, the buffer layer115, the gate insulation layer150, the insulating interlayer190, the driving transistor250, the first switching transistor255, a first trench305′, the planarization layer270, the pixel defining layer310, the sub-pixel structure200, the TFE structure450, etc. Here, the substrate110may include a first organic film layer111′, the first barrier layer112, the second organic film layer113, and the second barrier layer114. In addition, the second organic film layer113may have the first opening101and the first organic film layer111may have a first groove106. In example embodiments, the first trench305of the substrate110may be defined by the first groove106of the first organic film layer111and the first opening101of the second organic film layer113. In addition, the first barrier layer112may be in the first groove106.

The first groove106may be formed by removing at least a portion of the first organic film layer11. For example, a thickness of the first organic film layer111where the first groove106is formed may be less than or equal to about 1 micrometer. As the first groove106is formed by removing at least a portion of the first organic film layer111, an affect from electric charges included in the first organic film layer111under the driving transistor250may be relatively reduced. In other words, as the first groove106is formed, the number of the electric charges included in the first organic film layer111under the driving transistor250may be reduced, and reliability and lifetime of the driving transistor250may be increased.

FIG. 13is a cross-sectional view illustrating an OLED display device in accordance with example embodiments. An OLED display device700illustrated inFIG. 13may have a configuration substantially the same as or similar to that of an OLED display device600described with reference toFIG. 12except for including the first lower block pattern350. InFIG. 13, detailed descriptions for elements that are substantially the same as or similar to elements described with reference toFIG. 12may not be repeated.

Referring toFIG. 13, an OLED display device700may include the substrate110, the first lower block pattern350, the buffer layer115, the gate insulation layer150, the insulating interlayer190, the driving transistor250, the first switching transistor255, the first trench305′, the planarization layer270, the pixel defining layer310, the sub-pixel structure200, the TFE structure450, etc. Here, the substrate110may include the first organic film layer111′, the first barrier layer112, the second organic film layer113, and the second barrier layer114. In addition, the second organic film layer113may have the first opening101and the first organic film layer111may have the first groove106. In example embodiments, the first trench305of the substrate110may be defined by the first groove106of the first organic film layer111and the first opening101of the second organic film layer113. The first lower block pattern350may be buried in the internal substrate110under the driving transistor250.

The first lower block pattern350may be on the first barrier layer112. In example embodiments, the first lower block pattern350may be inside the first trench305, and between the first barrier layer112and the second barrier layer114. A predetermined voltage may be applied to the first lower block pattern350. As the voltage is applied to the first lower block pattern350, the first lower block pattern350may relatively reduce that electric charges included in the substrate110interfere with a drive of the driving transistor250. Alternatively, the first lower block pattern350may be grounded in an outer portion of the OLED display device700. In this case, the electric charges included in the substrate110may be discharged to an outside through the first lower block pattern350. That is, as the first lower block pattern350is grounded, the first lower block pattern350may relatively reduce that the electric charges included in the substrate110interfere with a drive of the driving transistor250.

FIG. 14is a cross-sectional view illustrating an OLED display device in accordance with example embodiments. An OLED display device800illustrated inFIG. 13may have a configuration substantially the same as or similar to that of an OLED display device700described with reference toFIG. 13except for a first signal wiring370and a second signal wiring375. InFIG. 14, detailed descriptions for elements that are substantially the same as or similar to elements described with reference toFIG. 13may not be repeated.

Referring toFIG. 14, an OLED display device800may include the substrate110, the first lower block pattern350, the buffer layer115, the gate insulation layer150, the insulating interlayer190, the driving transistor250, the first switching transistor255, a first signal wiring370, a second signal wiring375, the first trench305′, a second trench306, a third trench307, the planarization layer270, the pixel defining layer310, the sub-pixel structure200, the TFE structure450, etc. The substrate110may include the first organic film layer111′, the first barrier layer112, the second organic film layer113, and the second barrier layer114. The second organic film layer113may have the first opening101, a second opening102, and a third opening103. The first organic film layer111may have the first groove106, a second groove107, and a third groove108. Corresponding openings and groove may overlap one another along the third direction D3.

In example embodiments, the first trench305of the substrate110may be defined by the first groove106of the first organic film layer111′ and the first opening101of the second organic film layer113, and the first lower block pattern350may be buried in the internal substrate110under the driving transistor250. The second trench306of the substrate110may be defined by the second groove107of the first organic film layer111′ and the second opening102of the second organic film layer113. The third trench307of the substrate110may be defined by the first groove106of the first organic film layer111′ and the third opening103of the second organic film layer113. For example, the first trench305defined by the first groove106and the first opening101may be under the driving transistor250. The second groove107may be spaced apart from the first groove106along the first direction D1, and the second opening102and the first signal wiring370may be on the second groove107. The second groove107may be formed by removing at least a portion of the first organic film layer111′. The third groove108may be spaced apart from the first groove106along the first direction D1opposite the second groove107, e.g., such that the first groove106is between the second groove107and the third groove108, and the third opening103and the second signal wiring375may be on the third groove108. The third groove108may be formed by removing at least a portion of the first organic film layer111′.

The first signal wiring370may be inside the second trench306and a width of the second trench306may be less than a width of the first signal wiring370. Alternatively, a width of the second trench306may be greater than a width of the first signal wiring370. The first signal wiring370may include a data signal wiring, a scan signal wiring, a power supply voltage wiring, an emission signal wiring, an initialization signal wiring, and so forth. In example embodiments, the first signal wiring370may correspond to the emission signal wiring (e.g., the emission signal EM wiring ofFIG. 4), and may have a first voltage level. The first signal wiring370may include a metal, metal nitride, conductive metal oxide, transparent conductive materials, etc., alone or in a suitable combination thereof. Alternatively, the first signal wiring370may have a multi-layered structure including a plurality of layers.

The second signal wiring375may be inside the third trench307, and a width of the third trench307may be less than a width of the second signal wiring375. Alternatively, a width of the third trench307may be greater than a width of the second signal wiring375. The second signal wiring375may include a data signal wiring, a scan signal wiring, a power supply voltage wiring, an emission signal wiring, and an initialization signal wiring. In example embodiments, the second signal wiring375may correspond to the scan signal wiring (e.g., the scan signal GW wiring ofFIG. 4), and may have a second voltage level. Here, the first voltage level may be less than the second voltage level. The second signal wiring375may include a metal, metal nitride, conductive metal oxide, transparent conductive materials, etc. These may be used alone or in a suitable combination thereof. Alternatively, the second signal wiring375may have a multi-layered structure including a plurality of layers.

For example, when the OLED display device800is driven, an electric field may be generated by a difference of the first voltage level of the first signal wiring370and the second voltage level of the second signal wiring375, and the electric charges included in the substrate110may be non-uniformly distributed under transistors by the electric field. In example embodiments, as the second organic film layer113under each of the first signal wiring370and the second signal wiring375and at least a portion of the first organic film layer Ill are removed, an intensity of the electric field may be reduced. Accordingly, an effect of the electric charges with respect to the driving transistor250may be relatively reduced, and reliability and lifetime of the driving transistor250may be relatively increased.

FIG. 15is a cross-sectional view illustrating an OLED display device in accordance with example embodiments. An OLED display device900illustrated inFIG. 11may have a configuration substantially the same as or similar to that of an OLED display device100described with reference toFIGS. 1 through 4except for including a second switching transistor260. InFIG. 15, detailed descriptions for elements that are substantially the same as or similar to elements described with reference toFIGS. 1 through 4may not be repeated.

Referring toFIG. 15, an OLED display device900may include the substrate110, the buffer layer115, the gate insulation layer150, the insulating interlayer190, the driving transistor250, the first switching transistor255, a second switching transistor260, the first trench305, a planarization layer270, a pixel defining layer310, a sub-pixel structure200, the TFE structure450, etc. Here, the substrate110may include the first organic film layer111, the first barrier layer112, the second organic film layer113, and the second barrier layer114, The second organic film layer113may have a first opening101.

The driving transistor250may include the first active layer130, the first gate electrode170, the first source electrode210, and the first drain electrode230. The first switching transistor255may include the second active layer135, the second gate electrode175, the second source electrode215, and the second drain electrode235. The second switching transistor260may include a third active layer140, a third gate electrode180, a third source electrode220, and a third drain electrode240. In example embodiments, the first trench305of the substrate110may be defined by the first opening101of the second organic film layer113, and the driving transistor250and the second switching transistor260may be in the first trench305.

The second switching transistor260may be spaced apart from the driving transistor250along the first direction D1in the first trench305. In example embodiments, the driving transistor250may correspond to the first transistor TR1ofFIG. 4, the first switching transistor255may correspond to the seventh transistor TR7ofFIG. 4, and the second switching transistor260may correspond to the third transistor TR3_1ofFIG. 4.

As illustrated inFIG. 4, the first transistor TR1may generate the driving current ID based on a voltage difference of the gate terminal and the source terminal, and a gradation may be implemented based on the amount of the driving current ID generated by the first transistor TR1. That is, compared to the second through seventh transistors TR2, TR3_1, TR3_2, TR4_1, TR4_2, TR5, TR_6, and TR7, the first transistor TR1may have the largest influence with respect to light emission of the OLED. Meanwhile, the third transistor TR3_1among the second through seventh transistors TR2, TR3_1, TR3_2, TR4_1, TR4_2, TR5, TR_6, and TR7may have the second off largest influence with respect to an emission of the OLED (see Table 1). In example embodiments, as illustrated inFIG. 15, the first transistor TR1(e.g., the driving transistor250) and the third transistor TR3_1(e.g., second switching transistor260) that have a relatively large influence with respect to the emission of the OLED may be in the first trench305and spaced apart from each other. Accordingly, a display quality of the OLED display device900may be increased.

Table 1 is a table showing rate of luminance change of OLED as a threshold voltage of each of transistors, other than the driving transistor, is changed. As described above, the third transistor TR3_1may have a relatively large influence with respect to the light emission of the OLED.

FIG. 16is a cross-sectional view illustrating an OLED display device in accordance with example embodiments.FIG. 17is a circuit diagram for describing an OLED and transistors included in the OLED display device ofFIG. 16. An OLED display device1000illustrated inFIG. 16may have a configuration substantially the same as or similar to that of an OLED display device100described with reference toFIG. 15except for including the first lower block pattern350and a second lower block pattern355. InFIG. 16, detailed descriptions for elements that are substantially the same as or similar to elements described with reference toFIG. 15may not be repeated.

Referring toFIG. 16, an OLED display device1000may include the substrate110, the first lower block pattern350, the second lower block pattern355, the buffer layer115, the gate insulation layer150, the insulating interlayer190, the driving transistor250, the first switching transistor255, the second switching transistor260, the first trench305, the planarization layer270, the pixel defining layer310, the sub-pixel structure200, the TFE structure450, etc. Here, the substrate110may include the first organic film layer111, the first barrier layer112, the second organic film layer113, and the second barrier layer114, and the second organic film layer113may have the first opening101. In example embodiments, the first trench305of the substrate110may be defined by the first opening101of the second organic film layer113, and the first lower block pattern350may be buried in the internal substrate110under the driving transistor250. The second lower block pattern355may be buried in the internal substrate110under the second switching transistor260.

The first lower block pattern350and the second lower block pattern355may be on the first barrier layer112. In example embodiments, the first lower block pattern350and the second lower block pattern355may be in the first trench305, and may be between the first barrier layer112and the second barrier layer114. A predetermined voltage may be applied to each of the first and second lower block patterns350and355. As the voltage is applied to each of the first and second lower block patterns350and355, the first and second lower block patterns350and355may relatively reduce that electric charges included in the substrate110interfere with a drive of the driving transistor250and the second switching transistor260.

Each of the first and second lower block patterns350and355may include a metal, metal nitride, conductive metal oxide, transparent conductive materials, etc., alone or in a suitable combination thereof. Alternatively, each of the first and second lower block patterns350and355may have a multi-layered structure including a plurality of layers.

Referring toFIG. 17, the driving transistor250ofFIG. 16may correspond to a first transistor TR1ofFIG. 17, and the second switching transistor260ofFIG. 16may correspond to a third transistor TR3_1ofFIG. 17. In addition, the first lower block pattern350ofFIG. 16may correspond to a first back gate350ofFIG. 17, and the second lower block pattern355ofFIG. 16may correspond to a second back gate355ofFIG. 17.

As illustrated inFIG. 17, the first back gate350may be connected to a second power supply voltage ELVDD wiring and a second power supply voltage ELVDD may be applied to the first back gate350. In other words, a constant voltage may be applied to the first back gate350. Alternatively, the first back gate350may be connected to a wiring where a constant voltage of 1 volt or more is applied. The second back gate355may be connected to a scan signal GW wiring and a scan signal GW may be applied to the second back gate355. Additionally, to improve circuit characteristics (e.g., characteristics for blocking a leakage current), a first node N1between third transistors TR3_1and TR3_2may be connected to a second node N2between fourth transistors TR4_1and TR4_2.

Embodiments may be applied to various display devices including an OLED display device. For example, embodiments may be applied to vehicle-display device, a ship-display device, an aircraft-display device, portable communication devices, display devices for display or for information transfer, a medical-display device, etc.

By way of summation and review, when the lower substrate of the OLED display device includes a polyimide substrate, electric charges may interfere with driving transistors because the polyimide substrate includes the relatively large number of the electric charges than a glass substrate. However, according to embodiments, by removing a portion of the substrate under the driving transistors, this effect may be reduced. For example, as the OLED display device in accordance with example embodiments includes a driving transistor in a first trench, the driving transistor may receive a relatively small effect on non-uniformly distributed electric charges. Accordingly, reliability and lifetime of the driving transistor included in the OLED display device may be improved.