A semiconductor device according to an embodiment includes a silicon carbide layer having a first plane and a second plane; a source electrode; a drain electrode; first and second gate electrodes located; an n-type drift region and a p-type body region; n-type first and second source regions; a p-type first silicon carbide region and p-type second silicon carbide region having a p-type impurity concentration higher than the body region; first and second gate insulating layers; a p-type third silicon carbide region contacting the first silicon carbide region, a first n-type portion being located between the first gate insulating layer and the third silicon carbide region; and a p-type fourth silicon carbide region contacting the second silicon carbide region, a second n-type portion being located between the second gate insulating layer and the fourth silicon carbide region.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2017-100824, filed on May 22, 2017, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor device, an inverter circuit, a drive device, a vehicle, and an elevator.

BACKGROUND

Silicon carbide is expected as a material for next-generation semiconductor devices. As compared with silicon, the silicon carbide has superior physical properties such as a threefold band gap, approximately tenfold breakdown field strength, and approximately threefold thermal conductivity. By using these characteristics, a semiconductor device in which low loss and a high-temperature operation can be realized.

As a structure for reducing on-resistance of a metal oxide semiconductor field effect transistor (MOSFET) using the silicon carbide, there is a trench gate type MOSFET in which a gate electrode is provided in a trench. In the case where load short circuiting occurs at the output side of the trench gate type MOSFET, because the on-resistance is low, time until an excessive current flows and breakdown occurs may be shortened. That is, a short circuit tolerance may decrease.

DETAILED DESCRIPTION

A semiconductor device includes: a silicon carbide layer having a first plane and a second plane; a source electrode contacting the first plane; a drain electrode contacting the second plane; a first gate electrode located between the source electrode and the drain electrode; a second gate electrode located between the source electrode and the drain electrode; an n-type drift region located in the silicon carbide layer, the n-type drift region including a first n-type portion and a second n-type portion; a p-type body region located in the silicon carbide layer and located between the n-type drift region and the first plane; an n-type first source region located in the silicon carbide layer, the n-type first source region located between the p-type body region and the first plane, and the n-type first source region contacting the source electrode; an n-type second source region located in the silicon carbide layer, the n-type second source region located between the p-type body region and the first plane, the n-type second source region contacting the source electrode, and the first gate electrode being located between the n-type first source region and the n-type second source region; a p-type first silicon carbide region located in the silicon carbide layer, the p-type first silicon carbide region located between the n-type drift region and the first plane, the p-type first silicon carbide region contacting the source electrode, a distance between the second plane and the p-type first silicon carbide region being smaller than a distance between the second plane and the first gate electrode, the first gate electrode being located between the n-type first source region and the p-type first silicon carbide region, the p-type first silicon carbide region located between the first gate electrode and the p-type body region, and the p-type first silicon carbide region having a p-type impurity concentration higher than a p-type impurity concentration of the p-type body region; a p-type second silicon carbide region located in the silicon carbide layer, the p-type second silicon carbide region located between the n-type drift region and the first plane, the p-type second silicon carbide region contacting the source electrode, a distance between the second plane and the p-type second silicon carbide region being smaller than a distance between the second plane and the second gate electrode, the second gate electrode being located between the n-type second source region and the p-type second silicon carbide region, the p-type second silicon carbide region located between the second gate electrode and the p-type body region, and the p-type second silicon carbide region having a p-type impurity concentration higher than the p-type impurity concentration of the p-type body region; a first gate insulating layer located between the first gate electrode and the n-type drift region, between the first gate electrode and the p-type body region, between the first gate electrode and the p-type first silicon carbide region, and between the first gate electrode and the n-type first source region; a second gate insulating layer located between the second gate electrode and the n-type drift region, between the second gate electrode and the p-type body region, between the second gate electrode and the p-type second silicon carbide region, and between the second gate electrode and the n-type second source region; a p-type third silicon carbide region located in the silicon carbide layer, the p-type third silicon carbide region located between the second plane and the first gate electrode, the p-type third silicon carbide region contacting the p-type first silicon carbide region, the first n-type portion being located between the first gate insulating layer and the p-type third silicon carbide region; and a p-type fourth silicon carbide region located in the silicon carbide layer, the p-type fourth silicon carbide region located between the second plane and the second gate electrode, the p-type fourth silicon carbide region contacting the p-type second silicon carbide region, the second n-type portion being located between the second gate insulating layer and the p-type fourth silicon carbide region, and the p-type fourth silicon carbide region separated from the p-type third silicon carbide region.

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the following description, the same or similar members are denoted by the same reference numerals and the description of the members described once is appropriately omitted.

In addition, in the following description, notations n−, n, n−, p, and p−represent the relative magnitudes of impurity concentrations in respective conductive types. That is, an n-type impurity concentration of n+is relatively higher than an n-type impurity concentration of n and an n-type impurity concentration of n−is relatively lower than the n-type impurity concentration of n. In addition, a p-type impurity concentration of p+is relatively higher than a p-type impurity concentration of p and a p-type impurity concentration of p−is relatively lower than the p-type impurity concentration of p. The type and the n−type may be simply described as the n types and the p+type and the p−type may be simply described as the p types.

The impurity concentration can be measured by secondary ion mass spectrometry (SIMS), for example. In addition, the relative magnitude of the impurity concentration can be determined from the magnitude of a carrier concentration obtained by scanning capacitance microscopy (SCM), for example. In addition, a distance such as a depth of an impurity region can be obtained by SIMS, for example. In addition, the distance such as the depth of the impurity region can be obtained from a combined image of an SCM image and an atomic force microscope (AFM) image, for example.

First Embodiment

A semiconductor device according to this embodiment includes: a silicon carbide layer having a first plane and a second plane; a source electrode contacting the first plane; a drain electrode contacting the second plane; a first gate electrode located between the source electrode and the drain electrode; a second gate electrode located between the source electrode and the drain electrode; an n-type drift region located in the silicon carbide layer; a p-type body region located in the silicon carbide layer and located between the drift region and the first plane; an n-type first source region located in the silicon carbide layer, located between the body region and the first plane, and contacting the source electrode; an n-type second source region located in the silicon carbide layer, located between the body region and the first plane, and contacting the source electrode, the first gate electrode being located between the first source region and the second source region; a p-type first silicon carbide region located in the silicon carbide layer, located between the drift region and the first plane, contacting the source electrode, a distance between the second plane and the first silicon carbide region being smaller than a distance between the second plane and the first gate electrode, the first gate electrode being located between the first source region and the first silicon carbide region, located between the first gate electrode and the body region, and having a p-type impurity concentration higher than a p-type impurity concentration of the body region; a p-type second silicon carbide region located in the silicon carbide layer, located between the drift region and the first plane, contacting the source electrode, a distance between the second plane and the second silicon carbide region being smaller than a distance between the second plane and the second gate electrode, the second gate electrode being located between the second source region and the second silicon carbide region, located between the second gate electrode and the body region, and having a p-type impurity concentration higher than the p-type impurity concentration of the body region; a first gate insulating layer located between the first gate electrode and the drift region, between the first gate electrode and the body region, between the first gate electrode and the first silicon carbide region, and between the first gate electrode and the first source region; a second gate insulating layer located between the second gate electrode and the drift region, between the second gate electrode and the body region, between the second gate electrode and the second silicon carbide region, and between the second gate electrode and the second source region; a p-type third silicon carbide region located in the silicon carbide layer, located between the second plane and the first gate electrode, and contacting the first silicon carbide region, a first n-type portion to be a part of the drift region being located between the first gate insulating layer and the third silicon carbide region; and a p-type fourth silicon carbide region located in the silicon carbide layer, located between the second plane and the second gate electrode, and contacting the second silicon carbide region, a second n-type portion to be a part of the drift region being located between the second gate insulating layer and the fourth silicon carbide region, and separated from the third silicon carbide region.

FIG. 1is a schematic cross-sectional view of the semiconductor device according to this embodiment. The semiconductor device according to this embodiment is a trench gate type vertical MOSFET100using silicon carbide. The vertical MOSFET100is an n-channel MOSFET using electrons as carriers.

FIG. 2is a schematic plan view of the semiconductor device according to this embodiment.FIG. 2is a plan view of a first plane (P1ofFIG. 1) ofFIG. 1.

FIG. 3is a schematic plan view of the semiconductor device according to this embodiment.FIG. 3is a plan view of a plane Px ofFIG. 1.

The MOSFET100includes a silicon carbide layer10, a source electrode12, a drain electrode14, a first gate insulating layer16a, a second gate insulating layer16b, a first gate electrode18a, a second gate electrode18b, a first interlayer insulating layer20a, a second interlayer insulating layer20b, a first trench22a, and a second trench22b.

In the silicon carbide layer10, an n+-type drain region24, an n−-type or n-type drift region26, a p-type body region28, an n+-type first source region30a, an n+-type second source region30b, a p+-type first diode region32a(first silicon carbide region), a p+-type second diode region32b(second silicon carbide region), a p+-type first current limiting region34a(third silicon carbide region), and a p+-type second current limiting region34b(fourth silicon carbide region) are located.

The silicon carbide layer10includes a first plane (“P1” inFIG. 1) and a second plane (“P2” inFIG. 1). Hereinafter, the first plane is also referred to as a surface and the second plane is also referred to as a back surface. Hereinafter, the “depth” means a depth based on the first plane.

The first plane is, for example, a plane inclined by 0° to 8° (zero degree to eight degree) with respect to a (0001) face. That is, the first plane is a plane in which a normal is inclined by 0° to 8° with respect to a c axis in a [0001] direction. In other words, an off angle with respect to the (0001) face is 0° to 8°. In addition, the second plane is, for example, a plane inclined by 0° to 8° with respect to a (000-1) face.

The (0001) face is referred to as a silicon face. The (000-1) face is referred to as a carbon face. An inclination direction of each of the first plane and the second plane is, for example, a direction of an a axis to be a [11-20] direction. InFIG. 1, a second direction shown in the drawing is the direction of the a axis.

The n+-type drain region24is provided at the back surface side of the silicon carbide layer10. The drain region24contains nitrogen (N) as n-type impurities, for example. The n-type impurity concentration of the drain region24is, for example, 1×1018cm−3to 1×1021cm−3.

The n−-type or n-type drift region26is provided on the drain region24. The drift region26contains nitrogen (N) as n-type impurities, for example. The n-type impurity concentration of the drift region26is lower than the n-type impurity concentration of the drain region24. The n-type impurity concentration of the drift region26is, for example, 4×1014cm−3to 1×1019cm−3. Typically, the n-type impurity concentration is, for example, 2×1016cm−3. A thickness of the drift region26is, for example, 5 μm to 150 μm. Typically, the thickness is, for example, 10 μm.

The drift region26has an n−-type first low-concentration region26aand an n-type high-concentration region26b. The high-concentration region26bhas a function of reducing the on-resistance of the MOSFET100.

An n-type impurity concentration of the high-concentration region26bis higher than an n-type impurity concentration of the first low-concentration region26a. The n-type impurity concentration of the high-concentration region26bis, for example, 2×1017cm−3to 1×1019cm−3. The n-type impurity concentration is preferably 5×1017cm−3to 5×1018cm−3and more preferably 8×1017cm−3to 3×1018cm−3. Typically, the n-type impurity concentration is, for example, 1×1018cm−3. If the n-type impurity concentration of the high-concentration region26bis lowered, an ability to diffuse a current is lowered and if the n-type impurity concentration is high, a breakdown voltage may not be obtained.

The p-type body region28is provided between the drift region26and the surface of the silicon carbide layer10. The body region28functions as a channel region of the MOSFET100. That is, when the MOSFET100is turned on, a channel in which electrons flow to a region of the body region28contacting the first gate insulating layer16aand a region of the body region28contacting the second gate insulating layer16bis formed. The region of the body region28contacting the first gate insulating layer16aand the region of the body region28contacting the second gate insulating layer16bbecome channel formation regions.

In the MOSFET100, only the body region28of one side of the first trench22afunctions as a channel region. In addition, in the MOSFET100, only the body region28of one side of the second trench22bfunctions as a channel region.

The body region28contains aluminum (Al) as p-type impurities, for example. A p-type impurity concentration of the body region28is, for example, 5×1016cm−3to 5×1017cm−3. Typically, the p-type impurity concentration is, for example, 1×1017cm−3. If the p-type impurity concentration of the body region28is low, mobility is improved, but a threshold voltage decreases. If the p-type impurity concentration of the body region28is high, the mobility is lowered, but the threshold voltage increases.

For example, the body region28is formed with a stacked structure of a low-concentration layer and a high-concentration layer, so that high mobility can be realized by the low-concentration layer and a high threshold voltage can be realized by the high-concentration layer. For example, a p-type impurity concentration of the low-concentration layer is 2×1016cm−3and a p-type impurity concentration of the high-concentration layer is 4×1017cm−3.

A depth of the body region28is, for example, 0.2 μm to 1.0 μm. Typically, the depth is, for example, 0.6 μm.

The n+-type first source region30ais provided between the body region28and the surface of the silicon carbide layer10. The first source region30acontacts the source electrode12. The first source region30acontacts the first gate insulating layer16a.

The first source region30acontains phosphorus (P) as n-type impurities, for example. An n-type impurity concentration of the first source region30ais higher than the n-type impurity concentration of the drift region26.

The n-type impurity concentration of the first source region30ais, for example, 1×1019cm−3to 1×1021cm−3. A depth of the first source region30ais smaller than the depth of the body region28and the depth is, for example, 0.1 μm to 0.3 μm. Typically, the depth is, for example, 0.2 μm. A distance between the drift region26and the first source region30ais, for example, 0.1 μm to 0.9 μm. Typically, the distance is, for example, 0.4 μm.

The n+-type second source region30bis provided between the body region28and the surface of the silicon carbide layer10. The second source region30bcontacts the source electrode12. The second source region30bcontacts the second gate insulating layer16b.

The second source region30bcontains phosphorus (P) as n-type impurities, for example. An n-type impurity concentration of the second source region30bis higher than the n-type impurity concentration of the drift region26.

The n-type impurity concentration of the second source region30bis, for example, 1×1019cm−3to 1×1021cm−3. A depth of the second source region30bis smaller than the depth of the body region28and the depth is, for example, 0.1 μm to 0.3 μm. Typically, the depth is, for example, 0.2 μm. A distance between the drift region26and the second source region30bis, for example, 0.1 μm to 0.9 μm. Typically, the distance is, for example, 0.4 μm.

The first source region30aand the second source region30bhave the same shape and impurity concentration in a range of a manufacturing variation.

The p+-type first diode region32ais provided between the drift region26and the surface of the silicon carbide layer10. The first diode region32acontacts the source electrode12.

A distance (d1ofFIG. 1) between a back surface of the silicon carbide layer10and the first diode region32ais smaller than a distance (d2ofFIG. 1) between the back surface of the silicon carbide layer10and the first gate electrode18a.

The first gate electrode18ais located between the first diode region32aand the first source region30a. The first diode region32ais located between the first gate electrode18aand the body region28.

A depth of the first diode region32ais larger than a depth of an end portion of the first gate insulating layer16aat the back surface side of the silicon carbide layer10.

In the first diode region32a, a pn junction between the first diode region32aand the drift region26functions as a body diode of the MOSFET100. In addition, the first diode region32ahas a function of reducing contact resistance between the source electrode12and the silicon carbide layer10. A potential of the body region28is fixed to a source potential by the first diode region32a.

In addition, a field applied to the first gate insulating layer16acontacting the first diode region32ais alleviated by the first diode region32a. Therefore, a breakdown voltage of the first gate insulating layer16ais improved.

A p-type impurity concentration of the first diode region32ais higher than the p-type impurity concentration of the body region28, for example. The p-type impurity concentration is, for example, 1×1018cm−3to 1×1021cm−3. Typically, the p-type impurity concentration is, for example, 1×1019cm−3. In addition, a contact portion with a metal preferably has a high concentration, for example, 1×1019cm−3to 1×1021cm−3.

The p+-type second diode region32bis provided between the drift region26and the surface of the silicon carbide layer10. The second diode region32bcontacts the source electrode12.

A distance between the back surface of the silicon carbide layer10and the second diode region32bis smaller than a distance between the back surface of the silicon carbide layer10and the second gate electrode18b.

The second gate electrode18bis located between the second diode region32band the second source region30b. The second diode region32bis located between the second gate electrode18band the body region28.

A depth of the second diode region32bis larger than a depth of an end portion of the second gate insulating layer16bat the back surface side of the silicon carbide layer10.

In the second diode region32b, a pn junction between the second diode region32band the drift region26functions as the body diode of the MOSFET100. In addition, the second diode region32bhas a function of reducing contact resistance between the source electrode12and the silicon carbide layer10. The potential of the body region28is fixed to the source potential by the second diode region32b.

In addition, a field applied to the second gate insulating layer16bcontacting the second diode region32bis alleviated by the second diode region32b. Therefore, a breakdown voltage of the second gate insulating layer16bis improved.

A p-type impurity concentration of the second diode region32bis higher than the p-type impurity concentration of the body region28. The p-type impurity concentration is, for example, 1×1018cm−3to 1×1021cm−3. Typically, the p-type impurity concentration is, for example, 1×1019cm−3. In addition, a contact portion with a metal preferably has a high concentration, for example, 1×1019cm−3to 1×1021cm−3.

The first diode region32aand the second diode region32bhave the same shape and impurity concentration in a range of a manufacturing variation.

The first gate electrode18ais provided between the source electrode12and the drain electrode14. The first gate electrode18ais provided in the first trench22aformed in the silicon carbide layer10. The first gate electrode18ais provided on the first gate insulating layer16a. The first gate electrode18aextends in a first direction parallel to the surface of the silicon carbide layer10.

The first gate electrode18ais a conductive layer. The first gate electrode18ais, for example, polycrystalline silicon containing p-type impurities or n-type impurities.

The second gate electrode18bis provided between the source electrode12and the drain electrode14. The second gate electrode18bis provided in the second trench22bformed in the silicon carbide layer10. The second gate electrode18bis provided on the second gate insulating layer16b. The second gate electrode18bextends in the first direction parallel to the surface of the silicon carbide layer10.

The second gate electrode18bis a conductive layer. The second gate electrode18bis, for example, polycrystalline silicon containing p-type impurities or n-type impurities.

The first gate insulating layer16ais provided between the drift region26, the body region28, the first diode region32a, and the first source region30aand the first gate electrode18a. The first gate insulating layer16ais provided in the first trench22a.

The first gate insulating layer16aprovided on one side surface of the first trench22acontacts the first diode region32aand is covered with the first diode region32a.

The depth of the end portion of the first gate insulating layer16aat the back surface side of the silicon carbide layer10is larger than the depth of the body region28. In other words, a distance between the first gate insulating layer16aand the drain electrode14is smaller than a distance between the body region28and the drain electrode14.

The first gate insulating layer16ais, for example, a silicon oxide film. For example, a high-k insulating film (high-permittivity insulating film such as HfSiON, ZrSiON, and AlON) can be applied to the first gate insulating layer16a. In addition, a stacked film of the silicon oxide film (SiO2) and the high-K insulating film is also effective for improving drive performance or improving breakdown voltage characteristics. By increasing the thickness of the gate insulating film at the bottom of the trench, the breakdown voltage can be improved. By increasing the thickness of the gate insulating film at the side contacting the first diode region32a, the width of the first diode region32acan be reduced and the device can be miniaturized.

The second gate insulating layer16bis provided between the drift region26, the body region28, the second diode region32b, and the second source region30band the second gate electrode18b. The second gate insulating layer16bis provided in the second trench22b.

The second gate insulating layer16bprovided on one side surface of the second trench22bcontacts the second diode region32band is covered with the second diode region32b.

The depth of the end portion of the second gate insulating layer16bat the back surface side of the silicon carbide layer10is larger than the depth of the body region28. In other words, a distance between the second gate insulating layer16band the drain electrode14is smaller than a distance between the body region28and the drain electrode14.

The second gate insulating layer16bis, for example, a silicon oxide film. For example, a high-k insulating film (high-permittivity insulating film such as HfSiON, ZrSiON, and AlON) can be applied to the second gate insulating layer16b. In addition, a stacked film of the silicon oxide film (SiO2) and the high-K insulating film is also effective for improving drive performance or improving breakdown voltage characteristics. By increasing the thickness of the gate insulating film at the bottom of the trench, the breakdown voltage can be improved. By increasing the thickness of the gate insulating film at the side contacting the second diode region32b, the width of the second diode region32bcan be reduced and the device can be miniaturized.

The p+-type first current limiting region34ais located between the back surface of the silicon carbide layer10and the first gate electrode18a. The first current limiting region34acontacts the first diode region32a. The p+-type first current limiting region34aextends in the first direction.

In particular, the first current limiting region34ahas a function of limiting an amount of on-current or a path of the on-current at the time of load short circuiting of the MOSFET100.

The first field alleviation portion26wis located between the first current limiting region34aand the first gate electrode18a. The first field alleviation portion26wis located between the first current limiting region34aand the first gate insulating layer16a. The first field alleviation portion26wis a part of the drift region26. The first field alleviation portion26wis located in the n-type high-concentration region26b.

For example, a distance (d3ofFIG. 1) between the first current limiting region34aand the first gate insulating layer16ais 0.05 μm to 0.2 μm.

For example, a distance (d1ofFIG. 1) between the back surface of the silicon carbide layer10and the first diode region32ais smaller than a distance (d4ofFIG. 1) between the back surface of the silicon carbide layer10and the first current limiting region34a. In other words, the depth of the first diode region32ais larger than the depth of the first current limiting region34a.

For example, a width of the first current limiting region34ain the second direction is larger than a width of the first diode region32ain the second direction.

For example, an end portion of the first current limiting region34aexists at the side of the first diode region32afrom an extension line of the side surface of the first trench22aat the side where the channel formation region exists.

A p-type impurity concentration of the first current limiting region34ais higher than the p-type impurity concentration of the body region28. The p-type impurity concentration is, for example, 6×1018cm−3to 1×1020cm−3. Typically, the p-type impurity concentration is, for example, 2×1019cm−3.

For example, the p-type impurity concentration of the first current limiting region34ais higher than the p-type impurity concentration of the first diode region32acoming close to the first current limiting region34a. For example, the p-type impurity concentration of the first current limiting region34ais higher than the p-type impurity concentration near the bottom of the first diode region32a.

In particular, the second current limiting region34bhas a function of limiting an amount of on-current or a path of the on-current at the time of load short circuiting of the MOSFET100.

The second field alleviation portion26xis located between the second current limiting region34band the second gate electrode18b. The second field alleviation portion26xis located between the second current limiting region34band the second gate insulating layer16b. The second field alleviation portion26xis a part of the drift region26. The second field alleviation portion26xis located in the n-type high-concentration region26b.

For example, a distance between the second current limiting region34band the second gate insulating layer16bis 0.05 μm to 0.2 μm.

For example, a distance between the back surface of the silicon carbide layer10and the second diode region32bis smaller than a distance between the back surface of the silicon carbide layer10and the second current limiting region34b. In other words, the depth of the second diode region32bis larger than the depth of the second current limiting region34b.

For example, a width of the second current limiting region34bin the second direction is larger than a width of the second diode region32bin the second direction.

For example, an end portion of the second current limiting region34bexists at the side of the second diode region32bfrom an extension line of the side surface of the second trench22bat the side where the channel formation region exists.

A p-type impurity concentration of the second current limiting region34bis higher than the p-type impurity concentration of the body region28. The p-type impurity concentration is, for example, 6×1018cm−3to 1×1020cm−3. Typically, the p-type impurity concentration is, for example, 2×1019cm−3.

For example, the p-type impurity concentration of the second current limiting region34bis higher than the p-type impurity concentration of the second diode region32bcoming close to the second current limiting region34b. For example, the p-type impurity concentration of the second current limiting region34bis higher than the p-type impurity concentration near the bottom of the second diode region32b.

The first current limiting region34aand the second current limiting region34bhave the same shape and impurity concentration in a range of a manufacturing variation.

For example, a distance (d5ofFIG. 1) between the first current limiting region34aand the second current limiting region34bis smaller than a distance (d6ofFIG. 1) between the first diode region32aand the second gate insulating layer16b.

In addition, a boundary (position shown by a dotted line inFIG. 1) between the first low-concentration region26aand the high-concentration region26bis preferably located closer to the back surface of the silicon carbide layer10than the first current limiting region34aand the second current limiting region34b. As a result, a current easily flows around the back side of the first current limiting region34aor the second current limiting region34band low resistance is realized.

The first interlayer insulating layer20ais provided on the first gate electrode18a. The first interlayer insulating layer20ais, for example, a silicon oxide film.

The second interlayer insulating layer20bis provided on the second gate electrode18b. The second interlayer insulating layer20bis, for example, a silicon oxide film.

The source electrode12is provided on the surface of the silicon carbide layer10. The source electrode12contacts the first source region30a, the second source region30b, the first diode region32a, and the second diode region32b.

The source electrode12contains a metal. The metal forming the source electrode12has a stacked structure of titanium (Ti) and aluminum (Al), for example. The source electrode12may contain metal silicide or metal carbide that contacts the silicon carbide layer10.

The drain electrode14is provided on the back surface of the silicon carbide layer10. The drain electrode14contacts the drain region24.

The drain electrode14is, for example, a metal or a metal semiconductor compound. The drain electrode14contains a material selected from the group consisting of nickel silicide (NiSi), titanium (Ti), nickel (Ni), silver (Ag), and gold (Au), for example.

Hereinafter, a function and an effect of the semiconductor device according to the embodiment will be described.

In the MOSFET100according to this embodiment, the amount of on-current or the path of the on-current at the time of load short circuiting of the MOSFET100can be limited by the first current limiting region34aand the second current limiting region34b. Therefore, a short circuit tolerance of the MOSFET100can be improved. Details will be described below.

In a trench gate type MOSFET in which a gate electrode is provided in a trench, on-resistance per unit area can be reduced and an on-current can be increased. However, in the case where load short circuiting occurs at the output side of the MOSFET, because the on-resistance is low, time until an excessive current flows and breakdown occurs may be shortened. That is, a short circuit tolerance may decrease. In the MOSFET, it is required to guarantee the short circuit tolerance of 10 microseconds or more.

FIG. 4is a schematic cross-sectional view of a semiconductor device according to a first comparative example. A MOSFET 2000 is different from the MOSFET100according to this embodiment in that the body region28at both sides of the first trench22aand the body region28at both sides of the second trench22bfunction as channel regions. In addition, the MOSFET 2000 is different from the MOSFET100in that the first current limiting region34aand the second current limiting region34bare not included.

InFIG. 4, a path of an on-current is shown by a dotted arrow. As apparent fromFIG. 4, because the channel regions are formed at both sides of the first trench22aduring an on-operation, currents flowing from both the channel regions to the drift region26cross immediately below the first trench22aand an on-current density increases. Therefore, when load short circuiting occurs, an amount of heat generated immediately below the first trench22aincreases and time until breakdown occurs may be shortened. Accordingly, a short circuit tolerance decreases.

FIG. 5is a schematic cross-sectional view of a semiconductor device according to a second comparative example. A MOSFET 2100 is different from the MOSFET100according to this embodiment in that the first current limiting region34aand the second current limiting region34bare not included.

InFIG. 5, a path of an on-current is shown by a dotted arrow. As apparent fromFIG. 5, channel regions are formed in only the body region28of one side of the first trench22aand the body region28of one side of the second trench22b, during an on-operation. Since a distance between the two channel regions adjacent to each other is long, crossing of currents flowing from the two channel regions to the drift region26is suppressed. Therefore, an amount of heat generated when load short circuiting occurs is suppressed and time until breakdown occurs may be lengthened. Accordingly, the short circuit tolerance is improved.

FIG. 6is an explanatory view of a function and an effect of the semiconductor device according to this embodiment. In the MOSFET100according to this embodiment, the first current limiting region34aand the second current limiting region34bare added to the configuration of the MOSFET 2100. By including the first current limiting region34aand the second current limiting region34b, an amount of current flowing from the channel region to the drift region26and an extension of a path of the current are suppressed. The path of the current flowing from the channel region to the drift region26is limited to a narrow region. Therefore, the amount of currents flowing from the two adjacent channel regions to the drift region26and crossing of the currents are suppressed. Therefore, the amount of heat generated when load short circuiting occurs is further suppressed and the time until the breakdown occurs is further lengthened. Therefore, the short circuit tolerance is further improved.

From the viewpoint of limiting the path of the current flowing from the channel region to the drift region26, the distance (d5ofFIG. 1) between the first current limiting region34aand the second current limiting region34bis preferably smaller than the distance (d6ofFIG. 1) between the first diode region32aand the second gate insulating layer16b.

From the viewpoint of limiting the path of the current flowing from the channel region to the drift region26, the width of the first current limiting region34ain the second direction is preferably larger than the width of the first diode region32ain the second direction. Due to the same reason, the width of the second current limiting region34bin the second direction is preferably larger than the width of the second diode region32bin the second direction.

From the viewpoint of appropriately limiting the path of the current flowing from the channel region to the drift region26, the p-type impurity concentration of each of the first current limiting region34aand the second current limiting region34bis preferably 6×1018cm−3to 1×1020cm−3and more preferably 8×1018cm−3to 4×1019cm−3. Typically, the p-type impurity concentration is, for example, 2×1019cm−3.

From the viewpoint of not excessively limiting the path of the current flowing from the channel region to the drift region26, the end portion of the first current limiting region34apreferably exists at the side of the first diode region32afrom the extension line of the side surface of the first trench22aat the side where the channel formation region exists, and the end portion of the second current limiting region34bpreferably exists at the side of the second diode region32bfrom the extension line of the side surface of the second trench22bat the side where the channel formation region exists.

The ends, which are opposite to the channel formation regions, of the first current limiting region34aand the second current limiting region34bcan adjust the positions so that crossing of the current paths in the drift region26is minimized.

In the MOSFET100, the n-type first field alleviation portion26wexists between the p+-type first current limiting region34aand the first gate insulating layer16a. By providing the first field alleviation portion26w, it is possible to alleviate the field applied to the first gate insulating layer16awhen the MOSFET100is turned off. In other words, as compared with the case when the first field alleviation portion26wdoes not exist, that is, when the first current limiting region34acontacts the first gate insulating layer16, the field applied to the first gate insulating layer16ais alleviated. Therefore, the breakdown voltage of the first gate insulating layer16ais improved and reliability of the MOSFET100is improved. The n-type first field alleviation portion26wbecomes a barrier layer of hot holes. The n-type first field alleviation portion26wis also effective for preventing breakdown of the first gate insulating layer16adue to avalanche.

Likewise, the n-type second field alleviation portion26xexists between the second current limiting region34band the second gate insulating layer16b, so that the breakdown voltage of the second gate insulating layer16bis also improved.

From the viewpoint of improving the breakdown voltage of the first gate insulating layer16a, the distance (d3ofFIG. 1) between the first current limiting region34aand the first gate insulating layer16ais preferably 0.05 μm to 0.2 μm. Due to the same reason, the distance between the second current limiting region34band the second gate insulating layer16bis preferably 0.05 μm to 0.2 μm.

When the p-type impurity concentrations of the first current limiting region34aand the second current limiting region34bare higher than the p-type impurity concentrations of the first diode region32aand the second diode region32b, crystal defects induced at the time of forming the first current limiting region34aand the second current limiting region34bmay degrade the diode characteristics. Therefore, the depths of the first diode region32aand the second diode region32bare preferably caused to be larger than the depths of the first current limiting region34aand the second current limiting region34bso that the diode characteristics depend on the attributes of the first diode region32aand the second diode region32bmainly.

In particular, from the viewpoint of increasing the on-current in the normal on-state of the MOSFET100, the drift region26preferably has the n−-type first low-concentration region26aand the n-type high-concentration region26b. The resistance of the region to be the path of the on-current is reduced and the current efficiently diffuses in the drift region26. Therefore, the on-current increases.

The n-type impurity concentration of the first low-concentration region26ais, for example, 4×1014cm−3to 1×1019cm−3. Typically, the n-type impurity concentration is, for example, 2×1016cm−3. An n-type impurity concentration of the high-concentration region26bis higher than an n-type impurity concentration of the first low-concentration region26a. The n-type impurity concentration of the high-concentration region26bis, for example, 2×1017cm−3to 1×1019cm−3. The n-type impurity concentration is preferably 5×1017cm−3to 5×1018cm−3and more preferably 8×1017cm−3to 3×1018cm−3. Typically, the n-type impurity concentration is, for example, 1×1018cm−3. If the concentration is low, the ability to diffuse the current is lowered and if the concentration is high, the breakdown voltage is not obtained. If the concentration falls below the above range, the on-resistance may excessively increase. In addition, if the concentration exceeds the above range, sufficient current suppression may not be performed at the time of load short circuiting.

In this embodiment, the case where inclination angles between the side surfaces of the first trench22aand the second trench22band the surface of the silicon carbide layer10are 90° has been described as an example. However, the inclination angles are not necessarily limited to 90°.

For example, in the case where the second direction is the direction of the a axis, from the viewpoint of maximizing the mobility of the electrons, the side surfaces of the first trench22aand the second trench22b, where the channel regions are formed are preferably matched with the a face, that is, the (11-20) face. Therefore, for example, if an off-angle of the first plane with respect to the (0001) face is set to a, the inclination angle of the side surface of the trench is preferably set to 90°-α. At this time, because the other side surface forming a pair is not matched with the (11-20) face, the non-matched side surface is not used as the channel region.

Preferably, the first trench22aand the second trench22bare formed so that the first direction in which the first trench22aand the second trench22bextend is the a axis and the inclination angle of the side surface of the trench is 90°. The side surface of the trench is matched with the m face, that is, the (1-100) face and the mobility of the electrons is improved. At this time, both the two side faces forming a pair are matched with the (1-100) face.

From the viewpoint of maximizing the density of the trenches and reducing the on-resistance per unit area, the inclination angles between the side surfaces of the first trench22aand the second trench22band the surface of the silicon carbide layer10are preferably 90°. In the case of considering a structure of a MOSFET with a channel region on one side of a trench structure and a breakdown voltage structure and a diode on the opposite side as a unit, a structure formed at an angle of 90° becomes the smallest unit. Therefore, the density of the trenches can be maximized.

Generally speaking, the off-angle is provided in a substrate to realize epitaxial growth. However, by forming a plane having a side surface of 90° in a direction vertical to the off-angle, forming one side surface as a channel region, and causing a side surface forming a pair to have a breakdown voltage structure, a PiN built-in MOSFET with a high trench density can be formed.

In this embodiment, the case where the film thickness of the first gate insulating layer16aat both side surfaces of the first trench22ais the same has been described as an example. However, for example, the film thickness of the first gate insulating layer16aat the side surface contacting the first diode region32acan be larger than the film thickness of the first gate insulating layer16aat the side surface contacting the body region28. At this time, the width of the first diode region32acan be decreased, thereby decreasing the width of the unit. Finally, the trench density is improved. Likewise, for example, the film thickness of the second gate insulating layer16bat side surface contacting the second diode region32bcan be larger than the film thickness of the second gate insulating layer16bat the side surface contacting the body region28. At this time, the width of the second diode region32bcan be decreased, thereby decreasing the width of the unit. Finally, the trench density is improved.

According to the MOSFET100according to this embodiment, the heat generated at the time of the load short circuiting is suppressed and the short circuit tolerance is improved. In addition, a breakdown voltage of the gate insulating layer is improved and reliability is improved.

Second Embodiment

A semiconductor device according to this embodiment is the same as the semiconductor device according to the first embodiment, except that a drift region has, between the second n-type region and a body region, a third n-type region with an n-type impurity concentration lower than that of a second n-type region. Hereinafter, description of contents overlapping with those of the first embodiment will be omitted.

FIG. 7is a schematic cross-sectional view of the semiconductor device according to this embodiment. The semiconductor device according to this embodiment is a trench gate type vertical MOSFET200using silicon carbide.

The second low-concentration region26cis provided between the high-concentration region26band a body region28. An n-type impurity concentration of the second low-concentration region26cis lower than an n-type impurity concentration of the high-concentration region26b. The n-type impurity concentration of the second low-concentration region26cis, for example, 4×1014cm−3to 1×1019cm−3. Typically, the n-type impurity concentration is, for example, 2×1016cm−3.

Since the MOSFET200includes the second low-concentration region26c, a threshold voltage can be increased.

According to the MOSFET200according to this embodiment, a short circuit tolerance and reliability are improved, similar to the first embodiment. In addition, the threshold voltage can be increased.

Third Embodiment

A semiconductor device according to this embodiment is the same as the semiconductor device according to the first embodiment, except that a body region has a first p-type region and a second p-type region located between the first p-type region and a drift region and having a p-type impurity concentration higher than that of the first p-type region. Hereinafter, description of contents overlapping with those of the first embodiment will be omitted.

FIG. 8is a schematic cross-sectional view of the semiconductor device according to this embodiment. The semiconductor device according to this embodiment is a trench gate type vertical MOSFET300using silicon carbide.

The high-concentration region28bis located between the low-concentration region28aand a drift region26. A p-type impurity concentration of the high-concentration region28bis higher than a p-type impurity concentration of the low-concentration region28a.

Since the MOSFET300includes the high-concentration region28b, a threshold voltage can be increased.

According to the MOSFET300according to this embodiment, a short circuit tolerance and reliability are improved, similar to the first embodiment. In addition, the threshold voltage can be increased.

Fourth Embodiment

A semiconductor device according to this embodiment is the same as the semiconductor device according to the first embodiment, except that the semiconductor device further includes a p-type fifth silicon carbide region located in a drift region, located between a first gate electrode and a second plane, and extending in a first direction, a p-type sixth silicon carbide region located in the drift region, located between a second source region and the second plane, located between a third silicon carbide region and the second plane, and extending in the first direction, and a p-type seventh silicon carbide region located in the drift region, located between a second gate electrode and the second plane, and extending in the first direction. Hereinafter, description of contents overlapping with those of the first embodiment will be omitted.

FIG. 9is a schematic cross-sectional view of the semiconductor device according to this embodiment. The semiconductor device according to this embodiment is a trench gate type vertical MOSFET400using silicon carbide.

FIG. 10is a schematic plan view of the semiconductor device according to this embodiment.FIG. 10is a plan view of a plane Py ofFIG. 9.

The MOSFET400includes a p-type first intermediate region36a(fifth silicon carbide region) located in a drift region26, a p-type second intermediate region36b(sixth silicon carbide region), and a p-type third intermediate region36c(seventh silicon carbide region).

The first intermediate region36a, the second intermediate region36b, and the third intermediate region36cextend in the first direction. The first intermediate region36a, the second intermediate region36b, and the third intermediate region36care separated from each other.

The first intermediate region36ais located between a first gate electrode18aand a back surface of a silicon carbide layer10. The first intermediate region36ais located between a first current limiting region34aand the back surface of the silicon carbide layer10.

The second intermediate region36bis located between a second source region30band the back surface of the silicon carbide layer10. The second intermediate region36bis located between the first current limiting region34aand the back surface of the silicon carbide layer10.

The third intermediate region36cis located between a second gate electrode18band the back surface of the silicon carbide layer10. The third intermediate region36cis located between a second current limiting region34band the back surface of the silicon carbide layer10.

The first intermediate region36a, the second intermediate region36b, and the third intermediate region36care fixed to the same source potential as a source electrode12, for example.

A p-type impurity concentration of each of the first intermediate region36a, the second intermediate region36b, and the third intermediate region36cis, for example, 1×1017cm−3to 1×1020cm−3. The p-type impurity concentration is preferably 5×1017cm−3to 5×1019cm−3and more preferably 1×1010cm−3to 1×1019cm−3. If the p-type impurity concentration is low, a large region is necessary. If the p-type impurity concentration is high, structural defects are likely to occur even when a method of forming the first intermediate region36a, the second intermediate region36b, and the third intermediate region36cis epitaxial growth or ion implantation. Typically, the p-type impurity concentration is, for example, 4×1018cm−3.

In the MOSFET400, an on-current from a channel region of a side surface of a second trench22bflows through the drift region26between the second intermediate region36band the third intermediate region36cduring an on-operation. In addition, a forward current flowing from a first diode region32ato a drain electrode14flows through the drift region26between the first intermediate region36aand the second intermediate region36bduring a reflux operation in which a reflux current flows.

According to the MOSFET400according to this embodiment, an n-type impurity concentration of the drift region26can be increased without sacrificing a breakdown voltage when a reverse bias is applied. In the case of this embodiment, the first intermediate region36a, the second intermediate region36b, and the third intermediate region36care inserted into almost an intermediate portion of a first low-concentration region26a, so that the n-type impurity concentration of the drift region26can be almost doubled. Therefore, on-resistance can be further decreased. The on-resistance can be decreased to almost half. For example, if K of the same intermediate regions are inserted (K is an integer) and are divided by K, a concentration can be increased by K times and the on-resistance can be decreased to 1/K.

In addition, in this embodiment, a channel region is formed at only one side of the first trench22aand the second trench22b. Therefore, as compared with the case where channel regions are formed at both sides of the trenches, it is easy to dispose the first intermediate region36a, the second intermediate region36b, and the third intermediate region36cso that a path of an on-current and a path of a forward current of a diode are not disturbed and concentration of the on-current can be avoided.

According to the MOSFET400according to this embodiment, a short circuit tolerance and reliability are improved, similar to the first embodiment. In addition, the on-resistance can be decreased.

Fifth Embodiment

A semiconductor device according to this embodiment is the same as the semiconductor device according to the fourth embodiment, except that the semiconductor device further includes a p-type eighth silicon carbide region located in a drift region, extending in a second direction parallel to a first plane and vertical to a first direction, and contacting a fifth silicon carbide region, a sixth silicon carbide region, and a seventh silicon carbide region; and a p-type ninth silicon carbide region located in the drift region, extending in the second direction, contacting the fifth silicon carbide region, the sixth silicon carbide region, and the seventh silicon carbide region, and separated from the eighth silicon carbide region. Hereinafter, description of contents overlapping with those of the fourth embodiment will be omitted.

FIG. 11is a schematic plan view of the semiconductor device according to this embodiment. The semiconductor device according to this embodiment is a trench gate type vertical MOSFET500using silicon carbide.FIG. 11is a plan view of a plane corresponding to a plane Py ofFIG. 9.

The MOSFET500includes a p-type first intermediate region36a(fifth silicon carbide region) located in a drift region26, a p-type second intermediate region36b(sixth silicon carbide region), a p-type third intermediate region36c(seventh silicon carbide region), a p-type fourth intermediate region36d(eighth silicon carbide region), and a p-type fifth intermediate region36e(ninth silicon carbide region).

The fourth intermediate region36dand the fifth intermediate region36eextend in the second direction parallel to a surface of a silicon carbide layer10and vertical to the first direction. The fourth intermediate region36dand the fifth intermediate region36eare separated from each other.

The fourth intermediate region36dand the fifth intermediate region36econtact the first intermediate region36a, the second intermediate region36b, and the third intermediate region36c. The fourth intermediate region36dand the fifth intermediate region36ecross the first intermediate region36a, the second intermediate region36b, and the third intermediate region36c.

In the drift region26, the first intermediate region36a, the second intermediate region36b, the third intermediate region36c, the fourth intermediate region36d, and the fifth intermediate region36eform a mesh-like p-type region.

A p-type impurity concentration of each of the first intermediate region36a, the second intermediate region36b, the third intermediate region36c, the fourth intermediate region36d, and the fifth intermediate region36eis, for example, 1×1017cm−3to 1×1020cm−3. The p-type impurity concentration is preferably 5×1017cm−3to 5×1019cm−3and more preferably 1×1018cm−3to 1×1019cm−3. If the p-type impurity concentration is low, a large region is necessary. If the p-type impurity concentration is high, structural defects are likely to occur even when a method of forming the first intermediate region36a, the second intermediate region36b, the third intermediate region36c, the fourth intermediate region36d, and the fifth intermediate region36eis epitaxial growth or ion implantation. Typically, the p-type impurity concentration is, for example, 4×1018cm−3.

According to the MOSFET500according to this embodiment, an n-type impurity concentration of the drift region26can be increased without sacrificing a breakdown voltage when a reverse bias is applied. In the case of this embodiment, the first intermediate region36a, the second intermediate region36b, the third intermediate region36c, the fourth intermediate region36d, and the fifth intermediate region36eare inserted into almost an intermediate portion of a first low-concentration region26a, so that the n-type impurity concentration of the drift region26can be almost doubled. Therefore, on-resistance can be further decreased. The on-resistance can be decreased to almost half. For example, if K of the same intermediate regions are inserted (K is an integer) and are divided by K, a concentration can be increased by K times and the on-resistance can be decreased to 1/K.

According to the MOSFET500according to this embodiment, a short circuit tolerance and reliability are improved, similar to the first embodiment. In addition, the on-resistance can be decreased.

Sixth Embodiment

A semiconductor device according to this embodiment is different from the semiconductor device according to the first embodiment in that the semiconductor device further includes a p-type tenth silicon carbide region which is located between a first silicon carbide region and a body region, is located between the first silicon carbide region and a second source region, contacts a source electrode, has a fifth n-type portion to be a part of a drift region between the first silicon carbide region and the p-type tenth silicon carbide region, a distance between a second plane and the p-type tenth silicon carbide region being smaller than a distance between the second plane and a first gate electrode, and has p-type impurity concentration higher than that of the body region and the fifth n-type portion to be the part of the drift region contacts the source electrode. Hereinafter, description of contents overlapping with those of the first embodiment will be omitted.

FIG. 12is a schematic cross-sectional view of the semiconductor device according to this embodiment. The semiconductor device according to this embodiment is a trench gate type vertical MOSFET600using silicon carbide. The MOSFET600includes a merged PiN Schottky (MPS) diode.

The third diode region32cis located between the drift region26and a body region28. The third diode region32cis located between a first diode region32aand a second source region30b. The third diode region32ccontacts a source electrode12.

A distance (d7ofFIG. 12) between a back surface of a silicon carbide layer10and the third diode region32cis smaller than a distance (d2ofFIG. 12) between the back surface of the silicon carbide layer10and a first gate electrode18a. Depths of the third diode region32cand the first diode region32aare substantially the same. The depth of the third diode region32cis larger than a depth of an end portion of a first gate insulating layer16aat the back surface side of the silicon carbide layer10.

A p-type impurity concentration of the third diode region32cis higher than a p-type impurity concentration of the body region28. The p-type impurity concentration is, for example, 1×1018cm−3to 1×1021cm−3. Typically, the p-type impurity concentration is, for example, 1×1019cm−3.

The JFET region26uis provided between the third diode region32cand the first diode region32a. The JFET region26uis a part of the drift region26. The JFET region26ucontacts the source electrode12. A junction between the JFET region26uand the source electrode12is a Schottky junction.

The first diode region32a, the third diode region32c, the JFET region26u, the source electrode12, and the drain electrode14configure the MPS diode. The source electrode12functions as an anode electrode of the MPS diode and the drain electrode14functions as a cathode electrode of the MPS diode. The MPS diode functions as a freewheel diode.

Since the MOSFET600includes the MPS diode as the freewheel diode, a high-speed and low-loss operation is enabled.

According to the MOSFET600according to this embodiment, a short circuit tolerance and reliability are improved, similar to the first embodiment. In addition, the high-speed and low-loss operation is enabled.

Seventh Embodiment

A semiconductor device according to this embodiment is the same as the semiconductor device according to the sixth embodiment, except that the semiconductor device further includes a p-type fifth silicon carbide region which is located in a drift region, is located between a first gate electrode and a second plane, and extends in a first direction, a p-type sixth silicon carbide region which is located in the drift region, is located between a second source region and the second plane, is located between a third silicon carbide region and the second plane, and extends in the first direction, and a p-type seventh silicon carbide region which is located in the drift region, is located between a second gate electrode and the second plane, and extends in the first direction. Hereinafter, description of contents overlapping with those of the first embodiment will be omitted.

FIG. 13is a schematic cross-sectional view of the semiconductor device according to this embodiment. The semiconductor device according to this embodiment is a trench gate type vertical MOSFET700using silicon carbide. The MOSFET700includes an MPS diode.

The MOSFET700includes a p-type first intermediate region36a(fifth silicon carbide region) located in a drift region26, a p-type second intermediate region36b(sixth silicon carbide region), and a p-type third intermediate region36c(seventh silicon carbide region).

The first intermediate region36a, the second intermediate region36b, and the third intermediate region36cextend in the first direction. The first intermediate region36a, the second intermediate region36b, and the third intermediate region36care separated from each other.

The first intermediate region36ais located between a first gate electrode18aand a back surface of a silicon carbide layer10. The first intermediate region36ais located between a first current limiting region34aand the back surface of the silicon carbide layer10.

The second intermediate region36bis located between a third diode region32cand the back surface of the silicon carbide layer10.

The third intermediate region36cis located between a second gate electrode18band the back surface of the silicon carbide layer10. The third intermediate region36cis located between a second current limiting region34band the back surface of the silicon carbide layer10.

The first intermediate region36a, the second intermediate region36b, and the third intermediate region36care fixed to the same source potential as a source electrode12, for example.

A p-type impurity concentration of each of the first intermediate region36a, the second intermediate region36b, and the third intermediate region36cis, for example, 1×1017cm−3to 1×1020cm−3. The p-type impurity concentration is preferably 5×1017cm−3to 5×1019cm−3and more preferably 1×1018cm−3to 1×1019cm−3. If the p-type impurity concentration is low, a large region is necessary. If the p-type impurity concentration is high, structural defects are likely to occur even when a method of forming the first intermediate region36a, the second intermediate region36b, and the third intermediate region36cis epitaxial growth or ion implantation. Typically, the p-type impurity concentration is 4×1018cm−3.

According to the MOSFET700according to this embodiment, an n-type impurity concentration of the drift region26can be increased without sacrificing a breakdown voltage when a reverse bias is applied. In the case of this embodiment, the first intermediate region36a, the second intermediate region36b, and the third intermediate region36care inserted into almost an intermediate portion of a first low-concentration region26a, so that the n-type impurity concentration of the drift region26can be almost doubled. Therefore, on-resistance can be further decreased. The on-resistance can be decreased to almost half. For example, if K of the same intermediate regions are inserted (K is an integer) and are divided by K, a concentration can be increased by K times and the on-resistance can be decreased to 1/K.

According to the MOSFET700according to this embodiment, a short circuit tolerance and reliability are improved, similar to the sixth embodiment. In addition, a high-speed and low-loss operation is enabled. In addition, the on-resistance can be decreased.

Eighth Embodiment

A semiconductor device according to this embodiment includes: a silicon carbide layer having a first plane and a second plane; a source electrode contacting the first plane; a drain electrode contacting the second plane; a first gate electrode located between the source electrode and the drain electrode and extending in a first direction parallel to the first plane; a second gate electrode located between the source electrode and the drain electrode and extending in the first direction parallel to the first plane; an n-type drift region located in the silicon carbide layer; a p-type body region located in the silicon carbide layer and located between the drift region and the first plane; an n-type first source region located in the silicon carbide layer, located between the body region and the first plane, and contacting the source electrode; an n-type second source region located in the silicon carbide layer, located between the body region and the first plane, and contacting the source electrode, the first gate electrode being located between the first source region and the second source region; a p-type first silicon carbide region located in the silicon carbide layer, located between the drift region and the first plane, contacting the source electrode, a distance between the second plane and the first silicon carbide region being smaller than a distance between the second plane and the first gate electrode, the first gate electrode being located between the first source region and the first silicon carbide region, located between the first gate electrode and the body region, and having a p-type impurity concentration higher than a p-type impurity concentration of the body region; a p-type second silicon carbide region located in the silicon carbide layer, located between the drift region and the first plane, contacting the source electrode, a distance between the second plane and the second silicon carbide region being smaller than a distance between the second plane and the second gate electrode, the second gate electrode being located between the second source region and the second silicon carbide region, located between the second gate electrode and the body region, and having a p-type impurity concentration higher than the p-type impurity concentration of the body region; a first gate insulating layer located between the first gate electrode and the drift region, between the first gate electrode and the body region, between the first gate electrode and the first silicon carbide region, and between the first gate electrode and the first source region; a second gate insulating layer located between the second gate electrode and the drift region, between the second gate electrode and the body region, between the second gate electrode and the second silicon carbide region, and between the second gate electrode and the second source region; a p-type third silicon carbide region located in the silicon carbide layer, extending in a second direction parallel to the first plane and vertical to the first direction, located between the second plane and the first gate electrode, located between the second plane and the second gate electrode, and contacting the first silicon carbide region and the second silicon carbide region, a first n-type portion to be a part of the drift region being located between the first gate insulating layer and the third silicon carbide region, a second n-type portion to be a part of the drift region being located between the second gate insulating layer and the third silicon carbide region; and a p-type fourth silicon carbide region located in the silicon carbide layer, extending in the second direction, located between the second plane and the first gate electrode, located between the second plane and the second gate electrode, contacting the first silicon carbide region and the second silicon carbide region, a third n-type portion to be a part of the drift region being located between the first gate insulating layer and the fourth silicon carbide region, a fourth n-type portion to be a part of the drift region being located between the second gate insulating layer and the fourth silicon carbide region, and separated from the third silicon carbide region. The semiconductor device according to this embodiment is different from the semiconductor device according to the first embodiment in that the extension direction of the third silicon carbide region and the fourth silicon carbide region is not the first direction but the second direction. Hereinafter, description of contents overlapping with those of the first embodiment will be omitted.

FIG. 14is a schematic cross-sectional view of the semiconductor device according to this embodiment. The semiconductor device according to this embodiment is a trench gate type vertical MOSFET800using silicon carbide.

FIG. 15is a schematic plan view of the semiconductor device according to this embodiment.FIG. 15is a plan view of a plane Px ofFIG. 14.FIG. 14is a cross-sectional view taken along the line AA′ ofFIG. 15.

FIGS. 16 and 17are schematic cross-sectional views of the semiconductor device according to this embodiment.FIG. 16is a cross-sectional view taken along the line BB′ ofFIG. 15.FIG. 17is a cross-sectional view taken along the line CC′ ofFIG. 15.

In a silicon carbide layer10of the MOSFET800, a p+-type first current limiting region34a(third silicon carbide region) and a p+-type second current limiting region34b(fourth silicon carbide region) are located.

The first current limiting region34aand the second current limiting region34bextend in the second direction orthogonal to the first direction. The first current limiting region34aand the second current limiting region34bare provided in a direction orthogonal to a first gate electrode18aand a second gate electrode18b. The first current limiting region34aand the second current limiting region34bcontact a first diode region32aand a second diode region32b.

The first field alleviation portion26wis located between the first current limiting region34aand the first gate electrode18a. The first field alleviation portion26wis located between the first current limiting region34aand the first gate insulating layer16a. The first field alleviation portion26wis a part of the drift region26. The first field alleviation portion26wis located in the n-type high-concentration region26b.

The second field alleviation portion26xis located between the first current limiting region34aand the second gate electrode18b. The second field alleviation portion26xis located between the first current limiting region34aand a second gate insulating layer16b. The second field alleviation portion26xis a part of the drift region26. The second field alleviation portion26xis located in the n-type high-concentration region26b.

The third field alleviation portion26yis located between the second current limiting region34band the first gate electrode18a. The third field alleviation portion26yis located between the second current limiting region34band the first gate insulating layer16a. The third field alleviation portion26yis a part of the drift region26. The third field alleviation portion26yis located in the n-type high-concentration region26b.

The fourth field alleviation portion26zis located between the second current limiting region34band the second gate electrode18b. The fourth field alleviation portion26zis located between the second current limiting region34band the second gate insulating layer16b. The fourth field alleviation portion26zis a part of the drift region26. The fourth field alleviation portion26zis located in the n-type high-concentration region26b.

The first current limiting region34aand the second current limiting region34bare provided in a direction orthogonal to the first gate electrode18aand the second gate electrode18b. Therefore, even if misalignment occurs between the first current limiting region34aand the second current limiting region34band the first gate electrode18aand the second gate electrode18b, at the time of manufacturing the MOSFET800, the influence on characteristics of the MOSFET800is small. Therefore, a characteristic variation caused by the misalignment at the time of manufacturing can be suppressed.

According to the MOSFET800according to this embodiment, similar to the first embodiment, heat generation at the time of load short circuiting is suppressed and a short circuit tolerance is improved. In addition, a breakdown voltage of the gate insulating layer is improved and reliability is improved. In addition, the characteristic variation caused by the misalignment at the time of manufacturing can be suppressed.

Ninth Embodiment

A drive device according to this embodiment is a drive device including the semiconductor device according to the first embodiment.

FIG. 18is a schematic diagram of the drive device according to this embodiment. A drive device1000includes a motor140and an inverter circuit150.

The inverter circuit150is composed of three semiconductor modules150a,150b, and150cusing the MOSFET100according to the first embodiment as a switching element. By connecting the three semiconductor modules150a,150b, and150cin parallel, the three-phase inverter circuit150having three AC voltage output terminals U, V, and W is realized. The motor140is driven by an AC voltage output from the inverter circuit150.

According to this embodiment, characteristics of the inverter circuit150and the drive device1000are improved by including the MOSFET100having improved characteristics.

Tenth Embodiment

A vehicle according to this embodiment is a vehicle including the semiconductor device according to the first embodiment.

FIG. 19is a schematic diagram of the vehicle according to this embodiment. A vehicle1100according to this embodiment is a railroad vehicle. The vehicle1100includes motors140and an inverter circuit150.

The inverter circuit150is composed of three semiconductor modules using the MOSFET100according to the first embodiment as a switching element. By connecting the three semiconductor modules in parallel, the three-phase inverter circuit150having three AC voltage output terminals U, V, and W is realized. The motor140is driven by an AC voltage output from the inverter circuit150. Wheels90of the vehicle1100are rotated by the motor140.

According to this embodiment, characteristics of the vehicle1100are improved by including the MOSFET100having improved characteristics.

Eleventh Embodiment

A vehicle according to this embodiment is a vehicle including the semiconductor device according to the first embodiment.

FIG. 20is a schematic diagram of the vehicle according to this embodiment. A vehicle1200according to this embodiment is an automobile. The vehicle1200includes a motor140and an inverter circuit150.

The inverter circuit150is composed of three semiconductor modules using the MOSFET100according to the first embodiment as a switching element. By connecting the three semiconductor modules in parallel, the three-phase inverter circuit150having three AC voltage output terminals U, V, and W is realized.

The motor140is driven by an AC voltage output from the inverter circuit150. Wheels90of the vehicle1200are rotated by the motor140.

According to this embodiment, characteristics of the vehicle1200are improved by including the MOSFET100having improved characteristics.

Twelfth Embodiment

An elevator according to this embodiment is an elevator including the semiconductor device according to the first embodiment.

FIG. 21is a schematic diagram of the elevator according to this embodiment. An elevator1300according to this embodiment includes a car610, a counter weight612, a wire rope614, a winding machine616, a motor140, and an inverter circuit150.

The inverter circuit150is composed of three semiconductor modules using the MOSFET100according to the first embodiment as a switching element. By connecting the three semiconductor modules in parallel, the three-phase inverter circuit150having three AC voltage output terminals U, V, and W is realized.

The motor140is driven by an AC voltage output from the inverter circuit150. The winding machine616is rotated by the motor140and the car610is elevated.

According to this embodiment, characteristics of the elevator1300are improved by including the MOSFET100having improved characteristics.

In the embodiments, the case where 4H—SiC is used as a crystal structure of silicon carbide has been described as an example. However, the present disclosure can be applied to silicon carbide of other crystal structure such as 6H—SiC and 3C—SiC.

In addition, in the tenth to twelfth embodiments, the case where the semiconductor device according to the first embodiment is included has been described as an example. However, the semiconductor device according to any one of the first to eighth embodiments can be applied.

In addition, in the tenth to twelfth embodiments, the case where the semiconductor device according to the present disclosure is applied to the vehicle or the elevator has been described as an example. However, the semiconductor device according to the present disclosure can be applied to a power conditioner of a photovoltaic power generation system and the like.

While certain embodiments have been described, these embodiments have been presented by way of example only and are not intended to limit the range of the invention. These novel embodiments may be embodied in a variety of other forms and various omissions, substitutions, and changes can be made without departing from the scope of the invention. For example, the components according to one embodiment may be replaced or changed by or to the components according to another embodiment. These embodiments or modifications are included in the range or the scope of the invention and are included in a range of the accompanying claims and their equivalents.