Embodiments relate to design-based weighting for logic built-in self-test (LBIST). An aspect includes an integrated circuit development system for implementing design-based weighting for LBIST. The system includes a memory system to create an integrated circuit layout. A processing circuit is coupled to the memory system. The processing circuit is configured to execute integrated circuit development tools to perform a method. The method includes analyzing, by the processing circuit, a plurality of integrated circuit design organizational units to determine preferred weightings of the integrated circuit design organizational units that provide a highest level of failure coverage when applied to a random pattern generator. Based on determining the preferred weightings, the processing circuit creates an integrated circuit layout that includes a plurality of weighted test paths to respectively apply the preferred weightings to the integrated circuit design organizational units. The integrated circuit layout is incorporated in a device under test.

BACKGROUND

The present invention relates generally to integrated circuit testing, and more specifically, to design-based weighting for logic built-in self-test (LBIST).

LBIST is used to test integrated circuit logic of high-end servers and computers. LBIST is used at all levels of test including: integrated circuit, multi-chip module (MCM), and system levels. Conceptually, the LBIST approach is based on the realization that much of a circuit tester's electronics is semi-conductor based, just like the devices under test, and that many of the challenges and limitations of testing lie in the interface to the Device Under Test (DUT). The LBIST approach can be described as an attempt to move many of the already semiconductor-based test equipment functions into the DUT and eliminate complex interfacing. One of the major advantages LBIST has over other means of testing logic is that operation of the test is self-contained. All of the circuitry required to execute the test at-speed is contained within the integrated circuit. Very limited external controls are needed, so LBIST can be run at all levels of packaging (e.g., wafer, module and system) without requiring expensive external test equipment.

LBIST utilizes what is commonly referred to as Self-Test Using Multiple Signal Registers and Pseudo-Random Pattern Generators (STUMPS) architecture. The major components of LBIST include: a pseudo-random pattern generator (PRPG) used to generate the test patterns; a multiple input signature register (MISR) to compress the test results; and the self-test control macro (STCM) that is used to apply clocks and controls to the PRPG, MISR and system logic to perform the test. The PRPG applies test data to the system logic via multiple parallel scan chains, which are connected between the PRPG and MISR.

One of the limitations of LBIST is the maximum achievable test coverage. Because the PRPG is implemented using a linear feedback shift register (LFSR) that generates random patterns (i.e., 50% chance of being a 0 or a 1), certain random resistant structures are difficult, if not impossible, to test. Examples include very wide AND gates or OR gates where the probability of all inputs being a 1 in the case of an AND gate or all inputs being a 0 in the case of an OR gate is very small. Typically, LBIST test coverage peaks at around 96%. The remaining faults must be tested by some other means of logic test, either weighted random pattern test (WRPT), deterministic test, or a combination of both.

Weighting is a technique where patterns can be biased towards a 0 or 1 state by ANDing or ORing multiple bits of an LFSR together. Instead of a 50% chance of a 0 or a 1, the odds of a 0 or 1 are weighted to increase the probability of one or the other occurring. For example, if 3 random bits are ORed together, the resultant output has a 7/8 chance of being a 1. Conversely, if 4 random bits are ANDed together, the output has a 1/16 chance of being a 1. This weighting technique can be used to test random resistant structures such as large AND or OR structures.

In contemporary designs, many LBIST variations are used in manufacturing tests employing different weights. As one example, U.S. Pat. No. 6,671,838, “Method and Apparatus for Programmable LBIST Channel Weighting” filed Sep. 27, 2000, which is incorporated herein by reference, teaches a built-in self-test (BIST) method and apparatus for testing logic circuits on an integrated circuit, where a random resistant fault analysis (RRFA) program is used to determine weighting requirements on a per channel basis. In U.S. Pat. No. 6,671,838, weighting requirements from the RRFA program are applied to random test pattern data resulting in weighted test pattern data that is programmably applied to a scan chain.

SUMMARY

An aspect includes an integrated circuit development system for implementing design-based weighting for LBIST. The system includes a memory system with integrated circuit development tools and design files to create an integrated circuit layout for a device under test. A processing circuit is coupled to the memory system. The processing circuit is configured to execute the integrated circuit development tools to perform a method. The method includes analyzing, by the processing circuit, a plurality of integrated circuit design organizational units to determine preferred weightings of the integrated circuit design organizational units that provide a highest level of failure coverage when applied to a random pattern generator of the integrated circuit development tools. Based on determining the preferred weightings, the processing circuit creates an integrated circuit layout that includes a plurality of weighted test paths to respectively apply the preferred weightings to the integrated circuit design organizational units. The integrated circuit layout is stored in the design files, and the integrated circuit layout is incorporated in a device under test.

DETAILED DESCRIPTION

In exemplary embodiments, design-based weighting for logic built-in self-test (LBIST) is provided, where preferred weightings of the integrated circuit design organizational units are determined and an integrated circuit layout is created based on the preferred weightings. Rather than analyzing a design after the integrated circuit layout is finalized, embodiments perform analysis during the design process and ensure that preferred weightings are included. Where the integrated circuit design organizational units are macros, the macros can be assigned to scan chains or LBIST channels that include the preferred weighting of each respective macro. If the integrated circuit design organizational units are Self-Test Using Multiple Signal Registers and Pseudo-Random Pattern Generators (STUMPS) channels, the analyzing can be performed on a STUMPS channel basis, and the integrated circuit layout is updated to include the preferred weightings of each STUMPS channel.

In one embodiment, design for test (DFT) macro analysis is used to determine the preferred weightings per macro during an integrated circuit design process. The macros can be assigned to STUMPS channels that enable each macro to receive its preferred weighting as test input based on the preferred weightings determined during the DFT macro analysis. The preferred weightings represent weightings that provide a highest level of test coverage. By first learning the preferred weightings and then establishing an integrated circuit layout that enables routing of the preferred weightings to respective integrated circuit design organizational units, LBIST patterns can achieve a higher percentage of test coverage. The preferred weightings need not be limited to only a few options, such as 1/8 weighting and 7/8 weighting, but can include arbitrary weightings that provide the highest level of test coverage, such as a 1/16 weighting, 15/16 weighting, 1/32 weighting, 31/32 weighting, and so forth.

In another embodiment, the DFT analysis is performed after the STUMPS channels are assigned. In this case, the DFT analysis is done on the existing STUMPS channels, and the preferred weightings are established based on this data. The preferred weightings can be hard coded for each STUMPS channel or provided as a selectable input, e.g. as a multiplexer input, where other non-weighted inputs or non-preferred weighted inputs can also be made available for testing.

In a further embodiment, after determining preferred weightings for a design, a complete LBIST channel can be assigned for each unique instance of the preferred weightings. Integrated circuit design organizational units, such as macros, can be assigned to a corresponding LBIST channel based on the preferred weightings of the respective macros.

Turning now toFIG. 1, a system100is generally shown that includes an integrated circuit (IC) development system102configured to incorporate an integrated circuit layout into a device under test (DUT)112. The IC development system102can fabricate the DUT112as an integrated circuit chip. The DUT112can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the DUT112can be mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). The DUT112may also be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor. An exemplary design flow for developing the DUT112is described in greater detail herein with respect toFIG. 9.

Continuing with the description ofFIG. 1, the IC development system102includes a processing circuit104and a memory system106. The processing circuit104can be any type of processor or microcontroller, including multiple instances thereof, that is configurable to execute processes further described herein, where the memory system106is an example of a tangible storage medium. The memory system106can include IC development tools108and design files110. The IC development tools108may be partitioned as one or more computer program products. For example, the IC development tools108can include a DFT analyzer114and a random pattern generator116among other executable applications (not depicted). The design files110can include definition files for a plurality of integrated circuit design organizational units118, such as STUMPS channels120and macros122. The STUMPS channels120can include the macros122organized in scan chains. The macros122define logic circuits that can include latches and logic blocks (e.g., logic gates) organized to implement a particular function, such as an arithmetic logic unit macro, an error checking macro, a decoding macro, etc.

In an exemplary embodiment, the processing circuit104is coupled to the memory system106, and the processing circuit104is configured to execute the IC development tools108to analyze a plurality of integrated circuit design organizational units118defined in the design files110to determine preferred weightings of the integrated circuit design organizational units118that provide a highest level of failure coverage when applied to the random pattern generator116of the IC development tools108. For example, the DFT analyzer114can iterate over a large range of possible weightings to identify the preferred weightings of the integrated circuit design organizational units118, e.g., 1/2, 1/4, 3/4, 1/8, 7/8, 1/16, 15/16, 1/32, 31/32, 1/64, 63/64, 1/128, 127/128, 1/256, 255/256, and so forth. Based on determining the preferred weightings, the processing circuit104creates an integrated circuit layout124that includes a plurality of weighted test paths to respectively apply the preferred weightings to the integrated circuit design organizational units118. The integrated circuit layout124can be stored in the design files110, and at least one of the design files110associated with the integrated circuit layout124can be modified to annotate the preferred weightings of the integrated circuit design organizational units118in the design files110. The integrated circuit layout124is incorporated in the DUT112, for example, as a design structure as described herein with respect toFIG. 9.

FIG. 2depicts a design structure200in accordance with an embodiment. The design structure200illustrates a portion of the DUT112ofFIG. 1as a block diagram. The design structure200ofFIG. 2, includes a pseudo-random pattern generator (PRPG)202including a linear feedback shift register (LFSR)204that generates random patterns (i.e., 50% chance of being a 0 or a 1) and distributes the random patterns via a spreading network206to a plurality of scan chains208a,208b, . . . ,208m,208n. The scan chains208a-208nprovide test paths through partial or complete instances of the macros122ofFIG. 1as embodied in the DUT112ofFIG. 1. A multiple input signature register (MISR)210compresses the test results to confirm that failures are detected in a summarized format. Although several examples provided herein refer to use of a MISR, other result compression structures known in the art can be substituted in various embodiments, such as an XOR compression register. Exemplary embodiments include incorporating preferred weightings for the scan chains208a-208ninto the design structure200to provide a highest level of fault coverage over a shortest amount of time. The preferred weightings may be integrated into the spreading network206such that each of the scan chains208a-208nreceives its preferred weighting.

FIG. 3depicts another design structure300in accordance with an embodiment. In the example ofFIG. 3, the design structure300, which may be implemented in the DUT112ofFIG. 1, includes an LFSR304, a spreading network306, and a plurality of scan chains308a-308n. A plurality of multiplexers312a-312nare incorporated in the spreading network306to establish different weightings for scan chains308a-308n. Each combination of a multiplexer312and a scan chain308may be referred to as a STUMPS channel314. Accordingly, the example ofFIG. 3includes STUMPS channels314a-314n. Each of the multiplexers312has a number of multiplexer inputs316.

As depicted inFIG. 3, multiplexer312aincludes four multiplexer inputs316aas a 1/8 weighted input, a 7/8 weighted input, a non-weighted input, and a preferred weighting input. The 1/8 weighted input of the multiplexer inputs316amay be generated by an AND-gate318a, as only one of eight possible input combinations results in a logical ‘1’. The 7/8 weighted input of the multiplexer inputs316amay be generated by an OR-gate320a, as seven of eight possible input combinations result in a logical ‘1’. A direct link322abetween the LFSR304and the multiplexer312aprovides a non-weighted input with an implied weighting of 1/2, as the LFSR304generates random patterns with a 50% chance of a logical ‘1’. A preferred weighting324acan be generated in a similar manner as the 1/8 and 7/8 weights, such as a four input AND-gate for a 1/16 weight or a five input OR-gate for a 31/32 weight, etc. It will be understood that any circuit capable of producing a weighting can be used in various embodiments as described herein, and weighting (preferred or otherwise) is not limited to the use of AND-gates and OR-gates. A weighted test path326ais defined between the LFSR304, the preferred weighting324a, the multiplexer312a, and the scan chain308ato apply to the preferred weighting324ato the integrated circuit design organizational units118ofFIG. 1embodied in the scan chain308a.

A similar layout is repeated in the design structure300to test additional STUMPS channels314. For example, for STUMPS channel314n, multiplexer312nincludes four multiplexer inputs316nas a 1/8 weighted input, a 7/8 weighted input, a non-weighted input, and a preferred weighted input. The multiplex inputs316nare generated by AND-gate318n, OR-gate320n, direct link322n, and preferred weighting324n. A weighted test path326nis defined between the LFSR304, the preferred weighting324n, the multiplexer312n, and the scan chain308nto apply to the preferred weighting324nto the integrated circuit design organizational units118ofFIG. 1embodied in the scan chain308n. While each of the multiplexers312a-312nare depicted as having the same multiplexer inputs316a-316nat the same multiplexer input position, i.e., 1/8, 7/8, 1/2, and preferred weighting positions, the values of the preferred weightings324a-324ncan vary. For example, the preferred weightings324aand324nmay both be assigned as at a first multiplexer input position (e.g., channel 0) on respective multiplexers312aand312n, the weighting values produced by the preferred weightings324aand324ncan be different, such as 15/16 and 1/64. Each multiplexer312a-312nmay have a respective weight selection register328a-328nto enable independent routing of weights per STUMPS channel314a-314n.

If a given integrated circuit design has a large number of different preferred weightings, e.g., more than four, modifying the IC layout124ofFIG. 1to align the preferred weightings with corresponding integrated circuit design organizational units118ofFIG. 1results in a greater level of test coverage while also keeping the multiplexers312a-321nand respective weight selection registers328a-328nrelatively compact such that each STUMPS channel314a-314nneed not support all weighting permutations. While only four multiplexer inputs316a-316nare depicted for each multiplexer312a-312nwith specific example weights provided, it will be understood the multiplexer312a-312ncan support a different number of multiplexer inputs316a-316nwith different weights beyond those depicted inFIG. 3. For example, different or additional weights such as 1/4, 3/4, 1/16, 15/16, 1/32, 31/32, etc. can be included in various embodiments. Furthermore, as depicted in the example ofFIG. 3A, fewer multiplexer inputs316a-316n(e.g., two) can be provided to each multiplexer312a-312n. Upon incorporating the preferred weightings324aand324n, other weights can be removed from the spreading network306, such as the 1/8 and 7/8 weighted inputs (seeFIG. 3vs.FIG. 3A) to reduce overall LBIST circuitry and use narrower instances of the multiplexer312a-312nand weight selection registers328a-328n.

FIG. 4depicts an alternate embodiment of the design structure300ofFIG. 3in accordance with an embodiment as design structure400. Similar to the design structure300ofFIG. 3, the design structure400ofFIG. 4includes LFSR304, spreading network306, scan chains308a-308n, multiplexers312a-312n, STUMPS channels314a-314n, multiplexer inputs316a-316n, AND-gates318a-318n, OR-gates320a-320n, direct links322a-322n, preferred weightings324a-324n, and weighted test paths326a-326n. Where the same multiplexer inputs316a-316nare routed to the same multiplexer input position, i.e., 1/8, 7/8, 1/2, and preferred weighting positions, on the multiplexers312a-312n, a common weight selection register428can be used for two or more of the multiplexers312a-312n. In the example ofFIG. 4, the preferred weightings324a-324nare assigned to a same multiplexer input position across a plurality of multiplexers312a-314nsuch that selection of the same multiplexer input position for the multiplexers312a-314nresults in selecting the preferred weightings324a-324nacross the multiplexers312a-312nat the same time.

The common weight selection register428can further increase test speed as fewer write operations may be needed to establish a particular testing mode. For instance, a preferred weighting testing mode can be defined as selecting the preferred weighting324a-324nfrom at least two of the multiplexers312a-312nat the same multiplexer input position at the same time. While only four multiplexer inputs316a-316nare depicted for each multiplexer312a-312nwith specific example weights provided, it will be understood the multiplexer312a-312ncan support a different number of multiplexer inputs316a-316nwith different weights beyond those depicted inFIG. 4. Similar toFIG. 3A, fewer multiplexer inputs316a-316n(e.g., two) can be provided to each multiplexer312a-312nincluding, for instance, only the direct links322a-322nand preferred weightings324aand324n.

FIG. 5depicts an additional design structure500in accordance with an embodiment. The design structure500illustrates an embodiment of a portion of the DUT112ofFIG. 1as a block diagram. Similar to the example ofFIG. 2, the design structure500ofFIG. 5includes an LFSR504that generates random patterns (i.e., 50% chance of being a 0 or a 1) and distributes the random patterns via a spreading network506to a plurality of scan chains508a,508b, . . . ,508m,508n. The scan chains508a-508nprovide weighted test paths through various macros122ofFIG. 1as embodied in the DUT112ofFIG. 1. The MISR510compresses the test results to confirm that failures are detected in a summarized format.

When DFT analysis is performed using the STUMPS channels120ofFIG. 1as the integrated circuit design organizational units118ofFIG. 1, the scan chains508a-508mmay already have instances of the macros122ofFIG. 1assigned to them. In the example ofFIG. 5, scan chain508aincludes macro mac_a, scan chain508bincludes macro mac_b, scan chain508mincludes mac_m, and scan chain508nincludes macro mac_n. When the DFT analysis is performed by DFT analyzer114ofFIG. 1on a STUMPS channel basis, the IC layout124ofFIG. 1can be created as a modification that assigns preferred weightings based on an existing layout rather than reallocating the macros122ofFIG. 1. At least one of the design files110ofFIG. 1may be annotated to include the preferred weightings on a STUMPS channel basis. The IC layout124ofFIG. 1can be created or modified based on the annotations to layout the spreading network506to provide the preferred weightings to each of the scan chains508a-508n. AND-gate or OR-gate combinations can be laid out in the spreading network506to hard code the preferred weightings. For example, if mac_a of scan chain508aand mac_n of scan chain508nprefer a 1/2 weight (i.e., non-weighted), then the spreading network506layout can provide direct links from the LFSR504to scan chains508aand508n. If mac_b of scan chain508bhas a preferred weighting of 15/16, then the spreading network506layout can include an appropriate circuit (e.g., 4-input OR-gate) between the LFSR504and scan chain508bto form a weighted test path526b. Similarly, if mac_m of scan chain508mhas a preferred weighting of 1/16, then the spreading network506layout can include an appropriate circuit (e.g., 4-input AND-gate) between the LFSR504and scan chain508mto form a weighted test path526m.

FIG. 6depicts a further design structure600in accordance with an embodiment. The design structure600illustrates an embodiment of a portion of the DUT112ofFIG. 1as a block diagram. InFIG. 6, separate LBIST channels602for each unique instance of the preferred weightings are created, and the macros122ofFIG. 1are assigned to a corresponding LBIST channel602based on the preferred weightings of the macros122ofFIG. 1. For example, if four scan chains are determined to have a preferred weighting of 1/4 and LBIST channel602acorresponds to a preferred weighting of 1/4, then spreading network606awould include a preferred weighting of 1/4 (e.g., a 2-input AND-gate) between LFSR604aand each scan chain608a-608d, with test results captured in MISR610a. If three scan chains are determined to have a preferred weighting of 63/64 and LBIST channel602ncorresponds to a preferred weighting of 63/64, then spreading network606nwould include a preferred weighting of 63/64 (e.g., a 6-input OR-gate) between LFSR604nand each scan chain608n-608p, with test results captured in MISR610p.

Accordingly, with respect to the example ofFIG. 6, the integrated circuit layout124ofFIG. 1includes weighted test paths626a-626dto respectively apply the preferred weightings (i.e., 1/4) to the macros122ofFIG. 1embodied in the scan chains608a-608d. The integrated circuit layout124ofFIG. 1also includes weighted test paths626n-626pto respectively apply the preferred weightings (i.e., 63/64) to the macros122ofFIG. 1embodied in the scan chains608n-608pin this example. The example continues for all unique preferred weightings in the DUT112ofFIG. 1.

FIG. 7depicts a computer-implement process700for implementing design-based weighting for logic built-in self-test in accordance with an embodiment. The process700can be implemented by the IC development system102ofFIG. 1to incorporate one or more of the design structures200-600ofFIGS. 1-6into the DUT112ofFIG. 1. The process700is described with respect toFIGS. 1-7.

At block702, a plurality of integrated circuit design organizational units118are analyzed to determine preferred weightings of the integrated circuit design organizational units118that provide a highest level of failure coverage when applied to the random pattern generator116. The analysis can be performed by the DFT analyzer114. The integrated circuit design organizational units118may be analyzed as macros122prior to organizing the macros into STUMPS channels120or analyzed as STUMPS channels120after assignment of the macros122to the STUMPS channels120.

At block704, based on determining the preferred weightings, the processing circuit104creates an IC layout124that includes a plurality of weighted test paths to respectively apply the preferred weightings to the integrated circuit design organizational units118. For example, the preferred weightings324a-324ncan be applied to STUMPS channels314a-314nvia weighted test paths326a-326n. The preferred weightings324a-324ncan be assigned to multiplexer inputs316a-316nfor the weighted test paths326a-326n. Connecting a common weight selection register428to at least two of the multiplexers312a-312ncan enable selection of the same multiplexer input position for the at least two of the multiplexers312a-312nat a same time. At least one of the design files110can be modified to annotate the preferred weightings of the integrated circuit design organizational units118in the design files110, e.g., at a macro level or STUMPS channel level. Where multiple LBIST channels602a-602nare used, an LBIST channel602a-602ncan be assigned to each unique instance of the preferred weightings, and the macros122assigned to a corresponding LBIST channel602a-602-nbased on the preferred weightings of the macros122. At block706, the IC layout124is incorporated in the DUT112.

Technical effects and benefits include design-based weighting for logic built-in self-test, where integrated circuit design organizational units are analyzed to determine preferred weightings, and based on the preferred weightings an integrated circuit layout is created including a plurality of weighted test paths to respectively apply the preferred weightings to the integrated circuit design organizational units.

As will be appreciated by one of average skill in the art, aspects of embodiments may be embodied as a system, method or computer program product. Accordingly, aspects of embodiments may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as, for example, a “circuit,” “module” or “system.” Furthermore, aspects of embodiments may take the form of a computer program product embodied in one or more computer readable storage device(s) having computer readable program code embodied thereon.

One or more of the capabilities of embodiments can be implemented in software, firmware, hardware, or some combination thereof. Further, one or more of the capabilities can be emulated.

Referring toFIG. 8, one or more aspects of embodiments can be included in an article of manufacture (e.g., one or more computer program products800) having, for instance, computer readable storage media802. The media has embodied therein, for instance, computer readable program code (instructions)804to provide and facilitate the capabilities of embodiments. The article of manufacture can be included as a part of a computer system or as a separate product. For example, the memory system106ofFIG. 1can be or include an embodiment of the computer readable storage media802, where the IC development tools108ofFIG. 1are embodied as computer readable program code804for execution by the processing circuit104ofFIG. 1.

An embodiment may be a computer program product for enabling processor circuits to perform elements of the invention, the computer program product comprising a computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method.

The computer readable storage medium (or media), being a tangible, non-transitory, storage medium having instructions recorded thereon for causing a processor circuit to perform a method. The “computer readable storage medium” being non-transitory at least because once the instructions are recorded on the medium, the recorded instructions can be subsequently read one or more times by the processor circuit at times that are independent of the time of recording. The “computer readable storage media” being non-transitory including devices that retain recorded information only while powered (volatile devices) and devices that retain recorded information independently of being powered (non-volatile devices). An example, non-exhaustive list of “non-transitory storage media” includes, but is not limited to, for example: a semi-conductor storage device comprising, for example, a memory array such as a RAM or a memory circuit such as latch having instructions recorded thereon; a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon; an optically readable device such as a CD or DVD having instructions recorded thereon; and a magnetic encoded device such as a magnetic tape or a magnetic disk having instructions recorded thereon.

A non-exhaustive list of examples of computer readable storage medium include the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a portable compact disc read-only memory (CD-ROM). Program code can be distributed to respective computing/processing devices from an external computer or external storage device via a network, for example, the Internet, a local area network, wide area network and/or wireless network. The network may comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. A network adapter card or network interface card in each computing/processing device receives a program from the network and forwards the program for storage in a computer-readable storage device within the respective computing/processing device.

These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer program instructions may also be stored in a computer readable storage medium that can direct a computer, other programmable data processing apparatus, or other devices to function in a particular.

FIG. 9illustrates multiple such design structures including an input design structure920that is preferably processed by a design process910. Design structure920may be a logical simulation design structure generated and processed by design process910to produce a logically equivalent functional representation of a hardware device, e.g., design structures200-600ofFIGS. 2-6from IC layout124ofFIG. 1for DUT112ofFIG. 1. Design structure920may also or alternatively comprise data and/or program instructions that when processed by design process910, generate a functional representation of the physical structure of a hardware device. Whether representing functional and/or structural design features, design structure920may be generated using electronic computer-aided design (ECAD) such as implemented by a core developer/designer.

When encoded on a machine-readable data transmission, gate array, or storage medium, design structure920may be accessed and processed by one or more hardware and/or software modules within design process910to simulate or otherwise functionally represent an electronic component, circuit, electronic or logic module, apparatus, device, or system such as those shown inFIGS. 1-6. As such, design structure920may comprise files or other data structures including human and/or machine-readable source code, compiled structures, and computer-executable code structures that when processed by a design or simulation data processing system, functionally simulate or otherwise represent circuits or other levels of hardware logic design. Such data structures may include hardware-description language (HDL) design entities or other data structures conforming to and/or compatible with lower-level HDL design languages such as Verilog and VHDL, and/or higher level design languages such as C or C++. The design structure920may be stored in the memory system106ofFIG. 1and/or on the computer program product800ofFIG. 8.