Testing apparatus for providing per pin level setting

A testing apparatus for providing per pin level setting is disclosed, and the testing apparatus includes a control unit and a filter circuit, where the control unit is electrically connected to the filter circuit. The control unit includes a field programmable gate array (FPGA) for providing a PWM signal. The filter circuit receives the PWM signal and outputs at least one DC voltage.

RELATED APPLICATIONS

This application claims priority to Taiwan Application Serial Number 102110515, filed Mar. 25, 2013, which is herein incorporated by reference.

BACKGROUND

Technical Field

The present disclosure relates to electronic equipment, and more particularly, a testing apparatus.

Description of Related Art

For a pin card of a testing apparatus, a digital-to-analog conversion (DAC) IC is utilized to set voltages (e.g., Vih/Vterm/Voh/Vol) of a pin driver and pin receiver. When the pin card is in a per group architecture, a plurality of pin drivers and pin receivers serve as a group, the same voltages are set for the group of the pin drivers and pin receivers, and therefore the number of DAC ICs is not too much. When the pin card is in a per pin architecture, varied voltages can be set for respective pin drivers and pin receivers individually, and therefore the number of DAC ICs is increased; accordingly, the cost of the pin card is increased adversely.

In view of the foregoing, there exist problems and disadvantages in the current apparatus that waits further improvement. However, those skilled in the art sought vainly for a solution. In order to solve or circumvent above problems and disadvantages, there is an urgent need in the related field to reduce the cost effectively.

SUMMARY

In one or more various aspects, the present disclosure is directed to a testing apparatus for providing per pin level setting, so as to solve or circumvent aforesaid problems.

According to one embodiment of the present disclosure, a testing apparatus includes a control unit and a filter circuit. The filter circuit is electrically connected to the control unit. The control unit includes a field programmable gate array (FPGA) for providing a pulse width modulation (PWM) signal. The filter circuit receives the PWM signal and outputs at least one direct current (DC) voltage.

The testing apparatus further includes a pin driver and pin receiver. The pin driver and pin receiver is electrically connected to the filter circuit for receiving the DC voltage so as to test a tested circuit.

The control unit further includes at least one inverter. The inverter is electrically connected to the FPGA for transmitting the PWM signal to the filter circuit.

In addition, the filter circuit is a low-pass filter for attenuating a high frequency portion of the PWM signal and outputting the DC voltage.

Moreover, the low-pass filter is a RC low-pass filter.

The RC low-pass filter includes a first resistor, a first capacitor, a second resistor and a second capacitor. A first terminal of the first resistor is connected to an output terminal of the control unit. A first terminal of the first capacitor is connected to a second terminal of the first resistor, and a second terminal of the first capacitor is grounded. A first terminal of the second resistor is connected to the first terminal of the first capacitor. A first terminal of the second capacitor is connected to a second terminal of the second resistor and a load, and a second terminal of the second capacitor is grounded.

Technical advantages are generally achieved, by embodiments of the present invention, as follows:

1. A low-cost FPGA can be utilized to set the voltage of the pin driver and pin receiver in the per pin architecture, so that the cost of the pin card in the per pin architecture can be reduced; and

2. The occupied area of voltage setting on a printed circuit board (PCB) can be decreased compared to DAC-based method.

DETAILED DESCRIPTION

As used in the description herein and throughout the claims that follow, the meaning of “a”, “an”, and “the” includes reference to the plural unless the context clearly dictates otherwise. Also, as used in the description herein and throughout the claims that follow, the terms “comprise or comprising”, “include or including”, “have or having”, “contain or containing” and the like are to be understood to be open-ended, i.e., to mean including but not limited to. As used in the description herein and throughout the claims that follow, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.

In one aspect, the present invention is directed to a testing apparatus for providing per pin level setting. This testing apparatus may be easily applied in circuit test, and may be applicable or readily adaptable to all related technology. It should be noted that a field programmable gate array (FPGA) is configured in the testing apparatus to accomplish the output of a pulse width modulation (PWM) signal. For a more complete understanding of the testing apparatus apparatus, and the advantages thereof, please refer toFIGS. 1-3and embodiments of the present disclosure.

FIG. 1is a block diagram of a testing apparatus100for providing per pin level setting according to one embodiment of the present disclosure. As shown inFIG. 1, the testing apparatus100includes a control unit110and a filter circuit120. The filter circuit120is electrically connected to the control unit110. The control unit110includes a FPGA111for providing a PWM signal; the filter circuit120receives the PWM signal and outputs at least one direct current (DC) voltage. In the present disclosure, an expensive DAC IC can be replaced with a low-cost FPGA, so as to reduce the cost.

In one embodiment, the filter circuit120is a low-pass filter. The low-pass filter can attenuate a high frequency portion of the PWM signal and outputs the DC voltage. In practice, when the frequency of the PWM signal is relatively high, the ripple of the DC voltage is relatively small. In contrast, when the frequency of the PWM signal is relatively low, the ripple of the DC voltage is relatively large. When the duty cycle of the PWM signal is relatively long (e.g., 246/256) or relatively short (e.g., 10/256), the ripple of the DC voltage is relatively small. In contrast, when the duty cycle of the PWM signal is relatively close to a median (e.g., 128/256), the ripple of the DC voltage is relatively large. Those with ordinary skill in the art may flexibly choose the frequency and duty cycle of the PWM signal of the FPGA111depending on the desired application.

FIG. 2is a block diagram of the testing apparatus100for providing per pin level setting according to another embodiment of the present disclosure. As shown inFIG. 2, the testing apparatus100not only includes the FPGA111and the filter circuit120but also includes a pin driver and pin receiver130. The pin driver and pin receiver130is electrically connected to the filter circuit120. In use, the pin driver and pin receiver130receives the DC voltage from the filter circuit120, so as to test a tested circuit210. Thus, the FPGA can be configured to set the voltages (e.g., Vih/Vterm/Voh/Vol) of the pin driver and pin receiver130. Moreover, it should be noted that the hardware configured in the pin driver and pin receiver130are well known in the art and, thus, are not repeated herein.

FIG. 3is a circuit diagram of the testing apparatus for providing per pin level setting according to yet another embodiment of the present disclosure. As shown inFIG. 3, the testing apparatus100includes at least one inverter112. The inverter112is electrically connected to the FPGA111. The inverter112transmits the PWM signal to the filter circuit120. For example, the product model of the inverter112may be 74AC04. In an alternative embodiment, the inverter112can be omitted. Those with ordinary skill in the art may selectively decide whether the inverter112is needed depending on the desired application.

In addition, the filter circuit120is a low-pass filter. Specifically, the low-pass filter is a RC low-pass filter.

The RC low-pass filter includes a first resistor R1, a first capacitor C1, a second resistor R2and a second capacitor C2. A first terminal of the first resistor R1is connected to an output terminal of the control unit110. A first terminal of the first capacitor C1is connected to a second terminal of the first resistor R1, and a second terminal of the first capacitor C1is grounded. A first terminal of the second resistor R2is connected to the first terminal of the first capacitor C1. A first terminal of the second capacitor C2is connected to a second terminal of the second resistor R2and a load310, and a second terminal of the second capacitor C2is grounded.

In practice, a resistance value of the first resistor R1is equal to a resistance value of the second resistor R2, and a capacitance value of the first capacitor C1is equal to a capacitance value of the second capacitor C2. Accordingly, when the capacitance value is relatively large, the ripple of the DC voltage is relatively small. In contrast, when the capacitance value is relatively small, the ripple of the DC voltage is relatively large.

Moreover, the RC low-pass filter may further include a third capacitor NC. The third capacitor NC and the second capacitor C2are connected in parallel. The load310can be equivalent to an electronic switch, as shown inFIG. 3.

For example, a Table 1 of values for the first resistor R1, the first capacitor C1, the second resistor R2and the second capacitor C2is shown below:

Furthermore, a Table 2 of output results of DC voltages of the filter circuit120is shown below:

It should be noted that above values shown in Tables 1 and 2 for illustrative purposes only. Those with ordinary skill in the art may flexibly choose parameters depending on the desired application.