Integrated power package

An integrated power package includes a substrate having a first surface and an integrated circuit located within the substrate. At least one electrical conductor is located between the first surface and another point on the substrate. At least one transistor is electrically and mechanically coupled to the at least one first conductor. A support structure is electrically and mechanically coupled to the at least one transistor, wherein the at least one transistor is located between the first surface of the substrate and the support structure.

BACKGROUND

Integrated power packages conduct high current and require good thermal performance in a small footprint in order to be placed in small electronic devices. Many integrated power packages lack the ability to place integrated circuits (ICs) in a vertical stack with high-current transistors, such as MOSFETs because the thermal performance is degraded by such placements.

Many of the conventional integrated power packages do not have exposed metal on top of the packages, which reduces the thermal performance of the MOSFETs and the controllers. Furthermore, conventional packages use the same process step to interconnect the controller and the MOSFETs, which results in degraded electrical performance.

SUMMARY

An integrated power package includes a substrate having a first surface and an integrated circuit located within the substrate. At least one electrical conductor is located between the first surface and another point on the substrate. At least one transistor is electrically and mechanically coupled to the at least one first conductor. A support structure is electrically and mechanically coupled to the at least one transistor, wherein the at least one transistor is located between the first surface of the substrate and the support structure.

DETAILED DESCRIPTION

Devices are disclosed herein that enable placement of high power transistors proximate integrated circuits that may control the operation of the transistors, wherein the transistors are located side by side.FIG. 1is a schematic diagram of a high current circuit100wherein current I flows through a first FET Q1and a second FET Q2. While FETs are described herein, the circuit100may substitute the FETs with other types of transistors. The current I flows between a first voltage V1and a second voltage V2. A node N1located between the first FET Q1and the second FET Q2has a voltage V3. The gates of the first and second FETs Q1and Q2are coupled to an IC controller106that controls the gate voltages and the current flow through the first and second FETs Q1and Q2. The current I flowing through the first and second FETs Q1and Q2generates heat that may interfere with the operation of the IC controller106. Furthermore, the current I may be too high to pass through the IC controller106. Accordingly, the first and second FETs Q1and Q2are typically located external to the IC controller106. The circuits and structures described herein enable the IC controller106to be located proximate the first and second FETs Q1and Q2in an integrated power package that provides for heat dissipation. The transistors described with reference toFIG. 1are exemplary and other configurations may be applied, such as different P-channel and N-channel devices.

FIG. 2is a side cutaway view of an example of an integrated power package200for the circuit100ofFIG. 1andFIG. 3is a top plan view of the package200. The package200includes a dielectric structure202wherein the IC controller106is attached to the dielectric structure202. The dielectric structure202includes a plurality of conductors that are described below. In the example ofFIG. 2, the IC controller106is located within the dielectric structure202, but in other examples, the IC controller106is attached to other portions or surfaces of the dielectric structure202. In yet other examples, the IC controller106is located in other positions within the dielectric structure202. The dielectric structure202is fabricated from material that is substantially electrically insulating, such as dielectric materials commonly used in the fabrication of IC packages. Dielectric materials include polymer based materials.

The dielectric structure202includes a top surface204, which is sometimes referred to as a first surface, and a bottom surface206, which is sometimes referred to as a second surface. In addition, the dielectric structure202includes a front surface208and a rear surface210. A first gate pad214and a second gate pad216are located on the top surface204of the dielectric structure202. The pads described herein are illustrated with a bonding material located thereon. The first gate pad214serves as a conductor for the gate of the first FET Q1,FIG. 1, and the second gate pad216serves as a conductor for the gate of the second FET Q2. The first gate pad214and the second gate pad216may be solder pads that electrically and mechanically couple electronic components to substrates and other structures. A first source pad220and a second drain pad222are also located on the top surface204of the dielectric structure202. In the configuration of the IC package200, the first FET Q1is placed source down on the first source pad220and the second FET Q2is placed drain down on the second drain pad222. In other embodiments, the FETs may have other configurations relative to the dielectric structure202. The first source pad220and the second drain pad222may be solder pads that electrically and mechanically connect electronic components to substrates. The first source pad220and the second drain pad222may have thermal and electrical properties described herein.

The dielectric structure202includes a plurality of conductors that electrically connect the pads to external contacts and to the IC controller106. The conductors shown inFIGS. 2 and 3are for illustration purposes only and other conductor configurations may be located within the dielectric structure202. A first gate conductor230couples the first gate pad214to the IC controller106and a second gate conductor232couples the second gate pad216to the IC controller106. The first gate conductor230and the second gate conductor232conduct the gate current between the first and second FETS Q1and Q2and the IC controller106. Because the first and second gate conductors230and232conduct gate currents, the current flow is relatively low, so the first and second gate conductors230and232may be relatively small. Other low current conductors (not shown) may be located within the dielectric structure202to couple external connectors to the IC controller106.

Other conductors within the dielectric structure202serve to conduct the current I, shown inFIG. 1, through the first FET Q1and the second FET Q2. A first source conductor240conducts current between a point external to the dielectric structure202and the first source pad220. A second drain conductor242conducts current between a point external to the dielectric structure202and the second drain pad222. The external points described herein are shown as being on the bottom surface206of the dielectric structure202; however, the external points may be located anywhere on the dielectric structure202. The conductors240and242are fabricated from a low resistance material and are large enough to accommodate the current I so as to minimize losses as the current I flows through the conductors240and242. In some examples, the current I may be in the range of 1.0 to 100 Amps. In such embodiments, the conductors240and242should be less than 10 mΩ of resistance, and in some examples the resistance is less than 1.0 mΩ.

The first FET Q1is electrically and mechanically coupled to the first gate pad214and the first source pad220. More specifically, the gate of the first FET Q1is electrically and mechanically coupled to the first gate pad214and the source is electrically and mechanically coupled to the first source pad220. The second FET Q2is electrically and mechanically coupled to the second gate pad216and the second drain pad222. More specifically, the gate of the second FET Q2is electrically and mechanically coupled to the second gate pad216and the drain is electrically and mechanically coupled to the second drain pad222. In some examples the material bonding the FETS Q1and Q2to their respective pads has a thermal conductivity of greater than five watts per meter-Kelvin (W/mK) and an electrical resistivity of less than 500 micro-Ohm-cm (uΩcm) and has a thickness between 10 and 100 microns.

With additional reference toFIG. 4, conductor250is electrically and mechanically coupled to both the first FET Q1and the second FET Q2. The conductor250is sometimes referred to as a, “support structure”. In the embodiment ofFIG. 2, the conductor250has a horizontal portion252and a vertical portion254. The current I flows through the horizontal portion252, so the material of the horizontal portion252is such that it can accommodate the current I and electrically and mechanically couple to both FETS Q1and Q2. For example, the conductor250may be fabricated from copper or a similar material, and may have a thickness of 0.025 mm to 0.5 mm. The horizontal portion252has a top surface256, which is sometimes referred to as a first surface, and a bottom surface258, which is sometimes referred to as a second surface. The bottom surface258has a first drain pad260and a second source pad262that electrically and mechanically couple the first and second FETS Q1and Q2to the horizontal portion252. The horizontal portion252may also serve to dissipate heat from the package200. For example, the horizontal portion252may be larger than the first and second FETs Q1and Q2by 0.5 mm to 5 mm when viewed from the top plan view ofFIG. 4. Accordingly, the horizontal portion252may extend beyond the footprints of the first and second FETS Q1and Q2, which enables heat to be transferred from the first and second FETS Q1and Q2and to the horizontal portion252. The heat may then be transferred away from the package200by way of the horizontal portion252. The specific thickness, content, and size of the support structure250as well as the electrical and mechanical interconnection are selected in order to sufficiently conduct away the heat generated by the first and second FETs Q1and Q2.

In some examples, the vertical portion254secures the conductor250to the dielectric structure202and couples the voltage V3to the dielectric structure202. The potential of the conductor250is the voltage V3ofFIG. 1. In the example ofFIG. 2, the potential is conducted to the bottom surface206of the dielectric structure202by way of a conductor268. In some examples of the circuit100ofFIG. 1, the current I flows through the conductor268, so it may be fabricated in a manner to accommodate the current I with minimal loss. The material coupling the first and second FETS Q1and Q2to the conductor250may be the same or have the same electrical and/or thermal characteristics as the material coupling the first and second FETS Q1and Q2to the pads220and222.

As shown inFIG. 4, the horizontal portion252of the conductor250extends in a manner to cover both FETS Q1and Q2so as to provide efficient heat transfer and to accommodate the current I,FIG. 1. For example, the horizontal portion252may be a metal device that conducts heat and it may be exposed to the exterior of the package200. Heat sinks or other devices or methods for transferring heat from the horizontal portion252may be placed proximate the horizontal portion252when the package202is in use.

The package200has many advantages over conventional packages. For example, the package200has the first and second FETS Q1and Q2located on top of the IC controller106, which reduces the size of the package200. Additionally, the package200may have the horizontal portion252of the conductor250exposed, which enhances the thermal performance of the package200.

The fabrication techniques for the package200provide further enhancements over conventional packages. The dielectric structure202is fabricated with the IC controller106and the conductors located therein. The first FET Q1and the second FET Q2are electrically and mechanically coupled to the bottom surface258of the horizontal portion252. In some examples, solder or an epoxy having the electrical and thermal properties described above is used to couple the FETS Q1and Q2. The combination of the conductor250and the FETS Q1and Q2is then placed onto the top surface204of the substrate202so that the FETS Q1and Q2contact their appropriate pads on the top surface204of the dielectric structure202. In other examples, the FETS Q1and Q2are coupled to the top surface204of the dielectric structure202and the conductor250is subsequently coupled to the FETS Q1and Q2and the dielectric structure202.

An example of fabricating the package200is described by the flow chart500ofFIG. 5. Step502includes locating an integrated circuit within a dielectric structure wherein the dielectric structure has a surface. Step504includes locating a first conductor between the surface and another point on the dielectric structure. Step506includes locating a second conductor between the surface and another point on the dielectric structure. Step508includes coupling a first transistor to an electrically conductive support structure. Step510includes coupling a second transistor to the support structure. Step512includes coupling the combination of the support structure, the first transistor and the second transistor to the dielectric structure, wherein the first transistor couples to the first conductor and the second transistor couples to the second conductor.

Certain embodiments of integrated power packages and fabrication methods have been expressly described in detail herein. Alternative embodiments will occur to those skilled in the art after reading this disclosure. The claims are intended to be broadly construed to cover all such alternative embodiments, except as limited by the prior art.