Flexible transmitter circuitry for integrated circuits

A multichip package may include a transmitter die and a receiver mounted on a substrate. The transmitter die may be coupled to the receiver die through die-to-die connections such as microbumps and conductive paths in the substrate. The transmitter die may include flexible transmitter circuitry having transceiver logic and driver circuitry. The driver circuitry may include a high-swing driver and a low-swing driver optionally equalization circuitry. The driver circuitry may operable in a high-swing mode, a low-swing mode with equalization, and a low-swing mode without equalization. Transmitter circuitry provided in this way removes undesirable DC voltage paths to ground present in other driving schemes to reduce power consumption while still meeting bandwidth, flexibility, and scalability demands.

BACKGROUND

This relates generally to integrated circuits and more particularly, to integrated circuit packages with more than one integrated circuit die.

An integrated circuit package typically includes an integrated circuit (IC) die and a substrate on which the die is mounted. The integrated circuit die is coupled to the substrate through bonding wires or solder bumps. Signals from the integrated circuit die travels through the bonding wires or solder bumps to the substrate.

As demands on integrated circuit technology continue to outstrip even the gains afforded by ever decreasing device dimensions, an increasing number of applications demand a packaged solution with more integration than is possible in a single silicon die. In an effort to meet this need, more than one IC die can be placed within an integrated circuit package (i.e., a multichip package).

However, as more dies are communicatively connected to each other in the integrated circuit package, communications between the dies becomes increasingly important and a limiting factor to device performance. In particular, it may be crucial to incorporate different types of dies from different technology nodes to cater to different types of applications in a single integrated circuit package. This must all be done while meeting communications requirements between the different types of dies and accounting for reliability requirements, power requirements, space requirements, cost requirements, etc. for communications circuitry.

Accordingly, to obtain better performance and increase flexibility of communications circuitry for a wide variety of chip technologies, an integrated circuit die having improved communications circuitry such as improved transmitter circuitry is needed.

It is within this context that the embodiments described herein arise.

DETAILED DESCRIPTION

The present embodiments relate to integrated circuits and more particularly, integrated circuits with flexible transmitter circuitry operable in multiple modes of operation to cater to varying needs of different applications. In particular, the flexible transmitter circuitry may include driver circuitry having a high-swing driver, a low-swing driver, and optionally equalization circuitry in the low-swing driver.

Given that integrated circuit packages may include a wide range of integrated circuits with varying functions and formed using various technology nodes, the flexible transmitter circuitry can reliably meet the communication demands between these integrated circuits. The transmitter circuitry may also operate in different modes of operations optimized for different types of application to further provide flexible yet targeted solution for die-to-die connectivity.

It will be recognized by one skilled in the art, that the present exemplary embodiments may be practiced without some or all of these specific details. In other instances, well-known operations have not been described in detail in order not to unnecessarily obscure the present embodiments.

FIG. 1is a diagram of an illustrative system100of interconnected electronic devices. The system of interconnected electronic devices may have multiple electronic devices such as device A, device B, device C, device D, and interconnection resources102. Interconnection resources102such as conductive lines and busses, optical interconnect infrastructure, or wired and wireless networks with optional intermediate switching circuitry may be used to send signals from one electronic device to another electronic device or to broadcast information from one electronic device to multiple other electronic devices. For example, a transmitter in device B may transmit data signals to a receiver in device C. Similarly, device C may use a transmitter to transmit data to a receiver in device B.

The electronic devices may be any suitable type of electronic device that communicates with other electronic devices. Examples of such electronic devices include integrated circuits having electronic components and circuits such as analog circuits, digital circuits, mixed-signal circuits, circuits formed within a single package, circuits housed within different packages, circuits that are interconnected on a printed-circuit board (PCB), etc.

As integrated circuit fabrication technology scales towards smaller process nodes, it becomes increasingly challenging to design an entire system on a single integrated circuit die (sometimes referred to as a system-on-chip). Designing analog and digital circuitry to support desired performance levels while minimizing leakage and power consumption can be extremely time consuming and costly.

One alternative to single-die packages is an arrangement in which multiple dies are placed within one package. Such types of packages that contain multiple interconnected dies may sometimes be referred to as systems-in-package (SiPs), multichip modules (MCM), or multichip packages. Placing multiple dies (e.g., chips) within a single package may allow each die to be implemented using the most appropriate technology node, may increase the performance of die-to-die interface (e.g., driving signals from one die to another within a single package is substantially easier than driving signals from one package to another, thereby reducing power consumption of associated input-output buffers), may free up input-output pins (e.g., input-output pins associated with die-to-die connections are much smaller than pins associated with package-to-board connections), and may help simplify printed circuit board (PCB) design (i.e., the design of the PCB on which the multi-chip package is mounted during normal system operation).

FIG. 2is a diagram of an illustrative multichip package200. As shown inFIG. 2, multichip package200may include one or more integrated circuit dies such as an integrated circuit (IC) die203, an integrated circuit die203′, transceiver (XCVR) dies210, and high bandwidth memory (HBM) die206mounted on a common package substrate202. Substrate202may be a passive silicon substrate, an active silicon substrate (e.g., a substrate that includes transistors for assisting operations on a main die such as die203or die203′), or any interposer substrate carriers. This arrangement in which multiple dies are mounted on a common package substrate may sometimes be referred to as a “2.5D” arrangement.

IC dies203and203′ may, for example, each be a programmable integrated circuit such a field-programmable gate array (FPGA) device, an application-specific integrated circuit (ASIC) device, or any other type of device based on any type of technology. IC dies203and203′ may, as another example, each be a central processing unit (CPU), a graphic processing unit (GPU), or any other type of general- or specific-function processor. IC dies203and203′ may be formed from different technologies, may be integrated circuits of different types, and/or may be processors having different functions. Alternatively, if desired, IC dies203and203′ may be formed from the same technology, be integrated circuits of the same type, and/or be processors having the same function.

IC die203may include on-package interconnect circuitry such as the Advanced Interface Blocks (AIBs)208for communicating with transceiver dies210via bus305. Bus305is sometimes referred to as an interface bus. Bus305may be an Advanced Interface Bus or an ALTERA Interface Bus, as examples. Transceiver dies210may be configured to transmit and receive signals to and from components external to package200and to support high-speed data communications (e.g., at data rates of more than 10 Gbps, more than 50 Gbps, or more than 100 Gbps, etc.) over 1-16 lanes with the off-package components (as an example). The example ofFIG. 2in which AIBs208for interfacing with transceiver dies210are formed along the bottom peripheral edge (shoreline) of die203is merely illustrative. In general, AIBs208may be formed on portion of die203. The examples of the AIBs and the Advanced Interface Bus are merely illustrative. If desired, any suitable type of communications interface and any suitable type of bus may be used instead or in addition to AIBs208and bus305.

IC die203may also include on-package interconnect circuitry such as universal interface block (UIB)204for communicating with on-package components such as memory die206via bus205. Bus205is therefore sometimes referred to as a universal interface bus. As examples, memory die206may be implemented using random-access memory such as static random-access memory (SRAM), dynamic random-access memory (DRAM), low latency DRAM (LLDRAM), reduced latency DRAM (RLDRAM), or other types of volatile memory. If desired, memory die206may also be implemented using nonvolatile memory (e.g., fuse-based memory, antifuse-based memory, electrically-programmable read-only memory, etc.). Configured in this way, block204may serve as a physical-layer bridging interface between an associated memory controller (e.g., a non-reconfigurable “hard” memory controller or a reconfigurable “soft” memory controller logic) on IC die203and one or more high-bandwidth channels that is coupled to an associated memory die206. In general, universal interface block204may be capable of supporting a wide variety of communications protocols, which are not limited to memory interface protocols, for interfacing with different types of daughter dies.

In accordance with some embodiments, UIB204may be used to support multiple parallel channel interfaces such as the JEDEC JESD235 High Bandwidth Memory (HBM) DRAM interface or the Quad Data Rate (QDR) wide IO SRAM interface (as examples). In accordance with some embodiments, UIB204is able to support external memory interfaces (EMIF) having more than four (DDR) memory channels, four to eight memory channels, eight to 16 memory channels, or more than 16 memory channels. Each of the parallel channels can support single data rate (SDR) or double data rate (DDR) communications.

IC die203may further include external input-output (IO) blocks such as a high-speed interface (HSI) block. External IO blocks may support wide parallel interfaces such as EMIF or more generic interfaces like GPIO (general purpose input-output) or LVDS (lower voltage differential signaling) interfaces. External memory interfaces that are supported by external input-output blocks may include double data rate (DDR) interfaces such as DDR type-3 (DDR3), low power DDR3 (LPDDR3), DDR type-4 (DDR4), low power DDR4 (LPDDR4), DDR type-5 (DDR5), graphics DDRx, quad data rate (QDR), Open NAND Flash Interface (ONFI), or other suitable interfaces for communicating with memory that is external to package200.

In accordance with an embodiment, external input-output (IO) blocks may include an HSI block312that supports communications with other dies within package200(e.g., IC die203′). As shown inFIG. 2, a communications bus such as communications bus313may couple HSI block312in IC die203to IC die203′. In this illustrative example, external IO block312may support GPIO, LVDS, or other suitable interfaces to communicate with IC die203′.

If desired, IC die203may include any suitable additional circuitry other than the interfacial circuitry shown in the example ofFIG. 2. If desired, package200may include any suitable number of additional dies not shown inFIG. 2, each having a suitable number of interconnects with dies in package200.

FIG. 3shows an illustrative example where IC die203serving as a signal transmitting die (sometimes referred to as a transmitter die) may be connected with IC die310serving as a signal receiving die (sometimes referred to as a receiver die). As an example, receiver die310may be IC die203′ in package200as shown inFIG. 2(e.g., may be an ASIC device, a FPGA device, a CPU, a GPU, etc. inside the same package as IC die203). As other examples, receiver die310may be one of transceiver dies210or high bandwidth memory die206. If desired, however, receive die310may be any other die within package200. Receiver die310may include any suitable circuits configured to properly receive data signal (e.g., sent by transmitter die203). As examples, receiver die310may include transceiver circuitry or receiver circuitry having driver circuits, control logic circuits, etc.

To facilitate efficient and flexible communications between dies within a package such as IC dies203and310, IC die203may include flexible communications or transmitter circuitry (implemented in transceiver circuitry if desired). The transmitter circuitry may be utilized for transmitting signals out of IC die203through channel308into IC die310. Channel308may be formed from conductive traces, wires, copper cables, flip-chip bumps, solder bumps, microbumps, or any other connective structures. If desired, channel308may be implemented on multiple parallel communicative paths that are referred to as a channel308.

Transmitter circuitry in IC die203may include transmitter logic circuit300(sometimes referred to as transmitter logic) and driver circuitry302(sometimes referred to herein as data transmission driver circuitry). Driver circuitry302may include a first output driver or driver circuit such as a high-swing driver (e.g., high-swing driver304) and a second output driver or driver circuit such as low-swing driver (e.g., driver circuit306). Output driver304may be referred to as a ‘high-swing’ driver because driver304may generate an output signal for driver circuitry302that has high voltage swings (e.g., a voltage swing of 0 V to 1.2 V, 0 V to 1 V, 0 V to 0.8 V, 0 V to 0.6 V, 0 V to 0.5 V, 0 V to 0.4 V, 0 V to 0.3 V, or any other suitable voltage swing). Output driver306may be referred to as a ‘low-swing’ driver because driver306may generate an output signal for driver circuitry302that has low voltage swings (e.g., a voltage swing of 0 V to 0.6 V, 0 V to 0.5 V, 0 V to 0.4 V, 0 V to 0.3 V, 0 V to 0.2 V, 0 V to 0.1 V, or any other suitable voltage swing). In some embodiments, the output signal voltage swing for output driver304may be larger in magnitude than the output signal voltage swing for output driver306.

If desired, the respective operations of high-swing driver304and low-swing driver306may be mutually exclusive. In other words, when high-swing driver304is activated or enabled, low-swing driver306is deactivated or disabled (e.g., place in a tri-state mode) and vice versa. Driver circuitry302when using high-swing driver304(e.g., an activated high-swing driver304) may generate an output signal having a voltage swing that is larger than that of an output signal generated when using low-swing driver302(e.g., an activated low-swing driver306). As a specific example, the voltage swing of the output signal generated by an activated high-swing driver304may be 0.8 V, while the voltage swing of the output signal generated by an activated low-swing driver306may be 0.4 V. This is merely illustrative, if desired, any suitable voltage swing may be implemented for the respective output signals for high-swing driver304and low-swing driver306.

Additionally, driver circuitry302may include equalization circuitry (sometimes referred to as a pre-emphasis circuit) within low-swing driver305. Equalization circuitry may reduce or cancel frequency-dependent attenuations imparted to the signal by transmission channel308. Equalization circuitry may be used to provide high-frequency and direct signal level boosting to compensate for high-frequency signal loss (e.g., losses in copper-based channels that exhibit undesired low-pass transfer characteristics that result in signal degradation at high data rates) or to enhance signal-to-noise ratio (SNR) in scenarios in which uncorrelated noise such as crosstalk is present. As examples, equalization circuitry may implement linear equalization schemes such as finite impulse response (FIR) and feed forward equalization (FFE) schemes or nonlinear adaptive equalization schemes such as infinite impulse response (IIR) or decision feedback equalization (DFE) schemes.

By providing high-swing driver304, low-swing driver306and equalization circuitry in the transmitter circuitry of IC die203, IC die203may flexibly change the operating mode of the transmitter circuitry to adapt to the properties of transmitter die203and receiver die310. As such, the transmitter circuitry inFIG. 3may be implemented in one or more of blocks204,208,312in IC die203inFIG. 2, if desired. If desired, the transmitter circuitry described inFIG. 3may be implemented in interface blocks of any of dies203′,206, and/or210inFIG. 2.

FIG. 4shows illustrative modes of operation for transmitter circuitry of the type shown in IC die203inFIG. 3. In particular, driver circuitry302inFIG. 3may operate in a first mode of operation such as high-swing driver mode400(sometimes referred to as high-swing mode) by enabling a high-swing driver portion such as high-swing driver304inFIG. 3and disabling a low-swing driver portion such as placing low-swing driver306inFIG. 3in a tri-state mode. The driver circuitry may operate in high-swing driver mode400without equalization (e.g., by disabling equalization circuitry described inFIG. 3). If desired, the driver circuitry may operate in high-swing driver mode400for lower speed applications such as some AIB applications (e.g., utilizing speeds of 2 Gbps) or other applications utilizing speeds of 2 Gbps or lower. If desired, the driver circuitry may operate in high-swing driver mode400for cost-sensitive applications.

Driver circuitry302inFIG. 3may also operate in a second mode of operation such as low-swing driver mode402with equalization disabled (sometimes referred to as low-swing mode402without equalization). In this low-swing driver mode402, the high-swing driver portion may be disabled (e.g., high-swing driver304inFIG. 3may be placed in a tri-state mode), the low-swing driver portion (e.g., low-swing driver306inFIG. 3) may be enabled, and the equalization circuitry in low-swing driver306inFIG. 3may be disabled. If desired, the driver circuitry may operate in low-swing driver mode402without equalization for lower speed applications having very strict power requirements (e.g., for low power applications, or applications with limited power supply potential, etc.) as equalization circuitry may consume excess power.

Driver circuitry302inFIG. 3may also operate in a third mode of operation such as low-swing driver mode404with equalization enabled (sometimes referred to as low-swing mode with equalization). In this low-swing driver mode404, the high swing driver portion may be disabled (e.g., high-swing driver304inFIG. 3may be placed in a tri-state mode), the low-swing driver portion (e.g., low swing driver306inFIG. 3) may be enabled, and the equalization circuitry may be enabled. If desired, the driver circuitry may operate in low-swing driver mode404with equalization for high-speed applications and the equalization circuitry may compensate channel losses. As an example, low-swing driver306with equalization circuitry may compensate for channel losses up to 6 dB and may be suitable for applications having data rates of up to 10 Gbps or higher.

The modes of operation and illustrative applications shown and described in connection withFIG. 4are merely illustrative. If desired, the driver flexible driver circuitry of the type inFIG. 3may be operated in other suitable manners. If desired, the modes of operation described inFIG. 4and other modes of operation may be used in any suitable application (not limited to those applications described in connection withFIG. 4).

FIGS. 5A and 5Bshow block diagrams in cross-sectional side views of multichip package200of the type described in connection withFIG. 2. As shown inFIG. 5A, package200may include package (semiconductor) substrate202(or optionally an interposer) and IC die203mounted on substrate202. Package200may also include other dies. As examples, other dies in package200described in connection withFIG. 2may also be mounted on substrate202, or may be mounted on IC die203or on another package substrate.

Flip-chip (otherwise known as controlled collapse chip connection or “C4”) bumps504may be formed between substrate202and die203, and between substrate202and other various dies mounted on substrate202. An array of solder balls506(sometimes referred to collectively as a ball grid array or “BGA”) may be formed at the bottom surface of package substrate202. Multichip package200formed in this way may then be mounted on a printed circuit board (PCB) such as PCB500inFIG. 5Ato communicate with other devices in a larger system.

As described in connection withFIG. 3and shown inFIG. 5A, IC die203may include transmitter logic300, high-swing driver304, and low-swing driver306. Transmitter logic300may provide data signal txdin to high-swing driver304and low-swing driver206for transmission. Transmitter logic300may also provide a shifted version of data signal txdin (i.e., data signal txdin_shift) to low-swing driver306. As an example, data signal txdin_shift may be a one clock cycle delayed version of data signal txdin.

Low-swing driver306may receive control signal lowswing_en that controls whether low-swing driver306is enabled or in a tri-state mode (e.g., disabled). Low-swing driver306may receive control signal eq_en that controls whether equalization or pre-emphasis circuitry is enabled or disabled. If desired, high-swing driver304may similarly receive a control signal indicating whether high-swing driver304is enabled or in a tri-state mode (e.g., disabled). In some embodiments (e.g., in which the operations of low-swing driver306and high-swing driver304are mutually exclusive), high-swing driver304may also receive control signal lowswing_en or a modified version of control signal lowswing_en. In other words, control signal lowswing_en may be able to control the states (e.g., enabled or disabled states) of both high-swing driver304and low-swing driver306.

High-swing driver304and low-swing driver306may generate (e.g., drive) driver output signals off driver output path350in IC die203. The output signals may be provided through microbump522onto conductive paths in package substrate202. As an example, the conductive paths in package substrate202may be dedicated (ultra) high-density interconnections between dies within package200. These dedicated high-density interconnections may be an Embedded Multi-Die Interconnect Bridge (EMIB) silicon chip520that is embedded in package substrate202. EMIB520may generally include short wires such as wires524, which help to significantly reduce loading at output drivers and directly boost performance. The mesh of short wires524within EMIB520may be coupled to smaller solder bumps such as microbumps522, which exhibits reduced pitch and therefore offers denser interconnectivity relative to flip-chip bumps504. Wires524on EMIB520may provide the output signals from driver circuitry203on transmitter die203to a receiver die in package200(e.g., receiver die310inFIG. 3).

FIG. 5A, in particular, shows flexible transmitter circuitry on IC die203when operating in a high-swing driver mode of operation (e.g., mode400inFIG. 4). In the high-swing driver mode of operation, high-swing driver304may be activated and low-swing driver306may be placed in a tri-state mode (e.g., deactivated). Additionally, while driver circuitry302(e.g., high-swing driver304and low-swing driver306) may sometimes receive two different supply voltages VCCL and VCCH, conductive paths522supplying supply voltages VCCL and VCCH may be electrically shorted to each other to provide a single supply voltage level to driver circuitry302when operating in high-swing driver mode of operation. As an example, a voltage regulator such voltage regulator550on PCB500may supply the single supply voltage level to high-swing driver304in driver circuitry302through conductive traces on PCB500, solder bumps506, conductive traces552on package substrate202, bumps504, and conductive traces552on IC die203. If desired, conductive paths522may be shorted at PCB500to ensure that a single supply voltage level is provided to high-swing driver304.

In some embodiments, the single supply voltage level may be at 0.8 V, and as such, the high voltage level of output signal on path350may be at 0.8 V. This is merely illustrative. If desired, any other suitable voltage level may be used. As an example, the single supply voltage level may be the same as a core supply voltage level for a main die in package200.

Referring toFIG. 5B, the configurations of IC203, package substrate202, and PCB500inFIG. 5Bare similar to those described in connection withFIG. 5A. Similar features already described in connection withFIG. 5Aare not described further in connection withFIG. 5Bin order to not unnecessary obscure the details ofFIG. 5B.FIG. 5B, in particular, shows flexible transmitter circuitry on IC die203when operating in a low-swing driver mode of operation (e.g., mode402or mode404inFIG. 4). In the low-swing driver mode of operation, low-swing driver306may be activated and high-swing driver304may be placed in a tri-state mode (e.g., deactivated). Low-swing driver306may receive two different supply voltages such as first supply voltage VCCL and second supply voltage VCCH. Separate voltage regulator circuits on PCB500may provide supply voltages VCCL and VCCH to low-swing driver306in driver circuitry302. As an example, voltage regulator550-1may provide supply voltage VCCL through conductive traces552-1, solder bumps506, and bumps504to low-swing driver306. As another example, voltage regulator550-2may provide supply voltage VCCH through conductive traces552-2, solder bumps506, and bumps504to low-swing driver306.

In some embodiments, supply voltage VCCL may be at 0.8 V and supply voltage VCCH may be at 0.4 V. This is merely illustrative. If desired, any other suitable voltage levels may be used. As an example, supply voltage VCCL may use a core supply voltage level for a main die in package200and supply voltage VCCH may be dedicated voltage level used exclusively in IC blocks in package dies. As another example, voltage regulator550-2and supply voltage VCCL may be omitted if low-swing driver306does not include equalization circuitry.

The examples inFIGS. 5A and 5Bare merely illustrative. If desired, additional dies and interconnections may be formed in package200. If desired, driver circuitry302may receive additional suitable control signals to operate high-swing driver304, low-swing driver306, and/or equalization circuitry.

FIG. 6Ashows a schematic circuitry diagram of transceiver logic300and driver circuitry302of the type described in connection withFIGS. 3, 5A, and 5B. Driver circuitry302may include high-swing driver304, low-swing driver306, and pre-emphasis circuit620(sometimes referred to as equalization circuitry) within low-swing driver306. Transceiver logic300may include first pre-driver logic such as high-swing pre-driver logic circuit630, second pre-driver logic such as low-swing pre-driver logic circuitry660, driver control logic such as low-swing control logic circuit680, and equalization control logic such as equalization control logic circuit690.

High-swing driver304may include a pull-up transistor (PMOS) transistor M1having a first source-drain terminal (e.g., a source terminal) coupled to voltage supply (rail)602providing supply voltage VCCH. Transistor M1may have a second source-drain terminal (e.g., a drain terminal) coupled to a first source-drain terminal (e.g., drain terminal) of a pull-down transistor such as (NMOS) transistor M2. Transistor M1may have a gate terminal coupled to an output of NAND logic gate610that provides signal DRVP. Transistor M2may have a second source-drain terminal (e.g., source terminal) coupled to a grounding structure providing a reference voltage (i.e., a grounding voltage) and a gate terminal coupled to an output of NAND logic gate612that provides signal DRVN. A driver output may be coupled between transistors M1and M2and may be coupled to microbump522.

Level shifter632may receive input data signal for transmission and generate a corresponding (voltage level shifted) output. Since there are two power domains (e.g., voltages VCCL and VCCH), a level shifter may convert the voltage level of an input signal in a first power domain (associated with VCCL) into the voltage level of a second power domain (e.g., associated with voltage VCCH). Level shifter632may provide the corresponding output as respective first inputs to NAND logic gates610and612. High-swing pre-driver logic circuit630may provide respective second inputs to NAND logic gates610and612. In particular, pre-driver logic circuit630may include level shifter644that receives an input from NOR logic gate642and that generates a corresponding output supplied to NAND logic gate610as the second input. Pre-driver logic circuit630may similarly include level shifter654that receives an input from NAND logic gate652and that generates a corresponding output supplied to NAND logic gate612as the second input.

Additionally, pre-driver logic circuit630may include inverters640and650that receive control signals pdrv_sel and ndrv_selb, respectively, and that generate corresponding outputs that are supplied as respective inputs to NOR logic gate642and NAND logic gate652. NOR logic gate642and NAND logic gate652may receive respective additional inputs from low-swing control logic circuit680. In particular, NOR logic gate642may receive control signal lowswing_en as an additional input. NAND logic gate652may receive signal lowswing_enb as an additional input. Control signal lowswing_en may be passed through level shifter682and inverted by inverter684to generate signal lowswing_enb.

Control signals pdrv_sel and ndrv_selb may determine the pull-up strength and pull-down strength of driver circuits (e.g., in high-swing driver304). If desired, the pull-up and pull-down strengths may be independently controlled by control signals pdrv_sel and ndrv_selb. High-swing driver304may include multiple sets of driver circuits (e.g., circuits that include transistors M1and M2, and logic gates610and612) coupled in parallel to provide the driver output to microbump522. Different numbers of sets of these parallel driver circuits may be activated as desired to implement suitable driving strength.

Low-swing driver306may include a pull-up circuit or transistor such as (NMOS) transistor M3having a first source-drain terminal (e.g., drain terminal) coupled to voltage supply (rail)602providing supply voltage VCCH. Transistor M3may have a second source-drain terminal (e.g., source terminal) coupled to a first source-drain terminal (e.g., drain terminal) of a pull-down circuit or transistor such as (NMOS) transistor M4. Transistor M3may have a gate terminal coupled to an output of NOR logic gate614that provides signal DRVP1. Transistor M4may have a second source-drain terminal (e.g., source terminal) coupled to a grounding structure providing a ground voltage and a gate terminal coupled to an output of NOR logic gate616that provides signal DRVN1.

Low-swing pre-driver logic circuit660may provide inputs to NOR logic gates614and616. In particular, low-swing pre-driver logic circuit660may include inverters662and672, OR logic gate664, and NAND logic gates666,674, and676. Inverter662may receive data signal txdin and generate a corresponding output that is provided to OR logic gate664as a first input. OR logic gate664may receive as a second input a (one clock cycle) shifted version of data signal txdin (e.g., data signal txdin_shift). OR logic gate664may generate an output (signal PREEMP) that is received as an input at NAND logic gate666. NAND logic gate666may also receive as an input data signal txdin. NAND logic gate666may generate an output. NOR logic gate614may receive the output of NAND gate666as a first input.

Inverter672may receive the output of inverter662as an input and generate a corresponding output that is provided to NOR logic gate616as an input. NAND logic gates674and676may receive signal lowswing_en as inputs. Additionally, NAND logic gate674may receive signal ndrv_selb as an additional input and generate an output supplied to NOR logic gate616as an input. NAND logic gate676may receive signal pdrv_sel as an additional input an generate an output supplied to NOR logic gate614as an input.

Low-swing driver306may include a driver output line (between transistors M3and M4) coupled to microbump522. Pre-emphasis circuit620may also be coupled to the output line. In particular, pre-emphasis circuit620may include a pull-up circuit having two (PMOS) transistors M5and M6coupled in series between voltage supply (rail)606providing supply voltage VCCL and the driver output line. The gate terminal of transistor M5may receive signal PREEMP from OR logic gate664. The gate terminal of transistor M6may receive signal EQ_G from equalization control logic circuit690. Control logic circuit690may receive control signal eq_en at level shifter692and generate a corresponding output that is supplied to NAND logic gate694as an input. NAND logic gate694may receive the output of level shifter682as an additional input and generate signal EQ_G.

Control signals pdrv_sel and ndrv_selb may determine the pull-up strength and pull-down strength of driver circuits (e.g., in low-swing driver306). If desired, the pull-up and pull-down strengths may be independently controlled by control signals pdrv_sel and ndrv_selb. Low-swing driver306may include multiple sets of driver circuits (e.g., circuits that include transistors M3, M4, M5, and M6, and logic gates614and616) coupled in parallel to supply a driver output to microbump522. Different numbers of sets of these parallel driver circuits may be activated as desired to implement suitable driving strength.

As shown in the illustrative example ofFIG. 6A, level shifters in driver circuitry may receive signals in the VCCL domain and shift them to the VCCH domain. Logic gates in pre-driver logic circuits630and660and low-swing driver306may receive voltage VCCL (e.g., operate in the VCCL domain), and logic gates in control logic circuits680and690and high-swing driver304may receive voltage VCCH (e.g., operate in the VCCH domain). In other words, high-swing driver304may receive only one positive power supply voltage. Low swing driver306may receive two different positive power supply voltages (e.g., pull-up transistor M3may receive a first positive power supply voltage and pre-emphasis circuit620may receive a second positive power supply voltage). If desired, electrostatic discharge (ESD) protection may be implanted using diodes699-1and699-2for driver output.

FIG. 6Bshows how transceiver logic300and driver circuitry302of the type shown inFIG. 6Amay be operate in a high-swing driver mode (e.g., mode400inFIG. 4). As an example, during the high-swing driver mode, low-swing control logic circuit680may receive signal lowswing_en at a logic ‘0’. Signal lowswing_en at a logic ‘0’ consequently propagate through low-swing pre-driver logic circuit660and generates signal DRVP1at a logic ‘0’ and signal DRVN1at a logic ‘0’. Consequently, transistors M3and M4are turned off by signals DRVP1and DRVN1, thereby deactivating low-swing driver306.

During the high-swing driver mode, equalization control logic circuit690may receive signal eq_en at a logic ‘0’ and generate a corresponding output signal EQ_G at a logic ‘1’. Consequently, transistor M6in pre-emphasis circuit620is turned off by signal EQ_G, and pre-emphasis circuit620is deactivated.

Based on the signals lowswing_en and lowswing_enb generated by low-swing control logic circuit680, high-swing driver304is activated. The driver output using high-swing driver304is based on input data signal txdin and shorted (common) voltage level VCCH/VCCL.

FIG. 6Cshows how transceiver logic300and driver circuitry302of the type shown inFIG. 6Amay operate in a low-swing driver mode with equalization (e.g., mode404inFIG. 4). As an example, during the low-swing driver mode with equalization, low-swing control logic circuit680may receive signal lowswing_en at a logic ‘1’. Low-swing control logic circuit680may generate signal lowswing_enb at a logic ‘0’. Signals lowswing_en and lowswing_enb may propagate through high-swing pre-driver logic circuit630and generate signal DRVP at a logic ‘1’ and signal DRVN at a logic ‘0’. Consequently, transistors M1and M2are turned off by signals DRVP and DRVN, thereby deactivating high-swing driver304.

During the low-swing driver mode with equalization, equalization control logic circuit690may receive signal eq_en at a logic ‘1’ and generate a corresponding output signal EQ_G at a logic ‘0’. Consequently, transistor M6in pre-emphasis circuit620remains turned on by signal EQ_G, and pre-emphasis circuit620is activated.

Based on signal lowswing_en, low-swing driver306is activated. The driver output using low-swing driver306is based on input data txdin and voltage levels VCCH and VCCL. Pre-emphasis circuit620may be selective turned on based on pull-up transistor M5since pull-up transistor M6remains turned on as long as equalization control logic circuit690receives control signal eq_en at a logic ‘1’.

FIG. 7shows an illustrative timing diagram for operating pre-driver logic for low-swing driver306and low-swing driver306with pre-emphasis circuit620of the type shown inFIGS. 6A and 6C. As shown inFIG. 7, signal txdin is the original data signal for transmission, signal txdin_shift is a one clock cycle delayed version of signal txdin, and signal txdinb is an inverted version of signal txdin (e.g., after signal txdinb passes through inverter662inFIG. 6A). To generate signal PREEMP, signal txdin_shift is OR'ed with signal txdinb (e.g., using OR gate664inFIG. 6A).

When signal PREEMP is at a logic ‘0’ to activate (PMOS) transistor M5(inFIG. 6C), driver output line is pre-emphasized to supply voltage VCCL (e.g., 0.8 V). As an example, at time t1, transistor M5may be activated (e.g., since signal PREEMP is at a logic ‘0’). Between time t1and t2, driver output line coupled to a microbump is pre-emphasized to supply voltage VCCL. At time t2, transistor M5may be deactivated (e.g., since signal txdin_shift raises signal PREEMP to a logic ‘1’ as indicated by arrow700) and transistor M4may be activated. This process may repeat during a high (e.g., maximum) frequency data rate transmission period such as from time t1to t3.

Beginning at time t3, driver circuitry may operate in a lower frequency data rate transmission period. At time t4, similar to time t1, transistor M5may be activated to pre-emphasize the driver output line to supply voltage VCCL. At time t4, transistor M5may be deactivated and, in contrast to time t2, transistor M3may be activated (e.g., since signals txdin and txdin_shift are both at logic ‘1’s), thereby providing voltage VCCH (e.g., 0.4 V) to the driver output line.

In general, driver circuitry of the type described in connection withFIGS. 3-7that include a high-swing driver, a low-swing driver, and equalization circuitry provide flexible communications circuitry between different dies. The driver circuitry removes undesirable DC voltage paths to ground present in other driving schemes to reduce power consumption while still meeting bandwidth demands. Additionally, the flexibility of operating the driver circuitry in multiple modes of operations provides increase potential for efficient communications between dies of different technology nodes. As the components of the driver circuitry are digital, this provides good scalability for any future technology nodes.

EXAMPLES

The following examples pertain to further embodiments.

Example 1 is an integrated circuit die, comprising: data transmission driver circuitry having a first output driver and a second output driver that are coupled to a shared output of the integrated circuit die, wherein the first output driver is operable to generate a first output signal having a first voltage swing, and wherein the second output driver is operable to generate a second output signal having a second voltage swing smaller than the first voltage swing.

Example 2 is the integrated circuit die of example 1, wherein the first output driver is optionally disabled if the second output driver is enabled, and wherein the second output driver is optionally disabled if the first output driver is enabled.

Example 3 is the integrated circuit die of any one of examples 1-2, wherein the first output driver optionally uses only one positive power supply voltage.

Example 4 is the integrated circuit die of any one of examples 1-2, wherein the second output driver optionally uses at least first and second different positive power supply voltages.

Example 5 is the integrated circuit die of any one of examples 1-4, wherein the second output driver optionally comprises equalization circuitry configurable in an enabled state and a disabled state.

Example 6 is the integrated circuit die of any one of examples 4-5, wherein the second output driver optionally comprises a first pull-up circuit supplied with the first positive power supply voltage, and wherein the equalization circuitry optionally comprises a second pull-up circuit supplied with the second positive power supply voltage.

Example 7 is the integrated circuit die of example 6, wherein the second pull-up circuit of the equalization circuitry optionally comprises: a first pull-up transistor configured to receive a first control signal; and a second pull-up transistor coupled in series with the first pull-up transistor, wherein the second pull-up transistor is configured to receive a second control signal that is different than the first control signal.

Example 8 is the integrated circuit die of example 7, wherein the first pull-up circuit is optionally controlled based on the first control signal.

Example 9 is the integrated circuit die of any one of examples 7-8, wherein the second output driver is optionally configured to receive a data signal and to transmit the data signal onto the shared output, and wherein the first control signal is optionally generated based on the data signal.

Example 10 is the integrated circuit die of example 9, optionally further comprising: pre-driver logic circuitry configured to receive the data signal and a delayed version of the data signal and to generate the first control signal.

Example 11 is transmitter circuitry, comprising: a pull-up circuit; a pull-down circuit coupled in series with the pull-up circuit; a transmitter output coupled between the pull-up circuit and the pull-down circuit; and a pre-emphasis circuit coupled to the transmitter output, wherein the pre-emphasis circuit is operable to be enabled and disabled and lacks a direct current ground path.

Example 12 is the transmitter circuitry of example 11, wherein the pull-up circuit optionally receives a first positive supply voltage and the pre-emphasis circuit receives a second positive supply voltage that is different than the first positive supply voltage.

Example 13 is the transmitter circuitry of example 12, further optionally comprising: a pre-driver logic circuit coupled to the pull-up circuit, the pull-down circuit, and the pre-emphasis circuit, wherein the pre-driver logic circuit is configured to receive only one positive supply voltage and the one positive supply voltage is the second positive supply voltage.

Example 14 is the transmitter circuitry of any one of examples 11-13, wherein an output data signal on the transmitter output is associated with an input data signal, wherein the pre-emphasis circuit optionally comprises a transistor interposed between a positive voltage supply and the transmitter output, and wherein the transistor is optionally configured to receive a control signal generated based on an inverted version of the input data signal and a delayed version of the input data signal.

Example 15 is the transmitter circuitry of example 14, wherein the pre-emphasis circuit optionally comprises an additional transistor coupled in series with the transistor, wherein the additional transistor is configured to receive an additional control signal indicative of whether the pre-emphasis circuit is in an enabled state.

Example 16 is an integrated circuit package, comprising: a package substrate; a first integrated circuit die mounted on the package substrate; and a second integrated circuit die mounted on the package substrate, wherein the first integrated circuit die comprises: transmitter logic configured to generate data signals; and driver circuitry configured to receive the data signals from the transmitter logic and to output signals to the second integrated circuit die, wherein the output signals are driven to a first positive power supply voltage when a pre-emphasis circuit in the driver circuitry is in an activated state and is driven to a second positive power supply voltage that is different than the first positive power supply voltage when the pre-emphasis circuit is in a deactivated state.

Example 17 is the integrated circuit package of example 16, wherein the first integrated circuit die is optionally coupled to the package substrate by a microbump and wherein the second integrated circuit die is optionally configured to receive the output signals through a die-to-die connection that includes a microbump and a conductive path in the package substrate.

Example 18 is the integrated circuit package of example 17, wherein the conductive path in the package substrate optionally comprises a conductive path in an Embedded Multi-Die Interconnect Bridge (EMIB) chip that is embedded in the package substrate.

Example 19 is the integrated circuit package of any one of examples 16-18, wherein the first integrated circuit die is optionally coupled to the package substrate by first and second bumps and wherein the driver circuitry is optionally configured to receive the first positive power supply voltage through the first bump and to receive the second positive power supply voltage through the second bump.

Example 20 is the integrated circuit package of example 19, wherein the first integrated circuit die optionally further comprises: additional driver circuitry configurable to receive the second positive power supply voltage through the second bump.

For instance, all optional features of the apparatus described above may also be implemented with respect to the method or process described herein. The foregoing is merely illustrative of the principles of this disclosure and various modifications can be made by those skilled in the art. The foregoing embodiments may be implemented individually or in any combination.