Lateral PNP-type transistor based on a vertical NPN-structure and process for producing such PNP-type transistor

A lateral PNP-type transistor, and a process for producing such lateral PNP-type transistor from a substrate are provided. In particular, a PNP-emitter and a PNP-collector. The PNP-collector is provided at a predetermined distance from the PNP emitter. The PNP-emitter is electrically insulated from the PNP-collector.

DETAILED DESCRIPTION OF THE INVENTION The preferred embodiment of the present invention and its advantages are best understood by referring now in more detail to the drawings which like numeral refer to like parts. A preferred embodiment of a lateral PNP-type transistor, and the process to manufacture such lateral PNP-type transistor is preferably based on the structure and production of a vertical NPN-type transistor. This embodiment provides that a base implant is blocked. In this manner, an ohmic connection between an NPN-emitter and an NPN-collector of the transistor is created, along with a production of a lateral series of P-, N-, P-type silicon which can be used for the PNP-type transistor. The NPN-base implant can be blocked, e.g., by electrically isolating or insulating two NPN-base poly-silicon connections on both sides of an NPN-emitter. Such arrangement can be obtained by, e.g., the use of a ring-shaped NPN-emitter with an inner NPN-base and an NPN-outer base. The NPN-connections of the NPN-type transistor can be corresponded to PNP-type connections of the PNP-type transistor in the following manner: 1 NPN PNP Emitter Base Base-inner Emitter Base-outer Collector Collector Base The method and lateral PNP-type transistor according to the present invention is advantageous in that the base width is not limited by lithography because the width of the base window (as shall be described below) is reduced by a spacer for the NPN-emitter. Additionally, the PNP base is formed in a self-aligned manner. Accordingly, no alignment tolerances important for lateral structures have to be taken into consideration. It is also conceivable to further modify the basic NPN process, e.g., by increasing the PNP base doping by an N-type implant through an emitter window. Exemplary process steps for manufacturing the lateral PNP-type transistor and the structure of the lateral PNP-type transistor according to the present invention are described in further detail below. In particular, this description is provided e.g., for the bipolar part of a BiCMOS process flow which can be used as a baseline process for the fabrication of the lateral PNP-type transistor. However, it should be understood that it is possible to utilize other process steps according to the present invention (e.g. pure bipolar manufacturing steps, alternative BiCMOS production steps, etc.). This is because for the production of the PNP-type transistor, only the general structure of the NPN-type transistor preferably utilized. FIG. 1 shows the first step of the exemplary process according to the present invention in which the formation of n- and p-type buried layers (or diffusion under film layers—DUFs) is effectuated. These DUFs are advantageously used for isolating or insulating certain devices. In particular, an oxide which has a thickness of, e.g., 800 nm is grown on the substrate 10 to form an oxide mask 110 . Then, this oxide mask 110 is patterned, and a highly N-doped region (NDUF) 100 is implanted into the substrate 10 . The NDUF 100 can later be used as a connection for a PNP-base base of the lateral PNP-type transistor according to the present invention (or for a NPN-collector of the conventional NPN-type transistor). FIG. 2 shows the second step of the exemplary process according to the present invention, in which the oxide mask 110 is removed, and a new oxide mask 115 is grown. FIG. 3 shows the third step of the exemplary process in which, after the removal of the oxide mask 110 , a P-type DUF (or PDUF) layer 120 can be implanted into the substrate 10 . The PDUF layer 120 can be unpatterned because its concentration is preferably lower than that of the NDUF 100 . FIG. 3 also shows that a silicon epitaxial layer 130 is grown on top of the PDUF layer 120 for a width of, e.g., 500 &mgr;&mgr;the present invention, in which a field oxide (FOX) 160 is grown for a width of, e.g., 620 nm, so as to isolate (or insulate) the adjacent elements from one another. Before such growth takes place, a nitride layer 50 is grown on the substrate 10 and then etched (along with a portion of the silicon epitaxial layer 130 ) as shown in FIG. 3 . Certain regions 165 of the substrate 10 that are not covered by the FOX 160 may later act as active areas of the respective elements or devices. FIG. 5 shows the fifth step of the process according to present invention in which a resist 170 is patterned to expose a contact of the base of the lateral PNP-type transistor (corresponding to the collector of the NPN-type transistor), and phosphorus is implanted in the substrate 10 at the exposed location 180 . In this manner, an N implant (DEEPN) 190 is formed to be the low resistive connection after patterning the resist 170 so as to form the PNP-base contact. FIG. 6 shows the sixth step of the process according to the present invention, in which the gate-oxide is grown, and which is then followed by a growth of poly-silicon 205 . Then, the poly-silicon is removed from all surfaces of the substrate, except from an NPN-type collector 200 . Then, as shown in FIG. 7 (i.e., step seven of the process), the layers of boron-silicon-glass (BSG) 210 and of SiN 220 are deposited on the surface of the substrate 10 . These layers of BSG 210 are used as a boron source to lower the extrinsic base resistance of the NPN-type transistor at certain surface areas of the substrate 10 , while removing the respective portions of this BSG/SiN stack 210 , 220 from other surface areas thereof. FIG. 8 shows the eighth step of the process according to the present invention. In this step, another poly-silicon layer 230 is grown on the substrate 10 , and then boron is implanted in the substrate 10 after patterning the poly-silicon layer 230 . At a later point, this layer 230 may act as a PNP-emitter and a PNP-collector FIG. 9 shows a ninth step of the exemplary process according to the present invention. In this step, after the deposition of an oxide layer 240 and patterning it, the BSG/SiN stack 210 , 220 is etched down to the substrate along the pattern used for etching the oxide 240 . Only small portions 250 , 260 of the BSG/SiN stack 210 , 220 remain on the sides of a patterned window 270 . After a resist 300 is removed from all areas except from the patterned window 270 , a thermal anneal drives the boron doping from base poly-silicon into the substrate 10 to form an extrinsic NPN-base 280 , and from the BSG 210 into the substrate 10 to form a base link 290 (as shown in FIG. 10 ). For the conventional NPN-type transistors, an NPN-intrinsic base is generally implanted into the substrate 10 . For the PNP-type transistor according to the present invention, the NPN-base implant is blocked, e.g., by a resist. This can be done by patterning an NPN-base block in the lateral PNP-type transistor. Thus, the resist blocks the base implant so as to prevent any boron to be provided in the window 270 . In this manner, the intrinsic base is defined. FIG. 11 shows the eleventh step of the exemplary process of the present invention, in which the self-aligned emitter (for the NPN) is defined, and which acts as a base for the PNP-type transistor according to the present invention. Initially, a stack of thin oxide 310 , nitride 320 , thick oxide 330 is deposited on the substrate 10 within the window 270 , and then it is anisotropically etched. The nitride 320 has a thickness of, e.g., 80 &mgr;m, and the thick oxide has a thickness of, e.g., 325 nm. Thus, the width of the PNP-base is defined as the width of the window 270 minus two (2) times the thickness of the thin oxide/nitride/thick oxide stack 310 , 320 , 330 . Thus, the width is not limited by the lithography. In addition, even smaller windows than for the NPN-type transistor can be used for the lateral PNP-type transistor of the present invention, if desired. As shown in FIG. 12, a high energy n-implant through the emitter window 270 preferably defines an NPN-sub-collector 350 . The concentration of the sub-collector 350 may also define the doping concentration of the PNP-base, and therefore of the gain of the PNP-type transistor. The emitter (of the NPN-type transistor which corresponds to the base of the PNP-type transistor) is defined by depositing an emitter poly-silicon 360 in the window 270 , implanting an arsenic for the emitter doping and driving-in the emitter 360 into the substrate 10 during the annealing procedure. The emitter poly-silicon 360 and the thin oxide 310 are then removed from the substrate after a patterning procedure on non-emitter areas. In FIG. 13 , the poly-silicon provided over the NPN-collector (corresponding to the PNP-base) contact 400 is removed after the deposition of this poly-silicon. Thereafter, in FIG. 14 , the gate poly-silicon for the MOS devices is patterned and etched. Then, nitride 350 is deposited on the substrate and etched to ensure isolation between the base and collector of the PNP-type transistor (i.e., the base and emitter of the NPN); the same is applicable for the Source/Drain and gate of MOS devices. Thereafter, titanium silicide (TiSi) 360 is formed on all areas, except on the nitride 350 for a better contact. The backend processing (contacts, metal, via, etc) has not been depicted, since the conventional process for their formation can be utilized. FIG. 14 also shows the resultant PNP-base 400 , which is provided between the PNP-emitter 420 and the PNP-collector 410 . In addition, another PNP-base 430 is shown in FIG. 14 . As clearly shown in this drawing, the PNP-emitter 420 is electronically insulated from the PNP-collector. Although the present invention has been described with a preferred embodiment, various changes and modifications may be suggested to one skilled in the art. It is intended that the present invention encompass such changes and modifications as falling within the scope of the appended claims.