Structure and formation method of semiconductor device with metal gate stack

A structure and a formation method of a semiconductor device are provided. The method includes forming a dummy gate stack over a semiconductor substrate and forming spacer elements over sidewalls of the dummy gate stack. The method also includes removing the dummy gate stack to form a recess between the spacer elements and forming a metal gate stack in the recess. The method further includes etching back the metal gate stack while the metal gate stack is kept at a temperature that is in a range from about 20 degrees C. to about 55 degrees C. In addition, the method includes forming a protection element over the metal gate stack after etching back the metal gate stack.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs. Each generation has smaller and more complex circuits than the previous generation.

However, these advances have increased the complexity of processing and manufacturing ICs. Since feature sizes continue to decrease, fabrication processes continue to become more difficult to perform. Therefore, it is a challenge to form reliable semiconductor devices at smaller and smaller sizes.

DETAILED DESCRIPTION

The term “substantially” in the description, such as in “substantially flat” or in “substantially coplanar”, etc., will be understood by the person skilled in the art. In some embodiments the adjective substantially may be removed. Where applicable, the term “substantially” may also include embodiments with “entirely”, “completely”, “all”, etc. Where applicable, the term “substantially” may also relate to 90% or higher, such as 95% or higher, especially 99% or higher, including 100%. Furthermore, terms such as “substantially parallel” or “substantially perpendicular” are to be interpreted as not to exclude insignificant deviation from the specified arrangement and may include for example deviations of up to 10°. The word “substantially” does not exclude “completely” e.g. a composition which is “substantially free” from Y may be completely free from Y.

Terms such as “about” in conjunction with a specific distance or size are to be interpreted so as not to exclude insignificant deviation from the specified distance or size and may include for example deviations of up to 10%. The term “about” in relation to a numerical value x may mean x±5 or 10%.

FIGS. 1A-1Nare cross-sectional views of various stages of a process for forming a semiconductor device structure, in accordance with some embodiments. As shown inFIG. 1A, a semiconductor substrate100is received or provided. The semiconductor substrate100includes regions10and20. In some embodiments, narrower gate stacks and wider gate stacks are designed to be formed over the regions10and20, respectively. In some embodiments, the distribution densities of the gate stacks over the regions10and20are different. In some embodiments, the distribution densities of the gate stacks over the region10is greater than the distribution densities of the gate stacks over the region20.

In some embodiments, the semiconductor substrate100is a bulk semiconductor substrate, such as a semiconductor wafer. For example, the semiconductor substrate100includes silicon or other elementary semiconductor materials such as germanium. The semiconductor substrate100may be un-doped or doped (e.g., p-type, n-type, or a combination thereof). In some embodiments, the semiconductor substrate100includes an epitaxially grown semiconductor layer on a dielectric layer. The epitaxially grown semiconductor layer may be made of silicon germanium, silicon, germanium, one or more other suitable materials, or a combination thereof.

In some other embodiments, the semiconductor substrate100includes a compound semiconductor. For example, the compound semiconductor includes one or more III-V compound semiconductors having a composition defined by the formula AlX1GaX2InX3AsY1PY2NY3SbY4, where X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative proportions. Each of them is greater than or equal to zero, and added together they equal 1. The compound semiconductor may include silicon carbide, gallium arsenide, indium arsenide, indium phosphide, one or more other suitable compound semiconductors, or a combination thereof. Other suitable substrate including II-VI compound semiconductors may also be used.

In some embodiments, the semiconductor substrate100is an active layer of a semiconductor-on-insulator (SOI) substrate. The SOI substrate may be fabricated using a separation by implantation of oxygen (SIMOX) process, a wafer bonding process, another applicable method, or a combination thereof. In some other embodiments, the semiconductor substrate100includes a multi-layered structure. For example, the semiconductor substrate100includes a silicon-germanium layer formed on a bulk silicon layer.

As shown inFIG. 1A, multiple fin structures102A and102B are formed, in accordance with some embodiments. In some embodiments, multiple recesses (or trenches) are formed in the semiconductor substrate100. As a result, multiple fin structures that protrude from the surface of the semiconductor substrate100are formed or defined between the recesses. In some embodiments, one or more photolithography and etching processes are used to form the recesses. In some embodiments, the fin structures102A and102B are in direct contact with the semiconductor substrate100.

However, embodiments of the disclosure have many variations and/or modifications. In some other embodiments, the fin structures102A and102B are not in direct contact with the semiconductor substrate100. One or more other material layers may be formed between the semiconductor substrate100and the fin structures102A and102B. For example, a dielectric layer may be formed between the semiconductor substrate100and the fin structures102A and102B.

Afterwards, isolation features (not shown) are formed in the recesses to surround a lower portion of the fin structures102A and102B, in accordance with some embodiments. The isolation features are used to define and electrically isolate various device elements formed in and/or over the semiconductor substrate100. In some embodiments, the isolation features include shallow trench isolation (STI) features, local oxidation of silicon (LOCOS) features, another suitable isolation feature, or a combination thereof.

In some embodiments, each of the isolation features has a multi-layer structure. In some embodiments, the isolation features are made of a dielectric material. The dielectric material may include silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), low-K dielectric material, another suitable material, or a combination thereof. In some embodiments, an STI liner (not shown) is formed to reduce crystalline defects at the interface between the semiconductor substrate100and the isolation features. Similarly, the STI liner may also be used to reduce crystalline defects at the interface between the fin structures and the isolation features.

In some embodiments, a dielectric material layer is deposited over the semiconductor substrate100. The dielectric material layer covers the fin structures102A and102B and fills the recesses between the fin structures. In some embodiments, the dielectric material layer is deposited using a flowable chemical vapor deposition (FCVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a spin coating process, one or more other applicable processes, or a combination thereof.

In some embodiments, a planarization process is performed to thin down the dielectric material layer and to expose the fin structures102A and102B. The planarization process may include a chemical mechanical polishing (CMP) process, a grinding process, an etching process, a dry polishing process, one or more other applicable processes, or a combination thereof. Afterwards, the dielectric material layer is etched back to below the top of the fin structures102A and102B. As a result, the remaining portions of the dielectric material layer form the isolation features. The fin structures102A and102B protrude from the top surface of the isolation features.

As shown inFIG. 1A, dummy gate stacks104A and104B are formed over the semiconductor substrate100, in accordance with some embodiments. The dummy gate stacks104A and104B partially cover and wrap around the fin structures102A and102B, respectively. As shown inFIG. 1A, the dummy gate stack104A has a width W1, and the dummy gate stack104B has a width W2. The width W2is greater than the width W1.

In some embodiments, each of the dummy gate stacks104A and104B has a dummy gate dielectric layer106and a dummy gate electrode108. The dummy gate dielectric layer106may be made of or include silicon oxide, silicon oxynitride, silicon nitride, one or more other suitable materials, or a combination thereof. The dummy gate electrode108may be made of or include a semiconductor material, such as polysilicon.

In some embodiments, a dielectric material layer and a gate electrode layer are sequentially deposited over the semiconductor substrate100and the fin structures102A and102B. The dielectric material layer may be deposited using a CVD process, an ALD process, a thermal oxidation process, a physical vapor deposition (PVD) process, one or more other applicable processes, or a combination thereof.

Afterwards, one or more photolithography processes and one or more etching processes may be used to partially remove the dielectric material layer and the gate electrode layer. As a result, the remaining portions of the dielectric material layer and the gate electrode layer form the dummy gate stacks104A and104B.

Afterwards, spacer elements110are formed over sidewalls of the dummy gate stacks104A and104B, as shown inFIG. 1Ain accordance with some embodiments. The spacer elements110may be used to protect the dummy gate stacks104A and104B and assist in subsequent processes for forming source/drain features and/or metal gates. In some embodiments, the spacer elements110are made of or include a dielectric material. The dielectric material may include silicon nitride, silicon oxynitride, silicon oxide, silicon carbide, one or more other suitable materials, or a combination thereof.

In some embodiments, a dielectric material layer is deposited over the semiconductor substrate100, the fin structures102A and102B, and the dummy gate stacks104A and104B. The dielectric material layer may be deposited using a CVD process, an ALD process, a spin coating process, one or more other applicable processes, or a combination thereof. Afterwards, the dielectric material layer is partially removed using an etching process, such as an anisotropic etching process. As a result, the remaining portions of the dielectric material layer over the sidewalls of the dummy gate stacks104A and104B form the spacer elements110.

As shown inFIG. 1B, epitaxial structures112A and112B are respectively formed over the fin structures102A and102B, in accordance with some embodiments. The epitaxial structures112A and112B may function as source/drain features. In some embodiments, the portions of the fin structures102A and102B that are not covered by the dummy gate stacks104A and104B are recessed before the formation of the epitaxial structures112A and112B. In some embodiments, the recesses laterally extend towards the channel regions under the dummy gate stacks104A and104B. For example, portions of the recesses are directly below the spacer elements110. Afterwards, one or more semiconductor materials are grown on sidewalls and bottoms of the recesses to form the epitaxial structures112A and112B.

In some embodiments, both the epitaxial structures112A and112B are p-type semiconductor structures. In some other embodiments, both the epitaxial structures112A and112B are n-type semiconductor structures. In some other embodiments, one of the epitaxial structures112A and112B is a p-type semiconductor structure, and another one is an n-type semiconductor structure.

A p-type semiconductor structure may include epitaxially grown silicon germanium or silicon germanium doped with boron. An n-type semiconductor structure may include epitaxially grown silicon, epitaxially grown silicon carbide (SiC), epitaxially grown silicon phosphide (SiP), or another suitable epitaxially grown semiconductor material.

In some embodiments, the epitaxial structures112A and112B are simultaneously formed. In some other embodiments, the epitaxial structures112A and112B are separately formed using separate processes, such as separate epitaxial growth processes. In some embodiments, a first mask element is used to cover the fin structure102B while the epitaxial structures112A are grown on the fin structure102A. Afterwards, the first mask element is removed, and a second mask element is formed to cover the epitaxial structures112A. The fin structure102B is exposed without being covered by the second mask element. Then, the epitaxial structure112B is grown on the fin structure102B. Afterwards, the second mask element is removed, and the structure shown inFIG. 1Bis obtained.

In some embodiments, the epitaxial structures112A and112B are formed by using a selective epitaxial growth (SEG) process, a CVD process (e.g., a vapor-phase epitaxy (VPE) process, a low pressure chemical vapor deposition (LPCVD) process, and/or an ultra-high vacuum CVD (UHV-CVD) process), a molecular beam epitaxy process, one or more other applicable processes, or a combination thereof.

In some embodiments, one or both of the epitaxial structures112A and112B are doped with one or more suitable dopants. For example, the epitaxial structures112A and112B are SiGe source/drain features doped with boron (B), indium (In), or another suitable dopant. Alternatively, in some other embodiments, one or both of the epitaxial structures112A and112B are Si source/drain features doped with phosphor (P), antimony (Sb), or another suitable dopant.

In some embodiments, the epitaxial structures112A and112B are doped in-situ during their epitaxial growth. In some other embodiments, the epitaxial structures112A and112B are not doped during the growth of the epitaxial structures112A and112B. Instead, after the formation of the epitaxial structures112A and112B, the epitaxial structures112A and112B are doped in a subsequent process. In some embodiments, the doping is achieved by using an ion implantation process, a plasma immersion ion implantation process, a gas and/or solid source diffusion process, one or more other applicable processes, or a combination thereof. In some embodiments, the epitaxial structures112A and112B are further exposed to one or more annealing processes to activate the dopants. For example, a rapid thermal annealing process is used.

As shown inFIG. 1C, an etch stop layer114and a dielectric layer116are sequentially deposited over the semiconductor substrate100and the epitaxial structures112A and112B, in accordance with some embodiments. The etch stop layer114may conformally extend along the surfaces of the spacer elements110and the epitaxial structures112A and112B. The dielectric layer116covers the etch stop layer114and surrounds the spacer elements110and the dummy gate stacks104A and104B.

The etch stop layer114may be made of or include silicon nitride, silicon oxynitride, silicon carbide, one or more other suitable materials, or a combination thereof. In some embodiments, the etch stop layer114is deposited over the semiconductor substrate100and the dummy gate stacks104A and104B using a CVD process, an ALD process, a PVD process, one or more other applicable processes, or a combination thereof.

The dielectric layer116may be made of or include silicon oxide, silicon oxynitride, borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), low-k material, porous dielectric material, one or more other suitable materials, or a combination thereof. In some embodiments, the dielectric layer116is deposited over the etch stop layer114and the dummy gate stacks104A and104B using a CVD process, an ALD process, a FCVD process, a PVD process, one or more other applicable processes, or a combination thereof.

Afterwards, a planarization process is used to remove upper portions of the dielectric layer116, the etch stop layer114, the spacer elements110, and the dummy gate stacks104A and104B. As a result, the top surfaces of the dielectric layer116, the etch stop layer114, the spacer elements110, and the dummy gate stacks104A and104B are substantially level with each other, which benefits subsequent fabrication processes. The planarization process may include a CMP process, a grinding process, an etching process, a dry polishing process, one or more other applicable processes, or a combination thereof.

As shown inFIG. 1D, the dummy gate stacks104A and104B are removed to form recesses118, in accordance with some embodiments. Each of the recesses118is between two of the spacer elements110that are opposite to each other. The recesses118expose portions of the fin structures102A and102B, as shown inFIG. 1D. One or more etching processes may be used to remove the dummy gate stacks104A and104B.

As shown inFIG. 1E, a gate dielectric layer120is deposited over the dielectric layer116, in accordance with some embodiments. The gate dielectric layer120extends into the recesses118along the sidewalls and bottoms of the recesses118. In some embodiments, the gate dielectric layer120conformally extends along the sidewalls of the recesses118.

In some embodiments, the gate dielectric layer120is made of or includes a dielectric material with high dielectric constant (high-K). The gate dielectric layer120may be made of or include hafnium oxide, zirconium oxide, aluminum oxide, hafnium dioxide-alumina alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, one or more other suitable high-K materials, or a combination thereof.

The gate dielectric layer120may be deposited using an ALD process, a CVD process, one or more other applicable processes, or a combination thereof. In some embodiments, the formation of the gate dielectric layer120involves a thermal operation.

In some embodiments, an interfacial layer is formed on the exposed surfaces of the fin structures102A and102B before the formation of the gate dielectric layer120. The interfacial layer may be used to improve adhesion between the gate dielectric layer120and the fin structures102A and102B. The interfacial layer may be made of or include a semiconductor oxide material such as silicon oxide or germanium oxide. The interfacial layer may be formed using a thermal oxidation process, an oxygen-containing plasma operation, one or more other applicable processes, or a combination thereof.

Afterwards, a work function layer122is deposited over the gate dielectric layer120, as shown inFIG. 1Ein accordance with some embodiments. In some embodiments, the work function layer122fills the remaining space of the recess118over the region10. In some embodiments, the work function layer122partially fills the recess118over the region20. The work function layer122extends into the recess118along the sidewalls of the recess118over the region20. In some embodiments, the work function layer122conformally extends along the sidewalls of the recess118over the region20.

The work function layer122may be used to provide the desired work function for transistors to enhance device performance including improved threshold voltage. In some embodiments, the work function layer122is used for forming an NMOS device. The work function layer122is an n-type work function layer. The n-type work function layer is capable of providing a work function value suitable for the device, such as equal to or less than about 4.5 eV.

The n-type work function layer may include metal, metal carbide, metal nitride, or a combination thereof. For example, the n-type work function layer includes titanium nitride, tantalum, tantalum nitride, one or more other suitable materials, or a combination thereof. In some embodiments, the n-type work function is an aluminum-containing layer. The aluminum-containing layer may be made of or include TiAlC, TiAlO, TiAlN, one or more other suitable materials, or a combination thereof.

In some embodiments, the work function layer122is used for forming a PMOS device. The work function layer122is a p-type work function layer. The p-type work function layer is capable of providing a work function value that is suitable for the device, such as equal to or greater than about 4.8 eV.

The p-type work function layer may include metal, metal carbide, metal nitride, other suitable materials, or a combination thereof. For example, the p-type metal includes tantalum nitride, tungsten nitride, titanium, titanium nitride, other suitable materials, or a combination thereof.

The work function layer122may also be made of or include hafnium, zirconium, titanium, tantalum, aluminum, metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, aluminum carbide), aluminides, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides, or a combinations thereof. The thickness and/or the compositions of the work function layer122may be fine-tuned to adjust the work function level. For example, a titanium nitride layer may be used as a p-type work function layer or an n-type work function layer, depending on the thickness and/or the compositions of the titanium nitride layer.

The work function layer122may be deposited over the gate dielectric layer120using an ALD process, a CVD process, a PVD process, an electroplating process, an electroless plating process, one or more other applicable processes, or a combination thereof.

In some embodiments, a barrier layer is formed before the work function layer122to interface the gate dielectric layer120with the subsequently formed work function layer122. The barrier layer may also be used to prevent diffusion between the gate dielectric layer120and the work function layer122. The barrier layer may be made of or include a metal-containing material. The metal-containing material may include titanium nitride, tantalum nitride, one or more other suitable materials, or a combination thereof. The barrier layer may be deposited using an ALD process, a CVD process, a PVD process, an electroplating process, an electroless plating process, one or more other applicable processes, or a combination thereof.

Afterwards, a conductive filling layer124is deposited over the work function layer122to fill the remaining space of the recess118over the region20, as shown inFIG. 1Ein accordance with some embodiments. The conductive filling layer124is made of or includes a metal material. The metal material may include tungsten, aluminum, copper, cobalt, one or more other suitable materials, or a combination thereof. The conductive filling layer124may be deposited using a CVD process, an ALD process, a PVD process, an electroplating process, an electroless plating process, one or more other applicable processes, or a combination thereof.

In some embodiments, a blocking layer is formed over the work function layer122before the formation of the conductive filling layer124. The blocking layer may be used to prevent the subsequently formed conductive filling layer124from diffusing or penetrating into the work function layer122. The blocking layer may be made of or include tantalum nitride, titanium nitride, one or more other suitable materials, or a combination thereof. The blocking layer may be deposited using an ALD process, a PVD process, an electroplating process, an electroless plating process, one or more other applicable processes, or a combination thereof.

Many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, upper portions of the spacer elements110are partially removed to enlarge the recesses118before the depositions of the gate dielectric layer120, the work function layer122, and the conductive filling layer124. An anisotropic etching process may be used to partially remove the spacer elements110. Since the upper portions of the recesses118are widened, the subsequent deposition processes of the gate dielectric layer120, the work function layer122, and the conductive filling layer124may become easier.

As shown inFIG. 1F, a planarization process is performed to remove the portions of the gate dielectric layer120, the work function layer122, and the conductive filling layer124that are outside of the recesses118, in accordance with some embodiments. As a result, the remaining portions of the gate dielectric layer120and the work function layer122form a metal gate stack126A. The remaining portions of the gate dielectric layer120, the work function layer122, and the conductive filling layer124form a metal gate stack126B. The planarization process may include a CMP process, a grinding process, an etching process, a dry polishing process, one or more other applicable processes, or a combination thereof.

As shown inFIG. 1G, a cleaning treatment128is performed on the surfaces of the metal gate stacks126A and126B, in accordance with some embodiments. The cleaning treatment128may be used to remove native oxide materials that are grown on the surfaces of the work function layer122and the conductive filling layer124. After the removal of the native oxide materials, subsequent processes may be performed more smoothly.

In some embodiments, the cleaning treatment128involves a plasma treatment on the metal gate stacks126A and126B.FIG. 2shows a process chamber201used in some stages of a process for forming a semiconductor device structure, in accordance with some embodiments. In some embodiments, the cleaning treatment128is performed in the process chamber201.

In some embodiments, the process chamber201includes a plasma provider202and a substrate holder204. The plasma provider202may excite a provided reaction gas mixture into plasma. Then, the generated plasma may be directed onto the surface of the semiconductor substrate100for performing the cleaning treatment128. The substrate holder204may be used to hold the semiconductor substrate100. The substrate holder204may also be used to apply bias to the semiconductor substrate100and/or change the temperature of the semiconductor substrate100.

In some embodiments, the reaction gas mixture used in the cleaning treatment128includes Cl2, O2, and N2. The processing pressure of the process chamber201may be kept in a range from about 1 mtorr to about 5 mtorr. The power used for exciting the reaction gas mixture into plasma may be in a range from about 300 W to about 800 W. The bias applied to the semiconductor substrate100may be in a range from about 50 V to about 150 V. The duty cycle may be in a range from about 10 to about 30. The operation time of the cleaning treatment128may be in a range from about 5 seconds to about 15 seconds.

As shown inFIG. 1H, a protection layer130is formed on the surfaces treated by the cleaning treatment128, in accordance with some embodiments. In some embodiments, the protection layer130is in-situ formed in the process chamber201right after the cleaning treatment128without taking the semiconductor substrate100out of the process chamber201. Therefore, new native oxide materials are prevented from being grown on the surfaces of the metal gate stacks126A and126B. In some embodiments, the protection layer130is made of or includes a polymer material.

In some embodiments, the formation of the protection layer130involves using plasma. In some embodiments, the reaction gas mixture used for forming the protection layer130includes Cl2, BCl3, CH4, and Ar. The processing pressure of the process chamber201may be kept in a range from about 1 mtorr to about 6 mtorr. The power used for exciting the reaction gas mixture into plasma may be in a range from about 300 W to about 800 W. The bias applied to the semiconductor substrate100may be in a range from about 20 V to about 50 V. The duty cycle may be in a range from about 20 to about 50. The operation time for forming the protection layer130may be in a range from about 10 seconds to about 60 seconds.

In some embodiments, the protection layer130has a greater deposition rate over the region20than over the region10since the distribution densities of the metal gate stacks over the regions10and20are different. The portion of the protection layer130over the region10is formed to have a thickness T1. The portion of the protection layer130over the region20is formed to have a thickness T2. In some embodiments, the thickness T2is greater than the thickness T1. The protection layer130may be used to control or balance the etching loading on the metal gate stacks126A and126B that have different widths.

As shown inFIG. 1I, an etching back process is used to remove the protection layer130and upper portions of the metal gate stacks126A and126B, in accordance with some embodiments. As a result, recesses132are formed, as shown inFIG. 1I. Due to the protection layer130that controls or balances the etching loading of different regions10and20, the recesses132over the regions10and20have substantially the same depth.

In some embodiments, the etching back process is a dry etching process that involves using plasma. In some embodiments, the etching back process is performed at a low temperature, which allows a high etching selectivity between the work function layer122(or the conductive filling layer124) and the gate dielectric layer120. In some embodiments, the dry etching process partially remove the work function layer122and the conductive filling layer124while the gate dielectric layer120is substantially not etched or only slightly etched. The gate dielectric layer120may protect the inner sidewalls of the spacer elements110. Therefore, the spacer elements110may sustain without being damaged during a subsequent etching process for forming contact holes that expose the metal gate stacks126A and126B.

In some embodiments, the etching back process is in-situ performed in the process chamber201right after the formation of the protection layer130without taking the semiconductor substrate out of the process chamber201. In some embodiments, the reaction gas mixture used in the etching back process includes a first halogen-containing gas and a second halogen-containing gas. The second halogen-containing gas has a greater molecular weight than that of the first halogen-containing gas. The first halogen-containing gas may include Cl2, F2, or another suitable gas. The second halogen-containing gas may include BCl3, SiCl4, or another suitable gas. In some embodiments, the reaction gas mixture further includes an inert gas. The inert gas may include Ar, He, Ne, Kr, Xe, or Rn.

In some embodiments, the first halogen-containing gas is provided at a first flow rate, and the second halogen-containing gas is provided at a second flow rate. In some embodiments, the first flow rate is faster than the second flow rate. The first flow rate of the first halogen-containing gas may be in a range from about 50 standard cubic centimeters per minute (sccm) to about 500 sccm. The second flow rate of the second halogen-containing gas may be in a range from about 5 sccm to about 100 sccm. The flow rate of the inert gas may be in a range from about 1 sccm to about 1000 sccm. However, in some other embodiments, the inert gas is not used.

The processing pressure of the process chamber201for performing the etching back process may be kept in a range from about 2 mtorr to about 20 mtorr. The power used for exciting the reaction gas mixture into plasma may be in a range from about 200 W to about 900 W. The bias applied to the semiconductor substrate100may be in a range from about 50 V to about 150 V. The duty cycle may be in a range from about 3 to about 20. The operation time of the etching back process may be in a range from about 50 seconds to about 450 seconds.

As mentioned above, the etching back process is performed at a low temperature, so as to provide a high etching selectivity between the work function layer122(or the conductive filling layer124) and the gate dielectric layer120. The substrate holder shown inFIG. 2may be used to keep the semiconductor substrate100as well as the metal gate stacks126A and126B at a desired operation temperature. The operation temperature may be in a range from about 20 degrees C. to about 55 degrees C. In some other embodiments, the operation temperature is in a range from about 45 degrees C. to about 50 degrees C.

By using the low operation temperature, both the etching rate of the gate dielectric layer120and the etching rate of the work function layer122(or the conductive filling layer124) are reduced. At the operation temperature range mentioned above, in some embodiments, the reduction in the etching rate of the gate dielectric layer120is much greater than the reduction in the etching rate of the work function layer122(or the conductive filling layer124). The etching of the work function layer122(or the conductive filling layer124) becomes a little bit slower while the etching of the gate dielectric layer120becomes much slower. Therefore, the etching selectivity between the work function layer122(or the conductive filling layer124) and the gate dielectric layer120is significantly increased. In some embodiments, the etching selectivity of the work function layer122to the gate dielectric layer120is increased to be over 15 or even over 17.

In some other cases, the operation temperature is not in the range mentioned above. In some cases, if the operation temperature is high (such as higher than about 55 degrees C. or higher than about 80 degrees C.), the etching selectivity between the work function layer122(or the conductive filling layer124) and the gate dielectric layer120might not be sufficient. A greater amount of gate dielectric layer120may be removed. Upper portions of the inner sidewalls of the spacer elements110are thus exposed without being protected by the gate dielectric layer120. As a result, the spacer elements110may be damaged if contact holes are subsequently formed to expose the metal gate stacks126A and126B. The contact holes might penetrate through the spacer elements110to expose conductive contacts electrically connected to the epitaxial structures112A and/or112B. Short circuiting between the metal gate stacks and the epitaxial structures may be formed.

In some other cases, if the operation temperature is lower than about 20 degrees C., the etching back process may be too slow due to the low temperature. The wafer throughput may be reduced too much, which is also not desired.

Many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, the reaction gas mixture used in the etching back process further includes an oxygen-containing gas. The oxygen-containing gas may include O2, O3, NO, NO2, or another suitable gas. By adding the oxygen-containing gas, the etching rate of the gate dielectric layer120may be reduced further. It might be possible that the plasma generated from the oxygen-containing gas reacts with the second halogen-containing gas or the plasma generated from the second halogen-containing gas. As a result, the resulted plasma may have radicals that substantially do not react with the gate dielectric layer120. Therefore, the etching selectivity of the work function layer122(or the conductive filling layer124) to the gate dielectric layer120is significantly increased.

The flow rate of the oxygen-containing gas may be in a range from about 1 sccm to about 20 sccm. In some embodiments, the ratio of the flow rate of the oxygen-containing gas to the flow rate of the second halogen-containing gas is in a range from about 0.05 to about 0.6.

In some cases, if the flow rate ratio is greater than about 0.6, the flow rate of the oxygen-containing gas may be too high. The metal gate stacks126A and126B might have the risk to be oxidized, which might degrade the performance of the metal gate stacks126A and126B.

As shown inFIG. 1J, protection elements134A and134B are formed in the recesses132, in accordance with some embodiments. In some embodiments, the top surfaces of the protection elements134A and134B are substantially level with the top surface of the dielectric layer116. In some embodiments, the protection elements134A and134B are made of or include a dielectric material. The dielectric material may include silicon nitride, silicon carbide, silicon carbon nitride, silicon oxynitride, one or more other suitable materials, or a combination thereof. In some embodiments, the protection elements134A and134B are substantially free of oxygen.

In some embodiments, a protection material layer is deposited over the structure shown inFIG. 1Ito overfill the recesses132. The protection material layer may be deposited using a CVD process, an ALD process, a FCVD process, a spin-on process, another applicable process, or a combination thereof.

Afterwards, the portion of the protection material layer outside of the recess132is removed, in accordance with some embodiments. As a result, the remaining portions of the protection material layer in the recess132form the protection elements134A and134B, as shown inFIG. 1J. In some embodiments, a planarization process is used to partially remove the protection material layer outside of the recesses132. The planarization process may include a CMP process, a grinding process, an etching process, a dry polishing process, one or more other applicable processes, or a combination thereof.

As shown inFIG. 1K, conductive contacts136A and136B are formed in the dielectric layer116, in accordance with some embodiments. The conductive contacts136A and136B further penetrate through the etch stop layer114to be electrically connected to the epitaxial structures112A and112B, respectively. The conductive contacts136A and136B may be made of or include cobalt, tungsten, ruthenium, aluminum, copper, gold, one or more other suitable materials, or a combination thereof.

In some embodiments, one or more photolithography processes and one or more etching processes are used to form contact holes that expose the epitaxial structures112A and112B. Afterwards, metal-semiconductor compound regions (such as metal silicide regions) may be formed on the expose surfaces of the epitaxial structures112A and112B. Barrier layers or barrier regions may be formed along the sidewalls of the contact holes. Then, a conductive material is deposited to overfill the contact holes. A planarization process is performed to remove the portion of the conductive material outside of the contact holes. As a result, the remaining portions of the conductive material inside the contact holes form the conductive contacts136A and136B.

As shown inFIG. 1L, an etch stop layer138and a dielectric layer140are sequentially deposited over the structure shown inFIG. 1K, in accordance with some embodiments. The material and formation method of the etch stop layer138may be the same as or similar to those of the etch stop layer114. The material and formation method of the dielectric layer140may be the same as or similar to those of the dielectric layer116. A planarization process is then used to provide the dielectric layer140with a substantially planar top surface. The planarization process may include a CMP process, a grinding process, an etching process, a dry polishing process, one or more other applicable processes, or a combination thereof.

As shown inFIG. 1M, contact openings142are formed to expose the metal gate stacks126A and126B, in accordance with some embodiments. The contact openings142penetrate through the dielectric layer140, the etch stop layer138, and the protection elements134A and134B. One or more photolithography processes and one or more etching processes may be used to form the contact openings142. In some embodiments, an overlay shift might occur such that the gate dielectric layer120is exposed by the conduct opening142.

During the etching process for forming the contact openings142, the spacer elements110are protected by the gate dielectric layer120. The etchant is prevented from penetrating through the spacer elements110and reaching the conductive contacts136A and/or136B. The conductive contacts136A and136B are protected by the gate dielectric layer120, the spacer elements110, and the etch stop layer114without being exposed by the contact openings142. Short circuiting between the conductive contacts136A (or136B) and other conductive structures to be formed in the contact openings142is prevented.

As shown inFIG. 1N, conductive contacts144A and144B are formed in the contact openings142, in accordance with some embodiments. The conductive contacts144A and144B form electrical connections to the metal gate stacks126A and126B, respectively. The conductive contacts144A and144B may be made of or include tungsten, ruthenium, cobalt, copper, aluminum, gold, one or more other suitable materials, or a combination thereof. Due to the protection of the gate dielectric layer120, the conductive contacts144A and144B and the conductive contacts136A and136B are prevented from being electrically shorted together.

In some embodiments, metal-semiconductor compound regions (such as metal silicide regions) are formed on the surfaces of the metal gate stacks126A and126B exposed by the contact openings142shown inFIG. 1M. Barrier layers or barrier regions may be formed along the sidewalls of the contact openings142. Then, a conductive material is deposited to overfill the contact openings142. A planarization process is performed to remove the portion of the conductive material outside of the contact openings142. As a result, the remaining portions of the conductive material inside the contact openings142form the conductive contacts144A and144B.

FIGS. 3A-3Bare cross-sectional views of various stages of a process for forming a semiconductor device structure, in accordance with some embodiments. As shown inFIG. 3A, a structure similar to the structure shown inFIG. 1Iis received or formed. In some embodiments, the gate dielectric layer120is slightly etched during the etching back process even if the etching selectivity of the work function layer122to the gate dielectric layer has been significantly increased due to the low operation temperature and/or the adding of the oxygen-containing gas.

As shown inFIG. 3A, the top of the spacer element110is higher than the top of the gate dielectric layer120by a height difference H1. The top of the gate dielectric layer120is higher than the top of the work function layer122by a height difference H2. Due to the slow etching rate of the gate dielectric layer120, the height difference H1is smaller than the height difference H2. In some embodiments, the ratio (H1/H2) of the height difference H1to the height difference H2is smaller than about 1/14. In some cases, if the ratio (H1/H2) is greater 1/14, the height difference H1may be too large. As a result, the gate dielectric layer120might not be able to provide sufficient protection to the spacer elements110.

Afterwards, the processes the same as or similar to the processes illustrated inFIGS. 1J-1Lare performed, in accordance with some embodiments. As a result, the structure shown inFIG. 3Bis formed.

In some embodiments, the conductive contact144A is in direct contact with the gate dielectric layer120. In some embodiments, the conductive contact144A is in direct contact with the spacer element110. Since the gate dielectric layer120is only etched slightly, the exposed area of the spacer element110is small. The gate dielectric layer120still provides sufficient protection to the spacer elements110. The spacer element110is prevented from being damaged. The electrical isolation between the conductive contacts144A and112A is ensured. The performance and reliability of the semiconductor device structure are maintained.

Embodiments of the disclosure relate to a gate replacement process for forming a metal gate stack. The metal gate stack includes a gate dielectric layer and a work function layer. Afterwards, the metal gate stack is etched back to form space for containing a protection element. The etching back process is performed at a low temperature to ensure high etching selectivity of the work function layer to the gate dielectric layer. The gate dielectric layer is substantially not etched or slightly etched. The gate dielectric layer is capable of protecting spacer elements beside the metal gate stack to sustain a subsequent etching process for forming a contact opening to the metal gate stack. The performance and reliability of the semiconductor device structure are greatly improved.

In accordance with some embodiments, a method for forming a semiconductor device structure is provided. The method includes forming a dummy gate stack over a semiconductor substrate and forming spacer elements over sidewalls of the dummy gate stack. The method also includes removing the dummy gate stack to form a recess between the spacer elements and forming a metal gate stack in the recess. The method further includes etching back the metal gate stack while the metal gate stack is kept at a temperature that is in a range from about 20 degrees C. to about 55 degrees C. In addition, the method includes forming a protection element over the metal gate stack after etching back the metal gate stack.

In accordance with some embodiments, a method for forming a semiconductor device structure is provided. The method includes forming a metal gate stack over a fin structure. The method also includes removing an upper portion of the metal gate stack using an etching process while the metal gate stack is kept at a temperature that is in a range from about 20 degrees C. to about 55 degrees C. A reaction gas mixture used in the etching process includes a first halogen-containing gas and a second halogen-containing gas. The second halogen-containing gas has a greater molecular weight than that of the first halogen-containing gas. The first halogen-containing gas is provided at a first flow rate, and the second halogen-containing gas is provided at a second flow rate. The first flow rate is faster than the second flow rate. The method further includes forming a protection element over the metal gate stack after the upper portion of the metal gate stack is removed.

In accordance with some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a metal gate stack over the semiconductor substrate. The metal gate stack includes a gate dielectric layer and a work function layer over the gate dielectric layer. The semiconductor device structure also includes a spacer element over a sidewall of the metal gate stack. A top of the spacer element is higher than a top of the gate dielectric layer by a first height difference. The top of the gate dielectric layer is higher than a top of the work function layer by a second height difference. A ratio of the first height difference to the second height difference is smaller than about 1/14.