Voltage boost circuit

A voltage boost circuit for eDram using thin oxide field effect transistors (FETs) is disclosed. The voltage boost circuit includes a boost capacitor which is precharged with a precharge voltage in a precharge stage and which provides a boosted supply voltage to a thin oxide FET during a pump phase. The voltage boost circuit further include a drive capacitor which provides a turn on voltage to the thin oxide FET so that the boosted supply voltage can pass to an output node in the pump phase.

FIELD OF THE INVENTION

The invention relates to semiconductor structures and, more particularly, to a voltage boost circuit for eDram using thin oxide field effect transistors (FETs).

BACKGROUND

A voltage boost circuit or charge pump is an electronic circuit that uses capacitors for energy storage to create a higher voltage power source. By way of one implementation, voltage boost circuits are needed for eDram's boosted word line VPP, and negative word line off voltage, VWL.

A challenge with charge pumps is that when creating a higher voltage power source, e.g., two or three times a supply voltage, voltages may be generated in excess of the oxide-stress limit of a field effect transistor (FET), i.e., a stress limit of the gate oxide thickness. That is, node voltages within a voltage boost circuit can exceed the reliability limits of maximum Vdd voltage. This may cause a failure of the charge pump and hence fail to provide the required voltage boost.

To overcome these reliability issues, FET devices are designed to have an oxide stress limit greater than the output voltage of the pumping system. Such a design requires a thick oxide which results in a low performance device. For example, these low performance thick-oxide FETs have a Vt of about 500 mv at worst case, and low voltage pump operation is poor and limited to about 750 mv. Thick-oxide FETs also use VPP-boosted phases which must be distributed to all pump banks and burn C(VPP)2power. Vds stresses can also be remedied by stacking FETs to share the high differential voltage; however, this is expensive and requires a large amount of chip space.

SUMMARY

In an aspect of the invention, a voltage boost circuit comprises a boost capacitor which is precharged with a precharge voltage in a precharge stage and which provides a boosted supply voltage to a thin oxide FET during a pump phase. The voltage boost circuit further comprises a drive capacitor which provides a turn on voltage to the thin oxide FET so that the boosted supply voltage can pass to an output node in the pump phase.

In an aspect of the invention, a voltage boost circuit comprises a boost capacitor, a drive capacitor and a thin oxide FET. The boost capacitor and the drive capacitor have a precharge voltage provided in a precharge phase. In a pump phase, a power supply voltage is added to the precharge voltage of the boost capacitor to obtain a boosted output voltage passed through the thin oxide FET to an output node when the thin oxide FET is turned on by the precharge voltage of the drive capacitor applied at a gate node of the thin oxide FET.

In an aspect of the invention, a method comprises: precharging a first capacitor and a second capacitor with a precharge voltage during a precharge phase; boosting the precharge voltage of the first capacitor to a boosted output voltage during a pump phase; turning on a thin oxide FET by providing the precharge voltage of the second capacitor to a gate node of the thin oxide FET; and passing the boosted output voltage through the thin oxide FET to an output node when the thin oxide FET is turned on.

In another aspect of the invention, a design structure tangibly embodied in a machine readable storage medium for designing, manufacturing, or testing an integrated circuit is provided. The design structure comprises the structures of the present invention. In further embodiments, a hardware description language (HDL) design structure encoded on a machine-readable data storage medium comprises elements that when processed in a computer-aided design system generates a machine-executable representation of the voltage boost circuit, which comprises the structures of the present invention. In still further embodiments, a method in a computer-aided design system is provided for generating a functional design model of the voltage boost circuit. The method comprises generating a functional representation of the structural elements of the voltage boost circuit.

DETAILED DESCRIPTION

The invention relates to semiconductor structures and, more particularly, to a voltage boost circuit for eDram using thin oxide field effect transistors (FETs). Advantageously, for example, gate bias circuits of the voltage boost circuit are designed to have a function of a boosted internal voltage to provide a gate level to safely turn on a thin-oxide PFET. That is, the present invention provides a structure and method of developing a FET on-gate voltage which is controlled to a level less than the reliability limit set by the maximum power supply voltage.

More specifically, the present invention is directed to a voltage boost circuit wherein a 2-terminal capacitor is charged to a power supply level in a precharge phase, and both terminals of the capacitor are disconnected from the power supply level in a pump phase and connected to a gate and source of an output FET to limit the gate-to-source oxide stress to a voltage determined by the power supply level. In implementation, the capacitor can be precharged to Vdd, and both terminals can be switched across Vgs of the output FET to provide an on-voltage Vgs of Vdd, or less. Reliability limits are thus set to the Vdd supply voltage.

The voltage boost circuit of the present invention can be manufactured in a number of ways using a number of different tools. In general, though, the methodologies and tools are used to form structures with dimensions in the micrometer and nanometer scale. The methodologies, i.e., technologies, employed to manufacture the voltage boost circuit of the present invention have been adopted from integrated circuit (IC) technology. For example, the structures of the present invention are built on wafers and are realized in films of material patterned by photolithographic processes on the top of a wafer. In particular, the fabrication of the voltage boost circuit of the present invention uses three basic building blocks: (i) deposition of thin films of material on a substrate, (ii) applying a patterned mask on top of the films by photolithographic imaging, and (iii) etching the films selectively to the mask.

FIG. 1shows a schematic diagram of a voltage boost circuit in accordance with aspects of the present invention. In embodiments, the voltage boost circuit100is a two stage voltage pump circuit that generates an output, boosted voltage on output node VPP. By way of example, the two stages of the voltage boost circuit100include a precharge phase and a boost/pump phase. In the precharge phase of the voltage boost circuit100, capacitor C0and capacitor C1will be precharged to Vdd; whereas, in the boost/pump phase, the precharged voltage of capacitor C0will be added to Vdd (and the precharged voltage of capacitor C1will be provided as a gate voltage GATEP (to open a FET T3and reduce the voltage difference between the source and drain) in order to boost the output voltage at output node VPP.

In embodiments, the boosted voltage on output node VPP is approximately 2× a supply voltage, Vdd. For example, an output boosted voltage of approximately 2.0 V at node VPP can be obtained with a supply voltage Vdd of approximately 1V. In contrast to conventional voltage boost circuits, the voltage boost circuit100of the present invention can provide the boosted voltage output voltage using lower voltage limit FETs, e.g., thin gate oxide FETs, without sacrificing reliability and performance. For example, the voltage boost circuit100may use an approximately10-Angstrom gate oxide thickness FET (T3) that can only withstand a gate oxide stress voltage of approximately 1.0 V. In more specific embodiments, the voltage boost circuit100comprises the following thin oxide, high performance FETs with exemplary gate widths: (i) T1=15μ; (ii) T2, T3=10μ; (iii) T4=15μ; (iv) T5, T8, T9, T10, T15=2μ; (v) T6, T14, T19, T20, T22, T26=1μ; (vi) T7, T11, T12, T13, T21,T27=640 nm; and (vii) T17=4μ. In embodiments, FETs T1-T4are connected to output node VPP.

In embodiments, the precharge phase of the voltage boost circuit100will precharge the capacitor C0to Vdd, e.g., 1 V. The precharging phase can be performed by turning on FETs T4and T2. In this way, FET T4can precharge the capacitor C0to Vdd, e.g., 1 V, while FET T2can connect node L1to 0 V. In the boost/pump phase, FETs T4and T2are turned off, and FET T1is turned on. This will lift node L1to Vdd, e.g., 1 V, so that it can be added to the voltage Vdd of the precharged capacitor C0. This, in turn, will bring the voltage at node V1to 2× supply voltage, e.g., 2 V. The boosted voltage can then be passed through FET T3to output node VPP.

As to not overstress FET T3, e.g., exceed its oxide reliability (Vdd in this example), FET T3remains turned off until output gate voltage at node GATEP can be appropriately charged by drive-cap precharge circuit200(during the boost phase). That is, the drive-cap precharge circuit200will generate a gate voltage at node GATEP (e.g., V1−Vdd) which, in turn, can be applied across the gate and source of FET T3. As should be understood by those of skill in the art, not only will the gate voltage of node GATEP turn on the FET T3, it will also provide an on-voltage across the FET T3which is below its reliability limit, e.g., the voltage difference between the source and drain of FET T3will not exceed the reliability limit of FET T3(e.g., V1−Vdd). By turning on FET T3with the gate voltage of node GATEP, the 2× supply voltage, e.g., 2 V, at node V1can pass through FET T3to the output node VPP.

Referring to the control of the drive-cap precharge circuit200, during the precharge phase, capacitor C1can be precharged to Vdd (e.g., 1 V) by two activation signals: (i) a high input clock signal B makes XL1node low to turn on FET T21; and (ii) a high input clock signal BBUF to turn on FET T27and bring CAPL to GND (e.g., 0 V). In the precharge phase, XOFFN will also restore node GATEP to a high voltage, VPP, by turning on FET T5, thus ensuring that FET T3remains turned off (e.g., is not overstressed) until the boost/pump phase. Also, in the precharge phase, capacitors C0and C1will have the same voltage, e.g., 1 V.

After the precharge phase (e.g., during the boost/pump phase), FETs T2, T4, T5, T21are turned off and Vdd (1 V) of capacitor C1is supplied to node GATEP of FET T3as a gate voltage (V1−Vdd). In more specific embodiments, due to parasitic capacitance, the gate voltage at node GATEP is (V1−Vdd)/C1/(C1+Cp)), where Cp is a parasitic capacitance. As described in more detail herein, gate voltage is provided at node GATEP by turning on isolation FETs T6and T26. As noted herein, the gate voltage, e.g., V1−Vdd, turns on FET T3, while also ensuring that FET T3will not exceed its reliability limit, e.g., be overstressed. That is, the gate voltage of node GATEP will lower the voltage of node V1to within acceptable limits for a thin oxide device. It should thus be understood that FETs T5, T6and T26can control the output gate voltage of node GATEP, and pass an on-gate voltage equal to or less than V1−Vdd to FET T3. Accordingly, in this way, the drive-cap precharge circuit200will ensure that the voltage across FET T3will always be less than the reliability limit.

In embodiments, the transfer control circuit300provides a restore signal XL1to the drive-cap precharge circuit200, e.g., FET T21, and FET T26. For example, XL1can provide control for connecting the CAPH and CAPL terminals to Vdd and GND, respectively, in the precharge phase when BBUF is high and XL1is at GND (low). More specifically, during the precharge phase, a high input clock signal B will be inverted through FETs T19and T25, resulting in a low XLI signal. The low XLI signal will turn on FET T5. This low XLI signal will also turn off (control) FET T26. In contrast, during the boost/pump phase, input signal B is low, which turns off the FETs T27and T21, allowing the nodes of C1to float. Also, during the boost/pump phase, a high V1signal passes through FET T17and turns on FET T26, allowing conduction between CAPL and GATEP, e.g., passing the precharge voltage of C1to node GATEP of FET T3.

In embodiments, RBIAS generator circuit400can tailor the current of RBIAS during the precharge phase and boost/pump phase to provide a functional transfer of signal XL1to the drive-cap precharge circuit200, allowing CAPL to connect to the GATEP node of FET T3during, e.g., the boost/pump phase. In embodiments, the RBIAS generator circuit400will also generate an RBIAS signal to control FET T17(of the transfer control circuit300) which, in turn, provides the high V1signal to turn off the FET T3. In embodiments, the RBIAS is a function of VCMN, e.g., a bandgap voltage reference, and is preferably at a voltage level between Vdd and GND. For example, in embodiments, the RBIAS generator circuit400produces a bias voltage of about 2-Vt below the boosted node voltage V1. In embodiments, RBIAS voltage level is high when the input voltage V1rises. The RBIAS voltage will also rise close to power supply, Vdd when input BBUF is low.

FIG. 2shows input timing clocks using the voltage boost circuit ofFIG. 1, in accordance with aspects of the present invention. In embodiments, the voltage boost circuit is run by 2-non-overlapping phases A and B, and a translated version of A which cycles between VPP and VPP2. Voltage VPP2is a regulated voltage chosen to be approximately VPP−Vdd_max, where Vdd_max is the highest Vdd allowed by the limitations of gate-oxide and other technology related limits. Input VCMN is a current minor voltage which produces a 15 μa current through a 1μ/480 nm device in this example.

FIG. 3shows a basic operation of the voltage boost circuit ofFIG. 1, in accordance with aspects of the present invention. In the example ofFIG. 3, the output voltage VPP is regulated to 1.6V and Vdd is at its maximum of 1.05V. In the precharge time frame from181to182, nodes L1and V1of capacitor C0are restored to GND and Vdd, respectively, GATEP is at VPP, and transfer gate signal XL1is at GND. Immediately prior to time182, the A phase is activated and restore phase for signal XL1rises and is coupled to node V1to hold-off (turn-off) FET T4. Node L1is lifted to Vdd slowly by discharge of ABUFN through VCMN current source, which causes node V1to rise toward 2×Vdd. The gate of output FET T3, i.e., gate voltage GATEP, is driven to (V1−Vdd*n), where n is an efficiency factor less than 1 and defined by the ratio of GATEP node capacitance and the drive capacitance C1. Charge from boost capacitor C0is transferred into output node VPP.

FIG. 4shows generation of a restore phase XL1in accordance with aspects of the present invention. As shown inFIG. 4, the restore phase of signal XL1is generated by the transfer control circuit300inFIG. 1. An input to the transfer control circuit300is bias voltage RBIAS which is intended to turn on PFET T17connected to node V1at a safe gate-voltage limit. The RBIAS generator circuit400ofFIG. 1restores node RBIAS to Vdd in the precharge phase when conduction from boosted node V1is cut off. In the pump phase, inputs A and BBUFN are high and a predetermined current is drawn through T11and T12through current source of FET T15. Voltage RBIAS is thereby dropped to a voltage close to V1−2*Vt, which is sufficient to turn on a PFET (e.g., FET T17) with its source at node V1. In the precharge phase, both nodes V1and RBIAS are at Vdd so FET T17of the transfer control circuit300ofFIG. 1is off. Input XOFF is at VPP, so FET T18ofFIG. 1is also off. Input B is high so node XL1is discharged to GND through stacked isolation FET T19ofFIG. 1. Node XL1is used to turn on precharge device PFET T4, and turn off isolation NFET T26.

FIG. 5shows a charge up and transfer of Vdd to GATEP of the voltage pump shown inFIG. 1, in accordance with aspects of the present invention. In accordance withFIG. 5, the drive-cap precharge circuit200shown inFIG. 1connects CAPH and CAPL terminals to Vdd and GND, respectively, in the precharge phase when BBUF is high, and signal XL1is at GND. XOFFN is low at VPP2level which turns on FET T5and holds node GATEP at VPP level to cut off output FET T3. In the pump phase, input B and buffered node BBUF go low which releases node XL1. XOFFN goes high to VPP which cuts off restore FET T5, and XOFF going low turns on FET T13and allows restore phase XL1to rise to VPP level. The VPP level flows through stack device PFET T9which is held on with gate voltage RBIAS. Restore phase XL1is driven towards level VPP initially and then when boosted node V1rises above VPP, conduction through T17drives XL1to V1level. Any V1conduction back through FET T13to VPP aides transfer of boosted charge to VPP by output FET T3. With boosted level V1high, and precharge phase XL1at boosted level V1, FET T17is off and capacitor C1terminal CAPH rises to V1level from conduction through T22. Terminal CAPL rises with CAPH to a level Vdd below V1. NFET T26turns on and couples terminal CAPL to GATEP through stack FET T6.

Charge sharing from the node GATEP net will guarantee that stress on output FET T3will be less than Vdd. In other words, the source of FET T3is at V1potential and the gate is at a potential (V1−Vdd*n), where n is the capacitance ratio between node GATEP and the capacitance of C1. This gate drive is sufficient to transfer charge from boosted node V1to output node of FET T3and is below the maximum Vgs defined by the level of maximum Vdd.

FIG. 6shows IV characteristics of a6-pump system in accordance with aspects of the present invention. More specifically,FIG. 6shows an exemplary VPP system of 6-pumps clocked with dual clocks 180 degrees apart by a 650-mhz oscillator. Output current I_VPP at 1.2 volts is about 3 μa.

Design process910employs and incorporates logic and physical design tools such as HDL compilers and simulation model build tools to process design structure920together with some or all of the depicted supporting data structures along with any additional mechanical design or data (if applicable), to generate a second design structure990.