A method includes removing a dummy gate stack to form a trench between gate spacers, depositing a gate dielectric extending into the trench, and performing a first treatment process on the gate dielectric. The first treatment process is performed using a fluorine-containing gas. A first drive-in process is then performed to drive fluorine in the fluorine-containing gas into the gate dielectric. The method further includes performing a second treatment process on the gate dielectric, wherein the second treatment process is performed using the fluorine-containing gas, and performing a second drive-in process to drive fluorine in the fluorine-containing gas into the gate dielectric. After the second drive-in process, conductive layers are formed to fill the trench.

BACKGROUND

The semiconductor industry continues to improve the integration density of various electronic components (for example, transistors, diodes, resistors, capacitors, etc.) through continual reduction in minimum feature size, which allows more components to be integrated into a given chip area. As the minimum feature sizes are reduced, however, additional problems and requirements arise and are addressed.

DETAILED DESCRIPTION

Methods of incorporating fluorine into a gate dielectric in a transistor are provided. In accordance with some embodiments, nanostructures are formed. A plurality of gate dielectrics comprising a plurality of high-k dielectric layers are formed on the nanostructures. A fluorine-incorporation process is performed to incorporate fluorine into the high-k dielectric layers, so that the high-k dielectric layers may be passivated, and the defects therein may be repaired. The fluorine-incorporation process may include removal processes, so that the fluorine-incorporation process does not result in additional layers to be formed in the gaps between the nanostructures. The subsequent filling of the gaps with conductive layers can thus be performed without difficulty.

In the description of the present disclosure, Gate All-Around (GAA) transistors are discussed to explain the concept of the present disclosure. The embodiments of the present disclosure may also be applied to other types of transistors such as planar transistors, Fin Field-Effect Transistors (FinFETs), and the like. Embodiments discussed herein are to provide examples to enable making or using the subject matter of this disclosure, and a person having ordinary skill in the art will readily understand modifications that can be made while remaining within contemplated scopes of different embodiments. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

FIGS.1-4,5A,5B,6A,6B,7A,7B,8A,8B,9A,9B,10A,10B,10C,11A,11B,12A,12B,13A,13B,14-18,19A,19B,20A,20B,21A,21B,21C,21D and21E illustrate various views of intermediate stages in the formation of a GAA transistor in accordance with some embodiments of the present disclosure. The corresponding processes are also reflected schematically in the process flow200as shown inFIG.28.

Referring toFIG.1, a perspective view of wafer10is shown. Wafer10includes a multilayer structure comprising multilayer stack22on substrate20. In accordance with some embodiments, substrate20is a semiconductor substrate, which may be a silicon substrate, a silicon germanium (SiGe) substrate, or the like, while other substrates and/or structures, such as semiconductor-on-insulator (SOI), strained SOI, silicon germanium on insulator, or the like, could be used. Substrate20may be doped as a p-type semiconductor, although in other embodiments, it may be doped as an n-type semiconductor.

In accordance with some embodiments, multilayer stack22is formed through a series of deposition processes for depositing alternating materials. The respective process is illustrated as process202in the process flow200shown inFIG.28. In accordance with some embodiments, multilayer stack22comprises first layers22A formed of a first semiconductor material and second layers22B formed of a second semiconductor material different from the first semiconductor material.

In accordance with some embodiments, the first semiconductor material of a first layer22A is formed of or comprises SiGe, Ge, Si, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, or the like. In accordance with some embodiments, the deposition of first layers22A (for example, SiGe) is through epitaxial growth, and the corresponding deposition method may be Vapor-Phase Epitaxy (VPE), Molecular Beam Epitaxy (MBE), Chemical Vapor deposition (CVD), Low Pressure CVD (LPCVD), Atomic Layer Deposition (ALD), Ultra High Vacuum CVD (UHVCVD), Reduced Pressure CVD (RPCVD), or the like. In accordance with some embodiments, the first layer22A is formed to a first thickness in the range between about 30 Å and about 300 Å. However, any suitable thickness may be utilized while remaining within the scope of the embodiments.

Once the first layer22A has been deposited over substrate20, a second layer22B is deposited over the first layer22A. In accordance with some embodiments, the second layers22B is formed of or comprises a second semiconductor material such as Si, SiGe, Ge, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, combinations of these, or the like, with the second semiconductor material being different from the first semiconductor material of first layer22A. For example, in accordance with some embodiments in which the first layer22A is silicon germanium, the second layer22B may be formed of silicon, or vice versa. It is appreciated that any suitable combination of materials may be utilized for first layers22A and the second layers22B.

In accordance with some embodiments, the second layer22B is epitaxially grown on the first layer22A using a deposition technique similar to that is used to form the first layer22A. In accordance with some embodiments, the second layer22B is formed to a similar thickness to that of the first layer22A. The second layer22B may also be formed to a thickness that is different from the first layer22A. In accordance with some embodiments, the second layer22B may be formed to a second thickness in the range between about 10 Å and about 500 Å, for example.

Once the second layer22B has been formed over the first layer22A, the deposition process is repeated to form the remaining layers in multilayer stack22, until a desired topmost layer of multilayer stack22has been formed. In accordance with some embodiments, first layers22A have thicknesses the same as or similar to each other, and second layers22B have thicknesses the same as or similar to each other. First layers22A may also have the same thicknesses as, or different thicknesses from, that of second layers22B. In accordance with some embodiments, first layers22A are removed in the subsequent processes, and are alternatively referred to as sacrificial layers22A throughout the description. In accordance with alternative embodiments, second layers22B are sacrificial, and are removed in the subsequent processes.

In accordance with some embodiments, there are some pad oxide layer(s) and hard mask layer(s) (not shown) formed over multilayer stack22. These layers are patterned, and are used for the subsequent patterning of multilayer stack22.

Referring toFIG.2, multilayer stack22and a portion of the underlying substrate20are patterned in an etching process(es), so that trenches23are formed. The respective process is illustrated as process204in the process flow200shown inFIG.28. Trenches23extend into substrate20. The remaining portions of multilayer stacks are referred to as multilayer stacks22′ hereinafter. Underlying multilayer stacks22′, some portions of substrate20are left, and are referred to as substrate strips20′ hereinafter. Multilayer stacks22′ include semiconductor layers22A and22B. Semiconductor layers22A are alternatively referred to as sacrificial layers, and Semiconductor layers22B are alternatively referred to as nanostructures hereinafter. The portions of multilayer stacks22′ and the underlying substrate strips20′ are collectively referred to as semiconductor strips24.

FIG.3illustrates the formation of isolation regions26, which are also referred to as Shallow Trench Isolation (STI) regions throughout the description. The respective process is illustrated as process206in the process flow200shown inFIG.28. STI regions26may include a liner oxide (not shown), which may be a thermal oxide formed through the thermal oxidation of a surface layer of substrate20. The liner oxide may also be a deposited silicon oxide layer formed using, for example, ALD, High-Density Plasma Chemical Vapor Deposition (HDPCVD), CVD, or the like. STI regions26may also include a dielectric material over the liner oxide, wherein the dielectric material may be formed using Flowable Chemical Vapor Deposition (FCVD), spin-on coating, HDPCVD, or the like. A planarization process such as a Chemical Mechanical Polish (CMP) process or a mechanical grinding process may then be performed to level the top surface of the dielectric material, and the remaining portions of the dielectric material are STI regions26.

STI regions26are then recessed, so that the top portions of semiconductor strips24protrude higher than the top surfaces26T of the remaining portions of STI regions26to form protruding fins28. Protruding fins28include multilayer stacks22′ and the top portions of substrate strips20′. The recessing of STI regions26may be performed through a dry etching process, wherein NF3and NH3, for example, are used as the etching gases. During the etching process, plasma may be generated. Argon may also be included. In accordance with alternative embodiments of the present disclosure, the recessing of STI regions26is performed through a wet etching process. The etching chemical may include HF, for example.

Referring toFIG.4, dummy gate stacks30and gate spacers38are formed on the top surfaces and the sidewalls of (protruding) fins28. The respective process is illustrated as process208in the process flow200shown inFIG.28. Dummy gate stacks30may include dummy gate dielectrics32and dummy gate electrodes34over dummy gate dielectrics32. Dummy gate dielectrics32may be formed by oxidizing the surface portions of protruding fins28to form oxide layers, or by depositing a dielectric layer such as a silicon oxide layer. Dummy gate electrodes34may be formed, for example, using polysilicon or amorphous silicon, and other materials such as amorphous carbon may also be used.

Each of dummy gate stacks30may also include one (or a plurality of) hard mask layer36over dummy gate electrode34. Hard mask layers36may be formed of silicon nitride, silicon oxide, silicon carbo-nitride, silicon oxy-carbo nitride, or multilayers thereof. Dummy gate stacks30may cross over a single one or a plurality of protruding fins28and the STI regions26between protruding fins28. Dummy gate stacks30also have lengthwise directions perpendicular to the lengthwise directions of protruding fins28. The formation of dummy gate stacks30includes forming a dummy gate dielectric layer, depositing a dummy gate electrode layer over the dummy gate dielectric layer, depositing one or more hard mask layers, and then patterning the formed layers through a pattering process(es).

Next, gate spacers38are formed on the sidewalls of dummy gate stacks30. In accordance with some embodiments of the present disclosure, gate spacers38are formed of a dielectric material such as silicon nitride (SiN), silicon oxide (SiO2), silicon carbo-nitride (SiCN), silicon oxynitride (SiON), silicon oxy-carbo-nitride (SiOCN), or the like, and may have a single-layer structure or a multilayer structure including a plurality of dielectric layers. The formation process of gate spacers38may include depositing one or a plurality of dielectric layers, and then performing an anisotropic etching process(es) on the dielectric layer(s). The remaining portions of the dielectric layer(s) are gate spacers38.

FIGS.5A and5Billustrate the cross-sectional views of the structure shown inFIG.4.FIG.5Aillustrates the reference cross-section A1-A1inFIG.4, which cross-section cuts through the portions of protruding fins28not covered by gate stacks30and gate spacers38, and is perpendicular to the gate-length direction. Gate spacers38, which are on the sidewalls of protruding fins28, are also illustrated.FIG.5Billustrates the reference cross-section B-B inFIG.4, which reference cross-section is parallel to the lengthwise directions of protruding fins28.

Referring toFIGS.6A and6B, the portions of protruding fins28that are not directly underlying dummy gate stacks30and gate spacers38are recessed through an etching process to form recesses42. The respective process is illustrated as process210in the process flow200shown inFIG.28. For example, a dry etch process may be performed using C2F6, CF4, SO2, the mixture of HBr, Cl2, and O2, the mixture of HBr, Cl2, O2, and CH2F2, or the like to etch multilayer semiconductor stacks22′ and the underlying substrate strips20′. The bottoms of recesses42are at least level with, or may be lower than (as shown inFIG.6B), the bottoms of multilayer semiconductor stacks22′. The etching may be anisotropic, so that the sidewalls of multilayer semiconductor stacks22′ facing recesses42are vertical and straight, as shown inFIG.6B.

Referring toFIGS.7A and7B, sacrificial semiconductor layers22A are laterally recessed to form lateral recesses41, which are recessed from the edges of the respective overlying and underlying nanostructures22B. The respective process is illustrated as process212in the process flow200shown inFIG.28. The lateral recessing of sacrificial semiconductor layers22A may be achieved through a wet etching process using an etchant that is more selective to the material (for example, silicon germanium (SiGe)) of sacrificial semiconductor layers22A than the material (for example, silicon (Si)) of the nanostructures22B and substrate20. For example, in an embodiment in which sacrificial semiconductor layers22A are formed of silicon germanium and the nanostructures22B are formed of silicon, the wet etching process may be performed using an etchant such as hydrochloric acid (HCl). The wet etching process may be performed using a dip process, a spray process, or the like, and may be performed using any suitable process temperatures (for example, between about 400° C. and about 600° C.) and a suitable process time (for example, between about 100 seconds and about 1,000 seconds). In accordance with alternative embodiments, the lateral recessing of sacrificial semiconductor layers22A is performed through an isotropic dry etching process or a combination of a dry etching process and a wet etching process.

FIGS.8A and8Billustrate the formation of inner spacers44. The respective process is illustrated as process214in the process flow200shown inFIG.28. The formation process incudes depositing a spacer layer extending into recesses41, and performing an etching process to remove the portions of inner spacer layer outside of recesses41, thus leaving inner spacers44in recesses41. Inner spacers44may be formed of or comprise SiOCN, SiON, SiOC, SiCN, or the like. Inner spacers44may also be porous so that they have a lower-k value lower than, for example, about 3.5. In accordance with some embodiments, the etching of the spacer layer may be performed through a wet etching process, in which the etching chemical may include H2SO4, diluted HF, ammonia solution (NH4OH, ammonia in water), or the like, or combinations thereof.

Referring toFIGS.9A and9B, epitaxial source/drain regions48are formed in recesses42. The respective process is illustrated as process216in the process flow200shown inFIG.28. In accordance with some embodiments, the source/drain regions48may exert stress on the nanostructures22B, which are used as the channels of the corresponding GAA transistors, thereby improving performance. In accordance with some embodiments, the corresponding transistor is n-type, and epitaxial source/drain regions48are accordingly formed as of n-type by doping an n-type dopant. For example, silicon phosphorous (SiP), silicon carbon phosphorous (SiCP), or the like may be grown to form epitaxial source/drain regions48. After recesses42are filled with epitaxy regions48, the further epitaxial growth of epitaxy regions48causes epitaxy regions48to expand horizontally, and facets may be formed. The further growth of epitaxy regions48may also cause neighboring epitaxy regions48to merge with each other.

After the epitaxy process, epitaxy regions48may be further implanted with an n-type impurity to form source and drain regions, which are also denoted using reference numeral48. In accordance with alternative embodiments of the present disclosure, the implantation process is skipped when epitaxy regions48are in-situ doped with the n-type impurity during the epitaxy, and the epitaxy regions48are also source/drain regions.

FIGS.10A,10B, and10Cillustrate the cross-sectional views of the structure after the formation of Contact Etch Stop Layer (CESL)50and Inter-Layer Dielectric (ILD)52.FIGS.10A,10B, and10Care obtained from the same cross-section same as the cross-sections A2-A2, B-B, and A1-A1, respectively, inFIG.4. The respective process is illustrated as process218in the process flow200shown inFIG.28. CESL50may be formed of silicon oxide, silicon nitride, silicon carbo-nitride, or the like, and may be formed using CVD, ALD, or the like. ILD52may include a dielectric material formed using, for example, FCVD, spin-on coating, CVD, or any other suitable deposition method. ILD52may be formed of an oxygen-containing dielectric material, which may be a silicon-oxide based material formed using Tetra Ethyl Ortho Silicate (TEOS) as a precursor, Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), Boron-Doped Phospho-Silicate Glass (BPSG), Undoped Silicate Glass (USG), or the like.

In subsequent processes, replacement gate stacks are formed to replace dummy gate stacks30. Referring toFIGS.11A and11B, a planarization process such as a CMP process or a mechanical grinding process is performed to level the top surface of ILD52. The respective process is illustrated as process220in the process flow200shown inFIG.28. In accordance with some embodiments, the planarization process may remove hard masks36to reveal dummy gate electrodes34, as shown inFIG.11B. In accordance with alternative embodiments, the planarization process may reveal, and is stopped on, hard masks36. In accordance with some embodiments, after the planarization process, the top surfaces of dummy gate electrodes34(or hard masks36), gate spacers38, and ILD52are level with each other within process variations.

Next, dummy gate electrodes34(and hard masks36, if remaining) are removed in one or more etching processes, so that recesses58are formed, as shown inFIGS.12A and12B. The respective process is illustrated as process222in the process flow200shown inFIG.28. The portions of the dummy gate dielectrics32in recesses58are also removed. In accordance with some embodiments, dummy gate electrodes34and dummy gate dielectrics32are removed through dry etching processes. For example, the etching process may be performed using reaction gas(es) that selectively etch dummy gate electrodes34at a faster rate than ILD52. Each recess58exposes and/or overlies portions of multilayer stacks22′, which include the future channel regions in subsequently completed nano-FETs. The corresponding portions of the multilayer stacks22′ are between neighboring pairs of the epitaxial source/drain regions48.

Sacrificial layers22A are then removed to extend recesses58between nanostructures22B, and the resulting structure is shown inFIGS.13A and13B. The respective process is illustrated as process224in the process flow200shown inFIG.28. Sacrificial layers22A may be removed by performing an isotropic etching process such as a wet etching process using etchants which are selective to the materials of sacrificial layers22A. Nanostructures22B, substrate20, STI regions26remain relatively un-etched as compared to sacrificial layers22A. In accordance with some embodiments in which sacrificial layers22A include, for example, SiGe, and nanostructures22B include, for example, Si or SiC, tetra methyl ammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like may be used to remove sacrificial layers22A. It is appreciated that althoughFIG.13Aand subsequent figures illustrate the cross-sections of nanostructures22B as being rectangular, nanostructures22B may have rounded corners, as illustrated by dashed lines inFIG.13A.

Referring toFIG.14, gate dielectrics62are formed. The respective process is illustrated as process226in the process flow200shown inFIG.28. In accordance with some embodiments, each of gate dielectrics62includes interfacial layer62A and high-k dielectric layer62B on the interfacial layer62A. The interfacial layer62A may be formed of or comprises silicon oxide, which may be deposited through a conformal deposition process such as ALD or CVD. In accordance with alternative embodiments, interfacial layer62A is formed through thermal oxidation. When formed through thermal oxidation, the portions of interfacial layer62A on the top surfaces of STI regions26will not be formed. In accordance with some embodiments, the high-k dielectric layers62B comprise one or more dielectric layers. For example, the high-k dielectric layer(s)62B may include a metal oxide or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, or combinations thereof.

FIG.15illustrates the formation of work-function layer64. The respective process is illustrated as process228in the process flow200shown inFIG.28. Work-function layer64may be an n-type work-function layer when the resulting transistor is an n-type transistor, or may be a p-type work-function layer when the resulting transistor is a p-type transistor. In accordance with some embodiments, work-function layer64is an n-type work-function layer, and may be formed of or comprise TiAlC, TiAl, TiAlN, TaAl, TaAlN, TaAlC, or the like. Alternatively, work-function layer64is a p-type work-function layer, and may be formed of or comprise TiN, TaN, TiSiN, WCN, MOON, or the combinations thereof. In accordance with some embodiments, a capping layer (not shown) such as a TiN layer or a TiSiN layer is formed between (and contacting both of) the work-function layer64and the gate dielectric62. In accordance with alternative embodiments, work-function layer64is in physical contact with gate dielectric62, with no capping layer in between. The formation of work-function layer64may include Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), or the like.

In accordance with some embodiments, as shown inFIG.15, work-function layer64is formed before the subsequent fluorine-incorporation process68as shown inFIG.16. The corresponding fluorine-incorporation process68is also discussed in subsequent paragraphs referring toFIGS.22and24. In accordance with alternative embodiments, work-function layer64is formed after the subsequent fluorine-incorporation process68as shown inFIG.16. The corresponding fluorine-incorporation process68is discussed in subsequent paragraphs referring toFIGS.23and25. Work-function layer64is thus illustrated as being dashed inFIG.15to indicate that it may be, or may not be, formed at this time and at the time fluorine-incorporation process68is performed.

Referring toFIG.16, fluorine-incorporation process68is performed. The respective process is illustrated as process230in the process flow200shown inFIG.28. The fluorine-incorporation process68is used to incorporate fluorine into high-k dielectric layer62B, so that high-k dielectric layer62B is passivated, and the defects in high-k dielectric layer62B are repaired. Fluorine-containing layer66may be formed as a result of fluorine-incorporation process68in accordance with some embodiments.

FIGS.22through24illustrate the details of some example fluorine-incorporation processes68in accordance with various embodiments. The portions of the structure shown inFIGS.22through24may correspond to the region70as shown inFIG.16.

FIG.22illustrates an example fluorine-incorporation process68performed after the formation of work-function layer64. Accordingly, work-function layer64is a surface layer, with gate dielectric62(including high-k dielectric layer62B and interfacial layer62A) and nanostructure22B being under work-function layer64. The fluorine-incorporation process68may comprise treatment process302performed using a fluorine-containing gas comprising tungsten fluoride (WF6). In accordance with some embodiments, treatment process302is performed in a vacuum chamber, and is performed using pure fluorine-containing gas, with no other gas added, or using substantially pure fluorine-containing gas, for example, with the atomic percentage of the fluorine-containing gas being greater than about 90 percent, 95 percent, or 99 percent among all gases in the vacuum chamber. In accordance with alternative embodiments, a carrier gas is added to the fluorine-containing gas. The carrier gas may include N2, Ar, He, or the like, or combinations thereof. Treatment process302may also be performed in a furnace, which may or may not be vacuumed.

In accordance with some embodiments, treatment process302comprises a thermal treatment process performed at an elevated wafer temperature, which may be in the range between about 250° C. and about 600° C. In accordance with alternative embodiments, treatment process302comprises a plasma treatment performed in the vacuum chamber. The pressure in the vacuum chamber may be in the range between about 0.5 Torr and about 50 Torr. Treatment process302may last for a period of time in the range between about 1 second and about 600 seconds. In accordance with yet alternative embodiments, the treatment process302comprises both of the thermal treatment process and the plasma treatment process, as discussed above.

As a result of treatment process302, the fluorine-containing gas may be adsorbed on the surfaces of work-function layer64, which may (or may not) result in the deposition of fluorine-containing layer66. Fluorine-containing layer66also comprises tungsten when WF6is used. Other gases such as SiH4, B2H6, H2, or the like, or combinations thereof may also be added to the process gas used in treatment process302to aid the deposition of fluorine-containing layer66. The resulting fluorine-containing layer66may be a continuous layer, with the coverage of the underlying layer being equal to 100 percent. Alternatively, fluorine-containing layer66may have a coverage of the underlying layer as being smaller than 100 percent, with some portions of the underlying layer being exposed through fluorine-containing layer66, as schematically illustrated inFIG.22.

Further referring toFIG.22, fluorine drive-in process304is performed. Fluorine drive-in process304may be in-situ performed in the same environment (such as the vacuum chamber or the furnace) in which treatment process302is performed. Alternatively, fluorine drive-in process304may be ex-situ performed in a different environment than the environment in which treatment process302is performed. For example, fluorine drive-in process304may be performed in another vacuum chamber or furnace. Fluorine drive-in process304may be performed at an elevated wafer temperature, which may be higher than or equal to the wafer temperature of the treatment process302. For example, the wafer temperature in the fluorine drive-in process304may be in the range between about 400° C. and about 650° C. During the fluorine drive-in process304, gases such as N2, Ar, He, Ne, or the like may be conducted to prevent work-function layer604from being oxidized.

The fluorine-containing gas used in the treatment process302may be stopped during fluorine drive-in process304. Alternatively, the fluorine-containing gas is also conducted, but at a lower flow rate than the flow rate of the fluorine-containing gas in the treatment. In the drive-in process304, the pressure of the vacuum chamber (if used) may be in the range between about 0.5 Torr and about 760 Torr (one atmosphere). Fluorine drive-in process304may last for a period of time in the range between about 1 second and about 600 seconds.

In accordance with alternative embodiments, no fluorine drive-in process is performed. Since treatment process302comprises a thermal treatment process and/or a plasma treatment process, during treatment process302, fluorine can still diffuse into work-function layer64and gate dielectric layer62.

In the fluorine drive-in process304, fluorine and tungsten are driven into (diffuse into) work-function layer64, gate dielectric62, and possibly nanostructures22B. Tungsten is heavier and hence has a lower diffusion rate than fluorine. Accordingly, after the fluorine drive-in process304, fluorine-containing layer66has some remaining portions not diffused. Residue-removal process306is thus performed to remove the residue of fluorine-containing layer66. During residue-removal process306, the fluorine-containing process gases (such as WF6) used in treatment process302is stopped. In accordance with some embodiments, the residue-removal process306may be performed using an etching gas comprising nitrogen fluoride (NF3). In accordance with some embodiments, residue-removal process306is performed in a vacuum chamber, and is performed using pure or substantially pure etching gas, with no other gas added. For example, the atomic percentage of the etching gas (such as NF3) may be greater than about 90 percent, 95 percent, or 99 percent of all gases in the vacuum chamber. In accordance with alternative embodiments, a carrier gas is added to the etching gas such as NF3. The carrier gas may include N2, Ar, He, or the like.

In accordance with some embodiments, residue-removal process306comprises a thermal etching process performed at an elevated wafer temperature, which may be in the range between about 250° C. and about 600° C. In accordance with some embodiments, residue-removal process306comprises a plasma etching process performed in the vacuum chamber. The pressure of the vacuum chamber may be in the range between about 0.5 Torr and about 50 Torr. As a result of the etching process, the remaining fluorine-containing layer66may be full removed, or may be partially removed, with smaller residue portion remaining.

Treatment process302, fluorine drive-in process304, and residue-removal process306are collectively referred to as fluorine-incorporation cycle310. In accordance with some embodiments, after fluorine-incorporation cycle310, the process proceeds back to process302, and one or more fluorine-incorporation cycles310are performed. The total number of fluorine-incorporation cycles310may be 2, 3, 4, 5, or more.

Incorporating fluorine through fluorine-incorporation cycles310, in which fluorine-containing layer66is removed in each cycle, has some advantageous features. The gaps between neighboring nanostructures22B have small spacings S1(FIG.15), especially after the formation of gate dielectric layers62and work-function layers64. In order to diffuse enough fluorine into gate dielectric layer, fluorine-containing layer66may be thick. The thick fluorine-containing layer66, however, may block the gaps, and the fluorine-containing layer66deposited on an overlying nanostructure22B may be merged with the fluorine-containing layer66deposited on an underlying nanostructure22B. The merging may prevent the subsequent layers from being deposited into the gaps, causing performance degradation and reliability degradation.

By performing a residue-removal process306in each of the fluorine-incorporation cycles310, the gaps are cleared before the merging occurs. Furthermore, the fluorine drive-in process304may cause the fluorine concentration in the residue fluorine-containing layer66to be lower. By removing the fluorine-containing layer66and forming new fluorine-containing layer66, fluorine is replenished, and more fluorine may be diffused to high-k dielectric layer62, hence improving the efficiency in the defect-repair process.

Further referring toFIG.22, after the fluorine-incorporation cycles310, cleaning process308is performed. Cleaning process308may remove the tungsten on work-function layer64, if the tungsten is not fully removed in preceding residue-removal processes306. Cleaning process308may comprise a wet etching process or a dry etching process. In accordance with some embodiments, cleaning process308is performed using an etching chemical that comprises an oxidant-containing solution, which may include deionized water and an oxidant(s). For example, the etching chemical may include H2O2, DiO3, the mixture of NH4OH, H2O2, and H2O, the mixture of NH4OH and O3, the mixture of HCl and H2O2, the mixture of HCl and O3, or the like. The concentration of the oxidant in the oxidant-containing solution may be in the range between about 20 percent and about 50 percent. Cleaning process308may be performed a temperature in the range between about 18° C. and about 80° C.

FIG.23illustrates the fluorine-incorporation process68in accordance with alternative embodiments. The processes shown inFIG.23are essentially the same as what are shown inFIG.22, except that inFIG.23, fluorine-incorporation process68is performed on gate dielectric layer62, and is performed before the formation of work-function layer64. The details of the fluorine-incorporation process68are not repeated herein.

FIG.24illustrates the fluorine-incorporation process68in accordance with alternative embodiments. The processes shown inFIG.24are essentially the same as what are shown inFIG.22, except that instead of using WF6to perform treatment process302, NF3is used as in treatment process302. Furthermore, the residue fluorine-containing layer66(which contains the adsorbed NF3) is thin. After drive-in process304, the residue is even thinner. Therefore, no residue-removal process is performed.

As shown inFIG.24, treatment process302is performed. The treatment process302is essentially the same as the treatment process302discussed referring toFIG.22, except NF3replaces WF6as the fluorine-containing gas. After the treatment process302, the flow of the fluorine-containing gas such as NF3is stopped or the flow rate is reduced, and drive-in process304is performed. The details of drive-in process304may be found referring to the drive-in process304inFIG.22. The drive-in process304may also be performed at a higher (or equal) wafer temperature than treatment process302. The treatment process302and the drive-in process304are collectively referred to as fluorine-incorporation cycle310. Fluorine-incorporation cycles310are repeated.

FIG.25illustrates the fluorine-incorporation process68in accordance with yet alternative embodiments. The processes as shown inFIG.25are essentially the same as what are shown inFIG.24, except that in the process shown inFIG.25, fluorine-incorporation process68is performed on gate dielectric layer62, and is performed before the formation of work-function layer64. The details of the fluorine-incorporation process68may be found referring to preceding discussion, and are not repeated herein.

FIG.17illustrates the structure after fluorine-incorporation process68as discussed referring toFIGS.22through25has been performed. Work-function layer64may have been formed already in the preceding processes, or may not have been formed. If work-function layer64has been formed, the process proceeds to what is shown inFIG.18. Otherwise, if work-function layer64has not been formed, work-function layer64will be formed after fluorine-incorporation process68and before the process shown inFIG.18. The respective process is illustrated as process232in the process flow200shown inFIG.28.

Referring toFIG.18, conductive layers78are formed over work-function layer64. The respective process is illustrated as process234in the process flow200shown inFIG.28. Conductive layers78may or may not include a blocking layer such as a TiN layer. Conductive layers78may further include a filling metal filling the remaining recesses58if they are not fully filled yet. Conductive layers78may include a metal-containing material such as cobalt, ruthenium, aluminum, tungsten, combinations thereof, and/or multilayers thereof.

Referring toFIGS.19A and19B, after the filling of recesses58, a planarization process such as a CMP process or a mechanical grinding process is performed to remove the excess portions of gate dielectrics62and the material of gate electrodes80, which excess portions are over the top surface of ILD52. The remaining portions of the conductive layers78form parts of gate electrodes80. Gate electrodes80and gate dielectrics62are collectively referred to as gate stacks82.

Next, as shown inFIGS.20A and20B, gate stacks82are recessed, so that recesses are formed directly over gate stacks82and between opposing portions of gate spacers38. A gate mask84comprising one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, or the like, is filled in each of the recesses, followed by a planarization process to remove excess portions of the dielectric material extending over ILD52. The respective process is illustrated as process236in the process flow200shown inFIG.28.

As further illustrated byFIGS.20A and20B, ILD86is deposited over ILD52and over gate masks84. The respective process is illustrated as process238in the process flow200shown inFIG.28. An etch stop layer (not shown), may be, or may not be, deposited before the formation of ILD86. In accordance with some embodiments, ILD86is formed through FCVD, CVD, PECVD, or the like. ILD86is formed of a dielectric material, which may be selected from silicon oxide, PSG, BSG, BPSG, USG, or the like.

InFIGS.21A and21B, ILD86, ILD52, CESL50, and gate masks84are etched to form recesses (occupied by contact plugs88A and88B) exposing surfaces of the epitaxial source/drain regions48and/or gate stacks82. The recesses may be formed through etching using an anisotropic etching process.

After the recesses are formed, silicide regions90(FIG.21B) are formed over the epitaxial source/drain regions48. The respective process is illustrated as process240in the process flow200shown inFIG.28. In accordance with some embodiments, silicide regions90are formed by first depositing a metal layer (not shown) capable of reacting with the semiconductor materials of the underlying epitaxial source/drain regions48(for example, silicon, silicon germanium, or germanium) to form silicide and/or germanide regions, then performing a thermal annealing process to form silicide regions90. The metal may include nickel, cobalt, titanium, tantalum, platinum, tungsten, or the like. The un-reacted portions of the deposited metal are then removed, for example, through an etching process.

Contact plugs88B are then formed over silicide regions90. Also, contact plugs88A (may also be referred to as gate contact plugs) are also formed in the recesses, and are over and contacting gate electrodes80. The respective processes are illustrated as process242in the process flow200shown inFIG.28. AlthoughFIG.21Billustrates that contact plugs88A and88B are in a same cross-section, in various embodiments, contact plugs88A and88B may be formed in different cross-sections, thereby reducing the risk of shorting with each other. GAA transistor92is thus formed.

FIG.21Cillustrates a perspective view of the structure shown inFIGS.14A and24B, wherein the cross-sectional views shown inFIGS.21A and21Bare obtained from the cross-sections21A-21A and21B-21B, respectively, inFIG.21C.FIGS.24D and24Eillustrate the horizontal cross-sectional views of the structure shown inFIGS.21A,21B, and21C, wherein the horizontal cross-sectional views are obtained from the horizontal planes21D-21D and21E-21E, respectively, inFIG.21B.

FIG.26illustrates the fluorine atomic percentage in gate stacks82in accordance with some embodiments, wherein the X-axis represents the distance in the direction of arrows94inFIG.21B.FIG.26corresponds to the embodiments in which work-function layer64is formed before fluorine-incorporation process68is performed. Since fluorine-containing layer66(FIGS.16,22and24) is removed, at a time before the conductive layers78are formed, the peak fluorine atomic percentage may be at the outer surface of work-function layer64. Due to diffusion of fluorine into conductive layers78, in the final transistor92, the peak fluorine atomic percentage may be either in work-function layer64, as shown by dashed line106, or at the interface between work-function layer64and conductive layers78, as shown by solid line104. Furthermore, the fluorine atomic percentage in conductive layers78may be steeper than in work-function layer64and gate dielectric62.

FIG.27illustrates the fluorine atomic percentage in gate stacks82in accordance with some embodiments, wherein the X-axis also represents the distance in the direction of arrows94inFIG.21B.FIG.27corresponds to the embodiments in which work-function layer64is formed after the fluorine-incorporation process68. Since fluorine-containing layer66(FIGS.16,22and24) is removed, at a time before the conductive layers78are formed, the peak fluorine atomic percentage may be at the outer surface of gate dielectric62. Due to diffusion, in the final transistor92, the peak fluorine atomic percentage may be in gate dielectric62, as shown by dashed line110, or at the interface between gate dielectric62and work-function layer64, as shown as solid line108. Furthermore, the fluorine atomic percentage in work-function layer64and conductive layers78may be steeper than in gate dielectric62.

As appreciated fromFIGS.13B and16in combination, at the time fluorine-incorporation process68is performed, ILD52and gate spacers38have already been formed, and hence also have fluorine incorporated. The surfaces of ILD52and gate spacers38receiving fluorine has higher fluorine concentration than the deeper portions. For example, in the direction of arrow95inFIG.21B, the fluorine concentration may be continuously reduced, similar to the profile of the left parts of the fluorine profile inFIGS.26and27.

The embodiments of the present disclosure have some advantageous features. By incorporating fluorine into gate dielectrics, the defects in the high-k dielectric layer are fixed. Through cyclic fluorine-incorporation processes including the removal of fluorine-containing layers, the fluorine-containing layers are removed repeatedly, and the new fluorine-containing layers with higher fluorine concentrations are replenished. Accordingly, the fluorine-incorporation into the gate dielectrics is more efficient.

In accordance with some embodiments of the present disclosure, a method comprises removing a dummy gate stack to form a trench between gate spacers; depositing a gate dielectric extending into the trench; performing a first treatment process on the gate dielectric, wherein the first treatment process is performed using a fluorine-containing gas; performing a first drive-in process to drive fluorine in the fluorine-containing gas into the gate dielectric; performing a second treatment process on the gate dielectric, wherein the second treatment process is performed using the fluorine-containing gas; performing a second drive-in process to drive fluorine in the fluorine-containing gas into the gate dielectric; and after the second drive-in process, forming conductive layers to fill the trench.

In an embodiment, the method further comprises, after the first drive-in process, removing a first fluorine-containing layer formed due to the first treatment process; and after the second drive-in process, removing a second fluorine-containing layer formed due to the second treatment process. In an embodiment, the method further comprises, after the second fluorine-containing layer is removed, performing a cleaning process to further remove residues of the first fluorine-containing layer and the second fluorine-containing layer. In an embodiment, the fluorine-containing gas comprises tungsten fluoride, and the first fluorine-containing layer and the second fluorine-containing layer further comprise tungsten therein.

In an embodiment, the fluorine-containing gas comprises nitrogen fluoride. In an embodiment, the method further comprises depositing a work-function layer on the gate dielectric, wherein the first treatment process and the second treatment process are performed on the work-function layer. In an embodiment, the method further comprises, after the first treatment process and the second treatment process, depositing a work-function layer on the gate dielectric. In an embodiment, the first drive-in process comprises an annealing process. In an embodiment, the method further comprises, after the second drive-in process, performing a third treatment process on the gate dielectric, wherein the third treatment process is performed using the fluorine-containing gas; and performing a third drive-in process to drive fluorine in the fluorine-containing gas into the gate dielectric.

In accordance with some embodiments of the present disclosure, a method comprises forming a dummy gate stack on a top surface and sidewalls of a multilayer stack, wherein the multilayer stack comprises a plurality of sacrificial layers and a plurality of nanostructures located alternatingly; removing the dummy gate stack to form a recess in a dielectric layer; removing the plurality of sacrificial layers; depositing gate dielectrics wrapping around the plurality of nanostructures; depositing work-function layers on the gate dielectrics; performing a plurality of cycles, wherein each of the plurality of cycles comprises forming a plurality of fluorine-containing layers, each on one of the gate dielectrics; driving-in fluorine in the plurality of fluorine-containing layers into the gate dielectrics; and removing the plurality of fluorine-containing layers; and after the plurality of cycles, forming a conductive layer, wherein the conductive layer comprises portions in gaps between the plurality of nanostructures.

In an embodiment, the forming the plurality of fluorine-containing layers comprises treating the gate dielectrics using WF6as a process gas. In an embodiment, the removing the plurality of fluorine-containing layers is performed using NF3as an etching gas. In an embodiment, in each of the plurality of cycles, the plurality of fluorine-containing layers formed before the driving-in is fully removed.

In an embodiment, the driving-in fluorine comprises an annealing process. In an embodiment, the forming the plurality of fluorine-containing layers is performed at a first wafer temperature, and the driving-in fluorine is performed at a second wafer temperature higher than the first wafer temperature. In an embodiment, the removing the plurality of fluorine-containing layers is performed through a dry etching process, and wherein the method further comprises, after the plurality of cycles, performing a wet etching process to etch residues of the plurality of fluorine-containing layers. In an embodiment, the plurality of cycles are performed on the work-function layers.

In accordance with some embodiments of the present disclosure, a method comprises forming a nanostructure in a trench, with gate spacers being on opposite sides of the trench; depositing a gate dielectric extending into the trench to encircle the nanostructure, wherein the gate dielectric comprises a high-k dielectric material; and after the gate dielectric is deposited, performing a plurality of cycles, wherein each of the plurality of cycles comprises performing a treatment process on the gate dielectric using WF6as a first process gas; and after the treatment process, performing an etching process using NF3as a second process gas. In an embodiment, the method further comprises a drive-in process in each of the plurality of cycles, wherein the drive-in process is performed after the treatment process and before the etching process. In an embodiment, the treatment process results in a tungsten-and-fluorine-containing layer being left on the gate dielectric, and wherein the etching process results in the tungsten-and-fluorine-containing layer to be etched.