SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE

In an embodiment, a semiconductor device includes an edge termination region laterally surrounding an active area. The active area includes active transistor cells. The edge termination region includes one or more inactive cells, each including a first columnar trench and a first termination mesa arranged adjacent to the first columnar trench. Each first columnar trench includes a base, a side wall, a field plate, and a field dielectric arranged on the base and the side wall and surrounding the field plate. Each first termination mesa includes a drift region of a first conductivity type and a body region of a second conductivity type arranged above the drift region. Each field dielectric of the first columnar trenches has a first thickness in an upper region of the field plate and a second thickness in a lower region of the field plate, the first thickness being smaller than the second thickness.

BACKGROUND

Transistor devices used in power electronic applications are often fabricated with silicon (Si) semiconductor materials. Common transistor devices for power applications include Si CoolMOS®, Si Power MOSFETs and Si Insulated Gate Bipolar Transistors (IGBTs).

A transistor device for power applications may be based on the charge compensation principle and may include an active cell field including a plurality of trenches, each including a field plate for charge compensation. In some designs, the trenches and the mesas that are formed between adjacent trenches each have an elongate striped structure. In some other designs, the trenches have a columnar needle-like shape. Typically, the active cell field of the transistor device is laterally surrounded by an edge termination structure which may be helpful to avoid breakdown of the semiconductor device due to edge effects.

Avalanche breakdown is the phenomenon of current multiplication when a semiconductor device is subject to high electric fields. In the avalanche state, a high amount of power may be dissipated in the transistor device which may finally result in a destruction due to overheating if the avalanche current prevails longer than the time it takes to reach the thermal limit to overheat the transistor device. In order to prevent damage to the transistor device, it may be beneficial that the avalanche breakdown occur over a large area, thereby reducing the avalanche current density.

Discontinuities at the edges of semiconductor devices may create locally large electric fields, tending to produce avalanche breakdown preferentially at the edge of the device instead of uniformly distributed over the entire active area of the device. Edge termination structures may be useful to remove or smooth the discontinuities at the edge, thereby reducing the otherwise large fields at that location.

Avalanche breakdown can occur in the cell field. If the voltage required to reach breakdown electric field is lower for one device region, e.g. in a group of cells, than for others, the critical temperature will be reached more easily causing the device to fail in one specific area.

Further improvements would be desirable to further improve the performance of transistor devices, including MOSFET devices, to achieve improved avalanche robustness and a low on-state resistance.

SUMMARY

According to the invention, in an embodiment, a semiconductor device is provided that comprises an active area and an edge termination region laterally surrounding the active area. The active area comprises a plurality of active transistor cells. The edge termination region comprises a transition region laterally surrounding the active region. The transition region comprises one or more inactive cells, each inactive cell comprising a first columnar trench and a first termination mesa arranged adjacent to the first columnar trench. Each first columnar trench comprises a base, a side wall, a field plate, and a field dielectric arranged on the base and the side wall and surrounding the field plate. Each first termination mesa comprises a drift region of a first conductivity type and a body region of a second conductivity type arranged above the drift region. Each field dielectric of the first columnar trenches has a first thickness in an upper region of the field plate and a second thickness in a lower region of the field plate, the second thickness being greater than the first thickness.

According to the invention, in an embodiment, a method for fabricating a semiconductor device. The method comprises forming a plurality of columnar trenches in a first major surface of a semiconductor substrate having a first conductivity type, the columnar trenches being arranged in an array of offset rows and each having a base and a side wall extending form the base to the first major surface, lining the base and side wall of the columnar trenches with a field dielectric, inserting conductive material into the columnar trenches, whilst covering a second subset of the plurality of columnar trenches that lies laterally outboard of a first subset of the plurality of columnar trenches, in the first subset of trenches: removing an upper portion of the conductive member from an upper portion of the columnar trenches and exposing the field dielectric arranged on the side wall; removing a portion of the exposed field dielectric and reducing the thickness of the exposed field dielectric arranged on the side wall of the upper portion of the columnar trenches; inserting conductive material into the columnar trench and filling the upper portion of the trench with the conductive material, implanting dopants of a second conductivity type into a first predetermined area of the first major surface to form a body region, wherein the second subset of the plurality of columnar trenches is positioned laterally outboard of the first predetermined area and the first subset of the plurality of columnar trenches is positioned laterally within the first predetermined area and implanting dopants of the first conductive type into a second predetermined area that is smaller than the first predetermined area.

DETAILED DESCRIPTION

A number of exemplary embodiments will be explained below. In this case, identical structural features are identified by identical or similar reference symbols in the figures. In the context of the present description, “lateral” or “lateral direction” should be understood to mean a direction or extent that runs generally parallel to the lateral extent of a semiconductor material or semiconductor carrier. The lateral direction thus extends generally parallel to these surfaces or sides. In contrast thereto, the term “vertical” or “vertical direction” is understood to mean a direction that runs generally perpendicular to these surfaces or sides and thus to the lateral direction. The vertical direction therefore runs in the thickness direction of the semiconductor material or semiconductor carrier.

As employed in this specification, when an element such as a layer, region or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present.

As used herein, various device types and/or doped semiconductor regions may be identified as being of n type or p type, but this is merely for convenience of description and not intended to be limiting, and such identification may be replaced by the more general description of being of a “first conductivity type” or a “second, opposite conductivity type” where the first type may be either n or p type and the second type then is either p or n type.

FIGS.1A and1Billustrate a semiconductor device10, wherebyFIG.1Aillustrates a top view andFIG.1Ba cross-sectional view of a portion of the semiconductor device10. The semiconductor device10includes an active area11and an edge termination region12, which laterally surrounds the active area11, which are positioned in a semiconductor substrate23having a first major surface22. The semiconductor substrate23may be formed of silicon, for example monocrystalline silicon or an epitaxial silicon layer.

The semiconductor device10comprises at least one columnar trench14. A columnar trench, which may also be called a needle-shaped trench or needle trench or spicular trench, has a small or narrow circumference or width in proportion to its height/depth in the substrate. For example, the depth is at least twice the width.

One or more of these columnar trenches14may be arranged in the edge termination region12and/or in the active region11. The columnar trench14may form part of an inactive cell when it is positioned in the edge termination region12. When the columnar trench is positioned in the active region it may form part of a transistor cell. For example, the columnar trench14may not be part of a transistor cell.

The active area11comprises at least one active semiconductor device, for example at least one transistor device that comprises a plurality of active transistor cells which may be electrically connected to one another in parallel to switch a load. InFIGS.1A and1B, the transistor device in the active area11is not shown and the columnar trench14is located in the edge termination region12. The edge termination region12comprises one or more inactive cells13, each inactive cell13comprising one columnar trench14and a termination mesa15arranged adjacent to the first columnar trench14.

InFIG.1A, the columnar trenches14are illustrated as having a square lateral form in top view. However, the columnar trench14may have other lateral forms in top view. For example, the columnar or needle trench14may have an octagonal, circular, or hexagonal shape in plan view.

As can be seen in the cross-sectional view ofFIG.1B, the columnar trench14comprises a base16and a sidewall17. The side wall17extends from the base16to the first major surface22of the semiconductor substrate23. The columnar trench14further comprises a field plate18and a field dielectric19. The field dielectric19is arranged on the base16and sidewall17of the columnar first trench14and surrounds the field plate18which is located in the trench. The field plate18is electrically conductive and may be formed of polysilicon, for example. The field plate18may extend to the first major surface22and have an upper surface that is coplanar with the first major surface22of the semiconductor substrate23. The field dielectric19may include one or more sublayers having the same or differing compositions. The field dielectric19may be SiOx, for example.

In embodiments in which the columnar trench14is circular in plan view, the columnar trench14has a single side wall17. If the columnar trench14is square in plan view, as shown inFIG.1A, the side wall17is divided into four side wall sections arranged substantially perpendicularly to one another. Similarly, if the columnar trench14is hexagonal in plan view, the side wall17has six side wall sections etc.

A plurality of the columnar trenches14may be arranged in a regular array, such as a square grid array of rows and columns, or an array of offset rows (such as a hexagonal array), in which the spacing or pitch between neighboring ones of the columnar trenches14is substantially the same throughout the array. In some embodiments, such as that illustrated inFIG.1A, a plurality of columnar trenches14may be arranged in a ring in the edge termination region12. The ring laterally surrounds the active area11.

Referring toFIG.1B, in some embodiments, the field dielectric19in the first columnar trench14has a first thickness t1on the side wall17in an upper portion of the trench14and a second thickness t2on the side wall17in the lower portion of the trench14. The second thickness t2of the field dielectric19in a lower portion of trench14the trench is greater than the thickness t1in the upper portion of the trench14. As the field plate18and the field dielectric19together fill the columnar trench14, the field plate18has a larger width w1in the upper portion of the trench14than its width w2in the lower portion of the trench14.

Referring toFIG.1B, in some embodiments, the field dielectric19comprises an abrupt transition from the first to the second thickness that forms a step25so that the field dielectric19can be considered to have a stepped shape. In some embodiments, the field dielectric19has the smaller thickness t1over a first height h1of the columnar trench14in the upper portion and the larger thickness t2over a second height h2of the columnar trench14in the lower portion.

In some embodiments, the thickness t1≤1.15 times the thickness t2and consequently the thickness t1is greater than typical process variations. In some embodiments, the difference is greater so that t1≤1.2 t2or t1≤1.5 t2.

The field plate18may also have an abrupt transition between a larger width w1in the upper portion of the trench14and a smaller width w2towards the lower portion of the trench14. The field plate18can be considered to have a step26in its outer surface27corresponding to the step25formed in the field dielectric19. The field plate18can be considered to have a T-shape in cross-section.

The termination mesa15of each inactive cell13is formed by the region of the semiconductor substrate23that laterally surrounds the columnar trench14of that inactive cell13. The structure of the mesa15may differ, for example depending on the position of the columnar trench14and its associated mesa15within the edge termination region12. In some embodiments, for example as illustrated inFIG.1B, each termination mesa15comprises a drift region20of the first conductivity type, for example n-type. One or more of the termination mesas15, further comprises a body region21of the second conductivity type, for example p type if the drift region is n-type. For example, the termination mesa15illustrated in the right-hand portion of the edge termination region12that adjoins the active region11includes a body region21. The body region21is arranged above the drift region20and may form a pn junction with the drift region20. In some embodiments, in the termination mesa15, the body region21extends to the first major surface22of the semiconductor substrate23of the semiconductor device10. In some embodiments, for example as illustrated in the left-hand portion of the edge termination region12ofFIG.1B, the inactive cell13comprises a termination mesa15without a body region so that the drift region20extends to the first major surface22of the semiconductor substrate.

In some embodiments, such as those illustrated inFIGS.1B,2A and2B, the body region21is positioned laterally adjacent only a portion of the periphery of the columnar trench14and the drift region20is arranged laterally adjacent the remainder of the periphery of the columnar trench14. In other embodiments, the body region21laterally surrounds the entire columnar trench14. In other embodiments, the drift region20laterally surrounds the entire columnar trench14.

In some embodiments, the field dielectric19has the thickness t1in a first region of the side wall17that is contiguous to the body region21and the thickness t2in a second region of the side wall17that is contiguous to the drift region20. The step25is located at a depth d1from the first major surface22of the semiconductor substrate23and the pn junction formed between the body region21and the drift region20has a depth dpnfrom the first major surface of the semiconductor substrate, wherein d1>dpn. The step25may be positioned laterally adjacent the drift region20.

In some embodiments, the one or more first inactive transistor cells13ofFIG.1Bare directly adjacent to one or more of the plurality of active transistor cells in the active region11. The region of the edge termination region12in which the first columnar trenches14are located, can be referred to as a transition region.

An active transistor cell may comprise a columnar trench that has the same structure as columnar trench14, but with an active mesa. In the active transistor cell, the active mesa comprises the drift region20, the body region21on the drift region20and a source region of the first conductivity type on the body region21(not shown inFIG.1B). The active transistor cells are not illustrated inFIGS.1A and1B. In the active area, a gate trench comprising a gate electrode is located in the active mesa. A drain region58of the first conductivity type is arranged on a second major surface of the semiconductor substrate, the second major surface opposing the first major surface.

The columnar trench of the active transistor cells may have the form illustrated in and described with reference toFIGS.1B and2A-2B. The columnar trenches of the active transistor cells and the columnar trenches14of the inactive cells13may form an array with a common spacing or pitch between adjacent ones of the columnar trenches. The inactive cells13are distinguishable from the active transistor cells in that the active transistor cells include a source region on the body region and the inactive cells are without a source region. In the inactive cells13, the body region21may extend to the first major surface of the semiconductor substrate. At least one of the inactive cells13is arranged directly adjacent, i.e. is the immediate neighbour of, an active cell. For example, one or more rings of inactive cells13may laterally surround the active area11as shown inFIG.1A.

The field dielectric19and consequently the field plate18within the columnar trenches14may have other forms as an alternative to the one shown inFIG.1B.FIGS.2A and2Billustrate two embodiments of a columnar trench14that may be located in the edge termination region12as part of an inactive cell13or in the active area11as part of an active transistor cell. Referring toFIG.2A, the field plate18may have a tapering structure such that its width decreases from the top of the trench14towards the base16of the trench16. The field dielectric19has the opposite structure such that the thickness of the field dielectric19on the side wall17continuously increases in a direction from the first major surface22towards the base16of the trench14. The field dielectric has a thickness t1on the side wall17at the first major surface22and decreases continuously to a thickness t2on the side wall17at a portion laterally adjacent to the lower surface of the field plate18, whereby t1<t2.

Referring toFIG.2B, the field dielectric19may also have more than one step25.FIG.2Billustrates an embodiment in which the field dielectric19has two steps25,25′ such it has three different thicknesses on the side wall17of the columnar trench14. The thickness of the field dielectric19increases stepwise incrementally from the first major surface22towards the base16of the columnar trench14. In the upper portion of the side wall17, the field dielectric has a thickness t1, in the middle portion a thickness t2and in the third portion a thickness t3, whereby t1<t2<t3. The side face of the field plate18has two steps26,26′ such it has three different widths and such that the width of the field plate18decreases stepwise from the first major surface22towards the base16of the columnar trench14.

FIG.3Aillustrates a top view of a semiconductor device10according to an embodiment. The semiconductor device10comprises an active area11and an edge termination region12which laterally surrounds the active area11. The active area11comprises a plurality of transistor cells (e.g., with columnar trenches14as shown inFIGS.1B,2A and2B). The edge termination region12comprises a termination trench30and a plurality of inactive cells13, each comprising a columnar trench14and a termination mesa15which is formed by the region of the semiconductor substrate that laterally surrounds the columnar trench (as shown inFIGS.1B,2A and2B). A first one13′ of the inactive cells13comprises a first columnar trench14′ and a first termination mesa15′ and a second one13″ of the inactive cells13comprises a second columnar trench14″ and a second termination mesa15″. In this embodiment, the columnar trenches14have a hexagonal form in plan view. In other embodiments, the columnar trenches14may have different lateral forms, for example octagonal, square or circular. The first and second inactive cells13′,13″ are arranged directly adjacent to one another and directly adjacent to the termination trench30. The termination trench30is completely filled with dielectric, for example dielectric material37, e.g. SiOx.

The first and second columnar trenches14,14′ are part of a plurality of columnar trenches14which are arranged in an array comprising offset rows. In the embodiment illustrated inFIGS.3A-3B, the spacing or distance parallel to the first major surface12D3between the columnar trenches of the array is substantially equal such that the columnar trenches14are also arranged in a hexagonal array. The shortest distance D1between the termination trench30and the first columnar trench14is the same as the shortest distance D2between the termination trench30and the second columnar trench14′. The shortest distance D3between the first columnar trench14and the second columnar trench14′ of the array is larger than the shortest distance between the termination trench30and the first columnar trench14. In other words, D3is greater than D1and consequently D3is also greater than D2.

In some embodiments, such as that illustrated inFIG.3A, the termination trench30is a continuous trench that laterally uninterruptedly and continuously surrounds the active area11. In other embodiments, such as that illustrated inFIG.3B, the termination trench30is an interrupted trench and comprises a plurality of separate termination trench sections30′ which are arranged in a ring with the separate trench sections30′ being spaced part by portions of the semiconductor substrate23. In both designs, the termination trench30or plurality of termination trench sections30′ is/are filed with dielectric material37, for example SiOx, and is free of conductive material. The termination trench30comprises an inner side wall section31which faces towards the active area11and an outer sidewall section32which faces towards the periphery of the semiconductor substrate23and opposes the inner side wall section31. The inner and outer sidewall sections31,32extend substantially parallel to one another. In some embodiments, the spacing between the inner sidewall31of the termination trench30and the individual ones of the columnar trenches14that are arranged at the periphery of the array is substantially uniform. In top view, the continuous termination trench30has an undulating or wavy form, as shown inFIG.3A, or the ring shape of the plurality of trench sections30′ has an undulating or wavy form in top view, as shown inFIG.3B.

The columnar trenches14each have a plurality of sidewall sections33, in this embodiment, six sidewall sections, whereby adjoining ones of the sections33have an internal angle α1which is greater than 90°. In the case of a hexagonal columnar trench14, the angle α1is 120°. In order that the spacing between the inner wall31and the sidewall sections33of the columnar trenches14is substantially the same, the inner sidewall31and the outer sidewall32of the termination trench30have a plurality of subsections34. Adjoining sidewall subsections34of the inner side wall31of the termination trench30which are arranged adjacent adjoining sidewall sections33of the same columnar trench14, form an external angle α2which is substantially the same as α1. Adjoining sidewall sub sections34of the inner side wall section31of the termination trench30which are arranged adjacent neighbouring ones of the columnar trenches, form an internal angle α3which is substantially the same as α1.

In some embodiments, the edge termination region12includes a plurality of subregions which concentrically surround the active area11and which have different structures. For example, the edge termination region12may have the subregions described with reference toFIGS.4A to6C. In some embodiments, the edge termination region12comprises a transition region50which laterally surrounds the active area11, and inner termination region51that laterally surrounds the transition region50, an intermediate termination region52laterally surrounds the inner termination region51and an outer termination region53that laterally surround the intermediate termination region52. In an embodiment, the termination trench30and the first and second inactive cells13,13′ are arranged in the intermediate termination region52. The outer termination region53may be devoid of columnar trenches.

FIG.4Aillustrates a top view andFIG.4Ba cross-sectional view of a semiconductor device10according to an embodiment. The semiconductor device10comprises an active area11(not drawn to scale) including a plurality of active transistor cells and an edge termination region12formed in a semiconductor substrate23. The edge termination region12laterally surrounds the active area11on all lateral sides and comprises a plurality of inactive cells13. The inactive cells13in the edge termination region12each comprise a columnar trench14comprising a field plate18and a field dielectric19having a profile. The field dielectric19is arranged on the base16and sidewall17of the first columnar trench14and surrounds the first field plate18. In this embodiment, the profile of the field dielectric19is different depending on the position of the columnar trench14within the edge termination region12.

The edge termination region12comprises one or more first inactive cells13′, each comprising a columnar trench14′ which has a base, a sidewall17, a first field plate18′ and a field dielectric19having a first profile19′. The edge termination region12further includes one or more second inactive cells13″. Each of the second inactive cells13″ includes a columnar trench14″ comprising a base16″ and a sidewall17″, a second field plate18″ and a second dielectric profile19″. The first field dielectric structure19′ may have a different thickness profile from the second field dielectric structure19″.

The term “profile” and the term “thickness profile” of the field dielectric19are used herein to describe the thickness of the field dielectric19within the columnar trench14along a direction orthogonal to the first major surface22, pointing to the base16of the trench14. The cross-sections views ofFIGS.1B,2A and2Bshow such profiles for the field dielectric19. In these embodiments, the profile is non-uniform as the thickness of the field dielectric19, measured in a direction parallel to the first major surface22, varies in a direction orthogonal to the first major surface22. The thickness of the field dielectric19is smaller in the upper portion of the trench14, e.g. at the first major surface22, than in the lower portion of the trench14. The variation in the thickness is greater than that arising from processing variations.

In some embodiments, the active transistor cells40in the active area11each have a columnar trench41having a field plate42and a field dielectric43having the first field dielectric profile19′.

In some embodiments, the second inactive cells13″ are closer to the edge of the semiconductor substrate23than the first inactive cells13′. For example, one or more rows of first columnar trenches14′ with a first field dielectric structure19′ laterally surround the active area11and one or more rows of third columnar trenches14″ with a second field dielectric structure19″ laterally surround the first columnar trenches14′. The structure of the field dielectric19in the columnar trenches14varies depending on the position of that columnar trench14within the edge termination region12. The columnar trenches in the active area11and the columnar trenches14′,14″ in the edge termination region12may be arranged in an array that has the same spacing or pitch throughout the array. The array may be a square grid array, as shown inFIG.4A, or include off set rows. In some embodiments, the outermost ones of the columnar trenches14of the array have a different field dielectric profile to the remainder of the columnar trenches14of the array.

FIG.4Billustrates a cross-sectional view of a portion of the active area11and edge termination region12in which the first and second field dielectric profiles19′,19″ can be seen. In some embodiments, the first field dielectric structure19′ of the first columnar trench14has a thickness that is greater on the lower portion of the sidewall17than on an upper portion of the sidewall17. For example, the first field dielectric structure may be that shown in or described with reference toFIGS.1B,2A and2B. In contrast, the second dielectric structure19″ of the second columnar trench14″ has a thickness that is substantially uniform along the height of the side wall17. Therefore, the inactive cells13of the edge termination region12are not the same throughout the edge termination region12.

The active area11includes a plurality of transistor cells40that are electrically coupled in parallel to provide a transistor device for switching a load. The transistor device is a vertical field effect transistor device based on a charge compensation principle.

The semiconductor device10includes a semiconductor substrate23having a first surface22, a second surface, which cannot be seen in the partial cross-sectional view ofFIG.4B, that opposes the first surface22, and side faces extending between the first surface22and the second surface. The semiconductor substrate23may comprise silicon and may include a silicon epitaxial layer deposited on a substrate such as a single crystal silicon substrate. The first surface22can be referred to as the top surface and the second surface as the rear surface.

Each active transistor cell40comprises a columnar trench41and a mesa46. The columnar trench41comprises a field plate42and a field dielectric43that lines the base44and side wall45of the columnar trench41. The mesas46are formed by the regions of the semiconductor substrate23that are located between the columnar trenches41. The columnar trench41have the same structure as the innermost columnar trench14′ of the edge termination region12so that the field dielectric19′ has a non-uniform thickness on the side wall45. The field dielectric19′ may be thicker in the lower portion of the columnar trench41than in the upper portion. For example, the field dielectric43may have the structure and profile illustrated in or described with reference toFIGS.1B,2A and2B.

In the embodiment illustrated inFIGS.4A and4B, the columnar trenches14,41are arranged in a regular array, such as a regular square grid, for example of rows and columns in which the columnar trenches14,41have the same pitch or spacing. In some embodiments, such as that illustrated inFIGS.3A-3B or6A-6E, the columnar trenches19are arranged in an array of staggered or shifted rows. The lateral form of each of the columnar trenches14,41within the array having any form or pattern may be square, octagonal, round or hexagonal, for example. For example, the columnar trenches may have a lateral octagonal form in plan view and be arranged in staggered rows. The cross-sectional form of the columnar trenches14,41is however the same irrespective of the lateral form of the trench and the type of array.

In some embodiments, the columnar trenches14of the inactive cells13′ that are arranged directly adjacent to the active area11may have the same structure as the columnar trenches40of the transistor cells13and comprise a first dielectric structure19′.

In some embodiments, such as that illustrated inFIG.4B, the first dielectric structure19′ has a stepped profile, e.g. as shown and described with reference toFIGS.1B and2B, so that the thickness of the first dielectric structure19′ is smaller towards the top of the columnar trench14than towards the base16. In other embodiments, the first dielectric structure may have a tapered form, e.g., as shown with reference toFIG.2A. The second Inactive cells13″ that are arranged laterally outwardly from the first inactive cells13′ comprise a columnar trench14″ having the second dielectric structure19″ in which the thickness of the field dielectric is substantially uniform along the entire height of the side wall17. The first inactive cells13′ may be arranged in a transition region50and the second inactive cells13″ in an intermediate region52of the edge termination region12.

FIG.5Aillustrates a plan view andFIG.5Ba cross-sectional view of a semiconductor device10having an active area11and an edge termination region12that is subdivided into different regions which are arranged concentrically around the active area11. Each of these regions is distinguishable by a different structure.

The active area11includes a plurality of transistor cells40that are electrically coupled in parallel to provide a transistor device for switching a load. The transistor device is a vertical field effect transistor device based on a charge compensation principle.

The semiconductor device10includes a semiconductor substrate23having a first surface22, a second surface35, which cannot be seen in the top view ofFIG.5A, that opposes the first surface22, and side faces56extending between the first surface22and the second surface35. The semiconductor substrate23may comprise silicon and may include a silicon epitaxial layer deposited on a substrate such as a single crystal silicon substrate. The first surface22can be referred to as the top surface and the second surface35as the rear surface.

The semiconductor device10includes the active area11which is laterally surrounded by an edge termination region12on all sides. The active area11includes a plurality of active transistor cells40. Each active transistor cell40comprises a columnar trench41and a mesa46. The columnar trench41comprises a field plate42and a field dielectric43that lines the base44and side wall45of the columnar trench41. The mesas46are formed by the regions of the semiconductor substrate23that are located between the columnar trenches41. The columnar trench41have the same structure as the columnar trenches14′ in the transition region51so that the field dielectric19has a non-uniform thickness on the side wall45. The field dielectric may be thicker in the lower portion of the columnar trench41than in the upper portion. For example, the field dielectric43may have the structure illustrated in or described with reference toFIGS.1B,2A and2B.

In the embodiment illustrated inFIG.5A, the columnar trenches14,41are arranged in a regular array, such as a regular square grid, for example of rows and columns in which the columnar trenches14,41have the same pitch or spacing. In some embodiments, such as that illustrated inFIGS.3A-3B or6A-6E, the columnar trenches19are arranged in an array of staggered or shifted rows. The lateral form of each of the columnar trenches14,41within the array having any form or pattern may be square, octagonal, round or hexagonal, for example. For example, the columnar trenches may have a lateral octagonal form in plan view and be arranged in staggered rows. The cross-sectional form of the columnar trenches14,41is however the same irrespective of the lateral form of the trench and the type of array.

In the embodiments ofFIGS.5A and5B, the edge termination region12comprises a transition region50which laterally surrounds the active region11, an intermediate termination region52which laterally surrounds the transition region50and an outer termination region53that laterally surrounds the intermediate termination region52. In some embodiments, an inner termination region51is positioned between the transition region50and the intermediate termination region52.

The boundary between the transition region50and the intermediate termination region52is indicated by the dashed line55and the boundary between the intermediate termination region52and the outer termination region53is indicated by the dashed line57.

The transistor device formed by the active transistor cells40and positioned in the active region11may be a vertical MOSFET device that comprises the field plates42for charge compensation. The source and gate of the MOSFET device may be positioned at the first surface22and the drain region58may be positioned at the second opposing surface35so that the drift path of the MOSFET device extends vertically and substantially perpendicular to the first surface22and the second surface35.

Some MOSFET devices have a stripe design, i.e. the trenches41and the mesas46have an elongate strip form and are arranged alternatively so that a strip-like mesa46is defined by two adjacent strip-like trenches41. However, some types of designs of MOSFET devices with a field plate for charge compensation, such as that illustrated inFIGS.5A and5B, include columnar or needlelike trenches41so that the mesa46is formed by the material between the columnar trenches41. The cross-sectional is the same for both stripe-like trenches41and columnar trenches41.

A columnar field plate42is positioned in the columnar trenches41and is electrically insulated from the semiconductor substrate23by a dielectric material43that lines the sidewalls33and base40of the columnar trench19. The columnar trench41is typically a deep trench containing the field-plate42in the center.

The field dielectric43comprises a stepped shape and has a first upper portion47positioned in the upper portion of the trench with a thickness t1and a second lower portion48with a thickness t2that is positioned in the lower portion of the trench41, whereby t2>t1.

A separate shallower gate trench60is positioned in the mesa46. The gate electrode61of the transistor cell40is positioned in the gate trench60and is electrically insulated from the semiconductor substrate23by a gate dielectric62that lines the base63and side wall64of the gate trench60. The gate trench60has an elongate form.

The gate trenches60interconnect to form a grid structure that laterally surrounds each columnar trench41. The grid structure may be a square grid or a hexagonal or octagonal grid. The shape of the gate grid may follow the shape of the columnar trenches so that the spacing between the gate trenches60and the columnar trenches is substantially uniform.

In some embodiments, the gate trenches60do not interconnect to form a grid, but instead a plurality of separate gate trenches are provided, which extend across the first major surface in lines, which may be straight or zig-zag, e.g. meandering in top view. The meandering shape may follow the shape of the columnar trenches so that the spacing between the gate trenches60and the columnar trenches is substantially uniform. In some embodiments, the separate gate trenches and/or the gate grid are interrupted, i.e. discontinuous, to provide a plurality of discrete sections that are spaced apart from one another.

The transition region50and the inner edge termination region52of the edge termination region12comprise a plurality of inactive cells13. Each inactive cell13comprises a columnar termination trench14and a termination mesa15. The columnar termination trench13also comprises a field plate18. The termination mesa15includes a drift region20of a first conductivity type.

In some embodiments, the edge termination region12further includes at least one termination trench30that is positioned in the outer termination region53. The termination trench30may be a continuous trench that forms a single ring that continuously and uninterruptedly laterally surrounds the columnar termination trenches14and the inactive cells13or may comprise a plurality of sections30′ arranged in a ring that laterally surrounds the columnar termination trenches14. The sections30′ are each elongate and have a length measured in a plane parallel to the first major surface12that is greater, i.e. at 1.5 times larger, than a width measured in a plane parallel to the first major surface12. The termination trench30or the plurality of sections30′ are filled with dielectric material37. The plurality of sections30′ may be spaced apart by a portion of the semiconductor substrate23that has a width that may be less than the distance from the section30′ to the immediately adjacent columnar termination trench14. The width of the semiconductor substrate23between the sections30′ of the termination trench30may alternatively be the same as or greater than the distance from the section30′ to the immediately adjacent columnar termination trench14.

The columnar termination trenches14and the columnar trenches41of the active cells40are arranged in an array. The termination trench30laterally surrounds and is arranged at the periphery of this array, i.e. between the array and the side faces56of the semiconductor substrate23. The termination trench30is free of electrically conductive material and does not include a field plate.

In some embodiments, the termination trench30is spaced apart from a laterally outermost one of the columnar termination trenches14by a distance douter. doutermay be 50 nm≤douter≤2 μm. The semiconductor substrate23typically has a cuboid form with substantially perpendicular substantially straight side faces56that intersect at corners. The distance douteris measured adjacent to the side faces56rather than at the corners.

In some embodiments, the lateral shape, pattern and pitch (centre-to-centre spacing) of the columnar termination trenches14may be the same as that for the columnar trenches41of the active transistor cells40of the active area11.

In the active area11, transistor cells40each comprise a columnar trench41having a stepped field dielectric structure19and the mesas46comprise the drift region20of a first conductivity type, a body region21of a second conductive type that opposes the first conductivity type that is arranged on the drift region20and a source region49of the first conductive type that is arranged on the body region21and that extends to the first surface11. Typically, the source region49is more highly doped than the drift region20. For example, in some embodiments, the first conductivity type is n-type and the second conductivity type is p-type or vice versa.

In the transition region50, the inactive cells13′ each comprise a columnar trench14′ having a stepped field dielectric structure19′ and a termination mesa15′ that comprises a body region21of the second conductivity type that is arranged on the drift region20. In the transition region50, the body region21extends to the first surface22of the semiconductor substrate23so that no source region is provided. These cells13′ are, therefore, inactive. In other embodiments, the field dielectric structure19′ has a different form in which its thickness is greater on the lower portion of the side wall17than on the upper portion of the same side wall17. For example, the field dielectric19′ and the field plate18′ may each have the form illustrated in and described with reference to one ofFIGS.1B,2A and2B.

In the intermediate termination region52, the inactive cells13″ comprise a columnar trench14″ having a field dielectric structure19″ having a uniform thickness on the side wall17and a termination mesa15′ that comprises a drift region20that extends to the first ‘surface22of the semiconductor substrate2.3.

The transition region50is distinguishable from the intermediate termination region52by the presence of the body region20. The region of the semiconductor substrate23that is doped with the first conductivity type and provides the source region49is laterally smaller than the region of the semiconductor substrate23that is doped with the second conductivity type and that forms the body region21. The lateral extent of the body region21, as defined by the outer edge of the body region21, is less than the lateral extent of the drift region20and the first surface22.

The outer termination region53that surrounds and, in particular, is contiguous with the intermediate termination region52is free of inactive cells. Therefore, the outer termination region53is free of columnar trenches and mesas. The outer termination region53may include semiconductor material of the first conductivity type.

The mesas46of the active cells40, the termination mesas15of the inactive cells13of the transition region50and of intermediate termination region52of the edge termination region12include the drift region20comprising a first conductivity type. The drift region20and the outer termination region53may be formed from an epitaxial silicon layer.

If used in the edge termination region12, the at least one termination trench30, which may be a continuous trench or comprise a plurality of sections30′ arranged in a ring shape, is positioned in the intermediate termination region52and laterally surrounds the array of columnar termination trenches14′. The termination trench30is filled with at least one dielectric material37. In contrast to the columnar termination trenches14, the termination trench30is free of electrically conductive material and, therefore, free of a field plate. The termination trench30has side walls31,32and a base36that is positioned at a depth dcfrom the first major surface22. The depth de may be substantially the same as the depth d of the columnar trenches14,41or may be less than or greater than the depth d. The depth dcof the termination trench30is, however, greater than the depth dgof the gate trench60.

The dielectric material37positioned in the termination trench30has a dielectric constant εr which is lower than the dielectric constant of silicon which has εr of 11.7. Possible dielectric materials for the continuous trench50include SiO2with εr around 3.9, a vacuum with εr of 1.0 and silicon nitride with εr of around 6.0.

In some embodiments, the lateral shape of the gate trench60and the gate electrode61in the gate trench60has a form corresponding to the form of the columnar trenches41such that the distance between the gate trench60and the side wall45of the individual ones of the columnar trenches41is substantially uniform. For example, if the columnar trenches41are hexagonal in top view, the gate trench60and the gate electrode61positioned in the gate trench60may have a hexagonal ring shape such that the distance between the inner side wall of the hexagonal ring shape and the side wall45of the respective hexagonal columnar trench41is substantially uniform between the entire periphery of the columnar trench41and the entire inner side wall of the gate trench60. In other words, the gate trench60and gate electrode61are arranged concentrically with respect to the columnar trench41. The individual hexagonal rings of the gate trench60may be connected to form a grid shape in top view.

In another example, if the columnar trenches41have a square shape in top view, the gate trench60and the gate electrode61in the gate trench60have a square ring shape and the square ring shape is arranged laterally around and concentrically with respect to the columnar trench41arranged at its centre such that the distance between the inner side wall of the square ring shape of the gate trench60and the side wall45of the respective square columnar trench41is substantially uniform between the entire periphery of the columnar trench41and the entire inner side wall of the gate trench60.

FIG.6Aillustrates a plan view andFIG.6Bacross-sectional view of a portion of the semiconductor device10, which corresponds to a cross-sectional view of the semiconductor device ofFIG.5B.FIGS.6A and6Billustrates a portion of the active area11and the edge termination region12including the transition region50, the intermediate and outer termination regions52,53arranged in this order concentrically around the active area11. In this embodiment, the edge termination region12further comprises an inner termination region51that is arranged between the transition region50and the intermediate termination region52.

In the embodiment illustrated inFIGS.6A and6B, the columnar trenches41in the active area11and the columnar trenches14in the edge termination region12are arranged in an array having off set rows. The individual trenches14,41are hexagonal in top view and the array has a hexagonal pattern.

In the inner termination region51, the inactive cells13each comprise a columnar trench14′ having a stepped dielectric structure19′ and a termination mesa15′ that comprises a drift region20that extends to the first surface22of the semiconductor substrate23. The termination mesa15′ in the inner termination region51in contrast to the termination mesas15′ in the transition region50, does not include a body region.

The inner termination region51is also distinguishable from the intermediate termination region52in the profile of the field plate dielectric19. In the intermediate termination region52, the field dielectric19″ has a uniform thickness on the side wall17, whereas in the inner termination region51the field dielectric19′ has a smaller thickness at the top and a greater thickness in the lower portion of the side wall17and may have a stepped profile. The field dielectric19′ may have the same profile in the active area11, transition region50and inner termination region51.

In some embodiments, such as that shown and described with reference toFIGS.6A and6B, the edge termination region20further includes a doped region70of the second conductivity type. The outermost row of the columnar trenches14″ located in the intermediate termination region52is located within the doped region70.FIG.6Billustrates a cross-sectional view of a portion of the semiconductor substrate23with an active area11and edge termination region12corresponding to that ofFIG.6Aand shows the doped region70which laterally surrounds the sidewall17and base16of the outermost one of the columnar trenches14″ and the termination trench30. The outermost ones of the array of columnar trenches14′ have a field dielectric having the second field dielectric profile19′ and a substantially uniform thickness over the entire height of the sidewall17of the trenches. In other non-illustrated embodiments, the doped region70may laterally surround the termination trench30and be positioned adjacent to and spaced apart from one or more of the columnar trenches14″, which are positioned in the intermediate termination region52, by a portion of the drift region23.

In some embodiments and as illustrated inFIGS.6A and6B, the doped region70forms a continuous ring of the second conductivity type which laterally surrounds the remainder of the intermediate termination region52and extends in the mesa15″ located adjacent at least the outermost row of columnar trenches14″ located in the intermediate termination region52. In some embodiments, the continuous doped ring70of the second conductivity type may be arranged laterally adjacent to the termination trench30which laterally surrounds the intermediate termination region52. The doped region70may extend from the first major surface22into the substrate23by a depth which is at least the depth d of the columnar trenches14.

FIG.6Cillustrates a schematic top view of a semiconductor device10with an active area11and an edge termination region12according to an embodiment.FIG.6Dillustrates an enlarged view ofFIG.6CandFIG.6Ea cross-sectional view of the area A-A′. The semiconductor device10illustrated inFIGS.6Cto E differs from that illustrated inFIGS.6A and6Bin that the boundary54between the transition region50, which comprises a body region21, and the inner termination region51, which is without a body region, is located intermediate the width of the columnar trenches14′.

Referring toFIGS.6C to6E, a row1000of columnar trenches14, which are denoted with1001to1007, will now be described. In the view ofFIGS.6C and6D, the row1000of columnar trenches1001to1007are arranged in this order in a vertical direction from the bottom to the top and in the cross-sectional view ofFIG.6E, the columnar trenches1001to1007are arranged in this order in the row1000from right to left.

The columnar trench1001is located in the active area11and has a field dielectric19′ having the first non-uniform profile, e.g. the stepped profile ofFIG.1Bor non-uniform profile ofFIG.2A or2B. The columnar trench1001is laterally surrounded by a mesa15comprising a drift region20, a body region21and a source region49and also includes a contact100electrically connecting the source region49and field plate18′ to the overlying source metal101that is arranged on the first major surface22of the substrate23.

The adjacent columnar trench1002in the row1000is located in the transition region50of the edge termination region12and also comprises a field dielectric19′ having the first non-uniform profile. The columnar trench1002is laterally surrounded by a mesa15comprising a drift region20and a body region21that extends to the first major surface22. The columnar trench1002also includes a contact102electrically connecting the field plate18′ in the trench14′ to the overlying source metal101. The columnar trench1002differs from the columnar trench1001in that the columnar trench1002is not surrounded by the source region49.

The adjacent columnar trench1003in the row1000is located in the transition region50of the edge termination region12and also comprises a field dielectric19′ having the first non-uniform profile and is laterally surrounded by a mesa15comprising a drift region20and a body region21that extends to the first major surface22. The columnar trench1003differs from the columnar trench1002in that it is devoid of a contact102between the body region21and the source metal102.

The adjacent columnar trench1004of the row1000is located at the boundary54between the transition region50and the inner termination region51. The columnar trench1004comprises a field dielectric19′ having the first non-uniform profile.

The inboard periphery of the columnar trench1004is bounded by a mesa15′ comprising the drift region20and body region21that extends to the first major surface22. The outboard facing periphery of the columnar trench1004is bounded by a mesa15′ comprising the drift region20only. “Inboard” denotes directions facing towards the centre of the first major surface22and “outboard” denotes directions facing towards the side faces56of the first major surface22. The columnar trench1004is also devoid of a contact between the body region21and the source metal102.

The adjacent columnar trench1005of the row1000is located in the inner termination region51of the edge termination region12and comprises a field dielectric19′ having the first non-uniform profile. The columnar trench1005is laterally surrounded by a mesa15comprising the drift region20only that that extends to the first major surface22.

The transition55between the inner termination region51and intermediate termination region52is also shown inFIGS.6C to6E. The next columnar trenches1006and1007of the row1000are located in the intermediate region52, and are each laterally entirely surrounded by a mesa15″ formed of the drift region20only. The columnar trenches1007and1008each have a field plate18″ having a substantially uniform cross-sectional area over its height and a field dielectric19″ having a substantially uniform thickness over the entire height of the side wall17of the trench14″.FIGS.6C and6Dalso illustrate the gate104located in the mesas15. The field plates18′,18″ in all of the columnar trenches are electrically connected to source potential.

The termination trench30is located outboard of the columnar trench1008and in the embodiment illustrated inFIG.6Cis a continuous trench. The termination trench30has an inner side wall31and an outer side wall32that are substantially parallel to one another such that the trench has a substantially uniform width. The termination trench30laterally surrounds the columnar trenches14″ and has a meandering form in top view such that the spacing between the inner side wall31and the outermost row or ring of columnar trenches14″ is substantially the same. In other words, the outermost mesa15″ has a substantially uniform width. The continuous termination trench30may however be replaced by a termination trench comprising a plurality of separate trench sections arranged in a ring.

FIGS.7A to7Dillustrates a method with which the doped region70may be fabricated in a semiconductor device, such as a transistor device. Referring toFIG.7A, a plurality of columnar trenches14are formed in a first major surface22of a semiconductor substrate23having a first conductivity type, the columnar trenches14each having a base16and a side wall17extending form the base16to the first major surface22. The columnar trenches14may be arranged in an array of offset rows or in a square grid array. The plurality of trenches14are arranged in the edge termination region12of the semiconductor device10and may also be arranged in the active area11of the semiconductor device10. The columnar trenches14may be formed by etching, for example. The base16and side wall17of the columnar trenches14are lined with a field dielectric19which also extends over the first major surface22of the semiconductor substrate23.

A dielectric layer90may be formed on the first major surface22and optionally on the side wall17and base16of the trenches14. The dielectric layer90is thicker on the first major surface22than on the side wall17and base16of the trenches14. The dielectric layer90may be formed by thermal growth of an oxide, e.g. oxidation of the silicon substrate to form a silicon oxide lining and/or deposition of a dielectric, e.g. TEOS deposition of SiOx.

Referring toFIG.7B, at least some of the columnar trenches14are covered, for example by a mask75, so that the dopants of the second conductivity type are not implanted to the covered columnar trenches14. The covered columnar trenches14may be located in the active area11and also in laterally inboard parts of the edge termination region12. Dopants of the second conductivity type are implanted into the base and adjoining portions of the side walls of an outermost one of the columnar trenches14″ that remain uncovered by the mask75. The dopants are implanted over a first depth range of the columnar14from the first major surface22, as shown schematically by the arrows71, to form a doped region74that laterally surrounds the base16and lower side wall17of the trench14.

In some embodiments and referring toFIG.7C, the dopants of the second conductivity type are implanted into the side walls17of the outermost one of the columnar trenches14over a second depth range from the first major surface22, as shown schematically by the arrows72, to form a further doped region74′ arranged vertically above the doped region74. At least a part of the second depth range is vertically adjacent the first depth range. The depth range of the implant may be selected by selecting the angle or tilt of the implant. A wider tilt is used for a lower depth from the first major surface22.

Referring toFIG.7D, after implantation of the dopants of the second conductivity type at one, two or more depths, to form one, two or more doped regions74,74′, a so-called drive-in process may be carried out, e.g. by thermal annealing, as is schematically indicated by the arrows73. This may be carried out after removing the mask75. The annealing process may be used to form a continuous doped column and/or lateral doped ring70from the doped region(s)74,74′.

In some embodiments, the dielectric layer90is removed and the field dielectric19is formed on the side wall17and base16of the columnar trenches14. The field dielectric19may be formed by thermal growth of an oxide, e.g. oxidation of the silicon substrate to form a silicon oxide lining and/or deposition of a dielectric, e.g. TEOS deposition of SiOx, before the thermal annealing process or drive-in process is carried out. Afterwards, conductive material18for the field plates is inserted into the columnar trenches14.

In some embodiments, a continuous ring70of the second conductivity type is formed that extends from the first major surface22of the semiconductor substrate23into the semiconductor substrate23. In some embodiments, one or more of the outermost rows or rings of columnar trenches14in the edge termination region12are located in and surrounded by the continuous doped ring70of the second conductivity type—This arrangement may result from the spreading of the implanted regions74as a result of the thermal annealing process. The doped ring70may extend into the semiconductor substrate23by a depth that is at least as greater or greater than the depth d of the base16of the columnar trenches14from the first major surface22of the semiconductor substrate23.

FIGS.8A to8Hillustrates a method with which the columnar trench14with a field dielectric19having a stepped profile19′ can be fabricated. Referring toFIG.8A, at least one columnar trench14is formed in a first major surface22of a semiconductor substrate23having a first conductivity type. Typically, a plurality of columnar trenches14are formed that are arranged in an array, e.g. a square grid array or offset rows, having a common spacing. Each columnar trench14has a base16and a side wall17extending form the base16to the first major surface22. The plurality of trenches14may be arranged in the edge termination region12and/or in the active area11of the semiconductor device10. The columnar trenches14may be formed by etching, for example.

Referring toFIG.8B, the base16and side wall17of the columnar trenches14are then lined with a field dielectric19. The field dielectric19may be formed by thermal growth of an oxide, e.g. oxidation of the silicon substrate23to form a silicon oxide lining and/or deposition of a dielectric, e.g. TEOS deposition of SiOx. Conductive material18is then inserted into the columnar trenches14which may be used to form a field plate.

Referring toFIG.8C, a second subset80of the plurality of columnar trenches14that lies laterally outboard of a first subset81of the plurality of columnar trenches14is covered by a cover, e.g. a mask82, leaving the first subset81uncovered. Whilst covering the second subset80of the plurality of columnar trenches14that lies laterally outboard of a first subset81of the plurality of columnar trenches14, the following method is carried out in the first subset of trenches80. An upper portion of the conductive material18is removed from an upper portion of the columnar trenches14and the field dielectric19arranged on the side wall17is exposed.

Referring toFIG.8D, a portion of the exposed field dielectric19is removed and the thickness of the exposed field dielectric19arranged on the side wall of the upper portion of the columnar trenches14is reduced. The side wall17in the upper portion of the trench14remains covered by a thin layer of the field dielectric19.

Referring toFIG.8E, conductive material18is inserted into the columnar trench14and the upper portion of the trench14is filled with the conductive material18to from a field plate18with a wider upper portion and narrower lower portion. Consequently, the field dielectric19has a smaller thickness in the upper portion and a larger thickness in the lower portion of the columnar trench14has a stepped profile.

The method may continue by forming the transistor device and further features of the edge termination region12and active region11. Referring toFIG.8F, dopants of a second conductivity type are implanted into a first predetermined area83of the first major surface to form a body region20as is indicated schematically by the arrows85. The second subset81of the plurality of columnar trenches14is positioned laterally outboard of the first predetermined area83. In some embodiments, the entire first subset80of the plurality of columnar trenches14is positioned laterally within the first predetermined area83. In other embodiments, one or more or the outermost ones of the columnar trenches of the first subset80is positioned laterally outside of the first predetermined area83.

Referring toFIG.8G, dopants of the first conductive type are implanted into a second predetermined area84that is smaller than the first predetermined area83, as is indicated schematically with the arrows86. The dopants of the first conductive type form the source region49so that the second predetermined area84corresponds to the active area11of the transistor device.

A gate trench60and gate electrode61may be them be formed in the mesas15between neighbouring ones of the columnar trenches14in the second predetermined area84, as shown inFIG.8H.

The performance of transistor devices, including MOSFET devices is improved due to the structure of the edge termination region according to any one of the embodiments described herein and an improved avalanche robustness and a low on-state resistance is achieved.

Although the present disclosure is not so limited, the following numbered examples demonstrate one or more aspects of the disclosure.Example 1. A semiconductor device, comprising:i. an active area and an edge termination region laterally surrounding the active area, whereinii. the active area comprises a plurality of active transistor cells,iii. the edge termination region comprises a plurality of inactive cells, each inactive cell comprising a columnar trench and a termination mesa arranged adjacent to the columnar trench;iv, wherein each of the columnar trenches comprises a base, a side wall, a field plate, and a field dielectric arranged on the base and the side wall and surrounding the field plate, wherein each of the field dielectrics has a first thickness in an upper region of the field plate and a second thickness in a lower region of the field plate, the first thickness being smaller than the second thickness, andv. wherein each of the termination mesas comprises a drift region of a first conductivity type and a body region of a second conductivity type arranged above the drift region.Example 2. The semiconductor device of example 1, wherein the plurality of inactive transistor cells are directly adjacent to one or more of the plurality of active transistor cells.Example 3. A semiconductor device according to example 1 or example 2, wherein the upper region is contiguous to the body region and the lower region is contiguous to the drift region, wherein the first thickness (t1) is equal to or smaller than 1.15 times the second thickness (t2) or t1≤1.2 t2or t1≤1.5 t2.Example 4. A semiconductor device according to any one of examples 1 to 3, wherein the side face of each of the field plates comprises a step such that an upper portion of the field plate has a width that is greater than a width of a lower portion of the field plate and such that the field dielectric has the first thickness t1in the upper region and the second thickness t2in the lower region.Example 5. A semiconductor device according to example 4, wherein the step is located at a first depth (d1) from the first major surface of the semiconductor substrate and a pn junction is formed between the body region and the drift region at a second depth (dpn) from the first major surface of the semiconductor substrate, wherein the first depth (d1) is greater than the second depth (dpn).Example 6. A semiconductor device according to any one of examples 1 to 5, wherein the field plate of the first columnar trenches has a T-shape and the field plate of the second columnar trenches has a columnar shape.Example 7. A semiconductor device according to any one of examples 1 to 6, wherein the one or more inactive transistor cells are comprised in a transition region of the edge termination region that laterally surrounds the active region,wherein the edge termination region further comprises an inner termination region that laterally surrounds the transition region, wherein the inner termination region comprises a second plurality of inactive cells, each inactive cell of the second plurality of inactive cells comprising a second columnar trench having a base and a side wall and comprising a field plate and a second termination mesa comprising a drift region of a first conductivity type and no body region of the second conductivity type, wherein the drift region extends to the first major surface; wherein each field dielectric of the second columnar trenches has the first thickness adjacent an upper region of the field plate and the second thickness adjacent a lower region of the field plate.Example 8. A semiconductor device according to example 7, wherein the edge termination region further comprises an intermediate termination region that laterally surrounds the inner termination region, wherein the intermediate termination region comprises one or more inactive cells, each inactive cell comprising a third columnar trench having a base and a side wall and comprising a field plate and a third termination mesa comprising a drift region of a first conductivity type and no body region of the second conductivity type, wherein the drift region extends to the first major surface; wherein the third columnar trench comprises a field dielectric that is arranged on the base and the side wall and that has a thickness, t2, on the side wall that varies by less than ±1.1 t2.Example 9. A semiconductor device according to any one of examples 1 to 8, wherein the first and second and third columnar trenches are arranged in an array comprising offset rows, wherein the array is in the transition region and the intermediate termination region, and the pitch of the first and second columnar and third trenches in the array is substantially equal throughout the array.Example 10. A semiconductor device according to example 9, wherein the array is further arranged in the active area.Example 11. A semiconductor device according to any one of examples 1 to 10, wherein in the transition region the body region of the termination mesa extends to the first major surface.Example 12. A semiconductor device according to one of examples 1 to 117, wherein the edge termination region further comprises a continuous ring of the second conductivity type that laterally surrounds the plurality of inactive cells.Example 13. A semiconductor device according to example 12, wherein the continuous ring of the second conductivity type is arranged laterally adjacent to a continuous trench that laterally surrounds the continuous ring and that comprises a field plate.Example 14. A semiconductor device according to any one of examples 1 to 13, wherein the edge termination region further comprises an outer termination region that laterally surrounds the intermediate termination region and extends to the side face of the semiconductor substrate, wherein the outer termination region is devoid of columnar trenches.Example 15. A semiconductor device according to any one of examples 1 to 14, wherein the edge termination region further comprises at least one termination trench that laterally surrounds the intermediate transition region and that comprises dielectric material.Example 16. A semiconductor device according to example 15, wherein the termination trench is continuous and uninterrupted laterally surrounds the intermediate transition region or the termination trench comprises a plurality of trench sections arranged in a ring that laterally surrounds the intermediate transition region.Example 17. A semiconductor device according to example 15 or example 16, wherein the termination trench laterally surrounds the continuous ring of the second conductivity type.Example 18. A semiconductor device according to any one of examples 15 to 17, wherein the termination trench is spaced apart from an outermost columnar termination trench by a distance douterand 50 nm≤douter≤2 μm.Example 19. A semiconductor device according to any one of examples 15 to 18, wherein the dielectric material comprises portions of differing composition.Example 20. A semiconductor device according to any one of examples 15 to 19, wherein the dielectric material comprises at least one dielectric layer that lines sidewalls and a base of the continuous trench.Example 21. A semiconductor device according to any one of examples 15 to 20, wherein the at least one dielectric layer surrounds a gap or an enclosed cavity positioned in the continuous trench.Example 22. A semiconductor device according to any one of examples 15 to 21, wherein the dielectric material comprises a first dielectric layer and a second dielectric layer arranged on the first dielectric layer.Example 23. A semiconductor device according to example 22, wherein the first dielectric layer is thinner than the second dielectric layer.Example 24. A semiconductor device according to example 22 or example 23, wherein the first dielectric layer is a thermally grown SiOxlayer and the second dielectric layer is a TEOS layer.Example 25. A semiconductor device according to one of examples 1 to 24, wherein each active transistor cell comprises a mesa and a columnar trench, and the mesa comprises the drift region, the body region arranged on the drift region, a source region of the first conductivity type arranged on the body region and a gate trench comprising a gate electrode.Example 26. A semiconductor device according to example 25, wherein the columnar trench of each active transistor cell comprises a base, a side wall, a field plate, and a field dielectric arranged on the base and the side wall and surrounding the field plate, wherein the field dielectric has a first thickness in an upper region of the field plate and a second thickness in a lower region of the field plate, the first thickness being smaller than the second thickness.Example 27. A semiconductor device according to example 25 or example 26, wherein the gate trench extends through the source region and the body region into the drift region, wherein each of the columnar trenches extends from the first surface through the body region and into the drift region.Example 28. A semiconductor device according to any one of examples 25 to 27, further comprising at least one gate finger extending from the active area over the edge termination region to a gate runner.Example 29. A semiconductor device according to example 28, wherein the gate runner is positioned laterally between the side face of the semiconductor body and the continuous trench in the outer termination region.Example 30. A method for fabricating a semiconductor device, the method comprising:i. forming a plurality of columnar trenches in a first major surface of a semiconductor substrate having a first conductivity type, the columnar trenches being arranged in an array of offset rows and each having a base and a side wall extending form the base to the first major surface;ii. lining the base and side wall of the columnar trenches with a field dielectric;iii. inserting conductive material into the columnar trenches;iv. whilst covering a second subset of the plurality of columnar trenches that lies laterally outboard of a first subset of the plurality of columnar trenches, in the first subset of trenches:1. removing an upper portion of the conductive member from an upper portion of the columnar trenches and exposing the field dielectric arranged on the side wall;2. removing a portion of the exposed field dielectric and reducing the thickness of the exposed field dielectric arranged on the side wall of the upper portion of the columnar trenches;3. inserting conductive material into the columnar trench and filling the upper portion of the trench with the conductive material;v. implanting dopants of a second conductivity type into a first predetermined area of the first major surface to form a body region, wherein the second subset of the plurality of columnar trenches is positioned laterally outboard of the first predetermined area and the first subset of the plurality of columnar trenches is positioned laterally within the first predetermined area;vi. implanting dopants of the first conductive type into a second predetermined area that is smaller than the first predetermined area.Example 31. A method according to example 30, wherein an outer one of the first subset of the plurality of columnar trenches is positioned laterally outboard of the first predetermined area and in the second predetermined area.Example 32. A method according to example 30 or example 31, wherein an outermost one of the first subset of the plurality of columnar trenches is arranged laterally outboard of the second predetermined area.Example 33. A method according to any one of examples 30 to 32, further comprising:i. forming a termination trench that laterally surrounds the array of columnar trenches, the termination trench having a base and side walls;ii. implanting dopants of the second conductivity type into the side walls of the termination trench over a first depth range from the first major surface.Example 34. A method according to example 33, wherein the termination trench is continuous and uninterrupted laterally surrounds the array of columnar trenches or the termination trench comprises a plurality of trench sections arranged in a ring and the ring laterally surrounds the array of columnar trenches.Example 35. A method according to example 33 or example 34, further comprising implanting dopants of the second conductivity type into the base of the termination trench.Example 36. A method according to any one of examples 33 to 35, further comprising: implanting dopants of the second conductivity type into the side walls of the termination trench over a second depth range from the first major surface, wherein at least a part of the second depth range is vertically adjacent the first depth range.Example 37. A semiconductor device, comprising:i. an active area and an edge termination region laterally surrounding the active area, whereinii. the active area comprises a plurality of active transistor cells,iii. the edge termination region comprises a termination trench, a first inactive cell and a second inactive cell, wherein the first inactive cell comprises a first columnar trench and the second inactive cell comprises a second columnar trench,iv. wherein the first inactive cell and the second inactive cell are arranged directly adjacent to each other and directly adjacent to the termination trench,v. wherein the termination trench is filled completely with a dielectric, andvi. wherein the first trench and the second are arranged in an array comprising offset rows, andvii. wherein a shortest distance between the termination trench and the first columnar trench and a shortest distance between the termination trench and the second columnar trench is the same.Example 38. A semiconductor device according to example 37, wherein the shortest distance between the termination trench and the first columnar trench is smaller than a shortest distance between the first columnar trench and the second columnar trench.Example 39. A semiconductor device according to example 37 or example 38, wherein the termination trench comprises an inner and an outer side wall section, wherein the inner and outer sidewall sections extend substantially parallel to one another.Example 40. A semiconductor device according to example 39, wherein the termination trench is a continuous trench that laterally surrounds the active area and comprises a meandering form in top view such that the spacing of the inner side wall section from the first columnar trench and from the second columnar trench is substantially uniform and such that the spacing of the outer side wall section from the first columnar trench and from the second columnar trench is substantially uniform, or the termination trench comprises a plurality of trench sections arranged in a ring, wherein the ring laterally surrounds the active area and comprises a meandering form in top view such that the spacing of the inner side wall section from the first columnar trench and from the second columnar trench is substantially uniform and such that the spacing of the outer side wall section from the first columnar trench and from the second columnar trench is substantially uniform.Example 41. A semiconductor device according to any one of examples 37 to 40, wherein the first and second columnar trenches have a plurality of side wall sections, adjoining side wall sections forming an internal angle α1of greater than 90° and wherein a shortest distance between the termination trench and at least two adjoining side walls sections of the first columnar trench and a shortest distance between the termination trench and at least two adjoining side wall sections of the second columnar trench is substantially the same.Example 42. A semiconductor device according to example 41, wherein the inner and outer side wall section each comprise a plurality of side wall subsections, wherein adjoining side wall subsections forming an internal angle α2and α2=α1.Example 43. A semiconductor device according to any one of examples 37 to 42, wherein the first and second inactive cells are arranged in an intermediate termination region of the edge termination region, wherein the first inactive cell further comprises a field plate arranged in the first columnar trench and a termination mesa comprising a drift region of a first conductivity type, wherein the drift region extends to the first major surface and the second inactive cell further comprises a field plate arranged in the second columnar trench and a termination mesa comprising a drift region of a first conductivity type, wherein the drift region extends to the first major surface.Example 44. A semiconductor device according to example 43,i. wherein the edge termination region further comprises a transition region that laterally surrounds the active area, and the intermediate termination region laterally surrounds the transition region,ii. wherein the transition region comprises at least one third inactive cell, the third inactive cell comprising a third columnar trench comprising a field plate and a termination mesa comprising a drift region of a first conductivity type and a body region of the second conductivity type that opposes the first conductivity type, wherein the body region is arranged on the drift region.Example 45. A semiconductor device according to any one of examples 37 to 44, wherein the body region extends to the first major surface of the semiconductor substrate.Example 46. A semiconductor device according to example 45, wherein the first, second and third columnar trenches are arranged in the array and the array is arranged in the active area, in the transition region and the intermediate termination region, wherein the pitch of the first, second and third columnar trenches in the array is substantially equal throughout the array.Example 47. A semiconductor device according to any one of examples 37 to 46, wherein the third columnar trenches each comprise a base, a side wall and a field dielectric that is arranged on the base and the side wall, wherein the field dielectric has a thickness t1in a first region of the side wall that is contiguous to the body region and a thickness t2in a second region of the side wall that is contiguous to the drift region, wherein t1≤1.15 t2) or t1≤1.2 t2or t1≤1.5 t2,Example 48. A semiconductor device according to example 47, wherein the side face of the field plate of the third columnar trenches comprises a step such that an upper portion of the field plate has a width that is greater than a width of a lower portion of the field plate and such that the field dielectric has the thickness t1in the first region of the third columnar trench and the thickness t2in the second region of the third columnar trench.Example 49. A semiconductor device according to example 48, wherein the step is located at a depth d1from the first major surface of the semiconductor substrate and the pn junction formed between the body region and the drift region has a depth dpnfrom the first major surface of the semiconductor substrate, wherein d1>dpn.Example 50. A semiconductor device according to any one of examples 37 to 49, wherein the field plate of the third columnar trenches has a T-shape and the field plate of the second columnar trenches has a columnar shape.Example 51. A semiconductor device according to any one of examples 37 to 50, wherein the first and second columnar trenches each comprise a base, a side wall and a field dielectric that is arranged on the base and the side wall, wherein the field dielectric that has a thickness, t2, on the side wall that varies by less than ±1.1 t2.Example 52. A semiconductor device according to one of examples 37 to 51, wherein the edge termination region further comprises an inner termination region that laterally surrounds the transition region, wherein the intermediate termination region laterally surrounds the inner termination region and the inner termination region comprises one or more third inactive cells comprising a third columnar trench comprising a field plate and a termination mesa comprising a drift region of the first conductivity type that extends to the first surface.Example 53. A semiconductor device according to one of examples 37 to 54, wherein each active transistor cells comprises a mesa and a third columnar trench, wherein the mesa comprises the drift region of the first conductivity type, the body region arranged on the drift region, a source region of the first conductivity type arranged on the body region and a gate trench comprising a gate electrode.Example 54. A semiconductor device according to any one of examples 37 to 53, wherein the edge termination region further comprises an outer termination region that laterally surrounds the intermediate termination region and extends to the side face of the semiconductor substrate, wherein the outer termination region is devoid of columnar trenches.Example 55. A semiconductor device according to any one of examples 37 to 54, wherein the edge termination region further comprises at least one termination trench that laterally surrounds the intermediate transition region and that comprises dielectric material.Example 56. A semiconductor device according to example 55, wherein the termination trench is continuous and uninterrupted laterally surrounds the intermediate transition region or the termination trench comprises a plurality of trench sections arranged in a ring that laterally surrounds the intermediate transition region.Example 57. A semiconductor device according to example 55 or example 56, wherein the termination trench laterally surrounds the continuous ring of the second conductivity type.Example 58. A semiconductor device according to any one of examples 37 to 57, wherein the termination trench is spaced apart from an outermost columnar termination trench by a distance douterand 50 nm≤douter≤2 μm.Example 59. A semiconductor device according to any one of examples 37 to 58, wherein the dielectric material comprises portions of differing composition.Example 60. A semiconductor device according to any one of examples 37 to 59, wherein the dielectric material comprises at least one dielectric layer that lines sidewalls and a base of the continuous trench.Example 61. A semiconductor device according to any one of examples 37 to 60, wherein the at least one dielectric layer surrounds a gap or an enclosed cavity positioned in the continuous trench.Example 62. A semiconductor device according to any one of examples 37 to 61, wherein the dielectric material comprises a first dielectric layer and a second dielectric layer arranged on the first dielectric layer.Example 63. A semiconductor device according to example 62, wherein the first dielectric layer is thinner than the second dielectric layer.Example 64. A semiconductor device according to example 62 or example 63, wherein the first dielectric layer is a thermally grown SiOxlayer and the second dielectric layer is a TEOS layer.Example 65. A semiconductor device, comprising:i. an active area and an edge termination region laterally surrounding the active area, whereinii. the active area comprises a plurality of active transistor cells,iii. the edge termination region comprises one or more first inactive cells and one or more second inactive cells,iv. wherein each of the one or more first inactive transistor cells comprises a first columnar trench having a first base and a first side wall and comprises a first field plate and a first field dielectric structure that is arranged on the first base and the first side wall and that surrounds the first field plate,v. wherein each of the one or more second inactive transistor cells comprises a second columnar trench having a second base and a second side wall and comprises a second field plate and a second field dielectric structure that is arranged on the second base and the second side wall and that surrounds the second field plate,vi. wherein the first field dielectric structure has a different thickness profile than the second field dielectric structure.Example 66. A semiconductor device according to example 65, wherein the semiconductor device comprises a semiconductor substrate in which the active area and the edge termination region are formed, wherein the substrate has an edge surrounding a first major surface and the second inactive cells are closer to an edge of the semiconductor substrate than the first inactive transistor cells.Example 67. A semiconductor device according to example 65 or example 66, wherein the field dielectric of the first columnar trench has a thickness that is greater on a lower portion of the side wall than on an upper portion of the side wall and the field dielectric of the second columnar trench has a thickness that is substantially uniform.Example 68. A semiconductor device according to any one of examples 65 to 68, wherein the field dielectric of the first columnar trench has a thickness t1in an upper region of the side wall and a thickness t2in a lower region of the side wall, wherein t1≤1.15 t2or t1≤1.2 t2or t1≤1.5 t2.Example 69. A semiconductor device according to any one of examples 65 to 68, wherein the side face of the field plate of the first columnar trenches comprises a step such that an upper portion of the field plate has a width that is greater than a width of a lower portion of the field plate and such that the field dielectric has the thickness t1in the first region of the first columnar trench and the thickness t2in the second region of the first columnar trench.Example 70. A semiconductor device according to example 69, wherein the first inactive cells further comprise a termination mesa, wherein the termination mesa comprises a drift region of a first conductivity type and a body region of a second conductivity type that opposes the first conductivity type and the body region is arranged on the drift region, wherein the step is located at a depth d1from the first major surface of the semiconductor substrate and the pn junction formed between the body region and the drift region has a depth dpnfrom the first major surface of the semiconductor substrate, wherein d1>dpn.Example 71. A semiconductor device according to any one of examples 65 to 70, wherein the second inactive cells each comprises a field dielectric that is arranged on the base and the side wall and that has a thickness, t2, on the side wall that varies by less than ±1.1 t2.Example 72. A semiconductor device according to any one of examples 65 to 71, wherein the field plate of the first columnar trenches has a T-shape and the field plate of the second columnar trenches has a columnar shape.Example 73. A semiconductor device according to any one of examples 65 to 72, wherein the edge termination region comprises a transition region that laterally surrounds the active region and one or more of the first inactive cells are arranged in the transition region.Example 74. A semiconductor device according to example 73, wherein the edge termination region further comprises an intermediate region that laterally surrounds the transition region and the one or more second inactive cells are arranged in the intermediate region.Example 75. A semiconductor device according to example 73 or example 74, wherein the edge termination region further comprises an inner termination region that laterally surrounds the transition region, wherein the intermediate termination region laterally surrounds the inner termination region, wherein one or more of the first inactive cells are arranged in the inner termination region comprises one or more inactive cells comprising a first columnar trench comprising a field plate and a termination mesa comprising a drift region of the first conductivity type that extends to the first surface.Example 76. A semiconductor device according to any one of examples 74 to 75, wherein in the transition region, the first inactive cells comprise a mesa comprising a drift region and a body region is arranged on the drift region, wherein the body region extends to the first major surface, in the inner termination region, the first inactive cells comprise a mesa comprising a drift region extending to the first major surface and in the intermediate region the second inactive cells comprise a mesa comprising a drift region and the drift region extends to the first major surface.Example 77. A semiconductor device according to one of examples 74 to 76, wherein the first and second columnar trenches are arranged in an array comprising offset rows, wherein the array is arranged in the active area, in the transition region, the inner termination region and the intermediate termination region, and the pitch of the first and second columnar trenches in the array is substantially equal throughout the array.Example 78. A semiconductor device according to one of examples 65 to 77, wherein the active transistor cells each comprise a first columnar trench and an active mesa, wherein each active mesa comprises the drift region of the first conductivity type, the body region arranged on the drift region, a source region of the first conductivity type arranged on the body region and a gate trench comprising a gate electrode.Example 79. A semiconductor device according to one of examples 65 to 78, wherein the edge termination region further comprises a continuous ring of the second conductivity type that is arranged laterally outboard of the outermost second columnar trench in the intermediate termination region.Example 80. A semiconductor device according to example 79, wherein the continuous ring of the second conductivity type is arranged laterally adjacent to a continuous trench that laterally surrounds the intermediate termination region and that comprises a field plate.Example 81. A semiconductor device according to any one of examples 65 to 80, wherein the edge termination region further comprises an outer termination region that laterally surrounds the intermediate termination region and extends to the side face of the semiconductor substrate, wherein the outer termination region is devoid of columnar trenches.Example 82. A semiconductor device according to any one of examples 65 to 81, wherein the edge termination region further comprises at least one termination trench that laterally surrounds the intermediate transition region and that comprises dielectric material.Example 83. A semiconductor device according to example 82, wherein the termination trench is continuous and uninterrupted laterally surrounds the intermediate transition region or the termination trench comprises a plurality of trench sections arranged in a ring that laterally surrounds the intermediate transition region.Example 84. A semiconductor device according to example 82 or example 83, wherein the termination trench laterally surrounds the continuous ring of the second conductivity type.Example 85. A semiconductor device according to any one of examples 82 to 84, wherein the termination trench is spaced apart from an outermost columnar termination trench by a distance douterand 50 nm≤douter≤2 μm.Example 86. A semiconductor device according to any one of examples 82 to 85, wherein the dielectric material comprises portions of differing composition.Example 87. A semiconductor device according to any one of examples 82 to 86, wherein the dielectric material comprises at least one dielectric layer that lines sidewalls and a base of the continuous trench.Example 88. A semiconductor device according to any one of examples 82 to 87, wherein the at least one dielectric layer surrounds a gap or an enclosed cavity positioned in the continuous trench.Example 89. A semiconductor device according to any one of examples 82 to 88, wherein the dielectric material comprises a first dielectric layer and a second dielectric layer arranged on the first dielectric layer.Example 90. A semiconductor device according to example 89, wherein the first dielectric layer is thinner than the second dielectric layer.Example 91. A semiconductor device according to example 89 or example 90, wherein the first dielectric layer is a thermally grown SiOxlayer and the second dielectric layer is a TEOS layer.Example 92. A semiconductor device according to any one of examples 78 to 91, wherein the gate trench extends through the source region and the body region into the drift region, wherein each of the columnar trenches extends from the first surface through the body region and into the drift region.Example 93. A semiconductor device according to any one of examples 78 to 92, further comprising at least one gate finger extending from the active area over the edge termination region to a gate runner.Example 94. A semiconductor device according to example 93, wherein the gate runner is positioned laterally between the side face of the semiconductor body and the continuous trench in the outer termination region.