Semiconductor optical devices and method for forming

A semiconductor optical device includes an insulating layer, a photoelectric region formed on the insulating layer, a first electrode having a first conductivity type formed on the insulating layer and contacting a first side of the photoelectric region, and a second electrode having a second conductivity type formed on the insulating layer and contacting a second side of the photoelectric region. The photoelectric region may include nanoclusters or porous silicon such that the device operates as a light emitting device. Alternatively, the photoelectric region may include an intrinsic semiconductor material such that the device operates as a light sensing device. The semiconductor optical device may be further characterized as a vertical optical device. In one embodiment, different types of optical devices, including light emitting and light sensing devices, may be integrated together. The optical devices may also be integrated with other types of semiconductor devices, such as vertical field-effect transistors.

FIELD OF THE INVENTION

This invention relates generally to semiconductor optical devices, and more specifically, to vertically integrated semiconductor optical devices.

RELATED ART

Semiconductor optical devices may include light emitting diodes (LEDs), lasers, photo sensors, electroluminescent displays. One method known today for forming such devices is through the use of Gallium Arsenide (GaAs) or Cadmium Selenide (CdSe). However, these materials are not compatible with silicon CMOS processing, which prevents the ability to effectively integrate them with other silicon-based devices.

Another known method used today, use semiconductor structures, such as silicon structure, which are planar where the contacts are on the top and bottom of the device. Thus, these type of planar structures occupy large areas of silicon on a wafer. For example,FIG. 1illustrates in schematic form, a cross section of a prior art optical device8. Optical device8includes a semiconductor p+ region6, a semiconductor intrinsic region4, and a semiconductor n+ region2, where typically, p+ region6is located at a top surface of a semiconductor wafer and n+ region2is located at a bottom surface of a wafer. Note that based on the materials chosen for semiconductor intrinsic region4, device8may operate as an LED or a photo sensor. For example, in the case of an LED, intrinsic region4may be formed of porous silicon or discrete silicon nanoclusters. However, although device8may be formed using silicon, the sidewalls of device8are not used for emitting or detecting light or injecting holes and electrons. Therefore, device8does not effectively use the available dimensions. Furthermore, if planar contacts are needed, extra area is needed to route a contact to the n+ region or p+ region to the opposite side of the wafer. Therefore, a need exists for improved semiconductor optical devices which may make use of sidewall regions and which may be integrated with other types of semiconductor devices.

DETAILED DESCRIPTION OF THE DRAWINGS

One embodiment of the present invention relates to an improved optical semiconductor device or element which may be integrated with other types of optical semiconductor devices or elements or other types of semiconductor devices or elements. In one embodiment, nanoclusters are used within a photoelectric region of a vertical optical device, where the sides of the photoelectric region are in contact with conductive electrodes of different conductivity types which allow for the emitting of light. For example, these devices may include LEDs or lasers. In another embodiment, an intrinsic semiconductor material is used within a photoelectric region of a vertical optical device, where the sides of the photoelectric region are in contact with conductive electrodes of different conductivity types which allow for the detecting of light. For example, these devices may include photo detectors or sensors. Also, as used herein, vertical optical devices are devices having conductive electrodes of different conductivity types formed along and in contact with opposite sides of a photoelectric region, in which the conductive electrodes and photoelectric region overlie an insulating layer.

FIG. 2illustrates a semiconductor device10having a semiconductor wafer18which has an opening20etched within a top layer, in accordance with one embodiment of the present invention. In the illustrated embodiments, semiconductor wafer18is a semiconductor on insulator (SOI) wafer having a substrate12, a dielectric layer14overlying substrate12, and a semiconductor layer16overlying dielectric layer14. In the illustrated embodiment, opening20is formed using conventional masking and etching techniques to expose underlying dielectric layer14. (Note that the shape of opening20may be adjusted as desired to create inclined sidewalls which may allow for varying light emitting characteristics of the resulting fin.) Substrate12may be any type of material which provides mechanical support to overlying layers. For example, in one embodiment, substrate12may be any semiconductor material such as silicon, gallium arsenide, silicon germanium etc., or any insulating material such as glass or sapphire. Dielectric layer14may be any type of insulating material, such as, for example, oxide, nitride, glass, sapphire, etc. If dielectric layer14is of sufficient strength to provide mechanical support to overlying layers, substrate12may not be present. For example, dielectric layer14may be formed of glass, and thus able to provide support for overlying layers without the need for substrate12.

FIG. 3illustrates semiconductor device10ofFIG. 2after formation of nanoclusters22overlying semiconductor layer16and within opening20. Nanoclusters22are embedded within a dielectric layer (not numbered). In one embodiment, nanoclusters22are formed by thermal nucleation of silicon on an oxide surface. Alternatively, other materials such as cadmium selenide, zinc sulfide, and other photo active materials may be used for nanoclusters22. The dielectric layer may be any type of insulating material, such as, for example, an oxide.

FIG. 4illustrates semiconductor device10ofFIG. 3after the formation of multiple layers of nanoclusters, where each layer may be formed, for example, by thermal nucleation of silicon on a subsequent oxide surface. Therefore, the dielectric layer between nanoclusters22may be formed of oxide and controlled by the thermal oxidation. In one embodiment, the size and density of nanoclusters22may be different in different regions, and may be controlled by the thermal conditions during and after formation of the nanoclusters. For example, different layers may include different size and/or different densities of nanoclusters. The formation of different size nanoclusters may allow for the generation of different light wavelengths. Also, each of nanoclusters22may vary in size and shape. For example, some nanoclusters may be round, while others may be oval or bone-shaped. In the illustrated embodiments, sufficient layers of nanoclusters are formed in order to fill opening20. In one embodiment, elements such as, for example, erbium may be incorporated into the nanoclusters to increase the light emitting efficiency.

In an alternate embodiment, a layer of porous silicon may be formed overlying semiconductor layer16and filling opening20. In this embodiment, a deposited silicon layer may be etched to form porous silicon. Alternatively, other porous semiconductor materials may be used, such as, for example, silicon germanium.

In yet another alternate embodiment, opening20may not be formed within semiconductor layer16. In this alternate embodiment, nanocluscers22and the surrounding dielectric layer may be formed overlying semiconductor layer16. Also, sufficient layers of nanoclusters22may be formed until a desired height is achieved to form the LED.

FIG. 5illustrates semiconductor device10after planarization to remove the nanoclusters22and the surrounding dielectric layer overlying semiconductor layer16. Therefore, only the portion of nanoclusters22and the associated dielectric layer within opening20remain. After planarization, a dielectric layer24is formed overlying semiconductor layer16and nanoclusters22. In one embodiment, dielectric layer24may be a nitride or an oxide layer, or a combination thereof. Alternatively, dielectric layer24may not be present. A patterned masking layer26is formed over dielectric layer24to define fins for the formation of vertical optical and semiconductor devices, in one embodiment, patterned masking layer26is a photo resist layer where conventional masking and patterning techniques may be used.

FIG. 6illustrates semiconductor device10after formation of fins28,30, and32. Fin28, having nanocluster portion36and overlying dielectric portion34, will be used in the formation of a light emitting element (such as, for example, an LED or a laser). Fin30, having an intrinsic semiconductor portion40and overlying dielectric portion38, will be used in the formation of a light detecting element (such as, for example, a photo sensor). Therefore, note that each of36and40may be referred to as photoelectric regions. These photoelectric regions will operate to emit or detect light or photons, as will be described below. Note that the photoelectric regions may or may not include overlying dielectric portions such as portions34and38. Fin32, having semiconductor portion44(which may be subsequently doped) and overlying dielectric portion42, will be used in the formation of a vertical metal-oxynitride field effect transistor (MOSFET). Note that each of fins28,30, and32may not include a dielectric portion such as dielectric portion34,38, and42.

FIG. 7illustrates semiconductor device10ofFIG. 6after formation of a patterned masking layer46which masks fins28and30while exposing fin32. In one embodiment, patterned masking layer46is a nitride or an oxide layer. Conventional deposition and patterning techniques may be used to form patterned masking layer46. After formation of patterned masking layer46, an implant may be performed into semiconductor portion44. For example, in one embodiment, boron is implanted for an n-type (i.e. NMOS) device and arsenic for a p-type (i.e. PMOS) device. Alternatively, semiconductor portion44may be left undoped. After doping (if performed), dielectric regions48are formed along the sides of semiconductor portion44. In one embodiment, a thermal oxidation is used to form dielectric regions48. Alternatively, a high dielectric constant (K) material is deposited over and along the sides of fin32. Therefore, note that in the illustrated embodiment fin40remains as an intrinsic semiconductor portion. After formation of dielectric regions48, patterned masking layer46may be removed, using, for example, a conventional wet or dry etch technique.

FIG. 8illustrates semiconductor device10ofFIG. 7after formation of a second semiconductor layer50overlying dielectric layer14and fins28,30, and32. Second semiconductor layer50may be any type of semiconductor material, such as, for example, silicon or silicon germanium. After formation of second semiconductor layer50, an angled implant52of a first species is performed into second semiconductor layer50from a first direction. Angled implant52results in regions54,56, and58doped with the first species. The first species has a first conductivity type, which, in the illustrated embodiment ofFIG. 8, is n+. Tn one embodiment, the n+ species may include, for example, phosphorous or arsenic.FIG. 9illustrates semiconductor device10ofFIG. 7after an angled implant60of a second species is performed into second semiconductor layer50from a second direction, different from the first direction. Angled implant60results in the formation of regions62,64, and66doped with the second species. The second species has a second conductivity type, different from the conductivity type of the first species inFIG. 8, which, in the illustrated embodiment ofFIG. 9, is p+. In one embodiment, the p+ species may include, for example, boron. Regions that respectively separate regions54,62, regions56,64and regions58,66are regions which include both species due to an overlap in angled implants52and60. These regions will be electrically highly resistive compared to those regions in which only one species is implanted. Note that angled implant52forms regions of a first species within second semiconductor layer50along one side of each of fins28,30, and32while angled implant60forms regions of a second species within second semiconductor layer50along an opposite side of each of fins38,30, and32. Note that in alternate embodiments, angled implants52and60may be performed in the reverse order. Also note that each of angled implants52and60can be performed using any species, where the first species may be implanted before or after the second species.

In an alternate embodiment, a patterned masking layer (not shown) may be used to mask fin32and the portions of second semiconductor layer50overlying fin32and portions of second semiconductor layer50along the sides of fin32during angled implants52and60such that regions58and66are not formed.

FIG. 10illustrates semiconductor device10ofFIG. 9after an anisotropic etch of second semiconductor layer50to form electrodes72,74,76,78,80, and82(which may also be referred to as conductive electrodes72,74,76,78,80, and82, respectively). This etch isolates the n+ and p+ regions and removes most or all of highly resistive such as portions68and70ofFIG. 9. Electrode72is formed along a first side of fin28and has a first conductivity type, and electrode74is formed along a second side, opposite the first side, of fin28and has a second conductivity type, different from the first conductivity type. Each of electrodes72and74are coupled to the photoelectric region of fin28, and each of electrodes72and74and fin28are formed on dielectric layer14. In the illustrated embodiment, electrode72is n+ and electrode74is p+. Electrode76is formed along a first side of fin30and has a first conductivity type, and electrode78is formed along a second side, opposite the first side, of fin30and has a second conductivity type, different from the first conductivity type. Each of electrodes76and78are coupled to the photoelectric region of fin30, and each of electrodes76and78and fin30are formed on dielectric layer14. In the illustrated embodiment, electrode76is n+ and electrode78is p+. Electrode80is formed along a first side of fin32and has a first conductivity type, and electrode82is formed along a second side, opposite the first side, of fin32and has a second conductivity type, different from the first conductivity type. Each of electrodes80and82are coupled to the semiconductive material of fin28and each of electrodes80and82and fin32are formed on dielectric layer14. In the illustrated embodiment, electrode80is n+ and electrode82is p+. Therefore, in one embodiment, electrodes72,74,76,78,80, and82may be formed using a self-aligned spacer etch since they may be formed in a manner similar to sidewall spacers. Note that in an alternate embodiment, this etch is optional and thus, may not be performed.

FIG. 12illustrates semiconductor device10after patterning and etching of conductive layer84and electrodes72,74,76,78,80, and82to form a conductive portion86overlying fin28and electrodes72and74, a conductive portion88overlying fin30and electrodes76and78, and a conductive portion90overlying fin32and electrodes80and82.FIG. 13illustrates a top down view of semiconductor device10ofFIG. 12. Note that after the patterning and etching of conductive layer84and electrodes72,74,76,78,80, and82, three separate devices (also referred to as elements) are formed, corresponding to each of fins28,30, and32. Note that each of the fins can have any shape. For example, fin32may have a dumbbell shape to accommodate source and drain contacts. Conventional photolithographic techniques may be used to pattern and etch conductive layer84and electrodes72,74,76,78,80, and82.

FIG. 14illustrates semiconductor device10ofFIG. 12after formation of a planarization layer92over dielectric layer14and conductive portions86,88,90. In one embodiment, planarization layer92is formed by depositing a photoresist layer.FIG. 15illustrates semiconductor device10ofFIG. 14after planarization of planarization layer92to a level which exposes top portions of conductive portions86,88, and90. In the illustrated embodiment, planarization layer92is etched to expose the top portions of conductive portions86,88, and90, and afterwards, the top portions of conductive portions86,88, and90are removed, thus resulting in conductive portions94,96,98,100,102, and104, all isolated from each other. Conductive portions94and96are located on opposite sides of fin28and are isolated from each other, conductive portions98and100are located on opposite sides of fin30and are isolated from each other, and conductive portions102and104are located on opposite sides of fin32and are isolated from each other. In an alternate embodiment, conductive portion90may not be etched to form conductive portions102and104such that the resulting device will not include isolated gates. Note that during the etching of conductive portions86,88, and90, portions of electrodes72,74,76,78,80, and82may also be removed.FIG. 16illustrates semiconductor device10ofFIG. 15after removal of planarization layer92. Conventional etch and cleaning techniques may be used to remove planarization layer92.

Therefore, as illustrated inFIG. 17, three devices or elements140,142, and144are formed. In the illustrated embodiment, elements140and142are vertical optical devices and element144is a vertical field-effect transistor. In the illustrated embodiment, element140, formed from fin28, is a light emitting element, such as, for example, an LED or a laser. In the illustrated embodiment, element142, formed from fin30, is a light detecting element, such as, for example, a photo sensor. In the illustrated embodiment, element144, formed from fin32, is a MOSFET. Therefore, one embodiment of the present invention may allow for the integration of different types of elements or devices, including both optical semiconductor elements or devices and other types of semiconductor elements or devices. In alternate embodiments, only one or two types of elements may be formed. For example, in one embodiment, an array of light emitting elements such as element144may be formed without including elements such as elements142and144. Note that in the illustrated embodiment, the dielectric portions overlying the photoelectric regions of fins28and30are removed, but in alternate embodiments, they may not be removed.

Element140may be used to emit light146, where light refers to photons that are emitted in a wide range of wavelengths. For example, light may include infrared, visible, and ultraviolet light. In element140, the n+ region operates as an electron source region and the p+ region operates as a hole source region. Thus, the recombination of electron and holes in the nanoclusters (or, in an alternate embodiment, in the porous semiconductor material, if used in place of the nanoclusters) emits photons. For example, in one embodiment, a voltage applied to electrodes72and74causes the recombination of electron and holes in the photoelectric region of element140, thus causing the photoelectric region to emit photons. In one embodiment, the sides of fin28may be varied (such as, for example, by creating sidewalls that make cavities which enable a laser or by angling the sides of opening20inFIG. 2) to result in coherent light waves, i.e. a laser. Although element140is illustrated as emitting light from a top portion of fin28, element140may emit light in any direction along the sides of fin28and in a plane vertical to the plane in which the figure is drawn. Therefore, element140includes a photoelectric region in contact with electrodes72and74of different conductivity types which allows element140to emit light.

Element142may be used to sense or detect light. In element142, light148is incident on the p-i-n junction formed by electrode78, fin30(having an intrinsic semiconductor photoelectric region), and electrode80. When light148is incident upon the p-i-n junction, a potential difference can be sensed between electrodes76and78. (For example, when sensing light, a conductivity of the photoelectric region changes in response to changes in light intensity.) Therefore, element142includes a photoelectric region in contact with electrodes72and74of different conductivity types which allows element142to detect or sense light.

FIG. 18illustrates a top down view106of an alternate embodiment in which all elements are integrated such that each of the fins of the elements are linearly coupled. For example, as illustrated inFIG. 18, a fin108may be used to form different types of elements, such as elements140,142, and144ofFIG. 17. In this embodiment, a first portion110of fin108may be formed having nanoclusters, in a manner similar to the formation of nanocluster portion36ofFIG. 6, where this first portion corresponds to an element146. Alternatively, first portion110may be formed of a porous semiconductor material. A second portion112of fin108may be formed of intrinsic semiconductor material where this second portion corresponds to an element148, and a third portion114of fin108may be formed of doped or undoped semiconductor material where this third portion corresponds to an element150. In the illustrated embodiment, each of first portion110, second portion112, and third portion114are all linearly coupled.

Each of the first, second, and third portions of fin108may therefore correspond to different types of elements or devices. For example, element146may be a light emitting element having electrodes118and120and isolated conductive portions116and122. Note that electrodes118and120and isolated conductive portions116and122are similar to electrodes74and72and isolated conductive portions96and94, respectively. Therefore, element146operates similar to element140. Element148may be a light detecting element having electrodes126and128and isolated conductive portions124and130. Note that electrodes126and128and isolated conductive portions124and130are similar to electrodes78and76and isolated conductive portions100and98, respectively. Therefore, element148operates similar to element142. Element150may be a MOSFET having source/drain regions136and138, and a gate region132. Note that element150includes an oxide134along sides of third portion114of fin108underlying gate region132. Note that in this embodiment, gate region132is not separated into two isolated portions. This can be done using conventional masking techniques such as using a nitride or oxide hard mask.

By now it should be appreciated that there has been provided improved optical semiconductor devices or elements for emitting and detecting light. Also provided is a method for integrating these types of devices with each other and with other types of semiconductor devices such as MOSFETs or vertical MOSFETs. The integration of these types of devices may allow for a wide range of applications, such as, for example, opto-couplers, displays, cameras, and the electronic circuitry to control them. The optical devices described herein may also be used to form photocells. Also note that each of the types of devices or elements may be independently used, as desired. Note that use of vertical optical devices (such as those illustrated inFIG. 17) may allow for reduced surface area as compared to prior art planar devices which are laterally formed within a semiconductor layer. Also, the sides of the photoelectric region of a vertical optical device may allow for the ability to use more of the photo emitting or detecting dimensions as compared to prior art devices.