Amplifier and transceiver including the amplifier

An amplifier and a transceiver including the amplifier are provided. The amplifier includes an input terminal; a first transistor of a first conductivity and a second transistor of a second conductivity, each transistor comprising a source terminal, a gate terminal and a drain terminal respectively, the source terminal of the first transistor being coupled to the source terminal of the second transistor, and the gate terminal of the first transistor and the gate terminal of the second transistor being coupled to the input terminal; and an output terminal coupled to the drain terminal of the first transistor and the drain terminal of the second transistor.

TECHNICAL FIELD

Various embodiments relate generally to an amplifier and a transceiver including the amplifier.

BACKGROUND

In March 2009, the Federal Communications Commission (FCC) introduced the Medical Device Radiocommunications Service (MedRadio) band in the range of 401-406 MHz which is a wireless communication regulation dedicated for biomedical telemetry. Formerly known as the 402-405 MHz Medical Implant Communication Service (MICS) band allocated in 1999, MedRadio is the superset of MICS in which additional adjacent bands at 401-402 MHz and 405-406 MHz are newly designated with twenty 100 kHz bandwidth channels to provide a total of five megahertz of contiguous spectrum and accommodate both implantable and wearable sensor devices for medical use.

Due to the need for reliable, continuous, and cost-effective health monitoring in hospitals and homes in recent years, both implantable and wearable sensors in Wireless Body Area Networks (WBAN) must meet ultra-low-power consumption for prolonged battery life. Since the wireless part of the sensor device usually consumes the most power, it is important to reduce both the current and the supply voltage of the transceiver to minimize the power consumption without compromising the performance.

Among several wireless bands for wearable sensor applications such as the industrial, scientific, and medical (ISM) frequencies at 433 MHz, 868-928 MHz, and 2.4 GHz respectively, some of these bands are not recognized globally while higher frequencies have the disadvantage of increased power consumption and free-space path loss. As higher frequencies are utilized for many other non-medical applications, it is prone to interference issues which are critical in biomedical applications where highly reliable communication is of key importance.

A low noise amplifier (LNA) usually dominates the total noise performance and sensitivity of a receiver used in biomedical applications. However, conventional LNAs typically have a limitation in performance improvement without increasing power, complexity or area.

FIG. 1ashows a conventional source degeneration cascode LNA (SDCLNA)102. The SDCLNA102has a simple topology and can achieve a good noise performance with sufficient gain even at low bias current due to the passive amplification from the input matching circuitry. However, in order to constrain the current consumption of the SDCLNA102to less than 150 μA, the transistor Mn1is biased close to threshold and its size is limited which leads to a small transconductance gmand a small gate-to-source capacitance Cgs. A small gmand Cgswill require large values of depletion capacitance Cd, gate inductance Lg, and source inductance Lsin order to match the impedance to 50Ω at 400 MHz. Thus, at a low frequency of operation (e.g. <1 GHz) and low power (<˜mW), large sizes of passive matching components (e.g. source inductor) are required for 50Ω matching. A small gmalso leads to a limitation in the gain and noise performance. Thus, there is a limitation of performance improvement (noise and linearity) without power increase. It is difficult to further improve the noise figure (NF) of the SDCLNA102without increasing the power consumption.

FIG. 1bshows a conventional current-reuse LNA104. The current-reuse LNA104has a current reuse topology and can provide an improved noise performance. However, the current-reuse LNA104requires additional DC feedback circuitry and additional passive components for performance improvement.

SUMMARY

According to one embodiment, an amplifier is provided. The amplifier includes an input terminal; a first transistor of a first conductivity and a second transistor of a second conductivity, each transistor comprising a source terminal, a gate terminal and a drain terminal respectively, the source terminal of the first transistor being coupled to the source terminal of the second transistor, and the gate terminal of the first transistor and the gate terminal of the second transistor being coupled to the input terminal; and an output terminal coupled to the drain terminal of the first transistor and the drain terminal of the second transistor is provided.

In one embodiment, the amplifier may further include a first depletion capacitor coupled between the gate terminal and the source terminal of the first transistor.

In one embodiment, the first depletion capacitor may include a positive terminal and a negative terminal. The positive terminal of the first depletion capacitor may be coupled to the gate terminal of the first transistor and the negative terminal of the first depletion capacitor may be coupled to the source terminal of the first transistor.

In one embodiment, the amplifier may further include a second depletion capacitor coupled between the gate terminal and the source terminal of the second transistor.

In one embodiment, the second depletion capacitor may include a positive terminal and a negative terminal. The positive terminal of the second depletion capacitor may be coupled to the gate terminal of the second transistor and the negative terminal of the second depletion capacitor may be coupled to the source terminal of the second transistor.

In one embodiment, the amplifier may further include a first resistor coupled between the drain terminal of the first transistor and a first voltage reference point.

In one embodiment, the first resistor may include a first terminal and a second terminal. The first terminal of the first resistor may be coupled to the drain terminal of the first transistor and the second terminal of the first resistor may be coupled to the first voltage reference point.

In one embodiment, the amplifier may further include a second resistor coupled between the drain terminal of the second transistor and a second voltage reference point.

In one embodiment, the second resistor may include a first terminal and a second terminal. The first terminal of the second resistor may be coupled to the drain terminal of the second transistor and the second terminal of the second resistor may be coupled to the second voltage reference point.

In one embodiment, the amplifier may further include a first output capacitor coupled between the drain terminal of the first transistor and the output terminal.

In one embodiment, the first output capacitor may include a positive terminal and a negative terminal. The positive terminal of the first output capacitor may be coupled to the drain terminal of the first transistor and the first terminal of the first resistor and the negative terminal of the first output capacitor may be coupled to the output terminal.

In one embodiment, the amplifier may further include a second output capacitor coupled between the drain terminal of the second transistor and the output terminal.

In one embodiment, the second output capacitor may include a positive terminal and a negative terminal. The positive terminal of the second output capacitor may be coupled to the drain terminal of the second transistor and the first terminal of the second resistor and the negative terminal of the second output capacitor may be coupled to the output terminal.

In one embodiment, the amplifier may further include a gate inductor having a first terminal and a second terminal, a first gate capacitor having a positive terminal and a negative terminal, and a second gate capacitor having a positive terminal and a negative terminal. The first terminal of the gate inductor may be coupled to the input terminal, and the second terminal of the gate inductor may be coupled to the positive terminal of the first gate capacitor and the positive terminal of the second gate capacitor. The negative terminal of the first gate capacitor may be coupled to the gate terminal of the first transistor and the positive terminal of the first depletion capacitor. The negative terminal of the second gate capacitor may be coupled to the gate terminal of the second transistor and the positive terminal of the second depletion capacitor.

In one embodiment, the amplifier may further include a source inductor having a first terminal and a second terminal, and a source capacitor having a positive terminal and a negative terminal. The first terminal of the source inductor may be coupled to the source terminal of the first transistor, the negative terminal of the first depletion capacitor, the source terminal of the second transistor and the negative terminal of the second depletion capacitor. The second terminal of the source inductor may be coupled to the positive terminal of the source capacitor. The negative terminal of the source capacitor may be coupled to the second voltage reference point.

In one embodiment, the amplifier may further include a first bias voltage input terminal adapted to provide a first bias voltage to the gate terminal of the first transistor.

In one embodiment, the first bias voltage input terminal may be provided between the negative terminal of the first gate capacitor and the positive terminal of the first depletion capacitor.

In one embodiment, the amplifier may further include a second bias voltage input terminal adapted to provide a second bias voltage to the gate terminal of the second transistor.

In one embodiment, the second bias voltage input terminal may be provided between the negative terminal of the second gate capacitor and the positive terminal of the second depletion capacitor.

In one embodiment, the first transistor may include an n-channel metal-oxide-semiconductor field-effect transistor.

In one embodiment, the second transistor may include a p-channel metal-oxide-semiconductor field-effect transistor.

In one embodiment, the second voltage reference point may be ground.

According to another embodiment, a transceiver including an amplifier as described above is provided.

According to yet another embodiment, an amplifier is provided. The amplifier includes an input terminal and an output terminal, wherein the input terminal and the output terminal are single-ended with equal phases for a signal; and a core configured to operate as a differential mode.

In one embodiment, the core may include a first transistor of a first conductivity and a second transistor of a second conductivity, each transistor comprising a source terminal, a gate terminal and a drain terminal respectively, the source terminal of the first transistor being coupled to the source terminal of the second transistor, and the gate terminal of the first transistor and the gate terminal of the second transistor being coupled to the input terminal.

In one embodiment, the first transistor may include an n-channel metal-oxide-semiconductor field-effect transistor.

In one embodiment, the second transistor may include a p-channel metal-oxide-semiconductor field-effect transistor.

DETAILED DESCRIPTION

Embodiments of an amplifier and a transceiver including the amplifier will be described in detail below with reference to the accompanying figures. It will be appreciated that the embodiments described below can be modified in various aspects without changing the essence of the invention.

FIG. 2shows a schematic diagram of one embodiment of an amplifier200. The amplifier200includes an input terminal202and an output terminal204. The input terminal202and the output terminal204are single-ended with equal phases for a signal. The amplifier200also includes a core206.

The core206includes a first transistor208of a first conductivity and a second transistor210of a second conductivity. In one embodiment, the first transistor208may be an n-channel metal-oxide-semiconductor field-effect transistor (NMOS), and the second transistor210may be a p-channel metal-oxide-semiconductor field-effect transistor (PMOS). The first transistor208has a source terminal212, a gate terminal214and a drain terminal216. The second transistor210has a source terminal218, a gate terminal220and a drain terminal222.

In one embodiment, the source terminal212of the first transistor208is coupled to the source terminal218of the second transistor210. The gate terminal214of the first transistor208and the gate terminal220of the second transistor210are coupled to the input terminal202. The drain terminal216of the first transistor208and the drain terminal222of the second transistor210may be coupled to various electrical components which are not shown for ease of illustration. Details of the coupling of the drain terminal216of the first transistor208and the drain terminal222of the second transistor210are shown inFIG. 3and are described in detail with respect toFIG. 3.

The core206is configured to operate as a differential mode. The core206may operate as a differential mode due to the complementary characteristic of the first transistor208and the second transistor210. Since the first transistor208is NMOS and the second transistor210is PMOS, the core206can operate between a high (e.g. positive) voltage and a low (e.g. negative) voltage. When a high (e.g. positive) voltage is applied at the input terminal202, the first transistor208is on (i.e. operating) and the second transistor210is off. When a low (e.g. negative voltage) is applied at the input terminal202, the first transistor208is off and the second transistor210is on (i.e. operating).

FIG. 3shows a schematic diagram of another embodiment of an amplifier300. The amplifier300includes an input terminal302, a first transistor304of a first conductivity and a second transistor306of a second conductivity. In one embodiment, the first transistor304may be an n-channel metal-oxide-semiconductor field-effect transistor (NMOS), and the second transistor306may be a p-channel metal-oxide-semiconductor field-effect transistor (PMOS).

The first transistor304includes a source terminal308, a gate terminal310and a drain terminal312. The second transistor306includes a source terminal314, a gate terminal316and a drain terminal318. In one embodiment, the source terminal308of the first transistor304is coupled to the source terminal314of the second transistor306. The gate terminal310of the first transistor304and the gate terminal316of the second transistor306are coupled to the input terminal302.

The amplifier300includes an output terminal320coupled to the drain terminal312of the first transistor304and the drain terminal318of the second transistor306. The amplifier300also includes a first depletion capacitor322coupled between the gate terminal310and the source terminal308of the first transistor304. The first depletion capacitor322has a positive terminal324and a negative terminal326. The positive terminal324of the first depletion capacitor322is coupled to the gate terminal310of the first transistor304and the negative terminal326of the first depletion capacitor322is coupled to the source terminal308of the first transistor304.

The amplifier300includes a second depletion capacitor328coupled between the gate terminal316and the source terminal314of the second transistor306. The second depletion capacitor328has a positive terminal330and a negative terminal332. The positive terminal330of the second depletion capacitor328is coupled to the gate terminal316of the second transistor306and the negative terminal332of the second depletion capacitor328is coupled to the source terminal314of the second transistor306.

The amplifier300includes a first resistor334coupled between the drain terminal312of the first transistor304and a first voltage reference point336. The first resistor334includes a first terminal338and a second terminal340. The first terminal338of the first resistor334is coupled to the drain terminal312of the first transistor304and the second terminal340of the first resistor334is coupled to the first voltage reference point336.

The amplifier300includes a second resistor342coupled between the drain terminal318of the second transistor306and a second voltage reference point344. The second resistor has a first terminal346and a second terminal348. The first terminal346of the second resistor342is coupled to the drain terminal318of the second transistor306and the second terminal348of the second resistor342is coupled to the second voltage reference point344. In one embodiment, the second voltage reference point344may be ground.

The amplifier300includes a first output capacitor350coupled between the drain terminal312of the first transistor308and the output terminal320. The first output capacitor350has a positive terminal352and a negative terminal354. The positive terminal352of the first output capacitor350is coupled to the drain terminal312of the first transistor304and the first terminal338of the first resistor334. The negative terminal354of the first output capacitor350is coupled to the output terminal320.

The amplifier300includes a second output capacitor356coupled between the drain terminal318of the second transistor306and the output terminal320. The second output capacitor356has a positive terminal358and a negative terminal360. The positive terminal358of the second output capacitor356is coupled to the drain terminal318of the second transistor306and the first terminal346of the second resistor342. The negative terminal360of the second output capacitor356is coupled to the output terminal320.

In other words, the negative terminal354of the first output capacitor350is coupled to the negative terminal360of the second output capacitor356. The output terminal320is coupled between the negative terminal354of the first output capacitor350and the negative terminal360of the second output capacitor356.

The amplifier300includes a gate inductor362having a first terminal364and a second terminal366, a first gate capacitor368having a positive terminal370and a negative terminal372, and a second gate capacitor374having a positive terminal376and a negative terminal378. The first terminal364of the gate inductor362is coupled to the input terminal302, and the second terminal366of the gate inductor362is coupled to the positive terminal370of the first gate capacitor368and the positive terminal376of the second gate capacitor374. The negative terminal372of the first gate capacitor368is coupled to the gate terminal310of the first transistor304and the positive terminal324of the first depletion capacitor322. The negative terminal378of the second gate capacitor374is coupled to the gate terminal316of the second transistor306and the positive terminal330of the second depletion capacitor328.

The amplifier300also includes a source inductor380having a first terminal382and a second terminal384, and a source capacitor386having a positive terminal388and a negative terminal390. The first terminal382of the source inductor380is coupled to the source terminal308of the first transistor304, the negative terminal326of the first depletion capacitor322, the source terminal314of the second transistor306and the negative terminal332of the second depletion capacitor328. The second terminal384of the source inductor380is coupled to the positive terminal388of the source capacitor386. The negative terminal390of the source capacitor386is coupled to the second voltage reference point344.

The amplifier300includes a first bias voltage input terminal392adapted to provide a first bias voltage to the gate terminal310of the first transistor304. The first bias voltage input terminal392is provided between the negative terminal372of the first gate capacitor368and the positive terminal324of the first depletion capacitor322. The amplifier300also includes a second bias voltage input terminal394adapted to provide a second bias voltage to the gate terminal316of the second transistor306. The second bias voltage input terminal394is provided between the negative terminal378of the second gate capacitor374and the positive terminal330of the second depletion capacitor328.

In one embodiment, the amplifier300may include an n-channel metal-oxide-semiconductor field-effect transistor (NMOS) and a p-channel metal-oxide-semiconductor field-effect transistor (PMOS). The NMOS and the PMOS may be coupled such that the respective source terminals are coupled together. Thus, the amplifier300may have a common source topology. The respective gate terminals of the NMOS and the PMOS may be coupled together. An input terminal may be coupled between the gate terminals of the NMOS and the PMOS. The respective drain terminals of the NMOS and the PMOS may be coupled together. An output terminal may be coupled between the drain terminals of the NMOS and the PMOS. In other words, the amplifier300may provide a single input and a single output. The arrangement of the NMOS and the PMOS may provide a complementary metal-oxide-semiconductor field-effect transistor (CMOS). With this arrangement, the NMOS and the PMOS may be on (i.e. operating) depending on the input. When the input is high, the NMOS is on and the PMOS is off. When the input is low, the NMOS is off and the PMOS is on.

In one embodiment, the amplifier300may be formed by combining a first circuit arrangement400and a second circuit arrangement450as shown inFIG. 4. The first circuit arrangement400includes an input terminal401and an output terminal402. The first circuit arrangement400includes a transistor403of a first conductivity having a source terminal404, a gate terminal405and a drain terminal406, a depletion capacitor407having a positive terminal408and a negative terminal409, a resistor410having a first terminal411and a second terminal412, an output capacitor413having a positive terminal414and a negative terminal415, a gate inductor416having a first terminal417and a second terminal418, a gate capacitor419having a positive terminal420and a negative terminal421, and a source inductor422having a first terminal423and a second terminal424. In one embodiment, the transistor403may be an n-channel metal-oxide-semiconductor field-effect transistor (NMOS). The first circuit arrangement400also includes a bias voltage input terminal425.

The source terminal404of the transistor403is coupled to the negative terminal408of the depletion capacitor407and the first terminal423of the source inductor422. The gate terminal405of the transistor403is coupled to the positive terminal409of the depletion capacitor407and the negative terminal421of the gate capacitor419. The drain terminal406of the transistor403is coupled to the first terminal411of the resistor410and the positive terminal414of the output capacitor413.

The positive terminal420of the gate capacitor419is coupled to the second terminal418of the gate inductor416. The first terminal417of the gate inductor416is coupled to the input terminal401. The negative terminal415of the output capacitor413is coupled to the output terminal402. The second terminal412of the resistor410is coupled to a first voltage reference point426. The second terminal424of the source inductor422is coupled to a second voltage reference point427. In one embodiment, the second voltage reference point427may be ground. The bias voltage input terminal425is coupled between the negative terminal421of the gate capacitor419and the positive terminal409of the depletion capacitor407. The bias voltage input terminal425may be adapted to provide a bias voltage to the gate terminal405of the transistor403.

The second circuit arrangement450includes an input terminal451and an output terminal452. The second circuit arrangement450includes a transistor453of a second conductivity having a source terminal454, a gate terminal455and a drain terminal456, a depletion capacitor457having a positive terminal458and a negative terminal459, a resistor460having a first terminal461and a second terminal462, an output capacitor463having a positive terminal464and a negative terminal462, a gate inductor466having a first terminal467and a second terminal468, a gate capacitor469having a positive terminal470and a negative terminal471, and a source inductor472having a first terminal473and a second terminal474. In one embodiment, the transistor453may be a p-channel metal-oxide-semiconductor field-effect transistor (PMOS). The second circuit arrangement450also includes a bias voltage input terminal475.

The source terminal454of the transistor453is coupled to the negative terminal459of the depletion capacitor457and the second terminal474of the source inductor472. The gate terminal455of the transistor453is coupled to the positive terminal458of the depletion capacitor457and the negative terminal471of the gate capacitor469. The drain terminal456of the transistor453is coupled to the first terminal461of the resistor460and the positive terminal464of the output capacitor463.

The positive terminal470of the gate capacitor469is coupled to the second terminal468of the gate inductor466. The first terminal467of the gate inductor466is coupled to the input terminal451. The negative terminal462of the output capacitor463is coupled to the output terminal452. The first terminal473of the source inductor472is coupled to a third voltage reference point476. The second terminal462of the resistor460is coupled to a fourth voltage reference point477. In one embodiment, the fourth voltage reference point477may be ground. The bias voltage input terminal475is coupled between the negative terminal471of the gate capacitor469and the positive terminal458of the depletion capacitor457. The bias voltage input terminal475may be adapted to provide a bias voltage to the gate terminal455of the transistor453.

The first circuit arrangement400and the second circuit arrangement450may be combined to form the amplifier300by stacking the transistor403of the first circuit arrangement400on top of the transistor453of the second circuit arrangement450.

In one embodiment, the amplifier300may be a complementary current-reuse amplifier. The amplifier300may have a complementary current-reuse common-source (CS) topology where a NMOS CS amplifier (e.g. first transistor304) is stacked on top of a PMOS CS amplifier (e.g. second transistor306) to reuse the direct current (DC) among the two symmetrically stacked amplifiers. In short, the DC current can flow through both the NMOS CS amplifier (e.g. first transistor304) and the PMOS CS amplifier (e.g. second transistor306), i.e. through the drain terminal312of the first transistor304and the drain terminal318of the second transistor306. The advantage of having this configuration in comparison to a conventional current-reuse topology is that no DC feedback circuitry is required to define the operating point of high impedance output node. No additional circuit or complexity is required. Less number of passive components is required for input matching. The common-source (CS) topology can provide improved noise and linearity performance.

Since only a small amount of DC current flows through the drain terminals312,318of the transistors304,306, a small voltage drop occurs in both load resistors RL(e.g. first and second resistors334,342) and 1-V supply voltage can still be used without headroom issues. In other words, a low voltage and ultra-low power design can be used for the amplifier300. No additional power is required for the common-source (CS) topology of the amplifier300. Both the first transistor Mn1304and the second transistor Mp1306are biased so that the gate-to-source voltage VGSis close to the threshold voltage Vth. The transistors304,306are sized so that the voltage at node A is biased at VDD/2 (supply voltage/2) to provide symmetric characteristics between the two stacked amplifiers. Node A is alternating current (ac) ground at 400 MHz due to the large bypass capacitor Cs(e.g. source capacitor386). The large bypass capacitor Cs(e.g. source capacitor386) is included for ac ground and stability. The source degeneration on-chip spiral inductor Ls(e.g. source inductor380) is used for input impedance matching along with the depletion capacitors Cd322,328and the gate inductor Lg362. Since both the transconductance gmand gate-to-source capacitance Cgsare increased in comparison to the SDCLNA102ofFIG. 1at the same power consumption, the size of both the depletion capacitors Cd322,328and the source inductor Ls380can be reduced, resulting in a smaller die area. The ac-coupled gate terminals310,316and drain terminals312,318of the first transistor Mn1304and the second transistor Mp1306are connected together, respectively, which results in both the input and output of the resulting amplifier300being single-ended with equal phases for the signal. The amplifier300operates as a differential mode due to the complementary characteristic of NMOS (e.g. the first transistor304) and PMOS (e.g. the second transistor306). This may result in a single-ended input-output differential amplifier300.

Since the amplifier300effectively operates as a differential amplifier, the even-order distortion can be eliminated.FIG. 5shows a graph500of measured drain current iDS, transconductance gm, and first derivative of transconductance gm′ of a 120-μm/0.18-μm NMOS and a 240-μm/0.18-μm PMOS FET (see reference [1] I. Nam, B. Kim, and K. Lee, “CMOS RF amplifier and mixer circuits utilizing complementary characteristics of parallel combined NMOS and PMOS devices,”IEEE Trans. Microw. Theory and Tech., vol. 53, no. 5, pp. 1662-1671, May 2005). Plot502shows the measured total drain current iDSplotted against a gate-to-source voltage Vgs. Plot504shows the transconductance gmplotted against the gate-to-source voltage Vgs. Plot506shows the first derivative of transconductance gmplotted against the gate-to-source voltage Vgs. Plot506shows that gm′ of NMOS and gm′ of PMOS have opposite signs.

A small signal drain current idsof a common source metal-oxide semiconductor field effect transistor (e.g. the first transistor304and the second transistor306) can be expressed:

From the above equation, it can be understood by a skilled person that gm′ causes second-order nonlinearity of the drain current. Since gm′ of NMOS (e.g. the first transistor304) and gm′ of PMOS (e.g. the second transistor306) have opposite signs, combining them can suppress the second-order nonlinearity of the drain current. A slight improvement in third-order nonlinearity can be obtained due to cancelling effect of gm′. In other words, an improvement in the second order input intercept point IIP2performance can lead to a slight enhancement in the third order input intercept point IIP3.

FIG. 6shows a schematic diagram of an AC (alternating current) equivalent circuit600of the amplifier300. Vsig—inrepresents an input voltage of the circuit600, isig—nrepresents a current passing through the first transistor304, isig—prepresents a current passing through the second transistor306, and Voutrepresents an output voltage of the circuit600.

An external high inductance gate inductor Lg362may be employed for 50Ω impedance matching and passive amplification. The input matching circuit amplifies the input voltage and noise from the antenna with the effective inductance of the input matching circuit. The input matching circuit may include the gate inductor Lg362, the depletion capacitor Cdn322, the depletion capacitor Cdp328, and the source inductor Ls380.

If the inductance is large enough, the output noise of the amplifier300will be dominated by the amplified input noise. The signal-to-noise ratio is not much degraded due to the input referred noise of the amplifier300, and the resulting noise figure (NF) can be further improved.

FIG. 7ashows a schematic diagram of high impedance passive amplification circuit800. The circuit800has an antenna802and an amplifier804. The antenna802has an inductor806and a resistor808connected in series. The antenna802also has a capacitor810connected in parallel with a series connection812of the inductor806and the resistor808. The amplifier804may be a low noise amplifier. In one embodiment, the amplifier804may correspond to the amplifier200or the amplifier300as described above.

FIG. 7bshows a schematic diagram of an equivalent circuit814of the circuit800ofFIG. 7a. The equivalent circuit814includes the inductor806, the resistor808and a voltage source816connected in series. The equivalent circuit814also includes the capacitor810connected in parallel with a series connection818of the inductor806, the resistor808and the voltage source818. The equivalent circuit814includes a further capacitor820connected in parallel with the capacitor810, and a further resistor821connected in parallel with the further capacitor820. The equivalent circuit814is divided into a first portion822and a second portion824by a dotted line826. The first portion822of the equivalent circuit814includes the inductor806, the resistor808, the voltage source818and the capacitor810. The second portion824of the equivalent circuit814includes further capacitor820and the further resistor821. A source impedance ZScan be calculated based on the first portion822of the equivalent circuit814. A load impedance ZLcan be calculated based on the second portion824of the equivalent circuit814. In other words, the source impedance ZSshown inFIG. 7bmay be calculated based on the impedance of the antenna802shown inFIG. 7a. The load impedance ZLshown inFIG. 7amay be calculated based on the impedance of the amplifier804shown inFIG. 7b.

FIG. 7cshows a schematic diagram of an equivalent circuit828of the circuit800for noise calculation. The equivalent circuit828includes the inductor806, the resistor808and a voltage source816connected in series. The equivalent circuit828includes the capacitor810connected in parallel with a series connection818of the inductor806, the resistor808and the voltage source818, forming a parallel arrangement830. The equivalent circuit828also includes the amplifier804. One end832of the parallel arrangement830is coupled to an input terminal834of the amplifier804. The other end836of the parallel arrangement830is coupled to ground838.

The voltage gain of the amplifier804can be calculated using the following equation:

AV=Qi⁢⁢n·gm·RLoad·ZLZS+ZL
where AVis voltage gain of the amplifier804, Qinis an input charge (e.g. charge of capacitor810), gmis transconductance, RLoadis load resistance (e.g. resistance of resistor808), ZLis load impedance, and ZSis source impedance.

The noise figure (NF) can be calculated using the following equation:

N⁢⁢F=10⁢⁢log⁡(Vn2+VLNA_inputrefer2Vn2)=10⁢⁢log⁡(Av2⁢Qi⁢⁢n2⁢Vn2+VLNA_outputrefer2Av2⁢Qi⁢⁢n2⁢Vn2)(1)
where NF is noise figure, Vnis voltage of the voltage source816, VLNA—inputreferis a reference input voltage of the amplifier804, AVis voltage gain, Qinis a quality factor of the input matching circuit, and VLNA—outputreferis a reference input voltage of the amplifier804.
Referring to equation (1), if Av2Qin2Vn2>>VLNA2, the output noise is dominated by the input noise and the noise figure can be effectively reduced significantly.

The maximum passive amplification can be applied to the amplifier300for non-50Ω impedance matching applications. Additional gain, improved NF and further reduction in power can be achieved by using the maximum passive amplification.

The amplifier300and the conventional SDCLNA100are simulated at about 1.0 V, about 27° C. and with 50Ω impedance matching.FIG. 8shows a graph900of s-parameter plotted against frequency. Plot902shows insertion loss (S21) of the conventional SDCLNA100plotted against frequency. Plot904shows input return loss (S11) of the conventional SDCLNA100plotted against frequency. Plot906shows insertion loss (S21) of the amplifier300plotted against frequency. Plot908shows input return loss (S11) of the amplifier300plotted against frequency. It can be observed from graph900that the s-parameters of the conventional SDCLNA100and the amplifier300are similar.

FIG. 9shows a graph1000of noise figure (NF) plotted against frequency. Plot1002shows the NF of the conventional SDCLNA100plotted against frequency. Plot1004shows the minimum NF of the conventional SDCLNA100plotted against frequency. Plot1006shows the NF of the amplifier300plotted against frequency. Plot1008shows the minimum NF of the amplifier300plotted against frequency. The NF of the conventional SDCLNA100is about 2.6 dB. The NF of the amplifier300is about 1.8 dB. In comparison to the conventional SDCLNA100, the NF of the amplifier300is improved at the same power consumption. The NF of the amplifier300may be improved due to the increased transconductance of the current reuse structure of the amplifier300.

FIG. 10ashows the simulated third order input intercept point IIP3of the conventional SDCLNA100. The IIP3of the conventional SDCLNA100is about −10.7 dBm.FIG. 10bshows the shows the simulated third order input intercept point IIP3of the amplifier300. The IIP3of the amplifier300is about −6.5 dBm. It can be observed that in comparison to the conventional SDCLNA100, the IIP3of the amplifier300is improved.

FIG. 11shows a table1200listing the simulation results of the conventional SDCLNA100and the amplifier300. Column1202shows the targeted simulation results. Column1204shows the simulation results of the conventional SDCLNA100. Column1206shows the simulation results of the amplifier300. The amplifier300shows better performance than the conventional SDCLNA100.

FIG. 12shows a graph1300illustrating experimental results of the amplifier300at 50Ω impedance matching and at a frequency range of 401 MHz to 406 MHz. Plot1302shows the insertion loss (S21) of the amplifier300plotted against frequency. Plot1304shows the input return loss (S11) of the amplifier300plotted against frequency. Plot1306shows the noise figure (NF) of the amplifier300plotted against frequency. The NF of the amplifier300with 50Ω matching is about 2.9 dB.

FIG. 13shows a graph1400illustrating third order input intercept point (IIP3) linearity measurements of the amplifier300. Plot1402shows output power plotted against input power for a fundamental signal. Plot1404shows output power plotted against input power for a third-order product of the fundamental signal. A fitted line1406for plot1402is drawn and a fitted line1408for plot1404is drawn. It can be observed from an intersection point1410of line1406and line1408that a −8.1 dBm of IIP3is measured for the amplifier300.

FIG. 14shows a table1500listing simulation results of four conventional amplifiers (see references [2] “A 1V wireless transceiver for an ultra-low-power SoC for biotelemetry applications,” JSSC2008, [3] “A 1V wireless transceiver for an ultra-low-power SoC for biotelemetry applications,” JSSC2008, [4] “A subthreshold low-noise amplifier optimized for ultra-low-power applications in the ISM band,” TMTT2008, and [5] “A novel ultra-low power (ULP) low noise amplifier using differential inductor feedback” ESSCIRC2006), preliminary measurements of the amplifier300with 50Ω impedance matching, and simulation results of the amplifier300with high impedance matching (non-50Ω matching). Columns1502to1508show the simulation results of the four conventional amplifiers respectively. Column1510shows the preliminary measurements of the amplifier300with 50Ω impedance matching. Column1512shows the simulation results of the amplifier300with high impedance matching (non-50Ω matching).

With 50Ω impedance matching, the amplifier300has a gain of 20.2 dB, a noise figure of 2.9 dB, an IIP3of −8.1 dBm, a power consumption of 150 μW at 1-V and a figure of merit (F.O.M.) of 20. With high impedance matching, the amplifier300has a gain of 22 dB, a noise figure of 1.5 dB, an IIP3of −13 dBm, a power consumption of 100 μW at 1-V and a figure of merit (F.O.M.) of 22.6. In comparison with the four conventional amplifiers, the amplifier300exhibits an improved performance with 50Ω impedance matching and with high impedance matching.

FIG. 15shows a graph1600illustrating the simulation results of the amplifier300with high impedance passive network (non-50Ω matching). Plot1602shows the insertion loss (S21) of the amplifier300plotted against frequency. Plot1604shows the input return loss (S11) of the amplifier300plotted against frequency. Plot1606shows the noise figure (NF) of the amplifier300plotted against frequency. The NF of the amplifier300with non-50Ω matching is about 1.6 dB which is improved as compared to the NF of the amplifier300with 50Ω matching (e.g. 1.8 dB (seeFIG. 9) and 2.9 dB (seeFIG. 14)).

Simulation of the noise figure (NF) of the amplifier300at high impedance (non-50Ω matching) can be carried out using various methods. One possible method is the noise voltage method. Referring to the above-mentioned equation (1), Vn2+VLNA—inputreferand Av2Qin2Vn2+VLNA—outputrefercan be simulated. The NF of the amplifier300obtained from the noise voltage method is 1.617 dB. Another possible method is the S-parameter method where serial network is transformed to parallel network and conventional S-parameter simulation is used. The NF of the amplifier300obtained from the S-parameter method is 1.566 dB.

The amplifier300has a current reuse topology and requires no additional power or complexity required. Improvement of noise and linearity performance can be achieved without increase in power consumption. Power consumption can be reduced by more than 50%. Application of maximum passive amplification to the amplifier300to further reduce the power consumption for applications where 50Ω input matching may not be required. Nevertheless, high impedance matching can still result in further reduction in power consumption of the amplifier300. Smaller passive components can be used in the amplifier300for higher integration.

The amplifier300can be employed for receiver radio frequency (RF) front-ends as a low-noise amplifier in different applications (e.g. ultra-low-power implantable and wearable wireless sensors for biomedical applications). For example, the amplifier300can be applied to a full transceiver for MedRadio regulation compliant implant and wearable sensor applications where sufficient gain and noise performances are required and ultra-low-power consumption for prolonged battery life is provided. The amplifier300can be used in a low-voltage sub-mW transceiver for biomedical applications where the amplifier300is a key building block in the receiver part.

FIG. 16shows a block diagram of a receiver RF front-end1800. The receiver RF front-end1800includes an amplifier1802(e.g. low noise amplifier (LNA)). The amplifier1802may correspond to the amplifier300described above. The receiver RF front-end1800also includes a transconductor1804, an in-phase/quadrature (I/Q) folded active mixer1806, a first intermediate frequency (IF) buffer1808aand a second IF buffer1808b, and a two-stage passive polyphase filter (PPF)1810with a first buffer1812aand a second buffer1812b. The receiver RF front-end1800has an antenna1814.

The antenna1814is coupled to an input terminal1816of the amplifier1802. An output terminal1818of the amplifier1802is coupled to an input terminal1820of the transconductor1804. An output terminal1822of the transconductor1804is coupled to a first input terminal1824and a second input terminal1826of the I/Q folded mixer1806. A first output terminal1828and a second output terminal1830of the I/Q folded mixer1806are coupled to a first input terminal1832and a second input terminal1834of the first IF buffer1808arespectively. A third output terminal1836and a fourth output terminal1838of the I/Q folded mixer1806are coupled to a first input terminal1840and a second input terminal1842of the second IF buffer1808brespectively. The first IF buffer1808ahas a first output terminal1844and a second output terminal1846for transmitting in-phase signals. The second IF buffer1808bhas a first output terminal1848and a second output terminal1850for transmitting quadrature signals. The PPF1810has a first input terminal1852and a second input terminal1854for receiving I/Q local oscillator (LO) signal from an external LO source (not shown). A first output terminal1856and a second output terminal1858of the PPF1810are coupled to a first input terminal1860and a second input terminal1862of the first buffer1812arespectively. A third output terminal1864and a fourth output terminal1866of the PPF1810are coupled to a first input terminal1868and a second input terminal1870of the second buffer1812brespectively. A first output terminal1872and a second output terminal1874of the first buffer1812aare coupled to a third input terminal1876and a fourth input terminal1878of the I/Q folded mixer1806respectively. A first output terminal1880and a second output terminal1882of the second buffer1812bare coupled to a fifth input terminal1884and a sixth input terminal1886of the I/Q folded mixer1806respectively.

The two-stage passive polyphase filter1810with a first buffer1812aand a second buffer1812bare used to drive the mixer1806for I/Q LO signal generation from the external LO source (not shown). The two poles 1/R1C1and 1/R2C2are placed at 395 and 410 MHz, respectively, to broaden the frequency response. Considering low power consumption, the LO buffer (e.g. including first buffer1812aand second buffer1812b) may be an ac-coupled inverter type differential amplifier where a large differential swing can be obtained for a given operating current due to its push-pull operation.

In addition, a constant-gm bias circuitry may be included to supply accurate reference current to all the blocks (e.g. amplifier1802, transconductor1804, I/Q folded active mixer1806, first IF buffer1808a, second IF buffer1808b, PPF1810with first buffer1812aand second buffer1812b) of the receiver RF front-end1800regardless of process, voltage, and temperature (PVT) variations. Single-ended paths are employed up to the mixer1806to minimize the current consumption and to avoid the use of a lossy balun at the receiver input. To minimize power in each of the blocks, low-power design techniques such as current-reuse and weak inversion biasing are utilized with a 1-V supply voltage through the receiver chain (e.g. receiver RF front-end1800).

The antenna1814of the receiver RF front-end1800has a RF input band of 401-406 MHz. However, the narrow 100 kHz channel bandwidth of the 401-402 MHz and 405-406 MHz wing bands in MedRadio may severely be corrupted by the flicker noise and DC offset at baseband. Therefore, the RF input band of 401-406 MHz is downconverted to a low-IF of 50Ω kHz. The 50Ω kHz IF is selected as a compromise in order to avoid the 1/f noise and at the same time minimize the required power consumption of the IF blocks (e.g. first IF buffer1808aand second IF buffer1808b).

The mixer1806is used to alleviate the headroom issue and have separate biasing for the transconductor1804and the switching part of the mixer1806for better optimization.FIG. 17shows a schematic diagram of the folded active mixer1806. The mixer1806has seven p-channel MOSFET (PMOS)1902a-g, one n-channel MOSFET (NMOS)1904, ten resistors1906aj, eleven capacitors1908a-kand one current source1910. A source terminal1912of the first PMOS1902a, a source terminal1913of the second PMOS1902band a source terminal1914of the seventh PMOS1902gare coupled to a first voltage reference point1915. A gate terminal1916of the first PMOS1902ais coupled to a negative terminal1917of the first capacitor1908a. A positive terminal1918of the first capacitor1908ais coupled to a first terminal1919of the first resistor1906aand a gate terminal1920of the NMOS1904. A drain terminal1921of the first PMOS1902ais coupled to a second terminal1922of the first resistor1906a, a drain terminal1923of the NMOS1904, and a positive terminal1924of the second capacitor1908b. A source terminal1925of the NMOS1904is coupled to ground1901. The mixer1806has a first input terminal1926coupled to the positive terminal1918of the first capacitor1908a, the first terminal1919of the first resistor1906aand the gate terminal1920of the NMOS1904. The mixer1806also has a bias voltage input terminal1927coupled between the gate terminal1916of the first PMOS1902aand the negative terminal1917of the first capacitor1908a.

The gate terminal1928of the second PMOS1902bis coupled to a first terminal1929of the second resistor1906b. A second terminal1930of the second resistor1906bis coupled to a gate terminal1931of the seventh PMOS1902g, a positive terminal1932of the third capacitor1908c, a first terminal1933of the current source1910and a drain terminal1934of the seventh PMOS1902g. The negative terminal1935of the third capacitor1908cand the second terminal1936of the current source1910are respectively coupled to ground1901. The drain terminal1937of the second PMOS1902bis coupled to a negative terminal1938of the second capacitor1908b, a source terminal1940of the third PMOS1902c, a source terminal1941of the fourth PMOS1902d, a source terminal1942of the fifth PMOS1902e, and a source terminal1943of the sixth PMOS1902f.

A gate terminal1944of the third PMOS1902cis coupled to a negative terminal1945of the fourth capacitor1908dand a first terminal1946of the third resistor1906c. A gate terminal1947of the fourth PMOS1902dis coupled to a negative terminal1948of the fifth capacitor1908eand a first terminal1949of the fourth resistor1906d. A second terminal1950of the third resistor1906cis coupled to a second terminal1951of the fourth resistor1906d. A drain terminal1952of the third PMOS1902cis coupled to a positive terminal1953of the sixth capacitor1908fand a first terminal1954of the fifth resistor1906e. A negative terminal1955of the sixth capacitor1908fis coupled to a second terminal1956of the fifth resistor1906e. The negative terminal1955of the sixth capacitor1908fand second terminal1956of the fifth resistor1906eare coupled to ground1901. A drain terminal1957of the fourth PMOS1902dis coupled to a positive terminal1958of the seventh capacitor1908gand a first terminal1959of the sixth resistor1906f. A negative terminal1960of the seventh capacitor1908gis coupled to a second terminal1961of the sixth resistor1906f. The negative terminal1960of the seventh capacitor1908gand the second terminal1961of the sixth resistor1906fare coupled to ground1901.

The mixer1806includes a second input terminal1962coupled to a positive terminal1963of the fourth capacitor1908d, and a third input terminal1964coupled to a positive terminal1965of the fifth capacitor1908e. The mixer1806includes a first output terminal1966coupled between the drain terminal1952of the third PMOS1902cand a coupling point1967. The mixer1806includes a second output terminal1968coupled between the drain terminal1957of the fourth PMOS1902dand a coupling point1969. A bias voltage Vbis applied between the second terminal1950of the third resistor1906cand the second terminal1951of the fourth resistor1906d.

A gate terminal1970of the fifth PMOS1902eis coupled to a negative terminal1971of the eighth capacitor1908hand a first terminal1972of the seventh resistor1906g. A gate terminal1973of the sixth PMOS1902fis coupled to a negative terminal1974of the ninth capacitor1908iand a first terminal1975of the eighth resistor1906h. A second terminal1976of the seventh resistor1906gis coupled to a second terminal1977of the eighth resistor1906h. A drain terminal1978of the fifth PMOS1902eis coupled to a positive terminal1979of the tenth capacitor1908jand a first terminal1980of the ninth resistor1906i. A negative terminal1981of the tenth capacitor1908jis coupled to a second terminal1982of the ninth resistor1906i. The negative terminal1981of the tenth capacitor1908jand the second terminal1982of the ninth resistor1906iare coupled to ground1901. A drain terminal1983of the sixth PMOS1902fis coupled to a positive terminal1984of the eleventh capacitor1908kand a first terminal1985of the tenth resistor1906j. A negative terminal1986of the eleventh capacitor1908kis coupled to a second terminal1987of the tenth resistor1906j. The negative terminal1986of the eleventh capacitor1908kand the second terminal1987of the tenth resistor1906jare coupled to ground1901.

The mixer1806includes a fourth input terminal1988coupled to a positive terminal1989of the eighth capacitor1908h, and a fifth input terminal1990coupled to a positive terminal1991of the ninth capacitor1908i. The mixer1806includes a third output terminal1992coupled between the drain terminal1978of the fifth PMOS1902eand a coupling point1993. The mixer1806includes a fourth output terminal1994coupled between the drain terminal1983of the sixth PMOS1902fand a coupling point1995. A bias voltage Vbis applied between the second terminal1976of the seventh resistor1906gand the second terminal1977of the eighth resistor1906h.

Referring back toFIG. 16, the transconductor1804is an ac-coupled current reuse inverter type where the biasing for the transistor Mp1(e.g. first PMOS1902a) and transistor Mn1(e.g. NMOS1904) are separated in order to support low supply voltage and reduce its sensitivity to PVT variations. A single tail current source Mp2(e.g. second PMOS1902b) is used in the I/Q mixer1806in order to minimize mismatch between the two mixer paths. The mixer1806is a single-balanced active mixer with parallel RC load for low-pass filtering in the baseband.

The receiver RF front-end1800can be fabricated in one-poly six-metal (1P 6M) 0.18-μm CMOS process. The chip microphotograph2000of the receiver RF front-end1800is shown inFIG. 18. The total chip area of the core2002(e.g. including the amplifier1802, the I/Q mixer1806, the first IF buffer1808a, the second IF buffer1808b, the PPF1810with the first buffer1812aand the second buffer1812b) is 0.7 mm2. All pads include electrostatic discharge (ESD) circuits using diode pairs.

FIG. 19shows a graph2100of measured conversion gain and input return loss (S11) of the receiver front-end plotted against RF input frequency at an intermediate frequency (IF) of 50Ω kHz. The external LO signal is provided by a signal generator. Plot2102shows measured conversion gain plotted RF input frequency at an IF of 50Ω kHz. Plot2104shows input return loss (S11) plotted against RF input frequency at an IF of 50Ω kHz. It can be observed from plot2102that there is a conversion gain of 28.7 dB.

FIG. 20shows a graph2200of noise figure (NF) measurement plotted against output frequency of the receiver front-end. It can be observed from the graph2200that less than 5.5 dB of double-sideband (DSB) NF is obtained at an IF of 50Ω kHz to 2 MHz and at 28.7 dB of conversion gain.

FIG. 21shows a graph2300of third order input intercept point (IIP3) linearity measurement where two-tones at 402 and 402.1 MHz are applied to the input of the receiver. Plot2302shows output power plotted against input power for a fundamental signal. Plot2304shows output power plotted against input power for a third-order product of the fundamental signal. A fitted line2306for plot2302is drawn and a fitted line2308for plot2304is drawn. It can be observed from an intersection point2310of line2306and line2308that a −25 dBm of IIP3is measured for the RF receiver front-end.

In one embodiment, the receiver RF front-end1800may be a low-voltage ultra-low-power 401-406 MHz MedRadio receiver RF front-end targeted for wearable sensor applications. The receiver RF front-end1800may be an ultra-low-power 401-406 MHz Medical Device Radiocommunication Service (MedRadio) receiver RF front-end for biomedical telemetry applications implemented using 0.18-μm CMOS technology with a 1-V supply voltage. The receiver RF front-end1800employs the amplifier300(e.g. complementary current-reuse low-noise amplifier (CCRLNA)) which shows enhanced noise and linearity performance in comparison to the well-known source degeneration cascode LNA (SDCLNA)100at equal power consumption and design conditions. The receiver RF front-end1500including the amplifier1802(e.g. amplifier/CCRLNA300), transconductor1804, I/Q folded mixer1806, and LO buffers1812a,1812bcan achieve a conversion gain of 28.7 dB, NF of 5.5 dB, and IIP3of −25 dBm while consuming less than 500 μW (e.g. 490 μW) from a 1-V supply voltage and occupy 0.7 mm2of core die area. The receiver RF front-end1800exhibits enhanced noise and linearity performance.