RECONSTITUTED INTERPOSER SEMICONDUCTOR PACKAGE

A reconstituted semiconductor package and a method of making a reconstituted semiconductor package are described. An array of die-attach substrates is formed onto a carrier. A semiconductor device is mounted onto a first surface of each of the die-attach substrates. An interposer substrate is mounted over each of the semiconductor devices. The interposer substrates are electrically connected to the first surface of the respective die-attach substrates. A molding compound is filled in open spaces within and between the interposer substrates mounted to their respective die-attach substrates to form an array of reconstituted semiconductor packages. Electrical connections are mounted to a second surface of the die-attach substrates. The array of reconstituted semiconductor packages is singulated through the molding compound between each of the die-attach substrates and respective mounted interposer substrates.

BACKGROUND

A semiconductor package can be a metal, plastic, glass, or ceramic casing containing one or more semiconductor electronic components, also referred to as dies or integrated circuits (ICs). The package provides protection against impact and corrosion, as well as environmental factors, such as moisture, oxidation, heat, and contaminants. Electrical contacts or leads emminate from the package and are connected to other devices and/or to an intermediary substrate, or directly to a circuit board. The package may have as few as two leads or contacts for devices such as diodes, or have several hundred leads or contacts in the case of a microprocessor.

The semiconductor package can be a special purpose self-contained device, which can be mounted to a printed circuit board (PCB) or a printed wiring board (PWB) of an end product. ICs can be connected to a substrate in a variety of layouts, as well as stacked in multiple layers. In addition, packages can be mounted upon other packages to form a package-on-package device.

User products are becoming more complicated with several features and functions. In addition, many user products are becoming smaller, especially wireless devices. As a result, manufacturers are utilizing packaging alternatives as a way of achieving more features and functions in a smaller area.

SUMMARY

Embodiments include a reconstituted semiconductor package, which has an array of individual die-attach substrates on a carrier. The package also has a plurality of semiconductor devices, each mounted and electrically connected to a first surface of an associated die-attach substrate. The package also has a plurality of individual interposer substrates, each mounted over an associated semiconductor device and electrically connected to the first surface of the associated die-attach substrate. The package also has an encapsulation (for example, a molding compound) filled within open spaces between and around each of the interposer substrates mounted to its associated die-attach substrate to form a plurality of reconstituted semiconductor packages. The package has electrical connections mounted to a second surface of each of the die-attach substrates. Singulation of each of the reconstituted semiconductor packages cuts through the molding compound and between each of the die-attach substrates and respective mounted interposer substrates.

Embodiments also include a method of forming a semiconductor package. The method includes forming an array of die-attach substrates onto a carrier, and mounting a semiconductor device onto a first surface of each of the die-attach substrates. The method also includes forming solder ball or conductive post connections to a plurality of interposer substrates, mounting each interposer substrate over a respective semiconductor device, and electrically connecting the interposer substrates to the first surface of the respective die-attach substrates, via the solder ball or conductive post connections. The method also includes filling a molding compound in open spaces within and between the interposer substrates mounted to their respective die-attach substrates to form an array of reconstituted semiconductor packages. The method also includes mounting electrical connections to a second surface of the die-attach substrates, and singulating the array of reconstituted semiconductor packages through the molding compound between each of the die-attach substrates and respective mounted interposer substrates.

Embodiments also include a reconstituted interposer package. The reconstituted interposer package has an interposer substrate electrically mounted to a first surface of a reconstituted die-attach substrate and straddling over an integrated circuit mounted on the first surface of the reconstituted die-attach substrate. The interposer package also has a molding compound filled within open spaces between the interposer substrate and the first surface of the reconstituted die-attach substrate. Singulated surfaces of the molding compound also reside along edges of the interposer substrate mounted to the reconstituted die-attach substrate. The reconstituted interposer package has external electrical connections formed in a grid array on a second surface of the reconstituted die-attach substrate.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Multiple ICs can be assembled on a substrate and be interconnected with wire bonds and/or a metal pattern to form a package. An example of a multi-chip IC package is an application microprocessor, which may include separate ICs for such things as memory within the same package.

ICs can be manufactured in wafer level form, in which 10s, 100s, or 1000s of ICs are formed within a single semiconductor wafer. The wafer material may be silicon, gallium arsenide, or other semiconducting material.FIG. 1Aillustrates a wafer100containing multiple ICs110. The ICs110can be square or rectangular in shape, as well as other shapes suited to a particular manufacturing process. The ICs110are separated from one another in a singulation process, which can be implemented by scribing the boundaries between the individual ICs110, then sawing, breaking, or cutting the ICs110apart.

FIG. 1Billustrates a cross sectional area of an IC110. The IC110has an inactive surface120and an active surface130. The active surface130has a plurality of electrically conductive contact regions or contact pads140, which are designed to interconnect the IC110with other devices or substrates. An IC contact pad can have multiple layers, referred to as under-bump metallization (UBM). The base conductive layer may contain aluminum.

Since solder material does not adhere well to aluminum, another metallic or conductive layer can be patterned over the aluminum pad. An example UBM may include a combination of aluminum, nickel vanadium, and copper. However, several other UBM materials are contemplated by embodiments described herein. A contact pad, referred to herein may include a UBM layer.

The contact pads140can be arranged in various configurations, depending upon the medium in which it will be connected to another device or substrate.FIG. 2Aillustrates a top view of IC110, showing multiple contact pads140arranged primarily in the center of the active surface130of the IC110. This configuration can be used for a flip chip type of device, in which the device can have solder bumps or copper pillars connected to the contact pads140. The flip chip device and connected solder bumps are “flipped over” and connected to contact pads of another device or substrate.FIG. 2Billustrates a top view of IC110, showing multiple contact pads140arranged primarily around the perimeter of the active surface130of the IC110. This configuration can be used for a wire bonded type of device. The wire bonded device is attached, such as stacked devices or side-by-side wire bonded devices. Bonding wires connect the contact pads140of the wire bonded device to contact pads of another device or substrate.

Embodiments described herein include attaching individual ICs to a substrate.FIG. 3Aillustrates a substrate panel300, which can be used to form multiple die-attach substrates, shown individually as310. The substrate panel300can be made of a material, such as flex tape material, ceramic material, organic laminate material, resin-based material, lead frame, or other similar materials in which one or more ICs110can be supported. The substrate panel300is formed to include one or more routing layers and one or more electrically insulating layers. Electrically conductive vias are formed through the electrically insulating layers. Conductive contact pads on a first surface of the substrate panel300are connected through the substrate panel300by routing layers and vias to contact pads on a second surface of the substrate panel300.

The substrate panel300is separated into individual die-attach substrates310, which can be singulated similar to the wafer100singulation described above.FIG. 3Billustrates a cross section of an exemplary individual die-attach substrate310. The die-attach substrate310has metallization or contact pads320patterned on a first surface. Conductive vias330are formed through the die-attach substrate310and are electrically connected to contact pads340located on a second surface of the die-attach substrate310. The die-attach substrate310provides an interface to connect one or more ICs110on an upper surface, having a particular pattern of interconnecting contact pads to a PCB, for example having a different pattern of interconnecting contact pads or metallization. In an example, the lower contact pads340can be patterned to match a standard or commonly used PCB pattern.

After singulating the substrate panel300into individual die-attach substrates310, the individual die-attach substrates310are tested and sorted into working substrates and failed substrates. Testing may include, but is not limited to functional tests by applying probes to conductive features of substrates to provide test signals and to measure test results. Environmental tests may also be performed, such as exposure to moisture, extreme temperatures, and shock. Die-attach substrates310that are determined to be non-working can be marked by an ink mark, a laser marking, or other type of mark for later identification as a non-working substrate. This provides the advantage of continued processing with only good working substrates. The failed substrates are removed early in the process before investing further materials and resources. The substrate testing may also be performed in panel300before singulation.

FIG. 4Aillustrates an IC410in an inverted position with solder bumps430facing downward towards a die-attach substrate420. The IC410is a flip chip, in which solder bumps430have been attached to the active surface of the IC410. The solder bumps430may contain a metal core, such as copper with an outside solder film. The solder bumps430may also contain a solder material throughout, such as a tin/silver solder with no metal core. The solder bumps430may also be a copper post with tips coated with tin/silver solder.FIG. 4Billustrates the solder bumps430on the IC410are attached to contact pads on an upper surface of the die-attach substrate420. A tacking material can be used to temporarily hold the ICs410in place with their respective die-attach substrates420. For instance, solder flux can be applied to the contact pads to hold the solder bumps430in place until reflowing is completed.FIGS. 4A and 4Billustrate just one IC410and one mating die-attach substrate420for simplicity. However. ICs410are mated to each of the working die-attach substrates420on a reconstitution carrier. The entire reconstitution carrier of die-attach substrates420and mated ICs410is exposed to a reflow process, at a temperature above the reflow temperature of the solder bumps430. The reflow process mechanically and electrically connects each IC410to its respective die-attach substrate420. In an embodiment, a capillary underfill material440can be used to encapsulate the solder bumps430between each IC410and its respective die-attach substrate420. The capillary underfill material440is an insulative and non-conducting material used to protect the solder bump connections from oxidation and other environmental and physical elements.

FIG. 4Cillustrates an IC410connected to a die-attach substrate420in a face-up position. The inactive surface of the IC410is attached to the die-attach substrate420by an adhesive material. The active surface of the IC410contains contact pads435, which are connected to contact pads445on the die-attach substrate420by bonding wires450. The bonding wires450may be made of an oxidation-resistant material, such as gold, palladium-coated copper, or silver. In an embodiment, an insulative encapsulation material460can be formed over the bonding wires450and contact pads435of the IC410and contact pads445of the die-attach substrate420to protect the bonding wires450and respective contact pads from physical and environmental elements. The optional encapsulation material460may be applied by means of a glob top process, as an example. Glob-top materials, such as silicone or an epoxy having high viscosity, such that it can be applied to a substantially planar surface without being laterally confined. However, other methods of encapsulating bonding wires and associated contact pads are contemplated by embodiments described herein. The encapsulation material460also provides an advantage of preventing wire sweep in a future molding process. The encapsulation material460over the bonding wires450prevents the bonding wires450from touching one another when a molding material flows over the IC410.FIG. 4Cillustrates just one IC410and one mating die-attach substrate420for simplicity. However, ICs410are mated to each of the working die-attach substrates420on a reconstitution carrier.

FIGS. 5A-5Fillustrate a process of forming and integrating an interposer substrate, as used in embodiments described herein. The materials and processing can be similar to the die-attach substrate processing discussed above with reference toFIGS. 3A-3B.FIG. 5Aillustrates a substrate panel500, which can be used to form multiple interposer substrates, shown individually as510. The substrate panel500can be made of a material, such as flex tape material, ceramic material, organic laminate material, resin-based material, lead frame, or other similar materials. The substrate panel500is separated into individual interposer substrates510, which can be singulated in a similar process as the wafer100singulation process described above.

FIG. 5Billustrates a cross section of an exemplary individual interposer substrate510. The interposer substrate510has metallization or contact pads520patterned on a first surface. Conductive vias530are formed through the interposer substrate510and are electrically connected to contact pads540located on a second surface of the interposer substrate510. The conductive vias530redirect the upper contact pads520, patterned to receive additional devices or substrates to the lower contact pads540, patterned to connect with a die-attach substrate, for example.

FIG. 5Cillustrates solder balls550being connected to contact pads540on the second surface of the interposer substrate510. The solder balls550can be temporarily held in place by a tacking material, such as solder flux during processing. The solder balls550are mechanically and electrically connected to the contact pads540of the interposer substrate510by exposing the combined interposer substrate510and solder balls550to a temperature above the reflow temperature of the solder balls550.

FIG. 5Dillustrates how the interposer substrate510will be mounted over an IC410to a die-attach substrate420. The solder balls550straddle the IC410located in the center of the die-attach substrate420. The solder balls550are of a sufficient size to hold the interposer substrate510above the IC410when mounted.FIG. 5Dillustrates a flip chip IC410, in which the inactive surface of the IC410will be connected to the second surface of the interposer substrate510. An adhesive560has been applied to the inactive surface of the IC410. The adhesive560may include, but is not limited to an adhesive paste, a die-attach film, an epoxy solder flux, or other adhesive materials with properties that are suited for the adjoining materials of the IC410and the interposer substrate510, and are suited for the operating temperatures of the IC410. The adhesive560can be applied to the inactive surface of the IC410and/or the second surface of the interposer substrate510in a variety of patterns, as illustrated inFIG. 6. Other patterns of adhesive application are contemplated by embodiments described herein. The particular pattern may depend upon factors, such as but not limited to size of the IC410, power level of the IC410, heat dissipation of the IC410, environmental exposure, intended use of the final semiconductor package, as well as other factors.

FIG. 5Eillustrates an interposer substrate510mounted to a die-attach substrate420with a flip chip IC410mounted thereon to form a reconstituted semiconductor package. A tacking material, such as solder flux can be used to temporarily hold the solder balls550in place with contact pads of their respective die-attach substrates420. The interposer substrate510is also adhered to the back side of the flip chip IC410. The combined structure ofFIG. 5Eis exposed to a reflow process to mechanically and electrically connect the solder balls550to the contact pads of the die-attach substrate420(not shown inFIG. 5E). The adhesive560can be cured during the reflow process, or an additional process can be implemented to cure the adhesive560, preferably after the reflow process. In an embodiment, the interposer substrate510and the IC410can be attached in one reflow process.

FIG. 5Fillustrates an assembled die-attach substrate420and interposer substrate510for a wire bonded IC410to form another type of reconstituted semiconductor package. Since the active surface of the IC410is facing the interposer substrate510, the interposer substrate510is not connected or adhered to the IC410. The solder balls550are of a sufficient size to hold the interposer substrate510above the IC410. An additional embodiment includes copper posts or solder columns in lieu of solder balls550to insure adequate height of the interposer substrate510above the IC410. A tacking material can be used to temporarily hold the solder balls or copper posts550in place with their respective die-attach substrates420until a reflow process permanently connects the solder balls550to the two substrates.

FIG. 5Efor a flip chip IC andFIG. 5Ffor a wire bonded IC are given for exemplary purposes only. Another type of IC that can be used with embodiments described herein is an IC mounted to a lead frame, either with or without a die pad. With some adjustments, micro-electro-mechanical system (MEMS) devices and opto-electronic devices can be integrated into a reconstituted semiconductor package, according to embodiments described herein.

In the assembly process illustrated inFIGS. 4A-5F, there are multiple reflow processes. For the flip chip IC410, the solder bumps430are reflow connected to the die-attach substrate420(seeFIG. 4A), the solder balls550are reflow connected to the interposer substrate510(seeFIG. 5C), and the solder balls550are reflow connected to the die-attach substrate420(seeFIG. 5E).

The reconstituted semiconductor packages described above can be prepared for mold-injection, according to embodiments described herein.FIG. 7Aillustrates multiple assembled packages710affixed to a reconstitution carrier720. Each assembled package710comprises an IC mounted to a die-attach substrate at a first surface of the IC, and an interposer substrate mounted over a second surface of the IC, wherein the interposer substrate is electrically and mechanically connected to the die-attach substrate. The assembled packages710may contain the same type of IC or different types of ICs.

FIG. 7Billustrates a top view of the reconstitution carrier720in which individual assembled packages710are spaced apart in a rectangular array on the reconstitution carrier720. A rectangular panel carrier is illustrated; however, other configured carriers are within the scope of the described embodiments, such as a square panel carrier or a long and narrow strip carrier. The reconstitution carrier720may have a variety of materials that is suitable for holding and transporting the array of assembled packages710. Carrier materials may include, but are not limited to adhesion tape, ceramic, glass, plastic, semiconductor material, metal, or other material. An adhesive material can be applied to a surface of the carrier and/or to surfaces of the assembled packages710. An adhesive material may include, but is not limited to epoxy or an adhesive film. In an embodiment, an adhesive tape is used to maintain the positions of the assembled packages710during processing. The adhesive tape can be a panel configuration, such as the reconstitution carrier720, or it can be a roll or strip of adhesive tape for receiving the array of assembled packages710.

FIG. 8Aillustrates the assembled packages710attached to the reconstitution carrier720. The reconstitution carrier720can be marked at positions where each assembled package710is to be placed. The markings can be optically located for correct placement of the assembled packages710onto the reconstitution carrier720. A molding film810is pressed to the top surfaces of the assembled packages710. Film810typically does not have cuts or openings. Alternatively, holes such as820can be made and spaced on the molding film810for the purpose of allowing a molding compound830to reach within the assembled packages710, as well as reach in-between individual assembled packages710. In an embodiment, holes820are placed at positions in-between the individual assembled packages710. In another embodiment, the molding compound830is under vacuum to facilitate movement of the molding compound830to reach all open spaces within and in-between the assembled packages710. The molding film810on top of the assembled packages710keeps the contact pads on the upper surfaces of the interposer substrates clean and free from any molding compound830. Likewise, the reconstitution carrier720on the bottom of the assembled packages710keeps the contact pads on the lower surfaces of the die-attach substrates clean and free from any molding compound830.

FIG. 8Billustrates removal of the molding film810and the reconstitution carrier720. An adhesive tape type of reconstitution carrier720can be removed by mechanical de-taping or applying UV light to reconstitution carrier720to deactivate the adhesive nature of the tape. Solder balls840are attached to the contact pads on the bottom surfaces of the die-attach substrates to form a ball grid array (BGA) of each assembled package710. Solder flux can be applied to the contact pads of the die-attach substrate to hold the solder balls840in place until reflowing is completed. Embodiments for a reconstituted semiconductor package can be applied to most types of semiconductor packages, such as but not limited to fine-pitch ball grid arrays (FBGA), pin grid arrays (PGA), column grid arrays (CGA), land grid arrays (LGA), z-interconnect arrays, as well as others.

Another embodiment includes using the reconstitution carrier720illustrated inFIG. 8Aas a solder stencil. The reconstitution carrier720can be made of a polymer or photoimageable material, which can be patterned when exposed to ultraviolet (UV) light. A solder mask containing a plurality of openings that match the contact pads on the bottom surfaces of the die-attach substrates is placed over the reconstitution carrier720. UV light exposes the reconstitution carrier720through the openings in the solder mask. The exposed areas of the reconstitution carrier720are removed. The solder balls are placed within the openings over the contact pads. A reflow process mechanically and electrically connects the solder balls to their respective contact pads. Another embodiment provides a solder paste (a mixture of solder and flux) that is screen printed into the openings using a solder applicator. A reflow process causes the solder paste to reflow and connect the resulting solder balls or bumps to their respective contact pads. The reconstitution carrier720can be removed after the reflow process, or it can remain on the bottom side of the die-attach substrate.

FIG. 8Cillustrates the assembled and molded packages singulated into individual reconstitution semiconductor packages800. The singulation can be implemented by cutting, sawing, laser slicing, or any other method of cutting through molding compound. By exercising embodiments described herein, singulation occurs only through the molding compound. There is no cutting through either the interposer substrate or the die-attach substrate when the interposer substrate and the die-attach substrate are approximately the same size and the molding compound extends beyond the perimeters of the substrates. The interposer substrates mounted to their respective die-attach substrates are separated from one another to form a gap between the packages (seeFIGS. 7A-8B). Therefore, there is no cutting of either substrate, and as a result, there is no wasted substrate material from the singulation process. Also, the molding along the edges of the substrates will increase the protection of the final package.

FIG. 9Aillustrates a variation of the process illustrated inFIG. 5D, where an adhesive560was applied to the back side of the IC410. The adhesive560was also adhered to the interposer substrate510when the interposer substrate510was mounted to the die-attach substrate420.FIG. 9Aillustrates an absence of adhesive between the IC and the interposer substrate. Instead, the molding compound830fills the gap between the IC and the interposer substrate. A vacuum molding process helps to insure that the molding compound reaches all open spaces within the package.

FIG. 9Billustrates the same device and process illustrated inFIG. 9A, in addition to substituting molding compound830for the capillary underfill material between the IC and the die-attach substrate. A vacuum molding process helps to insure that the molding compound reaches all open spaces within the package.

FIG. 10Ais an illustration of an interposer package-on-package semiconductor device1000according to embodiments described herein. An interposer substrate1090is mounted to a die-attach substrate1030by means of solder balls1270a. The solder balls1270aare connected to the bottom surface1120bof the interposer substrate1090by means of contact pads1300b, and the solder balls1270aare connected to the top surface1060aof the die-attach substrate1030by means of contact pads1300a. A flip chip integrated circuit1150is connected to the top surface1060aof the die-attach substrate1030by means of contact pads1300d. A molding compound1240is filled within all open spaces between the interposer substrate1090and the die-attach substrate1030, as well as along the edges of the connected interposer substrate1090and the die-attach substrate1030. External solder balls1270bare attached to the bottom surface1060bof the die-attach substrate1030by means of contact pads1300c. Additional devices such as a surface mount device1210and a flip chip device1180are connected to the top surface1120aof the interposer substrate1090by means of contact pads1300.

FIG. 10Bis an illustration of a flip chip IC1030connected to a die-attach substrate1020, and an interposer substrate1010connected to the die-attach substrate1020by solder balls1040. Encapsulation1050is filled in between the interposer substrate1010and the die-attach substrate1020and around the IC. The encapsulation1050is also filled around the sides of both substrates. However, the interposer substrate1010is smaller than the die-attach substrate. InFIG. 10C, a similar flip chip package is illustrated, in which the interposer substrate1010is larger than the die-attach substrate1020. Although not illustrated, the flip chip packages ofFIGS. 10B and 10Cwould have solder balls connected to the bottom surface of the die-attach substrate1020, as illustrated in earlier figures.

FIG. 10Dis an illustration of a plurality of die-attach substrates1020, with associated flip chip ICs1030connected thereto, as well as associated interposer substrates1010connected to the die-attach substrates1020by solder columns or conductive posts1040. Encapsulation1050is filled in between the interposer substrates1010and the die-attach substrates1020. The die-attach substrates1020are abutted next to each other, so the encapsulation1050only resides along the sides of the interposer substrates1010and not along the sides of the die-attach substrates1020. In an embodiment, the die-attach substrates1020may be previously singulated, tested, and grouped together on a carrier, such as previously described. In another embodiment, the die-attach substrate1020may be one whole substrate or wafer, which is singulated during the final singulation process to form the individual packages.

FIG. 10Eis similar to the packages illustrated inFIG. 10D, except the interposer substrates1010are abutted next to each other, so the encapsulation1050only resides along the sides of the die-attach substrates1020and not along the sides of the interposer substrates1010. In an embodiment, the interposer substrates1010may be previously singulated, tested, and grouped together on a carrier, such as previously described. In another embodiment, the interposer substrate1010may be one whole substrate or wafer, which is singulated during the final singulation process to form the individual packages.

FIG. 11is a flowchart for a method of forming a semiconductor package1100, such as a reconstituted interposer package-on-package. An array of die-attach substrates is formed onto a carrier in step S1110. The array of individual die-attach substrates may contain reconstituted working substrates, wherein the substrates were previously tested and only the working substrates are held for further processing. The carrier may be comprised of an adhesive carrier. A semiconductor device is mounted onto a first surface of each of the die-attach substrates in step S1120. In an embodiment, the semiconductor device is a flip chip device. In another embodiment, the semiconductor device is a wire bonded device.

Solder ball connections are formed to a plurality of interposer substrates in step S1125. Each interposer substrate is mounted over a respective semiconductor device in step S1130. The interposer substrates are electrically and mechanically connected to the first surface of the respective die-attach substrates, via the solder ball connections in step S1140. In an embodiment, the die-attach substrate and the interposer substrate are approximately the same size. In another embodiment, the die-attach substrate is larger than the interposer substrate. In still another embodiment, the die-attach substrate is smaller than the interposer substrate. A molding compound is filled in open spaces within and between the interposer substrates mounted to their respective die-attach substrates to form an array of reconstituted semiconductor packages in step S1150. In an embodiment, the array of packages has a gap between each of the die-attach substrates and their respective mounted interposer substrates. As a result, the molding compound fills the gaps between each reconstituted semiconductor package of a die-attach substrate and mounted interposer substrate.

Electrical connections are mounted to a second surface of the die-attach substrates in step S1160. In an embodiment, the electrical connections are mounted in a grid array pattern. The array of reconstituted semiconductor packages are singulated through the molding compound between each of the die-attach substrates and respective mounted interposer substrates in step S1170. The singulation cuts through the molding compound only. Since there is a gap between each pair of die-attach substrates and respective mounted interposer substrates, neither substrate is cut by the singulation process.

The methods and devices described herein are exemplary and are given to illustrate the features and processes of certain embodiments. Embodiments are not restricted to any particular order or to the exemplary order described herein. For example, preparation of the interposer substrate and electrical connections could be executed before preparation of the IC and die-attach substrate connections. As another example, the interposer substrate processing could be con-current with the IC and die-attach substrate processing.

Embodiments described herein for a reconstituted interposer semiconductor package can be used in many applications, including but not limited to the networking, mobile, wireless, wearable electronics, and broadband. In the networking application, the reconstituted interposer semiconductor package described herein can be used in multi-core processors, knowledge-based processors, server message block (SMB) processors, encryption coprocessors, and security processors. In the mobile, wireless applications, and wearable applications, the reconstituted interposer semiconductor package described herein can be used in 3G baseband processors, LTE baseband processors, mobile video processors, mobile graphics processors, application processors, touch controllers, wireless power, Internet of things (IoT) and wearable system-on-chips (SoCs), wireless video, and antennas. In the broadband applications, the reconstituted interposer semiconductor package described herein can be used in cable set-top boxes (STBs), satellite STBs, Internet Protocol (IP) STBs, terrestrial STBs, ultra high definition (HD) processors. STB graphics processors, and STB security processors. These devices and systems can be used in products including but not limited to routers, smartphones, tablets, personal computers, and wearable devices such as watches, shoes, clothes, and glasses.

The foregoing discussion discloses and describes merely exemplary embodiments of the present invention. As will be understood by those skilled in the art, the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. Accordingly, the disclosure of the present embodiments is intended to be illustrative, but not limiting of the scope of the embodiments, as well as other claims. The disclosure, including any readily discernible variants of the teachings herein, define, in part, the scope of the foregoing claim terminology such that no subject matter is dedicated to the public.