Semiconductor device and method of fabricating the same

A method of fabricating a semiconductor device including depositing a first silicon oxide film on a silicon substrate, depositing a silicon-containing film on the first silicon oxide film, applying a coating solution for silica film formation over the silicon-containing film, and heat-treating the coating solution, thereby forming a second silicon oxide film.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2004-156214, filed on May 26, 2004, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device using a silica film forming coating liquid for forming a silica film and a method of fabricating the same.

2. Description of the Related Art

A degree of integration and miniaturization have recently been increased and miniaturization has recently progressed. With this, a size reduction in an element isolation region has been desired strongly. A shallow trench isolation (STI) structure has been employed in an increasing number of times to meet the needs. The STI structure can sufficiently render the element isolation region sufficiently small. As one of methods of burying a silicon oxide film (SiO2) in an isolation groove in the STI, methods using a polysilazane film are known. For example, Japanese Patent No. 3178412 discloses one of the methods using the polysilazane film.

In the method disclosed in Japanese Patent No. 3178412, an SiO2film is formed on a surface of a silicon substrate and thereafter, a silicon nitride (SiN) film is formed on the SiO2film. Furthermore, an isolation groove is formed in the SiN film. Successively, the surface of the substrate is covered with a polysilazane solution (a solution of a silazane perhydride polymer in the above-noted reference) by spin coating. Subsequently, oxidation by substitution is carried out using H2O (in an atmosphere of steam) so that the polysilazane film is denaturalized to an SiO2film.

The following problem arises when the polysilazane film is applied to STI. In the oxidation by substitution in the atmosphere of steam, H2O reaches the substrate, oxidating the same. Oxidation of the substrate increases a thickness of the gate oxide film. Oxidation of the substrate further shrinks the polysilazane film. When the groove has a large width, the SiO2film peels off.

BRIEF SUMMARY OF THE INVENTION

Therefore, an object of the present invention is to provide a semiconductor device in which the silicon substrate can be prevented from oxidation and the silicon oxide film can be prevented from peeling off when the coating film is oxidated and a method of fabricating the same.

The present invention provides a semiconductor device comprising a silicon substrate, a first silicon oxide film deposited on the silicon substrate, a silicon-rich film deposited on the first silicon oxide film, and a second silicon film deposited on the silicon-rich film and formed by heat-treating a fluid applied for forming a silica coat.

The invention also provides a method of fabricating a semiconductor device, comprising depositing a first silicon oxide film on a silicon substrate, depositing a silicon-containing film on the first silicon oxide film, applying a coating solution for silica film formation over the silicon-containing film, and heat-treating the coating solution, thereby forming a second silicon oxide film.

DETAILED DESCRIPTION OF THE INVENTION

One embodiment of the present invention will be described with reference toFIGS. 1 to 7. In the embodiment, the invention is applied to a technique of burying an element isolation groove of the shallow trench isolation (STI) structure.

Firstly, a grooved sample11for evaluation is prepared and has such a structure as shown inFIG. 2. The grooved sample11includes a silicon substrate1having an upper surface on which a silicon nitride (SiN) film2is deposited, for example, by 150 nm. Thereafter, for example, five grooves1aare formed by the lithography and dry etching techniques. Three of the five grooves1aare shown inFIG. 2. Each groove1ahas a depth of 450 nm, for example. Each groove1ahas a depth of 300 nm in the substrate1. Furthermore, the five grooves1ahave widths of 100 nm, 500 nm, 1000 nm, 5000 nm and 10000 nm respectively.

A silicon oxide (SiO2) film3is deposited on the grooved sample11or the substrate1, for example, by a high density plasma CVD (HDP) technique. The SiO2film3has a film thickness of 200 nm, for example. Subsequently, a polysilazane solution serving as a coating solution for silica film formation is applied to the SiO2film3by spin coating thereby to be formed into a polysilazane coating film4. As a result, a first sample12as shown inFIG. 3is formed. The first sample12corresponds to a conventional structure and a compared example to be compared with a sample of the embodiment (a second sample13as shown inFIG. 1).

The following is a condition for deposition of the SiO2film3using the HDP technique: the conditions of an SiH4/O2gas flow and source power/bias power are represented as SiH4/O2=55/110 sccm and SRF/BRF=4400/2600 W.

A second sample13with a structure as shown inFIG. 1is then formed. In this case, the SiO2film3is deposited by 200 nm on the grooved sample11with the foregoing structure using an HDP technique. Continually, an Si-rich film14is deposited by 100 nm, for example. Subsequently, a polysilazane solution is applied to the Si-rich film14by spin coating, thereby forming a polysilazane coating film4. As a result, a second sample13, which is a sample of the embodiment, is formed. The Si-rich film14constitutes a film containing Si.

The above-described Si-rich film14is a stoichiometrically silicon rich film and is composed of an Si-rich insulating film, for example, an Si-rich SiO2film. The silicon rich insulating film (SiO2film) has a refractive index ranging from 1.45 to 1.72. The reason for the setting of this range is that since Si has a refractive index of 1.72 and SiO2 has a refractive index of 1.45, the SiO2film becomes rich with Si if the SiO2 film has a refractive index ranges from 1.45 to 1.72.

In the embodiment, the conditions of an SiH4/O2gas flow and source power/bias power are represented as SiH4/O2=55/110 sccm and SRF/BRF=4400/2600 W. A CENTURA-Ultima chamber manufactured by Applied Materials Inc. was used to make the aforesaid SiO2film3and Si-rich film14.

For determination of the SiO2film3and Si-rich film14, a film was formed using a bare-Si wafer apart from the aforesaid two samples12and13. A refractive index was measured, and the determination of the SiO2film and Si-rich film14was made on the basis of the measured refractive index. More specifically, the SiO2film and Si-rich film were formed on the bare-Si wafer so as to each have a thickness of 400 nm, and then, the refractive index was measured. UV1280 Film Thickness Measurement System produced by KLA-Tencor Corporation was used for measurement of refractive index. Refractive indexes of the formed SiO2film and Si-rich film were 1.46 and 1.65 respectively.

Furthermore, as shown inFIG. 6, a bare Si wafer15was prepared, and the SiO2film3was formed on the bare Si wafer15under the same condition as the above-described first sample12. A polysilazane solution was applied to the SiO2film3to be formed into a polysilazane coating film4. Thus, a third sample16was formed.

Additionally, as shown inFIG. 7, the bare Si wafer15was prepared, and the SiO2film3and Si-rich film14were formed under the same condition as the above-described second sample13. A polysilazane solution was applied to the SiO2film3to be formed into a polysilazane coating film4. Thus, a fourth sample17was formed.

Subsequently, the aforesaid four samples12,13,16and17of the polysilazane coating film4were processed for oxidation by substitution in an atmosphere of H2O (steam). More specifically, the four samples12,13,16and17were heat-treated as follows. An oxidizing furnace ALPHA-8SE-Z manufactured by Tokyo Electron Ltd. was used for the heat-treatment.

Firstly, the samples were heat-treated in an atmosphere of H2O at 400° C. for 15 minutes and thereafter, further heat-treated in an atmosphere of O2at 800° C. for 30 minutes. Subsequently, refractive indexes of the third and fourth samples16and17were 1.458 and 1.456 respectively. Consequently, it was confirmed that the polysilazane coating film4deposited on each of the samples16and17became an SiO2film. From the results of the third and fourth samples16and17, it was confirmed that the polysilazane coating film4deposited on each of the first and second samples12and13also became an SiO2film.

A section of the first sample12was observed using a scanning electron microscope (SEM). Type S-5200 manufactured by Hitachi, Ltd. was used as SEM. As the result of the observation, it was confirmed that the silicon substrate1was oxidated in each groove1aof the first sample12, as shown inFIG. 4. An oxidated region is shown by oblique lines inFIG. 4. Furthermore, it was confirmed that peeling occurred in a boundary between high density plasma (HDP)-SiO2 film3and the polysilazane coating film4(SiO2film) in a part of the groove1ahaving a width of 10000 nm.

A section of the second sample13was also observed using SEM. No such fault as found in the first sample12was confirmed in the second sample13as shown inFIG. 5.

Causes of the fault in the first sample12will be considered. Firstly, a cause of oxidation on the substrate1of the first sample12will be described. When the polysilazane coating film4was oxidated, H2O reached the substrate1and oxygen (O) in H2O reacted with Si to form SiO2. Furthermore, as for a cause of the peeling in the groove part with the width of 10000 nm, the polysilazane coating film4shrinks when Si—NH is oxidized into SiO2. Accordingly, in the wide groove part where an absolute amount of shrinkage is large, the peeling occurs in a boundary between high density plasma (HDP)-SiO2 film3and the polysilazane coating film4(SiO2film).

On the other hand, the structure of the HDP-SiO2 film3, Si-rich film14and polysilazane coating film4as the second sample13causes the following reaction: when H2O reaches the Si-rich film in the oxidation of the polysilazane coating film4, oxygen of H2O reacts with the Si-rich film14to form SiO2. Since oxygen is thus consumed, H2O does not reach the substrate1. In this case, the Si-rich film14serves as a film with a function of preventing H2O or oxygen from permeation. Accordingly, the substrate1can be prevented from oxidation in the second sample13.

Furthermore, the second sample13expands when SiO2 is formed by the reaction of oxygen with Si-rich film14. The expansion compensates for the shrinkage of the second sample13when Si—NH of the polysilazane coating film is oxidated by substitution into SiO2. Consequently, the peeling does not occur in the boundary between the HDP-SiO2 film3and the polysilazane coating film4(SiO2film).

The foregoing embodiment includes depositing the SiO2film3on the silicon substrate1, depositing the Si-rich film14on the SiO2film, applying the polysilazane coating solution on the Si-rich film14, and oxidating (heat-treating) the polysilazane coating film14by substitution. When H2O reaches the Si-rich film14in the oxidation of the polysilazane coating film4by substitution, oxygen of H2O reacts with Si to form SiO2, whereupon oxygen is consumed.

Accordingly, since H2O is prevented from reaching the substrate1, the substrate1can be prevented from oxidation. Furthermore, the cubic volume of the Si-rich film14is expanded when oxygen of H2O reacts with Si to form the SiO2film. The cubic expansion can compensate for cubic shrinkage resulting from film shrinkage of the polysilazane coating film4due to oxidation by substitution. Consequently, the peeling of the SiO2film can be prevented in the boundary between the HDP-SiO2 film3and the polysilazane coating film4.

The following describes a case where the foregoing fabricating method is applied to fabrication of a NAND-type flash EEPROM. InFIG. 8, each one of NAND cells comprises a plurality of series-connected memory cells MC. Each NAND cell is isolated by a shallow trench isolation structure including a buried insulating film22formed, for example, in a p-type semiconductor substrate21.

In each memory cell MC, a gate oxide film23is formed on the surface of a semiconductor substrate21. A first floating gate24acomprising, for example, poly-silicon is formed on the gate oxide film23. The first floating gage24aconstitutes a floating gate FG. A second floating gate24bcomprising, for example, poly-silicon is formed on the first floating gate24a. The second floating gage24balso constitutes the floating gate FG.

For example, an oxygen-nitride-oxygen (ONO) film25serving as a composite insulating film is formed on the second floating gate24b. A control gate26comprising poly-silicon is formed on the ONO film25. A mask27comprising a silicon nitride film is formed on the control gate26. The mask27, control gate26and first and second floating gates24aand24bare covered with a silicon nitride film28, whereupon a gate structure GS is constituted.

An n-type diffusion layer29is formed in each part of the substrate21located between the gate structures GS. The diffusion layer29and the gate structure GS constitute each memory cell MC. The adjacent memory cells MC are connected in series to each other so as to own each diffusion layer jointly. The memory cells MC are covered with an interlayer insulating film30made from, for example, boro-phospho-silicate glass (BPSG). Wiring31made from tungsten, for example, is formed in the interlayer insulating film30.

The fabrication step of the NAND-type flash EEPROM will be described with reference toFIGS. 9A to 10B. Firstly, as shown inFIG. 9A, on the surface of the substrate1are formed the gate oxide film23, first floating gate24amade from poly-silicon and mask32made from the silicon nitride film sequentially. Subsequently, the mask32is patterned, and the first floating gate24a, gate oxide film23and substrate21are etched with the patterned mask32serving as a mask so that a plurality of trenches are formed.

Subsequently, a process for forming a buried insulating film22in the trenches33or an STI structure forming step is carried out. This step is carried out in the same manner as the step of forming and heat-treating the second sample13as shown inFIG. 1. More specifically, firstly, the SiO2film3is deposited on the substrate1as shown inFIG. 9B. Successively, the Si-rich film14is deposited on the SiO2film3. The film forming conditions for the SiO2film3and Si-rich film14are the same as described above.

A polysilazane coating liquid is applied to the Si-rich film14by spin coating, thereby forming the polysilazane coating film4. Thereafter, the polysilazane coating film4is oxidated by way of substitution or heat-treated to be formed into the SiO2film. The heat-treating conditions are the same as described above. As a result, as shown inFIG. 9C, the buried insulating film22comprising the SiO2film is formed, whereby the trenches33are filled. Subsequently, the aforesaid SiO2film (buried insulating film)22is flattened by chemical mechanical polishing with the mask32serving as a stopper.

Subsequently, the second floating gate24bcomprising, the surface of the SiO2film22in each trench33is etched by the dry or wet etching so as to be slightly lower than the surface of the mask32. As a result, a step between the first floating gate24aand the surface of the insulating film22is reduced. Subsequently, the mask32is removed.

Subsequently, as shown inFIG. 10A, the second floating gate24bcomprising, for example, poly-silicon8is formed on the surface of the first floating gate24a. Thereafter, the second floating gate24bis patterned by the dry etching, and a slit34is formed in the upper surface of the buried insulating film22as shown inFIG. 10B. For example, the ONO film25, the silicon gate (CG)26made from poly-silicon and the mask27are formed sequentially as a composite insulating film including the second floating gate.

Thereafter, as well known in the art, the mask27is patterned. Using the patterned mask27, the poly-silicon composing the control gate26and the ONO film25are etched using the patterned mask27. The mask27, control gate26and first and second floating gates24aand24bare covered by the silicon nitride film28, whereupon the gate structure GS is formed, as shown inFIG. 8.

Furthermore, the n-type diffusion layers29are formed in parts of the substrate21located between the gate structures GS. The n-type diffusion layers29serve as source or drain regions. Each memory cell MC is composed of the diffusion layer29and the gate structure GS. The memory cells MC are covered with an interlayer insulating film30made from, for example, BPSG. Wiring31made from tungsten and contact holes (not shown) are formed in the interlayer insulating film30, whereupon a NAND-type flash EEPROM is fabricated.

The invention should not be limited to the foregoing embodiment. The embodiment may be modified or expanded as follows. Firstly, although the thickness of the Si-rich film14is 100 nm in the foregoing embodiment, the thickness of the Si-rich film may be set to a suitable value ranging from 10 nm to 500 nm according to a thickness of the polysilazane coating film4.

A film containing Si, for example, an Si film may be deposited, instead of the Si-rich film14.

An insulating film deposited under the Si-rich film14or the SiO2film has a thickness of 100 nm in the foregoing embodiment. However, the thickness of the SiO2film may be set to a suitable value ranging from 10 nm to 300 nm according to a thickness of the polysilazane coating film4.

The SiO2film3deposited under the Si-rich film14is formed by the high density plasma (HDP) technique in the foregoing embodiment. However, for example, the plasma enhanced chemical vapor deposition (PECVD) technique or reflow burying technique may be employed, instead. Furthermore, the invention is applied to a burying technique for element isolation in the foregoing embodiment. However, for example, the invention may be applied to a burying technique for a space between the gate electrodes or for a space between metal wirings.

Furthermore, the coating liquid should not be limited to polysilazane. Any silica film forming liquid may be employed in which the oxide silicon whose characteristics are varied after the heat treatment is similar to the density of the oxide silica deposited by the high density plasma CVD.

The foregoing description and drawings are merely illustrative of the principles of the present invention and are not to be construed in a limiting sense. Various changes and modifications will become apparent to those of ordinary skill in the art. All such changes and modifications are seen to fall within the scope of the invention as defined by the appended claims.