Amplifying circuit, analog to digital converter with multi-stage conversion range and related conversion method

An amplifying circuit for analog to digital converter with multi-stage conversion range is used for dividing an analog input voltage into multiple voltage ranges to perform signal amplification and attenuation according to multiple magnifications (e.g., amplify the analog input voltage with low voltage level, and attenuate the analog input voltage with high voltage level). The analog to digital converter performs analog to digital conversion to the analog input voltage with amplification or attenuation to generate a digital bit with amplification or attenuation, and then generates an output digital bit according to the digital bit and the magnification. As a result, the analog to digital converter is adaptive to the analog input voltage with high voltage level, and precision and quantization error of the analog input voltage with low voltage level can be maintained as well.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an amplifying circuit, analog to digital converter with multi-stage conversion range and related conversion method, and more particularly, to an amplifying circuit, analog to digital converter with multi-stage conversion range and related conversion method adaptive to the analog input voltage with high voltage level, and maintain precision and quantization error of the analog input voltage with low voltage level.

2. Description of the Prior Art

Analog-to-Digital Converter (ADC) is widely used in microcontrollers, however, applicant notices two major problems in the circuit design and application of the analog-to-digital converter.

First, an input source signal must be attenuated before it is inputted to the analog to digital converter when a maximum voltage level of the input source signal is greater than a maximum allowable input voltage level of the analog to digital converter. However, when an input source signal with low voltage level (e.g., a small signal with voltage level 0 to 1 Volt) is inputted to the analog to digital converter, a quantization error of a digital output signal corresponding to the small signal appears to be greater than a quantization error of a digital output signal corresponding to an input signal without attenuation, which results low precision to the small signal.

Second, some specific applications require high precision for the small signal with low level range; however, the analog to digital converter adaptive to high level range cannot meet the requirement for the quantization error (or, precision) of the low level range. In particular using a design of uniform quantization error, the quantization error increases if the voltage level of the input source becomes smaller, thereby the precision of the small signal decreases.

Therefore, there is a need to provide an analog to digital converter adaptive to the input voltage with high level range and precision and quantization error of the input voltage with low voltage level can be maintained as well.

SUMMARY OF THE INVENTION

It is therefore an objective of the present invention to provide an amplifying circuit, analog to digital converter with multi-stage conversion range and related conversion method adaptive to the analog input voltage with high voltage level, and maintain precision and quantization error of the analog input voltage with low voltage level.

The present invention discloses an amplifying circuit for analog to digital converter with multi-stage conversion ranges includes a first comparator, a first operational amplifier, a first switch, a NOR Gate, a second operational amplifier, a second switch, a second comparator, a third operational amplifier, and a third switch. The first comparator is configured to output a first control signal according to a first threshold voltage and an analog input signal. The first operational amplifier is configured to amplify the analog input signal according to a first magnification to generate a first amplified analog input signal. The first switch is coupled to the first comparator and the first operational amplifier, and configured to control whether to output the first amplified analog input signal according to the first control signal, wherein the first switch control outputs the first amplified analog input signal when the analog input signal is substantially smaller than the first threshold voltage. The NOR Gate is configured to generate a second control signal according to the first control signal and a third control signal. The second operational amplifier is configured to amplify the analog input signal according to a second magnification to generate a second amplified analog input signal. The second switch is coupled to the NOR Gate and the second operational amplifier, and configured to control whether to output the second amplified analog input signal according to the second control signal, wherein the first switch control outputs the second amplified analog input signal when the analog input signal is substantially greater than the first threshold voltage and smaller than a second threshold voltage. The second comparator is configured to output the third control signal according to the second threshold voltage and the analog input signal. The third operational amplifier is configured to amplify the analog input signal according to a third magnification to generate a third amplified analog input signal. The third switch is coupled to the second comparator and the third operational amplifier, and configured to control whether to output the third amplified analog input signal according to the third control signal, wherein the third switch controls outputting the third amplified analog input signal when the analog input signal is substantially greater than the second threshold voltage.

The present invention further discloses an analog to digital converter with multi-stage conversion ranges includes the amplifying circuit as above mentioned and a microcontroller. The microcontroller is coupled to the amplifying circuit, and configured to perform analog to digital conversion to one of the first amplified analog input signal, the second amplified analog input signal and the third amplified analog input signal to generate an amplified digital code, and generate a digital output code according to the amplified digital code and one of the first magnification corresponding to the first control signal, the second magnification corresponding to the second control signal and the third magnification corresponding to the third control signal.

The present invention further discloses a method of analog to digital conversion, for an analog to digital converter with multi-stage conversion ranges, and includes determining a magnification according to a plurality of control signals; amplifying an analog input signal according to the magnification to generate an amplified analog input signal; performing analog to digital conversion to the amplified analog input signal to generate an amplified digital code; and generating an output digital code according to a reciprocal of the magnification and the amplified digital code.

The present invention divides the analog input voltage into multiple voltage level ranges, respectively performs signal amplification and attenuation based on different magnifications, and computes the digital codes corresponding to the analog input voltage according to the magnifications. As a result, the analog to digital converter is adaptive to the analog input voltage with high voltage level, and precision and quantization error of the analog input voltage with low voltage level can be maintained as well.

DETAILED DESCRIPTION

FIG. 1is a functional block diagram of an analog-to-digital Converter, (ADC)1. The analog to digital converter1is configured to convert an analog input signal V_IN into a digital output signal D_OUT, and includes a comparator10, a sample and hold unit11, an N-bit digital to analog converter (Digital-to-Analog Converter, DAC)12, a logic control circuit13and an N-bit register14.

The sample and hold unit11is coupled to comparator10, and configured to perform sampling to the analog input signal V_IN to generate a sampled signal V_SAMP to the comparator10. The comparator10is coupled to the sample and hold unit11, the digital to analog converter12and the logic control circuit13, and includes a positive input terminal, a negative input terminal and an output terminal. The comparator10is configured to compare the sampled signal V_SAMP with a reference analog voltage V_DA to generate a comparison result RST to the logic control circuit13. The logic control circuit13is coupled to the comparator10and the N-bit register14, and configured to generate a bit data D_BIT to the N-bit register14according to the comparison result RST. The N-bit register14is coupled to the digital to analog converter12and the logic control circuit13, and configured to generate the digital output signal D_OUT to the digital to analog converter12according to the bit data D_BIT, and output the digital output signal D_OUT. The digital to analog converter12is coupled to the comparator10and the N-bit register14, and configured to convert the digital output signal D_OUT into the reference analog voltage V_DA according to a reference voltage V_REF to output the reference analog voltage V_DA to the negative input terminal of the comparator10.

Given that the analog input signal V_IN is an analog small signal with a voltage level 0-1 Volt, and the analog to digital converter1is an eight-bit converter (i.e., N=8 bits). In operation, the comparator10compares the sampled signal V_SAMP with the reference analog voltage V_DA to generate the comparison result RST with a high voltage level when the sampled signal V_SAMP is greater than reference analog voltage V_DA, so the bit data D_BIT generated by the logic control circuit13is logic “1”. On the other hand, the comparator10generates the comparison result RST with a low voltage level when sampled signal V_SAMP is smaller than the reference analog voltage V_DA, so the bit data D_BIT generated by the logic control circuit13is logic “0”.

Then, the N-bit register14stores and output the bit data D_BIT to the digital to analog converter12, and the digital to analog converter12converts the bit data D_BIT into the discrete reference analog voltage V_DA to perform the next bit conversion cycle. Like wisely, once the analog to digital converter1has finished N-bit conversion cycle, the N-bit register14outputs the digital output signal D_OUT with paralleled N-bit to obtain the digital output code corresponding to the analog input signal V_IN.

FIG. 2illustrates a resolution curve and quantization error curve of an analog input signal with 0-1 volt,FIG. 3illustrates a conversion curve and a quantization error curve of an analog input signal with 0-5 volts. A real input voltage (e.g., the analog input signal V_IN) is denoted with a thick solid line, and an ideal transition voltage (e.g., the reference analog voltage V_DA) is denoted with a thin solid line. Given that the conversion bit number N is eight bits, and there are 256 (2^8) conversion digital codes. In ideal, the analog to digital converter1uniformly divides the reference voltage V_REF into 256 steps, each of the steps has the same voltage level range, wherein a resolution of each step is one LSB (least significant bit) and an averaged quantization error of each step is 0.5 LSB.

Table 1 illustrates resolution and averaged quantization error for analog input signals with voltage level 0-1 volt and 0-5 volts. As can be seen from Table 1, the voltage level of the analog input signal is positively proportional to the averaged quantization error. The averaged quantization error increases when the voltage level of the analog input signal increases. On the other hand, the averaged quantization error decreases when the voltage level of the analog input signal decreases.

Further, an error rate is a ratio of the averaged quantization error and the input voltage. InFIG. 2, the error rate is 9.75% (1.95 millivolts/20 millivolts=9.75%) if the voltage level of the analog input signal is 20 millivolts. In addition, the error rate is 0.205% (1.95 millivolts/950 millivolts=0.205%) if the voltage level of the analog input signal is 950 millivolts. As can be seen, the voltage level of the analog input signal is negatively proportional to the error rate. The error rate increases when the voltage level of the analog input signal decreases. On the other hand, the error rate decreases when the voltage level of the analog input signal increases.

When the voltage level of the analog input signal is greater than the conversion range of the analog to digital converter, the analog input signal must be attenuated before it is inputted to the analog to digital converter. In such a situation, since the voltage level of the analog input signal is attenuated, the error rate of the analog input signal is amplified. For example, given that the voltage level of the analog input signal V_IN is 0-5 Volts and the conversion range of the analog to digital converter1is 0-1 Volt, the analog input signal is attenuated by 1/5 times to be inputted to the analog to digital converter1. In such a situation, the error rate is amplified by 5 times when the analog input signal is attenuated by 1/5 times. Moreover, if there is noise mixed with the analog input signal to cause signal deformation of the analog signal with voltage level 0-1 Volt, it may not meet the requirement of high precision (i.e., low error rate).

FIG. 4is a functional block diagram of an analog to digital converter4with multi-stage conversion range4according to an embodiment of the present invention. The analog to digital converter4includes an amplifying circuit40and a microcontroller42. In this embodiment, the microcontroller42is built-in with the analog to digital converter1to perform analog to digital conversion to the analog input signal V_IN to generate a digital output signal D_OUT.

The amplifying circuit40is coupled to microcontroller42, and configured to perform signal simplification (or attenuation) to the analog input signal V_IN and generate control signals GPIO1, GPIO2and GPIO3according to different voltage level ranges and corresponding magnifications to output the amplified analog input signal V_IN and the control signals GPIO1, GPIO2and GPIO3to the microcontroller42. The microcontroller42performs analog to digital conversion to the amplified (or attenuated) analog input signal V_IN, and then recovers the analog input signal V_IN according to the control signals GPIO1, GPIO2and GPIO3to generate the digital code corresponding to the analog input signal V_IN. The amplifying circuit40includes operational amplifiers OP_AMP1, OP_AMP2and OP_AMP3, comparators COM1and COM2, switches SW1, SW2and SW3and a NOR Gate41.

The comparator COM1includes a positive input terminal, a negative input terminal and an output terminal. The positive input terminal receives a threshold voltage V_TH1, the negative input terminal receives an analog input signal V_IN, and the output terminal receives an output control signal GPIO1. The comparator COM1is coupled to the switch SW1, and configured to compare the analog input signal V_IN with the threshold voltage V_TH1to output the control signal GPIO1to the switch SW1. The operational amplifier OP_AMP1is configured to amplify the analog input signal V_IN according to a magnification AV1to generate an analog input signal V_IN_AMP1, wherein the magnification AV1is substantially greater than 1. The switch SW1is coupled to the comparator COM1, the operational amplifier OP_AMP1and the microcontroller42, and configured to connect the operational amplifier OP_AMP1with the microcontroller42or disconnect the operational amplifier OP_AMP1from the microcontroller42according to the control signal GPIO1, so as to control whether to input the analog input signal V_IN_AMP1to the microcontroller42.

The NOR Gate41includes a first input terminal, a second input terminal and an output terminal. The first input terminal receives the control signal GPIO1, the second input terminal receives the control signal GPIO3, and the output terminal outputs the control signal GPIO2. The NOR Gate41is coupled to the switch SW2, and configured to output the control signal GPIO2to the switch SW2according to the control signals GPIO1and GPIO3. The operational amplifier OP_AMP2is configured to amplify the analog input signal V_IN according to a magnification AV2to generate an analog input signal V_IN_AMP2, wherein the magnification AV2is substantially equal to 1. The switch SW2is coupled to the NOR Gate41, the operational amplifier OP_AMP2and the microcontroller42, and configured to connect the operational amplifier OP_AMP2with the microcontroller42or disconnect the operational amplifier OP_AMP2from the microcontroller42according to the control signal GPIO2, so as to control whether to input the analog input signal V_IN_AMP2to the microcontroller42.

The comparator COM3includes a positive input terminal, a negative input terminal and an output terminal. The positive input terminal receives the analog input signal V_IN, the negative input terminal receives a threshold voltage V_TH2, and the output terminal outputs the control signal GPIO3. The comparator COM3is coupled to the switch SW3, and configured to compare the analog input signal V_IN with the threshold voltage V_TH2to output the control signal GPIO3to the switch SW3. The operational amplifier OP_AMP3is configured to amplify the analog input signal V_IN according to a magnification AV3to generate an analog input signal V_IN_AMP3, wherein the magnification AV3is substantially smaller than 1. The switch SW3is coupled to the comparator COM3, the operational amplifier OP_AMP3and the microcontroller42, and configured to connect the operational amplifier OP_AMP3with microcontroller42or disconnect the operational amplifier OP_AMP3from the microcontroller42according to the control signal GPIO3, so as to control whether to input the analog input signal V_IN_AMP3to the microcontroller42.

Under the above mentioned structure, the present invention divides the analog input voltage into multiple voltage level ranges, and respectively performs signal amplification and attenuation based on different magnifications.

In detail, when the voltage level of the analog input signal V_IN is substantially smaller than threshold voltage V_TH1(V_IN<V_TH1), the operational amplifier OP_AMP1amplifies the analog input signal V_IN (by the magnification AV1>1) to generate the analog input signal V_IN_AMP1, and the control signal GPIO1generated by the comparator COM1is logic “1”. When the control signal GPIO1is logic “1”, the switch SW1connects the operational amplifier OP_AMP1and the microcontroller42to input the analog input signal V_IN_AMP1to the microcontroller42; while the microcontroller42performs analog to digital conversion to the analog input signal V_IN_AMP1, and then convert the digital code corresponding to the analog input signal V_IN_AMP1into the digital code corresponding to the analog input signal V_IN according to the reciprocal (1/AV1) of the magnification AV1. On the other hand, when the voltage level of the analog input signal V_IN is substantially greater than the threshold voltage V_TH1(V_IN>V_TH1), the control signal GPIO1generated by the comparator COM1is logic “0”. When the control signal GPIO1is logic “0”, the switch SW1disconnect the operational amplifier OP_AMP1from the microcontroller42to not input the analog input signal V_IN_AMP1to the microcontroller42, and thus the microcontroller42cannot perform analog to digital conversion to the analog input signal V_IN_AMP1.

When the voltage level of the analog input signal V_IN is substantially greater than the threshold voltage V_TH2(V_IN>V_TH2), the operational amplifier OP_AMP3attenuates the analog input signal V_IN (magnification AV3<1) to generate the analog input signal V_IN_AMP3, and the control signal GPIO3generated by the comparator COM2is logic “1”. When the control signal GPIO3is logic “1”, the switch SW3connects the operational amplifier OP_AMP3and the microcontroller42to input the analog input signal V_IN_AMP3to the microcontroller42; while the microcontroller42performs analog to digital conversion to the analog input signal V_IN_AMP3, and then convert the digital code corresponding to the analog input signal V_IN_AMP3into the digital code corresponding to the analog input signal V_IN according to the reciprocal (1/AV3) of the magnification AV3. On the other hand, When voltage level of the analog input signal V_IN is substantially smaller than the threshold voltage V_TH2(V_IN<V_TH2), the control signal GPIO3generated by the comparator COM2is logic “0”. When the control signal GPIO3is logic “0”, the switch SW3disconnects the operational amplifier OP_AMP3from the microcontroller42to not input the analog input signal V_IN_AMP3to the microcontroller42, and thus the microcontroller42cannot perform analog to digital conversion to the analog input signal V_IN_AMP3.

When the voltage level of the analog input signal V_IN is substantially greater than the threshold voltage V_TH1and smaller than the threshold voltage V_TH2(V_TH1<V_IN<V_TH2), the operational amplifier OP_AMP2maintains the analog input signal V_IN (magnification AV2=1) with the same to generate the analog input signal V_IN_AMP2, and the control signal GPIO2generated by the NOR Gate41is logic “1”, wherein both the control signals GPIO1and GPIO3are logic “0”. When the control signal GPIO2is logic “1”, the switch SW2connects the operational amplifier OP_AMP2and the microcontroller42to input the analog input signal V_IN_AMP2to the microcontroller42; while the microcontroller42performs analog to digital conversion to the analog input signal V_IN_AMP2, and then convert the digital code corresponding to the analog input signal V_IN_AMP2to the digital code corresponding to the analog input signal V_IN according to the reciprocal (1/AV2) of the magnification AV2. On the other hand, when the control signal GPIO2is logic “0”, the switch SW2disconnects the operational amplifier OP_AMP2from the microcontroller42to not input the analog input signal V_IN_AMP2to the microcontroller42, and thus the microcontroller42cannot perform analog to digital conversion to the analog input signal V_IN_AMP2.

As a result, the present invention divides the analog input voltage V_IN into multiple voltage level ranges (e.g., 0-VTH_1, V_TH1−V_TH2, V_TH2−V_MAX, wherein the V_MAX is a maximum voltage), and respectively performs signal amplification and attenuation based on different magnifications (e.g., AV1>1, AV2=1, AV3<1) to ensure the precision and quantization error of the input signal within low level range.

FIG. 5illustrates a resolution curve and quantization error curve of the analog to digital converter40, wherein a real input voltage (e.g., the analog input signal V_IN) is denoted with a thick solid line and an ideal transition voltage is denoted with a thin solid line. In this embodiment, given that the voltage level of the analog input signal V_IN is 0-5 volts, and a conversion range of the analog to digital converter built in the microcontroller42is 0-1.2 volts, which is not limited. Given that the threshold voltage V_TH1is substantially 0.5 volts, the threshold voltage V_TH2is substantially 1 volt, which is not limited. The magnification AV1corresponds to a voltage level range RNG1(e.g., 0-0.5 volts), the magnification AV2corresponds to a voltage level range RNG2(e.g., 0.5-1 volts), and magnification AV3corresponds to a voltage level range RNG3(e.g., 1-5 volts), which is not limited.

Take an 8-bit analog to digital conversion for example, Table 2 describes voltage level range/digital output range (hexadecimal notation), resolution and averaged quantization error corresponding to the analog input signal with voltage level 0-5 volts.

Compare with Table 1 and Table 2, the averaged quantization error corresponding to the voltage level range 0-0.5 volts decreases from 1.953 millivolts to 976.6 microvolts, the averaged quantization error corresponding to the voltage level range 0.5-1 is the same 1.953 millivolts, and the averaged quantization error corresponding to the voltage level range 1-5 volts is the same 9.765 millivolts, which means that the averaged quantization error corresponding to low level range is decreased and improved. In addition, the error rate is a ratio of the averaged quantization error and the input voltage, the error rate decreases when the averaged quantization error decreases to equivalently increase the precision. As a result, the analog to digital converter40of the present invention is adaptive to the analog input voltage with high voltage level, and precision and quantization error of the analog input voltage with low voltage level can be maintained as well.

Operations of the analog to digital converter40may be summarized into an analog to digital conversion process6, as shown inFIG. 6. The analog to digital conversion process6may be compiled into a program code and stored in the microcontroller42or a built-in memory of the microcontroller42for instructing the microcontroller42to perform signal amplification (or attenuation) and analog to digital conversion to the analog input signal, and then generate the corresponding digital code. The analog to digital conversion process6includes the following steps.

Step61: Determine a magnification according to a plurality of control signals.

Step62: Amplify an analog input signal according to the magnification to generate an amplified analog input signal.

Step63: Perform analog to digital conversion to the amplified analog input signal to generate an amplified digital code.

Step64: Generate an output digital code according to a reciprocal of the magnification and the amplified digital code.

Detailed descriptions of the analog to digital conversion process6may be obtained by referring to descriptions of the analog to digital converter40, which is omitted.

To sum up, the present invention divides the analog input voltage into multiple voltage level ranges, respectively performs signal amplification and attenuation based on different magnifications, and computes the digital codes corresponding to the analog input voltage according to the magnifications. As a result, the analog to digital converter is adaptive to the analog input voltage with high voltage level, and precision and quantization error of the analog input voltage with low voltage level can be maintained as well.