Magnetic storage apparatus and manufacturing method thereof

Problems in reliability and cross-talk of MRAM, which are intrinsically ascribable to the structure thereof, are solved at the same time. In a magnetic storage device (1) having write word lines (11) and bit lines (12) formed so as to cross while keeping a predetermined space therebetween, and provided with a TMR element (13) configured so as to sandwich a tunnel insulating layer (303) with a magnetization fixed layer (302) and a storage layer (304) comprising a ferromagnetic layer, in each of thus-formed intersectional region, and there is provided a semiconductor region (22) in which two read transistors (24, 24), which serve as read transistors, are formed, and which comprises a first region (22a) obliquely crosses a projected region of the write word line (11); a second region (22b) formed in parallel with the bit line (12) so as to be continued from one end of the first region; and a third region (22c) formed in parallel with the bit line (12) and so as to be continued from the other end of the first region (22a).

BACKGROUND OF THE INVENTION

The present invention relates to a magnetic storage device and a method of fabricating the same, and more specifically to a non-volatile magnetic storage device configured so as to store information in response to changes in resistance value depending on parallel or antiparallel alignment of spin of a ferromagnetic material composing a tunnel magnetoresistance element, and a method of fabricating the same.

With a dramatic popularization of information communication instruments in particular of mobile terminals, there are increasing demands for further advanced performances of elements such as memory elements and logic elements, with regard to higher degree of integration, higher speed, and lower power consumption. In particular, non-volatile memory is considered as an indispensable element in the ubiquitous era.

For example, non-volatile memory can protect important personal information even when exhaustion or any troubles occurred in power supply, or when a server and a network were disconnected due to some failure. Upgrading of the degree of integration or capacity of the non-volatile memory are thus increasingly adds its importance as a technology for providing alternatives for hard disks and optical disks which cannot be downsized by nature due to involvement of movable sections.

Meanwhile, recent mobile instruments are designed so as to suppress power consumption as possible by bringing unnecessary circuit blocks into stand-by status, but realization of a non-volatile memory capable of working both as a high-speed network memory and a high-capacity storage memory can expel any waste in power consumption and memory. So-called “Instant-On” function, which enables instantaneous activation upon power ON, can also be realized if the high-speed, large-capacity, non-volatile memory comes true.

Known non-volatile memories include flash memory using semiconductor, and FRAM (ferroelectric random access memory) using ferroelectric material. The flash memory, however, suffers from a problem that it is hard to be integrated to a large degree due to its complicated structure, and that it has only a write speed as slow as having an order of microsecond. It has also been pointed out as for FRAM that it has a number of times of rewriting of only as small as 1012to 1014times, indicating that it is too less durable to completely replace a static random access memory or a dynamic random access memory. Difficulty in microprocessing of the ferroelectric capacitor is also pointed out as a problem.

What is attracting a public attention as non-volatile memories free from these drawbacks is magnetic memory which is called as MRAM (Magnetic Random Access Memory) or simply as MR (Magneto resistance) memory, as described by Wang et al. in IEEE Trans. Magn., 33 (1997), p.4498, which is becoming more focused with progress in characteristics of TMR (Tunnel Magnetoresistance) material.

MRAM can easily be increased in the degree of integration by virtue of its simple structure, and is expected to be increased in the number of times of rewriting because the recording is based on rotation of magnetic moment. The access speed thereof is also expected to be very rapid, and R. Scheuerlein et al. have already reported in ISSCC Digest of Papers (February 2000), p. 128-129 that it was operable at 100 MHz.

Recording in MRAM is made effective based on rotation of a current magnetic field in a recording layer induced by current supplied to the wirings. Higher integration and consequently thinned wirings, however, inevitably reduce critical current value allowable by a write line to thereby weaken an obtainable magnetic field, and this unwillingly decreases coercive force of a recordable region. This means decrease in reliability of the information recording element. Moreover, a magnetic field cannot be condensed unlike light or electron beam, and this may possibly be a major cause for cross-talk in a case of a highly-integrated element.

To solve these problems in the reliability and cross-talk at the same time, it is essential, even under a highly integrated status, to ensure a sufficient width both for bit lines and write word lines crossing at a right angle to each other, both of which are magnetic field applying means for applying a magnetic field to ferromagnetic tunnel junction, where an optimum shield structure for suppressing a leakage magnetic field becomes also necessary.

A subject to be solved by the present invention therefore is to solve problems in reliability and cross-talk of MRAM, which are intrinsically ascribable to the structure thereof, at the same time.

SUMMARY OF THE INVENTION

The present invention relates to a magnetic storage device and a method of fabricating the same conceived to solve the aforementioned subject.

The magnetic storage device of the present invention is such as comprising a write word line; a bit line formed so as to cross the write word line while keeping a predetermined space therebetween; a magnetic storage element composed so that a tunnel insulating film is sandwiched by ferromagnetic material layers, and disposed at an intersectional region of the write word line and the bit line; and a connection layer containing an antiferromagnetic material layer formed on the write word line side of the magnetic storage element, characterized in having a semiconductor region in which two read transistors are formed, and which comprises a first region obliquely crosses a projected region of the write word line; a second region formed in parallel with the bit line so as to be continued from one end of the first region; and a third region formed in parallel with the bit line so as to be continued from the other end of the first region.

In the above-described semiconductor magnetic storage device, because the semiconductor region in which two read transistors are formed comprises the first region obliquely crosses a projected region of the write word line; the second region formed in parallel with the bit line so as to be continued from one end of the first region; and the third region formed in parallel with the bit line so as to be continued from the other end of the first region, storage cells which individually comprise the magnetic storage element and connection layer can be arranged to be shifted by 1/2n (where, n represents a natural number of 1 or larger) pitches in an oblique direction away from the extending direction of the write word line, even when the cell is designed so that the magnetic storage element is arranged in the intersectional region of the bit line and write word line, and so that the connection layer is connected to the end portion of the semiconductor region.

Moreover, one end portion of each of a plurality of semiconductor regions which compose a second semiconductor region array adjacent to a first semiconductor region array comprising a plurality of the semiconductor regions arranged in the extending direction of the write word line can be arranged one by one between the individual semiconductor regions in the first semiconductor region array on the second semiconductor region array side.

Accordingly, this makes it possible to isolate the semiconductor regions in which the read transistors are to be made, using the element isolation regions in an effective manner, while avoiding waste in terms of occupied area. It is also made possible to reduce contact holes for connecting the diffusion layers of the read transistors and the bit lines without causing short-circuiting of the individual semiconductor regions, and this makes it possible to avoid short-circuiting between the semiconductor regions even if the storage cells are further down-sized as compared with the contact holes.

The method of fabricating a semiconductor magnetic storage device of the present invention is such as fabricating an information storage device comprising magnetic storage devices each of which having a tunnel magnetoresistance element composed so that a tunnel insulating layer is sandwiched by ferromagnetic layers, disposed at an intersectional region of a write word line and a bit line which cross with each other while keeping a predetermined space therebetween, and configured so as to store information in response to changes in the resistivity depending on parallel or antiparallel alignment of spin of the ferromagnetic material layer; characterized in having a step of forming an element isolation region for partitioning a semiconductor region in which two read transistors are formed, and comprises a first region obliquely crosses a projected region of an expected region in which the write word line will be formed later; a second region formed in parallel with the bit line so as to be continued from one end of the first region; and a third region formed in parallel with the bit line so as to be continued from the other end of the first region; a step of forming gate electrodes on the semiconductor region in parallel with the expected region in which the write word line will be formed later while placing a gate insulating film in between, and of forming a pair of diffusion layers in the semiconductor region on both sides of the gate electrodes so that the first region of the semiconductor region can serve as a common diffusion layer, to thereby configure two read transistors; a step of forming a first insulating film so as to cover the two read transistors; a step of forming a power supply line so as to be connected with the common diffusion layer for the two read transistors, and in parallel with the expected region in which the write word line will be formed later; a step of forming a second insulating film so as to cover the power supply line; a step of forming, on the second insulating film, the write word line for applying magnetic field to the magnetic storage element; a step of forming a third insulating film so as to cover the write word line; a step of forming contact portions penetrating the third insulating film through the first insulating film, so as to be connected to each of two diffusion layers other than the common diffusion layer composing the two read transistors; a step of forming, on the third insulating film, a connection layer including antiferromagnetic material layer so as to be connected to each of the contact portions, and of forming a magnetic storage element having a ferromagnetic tunnel junction composed so that a tunnel insulating film is sandwiched by ferromagnetic layers; a step of forming a fourth insulating film so as to cover the magnetic storage element; and a step of forming, on the fourth insulating film, a bit line so as to be connected to the magnetic storage element, and so as to cross at a right angle to the write word line.

In the method of fabricating a magnetic storage device of the present invention, because the semiconductor region in which two read transistors are formed comprises the first region obliquely crosses a projected region of the write word line; the second region formed in parallel with the bit line so as to be continued from one end of the first region; and the third region formed in parallel with the bit line so as to be continued from the other end of the first region, storage cells which individually comprise the magnetic storage element and connection layer can be arranged so as to be shifted by 1/2n (where, n represents a natural number of 1 or larger) pitches in an oblique direction away from the extending direction of the write word line, even when the cell is designed so that the magnetic storage element is arranged in the intersectional region of the bit line and write word line, and so that the connection layer is connected to the end portion of the semiconductor region.

Moreover, one end portion of each of a plurality of semiconductor regions which compose a second semiconductor region array adjacent to a first semiconductor region array comprising a plurality of the semiconductor regions arranged in the extending direction of the write word line can be arranged one by one between the individual semiconductor regions in the first semiconductor region array on the second semiconductor region array side. This makes it possible to effectively layout the semiconductor regions in which the read transistors are to be made while avoiding waste in terms of occupied area.

This also solves the problem of cross-talk because distance between the individual magnetic storage elements and distance between the individual write word lines can be ensured to a sufficient degree.

DETAILED DESCRIPTION OF THE PRESENTLY PREFERRED EMBODIMENTS

First, a general MRAM (Magnetic Random Access Memory) will be explained referring toFIG. 3which is a schematic structural perspective view showing an essential portion thereof in a simplified manner. InFIG. 3, illustration of the read-out circuit portion is omitted for simplicity.

It includes nine memory cells, as can be seen inFIG. 3, where write word lines11(111,112,113) and bit lines12(121,122,123) are disposed so as to cross with each other. At intersectional regions of the write word lines11and the bit lines12, magnetoresistance effect (TMR) elements13(131to139) are disposed as magnetic storage elements. Write operation to the TMR elements13are accomplished by allowing electric current to flow in the bit lines12and the write word lines11, and changing the direction of magnetization of the storage layer304(seeFIG. 6for detail) of the TMR elements13, formed at the intersections between the bit lines12and the write word lines11, into parallel or antiparallel with respect to a magnetization fixed layer302(seeFIG. 6for detail) in response to a synthetic magnetic field created by the lines.

The asteroid curve shown inFIG. 4shows inversion threshold value in a direction of magnetization of a storage layer affected by a magnetic field in the easy axis direction HEAand a magnetic field in the hard axis direction HHA. The magnetic field will invert when any synthetic magnetic field vector which falls in the area outside the asteroid curve occurs. A synthetic magnetic field vector which falls within the asteroid curve will never result in inversion of the cell from either one of the current bistable statuses. In addition, because also the cells, other than those at the intersections where both of word lines and bit lines are supplied with electric current, are applied with the magnetic field generated solely by the word lines or bit lines, and because also the cells other than those in the intersections will cause inversion of the magnetization direction, if intensity of the magnetic field exceeds a unidirectional inversion magnetic field HK, selective writing to the selected cells is available only when the synthetic magnetic field falls within a hatched region401.

As has been described in the above, memory cells in the MRAM array are arranged at the intersections of a grid composed of the bit lines and write word lines. It is a general practice for MRAM to enable selective write operation to the individual memory cells based on magnetic inversion property by using the write word lines and bit lines.

Synthetic magnetization at a single storage region can be determined by vector synthesis of a magnetic field in the easy axis direction (HEA) and a magnetic field in the hard axis direction (HHA) applied thereto. Electric current flowing in the bit line applies the magnetic field in the easy axis direction (HEA) to the cell, and electric current flowing in the write word line applies the magnetic field in the hard axis direction (HHA).

Documents (R. H. Koch et al., Phys. Rev. Lett. 84 (2000), p.5419; and J. Z. Sun et al., Joint Magnetism and Magnetic Material 8 (2001)) disclose that “assistance of magnetic inversion by elevating temperature can successfully lower the inversion magnetic field HSWin the hard axis direction”. Therefore also for the magnetic storage device of the present invention, it is effective to elevate the temperature to a degree not adversely affective to the elements.

Next, a principle circuit of the MRAM explained in the above referring toFIG. 3will be explained referring to a circuit diagram in FIG.5.

As shown inFIG. 5, the MRAM circuit includes six memory cells, and has write word lines11(111,112) and bit lines12(121,122,123), which correspond to those shown inFIG. 3, crossing with each other. At the intersections of the write word lines11and the bit lines12, TMR elements13(131,132,134,135,137,138) which serve as storage elements are disposed, and further to the individual storage elements, field-effect transistors141,142,144,145,147,148for selecting elements to be read are connected. To the field-effect transistors141,144,147, a sense line151is connected, and to the field-effect transistors142,145,148, a sense line152is connected.

The sense line151is connected to a sense amplifier153, and the sense line152is connected to a sense amplifier154, so as to allow detection of information stored in the individual elements. On both ends of the write word line111, bidirectional write-word-line current supply circuits161,162are connected, and on both ends of the write word line112, bidirectional write-word-line current drive circuits163,164are connected. Moreover, on one end of the bit line121a bit-line current drive circuit171is connected, on one end of the bit line122a bit-line current drive circuit172is connected, and on one end of the bit line123a bit-line current drive circuit173is connected.

Next, a basic constitution of the magnetic storage device will be explained below. First, the tunnel magnetoresistance element (referred to as TMR element, hereinafter) which serves as a storage element of the memory cell will be explained referring to a perspective view in FIG.6.

As shown inFIG. 6, the magnetic storage device (TMR element)13is basically configured so as to sandwich a tunnel insulating layer303with a magnetization fixed layer302, which comprises a ferromagnetic material and has a fixed magnetization, and a storage layer304, which comprises a ferromagnetic material and can readily rotates the magnetization.

In an exemplary case shown inFIG. 6, an underlying electrode layer312is formed on a support substrate311, and further thereon an antiferromagnetic material layer305is formed. Further thereon, the above-mentioned magnetization fixed layer302, the above-mentioned tunnel insulating layer303and the above-mentioned storage layer304are sequentially stacked. The magnetization fixed layer302further comprises a first magnetization fixed layer306and a second magnetization fixed layer308, and between the first and second magnetization fixed layers306,308, a conductive material layer307such as allowing a magnetic layer to be coupled in an antiferromagnetic manner is disposed.

The above-mentioned underlying electrode layer312is used for connection with a switching element serially connected with the TMR element13, and may be composed so as to function also as an antiferromagnetic material layer305. In thus-configured cell, information is read out by detecting changes in tunnel current due to magnetoresistance effect, where effect thereof depends on a relative magnetization direction between the storage layer304and the magnetization fixed layer302.

The above-mentioned storage layer304, the above-mentioned first magnetization fixed layer306and the above-mentioned second magnetization fixed layer308are individually composed of a ferromagnetic material, and are typically composed of nickel, iron, cobalt, or an alloy composed of at least two elements selected from nickel, iron and cobalt.

The above-mentioned conductive material layer307is typically composed of ruthenium, copper, chromium, gold, silver or the like.

The first magnetization fixed layer306is formed so as to contact with the antiferromagnetic material layer305, and has a strong unidirectional magnetic anisotropy due to exchange interaction exerted between these layers.

The above-mentioned tunnel insulating layer303is typically composed of aluminum oxide, magnesium oxide, silicon oxide, aluminum nitride, magnesium nitride, silicon nitride, aluminum oxynitride, magnesium oxynitride or silicon oxynitride. The tunnel insulating layer303has a function of disconnecting magnetic coupling between the above-mentioned storage layer304and the above-mentioned magnetization fixed layer302, and of allowing tunnel current to flow. These magnetic films and conductive material films are typically formed by the sputtering process. The tunnel insulating layer303can be obtained by oxidizing, nitrifying or oxidizing-nitrifying a metal film formed by the sputtering process.

Furthermore, on the uppermost layer, a top-coat film313is formed. The top-coat film313has a function of preventing inter-diffusion between the TMR element13and a wiring used for connecting other TMR element13, reducing the contact resistance, and preventing oxidation of the storage layer304. It is generally composed of a material such as tantalum nitride, tantalum, titanium nitride or the like. The underlying electrode layer312is used for connection with a switching element serially connected with the TMR element, and may be composed so as to function also as the above-mentioned antiferromagnetic material layer305.

In thus-configured TMR element13, information is read out by detecting changes in tunnel current based on magnetoresistance effect, where effect thereof depends on relative magnetization direction among the storage layer304, and the first and second magnetization fixed layers306,308.

The above-mentioned magnetic layers and conductive material layers are typically formed by the sputtering process, ALD (atomic layer deposition) process or the like, and a tunnel barrier layer can be obtained also by oxidizing or nitrifying a metal film formed by the sputtering process as described in the above.

Next, one embodiment of the magnetic storage device of the present invention will be explained referring to FIG.1andFIGS. 2Ato2C. These drawings indicate the magnetic storage device having storage cells which are arranged so as to be shifted by 1/4 pitches, where drawing (a) inFIG. 1shows a sectional view taken along the line X-X′ in the layout drawings shown inFIGS. 2Ato2B, and drawing (b) inFIG. 1shows a sectional view taken along the line Y-Y′ in the layout drawings shown in FIG.2. Drawing A ofFIG. 2illustrates the semiconductor regions,FIG. 2Billustrates the read transistors, sense line and so forth, andFIG. 2Cshows a layout drawing of write word lines, TMR elements, bit lines and so forth.

As seen inFIG. 1, on a top surface side of a semiconductor substrate (p-type semiconductor substrate, for example), a plurality of semiconductor regions22which are isolated by element isolation regions23and comprise p-type well regions are formed. The above-mentioned element isolation regions23are formed by so-called STI (shallow trench isolation) technology.

Each of the above-mentioned semiconductor regions22has two electrolysis-type transistors24,24which serve as read transistors, and each of which comprises a first region22aobliquely crosses a projected region on the semiconductor substrate21of the write word line11described later); a second region22bformed in parallel with the bit line12so as to be continued from one end of the first region; and a third region22cformed in parallel with the bit line12and so as to be continued from the other end of the first region22a. Moreover, one end portion of each of a plurality of semiconductor regions22which compose a second semiconductor region array22v2adjacent to a first semiconductor region array22v1comprising a plurality of the semiconductor regions22arranged in the extending direction of the write word line11are arranged one by one between the individual semiconductor regions22in the first semiconductor region array22v1on the second semiconductor region array22v2side.

On each of the above-mentioned semiconductor regions22in the individual arrays arranged in a direction y in the drawing, two gate electrodes (read word line)26(26a),26(26b) are formed while being interposed by a gate insulating film25, diffusion layer regions (N+diffusion layer regions, for example)27,28are formed in the semiconductor regions22on both sides of the gate electrode26a, and diffusion layer regions (N+diffusion layer regions, for example)28,29are formed in the semiconductor regions22on both sides of the gate electrode26b, so as to configure two field-effect transistors24(24a),24(24b). Incidentally, the diffusion layer region28is provided as a common diffusion layer region for the field-effect transistors24a,24b.

The above-mentioned field-effect transistors24function as switching elements for read operation. Besides n-type and p-type field-effect transistors, it is also allowable to use other various switching elements such as diodes and bipolar transistors.

A first insulating film41is formed so as to cover each of the above-mentioned field-effect transistors24. As shown in the drawings, the surface of the first insulating film41is preferably planarized. In the first insulating film41, contacts30for making contact to the above-mentioned diffusion layer region28are formed. On the first insulating film41, sense lines (power supply lines)15connected to the contacts30are formed.

Further so as to cover the sense lines15, a second insulating film42is formed. As shown in the drawings, the surface of the second insulating film42is preferably planarized. Further on the above-mentioned second insulating film42, the write word lines11are formed so as to lie over the above-mentioned sense lines15and in parallel therewith.

On the above-mentioned second insulating film42, a third insulating film43is formed so as to cover the above-mentioned write word lines11. The surface of the third insulating film43is preferably planarized. In these third to first insulating films43to41, contact portions37connected to the above-mentioned semiconductor regions22are arranged in parallel with the above-mentioned write word lines11.

On the above-mentioned third insulating film43, connection layers31are formed using an antiferromagnetic material layer305so as to extend from areas over the above-mentioned write word lines11and to be connected to the upper end portions of the above-mentioned contact portions37. Further on the above-mentioned antiferromagnetic material layer305and over the above-mentioned write word lines11, TMR elements13are formed. Each of the TMR elements13is configured, as previously explained referring toFIG. 6, by sequentially stacking, on the antiferromagnetic material layer305, the magnetization fixed layer302having the first magnetization fixed layer306, the conductive material layer307such as allowing a magnetic layer to be coupled in an antiferromagnetic manner and the second magnetization fixed layer308; the tunnel insulating layer303; the storage layer304; and top-coat layer313in this order. Materials for composing the TMR element13are such as those previously explained referring to FIG.6.

Storage cells41individually composed of the above-mentioned TMR element13and the above-mentioned connection layer31are disposed at the intersections of the individual write word lines11and the individual bit lines12, where the individual storage cells41are arranged so as to be shifted by 1/2n (where, n represents a natural number of 1 or larger) pitches in an oblique direction away from the extending direction of the above-mentioned write word line11.

On the above-mentioned third insulating film43, a fourth insulating film44is formed so as to cover the above-mentioned antiferromagnetic material layer305, the TMR elements13and the like. The top surface of the fourth insulating film44is planarized so as to expose the uppermost layer of the above-mentioned TMR elements13. On the above-mentioned fourth insulating film44, the bit lines12are formed so as to be connected to the upper surface of the above-mentioned TMR elements13and to three-dimensionally cross (at right angles for example) the above-mentioned write word lines11while placing the above-mentioned TMR elements13in between.

The above-mentioned write word lines11, sense lines15, bit lines12and the like can be formed using any materials available for semiconductor devices, where examples of which include aluminum, aluminum alloy, copper, copper alloy, conductive polysilicon; refractory metals such as tungsten, molybdenum, rhodium and nickel; and refractory metal silicides such as tungsten silicide and cobalt silicide.

In the above-mentioned magnetic storage device1, each of the semiconductor regions22in which two field-effect transistors24,24, which serve as read transistors, comprises the first region22aobliquely crosses the projected region of the write word line11; the second region22bformed in parallel with the bit line12so as to be continued from one end of the first region22a; and the third region22cformed in parallel with the bit line12and so as to be continued from the other end of the above-mentioned first region22a, so that the storage cells41, each of which comprises the TMR element13and the connection layer31, can be arranged so as to be shifted by 1/2n (where, n represents a natural number of 1 or larger) pitches in an oblique direction away from the extending direction of the write word line, even if the TMR elements13are arranged in the intersectional regions of the bit lines12and write word lines11, and so that the connection layers31are connected to the end portions of the semiconductor regions22.

Moreover, this makes it possible to locate one end portion of each of a plurality of semiconductor regions22, which compose the second semiconductor region array22v2adjacent to the first semiconductor region array22v1comprising a plurality of the semiconductor regions22arranged in the extending direction of the write word line11, one by one between the individual semiconductor regions22in the first semiconductor region array22v1on the second semiconductor region array22v2side.

This makes it possible to isolate the semiconductor regions22in which the field effect transistors serving as the read transistors24,24are to be made using the element isolation regions23in an effective manner, while avoiding waste in terms of occupied area. It is also made possible to reduce the cell area because the sense lines15and the write word lines11are stacked while placing the second insulating film42in between. It is still also possible to solve a problem of cross-talk because the distance between the TMR elements13and between the write word lines11can be ensured to a sufficient level.

Next, the method of fabricating the semiconductor device of the present invention will be explained referring to sectional views showing process steps, layout drawings and the like inFIGS. 7Ato11C. In these drawings,FIGS. 7Ato11A show the layout drawings,FIGS. 7Bto11B show sectional views taken along the line X-X′ inFIGS. 7Ato11A, andFIGS. 7Cto11C show sectional views taken along the line Y-Y′ inFIGS. 7Ato11A. The method of fabrication described herein is such as fabricating a magnetic storage device in which storage cells are arranged to be shifted by 1/2n pitches.

As shown inFIGS. 7Ato7C, the element isolation regions23are formed in the semiconductor substrate21typically by the STI (shallow trench isolation) technology so as to isolate the semiconductor regions22in each of which two read transistors are to be formed. Each of the semiconductor regions22typically comprises the first region22aobliquely crosses a projected region of an expected region (indicated by two-dot chain line) in which the write word line will be formed later; the second region22bformed in parallel with the bit line which will be formed later, and so as to be continued from one end of the above-mentioned first region22a; and the third region22cformed in parallel with the bit line and so as to be continued from the other end of the above-mentioned first region22a.

Moreover, one end portion of each of a plurality of semiconductor regions22which compose a second semiconductor region array22v2adjacent to a first semiconductor region array22v1comprising a plurality of the semiconductor regions22arranged in the extending direction of the write word line11are arranged one by one between the above-mentioned individual semiconductor regions22in the first semiconductor region array22v1on the second semiconductor region array22v2side.

Next, as shown inFIGS. 8Ato8C, the gate electrodes26(26a),26(26b) are formed on the semiconductor regions22while placing the gate insulating film25in between on both sides of, and in parallel with, an expected region11ein which the above-mentioned write word line will be formed later, according to general techniques for fabricating insulated-gate, field-effect transistors. The diffusion layers27,28,29are then formed in the semiconductor regions22on both sides of two gate electrodes26,26. Among these, the diffusion layer28formed in the first region22abetween the gate electrodes26,26serves as a common diffusion layer for two read transistors. Thus the field-effect transistors24(24a),24(24b), which are two read transistors, are formed in the semiconductor regions22.

Next, as shown inFIGS. 9Ato9C, the first insulating film41is formed on the semiconductor substrate21so as to cover the field-effect transistors24which serve as the above-mentioned read transistors, using a technique for depositing insulating films such as the chemical vapor deposition process. The surface of the first insulating film41is preferably planarized by a planarization technique such as chemical mechanical polishing while keeping the gate electrodes26not exposed.

Next, after the contacts30to be connected to the common diffusion layers28of the individual field-effect transistors24which serves as the above-mentioned read transistors are formed in the above-mentioned first insulating film41, on the above-mentioned first insulating film41, the sense lines (power supply lines)15are formed so as to be connected with the above-mentioned contacts30in parallel with the expected regions in which the write word lines are formed later. Methods for forming the sense lines15may be similar to those in general wiring formation, where, for example, after a conductive material film is formed on the first insulating film41, the above-mentioned conductive material film is patterned to obtain a predetermined wiring form using lithography, etching techniques, or the like.

Furthermore, as shown inFIGS. 10Ato10C, the second insulating film42which covers the above-mentioned sense lines15is formed on the above-mentioned first insulating film41using silicon oxide or aluminum oxide according to a technique for depositing insulating films such as the chemical vapor deposition process. The surface of the second insulating film42is preferably planarized typically by a planarization technique such as chemical mechanical polishing, so as to leave the film in a thickness of 700 nm or around on the sense lines15.

On the aforementioned second insulating film42, the write word lines11for applying a magnetic field to the TMR elements which will be formed later are formed along the above-mentioned sense lines15. Methods for forming the write word lines11may be similar to those in general wiring formation, where, for example, after a conductive material film is formed on the second insulating film42, the above-mentioned conductive material film is patterned to obtain a predetermined wiring form using lithography, etching techniques or the like.

In a possible method for forming the write word lines11over the sense lines15by a lithographic technique without causing misalignment, the above-mentioned contact portions (not shown) are formed first, a conductive material film for forming the sense lines is formed on the first insulating film41, the second insulating film42is formed, and a conductive material film for forming the write word lines11is formed. Thereafter, the second insulating film42and two conductive material films sandwiching the insulating film are then patterned to obtain a predetermined form of the write word lines using lithography and etching techniques, to thereby successfully form the write word lines11and the sense lines15stacked with each other while placing the second insulating film42in between.

Next, the third insulating film42is formed so as to cover the above-mentioned write word lines11. The surface of the third insulating film43is preferably planarized by a planarization technique such as chemical mechanical polishing. It is to be noted that for s case where the write word lines11and the sense lines15are concomitantly patterned, the above-mentioned third insulating film43is formed on the above-mentioned first insulating film41so as to cover the write word lines11and the sense lines15.

In other method, a P-TEOS (plasma tetra-ethoxysilane) film of 100 nm thick, an HDP (high density plasma CVD) film of 800 nm thick and a P-TEOS film of 1200 nm thick are sequentially deposited on the above-mentioned sense lines15, and are then planarized by chemical mechanical polishing so as to leave the second insulating film42in a thickness of 700 nm on the sense lines15. Then a P-SiN (plasma silicon nitride) film is deposited to a thickness of 20 nm, and via holes (not shown) are formed in the film by photolithography and etching techniques. Then a P-TEOS film is deposited to a thickness of 300 nm, and the interlayer silicon oxide film is etched using a photoresist as a mask under a condition where a large SiO2/P-SiN etching selection ratio can be ensured, so as to concomitantly form the via holes and wiring grooves in which the write word lines to be formed. Next, a barrier layer (e.g., a Ti film of 5 nm thick and a TiN film of 20 nm thick as viewed from the bottom) is formed on an inner surface of the via holes and the wiring grooves by the PVD (physical vapor deposition) process, and the via holes and the wiring grooves are then filled with a tungsten film by the CVD process. Thereafter, the excessive portion of the tungsten film on the silicon oxide film is removed to thereby form the write word lines11and the contact portions (not shown) connected thereto. A P-TEOS film is then deposited to a thickness of 100 nm for example, to thereby form the third insulating film43on the above-mentioned second insulating film. The surface of the third insulating film43is desirably planarized because the P-TEOS film deposited to as thick as 100 nm is formed on the planarized surface.

Although the tungsten deposited by the chemical vapor deposition process was used in the above exemplary process for fabricating the write word lines11based on the groove wiring technique, it is also allowable to form them by depositing iridium, osmium, chromium, zirconium, tungsten, tantalum, titanium thorium, vanadium, molybdenum, rhodium, nickel, ruthenium or alloys thereof by sputtering or the chemical vapor deposition process.

The write word line may partially be thinned around a portion directly under the TMR in order to raise the resistivity, or may be planarized for more efficient heat dissipation.

Next, the contact portions37penetrating from the above-mentioned third insulating film43through the above-mentioned first insulating film41are formed so as to make contact to each of two diffusion layers27,29other than the common diffusion layer28composing the above-mentioned two field-effect transistors24,24which serve as read transistors. The above-mentioned contact portions37herein are formed to be arranged in parallel with the above-mentioned write word lines11.

Next, as shown inFIG. 11, the material layers composing the TMR elements13, previously explained referring toFIG. 6, are deposited typically by the PVD process.

For example, the underlying electrode layer312is formed, and the antiferromagnetic material layer305is formed thereon. Further thereon, the above-mentioned magnetization fixed layer302, the above-mentioned tunnel insulating layer303and the above-mentioned storage layer304are sequentially stacked. The magnetization fixed layer302is formed by stacking the first magnetization fixed layer306, the conductive material layer307such as allowing a magnetic layer to be coupled in an antiferromagnetic manner, and the second magnetization fixed layer308in this order from the bottom.

For example, material layers for forming the aforementioned individual layers are stacked, and the stacked film is then processed by reactive ion etching technique using a photoresist mask to thereby form the TMR elements13. The etching proceeds from the tunnel insulating layer303which comprises an aluminum oxide film and ends in midway of the lowermost antiferromagnetic layer305. Etching gas available herein is a chlorine-containing halogen gas, or a gas system added with carbon monoxide (CO) or ammonia (NH3), or the like. Next, using a photoresist mask, the residual stacked film is processed by reactive ion etching, to thereby form the connection layers31for connecting the TMR elements13and the contact portions37, using a part of the above-mentioned stacked film.

In the above-mentioned TMR element, as an example, the underlying electrode layer312is used for connection with a switching element serially connected with the TMR element13, and is composed using titanium nitride, tantalum, tantalum nitride or the like. The antiferromagnetic material layer305is typically, for example, composed of iron-manganese alloy, nickel-manganese alloy, platinum-manganese alloy, iridium-manganese alloy, rhodium-manganese alloy, cobalt oxide, nickel oxide or the like. It is also allowable for the antiferromagnetic material layer305to serve as the underlying electrode layer312.

The first magnetization fixed layer306is formed so as to contact with the antiferromagnetic material layer305, and has a strong unidirectional magnetic anisotropy based on exchange interaction exerted between these layers.

The tunnel insulating layer303is typically composed of aluminum oxide, magnesium oxide, silicon oxide, aluminum nitride, magnesium nitride, silicon nitride, aluminum oxynitride, magnesium oxynitride or silicon oxynitride. The thickness thereof is extremely as thin as 0.5 nm to 5 nm. Therefore, it is formed by the ALD (atomic layer deposition) process, or by depositing aluminum by sputtering and then oxidizing it in plasma. The tunnel insulating layer303has a function of disconnecting magnetic coupling between the storage layer304and the magnetization fixed layer302, and of allowing tunnel current to flow.

The above-mentioned storage layer304and the above-mentioned first and second magnetization fixed layers306,308are composed of ferromagnetic materials, and are formed typically using nickel, iron or cobalt, or an alloy composed of at least any two of nickel, iron and cobalt. The thickness of the above-mentioned first and second magnetization fixed layers306,308are generally set to 0.5 nm to 5 nm. The conductive material layer307is formed using ruthenium, copper, chromium, gold, silver or the like. It is possible to change the direction of magnetization of this layer parallel to or antiparallel to that of the underlying ferromagnetic material layer upon being applied with an external magnetic field.

These magnetic films and conductive films are formed mainly by the sputtering process or the ALD process. They can be formed also by oxidizing, nitrifying or oxidizing-nitrifying a metal film formed by the sputtering process.

On the uppermost layer, a top-coat film313is formed. The top-coat film313has a function of preventing inter-diffusion between the TMR element13and a wiring used for connecting other TMR element13, reducing the contact resistance, and preventing oxidation of the storage layer304. It is generally composed of a material such as tantalum nitride, tantalum, titanium nitride or the like.

The connection layer31including the underlying electrode layer312is used for connection with the field-effect transistor24which is a read transistor serving as a switching element serially connected to the TMR element13, and may be composed so as to function also as the above-mentioned antiferromagnetic material layer305.

Moreover, as shown in the drawings, when a plurality of storage cells41composed of thus-configured TMR elements13and the above-mentioned connection layers31are formed, the plurality of storage cells are arranged so as to be shifted by 1/2n (where, n represents a natural number of 1 or larger) pitches in an oblique direction away from the extending direction of the write word lines11.

Next, on the above-mentioned third insulating film43, the fourth insulating film44is formed typically by the chemical vapor deposition process so as to cover the above-mentioned TMR elements13. The fourth insulating film44is first formed by depositing an insulating film such as being composed of silicon oxide or aluminum oxide or the like over the entire surface typically by the CVD or PVD process, and is then planarized typically by chemical mechanical polishing so as to make the top-coat films313of the TMR elements13exposed.

Then according to the standardized wiring formation techniques, the bit lines12and other wirings for peripheral circuits (not shown) are formed. The above-mentioned bit lines12are formed so as to be connected to the above-mentioned TMR elements13and to cross with a right angle to the above-mentioned write word lines11.

Next, a plasma silicon nitride (P-SiN) film (not shown) is deposited typically by the chemical vapor deposition process over the entire surface, and openings are made at the portions for forming bonding pads, to thereby complete the LSI wafer process.

In the aforementioned fabrication method, because the semiconductor region22in which two read transistors24,24are formed comprises the first region22aobliquely crosses a projected region of the write word line11; the second region22bformed in parallel with the bit line12so as to be continued from one end of the first region22a; and the third region22cformed in parallel with the bit line12so as to be continued from the other end of the first region22a, the storage cells41which individually comprise the TMR element13and connection layer31can be arranged so as to be shifted by 1/2n (where, n represents a natural number of 1 or larger) pitches in an oblique direction away from the extending direction of the write word line11, even when the cell is designed so that the TMR element13is arranged in the intersectional region of the bit line12and write word line11, and so that the connection layer31is connected to the end portion of the semiconductor region22.

Moreover, this makes it possible to locate one end portion of each of a plurality of semiconductor regions22, which compose a second semiconductor region array22v2adjacent to a first semiconductor region array22v1comprising a plurality of the semiconductor regions22arranged in the extending direction of the write word line11, one by one between the individual semiconductor regions22in the first semiconductor region array22v1on the second semiconductor region array22v2side. This makes it possible to effectively layout the semiconductor regions22in which the read transistors24are to be made while avoiding waste in terms of occupied area.

It is also made possible to reduce the cell area because the sense lines15and write word lines11are stacked while placing the second insulating film42in between. It is still also possible to solve a problem of cross-talk because the distance between the TMR elements13and between the write word lines11can be ensured to a sufficient level.

Industrial Applicability

The magnetic storage device and the method of fabricating the same according to the present invention makes it possible to effectively layout the individual semiconductor regions in which the read transistors are to be made while avoiding waste in terms of occupied area. Also the structure in which the sense lines and the write word lines are stacked while placing the second insulating film in between can successfully reduce the cell area. In addition, it is still also possible to solve a problem of cross-talk because the distance between the TMR elements and between the write word lines can be ensured to a sufficient level. Accordingly the present invention is successful in providing an MRAM (magnetic random access memory) capable of achieving high reliability and high speed.