Comparator preamplifier robust to variations in supply and common-mode

An electronic circuit comprises a comparator circuit including an input circuit stage and an output circuit stage, and an input stage supply circuit coupled to a circuit supply rail and the input circuit stage. The input stage supply circuit includes a voltage generator circuit and a regulating circuit. The voltage generator circuit includes a replicate circuit of a portion of the input circuit stage to generate a voltage that is less than a voltage of the circuit supply rail and varies with the voltage of the circuit supply rail and device parameters of the replicate circuit. The regulating circuit generates a regulated input stage supply using the generated voltage.

FIELD OF THE DISCLOSURE

This document relates to integrated circuits and in particular to pre-amplifier circuits for comparator circuits.

BACKGROUND

Comparator circuits are used to detect or determine differences between two voltages or currents. For example, comparators can be used in successive approximation register (SAR) analog-to-digital converters (ADCs) to resolve the results of bit trials during the conversion process. However, performance of comparator circuits can be sensitive to variations in voltage of the circuit supply rail and to variations in the common mode voltage of the inputs to the comparator circuit.

SUMMARY OF THE DISCLOSURE

This document relates generally to comparator circuits and more specifically to preamplifier (preamp) circuits for comparator circuits that are robust to variations in supply voltage and input common mode voltage. In some aspects, an electronic circuit comprises a comparator circuit and an input stage supply circuit. The comparator circuit includes an input stage and an output stage. The input stage supply circuit is coupled to a circuit supply rail and the input circuit stage of the comparator. The input stage supply circuit includes a voltage generator circuit that includes a replicate circuit of a portion of the input circuit stage to generate a voltage that is less than a voltage of the circuit supply rail and varies with the voltage of the circuit supply rail and device parameters of the replicate circuit, and a regulating circuit configured to generate a regulated input stage supply using the generated voltage.

In some aspects, an electronic system includes an analog-to-digital converter (ADC) circuit. The ADC circuit includes a digital-to-analog converter (DAC) circuit, a comparator circuit operatively coupled to the DAC circuit and including an output circuit stage and a preamp circuit stage, and a preamp supply circuit coupled to a circuit supply rail and the preamp circuit stage. The preamp supply circuit includes a voltage generator circuit and a regulating circuit. The voltage generator circuit includes a replicate circuit of a portion of the preamp circuit stage to generate a voltage that is less than a voltage of the circuit supply rail and varies with the voltage of the circuit supply rail and device parameters of the replicate circuit. The regulating circuit generates a regulated preamp supply using the generated voltage.

In some aspects, an ADC circuit includes a digital-to-analog converter (DAC) circuit, and a comparator circuit including an output circuit stage and a preamp circuit stage. The preamp circuit stage includes a differential input transistor pair, and a preamp supply circuit coupled to a circuit supply rail and the preamp circuit stage. The preamp supply circuit includes a voltage generator circuit and a regulating circuit. The voltage generator circuit generates a voltage that is less than a voltage of the circuit supply rail and varies with the voltage of the circuit supply rail and an input common mode voltage, wherein the voltage generator circuit includes a differential input transistor pair matching the differential input transistor pair of the preamp circuit stage. The regulating circuit configured to generate a regulated preamp supply using the generated voltage.

DETAILED DESCRIPTION

FIG. 1is a block diagram of an example of portions of a comparator circuit. The comparator circuit115includes an input circuit stage and an output circuit stage. The input circuit stage is a preamplifier (preamp) circuit stage117. The circuit supply rail VDDof the preamp circuit stage117can be 1.8 volts (1.8V) to 3.6V. The full scale of the input signal to the preamp circuit may be 200 millivolts (200 mV) lower than the supply voltage (e.g., a 2.5V to 5V peak-to-peak differential input signal). The output circuit stage119can include a latch to capture the result of a comparison of the inputs. The circuit supply rail of the output circuit stage119can be lower (e.g., 1.1V) and still provide the desired performance.

The performance of the preamp circuit stage117can be affected by large differences in supply voltage for different applications of the preamp circuit. For example, an input signal with a large peak-to-peak signal swing may result in clipping of the input signal if the application has a low circuit supply rail voltage. The problem is compounded with variation in input common mode voltage. The comparator circuit115may be included in an ADC circuit.

FIG. 2is a block diagram of an example of two-stage ADC circuit200(sometimes called a pipeline ADC) including a front-end ADC circuit202and a main ADC circuit204. The front-end ADC circuit202resolves the first most significant bits (MSBs) of the conversion of the input (e.g., the first five MSBs D0-D4). The output of the front-end ADC is subtracted from the input and loaded onto the slower but more accurate main ADC circuit to resolve the remaining bits of the conversion.

FIG. 3is a functional block diagram of an example of a differential SAR ADC circuit such as front-end ADC circuit202ofFIG. 2. The SAR ADC circuit302includes a positive digital-to-analog converter (DAC)305, a negative DAC310, and a comparator circuit315. Each DAC includes weighted bit capacitors320. In the example, the capacitors are weighted as C/2, C/4 . . . C/(2N), where N is the number of bits (e.g., N=5) in the DACs and C is the total capacitance of the bit capacitors added together. A differential analog input voltage (IN+, IN−) is sampled onto the bit capacitors with respect to the common mode of the comparator (CompCM) by closing switches325and330. The input voltage is held on the capacitors by opening switches330, then opening switches325. The top plates of the capacitors are at the CompCM voltage.

The positive DAC305and the negative DAC310are also connected to positive and negative reference voltage (REF+, REF−). As part of the successive approximation routine, bit trials for each of the bit capacitors are performed iteratively. In a bit trial, the output of the positive DAC305and the output of the negative DAC310are applied to the inputs of the comparator circuit315. Based on the output of the comparator circuit, a bit capacitor is connected to either REF+ or REF− using switches335. If the bit capacitor is connected to REF+ the bit of the digital value corresponding to the bit capacitors is assigned a logic value ‘1’, and if the bit capacitor is connected to REF+ the bit of the digital value corresponding to the bit capacitors is assigned a logic value ‘0’. Conversion then proceeds to the next bit capacitor until all bits of the digital value are determined.

FIG. 4is a circuit diagram of an example of a preamp circuit417for a comparator circuit such as comparator circuit315ofFIG. 3for SAR ADC circuit302. For unhindered operation with minimum circuit supply rail and maximum input common mode, the input transistor pair Q1and Q2and the tail current transistor (transistor labeled “10”) of the preamp circuit417typically have a large area. The tail current transistor has a large area to reduce the drain-source saturation voltage (VDSAT) to ensure that the tail current transistor and the input transistor pair remain in the saturation region even for the lowest anticipated circuit supply rail voltage and highest input common mode voltage.

However, a large tail current transistor increases the capacitance on the tail-node and increases the power up time. The power up time can be critical to performance of a comparator used in an ADC circuit because it directly adds to the overall conversion time of the ADC. Additionally, a large tail current transistor can be slow to recover form an overdrive condition. An overdrive condition occurs when there is large change in charge during a conversion step (e.g., from the midpoint (REF/2) to a negative LSB). During the conversion step, all the nodes of the ADC circuit need to settle to within reasonable ranges of normal operating conditions before the subsequent conversion decision (e.g., a bit trial). If the capacitance on the tail-node is high, a significant amount of time is spent by the tail current transistor to charge the capacitance and the result of the conversion decision may be wrong.

It is preferred to have the smallest possible sizes for transistors Q1and Q2such that their parasitic caps are minimal for optimal SAR ADC design. An approach to allow unhindered operation of the comparator circuit without using large devices for the input transistor pair and the transistor tail current is to generate a separate circuit supply rail just for the preamp circuit stage of the comparator. If this internal separate circuit supply rail VDD_INTvaries with the external supply VDD and device parameters of the preamp circuit stage, smaller and better-performing transistors can be used in the preamp circuit stage.

FIG. 5is a circuit diagram of an example of a preamp circuit stage517for a comparator circuit. The output stage of the comparator is not shown. The preamp circuit stage517includes differential input transistor pair MP4and MP5, tail current transistor MP2, and tail current mirror transistor MP3.

FIG. 5also shows a circuit diagram of an example of a preamp supply circuit540. The preamp supply circuit540includes a voltage generator circuit542and a regulating circuit544. The voltage generator circuit542includes a voltage divider circuit. In the example ofFIG. 5, the voltage divider circuit is a resistive divider circuit that includes the two resistors (R) connected between the VDDcircuit supply rail and circuit ground. The voltage generator circuit542produces a preamp supply voltage that is less than VDD. Reducing the preamp supply voltage allows smaller devices to be used for the input transistor pair (MP4, MP5) and for the current tail transistors (MP2, MP3) of the preamp circuit ofFIG. 4.

The regulating circuit544may act as a buffer stage for the voltage produced by the voltage generator circuit542. The regulating circuit544generates a regulated preamp supply using the voltage generated by the voltage generator circuit542. In some aspects, the regulating circuit544is a low drop out (LDO) regulating circuit. Other aspects of the regulating circuit are described below.

The voltage generator circuit542includes a replicate of a portion of the preamp circuit stage517. This replicate circuit is used to make the voltage generator circuit542vary with device parameters of the preamp circuit stage517. In the example ofFIG. 5, the replicate circuit includes transistor MP-mir. This transistor is a copy of the transistors used in the input transistor pair of the preamp circuit stage517. The preamp supply voltage generated by the voltage generator circuit542is VDD_INT. Because the transistor MP-mir is a replicate transistor, the threshold voltage of transistor MP-mir is also the threshold voltage of transistors MP2, MP3, MP4, and MP5of the preamp circuit stage517. The preamp circuit supply rail varies with the voltage of the main circuit supply rail and device parameters of the replicate circuit.

The transistor used for the input transistor pair (MP4, MP5), the replicate transistor (MP_mir), and the current tail transistors (MP2, MP3) can be chosen from transistors in the process that have lower VTH, so that VTHis half of that of the transistors used in the preamp circuit ofFIG. 4without sacrificing reliability. The input transistors MP4, MP5are sized to remain in saturation so that the gate-to-source voltage (VGS) of the devices is approximately VTH. This allows the input transistor pair in preamp circuit stage517to be reduced in size from the input transistor pair of preamp circuit417ofFIG. 4. The smaller device size reduces the capacitance on the tail node and hence reduces the power up time of the preamp circuit stage517.

FIG. 6is a circuit diagram of another example of a preamp supply circuit640. The output node (VDD_INT) is connected to a preamp circuit stage as inFIG. 5.

The preamp supply circuit640includes a voltage generator circuit642and a regulating circuit644. In the example ofFIG. 6, the replicate circuit of a portion of the voltage generator circuit642includes transistors MP_mir0and MP_mir1which are a copy of the differential input transistor pair MP5and MP4of the preamp circuit stage517ofFIG. 5. Transistors MP_mir0and MP_mir1are connected to the differential input of the preamp circuit stage the transistors mirror transistors MP5, MP4. The voltage VXat node X inFIG. 6is
VX=VINCM+VGS+I*R,(1)
where VINCMis the common mode input voltage, VGSis the gate to source voltage of the transistors of the replicate circuit, and I*R is voltage drop of resistor R. The voltage VDD_INTat the output node of the preamp supply circuit640is approximately equal to VX. Thus, the preamp supply circuit640generates a voltage that varies with the voltage of the circuit supply rail, the device parameters of the circuit replicate, and the common mode of an input signal to the preamp circuit stage. Therefore, the circuit ofFIG. 6is robust to variations in the input common mode which may not always be VDD/2.

In the example ofFIG. 6, the inputs VINP, VINNto the input transistor pair MP5, MP4of the preamp circuit stage are also connected to the input transistor pair MP_mir0, MP_mir1of the replicate circuit of the voltage generator circuit642. The circuit node “X” may not track the input common mode when there is an overdrive condition.

FIG. 7is a circuit diagram of a sampling circuit750that can improve the performance of the preamp supply circuit640ofFIG. 6. The sampling circuit750samples the input common mode voltage at the differential input of the comparator circuit and applies the input common mode voltage to the differential input transistor pair (MP_mir0, MP_mir1) of the replicate circuit. The sampling circuit750includes two capacitors (C1, C2) and four switches (S1-S4). During a sampling phase switches S1and S2are connected to VINP, VINN, to sample the differential input voltage of the preamp circuit stage517onto the capacitors, and switches S3, S4are open.

During a following phase, switches S1and S2are open and switches S3and S4are closed to short the capacitor terminals together. Closing switches S3and S4also samples the input common mode (VINCM) onto the inputs of the differential input transistor pair (MP_mir0, MP_mir1) of the replicate circuit. This improves the tracking by the replicate circuit of the input common mode of the preamp circuit.

If the preamp circuit stage is included in the comparator of an ADC circuit, the input common mode may be sampled onto the replicate circuit in a timed relationship to an analog-to-digital conversion by the ADC circuit. For example, in the ADC circuit ofFIG. 3, the switches325,335may sample the input voltage onto the DAC circuits305,310. A clock signal can be used to sample the sample the input common mode voltage onto the differential input transistor pair of the replicate circuit in a timed relationship to the sampling of the input onto the DAC circuits. In certain aspects, the input common mode voltage is sampled onto the differential input transistor pair of the replicate circuit in a timed relationship to a bit trial by the ADC circuit. The clock signal that controls the switches does not impact the signal-to-noise ratio of the ADC circuit and the clock signal may be slow and noisy.

Returning toFIG. 6, the regulating circuit644includes a current mirror comprised of transistors MN1and MN1_mir. The current mirror transistors are n-type field effect transistors (NFETs) such as n-type metal oxide semiconductor (NMOS) transistors. The current mirror provides drive to buffer the output of the voltage generator circuit642. However, the current mirror adds a slight shift of a gate to source voltage VGSof transistor MN1to VX, and it is desired for the preamp supply voltage VDD_INTto be approximately equal to VX. The regulating circuit644includes a flipped-voltage-follower circuit in its output stage to cancel the VGSshift of the current mirror. The voltage follower circuit includes the MN1_mirtransistor and transistor MN2arranged below the MN1_mirtransistor.

The regulating circuit644also includes a biasing circuit coupled to the flipped-voltage-follower circuit. The biasing circuit includes transistor MP1, the voltage bias VBIASP, and the resistor RLARGEcoupled to the gate of MP1. The biasing circuit as shown inFIG. 6may introduce circuit noise. In some aspects, the regulating circuit642includes a noise filter circuit coupled to the biasing circuit to mitigate the noise in the output stage of the regulating circuit644.

FIG. 8is a circuit diagram of a portion of the regulating circuit644ofFIG. 6and a noise filter circuit. Transistors MP1, MN1_mir, and MN2correspond to the same transistors in the regulating circuit644ofFIG. 6. The noise filter adds a large time constant (τ) to the VBIASPnode to filter out the noise. To make the time constant large enough, a very large resistance R is implemented using the series connected diodes of diode chain852. The diodes are near-zero biased as the current through the diodes is small. Because the current through the near-zero biased diodes is small, the effective resistance of the diode chain is very high. The high resistance together with the capacitance at the anode connection of the diode chain (e.g., the capacitance of the gate oxide of transistors MP1and MP2) will result in a noise filter with a large time constant.

While the diode chain852provides a good noise filter, the diode chain852is susceptible to leakage currents flowing through the diodes. This will lead to a mismatch between the VGSof the mirror transistors and which causes a significant current mismatch. To compensate this leakage current and make sure the compensation tracks over PVT (process-voltage-temperature variation), the cancellation circuitry includes transistors PMOS transistors MP2, MP3, and MP4. The gate leakage current is applied to the gate of transistor MP2and the drain and source region of MP2are connected to diode-connected transistor MP4. MP2and MP4are matched transistors. Transistors MP3and MP4are connected to the n-well of the diodes. The cancellation circuitry minimizes the voltage drop across the diodes to minimize leakage current.

The devices, systems and methods described herein provide a pre-amp circuit that is robust to variations in the main circuit supply voltage and to variations in input common mode voltage. A preamp circuit supply is derived from the main circuit supply voltage. The preamp circuit supply may vary with one or both of the main circuit supply voltage and the input common mode voltage to maintain optimized biasing of the preamp circuit. This allows the preamp circuit to have reduced circuit area over conventional approaches without a decrease in performance.

Additional Description and Aspects

Aspect 1 can include subject matter (such as an electronic circuit) comprising a comparator circuit and an input stage supply circuit. The comparator circuit includes an input stage and an output stage. The input stage supply circuit is coupled to a circuit supply rail and the input circuit stage of the comparator. The input stage supply circuit includes a voltage generator circuit that includes a replicate circuit of a portion of the input circuit stage to generate a voltage that is less than a voltage of the circuit supply rail and varies with the voltage of the circuit supply rail and device parameters of the replicate circuit, and a regulating circuit configured to generate a regulated input stage supply using the generated voltage.

In Aspect 2, the subject matter of Aspect 1 includes a pre-amplifier (preamp) circuit stage as the input circuit stage, a preamp supply circuit coupled to the circuit supply rail and the preamp circuit stage as the input stage supply circuit, the replicate circuit includes a portion of the preamp circuit stage, and the regulating circuit is configured to generate a regulated preamp supply using the generated voltage.

In Aspect 3, the subject matter of Aspect 2 optionally includes a preamp circuit stage that includes a differential input transistor pair. The voltage generator circuit includes a voltage divider circuit, and the replicate circuit includes a transistor that is a copy of a transistor of the differential input transistor pair and is coupled to the voltage divider circuit.

In Aspect 4, the subject matter of one or both of Aspects 2 and 3 optionally include a voltage generator circuit configured to generate a voltage that varies with the voltage of the circuit supply rail, the device parameters of the replicate circuit, and a common mode of an input signal to the preamp circuit stage.

In Aspect 5, the subject matter of Aspect 4 optionally includes a preamp circuit stage that includes a differential input transistor pair coupled to a differential input of the comparator circuit, and the replicate circuit includes a copy of the differential input transistor pair coupled to the differential input of the comparator circuit.

In Aspect 56, the subject matter or Aspect 5 optionally includes a sampling circuit configured to sample the input common mode voltage at the differential input of the comparator circuit and apply the input common mode voltage to the differential input transistor pair of the replicate circuit.

In Aspect 7, the subject matter of one or any combination of Aspects 1-6 optionally includes regulating circuit includes a low dropout (LDO) circuit.

In Aspect 8, the subject matter of one or any combination of Aspects 1-7 optionally includes a regulating circuit that includes a flipped-voltage-follower circuit.

In Aspect 9, the subject matter of Aspect 8 optionally includes a biasing circuit coupled to the flipped-voltage-follower circuit; and a noise filter circuit coupled to the biasing circuit.

In Aspect 10, the subject matter of Aspect 9 optionally includes a noise filter circuit that includes one or more near-zero biased diodes.

In Aspect 11, the subject matter of Aspect 10 optionally includes cancellation circuitry configured to cancel noise in the noise filter circuit resulting from leakage current of the one or more near-zero biased diodes.

Aspect 12 can include subject matter (such as an electronic system) or can optionally be combined with one or any combination of Aspects 1-11 to include such subject matter, comprising a first analog-to-digital converter (ADC) circuit. The first ADC circuit including a digital-to-analog converter (DAC) circuit, a comparator circuit operatively coupled to the DAC circuit and including an output circuit stage and a pre-amplifier (preamp) circuit stage, and a preamp supply circuit coupled to a circuit supply rail and the preamp circuit stage. The preamp supply circuit includes a voltage generator circuit that includes a replicate circuit of a portion of the preamp circuit stage to generate a voltage that is less than a voltage of the circuit supply rail and varies with the voltage of the circuit supply rail and device parameters of the replicate circuit, and a regulating circuit configured to generate a regulated preamp supply using the generated voltage.

In Aspect 13, the subject matter of Aspect 12 optionally includes a preamp circuit stage that includes a differential input transistor pair coupled to a differential input of the comparator circuit, and the replicate circuit includes a copy of the differential input transistor pair coupled to the differential input of the comparator circuit. The generated voltage varies with the voltage of the circuit supply rail, the device parameters of the replicate circuit, and a common mode of the differential input of the comparator circuit.

In Aspect 14, the subject matter of Aspect 13 optionally includes a sampling circuit configured to sample the input common mode voltage at the differential input of the comparator circuit, and apply the input common mode voltage to the differential input transistor pair of the replicate circuit stage in a timed relationship to an analog-to-digital conversion by the first ADC circuit.

In Aspect 15, the subject matter of Aspect 14 optionally includes a preamp circuit stage that includes a differential input transistor pair, the voltage generator circuit includes a voltage divider circuit, and the replicate circuit includes a transistor that is a copy of a transistor of the differential input transistor pair and is coupled to the voltage divider circuit. The generated voltage varies with the voltage of the circuit supply rail and parameters of the voltage divider circuit and the transistor coupled to the voltage divider circuit.

In Aspect 16, the subject matter of one or any combination of Aspects 12-15 optionally includes a regulating circuit that includes a flipped-voltage-follower circuit.

In Aspect 17, the subject matter of Aspect 16 optionally includes a biasing circuit coupled to the flipped-voltage-follower circuit, and a noise filter circuit coupled to the biasing circuit.

In Aspect 18, the subject matter of Aspect 17 optionally includes a noise filter circuit that includes one or more near-zero biased diodes.

In Aspect 19, the subject matter of Aspect 18 optionally includes cancellation circuitry configured to cancel noise in the noise filter circuit resulting from leakage current of the one or more diodes of the leakage current.

In Aspect 20, the subject matter of Aspect 19 optionally includes a second ADC circuit coupled to the output stage of the comparator circuit.

Aspect 21 can include subject matter (such as an analog-to-digital (ADC) converter circuit) or can optionally be combined with one or any combination of Aspects 1-20 to include such subject matter, comprising a digital-to-analog converter (DAC) circuit, a comparator circuit, and a pre-amplifier (preamp) supply circuit. The comparator circuit includes an output circuit stage and a preamp circuit stage that includes a differential input transistor pair. The preamp supply circuit is coupled to a circuit supply rail and the preamp circuit stage. The preamp supply circuit includes a voltage generator circuit configured to generate a voltage that is less than a voltage of the circuit supply rail and varies with the voltage of the circuit supply rail and an input common mode voltage, wherein the voltage generator circuit includes a differential input transistor pair matching the differential input transistor pair of the preamp circuit stage; and a regulating circuit configured to generate a regulated preamp supply using the generated voltage.

In Aspect 22, the subject matter of Aspect 21 optionally includes a first sampling circuit configured to sample an input voltage onto the DAC circuit and a second sampling circuit configured to sample the input common mode voltage onto the differential input transistor pair of the voltage generator circuit to the sampling of the input voltage onto the DAC circuit.

In Aspect 23, the subject matter of one or both of Aspects 21 and 22 optionally include a voltage generator circuit that includes a voltage divider circuit, and the generated voltage varies with the voltage of the circuit supply rail, the input common mode voltage, and device parameters of the differential input transistor pair and the voltage divider.