2-T SRAM cell structure and method

The present invention, in one embodiment, provides a memory device including a substrate including at least one device region; a first field effect transistor having a first threshold voltage and a second field effect transistor having a second threshold voltage, the second field effect transistor including a second active region present in the at least one device region of the substrate, the second active region including a second drain and a second source separated by a second channel region, wherein the second channel region includes a second trap that stores holes produced when the first field effect transistor is in the on state, wherein the holes stored in the second trap increase the second threshold voltage to be greater than the first threshold voltage.

FIELD OF THE INVENTION

The present invention relates to microelectronics. In one embodiment, the present invention relates to a memory device in which the memory function is provided by at least two field effect transistors.

BACKGROUND OF THE INVENTION

Microelectronic circuits for data and/or signal processing contain memories with memory cells that make it possible to store data. As an increasing number of portable systems have come on the market, such as mobile telephones, palm-top computers and medical equipment, the requirements for these memories have become more stringent as processing speed increases. An important example of such memories is the SRAM (Static Random Access Memory), which can be implemented with a small area requirement and allows very rapid access to its content. A static random access memory (SRAM) is a significant memory device due to its high speed, low power consumption, and simple operation. Unlike a dynamic random access memory (DRAM) cell, the SRAM typically does not need to regularly refresh the stored data.

However, SRAM stability is typically impacted by scaling. It is desirable to make the silicon area occupied by the memory cell as small as practical so as to increase the density of the memory array. A memory cell that occupies a small area of silicon permits more memory cells to be fabricated on a single silicon chip of a given size. Hence, there is increasing efforts to scale memory cells and the devices present in memory cells, such as SRAM devices.

Unfortunately, the leakage per area of memory devices, such as SRAM devices, typically increases as device scaling increases. Further, as the device scaling is increased the threshold voltage mismatch (Vth) increases, which typically results in decreased device stability.

SUMMARY OF THE INVENTION

In one aspect, the present invention provides a memory device. In one embodiment, the memory device utilizes hole traps on the semiconductor isolation region interfaces as the memory function.

Broadly, the memory device includes:

a substrate including at least one device region;

a first field effect transistor having a first threshold voltage, the first field effect transistor including a first active region present in the at least one device region of the substrate, the first active region including a first drain and a first source; and

a second field effect transistor having a second threshold voltage, the second field effect transistor including a second active region present in the at least one device region of the substrate, the second active region including a second drain and a second source separated by a second channel region, the second source and the first source are provided by a shared dopant region in the at least one device region, wherein the second channel region includes a second trap that stores holes produced when the first field effect transistor is in the on state, wherein the holes stored in the second trap increase the second threshold voltage to be greater than the first threshold voltage.

In one embodiment, when the first field effect transistor has a first channel separating the first drain from the first source, the first channel includes a first trap. The first channel region extends along a first direction defined by the dimension separating the first drain from the first source that is substantially parallel to the second channel region that extends along a second direction defined by the dimension separating the second drain and the second source.

In one example of the memory device, in which the first field effect transistor includes a first gate structure and the second field effect transistor includes a second gate structure, the first gate structure to the first channel region is positioned on a first side of the at least one device region, and the second gate structure to the second channel region is positioned on a second side of the at least one device region.

The second gate structure may include an oxide containing gate dielectric and the second trap is positioned at an interface of the oxide containing gate dielectric and the second active region.

In one embodiment, the at least one device region has an area of about 0.015 um2, and the first active region and the second active region are composed of a Si-containing composition.

In another aspect, the present invention provides a method of manufacturing a memory device. In one embodiment, the method provides a memory device, in which the memory function of the device is provided by hole traps on the semiconductor isolation region interfaces. Broadly, the method of manufacturing a memory device includes:

providing a substrate;

forming at least one device region in the substrate;

forming at least two gate regions in contact with the at least one device region;

forming a common source region for the at least two gate regions to the at least one device region; and

forming a first drain region for one of the two gate regions on a first portion of the at least one device region, and a second drain region for an other of the two gate regions on a second portion of the at least one device region.

The forming of the at least one device region in the substrate may include etching the Si-containing substrate to provide at least one Si-containing island.

The forming of the at least one gate region in contact with the at least one device regions may include forming a gate dielectric atop at least one of the Si-containing islands; forming a gate conductor atop the gate dielectric; and removing a portion of the gate conductor and a portion of the gate dielectric that is positioned atop an upper surface of the Si-containing islands, wherein a remaining portion of the gate conductor and the gate dielectric is positioned on a sidewall of the Si-containing islands, and the upper surface of the Si-containing islands is exposed.

The forming of the common source region includes implanting an N-type or P-type dopant. The method may further include forming a contact to the at least two gate regions, the common source region, the first drain region, and the second drain region.

In another aspect, the present invention provides a method of storing memory. In one embodiment, the method of storing memory utilizes the above-described memory devices. Broadly, the method of storing memory includes:

providing a memory cell including a first field effect transistor and a second field effect transistor on a substrate, a first active region of the first field effect transistor and a second active region of the second field effect transistor are present on a device region of the substrate;

writing a value to the memory cell by applying a first voltage to the first gate of the first field effect transistor and a second voltage to the second gate of the second field effect transistor, wherein when the first voltage is greater than the second voltage and is greater than a first threshold voltage of the first field effect transistor, a “1” is written to the memory cell, and when the second voltage is greater than the first voltage and is greater than a second threshold voltage of the second field effect transistor, a “0” is written to the memory cell; and

retaining the value by applying a third voltage to a first source of the first field effect transistor and a second source of the second field effect transistor, and applying a fourth voltage to a first gate structure of the first field effect transistor and to a second gate structure of the second field effect transistor, wherein the third voltage is greater than or equal to the fourth voltage.

The method may further include reading the value by applying a fifth voltage to the first gate structure and the second gate structure, and measuring a first current at the first drain and a second current at the second drain, wherein the “1” is stored in the memory device when the second current at the second drain is less than the first current at the first drain, and the “0” is stored in the memory device when the first current at the first drain is less than the second current at the second drain.

In one embodiment of the method of storing memory, the application of the first voltage to the first gate of the first field effect transistor, which is greater than the first threshold voltage of the first field effect transistor, produces holes that are collected in a second trap of the second field effect transistor that is present at a second interface of the gate structure of the second field effect transistor and the region of the substrate in the second active region. The holes that are collected in the second trap of the second field effect transistor can increase the second threshold voltage of the second field effect transistor to be greater than the first threshold voltage of the first field effect transistor. In one embodiment, the holes that are collected in the second trap of the second field effect transistor are produced from impact ionization within the first field effect transistor and are released from a first trap positioned at a first interface of the gate structure of the first field effect transistor and a Si-containing layer of the substrate in which the first active region is present.

An electric field produced by a voltage differential between the first voltage and the second voltage may direct the holes from the first field effect transistor to the second trap of the second field effect transistor. The holes collected at the second trap produce a positively charged surface that increases the second threshold voltage of the second field effect transistor to be greater than the first threshold voltage of the first field effect transistor.

DETAILED DESCRIPTION OF THE INVENTION

The embodiments of the present invention relate to memory devices that employ hole traps on the interfaces of semiconducting and isolation regions, such as an interface of a silicon region and a silicon oxide region, as the memory function. In one embodiment, the memory devices of the present invention are SRAM memory devices.

As used herein, “semiconductor” refers to an intrinsic semiconductor material that may be doped, that is, into which a doping agent has been introduced, giving it different electrical properties than the intrinsic semiconductor. Doping involves adding dopant atoms to an intrinsic semiconductor, which changes the electron and hole carrier concentrations of the intrinsic semiconductor at thermal equilibrium. In intrinsic semiconductors the valence band and the conduction band are separated by the energy gap that may be as great as about 3.5 eV.

As used herein a “field effect transistor” is a transistor in which output current, i.e., source-drain current, is controlled by the voltage applied to the gate. A field effect transistor has three terminal, i.e, gate, source and drain.

As used herein, the term “drain” means a doped region in semiconductor substrates located at the end of the channel in field effect transistors, in which carriers are flowing out of the transistor through the drain.

As used herein, the term “source” is a doped region from which majority carriers are flowing into the channel.

A “gate structure” means a structure used to control output current (i.e., flow of carriers in the channel) of a semiconducting device, such as a field effect transistor (FET).

As used herein, the term “channel” is the region between the source and drain of a metal oxide semiconductor transistor that becomes conductive when the transistor is turned on.

As used herein, the term “dielectric” denotes a non-metallic material having insulating properties.

As used herein, “insulating” denotes a room temperature conductivity of less than about 10−10(Ω-m)−1.

As used herein, “conductive” denotes a room temperature conductivity of greater than about 10−8(Ω-m)−1.

As used herein, “threshold voltage” is the lowest attainable voltage that will turn on a transistor, such as a field effect transistor.

A “device region” includes a portion of the substrate on which at least the field effect transistors are positioned.

As used herein, an “active device region” is portion of the device region in which the source, drain and channel of a device are present.

As used herein, a “PFET” refers to a device created by the addition of trivalent impurities to an intrinsic semiconductor to create deficiencies of valence electrons, such as boron, aluminum or gallium to an intrinsic Si substrate.

As used herein, an “NFET” refers to a device created by the addition of pentavalent impurities that contributes free electrons to an intrinsic semiconductor, such as antimony, arsenic or phosphorous to an intrinsic Si substrate.

The term “trap” means a site that retains and stores a hole.

The term “hole” means a positive charge carrier in semiconductors, i.e., a vacant electron state in the valence band of the semiconducting material that is a positive charge carrier in an electric field.

For purposes of the description hereinafter, the terms “upper”, “lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, and derivatives thereof shall relate to the invention, as it is oriented in the drawing figures.

FIG. 1depicts one embodiment of a 2-T SRAM cell structure, in accordance with the present invention. SRAM (static RAM) is random access memory (RAM) that retains data bits in its memory as long as power is being supplied. Unlike dynamic RAM (DRAM), which stores bits in cells including a capacitor and a transistor, SRAM does not have to be periodically refreshed.

In one embodiment, the present invention provides a memory device110, e.g., a SRAM memory device that includes a substrate49including at least one device region120; a first field effect transistor10having a first threshold voltage, the first field effect transistor10including a first active device region121present in the at least one device region120of the substrate49, the first active device region121including a first drain11and a first source12; and a second field effect transistor20having a second threshold voltage, the second field effect transistor20including a second active region122present in the at least one device region of the substrate49, the second active device region122including a second drain21and a second source22separated by a second channel region, the second source22and the first source12are provided by a shared dopant region13(also referred to as common dopant region13) in the at least one device region120, wherein the second channel region includes a second trap50that stores holes produced when the first field effect transistor10is in the on state, wherein the holes stored in the second trap50increase the second threshold voltage to be greater than the first threshold voltage.

In one embodiment of the memory device110, the first channel region extends along a first direction D1defined by the dimension separating the first drain11from the first source12that is substantially parallel to the second channel region which extends along a second direction D2defined by the second drain21and the second source22. The first field effect transistor10may include a first gate structure GI and the second field effect transistor20may include a second gate structure G2, the first gate structure G1corresponding to the first channel region is positioned on a first side of the device region120, the second gate structure G2corresponding to the second channel region is positioned on a second side of the device region120.

In one embodiment, the device region120has an area on the order of 150×200 nm2on a 32 nm is on the order of about 40 nm, the gate length (LPOLY) is on the order of about 40 nm, and the CA-PC ground rules are on the order of about 25 nm. In another embodiment, the device region120has an area on the order of 100×150 nm2on a 32 nm technology, wherein CA is on the order of about 40 nm, the gate length (LPOLY) is on the order of about 40 nm, and the CA-PC ground rules are on the order of about 25 nm. CA is the stud contact from the first metal level to the terminals of the active region, e.g., source, drain or gate.

FIGS. 2A-2Care schematic views depicting the operation of a memory cell111including a 2-T SRAM cell structure in write mode. Referring toFIGS. 2A and 2B, writing a value to the memory cell111, i.e., memory device110, includes applying a first voltage to the first field effect transistor10and a second voltage to the second field effect transistor20. In one embodiment, when the voltage applied to the first field effect transistor10is greater than the voltage that is applied to the second field effect transistor20, and the voltage that is applied to the first field effect transistor10is greater than the threshold voltage of the first field effect transistor10, a “1” is written to the memory cell111, as depicted inFIG. 2A. In one embodiment, when the voltage applied to the second field effect transistor20is greater than the voltage applied to the first field effect transistor10, and the voltage that is applied to the second field effect transistor20is greater than the threshold voltage of the second field effect transistor20, a “0” is written to the memory cell111, as depicted inFIG. 2B.

Referring toFIG. 2A, when the voltage that is applied to the first field effect transistor10performs a write operation for a “1” value, the operating voltage (Vdd) is applied to the gate structure GI of the first field effect transistor10, which is greater than the threshold voltage of the first field effect transistor10and is greater than the voltage that is applied to the second field effect transistor20, wherein the voltage applied to the gate structure G2of the second field effect transistor20may be on the order of approximately 0V. In one embodiment, the operating voltage (Vdd) is lower than the voltage (Vdd2′) that is measured from the drain11of the first field effect transistor10, wherein the voltage of the drain of the device may be measured by employing resistors4.

The operating voltage (Vdd) for a write operation for a “1” value may range from about 0.7V to about 1.3V, when the threshold voltage (Vt) of the first field effect transistor10ranges from about 0.2V to about 0.4V. In another embodiment, the operating voltage (Vdd) for a write operation for a “1” value may range from about 0.7V to about 1.3V, when the threshold voltage (Vt) of the first field effect transistor10ranges from about 0.2V to about 0.4V.

Referring toFIG. 2B, when the voltage that is applied to the second field effect transistor20performs a write operation for a “0”, the operating voltage (Vdd) is applied to the gate structure G2of the second field effect transistor20, which is greater than the threshold voltage for the second field effect transistor20and is greater than the voltage that is applied to the first field effect transistor10, wherein the voltage that is applied to the gate structure G1of the first field effect transistor10may be on the order of approximately 0V. In one embodiment, the operating voltage (Vdd) is lower than the voltage (Vdd2′) measured from the drain21of the second field effect transistor20, wherein the voltage of the drain of the device may be measured by employing resistors4.

The operating voltage (Vdd) for a write operation for a “0” value may range from about 0.7V to about 1.3V, when the threshold voltage (Vt) of the second field effect transistor20ranges from about 0.2V to about 0.4V. In another embodiment, the operating voltage (Vdd) for a write operation for a “0” value may range from about 0.7V to about1.3V, when the threshold voltage (Vt) of the second field effect transistor20ranges from about 0.2V to about 0.4V.

Referring toFIG. 2C, in one embodiment when the voltage that is applied to the first field effect transistor10is greater than the threshold voltage of the first field effect transistor10, holes409are produced that are collected in a second trap50of the second field effect transistor20on about an interface of the gate structure G2of the second field effect transistor20in the device region120of the substrate49in which the second active region122is present. More specifically, the second trap50is positioned at an interface of a gate dielectric6, such as an oxide gate dielectric, of the second gate structure G2and the surface of the second active region122, such as a Si-containing surface.

In one embodiment, the holes409that are collected in the second trap50of the second field effect transistor20increases the threshold voltage (Vt) of the second field effect transistor20to be greater than the first threshold voltage (Vt) of the field effect transistor10.

The holes409that are collected in the second trap50of the second field effect transistor20may be produced from impact ionization within the first field effect transistor10and are released from a first trap40positioned at a first interface of the gate structure G1of the first field effect transistor10and the surface of the first active region121. More specifically, in one embodiment, first trap40is position at about an interface of a gate dielectric6, such as an oxide gate dielectric, of the first gate structure G1and the surface of the first active region121, such as a Si-containing surface.

Still referring toFIG. 2C, an electric field E may be produced by a voltage differential between the voltage that is applied to the first field effect transistor10and the voltage that is applied to the second field effect transistor20directs the holes409from the first field effect transistor10to the second trap50of the second field effect transistor20. In one embodiment, the voltage differential is provided by a voltage that is applied to the gate structure G1, i.e., a gate conductor, of the first field effect transistor10that is greater than the voltage that is applied to the gate structure G2of the second field effect transistor20, wherein the voltage that is applied to the first field effect transistor10is greater than the threshold voltage (Vt) of the first field effect transistor10and performs a write operation for a “1” value. In one embodiment, in which the electric field directs the holes409from the first field effect transistor10to the second trap50of the second field effect transistor20, the holes409that collect at the second trap50produce a positively charged surface (+), which increases the threshold voltage of the second field effect transistor20to be greater than the threshold voltage of the first field effect transistor10.

It is noted thatFIG. 2Cdepicts a write operation for a “1” value and that a write operation for a “0” value may be provided by employing the inverse relationship of the voltages that are being applied to the gates structures G1, G2of the first field effect transistor10and the second field effect transistor20, as depicted inFIG. 2C. More specifically, in one embodiment in which a “0” value is being written to the inventive memory device110, the voltage that is applied to the second field effect transistor20, which is greater than the threshold voltage of the second field effect transistor20and is greater than the voltage that is applied to the first field effect transistor10, creates a voltage differential that produces an electric field that directs the holes from the second field effect transistor20to the first trap40of the first field effect transistor10.

FIGS. 3A and 3Bdepict the operation of retaining a “1” value by applying a voltage to a first drain11of the first field effect transistor10and a second drain21of the second field effect transistor20, and applying a voltage to a first gate structure G1of the first field effect transistor10and to a second gate structure G2of the second field effect transistor20, wherein the voltage applied to the drain regions11,21, is greater than or equal to the voltage applied to the gate structures G1, G2. A value of 0 V may be applied to the gate structures G1, G2. As depicted inFIG. 3A, in the operation of retaining a “1” value, holes remained trapped in the second trap50of the second field effect transistor20, wherein the holes collected at the second trap50produce a positively charged surface that increases the threshold voltage of the second field effect transistor20to be greater than the threshold voltage of the first field effect transistor10. It is noted thatFIGS. 3A and 3Bdepict a retaining operation for a “1” value and that a retaining operation for a “0” value may be provided by employing the inverse relationship of the voltages that are being applied to the first field effect transistor10and the second field effect transistor20, as depicted inFIGS. 3A and 3B.

FIGS. 4A and 4Bdepict one embodiment of reading the value by applying a voltage to the first gate structure G2and the second gate structure G2, and measuring a first current at the first drain11and a second current at the second drain21, wherein the “1” value is stored in the memory device110when the second current at the second drain21is less than the first current at the first drain11, and the “0” value is stored in the memory cell111when the first current at the first drain11is less than the second current at the second drain21. When reading a “1” value, as depicted inFIGS. 4A and 4B, the second hole trap50being filled with holes increases the threshold voltage of the second field effect transistor20so that the second field effect transistor20turns on at a higher voltage and flows less current than the first field effect transistor10. When reading a “0”, the first hole trap40being filled with holes increases the threshold voltage of the first field effect transistor10so that the first field effect transistor10turns on at a higher voltage and flows less current than the second field effect transistor20.

FIG. 5depicts a plot of the impact ionization rate of one embodiment of an SRAM memory device110, as provided by the present invention. The x-axis represents voltage having units of V and the y-axis represents current (i.e. drain current (Id) to initiate ionization (reference number500) or body current (Ib) generated by impact ionization (reference number501)) having units of A/μm. In one example of the present invention, the inventive memory device110on a 32 nm SOI substrate has an impact ionization current equal to about 0.1 μA/μm, which is approximately 1000 times faster than prior flash memory devices.

FIGS. 6A to 14Edepict one embodiment of a method of manufacturing a memory device110. The method provides a memory device110, in which the memory function of the device is provided by hole traps40,50on the semiconductor isolation region interfaces. Broadly, the method of manufacturing a memory device110includes providing a substrate49; forming at least one device region in the substrate49; forming at least two gate regions G1, G2in contact with the at least one device region; forming a common source region13for the at least two gate regions G1, G2to one device region; and forming a first drain region11for one of the two gate regions on a first portion of the at least one device region and a second drain region21for an other of the two gate regions on a second portion of the at least one device region.

FIGS. 6A and 6Bdepict the steps of depositing first dielectric layer51, such as silicon oxide, and a second dielectric layer52, such as silicon nitride, on a substrate49, which may also be referred to as a wafer. The substrate49may be any silicon on insulator substrate including, but not limited to: silicon-on-insulator substrates (SOI), SiGe-on-insulator (SGOI), and strained-silicon-on-insulator substrates. In another embodiment, the substrate49may be composed of bulk Si, single crystal Si, polycrystalline Si, SiGe, amorphous Si, annealed poly Si, and poly Si line structures. The SOI or SGOI substrate49may be fabricated using a thermal bonding process, or alternatively be fabricated by an ion implantation process, such as separation by ion implantation of oxygen (SIMOX).

In one embodiment, when the substrate49is a silicon-on-insulator (SOI) or SiGe-on-insulator (SGOI) substrate, as depicted inFIGS. 6A and 6B, the thickness of the semiconducting Si-containing layer53atop the buried insulating layer54can be on the order of about 10 nm or greater. In another embodiment, when the substrate49is a silicon-on-insulator (SOI) or SiGe-on-insulator (SGOI) substrate, the thickness of the semiconducting Si-containing layer53atop the buried insulating layer54can have a thickness on the order of about 20 nm or greater.

The first dielectric layer51may be an oxide. The first dielectric layer51may be composed of silicon oxide. In one embodiment, the first dielectric layer51has a thickness ranging from about 2 nm to about 20 nm. In another embodiment, the first dielectric layer51has a thickness ranging from about 2 nm to about 5 nm

The first dielectric layer51may be deposited using chemical vapor deposition (CVD). Chemical Vapor Deposition is a deposition process in which a deposited species is formed as a result of a chemical reaction between gaseous reactants at greater than room temperature (25° C. to 600° C.), wherein solid product of the reaction is deposited on the surface on which a film, coating, or layer of the solid product is to be formed. Variations of CVD processes include, but is not limited to, Atmospheric Pressure CVD (APCVD), Low Pressure CVD (LPCVD), Plasma Enhanced CVD (EPCVD), Metal-Organic CVD (MOCVD) and combinations thereof may also be employed. Alternatively, the first dielectric layer51may be formed by thermal growth, such as thermal oxidation.

The second dielectric layer52may be a nitride. In one embodiment, the second dielectric layer52is composed of silicon nitride. In one embodiment, the second dielectric layer52has a thickness ranging from about 8 nm to about 30 nm. In another embodiment, the second dielectric layer52has a thickness ranging from about 2 nm to about 6 nm.

In one embodiment, similar to the first dielectric layer51, the second dielectric layer52is deposited using chemical vapor deposition. In another embodiment, the second dielectric layer53may be formed by Molecular Layer Deposition (MLD) or Atomic Layer Deposition (ALD).

FIGS. 7A-7Cdepict one embodiment of forming of the at least one device region120. The step of forming the device region120in a Si-containing substrate49includes etching the Si-containing substrate49to provide at least one Si-containing island55, as depicted inFIG. 7C, which depicts a side cross-sectional view along section line B-B of theFIG. 7A.FIG. 7Bdepicts a side cross sectional view along section line A-A ofFIG. 7A, which illustrates the cross section along the length of a single Si-containing island55.

The device region120may be provided by etching through the second dielectric layer52, the first dielectric layer51, and the semiconducting Si-containing layer53stopping on the buried insulating layer54to provide Si-containing islands55. The Si-containing islands55may be formed using photolithography and etch processes. The lithographic step may include applying a photoresist to the second dielectric layer52, exposing the photoresist to a pattern of radiation, and developing the pattern into the exposed photoresist utilizing a resist developer. The etching step used in providing the Si-containing islands55may include an anisotropic etch process. An anisotropic etch process denotes a material removal process in which the etch rate in the direction normal to the surface to be etched is higher than in the direction parallel to the surface to be etched. In one embodiment, the anisotropic etch process is provided by reactive ion etch (RIE). Reactive ion etching (RIE) is a form of plasma etching in which during etching the surface to be etched is placed on the RF powered electrode, wherein the surface to be etched takes on a potential that accelerates the etching species extracted from a plasma toward the surface to be etched, in which the chemical etching reaction is taking place in the direction normal to the surface. In other embodiments, the etch process may include plasma etching, ion beam etching or laser ablation. Following etching, the photoresist is typically removed from the structure utilizing a resist stripping process, such as an oxygen ash.

The etch process may be a multi-stage etch. In one embodiment, a first etch stage includes an etch chemistry for removing the second dielectric layer52selective to the first dielectric layer51; a second etch stage includes an etch chemistry to remove the first dielectric layer51selective to the second dielectric layer52and the semiconducting Si-containing layer53, wherein the previously etched second dielectric layer52acts as a mask for the second stage etch; and a third etch stage includes an etch chemistry to remove the semiconducting Si-containing layer53selective to the buried insulating layer54, wherein the previously etched second dielectric layer52acts as a mask for the third etch stage. In another embodiment, the etch process may be a single stage etch. In one embodiment, the width of the Si-containing islands55ranges from about 20 nm to about 500 nm. In another embodiment, the width of the Si-containing islands55ranges from about 50 nm to about 250 nm.

FIGS. 8A-9Cdepict one embodiment of forming a gate dielectric layer56and a gate conductor layer57that are subsequently processed to provide the gate structures G1, G2.FIGS. 8A-8Cdepict one embodiment of forming a gate dielectric layer56atop a least one of the Si-containing islands55and forming a gate conductor layer57atop the gate dielectric layer56. The gate dielectric layer56may be an oxide material and is greater than about 0.8 nm thick. In another embodiment, the gate dielectric layer56may have a thickness ranging from about 1.0 nm to about 6.0 nm. The gate dielectric layer56may be a high-k gate dielectric comprised of an insulating material having a dielectric constant of greater than about 4.0. The gate dielectric layer56is a high-k gate dielectric comprised of an insulating material having a dielectric constant of greater than about 7.0. The gate dielectric layer56employed in the present invention may include, but is not limited to: an oxide, nitride, oxynitride and/or silicate including metal silicates and nitrided metal silicates. The gate dielectric layer56may be comprised of an oxide such as, for example, HfO2, ZrO2, Al2O3, TiO2, La2O3, SrTiO3, LaAlO3, Y2O3and mixtures thereof. In another embodiment, the gate dielectric layer56is a hafnium containing dielectrics. Hafnium containing high-k dielectrics include HfO2, hafnium silicate and hafnium silicon oxynitride.

The gate dielectric layer56may be thermally grown. In another embodiment, the gate dielectric layer56is deposited. One example of a deposition method for forming the gate dielectric layer56is chemical vapor deposition (CVD).

The gate conductor layer57may be comprised of polysilicon or a metal. The gate conductor layer57is formed atop the gate dielectric layer56utilizing a deposition process, such as CVD and/or sputtering. In one embodiment, the gate conductor layer57comprises doped polysilicon. The polysilicon dopant can be elements from a group III or a group V of the Periodic Table of Elements. The dopant may be introduced during deposition of the gate conductor layer or following subsequent patterning and etching of the gate conductor layer57.

FIGS. 9A-9Cdepict one embodiment of removing a portion of the gate conductor layer57and a portion of the gate dielectric layer56that are positioned atop an upper surface of the Si-containing islands55to expose the Si-containing island's upper surface, wherein a remaining portion of the gate conductor layer57and the gate dielectric layer56are positioned on a sidewall of the Si-containing islands55. The portion of the gate conductor layer57and the gate dielectric layer56that are positioned atop the upper surface of the Si-containing islands55is removed by an anisotropic etch process.

In one embodiment, the remaining portion of the gate conductor layer57that is positioned on the sidewall of the Si-containing islands55has a width ranging from about 30 nm to about 100 nm. In another embodiment, the remaining portion of the gate conductor layer57that is positioned on the sidewall of the Si-containing islands55has a width ranging from about 10 nm to about 60 nm.

FIGS. 10A to 10Ddepict one embodiment of forming of the common dopant region13that includes the first source12of the first field effect transistor10and the second source22of the second field effect transistor20. Forming the common dopant region13may include implanting an N-type or P-type dopant via ion implantation. Prior to implanting the dopant for the common dopant region13, the second dielectric layer52may be removed from the area of the structure in which the common dopant region13is to be formed using an etch process, such as a selective etch process. In one embodiment, the second dielectric layer52may be composed of silicon nitride and is removed selective to a first dielectric layer51composed of silicon oxide.

In one embodiment, the second dielectric layer52is removed from the silicon islands55along section lines A-A and B-B, as depicted inFIGS. 10A-10C. The second dielectric layer53may remain atop the structure in section lines C-C, as depicted inFIGS. 10A and 10D, and the second dielectric layer52remains atop the structure in section lines D-D, wherein the side cross-sectional view along section line D-D is equal to the side cross-sectional view along section line C-C.

In a following process step, dopants60are introduced to the common dopant region13using ion implantation. Referring toFIG. 10C, the dopants60may be implanted through the first dielectric layer51that is positioned atop the Si-containing island55. PFET devices are produced within the semiconducting Si-containing layer53of the Si-containing island55by doping with elements from group III of the Periodic Table of Elements. NFET devices are produced within semiconducting Si-containing layer53of the Si-containing island55by doping with elements from group V of the Periodic Table of Elements. In one embodiment, the implant energy may range from about 15 KeV to about 30 KeV. In another embodiment, the implant energy may range from about 5 KeV to about 10 KeV. An activation anneal may be conducted at a temperature ranging from about 850° C. to about 1350° C.

FIGS. 11A to 11Edepict one embodiment of forming a first drain region11for first gate structure G1on a first portion of the device region and a second drain region21for a second gate structure G2on a second portion of the device region. In a first process step of one embodiment of the present invention, a selective etch process in combination with a patterned photomask (not shown) removes the gate conductor57from the silicon containing islands55present in section lines B-B, as depicted inFIG. 11C, and section line D-D, as depicted inFIG. 11E, to define the gate length of the first gate structure G1and the second gate structure G2, as depicted inFIG. 11A.

More specifically, in one embodiment, the patterned photomask (not shown) is produced by applying a photoresist to the surface to be etched, exposing the photoresist to a pattern of radiation, and then developing the pattern into the photoresist utilizing conventional resist developer to produce the patterned mask. Once the patterning of the photoresist is completed, the sections of the gate conductor57covered by the patterned photomask are protected, while the exposed regions are removed using a selective etching process that removes the unprotected regions. A selective etch process may remove the exposed portions of the gate conductor57selective to the second dielectric layer52and the buried insulating layer54. In one embodiment, the gate length L1may range from about 30 nm to about 60 nm. In another embodiment, the gate length L1may range from about 20 nm to about 40 nm. In a following process step, the patterned photomask may be removed by a chemical strip process.

FIGS. 12A-12Edepict one embodiment of forming a first drain region11on a first portion of the device region and a second drain region21on a second portion of the device region. In a first step, a selective etch, such as reactive ion etching, exposes a Si-containing surface of the Si-containing island55in which the source and drain regions of the device are to be subsequently formed via ion implantation. Prior to etching a protective photomask is formed atop the portion of the device region in which the gate structures G1, G2are present, wherein the photomask boundaries having reference number200are depicted inFIG. 12A. The protective photomask is similar to the photomask used to provide the gate structures G1, G2, as described above. Following the formation of the protective photomask, the first dielectric layer51may be removed from the portions of the Si-containing islands55to provide an exposed Si-containing surface, as depicted inFIGS. 12A,12B,12C, and12E.

In a following process step, the exposed Si-containing surface of the Si-containing islands55is doped70to provide a first drain region11for a first gate structure G1on a first portion of the device region and a second drain region21a second gate structure G2on a second portion of the device region. The dopants70may be implanted into the Si-containing surface63of the Si-containing islands55via ion implantation to provide the first drain region11and the second drain region21, as depicted inFIG. 12E. PFET devices are produced within the exposed semiconducting Si-containing surface63of the Si-containing island55by implanting elements from group III of the Periodic Table of Elements. NFET devices are produced within the exposed semiconducting Si-containing surface63of the Si-containing island55by implanting elements from group V of the Periodic Table of Elements. In one embodiment, the implant energy may range from about 3 KeV to about 5 KeV. In another embodiment, the implant energy may range from about 0.5 KeV to about 3 KeV. The gate structures G1, G2may be protected from being doped during ion implantation of the drain regions by an overlying photomask (not shown), as depicted inFIG. 12D. The source region of the device may also be doped by ion implantation at this stage of the inventive method, as depicted inFIG. 12C.

Referring toFIGS. 13A-13E, in a next process step, a silicide75is formed atop the source regions13,12,22, the drain regions11,21, and the gate structures G1, G2. Silicide75formation typically requires depositing a refractory metal, such as Ni or Ti, onto the surface of a Si-containing material or wafer. Following deposition, the structure is then subjected to an annealing step using conventional processes such as, but not limited to, rapid thermal annealing. During thermal annealing, the deposited metal reacts with Si forming a metal silicide. Following silicidation, the unreacted metal may be removed by a selective etch.

Following silicide formation, a layer of dielectric material300is blanket deposited atop the entire substrate49and planarized. The blanket dielectric300may be selected from the group consisting of silicon-containing materials such as SiO2, Si3N4, SiOxNy, SiC, SiCO, SiCOH, and SiCH compounds; the above-mentioned silicon-containing materials with some or all of the Si replaced by Ge; carbon-doped oxides; inorganic oxides; inorganic polymers; hybrid polymers; organic polymers such as polyamides or SiLK™ as provided by DOW Chemical Company; other carbon-containing materials; organo-inorganic materials such as spin-on glasses and silsesquioxane-based materials; and diamond-like carbon (DLC, also known as amorphous hydrogenated carbon, α-C:H). Additional choices for the blanket dielectric300include: any of the aforementioned materials in porous form, or in a form that changes during processing to or from being porous and/or permeable to being non-porous and/or non-permeable.

The blanket dielectric material300may be formed by various methods well known to those skilled in the art, including, but not limited to: spinning from solution, spraying from solution, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), sputter deposition, reactive sputter deposition, ion-beam deposition, and evaporation.

The deposited dielectric is then patterned and etched to form via holes to the various source/drain and gate conductor regions of the memory device110. Following via formation, interconnects are formed by depositing a conductive metal350into the via holes using conventional processing, such as CVD or plating. The conductive metal350may include, but is not limited to: tungsten, copper, aluminum, silver, gold, and alloys thereof.

In one embodiment, the present invention provides a memory device110that is suitable for SRAM applications, in which the memory function is provided by hole traps40,50at a Si/SiO2interface. In one embodiment, the present invention improves SRAM density by employing 2-T SRAM per cell and providing utilizing optimized routing. In one embodiment, the memory device110provides improves stand-by leakage, wherein only the lgd-off contributes to the leakage of the cell. In another embodiment, the present invention improves threshold voltage mismatch and thus provides increased stability. In a further embodiment, by applying a design that utilizes an asymmetrical source and drain layout the present invention enables increased scaling.

In one example, the above-described structures and methods can be employed to provide a 2-T SRAM cell structure that provides approximately 6 Gbits memory in 100×150 nm2/cells on 1.0 cm2area having a low stand-by leakage stand-by on the order of about 1 pA per cell or less, wherein only edge currents contribute to the leakage of the device.

While the present invention has been particularly shown and described with respect to the preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in forms of details may be made without departing form the spirit and scope of the present invention. It is therefore intended that the present invention not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.