Half-bridge power converter system and method of operation

In one embodiment, a power converter generates an output voltage by modulating an input voltage according to operations of a first switch and a second switch connected in a half-bridge arrangement. The power converter includes a switch driver circuit for controlling the turning on and off of the first and second switches. A PWM controller generates a switch driver control signal for controlling the switch driver circuit according to an output voltage. The switch driver circuit generates an on-time control signal for turning off the first switch when the first switch has been turned on for longer than a threshold period.

This application claims priority to and the benefit of Korean Patent Application No. 10-2006-0043765 filed in the Korean Intellectual Property Office on May 16, 2006, the entire content of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to power converters, and more particularly, a half-bridge power converter system and a method of operation.

2. Description of the Related Art

A bridge power converter is an insulation-type converter and is commonly used in a middle-sized to large-sized power module. A bridge power converter can be classified as a half-bridge power converter or a full-bridge power converter depending on the number of switches and the location of the switches.

A conventional half-bridge converter includes a high voltage or high-side switch, which is turned on and off according to a pulse width modulation (PWM)-based control method. However, when the high-side switch is turned on for a relatively long period of time, several problems may occur. For instance, when a half-bridge converter is used in a resonance-type power converter, the resonant capacitor may be fully discharged and/or the transformer of the converter may go into saturation. In addition, power is consumed in the high-side switch (which is inefficient) and the switch may be damaged.

SUMMARY OF THE INVENTION

In one aspect of the present invention, a half-bridge power converter system includes a switch driver circuit and a pulse width modulation (PWM) controller. The half-bridge converter generates an output voltage by modulating an input voltage according to operations of a first switch and a second switch coupled in a half-bridge arrangement. The switch driver circuit controls turning on/off of the first and second switches. The PWM controller generates a switch driver control signal for controlling the switch driver circuit according to the output voltage. If the first switch has been turned on for longer than a threshold period, the switch driver circuit generates a control signal for turning off the first switch.

In another aspect of the present invention, a switch driving apparatus is provided for controlling the turning on and off of a first switch and a second switch in a half-bridge power converter. The switch driving apparatus includes an input terminal for receiving an input control signal. A first dead-time controller provides a first control signal to keep the first switch turned off for a first dead-time period after the input control signal transitions from a first level to a second level. A second dead-time controller provides a second control signal to keep the second switch turned off for a second dead-time period after the input control signal transitions from the second level to the first level. An on-time controller provides an on-time control signal for turning off the first switch if the first switch has been turned on for longer than a threshold period.

In yet another aspect of the present invention, a method is provided for driving a power converter system that modulates an input voltage by using operations of a first switch and a second switch connected in a half-bridge arrangement. The method includes: generating a first switch control signal and a second switch control signal for respectively controlling the first switch and the second switch; generating an on-time control signal when the first switch control signal is maintained at a first level for longer than a first period; and performing a logic operation on the on-time control signal and the first switch control signal and generating a first switch off signal according to a result of the logic operation.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Embodiments of the present invention and their advantages are best understood by referring toFIGS. 1 through 3of the drawings. In the following detailed description, only certain exemplary embodiments of the present invention have been shown and described, simply by way of illustration. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not restrictive. Like reference numerals designate like elements throughout the specification.

Throughout this specification and the claims which follow, when an element is described as coupled to another element, the element may be directly coupled to the other element or electrically coupled to the other element through one or more other elements.

According to some embodiments of the invention, a half-bridge power converter system and a driving method thereof prevent power consumption when a switch is maintained in the turn-on state for a relatively long or excessive period of time.

FIG. 1is a schematic diagram of an exemplary implementation for a half-bridge power converter system10, according to an embodiment of the present invention. As shown inFIG. 1, the half-bridge power converter system10includes a switch driver block1, a pulse width modulation (PWM) controller block2, a bootstrap block3, a high voltage or high-side switch (Q1)20, a low voltage or low-side switch (Q2)22, a resonant capacitor (Cr)24, an inductor (Lm)26, a transformer4, and an output block5(at which an output voltage Vout is provided). In one embodiment, as shown, the high-side switch20and the low-side switch22of the exemplary can be implemented as N-type metal-oxide-semiconductor field effect transistors (MOSFETs), each having a gate (or control) electrode, a drain electrode, and a source electrode.

The switch driver block I may provide control signal to turn on and off the high-side switch20and the low-side switch22according to one or more switching control signals from the PWM controller block2. The PWM controller block2generates the one or more control signal (hereinafter referred to as a “switching control signal IN”) for controlling the high-side switch20and the low-side switch22, thereby controlling the level of the output voltage Vout provided at the output block5.

The bootstrap block3can include a bootstrap diode (Dbs)28and a bootstrap capacitor (Cbs)30. The bootstrap diode28is biased in a forward direction from a power source Vcc to the bootstrap capacitor30, which thus charges the bootstrap capacitor30to a predetermined voltage level. The charged voltage is provided to the switch driver block1, and is then used for controlling the high-side switch20.

The transformer4may include a primary coil (L1)30, a secondary coil (L2)32, and a third coil (L3)34. The primary coil30, in a primary side of the transformer4, can be coupled to the resonant capacitor24and the inductor26. The secondary coil32and the third coil34, in a secondary side of the transformer4, are coupled to an output capacitor (Cout)36of the output block5. The transformer4supplies power to the secondary side by using an input voltage transmitted to the primary side according to a duty ratio of the high-side switch20.

The output block5includes a first diode (D1)38, a second diode (D2)40, and the output capacitor36. The first diode38and the second diode40control or direct the flow of current from the secondary coil32or the third coil34to the output capacitor36. The first and second diodes38and40in the output block5direct or control current flow inducted to the secondary side of the transformer4. The output capacitor36may eliminate ripple from the output voltage Vout, and is charged by the current delivered through the first diode38and second diode40. When the first diode38and the second diode40are open, the output capacitor36supplies or provides the output voltage Vout to a load coupled to the output terminal of the system10.

The high-side switch20and the low-side switch22are coupled together at a node M in a half-bridge arrangement. The high-side switch20may be coupled to the primary side of the transformer4. The drain electrode of the high-side switch20receives the input voltage Vin. The gate electrode of the high-side switch20is coupled to the switch driver block1. The source electrode of the high-side switch20is coupled to the drain electrode of the low-side switch22at the node M. The gate electrode of the low-side switch22is coupled to the switch driver block1. The source electrode of the low-side switch22is coupled to a ground voltage Vg. The high-side switch20and the low-side switch22include parasitic capacitors (CQ1)50and (CQ2)52and parasitic diodes (DQ1)54and (DQ2)56.

The switch driver block I provides control signals HO and LO for turning on and off the high-side and low-side switches20,22. As depicted, switch driver block I includes a high-side switch controller13(which outputs the control signal HO) and a low-side switch controller12(which outputs the control signal LO). An exemplary implementation of the switch driver block1, according to an embodiment of the present invention, is described in further detail with reference toFIG. 2.

FIG. 2is a schematic diagram of an exemplary implementation for switch driver block1, according to an embodiment of the present invention. As shown inFIG. 2, the switch driver block I includes low-side switch controller12and high-side switch controller13. Each of the high-side switch controller13and the low-side switch controller12receives the switching control signal IN from the PWM controller2.

Low-side switch controller12outputs the control signal LO for controlling the low-side switch22. The low-side switch controller12may include a first dead-time controller121and a driver or level shifter circuit122.

The dead-time controller121of the low-side switch controller12receives the switching control signal IN (from PWM controller block2). The dead-time controller121detects a change of the level of the switching control signal IN from low to high, and in response provides a value for the control signal LO to maintain or turn off the low-side switch22for some period of time so as to create a “dead time” during which both switches of the half-bridge are turned off. In one embodiment, the dead-time controller121provides a low level output to the level shifter circuit122during the dead-time period. The implementation of dead-time controller121would be understood to one of ordinary skill in the art based on its description herein.

The level shifter circuit122may include an N-type channel transistor (Q21)140and a P-type channel transistor (Q22)142. In one embodiment, as shown, the N-type channel transistor140and the P-type channel transistor142are respectively an N-type bipolar junction transistor (BJT) and a P-type BJT. The level shifter circuit122outputs the control signal LO, which may have a value of either Vcc or Vg depending on the control signal from the dead-time controller121. When a level of the control signal from dead-time controller121is high, transistor140is turned on and transistor142is turned off, and thus the level shifter circuit122outputs a value of Vcc for the control signal LO, which turns on the low-side switch22. When the level of the control signal from dead-time controller121is low, transistor140is turned off and transistor142is turned on, and thus the level shifter circuit122outputs a value of Vg or ground for the control signal LO, which turns off the low-side switch22.

High-side switch controller13outputs the control signal HO for controlling the high-side switch20. The high-side switch controller13may include a dead-time controller131, a duty ratio controller132, an AND gate133, an inverter134, and a driver of level shifter circuit135.

The inverter134inverts the switching control signal IN and provides the inverted control signal to the dead-time controller131and the duty ratio controller132. The dead-time controller131, which receives the inverted control signal, detects a change of level of the inverted switching control signal from low to high (which corresponds to a change in the level of the (non-inverted) switching control signal IN from high to low). In response, the dead time controller131provides a value to maintain or turn off the high-side switch20for some period of time so as to create a “dead time” during which both switches of the half-bridge are turned off. In one embodiment, the dead-time controller131provides a low level output to the AND gate133during the dead-time period. The implementation of dead-time controller131would be understood to one of ordinary skill in the art based on its description herein.

The duty ratio controller132receives the inverted switching control signal from the inverter134. Duty ratio controller132implements or provides a timer which determines or keeps track of how long the high-side switch20has been turned on. If the high-side switch20has been turned on for longer than a predetermined period (hereinafter referred to as a “threshold period”), the duty ratio controller132generates a control signal to cause the high-side switch20to be turned off. In one embodiment, the duty ratio controller132outputs a high level output signal to the AND gate133until it determines that the on time for high-side switch20has exceeded the threshold period. When the on time for high-side switch20has exceeded the threshold period, duty ratio controller132provides a low level output to the AND gate133, which causes the high-side switch20to be turned off. In some embodiments, the threshold period may be the same as a duty ratio of the switching control signal, but the invention is not so limited. The threshold period may be set to prevent damage to the high-side switch20, to prevent the resonant capacitor24from being fully discharged, or to prevent the saturation of the transformer4. The implementation of the duty ratio controller132would be understood to one of ordinary skill in the art based on its description herein.

The AND gate133performs an AND operation on the control signals from the dead-time controller131and the duty ratio controller132. The AND gate133generates an output control signal according to the operation result. The output control signal from the AND gate is provided to the first level shifter circuit135.

The level shifter circuit135may includes an N-type channel transistor (Q11)144and a P-type channel transistor (Q12)146. In one embodiment, as shown, the N-type channel transistor144and the P-type channel transistor146are respectively an N-type BJT and a P-type BJT. The level shifter circuit135outputs the control signal HO, which may have a value of either Vbs or Vs depending on the switch control signal IN. When a level of the output control signal from the AND gate133is high, transistor144is turned on and transistor146is turned off, and thus the level shifter circuit135outputs a value of Vbs for the control signal HO, which turns on the high-side switch20. When the level of the control signal from AND gate133is low, transistor144is turned off and transistor146is turned on, and thus the level shifter circuit135outputs a value of Vs for the control signal HO, which turns off the low-side switch22.

A voltage level of Vcc for the control signal LO and a voltage level of Vbs for the control signal HO, respectively, turn on the low-side switch22and the high-side switch20. A voltage level of Vg for the control signal LO and a voltage level of Vs for the control signal HO, respectively, turn off the low-side switch22and the high-side switch20.

An exemplary method of operating the half-bridge power converter system10according to an embodiment of the present invention will now be described in further detail with reference toFIG. 3.

FIG. 3is a waveform diagram200illustrating an exemplary operation for half-bridge power converter system10, according to an embodiment of the present invention. Waveform diagram200includes exemplary waveforms202,204, and206. Waveform202represent the switching control signal IN output from PWM controller2. Waveforms204and206represent the high-side switch control signal HO and the low-side switch control signal LO, respectively output from the high-side switch controller13and the low-side switch controller12of the switch driver circuit1.

At a time T0, dead-time controller131in the high-side switch controller13detects a change in the level of the switching control signal IN from high to low. In response, dead-time controller131provides a control signal to keep high-side switch20turned off for some period of time—i.e., from time T0to time T1. This period between T0and T1can be a dead-time period, during which both control signals HO and LO are low, thus turning off the high-side switch20and the low-side switch22. During the dead-time period from T0to T1, an inverted current flows through the high-side switch20due to its parasitic diode54. While current flows through the parasitic diode54, zero-voltage switching occurs, and the high-side switch20is turned on at time T1.

During the period from T1to T2, the high-side switch20is turned on and the low-side switch22is turned off. Resonant capacitor24and inductor26generate a resonance such that a resonant current flows in one direction in primary coil30of the transformer4. This causes current flow in the third coil34of the transformer4. The diode40in the output circuit5is turned on and current flows in a forward direction from the third coil34of the transformer4to charge the output capacitor36, thereby increasing the output voltage Vout. The resonant current increases to a predetermined level with a sine wave line, and then decreases at time T2. At this time, the diode38is turned off.

At a time T2, dead-time controller121in the low-side switch controller12detects a change in the level of the switching control signal IN from low to high. In response, dead-time controller121provides a control signal to keep low-side switch22turned off for some period of time—i.e., from time T2to time T3. This period between T2and T3can be another dead-time period, during which both control signals HO and LO are low, thus turning off the high-side switch20and the low-side switch22. During the dead-time period from T2to T3, the resonant capacitor24and the inductor26, by resonance, discharges the parasitic capacitor52of the low-side switch22through the parasitic diode56. The output voltage Vout drops to near 0V at this time.

At time T3, the low-side switch22is turned on. Then, a voltage at the primary side of the transformer4becomes equal to the input voltage Vin, and a constant voltage is induced in the secondary side of the transformer4. This causes current to flow from the secondary coil32through diode38of the output circuit5. At this time, the diode40is turned off.

During the period from T3to T4, the low-side switch22is turned on and the high-side switch20is turned off. Current flows through the primary coil30of the transformer4to the ground voltage Vg through the low-side switch22. Current flows from the secondary coil32of transformer4through the diode38to charge capacitor36. After a predetermined time has passed, current ceases to flow through the primary coil30of the transformer4. Then, no current is generated in the secondary side of the transformer4so that the diodes38and40are both turned off. At this time, the output capacitor36discharges so that current flows to a load coupled to the output terminal, thereby supplying power.

By repeating the above process, the half-bridge power converter system10converts the input voltage Vin into an output voltage Vout of a predetermined level to supply power to the load.

However, if during operation of system10the high-side switch20is turned on for a relatively long or excessive period of time, embodiments of the present invention function to turn off the high-side switch20to prevent power consumption and possible damage to the switch.

For example, referring toFIG. 3, such a relatively long or excessive period of time for the high-side switch20to be turned on may be the period from time T5to time T6. If this occurs, the duty ratio controller132determines that the high-side switch20has been turned on for longer than the threshold period. The duty ratio controller132then outputs a control signal for turning off the switch20. In one embodiment, for example, the duty ratio controller provides a low level output signal to the AND gate133. The AND gate133receives the low level signal, and provides a low level output control signal to the first level shifter circuit135, according to the AND operation. In turn, the first level shifter circuit135outputs a low level voltage Vs for the high-side control HO, which turns off the high-side switch20.

As described, embodiments of the invention prevent the high-side switch20in half-bridge power converter system from being turned on for a relatively long or excessive periods of time. Thus, the half-bridge converter can operate under stable conditions. In addition, by keeping track of and responding to the turn-on time of the high-side switch, embodiments of the present invention prevent the full discharge of a resonant capacitor in the half-bridge converter, saturation of a transformer, and power consumption in the high-side switch.

Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made therein without departing from the spirit and scope of the invention as defined by the appended claims. That is, the discussion included in this application is intended to serve as a basic description. It should be understood that the specific discussion may not explicitly describe all embodiments possible; many alternatives are implicit. It also may not fully explain the generic nature of the invention and may not explicitly show how each feature or element can actually be representative of a broader function or of a great variety of alternative or equivalent elements. Again, these are implicitly included in this disclosure. Where the invention is described in device-oriented terminology, each element of the device implicitly performs a function. Neither the description nor the terminology is intended to limit the scope of the claims.