Semiconductor device and a method of manufacturing a semiconductor device

A semiconductor device is provided, including a MOSFET die, a first GaN die and a second GaN die. The first GaN die and the second GaN die are arranged in a cascode arrangement. The second GaN die is positioned in an inverted orientation. The MOSFET die controls the first GaN die and the second GaN die.

CROSS REFERENCE TO RELATED APPLICATION

This application claims the benefit under 35 U.S.C. § 119(a) of European Application No. 21157354.8 filed Feb. 16, 2021, the contents of which are incorporated by reference herein in their entirety.

BACKGROUND OF THE DISCLOSURE

1. Field of the Disclosure

The present disclosure relates to a semiconductor device comprising a MOSFET die and two GaN dies that are arranged in a cascode configuration. The disclosure also relates to a method of manufacturing a semiconductor device.

2. Description of the Related Art

It is known in the art that GaN technology and specifically GaN-on-Silicon HEMT technology has become very interesting over the last few years. The GaN technology can be used for applications that require the high-power performance and high-frequency switching. The GaN technology is optimistic applicant for future high-power and high-frequency applications, it is very promising for future power and high frequency applications. In particular, the GaN high electron mobility transistor (HEMT) grown on Si substrate is suitable for high frequency and high power switching applications.

Taking into account the physical and electrical nature of GaN HEMT devices, there is one obvious challenge. A GaN HEMT's natural operation mode is as a depletion mode FET with a naturally “on” state. That is different from a stereotype where the devices are naturally “off” devices. There is also a benefit with “off devices from a safety perspective. Therefore, a work around of the natural state of GaN HEMTs is needed to deliver naturally “off” operation. Currently there are two main approaches to this challenge. One is to change the structure of the device to operate in enhancement mode (or e-mode). The second is a stacked die cascode packaged device, shown inFIG.1a, with a naturally “off” low-voltage, low RDSon silicon MOSFET12placed in series to the naturally “on” GaN HEMT device10. The device shown inFIG.1ais an example of a single cascode circuit known in the art.

Another device known in the art is shown inFIG.1b. In this case a single FET18is used to control two HEMT devices, a first HEMT device14and a second HEMT device16. It is also noted that a skilled person can use a single FET to control two or multiple HEMT devices.

Normally GaN surface mount packages are used instead of traditional through-hole packages with a goal to reduce the package resistance, parasitic inductances and also the size of a product device. This also helps increasing the power density.

Furthermore, it is advantageous GaN package using a copper (Cu) clip interconnects design, since that improves the package resistance and inductance in a smaller footprint.

The disadvantage of the semiconductor devices as described above is that for multiple fast switching packaged devices that are in parallel layout, it is very difficult to achieve a stable performance.

SUMMARY

Various example embodiments are directed to the disadvantage as described above and/or others which may become apparent from the following disclosure.

According to an embodiment of this disclosure a semiconductor device comprises a MOSFET die, a first GaN die and a second GaN die. The first GaN die and the second GaN die are arranged in a cascode arrangement. In such configuration, the first GaN die is positioned in a normal/non-inverted orientation. The second GaN die is positioned in an inverted orientation.

The MOSFET die controls the first GaN die and the second GaN die. The semiconductor device can further comprise a first clip with two independent parts that are connected by a tie bar. A first part of the first clip is positioned on the top of a source pad of the first GaN die. This first part of the first clip, which is connected to the source pad of the first GaN die, will act as a die paddle for the MOSFET, while a second part of the first clip is a drain connection of the first GaN die.

The semiconductor device can further comprise a second and common attach clip with pillars. The second attach clip is positioned on the top of the second GaN die, so to connect the gates of both, the first GaN die and the second GaN die, to the source of the MOSFET die.

The MOSFET's drain, attached on the first clip/die paddle, is connected to a common source terminal of both, the first GaN die and the second GaN die.

The drain of the second GaN die is also using a common terminal, which is extended to the outside of package, forming gull wing leads.

The semiconductor device as described in the above embodiments can also realize by a skilled person with a bottom cooling or with a dual cooling.

The disclosure also relates to a method of producing a semiconductor device. The method comprises the following steps:Print/deposit a first solder or adhesive and attach a first GaN die on a die pad of a semiconductor device,print/deposit a second solder or adhesive on a drain pad and on a source pad of the first GaN die,attach a first two parts clip with tie bars on the top of the first GaN die,print/deposit the third solder or adhesive on the first two parts clip,attach a MOSFET die,attach a second GaN die in an upside-down/flipped orientation,print/deposit a fourth solder or adhesive on the top of the MOSFET die and the second GaN die,attach a second clip with pillars on the top of the MOSFET die and the second GaN die, so to connect both, a gate of the first GaN die and a gate of the second GaN die to a source of the MOSFET die, andattach a gate clip, or any interconnect such as wire or ribbon, for the MOSFET die so to complete the circuit.

Furthermore, the method can comprise other steps common in the production of the semiconductor devices:moulding,deflash,plating,trim,form,cutting external tie bars, andsingulation.

The semiconductor device according to the above described embodiments, wherein the first GaN die and the second GaN die are stacked, secures very stable performance. It is much better performance compared to the known semiconductor device wherein the first GaN die and the second GaN die are arranged in a parallel layout.

Such an arrangement, wherein the first GaN die and the second GaN die are stacked ensures more consistent performance of the device, in particular a low package resistance and low parasitic inductances. Also the size of semiconductor device is significantly reduced, which makes this disclosure very cost effective.

Furthermore, the disclosure describes an inventive arrangement/layout that allows very good thermal control of the package/semiconductor device.

DETAILED DESCRIPTION

FIG.2illustrates an embodiment of the present disclosure. A semiconductor device package100comprises a metal oxide semiconductor field effect transistor (MOSFET) die102and two GaN dies104and106, a first GaN die104and a second GaN die104. The first GaN die104and the second GaN die106are arranged in a cascode formation, i.e. stacked. The MOSFET die102is arranged to drive or switch both, the first GaN die104and the second GaN die106. The MOSFET die can be also a FET die. The first GaN die can be a first HEMT die. The second GaN die can be a second HEMT die.

Such an arrangement within the semiconductor device100, wherein the first GaN die104and the second GaN die106are stacked ensures that the semiconductor is significantly reduced in size and also better electrical performances.

In an embodiment of the present disclosure a first GaN die104is positioned in a normal, i.e. usual orientation, wherein a drain and a source of the first GaN die104are pointing upwards within the semiconductor device100. A second GaN die106is positioned in an opposite orientation, wherein a drain and a source of the second GaN die106are pointing downwards within the semiconductor device100.

A first two parts clip108and105, integrated by a tie bar (not shown in the figures) are used on the top of the first GaN104. The first part becomes a die paddle105of the MOSFET die102while the second part will be the common drain clip108of the first GaN die104and the second GaN die106. A second attach clip with pillars107is used-on the top of a second GaN die106, so to connect the gates of both the first GaN die104and the second GaN die106to the source of the MOSFET die102.

Moreover, the MOSFET die is attached on the die paddle105, as a MOSFET die drain, connected to a common source terminal of both, the first GaN die104and the second GaN die106. The drain of the second GaN die is also using a common terminal, which is extended to the outside of the semiconductor device, in this way forming gull wing leads, which significantly improves the respective board level reliability performance.

According to an embodiment of the present disclosure, the above described semiconductor device can be used for both, bottom cooling packages120and dual cooling packages122, which are shown inFIG.2.

According to an embodiment of the disclosure, a method of manufacturing a semiconductor device is disclosed. The semiconductor device comprises a MOSFET die, a first GaN die and a second GaN die stacked within the semiconductor device. The method is illustrated inFIG.3.

The method comprises the steps:reference sign200inFIG.3:print or deposit a first solder or a first adhesive and attach a first GaN die222on a die pad230of a semiconductor deviceprint or deposit a second solder or a second adhesive234on a drain pad and on a source pad of the first GaN die222reference sign202inFIG.3:attach a first two parts clip232integrated by a tie bar233on the source and the drain of the first GaN die222reference sign204inFIG.3:attach a MOSFET die220attach a second GaN die224(wherein the source and drain solderable pads are not visible inFIG.3) in an upside-down orientationprint or deposit a third solder or a third adhesive236on top of the MOSFET die220and the second GaN die224reference sign206inFIG.3:attach a second clip with pillars238on the top exposed surface of the MOSFET die220and the exposed surface of second GaN die224, so to connect both, a gate of the first GaN die222and a gate of the second GaN die224to a source of the MOSFET die220attach a third clip239, or any interconnect such as wire or ribbon, on MOSFET gate towards a gate pad240so to complete the device circuit.reference sign208inFIG.3:mouldingdeflashplatingreference sign210inFIG.3:dam bar cuttingtrimformreference sign212inFIG.3:cutting external tie bars, andsingulation.

According to the embodiment of the present disclosure, as described above, the drain and the source of both, the first GaN die and the second GaN die, are connected through a two parts clip with external tie bars. The source terminals and the drain terminals of both, the first GaN die and the second GaN die, are disconnected by cutting the external tie bars.

The semiconductor device, wherein the first GaN die and the second GaN die are stacked secures very stable performance, compared to the known semiconductor devices wherein the first GaN die and the second GaN die are arranged in a parallel layout.

In general, a drain-source on resistance (RDSon) reduction can be achieved by increasing a GaN die size. However, making the Gan die too large, introduces limitations, e.g. spreading resistance, die aspect ratio, yield, assembly reliability, etc.

This problem is fully solved by a semiconductor device as described in the embodiments of the present disclosure. A clip-bonded GaN package with a single MOSFET die to control multiple GaN dies is advantageous due the following:allowing much more power to be switched by using multiple and parallel GaN dies:low parasitic inductances, low switching losses, andlow RDSon, lower conduction losses.

Using only one large MOSFET die ensures that all the GaN dies switch at the same time. Such an inventive arrangement/layout allows very good thermal control of the package/semiconductor device.

This could be arranged as a bottom cooling package/semiconductor device, or a dual sided cooling package/semiconductor device.

Having the first GaN die and the second GaN die in a cascode arrangement is additionally a printed circuit board space saver, which makes this disclosure also very cost effective.

The present disclosure is not limited to the above described embodiments. All similar embodiments and obvious variations of the above embodiments are covered by the present disclosure. Some of the applications of the present disclosure include: a GaN package, a clip bonded package, a power semiconductor package, etc.

Particular and preferred aspects of the disclosure are set out in the accompanying independent claims. Combinations of features from the dependent and/or independent claims may be combined as appropriate and not merely as set out in the claims.

The scope of the present disclosure includes any novel feature or combination of features disclosed therein either explicitly or implicitly or any generalisation thereof irrespective of whether or not it relates to the claimed disclosure or mitigate against any or all of the problems addressed by the present disclosure. The applicant hereby gives notice that new claims may be formulated to such features during prosecution of this application or of any such further application derived therefrom. In particular, with reference to the appended claims, features from dependent claims may be combined with those of the independent claims and features from respective independent claims may be combined in any appropriate manner and not merely in specific combinations enumerated in the claims.

The term “comprising” does not exclude other elements or steps, the term “a” or “an” does not exclude a plurality. Reference signs in the claims shall not be construed as limiting the scope of the claims.