IPS mode liquid crystal display device and manufacturing method thereof

An IPS mode LCD for improving image quality and a manufacturing method thereof are provided. When a common-voltage supply line and common lines are formed on different layers using different materials and connected via a contact hole, a contact resistance is increased due to an increase of a contact area and thus common signals are delayed. To solve the common signal delay, the common-voltage supply line and the common lines are integrally formed using the same material so that common signals are applied to the common lines without delay. Thus, preventing image quality deterioration due to the delay of the common signals.

This application claims the benefit of Korean Patent Application No. 2004-118485, filed on Dec. 31, 2004, which is hereby incorporated by reference for all purposes as if fully set forth herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a liquid crystal display device (LCD), and more particularly, to an in-plane-switching (IPS) mode LCD and a manufacturing method thereof.

2. Description of the Related Art

Cathode ray tubes (CRTs) have been most widely used for display devices to display image information on a screen. However, the CRTs are large and heavy in their volume and weight for their display region and so there has been much inconvenience in an aspect of use.

With the recent development of the electronic industry, display devices whose usage has been limited to a television (TV) braun tube are now widely used for personal computers (PCs), notebook computers, automobile instrument panels, and electronic display boards. With development of information and telecommunication technology, next-generation display devices that are capable of processing and realizing large-capacity image information is emerging as an important issue.

The next-generation display devices should be lightweight, slim in profile, have high brightness, a large screen, low power consumption, and a low price. As one of the next-generation display devices, LCDs are drawing attention.

The display resolution in LCDs is excellent compared to other display devices and a response time is as fast as CRTs when displaying moving images.

The types of LCDs primarily being used are twisted nematic (TN) mode LCDs. In TN mode LCDs, electrodes are installed on two substrates, respectively, a director of liquid crystal molecules is arranged so as to be twisted 90 degrees, and then a voltage is applied to the respective electrodes so that the director of the liquid crystal molecules is driven.

However, the TN mode LCD has a crucial disadvantage of a narrow viewing angle.

To solve the narrow viewing angle problem, studies on LCDs adopting a variety of new modes are actively in progress. Examples of such modes includes an IPS mode and an optically compensated birefringence (OCB) mode.

The IPS mode LCDs have two electrodes formed on the same substrate so as to drive the liquid crystal molecules with the molecules maintained parallel with respect to the substrate, applies a voltage between the two electrodes to generate a horizontal, transverse electric field with respect to the substrate. That is, a longitudinal axis of the liquid crystal molecules is not allowed to stand up with respect to the substrate.

Therefore, the IPS mode LCDs have a small variation in a birefringence of the liquid crystal molecules with respect to a vision direction, and thus have far better viewing angle characteristics compared to the TN mode LCDs of a related art.

A structure of the IPS mode LCDs of the related art will be described below with reference to the accompanying drawings.

FIG. 1is a schematic, plan view of the IPS mode LCDs of the related art andFIG. 2is a cross-sectional view taken along line A-A′ ofFIG. 1.

As illustrated inFIGS. 1 and 2, IPS mode LCDs include: a plurality of gate lines112horizontally arranged in parallel with each other, and spaced a predetermined interval on a substrate110; a plurality of common lines116horizontally arranged in parallel with each other, closely to the gate lines112; and a plurality of data lines124crossing with the gate line112and common line116and vertically arranged and spaced a predetermined interval, for defining a pixel region P together with the gate lines112.

A thin film transistor (TFT) T that includes a gate electrode114, semiconductor layers (not shown), a source electrode126, and a drain electrode128are formed at crossings of the gate lines112and the data lines124. The source electrode126is connected with the data line124and the gate electrode114is connected with the gate line112.

A gate pad152is formed at one end of the gate lines112. On the gate pad152, a gate pad upper electrode153is connected with the gate pad152through a contact hole155that passes through a gate insulation layer118and a passivation layer134.

A pixel electrode130connected with the drain electrode128and a common electrode117arranged in parallel with the pixel electrode130and connected with the common lines116are formed on an upper part of the pixel region P.

The pixel electrode130includes: a plurality of vertical parts130bextended from the drain electrode128, formed in parallel with the data lines124, and spaced a predetermined interval each other; and a horizontal part130afor incorporating the vertical parts130binto one part at an upper portion of the common lines116.

The common electrode117includes: a plurality of vertical parts117bvertically extended from the common lines116and alternately formed in parallel with the vertical parts130bof the pixel electrode130; and a horizontal part117afor incorporating the vertical parts117binto one part.

The horizontal part130aof the pixel electrode130is formed with the gate insulation layer118interposed on part of the common lines116and forms a storage capacitor C together with the common lines116.

The common lines116and the common electrode117are made of the same material as the gate lines112and formed on the same layer as the gate lines112.

The gate lines112and the data lines124have, at their one end, an input pad for applying scanning signals and data signals provided from an external printed circuit board (PCB) to the gate lines112and the data lines124.

The common lines116arranged in parallel with the gate lines112are connected with a common-voltage supply line159provided to an outer block of a panel.

Since the common-voltage supply line159is formed in a direction that crosses the gate lines112so as to incorporate the common lines116into one line, the common-voltage supply line159is made of the same material as the data lines124and formed on the same layer as the data lines124so as to avoid connection of the gate lines112and the common-voltage supply line159on the same plane.

Therefore, since the common-voltage supply line159made of the same material as the data lines124has the gate insulation layer118interposed on a space between the common-voltage supply line159and the common lines116, a contact hole165bis formed in the common lines116and another contact hole165ais formed in the common-voltage supply line159so that the common lines116are connected with the common-voltage supply line159by a jumping electrode166.

With this configuration, in case the common lines116and the common-voltage supply line159are formed using different material and connected using the jumping electrode166as described above, common signals pass through PCB-> TCP (tape carrier package)-> a common-voltage supply line (data line material)->a jumping electrode and is finally applied to the common lines (gate line material).

In that case, a resistance of the data line material is larger than that of the gate line material. Further, in the case that a contact area for the common lines is made large so as to secure a contact area for the jumping electrode166, a contact resistance is increased. Thus, a contact resistance for an external TCP is increased and common signals applied from the outside are delayed. Signal delay due to the large contact resistance between the common lines and the jumping electrode causes image quality deterioration.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to an IPS mode LCD and a manufacturing method thereof that substantially obviates one or more problems due to limitations and disadvantages of the related art.

An advantage of the present invention is to provide an IPS mode LCD and a manufacturing method thereof capable of improving image quality by forming common lines and common-voltage supply line using the same material to prevent delay of common signals.

To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, there is provided an IPS mode LCD, which includes: a plurality of gate lines formed in a first direction on a substrate; a plurality of common lines formed substantially parallel to the gate lines in the first direction; a common-voltage supply line integrally formed with the common lines; a plurality of data lines formed in a second direction that perpendicularly crosses the first direction of the gate lines; a TFT formed at a crossing of the gate lines and the data lines; a plurality of common electrodes extended from the common lines; and a plurality of pixel electrodes arranged in an alternating pattern with the common lines.

In another aspect of the present invention, there is provided a method for manufacturing an IPS mode LCD, which includes: forming a plurality of gate lines having a first direction, a plurality of common lines substantially parallel to the gate lines, a plurality of common electrodes extending from the common lines, and a common-voltage supply line having the first direction and integrally connected at one end of the common lines; forming a plurality of data lines in a second direction so as to cross the gate lines; forming source and drain electrodes, wherein the source electrodes are extended from the data lines; and forming a pixel electrode connected with the drain electrode.

In another aspect of the present invention, there is provided an IPS mode LCD that includes a first metal layer including a plurality of gate lines, a plurality of common lines, a plurality of common electrodes, and a common-voltage supply line integrally formed with the common lines; a second metal layer including a plurality of data lines, and source and drain electrodes; and a third metal layer including a plurality of pixel electrodes and a jumping electrode.

In another aspect of the present invention, there is provided a method of manufacturing an in-plane switching (IPS) mode liquid crystal display device (LCD) that includes, forming a first metal layer including a plurality of gate lines, a plurality of common lines, a plurality of common electrodes, and a common-voltage supply line integrally formed with the common lines; forming a second metal layer including a plurality of data lines, and source and drain electrodes; and forming a third metal layer including a plurality of pixel electrodes and a jumping electrode.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

FIG. 3is a plan view of IPS mode LCDs according to the present invention andFIG. 4is a cross-sectional view taken along line B-B′ ofFIG. 3.

InFIGS. 3 and 4, the IPS mode LCDs includes: a plurality of gate lines212horizontally arranged substantially parallel with each other and spaced a predetermined interval on a substrate210; a plurality of common lines216horizontally arranged substantially parallel with each other, and closely to the gate lines212; and a plurality of data lines224crossing with the gate line212and common line216, vertically arranged substantially parallel with each other and spaced a predetermined interval, to define a pixel region P together with the gate lines212.

A plurality of common electrodes217extend to the pixel region P and are connected with the common lines216. The plurality of common electrodes may extend in a direction substantially perpendicular to a direction of the common lines216.

A gate pad252is formed at one end of the gate lines212and a data pad is formed at one end of the data lines224.

The common lines216are formed in a horizontal direction substantially parallel with the gate lines212. The common lines216are integrally formed with a common-voltage supply line259provided at an outer block of a panel.

The common electrode217includes: a plurality of vertical parts217bvertically extended from the common lines216and formed substantially parallel and in an alternating pattern with vertical parts230bof the pixel electrode230; and a horizontal part217afor incorporating the vertical parts217binto one part.

The common-voltage supply line259is formed in a direction substantially perpendicular to the common lines216to connect the common lines216of the respective pixel regions.

In the meantime, since the common-voltage supply line259and the gate lines212are formed in a crossing direction, the gate lines212are spaced a predetermined interval from the common-voltage supply line259for prevention of connection.

That is, the common-voltage supply line259is extended from the common lines216and formed in a direction substantially perpendicular to the common lines216. The gate lines212are cut at a portion crossing with the common-voltage supply line259and connected with the gate pad252through a jumping electrode265.

A thin film transistor (TFT) T that includes a gate electrode214, semiconductor layers227aand227b, a source electrode226, and a drain electrode228is formed at a crossing between the gate lines212and the data lines224.

A gate insulation layer218is formed on the gate electrode214protruded from the gate lines212and semiconductor layers227form an active layer227aand an ohmic contact layer227bon the gate insulation layer218.

Data lines224are formed on the gate insulation layer218so as to form a matrix structure together with the gate lines212.

Further, a source electrode226extended from the data lines224and a drain electrode228spaced a predetermined interval from the source electrode226are formed on the gate insulation layer218.

A passivation layer234is formed on the source and the drain electrodes226and228. A pixel electrode230connected through the drain electrode228and a pixel contact hole229is formed on the pixel region P with the passivation layer234interposed.

The pixel electrode230includes: a plurality of vertical parts230bextended from the drain electrode228, formed substantially parallel with the data lines224, and spaced a predetermined interval each other; and a horizontal part230aformed on an upper portion of the common lines216, for incorporating the vertical parts230binto one part.

The horizontal part230aof the pixel electrode230and the common lines216form a storage capacitor C.

The data lines224, the pixel electrode230, and the common electrode217can be of a zigzag type having more than at least one bent portion.

The common lines216and the common electrode217are made of the same material and formed on the same layer as the gate lines212. The material may include pure aluminum, pure copper, an aluminum alloy or a copper alloy.

Therefore, since the common-voltage supply line259and the common lines216are made of the same material as the gate lines212, common signals of the common-voltage supply line259are not hindered by any resistance and a signal delay is not generated. Accordingly, the common signals are supplied to the panel at a desired point of time and image quality of the panel can be improved.

The gate pad252contacts a gate pad upper electrode253made of a transparent conductive electrode through a gate pad contact hole255that passes through the gate insulation layer218and the passivation layer234. The gate pad252is connected with the gate lines212through the jumping electrode265made of a transparent conductive electrode and the gate line contact holes256aand256b.

The jumping electrode265crosses the common-voltage supply line259, and connects the gate line212and the gate pad252.

A manufacturing process of the IPS mode LCDs having the above-described structure will be described in more detail with reference toFIGS. 5 to 7.

FIGS. 5A and 5Bare a plan view and a cross-sectional view, respectively, illustrating a manufacturing process of IPS mode LCDs according to the present invention.

InFIGS. 5A and 5B, after metal is deposited on the substrate210, patterning is performed so that a plurality of gate lines212, a gate electrode214extending from the gate lines212, and a plurality of common lines216arranged in the same direction as the gate lines212close to the gate lines212are formed.

The gate lines212have a gate pad252located at one end.

The common lines216are formed in a first direction substantially parallel to the gate lines212, and one end of the common lines216is integrally formed with the common-voltage supply line259.

The common electrode217extends from the common lines216. The common electrode217includes: a plurality of vertical parts217bvertically extended from the common lines216; and a horizontal part217aincorporating the vertical parts217binto one part.

The common-voltage supply line259is integrally formed in a direction substantially perpendicular to the common lines216.

Since the common-voltage supply line259and the gate lines212are formed in a crossing direction, the gate lines212are spaced a predetermined interval from the common-voltage supply line259so that there is no connection between the gate lines and common-voltage supply line.

That is, the common-voltage supply line259is extended from the common lines216and formed in a direction substantially perpendicular to the common lines216. The gate lines212are cut at a portion intersecting with the common-voltage supply line259and connected with the gate pad252using a jumping electrode265.

Next, a gate insulation layer218is formed on a front surface that includes the gate electrode214.

FIGS. 6A to 6Bare a plan view and a cross-sectional view, respectively, illustrating a manufacturing process of IPS mode LCDs according to the present invention, subsequent toFIGS. 5A and 5B.

InFIGS. 6A and 6B, a semiconductor layer227including an active layer227aand an ohmic contact layer227bis formed at a position of the gate electrode214on the gate insulation layer218.

Data lines224are formed on the gate insulation layer218so as to form a matrix structure along with the gate lines212. The data lines224are formed substantially perpendicular to the gate lines212. Accordingly, the pixel region P is formed by the gate lines212and the data lines224.

When the data lines224are formed, source and drain electrodes226and228are simultaneously formed. The source electrode226is connected to the data lines224and the drain electrode228is spaced a predetermined interval from the source electrode226. Accordingly, a TFT T including the gate electrode214, the semiconductor layers227, the source and the drain electrodes226and228are formed.

FIGS. 7A and 7Bare a plan view and a cross-sectional view, respectively, illustrating a manufacturing process of IPS mode LCDs according to the present invention, subsequent toFIGS. 6A and 6B.

InFIGS. 7A and 7B, a passivation layer234is formed on a front surface of the TFT T.

After that, a pixel electrode230is formed so that it may be electrically connected with the drain electrode and substantially parallel to the data lines224.

A pixel contact hole229that passes through the passivation layer234on the drain electrode228is formed so that a predetermined region of the drain electrode228may be exposed. The drain electrode228is electrically connected with the pixel electrode230through the pixel contact hole229.

Further, the gate pad's contact hole255that passes through the gate insulation layer218and the passivation layer234on the gate pad252is formed so that a predetermined region of the gate pad252may be exposed. The gate line contact holes256aand256bthat pass through the gate insulation layer218and the passivation layer234on the gate pad252and the gate lines212are formed so that predetermined regions of the gate pad252in the vicinity of the common-voltage supply line259and the gate lines212may be exposed, respectively.

The pixel electrode230includes: a plurality of vertical parts230bthat extend from the drain electrode228, formed substantially parallel to the data lines224, and spaced a predetermined interval from each other; and a horizontal part230aformed on an upper portion of the common lines216to incorporate the vertical parts230binto one part.

The horizontal part230aof the pixel electrode230forms a storage capacitor C along with the common lines216.

The gate pad's upper electrode253connected with the gate pad252through the gate pad's contact hole255is formed on the gate pad252. Further, a jumping electrode265for connecting the gate pad252with the gate lines212is formed over the common-voltage supply line259. Therefore, the jumping electrode265connects the gate pad252with the gate lines212through the gate line contact holes256aand256b.

An alignment film (not shown) is formed on a front surface of the substrate210formed as described above.

As described above, according to the present invention, the common-voltage supply line259and the common lines216are made of the same material so that a delay of the common signals can be prevented, and thus the image quality can be improved.

FIG. 8is a plan view of an IPS mode LCD according to another embodiment of the present invention in which common electrodes are arranged in a direction parallel to the common lines. InFIG. 8, the IPS mode LCD includes: a plurality of gate lines812horizontally arranged substantially parallel with each other and spaced a predetermined interval on a substrate; a plurality of common lines816horizontally arranged substantially parallel with each other, and closely to the gate lines812; and a plurality of data lines824crossing with the gate line812and common lines816. vertically arranged substantially parallel with each other and spaced a predetermined interval, to define a pixel region P together with the gate lines812.

A plurality of common electrodes817extend to the pixel region P and are connected with the common lines816. The plurality of common electrodes may extend in a direction substantially parallel to a direction of the common lines816.

A gate pad852is formed at one end of the gate lines812and a data pad is formed at one end of the data lines824.

The common lines816are formed in a horizontal direction substantially parallel with the gate lines812. The common lines816are integrally formed with a common-voltage supply line859provided at an outer block of a panel.

The common-voltage supply line859is formed in a direction substantially perpendicular to the common lines816to connect the common lines816of the respective pixel regions.

Because the common-voltage supply line859and the gate lines812are formed in a crossing direction, the gate lines812are spaced a predetermined interval from the common-voltage supply line859to prevent contact between the two. Specifically, the common-voltage supply line859is extended from the common lines816and formed in a direction substantially perpendicular to the common lines816. The gate lines812are cut at portion crossing with the common-voltage supply line859and connected with the gate pad852through a jumping electrode865.

A thin film transistor (TFT) T that includes a gate electrode, semiconductor layers, a source electrode and a drain electrode is formed at a crossing between the gate lines812and the data lines824. A gate insulation layer is formed on the gate electrode which protrudes from the gate lines812and semiconductor layers including an active layer and ohmic contact layer are formed on the gate insulating layer.

The data lines824are formed on the gate insulation layer so as to form a matrix structure with the gate lines812. Further, the source electrode extends from the data lines824and a drain electrode, spaced a predetermined interval from the source electrode, is formed on the gate insulation layer.

A passivation layer is formed on the source and drain electrodes. A pixel electrode830connected through the drain electrode and a drain contact hole is formed on the pixel region P with the passivation layer interposed therebetween.

The common lines816and the common electrode817are made of the same material and formed on the same layer as the gate lines812. The material may include pure aluminum, pure copper, an aluminum alloy or a copper alloy. Therefore, since the common-voltage supply line859and the common lines816are made of the same material as the gate lines812, common signals of the common-voltage supply line859are not hindered by any resistance and a signal delay does not occur. Accordingly, the common signals are supplied to the panel at a desired time and image quality of the panel is improved.

The gate pad852contacts a gate pad upper electrode853made of a transparent conductive electrode through a gate pad contact hole855that passes through the gate insulation layer and the passivation layer. The gate pad is connected with the gate lines812through the jumping electrode865made of a transparent conductive electrode and the gate line contact holes856aand856b. The jumping electrode865crosses the common-voltage supply line859and connects the gate line812and the gate pad852.

FIG. 9is a plan view of an IPS mode LCD according to another embodiment of the present invention in which common electrodes are arranged in a zigzag pattern. InFIG. 9, the IPS mode LCD includes: a plurality of gate lines912horizontally arranged substantially parallel with each other and spaced a predetermined interval on a substrate; a plurality of common lines916horizontally arranged substantially parallel with each other, and close to the gate lines912; and a plurality of data lines924crossing with the gate line912and common lines916vertically arranged substantially parallel with each other and spaced a predetermined interval to define a pixel region P together with the gate lines912.

A plurality of common electrodes917extend to the pixel region P and are connected with the common lines916. The plurality of common electrodes may extend from the common lines916in a substantially zigzag pattern.

A gate pad952is formed at one end of the gate lines912and a data pad may be formed at one end of the data lines924.

The common lines916are formed in a horizontal direction substantially parallel with the gate lines912. The common lines916are integrally formed with a common-voltage supply line959provided at an outer block of a panel.

The common-voltage supply line959is formed in a direction substantially perpendicular to the common lines916to connect the common lines916of the respective pixel regions.

Because the common-voltage supply line959and the gate lines912are formed in a crossing direction, the gate lines912are spaced a predetermined interval from the common-voltage supply line959to prevent contact between the two. Specifically, the common-voltage supply line959is extended from the common lines916and formed in a direction substantially perpendicular to the common lines916. The gate lines912are cut at portion crossing with the common-voltage supply line959and connected with the gate pad952through a jumping electrode965.

A thin film transistor (TFT) T that includes a gate electrode, semiconductor layers, a source electrode and a drain electrode is formed at a crossing between the gate lines912and the data lines924. A gate insulation layer is formed on the gate electrode which protrudes from the gate lines912and semiconductor layers including an active layer and ohmic contact layer are formed on the gate insulating layer.

The data lines924are formed on the gate insulation layer so as to form a matrix structure with the gate lines912. Further, the source electrode extends from the data lines924and a drain electrode, spaced a predetermined interval from the source electrode, is formed on the gate insulation layer.

A passivation layer is formed on the source and drain electrodes. A pixel electrode930connected through the drain electrode and a drain contact hole is formed on the pixel region P with the passivation layer interposed therebetween.

The common lines916and the common electrode917are made of the same material and formed on the same layer as the gate lines912. The material may include pure aluminum, pure copper, an aluminum alloy or a copper alloy. Therefore, since the common-voltage supply line959and the common lines916are made of the same material as the gate lines912, common signals of the common-voltage supply line959are not hindered by any resistance and a signal delay does not occur. Accordingly, the common signals are supplied to the panel at a desired time and image quality of the panel is improved.

The gate pad952contacts a gate pad upper electrode953made of a transparent conductive electrode through a gate pad contact hole955that passes through the gate insulation layer and the passivation layer. The gate pad is connected with the gate lines912through the jumping electrode965made of a transparent conductive electrode and the gate line contact holes956aand956b. The jumping electrode965crosses the common-voltage supply line959and connects the gate line912and the gate pad952.

The manufacturing process of the IPS mode LCDs ofFIGS. 8 and 9are similar to those described inFIGS. 5 to 7.