Methods of forming semiconductor devices including low-k dielectric layer

Methods of forming a dielectric layer are provided. The methods may include introducing oxygen radicals and organic silicon precursors into a chamber to form a preliminary dielectric layer on a substrate. Each of the organic silicon precursors may include a carbon bridge and a porogen such that the preliminary dielectric layer may include carbon bridges and porogens. The methods may also include removing at least some of the porogens from the preliminary dielectric layer to form a porous dielectric layer including the carbon bridges.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. non-provisional application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2013-0067948, filed on Jun. 13, 2013, in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety.

FIELD

The present disclosure generally relates to the field of electronics, and more particularly, to semiconductor devices.

BACKGROUND

Porous low-k dielectric layers have been developed in response to a growing need for lower dielectric constant layers. However, the porous low-k dielectric layers do not have enough mechanical strength against stress applied during semiconductor device manufacturing processes, and thus, it is difficult to use the porous low-k dielectric layers in semiconductor devices.

SUMMARY

A method of forming a semiconductor device may include introducing a plasma and organic silicon precursors into a chamber to form a preliminary dielectric layer on a wafer. The plasma may include oxygen radicals generated from an external plasma generator that is outside the chamber, the organic silicon precursors may include carbon bridges and porogens, and the preliminary dielectric layer may include the porogens. The method may also include forming a porous dielectric layer by removing at least some of the porogens from the preliminary dielectric layer.

According to various embodiments, the external plasma generator may include a microwave generator configured to generate microwaves and a gas supply configured to supply a gas including oxygen, and the plasma may be generated by passing the gas including oxygen through the microwaves generated from the microwave generator. The gas including oxygen may be O2, N2O, H2O or combinations thereof.

According to various embodiments, the organic silicon precursors may include a compound represented by the following chemical formula:

Each of R1, R2, R3, R4, R5and R6may be one of hydrogen, alkyl, and alkoxy, n may be an integer of 1 to 5, and at least one of R1, R2, R3, R4, R5and R6may include one of the porogens.

According to various embodiments, the organic silicon precursors may include a compound represented by the following chemical formula:

Each of Ra, Rb, Rc, and Rd may be one of hydrogen, alkyl, and alkoxy, and at least one of Ra, Rb, Rc, and Rd may include one of the porogens.

In various embodiments, the porogens may include a —CHx-CHy- bonding structure.

In various embodiments, the organic silicon precursors may be combined with a carrier gas to be introduced into the chamber. The organic silicon precursors may be supplied at a flow rate of about 50 milligrams per minute (mg/min) to about 500 mg/min. The carrier gas may include an inert gas and may be supplied at a flow rate of about 500 standard-cubic-centimeters per minute (sccm) to about 3,000 sccm.

According to various embodiments, the method may further include loading the wafer onto a mounter in the chamber and controlling a temperature of the mounter at a range of about −25° C. to about 100° C.

According to various embodiments, the method may further include maintaining an internal pressure of the chamber at a range of about 0.9 Torr to about 5 Torr.

In various embodiments, removing the porogens may include irradiating UV light.

In various embodiments, the oxygen radicals may be introduced from an upper portion of the chamber, and the organic silicon precursors may be introduced through a tubular nozzle protruding from a side of the chamber.

A method of forming a semiconductor device may include forming a via hole in a lower layer formed on a substrate, forming a preliminary via dielectric layer including porogens on an upper surface of the lower layer and an inner wall of the via hole, converting the preliminary via dielectric layer into a porous via dielectric layer by performing a curing process to remove the porogens, and forming a via plug filling the via hole on the porous via dielectric layer. Forming the preliminary via dielectric layer may include introducing oxygen plasma generated outside a chamber and organic silicon precursors including carbon bridges and the porogens into the chamber.

According to various embodiments, the method may also include forming a transistor on the substrate and forming a lower interlayer dielectric layer covering the transistor on the substrate. The lower layer may include the lower interlayer dielectric layer and the via hole may vertically pass through the lower interlayer dielectric layer and the substrate.

A method of forming a dielectric layer may include introducing oxygen radicals and organic silicon precursors into a chamber to form a preliminary dielectric layer on a substrate. Each of the organic silicon precursors may include a carbon bridge and a porogen such that the preliminary dielectric layer includes carbon bridges and porogens. The method may also include removing at least some of the porogens from the preliminary dielectric layer to form a porous dielectric layer including the carbon bridges.

According to various embodiments, the oxygen radicals may be generated outside the chamber.

In various embodiments, the organic silicon precursors may include a compound having the following structure:

Each of R1, R2, R3, R4, R5and R6may be one of hydrogen, alkyl, and alkoxy, n may be an integer of 1 to 5, and at least one of R1, R2, R3, R4, R5and R6may include one of the porogens.

In various embodiments, the organic silicon precursors may include a compound having the following structure:

Each of Ra, Rb, Rc, and Rd may be one of hydrogen, alkyl, and alkoxy, and at least one of Ra, Rb, Rc, and Rd may include one of the porogens.

According to various embodiments, removing at least some of the porogens may include irradiating UV light.

DETAILED DESCRIPTION

Various embodiments are described below with reference to the accompanying drawings. These inventive concepts may, however, be embodied in different forms without deviating from the spirit and teachings of this disclosure and so the disclosure should not be construed as limited to example embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the disclosure to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. Like reference numbers refer to like elements throughout.

It will be understood that, although the terms first, second, A, B, etc. may be used herein to describe elements of the invention, such elements should not be construed as limited by these terms. For example, a first element could be termed a second element, and a second element could be termed a first element, without departing from the teachings of the present embodiments. Herein, the term “and/or” includes any and all combinations of one or more referents.

FIGS. 1A and 1Bare cross-sectional views illustrating semiconductor devices according to some embodiments of the present inventive concept. Referring toFIG. 1A, a semiconductor device100in accordance with some embodiments of the present inventive concept may include a substrate110having an upper surface and a lower surface, a transistor120, interlayer dielectric layers131,133, and134, metal layers150,160, and170disposed on the upper surface of the substrate110, and a via plug structure140formed in the substrate110. The semiconductor device100may further include an upper chip pad180disposed above the upper surface of the substrate110, and a lower surface redistribution layer190formed on the lower surface of the substrate110.

The substrate110may include a semiconductor wafer having a single crystalline silicon bulk wafer or an epitaxially grown layer. The transistor120may include a gate dielectric layer121, a gate electrode122, a gate capping layer123, and a gate spacer124. The gate dielectric layer121directly formed on the substrate110may include silicon oxide or a metal oxide. The gate electrode122disposed on the gate dielectric layer121may include polysilicon, a metal silicide, a metal, a metal alloy, a metal compound, or a combination thereof. The gate capping layer123may be formed on the gate electrode122. The gate spacer124may be formed on sidewalls of the gate dielectric layer121, the gate electrode122, and the gate capping layer123. The gate capping layer123and the gate spacer124may include a dielectric material, such as silicon nitride and silicon oxynitride, that is harder than silicon oxide.

A lower interlayer dielectric layer131covering the upper surface of the substrate110and the transistors120may be formed. The lower interlayer dielectric layer131may include silicon oxide. The lower interlayer dielectric layer131may include a porous low-k dielectric. A lower stopper layer132may be formed on the lower interlayer dielectric layer131. The lower stopper layer132may include silicon nitride.

The via plug structure140may vertically penetrate or pass through the lower stopper layer132, the lower interlayer dielectric layer131, and the substrate110. The via plug structure140may include a via hole141, a via dielectric layer142conformally formed on an inner wall of the via hole141, a via barrier layer143conformally formed on the via dielectric layer142, a via seed layer144conformally formed on the via barrier layer143, and a via plug145formed on the via seed layer144to fill the via hole141. The via dielectric layer142may include silicon oxide. In some embodiments, the via dielectric layer142may include a porous low-k dielectric. The via barrier layer143may include a barrier metal, such as Ti, TiN, Ta, TaN, TiW, and WN. The via seed layer144may include a single metal or alloy including Cu, W, TiW, Ni, etc. The via plug145may include a metal such as Cu. When the via seed layer144and the via plug145include the same metal, a boundary therebetween may be less visible.

The lower metal layer150may be formed on the via plug structure140and/or the lower stopper layer132. The lower metal layer150may include a lower metal interconnection151and a via plug pad152. The via plug pad152may be electrically connected to and in direct contact with the via plug structure140.

An intermediate interlayer dielectric layer133covering the lower metal layer150may be formed on lower stopper layer132. The intermediate interlayer dielectric layer133may include silicon oxide. In some embodiments, the intermediate interlayer dielectric layer133may include a porous low-k dielectric.

An intermediate metal layer160may be formed on the intermediate interlayer dielectric layer133. A lower inner via plug155vertically passing through the intermediate interlayer dielectric layer133and electrically connecting the via plug pad152to the intermediate metal layer160may be formed.

An upper interlayer dielectric layer134covering the intermediate metal layer160may be formed on the intermediate interlayer dielectric layer133. The upper interlayer dielectric layer134may include silicon oxide. In some embodiments, the upper interlayer dielectric layer134may include a porous low-k dielectric.

An upper metal layer170may be formed on the upper interlayer dielectric layer134. An upper inner via plug165vertically passing through the upper interlayer dielectric layer134and electrically connecting the intermediate metal layer160to the upper metal layer170may be formed.

A passivation layer135covering the upper metal layer170may be formed on the upper interlayer dielectric layer134. The passivation layer135may include silicon nitride, silicon oxide, or a polyimide.

The upper chip pad180may be formed on the passivation layer135. The upper chip pad180may include a plug part181passing through the passivation layer135to be connected to the upper metal layer170, and a pad part185disposed on the passivation layer135. The upper chip pad180may include a metal.

A lower surface dielectric layer136may be formed on the lower surface of the substrate110. The lower surface dielectric layer136may include silicon nitride, silicon oxide, or a polyimide. The via plug structure140may be exposed on the lower surface of the substrate110.

The lower surface redistribution layer190may be formed on the exposed via plug structure140. The lower surface redistribution layer190may include a plug part191passing through the lower surface dielectric layer136to be electrically connected to the via plug structure140, and a pad part195disposed on the lower surface dielectric layer136.

The semiconductor device100according to some embodiments of the present inventive concept may include at least one porous low-k dielectric. Accordingly, the capacitance between conductive materials and RC delay may be decreased and thus electrical signals may be more stably transferred at very high speed.

Referring toFIG. 1B, a semiconductor device200according to some embodiments of the present inventive concept may include a substrate210, a transistor220disposed on the substrate210, a lower interlayer dielectric layer231covering the transistor220, a first interconnection structure240disposed on the lower interlayer dielectric layer231, a second interconnection structure250disposed on the first interconnection structure240, a third interconnection structure260disposed on the second interconnection structure250, and a redistribution layer structure270disposed on the third interconnection structure260.

The substrate210may include a semiconductor wafer having a single crystalline silicon bulk or epitaxially grown layer. The transistor220may include a gate dielectric layer221, a gate electrode222, a gate capping layer223, and a gate spacer224. The gate dielectric layer221directly formed on the substrate210may include silicon oxide or a metal oxide. The gate electrode222disposed on the gate dielectric layer221may include polysilicon, a metal silicide, a metal, an alloy, a metal compound, or a combination thereof. The gate capping layer223may be formed on the gate electrode222. The gate spacer224may be formed on sidewalls of the gate dielectric layer221, the gate electrode222, and the gate capping layer223. The gate capping layer223and the gate spacer224may include a dielectric material, such as silicon nitride and silicon oxynitride, that is harder than silicon oxide.

The lower interlayer dielectric layer231may include silicon oxide. In some embodiments, the lower interlayer dielectric layer231may include a porous low-k dielectric. The semiconductor device200may further include a lower stopper layer232covering the lower interlayer dielectric layer231. The lower stopper layer232may include silicon nitride. A lower metal layer235may be formed on the lower stopper layer232.

The first interconnection structure240may include a first intermediate interlayer dielectric layer241covering the lower metal layer235, a first via plug243pand first interconnection plug245ppassing through the first intermediate interlayer dielectric layer241to be connected to the lower metal layer235, and a first intermediate stopper layer247covering the first intermediate interlayer dielectric layer241and the first interconnection plug245p.

The first intermediate interlayer dielectric layer241may include silicon oxide. In some embodiments, the first intermediate interlayer dielectric layer241may include a porous low-k dielectric. The first intermediate stopper layer247may include silicon nitride.

The second interconnection structure250may include a second intermediate interlayer dielectric layer251covering the first interconnection plug245p, a second via plug253pand second interconnection plug255ppassing through the second intermediate interlayer dielectric layer251to be connected to the first interconnection plug245p, and a second intermediate stopper layer257covering the second intermediate interlayer dielectric layer251and the second interconnection plug255p.

The second intermediate interlayer dielectric layer251may include silicon oxide. In some embodiments, the second intermediate interlayer dielectric layer251may include a porous low-k dielectric. The second intermediate stopper layer257may include silicon nitride.

The third interconnection structure260may include a third intermediate interlayer dielectric layer261covering the second interconnection plug255p, a third via plug263pand third interconnection plug265ppassing through the third intermediate interlayer dielectric layer261to be connected to the second interconnection plug255p, and a passivation layer267covering the third intermediate interlayer dielectric layer261and the third interconnection plug265p.

The third intermediate interlayer dielectric layer261may include silicon oxide. In some embodiment, the third intermediate interlayer dielectric layer261may include a porous low-k dielectric. The passivation layer267may include silicon nitride, silicon oxide, or a polyimide.

The redistribution layer structure270may include a plug part271vertically passing through the passivation layer267to be electrically connected to the third interconnection plug265p, and a pad part275disposed on the passivation layer267. The redistribution layer structure270may include a metal.

The semiconductor device200according to some embodiments of the present inventive concept may include at least one porous low-k dielectric. Accordingly, the capacitance between the conductive materials and RC delay may decrease and thus electrical signals may be stably transferred at high speed.

FIGS. 2A to 2Kare cross-sectional views illustrating a method of forming a semiconductor device according to some embodiments of the present inventive concept. Referring toFIG. 2A, a method of forming a semiconductor device according to some embodiments of the present inventive concept may include forming transistors120on a substrate110, and forming a lower interlayer dielectric layer131covering the substrate110and the transistors120. The substrate110may include a semiconductor wafer having a single crystalline silicon bulk or epitaxially grown layer. Each of the transistors120may include a gate dielectric layer121, a gate electrode122, a gate capping layer123, and a gate spacer124. The gate dielectric layer121may include silicon oxide or a metal oxide. The gate electrode122may include polysilicon, a metal silicide, a metal, an alloy, a metal compound, or a combination thereof. The gate capping layer123and the gate spacer124may include a dielectric material, such as silicon nitride or silicon oxynitride, that is harder than silicon oxide. The formation of the lower interlayer dielectric layer131may include depositing silicon oxide using, for example, a chemical vapor deposition (CVD) process. The method of forming the lower interlayer dielectric layer131will be described herein in detail.

Referring toFIG. 2B, the method may include forming a via hole141, and forming a via dielectric layer142on an inner wall of the via hole141. For example, the method may include forming an etch mask and/or, a lower stopper layer132on the lower interlayer dielectric layer131, forming the via hole141vertically passing through the lower interlayer dielectric layer131in the substrate110using an etch process, and conformally forming the via dielectric layer142on the inner wall of the via hole141. The method of forming the via dielectric layer142will be described herein in detail.

Referring toFIG. 2C, the method may include forming a via barrier layer143and a via seed layer144on the via dielectric layer142disposed on the inner wall of the via hole141, and forming a via plug145filling the via hole141on the via seed layer144. The via barrier layer143may be formed using a CVD process. The via barrier layer143may include a barrier metal, such as Ti, TiN, Ta, TaN, TiW, and WN. The via seed layer144may be formed using a physical vapor deposition (PVD) process such as sputtering, or a CVD process. The via seed layer144may include a single metal or alloy including Cu, W, TiW, Ni, etc. The via plug145may be formed using an electroplating process. The via plug145may include a metal such as Cu. When the via seed layer144and the via plug145include the same metal, a boundary therebetween may be less visible.

Referring toFIG. 2D, the method may include forming a via plug structure140by planarizing the via plug145, the via seed layer144, the via barrier layer143, and the via dielectric layer142. The planarization process may include a chemical mechanical polishing (CMP) process.

Referring toFIG. 2E, the method may include forming a lower metal layer150and an intermediate interlayer dielectric layer133covering the lower metal layer150on the lower interlayer dielectric layer131or the lower stopper layer132. The lower metal layer150may include a lower metal interconnection151and a via plug pad152connected to the via plug structure140.

Referring toFIG. 2F, the method may include forming lower inner via plugs155passing through the intermediate interlayer dielectric layer133, an intermediate metal layer160, and an upper interlayer dielectric layer134covering the intermediate metal layer160. At least one of the lower inner via plugs155may be electrically connected to the via plug pad152. The intermediate metal layer160may include a metal interconnection.

Referring toFIG. 2G, the method may include forming an upper inner via plugs165passing through the upper interlayer dielectric layer134, an upper metal layer170, and a passivation layer135covering the upper metal layer170. At least one of the upper inner via plugs165may be electrically connected to the via plug pad152. The upper metal layer170may include a metal interconnection. The passivation layer135may include silicon nitride and/or silicon oxide.

Referring toFIG. 2H, the method may include forming an upper chip pads180passing through the passivation layer135to be connected to the upper metal layer170. Each of the upper chip pads180may include a plug part181passing through the passivation layer135, and a pad part185disposed on the passivation layer135. The upper chip pads180may be formed using a process of forming a redistribution layer.

Referring toFIG. 2I, the method may include attaching a wafer support carrier (WSC) to the upper chip pads180, and turning over the substrate110.

Referring toFIG. 2J, the method may include etching a lower surface of the substrate110to expose an ending part of the via plug structure140. The exposed ending part of the via plug structure140may include the via barrier layer143covering the via plug145.

Referring toFIG. 2K, the method may include forming a lower surface dielectric layer136and a lower surface redistribution layer190on the lower surface of the substrate110. The lower surface dielectric layer136may include silicon oxide and/or silicon nitride. The lower surface redistribution layer190may be formed using a redistribution layer formation process. The lower surface redistribution layer190may include a metal. The lower surface redistribution layer190may include a plug part191passing through the lower surface dielectric layer136and a pad part195disposed on the lower surface dielectric layer136.

Referring toFIG. 1Aagain, the WSC may be removed and the semiconductor device100according to some embodiments of the present inventive concept may be manufactured.

FIGS. 3A to 3Gare cross-sectional views illustrating a method of forming a semiconductor device according to some embodiments of the present inventive concept. Referring toFIG. 3A, a method of forming a semiconductor device according to some embodiments of the present inventive concept may include forming a transistor220, a lower interlayer dielectric layer231, a lower stopper layer232, a lower metal layer235, and a first intermediate interlayer dielectric layer241on a substrate210. The substrate210may include a semiconductor wafer having a single crystalline silicon bulk or epitaxially grown layer. The transistor220may include a gate dielectric layer221, a gate electrode222, a gate capping layer223, and a gate spacer224. The gate dielectric layer221may include silicon oxide or a metal oxide. The gate electrode222may include polysilicon, a metal silicide, a metal, an alloy, a metal compound, or a combination thereof. The gate capping layer223and the gate spacer224may include a dielectric material, such as silicon nitride and silicon oxynitride, that is harder than silicon oxide. The formation of the lower interlayer dielectric layer231and the first intermediate interlayer dielectric layer241may include depositing silicon oxide using, for example, a CVD process. The method of forming the lower interlayer dielectric layer231and the first intermediate interlayer dielectric layer241will be described herein in detail. The lower metal layer235may include a metal interconnection.

Referring toFIG. 3B, the method may include forming first via holes243hand first interconnection trenches245tin the first intermediate interlayer dielectric layer241. The first via holes243hmay expose at least a portion of a surface of the lower metal layer235. The first interconnection trenches245tmay overlap at least one of the first via holes243h.

Referring toFIG. 3C, the method may include forming first via plugs243p, first interconnection plugs245p, and a first intermediate stopper layer247. The first via plugs243pmay fill the first via holes243h, and the first interconnection plugs245pmay fill the first interconnection trenches245t. The first via plugs243pand the first interconnection plugs245pmay be formed using a dual damascene process. Each of the first via plugs243pand the first interconnection plugs245pmay include a barrier metal or a core metal. The barrier metal may include a metal for barrier, such as Ti, TiN, Ta, TaN, TiW, and WN. The core metal may include a metal such as Cu and W. The first intermediate stopper layer247may include silicon nitride.

Referring toFIG. 3D, the method may include forming a second intermediate interlayer dielectric layer251on the first intermediate stopper layer247, and forming second via holes253hand second interconnection trenches255tin the second intermediate interlayer dielectric layer251. The second via holes253hmay expose parts of surfaces of the first interconnection plugs245p. The second interconnection trenches255tmay overlap at least one of the second via holes253h.

Referring toFIG. 3E, the method may include forming second via plugs253p, second interconnection plugs255p, and a second intermediate stopper layer257. The second via plugs253pmay fill the second via holes253h, and the second interconnection plugs255pmay fill the second interconnection trenches255t. The second via plugs253pand the second interconnection plugs255pmay be formed using a dual damascene process. Each of the second via plugs253pand the second interconnection plugs255pmay include a barrier metal and a core metal. The second intermediate stopper layer257may include silicon nitride.

Referring toFIG. 3F, the method may include forming a third intermediate interlayer dielectric layer261on the second intermediate stopper layer257, and forming third via holes263hand third interconnection trenches265tin the third intermediate interlayer dielectric layer261. The third via holes263hmay expose parts of surfaces of the second interconnection plugs255p. The third interconnection trenches265tmay overlap at least one of the third via holes263h.

Referring toFIG. 3G, the method may include forming third via plugs263p, third interconnection plugs265p, and a passivation layer267. The third via plugs263pmay fill the third via holes263h, and the third interconnection plugs265pmay fill the third interconnection trenches265t. The third via plugs263pand the third interconnection plugs265pmay be formed using a dual damascene process. Each of the third via plugs263pand the third interconnection plugs265pmay include a barrier metal and a core metal. The passivation layer267may include silicon nitride, silicon oxide, or a polyimide.

Referring toFIG. 1Bagain, the method may include forming a redistribution layer structure270on the passivation layer267. The redistribution layer structure270may include a plug part271passing through the passivation layer267to be connected to the third interconnection plugs265p, and a pad part275disposed on the passivation layer267.

FIG. 4Ais a diagram illustrating a deposition apparatus according to some embodiments of the present inventive concept. Referring toFIG. 4A, a deposition apparatus10may include a chamber20, a radical supply30, and a precursor supply40.

The chamber20may include a mounter25configured to support a wafer W at a lower part therein. That is, the wafer W may be mounted on the mounter25. The mounter25may include an electro-static chuck. The mounter25may include a temperature controller26therein. The temperature controller26may include a coil-type heater27for heating, and/or an air path28for cooling. An inert gas, such as helium, may cool down the mounter25through the air path28. A top source RF electrode RFt may be disposed at an upper part of the chamber20, a side RF electrode RFs may be disposed at an upper side part of the chamber20, and a bias RF electrode RFb may be disposed at the mounter25.

Oxygen radicals O* supplied from the radical supply30may be supplied to the inside of the chamber20through a radical supply pipe35. A radical supply nozzle36configured to spray or atomize the oxygen radicals O* in the chamber20may be formed at an ending portion of the radical supply pipe35. The radical supply nozzle36may be arranged at an upper center portion of the chamber20.

Precursors supplied from the precursor supply40may be uniformly supplied to the inside of the chamber20through a precursor supply pipe45and a precursor supply nozzle46. A plurality of the precursor supply nozzles46may be arranged in the chamber20. The precursor supply nozzle46may have a shape of a horizontal rod protruding from a side of the chamber20toward the center of chamber20. The precursor supply40may supply a carrier gas such as helium (He) and/or argon (Ar) together with organic silicon precursors. The carrier gas may transport the organic silicon precursors to the inside of the chamber20.

The outlet50may discharge reaction gases from the inside of the chamber20to the outside of the chamber20. The outlet50may include a vacuum pump such as a turbo pump.

FIG. 4Bis a diagram illustrating a radical supply of a deposition apparatus according to some embodiments of the present inventive concept. Referring toFIG. 4B, a radical supply30of the deposition apparatus10according to some embodiments of the present inventive concept may include a microwave generator31, a gas supply32, and a plasma generator33. For example, the microwave generator31may generate microwaves (MW) having a frequency of about 2.45 GHz, and power of about 1.5 to about 3.8 Kw. The gas supply32may supply O2, N2O, H2O, combinations thereof or other gas including oxygen to the plasma generator33. The gas may be plasmarized to include oxygen radicals O* while passing through the plasma generator33, and may be supplied to the inside of the chamber20through the radical supply pipe35. The microwaves passing through the plasma generator33may be discharged through an exhaust waveguide34.

In the deposition apparatus10according to some embodiments of the present inventive concept, a deposition process may be performed by preparing gas plasma, which is plasmarized to include the oxygen radicals O* outside the chamber20, and precursors separately and supplying the gas plasma and the precursors into the chamber20. Accordingly, the precursors may not be directly exposed to the plasma or the microwaves.

FIGS. 5A to 5Care diagrams illustrating a method of forming a dielectric layer according to some embodiments of the present inventive concept. The dielectric layer320may correspond to one of the lower interlayer dielectric layer131, the intermediate interlayer dielectric layer133, the upper interlayer dielectric layer134, the lower interlayer dielectric layer231, the first intermediate interlayer dielectric layer241, the second intermediate interlayer dielectric layer251, and the third intermediate interlayer dielectric layer261in theFIGS. 1A to 3G.

Referring toFIG. 5A, the method of forming the dielectric layer320according to some embodiments of the present inventive concept may include forming a preliminary dielectric layer320pincluding porogens325on a lower layer305. The lower layer305may include a silicon wafer, silicon nitride, silicon oxide, polysilicon, a metal, or a combination thereof.

Referring toFIGS. 4A and 4Bagain, the method may include introducing a wafer W into the chamber20, vacuumizing the inside of the chamber20, controlling and/or maintaining a temperature of the inside of the chamber20and/or the mounter25at an appropriate value, and supplying the oxygen radicals O* and the precursors including the porogens325to the chamber20.

The oxygen radicals O* may be supplied in a plasma state including O2, N2O, H2O, combinations thereof or other oxygen compound, or in a gas state which is not plasmarized. When the oxygen radicals O* are in the plasma state, the plasma may be formed outside the chamber20, for example, formed using a remote plasma process. The plasma-state oxygen radicals O* may be formed and prepared outside the chamber20to be supplied to the inside of the chamber20. Alternatively, the oxygen radicals O* may be excited by thermal energy and supplied without being accompanied by plasma.

The precursors may include organic silicon precursors. The precursors may include silicon atoms having a carbon bridge and the porogens325. For example, the precursors may include a compound represented by Chemical formula 1 below.

R1to R6are one of hydrogen, alkyl, and alkoxy, and n is an integer from 1 to 5. In some embodiments, alkyl is methyl. At least one of R1to R6may include the porogens325. Accordingly, the preliminary dielectric layer320pmay include a carbon bridge having a —(CH2)n- bonding structure in a network structure including a Si—O—Si bond.

In some embodiments, the precursors are the organic silicon precursors having a structure represented by Chemical formula 1.

As appreciated by the present inventors, the carbon bridge —(CH2)n- may have a superior mechanical strength to the Si—O—Si— bond. Accordingly, the preliminary dielectric layer320pmay have relatively higher mechanical strength than a dielectric material having the Si—O—Si bond only. However, as also appreciated by the present inventors, the carbon bridge —(CH2)n- may be vulnerable to a plasma or microwaves. Since the carbon bridge —(CH2)n- of the preliminary dielectric layer320pin the embodiments of the present inventive concept is not directly exposed to the plasma or microwaves, a Si—(CH2)n-Si bonding structure may be maintained without being chemically and/or physically degraded and/or separated. Accordingly, the preliminary dielectric layer320pin the embodiments of the present inventive concept may have sufficiently more Si—(CH2)n-Si bonding structures than that formed using a plasma deposition process.

In some embodiments, the organic silicon precursors may include a silicon bond —Si-Cx-Si— of a separated carbon bridge, and a compound represented by Chemical formula 2 below.

At least one of Ra, Rb, Rc, and Rd may be the porogens325, and the others may be one of hydrogen, alkyl, and alkoxy. In some embodiments, alkyl is methyl.

In some embodiments, the precursors are the organic silicon precursors having a structure represented by Chemical formula 2.

For example, a process of forming the preliminary dielectric layer320pmay include controlling and/or maintaining the temperature of the mounter25at about −25° C. to 100° C., and maintaining the internal pressure of the chamber20at about 0.9 Torr to 5 Torr. In addition, the process may include supplying oxygen gas (O2) including the oxygen radicals O* at about 1,500 to 3,000 standard-cubic-centimeters per minute (sccm) to the inside of the chamber20, and the organic silicon precursors including the porogens325at about 50 to 500 miligrams per minute (mgm) to the inside of the chamber20. Further referring toFIG. 4A, the organic silicon precursors may be mixed with the carrier gas in the precursor supply40and may be supplied together. The carrier gas may include an inert gas such as helium and argon. For example, helium gas may be supplied to the inside of the chamber20at about 1,000 to 3,000 sccm, and argon gas may be supplied to the inside of the chamber20at about 500 to 1,500 sccm. Alternatively, the helium gas and the argon gas may be supplied to the inside of the chamber20at the same time. The carrier gas may carry the organic silicon precursors to the inside of the chamber20. In some embodiments, the process of forming the preliminary dielectric layer320pmay include maintaining the temperature of the mounter25at about 80° C. and the internal pressure of the chamber20at about 1.9 Torr, and supplying the oxygen gas (O2) including the oxygen radicals O* at about 2,000 sccm, the organic silicon precursors including the porogens325at 600 mgm, and the carrier gas at 1,500 sccm, to the inside of the chamber20.

As the temperature of the mounter25rises, the deposition rate of the preliminary dielectric layer320pmay decrease, flowability may be lowered, the carbon bridge may be damaged, and therefore, the amount of the carbon bridges in the preliminary dielectric layer320pmay be reduced. Accordingly, when the temperature of the mounter25rises above 100° C., since the flowability of the preliminary dielectric layer320pis lowered, conformality and planarity of the preliminary dielectric layer320pmay be worse. In addition, since the amount of the carbon bridges in the preliminary dielectric layer320pis reduced, the mechanical strength and/or physical endurance may be degraded. Accordingly, some embodiments may sufficiently provide the mechanical strength and/or physical endurance of the preliminary dielectric layer320pwithout excessively degrading the deposition rate and flowability of the preliminary dielectric layer320p.

As the internal pressure of the chamber20rises, the deposition rate of the preliminary dielectric layer320pmay decrease, however, flowability may increase, and the amount of the carbon bridges in the preliminary dielectric layer320pmay increase. Accordingly, the flowability of the preliminary dielectric layer320pand the amount of the carbon bridges may be properly secured without excessively degrading the productivity, by maintaining an appropriate internal pressure of the chamber20as may be determined by one of ordinary skill in the art.

When the flow rate of the oxygen radicals O* increases, the deposition rate of the preliminary dielectric layer320pmay increase, however, the flowability of the preliminary dielectric layer320pand the amount of the carbon bridges may decrease. Methods according to some embodiments may provide appropriate flowability of the preliminary dielectric layer320pand the amount of the carbon bridges, and the deposition rate may be desirable.

For example, the porogens325may include at least one of various hydrocarbons represented by Chemical formulas 3 to 9 below.

Referring toFIG. 5B, the preliminary dielectric layer320pmay include SiCHO—R oligomer. The SiCHO—R oligomer may include an R—Si—(CH2)n-Si—R bond. Here, R may include the porogens325having carbon bridges of —CHx-CHy-, —H, —OH, —CH3, or alkyls having other various C, H, and O. Various types of SiCHO—R oligomers are exemplarily shown in (a) and (b).

Referring toFIG. 5C, the method of forming the dielectric layer320may include changing the preliminary dielectric layer320pto a porous dielectric layer320using a curing process. The curing process may include one of an ultra violet (UV) light irradiation process, an e-beam irradiation process, and/or a heat treatment process. When the curing process includes the UV light irradiation process, the UV light may include a multi-colored light with a plurality of wavelengths of 200 nm or more. By the curing process, the porogens325may be removed. Pores326may be formed where the porogens325are removed.

According to the present inventive concept, since the oxygen radicals O* are plasmarized outside the chamber and then supplied to the chamber, carbon bridges —(CH2)n- of the precursors may not be directly exposed to plasma that generates the oxygen radicals O*. For example, the carbon bridges —(CH2)n- may not be exposed to the microwaves. Since the carbon bridges —(CH2)n- are so vulnerable to plasma and/or microwaves to be easily separated, the preliminary dielectric layer320pand the dielectric layer320formed by methods according to some embodiments may have more carbon bridges —(CH2)n- than that formed using plasma in the chamber. A —Si—(CH2)n-Si— bonding structure may have superior physical endurance and/or mechanical strength to a —Si—O—Si— bonding structure, and therefore may be useful in a process of manufacturing a semiconductor device.

FIGS. 6A to 6Care cross-sectional views illustrating a method of forming a via plug structure400or a semiconductor device having the via plug structure400according to some embodiments of the present inventive concept. The via plug structure400may include the via plug structure140shown inFIG. 1AandFIG. 2A through 2K.

Referring toFIG. 6A, the method of forming the via plug structure400or the semiconductor device including the via plug structure400may include forming a via hole410in the lower layer405, and forming a preliminary via dielectric layer420pon a surface of the lower layer405and an inner wall of the via hole410. The preliminary via dielectric layer420pmay include a plurality of porogens425. The formation of the preliminary via dielectric layer420pmay be similar to those explained with reference toFIG. 5A.

Referring toFIG. 6B, the method may include changing the preliminary via dielectric layer420pto a porous via dielectric layer420by performing a curing process. The curing process may include one of an ultra violet (UV) light irradiation process, an e-beam irradiation process, and a heat treatment process. When the curing process includes the UV light irradiation process, the UV light may include a multi-colored light having a plurality of wavelengths of more than 200 nm. The porogens425may be removed by the curing process. Pores426may be formed where the porogens425are removed.

Referring toFIG. 6C, the method may include forming a via barrier layer430on the via dielectric layer420, forming a via seed layer440on the via barrier layer430, forming a via plug450on the via seed layer440, and forming a via plug structure400by performing a planarization process such as a CMP process.

For example, the via barrier layer430may include a barrier metal, such as Ti, TiN, Ta, and TaN, and the via seed layer440and the via plug450may include Cu. When the via seed layer440and the via plug450include the same metal, a boundary therebetween may be less visible. An upper surface of the lower layer405may be exposed by the planarization process.

FIG. 7Ais a diagram of a memory module2100according to some embodiments of the present inventive concept. Referring toFIG. 7A, the memory module2100may include a memory module substrate2110, a plurality of memory devices2120and terminals2130disposed on the memory module substrate2110. The memory module substrate2110may include a printed circuit board or a wafer. The memory devices2120may include a semiconductor device having a low-k dielectric layer according to various embodiments of the present inventive concept, or a semiconductor package including the semiconductor device having the low-k dielectric layer. The plurality of terminals2130may include a conductive metal. Each terminal2130may be electrically connected to each memory device2120. Since the memory module2100includes a semiconductor device having low leakage current and excellent on/off characteristics, module performance may be improved.

FIG. 7Bis a diagram of a memory card2200according to some embodiments of the present inventive concept. Referring toFIG. 7B, the memory card2200may include a semiconductor device having a low-k dielectric layer according to various embodiments of the present inventive concept mounted on a memory card board2210. The memory card2200may further include a microprocessor2220mounted on the memory card board2210. Input/output terminals2240may be disposed on at least one side of the memory card board2210.

FIG. 7Cis a block diagram of an electronic system2300according to some embodiments of the present inventive concept. Referring toFIG. 7C, the semiconductor device having a low-k dielectric layer according to various embodiments of the present inventive concept may be included in the electronic system2300. The electronic system2300may include a body2310. The body2310may include a microprocessor unit2320, a power supply2330, a function unit2340, and/or a display controller unit2350. The body2310may be a system board or mother board including, for example, a printed circuit board (PCB). The microprocessor unit2320, the power supply2330, the function unit2340, and the display controller unit2350may be mounted or installed on the body2310. A display unit2360may be arranged on a top surface or outside of the body2310. For example, the display unit2360may be arranged on a surface of the body2310and display an image processed by the display controller unit2350.

The power supply2330may receive a constant voltage from, for example, an external power source and may divide the voltage into various levels or may supply those voltages to the microprocessor unit2320, the function unit2340, the display controller unit2350, etc. The microprocessor unit2320may receive a voltage from the power supply2330to control the function unit2340and the display unit2360. The function unit2340may perform various functions of the electronic system2300. For example, if the electronic system2300is a mobile electronic apparatus such as a mobile phone, the function unit2340may have several components which can perform functions of wireless communication such as image output to the display unit2360and/or sound output to a speaker through dialing or communication with an external apparatus2370, and if a camera is installed, the function unit2340may serve as an image processor.

In some embodiments, when the electronic system2300is connected to, for example, a memory card in order to increase storage capacity, the function unit2340may be a memory card controller. The function unit2340may communicate signals with the external apparatus2370through a wired or wireless communication unit2380. In addition, when the electronic system2300needs a universal serial bus (USB) etc. in order to expand functions thereof, the function unit2340may serve as an interface controller. The semiconductor device having a low-k dielectric layer described in various embodiments according to the present inventive concept may be included in at least one of the microprocessor unit2320and the function unit2340.

FIG. 7Dis a block diagram of an electronic system2400according to some embodiments of the present inventive concept. Referring toFIG. 7D, the electronic system2300may include the semiconductor device having a low-k dielectric layer according to various embodiments of the present inventive concept. The electronic system2400may be included in a mobile apparatus or a computer. For example, the electronic system2400may include a memory system2412, a microprocessor2414performing data communication using a bus2420, a random access memory (RAM)2416, and a user interface2418. The microprocessor2414may program and control the electronic system2400. The RAM2416may be used as an operation memory of the microprocessor2414. For example, the microprocessor2414or the RAM2416may include a semiconductor device having a low-k dielectric layer according to various embodiments of the present inventive concept. The microprocessor2414, the RAM2416, and/or other components may be assembled in a single package. The user interface2418may be used to input data to, or output data from the electronic system2400. The memory2412may store codes for operating the microprocessor2414, data processed by the microprocessor2414, or external input data. The memory2412may include a controller and a memory device.

FIG. 7Eis a perspective view of a mobile wireless phone2500according to some embodiments of the present inventive concept. In some embodiments, the mobile wireless phone2500may be a tablet PC. In addition, the semiconductor device having a low-k dielectric layer according to various embodiments of the present inventive concept may be used in a portable computer such as a notebook, an MPEG-1 Audio Layer 3 (MP3) player, an MP4 player, a navigation apparatus, a solid state disk (SSD), a desktop computer, an automobile, or a home appliance, as well as a tablet PC.

A semiconductor device having a low-k dielectric layer according to various embodiments of the present inventive concept may include a dielectric layer having improved physical endurance and/or mechanical strength. Accordingly, the process of fabricating a semiconductor device may be stabilized, and productivity and/or yield may be improved. In addition, since physical and/or mechanical characteristics are improved, lifecycle of a semiconductor device may increase.