Logic circuits utilizing a composite junction transistor-MOSFET device

A composite device includes a junction transistor and an MOS transistor in which the channel region of the MOS transistor corresponds to a portion of the base region of the junction transistor. Such a device has a variety of applications in NAND and NOR circuits and as an analog transmission gate useful in a multiplexer.

FIELD OF THE INVENTION 
This invention relates to a composite device that combines the properties 
of a bipolar junction transistor and an insulated gate field effect 
transistor for use in logic circuits and to such logic circuits. 
BACKGROUND OF THE INVENTION 
It is known to integrate in separate surface areas of a common 
semiconductive chip both an insulated gate field effect transistor and a 
bipolar transistor. However, the need for separate surface areas for the 
two transistors limits the packing density possible. 
It has also been proposed hitherto to use common or over surface areas of a 
semiconductive chip to form various composite devices, particularly for 
use in power applications, such as variants of silicon controlled 
rectifiers, but these devices are not particularly suited for use as 
components of a logic circuit, where small size, high density and fast 
switching speeds are particularly important. 
SUMMARY OF THE INVENTION 
The present invention is directed to providing a composite device, useful 
in a logic circuit, that permits high density and fast switching speed by 
using a common surface region both as the channel of an insulated gate 
field effect transistor (IGFET) and as the base of a bipolar junction 
transistor. In particular, in accordance with the invention, a 
semiconductive chip, typically silicon, includes a region, such as a well, 
of one conductivity type, within which is included a limited region, or 
smaller well, of the opposite conductivity type, within the latter of 
which are included spaced apart a first surface region of the opposite 
conductivity type and a second surface region of the one conductivity 
type. This second surface region forms within the smaller well a PN 
junction, suitable for use as an emitting junction of a bipolar 
transistor, and an electrode connection to this second surface region 
serves both as the emitter electrode of the bipolar transistor and as the 
source electrode of the IGFET. An electrode connection to the first 
surface region serves as the base electrode for the junction transistor 
and the substrate connection of the IGFET. An insulating layer is provided 
over a limited surface portion of the smaller well that extends between 
its second surface region and the first well to serve as the gate oxide, 
and the underlying limited surface portion is used as the channel of the 
IGFET under control of an overlying gate electrode. A heavily doped 
surface region of the larger well serves as the contact region for the 
drain electrode of the IGFET and the collector of the junction transistor. 
Essentially when used in a logic circuit, the device includes a current 
path between the electrode connection to the second surface region of the 
smaller well and the electrode connection to the larger well that serves 
both as the source-to-drain path of an IGFET nand the emitter-to-collector 
path of a junction transistor. The gate electrode of the IGFET and the 
base electrode of the junction transistor are included in separate control 
circuit branches of the logic circuit and provide separate control of the 
path whereby it may be made conductive by appropriate potentials applied 
to either electrode. This characteristic adapts the device readily for use 
in logic circuits, such as two-input NAND or NOR circuits. Additionally, 
such device can also be used as an analog transmission gate for use in 
multiplexer circuits. 
The invention will be better understood from the following detailed 
description taken in conjunction with the accompanying drawings.

DESCRIPTION OF THE INVENTION 
Referring now to FIG. 1, there is shown a composite device 100 for use in 
the invention as discussed. It is formed in a silicon chip that 
encompasses a bulk or substrate monocrystalline N.sup.+ type portion 10 
over which has been grown a P-type epitaxial layer 12 in which are formed 
the various active components of an integrated circuit. There will be 
described only one composite device included within the epitaxial layer, 
although typically many will be incorporated spaced apart, along with 
other components of the integrated circuit. To this end, within the 
epitaxial layer there is formed a first relatively large N-type well 14 
within which is included the N.sup.+ type surface zone 18 spaced from an 
edge of the well 16 by a portion 17 of length d, that is chosen to be 
appropriate both for the channel of the IGFET of the composite device and 
for the base of the junction transistor of the composite device. For 
efficient operation, the distance d needs to be less than the diffusion 
length of the electrons so that they can readily diffuse between the 
emitting and collecting junctions 31 and 19, respectively, of the junction 
transistor. Typically this distance will be about one or two microns and 
will largely determine the switching speed of the device. Also within the 
well 16 is formed the P.sup.+ type surface zone 20 that will serve as the 
contact area of an electrode 22 to provide a low resistance connection to 
the P-type well 16. An electrode 24 is also positioned over the surface 
region 18 to serve as a low resistance connection thereto. Overlying the 
region 17 is a grown silicon oxide layer 26 suitable for serving as the 
gate insulator of the IGFET component of the composite device. Over this 
layer 26 is the gate electrode 28. As is known, one edge of this electrode 
should essentially line up with the edge at the surface of the PN junction 
18 formed between surface region 18 and the smaller well 16 while overlap 
of the edge at the surface of PN junction 19 is tolerable. Additionally, 
the larger well 14 is provided with an N.sup.+ type surface region 30 to 
serve as the contact area for electrode 32 to provide a low resistance 
connection to region 30. 
The resulting structure first includes the N-channel IGFET formed by region 
18 as the source, region 17 of the well 16 as the channel, and the regions 
14 and 30 as the drain, and electrodes 24, 28 and 32 as the source, gate 
and drain electrodes, respectively. It also includes the NPN junction 
transistor of which region 18 serves as the emitter, region 17 as the 
base, and regions 14 and 30 as the collector. This type of transistor is 
typically denoted as a lateral junction transistor. Electrodes 24, 22 and 
32 serve as the emitter, base, and collector electrodes, respectively. 
Referring now to FIG. 2, the composite device of FIG. 1 is shown, as 
separate NPN junction transistor 50 and N-channel IGFET 60, connected in a 
two-input NOR circuit 200. For the junction transistor 50, the emitter 51 
corresponds to electrode 24, the base 52 to electrode 22, and the 
collector 53 to electrode 32. For the IGFET 60, the source 61 corresponds 
to electrode 24, the gate 62 corresponds to electrode 28, and the drain 63 
to electrode 32. The input terminals 128 and 122 of the circuit 200, each 
available for the application of an input pulse, correspond to the gate 
electrode 28 and the base electrode 22, respectively. A load (illustrated 
as a resistor) 65 is connected between the common collector and drain, 
denoted as terminal 66, and a positive bus 67 Vdd of a voltage supply (not 
shown). The common emitter and source, denoted as node 68, is connected to 
a negative bus, shown as ground. Terminal 66 serves as an output terminal 
of circuit 200. 
It can be appreciated that if either or both of inputs 128 or 122 of 
control circuit branches of the circuit is at a "one", or a positive 
potential above the threshold voltage transistor 60 or positive enough to 
forward bias the emitter-base junction of transistor 50, of either of the 
two transistors, there is conduction through the load 65, and the voltage 
at the output terminal 66, composite device is close to ground potential 
which is defined as a low or a "0". On the other hand, when inputs 128 and 
122 are each at voltages such that transistors 50 and 60 are not biased 
on, the transistors do not conduct and the output terminal 66 remains 
essentially at Vdd which is defined as a high or a "1". 
The circuit 200 shown in FIG. 2 can also be adapted for use as a gated 
amplifier or sampling circuit. In particular, if there be applied an 
analog signal by way of input 122 to the base 52 of the junction 
transistor, this signal will little affect the voltage at the output 
terminal 66 so long as the voltage on input 128 is high enough that IGFET 
60 is already conducting in saturation. However, when the MOS transistor 
is non-conducting or at least not saturated, the signal applied at input 
122 is reflected as an inverted amplified signal at the output terminal 
66. Accordingly, if there be applied to input 128 a voltage which 
periodically cuts IGFET 60 off, at the intervals of cutoff, there become 
them available at output terminal 66, samples of the analog signal then 
being applied to the base electrode 52 of the junction transistor 50. 
These samples are inverted and amplified by the action of the junction 
transistor. 
Referring now to FIG. 3, there is shown the symbol 90 for use in 
representing the composite device 100 of FIG. 1 in circuit schematics. The 
various terminals of symbol 90 are given the reference numerals used for 
the corresponding elements in FIG. 1 with the postscript A. 
Referring now to FIG. 4, there is shown an analog multiplexing circuit 400 
that utilizes four composite devices 401, 402, 403, and 404, each shown by 
the symbol just discussed. Each of these devices is used as an analog 
transmission gate as previously discussed. To this end, each is operated 
to multiplex in turn samples of four analog signals V1, V2, V3 and V4, 
applied as first inputs to the four devices, into a common transmission 
path. The emitter-sources of each of the four composite devices is coupled 
to a terminal 414 which is shown coupled to a reference voltage which is 
ground. Typically the four composite devices will have been integrated in 
a common silicon chip in the usual integrated circuit fashion, as 
represented by their inclusion in broken line block 450. Each of the 
devices includes a separate load resistor 408 and a separate device output 
terminal 409. The various device output terminals are coupled by way of 
separate isolating resistors 410 to a common input terminal 411 of the 
operational amplifier 412, whose output terminal 405 supplies the common 
transmission path. The amplifier 412 serves as a buffer and has a resistor 
413 coupled between one input terminal 411 and output terminal 405. A 
second input of amplifier 412 is coupled to a terminal 414 which is 
coupled to a reference potential illustrated as ground. 
Each of the four analog signals, V1, V2, V3 and V4, to be multiplexed is 
supplied to a respective one of the bases 422 of the composite devices and 
each of the signals is sampled in turn by way of gating pulses supplied by 
the decoder 415 under control of the clock 416 to gates 423 of the 
composite devices. The decoder 41 supplies the gating pulses to the gates 
423 of the composite devices. As discussed above, during the interval of 
such a pulse, the analog signal is sampled. This sample is applied to the 
operational amplifier for insertion in the common transmission path by way 
of the multiplexer output terminal 405 to which this path is connected. 
It can be appreciated that by increasing the number of composite devices, 
the number of channels multiplexed is increased correspondingly. 
The composite device can also be made in the complementary form comprising 
a PNP junction transistor and a P-channel MOS transistor simply by 
reversing the conductivity types of the various zones of the device shown 
in FIG. 1. In such complementary form, the composite device is 
particularly well suited for use as a two-input NAND device. 
Referring now to FIG. 5, there is shown a two-input NAND circuit 500 in 
accordance with an embodiment of the present invention. Circuit 500 
comprises a PNP transistor 70, a P-channel MOS transistor 72 and a 
resistor 78. Transistors 70 and 72 are part of a composite device which is 
essentially the same as device 100 of FIG. 1, except the polarities of the 
regions are reversed. As shown, a terminal 73 is coupled to the emitter of 
the junction transistor, to the source of the MOS transistor, and to a 
negative bus 74 of a voltage supply (not shown). A terminal 76, which is 
connected to the collector of the junction transistor and to the drain of 
the MOS transistor, serves an output terminal, and is also coupled by way 
of a load resistor 78 to the bus 80 of the voltage supply, shown as 
ground. 
It can readily be appreciated when either of the input terminals 82 and 84 
of control circuit branches of the composite device is driven by an 
applied pulse to a voltage that permits either or both of the junction 
transistor and the IGFET to conduct, the voltage at output terminal 77 
approaches Vcc. However, when neither of the transistors is permitted to 
conduct, the voltage at the output terminal 77 remains essentially at 
ground. 
The circuit 500 described can also be used as an analog transmission gate 
in a manner analogous to that described earlier for FIG. 2. 
It should also be apparent that various changes should be made in the 
circuits described without departing from the spirit of the invention. In 
particular, it seems obvious that the various load resistors depicted may 
be replaced by active pulldown devices in the usual fashion to reduce 
power consumption. It should also be apparent that the particular 
characteristics of the composite devices described should make the devices 
useful in a variety of other circuit arrangements. 
It should also be evident that various fabrication techniques are available 
for the ready fabrication of a composite device of the kind involved.