Package structure for heat dissipation

A package structure and method of manufacturing is provided, whereby heat dissipating features are provided for heat dissipation. Heat dissipating features include conductive vias formed in a die stack, thermal chips, and thermal metal bulk, which can be bonded to a wafer level device. Hybrid bonding including chip to chip, chip to wafer, and wafer to wafer provides thermal conductivity without having to traverse a bonding material, such as a eutectic material. Plasma dicing the package structure can provide a smooth sidewall profile for interfacing with a thermal interface material.

BACKGROUND

Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. Dozens or hundreds of integrated circuits are typically manufactured on a single semiconductor wafer. The individual dies are singulated by sawing the integrated circuits along scribe lines. The individual dies are then packaged separately, in multi-chip modules, or in other types of packaging.

As semiconductor technologies further advance, stacked semiconductor devices, e.g., three dimensional integrated circuits (3DICs), have emerged as an effective alternative to further reduce the physical size of semiconductor devices. In a stacked semiconductor device, active circuits such as logic, memory, processor circuits, and the like are fabricated on different semiconductor wafers. Two or more semiconductor wafers may be installed or stacked on top of one another to further reduce the form factor of the semiconductor device. Package-on-package (POP) devices are one type of 3DIC wherein dies are packaged and are then packaged together with another packaged die or dies.

DETAILED DESCRIPTION

Embodiments provide a multi-die stacking structure (a die stack or chip stack) which includes heat dissipation through the use of a dummy thermal chip, through silicon vias (TSVs), thermal copper (Cu), or Cu bulk, or the like. Dies are stacked and bonded using a hybrid bonding technique. The structure can provide a multi-chip stack with chips of the same or different sizes. Chips can be singulated using plasma or laser dicing to provide smooth sides. Trenches can be formed in the backside of the package and filled with a thermal interface material (TIM) to provide heat dissipation. Embodiments can use hybrid bonding to provide die-to-die (chip on chip), die-to-wafer (chip on wafer), or wafer-to-wafer (wafer on wafer) bonding without using a material between bonded structures. Stacked chips can be thinned to provide for heat dissipation.

One problem faced in stacking packages or chips in a 3DIC package is heat dissipation. Heat created by the operation of a high performance device can inhibit performance. Molding compounds and underfill material traditionally used can inhibit heat dissipation and negatively impact the resulting package. By multi-die stacking using the disclosed embodiments can provide for high performance heat dissipation for high performance devices, such as a system-in-package (SiP) device or solution.

FIGS. 1 through 11illustrate intermediate steps in a process of forming a die stack, in accordance with some embodiments. Referring toFIG. 1, a portion of a semiconductor device100is illustrated. In the illustrated embodiments, the semiconductor device100comprises a processed wafer110having contact pads125formed thereon. In some embodiments, the semiconductor device100comprises one or more known good die (KGD) which have been functionally tested. Processed wafer110can comprise package areas or die areas150and non-package or non-die areas160. Generally, active and passive devices are formed in the die areas150and the non-die areas160do not have any active or passive devices formed therein. The non-package areas160can include dicing streets for singulating the die areas150into separate integrated circuit packages101aand101b.

In some embodiments, the processed wafer110comprises a substrate115, various active and passive devices on the substrate (not specifically shown), various metallization layers130(e.g., of interconnect137) over the substrate, vias120formed in the substrate, and seal rings135formed in a peripheral area of a die. Vias120can include dummy vias which are not electrically coupled to a device in the processed wafer110and conductive vias which are electrically coupled to at least one device or conductive feature in the processed wafer110. Dummy vias can be formed, for example, for heat dissipation of the substrate. Conductive vias can also serve for dissipating heat which may be a second purpose for the conductive vias.

Vias120are conductive and may be formed for a primary purpose of conducting heat away from heat generating devices in the substrate115. Thermally conductive vias120may traverse a substantial portion of the substrate115, such as the entire depth of the substrate or the entire depth of a portion of the substrate115having active and passive devices formed therein. Embodiments can also contain other vias (not shown) used for other purposes in the substrate115.

Vias120can be formed in the substrate by any suitable means. For example, vias can be formed by depositing a mask over the wafer, patterning the mask to form openings therein corresponding to the vias location, etching recesses in the substrate using the patterned mask, depositing an optional seed layer in the openings, depositing, for example, by electroplating, a conductive material in the openings, and removing the mask, for example, by an ashing process. Other methods can be used to create vias120.

The substrate may be formed of silicon, although it may also be formed of other group III, group IV, and/or group V elements, such as silicon, germanium, gallium, arsenic, and combinations thereof. The substrate may also be in the form of silicon-on-insulator (SOI). The SOI substrate may comprise a layer of a semiconductor material (e.g., silicon, germanium and/or the like) formed over an insulator layer (e.g., buried oxide and/or the like), which is formed on a silicon substrate. In addition, other substrates that may be used include multi-layered substrates, gradient substrates, hybrid orientation substrates, any combinations thereof and/or the like.

In some embodiments, the variety of active and passive devices may include various n-type metal-oxide semiconductor (NMOS) and/or p-type metal-oxide semiconductor (PMOS) devices such as transistors, capacitors, resistors, diodes, photo-diodes, fuses and/or the like.

In some embodiments, the metallization layers130of interconnect137may be formed over the active and passive devices and are designed to connect the various devices to form functional circuitry. The interconnect137may be formed of alternating layers of an insulating material140, such as a dielectric (e.g., low-k dielectric material), and conductive materials (e.g., copper) with vias (such as vias120or other vias) interconnecting the layers of conductive material130and may be formed through any suitable process (such as deposition, damascene, dual damascene, or the like). The insulating material140may be formed, for example, from phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), FSG, SiOxCy, Spin-On-Glass, Spin-On-Polymers, silicon carbon material, compounds thereof, composites thereof, combinations thereof, or the like, by any suitable method known in the art, such as spinning, chemical vapor deposition (CVD), and plasma enhanced CVD (PECVD).

In some embodiments, the processed wafer110may be a logic wafer, a memory wafer, a sensor wafer, an analog wafer, or the like. The processed wafer110may be formed using a complementary metal-oxide-semiconductor (CMOS) process, a micro-electro-mechanical systems (MEMS) process, a nano-electro-mechanical systems (NEMS) process, the like, or a combination thereof. As described below in greater detail, the processed wafer110will be stacked and singulated form stacked die structures.

Referring further toFIG. 1, contact pads125are formed on the processed wafer110. The contact pads125are physically and electrically coupled to circuitry in the processed wafer110, such as a via120(either an active via or dummy via) or a interconnect130. The contact pads125can eventually be coupled to external circuitry as described below in greater detail. The contact pads125may comprise a conductive material such as copper, tungsten, aluminum, silver, gold, the like, or a combination thereof, and may be formed by an electro-chemical plating process, an electroless plating process, ALD, PVD, the like, or a combination thereof. In some embodiments, the contact pads125may further comprise a thin seed layer (not shown), wherein the conductive material of the contact pads125is deposited over the thin seed layer. The seed layer may comprise copper, titanium, nickel, gold, manganese, the like, or a combination thereof, and may be formed by ALD, PVD, sputtering, the like, or a combination thereof.

The conductive material of the contact pads125, such as aluminum, is deposited over the processed wafer110and patterned to form the contact pads125as illustrated inFIG. 1. The contact pads125may be patterned using photolithography techniques. Generally, photolithography techniques involve depositing a photoresist material, which is subsequently irradiated (exposed) and developed to remove a portion of the photoresist material. The remaining photoresist material protects the underlying material, such as the conductive material of the contact pads125, from subsequent processing steps, such as etching. A suitable etching process, such as a reactive ion etch (RIE) or other dry etch, an isotropic or anisotropic wet etch, or any other suitable etch or patterning process may be applied to the conductive material of the contact pads125to remove the exposed portion of the conductive material and form the contact pads125. For example, exposed portions of the conductive material such as aluminum may be etched using a mixture of 80% phosphoric acid, 5% nitric acid, 5% acetic acid, and 10% de-ionized (DI) water.

In other embodiments, the contact pads125may be formed using alternative methods. For example, a photoresist material may be deposited over the processed wafer110, and subsequently irradiated (exposed) and developed to remove a portion of the photoresist material to form openings. The openings in the photoresist material are then filled with a conductive material to form the contact pads125. Subsequently, the photoresist material is removed and an insulating material140, such as described above with reference to the interconnect130, can optionally be added to partially or fully surround the vertical extents of the contact pads125. Alternatively, the contact pads125can be left on the surface of the processed wafer110, extending above the surface of the processed wafer110.

In some embodiments, a top surface of the processed wafer110can be planarized to make a top of the contact pads125substantially co-planar within process variations with a top surface of an insulating material140(e.g., as a top layer of an interconnect130, as described above). In some embodiments, contact pad125can extend above the surrounding insulating material140, as a result of the formation of the contact pad125. In some embodiments, contact pad125can extend above the surrounding insulating material140by etching back using a suitable etching technique to recess the surrounding insulating material140following planarization.

In some embodiments, one or more of vias120can be exposed at a top surface of the processed wafer110without adding a contact pad, such as contact pad125. For example, the vias120can be exposed using a planarization technique, such as a CMP or etch. A top of the exposed vias120can extend above the surrounding insulating material140by etching back the insulating material140using a suitable etching technique to recess the surrounding insulating material140following planarization or in combination with planarization.

Referring toFIG. 2, the processed wafer110can be flipped over and attached to a carrier205. Generally, carrier205provides temporary mechanical and structural support various features (e.g., processed wafer110) during subsequent processing steps. In this manner, damage to the device dies is reduced or prevented. Carrier205may comprise, for example, glass, ceramic, bulk silicon, and the like. In an embodiment, release layer210is used to attach processed wafer110to carrier205. In some embodiments, carrier205may be substantially free of any active devices and/or functional circuitry. In some embodiments, carrier205may comprise bulk silicon, and processed wafer110may be attached to carrier205by a dielectric release layer210. In some embodiments, the carrier205may comprise a support tape.

Release layer210may be any die attach film or any suitable adhesive, epoxy, ultraviolet (UV) glue (which loses its adhesive property when exposed to UV radiation), or the like. Release layer210may be formed using a deposition process, a spin coating, a printing process, a lamination process, or the like over the surface of the carrier205or over the surface of the processed wafer110. A surface of release layer210opposite insulating material140may be substantially level (e.g., planarized) to provide a suitable surface for carrier205to adhere to. In some embodiments, the release layer210may have a multilayer structure. In other embodiments, the release layer210may be a thermal type, wherein adhesive strength of the release layer is substantially reduced after exposing the release layer210to a suitable heat source.

In some embodiments, attaching the processed wafer110to the carrier205uses a fusion bonding process where an insulating layer of the processed wafer110(e.g., insulating material140or a subsequently deposited dielectric layer) is directly bonded to a dielectric release layer210to form a insulator-to-insulator bond. Further details on fusion bonding are discussed below in conjunction with hybrid bonding, with respect toFIG. 17.

In some embodiments, the processed wafer110is singulated into individual integrated circuit packages101aand101b, for example, by sawing, laser ablation, or the like. Subsequently, the carrier205can be removed from each of the integrated circuit packages101aand101b. Removing the carrier205may include applying UV radiation to release layer210, a mechanical grinding process, an etch back process, a heating process, combinations thereof, or the like. In some embodiments, the resulting integrated circuit packages101aand101bcan be tested to identify known good dies (KGDs) for further processing. In some embodiments, testing can be done for KGD prior to singulation or prior to removal of the carrier205. The resulting integrated circuit packages101aand101bcan be referred to as packages, dies, or chips.

Referring toFIG. 3, in embodiments where the integrated circuit packages are left as a processed wafer110, the processed wafer110is thinned to create processed wafer111. Thinning can be done by a CMP process, etching, or other suitable process. Thinning exposes vias120and also reduces the thickness to provide better heat dissipation and take less space. After thinning, the processed wafer111can be about 10 to 50 μm thick, for example, about 20 μm thick.

Referring toFIG. 4, dies212are bonded to processed wafer111. In some embodiments, the dies212are attached to the processed wafer111using, for example, a pick and place apparatus. In other embodiments, the dies212may be attached to the processed wafer111manually, or using any other suitable method.

Dies212can be the same type of device as the devices in processed wafer111or can be a different type of device. For example, if making a memory cube, dies212can be the same as the devices present in the processed wafer111. In particular, dies212can correspond to integrated circuit packages101aor101b, for example. That is, dies212can result from the singulation of another processed wafer consistent with processed wafer110, as described above. In some embodiments, dies212are KGDs.

In some embodiments, contact pads125of dies212are hybrid bonded to vias120of processed wafer111. Hybrid bonding has a benefit of not needing solder materials between the two bonded connectors. Hybrid bonding creates a bonding interface between two devices which includes direct metal-to-metal bonding of the metal features in a first device to metal features in a second device as well as fusion bonding (or dielectric-to-dielectric bonding) of insulating materials in the first device to insulating materials in the second device. Any suitable hybrid bonding process can be used; however, a process for hybrid bonding is described in detail below with respect toFIGS. 17 and 18.

In some embodiments, prior to hybrid bonding, contact pads (not shown) can be formed over the vias120of the processed wafer111. A process for forming contact pads is described above with respect toFIG. 1and is not repeated.

In some embodiments, the dies212are hybrid bonded to the processed wafer111. In the hybrid bonding, the contact pads125of dies212are directly bonded to vias120of processed wafer111. Also, the insulating materials140of dies212and the substrate115of processed wafer111(seeFIG. 1) are fusion bonded together. Thus, no underfill is needed between the dies212and the processed wafer111. The process for hybrid bonding will be described in more detail below with respect toFIGS. 17 and 18.

In other embodiments, dies212can be bonded to vias120by forming a eutectic-type connector or contact pad over the vias120of the processed wafer111, bringing the dies212and processed wafer111together after aligning the corresponding contacts, and reflowing the eutectic materials to form a physical and electrical coupling. Alternatively, a eutectic-type connector can be formed on the dies212or both the dies212and processed wafer111. In such embodiments, an underfill material can be used between the dies212and processed wafer111, or alternatively a gap-fill material, such as described below, can provide underfill capabilities.

Referring toFIG. 5, a gap-fill material216is formed over the workpiece to substantially fill the spaces between dies212. In some embodiments, the gap-fill material216can extend over the dies212. In some embodiments, the spaces may only partially be filled by the gap-fill material216. In some embodiments, the gap-fill material216may comprise a molding compound such as an epoxy, a resin, a moldable polymer, polymide, or the like. The molding compound may be applied while substantially liquid, and then may be cured through a chemical reaction, such as in an epoxy or resin. In other embodiments, the molding compound may be an ultraviolet (UV) or thermally cured polymer applied as a gel or malleable solid. In some embodiments, the gap-fill material216may comprise a non-polymer like silicon dioxide, silicon nitride, or the like, such as another oxide or nitride, which is deposited using any suitable process. For example, For example, the gap-fill material may be formed by CVD, PECVD or ALD deposition process, FCVD, or a spin-on-glass process.

Referring toFIG. 6, the gap-fill material216and dies212can be thinned to create gap-fill material217and thinned dies213. Thinning can be done by a CMP process, grinding, etching, or other suitable process. Thinning exposes vias120in dies213and also reduces the thickness of dies213to provide better heat dissipation and take less space. After thinning, the dies213can be about 10 to 50 μm thick, for example, about 20 μm thick. In some embodiments, a top surface of the gap-fill material217and dies213are substantially co-planar within process variations. The layer221comprises the combined gap-fill material217and dies213.

Referring toFIG. 7, in some embodiments, second dies222are bonded to dies213. In some embodiments, die222can be the same type of device or chip as die212. In some embodiments, die222can be a different type of device or chip. Dies222can be bonded to dies213in like manner as dies212are bonded to processed wafer111, such as described above with respect toFIG. 4, and is not repeated here. In particular, dies222can be hybrid bonded to dies213by a direct bonding of contact pads125of dies222and vias120or contact pads of dies213and fusion bonding of the insulating materials140of dies222and the substrate115(seeFIG. 1) of dies213.

Referring toFIG. 8, a gap-fill material226is formed over the workpiece to substantially fill the spaces between dies222. The process and materials is the same as those discussed above in relation toFIG. 5for the formation of gap-fill material216, and is not repeated.

Referring toFIG. 9, the gap-fill material226and dies222have been thinned to create gap-fill material227and thinned dies223. Thinning can be done in a similar manner as described above with respect toFIG. 6, resulting in a layer231that can be about 10 to 50 μm thick, for example, about 20 μm thick, comprising gap-fill material227and thinned dies223.

Still referring toFIG. 9, the process ofFIGS. 7-9can be repeated to bond additional dies to the die stack. For example,FIG. 9illustrates a fourth layer241comprising a thinned die233and gap-fill material237. One of skill in the art will understand that fewer or additional layers can be included than the number of layers illustrated. Although shown in distinctive layers, in some embodiments, the combined gap-fill material257can appear as a single material layer. In other embodiments, the combined gap-fill material257will maintain individual layers. The thinned die stack253comprises a combination of the thinned dies213,223, and233.

Referring toFIG. 10, the integrated circuit dies comprising die stacks can be singulated from the workpiece, resulting in integrated circuit packages102aand102b(ofFIG. 11). Singulation270can occur by any acceptable process, including plasma dicing, laser dicing, mechanical saw, or a combination thereof. Singulation occurs through the non-package regions160on scribe lines or dicing streets of the workpiece. The singulation cuts through the processed wafer111, down to the release layer210. In some embodiments, the singulation can continue through the release layer210and may continue into or through the carrier205.

An advantage of plasma dicing packages102aand102bis that, with the gap-fill material257, smooth sidewall profiles can be achieved through the plasma dicing.

Plasma dicing can be achieved by performing an etch of the layers of gap-fill material. A mask275can be deposited over the die stacks and patterned to expose the gap-fill material257for singulation. When the gap-fill material257is polysilicon, a process gas for plasma dicing may include Cl2/NF3/He or SF6or NF3or CF4or other suitable halogens based etch gas at a temperature of less than 200° C. (e.g., less than 100° C.), an RF power of less than 3 kW (e.g., less than 600 W), and at a pressure of less than 10 torr (e.g., less than 3 torr). When the gap-fill material257is a silicon oxide, a process gas for plasma dicing may include C4F6or a fluorine-based gas, at a temperature of less than 200° C. (e.g., less than 150° C.), an RF power of greater than 50 W (e.g., greater than 100 W), and at a pressure of less than 3 torr (e.g., less than 200 mtorr). When the gap-fill material257is a SiOC, a process gas for plasma dicing may include N2and H2, or SO2and O2, at a temperature of less than 200° C. (e.g., 20-100° C.), an RF power of greater than 100 W (e.g., greater than 300 W), and at a pressure of less than 3 torr (e.g., less than 200 mtorr).

Process gasses and environment can be adjusted based on the material of the gap-fill material257. To continue to plasma dicing through the processed wafer111, the process gasses may be adjusted to suitably etch the processed wafer111, depending on the material of the processed wafer111. Similarly, to continue to plasma dicing through the carrier205, the process gasses may be adjusted to suitably etch the carrier205, depending on the material of the carrier205.

Referring toFIG. 11, following the dicing, the carrier205is removed from the packages102aand102b. Removing the carrier205may include applying UV radiation to release layer210, a mechanical grinding process, an etch back process, a heating process, combinations thereof, or the like.

In some embodiments, the packages102aand102bare memory cubes280, comprising a wafer layer111′ and stacked chips261′. Following the singulation, additional processing or packaging can be applied to the packages102aand102b, for example, forming contacts thereon, mounting another package thereto, or mounting into another device or structure.

FIGS. 12 through 16illustrate intermediate steps in a process of forming a die stack, in accordance with some embodiments. Embodiments consistent with those illustrated inFIGS. 12 through 16are similar to the embodiments illustrated inFIGS. 1 through 11except that in the embodiments illustrated inFIGS. 12 through 16, rather than provide a processed wafer on carrier205, individual packages, such as integrated circuit packages101aand101b, are attached to carrier205. The processes and materials used to form embodiments such as illustrated inFIGS. 12 through 16that are similar to those for the previously described embodiments will not be repeated.

Referring toFIG. 12, the dies212are attached to the carrier205using, for example, a pick and place apparatus. In other embodiments, the dies212may be attached to carrier205manually, or using any other suitable method. Dies212can be attached to carrier205via a release layer210or fusion bonded to carrier205, in a process and using materials such as described above with respect to the attachment of processed wafer110to carrier205ofFIG. 2.

Referring toFIG. 13, a gap-fill material216is formed over the dies212. The process and materials can be the same as described above with respect toFIG. 5, and is not repeated.

Referring toFIG. 14, in some embodiments, the gap-fill material216and dies212ofFIG. 13can be thinned using processes and materials such as described above with respect toFIG. 6, and is not repeated. The resulting layer221, which includes the thinned gap-fill material217and thinned dies213, can be between about 10 and 50 μm thick, such as about 20 μm.

Referring toFIG. 15, the processes ofFIGS. 12 through 14can be repeated to attach additional dies. Additional dies can be attached by bonding using processes and materials similar to those described above with respect toFIG. 4, which is not repeated. Four total layers261include individual layers221,231,241, and251. One of skill will understand that additional layers can be included or fewer layers can be included. As few as two layers can be provided. Although shown in distinctive layers of gap-fill material217,227,237, and247, in some embodiments, the combined gap-fill material257can appear as a single material layer. In other embodiments, the combined gap-fill material257will maintain individual layers. The thinned die stack253comprises a combination of the thinned dies213,223,233, and243.

Referring toFIG. 16, the integrated circuit dies comprising die stacks can be singulated from the workpiece, resulting in integrated circuit packages102aand102b. Singulation can occur by using processes and materials such as described above with respect toFIG. 10, such as plasma dicing, laser dicing, mechanical saw, or a combination thereof, and is not repeated. Following the dicing, the carrier205is removed from the packages102aand102b. Removing the carrier205can include processes and materials such as described above with respect toFIG. 11, and is not repeated.

In some embodiments, the packages102aand102bofFIG. 16are memory cubes280, comprising stacked chip layers221′,231′,241′, and251′. Following the singulation, additional processing or packaging can be applied to the packages102aand102b, for example, forming contacts thereon, mounting another package thereto, or mounting into another device or structure.

Referring toFIG. 17, structures for a hybrid bonding process are illustrated. Structures310and330are portions of different chips, wafers, dies, integrated circuit devices, packages, and so forth which are to be hybrid bonded.FIG. 17illustrates three different types of hybrid bonding structures. Structure310has a via311, a via with contact pad312, and a via with contact pad313. Structure330has a via331, a via with contact pad332, and a via333. Hybrid bonding includes direct metal-to-metal bonding of the metal features in the structure310and structure330as well as fusion bonding insulating materials321in the structure310with insulating materials341in the structure330.

Direct bonding may occur between a via with contact pad313and via333, a via with contact pad312and via with contact pad332, and a via311and via331. In some embodiments, the contact pads, e.g.,312,313, and332, can be bonded to an underbump metallization or to a metal line, for example, from a redistribution layer. The bonding of via311to via331is representative of a via-to-via hybrid bonding. The bonding of the contact pad of312to the contact pad of332is representative of a pad-to-pad hybrid bonding. The bonding of the contact pad of313to the via333is representative of a via-to-pad or pad-to-via hybrid bonding. The vias and contact pads of structures310and330are made of conductive materials, such as copper, gold, tin, and the like, or alloys thereof. The conductive materials of each of the vias or contact pads in structure310can be the same or different than the conductive materials in structure330.

Structures310and330also comprise an insulating material321and341, respectively. Insulating material can be an oxide, oxynitride, dielectric, polymer, and so forth. In some embodiments, insulating material321can be the same material as insulating material341, while in other embodiments, insulating material321can be different than insulating material341.

In a hybrid bonding process, the vias and pads of structure310are aligned and contacted to the vias and pads of structure330. Insulting materials321of structure310are also be contacted to insulating materials341of structure330. Subsequently an anneal may be performed to directly bond the conductive materials and fusion bond the insulating materials together. The anneal causes the inter-diffusion of the metals in the pad/pad/via of310and via/pad/via of330to cause a direct metal-to-metal bond. In some embodiments, when insulating material321or341comprises a polymer, the annealing temperature is lower than about 250° C. in order to avoid damage to the polymer. For example, the annealing temperature (with the presence of polymer) may be in the range between about 150 C. and about 250 C., such as about 200 C. The annealing time may be between about 1 hour and 3 hours, such as about 1.5 hours. In embodiments where both insulating materials321or341are formed of inorganic dielectric materials such as an oxide or oxynitride, the annealing temperature may be higher, which is lower than about 400 C. For example, the annealing temperature (without the presence of polymer) may be in the range between about 250 C. and about 400 C., such as about 325 C. and the annealing time may be in the range between about 1 hour and about 3 hours, such as about 1.5 hours.

The bonded conductive materials of structures310and330may have distinguishable interfaces. The insulating material321may also be fusion bonded to the insulating material341, with bonds formed therebetween. For example, the atoms (such as oxygen atoms) in one of the insulating materials321and341can form chemical or covalence bonds (such as O—H bonds) with the atoms (such as hydrogen atoms) in the other one of the insulating materials321and341. The resulting bonds between the insulating materials321and341are insulator-to-insulator bonds, which may be inorganic-to-polymer, polymer-to-polymer, or inorganic-to-inorganic bonds in accordance with various embodiments. Slight variations in surfaces of the bonding structures can be overcome through the annealing process while pressure keeps the structures together. In some embodiments a pressing force of about 1 to 10 Newtons can be exerted, such as about 6 Newtons, to press the structures310and330together. Hybrid bonding can occur in an environment from about 1 atm to about 100 atm, such as about 5 atm. Expansion of materials under anneal temperatures can complete the bonding and substantially eliminate voids.

Prior to bonding, the structures310and330can be prepared, for example by a CMP or grinding process to expose contacts or thin the structures. In some embodiments, hybrid bonding may enable connectors to have a fine pitch, for example less than about 5 μm. As such, hybrid bonding may allow dies, such as dies101aand101bto comprise a high density of connections. Further, the hybrid bonding process allows for the bond between the two structures to not include a solder material, and thus, may increase the reliability and yield of package structures. Further still, because no connectors are used between dies, the hybrid ponding process results in a thinner die stack.

Referring toFIG. 18, a hybrid bonding process is illustrated when one or more of the devices being bonded are known good dies (KGDs). In such embodiments, KGD testing may require an aluminum pad for KDG testing. Structure405can be bonded to structure410. Structure405and structure410can each be a portion of a die, wafer, package, and so forth. A via415is electrically coupled to a metal layer420. An aluminum pad425is formed on the metal layer. Insulating layer445is part of the die or wafer for KGD. For illustration purposes, two possible options are provided to bond a wafer or die having an aluminum pad. A further insulating layer450is formed over the die or wafer.

In some embodiments, an opening is formed down to the metal layer420. The opening is filled with a conductive material to form via430to the metal layer420. In some embodiments, an opening is formed down to the aluminum pad425. In some embodiments, the opening is filled with a conductive material to form via435. A contact pad441/440can be formed over the via430/435. In some embodiments, a combination of techniques can be used, with some contact pads being coupled to the aluminum pad425and other contact pads being coupled to the metal layer420. In some embodiments, both techniques can be used to achieve an electrically identical signal at the contact pad441and contact pad440. In some embodiments, the structure can mix use of vias430and435on a connector-by-connector basis.

Subsequently, the structure405can be bonded to the structure410, using any of the bonding techniques described herein, including the hybrid bonding as discussed above with respect toFIG. 17.

FIG. 19illustrates a magnified portion ofFIG. 15that shows layer221from one of the die stacks, e.g.,102a. In some embodiments layer221may be a portion of processed wafer111. Vias120/415are illustrated as being coupled to a metallization layer130/420. In some embodiments vias120/415may be electrically isolated from the metallization layer130/420. Metallization layer130/420is illustrated as being a part of interconnect137and is formed of alternating layers of conductive material and insulating material, such as insulating material140/445. Vias430may connect to interconnect137or another metal feature which is electrically coupled to aluminum pad425on one end and contact pad441on the other end. In some embodiments, vias435may connect directly to an aluminum pad425on one end and contact pad440on the other end.

Aluminum pad425may be coupled to interconnect137. A passivation layer490may be formed over interconnect137. An opening may be formed in passivation layer490to expose a metal contact coupled to interconnect137and aluminum pad425formed therein. Aluminum pad425may be formed from a patterned metal layer (not shown). Another passivation layer492may be formed over aluminum pad425and the aluminum pad425revealed through an opening formed in passivation layer492. The process of forming aluminum pads425in connector layer495may be done, for example, for the purposes of known good die (KGD) testing. Subsequent to KGD testing, an insulating material494may be formed over the aluminum pads425. Aluminum pads425and insulating material494may be formed as part of the processing of wafer110, such as discussed above with respect toFIG. 1or thinned processed wafer111, such as discussed above with respect toFIG. 3, for example.

In some embodiments, a die attach film496may comprise insulating material selected such that a fusion bond can be formed between die attach film496and released layer210. In some embodiments, die attach film496may comprise a suitable adhesive layer, such as discussed above with respect to release film210ofFIG. 2. Similarly, an insulating layer498may be formed over layer221, and selected such that a fusion bond can be formed between insulating layer498of layer221and die attach film496of layer231.

FIGS. 20 through 24illustrate a die stack according to some embodiments where connectors are formed on a front side of the die stack.FIG. 20illustrates a die stack following the step illustrated inFIG. 9. A carrier206may be attached to the backside of the die stack100by a release layer211. The carrier206may include materials similar to carrier205which are not repeated. Release layer211may include materials similar to release layer210. For example, release layer211may be a dielectric or insulating layer provided to fusion bond carrier206to the die stack100.

Referring toFIG. 21, following the attachment of the carrier206, the carrier205may be removed using a suitable process. In some embodiments, release layer210may be exposed to UV light, thereby degrading an adhesive and allowing the carrier205to come free. In some embodiments, carrier205may be removed by grinding or etching, or the like. Following the removal of carrier205, contact pads425(or125ofFIG. 1) may be exposed. In some embodiments, insulating material450(or494ofFIG. 19) may be recessed by a mechanical process such as CMP or grinding, or by etching, or by a combination thereof, to expose the contact pad425/125.

Referring toFIG. 22, connectors985are formed on the front side of the die stack. In some embodiments, connectors985are formed on contact pad425/125. In some embodiments, connectors985are formed on a front side of the processed wafer511. Connectors985can be formed using any suitable process and comprise various configurations. In some embodiments, the connectors985may be controlled collapse chip connection (C4) bumps, micro-bumps, solder balls, or the like. In some embodiments, connectors985can be coupled to the exposed contact pads425. In other embodiments, openings (not shown) may be made in the front side of the processed wafer111, the opening exposing metal features of the processed wafer111. Connectors985are formed on the contact pads or in the openings. In some embodiments, an under bump metallurgy (UBM) layer can be formed on the contact pads or in the openings prior to the formation of the connectors985. In the illustrated embodiment, the connectors985have lower portions985L comprising a conductive material and upper portions985U comprising a solder material. The lower portions985L and the upper portions985U may be also referred as conductive pillars985L and solder caps985U, respectively.

Connectors985can be coupled to conductive features of the processed wafer111. Such conductive features can include for example an interconnect137(seeFIG. 19), vias, such as via120,130,415,420,430, or435(seeFIG. 19), or other metal traces or lines.

Referring toFIG. 23, the stacked chips may be singulated using processes and materials such as those discussed above with reference toFIG. 10, and are not repeated. Referring toFIG. 24, the singulated die stacks102aand102bare illustrated, in accordance with some embodiments. Optionally, the carrier206aand206bmay be removed, using a suitable technique.

FIGS. 25 through 27illustrate a die stack according to some embodiments where connectors are formed on a front side of the die stacks.FIG. 25illustrates a die stack following the step illustrated inFIG. 15. A carrier206may be attached to the backside of the die stack100by a release layer211. The carrier206may include materials similar to carrier205which are not repeated. Release layer211may include materials similar to release layer210. For example, release layer211may be a dielectric or insulating layer provided to fusion bond carrier206to the die stack100.

Referring toFIG. 26, following the attachment of the carrier206, the carrier205may be removed using a suitable process. In some embodiments, release layer210may be exposed to UV light, thereby degrading an adhesive and allowing the carrier205to come free. In some embodiments, carrier205may be removed by grinding or etching, or the like. Following the removal of carrier205, contact pads425(or125ofFIG. 1) may be exposed, such as discussed above with respect toFIG. 21.

Connectors985are formed on the front side of the die stacks using processes and materials such as those about with respect toFIG. 22, and are not repeated. Connectors985may be coupled to conductive features of the chip layer221. Such conductive features can include for example an interconnect137(seeFIG. 19), vias, such as via120,130,415,420,430, or435(seeFIG. 19), or other metal traces or lines.

Referring toFIG. 27, the stacked chips may be singulated using processes and materials such as those discussed above with reference toFIG. 10, and are not repeated. The singulated die stacks102aand102bare illustrated, in accordance with some embodiments. Optionally, the carrier206aand206bmay be removed, using a suitable technique.

FIGS. 28 through 44illustrate various intermediate steps in creating an application package500, in accordance with some embodiments. The application package500can be formed to include a combination of memory die stacks, logic die stacks, thermal chip stacks, and other devices, such as a power controller, wireless radio device, other memory, other logic, sensors, and so forth.

Referring toFIG. 28, application package500comprises a processed wafer510comprising a substrate515having devices formed therein. Substrate515can be formed of silicon, although it may also be formed of other group III, group IV, and/or group V elements, such as silicon, germanium, gallium, arsenic, and combinations thereof. The substrate may also be in the form of silicon-on-insulator (SOI). The SOI substrate may comprise a layer of a semiconductor material (e.g., silicon, germanium and/or the like) formed over an insulator layer (e.g., buried oxide and/or the like), which is formed on a silicon substrate. In addition, other substrates that may be used include multi-layered substrates, gradient substrates, hybrid orientation substrates, any combinations thereof and/or the like.

Processed wafer510can include several packages, including other application packages500which are formed in accordance with the description below. The multiple application packages500can all be formed at the same time. In some embodiments, processed wafer510includes packages of different types or designs than the illustrated application packages500. In some embodiments, processed wafer510includes packages including different variations of the embodiments of application packages500discussed below.

Application package500can comprise a system on a chip that includes a logic area550, a memory area560, and a thermal dissipation area570. In some embodiments, thermal dissipation area570is omitted. In such embodiments, it can be understood that any description below relating to the thermal dissipation area570does not apply.

Still referring toFIG. 28, processing unit520can include a logic device, such as a central processing unit or graphics processing unit or other suitable processor formed in the substrate515. Processing unit520can be formed using any suitable technique. The particular strategy for forming processing unit520is not critical to the use and understanding of the present application. In some embodiments, the processing unit520can be a separate die embedded in processed wafer510. Processing unit520can include transistors, such as NMOS, PMOS, and CMOS transistors, as well as other devices and interconnections.

Vias525can be formed in substrate515adjacent to the processing unit520. In some embodiments, vias525can be formed as part of a memory die formed in wafer510. In some embodiments, vias525can be formed as a part of a memory die region for receiving a memory die. Vias525can be conductive vias which are electrically coupled to an interconnect530. In some embodiments, one or more of the vias525can be dummy vias, i.e., floating or not electrically coupled to any device or metal feature in substrate515. Vias525can be formed using processes and materials similar to those described above with respect to the vias120ofFIG. 1.

Interconnect530can be coupled to processing unit520, vias525, and vias535. Interconnect530can provide connections between vias525and processing unit520, between processing unit520and connectors or connector pads, between processing unit520and other devices formed in substrate515, between vias525and connectors or connector pads, between vias525and other devices formed in substrate515, and so forth.

Interconnect530can be formed using processes and materials such as those described above with respect to the interconnect130ofFIG. 1. Insulating material540may be formed within and over the interconnect530to electrically separate conductive elements of interconnect530. Insulating material540may be formed by processes and materials such as those described above with respect to insulating material140ofFIG. 1.

Still referring toFIG. 28, vias535in the thermal dissipation area570can, in some embodiments, be conductive vias, i.e., vias coupled to the interconnect530or another conductive feature. In some embodiments, vias535are dummy vias, similar to the dummy vias525, described above. In some embodiments, vias535can include a combination of dummy vias and conductive vias. Vias535can be formed using processes and materials similar to those described above with respect to the vias120ofFIG. 1.

Vias525/535/546are thermally conductive and may be formed for a primary purpose of conducting heat away from heat generating devices in the substrate515. Thermally conductive vias525/535/546may traverse a substantial portion of the substrate515, such as the entire depth of the substrate or the entire depth of a portion of the substrate515having active and passive devices formed therein. Embodiments can also contain other vias (not shown) used for other purposes in the substrate515.

Referring toFIG. 29, the workpiece/processed wafer510can be flipped over and attached to a carrier605. Generally, carrier605provides temporary mechanical and structural support various features (e.g., processed wafer510) during subsequent processing steps. In this manner, damage to the device dies is reduced or prevented. Carrier605may comprise, for example, glass, ceramic, bulk silicon, and the like. In an embodiment, release layer610is used to attach die processed wafer510to carrier605. In some embodiments, carrier605may be substantially free of any active devices and/or functional circuitry. In some embodiments, carrier605may comprise bulk silicon, and processed wafer510may be attached to carrier605by a dielectric release layer610. In some embodiments, the carrier605may comprise a support tape.

Release layer610can comprise materials and processes in accordance with those discussed above with respect to release layer210.

In some embodiments, attaching the processed wafer510to the carrier605uses a fusion bonding process where an insulating layer of the processed wafer510(e.g., insulating layer540or a subsequently deposited dielectric layer) is directly bonded to a dielectric bonding layer610or to a dielectric surface of the carrier605to form a insulator-to-insulator bond.

Referring toFIG. 30, in some embodiments the processed wafer510is thinned to create processed wafer511. Thinning can be done by a CMP process, etching, or other suitable process. After thinning, the processed wafer111can be about 10 to 50 μm thick, for example, about 20 μm thick. Thinning exposes vias525and vias535and also reduces the thickness to provide better heat dissipation and take less space. In some embodiments, thinning can also expose metal features (not shown) on the processing unit520. These metal features may or may not be electrically connected to devices within the processing unit520. In some embodiments, contacts or contact pads545can be formed on the processing unit520. In some embodiments, the contact pads545are coupled to the exposed metal features. In some embodiments, the contact pads545are formed using processes and materials similar to those described above in the formation of contact pads125inFIG. 1. The contact pads545can be coupled to conductive features embedded within the processing unit520, such as vias546, traces, and metal lines (e.g.530).

Referring toFIG. 31, dies612,614, and618are bonded to processed wafer511. In some embodiments, the dies612,614, and618are attached to the processed wafer511using, for example, a pick and place apparatus. In other embodiments, the dies612,614, and618may be attached to the processed wafer511manually, or using any other suitable method.

Die612can be a memory die or other type of die. For example, die612can be a memory die similar to the integrated circuit packages101aor101b, discussed above in relation toFIG. 2. Die614can be a thermal chip comprising thermally conductive vias542and a surrounding material552. In some embodiments, die618is a thermal chip similar to die614comprising thermally conductive vias541and a surrounding material551. In other embodiments, die618is another type of device die, such as a sensor, power converter, radio, or the like. The use of dies612,614, and618are merely illustrative and is not intended to be limiting. It should be understood that additional dies can be attached in other areas of the processed wafer511. Dies612and614can be referred to as heat dissipating structures.

In some embodiments, in a separate process, thermal chips614and618can be made by forming vias, such as via542or541in a wafer comprised of the surrounding material551or552, respectively. The wafer can be singulated into thermal chips, such as thermal chips614and618. The wafer of the thermal chip can comprise a semiconductor material or an insulating material. In some embodiments, the wafer of the thermal chips614and618can comprise a semiconductor material that is one of the materials described above with respect to the substrate material115. In some embodiments, the wafer of the thermal chips614and618can comprise an insulating material that is one of the materials described above with respect to the carrier205ofFIG. 2.

The vias542/541can be formed in the surrounding material551/552by depositing a mask over the surrounding material, patterning the mask, etching recesses into the surrounding material551/552, depositing a seed layer, electroplating the seed layer to fill the recess and create the vias, and removing the mask. In some embodiments a second mask can be used over the seed layer to prevent the electroplating of the seed layer in places other than the recess. In some embodiments, other suitable processes and materials can be used to form the vias542/541. In some embodiments, contact pads (not shown) can be formed over the vias of the thermal chips614and618. Contact pads can be formed, for example, using processes and materials such as described above with respect toFIG. 1andFIG. 18and is not repeated.

Still referring toFIG. 31, in some embodiments, the dies612,614, and618can be hybrid bonded to processed wafer511by aligning and directly bonding the contacts of the die612to vias525, vias542to contacts pads545or vias546, and vias541to vias535. It should be understood that the bonding of the vias and contacts illustrated inFIG. 31are merely an example, and other configurations of hybrid bonded elements are contemplated. Hybrid bonding can be carried out using processes and materials as described above with respect toFIG. 17which are not repeated, including any combination of direct bonding of vias and contacts. Also as discussed above, as a result of the hybrid bonding, fusion bonding of insulating materials on the dies612,614, and618can also be achieved. Thus, no underfill is needed between the dies612,614,618and the processed wafer511.

In some embodiments, die612is bonded to vias525, die614is bonded to contacts pads545or vias546, and die618is bonded to vias535by forming a eutectic-type connector or conductive pillar over the vias525/535of the processed wafer511, bringing the dies612,614, and614together with the processed wafer511after aligning the corresponding contacts, and reflowing the eutectic materials to form a physical and electrical coupling. Alternatively, a eutectic-type connector or conductive pillar can be formed on the dies612/614/618, or on both the dies612/614/618and the processed wafer511. In such embodiments, an underfill material can be used between the dies612/614/618and processed wafer511, or alternatively a gap-fill material, such as described below, can provide underfill capabilities.

Referring toFIG. 32, a gap-fill material616is formed over the workpiece to substantially fill the spaces between the dies612,614, and618. The processes and materials can be the same as described above with respect to the gap-fill material ofFIG. 5and are not repeated.

Referring toFIG. 33, the gap-fill material616and dies612,614, and618can be thinned to create gap-fill material617and thinned dies613,615, and619. Thinning can be done by a CMP process, grinding, etching, or other suitable process. Thinning exposes vias120in die613, vias542in die615, and vias541in die619, and also reduces the thickness of dies613/615/619to provide better heat dissipation and take less space. After thinning, the dies613/615/619can be about 10 to 50 μm thick, for example, about 20 μm thick. In some embodiments, a top surface of the gap-fill material617and top surfaces of the dies613/615/619are substantially co-planar within process variations. The layer621comprises the combined gap-fill material617and thinned dies613/615/619.

Referring toFIG. 34, in some embodiments, dies622,624, and628are bonded to dies613,615, and619, respectively, to form a die stack. In some embodiments, dies622,624, and628can be the same type of device, chip, or die as their respective counterpart dies613,615, and619. In some embodiments, one or more of dies622,624, and628can be a different type of device, chip, or die than their respective counterpart dies613,615, and619. Dies622,624, and628can be bonded to dies613,615, and619, respectively, in like manner as dies612,614, and618are bonded to processed wafer511, as described above with respect toFIG. 31, and is not repeated here. In particular, dies622can be hybrid bonded to dies613by a direct bonding of contact pads125of dies622and vias120or contact pads of dies613. Similarly, dies624can be bonded to dies615by a direct bonding of vias542of dies624and vias542of dies615. Likewise, dies628can be bonded to dies619by a direct bonding of vias541of dies628and vias541of dies619. In some embodiments, a fusion boding of insulating materials of each of the bonded dies can also occur.

Referring toFIG. 35, a gap-fill material626is formed over the workpiece to substantially fill the spaces between dies622/624/628. The process and materials is the same as those discussed above in relation toFIG. 32for the formation of gap-fill material616, and is not repeated.

Referring toFIG. 36, in some embodiments, the process of thinning and attaching additional dies ofFIGS. 33-35are repeated until a desired die stack configuration is achieved. In some embodiments, a memory cube653can be formed by a four layer stack of memory dies comprising memory dies613,623,633, and643. In some embodiments, a corresponding thermal chip stack655can be formed by a four layer stack of thermal chips comprising thermal chips615,625,635, and645. In some embodiments, a corresponding thermal chip stack659can be formed by a four layer stack of thermal chips comprising thermal chips619,629,639, and649. In some embodiments, the processed gap-fill material657can include distinguishable layers617,627,637, and647. In some embodiments, the processed gap-fill material657will be continuous throughout the die layers and indistinguishable in a cross-section view. Thermal chip stacks655and659can be referred to as heat dissipating structures.

In some embodiments, the die stack655or659can comprise other types of devices. In some embodiments, additional layers can be included in a like manner as described herein with respect to any of stacks653,655, and659. Although the number of layers over processed wafer is depicted as the four layers621,631,641, and651, it should be understood that more or fewer layers can be included.

In some embodiments, the die stacks, i.e., memory cube653, thermal chip stack655, and thermal chip stack659, may be formed by separate processes and attached to processed wafer511. For example, memory cube653can be built using the processes described above with respect to packages102aor102bofFIG. 1-11 or 12-16. Similar processes can also be used to form thermal chip stacks655and659by substituting the layer-by-layer processes and materials for forming the thermal chip stacks655and659described above into the processes illustrated inFIG. 1-11 or 12-16. In some embodiments, a single layer thermal chip of sufficient height can be used.

FIGS. 62A-62Dillustrate various embodiments for a separately formed thermal chip stack, such as thermal chip stack655or659, which is then attached to processed wafer511. Because the thermal chip stack655and659has no active or passive devices formed therein, the height of the individual layers is not critical.FIG. 62Aillustrates a separately formed thermal chip stack, in accordance with some embodiments, which is substantially similar to the thermal chip stack655or659formed layer by layer, discussed above.FIG. 62Billustrates a separately formed thermal chip stack which has an overall height greater than a desired height, which can be thinned after bonding according to the described thinning process above.FIG. 62Cillustrates a separately formed thermal chip stack comprising two layers of approximately the same height.FIG. 62Dillustrates a separately formed thermal chip stack comprising three layers of varying heights. It should be understood that any number of layers can be used and that these embodiments can be combined in any combination.

Referring toFIG. 37, in some embodiments, a metal mask665can be formed over the workpiece. The metal mask665may be a hard mask and may be referred to as metal hard mask665hereafter. The optional metal hard mask665can be used to further conduct heat from the thermal chip stacks655and659as well as the memory cube653. The metal hard mask665can be formed in multiple layers, such as a first seed layer and one or more subsequent material layers. The seed layer (not shown) can be made of copper (Cu), tungsten (W), gold (Au), silver (Ag), aluminum, (Al), lead (Pb), tin (Sn), alloys of the same, or the like, and may be formed using an electro-plating or electroless plating process, ALD, PVD, sputtering, the like, or a combination thereof. The one or more subsequent material layers can be formed using similar processes and materials as the seed layer.

Referring toFIG. 38, in some embodiments where a metal hard mask665is used, the metal hard mask665can be patterned to form a patterned metal hard mask667. The metal hard mask665can be patterned using any suitable technique, such as, a photolithographic technique. Generally, photolithography techniques involve depositing a photoresist material (not shown), which is subsequently irradiated (exposed) and developed to remove a portion of the photoresist material. The remaining photoresist material can, in some embodiments, be used as a mask to etch exposed materials or, in other embodiments, prevent the formation of other materials thereon. The photoresist can then be removed.

In some embodiments, metal hard mask665can be formed as a patterned metal hard mask667by first forming a blanket seed layer, forming a photoresist material over the seed layer, patterning the photoresist layer, and forming metal materials in the openings of the seed layer by plating, such as electroplating or electroless plating, or the like. Subsequently, the photoresist is removed and the exposed seed layer is stripped using a wet or dry etch.

In some embodiments, such as illustrated inFIG. 38, if a metal hard mask665is used, it is at least patterned to form openings667oto expose the gap-fill material layers657(seeFIG. 36). In addition, openings667ocan be formed over the surrounding material551/552of the top layer645/649of the thermal chip stacks655/659. In some embodiments, openings can also be formed over the substrate115or insulating material140of the top layer643of the memory cube653.

Still referring toFIG. 38, the gap-fill material layers657between each of the stacks653,655, and659are cut down to the surface of the processed wafer511, using a cutting technique670to form openings680(seeFIG. 39). Cutting technique670can include a dry etch, wet etch, anisotropic etch, or plasma etch using a suitable etchant for the gap-fill material. Cutting technique670can include a laser making multiple passes to achieve a desired depth profile. Cutting technique670can include a mechanical process, such as a saw set to cut to a desired depth. A combination of the above described cutting techniques670can also be used. It may be desirable to use a plasma etching technique to achieve a smooth wall profile of the gap-fill material.

Still referring toFIG. 38, the multiple packages formed from the processed wafer511, such as application packages500, are singulated from the workpiece, resulting in a singulated application package501(seeFIG. 39). Singulation671can occur by any acceptable process, including plasma dicing, laser dicing, mechanical saw, or a combination thereof. Singulation occurs through the non-package regions (outside550/560/570ofFIG. 28) on scribe lines or dicing streets of the workpiece. The singulation cuts through the processed wafer511, down to the release layer610. In some embodiments, the singulation can continue through the release layer610and may continue into or through the carrier605.

In embodiments where plasma dicing is performed for the singulation671or etch or plasma etch is performed for the cutting technique670, the patterned metal hard mask667can be used as a plasma dicing/etch mask prior to the formation of openings667o. The openings667ein the patterned mask667can be formed prior to plasma dicing/etch to define the areas to be etched or diced.

In some embodiments, one or more masks675, such as a photoresist, can temporarily be formed over the patterned metal hard mask667and over portions of the gap-fill material layers657to protect them from etching or plasma dicing. The one or more masks675are removed when the cutting and singulation is complete.

An advantage of plasma dicing application dies501is that, with the gap-fill material657, smooth sidewall profiles can be achieved through the plasma dicing. Plasma dicing can be performed using processes and materials such as those described above with respect toFIG. 10, which are not repeated.

Referring toFIG. 39, using the patterned metal hard mask667, in some embodiments an etching672(illustrated by arrows) can be performed to form trenches (681ofFIG. 40) in the surrounding material551/552of the thermal chip stacks655/659. In some embodiments, the substrate115or insulating material140of the top layer643of the memory cube653can also be etched at the same time to form trenches therein. In some embodiments, the etching672can be performed in multiple steps using protective masks (not shown) to protect areas not being etched, so as to form trenches of different depths.

The singulation671and gap-fill cutting670discussed above result in openings680between the die stacks, and modified layers621′,631′,641′, and651′ resulting in layer structure679.

Referring toFIG. 40, the etching672forms trenches681in the top layer651′. Trenches681can be about 1 μm to about 40 μm deep, such as about 5 μm deep, and may traverse all the way through the surrounding material551/552of the top die651′ and into the layers below, such as641′ or631′. Trenches681can aid in heat dissipation by increasing the contact surface area between the thermal chip stacks655/659and a thermal interface material (690ofFIG. 42) and can shorten the distance between the thermal interface material and thermally conductive vias. Likewise, trenches681in the top layer643of the memory cube653can also increase surface area and shorten the distance between thermal interface material690and thermally conductive vias.

Referring toFIG. 41, following the dicing, the carrier605is removed from the package501. Removing the carrier505may include applying UV radiation to release layer610, a mechanical grinding process, an etch back process, a heating process, combinations thereof, or the like.

Connectors685are formed on a front side of the processed wafer511. Connectors685can be formed using any suitable process and comprise various configurations. In some embodiments, the connectors685may be controlled collapse chip connection (C4) bumps, micro-bumps, solder balls, or the like. For example, openings (not shown) can be made in the front side of the processed wafer511, the opening exposing metal features of the processed wafer511. Connectors685are formed in the openings. In some embodiments, an under bump metallurgy (UBM) layer can be formed in the openings prior to the formation of the connectors685. In the illustrated embodiment, the connectors685have lower portions685L comprising a conductive material and upper portions685U comprising a solder material. The lower portions685L and the upper portions685U may be also referred as conductive pillars685L and solder caps685U, respectively.

Connectors685can be coupled to conductive features of the processed wafer511in the logic area550, memory area560, and/or thermal dissipation area570. Such conductive features can include for example an interconnect530(seeFIG. 28), vias, such as via546,525, or535(seeFIG. 30), or other metal traces or lines.

Referring toFIG. 42, a thermal interface material (TIM)690is formed over the application package501. In some embodiments, the TIM690is dispensed over the die stacks653/655/659and on their sides, including sidewalls682of the die stacks, between the die stacks, in openings680, and in trenches681. In some embodiments, the TIM690is dispensed over the die stacks653/655/659, including enough material to be squeezed into openings680and trenches681. The TIM690is a material having a good thermal conductivity, which may be greater than about 5 W/m*K, and may be equal to, or higher than, about 50 W/m*K or 100 W/m*K.

Referring toFIG. 43, the package501can be coupled to a package component691, which may be a package substrate, an interposer, a Printed Circuit Board (PCB), or the like. In some embodiments, package component691includes metal traces and/or vias693(illustrated using dashed lines) that interconnect the electrical connectors (such as metal pads (not shown) and/or solder balls692) on the opposite sides of package component691. Discrete passive devices (not shown) such as resistors, capacitors, transformers, and the like, may also be bonded to package component691. Solder balls692are attached to package component691, wherein application package501and connectors685are on the opposite sides of package component691. The application package501and package component691(and other attached devices) are in combination referred to as package699.

Still referring toFIG. 43, a heat spreader695is mounted. Heat spreader695comprises an upper portion695U and lower portion695L, which may be one total piece or two or more separate pieces. The upper portion695U covers over the whole package699and contacts the lower portion on opposite sides of the package699. In some embodiments, the lower portion695L is only on two opposite sides of the package699at the periphery. In some embodiments, the lower portion695L can completely surround the periphery of the package699. In some embodiments, the lower portion695L can partially surround the periphery of the package699in multiple segments on two or more sides, with at least two of the sides being opposite to each other. In some embodiments, only the upper portion695U is present. In some embodiments, the lower portion695L may extend from the bottom of the upper portion695U, but not all the way to the package component691. In some embodiments, the lower portion695L can be attached by an adhesive694to the package component691.

An adhesive694may have a thermal conductivity lower than the thermal conductivity of TIM690. Adhesive694may have a better adhering ability than TIM690.

In the mounting of the heat spreader695, the heat spreader695is pushed down. As a result, TIM690may be squeezed and pushed into the openings680, and trenches681, and along the sidewalls682(seeFIG. 42) of the stacked dies. The resulting TIM690includes a top portion690A, sidewall portions690B, gap-fill portions690C, and trench-fill portions690D. TIM sidewall portions690B may, or may not, form a ring encircling the application package501. In some embodiments, TIM sidewall portions690B may extend lower than the application die501and may contact the package component691.

Heat spreader695has a high thermal conductivity and may be formed using a metal, a metal alloy, or the like. For example, heat spreader695may comprise a metal, such as Al, Cu, Ni, Co, and the like, or an alloy thereof. Heat spreader695may also be formed of a composite material selected from the group consisting of silicon carbide, aluminum nitride, graphite, and the like.

FIG. 44illustrates a package device in accordance with some embodiments. InFIG. 44, the die stacks653,655, and659are formed separately, and then attached to the processed wafer511. After the die stacks653,655, and659are attached to the processed wafer511, the package device can be formed using processes and materials such as those discussed above with respect toFIGS. 36 through 43. In particular, after the die stacks653,655, and659are attached to the processed wafer511, a gap fill material may be applied over and in between the attached dies, such as discussed above with respect to the gap fill material616ofFIG. 32, for example. The process may then proceed in a manner such as discussed above with respect toFIGS. 37 through 43.

In the illustrated embodiment ofFIG. 44, die stack653is a die stack similar to die stack102aas discussed above with respect toFIG. 24 or 27. In some embodiments, the backside carrier206amay be removed, while in other embodiments the backside carrier206amay be left intact or thinned. Die stack653is attached to processed wafer511using connectors985. Die stacks655and659are attached to the processed wafer511by hybrid bonding, such as discussed above.

FIGS. 45 through 58illustrate various intermediate steps in creating an application package, in accordance with some embodiments.

Referring toFIG. 45, application package500comprises a thinned processed wafer511which can include the features of and be formed using the processes and materials of processed wafer510ofFIG. 28, which is described above and not repeated. Processed wafer510can likewise be bonded to a carrier605(FIG. 29) and thinned (FIG. 30) using processes and materials as described above.

Die612and thermal metal pieces715and719are bonded to processed wafer511. In some embodiments, die612and thermal metal pieces715and719are attached to the processed wafer511using, for example, a pick and place apparatus. In other embodiments, die612and thermal metal pieces715and719may be attached to the processed wafer511manually, or using any other suitable method. Thermal metal pieces715/719can be referred to as heat dissipating structures.

Die612can be a die consistent with die612, as described above with respect toFIG. 31.

Thermal metal pieces715and719can be thermal metal bulk material that has prepared dimensions suitable for the respective footprint of the mounting area over the logic area550and footprint of the mounting area over the thermal dissipation area570of processed wafer511. In some embodiments, the thickness of the thermal metal pieces715and719can be selected to be a desired thickness of the layer (see721ofFIG. 48). For example, the thickness can be selected to be about 20 μm. In some embodiments, the thickness of the thermal metal pieces715and719can be selected to be a thickness greater than the desired thickness of the layer (721ofFIG. 48). The material of thermal metal pieces may comprise a metal, such as Al, Cu, Ni, Co, and the like, or an alloy thereof.

Still referring toFIG. 45, die612can be bonded to processed wafer511using the processes and materials as described above with respect toFIG. 31.

Thermal metal pieces715and719can be bonded to the logic area550and thermal dissipation area570of the processed wafer511. In some embodiments, metal pads710may be formed over the logic area550of the processed wafer. Metal pads710may or may not protrude from a top surface of the processed wafer511. Metal pads710can correspond to the contacts or contact pads545such as described above with respect toFIG. 30and may couple to one or more vias546in the logic area550of the processed wafer511. In some embodiments, metal pads711can be formed over the thermal dissipation area570of the processed wafer511and coupled to the vias535. In some embodiments, metal pads711may protrude from a top surface of the processed wafer511. Metal pads711can be formed, for example, using processes and materials such as described above with respect toFIG. 1andFIG. 18, for forming contacts and is not repeated.

In some embodiments, thermal metal pieces715and719can be hybrid bonded to processed wafer511by aligning and directly bonding the metal surfaces of the thermal metal pieces715and719to the processed wafer511. It should be understood that the bonding of the vias and contacts illustrated inFIG. 45are merely an example, and other configurations of hybrid bonded elements are contemplated. Hybrid bonding can be carried out using processes and materials as described above with respect toFIG. 17, which are not repeated, including any combination of hybrid bonding of vias and contacts. For example, the bonding surface of the thermal metal pieces715and719can be considered as a large contact for the purposes of hybrid bonding which can be bonded to other contacts, such as metal pads710or711or bonded to vias, such as vias535or546(seeFIG. 30). As with the die612, no underfill is needed between the metal pieces715/719and the processed wafer511.

In some embodiments, metal piece715is bonded to vias546or metal pads710and metal piece719is bonded to vias535or metal pads711by forming a eutectic-type connector or conductive pillar at the bond points between the metal pieces715/719and the processed wafer511, bringing the metal pieces715/719together with the processed wafer511after aligning the corresponding contacts, and reflowing the eutectic materials to form a physical and electrical coupling. The eutectic-type connector or conductive pillar can be formed on either side or on both sides of the bond point, i.e. on the metal pieces715/719and/or on the processed wafer511. In such embodiments, an underfill material can be used between the die612and processed wafer511and between the metal pieces715/719and the processed wafer511, or alternatively a gap-fill material, such as described below, can provide underfill capabilities.

Referring toFIG. 46, a gap-fill material616is formed over the workpiece to substantially fill the spaces between the die612and thermal metal pieces715and719. The processes and materials can be the same as described above with respect to the gap-fill material ofFIG. 32and are not repeated.

Referring toFIG. 47, the gap-fill material616and die612can be thinned to create gap-fill material617and thinned die613. Thinning can be done by a CMP process, grinding, etching, or other suitable process. Thinning exposes vias120in die613and also reduces the thickness of die613to provide better heat dissipation and take less space. In some embodiments, where the thermal metal pieces715/719are thicker than the desired thickness, the thermal metal pieces715/719are also thinned. For example, the thermal metal pieces715/719may be thicker than a desired thickness, but thinner than die612. After thinning, the layer721comprising thinned die613, thermal metal pieces715/719, and thinned gap-fill material617can be about 10 to 50 μm thick, for example, about 20 μm thick. In some embodiments, a top surface of the gap-fill material617and top surfaces of the die613and thermal metal pieces715/719are substantially co-planar within process variations.

Referring toFIG. 48, in some embodiments, die622and thermal metal pieces725and729are bonded to die613and thermal metal pieces715and719, respectively, to form a die stack and thermal metal bulk. In some embodiments, die622can be the same type of device, chip, or die as613. In some embodiments, die622can be a different type of device, chip, or die than die613. Die622can be bonded to die613and metal pieces625/629can be respectively bonded to metal pieces615/619, in like manner as dies612,614, and618are bonded to processed wafer511, as described above with respect toFIG. 45, and is not repeated here. In particular, die622can be hybrid bonded to die613by a direct bonding of contact pads125of die622and vias120or contact of dies613. Similarly, thermal metal piece725can be bonded thermal metal piece715by a direct bonding of their respective surfaces. Likewise, thermal metal piece729can be bonded thermal metal piece719by a direct bonding of their respective surfaces. In some embodiments, a fusion boding of insulating materials of the dies613and622can also occur. The direct bonding of the metal pieces can result in a substantially bonded interface across the entire interface between the thermal metal pieces715and725and the thermal metal pieces719and729.

Referring toFIG. 49, a gap-fill material626is formed over the workpiece to substantially fill the spaces between dies622and thermal metal pieces725and729. The process and materials is the same as those discussed above in relation toFIG. 46for the formation of gap-fill material616, and is not repeated.

Referring toFIG. 50, in some embodiments, the process of thinning and attaching additional dies and thermal metal pieces ofFIGS. 47-49are repeated until a desired die stack configuration and thermal metal configuration is achieved. In some embodiments, a memory cube653can be formed by a four layer die stack of memory dies comprising memory dies613,623,633, and643. In some embodiments, a corresponding thermal metal bulk755can be formed by a four layer stack of thermal metal pieces comprising metal pieces715,725,735, and745. In some embodiments, a corresponding thermal metal bulk759can be formed by a four layer die stack of thermal metal pieces comprising thermal metal pieces719,729,739, and749. In some embodiments, the processed gap-fill material657can include distinguishable layers617,627,637, and647. In some embodiments, the processed gap-fill material657will be continuous throughout the die layers and indistinguishable in a cross-section view. Thermal metal bulk755/759can be referred to as heat dissipating structures.

In some embodiments, each of the stacks, i.e., memory cube653, thermal metal bulk755, and thermal metal bulk759, may be formed by separate processes and attached to processed wafer511. For example, memory cube653can be built using the processes described above with respect toFIG. 1-11 or 12-16. Similar processes can also be used to form thermal metal bulk755or759by substituting the layer-by-layer processes and materials for forming the thermal metal bulk described above into the processes illustrated inFIG. 1-11 or 12-16. Alternatively, a single layer thermal metal bulk can be used.

FIGS. 63A-63Dillustrate various alternative embodiments for a separately formed thermal metal bulk755and759, which is then attached to processed wafer511. Because the thermal metal bulk755and759has no active or passive devices formed therein, the height of the individual layers is not critical.FIG. 63Aillustrates a separately formed thermal metal bulk, in accordance with some embodiments, which is substantially similar to the thermal metal bulk755and759formed layer by layer, discussed above.FIG. 63Billustrates a separately formed thermal metal bulk which has an overall height greater than a desired height, which can be thinned after bonding.FIG. 63Cillustrates a separately formed thermal metal bulk comprising two layers of approximately the same height.FIG. 63Dillustrates a separately formed thermal metal bulk comprising three layers of varying heights. It should be understood that any number of layers can be used and that these embodiments can be combined in any combination.

Referring toFIG. 51, in some embodiments, rather than apply the gap-fill material layer-by-layer, the gap-fill material754can be formed over the workpiece after all the dies613,623,633,643have been processed (attached and thinned) and after both the thermal metal bulk755and759have been formed. The gap-fill material754can be formed over the entire workpiece and thinned such that a top surface of the gap-fill material is substantially co-planar with a top surface of the die stack653and top surfaces of the thermal metal bulk755and759, within process variations. In such embodiments, the gap-fill material754will not have distinguishable layers, but will be continuous.

Referring toFIG. 52, a metal mask665is formed over the workpiece, in accordance with some embodiments. The metal mask665may be formed using processes and materials such as those described above with respect toFIG. 37, which are not repeated.

Referring toFIG. 53, the metal mask665can be patterned using processes and materials such as those described above with respect toFIG. 38, which are not repeated.

Still referring toFIG. 53, the gap-fill material657/754between the die stacks653and thermal metal bulk755and759are cut down to the surface of the processed wafer511, using a cutting technique670to form openings680(seeFIG. 54). Cutting technique670can be the same as the cutting technique670as described above with respect toFIG. 38and is not repeated.

Still referring toFIG. 53, the multiple die packages formed from the processed wafer511, such as application package500, are singulated from the workpiece, resulting in a singulated application package501(seeFIG. 54). Singulation671can be the same as the singulation technique671as described above with respect toFIG. 38and is not repeated.

Referring toFIG. 54, the singulation671and gap-fill cutting670discussed above result in openings680between the die stack653and thermal metal bulk655and659, and result in modified layers721′,731′,741′, and751′ of layer structure779.

Referring toFIG. 55, following the singulation, the carrier505is removed from the application package501. Removing the carrier505may include applying UV radiation to release layer610, a mechanical grinding process, an etch back process, a heating process, combinations thereof, or the like.

Connectors685are formed on a front side of the processed wafer511of application package501using processes and materials such as those discussed above with respect toFIG. 41, which are not repeated.

Referring toFIG. 56, a TIM690is formed over the application package501, in like manner as discussed above with respect toFIG. 42, except instead of thermal chips655and659, thermal metal bulk755and759are used.

Referring toFIG. 57, the application package501can be coupled to a package component691, using processes and materials such as those discussed above with respect toFIG. 43, which are not repeated.

Still referring toFIG. 57, a heat spreader695can be mounted using processes and materials such as those discussed above with respect toFIG. 43, which are not repeated.

FIG. 58illustrates a package device in accordance with some embodiments. InFIG. 58, the die stack653and thermal metal bulk755and759are formed separately, and then attached to the processed wafer511. After the die stack653and thermal metal bulk755and759are attached to the processed wafer511, the package device can be formed using processes and materials such as those discussed above with respect toFIGS. 50 through 57. In particular, after the die stacks653,755, and759are attached to the processed wafer511, a gap fill material may be applied over and in between the attached dies, such as discussed above with respect to the gap fill material754ofFIG. 51, for example. The process may then proceed in a manner such as discussed above with respect toFIGS. 51 through 57.

In the illustrated embodiment ofFIG. 58, die stack653is a die stack similar to die stack102aas discussed above with respect toFIG. 24 or 27. In some embodiments, the backside carrier206amay be removed, while in other embodiments the backside carrier206amay be left intact or thinned. Die stack653is attached to processed wafer511using connectors985. Thermal metal bulk755and759are attached to the processed wafer511by hybrid bonding, such as discussed above.

FIGS. 59-61illustrate heat paths for dissipating heat generated in the processed wafer511and die stack653.FIG. 59corresponds to embodiments consistent withFIG. 43. Heat can be dissipated through the thermally conductive vias.FIG. 60corresponds to embodiments consistent withFIG. 57. Heat can be dissipated through the thermally conductive vias and thermal metal bulk.FIG. 61corresponds to an alternative embodiment similar toFIG. 57, except that thermally conductive vias are not provided in the die stack653. As a result, thermal dissipation is performed through the adjacent thermal metal bulk755/759.

Embodiments dissipate heat from a stacked die package. Embodiments include wafer on wafer, chip on wafer, and chip on chip hybrid bonding for high thermal conduction without an intermediate connection material. Embodiments include the ability to have different sizes or types of chips attached to each other through hybrid bonding. Embodiments include plasma dicing and plasma etching gap-fill material for smooth sidewalls between dies and between package components. In some embodiments, a memory cube is formed by multiple memory dies in a stacked configuration, in a chip on chip, chip on wafer, or wafer on wafer configuration. In some embodiments, a stacked package is formed on a wafer level device, such as an processing unit wafer used in a System-in-Package configuration. A memory cube can be deposited thereon, as a single package or layer by layer. Thermal chips or bulk thermal metal can be formed next two the memory cube for heat dissipation. A heat spreader can be attached to the device through a thermal interface material. Some embodiments use thermal vias that are directly bonded in a hybrid bonding technique. This technique provides bonding without the use of underfill or interlayer molding compounds, which can inhibit thermal dissipation. Some embodiments have a metal hard mask can be used to connect the thermal TSVs to a thermal interface material. Some embodiments have trenches in the heat dissipation features to increase the interface surface area contact.

One embodiment is a method that includes bonding a first surface of a plurality of first dies to a wafer, where each one of the plurality of first dies is in a respective package area of the wafer. A first gap-filling material is deposited over the plurality of first dies. The plurality of first dies and first gap-filling material are thinned, thereby exposing conductive through vias at a second surface of the plurality of first dies. A second die of a plurality of second dies is bonded to each one of the plurality of first dies and a second gap-filling material is deposited over the plurality of second dies. The plurality of second dies and second gap-filling material are thinned, thereby exposing conductive through vias at a second surface of the plurality of second dies. The method includes singulating the first and second gap-filling material, the singulating producing a die stack that includes a first die of the plurality of first dies and a second die of the plurality of second dies.

Another embodiment is a die stack structure that includes a first device, a second device, and a third device. The first device includes a semiconductor substrate, where the semiconductor substrate has a metal feature disposed at a surface thereof and includes active elements. The second device includes a substrate and plurality of conductive vias traversing through an entire thickness of the substrate. The plurality of conductive vias are disposed in the substrate aligned to an adjacent plurality of conductive vias of the first device at a first surface of the second device. A first conductive via of the plurality of conductive vias is bonded to the metal feature of the first device. The third device includes a metal feature disposed at a surface of the third device, where the metal feature of the third device is bonded to the first conductive via. The dies stack structure also includes a gap-fill material disposed on sidewalls of the second device and the third device.

Another embodiment is a package structure that includes a substrate, where the substrate includes a logic area, a memory area, a first surface having connectors formed thereon, and a second surface opposite the first surface. The package structure includes a logic device formed in the substrate in the logic area and a memory die stack attached to the second surface of the substrate in the memory area. The package structure also includes a first heat dissipating structure attached to the second surface of the substrate in the logic area and a thermal interface material disposed over the memory die stack and first heat dissipating structure. A heat spreader is disposed over and in contact with the thermal interface material.