Package systems having interposers

A package system includes an integrated circuit disposed over an interposer. The interposer includes a first interconnect structure. A first substrate is disposed over the first interconnect structure. The first substrate includes at least one first through silicon via (TSV) structure therein. A molding compound material is disposed over the first interconnect structure and around the first substrate. The integrated circuit is electrically coupled with the at least one first TSV structure.

RELATED APPLICATIONS

The present application is related to U.S. patent application Ser. No. 12/781,960, entitled “PACKAGE SYSTEMS HAVING INTERPOSERS,” filed on May 18, 2010, which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates generally to the field of semiconductor package systems, and more particularly, to package systems having interposers.

BACKGROUND OF THE DISCLOSURE

Since the invention of integrated circuits, the semiconductor industry has experienced continual rapid growth due to continuous improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, allowing for the integration of more components into a given area.

These integration improvements are essentially two-dimensional (2D) in nature, in that the volume occupied by the integrated components is essentially on the surface of the semiconductor wafer. Although dramatic improvements in lithography have resulted in considerable improvements in 2D integrated circuit formation, there are physical limits to the density that can be achieved in two dimensions. One of these limits is the minimum size needed to make these components. Also, when more devices are put into one chip, more complex designs are required.

An additional limitation comes from the significant increase in the number and length of interconnections between devices as the number of devices increases. When the number and length of interconnections increase, both circuit resistance-capacitance (RC) delay and power consumption increase.

Three-dimensional integrated circuits (3D IC) are therefore created to resolve the above-discussed limitations. In a conventional formation process of 3D IC, two wafers, each including an integrated circuit, are formed. The wafers are then bonded with the devices aligned. Deep vias are then formed to interconnect devices on the first and second wafers.

Much higher device density has been achieved using 3D IC technology, and up to six layers of wafers have been bonded. As a result, the total wire length is significantly reduced. The number of vias is also reduced. Accordingly, 3D IC technology has the potential of being the mainstream technology of the next generation.

Conventional methods for forming 3D IC also include die-to-wafer bonding, wherein separate dies are bonded to a common wafer. An advantageous feature of the die-to-wafer bonding is that the size of the dies may be smaller than the size of chips on the wafer.

Recently, through-silicon-vias (TSVs), also referred to as through-wafer vias, are increasingly used as a way of implementing 3D IC. Conventionally, a bottom wafer is bonded to a top wafer. Both wafers include integrated circuits over substrates. The integrated circuits in the bottom wafer are connected to the integrated circuits in the wafer through interconnect structures. The integrated circuits in the wafers are further connected to external pads through through-silicon-vias. The stacked wafers can be subjected to a sawing process to provide a plurality of stacked die structures.

DETAILED DESCRIPTION OF THE DISCLOSURE

A package system has a silicon die directly disposed on an organic substrate that is disposed on a motherboard. The organic substrate serves as an intermediate apparatus to fan out the metal pitch of the silicon die to the metal pitch of the motherboard. It is found that a coefficient of thermal expansion (CTE) mismatch exists between the silicon die and the organic substrate. The CTE mismatch may result in an intermetal dielectric (IMD) layer delamination of the silicon die and/or a bump failure during an assembly process and/or a reliability test.

To solve the problem, a silicon interposer is disposed between the silicon die and the organic substrate, serving as another transition apparatus. The use of the silicon interposer increases the cost of manufacturing the package system. It is also found that the height of the package system with the silicon interposer is increased, too.

Based on the foregoing, package systems for integrated circuits are desired.

Embodiments of the present application relate to package systems having various interposers. The interposers can each have a molding compound material disposed around side edges of a substrate. The molding compound material can provide a surface area such that a fine metallic line pitch of an interconnect structure disposed on a surface of the substrate can be fanned out to a large metallic line pitch of an interconnect structure disposed on an opposite surface of the substrate. By using the interposer, the organic substrate used in the conventional package system can be saved.

FIG. 1is a schematic cross-sectional view of a first exemplary package system. InFIG. 1, a package system can include at least one integrated circuit, e.g., integrated circuits120and130, disposed over an interposer110. The integrated circuits120and130can be electrically coupled with the interposer110.

The interposer110can include an interconnect structure111. A substrate113can be disposed over the interconnect structure111. The substrate113can include at least one through silicon via (TSV) structures, e.g., TSV structures115aand115b, therein. A molding compound material117can be disposed over the interconnect structure111and around the substrate113. In some embodiments, the interposer110can include at least one passive device, e.g., capacitor, resistor, and/or inductor. In other embodiments, the interposer110can be substantially free from including any active device, e.g., metal-oxide-semiconductor (MOS) transistors, bipolar junction transistors (BJTs), complementary MOS (CMOS) transistors, etc.

In some embodiments, the interconnect structure111can include at least one dielectric layer and at least one electrical connection structure. In some embodiments, the interconnect structure111can include multiple dielectric layers and multiple layers of electrical connection structures. Each layer of the electrical connection structures can be sandwiched by the dielectric layers. In some embodiments, the dielectric layers and the conductive structures can be configured to form various passive devices, e.g., capacitors, resistors, and/or inductors.

In some embodiments, the dielectric layer (not labeled) may include at least one material, such as silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low-k) dielectric material, ultra low-k dielectric material, another dielectric material, or any combinations thereof. The electrical connection structures can include at least one structure, such as via plugs, contact plugs, damascene structures, dual damascene structures, metallic regions, metallic lines, or any combinations thereof. The via plugs, contact plugs, damascene structures, dual damascene structures, metallic regions, and metallic lines (not labeled) can be made of at least one material, such as tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, other proper conductive materials, and/or combinations thereof. In some embodiments, the interconnect structure111can have a dimension “D1” in the cross-sectional view shown inFIG. 1. The metallic lines of the interconnect structure111has a pitch width.

In some embodiments, the interconnect structure111can include at least one pad (not labeled) that can be disposed on a surface of the interconnect structure111. At least one connector, e.g., bumps135, can each be disposed over its corresponding pad for electrical connection with one or more substrates (not shown). The at least one pad may be made of at least one material, such as copper (Cu), aluminum (Al), aluminum copper (AlCu), aluminum silicon copper (AlSiCu), or other conductive material or various combinations thereof. In some embodiments, the at least one pad may include an under bump metallization (UBM) layer.

In some embodiments, the bumps135can include at least one material, such as a lead-free alloy (e.g., gold (Au), a tin/silver/copper (Sn/Ag/Cu) alloy, or other lead-free alloys), a lead-containing alloy (e.g., a lead/tin (Pb/Sn) alloy), copper, aluminum, aluminum copper, conductive polymer, other bump metal materials, or any combinations thereof.

As noted, the substrate113can be disposed over the interconnect structure111. The substrate113can be made of an elementary semiconductor including silicon or germanium in crystal, polycrystalline, or an amorphous structure; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable material; or combinations thereof. In one embodiment, the alloy semiconductor substrate may have a gradient SiGe feature in which the Si and Ge composition change from one ratio at one location to another ratio at another location of the gradient SiGe feature. In another embodiment, the alloy SiGe is formed over a silicon substrate. In another embodiment, a SiGe substrate is strained. Furthermore, the semiconductor substrate may be a semiconductor on insulator, such as a silicon on insulator (SOI). In some examples, the semiconductor substrate may include a doped epi layer or a buried layer. In other examples, the compound semiconductor substrate may have a multilayer structure, or the substrate may include a multilayer compound semiconductor structure.

The TSV structures115aand115bcan be disposed in the substrate113. The TSV structures115aand115bcan be electrically coupled with the integrated circuits120and130through connectors, e.g., bumps125aand125b, respectively. In some embodiments, the TSV structures115aand115bcan be made of at least one material, such as a barrier material (e.g., titanium, titanium-nitride, tantalum, tantalum-nitride, other barrier material, and/or any combinations thereof), conductive material (aluminum, copper, aluminum-copper, polysilicon, other conductive material, and/or any combinations thereof), other materials that are suitable for forming the TSV structures115aand115b, and/or combinations thereof.

Referring toFIG. 1, the molding compound material117can be disposed around the substrate113. In some embodiments, the molding compound material117can be made of at least one material, such as a polymer-based material. The term “polymer” can represent thermosetting polymers, thermoplastic polymers, or any mixtures thereof. The polymer-based material can include, for example, plastic materials, epoxy resin, polyimide, PET (polyethylene terephthalate), PVC (polyvinyl chloride), PMMA (polymethylmethacrylate), polymer components doped with specific fillers including fiber, clay, ceramic, and inorganic particles, or any combinations thereof. In other embodiments, the molding compound material117can be made of epoxy resin, such as epoxy cresol novolac (ECN), biphenyl epoxy resin, multifunctional liquid epoxy resin, or any combinations thereof. In still other embodiments, the molding compound material117can be made of epoxy resin optionally including one or more fillers to provide the composition with any of a variety of desirable properties. Examples of fillers can be aluminum, titanium dioxide, carbon black, calcium carbonate, kaolin clay, mica, silica, talc, wood flour, or any combinations thereof.

In some embodiments, the interposer110can include another interconnect structure119disposed over the substrate113. The TSV structures115aand115bcan be electrically coupled with the integrated circuits120and130through the interconnect structure119and the bumps125aand125b. The interconnect structure119can include at least one dielectric layer, via plugs, contact plugs, damascene structures, dual damascene structures, metallic regions, metallic lines, passivation materials, other semiconductor materials, or any combinations thereof. In some embodiments, the dielectric layer and the conductive structures can be configured to form various passive devices, e.g., capacitors, resistors, and/or inductors.

The dielectric layer (not labeled) may include at least one material, such as silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric material, ultra low-k dielectric material, other dielectric materials, or any combinations thereof. The via plugs, contact plugs, damascene structures, dual damascene structures, metallic regions, and metallic lines (not labeled) can be made of at least one material, such as tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, other proper conductive materials, and/or combinations thereof.

In some embodiments, the bumps125aand125bcan be made of at least one material, such as a lead-free alloy (such as gold (Au) or a tin/silver/copper (Sn/Ag/Cu) alloy), a lead-containing alloy (such as a lead/tin (Pb/Sn) alloy), copper, aluminum, aluminum copper, conductive polymer, other bump metal materials, and/or combinations thereof.

In some embodiments, the interconnect structure119can have a dimension “D2” in the cross-sectional view shown inFIG. 1. The dimension “D2” of the interconnect structure119is smaller than the dimension “D1” of the interconnect structure111. In other embodiments, the metallic lines of the interconnect structure119has a pitch width. The metallic line pitch of the interconnect structure119can be smaller than the metallic line pitch of the interconnect structure111. In an embodiment, the surface117aof the molding compound material117can be substantially level with the surface119aof the interconnect structure119. In other embodiments, the surface117aof the molding compound material117can be lower or higher than the surface119aof the interconnect structure119.

In some embodiments, the interconnect structure119can include at least one pad (not labeled) that can be disposed on a surface of the interconnect structure119. The bumps125aand125bcan each be disposed over its corresponding pad. In some embodiments, the pitch of the bumps125aand125bcan be smaller than the pitch of the bumps135. The at least one pad may comprise at least one material such as copper (Cu), aluminum (Al), aluminum copper (AlCu), aluminum silicon copper (AlSiCu), or other conductive material or various combinations thereof. In some embodiments, the at least pad may include an under bump metallization (UBM) layer.

Referring again toFIG. 1, at least one integrated circuit, e.g., the integrated circuits120and130, can be disposed over the interposer110. The integrated circuits120and130can include substrates121and131, respectively. The substrates121and131can each be similar to the substrate113described above. In some embodiments, each coefficient of thermal expansion (CTE) of the substrates121and131can be substantially equal to the CTE of the substrate113. The phrase “each coefficient of thermal expansion (CTE) of the substrates121and131can be substantially equal to the CTE of the substrate113” can represent that the CTE mismatch between the substrates does not result in a low-k intermetal dielectric (IMD) layer delamination of the integrated circuits120and130and/or a bump failure of the bumps125aand125bduring an assembly process and/or a reliability test. Though merely showing two integrated circuits disposed over the interposer110, the scope of this application is not limited thereto. In some embodiments, a single integrated circuit or more than two integrated circuits can be horizontally separated and/or vertically stacked over the interposer110.

InFIG. 1, the integrated circuits120and130can each include an interconnect structure (not labeled) disposed between the substrates121,131and bumps125a,125b, respectively. The integrated circuits120and130can each include various active devices. In some embodiments, the interconnect structures of the integrated circuits120and130can each be similar to the interconnect structure111or119described above. In some embodiments, the metallic lines of the interconnect structures of the integrated circuits120and130can have a pitch width. The metallic line pitch of the integrated circuits120and130can be smaller than the metallic line pitch of the interconnect structure119. In other embodiments, the metallic line pitch of at least one of the integrated circuits120and130can be substantially equal to the metallic line pitch of the interconnect structure119.

In some embodiments, the interconnect structures of the integrated circuits120and130can each include at least one pad (not labeled) that can be disposed on a surface of the interconnect structure. The bumps125aand125bcan each be electrically coupled with its corresponding pad. The at least one pad may comprise at least one material such as copper (Cu), aluminum (Al), aluminum copper (AlCu), aluminum silicon copper (AlSiCu), or other conductive material or various combinations thereof. In some embodiments, the at least pad may include an under bump metallization (UBM) layer.

As noted, the interposer110can have a fine metallic line pitch on the interconnect structure119and a large metallic line pitch on the interconnect structure111. The interposer110can fan out the pitch of the bumps125aand125bto the pitch of the bumps135through the interconnect structure119, the TSV structures115a,115b, and the interconnect structure111. Since the interconnect structure111has a larger dimension “D1” than the dimension “D2” of the interconnect structure119, the interconnect structure111can have more bumps135and accommodate more pin counts thereon.

It is also noted that since each CTE of the substrates121and131is substantially equal to the CTE of the substrate113, the CTE mismatch among the substrates121,131, and113can be reduced. In some embodiments, the package system100can be free from including any organic substrate that acts as an intermediate transformer between a motherboard and a die of a conventional package system. The cost of using the conventional organic substrate can be thus reduced. The concern resulting from the organic substrate and the substrate of the die can also be eliminated.

FIG. 2is a schematic cross-sectional view of a second exemplary package system. Items ofFIG. 2that are the same or similar items inFIG. 1are indicated by the same reference numerals, increased by 100. InFIG. 2, a package system200can include a molding compound layer218disposed between an interconnect structure211and a substrate213. TSV structures215aand215bare disposed through the molding compound layer218for electrically coupling the interconnect structure211.

Though divided by the TSV structures215aand215bas shown in the cross-sectional view ofFIG. 2, in some embodiments, the molding compound layer218can continuously extend from the left molding compound material217to the right molding compound material217in a top view of the package system200. The molding compound layer218can be made of at least one material that is the same or similar to the molding compound material117described above in conjunction withFIG. 1.

FIG. 3is a schematic cross-sectional view of a third exemplary package system. Items ofFIG. 3that are the same or similar items inFIG. 1are indicated by the same reference numerals, increased by 200. InFIG. 3, a portion of an interconnect structure319can extend over at least a portion of a molding compound material317. The molding compound material317can include at least one TSV structure, e.g., TSV structures315c, therein. The TSV structures315ccan be made of at least one material that is the same or similar to that of the TSV structures115aand115bdescribed above in conjunction withFIG. 1. The interconnect structure319can be at least partially electrically coupled with an interconnect structure311through the TSV structures315c.

By extending the interconnect structure319at least partially over the molding compound material317, the dimension and/or area of the interconnect structure319can be increased. The interconnect structure319can accommodate larger and/or more integrated circuits thereover. The package capacity of the package system300can thus be increased. In some embodiments, the molding compound layer218(shown inFIG. 2) can be disposed between the interconnect structure311and the substrate313.

FIG. 4is a schematic cross-sectional view of a fourth exemplary package system. Items ofFIG. 4that are the same or similar items inFIG. 2are indicated by the same reference numerals, increased by 200, respectively. InFIG. 4, another interposer440can be disposed between an interposer410and an integrated circuit420.

In some embodiments, the interposer440can include a substrate441that is disposed between interconnect structures (not labeled). The interconnect structures of the interposer440can have the same or similar dimensions. In other embodiments, the interposer440can have the same or similar structure of the interposer110described above in conjunction withFIG. 1.

In some embodiments, the substrate441can include at least one TSV structure (not labeled). Connectors, e.g., bumps445, can be electrically coupled with bumps425athrough the interposer440. The substrate441, the interconnect structures, and the TSV structures can be made of the same or similar materials of the substrate113, the interconnect structure119, and the TSV structures115a,115b, respectively, described above in conjunction withFIG. 1.

By disposing the interposer440between the interposer410and the integrated circuit420, the pitch of the bumps445can be fanned out to the pitch of the pumps435through the interposers440and410. The CTE mismatch of the integrated circuit420and the interposer410may be further reduced. In some embodiments, the interconnect structure419can extend at least partially over the molding compound material417as shown inFIG. 3. The molding compound material417can include TSV structures315cshown inFIG. 3.

FIG. 5is a schematic cross-sectional view of a fifth exemplary package system. Items ofFIG. 5that are the same or similar items inFIG. 4are indicated by the same reference numerals, increased by 100. InFIG. 5, an interconnect structure550can be disposed between a substrate513and an interconnect structure511. In some embodiments, the interconnect structure550can be made of the same or similar material of the interconnect structure519. In other embodiments, the metallic line pitch of the interconnect structure550can be substantially equal to the metallic line pitch of the interconnect structure519. The metallic line pitch of the interconnect structure550is then fanned out to the metallic line pitch of an interconnect structure511. In still other embodiments, the metallic line pitch of the interconnect structure550is larger than the metallic line pitch of the interconnect structure519and is smaller than the metallic line pitch of the interconnect structure511.

In some embodiments, the interconnect structure519can extend at least partially over the molding compound material517in the manner as interconnect structure319shown inFIG. 3. The molding compound material517can include TSV structures315cshown inFIG. 3. In other embodiments, the interconnect structure550can also extend such that edges of the interconnect structure550adjacent the molding compound material517can be substantially aligned with edges of the interconnect structure519.

FIGS. 6A-6Eare schematic cross-sectional views illustrating an exemplary method of forming a plurality of interposers. Items ofFIGS. 6A-6Ethat are the same or similar items inFIG. 1are indicated by the same reference numerals, increased by 500. InFIG. 6A, a method of forming a plurality of interposers can include disposing a plurality of substrates613over a carrier650, e.g., a glass substrate. The substrates613are separated from each other by spaces660. In some embodiments, the substrates613can be attached on an adhesive layer655that is disposed over the carrier650. The adhesive layer655can include a material such as a thermosetting resin to facilitate connection between the carrier650and the substrates613.

In some embodiments, each substrate613can include a plurality of TSV structures (not labeled). In other embodiments, a plurality of interconnect structures619can each be disposed between the corresponding substrate613and the carrier650. The interconnect structures619and the TSV structures can be formed before being disposed over the carrier650. In some embodiments, the interconnect structures619and the TSV structures can be made by at least one of deposition processes, photolithographic processes, etch processes, chemical-mechanical polish (CMP) processes, cleaning process, other semiconductor processes, or any combinations thereof.

Referring toFIG. 6B, a molding compound material617can be formed in the spaces660. In some embodiments, the molding compound material617is formed such that the surface (not labeled) of the molding compound material617can be substantially level with the surfaces of the substrate617. In other embodiments, the molding compound material617can be formed, covering the substrates613.

In some embodiments, a liquid or viscous molding compound can be applied in the spaces660and over the substrates617by any applicable equipment or methods. The portion of the liquid or viscous molding compound that is over the substrates617can be removed so as to form the molding compound material617in the spaces660. In still other embodiments, after removing the portion of the molding compound, the liquid or viscous molding compound can be cured and/or hardened by any applicable thermal curing technique.

Referring toFIG. 6C, a plurality of interconnect structures611and bumps635can be formed over the substrates613. Each of the interconnect structures611can be formed over the corresponding substrate613. The bumps635can be electrically coupled with the TSV structures of the substrates613through the interconnect structures611. The interconnect structures611can be formed, for example, by at least one of deposition processes, photolithographic processes, etch processes, chemical-mechanical polish (CMP) processes, cleaning process, other known semiconductor processes, or any combinations thereof.

In some embodiments, a plurality of pads (not labeled) can be formed between the interconnect structures611and the bumps635. In other embodiments, the pads can be optionally subjected to an electroless nickel immersion gold (ENIG) process or an immersion tin (Im-Sn) process for forming ENIG or Im-Sn material on the exposed surfaces of the pads. The ENIG or Im-Sn material can serve as a bonding interface between the pads and the bumps635.

Referring toFIG. 6D, the carrier650(shown inFIG. 6C) can be removed from the substrates613. In some embodiments, removing the carrier650can include removing the adhesive layer655that is disposed between the substrates613and the carrier650. Removing the adhesive layer655can include a thermal process, a wet etch process, a dry etch process, other applicable processes for removing the adhesive layer655, or any combinations thereof.

Referring toFIG. 6E, the structure shown inFIG. 6Dcan be subjected to a dicing process for dividing interposers610. In some embodiments, the dicing process can include a blade sawing process and/or a laser sawing process. The dicing process can be performed along portions of the molding compound material617that is disposed in the spaces660(shown inFIG. 6A). After the dicing process, the molding compound material617can be formed and disposed around each of the substrates613.

In some embodiments, at least one integrated circuit (not shown) can be disposed over each interposer610to form any package system described above in conjunction withFIGS. 1-5. It is noted that the number of the interposers610formed by the method described above in conjunction withFIGS. 6A-6Eare merely exemplary. In some embodiments, more interposers610can be formed. It is also noted that the method described above in conjunction withFIGS. 6A-6Ecan be modified to achieve the interposers210-510described above in conjunction withFIGS. 2-5, respectively.

FIG. 7is a schematic drawing illustrating a system including an exemplary package system disposed over a substrate board. InFIG. 7, a system700can include a package system702disposed over a substrate board701. The substrate board701can include a printed circuit board (PCB), a printed wiring board and/or other carrier that is capable of carrying a package system. The package system702can be similar to one of the package system100-500described above in conjunction withFIGS. 1-5, respectively. The package system702can be electrically coupled with the substrate board701. In some embodiments, the package system702can be electrically and/or thermally coupled with the substrate board701through bumps705. The system700can be part of an electronic system such as displays, panels, lighting systems, auto vehicles, entertainment devices, or the like. In some embodiments, the system700including the package system702can provides an entire system in one IC, so-called system on a chip (SOC) or system on integrated circuit (SOIC) devices.