Phase shifting in DLL/PLL

The disclosure relates to phase shifting in Delay Locked Loops (DLLs) and Phase-Locked Loops (PLLs). A charge pump in the DLL or PLL includes a capacitor connected in parallel to an output node. A primary current switching circuit charges the capacitor with a source current and discharges the capacitor with a sink current. A supplemental source circuit sources a positive phase shift producing current which has a range of magnitudes. A magnitude of the positive phase shift producing current is determined by at least one source selection signal. A supplemental sink circuit for sources a negative phase shift producing current which has a range of magnitudes. A magnitude of the negative phase shift producing current is determined by at least one sink selection signal.

FIELD OF THE INVENTION

The present invention relates generally to charge pump circuits.

BACKGROUND OF THE DISCLOSURE

As will be appreciated by those skilled in the art, a charge pump can be characterized as a circuit that uses capacitors to create either a higher or lower voltage. Charge pumps are used in a variety of different applications such as, for example, applications involving Delay Locked Loops (DLLs) and Phase-Locked Loops (PLLs).

With respect to PLLs, a charge pump can be used to provide a control voltage applied to a Voltage Controlled Oscillator (VCO). Typically, a PLL includes a phase detector, a loop filter coupled to the output of the charge pump, an amplifier, and a VCO interconnected in a known manner to form a feedback system. The charge pump converts logic level pulses generated by the phase detector into current pulses which are fed to the loop filter. The loop filter integrates the current pulses to produce a control voltage for the VCO.

With respect to DLLs, a charge pump can be used to provide a control voltage for a Voltage Control Delay Line (VCDL) of the DLL. As will be appreciated by those skilled in the art, in certain types of devices (for example, DRAM devices) a DLL can be used to change the phase of a clock signal. In this regard, a DLL includes a delay chain composed of number of delay gates connected in series (in a daisy chain manner).

Thus the charge pump is an important component in PLLs and DLLs, and many issued patent are directed towards them. One such patent is U.S. Pat. No. 7,092,689 of Boecker et al. which discloses a charge pump including a first array of mirror devices for producing, within the charge pump, a positive delta current, and a second array of mirror devices for producing, within the charge pump, a different delta current. Each mirror device in either of the arrays has current mirrored into it from a different reference current source, and the phase shift producing currents generated by the arrays do not track the charge pump current. As a result, trying to calculate the effects of the arrays under actual operating conditions based upon the conditions existing at testing/calibration time is difficult.

Accordingly, it would be advantageous to improve upon charge pump circuits that facilitate phase shifting in a DLL or PLL.

SUMMARY

According to one example embodiment, there is a method for charging and discharging a capacitance in a feedback system. The feedback system includes a charge pump in electrical communication with the capacitance. The charge pump has a source portion and a sink portion. The method includes the step of generating a source current from the source portion when a charge up control signal is at an active logic level. The source current charges the capacitance. The method also includes the step of generating a sink current from the sink portion when a charge down control signal is at an active logic level. The sink current discharges the capacitance. The method also includes the step of carrying out fine-tune phase shifting by generating at least one offset current in at least a selected one of the source and sink portions. The offset current tracks the charge pump current and is generated irrespective of either of the control signals.

According to another example embodiment, there is a charge pump circuit that includes a capacitor connected in parallel to an output node. A reference current source generates a reference current. A primary current switching circuit charges the capacitor with a source current and discharges the capacitor with a sink current. The source current tracks the reference current and the sink current tracks the reference current. A supplemental source circuit sources a positive phase shift producing current which has a range of magnitudes. A magnitude of the positive phase shift producing current is determined by at least one source selection signal. The positive phase shift producing current tracks the same current tracked by the source current. A supplemental sink circuit for sources a negative phase shift producing current which has a range of magnitudes. A magnitude of the negative phase shift producing current is determined by at least one sink selection signal. The negative phase shift producing current tracks the same current tracked by the sink current.

According to another example embodiment, there is a method for providing charge up and charge down control signals having active and inactive logic levels to a charge pump in a delay-locked loop. The charge pump charging a capacitance in response to the active logic level of the charge up signal, and discharging the capacitance in response to the active logic level of the charge down signal. In response to detection of a first edge of a reference clock signal, there is a change of logic levels of the charge down signal from the inactive logic level of the charge down signal to the active logic level of the charge down signal. In response to detection of an edge of a feedback clock signal falling within less than 180 degrees from the first edge, there is a change of logic levels of the charge up signal from the inactive logic level of the charge up signal to the active logic level of the charge up signal, and there is a change of logic levels of the charge down signal from the active logic level of the charge down signal to the inactive logic level of the charge down signal. In response to detection that an edge of an additional reference signal at a point in time about midway between the first edge and a subsequent edge of the reference clock signal has past, changing the active logic level of the charge up signal to the inactive logic level, while maintaining the charge down signal at the inactive logic level.

Expediently, charging and discharging can, in some examples, be disabled during a period of time between the midway point in time and the subsequent edge of the reference clock signal.

Conveniently, the additional reference signal can, in some example, be 180 degrees phase shifted relative to the reference clock signal.

According to another example embodiment, there is a delay-locked loop that includes a voltage control delay line for receiving a reference clock signal and for delaying the reference clock signal to provide a feedback clock signal. A phase detector for receiving the reference clock signal and the feedback clock signal. The phase detector generating charge up and charge down control signals dependent upon a phase difference between the reference clock signal and the feedback clock signal. A loop filter includes a capacitor for providing a variable bias voltage for selecting a delay to be added to the reference clock signal by the voltage control delay line. A charge pump includes at least two switching transistors. One of the switching transistors permits current to be added into the capacitor when switched on in response to the charge up signal. Another of the switching transistors permits current to be removed from the capacitor when switched on in response to the charge down signal. The switching transistor of source current is controlled by the charge up signal and the switching transistor of sink current is controlled by the charge down signal. The phase detector receives the reference clock signal, an additional reference signal, and the feedback clock signal. The phase detector generates a charge up control signal having a first duration of time in response to a first edge of the reference clock signal. A charge down control signal has a second duration of time in response to an edge of the feedback clock signal occurring within less than 180 degrees from the first edge. The first duration of time is substantially similar to a first time between the first edge of the reference clock signal and the edge of the feedback clock signal. The second duration of time is substantially similar to a second time between the edge of the feedback clock signal and a midway signal edge occurring between the first edge and a subsequent edge of the reference clock signal.

Conveniently, during one period of the reference clock signal the charge pump is, in some examples, disabled during about half of the period.

Expediently, the phase detector includes, in some examples, at least four D Flip-Flops, and each of the clock signals is received by at least one of the D Flip-Flops at a clock input.

According to yet another example embodiment, there is a delay-locked loop that includes a voltage control delay line for receiving a reference clock signal. A phase detector also receives the reference clock signal and generates charge up and charge down control signals dependent upon a phase difference between the reference clock signal and a feedback clock signal. A loop filter includes a capacitor. The loop filter integrates the charge up and charge down control signals to provide a variable bias voltage for selecting a delay to be added to the reference clock signal by the voltage control delay line. A source portion of a charge pump includes at least one switching transistor, a first sourcing transistor and at least another sourcing transistor. The sourcing transistors are in electrical communication with the capacitor. At least a current carrying terminal of the first sourcing transistor is electrically connected to a current carrying terminal of the source portion switching transistor. The source portion switching transistor is controlled by the charge up control signal and, if switched on, permits current to be sourced via the first sourcing transistor into the capacitor. The source portion further includes means for disabling the sourcing of current via the first sourcing transistor. A sink portion of the charge pump includes at least one switching transistor, a first sinking transistor and at least another sinking transistor. The sinking transistors are in electrical communication with the capacitor. At least a current carrying terminal of the first sinking transistor is electrically connected to a current carrying terminal of the sink portion switching transistor. The sink portion switching transistor is controlled by the charge down control signal and, if switched on, permits current to be sunk via the first sinking transistor from the capacitor. The sink portion further includes means for disabling the sinking of current via the first sinking transistor.

Conveniently, the current sourcing disabling means and the current sinking disabling means can, in some examples, each include a select transistor, the current sourcing or sinking via the first sourcing or sinking transistor being disabled if the select transistor is turned off.

Expediently, the current sourcing disabling means and the current sinking disabling means can, in some alternative examples, each include transmission gate means between a bias voltage terminal of a mirror master transistor and a bias voltage terminal of the first sourcing or sinking transistor, the current sourcing or sinking via the first sourcing or sinking transistor being disabled if the transmission gate means breaks a conduction path between the two bias voltage terminals.

Conveniently, the source portion switching transistor and the sourcing transistors can, in some examples, be PMOS transistors, and the sink portion switching transistor and the sinking transistors can, in some examples, be NMOS transistors.

Expediently, one current carrying terminal of each of the sourcing (or sinking) transistors can, in some examples, collectively all be electrically connected to the current carrying terminal (e.g. drain) of the source (or sink) portion switching transistor.

Conveniently, the charge pump can, in some alternative examples, further include another source portion switching transistor and another sink portion switching transistor, a current carrying terminal of the another sourcing transistor being electrically connected to a current carrying terminal of the another source portion switching transistor, and a current carrying terminal of the another sinking transistor being electrically connected to a current carrying terminal of the another sink portion switching transistor.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

In the following detailed description of example embodiments, a number of illustrated circuits and circuit components are of a type which performs known operations on electronic signals. Those skilled in the art will have knowledge of alternative circuits or circuit components which are recognized as equivalent because they provide the same operations on the signals. Similar or the same reference numerals and labeling may have been used in different figures to denote similar components or signals.

Referring now to the drawings,FIG. 1is a block diagram of a prior art Delay-Locked Loop (DLL)100. In the DLL100, an externally supplied clock (CLK) is buffered by clock buffer101to provide a reference clock (CLK_REF). As understood by those skilled in the art, the CLK signal could be, for example, a data strobe signal (DQS or DQSb signal) transmitted from a memory controller to a memory device. However, it is of course possible that the CLK signal will, in alternative examples, be some other type of clock signal. Continuing on with the discussion of the DLL block diagram ofFIG. 1, it will be seen that CLK_REF is coupled to a Voltage Controlled Delay Line (VCDL)102and a phase detector104. The VCDL102produces an output clock (CLK_OUT), which is a delayed version of CLK_REF and is routed to various circuits within the device containing the DLL100. As shown, CLK_OUT is also routed to the phase detector104, and thus the phase detector104receives CLK_OUT as a feedback clock signal, referred to as CLK_FB.

With respect to phase shifting by the DLL, those skilled in the art will appreciate that in some memory systems where the timing signal being phase shifted is DQS or DQSb (the complement of DQS), the timing signal will be shifted by 90 degrees so that the edges of the timing signal are centered with respect to its associated data. Also, as clock frequencies in memory systems become increasingly higher, the ability to make fine-tuned phase shifting adjustments will continue to become increasingly useful.

Still with reference to the illustrated DLL100, the phase detector104generates phase control signals (UP/DOWN) dependent on the phase difference between CLK_REF and CLK_FB. The phase control signals (UP/DOWN) of the phase detector104are provided to a charge pump105, the output thereof which is conditioned by a loop filter106to provide a variable bias voltage VCTRL110. Those skilled in the art will understand that loop filter106can include any number of passive components arranged in a desired configuration. The bias voltage VCTRLselects the delay to be added to CLK_REF by the VCDL102to provide for the proper phase relation between CLK_FB and CLK_REF. VCDL102can be implemented with a variety of known circuits.

Another type of feedback system known to those skilled in the art of memory design is a Phase-Locked Loop (PLL).FIG. 2is a block diagram of a prior art PLL200. An externally supplied clock (CLK) is buffered by clock buffer201to provide a reference clock (CLK_REF) that is coupled to a phase detector204. The phase detector204generates phase control signals (UP/DOWN) dependent on the phase difference between CLK_REF and CLK_FB.

The phase control signals (UP/DOWN) of the phase detector204are provided to a charge pump205, the output thereof which is conditioned by a loop filter206to provide a variable bias voltage VCTRL210. The bias voltage VCTRLcontrols a Voltage Controlled Oscillator (VCO)202which outputs a clock signal CLK_OUT. The frequency of the output clock signal CLK_OUT is proportional to the bias voltage VCTRL210. Also, the CLK_OUT signal is optionally coupled to a divider203to produce the CLK_FB signal.

Having now described the general architecture of PLLs and DLLs, it will be understood that the operation of a particular DLL will not always be independent of other PLLs present in the larger memory design. For example, two 90 degree phase shifted DQS and DQSb signals available within a master PLL can be provided to a slave DLL. It will be understood that, in such circumstances, the slave DLL output is dependent upon the phase and frequency information that the master PLL provides. This dependency is not necessarily disadvantageous, and it has been found, generally speaking, that slave DLLs relying upon master PLLs, as described above, provide output clocks that are, for a large majority of presently existing applications, properly phase shifted relative to the reference clock.

From the preceding cursory descriptions of PLLs and DLLs, it will be seen that if a PLL is examined and its components are compared to a DLL, one will find that at least some of the components of the PLL are similar to components in the DLL. For one, both a PLL and a DLL include a phase detector. Additionally, both a PLL and a DLL include a charge pump.

Turning now toFIG. 3, there is a circuit schematic representation of an XOR-type phase detector302and a charge pump304(some circuit components not relevant to an understanding of example embodiments may have been omitted fromFIG. 3). Those skilled in the art will appreciate that while XOR-type phase detectors can be employed in both DLLs and PLLs, their use is more common in DLLs; however their use in PLLs is also possible if the relevant design issues (for example, harmonic locking) are addressed.

The phase detector302is level sensitive and includes an XOR logic gate308to which the signals CLK_REF and CLK_FB are applied at the inputs of the XOR logic gate308. The output of the XOR logic gate308is electrically connected to both the gate of the switching transistor324and the gate of the switching transistor336. In operation, when the two compared signals CLK_REF and CLK_FB are completely in phase, the pair of in phase inputs to the XOR logic gate308will result in XOR gate outputting a constant level of logic ‘0’. When the two compared signals CLK_REF and CLK_FB are 180 degrees apart (one is logic ‘0’ when the other is logic ‘1’, and vice versa) the XOR logic gate308puts out a steady logic ‘1’ signal. Between the two extremes, the XOR logic gate308outputs logic ‘1’ for half of the cycle. Thus,FIG. 4is a timing diagram illustrating CLK_REF, CLK_FB, Pulse Up (PU) control signal and Pulse Down (PD) control signal when the XOR logic gate308outputs logic ‘1’ for half of the cycle. (It has been assumed for the above description that both compared signals CLK_REF and CLK_FB have 50 percent duty cycles.)

With respect to the illustrated charge pump304, it includes a source portion and a sink portion between which is a VCTRLnode320. The sourcing portion includes a switching transistor324and a sourcing transistor328, which are PMOS transistors in the illustrated example. The sinking portion includes a switching transistor336and a sinking transistor332, which are NMOS transistors in the illustrated example. The illustrated charge pump304also includes a current mirror344for mirroring current in the transistors328and332. Generally, current mirror344is a reference current source circuit. The current mirror344also establishes the bias voltages being applied to the gates of the transistors328and332. A capacitor340has one terminal electrically connected to Vddand another terminal electrically connected to the VCTRLnode320. As will be appreciated by those skilled in the art, VCTRLcan be changed by net charging or net discharging of the capacitor340, and by bringing about a change in VCTRL, a phase shift can be effected. Capacitor340can be a passive component of the loop filter, or alternately, capacitor340can be a component of charge pump304.

Charging is achieved by adding current to the capacitor340, while discharging is achieved by removing current from the capacitor340. It will be seen that if currents IMand INhave equal magnitudes over a period of time, then the capacitor340will continually charge and discharge by equal amounts and equal durations resulting in no net change to voltage Vcat the VCTRLnode320.

The conditions for equal IMand INmagnitudes in the illustrated example charge pump is as follows. IMand INwill have equal magnitudes if, for example (i) the width-to-length (W/L) ratio of the transistor328and the PMOS FET of the current mirror344are equal; and (ii) the W/L ratio of the transistor332and the NMOS FET of the current mirror344are equal. (In at least one example, regulation of current is further facilitated by use of an operational amplifier as described and illustrated in commonly assigned US patent application Publication No. 2005/0162200 of Haerle.)

With respect to when IMand INwill have equal durations in the illustrated example charge, under the assumption of clocks of 50 percent duty cycle, IMand INwill repeatedly be current pulses of the same duration if the CLK_FB signal is phase shifted by 90 degrees with respect to the CLK_REF signal.

FIG. 4is a sequence, or timing, diagram showing the operation of phase detector302ofFIG. 3.FIG. 4illustrates traces for input signals CLK_REF, CLK_FB and output signals PU and PD. It is assumed that the circuit is operating at a steady state, meaning that CLK_FB has reached the 90 degree phase shift relative to CLK_REF. As shown inFIG. 4, in one full CLK_REF clock cycle (ie. between t0and t4), signals PU and PD will cycle between the high and low logic states. Therefore, transistors324and336are constantly, and alternately, turned on and off.

Reference will now be made toFIG. 5.FIG. 5is a circuit schematic of a phase detector500in accordance with an example embodiment. As will be appreciated by those skilled in the art, not all components that will be present in an actual implementation have been illustrated, these absent components having been omitted in order to improve clarity and with an appreciation that their inclusion would not consequently impact an understanding of the illustrated example embodiment. The phase detector500can be employed within a DLL like the DLL shown inFIG. 1(from a system perspective). Employment of the phase detector500within a PLL like the PLL shown inFIG. 2(from a system perspective) may be less likely; however if the relevant design issues (for example, harmonic locking) are addressed, use of the phase detector500within PLLs is also possible. Also, the phase detector500may, in some examples, be used in combination with the charge pump circuits ofFIGS. 7 and 8(descriptions of which are provided in later paragraphs of this disclosure).

The illustrated phase detector500includes: four D Flip-Flops504,506,510and512, four inverters516,520,522and526, and two NAND logic gates530and534. The illustrated phase detector500receives four input signals: CLK_REF, CLK_FB, CLK—180 and Vdd. CLK_REF is electrically connected to the clock inputs of the D Flip-Flops504and510. (Each of the D Flip-Flops illustrated inFIG. 5is rising-edge triggered.) CLK_FB is electrically connected to the clock input of the D Flip-Flop512. CLK—180, which is a 180 degree phase shifted version of CLK_REF, is electrically connected to the clock input of the D Flip-Flop506. Finally, Vddis electrically connected to the inputs of the D Flip-Flops504,506,510and512.

Still with reference to the D Flip-Flops, the output of the D Flip-Flop504is electrically connected to a first input of the NAND logic gate530, a first input of the NAND logic gate534, and the reset (RSTB) terminal of the D Flip-Flop506. Also, the output of the D Flip-Flop506is electrically connected to the input of the inverter516, the output of the inverter516being electrically connected to the RSTB input of the D Flip-Flop504. The output of the D Flip-Flop510is electrically connected to a second input of the NAND logic gate534, and also the RSTB input of D Flip-Flop512and the input of inverter526, the output of the inverter526being electrically connected to a second input of the NAND logic gate530. Additionally, the output of the D Flip-Flop512is electrically connected to the input of inverter522, the output of the inverter522being electrically connected to the RSTB input of the D Flip-Flop510.

A Pulse UP (PU) control signal provided to a charge pump is generated at the output of the NAND logic gate530. (It will be understood that the term charge up control signal used in this application also refers to a control signal for controlling charging within a charge pump.) A Pulse Down (PD) control signal, which is also provided to the charge pump, is generated at the output of the inverter520, the output of the NAND logic gate534being electrically connected to the input of the inverter520. (It will be understood that the term charge down control signal used in this application also refers to a control signal for controlling discharging within a charge pump.)

In operation, the PU and PD signals produced by the illustrated phase detector500will cause, within the charge pump to which these signals are electrically connected, VCTRLnode capacitor charging/discharging activity during only half of the clock period. This behavior of the phase detector500will be apparent when the operation of the D Flip-Flops504,506,510and512is understood.

In the behavioral description of the phase detector500that follows, reference will be made to bothFIGS. 5 and 6.FIG. 6is a timing/sequence diagram illustrating the operation of the phase detector500with CLK_FB phase shifted 90 degrees relative to CLK_REF (as previously explained, in some examples this will be the desired phase shift for the clock signal so that the clock signal is properly aligned in the center of its associated data). Also, it will be understood that the clock signals illustrated inFIG. 6have duty cycles that are significantly less than 50 percent, but have the same period as the clock signals shown inFIG. 4. Those skilled in the art will understand that clocks having a 50 percent duty cycle can be used.

As explained in more detail below, in response to detection of a rising edge of CLK_REF (reference clock signal) the PD control signal will change logic levels (logic ‘0’ to logic ‘1’) and also the logic level of the PU control signal will be maintained (the logic level will stay at logic ‘1’) thereby enabling charge pump discharging, while keeping charge pump charging disabled. Referring to the D Flip-Flops504and510, these Flip-Flops output the logic level on their input, which is logic ‘1’ (Vdd) on the rising edge of CLK_REF. The logic ‘1’ on the output of the D Flip-Flop504is received at an input540of the NAND logic gate530and at an input542of the NAND logic gate534. The logic ‘1’ at the output of the D Flip-Flop504is also received by the RSTB input of the D Flip-Flop506, which is ignored because the RSTB input is active “low”. The logic ‘1’ at the output of the D Flip-Flop510is received by input546of the NAND logic gate534and the input of the inverter526, which inverts the logic ‘1’ to a logic ‘0’ that is received at input550of the NAND logic gate530. The logic ‘1’ at the output of the D Flip-Flop510is also received by the RSTB input of the D Flip-Flop512, but again, as previously explained, the D Flip-Flop512ignores this. If a logic ‘1’ received at the input540and a logic ‘0’ is received at the input550, output552of the NAND logic gate530will be logic ‘1’. Therefore, the PU signal is logic ‘1’ with the result being that charging in the charge pump remains disabled. With a logic ‘1’ signal on the input546of the NAND logic gate534and a logic ‘1’ signal on the input542of the NAND logic gate534, the output of the NAND logic gate534is logic ‘0’. The inverter520inverts the signal so that the PD signal will be logic ‘1’ enabling the charge pump, with respect to which the phase detector500communicates its control signals, to carry out discharging. Thus, in response to detection of a rising edge of CLK_REF, the PD control signal will change logic levels, as shown by transition arrows602and604inFIG. 6.

The next rising edge occurs in the CLK_FB signal (feedback clock signal). (Those skilled in the art will appreciate that harmonic locking problems can occur in PLLs if the edge of the CLK_FB signal becomes more than 180 degrees out of phase from the corresponding edge in the CLK_REF signal.) As explained in more detail below, in response to detection of the rising edge of CLK_FB, the PU control signal will change logic levels (logic ‘1’ to logic ‘0’) and also the PD control signal will change logic levels (logic ‘1’ to logic ‘0’) thereby enabling charge pump charging and disabling charge pump discharging. Referring to the D Flip-Flop512, its clock input receives the CLK_FB signal. In response, the D Flip-Flop512outputs a logic ‘1’ which is inverted by the inverter522. A logic ‘0’ at the RSTB input of the D Flip-Flop510forces the output of the D Flip-Flop510to logic ‘0’, and this change in logic levels causes logic ‘0’ to be received at the input546and logic ‘1’ to be received at the input550. The outputs of the NAND logic gates530and534now change their logic levels so that the PU signal changes from logic ‘1’ to logic ‘0’ enabling charging within the charge pump, and also the PD signal changes from logic ‘1’ to logic ‘0’ disabling discharging within the charge pump. Thus, in response to detection of a rising edge of CLK_FB, both the PU and PD control signals will change logic levels, as shown by transition arrows606,608,610and612inFIG. 6. The transition of the PD signal from the active logic level to the inactive logic level marks the end of a duration of time substantially similar to a time between the edge of CLK_REF at t0and the edge of CLK_FB at t1.

The next rising edge occurs in the CLK—180 signal (an additional reference clock signal, phase shifted 180 degrees from CLK_REF, so that its rising edge is about midway between sequential rising edges of CLK_REF, providing indication of this midway point in time). As explained in more detail below, in response to detection of the rising edge of CLK—180 signal, the PU control signal will change logic levels (logic ‘0’ to logic ‘1’) and also the logic level of the PD control signal will be maintained (the logic level will stay at logic ‘0’) thereby disabling charge pump charging and keeping charge pump discharging disabled. Referring to the D Flip-Flop506, its clock input receives the CLK—180 signal. In response, the D Flip-Flop506outputs a logic ‘1’ which is inverted by the inverter516. A logic ‘0’ at the RSTB input of the D Flip-Flop504forces the output of the D Flip-Flop504to logic ‘0’, and this change in logic levels causes a logic ‘0’ to be received the input540of the NAND logic gate530, so the output of the NAND logic gate530changes from logic ‘0’ to logic ‘1’ while the outputs of the NAND gate534and the inverter520remain unchanged. Therefore, the PU signal changes from logic ‘0’ to logic ‘1’ disabling charging within the charge pump, and also the logic level of the PD signal will be maintained (the logic level will stay at logic ‘0’) keeping charge pump discharging disabled. Thus, in response to detection of a rising edge of CLK—180, the PU control signal will change logic levels, as shown by transition arrows614and616inFIG. 6. The transition of the PU signal from the active logic level to the inactive logic level marks the end of a duration of time substantially similar to a time between the edge of CLK_FB at t1and the edge of CLK—180 at t2.

In a steady state, the change in the PU and PD signals triggered by the CLK_FB rising edge will occur about one quarter of a clock period subsequent to the previous change in the PD signal triggered by the rising edge of the CLK_REF signal. During the roughly one quarter clock period between the CLK_REF and the CLK_FB rising edge, discharging occurs and charging does not occur. Also in the steady state, the change in the PU signal triggered by the CLK—180 rising edge will occur about one quarter of a clock period subsequent to the previous change in the PU and PD signals triggered by the rising edge of the CLK_FB signal. During the roughly one quarter clock period between the CLK_FB and the CLK—180 rising edge, charging occurs and discharging does not occur. During the remainder of the clock period neither charging nor discharging occurs. For example, during a half clock period between times t2and t4(see timing diagram ofFIG. 6) neither charging nor discharging occurs (i.e., the PU and PD signals from the phase detector500would result in the switching transistors of the DLL's charge pump both being simultaneously switched off for half of the clock period, and hence the loop filter capacitor would be neither charged nor discharged during that period). During a corresponding period of time t2to t4for the phase detector308ofFIG. 3, charging and discharging is occurring (see the logic levels of the PU and PD signals in the timing diagram ofFIG. 4). The phase detector500may thus have the advantage of permitting implementation of a DLL with reduced power consumption as compared to the phase detector308.

The phase detector500eliminates the need for the reference clock signals that were previously discussed in previous paragraphs of the disclosure, or in other words, the phase detector500eliminates the need to have available a master DLL or PLL that would ordinarily provide the two reference clock signals used for phase shifting (however, as explained previously and as will be discussed in more detail below, the CLK—180 signal will, in some examples, be provided to the phase detector in order for the phase detector to operate as intended).

It will be understood that an additional characteristic of the illustrated phase detector500is that it is edge triggered rather than level sensitive. Typically, an edge triggered phase detector will not be subject to the same duty cycle requirements that a level sensitive phase detector is subject to.

Those skilled in the art will also appreciate that phase control signals similar to those generated by the illustrated phase detector500can be generated by alternative phase detectors comprised of different logic gates and circuitry than the phase detector500. For example, where CLK_REF is a 50 percent duty cycle clock, by replacing the D Flip-Flop506with one that is falling-edge triggered rather than rising-edge triggered, CLK_REF can be applied to the substituted D Flip-Flop, eliminating the need for CLK—180. With the D Flip-Flops504and510being triggered on a rising edge of the CLK_REF signal, the flip-flop put in substitution for the D Flip-Flop506is triggered on the falling edge (edge next in succession to the rising edge). While the above described implementation can be realized in some systems having phase detectors, it should be noted that in at least some instances it may be difficult to produce and make available a 50 percent duty cycle clock.

In some example embodiments, generated phase control signals may not exhibit the same logic level transitions that are characteristic of the illustrated phase detector500. As a simple example, if one were to add inverters along the paths between the phase detector and the gates of the switching transistors324and336(FIG. 3) one of skill in the art could readily alter the design of the phase detector to respond to the previously described clock edges in a similar manner, but with generated phase control signals having bit (logic level) sequences opposite to those of the phase detector500.

Other alternative example phase detectors are also contemplated. For instance, it will be understood that it would be straightforward for one of skill in the art to modify the illustrated phase detector500to realize a phase detector that would respond to falling clock edges rather that rising clock edges. Such a phase detector could achieve at least substantially the same effects and benefits associated with the illustrated phase detector500.

Reference will now be made toFIG. 7.FIG. 7is a circuit schematic of a charge pump700, in accordance with an example embodiment. As is known in the art, charge pump circuits uses capacitors to create either a higher or lower voltage. With respect to PLLs, a charge pump can be used to provide a control voltage applied to the VCO of the PLL. With respect to DLLs, a charge pump can be used to provide a control voltage for the VCDL of the DLL.

Referring now to the source portion of the illustrated charge pump700, in this portion there are secondary switching transistors706and708, secondary sourcing transistors710and712, and select transistors716and720. When current flows through primary switching transistor722and primary sourcing transistor724, current will only flow through the secondary switching transistor708and the secondary sourcing transistor712if a logic ‘0’ signal is applied to gate726of the select transistor720, and current will only flow through the secondary switching transistor706and the secondary sourcing transistor710if a similar logic ‘0’ signal is applied to gate728of the select transistor716. Thus, the sourcing of current via one or more of the secondary sourcing transistor710and712can be disabled if one or more of the select transistors716and720is made non-conducting. In the presently shown embodiment, gate726is controlled by enabling signal ep[0] and gate756is controlled by enabling signal en[0], while gate728and758are controlled by enabling signals ep[M] and en[N] respectively. M and N are integer values greater than 0, as there can be any number of select transistors and secondary switching transistors included in the circuit ofFIG. 7. In various alternate embodiments, N can be equal to M, or N can be different from M. IM, which is the sum of the currents sourced through the sourcing transistors710,712and724, tracks Iref.

In the sink portion of the illustrated charge pump700, there are secondary switching transistors732and734, secondary sinking transistors738and740, and select transistors744and746. When current flows through primary switching transistor750and primary sinking transistor754, current will only also flow through the secondary switching transistor734and the secondary sinking transistor740if a logic ‘1’ signal is applied at gate756of the select transistor746, and current will only flow through the secondary switching transistor732and the secondary sinking transistor738if a similar logic ‘1’ signal is applied at gate758of the select transistor744. Thus, the sinking of current via one or more of the secondary sinking transistor738and740can be disabled if one or more of the select transistors744and746is made non-conducting. IN, which is the sum of the currents sunk through the sinking transistors738,740and754, tracks Iref.

As will be appreciated by those skilled in the art, source portion current IMwill be greatest when all three of the sourcing transistors710,712and724are sourcing current, and IMwill be smaller when one or more of the select transistors716and720are turned off so that one or more of the secondary sourcing transistors710and712do not source additional current. Similarly, sink portion current INwill be greatest when all of the sinking transistors738,740and754are sinking current. However, INwill be less if one or more of the select transistors744and746are turned off so that one or more of the secondary sinking transistors732and734will not sink additional current. In this manner, the illustrated charge pump700permits scaling of charge pump currents to be carried out.

If one takes into account that, in the illustrated charge pump700, the phase shift corresponding to steady state will approximately follow equation (1) below:
Phase Shift=180*IN/(IM+IN)  (1)
It will be seen that scaling of charge pump currents as previously described provides for the ability to make fine-tuned adjustments in phase shifting. Also, if INand IMare expressed as (N+1)*Irefand (M+1)*Irefrespectively, where N and M represent the current mirror ratios, then the relationship expressed in equation (2) below also holds:
Phase Shift=180*(N+1)/(M+N+2)  (2)

As will be appreciated by those skilled in the art, a system that includes the charge pump700can also include a main controller having registers that provide the enable signals for controlling which of the select transistors716,720,744and746are made conducting or non-conducting. In particular, each of the enable signals from such main controller registers would be applied to one of the gates726,728,756and758. Alternate example embodiments ofFIG. 7can include any number of select transistors and corresponding secondary switching transistors. These select transistors and corresponding secondary switching transistors can be sized identically to the explicitly shown select transistors and secondary transistors to provide substantially linear scaling of the currents IMand IN. Alternately, these transistors can be sized differently to provide non-linear scaling of the currents IMand INFurthermore, any combination and number of enable signals can be driven to the activate logic level to turn on their corresponding select transistors.

FIG. 8is a circuit schematic of a charge pump800, in accordance with another example embodiment. As will be evident from the explanation that follows, it will be seen that the charge pump800scales charge pump currents in a similar matter to the charge pump700ofFIG. 7.

In the source portion of the illustrated charge pump800, there are M sourcing transistors (two of which are shown and labeled808and810), M transmission gates (two of which are shown and labeled804and805), M pull-up transistors (two of which are shown and labeled806and807), a mirror master transistor814, and a switching transistor816. It will be understood that the mirror master transistor814can mirror current in any one or more of the sourcing transistors808and810, but only if the interposed transmission gate804and/or805enables a path for the master transistor814to mirror current to sourcing transistor(s). Thus, the sourcing of current via one or more of the M sourcing transistors can be disabled if path(s) through the transmission gate(s) are disabled. By contrast, the sourcing of current via sourcing transistor813is not impacted by any of the transmission gates804. IM, which is the sum of the currents sourced through the sourcing transistors808,810,812and813, tracks Iref.

In the sink portion of the charge pump800, there are N sinking transistors (two of which are shown and labeled826and828), N transmission gates (two of which are shown and labeled822and823), N pull-down transistors (two of which are shown and labeled824and825), a mirror master transistor834, and a switching transistor836. Again, the mirror master transistor834can mirror current into one or more of the sinking transistors826and828, but only if the interposed transmission gates822and/or823enable a path for the master transistor834to mirror currents to sinking transistor(s). If one or more of the N transmission gates cause the path(s) between the sinking transistor(s) and the master transistor834to be closed, then current will not be mirrored into that/those sinking transistor(s). Thus, the sinking of current via one or more of the N sinking transistors can be disabled if path(s) through the transmission gate(s) are disabled. By contrast, the sinking of current via sinking transistor831is not impacted by any of the N transmission gates. IN, which is the sum of the currents sunk through the sinking transistors826,828,830and831, tracks Iref.

As will be appreciated by those skilled in the art, the pull-up and pull-down transistors806,807,824,825prevent the sourcing and the sinking transistors from turning on when their corresponding transmission gates are turned off. Also, it will be understood that each of the M transmission gates in the source portion of the charge pump800could be replaced by, for example, a PMOS transistor that would achieve a result similar to that achieved by use of a transmission gate. Similarly, each of the N transmission gates in the sink portion of the charge pump800could be replaced by, for example, an NMOS transistor that would achieve a result similar to that achieved by use of a transmission gate.

Still with reference toFIG. 8, it will be apparent that sourcing current IMwill be largest when all three of the sourcing transistors808,810and813are sourcing current, and when less than all three transistors are sourcing current, IMwill be smaller. Similarly, it will be seen that INwill be largest when all three of the sinking transistors826,828and831are sinking current, and INwill be smaller when less than all three sinking transistors are sinking current. In this manner, the illustrated charge pump800permits scaling of charge pump currents to be carried out.

If one takes into account that, in the illustrated charge pump800, the phase shift corresponding to steady state will approximately follow equation (3) below:
Phase Shift=180*IN/(IM+IN)  (3)

It will be seen that scaling of charge pump currents as previously described provides for the ability to make fine-tuned adjustments in phase shifting. Also, if INand IMare expressed as (N+1)*Irefand (M+1)*Irefrespectively, where N and M represent the current mirror ratios, then the relationship expressed in equation (4) below also holds:
Phase Shift=180*(N+1)/(M+N+2)  (4)

As will be appreciated by those skilled in the art, a system that includes the charge pump800can also include a main controller having registers that provide the enable signals ep[M:0] and epb[M:0] for controlling which of the M transmission gates in the source portion of the charge pump800are enabled or disabled, and for controlling which of the M pull-up transistors in the source portion of the charge pump800are made conducting or non-conducting. In particular, each of the enable signals from such main controller registers would be applied to at least one of the gates of the transmission gates and/or pull-up/pull-down transistors. Similar enable signals could also be provided in a similar manner for similar control in the sink portion of the charge pump800.

FIG. 9is a circuit schematic of a charge pump900in accordance with yet another example embodiment. The operations of the sourcing transistor328, the sinking transistor332, the current mirror344and the switching transistors324and336have been previously described, and hence it is unnecessary to repeat what has been previously described in detail. In the previously shown charge pump embodiments, the magnitude of currents IMand INprovided when PU or PD are at their active logic levels, can be adjusted by selectively turning on secondary switching transistors, secondary sourcing transistors, and select transistors. This is due to the configuration of the shown charge pump circuits in which the transistors receiving control signals PU and PD are in series with the sourcing and sinking transistors. In the presently shown embodiment ofFIG. 9, offset currents can be independently applied to currents IMand IN. Typically, these offset currents will be continuously generated.

In at least one example, the PU and PD signals applied at the gates of the switching transistors324and336are generated by a Phase Frequency Detector (PFD) such as the PFD described in “Phase-Locked Loops: Design, Simulation, and Applications, 4thEdition”, Best, Roland E., McGraw-Hill, ©1999 at pgs. 92-102, the entire contents of which are herein incorporated by reference.

Turning now to the source portion of the charge pump900, there is a supplemental source circuit that in the illustrated example embodiment comprises a first programmable array of transistors902for generating offset current IOFFSETP. Three of M pairs of PMOS transistors are shown within the illustrated programmable array of transistors902, with transistors of each pair being connected in series. In the illustrated example embodiment, the circuitry for controlling current sourcing in each pair comprises a select transistor. Each of select transistors906,908and910have their drains coupled to Vddand their sources electrically connected to the drains of one of sourcing transistors912,914and916.

The illustrated charge pump900also includes a supplemental sink circuit in the sink portion of the charge pump900. In the illustrated example embodiment, the supplemental sink circuit comprises a second programmable array of transistors904for generating offset current IOFFSETN. Three of N pairs of NMOS transistors are shown within the illustrated programmable array of transistors904, with transistors of each pair being connected in series. In the illustrated example embodiment, the circuitry for controlling current sinking in each pair comprises a select transistor. Three select transistors920,922and924are shown. Each of the select transistors920,922and924has its drain coupled to ground potential and its source coupled to one of the drains of sinking transistors928,930and932.

IOFFSETP, a positive phase shift producing current which is the sum of the currents sourced through the sourcing transistors912,914and916, tracks the charge pump current. In operation, IOFFSETPin the source portion of the charge pump900can be increased or decreased by turning on or turning off one or more of the select transistors906,908and910. The select transistors906,908and910are turned on by applying a logic low signal at their respective gates936,940and942.

IOFFSETN, a negative phase shift producing current which is the sum of the currents sunk through the sinking transistors928,930and932, tracks the charge pump current. IOFFSETNin the sink portion of the charge pump900can be increased or decreased by turning on or turning off one or more of the select transistors920,922and924. The select transistors920,922and924are turned on when a logic high signal is applied to their respective gates946,948and950.

It will be understood that the offset currents can be used to cause phase shifting. For instance, the phase shift in the illustrated charge pump900is equal to the difference between IOFFSETPand IOFFSETNmultiplied by 360 and divided by IM. In some examples, the sourcing transistors of the programmable array902have, from the Mthto the 1st, incrementally larger device channel W/L ratios, and the sink transistors of the programmable array904also have, from the Nthto the 1st, incrementally larger device channel W/L ratios. For instance, the transistors916and932, in one example, have equal device channel W/L ratios that are ½ the device channel W/L ratios of the transistors328and332, the transistors914and930have device channel W/L ratios that are ⅓ the device channel W/L ratios of the transistors328and332, and the transistors912and928have device channel W/L ratios that are ¼ the device channel W/L ratios of the transistors328and332. With these example values, any of various different phase shifts can be realized. For instance, if the select transistors906,910,922and924are turned off, and the select transistors908and920are turned on, the phase shift would be (⅓−¼)*360°=30°. Alternatively say the select transistors910,922and924are turned off, and the select transistors906,908and920are turned on, the phase shift would be ((⅓+¼)−¼)*360°=120°. It will be understood that although in the above example, each of the sourcing transistors has different ratios to accommodate phase shift adjustments that can either be quite fine or more coarse, in other examples the sourcing transistors could each have the same ratio.

As will be appreciated by those skilled in the art, a system that includes the charge pump900can also include a main controller having registers that provide the enable signals for controlling which of the select transistors906,908,910,920,922and924are made conducting or non-conducting. In particular, each of the enable signals from such main controller registers would be applied to one of the gates936,940,942,946,948and950.

If the charge pump900is designed into a PLL then, as will be appreciated by those skilled in the art, a resistor, such as illustrated resistor988, is typically added in series with the capacitor340. By contrast, if the charge pump900is designed into a DLL, then the resistor988would be absent.

FIG. 10is a circuit schematic of a charge pump1000in accordance with yet another example embodiment. This circuit provides offset currents which can be independently applied to currents IMand IN, and which will typically be continuously generated. The circuit embodiment ofFIG. 9has first and second programmable array of transistors connected directly to sourcing transistor328and sinking transistor332, thereby directly generating the offset currents. The circuit of the present embodiment on the other hand uses its first and second programmable array of transistors to control an offset generator circuit for generating the offset currents. The operations of the sourcing transistor328, the sinking transistor332, the current mirror344and the switching transistors324and336have been previously described, and hence it is unnecessary to repeat what has been previously described in detail. In at least one example, the PU and PD signals applied at the gates of the switching transistors324and336are generated by a PFD of the type described in the previously referred to Roland E. Best reference.

With reference to the source portion of the charge pump1000, there is a supplemental source circuit that in the illustrated example embodiment comprises a programmable array of transistors1002, a bias transistor1056, a current source transistor1058, and transistor1060. The illustrated programmable array of transistors1002includes M+1 pairs of PMOS transistors, with transistors of each pair being connected in series. Each of select transistors1006,1008and1010have their drains coupled to Vddand their sources electrically connected to the drains of one of gate-drain-connected transistors1012,1014and1016. As before, while in some examples each of the gate-drain connected transistors will have the same ratios, in other examples, each of the gate-drain connected transistors will have a different ratio. An additional pair of PMOS transistors1018,1019is provided to prevent deviation from the calibrated offset current (under certain conditions) as will be explained subsequently.

With reference to the sink portion of the charge pump1000, there is a supplemental sink circuit that in the illustrated example embodiment comprises a programmable array of transistors1004, a bias transistor1052, a current sink transistor1054, and transistor1064. The illustrated programmable array of transistors1004includes N+1 pairs of NMOS transistors, with transistors of each pair being connected in series. Each of select transistors1020,1022and1024has a drain coupled to ground potential and its source coupled to one of the drains of gate-drain connected transistors1028,1030and1032. An additional pair of NMOS transistors1033,1034is provided to prevent deviation from calibrated offset current (under certain conditions) as will be explained subsequently.

The array of transistors1002in the source portion of the illustrated charge pump1000is provided for setting offset current IOFFSETP. Also, it will be understood, as explained subsequently in more detail, that the circuitry for controlling the sourcing of current through sourcing transistor1058comprises the array of transistors1002. The array of transistors1004in the sink portion of the illustrated charge pump1000is provided for setting offset current IOFFSETN. Also, it will be understood that, as explained subsequently in more detail, the circuitry for controlling the sinking of current through sinking transistor1054comprises the array of transistors1004.

In the illustrated example, transistor1052, which is in a current mirror relationship with the PMOS FET of Iref, has the same device channel W/L ratio as the FET328and the PMOS FET of Iref. Also, each of the gate-drain connected transistors1028,1030and1032has the same device channel W/L ratio as the sinking transistor1054, and the sinking transistor1054is in a current mirror relationship with the array of transistors1004so that the sinking of current through the sinking transistor1054is controlled by the array of transistors1004. Furthermore, with device channel W/L ratios having relative values as mentioned above, the magnitude of IOFFSETNis roughly equal to

1H+1*Iref
(where H is the number of select transistors in the array of transistors1004that are turned on, and H being any whole number less than or equal to N, the total number of select transistors in the array of transistors1004). Those skilled in the art will appreciate the impact(s) of changing the relative device channel W/L ratios. For example, with all other factors remaining the same, a percentage increase/decrease in the device channel W/L ratio of the transistor1052will result in a correspondingly equal percentage increase/decease in the magnitude of IOFFSETN.

In the illustrated example, transistor1056, which is in a current mirror relationship with the NMOS FET of Iref, has the same device channel W/L ratio as the FET332and the NMOS FET of Iref. Also, each of the gate-drain connected transistors1012,1014and1016has the same device channel W/L ratio as the sourcing transistor1058, and the sourcing transistor1058is in a current mirror relationship with the array of transistors1002so that the sourcing of current through the sourcing transistor1058is controlled by the array of transistors1002. Furthermore, with relative device channel W/L ratios having relative values as mentioned above, the magnitude of IOFFSETPis roughly equal to

1G+1*Iref
(where G is the number of select transistors in the array of transistors1002that are turned on, and G being any whole number less than or equal to M, the total number of select transistors in the array of transistors1002). Those skilled in the art will appreciate the impact(s) of changing the relative device channel W/L ratios. For example, with all other factors remaining the same, a percentage increase/decrease in the device channel W/L ratio of the transistor1056will result in a correspondingly equal percentage increase/decease in the magnitude of IOFFSETP.

As previously explained in connection withFIG. 9, the phase shift in the illustrated charge pump1000is equal to the difference between IOFFSETPand IOFFSETNmultiplied by 360 and divided by IM. Substituting for the previously defined variables G and H, it will be seen that the phase shift can be expressed as follows:

360*(1G+1-1H+1).
Thus, in operation, IOFFSETPin the source portion of the charge pump1000can be increased or decreased by turning on or turning off one or more of the select transistors1006,1008and1010. The select transistors1006,1008and1010are turned on by applying a logic low signal at their respective gates1036,1040and1042via control signals ep[M:0]. Similarly, IOFFSETNin the sink portion of the charge pump1000can be increased or decreased by turning on or turning off one or more of the select transistors1020,1022and1024. The select transistors1020,1022and1024are turned on when a logic high signal is applied to their respective gates1046,1048and1050via control signals en[N:0].

As will be appreciated by those skilled in the art, a system that includes the charge pump1000can also include a main controller having registers that provide the enable signals for controlling which of the select transistors1006,1008,1010,1020,1022and1024are made conducting or non-conducting. In particular, each of the enable signals from such main controller registers would be applied to one of the gates1036,1040,1042,1046,1048and1050.

The offset generator includes transistors1060,1064,1058and1054, where additional enable signals en_p and en_n are applied to transistors1060and1064respectively. Under conditions where no select transistors in the array of transistors1002are turned on, en_p will be set to an inactive logic level (which is logic high in the illustrated example) and the transistors1018,1019and1060will help ensure deviation from calibrated offset current is avoided. For example, the voltage at the node to which the drain of the bias transistor1056is connected will not be allowed to float. Similarly under conditions where no select transistors in the array of transistors1004are turned on, en_n will be set to an inactive logic level (which is logic low in the illustrated example) and the transistors1033,1034and1064will help ensure deviation from calibrated offset current is avoided. For example, the voltage at the node to which the drain of the bias transistor1052is connected will not be allowed to float.

It will be understood that in those instances where M and N are greater than 1, few transistors are directly connected to the VCTRLnode of the charge pump1000as compared to the VCTRLnode of the charge pump900. As a result, the VCTRLnode of charge pump1000has less capacitance loading as compared to the charge pump900. Also, if the charge pump1000is designed into a PLL then, as will be appreciated by those skilled in the art, a resistor, such as the illustrated resistor988, is typically added in series with the capacitor340. By contrast, if the charge pump1000is designed into a DLL, then the resistor988would be absent.

A number of circuits and methods for scaling of charge pump currents in order to make fine-tuned adjustments in phase shifting have been described and illustrated. It will be apparent that these circuits and methods can be modified by one skilled in the art, and in so doing other circuits and methods can be realized which share at least some non-trivial similarities to the charge pump current scaling circuits and methods described herein. For example, one could incorporate circuitry into a charge pump that would continually cause an offset current to be sourced/added into and/or sunk/removed from the capacitor340regardless of the logic levels of the PU and PD control signals. Such an implementation would, in some examples, be less energy efficient than implementations previously described in this disclosure. It should be noted that capacitor340shown in the embodiments of the invention shown inFIGS. 7 and 8can be a passive component of the loop filter, or alternately, capacitor340can be a component of charge pumps700and800.

It will be understood that adjustments in phase shifting in accordance with example embodiments could be carried out, for example, during testing/calibration and/or dynamically.