RECESSED OXIDE AND SEAM-FIRST ETCH FOR AIR-GAPPED ISOLATION WALLS

Air gaps are incorporated into a transistor layer to reduce capacitance between conductive components. In some embodiments, along a gate cut region extending across the gates of multiple transistors, a gate cut dielectric may be partially or fully replaced by an air gap. The air gap may extend between two adjacent gates of two adjacent transistors, or between a gate and a via, where the via extends through the gate line and between two gates. The air gaps are capped by a dielectric material, so that additional layers (e.g., back side interconnect layers) may be formed over the air gap. An oxide layer over the transistor layer may be recessed relative to a via to ensure capping of the air gaps. The air gaps may be widened outward from a central seam in the gate cute dielectric.

BACKGROUND

Conventional transistors have a channel extending between a source region and a drain region, and a gate over the channel to turn the transistor on or off. The source region and drain region are each coupled to a respective contact that applies a current to the region. Similarly, the gate is connected to a contact to apply a current to the gate. Interconnect layers over a layer of transistors provide electrical connections to the transistors and to external devices and/or power supplies. In some IC designs, interconnect layers may be formed on both sides of the transistors, e.g., on a front side and a back side. For example, in some devices, gate, source, and/or drain contacts may be moved to the back side of the device. In some devices, power and/or signal connections may be formed on a back side of the device and extend through the transistor layer to the front side.

DETAILED DESCRIPTION

Overview

Transistor-based IC devices have isolation materials between different conductive components. The isolation materials provide electrical isolation between different components of transistors, e.g., between a gate and a source region. The isolation materials also provide electrical isolation between different transistors, e.g., between the gates of adjacent transistors.

In certain device architectures, parasitic capacitance between conductive components can degrade device performance. For example, there is a drive to reduce the feature size and increase density on IC chips. As transistor sizes decrease and transistor density increases, tightly-spaced conductive features (e.g., closely-packed gate lines) are subject to parasitic capacitance between adjacent features. As another example, in some designs, power may be delivered through the back side of an IC device, and the power can be routed to the front side of the IC device through the transistor layer. Power delivery vias extending through the transistor layer between adjacent gates can create unwanted capacitance with conductive gates, for example. As another example, back side contacts (e.g., back side source or drain contacts) can create parasitic capacitance with gate lines or other components.

Typically, a dielectric material is used as an isolation material between different conductive components in an IC device. Capacitance is proportional to the dielectric constant or relative permittivity of the material between two conductors, e.g., two adjacent gates, or a gate and a via next to the gate. Materials having a higher dielectric constant resulting in greater capacitance. Reducing the dielectric constant reduces the capacitance between conductors. Silicon dioxide is a common dielectric material that has a dielectric constant of 3.9. Dielectric materials with higher dielectric constants, such as silicon nitride, are often used between gates, as higher-k materials are often more robust than lower-k materials. Air gaps, with a dielectric constant of around 1, dramatically reduce capacitance relative to common dielectric materials.

As described herein, air gaps are incorporated into the device layer to reduce capacitance between conductive components of the IC device. For example, along a gate cut region extending across the gates of multiple transistors, a gate cut dielectric (e.g., silicon nitride) may be partially or fully replaced by an air gap. The air gap may extend between two adjacent gates (of two adjacent transistors), or between a gate and a via that extends through the gate line, between two gates.

The air gap may be formed from the back side of the transistor layer. For example, a transistor layer may be formed over a support structure, followed by several layers of front side interconnect. The device may then be flipped and the support structure removed to expose the back side of the transistor layer. Material in the transistor layer is etched from the back side to create the air gaps. The air gaps are then capped by a dielectric material, so that additional layers (e.g., back side interconnect layers) may be formed over the air gap.

Outside of the gate cut region, another dielectric material, such as an oxide, may be on a back side of the transistors. In a device that has a via extending through the transistor layer, the via may extend through the height of the oxide. When the assembly is flipped to expose the back side, as described above, the oxide layer is over the transistor layer, and the top of the via may be coplanar with the top of the oxide layer. If the gate cut dielectric is removed, forming air gaps, and then a dielectric cap deposited over the vias and oxide layer, the dielectric cap may not fill the tops of the air gaps, and thus, may not adequately cap and protect the air gaps during formation of the back side interconnect layers. As described herein, the top of the oxide layer may be recessed to a height below the ends of the vias. The dielectric cap material is deposited over the oxide layer and air gaps and polished to reveal the tops of the vias. By recessing the oxide layer, the dielectric cap is deposited below the tops of the vias, better ensuring adequate capping of the air gaps.

When the gate cut dielectric is deposited between adjacent gates, it may grow first in two layers over the pair of adjacent gates, and the two layers build towards the center of the gate cut region. A seam may be present where the two layers meet. When the gate cut dielectric is etched to form the air gaps, the seam may be etched first, and the gate cut dielectric may then be gradually widened. In some cases, layers of the gate cut dielectric may be left on the sides of the gates, e.g., to protect the gates during later processing steps. In the seam-first etch process, the air gap may extend to the bottom of the gate cut region (i.e., an end of the gate cut region nearest to the back side metallization layers). This may distinguish a seam-first etch from a deposition of a liner material within the air gap, as a liner material would also deposit along the bottom of the gate cut region. In addition, if different gate cut regions within a transistor layer have different widths, where width refers to a distance between adjacent gates, different air gaps may have the same width, while the layers of the gate cut dielectric remaining along the gates may have different widths or thicknesses.

Certain embodiments described herein relate to non-planar transistors. Non-planar transistors are three-dimensional electronic devices that deviate from a traditional flat transistor design. Compared to planar transistors, non-planar transistors can provide improved control over current flow, reduced leakage, and enhanced performance, making it a key technology for smaller, faster, and more energy-efficient electronic devices. Examples of non-planar transistors include fin-shaped field-effect transistors, referred to as FinFETs, and gate-all-around (GAA) transistors. FinFETs have a gate material that often surrounds a fin-shaped channel region on three sides. GAA transistors, also referred to as surrounding-gate transistors, have a gate material that surrounds a channel region on all sides. GAA transistors may be nanoribbon-based or nanowire-based.

In a nanoribbon transistor, a gate stack that may include one or more gate electrode materials and a gate dielectric may be provided around a portion of an elongated semiconductor structure called “nanoribbon”, forming the gate stack on all sides of the nanoribbon. A source region and a drain region are provided on the opposite ends of the nanoribbon(s) and on either side of the gate stack, forming, respectively, a source and a drain of the nanoribbon transistor. The source and drain regions are insulated from the gate stack, so that the voltages at the three terminals (gate, source, and drain) may be separately controlled.

Non-planar transistors provide several advantages over planar transistor architectures. For example, non-planar transistors provide improved electrostatic transistor control and faster transistor speeds relative to other transistor architectures. For certain applications, nanoribbon-based channels are particularly advantageous, providing increased drive current at smaller scales relative to other non-planar architectures.

IC devices typically include a metallization stack, which is a collection of several metal layers, stacked above one another, in which different interconnects are provided. As noted above, in some device architectures, both front side interconnect layers and back side interconnect layers, also referred to as front side metallization and back side metallization, are included. The front and back side metallization are provided on opposite sides of the transistor layer. Interconnect layers, also referred to as metal layers, include electrically conductive trenches, also referred to as lines, which provide connectivity across the layer, and electrically conductive vias (or, simply, “vias”) that provide electrical connectivity between different layers. In general, the term “trench” or “line” may be used to describe an electrically conductive element isolated by an insulator material (e.g., an insulator material typically comprising a low-k dielectric) that is provided in a plane parallel to the plane of an IC die/chip or a support structure over which an IC structure is provided, while the term “via” may be used to describe an electrically conductive element that interconnects two or more trenches of different levels of a metallization stack, or a component of the transistor layer and one or more trenches of a metallization layer. To that end, a via may be provided substantially perpendicularly to the plane of an IC die/chip or a support structure over which an IC structure is provided, and the via may interconnect two trenches in adjacent levels, two trenches in not adjacent levels, and/or a component of a transistor layer and a trench in adjacent or not adjacent layers. Sometimes, trenches and vias may be referred to as “metal trenches/tracks/lines/traces” and “metal vias”, respectively, to highlight the fact that these elements include electrically conductive materials such as, but not limited to, metals. Together, trenches and vias may be referred to as “interconnects,” where the term “interconnect” may be used to describe any element formed of an electrically conductive material for providing electrical connectivity to/from one or more components associated with an IC or/and between various such components.

The transistor layers with air gaps described herein may be implemented in one or more components associated with an IC. In various embodiments, components associated with an IC include, for example, transistors, diodes, power sources, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. Components associated with an IC may include those that are mounted on an IC or those connected to an IC. The IC may be either analog or digital and may be used in a number of applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. The IC may be employed as part of a chipset for executing one or more related functions in a computer.

For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term “between,” when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges. The meaning of “a,” “an,” and “the” include plural references. The meaning of “in” includes “in” and “on.”

In the following detailed description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. For example, as used herein, a “logic state” of a ferroelectric memory cell refers to one of a finite number of states that the cell can have, e.g. logic states “1” and “0,” each state represented by a different polarization of the ferroelectric material of the cell. In another example, as used herein, a “READ” and “WRITE” memory access or operations refer to, respectively, determining/sensing a logic state of a memory cell and programming/setting a logic state of a memory cell. In other examples, the term “connected” means a direct electrical or magnetic connection between the things that are connected, without any intermediary devices, while the term “coupled” means either a direct electrical or magnetic connection between the things that are connected or an indirect connection through one or more passive or active intermediary devices. The term “circuit” means one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. In yet another example, a “high-k dielectric” refers to a material having a higher dielectric constant (k) than silicon oxide. The terms “oxide,” “carbide,” “nitride,” etc. refer to compounds containing, respectively, oxygen, carbon, nitrogen, etc.

For convenience, if a collection of drawings designated with different letters are present, e.g., FIGS. 1A-1B, such a collection may be referred to herein without the letters, e.g., as “FIG. 1.”

FIGS. 1A-1B illustrate an example architecture of a nanoribbon-based transistor. FIG. 1A is a cross-section across a transistor 100 showing the source, gate, and drain. FIG. 1B is a cross-section across the gate regions of the transistor 100. FIG. 1B is a cross-section through the plane AA′ in FIG. 1A, and FIG. 1A is a cross-section through the plane BB′ in FIG. 1B.

A number of elements referred to in the description of FIGS. 1A, 1B, and 3-10, and with reference numerals are illustrated in these figures with different patterns, with a legend at the bottom of the page showing the correspondence between the reference numerals and patterns. The legend illustrates that FIGS. 1A and 1B use different patterns to show a support structure 102, a channel material 104, a dielectric material 106, a source or drain (S/D) region 108, a gate electrode 110, and a gate dielectric 112.

In the drawings, some example structures of various devices and assemblies described herein are shown with precise right angles and straight lines, but it is to be understood that such schematic illustrations may not reflect real-life process limitations which may cause the features to not look so “ideal” when any of the structures described herein are examined using e.g., scanning electron microscopy (SEM) images or transmission electron microscope (TEM) images. In such images of real structures, possible processing defects could also be visible, e.g., not-perfectly straight edges of materials, tapered vias or other openings, inadvertent rounding of corners or variations in thicknesses of different material layers, occasional screw, edge, or combination dislocations within the crystalline region, and/or occasional dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but that are common within the field of device fabrication.

In general, implementations of the present disclosure may be formed or carried out on a support structure, e.g., the support structure 102 illustrated in FIG. 1. The support structure 102 may be, e.g., a substrate, a die, a wafer or a chip. For example, the support structure may be the wafer 1500 of FIG. 15A, discussed below, and may be, or be included in, a die, e.g., the singulated die 1502 of FIG. 15B, discussed below. The support structure 102 extends along the x-y plane in the coordinate system shown in FIG. 1. In some embodiments, a support structure 102 may be used during a fabrication process and later removed. For example, a top side of the transistor 100 may be attached to a second support structure (e.g., a second one of the support structures 102, which may be referred to as a carrier structure), and the support structure 102 over which the transistor 100 is formed may be removed to expose the back side of the transistor 100.

In some embodiments, the support structure may be a substrate that includes silicon and/or hafnium. More generally, the support structure may be a semiconductor substrate composed of semiconductor material systems including, for example, N-type or P-type materials systems. In one implementation, the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator (SOI) substructure. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include, but are not limited to, germanium, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, aluminum gallium arsenide, aluminum arsenide, indium aluminum arsenide, aluminum indium antimonide, indium gallium arsenide, gallium nitride, indium gallium nitride, aluminum indium nitride or gallium antimonide, or other combinations of group III-V materials (i.e., materials from groups III and V of the periodic system of elements), group II-VI (i.e., materials from groups II and IV of the periodic system of elements), or group IV materials (i.e., materials from group IV of the periodic system of elements). In some embodiments, the substrate may be non-crystalline. In some embodiments, the support structure may be a printed circuit board (PCB) substrate. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which a semiconductor device including one or more nanoribbon transistors, as described herein, may be built falls within the spirit and scope of the present disclosure.

In FIGS. 1A and 1B, a transistor 100 is formed over a support structure 102. The transistor 100 includes a channel material 104 formed into four nanoribbons stacked on top of each other. In other examples, the transistor 100 may include more or fewer nanoribbons, e.g., one, two, three, five, six or more nanoribbons. The channel material 104 may be a semiconductor, such as silicon or other semiconductor materials described herein.

The transistor 100 includes nanoribbons 120a, 120b, 120c, and 120d, referred to collectively as nanoribbons 120 or individually as a nanoribbon 120. Each nanoribbon 120 is at a different height in the z-direction in the orientation shown in FIGS. 1A and 1B, i.e., a different distance from the support structure 102, where the nanoribbon 120a is the greatest distance from the support structure 102, and the nanoribbon 120d is the smallest distance from the support structure 102. S/D regions 108a and 108b are formed at either end of the nanoribbon channels 120, as illustrated in FIG. 1A.

In general, to form nanoribbon channels such as the nanoribbon channels 120, alternating layers of the channel material 104 and a sacrificial material are deposited over the support structure 102. The sacrificial material is removed from the stack and replaced with other material, e.g., material for forming a gate stack 116, so the sacrificial material is not shown in FIG. 1. The channel material 104 and sacrificial materials include different materials. In one example, the channel material 104 is silicon, while the sacrificial material includes silicon and germanium. The sacrificial material may be chosen to have a similar crystal structure to the channel material 104, so that monocrystalline layers of the channel material 104 (or substantially monocrystalline layers, e.g., with a grain size of at least 5 nanometers, at least 20 nanometers, at least 50 nanometers, or at least 100 nanometers) and monocrystalline layers of the sacrificial material (or substantially monocrystalline layers) may be formed over each other. In different embodiments, the channel material 104 and/or the sacrificial material may be formed of any suitable single-crystal material, such as sapphire, quartz, silicon, a compound of silicon (e.g., silicon oxide), indium phosphide, germanium or a germanium alloy (e.g., silicon germanium), gallium, arsenic (e.g., an arsenide III compound, where arsenic III is in combination with another element such as boron, aluminum, gallium, or indium), or any group III-V material (i.e., materials from groups III and V of the periodic system of elements).

In some embodiments, multiple channel materials may be included within an IC device. For example, an IC device may include both N-type metal-oxide-semiconductor (NMOS) transistors and P-type MOS (PMOS) transistors, e.g., alternating rows of NMOS and PMOS transistors. NMOS and PMOS logic can use different groups of channel material 104, e.g., silicon may be used to form an N-type semiconductor channel, while silicon germanium may be used to form a P-type semiconductor channel. In some embodiments, a single channel material 104 is used (e.g., silicon), and different portions (e.g., channel material to form different transistors) may include different dopants, e.g., N-type dopants for NMOS transistors and P-type dopants for PMOS transistors.

The S/D regions 108 may be formed from one or more layers of doped semiconductors, metals, metal alloys, or other materials. In some embodiments described herein, the S/D regions 108 may include a doped semiconductor, such as silicon or another semiconductor doped with an N-type dopant or a P-type dopant. In some embodiments, the S/D regions 108 may include multiple layers with different levels of conductivity, e.g., a doped semiconductor followed by a more highly doped semiconductor, or a semiconductor followed by metal.

A central portion of each of the nanoribbon channels 120 is surrounded by a gate stack 116, which in this example, includes a gate electrode 110 and gate dielectric 112. Nanoribbon transistors often include a gate dielectric that surrounds the nanoribbon channels 120, and a gate electrode that surrounds the gate dielectric. While not specifically shown, in some embodiments, the gate dielectric 112 around each nanoribbon channel 120 includes multiple layers, e.g., an oxide layer and a high-k dielectric layer. The oxide layer may be grown directly on the nanoribbon channels 120, and the high-k dielectric may surround the oxide. The oxide may include oxygen in combination with the channel material 104. For example, if the nanoribbon channels are formed from silicon, the gate dielectric 112 may include a layer of silicon oxide. The high-k dielectric may be formed over the oxide. The gate electrode 110 surrounds the gate dielectric 112, e.g., the high-k dielectric (if included). In this example, the gate electrode 110 is above and below the nanoribbon stack, and between adjacent nanoribbons 120.

The gate electrode 110 includes a conductive material, such as a metal. The gate electrode 110 may include at least one P-type work function metal or N-type work function metal, depending on whether the transistor 100 is a PMOS transistor or an NMOS transistor. For a PMOS transistor, metals that may be used for the gate electrode 110 may include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide). For an NMOS transistor, metals that may be used for the gate electrode 110 include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). In some embodiments, the gate electrode 110 may include a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer.

In various embodiments, the gate dielectric 112 may include one or more high-k dielectric materials and may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, the gate dielectric 112 may have a thickness between about 0.5 nanometers and 3 nanometers, including all values and ranges therein, e.g., between about 1 and 3 nanometers, or between about 1 and 2 nanometers.

Regions of the transistor 100 outside of the nanoribbons 120, gate stack 116, and S/D regions 108 are filled in with a dielectric material 106. In the region between the gate stack 116 and the S/D regions 108, the dielectric material 106 forms a series of cavity spacers. Cavity spacers, also referred to as “dimple spacers” or “inner spacers,” provide electrical isolation between the S/D regions 108 formed at the ends of the nanoribbons and the gate electrode 110 deposited around the nanoribbons 120.

FIG. 1 illustrates a single nanoribbon transistor 100. In IC devices, many similar or identical transistors are arranged within a transistor layer. The dielectric material 106 and/or different dielectric materials may provide isolation between different transistors, or between other conductive materials in or near the transistor layer. As described with respect to FIGS. 2-10, certain portions of isolation material within a transistor layer may be removed and replaced with air gaps, forming air gapped isolation walls. Air has a lower dielectric constant than typical dielectric materials, so including air gaps may reduce parasitic capacitance within the transistor layer.

Example Process for Forming Air Gaps with Recessed Oxide

FIG. 2 is a flow diagram of a first process 200 for fabricating a device with air gaps in the transistor layer, according to some embodiments of the present disclosure. The process 200 includes recessing an oxide layer below a height of vias extending through a transistor layer, so that a dielectric cap over the air gaps in the transistor layer are deposited below than the tops of the vias. This helps ensure that the air gaps in the transistor layer are sealed during further processing, e.g., fabrication of a front side metallization.

FIGS. 3-8 illustrate various steps in the processing method 200 of FIG. 2, according to some embodiments of the present disclosure. The processing method 200 can be performed across a wafer or die, with many individual transistors formed on the wafer or die. FIGS. 3-8 illustrate cross-sections of processing steps across several transistors. The processing method 200 describes a process of fabricating a device with air gaps in the transistor layer. Additional steps may be performed before, during, and/or after the process 200 to produce a device that includes the air gaps described herein.

At 202, a transistor layer with through-layer vias is provided. For example, a transistor layer including nanoribbon transistors 100 may be fabricated using known fabrication processes. The transistor layer may be formed over a support structure, such as the support structure 102. After forming the transistor layer, a front side metallization stack may be built up over the transistor layer, i.e., over a “front side” or top of the transistor layer. The front side metallization stack may include electrical connections to S/D regions and gate electrodes. After fabrication of the front side metallization stack, a carrier structure may be attached to the top or front of the front side metallization stack, and the assembly may be flipped, so that the support structure over which the transistor layer was formed is facing up. The support structure over which the transistor layer was formed is then removed, and the ends of vias that extend through the transistor layer are exposed. Alternatively, if the vias were not already in the transistor layer prior to flipping the assembly, vias may be formed that extend through the transistor layer and to a front side interconnect layer.

FIGS. 3A and 3B provide cross-sections of a portion of a transistor layer over a front side metallization stack, according to some embodiments of the present disclosure. FIG. 3B is a cross-section through the plane CC′ in FIG. 3A, illustrating the transistor layer and the front side metallization stack, and FIG. 3A is a cross-section through the plane DD′ in FIG. 3B, illustrating a cross-section through the transistor layer. More specifically, FIGS. 3A and 3B illustrate different cross-sections through four nanoribbon transistors 100a, 100b, 100c, and 100d. The nanoribbon transistors 100a-100d are examples of the nanoribbon transistor 100 described with respect to FIG. 1. FIG. 3A illustrates the nanoribbon transistors 100 in a cross-section through the gate stack 116 in the y-z plane, which corresponds to the cross-section shown in FIG. 1B. The nanoribbon transistors 100 may be formed as described with respect to FIG. 1. The nanoribbon transistors 100 are in a transistor layer 320, which may also be referred to as a device layer 320.

In the view shown in FIG. 3A, an oxide material 312 is directly over the nanoribbon transistors 100. The oxide material 312 forms oxide regions 332, e.g., the oxide region 332a over the transistor 100a, and the oxide region 332b over the transistor 100b. The oxide material 312 may be a dielectric material that includes oxygen. The oxide regions 332 may be formed prior to forming the nanoribbon transistors 100 or at a later time, e.g., after the back side of the transistor layer 320 is exposed. The oxide regions 332 may also be referred to as an oxide layer.

Furthermore, the nanoribbon transistors 100 are surrounded on their sides by a gate cut dielectric 302. FIG. 3B illustrates a gate line 350 that extends through the gate electrodes 110, gate dielectric 112, and the gate cut dielectric 302. FIG. 3B also illustrates the two S/D regions 108 on either side of the gate line 350. The channel material 104 of the nanoribbons extends through the gate electrode 110 and gate dielectric 112, and the channel material 104 extends between the S/D regions 108. While not illustrated in FIG. 3B, one or more other dielectric materials (e.g., the dielectric material 106) may fill other areas of the transistor layer 320 outside of the gate cut dielectric 302. Furthermore, in some cases, the gate cut dielectric 302 may be included outside of the gate area, e.g., the gate cut dielectric 302 can extend into or through areas around the S/D regions 108.

In some embodiments, the gate cut dielectric 302 is a high-k dielectric. In certain embodiments, the gate cut dielectric 302 includes nitrogen. The gate cut dielectric 302 may include silicon and nitrogen, e.g., silicon nitride. In other embodiments, the gate cut dielectric 302 may include one or more dielectric materials that may include, but are not limited to, elements such as hafnium, silicon, oxygen, nitrogen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Further examples of dielectric materials include, but are not limited to silicon oxide, silicon dioxide, silicon carbide, silicon nitride doped with carbon, silicon oxynitride, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate.

In the view shown in FIG. 3A, the transistor layer 320 is over (i.e., on top of) a front side metallization stack 322. The metallization stack 322 is over a support structure 102. The support structure 102 may be a carrier wafer that is coupled to the front side metallization stack 322 by a bonding layer 310. The carrier wafer may be bonded to the front side metallization stack 322 after fabrication of the front side metallization stack 322. The assembly (i.e., the transistor layer 320, front side metallization stack 322, bonding layer 310, and carrier wafer) may be flipped after bonding the carrier wafer, and a support structure over which the transistor layer 320 was formed may be removed, e.g., by grinding or polishing.

Each metal layer 324 includes conductive structures, including metal lines or trenches (e.g., the line 326) formed from a conductive material 308 and vias (e.g., the via 328) formed from the conductive material 308. The conductive material 308 may include one or more metals or metal alloys, with materials such as copper, ruthenium, palladium, platinum, cobalt, nickel, hafnium, zirconium, titanium, tantalum, and aluminum, tantalum nitride, tungsten, doped silicon, doped germanium, or alloys and mixtures of any of these. In some embodiments, the conductive material 308 may include one or more electrically conductive alloys, oxides, or carbides of one or more metals. While FIG. 3A illustrates the same conductive material 308 for the vias and the metal lines, at each metal layer, and for each type of interconnect, any suitable conductive material may be used. For example, in a given layer, the same conductive material may be used for both metal lines and vias, or different materials may be used for metal lines and vias. As another example, in different layers, different materials may be used for the metal lines and/or vias, e.g., ruthenium may be included in the metal lines in the metal layer 324a, while copper is included in the metal lines in the metal layer 324c. In various embodiments, conductive structures may include multiple conductive materials, e.g., a first metal as a liner, and a second metal as a fill.

The conductive material 308 may form conductive pathways to route power, ground, and/or signals to/from various components of the transistor layer 320. The arrangement of the conductive material 308 in the front side metallization stack 322 in FIG. 3A is merely illustrative, and the conductive pathways in the front side metallization stack 322 may be connected to one another in any suitable manner.

The metal lines and vias in the in the front side metallization stack 322 are surrounded by a dielectric material 306. The dielectric material 306 may be a low-k dielectric. The dielectric material 306 may include any of the materials described above with respect to the gate cut dielectric 302. In some embodiments, different dielectric materials may be included in different ones of the metal layers, e.g., the metal layer 324a may include a different dielectric material from the metal layer 324c. In some embodiments, multiple dielectric materials may be present in a given layer.

The assembly shown in FIGS. 3A and 3B further includes vias 330a and 330b (referred to jointly as vias 330) between certain pairs of adjacent gates. The vias 330 are formed within the gate cut regions and between adjacent gates. The vias 330 may be used for power and/or signal delivery between the back and front sides of the transistor layer 320, e.g., between the front side metallization stack 322 and a back side metallization stack formed later in the process.

In this example, the via 330a is between the gates of the transistors 100a and 100b, and the via 330b is between the gates of the transistors 100c and 100d. In this example, there is not a via between the gates of the transistors 100b and 100c; instead, the gate cut dielectric 302 fills the area between the gates of the transistors 100b and 100c. The vias 330 include a via material 304. The via material 304 may be a conductive material, such as a metal. Any of the conductive materials 308 described above may be used as or included in the via material 304.

The vias 330a and 330b are in the transistor layer 320, and, in the orientation shown, the vias 330 extend above the transistor layer 320. A top surface of the vias 330 (in the orientation shown) is level with, or coplanar with, a top surface of the oxide regions 332. The vias 330 extend downward to the front side metallization stack 322. The via 330b is over the via 328, and the via 330b is in electrical and physical contact with the via 328. To form the vias 330, a portion of the gate cut dielectric 302 may be patterned and etched, and the via material 304 is deposited in the etched regions. The vias 330 may be formed prior to filling the assembly shown in FIG. 3.

Returning to FIG. 2, at 204, a process to remove at least some of the gate cut dielectric is performed. The gate cut dielectric is etched from the exposed back side of the assembly, e.g., from the top of the assembly in the orientation of FIG. 3A. The etch chemistry may be highly selective to the gate cut dielectric 302 (e.g., silicon and/or nitrogen) so that other structures within the assembly are not removed or damaged by the etching process. For example, the oxide regions over the gate electrodes are left substantially intact. Removal of the gate cut dielectric forms air gaps within the transistor layer. The air gaps are created between adjacent gates and/or next to vias within the transistor layer, e.g., between a via and a gate. In some embodiments, the gate cut dielectric may be patterned, e.g., using a lithographic process, so that portions of the gate cut dielectric are removed while others are not.

FIG. 4 is a cross-section illustrating etching of portions of the gate cut dielectric, according to some embodiments of the present disclosure. The gate cut dielectric 402 is removed between the gate electrodes 110 of the four illustrated transistors, resulting in air gaps 410a and 410b on either side of the via 330a, air gaps 410c and 410d on either side of the via 330b, and the air gap 410e between the gates of the transistors 100b and 100c.

In FIG. 4, the oxide regions 332 have a thickness 430, which may also be referred to as a height 430. The height or thickness 430 is measured in the z-direction, e.g., parallel to the vias 330, and perpendicular to the nanoribbon channels 120 and the support structure 102, among other structures.

Returning to FIG. 2, at 206, a process to recess the oxide layer that is over the transistor layer is performed. An upper portion of the oxide layer over the transistors (e.g., over the gates) in the flipped orientation (e.g., the orientation shown in FIGS. 3A and 4) is removed, e.g., using an etching process. The heights of the vias are unchanged, so that, after the recessing, the top of the oxide layer is below the top ends of the vias. The etch chemistry for recessing the oxide layer is selective to the via material. In some embodiments, the orders of the processes 204 and 206 are swapped, i.e., the oxide layer is recessed prior to removal of the gate cut dielectric.

FIG. 5 is a cross-section illustrating recessing of an oxide layer to expose ends of the gate cut vias, according to some embodiments of the present disclosure. The oxide regions 332 have been etched from the top, reducing their heights or thicknesses and resulting in the recessed oxide regions 520, e.g., the recessed oxide regions 520a and 520b, also referred to as the recessed oxide layer 520. After the recessing process, the recessed oxide layer 520 has a height or thickness 530, which is less than the initial height 430 of the oxide regions 332 shown in FIG. 4. The recessing process exposes a top section 510a and 510b of the vias 330a and 330b. The top sections 510 of the vias have a height 512, where the height 530 plus the height 512 are equal to the height 430. The height 512 corresponds to the amount of the oxide layer 332 that was removed.

The height 512 may be, for example, between 5 and 100 nanometers (nm) or a range therein, e.g., at least 5 nm, at least 10 nm, at least 20 nm, at least 25 nm, at least 30 nm, at least 50 nm, etc. In some embodiments, the height 512 is between 10 and 25 nm, between 15 or 35 nm, or between 20 and 50 nm.

The height 530 may be, for example, between 5 and 100 nanometers (nm) or a range therein, e.g., at least 5 nm, at least 10 nm, at least 20 nm, at least 25 nm, at least 30 nm, at least 50 nm, etc. In some embodiments, the height 530 is between 10 and 30 nm, or between 20 and 50 nm. In some embodiments, most or all of the oxide regions 520 are removed, and the height 530 may be 5 nm or less, e.g., below 5 nm, below 2 nm, or zero (if the oxide layer 520 is fully removed).

Returning to FIG. 2, at 208, a process to deposit a dielectric over the oxide and the air gaps is performed. The dielectric layer may cover the air gaps formed in the process 204. Specifically, the dielectric material is deposited such that the dielectric material covers, but does not fill, the air gaps. The dielectric material may be deposited some distance into the air gaps, but at least a portion of each air gap remains after the dielectric deposition. In some embodiments, the air gaps extend slightly into the dielectric material, e.g., above the top surface of the oxide layer, but below the top surface of the vias. In some embodiments, a physical vapor deposition (PVD) or chemical vapor deposition (CVD) process may be used to deposit the dielectric material.

FIG. 6 is a cross-section illustrating deposition of a dielectric over the oxide and the air gaps, according to some embodiments of the present disclosure. A dielectric material 602 is deposited over the recessed oxide layer 520, air gaps 410, and vias 330. The dielectric material 602 has a height 610 that is greater than the height 512, so that the dielectric material 602 is deposited over the vias 330. While the upper surface of the dielectric material 602 is flat, in some cases, the upper surface of the dielectric material 602 may have bumps over the vias 330 or other nonuniformities. The dielectric material 602 may include, for example, silicon and oxygen. The dielectric material 602 may include additional or alternative materials, including any of the materials described with respect to the gate cut dielectric 302.

In the view shown in FIG. 5, the lower surface of the dielectric material 602 extends flat over the air gaps 410, so that the dielectric material 602 does not extend into the air gaps 410, nor do the air gaps 410 extend into the layer of dielectric material 602. In other examples, the air gaps 410 may extend into the dielectric material 602, or the dielectric material 602 may extend into the air gaps 410. An example where a small amount of the dielectric material 602 is deposited within the air gaps 410 is illustrated in FIG. 8B.

Returning to FIG. 2, at 210, the ends of the vias are exposed, e.g., by polishing the dielectric material deposited over the oxide regions 520, air gaps 410, and vias 330. The dielectric material that filled the top portion of the air gaps remains, capping the air gaps 410.

FIG. 7 is a cross-section illustrating exposure, or reveal, of the vias 330 that extend through the transistor layer 320, according to some embodiments of the present disclosure. At least the portion of the dielectric material 602 that extended upward from the tops of the vias 330 has been removed, exposing the upper surfaces of the vias 330a and 330b. A layer 710 of the dielectric material 602 remains over the air gaps 410 and recessed oxide regions 520. The layer 710 of dielectric material 602 over the air gaps 410 forms caps over the air gaps 410.

The layer 710 of the dielectric material 602 that remains has a height 712. The height 712 may be equal to or, in some cases, less than the height 512 of the top portions 510 of the vias 330. In some embodiments, the polishing process removes some amount of the top portions 510 of the vias 330, but less than the height 512 of the top portions 510 of the vias 330. The height 712 may be, for example, between 5 and 100 nm or a range therein, e.g., at least 5 nm, at least 10 nm, at least 20 nm, at least 25 nm, at least 30 nm, at least 50 nm, etc. In some embodiments, the height 712 is between 10 and 25 nm, between 15 or 35 nm, or between 20 and 50 nm. In this example, an interface between the air gaps 410 and the layer 710 of the dielectric material 602 is above an upper surface of the gates 110, and below an upper surface of the vias 330, in the orientation shown.

Returning to FIG. 2, at 212, back side metallization is formed over the back side of the transistor layer, and over the capped air gaps. The back side metallization may be formed in a similar manner to the front side metallization. The back side metallization may include electrical connections to at least a portion of the vias that extend through the transistor layer.

FIG. 8A is a cross-section illustrating back side interconnect layers over the capped air gaps, according to some embodiments of the present disclosure. FIG. 8A includes a back side metallization stack 822. In this example, the back side metallization stack 822 includes two back side metal layers 824a and 824b. The metal layer 824a is the nearest metal layer to the transistor layer 320, and the metal layer 824b is the farthest metal layer from the transistor layer 320. While two metal layers 824a and 824b are illustrated in FIG. 8A, an IC device may have fewer or more back side metal layers, e.g., up to 5 metal layers, up to 10 metal layers, up to 15 metal layers, or more.

Each back side metal layer 824 includes conductive structures, including metal lines or trenches formed from a conductive material 308 and vias formed from the conductive material 308. While FIG. 8A illustrates the same conductive material 308 for the vias and the metal lines within the back side metallization stack 822 that were included in the front side metallization stack 322, any suitable conductive material may be used, as described with respect to the front side metallization stack 322. Similarly, while the metal lines and vias in the in the back side metallization stack 822 are surrounded by the dielectric material 306, any suitable dielectric material or combination of dielectric materials may be used.

In the back side metallization stack 822, as with the front side metallization stack 322, the conductive material 308 may form conductive pathways to route power, ground, and/or signals to/from various components of the transistor layer 320. The arrangement of the conductive material 308 in the back side metallization stack 822 in FIG. 8A is merely illustrative, and the conductive pathways in the back side metallization stack 822 may be connected to one another in any suitable manner.

In this example, the via 330b that extends through the transistor layer 320 is coupled to the via 826 in the back side metallization stack 822. This connection may provide power delivery from the back side of the IC device, through the back side metallization stack 822, into the via 826, through the via 330b, and to the front side metallization stack 322 by way of the via 328. In this example, a portion of the via 826 is over the layer 710 of the dielectric material 602 and over the air gap 410d; the dielectric material 602 prevents the conductive material 308 from the via 826 from entering the air gap 410d.

FIG. 8B is an enlarged view of a portion 800 of FIG. 8A. FIG. 8B more clearly shows a pair of air gaps 410a and 410b around the via 330a. The air gap 410a is between the gate electrode 110a of the transistor 100a and the via 330a, and the air gap 410b is between the gate electrode 110b of the transistor 100b and the via 330a. The air gaps 410a and 410b also extend into the recessed oxide layer 520. For example, an upper portion of the air gap 410 is between the recessed oxide region 520a and the via 330a.

The air gaps 410 provide isolation walls between conductive components, e.g., the via 330a and the gate electrode 110a. The via 330a has an upper surface 830 that is above an upper surface 832a of the gate 110a and above an upper surface 832b of the gate 110b. The upper surface 830 of the via 330a is also above the tops of the air gaps 410, i.e., at an interface between the air gaps 410 and the layer 710 of the dielectric material 602. The upper surface 830 of the via 330a is above the upper surface of the recessed oxide layer 520, e.g., the recessed oxide regions 520a and 520b. The upper surface 830 of the via 330a is coplanar (i.e., at the same position in the z-direction) with the upper surface 836 of the layer 710.

In the example shown in FIG. 8B, the gate electrodes 110a and 110b and via 330a form the sides of the air gaps 410a and 410b, and the dielectric material in the front side metallization stack 322 forms the base of the air gaps 410a and 410b. In other embodiments, a portion of the gate cut dielectric 302 remains after etching the air gaps 410 in the process 204, and a dielectric liner formed from the gate cut dielectric 302 is along the base and/or sides of the air gaps. An example of this is described with respect to FIGS. 9-14.

As noted above, in some cases, a small amount of the dielectric material 602 may be present below the layer 710, e.g., along the sides of the air gaps 410. In the example shown in FIG. 8B, near the tops of the air gaps 410a and 410b, the dielectric material 602 extends into the tops of the air gaps, along the sides of the recessed oxide regions 520 and/or the vias 330. For example, a region 840 of dielectric material 602 is along the side of the recessed oxide region 520a.

Example Process for Forming Air Gaps with Seam-First Dielectric Etch

FIG. 9 is a flow diagram of a second process for fabricating a device with air gaps in the transistor layer, according to some embodiments of the present disclosure. In process 900, when the gate cut dielectric is etched to form the air gaps, the seam is etched first, and the gate cut dielectric is then widened outward from the seam.

FIGS. 10-14 illustrate various steps in the processing method 900 of FIG. 9, according to some embodiments of the present disclosure. The processing method 900 can be performed across a wafer or die, with many individual transistors formed on the wafer or die. FIGS. 9-14 illustrate cross-sections of processing steps across several transistors. The processing method 900 describes a process of fabricating a device with air gaps in the transistor layer. Additional steps may be performed before, during, and/or after the process 900 to produce a device that includes the air gaps described herein.

At 902, a transistor layer with through-layer vias is provided. For example, a transistor layer including nanoribbon transistors 100 may be fabricated using known fabrication processes. The fabrication of the transistor layer and front side metallization stack may be similar to the process 202, described above.

FIGS. 10A and 10B provide cross-sections of a portion of a transistor layer over a front side metallization stack, according to some embodiments of the present disclosure. FIG. 10B is a cross-section through the plane EE′ in FIG. 10A, illustrating the transistor layer and the front side metallization stack, and FIG. 10A is a cross-section through the plane FF′ in FIG. 10B, illustrating a cross-section through the transistor layer. As with FIGS. 3A and 3B, FIGS. 10A and 10B illustrate different cross-sections through four nanoribbon transistors 100a, 100b, 100c, and 100d. FIG. 10A illustrates the nanoribbon transistors 100 in a cross-section through the gate stack 116 in the y-z plane, which corresponds to the cross-section shown in FIG. 1B. The nanoribbon transistors 100 may be formed as described with respect to FIG. 1. The nanoribbon transistors 100 are in a transistor layer 1020, which may also be referred to as a device layer 1020.

The oxide material 312 is directly over the nanoribbon transistors 100. The oxide material 312 forms oxide regions 1032 or an oxide layer 1032, including the oxide region 1032a over the transistor 100a, and the oxide region 1032b over the transistor 100b, similar to the oxide regions 332 of FIG. 3.

The nanoribbon transistors 100 are surrounded on their sides by the gate cut dielectric 302. FIG. 10B illustrates a gate line 1050 that extends through the gate electrodes 110, gate dielectric 112, and the gate cut dielectric 302. FIG. 10B also illustrates the two S/D regions 108 on either side of the gate line 350. The channel material 104 of the nanoribbons extends through the gate electrode 110 and gate dielectric 112, and the channel material 104 extends between the S/D regions 108. While not illustrated in FIG. 10B, one or more other dielectric materials (e.g., the dielectric material 106) may fill other areas of the transistor layer 320 outside of the gate cut dielectric 302.

In the view shown in FIG. 10A, the transistor layer 1020 is over (i.e., on top of) a front side metallization stack 1022, which is similar to the front side metallization stack 322. The metallization stack 1022 is over a support structure 102, e.g., a carrier wafer that is coupled to the front side metallization stack 1022 by a bonding layer 310, as described with respect to FIG. 3.

A via 1030 between the gates of the transistors 100c and 100d. The via 1030 is similar to the vias 330 described above. The assembly shown in FIGS. 10A and 10B further includes the gate cut dielectric 302 between the gates of the transistors 100a and 100b and between the gates of the transistors 100b and 100c. The gate cut dielectric 302 is in the gate cut dielectric regions 1040a (between the gates of the transistors 100a and 100b), 1040b (between the gates of the transistors 100b and 100c), 1040c (between the gate of the transistors 100c and the via 1030), and 1040d (between the gate of the transistors 100d and the via 1030). The gate cut dielectric regions 1040a and 1040b have a 1042a or 1042b down the center of the respective gate cut region dielectric 1040. The seams 1042a and 1042b extend vertically, in the z-direction of the example coordinate system. In this example, the gate cut dielectric regions 1040c and 1040d on either side of the via 1030 do not have a seam; a seam of this gate cut dielectric region may have been removed to form the via 1030.

The gate cut dielectric regions 1040 have different widths, where width is measured in the y-direction in the coordinate system shown. Because of the via 1030, the gate cut dielectric regions 1040c and 1040d are narrower than the gate cut dielectric regions 1040a and 1040b, which extend between adjacent gates. Furthermore, the gate cut dielectric region 1040b has a greater width than the gate cut dielectric region 1040a. The widths 1044a and 1044b of the gate cut dielectric regions 1040a and 1040b, which also correspond to the distances between adjacent gates, are illustrated in FIG. 10B.

Returning to FIG. 9, at 904, a process to etch a seam within the gate cut dielectric is performed. The gate cut dielectric is etched from the exposed back side of the assembly, e.g., from the top of the assembly in the orientation of FIG. 10A. As described with respect to FIG. 2, the etch chemistry may be highly selective to the gate cut dielectric 302 (e.g., silicon and/or nitrogen) so that other structures within the assembly are not removed or damaged by the etching process. For example, the oxide regions over the gate electrodes are left substantially intact. In addition, the etching process is well controlled, e.g., removing thin layers, which helps preserve the gates and other materials in the assembly. The etching process may first remove the seams of the gate cut dielectric, and then further etching may expand the air gaps outwards from the etched seams. For example, at a first stage of the etch or a first stage of a multi-step etch process, relatively narrow openings are formed along the seams. The openings may extend through the height of the gate cut dielectric.

FIG. 11 is a cross-section illustrating etching of the seams of the gate cut dielectric, according to some embodiments of the present disclosure. Portions of the gate cut dielectric regions 1040a and 1040b directly at and around the seams 1042a and 1042b have been removed, forming air gaps 1140a and 1140b. The air gaps 1140a and 1140b extend through the transistor layer 1020, to the upper surface of the front side metallization stack 1022. In this example, the gate cut dielectric regions 1040c and 1040d, which do not have seams, have not been etched, but instead, remain on either side of the via 1030.

Returning to FIG. 9, at 906, the openings formed at the seams of the gate cut dielectric are widened. The etching process of 904 may be continued, or additional etching steps of a multi-step etch process may be performed. FIG. 12 is a cross-section illustrating further widening of the openings shown in FIG. 11, according to some embodiments of the present disclosure. Further portions of the gate cut dielectric regions 1040a and 1040b around the openings 1140a and 1140b have been removed, forming widened air gaps 1240a and 1240b. In this example, in addition to widening the openings 1140a and 1140b around the seams, a portion of the gate cut dielectric regions 1040a and 1040b is etched downward from an upper surface of the gate cut dielectric regions 1040a and 1040b. In this example, the gate cut dielectric regions 1040c and 1040d have still not been etched. In some cases, the seam-first etching process may result in seams, and regions that have seams, being etched, while regions without seams remain largely intact. In other embodiments, the gate cut dielectric regions 1040c and 1040d may be etched in the process 904 and/or 906, resulting in an air gap or partial air gap, e.g., as shown in FIGS. 3-8.

At 908, a process to deposit a dielectric layer over the oxide and the air gaps and to expose the ends of the vias is performed. In some embodiments, the oxide may be recessed, as described with respect to FIGS. 2 and 5. The dielectric layer covers the air gaps formed in the processes 204 and 206. The dielectric may be deposited and then polished in the manner described with respect to FIGS. 2, 6, and 7.

FIG. 13 is a cross-section illustrating deposition of a dielectric over the oxide and the air gaps and polishing of the dielectric, according to some embodiments of the present disclosure. In this example, the oxide material 312 is recessed relative to the via 1030, as described with respect to FIGS. 2 and 6. The oxide material 312 and the top surface of the remaining gate cut dielectric 302 may be even, as depicted, or one of the oxide material 312 and gate cut dielectric 302 may be higher in the z-direction in the orientation shown than the other.

A layer 1310 of the dielectric material 602 is deposited over the oxide material 312, air gaps 1240a and 1240b, the gate cut dielectric regions 1040c and 1040d. The dielectric material 602 may have been deposited over the via 1030 and then polished to expose the top surface of the via 1030, as described with respect to FIGS. 2 and 7. The layer 1310 of the dielectric material 602 forms caps over the air gaps 1240a and 1240. The sides of the air gaps 1240a and 1240b are formed by the gate cut dielectric 302, and the bases of the air gaps 1240a and 1240b are formed by the front side metallization stack 1022.

In the view shown in FIG. 13, the lower surface of the dielectric material 602 extends flat over the air gaps 1240a and 1240b, so that the dielectric material 602 does not extend into the air gaps, nor do the air gaps extend into the layer of dielectric material 602. As described with respect to FIG. 6, in other examples, the air gaps 1240a and 1240b may extend into the dielectric material 602, or the dielectric material 602 may extend into the air gaps 1240a and 1240b, e.g., as shown in FIG. 8B.

Returning to FIG. 9, at 910, back side metallization is formed over the back side of the transistor layer, and over the capped air gaps. The back side metallization may be formed in a similar manner to the front side metallization. The back side metallization may include electrical connections to at least a portion of the vias that extend through the transistor layer.

FIG. 14A is a cross-section illustrating back side interconnect layers over the capped air gaps, according to some embodiments of the present disclosure. FIG. 14A includes a back side metallization stack 1422, which is similar to the back side metallization stack 822, described above. FIGS. 10-14A illustrate an example, embodiment that includes a via 1030. In other embodiments, the air gaps with seam-first dielectric etch (e.g., the air gaps 1240a and 1240b) may be formed in a gate cut region that does not include vias such as the via 1030. In other embodiments, air gaps with a seam-first dielectric etch may be formed in regions other than a gate cut region, e.g., between adjacent S/D regions of adjacent transistors. In such embodiments, the dielectric material 302 may not be a gate cut dielectric, but rather, a different dielectric material (e.g., the dielectric material 106).

FIG. 14B is an enlarged view of a portion 1400 of FIG. 14A. FIG. 14B more clearly shows a pair of air gaps 1240a and 1240b. The air gap 1240a is between the gates 110a and 110b of the transistors 100a and 100b, and the air gap 1240b is between the gates 110b and 110c of the transistors 100b and 100c.

FIG. 14B includes the dielectric material 306 of the front side metallization stack 1022 below the transistor layer 1020, and specifically, below the air gaps 1240. After the etching process, layers 1410 of the gate cut dielectric 302 are along the sides of the gate electrodes 110. In particular, the layer 1410 a of the gate cut dielectric 302 is along a right side of the gate electrode 110a; the layer 1410b of the gate cut dielectric 302 is along a left side of the gate electrode 110b; the layer 1410c of the gate cut dielectric 302 is along a right side of the gate electrode 110b, which is opposite the left side of the gate electrode 110b; and the layer 1410c of the gate cut dielectric 302 is along the left side of the gate electrode 110c.

The air gaps 1240 are between pairs of the layers 1410 of the gate cut dielectric 302. The air gap 1240a is between the layers 1410a and 1410b, and the air gap 1240b is between the layers 1410c and 1410d. The air gaps 1240 extend downward through the transistor layer 1020 and to the front side metallization stack 1022.

FIG. 14B illustrates widths, measured in the y-direction in the coordinate system shown, of the layers 1410 and the air gaps 1240. Each air gap 1240a and 1240b has a respective width 1440a and 1440b, and each layer 1410a, 1410b, 1410c, and 1410d has a respective width 1430a, 1430b, 1430c, and 1430d. The widths 1440a and 1440b of the air gaps 1240a and 1240b may be substantially the same, e.g., within a certain tolerance, such as 50%, 30%, 20%, 10%, 5%, or another tolerance. As used herein, as an example tolerance, a 20% tolerance means a difference between one width (e.g., 1440a) is within 20% of another width (e.g., 1440b). The widths 1440a and 1440b may be in a range of, for example, 5-50 nm or a range therein, e.g., between 5 and 15 nm, between 10 and 20 nm, between 15 and 30 nm, etc.

The widths 1430a and 1430b of the layers 1410 on either side of the air gap 1240a may be substantially the same, e.g., within a certain tolerance, such as 50%, 30%, 20%, 10%, 5%, or another tolerance. Likewise, the widths 1430c and 1430d on either side of the air gap 1240b may be substantially the same, e.g., within a certain tolerance, such as 50%, 30%, 20%, 10%, 5%, or another tolerance. This is because the seams 1040 are typically near a central line of a given dielectric region 1040, so the air gaps 1240 are etched from the centers of the dielectric regions 1040. The widths 1430 may be in a range of, for example, 0.5-10 nm or a range therein, e.g., between 0.5 and 2 nm, between 1 and 2 nm, between 2 and 5 nm, etc.

The widths of the layers 1410 next to different air gaps 1240 may be different, as illustrated in FIG. 14B. In this example, the widths 1430a and 1430b are substantially the same as each other, but are different from the widths 1430c and 1430d; the widths 1430d and 1430c are greater than the widths 1430a and 1430b. As noted with respect to FIG. 10, the gate cut dielectric region 1040b has a greater width 1044b than the width 1044a of the gate cut dielectric region 1040a. This results in the widths 1430a and 1430b of the layers 1410a and 1410b of the remaining gate cut dielectric 302 around the air gap 1240a being smaller than the widths 1430c and 1430d of the layers 1410c and 1410d of the remaining gate cut dielectric 302 around the air gap 1240b.

Example Devices

The circuit devices with transistor layers with air gapped isolation walls disclosed herein may be included in any suitable electronic device. FIGS. 15-18 illustrate various examples of apparatuses that may include the one or more transistors disclosed herein, which may have been fabricated using the processes disclosed herein.

FIGS. 15A and 15B are top views of a wafer and dies that include one or more IC structures including one or more transistor layers with air gapped isolation walls in accordance with any of the embodiments disclosed herein. The wafer 1500 may be composed of semiconductor material and may include one or more dies 1502 having IC structures formed on a surface of the wafer 1500. Each of the dies 1502 may be a repeating unit of a semiconductor product that includes any suitable IC structure (e.g., the IC structures as shown in any of FIGS. 2-14, or any further embodiments of the IC structures described herein). After the fabrication of the semiconductor product is complete (e.g., after manufacture of one or more IC structures with one or more of the transistors as described herein, included in a particular electronic component, e.g., in a transistor or in a memory device), the wafer 1500 may undergo a singulation process in which each of the dies 1502 is separated from one another to provide discrete “chips” of the semiconductor product. In particular, devices that include one or more of the transistors as disclosed herein may take the form of the wafer 1500 (e.g., not singulated) or the form of the die 1502 (e.g., singulated). The die 1502 may include one or more transistors (e.g., one or more of the transistors 1640 of FIG. 16, discussed below) and/or supporting circuitry to route electrical signals to the transistors, as well as any other IC components (e.g., one or more of the non-planar transistors described herein). In some embodiments, the wafer 1500 or the die 1502 may include a memory device (e.g., an SRAM device), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die 1502. For example, a memory array formed by multiple memory devices may be formed on a same die 1502 as a processing device (e.g., the processing device 1802 of FIG. 18) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

FIG. 16 is a cross-sectional side view of an IC device 1600 that may include one or more transistor layers with air gapped isolation walls in accordance with any of the embodiments disclosed herein. The IC device 1600 may be formed on a substrate 1602 (e.g., the wafer 1500 of FIG. 15A) and may be included in a die (e.g., the die 1502 of FIG. 15B). The substrate 1602 may be any substrate as described herein. The substrate 1602 may be part of a singulated die (e.g., the dies 1502 of FIG. 15B) or a wafer (e.g., the wafer 1500 of FIG. 15A).

The IC device 1600 may include one or more device layers 1604 disposed on the substrate 1602. The device layer 1604 may include features of one or more transistors 1640 (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)) formed on the substrate 1602. The device layer 1604 may include, for example, one or more source and/or drain (S/D) regions 1620, a gate 1622 to control current flow in the transistors 1640 between the S/D regions 1620, and one or more S/D contacts 1624 to route electrical signals to/from the S/D regions 1620. The transistors 1640 may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors 1640 are not limited to the type and configuration depicted in FIG. 16 and may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include FinFET transistors, such as double-gate transistors or tri-gate transistors, and wrap-around or all-around gate transistors, such as nanoribbon and nanowire transistors.

Each transistor 1640 may include a gate 1622 formed of at least two layers, a gate electrode layer and a gate dielectric layer.

The gate electrode layer may be formed on the gate interconnect support layer and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor, respectively. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer or/and an adhesion layer.

An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV.

In some embodiments, when viewed as a cross-section of the transistor 1640 along the source-channel-drain direction, the gate electrode may be formed as a U-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In other embodiments, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In other embodiments, the gate electrode may be implemented as a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may be implemented as one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers. In some embodiments, the gate electrode may consist of a V-shaped structure (e.g., when a fin of a FinFET transistor does not have a “flat” upper surface, but instead has a rounded peak).

The IC device 1600 may include one or more transistor layers with air gapped isolation walls at any suitable location in the IC device 1600.

The S/D regions 1620 may be formed within the substrate 1602 adjacent to the gate 1622 of each transistor 1640, using any suitable processes known in the art. For example, the S/D regions 1620 may be formed using either an implantation/diffusion process or a deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate 1602 to form the S/D regions 1620. An annealing process that activates the dopants and causes them to diffuse farther into the substrate 1602 may follow the ion implantation process. In the latter process, an epitaxial deposition process may provide material that is used to fabricate the S/D regions 1620. In some implementations, the S/D regions 1620 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D regions 1620 may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions 1620. In some embodiments, an etch process may be performed before the epitaxial deposition to create recesses in the substrate 1602 in which the material for the S/D regions 1620 is deposited.

Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the transistors 1640 of the device layer 1604 through one or more interconnect layers disposed on the device layer 1604 (illustrated in FIG. 16 as interconnect layers 1606-1610). For example, electrically conductive features of the device layer 1604 (e.g., the gate 1622 and the S/D contacts 1624) may be electrically coupled with the interconnect structures 1628 of the interconnect layers 1606-1610. The one or more interconnect layers 1606-1610 may form an ILD stack 1619 of the IC device 1600.

The interconnect structures 1628 may be arranged within the interconnect layers 1606-1610 to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures 1628 depicted in FIG. 16). Although a particular number of interconnect layers 1606-1610 is depicted in FIG. 16, embodiments of the present disclosure include IC devices having more or fewer interconnect layers than depicted.

In some embodiments, the interconnect structures 1628 may include trench contact structures 1628a (sometimes referred to as “lines”) and/or via structures 1628b (sometimes referred to as “holes”) filled with an electrically conductive material such as a metal. The trench contact structures 1628a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the substrate 1602 upon which the device layer 1604 is formed. For example, the trench contact structures 1628a may route electrical signals in a direction in and out of the page from the perspective of FIG. 16. The via structures 1628b may be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the substrate 1602 upon which the device layer 1604 is formed. In some embodiments, the via structures 1628b may electrically couple trench contact structures 1628a of different interconnect layers 1606-1610 together.

The interconnect layers 1606-1610 may include a dielectric material 1626 disposed between the interconnect structures 1628, as shown in FIG. 16. The dielectric material 1626 may take the form of any of the embodiments of the dielectric material provided between the interconnects of the IC structures disclosed herein.

In some embodiments, the dielectric material 1626 disposed between the interconnect structures 1628 in different ones of the interconnect layers 1606-1610 may have different compositions. In other embodiments, the composition of the dielectric material 1626 between different interconnect layers 1606-1610 may be the same.

A first interconnect layer 1606 (referred to as Metal 1 or “M1”) may be formed directly on the device layer 1604. In some embodiments, the first interconnect layer 1606 may include trench contact structures 1628a and/or via structures 1628b, as shown. The trench contact structures 1628a of the first interconnect layer 1606 may be coupled with contacts (e.g., the S/D contacts 1624) of the device layer 1604.

A second interconnect layer 1608 (referred to as Metal 2 or “M2”) may be formed directly on the first interconnect layer 1606. In some embodiments, the second interconnect layer 1608 may include via structures 1628b to couple the trench contact structures 1628a of the second interconnect layer 1608 with the trench contact structures 1628a of the first interconnect layer 1606. Although the trench contact structures 1628a and the via structures 1628b are structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer 1608) for the sake of clarity, the trench contact structures 1628a and the via structures 1628b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments.

A third interconnect layer 1610 (referred to as Metal 3 or “M3”) (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 1608 according to similar techniques and configurations described in connection with the second interconnect layer 1608 or the first interconnect layer 1606.

The IC device 1600 may include a solder resist material 1634 (e.g., polyimide or similar material) and one or more bond pads 1636 formed on the interconnect layers 1606-1610. The bond pads 1636 may be electrically coupled with the interconnect structures 1628 and configured to route the electrical signals of the transistor(s) 1640 to other external devices. For example, solder bonds may be formed on the one or more bond pads 1636 to mechanically and/or electrically couple a chip including the IC device 1600 with another component (e.g., a circuit board). The IC device 1600 may have other alternative configurations to route the electrical signals from the interconnect layers 1606-1610 than depicted in other embodiments. For example, the bond pads 1636 may be replaced by or may further include other analogous features (e.g., posts) that route the electrical signals to external components.

FIG. 17 is a cross-sectional side view of an IC device assembly 1700 that may include components having or being associated with (e.g., being electrically connected by means of) one or more transistor layers with air gapped isolation walls in accordance with any of the embodiments disclosed herein. The IC device assembly 1700 includes a number of components disposed on a circuit board 1702 (which may be, e.g., a motherboard). The IC device assembly 1700 includes components disposed on a first face 1740 of the circuit board 1702 and an opposing second face 1742 of the circuit board 1702; generally, components may be disposed on one or both faces 1740 and 1742. In particular, any suitable ones of the components of the IC device assembly 1700 may include one or more of the non-planar transistors disclosed herein.

In some embodiments, the circuit board 1702 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 1702. In other embodiments, the circuit board 1702 may be a non-PCB substrate.

The IC device assembly 1700 illustrated in FIG. 17 includes a package-on-interposer structure 1736 coupled to the first face 1740 of the circuit board 1702 by coupling components 1716. The coupling components 1716 may electrically and mechanically couple the package-on-interposer structure 1736 to the circuit board 1702 and may include solder balls (as shown in FIG. 17), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

The package-on-interposer structure 1736 may include an IC package 1720 coupled to an interposer 1704 by coupling components 1718. The coupling components 1718 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 1716. Although a single IC package 1720 is shown in FIG. 17, multiple IC packages may be coupled to the interposer 1704; indeed, additional interposers may be coupled to the interposer 1704. The interposer 1704 may provide an intervening substrate used to bridge the circuit board 1702 and the IC package 1720. The IC package 1720 may be or include, for example, a die (the die 1502 of FIG. 15B), an IC device (e.g., the IC device 1600 of FIG. 16), or any other suitable component. In some embodiments, the IC package 1720 may include one or more transistor layers with air gapped isolation walls, as described herein. Generally, the interposer 1704 may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer 1704 may couple the IC package 1720 (e.g., a die) to a ball grid array (BGA) of the coupling components 1716 for coupling to the circuit board 1702. In the embodiment illustrated in FIG. 17, the IC package 1720 and the circuit board 1702 are attached to opposing sides of the interposer 1704; in other embodiments, the IC package 1720 and the circuit board 1702 may be attached to a same side of the interposer 1704. In some embodiments, three or more components may be interconnected by way of the interposer 1704.

The interposer 1704 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer 1704 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer 1704 may include metal interconnects 1708 and vias 1710, including but not limited to TSVs 1706. The interposer 1704 may further include embedded devices 1714, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 1704. The package-on-interposer structure 1736 may take the form of any of the package-on-interposer structures known in the art.

The IC device assembly 1700 may include an IC package 1724 coupled to the first face 1740 of the circuit board 1702 by coupling components 1722. The coupling components 1722 may take the form of any of the embodiments discussed above with reference to the coupling components 1716, and the IC package 1724 may take the form of any of the embodiments discussed above with reference to the IC package 1720.

The IC device assembly 1700 illustrated in FIG. 17 includes a package-on-package structure 1734 coupled to the second face 1742 of the circuit board 1702 by coupling components 1728. The package-on-package structure 1734 may include an IC package 1726 and an IC package 1732 coupled together by coupling components 1730 such that the IC package 1726 is disposed between the circuit board 1702 and the IC package 1732. The coupling components 1728 and 1730 may take the form of any of the embodiments of the coupling components 1716 discussed above, and the IC packages 1726 and 1732 may take the form of any of the embodiments of the IC package 1720 discussed above. The package-on-package structure 1734 may be configured in accordance with any of the package-on-package structures known in the art.

FIG. 18 is a block diagram of an example computing device 1800 that may include one or more transistor layers with air gapped isolation walls in accordance with any of the embodiments disclosed herein. For example, any suitable ones of the components of the computing device 1800 may include a die (e.g., the die 1502 (FIG. 15B)) having one or more transistor layers with air gapped isolation walls. Any one or more of the components of the computing device 1800 may include, or be included in, an IC device 1600 (FIG. 16). Any one or more of the components of the computing device 1800 may include, or be included in, an IC device assembly 1700 (FIG. 17).

A number of components are illustrated in FIG. 18 as included in the computing device 1800, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the computing device 1800 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die.

Additionally, in various embodiments, the computing device 1800 may not include one or more of the components illustrated in FIG. 18, but the computing device 1800 may include interface circuitry for coupling to the one or more components. For example, the computing device 1800 may not include a display device 1812, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 1812 may be coupled. In another set of examples, the computing device 1800 may not include an audio input device 1816 or an audio output device 1814, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 1816 or audio output device 1814 may be coupled.

In some embodiments, the communication chip 1806 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 1806 may include multiple communication chips. For instance, a first communication chip 1806 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 1806 may be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 1806 may be dedicated to wireless communications, and a second communication chip 1806 may be dedicated to wired communications.

The computing device 1800 may include a battery/power circuitry 1810. The battery/power circuitry 1810 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the computing device 1800 to an energy source separate from the computing device 1800 (e.g., AC line power).

The computing device 1800 may include a display device 1812 (or corresponding interface circuitry, as discussed above). The display device 1812 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.

The computing device 1800 may include an audio output device 1814 (or corresponding interface circuitry, as discussed above). The audio output device 1814 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.

The computing device 1800 may include an audio input device 1816 (or corresponding interface circuitry, as discussed above). The audio input device 1816 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).

The computing device 1800 may include another output device 1818 (or corresponding interface circuitry, as discussed above). Examples of the other output device 1818 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

The computing device 1800 may include another input device 1820 (or corresponding interface circuitry, as discussed above). Examples of the other input device 1820 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

The computing device 1800 may include a global positioning system (GPS) device 1822 (or corresponding interface circuitry, as discussed above). The GPS device 1822 may be in communication with a satellite-based system and may receive a location of the computing device 1800, as known in the art.

The computing device 1800 may include a security interface device 1824. The security interface device 1824 may include any device that provides security features for the computing device 1800 or for any individual components therein (e.g., for the processing device 1802 or for the memory 1804). Examples of security features may include authorization, access to digital certificates, access to items in keychains, etc. Examples of the security interface device 1824 may include a software firewall, a hardware firewall, an antivirus, a content filtering device, or an intrusion detection device.

Select Examples

Example 1 provides an integrated circuit (IC) device including a device layer including a first transistor including a first gate; and a second transistor including a second gate, the first gate and the second gate arranged along a gate line; a first dielectric layer over the device layer; a second dielectric layer over the first dielectric layer; a conductive structure between the first gate and the second gate, the conductive structure extending through the device layer, the first dielectric layer, and the second dielectric layer; and an air gap between the conductive structure and the first gate, where the air gap is under the second dielectric layer.

Example 2 provides the IC device of example 1, where the air gap is between the conductive structure and at least a portion of the first dielectric layer.

Example 3 provides the IC device of any preceding example, where the air gap is a first air gap, the IC device further including a second air gap between the conductive structure and the second gate, where the second air gap is under the second dielectric layer.

Example 4 provides the IC device of any preceding example, where the conductive structure has an upper surface higher than an upper surface of the first dielectric layer.

Example 5 provides the IC device of any preceding example, where the conductive structure has an upper surface that is level with an upper surface of the second dielectric layer.

Example 6 provides the IC device of any preceding example, where the first dielectric layer includes oxygen.

Example 7 provides the IC device of any preceding example, further including a third transistor including a third gate, the third transistor arranged along the gate line, and the third transistor adjacent to the second transistor; and a second air gap between the second gate and the third gate, where the second air gap is under the second dielectric layer.

Example 8 provides the IC device of example 7, where the second air gap extends into the first dielectric layer.

Example 9 provides the IC device of any preceding example, where the conductive structure is a first conductive structure, the IC device further including a second conductive structure having a base that is in contact with the first conductive structure, and the base of the second conductive structure is coplanar with an upper surface of the second dielectric layer.

Example 10 provides an integrated circuit (IC) device including a first layer including a dielectric material; and a second layer over the first layer, the second layer including a first transistor including a first gate; a second transistor including a second gate, the first gate and the second gate arranged along a gate line; a first dielectric layer along a side of the first gate, the first dielectric layer perpendicular to the first layer and to the second layer; a second dielectric layer along a side of the second gate, the second dielectric layer perpendicular to the first layer and to the second layer; and an air gap between the first dielectric layer and the second dielectric layer, the air gap extending through the second layer to an upper surface of the first layer.

Example 11 provides the IC device of example 10, where the first layer is an interconnect layer including a plurality of conductive structures in the dielectric material.

Example 12 provides the IC device of example 10 or 11, where a thickness of the first dielectric layer between the first gate and the air gap is between 1 and 2 nanometers.

Example 13 provides the IC device of example 12, where a thickness of the second dielectric layer between the second gate and the air gap is between 1 and 2 nanometers.

Example 14 provides the IC device of example 13, where the thickness of the first dielectric layer is within 20% of the thickness of the second dielectric layer.

Example 15 provides the IC device of any of examples 10 through 14, where the air gap is a first air gap, the side of the second gate is a first side of the second gate, and the IC device further includes a third transistor including a third gate, the third transistor arranged along the gate line, and the third transistor adjacent to the second transistor; a third dielectric layer along a second side of the second gate, the second side opposite the first side of the second gate; a fourth dielectric layer along a side of the third gate; and a second air gap between the third dielectric layer and the fourth dielectric layer.

Example 16 provides the IC device of example 15, where a first width of the first air gap between the first dielectric layer and the second dielectric layer is substantially the same as a second width of the second air gap between the third dielectric layer and the fourth dielectric layer.

Example 17 provides the IC device of example 15 or 16, where a thickness of the second dielectric layer is less than a thickness of the third dielectric layer.

Example 18 provides the IC device of any of examples 15 through 17, where a first distance between the first gate and the second gate is less than a second distance between the second gate and the third gate.

Example 19 provides an integrated circuit (IC) device including forming a first gate and a second gate; forming a conductive structure between the first gate and the second gate, the conductive structure having a greater height than the first gate and the second gate; forming an oxide layer over the gates, where an upper surface of the conductive structure extends above an upper surface of the oxide layer; forming an air gap between the first gate and the conductive structure; and forming a dielectric layer over the oxide layer and the air gap.

Example 20 provides the IC device of example 19, where forming the oxide layer over the gates includes forming the oxide layer with a first thickness; and removing a portion of the oxide layer to achieve a second thickness less than the first thickness.

Example 21 provides an IC package that includes an IC die, including one or more of the IC devices according to any one of the preceding examples. The IC package may also include a further component, coupled to the IC die.

Example 22 provides the IC package according to example 21, where the further component is one of a package substrate, a flexible substrate, or an interposer.

Example 23 provides the IC package according to examples 21 or 22, where the further component is coupled to the IC die via one or more first level interconnects.

Example 24 provides the IC package according to example 23, where the one or more first level interconnects include one or more solder bumps, solder posts, or bond wires.

Example 25 provides a computing device that includes a circuit board; and an IC die coupled to the circuit board, where the IC die includes one or more of the transistor/IC devices according to any one of the preceding examples (e.g., transistor/IC devices according to any one of examples 1-20), and/or the IC die is included in the IC package according to any one of the preceding examples (e.g., the IC package according to any one of examples 21-24).

Example 26 provides the computing device according to example 25, where the computing device is a wearable computing device (e.g., a smart watch) or hand-held computing device (e.g., a mobile phone).

Example 27 provides the computing device according to examples 25 or 26, where the computing device is a server processor.

Example 28 provides the computing device according to examples 25 or 26, where the computing device is a motherboard.

Example 29 provides the computing device according to any one of examples 25-28, where the computing device further includes one or more communication chips and an antenna.