Buffer circuit with reduced static leakage through controlled body biasing in FDSOI technology

A buffer includes an input configured to receive a first digital signal having first and second logic states referenced, respectively, to a first high voltage and a first low voltage of a first supply domain. A first inverter circuit includes a pMOS transistor and nMOS transistor having gate terminals connected to the input. A second inverter is connected in series with the output of the first inverter. The second inverter has an output configured to generate a second digital signal having first and second logic states referenced, respectively, to a second high voltage and a second low voltage of a second, different, supply domain, wherein at least the second high voltage is greater than the first high voltage. A feedback circuit is configured to apply the second digital signal as a bias to a transistor body of the p-MOS transistor of the first inverter circuit.

FIELD OF THE INVENTION

The present disclosure generally relates buffer circuits and, more particularly, to a buffer circuit with reduced static leakage.

BACKGROUND

Reference is made toFIG. 1which illustrates a prior art buffer circuit10comprising a pair of series connected CMOS inverters12. Each inverter12is formed of a p-channel MOSFET (pMOS)14having a source-drain path coupled in series with the source-drain path of an n-channel MOSFET (nMOS)16. More particularly, the source terminal and transistor body (bulk or well) of the pMOS transistor14are coupled to a high supply node18and the source terminal and body (bulk or well) of the nMOS transistor16are coupled to a low supply node20. The high and low supply nodes18and20, respectively, receive high and low supply voltages associated with a supply voltage domain. For example, the high supply voltage, referred to as Vdd, may comprise 1.8 Volts and the low supply voltage, referred to as ground, may comprise 0 Volts. The gate terminals of the pMOS transistor14and nMOS transistor16are coupled together at an inverter input node22. The drain terminals of the pMOS transistor14and nMOS transistor16are coupled together at an inverter output node24. With the series connection of the CMOS inverters12, the inverter output node24of a first one of the inverters is coupled to the inverter input node22of a second one of the inverters.

The operation of the inverters12is well known to those skilled in the art. In response to a logic high signal at the inverter input node22, the pMOS transistor14is turned off and the nMOS transistor16is turned on. The inverter output node24is accordingly coupled to the low supply node20and the inverter outputs a logic low signal. Conversely, in response to a logic low signal at the inverter input node22, the pMOS transistor14is turned on and the nMOS transistor16is turned off. The inverter output node24is accordingly coupled to the high supply node18and the inverter outputs a logic high signal. The back-to-back inversions provided by the series connected inverters12provide a signal buffering operation with the input signal IN and output signal OUT having a same logic state.

It is common for the supply range of the input signal IN to be the same as the supply range of the supply voltage domain for the circuit10. In such scenarios, static leakage of the circuit10is well within specifications at all times because one of the pull up transistor or pull down transistor of each inverter will be completely turned off.

However, certain circumstances exist where the supply range of the input signal IN may be different from the supply range of the supply voltage domain for the circuit10. A common situation is a buffering operation with respect to an input signal whose supply range is less than the supply range of the circuit10. In such a scenario, there is a significant increase in static leakage because the logic high voltage of the input signal (at 1.2V, for example) is not sufficiently high enough to fully turn off the pMOS transistor14(referenced to Vdd=1.8V. for example).

To address the static leakage issue, a commonly used design solution is to reduce the strength of the pMOS transistor14. This unfortunately has an adverse effect on the switching speed of the buffer circuit10. Such a circuit would be suitable only for low speed applications. For high speed applications, another solution is needed.

There is accordingly a need in the art for a buffer circuit with reduced static current leakage which is suitable for high speed applications.

SUMMARY

In an embodiment, a circuit comprises: a first system including a drive circuit configured to generate a first digital signal having a first logic state and a second logic state referenced, respectively, to a first high voltage and a first low voltage of a first supply domain; a second system including a buffer circuit configured to receive the first digital signal and generate a second digital signal having a first logic state and a second logic state referenced, respectively, to a second high voltage and a second low voltage of a second supply domain; wherein the second high voltage is greater than the first high voltage, The buffer circuit comprises: a first inverter circuit including a p-channel MOSFET having a gate terminal configured to receive the first digital signal and a transistor body; a second inverter having an input coupled to an output of the first inverter circuit and having an output configured to generate the second digital signal; and a feedback circuit configured to apply the signal digital signal as a bias to the transistor body of the p-channel MOSFET of the first inverter circuit.

In an embodiment, a circuit comprises: a fully depleted silicon on insulator (FDSOI) substrate; a first inverter circuit implemented on said FDSOI substrate and including: a p-channel MOSFET having a gate terminal configured to receive a first digital signal and further having a transistor body; and an n-channel MOSFET having a gate terminal configured to receive the first digital signal and further having a transistor body connected to a source terminal of the n-channel MOSFET; a second inverter implemented on said FDSOI substrate and having an input coupled to an output of the first inverter circuit and having an output configured to generate a second digital signal; and a feedback circuit configured to apply the second digital signal as a bias to the transistor body of the p-channel MOSFET of the first inverter circuit.

In an embodiment, a circuit comprises: an input line configured to receive a first digital signal having a first logic state and a second logic state referenced, respectively, to a first high voltage and a first low voltage of a first supply domain; a first inverter circuit including: a p-channel MOSFET having a gate terminal connected to the input line, a source-drain path and a transistor body; and an n-channel MOSFET having a gate terminal connected to the input line, a source-drain path coupled in series with the source-drain path of the p-channel MOSFET and a transistor body connected to a source terminal of the n-channel MOSFET; a second inverter having an input coupled to an output of the first inverter circuit and having an output configured to generate a second digital signal having a first logic state and a second logic state referenced, respectively, to a second high voltage and a second low voltage of a second supply domain different from the first supply domain; an output line connected to the output of the second inverter; and a feedback circuit configured to apply the second digital signal as a bias to the transistor body of the p-channel MOSFET of the first inverter circuit.

The foregoing and other features and advantages of the present disclosure will become further apparent from the following detailed description of the embodiments, read in conjunction with the accompanying drawings. The detailed description and drawings are merely illustrative of the disclosure, rather than limiting the scope of the invention as defined by the appended claims and equivalents thereof.

DETAILED DESCRIPTION OF THE DRAWINGS

Those skilled in the art are familiar with integrated circuits fabricated using fully depleted silicon on insulator (FDSOI) substrates.FIG. 2illustrates a cross-section of an exemplary transistor implemented using an FDSOI substrate. Such substrates include a bottom support substrate, for example made of silicon, with an insulating layer, for example made of an oxide material, over the support substrate, and with a semiconductor layer over the oxide layer. The insulating layer is typically very thin and is often referred to as a buried oxide layer. The semiconductor layer is also very thin and is used to form the body, source, drain and channel regions of integrated transistor devices. The channel region in an FDSOI device differs from the channel region in conventional bulk transistor technologies in that there are no dopants present in the semiconductor material (i.e., it is fully depleted). The active region can be defined using trench isolation structures which penetrate through the semiconductor and buried oxide layers. Dopant implants for source and drain regions are then provided in the semiconductor layer. A gate stack (with gate conductor, gate dielectric and sidewall spacers) is provided over the fully depleted channel region. Although not shown inFIG. 2, the integrated circuit will further include a premetal dielectric layer over the FDSOI substrate with contacts passing there through for making electrical contact to the gate, body, source and drain regions. Further overlying metallization layers contain electric lines and vias for making electrical connections to and between the contacts.

Reference is now made toFIG. 3which illustrates a circuit diagram of a buffer circuit100in accordance with an embodiment. The buffer circuit100comprises a pair of series connected inverters112. In a preferred embodiment, each inverter112is a CMOS inverter formed of a p-channel MOSFET (pMOS)114having a source-drain path coupled in series with the source-drain path of an n-channel MOSFET (nMOS)116. The transistors112and114are fabricated using a fully depleted silicon on insulator (FDSOI) substrate of the type described above and are implemented in a manner, for example, like that shown inFIG. 2. Thus, the source, drain, channel and body regions are provided in the fully depleted semiconductor layer and the active regions of the transistors are isolated from each other by the trench isolation structures.

The first inverter112(1) is configured with the source terminal of its pMOS transistor114coupled to a high supply node118and the source terminal and transistor body of its nMOS transistor116coupled to a low supply node120. The gate terminals of the pMOS transistor114and nMOS transistor116are coupled together at a first inverter input node122(1) to receive a digital input signal N. The drain terminals of the pMOS transistor114and nMOS transistor116are coupled together at a first inverter output node124(1) to generate an inverted digital signal INV.

The second inverter112(2) is configured with the source terminal and transistor body of its pMOS transistor114coupled to the high supply node118and the source terminal and transistor body of its nMOS transistor116coupled to the low supply node120. The gate terminals of the pMOS transistor114and nMOS transistor116are coupled together at a second inverter input node122(2) to receive the inverted digital signal INV from the first inverter output node124(1). The drain terminals of the pMOS transistor114and nMOS transistor116are coupled together at a second inverter output node124(2) to generate an output digital signal OUT.

The transistor body of the pMOS transistor114of the first inverter112(1) is coupled to the second inverter output node124(2) via a feedback path126to pass a digital bias signal (BIAS) having a logic state and voltage level equal to the digital output signal OUT.

The high and low supply nodes118and120, respectively, receive high and low supply voltages associated with a supply voltage domain. For example, the high supply voltage, which may be referred to as Vdd, may comprise 1.8 Volts and the low supply voltage, which may be referred to as ground, may comprise 0 Volts. Alternatively, the high supply voltage may be set at +Vdd and the low supply voltage may be set at —Vdd or some other reference voltage Vss. The inverted digital signal INV and the output digital signal OUT accordingly having logic states defined by the high and low supply voltages, respectively.

The circuit ofFIG. 3is advantageously implemented to provide for reduced static current operation in operating scenarios where the input digital signal IN is provided with reference to a different voltage domain than the supply voltage domain for the buffer100. This circuit configuration is illustrated inFIG. 4. For example, the input digital signal IN may be generated in a first system150by a drive circuit154which has a voltage domain (supply range) referenced to a signal high voltage (Vdd1) for a logic 1 state and a signal low voltage (ground) for a logic 0 state, while the buffer100is provided in a second system152which has a voltage domain (supply range) referenced to a high supply voltage (Vdd2), that is greater than the signal high voltage (Vdd1), and a low supply voltage (ground). Thus, the input digital signal IN has logic states defined by the signal high and signal low voltages, respectively, with at least the high supply voltage (Vdd2) and signal high voltage (Vdd1) being different. For example, in an embodiment, the high supply voltage Vdd2may be 1.8 Volts and the signal high voltage Vdd1may be 1.2 Volts.

In this operating scenario, when the input digital signal IN rises to logic high at voltage 1.2V, this gate voltage on the pMOS transistor114of the first inverter112(1) may be sufficient to flip the logic state of the first inverter112(1) (and cause a further flip of the logic state of the second inverter112(2)) but is insufficient, by itself, to fully turn off the pMOS transistor114whose source voltage is at the high supply voltage Vdd2of 1.8 Volts. A leakage current could thus flow through the partially on pMOS transistor114of the first inverter112(1) and the fully on nMOS transistor116of the second inverter112(2). The output signal OUT, however, will be driven to logic high at the high supply voltage Vdd2by the fully on pMOS transistor114of the second inverter112(2). The digital BIAS signal, which equals the output digital signal OUT at the logic high state voltage Vdd2, is passed in the feedback path126from the second inverter output node124(2) for application to the transistor body of the pMOS transistor114of the first inverter112(1). The application of the high supply voltage Vdd2to the transistor body of the pMOS transistor114of the first inverter112(1) is sufficient to ensure that the pMOS transistor114is fully turned off More specifically, the application of the BIAS signal at logic high (1.8V) causes an increase in the threshold voltage Vt of the transistor114of the first inverter112(1). The change in the threshold voltage Vt results in a reduction of leakage current through transistor114of the first inverter112(1).

In comparison to the operation of the circuit ofFIG. 1, the circuit ofFIG. 3exhibits a 90+% reduction in static leakage.

The first and second systems150and152may be located on a same integrated circuit chip, for example as operating domains of a system on chip supporting different supply domains. Alternatively, the first and second systems150and152may be located on different integrated circuit chips, for example as different components with different power supply domains that are interconnected with each other in a system.

Although two inverter circuits are illustrated for the buffer100, it will be understood that the buffer may include more than two inverter circuits. In an embodiment, the buffer100may include n inverter circuits, wherein n is preferably an even integer greater than or equal to 2. Where n is greater than 2, the feedback bias signal BIAS should preferably be taken at the output of the second inverter is the series chain of n inverters, but it is noted that the feedback bias signal could alternatively be taken from the output of any included even-numbered inverter.

Although the output signal OUT is shown as being taken at the output of the second inverter, it will be understood than an inverting buffer circuit may be implemented with the output signal OUT instead being taken as the inverted signal INV.

Although the second inverter112(2) is shown as a CMOS inverter, it will be understood that the second inverter112(2) may alternatively comprise any suitable inverter circuitry and the illustration and use of a CMOS inverter is exemplary only.

In an embodiment, the pMOS transistor114may have a W=10u and L=150u, and the nMOS116may have a W=5u and L=150u.

It will be understood that the reference to a 1.2V domain and a 1.8V domain is exemplary only. Without limitation, it will be understood that that the circuit presented herein is useful when the voltage domain (supply range) for the first system150has a logic high voltage which is less than the logic high voltage of the voltage domain (supply range) for the second system152. As another example, the voltage domain (supply range) for the first system150may have a logic high voltage at 1.8V and the voltage domain (supply range) for the second system152may have a logic high voltage of 2.5V.