N-type metal oxide semiconductor (NMOS) transistor for electrostatic discharge (ESD)

One or more techniques or systems for forming an n-type metal oxide semiconductor (NMOS) transistor for electrostatic discharge (ESD) are provided herein. In some embodiments, the NMOS transistor includes a first region, a first n-type plus (NP) region, a first p-type plus (PP) region, a second NP region, a second PP region, a shallow trench isolation (STI) region, and a gate stack. In some embodiments, the first PP region is between the first NP region and the second NP region. In some embodiments, the second NP region is between the first PP region and the second PP region, the gate stack is between the first PP region and the second NP region, the STI region is between the second NP region and the second PP region. Accordingly, the first PP region enables ESD current to discharge based on a low trigger voltage for the NMOS transistor.

BACKGROUND

Generally, an n-type metal oxide semiconductor (NMOS) transistor is used in electrostatic discharge (ESD) circuitry. For example, an NMOS ESD transistor generally comprises an implant. It will be appreciated that an implant is generally associated with an additional fabrication procedure, such as a mask, for example.

SUMMARY

This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to be an extensive overview of the claimed subject matter, identify key factors or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

One or more techniques or systems for forming an n-type metal oxide semiconductor (NMOS) transistor for electrostatic discharge (ESD) are provided herein. Generally, NMOS transistors used in ESD circuitry requires an implant. However, in some embodiments, an NMOS transistor for ESD does not comprise an implant. For example, the NMOS transistor comprises a first region, a first n-type plus (NP) region, a first p-type plus (PP) region, a second NP region, a second PP region, a shallow trench isolation (STI) region, and a gate stack. In some embodiments, at least some of at least one of the first NP region, the first PP region, the second NP region, the second PP region, the STI region, or the gate stack is above at least some of the first region. In some embodiments, the first PP region is between the first NP region and the second NP region. In some embodiments, the second NP region is between the first PP region and the second PP region. In some embodiments, the gate stack is between the first PP region and the second NP region. In some embodiments, the STI region is between the second NP region and the second PP region. Accordingly, the first PP region facilitates a reduction of a trigger voltage associated with the NMOS transistor, thereby enabling the NMOS transistor to be triggered earlier during an ESD event, for example. Additionally, the first PP region facilitates an increase in a holding voltage associated with the NMOS transistor, thereby enabling the NMOS transistor to remain non-operational during normal operation of a circuit, for example.

The following description and annexed drawings set forth certain illustrative aspects and implementations. These are indicative of but a few of the various ways in which one or more aspects are employed. Other aspects, advantages, or novel features of the disclosure will become apparent from the following detailed description when considered in conjunction with the annexed drawings.

DETAILED DESCRIPTION

Embodiments or examples, illustrated in the drawings are disclosed below using specific language. It will nevertheless be understood that the embodiments or examples are not intended to be limiting. Any alterations and modifications in the disclosed embodiments, and any further applications of the principles disclosed in this document are contemplated as would normally occur to one of ordinary skill in the pertinent art.

It will be appreciated that ‘layer’, as used herein, contemplates a region, and does not necessarily comprise a uniform thickness. For example, a layer is a region, such as an area comprising arbitrary boundaries. For another example, a layer is a region comprising at least some variation in thickness. Additionally a stack, such as a gate stack comprises one or more regions, according to some embodiments. It will be appreciated that ‘between’, as used herein, contemplates no overlap of regions in some scenarios, and at least some overlap of regions in other scenarios.

As used herein, the “+” symbol or a plus region is indicative of strong doping associated with a conductivity type. For example, N+ is indicative of a strongly doped N type region. Conversely, the “−” symbol or a minus region is indicative of weak doping associated with a conductivity type. For example, P− is indicative of a weakly doped P type region.

It will be appreciated that for at least some of the figures herein, one or more boundaries, such as boundary110ofFIG. 3orFIG. 4, for example, are drawn with different heights, widths, perimeters, aspect ratios, etc. relative to one another merely for illustrative purposes, and are not necessarily drawn to scale. For example, because dashed or dotted lines are used to represent different boundaries, if the dashed and dotted lines were drawn on top of one another they would not be distinguishable in the figures, and thus are drawn slightly apart from one another, in at least some of the figures, so that they are distinguishable from one another, for example. As another example, because a component is associated with an irregular shape, such as the first region110, a box drawn with a dashed line, dotted lined, etc. does not necessarily encompass an entire component. For example, one or more portions of110are not encompassed by the dashed or dotted line associated with110ofFIG. 3orFIG. 4. Similarly, a drawn box does not necessarily encompass merely the associated component, but encompasses at least some of one or more other components as well, in some embodiments. For example, one or more portions of other regions are encompassed by the dashed or dotted line associated with110ofFIG. 3orFIG. 4. Accordingly, dimensions of some of these boundaries are drawn taller, shorter, wider, narrower, etc. than needed in some embodiments so that the different boundaries are visible in the figures, for example.

FIG. 1is a cross-sectional view100of an example n-type metal oxide semiconductor (NMOS) transistor for electrostatic discharge (ESD), according to some embodiments. In some embodiments, the NMOS transistor comprises a first region110, a first n-type plus (NP) region120, a first p-type plus (PP) region130, a second NP region140, a second PP region150, an epitaxy block region152, a gate stack164, and a shallow trench isolation (STI) region160. In some embodiments, at least some of at least one of the first NP region120, the first PP region130, the second NP region140, the second PP region150, the epitaxy block region152, the gate stack164, or the shallow trench isolation (STI) region160is above at least some of the first region110. In some embodiments, the first region110comprises a p-type well (PW) region. In some embodiments, the first region110comprises silicon.

In some embodiments, the first PP region130is between the first NP region120and the second NP region140. In some embodiments, the second NP region140is between the first PP region130and the second PP region150. In some embodiments, the gate stack164is between the first PP region130and the second NP region150. In some embodiments, the STI region160is between the second NP region140and the second PP region150. In some embodiments, the epitaxy block region152is between the first NP region120and the first PP region130. In some embodiments, the first PP region130is between the epitaxy block region152and the gate stack164. In some embodiments, the second NP region140is between the gate stack164and the STI region160. In some embodiments, at least some of at least one of the first NP region120, the first PP region130, the second NP region140, the second PP region150, the epitaxy block region152, or the shallow trench isolation (STI) region160are flush with at least one of a surface of the NMOS transistor or one another. In some embodiments, the epitaxy block region152is configured to mitigate leakage, at least because the epitaxy block region152comprises resist protective oxide (RPO), for example.

In some embodiments, the first NP region120is associated with a collector of an NMOS transistor. In some embodiments, the second NP region140is associated with an emitter of an NMOS transistor. In some embodiments, the second PP region150is associated with a base of an NMOS transistor.

In some embodiments, the NMOS transistor ofFIG. 1is formed in association with at least one of a FinFET (field effect transistor) process or a planar process. It will be appreciated that the NMOS transistor ofFIG. 1does not comprise an implant. Accordingly, the NMOS is not associated with additional processing required for implants, such as an additional mask, for example. In some embodiments, the first PP region130is configured to reduce a trigger voltage associated with the NMOS, at least because the first PP region130is part of a p-n junction that facilitates activation of the NMOS transistor. Additionally, it will be appreciated that a holding voltage associated with the NMOS transistor is increased, thus mitigating activation of the NMOS transistor during normal circuit operation, for example. In some embodiments, the holding voltage is increased at least due to a high doping concentration of the first PP region130associated with a path of current flow. In some embodiments, a latch up (LU) immunity is increased at least because the holding voltage is increased. Additionally, a capacitance associated with the NMOS is mitigated, at least because the first PP region130is not an implant region, for example. It will be appreciated that the trigger voltage associated with the NMOS ofFIG. 1is tunable based on the structure, for example.

In some embodiments, ESD discharge current flows from the first NP region120to the first region110, to the first PP region130, to the first region110, to the second NP region140. In some embodiments, the ESD discharge current flows from the first NP region120to the first region110, to the second NP region140.

FIG. 2is a cross-sectional view200of an example n-type metal oxide semiconductor (NMOS) transistor for electrostatic discharge (ESD), according to some embodiments. It will be appreciated that the NMOS transistor ofFIG. 2is similar to the NMOS transistor ofFIG. 1, except that the NMOS transistor ofFIG. 2comprises a dummy gate stack162. In some embodiments, at least some of the dummy gate stack162is above at least some of the first region110. In some embodiments, the dummy gate stack162is between the first NP region120and the first PP region130. In some embodiments, the first PP region130is between the dummy gate stack162and the gate stack164. In some embodiments, at least some of at least one of the first NP region120, the first PP region130, the second NP region140, the second PP region150, or the shallow trench isolation (STI) region160are flush with at least one of a surface of the NMOS transistor or one another. In some embodiments, the dummy gate stack162and the gate stack164are at least one of flush with one another or associated with a similar height, for example. In some embodiments, the dummy gate stack162comprises RPO.

FIG. 3is a cross-sectional view300of an example n-type metal oxide semiconductor (NMOS) transistor for electrostatic discharge (ESD), according to some embodiments. It will be appreciated that the NMOS transistor ofFIG. 3is similar to the NMOS transistor ofFIG. 1, except that the first region110of the NMOS transistor ofFIG. 3comprises one or more regions. For example, the first region110ofFIG. 3comprises a first native NMOS blocked implant (NTN) region102, a second NTN region104, and a p-type well (PW) region106. In some embodiments, the PW region106is between the first NTN region102and the second NTN region104. In some embodiments, at least some of at least one of the first NP region120, the epitaxy block region152, or the first PP region130is above at least some of the first NTN region102. In some embodiments, at least some of at least one of the first PP region130, the gate stack164, the second NP region140, or the STI region160is above at least some of the PW region106. In some embodiments, at least some of at least one of the STI region160or the second PP region150is above at least some of the second NTN region104.

In some embodiments, the first PP region130is between the first NP region120and the second NP region140. In some embodiments, the second NP region140is between the first PP region130and the second PP region150. In some embodiments, the gate stack164is between the first PP region130and the second NP region150. In some embodiments, the STI region160is between the second NP region140and the second PP region150. In some embodiments, the epitaxy block region152is between the first NP region120and the first PP region130. In some embodiments, the first PP region130is between the epitaxy block region152and the gate stack164. In some embodiments, the second NP region140is between the gate stack164and the STI region160. In some embodiments, at least some of at least one of the first NP region120, the first PP region130, the second NP region140, the second PP region150, the epitaxy block region152, or the shallow trench isolation (STI) region160are flush with at least one of a surface of the NMOS transistor or one another.

In some embodiments, ESD discharge current flows from the first NP region120to the first NTN region102, to the first PP region130, to the PW region106, to the second NP region140. In other embodiments, the ESD discharge current flows from the first NP region120to the first NTN region102, to the PW region106, to the second NP region140.

FIG. 4is a cross-sectional view400of an example n-type metal oxide semiconductor (NMOS) transistor for electrostatic discharge (ESD), according to some embodiments. It will be appreciated that the NMOS transistor ofFIG. 4is similar to the NMOS transistor ofFIG. 3, except that the NMOS transistor ofFIG. 4comprises a dummy gate stack162. In some embodiments, at least some of the dummy gate stack162is above at least some of the first NTN region102. In some embodiments, the dummy gate stack162is between the first NP region120and the first PP region130. In some embodiments, the first PP region130is between the dummy gate stack162and the gate stack164. In some embodiments, at least some of at least one of the first NP region120, the first PP region130, the second NP region140, the second PP region150, or the shallow trench isolation (STI) region160are flush with at least one of a surface of the NMOS transistor or one another. In some embodiments, the dummy gate stack162and the gate stack164are at least one of flush with one another or associated with a similar height, for example.

FIG. 5is a flow diagram of an example method500for forming an n-type metal oxide semiconductor (NMOS) transistor for electrostatic discharge (ESD), according to some embodiments. In some embodiments, the method500comprises forming a first region at502. Additionally, a first NP region, a first PP region, a second NP region, a second PP region, an STI region, or a gate stack are formed above the first region at502. At504, the method500comprises forming the first PP region between the first NP region and the second NP region. Additionally, the method500comprises forming the second NP region between the first PP region and the second PP region at504. In some embodiments, the method500comprises forming a gate stack between the first PP region and the second NP region. In some embodiments, the method500comprises forming the STI region between the second NP region and the second PP region.

According to some aspects, an n-type metal oxide semiconductor (NMOS) transistor for electrostatic discharge (ESD) is provided, comprising a first region. In some embodiments, the NMOS transistor comprises a first n-type plus (NP) region above at least some of the first region. In some embodiments, the NMOS transistor comprises a first p-type plus (PP) region above at least some of the first region. In some embodiments, the NMOS transistor comprises a second NP region above at least some of the first region. In some embodiments, the NMOS transistor comprises a second PP region above at least some of the first region. In some embodiments, the NMOS transistor comprises a shallow trench isolation (STI) region above at least some of the first region. In some embodiments, the NMOS transistor comprises a gate stack above at least some of the first region. In some embodiments, the first PP region is between the first NP region and the second NP region. In some embodiments, the second NP region is between the first PP region and the second PP region. In some embodiments, the gate stack is between the first PP region and the second NP region. In some embodiments, the STI region is between the second NP region and the second PP region.

According to some aspects, an n-type metal oxide semiconductor (NMOS) transistor for electrostatic discharge (ESD) is provided, comprising a first region comprising a p-type well (PW) region, a first native NMOS blocked implant (NTN) region, and a second NTN region. In some embodiments, the NMOS transistor comprises a first n-type plus (NP) region above at least some of the first NTN region. In some embodiments, the NMOS transistor comprises a first p-type plus (PP) region above at least some of at least one of the first NTN region or the PW region. In some embodiments, the NMOS transistor comprises a second NP region above at least some of the PW region. In some embodiments, the NMOS transistor comprises a second PP region above at least some of the second NTN region. In some embodiments, the NMOS transistor comprises a shallow trench isolation (STI) region above at least some of at least one of the PW region or the second NTN region. In some embodiments, the NMOS transistor comprises a gate stack above at least some of the PW region. In some embodiments, the first PP region is between the first NP region and the second NP region. In some embodiments, the second NP region is between the first PP region and the second PP region. In some embodiments, the gate stack is between the first PP region and the second NP region. In some embodiments, the STI region is between the second NP region and the second PP region.

According to some aspects, an n-type metal oxide semiconductor (NMOS) transistor for electrostatic discharge (ESD) is provided, comprising a first region. In some embodiments, the NMOS transistor comprises a first n-type plus (NP) region above at least some of the first region. In some embodiments, the NMOS transistor comprises a first p-type plus (PP) region above at least some of the first region. In some embodiments, the NMOS transistor comprises a second NP region above at least some of the first region. In some embodiments, the NMOS transistor comprises a second PP region above at least some of the first region. In some embodiments, the NMOS transistor comprises a shallow trench isolation (STI) region above at least some of the first region. In some embodiments, the NMOS transistor comprises a dummy gate stack above at least some of the first region. In some embodiments, the NMOS transistor comprises a gate stack above at least some of the first region. In some embodiments, the first PP region is between the first NP region and the second NP region. In some embodiments, the second NP region is between the first PP region and the second PP region. In some embodiments, the dummy gate stack is between the first NP region and the first PP region. In some embodiments, the gate stack is between the first PP region and the second NP region. In some embodiments, the STI region is between the second NP region and the second PP region.

It will be appreciated that layers, features, regions, elements, such as the first region, p-type well (PW) region, first NTN region, second NTN region, gate stack, dummy gate stack, shallow trench isolation (STI) region, first n-type plus (NP) region, second NP region, first p-type plus (PP) region, second PP region, epitaxy block region, etc. depicted herein are illustrated with particular dimensions relative to one another, such as structural dimensions or orientations, for example, for purposes of simplicity and ease of understanding and that actual dimensions of the same differ substantially from that illustrated herein, in some embodiments. Additionally, a variety of techniques exist for forming the layers, features, regions, elements, etc. mentioned herein, such as implanting techniques, etching techniques, doping techniques, spin-on techniques, such as spin coating, sputtering techniques such as magnetron or ion beam sputtering, growth techniques, such as thermal growth or deposition techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD), for example.

Also, although the disclosure has been shown and described with respect to one or more implementations, equivalent alterations and modifications will occur based on a reading and understanding of this specification and the annexed drawings. The disclosure includes all such modifications and alterations and is limited only by the scope of the following claims.