Method for generating post-OPC layout in consideration of top loss of etch mask layer

A method of forming a semiconductor circuit includes receiving target layout. An optical proximity correction process is performed on the target layout data to generate a post-OPC layout. A patterning process is performed using the post-OPC layout. The post-OPC layout may be adjusted to compensate for a top loss of an etch mask layer.

TECHNICAL FIELD

Exemplary embodiments of the inventive concept relate to a method of forming a semiconductor circuit.

DISCUSSION OF THE RELATED ART

When fabricating micro patterns (e.g., semiconductor circuits), the formation of a mask pattern may be affected by diffracted or scattered light. For example, a plasma etching process may be influenced by scattered or diffracted plasma. Accordingly, patterns formed on a wafer may be inconsistent with those of a target layout. To address such inconsistency, an optical proximity correction (OPC) process may be performed.

SUMMARY

According to an exemplary embodiment of the inventive concept, a method of forming a semiconductor circuit may include receiving a target layout, performing an optical proximity correction process to the target layout and generating a post-OPC layout, and performing a patterning process using the post-OPC layout. The post-OPC layout may be obtained in consideration of a top loss of an etch mask layer that occurs in an etching process that is performed using the etch mask layer.

In an exemplary embodiment of the inventive concept, the etch mask layer may include a photoresist layer.

In an exemplary embodiment of the inventive concept, the method may further include calculating a threshold light amount of the etch mask layer. The threshold light amount may be selected to prevent the etch mask layer from being removed in the etching process.

In an exemplary embodiment of the inventive concept, the method may further include calculating a threshold background light intensity of the etch mask layer based on the threshold light amount. The threshold background light intensity may be a light intensity when the amount of background light that may leak from an exposed region of the etch mask layer to an unexposed region may be substantially equal to the threshold light amount.

In an exemplary embodiment of the inventive concept, performing the optical proximity correction process may include adjusting the target layout. In adjusting the target layout, a background light intensity of at least a portion of the unexposed region separating two or more exposed regions of the etch mask layer may be less than the threshold background light intensity.

In an exemplary embodiment of the inventive concept, performing the optical proximity correction process may include adjusting an edge of the target layout, calculating aerial image information based on the edge-adjusted target layout, determining whether the aerial image information satisfies the threshold background light intensity, and classifying the edge-adjusted target layout to be in a state of satisfying a litho-resist rule of the optical proximity correction process, when the aerial image information satisfies the threshold background light intensity, and classifying the edge-adjusted target layout not to be in a state of satisfying the litho-resist rule of the optical proximity correction process, when the aerial image information does not satisfy the threshold background light intensity.

In an exemplary embodiment of the inventive concept, performing the optical proximity correction process may include adjusting the target layout to prevent at least a portion of an unexposed region separating exposed regions from having a thickness smaller than a reference thickness by a background light that may leak from the exposed regions of the etch mask layer to the unexposed region during a photolithography process.

According to an exemplary embodiment of the inventive concept, a method of forming a semiconductor circuit may include receiving a target layout, performing an optical proximity correction process and generating a post-OPC layout. The post-OPC layout may be prepared such that at least a portion of an unexposed region, which may be provided between exposed regions of a photoresist layer, can have a thickness greater than a reference thickness, after a photolithography process. A patterning process may be performed using the post-OPC layout.

In an exemplary embodiment of the inventive concept, performing the optical proximity correction process may include adjusting a distance between the exposed regions.

According to an exemplary embodiment of the inventive concept, a system for forming a semiconductor circuit is provided. The system includes a target-layout generator configured to generate a target layout and a patterning apparatus configured to receive the target layout from the target-layout generator. The patterning apparatus adjusts the target layout based on an intensity of background light that leaks from an exposed region of an etch mask layer to an unexposed region of the etch mask layer. The patterning apparatus patterns a semiconductor substrate based on the adjusted target layout.

The target layout may be adjusted by controlling the intensity of the background light to be equal to or lower than a threshold background light intensity.

The patterning apparatus may be configured to divide the target layout into a plurality of fragmentations. The patterning apparatus may be configured to independently adjust a size of each of the plurality of fragmentations.

The patterning apparatus may be configured to produce aerial image information based on the adjusted target layout. The aerial image information may include information on the light leakage. The patterning apparatus may be configured to perform a simulation based on the adjusted target layout. The patterning apparatus may be configured to determine whether a result of the simulation converges to the target layout. The patterning apparatus may be configured to further adjust the adjusted target layout when the result of the simulation does not converge to the target layout. The patterning apparatus may be configured to perform the adjustment of the target layout by a predetermined number of times. The patterning apparatus may be configured to adjust an edge of the target layout. The patterning apparatus may be configured to adjust the intensity of the background light so that the exposed region of the etch mask layer is not removed during an etching process.

DETAILED DESCRIPTION

Exemplary embodiments of the inventive concept will now be described in more detail with reference to the accompanying drawings. Exemplary embodiments of the inventive concept may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Like reference numerals may denote like or similar elements throughout the specification and the drawings.

It will be understood that when an element is referred to as being “on,” “connected” or “coupled” to another element, it can be directly on, connected or coupled to the other element or intervening elements may be present. As used herein the term “and/or” includes any and all combinations of one or more of the associated listed items. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

FIG. 1shows an example of a target layout according to an exemplary embodiment of the inventive concept. For example, the target layout may be prepared corresponding to patterns (of, e.g., a semiconductor circuit) to be formed in a patterning process. The target layout may define various patterns (e.g., line patterns and via patterns) constituting a semiconductor circuit. The target layout may be provided in the form of data, for example.

To compensate for optical proximity effects in a practical process to form the semiconductor circuit, an optical proximity correction (OPC) process may be performed on the target layout. For example, during the OPC process, the target layout may be adjusted or changed in consideration of the optical proximity effects and may be simulated estimating a final structure of patterns to be formed on a wafer. The OPC process may be repeated until the estimated structure has a predetermined degree of similarity with the target layout or until the estimated structure converges to the target layout.

The target layout may be adjusted on a per-fragment basis. For example, the target layout may be divided into a plurality of fragments with predetermined sizes that may be adjusted independently.

FIG. 2shows an example of a post-OPC layout obtained from the target layout ofFIG. 1. The post-OPC layout is depicted with solid lines, and the target layout is depicted with dotted lines. The post-OPC layout has a different shape from the target layout.

FIGS. 3 through 6are sectional views illustrating a process of forming a pattern based on the target layout ofFIG. 2. For example,FIGS. 3 through 6may be sectional views taken along line ofFIG. 2.

Referring toFIG. 3, a first layer110, a second layer120, and an etch mask layer130may be sequentially stacked. The first layer110may include an insulating material or a conductive material. The second layer120may include an insulating material or a conductive material. In an exemplary embodiment of the inventive concept, the second layer120may be an etch-target layer to which a patterning process is later applied.

The etch mask layer130may function as a mask layer in a process of etching the second layer120. For example, the etch mask layer130may include a photoresist layer.

The etch mask layer130may be exposed by light (e.g., laser light). For example, light may be incident onto the etch mask layer130through a photo mask including photomask patterns to be copied onto the etch mask layer130.

The etch mask layer130may include first regions131. The first regions131function as an etch mask and thus are not removed. The etch mask layer130may include second regions133. The second regions133are to be removed during a subsequent step, e.g., a development step.

For example, an exposure process may be performed depending on the material of the etch mask layer130. When the etch mask layer130includes a positive-type photo resist, regions of the etch mask layer130exposed by light may be removed during a subsequent development step, and other regions unexposed by light may remain after the development step. In an exemplary embodiment of the inventive concept, the first regions131may be exposed to light, and the second regions133may be blocked from light. When the etch mask layer130includes a negative-type photoresist, regions of the etch mask layer130exposed by light may be left after the development step. For purposes of description, the exposed or open regions of the etch mask layer130may be removed. However, exemplary embodiments of the inventive concept are not limited to thereto, and for example, the exposed regions may remain.

As a result of a photolithography process, as shown inFIGS. 3 and 4, an etch mask layer130′ may be formed on the second layer120and have only first regions131′.

During an exposure step of the photolithography process, light may be diffracted and scattered to the first regions131functioning as blind regions from the second regions133functioning as open regions and thus may cause upper portions of the first regions131′ to be removed. Accordingly, the top surface of the first regions131′ may be rendered lower than the top surface of the etch mask layer130.

After a photolithography process is performed on the etch mask layer130, the second layer120may be etched using the first regions131′ as an etch mask. The first regions131′ may also be etched during the etching process. The first regions131′ may exhibit a lower etch rate than an etch rate of the second layer120.

Since the upper portions of the first regions131′ are removed, the first regions131′ may be thinner than a target thickness of the etch mask layer130. Thus, the first regions131′ may be removed during the etching process, and thus, portions of the second layer120located below the first regions131′ may be etched partially and unintentionally.

Referring toFIG. 5, by the etching process, a second layer120′ may be formed including target patterns121that remain below the first regions131′. However, as described above, the target patterns121may be partially etched. For example, as illustrated inFIG. 5, upper portion of the target patterns121may be etched and may be rendered to have a similar shape to the shape of the first regions131′.

Referring toFIGS. 5 and 6, the etch mask layer130′ may be removed, and then, a deposition process may be performed. For example, a deposition layer140may be formed on the second material layer120′ which has undergone the etching process. For example, the deposition layer140may be formed of a conductive material or an insulating material and may cover the first layer110and the target patterns121of the second layer120′. Thereafter, a planarization process may be performed on the deposition layer140.

The target layout may include three patterns spaced apart from each other, as shown along line III-III′ ofFIG. 2. Referring toFIG. 6, as a result of the recessed profile of the target patterns121, the deposition layer140may include contact regions141crossing over the target patterns121. For example, the deposition layer140is not separated by the target patterns121. As such, light that leaks to the unexposed regions during a photolithography process may cause an upper portion of the etch mask layer130to be removed (such removal of an upper portion of a layer may be herein referred to as “top loss”), and accordingly, a process failure may happen.

For example, a top loss that may occur due to such light leakage may be compensated by an optical proximity correction method according to an exemplary embodiment of the inventive concept.

FIG. 7is a flow chart illustrating a method of forming a pattern according to an exemplary embodiment of the inventive concept. Referring toFIG. 7, a target layout is received at step S110.

At step S120, an OPC (Optical Proximity Correction) process may be performed in consideration of a top loss of an etch mask layer. For example, during the OPC process, the target layout may be modified to compensate for a top loss of the etch mask layer.

At step S130, a patterning process may be performed using the post-OPC layout.

FIG. 8is a flow chart illustrating a detailed process of an optical proximity correction process (e.g., step S120ofFIG. 7). Referring toFIG. 8, a threshold light amount for an etch mask layer (for example, a photoresist layer) may be calculated at step S210. The threshold light amount may refer to the amount of light allowing the photoresist layer to have a minimum thickness required for an etching process. For example, when the photoresist layer is exposed to light having an amount less than the threshold light amount, the photoresist is not removed in the etching process, thereby effectively functioning as an etch mask.

A threshold background light intensity may be calculated based on the threshold light amount at step S220. The threshold background light intensity may be the intensity of light when the amount of background light that leaks from an exposed region of the photoresist layer to an unexposed region is equal to the threshold light amount. The threshold background light intensity may be used as a litho-resist rule of the optical proximity correction process.

In an exemplary embodiment of the inventive concept, steps S210and S220may be performed as an initial operation of the optical proximity correction process. Steps S210and S220may be performed before the optical proximity correction process is carried out, and a result of the calculation may be used in the optical proximity correction process.

At step S230, the target layout may be adjusted, and thus, an edge of the target layout may be modified. For example, the target layout may be divided into fragments, and the sizes of the fragments may then be adjusted independently. Step S230may be performed as a layout-adjusting operation of the optical proximity correction process.

At step S240, aerial image information may be calculated based on the adjusted layout. The aerial image information may contain information on various phenomena that may occur during a process based on the adjusted layout. For example, the aerial image information may contain information on light leakage which may occur during a photolithography process.

At step S250, it may be examined whether the aerial image information can satisfy the threshold background light intensity. For example, it may be examined whether the intensity of background light, which may be incident into an unexposed region or at least a portion of the unexposed region provided between at least two exposed regions, reaches the threshold background light intensity. For example, it may be determined whether the thickness of the unexposed region can be within a range in which the unexposed region may remain even after an etching process.

When the aerial image information satisfies the threshold background light intensity, a result of the optical proximity correction process may be determined to satisfy the litho-resist rule at step S260. When the aerial image information does not satisfy the threshold background light intensity, the result of the optical proximity correction process may be determined not to satisfy the litho-resist rule at step S270.

Steps S250to S270may include a rule-check operation of the optical proximity correction process. Although the rule-check operation based on the threshold background light intensity is described as an example in connection withFIG. 8, various other rules may be checked during the optical proximity correction process.

When the rule of the optical proximity correction (OPC) process is satisfied, a simulation may be performed. When a result of the simulation is estimated to have a predetermined degree of similarity with the target layout or to converge to the target layout, the optical proximity correction process may be terminated. When the result of the simulation is estimated not to converge to the target layout, step S230may be repeated. Further, when the rule of the optical proximity correction process is not satisfied, step S230may be repeated.

In an exemplary embodiment of the inventive concept, the optical proximity correction (OPC) process may be performed until the number of times of the repetition reaches a predetermined iteration number. Even when the number of times of the repetition reaches the predetermined iteration number, when the result of the simulation is estimated not to converge to the target layout, the optical proximity correction (OPC) process may be terminated.

FIG. 9Ashows an example of a post-OPC layout obtained from the target layout ofFIG. 1.FIG. 9Bshows an example of a post-OPC layout obtained from the target layout ofFIG. 1using an optical proximity correction process according to an exemplary embodiment of the inventive concept.

Referring toFIGS. 9A and 9B, a distance D1 between exposed regions in an area A ofFIG. 9Amay be smaller than a distance D2 between exposed regions in a corresponding area B ofFIG. 9B. The distance D1 being smaller than the distance D2 means that, according to an exemplary embodiment of the inventive concept, a distance between adjacent exposed regions may be adjusted and a background light intensity in an unexposed region (for example, positioned between the adjacent exposed regions) is thus lower than a threshold background light intensity.

FIG. 10Ashows patterns formed by a conventional optical proximity correction process.FIG. 10Bshows patterns formed by an optical proximity correction process according to an exemplary embodiment of the inventive concept. When the conventional optical proximity correction process is used, adjacent patterns in an area C are connected to each other as shown inFIG. 10A. However, when the OPC method according to an exemplary embodiment of the inventive concept is used, adjacent patterns in a corresponding area D are separated from each other as shown inFIG. 10B.

According to an exemplary embodiment of the inventive concept, a top loss of the etch mask layer may be considered when performing the optical proximity correction process. Accordingly, adjacent patterns may be prevented from being connected to each other, thus increasing the fabrication reliability of the semiconductor device.

FIG. 11is a block diagram illustrating a patterning system according to an exemplary embodiment of the inventive concept. Referring toFIG. 11, a patterning system1000may include a target-layout generator1100and a patterning apparatus1200.

The target-layout generator1100may be configured to generate a target layout. For example, the target-layout generator1100may include an operating device with an embedded layout design tool.

The patterning apparatus1200may perform the steps ofFIGS. 7 and 8, for example. The patterning apparatus1200may be configured to receive the target layout from the target-layout generator1100and may be configured to process a layer provided on a wafer or on a substrate. The patterning apparatus1200may be configured to execute an optical proximity correction process on the target layout and may be configured to process a layer provided on a wafer or on a substrate using the post-OPC layout. For example, the patterning apparatus1200may adjust the target layout based on an intensity of background light that leaks from an exposed region of an etch mask layer to an unexposed region of the etch mask layer, and configured to pattern a semiconductor substrate based on the adjusted target layout.

The target layout may be adjusted by controlling the intensity of the background light to be equal to or lower than a threshold background light intensity. The patterning apparatus may be configured to divide the target layout into a plurality of fragmentations and may be configured to independently adjust a size of each of the plurality of fragmentations. The patterning apparatus may be configured to produce aerial image information based on the adjusted target layout.

The aerial image information may include information on the light leakage. The patterning apparatus may be configured to perform a simulation based on the adjusted target layout and may be configured to determine whether a result of the simulation converges to the target layout.

The patterning apparatus may be configured to further adjust the adjusted target layout when the result of the simulation does not converge to the target layout. The patterning apparatus may be configured to perform the adjustment of the target layout by a predetermined number of times.

The patterning apparatus may be configured to adjust an edge of the target layout. The patterning apparatus may be configured to adjust the intensity of the background light so that the exposed region of the etch mask layer is not removed during an etching process.

The patterning apparatus1200may include an optical proximity correction part1210. The optical proximity correction part1210may be configured to perform an optical proximity correction process in consideration of a top loss of the etch mask layer or a background light leakage that may occur during a photolithography process, as described above with reference toFIGS. 7 and 8.

For example, the patterning apparatus1200may include a plurality of units, such as an operating unit (e.g., the optical proximity correction part1210) configured to perform an operation and a processing unit configured to process a layer1300provided on a wafer.

According to exemplary embodiments of the inventive concept, an optical proximity correction (OPC) process may be performed in consideration of a top loss of an etch mask layer that may occur during an etching process. Accordingly, reliability of a post-OPC layout may be increased, and thus, the fabrication reliability of a semiconductor circuit may be increased.