Insulated gate power semiconductor device and method for manufacturing such device

An insulated gate power semiconductor device (1a), comprises in an order from a first main side (20) towards a second main side (27) opposite to the first main side (20) a first conductivity type source layer (3), a second conductivity type base layer (4), a first conductivity type enhancement layer (6) and a first conductivity type drift layer (5). The insulated gate power semiconductor device (1a) further comprises two neighbouring trench gate electrodes (7) to form a vertical MOS cell sandwiched between the two neighbouring trench gate electrodes (7). At least a portion of a second conductivity type protection layer (8a) is arranged in an area between the two neighbouring trench gate electrodes (7), wherein the protection layer (8a) is separated from the gate insulating layer (72) by a first conductivity type channel layer (60a; 60b) extending along the gate insulating layer (72).

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a national stage application of International Application No. PCT/EP2019/074531, filed on Sep. 13, 2019, which claims priority to European Patent Application No. 18201282.3, filed on Oct. 18, 2018, which applications are hereby incorporated herein by reference.

DESCRIPTION

Field of the Invention

The invention relates to the field of power electronics, and more particularly to an insulated gate power semiconductor device according to the preamble of claim1and to a method for manufacturing such an insulated gate power semiconductor device.

Background of the Invention

In the prior art there are known several vertical power semiconductor devices which make use of a vertical metal oxide semiconductor (MOS) cell design, such as a trench insulated gate bipolar transistor (IGBT), or a trench power MOSFET (metal oxide semiconductor field effect transistor).

From EP 0 795 911 A2 there is known a trench IGBT100as shown inFIG. 10. This known trench IGBT100comprises an active MOS cell, in which the following layers are arranged from a first main side20to a second main side27opposite to the first main side20: an (n+) doped source layer3, a p doped base layer4, an n doped enhancement layer6and an (n−) doped drift layer5. Two trench gate electrodes7are arranged adjacent to the first main side20, each trench gate electrode7including an electrically conductive gate layer70, which is separated from the doped layers (i.e. the drift layer5, the enhancement layer6, the base layer4and the source layer3) by a gate insulating layer72(e.g. a gate insulating layer). Towards the second main side27, the trench IGBT100further comprises an (n+) doped buffer layer55and a p doped collector layer9. With the buffer layer55separating the collector layer9from the drift layer5, the trench IGBT100as shown inFIG. 10has a punch-through (PT) configuration. Throughout the specification, if a layer in a specific device is described to be (n+) doped, it is considered to have higher doping concentration than a layer in this specific device which is described to be n doped. Likewise, if a layer in a specific device is described to be (n−) doped, it is considered to have lower doping concentration than a layer in this specific device which is described to be n doped.

A first main electrode2, which forms the emitter electrode of the trench IGBT100, is arranged on the first main side20to electrically contact both, the source layer3and the base layer4. On the second main side27there is arranged a second main electrode25, which forms the collector electrode of the trench IGBT100and which electrically contacts the collector layer9.

A top gate insulating layer74is arranged between the gate layer70and the first main electrode2to electrically insulate the gate layer70from the first main electrode2. The trench gate electrode7extends from the first main side20up to a trench depth77, at which a bottom76of the trench gate electrode7is arranged. The trench gate electrode7has lateral sides75extending from the bottom76to the first main side20.

The enhancement layer6, which has a higher doping concentration than the drift layer5, allows for a reduction of an on-state voltage by increasing the plasma concentration. Lowering the on-state voltage means to lower also the on state losses. The reduction of the on-state voltage by increasing the plasma concentration is more pronounced for larger enhancement layer doping concentrations.

However, on the other side, for larger enhancement layer doping concentrations, the safe operating area (SOA), in particular the turn-off SOA or reverse blocking SOA (RBSOA), becomes worse and the breakdown voltage, which the IGBT is able to sustain, decreases significantly. In addition, the enhancement layer is also exacerbating the impact ionization effect, i.e. the avalanche generation of carriers. This phenomena of avalanche generation becomes even more severe during turn-off of the trench IGBT100, where it is known as dynamic avalanche. The maximum avalanche energy is generated after turn-off and diminishes after a few micro seconds. Avalanche generation of hot carriers having high kinetic energies is in particular very critical at the bottom76of the trench gate electrode7and also at a location, at which the enhancement layer6touches the gate insulating layer72, because hot carriers are injected into the gate insulating layer72and lead to a damage of the gate insulating layer72.

In order to be able to exploit the on-state benefits of a highly doped enhancement layer, without suffering from the drawbacks of reduced blocking performance and reduced RBSOA, p doped protection layer regions80(also referred to as “protection pillows”) have been suggested in EP 0 795 911 A2 as shown inFIG. 10. The p doped protection layer regions80have the effect to reduce the electric field strength at the bottom76of the trench gate electrodes7, so that the RBSOA and breakdown voltage is improved. The introduction of p doped protection layer regions80at the trench bottoms improves the device robustness, being able to postpone the onset of the breakdown mechanism, but the p doped protection layer regions80are not able to redeem the inherent weakness of a trench IGBT device sufficiently where the impact ionization is caused by an increased enhancement layer doping concentration above 2.5·1016cm−3.

For moderate doping levels of the enhancement layer6, namely for doping concentrations of the enhancement layer6below about 2.5·1016cm−3the impact ionization effect or avalanche generation, responsible for the detrimental degradation of the trench IGBT100, is taking place mainly at the bottom76of the trench gate electrodes7. However, in a device with an increased enhancement doping concentration above 2.5·1016cm−3, the avalanche generation becomes more and more significant also at the interface between the base layer4and the enhancement layer6close to the gate insulating layer72.

Avalanche generation of hot carriers near the interface between the enhancement layer6and the gate insulating layer72potentially translates in unwanted drawbacks such as hot carrier injection into the gate insulating layer72with consequent threshold voltage instabilities. Eventually, this results in a degraded dynamic avalanche robustness, and such negative effect is even more exacerbated under hard switching conditions.

From EP 3 251 153 B1 it is known a trench IGBT200as shown inFIG. 11and a method for manufacturing the same. The trench IGBT200is similar to the trench IGBT100shown inFIG. 10. Compared to the trench IGBT100shown inFIG. 10the trench IGBT200disclosed in EP 3 251 153 B1 has in addition to the p doped first protection layer regions80at the bottom76of the trench gate electrodes7n doped second protection layer regions81, which have a higher doping concentration than that of the drift layer5and which encircle the trench gate electrodes7respectively at its lateral side75at a vertical position between the enhancement layer6and the first protection layer region80. The n doped second protection layer regions81act as a sort of additional enhancement layer and to provide the benefits of plasma enhancement without the drawbacks of premature avalanche generation and hot carrier injection into the gate insulating layer72, as it could happen in a trench IGBT100as shown inFIG. 10with increased doping concentration of the enhancement layer6. The role of the p doped first protection layer regions80is to protect the second protection layer regions81from the incoming electric field, thereby delaying the onset of impact ionization and increasing in this way the robustness of the device. With the additional second protection layer regions81plasma concentration can be increased, which means reduced on-state losses, without the drawbacks of an enhancement layer having an increased doping concentration.

The manufacturing method for the trench IGBT200disclosed in EP 3 251 153 B1 is relatively complex as it requires to form a trench recess for the trench gate electrode7in two separate process steps with another process step for creating the second protection layer regions81between these two separate process steps. Further, despite using the first and second protection layer regions80and81avalanche generation of carriers is still relatively high, especially at the interface between enhancement layer6and the base layer4close to the gate insulating layer72, and breakdown voltage is therefore still relatively low in the trench IGBT200of the prior art, while the on state losses are not at its optimum due to the limited enhancement layer doping concentration for which the n doped second protection layer regions81can compensate only to a certain degree.

In WO 2012/113818 A2 is disclosed an insulated gate bipolar device, which has layers of different conductivity types between an emitter electrode on an emitter side and a collector electrode on a collector side in the following order: a source region of a first conductivity type, a base layer of a second conductivity type, which contacts the emitter electrode in a contact area, an enhancement layer of the first conductivity type, a floating compensation layer of the second conductivity type having a compensation layer thickness tp, a drift layer of the first conductivity type having lower doping concentration than the enhancement layer and a collector layer of the second conductivity type. The compensation layer is arranged in a projection of the contact area between the enhancement layer and the drift layer, such that a channel between the enhancement layer and the drift layer is maintained. The enhancement layer has an enhancement layer thickness tn, which is measured in the same plane as the compensation layer thickness, and the following rule applies: Np·tp=k·Nn·tn, wherein Nn and Np are the doping concentrations of the enhancement layer and of the compensation layer, respectively, and k is a factor between 0.67 and 1.5.

In JP 2007 266133 A is disclosed a semiconductor device that is provided with an n-type drift region; an n+-type carrier accumulating region contacting the drift region, a p-type body region contacting the carrier accumulating region; an n+-type emitter region contacting the body region; and a trench gate electrode opposing the body region positioned between the drift region and the emitter region, and the carrier accumulating region via a gate insulating film. The semiconductor device is further provided with floating body regions. The floating body regions are formed in a region including one part of the carrier accumulating region.

In US 2017 018642 A1 it is described a semiconductor device that includes a first conductivity type region provided to at least one of a second conductivity type column region and a second conductivity type layer located on the second conductivity type column region. The first conductivity type region has a non-depletion layer region when a voltage between a first electrode and a second electrode is 0V. When the voltage between the first electrode and the second electrode is a predetermined voltage, a depletion layer formed on interfaces between a first conductivity type column region and the second conductivity type column region as well as the first conductivity type column region and the second conductivity type layer and a depletion layer formed between the first conductivity type region and an interface of a region provided with the first conductivity type region connect to each other.

In EP 2 763 178 A1 it is discussed an IGBT, which comprises an emitter region, a top body region that is formed below the emitter region, a floating region that is formed below the top body region, a bottom body region that is formed below the floating region, a trench, a gate insulating film that covers an inner face of the trench, and a gate electrode that is arranged inside the trench. When a distribution of a concentration of p-type impurities in the top body region and the floating region, which are located below the emitter region, is viewed along a thickness direction of a semiconductor substrate, the concentration of the p-type impurities decreases as a downward distance increases from an upper end of the top body region that is located below the emitter region, and assumes a local minimum value at a predetermined depth in the floating region.

SUMMARY OF THE INVENTION

It is an object of the invention to provide an insulated gate power semiconductor device, in which avalanche generation is reduced and/or shifted away from a gate insulating layer without increasing the on state losses.

The object of the invention is attained by an insulated gate power semiconductor device according to claim1. Further developments of the invention are specified in the dependent claims.

The insulated gate power semiconductor device according to claim1has a protection layer of a second conductivity type which is arranged between two neighboring trench gate electrodes, by which protection layer the electric field lines can be shifted away from the trench gate electrodes to reduce the avalanche generation of hot carriers at the bottom of the trench gate electrode and from the interface between the enhancement layer and the base layer close to the gate insulating layer. The protection layer of the second conductivity type can efficiently protect the gate insulating layer from high electric fields and the channel layer of the a conductivity type different from the second conductivity type separating the protection layer from the gate insulating layer allows a quick removal of carriers by providing a pathway for carriers from the enhancement layer to the drift layer. In the insulated gate power semiconductor device of the invention no high avalanche generation can occur at the gate insulating layer.

The protection layer extends from the area between the two neighbouring trench gate electrodes to a region below the neighbouring trench gate electrodes, so that in an orthogonal projection onto a plane parallel to the first main side, the protection layer overlaps with the two neighbouring trench gate electrodes. Therein, “below the neighbouring trench gate electrodes” means a position on a side of the trench gate electrodes towards the second main side (i.e. between a trench bottom and the second main side) so that in orthogonal projection onto the first main side the protection layer overlaps with each one of the neighbouring trench gate electrodes. With such features the bottom of the neighbouring trench gate electrodes is especially protected from high electric fields during turn-off to thus prevent avalanche generation at the bottom of the neighbouring trench gate electrodes.

In an exemplary embodiment a maximum doping concentration of the protection layer is in a range from 5·1015cm−3to 1·1017cm−3, exemplarily in a range from 5·1015cm−3to 5·1016cm−3. Such doping concentration of the protection layer allows an efficient protection of the gate insulating layer from high electric fields during turn-off without any significant increase of the on-state voltage.

In an exemplary embodiment a maximum doping concentration of the enhancement layer is higher than the maximum doping concentration of the protection layer. A higher doping concentration of the enhancement layer allows a higher plasma concentration in the on-state which translates into a lower on-state voltage and lower on-state losses.

In an exemplary embodiment the first conductivity type is n-type and the second conductivity type is p-type.

In an exemplary embodiment a maximum doping concentration of the enhancement layer is in a range from 4·1016cm−3to 4·1017cm−3, more exemplarily in a range from 1·1017cm−3to 4·1017cm−3. With a relatively high maximum doping concentration in this range it is possible to obtain have a low on-state voltage while the blocking capability is high.

In an exemplary embodiment the area between the two neighbouring trench gate electrodes has, along a line parallel to the first main side and crossing the two neighbouring trench gate electrodes, a varied lateral doping profile, which has a maximum concentration of a second conductivity type dopant in a central area between the two neighbouring trench gate electrodes and which is decreasing from the maximum concentration to a minimum concentration of the second conductivity type dopant towards the two neighbouring trench gate electrodes, respectively. With such concentration profile of the second conductivity type dopant the reduction of the electrical field strength at the gate insulating layer is most efficient while the on-state voltage and the on-state losses can be kept at a minimum. Moreover, such concentration profile of the second conductivity type dopant allows to form the channel layer of the first conductivity type by overcompensation in an easy manner.

In exemplary embodiments the insulated gate power semiconductor device is an IGBT having a collector layer of the second conductivity type on the second main side or is a reverse conducting IGBT having alternatingly a collector layer of the second conductivity type and shorts of the first conductivity type on the second main side or is a MOSFET having a drain layer of the first conductivity type on the second main side.

In an exemplary embodiment the protection layer extends in a direction from the first main side towards a second main side from a first depth, which is less deep than a depth of the bottom of each one of the two neighbouring gate electrode, to a second depth, which is deeper than the depth of the bottom of each one of the two neighbouring gate electrode. In such exemplary embodiment the protection layer can most efficiently protect the gate insulating layer from high electric fields during turn-off of the device.

The object of the invention is also attained by a method according to claim10.

In the method for manufacturing an insulated gate power semiconductor device according claim10the channel layer separating the protection layer from the gate insulating layer is formed by overcompensation due to the first dopant of the second conductivity type being diffused into the substrate and being segregated into the gate insulating layer during and after the step of forming a gate insulating layer. Therein, overcompensation means that the concentration of dopants of the second conductivity is overcompensated by the concentration of dopants of the first conductivity type (i.e. a concentration of dopants of the first conductivity type becomes higher than the concentration of dopants of the second conductivity type) in the area of channel layer. Such method for manufacturing an insulated gate power semiconductor device allows to form the channel layer reliably and with a low number of process steps. The low number of process steps results in a relatively short time required for performing the manufacturing method and in lower manufacturing costs, for example.

In an exemplary embodiment the substrate is made of silicon and the gate insulating layer is made of silicon oxide. Segregation of the (second conductivity type) first dopant takes place particularly efficient at the interface between silicon and silicon oxide.

In an exemplary embodiment the first dopant, which is used for forming the protection layer, is Boron. Boron has a high segregation coefficient and is particularly suitable for the segregation process employed in the manufacturing method of the invention.

In an exemplary embodiment the (first conductivity type) second dopant used for forming the enhancement layer and for overcompensating the first dopant in the area of the channel layer is Phosphorus. Using Phosphorus facilitates the overcompensation in the area of the channel layer during the manufacturing method of the invention.

In an exemplary embodiment the trench recess has a depth in a range from 2.5 μm to 10 μm.

In an exemplary embodiment during and after the step of forming a gate insulating layer a temperature of at least 900° C., exemplarily of at least 975° C., more exemplarily of at least 1050° C., is applied for at least one hour in total. When applying such high temperature for such long time the segregation of the first dopant is most efficient to reliably form the channel layer of the first conductivity type by overcompensation along the gate insulating layer.

The reference symbols used in the figures and their meanings are summarized in the list of reference symbols. Generally, alike or alike-functioning parts are given the same reference symbols. The described embodiment and examples shall not limit the scope of the invention as defined by the appended claims. Therein, the first to fourth examples do as such not fall under the scope of the claims but describe partial aspects of the invention and serve for a better understanding.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

FIG. 1illustrates an insulated gate power semiconductor device according to a first example. The insulated gate power semiconductor device according to the first example is a trench IGBT1acomprising in an order from a first main side20towards a second main side27opposite to the first main side20an (n+)-type source layer3, a p-type base layer4, an n-type enhancement layer6, and a (n−)-type drift layer5. The base layer4is in direct contact with the source layer3to form a first pn junction and the enhancement layer6is in direct contact with the base layer4to form a second pn junction. The trench IGBT1aaccording to the first example further comprises two neighbouring trench gate electrodes7, each of which is arranged at the first main side20and extends from the first main side20in a direction towards the second main side27. Each of the two trench gate electrodes7has an electrically conductive gate layer70, which is covered at a lateral side75and at a bottom76of the trench gate electrode7by a gate insulating layer72, so that the gate insulating layer72separates the gate layer70from the doped layers, i.e. from the source layer3, the base layer4, the enhancement layer6and the drift layer5. A first main electrode2, which forms the emitter electrode of the trench IGBT1a, is arranged on the first main side20to electrically contact both, the source layer3and the base layer4. A top gate insulating layer74is arranged between the gate layer70and the first main electrode2to electrically insulate the gate layer70from the first main electrode2. In other areas (of an orthogonal projection onto a plane parallel to the first main side20) than an area laterally sandwiched between the two neighbouring trench gate electrodes7, the top gate insulating74extends further on the base layer4to separate the first main electrode2from the base layer4. With the above configuration a vertical MOS cell sandwiched between the two neighbouring trench gate electrodes7is formed.

Towards the second main side27, the trench IGBT1afurther comprises a p-type collector layer9. The trench IGBT1aas shown inFIG. 1has a non-punch-through (NPT) configuration, where the collector layer9is in direct contact with the drift layer5. The electric field in blocking condition for a NPT configuration is triangular and stops within the drift layer5and the space charge region does not reach the collector layer9. On the second main side27there is arranged a second main electrode25, which forms the collector electrode of the trench IGBT1aand which electrically contacts the collector layer9.

The source layer3, the base layer4, the enhancement layer6and the drift layer5may be formed of silicon, and the gate insulating layer7may be formed of silicon oxide, for example.

The trench IGBT1afurther comprises a p-type protection layer8aand an n-type channel layer60aextending along and separating the p-type protection layer8afrom the gate insulating layer72. A portion of the p-type protection layer8ais formed in an area between the two neighbouring trench gate electrodes7. The protection layer8aextends, in a direction from the first main side20towards a second main side27from a first depth, which is less deep than a depth of the bottom76of each one of the two neighbouring gate electrode7, to a second depth, which is deeper than the depth of the bottom76of each one of the two neighbouring gate electrodes7. Therein, the depth of certain position means a distance of that position from the first main side2, wherein the first main side2is defined as an outermost plane to which the doped semiconductor layers of the trench IGBT1a, i.e. here the source layer3and the gate layer70, extend on an emitter side of the trench IGBT1a.

The doping concentration of the source layer3is higher than that of the base layer4. Exemplary doping concentrations for the source layer3are higher than 1·10′ cm−3and smaller than 1·1021cm−3, exemplarily between 1·1019cm−3and 5·1019cm−3. The drift layer5has a relatively low doping concentration. Exemplarily, the drift layer5has a constantly low doping concentration. Therein, the substantially constant doping concentration of the drift layer5means that the doping concentration is substantially homogeneous throughout the drift layer5, however without excluding that fluctuations in the doping concentration within the drift layer being in the order of a factor of one to five may be possibly present due to e.g. a fluctuations in the epitaxial growth process. The final drift layer thickness and doping concentration is chosen due to the application needs. The final drift layer thickness and doping concentration is chosen due to the application needs. For devices above 600 V the doping concentration of the drift layer is exemplarily below 5·1014cm−3. For power devices (voltage above 600 V) an exemplary doping concentration of the drift layer5is between 2·1012cm−3and 5·1014cm−3.

The structures as described above form an active MOS cell. The IGBT device may comprise only one active MOS cell as disclosed above, but it is also possible that the trench IGBT comprises at least two or more such active MOS cells, i.e. the active MOS cells can be repetitively arranged in one substrate.

A maximum doping concentration of the protection layer8ais in a range from 5·1015cm−3to 1·1017cm−3, exemplarily in a range from 5·1015cm−3to 5·1016cm−3. A maximum doping concentration of the enhancement layer6may exemplarily be higher than the maximum doping concentration of the protection layer8a, and is exemplarily in a range from 4·1016cm−3to 4·1017cm−3, more exemplarily in a range from 1·1017cm−3to 4·1017cm−3.

The protection layer8ais arranged below the enhancement layer6, i.e. on a side of the enhancement layer6towards the second main side25. Boron is exemplarily used as a p-type dopant for the protection layer8a. Phosphorus is exemplarily used as an n-type dopant for the enhancement layer6. The protection layer8aextends from the enhancement layer6in a direction from the first main side20towards the second main side27, from a first depth, which is less deep than a depth77of the bottom76of each one of the two neighbouring gate electrode7, to a second depth, which is deeper than the depth77of the bottom76of each one of the two neighbouring gate electrode7. Therein, the depth shall be measured from the first main side20, i.e. from the outermost plane to which the doped layers extend, which is in this case the n source layer3and the gate layer70. In the first example, the protection layer8ais limited, in an orthogonal projection onto a plane parallel to the first main side20, to a region between the two neighbouring trench gate electrodes7, i.e. in the orthogonal projection onto the plane parallel to the first main side20the protection layer8ais not overlapping with the trench gate electrodes7.

The area between the two neighbouring trench gate electrodes7may exemplarily have, along any line85, which is below the enhancement layer6, parallel to the first main side20and crossing the two neighbouring trench gate electrodes7, a varied lateral p-type doping profile, which has a maximum concentration of a p-type dopant in a central area between the two neighbouring trench gate electrodes7and which is decreasing from the maximum concentration to a minimum concentration of the p-type dopant towards the two neighbouring trench gate electrodes7, respectively. An n-type dopant may exemplarily have in the area between the two neighbouring trench gate electrodes7, along the line85, a concentration profile which is substantially constant. In the central area, the concentration of the n-type dopant may be less than the concentration of the p-type dopant and in areas adjacent to the two neighbouring gate electrodes7the concentration of the n-type dopant may respectively become higher than the concentration of the p-type dopant due to the lower concentration of the p-type dopant in these areas adjacent to the trench gate electrodes7to form the n-type channel layer60aby overcompensation, i.e. by the n-type dopant overcompensating the p-type dopant.

FIG. 2shows an embodiment of the insulated gate power semiconductor device of the invention. Due to the many similarities between the first example and this embodiment, only differences between the first example and this embodiment will be described. With regard to all other features it is referred to the above discussion of the first example. In particular, elements having the same reference sign shall refer to elements having the same characteristics as the elements described above for the first example. The insulated gate power semiconductor device according to the embodiment is a trench IGBT1band differs from the trench IGBT1ashown inFIG. 1in that the protection layer8bhas another shape than the protection layer8aof the first example. Specifically, different from the protection layer8aof the first example, the protection layer8bof the embodiment extends to a region below the neighbouring trench gate electrodes7. Therein, a position “below the neighbouring trench gate electrodes” means a position on a side of the trench gate electrodes7towards the second main side27so that in orthogonal projection onto a plane parallel to the first main side20the protection layer8boverlaps with each one of the neighbouring trench gate electrodes7. Accordingly, the protection layer8bhas a smaller lateral extension between the two neighbouring trench gate electrodes7than the lateral distance of the trench gate electrodes7(smaller by two times the lateral width of the channel layer60bin a lateral direction parallel to the first main side20). In a region below the trench gate electrodes7, the protection layer has a wider width so that the protection layer8bspreads to a region below the trench gate electrodes7, but is separated from it by the n channel layer60bextending along the lateral sides75and the bottom76of the trench gate electrodes7. As the channel layer60ain the first example, also the channel layer60bin the embodiment shown inFIG. 2provides a continuous n-type region extending from the enhancement layer6to the drift layer5.

FIG. 3illustrates several graphs related to the turn-off behavior of a first trench IGBT without any protection layer (“Device A” inFIG. 3), of a second trench IGBT according to the first example (“Device B” inFIG. 3), and a third trench IGBT according to the embodiment discussed above with reference toFIG. 2(“Device C” inFIG. 3). The first to third trench IGBTs (“Device A”, “Device B” and “Device C”) differ from each other only in the configuration of the protection layer, whereas the remaining configuration of the first to third trench IGBTs is the same with regard to all other aspects.FIG. 3shows from top to bottom graphs of the gate-emitter voltage Vge, graphs of the collector-emitter voltage Vce (see the ordinate on the left) and graphs of the collector current (see the ordinate on the right), and graphs of the maximum avalanche generation Max{AvGen} as a function of the time during turn-off of the first to third trench IGBT, respectively.

As can be seen fromFIG. 3, the gate-emitter voltage Vge decreases quicker for the third trench IGBT (“Device C” inFIG. 3) than for the second trench IGBT (“Device B” inFIG. 3) and decreases quicker for second trench IGBT (“Device B” inFIG. 3) than for the first trench IGBT (“Device A” inFIG. 3). Also a peak in the gate-emitter voltage Vge curve is less pronounced for the third trench IGBT compared to the first and second trench IGBT. A similar faster switching behavior can be observed for the collector-emitter voltage Vce and the collector current Ic. That means that the second and third trench IGBTs allow a faster turn-off compared to the first trench IGBT without protection layer. For the second and third trench IGBT according to embodiments of the invention, much less carriers are created leading to a drastically reduced avalanche generation. That means that for the second and third trench IGBT tremendously less carriers are created and these carriers are created during a shorter period leading to less injection, especially at the critical areas of the gate insulating layer72so that less heat is generated and in addition this heat is generated for a shorter time period.

The risk of hot carrier injection in the gate insulating layer72is reduced in trench IGBTs according to embodiments of the invention. As a result of the reduced risk of hot carrier injection at the gate insulating layer72, especially at the interface between the enhancement layer6and gate insulating layer72, and at the trench bottom76, the device reliability is improved.

FIG. 4illustrates blocking voltage Vbd and on-state voltage Vce,on of a first trench IGBT without any protection layer (“Device A” inFIG. 4), a second trench IGBT according to the first example (“Device B” inFIG. 4), and of a third trench IGBT according to the embodiment discussed above with reference toFIG. 2(“Device C” inFIG. 4) for different doping concentrations of the enhancement layer6, respectively. The first to third trench IGBTs (“Device A”, “Device B” and “Device C” inFIG. 4) differed from each other only in the configuration of the protection layer8a,8band in the doping concentration of the enhancement layer6, whereas the remaining configuration of the first to third trench IGBTs was the same with regard to all other aspects. As can be seen fromFIG. 4, when increasing the doping concentration of the enhancement layer from 3·1016cm−3to 4·1016cm−3, the static blocking voltage or breakdown voltage Vbd does not significantly decrease in the second and third trench IGBT, whereas it decreases drastically for the first trench IGBT. In the second and third trench IGBT (“Device B” and “Device C” inFIG. 4), when increasing the doping concentration of the enhancement layer from 3·1016cm−3to 4·1017cm−3, the breakdown voltage Vbd is decreased by less than 10%, whereas at the same time the on-state voltage Vce,on is decreased by more than 25%. Accordingly, in the second and third trench IGBTs, the on-state voltage Vce,on can be optimized (reduced) by increasing the doping concentration of the enhancement layer6to relatively high values up to 4·1017cm−3(with only small reduction of the optimum breakdown voltage Vbd), whereas increasing the doping concentration of the enhancement layer6in the first trench IGBT without any protection layer beyond 5·1016cm−3results in a drastic drop of the breakdown voltage Vbd.

FIG. 5shows a technology curve for first trench IGBTs without any protection layer (“Device A” inFIG. 5), second trench IGBTs according to the first example (“Device B” inFIG. 5), and of third trench IGBTs according to the embodiment discussed above with reference toFIG. 2(“Device C” inFIG. 5). The switching energy Eoff is shown versus Vce,on. InFIG. 5there is also indicated the total number of electrons generated due to the dynamic avalanche mechanism during a single switching event. For prior art devices, less avalanche electrons are generated. For the same Vce,on the switching losses can be reduced by about 10% (i.e. only half of the numbers of electrons are generated in the second and third trench IGBTs). For a given switching loss, the on state voltage Vce,on can be reduced by about 0.2 V.

InFIG. 6it is shown an insulated gate power semiconductor device according to a second example, which is a trench IGBT1c. Due to the many similarities between the first and the second example, only differences between these two examples will be described. With regard to all other features it is referred to the above discussion of the first example. In particular, elements having the same reference sign shall refer to same elements having the same characteristics as the elements described above for the first example. The trench IGBT1cshown inFIG. 6differs from the trench IGBT1ain that it further comprises an (n+)-type buffer layer55, which has a higher doping concentration than the drift layer5. The buffer layer55is arranged on drift layer5towards the second main side27to separate the collector layer9from the drift layer5. Accordingly, the trench IGBT1cas shown inFIG. 6has a punch-through (PT) configuration. The buffer layer55may either have a constant doping concentration profile, or may have a gradually rising doping concentration profile in a direction towards the second main side27. In operation of the trench IGBT1cat higher blocking voltages, the electric field at the interface between the drift layer5and buffer layer55will not have reached zero. Along a short distance in the buffer layer55it is then steeply decreased to zero due to the relatively high doping concentration thereof.

InFIG. 7it is shown an insulated gate power semiconductor device according to a third example, which is a reverse conducting (RC) trench IGBT1d. Due to the many similarities between the second and the third example, only differences between these two examples will be described. With regard to all other features it is referred to the above discussion of the second example. In particular, elements having the same reference sign shall refer to the same elements having the same characteristics. The RC trench IGBT1dof the third example differs from the trench IGBT1aof the second example in that it comprises a plurality of n-type shorts92which are arranged on the second main side27to penetrate through the p doped collector layer9and electrically connect the n-type drift layer5to the second main electrode25. Accordingly, the p doped collector layer9alternates with the n-type shorts92in a plane parallel to the second main side27as shown inFIG. 7. The buffer layer55has a higher doping concentration than the drift layer5and the shorts92have an even higher doping concentration than the buffer layer55.

FIG. 8shows an insulated gate power semiconductor device according to a fourth example. Due to the many similarities between the first and the fourth example, only differences between these two examples will be described in the following. With regard to all other features it is referred to the above discussion of the first example. In particular, elements having the same reference sign shall refer to same elements having the same characteristics. The insulated gate power semiconductor device according to the fourth example is a vertical power MOSFET10, which differs from the trench IGBT1ashown inFIG. 1in that it does not comprise the p-type collector layer25but comprises on the second main side27an (n+)-doped drain layer95between the drift layer5and the second main electrode25. For the power MOSFET shown inFIG. 8, the first main electrode2forms a source electrode and the second main electrode25forms a drain electrode.

In the following a method manufacturing an insulated gate trench power semiconductor device according the embodiment discussed above with reference toFIG. 2is described with reference toFIGS. 9A to 9F. The method comprises the following steps:

In a step (a) as illustrated inFIG. 9A, an (n−)-type substrate10having a first main side20and second main side27opposite to the first main side20is provided, wherein the doping level of the substrate10is the same as that of the drift layer5in the finalized insulated gate power semiconductor device. Exemplarily, the substrate10may be made of silicon.

In a step (b) illustrated inFIG. 9Ba p-type first dopant18is selectively implanted from the first main side20into the substrate10. Exemplarily, the p-type dopant may be Boron. An implantation mask15may be used for selectively implanting the first dopant into a region28at a predetermined depth as shown inFIG. 9B.

In a step (c), an n-type second dopant is applied and diffused or is implanted into the substrate10from the first main side20for creating the enhancement layer6and the channel layer60bin the finalized device. The n-type second dopant is exemplarily Phosphorous. The elevated n-type doping concentration which is created in step (c) is shown as an n-type layer100inFIG. 9C. Its doping concentration is lower than that of region28.

In a step (d) two neighbouring trench recesses78are formed in the substrate10, wherein each of the trench recesses78extends from the first main side20into the substrate10, and wherein each trench recess78has lateral sides75and a bottom76as shown inFIG. 9D. The trench recess78has exemplarily a depth between 2.5 μm and 10 μm. In the present embodiment each of the two neighbouring trench recesses78overlaps partially with the p-type region28in an orthogonal projection onto a plane parallel to the first main side20of the substrate10. The trench recesses78penetrate into the region28so that a portion of the bottom76and a lower portion of the lateral sides75of trench recess78is directly adjacent to the region28as shown inFIG. 9D.

In a step (e) a gate insulating layer72is formed on the lateral sides75and on the bottom76of each trench recess78as shown inFIG. 9E. Exemplarily, the gate insulating layer72may be a gate oxide layer, in particular the gate insulating layer72may be made of silicon oxide. During or after step (e) of forming a gate insulating layer72a temperature of at least 900° C., exemplarily of at least 975° C., more exemplarily of at least 1050° C. is applied for at least one hour in total. With the heat energy input associated therewith, diffusion and segregation of the p-type dopant results in a reduction of the concentration of first dopants below the concentration of n-type dopant in areas directly adjacent to the trench recesses78. This results in the creation of the n-type channel layer60bby overcompensation as shown inFIG. 9E.

In a step (f), a p-type third dopant is applied and diffused or is implanted into the substrate10from the first main side20for forming the base layer4in the finalized insulated gate power semiconductor device.

In a step (g) an n-type forth dopant is applied and diffused or is implanted into the substrate (10) from the first main side (20) for forming the highly doped (n+)-type source layer3in the finalized insulated gate power semiconductor device. The step (g) is exemplarily performed after step (e). Afterwards, an etching step may be performed, by which in a central region between the two neighbouring gate electrodes7, material is removed to a depth, in which the p-type dopant of the base layer4predominates to enable a contact from a later formed emitter electrode2to the base layer4.

Depending on which specific insulated gate power semiconductor device is to be manufactured, the method may include additional method steps which are well known to the skilled person. For example for manufacturing a trench IGBT1a,1b,1cor1das shown any one ofFIG. 1, 2, 6 or 7, a p type dopant may be implanted from the second main side27and annealed for the creation of the collector layer9. For manufacturing a PT trench IGBT1cas shown inFIG. 6an n-type dopant may be implanted from the second main side27into the substrate10and annealed for the creation of the buffer layer55. For manufacturing the RC IGBT1das shown inFIG. 7an n-type dopant may selectively be implanted into the collector layer9by using a mask, for example, and annealed to create the shorts92penetrating the collector layer9. For manufacturing the power MOSFET10as shown inFIG. 8an n-type dopant may be implanted from the second main side27into the substrate and the substrate10may be annealed to form the drain layer95.

Further, trench recesses80are filled with electrically conductive material thereby forming the gate layer70such that the electrically insulating gate insulating layer72separates the gate layer70from the drift layer5, the base layer4and the source layer3. Thus, a trench gate electrode7is formed, which comprises the gate layer70and the gate insulating layer72, wherein the trench gate electrode7is arranged laterally to the base layer4in a plane parallel to the first main side22. Thereafter, a top gate insulating74is formed at least on the trench gate electrode7.

Finally, an emitter electrode2is formed on the first main side20, which contacts both, the base layer4and the source layer3. On the second main side27a collector electrode25is formed, which contacts the doped layer on the second side27, i.e. the collector layer9for the trench IGBT1a,1b,1cand1das shown inFIGS. 1, 2, 6 and 7, for example, or the drain layer95for a power MOSFET10as shown inFIG. 8, for example.

Modifications and variations of the above described embodiments and examples may be possible.

The gate electrode7may have different designs like a stripe design, i.e. having in a plane parallel to the first main side20a short side and a long side perpendicular to the short side. The source layer3is arranged along the long sides of the gate electrode7. Other designs for the trench gate electrode7are also possible like square design, circular design, ring design, hexagonal design, etc. The device may have two neighbouring trench gate electrodes7or it may comprise a more than two trench gate electrodes7. Exemplarily, in the latter case the gate electrodes7are arranged in a regular geometrical design.

In all embodiments and examples, the conductivity types may be switched, i.e. all layers which are described above as n-type may be p type (e.g. the drift layer5, the source layer3, the enhancement layer6, the buffer layer55, shorts92and the channel layers60a,60b) and all layers which are described above to be p-type may be n-type (e.g. base layer4, the collector layer6and the protection layers8aand8b).

In the embodiments and examples shown in the figures, a source layer4is formed only on one side of the trench gate electrodes7, respectively. However, the source layer may be formed also on both sides of the gate electrodes7. Also in some modified embodiments or examples, active MOS cells may be separated from each other by dummy cells or any other appropriate layer configuration or structure.

The order of steps in the method for manufacturing an insulated gate power semiconductor device is not limited to the indicated order of above discussed steps (a) to (f), but may be any other appropriate order. For, example, it is also possible to create the base and/or source layer4,3at any other appropriate point in time during the manufacturing method, the base layer4may be created before or after the step (d) of forming trench recesses78, for example, while the source layer3may be created at any time after the step (e) of forming a gate insulating layer72.

It should be noted the term “comprising” does not exclude other elements or steps and that the indefinite article “a” or “an” does not exclude the plural. Also elements described in association with different embodiments may be combined. It should also be noted that reference signs in the claims shall not be construed as limiting the scope of the claims.

It will be appreciated by those skilled in the art that the present invention can be embodied in other specific forms without departing from the scope of the invention as defined by the appended claims.

LIST OF REFERENCE SIGNS