Phase change memory devices

A phase change memory device includes a switching device and a storage node connected to the switching device. The storage node includes a bottom stack, a phase change layer disposed on the bottom stack and a top stack disposed on the phase change layer. The phase change layer includes a unit for increasing a path of current flowing through the phase change layer and reducing a volume of a phase change memory region. The area of a surface of the unit disposed opposite to the bottom stack is greater than or equal to the area of a surface of the bottom stack in contact with the phase change layer.

PRIORITY STATEMENT

This non-provisional U.S. patent application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2006-0130442, filed on Dec. 19, 2006, in the Korean Intellectual Property Office, the entire contents of which is incorporated herein by reference.

BACKGROUND

Description of the Related Art

A conventional phase change memory device (such as a phase change random access memory (PRAM)) may include a storage node having a phase change material layer and a transistor connected to the storage node. When a reset current is applied to the phase change memory device, a region in contact with a bottom electrode contact layer of the phase change material layer may be heated to a temperature higher than a melting point of the phase change material layer. As a result, the region in contact with the bottom electrode contact layer may become amorphous. The amorphous region may be changed into a crystalline region by applying a set current to the storage node.

An amorphous region of the phase change material layer may have a higher resistance than other regions of the phase change material layer. As a result, the value of a current passing through the phase change material layer may depend on whether or not an amorphous region exists in the phase change material layer. In one example, when the amorphous region is present in the phase change material layer, a current supplied to the phase change material layer may be smaller than a reference current, and a data “1” may be read from the PRAM. Conversely, when the amorphous region is not present in the phase change material layer, a current passing through the phase change material layer may be larger than the reference current, and a data “0” may be read from the PRAM. Opposite standards may be used in deciding whether data “1” or data “0” is read from the PRAM.

As integration density of conventional semiconductor memory devices increases, transistor size should decrease. As a result, the maximum sustainable current in the transistor may also decrease. In conventional phase change memory devices, a reset current and a set current may be supplied through the transistor. The reset current may be larger than the set current. When transistor size is reduced, the reset current may decrease so that the smaller transistor may sustain the reset current.

SUMMARY

Example embodiments relate to phase change memory devices, methods of manufacturing and methods of operating the same. Phase change memory devices according to example embodiments may include an expanded current path, a reduced memory region and/or reduced program volume, methods of manufacturing and methods of operating the same.

Example embodiments provide phase change memory devices, which may have increased integration density by reducing a reset current. Example embodiments may suppress and/or prevent data loss due to external heat.

At least one example embodiment provides a phase change memory device including a switching device and a storage node connected to the switching device. The storage node may include a bottom stack, a phase change layer disposed on the bottom stack, and a top stack disposed on the phase change layer. The phase change layer may include a current path increase unit for increasing a path of current flowing through the phase change layer. The current path increase unit may also reduce a volume of a phase change memory region.

According to example embodiments, an area of a surface of the current path increase unit disposed opposite the bottom stack may be greater than or equal to an area of a surface of the bottom stack in contact with the phase change layer. The current path increase unit may be a material layer having a lower electric conductivity than an amorphous region to be formed in the phase change layer. The material layer may be an insulating layer or a conductive layer. The material layer may have a thickness sufficient to suppress and/or prevent tunneling of the current flowing through the phase change layer.

According to example embodiments, the phase change layer may include a plurality of material layers stacked vertically and spaced from one another. In this example, the width of at least a portion of the material layers may be different from the width of the other material layers. The storage node may further include a plurality of (e.g., two) material layers stacked vertically between the material layers. The plurality of material layers may be disposed on the same or substantially the same level (e.g., in the same plane) and/or spaced over an underlying material layer.

At least one other example embodiment provides a phase change random access memory (PRAM) including a switching device and a storage node connected to the switching device. The storage node may include a bottom stack, a phase change layer having a trench filled with a material layer, disposed on the bottom stack, a top stack disposed on the phase change layer and the material layer. The trench may be filled with a material layer. The material layer may have an area greater than or equal to an area of a surface of the bottom stack in contact with the phase change layer. The material layer may have lower electric conductivity than an amorphous region to be formed in the phase change layer.

According to at least some example embodiments, the storage node may further include a cylindrical material layer disposed apart from the material layer to enclose the surface of the bottom stack and the material layer. The cylindrical material layer may have lower electric conductivity than the amorphous region to be formed in the phase change layer. The material layer filled in the trench may extend beyond the cylindrical material layer. The material layer filled in the trench may be an insulating layer or a conductive layer. The cylindrical material layer may have the same or substantially the same electric conductivity as the material layer filling the trench. Alternatively, the cylindrical material may have a different electric conductivity than the material layer filled in the trench.

At least one other example embodiment provides a method of manufacturing a memory device (e.g., a PRAM) including a switching device and a storage node connected to the switching device. According to at least this method, a storage node may be formed. For example, a first phase change layer may be formed on an insulating interlayer to cover an exposed surface of a bottom electrode contact layer. A first material layer may be formed on a region of the first phase change layer to cover the exposed surface of the bottom electrode contact layer. A second phase change layer may be formed on the first phase change layer to cover the first material layer. The first material layer may have a lower electric conductivity than an amorphous region formed in the first phase change layer.

According to at least some example embodiments, the first material layer may be an insulating layer or a conductive layer. A second material layer may be formed on the second phase change layer, and a third phase change layer may be formed on the second phase change layer to cover the second material layer. The second material layer may have lower electric conductivity than each of the first through third phase change layers. The second material layer may be formed in a plurality of (e.g., at least two) separate portions. The plurality of portions may be formed apart from each other such that a space between the plurality of portions may be positioned over the first material layer. The second material layer may be formed to have an area greater than or equal to the first material layer.

According to at least some example embodiments, the first and second material layers may have the same, substantially the same or different electric conductivities. The second material layer may be one of an insulating layer and a conductive layer.

At least one other example embodiment provides a method of manufacturing a memory device (e.g., a PRAM) including a switching device and a storage node connected to the switching device. According to at least this method, a storage node may be formed. For example, a phase change layer may be formed on an insulating interlayer to cover an exposed surface of a bottom electrode contact layer. A trench may be formed over the exposed surface of the bottom electrode contact layer in the phase change layer, and the trench may be filled with a material layer. A top stack may be formed on the phase change layer and the material layer. The trench may have a bottom surface with at least the same or substantially the same area as the exposed surface of the bottom electrode contact layer. The material layer may have a lower electric conductivity than an amorphous region formed in the phase change layer.

According to at least some example embodiments, before forming the phase change layer on the insulating interlayer, a cylindrical material layer may be formed on the insulating interlayer to enclose the exposed surface of the bottom electrode contact layer and the trench. The material layer filling the trench may expand beyond the cylindrical material layer. The cylindrical material layer may have lower electric conductivity than the phase change layer. The material filling the trench may have different electric conductivity than the cylindrical material layer. The cylindrical material layer may be one of an insulating layer and a conductive layer.

At least one other example embodiment provides a method of operating a memory device (e.g., a PRAM) including a switching device and a storage node connected to the switching device. According to at least this method, the switching device may be maintained in an on state and an operating voltage may be applied to the storage node. The operating voltage may be one of a write voltage, a read voltage and an erase voltage.

According to at least some example embodiments, when the operating voltage is a read voltage, a current measured in the storage node may be compared with a reference current. The reset current of the memory may be reduced, which may increase integration density of the memory. Furthermore, the insulating layer included in the phase change layer may suppress and/or prevent a program volume (e.g., an amorphous region) of the phase change layer from being arbitrarily changed into a crystalline region due to external agents, such as heat. As a result, loss and/or change of written data may be suppressed and/or inhibited.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Various example embodiments will now be described more fully with reference to the accompanying drawings in which some example embodiments are shown. In the drawings, the thicknesses of layers and regions are exaggerated for clarity.

It will be understood that when an element or layer is referred to as being “formed on,” another element or layer, it can be directly or indirectly formed on the other element or layer. That is, for example, intervening elements or layers may be present. In contrast, when an element or layer is referred to as being “directly formed on,” to another element, there are no intervening elements or layers present. Other words used to describe the relationship between elements or layers should be interpreted in a like fashion (e.g., “between,” versus “directly between,” “adjacent,” versus “directly adjacent,” etc.).

Example embodiments of phase change memory devices, methods of manufacturing the same and operating the same will now be described more fully hereinafter with reference to the accompanying drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity.

FIG. 1is a cross-sectional view of a phase change memory device according to an example embodiment.

Referring toFIG. 1, a first impurity region12and a second impurity region14may be formed apart from each other in a substrate10. The first and second impurity regions12and14may be doped with conductivity type impurities, for example, n-type or p-type impurities. One of the first and second impurity regions12and14may be a source region, while the other may be a drain region. A gate stack20may be disposed between the first and second impurity regions12and14on the substrate10. A channel region16may be disposed under the gate stack20. The gate stack20may include a gate insulating layer18and a gate electrode19stacked sequentially. The substrate10having the first and second impurity regions12and14and the gate stack20may constitute a switching device or transistor.

A first insulating interlayer22may be disposed on the substrate10to cover the transistor. A first contact hole h1may be formed in or through the first insulating interlayer22to expose the second impurity region14. The first contact hole h1may be filled with a conductive plug24. A bottom electrode30may be disposed on the first insulating interlayer22to cover at least an exposed surface of the conductive plug24. For example, bottom electrode30may have a size sufficient to cover the exposed portion of the bottom electrode30, or may have a size larger than the exposed portion of the bottom electrode30in at least one direction.

A second insulating interlayer32may be stacked on the first insulating interlayer22to cover the bottom electrode30. A second contact hole h2may be formed in or through the second insulating interlayer32to expose a portion of the bottom electrode30. The second contact hole h2may be filled with a bottom electrode contact layer34. The bottom electrode30and the bottom electrode contact layer34may constitute a bottom stack. The bottom electrode contact layer34may be, for example, a TiN layer, a TiAlN layer or the like. The second insulating interlayer32may be formed of the same material as the first insulating interlayer22.

A phase change layer36may be disposed on the second insulating interlayer32to cover an exposed surface of the bottom electrode contact layer34. For example, phase change layer36may have a size sufficient to cover the exposed surface of the bottom electrode contact layer34, or may have a size larger than the exposed surface of the bottom electrode contact layer34in at least one direction. In at least one example embodiment, the phase change layer36may be a GeSbTe (GST) layer or a binary, ternary, or quaternary chalcogenide layer. An insulating layer38may be formed in the phase change layer36. The insulating layer38may have a first thickness.

The insulating layer38may be, for example, a silicon oxide layer or the like. Alternatively, the insulating layer38may be a nitride layer or another insulating material layer. The insulating layer38may function as a current path increase unit for increasing (expanding) a path of current flowing through the phase change layer36. Although the current path increase unit is shown as insulating layer38inFIG. 1, the current path increase unit is not limited to the insulating layer38. For example, any material layer having an electric conductivity lower than that of the phase change layer36may function as the current path increase unit. Therefore, the insulating layer38may be replaced by any suitable material layer having an electric conductivity lower than that of the phase change layer36.

Considering that an amorphous region is formed in the phase change layer36after a reset current is supplied thereto, the electric conductivity of the insulating layer38or the material layer may be lower than that of the amorphous region of the phase change layer36. The insulating layer38may cause a phase change memory region, which may transition into an amorphous region (e.g., a program volume), to narrow to a region between the insulating layer38and the bottom electrode contact layer34. If the program volume narrows in the phase change layer36, the density of current passing through the program volume may increase more than when the insulating layer38is omitted. This may decrease a current required for a memory operation (e.g., a reset current).

The insulating layer38may be disposed opposite to the bottom electrode contact layer34and the second insulating interlayer32, but may be disposed adjacent to the bottom electrode contact layer34. The insulating layer38may have a thickness sufficient to suppress and/or prevent tunneling of a reset current applied to the phase change memory device (hereinafter, a reduced or minimum thickness). As a result, if the reset current is reduced, the thickness of the insulating layer38may also be reduced. The insulating layer38may suppress and/or prevent the program volume of the phase change layer36(e.g., the region of the phase change layer36) changed from a crystalline state to an amorphous state when the reset current is supplied thereto, for example, the region between the insulating layer38and the bottom electrode contact layer34, from being damaged by heat generated during subsequent processes.

FIG. 2is a cross-sectional view of the phase change memory device ofFIG. 1in which an amorphous region is formed in a phase change layer.

Referring toFIG. 2, region A1may be a region of the phase change layer36, which may be changed into an amorphous region due to the insulating layer38. As shown, the region A1may narrow to a region between the insulating layer38and the bottom electrode contact layer34. Also, if a current supplied from the bottom electrode contact layer34to a top electrode42bypasses the insulating layer38and passes through the phase change layer36, the current path may expand more than when the insulating layer38is omitted. As described above, because the region A1narrows and the current path expands, the current density and/or resistance of the region A1may increase. As a result, the energy amount at the region A1may be greater than or equal to that in the conventional art at a smaller current than in the conventional art. Therefore, a reset current supplied to the phase change layer36may be reduced as compared to the conventional art. InFIG. 2, a region A2refers to a region where a face-centered cubic (FCC) crystal lattice is changed into a hexagonal close-packed (HCP) crystal lattice.

Referring back toFIG. 1, a top stack may be formed on the phase change layer36. The top stack may include an adhesive layer40and a top electrode42stacked sequentially. The adhesive layer40may be, for example, a Ti layer or the like, and the top electrode42may be, for example, a TiN electrode or the like. The bottom stack, the phase change layer36, and the top stack may constitute a storage node S.

FIG. 3is a cross-sectional view of a phase change memory device according to another example embodiment.

Referring toFIG. 3, a trench37may be formed to a first depth in the phase change layer36. The trench37may be filled with an insulating layer38. An adhesive layer40may be formed on the phase change layer36to cover the insulating layer38, and a top electrode42may be formed on the adhesive layer40. The remaining elements of a phase change memory device may be the same as the example embodiment shown inFIG. 1.

FIG. 4is a cross-sectional view of a phase change memory device according to another example embodiment.

Referring toFIG. 4, a plurality of insulating layers38,39,41and43may be formed in a phase change layer36. The plurality of insulating layers38,39,41and43may be stacked at given intervals in a vertical direction. The insulating layers38,39,41and43may be arranged or configured to expand a path of current flowing between a bottom electrode contact layer34and a top electrode42.

In one example embodiment, two first insulating layers39may be spaced apart from each other over the insulating layer38. In this example, a space between the two first insulating layers39may correspond to (e.g., be aligned with) the center of the insulating layer38. A second insulating layer41may be disposed over the first insulating layers39in a position corresponding to the insulating layer38. Two third insulating layers43may be arranged in the same manner as the first insulating layers39. The remaining elements of a phase change memory device may be the same as the example embodiment shown inFIG. 1. As illustrated inFIG. 4, while passing through the phase change layer36, a current “I” bypasses the insulating layer38, may pass between the first insulating layers39, bypass the second insulating layer41, and pass between the third insulating layers43.

As described above, a path of the current “I” passing through the phase change layer36may expand more than without the plurality of insulating layers38,39,41and43. Thus, the resistance of the path of the current “I” may increase more than when the current “I” flows through a linear path. Furthermore, because a region between the insulating layer38and the bottom electrode contact layer34narrows due to the insulating layer38, the current density of the region between the insulating layer38and the bottom electrode contact layer34may increase. Therefore, when the same voltage is applied to the phase change layer36as in the conventional art, a reset current required to change the region between the insulating layer38and the bottom electrode contact layer34into an amorphous region may be reduced as compared to the conventional art.

FIG. 5is a cross-sectional view of a phase change memory device according to another example embodiment.

Referring toFIG. 5, a first insulating layer52and a second insulating layer54may be disposed between a second insulating interlayer32including a bottom electrode contact layer34and an adhesive layer40. The first insulating layer52may be a cylindrical insulating layer spaced apart from the bottom electrode contact layer34. For example, the first insulating layer52may include a first insulating layer portion formed on one side of the bottom electrode contact layer34, and a second insulating layer portion formed on another side of the bottom electrode contact layer34. The first insulating layer52may enclose the bottom electrode contact layer34.

The second insulating layer54may be formed over the first insulating layer52, but the second insulating layer54may not contact the first insulating layer52. The second insulating layer54may include a middle protrusion portion54a. The middle protrusion portion54amay protrude toward the inside of the cylindrical first insulating layer52such that the protrusion portion54ais relatively close to and faces the bottom electrode contact layer34. The remaining portion of the second insulating layer54expands from the protrusion54aoutward to the first insulating layer52and then expands toward the second insulating interlayer32parallel to an outer surface of the first insulating layer52. The vertical length of an outer portion of the second insulating layer54may be less than an intermediate portion of the second insulating layer54(e.g., between the outer portion and the middle protrusion portion), but less than the vertical length of the middle protrusion portion54a. The horizontal width of the second portion of the second insulating layer54may be the same as the horizontal width of the third portion of the second insulating layer54, but less than the horizontal width of the middle protrusion portion54a.

A top surface of the second insulating layer54may contact the adhesive layer40. The length of the top surface of the second insulating layer54may be less than that of the adhesive layer40and/or the top electrode42. The first and second insulating layers52and54may be enclosed by the phase change layer36. Also, the space between the first and second insulating layers52and54may be filled with the phase change layer36. The first and second insulating layers52and54may be formed of the same material as the insulating layer38discussed above with regard to the example embodiment shown inFIG. 1. Alternatively, the first and second insulating layers52and54may be formed of different insulating material. InFIG. 5, for example, a current may flow through a path11from the bottom electrode contact layer34to a top electrode42.

Still referring toFIG. 3, for the same reason as described in the previous example embodiments, a region A3between an edge of the bottom electrode contact layer34and the protrusion54aof the second insulating layer54adjacent to the edge of the bottom electrode contact layer34may change into an amorphous region at a lower reset current than in the conventional art.

FIGS. 6 through 11are cross-sectional views for illustrating a method of manufacturing a phase change memory device according to an example embodiment.

Referring toFIG. 6, a gate stack20may be formed on a given region of a substrate10. The gate stack20may be obtained by sequentially stacking a gate insulating layer18and a gate electrode19on the substrate10. A conductive impurity may be implanted into the substrate10using the gate stack20as a mask to form first and second impurity regions12and14. The conductive impurity may be, for example, n-type or a p-type impurity. The gate stack20may be interposed between the first and second impurity regions12and14. One of the first and second impurity regions12and14may be a source region, while the other one may be a drain region. The first and second impurity regions12and14and the gate stack20may constitute a transistor, which may be one of a plurality of switching devices. A region disposed under (e.g., directly under) the gate insulating layer18of the substrate10(e.g., a region between the first and second impurity regions12and14) may serve as a channel region16.

A first insulating interlayer22may be formed on the substrate10to cover the transistor. The first insulating interlayer22may be formed of a dielectric material, such as, SiOX, SiOXNY, or other similar insulating material. A first contact hole h1may be formed through the first insulating interlayer22to expose at least a portion of the second impurity region14. The first contact hole h1may be filled with a conductive material to form a conductive plug24. A bottom electrode30may be formed on the first insulating interlayer22to cover an exposed surface of the conductive plug24. The bottom electrode30may be formed of TiN, TiAlN or the like. Alternatively, the bottom electrode30may be formed of silicide containing ions of a metal selected from the group consisting of or including Ag, Au, Al, Cu, Cr, Co, Ni, Ti, Sb, V, Mo, Ta, Nb, Ru, W, Pt, Pd, Zn, Mg, an alloy thereof and the like.

Referring toFIG. 7, a second insulating interlayer32may be formed on the first insulating interlayer22to cover the bottom electrode30. The second insulating interlayer32may be formed of a dielectric material, such as, SiOX, SiOXNYor the like. A second contact hole h2may be formed in the second insulating interlayer32to partially expose a top surface of the bottom electrode30. The second contact hole h2may be filled with TiN, TiAlN or the like to form a bottom electrode contact layer34.

Referring toFIG. 8, a first phase change layer36amay be formed on the second insulating interlayer32to cover at least the top surface of the bottom electrode contact layer34. The first phase change layer36amay be formed of, for example, GST or the like. Alternatively, the first phase change layer36amay be formed of another phase change material, for example, a binary, ternary, or quaternary chalcogenide material. The first phase change layer36amay be formed to a thickness of several to several tens of nanometers.

A photoresist pattern50may be formed on the first phase change layer36a. The photoresist pattern50may be formed to expose a region of the first phase change layer36acorresponding to the bottom electrode contact layer34and a portion of the second insulating interlayer32around the bottom electrode contact layer34. An insulating layer38may be formed on the photoresist pattern50to cover an exposed region of the first phase change layer36a. The insulating layer38may be formed of silicon oxide or other similar insulating material such as nitride or the like. The insulating layer38may be formed to the above-described thickness or more. The insulating layer38may be formed to a smaller thickness based on a reset current to be supplied to the phase change memory device. The insulating layer38may be replaced by a material layer having any suitable material having an electric conductivity lower than that of the first phase change layer36a. Thus, the material layer may be an insulating layer or a conductive layer. In one example, the material layer may have an electric conductivity lower than that of an amorphous region to be formed in the first phase change layer36a. The above description regarding the material layer may refer to any insulating layer to be formed in a phase change layer as described later.

Referring toFIG. 9, the photoresist pattern50and a portion of the insulating layer38formed on the photoresist pattern50may be removed (e.g., simultaneously) using any suitable lift-off or removal process. A portion of the insulating layer38may remain on a portion of the first phase change layer36aas illustrated inFIG. 9. The remaining insulating layer38may be formed on a portion of the first phase change layer36acorresponding to the bottom electrode contact layer34and a portion of the second insulating interlayer32disposed around the bottom electrode contact layer34with the first phase change layer36ainterposed there between.

Referring toFIG. 10, a second phase change layer36bmay be formed on the first phase change layer36ato cover the insulating layer38. The second phase change layer36bmay be formed of the same phase change material as the first phase change layer36a. A top surface of the second phase change layer36bmay be planarized, and an adhesive layer40and a top electrode42may be sequentially formed on the planarized surface of the second phase change layer36b. The adhesive layer40may be formed of, for example, Ti or the like, while the top electrode42may be formed of, for example, TiN, TiAlN or the like.

A photoresist pattern60may be formed on the top electrode42. In this example, the photoresist pattern60may be formed on a portion of the top electrode corresponding to the insulating layer38and a portion of the first phase change layer36adisposed around the insulating layer38. The top electrode42may be etched using the photoresist pattern60as an etch mask. The etching process may be sequentially performed on the adhesive layer40and the second and first phase change layers36band36ato expose the second insulating interlayer32. As a result, as illustrated inFIG. 11, a phase change layer36, the adhesive layer40, and the top electrode42, each having the same shape as the photoresist pattern60, may be formed on the second insulating interlayer32. The phase change layer36, the adhesive layer40and the top electrode42may constitute a storage node along with the bottom electrode30and the bottom electrode contact layer34. The photoresist pattern60may be removed after etching.

The formation of a second contact hole h2in a second insulating interlayer32and the formation of a bottom electrode contact layer34in the second contact hole h2may be the same as described with reference toFIG. 7.

FIGS. 12 through 16are cross-sectional views for illustrating a method of manufacturing a phase change memory device according to another example embodiment;

Referring toFIG. 12, a first phase change layer68may be formed on the second insulating interlayer32to cover an exposed surface of the bottom electrode contact layer34. In this example embodiment, the first phase change layer68may be formed to a thickness greater than the first phase change layer36adescribed above. A photoresist pattern70may be formed on the first phase change layer68to expose a region of the first phase change layer68. The exposed region of the first phase change layer68may correspond to the bottom electrode contact layer34and a portion of the second insulating interlayer32disposed around the bottom electrode contact layer34.

Referring toFIG. 13, the exposed region of the first phase change layer68may be etched using the photoresist pattern70as an etch mask to form a trench69having a depth, which protrudes into the first phase change layer68. An insulating layer38may be formed on the photoresist pattern70to fill the trench69. The insulating layer38may be formed of the same material as described above. The photoresist pattern70and the insulating layer38formed thereon may be removed (e.g., simultaneously) using any suitable removal or lift-off process. As a result, as illustrated inFIG. 14, the remaining insulating layer38may fill the trench69and protrude from the first phase change layer68to a thickness. A top surface of the remaining insulating layer38may be planarized until a top surface of the first phase change layer68is exposed.

Referring toFIG. 15, a second phase change layer71may be formed on the first phase change layer68to cover the planarized top surface of the insulating layer38. The second phase change layer71may be formed of the same, substantially the same or a different phase change material as the first phase change layer68. By forming the second phase change layer71, the insulating layer38may be sandwiched in a phase change layer including the first and second phase change layers68and71. An adhesive layer40and a top electrode42may be formed on the second phase change layer71. Thereafter, a photoresist pattern60may be formed as described above with reference toFIG. 10, and a stacked structure formed on the second insulating interlayer32may be etched using the photoresist pattern60as an etch mask as described above with reference toFIG. 11.

As a result, as illustrated inFIG. 16, a stacked structure including the phase change layer68and71, the adhesive layer40, and the top electrode42may be formed on the second insulating interlayer32. The phase change layer68and71, in which the insulating layer38may be sandwiched, may contact the exposed surface of the bottom electrode contact layer34. The stacked structure may constitute a storage node along with the bottom electrode contact layer34.

Because the processes performed until forming a bottom electrode contact layer34on a second insulating interlayer32may be the same as the above-described example embodiments, the detailed description of those portions of the following example embodiments begin with subsequent processes.

FIGS. 17 and 18are cross-sectional views for partially illustrating a method of manufacturing a phase change memory device according to another example embodiment.

Referring toFIG. 17, a first phase change layer68may be formed on the second insulating interlayer32to cover a top surface of the bottom electrode contact layer34. A trench69may be formed to a depth extending into the first phase change layer68. The trench69may be formed opposite to the bottom electrode contact layer34and a portion of the second insulating interlayer32disposed around the bottom electrode contact layer34. For example, the trench69may be formed in a portion of the first insulating layer68corresponding to the bottom electrode contact layer34and a portion of the second insulating interlayer32disposed around the bottom electrode contact layer34. The trench69may be filled with an insulating layer38.

Referring toFIG. 18, an adhesive layer40may be formed on the first phase change layer68to cover the insulating layer38. A top electrode42may be formed on the adhesive layer40. A photoresist pattern80may be formed on the top electrode42to define a region in which a storage node may be formed. The top electrode42, the adhesive layer40, and the first phase change layer68may be sequentially etched using the photoresist pattern80as an etch mask. This etching process may be performed until the second insulating interlayer32is exposed. After the etching process is completed, the photoresist pattern80may be removed.

Because the processes performed until forming a bottom electrode contact layer34on a second insulating interlayer32may be the same as the processes of the above-described example embodiment, a detailed description of this example embodiment will begin with subsequent processes.

Referring toFIG. 19, a first phase change layer36amay be formed on the second insulating interlayer32. An insulating layer38may be formed on a first region of the first phase change layer36a. In this example embodiment, the insulating layer38may be formed to the above-described thickness. The insulating layer38may have a central region corresponding to the bottom electrode contact layer34and may extend onto a portion of the second insulating interlayer32disposed around the bottom electrode contact layer34.

Referring toFIG. 20, a second phase change layer36bmay be formed on the first phase change layer36ato cover the insulating layer38, and a top surface of the second phase change layer36bmay be planarized. First insulating layers39may be formed on the planarized top surface of the second phase change layer36b. The first insulating layers39may be formed spaced at intervals on the insulating layer38. The interval between the first insulating layers39may be controlled within the range of the insulating layer38. A third phase change layer36cmay be formed on the first insulating layers39to fill a space between the first insulating layers39.

Referring toFIG. 21, a second insulating layer41may be formed on a region of the third phase change layer36c. The second insulating layer41may be formed in the same shape and/or to the same thickness as the insulating layer38. The second insulating layer41may be formed in a position corresponding to the position of the space between the first insulating layers39. A fourth phase change layer36dmay be formed on the third phase change layer36cto cover the second insulating layer41, and a top surface of the fourth phase change layer36dmay be planarized.

Referring toFIG. 22, third insulating layers43may be formed on the planarized top surface of the fourth phase change layer36d. The third insulating layers43may be formed spaced at intervals, and a space between the third insulating layers43may be positioned over the second insulating layer41. The space between the third insulating layers43may be controlled within the range of the second insulating layer41. The insulating layer38and the first through third insulating layers39,41, and43may be formed of SiO2or other insulating material, for example, nitride or the like. The insulating layer38and the first through third insulating layers39,41, and43may be wholly or partially formed of different insulating materials. For example, the insulating layer38and the second insulating layer41may be formed of SiO2or the like, while the first and third insulating layers39and43may be formed of other insulating materials.

Referring toFIG. 23, a fifth phase change layer36emay be formed on the third insulating layers43to fill a space between the third insulating layers43, and a top surface of the fifth phase change layer36emay be planarized. The first through fifth phase change layers36ato36emay be formed of the same phase change material, such as GST or other chalcogenide material. Alternatively, at least some of the phase change layers36athrough36emay be formed of other phase change material than remaining phase change layers among36athrough36e. An adhesive layer40and a top electrode42may be sequentially formed on the planarized top surface of the fifth phase change layer36e. A photoresist pattern90may be formed on the top electrode42to define a region in which a storage node may be formed. In this example embodiment, the photoresist pattern90may be formed in a position for defining the insulating layer38, the first and second phase change layers36aand36bdisposed around the insulating layer38, the second insulating layer41and the third and fourth phase change layers36cand36ddisposed around the second insulating layer41.

Considering a positional relationship between the insulating layer38and the first insulating layers39and a positional relationship between the second insulating layer41and the third insulating layers43, the space between the first insulating layers39and its adjacent portions of the first insulating layers39and the space between the third insulating layers39and its adjacent portions of the third insulating layers39may be defined by the photoresist pattern90.

A stacked structure formed on the second insulating interlayer32may be sequentially etched using the photoresist pattern90as an etch mask. The etching process may be performed to expose the second insulating interlayer32. As a result, as illustrated inFIG. 24, a stack structure including a phase change layer36having the first through fifth phase change layers36ato36e, the insulating layers38,39,41, and43, the adhesive layer40, and the top electrode42may be formed on the bottom electrode contact layer34and a portion of the second insulating interlayer32disposed around the bottom electrode contact layer34. In the stacked structure, the insulating layers38,39,41, and43may be arranged to expand a current path between the bottom electrode contact layer34and the top electrode42.

After the etching process is completed, the photoresist pattern90may be removed.

A method of operating the phase change memory device according to an example embodiment will now be described.

An example embodiment of a method of operating the phase change memory device shown inFIG. 1will be described as an example. However, methods according to example embodiments may be also applied to other phase change memory devices such as those shown inFIGS. 3 through 5.

Referring again toFIG. 1, a first voltage higher than a threshold voltage may be applied to a gate electrode19such that a transistor remains turned on. An operating voltage may be applied between a top electrode42and a bottom electrode30. In at least this example embodiment, the operating voltage may be a voltage for supplying a reset current (e.g., a write voltage). In another example embodiment, the operating voltage may be a voltage for supplying a set current (e.g., an erase voltage). In still another example embodiment, the operating voltage may be a voltage for supplying a current between the reset current and the set current (e.g., a read voltage).

As will be appreciated from the following simulation results, when the operating voltage is a write voltage, a reset current for changing a region between an insulating layer38and a bottom electrode contact layer34into an amorphous state may decrease smaller than in the conventional art.

When the operating voltage is a read voltage, a measured current flowing through the phase change layer36may be compared with a reference current. When the measured current is smaller than the reference current, a partial region of the phase change layer36disposed on a current path may be in an amorphous state. As a result, a data “1” may be written in the phase change memory device ofFIG. 1. By contrast, when the measured current is larger than the reference current, a data “0” may be written in the phase change memory device ofFIG. 1. Although data “1” and “0” have been described with regard to particular voltage levels, data may be read and/or written reversely.

An example simulation for showing a variation of a reset current for forming an amorphous region in a phase change layer according to an insulating layer included in the phase change layer of the phase change memory device according to an example embodiment and the temperature distribution obtained when the reset current is supplied was conducted.

FIG. 25is a plan view of a storage node of the phase change memory device used in the simulation.FIG. 26illustrates a portion of a section cut along a direction26-26′ ofFIG. 25. The plan view ofFIG. 25is seen in the arrow direction inFIG. 26.FIG. 26illustrates only an upper portion of the section of the laid resultant structure for the sake of clarity and convenience.

Referring toFIGS. 25 and 26, the phase change layer99, an insulating layer93, and a bottom electrode contact layer95were all processed as a cylindrical type during the simulation.

In the simulation, the phase change layer99was formed of GST, the bottom electrode contact layer95was formed of TiAlN, and the insulating layer93was formed of SiO2. The reference numeral97denotes an insulating layer formed of SiO2. The simulation was performed twice under different conditions.

In the first simulation, an interval between the insulating layer93and the bottom electrode contact layer95was maintained constant, and the insulating layer93was formed to have different diameters W2of about 50 nm and about 100 nm, respectively.

For the second, a diameter W2of the insulating layer93was fixed at a larger value than a diameter W1of the bottom electrode contact layer95, while an interval between the insulating layer93and the bottom electrode contact layer95was formed to different values of about 30 nm and about 10 nm, respectively.

In the two cases, a diameter W3of the phase change layer99was fixed at about 250 nm, and the diameter W1of the bottom electrode contact layer95was fixed at about 50 nm. Also, a conventional phase change memory device in which a phase change layer does not include an insulating layer was compared with the phase change memory devices according to example embodiments in the simulation.

FIGS. 27 through 31are photographic images of simulation results showing a variation of a reset current and the temperature distribution of a phase change memory layer of the phase change memory devices according to example embodiments when an insulating layer is included in the phase change memory layer.

FIGS. 27 through 29show results under the foregoing first conditions.FIG. 27is a photographic image of simulation results of the conventional phase change random access memory (PRAM), whileFIGS. 28 and 29are photographic images of simulation results of the PRAM according to example embodiments.FIG. 28shows a case where the diameter W2of the insulating layer93was about 50 nm like the diameter W1of the bottom electrode contact layer95, andFIG. 29shows a case where the diameter W2of the insulating layer93was about 100 nm.

Referring toFIGS. 27 through 29, in the conventional PRAM and PRAMs according to example embodiments, a temperature measured in a region where the phase change layer99contacts the bottom electrode contact layer95was sufficiently raised so as to change the region into an amorphous region.

However, a reset current Iresetof the conventional PRAM was 2.04 mA as shown inFIG. 27, while reset currents Iresetof the PRAMs according to example embodiments were 1.94 mA and 1.88 mA, respectively, which are smaller than the reset current Iresetof the conventional PRAM, as shown inFIGS. 28 and 29.

Even if the diameter W2of the insulating layer93was equal or substantially equal to the diameter W1of the bottom electrode contact layer95, the reset current Iresetof the PRAM according to example embodiments was smaller than that of the conventional PRAM. Also, when the insulating layer93is included in the phase change layer99, as a difference between the diameter W2of the insulating layer93and the diameter W1of the bottom electrode contact layer95increased, the reset current Iresetof the PRAM according to example embodiments decreased.

FIGS. 30 and 31show results under the foregoing second conditions according to example embodiments.FIG. 30shows a case where an interval between the insulating layer93and the bottom electrode contact layer95was about 30 nm, andFIG. 31shows a case where the interval between the insulating layer93and the bottom electrode contact layer95was about 10 nm.

Referring toFIG. 30, when the diameter W2of the insulating layer93was greater than the diameter W1of the bottom electrode contact layer95and the interval between the insulating layer93and the bottom electrode contact layer95was 30 nm, the reset current Iresetwas 1.88 mA, and a region of the phase change layer99in contact with the bottom electrode contact layer95was completely changed into an amorphous region.

Referring toFIG. 31, when the diameter W2of the insulating layer93was greater than the diameter W1of the bottom electrode contact layer95and the interval between the insulating layer93and the bottom electrode contact layer95was about 10 nm, the reset current Iresetwas 1.472 mA, and only a region of the phase change layer99in contact with an edge of the bottom electrode contact layer95was changed into an amorphous region.

From the results ofFIGS. 30 and 31, when the diameter W2of the insulating layer93was greater than the diameter W1of the bottom electrode contact layer95, as the interval between the insulating layer93and the bottom electrode contact layer95decreased, the reset current Iresetdecreased, and a smaller region of the insulating layer93in contact with the edge of the bottom electrode contact layer95was changed into an amorphous region.

As described above, the phase change memory device according to example embodiments include an insulating layer disposed in the phase change layer opposite to the bottom electrode contact layer. Due to the insulating layer, a program volume of the phase change layer changed into an amorphous region may narrow, and current density may increase in the program volume. As a result, the program volume may change into the amorphous region with a smaller current than in the conventional art.

Also, a current path between the bottom electrode contact layer and the top electrode may expand due to the insulating layer. Thus, a resistance in the current path may increase, so that the amorphous region may form in the phase change layer using a smaller reset current than in the conventional art.

Therefore, the reset current of the phase change memory device according to example embodiments may be further reduced by considering both a reduction in the program volume and an increase in the current path.

According to example embodiments, a phase change memory device may reduce reset current due to the insulating layer included in the phase change layer. The reset current of the phase change memory device may be further reduced by controlling the diameter of the insulating layer and a positional relationship between the bottom electrode contact layer and the insulating layer. As a result, the integration density of the phase change memory device may increase.

The insulating layer included in the phase change layer may suppress, prevent and/or cut off the transmission of heat from the external environment into the program volume (e.g., the amorphous region) of the phase change layer. Therefore, the phase change memory device according to example embodiments may prevent data from being changed and/or lost due to external heat. In other words, the reliability of the phase change memory device according to example embodiments may be maintained constant in a relatively poor external environment characterized, for example, in relatively high temperatures.

In example embodiments, the phase change layers may include phase change materials, for example, chalcogenide alloys such as germanium-antimony-tellurium (Ge—Sb—Te), arsenic-antimony-tellurium (As—Sb—Te), tin-antimony-tellurium (Sn—Sb—Te), or tin-indium-antimony-tellurium (Sn—In—Sb—Te), arsenic-germanium-antimony-tellurium (As—Ge—Sb—Te). Alternatively, the phase change material may include an element in Group VA-antimony-tellurium such as tantalum-antimony-tellurium (Ta—Sb—Te), niobium-antimony-tellurium (Nb—Sb—Te) or vanadium-antimony-tellurium (V—Sb—Te) or an element in Group VA-antimony-selenium such as tantalum-antimony-selenium (Ta—Sb—Se), niobium-antimony-selenium (Nb—Sb—Se) or vanadium-antimony-selenium (V—Sb—Se). Further, the phase change material may include an element in Group VIA-antimony-tellurium such as tungsten-antimony-tellurium (W—Sb—Te), molybdenum-antimony-tellurium (Mo—Sb—Te), or chrome-antimony-tellurium (Cr—Sb—Te) or an element in Group VIA-antimony-selenium such as tungsten-antimony-selenium (W—Sb—Se), molybdenum-antimony-selenium (Mo—Sb—Se) or chrome-antimony-selenium (Cr—Sb—Se).

Although the phase change material is described above as being formed primarily of ternary phase-change chalcogenide alloys, the chalcogenide alloy of the phase change material could be selected from a binary phase-change chalcogenide alloy or a quaternary phase-change chalcogenide alloy. Example binary phase-change chalcogenide alloys may include one or more of Ga—Sb, In—Sb, In—Se, Sb2—Te3or Ge—Te alloys; example quaternary phase-change chalcogenide alloys may include one or more of an Ag—In—Sb—Te, (Ge—Sn)—Sb—Te, Ge—Sb—(Se—Te) or Te81—Ge15—Sb2—S2alloy, for example.

In an example embodiment, the phase change material may be made of a transition metal oxide having multiple resistance states, as described above. For example, the phase change material may be made of at least one material selected from the group consisting of NiO, TiO2, HfO, Nb2O5, ZnO, WO3, and CoO or GST (Ge2Sb2Te5) or PCMO(PrxCa1-xMnO3). The phase change material may be a chemical compound including one or more elements selected from the group consisting of S, Se, Te, As, Sb, Ge, Sn, In and Ag.