Systems and methods for acquiring modified rate burst demodulation in servo systems

Various embodiments of the present invention provide systems and methods for performing modified rate burst demodulation. For example, a method for performing modified rate burst demodulation is disclosed. The method includes receiving a data input that includes a synchronization pattern, an information pattern, and a demodulation pattern. A periodic boundary is established along with a phase and frequency of a sampling clock based at least in part on the synchronization pattern. The information pattern is processed using the sampling clock to determine a location fix. The sampling clock is phase shifted by a skew amount and a phase shifted sampling clock is provided. The demodulation pattern is processed using the phase shifted sampling clock.

BACKGROUND OF THE INVENTION

The present inventions are related to systems and methods for operating a servo system, and more particularly to system and methods for performing burst demodulation in a servo system.

A read channel integrated circuit (IC) is one of the core electronic components in a magnetic recording system such as a hard disk drive. A read channel converts and encodes data to enable magnetic read heads to write data to the disk drive and then read back the data accurately. The disks in a drive typically have many tracks on them. Each track typically consists of user data sectors, as well as control or “servo” data sectors embedded between the user sectors. The servo sectors help to position the magnetic recording head on a track so that the information stored in the read sectors is retrieved properly.

FIG. 1adepicts a data format of a servo data sector100. As shown, servo data sector100may include a preamble pattern102which allows the system to recover the timing and gain of the written servo data. Preamble pattern102is typically followed by a servo address mark (SAM)104which is the same for all servo sectors. SAM104is then followed by encoded servo GRAY data106, and GRAY data106is followed by one or more burst demodulation fields108. GRAY data106may represent the track number/cylinder information and provides coarse positioning information for a read head traversing a magnetic storage medium. Burst demodulation field108provides fine positioning information for the read head traversing a magnetic storage medium. Burst demodulation field108typically includes sine waves written to a medium that can be used for retrieving head position information relative to the medium. Traditional systems use full rate demodulation where the frequency of the sine waves match that of preamble pattern102. Thus, any timing acquisition done based on preamble pattern102may be applied to burst demodulation field108.FIG. 1bshows the aforementioned servo data sector100incorporated as part of each of a number of tracks160each extending in a radial pattern around a radial magnetic storage medium150. In an ideal case, a read head traverses an individual track over alternating servo data sectors and user data sectors.

When synchronizing to magnetic storage medium150, data obtained using a read head traversing the medium is typically equalized to a desired target partial response by an equalizer configured as a continuous time filter (CTF) followed by a discrete-time finite impulse response (FIR) filter. In a synchronous system, the sampling of the CTF output signal uses timing information generated by a digital phase-locked loop (DPLL) locked to the symbol rate. The output samples of the equalizer are quantized to digital sample values (‘Y’ values) using an A/D converter (ADC). The ‘Y’ values are applied to a data detector (e.g., threshold detector or Viterbi detector). A SAM detector then searches for the SAM bit pattern in the detected data. Once SAM is detected, the GRAY code decoder decodes the data following the SAM data as GRAY data. The burst demodulation is timed with respect to the detected SAM data based on known lengths of the SAM and GRAY data. The detected SAM data thus serves as a reference for timing of the burst demodulation operation.

FIG. 2depicts a prior art burst demodulation system200that may be used in relation to a servo system. An input signal202is received via an analog coupling stage205, an automatic gain control circuit210, and a continuous time filter222. Input signal202intermittently includes servo data that is used to direct the sampling rate and sampling phase used for data within a given sector. A digital phase lock loop circuit235provides a clock output237that controls the points at which input signal202is sampled by an analog to digital converter230. The phase and frequency of clock output237is adjusted based on an error signal provided by a phase/frequency detector280. Phase frequency detector280generates the error and a slope based on the output from analog to digital converter230. The error and slope signals from phase/frequency detector circuit280cause an adjustment to the phase and/or frequency of clock output237, and continues to cause an adjustment until the error signal goes to zero.

In addition, the digital samples from analog to digital converter230are provided to a digital FIR filter240and to one or more digital interpolators245. Digital interpolators245are operable to identify an incoming preamble signal and to determine the optimal phase/frequency for sampling the preamble. In particular, the processing of the preamble develops periodic boundaries (T) corresponding to the symbol rate defining the sampling times that are used in processing a subsequent SAM pattern and GRAY code pattern using a SAM detect and GRAY code detect circuit255to, among other things, identify the SAM incorporated in input signal202. SAM detect and GRAY code detect circuit255provides a SAM found output signal257indicating that the SAM has been identified. A burst demod circuit260then seeks to identify the burst demodulation information incorporated in input signal202.

In typical existing servo systems, processing a full rate burst demodulation pattern hinges only on proper assertion of the SAM found output signal. In particular, the burst demodulation information is found by counting a defined number of periodic boundaries (T) from SAM found output signal257.FIG. 3depicts such a situation where sampling to identify a SAM pattern301is indicated by vertical lines303,305separated by four periodic boundaries (i.e., 4T). A SAM found output307is asserted coincident with sample305. An intervening GRAY code309is decoded, followed by detection of a full rate burst demodulation pattern311. The peak of a full rate burst demodulation pattern is an integer multiple (n) of periodic boundaries (T) (i.e., nT313) from SAM found output307. Of note, the sine of the sample is much greater than the cosine where the sample is taken near its peak. Such a situation results in a high signal to noise ratio.

This process of performing burst demodulation processing works very well where for full rate burst demodulation patterns as the peaks of the patterns occur an integer multiple of periodic boundaries from the SAM found signal. There are trends in the art, however, to use half rate demodulation patterns in place of the aforementioned full rate patterns. Such patterns offer a variety of advantages, but they do not typically align on periodic boundaries measurable from the SAM found signal. In some cases, while such half rate demodulation patterns offer some advantages, they can be difficult to detect and process.

Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for performing burst demodulation.

BRIEF SUMMARY OF THE INVENTION

The present inventions are related to systems and methods for operating a servo system, and more particularly to system and methods for performing burst demodulation in a servo system.

Various embodiments of the present invention provide hard disk drive systems. Such hard disk drive systems include a read channel device that includes a servo data processing circuit. The servo data processing circuit receives an analog input that includes servo data. The servo data includes a preamble pattern, a servo address mark pattern, a GRAY code pattern, and a burst rate demodulation pattern. The servo processing circuit includes an analog to digital converter that utilizes a sampling clock to provide a digital data input corresponding to the analog data input. A preamble pattern processing circuit receives at least the preamble pattern portion of the digital data input and is operable to establish a periodic boundary. The phase of the sampling clock at least indirectly corresponds to the established periodic boundary. A servo address mark processing circuit identifies a servo address mark found position. A clock generation circuit provides the sampling clock and is operable to phase shift the sampling clock by a skew amount. A burst mode demodulation processing circuit receives at least the burst rate demodulation pattern portion of the digital data input, and performs a modified rate burst mode demodulation using the phase shifted sampling clock. In one particular instance of the aforementioned embodiments, the phase shift by the skew amount is slowly implemented over the course of processing the GRAY code pattern. In various instances of the aforementioned embodiments, the periodic boundary recurs at a symbol rate, and the demodulation pattern is processed an integer number of periodic boundaries plus the skew amount after the location fix.

Other embodiments of the present invention provide methods for performing modified rate burst demodulation in a servo system. Such methods include receiving a data input that includes a synchronization pattern, an information pattern, and a demodulation pattern. A periodic boundary is established based at least in part on the synchronization pattern. A phase of a sampling clock used to receive the data input at least indirectly corresponds to the established periodic boundary. The information pattern is processed using the sampling clock to determine a location fix. The sampling clock is phase shifted by a skew amount and a phase shifted sampling clock is provided. The demodulation pattern is processed using the phase shifted sampling clock. In particular instances of the aforementioned embodiments, the modified rate burst demodulation pattern is a half rate burst demodulation pattern.

In some instances of the aforementioned embodiments, the data input includes servo data. In such instances, the synchronization pattern includes a preamble pattern of the servo data, the information pattern includes both a servo address mark pattern and a GRAY code pattern of the servo data, and the demodulation pattern is a modified rate burst demodulation pattern of the servo data. In some instances of the aforementioned embodiments, the location fix corresponds to the finding of the servo address mark within the servo address mark pattern. In various instances, the phase shift by the skew amount is slowly implemented over the course of processing the GRAY code pattern. In some cases, the skew amount is only partially implemented during processing of early portions of the GRAY code pattern, and the skew amount is fully implemented during processing of the final portions of the GRAY code pattern. The skew amount may be, but is not limited to, a user programmable skew amount or an automatically determined skew amount.

Yet other embodiments of the present invention provide servo systems. Such servo systems include an analog data input including a synchronization pattern, an information pattern, and a demodulation pattern. An analog to digital converter utilizes a sampling clock to provide a digital data input corresponding to the analog data input, and a synchronization pattern processing circuit receives at least a portion of the digital data input and is operable to establish a periodic boundary. A phase of the sampling clock at least indirectly corresponds to the established periodic boundary. An information pattern processing circuit is included that is operable to establish a position fix using the sampling clock. A clock generation circuit is included that is operable to provide the sampling clock, and to phase shift the sampling clock by a skew amount to provide a phase shifted sampling clock. A demodulation processing circuit operable to perform demodulation processing of the demodulation pattern using the phase shifted sampling clock.

This summary provides only a general outline of some embodiments of the invention. Many other objects, features, advantages and other embodiments of the invention will become more fully apparent from the following detailed description, the appended claims and the accompanying drawings.

DETAILED DESCRIPTION OF THE INVENTION

The present inventions are related to systems and methods for operating a servo system, and more particularly to system and methods for performing burst demodulation in a servo system.

As mentioned above, there is a trend in the industry to switch to half rate burst demodulation. In half rate burst demodulation, the frequency of the burst sine wave defining the burst demod pattern is only one half that of the sine wave defining the preceding preamble pattern. Thus, if an integer multiple of the periodic boundaries developed during processing of the preamble pattern is used, it may not provide sampling points where the sine of the sample is much greater than the cosine during processing of the burst mode demodulation. In such cases, the signal to noise ratio may be substantially less than that desired.FIG. 4depicts such a scenario where sampling to identify a SAM pattern401is indicated by vertical lines403,405separated by four periodic boundaries (i.e., 4T). A SAM found output407is asserted coincident with sample305. An intervening GRAY code409is decoded, followed by detection of a modified rate burst demodulation pattern411. The peak of modified rate burst demodulation pattern411is not necessarily an integer multiple (n) of periodic boundaries (T) (i.e., nT413) from SAM found output407. Such a situation may result in substantially degraded signal to noise ratios. Further, because traditional analog front-end phase response (e.g., read channel analog front end) is not a constant between the frequency of the preamble pattern and that of a half rate burst demodulation pattern, there always exists a phase mismatch between the sampling instants (i.e., periodic boundaries) of the preamble and those of the half rate burst demodulation pattern when the signals are processed through an analog front-end with a non-linear phase response.

Various embodiments of the present invention provide for processing modified rate burst demodulation patterns. As used herein, the phrase “modified rate” is used in its broadest sense to mean anything other than a full rate or some integer multiple of a full rate. Thus, as one example, a half rate burst demodulation is considered a modified rate burst demodulation. Such embodiments of the present invention provide for initializing burst demodulation an integer multiple of a periodic boundary established during processing of the preamble pattern offset by a skew factor (i.e., nT+Skew). The skew factor represents a phase shift of the clock that is a fraction of T. In some cases, the skew factor is user programmable. Thus, the user knowing which form of burst mode demodulation is selected as well as the characteristics of the analog front end can determine a desired skew factor and program that factor into a register that is used during servo processing. Alternatively, in other cases the skew factor may be automatically generated during, for example, a calibration period where the peaks of multiple burst mode demodulation patterns are timed from the SAM found signal to establish a desired skew. In some cases, the sampling clock is adjusted upon receiving the SAM found signal. In particular, the phase shift may be introduced slowly during GRAY code processing intervening between identification of the SAM boundary and the beginning of burst demodulation processing. This slewing of the phase shift allows for reasonable processing of the GRAY code pattern, but assures proper alignment with the subsequent burst demodulation pattern in time for processing that pattern. Thus, by the time the burst demodulation pattern is sampled, the sampling clock is correctly adjusted and properly samples the modified rate sinusoid with the correct phase.

Turning toFIG. 5a, a skew adjusted burst demodulation system400is depicted in accordance with various embodiments of the present invention. Skew adjusted burst demodulation system400includes an input signal402that is received via an analog coupling stage405, an automatic gain control circuit410, and a continuous time filter422. Analog coupling stage405is tailored for receiving input signal402and converting that signal to a usable analog electrical signal. In one particular embodiment of the present invention, skew adjusted burst demodulation system400is implemented as part of a hard disk drive including a magnetic storage medium. In such an embodiment, analog coupling stage405may be tailored for detecting a magnetic field from the magnetic storage medium, and for converting the magnetic field to an analog electrical signal. It should be noted that, depending upon the application, analog coupling stage405may be tailored for converting an RF signal or other signal type to an analog electrical signal. The analog electrical signal is provided to automatic gain control circuit410that operates to perform gain control on the analog electrical signal. Continuous time filter422receives the analog electrical signal from automatic gain control410and provides a filtered output. In a synchronous system, the sampling of the output signal from continuous time filter422uses timing information from a digitally controlled clock generator480. It should be noted that other types of analog filters may be used in relation to different embodiments of the present invention. Based on the disclosure provided herein, one of ordinary skill in the art will recognize an appropriate analog filtering scheme that may be used in relation with different embodiments of the present invention.

The output from continuous time filter422is provided to an analog to digital converter430. Analog to digital converter430converts the filtered analog signal from continuous time filter422to produce a sequence of digital samples432. Digital samples432correspond to an original data set except that there may be some noise corruption. Analog to digital converter230may be any circuit, device or system known in the art that is capable of converting an electrical signal from the analog domain to the digital domain. Based on the disclosure provided herein, one of ordinary skill in the art will recognize a variety of analog to digital converters that may be used in relation to different embodiments of the present invention.

Samples432are provided in series to a phase/frequency detector circuit485that provides an error signal482indicating any phase and/or frequency error in a clock output437that is used to control the sample timing of analog to digital converter430. Error signal482may include both a slope error and phase error that are used as feedback to a digitally controlled clock generator480. As one example, phase/frequency detector485may be similar to that disclosed in U.S. Pat. No. 6,856,183 entitled “Scheme to Improve Performance of Timing Recovery Systems for Read Channels in a Disk Drive” and filed by Annampedu on Oct. 12, 2001. The entirety of the aforementioned patent is incorporated herein by reference for all purposes. As discussed therein, the phase/frequency detector circuit may include a slope look-up table (not shown) that is used to generate a slope output that is part of error signal482. Further, as discussed therein, the circuit compares the preliminary decisions from a detector (e.g., a Viterbi detector) and the raw output from analog to digital converter430. The aforementioned slope output and phase error may be combined into error signal482in a manner similar to that described in relation to FIG. 2 of U.S. patent application Ser. No. 11/841,033 entitled “Systems and Methods for Improved Timing Recovery”, and filed by Annampedu on Aug. 20, 2007. The entirety of the aforementioned patent application is incorporated herein by reference for all purposes. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize other implementations of phase/frequency detector circuits that may be used in relation to different embodiments of the present invention.

Digitally controlled clock generator480adjusts the frequency of clock output437based on error output482from phase/frequency detector circuit485. Further, digitally controlled clock generator480is capable of implementing a clock skew or phase shift that may be slowly incorporated into clock output437beginning from the detection of the SAM. This slewed clock skew or phase shift may be implemented via a phase offset value475that is provided to a digital phase lock loop circuit465. Phase offset value475is a known value obtained from a phase adjust register465, but that is ramped up slowly according to an algorithm implemented by a phase skew circuit470. The ramping process limits the amount of oscillation induced in digital phase lock loop circuit465due to the change. The process of ramping (i.e., slewing) phase offset value475is started when a SAM found output signal457is asserted. As will be appreciated from the disclosure provided herein, digitally controlled clock generator480is a decision directed loop that is operated based on input data stream and/or earlier decisions made in relation to the data stream to avoid latency in obtaining updated sample times. A more detailed diagram of digitally controlled clock generator480is discussed below in relation toFIG. 5b. It should be noted that alternatives to digitally controlled clock generator480may be used in relation to different embodiments of the present invention to provide clock synthesis and clock skewing. Based on the disclosure provided herein, one of ordinary skill in the art will recognize a variety of clock generator circuits capable of phase shifting and/or slew limited phase shifting that may be used.

Samples432are also provided in series to a digital FIR filter440and to one or more digital interpolators445. Digital interpolators445are operable to identify an incoming preamble signal and to determine the optimal phase/frequency for sampling the preamble. In particular, a best phase selection and phase update circuit450processes the preamble and develops periodic boundaries (T) defining the sampling times that are used in processing a subsequent SAM pattern and GRAY code pattern using a SAM detect and GRAY code detect circuit455to, among other things, identify the SAM incorporated in input signal402. SAM detect and GRAY code detect circuit455provides SAM found output signal457indicating that the SAM has been identified. A burst demod circuit460processes samples432beginning sometime after SAM found output signal457is asserted. In particular, burst demod circuit460performs burst demodulation beginning an integer multiple of the previously determined periodic boundaries (T) plus a clock skew factor corresponding to phase offset value475(i.e., nT+Skew).

Thus, in contrast to existing systems, the aforementioned embodiments of the present invention provides fractional phase compensation by slowly modifying the phase of the sample clock by a certain amount after SAM is found. In this way, modified rate burst demodulation information may be performed in much the same way that full rate demodulation is currently performed. The phase adjustment amount (i.e., the value written to phase adjust register465) to be slewed over GRAY code region can be pre-computed or hard-coded after the analog front-end setup is fixed. Alternatively, the phase adjustment amount (i.e., the value written to phase adjust register465) to be slewed over GRAY code region may be automatically generated during a calibration operation. Such automatic generation allows for optimizing the channel for a particular modified rate burst demodulation, such as, for example, a half rate burst demodulation. Using a reasonably robust asynchronous detector, a slow variation in timing over SAM and GRAY code fields does not compromise the SAM and GRAY code detection performance.

It should be noted that among other advantages, various embodiments of the present invention may be implemented through only minimal changes to an existing read channel architecture. As another advantage, some embodiments of the present invention provide a general ability to match phases between any two signals with arbitrary frequencies—not necessarily at half rate frequency. Furthermore, the idea can help to compensate for phase mismatches outside of a particular read channel device, such as those introduced by non-linear preamplifiers.

Turning toFIG. 5b, digitally controlled clock generator480is discussed in further detail. As shown, digitally controlled clock generator480receives error signal482along with a defined phase gain and frequency gain input. Again, in some cases, error signal482includes both error and slope information. A multiplier421receives error signal482and a frequency gain and provides the product thereof to a summation element425. Further, a multiplier423receives error signal482and a phase gain and provides the product thereof to a summation element427. Summation element425adds the product of multiplier421to a value maintained in a frequency register475, and provides the result back to frequency register475to perform an integration function. The value in frequency register475is provided to summation element427along with the product of multiplier423. The product of summation element427is provided to a phase offset register475that holds a phase offset value in part controlled by phase skew circuit470. Of note, phase skew circuit470causes the value in phase offset register475to slowly adjust to a value offset by a skew amount maintained in phase adjust register465. The value in phase offset register475is provided to a phase mixer circuit491which drives a voltage controlled oscillator433. Based on this input, voltage controlled oscillator generates clock output437. Of note, digitally controlled clock generator480is a decision directed loop that is operated based on input data stream and/or earlier decisions made in relation to the data stream to avoid latency in obtaining updated sample times. Again, it should be noted that digitally controlled clock generator480is only one implementation that may be used in relation to the various embodiments of the present invention, and that based on the disclosure provided herein, one of ordinary skill in the art will recognize other clock synthesizers or other circuits include slew rate controlled phase skew adjustment capabilities that allow for implementation of different embodiments of the present invention.

Turning toFIG. 6, an exemplary operation of skew adjusted burst demodulation system400is depicted in accordance with various embodiments of the present invention. Following the diagram, sampling is performed to identify a SAM pattern601as indicated by vertical lines603,605separated by four periodic boundaries (i.e., 4T). A SAM found output607is asserted coincident with sample605. An intervening GRAY code609is decoded using a clock that is being adjusted to add the skew needed for burst demodulation processing. Following processing of GRAY code information, detection of a modified rate burst demodulation pattern611is performed. Of note, by the time burst rate demodulation begins, the clock has been phase shifted by an amount designated “skew” on the diagram. Modified burst rate demodulation611aligns with an integer (n) multiplication of the periodic boundaries (T) plus “skew” (i.e., nT+Skew613) from SAM found output607. This provides a substantial increase in signal to noise ratio when compared with the scenario discussed above in relation toFIG. 4.

Turning toFIG. 7, a flow diagram700depicts a method in accordance with various embodiments of the present invention for performing burst demodulation. Following flow diagram700, filtered servo data is received (block705). The received servo data is interpolated (block710) and optimal periodic boundaries (T) are identified (block715). The servo data is processed including the SAM data pattern therein using the identified periodic boundaries (block720). This process of SAM identification continues until the SAM found signal is asserted indicating that SAM processing has completed (block725). At this point, processing of the succeeding GRAY code pattern is accomplished while at the same time the sampling clock is purposely skewed (block730). The sampling clock is skewed such that the sampling times are slowly phase shifted away from the periodic boundaries that were used during the preceding SAM processing. The slew rate at which the sampling clock is phase shifted is designed such that it allows for accepting and identifying the GRAY code pattern, but is shifted a desired skew amount before the subsequent burst demodulation process begins. In particular, this process of phase shifting the sampling clock is done before a defined integer number (n) of the previously determined periodic boundaries have passed since the SAM found signal was asserted (block735). Once the defined integer number of periodic boundaries has passed (block735), the process of burst demodulation is performed (block740). Because of the clock skewing, the sampling clock used during burst demodulation is the integral number of periodic boundaries (nT) plus a skew factor. This continues until burst demodulation completes (block745). Again, the skew factor may be preprogrammed into a register, or may be automatically calibrated through a process of identifying an optimal sampling point within the burst demodulation pattern, and determining the distance from the preceding SAM found point.