System and method for jitter negation in a high speed serial interface

A serial data channel includes a transmitter with a jitter generator that receives a jitter setting and injects a timing delay into an output signal of the transmitter in response to the jitter setting. The serial data channel further includes a receiver with an eye detector configured to evaluate a signal eye of the received output signal. The serial data channel provides a plurality of jitter settings to the jitter generator, and evaluates a plurality of signal eyes of the received output signal, where each signal eye of the plurality of signal eyes being associated with a particular received output signal generated in response to a particular one of the plurality of jitter settings. The serial data channel further selects a particular jitter setting of the plurality of jitter settings based upon the evaluation of the associated received output signal.

FIELD OF THE DISCLOSURE

This disclosure generally relates to information handling systems, and more particularly relates to jitter negation for improved channel performance in a high speed serial interface.

BACKGROUND

SUMMARY

A serial data channel can includes a transmitter and a receiver. The transmitter may include a jitter generator that can receive a jitter setting and inject a timing delay into an output signal of the transmitter in response to the jitter setting. The receiver can include an eye detector that can evaluate a signal eye of the received output signal. The serial data channel can provide a plurality of jitter settings to the jitter generator, and evaluate a plurality of signal eyes of the received output signal, where each signal eye of the plurality of signal eyes being associated with a particular received output signal generated in response to a particular one of the plurality of jitter settings. The serial data channel can further select a particular jitter setting of the plurality of jitter settings based upon the evaluation of the associated received output signal.

DETAILED DESCRIPTION OF DRAWINGS

Serial channel100includes a transmitter (TX)110, a transmission channel120, and a receiver (RX)130. Serial channel100represents one half of a bi-directional serial data link for communicating data from transmitter110located at a first component to receiver130located at a second component. The other half of the bi-directional serial data link is similar to serial channel100, but with a receiver in the first component, and a transmitter in the second component, for communicating data back from the second component to the first component. Here, the components can be understood to include elements within an information handling system, such as components that are attached to one or more printed circuit board of the information handling system, where transmission channel120can represent one or more circuit traces on the printed circuit board, and can include one or more connectors. The components can also be understood to include devices of an information handling system, such as a hard drive, a storage array, and the like, that are separate from the printed circuit board of the information handling system, where transmission channel120can include one or more transmission cables. An example of serial channel100may include a PCI-Express (PCIe) channel that is in compliance with an advanced PCIe specification, up to, and beyond the PCIe 4.0 Specification, a Serial ATA (SATA) channel that is in compliance with one or more SATA specification, up to, and beyond the SATA 3.2 Specification, an Ethernet channel including a 1000BASE-T channel, or beyond, or another high speed serial channel.

As the speed of high speed serial interfaces increases, maintaining good signal integrity across the channel becomes an increasingly difficult problem. Transmitter110includes a back-channel interface112and a jitter generator114, and receiver130includes a back-channel interface132and an eye detector134. Serial channel100operates to provide back-channel adaptation where transmitter110and receiver130communicate with each other via back-channel interfaces112and132to optimize and adjust various compensation values within the transmitter and the receiver to compensate for the insertion loss and cross-talk on transmission channel120. In a particular embodiment, back-channel interfaces112and132represent a separate communication channel between transmitter110and receiver130. In another embodiment, back-channel interfaces112and132represent a communication channel between transmitter110and receiver130that is established on another serial channel that is the other half of a bi-directional serial data link. In yet another embodiment, back-channel interfaces112and132represent a serial channel between transmitter110and receiver130that is part of a different bi-directional serial data link.

A determination is made as to whether or not a set of compensation values is satisfactory based upon a determination of the bit error rate (BER) associated with the set of values. It is possible for multiple different sets of compensation values to result in acceptable BER in serial channel100. Thus, when a particular set of compensation values is obtained through the back-channel adaptation, serial channel100further operates to adjust the particular set of compensation values to lower the settings of compensation mechanisms that are known to consume a greater amount of power, and to adjust other mechanisms to correct for the lowered settings, thereby reducing the power consumption of serial channel100, while maintaining an acceptable BER. Eye detector134operates to detect the signal eye generated at receiver130in response to the various compensation values, and to provide for the determination of the BER associated with the various compensation values.

Serial channel100experiences various deviations from true periodicity in both the signals transmitted by transmitter110and the signals received by receiver130. Such deviations include random jitter, the Gaussian white noise produced within the elements of serial channel100, and deterministic jitter, the noise produced by deterministic causes. Deterministic jitter includes periodic jitter, or sinusoidal jitter, inter-symbol interference, duty cycle distortion, and echo jitter. Periodic jitter may be related to various data patterns transmitted by serial channel100, to ground bounce in the circuits of the serial channel, or power supply variations in the serial channel. Inter-symbol interference is related to signal distortion when a signal bit is surrounded by signal bits of the opposite signal state, and may be caused by bandwidth limitations in transmission channel120. Duty cycle distortion is related to asymmetries in signal states, such as where transitions from logic “0” to logic “1” have different durations than transitions from logic “1” to logic “0”, and which may by improper bias settings or insufficient power supply capacities to the elements of serial channel100. Echo jitter is caused by mismatched components and trace lengths in the elements of serial channel100.

Jitter generator114represents hardware functions of transmitter110that operate to inject jitter, in the form of various timing shifts, into the signal states transmitted by transmitter110. Eye detector134then detects the signal eye generated at receiver130in response to the various timing shifts, and determines a set of timing shifts that contribute to a better BER for serial channel100. After determining the set of timing shifts, serial channel100performs back-channel adaptation as described above. Jitter generator114includes a unit interval change (AUI) generator116and a phase change (APhase) generator118.

FIG. 2illustrates a transmitter signal of transmitter110, as modified by the action of unit interval change generator116and phase change generator118. In particular, an unmodified transmitter signal200has a unit interval (UI). The UI of unmodified transmitter signal200is determined by the bandwidth of serial channel100. Note that serial channel100may have different operating modes that are each associated with a different bandwidth. Thus unmodified transmitter signal200is understood to be a generalized depiction of the unit interval of any of the various operating modes. Unit interval change generator116operates to modify the UI of one of the state transitions (i.e., low-to-high or high-to-low) in the transmitter signal of transmitter110. Here, unit interval change generator116operates to incrementally change the effective UI for the particular state transition. For example, unit interval change generator116provides an accelerated transition transmitter signal210, where the low-to-high transition occurs at a time equal to:
UIeff=UI−AΔx,(A=0,1,2, . . . ,p)  Equation 1
where UIeffis an effective UI for the low-to-high transition, Δx is an increment by which the unit interval change generator accelerates the low-to-high transition, A is an integer number of increments of Δx by which the low-to-high transition is accelerated, and p is a maximum number of increments by which the unit interval change generator can accelerate the low-to-high transition. Further, unit interval change generator116provides a decelerated transition transmitter signal212, where the low-to-high transition occurs at a time equal to:
UIeff=UI+AΔx,(A=1,2, . . . ,q)  Equation 2
where q is a maximum number of increments by which the unit interval change generator can decelerate the low-to-high transition. As such, unit cell change generator116has:
(p+q+1)  Equation 3
settings by which the low-to-high transition may be incremented. Note that Δx can be defined by a unit of time, by a percentage, or by another value that provides an increment for accelerating or decelerating the low-to-high transition. In another embodiment, unit cell change generator116operates to change the high-to-low transition UI instead of the low-to-high transition UI.

Phase change generator118operates to incrementally shift the phase of the UI of the transmitter signal of transmitter110. For example, phase change generator118provides an accelerated phase transmitter signal220, where the phase of the transmitter signal is:
Phaseeff=0°−BΔy,(B=0,1,2, . . . ,r)  Equation 4
where Phaseeffis an effective phase for the transmitter signal, Δy is an increment by which the phase change generator accelerates the phase of the transmitter signal, B is an integer number of increments of Δy by which the phase is accelerated, and r is a maximum number of increments by which the phase change generator can accelerate the phase of the transmitter signal. Further, phase change generator118provides a decelerated phase transmitter signal222, where the phase of the transmitter signal is:
Phaseeff=0°+BΔy,(B=1,2, . . . ,s)  Equation 5
where s is a maximum number of increments by which the phase change generator can decelerate the phase of the transmitter signal. As such, phase change generator116has:
(r+s+l)  Equation 6
settings by which the low-to-high transition may be incremented. Note that Δy can be defined by a unit of time, by a percentage, by a phase in degrees, or by another value that provides an increment for accelerating or decelerating the phase.

FIG. 3illustrates a method of jitter negation for improved channel performance in a high speed serial interface starting at block300. An auto-negotiation and link training of a high speed serial interface is initiated at block302. For example, a high speed serial link can conduct auto-negotiation and link training per an associated specification, such as a PCI-Express (PCIe) channel that is in compliance with an advanced PCIe specification, a Serial ATA (SATA) channel that is in compliance with one or more SATA specification, or an Ethernet channel specification. A knob setting for a unit interval change generator in a transmitter is set to its lowest setting, such that a particular signal transition is accelerated by a maximum number of increments, Δx, in block304. For example, unit interval change generator116can be set such that:
UIeff=UI−pΔxEquation 7.

An eye opening for the serial data signal provided by the transmitter is characterized in a receiver in block306. For example, eye detector134can determine the characteristics of the eye opening that results from the transmitter signal as modified in block304. In particular, an eye height, an eye width, or another characteristic of the signal eye can be captured by eye detector134. A decision is made as to whether or not the knob setting for the unit interval change generator is set to its highest setting, such that a particular signal transition is decelerated by a maximum number of increments, Δx, in decision block308. For example, a decision can be made as to whether or not unit interval change generator116is set such that:
UIeff=UI+qΔxEquation 8.
If not, the “NO” branch of decision block308is taken, the knob setting for the unit interval change generator is set to a next higher setting in block310, and the method returns to block306where the eye opening for the serial data signal provided by the transmitter is re-characterized.

If the knob setting for the unit interval change generator is set to its highest setting, the “YES” branch of decision block308is taken, the receiver determines a value for the setting for the unit interval change generator that generated a best eye opening, as characterized in block306, and sends the setting information to the transmitter in block312. For example, receiver130can evaluate the eye characteristics for the eyes characterized by eye detector134in block306, can select a “best” eye, and can communicate which delay setting generated the best eye to transmitter110via back channel interfaces112and132. A best eye can be determined based upon a maximum value for an eye height or eye width, based upon a highest average value for a product of the eye height and eye width, or based upon another characteristic of the eyes generated by eye detector134. The unit interval change generator is set with the delay setting that produced the best eye in block314.

A knob setting for a phase change generator in a transmitter is set to its lowest setting, such that the phase of the signal transmitted by the transmitter is accelerated by a maximum number of increments, Δy, in block316. For example, phase change generator118can be set such that:
Phaseeff=0°−rΔyEquation 9.
An eye opening for the serial data signal provided by the transmitter is characterized in a receiver in block318. For example, eye detector134can determine the characteristics of the eye opening that results from the transmitter signal as modified in block316. A decision is made as to whether or not the knob setting for the phase change generator is set to its highest setting, such that phase of the signal transmitted by the transmitter is decelerated by a maximum number of increments, Δy, in decision block320. For example, a decision can be made as to whether or not phase change generator118is set such that:
Phaseeff=0°+sΔyEquation 10.
If not, the “NO” branch of decision block320is taken, the knob setting for the phase change generator is set to a next higher setting in block322, and the method returns to block316where the eye opening for the serial data signal provided by the transmitter is re-characterized.

If the knob setting for the phase change generator is set to its highest setting, the “YES” branch of decision block320is taken, the receiver determines a value for the setting for the phase change generator that generated a best eye opening, as characterized in block318, and sends the setting information to the transmitter in block324. For example, receiver130can evaluate the eye characteristics for the eyes characterized by eye detector134in block318, can select a best eye, and can communicate which phase setting generated the best eye to transmitter110via back channel interfaces112and132. The phase change generator is set with the phase setting that produced the best eye in block326. The serial channel continues to determine the transmit and receive side equalization settings in block328, and the method ends in block330.

Information handling system400can include devices or modules that embody one or more of the devices or modules described above, and operates to perform one or more of the methods described above. Information handling system400includes a processors402and404, a chipset410, a memory420, a graphics interface430, include a basic input and output system/extensible firmware interface (BIOS/EFI) module440, a disk controller450, a disk emulator460, an input/output (I/O) interface470, and a network interface480. Processor402is connected to chipset410via processor interface406, and processor404is connected to the chipset via processor interface408. Memory420is connected to chipset410via a memory bus422. Graphics interface430is connected to chipset410via a graphics interface432, and provides a video display output436to a video display434. In a particular embodiment, information handling system400includes separate memories that are dedicated to each of processors402and404via separate memory interfaces. An example of memory420includes random access memory (RAM) such as static RAM (SRAM), dynamic RAM (DRAM), non-volatile RAM (NV-RAM), or the like, read only memory (ROM), another type of memory, or a combination thereof.

BIOS/EFI module440, disk controller450, and I/O interface470are connected to chipset410via an I/O channel412. An example of I/O channel412includes a Peripheral Component Interconnect (PCI) interface, a PCI-Extended (PCI-X) interface, a high speed PCI-Express (PCIe) interface, another industry standard or proprietary communication interface, or a combination thereof. Chipset410can also include one or more other I/O interfaces, including an Industry Standard Architecture (ISA) interface, a Small Computer Serial Interface (SCSI) interface, an Inter-Integrated Circuit (I2C) interface, a System Packet Interface (SPI), a Universal Serial Bus (USB), another interface, or a combination thereof. BIOS/EFI module440includes BIOS/EFI code operable to detect resources within information handling system400, to provide drivers for the resources, initialize the resources, and access the resources. BIOS/EFI module440includes code that operates to detect resources within information handling system400, to provide drivers for the resources, to initialize the resources, and to access the resources.

Disk controller450includes a disk interface452that connects the disc controller to a hard disk drive (HDD)454, to an optical disk drive (ODD)456, and to disk emulator460. An example of disk interface452includes an Integrated Drive Electronics (IDE) interface, an Advanced Technology Attachment (ATA) such as a parallel ATA (PATA) interface or a serial ATA (SATA) interface, a SCSI interface, a USB interface, a proprietary interface, or a combination thereof. Disk emulator460permits a solid-state drive464to be connected to information handling system400via an external interface462. An example of external interface462includes a USB interface, an IEEE 1394 (Firewire) interface, a proprietary interface, or a combination thereof. Alternatively, solid-state drive464can be disposed within information handling system400.

I/O interface470includes a peripheral interface472that connects the I/O interface to an add-on resource474, to a TPM476, and to network interface480. Peripheral interface472can be the same type of interface as I/O channel412, or can be a different type of interface. As such, I/O interface470extends the capacity of I/O channel412when peripheral interface472and the I/O channel are of the same type, and the I/O interface translates information from a format suitable to the I/O channel to a format suitable to the peripheral channel472when they are of a different type. Add-on resource474can include a data storage system, an additional graphics interface, a network interface card (NIC), a sound/video processing card, another add-on resource, or a combination thereof. Add-on resource474can be on a main circuit board, on separate circuit board or add-in card disposed within information handling system400, a device that is external to the information handling system, or a combination thereof.

Network interface480represents a NIC disposed within information handling system400, on a main circuit board of the information handling system, integrated onto another component such as chipset410, in another suitable location, or a combination thereof. Network interface device480includes network channels482and484that provide interfaces to devices that are external to information handling system400. In a particular embodiment, network channels482and484are of a different type than peripheral channel472and network interface480translates information from a format suitable to the peripheral channel to a format suitable to external devices. An example of network channels482and484includes InfiniBand channels, Fibre Channel channels, Gigabit Ethernet channels, proprietary channel architectures, or a combination thereof. Network channels482and484can be connected to external network resources (not illustrated). The network resource can include another information handling system, a data storage system, another network, a grid management system, another suitable resource, or a combination thereof.