Vertical transistors with different gate lengths

Techniques for forming VFETs with differing gate lengths are provided. In one aspect, a method for forming a VFET device includes: patterning fins in a substrate, wherein at least one of the fins includes a vertical fin channel of a FET1 and at least another one of the fins includes a vertical fin channel of a FET2; forming a bottom source and drain; forming bottom spacers on the bottom source and drain; forming gates surrounding the vertical fin channel of the FET1 and FET2; forming top spacers on the gate; and forming top source and drains at the tops of the fins by varying a positioning of the top source and drains relative to at least one of the vertical fin channel of the FET1 and the FET2 such that the FET1/FET2 have an effective gate length Lgate1/Lgate2, wherein Lgate1>Lgate2. A VFET device is also provided.

FIELD OF THE INVENTION

The present invention relates to vertical field effect transistors (VFETs), and more particularly, to techniques for forming VFETs with differing gate lengths on the same chip.

BACKGROUND OF THE INVENTION

As opposed to planar complementary metal-oxide-semiconductor (CMOS) devices, vertical field effect transistors (VFETs) are oriented with a vertical fin channel disposed on a bottom source/drain and a top source/drain disposed on the fin channel. VFETs have been pursued as a potential device option for scaling CMOS to the 5 nanometer (nm) node and beyond.

A reduction in chip power consumption can be realized by increasing the gate length (Lgate) of transistors (as compared to nominal transistors) along non-critical paths on the chip as this reduces off current leakage. However, it is difficult to implement FETs of differing lengths in VFET architecture due to challenges in aligning the junction with the physical gate.

Thus, techniques for effectively forming VFET devices with differing Lgate would be desirable.

SUMMARY OF THE INVENTION

The present invention provides techniques for forming vertical field effect transistors (VFETs) with differing gate lengths on the same chip. In one aspect of the invention, a method for forming a VFET device is provided. The method includes: patterning fins in a substrate using fin hardmasks, wherein at least one of the fins includes a vertical fin channel of a first FET device (FET1) and at least another one of the fins includes a vertical fin channel of a second FET device (FET2), and wherein the fins extend partway through the substrate; forming a bottom source and drain in the substrate beneath the fins; forming bottom spacers on the bottom source and drain; forming gates surrounding the vertical fin channel of the FET1and the vertical fin channel of the FET2; forming top spacers on the gates; and forming top source and drains at the tops of the fins, wherein the step of forming the top source and drains includes varying a positioning of the top source and drains relative to at least one of the vertical fin channel of the FET1and the vertical fin channel of the FET2such that the FET1has an effective gate length Lgate1and the FET2has an effective gate length Lgate2, and wherein Lgate1>Lgate2.

In another aspect of the invention, a VFET device is provided. The VFET device includes: fins patterned in a substrate, wherein at least one of the fins includes a vertical fin channel of a first FET device (FET1) and at least another one of the fins includes a vertical fin channel of a second FET device (FET2), and wherein the fins extend partway through the substrate; a bottom source and drain in the substrate beneath the fins; bottom spacers on the bottom source and drain; gates surrounding the vertical fin channel of the FET1and the vertical fin channel of the FET2; top spacers on the gates; and top source and drains at the tops of the fins, wherein a positioning of the top source and drains relative to the vertical fin channel of the FET1and the vertical fin channel of the FET2is different such that the FET1has an effective gate length Lgate1and the FET2has an effective gate length Lgate2, and wherein Lgate1>Lgate2.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Provided herein are techniques for effectively forming vertical field effect transistors (VFETs) with differing effective gate lengths (Lgate) on the same chip. Reference is made herein to ‘Wimpy’ VFETs, which are VFETs with an Lgate that is slightly greater than a nominal VFET transistor. For instance, the Lgate of a wimpy VFET is from about 1.5 nanometers (nm) to about 10 nm and ranges therebetween greater than the Lgate of a nominal VFET. As provided above, employing these ‘wimpy’ transistors along non-critical paths in the chip circuitry can reduce power consumption. Advantageously, the present techniques can be leveraged to form both types of VFET devices (i.e., wimpy and nominal VFETs) on the same chip.

In the description that follows reference will be made to two VFET designs, one having a longer gate length Lgate1, and another having a regular gate length Lgate2, i.e., Lgate1>Lgate2. As provided above, the difference between Lgate1and Lgate2, i.e., Lgate1−Lgate2, is from about 1.5 nm to about 10 nm and ranges therebetween. Reference will also be made to effective gate length and physical gate length. The effective gate length (Lgate) is the length of the gate in between the top and bottom source and drains. Namely, each of the VFET devices described herein will have an (undoped or lightly doped) vertical fin channel in between the top and bottom source and drains. The gate surrounds the vertical fin channel. The length of the gate alongside the vertical fin channel in between the top and bottom source and drains (heavily doped) is the effective gate length (Lgate). The gates themselves can be physically longer than the distance between the top and bottom source and drains. The actual length of the gate is the physical gate length. In the examples that follow, the effective gate length (Lgate) is less than the physical gate length.

Further, the physical gate length of all of the VFET devices can be the same. However, by adjusting the positioning of the top source and drains relative to the gate, the effective gate length (Lgate) can be varied to achieve Lgate1and Lgate2, wherein Lgate1>Lgate2. Thus, embodiments are contemplated herein where the VFET devices have the same physical gate length as one another but a different effective gate length (Lgate) from one another.

A first exemplary embodiment of the present techniques for fabricating a VFET device with different gate lengths is now described by way of reference toFIGS. 1-19. In the following example, the fabrication of one (nominal) VFET having the (shorter) gate length Lgate2(i.e., FET2in the following description) and one (wimpy) VFET having the (longer) gate length Lgate1(i.e., FET1in the following description) on the same chip will be described. However, it is to be understood that the process can be implemented in the same manner described to produce VFETs of either type in multiples and/or individually.

Referring toFIG. 1, the process begins with an undoped substrate102. According to an exemplary embodiment, substrate102is a bulk semiconductor wafer, such as a bulk silicon (Si), bulk germanium (Ge), bulk silicon germanium (SiGe) and/or bulk III-V semiconductor wafer. Alternatively, substrate102can be a semiconductor-on-insulator (SOI) wafer. A SOI wafer includes a SOI layer separated from an underlying substrate by a buried insulator. When the buried insulator is an oxide it is referred to herein as a buried oxide or BOX. The SOI layer can include any suitable semiconductor, such as Si, Ge, SiGe, and/or a III-V semiconductor.

One or more fins will be patterned in the substrate102. Generally, each of the VFETs formed herein will have a vertical fin channel extending up from the substrate. Top and bottom source and drains are situated in electrical contact with the top and bottom ends of the channel region, respectively. A gate is disposed on one or more of the fin sidewalls.

In this particular example, a doped epitaxial layer104is grown on the substrate102for use in forming the top source and drains. The bottom source and drains will be formed after fin patterning. However, as will be described in detail below, embodiments are anticipated herein where doped epitaxial layers for both the top and bottom source and drains are grown on the substrate102prior to fin patterning.

According to an exemplary embodiment, doped epitaxial layer104is formed from Si, Ge and/or SiGe that is in-situ (during epitaxial growth) or ex-situ (such as via ion implantation) doped with an n-type or p-type dopant. Suitable n-type dopants include, but are not limited to, phosphorous (P) and/or arsenic (As). Suitable p-type dopants include, but are not limited to, boron (B).

The next task is to pattern one or more fins in the substrate102and doped epitaxial layer104. To do so, a patterned fin hardmask202is first formed on the doped epitaxial layer104marking the footprint and location of the fins. Suitable hardmask materials include, but are not limited to, nitride hardmask materials such as silicon nitride (SiN). An etch using the fin hardmasks202is then used to pattern fins204in the substrate102and doped epitaxial layer104. SeeFIG. 2. An anisotropic etching process such as reactive ion etching (RIE) can be employed for the fin etch.

As shown inFIG. 2, the fin etch extends completely through the epitaxial layer104and partway into the substrate102, with a portion of the substrate102remaining intact beneath each of the fins204. As such, each of the fins204now includes a portion102a(formed from the substrate102) which will serve as the (undoped) vertical fin channel, and a portion104a(formed from the doped epitaxial layer104) which will be used to form the top source and drains.

As highlighted above, this example involves forming at least one (wimpy) VFET having the (longer) gate length Lgate1(i.e., FET1) and at least one (nominal) VFET having the (shorter) gate length Lgate2(i.e., FET2) on the same chip. The fins204that will be used in fabricating each of these devices are labeled “FET1” and “FET2,” respectively.

In this particular example, a bottom source and drain302is now formed in the substrate102beneath the fins204. SeeFIG. 3. According to an exemplary embodiment, the bottom source and drain302is formed using ion implantation. As provided above, suitable n-type dopants include phosphorous and/or arsenic, and suitable p-type dopants include, but are not limited to, boron. The (undoped) portion102aof each of the fins204above the bottom source and drain302serves as the vertical fin channel of the respective FET (i.e., FET1and FET2).

Ion implantation is only one of the techniques contemplated herein for forming the bottom source and drain302. For instance, a thermally-driven diffusion of dopants from a highly-doped epitaxial material (such as phosphorous-doped epitaxial Si (Si:P) or boron-doped epitaxial SiGe (SiGe:B)) deposited between the fins (not shown) can instead be used to form the bottom source and drain302. This technique is described, for example, in U.S. patent application Ser. No. 15/713,975 by Li et al., entitled “Vertical FET with Sharp Junctions,” the contents of which are incorporated by reference as if fully set forth herein.

Shallow trench isolation (STI) regions402are then formed in the substrate102in between the fins204. SeeFIG. 4. The STI regions402will isolate the VFET devices (i.e., FET1and FET2) from one another. The STI regions402are formed by forming trenches in the substrate102, filling the trenches with an insulator such as an STI oxide, and then recess-etching the STI oxide to the appropriate depth/thickness (e.g., using processes such as chemical-mechanical polishing (CMP) and RIE/wet etching). Suitable STI oxides include, but are not limited to, silicon dioxide (SiO2).

A bottom spacer502is then formed on the bottom source and drain302and on the fin hardmasks202. SeeFIG. 5. Suitable materials for the bottom spacer502include, but are not limited to, oxide spacer materials such as SiO2and/or silicon oxycarbide (SiOC) and/or nitride spacer materials such as SiN and/or silicon-boron-nitride (SiBN).

According to an exemplary embodiment, the bottom spacer502is formed using a directional deposition process whereby the spacer material is deposited onto the bottom source and drain302, fin hardmasks202and fins204with a greater amount of the material being deposited on horizontal surfaces (including on top of the bottom source and drain302in between the fins204), as compared to vertical surfaces (such as along sidewalls of the fins204). Thus, when an etch is used on the spacer material, the timing of the etch needed to remove the spacer material from the vertical surfaces will leave the bottom spacer502shown inFIG. 5on the bottom source and drain302and on the fin hardmasks202since a greater amount of the spacer material was deposited on the bottom source and drain302. By way of example only, a high density plasma (HDP) chemical vapor deposition (CVD) or physical vapor deposition (PVD) process can be used for directional film deposition, and an oxide- or nitride-selective (depending on the spacer material) isotropic etch can be used to remove the (thinner) spacer material deposited onto the vertical surfaces.

Next, a gate (i.e., a gate dielectric and a gate conductor) is formed surrounding each of the fins204. To form the gate, an interfacial oxide601(e.g., SiO2which may include other chemical elements in it such as nitrogen, germanium, etc.) is first formed selectively on exposed (e.g., Si/SiGe) surfaces of the fins204by an oxidation process to a thickness of from about 0.3 nm to about 5 nm, and ranges therebetween, e.g., about 1 nm. A conformal gate dielectric602is then deposited onto the fins204over the interfacial oxide601and over the bottom spacers502, and a conformal gate conductor604is deposited onto the gate dielectric602. SeeFIG. 6. According to an exemplary embodiment, a metal gate is formed wherein the gate conductor604is a metal or combination of metals and the gate dielectric602is a high-κ dielectric. For instance, the gate conductor604is a workfunction setting metal. The particular workfunction metal employed can vary depending on whether an n-type or p-type transistor is desired. Suitable n-type workfunction setting metals include, but are not limited to, titanium nitride (TiN), tantalum nitride (TaN) and/or aluminum (Al)-containing alloys such as titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), titanium aluminum carbide (TiAlC), tantalum aluminide (TaAl), tantalum aluminum nitride (TaAlN), and/or tantalum aluminum carbide (TaAlC). Suitable p-type workfunction setting metals include, but are not limited to, TiN, TaN, and tungsten (W). TiN and TaN are relatively thick (e.g., greater than about 2 nm) when used as p-type workfunction metals. However, very thin TiN or TaN layers (e.g., less than about 2 nm) may also be used beneath Al-containing alloys in n-type workfunction stacks to improve electrical properties such as gate leakage currents. Thus, there is some overlap in the exemplary n- and p-type workfunction metals given above.

The term “high-κ” as used herein refers to a material having a relative dielectric constant κ which is much higher than that of silicon dioxide (e.g., a dielectric constant κ=25 for hafnium oxide (HfO2) rather than 4 for SiO2). Suitable high-κ gate dielectrics include, but are not limited to, HfO2and/or lanthanum oxide (La2O3).

The gate dielectric602and gate conductor604need to be recessed to expose the tops of the fins204in order to permit formation of the top source and drain regions. To do so, a directional etching of the gate dielectric602and gate conductor604is first implemented to disconnect the gate dielectric602and gate conductor604between the fins, followed by a dielectric such as an organic planarizing layer (OPL)702being deposited onto the gate conductor604and bottom spacers502filling in the spaces between the fins204. SeeFIG. 7. Suitable OPL materials include, but are not limited to, aromatic cross-linkable polymers (such as naphthalene-based polymers). See, for example, U.S. Pat. No. 9,093,379 issued to Guillorn et al., entitled “Silicidation Blocking Process Using Optically Sensitive HSQ Resist and Organic Planarizing Layer,” the contents of which are incorporated by reference as if fully set forth herein.

The OPL702is then recessed to below the tops of the fins204. SeeFIG. 8. For instance, in the example depicted inFIG. 8the top of the (recessed) OPL702is now alongside the doped epitaxial portion104aof each fin204. As will become apparent from the description that follows, the recessed OPL702will set the physical gate length of each of the VFET devices being formed. As provided above, the physical gate length is the actual length of the gate. The physical gate length is different from the effective gate length (Lgate), i.e., the length of the gate between the top and bottom source and drains.

The gate dielectric602and gate conductor604are then also recessed. SeeFIG. 9. As shown inFIG. 9, the tops of the gate dielectric602and gate conductor604are now coplanar with the (recessed) top of the OPL702. Following recess of the gate dielectric602and gate conductor604, the remaining OPL702is removed. SeeFIG. 10.

As provided above, the physical gate length is established by the recess of OPL702/gate dielectric602and gate conductor604. Notably, the physical gate length of FET1and FET2are the same. SeeFIG. 10. However, as will be described in detail below, the effective gate length of the (wimpy) VFET (Lgate1of FET1in this example) vis-à-vis the (nominal) VFET (Lgate2of FET2in this example) will be varied relative to one another by adjusting the positioning of the top source and drains relative to the gate.

A conformal encapsulation layer1102is then formed on the fins204, bottom spacer502, and gate conductor604. SeeFIG. 11. As shown inFIG. 11, formation of the encapsulation layer1102provides top spacers1104over the gate. The top spacers1104and the counterpart bottom spacer502on top of the bottom source and drain302and the STI402serve to offset the gate from the top and bottom source and drains, respectively. Suitable materials for the encapsulation layer1102include, but are not limited to, oxide materials such as SiO2and/or silicon oxycarbide (SiOC) and nitride materials such as SiN and/or SiBN. According to an exemplary embodiment, the encapsulation layer1102and the bottom spacer502are both formed from the same material such that the top spacers1104and the bottom spacer502are both formed from the same material, e.g., SiOC or SiBN.

To enable further processing of the top source and drains, an interlayer dielectric (ILD)1202is next blanket deposited on the encapsulation layer1102over the fins204, filling the spaces between the fins204. SeeFIG. 12. Suitable ILD materials include, but are not limited to, oxide dielectric materials such as SiO2. Excess ILD1202is then removed, exposing the tops of the fin hardmasks202. SeeFIG. 13. A process such as chemical-mechanical polishing (CMP) can be employed in this step to polish the ILD1202down to the fin hardmasks202.

Once exposed, the fin hardmasks202are then removed. SeeFIG. 14. The fin hardmasks202can be removed using a nitride-selective etching process such as a nitride-selective reactive ion etching (RIE). As provided above, (like the fin hardmasks202) the encapsulation layer1102can also be formed from a nitride material such as SiN. Thus, the encapsulation layer1102at the tops of the fins204will be removed along with the fin hardmasks202. Namely, as shown inFIG. 14the encapsulation layer1102is now recessed below the top of the doped epitaxial portion104aof each fin204. However, if the encapsulation layer1102is a different material than the fin hardmasks202, the encapsulation layer1102can be selectively recessed to the appropriate depth after the removal of fin hardmasks202. The doped epitaxial portion104aof each fin204is now exposed.

As shown inFIG. 14, removal of the fin hardmasks202forms trenches in the ILD1202above each of the fins204. The doped epitaxial portion104aof each fin204is exposed at the bottoms of the trenches. The process to adjust the positioning of the top source and drains relative to the gate begins by forming sacrificial spacers1502along the sidewalls of the trenches above each of the fins204. Suitable materials for forming the sacrificial spacers1502include, but are not limited to, nitride spacer materials such as SiN and/or SiBN, or oxide spacer materials such as SiO2and/or SiOC. According to an exemplary embodiment, the sacrificial spacers1502are formed by depositing the respective spacer material into and filling the trenches, and then using an anisotropic etching process such as RIE to pattern the spacer material into the individual sacrificial spacers1502alongside the sidewalls of the trenches.

As will become apparent from the description that follows, the sacrificial spacers1502will be used during a recess etch into FET2(to adjust the positioning of the top source and drains in the FET2) to insure that a sliver of the vertical fin channel material remains separating the gate from the top source and drain regions in the (nominal) VFET devices (FET2in this example). Thus, as shown inFIG. 15the sacrificial spacers1502are configured to cover side portions of the doped epitaxial portion104aand underlying vertical fin channel portion102aof each fin204thereby preventing a sliver of the doped epitaxial portion104aand underlying vertical fin channel portion102aof the fin204in FET2from being recessed. For instance, the sacrificial spacers1502overlap the sides of the doped epitaxial portion104aby a distance x, wherein x is from about 1 nm to about 5 nm and ranges therebetween, e.g., 2 nm. According to an exemplary embodiment, the sacrificial spacers1502are formed having a width W1and the encapsulation layer1102is formed having a width W2, wherein W1>W2. SeeFIG. 15.

Up to this point, for ease of manufacture, all VFET devices have been processed the same (i.e., FET1and FET2have identical structures) even though the sacrificial spacers1502will only be used in the (nominal) VFET (FET2). However, selective processing is now needed to adjust the positioning of the top source and drains in the (nominal) VFET (FET2in this example). To do so, a block mask1602is formed covering the (wimpy) VFET (FET1in this example). SeeFIG. 16. Suitable block mask materials include, but are not limited to, photoresist materials such as OPL, oxide materials such as SiO2and/or SiOC and nitride materials such as SiN and/or SiBN.

An etch (an anisotropic etch such as RIE) is then performed between the sacrificial spacers1502in the (nominal) VFET (FET2) to recess the doped epitaxial portion104aand underlying vertical fin channel portion102aof the fin204in FET2. As shown inFIG. 16, following the recess a top of the vertical fin channel portion102aof the fin204in FET2is below a top of the vertical fin channel portion102aof the fin204in FET1. As also shown inFIG. 16, positioning the sacrificial spacers1502so as to overlap the doped epitaxial portion104a(see above) results in a sliver of the fin204remaining between the recess and the gate. That sliver of remaining fin will prevent exposing and damaging the interfacial oxide601, gate dielectric602and gate conductor604. As provided above, the sacrificial spacers1502are configured to overlap the sides of the doped epitaxial portion104aby a distance x of from about 1 nm to about 5 nm and ranges therebetween, e.g., 2 nm. Thus, the sliver of remaining fin will have a width W3(seeFIG. 16) that is equal to x (i.e., W3=x).

Following the selective recess etch in FET2, the block mask1602is removed from FET1. SeeFIG. 17. FET1and FET2will again be processed together. Namely, as shown inFIG. 18the sacrificial spacers1502are removed from both FET1and FET2(seeFIG. 18) and top source and drains1902and1904are formed in FET1and FET2, respectively (seeFIG. 19). In FET1the top source and drains1902are formed on the doped epitaxial portion104aof the fin204, whereas in FET2the top source and drains1904are formed in the recessed doped epitaxial portion104a/vertical fin channel portion102aof the fin204. According to an exemplary embodiment, the top source and drains1902and1904are formed from epitaxial Si, Ge and/or SiGe that is in-situ (during epitaxial growth) or ex-situ (such as via ion implantation) doped with an n-type or p-type dopant. As provided above, suitable n-type dopants include, but are not limited to, phosphorous (P) and/or arsenic (As), and suitable p-type dopants include, but are not limited to, boron (B).

As shown inFIG. 19, the top source and drains1902and1904have different positioning vis-à-vis their respective vertical fin channel portion102aof the fins204giving FET1and FET2different effective gate lengths Lgate1and Lgate2, respectively. Specifically, both FET1and FET2have a bottom junction at the interface between the bottom source and drains302and the vertical fin channel portion102aof the fins204. FET1has a top junction at the interface between the vertical fin channel portion102aand the doped epitaxial portion104aof the fin204. By contrast, FET2has its top junction at the interface between the vertical fin channel portion102aand the top source and drain1904. The longer effective gate length Lgate1in FET1results in a wimpy VFET while the shorter effective gate length Lgate2in FET2results in a nominal VFET (i.e., Lgate1>Lgate2).

Further, it is notable that while FET1and FET2have different effective gate lengths, FET1and FET2have the same physical gate length. Namely, as provided above, the gates (gate dielectric602and gate conductor604) were co-fabricated in FET1and FET2. Thus, the gates in FET1and FET2are physically the same. However, due to the selective placement of the top source and drains, the effective gate lengths (Lgate) in FET1and FET are different.

In the process flow just described a selective recess etch of FET2only was used to adjust the positioning of the top source and drain to produce VFETs with differing effective gate lengths (Lgate) on the same chip. According to another exemplary embodiment, this same process of a selective recess etch is used in both FET1and FET2with the recess being deeper in FET2than in FET1to produce VFETs with differing effective gate lengths (Lgate) on the same chip. This alternative exemplary embodiment is described by way of reference toFIGS. 20-26.

A number of the processes in this alternative embodiment are the same as shown and described above. Thus, for ease and clarity of description, steps which have already been individually depicted above may in some instance be combined into a single figure.

Since the placement of the top source and drains will be adjusted in both the (wimpy) FET1and (nominal) FET2based on the depth of the recess, a notable difference in this process flow is that a doped epitaxial layer104is not needed on the starting substrate. Namely, referring toFIG. 20, the process begins simply with an undoped substrate2002. According to an exemplary embodiment, substrate2002is a bulk semiconductor wafer, such as a bulk Si, bulk Ge, bulk SiGe and/or III-V semiconductor wafer. Alternatively, substrate2002can be an SOI wafer having an SOI layer (e.g., Si, Ge, SiGe and/or III-V semiconductor) separated from an underlying substrate by a buried insulator such as a buried oxide or BOX.

As shown inFIG. 20, a patterned fin hardmask2004is formed on the substrate2002marking the footprint and location of multiple fins. Suitable hardmask materials include, but are not limited to, nitride hardmask materials such as SiN. An etch with the fin hardmasks2004is then used to pattern fins2006in the substrate2002. An anisotropic etching process such as RIE can be employed for the fin etch.

As shown inFIG. 20, the fin etch extends partway into the substrate2002, with a portion of the substrate2002remaining intact beneath each of the fins2006. Each of the fins2006will serve as the (undoped) vertical fin channel of a FET. As above, this example involves forming at least one (wimpy) VFET having the (longer) gate length Lgate1(i.e., FET1) and at least one (nominal) VFET having the (shorter) gate length Lgate2(i.e., FET2) on the same chip. The fins2006that will be used in fabricating each of these devices are labeled “FET1” and “FET2,” respectively.

As in the process flow above, a process such as ion implantation is now used to form a bottom source and drain2102in the substrate2002beneath the fins2006. SeeFIG. 21. As provided above, suitable n-type dopants include phosphorous and/or arsenic, and suitable p-type dopants include, but are not limited to, boron. An (undoped) portion2002aof each of the fins2006above the bottom source and drain2102serves as the vertical fin channel of the respective FET (i.e., FET1and FET2).

After formation of the bottom source and drain2102, STI regions2104are formed in the substrate2002in between the fins2006. As described above, the STI regions2104serve to isolate the VFET devices (i.e., FET1and FET2) from one another.

A bottom spacer2106is next formed on the bottom source and drain2102and on the fin hardmasks2004. As provided above, suitable materials for the bottom spacer2106include, but are not limited to, oxide spacer materials such as SiO2and/or SiOC and/or nitride spacer materials such as SiN and/or SiBN.

According to an exemplary embodiment, the bottom spacer2106is formed using a directional deposition process whereby the spacer material is deposited onto the bottom source and drain2102, fin hardmasks2004and fins2006with a greater amount of the material being deposited on horizontal surfaces (including on top of the bottom source and drain2102in between the fins2006and on top of the fin hardmasks2004), as compared to vertical surfaces (such as along sidewalls of the fins2006). Thus, when an etch is used on the spacer material, the timing of the etch needed to remove the spacer material from the vertical surfaces will leave the bottom spacer2106shown inFIG. 21on the bottom source and drain2102(and also on the fin hardmasks2004—however inFIG. 21the bottom spacer2106on top of the fin hardmasks2004has already been removed) since a greater amount of the spacer material was deposited on the bottom source and drain2102and on the fin hardmasks2004. By way of example only, a HDP CVD or PVD process can be used for directional film deposition, and an oxide- or nitride-selective (depending on the spacer material) isotropic etch can be used to remove the (thinner) spacer material deposited onto the vertical surfaces.

Next, a gate (i.e., a gate dielectric and a gate conductor) is formed surrounding each of the fins2006. To form the gate, an interfacial oxide2107(e.g., SiO2which may include other chemical elements in it such as nitrogen, germanium, etc.) is first formed selectively on exposed (e.g., Si/SiGe) surfaces of the fins2006by an oxidation process to a thickness of from about 0.3 nm to about 5 nm, and ranges therebetween, e.g., about 1 nm. A conformal gate dielectric2108is deposited onto the fins2006over the interfacial oxide2107and over the bottom spacers2106, and a conformal gate conductor2110is deposited onto the gate dielectric2108. According to an exemplary embodiment, a metal gate is formed wherein the gate conductor2110is a metal or combination of metals and the gate dielectric2108is a high-κ dielectric. For instance, the gate conductor2110is a workfunction setting metal. The particular workfunction metal employed can vary depending on whether an n-type or p-type transistor is desired. As provided above, suitable n-type workfunction setting metals include, but are not limited to, TiN, TaN and/or Al-containing alloys such as TiAl, TiAlN, TiAlC, TaAl, TaAlN, and/or TaAlC. Suitable p-type workfunction setting metals include, but are not limited to, TiN, TaN, and W. Suitable high-κ gate dielectrics include, but are not limited to, HfO2and/or La2O3.

The gate dielectric2108and gate conductor2110are deposited as conformal layers covering the fins2006and, in the same manner as described above, the gate dielectric2108and gate conductor2110are recessed to expose the tops of the fins2006in order to permit formation of the top source and drain regions. The individual steps used to recess the gate dielectric2108and gate conductor2110using, for example a directional etching and a dielectric such as an OPL (not shown) masked etching, are described in conjunction with the description ofFIGS. 6-10, above.

Since the gates are being co-fabricated for each of the VFET devices, the gates are physically identical in FET1and FET2meaning that the physical gate length of FET1and FET2are the same. SeeFIG. 21. However, as will be described in detail below, the effective gate length of the (wimpy) VFET (Lgate1of FET1in this example) vis-à-vis the (nominal) VFET (Lgate2of FET2in this example) will be varied relative to one another by adjusting the positioning of the top source and drains relative to the gate. Notably, the way in which this adjustment is made involves separately processing each of FET1and FET2to control the recess depth of the vertical fin channel in each device (see below). By contrast, in the process flow provided above, the vertical fin channel of only FET2was recessed. While selective processing of each of FET1and FET2individually involves a tradeoff in terms of needing additional masking steps (see below), the positioning of the top source and drains for both FET1and FET2will be set at the end of the process and thus there is no need for a doped epitaxial portion in each fin.

As shown inFIG. 21, a conformal encapsulation layer2112is formed on the fins2006, bottom spacer2106, and gate conductor2110. Formation of the encapsulation layer2112provides top spacers2114over the gate. The top spacers2114and the counterpart bottom spacer2106serve to offset the gate from the top and bottom source and drains, respectively. Suitable materials for the encapsulation layer2112include, but are not limited to, oxide materials such as SiO2and/or silicon oxycarbide (SiOC), and nitride materials such as SiN and/or SiBN. According to an exemplary embodiment, the encapsulation layer2112and the bottom spacer2106are both formed from the same material such that the top spacers2114and the bottom spacer2106are both formed from the same material, e.g., SiOC or SiBN.

An ILD2116is blanket deposited over the encapsulation layer2112, filling the spaces between the fins2006, and then polished (e.g., using CMP) down to, and exposing, the fin hardmasks2004. As provided above, suitable ILD materials include, but are not limited to, oxide dielectric materials such as SiO2. SeeFIG. 21.

Once exposed, the fin hardmasks2004are then removed. SeeFIG. 22. The fin hardmasks2004can be removed using a nitride-selective etching process such as a nitride-selective RIE. As provided above, (like the fin hardmasks2004) the encapsulation layer2112can also be formed from a nitride material such as SiN. Thus, the encapsulation layer2112at the tops of the fins2006will be removed along with the fin hardmasks2004. Namely, as shown inFIG. 22the encapsulation layer2112is now recessed below the tops of the vertical fin channel portion2002aof each of the fins2006. However, if the encapsulation layer2112is a different material than the fin hardmasks2004, the encapsulation layer2112can be selectively recessed to the appropriate depth after the removal of fin hardmasks2004.

As shown inFIG. 22, removal of the fin hardmasks2004forms trenches in the ILD2116above each of the fins2006. The vertical fin channel portion2002aof each fin2006is exposed at the bottoms of the trenches. The process to adjust the positioning of the top source and drains relative to the gate begins by forming sacrificial spacers2302along the sidewalls of the trenches above each of the fins2006. As provided above, suitable materials for forming the sacrificial spacers2302include, but are not limited to, nitride spacer materials such as SiN and/or SiBN, or oxide spacer materials such as SiO2and/or SiOC. According to an exemplary embodiment, the sacrificial spacers2302are formed by depositing the respective spacer material into and filling the trenches, and then using an anisotropic etching process such as RIE to pattern the spacer material into the individual sacrificial spacers2302alongside the sidewalls of the trenches.

As will become apparent from the description that follows, the sacrificial spacers2302will be used to selectively perform recess etches to different depths in FET1and FET2(to adjust the positioning of the top source and drains) to insure that, following the recess etches, a sliver of the vertical fin channel material remains separating the gate from the top source and drain regions. Thus, as shown inFIG. 23the sacrificial spacers2302are configured to cover the side portions of vertical fin channel portion2002aof each fin2006thereby preventing a sliver of the vertical fin channel portion2002aof the fins2006in FET1and FET2from being recessed. For instance, the sacrificial spacers2302overlap the sides of the vertical fin channel portion2002aby a distance y, wherein y is from about 1 nm to about 5 nm and ranges therebetween, e.g., 2 nm. According to an exemplary embodiment, the sacrificial spacers2302are formed having a width W4and the encapsulation layer2112is formed having a width W5, wherein W4>W5. SeeFIG. 23.

Up to this point, all VFET devices have been processed the same (i.e., FET1and FET2have identical structures). However, in order to selectively set different recess depths in FET1and FET2(to adjust the positioning of the top source and drains) one FET must be masked while the other is processed, and vice versa. In the present example FET1will be masked first while a top recess etch is performed in FET2. The process is repeated by next masking FET2and performing a top recess etch (to a different depth) in FET2. This sequence is however arbitrary and either FET1or FET2can be masked/recessed before the other.

As shown inFIG. 24, a block mask2402is formed covering the (wimpy) VFET (FET1in this example). As provided above, suitable block mask materials include, but are not limited to, photoresist materials such as OPL, oxide materials such as SiO2and/or SiOC, and nitride materials such as SiN and/or SiBN.

An etch (an anisotropic etch such as RIE) is then performed between the sacrificial spacers2302in the (nominal) VFET (FET2in this example) to recess the vertical fin channel portion2002aof the fin2006in FET2to a depth D1. As shown inFIG. 24, positioning the sacrificial spacers2302so as to overlap the vertical fin channel portion2002a(see above) results in a sliver of the fin2006remaining between the recess and the gate. That sliver of remaining fin will prevent exposing and damaging interfacial oxide2107, gate dielectric2108and gate conductor2110. As provided above, the sacrificial spacers2302are configured to overlap the sides of the vertical fin channel portion2002aby a distance y of from about 1 nm to about 5 nm and ranges therebetween, e.g., 2 nm. Thus, the sliver of remaining fin will have a width W6(seeFIG. 24) that is equal toy (i.e., W6=y).

The block mask2402is removed from the FET1and the process is repeated to perform a recess etch in FET1to a depth D2, wherein D2<D1. Namely, as shown inFIG. 25the block mask2402is removed from the FET1and a block mask2502is formed covering the (nominal) VFET (FET2in this example).

An etch (an anisotropic etch such as RIE) is then performed between the sacrificial spacers2302in the (wimpy) VFET (FET1in this example) to recess the vertical fin channel portion2002aof the fin2006in FET1to a depth D2, wherein D2<D1. As shown inFIG. 25, following the recess a top of the vertical fin channel portion2002aof the fin2006in FET2is below a top of the vertical fin channel portion2002aof the fin2006in FET1. As also shown inFIG. 25, positioning the sacrificial spacers2302so as to overlap the vertical fin channel portion2002a(see above) results in a sliver of the fin2006remaining between the recess and the gate. That sliver of remaining fin will prevent shorting between the FET1top source and drains (which will be formed in the recess) and the gate. As provided above, the sacrificial spacers2302are configured to overlap the sides of the vertical fin channel portion2002aby a distance y of from about 1 nm to about 5 nm and ranges therebetween, e.g., 2 nm. Thus, the sliver of remaining fin will have a width W7(seeFIG. 25) that is equal to x (i.e., W7=y).

Following the selective recess etch in FET1, the block mask2502is removed from FET2and, as shown inFIG. 26, the sacrificial spacers2302are removed from both FET1and FET2and top source and drains2602and2604are formed in the recesses of FET1and FET2, respectively. According to an exemplary embodiment, the top source and drains2602and2604are formed from epitaxial Si, Ge and/or SiGe that is in-situ (during epitaxial growth) or ex-situ (such as via ion implantation) doped with an n-type or p-type dopant. As provided above, suitable n-type dopants include, but are not limited to, phosphorous (P) and/or arsenic (As), and suitable p-type dopants include, but are not limited to, boron (B).

As shown inFIG. 26, based on the different depths of the top recess etch, the top source and drains2602and2604(formed in the recesses) have different positioning vis-à-vis their respective vertical fin channel portion2002aof the fins2006giving FET1and FET2different effective gate lengths Lgate1and Lgate2, respectively. Specifically, both FET1and FET2have a bottom junction at the interface between the bottom source and drains2102and the vertical fin channel portion2002aof the fins2006. FET1has a top junction at the interface between the vertical fin channel portion2002aand the top source and drains2602the positioning of which is set by the recess etch depth D2. By contrast, FET2has its top junction at the interface between the vertical fin channel portion2002aand the top source and drain2604the positioning of which is set by the recess etch depth D1. The longer effective gate length Lgate1in FET1results in a wimpy VFET while the shorter effective gate length Lgate2in FET2results in a nominal VFET (i.e., Lgate1>Lgate2). Both FET1and FET2have the same physical gate lengths.

Further, it is notable that while FET1and FET2have different effective gate lengths, FET1and FET2have the same physical gate length. Namely, as provided above, the gates (gate dielectric2108and gate conductor2110) were co-fabricated in FET1and FET2. Thus, the gates in FET1and FET2are physically the same. However, due to the selective placement of the top source and drains, the effective gate lengths (Lgate) in FET1and FET2are different.

In the examples provided above, the bottom source and drains are formed (e.g., via implantation) following fin patterning. Embodiments are also anticipated herein where a doped epitaxial layer is placed on the substrate prior to fin patterning that will serve as the bottom source and drains below the vertical fin channel. See, for example, methodology2700ofFIG. 27and methodology2800ofFIG. 28. Methodology2700ofFIG. 27follows the process flow illustrated inFIGS. 1-19where a doped epitaxial layer (i.e., doped epitaxial layer104) is also placed on top of the vertical fin channel. Methodology2800ofFIG. 28follows the process flow illustrated inFIGS. 20-26where no prior doped epitaxial material (i.e., doped epitaxial layer104) is needed over the vertical fin channels.

Referring first to methodology2700ofFIG. 27, in step2702a first doped epitaxial layer2712is formed on a substrate2710, an undoped epitaxial layer2714is formed on the first doped epitaxial layer2712, and a second doped epitaxial layer2716is formed on the undoped epitaxial layer2714. Suitable (bulk and SOI) substrate2710configurations were provided above. In-situ or ex-situ doping can be used to dope epitaxial layers2712and2716. By way of example only, epitaxial layers2712and2716can be formed from doped epitaxial SiGe and undoped epitaxial layer2714can be formed from epitaxial Si, or vice versa.

In the same manner as described above, fin hardmasks2718are formed on top of the stack (i.e., substrate2710/first doped epitaxial layer2712/undoped epitaxial layer2714/second doped epitaxial layer2716) and used to pattern fins2720in the stack corresponding to at least one FET1and at least one FET2. See step2704. As shown in step2704, the fins2720extend completely through the second doped epitaxial layer2716and the undoped epitaxial layer2714, and partway through the first doped epitaxial layer2712. As such, each fin2720includes a portion2712a(formed from first doped epitaxial layer2712—which will serve as the bottom source and drain), a portion2714a(formed from the undoped epitaxial layer2714—which will serve as the vertical fin channel), and a portion2716a(formed from the second doped epitaxial layer2716—which will be used in the top source and drains).

In step2706, STI regions2722are then formed in between the fins2720. As provided above, the STI regions2722isolate the FET devices from one another. At this stage, the structure shown in step2706is equivalent to the structure shown inFIG. 4—described above. Thus, this alternative methodology2700may be performed prior to forming the bottom spacer502as shown inFIG. 5, with the balance of the process being the same as that described in conjunction with the description ofFIGS. 5-19, above.

Referring next to methodology2800ofFIG. 28, in step2802a doped epitaxial layer2812is formed on a substrate2810, and an undoped epitaxial layer2814is formed on the doped epitaxial layer2812. Suitable (bulk and SOI) substrate2810configurations were provided above. In-situ or ex-situ doping can be used to dope epitaxial layer2812. By way of example only, epitaxial layer2812can be formed from doped epitaxial SiGe and undoped epitaxial layer2814can be formed from epitaxial Si, or vice versa.

In the same manner as described above, fin hardmasks2816are formed on top of the stack (i.e., substrate2810/doped epitaxial layer2812/undoped epitaxial layer2814) and used to pattern fins2818in the stack corresponding to at least one FET1and at least one FET2. See step2804. As shown in step2804, the fins2818extend completely through the undoped epitaxial layer2814, and partway through the doped epitaxial layer2812. As such, each fin2818includes a portion2812a(formed from doped epitaxial layer2812—which will serve as the bottom source and drain), and a portion2814a(formed from the undoped epitaxial layer2814—which will serve as the vertical fin channel).

In step2806, STI regions2820are then formed in between the fins2818. As provided above, the STI regions2820isolate the FET devices from one another. At this stage, the structure shown in step2806is equivalent to the structure shown inFIG. 21(described above) onto which the bottom spacer2106, the gate (i.e., gate dielectric2108and gate conductor2110), the conformal encapsulation layer2112, and the ILD2116are formed. Thus, this alternative methodology2800may be performed prior to forming the bottom spacer2106, the gate (i.e., gate dielectric2108and gate conductor2110), the conformal encapsulation layer2112, and the ILD2116as shown inFIG. 21, with the balance of the process being the same as that described in conjunction with the description ofFIGS. 21-26, above.