Dead-time optimization of DC-DC converters

Representative implementations of devices and techniques determine the timing of switches associated with a dc-dc converter. The determination is based on a body diode conduction of at least one of the switches, which is detected and used to determine a switching delay.

BACKGROUND

Various mobile or portable electronic devices may have reduced power consumption by operating some of the systems within these devices at low voltages (e.g., 3.0 volts, 1.5 volts, etc.). Such electronic devices often use direct current to direct current converters (“dc to dc converters” or “dc-dc converters”) to “step down” voltages available from their power supplies to the lower voltages used by these systems.

In complex systems, e.g. microcontrollers or mobile communication systems, there may be several different power supply output voltage requirements. For example a digital block might need voltage scaling capability, whereas analog parts may need different supply voltages. In some cases, multiple dc-dc converters may be implemented within a complex device. For example, dc-dc converters may be integrated with various systems on-chip. However, dc-dc converter solutions often suffer from significant switching losses, especially when operated at higher switching frequencies.

Body diode conduction losses can be a major loss contributor, especially in high frequency dc-dc converters. These losses occur due to imperfect switching time instances of the power switches, which lead to current flow through the parasitic body diode of one or more power switches. Converters having fixed power switch timing often have poor efficiency since dc-dc converters operate over various process, voltage, and temperature (PVT) variations that may impact switch timing.

DETAILED DESCRIPTION

Overview

Representative implementations of techniques and/or devices provide power switch timing control of a dc-dc converter, and in particular, provide optimized coordination of input power switch timing to output power switch timing. In various implementations, the coordination is based on a measurement of body diode conduction in one or more power switches. Power switch timing may be dynamically adjusted with ongoing switching cycles, by introducing varying switching delays based on the measured body diode conduction.

Various implementations of power switch timing control for a dc-dc converter with respect to an example dc-dc converter design illustrated inFIG. 1are discussed. The representative dc-dc converter illustrates one example of techniques and devices as may be applied to an electronic device. Techniques and devices of power switch timing control are then discussed with reference to example sensing and control circuits, along with various related waveforms illustrated inFIGS. 2 and 3. The techniques and devices discussed may be applied to any of various dc-dc converter designs, circuits, and devices and remain within the scope of the disclosure. The illustrated waveforms show current through the coil in the example dc-dc converter, and demonstrate how a switch control determination may be made based on timing characteristics of the current waveforms and associated control signals. Example implementations of a body diode conduction sensor circuit and a dead time control unit circuit are then discussed with reference toFIGS. 4 and 5. Finally, this disclosure discusses example processes of controlling power switch timing of a dc-dc converter with reference to flow diagrams shown inFIGS. 6 and 7.

Implementations are explained in more detail below using a plurality of examples. Although various implementations and examples are discussed here and below, further implementations and examples may be possible by combining the features and elements of individual implementations and examples.

Example DC-DC Converter

FIG. 1is a schematic drawing showing an illustrative dc-dc converter circuit100, wherein an implementation of power switch timing control may be employed. It is to be understood that power switch timing control may be implemented as part of the dc-dc converter circuit100, or as part of another system (e.g., as a peripheral to a dc-dc converter100, etc.). The illustrated dc-dc converter inFIG. 1is shown and described in terms of a “buck” device, which reduces the input DC voltage (VBAT) to a desired lower output DC voltage (VOUT). This illustration is, however, for ease of discussion. The techniques and devices described herein with respect to power switch timing control for dc-dc converters is not limited to the circuit illustrated inFIG. 1or to a buck device, and may be applied to other types of dc-dc converters (e.g., boost, buck-boost, etc.), or other dc-dc converter designs without departing from the scope of the disclosure.

As shown inFIG. 1, the output stage of example dc-dc converter100consists of input-side and output-side power switches, which are connected to a passive output filter. The dc-dc converter100may be designed with input power supply switching devices102and output power supply switching devices104such as P-type Metal Oxide Semiconductor (PMOS) and N-type Metal Oxide Semiconductor (NMOS) devices, for example. In other implementations, a dc-dc converter100may be implemented using diodes, other types of transistors, or the like, as power supply switching devices102and104. In alternate implementations, one or more switching devices may be used as an input power supply switching device102or as an output power supply switching device104. Stacked transistors may be used for the power switches102and104to provide a supply voltage capability up to a desired voltage (e.g., 5 V).

The power supply switching function of the power supply switching devices102and104determines the flow of current through the output coil (inductor) L and the current through the capacitor COUTby switching on and off at particular times. Load current is supplied by both the current through the inductor L, when one of the output switching device(s)102and104are “on,” and current through the capacitor COUT, when the capacitor COUTdischarges.

Bias voltages for the power supply switching devices102and104, bias1and bias2respectively, may be generated internally by means of source follower structures. Tapered buffers may be used as gate drivers, shown connected to bias1and VSS, and bias2and VBatrespectively. This structure allows simple and fast control of the power switches102and104using the signals pmos_dig and nmos_dig respectively. Both signals pmos_dig and nmos_dig are controlled by a dead time control unit (DTCU)106in this example. In the illustrated implementation, two level shifters are used to shift the signals coming from the core supply domain (e.g., 1.2 V) of the DTCU106to the power domain of the output stage of the dc-dc converter100. The DTCU106generates a non-overlapping switching time sequence of the power switches102and104. Additionally, as shown in the illustrated implementation, a body diode conduction sensor (BDCS)108is used to detect body diode conduction at the output power switches104. The detection information is fed back to a finite state machine (FSM)110where two control signals TD1and TD2for the non-overlapping delay times may be adjusted.

In one implementation, the dc-dc converter100operates in pulse width modulation—discontinuous conduction mode (PWM-DCM). An analog PI controller112compares the feedback voltage, which is divided by resistors down to the core voltage domain (e.g., 1.2 V), with an internally generated reference voltage. A voltage to current converter (V/I converter)114converts the output voltage of the PI controller112into a current. This current is the actuating variable and sets the peak current through the power inductor L during operation (current mode control). A current comparator116compares the actuating variable with the current through the input-side power switch102, which is also the current through the power inductor L during the on-phase. In an implementation, a rising edge at the comparator116output signals a current cross point to the DTCU106, subsequently switching off the input-side power switch102.

Power Switch Timing Optimization

As mentioned above, body diode conduction losses can be a major loss contributor especially in high frequency dc-dc converters. Body diode conduction losses may occur due to imperfect switching time instances of the power switches102and104, which may lead to a current flow through the parasitic body diode of the input power switch102and/or the output power switch104. Accordingly, power switch timing may be optimized to minimize body diode conduction durations, while ensuring that little or no shoot through current flows through power switches102and104. Further, power switch timing optimization may be applied over process, voltage, and temperature (PVT) variations and operating conditions. In an implementation, power switch timing may be optimized during normal dc-dc converter operation by varying the dead time between switching points of the input and output power switches (i.e.,102and104respectively).

In an implementation, the switching time instances (e.g., switching on and/or off) of the output-side power switch104are adjusted depending on the level of body diode conduction at the switch104. Control of power switch timing may be accomplished using an apparatus (such as apparatus200inFIG. 2) or a combination of devices that perform the functions of detecting body diode conduction in a power switch and adjusting the switching time instances based on the detected conduction. The block diagram ofFIG. 2illustrates an example body diode conduction sensor (BDCS)108(“detector block”108) and an example dead time control unit (DTCU)106(“control block”106) according to an implementation, for performing these functions. In various implementations, these functional blocks may be carried out using devices integrated into a dc-dc converter (e.g., as shown in the example dc-dc converter100ofFIG. 1), they may be separate components that are coupled to a dc-dc converter, stand-alone components, or they may be a combination of integrated and separate components.

In an implementation, the detector block108detects body diode conduction at an output power switch (e.g., switch104) of a dc-dc converter (e.g., dc-dc converter100). The detector block108outputs the body diode conduction detections202, to be received by the control block106. As shown inFIGS. 1 and 2, an asynchronous or synchronous digital state machine such as finite state machine (FSM)110may also be included and arranged to generate control signals for the control block106. The generated control signals are configured to control timing of the output power switch104, based on the body diode conduction detected by the detector block108. If included, the FSM110receives the body diode conduction detections202output by the detection block108and outputs adjustable values TD1, TD2, and switch control signals to the control block106. Further, the FSM110may use inputs such as clock signals and/or outputs from the PI controller in generating adjustable values TD1and TD2. In various implementations, some or all of the functionality of the FSM110may be included in another block, for example, control block106.

Control block106receives a trigger204and sends control signals pmos_dig and/or nmos_dig to power switches102and104respectively. In one implementation, trigger204is based on a current at an input stage of the dc-dc converter100(e.g., the current through inductor L). For example, the trigger204may be based on the current crossing a threshold value, such as an upper current limit. Alternatively, the trigger204may be based on an analog voltage or digital counter. Moreover, the trigger204may be based on an amount of time the input power switch102is in an enabled state. Upon receiving the trigger204, the control block106may send a signal pmos_dig to switch off the input power switch102. Concurrently or simultaneously, the control block106may initiate a delay of the switching operation of the output power switch104based on the adjustable value TD1received from the FSM110. At the conclusion of the delay, the control block106sends a signal nmos_dig to the output power switch104, for example, to turn on the output power switch104. Additionally, in an implementation, the control block106receives a second trigger, for example when the inductor current L meets a second threshold (e.g., at a minimum value). The control block106then initiates another delay based on adjustable value TD2, after which the control block106sends another signal nmos_dig to turn off the output power switch104. The adjustable values TD1and TD2may be adjusted at each switching cycle, as is described further below.

FIG. 3shows an illustrative signal timing diagram for an example dc-dc controller100. Included inFIG. 3are digital control signals pmos_dig and nmos_dig for power switches102and104respectively, the current waveform (iL) through the power inductor L, and the voltage waveform at the switching node (Vsw). According to an example implementation, the coil current iLincreases at time t1, when the input-side power switch102is switched on. If the coil current iLcrosses the upper current limit, the input-side switch102is switched off (at time instant t2). At the same time instant, a programmable delay is triggered which delays the switch-on phase of the output-side switch104(delay Tdel1) according to a predefined value set by adjustable value TD1. The switch-on phase of the output-side switch104occurs at time t3, at the conclusion of the programmable delay. In an implementation, body diode conduction may be minimized, if not completely avoided, by choosing a particular value for TD1, and thus, particular delay duration. The same approach may be used to optimize the switch-off phase of the output-side switch104. If the coil current iLcrosses a given lower current limit, a second programmable delay (delay Tdel2) is triggered which delays the switch-off phase of the output-side switch104according to another predefined value TD2. The switch-off phase of the output-side switch104occurs at time t4, at the conclusion of the second programmable delay. By properly choosing the value TD2, the output-side power switch104is switched-off substantially when the coil current becomes zero (e.g., at time t5). With that switch timing, no body diode conduction occurs. The maximum delays for both programmable delays may be designed to be large enough to ensure that the delays are within the delay range for all PVT corners and over all converter conditions.

Example Body Diode Conduction Sensor

FIG. 4is a schematic drawing of an example body diode conduction sensor circuit (e.g., BDCS108) according to an example implementation. In various implementations, other designs may be used to perform the functions described herein. One or more body diode conduction sensors (BDCS)108may be used to detect body diode conduction for both, the on- and off-transition of the output-side switch104. The BDCS108may be coupled between the switching node SW and VSS (seeFIG. 1). At each switching cycle, the BDCS108detects whether body diode conduction occurs during operation of the output power switch104. In an example implementation, as described above, this information is fed back to the FSM110where an optimization algorithm adjusts the preset values TD1and TD2for the delay lines of the DTCU106.

For ease of discussion, the schematic ofFIG. 4includes an example BDCS circuit (such as BDCS108) and an output driver portion of an example dc-dc converter. As shown in the schematic ofFIG. 4, the BDCS108rectifies the forward voltage across the body diode of MNand stores the rectified voltage in a capacitor C. Accordingly, the BDCS108works as fast peak detector such that the negative voltage peak at the switching node VSWdue to body diode conduction is detected. The BDCS108is connected to the source of one switch transistor MNiand a reference voltage Vref, which is close in voltage to VSS. Two digital input signals “en” and “rst” control the three different operating modes of the sensor: 1) reset mode when rst=1 (capacitor C will be discharged and the sensor output voltage VCbecomes zero); 2) sense mode when rst=0 and en=1 (enables the BDCS108for sensing body diode conduction); and 3) hold mode when rst=0 and en=0 (disables the BDCS108and holds the stored charge in capacitor C). In example implementations, one sensor can be used to detect body diode conduction from t=t2to t=t3or from t=t4to t=t5(seeFIG. 3).

For body diode conduction detection at the second period, the functionality of the BDCS108may be as follows: during period t=t3to t=t4MN5and MN6are switched on by the control signal “rst” (reset mode), discharging the capacitor C. During phase t=t4to t=t5the switching transistor MN1and the pass transistors MN3and MN4are switched on (sense mode). During this period the BDCS108acts as a negative voltage peak detector with respect to Vref. When VSWbecomes negative with respect to Vref, current can flow through MN2which results in charging the capacitor C. The amount of charging is determined by the duration of body diode conduction. After detecting body diode conduction, the BDCS108can be disabled and the stored charge in C may remain constant (hold mode). Thus, a slow comparator K1with inherent offset VOScan be used to evaluate VCand therefore evaluate if body diode conduction occurred. In sense mode, the voltage VCacross the capacitor C can be determined by the equation:
VC=VrefVDS MN−VDS MN4−VDS MN3−VGS MN2−VDS MN1|max(1)
where the VDSare the drain source voltages of the corresponding transistors and VGS MN2is the gate source voltage of transistor MN2. If the time constant C·(rON MN4+rON MN3+rON MN1) is low compared to the lowest possible detectable body diode conduction duration, the drain-source voltage drops of the switch and pass transistors can be neglected, and equation (1) can be simplified to:
VC≈Vref−VDS MN−VGS MN2|max(2)

Assuming, for example, that the threshold voltage of transistor MN2is 0.3 V and Vrefis set to 0.1 V, by evaluating equation (2) VCbecomes positive if VDS MNis lower than negative 0.2 V. In other words, the detector is able to detect body diode conduction voltages VBD MN t5down to 0.2 V. As seen in equation (2), Vrefcan be used to adjust the detection thresholds. If Vrefis increased, the sensor is adjusted to sense smaller body diode conduction voltages and vice versa. Vrefis capacitively coupled to the power ground VSS by a capacitor CC. This makes the BDCS108generally insensitive concerning ringing at VSS.

Example Dead Time Control Unit

FIG. 5is a schematic drawing of an example dead time control unit circuit (such as DTCU106) according to an implementation. In various implementations, other designs may be used to perform the functions described herein. For example, the DTCU106is a state machine that generates the digital control sequence for the power switches102and104, outputting control signals pmos_dig and nmos_dig. As discussed above, the generated control signals control the three different states: 1) both input-side and output-side power switches are off; 2) only the input-side switch is on; and 3) only the output-side switch is on.

An example of the operation of DTCU106as illustrated is as follows. After reset, the DTCU106is in state 1 where both control signals pmos_dig and nmos_dig are logical “0”. At the rising edge of a voltage pulse at pin start_sw the DTCU106changes to state 2 where pmos_dig goes to logical “1”. The DTCU106remains in this state at least as long as the signal start_sw is logical “1”, which allows defining a minimal state duration of this state. If the upper current limit is detected (comp_p goes to logical “1”) (see alsoFIG. 3) the DTCU106changes from state 2 to state 3. The signal start_cnt_TD1indicates the state transition and it is delayed by dint of a programmable delay line. This means that the rising edge of control signal nmos_dig of the output-side switch is delayed according to a predefined multi-bit (e.g., 5-bit) value of TD1(seeFIG. 3). The DTCU106goes back again to state 1 on receipt of a rising edge of signal comp_n (i.e., lower current limit was detected). At the state transition the signal start_cnt_TD2is delayed by a second programmable delay line. This means that the falling edge of the output-side switch control signal nmos_dig is delayed according to the predefined value of TD2(seeFIG. 3). The programmable delay line consists of a ring oscillator which clocks an asynchronous multi-bit (e.g., 5-bit) down counter. The oscillator starts if signal start_cnt goes to logical “1” and it stops if the counter value becomes “zero”. In one implementation, the oscillator frequency is approximately 1 GHz, therefore, the resolution of the delay line is about 1 ns. Since the delay line blocks are typically only active for a few oscillator cycles their power consumption is negligible.

Representative Optimization Algorithm

FIG. 6is a flow diagram illustrating an example optimization algorithm600for controlling switching operations of a dc-dc converter100according to an implementation. In various implementations, the example optimization algorithm600may be used by a DTCU106as described above, or by another component or components to perform the described functions. In general, the FSM110adjusts the adjustable values (TD1and TD2) of the programmable delay lines in the DTCU106according to the output of the body diode conduction sensor(s)108. The block diagram of the optimization algorithm600as shown inFIG. 4describes one example process. In the example shown, two body diode conduction sensors108are used, one (BDCS1) for switching “on” the output power switch104and another (BDCS2) for switching “off” the output power switch104. This arrangement is for ease of discussion, since in various implementations, the functions described may be performed by one single BDCS108, or more than 2 BDCS108devices.

As described above, the one or more BDCS108devices provide output that determines the adjustable values TD1and TD2. The adjustable values TD1and TD2determine the duration of programmable delays that are applied to switch timing for the power switches102and104. In various implementations, one or more programmable delays may be triggered by a current based on an input power stage of the dc-dc converter100reaching a preset current threshold.

During reset at block602, the preset (adjustable) values TD1and TD2are initialized. Next, at blocks604and606, the algorithm600checks if BDCS1(sens_T1=“1”) or if BDCS2(sens_T2=″1″) have detected body diode conduction. For instance, if BDCS1has detected body diode conduction (at block604), and the value of TD1has not reached a minimum value (block612), then the value of TD1for the programmable delay line is decremented (block614), which means that the output-side switch104is switched on earlier at the next switching cycle (the programmable delay count is decreased).

Alternately, if BDCS1has not detected body diode conduction (at block604) and the value of TD1has not reached a maximum value (block608), then TD1will be incremented (block610). Accordingly, the output-side switch104is switched on later at the next switching cycle (the programmable delay count is increased).

This means that in steady state, TD1may toggle between two values, where in one switching cycle body diode conduction is detected and at the next cycle no body diode conduction is detected. In an implementation where the resolution of the programmable delay line is about 1 ns, the remaining body diode conduction duration averages about 500 ps, which is generally sufficient for high frequency converters. This remaining body diode conduction duration can be further reduced by increasing the resolution of the programmable delay line. It is also important that the resolution of the programmable delay line is chosen high enough to avoid shoot through currents through the power switches due to large delay time steps.

Continuing, if BDCS2has detected body diode conduction (at block606), and the value of TD1has not reached a maximum value (block620), then the value of TD2for the programmable delay line is incremented (block622), which means that the output-side switch104is switched off later at the next switching cycle (the programmable delay count is increased).

Alternately, if BDCS2has not detected body diode conduction (at block606) and the value of TD2has not reached a minimum value (block616), then TD1will be decremented (block618). Accordingly, the output-side switch104is switched off earlier at the next switching cycle (the programmable delay count is decreased).

Representative Process

FIG. 7illustrates a representative process700for implementing power switch timing control including dead-time optimization for a dc-dc converter (such as the dc-dc converter100). An example process700includes determining when the power switches (such as power switches102and104) of the dc-dc converter switch on and off relative to each other. In various implementations, the determination is based on a detection of body diode conduction at one or more of the power switches102and104. In one implementation, the operation of one or more of the switches102and104may be delayed based on detected body diode conduction. The process700is described with reference toFIGS. 1-6.

The order in which the process is described is not intended to be construed as a limitation, and any number of the described process blocks can be combined in any order to implement the process, or alternate processes. Additionally, individual blocks may be deleted from the process without departing from the spirit and scope of the subject matter described herein. Furthermore, the process can be implemented in any suitable hardware, software, firmware, or a combination thereof, without departing from the scope of the subject matter described herein.

At block702, current based on a first switch (such as input power switch102) meets a current threshold. In one implementation, the current is the inductor output current and the current threshold is an upper current limit.

At block704, the first switch is switched off, based on the current meeting the current threshold. In one implementation, switching off the first switch comprises switching off an input stage of a dc-dc converter. Concurrently, at block706, a programmable time delay is triggered. In an implementation, the programmable time delay is based on an adjustable value (such as adjustable value TD1).

At block708, a second switch (such as output power switch104) is switched on at the conclusion of the programmable time delay. In one implementation, switching on the second switch comprises switching on an output stage of the dc-dc converter.

At block710, the adjustable value is adjusted based on body diode conduction of least at one of the first switch or the second switch. The adjustable value, as adjusted, is applied to the programmable delay during the next switch cycle.

In one implementation, the process700further comprises measuring the body diode conduction of at least one of the first switch and the second switch. In such an implementation, the measuring may be performed by a body diode conduction sensor (such as BDCS108).

In another implementation, the process700further comprises adjusting the adjustable value at successive switching cycles of the second switch. In the implementation, the body diode conduction at the second switch is minimized with each successive switching cycle.

In a further implementation, the process700further comprises triggering a second programmable time delay based on a second adjustable value when the current based on the first switch meets a second current threshold. At the conclusion of the second programmable time delay, the second switch is switched off In one implementation, switching off the second switch comprises switching off the output stage of the dc-dc converter.

In an implementation, the process700further comprises adjusting the second adjustable value based on a body diode conduction of at least one of the first switch and the second switch. In one example, the process700includes adjusting the second adjustable value such that the second switch is switched off when the current based on the first switch becomes zero.

In alternate implementations, other techniques may be included in the process700in various combinations, and remain within the scope of the disclosure.

CONCLUSION

Although the implementations of the disclosure have been described in language specific to structural features and/or methodological acts, it is to be understood that the implementations are not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as representative forms of implementing example devices and techniques.