MEMORY SYSTEM AND METHOD OF CONTROLLING THE MEMORY SYSTEM

According to one embodiment, a memory system includes a nonvolatile memory, a first write buffer, a second write buffer having a capacity smaller than that of the first write buffer and a bandwidth larger than that of the first write buffer, and a controller. When the write speed of the first group is less than a first value, the controller loads unloaded data among first data into the first write buffer, and after an amount of the first data reaches or exceeds a minimum write size, writes the first data to a first write destination block. When the write speed of the second group is greater than or equal to the first value, the controller loads second data having the minimum write size into the second write buffer and writes the second data to the second write destination block.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2023-041614, filed Mar. 16, 2023, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a memory system including a nonvolatile memory and a method of controlling the memory system.

BACKGROUND

Memory systems implemented with a nonvolatile memory have recently become widespread. As one of such memory systems, a solid state drive (SSD) including a nonvolatile memory such as a NAND flash memory and a controller that controls the nonvolatile memory is known.

The controller of the memory system processes input/output (I/O) signals (data, commands) received from an external host via a host interface conforming to a certain standard, and thus performs a read process for reading data from the nonvolatile memory and a write process for writing data to the nonvolatile memory.

In the memory system, there is a need for a technology that can improve the performance of write process.

DETAILED DESCRIPTION

In general, according to one embodiment, a memory system comprises a nonvolatile memory including a plurality of blocks, a first write buffer, a second write buffer having a capacity smaller than that of the first write buffer and a bandwidth greater than that of the first write buffer, and a controller. The controller is configured to manage a plurality of write destination blocks allocated from the plurality of blocks. The controller is capable of receiving, from a host, a write command that includes first information indicating a size of data to be written to the nonvolatile memory and second information that is able to directly or indirectly specify a write destination block associated with the data. The controller classifies the received write command into a first group for writing data to a first write destination block or a second group for writing data to a second write destination block, based on the second information included in the received write command. The controller determines, based on the first information included in the received write command, whether a write speed, which indicates an amount of data required to be written per predetermined time, is greater than or equal to a first value for each of the first and second groups. When the write speed of the first group is less than the first value, the controller loads unloaded data among first data associated with the first group from a memory of the host into the first write buffer, and after an amount of the first data reaches or exceeds a minimum write size of the nonvolatile memory, writes the first data to a first write destination block allocated to the first group. When the write speed of the second group is greater than or equal to the first value, the controller loads second data associated with the second group and having the minimum write size from the memory of the host into the second write buffer, and writes the second data to a second destination block allocated to the second group.

In the following descriptions, such a case is assumed that the memory system according to the embodiment is implemented as a solid state drive (SSD).FIG.1is a block diagram illustrating an example of a configuration of an information processing system1including the memory system according to the embodiment. The information processing system1includes a host (host device)2and an SSD3.

The host2is an information processing apparatus. The host2is, for example, a personal computer, a server computer, or a mobile device. The host2accesses the SSD3. More specifically, the host2issues a write command, which is a command for writing data, to the SSD3. Further, the host2issues a read command, which is a command for reading data, to the SSD3.

The SSD3is a storage device which is connectable to the host2. The SSD3includes a nonvolatile memory. The SSD3can write data to an internal nonvolatile memory. The SSD3can read data from the internal nonvolatile memory.

Communication between the SSD3and the host2is performed via a bus7. The bus7is a transmission path which connects the host2and the SSD3to each other. The bus7is, for example, a PCI Express™ (PCIe™) bus. The PCIe bus is a full duplex transmission path. The full duplex transmission path includes both a transmission path for transmitting data and input/output (I/O) commands from the host2to the SSD3and a transmission path for transmitting data and responses from the SSD3to the host2. The I/O command is, for example, a command for performing writing of data to the nonvolatile memory or a command for performing reading of data from the nonvolatile memory. The I/O command is, for example, a write command or a read command.

As a standard of a logical interface for connecting the host2and the SSD3, for example, a standard of NVM Express™ (NVMe™) may be used. In the interface conforming to the NVMe™ standard, communication between the host2and the SSD3is performed using a pair of queues that includes at least one submission queue (SQ) and a completion queue (CQ) associated with the at least one submission queue (SQ). This pair of queues is referred to as a submission queue/completion queue pair (SQ/CQ pair).

Next, the configuration of the host2will be described.

The host2includes a processor21and a memory22. The processor21and the memory22are interconnected via an internal bus20.

The processor21is, for example, a CPU. The processor21executes software (host software) loaded into the memory22from the SSD3or some other storage device connected to the host2. The host software includes, for example, an operating system, a file system, and application programs.

The memory22is, for example, a volatile memory. The memory22may as well be referred to as a main memory, system memory, or host memory. The memory22is, for example, a dynamic random access memory (DRAM). A part of the memory area of the memory22is used as a host write buffer221. The host write buffer221is a memory area that temporarily stores data to be written to the nonvolatile memory of the SSD3.

Further, another part of the memory area of the memory22is used to store SQ/CQ pairs222. Each of submission queues SQs included in the SQ/CQ pairs222is a queue used to issue I/O commands (write commands and read commands) to the SSD3. Each of the submission queues SQ includes a plurality of slots. Each of the slots can store one I/O command. The host2creates the submission queue SQ in the memory22of the host2. Further, the host2issues a submission queue create command to the SSD3. The addresses indicating the memory location in the memory22where each of these submission queues SQ is created, the size of each of these submission queues SQ, the identifier of the completion queue CQ associated with these submission queues SQ and the like are notified to the SSD3by the submission queue create command.

The completion queue CQ included in the SQ/CQ pair222is a queue used to receive from the SSD3a completion response indicating the completion of the I/O command. The completion response includes information that indicates a status of success or failure of the processing of the completed command. The completion response may as well be referred to as a command completion or a command completion notification. The completion queue CQ includes a plurality of slots. Each of these slots can store one completion response. The host2creates the completion queue CQ in the memory22of the host2. Further, the host2issues a completion queue create command to the SSD3. The address which indicate the memory locations in the memory22where the completion queue CQ is created, the size of this completion queues CQ and the like are notified to the SSD3by the completion queue create command.

Next, the internal configuration of the SSD3will be described. In the following descriptions, such a case is assumed that the nonvolatile memory included in the SSD3is implemented by a NAND flash memory. Note that the NAND flash memory may as well be some other flash memory or some other nonvolatile memory such as MRAM, ReRAM, FeRAM, phase-change memory or the like.

The SSD3includes a controller4and a NAND flash memory5. Further, the SSD3may as well include a random access memory, for example, a dynamic random access memory (DRAM)6, which is a volatile memory.

The NAND flash memory5may be a flash memory of a two-dimensional structure or a three-dimensional structure. The NAND flash memory5includes a plurality of blocks. Each of the plurality of blocks is the smallest unit of data erase operation. Each of the plurality of blocks may as well be referred to as a memory block or a physical block. Each of the plurality of blocks includes a plurality of pages. Each of the pages is a unit for each of the data write operations and data read operations. Each page includes a set of memory cells connected to the same word line. Each page may as well be referred to as a physical page.

The NAND flash memory5includes a plurality of dies. Each die may as well be referred to as a memory die, a flash die, a memory chip or a flash chip. Each of these dies is implemented as a NAND flash memory die. Hereafter, a die will be referred to as a flash die.FIG.1shows the case where the NAND flash memory5includes thirty two flash dies #0 to #31 as an example.

The controller4is a memory controller. The controller4is, for example, a control circuit such as a system-on-a-chip (SoC). The controller4is electrically connected to each of the NAND flash memory5and the DRAM6. The controller4performs a read process for reading data from the NAND flash memory5and a write process for writing data to the NAND flash memory5by processing each of the I/O commands received from the host2. As a physical interface which connects the controller4and the NAND flash memory5to each other, a Toggle interface or an open NAND flash interface (ONFI) is used. The function of each part of the controller4can be implemented by dedicated hardware, a processor which executes a program, or a combination of the dedicated hardware and the processor.

The controller4manages a plurality of write destination blocks. Each write destination block is a block in an open state (a block in which data is being written) to which data can be written. In the write process, the controller4executes a process for writing different types of data to different write destination blocks. Note here that these different types of data are, for example, data from different applications, data from different end users (different tenants such as containers and virtual machines), data having different lifetimes, and the like.

For example, in the case where write data are transmitted respectively from different applications at different timings and the write data are written by the SSD3in the order in which they are transmitted, a single block may contain a mixture of data from different applications. In such a case, the frequency of performing garbage collection, which involves exchanging data between blocks is increased, thereby degrading the write amplification (write processing efficiency). In order to prevent such degradation in write processing efficiency, a stream write operation, in which data is grouped by application and these data are written to contiguous physical addresses of a certain block, is performed. Recently, as the number of streams has increased, it has become necessary to support a large number of streams in a limited memory capacity. Writing to more streams than one stream as described above is referred to as multi-stream writing.

When executing multi-stream writing, the controller4recognizes identifiers assigned by the command for each of a plurality of streams and manages a plurality of write destination blocks corresponding to the respective identifiers. At this time, the controller4sets the same number of blocks as the number of active streams to an open state. The controller4then allocates a write destination block in the open state to each of the plurality of active streams.

In the case where a plurality of zones defined in the NVMe zoned namespace standard are used, the controller4manages a plurality of blocks corresponding respectively to the plurality of zones. At this time, the controller4sets the same number of blocks as the number of opened zones to the open state. Then, the controller4allocate a write destination block in the open state to each of the opened zones.

Further, in the case where such a system configuration is used that the host2issues to the SSD3a write command that specifies a block address indicating a write destination block (for example, a write destination super block), the controller4allocates a plurality of write destination blocks to the host2. The controller4manages these write destination blocks allocated to the host2.

In the case where a plurality of storage areas (QoS domains) are created and managed, and a plurality of write destination blocks corresponding respectively to a plurality of placement IDs are managed for each QoS domain, the controller4manages the same number of write destination blocks as the number of placement IDs used in each QoS domain for each QoS domain.

Further, in the case where the storage area is physically separated for each namespace, the controller4manages the same number of write destination blocks as the number of namespaces, as the physical storage areas for these namespaces.

The DRAM6includes a memory area for storing a logical-to-physical address translation table (L2P table)61. The DRAM6further includes a memory area for storing a block management table62, a memory area used as a DRAM write buffer63, and a memory area for storing a plurality of virtual write buffers (VWBs)64.

The L2P table61is a table that stores mapping information. The mapping information is information which indicates mapping between each of logical addresses and each of physical addresses of the NAND flash memory5in units of a predetermined management size. A logical address is an address used by the host2to access the SSD3. For example, a logical block address (LBA) is used as the logical address. The physical address is an address that indicates a storage location in the NAND flash memory5. The physical address can be expressed, for example, by a flash die address, a block address, a page address, an offset address in a page, and any combination of all or some of these. In the case where the addresses included in the I/O commands transmitted from the host2include a physical address and a logical address, the L2P table may be stored in the memory22of the host2.

The block management table62is a table that stores information for managing the status of each of the plurality of blocks included in the NAND flash memory5.

The DRAM write buffer63is a memory area that temporarily stores data to be written to the NAND flash memory5. The DRAM write buffer63may as well be referred to as a first write buffer.

A plurality of VWBs64are respectively associated with a plurality of write destination blocks in a one-to-one relationship. Each of VWBs64is used to store information indicating an amount of unwritten data for the corresponding write destination block, and the like. The details of the VWBs64will be described later.

Next, the internal configuration of the controller4will be described. The controller4includes, for example, a host interface (host I/F)41, a static RAM (SRAM)42, a CPU43, a direct memory access controller (DMAC)44, an error correction circuit45, a NAND interface (NANDI/F)46and a DRAM interface (DRAM I/F)47. The host interface41, the SRAM42, the CPU43, the DMAC44, the error correction circuit45, the NAND interface46, and the DRAM interface47are interconnected via an internal bus40.

The host interface41is a communication interface circuit which executes communications with the host2. The host interface41is implemented, for example, by a PCIe controller. For example, in the case where the host interface41is a fifth-generation PCIe controller and the number of lanes contained in the bus7is four, the data reception rate of the host interface41is about 16 gigabytes/second (GB/s). Or, in the case where the host interface41is a sixth-generation PCIe controller and the number of lanes contained in the bus7is four, the data reception rate of the host interface41is about 30 GB/s. Further, the host interface41includes an arbitration mechanism (not shown). The arbitration mechanism is a mechanism which selects a submission queue SQ from which an I/O command should be fetched, from a plurality of submission queues SQ included in the SQ/CQ pairs222. The arbitration mechanism is, for example, a round-robin arbitration mechanism or a weighted round-robin arbitration mechanism.

The SRAM42is a volatile memory. The memory area of the SRAM42is used, for example, as a work area of the CPU43. Further, the SRAM42includes a memory area which stores an SRAM write buffer421. The SRAM write buffer421is a memory area which temporarily stores data to be written to the NAND flash memory5. The SRAM write buffer421has a capacity smaller than that of the DRAM write buffer63and a bandwidth greater than that of the DRAM write buffer63. The SRAM write buffer421may as well be referred to as a second write buffer.

Here, an example will be described with regard to the respective relationships between the capacity and bandwidth of the DRAM write buffer63and the capacity and bandwidth of the SRAM write buffer421.

The bandwidth of a typical DRAM usable for the SSD3is, for example, 25 GB/s. With this configuration, the DRAM write buffer63has a bandwidth of 25 GB/s. The write process using the DRAM write buffer63requires a process of writing data to the DRAM write buffer63and a process of reading the data from the DRAM write buffer63. Therefore, when writing data to the NAND flash memory5via the DRAM write buffer63, the speed of data passing through the DRAM write buffer63is half the speed of the bandwidth of the DRAM write buffer63, which is about 12.5 GB/s.

The capacity of the DRAM write buffer63is set, for example, to the capacity given by the formula: [the minimum write size of the NAND flash memory5]×[the number of write destination blocks]. Here, the minimum write size of the NAND flash memory5is the minimum size of data required for the data write operation of the NAND flash memory5. For example, in the case where the page size is 16 KiB, a mode of the data write operation is a triple level cell (TLC) mode, which stores 3 bits per memory cell, and the number of planes per flash die is four, the minimum write size is 192 KiB (=16 KiB×3 bits×4 planes).

Note that when data is written to a plurality of flash dies in parallel via a plurality of channels, the minimum write size will be even greater. It is assumed here that, for example, the number of channels used for parallel writing is eight. In this case, the minimum write size is about 1.5 MiB (=16 KiB×3 bits×4 plains×8 channels). Here, when the number of write destination blocks is 1000, the capacity of the DRAM write buffer63may be set to about 1.5 GB.

On the other hand, the bandwidth of a typical SRAM usable for the controller4is sufficiently greater than that of a DRAM. Therefore, the speed of data passing through the SPAM write buffer421when writing data to the NAND flash memory5via the SRAM write buffer421is sufficiently faster than the speed of data passing through the DRAM write buffer63. The capacity of the SPAM write buffer421is set to the capacity given, for example, by [the minimum write size of the NAND flash memory5]. In other words, when the minimum write size of the NAND flash memory5is 1.5 MiB, the capacity of the SRAM write buffer421may be set to 1.5 MiB.

The CPU43is a processor. The CPU43loads a control program (firmware) stored in the NAND flash memory5or in a ROM (not shown) to the SRAM42. Then, the CPU43performs various types of processes by executing this firmware. Note that the firmware may as well be loaded to the DRAM6.

The CPU43performs management of the data stored in the NAND flash memory5and management of the blocks included in the NAND flash memory5as a flash translation layer (FTL), for example. The management of the data stored in the NAND flash memory5includes the management of the mapping information, for example. The CPU43manages the mapping between each of the logical addresses and each of the physical addresses in units of management size, using the mapping information of the L2P table61. The management size is, for example, 4 KiB.

In the NAND flash memory5, data can be written to a page in a block only once per program/erase cycle of this block. In other words, new data cannot be directly overwritten to a storage location (physical storage location) within the block, where data has already been written. Therefore, when updating data that has already been written to the physical storage location within the block, the controller4writes new data to a not-yet-written page (free page) within the block (or another block) and handles the previous data as invalid data. In other words, the controller4writes update data corresponding to a certain logical address to a physical storage location different from the physical storage location in which the previous data corresponding to this logical address is stored. The controller4then updates the L2P table61and associates this logical address with a physical address which indicates this other physical storage location.

The management of blocks included in the NAND flash memory5includes management of defective blocks (bad blocks) included in the NAND flash memory5, wear leveling, and garbage collection (GC).

The DMAC44is a circuit which performs direct memory access (DMA). The DMAC15performs data transfer between the memory22of the host2and the SRAM42(or DRAM46). For example, in a write process, the DMAC44executes the transfer of write data from the host write buffer221to the SRAM42(or DRAM6).

The error correction circuit45executes the encoding process when data is to be written to the NAND flash memory5. In the encoding process, the error correction circuit45adds an error correction code (ECC) as a redundancy code to the data to be written to the NAND flash memory5. When data is read from the NAND flash memory5, the error correction circuit45executes the decoding process. In the decoding process, the error correction circuit45executes error correction of the data read out from the NAND flash memory5by using the ECC added to this data.

The NAND interface46is a circuit which controls the NAND flash memory5. The NAND interface46is electrically connected to a plurality of flash dies included in the NAND flash memory5.

Each flash die can operate independently. Therefore, the flash dies function as parallel operable units. The NAND interface46includes, for example, NAND controllers461-0,461-1, . . . ,461-7. The NAND controllers461-0,461-1, . . . ,461-7are connected to channels ch0, ch1, . . . , ch7, respectively. The controllers461-0,461-1, . . . ,461-7are each connected to one or more flash dies via the corresponding channel.FIG.1illustrates an example case in which four flash dies are connected to each of the channels ch0, ch1, . . . , ch7. In this case, the NAND controller461-0is connected to flash dies #0, #8, #16 and #24 via the channel ch0. The NAND controller461-1is connected to flash dies #1, #9, #17 and #25 via the channel ch1. Further, the NAND controller461-7is connected to flash dies #7, #15, #23 and #31 via the channel ch7. The flash dies #0, #1, . . . , and #7 are handled by the controller4as a bank BNK0. The flash dies #8, #9, . . . , #15 are handled by the controller4as a bank BNK1. The flash dies #16, #17, . . . , #23 are handled by the controller4as a bank BNK2. The flash dies #24, #25, . . . , #31 are handled by the controller4as a bank BNK3. A bank is a unit by which a plurality of flash dies are operated in parallel by an interleaving operation.

FIG.2is a block diagram illustrating an example of a configuration of the relationship between a plurality of channels and a plurality of flash memory dies used in the memory system according to the embodiment.

As illustrated inFIG.2, each of the flash dies #0 to #31 includes a plurality of blocks BLK1 to BLKx−1. In the configuration example illustrated inFIGS.1and2, the controller4can access the flash dies #0 to #31 in parallel by means of 8 channels and bank interleaving operation. Therefore, the controller4can execute write or read of data up to a maximum of 32 flash dies in parallel. Each of the flash dies #0 to #31 may have a multi-plane configuration which includes a plurality of planes. For example, when each of the flash dies #0 to #31 includes four planes, the controller4can execute a write or read of data up to a maximum of 128 planes in parallel.

Each of the plurality of write destination blocks may be a single block (physical block) or a super block including a set of a plurality of physical blocks that can be operated in parallel.

One super block may include a total of 32 physical blocks selected one by one from the NAND flash memory dies #0 to #31, though the configuration is not limited to this. Note that each of the NAND flash memory dies #0 to #31 may have a multi-plane configuration. For example, in the case where each of the NAND flash memory dies #0 to #31 has a multiplane configuration including four planes, one super block may include a total of 128 physical blocks selected one by one from 128 planes corresponding to the NAND flash memory dies #0 to #31.

FIG.3illustrates an example of a configuration of a super block used in the memory system of the embodiment.FIG.3illustrates an example of one super block (SB) which includes thirty two physical blocks (here, the physical block BLK2 in the NAND flash memory die #0, the physical block BLK3 in the NAND flash memory die #1, the physical block BLK7 in the NAND flash memory die #2, . . . , the physical block BLK4 in the NAND flash memory die #24, the physical block BLK6 in the NAND flash memory die #25, . . . , the physical block BLK3 in the NAND flash memory die #31).

Note that such a configuration that one super block includes only one physical block may be adopted, and in such a case, each one super block is equivalent to one physical block. Further, here, the same Pages 0, 1, 2, . . . are set in the super block for the flash dies #0 to #31, but the setting is not limited to this, and can be set up in some other way.

Let us return to the explanation ofFIG.1. The DRAM interface47is a circuit which controls the DRAM6. The DRAM interface47stores data in the DRAM6. Further, the DRAM interface47reads data stored in the DRAM6.

Next, the internal configuration of the CPU43will be described. The CPU43includes a read process unit431and a write process unit432in addition to the components that function as FTL (Flash Translation Layer).

Each of the read process unit431and the write process unit432may be partially or entirely implemented by the dedicated hardware in the controller4.

The read process unit431performs a read process by processing the respective read commands received from the host2. The read process includes a process of converting a logical address specified by the read command into a physical address by referring to the L2P table61, a process of reading data from a storage location in the NAND flash memory5, which is indicated by this physical address, and a process of transferring the read data to the memory22of the host2.

The write process unit432executes a write process by processing the respective write commands received from the host2. The write process includes a process of loading (transferring) write data from the host write buffer221to the SRAM write buffer421or the DRAM write buffer63, a process of writing the write data loaded into the SRAM write buffer421or the DRAM write buffer63to a storage location in the NAND flash memory5, and a process of updating the L2P table61so that a physical address indicating the storage location where the write data has been written is mapped to a logical address specified by the write command.

The write process unit432includes a flash management unit433and a scheduler434.

The flash management unit433receives a write commands from the submission queue (SQ) of the host2. The write command includes at least information (first information) indicating the size of write data to be written to the NAND flash memory5and information (second information) that is able to directly or indirectly specify a write destination block associated with the write data. The information that is able to indirectly specify the write destination block is, for example, (1) a stream identifier included in a write command used for multi-stream writing, (2) the high-order bit (the upper bit) part of the logical address (Start LBA: SLBA) included in a write command used in the zoned namespace standard, (3) a combination of the QoS domain ID and placement ID included in a write command that specifies the QoS domain of the write destination, or (4) a namespace identifier included in a write command when the storage area is physically separated for each namespace.

The information that is able to directly specify the write destination block is, for example, a block address (super block address) included in a write command issued by the host2in a system configuration in which a plurality of write destination blocks are assigned to the host2.

Based on the second information included in the received write command, the flash management unit433classifies the received write command into a first group for writing data to the first write destination block or a second group for writing data to the second write destination block. The first group is a set of write commands for writing data to the same write destination block (in this case, the first write destination block). The data associated with the first group, that is, the data associated with the set of write commands belonging to the first group, is written to the first write destination block corresponding to this first group. The second group is a set of write commands for writing data to the same write destination block (here, the second write destination block). The data associated with the second group, that is, the data associated with the set of write commands belonging to the second group, is written to the second write destination block corresponding to this second group. The flash management unit433manages the data associated with the first group and not yet written to the NAND flash memory5(unwritten data) using the VWB64corresponding to the first write destination block. Further, the flash management unit433manages the data associated with the second group and not yet written to the NAND flash memory5(unwritten data) using the VWB64corresponding to the second write destination block.

Based on the first information (information indicating the size of the write data to be written to the NAND flash memory5) included in the received write command, the flash management unit433determines whether the write speed, which indicates the amount of data required to be written per predetermined time, is greater than or equal to s first value, for each of the first and second groups. In this case, the flash management unit433calculates the amount of unwritten data associated with the same group based on the first information included in each of the received write commands for each of the plurality of groups. For example, the flash management unit433calculates the amount of unwritten data associated with the first group based on the first information included in each of the write commands classified into the first group. Further, the flash management unit433calculates the amount of unwritten data associated with the second group based on the first information included in each of the write commands classified into the second group.

It is assumed here that, for example, write commands CMD1 to CMD5 are received, and the write commands CMD1 to CMD3 are classified into the first group, whereas the write commands CMD4 to CMD5 are classified into the second group. In this case, the flash management unit433calculates the sum of the sizes of the write data respectively specified by the write commands CMD1 to CMD3, as the amount of unwritten data associated with the first group. Further, the flash management unit433calculates the sum of the sizes of the write data respectively specified by the write commands CMD4 to CMD5, as the amount of unwritten data associated with the second group.

The flash management unit433determines whether or not the write speed of the first group is higher than or equal to the first value based on the amount of unwritten data associated with the first group(, which may as well be referred to as the first data). Further, the flash management unit433determines whether or not the write speed of the second group is higher than or equal to the first value based on the amount of unwritten data associated with the second group(, which may as well be referred to as the second data).

When the write speed of the first group is higher than or equal to the first value, the flash management unit433determines that the first group is a group with a fast write speed. When the write speed of the first group is less than the first value, the flash management unit433determines that the first group is a group with a slow write speed. Similarly, when the write speed of the second group is higher than or equal to the first value, the flash management unit433determines that the second group is a group with a fast write speed. Or when the write speed of the second group is less than the first value, the flash management unit433determines that the second group is a group with a slow write speed.

The scheduler434executes the scheduling process. The scheduling process includes a process for periodically selecting a write destination block to which data should be written, from a plurality of write destination blocks. In other words, the scheduling process is a process of selecting one of a plurality of groups which include at least the first and second groups, as a group permitted to write to the NAND flash memory5. The scheduler434executes the scheduling process to select one of the groups which include new write commands whose data is not yet loaded, in response to the start or end of a data write operation in the NAND flash memory5. In other words, the scheduler434selects one of the first and second groups, which includes a new write command whose data is not yet loaded. The unloaded write data is write data which has not yet been loaded into either the DRAM write buffer63or the SRAM write buffer421and is stored on the host write buffer221, among the unwritten data. The scheduler434selects one group corresponding to one write destination block as the group permitted to write to the NAND flash memory5, for example, by selecting one of a plurality of VWBs64in the scheduling process. The scheduler434selects one of VWBs64in which a new write command whose write data is not yet loaded has arrived, as the group permitted to write to the NAND flash memory5.

When a certain VWB64(that is, a certain group) is selected by the scheduler434, the flash management unit433determines whether or not the write speed of the selected group is higher than or equal to the first value, that is, whether the selected group is a group with a fast write speed or a slow write speed.

Here, such a case is assumed that the first group is selected and the first group is a group with a slow write speed, that is, the write speed of the first group is less than the first value. The flash management unit433loads unloaded write data of the write data corresponding to the first group, that is, write data stored in the host write buffer221, into the DRAM write buffer63. Then, the flash management unit433transmits to the host2one or more completion responses corresponding to one or more write commands associated with the write data loaded into the DRAM write buffer63. After one or more new write commands belonging to the first group are received and the total amount of unwritten write data corresponding to the first group reaches or exceeds the minimum write size of the NAND flash memory5, the flash management unit433writes the write data (i.e., the unwritten write data) from the DRAM write buffer63to the write destination block. This write destination block is the first write destination block allocated to the first group. In writing write data to the first write destination block, the write data read from the DRAM write buffer63may be directly transferred to the NAND flash memory5, or the write data read from the DRAM write buffer63may be transferred to the NAND flash memory5via some other data buffer such as the SRAM write buffer421.

Next, such a case is assumed that the second group is selected and the second group is a group with the fast write speed, that is, the write speed of the second group is higher than or equal to the first value. The flash management unit433loads the write data associated with the second group and having the minimum write size from the host write buffer221to the SRAM write buffer421and immediately writes the write data to the destination block. This write destination block is the second write destination block allocated to the selected second group. In this case, the write data loaded into the SRAM write buffer421is transferred to the NAND flash memory5and then written to the second write destination block allocated to the second group. When the transferring of the write data to the NAND flash memory5is completed, the memory area of the SRAM write buffer421is released. Thus, the SRAM write buffer421becomes available for storing next write data having the minimum write size.

Note that in the above-provided explanation, whether or not the write speed of each group is higher than or equal to the first value is determined by judging whether the amount of unwritten data is greater than or equal to the minimum write size at the timing when the preparation for the next write to the NAND flash memory5becomes ready to start. But, the judgment of whether or not the write speed is higher than or equal to the first value can be executed using various other methods based on the first information included in each write command. Note that the first value is automatically controlled to approach a value to be determined from the size of the SRAM write buffer421, the DRAM write buffer63or the virtual write buffer64, the bandwidth of the SRAM42, the bandwidth of the DRAM6or the like.

Next, the flow of write data in a memory system according to each of comparative examples will be described.FIG.4illustrates the flow of write data in the write process of the memory system according to the first comparative example. The first comparative example is an example in which write data corresponding to all groups is written to a NAND flash memory5A via a small-size write buffer421A, which is a volatile memory.

In the first comparative example, a controller manages the total amount of write data (unwritten data) corresponding to each of a plurality of groups. When the total amount of write data corresponding to a certain group reaches and exceeds the minimum write size, the controller loads the write data having the minimum write size from a host write buffer221A to the small-size write buffer421A. The write data loaded into the small-size write buffer421A is then written to the NAND flash memory5A. Here, write data having such a size that can be written to the NAND flash memory5A is loaded into the small write buffer421A, the period during which this write data is stored in the small-size write buffer42A is shortened. With this configuration, each of the write data on the small-size write buffer421A will not be overtaken by any other write data.

That is, the write data first loaded from the host write buffer221A into the small-size write buffer421A is written first from the small-size write buffer421A into the NAND flash memory5A. The write data second loaded from the host write buffer221A into the small-size write buffer4is written second to the NAND flash memory5A from the small-size write buffer421A. The write data third loaded into the small-size write buffer421A from the host write buffer221A is written third to the NAND flash memory5A from the small-size write buffer421A. The, the write data fourth loaded from the host write buffer221A into the small-size write buffer421A is written fourth to the NAND flash memory5A from the small-size write buffer421A.

As described above, (i) the order in which write data are loaded from the host write buffer221A to the small-size write buffer421A and (ii) the order in which the write data are written from the small-size write buffer421A to the NAND flash memory5A are the same.

However, write data associated with a group having a slow write speed may take a long time before the total amount of write data reaches or exceeds the minimum write size. In this case, this write data is not loaded for a long time from the host write buffer221A to the small-size write buffer421A. Until the write data associated with the group with the slow write speed is loaded into the small-size write buffer421A, it is required that the write data should be maintained in the host write buffer221A. As a result, the controller cannot return a completion response to the host for each of the write commands belonging to the group having the slow write speed, and thus the latency of the command process is prolonged.

In addition, when there are a large number of groups having a slow write speed, the host write buffer221A may be occupied by the write data of these groups with the slow write speed.

FIG.5illustrates the flow of write data in a write process of a memory system according to the second comparative example. In the second comparative example, write data corresponding to all groups are written to the NAND flash memory5B via a large-size write buffer63B, which is a volatile memory.

In the second comparative example, in response to receiving one write command, the controller loads write data associated with that write command from a host write buffer221B to the large size write buffer63B. Then, when the total amount of write data corresponding to one group, among the write data stored in the large-size write buffer63B reaches the minimum write size, the controller writes the write data having the minimum write size from the large-size write buffer63B to the NAND flash memory5. With this configuration, the write data loaded into the large-size write buffer63B remains in the large-size write buffer63B until it reaches the minimum write size. Therefore, the period during which write data is stored in the large-size write buffer63B is prolonged. As a result, the write data may be overtaken by write data associated with another group on the large-size write buffer63B.

In other words, even in the case of write data loaded first from the host write buffer221B to the large-size write buffer63B, if the timing of the total amount of unwritten data in the group corresponding to that write data reaching the minimum write size is the second, then the timing of the writing from the large-size write buffer63B to the NAND flash memory5B will be the second. Even in the case of write data loaded second from the host write buffer221B to the large-size write buffer63B, if the timing of the total amount of unwritten data of the group corresponding to that write data reaching the minimum write size is the fourth, then the timing of the writing from the large-size write buffer63B to the NAND flash memory5B will be the fourth. Even in the case of write data loaded third from the host write buffer221B to the large-size write buffer63B, if the timing of the total amount of unwritten data of the group corresponding to that write data reaching the minimum write size is the first, then the timing of the writing from the large-size write buffer63B to the NAND flash memory5B will be the first. Further, even in the case of write data loaded fourth from the host write buffer221B to the large-size write buffer63B, if the timing of the total amount of unwritten data of the group corresponding to that write data reaching the minimum write size is the third, then the timing of the writing from the large-size write buffer63B to the NAND flash memory5B will be the third.

As described above, (i) the order in which write data are loaded from the host write buffer221B to the large-size write buffer63B and (ii) the order in which the write data are written from the large-size write buffer63B to the NAND flash memory5A are different from each other.

Next, the write process executed in the SSD3according to the embodiment will be described.FIG.6illustrates the flow of write data in the write process of the memory system according to the embodiment.

Upon receiving a plurality of write commands, the flash management unit433of the SSD3classifies these write commands into a plurality of groups for writing data to different write destination blocks. More specifically, the flash management unit433classifies the plurality of write commands into the plurality of groups, based on the second information included in each of the plurality of write commands.

When each write command issued to the SSD3is a write command which directly specifies a write destination super block, each write command includes the size of write data, the super block address, the start LBA, and the data pointer. The size of the write data is expressed, for example, by the number of LBAs. The super block address is information which indicates a super block to which the write data is to be written. The start LBA is the starting LBA among the LBAs corresponding to the write data. The data pointer is information which indicates a memory location of the host write buffer221, where the write data is stored. The flash management unit433classifies the received plurality of write commands into a plurality of groups based on the super block address included in each of the received write commands, so that a set of write commands that specify the same super block address belong to the same group.

When each write command issued to the SSD3is a write command used for the multi-stream writing, each write command includes the size of write data, the stream ID, the start LBA, and the data pointer. The data associated with a set of write commands having the same stream ID is, for example, data with the same expected lifetime or data associated with the same application. Based on the stream IDs included respectively in the plurality of write commands received, the flash management unit433classifies the received write commands into a plurality of groups so that a set of write commands that specify the same stream ID belong to the same group.

When each write command issued to the SSD3is a write command that specifies the QoS domain of the write destination, each write command includes the size of write data, the QoS domain ID, the placement ID, the start LBA, and the data pointer. Based on the QoS domain ID and the placement ID included in each of the received write commands, the flash management unit433classifies the received write commands into a plurality of groups so that a set of write commands having the same combination of the specified QoS domain ID and the specified placement ID belong to the same group.

When each write command issued to the SSD3is a write command used in the Zoned Namespace standard, each write command includes the size of write data, the start LBA, and the data pointer. The high-order bit part of the starting LBA is an address that specifies a zone of the write destination. Based on the high-order bit part of the start LBA included in each of the received write commands, the flash management unit433classifies the received write commands into a plurality of groups so that a set of write commands that specify the same zone belong to the same group.

When each write command issued to the SSD3is a write command that specifies a namespace, each write command includes the size of write data, the namespace ID, the start LBA, and the data pointer. When the storage area is physically divided for each namespace, a single write destination block is specified by the namespace ID. In this case, the flash management unit433classifies the received write commands into a plurality of groups based on the high-order bit part of the start LBA included in each of the received write commands, so that a set of write commands that specify the same namespace ID belong to the same group.

In the following descriptions, a plurality of groups may as well be referred to as a plurality of streams. The streams are not limited to narrowly defined streams specified by stream IDs, but are broadly defined streams specified by various identifiers or various addresses described above.

The flash management unit433calculates the write speed for each of the plurality of streams based on the size of the write data included in each respective one of the received write commands. The write speed is calculated, for example, by the total amount of write data associated with the write commands issued per predetermined time.

First, the flow of data of a stream(, which may as well be referred to as the first group) whose write speed is higher than or equal to the first value among the plurality of streams will be described.

The flash management unit433determines that this stream is a stream with a fast write speed(, which may as well be referred to as a fast stream). The flash management unit433loads write data associated with the set of write commands belonging to this stream and having the minimum write size from the host write buffer221to the SRAM write buffer421. Then, the flash management unit433writes the write data loaded into the SRAM write buffer421. to the NAND flash memory5. Here, since write data having such a size that can be written to the NAND flash memory5is loaded into the SRAM write buffer421, the period during which this write data is stored in the SRAM write buffer421is shortened. With this configuration, each of the write data on the SRAM write buffer421will not be overtaken by any other write data.

That is, the write data first loaded from the host write buffer221to the SRAM write buffer421is written first to the NAND flash memory5from the SRAM write buffer421. Then, the write data second loaded from the host write buffer221to the SRAM write buffer421is written second to the NAND flash memory5from the SRAM write buffer421. The write data third loaded from the host write buffer221to the SRAM write buffer421is written third to the NAND flash memory5from the SRAM write buffer421. The write data fourth loaded from the host write buffer221to the SRAM write buffer421is written fourth to the NAND flash memory5from the SRAM write buffer421.

As described above, (i) the order in which write data are loaded from the host write buffer221to the SRAM write buffer421and (ii) the order in which write data are written from the SRAM write buffer421to the NAND flash memory5are the same.

In this manner, the write data associated with the fast stream is written to the NAND flash memory5via the SRAM write buffer421. Therefore, the write data associated with the fast stream can be written to the NAND flash memory5at a higher speed as compared to the case where the write data associated with the fast stream is written to the NAND flash memory5via the DRAM write buffer63.

Next, the data flow of the stream whose write speed is less than the first value(, which may as well be referred to as the second group) among the plurality of streams will be described.

The flash management unit433determines that this stream is a stream with a slow write speed(, which may as well be to as a slow stream). The flash management unit433loads the write data associated with the set of write commands belonging to this stream from the host write buffer221to the DRAM write buffer63. Then, when the total amount of unwritten write data corresponding to one group among the write data stored in the DRAM write buffer63reaches the minimum write size, the flash management unit433writes the write data (unwritten write data) having the minimum write size from the DRAM write buffer63to the NAND flash memory5. Thus, write data loaded into the DRAM write buffer63is held in the DRAM write buffer63until it reaches the minimum write size. Therefore, the period during which write data is stored in the DRAM write buffer63is prolonged. In addition, write data on the DRAM write buffer63may be overtaken by any other write data on the DRAM write buffer63.

That is, even in the case of write data loaded first from the host write buffer221to the DRAM write buffer63, if the timing at which the total amount of unwritten data of the group corresponding to this write data reaches the minimum write size is the second, then the timing of the writing from the DRAM write buffer63to the NAND flash memory5will be the second. Even in the case where write data second loaded from the host write buffer221to the DRAM write buffer63, if the timing at which the total amount of unwritten data of the group corresponding to this write data reaches the minimum write size is the fourth, then the timing of the writing from the DRAM write buffer63to the NAND flash memory5will be the fourth. Even in the case of write data third loaded from the host write buffer221to the DRAM write buffer63, if the timing at which the total amount of unwritten data of the group corresponding to this write data reaches the minimum write size is the first, then the timing of the writing from the DRAM write buffer63to the NAND flash memory5will be the first. Even in the case of write data fourth loaded from the host write buffer221to the DRAM write buffer63, if the timing at which the total amount of unwritten data of the group corresponding to this write data reaches the minimum write size is the third, then the timing of the writing from the DRAM write buffer63to the NAND flash memory5will be the third.

As described above, (i) the order in which write data are loaded from the host write buffer221to the DRAM write buffer63and (ii) the order in which write data are written from the DRAM write buffer63to the NAND flash memory5are different from each other.

As described above, in the present embodiment, even when the total amount of write data associated with a slow stream is less than the minimum write size, this write data is loaded from the host write buffer221to the DRAM write buffer63. Once this write data is loaded into DRAM write buffer63, the memory area in the host write buffer221, where this write data has been stored, becomes releasable. Therefore, when the loading of write data into the DRAM write buffer63is completed, a completion response to each of the write commands belonging to the slow stream can be returned to the host2. Therefore, as compared to the comparative example described with reference toFIG.4, the latency of the command processing for the slow stream can be shortened.

FIG.7illustrates the flow of write data in another write process of the memory system according to the embodiment.

The write speed of individual streams may vary dynamically. In the second example, a write process that can follow dynamic changes in the write speed of streams is executed.

FIG.7illustrates an example case where the VWB64includes four VWBs #1 to #4 corresponding to write destination super blocks SB #1 to SB #4 and four first-in-first-out (FIFO) buffers corresponding to the four VWBs #1 to #4, respectively.

The flash management unit433fetches a plurality of write commands from the submission queue222aof the host2.

Based on the second information included in each of the plurality of write commands fetched, the flash management unit433classifies the fetched write commands into four streams respectively corresponding to the four write destination super blocks SB #1 to SB #4.

For a stream corresponding to the write destination super block SB #1, the flash management unit433stores each of the write commands belonging to this stream in the FIFO which corresponds to the VWB #1. The flash management unit433then registers information indicating the total amount of write data associated with the set of write commands stored in this FIFO and information indicating memory locations in the host write buffer221, where this write data are respectively stored, in the VWB #1. The total amount of write data associated with the set of write commands stored in this FIFO indicates the amount of unwritten data associated with the stream corresponding to the write destination super block SB #1. Unwritten data is data that has not yet been written to the NAND flash memory5. Thus, the flash management unit433manages the unwritten data associated with the stream corresponding to the write destination super block SB #1 using the VWB #1.

For a stream corresponding to the write destination super block SB #2, the flash management unit433stores each of the write commands belonging to this stream in the FIFO corresponding to the VWB #2. Then, the flash management unit433registers information indicating the total amount of write data associated with the set of write commands stored in this FIFO and information indicating memory locations in the host write buffer221, where this write data are respectively stored, in the VWB #2. The total amount of write data associated with the set of write commands stored in this FIFO indicates the amount of unwritten data associated with the stream corresponding to the write destination super block SB #2. In this manner, the flash management unit433manages the unwritten data of the stream which corresponds to the write destination super block SB #1 using the VWB #2.

For a stream corresponding to the write destination super block SB #3, the flash management unit433stores each of the write commands belonging to this stream in the FIFO which corresponds to the VWB #3. Then, the flash management unit433registers information indicating the total amount of write data associated with the set of write commands stored in this FIFO and information indicating memory locations in the host write buffer221, where this write data are respectively stored, in the VWB #3. The total amount of write data associated with the set of write commands stored in this FIFO indicates the amount of unwritten data associated with the stream corresponding to the write destination super block SB #3. In this manner, the flash management unit433manages the unwritten data of the stream which corresponds to the write destination super block SB #3 using the VWB #3.

For a stream corresponding to the write destination super block SB #4, the flash management unit433stores each of the write commands belonging to this stream in the FIFO which corresponds to the VWB #4. Then, the flash management unit433registers information indicating the total amount of write data associated with the set of write commands stored in this FIFO and information indicating memory locations in the host write buffer221, where this write data are respectively stored, in the VWB #4. The total amount of write data associated with the set of write commands stored in this FIFO indicates the amount of unwritten data associated with the stream corresponding to the write destination super block SB #4. Thus, the flash management unit433manages the unwritten data of the stream corresponding to the write destination super block SB #4 the using VWB #4.

Of the VWBs #1 to #4, each VWB in which a new write command whose data is not yet loaded have been arrived notifies to the scheduler434that there is a write request. Therefore, the scheduler434maintains a list of VWBs in which new write commands whose data are not yet loaded data have been arrived, that is, a list of streams including new write commands whose data have not been loaded.

At the timing when preparation for the next write to the NAND flash memory5can be started, that is, in response to the start or end of the data write operation of the NAND flash memory5, the scheduler434selects either one of the VWBs in which new write commands with unloaded data have been arrived, that is, one of the streams including new write commands in which data is not yet loaded, as a VWB (stream) permitted to write.

The flash management unit433determines whether or not the amount of unwritten data registered in the VWB selected by the scheduler434is greater than or equal to the minimum write size.

Here, such an example case is assumed that the VWB #3 corresponding to the write destination super block (SB) #3 is selected by the scheduler434. The flash management unit433determines whether or not the amount of unwritten data registered in VWB #3 is greater than or equal to the minimum write size. Since the VWB #3 corresponds to the write destination super block SB #3, the amount of unwritten data registered in the VWB #3 is equal to the amount of data to be written to the write destination super block SB #3, that is, the amount of unwritten data associated with the stream corresponding to the VWB #3. Here, such a case is assumed that the amount of unwritten data registered in the VWB #3 is greater than or equal to the minimum write size.

In this case, the flash management unit433determines that the stream corresponding to the VWB #3 has a fast write speed. Then, the flash management unit433determines whether or not there is data which has already been loaded into the DRAM write buffer63, among unwritten data registered in the VWB #3. For example, in the case where the amount of unwritten data registered in the VWB #3 is less than the minimum write size when the VWB #3 is selected in the previous scheduling process, some of the unwritten data currently registered in the VWB #3 have already been loaded into the DRAM write buffer63. On the other hand, in the case where the amount of unwritten data registered in the VWB #3 is greater than or equal to the minimum write size when the VWB #3 is selected in the previous scheduling process, all of the unwritten data registered in the VWB #3 exist in the host write buffer221, and therefore none of the unwritten data registered in the VWB #3 exists in the DRAM write buffer63.

When there is unwritten data already loaded into the DRAM write buffer63, the flash management unit433loads unwritten data from each of the DRAM write buffer63and the host write buffer221into the SRAM write buffer421so that the total amount of unwritten data loaded into the SRAM write buffer421from both the DRAM write buffer63and the host write buffer221becomes the minimum write size.

Such a case will be assumed that, for example, the minimum write size is 1.5 MiB, 1.3 MiB of data among the unwritten data registered in the VWB #3 is already loaded into the DRAM write buffer63, and 0.2 MiB of data among the unwritten data registered in the VWB #3 is unloaded data.

In this case, the flash management unit433loads (copies) 1.3 MiB of data from the DRAM write buffer63to the SRAM write buffer421, and then loads 0.2 MiB of data from the host write buffer221to the SRAM write buffer421via the DRAM write buffer63or directly.

After that, the flash management unit433writes the unwritten data loaded into the SRAM write buffer421to the write destination super block SB #3.

In response to completion of the writing to the write destination super block SB #3, the flash management unit433performs the following processing. That is, the flash management unit443issues one or more completion responses corresponding to one or more write commands associated with the write data loaded from the host write buffer221to the SRAM write buffer421and written to the write destination super block SB #3, and store the one or more completion responses in the completion queue222b. In other words, the flash management unit433transmits one or more completion responses corresponding to 0.2 MiB of data among the unwritten data registered in the VWB #1, to the host2. This is because each of the completion responses corresponding to 1.3 MiB of data among the unwritten data registered in the VWB #3 has already been transmitted to the host2when these data were loaded into the DRAM write buffer63.

In the case where there is no unwritten data that has already been loaded into the DRAM write buffer63, among the unwritten data registered in the VWB #3, the flash management unit433loads the unwritten data registered in the VWB #3, which has the minimum write size, from the host write buffer221to the SRAM write buffer421. After that, the flash management unit433writes the unwritten data loaded into the SRAM write buffer421, to the write destination super block SB #3. In response to completion of the writing to the write destination super block SB #3, the flash management unit433performs the following processing. That is, the flash management unit443issues one or more completion responses corresponding to one or more write commands associated with the write data loaded from the host write buffer221to the SRAM write buffer421and written to the write destination super block SB #3, and store the one or more completion responses in the completion queue222b. That is, all of the 1.5 MiB of data registered in the VWB #3 has been loaded from the host write buffer221to the SRAM write buffer421, and therefore the flash management unit433transmits all completion responses corresponding to this 1.5 MiB of data to the host2.

Next, the case where the VWB #1 corresponding to write destination super block SB #1 is selected by the scheduler434will be described. The flash management unit433determines whether or not the total amount of unwritten data registered in the VWB #1 is greater than or equal to the minimum write size. Here, since the VWB #1 corresponds to the write destination super block SB #1, the unwritten data registered in the VWB #1 is the data to be written to the write destination super block SB #1. Here, such a case is assumed that the unwritten data registered in the VWB #1 is less than the minimum write size.

In this case, the flash management unit433determines that the stream corresponding to the VWB #1 has a slow write speed. Then, the flash management unit433loads unloaded data among the unwritten data registered in the VWB #1 from the host write buffer221to the DRAM write buffer63. Subsequently, the flash management unit433issues one or more completion responses corresponding to one or more write commands associated with the data loaded into the DRAM write buffer63, and stores the one or more completion responses in the completion queue222b.

As described above, in the second example of the write process, the scheduler434selects one VWB each time the next write to the NAND flash memory5is ready to start. Then, based on whether or not the total amount of unwritten data registered in the selected VWB is greater than or equal to the minimum write size, the DRAM write buffer63or the SRAM write buffer421is selectively used. Thus, even when the write speed of some streams changes dynamically, the write buffer of the load destination can be appropriately switched between the DRAM write buffer63and the SRAM write buffer421according to the dynamic change in write speed.

In the above-provided descriptions, the case of copying data loaded into the DRAM write buffer63to the SRAM write buffer421is described, but it is possible as well to use a method of writing data loaded in the DRAM write buffer63directly to the NAND flash memory5.

Next, the procedure of the write process will be described.FIG.8is a flowchart illustrate the first example of the procedure of the write process in the memory system according to the embodiment.

The controller4receives a plurality of write commands from the host2(step S101).

The controller4classifies the received write commands into a plurality of groups respectively corresponding to a plurality of write destination blocks (step S102). More specifically, the controller4classifies the received write commands respectively into a plurality of groups based on the second information included in each of the received write commands.

The controller4selects one group among groups each including a new write commands whose data has not yet been loaded, as a group permitted to write to the NAND flash memory5(step S103). The process of selecting the one group should only be executed at a predetermined timing, and the timing for selecting the one group is not particularly limited.

The controller4determines whether or not the write speed of the group selected in S103is greater than or equal to the first value (step S104). More specifically, the controller4calculates the write speed based on the first information included in each of the plurality of write commands received in S101.

When the write speed is greater than or equal to the first value (Yes in S104), the controller4loads unloaded data associated with the group selected in S103and having the minimum write size from the host write buffer221to the SRAM write buffer421(step S105). The flash management unit433of the controller4can register information indicating the memory location in the SRAM write buffer421, where the data is loaded, to the VWB corresponding to the selected group.

The controller4writes the data loaded into the SRAM write buffer421in S105having the minimum write size to the write destination block (step S106).

In response to the completion of the write process in S106, the controller4transmits one or more completion responses indicating the completion of one or more write commands associated with the data written to the NAND flash memory5, to the host2(step S107).

When there remains an unselected group in the groups each including a new write command whose data is not yet loaded, the controller4may newly select some other one of the remaining unselected groups and perform a similar process for the newly selected other group.

In this case, the controller4determines whether or not all of the groups each including a new write commands whose data is not yet loaded have been selected (step S108).

When all of the groups each including a new write commands whose data is not yet loaded have been selected in S103(Yes in S108), the controller4terminates the write process.

When there are still unselected groups remaining in the groups each including a new write command whose data is not yet loaded (No in S108), the controller4returns to the step of S103and selects one group from the groups each including a new write command whose data is not yet loaded, that have not yet been selected.

On the other hand, when the write speed of the group selected in S103is less than the first value (No in S104), the controller4loads the data associated with the group selected in S103and not yet loaded, from the host write buffer221to the DRAM write buffer63(step S109). The flash management unit433of the controller4may register information indicating the memory location in the DRAM write buffer63, where the data is loaded, to the VWB corresponding to the selected group.

The controller4transmits one or more completion responses indicating the completion of one or more write commands associated with the data loaded into the DRAM write buffer63in S109, to the host2(step S110).

In the case where the same group as that selected in S103in the previous write process is selected, the data associated with this group may have already been loaded into the DRAM write buffer63. Therefore, the controller4determines whether or not the amount of unwritten data associated with the group selected in S103is greater than or equal to the minimum write size (step S111). For example, the flash management unit433of the controller4calculates the amount of the unwritten data, based on the information indicating the size of the write data registered in the VWB64corresponding to the selected group.

When the amount of unwritten data corresponding to the group selected in S103is greater than or equal to the minimum write size (Yes in S111), the controller4writes the data to the write destination block corresponding to the group selected in S103(step S112).

When the amount of unwritten data corresponding to the group selected in S103is less than the minimum write size (No in S111), the controller4skips the procedure of S112.

In the next write process, the group selected in S103may be selected again. In this case, data associated with this group and not yet loaded is loaded from the host write buffer221to the DRAM write buffer63. Then, when the amount of unwritten data for this group is greater than or equal to the minimum write size, the controller4writes the unwritten data associated with this group to the destination block corresponding to this group.

FIG.9is a flowchart illustrating the second example of the procedure of the write process in the memory system according to the embodiment.

Here, it is assumed that the write buffer of the load destination is appropriately switched between the DRAM write buffer63and the SRAM write buffer421according to dynamic changes in the write speed of the stream.

The controller4receives a plurality of write commands from the host2(step S201).

The controller4classifies the received write commands into a plurality of groups corresponding respectively to a plurality of write destination blocks (step S202). More specifically, the controller4classifies the received write commands into a plurality of groups based on the second information included in each of the received write commands.

The controller4calculates the amount of unwritten data associated with the same group for each of the plurality of groups (step S203). More specifically, the controller4calculates the amount of unwritten data for each group, based on the first information indicating the size of the write data registered in each VWB.

The controller4determines whether or not the data write operation in the NAND flash memory5has been started or finished (step S204).

In the case where neither the timing corresponds to when the data write operation in the NAND flash memory5has been started or finished (No in S204), the controller4waits until the data write operation in the NAND flash memory5is started or finished.

When the data write operation in the NAND flash memory5is started or finished (Yes in S204), the controller4selects one of the groups each including a new write command whose data has not yet been loaded (step S205).

The controller4determines whether or not the amount of unwritten data associated with the group selected in S205is greater than or equal to the minimum write size, based on the amount of unwritten data calculated in S203(step S206).

When the amount of unwritten data is less than the minimum write size (No in S206), the controller4loads the unloaded data associated with the group selected in S205from the host write buffer221to the DRAM write buffer63(step S207). The flash management unit433of the controller4can register information indicating the memory location in the DRAM write buffer63, where the data is loaded, to the VWB corresponding to the selected group.

The controller4transmits one or more completion responses indicating the completion of one or more write commands associated with the data loaded into the DRAM write buffer63in S207, to the host2(step S209).

When the amount of unwritten data associated with the group selected in S205is greater than or equal to the minimum write size (Yes in S206), the controller4determines whether or not there is unwritten data associated with the group selected in S205and already loaded into the DRAM write buffer63(step S209).

When there is unwritten data associated with the group selected in S205and already loaded into the DRAM write buffer63(Yes in S209), the controller4loads the unwritten data associated with the selected group from each of the DRAM write buffer63and the host write buffer221into the SRAM write buffer421so that the total amount of unwritten data loaded from both the DRAM write buffer63and the host write buffer221into the SRAM write buffer421becomes the minimum write size (step S210).

The controller4writes the data loaded into the SRAM write buffer421in S210, to the write destination block (step S211).

In response to the completion of the data write process in S211, the controller4transmits one or more completion responses indicating the completion of one or more write commands associated with the write data loaded from host write buffer221in S210to the SRAM write buffer421and written to the write destination block in S211, to the host (step S212).

The controller4that has transmitted the completion responses in S212determines whether or not all of the groups each including a new write command whose data is not yet loaded have been selected (step S213).

When all of the groups each including a new write command whose data is not yet loaded have been selected in S205(Yes in S213), the controller4terminates the write process.

When there are still unselected groups remaining in the group each including a new write command whose data is not yet loaded (No in S213), the controller4returns its operation to step S204. Then, at the timing when the data write operation in the NAND flash memory5has been started or finished, the controller4selects one group from the groups that have not yet been selected among the groups each including a new write command whose data is not yet loaded.

When there is no unwritten data associated with the selected group and already loaded in the DRAM write buffer63(No in S209), the controller4loads the unloaded data associated with the group selected in S205and having the minimum write size from the host write buffer221to the SRAM write buffer421(step S213).

Then, the controller4writes the data loaded into the SRAM write buffer421in S214to the write destination block (step S211) and transmits one or more completion responses indicating the completion of one or more write commands associated with the data written to the write destination block in S211, to the host2(step S212).

The controller4that has transmitted the completion responses in S212determines whether or not all of the groups each including a new write command whose data is not yet loaded have been selected (step S213).

When the groups including a new write commands whose data is not yet loaded are all selected in S205(Yes in S213), the controller4terminates the write process.

When there are still unselected groups remaining in the group each including a new write commands whose data is not yet loaded (No in S213), the controller4returns its operation to step S204.

Next, the operation to be executed when a write command is received from the host2will be described in detail.FIG.10is a flowchart illustrating the procedure at the time of receiving a write command in the memory system according to the embodiment.

The controller4receives a write command from the host2(step S301). More specifically, the controller4fetches the write command from the submission queue222a.

The controller4adds the size of the write data associated with the received write command to the amount of unwritten data in the group to which the write command received in S301belongs, thereby updating the amount of unwritten data (step S302).

The controller4determines whether or not unwritten data is being loaded into the DRAM write buffer63(step S303).

When the unwritten data is being loaded into the DRAM write buffer63(Yes in S303), the controller4terminates the write command receiving operation.

When unwritten data is not being loaded into the DRAM write buffer63(No in S303), the flash management unit433of the controller4notifies to the scheduler434of controller4that a new write command whose data is not yet loaded exists in the group to which the write command received in S301belongs (step S304).

Next, the procedure for writing data to the NAND flash memory after the completion of the write command receiving operation shown inFIG.10will be described.FIG.11is a flowchart illustrating the procedure of the write operation executed in the memory system according to the embodiment. In the controller4, the scheduler434of the controller4selects one group from a plurality of groups in response to the start or end of a data write operation of the NAND flash memory5and starts the write operation corresponding to the selected group. For example, the scheduler434may select one group from the groups corresponding to the notification issued in S304ofFIG.10.

The controller4determines whether or not the total amount of unwritten data associated with the group selected by the scheduler434is greater than or equal to the minimum write size (step S401).

When the total amount of unwritten data is greater than or equal to the minimum write size (Yes in S401), the controller4determines whether or not there is unwritten data associated with the selected group and already loaded in the DRAM write buffer63(step S402).

When there is unwritten data associated with the selected group and already loaded into the DRAM write buffer63(Yes in S402), the controller4copies this unwritten data from the DRAM write buffer63to the SRAM write buffer421(step S403).

When there is no unwritten data associated with the selected group and already loaded in the DRAM write buffer63(No in S402), the controller4skips the procedure of step S403.

The controller4determines whether or not write data to be written next to the write destination block have all been loaded into the SRAM write buffer421(Step S404).

When there is data that has not yet been loaded into the SRAM write buffer421among the write data to be written next to the write destination block (No in S404), the controller4loads the unloaded write data from the host write buffer221into the SRAM write buffer421(step S405).

When write data to be written next to the write destination block have all been loaded into the SRAM write buffer421(Yes in S404), the controller4skips the procedure in step S405.

The controller4sends one page of write data and write instructions from the SRAM write buffer421to the NAND flash memory5(step S406).

The controller4determines whether or not the write instructions for the minimum write size have been completed (step S407).

When the write instructions for the minimum write size have not been completed (No in S407), the controller4returns its operation to the procedure in step S402and executes the writing of the subsequent write data.

When the write instructions for the minimum write size have been completed (Yes in S407), the controller4terminates the write operation.

When the total amount of unwritten data is less than the minimum write size (No in step S401), the controller4notifies the scheduler434that the selected group will shift to a state waiting for subsequent write commands (step S408).

The controller4loads the unloaded data associated with the selected group into the DRAM write buffer63(step S409).

The controller4registers information indicating the storage location in the DRAM write buffer63, where the data is loaded in S409, in the VWB64(step S410).

Then, the controller4determines whether or not there is a write command associated with unloaded data that has not been loaded in the DRAM write buffer63and existing on the host write buffer221(step S411). The write command associated with the data which can correspond to unloaded data in step S411is, for example, a write command received during loading of data in step S409and for which the notification in step S304ofFIG.10could not be issued.

When there is a write command associated with unloaded data (Yes in S411), the controller4notifies the scheduler434that there is a write request (step S412) and terminates the write operation.

When there is no write command associated with unloaded data (No in S411), the controller4skips the procedure of step S412and terminates the write operation.

As described above, in the SSD3of the embodiment, the controller4executes either writing data using the SRAM write buffer421or writing data using the DRAM write buffer63, in accordance with the write speed of each of the plurality of groups.

When the selected group has a higher write speed, the controller4loads write data into the SRAM write buffer421and writes the loaded write data to the NAND flash memory5. That is, the controller4writes the write data to the write destination block of the NAND flash memory5via the SRAM write buffer421. Here, although it is considerable that write data is written to the NAND flash memory5via the DRAM write buffer63, in this case the bandwidth of the DRAM6may be bottlenecked, and thus the write performance of the SSD3may be limited. The bandwidth of the SRAM42is sufficiently greater compared to that of the DRAM6. Therefore, by writing the write data associated with the group having a fast write speed to the NAND flash memory5via the SRAM write buffer421, the write data can be written to the NAND flash memory5at a higher speed, compared to the case of writing the write data to the NAND flash memory5via the DRAM write buffer63.

On the other hand, when the selected group has a low write speed, write data associated with the selected group is loaded into the DRAM write buffer63, and after subsequent write commands belonging to the selected group are received and the amount of write data associated with the selected group reaches the minimum write size, the write data associated with the selected group is written to the NAND flash memory5. Therefore, the volatile memory used as the write buffer needs to have sufficient capacity to store the write data. Therefore, when all volatile memories are implemented by the SRAM42, an increase in cost may be caused. Thus, with the use of relatively inexpensive DRAM6, it is possible to avoid the increase in cost.

Further, the controller4transmits a completion response to the host2when write data is stored in the DRAM write buffer63. Thus, it is possible to shorten the latency of command processing for groups with slow write speeds.

Further, in this system, one VWB is selected each time the preparation for the next write to the NAND flash memory5becomes ready to start. Then, based on whether or not the amount of unwritten data registered in the selected VWB is greater than or equal to the minimum write size, the DRAM write buffer63or the SRAM write buffer421is selectively used. Thus, even when the write speed of some streams changes dynamically, a write buffer of the load destination can be appropriately switched between the DRAM write buffer63and the SRAM write buffer421according to the dynamic change in write speed.