DEVICE, METHOD AND SYSTEM FOR IMPROVED ELECTROSTATIC DISCHARGE PROTECTION

Techniques and mechanisms for a DC-DC voltage converter to mitigate a risk of damage to circuitry due to electrostatic discharge (ESD). In an embodiment, a protection circuit of the DC-DC voltage converter comprises a pull-up circuit and a pull-down circuit which are coupled in series between a first interconnect and a second interconnect, which are to receive a first supply voltage and a second supply voltage, respectively. A voltage divider comprises capacitors which are coupled in series with each other between the first interconnect and the second interconnect. Control circuitry is coupled with the voltage divider, and is further coupled to automatically configure a first operational mode based on an ESD event. During the first mode, the pull-up circuit is disabled and the pull-down circuit is enabled. In another embodiment, a resistor-capacitor (RC) circuit automatically transitions the protection circuit from the first mode.

BACKGROUND

1. Technical Field

This disclosure generally relates to electrostatic discharge protection and more particularly, but not exclusively, to improved performance of input/output (IO) protection or power clamp circuitry.

2. Background Art

Electrostatic discharge (ESD) refers to the phenomenon of electrical discharge of high current for a short time duration resulting from a buildup of static charge on a particular integrated circuit package, or on a nearby human handling that particular IC package. ESD events can have serious detrimental effects on manufacture and performance of integrated circuits (ICs) and other microelectronic devices, systems that contain such devices and manufacturing facilities that produce them. Advances in silicon process technology have led to the development of increasingly smaller sizes for transistors in integrated circuits. In turn, the decreasing size of transistors has made the circuits increasingly susceptible to damage from ESD events.

The electronic industry continues to scale microelectronic structure to achieve faster devices, new devices, and more per unit area. ESD continues to be a threat for scaled structures produced using various new technologies used in the electronic industry, such as, submicron device technologies, high system operation speeds, higher levels of factory automation, etc. As integrated circuit devices increase in density and their operating supply voltages decrease, the integrated circuits become more sensitive to the effects of ESD. Especially, ESD is a serious problem for semiconductor devices since it has the potential to cause malfunction of an entire IC due to device or interconnect damage. Because ESD events occur often across the silicon circuits attached to IC package terminals, circuit designers have concentrated their efforts on developing adequate protection mechanisms for these sensitive circuits.

DETAILED DESCRIPTION

Embodiments discussed herein variously provide techniques and mechanisms for efficiently mitigating the risk of damage to circuitry due to electrostatic discharge. Various direct current (DC) to DC (or “DC-DC”) voltage converters typically use a type of transistor—referred to as a “high voltage” transistor—which, as compared to other types, have relatively high breakdown voltages. High-voltage transistors typically handle about 1.8 Volts (V) to 5V or more (where more recent finFET technologies can handle 1.32 V to 2 V, for example), while low-voltage transistors are designed to operate at a smaller supply voltage—e.g., less than 1 V. and typically in a range of 0.7 V to 1 V. Accordingly, high-voltage transistors have gate lengths that can be an order of magnitude larger than low-voltage transistors. In the state-of-the-art devices, the low-voltage transistors are fabricated to have gate lengths in the sub-micron range.

Some embodiments variously provide and/or otherwise use an efficient circuit architecture which facilitates ESD protection with a DC-DC output stage. Circuitry of such an architecture (referred to herein as “protection circuitry”) is operable to provide a deterministic state of pull-up circuitry and/or pull-down circuitry. For example, protection circuitry according to some embodiments provides “keep-on/keep-off” functionality whereby pull-up circuitry is deterministically kept in an inactive (e.g., non-conducting, or “off”) state during an ESD event, while pull-down circuitry is deterministically kept in an active (e.g., conducting, or “on”) state during the ESD event. Some embodiments additionally or alternatively provide “keep-on/keep-on” functionality whereby both pull-up and pull-down circuitry are deterministically kept each in a respective active state. In providing such deterministic states, some embodiments variously improve upon existing ESD protection circuit designs—e.g., by significantly mitigating the chance of an excessively large voltage drop across a single circuit element (a single transistor, for example). These improvements facilitate the use of low-voltage transistors in a DC-DC voltage converter, which enables improved area efficiency and/or costs.

The technologies described herein may be implemented in one or more electronic devices. Non-limiting examples of electronic devices that may utilize the technologies described herein include any kind of mobile device and/or stationary device, such as cameras, cell phones, computer terminals, desktop computers, electronic readers, facsimile machines, kiosks, laptop computers, netbook computers, notebook computers, internet devices, payment terminals, personal digital assistants, media players and/or recorders, servers (e.g., blade server, rack mount server, combinations thereof, etc.), set-top boxes, smart phones, tablet personal computers, ultra-mobile personal computers, wired telephones, combinations thereof, and the like. More generally, the technologies described herein may be employed in any of a variety of electronic devices including a DC-DC voltage converter circuit.

FIG.1shows a system100which provides electrostatic discharge protection functionality according to an embodiment. System100illustrates features of one example embodiment which automatically transitions to, and subsequently from, an operational mode which prevents or otherwise mitigates circuit damage which would otherwise be possible due to an electrostatic discharge (ESD).

As shown inFIG.1, system100comprises one or more integrated circuit (IC) chips—e.g., comprising the illustrative IC101shown—and (for example) a voltage supply which provides power to some or all circuitry of the one or more IC chips. For example, system100comprises—or alternatively, is to couple to—a voltage supply102with which power is delivered to a load of IC101(such as the illustrative load circuitry160shown).

In one such embodiment, system100comprises a first interconnect (e.g., a first power supply rail) which is coupled to provide a supply voltage VDD from voltage supply102. Furthermore, system100comprises a second interconnect (e.g., a ground rail) for providing another supply voltage VSS. For example, the supply voltage VSS is a ground voltage or other suitable reference potential. The supply voltage VSS is a potential which is at a level lower than that of the supply voltage VDD. In one example embodiment, during a steady state of operations by system100, the supply voltage VDD is substantially equal to 3.3 V—e.g., wherein, during the steady state, the supply voltage VSS is substantially equal to 0 V. However, some embodiments are not limited to a particular level of supply voltage VDD or of supply voltage VSS.

In the example embodiment shown, the load circuitry160of IC101is coupled between the first and second interconnects—e.g., wherein load circuitry160is designed to perform any of various predetermined functions. In an illustrative scenario according to one embodiment, load circuitry160comprises one or more processors, controllers, memory devices, application specific integrated circuits (ASICs), input/output (IO) interfaces, and/or the like. However, some embodiments are not limited with respect to any particular function or functions that might be provided with load circuitry160.

To facilitate safe delivery of power to load circuitry160, IC101further comprises interconnected circuit elements—referred to herein as an electrostatic discharge (ESD) network-which are to provide, at least in part, a circuit path for conducting an ESD current. In the illustrative embodiment shown, IC101comprises an ESD network150which (for example) comprises a power clamp152. The power clamp152comprises a current sinking circuit in the form of a switchable discharge device coupled between the respective interconnects for providing supply voltage VDD and supply voltage VSS. In some embodiments, power clamp152includes circuitry which (for example) is adapted from any of various conventional clamp circuit designs. The details of such conventional clamp circuit designs are not set forth hereinto avoid obscuring certain features of said embodiments.

ESD network150operates in combination with a protection circuit110of IC101. Protection circuit110is operable to selectively make available another circuit path for conducting ESD current. ESD network150and protection circuit110provide functionality to protect load circuitry160, at least in part, against electrostatic discharge by non-destructively passing, for a short time period, large currents through a low impedance path—e.g., when one or more circuit elements along said path are in a conductive (or “on” state). Various other embodiments omit some or all of voltage supply102. ESD network150, and/or load circuitry160.

In the example embodiment shown, protection circuit110comprises pull-up circuitry122and pull-down circuitry132which, for example, are coupled in series with each other between the first interconnect and the second interconnect. For example, pull-up circuitry122and pull-down circuitry132are coupled to each other via a node (referred to herein as an “output node”) by which IC101provides to load circuitry160a voltage Vout which is based on supply voltages VDD. VSS. In an embodiment, pull-up circuitry122and pull-down circuitry132are further coupled to ESD network150via the output node.

In one such embodiment, pull-up circuitry122comprises first switch circuits—e.g., a first plurality of transistors-which are coupled in series with each other between the first interconnect and the output node. Additionally or alternatively, pull-down circuitry132comprises second switch circuits—e.g., a second plurality of transistors-which are coupled in series with each other between the output node and the second interconnect.

In various embodiments, protection circuit110is variously (re)configurable to operate, at different times, in any of various operational modes (or simply “modes” herein, for brevity)—e.g., based on whether load circuitry160(and/or other circuitry of IC101) is experiencing an ESD event. In one such embodiment, the modes of protection circuit110comprise a first mode which (for example) a control circuitry120of protection circuit110is to configure based on the detection of an ESD event—e.g., wherein the first mode is to provide a conductive path for an ESD current.

During the first mode, pull-up circuitry122is in a disabled state which (for example) prevents a conduction of current between the first interconnect and the output node via the pull-up circuitry122. By way of illustration and not limitation, the first mode comprises in-series switch circuits of pull-up circuitry122each being in a respective inactive (e.g., non-conducting, or “off”) state. Furthermore, during the first mode, pull-down circuitry132is in an enabled state which (for example) enables a conduction of current between the output node and the second interconnect via the pull-down circuitry132. In one such embodiment, the first mode further comprises in-series switch circuits of pull-down circuitry132each being in a respective active (e.g., conducting, or “on”) state.

In some embodiments, the modes of protection circuit110further comprise a second mode which (for example) protection circuit110automatically transitions to—e.g., based on operation of IC101according to the first mode. In one such embodiment, transitioning to the second mode comprises disabling or otherwise preventing a conductive path which is provided by the first mode. During the second mode, pull-up circuitry122is in an enabled state which (for example) enables a conduction of current between the first interconnect and the output node via the pull-up circuitry122. By way of illustration and not limitation, the second mode comprises in-series switch circuits of pull-up circuitry122each being in a respective active state. Furthermore, during the second mode, pull-down circuitry132is in a disabled state which (for example) prevents a conduction of current between the output node and the second interconnect via the pull-down circuitry132. In one such embodiment, the second mode further comprises in-series switch circuits of pull-down circuitry132each being in a respective inactive state.

In one embodiment, control circuitry120is coupled to detect one or more indicia of an ESD event, and to variously provide—e.g., to pull-up circuitry122and/or pull-down circuitry132—control signaling, based on such detecting, which transitions protection circuit110to the first mode. By way of illustration and not limitation, control circuitry120is coupled to directly or indirectly detect a change to the supply voltage VDD—e.g., wherein control circuitry120detects that such a voltage change is sufficiently large and/or sufficiently fast. In one such embodiment, control circuitry120is operable to detect a relatively high frequency component of the voltage change. Whether the component in question is sufficiently high frequency is determined, for example, based on some or all of one or more threshold voltages, biases, impedances (for example, one or more capacitances, and/or or more resistances) and/or other characteristics of the protection circuit110.

In various embodiments, the first mode provides a path by which ESD current is conducted—e.g., wherein such conduction contributes to a subsequent, and automatic, transition of IC101from the first mode (to the second mode or another mode, for example). For example, the first mode enables conduction with a resistor-capacitor (RC) circuit of protection circuit110. In this particular context, “RC circuit” refers herein to a set of circuit elements which are coupled to each other, wherein the set of circuit elements comprises at least one capacitor and at least one resistor. In an embodiment, the RC circuit has any of various suitable architectures—e.g., comprising a bridge circuit architecture-which facilitates, for each of one or more switch circuits of protection circuit110, a respective one of a turn-off time or a turn-on time. In providing these one or more turn-on times and/or one or more turn-off times, some embodiments automatically limit a duration of protection circuit110being in the first mode. In some embodiments, protection circuit110automatically transitions from the first mode to another mode (such as the second mode). For example, in transitioning to the second mode, protection circuit110(re)enables control circuitry120to detect a next ESD event—e.g., to (re)enable an automatic triggering of a next instance of the first mode based on the next ESD event.

In the example embodiment shown, control circuitry120is coupled to a voltage divider circuit105which is also coupled between the first interconnect and the second interconnect. For example, voltage divider circuit105comprises an in-series arrangement of impedance elements (e.g., comprising capacitors or resistors), wherein control circuitry120is coupled to sample or otherwise detect various voltages each between a respective two of said impedance elements. In an embodiment, configuration of the first mode comprises activating one or more elements of an RC circuit which is to limit a duration of the first mode. For example, such an RC circuit comprises one or more circuit elements of voltage divider circuit105, control circuitry120, pull-up circuitry122, and/or pull-down circuitry132.

FIG.2shows a method200for operating electrostatic discharge circuitry according to an embodiment. Method200illustrates one example of an embodiment which is performed at an integrated circuit (IC) comprising a voltage converter that provides electrostatic discharge (ESD) protection functionality by automatically transitioning to (and subsequently from) a mode which facilitates conduction of an ESD current. Operations such as those of method200are performed with any of various combinations of suitable hardware (e.g., circuitry) which, for example, provides some or all of the functionality of protection circuit110.

As shown inFIG.2, method200comprises (at210) receiving a first supply voltage at a first interconnect—e.g., including receiving the supply voltage VDD shown inFIG.1. Method200further comprises (at212) receiving at a second interconnect a second supply voltage such as a ground voltage or other reference potential.

In various embodiments, the IC comprises a voltage divider (such as voltage divider105) which includes capacitors coupled in series with each other between the first interconnect and the second interconnect. In one such embodiment, the IC further comprises a pull-up circuit and a pull-down circuit—e.g., pull-up circuitry122and pull-down circuitry132(respectively)—which are coupled in series with each other between the first interconnect and the second interconnect. For example, the IC is to provide an output voltage Vout at a first node which is between the first interconnect and the second interconnect, wherein the output voltage Vout is based on the supply voltages VDD. VSS. The IC further comprises control circuitry (such as control circuitry120) which is coupled—e.g., in a bridge configuration with the voltage divider—between the first interconnect and the second interconnect.

In various embodiments, the pull-up circuitry comprises p-channel metal-oxide semiconductor (PMOS) transistors which are coupled in series with each other between the first interconnect and the first node which provides output voltage Vout. The pull-down circuitry comprises n-channel metal-oxide semiconductor (NMOS) transistors which are coupled in series with each other between the first node and the second interconnect. In one such embodiment, the IC further comprises ballast resistors which each correspond to a different respective transistor of the PMOS transistors and the NMOS transistors. For example, each of the ballast resistors is coupled between a respective two terminals of the corresponding transistor.

Method200further comprises (at214) automatically performing a transition of the IC to a first mode based on an electrostatic discharge (ESD) event. During the first mode, the pull-up circuit is disabled and the pull-down circuit is enabled. More particularly, the first mode prevents conductivity between the first interconnect and the first node via the pull-up circuitry, wherein the first mode provides conductivity between the first node and the first interconnect via the pull-down circuitry.

In some embodiments, the control circuitry comprises pull-up control circuitry, which controls operation of the pull-up circuitry, and further comprises pull-down control circuitry which controls operation of the pull-down circuitry. In one such embodiment, one of the pull-up control circuitry or the pull-down control circuitry comprises driver circuitry which receives a first input signal based on a first voltage at a first node (e.g., between a first pair of capacitors) of the voltage divider. For example, the driver circuitry comprises an inverter circuit, and a capacitor which is coupled to the inverter circuit (e.g., at an input thereof).

Referring again toFIG.2, method200further comprises (at216) automatically transitioning the IC from the first mode with a resistor-capacitor (RC) circuit of the IC. For example, in some embodiments, one of the pull-up circuitry or the pull-down circuitry comprises a first transistor, wherein a gate terminal of the first transistor receives a first gate signal which is generated with the capacitor and the inverter circuit based on the first input signal.

In one such embodiment, the first mode comprises an activation state of the first transistor (e.g., a particular one of an active state or an inactive state), wherein a duration of the activation state of the first transistor is based on the capacitor. For example, the RC circuit, which includes the capacitor, limits a duration of the first transistor being in the activation state.

In some embodiments, the one of the pull-up circuitry or the pull-down circuitry further comprises a second transistor, wherein a gate terminal of the second transistor receives a second gate signal which is based on the first input signal. In one such embodiment, the second gate signal is generated, based on the first input signal, with a resistor which is coupled between the capacitor and the gate terminal of the second transistor.

In various embodiments, the one of the pull-up control circuitry or the pull-down control circuitry further comprises a first turn-on circuit which receives a second input signal which is based on a second voltage at a second node (e.g., between a second pair of capacitors) of the voltage divider. In one such embodiment, the first turn-on circuit provides a third gate signal, based on the second input signal, to a gate terminal of a third transistor of the one of the pull-up circuitry or the pull-down circuitry. The first mode further comprises an activation state of the third transistor, wherein a duration of the activation state of the third transistor is based on two capacitors of the voltage divider.

In one example embodiment, the pull-down circuitry comprises the first transistor, wherein the first gate signal is further generated with a first resistor based on the first input signal. The first resistor is coupled between the inverter circuit and the gate terminal of the first transistor—e.g., wherein the duration of the activation state of the first transistor is further based on the resistor.

FIG.3shows a device300which facilitates electrostatic discharge protection according to an embodiment. Device300illustrates features of one example embodiment which automatically provides a “keep-on/keep-off” mode wherein pull-up circuitry is deterministically kept in an inactive state during an ESD event, while pull-down circuitry is deterministically kept in an active state during the ESD event. In some embodiments, device300provides functionality such as that of system100—e.g., wherein one or more operations of method200are performed with circuitry of device300.

As shown inFIG.3, device300comprises a protection circuit310and an ESD network350which is coupled to protection circuit310via an “output node” by which a voltage Vout is provided to a load circuit (not shown). In the example embodiment shown, circuitry of protection circuit310is coupled between a first interconnect and a second interconnect which are to receive, respectively, a first supply voltage VDD and a second supply voltage VSS—e.g., where the voltages VDD. VSS are generated by a voltage supply (not shown) which is part of, or is to be coupled to, device300. In one such embodiment, protection circuit310provides DC-DC converter functionality to generate voltage Vout based on supply voltages VDD, VSS.

In an embodiment, protection circuit310and ESD network350correspond functionally to protection circuit110and ESD network150(respectively). For example, device300comprises pull-up transistors322and pull-down transistors332which, in some embodiments, correspond functionally to pull-up circuitry122and pull-down circuitry132(respectively). Pull-up transistors322and pull-down transistors332are controlled with pull-up control circuitry320and pull-down control circuitry330(respectively) of device300—e.g., wherein functionality of control circuitry120is provided with pull-up control circuitry320and pull-down control circuitry330. In one such embodiment, protection circuit310further comprises a voltage divider circuit305which is coupled to pull-up control circuitry320and pull-down control circuitry330—e.g., wherein voltage divider circuit305provides functionality such as that of voltage divider circuit105.

In the example embodiment shown, ESD network350comprises a p-type diode Dp which is coupled between the first interconnect and the output node. Furthermore, ESD network350comprises an n-type diode Dn which is coupled between the output node and the second interconnect. It should be appreciated that the level of supply voltage VDD at the first interconnect controls at least in part when electrical current is transmitted through diode Dp from the output node. For example, when voltage Vout at the output node is higher than the level of supply voltage VDD, diode Dp is forward biased. Hence, electrical current at the output node may be transmitted through diode Dp to first interconnect. In one illustrative embodiment, diodes Dp, Dn are shallow trench isolation (STI) diodes—e.g., wherein diode Dp includes a P+ diffusion region formed in an N-well (P+/N-well) whereas diode Dn includes an N+ diffusion region formed in a P-well (N+/P-well).

Under normal operation (e.g., not during an ESD event), diodes Dp, Dn are in reverse biased states because the supply voltage VDD at the first interconnect is at a level higher than (or equal to) the output voltage Vout, the supply voltage VSS at the second interconnect is at a level lower than the output voltage Vout. However, when an ESD event occurs, a large amount of electrical current may be transmitted through the output node which provides voltage Vout. As a result, the level of voltage Vout is at risk of being, at least temporarily, greater than that of supply voltage VDD. This causes diode Dp to become forward biased, which results in ESD current being conducted through the first interconnect to power clamp352.

In an illustrative scenario according to one embodiment, an electrostatic discharge event forces an ESD current (represented symbolically as the current source Is shown) to the output node by which the voltage Vout is provided to load circuitry. To accommodate such an ESD current, ESD network350enables one or more conductive paths between the output node and the second interconnect. By way of illustration and not limitation, one such path conducts ESD current from the output node to the first interconnect via diode Dp, and then from the first interconnect to the second interconnect via power clamp352. Protection circuit310further facilitates an additional (or alternative) path to conduct ESD current—e.g., a path from the output node to the second interconnect via pull-down transistors332.

For example, voltage divider circuit305comprises an in-series arrangement of capacitors (and/or other suitable impedance elements) which are coupled between the first interconnect and the second interconnect. Driver circuitry324of pull-up control circuitry320is coupled to receive a first signal301which is based on a first voltage at a first node between a respective two capacitors of voltage divider circuit305. Furthermore, both a turn-on/off circuit326of pull-up control circuitry320and a turn-on circuit336of pull-down control circuitry330are coupled to receive a second signal302which is based on a second voltage at a second node between a respective two capacitors of voltage divider circuit305. Further still, a driver circuitry334of pull-down control circuitry330is coupled to receive a third signal303which is based on a third voltage at a third node between a respective two capacitors of voltage divider circuit305. In one such embodiment, the first voltage is greater than the second voltage, which is greater than the third voltage.

In an embodiment, pull-up transistors322(such as the illustrative three PMOS transistors p1, p2, p3shown) are coupled, in series with each other, between the first interconnect and the output node. In the example embodiment, transistors p1, p2are coupled in series with each other between the first interconnect and transistor p3—e.g., wherein transistor p3is coupled between the output node and the transistors p1, p2. Based on signal301, driver circuitry324provides a gate voltage vpg1to selectively enable or disable transistor P1, and another gate voltage vpg2to selectively enable or disable transistor P2. Based on signal302, turn-on/off circuit326provides a gate voltage vpg3to selectively enable or disable transistor P3. In an embodiment, the difference between voltage Vout and supply voltage VDD is relatively small, as there is only a small voltage drop across diode Dp while transistors N1, N2and N3conduct a relatively high current. This small voltage difference—e.g., in combination with the respective biases of gate voltages vpg1, vpg2, vpg3-contributes to transistors P1, P2and P3remaining off.

Furthermore, pull-down transistors332(such as the illustrative three NMOS transistors N1, N2, N3shown) are coupled, in series with each other, between the output node and the second interconnect. In the example embodiment, transistors N2, N3are coupled in series with each other between the second interconnect and transistor N1—e.g., wherein transistor N1is coupled between the output node and the transistors N2, N3. Based on signal303, driver circuitry334provides a gate voltage vng2to selectively enable or disable transistor N2, and another gate voltage vng3to selectively enable or disable transistor N3. Based on signal302, turn-on circuit336provides a gate voltage vng1to selectively enable or disable transistor N1.

In some embodiments, one or more circuit elements of pull-up control circuitry320are coupled, in series with one or more other circuit elements of pull-down control circuitry330, between the first interconnect and the second interconnect. For example, one or more circuit elements of driver circuitry324are coupled in series with one or more circuit elements of turn-on/off circuit326—e.g., wherein turn-on/off circuit326is coupled to the first interconnect via driver circuitry324. Furthermore, one or more circuit elements of circuitry of driver circuitry334are coupled in series with one or more circuit elements of turn-on circuit336—e.g., wherein turn-on circuit336is coupled to the second interconnect via driver circuitry334.

Accordingly, in some embodiments, an activity state (e.g., one of an active state or an inactive state) of one of pull-up control circuitry320or pull-down control circuitry330determines, at least in part, whether the other of pull-up control circuitry320or pull-down control circuitry330is to be able to draw current from the first interconnect. Additionally or alternatively, an activity state of one of driver circuitry324or turn-on/off circuit326determines, at least in part, whether the other of driver circuitry324or turn-on/off circuit326is to be able to draw current from the first interconnect. Similarly, an activity state of one of driver circuitry334or turn-on circuitry336determines, at least in part, whether the other of driver circuitry334or turn-on circuitry336is to be able to draw current.

Although some embodiments are not limited in this regard, some or all of pull-up transistors322and/or some or all of pull-down transistors332are each coupled to a respective ballast resistor. By way of illustration and not limitation, for each of transistors P1, P2, P3, a respective one of ballast resistors Rpb1, Rpb2, Rpb3is coupled between a body terminal of the transistor and a source terminal of the transistor. Alternatively or in addition, for each of transistors N1, N2, N3, a respective one of ballast resistors Rnb1, Rnb2, Rnb3is coupled between a body terminal of the transistor and a source terminal of the transistor. Such ballast resistors facilitate parasitic bipolar junction transistor (BJT) characteristics of some or all of pull-up transistors322and/or of some or all of pull-down transistors332. In one such embodiment, a given one of one of ballast resistors Rpb1, Rpb2, Rpb3or ballast resistors Rnb1, Rnb2, Rnb3has a resistance is in a range of 5 kiloOhms (kΩ) and 15 kΩ—e.g., wherein the resistance is substantially equal to 10 kΩ. However, other embodiments have alternative ballast resistors, or omit some or all such ballast resistors.

In various embodiments, protection circuit310is variously (re)configurable to operate, at different times, in any of various operational modes comprising a first mode wherein pull-down transistors332is configured—e.g., based on the detection of an ESD event—to provide a conductive path for an ESD current. For example, in the first mode, each of the NMOS transistors N1, N2, N3is in a respective active (“on”) state—e.g., while each of the PMOS transistors P1, P2, P3is in a respective inactive (“off”) state. In some embodiments, the various operational modes further comprise a second mode which (for example) protection circuit310automatically transitions to—e.g., based on operation of protection circuit310according to the first mode. In one such embodiment, transitioning to the second mode comprises inactivating each of the NMOS transistors N1, N2, N3, and activating each of the PMOS transistors P1, P2, P3.

In some embodiments, configuration of the first mode comprises activating one or transistors of pull-up control circuitry320or pull-down control circuitry330, which enables some or all conductive paths of an RC circuit. For example, such an RC circuit comprises one or more impedance elements of voltage divider circuit305, pull-up control circuitry320and/or pull-down control circuitry330. In one such embodiment, capacitive and resistive properties of the RC circuit determine, at least in part, respective turn off times which limit a duration of pull-down transistors332being active. Alternatively or in addition, such capacitive and resistive properties determine, at least in part, respective turn on times which limit a duration of pull-down transistors332being inactive.

FIG.4shows a device400which mitigates damage due to electrostatic discharge according to an embodiment. Device400illustrates features of one example embodiment which, in a particular ESD protection mode, enables current to be conducted in an RC circuit which limits a duration of said ESD protection mode. In some embodiments, device400provides functionality such as that of system100or device300—e.g., wherein operations of method200are performed with some or all of device400.

As shown inFIG.4, device400comprises a protection circuit410and an ESD network450which is coupled to protection circuit410via a node (an “output node” herein) with which a voltage Vout is to be output to a load circuit (not shown). In an embodiment, protection circuit410and ESD network450provide functionality of protection circuit310and ESD network350(respectively). For example, a voltage divider of protection circuit410comprises an in-series arrangement of capacitors C1through C4which, for example, provide functionality such as that of voltage divider circuit105(or voltage divider circuit305). The capacitors C1-C4are coupled in series with each other between a first interconnect which is to receive a supply voltage VDD, and a second interconnect which is to receive another supply voltage VSS (such as a ground voltage or other reference potential). Protection circuit410further comprises an in-series arrangement of pull-up transistors422and pull-down transistors432, which are also coupled between the first interconnect and the second interconnect. For example, pull-up transistors422comprise PMOS transistors P1, P2, P3which are coupled in series with each other between the first interconnect and the output node, wherein pull-down transistors432comprise NMOS transistors N1, N2, N3which are coupled in series with each other between the output node and the second interconnect.

In some embodiments, functionality such as that of control circuitry120is provided with pull-up control circuitry420and pull-down control circuitry430of protection circuit410. In one such embodiment, pull-up control circuitry420and pull-down control circuitry430correspond functionally to pull-up control circuitry320and pull-down control circuitry330(respectively). By way of illustration and not limitation, driver circuitry424of pull-up control circuitry420corresponds functionally to driver circuitry324—e.g., wherein functionality such as that of turn-on/off circuit326is provided with transistors426,428of pull-up control circuitry420. Furthermore, driver circuitry434of pull-down control circuitry430corresponds functionally to driver circuitry334—e.g., wherein functionality such as that of turn-on circuitry336is provided with transistors436,438of pull-down control circuitry430.

In the example embodiment shown, driver circuitry424is coupled to receive a signal411which (for example) is provided based on a first voltage at a node401between capacitors C1, C2. Furthermore, transistors428,438are each coupled to receive a signal412which (for example) is provided based on a second voltage at a node402between capacitors C2, C3. Further still, driver circuitry434is coupled to receive a signal413which (for example) is provided based on a third voltage at a node403between capacitors C3, C4.

Although some embodiments are not limited in this regard, pull-up transistors422are each coupled to a respective one of ballast transistors Rpb1, Rpb2, Rpb3—e.g., wherein pull-down transistors432are each coupled to a respective one of other ballast transistors Rnb1, Rnb2, Rnb3. In other embodiments, protection circuit410omits some or all such ballast resistors.

In the example embodiment shown, ESD network450comprises diodes Dp, Dn and a power clamp452which (for example) has some or all of the features of power clamp152or power clamp352. In one such embodiment, protection circuit410provides functionality to selectively provide a path for conducting ESD current from ESD network450to the second interconnect via the output node to and pull-down transistors432.

For example, in one such embodiment, signals411,413are provided to the respective gate terminals of transistors P2, N2(respectively)—e.g., as the illustrative signals vpg2, vng2shown. Based on signal411(signal vpg2), driver circuitry424generates another signal vpg1, which is provided to the gate terminal of transistor P1. In the example embodiment shown, driver circuitry424comprises an inverter circuit and a capacitor Cpg1which (for example) helps limit a duration of protection circuit410being in an ESD protection mode. Furthermore, based on signal413(signal vng2), driver circuitry434generates another signal vng3, which is provided to the gate terminal of transistor P3. In the example embodiment shown, driver circuitry434comprises an inverter circuit and a capacitor Cng3which helps limit a duration of protection circuit410being in the ESD protection mode.

Further still, transistor428provides to the gate terminal of transistor P3a signal vpg3which is based on the signal412. Similarly, transistor438provides to the gate terminal of transistors N1a signal vng1which is based on the signal412. In an embodiment, a node between transistors P2. P3provides a feedback signal to the gate terminal of transistor426—e.g., wherein another node between transistors N1, N2provides a feedback signal to the gate terminal of transistor436. In one such embodiment, transistors426,436provide functionality to selectively enable or disable a conduction of current between driver circuitry424and driver circuitry434.

In an illustrative scenario according to one embodiment, pull-up control circuitry420and pull-down control circuitry430are configured to detect a spike or other relatively high frequency change to the supply voltage VDD and/or to a current conducted with the first interconnect. Such a change occurs, for example, based on an ESD event which generates a current (represented symbolically as the current source Is shown) which biases diode Dp of ESD network450to conduct said current to the first interconnect.

The change to VDD results in a sequence of changes to the respective activation states of one or more transistors of protection circuit410—e.g., including some or all of transistors426,428,436,438, transistors of driver circuitry424and/or driver circuitry434, pull-up transistors422and pull-down transistors432.

In one embodiment, an ESD event results in a first mode of protection circuit410wherein each of transistors P1, P2, P3is in a respective inactive (“off”) state, and wherein each of transistors N1, N2, N3is in a respective active (“on”) state. Such a first mode provides a path to conduct at least some ESD current from the output terminal the second interconnect via pull-down transistors432.

In various embodiments, the first mode enables one or more currents to be conducted each in a respective resistor-capacitor (RC) circuit of protection circuit410. Based on the conduction, protection circuit410is able to remain in the first mode for only a limited period of time—e.g., before protection circuit410is automatically transitioned from the first mode to some alternative mode. In one such embodiment, the alternative mode disables a path between the output node and the second interconnect via pull-down transistors432and (for example) enables a path between the first interconnect and the output node via pull-up transistors422.

A duration of one particular instance of the first mode is limited, at least in part, due to the respective keep-on times of transistors N1, N2, N3, where said keep-on times are based on RC characteristics of protection circuit410. In an illustrative scenario according to one embodiment, a keep-on time of transistor N1is limited based on an RC circuit comprising some or all of a resistor Rng1, and capacitors C3, C4(e.g., in addition to any resistance and/or capacitance properties of transistor438). Alternatively or in addition, a keep-on time of transistor N2is limited based on an RC circuit comprising some or all of a resistor Rng2, and capacitor C4. Alternatively or in addition, a keep-on time of transistor N3is limited based on an RC circuit comprising some or all of a resistor Rng3and capacitors Cng2, C4(e.g., in addition to any resistance and/or capacitance properties of the inverter in driver circuitry434).

In some embodiments, the duration of said instance of the first mode is additionally or alternatively limited, at least in part, due to the respective keep-off times of transistors P1, P2, P3, where said keep-on times are based on RC characteristics of protection circuit410. For example, a keep-off time of transistor P1is limited based on an RC circuit comprising some or all of capacitor Cpg1, a resistance of the transistors of driver circuitry424, a gate capacitance of transitor P1, resistor Rpg1, and capacitor C1. Alternatively or in addition, a keep-off time of transistor P2is limited based on an RC circuit comprising some or all of a resistance of the transistors of driver circuitry424, a gate capacitance of transitor P2, resistor Rpg2, and capacitor C1. Alternatively or in addition, a keep-off time of transistor P3is limited based on an RC circuit comprising some or all of a resistance of transistor428, capacitor C2, resistor Rpg3, and capacitor C1.

In various embodiments, the respective capacitances of capacitors C1and C4are substantially equal to each other, and the respective capacitances of capacitors C2and C3are substantially equal to each other. In one such embodiment, a ratio of capacitor C1to capacitor C2(and/or a ratio of capacitor C4to capacitor C3) is in a range of 1.5 to 3. In an illustrative scenario according to one embodiment, capacitors C1and C4are each in a range of 500 picoFarads (pF) to 3 nanoFarads (nF), wherein capacitors C2and C3are each in a range of 250 pF to 1.5 nF. In one such embodiment, a resistance of resistor Rng1is in a range of 50 Ohms (Ω) to 1 kΩ—e.g., wherein a resistance of resistor Rng2is in a range of 100Ω to 1 kΩ, and a resistance of resistor Rng3is in a range of 100 kΩ to 1 kΩ. However, in other embodiments, impedance elements of protection circuit410have any of various other suitable capacitances or resistances, according to implementation-specific details.

FIG.5shows a device500which selectively enables or disables functionality of a power clamp according to an embodiment. Device500illustrates features of one example embodiment which is operable to prevent a power clamp circuit from providing a path for conducting an ESD current. In some embodiments, device500provides functionality such as that of system100.

As shown inFIG.5, device500comprises a disable circuit505and a power clamp510which is coupled thereto. In some embodiments, device500further comprises (or alternatively, is to be coupled to) control logic502which provides a control signal Vsd to determine whether disable circuit505is to disable a functionality of power clamp510. In some embodiments, power clamp510is a clamp circuit such as one of power clamps152,352,452, for example. However, some embodiments variously provide functionality of one of protection circuit110or disable circuit505, but omit functionality of the other one of protection circuit110or disable circuit505.

Power clamp510is operable to selectively provide a conductive path by which a current—e.g., such as one generated by an ESD event—is conducted from a relatively high potential conductor to a relatively low potential conductor. In the example embodiment shown, power clamp510comprises a field effect transistor (FET)570and a FET575which are coupled in series with each other between a first interconnect and a second interconnect that, respectively, are to receive a first supply voltage VDD and a second supply voltage VSS (such as a ground voltage or other reference potential).

In one such embodiment, other circuitry of power clamp510is operable to detect any of various indicia of an ESD event (or other suitable event)—e.g., wherein power clamp510detects a change to the supply voltage VDD. Based on the detected indicia, such circuitry generates one or more signals for activating one or both of FETs570,575to provide a conductive path between the first interconnect and the second interconnect.

For example, power clamp510further comprises a clamp timer circuit550and a detector circuit560which are each also coupled between the first interconnect and the second interconnect—e.g., in parallel with each other, and in parallel with FETs570,575. Clamp timer circuit550provides functionality to receive a direct or indirect indication of a change to supply voltage VDD—e.g., wherein an RC circuit of clamp timer circuit550generates, based on the change, one or more signals552which indicate whether the change satisfies a condition for providing a conductive path via FETs570,575. For example, the one or more signals552indicate whether the voltage change has a component which is above some threshold frequency. In some embodiments, clamp timer circuit550subsequently changes some or all of the one or more signals552to automatically limit a duration of a period of time during which both of FETs570,575are active. Detector circuit560is configured to detect an ESD event based on the one or more signals552, and in response, to variously operate FETs570,575to provide a conductive path for at least some ESD current.

Disable circuit505is configured to selectively allow or prevent the above-described functionality of power clamp510by which FET570and/or FET575are operated to provide a conductive path between the first interconnect and the second interconnect. For example, control signal Vsd comprises an indication from control logic502as to whether said functionality is to be enabled or disabled. In an example embodiment, control logic502is a component of (or operates with) any of various suitable types of power management hardware or software. Alternatively or in addition, control logic502is part of a load circuit which is powered with a DC-DC converter (such as one which comprises protection circuit110).

In an illustrative scenario according to one embodiment, control signal Vsd is asserted based on control logic502determining or otherwise detecting that device500is to transition from one power state to another power state. For example, control logic502determines that a current (or expected future) power state change could result in an at least temporary change to supply voltage VDD—e.g., where said change is at risk of being incorrectly evaluated as indicating an ESD event. In an embodiment, generation of control signal Vsd includes or is otherwise based on one or more operations which (for example) are adapted from any of various conventional power management techniques. It is to be appreciated that some embodiments are not limited with respect to a particular source from which, or basis upon which, control signal Vsd is generated.

In the example embodiment shown, device500comprises a shutoff timer circuit520, a pull-down control circuit530, and a shut-off control circuit540. Shutoff timer circuit520provides a filter functionality which, for example, generates a signal522that represents a filtered version of control signal Vsd. In one such embodiment, shutoff timer circuit520mitigates the possibility of a spurious change to control signal Vsd resulting in an unintended disabling of power clamp510(especially during an ESD event, for example).

In one such embodiment, the signal522is provided to each of pull-down control circuit530and shut-off control circuit540. Pull-down control circuit530provides functionality to generate, based on signal522, one or more signals-such as the illustrative signal532shown—which are to selectively pull-down a gate terminal of FET575(or to otherwise prevent activation of FET575). Shut-off control circuit540provides functionality to generate, based on signal522, one or more other signals—such as the illustrative signal542shown—which are to selectively prevent activation of FET570. In one example embodiment, the one or more other signals (illustrated by signal542) comprises a first signal which is provided to a gate terminal of FET570, and a second signal which is provided to a source terminal of FET570.

FIG.6shows a method600for controlling operation of a power clamp circuit according to an embodiment. Operations such as those of method600are performed with any of various combinations of suitable hardware (e.g., circuitry) and/or executing software which, for example, provide some or all of the functionality of device500. The illustrative method600shows operations which are variously performed with a controller, a power clamp circuit, and a disable circuit. However, other embodiments comprise operations which are performed with only one (or, for example, only two) of such a controller, power clamp circuit, and disable circuit.

As shown inFIG.6, method600comprises (at610) receiving a first supply voltage and a second supply voltage at a first interconnect and a second interconnect, respectively. In an embodiment, a power clamp circuit (such as power clamp510) comprises an upper transistor and a lower transistor which are coupled in series with each other between the first interconnect and the second interconnect.

In some embodiments, method600further comprises (at612) performing an evaluation—e.g., at a controller such as control logic502—which detects a transition to a first power state by a load circuit. For example, the evaluation at612detects that a processor (and/or one or more other components) of the load circuit is undergoing a power state transition, or is expected to undergo a future power state transition. In one such embodiment, based on the evaluation performed at612, method600(at614) communicates an indication of the transition, via a control signal, to a disable circuit which is coupled to the controller. Method600further comprises (at616) receiving the control signal at the disable circuit (e.g., at disable circuit505).

Method600further comprises (at618) generating a first signal with a timer circuit of the disable circuit, wherein the first signal comprises a filtered—e.g., a low pass filtered—version of the control signal. Method600further comprises (at620) generating a first one or more signals, based on the first signal, with a pull-down control circuit of the disable circuit. In an embodiment, the first one or more signals are provided to selectively enable or disable the lower transistor. Method600further comprises (at622) generating a second one or more signals, based on the first signal, with a shut-off control circuit. In one such embodiment, the second one or more signals are provided to selectively enable or disable the upper transistor.

In an illustrative scenario according to one embodiment, the shut-off control circuit comprises a voltage divider which comprises two resistors coupled in series with each other between the first interconnect and the second interconnect. The shut-off control circuit further comprises an inverter circuit which is coupled between a first node, which is between the two resistors, and the second interconnect. In one such embodiment, the inverter circuit is further coupled to receive the first signal, and to generate a second signal based on the first signal. The shut-off control circuit further comprises a first transistor, coupled between the first node and a gate terminal of the upper transistor, a second transistor which is coupled between the first node and another terminal (e.g., a source terminal) of the upper transistor.

In an embodiment, respective gate terminals of the first transistor and the second transistor are each coupled to receive the second signal. In one such embodiment, the first transistor and the second transistor are PMOS transistors, wherein respective body terminals of the first transistor and the second transistor are each coupled to receive the first supply voltage. In an embodiment, the pull-down control circuit comprises a third transistor which is coupled between a gate terminal of the lower transistor and the second interconnect, wherein a gate terminal of the third transistor is coupled to receive the first signal. In one such embodiment, the third transistor is an NMOS transistor, and wherein a body terminal of the third transistor and the second transistor are each coupled to receive the second supply voltage. In an embodiment, the inverter circuit comprises a PMOS transistor and an NMOS transistor, wherein a body terminal of the PMOS transistor is coupled to receive the first supply voltage. In one such embodiment, a body terminal of the NMOS transistor is coupled to receive the second supply voltage.

FIG.7Ashows a disable circuit700which controls a power clamp according to an embodiment. Disable circuit700illustrates features of one example embodiment which is operable to prevent a power clamp from providing a conductive part for conducting an ESD current.FIG.7Bshows one example of a power clamp710which accommodates being selectively controlled with disable circuit700according to an embodiment. In some embodiments, disable circuit700and power clamp710correspond functionally to disable circuit505and power clamp510(respectively)—e.g., wherein one or more operations of method600are performed with disable circuit700and/or power clamp710.

As shown inFIG.7A, disable circuit700comprises a timer circuit720and a pull-down control circuit730which is coupled to timer circuit720. Disable circuit700further comprises a shut-off control circuit740that is coupled to timer circuit720and pull-down control circuit730. In an embodiment, shut-off control circuit740is coupled between a first interconnect and a second interconnect, which are to receive, respectively, a supply voltage VDD and another supply voltage VSS (such as a ground voltage or other reference potential).

Timer circuit720illustrates any of various filter circuit which are suitable to receive a control signal Vsd which indicates whether a power clamp (such as power clamp710) is to be disabled from providing a path for conducting an ESD current. In the example embodiment shown, timer circuit720comprises a resistor R10and a capacitor C10which are coupled in series with each other between an input terminal (or other suitable contact) by which disable circuit700receives the control signal Vsd. Pull-down control circuit730comprises a transistor N10which is coupled between a first node (represented by the symbol A shown) and the second interconnect.

In the example embodiment shown, shut-off control circuit740comprises resistors R12, R15which are coupled, in a voltage divider configuration between the first interconnect and the second interconnect, to provide a voltage Vmid which is between the respective levels of supply voltages VDD. VSS. Shut-off control circuit740further comprises a PMOS transistor P11and an NMOS transistor N11which are configured together to provide an inverter circuit between the voltage Vmid and the second interconnect. Furthermore, shut-off control circuit740comprises a PMOS transistor P12which is coupled between the voltage Vmid and a second node (represented by the symbol B shown). Further still, shut-off control circuit740comprises another PMOS transistor P14which is coupled between the voltage Vmid and a third node (represented by the symbol C shown).

Referring now toFIG.7B, power clamp710comprises NMOS transistors N0, N1which are coupled in series with each other between the first interconnect and the second interconnect. Power clamp710further comprises a clamp timer circuit750and a detector circuit760which are also coupled between the first interconnect and the second interconnect. In an embodiment, transistors N0, N1provide functionality of FET570and FET575(respectively)—e.g., wherein clamp timer circuit750and detector circuit760correspond functionally to clamp timer circuit550and detector circuit560, respectively. As shown inFIG.7B, the first node (represented by the symbol A) extends to a gate terminal of transistor N1. Furthermore, the second node extends to a gate terminal of transistor N0—e.g., wherein the third node is between transistors N0, N1. In the example embodiment shown, power clamp710further comprises a diode D1which is coupled in parallel with the circuit path comprising transistors N0, N1.

In one such embodiment, clamp timer circuit750comprises an RC network which includes resistors R0, R2, R5and capacitors C0, C1. Detector circuit760comprises PMOS transistors P0, P1which are coupled to variously receive respective signals752,754from clamp timer circuit750. When power clamp710is functional—i.e., when disable circuit700does not prevent said functionality based on control signal Vsd—detector circuit760is operable to selectively determine respective activation states of transistors N0, N1based on signals752,754.

In an illustrative scenario according to one embodiment, capacitor C10has a capacitance which is in a range of 1 picoFarads (pF) to 5 pF—e.g., wherein a resistance of resistor R10is in a range of 200 kiloOhms (kΩ) to 2 MegaOhms (MΩ). In one such embodiment, a resistance of resistor R12is in a range of 1 MΩ to 10 MΩ, and a resistance of resistor R15is in a range of 1 MΩ to 10 MΩ. In some embodiments, the RC circuit time constant of timer circuit720is greater than an expected time window of an ESD event. In one such embodiment, the time constant is greater than 500 nanoseconds (ns). However, in other embodiments, impedance elements of disable circuit700have any of various other suitable capacitances or resistances, according to implementation-specific details.

Alternatively or in addition, capacitor C0has a capacitance which is in a range of 1 pF to 10 pF, and capacitor C1has a capacitance which is in a range of 1 pF to 10 pF—e.g., wherein a resistance of resistor R0is in a range of 100 kΩ to 1 MΩ, a resistance of resistor R2is in a range of 1 MΩ to 10 MΩ, and a resistance of resistor R5is in a range of 1 MΩ to 10 MΩ. In one such embodiment, a resistance of resistor R1is in a range of 1 kΩ to 5 kΩ. However, in other embodiments, impedance elements of power clamp710have any of various other suitable capacitances or resistances, according to implementation-specific details.

In an illustrative scenario according to one embodiment, timer circuit720provides a signal722, based on control signal Vsd, which is equal to (or otherwise based on) a voltage at a node between resistor R10and capacitor C10. Signal722represents a filtered (e.g., low pass) version of control signal Vsd—e.g., to mitigate the possibility of noise in control signal Vsd resulting in an unintended disabling of power clamp710.

Signal722is provided both to pull-down control circuit730and shut-off control circuit740. In an embodiment, an assertion of control signal Vsd (and, correspondingly, of signal722)—e.g., to indicate a detected power state transition-results in activation of transistor N10, which in turn pulls down a signal732at the gate terminal of the lower (e.g., a pull-down) transistor N1. In one such embodiment, the assertion of signal722further results in the deassertion of a complementary signal741, which is provided by the inverter circuit to each of PMOS transistors P12, P14. In an embodiment, deassertion of signal741activates each of transistors P12, P14, which deactivates upper transistor N0—e.g., by providing substantially equal voltage levels of signals742,743at the second node and third node (respectively) to reduce a source-to-gate voltage at upper transistor N0.

FIG.8shows a graph800which illustrates operations performed with disable circuit700and power clamp710and a power clamp according to one example embodiment. Graph800shows an example of operational features which are exhibited during a period of time805. More particularly, graph800comprises a first axis810for various voltages at disable circuit700and power clamp710, and a second axis820for a supply current which (for example) is provided by the voltage converter circuit that is coupled to disable circuit700and power clamp710.

As shown inFIG.8, at a time to, supply voltage VDD experiences a perturbance which (for example) is due to a power state transition of a load circuit which is powered by a DC-DC voltage converter. In anticipation of the perturbance, a controller (such as control logic502or any of various other suitable control resources) asserts control signal Vsd at some earlier time. For example, control signal Vsd is asserted so that, by time t0, control signal Vsd has increased to a sufficiently high level (in this example scenario, 1.8 V) to disable the upper transistor N0and the lower transistor N1of power clamp710.

The perturbance of supply voltage VDD (which, in this example scenario, lasts to the time t1shown) results in corresponding changes to voltage Vmid, and to signals752,754. Due to the assertion of control signal Vsd, which results in activation of transistor N10, an increase (if any) to the signal732at the first node is insufficient to activate pull-down transistor N1. Furthermore, assertion of control signal Vsd results in signals742,743being substantially equal to each other, which—in turn—prevents activation of upper transistor N0.

FIG.9shows a device900which provides electrostatic discharge protection according to an embodiment. Device900illustrates features of one example embodiment which mitigates a draw of current from a voltage supply due to an electrostatic discharge event. In some embodiments, device900provides functionality such as that of device500, or (for example) that of a combination of disable circuit700and power clamp710. In one such embodiment, operations of method600are performed with device900.

As shown inFIG.9, device900comprises a disable circuit905and a power clamp910which is coupled to disable circuit905. Disable circuit905provides functionality such as that of disable circuit505or disable circuit700—e.g., wherein power clamp910provides functionality such as that of power clamp510or power clamp710.

In one such embodiment, a first interconnect of device900is configured to receive a first supply voltage VDD, wherein a second interconnect of device900is configured to receive a second supply voltage (VSS) which, for example, is a ground voltage or other reference potential. Device900further comprises an input terminal by which a control signal Vsd is received to selectively enable or disable functionality of power clamp910with disable circuit905.

Whereas various respective circuit elements of disable circuit700and power clamp710are each directly coupled to an interconnect which receives a supply voltage VDD, circuit elements of disable circuit905and power clamp910are only indirectly coupled to the first interconnect via a diode D2, and a third interconnect which provides a voltage Vsup based on the supply voltage VDD.

Other than this difference, disable circuit905is shown as having a similar circuit architecture to that of disable circuit700, and power clamp910is shown as having a similar circuit architecture to that of power clamp710. Some embodiments, in coupling some or all circuit elements of disable circuit905and power clamp910to the first interconnect via the diode D2and the third interconnect, further reduce current draw from a voltage supply. Additionally or alternatively, such embodiments variously increase robustness against voltage supply overshoots.

FIG.10illustrates a computing device1000in accordance with one embodiment. The computing device1000houses a board1002. The board1002may include a number of components, including but not limited to a processor1004and at least one communication chip1006. The processor1004is physically and electrically coupled to the board1002. In some implementations the at least one communication chip1006is also physically and electrically coupled to the board1002. In further implementations, the communication chip1006is part of the processor1004.

The processor1004of the computing device1000includes an integrated circuit die packaged within the processor1004. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The communication chip1006also includes an integrated circuit die packaged within the communication chip1006.

The exemplary computer system1100includes a processor1102, a main memory1104(e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory1106(e.g., flash memory, static random access memory (SRAM), etc.), and a secondary memory1118(e.g., a data storage device), which communicate with each other via a bus1130.

The computer system1100may further include a network interface device1108. The computer system1100also may include a video display unit1110(e.g., a liquid crystal display (LCD), a light emitting diode display (LED), or a cathode ray tube (CRT)), an alphanumeric input device1112(e.g., a keyboard), a cursor control device1114(e.g., a mouse), and a signal generation device1116(e.g., a speaker).

The secondary memory1118may include a machine-accessible storage medium (or more specifically a computer-readable storage medium)1132on which is stored one or more sets of instructions (e.g., software1122) embodying any one or more of the methodologies or functions described herein. The software1122may also reside, completely or at least partially, within the main memory1104and/or within the processor1102during execution thereof by the computer system1100, the main memory1104and the processor1102also constituting machine-readable storage media. The software1122may further be transmitted or received over a network1120via the network interface device1108.

In one or more first embodiments, an integrated circuit (IC) comprises a voltage divider comprising capacitors which are coupled in series with each other between a first interconnect and a second interconnect, wherein the first interconnect and the second interconnect are to receive a first supply voltage and a second supply voltage, respectively, a pull-up circuit and a pull-down circuit which are coupled in series with each other between the first interconnect and the second interconnect, and control circuitry coupled between the first interconnect and the second interconnect, wherein the control circuitry is coupled in a bridge configuration with the voltage divider, wherein the control circuitry is coupled to automatically perform a transition of the IC to a first mode based on an electrostatic discharge (ESD) event, and wherein, during the first mode, the pull-up circuit is disabled and the pull-down circuit is enabled, wherein an RC circuit of the IC is to automatically transition the IC from the first mode.

In one or more second embodiments, further to the first embodiment, the control circuitry comprises first driver circuitry coupled to receive a first input signal which is based on a first voltage at a first node of the voltage divider, the first driver circuitry comprises a first capacitor and a first inverter circuit, and one of the pull-up circuit or the pull-down circuit comprises a first transistor, wherein a gate terminal of the first transistor is coupled to receive a first gate signal which is generated with the first capacitor and the first inverter circuit based on the first input signal.

In one or more third embodiments, further to the second embodiment, the first mode comprises an activation state of the first transistor, and wherein a duration of the activation state of the first transistor is based on the first capacitor.

In one or more fourth embodiments, further to the second embodiment, the one of the pull-up circuit or the pull-down circuit further comprises a second transistor, wherein a gate terminal of the second transistor is coupled to receive a second gate signal which is to be based on the first input signal.

In one or more fifth embodiments, further to the fourth embodiment, the second gate signal is to be generated with a resistor based on the first input signal, wherein the resistor is coupled between the first capacitor and the gate terminal of the second transistor.

In one or more sixth embodiments, further to the fourth embodiment, the control circuitry further comprises a first turn-on circuit which is coupled to receive a second input signal which is to be based on a second voltage at a second node of the voltage divider, and the first turn-on circuit is to provide a third gate signal, based on the second input signal, to a gate terminal of a third transistor of the one of the pull-up circuit or the pull-down circuit.

In one or more seventh embodiments, further to the sixth embodiment, the first mode comprises an activation state of the third transistor, and wherein a duration of the activation state of the third transistor is to be based on two capacitors of the voltage divider.

In one or more eighth embodiments, further to the second embodiment, the pull-down circuit comprises the first transistor, the first gate signal is to be further generated with a first resistor based on the first input signal, and the first resistor is coupled between the first inverter circuit and the gate terminal of the first transistor.

In one or more ninth embodiments, further to the first embodiment or the second embodiment, the pull-up circuit comprises p-channel metal-oxide semiconductor (PMOS) transistors which are coupled in series with each other between the first interconnect and a first node, the pull-down circuit comprises n-channel metal-oxide semiconductor (NMOS) transistors which are coupled in series with each other between the first node and the second interconnect, the IC further comprises ballast resistors each corresponding to a different respective transistor of the PMOS transistors and the NMOS transistors, for each of the ballast resistors, the ballast resistor is coupled between a respective two terminals of the corresponding transistor.

In one or more tenth embodiments, a method at an integrated circuit (IC) comprises receiving a first supply voltage at a first interconnect, receiving a second supply voltage at a second interconnect, wherein the IC comprises a voltage divider comprising capacitors which are coupled in series with each other between the first interconnect and the second interconnect, a pull-up circuit and a pull-down circuit which are coupled in series with each other between the first interconnect and the second interconnect, and control circuitry coupled in a bridge configuration with the voltage divider between the first interconnect and the second interconnect, with the control circuitry, automatically performing a transition of the IC to a first mode based on an electrostatic discharge (ESD) event, and wherein, during the first mode, the pull-up circuit is disabled and the pull-down circuit is enabled, with an RC circuit of the IC, automatically transitioning the IC from the first mode.

In one or more eleventh embodiments, further to the tenth embodiment, the control circuitry comprises first driver circuitry which receives a first input signal based on a first voltage at a first node of the voltage divider, the first driver circuitry comprises a first capacitor and a first inverter circuit, and one of the pull-up circuit or the pull-down circuit comprises a first transistor, wherein a gate terminal of the first transistor receives a first gate signal which is generated with the first capacitor and the first inverter circuit based on the first input signal.

In one or more twelfth embodiments, further to the eleventh embodiment, the first mode comprises an activation state of the first transistor, and wherein a duration of the activation state of the first transistor is based on the first capacitor.

In one or more thirteenth embodiments, further to the eleventh embodiment, the one of the pull-up circuit or the pull-down circuit further comprises a second transistor, wherein a gate terminal of the second transistor receives a second gate signal which is based on the first input signal.

In one or more fourteenth embodiments, further to the thirteenth embodiment, the second gate signal is generated with a resistor based on the first input signal, wherein the resistor is coupled between the first capacitor and the gate terminal of the second transistor.

In one or more fifteenth embodiments, further to the thirteenth embodiment, the control circuitry further comprises a first turn-on circuit which receives a second input signal which is based on a second voltage at a second node of the voltage divider, and the first turn-on circuit provides a third gate signal, based on the second input signal, to a gate terminal of a third transistor of the one of the pull-up circuit or the pull-down circuit.

In one or more sixteenth embodiments, further to the fifteenth embodiment, the first mode comprises an activation state of the third transistor, and wherein a duration of the activation state of the third transistor is based on two capacitors of the voltage divider.

In one or more seventeenth embodiments, further to the eleventh embodiment, the pull-down circuit comprises the first transistor, the first gate signal is further generated with a first resistor based on the first input signal, and the first resistor is coupled between the first inverter circuit and the gate terminal of the first transistor.

In one or more eighteenth embodiments, further to the tenth embodiment or the eleventh embodiment, the pull-up circuit comprises p-channel metal-oxide semiconductor (PMOS) transistors which are coupled in series with each other between the first interconnect and a first node, the pull-down circuit comprises n-channel metal-oxide semiconductor (NMOS) transistors which are coupled in series with each other between the first node and the second interconnect, the IC further comprises ballast resistors each corresponding to a different respective transistor of the PMOS transistors and the NMOS transistors, for each of the ballast resistors, the ballast resistor is coupled between a respective two terminals of the corresponding transistor.

In one or more nineteenth embodiments, a system comprises a voltage converter comprising a voltage divider comprising capacitors which are coupled in series with each other between a first interconnect and a second interconnect, wherein the first interconnect and the second interconnect are to receive a first supply voltage and a second supply voltage, respectively, a pull-up circuit and a pull-down circuit which are coupled in series with each other between the first interconnect and the second interconnect, and control circuitry coupled between the first interconnect and the second interconnect, wherein the control circuitry is coupled in a bridge configuration with the voltage divider, wherein the control circuitry is coupled to automatically perform a transition of the voltage converter to a first mode based on an electrostatic discharge (ESD) event, and wherein, during the first mode, the pull-up circuit is disabled and the pull-down circuit is enabled, wherein an RC circuit of the voltage converter is to automatically transition the voltage converter from the first mode, an ESD network coupled to the voltage converter via an output node which is between the pull-up circuit and the pull-down circuit, and a load circuit coupled to receive an output voltage from the output node, wherein the output voltage is based on the first supply voltage and the second supply voltage.

In one or more twentieth embodiments, further to the nineteenth embodiment, the control circuitry comprises first driver circuitry coupled to receive a first input signal which is based on a first voltage at a first node of the voltage divider, the first driver circuitry comprises a first capacitor and a first inverter circuit, and one of the pull-up circuit or the pull-down circuit comprises a first transistor, wherein a gate terminal of the first transistor is coupled to receive a first gate signal which is generated with the first capacitor and the first inverter circuit based on the first input signal.

In one or more twenty-first embodiments, further to the twentieth embodiment, the first mode comprises an activation state of the first transistor, and wherein a duration of the activation state of the first transistor is based on the first capacitor.

In one or more twenty-second embodiments, further to the twentieth embodiment, the one of the pull-up circuit or the pull-down circuit further comprises a second transistor, wherein a gate terminal of the second transistor is coupled to receive a second gate signal which is to be based on the first input signal.

In one or more twenty-third embodiments, further to the twenty-second embodiment, the second gate signal is to be generated with a resistor based on the first input signal, wherein the resistor is coupled between the first capacitor and the gate terminal of the second transistor.

In one or more twenty-fourth embodiments, further to the twenty-second embodiment, the control circuitry further comprises a first turn-on circuit which is coupled to receive a second input signal which is to be based on a second voltage at a second node of the voltage divider, and the first turn-on circuit is to provide a third gate signal, based on the second input signal, to a gate terminal of a third transistor of the one of the pull-up circuit or the pull-down circuit.

In one or more twenty-fifth embodiments, further to the twenty-fourth embodiment, the first mode comprises an activation state of the third transistor, and wherein a duration of the activation state of the third transistor is to be based on two capacitors of the voltage divider.

In one or more twenty-sixth embodiments, further to the twentieth embodiment, the pull-down circuit comprises the first transistor, the first gate signal is to be further generated with a first resistor based on the first input signal, and the first resistor is coupled between the first inverter circuit and the gate terminal of the first transistor.

In one or more twenty-seventh embodiments, further to the nineteenth embodiment or the twentieth embodiment, the pull-up circuit comprises p-channel metal-oxide semiconductor (PMOS) transistors which are coupled in series with each other between the first interconnect and a first node, the pull-down circuit comprises n-channel metal-oxide semiconductor (NMOS) transistors which are coupled in series with each other between the first node and the second interconnect, the voltage converter further comprises ballast resistors each corresponding to a different respective transistor of the PMOS transistors and the NMOS transistors, for each of the ballast resistors, the ballast resistor is coupled between a respective two terminals of the corresponding transistor.