Method of forming a pressure switch thin film device

This invention provides a method of forming at least one pressure switch thin film device. The method includes providing a substrate and depositing a plurality of thin film device layers as a stack upon the substrate. An imprinted 3D template structure is provided upon the plurality of thin film device layers. The plurality of thin film device layers and the 3D template structure are then etched and at least one thin film device layer is undercut to provide a plurality of aligned electrical contact pairs and adjacent spacer posts. A flexible membrane providing a plurality of separate electrical contacts is deposited upon the spacer posts, the separate electrical contacts overlapping the contact pairs. The spacer posts provide a gap between the electrical contacts and the contact pairs.

FIELD OF THE INVENTION

The present invention relates generally to the field of forming semiconductor devices, and in particular to an improved method of making at least one pressure switch thin film device.

BACKGROUND

Socially and professionally, identification of an individual is an issue of growing importance. Passwords are commonly used, but can be shared and such sharing immediately defeats assurance of true personal identification.

Greater assurance of proper identification can be achieved with biometric verification. Voice print analysis, breath and retinal scanning have been recognized as effective means of identification, but each typically requires specialized equipment and backend processing. Fingerprint analysis has also proven to be an effective means of personal identification.

The fingerprint is comprised of a series of ridges and valleys of epidural tissue. It has been known for years that applying ink to a fingers permits an impression to be made that visually displays these ridges and valleys and permits individual identification. This impression is of course achieved because the ridges apply pressure to the paper and therefore transfer the applied ink, whereas the valleys apply no pressure and thus transfer little if any ink.

The presence of ridges and valleys in the finger print has permitted various systems to be devised that attempt to detect and recognize these same pressure point patterns in electronic form. Some of these include optical detection and others involve capacitance, and still others may employ physical pressure sensors. Indeed many computer systems now present the user with a sensor strip over which a user may drag his or her finger as a method of identification.

With respect to sensors employing physical pressure detecting devices, these are typically based on a cross point network. At each cross point there is a pressure activated contact and a resister in series. The matrix is implemented in a clam shell design. More specifically there are two substrates and each has a set of parallel features spaced about 50μ apart. On one substrate there is a stack of three thin films: a bottom layer of gold, a doped amorphous silicon layer which serves as the resister; and a second gold layer that makes up half of the mechanical contact. On this substrate all three layers are first patterned into lines and the top metal contact layer is then segmented into rectangles spaced at 50μ pitch to define individual elements at each crosspoint.

The silicon layer may be co-patterned with the top metal if its lateral conduction is significant relative to its conduction through the film. The second substrate has a set of parallel metal lines on it. The substrates are assembled with the patterned films facing each other. The parallel features on each substrate must be properly aligned so that they are orthogonal with respect to those on the other substrate.

The substrates are assembled so that the metal contacts on top of the silicon films are aligned with the metal traces on the opposing film. The substrates are held apart by some form of spacer that must also be aligned and positioned so as not to prevent contact between the metal contacts on top of the silicon films and the metal traces. A typical fingertip sensor contains 256 rows and 256 columns resulting in a sensor of approximately 13×13 mm.

When a finger is pressed down on the sensor, the substrates are forced together under the ridges closing the electrical contacts at those locations in the cross point array. Between the ridges no electrical contact is made. The pitch of the ridges on the fingertip is approximately 400μ.

The detection of a single open or closed switch in such a crosspoint resister array is a difficult problem. If all the switches are closed and voltage is applied to one row and one column, then in addition to the current that is flowing through the switch at the selected row and column, there will be additional currents flowing through all the unselected row and column resisters to ground. The ‘sneak path current’ is equal to 510 1MΩ resistors (the non-selected resistors on the selected row and column) in parallel through half the voltage drop or 255 resistors in parallel through the whole voltage drop.

This problem is not substantially changed if the unselected lines are left floating instead of being grounded. The detection problem is equivalent to detecting the difference between 255 and 256 resistors in parallel. Because these resistors ate vertical thin film resistors their resistance is hard to control and the variability will further complicate the detection problem. This detection can be made easier if the common mode signal (sneak path current) can be turned off, however this is difficult because it is data (fingerprint) dependent and will take time to isolate. Readout is also slow as it is made one pixel at a time.

Moreover, large crosstalk in the device makes detection difficult. In addition, the use of gold is expensive and the issue of precise alignment makes fabrication difficult. In the event of a short, the short will kill the row and column that it is located on. Multiple shorts will quickly result in a non-viable crosspoint array.

Due to the these technical issues, it is often more common to see applications of a sensor strip across which the fingertip is swiped. As the swipe sensor is narrower in at least one dimension it is lower in cost and it lessens some of the above issues, though they still remain.

With respect to the fabrication of the substrates, each is fabricated through traditional photolithography. In a photolithographic process, a substrate is provided and at least one material layer is uniformly deposited upon the substrate. A photo-resist layer, also commonly known simply as a photoresist, or even resist, is deposited upon the material layer, typically by a spin coating machine. A mask is then placed over the photo resist and light, typically ultra-violet (UV) light, is applied. During the process of exposure, the photoresist undergoes a chemical reaction. Generally the photoresist will react in one of two ways.

With a positive photoresist, UV light changes the chemical structure of the photoresist so that it is soluble in a developer. What “shows” therefore goes, and the mask provides an exact copy of the patterns which are to remain—such as, for example, the trace lines of a circuit.

A negative photoresist behaves in the opposite manner—the UV exposure causes it to polymerize and not dissolve in the presence of a developer. As such the mask is a photographic negative of the pattern to be left. Following the developing with either a negative or positive photoresist, blocks of photoresist remain. These blocks may be used to protect portions of the original material layer, serve as isolators or other components.

Very commonly, these blocks serve as templates during an etching process, wherein the exposed portions of the material layer are removed, such as, for example, to establish a plurality of conductive rows.

The process may be repeated several times to provide the desired thin film devices. As such, new material layers are set down on layers that have undergone processing. Such processing may inadvertently leave surface defects in the prior layers as well as unintended contaminant particles.

The crystalline texture of the materials composing each material layer, and specifically the crystalline texture of each material at an interface between materials is often of significant importance to the operation of the thin film device. Surface defects and surface contaminants may negatively affect the interfaces between layers and possibly degrade the performance of the thin film device.

In addition, photolithography is a precise process applied to small substrates. In part this is due to the high cost of the photo masks. For the fabrication of larger devices, typically rather than employing a larger and even more costly photo mask, a smaller mask is repeatedly used—a process that requires precise alignment.

As a photolithographic process typically involves multiple applications of materials, repeated masking and etching, issues of alignment between the thin film layers is of high importance. A photolithographic process is not well suited for formation of thin film devices on flexible substrates, where expansion, contraction or compression of the substrate may result in significant misalignment between material layers, thereby leading to inoperable thin film devices. In addition a flexible substrate is not flat—it is difficult to hold flat during the imprinting and/or exposure process, and thickness and surface roughness typically can not be controlled as well as they can for glass or other non-flexible substrates.

The issue of flatness in photolithography can be a problem because the minimum feature size that can be produced by a given imaging system is proportional to the wavelength of the illumination divided by the numerical aperture of the imaging system. However the depth of field of the imaging system is proportional to the wavelength of the illumination divided by the square of the numerical aperture. Therefore, as resolution is increased the flatness of the substrate quickly becomes the critical issue.

These issues of fabrication are of concern in the fabrication of a fingerprint sensor and typically limit the size of such a device to the 256 by 256 pixel device noted above. As applications may well exist where a larger device would be well suited, multiple small devices must be combined, each of which enjoys the same problems and limitations in performance and fabrication as noted above.

Hence, there is a need for a process to provide at least one pressure sensor thin film device that overcomes one or more of the drawbacks identified above.

SUMMARY

The present disclosure advances the art by providing a method of forming at least one pressure sensor thin film device.

In particular and by way of example only, according to an embodiment of the present invention, a method of forming a pressure switch thin film device including: providing a substrate; depositing a plurality of thin film device layers upon the substrate; providing a 3D template structure upon the plurality of thin film device layers, the 3D template providing all patterning and alignment for all subsequent etching and undercutting; etching the plurality of thin film device layers and 3D template structure to define a plurality of aligned electrical contact pairs and adjacent spacer posts; undercutting at least one thin film device layer to provide an active matrix; depositing a flexible membrane upon the active matrix, the membrane providing a plurality of separate electrical contacts overlapping the contact pairs, the spacer posts providing a gap between the electrical contacts and the contact pairs.

In yet another embodiment, provided is a pressure switch thin film device including: a first substrate; at least one paired set of bottom gate thin film transistors upon the first substrate as an active matrix, each paired set of transistors providing electrical contact pairs adjacent to inherently aligned spacer posts extending above the electrical contact pairs, opposite from the first substrate, each electrical contact pair separated by a physical gap having a depth, a length and a width, each electrical contact having a first dimension parallel to the length; and a second flexible substrate providing a plurality of separate electrical contacts disposed upon the spacer posts, each separate electrical contact upon the second flexible substrate having a width dimension greater than the gap width and a length dimension less than the electrical contact length, the separate electrical contacts staggered in arrangement upon the second flexible substrate; and the spacer posts providing a physical gap between the electrical contact pairs and the separate electrical contacts.

DETAILED DESCRIPTION

Before proceeding with the detailed description, it is to be appreciated that the present teaching is by way of example, not by limitation. Thus, although the instrumentalities described herein are for the convenience of explanation shown and described with respect to exemplary embodiments, it will be appreciated that the principles herein may be equally applied in other types of pressure switch thin film devices.

In at least one embodiment, the method for forming at least one pressure sensor-thin film device incorporates Self-Aligned Imprint Lithography (“SAIL”), a recently developed technique for producing multilayer patterns on flexible substrates. The basics of this process are set forth and described in U.S. Pat. No. 6,861,365 entitled “Method and System for Forming a Semiconductor Device” which is incorporated herein by reference.

In addition, in at least one embodiment, the method of forming at least one pressure sensor thin film device further incorporates a SAIL undercutting method, the basics of which are set forth and described in U.S. patent application Ser. No. 11/025,750, published as 2006/0134922A1, the disclosure of which is incorporated herein by reference.

The SAIL technique uses a 3D patterned resist and is typically employed with a roll-to-roll process. As the 3D resist is flexible, the pattern will stretch or distort to the same degree as the substrate. As such, a SAIL roll-to-roll fabrication process may be employed to provide low cost manufacturing solutions for devices such as flat and/or flexible displays, or other devices suitable for roll-to-roll processing. It shall also be realized that the disclosed method may be employed upon a non-flexible substrate while remaining within the spirit and scope of at least one embodiment.

Referring now to the drawings, the flow diagram ofFIG. 1in connection withFIGS. 2˜19conceptually illustrates at least one embodiment of a method of forming at least one pressure sensor thin film device (hereinafter “TFD”). It will be appreciated that the described process need not be performed in the order in which it is herein described, but that this description is merely exemplary of one preferred method of fabricating at least one TFD. In addition, it is understood and appreciated that the scale of the components and features illustrated in the Figures has been exaggerated to facilitate ease of discussion.

FIG. 1is a high level flowchart of a method for forming at least one TFD. As indicated in block100, the processes are generally commenced by providing a flexible substrate. A plurality of thin film device layers are then deposited upon the substrate, block102. An imprinted 3D template structure, such as an imprinted polymer, is then provided upon the plurality of thin film device layers, block104.

The plurality of thin film device layers and the 3D template structure are then etched, block106. This etching forms the rudimentary structure for a the thin film device and more specifically a plurality of aligned electrical contact pairs and adjacent spacer posts.

The rudimentary structure is further transformed into an active matrix by undercutting at least one thin film device layer, block108. As is further explained below, it is to be appreciated that under the present method, a planarizing material is not employed. More specifically, all thin film device layers are advantageously deposited before etching is performed, and subsequent planarization steps and the deposition of further material layers are not required to achieve a TFD.

A flexible membrane having a plurality of separate electrical contacts is the disposed upon the active matrix, block110. In at least one embodiment, the flexible membrane is established by providing a second flexible substrate, block112. At least one conductive layer is then deposited upon the second flexible substrate, block114. This conductive layer is then patterned to define the plurality of separate electrical contacts, block116.

Turning toFIG. 2, provided is a more detailed illustration of the initial processes described above. Specifically there is shown a portion of a substrate200. Typically, the substrate200is chemically cleaned to remove any particulate matter, organic, ionic, and or metallic impurities or debris which may be present upon the surface of the substrate200. A plurality of thin film layers202are deposited upon the substrate200as a stack, the stack having a top layer and a bottom layer. Moreover, thin film layers202may be collectively referred to as thin film stack202.

An area indicated by dotted circle204is enlarged to more clearly show the plurality of thin film layers202. In at least one embodiment, the plurality of thin film layers202include a first metal layer206and a second metal layer208with at least one material layer there between. As shown, the first metal layer206is the bottom layer and the second metal layer208is the top layer. As will be further explained below, the composition of the first metal layer206is different from the composition of the second metal layer208.

In at least one example first metal layer206and second metal layer are selected from the group of chromium, molybdenum chromium, aluminum, titanium tungsten, and or combinations thereof. These two layers (206,208) can be also made by other conductive materials such as indium tin oxide. Further, dielectric layer210can be selected from the group of silicon nitride, silicon oxide, aluminum oxide, and or combinations thereof. Further still, semiconductor layer214can be selected from the group of amorphous or micro-crystalline Si, zinc oxide, and or combinations thereof.

In at least one embodiment the pressure switch thin film device utilizes matched pairs of transistors. As such, for the purposes of discussion herein, the illustrated layers between the first metal layer206and the second metal layer208are a dielectric layer210, a channel semiconductor212, and a contact layer214. Moreover, it is appreciated that the matched pairs of transistors to be formed from thin film layers202are bottom gate transistors.

With respect to transistors, there are two types—bottom-gate transistors and top gate transistors. Bottom-gate transistors incorporating amorphous silicon are generally more desirable then top gate amorphous silicon transistors. This is due in part to better device performance in terms of a higher electron field effect mobility and a lower off-state leakage current. For purposes of discussion, the fabrication of a bottom-gate thin film transistor (TFT) will be used as an example. It is, of course, understood and appreciated that the undercutting method herein described is not limited to the fabrication of bottom-gate TFT's, but may be employed in a variety of different fabrication settings.

In at least one embodiment substrate200is a flexible substrate, such as, for example, a polyimide plastic sheet with or without an inorganic coating. In at least one alternative embodiment, substrate200is transparent. Further substrate200may be both transparent and flexible. In addition, in at least one embodiment, the plurality of thin film layers202is a stack of Aluminum, Silicon Nitride, Amorphous Silicon, N+ doped microcrystalline or amorphous Silicon, and Titanium. In an alternative embodiment, the plurality of thin film layers202is a stack of Titanium, Alumina, Zinc Oxide, and Aluminum.

Deposition of the thin film layers202may be done by vacuum deposition, gravure coating, or such other method as is appropriate for the material being deposited and/or the TFD being formed. As each of the thin film layers202is deposited directly upon the other and without intervening processing steps, such as but not limited to, masking, etching, and planarizing, the interfaces between each of the thin film layers202may be of high quality.

Typically, when one material layer is deposited upon another, the morphology surface roughness and surface chemistry of the base layer will affect the development of the structure within the deposited layer. The propagation of a desirable thin film structure is often desired to establish high quality interfaces, and ultimately the operational characteristics of the TFD. The deposition of all thin film layers202prior to further processing may advantageously permit the formation of TFDs with highly uniform and/or superior operational properties.

To provide a template for forming at least one TFD, it is desirable to have a 3D template structure over the stacked thin film layers202. In at least one embodiment, a polymer216, such as an imprint polymer or imprint resist, is deposited upon the stacked thin film layers202and imprinted by a stamping tool218. The resist or polymer216may comprise any of a variety of commercially available polymers. For example, a polymer from the Norland optical adhesives (NOA) family of polymers could be used. A silicone material may also be used as is described in patent application Ser. No. 10/641,213 entitled “A Silicone Elastomer Material for High-Resolution Lithography” which is herein incorporated by reference.

As will be further discussed below, portions of the polymer216will ultimately provide spacer posts1304(seeFIG. 13) between components of the pressure switch thin film device. As such, in at least one embodiment, polymer216is selected to be a non-conductive material.

The stamp218, though shown as a block, is in at least one embodiment provided by a stamping roller. In at least one embodiment this is a seamless imprinting roller as set forth and described in U.S. patent application Ser. No. 11/688,086 filed on Mar. 19, 2007 and entitled “Seamless Imprint Roller And Method of Making,” which is herein incorporated by reference. With further respect to roll-to-roll processing where substrate200may be of arbitrary size, yet another method for providing a 3D Structure is described in U.S. Pat. No. 6,808,646 entitled “Method of Replicating a High Resolution Three-Dimension Imprint Pattern on a Compliant Media of Arbitrary Size” which is also herein incorporated by reference.

For the formation of a TFD such as a pressure switch thin film device1800(seeFIG. 18), stamping tool218as shown has an imprinting pattern with five (5) different vertical elevations—the first, elevation Ø corresponding to the base of the stamping tool218, and elevations I, II, III and IV extending inwardly from elevation Ø.

As illustrated by arrows220, stamping tool218is brought into intimate contact with polymer216with sufficient force to imprint polymer216and establish a 3D template structure. In at least one embodiment, capillary forces are used to draw the imprint polymer216into the stamping tool218, thus permitting very low contact pressure. Stamping tool218may be translucent such that the stamped polymer may be hardened or otherwise cured, such as by UV light, to retain the 3D template structure.

FIG. 3illustrates the resulting 3D template structure300. 3D template structure300has a plurality of different levels, also know as vertical heights. Ideally, after the imprinting process there is no polymer material in areas corresponding to stamping tool218elevation Ø, however due to squeeze film effects, a thin residual film of polymer may be present. This thin residual film is generally on the order of 100 nm. As indicated above, the scale in the illustrations has been exaggerated.

As shown, each of the thin film layers202is substantially the same thickness, an arbitrary one unit. In actuality, each layer may vary in thickness. For example, typical thickness for amorphous Si as semiconductor212and doped Si as contact layer214are 100 nm and 20 nm, respectively. Further, each layer may in actuality consist of multiple layers due to the method of deposition selected. In addition, although the 3D template structure300is shown to be four arbitrary units high, the step heights in an actual polymer mask are about ten times the thickness of the thin film layers (202), i.e., 1μ versus 0.1μ.

This residual film represents 3D template structure300mask level0. 3D template structure300mask level1covers the region of thin film layers202that will ultimately form gate lines. 3D template structure300mask level2covers the region of thin film layers202that will ultimately form the channel region. 3D template structure300mask level3covers the region of thin film layers202that will ultimately form the source and drain contacts. 3D template structure300mask level4covers areas of the 3D template structure300that will provide spacer posts inherently aligned to the source and drain contacts.

In at least one embodiment, the polymer material present at mask level0is used to provide electrical isolation between features and to provide an entry area for the undercut permitted by feature302discussed below. The material providing levels1,2,3and4are the primary vertical heights used to template the formation of the pressure switch thin film device. The difference in heights between each of the primary vertical heights (1,2,3and4) is on the order of 1μ and may be different for different levels.

In a properly functioning transistor, capacitive coupling between the gate metal and the source and drain metal is minimized. 3D template structure300provides at least one feature302that is used to promote this isolation. As shown, a plurality of features302are grouped together in different areas to promote this isolation. An enlarged section bounded by dotted line304is also provided to further show the thin film layers202once again and a portion of the 3D template300.

FIG. 4illustrates the process of etching, specifically ion etching. This etching process may involve a series of etches, first to remove any residual polymer at level0, then second metal layer208, contact layer214, semiconductor layer212, dielectric layer210, and first metal layer206. Preferably, in at least one embodiment these etches are substantially anisotropic, as illustrated by arrows400being substantially perpendicular to substrate200.

Features302in 3D template structure300permit the etching process to be performed on specifically localized sections of the thin film layers202that are otherwise covered by 3D template structure. As may be more fully appreciated in partial enlarged cutaway bounded by dotted oval402, the anisotropic etching400removes material from thin film layers202so as to create a hollow below feature302.

These etches are mutually selective. Further, it is understood that generally a layer is completely removed before etching on the layer beneath is commenced. The condensed stair step depiction of removal shown inFIG. 4is intended as a composite image demonstrating multiple etching steps.

As noted above, traditional lithographic processes such as photolithography involve the steps of deposition of a layer, 2D masking, etching, and repetition of these actions in order to achieve the desired thin film device or other structure. As masking, etching and layering are performed again and again, alignment throughout the process is highly critical and substrate distortion will likely undermine the functionality of the intended device.

FIG. 5illustrates the highly advantageous nature of the SAIL process to effectively provide alignment with respect to each level of the 3D template300, the thin film layer202and the substrate200without respect to distortion. Moreover, once the 3D template is established the alignment of all features, including the spacer posts is inherently established and remains so throughout the fabrication process and into the final device regardless of any distortion.

FIG. 6illustrates the status of the forming pressure switch thin film device with the unmasked portions of the thin film layers202removed. As shown by arrows404(FIG. 4), the etching process is applied through features302of 3D template structure300as well. A cross section view bounded by dotted line600(FIG. 6) illustrates a portion of the structure and further illustrates the relative heights (0,1,2,3,4) of the 3D template structure300.

It is generally understood that an ion etching process may be accomplished by either of two traditional processes—a physical process or an assisted physical process. In a physical etching environment, no chemical agent is provided. Rather, the removal of material is entirely dependent upon the physical impact of the ions knocking atoms off the material surface by physical force alone. Physical ion etching is commonly referred to as ion milling or ion beam etching. Physical ion etching is also typically referred to as a dry process. A physical etching process is typically very anisotropic.

In an assisted physical process such as a reactive ion etching process, or RIE, removal of material comes as a combined result of chemical reactions and physical impact. Generally, the ions are accelerated by a voltage applied in a vacuum. The effect of their impact is aided by the introduction of a chemical which reacts with the surface being etched. In other words the reaction attacks and removes the exposed surface layers of the material being etched.

An RIE process advantageously permits very accurate etching of the one or more layers with little appreciable affect upon other layers. In other words, specific selection of different materials permits an RIE process to soften one layer without significantly softening another. In at least one embodiment, the removal or etching of the plurality of thin film layers202is accomplished with RIE. Although ion etching and RIE have been described in conjunction with at least one embodiment, it is understood and appreciated that one of ordinary skill in the art will recognize that a variety of different etch processes could be utilized without departing from the scope and spirit herein disclosed.

So as to provide device isolation, an undercutting process is also performed upon at least one thin film device layer. This undercutting provides at least one bridge island. More specifically, as shown inFIG. 7, in at least one embodiment, it is the first metal layer206that is undercut.

For the creation of transistors, such as the paired thin-film transistors (hereinafter “TFTs”) utilized in at least one embodiment of the pressure switch thin film device, the undercutting process also allows the source/drain to gate capacitance to be minimized thereby enabling high speed operation of the transistor and minimizing the feed through voltage that can degrade the performance of display applications.

To accomplish the undercutting, the etchant is preferably highly selective to the material of the thin film layer being undercut. It is for this reason that the composition of the first metal layer206is selected to be different from the composition of the second metal layer208. It is also important that the etch process is isotropic since lateral etching of the film to be undercut is desired. Wet or dry isotropic etches can be used.

In at least one embodiment, the first metal layer206comprises chrome and the second metal layer208comprises aluminum. By utilizing an etchant that is highly selective to first metal layer206and not second metal layer208, first metal layer206may be undercut without significant degradation to second metal layer208, or the other thin film layers.

As shown inFIG. 8the isotropic etching process indicated by arrows800is continued upon the bottom layer, shown as first metal layer206, to expose the substrate200. As is appreciated inFIG. 7this results in a plurality of simply connected regions, of which700and702are exemplary, which are otherwise isolated from other portions of first metal layer206by physical void704. Indeed, physical void704includes a physical gap706that lies directly between simply connected regions700and702.

It is understood and appreciated that in the example embodiment herein described and illustrated, dielectric layer210has not been undercut and therefore provides a single simply connected region adjacent to the plurality of simply connected regions700and702now present in the first metal layer206physical connection between the dielectric layer210vertically above the simply connected regions700and702.

The single simply connected region of the dielectric layer210, as well as that of semiconductor212, contact layer214and second metal layer208bridge over many locations of physical void704that serves to isolate the plurality of simply connected regions700and702now provided in first metal layer206. Moreover, simply connected regions700and702are bridge islands that will form the source/drain paired electrical contacts of the developing paired transistors.

It is of course realized that for the undercutting process to be effective there is preferably a significant difference in width between the width of the first metal layer206lines in the area desired to be etched through and the narrowest first metal layer206lines in the area desired to remain continuous. 3D template structure300and feature302define these areas.

Further, feature302provides the etchant to the first metal layer206in the specific area desired for undercutting. It is once again understood and appreciated that the scale of features302has been exaggerated with respect to other features of the 3D template structure300for purposes of illustration and discussion. For example the region of 3D template structure300defining the gate and channel area is likely quite different in scale from that shown.

A reasonable width to be cut through in first metal layer206with the undercutting process is about 1˜3 microns, i.e., 0.5˜1.5 micron from each side. The minimum feature width for features to remain in first metal layer206should be at least 4˜6 microns. This undercutting process advantageously permits the plurality of thin film layers202that were initially deposited in succession without intervening masking, etching, or other reforming processes to now provide at least one cross over.

Further, it shall also be noted that for a bottom gate TFT, initial deposit of thin film layers202does not restrict the minimum channel length of the device. Channel length is an important factor in determining TFT performance. Minimum channel length is only limited by imprint resolution. The imprinting process described above advantageously permits the fabrication of channel lengths less than one micron.

Although the undercutting process has been described in this example to provide simply connected regions700and702, it will be understood and appreciated by those skilled in the art that the undercutting process may also be employed to provide a released structure. Such a released structure may be desired in a TFD such as an accelerometer or other microelectromechanical system device, commonly referred to as MEMS.

As shown inFIG. 9, in at least one embodiment, following the undercutting process, the imprinted 3D template structure300is etched to expose the thin films beneath the thinnest remaining portion of the imprinted mask, level1. As may be more clearly appreciated in the cross section view bounded by dotted line900, levels2,3and4have each been reduced by a unit of height.

In others words the 3D template structure300is etched to lower the overall height sufficient to remove the lowest vertical height (e g., original material at level1). This etch exposes at least a portion of the stacked thin film layers202as representative areas902,904and906indicate. The remaining portions of 3D template structure300have also been reduced.

Etching is now performed upon the exposed portions of the stacked thin film layers202to expose first metal layer206. In at least one embodiment this etching is performed with highly selective etchants. In addition the etching process is anisotropic. The resulting structure with exposed first metal layer206is shown inFIG. 10

As shown inFIG. 11, the imprinted 3D template structure300is etched again to remove the lowest vertical height, now level2, Etching through the lowest remaining vertical height exposes at least a portion of the stacked thin film layers202. The remaining portions of 3D template structure300have also been reduced in height. A narrow channel1100in 3D template structure300now exposes second metal layer208, as the exposed portion of the thin film layers202. A cross section view bounded by dotted line1102inFIG. 11illustrates the side view of the center structure and further illustrates the respective remaining height levels3and4of 3D template structure300as being again reduced by a unit of height.

The second metal layer208as exposed through channel1100is now etched through to expose a sub layer. Specifically, in the embodiment shown, second metal layer208is etched through as is the contact layer214so as to expose the semiconductor layer212. This etching process is preferably highly anisotropic so that the exposed portion of second metal layer208is removed while portions of second metal layer208remaining beneath 3D template structure300remain substantially intact. In at least one embodiment, this is also aided by the fact that the thickness of the second metal layer208is about 1/10th the thickness of the thin metal regions adjacent to the aperture provided features302.

For the exemplary embodiment herein described,FIG. 12illustrates the exposed semiconductor layer212in channel1100. This etching to expose semiconductor layer212establishes the channel1200for developing transistors. A cross section view bounded by dotted line1202illustrates the side view of the center structure and further illustrates the respective height levels of 3D template structure300and channel1200.

As shown inFIG. 13, the lowest portion of 3D template structure300(what was initially height3) has been etched through to expose the formed electrical contact pads (e.g., the source/drain contacts) of paired bottom gate transistors1300and1302. The remaining portions of 3D template structure300(what was initially height4) now provide spacer posts1304adjacent to the exposed paired electrical contacts1306and1308of transistors1300and1302.

Moreover, the first metal layer206provides gate contacts1310, and second metal layer208provides source contacts1312and drain contacts, corresponding to electrical contacts1306and1308. More specifically, paired bottom-gate TFT1300and1302are 3D contoured structures providing at least 4 substantially different vertical heights. The gate contacts1310are provided proximate to the substrate at the lowest height. The channel1200is provided proximate to the intermediate height. The source contacts1312and drain1306,1308are provided above the channel1200, and aligned spacer posts1304are provided at the highest level.

With respect to the above description, it is understood and appreciated that the alignment of these elements is inherently established at the outset of fabrication and remains unchanged. Though distortion may occur in roll-to-roll processing, the distortion is relative to all elements such that spacer posts1304remain properly positioned with respect to electrical contacts1306and1308. Moreover, the resulting structure is an active matrix1314. A cross section view bounded by dotted line1316inFIG. 13further illustrates the remaining portion of 3D template structure300as well as channel1200.

Physical gap706separates electrical contacts1306and1308. Moreover the gap has a depth, a length1318and a width1320. Each electrical contact1306and1308has a first dimension (e.g., a length1322) substantially parallel to the gap length1318. With respect to the notion of an active matrix, the paired electrical contacts1306and1308TFT1300and1302define a pixel as indicated by dotted line1324. The pixel to pixel spacing may of course be varied depending on application, however each pixel1324defines the size and location of the functional pressure switch.

With the active matrix1314component now established a flexible membrane having a plurality of separate electrical contacts overlapping the contact pairs1306and1308is provided and disposed upon the active matrix1314. Spacer posts1304provide a gap between the electrical contacts and the contact pairs.FIGS. 14˜16provide at least one method of providing such a flexible membrane in accordance with at least one embodiment.

FIG. 14shows a portion of a flexible membrane, otherwise also referred to as a flexible substrate1400. In at least one embodiment, the flexible substrate1400is both flexible and transparent. Typically, the flexible substrate1400is chemically cleaned to remove any particulate matter, organic, ionic, and or metallic impurities or debris which may be present upon the surface of the substrate. In at least one embodiment an appropriate flexible substrate1400is selected as one that under application of about 0.01 MPa will deflect sufficiently over the distance of the pixel spacing1324so as to permit contact with the paired electrical contacts1306and1308as further described below. In at least one embodiment, flexible substrate1400is silicone rubber.

At least one layer of conductive material1402is deposited upon the substrate. Deposition of the conductive material layer1402may be done by vacuum deposition, gravure coating, or such other method as is appropriate for the material being deposited and/or the TFD being formed.

To provide a template for forming a plurality of electrical contacts, in at least one embodiment it is desirable to have a 3D template structure over the conductive material layer1402. In at least one embodiment, a polymer1404, such as an imprint polymer or imprint resist, is deposited upon the conducive material layer1402. This resist or polymer1404may comprise any of a variety of commercially available polymers. For example, a polymer from the Norland optical adhesives (NOA) family of polymers could be used. A silicone material may also be used as is described in patent application Ser. No. 10/641,213 entitled “A Silicone Elastomer Material for High-Resolution Lithography” which is herein incorporated by reference.

The stamping tool1406, though shown as a block, is in at least one embodiment provided by a stamping roller. In at least one embodiment this is a seamless imprinting roller as set forth and described in U.S. patent application Ser. No. 11/688,086 filed on Mar. 19, 2007 and entitled “Seamless Imprint Roller And Method of Making,” noted above and incorporated by reference. With further respect to roll-to-roll processing where flexible substrate1400may be of arbitrary size, yet another method for providing a 3D Structure is described in U.S. Pat. No. 6,808,646 entitled “Method of Replicating a High Resolution Three-Dimension Imprint Pattern on a Compliant Media of Arbitrary Size” which is also herein incorporated by reference.

As illustrated by arrows1408, stamping tool1406is brought into intimate contact with polymer1404with sufficient force to imprint polymer1404and establish a 3D template structure. In at least one embodiment, capillary forces are used to draw the imprint polymer1404into the stamping tool1406, thus permitting very low contact pressure. Stamping tool1406may be translucent such that the stamped polymer may be hardened or otherwise cured, such as by UV light, to retain the 3D template structure.

FIG. 15illustrates the resulting 3D template structure1500. For the purpose of establishing the plurality of electrical contacts upon the flexible substrate1400, in at least one embodiment the 3D template structure provides simple features having only one raised elevation. It is of course understood and appreciated that as described above, the 3D template structure1500may in certain embodiments provide a template structure having a plurality of different elevations.

An etching process is performed substantially as discussed and described above with respect toFIG. 4, withFIG. 16illustrating the resulting plurality of separate electrical contacts1600, of which electrical contacts1600A is exemplary. Moreover, the results of the etching process flexible membrane structure1602.

In at least one embodiment, the separate electrical contacts are presented in a staggered arrangement. Each of the separate electrical contacts, such as, for example, electrical contact1600A has a width dimension1604and a length dimension1606. In at least one embodiment, the length dimension1604is greater than the gap width1320(seeFIG. 13) and the width dimension1606is less than the electrical contact length1322(seeFIG. 13). The relationship of these dimensions is further illustrated inFIG. 18.

As shown inFIG. 17, the flexible membrane structure1602is oriented to present the plurality of separate electrical contacts1600towards the active matrix1314. As is indicated by arrows1700, the flexible membrane structure1602and active matrix1314are brought together.

FIG. 18presents the assembled pressure switch thin film device1800. In at least one embodiment, the pressure switch thin film device1800is fabricated in accordance with the above described method. As is also shown, the relationship of the length1604and width1606of electrical contact1600with respect to the length1322of the electrical contacts1306,1308and the width1320of physical gap706is also illustrated. In at least one embodiment the electrical contacts1600are of substantially equal size and shape.

AsFIGS. 14-18show partial perspective views, it is understood and appreciated that in some cases only portions of an electrical contact1600may be shown. In at least one alternative embodiment, the electrical contacts may be of varying size. In further addition, although shown to be generally rectangular, it is understood and appreciated that the electrical contacts1600may be provided in other geometric forms as well.

FIG. 19provides a cut through of the assembled pressure switch thin film device1800as shown inFIG. 18. The alignment of the thin film layers202and specifically the undercut portions of first metal layer206are also shown, as is the alignment of the channel1200and gate conductor1310.

FIG. 19also illustrates that the flexible membrane1602has a first relaxed position1900. In this first relaxed position1900it is appreciated that a physical gap1902exists and separates electrical contact1600from physically contacting either paired electrical contacts1306or1308. This gap1902is provided by the spacer posts1304displacing the flexible membrane1602from the electrical contacts1306and1308of active matrix1314.

When a force is applied, as indicated by arrows1904, such as by a fingertip1906, the flexible membrane1602distorts from the first relaxed position1900to a second deformed position1908. The deformation is localized to the areas where the force1904is applied. As shown, the deformation is sufficient to place electrical contact1600in physical contact as a bridge between electrical contacts1306and1308.

When the pressure is removed, the flexible membrane1602will return to the first relaxed state1900and the contact between electrical contact1600and electrical contacts1306and1308will cease. It is also understood and appreciated, that as flexible membrane1602provides a plurality of separate, short and redundant electrical contacts1600rather than continuous strips of contacts (powered or un-powered), the yield of the contacts1600upon the flexible membrane can be much higher than devices requiring continuous electrodes that subtend the entire array width. In addition, the failure of one or even several electrical contacts1600due to movement stress is unlikely. However, even in the event of such failure the overall functionality of the flexible membrane1602is substantially unaffected. This is highly advantageous over devices requiring continuous electrodes, the loss or damage of one or more significantly affecting the operation of the device.

Moreover, this operation yields the pressure switch which permits operation of the pressure switch thin film device1800. When electrical contact1600bridges between electrical contacts1306and1308current is permitted to flow between electrical contacts1306and1308by way of electrical contact1600.

FIG. 20illustrates at least two different circuit embodiments that employ the pressure switch thin film device1800. In the first, each pixel1324has two data lines:2000A,2002A for pixel1324A; and2000B,2002B for pixel1324B. In this first circuit, when the switch is closed by depressing the flexible membrane1602, the signal will propagate from the first TFT through the second TFT (e.g., from TFT1300to TFT1302) of the pixel1324A where the current flowing can be measured through a transconduction amplifier or even with a resistor used as a current shunt.

In the second circuit embodiment, the pixels1324A,1324B share datalines, e.g.,2004. In this case, each pixel1324A,1324B shares voltage drive lines2004and current sense lines2006with its neighbors. In at least one embodiment employing the shared circuit design, half the resolution in the device is lost, but the device has greater redundancy. For example, if multiple level detection is used then the resolution can be enhanced at the cost of greater processing (providing a greater density of pixels1324). In such a setting, if the current is 1 unit, then only one of the switches is closed, i.e.,1324A or1324B. If both pixels1324A and1324B are closed then twice the current will flow. It is understood and appreciated that other circuit arrangements may also be architected to employ the pressure switch thin film device1800.

The arrangement of the elements as shown and described is not arbitrary. If gate contacts1310are highly exposed in the pixel1324A,1324B, shorting from the actuated conductor1600might inadvertently occur. Therefore, gate contacts1300are arranged to occur on the edge of the array as shown, rather than inside the pixel1324A,1324B.

Although illustrated with respect to a single paired set of bottom-gate transistors, it will be understood and appreciated that the above described processes may be performed substantially simultaneously across a large substrate to provide a plurality of paired bottom-gate TFTs in a large matrix array. In larger form, the resulting pressure switch thin film device1800may be suitable not only for fingerprint recognition but entire hand print recognition. In addition, the pressure switch thin film device1800may be employed to detect feature differentiation in materials such as but not limited to, documents, cards, the surface of fruit, or other such materials that have surfaces with varying features.

In at least one embodiment, it is possible to achieve transparent or semi-transparent pressure switch thin film device1800via the use of Indium Tin Oxide, one of the known few transparent conductive materials. Other transparent conductive and semiconductor materials may also be used such as, for example, ZnO as well as certain organic and doped semiconductor materials. Transparent dielectrics, such as, for example, SiN or AL2O3may also be used.

Depending upon the thickness of the etched thin film layers202(the top and bottom conductors in materials therebetween) and the size of the resulting electrical contacts1306and1308of the active matrix1314and the separate electrical contacts1600of the flexible membrane1602, to some extent, pressure switch thin film devices1800made with common materials such as Al, Au, Cu, Si SiN, Cr, or the like may also be used to provide the components of the active matrix1314and flexible membrane1602of sufficiently small and thin size so as not to be visually obvious or intrusive. In other words the structures may be designed to have small enough thicknesses and small enough widths and intervening aperture spacing between components that they are either nearly transparent and/or the loss of light due to absorption is minimal.

Changes may be made in the above methods, systems and structures without departing from the scope thereof. It should thus be noted that the matter contained in the above description and/or shown in the accompanying drawings should be interpreted as illustrative and not in a limiting sense. The following claims address all generic and specific features described herein, as well as all statements of the scope of the present method, system and structure, which, as a matter of language, might be said to fall therebetween.