CMOS amplifier circuit and CCD delay line with CMOS amplifier

A CCD amplifier circuit including an active load type source-grounded inverting amplifier circuit which includes a driving MOS transistor, an active load MOS transistor connected to the driving MOS transistor, and a control circuit. The control circuit controls the voltage at the gate electrode of the active load MOS transistor with a control signal of low output impedance which is substantially inversely proportional to the drain-source voltage of the active load MOS transistor and level-shifted by a predetermined voltage. Further, a CCD delay line includes a floating diffusion region of predetermined impurities formed at an end of a charge-coupled device with a gate section having a predetermined fixed gate voltage, and a switched capacitor integrator for detecting the injection charge of the floating diffusion region to detect signal charges transferred to the floating diffusion region from the charge-coupled device. The CCD amplifier circuit is employed as an output circuit of the switched capacitor integrator.

BACKGROUND OF THE INVENTION 
The present invention relates to a CMOS amplifier circuit formed by a CMOS 
semiconductor process, and to an output circuit of a charge-coupled device 
(CCD) delay line which includes the CMOS amplifier circuit. 
Recently, integrated circuit devices (ICs and LSICs) formed by a CMOS 
semiconductor process have been extensively employed because they have 
excellent characteristics. Namely, CMOS circuits have a wide operating 
voltage range and are low in power consumption. CMOS amplifier circuits 
formed by a CMOS semiconductor process are applied to internal signal 
amplifier circuits, output power amplifier circuits, and so forth. 
A CMOS amplifier circuit AMP shown in FIG. 7 is known in the art. 
Specifically, the CMOS amplifier circuit is an active load type 
source-grounded inverting amplifier circuit. A P-channel MOS transistor 
Q.sub.1 serving as an active load has its gate and source electrodes 
connected together. An N-channel MOS transistor Q.sub.2 is connected 
between a high voltage source V.sub.CC and a low voltage source V.sub.EE 
(V.sub.CC &gt;V.sub.EE). A signal V.sub.G is applied to the gate electrode of 
the MOS transistor Q.sub.2 and subjected to inversion and amplification to 
provide an output signal V.sub.0 at the common connecting point of the 
transistors Q.sub.1 and Q.sub.2. 
It is assumed that the mutual conductance of the MOS transistor Q.sub.1 is 
represented by g.sub.mL, the resistance between the drain and the source 
thereof is represented by r.sub.dsL, the mutual conductance of the MOS 
transistor Q.sub.2 is represented by g.sub.mD, and the resistance between 
the drain and the source thereof is represented by r.sub.dsD. Hence, the 
output impedance Z.sub.0 of the amplifier circuit is as follows: 
##EQU1## 
The voltage amplification factor A.sub.V is as follows: 
EQU A.sub.V =V.sub.0 /V.sub.G =-g.sub.mD .times.Z.sub.0 ( 2) 
In the amplifier circuit, the parallel resistance of r.sub.dsL and 
r.sub.dsD has the following relationship: 
EQU (r.sub.dsL .times.r.sub.dsD)/(r.sub.dsL +r.sub.dsD)&gt;1/g.sub.mL( 3) 
Therefore, in above-described equation (2), the voltage amplification 
factor A.sub.V, can be rewritten as follows: 
EQU A.sub.V .apprxeq.-g.sub.mD /g.sub.mL ( 4) 
The above-described CMOS amplifier circuit is advantageous over a 
source-grounded inverting amplifier circuit in that it can be lower in 
impedance and it can be miniaturized. 
The signal V.sub.G applied to the gate electrode of the MOS transistor 
Q.sub.2 is generally supplied from a differential amplifier as shown in 
FIG. 7. The differential amplifier includes N-channel MOS transistors 
Q.sub.3 and Q.sub.4 forming a differential pair a constant current circuit 
I.sub.0, and P-channel MOS transistors Q.sub.5 and Q.sub.6 forming an 
active load. An input signal V.sub.I from- various circuits (not shown) is 
applied to the gate electrode of the MOS- transistor Q.sub.3. 
The amplifier circuit can also be employed as a voltage follower circuit 
which has improved linearity with the output signal V.sub.0 fed back to 
the gate electrode of the MOS transistor Q.sub.4 on the non-inverting 
input side of the differential amplifier. 
However, the above-described conventional amplifier circuit suffers from 
certain problems and disadvantages which are discussed below. 
First, as shown in FIG. 8, the threshold voltage V.sub.th of the MOS 
transistor Q.sub.1 connected to the high voltage source V.sub.CC causes 
compression of the output DC dynamic range on the side of V.sub.CC. 
Second, in the case where the CMOS amplifier circuit is used as a buffer 
amplifier where a plurality of circuits are connected to it in subsequent 
stages, it is desirable that the output impedance Z.sub.0 be low. However, 
since the voltage of the output signal V.sub.0 is increased with the 
decreasing voltage of the input signal V.sub.G of the MOS transistor 
Q.sub.2, the bias voltage V.sub.GS between the gate and the source of the 
MOS transistor Q.sub.1 is decreased, and the mutual conductance g.sub.mL 
is also decreased. Therefore, as is apparent from the above equations (2) 
and (4), as the mutual conductance g.sub.mL decreases, the output 
impedance Z.sub.0 increases. As the output impedance Z.sub.0 increases in 
this manner, the high-frequency cut-off frequency f.sub.H is decreased. As 
a result, the circuit may become unstable, resulting in undesirable 
oscillation. 
Third, the capacitance between the gate and the drain of the MOS transistor 
Q.sub.1 forms a capacitive load on the MOS transistor Q.sub.2. Hence, the 
high-frequency cut-off frequency f.sub.H is lowered by the capacitive 
load, thus making it difficult to increase the bandwidth of the circuit. 
SUMMARY OF THE INVENTION 
In view of the foregoing an object of the invention is to provide an active 
load type source-grounded inverting amplifier circuit which is superior to 
conventional active load type source-grounded inversion amplifier circuits 
in both dynamic range and bandwidth. 
Another object of the invention is to provide a CCD delay line with 
excellent characteristics and which has a CCD amplifier circuit as its 
output circuit. When employing a charge-coupled device (CCD) as a video 
signal delay line, it is essential to employ an output circuit which has a 
wide frequency band and a low output impedance. 
The foregoing objects and other objects of the invention have been achieved 
by the provision of a CCD amplifier circuit including an active load type 
inverting amplifier circuit which includes a driving MOS transistor, an 
active load MOS transistor connected to the driving MOS transistor, and a 
control circuit for controlling the voltage at the gate electrode of the 
active load MOS transistor with a control signal so as to provide low 
output impedance, the control signal being substantially inversely 
proportional to the drain-source voltage of the active load MOS transistor 
and is level-shifted by a predetermined voltage. 
In an example of the CCD amplifier circuit, the gate electrode of an active 
load MOS transistor is driven by the output of a drain-grounded buffer 
circuit having a gate electrode to which the drain-source voltage of the 
active load MOS- transistor is applied, and having a source electrode 
which is connected to a constant current source. 
In addition, in a CCD delay line in which a floating diffusion region of 
predetermined impurities is formed at the end of a charge-coupled device 
with a gate section having a predetermined fixed gate voltage, and a 
switched capacitor integrator for detecting the injection charge of the 
floating diffusion region is provided so as to detect signal charges 
transferred to the floating diffusion region from the charge-coupled 
device. The above-described CCD amplifier circuit is employed in an output 
circuit of the switched capacitor integrator. 
In the CCD amplifier circuit thus constructed, even when the output signal 
increases in voltage amplitude, neither the mutual conductance of the 
active load MOS transistor nor the pinch-off voltage is decreased because 
a forward bias voltage is applied between the gate and source electrodes 
of the active load MOS transistor at all times. 
Furthermore, because the gate capacitance of the active load MOS transistor 
is charged by a control signal of a low output impedance control circuit, 
it does not become a capacitive load on the driving MOS transistor. Hence, 
the amplitude of the output signal is not collapsed by the effect of a 
pinch-off voltage, that is, the dynamic range is increased. In addition, 
as is apparent from the above expressions (1) and (4), the output 
impedance does not increase, while the high-frequency cut-off frequency is 
increased. Thus, the resultant CCD amplifier circuit has a wide bandwidth. 
A CCD delay line capable of processing video signals having a wide 
bandwidth can be realized by applying the CCD amplifier to an output 
circuit thereof.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
An example of a CCD amplifier circuit, which constitutes an embodiment of 
the invention, will be described with reference to the accompanying 
drawings. 
First, the arrangement of the CCD amplifier circuit will be described with 
reference to FIG. 1. 
In FIG. 1, a circuit AMP is an essential part of the CCD amplifier circuit. 
The circuit AMP includes an N-channel MOS transistor Q.sub.7, which has a 
source electrode connected to a low voltage source terminal V.sub.EE and a 
gate electrode to which a signal V.sub.G to be amplified is applied, and a 
P-channel MOS transistor Q.sub.8, which has a drain electrode connected to 
a high voltage drain terminal V.sub.CC and a drain electrode connected to 
a drain electrode of the MOS transistor Q.sub.7. An output signal V.sub.0 
is provided at the connecting point P of the two MOS transistors Q.sub.7 
and Q.sub.8. As an example, the low voltage source terminal V.sub.EE can 
be ground and the high voltage source terminal V.sub.CC can be 5 volts. 
The circuit AMP further includes an N-channel MOS transistor Q.sub.9 having 
a gate electrode connected to the connecting point P, a drain electrode 
connected to the high voltage source terminal V.sub.CC, and a source 
electrode connected to a gate electrode of the MOS transistor Q.sub.8 and 
connected to the low voltage source terminal V.sub.EE through a constant 
current source I.sub.1. 
The circuit AMP thus constructed is coupled to a differential amplifier 
including, for instance, CMOS transistors and a constant current source, 
so as to be employed as a power amplifying buffer amplifier. The 
differential amplifier includes N-channel MOS transistors Q.sub.10 and 
Q.sub.11 forming a differential pair, a constant current source I.sub.2, 
and P-channel MOS transistors Q.sub.12 and Q.sub.13 serving as an active 
load for the differential pair. A gate electrode of the MOS transistor 
Q.sub.11 is connected to the connecting point P. A drain electrode of the 
MOS transistor Q.sub.10 is connected to the gate electrode of the MOS 
transistor Q.sub.7. An input signal V.sub.I from an external circuit is 
applied to a gate electrode of the MOS transistor Q.sub.10. 
The operation of the CCD amplifier circuit thus constructed is described 
below. 
The MOS transistor Q.sub.9 and the constant current circuit I.sub.1 form a 
level shifting circuit which subjects the output signal provided at the 
connecting point P to power amplification and supplies the resultant 
output signal V.sub.X to the gate electrode of the MOS transistor Q.sub.8. 
In the MOS transistor Q.sub.8, unlike its counterpart in the conventional 
amplifier circuit, the gate electrode and the source electrode are not 
connected to each other, and instead the bias voltage between the gate 
electrode and the source electrode is controlled by the output signal 
V.sub.X. 
In the case where the amplitude of the input signal V.sub.G goes towards 
the voltage V.sub.CC, the output signal V.sub.0 is inverted and amplified, 
as indicated in period .tau..sub.1 shown in FIG. 2. Further, the output 
signal V.sub.X is also inverted and amplified. Thus, the MOS transistor 
Q.sub.8 is maintained forward-biased, and the gate electrode voltage is 
decreased. 
On the other hand, in the case where the amplitude of the input signal 
V.sub.G goes towards the voltage V.sub.EE, the output signal V.sub.0 is 
inverted and amplified, as indicated in period .tau..sub.2 shown in FIG. 
2, and the output signal V.sub.X also shows a waveform inverted and 
amplified. Thus, the gate electrode voltage of the MOS transistor Q.sub.8 
is increased. In this case, the output signal V.sub.X is level-shifted by 
an amount equal to the gate-source voltage V.sub.GS of the MOS transistor 
Q.sub.9, and accordingly the gate electrode voltage of the MOS transistor 
Q.sub.8 is lower than the voltage of the output signal V.sub.0 by as much 
as the level-shifting voltage V.sub.GS. Thus, the MOS transistor Q.sub.8 
is forward-biased at all times and never pinched off. 
Accordingly, as indicated in FIG. 2, the waveform will not collapse, that 
is, the dynamic range is increased as compared to the dynamic ranges of 
conventional circuits. In addition, the mutual conductance g.sub.mL of the 
MOS transistor Q.sub.8 is not decreased because the MOS transistor Q.sub.8 
is maintained forward-biased at all times, as described above. Therefore, 
as is seen from the above equations (1), (2) and (4), the output impedance 
Z.sub.0 can be maintained low and the amplification factor A.sub.V can be 
increased. 
The gate electrode capacitors C.sub.DG and C.sub.SG of the MOS transistor 
Q.sub.8 are charged by the low impedance signal V.sub.X. Therefore, the 
capacitive load of the driving MOS transistor Q.sub.7 is reduced, and the 
high-frequency cut-off frequency f.sub.H is increased. Hence, the 
amplifier circuit is free from oscillations, stable in operation, and it 
has a wide bandwidth. 
The frequency versus gain characteristic of the CCD amplifier circuit has a 
wide bandwidth characteristic and a high-frequency cut-off frequency 
f.sub.2, as indicated by a characteristic curve A.sub.V1 in FIG. 3. The 
frequency versus gain characteristic of the differential amplifier shows a 
wide bandwidth characteristic (with a high-frequency cut-off frequency 
f.sub.1) as indicated by a characteristic curve A.sub.V2 in FIG. 3. In the 
case where the output voltage V.sub.0 is fed back to the differential 
amplifier in order to improve linearity, phase compensation can be 
achieved by suitably adjusting the gate-source capacitance C.sub.P of the 
MOS transistor Q.sub.7 in such a manner as to shift the cut-off frequency 
f.sub.1 from the cut-off frequency f.sub.2. 
Now, an example of a CCD delay line using a charge-coupled device will be 
described. The CCD delay line according to the present invention is an 
improvement of the CCD delay line which the present inventor has described 
in Japanese Patent Application No. 103100/1990. 
First, the structure of the delay line will be described with reference to 
FIG. 4. 
As shown in FIG. 4, an N.sup.- impurity ion implantation layer 2 is formed 
in the surface of a P-type semiconductor substrate 1, and charge 
transferring gate electrodes are formed thereon through a gate oxide film. 
Thus, a buried channel CCD (BCCD), which is the body of the delay line, is 
formed. In FIG. 4, gate electrodes 3, 4, 5, 6, 7 and 8 are shown as part 
of the output section of the BCCD, and drive signals .phi..sub.1, 
.phi..sub.2 and .phi..sub.2A are applied to the gate electrodes to 
transfer signal charges. The drive signals .phi..sub.1 and .phi..sub.2 are 
transfer clock signals in a two-phase drive system, and the drive signal 
.phi..sub.2A is a clock signal which becomes positive or negative in 
synchronization with the signal .phi..sub.2. 
A gate electrode 9 is formed adjacent the gate electrode 8. A predetermined 
DC voltage OG is applied to the gate electrode 9. In this example, the 
predetermined DC voltage OG is zero (0) volts. In addition, an N.sup.+ 
impurity layer 10 is buried in the surface of the P-type semiconductor 
substrate 1 adjacent the gate-electrode 9. The impurity layer 10 is 
connected to an output circuit. 
The output circuit of the CCD delay line includes differential amplifiers 
11 and 12. The differential amplifier 11 has an inverting input terminal 
connected to the N.sup.+ impurity layer 10, and a non-inverting input 
terminal receiving a predetermined bias voltage V.sub.B (e.g., 3 volts). A 
parallel circuit of a capacitive element 13 and an analog switch 14 is 
connected between the inverting input terminal and the output terminal of 
the differential amplifier 11. Thus, the differential amplifier 11 forms a 
switched-capacitance integrator. 
In the differential amplifier 12, the non-inverting input terminal is 
connected to the output terminal of the differential amplifier 11, and the 
inverting input terminal is connected to an output terminal of the output 
circuit. Thus, the differential amplifier 12 serves as a buffer amplifier. 
The output terminal of the differential amplifier 11 is connected through 
an analog switch 16 to the non-inverting input terminal of the 
differential amplifier 12. The non-inverting input to the differential 
amplifier 12 is grounded through a capacitive element 17. The analog 
switch 16 and the capacitive element 17 form a sample and hold circuit. 
The output circuit is shown in more detail in FIG. 5. As shown in FIG. 5, 
the differential amplifier 11, which forms the switched capacitor 
integrator, includes MOS transistors Q.sub.14 through Q.sub.22. The analog 
switch 16 includes MOS transistors Q.sub.23 and Q.sub.24, and an inverter 
18. The buffer amplifier 12 includes MOS transistors Q.sub.25 through 
Q.sub.33. 
The differential amplifier 11, which forms the switched-capacitance 
integrator, is constructed as follows. In the differential amplifier 11, 
the N-channel MOS transistors Q.sub.14 and Q.sub.15 form a differential 
pair which is connected to the N-channel MOS transistor Q.sub.16 and to 
the P-channel MOS transistors Q.sub.17 and Q.sub.18 serving as active 
loads. The N-channel MOS transistor Q.sub.16 serves as a constant current 
source when controlled by a fixed bias voltage V.sub.BIAS. The drain 
electrode of the MOS transistor Q.sub.15 is connected to a CCD amplifier 
circuit (corresponding to the amplifier circuit AMP in FIG. 1) including 
the MOS transistors Q.sub.19 through Q.sub.22. 
In the CCD amplifier circuit within the differential amplifier 11, the 
transistor Q.sub.19 is a driving N-channel MOS transistor, the transistor 
Q.sub.20 is a P-channel MOS transistor serving as an active load, and the 
transistors Q.sub.21 and Q.sub.22 are N-channel MOS transistors forming a 
level-shifting circuit. The N-channel MOS transistor Q.sub.22 forms a 
constant current source when controlled by a fixed bias voltage V.sub.BIAS 
(e.g., I.sub.1 in FIG. 1). A capacitive element C.sub.P1 is connected 
between the gate electrode and the source electrode of the driving MOS 
transistor Q.sub.19 for the purpose of phase compensation. 
A parallel circuit of a capacitive element 13 and a P-channel MOS 
transistor 14 is connected between the gate electrode of the MOS 
transistor Q.sub.14 and the drain electrode of the driving MOS transistor 
Q.sub.19. The fixed bias voltage V.sub.B is applied to the gate electrode 
of the MOS transistor Q.sub.15. The gate electrode of the MOS transistor 
Q.sub.14 is connected to the floating diffusion region 10. 
The analog switch 16 forming the sample-and-hold circuit includes a 
P-channel MOS transistor Q.sub.23 which is rendered conductive when the 
sample-and-hold control signal SH is at the "L" level, a P-channel MOS 
transistor Q.sub.24 serving as a gate electrode capacitor and connected to 
the source electrode of the MOS transistor Q.sub.23, and an inverter 18 
for inverting the sample-and-hold control signal SH and supplying the 
inverted signal to the gate electrode of the MOS transistor Q.sub.24. A 
capacitive element 17 is connected to the source and drain electrodes of 
the MOS transistor Q.sub.24. Thus, the sample-and-hold circuit is formed. 
The differential amplifier 12, which forms the buffer amplifier, is 
constructed as follows. The N-channel MOS transistors Q.sub.25 and 
Q.sub.26 form a differential pair. The differential pair is connected to 
the N-channel MOS transistor Q.sub.27, which serves as a constant current 
source when controlled by the fixed bias voltage V.sub.BIAS, to the 
P-channel MOS transistors Q.sub.28 and Q.sub.29 serving as active loads. A 
drain electrode of the MOS transistor Q.sub.25 is connected to the CCD 
amplifier circuit (corresponding to the amplifier AMP in FIG. 1). 
In the CCD amplifier circuit within the differential amplifier 12, the 
transistor Q.sub.30 is a driving N-channel MOS transistor, the transistor 
Q.sub.31 is a P-channel MOS transistor serving as an active load, and the 
transistors Q.sub.32 and Q.sub.33 are N-channel MOS transistors forming a 
level-shifting circuit. The MOS transistor Q.sub.33 forms the constant 
current source when controlled by the fixed bias voltage V.sub.BIAS (e.g., 
I.sub.1 in FIG. 1). A capacitive element C.sub.P2 is connected between a 
gate electrode and a source electrode of the driving MOS transistor 
Q.sub.30 for the purpose of phase compensation. 
The output signal of the sample-and-hold circuit is applied to a gate 
electrode of the MOS transistor Q.sub.25, and the gate electrode of the 
MOS transistor Q.sub.26 is connected directly to the output terminal of 
the differential amplifier 12. Thus, the differential amplifier serves as 
a negative feedback buffer amplifier. 
The operation of the CCD delay line thus constructed will be described with 
reference FIGS. 4B, 4C and 6. FIGS. 4B and 4C show potential profiles with 
respect to the gate electrodes. 
In order to read signal charges transferred having a predetermined period 
in synchronization with the transfer clock signals .phi..sub.1 and 
.phi..sub.2, at the beginning of each period .tau. unnecessary charge is 
removed from the capacitive element 13 connected to the differential 
amplifier 11, and the potential of the floating diffusion region 10 is 
initialized. For instance, at the time instant T1 in a period .tau., the 
reset signal RST is raised to the "H" level to render the analog switch 14 
conductive thereby to set the voltages at the inverting input terminal and 
the non-inverting input terminals of the differential amplifier 11 to 
V.sub.B (e.g., 3 volts). As a result, 3 volts is applied to the floating 
diffusion region 10. Next, the reset signal RST is set to the "H" level to 
render the analog switch 14 non-conductive, whereby the potential under 
the floating diffusion region 10 is initialized to a level corresponding 
to 3 volts. At the time instant T1 of the initialization, as shown in FIG. 
4B, the signal charge q.sub.1 closest to the output side is transferred to 
the region under the gate electrode 8, and the next signal charge q.sub.2 
is transferred to the region under the gate electrode 4. 
Next, at the time instant T2 the signal .phi..sub.1 is raised to the "H" 
level, the signal .phi..sub.2 is set to the "L" level, and the signal 
.phi..sub.2A is set to the "L" level in the negative range, so that the 
regions under the gate electrodes 7 and 8 are reduced in potential as 
shown in FIG. 4C. As a result, the signal charge q.sub.1 is transferred 
over the potential barrier under the gate electrode 9 to the floating 
diffusion region 10, and the signal charge q.sub.2 is transferred to the 
region under the gate electrode 6. Hence, the signal charge q.sub.1 thus 
transferred charges the capacitive element 13, so that the output signal 
SC.sub.1 of the differential amplifier 11 changes as shown in FIG. 6. 
Next, at the time instant T3, the sample and hold signal SH is set to the 
"L" level. Hence, the output signal SC.sub.1 of the differential amplifier 
11 is held by the capacitive element 17, and an output signal S.sub.0 
proportional to the signal thus held is provided at the output terminal 15 
by the differential amplifier 12. 
At the time instant T4, the same operations are carried out as at the time 
instant T1, the next signal charge transferred next is read, and similarly 
the process for the period .tau. is performed. Thus, signal charges which 
are successively transferred are read out. 
As described above, in the CCD delay line, the output stages of the 
switched capacitor integrator and the buffer amplifier in the output 
circuit are implemented with the CCD amplifier circuit according to the 
invention. Hence, the output circuit is low in output impedance and wide 
in bandwidth thus being suitable for processing video signals. 
As described above, with the CCD amplifier circuit of the invention, even 
when the output signal increases in voltage amplitude, neither is the 
mutual conductance of the active load MOS transistor decreased nor is the 
pinch-off voltage decreased because a forward bias voltage is always 
applied between the gate and source electrode of the active load MOS 
transistor. Furthermore, the gate capacitance of the active load MOS 
transistor is charged by the control signal of low output impedance 
provided by a control circuit, and thus the active load MOS transistor 
does not become a capacitive load for the driving MOS transistor. Hence, 
the waveform of the output signal does not collapse due to the effect of 
the pinch-off voltage because the dynamic range is increased. In addition, 
the output impedance is not increased, and the high-frequency cut-off 
frequency can be increased. Hence, the resultant CCD amplifier circuit has 
a wide bandwidth. 
Furthermore, a CCD delay line capable of processing video signals over a 
wide frequency range can be formed by applying the inventive CCD amplifier 
to its output circuit. 
While the invention has been described in connection with the preferred 
embodiments of the invention, it will be obvious to those skilled in the 
art that various changes and modifications may be made therein without 
departing from the invention, and it is intended, therefore, to cover in 
the appended claims all such changes and modifications which fall within 
the true spirit and scope of the invention.