A method, apparatus, and computer program product in a data processing system for testing differential clock or oscillator signals. A method is comprised of the following steps: A first single-ended receiver is connected to a positive leg of a differential pair, and a second single-ended receiver is connected to a negative leg of the differential pair. An output of the first single-ended receiver is inverted and delayed before being input into a first RS Flip-Flop. An output of the second single-ended receiver is delayed before being input into a second RS Flip-Flop. An output of a differential receiver is inverted and input into the first and second RS Flip Flops as reset signals. Then a Wire OK signal is output indicating the condition of the legs of the differential pair.

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates generally to an improved data processing system and, in particular, to a method, apparatus, and computer program product for enhancing performance in a data processing system. Still more particularly, the present invention provides a method, apparatus, and computer program product for testing differential clock or oscillator signals in a data processing system.

2. Description of Related Art

A microprocessor is a silicon chip that contains a central processing unit (CPU) which controls all the other parts of a digital device. Designs vary widely but, in general, the CPU consists of a control unit, an arithmetic and logic unit (ALU) and memory (registers, cache, RAM and ROM) as well as various temporary buffers and other logic. The control unit fetches instructions from memory and decodes them to produce signals which control the other part of the computer. This may cause the control unit to transfer data between memory and ALU or to activate peripherals to perform input or output. A parallel computer has several CPUs which may share other resources such as memory and peripherals. In addition to bandwidth (the number of bits processed in a single instruction) and clock speed (how many instructions per second the microprocessor can execute), microprocessors are classified as being either RISC (reduced instruction set computer) or CISC (complex instruction set computer).

An oscillator clock is a circuit within a microprocessor that creates a series of pulses that pace the microprocessor's electronic system. The oscillator clock synchronizes, paces and coordinates the operations of the microprocessor's circuit. For differential signals, such as those used for oscillator distribution between oscillator generator circuits and user chips, to detect if one leg of a differential pair is broken is always a problem. Due to the nature of this differential signal, the function will still be partially available even with one leg broken.

One currently available technique to detect a broken leg of a differential pair is to add two single-ended receivers to the main differential receiver. One of these additional single-ended receivers is connected to the positive leg of the differential pair, and the other single-ended receiver is connected to the negative leg of the differential pair. The three output signals of the three receivers can then be observed by standard missing pulse detectors. The problem with this scheme is that standard missing pulse detectors need several cycles to detect a missing pulse, and in some situations the single-ended receiver is generating inverted signals, which cannot be detected by standard missing pulse generators.

Therefore, it would be advantageous to have an improved method, apparatus, and computer program product for detecting a broken leg of a differential pair. The wiretest system of the present invention tests differential clock or oscillator signals, and detects failures due to a broken leg within one cycle.

SUMMARY OF THE INVENTION

The present invention provides a method, apparatus, and computer program product in a data processing system for testing differential clock or oscillator signals. A method according to the invention is comprised of the following steps: A first single-ended receiver is connected to a positive leg of a differential pair, and a second single-ended receiver is connected to a negative leg of the differential pair. An output of the first single-ended receiver is inverted and delayed before being input into a first RS Flip-Flop. An output of the second single-ended receiver is delayed before being input into a second RS Flip-Flop. An output of a differential receiver is inverted and input into the first and second RS Flip Flops as reset signals. Then a Wire OK signal is output indicating the condition of the legs of the differential pair.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 1is a block diagram of a processor system for processing information with which the present invention may be implemented in accordance with a preferred embodiment of the present invention. The processor is designated by reference number110, and in the preferred embodiment, processor110is a single integrated circuit superscalar microprocessor. Accordingly, as discussed further herein below, processor110includes various units, registers, buffers, memories, and other sections, all of which are formed by integrated circuitry. Also, in the preferred embodiment, processor110operates according to reduced instruction set computer (“RISC”) techniques. As shown inFIG. 1, a system bus111is connected to a bus interface unit (“BIU”)112of processor110. BIU112controls the transfer of information between processor110and system bus111.

BIU112is connected to an instruction cache114and to a data cache116of processor110. Instruction cache114outputs instructions to a sequencer unit118. In response to such instructions from instruction cache114, sequencer unit118selectively outputs instructions to other execution circuitry of processor110.

In addition to sequencer unit118, in the preferred embodiment, the execution circuitry of processor110includes multiple execution units, namely a branch unit120, a fixed-point unit A (“FXUA”)122, a fixed-point unit B (“FXUB”)124, a complex fixed-point unit (“CFXU”)126, a load/store unit (“LSU”)128, and a floating-point unit (“FPU”)130. FXUA122, FXUB124, CFXU126, and LSU128input their source operand information from general-purpose architectural registers (“GPRs”)132and fixed-point rename buffers134. Moreover, FXUA122and FXUB124input a “carry bit” from a carry bit (“CA”) register142. FXUA122, FXUB124, CFXU126, and LSU128output results (destination operand information) of their operations for storage at selected entries in fixed-point rename buffers134. Also, CFXU126inputs and outputs source operand information and destination operand information to and from special-purpose register processing unit (“SPR unit”)140.

FPU130inputs its source operand information from floating-point architectural registers (“FPRs”)136and floating-point rename buffers138. FPU130outputs results (destination operand information) of its operation for storage at selected entries in floating-point rename buffers138.

In response to a Load instruction, LSU128inputs information from data cache116and copies such information to selected ones of rename buffers134and138. If such information is not stored in data cache116, then data cache116inputs (through BIU112and system bus111) such information from a system memory139connected to system bus111. Moreover, data cache116is able to output (through BIU112and system bus111) information from data cache116to system memory139connected to system bus111. In response to a Store instruction, LSU128inputs information from a selected one of GPRs132and FPRs136and copies such information to data cache116.

Sequencer unit118inputs and outputs information to and from GPRs132and FPRs136. From sequencer unit118, branch unit120inputs instructions and signals indicating a present state of processor110. In response to such instructions and signals, branch unit120outputs (to sequencer unit118) signals indicating suitable memory addresses storing a sequence of instructions for execution by processor110. In response to such signals from branch unit120, sequencer unit118inputs the indicated sequence of instructions from instruction cache114. If one or more of the sequence of instructions is not stored in instruction cache114, then instruction cache114inputs (through BIU112and system bus111) such instructions from system memory139connected to system bus111.

In response to the instructions input from instruction cache114, sequencer unit118selectively dispatches the instructions to selected ones of execution units120,122,124,126,128, and130. Each execution unit executes one or more instructions of a particular class of instructions. For example, FXUA122and FXUB124execute a first class of fixed-point mathematical operations on source operands, such as addition, subtraction, ANDing, ORing and XORing. CFXU126executes a second class of fixed-point operations on source operands, such as fixed-point multiplication and division. FPU130executes floating-point operations on source operands, such as floating-point multiplication and division.

As information is stored at a selected one of rename buffers134, such information is associated with a storage location (e.g., one of GPRs132or CA register142) as specified by the instruction for which the selected rename buffer is allocated. Information stored at a selected one of rename buffers134is copied to its associated one of GPRs132(or CA register142) in response to signals from sequencer unit118. Sequencer unit118directs such copying of information stored at a selected one of rename buffers134in response to “completing” the instruction that generated the information. Such copying is called “writeback.”

As information is stored at a selected one of rename buffers138, such information is associated with one of FPRs136. Information stored at a selected one of rename buffers138is copied to its associated one of FPRs136in response to signals from sequencer unit118. Sequencer unit118directs such copying of information stored at a selected one of rename buffers138in response to “completing” the instruction that generated the information.

Processor110achieves high performance by processing multiple instructions simultaneously at various ones of execution units120,122,124,126,128, and130. Accordingly, each instruction is processed as a sequence of stages, each being executable in parallel with stages of other instructions. Such a technique is called “pipelining.” In a significant aspect of the illustrative embodiment, an instruction is normally processed as six stages, namely fetch, decode, dispatch, execute, completion, and writeback.

In the fetch stage, sequencer unit118selectively inputs (from instruction cache114) one or more instructions from one or more memory addresses storing the sequence of instructions discussed further hereinabove in connection with branch unit120, and sequencer unit118.

In the decode stage, sequencer unit118decodes up to four fetched instructions.

In the dispatch stage, sequencer unit118selectively dispatches up to four decoded instructions to selected (in response to the decoding in the decode stage) ones of execution units120,122,124,126,128, and130after reserving rename buffer entries for the dispatched instructions' results (destination operand information). In the dispatch stage, operand information is supplied to the selected execution units for dispatched instructions. Processor110dispatches instructions in order of their programmed sequence.

In the execute stage, execution units execute their dispatched instructions and output results (destination operand information) of their operations for storage at selected entries in rename buffers134and rename buffers138as discussed further hereinabove. In this manner, processor110is able to execute instructions out-of-order relative to their programmed sequence.

In the completion stage, sequencer unit118indicates an instruction is “complete.” Processor110“completes” instructions in order of their programmed sequence.

In the writeback stage, sequencer118directs the copying of information from rename buffers134and138to GPRs132and FPRs136, respectively. Sequencer unit118directs such copying of information stored at a selected rename buffer. Likewise, in the writeback stage of a particular instruction, processor110updates its architectural states in response to the particular instruction. Processor110processes the respective “writeback” stages of instructions in order of their programmed sequence. Processor110advantageously merges an instruction's completion stage and writeback stage in specified situations.

In the illustrative embodiment, each instruction requires one machine cycle to complete each of the stages of instruction processing. Nevertheless, some instructions (e.g., complex fixed-point instructions executed by CFXU126) may require more than one cycle. Accordingly, a variable delay may occur between a particular instruction's execution and completion stages in response to the variation in time required for completion of preceding instructions.

A completion buffer148is provided within sequencer118to track the completion of the multiple instructions which are being executed within the execution units. Upon an indication that an instruction or a group of instructions have been completed successfully, in an application specified sequential order, completion buffer148may be utilized to initiate the transfer of the results of those completed instructions to the associated general-purpose registers.

The wiretest system of the present invention conducts an on-going wire test of a microprocessor's differential oscillator or clock distribution signal, which coordinates the functioning of microprocessor components as shown inFIG. 1, and detects failures due to a broken leg within one cycle. The wiretest system not only checks if the signals from the differential output and the single-ended receivers connected to the legs of the differential pair are oscillating, but also checks for the sequence of these three signals.

FIG. 2shows a diagram of wiretest circuit250in accordance with a preferred embodiment of the present invention connected to combined differential receiver200, functioning as a wiretest for differential signals. One single-ended receiver202is connected to positive leg204of the differential pair, and another single-ended receiver206is connected to negative leg208of the differential pair. The input signals into the wiretest circuit of the present invention are output of the differential receiver210, output of the single-ended receiver connected to the positive input to the differential receiver212, and output of the single-ended receiver connected to the negative input to the differential receiver214. Output of the single-ended receiver connected to the positive input to the differential receiver212is inverted by inverter216and delayed by delay mechanism218before the output is input220into RS Flip-Flop1222. Output of the single-ended receiver connected to the negative input to the differential receiver214is delayed by delay mechanism224before the output is input226into RS Flip-Flop2228. Output of the differential receiver210is inverted by inverter230and input into the first and second RS Flip Flops as reset signals232,234. Outputs of Flip-Flops236,238are input into AND gate240, and output of the AND gate242is fed through filter244to become Wire OK signal246. Optionally, Wire OK signal246can be input into AND gate248along with output of the differential receiver210. Wire OK signal246can also be used to delegate the output from the differential signal elsewhere, or used just as an error indicator.

FIG. 3shows, in accordance with a preferred embodiment of the present invention, a wiretest system's timing diagram for differential signals in a good case, when there is no broken leg for either the negative or positive input to the combined differential receiver. The timing diagram displays the signals for positive input to the combined differential receiver302, negative input to the combined differential receiver304, output from the combined differential receiver306, delayed output from the single-ended receiver connected to the positive leg of the differential pair308, delayed output from the single-ended receiver connected to the negative leg of the differential pair310, output of RS Flip-Flop1312, output of RS Flip-Flop2314, and Wire OK signal316.

Negative edge318(because the signal is actually inverted) of output from the combined differential receiver306resets320output of RS Flip-Flop1312and also resets322output of RS Flip-Flop2314. Positive edge324of delayed output from the single-ended receiver connected to the negative leg of the differential pair310sets326output of RS Flip-Flop2314. Negative edge328(because the signal is actually inverted) of the delayed output from the single-ended receiver connected to the positive leg of the differential pair308sets330output of RS Flip-Flop1312. Output of RS Flip-Flop1312and output of RS Flip-Flop2314are only reset for the delay time specified for delayed output from the single-ended receiver connected to the positive leg of the differential pair308and delayed output from the single-ended receiver connected to the negative leg of the differential pair310. Wire OK signal316stays set because the short delay time for the delayed outputs from the single-ended receivers is less than the filter delay time specified by the filter delay following the AND gate for the output of RS Flip-Flops. In contrast, Wire OK316signal does not stay set in a bad case.

FIG. 4shows, in accordance with a preferred embodiment of the present invention, a wiretest system's timing diagram for differential signals in a bad case, when there is a broken leg at the receive side for the negative input to the combined differential receiver. The timing diagram displays the signals for positive input to the combined differential receiver402, negative input to the combined differential receiver404, output from the combined differential receiver406, delayed output from the single-ended receiver connected to the positive leg of the differential pair408, delayed output from the single-ended receiver connected to the negative leg of the differential pair410, output of RS Flip-Flop1412, output of RS Flip-Flop2414, and Wire OK signal416.

The negative edge418(the signal is actually inverted) of output from the combined differential receiver406resets420output of RS Flip-Flop1412and also resets422output of RS Flip-Flop2414. Negative edge424(the signal is actually inverted) of delayed output from the single-ended receiver connected to the positive leg of the differential pair408sets426output of RS Flip-Flop1412. But after the negative wire is broken at the receive side, delayed output from the single-ended receiver connected to the negative leg of the differential pair410no longer has positive edge428to set430output of RS Flip-Flop2414. Sometimes when a wire is broken at the sending side of a transmission line, there is a signal with the same phase as the unbroken leg, but that is not the case in this example. Therefore, although output of RS Flip-Flop1412is only reset for the delay time specified for delayed output from the single-ended receiver connected to the positive leg of the differential pair408, output of RS Flip-Flop2414stays reset. Wire OK signal416resets432because once the filter delay time434expires as specified by the filter delay following the AND gate for the output of RS Flip-Flops, the AND gate combines a set and a reset signal from the RS Flip-Flops to produce a reset signal, and the signal stays reset until the negative wire is no longer broken.

FIG. 5shows, in accordance with a preferred embodiment of the present invention, a wiretest system's timing diagram for differential signals in a bad case, when there is a broken leg at the receive side for the positive input to the combined differential receiver. The timing diagram displays the signals for positive input to the combined differential receiver502, negative input to the combined differential receiver504, output from the combined differential receiver506, delayed output from the single-ended receiver connected to the positive leg of the differential pair508, delayed output from the single-ended receiver connected to the negative leg of the differential pair510, output of RS Flip-Flop1512, output of RS Flip-Flop2514, and Wire OK signal516.

The negative edge518(the signal is actually inverted) of output from the combined differential receiver506resets520output of RS Flip-Flop1512and also resets522output of RS Flip-Flop2514. The positive edge524of delayed output from the single-ended receiver connected to the negative leg of the differential pair510sets526output of RS Flip-Flop2514. But after the positive wire is broken at the receive side, delayed output from the single-ended receiver connected to the positive leg of the differential pair508no longer has negative edge528(the signal is actually inverted) to set530output of RS Flip-Flop1512. Sometimes when a wire is broken at the sending side of a transmission line, there is a signal with the same phase as the unbroken leg, but that is not the case in this example. Therefore, although output of RS Flip-Flop2514is only reset for the delay time specified for delayed output from the single-ended receiver connected to the negative leg of the differential pair510, output of RS Flip-Flop1512stays reset. Wire OK signal516resets532because once the filter delay time534expires as specified by the filter delay following the AND gate for the output of RS Flip-Flops, the AND gate combines a set and a reset signal from the RS Flip-Flops to produce a reset signal, and the signal stays reset until the positive wire is no longer broken.

FIG. 6is a diagram of a typical oscillator distribution scheme with a thevenin termination, with outputs to a wiretest circuit in accordance with a preferred embodiment of the present invention. The diagram displays differential driver602at the sending side, positive leg of the oscillator distribution wire604, negative leg of the oscillator distribution wire606, resistor608for positive leg of the oscillator distribution wire604at the receiving side, resistor610for negative leg of the oscillator distribution wire606at the receiving side, combined differential receiver612, positive input to the combined differential receiver614, negative input to the combined differential receiver616, output from the combined differential receiver618, output from the single-ended receiver connected to the positive leg of the differential pair620, and output from the single-ended receiver connected to the negative leg of the differential pair622.

In a Thevenin termination, input614and input616to the combined differential receiver612are terminated at the end of transmission line604and transmission line606, respectively, by resistor608and resistor610, respectively, to VDD/2. Usually VDD/2 is a voltage that is exactly equal to or very close to the threshold voltage of the combined differential receiver612. Therefore, this Thevenin termination scheme is very sensitive to noise, such as in the case of a broken leg. However, a problem exists for Thevenin terminations. Because transmission line604and transmission line606are quite long and have a capacitive coupling from one leg of the differential pair to the other, in case of a broken leg at the sending side of the transmission lines, the signals at the receiving side may be in phase for a Thevenin termination.

FIG. 7shows, in accordance with a preferred embodiment of the present invention, a wiretest system's timing diagram for differential signals with a thevenin termination in a bad case, when there is a broken leg at the sending side for the negative input to the combined differential receiver. The timing diagram displays the signals for positive input to the combined differential receiver702, negative input to the combined differential receiver704, output from the combined differential receiver706, output from the single-ended receiver connected to the positive leg of the differential pair708, output from the single-ended receiver connected to the negative leg of the differential pair710, Wire OK signal712, and output from the combined differential receiver AND Wire OK signal714.

When there is a broken leg at the sending side for the negative input to the combined differential receiver, negative input to the combined differential receiver704can have a signal that is inverted to the regular signal with reduced amplitude716, as illustrated in this example, but output from the combined differential receiver706continues to toggle normally. Output from the single-ended receiver connected to the positive leg of the differential pair708also continues to toggle normally.

Output from the single-ended receiver connected to the negative leg of the differential pair710first drops718, then toggles with the changed phase720. The negative edge (the signal is actually inverted) of output from the combined differential receiver706resets the output of RS Flip-Flop1and also resets the output of RS Flip-Flop2. The negative edge (the signal is actually inverted) of output from the single-ended receiver connected to the positive leg of the differential pair708sets the output of RS Flip-Flop1. But shortly after the negative wire is broken, output from the single-ended receiver connected to the negative leg of the differential pair710no longer has the positive edge to set the output of RS Flip-Flop2.

Because the transmission line is quite long and has a capacitive coupling from one leg of the differential pair to the other, in case of a broken leg at the sending side of the transmission line, the signals at the receiving side may be in phase, as illustrated in this example. After output from the single-ended receiver connected to the negative leg of the differential pair710drops718, then the output toggles with the changed phase720.

Because output from the single-ended receiver connected to the negative leg of the differential pair710becomes in phase with output from the single-ended receiver connected to the positive leg of the differential pair708, output from the single-ended receiver connected to the negative leg of the differential pair710now has a positive edge to set output of RS Flip-Flop2, but only after the filter delay time expires, as specified by the filter delay following the AND gate for the output of RS Flip-Flops. The set occurring after the filter delay time has expired results in the output of RS Flip-Flop2staying reset for too long. Wire OK signal712resets722because once the filter delay time expires as specified by the filter delay following the AND gate for the output of RS Flip-Flops, the AND gate combines a set and a reset signal from the RS Flip-Flops to produce a reset signal. Wire OK signal712stays reset until the negative wire is no longer broken. Because Wire OK signal712resets722, output from the combined differential receiver AND Wire OK signal714also resets.

FIG. 8shows, in accordance with a preferred embodiment of the present invention, a wiretest system's timing diagram for differential signals with a thevenin termination in a bad case, when there is a broken leg at the sending side for the positive input to the combined differential receiver. The timing diagram displays the signals for positive input to the combined differential receiver802, negative input to the combined differential receiver804, output from the combined differential receiver806, output from the single-ended receiver connected to the positive leg of the differential pair808, output from the single-ended receiver connected to the negative leg of the differential pair810, Wire OK signal812, output from the combined differential receiver AND Wire OK signal814, output from Pulse Generation1816, output from Pulse Generation2818, output from Pulse Generation3820, output of RS Flip-Flop1822, and output of RS Flip-Flop2824.

When there is a broken leg at the sending side for the positive input to the combined differential receiver, positive input to the combined differential receiver802can have a signal that is inverted to the regular signal with reduced amplitude826, as illustrated in this example, but output from the combined differential receiver806continues to toggle normally. Output from the single-ended receiver connected to the negative leg of the differential pair810also continues to toggle normally.

Output from the single-ended receiver connected to the positive leg of the differential pair808first drops828, then toggles with the changed phase830. The negative edge (the signal is actually inverted) of output from the combined differential receiver806resets the output of RS Flip-Flop1and also resets the output of RS Flip-Flop2. The positive edge of output from the single-ended receiver connected to the negative leg of the differential pair810sets the output of RS Flip-Flop2. But shortly after the positive wire is broken, output from the single-ended receiver connected to the positive leg of the differential pair808no longer has the negative edge (the signal is actually inverted) to set the output of RS Flip-Flop1.

Because the transmission line is quite long and has a capacitive coupling from one leg of the differential pair to the other, in case of a broken leg at the sending side of the transmission line, the signals at the receiving side may be in phase, as illustrated in this example. After output from the single-ended receiver connected to the positive leg of the differential pair808drops828, then the output toggles with the changed phase830.

Because output from the single-ended receiver connected to the positive leg of the differential pair808becomes in phase with output from the single-ended receiver connected to the positive leg of the differential pair810, output from the single-ended receiver connected to the negative leg of the differential pair808now has a positive edge to set output of RS Flip-Flop2, but only after the filter delay time expires, as specified by the filter delay following the AND gate for the output of RS Flip-Flops. The set occurring after the filter delay time has expired results in the output of RS Flip-Flop2staying reset for too long. Wire OK signal812resets832because once the filter delay time expires as specified by the filter delay following the AND gate for the output of RS Flip-Flops, the AND gate combines a set and a reset signal from the RS Flip-Flops to produce a reset signal. Wire OK signal812stays reset until the positive wire is no longer broken. Because Wire OK signal812resets832, output from the combined differential receiver AND Wire OK signal814also resets.

FIG. 9shows a schematic diagram of a wiretest system in accordance with a preferred embodiment of the present invention. The schematic diagram displays output from the combined differential receiver902, output from the single-ended receiver connected to the positive leg of the differential pair904, output from the single-ended receiver connected to the negative leg of the differential pair906, output of RS Flip-Flop1908, output of RS Flip-Flop2910, Wire OK signal912, output from the combined differential receiver AND Wire OK signal914, output from Pulse Generation1916, output from Pulse Generation2918, and output from Pulse Generation3920.

The wiretest system of the present invention tests differential oscillator or clock distribution signals, and detects failures due to a broken leg within one cycle, whether the broken leg results in the loss of a signal or whether the broken leg, as in the case of a thevenin termination scheme, results in a reduced-amplitude signal that is in-phase with the unbroken leg.