Analogue current switch bipolar injection technology

An analogue current switch comprising a cascade of n identical switching elements, each element comprising an I.sup.2 L integrated current-injection logic gate having one or more collector outputs. The signal input (e.sub.1) is the emitter of the PNP injection transistor (T.sub.1), the switching-signal input (e.sub.2) is the base of the NPN switching transistor (T.sub.2), and the signal output (s) is the junction point of the emitter of T.sub.2 and the base of T.sub.1.

This invention relates to an analogue current switch formed by means of 
switching elements comprising integrated current-injection logic gates of 
the I.sup.2 L type. These switching elements each comprise a signal input 
at the emitter of the injection transistor and a switching-signal input at 
the base of the switching transistor. The last-mentioned transistor 
comprises m collectors one of which is coupled to the base of said 
switching transistor and the other m-1 of which are connected to 
respective ones of the m-1 current inputs. The switching signal either 
turns on said switching transistor so that the current supplied by a 
current source and injected at said signal input is reflected to said m-1 
current inputs, or turns off said transistor so that said injected current 
is diverted towards the switching-signal input. 
Such a device in which one of the switching signal commands causes the 
current to be reflected in the multiplicity of collectors of the I.sup.2 L 
gate is known from French Patent Specification No. 2,316,804 entitled 
"multilevel injection-logic semiconductor device". This Specification 
describes how special logic functions, e.g. those of the kind mentioned in 
the opening paragraph, can be obtained. This reflection function is 
specifically utilized for the formation of current mirrors (see Japanese 
Patent Specification No. 53 147 892). 
However, the prior-art logic devices do not perform the function of 
transferring the injected current. It is an object of the invention to 
fill this gap by forming an analogue switching element based on the 
I.sup.2 L gate, which element is simplified in comparison with the many 
known variants of transistor switches and has the advantage that it also 
transfers the injected current. This advantage is obtained in addition to 
those inherent in I.sup.2 L integrated circuits, namely their high 
integration density and their low dissipation, which enables their field 
of application to be extended to, for example, digital-to-analogue signal 
processing. 
According to the invention said switching element moreover comprises a 
signal output at the junction point of the base of said injection 
transistor and the emitter of said switching transistor such that in said 
turned-on state the injected current is transferred to said signal output 
with a specific transfer coefficient which is a function of the 
characteristics of said transistors of the I.sup.2 L gate. 
The calculation in the following description shows that said transfer 
coefficient becomes exactly equal to unity when the switching transistor 
comprises only one collector, which is particularly interesting for the 
use of the switching element thus formed in, for example, 
digital-to-analogue converters.

In FIG. 1 the integrated current-injection logic gate of the I.sup.2 L type 
comprises a PNP-transistor T.sub.1 and an NAN-transistor T.sub.2. The 
emitter and the collector of T.sub.1 are respectively constituted by two 
P-zones which are diffused simultaneously into an epitaxial N-zone to form 
a lateral transistor. The epitaxial zone constitutes the base of T.sub.1 
and the emitter of T.sub.2. The transistor T.sub.2 comprises m collectors 
formed by N.sup.+ diffusions in the P-type collector zone of T.sub.1, 
thereby forming the base zones of T.sub.2 in the parts underlying the said 
m N.sup.+ -diffusions. If any one of the said m collectors is coupled to 
the base of T.sub.2, the other m-1 collectors being connected to the 
current inputs C.sub.2, C.sub.3 . . . C.sub.m to which current injectors, 
not shown, are connected, the current I.sub.e from a current source S, 
which is connected to the signal input e.sub.1 at the emitter of T.sub.1, 
is reflected to said m collectors as currents I.sub.1, I.sub.2, . . . 
I.sub.m when a logic command applied to the switching signal input e.sub.2 
at the base of T.sub.2 turns on the last-mentioned transistor. Since the 
diffusions of the m collectors of T.sub.2 are situated very close to each 
other it may be assumed that the characteristics of the m corresponding 
partial transistors are identical if the areas of the m collectors are 
equal. As a result of this the currents I.sub.1, I.sub.2, . . . I.sub.m 
are equal. A calculation shows that they have the following value: 
##EQU1## 
in which .beta..sub.p is the current gain of T.sub.1 in common-emitter 
arrangement and .beta..sub.N the current gain of each partial transistor 
of T.sub.2 in common-emitter arrangement. If .beta..sub.p and .beta..sub.N 
are high the currents I.sub.1, I.sub.2, . . . I.sub.m will be 
substantially equal to the injected current I.sub.e, which is consequently 
reflected to each of the collectors of T.sub.2. 
In order to ensure that the injected current is also transferred when the 
switching signal turns on transistor T.sub.2 in accordance with the 
invention, the current switching element of FIG. 1 moreover comprises a 
signal output s formed by the junction point of the base of T.sub.1 and 
the emitter of T.sub.2. The current transferred to the signal output s is 
consequently the sum of the various emitter currents of T.sub.2, which 
correspond to its m collectors, and the base current of T.sub.1. Moreover, 
the collector current of T.sub.1 is the sum of the current I.sub.1 in the 
collector of T.sub.2 which is coupled to the base of this transistor and 
the base currents corresponding to the m-1 other collectors of T.sub.2, 
i.e. 
##EQU2## 
Combining these results yields the expression for the transferred current 
I.sub.s in its most general form: 
##EQU3## 
and .beta..sub.Ni =current gain of the transistor T.sub.2 corresponding to 
the collector i, the collector 1 being the collector which is coupled to 
the base of T.sub.2. 
If the ratio k.sub.i is written as K.sub.i =1+.epsilon..sub.i, the term 
.epsilon..sub.i represents the distribution of the emitter current 
corresponding to the collector i relative to the emitter current 
corresponding to the collector 1. The current I.sub.s is then written: 
##EQU4## 
The terms .epsilon..sub.i become substantially zero if the m collectors 
are identical and the transfer coefficient then has the value: 
##EQU5## 
When the switching signal turns off transistor T.sub.2 the part of the 
injected current constituted by the collector current .alpha..sub.p 
I.sub.e of T.sub.1 (.alpha..sub.p being the gain in common-base 
arrangement) is diverted to the switching signal input e.sub.2, whereas 
the other part of the injected current constituted by the base current 
(1-.alpha..sub.p)I.sub.e of T.sub.1 gives rise to an undesired transfer to 
the signal output s. 
FIG. 2 shows the circuit diagram of an analogue current switch in which the 
transistor T.sub.2 comprises only one collector which is coupled to its 
base. The expression for the transfer coefficient given in the foregoing 
shows that it is independent of current gain factors and is equal to 
unity. The current I.sub.e injected at the signal input e.sub.1 is 
therefore completely transferred to the signal output s, which may be used 
to advantage in digital-to-analogue signal processing. 
A method of reducing the undesirable transfer of the base current of 
T.sub.1 when T.sub.2 is not conductive is to provide a switch as 
represented schematically in FIG. 3. This switch comprises the cascade of 
n identical switching elements, for example as shown in the diagram of 
FIG. 2, each element i having its signal input e.sub.1i connected to the 
signal output s.sub.i-1 of the preceding element. The signal input is the 
signal input e.sub.11 of the first element, the signal output is the 
signal output s.sub.n of the n.sup.th element, and the n switching-signal 
inputs e.sub.21, e.sub.22, . . . e.sub.2n receive the same signal value 
simultaneously. Thus, when the n switching transistors are conductive, the 
injected current I.sub.e is completely transferred to the signal output, 
while in their non-conductive states the undesirable signal that is 
transferred has the value (1-.alpha..sub.p).sup.n I.sub.e. For a mean 
value .beta..sub.p =10 of the current gain of a lateral PNP transistor the 
undesirable transfer by a switching element is substantially equal to one 
tenth of the injected current, which when such a switching element is used 
in digital-to-analogue converters in the main invalidates analogue 
quantities which correspond to small weights of the digital signal. 
Cascading three switching elements reduces the undesirable signal by a 
factor of 120. It is to be noted that the n I.sup.2 L switching elements 
should be formed in islands which are isolated from each other. 
An example of an application is the synthesis of a sinusoidal function by 
means of a digital-to-analogue converter provided with the simplified 
version of the switching elements shown in FIG. 2. FIG. 4 shows the 
variation of the synthesized levels N of such a function with the angular 
variable .pi./16+K(.pi./8), K being a positive or negative integer. These 
synthesized levels are obtained as follows, in conformity with the Table I 
given hereinafter. The second column of this Table gives the values of sin 
(.pi./16+K(.pi./8) for K=0, 1, 2 and 3. The third column gives the 
calculated levels of the function obtained by multiplying the various 
values of sin (.pi./16+K(.pi./8) by the factor 33.3, and the fourth column 
of the Table gives the synthesized levels with the tenths rounded off to 
5. In this way, if -.pi./16(K=-1) is assumed to be an origin, the 
difference between the consecutive synthesized levels have the values of 
the integers 13, 12, 9 and 5 which can be reproduced by means of the 
function a+b.4+c.4+d.4, in which a, b and c may take the values 0 or 1 and 
d has the value 1. As a result of symmetry said differences in levels 
obtained in the third quadrant of the angular variable are the same for 
the three others, except for the sign. They are successively added to each 
other in the increasing ranges of the sinusoidal function and are 
subtracted from each other in the decreasing ranges in conformity with the 
sixteen sampling levels distributed over one period, in such a way that an 
approximation to the function is formed. 
TABLE I 
______________________________________ 
K 
##STR1## Calculated level 
Synthesized level 
______________________________________ 
0 0.195 6.5 6.5 
1 0.555 18.5 18.5 
2 0.831 27.9 27.5 
3 0.950 32.6 32.5 
______________________________________ 
FIG. 5 shows the variation as a function of time, indicated by a clock 
signal h, of the weighting coefficients a, b, c and d of the function 
defined in the foregoing. Each period of the clock signal corresponds to 
an angular variation of .pi./8 between two consecutive sampling levels. 
The signal f and its complement e are used for assigning the + sign or the 
- sign to the differences between the synthesized levels depending on 
whether the sinusoidal function is increasing or decreasing. 
The digital-to-analogue converter for carrying out the synthesis of the 
sinusoidal function shown in FIG. 4 is shown schematically in FIG. 6. A 
current source 15 energizes an arrangement of identical switching elements 
which are each in accordance with the simplified diagram shown in FIG. 2 
and bear the respective references 1 to 14. The signal inputs e.sub.1 of 
the switching elements are connected to the current source 15 in such a 
way that the current I supplied by said source is equally distributed 
among these signal inputs, which inputs each receive a current i.sub.e. 
The I.sup.2 L logic device 16, energized by the current source 17 and 
controlled by the clock signal h from the clock generator 18, supplies the 
signals a, b, c, e and f shown in FIG. 5. The switching element 1 has its 
switching signal input e.sub.2 connected to the logic device 16, which 
supplies the signal a to said element. The switching elements 2 to 13 
comprise three groups of four elements, each group having its 
switching-signal inputs e.sub.2 interconnected and the logic device 16 
applying the signals b and c to the first and second groups of inputs 
e.sub.2 respectively, a constant level d=1 being applied to the third 
group. The switch 14, which is not used but which is formed together with 
the preceding switch for technological reasons, is disabled by connecting 
its switching-signal input directly to ground. The signal outputs s of the 
switches 1 to 14 are also interconnected in order to receive the weighted 
sum of the currents .SIGMA.i.sub.e =a i.sub.e +b.4i.sub.e +c.4i.sub.e 
+d.4i.sub.e proportional to the function defined in the foregoing. Each 
combination of weighting coefficients a, b, c and d thus corresponds to 
the difference between two consecutive synthesized levels. This 
consecutively yields the values 13i.sub.e, 12i.sub.e, 9i.sub.e and 
5i.sub.e corresponding to an angular variation in steps of .pi./8 in the 
first quadrant of the variable where the sinusoidal function increases. 
When this function decreases in the second quadrant and in the third 
quadrant the same values are found for the differences between the 
synthesized levels but with a negative sign. They recur with a positive 
sign when the function increases again in the fourth quadrant. 
In order to transform .SIGMA.i.sub.e into .+-..SIGMA.i.sub.e the weighted 
sum of the currents is first passed through an intermediate circuit 19, 
which in the form shown is a current mirror comprising the transistor pair 
T.sub.3 -T'.sub.3 arranged as shown in the Figure. Subsequently the sum 
.SIGMA.i.sub.e is transferred from the collector of transistor T'.sub.3 to 
the interconnected emitters of the transistor pair T.sub.4 -T'.sub.4 
belonging to the circuit 20, which operates as follows. When the 
difference between two consecutive synthesized levels is positive the 
signal f is applied to the base of transistor T.sub.4 so that this 
transistor is turned on, and the signal e is applied to the base of 
transistor T'.sub.4 so that this transistor is turned off. As a result of 
the current mirror comprising the transistors T.sub.5 and T'.sub.5 the 
weighted sum of the currents .SIGMA.i.sub.e will flow as indicated by the 
solid arrows, through the transistors T'.sub.5, T.sub.5 and the transistor 
T.sub.6 of the pair T.sub.6 -T'.sub.6 whose emitters are interconnected 
and connected to the collector of T.sub.5. Similarly, when the difference 
between two consecutive synthesized levels is negative, the signal e turns 
on T'.sub.4, while the signal f turns off T.sub.4. As a result of the 
current mirror comprising the transistors T.sub.5 and T".sub.5, 
.SIGMA.i.sub.e flows, as is indicated by the dashed arrows, through the 
transistors T".sub.5, T.sub.5, T'.sub.6 and, as a result of the current 
mirror comprising the transistor pair T.sub.7 -T'.sub.7, through 
transistor T.sub.8. It is to be noted that the solid and dashed arrows 
have opposite directions at the terminals of the capacitor 30 arranged 
between ground and the point which is common to the collectors of the 
transistors T.sub.6 and T.sub.8, which provides the change of sign when 
the summation of the differences between consecutive synthesized levels 
##EQU6## 
available across said capacitor constitutes the analogue quantity, k being 
an integer between 1 and the number of sampling levels occurring over one 
period of the sinusoidal function.