Devices and methods of forming finFETs with self aligned fin formation

Devices and methods for forming semiconductor devices with FinFETs are provided. One method includes, for instance: obtaining an intermediate semiconductor device with a substrate and at least one shallow trench isolation region; depositing a hard mask layer over the intermediate semiconductor device; etching the hard mask layer to form at least one fin hard mask; and depositing at least one sacrificial gate structure over the at least one fin hard mask and at least a portion of the substrate. One intermediate semiconductor device includes, for instance: a substrate with at least one shallow trench isolation region; at least one fin hard mask over the substrate; at least one sacrificial gate structure over the at least one fin hard mask; at least one spacer disposed on the at least one sacrificial gate structure; and at least one pFET region and at least one nFET region grown into the substrate.

FIELD OF THE INVENTION

The present invention relates to semiconductor devices and methods of fabricating semiconductor devices, and more particularly, to FinFETs and methods of fabricating semiconductor devices with self aligned fin formation and a source and drain junction compatible with planar fabrication processes.

BACKGROUND OF THE INVENTION

Conventional planar MOSFET devices have been scaling down over the last few decades to provide higher integration density, higher operation speed and lower cost. However, the scaling down of MOSFET devices is restricted by the short channel effect which causes a high leakage current. In order to counteract the short channel effect, FinFETs have started being used due to the FinFETs stronger gate electrostatic control over the channel which can mitigate the short channel effect. However, the fabrication of FinFETs is more challenging than conventional planar device fabrication because of the high topology of the fins.

During conventional FinFET fabrication, the fin is formed first. Then the gate, spacer and junction/contact may be formed. As the gate, spacer and junction are formed they must be formed over and around the high topology fins. The high topology fins may cause challenges during deposition, lithography and etching to form the gate, spacer, and junction. Further, epitaxy must be grown on the three dimensional fin rather than the previous two dimensional planar substrate, this results in less epitaxy volume on the three dimensional fin than was previously on the planar substrate thereby limiting the stress enhancement. With a limited epitaxy volume on the three dimensional fins, the silicidation cannot consume too much epitaxy material. Currently, titanium silicide is being used because it consumes less epitaxy, however titanium silicide has poor contact properties.

Thus, the fabrication of FinFET devices can be problematic with existing fabrication techniques and improved FinFET fabrication techniques are needed for forming FinFET devices to improve the performance of the resultant semiconductors.

BRIEF SUMMARY

The shortcomings of the prior art are overcome and additional advantages are provided through the provision, in one aspect, a method includes, for instance: obtaining an intermediate semiconductor device with a substrate and at least one shallow trench isolation region; depositing a hard mask layer over the intermediate semiconductor device; etching the hard mask layer to form at least one fin hard mask; and depositing at least one sacrificial gate structure over the at least one fin hard mask and at least a portion of the substrate.

In another aspect, an intermediate semiconductor device which includes, for instance: a substrate with at least one shallow trench isolation region; at least one fin hard mask over the substrate; at least one sacrificial gate structure over the at least one fin hard mask; at least one spacer disposed on the at least one sacrificial gate structure; and at least one pFET region and at least one nFET region grown into the substrate

DETAILED DESCRIPTION

Aspects of the present invention and certain features, advantages, and details thereof, are explained more fully below with reference to the non-limiting embodiments illustrated in the accompanying drawings. Descriptions of well-known materials, fabrication tools, processing techniques, etc., are omitted so as to not unnecessarily obscure the invention in detail. It should be understood, however, that the detailed description and the specific examples, while indicating embodiments of the invention, are given by way of illustration only, and are not by way of limitation. Various substitutions, modifications, additions and/or arrangements within the spirit and/or scope of the underlying inventive concepts will be apparent to those skilled in the art from this disclosure. Note also that reference is made below to the drawings, which are not drawn to scale for ease of understanding, wherein the same reference numbers used throughout different figures designate the same or similar components.

Generally stated, disclosed herein are certain novel FinFET device formation methods and FinFET structures, which provide advantages over the above noted, existing FinFET device fabrication processes and structures. Advantageously, the FinFET device fabrication processes disclosed herein provide for a FinFET fabrication process with self aligned fin formation and easier fabrication of source and drain epi contacts. The FinFET fabrication process enables fin lines to be etched into a hard mask without etching into the substrate. Thus, during fabrication the device has a low topology and the spacer, source and drain junction or epitaxy contact may be formed without having to work around the fin. After the spacer and source and drain are formed, the fin may be etched into the substrate during the replacement metal gate (RMG) process allowing for the fin to be self aligned to the gate.

In one aspect, in one embodiment, as shown inFIG. 1, FinFET device formation in accordance with one or more aspects of the present invention may include, for instance: obtaining an intermediate semiconductor device100; depositing a hard mask layer over the intermediate semiconductor device110; etching the hard mask layer to form at least one fin hard mask120; depositing at least one sacrificial gate structure over the at least one fin hard mask and the substrate130; etching the intermediate semiconductor device to remove a portion of the at least one fin hard mask using the at least one sacrificial gate structure as a mask140; forming at least one pFET region and at least one nFET region150; removing the at least one sacrificial gate structure to create at least one opening160; etching over the at least one fin hard mask to form at least one fin and removing the at least one fin hard mask170; forming a side wall spacer in the at least one opening180; and depositing at least one gate material into the at least one opening190.

FIGS. 2-18depict, by way of example only, one detailed embodiment of a FinFET device formation process ofFIG. 1, and the resultant FinFET structure, in accordance with one or more aspects of the present invention. Note again that these figures are not drawn to scale in order to facilitate understanding of the invention, and that the same reference numerals used throughout different figures designate the same or similar elements.

An intermediate semiconductor device200is schematically illustrated inFIGS. 2-18at several intermediate stages of manufacturing. The terms “intermediate semiconductor device,” “intermediate device,” “semiconductor device,” and “device” may be used interchangeably herein. The semiconductor device200, as shown inFIG. 2, may have been processed through, for example, shallow trench isolation (STI) and well doping. As depicted inFIG. 2, the intermediate device200may include a substrate202which may be made of, for example, a semiconductor material. The semiconductor material may include, e.g., silicon, germanium, a compound semiconductor material, a layered semiconductor material, a silicon-on-insulator (SOI) material, a SiGe-on-insulator (SGOI) material, a germanium-on-insulator (GOI) material, and/or the like. The intermediate structure200may also include at least one shallow trench isolation (STI) region204in the substrate202. The intermediate structure200may further include a first oxide layer206, for example, a sacrificial gate oxide, deposited over the substrate202and the at least one STI region204. A fin hard mask layer208, for example, a SiN layer, may be applied over the first oxide layer206.

As shown inFIGS. 3A-3B, the intermediate device200may be patterned with, for example, lithography and then the fin hard mask layer may be etched to form at least one fin hard mask210. By way of specific example, two fin hard masks210are shown inFIGS. 3A and 3B. The fin hard mask210enables the device200to have a low topology during spacer and junction formation.

FIGS. 4A-4Cshow the intermediate device200after a sacrificial gate structure212is applied over the at least one fin hard mask210and a portion of the first oxide layer206. The sacrificial gate structure212may include a sacrificial material214, for example, an a-Si, a mask216made of, for example, SiN, and an oxide material218made of, for example, SiO2. The sacrificial gate structure212may be formed using known methods, which may include, for example, deposition, lithography, polygate etching, and cut mask etching.

After the sacrificial gate structure212is applied over the at least one fin hard mask210, the sacrificial gate structure212may be used as a mask during etching of the at least one fin hard mask210and the first oxide layer206. As shown inFIGS. 5A-5C, the device200has been etched to remove a portion of the at least one fin hard mask210and a portion of the first oxide layer206. The sacrificial gate structure212preserves the portion of the at least one fin hard mask210and the portion of the first oxide layer206covered by the sacrificial gate structure212. As the device200is etched the remaining at least one fin hard mask210is self-aligned with the sacrificial gate structure212.

As shown inFIGS. 6A-6B, a first spacer220may then be applied to the side walls of the sacrificial gate structure212. The first spacer220may then be etched back to form the desired shape for the first spacer220. For a pFET region, the first spacer220may be, for example, a SiN spacer. Next, as shown inFIGS. 7A-7B, sigma etching may be performed to form the pFET regions222. After the pFET regions222are etched, epitaxial growth may then be performed in the pFET regions222. The pFET epitaxial growth may be, for example, eSiGe or any other pFET material.

Next, as shown inFIGS. 8A-8B, a second spacer224may be applied over the first spacer220to the side of the sacrificial gate structure212. The second spacer224may then be etched back to form the desired shape second spacer224. For an nFET region, the second spacer224may be, for example, a SiN spacer. Then sigma etching may be performed to form the nFET regions226. Next, epitaxial growth may be performed in the nFET regions226. The nFET expitaxial growth may be, for example, SiP or any other nFET material.

A flowable oxide layer228may then be deposited over the device200and the surface of the device200may be planarized, as shown inFIGS. 9A-9B. The flowable oxide layer228may be, for example, a flowable chemical vapor deposition (FCVD) oxide or DUO™. Planarization of the device200may be performed by, for example, chemical mechanical planarization (CMP).

As shown inFIGS. 10A-10C, the replacement metal gate (RMG) process may be performed. The RMG process may include etching the sacrificial gate structure212to remove the mask216and the oxide material218to create an opening230between the first spacer220. When the mask216and the oxide material218are etched the fin hard mask210is revealed. Once the fin hard mask210is revealed, etching may be performed using the fin hard mask210to etch into the substrate202to form at least one fin232. As the at least one fin232is formed during the RMG process the fin is self-aligned to the gate. After the at least one fin232is etched into the substrate202, the fin hard mask210may be removed as well as the first oxide layer206, as shown inFIGS. 11A-11B.

By way of specific example, an intermediate device250with a silicon on insulator (SOI) substrate202may also be used. Dry anistropic etching may be performed on the intermediate device250to form the at least one fin232, as shown inFIGS. 12A-12B. Then the fin hard mask210may be removed, as shown inFIG. 12B.

FIGS. 13A-13Cshow the intermediate device200with a thin barrier layer234applied over the flowable oxide layer228and into the opening230. The barrier layer234may be, for example, SiN. Then an oxide236may be deposited over the barrier layer234of the device200to fill the rest of the opening230. Next the device200may be planarized to remove any extra oxide236over the barrier layer234on the top surface of the device200by, for example, CMP.

As shown inFIGS. 14A-14C, the oxide236may then be etched back to reveal the tip of the at least one fin232. A portion of the oxide236may remain in the bottom of the openings230for isolation, as shown inFIG. 14C. Next the barrier layer234may be etched to form an inner side wall spacer238and to reveal the fins232, as shown inFIGS. 15A-15D. The inner spacer238may be aligned at least partially with the first and second spacers220,224, as shown inFIGS. 15B-15C. The inner spacer238may be, for example, wider at the top of the opening230and narrower at the bottom of the opening230, as shown inFIG. 15B. This shape may enable better deposition of the gate material.

In one embodiment, as shown inFIGS. 16A-16D, the fins232of the device200may include high mobility channels240made of high mobility materials. The high mobility materials for the channels240may include, for example, SiGe or other materials from Groups III-V. If high mobility channels240are desired for the device200, then a portion of the revealed fins232may be etched away. Next an epitaxy process may be performed to grow new channels240in place of the removed portions of the fins232.

Once the fins232are revealed, the gate deposition process may be performed, as shown inFIGS. 17A-17D. The gate deposition process may include applying a dielectric layer242over the fins232, as shown inFIGS. 17B and 17D. The dielectric layer242may be, for example, a high-k dielectric material, such as an oxide. Next a gate material244may be deposited into the opening230over the dielectric layer242. The gate material244may be, for example, a metal gate, a polysilicon gate, or any other known gate material. Then CMP may be performed to remove any extra material on the surface of the device200left during depositing of the gate material244.

As shown inFIG. 18, the device250with a SOI substrate may skip the fabrication steps described above with reference toFIGS. 13A-15Dfor exposing the fins232and proceed to gate deposition. As described above with reference toFIGS. 17A-17D, a dielectric layer242may be deposited over the fins232. Then a gate material244may be deposited over the device250. After the gate material244is applied, CMP may be performed on the device to remove any extra material left on the device during deposition of the gate material244and stopping on the flowable oxide layer228.

Following the gate deposition processes, shown inFIGS. 17A-18, the devices200,250may be passed to MOL and BEOL processes to continue with the fabrication process. If silicidation is performed on the devices200,250, it may be performed as it would be on a planar device making the silicidation process easier than the silicidation process performed during conventional FinFET fabrication.