Method and apparatus for data reception in high-speed applications

A method and apparatus for receiving data in high-speed applications wherein an analog-to-digital converter (ADC) samples a received signal and a data decoder implemented with a tree search algorithm detects the bits of the sampled data for timing recovery. In some embodiments, a Viterbi detector is implemented to provide accurate bit detection for data output while tree search detected data is used to determine the optimal sampling phase for the ADC. In some embodiments, after the phase acquisition stage of timing recovery has completed, the tree search decoder may decrease the rate of data detection to maintain phase tracking.

FIELD

Aspects of the present invention relate generally to the field of data transmission and more specifically to timing recovery using a low latency tree search algorithm for data detection.

DESCRIPTION OF THE RELATED ART

In high-speed data transmission channels, for example backplane 10GBASE-KR or fiber 10GBASE-LRM channels, channel induced amplitude attenuation, group delay, and pulse spreading may result in significant inter-symbol interference (ISI). Conventional high-speed receivers often implement a decision feedback equalizer (DFE) to deal with the group delay distortion and to compensate for induced ISI by decoding or detecting the value of the received bits.

FIG. 1is a simplified block diagram illustrating a conventional high-speed data transmission system. A data transmission system100may include a transmitter110with a transmit filter111and a digital-to-analog converter (DAC)112. The analog signal may be transmitted on a channel120and received at receiver130. Receiver130may include an analog-to-digital converter (ADC)140, a feed-forward equalizer (FFE)150, a decision feedback equalizer (DFE)160, a timing recovery loop170, and a slicer180. The FFE150may filter the input signal to minimize the effect of precursor ISI (ISI induced by bits not yet detected). The DFE160may be implemented to minimize the effect of the post-cursor ISI (ISI induced by previously detected hits). Then, the equalized signal input into slicer180may be substantially free of ISI. The slicer180may be a data detector or limiter that may determine whether to output a +1 bit or a −1 hit based on the sign of the equalized signal.

The timing recovery loop170may determine the optimal sampling phase for the ADC to maximize the signal-to-noise ratio (SNR). The optimal sampling phase may be determined by calculating the error existent in the equalized signal and using that calculation to anticipate the proper sampling phase needed to minimize error in the conversion of the received signals. However, the implementation of a data transmission system shown inFIG. 1may not be desirable where error introduced by the DFE160may be fed back and replicated throughout the timing recovery loop170.

One method for mitigating error propagation in data transmission systems having complex channels has conventionally involved the implementation of a Viterbi detector.FIG. 2is a simplified block diagram illustrating a conventional high-speed data transmission system implemented with a Viterbi detector. Similar to the system100shown inFIG. 1, system200may include a transmitter210with a transmit filter211and a DAC212. The converted signal may be transmitted on channel220and received at receiver230. Receiver230may include an ADC240, an FFE250, a timing recovery loop270, and a Viterbi detector260. As is known in the art, Viterbi detector260may be a maximum likelihood sequence detector capable of accurately decoding the bits of the equalized signal.

In receivers implemented with a timing recovery loop, like those in data transmission system100and data transmission system200, the jitter bandwidth that the receiver is able to track, and therefore the signal-to-noise ratio (SNR), may be directly impacted by the loop latency. Loops with smaller latencies may have larger tracking bandwidths. Unfortunately, Viterbi detector implementation is complex and may introduce significant latency into the signal detection and timing recovery loop. Each sequence determination by a Viterbi detector may require hundreds of clock cycles. Therefore, in a high speed system, the high loop latency inherent in Viterbi detection may have a significant and negative impact on the timing recovery loop270, and may result in a very low tracking bandwidth thereby limiting the jitter that the receiver230is able to track, and may significantly degrade the signal-to-noise ratio (SNR) due to untracked jitter.

Accordingly, there is a need in the art for a receiver that negates ISI without inducing significant latency.

DETAILED DESCRIPTION

At speeds of 1 Gbps or lower, oversampled CDR is very common. However, at speeds such as 10 Gbps, the receiver has to perform baud-rate timing recovery. Since such schemes are dependent on the error signal, there is also a high latency associated with the scheme. A data decoder implemented with a tree decoding algorithm may be used for timing recovery in high-speed applications and may provide a low latency, low power alternative to traditional timing recovery methods. A tree decoder may be implemented along with a Viterbi detector to provide accurate results when decoding the input data and to maintain efficient timing recovery.

FIG. 3is a simplified block diagram of an embodiment of a data receiver implemented with a tree search decoder. Receiver300may receive an input signal from channel310and may include an analog-to-digital converter320, an FFE330, a tree decoder module340, a target filter350and a timing recovery loop360. Channel310may be any transmission channel provided by communications or computer networks, for example either a wired or wireless network or any high-speed channel, for example backplane 10GBASE-KR or fiber 10GBASE-LRM. The FFE330may minimize the effect of precursor ISI, limit noise, and equalize the channel. As shown inFIG. 3, the FFE output sampled at instant k is denoted by yk.

Target filter350may be a filter with taps set to limit the post-cursor ISI from the detected bits thereby approximating desired input signal. In an embodiment using a four-bit sequence, target filter350may have four taps designated by {g0, g1, g2, g3} where g0-g3may represent the target coefficients.

The tree decoder module340may be implemented to decode the bits of the equalized channel with minimum latency. In an embodiment of the present invention, the tree decoder module340may be implemented with a tree having multiple potential states. In an exemplary embodiment having 16 states, the decoding delay of the tree decoder module340may be represented by Equation 1, and the decoding delay of the tree decoder module340may be 3. A delay of 3 indicates that bit bkmay be decoded when yk+3is output by the FFE350.
(log2(NSTATES)−1)  Eq. 1

According to another feature, tree decoder module340may decode the same number of bits with fewer potential states by implementing a sequence feedback in the branch metric computation.

FIG. 4shows one embodiment of a state tree for the tree decoder module340. A bit sequence for each of the 16 potential states, represented by each distinct path in the tree, may be labeled as s0through s15where s0is the topmost path and may be represented as s0={1,1,1,1} and the bottommost path may be represented as s15={−1, −1, −1, −1}. A branch metric λj, representing the distance metric for the target sequence at the current level of the tree, for branch j may be calculated in accordance with Equation 2.

A path metric representing a Euclidean metric for the negative of the distance between the received signal and a certain branch, may then be calculated in accordance with Equation 3.

Once the path metric for each state in the state tree is calculated, the kthbit may be decoded as a 1 if the largest metric lies in the top half of the tree, otherwise, the kthbit may be decoded as −1. Then, every metric in the top half of the tree may need to be compared to every metric in the bottom to determine the decoded bit. Alternatively, the determination may be made by summing the exponential of all the top half metrics and comparing that value to the sum of the exponentials of the bottom half metrics in accordance with Equation 4.

Returning toFIG. 3, while the tree decoder module340may decode the equalized hits with limited delay appropriate for proper timing recovery, the accuracy of the decoded bits may still suffer from error propagation. To produce a higher quality of output without losing the benefits to the timing recovery loop360gained by the small latency of the tree decoder module340, a Viterbi detector may be implemented as shown inFIG. 5.

FIG. 5is a simplified block diagram of an embodiment of a data receiver implemented with a tree search decoder and a Viterbi detector. Receiver500may receive an input signal from channel510and may include an ADC520, an HE530, a tree decoder module540, a target filter550, a Viterbi detector560and a timing recovery loop570. The tree decoder module540and target filter550may be implemented as described above with reference toFIG. 3. Additionally, Viterbi detector560may operate as previously described with reference toFIG. 2. However, the output of the receiver, the decoded bits, may be the decoded results output from the Viterbi detector560rather than from the tree decoder module540. However, the Viterbi decoded bits have no impact on the timing recovery loop570.

FIG. 6is a simplified block diagram of an embodiment of a data receiver with detail in the timing recovery loop. Receiver600may receive an input signal from channel610and may include an ADC620, an FFE630, a tree decoder module640, a target filter650, a Viterbi detector660and a timing recovery loop670. The tree decoder module640, target filter650, and Viterbi detector660may each be implemented as described above with reference toFIG. 5.

Timing recovery loop670may be implemented digitally to obtain frequency and phase lock at the receiver and further minimize ISI. Conventional oversampling of the analog-to-digital conversion to obtain multiple samples per symbol period and achieve frequency and phase lock is not feasible in high-speed applications, thus baud rate timing recovery is preferable. Zero-forcing (ZF) timing recovery may be implemented at baud rate while still achieving near optimal timing results. Then, as shown inFIG. 6, an embodiment of the timing recovery loop670may implement a timing error detector671, a loop filter672, and a voltage-controlled oscillator (VCO)673.

Timing error detector671may be implemented to determine sampling phase error χkby de-correlating an error signal ekwith the derivative of a desired received signal. This has the effect of minimizing the sampling phase error and automatically minimizes the error power. The detected signal dkmay be calculated as the decoded bits bk, filtered through the target filter. The error signal ekmay be determined as the difference between the detected signal dkand the received signal ykin accordance with Equation 5.
ek=yk−(b*g)kEq. 5

Then, the timing error detector671may determine the sampling phase error χkin accordance with Equation 6 where the instantaneous sampling phase is represented by ψk.

The derivative of the FFE output ykmay be approximated in the digital domain using a (1−D2) filter, eliminating the need for a separate sampler to obtain the derivative of yk. However, ykmay still contain residual ISI and other noise (i.e. thermal noise or phase noise), which may lead to a drift in the sampling phase. Sampling phase drift may be countered by replacing ykwith dkyielding Equation 7.
χk=2ek(dk+1−dk−1)  Eq. 7

The loop filter672may then filter the timing error χkand the frequency, and the phase of the VCO673may then be adjusted by the filtered timing error. The VCO673may then output the timing control information. The timing control information may include a sampling clock signal that may drive the ADC620. The effect of the timing control information on the sampling phase may then be illustrated by Equation 8 where Kpand Kfmay represent the first and second order loop constants respectively.
ψk+1=ψk+Kpχk+Kf,outkwhereKf,outk=Kf,outk−1+KfχkEq. 8

Once the timing recovery loop670has completed acquisition of the timing phase and is simply tracking the sampling phase, the update rate of the timing recovery may be reduced. Then only a portion of the input bits need be decoded by the tree decoder module640and input into the timing recovery loop670. The update rate may be determined by the available power in the receiver600.

As discussed above,FIG. 6is a simplified block diagram of the basic architecture of an embodiment of the receiver. The receiver may be embodied as a hardware system, in which case, the blocks illustrated inFIG. 6may correspond to circuit sub-systems within a receiver system. The circuit sub-systems may be implemented together on a single integrated circuit or a single chip. Alternatively, the receiver may be embodied as a software system, in which case the blocks illustrated may correspond to program modules within a receiver software program. In yet another embodiment, the receiver may be a hybrid system involving both hardware circuit systems and software programs. In any event, the basic flow through the receiver, with input from a channel and an output of decoded bits, results.

Additionally, it is noted that the arrangement of the blocks inFIG. 6does not necessarily imply a required set of components, nor is it intended to exclude other possibilities. For example, the functions depicted by blocks650and670may be implemented by a single functional unit, or may be eliminated in some instances.

FIG. 7is a simplified flow diagram illustrating decoding received data to limit ISI according to an embodiment of the present invention. As previously noted, ISI may be introduced in a signal transmitted over a channel that may cause amplitude attenuation, pulse spreading, or group delay leading to signal distortion. A received signal may be adaptively equalized to limit the effect of the ISI introduced during transmission.

At710, an analog signal may be received and converted to digital. To effectively convert the signal, it may be sampled in set intervals, the number of samples taken per time period (e.g. per second) known as the sampling rate. At720, the converted digital sample may be filtered to limit the precursor ISI and/or other noise existent in the sample. Precursor ISI is noise that may be introduced in the signal due to a portion of the signal not yet received.

The filtered sample may be decoded at730to determine the probable value of the received signal. During the analog to digital conversion at710, the signal may not have been sampled at the peak of the signal waveform, or the ISI and noise existent in the signal may have significantly impacted the sampled value of the signal. Therefore, decoding is necessary to detect and output the best possible result. At730, a tree search algorithm may be implemented to decode the littered sample. The tree search algorithm is further explained below with reference toFIG. 8.

After the filtered sample is decoded, the decoded bits may be output as the detected received value and may additionally be used for timing recovery. At740, the decoded sample may be filtered with a target filter to limit post cursor ISI. At750, the filtered decoded sample may be used with the filtered sample output from720to calculate the error in the digital sample in accordance with Equation 7. At760, the calculated error may be used to determine an appropriate sampling phase to further minimize the sample error. That sampling phase may then be used to convert future input signals into digital samples at710.

FIG. 8is a simplified flow diagram illustrating decoding sampled data using a tree search algorithm according to an embodiment of the present invention. A tree search algorithm may use as metric the negative of the squared Euclidean distance between the filtered sample ykand the target sample, where the target sample represents the value that should be received when ISI and noise are reduced to a predefined level, from the signal and when the sampling phase is accurate. To utilize the tree search algorithm, a branch metric for each branch may be calculated in accordance with Equation 2, at810.

At820, a path metric may be calculated for each path in accordance with Equation 3. After the relevant metrics have been calculated, the decoded bit, bk, for the filtered sample, yk, may be determined. The bit bkmay be decoded to be a +1 if the largest metric lies in the top half of the tree, otherwise the bit may be decoded to be a −1. This determination may be accomplished by comparing every metric in the top half of the tree with every metric in the bottom half of the tree. However, if each bit may be considered to be independent and uniformly distributed within {±1}, then the decoded bit may be determined as shown at830, and in accordance with Equation 4. Then, if Σexp(top-half)>Σexp(bottom-half) at830, at840, bkmay be determined as bk=+1. Additionally, because the first bit of a detected sequence may be positive, the branch metrics associated with the remaining bottom half of the tree (with reference toFIG. 4, all branches following and including branch430) may be discarded while the branch metrics of the top half of the tree may persist. However, if at830Σexp(top-half)≦Σexp(bottom-half), at850, bkmay be determined as bk=−1 and, because the first bit in a sequence may be determined to be −1, the branch metrics associated with the top half of the tree (with reference toFIG. 4, all branches following and including branch440) may be discarded while the branch metrics of the bottom half of the tree may persist.

After bkis determined, and half of the tree may be discarded, at860, the tree may be expanded to again include 16 states by adding new branches to the remaining end branches (with reference toFIG. 4, the end branches are the branches at m0410through m15420). Thus, the branch metrics may be persistent and accumulative over time. Then, with a complete and partially persistent tree, the next value of bk+1may be determined by returning to810with next filtered sample yk+1.

FIG. 9is a simplified flow diagram illustrating decoding received data to limit ISI with separate decoders for output and timing recovery according to one feature of the present invention. Similarly to the embodiment illustrated inFIG. 7, inFIG. 9at910, an input signal is received and converted to a digital sample. At920, the converted digital sample may be filtered and at930, decoded. At940, the decoded sample may be filtered. At950, the error in the digital sample may be calculated using the filtered decoded sample calculated at940and the filtered sample calculated at920. At960, the calculated error may be used to determine an appropriate sampling phase that may then be used at910for future input signals.

However, the decoded sample determined at930may be used for timing recovery while an alternate decoder may be used to decode the filtered sample with higher accuracy. For example, a Viterbi detection algorithm may be implemented at935to decode the filtered sample. Using two different decoding algorithms may allow the advantages of both to be utilized in the system. For example, the significant latency inherent with the Viterbi algorithm may not affect the timing recovery, and the error propagation inherent with the tree search algorithm may not affect the accuracy of the output decoded bits.

It is noted that the arrangement inFIGS. 7-9do not necessarily imply a particular order or sequence of events, nor is it intended to exclude other possibilities. For example, the calculations depicted at810,820and830may occur substantially simultaneously with each other; additionally, the operations depicted at740and750may be combined into a single operation or may be eliminated in some instances.

While the invention has been described in detail above with reference to some embodiments, variations within the scope and spirit of the invention will be apparent to those of ordinary skill in the art. Thus, the invention should be considered as limited only by the scope of the appended claims.