UNIFIED CRACKSTOP STRUCTURE FOR JOINING SEMICONDUCTOR BUILDS

A unified crackstop structure is described incorporating at least two semiconductor builds, each having a crackstop structure on its periphery and a metal wall or line extending from one crackstop structure to the other.

BACKGROUND

The present invention relates generally to the electrical, electronic and computer arts and, more particularly, to joining two semiconductor builds such as chips, dies, wafers, interposers, or combinations thereof together and, more particularly, to structures that prevent moisture ingress as well as block or minimize external or internal crack growth or propagation originating primarily from dicing wafers and delamination and warpage from chip package interaction (CPI) related issues or threats, and the like.

In 2.5 and 3D packaging, two or more semiconductor builds may be joined together by thermal compression bonding, with each respective semiconductor build having respective metal based crackstop structures built in the back end of line (BEOL) dielectric stack layers. Thermal compression bonding is a semiconductor package joining technique that connects two or more semiconductor based builds through the use of solder bumps but inadvertently leaves a gap between the semiconductor builds at the edges where the crackstop structures are located. In the gap, with or without underfill, cracks can form in either semiconductor build; the cracks can separate the two bonded semiconductor builds or provide an entry point for cracks to bypass the crackstop structures and have direct access into the active device regions of the respective semiconductor builds and therefore could potentially rip/pull apart portions of the two adjoined semiconductor builds resulting in catastrophic failure of the semiconductor package assembly. The terms ‘2.5D’ and ‘3D’ are used herein in their normal sense as will be familiar to the skilled artisan; namely, they refer to packaging methodologies for including multiple integrated circuits in the same package. In a 2.5D structure, two or more active semiconductor chips are placed side-by-side on a silicon interposer or substrate to obtain high die-to-die interconnect density. In a 3D structure, active chips are integrated by die stacking to provide short interconnects and a small package footprint.

BRIEF SUMMARY

Principles of the invention provide techniques for a unified crackstop structure for joining semiconductor builds. In one aspect, an exemplary semiconductor structure includes a first semiconductor build having a first crackstop structure along a first periphery of the first semiconductor build, a second semiconductor build having a first crackstop structure along a first periphery of the second semiconductor build, and a metal line bonded to the first crackstop structure of the first semiconductor build and the first crackstop structure of the second semiconductor build to form a wall between and along a portion of the first peripheries of the first and second semiconductor build such that the crackstop structures are joined together by the metal line.

In another aspect, an exemplary method for joining two semiconductor builds includes the steps of selecting two semiconductor builds, each having a crackstop structure on a periphery thereof, forming a metal line adjoining a corresponding one of the crackstop structures on one of the semiconductor builds, aligning the metal line over the crackstop structure of the other semiconductor build, and bonding the metal line to the other semiconductor build such that the two semiconductor builds form a rigid structure to resist external and internal crack nucleation or growth, delamination and warpage resulting from external energies and other CPI-related threats.

As used herein, “facilitating” an action includes performing the action, making the action easier, helping to carry the action out, or causing the action to be performed. Thus, by way of example and not limitation, instructions executing on a processor might facilitate an action carried out by semiconductor fabrication equipment, by sending appropriate data or commands to cause or aid the action to be performed. Where an actor facilitates an action by other than performing the action, the action is nevertheless performed by some entity or combination of entities.

Techniques as disclosed herein can provide substantial beneficial technical effects. Some embodiments may not have these potential advantages and these potential advantages are not necessarily required of all embodiments. By way of example only and without limitation, one or more embodiments may provide one or more of:Preventing/blocking external cracks in semiconductor structures formed from multiple semiconductor builds;Holding dies or other semiconductor builds together preventing internal cracking/delamination from occurring;Enhancing rigidity of semiconductor structures by preventing shear tearing apart the C4 (controlled collapse of chip connection) structures;Enhancing rigidity/strength by preventing pull-apart/tensile disruption.

DETAILED DESCRIPTION

Principles of inventions described herein will be in the context of illustrative embodiments. Moreover, it will become apparent to those skilled in the art given the teachings herein that numerous modifications can be made to the embodiments shown that are within the scope of the claims. That is, no limitations with respect to the embodiments shown and described herein are intended or should be inferred.

Referring now to the drawing,FIG.1shows a cross section view of semiconductor structure10comprising semiconductor builds12,14, and16. Semiconductor build12includes a silicon substrate18which has devices therein not shown and device contacts not separately numbered. Interconnect layers30interconnect the devices with metal wiring32to the device contacts and to contact pads38,40and42. Crackstop structures44and46are built at the same time interconnect layer30is formed and include landing pads50and52above crackstop structures44and46. Crackstop structures44and46follows a periphery path around the perimeter of silicon substrate18. Landing pads50and52likewise are above respective crackstop structures44and46and follows the periphery around silicon substrate18.

Semiconductor build14has the same structure as semiconductor build12. Semiconductor14has silicon substrate58, an interconnect layers70, and metal wiring72. Semiconductor build14has contact pads78,80and82, and crackstop structures84and86and respective landing pads90and92positioned above crackstop structures84and86at the surface of substrate58. Semiconductor builds12and14are positioned to interconnect contact pads38,40,42,78,80, and82to contact pads114-119of semiconductor build16.

Semiconductor build16has a silicon substrate88, an interconnection layer110, metal wiring112, contact pads114-119and crackstop structures122,124,126and128and have respective landing pads123,125,127and129. Semiconductor build16is aligned with respective crackstop structures on semiconductor build12and semiconductor build14wherein metal lines130,132,134and136are formed by thermal compression bonding semiconductor build12and semiconductor build14to semiconductor build16. At the same time contact pads of semiconductor build12and16are joined by solder bumps positioned on one semiconductor build being compressed against and bonded to the contact pads of the other.

As shown inFIG.1, Metal line130along with landing pads50and123provide a unified crackstop with a continuous metal wall from crackstops44of semiconductor build12to crackstops122of semiconductor build16. Metal line132along with landing pads52and125provide a unified crackstop structure with a continuous metal wall from crackstop structure46of semiconductor build12to crackstop structure124of semiconductor build16. Metal line134along with landing pads90and127provide a unified crackstop structure with a continuous metal wall from crackstop structure84of semiconductor build14to crackstop126of semiconductor build16. Metal line136along with landing pads92and129provide a unified crackstop structure with a continuous metal wall from crackstop structure86of semiconductor build14to crackstop structure128of semiconductor build16. Metal lines130,132,134and136may include, for example, lead tin solder. While two unified crackstop structure130and132are shown inFIG.1on the periphery of semiconductor builds12and14, one unified crackstop structure may be used for simplicity but potentially with a higher risk of cracks propagating into the active or device area of the semiconductor build. An underfill138may be inserted into the space between semiconductor builds12and16and underfill139may be inserted into the space between semiconductor builds14and16.

FIG.2is a cross section view showing a defective semiconductor structure150comprising semiconductor build152over a silicon interposer154positioned over a laminate156to form a semiconductor structure. Solder bumps or C4 bumps are shown making interconnections between semiconductor build152and silicon interposer154and between silicon interposer154and laminate156. Silicon interposer154is shown warped into an arc profile causing solder bumps155and158to separate at the ends of silicon interposer154and solder bump157to separate in the middle of interposer154due to its' deformation or warping. The terms ‘2.5D’ and ‘3D’ are used herein in their normal sense as will be familiar to the skilled artisan; namely, they refer to packaging methodologies for including multiple integrated circuits in the same package. In a 2.5D structure, two or more active semiconductor chips are placed side-by-side on a silicon interposer to obtain high die-to-die interconnect density. In a 3D structure, active chips are integrated by die stacking to provide short interconnects and a small package footprint.

FIGS.3A-3Fare cross section views of unified crackstop structures having different landing pad shapes affecting the shape of the metal line formed along with other factors such as spacing between landing pads, quantity of solder and the surface tension of the solder.FIG.3Ashows semiconductor builds160and162having unified crackstop structures164and166. Unified crackstop structure164has landing pads168and170and metal line172there between. Landing pads168and170have a flat surface and are flush with the surrounding surfaces171and173. Unified crackstop structure166is the same as crackstop structure164.FIG.3Bis similar toFIG.3Aexcept landing pads174and176are recessed below the surrounding surfaces173and175and allow a larger volume of metal and allows for a taller metal line177.FIG.3Cis similar toFIG.3Bexcept inFIG.3Clanding pads180and182extend laterally from unified crackstop structure164to166(as numbered inFIG.3A) forming one metal line184with a larger volume of solder.

FIG.3Dis similar toFIG.3Aexcept landing pads188and190of unified crackstop structure164(as numbered inFIG.3A) extends laterally outward away from beneath the crackstop structure164towards the edges of semiconductor builds160and162. Metal line192is wider than unified crackstop structure164ofFIG.3A.FIG.3Eis similar toFIG.3Dexcept landing pads194and196extend from unified crackstop structure164to166(as numbered inFIG.3A) forming one metal line198with a larger volume of solder.FIG.3Fis similar toFIG.3Eexcept inFIG.3Flanding pads202and204extend laterally from unified crackstop structure164to166(as numbered inFIG.3A) forming one metal line206with a larger volume of solder. It is worth noting that the top landing pads of the crackstops could be, for example, copper, aluminum, or the like.

FIG.4shows a portion of the upper surface210of a semiconductor build212in a three dimensional view. Metal line214is positioned on landing pad216. Solder balls217are shown spaced apart on contact pads218.

FIG.5shows a three dimensional view of a partially separated embodiment of the invention. Semiconductor structure220comprises semiconductor builds222and224. Semiconductor build222has crackstop structure226on the periphery of the semiconductor build222. Above crackstop structure226is landing pad228and metal line230. Interior of metal line230are solder bumps232on contact pads234.

Semiconductor build224has crackstop structure238on the periphery of the semiconductor build224. Above crackstop structure238is landing pad242positioned to receive metal line230when semiconductor build222is aligned and thermal compression bonded to semiconductor build224. Interior of metal line244are contact pads246positioned to receive solder bumps232during the step of bonding.

FIGS.6A-6Care enlarged cross-section views showing the formation of unified crackstop structure250without showing other portions of the semiconductor builds252and254. As shown inFIG.6A, semiconductor build252has two parallel crackstop structures256and258, two landing pads260and262thereon and two solder lines264and266. Semiconductor build254has two corresponding parallel crackstop structures268and270and two landing pads272and274thereon.FIG.6Bis similar toFIG.6Aexcept solder lines264and266(as numbered inFIG.6A) are positioned over and in initial contact with landing pads272and274(as numbered in FIG.6A) respectively.FIG.6Cshows semiconductor builds252and254(as numbered inFIG.6A) joined together by compressing the solder lines264and266(as numbered inFIG.6A) to form unified crackstop structure250. As shown inFIG.6C, solder lines264and266are electrically and mechanically joined due to solder deformation during compression or bonding of solder lines264and266and the spacing of the landing pads.

FIGS.7A-12Bare top views and cross section views illustrating a first method for forming metal lines on a semiconductor build for building a unified crackstop structure. Such a structure can be formed at times when the semiconductor build is joined with another semiconductor build having a crackstop structure and metal landing pads thereon for receiving metal lines.FIG.7Ais a top view showing the outline on a semiconductor build280having two crackstop structures282and284and four bump pads286underneath a seed layer288.FIG.7Bshows a cross-section view of7A along the lines7B-7B showing the upper layers of semiconductor build280.FIG.8Ais a top view as shown inFIG.7Aexcept with a photoresist layer290on the top surface.FIG.8Bis a cross-section view ofFIG.8Aalong the lines8B-8B.FIG.9Ais a top view as shown inFIG.8Aexcept with photoresist layer290patterned and developed as patterned layer292.FIG.9Bis a cross-section view ofFIG.9Aalong the lines9B-9B showing openings294,296,298and300.

FIG.10Ais a top view as shown inFIG.9Aafter solder302has been electroplated where the seed layer is exposed.FIG.10Bis a cross-section view ofFIG.10Aalong the lines10B-10B.FIG.11Ais a top view as shown inFIG.10Aafter the photoresist290has been removed.FIG.11Bis a cross-section view ofFIG.11Aalong the lines11B-11B showing solder302.FIG.12Ais a top view of the structure ofFIG.11Aafter metal reflow-referring also toFIG.12Bshowing metal lines304and306and solder bumps308after metal reflow.FIG.12Bis a cross-section view ofFIG.12Aalong the lines12B-12B after metal reflow. The height of bumps306and308is shown by arrow305.

FIGS.7A-8B and13A-16Bare top views and cross section views illustrating a second method for forming metal lines on a semiconductor build for building a unified crackstop structure (FIGS.7A-8Bare the same for both methods). Such a structure can be formed at times when the semiconductor build is joined with another semiconductor build having a crackstop structure and metal landing pads thereon for receiving metal lines.FIG.7Ais a top view showing the outline on a semiconductor build280having two crackstop structures282and284and four bump pads286underneath a seed layer288.FIG.7Bshows a cross-section view of7A along the lines7B-7B showing the upper layers of semiconductor build280.FIG.8Ais a top view as shown inFIG.7Aexcept with a photoresist layer290on the top surface.FIG.8Bis a cross-section view ofFIG.8Aalong the lines8B-8B.FIG.13Ais a top view as shown inFIG.8Awith the photoresist290patterned and developed as patterned photoresist307forming an array of openings310for two metal lines and solder bump openings312.FIG.13Bis a cross-section view ofFIG.13Aalong the lines13B-13B.FIG.14Ais a top view as shown inFIG.13Aexcept solder302,303has been electroplated where the seed layer is exposed.FIG.14Bis a cross-section view ofFIG.14Aalong the lines14B-14B.

FIG.15Ais a top view as shown inFIG.14Aafter patterned photoresist308has been removed.FIG.15Bis a cross-section view ofFIG.15Aalong the lines15B-15B showing the solder302and303remaining after the photo resist is removed.FIG.16Ais a top view as shown inFIG.15Ashowing two arrays of metal bumps312for two metal lines and solder bumps315after metal reflow.FIG.16Bis a cross-section view ofFIG.16Aalong the lines16B-16B. The height of solder bumps312and315is shown by arrow313.

FIGS.17-19are cross section views to show steps for joining two semiconductor builds320and322to form two unified crackstop structures. Semiconductor build320has crackstop structures330and332each contacting a respective landing pad334and336. On landing pads334and336are solder bumps338sized to form a metal line after (i) compression with another semiconductor build and (ii) metal reflow. Solder bumps340are for electrical contacts. Semiconductor build322has crackstop structures342and344each contacting a respective landing pad346and348. Landing pads346and348are shaped to receive solder338. Contact pads350are flat for receiving solder bumps340.

FIG.18is the same asFIG.17except semiconductor build320is aligned and brought in contact with semiconductor build322. Pressure351is applied to compress solder bumps338and340a predetermined amount.

FIG.19is the same asFIG.18except solder bumps have reflowed into metal lines356and358in response to heat. InFIG.19a solid metal wall or line is formed between crackstop structures330and342to form one unified crackstop structure360and a solid metal wall is formed between crackstop structures332and344to form unified crackstop structure362.FIG.19is a cross section view of metal lines356and358that extend around a portion of or the entire periphery on landing pads334and336of semiconductor builds320and322. It is understood that inFIG.19, metal lines356and358run in the direction perpendicular to the printed page they are shown on.

FIG.20Ais a top view of internal surface370of a semiconductor build joined with another semiconductor build, not shown, having two continuous unified crackstop structures having respective peripheral metal lines372and374and solder bumps375in the interior370. A needle378is shown inserting dielectric376to underfill any voids or spaces. Arrow380shows the direction of dielectric flow.

FIG.20Bis the same asFIG.20Aexcept peripheral metal line374has openings382to allow dielectric376to flow between metal lines372and374and to all voids and spaces.

FIG.20Cis the same asFIG.20Aexcept peripheral metal lines372and374both have respective openings381and382for inserting and flowing dielectric376to all voids and spaces.

Semiconductor device manufacturing includes various steps of device patterning processes. For example, the manufacturing of a semiconductor chip may start with, for example, a plurality of CAD (computer aided design) generated device patterns, which is then followed by effort to replicate these device patterns in a substrate. The replication process may involve the use of various exposing techniques and a variety of subtractive (etching) and/or additive (deposition) material processing procedures. For example, in a photolithographic process, a layer of photo-resist material may first be applied on top of a substrate, and then be exposed selectively according to a pre-determined device pattern or patterns. Portions of the photo-resist that are exposed to light or other ionizing radiation (e.g., ultraviolet, electron beams, X-rays, etc.) may experience some changes in their solubility to certain solutions. The photo-resist may then be developed in a developer solution, thereby removing the non-irradiated (in a negative resist) or irradiated (in a positive resist) portions of the resist layer, to create a photo-resist pattern or photo-mask. The photo-resist pattern or photo-mask may subsequently be copied or transferred to the substrate underneath the photo-resist pattern.

There are numerous techniques used by those skilled in the art to remove material at various stages of creating a semiconductor structure. As used herein, these processes are referred to generically as “etching”. For example, etching includes techniques of wet etching, dry etching, chemical oxide removal (COR) etching, and reactive ion etching (RIE), which are all known techniques to remove select material(s) when forming a semiconductor structure. The Standard Clean 1 (SC1) contains a strong base, typically ammonium hydroxide, and hydrogen peroxide. The SC2 contains a strong acid such as hydrochloric acid and hydrogen peroxide. The techniques and application of etching is well understood by those skilled in the art and, as such, a more detailed description of such processes is not presented herein.

Although the overall fabrication method and the structures formed thereby are novel, certain individual processing steps required to implement the method may utilize conventional semiconductor fabrication techniques and conventional semiconductor fabrication tooling. These techniques and tooling will already be familiar to one having ordinary skill in the relevant arts given the teachings herein. For example, the skilled artisan will be familiar with epitaxial growth, self-aligned contact formation, formation of high-K metal gates, and so on. The term “high-K” has a definite meaning to the skilled artisan in the context of high-K metal gate (HKMG) stacks, and is not a mere relative term. Moreover, one or more of the processing steps and tooling used to fabricate semiconductor devices are also described in a number of readily available publications, including, for example: James D. Plummer et al.,Silicon VLSI Technology: Fundamentals, Practice, and Modeling1st Edition, Prentice Hall, 2001 and P. H. Holloway et al.,Handbook of Compound Semiconductors: Growth, Processing, Characterization, and Devices, Cambridge University Press, 2008, which are both hereby incorporated by reference herein. It is emphasized that while some individual processing steps are set forth herein, those steps are merely illustrative, and one skilled in the art may be familiar with several equally suitable alternatives that would be applicable.

It is to be appreciated that the various layers and/or regions shown in the accompanying figures may not be drawn to scale. Furthermore, one or more semiconductor layers of a type commonly used in such integrated circuit devices may not be explicitly shown in a given figure for ease of explanation. This does not imply that the semiconductor layer(s) not explicitly shown are omitted in the actual integrated circuit device.

Those skilled in the art will appreciate that the exemplary structures discussed above can be distributed in raw form (i.e., a single wafer having multiple unpackaged chips), as bare dies, in packaged form, or incorporated as parts of intermediate products or end products.

An integrated circuit in accordance with aspects of the present inventions can be employed in essentially any application and/or electronic system. Given the teachings of the present disclosure provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of embodiments disclosed herein.

The illustrations of embodiments described herein are intended to provide a general understanding of the various embodiments, and they are not intended to serve as a complete description of all the elements and features of apparatus and systems that might make use of the circuits and techniques described herein. Many other embodiments will become apparent to those skilled in the art given the teachings herein; other embodiments are utilized and derived therefrom, such that structural and logical substitutions and changes can be made without departing from the scope of this disclosure. It should also be noted that, in some alternative implementations, some of the steps of the exemplary methods may occur out of the order noted in the figures. For example, two steps shown in succession may, in fact, be executed substantially concurrently, or certain steps may sometimes be executed in the reverse order, depending upon the functionality involved. The drawings are also merely representational and are not drawn to scale. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof. Terms such as “bottom”, “top”, “above”, “over”, “under” and “below” are used to indicate relative positioning of elements or structures to each other as opposed to relative elevation. If a layer of a structure is described herein as “over” another layer, it will be understood that there may or may not be intermediate elements or layers between the two specified layers. If a layer is described as “directly on” another layer, direct contact of the two layers is indicated. As the term is used herein and in the appended claims, “about” means within plus or minus ten percent.

The corresponding structures, materials, acts, and equivalents of any means or step-plus-function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the various embodiments has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the forms disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit thereof. The embodiments were chosen and described in order to best explain principles and practical applications, and to enable others of ordinary skill in the art to understand the various embodiments with various modifications as are suited to the particular use contemplated.

Given the teachings provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of the techniques and disclosed embodiments. Although illustrative embodiments have been described herein with reference to the accompanying drawings, it is to be understood that illustrative embodiments are not limited to those precise embodiments, and that various other changes and modifications are made therein by one skilled in the art without departing from the scope of the appended claims.