System for and method of integrating test structures into an integrated circuit

A system and method for performing device-specific testing and acquiring parametric data on integrated circuits, for example ASICs, such that each chip is tested individually without excessive test time requirements, additional silicon, or special test equipment. The testing system includes a device test structure integrated into unused backfill space in an IC design which tests a set of dummy devices that are identical to a selected set of devices contained in the IC. The device test structures are selected from a library according to customer requirements and design requirements. The selected test structures are further prioritized and assigned to design elements within the design in order of priority. Placement algorithms use design, layout, and manufacturing requirements to place the selected test structures into the final layout of the design to be manufactured.

CROSS REFERENCES RELATED TO THE APPLICATION

This application is related to pending U.S. application Ser. No. 11/459,367 assigned to the present assignee.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to the field of acquiring manufacturing process data on a part-by-part basis (e.g. chip), and more specifically, to providing a means to acquire device data with which to perform a detailed product analysis, which is further used to tune the manufacturing processes.

2. Background of the Invention

Due to the complex and precise nature of semiconductor manufacturing, it is critical to ensure that all processes in the manufacturing line are within required specifications. This ensures the highest product yield. Monitoring the manufacturing process and correcting for deficiencies is critical for maintaining the health of the line (HOL).

Some testing is done in-line during manufacturing to tune the process real-time, and other tests are performed after manufacturing. Kerf testing is a common type of testing and provides information for a group of die on a wafer relating to process, voltage, and temperature (PVT). Other tests include: I/O receiver/driver levels, performance screen ring oscillator (PSRO) testing, and MUX scan testing, also known as “at speed” testing.

The problem with kerf testing is that it does not provide detailed information specific to each die on the wafer and further, cannot provide information about the electrical parameters of certain devices within each of the chips; especially custom designs which have smaller manufacturing lot sizes, device dimensions which vary from standard devices, and other product-specific qualities.

Since in-line testing is time consuming and expensive, it is important to perform adequate testing within a minimal amount of time. Generally, testing is done by sampling a set of kerfs to obtain an overall HOL measurement. For customized circuits, such as application specific integrated circuits (ASIC) testing by sampling does not provide an accurate assessment of device parameters within each die of the wafer. Maintaining device parameters within specifications is critical for improving yield and ensuring that customer requirements and delivery expectations are met.

BRIEF SUMMARY OF THE INVENTION

Based on the issues identified above, what is needed is a means for accurately testing customized circuitry so that adequate feedback can be relayed to the manufacturing line to ensure the highest possible yields. It is a further requirement that the testing process does not take an exceptional amount of time, nor take excessive silicon real estate and therefore, affect cost. The testing process must be adaptable to meet specific testing requirements without providing unnecessary test structure overhead.

The present invention is a system and method of integrating a test structure into a physical integrated circuit design (i.e. into a netlist), typically in the backfill. The test structure and corresponding system provides accurate electrical and physical measurements of the circuit and its devices on an associated die. Test structure100is shown inFIG. 1and includes a logic controller110having a decoder for activating one or more device under test (DUT) structures170and180, a decode level translator (DLT)120, which provides a required logic level or required voltage to one or more DUT structures170or180, and a protection circuit which isolates the integrated circuit when the test system is inactive.

Test structure100may operate in either a single or dual supply mode. In the single supply mode, during wafer final test (WFT) and/or module final test (MFT), the current (Ion) measurement for each DUT170and/or180is calculated and recorded. In dual supply mode, a control block190controls the voltage to a DUT170and/or180gate, for example, as well as provides power to the DUT170and/or180source and/or drain. Measurements for threshold voltage (Vt), Ion, and effective current (Ieff) for each DUT170and/or180are then calculated and recorded.

Test structure100is a device performance monitor within application specific integrated circuits (ASIC). The macro represents all device types and design points used on an ASIC chip. Test structure100may be, for example, integrated with the existing electronic chip identification macro (ECID: used at IBM) or placed near a performance screen ring oscillator (PSRO), placed as a standalone macro, or placed non-contiguously such that control block190is placed in a physically separate location on a chip from DUTs170or180.

Test structure100provides several unique, user-defined device tests. All tests include measuring and recording applicable parameters of on-chip devices such as average Ion, Vt, and Ieffpertaining to an array of FETs. The tests account for spatial variations. Each DUT170and/or180in this specification refers to but is not limited to nFET or pFET devices. DUTs170and/or180may also be wires, resistors, capacitors, inductors, and other circuit components. Additionally, across chip variation (ACV) data can be extracted and analyzed by placing multiple test structures100on a single chip.

During release checking, all device types and design points on a particular IC chip are determined and matched with those present in a test structure100. If test structure100contains DUTs170and/or180that are not part of the IC design, then that test structure100will not be included in the design. Test structure100must not drive unique mask requirements. Only test structures100which are compatible with the IC will be chosen. Information describing what is both on the chip and in test structure100will be relayed to the manufacturing and test engineers.

Test structures100may be integrated into the design and coupled to existing ECID macros, which contain at least one fatwire I/O with very low-resistance requirements (<10 Ohms guaranteed). The fatwire I/O is connected to a Precision Measurement Unit (PMU) at test which will be used for accurate voltage force and current measure activity.

Determination for the number, type, location, and routing of required test structures100per chip is defined during the chip design process. Customer directives, internal rules, and historical data provide requirements for selection, synthesis, and placement of the test structures100. These requirements include, but are not limited to: available backfill, distance from the fatwire I/O, proximity to critical logic macros, e.g. PSROs used to guarantee product performance, continuity of test structures100, desired test data for analysis, and minimum distances between test structures100for the design. One of ordinary skill in the art can appreciate the many requirements and specifications that must be maintained and adhered to in the design and manufacture of ICs.

The process of integrating test structures100into a customer design (e.g. netlist) includes identifying discrete elements within the design and comparing a library of test structures100, each having varying DUTs170and180. Test structures100which match various discrete elements are stored in a list. The list is further prioritized according to requirements including but not limited to: customer directives, internal rules, and historical data. A data structure comprising available fatwire I/O and other elements along with possible placement blocks (e.g. areas) on the die for test structures100is used to process and assign the prioritized list of test structures100to optimum elements and placement areas to the extent possible. Test structures100which are placeable, are synthesized in the netlist and placed using place and route tools. Final design checking is performed to ensure compliance with DFM rules. Test structures100that cause failures are removed from the netlist, the netlist resynthesized and checked. The process iterates until all DFM tests pass. The final netlist is recorded as a data structure, which is then released to manufacturing (i.e. tape-out) for example, as a GDSII file.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1shows a test structure100of the present invention. Test structure100includes a control block190, which further includes logic control110, a group of decode level translators (DLT)120a-d(four DLTs are shown in this example), a pFET SPI circuit140coupled to an SPI control circuit130, and an nFET SPI circuit150coupled to SPI control circuit160. Test structure100further includes a DUT170, which represents one device type (in this example, an array of pFETs) and a DUT180, which represents a second device type (in this example, an array of nFETs). Each of DUTs170and180are coupled to control block190.

In operation, control block190exercises corresponding DUTs170and/or180and provides resulting test data to a test apparatus (not shown). Each element of test structure100is further discussed in the following figures.

FIG. 2shows logic control110, which includes a control signal C1coupled to a latch L1, which is further connected to a pad S1of a decoder210. Control signal C2is coupled to a latch L2, the output of which is coupled to a pad S0of decoder210. An enable signal, EN, is coupled to a third latch L3, the output of which is coupled to a pad EN of decoder210. Decoder210further comprises a series of outputs D0-D3, which are each coupled to DLT120a-drespectively.

Logic control110enables each DUT170or180to be activated individually for test. Decoder210is shown inFIG. 2as a 2:4 decoder for illustrative purposes but need not be limited to a 2:4 decoder. Since DUT170and DUT180experiments are separated, decoder210behaves as a 2 to 8 decoder, controlling DUT170and DUT180with each decoder output. Typical decode sizes will be 4:16 or 5:32, which will achieve capability of controlling 32 to 64 DUTs. If EN is low, decoder210outputs D0-D3will be low, which ensures all DUT170and DUT180gates are off.

FIG. 3shows a detailed diagram of DLT120a. DLT120ais exemplary of any of DLT120b-dand thus will serve to explain DLT120functionality and structure by way of example. DLT120aincludes an input signal, I, from output D3of decoder210, a pFET level translator310, and an nFET level translator320. pFET level translator310, further includes an input pad, I, an output pad, P, which is coupled to DUT170, a second input pad, HP, and a third input pad, LP. nFET level translator320includes an input pad, I, which activates/deactivates DLT120a, an output pad, N, which is coupled to DUT180, a second input pad, HN, and a third input pad, LN. pFET level translator310and nFET level translator320are shown in detail inFIGS. 4 and 5respectively.

In operation, input I to DLT120acomes from decoder210. When the output signal D3from decoder210, which is connected to the I pin of DLT120a, is high, the P and N outputs of DLT120aare active (i.e. N=1, and P=0), which turns on the associated DUT170gates, as well as the associated DUT180gates. The supply voltage inputs to DLT120aare shown in Table 1 below.

TABLE 1values of HP, LP, HN and LN for single and dual supply modesSingleDualHPS0PS0PLPGNDS1HNS0NS1LNGNDGND

In Table 1, “single” supply represents DUT170and DUT180input from a single voltage source (S0P, S0N) which will drive simple logic 1's and 0's to DUT170and DUT180respectively.

In Table 1, “dual” represents input from two distinct voltage supplies where HN on nFET level translator320receives the signal S1and LP on pFET level translator310also receives the signal S1.

In dual supply mode, S1is sent to the gates of DUT170and180from outputs P and N respectively. S1can be swept to determine the switching voltage (Vth) and FET current (ION) of DUT170and DUT180.

In general, DLT120enables logic control110to control DUTs170and180residing in different voltage realms. DLT120provides a means for communication between two voltage domains including Vdd, supplied to control logic110, and test structure “Supply/VDD/GND” used to generate S0for DLT120. The purpose of DLT120is to provide accurate logic levels and/or analog gate voltages to DUT170and DUT180in order to perform device level testing. In the case of BEOL characterization, either nFET level translator320or pFET level translator310will be used, depending on the FET type used to control DUT120. Equalizing DUT experiments (equal n and p experiments) optimize use of the test structure.

FIG. 4shows a detailed schematic diagram of pFET level translator310which includes pFETs P1-P5, nFETs N1-N2, and a first inverter whose input is I. This inverter is serially connected to a second S0P powered inverter. HP and LP are driven according to the type of test, as shown in Table 1. The output P is sent to DUT170.

The input to pFET level translator310is inverted by the first inverter to achieve an opposite output state when enabled, which is required by pFETs associated with DUT170. In a single supply application, e.g. applying S0P to HP, the output of pFET level translator310has the opposite logic level with respect to the input.

In a dual supply application, S1is applied to LP. GND is replaced by S1to allow voltage sweeping through a pass-gate, shown inFIG. 4as FETs N2and P5, to DUT170gates.

FIG. 5shows a detailed schematic diagram of nFET level translator320which includes pFETs P1-P5, nFETs N1-N2, an inverter whose input is I, and is powered by either S0N or S1. HN and LN are driven according to the type of test, as shown in Table 1. The output N is sent to DUT180.

nFET level translator320has an input which is non-inverting. The power supply for nFET level translator320may originate from a derivative of the entire test structure power supply (S0N), or from a separate power supply (S1). S1controls analog gate voltages for DUT180.

FIG. 6is a schematic block diagram of SPI circuit140which includes a protect circuit610, a supply circuit620, and an isolation circuit630. Isolation circuit630further includes level translator640having a supply/VDD/GND power supply, an enable input I, and an output P, which is coupled to a pFET of supply circuit620. A detailed schematic diagram of isolation circuit630is shown inFIG. 7and described below.

Level translator640ofFIG. 7includes pFETs P1-P4, nFETs N1-N3, and a Vdd powered inverter which has input I. Isolation circuit630electrically isolates DUT170so that the actual ASIC circuitry is not affected during test, nor is it affected by any leakage current from DUT170while the test structure is not in operation. Level translator640routes the supply voltage (Supply/VDD/GND) directly to the corresponding gate of the supply pFET in supply circuit620ofFIG. 6.

Since the test structure separates nFET and pFET DUTs, it supplies each with a dedicated SPI structure. Only one of SPI circuits140or150is activated at a time. This is accomplished by selecting the appropriate SPI circuit140or150to activate using either SPI control circuit130or SPI control circuit160respectively. AlthoughFIG. 6shows SPI circuit140, it is meant to be exemplary of any SPI circuit, including SPI circuit150and therefore SPI circuit150will not be discussed in further detail.

FIG. 8ashows a logic diagram of SPI control circuit130andFIG. 8bshows a logic diagram of SPI control circuit160. SPI control circuit130further includes an Enable signal, an Efuse_prog signal, a selPfet signal, and a NAND gate having inputs from Enable and selPfet, which comes from a latch on the chip (not shown). The Enable, and Efuse_prog signal are further coupled to protect circuit610. The NAND output directly feeds the I input of SPI circuit140. By choosing only one SPI circuit at a time (using selPfet, and Enable), current through unused SPI circuit150is gated to reduce incidental leakage. Efuse_prog exists to protect non-test structure ASIC circuits (not shown). Since the test structure shares the Supply/VDD/GND pin with ASIC circuits, the existing Efuse_prog signal is used to isolate the test structure from other ASIC operations and vise versa.

The supply voltage is sourced through supply circuit620. Supply circuit620includes a large supply pFET which sends an output signal to DUT170. The gate of the supply pFET is coupled to the output of isolation circuit630, the source is connected to Supply/VDD/GND, and the drain is connected to the output of protect circuit610. The supply pFET is sufficiently large to ensure it will have a minimum voltage drop during test structure measurements (<50 mV), but robust enough to handle high voltages, which may be at or above 3.0V.

SPI protect circuit610protects the supply pFET of supply circuit620from excessive source to drain, and gate to drain potential differences when high voltages are applied to Supply/VDD/GND (fatwire I/O). During high voltage applications, Supply=3.0 v and the test structure is inactive (off), i.e. all DUTs170and180are turned off. When Enable=0 and Efuse_prog=1, VDD is forced through protect circuit610and onto the drain of the supply pFET of supply circuit620. The largest potential difference across the supply pFET is guaranteed to never be larger than Supply minus VDD. Simulation was completed to verify this voltage level is not damaging to the supply pFET.

In the single supply mode of operation either during wafer or module final test (WFT, MFT), a tester (not shown) calculates the current by measuring the background current (IBG) and DUT current (IMEAS) for each of DUT170and DUT180. IONis equal to the difference between IMEASand IBG(i.e. ION=IMEAS−IBG). The tester records the IONdata for both DUT170and DUT180. Table 2 shows a truth table for the Single Mode of operation used for controlling the test structure DUTs.

TABLE 2Example truth table for single supply modeInputSingle ModeselPfetC1C2S0PS0NP0P1P2P3N0N1N2N3000S0P0GNDS0S0S0PS0NGNDGNDGND001S0P0S0GNDS0S0PGNDS0NGNDGND010S0P0S0S0GNDS0PGNDGNDS0NGND011S0P0S0S0S0GNDGNDGNDGNDS0N1000S0NGNDS0S0S0PS0NGNDGNDGND1010S0NS0GNDS0S0PGNDS0NGNDGND1100S0NS0S0GNDS0PGNDGNDS0NGND1110S0NS0S0S0GNDGNDGNDGNDS0N

The test structure is also configurable to separately control the DUT170and180gate voltages. Dual supply mode testing enables threshold voltage, Vt, measurement capability, in addition to IONmeasurement capability. In dual supply mode, effective current (Ieff) can be calculated. Ieffis a better indicator of device performance than IONalone. To implement dual supply mode a dedicated pad, S1, must be wired out. S1is shown inFIG. 3as LN and HP respectively.

Table 3 shows an example truth table for dual supply mode.

Test structure100may be placed in various locations within an ASIC design to test different areas of the same chip. Alternative DUT170/180structures may also be incorporated into the design such that each test structure is able to test a particular DUT structure in proximity to it. A single test structure100may also be designed to test multiple varieties of DUT170and/or180structures, such as wires, resistors, capacitors, inductors, etc., within a specific chip location. The following figures provide examples of integrating test structure100into a circuit design. The following examples are shown for illustrative purposes and are not intended to limit the invention to only those configurations illustrated. One of ordinary skill in the art will appreciate other configurations within the scope and spirit of the present invention.

FIG. 9shows a system900for integrating test structure100into an integrated circuit netlist910. System900includes a test structure library920, which generates a matching test structures list915according to integrated circuit netlist910. A priority specifications930database provides prioritization information for generating a prioritized matching test structures list925from matching test structures list915. An elements and placement blocks940database provides information to generate a test structure assignment list935from prioritized matching test structures list925. An unused test structures945database receives all test structures100that are in prioritized matching test structures list925but not test structure assignment list935. System900further includes a placement/design rules955database to finalize placement and integration of test structures100resulting in a data structure950used for manufacturing the IC. Data structure950may be a GDSII file, for example. Data structure950comprises the at least one prioritized matching test structure100coupled to the at least one element of integrated circuit netlist910.

FIG. 10shows a method1000of operating system900to integrate test structures100into netlist910. In step1010, method1000identifies discrete elements or devices in customer netlist910which may be potential candidates for testing.

In step1020, method1000compares the discrete devices identified in step1010with test structures100comprised in test structure library920and creates matching test structures list915, which comprises a list of test structures100which contain DUTs170and/or DUTs180, wherein DUTs170and/or DUTs180match at least one of the discrete devices in netlist910.

In step1030, method1000creates prioritized matching test structures list925by prioritizing matching test structures list915. Method1000uses prioritization algorithms and prioritization data stored in priority specifications930database (seeFIG. 11for details) to prioritize test structures100located in matching test structures list915and generates prioritized matching test structures list925. The highest priority discrete devices, elements, cores, IP, macros, etc. in netlist910will be the first to have an assigned test structure100and the corresponding test structures100are prioritized accordingly.

In step1040, method1000assigns test structures100from prioritized matching test structures list925(beginning with the highest priority test structures100) to elements (e.g. fat wires) of netlist910as provided by elements and placement blocks940database. Step1040continues until either 1. there are no more elements of netlist910capable of being assigned a test structure100, 2. there are no more test structures100to assign, or 3. there is no physical space available (placement block) to insert another test structure100into netlist910. Step1040is described in detail inFIGS. 19-22.

In step1050, method1000populates unused test structures945database with test structures100which were listed in prioritized matching test structure list925, but which were not assigned to a design element in step1040.

In step1060, method1000integrates selected test structures100into netlist910using placement/design rules955and synthesis tools to generate data structure950. Several examples of test structure100placement into customer netlist910are shown inFIGS. 12-18.

In step1070, method1000performs final checking algorithms on data structure950to ensure design for manufacturability requirements are met (e.g. release process rules, DRC, LVS, wire load checking, etc.). If any design checking rules fail, method1000makes the necessary placement and routing changes to ensure compliance with specifications such as, DFM rules, product specifications, functional design requirements. If no solution is found for a particular test structure100, it is removed from data structure950and placed in unused test structures945.

In step1090, method1000removes test structure100which is causing failure(s) and proceeds to step1050. Method1000iterates until all checking algorithms pass.

FIG. 11shows a detailed example diagram of prioritization step1030of method1000. Test structure matching list915shows a list of matching test structures: TS1, TS2, TS3, TS10, TS25, and TS50which correspond to devices and/or elements in netlist910. A plurality of prioritization algorithms1100, prioritize list915to generate prioritized matching test structures list925. Prioritization algorithms1100use data input from priority specifications930. Priority specifications930includes rules and directives1140, which further includes, for example, internal rules1110and customer directives1120. Priority specifications930further includes historical data1130. One of skill in the art would appreciate that there are many other data points which could be used to prioritize list915. In this example, prioritized matching test structures list925shows test structures100prioritized in the following order: TS3, TS50, TS2, TS1, TS10, and TS25. Therefore, TS3is the highest priority test structure100in this example and will be the first to be placed into netlist910in step1040by method1000. Following the placement of TS3is TS50, and so on.

FIGS. 12-17show examples of test structure100placements within design950.FIGS. 12-17are only a few examples of placement configurations and should not be construed as limitations. As can be appreciated by one of ordinary skill in the art, test structures100may be placed anywhere in an integrated circuit design such that all design rules are satisfied and the purpose of test structure100is fulfilled. Additionally, the types of measurements desired will dictate the optimum placement or placements within an integrated circuit design.

FIG. 12shows an example placement configuration that provides routing optimization by remaining within wiring limitations of a power supply, effectively minimizing IR drop through constraining metal routing distances. This is an example placement configuration in which internal rules and directives1140dictates that test structures100a, b, andcneed to be coupled to elements1200a,1200b, and1200crespectively such that metal routing distances are minimized, thus minimizing IR drop. Test structures100are coupled to elements1200at the supply/Vdd/GND rail, as shown inFIG. 1.

FIG. 13shows a placement example where internal rules and directives1140dictates a fanout configuration for placement such that test structures100aand100cmust be coupled to element1200aand test structures100band100dmust be coupled to element1200b. In this example, the fanout optimization maintains leakage limits, capacitive loading and balance loading for customer chip1300.

FIG. 14shows a placement configuration example where internal rules and directives1140dictates a proximity requirement for a plurality of macros1410a-dsuch that each of test structures100a-dis located near to its respective macro1410. For example, macro1410may be a PSRO. This configuration is used to validate, for example, screening methodology and AC to DC correlation.

FIG. 15shows a placement configuration example where internal rules and directives1140dictates a logic1500must comprise DUTs170a-cand DUTs180a-dand further that control block190may be placed either within logic1500or outside of logic1500.FIG. 15is further an example of a non-contiguous test structure100.

FIG. 16is a configuration example of a placement for both a contiguous and non-contiguous test structure100, where DUTs170a-cand DUTs180a-dmay be placed both within and/or without a logic1600and control block190must be placed in proximity to logic1600for controlling DUTs170a-cand DUTs180a-d. Test structure100ais a contiguous test structure which must be placed in proximity to element1620. Element1620may be a kerf, for example.

FIG. 17shows a placement configuration example where internal rules and directives1140dictates a particular DUT170must be placed within a logic block1700. Control block190has a proximity requirement in order to control DUT170.

FIG. 18shows an example of a netlist910layout in combination with elements and placement blocks940. Netlist910layout includes elements1200a,1200b, and1200c, a plurality of placement blocks1800, and a plurality of logic macros1810-1890. Placement blocks1800are areas of available silicon that are large enough to hold contiguous and/or non-contiguous test structures100. Test structures100from prioritized matching test structures list925are assigned to one or more of placement blocks1800in step1040of method1000. A resulting placement options table2300is shown inFIG. 23.

Other example configurations, which are not shown include: placing enough test structures100in a customer chip such that the special placement of the test structures100provides systematic cross chip variations measurements. Placing a test structure100near a macro having critical timing requirements allows verification of ASST testing results and verification of AC testing results. Placing DUT170and/or DUT180within a macro's boundaries on a customer chip provides a controlled physical environment including similar backfill and is consistent with wiring density and device geometries. Yet another placement example includes placing a test structure100near a kerf and another test structure100near a macro to quantify DC offset from: chip to kerf, kerf to macro, and chip to macro.

An important process improvement provided by the present invention is that the parametric data collected from the test structures during test is fed back into the manufacturing line to adjust the responsible process steps necessary to bring the chip parameters into compliance with specifications. For example, a key process parameter that has heretofore gone unmonitored is N to P skew, which is a measurement of Nfet to Pfet of a deviation from their nominal threshold voltages. By using this invention the Nfet and Pfet skew can be adjusted to the correct the skew variation between the devices by changing one of the processes, such as the implant process, in the line to correct the skew.

FIG. 19is a detailed description of step1040of method1000. In step1910, method1000determines whether all test structures100in prioritized test structures list925have been assigned a placement block1800. If yes method1000proceeds to step1940, if no, method1000proceeds to step1920.

In step1930method1000analyzes each element1200and assigns selected test structure100to appropriate placement blocks1800for each element1200. For example, method1000analyzes element1200aand assigns placement blocks1800a,1800b, and1800ias optimal placement areas for TS3and records the data in placement options table2300(seeFIG. 23). Method1000continues to element1200band assigns placement blocks1800b,1800c′, and1800d′ to TS3in placement options table2300. Whereby1800bis an optimal placement block and1800c′ and1800d′ are best-fit placement blocks. Method1000proceeds to analyzing element1200c. It assigns placement blocks1800k,1800f,1800g′ to TS3in placement options table2300, whereby1800kand1800fare optimal placement blocks and1800g′ is a best-fit placement block. Since there are no more elements1200, method1000returns to step1910.

In step1940, method1000generates a test structure assignment list935and proceeds to step1950. Step1940is explained in further detail inFIG. 24.

FIG. 20is an alternate step1040. In step1910amethod1000determines whether all elements1200have been assigned. If yes method1000proceeds to step1940, if no, method1000proceeds to step1920a.

In step1920amethod1000chooses the next unassigned element1200and proceeds to step1930a.

FIG. 21shows a flow diagram of the details of steps1930or1930a. In step2110, method1000determines whether the selected test structure is contiguous. If yes, method1000proceeds to step2200. If no, method1000proceeds to step2120.

In step2120, method1000determines whether selected test structure100has a proximity requirement (typically established in customer directives1120) to a particular element, logic block, core, macro, etc. If yes, method1000proceeds to step2140, if no, method1000proceeds to step2130.

In step2130, method1000analyzes each placement block1800to determine whether it satisfies size and route-ability requirements for the selected test structure100and design element1200; if yes, method1000labels the selected placement block1800as a possible placement block1800option in placement options table2300. Method1000returns to step1910.

In step2140, method1000analyzes each placement block1800to determine whether it satisfies proximity, size, and route-ability requirements for the selected test structure100and design element1200; if yes, method1000labels the selected placement block1800as an optimal placement block1800option in placement options table2300. Method1000returns to step1910.

FIG. 22is a flow diagram of step2200, which assigns placement block1800options to non-contiguous test structures100. In step2210method1000determines whether control block190of the selected test structure100have a proximity requirement; if yes, method1000proceeds to step2230, if no method1000proceeds to step2220.

In step2220, method1000analyzes each placement block1800to determine whether it satisfies size and routeability requirements for selected test structure control block190and selected element1200; if so, label selected placement block1800as a possible placement block1800′ in placement options table2300. When all placement blocks1800have been analyzed, method1000proceeds to decision step2240.

In step2230, for each placement block1800, method1000analyzes whether it satisfies proximity, size, and route-ability requirements for selected test structure control block190and selected element1200; if so, label selected placement block1800as optimal placement block1800in placement options table2300. When all placement blocks1800have been analyzed, method1000proceeds to decision step2235.

In step2235method1000determines whether an optimal placement block1800was found for the selected control block190of test structure100; if yes method1000proceeds to step2235, if no, method1000proceeds to step2220.

In step2240, method1000determines whether DUTs170and/or180associated with the selected test structure100have proximity requirements; if yes, method1000proceeds to step2250, if no, method1000proceeds to step2260.

In step2250, for each placement block1800, method1000analyzes whether it satisfies proximity, size, and routeability requirements for selected test structure100DUTs170and/or180and selected element1200; if so, label selected placement block1800as optimal placement block1800in placement options table2300. When all placement blocks1800have been analyzed, method1000proceeds to step2255.

In step2255method1000determines whether an optimal placement block1800was found for the selected DUTs170and/or180of test structure100; if yes method1000returns to step1910, if no, method1000proceeds to step2260.

In step2260, method1000analyzes each placement block1800to determine whether it satisfies size and route-ability requirements for selected DUTs170and/or180and selected element1200; if so, label selected placement block1800as a best fit possible placement block1800′ in placement options table2300. When all placement blocks1800have been analyzed, method1000returns to step1910.

FIG. 23shows an example placement options table2300. For each applicable test structure100and each applicable element1200, the optimal placement blocks1800and best fit placement blocks1800′ are recorded in placement options table2300.

FIG. 24shows a flow diagram of a detail of step1940. In decision step2410, method1000determines whether all contiguous and non-contiguous test structures100can be assigned to optimal placement blocks1800; if yes, method1000proceeds to step2420, if no, method1000proceeds to step2430.

In step2430, method1000determines whether all contiguous and non-contiguous test structures be assigned to placement blocks1800if test structures100are allowed to share common optimal placement blocks1800. If yes, method1000proceeds to step2450, if no, method1000proceeds to step2440.

In step2440, method1000assigns as many contiguous and non-contiguous test structures100as possible into their respective optimal placement blocks1800starting with the highest priority test structures100. All remaining test structures100are then assigned to their respective best-fit placement blocks1800′. Method1000proceeds to step2460.

In step2460, method1000determines whether all test structures100are assigned to at least one placement block1800or1800′. If yes, method1000proceeds to step2470, if no, method1000proceeds to step1050to store non-placeable test structures100into unused test structures945database.

In step2420, method1000generates test structure assignment list935using the corresponding optimal placement blocks1800and proceeds to step1060.

In step2450, method1000generates test structure assignment list935using the corresponding optimal placement blocks1800and shared placement blocks1800. Method1000proceeds to step1060.

In step2470, method1000generates test structure assignment list935using the optimal placements blocks1800, shared placement blocks1800, and best-fit placement blocks1800′. Method1000proceeds to step1060.

FIG. 25is an example test structure assignment list935for elements1200a-c, Test structures TS3, TS50, DUTs170a-d, TS2, and TS1. In this example TS1could not be placed and therefore will be added to unused test structure945database. TS2will share placement block1800bwith TS3, and DUT170dwill be tied off (e.g. FET(s) that are in the off position or some other low leakage configuration).

FIG. 26illustrates a block diagram of a general-purpose computer system which can be used to implement the system and method described herein. The system and method may be coded as a set of instructions on removable or hard media for use by general-purpose computer.FIG. 26is a schematic block diagram of a general-purpose computer for practicing the present invention.FIG. 26shows a computer system2600, which has at least one microprocessor or central processing unit (CPU)2605. CPU2605is interconnected via a system bus2620to a random access memory (RAM)2610, a read-only memory (ROM)2615, an input/output (I/O) adapter2630for connecting a removable and/or program storage device2655and a mass data and/or program storage device2650, a user interface2635for connecting a keyboard2665and a mouse2660, a port adapter2625for connecting a data port2645and a display adapter2640for connecting a display device2670. ROM2615contains the basic operating system for computer system2600. Examples of removable data and/or program storage device2655include magnetic media such as floppy drives, tape drives, portable flash drives, zip drives, and optical media such as CD ROM or DVD drives. Examples of mass data and/or program storage device2650include hard disk drives and non-volatile memory such as flash memory. In addition to keyboard2665and mouse2660, other user input devices such as trackballs, writing tablets, pressure pads, microphones, light pens and position-sensing screen displays may be connected to user interface2635. Examples of display device2670include cathode-ray tubes (CRT) and liquid crystal displays (LCD).

A computer program may be created by one of skill in the art and stored in computer system2600or a data and/or removable program storage device2665to simplify the practicing of this invention. In operation, information for the computer program created to run the present invention is loaded on the appropriate removable data and/or program storage device2655, fed through data port2645or entered using keyboard2665. A user controls the program by manipulating functions performed by the computer program and providing other data inputs via any of the above mentioned data input means. Display device2670provides a means for the user to accurately control the computer program and perform the desired tasks described herein.

The above description and drawings are only to be considered illustrative of exemplary embodiments, which achieve the features and advantages of the invention. It should be appreciated by one of ordinary skill in the art that modification and substitutions to specific layout designs, systems for performing the tests and analysis, and the devices themselves can be made without departing from the spirit and scope of the invention. Accordingly, the invention is not to be considered as being limited by the foregoing description and drawings.