A delay locked loop (DLL) includes a delay unit configured to delay an input clock signal by a specified amount to produce a delayed clock signal. A phase detector receives as input the input clock signal and the delayed clock signal and outputs a signal proportional to the phase difference between the input clock signal and the delayed clock signal to provide a control voltage for adjusting the delay to the specified amount. A pulse swallower removes a pulse from the input clock signal or from the delayed clock signal to reverse the direction of the control signal.

TECHNICAL FIELD

The invention relates to the field of clock generation and more particularly to delay-locked loops for clock generation.

BACKGROUND

FIG. 1shows a delay-locked loop (DLL)101of the prior art (see U.S. Pat. No. 6,239,634 to McDonagh, for example). The DLL101comprises a phase frequency detector (PFD)103, a charge pump105, a loop filter (loop capacitor)107and a voltage controlled delay line (VCDL)109. The VCDL109can include n stages, each stage contributing a certain amount of delay to the overall delay. The DLL101receives a reference clock signal (input clock signal)111and generates an output clock signal113that has its phase delayed by a fraction of a period of the reference clock signal111.

The PFD103receives, on its input terminals, the reference clock signal111and the output clock signal113. In a conventional arrangement, the PFD103is a rising edge detector that compares the rising edges of the two clock signals. Based on this comparison, the PFD103generates one of three states. If the phases of the two signals differ by the desired amount, then the loop is “locked”. Neither the UP nor the DOWN signal is asserted and the delay of the VCDL remains the same. If the reference clock signal111leads the output clock signal113by more than the desired amount, then the delay of the DLL101is too much. If the reference clock signal111lags the output clock signal113by more than the desired amount, then the delay of the DLL101is too little. The detector103then outputs an UP or a DOWN signal (depending on the particular circuit design) proportional to the phase difference between the reference clock signal111and the output clock signal113. The UP and DOWN signals typically take the form of pulses having a width or duration corresponding to the timing difference between the rising edges of the reference and output clock signals. The UP and DOWN signals are output to the charge pump105through two separate lines.

The charge pump105generates a current Icp115that controls the voltage of the loop filter107and thereby the delay of the VCDL109. The current115is dependent on the signal output by the PFD103. If the charge pump105receives an UP signal from the PFD103, Icp115is increased. If the charge pump105receives a DOWN signal from the PFD103, Icp115is decreased. If neither an UP nor a DOWN signal is received, indicating that the clock signals have the desired phase difference, the charge pump105does not adjust Icp115.

The loop filter107is positioned between the charge pump105and the VCDL109. An UP signal from the PFD103results in an increase of the voltage Vloop117on the loop filter107, while a DOWN signal from the PFD103results in a decrease of the voltage Vloop117on the loop filter107. Vloop117is applied to the VCDL109. The VCDL109can be comprised of a voltage-to-current converter, which then supplies a current to a current controlled delay line to control the delay. The loop filter107also removes out-of-band, interfering signals before application of Vloop117to the VCDL109. A common configuration for the loop filter107in the DLL101is a simple single-pole, low-pass filter that can be realized with a single capacitor.

The output clock signal113is looped back to the PFD103to facilitate the delay-locked loop operation. The DLL101thus compares the reference clock signal111phase to the output clock signal113phase and adjusts the detected phase difference between the two to a desired amount by adjusting the delay of the VCDL109.

The prior-art DLL101faces lock problems. In order to prevent a false lock to a zero or incorrect phase, the initial state of the DLL101must be well defined so that the leading edge of the output clock signal113is delayed between ½ a period and 1½ periods. Additionally, a reset signal must be applied if the input frequency is changed.

FIG. 4illustrates the lock-to-zero problem of the prior art. As can be seen, the fed-back output clock signal113has a phase, which is delayed by a small amount relative to the reference clock signal111. The PFD103outputs an up signal403to the charge pump105, increasing the voltage Vloop117in order to decrease the delay of the fed-back output clock signal113. However, the Vloop117cannot increase enough and the DLL201becomes stuck, or locked-to-zero trying to achieve the zero phase delay.

FIG. 6illustrates the false locking of the prior-art DLL. Due to the false locking, the reference clock signal111has a phase, which is delayed relative to fed-back output clock signal113. The PFD103outputs a down signal503to the charge pump105, decreasing the voltage Vloop117in order to increase the delay of the fed-back output clock signal113.

McDonagh provides a circuit providing correct start-up and locking of the DLL circuit, but still requires that the DLL be biased to the smallest delay value. If the reference clock signal frequency is changed, then the DLL needs to be reset.

It would be desirable to have a DLL that would, without being reset, achieve correct startup and lock to the correct phase even if the reference clock signal frequency is changed.

SUMMARY OF THE INVENTION

The present invention provides a DLL that does not require reset to achieve correct startup and that locks to the correct phase even when the reference frequency is changed. The present invention achieves these features by setting the boundaries at both sides of the VCDL, and by using a pulse swallow technique to reverse the direction of the PFD.

In a preferred embodiment, the invention is for a delay locked loop (DLL) including a delay unit configured to delay an input clock signal by a specified amount to produce a delayed clock signal. A phase detector receives as input the input clock signal and the delayed clock signal and outputs a signal proportional to the phase difference between the input clock signal and the delayed clock signal to provide a control voltage for adjusting the delay to the specified amount. A pulse swallower removes a pulse from the input clock signal or from the delayed clock signal to reverse the direction of the control signal.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

A DLL201of the present invention is shown inFIG. 2. The prior art DLL101ofFIG. 1is modified by adding three additional circuit blocks. These blocks are a lock to zero detector203, a false lock detector205and a pulse swallower207.

In the examples, it is assumed that increasing the voltage Vloop117decreases the delay of the VCDL109and decreasing the voltage Vloop117increases the delay of the VCDL109. However, when other circuits are used for the VCDL the opposite can be true.

The lock to zero detector203detects “lock to zero” error. In the prior-art circuit101of theFIG. 1, the “lock to zero” error can occur if the delay of the output clock signal113is less than ½ period (π radians) relative to the reference clock signal111when the PFD103first detects the reference clock signal111, following reset. In this case, the DLL101will keep decreasing the delay of the VCDL109in order to achieve lock, and the DLL101will attempt to lock to zero delay. This is not possible to achieve since it is impossible to have no delay in a circuit, so the DLL101will not be able to lock (thus the “lock to zero” error).

The lock to zero detector203functions as a comparator (seeFIG. 3). It compares Vloop117to a reference voltage Vref209. If Vloop>Vref then a lock_to_zero_o signal (active High)211is generated, which is sent to the pulse swallower207.

The false lock detector205prevents the DLL201from locking to the wrong phase (e.g., 4π, 6π, etc.). False locking of the DLL101ofFIG. 1can occur if the delay in the VCDL109is too great. The false lock detector205uses the plurality of phases213from the VCDL109to determine whether the DLL101is locked to a false phase. If such a false lock occurs, a false_lock_o signal215is generated and sent to the pulse swallower207.

The pulse swallower207functions to remove a pulse from the reference clock signal111, if the lock_to_zero_o signal211goes to high (indicating that Vloop117has increased too much). By doing so, the direction of the PFD103output is reversed from an up signal to a down signal to decrease the delay of the VCDL109.

FIG. 5shows the effect of the present invention when the lock_to_zero_o signal211goes to high (indicating that Vloop117has increased too much). In response to the lock_to_zero_o signal211going to high, the pulse swallower207removes a pulse from the reference clock signal111. By removing the pulse, the fed-back output clock signal113appears to lead the reference clock signal111and the direction of the PFD103up signal403is reversed to become a PFD103down signal503having a width from a leading edge of the reference clock signal111to a leading edge of the output clock signal113. Thus, the Vloop117is decreased to increase the delay and prevent the DLL201from becoming stuck.

The pulse swallower207also functions to remove a pulse from the output clock signal113if the false_lock_o signal215goes high (indicating that the DLL101is locked to a false phase). By doing so, the direction of the PFD103output is reversed from a down signal to an up signal to increase the delay of the VCDL109.

FIG. 7shows the effect of the present invention when the false_lock_o signal215goes to high. In response to the false_lock_o signal215going to high, the pulse swallower207removes a pulse from the fed-back output clock signal113. By removing the pulse, the direction of the PFD103down signal503is reversed to become a PFD103up signal403having a width from a leading edge of the output clock signal113to a leading edge of the reference clock signal111. Thus, the Vloop117is increased to decrease the delay of the DLL201to prevent locking on the wrong phase.

With the help of these circuits203,205and207, the DLL201initial condition can be set at any point. Also, the reference clock signal can be changed without resetting the DLL201.

The present invention may be embodied in other forms without departing from its spirit and scope. The embodiments described above are therefore illustrative and not restrictive, since the scope of the invention is determined by the appended claims rather then by the foregoing description, and all changes that fall within the meaning and range of equivalency of the claims are to be embraced within their scope.