Array substrate with additional electrode formed above gate line, manufacturing method thereof and liquid crystal display

Embodiments of the invention disclose an array substrate and a manufacturing method thereof and a liquid crystal display. In the array substrate, an additional electrode is formed above a gate line, the additional electrode and the gate line are spaced from each other by a gate insulation layer, and the additional electrode is connected electrically with the common electrode line; pixel electrode extends to over the additional electrode and is overlapped with the additional electrode, the overlapped portion of the pixel electrode and both the additional electrode and the common electrode line forms a storage capacitor. The liquid crystal display according to the embodiment of the invention comprises the above array substrate.

TECHNICAL FIELD

Embodiments of the present invention relate to an array substrate, a manufacturing method thereof and a liquid crystal display.

BACKGROUND

Liquid crystal displays are conventional plat plate displays at present; the thin film transistor liquid crystal displays (TFT-LCDs) are popular products among liquid crystal displays. A liquid crystal panel is an important component in a TFT-LCD, which generally comprises an array substrate and a color filter substrate which are assembled together, with a liquid crystal layer filled therebetween.

FIG. 1Ais a schematic partial top structure view of an existing array substrate.FIG. 1Bis a schematic side sectional structure view along line A-A inFIG. 1A. As shown inFIGS. 1A and 1B, this array substrate comprises a base substrate1, on which data lines5and gate lines2which are cross each other are formed; the data lines5and the gate lines2define pixel units which are arranged in a matrix; each pixel unit comprises a TFT switch and a pixel electrode11; the TFT switch comprises a gate electrode3, a source electrode7, a drain electrode8and an active layer61; the gate electrode3is connected with a gate line2, the source electrode7is connected with a data line5, the drain electrode8is connected with the pixel electrode11, and the active layer61is formed between the source and drain electrodes7and8and the gate electrode3. The data lines5, the gate lines2, the gate electrodes3, the source electrodes7, the drain electrodes8and the active layer61of TFT switches, and the pixel electrodes11described above may be referred to collectively as conductive patterns. For the insulation between the conductive patterns, the conductive patterns provided in the same layer may be achieved by separate arrangement, and the conductive patterns provided in different layers may be achieved by providing an interlayer insulation layer sandwiched between the patterns. Additionally, the conductive patterns provided in different layers can be connected electrically with each other through via holes passing through the insulation layer between the layers.

During the display process of a TFT-LCD, the image signal voltages are input into pixel electrodes via data lines through TFT switches. Since it is necessary for the pixel electrodes to keep the image signal voltages in the period of one frame, a storage capacitor (Cs) is needed to be formed in each pixel unit to keep the image signal voltage on the pixel electrode. There are two ways to form the storage capacitor in the related art, one is form storage capacitors based on gate lines (Cs on Gate), the structure of which is shown inFIGS. 1A and 1B. The pixel electrode11in each pixel unit extends over the gate line2of the adjacent pixel unit, therefore this overlapped portions of the pixel electrode11and the adjacent gate line2form the storage capacitor.

The other way is to form storage capacitors based on common electrode lines (Cs on Common), the structure of which is as shown inFIGS. 2A and 2B. In this way, the array substrate further comprises common electrode lines12which are in the same layer as but not crossed with the gate lines2, and the overlapped portions of the pixel electrode11and the common electrode line12form the storage capacitor. In the structure shown inFIGS. 2A and 2B, the difference compared withFIGS. 1A and 1Blies in the common electrode lines12and the ohmic contact layer62formed on the active layer61for reducing the contact resistance of the active layer61with both the source electrode7and the drain electrode8.

SUMMARY

One embodiment of the invention provides an array substrate comprising a base substrate; a data line and a gate line which are formed on the base substrate and intersect with each other, wherein the data line and the gate line define pixel unit arranged in a matrix, and each pixel unit comprises a thin film transistor (TFT) switch and a pixel electrode; a common electrode line formed on the base substrate; and an additional electrode formed above the gate line, wherein the additional electrode and the gate line are spaced from each other with an insulation layer, and the additional electrode is connected electrically with the common electrode line; and wherein the pixel electrode extends to over the additional electrode and is overlapped with the additional electrode with a passivation layer spaces them, the pixel electrode is overlapped with the additional electrode and common electrode line to form the storage capacitor.

Another embodiment of the invention provides a manufacturing method of array substrate comprising a step of forming a gate line, a common electrode line, a data line, a thin film transistor (TFT) switch and a pixel electrode on a base substrate respectively, the gate line and the data line are cross to form pixel units arranged in matrix manner, each pixel unit comprises a TFT switch and pixel electrode, wherein an additional electrode is also formed at the same time of forming the data line, so as to enable the additional electrode to be located above the gate line, the additional electrode and the gate line are spaced from each other with an insulation layer, and the additional electrode is connected electrically with the common electrode line; the pixel electrode extends to over the additional electrode and is overlapped with the additional electrode, and the pixel electrode is overlapped with the additional electrode and common electrode line to form the storage capacitor.

Yet another embodiment of the invention provides a liquid crystal display comprising a liquid crystal panel, wherein the liquid crystal panel comprises a color filter substrate and the array substrate described above.

DETAILED DESCRIPTION

To make the purpose, the technical solutions and the advantages of the embodiments of the invention more clear, the technical solutions in the embodiment of the invention will be described clearly and entirely in conjunction with the drawings in the embodiment of the invention below. Apparently, the described embodiments are a portion of the embodiments of the invention, but not all embodiments. Based on the embodiment in the invention, all the other embodiments obtained by those skilled in the art under the precondition of no inventive work belong to the protection scope of the invention.

FIG. 3Ais the schematic partial top structure view of an array substrate100provided by the embodiment 1 of the invention.FIG. 3Bis the schematic side sectional structure view along line C-C inFIG. 3A.

As shown inFIGS. 3A and 3B, this array substrate100comprises a base substrate1which may be a glass substrate or a plastic substrate. A plurality of data lines5and a plurality of gate lines2, which intersect with each other, are formed on the base substrate1. The data lines5and the gate lines2define pixel units arranged in a matrix. Each pixel unit comprises a thin film transistor (TFT) switch and a pixel electrode11, and the TFT switch is used for controlling display or no display of each pixel unit. The TFT switch comprised a gate electrode3, a source electrode7, a drain electrode8and an active layer61, which are provided to obtain a layered structure. For each pixel unit, the gate electrode3of the TFT switch is connected with a gate line2, the source electrode7is connected with a data line5, the drain electrode8is connected with the pixel electrode11, the active layer61is formed between the source and drain electrodes7and8and the gate electrode3. The data line5, the gate lines2, the gate electrodes3of TFT switches, the source electrodes7, the drain electrodes8, the active layer61and the pixel electrodes11described above may be referred to collectively as conductive patterns. The insulation between the respective conductive patterns, for the conductive patterns provided in same one layer, may be achieved by providing spacing, and, for the conductive patterns provided in different layers, may be achieved by providing an insulation layer sandwiched between them. Additionally, the conductive patterns provided in different layers can be connected electrically with each other through via holes passing through the insulation layer between the layers; for example, the pixel electrode11may be connected with the drain electrode8through the via hole10in a passivation layer.

Common electrode lines12are also formed on the array substrate100. In the embodiment, common electrode lines12are formed on the same layer as the gate lines2, and the patterns of them are spaced from each other. Additional electrodes13are formed above the gate lines2(perpendicular to the direction of the base substrate1), the additional electrodes13and the gate lines2are spaced from each other with an insulation layer4, and the additional electrodes13is connected electrically with the common electrode lines12respectively. When the common electrode lines12are formed with the gate lines2on the same layer, the additional electrodes13are connected electrically with the common electrode lines12by the additional via holes14,15. The pattern of the pixel electrode11extends to over the additional electrode13and is overlapped with the additional electrode13by a passivation layer9. The overlapped portions of the pixel electrode11and both the additional electrode13and the common electrode line12form a storage capacitor, the pixel electrode11functions as one electrode of the storage capacitor, and the additional electrode13and common electrode line12function as the other electrode of the storage capacitor.

In this embodiment, the additional via holes particularly comprises a first via hole14and a second via hole15, the first via hole14is formed in the passivation layer9covering the data line5and the additional electrode13, and is located over the additional electrode13. The second via hole15is formed in the insulation layer4and the passivation layer9, and is located over the common electrode line12. A bridge line16is formed on the passivation layer9, the bridge line16is connected with the additional electrode13and the common electrode line12through the first via hole14and the second via hole15. This technical solution may adopt an etching process to form the additional via hole14,15when etching to form the passivation layer via hole10by using an existing manufacturing process for the array substrate, and may form the bridge line16when etching to form the pixel electrode11.

The additional electrodes13and the common electrode lines12may be connected in may ways, for example, the additional electrode13can be designed to have a shape not only over the gate line but also extending to over the common electrode line12, and be connected with the common electrode line12by the additional via hole (not shown) in the gate insulation layer. In such a structure, it is not necessary to form the bridge line16as shown above.

The technical solution of this embodiment combined the two configurations of storage capacitor, one based on the gate line2and the other based on the common electrode line12. The additional electrodes13formed on the gate lines2belong to an independent electrode area and form storage capacitors along with the pixel electrodes11therebetween. Simultaneously, the storage capacitors are also formed in the overlapped areas between the common electrode lines12and the pixel electrodes11. These two kinds of storage capacitors together constitute the storage capacitors in the pixel units.

The computing formula of the capacitance value for a flat capacitor is: C=εS/4πkd, wherein C is the capacitance value, ε is the dielectric constant, k is the electrostatic force constant, S is the overlapped area value between the two electrodes of the capacitor, and d is the distance between the two electrodes of the capacitor. The technical solution of the embodiment of the invention, on one hand, increases the overlapped area value of a storage capacitor by means of an additional electrode, which therefore can improve the capacitance value of the storage capacitor or can reduce the area of the common electrode line given that the capacitance storage capacitance value is kept constant, such that the aperture ratio of the pixel unit can be improved; on the other hand, in the configuration of the storage capacitor based on the gate line, the distance between the gate line and the pixel electrode is greater than the distance between the additional electrode and the pixel electrode, thus this portion of the value for storage capacitor of the technical solution of this embodiment is also enhanced compared with the related art; on sill another hand, since the parasitic capacitance is reduced, the structure of this embodiment may further improve the resistance-capacitance delay characteristics and improve display quality compared with the storage capacitor based on the gate line.

FIG. 4is a schematic partial top structure view of an array substrate200provided by the embodiment 2 of the invention. This embodiment differs from the embodiment 1 in that, the additional electrode13on each gate line2is connected electrically with the common electrode lines12in the adjacent two pixel units. This technical solution may be achieved simply by modifying the number of the additional via holes and position appropriately, and modifying the pattern of the bridge line16. InFIG. 4, the bridge line16is connected electrically with the two common electrode lines12by the via holes151,152above the common electrode lines12formed respectively in the adjacent two pixel units.

The technical solution of this embodiment can not only improve the storage capacitance, but also connect the adjacent common electrode lines formed in lines by the another electrodes to avoid the common voltage difference from being produced between the respective common electrode lines and to enable the higher uniformity of the common voltage over the common electrode lines, so as to avoid the flicking phenomenon of the pixel unit which occurs during the process of display.

FIG. 5Ais a schematic partial top structure view of an array substrate300provided by the embodiment 3 of the invention.FIG. 5Bis a schematic side sectional structure view along line D-D inFIG. 5A.

The technical solution of this embodiment differs from the embodiment 1 in that: the common electrode line12is in a same layer as the data line5and the patterns of them are spaced from each other, and the additional electrode13and the common electrode line12are formed integratedly. As shown inFIG. 5A, the additional electrode13extends transversely parallel to and above the gate line2from the common electrode line12which extends longitudinally so as to be overlapped with the gate line2through the gate insulation layer4.

The technical solution of this embodiment still has the advantage of increasing the storage capacitance, and can reduce the area of the common electrode lines under the condition of forming the same storage capacitance, improving the aperture ratio of the pixel unit. Additionally, compared with the technical solution of the embodiment 1, this embodiment also omits the process of forming the additional electrode via hole and the bridge line.

FIG. 6is a schematic partial top structure view of an array substrate400provided by the embodiment 4 of the invention. This embodiment is based on embodiment 3. Connection via holes17are formed in the passivation layer9on the common electrode lines12in the adjacent pixel units on both sides of each data line5. Connection lines18are formed in the passivation layer9on the data line5. The connection lines18are connected with the common electrode lines12in the adjacent pixel units by the connection via holes17.

The technical solution of this embodiment can not only improve the storage capacitance, but connect the adjacent common electrode lines formed in lines to avoid the common voltage difference from being produced between the common electrode lines and to enable the higher uniformity of the common voltage over the common electrode lines, avoiding the flicker phenomenon of the pixel unit which occurs during the process of display.

The embodiment of the invention further provides a manufacturing method of an array substrate. This method comprises a step of forming patterns of a gate line, a gate electrode, a common electrode line, a data line, an active layer, a source electrode, a drain electrode and a pixel electrode on a base substrate respectively; at the time of forming the pattern of the data line, also simultaneously forming a pattern of an additional electrode which is above the gate line, the additional electrode being spaced from the gate line through a gate insulation layer and connected electrically with the common electrode line. The formed pattern of the pixel electrode extends to over the additional electrode and is overlapped with the additional electrode, and the overlapped portions of the pixel electrode and both the additional electrode and the common electrode line form a storage capacitor.

There are various manners for the step of forming the gate line, the gate electrode, the common electrode line, the data line, the active layer, the source electrode, the drain electrode and the pixel electrode pattern; a typical 4-mask process will be taken as an example for illustration below.

A manufacturing method of array substrate provided by the embodiment 5 of the invention comprises the following steps:

Step 710, forming patterns comprising a gate line2, gate electrode3and a common electrode line12on a base substrate1, wherein the patterns of the common electrode line12and the gate line2are spaced from each other, as shown inFIGS. 7A and 7B. The base substrate1may be a glass substrate or a plastic substrate.

Step 710, particularly depositing a layer of metal thin film, which may be an opaque metal, such as aluminum, molybdenum etc., by a magnetron sputtering method, and then adopting a patterning process to form the required pattern by exposing with a mask plate, developing, etching and so on.

Step 720, forming a gate insulation layer4on the base substrate1which has been formed with the above patterns. The gate insulation layer4may be formed by depositing an insulated material by a plasma enhanced chemical vapor deposition (PECVD) method.

Step 730, forming pattern comprising a data line5, an active layer61, a source electrode7, a drain electrode8and an additional electrode13on the gate insulation layer4, particularly as shown inFIGS. 8A and 8B.

Step 730 may particularly be conducted to form the patterns by using a dual-tone mask plate to perform half exposure mask etching.

Step 740, forming a passivation layer9on the base substrate1with the above patterns formed.

Step 750, forming a passivation layer via hole10and an additional via hole in the passivation layer9, wherein the passivation layer via hole10corresponds to the position of the drain electrode8and the additional via holes14,15correspond respectively to the positions of the additional electrode13and the common electrode line12;

Step 760, for patterns comprising a pixel electrode11and a bridge line16on the base substrate1with the above patterns formed. The bridge line is connected with the additional electrode13and common electrode line12through the additional via holes14,15, in reference toFIGS. 3A and 3B. According to the different positions of the additional via holes14,15and the bridge line16, the structure as shown inFIGS. 4A and 4Bmay also be formed.

Based on the embodiment, a third additional via hole located in the adjacent pixel units may be formed in the passivation layer. The third additional via holes are formed in the passivation layer and the gate insulation layer, and correspond to the positions of common electrode lines in adjacent pixel units. Therefore, each bridge line formed on the passivation layer passes the first, the second and the third additional via holes and is connected with the additional electrode, the common electrode line and the common electrode line in the adjacent pixel unit.

The manufacturing method provided by this embodiment can be used for manufacturing the array substrate according to the embodiment of the invention, which has advantages of increasing the storage capacitance value and the pixel unit aperture ratio, and can use the existing processes of manufacturing the array substrate without increasing the difficulty of the process.

The manufacturing method of array substrate provided by the embodiment 6 of the invention comprises the following steps.

Step 101, forming patterns comprising a gate line2and a gate electrode3on a base substrate1, as shown inFIGS. 9A and 9B.

Step 102, forming a gate insulation layer4on the base substrate1with the above formed pattern.

Step 103, forming patterns comprising a data line5, an active layer61, a source electrode7, a drain electrode8, an additional electrode13and a common electrode line12on the gate insulation layer4, wherein the common electrode line12and the additional electrode13are formed in one piece. As shown inFIGS. 10A and 10B, the additional electrode13extends transversely parallel to and above the gate line2from the common electrode line12which extends longitudinally, so as to be overlapped with the gate line2through the gate insulation layer4.

Step 104, forming a passivation layer9on the base substrate1with the above formed pattern.

Step 105, forming a passivation layer via hole10in the passivation layer9. The passivation layer via hole10corresponds to the position of the drain electrode8.

Step 106, forming patterns comprising a pixel electrode11on the base substrate1with the above formed pattern, as shown inFIG. 5A and 5B.

Based on the embodiment, possible steps may further include: forming the connection via holes17when forming the passivation layer via hole10, wherein the connection via holes17are formed over the common electrode line12in the adjacent pixel units on the both sides of each data line5; forming the pattern of a connection line18when forming the pixel electrode11, wherein the connection line18is connected with the common electrode lines12in the adjacent pixel units through the connection via holes17, particularly in reference toFIG. 6.

The manufacturing method provided by this embodiment may be used for manufacturing the array substrate according to the embodiment of the invention, which has advantages of increasing the storage capacitance value and the pixel unit aperture ratio, and uses the existing processes of manufacturing the array substrate without increasing the difficulty of the process.

The embodiment of the invention further provides a liquid crystal display comprising a liquid crystal panel, wherein the liquid crystal panel comprises a color filter substrate and an array substrate provided by any embodiment of the invention.

Finally, it should be explained that, the above embodiments are only used for explaining the technical solution of present invention, and not for limitation thereto. Although the present invention has been explained in details with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications and equivalent alternations may be made to the technical solution of present invention, and these modifications and equivalent alternations can not depart the modified technical solution from the spirit and scope of the technical solution of present invention.