Internal voltage generating circuit of a semiconductor device

An internal voltage generating circuit of a semiconductor device for receiving an external voltage and generating an internal voltage. In a first voltage interval of the external voltage the internal voltage increases linearly according to the external voltage until a reference voltage is reached. In a second voltage range of the external voltage the internal voltage remains at the reference voltage. After the second voltage range, the internal voltage sharply increases and increases linearly thereafter. Accordingly, the circuit can improve the reliability of the tested semiconductor device.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The present invention relates to a semiconductor device and, more 
particularly to an internal voltage generating circuit within a 
semiconductor device. 
2. Description of the Related Art 
An internal voltage generating circuit regulates internal voltage at a 
constant predetermined value within a highly integrated semiconductor 
device. Generally, the internal voltage is obtained by reducing an 
external voltage down to the predetermined voltage level. The internal 
voltage generating circuit operates in either a standard mode for normal 
operation or a test mode for chip reliability testing depending on the 
externally supplied voltage. Ordinarily, a normal mode test and a stress 
mode test are available in the test mode. 
The normal mode test uses an internal voltage regulator that lowers the 
external voltage to an internal reference voltage. The voltage regulator 
typically supplies an internal reference voltage of about +5V. 
In the stress test mode, the internal voltage must be higher than the 
reference voltage. However, raising the internal voltage cannot be 
accomplished since the voltage regulator generates the predetermined 
reference voltage. Therefore, an output terminal of the voltage regulator 
circuitry has a voltage boosting circuit to execute the test. In this 
mode, the boosting circuit generates a boosted voltage of about 6-7 volts. 
FIG. 1 is a circuit diagram illustrating a conventional internal voltage 
generating circuit of a semiconductor device. A voltage regulator 10 is 
connected between voltage supply terminals V.sub.ext and V.sub.ss and 
supplies a reference voltage V.sub.ref on internal voltage terminal 
V.sub.int. A boosting circuit 11 is connected between the voltage supply 
terminal V.sub.ext and the internal voltage terminal V.sub.int. Boosting 
circuit 11 has a plurality of serially connected PMOS transistors M.sub.1 
-M.sub.n. In each of the PMOS transistors, their source electrode is 
connected with their substrate and their gate electrode is commonly 
connected with their drain electrode. The reference voltage V.sub.ref is 
used to perform the normal mode test. The boosting circuit 11 boosts the 
voltage supplied on the internal voltage terminal V.sub.int above the 
reference voltage V.sub.ref. 
FIG. 2 is a graph showing the relationship between the internal supply 
voltage V.sub.int and an external supply voltage V.sub.ext of the circuit 
shown in FIG. 1. A low range of the external supply voltage is the range 
below V.sub.3. In the low range, the internal supply voltage V.sub.int 
generated by the voltage regulator 10 increases linearly to the value 
V.sub.ref. A middle range of the external supply voltage is the range 
between V.sub.3 and V.sub.4. In the middle range, the internal supply 
voltage V.sub.int remains at the reference voltage V.sub.ref. A high range 
of the external supply voltage is the range above V.sub.4. In the high 
range, the internal supply voltage V.sub.int increases linearly again. 
That is, the internal supply voltage V.sub.int increases proportionally to 
the external supply voltage V.sub.ext (after being held constant at the 
reference voltage V.sub.ref), when the voltage difference between the 
external supply voltage V.sub.ext and the reference voltage V.sub.ref 
exceeds a threshold voltage n.cndot.V.sub.th (the sum of the transistor 
thresholds) of the n PMOS transistors in the boosting circuit 11. 
In other words, when the conventional internal voltage generating circuit 
uses the boosting circuit 11, the internal supply voltage V.sub.int is 
Vext-(n.cndot.V.sub.th) obtained by subtracting the summed threshold 
voltages across boosting circuit 11 from the external supply voltage 
V.sub.ext. If a plurality of PMOS transistors constituting boosting 
circuit 11 are used, so that the threshold voltage (n.cndot.V.sub.th) 
circuit 11 across boosting is large, external supply voltage V.sub.ext 
applied during the reliability test should be very high. In this case, the 
reliability of the transistors to which external supply voltage V.sub.ext 
is directly applied can be greatly eroded. Conversely, if the number of 
the PMOS transistors in the boosting circuit 11 is reduced to the minimum, 
the threshold voltage, (n.cndot.V.sub.th) is reduced. Therefore, the 
internal supply voltage V.sub.int increases at low external supply voltage 
V.sub.ext. Accordingly, the reliability test is not as effective. 
SUMMARY OF THE INVENTION 
It is an object of the present invention to provide an internal voltage 
generating circuit which can generate a stable internal supply voltage 
irrespective of external supply voltage fluctuations and capable of 
boosting the internal supply voltage even if low external supply voltage 
is applied during reliability testing. 
The internal voltage generating circuit has a voltage regulator, a first 
boosting circuit and a second boosting circuit connected in parallel 
between an external supply terminal and an internal supply terminal. The 
voltage regulator generates a comparison voltage and an internal voltage. 
The internal voltage is regulated at a predetermined reference voltage 
when the voltage regulator is operating in the normal mode. A comparator 
receives the internal supply voltage, the comparison voltage and the 
external supply voltage and generates a trigger signal. A driver buffers 
the trigger signal before supplying it to the second boosting circuit. 
When the difference between the external supply voltage and the reference 
voltage exceeds the threshold voltage of the first boosting circuit, the 
first boosting circuit boost the internal supply voltage above the 
internal voltage to increase linearly as the external supply voltage 
increases. The comparator compares the internal supply voltage to the 
comparison voltage and generates the trigger signal when the difference 
between the two voltages exceeds a predetermined value. The trigger signal 
enables the second boosting circuit to boost the internal supply voltage 
to a predetermined value below the external supply voltage.

DETAILED DESCRIPTION OF THE INVENTION 
An internal voltage generating circuit of a semiconductor device according 
to the present invention is generally shown in the circuit diagram 
illustrated in FIG. 3. A voltage regulator 20, a first boosting circuit 
23, a second boosting circuit 24 and a comparator 21 are connected in 
parallel between an external supply voltage terminal V.sub.ext and 
internal supply voltage terminal V.sub.int. A comparison voltage terminal 
V.sub.comp connects the voltage regulator 20 to the comparator 21. A 
driver 22 receives the output of the comparator 21 and outputs a trigger 
signal .PHI..sub.STR to the second boosting circuit 24. The voltage 
regulator 20 generates a comparison voltage V.sub.comp and an internal 
supply voltage V.sub.int which is compared by comparator 21. The second 
boosting circuit 24 is responsive to the comparator 21 (through trigger 
signal .PHI..sub.STR) and boosts the internal voltage V.sub.int to a 
predetermined voltage relative to the external supply voltage. In addition 
the first boosting circuit 23 boosts the internal supply voltage 
V.sub.int. 
The first boosting circuit 23 has a plurality of serially connected PMOS 
transistors PT.sub.1 through PT.sub.m. Each of the source electrodes of 
the PMOS transistors is connected to its respective substrate. Also, all 
the gate electrodes of the PMOS transistors PT.sub.1 to PT.sub.m are 
connected to their respective drain electrodes. 
The second boosting circuit 24 has serially connected PMOS transistors 
PS.sub.1 through PS.sub.n. The source electrode and the substrate of the 
PMOS transistor PS.sub.1 are connected to the external supply voltage 
terminal V.sub.ext. The gate electrode of the PMOS transistor PS.sub.1 is 
connected to the trigger signal terminal .PHI..sub.STR (of driver circuit 
22). Each of the source electrodes of the PMOS transistors PS.sub.2 
-PS.sub.n are connected with the respective substrates. In addition, all 
of the gate electrodes of the PMOS transistors PS.sub.2 to PS.sub.n are 
connected in common with their respective drain electrodes. 
FIG. 4 is a graph showing the relationship of the internal supply voltage 
V.sub.int with respect to the external supply voltage V.sub.ext of the 
circuit shown in FIG. 3. Within the low voltage range in which external 
supply voltage V.sub.ext is low (below V.sub.3), internal supply voltage 
V.sub.int increases linearly up to the reference voltage V.sub.ref 
(V.sub.3) . When external supply voltage V.sub.ext is in the middle 
voltage range (between V.sub.3 and V.sub.4), internal supply voltage 
V.sub.int maintains a level equal to the reference voltage V.sub.ref. 
Within the high voltage range in which external supply voltage V.sub.ext 
is high (above V.sub.4), internal supply voltage V.sub.int rises sharply 
and thereafter increases linearly again. 
FIG. 5 is a circuit diagram illustrating one embodiment of the internal 
power generating circuit shown in the circuit illustrated in FIG. 3. The 
voltage regulator 20 has a reference voltage generating circuit 30, a 
first amplifying circuit 31 and a second amplifying circuit 32 connected 
in parallel between the external supply voltage terminal V.sub.ext and 
ground. The reference voltage generating circuit 30 supplies an internal 
reference voltage VI.sub.REF to the first and second amplifying circuits 
31 and 32 respectively. The first amplifying circuit 31 supplies the 
internal supply voltage V.sub.int to the first and second boosting 
circuits 23 and 24 and comparator circuit 21 respectively. The second 
amplifying circuit 32 supplies the comparison voltage V.sub.comp to the 
comparator circuit 21. 
The comparator circuit 21 has a PMOS transistor P1 with its source 
electrode and substrate commonly connected to the external supply voltage 
terminal V.sub.ext. Another PMOS transistor P2 has its source electrode 
and substrate commonly connected to the external supply voltage terminal 
V.sub.ext, and its gate and drain electrodes commonly connected to the 
gate electrode of the PMOS transistor P1. An NMOS transistor N1 has its 
drain electrode commonly connected to the input of the driver 22 and the 
drain electrode of the PMOS transistor P1, and its gate electrode 
connected to the comparison voltage terminal V.sub.comp. Another NMOS 
transistor N2 has its drain electrode commonly connected to the drain and 
gate electrodes of the PMOS transistor P2, and its gate electrode 
connected to the internal supply voltage terminal V.sub.int. Finally, an 
NMOS transistor N3 has its drain electrode commonly connected to the 
source electrodes of the NMOS transistors N1 and N2, its gate electrode is 
connected to the comparison voltage terminal V.sub.comp and its source 
electrode connected to ground. 
The driver circuit 22 has three serially connected inverters INV1, INV2, 
and INV3 receiving the output from the drain electrode of the NMOS 
transistor N1 (of the comparator circuit 21). Inverter INV3 generates the 
trigger signal .PHI..sub.STR. 
The first boosting circuit 23 has a PMOS transistor P3 with its source 
electrode and substrate commonly connected to the external supply voltage 
terminal V.sub.ext, and its gate and drain electrodes commonly connected. 
A PMOS transistor P4 has its source electrode and substrate commonly 
connected to the drain electrode of the PMOS transistors P3, and its gate 
and drain electrodes commonly connected to the internal supply voltage 
terminal V.sub.int. 
The second boosting circuit 24 has a PMOS transistor P5 with its source 
electrode and substrate commonly connected to the external supply voltage 
terminal V.sub.ext, and its gate electrode connected to the output of 
inverter INV3 (of driver 22). A PMOS transistor P6 has its source 
electrode and substrate commonly connected to the drain electrode of the 
PMOS transistor P5, and its gate and drain electrodes commonly connected 
to the internal supply voltage terminal V.sub.int. 
In the above embodiment, the first and second boosting circuits 23 and 24 
each have only two PMOS transistors. However, more PMOS transistors can be 
connected thereto to change the boosting characteristics. 
The operation of the apparatus having the above structure will be explained 
below with an assumption that the threshold voltage V.sub.th of each of 
the transistors in the first and second boosting circuit 23 and 24 is 
0.8V. Initially, when a predetermined range of the external supply voltage 
V.sub.ext is applied to the voltage regulator 20, the internal supply 
voltage V.sub.int (from first amplifying circuit 31) and the comparison 
voltage V.sub.comp (from second amplifying circuit 32) are equal. In the 
comparator circuit 21, the bias current of the NMOS transistor N1 
(receiving the reference voltage V.sub.ref) is set to be larger than that 
of the NMOS transistor N2 (receiving internal supply voltage V.sub.int), 
so the drain electrode potential of the NMOS transistor N1 is lower than 
the drain electrode potential of the NMOS transistor N2. 
When the voltage difference between the external supply voltage V.sub.ext 
and internal supply voltage V.sub.int is greater than or equal to a summed 
threshold voltage (2.cndot.V.sub.th), the first boosting circuit 23 is 
enabled. Thus, the internal supply voltage V.sub.int increases 
proportionally to the external supply voltage V.sub.ext. The trigger 
signal .PHI..sub.STR output from driver circuit 22 changes from logic 
level "low" to "high" since the drain electrode potential of the NMOS 
transistor N1 (of the comparator circuit 21) is higher than that of the 
NMOS transistor N2. Subsequently, the second boosting circuit 24 
(receiving the trigger signal .PHI..sub.STR of driver circuit 22) is 
enabled, so that a voltage of V.sub.th is maintained between the internal 
supply voltage V.sub.int and the external supply voltage V.sub.ext. 
According to the above assumption, a voltage difference of about 0.8V (1 
V.sub.th) is maintained. The present invention can vary the boosting level 
according to the number of transistors within the boosting circuits. Here, 
at least one transistor should be used. Of course, the precise 
configurations at the 1st and 2nd boosting circuits can be adjusted to 
achieve desired test voltage levels. 
Therefore, the internal voltage generating circuit of the semiconductor 
device according to the present invention outputs a predetermined voltage 
by the voltage regulator irrespective of variations in the external supply 
voltage V.sub.ext during the normal mode. Also, since the internal supply 
voltage V.sub.int can be increased by the boosting circuits even when low 
external voltages V.sub.ext are applied during reliability testing, the 
reliability of a tested semiconductor device can be improved.