MAGNETIC MEMORY ELEMENT HAVING MgO ISOLATION LAYER

A magnetic memory element array having a memory element structure that is robust against the affects of high temperature annealing. The memory element array includes a magnetic memory element pillar having a barrier layer (e.g. MgO). A first isolation layer is formed at the side of the memory element pillar, the first isolation layer being a material that is substantially the same as the barrier layer of the magnetic memory element pillar. A second isolation layer such as SiOx is formed such that the first isolation layer separates the second isolation layer from the magnetic memory element pillar. The presence of the first isolation layer advantageously prevents Si migration into the barrier layer during high temperature annealing and advantageously prevents the formation of nano-crystal filaments causing current shunts which would degrade performance of the magnetic memory element pillar.

FIELD OF THE INVENTION

The present invention relates to magnetic random access memory (MRAM) and more particularly to a magnetic memory element having a MgO isolation layer located at the side of the memory element to improve robustness to high temperature processing.

BACKGROUND

Magnetic Random Access Memory (MRAM) is a non-volatile data memory technology that stores data using magnetoresistive cells such as Magnetoresistive Tunnel Junction (MTJ) cells. At their most basic level, such MTJ elements include first and second magnetic layers that are separated by a thin, non-magnetic layer such as a tunnel barrier layer, which can be constructed of a material such as Mg—O. The first magnetic layer, which can be referred to as a reference layer, has a magnetization that is fixed in a direction that is perpendicular to that plane of the layer. The second magnetic layer, which can be referred to as a magnetic free layer, has a magnetization that is free to move so that it can be oriented in either of two directions that are both generally perpendicular to the plane of the magnetic free layer. Therefore, the magnetization of the free layer can be either parallel with the magnetization of the reference layer or anti-parallel with the direction of the reference layer (i.e. opposite to the direction of the reference layer).

The electrical resistance through the MTJ element in a direction perpendicular to the planes of the layers changes with the relative orientations of the magnetizations of the magnetic reference layer and magnetic free layer. When the magnetization of the magnetic free layer is oriented in the same direction as the magnetization of the magnetic reference layer, the electrical resistance through the MTJ element is at its lowest electrical resistance state. Conversely, when the magnetization of the magnetic free layer is in a direction that is opposite to that of the magnetic reference layer, the electrical resistance across the MTJ element is at its highest electrical resistance state.

The switching of the MTJ element between high and low resistance states results from electron spin transfer. An electron has a spin orientation. Generally, electrons flowing through a conductive material have random spin orientations with no net spin orientation. However, when electrons flow through a magnetized layer, the spin orientations of the electrons become aligned so that there is a net aligned orientation of electrons flowing through the magnetic layer, and the orientation of this alignment is dependent on the orientation of the magnetization of the magnetic layer through which they travel. When the orientations of the magnetizations of the free and reference layer are oriented in the same direction, the majority spin of the electrons in the free layer are is in the same direction as the orientation of the majority spin of the electrons in the reference layer. Because these electron spins are in generally the same direction, the electrons can pass relatively easily through the tunnel barrier layer. However, if the orientations of the magnetizations of the free and reference layers are opposite to one another, the spin of majority electrons in the free layer will be generally opposite to the majority spin of electrons in the reference layer. In this case, electrons cannot easily pass through the barrier layer, resulting in a higher electrical resistance through the MTJ stack.

Because the MTJ element can be switched between low and high electrical resistance states, it can be used as a memory element to store a bit of data. For example, the low resistance state can be read as an on or “1”, whereas the high resistance state can be read as a “0”. In addition, because the magnetic orientation of the magnetic free layer remains in its switched orientation without any electrical power to the element, it provides a robust, non-volatile data memory bit.

To write a bit of data to the MTJ cell, the magnetic orientation of the magnetic free layer can be switched from a first direction to a second direction that is 180 degrees from the first direction. This can be accomplished, for example, by applying a current through the MTJ element in a direction that is perpendicular to the planes of the layers of the MTJ element. An electrical current applied in one direction will switch the magnetization of the free layer to a first orientation, whereas switching the direction of the current and such that it is applied in a second direction will switch the magnetization of the free layer to a second, opposite orientation. Once the magnetization of the free layer has been switched by the current, the state of the MTJ element can be read by reading a voltage across the MTJ element, thereby determining whether the MTJ element is in a “1” or “0” bit state. Advantageously, once the switching electrical current has been removed, the magnetic state of the free layer will remain in the switched orientation until such time as another electrical current is applied to again switch the MTJ element. Therefore, the recorded date bit is non-volatile in that it remains intact in the absence of any electrical power.

SUMMARY

The present invention provides a magnetic memory device that includes a magnetic memory element having a side and having a barrier layer. The magnetic memory device further includes a first isolation layer formed of a material that is substantially the same as the material of the barrier layer, and a second isolation layer arranged such that the first isolation layer separates the second isolation layer from the magnetic memory element.

The barrier layer and the first isolation layer can be constructed of magnesium oxide, whereas the second isolation layer can be formed of a material such as silicon oxide, which provides good dielectric properties, good hardness and resistance to corrosion and also has good properties for chemical mechanical polishing. A third isolation layer, which can be constructed of a material such as silicon nitride can be provided over the second insulation layer and can serve as a chemical mechanical polishing (CMP) stop layer to facilitate manufacture of the device.

In a magnetic memory device, magnetic memory elements are connected with circuitry such as CMOS circuitry that requires high temperature treatment to be performed after formation of the magnetic memory element. This high temperature treatment can include treatment at temperatures of around 400 degrees C. for extended periods of time. This high temperature treatment can cause Si diffusion into the barrier layer which greatly degrades spin tunneling properties and decreases performance. In addition, the high temperature treatment can cause the formation of crystals at the outer edges of the barrier layer which can lead to current shunting and reduced electrical resistance of the memory element.

The presence of the first isolation layer advantageously prevents Si from migrating from the other isolation layer or layer and diffusing into the barrier layer. The first isolation layer also advantageously prevents the problematic formation of crystals at the outer edges of the barrier layer which would act as current shunts and greatly degrade performance of the device.

As discussed, the first isolation layer can be constructed of substantially the same material as the barrier layer. For example, if the barrier layer is constructed of magnesium oxide, the first isolation layer can be constructed of magnesium oxide having an oxygen content that is within plus or minus five atomic percent of that of the barrier layer.

These and other features and advantages of the invention will be apparent upon reading of the following detailed description of the embodiments taken in conjunction with the figures in which like reference numeral indicate like elements throughout.

DETAILED DESCRIPTION

Referring now toFIG. 1, a magnetic memory element100can be in the form a of a perpendicular magnetic tunnel junction (pMTJ) memory element. The magnetic memory element can include an MTJ101that can include a magnetic reference layer102, a magnetic free layer104and a thin, non-magnetic, electrically insulating magnetic barrier layer106located between the magnetic reference layer102, and magnetic free layer104. The barrier layer106can be an oxide such as MgO. The magnetic reference layer has a magnetization108that is fixed in a direction that is preferably perpendicular to the plane of the layers as indicated by arrow108. The magnetic free layer has a magnetization110that can be in either of two directions perpendicular to the plane of the layer104. While the magnetization110of the free layer remains in either of two directions perpendicular to the plane of the layer104in a quiescent state, it can be moved between these two directions as will be described in greater detail herein below. When the magnetization110of the magnetic free layer104is in the same direction as the magnetization108of the reference layer102, the electrical resistance across the layers102,106,104is at a low resistance state. Conversely, when the magnetization110of the free layer104is opposite to the magnetization108of the reference layer102, the electrical resistance across the layers102,106,104is in a high resistance state.

The magnetic reference layer102can be part of an anti-parallel magnetic pinning structure112that can include a magnetic keeper layer114, and a non-magnetic, antiparallel coupling layer116located between the keeper layer114and reference layer102. The antiparallel coupling layer116can be a material such as Ru and can be constructed to have a thickness such that it will ferromagnetically antiparallel couple the layers114,102. The antiparallel coupling between the layers114,102pins the magnetization108of the reference layer102in a direction opposite to the direction of magnetization118of the keeper layer114.

A seed layer120may be provided near the bottom of the memory element100to initiate a desired crystalline structure in the above deposited layers. A capping layer122may be provided near the top of the memory element100to protect the underlying layers during manufacture, such as during high temperature annealing and from exposure to ambient atmosphere. Also, electrodes124,126may be provided at the top and bottom of the memory element100. The electrodes124,126may be constructed of a non-magnetic, electrically conductive material such as Ta, W, Cu and Al can provide electrical connection with circuitry128that can include a current source and can further include circuitry for reading an electrical resistance across the memory element100.

The magnetic free layer104has a perpendicular magnetic anisotropy that causes the magnetization110of the free layer104to remain stable in one of two directions perpendicular to the plane of the free layer104. In a write mode, the orientation of the magnetization110of the free layer104can be switched between these two directions by applying an electrical current through the memory element100from the circuitry128. A current in one direction will cause the memory element to flip to a first orientation, and a current in an opposite direction will cause the magnetization to flip to a second, opposite direction. For example, if the magnetization110is initially oriented in a downward direction inFIG. 1, applying a current in a downward direction through the element100will cause electrons to flow in an opposite direction upward through the element100. The electrons travelling through the reference layer will become spin polarized as a result of the magnetization108of the reference layer102. These spin polarized electrons cause a spin torque on the magnetization110of the free layer104, which causes the magnetization to flip directions.

On the other hand, if the magnetization110of the free layer104is initially in an upward direction inFIG. 1, applying an electrical current through the element100in an upward direction will cause electrons to flow in an opposite direction, downward through the element100. However, because the magnetization110of the free layer104is opposite to the magnetization108of the reference layer102, the electrons with an opposite spin will not be able to pass through the barrier layer106to the reference layer102. As a result, the electrons having an opposite spin will accumulate at the junction between the free layer104and barrier layer106. This accumulation of spin polarized electrons causes a spin torque that causes the magnetization110of the free layer104to flip from a downward direction to an upward direction.

In order to assist the switching of the magnetization110of the free layer104, the memory element100may include a spin polarization layer130formed above the free layer104. The spin polarization layer can be separated from the free layer104by a coupling layer132. The spin polarization layer130has a magnetic anisotropy that causes it to have a magnetization134with a primary component oriented in the in-plane direction (e.g. perpendicular to the magnetizations110,108of the free and reference layers104,102. The magnetization134, of the spin polarization layer130may either be fixed or can move in a precessional manner as shown inFIG. 100. The magnetization134of the spin polarization layer130causes a spin torque on the free layer104that assists in moving its magnetization away from its quiescent state perpendicular to the plane of the free layer104. This allows the magnetization110of the free layer104to more easily flip using less energy when applying a write current to the memory element100.

FIG. 2shows a side, cross sectional view of a magnetic memory element202, incorporated into a magnetic memory array200, a small portion of which is shown inFIG. 2. Although only one memory element202is shown inFIG. 2, it should be appreciated that this is for purposes of illustration and that the memory array200can include many memory elements202. The memory element202can be connected with circuitry such as CMOS circuitry204, and connection between the memory element202and the circuitry204can be accomplished via a first electrode206. The memory element202can also be connected with a second electrode208for further connection with memory array circuitry. Areas at either side of the circuitry204and first electrode206can be filled with a dielectric fill material210such as SiO2.

The memory element202can have a structure such as the memory element100described above with reference toFIG. 1. Although this is by way of example, as the memory element202can have some other suitable structure. As shown inFIG. 2, the memory element202can include a thin barrier layer214, which is preferably a material such as MgOx. In addition, a novel dielectric isolation layer structure216, which will be described in greater detail herein below, is formed at either side of the memory element202in order to electrically isolate the memory element202to ensure that switching is applied across the memory element202as desired and not shunted at areas outside of the memory element202.

Maintaining a desired crystal structure and thickness of the barrier layer214is important to maintaining good magnetic tunnel junction performance. However, it has been found that high temperature treatment processes necessary for the CMOS circuitry fabrication which are performed after formation of the magnetic memory element202can degrade the structure of the barrier layer214and, therefore, negatively affect memory element performance.

The nanofabrication of magnetic memory element pillars in magnetic memory arrays involves the use of back-end CMOS semiconductor circuitry fabrication technology. Part of this back-end-of-line CMOS processing requires a thermal treatment after the formation of the magnetic memory element pillars (e.g.202). This thermal treatment can include treatment at temperatures of up to 400 degrees Celsius for an extended period of time.

Because this thermal annealing treatment is performed after the formation of the memory element pillars202, the pillars and surrounding structure must be designed to withstand such thermal treatments. One challenge that arises as a result of the thermal annealing is the affect of such thermal treatment on the already formed barrier layer214, especially with regard to the use of dielectric isolation layer structures at the side of the memory element. Materials such as silicon oxides (SiOx) and silicon nitrides (SiNx) are desirable materials for use in such isolation structure for electrically isolating pillar structures from one another, because they have good dielectric properties and good properties for chemical mechanical polishing (CMP), the use of which will be described in greater detail herein below. However, at such high temperatures Si from the SiOx or SiNx layers can diffuse into the barrier layer, greatly degrading the performance of the memory element by negatively affecting the quantum tunneling properties of the barrier layer214and also by creating shunting paths at the outer edges of the barrier layer214due to formation of conductive Si nanocrystal filaments in proximity of the barrier layer214. This problem is further exacerbated by the fact that the milling process used to form the pillar structure forms a rough surface on the outer edge of the pillar structure. This rough edge forms nucleation points which encourage the formation of Si nanocrystals at the outer edge of the pillar structure. These nanocrystals can connect to each other and act as electrical shunts which lead to low device resistance and greatly reduced performance of the memory element. In addition, defects in the MgO barrier resulting from the presence of Si degrade the tunneling properties of the MgO barrier layer, substantially decreasing TMR performance.

A novel structure as described generally with reference toFIGS. 2 and 3solves this problem by mitigating the effects of having a SiOx or SiNx layer adjacent to the sides of the pillar structure. As shown inFIG. 2, an isolation structure216is formed as a multi-layer structure. The multi-layer isolation structure216includes a first layer218that is a bottom layer located adjacent to the memory element pillar structure202. This first layer can be formed of the same material as the barrier layer214and is preferably in contact with the sides of the memory element pillar structure202. In one exemplary embodiment, the barrier layer214and first layer218are both constructed of MgO.

The isolation structure216can further include one or more other types of dielectric layers formed over or beside the first layer218, so that the first layer218separates these other layers from the pillar structure202and more importantly separates these other layers from the barrier layer214. In the exemplary embodiment shown inFIG. 2, the isolation structure can include a second layer220formed over the first layer218and a third layer222formed over the second layer220. In this exemplary embodiment, the second layer220can be silicon oxide (SiOx) and the third layer222can be formed of silicon nitride (SiNx). More preferably, the layer220is silicon dioxide (SiO2). This structure provides advantages that will become more apparent below upon a discussion of a method for manufacturing a memory array. In this embodiment first layer218acts as a diffusion barrier effectively preventing Si from the SiOx or SiNx layers220,222from migrating into and diffusing into the barrier layer214. Advantageously, because the first layer218is formed of the same material as the barrier layer216, it will have no negative impact on the properties of the barrier layer214, even when subjected to prolonged high temperature treatment processes. In an optional, alternate embodiment, the second and third layers220,222can be replaced with a single layer of, for example, SiNx or SiOx.

The first layer218can be constructed as a single layer or as a multi-layer structure and can be have a thickness of 1-5 nm. Preferably, the first layer218can be formed as a single layer of naturally oxidized or reactively oxidized Mg to form single MgO layer.

FIG. 3shows a portion of a memory element array300according to an alternate embodiment of the invention. The memory element array300includes a magnetic memory element302, which can include various layers similar to the memory element100ofFIG. 1. The memory element302includes a barrier layer214, which is preferably constructed of MgO. In addition, the memory element302can include a lower seed layer305, which can be constructed of a material such as Tantalum (Ta), Ruthenium (Ru), Copper (Cu) and their respective Nitrides. As can be seen inFIG. 3, the seed layer305extends laterally outward from the rest of the memory element302and has an outer edge that can be aligned with an outer edge of the lower electrical contact206. The lower electrical contact can be constructed of a material such as TaN, which is both electrically conductive and resistant to certain dry etching and ion milling processes for reasons that will become clearer herein below.

The memory element array300can be formed with an isolation structure304that includes first second and third layers306,308,310. The first layer306is formed of a material that is the same as or similar to the material of the barrier layer214of the memory element pillar202. For example, the barrier layer214can be formed of magnesium oxide and the first isolation layer306can be formed of magnesium oxide having an oxygen concentration that is within plus or minus 5 atomic percent of the magnesium oxide of the barrier layer214. The first layer306has a tapered structure as shown inFIG. 3, wherein the layer306is narrower toward the top end of the memory element pillar306and wider toward its bottom end where it contacts the seed layer structure305. As shown inFIG. 3, the bottom of the first layer306can be aligned with the outer edge of the memory element seed layer305while the narrower end near the top of the first layer306terminates before the top of the memory element302but extends above MgO layer214. Therefore, the top of the first layer306terminates at a point that is between the barrier layer214and the top end of the memory element302so that it is not in contact with the top contact layer208. The first isolation layer306is formed by a self-aligned process that will be described in greater detail herein below.

In the exemplary embodiment described with reference toFIG. 3, the second isolation layer308can be constructed of a dielectric material such as silicon oxide (SiOx) and the third isolation layer310can be constructed of a dielectric material such as silicon nitride (SiNx). The use of the second and third layers308,310are advantageous for facilitating manufacture for reasons that will become clearer below. However, alternatively, the second and third layers308,310can be formed as a single layer of a material such as SiOx or SiNx.

The tapered shape of the first layer306is optimal for both facilitating manufacturing such as by providing optimal properties for chemical mechanical polishing (CMP) and also effectively preventing Si diffusion into the barrier layer214. MgOx is not an optimal material for chemical mechanical polishing (a process which will be needed to form a planar upper surface on the memory element pillar structure), while silicon oxide (SiOx) responds well to chemical mechanical polishing and provides good process control for chemical mechanical polishing. Because the first layer306does not extend to the top of the pillar structure302, there will be no MgO at this region to be subject to chemical mechanical polishing. This advantageously leaves the SiOx layer308and SiNx layer310to withstand the chemical mechanical polishing. However, because the layer306is present in the region adjacent to the barrier layer structure214it can provide very effective protection against Si diffusion into the barrier layer. This advantageously allows greatly improved diffusion barrier protection while eliminating any disadvantage of having the MgOx being subject chemical mechanical polishing.

FIGS. 4-9show a portion of a magnetic memory array in various intermediate stages of manufacture in order to illustrate a method of manufacturing a magnetic memory array according to an embodiment such as the embodiment shown with reference toFIG. 2. With particular reference toFIG. 4, a first, or lower, electrical contact402is formed. The electrical contact402can be surrounded by a dielectric material404, such as silicon oxide or silicon nitride. The contact402can be constructed of an electrically conductive metal such as TaN. The electrical contact can be electrically connected with electrical circuitry (not shown) such as CMOS circuitry that can be located beneath the contact402. The upper surface of the contact402and surrounding dielectric404can have a smooth coplanar surface that can be formed by chemical mechanical polishing (CMP). Magnetic memory element material406can be deposited over the coplanar surface of the contact402and surrounding dielectric material404. Although shown as a single layer406inFIG. 4, it should be understood that the material406would actually include various layers necessary to construct a magnetic memory element pillar such the magnetic memory element pillar100ofFIG. 1, or the memory elements202, ofFIG. 2.

With reference now toFIG. 5, a mask structure502is formed over the magnetic memory element material406. The mask may include various mask layers such as a photoresist mask, hard mask, adhesion layer etc., and as shown inFIG. 5includes a photoresist mask structure501formed over a hard mask material503such as TaN. The mask502is configured to define a magnetic element pillar structure.

With the mask502in place, a material removal process is performed to remove portions of the magnetic element material406that are not protected by the mask structure502, leaving a structure as shown inFIG. 6. The material removal process could be one of several available etching or milling processes but is preferably an ion beam etching process which has been shown to provide good performance in creating well defined magnetic element pillar structures. This material removal process used to define the pillar structure406can also remove the photoresist mask501(FIG. 5) leaving just the hard mask503over the pillar structure406, as shown inFIG. 6.

With reference now toFIG. 7, a series of dielectric isolation layers is deposited. A first layer702is deposited, preferably so as to be in direct contact with the magnetic element pillar structure406. The first layer702is a dielectric layer that is the same as or similar to a material making up a barrier layer of the magnetic memory element structure406(such as the barrier layer214ofFIGS. 2 and 3). Preferably, both the barrier layer (not shown) and the first layer702can be constructed of MgOx, with the first layer702having an oxygen content that is within plus or minus 5 atomic percent of that of the barrier layer (not shown).

The first layer702can be deposited by one of several deposition techniques so as to form an oxide, such as MgOx. Since the layer702is preferably MgOx so as to match with the barrier layer (not shown), the deposition of the first layer702will be described as a process for depositing MgOx. One way to deposit a MgOx layer702is by a plasma vapor deposition (PVD) process in a deposition chamber using a target containing both Mg and O (e.g. a MgO target). In this deposition process Radio Frequency (RF) sputtering can be used by sputtering MgO directly from the MgO target. Alternatively, the deposition of the layer702can be performed using DC magnetron sputtering or radio frequency (RF) sputtering and can be deposited as a series of layers or as a single layer. Preferably, however, the layer702is deposited as a series of layers of Magnesium (Mg) using a Plasma Vapor Deposition (PVD) process by sputtering from Mg target and is then reactively (ROx) or naturally (NOx) oxidized until a desired oxygen content is achieved to effectively match stochimetric MgO for layer702. This process allows the layer702to be more easily deposited to a desired thickness (preferably 1-5 nm) and also advantageously allows good control of the oxidation process. Again, this process could be performed so as to deposit the layer702as multiple oxide layers rather than a single layer.

After the first layer702has been deposited, second, third and fourth layers704,706,708are successively deposited over the first layer702. The second layer704, deposited directly over the first layer702, can be silicon oxide (SiOx). The third layer706can be deposited as a dielectric layer that is resistant to chemical mechanical polishing (CMP) so as to make a good CMP stop layer. For example, the third layer706is preferably SiNx, which provides good dielectric properties and also functions as a good CMP stop layer. The fourth layer708is preferably formed of SiOx, which provides good properties for subsequent chemical mechanical polishing (CMP) such as good control of CMP material removal rate. The second, third and forth layers704,706,708can all be deposited by various conformal deposition processes and are preferably deposited by plasma-enhanced chemical vapor deposition (PECVD).

After the layers702,704,706,708have been deposited, a chemical mechanical polishing (CMP) can be performed to planarize the structure. The CMP process is performed until the third layer706is reached. The layer706is used as a CMP stop layer (as discussed) because of its good resistance to removal by CMP. The fourth layer708, which was included to facilitate the CMP process can be removed by the CMP, leaving a structure such as that shown inFIG. 7.

With reference toFIG. 9, after the chemical mechanical polishing process has been performed, an electrically conductive contact layer902is formed over the memory element pillar structure406and isolation layers702,704,706. The electrically conductive contact layer902can be deposited by sputter deposition or electroplating and can be a material such as TaN.

FIGS. 10-15show a magnetic memory array in various intermediate stages of manufacture in order to illustrate a method of forming a magnetic memory array according to an alternate embodiment. With particular reference toFIG. 10, a first electrical contact402is formed. The first electrical contact can be surrounded at its side by a dielectric layer404, such as silicon oxide or silicon nitride. Magnetic memory element material406is deposited over the first contact402and surrounding dielectric404. As with the previously described embodiment, the magnetic memory element material406can include various material layers necessary to form a magnetic element pillar such as the memory element pillar100described with reference toFIG. 1. The memory element material may also include a seed layer1005deposited at the bottom of the memory element material406. The seed layer1005can be a material such as Ta, Ru, Cu or their Nitrides respectively. A mask structure1002is formed over the memory element material406. The mask structure1002can include a photoresist mask1003formed over a hard mask structure1004such as TaN or Diamond like Carbon (DLC) and is configured to define a diameter of a desired memory element pillar. In addition to the layers1003,1004, the mask structure1002can include other layers (not shown) such as adhesion layers, bottom antireflective coating layers, etc.

With reference toFIG. 11, a material removal process such as ion beam etching is performed to remove portions of the memory element material that are not protected by the mask structure1002in order to form a memory element pillar406. This material removal process may remove the photoresist mask1003(FIG. 10) and may also consume some of the hard mask structure1004, leaving the structure shown inFIG. 11. As shown inFIG. 12, the material removal process used to form the pillar structure406is terminated before removing the seed layer1005. Also, not shown, the material removal process can be terminated earlier leaving part of the layer406thickness not etched as long as it is terminated after etching through MgO layer214. This leaves the seed layer or seed layer with part of the MTJ structure406extending beyond the sides of the pillar structure406as shown. The seed layer1005can be constructed of a material such as Ta, Ru, or Cu.

With reference toFIG. 12, a first dielectric isolation layer1202is deposited over the layer1005. The first dielectric isolation layer1202is a material that is the same as or similar to the barrier layer material214of the magnetic memory element layer406. Preferably both the barrier layer214of the magnetic memory element406and the first dielectric layer1202are formed of MgO, and preferably both layers have about the same oxygen content as one another. In one possible embodiment, the first dielectric layer1202is deposited to a thickness that is about the same as the thickness of the magnetic memory element pillar406.

Then, an etching process is performed to etch back the first dielectric layer1202. This etching process causes the first dielectric layer to form a tapered dielectric sidewall1202as shown inFIG. 13. The tapered dielectric sidewall is thinner at the top and thicker at the bottom, which provides advantageous that will become clearer herein below. This etching process also remove an outer portion of the seed layer1005, leaving an outer edge of the seed layer1005that is self-aligned with the bottom portion of the remaining first dielectric isolation layer1202. The etching process is also performed sufficiently that the top of the side tapered sidewall1202terminates at a location between the barrier layer1402and the top of the memory element pillar structure406such that it terminates short of the top of the memory element pillar structure406.

With reference toFIG. 14, second, third and fourth dielectric layers1302,1304,1306are sequentially deposited over the first dielectric layer1202. The second dielectric layer1304is preferably silicon oxide (SiOx) and can be deposited directly over the first dielectric layer1202. The third dielectric layer1304is preferably silicon nitride (SiNx) and can be deposited directly over the second dielectric layer1302. Silicon nitride has good dielectric properties, but also has good properties for use as a stop layer for chemical mechanical polishing (i.e. it makes a good CMP stop), as it has good resistance to removal by CMP. The fourth layer1306can be another layer of silicon oxide (SiOx) and can be deposited directly onto the third layer1304. The second, third and fourth dielectric layers are preferably deposited by physical electron beam vapor deposition, although they could be deposited by some other conformal deposition process as well. Optionally, the second and third layers1304could be deposited as a single layer, of for example, SiNx.

After the layers1302,1304,1306have been deposited, a chemical mechanical polishing process can be performed to planarize the structure, leaving a structure as shown inFIG. 15. As can be seen inFIG. 15, the chemical mechanical polishing (CMP) removes substantially all of the fourth dielectric layer1306and is terminated at the level of the third dielectric layer1304, which as discussed above is a material such as SiNx that has properties to make it a good CMP stop layer. The above deposited fourth dielectric layer1306, which is preferably SiOx, facilitates the CMP process until the CMP stop layer1304is reached, because it provides good control of CMP material removal rate.

With reference toFIG. 16, after the CMP process has been performed to planarize the structure, an upper lead1602can be formed. The upper lead1602can be of various electrically conductive metals and is preferably Ta, TaN and Aluminium (Al) or combination of both.