A/D Converter to convert an analog signal from a bridge circuit to a digital signal

An AD converter comprising: a delta-sigma-modulation circuit to output an analog signal from a bridge circuit as a quantized signal; a switch circuit to switch between a first state, where a first level voltage is applied to one terminal of the bridge circuit and a second level voltage different in level from the first level voltage is applied to the other terminal thereof, and a second state, where voltages opposite in level to those in the first state are applied thereto, based on a logic level of a control signal; and an up-down counter to increase a count value based on a rate of the quantized signal being one logic level, during a predetermined period, in the first state, and decrease the count value based on the rate, during the predetermined period, in the second state, the count value representing a digital signal according to the physical quantity.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of priority to Japanese Patent Application No. 2007-330559, filed Dec. 21, 2007, of which full contents are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an AD (analog to digital) converter.

2. Description of the Related Art

In a sensor circuit for processing physical quantity, such as acceleration and magnetism, detected by a sensor, offset adjustment is generally performed in order to more precisely process the physical quantity to be detected (see Japanese Laid-Open Patent Publication No. 2001-91373, for example). There is shown inFIG. 7an example of a sensor circuit500for processing an output from a bridge circuit600to be used as an acceleration sensor. A preamplifier610amplifies an output from the bridge circuit600, to be output to a delta-sigma AD converter including a delta-sigma modulation circuit620and a digital filter630. The delta-sigma AD converter converts an output from the preamplifier610into a digital value, and an output interface circuit640outputs the digital value to a microcomputer (not shown.)

As a first example of an offset adjustment method in the sensor circuit500, a method is cited where only a polarity of a voltage applied to the bridge circuit600is changed and the digital value in one state where the polarity of the voltage is not changed and the other state where the polarity of the voltage is changed are compared in the microcomputer (not shown.) Specifically, first of all, the control circuit650controls switches SW100to SW130, so that a power supply VCC is connected to a node VA to which resistors R100and R110are connected, and a ground GND is connected to a node VB to which resistors R120and R130are connected, respectively. And then, the output interface640outputs to the microcomputer (not shown) the digital value in a state where the power supply VCC is connected to the node VA and the ground GND is connected to the node VB. Next, the control circuit650controls the switches SW100to SW130, so that the ground GND is connected to the node VA and the power supply VCC is connected to the node VB, respectively. And then, the output interface circuit640outputs to the microcomputer (not shown) the digital value in a state where the ground GND is connected to the node VA and the power supply VCC is connected to the node VB. Thus, in a case where only the polarity is changed of the voltage applied to the bridge circuit600, the polarity of the output from the bridge circuit600is changed, however, the polarities of offsets in the preamplifier610and the delta-sigma modulation circuit620are not changed. Therefore, an offset of the sensor circuit500can be cancelled by comparing the digital values in the above-mentioned different states in the microcomputer (not shown.)

Furthermore, as a second example of the offset adjustment method, there is cited a method of using a chopper amplifier, etc., in order to reduce an offset of the preamplifier610, for example (see non-patent document: Eric Nolan, “Demystifying Auto-Zero Amplifiers-Part 1,” Analog Dialogue, Analog Devices, Inc., March, 2000, vol. 34-2, pp. 1-3.)

In the case where the polarity of the voltage applied to the bridge circuit600is changed and the digital values in the different states are compared in the microcomputer (not shown) as described in the above first example, there is a problem that processing in the microcomputer (not shown) increases due to the adjustment of the offset of the sensor circuit500. Moreover, in the case where the offset adjustment is performed only for the preamplifier610as described in the above second example, there is a problem that the adjustment has no effect on an offset generated in the delta-sigma modulation circuit620which is a circuit including an analog circuit other than the preamplifier610including that, for example.

SUMMARY OF THE INVENTION

An AD converter according to an aspect of the present invention, comprises: a delta-sigma modulation circuit configured to perform delta-sigma modulation for an analog signal from a bridge circuit, and output a delta-sigma modulated signal as a quantized signal, the bridge circuit being configured to output the analog signal according to physical quantity to be measured; a switch circuit configured to switch between a first state and a second state based on a logic level of a control signal, the first state being a state where a voltage of a first level is applied to one terminal of the bridge circuit and a voltage of a second level different from the first level is applied to the other terminal of the bridge circuit, the second state being a state where the voltage of the second level is applied to the one terminal and the voltage of the first level is applied to the other terminal; and an up-down counter configured to increase a count value based on a rate of the quantized signal being one logic level, during a predetermined period, when the bridge circuit is in the first state, and decrease the count value based on a rate of the quantized signal being one logic level, during the predetermined period, when the bridge circuit is in the second state, the count value being a value to be a digital signal according to the physical quantity.

Other features of the present invention will become apparent from descriptions of this specification and of the accompanying drawings.

DETAILED DESCRIPTION OF THE INVENTION

At least the following details will become apparent from descriptions of this specification and of the accompanying drawings.

FIG. 1is a diagram showing a configuration of sensors10to12and a sensor circuit15for processing outputs from the sensors10to12according to an embodiment of the present invention.

The sensors10to12are acceleration sensors for respectively detecting acceleration of an x-axis, a y-axis, and a z-axis, and respectively outputs output voltages VS1and VS2according to the acceleration of the x-axis, output voltages VS3and VS4according to the acceleration of the y-axis, output voltages VS5and VS6according to the acceleration of the z-axis, by being connected with a power supply VCC and a ground GND, for example. According to an embodiment of the present invention, it is assumed that each of the sensors10to12has the same configuration, and therefore, detailed description will be given only for the sensor10. Moreover, a voltage value of the power supply VCC will hereinafter be represented as VCC.

The sensor10is a bridge circuit where resistors R1to R4are bridge-connected. When a voltage between a node N1(one terminal) connected with the resistors R1and R2, and a node N2(the other terminal) connected with the resistors R3and R4is VCC, the sensor10respectively outputs the output voltages VS1and VS2according to the acceleration of the x-axis, from a node connected with the resistors R2and R3, and a node connected with the resistors R1and R4. In an embodiment according to the present invention, it is assumed that when the voltage between the node N1and the node N2is VCC and the acceleration of the x-axis is zero, each of the output voltages VS1and VS2from the sensor10is (½)×VCC. Furthermore, when the polarity of the voltage between the node N2and the node N1is reversed, the outputs from the sensors10to12are also reversed, in the sensors10to12according to an embodiment of the present invention. That is, for example, the sensor10is designed such that voltages Va and Vb are respectively output as the output voltages VS1and VS2in a case where the voltage between the node N2and the node N1is +VCC, and the voltages Vb and Va are respectively output as the output voltages VS1and VS2in a case where the voltage between the node N2and the node N1is −VCC.

It is assumed that two nodes except nodes for outputting the output voltages VS3and VS4in the sensor11are connected to the nodes N1and N2, respectively, and two nodes except nodes for outputting the output voltages VS5and VS6in the sensor12are also connected to the nodes N1and N2, respectively.

The sensor circuit15is a circuit for converting the output voltages VS1to VS6output from the sensors10to12into digital values, to be output to a microcomputer (not shown) as data DATA. The sensor circuit15includes a first switch circuit20, a second switch circuit21, a processing circuit22, and a control circuit23. The first switch circuit20corresponds to a switch circuit according to an embodiment of the present invention.

First, outlines will be described of circuits included in the sensor circuit15.

The first switch circuit20is a circuit for changing the polarity of the voltage of the nodes N1and N2so that the voltage between the node N2and the node N1in the sensors10to12is +VCC or −VCC based on a control signal CONT1from the control circuit23, and includes switches SW1to SW4.

The second switch circuit21is a circuit for selecting two output voltages output from any one sensor among the sensors10to12based on the control signals CONT2to CONT4from the control circuit23to be output to the processing circuit22as output signals AO1and AO2, and includes switches SW10to SW15.

The processing circuit22is a circuit for converting into digital signals corresponding to analog output signals AO1and AO2indicating the outputs from the sensors10to12based on an enable signal CE, a clock signal CLK, a reversal signal REV, and a reset signal RST that are input from the control circuit23, and for outputting the converted digital signals as the data DATA to the microcomputer (not shown) based on output instruction signal CS, and includes a preamplifier30, a delta-sigma modulation circuit31, a digital filter32, and an output interface33.

The control circuit23is a circuit for outputting the control signal CONT1to the first switch circuit20, outputting the control signals CONT2to CONT4to the second switch circuit21, and outputting the enable signal CE, the clock signal CLK, the reversal signal REV, the reset signal RST, and the output instruction signal CS to the processing circuit22, in predetermined timing, and is a sequencer, for example.

Next, configurations of circuits making up the sensor circuit15will be described.

In the first switch circuit20, one end of each of the switches SW1to SW4is respectively connected to the power supply VCC, the node N1, the node N2, and ground GND. According to an embodiment of the present invention, when the control signal CONT1from the control circuit23is a high level (hereinafter, “H level”), it is assumed that the other end of switch SW1is connected with the other end of switch SW2and the other end of switch SW3is connected with the other end of switch SW4. On the other hand, when the control signal CONT1is a low level (hereinafter, “L level”), it is assumed that the other end of switch SW1is connected with the other end of switch SW3may be connected and the other end of switch SW2is connected with the other end of switch SW4. That is, when the control signal CONT1is H level, the nodes N1and N2are connected to the power supply VCC and ground GND, respectively, and when the control signal CONT1is L level, the nodes N1and N2are connected to ground GND and the power supply VCC, respectively. Hereinafter, in an embodiment of the present invention, a state where the nodes N1and N2are connected to the power supply VCC and ground GND, respectively, is designated as a first sate, and a state where the nodes N1and N2are connected to the ground GND and the power supply VCC, respectively, is designated as a second state.

In the second switch circuit21, the output voltages VS1and VS2from the sensor10are respectively applied to one-side ends of switches SW10and SW11, the output voltages VS3and VS4from the sensor11are respectively applied to one-side ends of switches SW12and SW13, and the output voltages VS5and VS6from the sensor12are applied to one-side ends of switches SW14and SW15. According to an embodiment of the present invention, it is assumed that when the control signal CONT2is H level, only the switches SW10and SW11are turned on so that the output voltages VS1and VS2from the sensor10are output as the output signals AO1and AO2. Similarly, it is assumed that when the control signal CONT3is H level, only the switches SW12and SW13are turned on so that the output voltages VS3and VS4are output as the output signals AO1and AO2, and when the control signal CONT4is H level, only the switches SW14and SW15are turned on so that the output voltages VS5and VS6are output as the output signals AO1and AO2. It is also assumed that when the control signals CONT2to CONT4are L level, the switches SW10to SW15are turned off.

The preamplifier30in the processing circuit22is a circuit for amplifying the output signals AO1and AO2output from the second switch circuit21by a predetermined gain, to be output to the delta-sigma modulation circuit31.

The delta-sigma modulation circuit31is a circuit for outputting a signal input from the preamplifier30as a one-bit digital signal DO in synchronization with the clock signal CLK input from the control circuit23. As shown inFIG. 2, in an embodiment according to the present invention, a rate of the digital signal DO being H level increases as the output signal AO1becomes greater in level than the output signal AO2, and a rate of the digital signal DO being L level increases as the output signal AO1becomes smaller in level than the output signal AO2. That is, the delta-sigma modulation circuit31is assumed to be designed such that the digital signal DO stays H level when the output signal AO1is greater in level than the output signal AO2sufficiently (AO1>>AO2), and the digital signal DO stays L level when the output signal AO1is smaller in level than the output signal AO2sufficiently (AO1<<AO2). Furthermore, the delta-sigma modulation circuit31is assumed to be designed such that the rate of the digital signal DO being H level and the rate of the digital signal DO being L level are the same when the output signal AO1and the output signal AO2are the same in level and each of voltages thereof is VCC/2 (AO1=AO2=VCC/2), that is, when an acceleration of the x-axis is zero. As mentioned above, the sensor10is designed such that the voltage value of the output voltage VS1and the voltage value of the output voltage VS2output from the sensor10are exchanged with each other when the polarity of the voltage between the node N2and the node N1is reversed. Therefore, when a state of the nodes N1and N2is changed from the first state to the second state, a difference between the output signal AO1and the output signal AO2is also reversed, and the rate of the digital signal DO being H level and the rate of the digital signal DO being L level are also reversed.

The digital filter32is a circuit which attenuates high frequency noise in the digital signal DO, and converts the one-bit digital signal DO into a multi-bit digital signal OUT. As will be described later in detail, the digital filter32according to an embodiment of the present invention operates as an adding circuit when the reversal signal REV is L level, and operates as an adding circuit which performs a complementary operation by two's complement when the reversal signal REV is H level, in order to attenuate the high frequency noise of the digital signal DO and output the multi-bit digital signal OUT as mentioned above. The delta-sigma modulation circuit31and the digital filter32makes up a delta-sigma AD converter. The digital filter32according to an embodiment of the present invention operates with the same clock signal CLK as the clock signal CLK input to the delta-sigma modulation circuit31.

The output interface circuit33is a circuit for outputting the digital signal OUT to the microcomputer (not shown) as the data DATA in response to the output instruction signal CS of H level input from the control circuit23.

As shown inFIG. 3, the digital filter32according to an embodiment of the present invention includes a FIR filter40, an adding circuit41, a shift circuit42, D flip-flops50to53, selectors60to63, an inverter70, and an AND circuit71. The FIR filter40, the adding circuit41, the D flip-flops50to53, the selectors60to63, the inverter70, and the AND circuit71correspond to an up-down counter according to an embodiment of the present invention, the FIR filter40corresponds to a filter according to an embodiment of the present invention, the adding circuit41, the D flip-flops50to53, the selectors60to63, the inverter70, and the AND circuit71corresponds to an adding and subtracting circuit according to an embodiment of the present invention, and the shift circuit42corresponds to a shift operation circuit according to an embodiment of the present invention.

First, circuits making up the digital filter32will be described in detail.

The FIR filter40is a filter holds and adds, for example, 16 bits of the one-bit digital signal DO which is input in sequence from the delta-sigma modulation circuit31in synchronization with the clock signal CLK, and outputs an addition result as 4-bit output signals O1to O4, in synchronization with the clock signal CLK, in order to attenuate the high frequency component in the one-bit digital signal DO. In an embodiment according to the present invention, it is assumed that a filter order is 16 and a filter factor of each order is 1. The output signals O1to O4correspond to 4-bits in order from the most significant bit to the least significant bit.

The output signals O1to O4from the FIR filter40are respectively input to D inputs of the D flip-flops50to53. Since the clock signals CLK1output from the AND circuit71are input to C inputs of the D flip-flops50to53based on the clock signal CLK when the enable signal CE is H level, the output signals O1to O4of the FIR filter40are respectively output in sequence from Q outputs of the D flip-flops50to53based on the clock signal CLK1. Signals obtained by reversing the output signals O1to O4of the FIR filter40are respectively output from QN outputs of the D flip-flops50to53based on the clock signal CLK1.

The selector60is a circuit that outputs a signal input to an X1input thereof from a Y output thereof when a signal of H level is input to an S input, and that outputs a signal input to the X2input thereof from the Y output when a signal of L level is input to the S input thereof. In an embodiment according to the present invention, it is assumed that the selectors61to63are the same as the selector60, and the signals output from Y outputs of the selectors60to63are the output signals SO1to SO4, respectively. The Q outputs from the D flip-flops50to53are input to X1inputs of the selectors60to63, and the QN outputs from the D flip-flops50to53are input to X2inputs of the selectors60to63. Since the signal of H level is input from the inverter70to S inputs of the selectors60to63when the reversal signal REV is L level, data of bits of the output signals O1to O4are output from the Y outputs of the selectors60to63as the output signals SO1to SO4. On the other hand, when the reversal signal REV is H level, the data obtained by reversing bits of the output signals O1to O4are output from the Y outputs of the selectors60to63as the output signals SO1to SO4accordingly. The adding circuit41is a circuit that sequentially adds the output signals S01to SO4output from the selectors60to63in synchronization with the clock signal CLK1, and the reversal signal REV, and that includes full adders80to89and D flip-flops90to99illustrated inFIG. 4.

The full adder80is a circuit that adds a one-bit signal input to an A input thereof, a one-bit signal input to a B input thereof, and a one-bit carry signal input to a CI input thereof, and outputs a one-bit addition result from an S output thereof, and outputs a one-bit carry signal from a CO output thereof. In an embodiment according to the present invention, it is assumed that the full adders81to89are also the same as above. The S output of the full adder80is connected with a D input of the D flip-flop90, and a Q output of the D flip-flop90is connected with the B input of the full adder80. Here, an operation will be described of the full adder80and the D flip-flop90by giving an example of a case where the pulse signal which is H level for a predetermined period is input twice to a C input of the D flip-flop90. It is assumed that the reset signal RST is H level. First, when a first pulse signal is input to the C input of D flip-flop90, the addition result (hereinafter, “first addition result”) output from the S output of the full adder80is output from a Q output of the D flip-flop90. Therefore, the first addition result is input to the B input of the full adder80, and is further added to the signals input to the A input and the CI input of the full adder80. An addition result of the above-mentioned first addition result input to the B input and the signals input to the A input and the CI input is designated as a “second addition result.” Next, when a second pulse signal is input to the C input of the D flip-flop90, the second addition result is output from the Q output. That is, the full adder80and the D flip-flop90serve as a circuit for adding a one-bit signal input to the A input of the full adder80, a one-bit signal input to the B input thereof, and a one-bit signal input to the CI input sequentially, and outputting the addition result from the Q output of the D flip-flop90, based on the clock signal input to the C input of the D flip-flop90. The S outputs and the B inputs of the full adders81to89are connected with the D inputs and the Q outputs of the D flip-flops91to99, respectively. That is, the adding circuit41according to an embodiment of the present invention is a 10-bit adding circuit.

Here, when the reversal signal REV is L level, 0 (zero) is input to the CI input of the full adder89and the output signals SO1to SO4input to the A inputs of the full adders86to89are the output signals O1to O4output from the FIR filter40. Therefore, the output signals O1to O4are sequentially added based on the clock signal CLK1. On the other hand, when the reversal signal REV is H level, 1 is input to the A inputs of the full adders80to85and the CI input of the full adder89, and the output signals SO1to SO4input to the A inputs of the full adders86to89are signals obtained by reversing bits of the output signals O1to O4output from the FIR filter40. Therefore, when the reversal signal REV is H level, the output signals O1to O4become in two's complement representation and are sequentially added, based on the clock signal CLK1. That is, when the reversal signal REV is H level, the output signals O1to O4are sequentially subtracted. According to an embodiment of the present invention, signals output from Q outputs of the D flip-flops90to99are designated as output signals AD1to AD10. In the adding circuit41, the output signals AD1to AD10correspond to 10-bits in order from the most significant bit to the least significant bit. Since the D flip-flops90to96are reset when the reset signal RST is L level, the output signals AD1to AD10are reset.

The shift circuit42according to an embodiment of the present invention is a circuit that performs a one-bit right shift based on the reversal signal REV for higher-order 7-bit output signals AD1to AD7among the 10-bit output signals AD1to AD10output from the adding circuit41, to be output as 6-bit output signals OUT1to OUT6, and includes selectors100to105. As mentioned above, since the adding circuit41sequentially adds or subtracts the output signals O1to O4in synchronization with the clock signal CLK1, it can attenuate the high frequency component in the one-bit digital signal DO as well as the FIR filter40. Since it is required to add or subtract the output signals O1to O4in synchronization with the clock signal CLK1during a long period in order to increase an amount of attenuation of the high frequency component, the number of bits of the adding circuit41increases as a result, and when processing all the outputs from the adding circuit41by the microcomputer (not shown,) a load on the microcomputer (not shown) increases. In a case where an addition period or subtraction period in an adding circuit is made longer, an influence that a low-order bit has on an addition result or subtraction result becomes small. Therefore, in an embodiment of the present invention, lower-order 3 bits having little influence on an addition result or subtraction result are discarded, and higher-order 7 bits of the output signals AD1to AD7are input to the shift circuit42as mentioned above. The selectors100to105are the same as the above-mentioned selectors60to63. According to an embodiment of the present invention, output signals AD1to AD6are input to X1inputs of the selectors100to105, respectively and the output signals AD2to AD7are input to X2inputs of the selectors100to105. The reversal signal REV is input to each of S inputs of the selectors100to105. In an embodiment of the present invention, signals output from Y outputs of the selectors100to105are designated as the output signals OUT1to OUT6. Therefore, when the reversal signal REV is L level, the output signals AD2to AD7are output among the output signals AD1to AD7as the output signals OUT1to OUT6, and when the reversal signal REV is H level, the output signals AD1to AD6obtained by performing the one-bit right shift therefor are output among the output signals AD1to AD7as the output signals OUT1to OUT6.

Next, an example will be described of an operation of the digital filter32. Here, it is assumed that every time the one-bit digital signal DO is input to the FIR filter40based on the clock signal CLK, for example, the output signals O1to O4defined as (O1, O2, O3, O4)=(0, 1, 1, 0) “6 in a decimal number” are output. Both of the reset signal RST and enable signal CE are assumed to be H level, unless otherwise specified.

First, a case will be described where the reversal signal REV is L level, that is, a case where the adding circuit41performs adding processing. When the reversal signal REV is L level, signals input to the S inputs of the selectors60to63are H level. Therefore, the data input to X1inputs of the selectors60to63are output from the Y outputs thereof, so that the output signals SO1to SO4defined as (SO1, SO2, SO3, SO4)=(0, 1, 1, 0) are sequentially output based on the clock signal CLK1. The output signals S01to SO4are input to the A inputs of the full adders86to89in the adding circuit41, respectively. The reversal signal REV of L level, i.e., 0 (zero) is input to each of A inputs of the full adders80to85and the CI input of the full adder89.

As mentioned above, the full adders80to89and the D flip-flops90to99make up a 10-bit adding circuit, and the output signals SO1to SO4defined as (SO1, SO2, S03, SO4)=(0, 1, 1, 0) are sequentially added.

Furthermore, a case where the output signals SO1to SO4defined as (SO1, SO2, S03, SO4)=(0, 1, 1, 0) are sequentially input to the adding circuit41, a result becomes the output signals AD1to AD10defined as (AD1, AD2, AD3, AD4, AD5, AD6, AD7, AD8, AD9, AD10)=(0, 0, 1, 0, 0, 0, 1, 1, 0, 0) “140 in a decimal number.” In this case, the output signals AD2to AD7among the output signals AD1to AD7are output from the shift circuit42as the output signals OUT1to OUT6as mentioned above. Therefore, the addition result in a case where the lower-order 3 bits are discarded among the 10-bit output signals AD1to AD10is expressed as the output signals OUT1to OUT6accordingly, which are the output signals OUT1to OUT6defined as (OUT1, OUT2, OUT3, OUT4, OUT5, OUT6)=(0, 1, 0, 0, 0, 1) “136 in a decimal number.” Thus, in the case where the reversal signal REV is L level, when the output signals O1to O4from the FIR filter40corresponding to the one-bit digital signal DO are sequentially added based on the clock signal CLK1, an addition result almost equal to a 10-bit addition result is output as a 6-bit digital signal.

Next, a case will be described where the reversal signal REV is H level, that is, a case where the adding circuit41performs subtraction processing. When the reversal signal REV is H level, signals input to the S inputs of the selectors60to63are L level. Therefore, the data input to X2inputs of the selectors60to63are output from the Y outputs thereof. Since signals obtained by reversing the output signals O1to O4defined as (O1, O2, O3, O4)=(0, 1, 1, 0) “6 in a decimal number” from the FIR filter40are output to the X2inputs of the selectors60to63from the QN outputs of the D flip-flops50to53, the output signals SO1to SO4defined as (SO1, SO2, S03, SO4)=(1, 0, 0, 1) are sequentially output based on the clock signal CLK1as the output signals SO1to SO4accordingly. The reversal signal REV of H level, i.e., 1 is input to each of the A inputs of the full adders80to85and the CI input of the full adder89. Therefore, in a case where “128 in a decimal number” is held in the adding circuit41, when the output signals SO1to SO4defined as (SO1, SO2, SO3, SO4)=(1, 0, 1, 0) and “1” to the A inputs of the full adders80to85are input, respectively, a result becomes the output signals AD1to AD10defined as (AD1, AD2, AD3, AD4, AD5, AD6, AD7, AD8, AD9, AD10)=(0, 0, 0, 1, 1, 1, 1, 0, 1, 0) “122 in a decimal number.”

Furthermore, a case where the output signals SO1to SO4defined as (SO1, SO2, S03, SO4)=(1, 0, 1, 0) and “1” to the A inputs of the full adders80to85are sequentially input to the adding circuit41, a result becomes the output signals AD1to AD10defined as (AD1, AD2, AD3, AD4, AD5, AD6, AD7, AD8, AD9, AD10)=(0, 0, 0, 1, 1, 1, 0, 1, 0, 0) “116 in a decimal number.” Thus, in the case where the reversal signal REV is L level, the output signals O1to O4from the FIR filter40corresponding to the one-bit digital signal DO are sequentially subtracted based on the clock signal CLK1, to be output as a 10-bit digital signal. The output signals AD1to AD7obtained by discarding the lower-order 3 bits among the 10-bit output signals AD1to AD10of the adding circuit41are input to the shift circuit42. Therefore, the output signals AD1to AD7defined as (AD1, AD2, AD3, AD4, AD5, AD6, AD7)=(0, 0, 0, 1, 1, 1, 0) “112 in a decimal number” are input to the shift circuit42. Hereinafter, in an embodiment of the present invention, the lower-order 3 bits are not expressed when the output signals AD8to AD10of the lower-order 3 bits are discarded. In this case, the 7-bit output signals AD1to AD7obtained by performing the one-bit right shift are output as the output signals OUT1to OUT6from the shift circuit42, as mentioned above. Therefore, the output signals OUT1to OUT6become the output signals OUT1to OUT6defined as (OUT1, OUT2, OUT3, OUT4, OUT5, OUT6)=(0, 0, 0, 1, 1, 1) “56 in a decimal number” accordingly.

Here, an operation of the sensor circuit15will be described, referring to a timing chart of main signals in the sensor circuit15shown inFIG. 5, and an example of an output of the digital filter32shown inFIG. 6.

First, at time T1inFIG. 5, the control circuit23outputs the control signal CONT1of H level so that the nodes N1and N2are made in the first state where the nodes N1and N2are connected to the power supply VCC and the ground GND, respectively, outputs the control signal CONT2of H level so that the output from the sensor10of the x-axis is selected, and outputs the control signals CONT3and CONT4of L level. Further, at the time T1, the control circuit23outputs the reset signal RST of L level for a predetermined period so that the adding circuit41in the digital filter32is reset, and outputs the reversal signal REV of L level so that the adding circuit41performs adding processing. At the time T1when the nodes N1and N2are made in the first state, levels of the output signals AO1and AO2from the sensor10are not stabilized, and therefore, in a embodiment of the present invention, the enable signal CE of L level is input to the digital filter32so that the adding circuit41does not operate based on the output signals SO1to SO4and the clock signal CLK1which are output from the FIR filter40at the time T1.

At time T2when the levels of output signals AO1and AO2are stabilized, the control circuit23outputs the enable signal CE of H level so that the processing circuit22processes the output signals AO1and AO2. In an embodiment according to the present invention, a period from the time T2to time T3during which the enable signal CE is H level is designated as a period TA. According to an embodiment of the present invention, the period TA is a period during which the addition result of the adding circuit41, which performs adding processing when the digital signal DO being always H level as exemplified inFIG. 2is input to the digital filter32, is from 0 (decimal number to 512 (decimal number.) That is, the period TA is a period during which the output signals AD1to AD7of the adding circuit41are from (AD1, AD2, AD3, AD4, AD5, AD6, AD7)=(0, 0, 0, 0, 0, 0, 0) to (AD1, AD2, AD3, AD4, AD5, AD6, AD7)=(1, 0, 0, 0, 0, 0, 0). By setting up the above period TA, the adding circuit41can express the digital signal DO corresponding to the levels of the output signals AO1and AO2as a number which is any number among 0 to 512 (decimal number.) When assuming that offsets of the preamplifier30and the delta-sigma modulation circuit31are zero, for example, an addition result of the adding circuit41is 512 (decimal number) in a state where the nodes N1and N2is in the first state, while an addition result thereof is 0 (decimal number) in a state where the nodes N1and N2are in the second state since the rate of the digital signal DO being H level and the rate of the digital signal DO being L level are reversed, as mentioned above. When an addition result of the adding circuit41is 448 (decimal number) in a state where the nodes N1and N2is in the first state, an addition result thereof becomes 64 (decimal number) in a state where the nodes N1and N2is in the second state. That is, when an addition result of the adding circuit41is x in the first state, an addition result is 512-x (decimal number) in the second state.

Hereinafter, a description will be made by giving an example of a case where such a digital signal DO in the digital filter32that the 6-bit output signals OUT1to OUT6are set at 448 (decimal number) is output from the delta-sigma modulation circuit31at the time T3when the period TA has passed since the time T2, as shown inFIG. 6, in an embodiment of the present invention. That is, the output signals AD1to AD7defined as (AD1, AD2, AD3, AD4, AD5, AD6, AD7)=(0, 1, 1, 1, 0, 0, 0) “448 in a decimal number” are held in the output signals AD1to AD7of the adding circuit41at the time T3. The digital signal DO from the delta-sigma modulation circuit31corresponds to a level difference between the output signals AO1and AO2, and the offsets in the preamplifier30and the delta-sigma modulation circuit31. Here, when a signal showing the level difference between the output signals AO1and AO2is designated as an output signal SIG, and the offsets in the preamplifier30and the delta-sigma modulation circuit31are designated as an offset signal OST obtained by converting the offsets assuming that the offsets are generated in the input in the preamplifier30, the digital signal DO and the addition result of the adding circuit41change according to a sum of the output signal SIG and the offset signal OST. Hereinafter, in an embodiment of the present invention, it is assumed that 416 (decimal number) is added by the output signal SIG and 32 (decimal number) is added by the offset signal OST, for example, out of 448 (decimal number) which is an addition result of the adding circuit41.

At time T4, the control circuit23changes the control signal CONT1into L level from H level so that a level of the output signal AO1and a level of the output signal AO2are exchanged with each other, and the nodes N1and N2are changed in state from the first state into the second state. Furthermore, the control circuit23changes the reversal signal REV into H level from L level so that the adding circuit41in the digital filter32performs subtraction processing. In this case, since the enable signal CE is L level and the addition result of the adding circuit41is not updated, the output signals AD1to AD7of the adding circuit41are not changed so that the output signals AD1to AD7defined as (AD1, AD2, AD3, AD4, AD5, AD6, AD7)=(0, 1, 1, 1, 0, 0, 0) “448 in a decimal number” are held. In the shift circuit42, the one-bit right shift is performed for the output signals AD1to AD7. Therefore, 6 bit outputs of the digital filter32at the time T4become the output signals OUT1to OUT6defined as (OUT1, OUT2, OUT3, OUT4, OUT5, OUT6)=(0, 1, 1, 1, 0, 0) “224 in a decimal number,” that is half of 448 (decimal number) which is 6 bit outputs in the digital filter32at the time T3.

Furthermore, at time T5when the levels of the output signals AO1and AO2are stabilized, the control circuit23outputs the enable signal CE of H level so that the output signals SO1to SO4and the clock signal CLK1are input to the adding circuit41. The period from the time T5to T6is assumed to be the period TA equivalent to the period from the time T2to T3. Here, since 416 (decimal number) out of addition results in the period TA from the time T2to T3is assumed to be added by the output signal SIG as mentioned above, only 96 (96=512−416) is subtracted by the output signal SIG in the period TA from the time T5to T6by changing a state of the nodes N1and N2to the second state and exchanging the levels of output signals AO1and AO2. On the other hand, even if the nodes N1and N2is made in the second state so that the processing of the adding circuit41is changed into subtraction from addition, a bias state of the preamplifier30and the delta-sigma modulation circuit31are not changed, and therefore, the offset signal OST does not change. Accordingly, a value to be subtracted by the offset signal OST in the period TA from the time T5to T6is 32 which is equivalent to a value to be added in the period TA from the time T2to T3. Therefore, in the period TA equivalent to the period from the time T2to T3and the period from time T5to T6, the values of the output signals AO1and AO2are exchanged with each other and the addition and subtraction processing is performed, so that only the offset signal OST can be canceled as well as only the output signal SIG can be output. In specific, first, in the adding processing in the period from the time T2to T3, 416 (decimal number) by the output signal SIG and 32 (decimal number) by the offset signal OST are added, so that 448 (decimal number) is held as an addition result in the adding circuit41. Next, in the subtraction processing in the period from the time T5to T6, 96 (decimal number) by a reversed output signal SIG and 32 (decimal number) by the offset signal OST are subtracted from the addition result. That is, the offset signal OST is canceled since 32 (decimal number) is subtracted after 32 (decimal number) added, and the output signal SIG is set to 320 (decimal number) since 96 (decimal number) is subtracted after 416 (decimal number) added. Thus, only the output signal SIG is output as the output signals AD1to AD7from the adding circuit41. In the digital filter32according to an embodiment of the present invention as mentioned above, when the reversal signal REV of H level is output so that the subtraction processing is performed in the adding circuit41, the one-bit right shift is performed for the output signals AD1to AD7from the adding circuit41, resulting in the output signals OUT1to OUT6. Therefore, 160 (decimal number) is output as the output signals OUT1to OUT6from the digital filter32, as a result.

Furthermore, at time T7, the control circuit23outputs the output instruction signal CS of H level, so as to send 160 (decimal number) which is an output from the digital filter32to the microcomputer (not shown) through the output interface33. At time T8and thereafter, a timing chart indicates that an output of the sensor11of the y-axis is selected, and the output from the sensor11is made into the digital signals OUT1to OUT6, to be sent to the microcomputer (not shown,) and the same process as that of the x-axis is performed. The same process is performed also as for the sensor12of the z-axis.

In the sensor circuit15according to an embodiment of the present invention including a configuration described above, the digital signal DO output from the delta-sigma modulation circuit31is added in the adding circuit41in the digital filter32during the period TA from the time T2to T3, after the nodes N1and N2in the sensor10are changed in state into the first state at the time T1. Furthermore, in the sensor circuit15, the digital signal DO output from the delta-sigma modulation circuit31is subtracted in the adding circuit41in the digital filter32during the period TA from the time T5to T6, after the nodes N1and N2in the sensor10are changed in state into the second state from the first state at the time T4. As a result, in the adding circuit41the offset signal OST can be cancelled among the offset signal OST representing the offsets of the preamplifier30and the delta-sigma modulation circuit31and the output signal SIG representing a difference between the output signals AO1and AO2, and only the output signal SIG can be converted into the 7-bit output signals AD1to AD7. Therefore, according to an embodiment of the present invention, since the process for cancelling the offset signal OST by the microcomputer (not shown), for example, is not required, it is possible to reduce a process of the microcomputer (not shown.) Furthermore, according to an embodiment of the present invention, the offset adjustment to each circuit of the preamplifier30and the delta-sigma modulation circuit31is not required. Moreover, when compared to a case of using a chopper amplifier for adjusting an offset of the preamplifier30, for example, the offsets of both the preamplifier30and the delta-sigma modulation circuit31can be cancelled according to an embodiment of the present invention, so that the offset adjustment can be performed with high accuracy.

According to an embodiment of the present invention, the one-bit digital signal DO output from the delta-sigma modulation circuit31is subjected to filtering in the FIR filter40to be output as the 4-bit output signals O1to O4, and then the addition or subtraction processing is performed in the adding circuit41. Addition or subtraction processing of the one-bit digital signal DO can be a processing where the digital signal DO is input to the up-down counter including a common T flip-flop, added by performing up counting, and subtracted by performing down counting, for example. However, when using the up-down counter including the above-mentioned common T flip-flop, since the digital signal DO is required to be directly input to the up-down counter including the T flip-flops, filtering cannot be performed for the digital signal DO in the FIR filter40, for example, as in an embodiment of the present invention. Therefore, according to an embodiment of the present invention, when compared to a case of using the up-down counter including a common T flip-flop, for example, noise of the high frequency of the digital signal DO can be more reduced. Furthermore, a case will be described where such a digital signal DO is output that an addition result of the adding circuit41at the time T3is 480 (decimal number) or 32 (decimal number), for example. Here, it is assumed that the offset signal OST is zero. First, in a case where an addition result of the adding circuit41at the time T3is 480 (decimal number,) when the nodes N1and N2is changed in a state into the second state from the first state at the time T4, the rate of the digital signal DO being H level and the rate of the digital signal DO being L level are also reversed, and therefore, 32 (decimal number) is subtracted during a period from the time T5to T6. Accordingly, an addition result of the adding circuit41at the time T6becomes 448 (decimal number.) On the other hand, in a case where the addition result of the adding circuit41at the time T3is 32 (decimal number,) when the nodes N1and N2is changed in a state into the second state from the first state at the time T4, 480 (decimal number) is subtracted at the time T5to T6as a result. Therefore, an addition result of the adding circuit41becomes −448 (decimal number.) Thus, according to an embodiment of the present invention, 7 bits are required for expressing an addition result at the time T6by subtracting 6-bit data from the time T5to T6from 6-bit data from the time T2to T3. According to an embodiment of the present invention, in the shift circuit42, the 7-bit output signals AD1to AD7of the adding circuit41are subjected to the one-bit right shift to be output as the 6-bit output signals OUT1to OUT6, and therefore, the number of bits can be reduced from 7 bits to 6 bits.

According to an embodiment of the present invention, lower-order 3 bits are discarded among the output signals AD1to AD10output from the 10-bit adding circuit41, and only the high-order 7-bit output signals AD1to AD7are input to the shift circuit42, as mentioned above. Therefore, when comparing an embodiment of the present invention with a configuration where the adding circuit41is the 7-bit adding circuit and all the output signals output from the 7-bit adding circuit are input to the shift circuit42, for example, addition and subtraction can be performed during a long period when performing the addition or subtraction with the clock signal having the same frequency, with reducing an error in an addition or subtraction result, in an embodiment of the present invention. That is, since integration time of input data becomes long, it is possible to enhance attenuation of the high frequency component in the one-bit digital signal DO.

The above embodiments of the present invention are simply for facilitating the understanding of the present invention and are not in any way to be construed as limiting the present invention. The present invention may variously be changed or altered without departing from its spirit and encompass equivalents thereof.

In an embodiment of the present invention, although the one-bit right shift is performed for the output signals AD1to AD7in the shift circuit42at the time T4, it is not limited to this timing. The one-bit right shift may be performed in any timing in a period from the time T1to the time T6shown inFIG. 6. Moreover, for example, the one-bit right shift may always be performed for the output signals AD1to AD7while the sensor circuit15according to an embodiment of the present invention is operating, with the S inputs of the selectors100to105being fixed to H level.

Moreover, in an embodiment of the present invention, although the delta-sigma modulation circuit31and the FIR filter40are operated with the clock signal CLK having the same frequency, this is not limitative. For example, if an increase in power consumption is allowed, a frequency of the clock signal with which the FIR filter40operates may be twice the frequency with which the delta-sigma modulation circuit31operates. When the frequency of the clock signal with which the FIR filter40operates is made twice, as mentioned above, since a folding frequency in the FIR filter40becomes high as compared with a case where the FIR filter40operates with the clock signal having the same frequency, the noise of the high frequency of the digital signal DO can be more reduced. If the clock signal with which FIR filter40operates is made twice, the number of bits output from the FIR filter40is twice, and therefore, the numbers of the D flip-flop and the selector shown inFIG. 3are required to be increased by one, accordingly.

Although the digital filter32according to an embodiment of the present invention performs adding processing and subtraction processing based on the rate of the digital signal DO being H level, a configuration may be made, for example, by using a common up-down counter such that when the nodes N1and N2of the sensor10are in the first state, a count value of the up-down counter is increased during a predetermined period based on the rate of the digital signal DO being H level, when the nodes N1and N2of the sensor10are in the second state, a count value of the up-down counter is decreased during the same predetermined period as that in the first state based on a calculation result obtained by calculating the rate of the digital signal DO being H level based on the rate of digital signal DO being L level.