Thin film field effect transistors having Schottky gate-channel junctions

An active electronic device has drain and source electrodes that make ohmic conduct with a layer of a semiconductor. The semiconductor layer may be a thin layer of an organic or amorphous semiconductor. The drain and source electrodes are on a first face of the layer of semiconductor at locations that are spaced apart on either side of a channel. The device has a gate electrode on a second face of the layer of semiconductor adjacent to the channel. The gate electrode makes a Schottky contact with the semiconductor to produce a depletion region in the channel. The gate electrode may encapsulate the channel so that the channel is protected from contact with oxygen, water molecules or other materials in the environment. In some embodiments, the device has an additional gate electrode separated from the semiconductor layer by an insulating layer. Such embodiments combine features of OFETs and MESFETs.

TECHNICAL FIELD

The invention relates to field effect transistors. The invention has application, for example, in field effect transistors based on organic or amorphous semiconductors.

BACKGROUND

Devices based on organic semiconductors can be inexpensive to fabricate. Such devices have promise for making very inexpensive electronic products. Organic devices have particular advantages over conventional silicon-based devices in large area devices (e.g. displays) or in moderate quantities (where the economies of scale offered by silicon fabrication are not available).

Many organic semiconductors are soluble in organic solvents. It is possible to deposit thin films of such materials (typically less than 1 μm in thickness) by various methods such as spin coating, inkjet printing, and micro stamping. Other organic semiconductors can be deposited by thermal evaporation in vacuum or single crystal growth methods.

Transistors are important components in various electronic circuits and integrated circuits. The Thin Film Transistor (TFT) structure is a common structure for making transistors that incorporate organic semiconductors. A TFT is a type of Isolated Gate Field Effect Transistor (IGFET) and its structure is very similar to that of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). A TFT made of organic semiconductors is usually called an Organic FET or OFET.

FIG. 1shows an OFET10. OFET10is formed on a substrate12and comprises a gate electrode14separated from a semiconductor15by an insulating layer16. Source and drain electrodes17and18are deposited on either side of a channel19in semiconductor15.FIG. 1Ashows an alternative OFET10A which differ from OFET10primarily in that source17and drain18lie under semiconductor15.

Since the mobility of one type of carrier (electron or hole) in organic semiconductors is usually much higher than the other, organic semiconductor devices can generally be considered to be single-carrier devices. OFETs typically work either in accumulation or depletion modes.

If applying a voltage to the gate causes accumulation of carriers at the semiconductor/insulator interface, the conductance between the drain and the source increases, which is referred to as the accumulation mode. In order to decrease the channel conductance the opposite voltage can be applied to the gate to repel carriers not only from the semiconductor/insulator interface but also from the bulk of the semiconductor. Switching between accumulation and depletion modes can be used in digital logic applications. OFETs produced by simple deposition methods such as inkjet printing and stamping have shown very poor molecular order at the semiconductor/insulator interface. Such OFETs have suffered from poor performance in accumulation mode, presumably because they exhibit very poor molecular order at the semiconductor/insulator interface. Poor molecular order results in low carrier mobility. OFETs that provide improved performance have been made by growing single crystals of small semiconductor organic molecules. However, single crystal growth is a very expensive fabrication method, which substantially increases the final product price.

Another problem with current OFETs is that switching a typical OFET from the accumulation mode to the depletion mode needs a large change in the gate voltage (usually more than 40 volts). The reason that such a wide range of voltage is needed relates to the conductivity of the bulk semiconductor at subthreshold voltages. In order to reduce the conductivity of the channel in the depletion mode, carriers have to be removed from the bulk semiconductor. This can be done by applying a voltage across the semiconductor. However a significant amount of the applied gate voltage is dropped across insulator16. Because insulating layer16usually has a much smaller unit capacitance than does semiconductor15, a relatively small electric field is present in the bulk of semiconductor15to push away the carriers.

The required gate voltage can be reduced by making insulating layer16thinner or by making insulating layer16of a high dielectric material. Both of these solutions greatly increase the cost of fabricating the OFET because they require advanced and complicated fabrication processes.

Another prior art device is a Metal Semiconductor Field Effect Transistor (MESFET). A MESFET works only in the depletion mode. The behavior of OFETs in the depletion mode can be modeled as a MESFET with an interfacial layer between gate and semiconductor: G. Horowitz,Organic Field-Effect Transistors, Adv. Mater 1998, 10, No. 5, pp. 365-377. It is known in the art that organic MESFETs provide inferior performance.

MESFETs based upon crystalline semiconductors, such as GaAs, are well known.FIG. 1Bshows the structure of a conventional MESFET. A semiconductor15is located on top of an insulating substrate12. Source17and drain18electrodes make Ohmic contacts to semiconductor15. A gate electrode14is made from a material which can produce a Schottky contact with semiconductor15. Since the gate is located between drain17and source18, changing the voltage between gate14and source17can change the width of the depletion region produced by the Schottky contact. This changes the cross section of the conductive channel19between drain17and source18. Consequently, modulating the gate-source voltage can modulate the drain current.

Since there is no insulating layer between gate and the semiconductor in the MESFET the gate voltage directly drops across the semiconductor, and so a smaller gate voltage is required in the MESFET in the depletion mode as compared to the OFET. Another advantage of the MESFET structure is that the characteristics of the transistor depend on the bulk properties of the semiconductor rather than the molecular structure of the interface with the gate.

A significant problem MESFETs based on organic/amorphous semiconductors is low transconductance and low conductance relative to transistors having the TFT structure. One of the effective parameters in conductance and transconductance is the channel length. Since in the conventional MESFET the gate is located between the drain and the source contacts, the channel length is equal to the sum of gate length, WG, the gap WGSbetween the gate and the source and the gap WGDbetween the gate and the drain.

Patents and applications that relate to transistors similar to those described above include:

There is a need for transistors that can be fabricated inexpensively and yet offer performance acceptable for various applications.

SUMMARY OF THE INVENTION

This invention provides active electronic devices comprising drain and source electrodes that make ohmic contact with a layer of a semiconductor. The drain and source electrodes are on a first face of the layer of semiconductor at locations that are spaced apart on either side of a channel in the layer of semiconductor. The devices also comprise a gate electrode on a second face of the layer of semiconductor adjacent to the channel. The gate electrode makes a Schottky contact with the layer of semiconductor to produce a depletion region in the channel.

The invention also provides electrical devices that include such active electronic devices and methods for making active semiconductor devices.

Further aspects of the invention and features of specific embodiments of the invention are described below.

DESCRIPTION

FIG. 2shows a transistor20according to an embodiment of the invention. Transistor20has a layer25of a semiconductor on a substrate22. A gate24is on a25first side31of semiconductor layer25. Gate24forms a Schottky contact with the material of semiconductor layer25.

A source electrode27and a drain electrode28are each in ohmic contact with semiconductor layer25. Source electrode27and drain electrode28are separated from gate24by the material of layer25. In the illustrated embodiment, source electrode27and drain electrode28are on a second side32of semiconductor layer25opposed to first side31. In the illustrated embodiment, source electrode27and drain electrode28are on substrate22. A channel29extends through semiconductor layer25between source electrode27and drain electrode28.

Gate electrode24substantially covers channel29. In the illustrated embodiment, gate electrode24also covers source electrode27and drain electrode28. Since gate24does not lie between source electrode27and drain electrode28channel29may be made very short, if desired. Decreasing the length of channel29tends to cause transconductance to increase. In general, channel29should be kept longer than the thickness of layer25to avoid the “short channel effect”. For example, channel29may be 5 or more times longer than layer25is thick. In an example embodiment, layer25has a thickness of about 100 nm and channel19has a length of about 800 nm. This length is determined by the separation between source electrode27and drain electrode28.

Transistor20may have any of a wide variety of configurations.FIG. 3shows one possible configuration. In general, the width W of channel29may be chosen to provide a desired conductivity. A transistor20may require a channel that is substantially wider than the channel of a comparable OFET to provide the same conductivity as the comparable OFET. Some simulations, that have been done with poly 3hexyl-thiophene as the semiconductor, indicate that channel29should have a width approximately twenty times wider than the width of the channel in a comparable OFET to provide the same current-carrying capacity.

Semiconductor layer25may comprise any suitable semiconductor. Layer25may be an n-type material or a p-type material. In preferred embodiments, semiconductor layer25is one or both of amorphous and organic. Suitable organic semiconductors include semiconducting organic polymers, oligomers, and small-molecule organic semiconductors. Some non-limiting examples of organic semiconductors that may be used to provide layer25are:

Most suitable organic semiconductors tend to be p-type semiconductor materials.

Layer25is preferably thin, at least in channel19. For example, layer25may have a thickness that is 1 μm or less. In some embodiments, layer25has a thickness in the range of 30 nm to 400 nm, such as approximately 100 nm. The thickness of layer25will affect the behavior of transistor20. If layer25is thick enough that, at zero applied gate voltage, the depletion region does not extend all of the way through layer25in channel19then transistor20will operate in the same manner as a depletion MESFET. If layer25is so thin that, at zero applied gate voltage, the depletion region extends all of the way through layer25in channel19then transistor20will operate in the same manner as an enhancement MESFET.

Simulations show that for the Schottky junction between rr-P3HT and an aluminum gate electrode, the depletion region has a thickness of approximately 70 nm with zero applied gate voltage. In this example case, for a transistor20to function as a depletion device, the thickness of layer25should exceed 70 nm and for the transistor20to function as an enhancement device the thickness of layer25should be less than 70 nm, for example, 50 nm.

Some non-limiting examples of inorganic amorphous semiconductors that may be used to provide layer25are:

Substrate22may be any material capable of supporting transistor20. For some applications, substrate22may advantageously be somewhat flexible. For example, substrate22may comprise a sheet of a plastic material of the type that may be used to make credit cards, identification cards and the like. For other applications, substrate22may be more rigid or more flexible.

Source and drain electrodes27and28may be of any material or materials that provide a substantially ohmic contact with the semiconductor material of layer25. Suitable materials may be chosen from metals, carbon nanotubes, suitable doped semiconductors, and electrically-conducting polymers. Which materials are most suitable for source and drain electrodes27and28depends upon whether semiconductor layer25is of an n-type semiconductor or a p-type semiconductor.

Where the semiconductor is a p-type semiconductor, source and drain electrodes27and28may be of a metal having a high work function. Some examples of such metals that also have other desirable properties are gold and platinum. Where the semiconductor is an n-type semiconductor, then the material of source and drain electrodes27and28should have a relatively low work function to provide an ohmic contact with the semiconductor material of layer25.

The material of gate electrode24should provide a Schottky contact with the semiconductor material of layer25. Where the semiconductor is an p-type semiconductor, then a metal having a low work function may be used for gate24. For example, gate24may comprise a layer of silver, calcium, cesium, magnesium or aluminum. In some embodiments, the gate electrode is of a material having a work function not exceeding 3½ eV.

Although cesium and calcium have low work functions, their reactivity may be a disadvantage in some applications. Also, small calcium ions may tend to diffuse into some organic semiconductors. Therefore, in certain applications, aluminum may be preferable to calcium, cesium or magnesium. A suitable electrically-conducting polymer that has a low work function may also be used for gate electrode24.

Preferably gate electrode24is substantially impermeable to oxygen and water such that gate electrode24protects channel29from contact with oxygen or water from the environment.

In one example embodiment, transistor20is made with source and drain electrodes27and28made of platinum, a semiconductor layer made of pentacene, and a gate electrode made of cesium.

In another example embodiment of the invention, transistor20is made with source and drain electrodes27and28made of a conducting polymer such as Poly(3,4-ethylenedioxythiophene) poly(styrenesulfonate) also known as PEDOT and available under the brand name Baytron-P™ from Bayer AG, a semiconductor layer25pentacene, and a gate electrode made of a conducting polymer that has been chemically reduced so that it has a diminished work function.

Any suitable methods may be used to fabricate a transistor20as shown inFIG. 2. For example, source and drain electrodes26and27may be fabricated by any of:

inkjet printing, or

the like.

Semiconductor layer25may be applied by any of a wide variety of techniques of which the following are non-limiting examples:

shadow masking

micro contact printing,

single crystal growth methods,

sputtering, or

the like.

Semiconductor25may be deposited in one step and then patterned subsequently or deposited in a desired pattern.

Gate electrode24may be formed by any suitable techniques such as:

inkjet printing, or

the like.

In an example fabrication method, source and gate electrodes27and28(as well as suitable interconnections) are formed on a substrate22by any suitable method. Then semiconductor layer25is deposited by an appropriate method. Finally, gate electrode24is deposited. In depositing gate electrodes24one should avoid the use of solvents that could deleteriously affect semiconductor layer25. Shadow masking is one method that may be used to deposit gate electrodes24without the use of solvents.

It is notable that the resolution of the techniques by which semiconductor layer25and gate electrode24are patterned may be significantly lower than that of the technique by which source and drain electrodes27and28are patterned. Further, since gate electrode24can overlap with source and drain electrodes27and28, it is not critical to maintain precise alignment of gate electrode24with underlying structures. The dimensions of channel19are defined primarily by the geometry of source and drain electrodes27,28. Further, since gate electrode24can overlap with source and drain electrodes27and28, it is not critical to maintain precise alignment of gate electrode24with underlying structures.

It can be appreciated that the transistor ofFIG. 2has a number of features that may be advantageous in particular applications. These include:Gate24protects channel19from contamination by oxygen, water, or other chemicals that may be present in the environment surrounding transistor20.Because gate24encapsulates channel19, no additional passive layer is needed to protect channel19. This reduces fabrication costs.Since gate24is located at a different level from drain and source electrodes27and28, the length, L (SeeFIG. 3) of channel19can be made to be as small as the gap between drain and the source electrodes27,28. Hence it is possible to fabricate a transistor like that shown inFIG. 2in which channel19is as short as the minimum feature size provided by whatever method is used to pattern drain and source electrodes27and28. This enhances the conductance and transconductance of the fabricated transistors20.Since transistor20can operate entirely in depletion mode, there is no need for the semiconductor to have a particularly high degree of order at the semiconductor/gate interface. Thus low-cost methods such as spin coating may be used to deposit semiconductor layer25.The lack of an insulating layer in transistor20reduces the number of steps in its production as compared to a comparable OFET design. This reduces the fabrication cost compared to the OFET.If gate electrode24and source and drain electrodes27and28are all made of suitable electrically conducting polymers then the transistor and even an entire electrical circuit that includes the transistor may be made without metal and through the use of low-cost fabrication techniques such as inkjet printing.

FIG. 2Ashows a transistor20A that is similar to transistor20ofFIG. 2except that the gate24is located on the same side of semiconductor layer25as substrate22while source and drain electrodes27and28are located on the opposing side of semiconductor layer25. Transistor20A has the disadvantage relative to transistor20that gate24does not encapsulate channel19.

FIG. 2Bshows a transistor20B that is similar to transistor20except that it is surrounded by an insulating barrier33. Barrier33prevents oxygen and other contaminants from diffusing into channel19from edges of the transistor20. Gate electrode24overlaps with insulating barrier33to protect semiconductor layer25from any contamination. Barrier33may also insulate transistor20B from other transistors or other electronic devices on substrate22.

FIG. 2Cis a cross section through a transistor20C that is in the form of a drop on substrate22. If the width (Wg) of gate electrode24is bigger than the diameter (Wdrop) of the drop then gate electrode24encapsulates the transistor. In such embodiment, gate electrode24may seal to substrate22around the perimeter of transistor20C (except where electrical conducting traces cross the perimeter to connect to source and drain electrodes27and28).

FIG. 2Dis a cross section through a transistor20D that combines structural features of a MESFET and a TFT. Transistor20D is made on a substrate22and has a semiconductor layer25having a gate electrode24on a first side and source and drain electrodes27and28on a second side. Transistor20D differs from transistor20in that a second gate electrode34and an insulating layer36are disposed between substrate22and semiconductor layer25.

Transistor20D has a number of advantages over a standard thin film transistor. These include:gate24provides encapsulation that protects semiconductor layer25;gates24and34may both be used to increase the gain of the transistor; and,gate24depletes the bulk of semiconductor layer25and thereby enhances characteristics such as the current on/off ratio when the transistor is used as a TFT (with gate34controlling current between source27and drain28).

As will be apparent to those skilled in the art in the light of the foregoing disclosure, many alterations and modifications are possible in the practice of this invention without departing from the spirit or scope thereof. For example:If substrate22or gate electrode24are made to be optically transparent (in a transistor20like that shown inFIG. 2) then the transistor may be operated as an optical sensor. A transistor20A like that shown inFIG. 2Amay also be operated as an optical sensor.
Accordingly, the scope of the invention is to be construed in accordance with the substance defined by the following claims.