Integrated circuit packaging system with stacking interconnect and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: fabricating a base package substrate; coupling a conductive column lead frame to the base package substrate by: providing a lead frame support, patterning a conductive material on the lead frame support including forming an interconnect securing structure, and coupling the conductive material to the base package substrate; forming a base package body between the base package substrate and the conductive column lead frame; and removing the lead frame support from the conductive column lead frame for exposing the interconnect securing structure from the base package body.

CROSS-REFERENCE TO RELATED APPLICATION(S)

The present application contains subject matter related to U.S. patent application Ser. No. 12/488,089 filed Jun. 19, 2009, now U.S. Pat. No. 7,927,917. The related application is assigned to STATS ChipPAC Ltd. and the subject matter thereof is incorporated herein by reference thereto.

TECHNICAL FIELD

The present invention relates generally to an integrated circuit packaging system, and more particularly to a system for stacking integrated circuit packages.

BACKGROUND ART

The electronic industry continues to seek products that are lighter, faster, smaller, multi-functional, more reliable and more cost-effective. The advent of multi-function electronic devices, such as cell phones that are also game platforms, cameras, Internet portals, and music or video players, has brought immense pressure on the electronics device manufacturers and the manufacturing companies that support them.

In an effort to meet such requirements, package assembly techniques have been developed for multi-chip packages (MCP) and chip stack packages. These types of packages combine two or more semiconductor chips in a single package, thereby realizing increased memory density, multi-functionality and/or reduced package footprint.

The use of several chips in a single package does, however, tend to reduce both reliability and yield. During post assembly testing, if just one chip in the multi-chip or chip stack package fails to meet the functional or performance specifications, the entire package fails, causing the good chip(s) to be discarded along with the failing chip. As a result, multi-chip and chip stack package tend to lower the productivity from the assembly process.

A 3-dimensional package stack addresses this yield problem by stacking several assembled packages that each contain a single chip and that have already passed the necessary tests, thereby improving the yield and reliability of the final composite package. However, package stacks have tended to use lead frame type packages rather than area array type packages. Lead frame type packages typically utilize edge-located terminals such as outer leads, whereas area array type packages typically utilize surface-distributed terminals such as solder balls. Area array type package may therefore provide larger terminal counts and/or smaller footprints when compared with corresponding lead frame type packages.

Attempts to form area array type packages have met with other difficulties. Positioning of the contacts within the array and alignment between the two stacked interfaces has proved a daunting problem. As the number of interface contacts increases the critical alignment between the integrated circuit package interfaces becomes even more challenging.

Thus, a need still remains for an integrated circuit packaging system with stacking interconnects, in order to meet the volume and performance needs of the electronic devices industry. In view of the public demand for smaller devices with more function, it is increasingly critical that answers be found to these problems. In view of the ever-increasing commercial competitive pressures, along with growing consumer expectations and the diminishing opportunities for meaningful product differentiation in the marketplace, it is critical that answers be found for these problems. Additionally, the need to reduce costs, improve efficiencies and performance, and meet competitive pressures adds an even greater urgency to the critical necessity for finding answers to these problems.

DISCLOSURE OF THE INVENTION

The present invention provides a method of manufacture of an integrated circuit packaging system including: fabricating a base package substrate; coupling a conductive column lead frame to the base package substrate by: providing a lead frame support, patterning a conductive material on the lead frame support including forming an interconnect securing structure, and coupling the conductive material to the base package substrate; forming a base package body between the base package substrate and the conductive column lead frame; and removing the lead frame support from the conductive column lead frame for exposing the interconnect securing structure from the base package body.

The present invention provides an integrated circuit packaging system including: a base package substrate; a conductive column having an interconnect securing structure coupled to the base package substrate; and a base package body on the base package substrate with the conductive column and the interconnect securing structure exposed on a top surface.

BEST MODE FOR CARRYING OUT THE INVENTION

Where multiple embodiments are disclosed and described, each having some features in common, for clarity and ease of illustration, description, and comprehension thereof, similar and like features one to another will ordinarily be described with similar reference numerals. The embodiments have been numbered first embodiment, second embodiment, etc. as a matter of descriptive convenience and are not intended to have any other significance or provide limitations for the present invention.

Referring now toFIG. 1, therein is shown a cross-sectional view of an integrated circuit packaging system100with stacking interconnects in an embodiment of the present invention. The cross-sectional view of the integrated circuit packaging system100depicts a base package102.

The base package102includes a base package substrate106, having a component side108and a system side110. Component pads112on the component side108may be coupled to system pads114on the system side110by internal wiring116, such as traces, vias, or a combination thereof. System interconnects118, such as solder bumps, solder balls, solder columns, or stud bumps, may be formed on the system pads114in order to couple to the next level system, not shown.

A base integrated circuit die120may be coupled to the component pad112by chip interconnects122, such as solder bumps, solder balls, or bond wires. A sealing adhesive124, such as an underfill material or a die attach material, may be applied between the component side108and the base integrated circuit die120to enclose the chip interconnects122in order to protect them from moisture or fracture due to shock.

The base integrated circuit die120is shown as a flip chip die, but this is an example only and other die configurations are possible. In other configurations of the base integrated circuit die120, the sealing adhesive124may be a die attach material.

Conductive columns126may be attached to the component pads112by a conductive adhesive128, such as solder or conductive epoxy, or by thermal compression bonding. The conductive columns126may include a seed layer130, such as a solder wettable layer or a temporary adhesive layer, deposited as part of the conductive columns126to form an interconnect securing structure132in the top of the conductive columns126.

A base package body134may be formed of an encapsulant, such as epoxy molding compound or ceramic, on the component side108, the base integrated circuit die120, the sealing adhesive124, and the conductive columns126. The base package body134leaves the seed layer130and the interconnect securing structure132exposed on a top surface.

Referring now toFIG. 2, therein is shown a cross-sectional view of a base package200with the stacking interconnects in a molding phase of manufacture. The cross-sectional view of the base package200depicts the base package substrate106having a conductive column lead frame202coupled to the component pads112by the conductive adhesive128. The base package body134may be formed by filling the space between the component side108, of the base package substrate106, and a lead frame support204.

It has been discovered that the position and alignment of the conductive columns126relative to the component pads112may be assured by the application of the conductive column lead frame202on the component side108of the base package substrate106. Also by having the lead frame support204in place during the molding process, the integrity of the electrical connection to the component pads112and the location of the conductive columns126is maintained by the base package body134.

It has also been discovered that multiple rows of the conductive columns126may be coupled to the component pads112with great precision and providing better control of the package alignment during the stacking process. In the example shown two rows of the conductive columns126are coupled to the component pads112, but it is understood that a different number of rows may be used for the base package200.

It has been discovered that the lead frame support204may be removed from the base package200by means of etching, grinding, mechanical peel, or a combination thereof. The seed layer130may act as an etch stop layer or it may provide a separation point for the mechanical peel process.

Referring now toFIG. 3, therein is shown a cross-sectional view of an integrated circuit packaging system300with the stacking interconnects in a stacked package. The cross-sectional view of the integrated circuit packaging system300depicts the conductive columns126held in precise place by the base package body134. The lead frame support204, ofFIG. 2, having been removed to leave the seed layer130and the interconnect securing structure132of each of the conductive columns126exposed from a top surface302of the base package300.

A stacked package304may be of any package configuration. The stacked package304may have a stacked substrate306that includes interconnect pads308. The interconnect pads308may be coupled to the conductive columns126by the system interconnects118. A stacked integrated circuit die310may be coupled to the base integrated circuit die120, the system interconnects118, or a combination thereof, through the conductive columns126.

It has been discovered that the conductive columns126having the interconnect securing structure132may provide a reliable stacking interconnect without alignment problems experienced by the prior art interconnects. The seed layer130in combination with the interconnect securing structure132assures proper alignment and connection by drawing the system interconnects118of the stacked package304into the interconnect securing structure during the reflow process.

Referring now toFIG. 4, therein is shown a cross-sectional view of an integrated circuit packaging system400with stacking interconnects in a first alternative embodiment of the present invention. The cross-sectional view of the integrated circuit packaging system400depicts the conductive columns126, coupled to the base package substrate106, recessed within the base package body134.

The seed layer130may be recessed within the base package body134to form an interconnect securing structure402provided by the base package body134. The position and alignment of the conductive columns126may be assured by using the conductive column lead frame202, ofFIG. 2.

Referring now toFIG. 5, therein is shown a cross-sectional view of an integrated circuit packaging system500with stacking interconnects in a second alternative embodiment of the present invention. The a cross-sectional view of the integrated circuit packaging system500depicts the conductive columns126aligned in rows about the periphery of the integrated circuit packaging system500having an array of contact pads502formed in the top surface of the base package body134.

It has been discovered that the array of contact pads502may be formed by patterning the seed layer130on the lead frame support204, ofFIG. 2. The array of contact pads502, formed of the seed layer130, may include contacts504and interconnect traces506applied to the lead frame support204prior to the formation of the base package body134. The process used to separate the lead frame support204from the integrated circuit packaging system500would leave the array of contact pads502and the conductive columns exposed on the top surface to the integrated circuit packaging system500.

Referring now toFIG. 6, therein is shown a cross-sectional view of an integrated circuit packaging system600with stacking interconnects in a third alternative embodiment of the present invention. The cross-sectional view of the integrated circuit packaging system600depicts an array of secure contacts602includes the seed layer130with the interconnect securing structure132formed therein.

The array of secure contacts602may be formed by the same process described for the array of contact pads502, ofFIG. 5. Secure contact pads604and interconnect traces606necessary for coupling the array of secure contacts602may also be patterned on the lead frame support204, ofFIG. 2.

Referring now toFIG. 7, therein is shown a cross-sectional view of a conductive post frame base700in an embodiment of the present invention. The cross-sectional view of the conductive post frame base700depicts the lead frame support204having secure interconnect forms702applied thereon.

The secure interconnect forms702may be patterned by etching, machining, deposition, adhering, or a combination thereof. It has been discovered that the precise location of the secure interconnect forms702may mirror the design of the component side108, ofFIG. 1, of the base package substrate106, ofFIG. 1and may be developed from the same data base.

Referring now toFIG. 8, therein is shown a cross-sectional view of a conductive post frame800in a seed layer deposition phase of manufacturing. The cross-sectional view of the conductive post frame800depicts the conductive post frame base700with a resist layer802patterned thereon.

The patterning of the resist layer802may provide a space around the secure interconnect forms702. The seed layer130may be deposited in patterned openings804of the resist layer802.

Referring now toFIG. 9, therein is shown a cross-sectional view of a conductive post lead frame900in the conductive post126deposition phase of manufacturing. The cross-sectional view of the conductive post lead frame900depicts the conductive columns126formed by depositing a conductive material902, such as Copper (Cu), Tin (Sn), Aluminum (Al), or an alloy thereof, to fill the patterned openings804in the resist layer802.

Referring now toFIG. 10, therein is shown a cross-sectional view of the conductive column lead frame202in a mask layer removal phase of manufacturing. The cross-sectional view of the conductive column lead frame202depicts the lead frame support204having the conductive columns126formed thereon.

It has been discovered that by carefully choosing dissimilar metals for the lead frame support204and the seed layer130, a simplified disconnect process may be utilized after the base package body134, ofFIG. 1, supports the conductive columns126. Also by careful selection of the conductive material902a solid and reliable connection may be provided. The precise locations and dimensions of the conductive columns126may be developed from the construction database for the base package substrate106, ofFIG. 1.

Referring nor toFIG. 11, therein is shown a cross-sectional view of an integrated circuit packaging system1100with stacking interconnects in a fourth alternative embodiment of the present invention. The cross-sectional view of the integrated circuit packaging system1100depicts the conductive columns126attached to the component pads112by the conductive adhesive128, such as solder or conductive epoxy. The conductive columns126may include the seed layer130, such as a solder wettable layer, deposited as part of the conductive columns126to form the interconnect securing structure132in the top of the conductive columns126.

The interconnect securing structure132of this embodiment extends above the base package body134and includes the seed layer130covering the interconnect securing structure132. The interconnect securing structure132of this embodiment may be used to control the collapse height of the system interconnects118of the stacked package304.

An array of secure contacts1102may extend across the upper surface of the base package body134. It has been discovered that the array of secure contacts1102may provide additional package reliability and prevent warping of the stacked package304.

Referring now toFIG. 12, therein is shown a top view of interconnect securing structures1200. The view of the interconnect securing structures1200depicts an interconnect securing cross1202, an interconnect securing rectangle1204, and an interconnect securing cylinder1206.

While these shapes are for an example only, other advantageous shapes may be used to help establish the interconnect securing structure132, ofFIG. 1andFIG. 11, for providing the right support for the application. It is further understood that the shapes of the interconnect securing cross1202, the interconnect securing rectangle1204, and the interconnect securing cylinder1206may either be recessed into the conductive column126, ofFIG. 1, or protrude from the conductive column126as best suits the application. The seed layer130, ofFIG. 1andFIG. 11, will provide a solder wettable surface to assure a reliable connection.

Referring now toFIG. 13, therein is shown a cross-sectional view of an integrated circuit packaging system1300with stacking interconnects in a fifth alternative embodiment of the present invention. The cross-sectional view of the integrated circuit packaging system1300depicts the stacked package304coupled to the array of secure contacts1102while leaving the conductive columns126at the periphery of the integrated circuit packaging system1300available for test connection or further stacking of additional packages.

The conductive column126having the interconnect securing structure132coated by the seed layer130is shown to be coplanar with the array of secure contacts1102, but this is an example only and the actual implementation may differ. The conductive column126must have the base package body134for support and location.

Referring now toFIG. 14, therein is shown a flow chart of a method1400of manufacture of the integrated circuit packaging system100in an embodiment of the present invention. The method1400includes: fabricating a base package substrate in a block1402; coupling a conductive column lead frame to the base package substrate by: providing a lead frame support, patterning a conductive material on the lead frame support includes forming an interconnect securing structure, and coupling the conductive material to the base package substrate in a block1404; forming a base package body between the base package substrate and the conductive column lead frame in a block1406; and removing the lead frame support from the conductive column lead frame for exposing the interconnect securing structure from the base package body in a block1408.

The resulting method, process, apparatus, device, product, and/or system is straightforward, cost-effective, uncomplicated, highly versatile and effective, can be surprisingly and unobviously implemented by adapting known technologies, and are thus readily suited for efficiently and economically manufacturing integrated circuit packaging systems with stacking interconnects fully compatible with conventional manufacturing methods or processes and technologies.