Array substrate, method for fabricating the same and display device

An array substrate, a method for fabricating the same and a display device are disclosed. The method for fabricating the array substrate includes: forming a pattern of a gate electrode, a pattern of a gate insulation layer and a pattern of a metal oxide semiconductor active layer on a base substrate; forming an etch stop layer; forming a pattern of a pixel electrode first, and then forming a pattern of a source electrode and a pattern of a drain electrode; wherein the pattern of the pixel electrode is connected to the pattern of the metal oxide semiconductor active layer through the pattern of the source electrode or the pattern of the drain electrode. The method can prevent the problem that the pattern of the pixel electrode failing to connect to the pattern of the source electrode or the pattern of the drain electrode.

The application is a U.S. National Phase Entry of International Application No. PCT/CN2014/091906 filed on Nov. 21, 2014, designating the United States of America and claiming priority to Chinese Patent Application No. 201410373777.2, filed on Jul. 31, 2014. The present application claims priority to and the benefit of the above-identified applications and the above-identified applications are incorporated by reference herein in their entirety.

FIELD OF THE ART

Embodiments of the invention relate to an array substrate, a method for fabricating the same and a display device.

BACKGROUND

In the field of display technologies having liquid crystal displays (LCD) as a representative, due to the increases of resolution and size of the display devices and the need for low resistance wiring for integrating driver circuits in display devices, metals with low resistances, such as Cu, are used to fabricate gate lines and data lines in the display devices. Moreover, gate electrodes, source electrodes and drain electrodes in thin film transistors (TFTs) are also made of Cu.

However, as metals with low resistances such as Cu are active, the surface of Cu is easily oxidized while etching is performed to form a pixel electrode. The thickness of oxidized Cu layer would increase gradually with time. Due to the above fact, contact resistances of the source electrode and the drain electrode made of Cu will increase, making it impossible to connect the pixel electrode to the drain electrode, which will compromise the yield rate of products.

SUMMARY

A first aspect of the invention provides a method for fabricating an array substrate. The method comprises: forming a pattern of a gate electrode, a pattern of a gate insulation layer and a pattern of a metal oxide semiconductor active layer on a base substrate; forming an etch stop layer; forming a pattern of a pixel electrode first, then forming a pattern of a source electrode and a pattern of a drain electrode; wherein the pattern of the pixel electrode is connected to the pattern of the metal oxide semiconductor active layer through the pattern of the source electrode or the pattern of the drain electrode.

Another aspect of the invention provides an array substrate, comprising: a base substrate, a pattern of a gate electrode, a pattern of a gate insulation layer, a pattern of a metal oxide semiconductor active layer, a pattern of an etch stop layer, a pattern of a pixel electrode, and a pattern of a source electrode and a pattern of a drain electrode sequentially disposed on the base substrate; wherein the pattern of the etch stop layer comprises a first via hole and a second via hole, the first via hole and the second via hole are configured as respectively connecting the pattern of the source electrode and the pattern of the drain electrode to the pattern of the metal oxide semiconductor active layer; the pattern of the pixel electrode is connected to the pattern of the source electrode or the pattern of the drain electrode, and the pattern of the source electrode or the pattern of the drain electrode connected to the pattern of the pixel electrode partly overlays the pattern of the pixel electrode.

Still another aspect of the invention provides a display device comprising the array substrate.

The embodiments of the invention provide an array substrate, a method for fabricating the same and a display device. The method for fabricating the array substrate comprises: forming a pattern of a gate electrode, a pattern of a gate insulation layer and a pattern of a metal oxide semiconductor active layer on a base substrate; forming an etch stop layer; forming a pattern of a pixel electrode first, then forming a pattern of a source electrode and a pattern of a drain electrode; wherein the pattern of the pixel electrode is connected to the pattern of the metal oxide semiconductor active layer through the pattern of the source electrode or the pattern of the drain electrode.

NUMERAL REFERENCES

DETAILED DESCRIPTION

In order to clearly illustrate the technical solution of the embodiments of the invention, the drawings of the embodiments will be briefly described in the following; it is obvious that the described drawings are only related to some embodiments of the invention and thus are not limitative of the invention. Based on the described embodiments herein, those skilled in the art can obtain other embodiment(s), without any inventive work, which should be within the scope of the invention.

Embodiments of the invention provide an array substrate, a method for fabricating the same and a display device, which can prevent the problem of a pattern of a pixel electrode fails to connect to a pattern of a source electrode or a pattern of a drain electrode due to surface oxidation of the pattern of the source electrode and the pattern of the drain electrode when active materials are used therefore.

As illustrated inFIG. 1, an embodiment of the invention provides a method for fabricating an array substrate. The method comprises the following steps:

S10, forming a pattern of a gate electrode10, a pattern of a gate insulation layer (not illustrated inFIG. 1) and a pattern of a metal oxide semiconductor active layer30on a base substrate.

It can be contemplated that a gate line and a gate connection and the like may further be formed while the pattern of the gate electrode10is formed. The pattern of the gate electrode, the gate line and the gate connection may be made of relatively strong active materials having low resistances such as Cu, so as to reduce the resistances.

The pattern of the metal oxide semiconductor active layer30may be made of at least one of transparent metal oxide semiconductor materials including Indium Gallium Zinc Oxide (IGZO), Indium Tin Zinc Oxide (ITZO), indium oxide (In2O3) and zinc oxide (ZnO).

S11, forming an etch stop layer on the substrate done with the step S10.

S12, forming a pattern of a pixel electrode70first on the substrate done with the step S11, and then forming a pattern of a source electrode801and a pattern of a drain electrode802; wherein the pattern of the pixel electrode70is connected to the pattern of the metal oxide semiconductor active layer30through the pattern of the source electrode801or the pattern of the drain electrode802.

The pattern of the source electrode801and the pattern of the drain electrode802may be made of a material having a low resistance and a relatively strong activity such as Cu.

As Cu has rich reserves in nature and it is conductive material with relatively low resistance, the materials of the pattern of the gate electrode10, the pattern of the source electrode801and the pattern of the drain electrode802in the embodiment of the invention are preferably Cu.

Please note the following: 1) in the embodiment of the invention, the layer finally presents on the array substrate01is referred to as a pattern of the layer, such as the pattern of the gate electrode10, the pattern of the gate insulation layer, the pattern of the metal oxide semiconductor active layer30, the pattern of the pixel electrode70, the pattern of the source electrode801, the pattern of the drain electrode802and so on. The layer in the other stages is referred to as the layer itself, such as the etch stop layer, which means corresponding operations are needed to performed on the layer so as to form the final pattern.

2) In the embodiment of the invention, the pattern of the metal oxide semiconductor active layer30is formed first, and then the etch stop layer is formed thereafter, finally, the pattern of the source electrode801and the pattern of the drain electrode802are formed. That is, the etch stop layer is disposed above the pattern of the metal oxide semiconductor active layer30, while the pattern of the source electrode801as well as the pattern of the drain electrode802is disposed above the etch stop layer. As the pattern of the source electrode801and the pattern of the drain electrode802have to be connected to the pattern of the metal oxide semiconductor active layer30, the etch stop layer has to be processed to eventually form a pattern of the etch stop layer that comprises a first via hole and a second via hole.

Based on that, those skilled in the art will understand that an etchant used on the material of the pattern of the metal oxide semiconductor active layer30and the etchant used on the material of the pixel electrode70such as ITO are the same. If the pattern of the etch stop layer comprising the first and second via holes has been formed before the pattern of the pixel electrode70, and the pattern of the pixel electrode70is to be formed directly on the pattern of the etch stop layer comprising the first and second via holes, then the pattern of the metal oxide semiconductor active layer30exposed by the first and second via holes will inevitably be etched while etching is performed to form the pattern of the pixel electrode70, thereby affecting the pattern of the metal oxide semiconductor active layer30.

Based on that, the embodiment of the invention defines only that the etch stop layer is formed before the pattern of the pixel electrode70is formed. Whether the pattern of the etch stop layer that is finally present on the array substrate01and comprises the first and second via holes is formed before or after the pattern of the pixel electrode70is formed is not defined. That is, the pattern of the etch stop layer comprising the first and second via holes may be formed by way of a patterning process to the etch stop layer after the pattern of the pixel electrode70is formed. Alternatively, the pattern of the etch stop layer comprising the first and second via holes may be formed by way of a patterning process to the etch stop layer before the pattern of the pixel electrode70is formed, in this situation, for example, other patterns of layers overlaying the first and second via holes may be further formed, thereby preventing the influence on the pattern of the metal oxide semiconductor active layer30while forming the pattern of the pixel electrode70by etching process.

3) the pattern of the pixel electrode70is connected to the pattern of the metal oxide semiconductor active layer30through the pattern of the source electrode801or the pattern of the drain electrode802, that is, on the basis that the pattern of the source electrode801and the pattern of the drain electrode802are respectively connected to the pattern of the metal oxide semiconductor active layer30, since the pattern of the pixel electrode70is directly connected to the pattern of the source electrode801or the pattern of the drain electrode802, thereby allowing the pattern of the pixel electrode70to be indirectly connected to the metal oxide semiconductor active layer30.

The embodiment of the invention provides a method for fabricating an array substrate. The method comprises: forming a pattern of a gate electrode10, a pattern of a gate insulation layer and a pattern of a metal oxide semiconductor active layer30on a base substrate; forming an etch stop layer; forming a pattern of a pixel electrode70first, and then forming a pattern of a source electrode801and a pattern of a drain electrode802; wherein the pattern of the pixel electrode70is connected to the pattern of the metal oxide semiconductor active layer30through the pattern of the source electrode801or the pattern of the drain electrode802.

On one hand, it is possible to fabricate an array substrate with a higher resolution, a better performance and a relatively big size by using the pattern of the metal oxide semiconductor active layer30and electrodes having low resistances. On the other hand, comparing with the conventional solutions of forming the pattern of the source electrode801and the pattern of the drain electrode802first and then forming the pattern of the pixel electrode70, by forming the pattern of the pixel electrode70first and then forming the pattern of the source electrode801and the pattern of the drain electrode802, it is possible to prevent the problem of the pattern of the pixel electrode70failing to connect to the pattern of the source electrode801and the pattern of the drain electrode802caused by the surface oxidation of the pattern of the source electrode801and the pattern of the drain electrode802due to the strong activity of the material having a low resistance.

Based on the above description, to connect the pattern of the source electrode801and the pattern of the drain electrode802to the pattern of the metal oxide semiconductor active layer30and to prevent the influence on the pattern of the metal oxide semiconductor active layer30while etching to form the pattern of the pixel electrode70, the following two methods may be used:

The first method: between the steps S11and S12, performing a single pattern process on the etch stop layer to form the pattern of the etch stop layer comprising the first and second via holes; and forming a pattern of a photoresist layer which is disposed outside a pixel region and overlays at least the first via hole and the second via hole.

Based on that, the step S12can be realized through for example the following steps:

S121, forming the pattern of the pixel electrode70on the substrate having the pattern of the photoresist layer formed thereon, and removing the pattern of the photoresist layer to expose the first via hole and the second via hole.

Herein, since the pattern of the photoresist layer is not present in the pixel region, it is possible to remove the exposed pattern of the photoresist layer after etching off a transparent conductive film outside the pixel region (where the pattern of the pixel electrode70is formed).

S122, forming the pattern of the source electrode801and the pattern of the drain electrode802on the substrate having the pattern of the pixel electrode70formed thereon, wherein the pattern of the source electrode801is connected to the pattern of the metal oxide semiconductor active layer30through the first via hole, the pattern of the drain electrode802is connected to the pattern of the metal oxide semiconductor active layer30through the second via hole, and the pattern of the source electrode801or the pattern of the drain electrode802is connected to the pattern of the pixel electrode70.

It is noted that, 1) the pixel region is the region where the pattern of the pixel electrode70is located. Based on that, what is meant by “the pattern of the photoresist layer is disposed outside the pixel region and overlays at least the first via hole and the second via hole” is that, the pattern of the photoresist layer is not present in the pixel region, and the existence of the pattern of the photoresist layer in other regions outside the pixel region is not explicitly defined, as long as it can overlay the first via hole and the second via hole.

2) The method of forming the pattern of the photoresist layer is not defined. It may be formed after the pattern of the etch stop layer is formed, or formed from the photoresist covering the etch stop layer and used in forming the pattern of the etch stop layer. The specific configuration depends on the actual situation, which will not be defined here.

The second method: during the step S12, after forming the pattern of the pixel electrode and before forming the pattern of the source electrode801and the pattern of the drain electrode802, it may further perform a single patterning process on the etch stop layer, so as to form the pattern of the etch stop layer comprising the first via hole and the second via hole.

Based on that, the step of the pattern of the pixel electrode70being connected to the pattern of the metal oxide semiconductor active layer30through the pattern of the source electrode801or the pattern of the drain electrode802is as follows: the pattern of the source electrode801is connected to the pattern of the metal oxide semiconductor active layer30through the first via hole, the pattern of the drain electrode802is connected to the pattern of the metal oxide semiconductor active layer30through the second via hole, and the pattern of the source electrode801or the pattern of the drain electrode802is connected to the pattern of the pixel electrode70.

With respect to the first method, the pattern of the photoresist layer is formed on the pattern of the etch stop layer comprising the first and second via holes, no other materials are needed when forming the pattern of the photoresist layer, thereby reducing the cost.

With respect to the second method, as the pattern of the etch stop layer only needs to comprise the first via hole which allows the pattern of the source electrode801to be connected to the pattern of the metal oxide semiconductor active layer30and the second via hole which allows the pattern of the drain electrode802to be connected to the pattern of the metal oxide semiconductor active layer30, the etch stop layer formed in the step S11can be a layer of unprocessed film. Thus, the pattern of the etch stop layer comprising the first and second via holes can be formed through a single pattern process on the film after the pattern of the pixel electrode70is formed and before the pattern of the source electrode801and the pattern of the drain electrode802are formed, thereby simplifying the process.

According to the first method, an embodiment of the invention provides an example to describe a process for fabricating the array substrate01in detail.

As illustrated inFIG. 2, the fabrication method comprises the following steps:

S101, as illustrated inFIG. 3, forming a pattern of a gate electrode10, a pattern of a gate insulation layer20and a pattern of a metal oxide semiconductor active layer30on a base substrate.

S102, as illustrated inFIG. 3, sequentially forming an etch stop layer40aand a first photoresist layer50aon the substrate having the pattern of the gate electrode10, the pattern of the gate insulation layer20and the pattern of the metal oxide semiconductor active layer30formed thereon.

As an example, the etch stop layer40amay be made of a compact material such as silicon nitride, silicon oxide and silicon oxynitride.

S103, as illustrated inFIG. 4, forming a first-photoresist-completely-retained region50a1and a first-photoresist-completely-removed region, after exposing and developing the base substrate having the first photoresist layer50aformed thereon by using a regular mask; wherein the first-photoresist-completely-removed region at least corresponds to a pixel region as well as regions having a first via hole401and a second via hole402, whereas the first-photoresist-completely-retained region50a1corresponds to the remaining regions.

S104, as illustrated inFIG. 4, removing the etch stop layer film in the first-photoresist-completely-removed region by way of an etching process to form the pattern of the etch stop layer40.

In this step, an wet-etching process is preferably used to remove the etch stop layer film in the first-photoresist-completely-removed region, which allows a diameter of the first via hole401to be larger than a gap between the first-photoresist-completely-retained regions corresponding to the first via hole401, and a diameter of the second via hole402to be larger than a gap between the first-photoresist-completely-retained regions corresponding to the second via hole402.

Thus, in the following step S105, while curing the photoresist in the first-photoresist-completely-retained regions50a1, it is easier to make the photoresist fill in the first via hole401and the second via hole402.

It is noted that, the wet-etching process is used in this step as it has a property of anisotropy which comprises vertical etching and also lateral drill etching, thereby allowing the diameters of the first via hole401and the second via hole402to be larger than the gaps of first-photoresist-completely-retained regions50a1corresponding to the respective via holes.

S105, as illustrated inFIG. 5, curing the photoresist in the first-photoresist-completely-retained regions50a1to make the photoresist deform and fill the first via hole401and the second via hole402with the deformed photoresist, such that the pattern of the photoresist layer50which is disposed outside the pixel region and overlays at least the first via hole401and the second via hole402is formed.

As an example, the photoresist in the first-photoresist-completely-retained regions50a1may be cured at a temperature of 150-180° C. for 130-200 seconds, which allows the photoresist of the first-photoresist-completely-retained regions50a1to be melted and then allows the photoresist around the first via hole401and the second via hole402to flow into the first via hole and the second via hole. That is, the photoresist of the first-photoresist-completely-retained regions50a1is deformed after the previous process, which allows the deformed photoresist to fill in the first via hole401and the second via hole402, so as to form the pattern of the photoresist layer50which is disposed outside the pixel region and overlays at least the first via hole401and the second via hole402.

It is noted that, the difference between the photoresist in the first-photoresist-completely-retained region50a1and the pattern of the photoresist layer50is whether the photoresist overlaying the first via hole401and the second via hole402is present in the region having the first via hole401and the second via hole402.

As the etch stop layer film in the first-photoresist-completely-removed region is removed by way of the wet-etching process, the border of the formed pattern of etch stop layer40is recessed inwards relative to the border the first-photoresist-completely-retained region50a1, the cured pattern of the photoresist layer50will overlay the pattern of the etch stop layer40which is recessed inwards relative to that.

Through the previous steps S101to S105, during the process of forming the pattern of the etch stop layer40, it is possible to use photoresist of the first-photoresist-completely-retained region50a1disposed above the pattern of the etch stop layer40to form the pattern of the photoresist50simply by way of a curing process, making the process relatively simple and requiring no extra patterning processes.

S106, as illustrated inFIG. 6, sequentially forming a transparent conductive layer70aand a second photoresist layer50bon the substrate having the pattern of the photoresist layer50formed thereon.

S107, as illustrated inFIG. 7, exposing and developing the substrate having the second photoresist layer50bformed thereon by using a regular mask to form a second-photoresist-completely-retained region50b1and a second-photoresist-completely-removed region (not shown inFIG. 7); wherein the second-photoresist-completely-retained region50b1corresponds to the pixel region, and the second-photoresist-completely-removed region corresponds to the remaining regions.

S108, as illustrated inFIG. 8, removing the transparent conductive layer film of the second-photoresist-completely-removed region by way of an etching process to form the pattern of the pixel electrode70and to expose the pattern of the photoresist layer50.

S109, as illustrated inFIG. 9, removing the pattern of the photoresist layer50and photoresist in the second-photoresist-completely-retained region50b1by way of a peeling process to expose the first via hole401and the second via hole402.

During the above steps S106to S109, the pattern of the photoresist layer50is not present under the pattern of the pixel electrode70. Thus, even if the transparent conductive layer film is formed above the pattern of the photoresist layer50, it is still possible to remove the pattern of the photoresist layer50and the photoresist of the second-photoresist-completely-retained region50b1disposed above the pattern of the pixel electrode70together, after the pattern of the pixel electrode70is formed.

S110, as illustrated10, forming the pattern of the source electrode801and the pattern of the drain electrode802on the substrate having the pattern of the pixel electrode70formed thereon.

As an example, the pattern of the source electrode801is connected to the pattern of the metal oxide semiconductor active layer30through the first via hole401, the pattern of the drain electrode802is connected to the pattern of the metal oxide semiconductor active layer30through the second via hole402, and the pattern of the drain electrode802is connected to the pattern of the pixel electrode70.

The pattern of the source electrode801and the pattern of the drain electrode802can be made of materials having low resistances and strong activity such as Cu.

It can be contemplated that, if the pixel electrode70is formed on the array substrate01only, a protection layer may be further formed to protect the pattern of the source electrode801and the pattern of the drain electrode802after the pattern of the source electrode801and the pattern of the drain electrode802are formed.

Based on the mentioned above, considering that the Advanced Super Dimension Switch technology can improve the display quality of the display panel and has advantages such as high resolution, high transmissivity, low power consumption, high aperture ratio, low chromatic aberration, no push mura and so on, as illustrated inFIG. 11, the method further comprises: forming the pattern of a passivation layer90and the pattern of a common electrode100.

As an example, the following steps may be used instead of the above steps S102to S105:

S202, as illustrated inFIG. 3, sequentially forming an etch stop layer40aand a first photoresist layer50aon the substrate having the pattern of the gate electrode10, the pattern of the gate insulation layer20and the pattern of the metal oxide semiconductor active layer30formed thereon.

S203, as illustrated inFIG. 12, exposing and developing the base substrate having the first photoresist layer50formed thereon by using a half-tone mask60or a grey-tone mask and forming a third-photoresist-completely-retained region50a2, a third-photoresist-partially-removed region50a3and a third-photoresist-completely-removed region50a4; wherein the third-photoresist-completely-removed region50a4at least corresponds to the pixel region, the third-photoresist-partially-removed region50a3corresponds to regions having the first via hole and the second via hole, and the third-photoresist-completely-retained region corresponds to the remaining regions.

The first via hole401and the second via hole402are used to respectively connect the pattern of the source electrode801and the pattern of the drain electrode802to the pattern of the metal oxide semiconductor active layer30.

With reference toFIG. 12, the half-tone mask60comprises a completely-opaque region601, a partially-transparent region602and a completely-transparent region603. That is: the half-tone mask60is a transparent substrate that has an opaque light-shielding metal layer in some regions, a partially transparent light-shielding metal layer in some other regions and no light-shielding metal layer in the remaining regions. Herein, a thickness of the partially transparent light-shielding metal layer is smaller than that of the opaque light-shielding metal layer. Furthermore, the UV-light transmissivity of the partially transparent light-shielding metal layer can be changed by adjusting the thickness of the partially transparent light-shielding metal layer.

Based on that, the operational principle of the half-tone mask60is described as follows: by controlling thicknesses of the light-shielding metal layers in different regions of the half-tone mask60, it is possible to have different light intensities in different regions under the exposure, thereby selectively exposing and developing the first photoresist layer50ato form the third-photoresist-completely-retained region50a2, the third-photoresist-partially-removed region50a3and the third-photoresist-completely-removed region50a4which respectively correspond to the completely-opaque region601, the partially-transparent region602and the completely-transparent region603of the half-tone mask60.

The principle of the grey-tone mask is similar to that of the half-tone mask60.

The photoresist in the embodiment of the invention are all positive photoresist, negative photoresist is similar thereto and will not be elaborated herein.

S204, as illustrated inFIG. 13, removing the etch stop layer film in the third-photoresist-completely-removed region50a4by way of an etching process.

S205, as illustrated inFIG. 14, removing a photoresist in the third-photoresist-partially-removed region50a3by way of an ashing process, etching the etch stop layer films in the first via hole401and the second via hole402to form the pattern of the etch stop layer40comprising the first via hole401and the second via hole402.

In this step, a wet-etching process is preferably used to remove the etch stop layer film in the region having the first via hole401and the second via hole402, allowing a diameter of the first via hole401to be larger than a gap between third-photoresist-completely-retained regions50a2corresponding to the first via hole401, and a diameter of the second via hole402to be larger than a gap between third-photoresist-completely-retained regions50a2corresponding to the second via hole402.

Thus, in the following step S206, while curing the photoresist of the third-photoresist-completely-retained regions50a2, it is easier to make the photoresist fill in the first via hole401and the second via hole402.

S206, as illustrated inFIG. 5, curing the photoresist of the third-photoresist-completely-retained regions50a2to deform the photoresist and fill the first via hole401and the second via hole402with the deformed photoresist of the third-photoresist-completely-retained region50a2, such that the pattern of the photoresist layer50is formed.

Based on the above, comparing with the steps S202to S206, the steps S102to S105are simpler in procedure. Thus, the regular mask is preferably used to form the etch stop layer40and the photoresist layer50in the embodiment of the invention.

According to the second method, an embodiment of the invention provides an example to describe a process for fabricating the array substrate in detail.

As illustrated inFIG. 15, the fabrication method comprises the following steps:

S301, as illustrated inFIG. 3, forming a pattern of a gate electrode10, a pattern of a gate insulation layer20and a pattern of a metal oxide semiconductor active layer30on a base substrate.

S302, as illustrated inFIG. 16, forming an etch stop layer40aon the substrate having the pattern of the gate electrode10, the pattern of the gate insulation layer20and the pattern of the metal oxide semiconductor active layer30formed thereon.

S303, as illustrated inFIG. 16, forming a pattern of a pixel electrode70on the substrate having the etch stop layer40aformed thereon.

S304, as illustrated inFIG. 16, forming a fourth photoresist layer50con the substrate having the pattern of the pixel electrode70formed thereon.

S305, as illustrated inFIG. 17, forming a fourth-photoresist-completely-retained region50c1and a fourth-photoresist-completely-removed region after exposing and developing the base substrate having the fourth photoresist layer50cformed thereon by using a regular mask; wherein the fourth-photoresist-completely-removed region corresponds to regions having a first via hole401and a second via hole402, and the fourth-photoresist-completely-retained region50c1corresponds to the remaining regions.

S306, as illustrated inFIG. 18, removing the etch stop layer film in the fourth-photoresist-completely-removed region by way of an etching process to form the pattern of the etch stop layer40comprising the first via hole401and the second via hole402, and peeling the photoresist in the fourth-photoresist-completely-retained region50c1.

S307, as illustrated inFIG. 19, forming the pattern of the source electrode801and the pattern of the drain electrode802on the substrate having the pattern of the pixel electrode70and the pattern of the etch stop layer40formed thereon.

As an example, the pattern of the source electrode801is connected to the pattern of the metal oxide semiconductor active layer30through the first via hole401, the pattern of the drain electrode802is connected to the pattern of the metal oxide semiconductor active layer30through the second via hole402, and the pattern of the drain electrode802is connected to the pattern of the pixel electrode70.

Based on the mentioned above, considering that the Advanced Super Dimension Switch technology can improve the display quality of the display panel and have advantages such as high resolution, high transmissivity, low power consumption, high aperture ratio, low chromatic aberration, no push mura, etc., as illustrated inFIG. 20, the method further comprises: forming the pattern of the passivation layer90and the pattern of the common electrode100.

An embodiment of the invention further provides an array substrate01, as illustrated inFIG. 10andFIG. 19. The array substrate01comprises: a base substrate, a pattern of a gate electrode10, a pattern of a gate insulation layer20, a pattern of a metal oxide semiconductor active layer30, a pattern of an etch stop layer40, a pattern of a pixel electrode70, and a pattern of a source electrode801and a pattern of a drain electrode802sequentially disposed on the base substrate.

As an example, the pattern of the etch stop layer40comprises a first via hole401and a second via hole402, the first via hole401and the second via hole402are configured for respectively connecting the pattern of the source electrode801and the pattern of the drain electrode802to the pattern of the metal oxide semiconductor active layer30; the pattern of the pixel electrode70is connected to the pattern of the source electrode801or the pattern of the drain electrode802, and the pattern of the source electrode801or the pattern of the drain electrode802connected to the pattern of the pixel electrode70partly overlays the pattern of the pixel electrode70.

It can be contemplated that, the array substrate may further comprise a gate line and a gate connection disposed in the same layer as the pattern of the gate electrode10, as well as a date lines and a data connection disposed in the same layer as the pattern of the source electrode801and the pattern of the drain electrode802and so on. Further, the pattern of the gate electrode10, the gate line, the gate connection, the pattern of the source electrode801and the pattern of the drain electrode802, the data line and the data connection and the like can all be made of a material with low resistance and strong activity such as Cu.

As Cu has rich reserves in nature and it is conductive material with relatively low resistance, the materials of the pattern of the gate electrode10, the pattern of the source electrode801and the pattern of the drain electrode802in the embodiment of the invention are preferably Cu.

On one hand, it is possible to fabricate an array substrate with a higher resolution, a better performance and a relatively big size by using the pattern of the metal oxide semiconductor active layer30and electrodes having low resistances. On the other hand, comparing with the conventional solutions of forming the pattern of the source electrode801and the pattern of the drain electrode802first and then forming the pattern of the pixel electrode70, by forming the pattern of the pixel electrode70first and then forming the pattern of the source electrode801and the pattern of the drain electrode802, it is possible to prevent the problem that the pattern of the pixel electrode70failing to connect to the pattern of the source electrode801and the pattern of the drain electrode802caused by the surface oxidation of the pattern of the source electrode801and the pattern of the drain electrode802due to the strong activity of the material having a low resistance.

As illustrated inFIG. 10, the pattern of the etch stop layer40is not present under the pattern of the pixel electrode70.

Thus, during the process of forming the pattern of the etch stop layer40, it is possible to use photoresist of the photoresist-completely-retained region disposed above the pattern of the etch stop layer40to form the pattern of the photoresist50simply by way of a curing process, thereby allowing the process to be relatively simple and requiring no extra patterning processes.

Further, considering that the Advanced Super Dimension Switch technology can improve the display quality of the display panel and have advantages such as high resolution, high transmissivity, low power consumption, high aperture ratio, low chromatic aberration, no push mura, etc., as illustrated inFIG. 11andFIG. 20, the array substrate01may further comprise the passivation layer90and the pattern of the common electrode100disposed above the pattern of the source electrode801and the pattern of the drain electrode802.

An embodiment of the invention further provides a display device comprising the array substrate01.

The display device provided in the embodiment of the invention is for example a LCD panel, a LCD TV, a LCD display, a digital photo-frame, a mobile phone, tablet PC or any products or components with a display function.

It is noted that, though the example of connecting the pattern of the drain electrode802to the pattern of the pixel electrode70in the thin film transistor is described in the above embodiments of the invention and drawings, those skilled in the art will understand that, due to the interchangeability of structure and form of the pattern of the source electrode801and the pattern of the drain electrode802in the thin film transistor, it is also possible to connect the pattern of the source electrode801to the pattern of the pixel electrode70and connect the pattern of the drain electrode802to the data line, which is an equivalent variation in the embodiment of the invention.

This application claims the priority of Chinese Patent Application No. 201410373777.2, filed on Jul. 31, 2014, and which application is incorporated herein by reference.