Memory system and operating method of the same

A memory system includes: a memory device that includes a plurality of memory dies each of which includes a plurality of planes, each of which includes a plurality of memory blocks that store data; and a controller including a first memory, and configured to: receive a plurality of commands from a host; perform command operations corresponding to the received commands in the memory blocks; detect patterns of the commands, the command operations, and user data corresponding to the command operations; dynamically allocate as pattern zones the first memory based on the patterns; and load map segments of map data corresponding to the commands, the command operations, and the user data into the pattern zones.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority of Korean Patent Application No. 10-2017-0090257, filed on Jul. 17, 2017, which is incorporated herein by reference in its entirety.

BACKGROUND

Exemplary embodiments of the present invention relate to a memory system, and more particularly, to a memory system capable of processing data with a memory device and a method for operating the memory system.

2. Description of the Related Art

The paradigm for computing environments is shifting toward ubiquitous computing which allows users to use computer systems anytime anywhere. For this reason, the demands for portable electronic devices, such as mobile phones, digital cameras and laptop computers are soaring. Those electronic devices generally include a memory system using a memory device as a data storage device. The data storage device may be used as a main memory unit or an auxiliary memory unit of a portable electronic device.

Since the data storage device using a memory device is not provided with a mechanical driving unit, it may have excellent stability and durability. Also, the data storage device has a quick data access rate with low power consumption. Non-limiting examples of the data storage device having such advantages include Universal Serial Bus (USB) memory devices, memory cards of diverse interfaces, Solid-State Drives (SSD) and the like.

SUMMARY

Embodiments of the present invention are directed to a memory system and a method for operating the memory system that are capable of processing data with a memory device rapidly and stably by minimizing complexity and performance deterioration of the memory system and maximizing the utility efficiency of the memory device.

In accordance with an embodiment of the present invention, a memory system includes: a memory device that includes a plurality of memory dies each of which includes a plurality of planes, each of which includes a plurality of memory blocks that store data; and a controller including a first memory, and configured to: receive a plurality of commands from a host; perform command operations corresponding to the received commands in the memory blocks; detect patterns of the commands, the command operations, and user data corresponding to the command operations; dynamically allocate as pattern zones the first memory based on the patterns; and load map segments of map data corresponding to the commands, the command operations, and the user data into the pattern zones.

The controller loads map segments of a first map data corresponding to a first pattern among the patterns into a first pattern zone among the pattern zones, and loads map segments of a second map data corresponding to a second pattern among the patterns into a second pattern zone among the pattern zones.

The first pattern is a pattern that informations on the commands, the command operations, and the user data are discontinuous, and the second pattern is a pattern that informations on the commands, the command operations, and the user data are continuous.

The controller reads each of the map segments of the first map data based on a first unit size from the memory blocks, and loads each of the read map segments of the first map data into the first pattern zone based on the first unit size.

The controller reads each map segment of the first unit size among the map segments of the first map data; stores the read map segment of the first unit size in buffers corresponding to at least one among the memory blocks, the planes, and the memory dies; and then loads the stored map segment of the first unit size into the first pattern zone.

The controller reads map segments of the second map data based on a second unit size from the memory blocks and loads the map segments into the second pattern zone based on the second unit size.

The controller reads all map segments of the second unit size among the map segments of the second map data; stores all the read map segments of the second unit size in buffers corresponding to at least one among the memory blocks, the planes, and the memory dies; and then loads all the stored map segments of the second unit size into the second pattern zone.

The controller reads all the map segments of the second unit size from the memory blocks through an interleaving method for the planes or the memory dies.

The map segments of the first map data that are loaded into the first pattern zone are managed by MRU (Most Recently Used) and LRU (Least Recently Used), and the map segments of the second map data that are loaded into the second pattern zone are managed according to performance of the command operations.

The controller detects whether background operations for the memory device or user data corresponding to the background operations are of the first pattern or the second pattern.

In accordance with another embodiment of the present invention, a method for operating a memory system includes: receiving a plurality of commands for a memory device that includes a plurality of memory dies, each of which includes a plurality of planes, each of which includes a plurality of memory blocks for storing data from a host; detecting patterns of the commands, the command operations corresponding to the commands, and user data corresponding to the command operations; dynamically allocating as pattern zones to a first memory based on the patterns; and loading map segments of map data corresponding to the commands, the command operations, and the user data into the pattern zones.

The loading of the map segments of the map data corresponding to the commands, the command operations, and the user data into the pattern zones includes: loading map segments of a first map data corresponding to a first pattern among the patterns into a first pattern zone among the pattern zones; and loading map segments of a second map data corresponding to a second pattern among the patterns into a second pattern zone among the pattern zones.

The first pattern is a pattern in which information on the commands, the command operations, and the user data are discontinuous, and the second pattern is a pattern in which information on the commands, the command operations, and the user data are continuous.

In loading of the map segments of the first map data corresponding to the first pattern among the patterns into the first pattern zone among the pattern zones, each of the map segments of the first map data is read based on a first unit size from the memory blocks, and each of the read map segments of the first map data is loaded into the first pattern zone based on the first unit size.

The loading of the map segments of the first map data corresponding to the first pattern among the patterns into the first pattern zone among the pattern zones includes: reading each map segment of the first unit size among the map segments of the first map data; storing the read map segment of the first unit size in buffers corresponding to at least one among the memory blocks, the planes, and the memory dies; and loading the map segment of the first unit size stored in the buffers into the first pattern zone.

In the loading of the map segments of the second map data corresponding to the second pattern among the patterns into the second pattern zone among the pattern zones, map segments of the second map data are read based on a second unit size from the memory blocks and the map segments are loaded into the second pattern zone based on the second unit size.

The loading of the map segments of the second map data corresponding to the second pattern among the patterns into the second pattern zone among the pattern zones includes: reading all map segments of the second unit size among the map segments of the second map data; storing all the read map segments of the second unit size in buffers corresponding to at least one among the memory blocks, the planes, and the memory dies; and loading all the map segments of the second unit size stored in the buffers into the second pattern zone.

In the reading of all the map segments of the second unit size among the map segments of the second map data, all the map segments of the second unit size are read from the memory blocks through an interleaving method for the planes or the memory dies.

The map segments of the first map data that are loaded into the first pattern zone are managed by MRU (Most Recently Used) and LRU (Least Recently Used), and the map segments of the second map data that are loaded into the second pattern zone are managed according to performance of the command operations.

The method may further include: detecting whether background operations for the memory device or user data corresponding to the background operations are of the first pattern or the second pattern.

In accordance with another embodiment of the present invention, a method for operating a controller includes: controlling a memory device to provide groups of map segments; loading the provided map segments by dynamically allocating buffer spaces of the controller for the respective groups based on continuous and discontinuous patterns of operands related to operations to be performed by the memory device, the patterns respectively corresponding to the groups; and controlling the memory device to perform one or more of the operations according to the loaded groups, wherein the respective groups are provided and loaded in different units of sizes.

DETAILED DESCRIPTION

FIG. 1is a block diagram illustrating a data processing system100including a memory system110in accordance with an embodiment of the present invention.

Referring toFIG. 1, the data processing system100may include a host102and the memory system110.

The host102may be any suitable electronic device including a portable electronic device such as a mobile phone, an MP3 player and a laptop computer or a non-portable electronic device such as a desktop computer, a game machine, a TV and a projector.

The host102may include at least one OS (operating system), and the OS may manage and control overall functions and operations of the host102, and provide an operation between the host102and a user using the data processing system100or the memory system110. The OS may support functions and operations corresponding to the use, purpose and usage of a user. For example, the OS may be divided into a general OS and a mobile OS, depending on the mobility of the host102. The general OS may be divided into a personal OS and an enterprise OS, depending on the environment of a user. For example, the personal OS configured to support a function of providing a service to general users may include Windows and Chrome, and the enterprise OS configured to secure and support high performance may include Windows server, Linux and Unix. Furthermore, the mobile OS configured to support a function of providing a mobile service to users and a power saving function of a system may include Android, iOS and Windows Mobile. At this time, the host102may include a plurality of OSs, and execute an OS to perform an operation corresponding to a user's request on the memory system110.

The memory system110may operate to store data for the host102in response to a request received from the host102. Non-limited examples of the memory system110may include a solid-state drive (SSD), a multi-media card (MMC), a secure digital (SD) card, a universal storage bus (USB) device, a universal flash storage (UFS) device, compact flash (CF) card, a smart media card (SMC), a personal computer memory card international association (PCMCIA) card and memory stick. The MMC may include an embedded MMC (eMMC), a reduced size MMC (RS-MMC) and a micro-MMC. The SD card may include a mini-SD card and micro-SD card.

The memory system110may employ various types of storage devices. Non-limited examples of storage devices included in the memory system110may include volatile memory devices such as a DRAM dynamic random access memory (DRAM) and a static RAM (SRAM) and nonvolatile memory devices such as a read only memory (ROM), a mask ROM (MROM), a programmable ROM (PROM), an erasable programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a ferroelectric RAM (FRAM), a phase-change RAM (PRAM), a magneto-resistive RAM (MRAM), resistive RAM (RRAM) and a flash memory. The flash memory may have a 3-dimensional (3D) stack structure.

The memory system110may include a memory device150and a controller130. The memory device150may store data for the host120, and the controller130may control storing data into the memory device150and reading data from the memory device150and transferring the read data to the host HOST.

The controller130and the memory device150may be integrated into a single semiconductor device, which may be included in the various types of memory systems as exemplified above.

Non-limited application examples of the memory system110may include a computer, an Ultra Mobile PC (UMPC), a workstation, a net-book, a Personal Digital Assistant (PDA), a portable computer, a web tablet, a tablet computer, a wireless phone, a mobile phone, a smart phone, an e-book, a Portable Multimedia Player (PMP), a portable game machine, a navigation system, a black box, a digital camera, a Digital Multimedia Broadcasting (DMB) player, a 3-dimensional television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage device constituting a data center, a device capable of transmitting/receiving information in a wireless environment, one of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network, a Radio Frequency Identification (RFID) device, or one of various components constituting a computing system.

Meanwhile, the memory device150of the memory system110may retain data stored therein even though a power source is cut off. Particularly, the memory device150may store the data transferred from the host102through a write operation, and transfer the data stored therein to the host102through a read operation. Herein, the memory device150may include a plurality of memory blocks152,154and156, and each of the memory blocks152,154and156may include a plurality of pages. Each of the pages may include a plurality of memory cells that are coupled to a plurality of word lines WL. Also, the memory device150may include a plurality of planes each of which includes the memory blocks152,154and156. Particularly, the memory device150may include a plurality of memory dies each of which includes a plurality of planes. Also, the memory device150may be a non-volatile memory device, e.g., a flash memory. Herein, the flash memory may be a three-dimensional (3D) stereoscopic stack structure.

Herein, the structure of the memory device150and the 3D stereoscopic stack structure of the memory device150will be described in detail below with reference toFIGS. 2 to 4, and the memory device150including a plurality of memory dies, each of which includes a plurality of planes, each of which includes a plurality of memory blocks152,154and156will be described later in detail below with reference toFIG. 6. Therefore, further description will not be provided herein.

The controller130of the memory system110may control the memory device150in response to a request from the host102. For example, the controller130may provide the host102with data that are read from the memory device150and store the data transferred from the host102in the memory device150. To this end, the controller130may control a read operation, a write operation, a program operation and an erase operation of the memory device150.

The controller130may include a host interface (I/F) unit132, a processor134, an error correction code (ECC) unit138, a Power Management Unit (PMU)140, a memory device controller such as a NAND flash controller (NFC)142and a memory144all operatively coupled via an internal bus.

The host interface unit132may be configured to process a command and data of the host102, and may communicate with the host102through one or more of various interface protocols such as universal serial bus (USB), multi-media card (MMC), peripheral component interconnect-express (PCI-E), small computer system interface (SCSI), serial-attached SCSI (SAS), serial advanced technology attachment (SATA), parallel advanced technology attachment (PATA), enhanced small disk interface (ESDI) and integrated drive electronics (IDE).

The ECC unit138may detect and correct an error contained in the data read from the memory device150. In other words, the ECC unit138may perform an error correction decoding process to the data read from the memory device150through an ECC code used during an ECC encoding process. According to a result of the error correction decoding process, the ECC unit138may output a signal, for example, an error correction success/fail signal. When the number of error bits is more than a threshold value of correctable error bits, the ECC unit138may not correct the error bits, and may output an error correction fail signal.

The ECC unit138may perform error correction through any suitable method included a coded modulation such as Low-Density Parity Check (LDPC) code, Bose-Chaudhuri-Hocquenghem (BCH) code, turbo code, Reed-Solomon code, convolution code, Recursive Systematic Code (RSC), Trellis-Coded Modulation (TCM) and Block coded modulation (BCM). However, the ECC unit138is not limited thereto. The ECC unit138may include all circuits, modules, systems or devices needed for error correction.

The PMU140may provide and manage power of the controller130. Any suitable PMU may be employed.

The NFC142is an example of a suitable memory/storage interface for interfacing the controller130and the memory device150such that the controller130controls the memory device150in response to a request from the host102, when the memory device is a NAND flash memory. When the memory device150is a flash memory or specifically a NAND flash memory, the NFC142may generate a control signal for the memory device150and process data to be provided to the memory device150under the control of the processor134. The NFC142may work as an interface (e.g., a NAND flash interface) for processing a command and data between the controller130and the memory device150. Specifically, the NFC142may support data transfer between the controller130and the memory device150. A suitable memory/storage interface may be selected depending upon the type of the memory device150.

The memory144may serve as a working memory of the memory system110and the controller130, and store data for driving the memory system110and the controller130. The controller130may control the memory device150to perform read, write, program and erase operations in response to a request from the host102. The controller130may provide data read from the memory device150to the host102, may store data provided from the host102into the memory device150. The memory144may store data required for the controller130and the memory device150to perform these operations.

The memory144may be embodied by a volatile memory. For example, the memory144may be embodied by static random-access memory (SRAM) or dynamic random-access memory (DRAM). The memory144may be disposed within or out of the controller130.FIG. 1exemplifies the memory144disposed within the controller130. In an embodiment, the memory144may be embodied by an external volatile memory having a memory interface transferring data between the memory144and the controller130.

The processor134may control the overall operations of the memory system110. The processor134may drive firmware to control the overall operations of the memory system110. The firmware may be referred to as flash translation layer (FTL).

Also, in the memory system in accordance with the embodiment of the present invention, for example, the controller130may perform a plurality of command operations corresponding to a plurality of commands received from the host102in the memory device150. For example, the controller130may perform a plurality of program operations corresponding to a plurality of write commands, a plurality of read operations corresponding to a plurality of read commands, and a plurality of erase operations corresponding to a plurality of erase commands in the memory device150. Also, as the command operations are performed, the controller130may update metadata, particularly, map data. For example, in the memory system in accordance with the embodiment of the present invention, when the controller130receives a plurality of commands from the host102, particularly, when the controller130receives a plurality of read commands or write commands from the host102, the controller130may detect a pattern of the read commands or the write commands, a pattern of the read operations or write operations corresponding to the read commands or write commands, or a pattern of data corresponding to the read operations or write operations, load metadata, particularly, map data, corresponding to the read operations or write operations in the memory144of the controller130based on the detected pattern. At this time, the controller130may allocate pattern zones in the memory144of the controller130based on the detected pattern, and load the map data into the corresponding pattern zones. Also, in the memory system in accordance with the embodiment of the present invention, when the controller130performs background operations onto the memory device150, the controller130may detect the pattern of the background operations or the pattern of data corresponding to the background operations, load metadata, particularly, map data, corresponding to the background operations, into the memory144of the controller130based on the detected pattern. At this time, the controller130may allocate pattern zones in the memory144of the controller130based on the detected pattern, and load the map data to the corresponding pattern zones. Herein, in the memory system in accordance with the embodiment of the present invention, since the management operations performed after the command operations corresponding to the commands received from the host102are performed and the map data corresponding to the command operations are loaded will be described later in detail with reference toFIGS. 5 to 9, further description on it is not provided herein.

Also, the processor134of the controller130may include a management unit (not shown) for performing a bad management of the memory device150, and the management unit may detect a bad block in a plurality of memory blocks152,154and156that are included in the memory device150, and perform the bad management of treating the detected bad block as a bad block. Herein, the bad management may mean that when the memory device150is a flash memory, e.g., a NAND flash memory, a program failure may occur during a data program operation due to the characteristics of NAND, and the memory block where the program failure has occurred may be treated as a bad block and then the data that has failed to be programmed may be written, i.e., programmed, in a new memory block with. Also, as described above, when the memory device150has a three-dimensional stereoscopic stack structure and a program failure occurs and the block where the program failure has occurred is treated as a bad block, the utility efficiency of the memory device150and the reliability of the memory system110are dropped drastically. Therefore, it is required to perform a more reliable bad block management. Hereafter, a memory device in the memory system in accordance with the embodiment of the present invention will be described in detail with reference toFIGS. 2 to 4.

FIG. 2is a schematic diagram illustrating the memory device150.

Referring toFIG. 2, the memory device150may include a plurality of memory blocks0to N-1, and each of the blocks0to N-1may include a plurality of pages, for example, 2Mpages, the number of which may vary according to circuit design. Memory cells included in the respective memory blocks0to N-1may be one or more of a single level cell (SLC) storing 1-bit data, a multi-level cell (MLC) storing 2-bit data, a triple level cell (TLC) storing 3-bit data, a quadruple level cell (QLC) storing 4-bit level cell, a multiple level cell storing 5-or-more-bit data, and so forth.

FIG. 3is a circuit diagram illustrating an exemplary configuration of a memory cell array of a memory block in the memory device150.

Referring toFIG. 3, a memory block330which may correspond to any of the plurality of memory blocks152to156included in the memory device150of the memory system110may include a plurality of cell strings340coupled to a plurality of corresponding bit lines BL0to BLm-1. The cell string340of each column may include one or more drain select transistors DST and one or more source select transistors SST. Between the drain and select transistors DST and SST, a plurality of memory cells MC0to MCn-1may be coupled in series. In an embodiment, each of the memory cell transistors MC0to MCn-1may be embodied by an MLC capable of storing data information of a plurality of bits. Each of the cell strings340may be electrically coupled to a corresponding bit line among the plurality of bit lines BL0to BLm-1. For example, as illustrated inFIG. 3, the first cell string is coupled to the first bit line BL0, and the last cell string is coupled to the last bit line BLm-1.

AlthoughFIG. 3illustrates NAND flash memory cells, the invention is not limited in this way. It is noted that the memory cells may be NOR flash memory cells, or hybrid flash memory cells including two or more types of memory cells combined therein. Also, it is noted that the memory device150may be a flash memory device including a conductive floating gate as a charge storage layer or a charge trap flash (CTF) memory device including an insulation layer as a charge storage layer.

The memory device150may further include a voltage supply unit310which provides word line voltages including a program voltage, a read voltage and a pass voltage to supply to the word lines according to an operation mode. The voltage generation operation of the voltage supply unit310may be controlled by a control circuit (not illustrated). Under the control of the control circuit, the voltage supply unit310may select one of the memory blocks (or sectors) of the memory cell array, select one of the word lines of the selected memory block, and provide the word line voltages to the selected word line and the unselected word lines as may be needed.

The memory device150may include a read/write circuit320which is controlled by the control circuit. During a verification/normal read operation, the read/write circuit320may operate as a sense amplifier for reading data from the memory cell array. During a program operation, the read/write circuit320may operate as a write driver for driving bit lines according to data to be stored in the memory cell array. During a program operation, the read/write circuit320may receive from a buffer (not illustrated) data to be stored into the memory cell array, and drive bit lines according to the received data. The read/write circuit320may include a plurality of page buffers322to326respectively corresponding to columns (or bit lines) or column pairs (or bit line pairs), and each of the page buffers322to326may include a plurality of latches (not illustrated).

FIG. 4is a schematic diagram illustrating an exemplary 3D structure of the memory device150.

The memory device150may be embodied by a 2D or 3D memory device. Specifically, as illustrated inFIG. 4, the memory device150may be embodied by a nonvolatile memory device having a 3D stack structure. When the memory device150has a 3D structure, the memory device150may include a plurality of memory blocks BLK0to BLKN-1each having a 3D structure (or vertical structure).

Hereafter, a data processing operation into a memory device in the memory system in accordance with the embodiment of the present invention with reference toFIGS. 5 to 9, particularly, a data processing operation performed when a plurality of commands are received from the host102and a plurality of command operations corresponding to the commands are performed, will be described in detail.

FIGS. 5 to 8illustrate an example of a data processing operation when a plurality of command operations corresponding to a plurality of commands are performed in a memory system in accordance with an embodiment of the present invention. Herein, for the sake of convenience in description, a case where a plurality of commands are received from the host102in the memory system110shown inFIG. 1and command operations corresponding to the commands are performed in the memory system in accordance with the embodiment of the present invention will be described in detail. For example, a case where a plurality of write commands are received from the host102and program operations corresponding to the write commands are performed, a case where a plurality of read commands are received from the host102and read operations corresponding to the read commands are performed, a case where a plurality of erase commands are received from the host102and erase operations corresponding to the erase commands are performed, or a case where a plurality of write commands and a plurality of read commands are received from the host102and program operations and read operations corresponding to the write commands and the read commands are performed is taken as an example and described in detail.

Also, in the memory system in accordance with the embodiment of the present invention, a case where write data corresponding to a plurality of write commands received from the host102are stored in a buffer/cache included in the memory144of the controller130and the data stored in the buffer/cache are programmed and stored in a plurality of memory blocks included in the memory device150, which are program operations, and map data are updated upon the performance of the program operations into the memory device150, and then the updated map data are stored in the memory blocks included in the memory device150, which is a case where program operations corresponding to a plurality of write commands received from the host102are performed, is taken as an example and described. Also, a case where when a plurality of read commands are received from the host102for the data stored in the memory device150, data corresponding to the read commands may be read from the memory device150by detecting map data of data corresponding to the read commands, and the read data are stored in the buffer/cache included in the memory144of the controller130, and the data stored in the buffer/cache are provided from the host102, that is, a case where read operations corresponding to the read commands received from the host102are performed is taken as an example and described in the embodiment of the present invention. Also, a case where when a plurality of erase commands are received from the host102for the memory blocks included in the memory device150, the memory blocks corresponding to the erase commands are detected and the data stored in the detected memory blocks are erased and the map data corresponding to the erased data are updated and the updated map data are stored in the memory blocks included in the memory device150is taken as an example and described in the embodiment of the present invention. In short, a case where erase operations corresponding to the erase commands received from the host102are performed is taken as an example and described in the embodiment of the present invention.

Herein, it is assumed in the embodiment of the present invention for the sake of convenience in description that the command operations performed in the memory system110are performed by the controller130. However, this is not more than an example and, as described above, the processor134included in the controller130, e.g., the FTL, may perform the command operations. Also, in this embodiment of the present invention, the controller130may program and store the user data corresponding to the write commands received from the host102and metadata in some memory blocks among the memory blocks included in the memory device150, read the user data corresponding to the read commands received from the host102and the metadata from the memory blocks storing the user data and the metadata among the memory blocks included in the memory device150and transfer the read user data and metadata to the host102, or erase the user data corresponding to the erase commands received from the host102and the metadata from the memory blocks storing the user data and the metadata among the memory blocks included in the memory device150.

Herein, the metadata may include a first map data including Logical to Physical (L2P) information (which is called logical information, hereafter) for the data stored in memory blocks through a program operation, and a second map data including Physical to Logical (P2L) information (which is called physical information, hereafter). Also, the metadata may include information on the command data corresponding to a command received from the host102, information on a command operation corresponding to the command, information on the memory blocks of the memory device150where the command operation is performed, and information on the map data corresponding to the command operation. In other words, the metadata may include all the other informations and data except the user data corresponding to a command received from the host102.

According to the embodiment of the present invention, the controller130may perform command operations corresponding to a plurality of commands received from the host102. For example, when the controller130receives write commands from the host102, the controller130may perform program operations corresponding to the write commands. Herein, the controller130may program and store user data corresponding to the write commands in the memory blocks of the memory device150, such as empty memory blocks where an erase operation is performed, open memory blocks, or free memory blocks. Also, the controller130may program and store mapping information between the logical addresses and the physical addresses for the user data stored in the memory blocks (which are first map data including an L2P map table or an L2P map list containing logical information) and mapping information between the physical addresses and the logical addresses for the memory blocks storing the user data (which are second map data including a P2L map table or a P2L map list containing physical information) in the empty memory blocks, open memory blocks, or free memory blocks among the memory blocks included in the memory device150.

When the controller130receives write commands from the host102, the controller130may program and store user data corresponding to the write commands in the memory blocks and store metadata that includes the first map data and the second map data for the user data stored in the memory blocks in memory blocks. Particularly, since data segments of the user data are stored in the memory blocks of the memory device150, the controller130may generate and update meta segments of the meta data, which are map segments of map data including L2P segments of the first map data and P2L segments of the second map data, and store them in the memory blocks of the memory device150. Herein, the map segments stored in the memory blocks of the memory device150may be loaded onto the memory144of the controller130to be updated.

Also, when the controller130receives a plurality of read commands from the host102, the controller130may read out the read data corresponding to the read commands from the memory device150, store the read data in the buffer/cache included in the memory144of the controller130, transfer the data stored in the buffer/cache to the host102. In this way, read operations corresponding to the read commands may be performed.

Also, when the controller130receives a plurality of erase commands from the host102, the controller130may detect memory blocks of the memory device150that correspond to the erase commands and perform erase operations onto the detected memory blocks. Hereafter, a data processing operation performed in the memory system in accordance with the embodiments of the present invention is described in detail with reference toFIGS. 5 to 8.

First of all, referring toFIG. 5, the controller130may perform command operations corresponding to a plurality of commands received from the host102. For example, the controller130may perform program operations corresponding to a plurality of write commands received from the host102. Herein, the controller130may program and store user data corresponding to the write commands in memory blocks552,554,562,564,572,574,582and584of the memory device150, and generate and update metadata for the user data when the program operation is performed onto the memory blocks552,554,562,564,572,574,582and584, and then store the generated and updated metadata in the memory blocks552,554,562,564,572,574,582and584of the memory device150.

Herein, the controller130may generate and update information representing that the user data are stored in the pages included in the memory blocks552,554,562,564,572,574,582and584of the memory device150, e.g., the first map data and the second map data, and store the generated and updated information in the pages included in the memory blocks552,554,562,564,572,574,582and584of the memory device150. In other words, the controller130may generate and update logical segments of the first map data, which include L2P segments, and physical segments of the second map data, which include P2L segments, and store the generated and updated logical segments in the pages included in the memory blocks552,554,562,564,572,574,582and584of the memory device150.

For example, the controller130may cache and buffer the user data corresponding to the write commands received from the host102in the first buffer510included in the memory144of the controller130, in other words, the controller130may store the data segments512of the user data in the first buffer510, which is a data buffer/cache, and store the data segments512stored in the first buffer510in the pages included in the memory blocks552,554,562,564,572,574,582and584of the memory device150. Since the data segments512of the user data corresponding to the write commands received from the host102are programmed and stored in the pages included in the memory blocks552,554,562,564,572,574,582and584of the memory device150, the controller130may generate and update the first map data and the second map data and store them in the second buffer520included in the memory144of the controller130. In short, the controller130may store the L2P segments522of the first map data and the P2L segments524of the second map data for the user data in the second buffer520, which is a map buffer/cache. Herein, as described above, the L2P segments522of the first map data and the P2L segments524of the second map data or a map list for the L2P segments522of the first map data and a map list for the P2L segments524of the second map data may be stored in the second buffer520in the memory144of the controller130. Also, the controller130may store the L2P segments522of the first map data and the P2L segments524of the second map data that are stored in the second buffer520in the pages stored in the memory blocks552,554,562,564,572,574,582and584of the memory device150.

Also, the controller130may perform command operations corresponding to a plurality of commands received from the host102. For example, the controller130may perform read operations corresponding to a plurality of read commands received from the host102. Herein, the controller130may load and check out the map segments of the map data for the user data corresponding to the read commands, e.g., the L2P segments522of the first map data and the P2L segments524of the second map data, onto the second buffer520, and then read the user data stored in the pages of the corresponding memory blocks among the memory blocks552,554,562,564,572,574,582and584of the memory device150, store the data segments512of the read user data in the first buffer510, and transfer them to the host102.

Also, the controller130may perform command operations corresponding to a plurality of commands received from the host102. In other words, the controller130may perform erase operations corresponding to a plurality of erase commands received from the host102. Herein, the controller130may detect memory blocks corresponding to the erase commands among the memory blocks552,554,562,564,572,574,582and584of the memory device150, and perform the erase operations onto the detected memory blocks.

When a background operation, for example, an operation of copying data or swapping data from the memory blocks included in the memory device150, such as a garbage collection operation or a wear-leveling operation, is performed, the controller130may store the data segments512of the corresponding user data in the first buffer510, store the map segments522and524of the map data corresponding to the user data in the second buffer520, and perform the garbage collection operation or the wear-leveling operation.

Also, referring toFIG. 6, the memory device150may include a plurality of memory dies, e.g., a memory die0610, a memory die1630, a memory die2650, and a memory die3670. Each of the memory dies610,630,650and670may include a plurality of planes. For example, the memory die0610may include a plane0612, a plane1616, a plane2620and a plane3624. The memory die1630may include a plane0632, a plane1636, a plane2640and a plane3644. The memory die2650may include a plane0652, a plane1656, a plane2660and a plane3664. The memory die3670may include a plane0672, a plane1676, a plane2680and a plane3684. Each of the planes612,616,620,624,632,636,640,644,652,656,660,664,672,676,680and684of the memory dies610,630,650and670included in the memory device150may include a plurality of memory blocks614,618,622,626,634,638,642,646,654,658,662,666,674,678,682and686. For example, as described earlier with reference toFIG. 2, each of the planes612,616,620,624,632,636,640,644,652,656,660,664,672,676,680and684may include N blocks Block0, Block1, . . . , Block N-1including a plurality of pages, e.g., 2Mpages. Also, the memory device150may include a plurality of buffers that respectively correspond to the memory dies610,630,650and670. For example, the memory device150may include a buffer0628corresponding to the memory die0610, a buffer1648corresponding to the memory die1630, a buffer2668corresponding to the memory die2650, and a buffer3688corresponding to the memory die3670.

When command operations corresponding to a plurality of commands received from the host102are performed, data corresponding to the command operations may be stored in the buffers628,648,668and688included in the memory device150. For example, when program operations are performed, data corresponding to the program operations may be stored in the buffers628,648,668and688, and then stored in the pages included in the memory blocks of the memory dies610,630,650and670. When read operations are performed, data corresponding to the read operations may be read from the pages included in the memory blocks of the memory dies610,630,650and670, stored in the buffers628,648,668and688, and transferred to the host102through the controller130.

Herein, in the embodiment of the present invention, for the sake of convenience in description, a case where the buffers628,648,668and688included in the memory device150exist in the outside of the corresponding memory dies610,630,650and670is taken as an example and described. However, the buffers628,648,668and688included in the memory device150may exist in the inside of the corresponding memory dies610,630,650and670. Also, the buffers628,648,668and688may correspond to the planes612,616,620,624,632,636,640,644,652,656,660,664,672,676,680and684or the memory blocks614,618,622,626,634,638,642,646,654,658,662,666,674,678,682and686in the memory dies610,630,650and670. In the embodiment of the present invention, for the sake of convenience in description, a case where the buffers628,648,668and688included in the memory device150are a plurality of page buffers322,324and326included in the memory device150is described as an example, as described earlier with reference toFIG. 3. However, the buffers628,648,668and688included in the memory device150may be a plurality of caches or a plurality of registers included in the memory device150.

Also, the memory blocks included in the memory device150may be grouped into a plurality of super memory blocks, and then command operations may be performed onto the super memory blocks. Herein, each of the super memory blocks may include a plurality of memory blocks, for example, memory blocks included in a first memory block group and a second memory block group. Herein, when the first memory block group is included in a first plane of a first memory die, the second memory block group may be included in the first plane of the first memory die or a second plane of the first memory die. Also, the second memory block group may be included in the planes of the second memory die. Hereafter, as described above, a case where a plurality of commands is received from the host102and command operations are performed, or when background operations are performed onto the memory device150, metadata, particularly, map data, are loaded onto the memory144of the controller130and managed in the memory system in accordance with the embodiment of the present invention is taken as an example and described in detail with reference toFIGS. 7 and 8.

Referring toFIG. 7, when the controller130receives a plurality of commands, for example, a plurality of read commands, the controller130may perform a plurality of read operations corresponding to the read commands received from the host102to the memory blocks included in the memory device150. In other words, as described above, the controller130may load map segments of map data for the user data corresponding to the read commands received from the host102in the second buffer520included in the memory144of the controller130, check out the map segments, read the user data from the memory blocks included in the memory device150, store the read user data in the first buffer510included in the memory144of the controller130, and transfer the user data to the host102.

Herein, for the sake of convenience in description, a case where a plurality of commands, particularly, a plurality of read commands, are received from the host102and then read operations corresponding to the read commands are performed in accordance with the embodiment of the present invention is taken as an example and described. However, the embodiment of the present invention may also be applied to a case of performing program operations or erase operations corresponding to a plurality of write commands or erase commands after a plurality of write commands or erase commands are received. Also, in accordance with the embodiment of the present invention, for the sake of convenience in description, a case where command operations corresponding to a plurality of commands received from the host102are performed is taken as an example and described. However, the embodiment of the present invention may also be applied to a case of performing background operations onto the memory device150.

In short, in the memory system in accordance with the embodiment of the present invention, when the controller130receives a plurality of commands from the host102, the controller130may detect the pattern of the commands received from the host102, the pattern of the command operations corresponding to the commands, or the pattern of data corresponding to the command operations. Herein, the patterns of the commands, the command operations, or the data may include a first pattern, which is a normal pattern, and a second pattern, which is a sequential pattern, and they may be decided based on a command pattern of the commands received from the host102, a performance pattern of the command operations performed in the memory device150according to the commands, or a data pattern of the data corresponding to the command operations, particularly, a data pattern of user data.

The normal pattern of the first pattern may represent discontinuous patterns of the information on the commands, the command operations or the user data. For example, the normal pattern of the first pattern may represent discontinuous patterns of command identification information, command operation, sequence information or memory block access information for accessing the memory blocks of the memory device150, and logical information of user data, e.g., Logical Block Address (LBA) or Logical Page Number (LPN).

Also, the sequential pattern of the second pattern may represent continuous patterns of the information on commands, command operations, or user data. For example, the sequential pattern of the second pattern may represent continuous patterns of command identification information, command operation sequence information or memory block access information for accessing the memory blocks of the memory device150, and logical information of user data, e.g., Logical Block Address (LBA) or Logical Page Number (LPN).

For example, the user data of the first pattern, which is the normal user data, may be user data, whose LBA or LPN number is one or equal to or less than a threshold number, having a data size of a threshold size or less. An example of the normal user data may be random user data. Also, the user data of the first pattern may be hot data, an access frequency to which is equal to or greater than a threshold value.

Also, the user data of the second pattern, which is the sequential user data, may be user data, which have a plurality of consecutive LBAs or LPNs and the number of LBAs or LPNs that is equal to or greater than a threshold number and have a data size that is equal to or greater than a threshold size. An example of the sequential user data may be consecutive user data. Also, the user data of the second pattern may be cold data, an access frequency to which is equal to or less than a threshold value.

Also, when the controller130receives a plurality of commands from the host102, the controller130may decide whether a plurality of commands received from the host102, e.g., a plurality of read commands, are normal read commands or sequential read commands; whether a plurality of command operations corresponding to the commands, e.g., read operations corresponding to the read commands, are normal read operations or sequential read operations; or whether the user data corresponding to the command operations, e.g., user data corresponding to the read operations, are normal read operations or sequential read operations. Also, when the controller130performs background operations onto the memory device150, the controller130may detect the pattern of the background operations. Herein, the controller130may decide whether the background operations performed onto the memory device150are normal background operations or sequential background operations, or decide whether the user data corresponding to the background operations are normal user data or sequential user data.

As described above, the controller130may allocate map buffer or map cache (i.e., the second buffer520in the memory144of the controller130), on which the map data for the user data are loaded, as a first pattern zone and a second pattern zone based on the detected first and second patterns of the commands received from the host102when a plurality of commands are received from the host102or of the background operations when the background operations are performed onto the memory device150. The controller130may dynamically allocate as the first pattern zone or the first and second pattern zones, the map buffer or map cache included in the memory144of the controller130based on the first pattern and the second pattern.

Also, the controller130may load map segments of the map data corresponding to the command operations or background operations into the second buffer520included in the memory144of the controller130to perform the command operations or background operations. Particularly, the controller130may load the map segments of the map data corresponding to the first pattern into the allocated first pattern zone of the memory144of the controller130, load the map segments of the map data corresponding to the second pattern to the allocated second pattern zone of the memory144of the controller130, and manage the map segments that are loaded into the first pattern zone or the second pattern zone in the memory144of the controller130. Hereafter, a case where the controller130receives a plurality of read commands from the host102is taken as an example and described in detail.

For example, when the controller130receives first group read commands from the host102, the controller130may detect a pattern of the first group read commands, a pattern of first group read command operations corresponding to the first group read commands, or a pattern of first group data corresponding to the first group read command operations, particularly, first group user data. Herein, the controller130may detect that the first group read commands, the first group read command operations, or the first group user data are of the first pattern. In other words, the controller130may detect that the first group read commands are normal read commands, or the first group read command operations corresponding to the first group read commands are normal read operations, or the first group user data corresponding to the first group read command operations are normal user data.

The controller130may allocate as the first pattern zone of the second buffer700included in the memory144of the controller130.

Also, the controller130may load map segments of first group map data for the first group user data into the memory144of the controller130to perform the first group read command operations, in other words, to read the first group user data from the memory device150. Herein, since the first group read commands, the first group read command operations, or the first group user data are of the first pattern, the controller130may load the map segments712,714,716,718,720,722,724and726of the first group map data corresponding to the first pattern into the first pattern zone700in the memory144of the controller130.

Herein, the map segments712,714,716,718,720,722,724and726of the first group map data corresponding to the first pattern may have a first unit size, e.g., a size of 2K, and the controller130may load each of the map segments712,714,716,718,720,722,724and726of the first group map data corresponding to the first pattern into the first pattern zone700by units of the first unit size.

In other words, when the map segments712,714,716,718,720,722,724and726of the first group map data do not exist in the first pattern zone700of the second buffer700, the controller130may read the map segments712,714,716,718,720,722,724and726of the first group map data from the memory blocks of the memory device150and load them into the first pattern zone700. Herein, as described above, the controller130may read the map segments712,714,716,718,720,722,724and726from the memory blocks of the memory device150and load them into the memory144of the controller130through a plurality of buffers628,648,668and688which respectively correspond to a plurality of memory dies, a plurality of planes, or a plurality of memory blocks in the memory device150. Herein, each of the map segments712,714,716,718,720,722,724and726may be read from the memory blocks of the memory device150by units of the first unit size, and then the read map segments may be loaded into the memory144of the controller130by units of the first unit size through the page buffers. Since the loading operation of the map segments712,714,716,718,720,722,724and726will be described later with reference toFIG. 8, further description on it will not be provided herein.

Also, the controller130may manage the map segments712,714,716,718,720,722,724and726loaded into the first pattern zone700based on Most Recently Used (MRU)/Least Recently Used (LRU) schemes.FIG. 7exemplarily shows MRU map segment702and LRU map segments704. Particularly, the controller130may maintain the map segments712,714,716,718,720,722,724and726in the second buffer700, which is the first pattern zone700, or discard them after performing a map flush operation onto the memory device150according to the MRU/LRU schemes. Herein, the controller130may manage a list (e.g., an MRU/LRU list) for the map segments712,714,716,718,720,722,724and726stored in the first pattern zone700.

Also, the controller130may read the first group user data from the memory blocks of the memory device150through the map segments712,714,716,718,720,722,724and726of the first group map data loaded into the first pattern zone700, and then store the first group user data that are read from the memory device150into the first buffer510included in the memory144of the controller130, and transfer the first group user data stored in the first buffer510to the host102in response to the first group read commands. Herein, when the controller130reads the first group user data from the memory blocks of the memory device150, as described above, the controller130may read the first group user data from the memory blocks of the memory device150and then store them in the memory144of the controller130through the buffers628,648,668and688which respectively correspond to the memory dies, the planes, or the memory blocks in the memory device150. Since the read operation of the first group user data is described before in detail with reference toFIGS. 5 and 6, further description on it will not be provided herein.

When the controller130receives second group read commands from the host102, the controller130may detect a pattern of the second group read commands, a pattern of second group read command operations corresponding to the second group read commands, or a pattern of second group data corresponding to the second group read command operations, particularly, second group user data. Herein, the controller130may detect that the second group read commands, the second group read command operations, or the second group user data are of the second pattern. In other words, the controller130may detect that the second group read commands are sequential read commands, or the second group read command operations corresponding to the second group read commands are sequential read operations, or the second group user data corresponding to the second group read command operations are sequential user data.

Also, when the second group read command is decided as the sequential user data, i.e., the second pattern, the controller130may allocate as the first pattern zone700_1and the second pattern zone700_2to the second buffer700. Particularly, since the second group read commands, the second group read command operations, or the second group user data are of the second pattern, the controller130may allocate the second buffer700as the first pattern zone700_1corresponding to the first group read commands and the second pattern zone700_2corresponding to the second group read commands, while allocating the second buffer700is allocated as the first pattern zone700corresponding to the first group read commands received from the host102. Herein, the controller130may allocate as the second pattern zone700_2to a portion of the memory zone of the first pattern zone700for storing LRU map segments of the first pattern zone700in the second buffer700included in the memory144of the controller130.

Also, the controller130may load the map segments762,764,766,768,770and772of the first group map data for the first group user data into the memory144of the controller130to perform the first group read command operations, in other words, to read the first group user data from the memory device150. Herein, since the first group read commands, the first group read command operations, or the first group user data are of the first pattern, the controller130may load the map segments762,764,766,768,770and772of the first group map data corresponding to the first pattern into the first pattern zone700_1in the second buffer700included in the memory144of the controller130.

Also, the controller130may load a map segment782of the second group map data for the second group user data into the memory144of the controller130to perform the second group read command operations, in other words, to read the second group user data from the memory device150. Herein, since the second group read commands, the second group read command operations, or the second group user data are of the second pattern, the controller130may load the map segment782of the second group map data corresponding to the second pattern into the second pattern zone700_2in the second buffer700included in the memory144of the controller130.

Herein, the map segments762,764,766,768,770and772of the first group map data corresponding to the first pattern may have the first unit size, e.g., a size of 2K, and the controller130may load each of the map segments762,764,766,768,770and772of the first group map data corresponding to the first pattern into the first pattern zone700_1by units of the first unit size.

Also, the map segment782of the second group map data corresponding to the second pattern may have a second unit size, e.g., a size of 32K, and the controller130may load the map segment782of the second group map data corresponding to the second pattern into the second pattern zone700_2by units of the second unit size. Herein, the second unit size may have a large-capacity size as much as an integer multiple of the first unit size. Particularly, the second buffer700second pattern zone700_2may be dynamically allocated as the second pattern zone700_2second buffer700based on the size of the map segment782of the second group map data loaded into the second pattern zone700_2.

In other words, when the map segments762,764,766,768,770and772of the first group map data do not exist in the first pattern zone700_1of the second buffer700, the controller130may read the map segments762,764,766,768,770and772of the first group map data from the memory blocks of the memory device150, and load them into the first pattern zone700_1. Herein, as described above, the controller130may read map segments762,764,766,768,770and772from the memory blocks of the memory device150and then load them into the memory144of the controller130through the buffers628,648,668and688which respectively correspond to the memory dies, the planes, or the memory blocks in the memory device150. Herein, each of the map segments762,764,766,768,770and772of the first group map data may be read from the memory blocks of the memory device150by units of the first unit size, and then the read map segments may be loaded into the memory144of the controller130by units of the first unit size through the page buffers. Since the loading operation of the map segments762,764,766,768,770and772will be described later with reference toFIG. 8, further description on it will not be provided herein.

Also, when the map segment782of the second group map data does not exist in the second pattern zone700_2of the second buffer700, the controller130may read the map segment782of the second group map data from the memory blocks of the memory device150and load them into the second pattern zone700_2. Herein, as described above, the controller130may read the map segment782from the memory blocks of the memory device150and load the map segment782into the memory144of the controller130through a plurality of buffers628,648,668and688which respectively correspond to a plurality of memory dies, a plurality of planes, or a plurality of memory blocks in the memory device150. Herein, the map segment782of the second group map data may be read from the memory blocks of the memory device150through an interleaving method for the planes or memory dies by units of the second unit size, and then the read map segments may be loaded into the memory144of the controller130by units of the second unit size from the page buffers. Since the loading operation of the map segment782will be described later with reference toFIG. 8, further description on it will not be provided herein.

Also, the controller130may manage the map segments762,764,766,768,770and772loaded into the first pattern zone700_1based on Most Recently Used (MRU)/Least Recently Used (LRU) schemes. Particularly, the controller130may maintain the map segments762,764,766,768,770and772in the first pattern zone700_1, or discard them after performing a map flush operation onto the memory device150according to the MRU/LRU schemes. Herein, the controller130may manage a list (e.g., an MRU LRU list) for the map segments762,764,766,768,770and772stored in the first pattern zone700_1.

Also, as command operations or background operations are performed according to the map segment782loaded into the second pattern zone700_2, the controller130may manage the map segment782loaded into the second pattern zone700_2. In other words, the controller130may perform the command operations or background operations according to the map segment782loaded into the second pattern zone700_2, and then the controller130may discard the map segment782loaded into the second pattern zone700_2by performing the map flush operation of flushing into the memory device150.

Herein, in accordance with the embodiment of the present invention, for the sake of convenience in description, a case where the single map segment782of the second unit size is loaded into the second pattern zone700_2is taken as an example and described. However, a plurality of map segments for the second group map data may be loaded into the second pattern zone700_2. Herein, the map segments for the second group map data that are loaded into the second pattern zone700_2may be managed based on the MRU/LRU schemes. Herein, when a plurality of the map segments for the second group map data are loaded into the second pattern zone700_2, the size of the second pattern zone700_2may increase in the memory144of the controller130when compared with the size of the first pattern zone700_1. In other words, when a plurality of the map segments for the second group map data are loaded into the second pattern zone700_2, the number or size of the map segments for the second group map data may increase more than that of the map segments for the first group map data. Particularly, when there are only the map segments for the second group map data in the memory144of the controller130, the operation performance for the first group read command operations may be deteriorated. In accordance with the embodiment of the present invention, as described above, one map segment782having the second unit size may be loaded into the second pattern zone700_2. Herein, the map segment782currently loaded into the second pattern zone700_2may be discarded from the second pattern zone700_2such that, another map segment for the second group map data is loaded into the second pattern zone700_2after the command operations and background operations is performed according to the currently loaded map segment782.

Also, the controller130may read the first group user data from the memory blocks of the memory device150through the map segments762,764,766,768,770and772of the first group map data loaded into the first pattern zone700_1, and then store the first group user data that are read from the memory device150into the first buffer510included in the memory144of the controller130, and transfer the first group user data stored in the first buffer510to the host102in response to the first group read commands. Herein, when the controller130reads the first group user data from the memory blocks of the memory device150, as described above, the controller130may read the first group user data from the memory blocks of the memory device150and then store them in the memory144of the controller130through the buffers628,648,668and688which respectively correspond to the memory dies, the planes, or the memory blocks in the memory device150. Since the read operation of the first group user data is described before in detail with reference toFIGS. 5 and 6, further description on it will not be provided herein.

Also, the controller130may read the second group user data from the memory blocks of the memory device150through the map segment782of the second group map data loaded into the second pattern zone700_2, and then store the second group user data that are read from the memory device150into the first buffer510included in the memory144of the controller130, and transfer the second group user data stored in the first buffer510to the host102in response to the second group read commands. Herein, when the controller130reads the second group user data from the memory blocks of the memory device150, as described above, the controller130may read the second group user data from the memory dies, the planes, or the memory blocks of the memory device150through an interleaving method for the planes or memory dies, and then store the second group user data in the memory144of the controller130through the buffers628,648,668and688which respectively correspond to the memory dies, the planes, or the memory blocks in the memory device150. Since the read operation of the second group user data is described before in detail with reference toFIGS. 5 and 6, further description on it will not be provided herein.

Subsequently, referring toFIG. 8, as described above, when the controller130reads the map segments762,764,766,768,770and772of the first group map data or the map segment782of the second group map data from the memory blocks of the memory device150, the controller130may read them from the memory blocks of the memory device150into the memory144of the controller130through the buffers, e.g., page buffers802,804,806and808, which respectively correspond to the memory dies, the planes, or the memory blocks in the memory device150. Herein, in the embodiment of the present invention, for the sake of convenience in description, a case where the page buffers802,804,806and808respectively correspond to a plurality of planes, that is, a case where a page buffer0802corresponds to a plane0in the memory device150, and a page buffer1804corresponds to a plane1in the memory device150, and a page buffer2806corresponds to a plane2in the memory device150, and a page buffer3808corresponds to a plane3in the memory device150is taken as an example and described in detail.

In short, the controller130may read map segments0850from the memory blocks included in the plane0of the memory device150and store the map segments0850in the page buffer0802, and load the map segments0850stored in the page buffer0802into the memory144of the controller130. Also, the controller130may read map segments1860from the memory blocks included in the plane1of the memory device150and store the map segments1860in the page buffer1804, and load the map segments1860stored in the page buffer1804into the memory144of the controller130. Also, the controller130may read map segments2870from the memory blocks included in the plane2of the memory device150and store the map segments2870in the page buffer2806, and load the map segments2870stored in the page buffer2806into the memory144of the controller130. Also, the controller130may read map segments3880from the memory blocks included in the plane3of the memory device150and store the map segments3880in the page buffer3808, and load the map segments3880stored in the page buffer3808into the memory144of the controller130. Hereafter, in the memory system in accordance with the embodiment of the present invention, an operation that the controller130loads the map segments762,764,766,768,770and772of the first group map data and the map segment782of the second group map data into the memory144of the controller130will be described in detail by taking an example.

For example, when the controller130loads a first map segment768into the memory144of the controller130among the map segments762,764,766,768,770and772of the first group map data, the controller130may read the first map segment768from the memory blocks of the memory device150, e.g., the memory blocks of the plane0, and store the read first map segment768in the page buffer0802as a first map segment852of the map segments0850. Herein, the first map segment768may be read from the memory blocks of the plane0by units of the first unit size, and thus the first map segment852of the map segments0850may be stored in the page buffer0802by units of the first unit size. The controller130then may load the first map segment852stored in the page buffer0802into the first pattern zone700_1by units of the first unit size. In short, the controller130may load the first map segment768of the first unit size into the first pattern zone700_1.

Also, when the controller130loads a second map segment766into the memory144of the controller130among the map segments762,764,766,768,770and772of the first group map data, the controller130may read the second map segment766from the memory blocks of the memory device150, e.g., the memory blocks of the plane0, and store the read second map segment766in the page buffer0802as a second map segment854of the map segments0850. Herein, the second map segment766may be read from the memory blocks of the plane0by units of the first unit size, and thus the second map segment854of the map segments0850may be stored in the page buffer0802by units of the first unit size. The controller130then may load the second map segment854stored in the page buffer0802into the first pattern zone700_1by units of the first unit size. In short, the controller130may load the second map segment766of the first unit size into the first pattern zone700_1.

Also, when the controller130loads a third map segment764into the memory144of the controller130among the map segments762,764,766,768,770and772of the first group map data, the controller130may read the third map segment764from the memory blocks of the memory device150, e.g., the memory blocks of the plane1, and store the read third map segment764in the page buffer1804as a first map segment862of the map segments1860. Herein, the third map segment764may be read from the memory blocks of the plane1by units of the first unit size, and thus the first map segment862of the map segments1860may be stored in the page buffer1804by units of the first unit size. The controller130then may load the first map segment862stored in the page buffer1804into the first pattern zone700_1by units of the first unit size. In short, the controller130may load the third map segment764of the first unit size into the first pattern zone700_1.

Also, when the controller130loads a fourth map segment762into the memory144of the controller130among the map segments762,764,766,768,770and772of the first group map data, the controller130may read the fourth map segment762from the memory blocks of the memory device150, e.g., the memory blocks of the plane2, and store the read fourth map segment762in the page buffer2806as a first map segment872of the map segments2870. Herein, the fourth map segment762may be read from the memory blocks of the plane2by units of the first unit size, and thus the first map segment872of the map segments2870may be stored in the page buffer2806by units of the first unit size. The controller130then may load the first map segment872stored in the page buffer2806into the first pattern zone700_1by units of the first unit size. In short, the controller130may load the fourth map segment762of the first unit size into the first pattern zone700_1.

Herein, as described above, the controller130may read each of the map segments762,764,766,768,770and772of the first group map data from the memory blocks of the memory device150by units of the first unit size and then store the map segments762,764,766,768,770and772in the corresponding page buffers802,804,806and808, respectively, and load the map segments stored in the page buffers802,804,806and808into the first pattern zone700_1by units of the first unit size. In short, the controller130may perform a single read operation to the memory blocks of the memory device150or a single loading operation into the first pattern zone700_1by units of the first unit size for each map segment among the map segments762,764,766,768,770and772of the first group map data. Also, as described above, the map segments762,764,766,768,770and772of the first group map data that are loaded into the first pattern zone700_1may be managed based on the MRU/LRU schemes.

Also, when the controller130loads the map segment782of the second group map data into the memory144of the controller130, the controller130may read the map segment782from the memory blocks of the memory device150. For example, the controller130may read the map segment782from the memory blocks of the plane0, the memory blocks of the plane1, the memory blocks of the plane2, and the memory blocks of the plane3through an interleaving method for memory dies or the planes of the memory device150. Herein, the map segment782of the second group map data may be read from the memory blocks of the memory device150by units of the second unit size. For example, the map segment782of the second group map data may be read from the memory blocks of the plane0, the memory blocks of the plane1, the memory blocks of the plane2, and the memory blocks of the plane3by units of the second unit size.

The map segment782of the second group map data which is read by units of the second unit size may be stored in the page buffer0802as map segments0850, in the page buffer1804as map segments1860, in the page buffer2806as map segments2870, and in the page buffer3808as map segments3880by units of a third unit size, e.g., a size of 8K, individually. In other words, the map segments0850of the map segment782of the second group map data may be read from the memory blocks of the plane0and stored in the page buffer0802by units of the third unit size. Also, the map segments1860of the map segment782of the second group map data may be read from the memory blocks of the plane1and stored in the page buffer1804by units of the third unit size. Also, the map segments2870of the map segment782of the second group map data may be read from the memory blocks of the plane2and stored in the page buffer2806by units of the third unit size. Also, the map segments3880of the map segment782of the second group map data may be read from the memory blocks of the plane3and stored in the page buffer3808by units of the third unit size. The controller130may load the map segments850,860,870and880that are stored in the page buffers802,804,806and808into the second pattern zone700_2by units of the second unit size. In short, the controller130may load the map segment782of the second group map data into the second pattern zone700_2by units of the second unit size.

Herein, as described above, the controller130may read map segment782of the second group map data from the memory blocks of the memory device150through an interleaving method for the memory dies or planes of the memory device150by units of the second unit size and then store the map segment782in the page buffers802,804,806and808respectively by units of the third unit size, and load the map segment782of the second group map data stored in the page buffers802,804,806and808into the second pattern zone700_2by units of the second unit size. In short, the controller130may perform a single read operation to the memory blocks of the memory device150or a single loading operation into the second pattern zone700_2by units of the second unit size for the map segments0850, the map segments1860, the map segments2870, and the map segments3880of the map segment782of the second group map data.

In the memory system in accordance with the embodiment of the present invention, which is described above, the memory144of the controller130may be efficiently used by dynamically allocating a map buffer or a map cache to the memory144of the controller130after detecting the commands received from the host102, command operations corresponding to the commands, or data corresponding to the command operations, or detecting background operations or data corresponding to the background operations. Also, the operation performance of the memory system may be improved by efficiently loading and managing the map segments of the map data with the memory144of the controller130. Hereafter, an operation of processing data in the memory system in accordance with the embodiment of the present invention will be described in detail with reference toFIG. 9.

FIG. 9is a flowchart describing a data processing operation in the memory system in accordance with the embodiment of the present invention.

Referring toFIG. 9, in step910, the memory system110may receive a plurality of commands from the host102. In step920, the memory system110may detect a pattern of the commands received from the host102, a pattern of a plurality of command operations corresponding to the commands, and a pattern of data corresponding to the command operations. Herein, the memory system110may detect whether the pattern of the commands, the command operations, or the data, particularly, user data, are the first pattern or the second pattern. Also, when background operations for the memory device150are performed, the memory system110may detect whether the pattern of the background operations or the data, particularly, the user data, corresponding to the background operations are the first pattern or the second pattern.

In step930, a map buffer or a map cache of the memory144of the controller130may be allocated in order to load the commands, the command operations, the background operations, or map segments of map data corresponding to the data into the memory144of the controller130. Particularly, the map buffer or the map cache may be allocated as pattern zones based on the detected pattern. For example, the memory144of the controller130may be dynamically allocated as the first pattern zone and the second pattern zone.

Subsequently, in step940, the map segments of the map data corresponding to each pattern may be read from the memory blocks of the memory device150, and then they are loaded into the memory144of the controller130through the buffers included in the memory device150, i.e., the first pattern zone and the second pattern zone.

In step950, the command operations may be performed based on the map segments loaded into the first pattern zone and the second pattern zone, and the map segments may be updated according to the performance of the command operations.

Herein, since the operation of allocating the map buffer or the map cache, for example, dynamically allocating the pattern zones, to the memory144of the controller130and loading the map segments of the map data to the pattern zones based on the pattern of the commands, the pattern of the command operations corresponding to the commands, the pattern of the data, particularly, the user data, corresponding to the command operations, the pattern of the background operations, and the pattern of the data, particularly, the user data, corresponding to the background operations, is described before in detail with reference toFIGS. 5 to 8, further description on it will not be provided herein. Hereafter, a data processing system and electronic devices to which the memory system110including the memory device150and the controller130which are described above with reference toFIGS. 1 to 9in accordance with the embodiment of the present invention will be described in detail below with reference toFIGS. 10 to 18.

FIG. 10is a diagram schematically illustrating another example of the data processing system including the memory system in accordance with the present embodiment.FIG. 10schematically illustrates a memory card system to which the memory system in accordance with the present embodiment is applied.

Referring toFIG. 10, the memory card system6100may include a memory controller6120, a memory device6130and a connector6110.

More specifically, the memory controller6120may be connected to the memory device6130embodied by a nonvolatile memory, and configured to access the memory device6130. For example, the memory controller6120may be configured to control read, write, erase and background operations of the memory device6130. The memory controller6120may be configured to provide an interface between the memory device6130and a host, and drive firmware for controlling the memory device6130. That is, the memory controller6120may correspond to the controller130of the memory system110described with reference toFIG. 1, and the memory device6130may correspond to the memory device150of the memory system110described with reference toFIG. 1.

Thus, the memory controller6120may include a RAM, a processing unit, a host interface, a memory interface and an error correction unit.

The memory controller6120may communicate with an external device, for example, the host102ofFIG. 1through the connector6110. For example, as described with reference toFIG. 1, the memory controller6120may be configured to communicate with an external device through one or more of various communication protocols such as universal serial bus (USB), multimedia card (MMC), embedded MMC (eMMC), peripheral component interconnection (PCI), PCI express (PCIe), Advanced Technology Attachment (ATA), Serial-ATA, Parallel-ATA, small computer system interface (SCSI), enhanced small disk interface (EDSI), Integrated Drive Electronics (IDE), Firewire, universal flash storage (UFS), WIFI and Bluetooth. Thus, the memory system and the data processing system in accordance with the present embodiment may be applied to wired/wireless electronic devices or particularly mobile electronic devices.

The memory device6130may be implemented by a nonvolatile memory. For example, the memory device6130may be implemented by various nonvolatile memory devices such as an erasable and programmable ROM (EPROM), an electrically erasable and programmable ROM (EEPROM), a NAND flash memory, a NOR flash memory, a phase-change RAM (PRAM), a resistive RAM (ReRAM), a ferroelectric RAM (FRAM) and a spin torque transfer magnetic RAM (STT-RAM).

The memory controller6120and the memory device6130may be integrated into a single semiconductor device. For example, the memory controller6120and the memory device6130may construct a solid-state driver (SSD) by being integrated into a single semiconductor device. Also, the memory controller6120and the memory device6130may construct a memory card such as a PC card (PCMCIA: Personal Computer Memory Card International Association), a compact flash (CF) card, a smart media card (e.g., SM and SMC), a memory stick, a multimedia card (e.g., MMC, RS-MMC, MMCmicro and eMMC), an SD card (e.g., SD, miniSD, microSD and SDHC) and a universal flash storage (UFS).

FIG. 11is a diagram schematically illustrating another example of the data processing system including the memory system in accordance with the present embodiment.

Referring toFIG. 11, the data processing system6200may include a memory device6230having one or more nonvolatile memories and a memory controller6220for controlling the memory device6230. The data processing system6200illustrated inFIG. 11may serve as a storage medium such as a memory card (CF, SD, micro-SD or the like) or USB device, as described with reference toFIG. 1. The memory device6230may correspond to the memory device150in the memory system110illustrated inFIG. 1, and the memory controller6220may correspond to the controller130in the memory system110illustrated inFIG. 1.

The memory controller6220may control a read, write or erase operation on the memory device6230in response to a request of the host6210, and the memory controller6220may include one or more CPUs6221, a buffer memory such as RAM6222, an ECC circuit6223, a host interface6224and a memory interface such as an NVM interface6225.

The CPU6221may control overall operations on the memory device6230, for example, read, write, file system management and bad page management operations. The RAM6222may be operated according to control of the CPU6221, and used as a work memory, buffer memory or cache memory. When the RAM6222is used as a work memory, data processed by the CPU6221may be temporarily stored in the RAM6222. When the RAM6222is used as a buffer memory, the RAM6222may be used for buffering data transmitted to the memory device6230from the host6210or transmitted to the host6210from the memory device6230. When the RAM6222is used as a cache memory, the RAM6222may assist the low-speed memory device6230to operate at high speed.

The ECC circuit6223may correspond to the ECC unit138of the controller130illustrated inFIG. 1. As described with reference toFIG. 1, the ECC circuit6223may generate an ECC (Error Correction Code) for correcting a fail bit or error bit of data provided from the memory device6230. The ECC circuit6223may perform error correction encoding on data provided to the memory device6230, thereby forming data with a parity bit. The parity bit may be stored in the memory device6230. The ECC circuit6223may perform error correction decoding on data outputted from the memory device6230. At this time, the ECC circuit6223may correct an error using the parity bit. For example, as described with reference toFIG. 1, the ECC circuit6223may correct an error using the LDPC code, BCH code, turbo code, Reed-Solomon code, convolution code, RSC or coded modulation such as TCM or BCM.

The memory controller6220may transmit/receive data to/from the host6210through the host interface6224, and transmit/receive data to/from the memory device6230through the NVM interface6225. The host interface6224may be connected to the host6210through a PATA bus, SATA bus, SCSI, USB, PCIe or NAND interface. The memory controller6220may have a wireless communication function with a mobile communication protocol such as WiFi or Long Term Evolution (LTE). The memory controller6220may be connected to an external device, for example, the host6210or another external device, and then transmit/receive data to/from the external device. In particular, as the memory controller6220is configured to communicate with the external device through one or more of various communication protocols, the memory system and the data processing system in accordance with the present embodiment may be applied to wired/wireless electronic devices or particularly a mobile electronic device.

FIG. 12is a diagram schematically illustrating another example of the data processing system including the memory system in accordance with the present embodiment.FIG. 12schematically illustrates an SSD to which the memory system in accordance with the present embodiment is applied.

Referring toFIG. 12, the SSD6300may include a controller6320and a memory device6340including a plurality of nonvolatile memories. The controller6320may correspond to the controller130in the memory system110ofFIG. 1, and the memory device6340may correspond to the memory device150in the memory system ofFIG. 1

More specifically, the controller6320may be connected to the memory device6340through a plurality of channels CH1to CHi. The controller6320may include one or more processors6321, a buffer memory6325, an ECC circuit6322, a host interface6324and a memory interface, for example, a nonvolatile memory interface6326.

The buffer memory6325may temporarily store data provided from the host6310or data provided from a plurality of flash memories NVM included in the memory device6340, or temporarily store meta data of the plurality of flash memories NVM, for example, map data including a mapping table. The buffer memory6325may be embodied by volatile memories such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM and GRAM or nonvolatile memories such as FRAM, ReRAM, STT-MRAM and PRAM. For convenience of description,FIG. 8illustrates that the buffer memory6325exists in the controller6320. However, the buffer memory6325may exist outside the controller6320.

The ECC circuit6322may calculate an ECC value of data to be programmed to the memory device6340during a program operation, perform an error correction operation on data read from the memory device6340based on the ECC value during a read operation, and perform an error correction operation on data recovered from the memory device6340during a failed data recovery operation.

The host interface6324may provide an interface function with an external device, for example, the host6310, and the nonvolatile memory interface6326may provide an interface function with the memory device6340connected through the plurality of channels.

Furthermore, a plurality of SSDs6300to which the memory system110ofFIG. 1is applied may be provided to embody a data processing system, for example, RAID (Redundant Array of Independent Disks) system. At this time, the RAID system may include the plurality of SSDs6300and a RAID controller for controlling the plurality of SSDs6300. When the RAID controller performs a program operation in response to a write command provided from the host6310, the RAID controller may select one or more memory systems or SSDs6300according to a plurality of RAID levels, that is, RAID level information of the write command provided from the host6310in the SSDs6300, and output data corresponding to the write command to the selected SSDs6300. Furthermore, when the RAID controller performs a read command in response to a read command provided from the host6310, the RAID controller may select one or more memory systems or SSDs6300according to a plurality of RAID levels, that is, RAID level information of the read command provided from the host6310in the SSDs6300, and provide data read from the selected SSDs6300to the host6310.

FIG. 13is a diagram schematically illustrating another example of the data processing system including the memory system in accordance with the present embodiment.FIG. 13schematically illustrates an embedded Multi-Media Card (eMMC) to which the memory system in accordance with the present embodiment is applied.

Referring toFIG. 13, the eMMC6400may include a controller6430and a memory device6440embodied by one or more NAND flash memories. The controller6430may correspond to the controller130in the memory system110ofFIG. 1, and the memory device6440may correspond to the memory device150in the memory system110ofFIG. 1.

More specifically, the controller6430may be connected to the memory device6440through a plurality of channels. The controller6430may include one or more cores6432, a host interface6431and a memory interface, for example, a NAND interface6433.

The core6432may control overall operations of the eMMC6400, the host interface6431may provide an interface function between the controller6430and the host6410, and the NAND interface6433may provide an interface function between the memory device6440and the controller6430. For example, the host interface6431may serve as a parallel interface, for example, MMC interface as described with reference toFIG. 1. Furthermore, the host interface6431may serve as a serial interface, for example, UHS ((Ultra High Speed)-I/UHS-II) interface.

FIGS. 14 to 17are diagrams schematically illustrating other examples of the data processing system including the memory system in accordance with the present embodiment.FIGS. 14 to 17schematically illustrate UFS (Universal Flash Storage) systems to which the memory system in accordance with the present embodiment is applied.

Referring toFIGS. 14 to 17, the UFS systems6500,6600,6700and6800may include hosts6510,6610,6710and6810, UFS devices6520,6620,6720and6820and UFS cards6530,6630,6730and6830, respectively. The hosts6510,6610,6710and6810may serve as application processors of wired/wireless electronic devices or particularly mobile electronic devices, the UFS devices6520,6620,6720and6820may serve as embedded UFS devices, and the UFS cards6530,6630,6730and6830may serve as external embedded UFS devices or removable UFS cards.

The hosts6510,6610,6710and6810, the UFS devices6520,6620,6720and6820and the UFS cards6530,6630,6730and6830in the respective UFS systems6500,6600,6700and6800may communicate with external devices, for example, wired/wireless electronic devices or particularly mobile electronic devices through UFS protocols, and the UFS devices6520,6620,6720and6820and the UFS cards6530,6630,6730and6830may be embodied by the memory system110illustrated inFIG. 1. For example, in the UFS systems6500,6600,6700and6800, the UFS devices6520,6620,6720and6820may be embodied in the form of the data processing system6200, the SSD6300or the eMMC6400described with reference toFIGS. 10 to 12, and the UFS cards6530,6630,6730and6830may be embodied in the form of the memory card system6100described with reference toFIG. 10.

Furthermore, in the UFS systems6500,6600,6700and6800, the hosts6510,6610,6710and6810, the UFS devices6520,6620,6720and6820and the UFS cards6530,6630,6730and6830may communicate with each other through an UFS interface, for example, MIPI M-PHY and MIPI UniPro (Unified Protocol) in MIPI (Mobile Industry Processor Interface). Furthermore, the UFS devices6520,6620,6720and6820and the UFS cards6530,6630,6730and6830may communicate with each other through various protocols other than the UFS protocol, for example, UFDs, MMC, SD, mini-SD, and micro-SD.

In the UFS system6500illustrated inFIG. 14, each of the host6510, the UFS device6520and the UFS card6530may include UniPro. The host6510may perform a switching operation in order to communicate with the UFS device6520and the UFS card6530. In particular, the host6510may communicate with the UFS device6520or the UFS card6530through link layer switching, for example, L3 switching at the UniPro. At this time, the UFS device6520and the UFS card6530may communicate with each other through link layer switching at the UniPro of the host6510. In the present embodiment, the configuration in which one UFS device6520and one UFS card6530are connected to the host6510has been exemplified for convenience of description. However, a plurality of UFS devices and UFS cards may be connected in parallel or in the form of a star to the host6410, and a plurality of UFS cards may be connected in parallel or in the form of a star to the UFS device6520or connected in series or in the form of a chain to the UFS device6520.

In the UFS system6600illustrated inFIG. 15, each of the host6610, the UFS device6620and the UFS card6630may include UniPro, and the host6610may communicate with the UFS device6620or the UFS card6630through a switching module6640performing a switching operation, for example, through the switching module6640which performs link layer switching at the UniPro, for example, L3 switching. The UFS device6620and the UFS card6630may communicate with each other through link layer switching of the switching module6640at UniPro. In the present embodiment, the configuration in which one UFS device6620and one UFS card6630are connected to the switching module6640has been exemplified for convenience of description. However, a plurality of UFS devices and UFS cards may be connected in parallel or in the form of a star to the switching module6640, and a plurality of UFS cards may be connected in series or in the form of a chain to the UFS device6620.

In the UFS system6700illustrated inFIG. 16, each of the host6710, the UFS device6720and the UFS card6730may include UniPro, and the host6710may communicate with the UFS device6720or the UFS card6730through a switching module6740performing a switching operation, for example, through the switching module6740which performs link layer switching at the UniPro, for example, L3 switching. At this time, the UFS device6720and the UFS card6730may communicate with each other through link layer switching of the switching module6740at the UniPro, and the switching module6740may be integrated as one module with the UFS device6720inside or outside the UFS device6720. In the present embodiment, the configuration in which one UFS device6720and one UFS card6730are connected to the switching module6740has been exemplified for convenience of description. However, a plurality of modules each including the switching module6740and the UFS device6720may be connected in parallel or in the form of a star to the host6710or connected in series or in the form of a chain to each other. Furthermore, a plurality of UFS cards may be connected in parallel or in the form of a star to the UFS device6720.

In the UFS system6800illustrated inFIG. 17, each of the host6810, the UFS device6820and the UFS card6830may include M-PHY and UniPro. The UFS device6820may perform a switching operation in order to communicate with the host6810and the UFS card6830. In particular, the UFS device6820may communicate with the host6810or the UFS card6830through a switching operation between the M-PHY and UniPro module for communication with the host6810and the M-PHY and UniPro module for communication with the UFS card6830, for example, through a target ID (Identifier) switching operation. At this time, the host6810and the UFS card6830may communicate with each other through target ID switching between the M-PHY and UniPro modules of the UFS device6820. In the present embodiment, the configuration in which one UFS device6820is connected to the host6810and one UFS card6830is connected to the UFS device6820has been exemplified for convenience of description. However, a plurality of UFS devices may be connected in parallel or in the form of a star to the host6810, or connected in series or in the form of a chain to the host6810, and a plurality of UFS cards may be connected in parallel or in the form of a star to the UFS device6820, or connected in series or in the form of a chain to the UFS device6820.

FIG. 18is a diagram schematically illustrating another example of the data processing system including the memory system in accordance with an embodiment.FIG. 18is a diagram schematically illustrating a user system to which the memory system in accordance with the present embodiment is applied.

Referring toFIG. 18, the user system6900may include an application processor6930, a memory module6920, a network module6940, a storage module6950and a user interface6910.

More specifically, the application processor6930may drive components included in the user system6900, for example, an OS, and include controllers, interfaces and a graphic engine which control the components included in the user system6900. The application processor6930may be provided as System-on-Chip (SoC).

The memory module6920may be used as a main memory, work memory, buffer memory or cache memory of the user system6900. The memory module6920may include a volatile RAM such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDARM, LPDDR3 SDRAM or LPDDR3 SDRAM or a nonvolatile RAM such as PRAM, ReRAM, MRAM or FRAM. For example, the application processor6930and the memory module6920may be packaged and mounted, based on POP (Package on Package).

The network module6940may communicate with external devices. For example, the network module6940may not only support wired communication, but also support various wireless communication protocols such as code division multiple access (CDMA), global system for mobile communication (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution (LTE), worldwide interoperability for microwave access (Wimax), wireless local area network (WLAN), ultra-wideband (UWB), Bluetooth, wireless display (WI-DI), thereby communicating with wired/wireless electronic devices or particularly mobile electronic devices. Therefore, the memory system and the data processing system, in accordance with an embodiment of the present invention, can be applied to wired/wireless electronic devices. The network module6940may be included in the application processor6930.

The storage module6950may store data, for example, data received from the application processor6930, and then may transmit the stored data to the application processor6930. The storage module6950may be embodied by a nonvolatile semiconductor memory device such as a phase-change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (ReRAM), a NAND flash, NOR flash and 3D NAND flash, and provided as a removable storage medium such as a memory card or external drive of the user system6900. The storage module6950may correspond to the memory system110described with reference toFIG. 1. Furthermore, the storage module6950may be embodied as an SSD, eMMC and UFS as described above with reference toFIGS. 12 to 17.

Furthermore, when the memory system110ofFIG. 1is applied to a mobile electronic device of the user system6900, the application processor6930may control overall operations of the mobile electronic device, and the network module6940may serve as a communication module for controlling wired/wireless communication with an external device. The user interface6910may display data processed by the processor6930on a display/touch module of the mobile electronic device, or support a function of receiving data from the touch panel.

According to the embodiments of the present invention, a memory system and a method for operating the memory system are capable of processing data with a memory device rapidly and stably by minimizing complexity and performance deterioration of the memory system and maximizing the utility efficiency of the memory device.