Transmitting device for high speed communication, interface circuit and system including the same

A transmission device may include a main driver configured to drive an output node based on an input signal, and may generate an output signal with multiple levels. The transmission device may include a variable emphasis driver configured to drive the output node with various driving forces based on transition information of the input signal.

BACKGROUND

1. Technical Field

Various embodiments generally relate to a communication system, and more particularly, to a transmitting device for high speed communication, an interface circuit and a system including the same.

2. Related Art

Electronic products for personal uses, such as a personal computer, a tablet PC, a laptop computer and a smart phone, are constructed by various electronic components. Two different electronic components in the electronic products may communicate at a high speed to process a large amount of data within a short amount of time. The electronic components generally communicate through interface circuits. The electronic components communicate in various schemes. As an example, one of the schemes may be a serial communication scheme.

As the performances of electronic components are improved, necessity for a communication scheme capable of increasing a bandwidth and reducing power consumption is being increased. In order to meet such necessity, various new serial communication schemes are suggested in the art, and improved interface circuits for supporting the new serial communication schemes are being developed.

SUMMARY

In an embodiment, a transmission device may be provided. The transmission device may include a main driver. The main driver may be configured to drive an output node based on an input signal, and may be configured to generate an output signal with multiple levels. The transmission device may include a variable emphasis driver configured to drive the output node with various driving forces based on transition information of the input signal.

In an embodiment, a transmission device may be provided. The transmission device may include a main driver configured to output an output signal with one level among a high level, a middle level and a low level, to an output node, based on an input signal. The transmission device may include a variable emphasis driver configured to drive the output node with one of first and second driving forces based on transition information of the input signal.

In an embodiment, a transmission device may be provided. The transmission device may include a variable emphasis driver configured to change a pre-emphasis strength according to a level by which an input signal transitions to control a transition time of an output signal.

DETAILED DESCRIPTION

Hereinafter, an interface circuit for high speed communication and a system including the same will be described below with reference to the accompanying drawings through various examples of embodiments.

Referring toFIG. 1, a system1in accordance with an embodiment may include a first device110and a second device120. The first device110may represent a component configured to transmit data, and the second device120may represent a component configured for receiving the data transmitted from the first device110. For example, the system1may include a master device and a slave device. When data are transmitted from the master device to the slave device, the master device may be the first device110, and the slave device may be the second device120. Conversely, when data is transmitted from the slave device to the master device, the master device may be the second device120, and the slave device may be the first device110.

The master device may be a host device such as a processor, and the processor may include, for example but not limited to, a central processing unit (CPU), a graphic processing unit (GPU), a multimedia processor (MMP) or a digital signal processor (DSP). The master device may be realized in the form of a system-on-chip (SoC) by combining processor chips having various functions, such as application processors. The slave device may be a memory, and the memory may include a volatile memory and/or a nonvolatile memory. The volatile memory may include, for example but not limited to, an SRAM (static RAM), a DRAM (dynamic RAM) and an SDRAM (synchronous DRAM), and the nonvolatile memory may include, for example but not limited to, a ROM (read only memory), a PROM (programmable ROM), an EEPROM (electrically erasable and programmable ROM), an EPROM (electrically programmable ROM), a flash memory, a PRAM (phase change RAM), an MRAM (magnetic RAM), an RRAM (resistive RAM) and an FRAM (ferroelectric RAM).

The first device110and the second device120may be electrically coupled through at least one signal transmission line group, and form a link. The first device110and the second device120may communicate in a balanced code multilevel signal transmission scheme through the at least one signal transmission line group. The at least one signal transmission line group may include a plurality of signal transmission lines. For example, in the example where the first device110and the second device120use an n level (phase or state) signal transmission scheme, the number of signal transmission lines forming one signal transmission line group may be equal to or larger than n. The first device110and the second device120may be electrically coupled through a plurality of signal transmission line groups. InFIG. 1, the first device110and the second device120may be electrically coupled through first and second signal transmission line groups131and132, and each of the first and second signal transmission line groups131and132may include at least n signal transmission lines.

The first device110and the second device120may respectively include interface circuits111and121. The interface circuits111and121may be physical layers for communication between the first device110and the second device120. The interface circuit111of the first device110may convert a plurality of data into n level symbols, and may transmit the n level symbols to the second device120through the signal transmission line groups131and132. The n level symbols may be configured by balanced codes. The interface circuit121of the second device120may receive the n level symbols transmitted through the signal transmission line groups131and132, and may recover the n level symbols into the plurality of data. For instance, in the example where the plurality of data are m bits, the interface circuit111of the first device110may convert the m bit data into a plurality of n level symbols, and may sequentially transmit in series the plurality of n level symbols through the signal transmission lines. The interface circuit121of the second device120may sequentially receive the plurality of n level symbols, and recover the m bit data based on the plurality of n level symbols. In the example where the first device110and the second device120include a plurality of signal transmission line groups, information corresponding to the number of signal transmission line groups*n level symbols may be simultaneously transmitted.

In an embodiment, one of the n level symbols may not be configured by a balanced code, and the plurality of n level symbols may be configured by balanced codes. That is to say, the plurality of n level symbols may become balanced codes in their entireties. Accordingly, even though each symbol is not configured by a balanced code, in the example where the plurality of n level symbols are transmitted through the signal transmission line groups131and132, balanced code multilevel signal transmission may be implemented.

FIG. 2is a diagram illustrating a representation of an example of the configuration of the interface circuit111of the first device110illustrated inFIG. 1. Referring toFIG. 2, the interface circuit111of the first device110may include a mapper210, a serialization unit220, and a transmission driver230. InFIG. 2, it is illustrated as an example that the interface circuit111is disposed for a three level serial communication scheme. Also, it is illustrated as an example that the interface circuit111is electrically coupled with the interface circuit121of the second device120through one signal transmission line group, and the one signal transmission line group may include three signal transmission lines251,252and253to transmit three level symbols. The mapper210may convert data into symbols. For example, the mapper210may convert 16 bit data DQ<0:15> into seven symbols. Each symbol may have three level information. The data DQ<0:15> may be information of a pattern suitable for being used in the first device110and the second device120. The mapper210may convert the data DQ<0:15> into symbols corresponding to the pattern of the data DQ<0:15> according to a table stored therein. For example, the mapper210may encode seven symbols, each symbol having three level information. Three levels may be defined as a high level, a middle level and a low level. For example, the high level may have a voltage level corresponding to ¾ V, the middle level may have a voltage level corresponding to 2/4 V, and the low level may have a voltage level corresponding to ¼ V. Since a system using the multilevel signal transmission scheme such as the system1ofFIG. 1does not use a clock signal, the first device110and the second device120may internally generate clock signals based on the signals transmitted through the signal transmission line groups131and132.

The serialization unit220may receive the seven symbols, each symbol having the three level information, and sequentially output the seven symbols, each symbol having the three level information. The transmission driver230may sequentially output the seven symbols, each symbol having the three level information, outputted from the serialization unit220, to the signal transmission lines251,252and253. The transmission driver230may include three transmitters TX, and the three transmitters TX may respectively output one of three level symbols outputted from the serialization unit220, to the signal transmission lines251,252and253. The serialization unit220and the transmission driver230may transmit in series seven symbols through the signal transmission lines251,252and253.

FIG. 3is a diagram illustrating a representation of an example of the configuration of the interface circuit121of the second device120illustrated inFIG. 1. Referring toFIG. 3, the interface circuit121of the second device120may include a reception driver310, a clock data recovery CDR circuit320, a parallelization unit330, and a demapper340. The reception driver310may be electrically coupled with the signal transmission lines251,252and253, and may receive the signals transmitted from the first device110. The reception driver310may include three receivers RX. The three receivers RX are respectively electrically coupled with the three signal transmission lines251,252and253configured for transmitting three level symbols. The clock data recovery circuit320may receive the three level symbols received by the reception driver310, and generate a clock signal CLK based on the three level symbols. The parallelization unit330may align the plurality of three level symbols received through the reception driver310, and output the aligned symbols in synchronization with the clock signal CLK. The reception driver310and the parallelization unit330may receive seven symbols, each symbol having three level information. The demapper340decodes the seven symbols. The demapper340may decode the seven symbols in a scheme corresponding to the encoding scheme of the mapper210. The demapper340may convert the seven symbols into 16 bit data DQ<0:15> according to a table stored therein. The 16 bit data DQ<0:15> outputted by the demapper340of the interface circuit121may be substantially the same data as the data inputted to the mapper210of the interface circuit111.

FIG. 4is a diagram illustrating a representation of an example of a system4including electronic components configured to use the balanced code multilevel signal transmission scheme described above with reference toFIGS. 1 to 3. Referring toFIG. 4, the system4may include a host device410, a large capacity storage device421, a memory422, and a display device423. The system4may include a camera device424, a modem425, and a bridge chip426. The system4may include a wireless chip427, a sensor428, and an audio device429. The host device410may communicate with the remaining components by forming respective individual links. The components for an electronic device illustrated inFIG. 4are nothing but a mere illustration, and it is to be noted that the system may include any components capable of performing data communication with the host device410.

The host device410may include at least one integrated circuit device such as an application processor and an application specific integrated circuit (ASIC). The large capacity storage device421may include at least one storage device such as a solid state drive (SSD) and a flash drive through USB coupling. The memory422may include any kind(s) of memory devices. For example, the memory422may include a volatile memory device such as a DRAM (dynamic RAM), or may include a nonvolatile memory device such as a ROM (read only memory), a PROM (programmable ROM), an EEPROM (electrically erasable and programmable ROM), an EPROM (electrically programmable ROM), a FLASH memory, a PRAM (phase change RAM), an MRAM (magnetic RAM), an RRAM (resistive RAM) and an FRAM (ferroelectric RAM).

The host device410may communicate with the large capacity storage device421and the memory422by forming respective links. The host device410, the large capacity storage device421and the memory422may include the interface circuits illustrated inFIGS. 1 to 3, and may exchange signals with one another with a serial communication scheme. Similarly, the host device410may communicate serially with the display device423, the camera device424, the modem425, the bridge chip426, the wireless chip427, the sensor428and the audio device429by forming individual links.

FIG. 5is a diagram illustrating a representation of an example of the configuration of a transmission device5in accordance with an embodiment. The transmission device5ofFIG. 5may be applied as the transmission driver230of the interface circuit111of the first device110illustrated inFIG. 2. Referring toFIG. 5, the transmission device5may include a main driver510, and a variable emphasis driver520. The main driver510may output an output signal OUT with multiple levels to an output node530based on an input signal IN. The multiple levels may be at least 3 levels. The multiple levels may include a plurality of levels respectively having a potential difference corresponding to a unit voltage.

In an embodiment, the multiple levels may be 3 levels, and may include a high level, a middle level and a low level. The high level may have a potential higher than the middle level, and the middle level may have a potential higher than the low level. The respective levels may have a potential difference corresponding to a unit voltage. The high level, the middle level and the low level may be levels between the power supply voltage of the main driver510and a ground voltage. For instance, in the example where the level of the power supply voltage is V, the high level may be a voltage level corresponding to ¾*V, the middle level may be a voltage level corresponding to 2/4*V, and the low level may be a voltage level corresponding to ¼*V. In the example where the input signal IN is a high level, the main driver510may generate the output signal OUT with the high level by driving the output node530to a voltage level corresponding to the high level. In the example where the input signal IN is a low level, the main driver510may generate the output signal OUT with the low level by driving the output node530to a voltage level corresponding to the low level. In the example where the input signal IN is a middle level, the main driver510may generate the output signal OUT with the middle level by driving the output node530to a voltage level corresponding to the middle level.

The variable emphasis driver520may drive the output node530with various driving forces based on the transition information of the input signal IN. The variable emphasis driver520may change a strength for driving the output node530, according to a change in a voltage level by which transition occurs when the input signal IN transitions. The variable emphasis driver520may drive the output node530strongly as the voltage level of the input signal IN changes largely. In other words, the variable emphasis driver520may increase a strength for driving the output node530, as a voltage level difference by which the input signal IN transitions is large. The variable emphasis driver520may drive the output node530with a predetermined strength, when the input signal IN transitions from any one level to an adjacent level. The variable emphasis driver520may drive the output node530until the voltage level of the output node530transitions from any one level to another level.

The adjacent level may mean a level that is higher or lower by a unit voltage than the any one level. The variable emphasis driver520may drive the output node530with a strength larger than the predetermined strength, when the input signal IN transitions from the any one level to a level exceeding the adjacent level. The level exceeding the adjacent level may mean a level that is higher or lower by a potential exceeding the unit voltage than the any one level.

For example, it is assumed that the multiple levels include 4 levels, the input signal IN currently inputted is the first level, and an input signal to be inputted next may transition to one of the second to fourth levels having potentials higher sequentially by a unit voltage than the first level. The second level may correspond to a potential higher by the unit voltage than the first level, the third level may correspond to a potential higher by the unit voltage than the second level, and the fourth level may correspond to a potential higher by the unit voltage than the third level. In the example where the input signal IN transitions from the first level to the second level, the variable emphasis driver520may drive the output node530with the smallest driving force. In the example where the input signal IN transitions from the first level to the fourth level, the variable emphasis driver520may drive the output node530with the largest driving force. In the example where the input signal IN transitions from the first level to the third level, the variable emphasis driver520may drive the output node530with a driving force larger than the smallest driving force and smaller than the largest driving force. Accordingly, the variable emphasis driver520efficiently enables the pre-emphasis of the output signal OUT according to a level change of the input signal IN.

The transmission device5may further include an output control unit540. The output control unit540may receive the input signal IN, and may generate main driver control signals MCON<0:n> and variable emphasis driver control signals PCON<0:m> based on the input signal IN. The output control unit540may control the driving force of the main driver510and the driving force of the variable emphasis driver520by generating the main driver control signals MCON<0:n> and the variable emphasis driver control signals PCON<0:m>.

FIG. 6is a diagram illustrating a representation of an example of the configuration of a transmission device6in accordance with an embodiment. Referring toFIG. 6, the transmission device6may include a plurality of main drivers and a plurality of variable emphasis drivers. WhileFIG. 6illustrates an example in which 3 main drivers and 3 variable emphasis drivers are provided, it is to be noted that the embodiment is not limited to such an example. The number of main drivers and variable emphasis drivers may be changed according to the number of the levels, phases or states of the data and/or symbols to be transmitted by the transmission device6. A first main driver601and a first variable emphasis driver602may be electrically coupled with a first signal transmission line611. The first signal transmission line611may be electrically coupled with a pad and an output node, and may transmit a first output signal DQ_A. The first main driver601and the first variable emphasis driver602may drive the first signal transmission line611and transmit the first output signal DQ_A through the first signal transmission line611. A second main driver603and a second variable emphasis driver604may be electrically coupled with a second signal transmission line631. The second signal transmission line631may be electrically coupled with a pad and an output node, and may transmit a second output signal DQ_B. The second main driver603and the second variable emphasis driver604may drive the second signal transmission line631and transmit the second output signal DQ_B through the second signal transmission line631. A third main driver605and a third variable emphasis driver606may be electrically coupled with a third signal transmission line651. The third signal transmission line651may be electrically coupled with a pad and an output node, and may transmit a third output signal DQ_C. The third main driver605and the third variable emphasis driver606may drive the third signal transmission line651and may transmit the third output signal DQ_C through the third signal transmission line651.

The first to third main drivers601,603and605may respectively generate the first to third output signals DQ_A, DQ_B and DQ_C with multiple levels based on input signals DQ<0:2>. For example, if the first input signal DQ<0> is a high level, the second input signal DQ<1> is a middle level and the third input signal DQ<2> is a low level, the first main driver601may drive the first signal transmission line611to the high level, the second main driver603may drive the second signal transmission line631to the middle level, and the third main driver605may drive the third signal transmission line651to the low level. The first to third main drivers601,603and605may operate by receiving a power supply voltage. For instance, in the example where the level of the power supply voltage is V, the high level may be a voltage level corresponding to ¾*V, the middle level may be a voltage level corresponding to 2/4*V, and the low level may be a voltage level corresponding to ¼*V.

The first to third variable emphasis drivers602,604and606enable the pre-emphasis of the output signals DQ_A, DQ_B and DQ_C. To this end, the first to third variable emphasis drivers602,604and606may respectively drive the first to third signal transmission lines611,631and651with various driving forces based on the transition information of the first to third input signals DQ<0:2>. The first to third variable emphasis drivers602,604and606may control the driving forces according to the level changes of the first to third input signals DQ<0:2>. The transmission device6may be an interface circuit capable of transmitting multilevel signals with a high level, a middle level and a low level, and the first to third input signals DQ<0:2> may each have one level of the high level, the middle level and the low level. The first variable emphasis driver602may additionally drive the first signal transmission line611when the first input signal DQ<0> transitions from any one level to another level. The first variable emphasis driver602may drive the first signal transmission line611with a first driving force when the first input signal DQ<0> transitions from the middle level to the high level, and may drive the first signal transmission line611with a second driving force when the first input signal DQ<0> transitions from the low level to the high level. The second driving force may be larger than the first driving force. For instance, the second driving force may be 2 times the first driving force. Similarly, the first variable emphasis driver602may drive the first signal transmission line611with the first driving force when the first input signal DQ<0> transitions from the middle level to the low level, and may drive the first signal transmission line611with the second driving force when the first input signal DQ<0> transitions from the high level to the low level. Namely, the first variable emphasis driver602may control a driving force for driving the first signal transmission line611based on a voltage level difference by which the first input signal DQ<0> transitions. The first variable emphasis driver602may drive the first signal transmission line611to a voltage level corresponding to the middle level when the first input signal DQ<0> retains the middle level or transitions from the high level or the low level to the middle level.

Similarly to the first variable emphasis driver602, the second and third variable emphasis drivers604and606may control driving forces for driving the second and third signal transmission lines631and651, respectively, based on voltage level differences by which the second and third input signals DQ<1> and DQ<2> transition, respectively. The second and third variable emphasis drivers604and606may drive the second and third signal transmission lines631and651to a voltage level corresponding to the middle level when the second and third input signals DQ<1> and DQ<2> retain the middle level or transition from the high level or the low level to the middle level.

Referring toFIG. 6, the first variable emphasis driver602may include first and second pre-emphasis drivers621and622. The first and second pre-emphasis drivers621and622may drive the first signal transmission line611to the power supply voltage or a ground voltage based on the transition information of the first input signal DQ<0>. The first and second pre-emphasis drivers621and622may operate by receiving the power supply voltage. The first and second pre-emphasis drivers621and622may respectively have a driving force corresponding to the first driving force. The driving strength and magnitude of the first and second pre-emphasis drivers621and622may be smaller than the driving strength and magnitude of the first main driver601. If the first input signal DQ<0> transitions from the middle level to the high level, any one of the first and second pre-emphasis drivers621and622may be turned on and drive the first signal transmission line611to the level of the power supply voltage. If the first input signal DQ<0> transitions from the low level to the high level, both the first and second pre-emphasis drivers621and622may be turned on and drive the first signal transmission line611to the level of the power supply voltage. If the first input signal DQ<0> transitions from the middle level to the low level, any one of the first and second pre-emphasis drivers621and622may be turned on and drive the first signal transmission line611to the level of the ground voltage. If the first input signal DQ<0> transitions from the high level to the low level, both the first and second pre-emphasis drivers621and622may be turned on and drive the first signal transmission line611to the level of the ground voltage. When the first input signal DQ<0> retains the middle level or transitions from the high level or the low level to the middle level, both the first and second pre-emphasis drivers621and622may be turned on. In this example, any one of the first and second pre-emphasis drivers621and622may drive the first signal transmission line611to the level of the power supply voltage, and the other may drive the first signal transmission line611to the level of the ground voltage.

The second variable emphasis driver604may include third and fourth pre-emphasis drivers641and642, and the third variable emphasis driver606may include fifth and sixth pre-emphasis drivers661and662. The third to sixth pre-emphasis drivers641,642,661and662may drive the second and third signal transmission lines631and651to the power supply voltage or the ground voltage based on the transition information of the second and third input signals DQ<1> and DQ<2>, respectively. The third to sixth pre-emphasis drivers641,642,661and662may operate similarly to the first and second pre-emphasis drivers621and622.

The transmission device6may further include an output control unit670. The output control unit670may control the driving forces of the first to third main drivers601,603and605and the first to third variable emphasis drivers602,604and606based on the first to third input signals DQ<0:2>. The output control unit670may generate first to third main driver control signals MCONA, MCONB and MCONC based on the first to third input signals DQ<0:2>. The first to third main drivers601,603and605may respectively drive the first to third signal transmission lines611,631and651to levels corresponding to the first to third input signals DQ<0:2> in response to the first to third main driver control signals MCONA, MCONB and MCONC. The output control unit670may generate first to sixth pre-emphasis driver control signals PCONA1, PCONA2, PCONB1, PCONB2, PCONC1and PCONC2based on the transition information of the first to third input signals DQ<0:2>. The first to sixth pre-emphasis driver control signals PCONA1, PCONA2, PCONB1, PCONB2, PCONC1and PCONC2may respectively have information on whether to turn on the first to sixth pre-emphasis drivers621,622,641,642,661and662and whether to perform pull-up or pull-down driving. The output control unit670may determine whether the first to sixth pre-emphasis drivers621,622,641,642,661and662pull-up or pull-down drive the first to third signal transmission lines611,631and651, based on voltage levels by which the first to third input signals DQ<0:2> transition. The output control unit670may generate the transition information according to the level changes of the input signals DQ<0:2>. The output control unit670may generate the transition information by comparing the levels of previously inputted input signals DQ<0:2> and the levels of currently inputted input signals DQ<0:2>, and generate the first to sixth pre-emphasis driver control signals PCONA1, PCONA2, PCONB1, PCONB2, PCONC1and PCONC2based on the transition information.

In the example where a variable emphasis driver includes at least 3 pre-emphasis drivers, transmission of multilevel signals having at least 4 levels is enabled. For example, when assuming that an output signal may have a low level, a middle-low level, a middle-high level and a high level, a variable emphasis driver may include 3 pre-emphasis drivers. If an input signal transitions from a middle-high level to a high level, 1 pre-emphasis driver may be turned on and drive a signal transmission line to a power supply voltage, and if the input signal transitions from a middle-low level to the high level, 2 pre-emphasis drivers may be turned on and drive the signal transmission line to the power supply voltage. Further, if the input signal transitions from a low level to the high level, all the 3 pre-emphasis drivers may be turned on and drive the signal transmission line to the power supply voltage. Accordingly, a pre-emphasis strength may be variously changed according to a level by which the input signal transitions, and the transition time of the output signal outputted through the signal transmission line may be variously controlled.

FIG. 7is a representation of an example of a timing diagram to assist in the explanation of the operation of the transmission device6illustrated inFIG. 6. Referring toFIG. 7, illustrated are a waveform A of the first output signal DQ_A in the example where the first input signal DQ<0> transitions from the middle level to the high level and a waveform B of the first output signal DQ_A in the example where the first input signal DQ<0> transitions from the low level to the high level. In the example of the waveform A, any one of the first and second pre-emphasis drivers621and622may be turned on, and the turned-on one pre-emphasis driver may drive the first signal transmission line611to the level of the power supply voltage. As the first signal transmission line611is driven to the high level by the first main driver601and is additionally driven by the turned-on one pre-emphasis driver, the first signal transmission line611may easily reach the high level. In the example of the waveform B, since the level change of the first input signal DQ<0> is larger than the case of the waveform A, both the first and second pre-emphasis drivers621and622may be turned on and drive the first signal transmission line611to the level of the power supply voltage. The variable emphasis driver602may drive the first signal transmission line611with a first driving force in the example used with the waveform A, and may drive the first signal transmission line611with a second driving force larger than the first driving force in the example used with the waveform B. Accordingly, even when the first input signal DQ<0> transitions by a large voltage level difference, the first signal transmission line611may easily reach the high level. In an embodiment, by controlling the driving force of the variable emphasis driver602, it may be possible to make a time at which the first signal transmission line611transitions to the high level in the example of the waveform A and a time at which the first signal transmission line611transitions to the high level in the case of the waveform B, the same or substantially the same.

Referring toFIG. 7, there are illustrated a waveform C of the first output signal DQ_A in the example where the first input signal DQ<0> transitions from the middle level to the low level and a waveform D of the first output signal DQ_A in the example where the first input signal DQ<0> transitions from the high level to the low level. In the example of the waveform C, any one of the first and second pre-emphasis drivers621and622may be turned on, and the turned-on one pre-emphasis driver may drive the first signal transmission line611to the level of the ground voltage. As the first signal transmission line611is driven to the low level by the first main driver601and is additionally driven by the turned-on one pre-emphasis driver, the first signal transmission line611may easily reach the low level. In the example of the waveform D, since the level change of the first input signal DQ<0> is larger than the example of the waveform C, both the first and second pre-emphasis drivers621and622may be turned on and may drive the first signal transmission line611to the level of the ground voltage. The variable emphasis driver602may drive the first signal transmission line611with the first driving force in the example used with the waveform C, and may drive the first signal transmission line611with the second driving force larger than the first driving force in the example used with the waveform D. Accordingly, even when the first input signal DQ<0> transitions by a large voltage level difference, the first signal transmission line611may easily reach the low level.

In the embodiments, since the pre-emphasis strength of an output signal to be transmitted through a signal transmission line is controlled in a variety of ways according to the transition information of an input signal, a signal may be precisely transmitted, and the data eye or window of the signal to be transmitted through the signal transmission line may be sufficiently secured.

While various embodiments have been described above, it will be understood to those skilled in the art that the embodiments described are examples only. Accordingly, the interface circuit for high speed communication and the system including the same described herein should not be limited based on the described embodiments.