Register slicing circuit and system on chip including the same

A register slicing circuit includes first and second register circuits, a forward channel and a backward channel. The first and second register circuits sequentially store requests received from a plurality of master devices to output the stored requests toward a slave device. The forward channel is used for sending a first request from the first register circuit to the second register circuit, and the backward channel is used for sending back a second request from the second register circuit to the first register circuit.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. non-provisional patent application claims priority under 35 USC §119 to Korean Patent Application No. 10-2012-0132818, filed on Nov. 22, 2012, in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated by reference in its entirety herein.

BACKGROUND

1. Technical Field

Example embodiments of the inventive concept relate generally to semiconductor integrated circuits and, more particularly, to a register slicing circuit and a system on chip (SOC) to expedite flows of urgent requests.

2. Discussion of the Related Art

An SOC indicates a chip, or a system on chip in which various semiconductor components are integrated together. The recent market trend is away from application specific integrated circuits (ASICs) and application specific standard products (ASSPs), toward SOC technologies. Further, there is an increasing demand for reducing the size and increasing the performance level of the SOC. While the integration degree of the SOC may be increased by integrating additional components into one chip, an operational speed of the SOC may not increase sufficiently.

SUMMARY

At least one example embodiment of the inventive concept provides a register slicing circuit capable of efficiently controlling request flows of an entire system by expediting flows of urgent requests.

At least one example embodiment of the inventive concept provides a SOC including a register slicing circuit capable of efficiently controlling request flows of the SOC by expediting flows of urgent requests.

According to an example embodiment of the inventive concept, a register slicing circuit includes first and second register circuits, a forward channel and a backward channel. The first and second register circuits sequentially store requests received from a plurality of master devices to output the stored requests toward a slave device. The forward channel is used for sending a first request from the first register circuit to the second register circuit, and the backward channel is used for sending back a second request from the second register circuit to the first register circuit.

A number of signal lines in the backward channel for sending back the second request may be less than a number of signal lines in the forward channel for sending the first request.

The second register circuit may divide the second request into a plurality of segments and send back the segments sequentially through the backward channel to the first register circuit.

The requests may each include a corresponding urgent flag, and each urgent flag may indicate whether or not an urgent service of the corresponding request is required such that a request having the urgent flag of a first value corresponds to an urgent request and a request having the urgent flag of a second value corresponds to a normal request.

The first register circuit and the second register circuit may perform an inter-node swapping operation based on the urgent flags for exchanging the first request and the second request.

The inter-node swapping operation may be performed when both: the second register circuit is in an issue-full state in which the second register circuit stores a maximum number of the requests; and the first request corresponds to an urgent request.

The first register circuit and the second register circuit may cancel the inter-node swapping operation when the second register circuit is relieved from the issue-full state before the inter-node swapping operation is completed.

Each of the first register circuit and the second register circuit may perform an in-node swapping operation based on the urgent flags for exchanging a storing order of two requests adjacently stored in each of the first register circuit and the second register circuit such that an urgent request stored later is exchanged with a normal request stored earlier.

The requests may further each include an order-dependency flag, and the order-dependency flags may indicate a limitation of a service order between two or more requests. Each of the first register circuit and the second register circuit may determine, based on the order-dependency flags, a group of the requests the service order of which is limited within the group. When the group includes an urgent request stored later and a normal request stored earlier, each of the first register circuit and the second register circuit may change the urgent flag of the normal request stored earlier from the second value to the first value.

Each of the first register circuit and the second register circuit may include a request buffer configured to store the requests, a backward buffer configured to temporarily store the second request to be sent back during the inter-node swapping operation, and a control unit configured to control the request buffer and the backward buffer.

The control unit of the second register circuit may provide a full count signal to the first register circuit, and the full count signal may indicate an issue-full state in which the second register circuit stores a maximum number of the requests. The control unit of the first register circuit may whether to perform the inter-node swapping operation based on the full count signal from the second register circuit and the urgent flag in the first request.

According to an example embodiment of the inventive concept, a system on chip (SOC) includes a slave device, a plurality of master devices configured to generate requests to demand services from the slave device, respectively, and an interconnect device coupling the slave device and the master devices. The interconnect device includes first and second register circuits configured to sequentially store the requests received from the master devices to output the stored requests toward the slave device, a forward channel configured to send a first request from the first register circuit to the second register circuit, and a backward channel configured to send back a second request from the second register circuit to the first register circuit.

The requests may each include a corresponding urgent flag, and each urgent flag may indicate whether or not an urgent service of the corresponding request is required such that a request having the urgent flag of a first value corresponds to an urgent request and a request having the urgent flag of a second value corresponds to a normal request.

The first register circuit and the second register circuit may perform an inter-node swapping operation and an in-node swapping operation based on the urgent flags, and the inter-node swapping operation may be for exchanging the first request and the second request. Also the first register circuit and the second register circuit may perform the in-node swapping operation for exchanging a storing order of two requests adjacently stored in each of the first register circuit and the second register circuit such that an urgent request stored later is exchanged with a normal request stored earlier.

Urgent information indicating requirements of the urgent services of the respective requests may be provided in real time from the master devices to the first register circuit and the second register circuit, and the values of the urgent flags in the request stored in the first register circuit and the second register circuit may be upgraded in real time based on the urgent information.

According to yet another example embodiment of the inventive concept, a device, includes: a first register circuit having a first request buffer comprising a first plurality of storage units connected together in a shift register configuration, the first plurality of storage units being configured to store therein a plurality of requests, including requests having at least two different levels of urgency than each other; and a second register circuit connected to the first register circuit by a forward channel which is configured to send the requests from the first register circuit to the second register circuit, and a backward channel which is configured to send the requests from the second register circuit back to the second register circuit. The second register circuit includes: a second request buffer comprising a second plurality of storage units connected together in the shift register configuration, the second plurality of storage units being configured to receive the requests from the first register circuit via the forward channel and to store the requests therein, including the requests having the at least two different levels of urgency; a backward buffer configured to receive and temporarily store at least one of the requests from the second plurality of storage units to be sent back to the first resister circuit via the backward channel; and a control unit configured to control operations of the second register circuit.

The control unit may be configured to control the second register circuit to divide each of at least one of the requests stored in the backward buffer into a plurality of segments and to send back the segments sequentially through the backward channel to the first register circuit.

The requests may each include a corresponding urgent flag, each urgent flag indicating an urgency of the corresponding request, wherein the urgent flag having a first value indicates an urgent request and the urgent flag having a second value indicates a normal request, and the device may be configured to perform an inter-node swapping operation based on the urgent flags for exchanging an urgent request stored in the first plurality of storage units of the first register circuit with a normal request stored in the second plurality of storage units of the second register circuit by sending the normal request from the backward buffer of the second register circuit to the first register circuit via the backward channel.

The inter-node swapping operation may be performed when both: the second register circuit is in an issue-full state in which the second register circuit stores a maximum number of the requests; and the urgent request is stored in the first plurality of storage units.

DETAILED DESCRIPTION OF THE EMBODIMENTS

FIG. 1is a diagram illustrating a register slicing circuit according to example embodiments of the inventive concept.

Referring toFIG. 1, a register slicing circuit500includes a first register circuit100, a second register circuit200, a forward channel10and a backward channel20.

First and second register circuits100and200sequentially store requests received from a plurality of master devices, or master intellectual property cores or blocks (IPs), to output the stored requests toward a slave device or a slave IP. Forward channel10is a channel for sending a first request FRQ from first register circuit100to second register circuit200. Backward channel20is a channel for sending back a second request BRQ from second register circuit200to first register circuit100.

To support high-performance applications in mobile devices for wireless internet, broadcasting, multimedia, etc., an operational frequency of an on-chip bus or an interconnect device in a system on chip (SOC) is ever-increasing. As various devices or IPs are included in the SOC, design margin may be decreased and a distance between network nodes or slicing nodes for timing closure may be increased. Because the signal transfer time is increased as the distance between the network nodes is increased, the long distance between the network nodes limits the increase of the operational frequency. To solve such problems, the advanced extensible interface (AXI) protocol or the open core protocol (OCP) specifies that at least one register slice or register point may be inserted between the long-distance network nodes.

Register slicing circuit500ofFIG. 1may be used for the register slicing according to the AXI protocol or the OCP, and register slicing circuit500may be inserted in an arbitrary path in an interconnect device800as illustrated inFIG. 11. In particular, register slicing circuit500may be inserted in a time-critical portion of a channel between the master devices and the slave device.

The conventional register slicing circuit includes only the forward channel for transferring the requests from the master devices toward the slave device. In this case, the flow of an urgent request may be retarded when the latter register circuit is in an issue-full state in which the latter register circuit stores a maximum number of the requests, because the urgent request cannot be transferred from the former register circuit to the latter register circuit in the issue-full state. As an example to solve this problem, the flow of the normal requests blocking the urgent request in a link may be expedited. In this case, however, starvation of another link may be caused due to the excessive flow of the link including the urgent request. As another solution, a plurality of request buffers may be included in one network node to store the respective requests divided by priority, and transfer first the requests of higher priority. In this case, however, gate-count overhead is increased due to the large number of request buffers.

Register slicing circuit500according to example embodiments further includes the backward channel20for performing an inter-node swapping operation so that an urgent request in first register circuit100may be transferred to second register circuit200even though the second register200is in the issue-full state.

In an example embodiment, a number N of signal lines in backward channel20for sending back the second request BRQ is less than a number M of signal lines in forward channel10for sending the first request FRQ. The time for the inter-node swapping operation may be increased as the number N of the signal lines in backward channel20is decreased, and thus the number N may be determined properly considering the time for the inter-node swapping operation and the design margin of the system adopting register slicing circuit500.

As such, the register slicing circuit500according to example embodiments may expedite the flow of the urgent request by performing the inter-node swapping operation using backward channel20implemented with the proper number N of the signal lines.

Even thoughFIG. 1illustrates two register circuits100and200for convenience of illustration, register slicing circuit500may include three or more register circuits that are cascade-coupled. For example, first register circuit100may perform the inter-node swapping operation with a register circuit (not shown) before first register circuit100using a forward channel11and a backward channel21, and/or second register circuit200may perform the inter-node swapping operation with a register circuit (not shown) after second register circuit200using a forward channel12and a backward channel22.

FIG. 2is a block diagram illustrating a register slicing circuit according to an example embodiment of the inventive concept.

Referring toFIG. 2, a register slicing circuit500amay include first register circuit100, second register circuit200, forward channel10and backward channel20, and first and second register circuits100and200may include request buffers120and220, backward buffers (BBs)140and240and control units (CTRLs)160and260, respectively.

Request buffers120and220store the requests transferred from the preceding node and backward buffers140and240temporarily store the request to be sent back to the preceding node during the inter-node swapping operation. Control units160and260control request buffers120and220and backward buffers140and240, respectively.

As described above, first register circuit100may perform the inter-node swapping operation with a register circuit (not shown) before first register circuit100. If first register circuit100does not perform the inter-node swapping operation with the preceding register circuit, back ward buffer140and backward channel21illustrated inFIG. 2may be omitted. Similarly second register circuit200may perform the inter-node swapping operation with a register circuit (not shown) after second register circuit200. If second register circuit200does not perform the inter-node swapping operation with the next register circuit, backward channel22illustrated inFIG. 2may be omitted.

Hereinafter, the inter-node swapping operation is described between first register circuit100and second register circuit200. The inter-node operation between first register circuit100and the preceding node, or between second register circuit200and the next node, may be similar to the inter-node swapping operation between first register circuit100and second register circuit200.

First request buffer120in first register circuit100may include a plurality of storage units101through106, and second request buffer220in second register circuit200may include a plurality of storage units201through206.FIG. 2illustrates for convenience of description that each of first and second request buffers120and220includes the six storage units, but the number of the storage units in each request buffer may be changed to a different number. The first request buffer120and second request buffer220may include the same number, or different numbers, of the storage units.

Request buffers120and140may perform fundamentally a shifting operation similar to a shift register and an input-output operation according to a first-in first out (FIFO) scheme when the expedition of an urgent request is not required.

First request buffer120may store the requests from the preceding node sequentially in first storage unit101through sixth storage unit106. Control unit160may activate a full count signal FC1when a request is stored in the last storage unit, that is, sixth storage unit106(e.g., when all of storage units101-106are occupied with requests). The full count signal FC1may be provided to the preceding node to provide the occupancy state of first request buffer120. First request buffer120may transfer the request stored in first storage unit101as the first request FRQ to second register circuit200through forward channel10. Whenever one request is transferred to second register circuit200, the requests in first request buffer120may be shifted sequentially unit by unit. In other words, the request in second storage unit102may move to first storage unit101, the request in third storage unit103may move to second storage unit102, and so on. Through such shifting operation, the FIFO input-output operation may be performed such that the request stored earlier may be output earlier.

The shifting operation and the FIFO input-output operation may be limited during an in-node swapping operation and an inter-node swapping operation. As described in greater detail below with reference toFIGS. 5A through 5B, the shifting operation of first request buffer120may be limited in case of the inter-node swapping operation because the second request BRQ sent back from second register circuit200is stored in first storage unit101. As described in greater detail below with reference toFIG. 7, the FIFO input-output operation may be limited in case of the in-node swapping operation because the storing order of the requests may be swapped such that an urgent request stored later may be output earlier than a normal request stored earlier.

Second request buffer220may store the requests from first register circuit100sequentially in first storage unit201through sixth storage unit206. Control unit260may activate a full count signal FC2when the request is stored in the last storage unit, that is, sixth storage unit206(e.g., when all of storage units201-206are occupied with requests). The full count signal FC2may be provided to first register circuit100to provide the occupancy state of second request buffer220.

The first register circuit100and the second register circuit200may perform an inter-node swapping operation for exchanging the first request FRQ and the second request BRQ. The inter-node swapping operation may be performed when the second register circuit200is in an issue-full state in which second register circuit200stores a maximum number of requests (e.g., six requests) and when the first request FRQ corresponds to an urgent request. For the inter-node swapping operation, the request stored in sixth storage unit206of second request buffer220is moved to backward buffer240and then first request FRQ from first register circuit100may be stored in sixth storage unit206of second request buffer220. The request temporarily stored in backward buffer240may be sent back as the second request BRQ through backward channel20and then stored in first storage unit101of first request buffer120.

FIG. 3is a diagram illustrating an example structure of requests stored in a register slicing circuit according to an example embodiment of the inventive concept.

Referring toFIG. 3, the respective requests RQ, which are stored in request buffers120and220and transferred through forward and backward channels10and20, may include a master identifier MID indicating the master device that issued the request RQ, a request identifier AxID for distinguishing the request RQ from the other requests from the same master device, an address-command ADD-COM representing the contents of the request RQ, a priority AxQ of the request RQ, and an urgent flag UP.

The urgent flag UP indicates whether an urgent service of the corresponding request RQ is required or not, such that the request having the flag of a first value (e.g., “1”) corresponds to an urgent request and the request having the flag of a second value (e.g., “0”) corresponds to a normal request. The urgent flag UP may include only one bit for representing whether the request RQ is the urgent request or not, or the urgent flag UP may include a plurality of bits for representing a degree of the urgency.

The request identifier AxID may represent a group of the requests that have a certain correlation. For example, the correlation may be a limit to a service order between the requests in the group. The limit to the service order may be a restriction that the request issued earlier has to be serviced earlier than the request issued later. The order-dependency flag OD, which will be described in greater detail below with reference toFIGS. 10A through 10F, may be a value based on the request identifier AxID.

FIGS. 4A and 4Bare diagrams for describing a normal inter-node transfer of a register slicing circuit according to an example embodiment of the inventive concept.

For convenience of illustration,FIGS. 4A and 4Billustrate only some storage units101,102and103in first request buffer120and some storage units204,205and206in second request buffer220. EMT represents an empty state or a non-occupied state inFIGS. 4A and 4B, for example, that a valid request is not stored in backward buffer240or storage unit206.

FIG. 4Arepresents the states of request buffers120and220and backward buffer240before the normal inter-node transfer of the request RQ3, andFIG. 4Brepresents the states of request buffers120and200and backward buffer240after the normal inter-node transfer of the request RQ3. As illustrated inFIG. 4A, second request buffer220is not in the issue-full state because sixth storage unit206is in the non-occupied state EMT.

The inter-node swapping operation is not required when second request buffer220is not in the issue-full state, and thus the normal inter-node transfer is performed such that the request RQ3in first storage unit101in first request buffer120is transferred through the forward channel10and then stored in sixth storage unit206of second request buffer220. As the one request RQ3is output, the other requests RQ4, RQ5and RQ6are shifted forward unit by unit.

Such normal inter-node transfer may be performed regardless of the request RQ3to be transferred being a normal request or a urgent request because second request buffer220is not in the issue-full state. Backward channel20and backward buffer240do not perform any operation and remain disabled in case of the normal inter-node transfer.

FIGS. 5A through 5Eare diagrams for describing an inter-node swapping operation of a register slicing circuit according to an example embodiment of the inventive concept.

For convenience of illustration,FIGS. 5A through 5Eillustrate only some storage units101,102and103in first request buffer120and some storage units204,205and206in second request buffer220. EMT represents an empty state or a non-occupied state inFIG. 5A through 5E, for example, that a valid request or a segment of the request is not stored in backward buffer240or storage units101and206. It is assumed that the one request RQ4corresponds to an urgent request and the other requests RQ1, RQ2, RQ3, RQ5and RQ6correspond to normal requests.

FIGS. 5A through 5Brepresent the states of request buffers120and220and the backward buffer240, which are changed by a unit time interval. For example, the unit time interval may be a cyclic period of an operational clock signal of register slicing circuit500ofFIG. 1.

Referring toFIG. 5A, the inter-node swapping operation may be performed when second request buffer220in second register circuit200is in an issue-full state in which second register circuit200stores a maximum number of requests (e.g., six requests) and when request RQ4corresponding to the above-mentioned first request FRQ is an urgent request.

Referring toFIG. 5B, the request RQ3stored in sixth storage unit206of second request buffer220is moved to backward buffer240, and then urgent request RQ4transferred through forward channel10is stored in sixth storage unit206of second request buffer220. First request buffer120does not perform the shifting operation during the inter-node swapping operation, even though the one request RQ4is output and first storage unit101of first request buffer120maintains the non-occupied state EMT.

As illustrated inFIGS. 5C, 5D and 5E, second request buffer120in second register circuit200ofFIG. 2may divide the request RQ3corresponding to the above-mentioned second request BRQ into a plurality of segments RQ3a, RQ3band RQ3c, and send back the segments RQ3a, RQ3band RQ3csequentially through backward channel20to first request buffer120in first register circuit100ofFIG. 2. The division and the backward transfer of the request RQ3may be performed using backward buffer240.FIGS. 5C, 5D and 5Eillustrate an example wherein the one request RQ3is divided and sent back as the three segments RQ3a, RQ3band RQ3c, but the number of the segments may be determined variously in relation with the number of the signal lines in backward channel20. Adopting the division of the segments, the number of the signal lines for the backward transfer may be reduced and the design burden may be reduced.

In addition,FIGS. 5C, 5D and 5Eillustrate that the urgent request RQ4transferred from first request buffer120to second request buffer220is swapped sequentially with normal requests RQ2, RQ1and RQ0that are stored earlier in second request buffer220. Such in-node swapping operation is further described in greater detail below with reference toFIG. 7.

FIGS. 6A and 6Bare diagrams for describing canceling of an inter-node swapping operation of a register slicing circuit according to an example embodiment of the inventive concept.

For convenience of illustration,FIGS. 6A and 6Billustrate only some storage units101,102and103in first request buffer120and some storage units204,205and206in second request buffer220. EMT represents an empty state or a non-occupied state in FIGS.6A and6B, for example, that a valid request, or a segment of a request, is not stored in backward buffer240or storage units101and206. It is assumed that the one request RQ4corresponds to an urgent request and the other requests RQ2, RQ3, RQ5and RQ6correspond to normal requests.

First register circuit100and second register circuit200may cancel the inter-node swapping operation, if second request buffer220in second register circuit200is relieved from the issue-full state before the inter-node swapping operation is completed.

Referring toFIG. 6A, second request buffer220may perform the shifting operation and thus sixth storage unit206of second request buffer220may be in the non-occupied state EMT before all of the segments RQ3a, RQ3band RQ3care sent back through backward channel20. In this case, it is not efficient that the remaining segments RQ3band RQ3cshould be sent back completely through backward channel20to first storage unit101of first request buffer120and then request RQ3is sent again as the first request FRQ through forward channel10to sixth storage unit206of second request buffer220.

Accordingly, referring toFIG. 6A, by cancelling the partially complete inter-node swapping operation, the segment RQ3aalready sent back and stored in first storage unit101is neglected and first request buffer120performs the shifting operation to move the request RQ5, RQ6and RQ7forward. Simultaneously the request RQ3temporarily stored in backward buffer240may be restored to the empty sixth storage206of second request buffer220.

FIG. 7is a diagram illustrating an example of a first control logic for an in-node swapping operation of a register slicing circuit according to an example embodiment of the inventive concept.

FIG. 7illustrates first control logic162for an in-node swapping operation together with the above-described first request buffer120including storage units101through106. First control logic162may be included in control unit160of first register circuit100inFIG. 2. First control logic162may include first through fifth logic gates G1through G5configured to generate swapping signals SW1through SW5based on first through sixth urgent flags UP1through UP6respectively included in the requests RQ1through RQ6.

The first logic gate G1is enabled in response to a first enable signal EN1to compare the first urgent flag UP1and the second urgent flag UP2. The first logic gate G1may activate the first swapping signal SW1only when the first urgent flag UP1has a second value (e.g., “0”) indicating that the corresponding request RQ1is a normal request and the second urgent flag UP2has a first value (e.g., “1”) indicating that the corresponding request RQ2is an urgent request. When the first swapping signal SW1is activated, control logic160inFIG. 2may perform the in-node swapping operation for exchanging the normal request RQ1in first storage unit101and the urgent request RQ2stored in second storage unit102. In the similar way, an in-node swapping operation may be performed between the request RQ3in third storage unit103and the request RQ4in fourth storage unit104in response to the third swapping signal SW3generated from third logic gate G3, and an in-node swapping operation may be performed between the request RQ5in fifth storage unit105and the request RQ6in sixth storage unit106in response to the fifth swapping signal SW5generated from fifth logic gate G3.

Second logic gate G2is enabled in response to a second enable signal EN2to compare the second urgent flag UP2and the third urgent flag UP3. Second logic gate G2may activate the second swapping signal SW2only when the second urgent flag UP2has the second value indicating that the corresponding request RQ2is a normal request and the third urgent flag UP3has the first value indicating that the corresponding request RQ3is an urgent request. When the second swapping signal SW2is activated, the control logic160inFIG. 2may perform the in-node swapping operation for exchanging the normal request RQ2in second storage unit102and the urgent request RQ3stored in third storage unit103. In the similar way, an in-node swapping operation may be performed between the request RQ4in fourth storage unit104and the request RQ5in fifth storage unit105in response to the fourth swapping signal SW4generated from fourth logic gate G4.

An operational error may be caused when the two adjacent logic gates are enabled simultaneously, because the one request may participate in the two inter-node swapping operations. To prevent this error, the first enable signal EN1and the second enable signal EN2may be activated complementarily as illustrated inFIGS. 8A and 8B.

FIGS. 8A and 8Bare diagrams illustrating examples of enable signals for first control logic162ofFIG. 7.

FIG. 8Aillustrates an example wherein the first enable signal EN1and the second enable signal EN2are activated with the same period as the cyclic period of the clock signal CLK, andFIG. 8Billustrates an example wherein the first enable signal EN1and the second enable signal EN2are activated with twice the cyclic period of the clock signal CLK. The first enable signal EN1and the second enable signal EN2are complementarily activated in both ofFIGS. 8A and 8B. As a result, the swapping operations by the odd-numbered logic gates G1, G3and G5and the swapping operations by the even-numbered logic gates G2and G4may be performed alternatively and the above-mentioned operational error may be prevented.

As the in-node swapping operation of first register circuit100is described with referenceFIG. 7, the in-node swapping operation of second register circuit200may be performed in the same way. As such, each of first register circuit100and second register circuit200may perform the in-node swapping operation based on the urgent flags UP1through UP6for exchanging a storing order of two requests adjacently stored in each of first register circuit100and second register circuit200such that an urgent request stored later may be exchanged with a normal request stored earlier.

FIG. 9is a diagram illustrating an example of a second control logic164for an inter-node swapping operation of a register slicing circuit according to an example embodiment of the inventive concept.

Second control logic164may be included in control unit160of first register circuit100inFIG. 2. Second control logic164may be implemented with a logic gate configured to generate an inter-node swapping signal INTSW based on the first urgent flag UP1and the second full count signal FC2. The first urgent flag is a flag included in the above-mentioned first request FRQ, that is, the request stored in first storage unit101of first request buffer120. The second full count signal FC2is provided from second register circuit200to indicate the issue-full state of second request buffer220in second register circuit200. Second control logic164may activate the inter-node swapping signal INTSW only when both: the first urgent flag UP1has the first value indicating that the corresponding request RQ1is an urgent request; and the second full count signal FC is activated to indicate that second register circuit200is in an issue-full state. The inter-node swapping signal INTSW may be provided from first register circuit100to second register circuit200and first and second register circuits100and200may perform the above-described inter-node swapping operation in response to the inter-node swapping signal INTSW.

FIGS. 10A through 10Fare diagrams illustrating an example sequence of an in-node swapping operation of a register slicing circuit according to an example embodiment of the inventive concept.

FIGS. 10A through 10Fillustrate states of first request buffer120storing the requests at time points Ta through Tf, respectively. The time interval between the adjacent time point, e.g. between the time points Ta and Tb and between the time points Tb and Tc may correspond to a swapping period. OD indicates the above-mentioned order-dependency flag and UP indicates the above-mentioned urgent flag. U indicates an urgent request and N indicates a normal request. As illustrated inFIGS. 10A through 10F, it is assumed that the second and sixth requests RQ2and RQ6are urgent requests, and the third and sixth requests RQ3and RQ6form a group such that the service order of the third and sixth requests RQ3and RQ6are limited within the group. That is, it is assumed that the third request RQ3has to be serviced earlier than the sixth request RQ6.

Referring toFIGS. 10A and 10B, the second request RQ2corresponding to an urgent request is swapped with the first request RQ1corresponding to a normal request, and the sixth request RQ6corresponding to an urgent request is swapped with the fifth request RQ5corresponding to a normal request, based on the respective urgent flags UP. Referring toFIGS. 10B and 10C, the sixth request RQ6corresponding to the urgent request is swapped again with the fourth request RQ4corresponding to a normal request. The second request RQ2may not be swapped by the in-node swapping operation because the urgent request RQ2is already stored in the most leading, or first, storage unit101in first request buffer120. As described above, the request RQ2in first storage unit101may be transferred to second register circuit200by the normal inter-node transfer, or the inter-node swapping operation. As illustrated inFIG. 10C, the third request RQ3stored earlier is a normal request and the sixth request RQ6stored later is an urgent request. The adjacent third and sixth requests RQ3and RQ6should normally be swapped according to the in-node swapping operation, but the in-node swapping may be inhibited due to the limit to the service order between the requests RQ3and RQ6in the group based on the order-dependency flags OD. In this case, the flow of the urgent request RQ6may be retarded. Thus, the urgent flag of the third request RQ3may be changed from the second value N indicating a normal request to the first value U indicating an urgent request as illustrated inFIG. 10D. Referring toFIGS. 10D and 10E, the third request RQ3that has been changed to an urgent request is swapped with the first request RQ1corresponding to a normal request. Referring toFIGS. 10E and 10F, the sixth request RQ6corresponding to an urgent request is swapped with the first request RQ1corresponding to a normal request.

As the in-node swapping operation of first register circuit100is described with referenceFIGS. 10A through 10F, the in-node swapping operation of second register circuit200may be performed in the same way.

Each of first register circuit100and second register circuit200may determine, based on the order-dependency flags OD, a group of the requests the service order of which is limited within the group. When the group includes an urgent request stored later and a normal request stored earlier, the urgent flag of a normal request stored earlier may be changed from the second value N to the first value U to effectively change the normal request into an urgent request.

As such, if there is a limit to the service order between the requests, the retardation of the flow of the urgent request may be prevented by changing the normal request stored earlier to the urgent request.

FIG. 11is a diagram illustrating a system on chip (SOC) according to example embodiments of the inventive concept.

Referring toFIG. 11, an SOC1000may include a plurality of master devices (MASTERi, i=1, 2, 3, 4)31,32,33and34, a plurality of slave devices (SLAVEj, j=1, 2, 3)41,42and43, and an interconnect device800. The master devices and/or slave devices may also be referred to as IP cores or IP blocks. WhileFIG. 11shows three slaves and four masters, this is merely one example, as the inventive concept is not limited to any particular number of slaves or masters.

Master devices31,32,33and34may generate requests to demand services from at least one of slave devices41,42and43, respectively. Master devices31,32,33and34may generate, in real time, urgent information and priority information indicating service requirement levels of respective master devices31,32,33and34.

Master devices31,32,33and34and slave devices41,42and43may be coupled to interconnect device800through respective channels. Interconnect device800may perform an arbitrating operation on the requests based on the priority information and may control request flows between master devices31,32,33and34and slave devices41,42and43based on the urgent information.

Interconnect device800includes at least one register slicing circuit (RSC)500as described with reference toFIGS. 1 through 10F, and register slicing circuit500may be inserted in an arbitrary path between master devices31,32,33and34and slave devices41,42and43. In an example embodiment, a plurality of register slicing circuits of the same or similar configuration may be included in interconnect device800.

As described above, register slicing circuit500may expedite the flow of the urgent requests between the network nodes spaced apart from each other with a relatively long distance, through the in-node operation and the inter-node swapping operations using the backward channel. In addition, if there is a limit to the service order between requests, the retardation of the flow of an urgent request may be prevented by changing a normal request stored earlier to an urgent request.

FIG. 12is a diagram illustrating an interconnect device adopting a register slicing circuit according to an example embodiment of the inventive concept.

Referring toFIG. 12, an interconnect device800amay have a multi-layered architecture for transferring a plurality of requests REQ1, REQ2, REQ3and REQ4from respective master devices to a common slave device through a plurality of arbitration points ABT1and ABT2.

Respective arbiter circuits may be disposed in the arbitration points ABT1and ABT2on which the two or more requests converge. The arbiter circuit may transfer requests one by one toward the slave device based on the priorities and/or the urgent flags of the competing requests. As illustrated inFIG. 12, for timing closure, slicing nodes RG1through RG6may be disposed at proper portions in interconnect device800a. Each of the slicing nodes RG1through RG6may have a configuration to support multiple outstanding requests. For example, above-described register circuit100may be included in each of the slicing nodes RG1through RG6.

Each of the slicing nodes RG1through RG6may perform the above-described in-node swapping operation. In addition, register slicing circuit500may include the slicing nodes RG5and RG6that are coupled through forward channel10and backward channel20to perform the inter-node swapping operation. As described above, the number N of the signal lines in backward channel20may be less than the number M of the signal lines in forward channel10. In this case, as described with reference toFIGS. 5A through 5E, the request RQ3sent back through backward channel20may be divided into the segments RQ3a, RQ3band RG3c, and the segments RQ3a, RQ3band RG3cmay be sent back sequentially through backward channel20from the slicing node RG6to the slicing node RG5.

Register slicing circuit500may efficiently expedite the flows of the urgent requests without excessively demoting the flows of the normal requests. Also the design burden of the complex SOC may be reduced by determining the proper number of signal lines in backward channel20.

A master device or the master intellectual property core or block (IP) may be divided into a hard realtime IP, a soft realtime IP, and a best effort IP, etc. depending on the type or the operational characteristic of the master IP.

The hard realtime IP may be an IP such as a display device that consumes data steadily and thus requires a necessary bandwidth. An underrun of a data buffer in the hard realtime IP may be caused if the necessary bandwidth is not satisfied. The hard realtime IP buffers the serviced data sufficiently in the data buffer if the necessary bandwidth is satisfied and controls the request flow itself such that the hard realtime IP issues the request according to the amount of the consumed data.

To reduce manufacturing cost, an external modem chip may share a memory in the SOC. Such an external modem chip may not operate normally if an average latency requirement level is not satisfied. It may be difficult to determine and fix the average latency requirement level because the type of the modem chip varies.

The soft realtime IP may be an IP such as a video codec that requires an average operation time. The video codec may have a frame rate such as 30 or 60 frames per second and may require an average decode/encode time. The bandwidth requirement level of the video codec may be changed according to respective frames and the video codec may require an average encoding time and/or an average decoding time. The video codec tends to proceed with the encoding/decoding of the next frame as soon as possible if the request flow is not controlled but the issue of the requests is limited due to dependency between the previously and currently processed data. Thus the operation speed of the video codec may satisfy the determined frame rate if the required bandwidth and/or latency are secured, but the operation speed of the codec may be sharply decreased if the latency becomes greater than a threshold value.

The best effort IP may be an IP such as two-dimensional or a three-dimensional graphics engine that issues requests endlessly if the request flow is not controlled and thus request flow control is needed in the best effort IP. It is desirable to support maximum service requirement levels of the best effort IP if one or more other IPs of higher priority than the best effort IP is/are not in the urgent state. If another IP is in the urgent state, the request flow from the best effort IP is limited so that the other IP of the higher priority may exit from the urgent state.

The latency-oriented IP such as a central processing unit (CPU) may have a variable bandwidth requirement level depending on the situation but its performance is directly influenced by an average latency. The request flow of the latency-oriented IP needs to be controlled based on the latency because the average bandwidth requirement level may not be defined.

According to such characteristics of the master IPs, the priority information and/or the urgent information of the respective master IPs may be provided to control the request flows.

FIG. 13is a diagram illustrating an example structure of urgent information used in an SOC according to an example embodiment of the inventive concept.

Referring toFIG. 13, the urgent information UGNT may include a master identifier MID indicating the master device that issued the corresponding request, a request identifier AxID for distinguishing the requests, and an urgent flag UP. As described below with reference toFIG. 14, the urgent information may be propagated into the interconnect device independently of the request flows, and the urgent flags in the requests, which are issued before and stored in the interconnect device may be upgraded in real time based on the corresponding urgent information UGNT.

FIG. 14is a diagram illustrating an interconnect device800badopting a register slicing circuit according to an example embodiment of the inventive concept.

Referring toFIG. 14, interconnect device800bmay include at least one arbitration point ABT and a plurality of slicing nodes RG1, RG2, RG3and RG4. As described above, register slicing circuit500may be implemented at the proper position in interconnect device800b.

As described with reference toFIG. 13, urgent information UGNT1and UGNT2may indicate the urgency of the corresponding requests REQ1and REQ2, and the urgent information UGNT1and UGNT2may be transferred to interconnect device800bin real time. Based on the urgent information UGNT1and UGNT2, the urgent flags stored in the slicing nodes RG1, RG2, RG3and RG4may be upgraded in real time.

FIG. 15is a block diagram illustrating a computing system or electronic system2000including a system on chip according to an example embodiment of the inventive concept.

Referring toFIG. 15, system2000includes a system on chip (SOC), a memory device1020, a storage device1030, an input/output (I/O) device1040, a power supply1050and an image sensor1060. Although it is not illustrated inFIG. 15, system2000may further include ports that communicate with a video card, a sound card, a memory card, a USB device, or other electronic devices.

SOC1010may be an application processor (AP) SOC including an interconnect device INT and a plurality of intellectual property cores or blocks (IPs) coupled to the interconnect device INT as described with reference toFIGS. 1 through 14. As illustrated inFIG. 15, the IPs may include a memory controller MC, a central processing unit CPU, a display controller DIS, a file system block FSYS, a graphic processing unit GPU, an image signal processor ISP, a multi-format codec block MFC, etc. For example, the memory controller MC may correspond to the above-described slave device and other IPs may correspond to the above-described master devices that use the memory controller MC as a common resource. Even though not specifically illustrated inFIG. 15, the interconnect device INT in SOC1010may include the above-described register slicing circuit.

SOC1010may communicate with memory device1020, storage device1030, input/output device1040and image sensor1060via a bus such as an address bus, a control bus, and/or a data bus. In at least one example embodiment, SOC1010is coupled to an extended bus, such as a peripheral component interconnection (PCI) bus.

Memory device1020may store data for operating the system2000. For example, memory device1020may be implemented with a dynamic random access memory (DRAM) device, a mobile DRAM device, a static random access memory (SRAM) device, a phase random access memory (PRAM) device, a ferroelectric random access memory (FRAM) device, a resistive random access memory (RRAM) device, and/or a magnetic random access memory (MRAM) device. Storage device1030may include a solid state drive (SSD), a hard disk drive (HDD), a CD-ROM, etc. Input/output device1040may include an input device (e.g., a keyboard, a keypad, a mouse, etc.) and an output device (e.g., a printer, a display device, etc.). Power supply1050supplies operation voltages for system2000.

Image sensor1060may communicate with SOC1010via the buses or other communication links. As described above, image sensor1060may be integrated with SOC1010in one chip, or image sensor1060and SOC1010may be implemented as separate chips.

System2000may comprise any computing system including at least one SOC. For example, system2000may include a digital camera, a mobile phone, a smart phone, a portable multimedia player (PMP), a personal digital assistant (PDA), a tablet computer, etc.

FIG. 16is a block diagram illustrating one or more interfaces employable with system2000ofFIG. 15according to an example embodiment of the inventive concept.

Referring toFIG. 16, a computing system1100may be implemented by a data processing device that uses or supports mobile industry processor interface (MIPI). Computing system1100may include SOC1110in a form of an application processor (AP), an image sensor1140, a display device1150, etc. SOC1110may include an interconnect device and service controllers as described above according to example embodiments.

A camera serial interface (CSI) host1112of SOC1110may perform a serial communication with a CSI device1141of the image sensor1140via a camera serial interface. In an example embodiment, CSI host1112may include a deserializer (DES), and CSI device1141may include a serializer (SER). A display serial interface (DSI) host1111of SOC1110may perform a serial communication with a DSI device1151of the display device1150via a display serial interface.

In an example embodiment, DSI host1111may include a serializer (SER), and DSI device1151may include a deserializer (DES). Computing system1100may further include a radio frequency (RF) chip1160performing a communication with SOC1110. A physical layer (PHY)1113of computing system1100and a physical layer (PHY)1161of RF chip1160may perform data communications based on a MIPI DigRF. SOC1110may further include a DigRF master1114that controls the data communications of the physical layer PHY1113.

Computing system1100may further include a global positioning system (GPS) block1120, storage1170, a microphone MIC1180, DRAM device1185, and a speaker1190. In addition, computing system1100may perform communications using an ultra wideband (UWB) block1210, a wireless local area network (WLAN) block1220, a worldwide interoperability for microwave access (WIMAX) block1230, etc. However, the structure and the interface of system1100may not be limited thereto.

A register slicing circuit according to at least one example embodiment of the inventive may be efficiently used in connecting master devices to at least one slave device which is commonly accessed by the master devices. At least one of the example embodiments may be applied to an SOC in which various semiconductor components are integrated as one chip. According to at least one example embodiment of the inventive concept, request flows may be controlled efficiently in systems such a digital camera, a mobile phone, a PDA, APMT, a smart phone, etc. requiring a smaller size, a higher performance and a higher operational speed.