Clock control and power management for semiconductor apparatus and system

A semiconductor apparatus according to the present invention includes a circuit including a predetermined function, a clock generating circuit that generates a clock signal supplied to the circuit, a clock control circuit that controls the clock generating circuit, and a notification signal generating circuit that generates a notification signal for notifying a timing for the clock control circuit to control the clock generating circuit. A voltage supplied to the semiconductor apparatus is adjusted according to the notification signal.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese patent application No. 2011-149875, filed on Jul. 6, 2011, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND

The present invention relates to a semiconductor apparatus and a system including the semiconductor apparatus.

In recent years, SoC (System-on-a-chip) technology that integrates a circuit capable of providing a plurality of functions into one semiconductor chip has been developed. In the semiconductor apparatus using this SoC technology, the size of the semiconductor apparatus and the operating frequency of the semiconductor apparatus tend to increase.

Japanese Unexamined Patent Application Publication Nos. 2000-023355 and 2009-106097 disclose the technique concerning a power supply apparatus that can control the output voltage to be stable. Japanese Unexamined Patent Application Publication No. 2007-220148 discloses a technique concerning the microprocessor capable of reducing the power consumption and increasing the speed.

SUMMARY

The present inventors have found various tasks while developing a semiconductor apparatus and a system including the semiconductor apparatus. One of the tasks of the present invention is to provide a semiconductor apparatus and a system including the semiconductor apparatus that can achieve stable operation.

An aspect disclosed in this document includes a semiconductor apparatus and the semiconductor apparatus includes a notification signal generating circuit.

Another aspect of the present invention is a system including a semiconductor circuit having the notification signal generating circuit and a power supply apparatus that supplies power to the semiconductor apparatus.

The present invention can provide a semiconductor apparatus and a system including the semiconductor apparatus that can achieve stable operation.

DETAILED DESCRIPTION

First Embodiment

Electronic Apparatus to which a Semiconductor Apparatus is Mounted

Hereinafter, an embodiment of the present invention is described with reference to the drawings. First, before explaining the embodiment of the present invention in detail, an electronic apparatus to which a semiconductor apparatus according to the present invention is mounted is described. This electronic apparatus is a wireless communication terminal including a communication function such as a mobile phone, a smartphone, a portable game terminal, a tablet terminal, and a notebook PC (Personal Computer).

FIGS. 1A and 1Bare external views showing an example of the wireless communication terminal to which the semiconductor apparatus according to the present invention is mounted.FIGS. 1A and 1Bshow a foldable mobile phone terminal as an example of the wireless communication terminal.FIG. 1Ashows a closed state (folded state) of a wireless communication terminal500as the foldable mobile phone terminal.FIG. 1Bshows an opened state of the wireless communication terminal500. The wireless communication terminal500has a configuration in which a first housing501and a second housing502are coupled by a hinge503. In the example ofFIGS. 1A and 1B, a plurality of operation buttons are disposed on the first housing501. On the other hand, the second housing502includes two display devices20A and30A and two camera devices20B and30B. The display devices20A and30A are LCD (Liquid crystal display) or OLED (Organic light-emitting diode) display ad the like.

The display device20A is disposed so that its display surface is positioned to a main surface (main surface) inside the second housing502. That is, the display device20A is a main display that is visually recognized by a user when the user operates the opened terminal500. On the other hand, the display device30A is a sub display that is disposed so that its display surface is positioned to an outer main surface (back surface) of the second housing502.

The camera device20B is a main camera with a lens unit positioned to the outer main surface (back surface) of the second housing502. On the other hand, the camera device30B is a sub camera with a lens unit positioned to the inner surface (front surface) of the second housing502.

Next, a configuration of the electronic apparatus (wireless communication terminal) to which the semiconductor apparatus according to the present invention is mounted is explained with reference toFIG. 2. As shown inFIG. 2, an electronic apparatus600includes an application processor601, a baseband processor602, an RF (Radio Frequency) subsystem603, a memory604, a battery605, and a power management IC (Integrated Circuit)606, a display unit607, a camera unit608, an operation input unit609, an audio IC (610), a microphone611, and a speaker612.

The application processor601reads a program stored to the memory604and performs processes for realizing various functions of the electronic apparatus600. For example, the application processor601reads OS (Operating System) program from the memory604and executes this OS software.

The baseband processor602performs a baseband process including a coding process (for example, error correction coding for a convolutional code, a turbo code, and the like) and a decoding process to the data transmitted and received by an electronic terminal. More specifically, the baseband processor602receives transmission data from the application processor601, performs the coding process to the received transmission data, and transmits the data to the RF subsystem603. Further, the baseband processor602receives reception data from the RF subsystem603, performs the decoding process to the received reception data, and transmits the data to the application processor601.

The RF subsystem603performs a modulation process or a demodulation process to the data transmitted and received by the electronic terminal600. More specifically, the RF subsystem603modulates the transmission data received from the baseband processor602with a carrier to generate a transmission signal and outputs the transmission signal via an antenna. Further, the RF subsystem603receives a reception signal via the antenna, demodulates the reception signal with a carrier to generate the reception data, and transmits the reception data to the baseband processor602.

The memory604stores the program and the data used by the application processor601. Further, the memory604includes a volatile memory that holds the stored data even when the power is cut off and a non-volatile memory that clears the stored data when the power is cut off.

The battery605is a battery that is used when the electronic apparatus600operates without depending on external power supply. Note that the electronic apparatus600may use the power of the battery605even when the external power supply is connected. In addition, it is preferable to use a secondary battery for the battery605.

The power management IC (606) generates internal power supply based on the battery605or the external power supply. This internal power supply is supplied to each block of the electronic apparatus600. At this time, the power management IC (606) controls the voltage of the internal power supply for each block that is supplied with the internal power supply. The power management IC (606) controls the voltage of the internal power supply in accordance with an instruction from the application processor601. The power management IC (606) can also control supply and stop of the internal power supply for each block. The power management IC (606) also controls charging to the battery605when there is the external power supply.

The display unit607is, for example, a liquid crystal display, and displays various images in accordance with the process in the application processor601. The images displayed on the display unit607includes a user interface image that gives operation instructions from the user to the electronic apparatus600, a camera image, a video, and the like.

The camera unit608obtains the image in accordance with the instructions from the application processor. The operation input unit609is a user interface that is operated by the user and gives operation instructions to the electronic apparatus600. The audio IC (610) encodes audio information obtained from the microphone611, generates audio data, and outputs the audio data to the application processor601while decoding audio data transmitted from the application processor601and driving the speaker612.

Configuration of the Semiconductor Apparatus

Next, the semiconductor apparatus according to this embodiment is explained.

FIG. 3is a block diagram showing a system including a semiconductor apparatus1and a power supply apparatus2according to the first embodiment. The semiconductor apparatus1shown inFIG. 3corresponds to the application processor601shown inFIG. 2, for example, and the power supply apparatus2shown inFIG. 3corresponds to the power management IC (606) shown inFIG. 2.

The semiconductor apparatus1shown inFIG. 3includes a DSP (Digital Signal Processing)3, a CPU (4), a multimedia circuit5, an internal power control circuit8, a clock control circuit9, a clock generating circuit10, and a notification signal generating circuit11. The DSP (3), the CPU (4), and the multimedia circuit5are circuits that include a predetermined function. The semiconductor apparatus1is SoC, for example.

The DSP (3) is a processor for processing a digital signal. The DSP (3) is a processor for performing specific processes at a high speed. When the DSP (3) is mounted on a mobile phone, for example, the DSP (3) is used for processes such as modulation and demodulation of an audio signal. The high-side power supply voltage is supplied to the DSP (3) from the power supply apparatus2via a terminal17. Further, the DSP (3) is connected to the low-side power supply (for example, ground) via a transistor Tr1, which is a switch. Accordingly, when the transistor Tr1is turned on (conductive state), the power is supplied to the DSP (3). A control signal CTR_DSP output from the internal power control circuit8controls turning on and off the power supplied to the DSP (3), which is to control turning on and off the transistor Tr1. The clock signal CLK_DSP output from the clock generating circuit10is supplied to the DSP (3). The DSP (3) is connected to an internal bus A (12), and can output and receive data to and from other circuits via the internal bus A (12) and other internal buses (internal buses B and C and the like). Note that a clock signal CLK_BUS_A output from the clock generating circuit10is supplied to the internal bus A (12).

The CPU (4) is a processor for performing various processes. The high-side power supply voltage is supplied to the CPU (4) from the power supply apparatus2via the terminal17. Further, the CPU (4) is connected to the low-side power supply via a transistor Tr2, which is a switch. That is, when the transistor Tr2is turned on (conductive state), the power is supplied to the DSP (4). A control signal CTR_CPU output from the internal power control circuit8controls turning on and off the power supplied to the CPU (4), which is to control turning on and off the transistor Tr2. A clock signal CLK_CPU output from the clock generating circuit10is supplied to the CPU (4). The CPU (4) is connected to the internal bus A (12), and can output and receive data to and from other circuits via the internal bus A (12) and other internal buses (the internal buses B and C and the like).

The multimedia circuit5is a circuit used for image processing and the like, and includes a multimedia CPU (6) and a multimedia module7. The high-side power supply voltage is supplied to the multimedia circuit5(that is, a power supply region including the multimedia CPU (6) and the multimedia module7) from the power supply apparatus2via the terminal17. Further, the multimedia circuit5is connected to the low-side power supply via a transistor Tr3, which is a switch. That is, when the transistor Tr3is turned on (conductive state), the power is supplied to the multimedia circuit5. A control signal CTR_MM output from the internal power control circuit8controls turning on and off the power supplied to the multimedia circuit5, which is to control turning on and off the transistor Tr3.

A clock signal CLK_MM_CPU output from the clock generating circuit10is supplied to the multimedia CPU (6). A clock signal CLK_MM_M output from the clock generating circuit10is supplied to the multimedia module7. Additionally, the multimedia CPU (6) and the multimedia module7are connected to each other via the internal bus B (13). The internal bus B (13) is connected to the internal bus A (12) via a bus bridge35. The multimedia CPU (6) and the multimedia module7can output and receive data to and from other circuits via the internal bus B (13) and other internal buses (for example internal buses A and C and the like). Note that a clock-signal CLK_BUS_B output from the clock generating circuit10is supplied to the internal bus B (13).

A CPU peripheral circuit15is a circuit used by the CPU (4). As the CPU peripheral circuit15, there are for example, a timer unit, a watchdog timer unit, a DMA (Direct Memory Access) unit, a low voltage detecting unit, a power-on reset (POR) unit, and the like. The CPU peripheral circuit15is connected to the internal bus C (14). When the CPU peripheral circuit15issues an interrupt request to the CPU (4), the CPU peripheral circuit15outputs an interrupt signal IP_INTR to an interrupt control circuit16.

The interrupt control circuit16receives an interrupt signal TML_INTR supplied externally via a terminal18and the interrupt signal IP_INTR output from the CPU peripheral circuit15, and outputs an interrupt signal INTR to the CPU (4), the internal power control circuit8, and the clock control circuit9. That is, the interrupt control circuit16outputs the interrupt signal INTR to the CPU (4), the internal power control circuit8, and the clock control circuit9at the timing when at least one of the interrupt signal TML_INTR and the interrupt signal IP_INTR is supplied. When the interrupt signal INTR is supplied to the CPU (4), the power and the clock signal is supplied to the CPU (4).

The internal power control circuit (power control circuit)8is a circuit for controlling turning on and off the DSP (3), the CPU (4), and the multimedia circuit5included in the semiconductor apparatus1. The internal power control circuit8is connected to the internal bus C (14). The internal bus C (14) is connected to the internal bus A (12). Note that a clock signal CLK_BUS_C output from the clock generating circuit10is supplied to the internal bus C (14).

FIG. 4is a block diagram showing details of the internal power control circuit8, the clock control circuit9, the clock generating circuit10, and the notification signal generating circuit11included in the semiconductor apparatus1according to this exemplary embodiment. As shown inFIG. 4, the internal power control circuit8includes a register31and a state machine (PWR)32(a second state machine). In response to an instruction set to the register31or the CPU interruption signal INTR, the state machine (PWR)32controls turning on and off the power of the DSP (3), the CPU (4), and the multimedia circuit5. When setting the instruction to the register31, the CPU (4) writes the instruction to the register31via the internal bus A (12) and the internal bus C (14), for example. In response to the set instruction, the register31outputs to the state machine (PWR)32a state setting signal SET_STATE for controlling the power of the DSP (3), the CPU (4), and the multimedia circuit5.

When the state machine (PWR)32controls the power of the DSP (3), the state machine (PWR)32outputs the control signal CTR_DSP and a power supply reset signal RESET_DSP to the DSP (3), and outputs a clock request signal CLK_REQ_DSP to the clock control circuit9. Further, when the state machine (PWR)32controls the power of the CPU (4), the state machine (PWR)32outputs the control signal CTR_CPU and a power supply reset signal RESET_CPU to the CPU (4), and outputs a clock request signal CLK_REQ_CPU to the clock control circuit9. Furthermore, when the state machine (PWR)32controls the power of the multimedia circuit5, the state machine (PWR)32outputs the control signal CTR_MM and a power supply reset signal RESET_MM to the multimedia circuit5, and outputs a clock request signal CLK_REQ_MM to the clock control circuit9.

Moreover, the state machine (PWR)32outputs to the notification signal generating circuit11a signal PRD_DSP_ON indicating a period in which the state machine (PWR)32is performing a power supply process, a signal PRD_CPU_ON indicating a period in which the state machine (PWR)32is performing the power supply process to the CPU (4), and a signal PRD_MM_ON indicating a period in which the state machine (PWR)32is performing the power supply process to the multimedia circuit5.

The state machine (PWR)32can have three states, which are the power supply process, a power stop state, and an idle state in order to control turning on and off the power of the DSP (3), the CPU (4), and the multimedia circuit5. For example, to turn on the power of the CPU (4), the state machine (PWR)32transitions in the order of the idle state→the CPU power supply process→the idle state. On the other hand, to turn off the power of the CPU (4), the state machine (PWR)32transitions in the order of the idle state→the CPU power stop process→the idle state.

More specifically, for example, in order to turn on the power of the CPU (4), the state machine (PWR)32transitions from the idle state to the CPU power supply process state, and performs the CPU power supply process (see the timing chart ofFIG. 12). At this time, the state machine (PWR)32outputs the clock request signal CLK_REQ_CPU to the clock control circuit9so that the clock signal CLK_CPU is supplied to the CPU (4). The state machine (PWR)32further outputs the control signal CTR_CPU to the gate of the transistor Tr2connected to the CPU (4) in order to turn on the power of the CPU (4). Moreover, the state machine (PWR)32asserts the power supply reset signal RESET_CPU to the CPU (4).

Then, the state machine (PWR)32cancels the power supply reset signal RESET_CPU (that is, the power supply reset signal RESET_CPU is set to low level) asserted to the CPU (4) at the timing when the clock signal supplied to the CPU (4) is stabilized. When the power supply reset signal RESET_CPU is set to low level, the state machine (PWR)32enters the idle state again. At this time, the power supply voltage and the clock signal CLK_CPU are supplied to the CPU (4). Further, while the state machine (PWR)32is performing the power supply process to the CPU (4), the state machine (PWR)32outputs the signal PRD_CPU_ON indicating the period of the power supply process to the notification signal generating circuit11.

Note that the case of turning on the power of the DSP (3) and the multimedia circuit5is the same as the above process.

The clock control circuit9is a circuit for controlling the clock generating circuit10. The clock control circuit9is connected to the internal bus C (14). As shown inFIG. 4, the clock control circuit9includes registers41to43and a state machine (CLK)44(a first state machine). The state machine (CLK)44receives a PLL setting signal SET_PLL stored to the register41, a frequency divider setting signal SET_DIV stored to the register42, a stop setting signal SET_STP stored to the register43, the CPU interrupt signal INTR, and the clock request signals CLK_REQ_DSP, CLK_REQ_CPU, and CLK_REQ_MM that are output from the internal power control circuit8.

For example, the PLL setting signal SET_PLL, the frequency divider setting signal SET_DIV, and the stop setting signal SET_STP stored to the registers41to43can be written by the CPU (4) accessing respectively to the registers41to43via the internal bus A (12) and the internal bus C (14). The PLL setting signal SET_PLL here is a signal for setting on and off of a PLL circuit51. The frequency divider setting signal SET_DIV is a signal for setting a frequency division ratio of a frequency divider53. The stop setting signal SET_STP is a signal for setting supply and stop of the clock signal to the DSP (3), the CPU (4), the multimedia circuit5, and the internal buses12to14.

Further, the state machine (CLK)44outputs a PLL control signal CTR_PLL to the PLL circuit51, a clock selecting signal SEL_CLK to a selector52, a frequency division control signal CTR_DIV to the frequency divider53, and a stop control signal CTR_STP to a stop control circuit54.

In order to control the clock signal supplied to the DSP (3), the CPU (4), the multimedia circuit5, and each internal bus12to14, the state machine (CLK)44can have four states, which are a clock frequency change process, a clock supply process, a clock stop process, and an idle state. For example, to change the frequency of the clock signal output from the clock generating circuit10, the state machine (CLK)44transitions in the order of the idle state→the clock frequency change process→the idle state. Further, to output the clock signal from the clock generating circuit10, the state machine (CLK)44transitions in the order of the idle state→the clock supply process→the idle state. On the other hand, to stop the clock signal output from the clock generating circuit10(to stop the clock signal generated in the clock generating circuit10using the stop control circuit54), the state machine (CLK)44transitions in the order of the idle state→the clock stop process→the idle state.

The state machine (CLK)44outputs a signal PRD_FRQ indicating a period in which the state machine (CLK)44is performing the frequency change process to the notification signal generating circuit11. The state machine (CLK)44further outputs a signal PRD_CLK indicating a period in which the state machine (44) is performing the clock supply process to the notification signal generating circuit11.

The clock generating circuit10is a circuit for generating the clock signal supplied to the DSP (3), the CPU (4), the multimedia circuit5, and each internal bus12to14. As shown inFIG. 4, the clock generating circuit10includes the PLL circuit51, the selector52, the frequency divider53, and the stop control circuit54.

The PLL circuit51receives an input clock signal CLK_IN output from an external oscillator circuit and the like via a terminal19. The PLL control signal CTR_PLL output from the clock control circuit9controls turning on and off the PLL circuit51. When the PLL control signal CTR_PLL is high level, the PLL circuit51is turned on, generates a signal of a predetermined frequency, and outputs the generated signal to the selector52. On the other hand, when the PLL control signal CTR_PLL is low level, the PLL circuit51is turned off. The PLL setting signal SET_PLL output from the register41sets turning on and off of the PLL circuit51.

The selector52selects an output or the input clock signal CLK_IN according to the clock selecting signal SEL_CLK and outputs the selected signal to the frequency divider53as a signal CLK_DIV_IN.

The frequency divider53divides the frequency of the signal CLK_DIV_IN according to the frequency division control signal CTR_DIV and outputs the frequency-divided signal to the stop control circuit54. The frequency division ratio of the frequency divider53is set based on the frequency divider setting signal SET_DIV output from the register42.

The stop control circuit54is a circuit for controlling whether or not to supply the clock signal output from the frequency divider53to the DSP (3), the CPU (4), the multimedia circuit5, and each internal bus12to14according to the stop control signal CTR_STP. The stop setting signal SET_STP output from the register43sets supply and stop of the clock signal to each circuit3to5and each internal buses12to14. Note that the clock signal output from the stop control circuit54of the clock generating circuit10is also referred to as an internal clock signal. Further, the circuit including the DSP (3), the CPU (4), the multimedia circuit5, and each internal bus12to14is hereinafter referred to as an internal circuit of the semiconductor apparatus1.

The notification signal generating circuit11generates a notification signal NTC_SIG. The notification signal NTC_SIG is a signal for notifying a timing for the clock control circuit9to control the clock generating circuit10. Further, the notification signal NTC_SIG is a signal for notifying the timing of the control in the internal power control circuit8.

That is, the notification signal generating circuit11generates the notification signal NTC_SIG according to the signals PRD_DSP_ON, PRD_CPU_ON, and PRD_MM_ON output from the internal power control circuit8, and signals the PRD_CLK and PRD_FRQ output from the clock control circuit9, and outputs the generated notification signal NTC_SIG to a terminal20.FIG. 5is a block diagram showing details of the notification signal generating circuit11. As shown inFIG. 5, the notification signal generating circuit11includes a register60, an AND1to an AND5, and an OR1.

A signal output from the register60is supplied to one input of the AND1, and the signal PRD_DSP_ON output from the internal power control circuit8is supplied to the other input, and an output from the AND1is supplied to the OR1. A signal output from the register60is supplied to one input of the AND2, and the signal PRD_CPU_ON output from the internal power control circuit8is supplied to the other input, and an output from the AND2is supplied to the OR1. A signal output from the register60is supplied to one input of the AND3, and the signal PRD_MM_ON output from the internal power control circuit8is supplied to the other input, and an output from the AND3is supplied to the OR1. A signal output from the register60is supplied to one input of the AND4, and the signal PRD_FRQ output from the internal power control circuit8is supplied to the other input, and an output from the AND4is supplied to the OR1. A signal output from the register60is supplied to one input of the AND5, and the signal PRD_CLK output from the internal power control circuit8is supplied to the other input, and an output from the AND5is supplied to the OR1. The OR1outputs logical OR of the signals output from the AND1to the AND5as the notification signal NTC_SIG.

The information concerning whether or not to allow the AND1to the AND5to output the signal corresponding to the notification signal NTC_SIG is stored in the register60. For example, the state machine (PWR)32of the internal power control circuit8outputs a signal in an active state (typically the signal is a high-level signal and the high-level signal is hereinafter explained as the signal in the active state) as the signal PRD_DSP_ON to the other input of the AND1while the state machine (PWR)32is performing the power supply process to the DSP (3). Then, when the AND1is allowed to output the signal corresponding to the notification signal NTC_SIG, the register60is set so that a high-level signal is supplied to one input of the AND1. In this case, the AND1outputs the high-level signal to the OR1while the signal PRD_DSP_ON is high level. At this time, the high-level notification signal NTC_SIG is output from the OR1.

On the other hand, when the AND1is not allowed to output the signal corresponding to the notification signal NTC_SIG, the register60is set so that a low-level signal is supplied to one input of the AND1. In this case, even when the signal PRD_DSP_ON is high level, the AND1outputs the low-level signal to the OR1. Accordingly, the signal corresponding to the notification signal NTC_SIG is not output from the AND1. This also applies to the AND2to AND5.

That is, by providing the register60and the AND1to the AND5, a signal can be selected from the signals PRD_DSP_ON, PRD_CPU_ON, PRD_MM_ON, PRD_FRQ, and PRD_CLK to use as an element for generating the notification signal NTC_SIG. The information concerning whether or not to allow the AND1to the AND5to output the signal corresponding to the notification signal NTC_SIG can be written by the CPU (4) accessing the register60via the internal bus A (12) and the internal bus C (14), for example.

Power Supply Apparatus

Next, the power supply apparatus2is explained. The power supply apparatus2includes a regulator21and a voltage setting circuit22. The power supply apparatus2is an LSI for power supply, for example. The regulator21can adjust the voltage output to a terminal24according to a control signal output from the voltage setting circuit22. The power supply output from the regulator21is supplied to the terminal17(VDD_IN) of the semiconductor apparatus1via the terminal24.

The voltage setting circuit22adjusts the voltage output from the regulator21according to the notification signal NTC_SIG supplied to a terminal23from the terminal20of the semiconductor apparatus1. Specifically, when the notification signal NTC_SIG is low level, the voltage setting circuit22sets the voltage of the regulator21so that a normally set voltage is output from the regulator21. On the other hand, when the notification signal NTC_SIG is high level (that is, in the period including a period in which an operating current increases in the semiconductor apparatus1), the voltage setting circuit22sets the voltage of the regulator21so that the voltage output from the regulator21will be higher than the normally set voltage. For example, the voltage setting circuit22sets the voltage of the regulator21so that the voltage as high as the semiconductor apparatus1to normally operate is output from the regulator21in the period when the notification signal NTC_SIG is high level. Further, a bypass capacitor C1is provided between the terminal17of the semiconductor apparatus1and the terminal24of the power supply apparatus2.

Note that the semiconductor apparatus1and the power supply apparatus2may be formed on the same chip or may be formed on different chips. When the semiconductor apparatus1and the power supply apparatus2are formed on different chips, the terminal20of the semiconductor chip (semiconductor apparatus1) is an external terminal for connecting to an external chip (power supply apparatus2).

Operation Example A of the Semiconductor Apparatus

Next, an operation example of the semiconductor apparatus1according to this embodiment is explained.FIG. 6is a timing chart showing an operation of the semiconductor apparatus1according to this embodiment. The timing chart shown inFIG. 6illustrates a case in which the internal clock signal of the semiconductor apparatus1changes from low speed and high speed.

The low-level PLL setting signal SET_PLL is output from the register41of the clock control circuit9before the timing t1. As the PLL control signal CTR_PLL is low level at this time, the PLL circuit51of the clock generating circuit10is turned off. Since the clock selecting signal SEL_CLK is low level, the selector52selects the input clock signal CLK_IN and outputs the input clock signal CLK_IN to the frequency divider53as the frequency divider input clock signal CLK_DIV_IN. The frequency divider53divides the frequency of the frequency divider input clock signal CLK_DIV_IN (for example, the frequency division ratio shall be two). Then, the frequency-divided signal is supplied to the internal circuit of the semiconductor apparatus1as the internal clock signal. In the example shown inFIG. 6, the power of the CPU (4) is turned on, and the power of the DSP (3) and the multimedia circuit5is turned off. Note that in this case, since the internal clock signal is low speed, the semiconductor apparatus1is in a sleep state.

After that, when an instruction for switching the internal clock signal from low speed to high speed is written to the register41of the clock control circuit9, the register41outputs the high-level PLL setting signal SET_PLL to the state machine (CLK)44.

The state machine (CLK)44receives the high-level PLL setting signal SET_PLL and at the timing t2and transitions from the idle state to the clock frequency change process. At this time, the state machine (CLK)44outputs the high-level signal PRD_FRQ indicating the period of performing the clock frequency change process to the notification signal generating circuit11. The notification signal generating circuit11receives the high-level signal PRD_FRQ and outputs the high-level notification signal NTC_SIG to the terminal20. At this time, the high-level signal is supplied from the register60to one input of the AND4shown inFIG. 5.

The high-level notification signal NTC_SIG output to the terminal20is supplied to the voltage setting circuit22via the terminal23of the power supply apparatus2. Then, the voltage setting circuit22sets the voltage of the regulator21so that the voltage output from the regulator21will be higher than the normally set voltage at the timing t3. Then the input voltage VDD_IN of the semiconductor apparatus1increases. At this time, the voltage setting circuit22sets the voltage of the regulator21so that the internal voltage at the time of voltage drop in the semiconductor apparatus1caused when the internal clock signal changes from low speed to high speed will be higher than a minimum operating voltage Vmin of the semiconductor apparatus1. The minimum operating voltage Vmin of the semiconductor apparatus1is a minimum value of the voltage on which an element (for example, a transistor) which composes the internal circuit of the semiconductor apparatus1normally operates.

The state machine (CLK)44, which transitioned from the idle state to the clock frequency change process at the timing t2, outputs the high-level PLL control signal CTR_PLL to the PLL circuit51in order to perform the clock frequency change process. Accordingly, the PLL circuit51is turned on. Then, at the timing t4after a predetermined time since the PLL circuit51is turned on and the PLL circuit511is stabilized, the state machine (CLK)44outputs the high-level clock selecting signal SEL_CLK to the selector52. The selector52receives the high-level clock selecting signal SEL_CLK and selects an output from the PLL circuit51.

After that, the internal clock signal of the semiconductor apparatus1becomes a high-speed clock signal (a clock signal with a higher frequency than the predetermined frequency) at the timing t5. As the internal clock signal of the semiconductor apparatus1becomes the high-speed clock signal, the operating current of the semiconductor apparatus1(operating current of the CPU (4) in the example ofFIG. 6) increases. The increase in the operating current reduces the internal voltage of the semiconductor apparatus1(the power supply voltage VDD_CPU in the CPU (4) in the example ofFIG. 6). However, as the input voltage VDD_IN of the semiconductor apparatus1is set higher than the normally set voltage, the internal voltage VDD_CPU of the semiconductor apparatus1will not be less than or equal to the minimum operating voltage Vmin of the semiconductor apparatus1. Accordingly, the semiconductor apparatus1can normally operate.

The clock frequency change process of the state machine (CLK)44is completed and the state machine (CLK)44enters the idle state at the timing t6. As the clock frequency change process is completed at this time, the state machine (CLK)44outputs the low-level signal PRD_FRQ to the notification signal generating circuit11. The notification signal generating circuit11receives the low-level signal PRD_FRQ and outputs the low-level notification signal NTC_SIG to the terminal20.

Since the notification signal NTC_SIG falls to low level, the voltage setting circuit22of the power supply apparatus2sets the voltage of the regulator21so that the voltage output from the regulator21will be the normally set voltage at the timing t7. Accordingly, the input voltage VDD_IN of the semiconductor apparatus1will be the normal voltage.

Operation Example B of the Semiconductor Apparatus

Next, another operation example of the semiconductor apparatus1according to this embodiment is explained.FIG. 7is a timing chart showing an operation of the semiconductor device according to this embodiment. The timing chart shown inFIG. 7illustrates the case in which the internal clock signal of the semiconductor apparatus1returns from the stop state to the supply state. Note that in this case, in the initial state before the timing t11, the PLL circuit51is turned on, and the selector52selects the output from the PLL circuit51, and the frequency divider53outputs the high-speed clock signal to the stop control circuit54. However, since the stop control signal CTR_STP is low level, the stop control circuit54does not supply the clock signal output from the frequency divider53to the internal circuit of the semiconductor apparatus1. Accordingly, although the PLL circuit51is turned on in the initial state, as the internal clock signal is not supplied to the CPU (4), the CPU (4) is in the sleep state.

When the CPU interrupt signal INTR rises to high level at the timing t11, the state machine (CLK)44transitions from the idle state to the clock supply process at the timing t12. At this time, the state machine (CLK)44outputs the high-level signal PRD_CLK indicating the period of performing the clock supply process to the notification signal generating circuit11. The notification signal generating circuit11receives the high-level signal PRD_CLK and outputs the high-level notification signal NTC_SIG to the terminal20. At this time, the high-level signal is supplied from the register60to one input of the AND5shown inFIG. 5.

The high-level notification signal NTC_SIG output to the terminal20is supplied to the voltage setting circuit22via the terminal23of the power supply apparatus2. Then, the voltage setting circuit22sets the voltage of the regulator21so that the voltage output from the regulator21will be higher than the normally set voltage at the timing t13. Accordingly, the input voltage VDD_IN of the semiconductor apparatus1increases.

Then, the state machine (CLK)44outputs the high-level stop control signal CTR_STP to the stop control circuit54of clock the generating circuit10at the timing t14in order to perform the clock supply process. When the stop control signal CTR_STP rises to high level, the stop control circuit54supplies the internal clock signal output from the frequency divider53to the internal circuit of the semiconductor apparatus1including the CPU (4) at the timing t15. When the internal clock signal is supplied to the CPU (4), the operating current of the CPU (4) increases. The increase in the operating current reduces the internal voltage VDD_CPU of the CPU (4). However, as the input voltage VDD_IN of the semiconductor apparatus1is set to the higher voltage than the normally set voltage at this time, the internal voltage VDD_CPU of the CPU (4) will not be less than or equal to the minimum operating voltage Vmin of the CPU (4). Accordingly, the CPU (4) can normally operate.

The clock supply process of the state machine (CLK)44is completed and the state machine (CLK)44enters the idle state at the timing t16. Since the clock supply process is completed, the state machine (CLK)44outputs the low-level signal PRD_CLK to the notification signal generating circuit11at this time. The notification signal generating circuit11receives the low-level signal PRD_CLK and outputs the low-level notification signal NTC_SIG to the terminal20.

As the notification signal NTC_SIG falls to low level, the voltage setting circuit22of the power supply apparatus2sets the voltage of the regulator21so that the voltage output from the regulator21will be the normally set voltage at the timing t17. Accordingly, the input voltage VDD_IN of the semiconductor apparatus1will be the normal voltage.

Comparative Example A

Next, a comparative example of the present invention according to this embodiment is explained.FIG. 8is a block diagram showing the comparative example of a system including a semiconductor apparatus and a power supply apparatus.FIG. 9is a block diagram showing details of an internal power control circuit8, a clock control circuit9, and a clock generating circuit10included in a semiconductor apparatus101shown inFIG. 8. The system including the semiconductor apparatus101and a power supply apparatus102shown inFIGS. 8 and 9is different from the system including the semiconductor apparatus1and the power supply apparatus2according to this embodiment shown inFIG. 3in the point that the notification signal generating circuit11is not included and the voltage setting circuit22does not set the voltage of the regulator21based on the notification signal NTC_SIG. Other points are same as the system including the semiconductor apparatus1and the power supply apparatus2shown inFIG. 3. Thus the same components are denoted by the same numerals and repeated explanation is omitted. Accordingly, since the semiconductor apparatus101shown inFIG. 8does not include the notification signal generating circuit11, the semiconductor apparatus101cannot generate the notification signal NTC_SIG for notifying the increase in the internal voltage.

First, an operation example of the semiconductor apparatus101shown inFIG. 8is explained as the comparative example of the present invention according to this embodiment.FIG. 10is a timing chart showing an operation of the semiconductor apparatus101shown inFIG. 8. The timing chart shown inFIG. 10illustrates the case in which an internal clock signal of the semiconductor apparatus101changes from low speed to high speed. The timing chart shown inFIG. 10corresponds to the timing chart shown inFIG. 6, and is different from the timing chart shown inFIG. 6in the point that the notification signal NTC_SIG is not generated and the input voltage VDD_IN is not set to the higher voltage than the normally set voltage.

As the PLL control signal CTR_PLL is low level in a similar manner as the case shown inFIG. 6before the timing t101shown inFIG. 10, the PLL circuit51of the clock generating circuit10is turned off. Further, since the clock selecting signal SEL_CLK is low level, the selector52selects the input clock signal CLK_IN and outputs the input clock signal CLK_IN to the frequency divider53as the frequency divider input clock signal CLK_DIV_IN. The frequency divider53divides the frequency of the divider input clock signal CLK_DIV_IN (for example, the frequency division ratio shall be two). Then, the frequency-divided signal is supplied to the internal circuit of the semiconductor apparatus101as the internal clock signal. Note that in this case, since the internal clock signal is low speed, the semiconductor apparatus101is in the sleep state.

Then, the register41outputs the high-level PLL setting signal SET_PLL to the state machine (CLK)44at the timing t101. The state machine (CLK)44transitions from the idle state to the clock frequency change process at the timing t102. The state machine (CLK)44, which transitioned to the clock frequency change process, outputs the high-level PLL control signal CTR_PLL to the PLL circuit51in order to perform the clock frequency change process. Accordingly, the PLL circuit51is turned on. Then, at the timing t103after a predetermined time since the PLL circuit51is turned on and the PLL circuit51is stabilized, the state machine (CLK)44outputs the high-level clock selecting signal SEL_CLK to the selector52. The selector52receives the high-level clock selecting signal SEL_CLK and selects the output from the PLL circuit51.

After that, the internal clock signal of the semiconductor apparatus101will be a high-speed clock signal at the timing t104. As the internal clock signal of the semiconductor apparatus101becomes the high-speed clock signal, the operating current of the CPU (4) increases. The increase in the operating current reduces the internal voltage VDD_CPU of the CPU (4). Therefore, the internal voltage VDD_CPU of the CPU (4) will temporarily be less than or equal to the minimum operating voltage Vmin of the CPU (4), and then the operation of the CPU (4) will be unstable.

After that, the clock frequency change process of the state machine (CLK)44is completed and the state machine (CLK)44enters the idle state at the timing t105.

Comparative Example B

Next, another operation example of the semiconductor apparatus101shown inFIG. 8is explained as a comparative example of the present invention according to this embodiment.FIG. 11is a timing chart showing an operation of the semiconductor apparatus101shown inFIG. 8. The timing chart shown inFIG. 11illustrates the case in which the internal clock signal of the semiconductor apparatus101returns to the supply state from the suspended state. Note that the timing chart shown inFIG. 11corresponds to the timing chart shown inFIG. 7, and is different from the timing chart shown inFIG. 7in the point that the notification signal NTC_SIG is not generated and the point that the input voltage VDD_IN is not set to the higher voltage than the normally set voltage.

In the example shown inFIG. 11, in the initial state before the timing t111, the PLL circuit51is turned on, the selector52selects the output from the PLL circuit51, and the frequency divider53outputs the high-speed clock signal to the stop control circuit54. However, since the stop control signal CTR_STP is low level, the stop control circuit54does not supply the clock signal output from the frequency divider53to the internal circuit of the semiconductor apparatus101. Accordingly, although the PLL circuit51is turned on in the initial state, as the internal clock signal is not supplied to the CPU (4), the CPU (4) is in the sleep state.

When the CPU interrupt signal INTR rises to high level at the timing t111, the state machine (CLK)44transitions from the idle state to the clock supply process at the timing t112. Then, the state machine (CLK)44outputs the high-level stop control signal CTR_STP to the stop control circuit54of the clock generating circuit10in order to perform the clock supply process.

When the stop control signal CTR_STP rises to high level, the stop control circuit54supplies the internal clock signal output from the frequency divider53to the internal circuit of the semiconductor apparatus101including the CPU (4) at the timing t114. When the internal clock signal is supplied to the CPU (4), the operating current of the CPU (4) increases. The increase in the operating current reduces the internal voltage VDD_CPU of the CPU (4). Therefore, the internal voltage VDD_CPU of the CPU (4) will temporarily be less than or equal to the minimum operating voltage Vmin of the CPU (4), and then the operation of the CPU (4) will be unstable.

After that, the clock supply process of the state machine (CLK)44is completed and the state machine (CLK)44enters the idle state at the timing t115.

In the system including the semiconductor apparatus101and the power supply apparatus102shown inFIG. 8, providing the bypass capacitor C1between the terminals17and24, for example, enables the system to deal with a rapid increase in the operating current of the semiconductor apparatus101. However, there is a problem in the semiconductor apparatus101shown inFIG. 8that an influence of a resistance component and an inductance component in the internal circuit of the semiconductor apparatus101(especially an influence of the resistance component and the inductance component in the wiring between each of the DSP (3), the CPU (4), and the multimedia circuit5and the terminal17) causes a delay until the amount of power supply increases after the rapid increase in the operating current.

Further, as for the rapid increase in the operating current of the semiconductor apparatus101, for example after the rapid increase in the operating current of the semiconductor apparatus101is detected, increasing the power supply to the power supply apparatus102temporarily increases the amount of current supply and enables dealing with the rapid increase in the operating current. That is, the power supply apparatus may have a first operating state with small current supply ability and small power consumption of the power supply apparatus itself and a second operating mode with large current supply ability and larger power consumption of the power supply apparatus itself as compared to that of the first operating state. When the operating current increases in the semiconductor apparatus, the power supply apparatus can automatically switch from the first operating state to the second operating state.

However, the power supply apparatus transitions from the first operating state to the second operating state after the increase in the operating current is detected in the semiconductor apparatus. Therefore, there has been a problem that when it takes time to detect the operating current and to supply power to the semiconductor apparatus from the power supply apparatus after the detection, the power cannot be supplied to the semiconductor apparatus in time.

As described so far, in the case in which the operating current rapidly increases in the semiconductor apparatus, when the amount of power supply to the semiconductor apparatus is not increased in a predetermined time, there is a large voltage drop in the internal circuit of the semiconductor apparatus. Then, there has been a problem that when this voltage drop causes the input voltage of the semiconductor apparatus to decrease lower than the minimum operating voltage Vmin of the transistor, the semiconductor apparatus malfunctions.

On the other hand, in the semiconductor apparatus1according to this embodiment, the notification signal generating circuit11is included that generates the notification signal NTC_SIG for notifying that the operating current increases in the internal circuit of the semiconductor apparatus1. Therefore, the increase in the operating current can be detected beforehand in the internal circuit of the semiconductor apparatus1. Accordingly, even when the operating current of the semiconductor apparatus rapidly increases, the power supplied to the semiconductor apparatus1can be increased without delay. Further, outputting the notification signal NTC_SIG from the terminal20enables the power supply apparatus2provided outside to be notified of the increase in the operating current of the semiconductor apparatus1. Furthermore, the voltage setting circuit22is provided in the power supply apparatus2for setting the voltage of the regulator21to be high while the notification signal NTC_SIG is in the active state, thereby increasing the input voltage of the semiconductor apparatus1only when it is necessary.

The notification signal generating circuit11of the semiconductor apparatus1according to this embodiment can generate the notification signal NTC_SIG according to the process of the state machine (CLK)44of the clock control circuit9. That is, the notification signal NTC_SIG in the active state can be generated in synchronization with the clock frequency change process (process for changing the internal clock signal in the semiconductor apparatus1from low speed to high speed) and the clock supply process (process for starting to supply the internal clock signal to the semiconductor apparatus1) of the state machine (CLK)44. As described above, generating the notification signal NTC_SIG in the active state according to the process of the state machine (CLK)44enables correct and easy generation of the notification signal NTC_SIG.

The present invention according to this embodiment described above can provide a semiconductor apparatus and a system including the semiconductor apparatus that can achieve stable operation.

Second Embodiment

Next, a second embodiment of the present invention is explained. The first embodiment explained the operation in the case of controlling the supply of the internal clock signal using the clock control circuit9of the semiconductor apparatus1(seeFIGS. 6 and 7). This embodiment explains the case of controlling the power of the DSP (3), the DPU (4), and the multimedia circuit5using the internal power control circuit8while controlling the supply of the internal clock signal using the clock control circuit9of the semiconductor apparatus1. Note that as the system including the semiconductor apparatus and the power supply apparatus used in this embodiment is the same as the system including the semiconductor1and the power supply apparatus2explained in the first embodiment (FIGS. 3 to 5), repeated explanation is omitted.

Operation Example C of the Semiconductor Apparatus

An operation example of the semiconductor apparatus1according to this embodiment is explained.FIG. 12is a timing chart showing an operation of the semiconductor apparatus according this embodiment. The timing chart shown inFIG. 12shows the case in which the internal power control circuit8turns on the power of the CPU (4), and further the clock control circuit9switches the internal clock signal from the stopped state to the supply state.

In the initial state before the timing t21, the PLL circuit51is turned on, the selector52selects the output from the PLL circuit51, and the frequency divider53outputs the high-speed clock signal to the stop control circuit54. However, since the stop control signal CTR_STP is low level, the stop control circuit54does not supply the clock signal output from the frequency divider53to the internal circuit of the semiconductor apparatus1.

When the CPU interrupt signal INTR rises to high level at the timing t21, the state machine (CLK)44transitions from the idle state to the clock supply process at the timing t22. At this time, the state machine (CLK)44outputs the high-level signal PRD_CLK indicating the period of performing the clock supply process to the notification signal generating circuit11. Further, when the CPU interrupt signal INTR rises to high level at the timing t21, the state machine (PWR)32transitions from the idle state to the power supply process at the timing t22. At this time, the state machine (PWR)32outputs the high-level signal PRD_CPU_ON indicating the period of performing the power supply process to the notification signal generating circuit11.

The notification signal generating circuit11receives the high-level signal PRD_CLK and the signal PRD_CPU_ON, and outputs the high-level notification signal NTC_SIG to the terminal20. At this time, the high-level signal is respectively supplied from the register60to one input of the AND2and one input of the AND5which are shown inFIG. 5.

The high-level notification signal NTC_SIG output to the terminal20is supplied to the voltage setting circuit22via the terminal23of the power supply apparatus2. Then, the voltage setting circuit22sets the voltage of the regulator21so that the voltage output from the regulator21will be higher than the normal set voltage at the timing t23. Accordingly, the input voltage VDD_IN of the semiconductor apparatus1increases.

Note thatFIG. 12explained the case in which the timing for the state machine (CLK)44to transition to the clock supply process is simultaneous (at the timing t22) as the timing for the state machine (PWR)32to transition to the power supply process. However, those timings may be different from each other. In this case, between the state machine (CLK)44and the state machine (PWR)32, at the timing when the state machine which transitions first outputs the high-level signal to the notification signal generating circuit11, the high-level notification signal NTC_SIG is output from the notification signal generating circuit11.

The state machine (PWR)32, which transitioned to the power supply process at the timing t22, outputs the high-level clock request signal CLK_REQ_CPU to the state machine (CLK)44of the clock control circuit9so that the clock signal CLK_CPU is supplied to the CPU (4). Further, the state machine (PWR)32outputs the high-level control signal CTR_CPU to the gate of the transistor Tr2connected to the CPU (4) in order to turn on the power of the CPU (4). When the high-level control signal CTR_CPU is supplied, a low-side power supply potential VSS_CPU of the CPU (4) gradually starts decreasing from the timing t24and will be an operational potential VSS after a predetermined time. Moreover, the operating current of the CPU (4) gradually starts increasing from the timing t24when the low-side power supply potential VSS_CPU of the CPU (4) starts decreasing.

The state machine (CLK)44, which is supplied with the high-level clock request signal CLK_REQ_CPU, outputs the high-level stop control signal CTR_STP to the stop control circuit54of the clock generating circuit10at the timing t25in order to perform the clock supply process. When the stop control signal CTR_STP rises to high level, the stop control circuit54supplies the clock signal output from the frequency divider53to the internal circuit of the semiconductor apparatus1including the CPU (4) at the timing t26.

At this time, the state machine (PWR)32is asserting the high-level power supply reset signal RESET_CPU to the CPU (4) so that the CPU (4) does not malfunction. During reset, all clock gating of the CPU (4) is canceled, for example, and the internal clock signal is supplied to all flip-flops for initialization. Therefore, the operating current of the CPU (4) increases. The increase in the operating current reduces the internal voltage VDD_CPU of the CPU (4). However, as the input voltage VDD_IN of the semiconductor apparatus1is set to the voltage higher than the normally set voltage at this time, the internal voltage VDD_CPU of the CPU (4) will not be less than or equal to the minimum operating voltage Vmin of the CPU (4). Accordingly, the CPU (4) is normally initialized.

Then, at the timing t27when the initialization process of the CPU (4) is completed (that is, after the initialization period), the state machine (PWR)32cancels the power supply reset signal RESET_CPU asserted to the CPU (4) (that is, the power supply reset signal RESET_CPU is set to low level). When the power supply reset signal RESET_CPU is set to low level, the state machine (PWR)32enters the idle state again. Since the power supply process is completed, the state machine (PWR)32outputs the low-level signal PRD_CPU_ON to the notification signal generating circuit11.

Further, the clock supply process of the state machine (CLK)44is completed and the state machine (CLK)44enters the idle state at the timing t27. At this time, as the clock supply process is completed, the state machine (CLK)44outputs the low-level signal PRD_CLK to the notification signal generating circuit11.

The notification signal generating circuit11receives the low-level signal PRD_CPU_ON and the signal PRD_CLK, and outputs the low-level notification signal NTC_SIG to the terminal20. Since the notification signal NTC_SIG falls to low level, the voltage setting circuit22of the power supply apparatus2sets the voltage of the regulator21so that the voltage output from the regulator21will be higher than the normally set voltage at the timing t28. Accordingly, the input voltage VDD_IN of the semiconductor apparatus1will be the normal voltage.

Note thatFIG. 12explained the case in which the timing when the state machine (CLK)44transitions to the idle state is simultaneous (at the timing t27) as the timing when the state machine (PWR)32transitions to the idle state. However, these timings may be different from each other. In this case, between the state machine (CLK)44and the state machine (PWR)32, at the timing when the state machine which transitions later outputs the low-level signal to the notification signal generating circuit11, the low-level notification signal NTC_SIG is output from the notification signal generating circuit11.

Operation Example D of the Semiconductor Apparatus

Next, another operation example of the semiconductor apparatus1according to this embodiment is explained.FIG. 13is a timing chart showing an operation of the semiconductor apparatus according to this embodiment. The timing chart shown inFIG. 13illustrates the case in which the internal power control circuit8turns on the power of the multimedia circuit5, and further the clock control circuit9switches the internal clock signal from the stopped state to the supply state.

In the initial state before the timing t31, the PLL circuit51is turned on, the selector52selects the output from the PLL circuit51, and the frequency divider53outputs the high-speed clock signal to the stop control circuit54. However, since the stop control signal CTR_STP is low level, the stop control circuit54does not supply the clock signal output from the frequency divider53to the internal circuit of the semiconductor apparatus1.

When the internal power state setting signal SET_STATE that turns on the multimedia circuit5is supplied at the timing t31, the state machine (PWR)32transitions from the idle state to the power supply process at the timing t32. At this time, the state machine (PWR)32outputs the high-level signal PRD_MM_ON indicating the period of performing the power supply process to the notification signal generating circuit11.

The notification signal generating circuit11receives the high-level signal PRD_MM_ON and outputs the high-level notification signal NTC_SIG to the terminal20. At this time, the high-level signal is supplied from the register60to one input of the AND3shown inFIG. 5.

The high-level notification signal NTC_SIG output to the terminal20is supplied to the voltage setting circuit22via the terminal23of the power supply apparatus2. Then, the voltage setting circuit22sets the voltage of the regulator21so that the voltage output from the regulator21will be higher than the normally set voltage at the timing t33. Accordingly, the input voltage VDD_IN of the semiconductor apparatus1increases.

The state machine (PWR)32, which transitioned to the power supply process at the timing t32, outputs the high-level clock request signal CLK_REQ_MM to the state machine (CLK)44of the clock control circuit9so that the clock signals CLK_MM_CPU, CLK_MM_M, and CLK_BUS_B are respectively supplied to the multimedia CPU (6), the multimedia module7, and the internal bus B (13). When the high-level clock request signal CLK_REQ_MM is supplied, the state machine (CLK)44transitions from the idle state to the clock supply process. At this time, the state machine (CLK)44outputs the high-level signal PRD_CLK indicating the period of performing the clock supply process to the notification signal generating circuit11. Note that the notification signal generating circuit11has already output the high-level notification signal NTC_SIG to the terminal20at this point.

Further, the state machine (PWR)32outputs the high-level control signal CTR_MM to the gate of the transistor Tr3connected to the multimedia circuit5in order to turn on the power of the multimedia circuit5. When the high-level control signal CTR_MM is supplied, a low-side power potential VSS_MM of the multimedia circuit5gradually starts decreasing from the timing t34and will be the low-side operational potential VSS after a predetermined time. The operating current of the multimedia circuit5gradually starts increasing from the timing t34when the low-side power supply potential VSS_MM of the multimedia circuit5starts decreasing.

The state machine (CLK)44, which is supplied with the high-level clock request signal CLK_REQ_MM, outputs the high-level stop control signal CTR_STP to the stop control circuit54of the clock generating circuit10at the timing t35in order to perform the clock supply process. When the stop control signal CTR_STP rises to high level, the stop control circuit54supplies the clock signal output from the frequency divider53to the internal circuit of the semiconductor apparatus1including the multimedia circuit5at the timing t36. At this time, the state machine (PWR)32is asserting the high-level power supply reset signal RESET_MM to the multimedia circuit5so that the multimedia circuit5does not malfunction. During reset, all clock gating of the multimedia circuit5is canceled, for example, and the internal clock signal is supplied to all the flip-flops for initialization. Therefore, the operating current of the multimedia circuit5increases. The increase in this operating current reduces an internal voltage VDD_MM of the multimedia circuit5. However, since the input voltage VDD_IN of the semiconductor apparatus1is set to the voltage higher than the normally set voltage, the internal voltage VDD_MM of the multimedia circuit5will not be less than or equal to the minimum operating voltage Vmin of the multimedia circuit5. Accordingly, the multimedia circuit5is normally initialized.

Then, at the timing t37when the initialization process of the multimedia circuit5is completed (that is, after the initialization period), the state machine (PWR)32cancels the power supply reset signal RESET_MM asserted to the multimedia circuit5(that is, the power supply reset signal RESET_MM is set to low level). When the power supply reset signal RESET_MM is set to low level, the state machine (PWR)32enters the idle state again. Since the power supply process is completed at this time, the state machine (PWR)32outputs the low-level signal PRD_MM_ON to the notification signal generating circuit11.

Further, the clock supply process of the state machine (CLK)44is completed and the state machine (CLK)44enters the idle state at the timing t37. Since the clock supply process is completed at this time, the state machine (CLK)44outputs the low-level signal PRD_CLK to the notification signal generating circuit11.

The notification signal generating circuit11receives the low-level signal PRD_MM_ON and the signal PRD_CLK, and outputs the low-level notification signal NTC_SIG to the terminal20. Since the notification signal NTC_SIG falls to low level, the voltage setting circuit22of the power supply apparatus2sets the voltage of the regulator21so that the voltage output from the regulator21will be the normally set voltage at the timing t38. Accordingly, the input voltage VDD_IN of the semiconductor apparatus1will be the normal voltage.

Note thatFIG. 13explained the case in which the timing for the state machine (CLK)44to transition to the idle state is simultaneous (at the timing t37) as the timing for the state machine (PWR)32to transition to the idle state. However, those timings may be different from each other. In this case, between the state machine (CLK)44and the state machine (PWR)32, at the timing when the state machine which transitions later outputs the low-level signal to the notification signal generating circuit11, the low-level notification signal NTC_SIG is output from the notification signal generating circuit11.

Next, a comparative example of the present invention according to this embodiment is explained. The comparative example to be explained below illustrates an operation of the system including the semiconductor apparatus and the power supply apparatus shown inFIG. 8(see the first embodiment).

Comparative Example C

First, an operation example of the semiconductor apparatus shown inFIG. 8is explained as the comparative example of the present invention according to this embodiment.FIG. 14is a timing chart showing an operation of the semiconductor apparatus shown inFIG. 8. The timing chart shown inFIG. 14illustrates the case in which the internal power control circuit8turns on the power of the CPU (4), and further the clock control circuit9switches the internal clock signal from the stopped state to the supply state. Note that the timing chart shown inFIG. 14corresponds to the timing chart shown inFIG. 12, and is different from the timing chart shown inFIG. 12in the point that the notification signal NTC_SIG is not generated and the input voltage VDD_IN is not set to the higher voltage than the normally set voltage.

In the initial state before the timing t121, the PLL circuit51is turned on, the selector52selects the output from the PLL circuit51, and the frequency divider53outputs the high-speed clock signal to the stop control circuit54. However, since the stop control signal CTR_STP is low level, the stop control circuit54does not supply the clock signal output from the frequency divider53to the internal circuit of the semiconductor apparatus101.

When the CPU interrupt signal INTR rises to high level at the timing t121, the state machine (CLK)44transitions from the idle state to the clock supply process at the timing t122. Further, when the CPU interrupt signal INTR rises to high level at the timing t121, the state machine (PWR)32transitions from the idle state to the power supply process at the timing t122.

The state machine (PWR)32, which transitioned to the power supply process at the timing t122, outputs the high-level clock request signal CLK_REQ_CPU to the state machine (CLK)44of the clock control circuit9so that the clock signal CLK_CPU is supplied to the CPU (4). Further, the state machine (PWR)32outputs the high-level control signal CTR_CPU to the gate of the transistor Tr2connected to the CPU (4) in order to turn on the power of the CPU (4). When the high-level control signal CTR_CPU is supplied, the low-side power supply potential VSS_CPU gradually starts decreasing from the timing t123and will be the operational potential VSS after a predetermined time. The operating current of the CPU (4) gradually starts increasing from the timing t123when the low-side power supply potential VSS_CPU of the CPU (4) starts decreasing.

The state machine (CLK)44, which is supplied with the high-level clock request signal CLK_REQ_CPU, outputs the high-level stop control signal CTR_STP to the stop control circuit54of the clock generating circuit10at the timing t124in order to perform the clock supply process. When the stop control signal CTR_STP rises to high level, the stop control circuit54supplies the clock signal output from the frequency divider53to the internal circuit of the semiconductor apparatus1including the CPU (4) at the timing t125. At this time, the state machine (PWR)32is asserting the high-level power supply reset signal RESET_CPU to the CPU (4) so that the CPU (4) does not malfunction. During reset, all the clock gating of the CPU (4) is canceled, for example, and the internal clock signal is supplied to all the flip-flops for initialization. Accordingly, the operating current of the CPU (4) increases. The increase in the operating current reduces the internal voltage VDD_CPU of the CPU (4). Therefore, the internal voltage VDD_CPU of the CPU (4) will be less than or equal to the minimum operating voltage Vmin of the CPU (4), and the initialization process is not normally performed.

Then, at the timing t126when the initialization process of the CPU (4) is completed (that is, after the initialization period), the state machine (PWR)32cancels the power supply reset signal RESET_CPU asserted to the CPU (4) (that is, the power supply reset signal RESET_CPU is set to low level). When the power supply reset signal RESET_CPU is set to low level, the state machine (PWR)32enters the idle state again.

Comparative Example D

Next, another operation example of the semiconductor apparatus shown inFIG. 8is explained as a comparative example of the present invention according to this embodiment.FIG. 15is a timing chart showing an operation of the semiconductor apparatus shown inFIG. 8. The timing chart shown inFIG. 15illustrates the case in which the internal power control circuit8turns on the power of the multimedia circuit5, and further the clock control circuit9switches the internal clock signal from the stopped state to the supply state. Note that the timing chart shown inFIG. 15corresponds to the timing chart shown inFIG. 13, and is different from the timing chart shown inFIG. 13in the point that the notification signal NTC_SIG is not generated and the input voltage VDD_IN is not set to the higher voltage than the normally set voltage.

In the initial state before the timing t131, the PLL circuit51is turned on, the selector52selects the output from the PLL circuit51, and the frequency divider53outputs the high-speed clock signal to the stop control circuit54. However, since the stop control signal CTR_STP is low level, the stop control circuit54does not supply the clock signal output from the frequency divider53to the internal circuit of the semiconductor apparatus101.

When the internal power state setting signal SET_STATE that turns on the multimedia circuit5is supplied at the timing t131, the state machine (PWR)32transitions from the idle state to the power supply process at the timing t132.

The state machine (PWR)32, which transitioned to the power supply process at the timing t132, outputs the high-level clock request signal CLK_REQ_MM to the state machine (CLK)44of the clock control circuit9so that the clock signals CLK_MM_CPU, CLK_MM_M, and CLK_BUS_B are respectively supplied to the multimedia CPU (6), the multimedia module7, and the internal bus B (13). When the high-level clock request signal CLK_REQ_MM is supplied, the state machine (CLK)44transitions from the idle state to the clock supply process.

Further, the state machine (PWR)32outputs the high-level control signal CTR_MM to the gate of the transistor Tr3connected to the multimedia circuit5in order to turn on the power of the multimedia circuit5. When the high-level control signal CTR_MM is supplied, the low-side power potential VSS_MM of the multimedia circuit5gradually starts decreasing from the timing t133and will be the low-side operational potential VSS after a predetermined time. Additionally, the operating current of the multimedia circuit5gradually starts increasing from the timing t133when the low-side power supply potential VSS_MM of the multimedia circuit5starts decreasing.

Moreover, the state machine (CLK)44, which is supplied with the high-level clock request signal CLK_REQ_MM, outputs the high-level stop control signal CTR_STP to the stop control circuit54of the clock generating circuit10at the timing t134in order to perform the clock supply process. When the stop control signal CTR_STP rises to high level, the stop control circuit54supplies the clock signal output from the frequency divider53to the internal circuit of the semiconductor apparatus101including the multimedia circuit5at the timing t135. At this time, the state machine (PWR)32is asserting the high-level power supply reset signal RESET_MM to the multimedia circuit5so that the multimedia circuit5does not malfunction. During reset, all clock gating of the multimedia circuit5is canceled, for example, and the internal clock signal is supplied to all the flip-flops for initialization. Accordingly, the operating current of the multimedia circuit5increases. The increase in this operating current reduces the internal voltage VDD_MM of the multimedia circuit5. Therefore, the internal voltage VDD_MM of the multimedia circuit5will be less than or equal to the minimum operating voltage Vmin of the multimedia circuit5, and the initialization process is not normally performed.

Then, at the timing t136when the initialization process of the multimedia circuit5is completed (that is, after the initialization period), the state machine (PWR)32cancels the power supply reset signal RESET_MM asserted to the multimedia circuit5(that is, the power supply reset signal RESET_MM is set to low level). When the power supply reset signal RESET_MM is set to low level, the state machine (PWR)32enters the idle state again.

In the system including the semiconductor apparatus101and the power supply apparatus102shown inFIG. 8, when the internal clock signal is supplied to the CPU (4) and the multimedia circuit5as shown inFIGS. 14 and 15, for example, the operating current of the CPU (4) and the multimedia circuit5increases. The increase in the operating current reduces the internal voltages VDD_CPU and VDD_MM of the CPU (4) and the multimedia circuit5. Therefore, there has been a problem that the internal voltages VDD_CPU and VDD_MM of the CPU (4) and the multimedia circuit5will temporarily be less than or equal to the minimum operating voltage Vmin of the CPU (4) and the multimedia circuit5, and the CPU (4) and the multimedia circuit5are not normally initialized.

On the other hand, in the semiconductor apparatus1according to this embodiment, the notification signal generating circuit11is included that generates the notification signal NTC_SIG for notifying that the operating current increases in the internal circuit of the semiconductor apparatus1. Therefore, the increase in the operating current can be detected beforehand in the internal circuit of the semiconductor apparatus1. Accordingly, even when the operating current of the semiconductor apparatus1rapidly increases, the power supplied to the semiconductor apparatus1can be increased without delay and the internal circuit of the semiconductor apparatus can be normally initialized.

Additionally, the notification signal generating circuit11of the semiconductor apparatus1according to this embodiment can generate the notification signal NTC_SIG according to the process of the state machine (PWR)32of the internal power control circuit8. That is, the notification signal NTC_SIG in the active state can be generated in synchronization with the power supply process for the DSP (3), the power supply process for the CPU (4), or the power supply process for the multimedia circuit5by the state machine (PWR)32. As described above, generating the notification signal NTC_SIG in the active state according to the process of the state machine (PWR)32enables correct and easy generation of the notification signal NTC_SIG. Note that other effects are same as the first embodiment.

AlthoughFIG. 12explained the case in which the CPU (4) switches from being turned off to turned on as an example andFIG. 13explained the case in which the multimedia circuit6switches from being turned off to turned on as an example, the case in which the DSP (3) switches from being turned off to turned on is the same as these cases.

The present invention according to this embodiment described above can provide a semiconductor apparatus and a system including the semiconductor apparatus that can achieve stable operation.

Third Embodiment

Next, a third embodiment of the present invention is explained. The first embodiment explained the operation in the case of controlling the supply of the internal clock signal using the clock control circuit9of the semiconductor apparatus1(seeFIGS. 6 and 7). The second embodiment explained the operation of controlling the power of the DSP (3), the CPU (4), and the multimedia circuit5using the internal power control circuit8while controlling the supply of the internal clock signal using the clock control circuit9of the semiconductor apparatus1(seeFIGS. 12 and 13). This embodiment explains an operation of controlling the power of the DSP (3), the CPU (4), and the multimedia circuit5using the internal control circuit8of the semiconductor apparatus1. Note that as a system including a semiconductor apparatus and a power supply apparatus used in this embodiment is same as the system including the semiconductor apparatus1and the power supply apparatus2explained in the first embodiment (FIGS. 3 to 5), repeated explanation is omitted.

Operation Example E of the Semiconductor Apparatus

An operation example of the semiconductor apparatus1according to this embodiment is explained.FIG. 16is a timing chart showing an operation of the semiconductor apparatus according to this embodiment. The timing chart shown inFIG. 16illustrates the case in which the internal power control circuit8turns on the power of the multimedia circuit5.

In the initial state before the timing t41, the PLL circuit51is turned on, the selector52selects the output from the PLL circuit51, and the frequency divider53outputs the high-speed clock signal to the stop control circuit54. Then, since the stop control signal CTR_STP is high level, the stop control circuit54supplies the internal clock signal output from the frequency divider53to the internal circuit of the semiconductor apparatus1. At this time, the state machine (CLK)44of the clock control circuit9is in the idle state. The power of the multimedia circuit5is turned off.

When the internal power state setting signal SET_STATE that turns on the multimedia circuit5is supplied at the timing t41, the state machine (PWR)32transitions from the idle state to the power supply process at the timing t42. At this time, the state machine (PWR)42outputs the high-level signal PRD_MM_ON indicating the period of performing the power supply process to the notification signal generating circuit11.

The notification signal generating circuit11receives the high-level signal PRD_MM_ON and outputs the high-level notification signal NTC_SIG to the terminal20. At this time, the high-level signal is supplied from the register60to one input of the AND3shown inFIG. 5.

The high-level notification signal NTC_SIG output to the terminal20is supplied to the voltage setting circuit22via the terminal23of the power supply apparatus2. Then, the voltage setting circuit22sets the voltage of the regulator21so that the voltage output from the regulator21will be higher than the normally set voltage at the timing t43. Accordingly, the input voltage VDD_IN of the semiconductor apparatus1increases.

Further, the state machine (PWR)32outputs the high-level control signal CTR_MM to the gate of the transistor Tr3connected to the multimedia circuit5in order to turn on the power of the multimedia circuit5. When the high-level control signal CTR_MM is supplied, the low-side power potential VSS_MM of the multimedia circuit5gradually starts decreasing from the timing t44and will be the low-side operational potential VSS at the timing t45when a predetermined time elapsed. At this time, the high-speed internal clock signal is supplied to the multimedia circuit5.

Further, the state machine (PWR)32is asserting the high-level power supply reset signal RESET_MM to the multimedia circuit5so that the multimedia circuit5does not malfunction. During reset, all clock gating of the multimedia circuit5is canceled, for example, and the internal clock signal is supplied to all the flip-flops for initialization. Therefore, the operating current of the multimedia circuit5increases. The increase in this operating current reduces the internal voltage VDD_MM of the multimedia circuit5. However, since the input voltage VDD_IN of the semiconductor apparatus1is set to the higher voltage than the normally set voltage, the internal voltage VDD_MM of the multimedia circuit5will not be less than or equal to the minimum operating voltage Vmin of the multimedia circuit5. Accordingly, the multimedia circuit5is normally initialized.

Then, at the timing t46when the initialization process of the multimedia circuit5is completed (that is, after the initialization period), the state machine (PWR)32cancels the power supply reset signal RESET_MM asserted to the multimedia circuit5(that is, the power supply reset signal RESET_MM is set to low level). When the power supply reset signal RESET_MM is set to low level, the state machine (PWR)32enters the idle state again. Since the power supply process is completed at this time, the state machine (PWR)32outputs the low-level signal PRD_MM_ON to the notification signal generating circuit11.

The notification signal generating circuit11receives the low-level signal PRD_MM_ON and outputs the low-level notification signal NTC_SIG to the terminal20. Since the notification signal NTC_SIG is set to low level, the voltage setting circuit22of the power supply apparatus2sets the voltage of the regulator21so that the voltage output from the regulator21will be the normally set voltage at the timing t47. Accordingly, the input voltage VDD_IN of the semiconductor apparatus1will be the normal voltage.

Comparative Example E

Next, a comparative example of the present invention according to this embodiment is explained. Note that the comparative example explained below illustrates the operation of the system including the semiconductor apparatus and the power supply apparatus shown inFIG. 8(see the first embodiment).FIG. 17is a timing chart showing an operation of the semiconductor apparatus shown inFIG. 8according to this embodiment. The timing chart shown inFIG. 17illustrates the case in which the internal power control circuit8turns on the power of the multimedia circuit5. Note that the timing chart shown inFIG. 17corresponds to the timing chart shown inFIG. 16, and is different from the timing chart shown inFIG. 16in the point that the notification signal NTC_SIG is not generated and the input voltage VDD_IN is not set to the higher voltage than the normally set voltage.

In the initial state before the timing t141, the PLL circuit51is turned on, the selector52selects the output from the PLL circuit51, and the frequency divider53outputs the high-speed clock signal to the stop control circuit54. Then, since the stop control signal CTR_STP is high level, the stop control circuit54supplies the internal clock signal output from the frequency divider53to the internal circuit of the semiconductor apparatus101. At this time, the state machine (CLK)44of the clock control circuit9is in the idle state. The power of the multimedia circuit5is turned off.

When the internal power state setting signal SET_STATE that turns on the multimedia circuit5is supplied at the timing t141, the state machine (PWR)32transitions from the idle state to the power supply process at the timing t142. After that, the state machine (PWR)32outputs the high-level control signal CTR_MM to the gate of the transistor Tr3connected to the multimedia circuit5in order to turn on the power of the multimedia circuit5. When the high-level control signal CTR_MM is supplied, the low-side power potential VSS_MM of the multimedia circuit5gradually starts decreasing from the timing t143and will be the low-side operational potential VSS at the timing t144when a predetermined time elapsed.

At this time, the state machine (PWR)32is asserting the high-level power supply reset signal RESET_MM to the multimedia circuit5so that the multimedia circuit5does not malfunction. During reset, all clock gating of the multimedia circuit5is canceled, for example, and the internal clock signal is supplied to all the flip-flops for initialization. Accordingly, the operating current of the multimedia circuit5increases. The increase in this operating current reduces the internal voltage VDD_MM of the multimedia circuit5. Therefore, the internal voltage VDD_MM of the multimedia circuit5will be less than or equal to the minimum operating voltage Vmin of the multimedia circuit5, and the initialization process is not normally performed.

Then, at the timing t145when the initialization process of the multimedia circuit5is completed (that is, after the initialization period), the state machine (PWR)32cancels the power supply reset signal RESET_MM asserted to the multimedia circuit5(that is, the power supply reset signal RESET_MM is set to low level). When the power supply reset signal RESET_MM is set to low level, the state machine (PWR)32enters the idle state again.

In the system including the semiconductor apparatus101and the power supply apparatus102shown inFIG. 8, as shown inFIG. 17, when the multimedia circuit5is turned on, the operating current of the multimedia circuit6increases. The increase in this operating current reduces the internal voltage VDD_MM of the multimedia circuit5. Therefore, the internal voltage VDD_MM of the multimedia circuit5will be less than or equal to the minimum operating voltage Vmin of the multimedia circuit5, and the multimedia circuit5is not normally initialized.

On the other hand, in the semiconductor apparatus1according to this embodiment, the notification signal generating circuit11is included that generates the notification signal NTC_SIG for notifying that the operating current increases in the internal circuit of the semiconductor apparatus1. Therefore, the increase in the operating current of the internal circuit of the semiconductor apparatus1can be detected beforehand. Accordingly, even when the operating current of the semiconductor apparatus1rapidly increases, the power supplied to the semiconductor apparatus1can be increased without delay and the internal circuit of the semiconductor apparatus1can be normally initialized.

Further, the notification signal generating circuit11of the semiconductor apparatus1according to this embodiment can generate the notification signal NTC_SIG according to the process of the state machine (PWR)32of the internal power control circuit8. That is, the notification signal NTC_SIG in the active state can be generated in synchronization with the power supply process for the DSP (3), the power supply process for the CPU (4), or the power supply process for the multimedia circuit5by the state machine (PWR)32. As described above, generating the notification signal NTC_SIG in the active state according to the process of the state machine (PWR)32enables correct and easy generation of the notification signal NTC_SIG. Note that other effects are same as the first embodiment.

AlthoughFIG. 16explained the case in which the multimedia circuit5switches from being turned off to turned on, the case in which the DSP (3) and the CPU (4) switch from being turned off to turned on is the same as the above case.

The present invention according to this embodiment described above can provide a semiconductor apparatus and a system including the semiconductor apparatus that can achieve stable operation.

Fourth Embodiment

Next, a fourth embodiment of the present invention is explained.

FIG. 18is a block diagram showing a system including a semiconductor apparatus81and a power supply apparatus2according to the fourth embodiment. The semiconductor device81according to this embodiment differs from the semiconductor apparatus1according to the first embodiment in the point that a multi-core processor91and a memory access detecting unit92are included as circuits including a predetermined function. Other points are same as the system including the semiconductor apparatus1and the power supply apparatus2. Thus the same components are denoted by the same numerals and repeated explanation is omitted.

As shown inFIG. 18, a CPU power supply region90of the semiconductor apparatus81includes the processor91(for example a multi-core processor) that has a CPU and a cache memory, and the memory access detecting unit92that detects the number of times the CPU accesses the cache memory and calculates an expected amount of current consumption in the processor based on the number of accesses. For example, the multi-core processor91includes a plurality of cores, a level one cache provided for each core, and a level two cache shared between the cores, and performs various processes.

A high-side power supply voltage VDD is supplied to the CPU power supply region90(that is, the multi-core processor91and the memory access detecting unit92) from the power supply apparatus2via the terminal17. Further, the CPU power supply region90is connected to the low-side power supply (for example, ground) via the transistor Tr2, which is a switch. Accordingly, when the transistor Tr2is turned on (conductive state), the power is supplied to the multi-core processor91and the memory access detecting unit92. The control signal CTR_CPU output from the internal power control circuit8controls turning on and off the power supplied to the CPU power region90, which is to control turning on and off the transistor Tr2. Moreover, the clock signal CLK_CPU output from the clock generating circuit10is supplied to the multi-core processor91. The multi-core processor91can transmit and receive data to and from other circuits via the internal bus A (12).

The memory access detecting unit92detects the number of activation (the number of accesses) of an access signal cen that is output when each core in the multi-core processor91accesses the level one cache and the level two cache, that is, an activation ratio. For example, accesses to the level one and the level two cache in each core are controlled by a memory controller included inside the multi-core processor91. The access signal cen is output from this memory controller. Then, the memory access detecting unit92calculates the expected amount of current consumption in the multi-core processor91based on the number of activation (the number of accesses) of the access signal cen. At this time, the memory access detecting unit92may calculate the expected amount of current consumption from the activation ratio of the access signal cen. When this expected amount of current consumption exceeds a reference value, the memory access detecting unit92outputs to the clock control circuit9a request signal psreq1for requesting a reduction in the frequency of the clock signal CLK_CPU supplied to the multi-core processor91. Further, also when an amount of change in this expected amount of current consumption exceeds a predetermined reference value, the memory access detecting unit92outputs to the clock control circuit9a request signal psreq2for requesting a reduction in the frequency of the clock signal CLK_CPU supplied to the multi-core processor91.

The internal power control circuit8outputs to the gate of the transistor Tr2the control signal CTR_CPU for controlling turning on and off the power of the CPU power supply region90. Moreover, the internal power control circuit8outputs to the clock control circuit9the clock request signal CLK_REQ_CPU for requesting supply of the clocks to the multi-core processor91.

The clock control circuit9periodically outputs to the memory access detecting unit92an execution signal check for causing the memory access detecting unit92to detect the number of activation and the activation ratio. Further, the clock control circuit9outputs the frequency division control signal CTR_DIV according to the request signals psreq1and psreq2output from the memory access detecting unit92to the clock generating circuit10. Furthermore, the clock control circuit9outputs the stop control signal CTR_STP according to the clock request signal CLK_REQ_CPU output from internal power control circuit8to the clock generating circuit10. That is, when the clock request signal CLK_REQ_CPU is output from the internal power control circuit8, the clock control circuit9outputs the stop control signal CTR_STP for canceling to stop the clock signal CLK_CPU. Accordingly, the clock generating circuit10starts outputting the clock signal CLK_CPU.

The clock generating circuit10can change the frequency of the clock signal CLK_CPU supplied to the multi-core processor91according to the frequency division control signal CTR_DIV output from the clock control circuit9. Further, the clock generating circuit10starts or stops outputting each clock signal according to the stop control signal CTR_STP output from the clock control circuit10. Note that the configuration and operation of the clock control circuit9and the clock generating circuit10are basically the same as those of the first to third embodiments.

The CPU peripheral circuit15is a circuit used by the multi-core processor91. As the CPU peripheral circuit15, there are for example a timer unit, a watchdog timer unit, a DMA (Direct Memory Access) unit, a low voltage detecting unit, a power-on-reset (POR) unit, and the like. The CPU peripheral circuit15is connected to the internal bus C (14).

As described above, the semiconductor apparatus81according to this embodiment includes the memory access detecting unit92that detects the number of accesses from each core to each memory region and can expect the amount of current consumption in the multi-core processor91. Therefore, when this expected amount of current consumption or the amount of change thereof exceed the reference value, the frequency of the clock signal CLK_CPU supplied to the multi-core processor91can be automatically reduced. Therefore, malfunction caused by exceeding the amount of allowable current can be prevented.

Although in this embodiment, the processor is the multi-core processor, it is needless to say that the present invention according to this embodiment can be applied to a single-core processor. It is rare in the multi-core processor that the operation rates of the cores increase at the same time. Therefore, increasing the amount of allowable current in accordance with such a case is not preferable as it leads to a larger size and an increase in the cost. This embodiment can temporarily reduce the frequency of the clock signal supplied to the processor without increasing the amount of allowable current only when the operation rates of cores increase at the same time. Accordingly, the present invention according to this embodiment is preferable for multi-core processor usage.

The first to fourth embodiments can be combined as desirable by one of ordinary skill in the art.