Inspection apparatus, image sensing apparatus, electronic equipment, and transportation equipment

An inspection apparatus includes a plurality of BIST circuits, each BIST circuit being configured to compare a test pattern output from an inspection target circuit with an expected value and output a signal indicating a comparison result, and a combining unit configured to generate one signal by performing a logical operation on a plurality of the signals indicating the comparison results which are output from the plurality of BIST circuits. The combining unit includes a plurality of level inspection circuits each configured to perform a level inspection of detecting a stuck-at fault. Each of the plurality of BIST circuits is connected to a corresponding one of the plurality of level inspection circuits.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to an inspection apparatus, an image sensing apparatus, an electronic equipment, and a transportation equipment.

Description of the Related Art

There is a method that uses a BIST (Built-In Self-Test) circuit for inspecting a memory. A BIST circuit stores a test pattern in a memory and determines whether there is a fault by comparing a value that has been read out from the memory with an expected value. Japanese Patent Laid-Open No. 6-194421 discloses a technique of sequentially inspecting a plurality of memories by using one BIST circuit when these memories are set as inspection targets.

SUMMARY OF THE INVENTION

When one BIST circuit is arranged for a plurality of inspection target circuits, the inspection time is prolonged since the inspection needs to be executed sequentially. An aspect of the present invention shortens the time taken to inspect the plurality of inspection target circuits by using the BIST circuit.

According to an embodiment, an inspection apparatus comprising: a plurality of BIST circuits, each BIST circuit being configured to compare a test pattern output from an inspection target circuit with an expected value and output a signal indicating a comparison result; and a combining unit configured to generate one signal by performing a logical operation on a plurality of the signals indicating the comparison results which are output from the plurality of BIST circuits, wherein the combining unit includes a plurality of level inspection circuits each configured to perform a level inspection of detecting a stuck-at fault, and each of the plurality of BIST circuits is connected to a corresponding one of the plurality of level inspection circuits, is provided.

DESCRIPTION OF THE EMBODIMENTS

Embodiments of the present invention will be described hereinafter with reference to the accompanying drawings. The same reference numerals are used for the same components throughout the various embodiments, and a repetitive description thereof will be omitted. The embodiments can be changed and combined appropriately. Some embodiments of the present invention are related to an inspection apparatus configured to perform a BIST inspection and a level inspection. A BIST inspection is an inspection for detecting a fault in an inspection target circuit by using a test pattern. A level inspection is an inspection for detecting a stuck-at fault in a node to which a signal indicating the result of the BIST inspection is output. A case in which such an inspection apparatus has been mounted on an image sensing apparatus will be exemplified hereinafter.

First Embodiment

An outline of an image sensing apparatus1according to this first embodiment will be described with reference to the block diagram ofFIG. 1. The image sensing apparatus1includes control units2, a vertical scanning unit3, a pixel portion4, column circuits5, horizontal scanning units6, signal output units7, a result combining unit8, and a CPU9. Each control unit2operates in accordance with a control signal such as a synchronization signal from the CPU9and a setting signal such as an operation mode. The pixel portion4includes a pixel array in which a plurality of pixels are arranged so as to form a plurality of rows and a plurality of columns. In this specification, a row direction indicates a horizontal direction (lateral direction) in each drawing, and a column direction indicates a vertical direction (longitudinal direction) in the drawing.

The vertical scanning unit3performs readout scanning of the pixel portion4and an electron shutter scanning operation in accordance with the control signal from each control unit2. Each of the column circuits5includes an amplification circuit, an analog/digital (AD) conversion circuit, and a column memory51. The column circuit5amplifies a signal from the pixel portion4by the amplification circuit, performs AD-conversion on the amplified signal by the AD conversion circuit, and holds the converted signal as a digital signal in the column memory51. Hence, the column memory51stores the signals from the pixel array of pixel portion4. The image sensing apparatus1includes two column circuits5, and for example, a signal from each pixel in an odd-number column of the pixel portion4is supplied to one column circuit5and a signal from each pixel in an even-number column of the pixel portion4is supplied to the other column circuit5. Each of the control units2supplies a test pattern to the column memory51of the corresponding column circuit5at the time of a BIST inspection.

Each of the horizontal scanning units6receives a control signal from the corresponding control unit2, and sequentially scans and outputs the signals held in the column memory51of the corresponding column circuit5. The image sensing apparatus1includes two horizontal scanning units6in correspondence with the two column circuits5. Each of the signal output units7includes a digital processing unit, BIST circuits71and72, a parallel/serial conversion circuit, and an output circuit such as LVDS (low Voltage Differential Signaling) or the like. The signal output unit7digitally processes the signal output from the corresponding horizontal scanning unit6, and outputs the processed signal as serial data to the outside of the image sensing apparatus1. The image sensing apparatus1includes two signal output units7in correspondence with the two horizontal scanning units6. One signal output unit7includes the BIST circuit71, and the other signal output unit7includes the BIST circuit72. In the following description, a description related to the BIST circuit71is similarly applicable to the BIST circuit72unless otherwise specified. Although the image sensing apparatus1includes two BIST circuits71and72in this embodiment, the number of BIST circuits is not limited to this, and the image sensing apparatus1includes a plurality of BIST circuits.

The result combining unit8generates one signal by performing a logical operation on a plurality of signals indicating the inspection results by the BIST circuits71and72. The result combining unit8may be included in another circuit. An inspection circuit is formed by the plurality of BIST circuits71and72and the result combining unit8. The CPU9controls the overall image sensing apparatus. The CPU9may be arranged in an image sensing system (for example, a camera) on which the image sensing apparatus1is mounted, that is, arranged outside the image sensing apparatus1. Each of column circuits5may not have an AD conversion function, and for example, the image sensing apparatus1may be formed so that AD conversion is performed outside the image sensing apparatus1. In this case, the arrangement of the horizontal scanning units6and the signal output units7is appropriately changed to be compatible with analog signal processing. Each of the control units2, the vertical scanning unit3, the horizontal scanning units6, the signal output units7, and the result combining unit8may be formed by a circuit. Hence, each control unit2may be referred to as a control circuit.

The BIST circuits71and72and the result combining unit8will be described in more detail with reference to the block diagram ofFIG. 2. The BIST circuit71includes a level output unit711and a pass/fail determination unit712. The BIST circuit72includes a level output unit721and a pass/fail determination unit722. The result combining unit8includes level inspection units81and82and an AND circuit83. Each of the level output unit711and the pass/fail determination unit712supplies an inspection result signal nfail1to the level inspection unit81via a node n01. Each of the level output unit721and the pass/fail determination unit722supplies an inspection result signal nfail2to the level inspection unit82via a node n02. The inspection result signals nfail1and nfail2indicate the BIST inspection results in the BIST inspection and are signals of two types of levels in the level inspection. The level inspection unit81supplies a signal corresponding to the level of the input inspection result signal nfail1to the AND circuit83. The level inspection unit82supplies a signal corresponding to the level of the input inspection result signal nfail2to the AND circuit83. The AND circuit83outputs a logical product, which is obtained from the output of the level inspection unit81and the level inspection unit82, as an inspection result signal nfail to a node n03.

When the BIST circuit71is to perform a BIST inspection, the control unit2writes an inspection value of the test pattern in the column memory51by controlling the column circuit5. The control unit2reads out the inspection value of the column memory51and supplies the value to the pass/fail determination unit712of the signal output unit7by controlling the horizontal scanning unit6. The pass/fail determination unit712determines whether each test pattern indicates a “pass” or “fail” result based on the inspection value, and supplies the determination result to the level inspection unit81. In the following example, the pass/fail determination unit712sets the level of the inspection result signal nfail1to high when the determination result is a “pass”, and sets the inspection result signal nfail1to low when the result is a “fail”. The level inspection unit81outputs a high-level signal when the high inspection result signal has been input and outputs a low-level signal when the low inspection result signal has been input. This is the same when the BIST circuit72is to perform the BIST inspection. Hence, the inspection result signal nfail is set to high level if both determination results of the two BIST circuits71and72indicate a “pass”, and the inspection result signal nfail is set to low level if at least one of the determination results is a “fail”.

The level output units711and721and the level inspection units81and82will be described in detail with reference to the block diagram ofFIG. 3. The inspection apparatus according to this embodiment executes a level inspection. More specifically, in a level inspection, an inspection for detecting a stuck-at fault in the plurality of nodes n01and n02that connect the BIST circuits71and72to the result combining unit8will be performed. A stuck-at fault is a state in which a circuit or an input terminal of an element or an output terminal of the element is fixed to either high level (logical value “1”) or low level (logical value “0”). The level output unit711includes a first level output unit7111and a second level output unit7112. In the level inspection, the first level output unit7111outputs a first level signal to the node n01which is connected to itself, and the second level output unit7112outputs a second level signal to the node n01which is connected to itself In this manner, the level output unit711outputs a plurality of signals of different levels for inspection. In the following example, assume that the level of the first level signal is high and the level of the second level signal is low.

The level inspection unit81includes a first level inspection unit811and a second level inspection unit812to determine whether a signal of two-types of levels has been supplied from the node n01. The first level inspection unit811holds a high-level signal when the level of the signal supplied to the level inspection unit81is the first level, and holds a low-level signal when otherwise. The second level inspection unit812holds a high-level signal when the level of the signal supplied to the level inspection unit81is the second level, and holds a low-level signal when otherwise. In the level inspection, when the first level inspection unit811and the second level inspection unit812are both held at high level, the level inspection unit81supplies, to a node n88, a signal (to be referred to as a high-level signal hereinafter) of a level indicating a “pass” as the result of the level inspection. Otherwise, the level inspection unit81supplies a signal (to be referred to as a low-level signal hereinafter) of a level indicating a “fail” to the node n88.

The level output unit721includes a first level output unit7211and a second level output unit7212and operates in the same manner as the level output unit711. The level inspection unit82includes a first level inspection unit821and a second level inspection unit822, and operates in the same manner as the level inspection unit81.

The output from the level inspection unit81is supplied to one of the input terminals of the AND circuit83via the node n88, and the output from the level inspection unit82is supplied to the other input terminal of the AND circuit83via a node n89. Hence, when the level inspection result of the node n01and the level inspection result of the node n02both indicate a “pass”, the result combining unit8sets the inspection result signal nfail which is to be output to the node n03to a signal (to be referred to as a high-level signal hereinafter) of a level indicating a “pass”. When at least one of the inspection results is a “fail”, the result combining unit8sets the inspection result signal nfail which is to be output to the node n03to a signal (to be referred to as a low-level signal hereinafter) of a level indicating a “fail”.

A more specific arrangement example of the result combining unit8will be described with reference to the block diagram ofFIG. 4. The level inspection unit81includes, other than the first level inspection unit811and the second level inspection unit812described above, AND circuits813and816and FFs814and817. The two input terminals of the AND circuit813are connected to the node n01and a node04, respectively. As described above, the inspection result signal nfail1is supplied to the node n01. An inspection start signal bist_start is supplied to the node n04. The inspection start signal bist_start is a signal that indicates the start of the level inspection and the BIST inspection. The level of the inspection start signal bist_start changes from low to high when these inspection operations are to be started, and changes from high to low when these inspection operations are to end. The output terminal of the AND circuit813is connected to the input terminal of the FF814. The output terminal of the FF814is connected to a node n815.

The first level inspection unit811includes an OR circuit8111and an FF8112. One input terminal of the OR circuit8111is connected to the node n815, and the other input terminal is connected to a node n8113. The output terminal of the OR circuit8111is connected to the input terminal of the FF8112. The output terminal of the FF8112is connected to the node n8113.

The second level inspection unit812includes an AND circuit8121, an OR circuit8122, and an FF8123. One input terminal of the AND circuit8121is connected to the node n815via a NOT circuit, and the other input terminal is connected to the node n8113. One input terminal of the OR circuit8122is connected to the output terminal of the AND circuit8121, and the other input terminal is connected to a node n8124. The output terminal of the OR circuit8122is connected to the input terminal of the FF8123. The output terminal of the FF8123is connected to the node n8124.

One input terminal of the AND circuit816is connected to the node n815, and the other input terminal is connected to the node n8124. The output terminal of the AND circuit816is connected to the input terminal of the FF817. The output terminal of the FF817is connected to the node n88.

The level inspection unit82includes, other than the first level inspection unit821and the second level inspection unit822described above, AND circuits823and826and FFs824and827. The connection between the elements of the level inspection unit82is the same as that of the level inspection unit81. The first level inspection unit821includes an OR circuit8211and an FF8212. The connection between the elements of the first level inspection unit821is the same as that of the first level inspection unit811. The second level inspection unit822includes an AND circuit8221, an OR circuit8222, and an FF8223. The connection between the elements of the second level inspection unit822is the same as that of the second level inspection unit812. The result combining unit8may detect a stuck-at fault that occurs between the FF814and the node n03and between the FF824and the node n03by a logic test (scan test). A fault in the AND circuits813and823can be detected by performing the level inspection.

An operation example of the BIST circuit71in the execution of the level inspection and the BIST inspection will be described with reference to the flowchart ofFIG. 5. The BIST circuit72also performs the same operation. The signal nfail1shown in the flowchart ofFIG. 5is replaced by the signal nfail2in the operation of the BIST circuit72. The BIST circuit71performs the operation for the level inspection in steps S11to S14and performs the operation for the BIST inspection in step S15after the level inspection has been completed.

In step S11, the level output unit711outputs the inspection result signal nfail1at low level. In step S12, the level output unit711outputs the inspection result signal nfail1at high level during M cycle(s) (M is an integer of 1 or more). More specifically, step S12is formed by steps S121to S124. In step S121, M which is the number of cycles set in advance is substituted into a loop variable Loop by the level output unit711. In step S122, the level output unit711outputs the inspection result signal nfail1at high level. In step S123, the level output unit711decrements the value of loop variable Loop by 1. In step S124, the level output unit711determines whether the value of the loop variable Loop is 0. If the loop variable Loop is 0 (YES in step S124), the level output unit711advances the process to step S131. If the value of the loop variable Loop is not 0 (NO in step S124), the level output unit711returns the process to step S122.

In step S13, the level output unit711outputs the inspection result signal nfail1at low level during N cycle(s) (N is an integer of 1 or more). More specifically, step S13is formed by steps S131to S134. The processes of steps S131to S134are the same as those of steps S121to S124except for the point that the number of cycles is N.

In step S14, the level output unit711outputs the inspection result signal nfail1at high level. In step S15, the pass/fail determination unit712performs the operation for the BIST inspection of the column memory51. More specifically, the pass/fail determination unit712performs pass/fail determination on each test pattern based on the inspection value written in the column memory51.

An operation example of the level inspection unit81at the execution of the level inspection and the BIST inspection will be described with reference to the flowchart ofFIG. 6. The level inspection unit82also performs the same operation. The signal nfail1shown in the flowchart ofFIG. 6is replaced by the signal nfail2in the operation of the level inspection unit82. The level inspection unit81performs the operation for the level inspection in steps S21to S24and subsequently performs the operation for the BIST inspection in step S25.

In step S21, the level inspection unit81sets the level of the node n88at low level. In step S22, the level inspection unit81determines whether the inspection result signal nfail1is at high level. If the inspection result signal nfail1is at high level (YES in step S22), the level inspection unit81advances the process to step S23. If the inspection result signal nfail1is not at high level (NO in step S22), the level inspection unit81returns the process to step S22. In step S23, the level inspection unit81determines whether the inspection result signal nfail1is at low level. If the inspection result signal nfail1is at low level (YES in step S23), the level inspection unit81advances the process to step S24. If the inspection result signal nfail1is not at low level (NO in step S23), the level inspection unit81returns the process to step S23.

In step S24, the level inspection unit81sets the level of the node n88to high. In step S25, the level inspection unit81performs the operation for the BIST inspection. More specifically, the level inspection unit81sets the level of the node n88to high if the level of the inspection result signal nfail1is high, and sets the level of the node n88to low if the level of the inspection result signal nfail1is low.

As described above, in the level inspection, the BIST circuit71switches the level of the inspection result signal nfail1to low after setting the level of this signal to high. Since “YES” will be determined in steps S22and S23ofFIG. 6if a stuck-at fault does not occur, the level inspection unit81will start the BIST inspection in step S25. On the other hand, since “YES” will not be determined in step S23if the inspection result signal nfail1remains high due to a stuck-at fault, the BIST inspection will not be started. In the same manner, since the “YES” will not be determined in step S22if the inspection result signal nfail1remains low due to a stuck-at fault, the BIST inspection will not be started. In either case, the level of the node n88will remain low if a stuck-at fault has occurred.

An operation example of the CPU9at the execution of the level inspection and the BIST inspection will be described with reference to the flowchart ofFIG. 7. This operation may be performed by another circuit instead of the CPU9. In step S31, the CPU9switches the level of the inspection start signal bist_start, which is to be supplied to the node n04, from low to high. Along with this process, 0 is substituted into a test cycle variable test_cycle. In addition, the CPU causes each of the two BIST circuits71and72to start the operation ofFIG. 5, and causes each of the two level inspection units81and82to start the operation ofFIG. 6.

In step S32, the CPU9determines whether the value of the test cycle variable test_cycle is M+N+P. M is the value to be substituted into the loop variable Loop in step S121ofFIG. 5, and indicates the number of cycles in which nfail1=high. N is the value to be substituted into the loop variable Loop in step S131ofFIG. 5, and indicates the number of cycles in which nfail1=low. P is the number of cycles other than these cycles, and is, for example, a value that has been determined in advance based on the step count of the FFs included in a signal path, a delay that occurs between the BIST circuits71and72and the result combining unit8, and the like. If the value of the test cycle variable test_cycle is M+N+P (YES in step S32), the CPU9advances the process to step S34. If the value of the test cycle variable test_cycle is not M+N+P (NO in step S32), the CPU9advances the process to step S33.

In step S33, the CPU9increments the value of the test cycle variable test_cycle by 1 and returns the process to step S32. In step S34, the CPU9determines whether the level of the inspection result signal nfail output to the node n03is high. Since (M+N+P) cycles have elapsed since the level inspection was started in step S31, the inspection result signal nfail will be high, as described above, if a stuck-at fault has not occurred in both of the nodes n01and n02. Thus, if the level of the inspection result signal nfail is high (YES in step S34), the CPU9advances to the process to step S35. If the level of the inspection result signal nfail is not high (NO in step S34), the CPU9advances the process to step S36.

In step S35, the CPU9starts an operation related to the BIST inspection. More specifically, the CPU9writes a test pattern in each column memory51by controlling the corresponding control unit2. At this stage, each of the two BIST circuits71and72has started the operation related to the BIST inspection in step S15ofFIG. 5, and each of the two level inspection units81and82has started the operation related to the BIST inspection in step S25ofFIG. 6. If the level of the inspection result signal nfail has switched from high to low, the CPU9detects that a fault has occurred in one of the two column memories51and performs corresponding processing. This processing may be a known processing operation.

In step S36, since a stuck-at fault has occurred in at least one of the nodes n01and n02, the CPU9performs processing corresponding to the stuck-at fault without performing the BIST inspection. This processing may be an error notification to a user of the image sensing apparatus1.

The level of each node corresponding to the inspection results of the level inspection and the BIST inspection will be described with reference to the timing charts ofFIGS. 8 to 11. In these timing charts, a reference symbol “clk” indicates a clock signal which is supplied to the respective circuits. Other reference symbols indicate the levels of the respective nodes. Assume that 2 is the value for each of M and N ofFIG. 5, and 4 is the value of P ofFIG. 7. Values different from these may be used as the values of M, N, and P. For example, M and N may have values different from each other. The values of M and N which are to be used in the BIST circuit71may be different from those to be used in the BIST circuit72. As will be shown in the timing chart hereinafter, the BIST circuit71and the BIST circuit72execute the level inspection in parallel and subsequently execute the BIST inspection in parallel.

The timing chart ofFIG. 8shows a case in which the inspection results of both the level inspection and the BIST inspection are a “pass”. At time t1, the CPU9starts step S31. This causes the level of the node n04to switch from low to high, and the level inspection is started. The level of node n04will be kept at high after this. The BIST circuits71and72start the process of step S11in response to the inspection start instruction from the CPU9. As result, the levels of the respective nodes n01and n02are set to low. The level inspection units81and82start the process of step S21in response to the inspection start instruction from the CPU9. As a result, the respective nodes n88and n89are set to low level.

At time t2, the CPU9starts the process of step S32, the BIST circuits71and72start the process of step S12, and the level inspection units81and82start the process of step S22. This causes the levels of the respective nodes n01and n02to switch from low to high. The time at which the BIST circuit71starts the process of step S12may be the same as or different from the time at which the BIST circuit72starts the process of step S12.

At time t3, since a high-level signal is supplied to both input terminals of the AND circuit813, the AND circuit813supplies a high-level signal to the input terminal of the FF814. Hence, the internal state of the FF814changes to high level, and the level of the node n815is switched from low to high accordingly. In the same manner, the internal state of the FF824changes to high level, and the level of a node n825is switched from low to high accordingly.

At time t4, the BIST circuits71and72end the process of step S12and start the process of step S13. This causes the levels of the nodes n01and n02to switch from high to low. Since a high-level signal is supplied to one input terminal of the OR circuit8111, the OR circuit8111supplies a high-level signal to the input terminal of the FF8112. Hence, the internal state of the FF8112changes to high level, and the level of the node n8113is switched from low to high accordingly. Since the node n8113is connected to the input terminal of the OR circuit8111, the FF8112will be held at high level even if the level of the node n815is subsequently changed. A state in which the FF8112is held at high level corresponds to the determination of nfail1=high in step S22. Thus, the level inspection unit81starts the process of step S23. In the same manner, the internal state of the FF8212changes to high level, and a node n8213is switched from low to high accordingly.

At time t5, since a low-level signal is supplied one input terminal (the terminal connected to the node n01) of the AND circuit813, the AND circuit813supplies a low-level signal to the input terminal of the FF814. Hence, the internal state of the FF814changes to low level, and the level of the node n815is switched high to low accordingly. In the same manner, the internal state of the FF824changes to low level, and the level of the node n825is switched from high to low accordingly.

At time t6, the BIST circuits71and72end the process of step S13and start the process of step S14. This causes the levels of the nodes n01and n02to switch from low to high. Since a high-level signal is supplied to both input terminals of the AND circuit8121, the AND circuit8121supplies a high-level signal to one input terminal of the FF8122. In response to this, the OR circuit8122supplies a high-level signal to the input terminal of the FF8123. Hence, the internal state of the FF8123changes to high level, and the level of the node n8124is switched from low to high accordingly. A state in which the FF8123is held at high level corresponds to a state in which nfail1=low has been determined in step S23. In the same manner, the internal state of the FF8223is changed to high level, and the level of a node n8224is switched from low to high.

At time t7, since a high-level signal is supplied to both input terminals of the AND circuit813, the AND circuit813supplies a high-level signal to the input terminal of the FF814. Hence, the internal state of the FF814changes to high level, and the level of the node n815is switched from low to high accordingly. In the same manner, the internal state of the FF824changes to high level, and the level of the node n825is switched from low to high accordingly.

At time t8, since a high-level signal is supplied to both input terminals of the AND circuit816, the AND circuit816supplies a high-level signal to the input terminal of the FF817. Hence, the internal state of the FF817changes to high level, and the level of the node n88is switched from low to high accordingly. This operation corresponds to the process of step S24. In the same manner, the internal state of the FF827changes to high level, and the level of the node n89is switched from low to high accordingly. Since a high-level signal is supplied to both input terminals of the AND circuit83, the AND circuit83switches the level of the inspection result signal nfail, which is to be output to the node n03, from low to high.

At time t9, the CPU9starts the process of step S34, the BIST circuits71and72start the process of step S15, and the level inspection units81and82start the process of step S25. Since the inspection result signal nfail is set to high level, the CPU9starts the process of step S35(BIST inspection). In the subsequent processes, the BIST circuits71and72will continue to supply high-level signals to the nodes n01and n02, respectively, if the result of the BIST inspection is a “pass”. As a result, the levels of the respective nodes n88and n89will be kept at high level, and the level of the inspection result signal nfail will be kept at high level. At time t10, when all of the BIST inspections have been completed while level of the inspection result signal nfail has been kept at high level, the CPU9determines that the BIST inspection indicates a “pass” result.

The timing chart ofFIG. 9shows a case in which the inspection result of the level inspection is a “pass” but the inspection result of the BIST inspection is a “fail”. The processes of times t1to t9are the same as those ofFIG. 8, and thus a description will be omitted. At time t11, upon determining that result of the BIST inspection is a “fail”, the BIST circuit71switches the level of the inspection result signal nfail, which is to be supplied to the node n01, from high to low. At time t12, since a low-level signal is supplied to one input terminal (the terminal connected to the node n01) of the AND circuit813, the AND circuit813supplies a low-level signal to the input terminal of the FF814. Hence, the internal state of the FF814changes to low level, and the level of the node n815is switched from high to low accordingly.

At time t13, since a low-level signal is supplied to one input terminal (the terminal connected to the node n815) of the AND circuit816, the AND circuit816supplies a low-level signal to the input terminal of the FF817. Hence, the internal state of the FF817is changed to low level, and the level of the node n88is switched from high to low accordingly. Since a low-level signal is supplied to one input terminal (the terminal connected to the node n88) of the AND circuit83, the AND circuit83switches the level of the inspection result signal nfail, which is to be output to the node n03, from high to low. Upon detecting that the inspection result signal nfail has changed to low level, the CPU9stops the BIST inspection and determines that the BIST inspection indicates a “fail” result.

The timing chart ofFIG. 10shows a case in which the inspection result of the level inspection is a “fail” because a stuck-at fault in which the node n01is maintained at high level has occurred. As shown inFIG. 10, the level of the node n01is constantly high. The operations of the BIST circuits71and72and the level inspection unit82are the same as those described inFIG. 8, and thus a description will be omitted.

The operation performed at time t1is the same as that performed inFIG. 8. However, since a stuck-at fault has occurred in the node n01, the level of the node n01is kept high even when the BIST circuit71changes the inspection result signal nfail1to low level. The operations performed at times t2and t3are the same as those performed inFIG. 8.

At time t4, the BIST circuit71ends the process of step S12and starts the process of step S13. However, since the stuck-at fault has occurred in the node n01, the level of the node n01is kept high. In the same manner as in the case ofFIG. 8, the internal state of the FF8112changes to high level, and the level of the node n8113is switched from low to high accordingly.

At time t5, since a high-level signal is supplied to both input terminals of the AND circuit813, the AND circuit813supplies a high-level signal to the input terminal of the FF814. Hence, the internal state of the FF814is kept at high level, and the level of the node n815is kept high accordingly.

At time t6, since a low-level signal is supplied one input terminal (the terminal connected to the NOT circuit) of the AND circuit8121, the AND circuit8121supplies a low-level signal to the one of the input terminals of the OR circuit8122. In response to this, the OR circuit8122supplies a low-level signal to the input terminal of the FF8123. Hence, the internal state of the FF8123is kept at low level, and the level of the node n8124is kept low accordingly. A state in which the FF8123is held at low level corresponds to a state in which nfail1≠low has been determined in step S23. This causes the level inspection unit81to repeat the process of step S23, and the process cannot advance to step S24.

At time t7, since a high-level signal is supplied to both input terminals of the AND circuit813, the AND circuit813supplies a high-level signal to the input terminal of the FF814. Hence, the internal state of the FF814is kept at high level, and the level of the node n815is kept high accordingly.

At time t8, since a low-level signal is supplied to one input terminal (the terminal connected to the node n8124) of the AND circuit816, the AND circuit816supplies a low-level signal to the input terminal of the FF817. Hence, the internal state of the FF817is kept at low level, and the level of the node n88is kept low accordingly. Since a low-level signal is supplied to one input terminal (the terminal connected to the node n88) of the AND circuit83, the AND circuit83maintains the inspection result signal nfail, which is to be output to the node n03, at low level.

At time t9, the CPU9starts the process of step S34, the BIST circuits71and72start the process of step S15, and the level inspection unit82starts the process of step S25. The level inspection unit81continues to execute the process of step S23. Since the inspection result signal nfail is set to low level, the CPU9starts the process of step S36(fault detection). The CPU9will not perform the BIST inspection in this case.

The timing chart ofFIG. 11shows a case in which the inspection result of the level inspection is a “fail” because a stuck-at fault in which the node n01is maintained at low level has occurred. As shown inFIG. 11, the level of the node n01is constantly low. The operations of the BIST circuits71and72and the level inspection unit82are the same as those described inFIG. 8, and thus a description will be omitted.

The operations performed at times t1and t2are the same as those performed inFIG. 8. However, since a stuck-at fault has occurred in the node n01, the level of the node n01is kept low even when the BIST circuit71changes the inspection result signal nfail1to high level.

At time t3, since a low-level signal is supplied to one input terminal (the terminal connected to the node n01) of the AND circuit813, the AND circuit813supplies a low-level signal to the input terminal of the FF814. Hence, the internal state of the FF814is kept at low level, and the level of the node n815is kept low accordingly.

At time t4, since a low-level signal is supplied to both input terminals of the OR circuit8111, the OR circuit8111supplies a low-level signal to the input terminal of the FF8112. Hence, the internal state of the FF8112is kept at low level, and the level of the node n8113is kept low accordingly. A state in which the FF8112is held at low level corresponds to a state in which nfail1≠high has been determined in step S22. This causes the level inspection unit81to repeat the process of step S22, and the process cannot advance to step S23.

At time t5, since a low-level signal is supplied to one input terminal (the terminal connected to the node n01) of the AND circuit813, the AND circuit813supplies a low-level signal to the input terminal of the FF814. Hence, the internal state of the FF814is kept at low level, and the level of the node n815is kept low accordingly.

At time t6, since a low-level signal is supplied to one input terminal (the terminal connected to the node n8113) of the AND circuit8121, the AND circuit8121supplies a low-level signal to one input terminal of the OR circuit8122. Accordingly, the OR circuit8122supplies a low-level signal to the input terminal of the FF8123. Hence, the internal state of the FF8123is kept at low level, and the level of the node n8124is kept low accordingly.

At time t7, since a low-level signal is supplied to one input terminal (the terminal connected to the node n01) of the AND circuit813, the AND circuit813supplies a low-level signal to the input terminal of the FF814. Hence, the internal state of the FF814is kept at low level, and the level of the node n815is kept low accordingly.

At time t8, since a low-level signal is supplied to both input terminals of the AND circuit816, the AND circuit816supplies a low-level signal to the input terminal of the FF817. Hence, the internal state of the FF817is kept at low level, and the level of the node n88is kept low accordingly. Since a low-level signal is supplied to one input terminal (the terminal connected to the node n88) of the AND circuit83, the AND circuit83maintains the inspection result signal nfail, which is to be output to the node n03, at low level.

At time t9, the CPU9starts the process of step S34, the BIST circuits71and72start the process of step S15, and the level inspection unit82starts the process of step S25. The level inspection unit81continues to execute the process of step S22. Since the inspection result signal nfail is set to low level, the CPU9starts the process of step S36(fault detection). The CPU9will not perform the BIST inspection in this case.

An operation example of the image sensing apparatus1will be described with reference to the flowchart ofFIG. 12. The image sensing apparatus1is mounted, for example, on a vehicle. In step S41, the CPU9performs an initial operation. More specifically, in step S411, the CPU9executes initial settings of the image sensing apparatus1. Next, in step S412, the CPU9executes the operation ofFIG. 7.

In step S42, the CPU9executes an image sensing operation. More specifically, in step S421, the CPU9generates a frame. Next, in step S422, the CPU9executes the operation ofFIG. 7. In step S43, the CPU9determines whether to end the image sensing operation. If the image sensing operation is to end (YES in step S43), the CPU9ends the processing. Otherwise (NO in step S43), the CPU9returns the process to step S42.

According to the above-described processing, the CPU9executes inspections using the BIST circuits71and72, that is, the level inspection and the BIST inspection, before the image sensing operation and in a period (a so-called vertical blanking period) between frames during the image sensing operation. If the results of both the level inspection and the BIST inspection are a “pass”, the CPU9will continue the operation ofFIG. 12. Otherwise, the processing ends. In this embodiment, since the level inspection and the BIST inspection of the plurality of column memories51are performed in parallel, the inspection time can be shortened.

In the embodiment described above, it is arranged so that the inspection circuit executes both the BIST inspection and the level inspection. Instead of this arrangement, it may be set so that the inspection circuit will execute only one of the BIST inspection and the level inspection. In either case, since the inspections by the BIST circuits71and72can be performed in parallel by using the result combining unit8to combine the inspection results obtained by the BIST circuits71and72, it is possible to shorten the inspection time of the plurality of inspection target circuits using the BIST circuit. Although the inspection target circuit of the BIST circuit was a memory in the above-described embodiment, the BIST circuit may inspect a logic circuit or another circuit instead.

In the above-described embodiment, the BIST circuits71and72may have the same circuit arrangement as each other or different circuit arrangements. The BIST circuits71and72will execute the operation of the above-describedFIG. 5even in a case in which they have circuit arrangements different from each other.

Second Embodiment

An inspection apparatus according to the second embodiment will be described with reference to the block diagram ofFIG. 13. A control unit2200controls a plurality of identical inspection circuits2700. Each inspection circuit2700includes a level output unit711. An inspection apparatus2800includes two identical level inspection units81and an AND circuit83. One inspection circuit2700is connected to one level inspection unit81via a node n2001, and the other inspection circuit2700is connected to the other level inspection unit81via a node n2002. The inspection apparatus2800supplies an inspection result signal nfail from the AND circuit83to an ATE (Automated Test Equipment) via a node n2003.

Other Embodiments

As application examples of the image sensing apparatus1according to the above-described embodiments, an electronic equipment such as a camera or a smartphone incorporating the image sensing apparatus1and a transportation equipment such as an automobile will be exemplified hereinafter. Here, the concept of a camera includes not only an apparatus whose main purpose is image sensing but also an apparatus (for example, a personal computer, a mobile terminal such as a tablet, etc.) that auxiliarly has an image sensing function.

FIG. 14is a schematic view of an equipment EQP incorporating an image sensing apparatus IM. An electronic equipment (an information equipment) such as a camera or a smartphone, a transportation equipment such as an automobile or an airplane, or the like is an example of the equipment EQP. The image sensing apparatus IM can include, other than a semiconductor device IC that includes a semiconductor chip on which an image sensing region IMR on which pixels PX have been arranged in an array has been arranged, a package PKG that contains the semiconductor device IC. The package PKG can include a base on which the semiconductor device IC is fixed and a lid member made of glass or the like which faces the semiconductor device IC, and connection members such as a bump and a bonding wire that connect a terminal arranged in the base to a terminal arranged in the semiconductor device IC. The equipment EQP can further include at least one of an optical system OPT, a control apparatus CTRL, a processing apparatus PRCS, a display apparatus DSPL, and a memory apparatus MMRY. The optical system OPT forms an optical image on the image sensing apparatus IM and is formed from, for example, a lens, a shutter, and a mirror. The control apparatus CTRL controls the operation of the image sensing apparatus IM and is a semiconductor device such as an ASIC. The processing apparatus PRCS processes signals output from the image sensing apparatus IM and is a semiconductor device such as a CPU or an ASIC for forming an AFE (Analog Front End) or a DFE (Digital Front End). The display apparatus DSPL is an EL display apparatus or a liquid crystal display apparatus that displays information (image) acquired by the image sensing apparatus IM. The memory apparatus MMRY is a magnetic device or a semiconductor device for storing information (image) acquired by the image sensing apparatus IM. The memory apparatus MMRY is a volatile memory such as an SRAM, DRAM, or the like or a nonvolatile memory such as a flash memory, a hard disk drive, or the like. A mechanical apparatus MCHN includes a driving unit or propulsion unit such as a motor, an engine, or the like. The mechanical apparatus MCHN in the camera can drive the components of the optical system OPT for zooming, focusing, and shutter operations. In the equipment EQP, signals output from the image sensing apparatus IM are displayed on the display apparatus DSPL and are transmitted externally by a communication apparatus (not shown) included in the equipment EQP. Hence, the equipment EQP may further include the memory apparatus MMRY and the processing apparatus PRCS that are separate from a storage circuit unit and a calculation circuit unit included in a control/signal processing circuit provided in the image sensing apparatus IM.

A camera incorporating the image sensing apparatus IM is applicable as a monitoring camera, an onboard camera mounted in a transportation equipment such as an automobile or a railroad car, or the like. A case in which the camera incorporating the image sensing apparatus IM is applied to a transportation equipment will be exemplified here. A transportation equipment2100is, for example, an automobile including an onboard camera2101shown inFIGS. 15A and 15B.FIG. 15Aschematically shows the outer appearance and the main internal structure of the transportation equipment2100. The transportation equipment2100includes an image sensing apparatus2102, an image sensing system ASIC (Application Specific Integrated Circuit)2103, a warning apparatus2112, and a control apparatus2113.

The above-described image sensing apparatus IM is used in the image sensing apparatus2102. The warning apparatus2112warns a driver when it receives an abnormality signal from an image-sensing system, a vehicle sensor, a control unit, or the like. The control apparatus2113comprehensively controls the operations of the image sensing system, the vehicle sensor, the control unit, and the like. Note that the transportation equipment2100need not include the control apparatus2113. In this case, the image sensing system, the vehicle sensor, and the control unit each can individually include a communication interface and exchange control signals via a communication network (for example, CAN standards).

FIG. 15Bis a block diagram showing the system arrangement of the transportation equipment2100. The transportation equipment2100includes the image sensing apparatus2102and the image sensing apparatus2102. That is, the onboard camera according to this embodiment is a stereo camera. An object image is formed by an optical section2114on each image sensing apparatus2102. An image signal output from each image sensing apparatus2102is processed by an image pre-processor2115and transmitted to the image sensing system ASIC2103. The image pre-processor2115performs processing such as S-N calculation and synchronization signal addition.

The image sensing system ASIC2103includes an image processor2104, a memory2105, an optical distance measuring unit2106, a parallax calculator2107, an object recognition unit2108, an abnormality detection unit2109, and an external interface (I/F) unit2116. The image processor2104generates an image signal by processing signals output from the pixels of each image sensing apparatus2102. The image processor2104also performs correction of image signals and interpolation of abnormal pixels. The memory2105temporarily holds the image signal. The memory2105may also store the position of a known abnormal pixel in the image sensing apparatus2102. The optical distance measuring unit2106uses the image signal to perform focusing or distance measurement of an object. The parallax calculator2107performs object collation (stereo matching) of a parallax image. The object recognition unit2108analyzes image signals to recognize objects such as a transportation equipment, a person, a road sign, a road, and the like. The abnormality detection unit2109detects a fault or an error operation of the image sensing apparatus2102. When a fault or an error operation has been detected, the abnormality detection unit2109transmits a signal indicating the detection of an abnormality to the control apparatus2113. The external I/F unit2116mediates the exchange of information between the units of the image sensing system ASIC2103and the control apparatus2113or the various kinds of control units.

The transportation equipment2100includes a vehicle information acquisition unit2110and a driving support unit2111. The vehicle information acquisition unit2110includes vehicle sensors such as a speed/acceleration sensor, an angular velocity sensor, a steering angle sensor, a ranging radar, and a pressure sensor.

The driving support unit2111includes a collision determination unit. The collision determination unit determines whether there is a possibility of collision with an object based on the pieces of information from the optical distance measuring unit2106, the parallax calculator2107, and the object recognition unit2108. The optical distance measuring unit2106and the parallax calculator2107are examples of distance information acquisition units that acquire distance information of a target object. That is, distance information includes pieces of information related to the parallax, the defocus amount, the distance to the target object, and the like. The collision determination unit may use one of these pieces of distance information to determine the possibility of a collision. Each distance information acquisition unit may be implemented by dedicated hardware or a software module.

An example in which the driving support unit2111controls the transportation equipment2100so as to avoid a collision with another object has been described. However, the present invention is also applicable to a case in which automated driving control for following another vehicle or automated driving control for preventing the vehicle from drifting out of the lane is performed.

The transportation equipment2100also includes driving apparatuses, which are used for movement or for supporting the movement, such as an air bag, an accelerator, a brake, a steering wheel, a transmission, an engine, a motor, wheels, propellers, and the like. The transportation equipment2100also includes control units for these apparatuses. Each control unit controls a corresponding driving apparatus based on a control signal of the control apparatus2113.

The image sensing system used in each embodiment is applicable not only to an automobile and a railroad car but also to, for example, a transportation equipment such as a ship, an airplane, or an industrial robot. In addition, the image sensing system is applicable not only to a transportation equipment but also to an equipment that uses object recognition widely such as an ITS (Intelligent Transportation System).

This application claims the benefit of Japanese Patent Application No. 2017-245393, filed Dec. 21, 2017, which is hereby incorporated by reference herein in its entirety.