Varactor shunt switches with parallel capacitor architecture

A parallel capacitor varactor shunt switch device may include a shunt layer, a coplanar waveguide (CPW) layer, and a tunable thin film dielectric layer that is interposed between the shunt layer and the CPW layer. The tunable thin film dielectric layer electrically isolates the shunt layer from the CPW layer. The shunt layer includes a plurality of parallel shunt lines. The CPW layer includes a CPW signal transmission line with two CPW ground lines parallel to the CPW signal transmission line. A plurality of varactor areas equal in number to the plurality of parallel shunt lines are defined in the CPW signal transmission line, each varactor area corresponding to an overlap of the CPW signal transmission line with a respective shunt line and each respective parallel shunt line and its corresponding varactor area defines a capacitor.

BACKGROUND

The present disclosure generally relates to thin film varactor device structures and, in particular, to nanostructured dielectric thin-film varactors having a parallel capacitor architecture.

High K tunable, microwave dielectrics such as barium strontium titanate (BaxSr(1-x)TiO3), or BST, are gaining acceptance in microwave integrated circuits due to a large need for tunable/reconfigurable circuits. Semiconductor varactor diodes and PIN diodes can have relatively large Q below 10 GHz, but the Q can drop down drastically above 10 GHz making them less attractive for applications above 10 GHz. Radio-frequency (RF) microelectromechanical system (MEMS) switches can offer high Q at microwave and millimeterwave frequencies, but can be complex in nature, and the slow speed of switching can be undesirable for many applications. Ferroelectric varactors can be characterized by fast switching speed, ease of integration with silicon (Si) monolithic microwave integrated circuits (MMICs), and can have reasonable Q at microwave and millimeter-wave frequencies.

Ongoing needs remain for an improving RF performance over a broad frequency range that allows for larger signal isolation at lower frequencies.

SUMMARY

According to some embodiments, a parallel capacitor varactor shunt switch (VSS) device may include a shunt layer, a signal layer, and a tunable thin film dielectric layer that is interposed between the shunt layer and the signal layer. The tunable thin film dielectric layer electrically isolates the shunt layer from the signal layer. The shunt layer includes a first shunt-layer ground line, a second shunt-layer ground line parallel to the first shunt-layer ground line, and a plurality of parallel shunt lines. Each of the parallel shunt lines from the plurality of parallel shunt lines electrically connects the two ground lines. The coplanar waveguide (CPW) layer includes a CPW signal transmission line interposed between two ground lines. The plurality of shunt lines in the shunt layer are not in parallel to the CPW signal transmission line in the signal layer. A plurality of varactor areas equal in number to the plurality of parallel shunt lines are defined in the CPW signal transmission line, each varactor area corresponding to an overlap of the CPW signal transmission line with a respective shunt line and each respective parallel shunt line and its corresponding varactor area defines a capacitor.

Accordingly, it is a feature of some embodiments of the present disclosure to improve the tunability and RF performance of a nanostructured BST thin film varactor by increasing the number of parallel capacitors through increasing the number of shunt lines in the VSS device. Other features of the embodiments of the present disclosure will be apparent in light of the description provided herein.

DETAILED DESCRIPTION

Referring to the exemplary embodiment ofFIGS. 1 and 2, a parallel capacitor varactor shunt switch (VSS) device10may comprise a shunt layer30, a signal layer25, a substrate20, and a tunable dielectric thin film layer35. The tunable dielectric thin film layer35is interposed between the shunt layer30and the signal layer25and electrically isolates the shunt layer30from the signal layer25.

The shunt layer30may comprise a first shunt-layer ground line45A and a second shunt-layer ground line45B parallel to the first shunt-layer ground line45A, and a plurality of parallel shunt lines50A,50B,50C that each electrically connects the first shunt-layer ground line45A and the second shunt-layer ground line45B. In illustrative embodiments, the plurality of parallel shunt lines comprise greater than 1 shunt line, such as from 2 to 100, from 2 to 50, from 2 to 25, from 2 to 10, from 2 to 8, from 2 to 6, from 3 to 6, or from 4 to 6 parallel shunt lines, for example. Therefore, it should be understood that though the embodiments ofFIGS. 1and2include only three parallel shunt lines50A,50B,50C, this is intended for illustrative purposes only and that the shunt layer30need only contain greater than one shunt line.

The coplanar waveguide (CPW) layer25may comprise a first CPW ground line40A, a second CPW ground line40B parallel to the first CPW ground line40A, and a CPW signal transmission line15interposed between the first CPW ground line40A and the second CPW ground line40B. The plurality of parallel shunt lines50A,50B,50C in the shunt layer30are not parallel to the CPW signal transmission line15in the signal layer25. In preferred embodiments each individual shunt line of the plurality of parallel shunt lines50A,50B,50C are skew to the CPW signal transmission line15and run in a direction perpendicular to the direction to the CPW signal transmission line15.

A plurality of varactor areas55A,55B,55C, equal in number to the plurality of parallel shunt lines50A,50B,50C, are defined in the CPW signal transmission line15. Each varactor area55A,55B,55C corresponds to an overlap of the CPW signal transmission line15with a respective parallel shunt line50A,50B,50C and each respective shunt line (for example50A) and its corresponding varactor area (55A) defines a capacitor. Each varactor area55A,55B,55C is the area affected by a capacitance between the CPW signal transmission line15and each of the parallel shunt lines50A,50B,50C. The effective capacitance of the VSS device10includes the sum of the capacitance from each varactor area (e.g., the three varactor areas55A,55B,55C in the embodiment ofFIGS. 1 and 2), and also includes the capacitance between the two CPW ground lines40A,40B and the two shunt-layer ground lines45A,45B.

The large capacitance of the varactor areas55A,55B,55C at zero bias may shunt an input signal to ground, thus isolating the output port of the CPW signal transmission line15and resulting in an OFF state of the VSS device10. When a DC bias voltage is applied to the VSS device10, capacitance between the CPW signal transmission line15and the varactor areas55A,55B,55C may be reduced to a minimum, allowing the transmission of a larger portion of the input signal from an input port60of the CPW signal transmission line15to the output port65of the CPW signal transmission line15, thus resulting in an ON state of the VSS device10.

In one exemplary embodiment, the substrate20may be a high resistivity silicon substrate. The thickness of the high resistivity silicon substrate may be from about 100 μm to about 1000 μm, for example about 500 μm. The dimensions of the VSS device10may be scaled to fit an appropriate application. In an exemplary embodiment, the VSS device10may have outer dimensions such as approximately 450 μm×500 μm. In another illustrative embodiment, to obtain a characteristic impedance of about 50Ω at zero-bias, the CPW signal transmission line15width may be about 50 μm. In the same embodiment, the two CPW ground lines40A,40B may have widths of about 150 μm, and the CPW signal transmission line15may be separated from the two CPW ground lines40A,40B by about 50 μm.

In another exemplary embodiment, the tunable dielectric thin film layer35may be a nanostructured barium strontium titanate (BST) dielectric thin film. Though the BST have any suitable ratio of barium to strontium that provides a high level of tunability, in one non-limiting preferred embodiment, the BST may be Ba0.6Sr0.4TiO3, for example. As used herein, the term “nanostructured” refers to a thin film made of a material having an average grain size of less than 100 nm, preferably less than 75 nm, for example from about 30 nm to about 75 nm. Thus, in one embodiment, the tunable dielectric thin film layer35may be a nanostructured BST dielectric thin film may have an average grain size less than 60 nm. In yet another exemplary embodiment, the nanostructured BST dielectric thin film may have an average grain size of about 30 nm to about 50 nm.

Referring toFIG. 1, a top-view of the VSS device10shows the first CPW ground line40A and the second CPW ground line40B, the CPW signal transmission line15and the plurality of parallel shunt lines50A,50B,50C. The overlap area of the CPW signal transmission line15and plurality of parallel shunt lines50A,50B,50C define the plurality of varactor areas55A,55B,55C. In some embodiment, an input port60and an output port65may be attached to the CPW signal transmission line15for connecting other components (not shown) or external circuitry that transmits an input signal through the VSS device10.

The perspective view ofFIG. 2further illustrates the layers of one embodiment of the VSS device10. In this embodiment, the VSS device10is provided on a substrate20. To form the VSS device10, the shunt layer30may be deposited on the substrate20, the tunable dielectric thin film layer35may be deposited on the shunt layer30, and the signal layer25may be deposited on the tunable dielectric thin film layer35. The CPW ground lines40A,40B are not parallel to the shunt-layer ground lines45A,45B. In preferred embodiments, the CPW ground lines40A,40B run in a direction that is perpendicular to the direction of the shunt-layer ground lines45A,45B. The overlap of the CPW signal transmission line15and the plurality of parallel shunt lines50A,50B,50C results in the varactor areas55A,55B,55C, from which it should be apparent that the number of varactor areas (i.e., three) is equal to the number of parallel shunt lines (i.e., three). The electrical symbols of capacitance and resistance inFIG. 2indicate areas where the total effective capacitance, consistent with the equivalent circuit diagram ofFIG. 3.

In one exemplary embodiment, the shunt layer30may comprise a metal stack. Standard positive photoresist lift-off photolithography can be used to form the metal stack. In an exemplary process for forming the metal stack, a Ti adhesion layer (e.g., 20 nm thick) may be deposited on the substrate20, followed by deposition of gold (e.g., 800 nm thick) and platinum (e.g., 55 nm thick) to form the shunt layer30. Any suitable metal-deposition system may be used such as, for example, an electron-beam evaporation system. In an alternative embodiment, lift-off photolithography may be used to deposit the shunt layer30. After the shunt layer30has been formed, the tunable dielectric thin film layer35may be deposited over the entire surface of the shunt layer30by a suitable deposition method for forming dielectric films, particularly nanostructured dielectric films, such as pulsed-laser deposition, for example. In one preferred embodiment, the tunable dielectric thin film layer35may be a nanostructured Ba0.6Sr0.4TiO3dielectric thin-film. In additional embodiments, the nanostructured BST dielectric thin film may be deposited by sputtering, chemical vapor deposition, sol-gel method, or by any other suitable deposition method.

The BST dielectric thin film can be processed at oxygen partial pressure below about 150 mTorr in a large area deposition system (for example, using a Neocera Pioneer system capable of deposition on 4-inch diameter wafers) which may result in an average grain-size of the nanostructured BST dielectric thin film of approximately 30 nm to approximately 100 nm. The nanostructured BST dielectric thin-films may be fabricated by any suitable method known in the art such as, for example, RF sputtering and metal organic chemical vapor deposition (MOCVD). After the nanostructured BST dielectric thin film deposition, the signal layer25may be defined and processed using a lift-off technique to complete the VSS device10fabrication. The signal layer25may be defined by e-beam deposition or sputtering, for example, or by any other suitable method. The signal layer25may also comprise a metal stack.

FIG. 3shows an electrical model for the VSS device10. With reference toFIG. 2, the VSS device10can be precisely modeled upon knowing several device parameters, specifically: (i) the varactor area55; (ii) CPW signal transmission line15parameters, such as the width of the CPW signal transmission line15, spacing between the CPW signal transmission line15and the two CPW ground lines40A,40B, and the length of the CPW signal transmission line15sections; (iii) parasitic inductance L and resistance R of the CPW signal transmission line15to ground70of the shunt layer30; and (iv) the dielectric properties of the tunable dielectric thin film layer35. The electrical properties of the varactor areas55A,55B,55C such as capacitance C(V) and resistance R(V) may be included in the model. The parasitic inductance L and resistance R can be precisely calculated through the use of the electrical model.

Referring toFIG. 4, in a top view of the VSS device10on the substrate20, the two shunt-layer ground lines45A,45B lie directly below the two CPW ground lines40A,40B. The input port60and the output port65are larger areas to allow for the connection of the VSS device10to other components or external circuitry (not shown). The input port60and the output port65are connected to the VSS device10through opposite ends of the CPW signal transmission line15.

The VSS device10exemplified inFIG. 2may be tailored to have a desired specific frequency range of operation, because the unbiased state (OFF) resonance frequency determines the maximum isolation of the VSS device10. Large-area varactors can result in high isolation, while at the same time increasing the insertion loss of the VSS device10. The larger area of the varactor can also result in a large zero-bias capacitance of the VSS device10. Ideally, the varactor capacitance can be reduced to the level of the line capacitance to obtain low insertion loss in the biased state (ON).

Compared to a VSS device having only a single shunt line, the VSS device10that contains a plurality of parallel shunt lines50A,50B,50C may advantageously have a larger effective capacitance at zero-bias, resulting in high isolation for the VSS device10. The high isolation characteristic of the VSS device10with a plurality of parallel shunt lines50A,50B,50C instead of only one shunt line may be desirable even at low GHz frequencies, because a larger difference between the biased state (ON) and unbiased state (OFF) may be expected. Having multiple smaller capacitors in parallel, as accomplished by the varactor areas55A,55B,55C, may improve the reliability of the VSS device10compared to a VSS having a single, large-area capacitor. Higher capacitance tunability is a characteristic of being able to apply higher bias voltage to the VSS device10compared to a VSS with the same equivalent capacitance. Although the shunt resistance R (FIG. 3) for the capacitors may effectively be lower, a positive aspect of this is the reduced parasitic inductance L (FIG. 3).

Experimental results have been obtained on several 5 μm×5 μm VSS devices with a varying number of parallel shunt lines50A,50b,50C. The results are shown inFIG. 4. The characteristic swept frequency S21, as used inFIGS. 5-7, is the ratio of transmitted power to input power.

The graph ofFIG. 5compares the isolation (S21at 0 V) of VSS devices having increasing numbers of parallel shunt lines. The number of parallel shunt lines (i.e., from 1 to 6) are shown on each plot inFIG. 5. Steady improvement in isolation has been demonstrated to occur with increasing the number of parallel shunt lines from 2 to 6, particularly as compared to a single shunt line. As the number of parallel shunt lines increases, the capacitance of the VSS devices also increases.FIG. 5also depicts increased isolation at higher frequencies.

The graph ofFIG. 6compares the insertion loss (S21at 0 V) of a single shunt line VSS and the plurality of parallel shunt lines50A,50B,50C of the VSS device10ofFIG. 4. In general, the graph is consistent with an increase of insertion loss with an increase in number of parallel shunt lines. The plots are shown at a 10 V DC bias voltage. The number of parallel shunt lines50are shown with each plot inFIG. 6.

The graph ofFIG. 7compares the capacitance to the DC bias voltage of the VSS device10ofFIG. 4. VSS devices having a plurality of parallel shunt lines are compared with a similar device having only a single shunt line. It is believed that the data ofFIG. 7indicate that large-capacitance varactors can indeed be realized without sacrificing the area of the devices.FIG. 7also shows excellent tunability for the plurality of parallel shunt lines50A,50B,50C, i.e. two or more parallel shunt lines, without the need for more real estate on a substrate, in general because the overall capacitance of the VSS device10is higher with multiple shunt lines, compared to a VSS with only a single thin shunt line. Some of the multi-shunt VSS devices were able to support DC bias voltages as high as 16 V.FIG. 7illustrates that the multiple-shunt VSS device does not exhibit degradations in radio frequency (RF) performance over single-shunt line VSS devices.

The VSS device10ofFIG. 4may provide increased isolation at the expense of increased insertion loss. Although the insertion loss is higher for switching applications, the potential to implement large varactors using the VSS device10is attractive, as it does not sacrifice area. Also, the leakage currents in the VSS device10were comparable to the single shunt line VSS.

From the foregoing disclosure and its specific embodiments, it will be apparent that modifications and variations are possible without departing from the scope of the disclosure defined in the appended claims. It should be noted that, although some aspects of the present disclosure are identified herein as preferred or particularly advantageous, it is contemplated that the present disclosure is not meant to be limited to these preferred aspects of the disclosure.