Interposer and method of manufacturing the same

A method of manufacturing an interposer is provided, including forming a plurality of first openings on one surface side of a substrate, forming a first metal layer in the first openings, forming on the other surface side of the substrate a plurality of second openings that are in communication with the first openings, forming a second metal layer in the second openings, and electrically connecting the first metal layer to the second metal layer, so as to form conductive through holes. The conductive through holes are formed stage by stage, such that the fabrication time in forming the metal layers is reduced, and a metal material will not be accumulated too thick on a surface of the substrate. Therefore, the metal material has a smoother surface, and no overburden will be formed around end surfaces of the through holes. An interposer is also provided.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application claims under 35 U.S.C. §119(a) the benefit of Taiwanese Application No. 102121484, filed Jun. 18, 2013, the entire contents of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to interposers, and, more particularly, to an interposer having conductive through holes and a method of manufacturing the interposer.

2. Description of Related Art

In a flip-chip packaging process, since the coefficients of thermal expansion (CTE) of a semiconductor chip and a package substrate differ from each other significantly, bumps around the semiconductor chip cannot be well bonded to corresponding contacts disposed on the package substrate, and the semiconductor chip is thus easily peeling from the package substrate. With the rapid increase of integrity of an integrated circuit, the stress generated by and the warpage occurred on the semiconductor chip and the package substrate are getting worse due to the CTE mismatch of the semiconductor chip and the package substrate. As a result, the reliability of the semiconductor chip and the package substrate becomes worse, and a reliability test often fails.

In order to solve the above problems, a process in which a semiconductor substrate acts as an interposer is brought to the market. In the process, a silicon interposer is disposed between a package substrate and a semiconductor chip. Since the silicon interposer and the semiconductor chip are made of similar materials, the problem occurred due to CTE mismatch is avoided.

FIGS. 1A to 1Dare cross sectional views illustrating a method of manufacturing an interposer1according to the prior art.

As shown inFIG. 1A, an insulating layer11and a plurality of through-silicon vias (TSV)14are formed in a silicon substrate10. As shown in FIG.1A′, the through-silicon vias14are formed by forming through holes100, forming the insulating layer11and a conductive layer12in the through holes100and on the silicon substrate10, electroplating the conductive layer12with a copper layer140, and removing the copper layer140on a surface of the silicon substrate10, the conductive layer12and the insulating layer11after the through-silicon vias14are formed in the through holes100.

As shown inFIG. 1B, a first redistribution layer (RDL)13is formed on an upper surface side10aof the silicon substrate10and electrically connected to the through-silicon vias14, for a semiconductor chip (not shown) or a package substrate (not shown) to be mounted thereon.

As shown inFIG. 1C, a lower surface side10bof the silicon substrate10is thinned.

As shown inFIG. 1D, a second redistribution layer (RDL)16is formed on the lower surface side10bof the silicon substrate10and electrically connected to the through-silicon vias14, for a semiconductor chip (not shown) or a package substrate (not shown) to be mounted thereon.

In the method of manufacturing the interposer1according to the prior art, the silicon substrate10is very thick, and the through holes100thus have a great depth h, e.g., 100 to 500 um, and a radius of 100 to 200 um. Therefore, an electroplating process has to be performed in the through holes100for a long time, in order for the copper layer140to be formed on the hole walls and bottom portions of the through holes100. Because the electroplating process is performed for a long time, the copper layer140formed on a surface of the silicon substrate10is very thick, and has a rough surface. As a result, an overburden141is likely formed around end surfaces of the through holes, as shown in FIG.1A″.

According to the prior art, a chemical mechanical polishing (CMP) process is used to remove the copper layer140on the surface of the silicon substrate10. However, it is unlikely to remove the copper layer140and the overburden141completely without the surface of the silicon substrate10penetrated, if the copper layer140is very thick. Hence, the prior art suffers from a long process time, a high cost of chemical fluid, and a complicated process.

However, how to solve the problems of the prior art is becoming an urgent issue in the art.

SUMMARY OF THE INVENTION

In view of the above-mentioned problems of the prior art, the present invention discloses an interposer, comprising: a substrate having opposing first surface side and second surface side, the substrate having a plurality of first openings on the first surface side and a plurality of second openings on the second surface side, the first openings being in communication with the second openings to form through holes; a first metal layer formed in the first openings; and a second metal layer formed in the second openings and electrically connected to the first metal layer, such that conductive through holes constituted by the first metal layer and the second metal layer are formed in the through holes.

The present invention further discloses a method of manufacturing an interposer, comprising: providing a substrate having opposing first surface side and second surface side; forming a plurality of first openings on the first surface side of the substrate; forming a first metal layer in the first openings; forming a plurality of second openings on the second surface side of the substrate, the first openings being in communication with the second openings to form through holes; and forming a second metal layer in the second openings and electrically connecting the second metal layer to the first metal layer, such that conductive through holes constituted by the first metal layer and the second metal layer are formed in the through holes.

In an embodiment, the substrate is at least made of silicon or a silicon-containing substrate (silicon substrate or a glass substrate).

In an embodiment, the method further comprises forming a first redistribution layer on the first surface side of the substrate and electrically connecting the conductive through holes to the first redistribution layer.

In an embodiment, the method further comprises forming a second redistribution layer on the second surface side of the substrate and electrically connecting the conductive through holes to the second redistribution layer.

In an embodiment, the method further comprises, prior to forming a first metal layer, forming an insulating layer on hole walls of the first openings, such that the first metal layer is formed on the insulating layer. In an embodiment, the method further comprises, prior to forming a first metal layer, forming an etch-stop layer on the insulating layer, such that the etch-stop layer is formed between the insulating layer and the first metal layer. In an embodiment, the method further comprises, prior to forming a second metal, removing the etch-stop layer in the through holes, such that the first metal layer is exposed from the through holes.

In an embodiment, the method further comprises, prior to forming a second metal layer, forming an insulating layer on hole walls of the second openings, such that the second metal layer is formed on the insulating layer.

In an embodiment, the method further comprises, prior to forming a first metal layer, forming conductive bumps in the first openings, such that the first metal layer is formed on the conductive bumps and is electrically to the second metal layer via the conductive bumps.

According to an interposer and a method of manufacturing the interposer according to the present invention, the conductive through holes are formed stage by stage (i.e., first forming the first openings and the first metal layer, and then forming the second openings and the second metal layer), in order to reduce the depth of the through holes and the time for forming the metal layers. Compared to the prior art, a thick metal material will not be accumulated on the first surface side and the second surface side of the substrate, and the metal material has a smoother surface. Further, an overburden will not formed around end surfaces of the through holes. Therefore, the CMP process is omitted, process time is reduced, the cost of chemical fluid is decreased, and the process is simplified.

DETAILED DESCRIPTION OF THE INVENTION

The following illustrative embodiments are provided to illustrate the disclosure of the present invention, these and other advantages and effects can be apparently understood by those in the art after reading the disclosure of this specification. The present invention can also be performed or applied by other different embodiments. The details of the specification may be on the basis of different points and applications, and numerous modifications and variations can be devised without departing from the spirit of the present invention.

FIGS. 2A to 2Eare cross sectional views illustrating a method of manufacturing an interposer2according to the present invention.

As shown inFIG. 2A, a substrate20having opposing first surface side20aand second surface side20bis provided, a plurality of first openings200aare formed on the first surface side20aof the substrate20, and an insulating layer21is formed on hole walls of the first openings200aand the first surface side20aof the substrate20. An etch-stop layer22is then formed on the insulating layer21.

In an embodiment, the substrate20is at least made of silicon or a silicon-containing substrate (e.g., a silicon substrate or a glass substrate), and the insulating layer21is made of thermal oxide and acts as a stress buffer layer.

In an embodiment, the etch-stop layer22is made of silicon nitride, for an etch fluid to be highly selective etching between a silicon material and the silicon nitride.

In an embodiment, the insulating layer21is formed by an annealed chemical vapor deposition (CVD) oxide material.

In an embodiment, if the substrate20is a glass substrate, the insulating layer21is omitted.

As shown inFIG. 2B, a first redistribution layer23is formed on the etch-stop layer22on the first surface side20aof the substrate20, and a first metal layer24ais formed on the etch-stop layer22in the first openings200a.

In an embodiment, the first redistribution layer23has at least one dielectric layer230, a circuit layer231formed on the dielectric layer230, and conductive blind vias232disposed in the dielectric layer230and electrically connected to the circuit layer231.

In an embodiment, the first metal layer24aand the circuit layer231are made of copper, and the dielectric layer230is made of polyimide (PI), a dry film, epoxy resin or a packaging material.

In an embodiment, the bottommost one of the dielectric layer230is a protection material copper, to prevent foreign matters from entering the first openings200aand affecting the electrical quality of the first metal layer24a.

In an embodiment, before the first metal layer24aand the bottommost circuit layer231of the first redistribution layer23are formed a barrier layer (not shown) is formed on the etch-stop layer22, and a conductive layer (not shown) is then formed on the barrier layer by a physical vapor deposition (PVD) process.

In an embodiment, the barrier layer is made of Ti, TiN, Ta or TaN, which improve the bondage of the metal material.

In an embodiment, the conductive layer is made of copper, and is used as a seed layer for electroplating the first metal layer24aand the circuit layer231.

In the electroplating process according to the present invention, since the depth of the first openings200ais smaller than that of the through holes of the prior art less fabrication time is needed to electroplate the first metal layer24a. As a result, the metal layer formed on the substrate20is not very thick and has a smoother surface, and therefore no overburden is formed.

As shown inFIG. 2C, a plurality of second openings200bare formed on the second surface side20bof the substrate20, and the first openings200aare in communication with the second openings200bcorrespondingly to form a plurality of through holes200.

In an embodiment, the second openings200bare formed by an etch process.

As shown inFIG. 2D, the etch-stop layer22in the through holes200(i.e., the etch-stop layer22in the second openings200b) is removed, to expose the first metal layer24afrom the through holes200. Another insulating layer25is then formed on hole walls of the second openings200band the second surface side20bof the substrate20.

In an embodiment, the insulating layer25is made of thermal oxide or annealed CVD oxide material, and acts as a stress buffer layer.

In an embodiment, if the substrate20is a glass substrate, the insulating layer25is omitted.

In an embodiment, the depth of the through holes200is about 100 to 500 um, and the depths of the first openings200aand the second openings200bare less than the depth of the through holes200.

As shown inFIG. 2E, a second redistribution layer26is formed on the insulating layer25on the second surface side20bof the substrate20, a second metal layer24bis formed on the insulating layer25in the second openings200b, and the first metal layer24ais in contact with and electrically connected to the second metal layer24b, such that a metal structure in the through holes200forms conductive through holes24and the conductive through holes24are electrically connected to the first redistribution layer23and the second redistribution layer26.

In an embodiment, the second redistribution layer26has at least one dielectric layer260formed on the circuit layer261on the dielectric layer260and in the dielectric layer260and electrically connected to the conductive vias262of the circuit layer261.

In an embodiment, the first metal layer24aand the second metal layer24bare made of the same or different material, and an interface S is formed between the first metal layer24aand the second metal layer24bsince the first metal layer24aand the second metal layer24bare formed by different process steps.

In an embodiment, the circuit layer261is made of copper, the dielectric layer260is made of polyimide (PI), a dry film, epoxy resin or a packaging material, and the bottommost one of the dielectric layer260is a protection copper material, in order to prevent foreign matters from entering the second openings200band affecting the electrical quality of the second metal layer24b.

In an embodiment, before the bottommost circuit layer261of the second redistribution layer26and the second metal layer24bare formed, a barrier layer (not shown) can be formed on the insulating layer25, and a conductive layer (not shown) can then be formed on the barrier layer by a PVD process.

In an embodiment, the barrier layer is made of Ti, TiN, Ta or TaN, to improve the bondage of a metal material.

In an embodiment, the conductive layer is made of copper, and acts as a seed layer for electroplating the second metal layer24band the circuit layer261.

In a method of manufacturing an interposer according to the present invention, the first openings200aand the second openings200bare formed subsequently on the first surface side20aand the second surface side20bof the substrate20, respectively, and have opening depths reduced significantly. A electroplating process is performed in the first openings200aand the second openings200bsubsequently. As a result, the first metal layer24ais formed to cover the hole walls and the bottom portion of the first openings200a, and the second metal layer24bis formed to cover the hole walls and the bottom portion of the second openings200b. Therefore, it does not take long time to perform the electroplating process.

Compared with the prior art, the metal material on the first surface side20aand the second surface side20bof the substrate20is thinner and has a smoother surface, and no overburden will be formed around end surfaces of the through holes200. Therefore, the CMP process is omitted, the process time is reduced, the cost of chemical fluid is decreased, and the process is simplified.

FIGS. 3A and 3Bare cross sectional views illustrating another method of manufacturing an interposer3according to the present invention.

As shown inFIG. 3A, an insulating layer21is formed on the substrate20shown inFIG. 2Afirst, and then conductive bumps37are disposed in the first openings200a.

As shown inFIG. 3B, subsequent to the process steps shown inFIGs. from 2B to 2E, the first metal layer24ais formed on the conductive bumps37, the conductive bumps37are exposed from the through holes200when the second openings200bare formed, and the first metal layer24ais electrically connected to the second metal layer24bvia the conductive bumps37.

In an embodiment, the conductive through holes34comprise the first metal layer24a, the conductive bumps37and the second metal layer24b.

In an embodiment, the first redistribution layer33has a dielectric layer330and a circuit layer331formed on the dielectric layer330, and the second redistribution layer36has a dielectric layer360and a circuit layer361formed on the dielectric layer360.

In an embodiment, since the conductive bumps37are disposed in the through holes200, the connection strength between the first metal layer24aand the second metal layer24bis enhanced, which also acts as an etch-stop layer.

In an embodiment, the bottommost circuit layer231,331of the first redistribution layer23,33and the first metal layer24acan be formed simultaneously or formed individually. Similarly, the bottommost circuit layer261,361of the second redistribution layer26,36and the second metal layer24bcan be formed simultaneously or formed individually.

In an embodiment, under bump metallurgy (UBM)27can be disposed on the outermost circuit layer231,331of the first redistribution layer23,33and the outermost circuit layer261,361of the second redistribution layer26,36on demands.

The present invention also provides an interposer2,3, comprising a substrate20, a first metal layer24aand a second metal layer24b.

The substrate20comprises opposing first surface side20aand second surface side20b. A plurality of first openings200aare formed on the first surface side20aof the substrate20. A plurality of second openings200bare formed on the second surface side20bof the substrate20. The first openings200aare in communication with the second openings200bcorrespondingly to form a plurality of through holes200. In an embodiment, the substrate20is at least made of silicon or a silicon-containing substrate (e.g., a silicon substrate or a glass substrate).

The first metal layer24ais formed in the first openings200a.

The second metal layer24bis formed in the second openings200b. The first metal layer24ais electrically connected to the second metal layer24b. Conductive through holes24,34are formed in the through holes200.

In an embodiment, the interposer2,3further comprises a first redistribution layer23,33formed on the first surface side20aof the substrate20and electrically connected to the conductive through holes24,34.

In an embodiment, the interposer2,3further comprises a second redistribution layer26,36formed on the second surface side20bof the substrate20and electrically connected to the conductive through holes24,34.

In an embodiment, the interposer2,3further comprises an insulating layer21,25formed between the first surface side20aof the substrate20and the first redistribution layer23,33, between the first metal layer24aand the hole walls of the first openings200a, between the second surface side20bof the substrate20and the second redistribution layer26,36, and between the second metal layer24band the hole walls of the second openings200b. The interposer2comprises an etch-stop layer22formed between the insulating layer21and the first metal layer24aand between the insulating layer21and the first redistribution layer23.

In an embodiment, the interposer3further comprises a plurality of conductive bumps37disposed in the through holes200and disposed between the first metal layer24aand the second metal layer24b. The first metal layer24ais electrically connected to the second metal layer24bvia the conductive bumps37.

According to an interposer and a method of manufacturing the interposer according to the present invention, the conductive through holes are formed stage by stage, in order to reduce the depth of the through holes and the time for forming the metal layers. Compared to the prior art, a metal material will not be accumulated too thick on the first surface side and the second surface side of the substrate, and the metal material has a smoother surface. Further, an overburden will not formed around end surfaces of the through holes. Therefore, the CMP process is omitted, process time is reduced, the cost of chemical fluid is decreased, and the process is simplified.

The foregoing descriptions of the detailed embodiments are only illustrated to disclose the features and functions of the present invention and not restrictive of the scope of the present invention. It should be understood to those in the art that all modifications and variations according to the spirit and principle in the disclosure of the present invention should fall within the scope of the appended claims.