Semiconductor device having stacked body on substrate via joining metal and method for manufacturing the same

According to one embodiment, a semiconductor device includes a substrate and a stacked body on the substrate via a joining metal layer. The stacked body includes a device portion and a peripheral portion. The device portion includes from a bottommost layer to a topmost layer included in the stacked body. The peripheral portion surrounding and provided around the device portion; the peripheral portion is a portion of the bottommost layer to the topmost layer included in the stacked body and includes a portion of a semiconductor layer in contact with the joining metal layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2010-165583, filed on Jul. 23, 2010; the entire contents of which are incorporated herein by reference.

FIELD

Embodiments of the invention relate generally to a semiconductor device and method for manufacturing the same.

BACKGROUND

Many semiconductor devices are fabricated using semiconductor layers that are epitaxially grown on a substrate. Compared to bulk crystals of semiconductors, semiconductor layers that are epitaxially grown have fewer defects, are of higher quality, and therefore can improve the characteristics of the semiconductor devices.

However, substrates that are used for the epitaxial growth principally perform a role of mechanically supporting thin film semiconductor layers and rarely proactively function to improve the characteristics of semiconductor devices. In some cases, such substrates are a factor that inhibits the realization of high performance in semiconductor devices. For example, in light emitting devices formed by using InGaAlP semiconductors that emit light in the green to red wavelength range, GaAs substrates that have similar lattice constants are used as growth substrates. However, there is a problem in that GaAs crystals absorb green to red light, thus causing luminous intensity to decrease.

Hence, a technique is used wherein a high-quality InGaAlP semiconductor is grown on the GaAs substrate, and thereafter a stacked body having a plurality of semiconductor layers including a light emitting layer is transferred to another substrate. For example, the stacked body can be adhered to a support substrate formed from silicon or the like via a joining metal layer that reflects light emitted from the light emitting layer. Thereby, the light absorption by the substrate can be eliminated and the luminous intensity of the light emitting device can be increased.

However, in a cutting process in which the support substrate provided with the joining metal layer is diced, curls and other defects are prone to be formed on an edge of the cut-out chip, which leads to a decline in production yield. Therefore, there is a need for a semiconductor device and method for manufacturing the same wherein the forming of curls and other defects can be suppressed when cutting the chips from a support substrate that has a joining metal layer provided on a surface thereof.

DETAILED DESCRIPTION

In general, according to one embodiment, a semiconductor device includes a substrate and a stacked body on the substrate via a joining metal layer. The stacked body includes a device portion and a peripheral portion. The device portion includes from a bottommost layer to a topmost layer included in the stacked body. The peripheral portion surrounding and provided around the device portion; the peripheral portion is a portion of the bottommost layer to the topmost layer included in the stacked body and includes a portion of a semiconductor layer in contact with the joining metal layer.

Embodiments of the invention will now be described while referring to the drawings. Note that in the following embodiments, the same numerals are applied to constituents that have already appeared in the drawings and, and repetitious detailed descriptions of such constituents are appropriately omitted.

FIGS. 1A and 1Bare schematic views illustrating a semiconductor device100according to an embodiment.FIG. 1Aschematically illustrates a structure of a cross-section taken across the line1a-1aillustrated inFIG. 1B.FIG. 1Bis a planar photograph illustrating a chip surface of the semiconductor device100.

The semiconductor device100is, for example, a light emitting diode and has a stacked body25adhered on a substrate (support substrate27) via a joining metal layer40.

As illustrated inFIG. 1A, the semiconductor device100includes a device portion50provided in the stacked body25and a peripheral portion60provided so as to surround the device portion50.

The device portion50includes from a p-type contact layer24that is a bottommost layer to an n-type current diffusion layer16that is a topmost layer of the stacked body25. Additionally, the device portion50includes a light emitting layer20that emits luminescent light. The joining metal layer40contains a metal that reflects the light that the light emitting layer20emits. The peripheral portion60is a portion of a plurality of layers included from the bottommost layer to the topmost layer of the stacked body25, and includes at least a portion of the p-type contact layer24that is a semiconductor layer in contact with the joining metal layer40

Hereinafter, the semiconductor device100is described in detail while referring toFIG. 1A.

In the semiconductor device100, the stacked body25having the light emitting layer20and the support substrate27are joined via the joining metal layer40. The joining metal layer40includes a first joining metal layer26provided on a first major surface25aof the stacked body25and a second joining metal layer28provided on the support substrate27. The first joining metal layer26and the second joining metal layer28are joined at a joint interface32. The second joining metal layer28is connected to a p-side electrode29via the conductive support substrate27.

A second major surface25bof the stacked body25is, for example, connected to an n-side electrode34via an n-type contact layer14. Current is fed into the light emitting layer20by the current flowing from the p-side electrode29to the n-side electrode34, and luminescent light having a wavelength corresponding to a band gap energy of the light emitting layer20is emitted.

InFIG. 1A, the stacked body25has, from the n-side electrode34, the n-type current diffusion layer16, an n-type clad layer18, the light emitting layer20, a p-type clad layer22, and the p-type contact layer24. An InGaAlP semiconductor material can be used, for example, for the stacked body25.

A silicon wafer can be used, for example, for the support substrate27.

Note that “InGaAlP semiconductor” refers to a semiconductor expressed by the composition formula Inx(GayAl1-y)1-xP (where 0≦x≦1 and 0≦y≦1), and includes semiconductors that have been doped with p-type impurities or n-type impurities. In this case, the wavelength of the luminescent light can be selected from a range of from green to red by changing the composition of the InGaAlP contained in the light emitting layer20.

Furthermore, a nitride semiconductor expressed by the composition formula BxInyGazAl1-x-y-zN (where 0≦x≦1, 0≦y≦1, 0≦z≦1, and x+y+z≦1) can be used for the stacked body25. In this case, the wavelength of the luminescent light can be selected from a range of from purple to green.

Next, a method for manufacturing the semiconductor device100will be described while referring toFIGS. 2 to 4.

FIG. 2Ais a schematic cross-sectional view illustrating a state in which the stacked body25and the first joining metal layer26have been formed on a GaAs substrate30.

For example, a GaAs buffer layer (not shown) and an n-type GaAs contact layer14(impurity concentration: 1×1018cm−3; thickness: 0.1 μm) are formed on the GaAs substrate30.

These semiconductor layers can, for example, be epitaxially grown by using Metal Organic Chemical Vapor Deposition (MOCVD) or the like.

The light emitting layer20can include a p-type Multi Quantum Well (MQW) structure in which an impurity concentration is about 1×1017cm−3. The MQW can be formed by alternately stacking In0.5(Ga0.94Al0.6)0.5P having a width of about 10 nm that is a well layer and In0.5(Ga0.94Al0.6)0.5P having a width of about 20 nm that is a barrier layer.

In this case, red light with a peak wavelength of roughly 624 nm and a dominant wavelength of roughly 615 nm can be obtained as the luminescent light.

Next, as illustrated inFIG. 2B, the stacked body25is joined to the support substrate27(impurity concentration: 1×1019cm−3; thickness: 200 μm) formed from a p-type silicon having, for example, a face orientation of (100), via the first joining metal layer26and the second joining metal layer28.

The second joining metal layer28formed from Ti (thickness: 0.1 μm), Pt (thickness: 0.12 μm), and Au (thickness: 0.2 μm) is formed by a vacuum evaporation method or the like on a first face of the support substrate27.

Thereafter, as illustrated inFIG. 2B, the first joining metal layer26and the second joining metal layer28are aligned, and the stacked body25and the support substrate27are joined, for example, by heating at about 300° C. while applying pressure in a vacuum.

Next, as illustrated inFIG. 3A, the GaAs substrate30is removed, for example, by a wet etching process. Thereafter, for example, by sintering the support substrate27and the stacked body25at 400° C., adhesive strength of the interface32of the Au layers between the first joining metal layer26and the second joining metal layer28can be increased.

The joining metal layer40is formed by aligning the first joining metal layer26and the second joining metal layer28and contact bonding each Au layer thereof. The Au layer included in the joining metal layer40is a metal that reflects the light emitted from the light emitting layer20upwards, thereby increasing luminous intensity.

Thereafter, for example, the n-type contact layer14is etched using the n-side electrode34as a mask.

Next, as illustrated inFIG. 4A, a resist mask41for forming the peripheral portion60is formed on a portion of the surface of the stacked body25that will become the device portion50.

Thereafter, as illustrated inFIG. 4B, a wet etching process, for example, is used to etch a portion around the device portion50that will become the peripheral portion60. Here, etching can be performed so that the p-type contact layer24in contact with the joining metal layer40remains.

Specifically, the n-type current diffusion layer16, the n-type clad layer18, the light emitting layer20, and the p-type clad layer22are subsequently removed by etching. Here, an etching time is adjusted so that the p-type contact layer24will be left on the joining metal layer40.

For example, etching is performed for from 10 to 60 minutes using a compound liquid of HCl+H2O2+H2O with a solution temperature adjusted to be in a range of from −30 to 30° C.

Furthermore, when etching the p-type clad layer22formed from InAlP, an etchant with a faster etching speed with respect to

InAlP than to p-type Ga0.5Al0.5As can be used. Thereby, leaving the p-type contact layer24formed from the p-type Ga0.5Al0.5As on the joining metal layer40will be facilitated. A layer having a uniform thickness can be left as a protective layer by using selective etching or Reactive Ion Etching (RIE).

The p-type contact layer24left on the joining metal layer40may be etched, for example, to a thickness less than the initial thickness of 0.4 μm. Furthermore, the semiconductor layer left on the joining metal layer40is not limited to the p-type contact layer24, and, for example, the p-type clad layer22may be left in addition to the p-type contact layer24. By leaving a plurality of layers as desired in this way, the plurality of layers can be designed according to the dicing conditions and/or the joining metal layer to function as a protective layer.

Next, the p-side electrode29is formed on a reverse side of the support substrate27by subsequently stacking Ti (thickness: 0.1 μm), Pt (thickness: 0.12 μm), and Au (thickness: 0.2 μm).

Thereafter, individual chips including the device portion50are separated by cutting the peripheral portion60using, for example, a dicing saw.

FIGS. 5A and 5Bare, respectively, a schematic view and an SEM image illustrating a cross-section of the semiconductor device100.FIG. 5Ais a schematic cross-sectional view centered on the peripheral portion60.FIG. 5Bis an SEM image showing an edge A of the semiconductor device100that is separated into individual chips.

As illustrated inFIG. 5A, a cutting portion C in a center of the peripheral portion60is cut by using, for example, a dicing saw.

The dicing parameters can be set to, for example, a dicing blade feed rate of from 5 to 20 mm/sec and to a revolution rate of from 25,000 to 50,000 RPM. A supply rate of coolant liquid to the dicing blade can be set to from 0.5 to 1.0 liters/min.

FIG. 5Bis an SEM image of the edge A illustrated inFIG. 5A. Cut surfaces of the support substrate27, the joining metal layer40, and the p-type contact layer24left on the joining metal layer40are shown.

On the other hand,FIGS. 6A and 6Bare, respectively, a schematic view and an SEM image illustrating a cross-section of a semiconductor device150according to a comparative example.FIG. 6Ais a schematic cross-sectional view centered on the peripheral portion60.FIG. 6Bis an SEM image showing an edge B of the semiconductor device150that is separated into individual chips.

As illustrated inFIG. 6A, in the semiconductor device150, an entirety of the p-type contact layer24is removed in the peripheral portion60by etching and the surface of the joining metal layer40is exposed.

As shown inFIG. 6B, cracking has occurred in a surface of the support substrate27at the chip edge B of the semiconductor device150that has been cut using a dicing saw. Furthermore, it is clear that the joining metal layer40has curled and so-called Au curls have formed.

In contrast, in the chip edge A shown inFIG. 5B, it is clear that curls such as those seen inFIG. 6Bare not present and that the chip has been cut into a satisfactory shape.

Specifically, by leaving a semiconductor layer (the p-type contact layer24) on the joining metal layer40, it is possible to suppress the formation of defects such as curls and the like when dicing processing, and thereby the quality of the chips can be improved. Furthermore, because the thickness of the protective layer formed from the semiconductor layer is uniform, shape reproducibility after dicing can be improved.

FIGS. 7A and 7Bare schematic cross-sectional views illustrating a manufacturing process of a semiconductor device200according to a variation of this embodiment.

As illustrated inFIG. 7A, after forming the peripheral portion60while leaving the p-type contact layer24on the joining metal layer40, a resist mask42covering the device portion50is formed.

Thereafter, individual chips including the device portion50are separated by cutting the peripheral portion60using, for example, a dicing saw.

Then, using the resist mask42as an etching mask, the p-type contact layer24that was left on the surface of the peripheral portion60is removed. A wet etching process can be used, for example, for the etching of the p-type contact layer24.

Specifically, after the support substrate27is cut on a dicing sheet (not shown) and separated into individual chips, the p-type contact layer24of the chips adhered to the dicing sheet can be etched by immersing the dicing sheet in an etchant.

Thereby, as shown inFIG. 7B, the surface of the joining metal layer40can be exposed while leaving a p-type contact layer24aon a portion of the peripheral portion60.

On the other hand, because the device portion50is protected by the resist mask42, the light emitting layer20, the n-side electrode34, and the like will not be eroded by the etchant, and therefore, the characteristics of the semiconductor device200will not deteriorate.

The resist mask42can be removed by, for example, wet processing or oxygen ashing.

In the semiconductor device200according to this variation, the surface of the joining metal layer40is exposed at the chip edge. Thereby, for example, adhesion between the chip and a resin when resin sealing the chip can be improved, and the formation of defects such as voids in the chip edge can be prevented.

In the example illustrated inFIG. 7B, the p-type contact layer24ais left on a portion of the peripheral portion60, but this embodiment is not limited thereto. For example, substantially all of the p-type contact layer24amay be etched and removed from the peripheral portion60. Moreover, cases where the p-type contact layer24ais over-etched or where the p-type contact layer24ais etched and removed up to a portion of the device portion50are included within the range of this embodiment.

In the embodiment described above, examples of semiconductor light emitting devices were given for the purpose of explanation, but it is possible to apply this embodiment to, for example, electronic devices such as Field Effect Transistors (FET) formed using GaN nitride semiconductors.

Note that, in this specification, “nitride semiconductor” includes BxInyAlzGa(1-x-y-z)N (where 0≦x≦1, 0≦y≦1, 0≦z≦1, and 0≦x+y+z≦1) group III-V compound semiconductors, and furthermore includes mixed crystals containing phosphorus (P) and/or arsenic (As) in addition to nitrogen (N) as group V elements.