Method for fabricating a semiconductor device with self-aligned contact

A method for fabricating a semiconductor device includes forming electrode patterns over a substrate, wherein the electrode patterns include a hard mask, forming a passivation layer on the electrode patterns, forming an insulation layer on the passivation layer, filling a space between the electrode patterns, planarizing the insulation layer until shoulder portions of the hard mask are planarized, forming a mask pattern on a resultant structure, and etching a portion of the insulation layer to form a contact hole.

RELATED APPLICATIONS

This application is based upon and claims the benefit of priority to Korean Application numbers 10-2006-0018333 and 10-2006-0124739, filed on Feb. 24, 2006, and Dec. 8, 2006, respectively, the entire contents of which are incorporated herein by reference.

BACKGROUND

The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device with a self-aligned contact (SAC).

In conventional semiconductor device fabrication processes, various attempts have been made to overcome limitations associated with mask overlay and patterning. A SAC method is one example of such attempts. According to the SAC method, an upper part of an electrode (e.g., gate electrode) is protected with a nitride layer using a selectivity ratio between nitride and oxide, and an oxide-based inter-layer insulation layer is etched to form a contact.

In consideration of SAC process conditions, if sufficient amounts of polymers are produced over a nitride layer formed over an upper part of an electrode patterned in a line type, a profile of the nitride layer usually becomes normal after SAC etching. However, the upper part of the electrode pattern is generally rounded. Thus, an amount of polymer deposited over the upper edge portions (hereinafter “shoulder portions”) of the electrode pattern is small, and nitride-based spacers formed on sidewalls of the electrode pattern physically conjoin with a hard mask of the electrode pattern. As a result, during SAC etching, the nitride layer formed over the upper part of the electrode pattern is damaged, resulting in a convex-concave profile.

FIGS. 1A to 1Care sectional views to illustrate a conventional SAC process.FIGS. 2A to 2Care transmission electron microscopic (TEM) images of semiconductor structures obtained by the conventional SAC process. Referring toFIG. 1A, a gate insulation layer12is formed over a substrate11, and a plurality of gate patterns13are formed thereon. Each of gate patterns13includes a gate electrode13A and a gate hard mask13B, which are sequentially formed in a stack structure.

A passivation layer14is formed over the above resultant structure. Passivation layer14protects gate patterns13. An inter-layer insulation layer15is formed over passivation layer14, filling the space between gate patterns13. Inter-layer insulation layer15is formed of an oxide-based material. A contact mask pattern16is formed over a portion of inter-layer insulation layer15where a SAC region is to be formed. Contact mask pattern16is usually formed of a nitride-based material, and has an opening wider than the space between gate patterns13.

Referring toFIGS. 1B and 1C, the SAC designated region of inter-layer insulation layer15is etched using contact mask pattern16as an etch mask to form a SAC hole17. Reference numeral15A illustrated inFIG. 1Brepresents a first patterned inter-layer insulation layer. Reference numerals12A,14A, and15B, illustrated inFIG. 1C, respectively represent a patterned gate insulation layer, a patterned passivation layer, and a second patterned inter-layer insulation layer during the formation of SAC hole17. Since shoulder portions of gate patterns13are rounded, polymers are less likely to be deposited over the shoulder portions during etching of inter-layer insulation layer15(i.e., SAC etching), and thus, gate hard masks13B are more likely to be damaged. This damage is illustrated inFIG. 1Cand labeled as “P.” If gate hard masks13B are severely damaged, a short failure may occur between each of gate electrodes13A and a conductive material to fill SAC hole17. Reference numerals13C and13X represents damaged gate hard masks and gate patterns during the SAC etching, respectively.

FIG. 2Aillustrates a TEM image of a semiconductor structure obtained after sequential process steps illustrated inFIG. 1A. Gate patterns13have rounded upper parts.FIGS. 2B and 2Cillustrate TEM images of semiconductor structures obtained after sequential process steps illustrated inFIGS. 1B and 1C, respectively.

Although SAC etching can be performed under the condition that produces lots of polymers to reduce damage to a gate hard mask, an inter-layer insulation layer between gate patterns may not be removed to a sufficient level. Accordingly, contact regions may not be opened properly.

BRIEF SUMMARY

Specific embodiments consistent with the present invention are directed to provide a method for fabricating a semiconductor device with a self-aligned contact, wherein the semiconductor device can prevent a short failure and a contact hole opening failure by reducing damage to a hard mask of an electrode.

In accordance with one aspect consistent with the present invention, there is provided a method for fabricating a semiconductor device. The method includes forming electrode patterns over a substrate, wherein the electrode patterns include a hard mask, forming a passivation layer on the electrode patterns, forming an insulation layer on the passivation layer, filling a space between the electrode patterns, planarizing the insulation layer until shoulder portions of the hard mask are planarized, forming a mask pattern on a resultant structure, and etching a portion of the insulation layer to form a contact hole.

In accordance with another aspect consistent with the present invention, there is provided a method for fabricating a semiconductor device. The method includes forming electrode patterns over a substrate, wherein the electrode patterns include a hard mask, forming a passivation layer on the electrode patterns, forming an insulation layer on the passivation layer, filling a space between the electrode patterns, forming a mask pattern over a certain region of the insulation layer, etching the insulation layer until shoulder portions of the hard mask are planarized, and etching a portion of the insulation layer to form a contact hole.

DESCRIPTION OF SPECIFIC EMBODIMENTS

A fabrication method of a semiconductor device according to various embodiments consistent with the present invention may be implemented to any semiconductor device required of a self-aligned contact (SAC). However, the embodiments consistent with the present invention are exemplified for forming a contact hole between gate patterns for the simplicity of description. In other words, although forming the contact hole between the gate patterns is described in the following embodiments consistent with the present invention, these embodiments consistent with the present invention can still be applied to a method for forming an opening between bit lines or between metal interconnections.

FIGS. 3A to 3Care sectional views illustrating a method for fabricating a semiconductor device in accordance with an embodiment consistent with the present invention. In particular, the method includes a SAC method. Referring toFIG. 3A, a gate insulation layer32is formed over a substrate31. Although not illustrated, substrate31may include an isolation structure that defines an active region and wells. Gate insulation layer32may be formed from a material including an oxide-based material, a nitride-based material, or an oxynitride-based material.

Gate patterns33are formed over gate insulation layer32. Each of gate patterns33includes a gate electrode including polysilicon layer33A, a tungsten or tungsten silicide layer33B, and a gate hard mask33C, which are formed in a stack structure. Gate hard masks33C include a material having etch selectivity to a subsequent inter-layer insulation layer. For instance, gate hard masks33C include one selected from a group consisting of silicon nitride (Si3N4), silicon rich oxynitride (SiON), silicon oxynitride (SiON), and a combination thereof. Gate patterns33are formed in a line type and have fine line widths. After gate patterning, gate hard masks33C, which are upper parts of gate patterns33, have a rounded profile.

A passivation layer34is formed to a certain thickness over gate patterns33and gate insulation layer32. Passivation layer34includes a material having etch selectivity to a subsequent insulation layer (e.g., interlayer). For instance, passivation layer34includes one selected from a group consisting of Si3N4, silicon rich oxynitride, SiON, and a combination thereof.

An insulation layer35is formed over passivation layer34, filling the space between gate patterns33. Insulation layer35includes an oxide-based material having etch selectivity to gate hard masks33C and passivation layer34. For instance, insulation layer35includes one selected from a group consisting of borophosphosilicate glass (BPSG), an oxide-based layer obtained by a high density plasma-chemical vapor deposition (HDP-CVD) method, spin-on-glass (SOG), and a combination thereof.

Referring toFIG. 3B, the resultant structure illustrated inFIG. 3Ais planarized until the round profile of gate patterns33is removed (i.e., the upper parts of gate patterns33). The planarization may be performed by a chemical mechanical polishing (CMP) process. During the CMP process, insulation layer35, passivation layer34and gate hard masks33C are polished. Reference numerals33X,33D,34A and35A represent planarized gate patterns, planarized gate hard masks, a planarized passivation layer and a planarized insulation layer, respectively. Since the main planarization target is gate hard masks33C, a slurry having a high etch rate to gate hard masks33C is used.

A contact mask pattern36for a SAC is formed over planarized insulation layer35A and planarized gate patterns33X. Contact mask pattern36includes one selected from a group consisting of a nitride-based material, polysilicon, a carbon-based polymer material, and a combination thereof. Contact mask pattern36is formed by forming a contact mask layer and applying photolithography thereon. In detail, although not illustrated, an anti-reflective coating layer (e.g., organic bottom anti-reflective coating layer) and a photoresist layer may be formed over the contact mask layer. The photoresist layer is patterned by performing photo-exposure and developing processes, and the contact mask layer is patterned using the photoresist pattern. Finally, the photoresist pattern is removed.

Referring toFIG. 3C, portions of planarized insulation layer35A and planarized passivation layer34A exposed by contact mask pattern36are etched. At this time, gate insulation layer32is also etched to expose a portion of substrate31where source and drain junctions of a transistor are to be formed. As a result, a SAC hole37is formed. Reference numerals32A and35B represent a patterned gate insulation layer and a patterned insulation layer, respectively.

During this etching (i.e., SAC etching), since the profile of gate hard masks33C are previously planarized, polymers are deposited over shoulder portions of planarized gate hard masks33D. Hence, damage to planarized gate hard masks33D can be reduced. Therefore, it is possible to prevent a short failure usually occurring between a conductive material to fill SAC hole37and the gate electrodes, each including polysilicon layer33A and tungsten or tungsten silicide layer33B. Since the SAC etching is not necessarily performed under a condition which produces lots of polymers, the formation of an improper contact opening may be prevented.

FIGS. 4A to 4Care sectional views illustrating a method for fabricating a semiconductor device in accordance with another embodiment consistent with the present invention. In particular, the method includes a SAC method. Referring toFIG. 4A, a gate insulation layer42is formed over a substrate41. Although not illustrated, substrate41may include an isolation structure defining an active region and wells. Gate insulation layer42includes an oxide-based material, a nitride-based material, and an oxynitride-based material.

Gate patterns43are formed over gate insulation layer42. Each of gate patterns43includes a gate electrode including a polysilicon layer43A, a tungsten or tungsten silicide layer42B, and a gate hard mask43C, which are formed in a stack structure. Gate hard masks43C include a material having etch selectivity to a subsequent insulation layer (e.g., interlayer). For instance, gate hard masks43C include one selected form a group consisting of Si3N4, silicon rich oxynitride, SiON, and a combination thereof. Since gate patterns43are formed in a line type and have fine line widths, gate hard masks43C, which are upper parts of gate patterns43, have a round profile after gate patterning.

A passivation layer44is formed over gate patterns43and gate insulation layer42. Passivation layer44includes a material having etch selectivity to the insulation layer. For example, passivation layer44includes a material selected form a group consisting of Si3N4, silicon rich oxynitride, SiON, and a combination thereof.

Insulation layer45is formed over the above resultant structure, filling the space between gate patterns43. Insulation layer45includes an oxide-based material having etch selectivity to gate hard masks43C and passivation layer44. For instance, insulation layer45includes a material selected from a group consisting of BPSG, an oxide layer obtained by a HDP-CVD method, SOG, and a combination thereof.

Referring toFIG. 4B, a contact mask pattern46for a SAC is formed over insulation layer45. Contact mask pattern46includes a nitride-based material, polysilicon, a carbon-based polymer material, or a combination thereof. Similar to the first described embodiment, contact mask pattern46is formed by depositing a contact mask layer and applying photolithography to the contact mask layer. Portions of insulation layer45, passivation layer44and gate hard masks43C exposed by contact mask pattern46are etched such that shoulder portions of gate hard masks43C are partially planarized. This etching may be performed by employing a dry etching process or a wet etching process. Partially planarized gate hard masks and gate patterns are labeled as43D and43X, respectively. Also, reference numerals44A and45A represent a patterned insulation layer and a patterned passivation layer, respectively. Due to planarized gate hard masks43D, polymers are deposited over the planarized surface of gate hard masks43D during subsequent SAC etching, so that an additional loss of partially planarized gate hard masks43D can be prevented.

Referring toFIG. 4C, portions of patterned insulation layer45A and patterned passivation layer44A disposed between partially planarized gate patterns43X are etched. At this time, gate insulation layer42is also etched to form a SAC hole47. SAC hole47exposes a portion of substrate41(e.g., source and drain junctions of a transistor). Reference numeral42A denotes a patterned gate insulation layer.

FIGS. 5A to 5Cillustrate TEM images of semiconductor structures obtained by a fabrication method of a semiconductor device in accordance with another embodiment consistent with the present invention.FIG. 5Aillustrates gate patterns with upper parts which are planarized by dry etching. Such a planarized profile of the gate patterns allows sufficient deposition of polymers over the gate patterns during subsequent SAC etching. As a result, damage to the upper parts of the gate patterns can be reduced.

FIGS. 5B and 5Cillustrate profiles of gate patterns after SAC etching. As compared with profiles of the conventional gate patterns illustrated inFIG. 2Bor2C, the gate patterns illustrated inFIGS. 5B and 5Chave upper parts which are less damaged.

FIGS. 6A and 6Billustrate comparative TEM images of semiconductor devices, which are respectively fabricated by the conventional fabrication method and the fabrication method according to another embodiment consistent with the present invention. Referring toFIG. 6A, upper parts of the conventional gate patterns are rounded. On the other hand, as illustrated inFIG. 6B, upper parts of gate patterns formed according to the present embodiment are planarized. As compared with the round profile of the gate patterns illustrated inFIG. 6A, the planarized profile of the gate patterns illustrated inFIG. 6Ballows deposition of polymers over the planarized surface of the gate patterns during SAC etching. The deposited polymers function as a protector, which can contribute to reduction in the loss of the gate hard masks.

On the basis of various embodiments consistent with the present invention, prior to SAC etching, the rounded upper parts of the gate patterns are planarized using one of CMP, dry etching, and wet etching. Thus, damage to the gate hard masks can be reduced during the SAC etching. Due to this effect, a short failure usually occurring between a contact material to fill the SAC hole and the individual gate electrodes can be prevented. It is unnecessary to perform the SAC etching under the condition that produces lots of polymers, and thus, an improper contact opening can be reduced.

It will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope consistent with the invention as defined in the following claims.