Semiconductor memory device

A semiconductor memory device of an embodiment has stacked semiconductor memories, each semiconductor memory including first lines intersecting with second lines, and resistive change elements each disposed between one of the first lines and one of the second lines. In two of the semiconductor memories adjacent to each other in the stacking direction, either two of the first lines or two of the second lines are disposed along and in contact with each other. A first contact electrically connected to the second line of the uppermost semiconductor memory passes through a region between the second lines of each of the semiconductor memories located below the uppermost semiconductor memory, and a second contact electrically connected to the second line of each of the semiconductor memories located at an intermediate level passes through a region between the second lines of each of the semiconductor memories located below the intermediate level.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2019-166252, filed on Sep. 12, 2019, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to semiconductor memory devices.

BACKGROUND

Semiconductor memories including resistive change elements such as phase-change memory elements (hereinafter also referred to as “phase-change material (PCM) elements”) serving as storage elements disposed in intersections of wirings are known.

Such semiconductor memories may be stacked and integrated. In such a case, however, the chip size may be increased.

DETAILED DESCRIPTION

In a semiconductor memory including resistive change elements such as a phase-change memory elements (hereinafter also referred to as phase-change material (PCM) elements) serving as storage elements, a wiring (for example, a first bit line) intersects with another wiring (for example, a first word line) in a stacking manner, a second bit line is disposed to intersect with the first word line, a second word line is disposed to intersect with the second bit line, and each resistive change element is disposed at an intersection of a bit line and a word line. If wirings are further stacked, and a third bit line is disposed to intersect with the second word line and a third word line is disposed to intersect with the third bit line, a contact that electrically connects the third word line and a driving circuit for driving the third word line disposed on the lowest level of the semiconductor memory may contact the first word line or the second word line which is disposed below the third word line. This problem may be solved by dividing the word line that may possibly contact the contact. In such a case, however, another wiring that connects the divided word lines is needed, which increases the chip size. If the divided word lines are not connected by using another wiring, additional transistors may be needed to drive the divided word lines, which also increases the chip size.

A semiconductor memory capable of preventing an increase in chip size if having an increased number of layers will then be described by referring to embodiments below.

A semiconductor memory device according to an embodiment includes: a plurality of first wirings disposed at a first level and extending in a first direction; a second wiring and a third wiring disposed at a second level, a position of which in a second direction intersecting with the first direction is different from that of the first level, the second wiring and the third wiring extending in a third direction that intersects with the first direction and the second direction, and being separated from each other; a plurality of first resistive change elements each including a first terminal and a second terminal and disposed between one of the first wirings and one of the second wiring and the third wiring, the first terminal being electrically connected to the one of the first wirings, and the second terminal being electrically connected to the one of the second wiring and the third wiring; a fourth wiring disposed to be in contact with a face of the second wiring opposite to the first wirings and extending in the third direction; a fifth wiring disposed to be in contact with a face of the third wiring opposite to the first wirings, extending in the third direction, and separated from the fourth wiring; a plurality of sixth wirings disposed at a third level and extending in the first direction, the second level being between the first level and the third level; a plurality of second resistive change elements each including a third terminal and a fourth terminal and disposed between one of the fourth wiring and the fifth wiring and one of the sixth wirings, the third terminal being electrically connected to the one of the fourth wiring and the fifth wiring, and the fourth terminal being electrically connected to the one of the sixth wirings; a plurality of seventh wirings disposed to correspond to the sixth wirings and extending in the first direction, each of the seventh wirings being disposed to be in contact with a face of corresponding one of the sixth wirings opposite to the second resistive change elements; an eighth wiring and a ninth wiring disposed at a fourth level, extending in the third direction, and separated from each other, the third level being between the fourth level and the second level; a plurality of third resistive change elements each including a fifth terminal and a six terminal and disposed between one of the seventh wirings and one of the eighth wiring and the ninth wiring, the fifth terminal being electrically connected to the one of the seventh wirings, and the six terminal being electrically connected to the one of the eighth wiring and the ninth wiring; a tenth wiring disposed to be in contact with a face of the eighth wiring opposite to the seventh wirings and extending in the third direction; an eleventh wiring disposed to be in contact with a face of the ninth wiring opposite to the seventh wirings and extending in the third direction, and separated from the tenth wiring; a plurality of twelfth wirings disposed at a fifth level and extending in the first direction, the fourth level being between the fifth level and the third level; a plurality of fourth resistive change elements each including a seventh terminal and an eighth terminal and disposed between one of the tenth wiring and the eleventh wiring and one of the twelfth wirings, the seventh terminal being electrically connected to the one of the tenth wiring and the eleventh wiring, and the eighth terminal being electrically connected to the one of the twelfth wirings; a plurality of thirteenth wirings disposed to correspond to the twelfth wirings and extending in the first direction, each of the thirteenth wirings disposed to be in contact with a face of corresponding one of the twelfth wirings opposite to the fourth resistive change elements; a fourteenth wiring and a fifteenth wiring disposed at a sixth level, extending in the third direction, and separated from each other, the fifth level being between the sixth level and the fourth level, a region between the tenth wiring and the eleventh wiring, a region between the eighth wiring and the ninth wiring, a region between the fourth wiring and the fifth wiring, and a region between the second wiring and the third wiring being located at positions in the second direction from a portion of the fourteenth wiring; a plurality of fifth resistive change elements each including a ninth terminal and a tenth terminal and disposed between one of the thirteenth wirings and one of the fourteenth wiring and the fifteenth wiring, the ninth terminal being electrically connected to the one of the thirteenth wirings, and the tenth terminal being electrically connected to the one of the fourteenth wiring and the fifteenth wiring; a sixteenth wiring disposed to be in contact with a face of the fourteenth wiring opposite to the thirteenth wirings and extending in the third direction; a seventeenth wiring disposed to be in contact with a face of the fifteenth wiring opposite to the thirteenth wirings and extending in the third direction, and separated from the sixteenth wiring; a plurality of eighteenth wirings disposed at a seventh level and extending in the first direction, the sixth level being between the seventh level and the fifth level; a plurality of sixth resistive change elements each including an eleventh terminal and a twelfth terminal and disposed between one of the sixteenth wiring and the seventeenth wiring and one of the eighteenth wirings, the eleventh terminal being electrically connected to the one of the sixteenth wiring and the seventeenth wiring, and the twelfth terminal being electrically connected to the one of the eighteenth wirings; a first contact electrically connected to a portion of the third wiring; a second contact electrically connected to an end of the ninth wiring on a side of the eighth wiring, and passing through the region between the fourth wiring and the fifth wiring and the region between the second wiring and the third wiring; and a third contact electrically connected to the portion of the fourteenth wiring, and passing through the region between the tenth wiring and the eleventh wiring, the region between the eighth wiring and the ninth wiring, the region between the fourth wiring and the fifth wiring, and the region between the second wiring and the third wiring.

First Embodiment

A semiconductor memory device according to a first embodiment will be described with reference toFIGS. 1 and 2.FIG. 1is a cross-sectional view of the semiconductor memory device according to the first embodiment. The cross-sectional view shown inFIG. 1shows a z-y plane.FIG. 2shows a cross-sectional view taken along line J-J shown inFIG. 1.

The semiconductor memory device according to the first embodiment has a structure obtained by sequentially stacking a cross-point semiconductor memory101, a cross-point semiconductor memory102, a cross-point semiconductor memory103, a cross-point semiconductor memory104, a cross-point semiconductor memory105, and a cross-point semiconductor memory106. In the following descriptions, each memory cell of the respective semiconductor memories has a resistive change element serving as a storage element. The resistive change element is a PCM element in the following descriptions, but not limited thereto.

The semiconductor memory101includes a plurality of (nine inFIG. 1) bit lines BL14to BL112, a plurality of (nine in FIG.1) PCM elements1114to11112, and a plurality of (two inFIG. 1) word lines WL11and WL12. The bit lines BL14to BL112, the PCM elements1114to11112, and the word lines WL11and WL12are disposed at different levels in a z direction (the vertical direction inFIG. 1).

The bit lines BL14to BL112extend in a direction perpendicular to the plane ofFIG. 1(x direction). The word lines WL11and the word line WL12extend in a lateral direction inFIG. 1(y direction), and separated from each other. In other words, there is a space between the word line WL11and the word line WL12. One end of the PCM element111jis electrically connected to the bit line BL1j(j=4, . . . , 12). The other end of each of the PCM elements1114to1116is electrically connected to the word line WL11. The other end of each of the PCM elements1117to11112is electrically connected to the word line WL12. The description “A and B are electrically connected” herein means that A and B may be directly connected or indirectly connected via a conductive member disposed between A and B.

The semiconductor memory102includes a plurality of (two inFIG. 1) word lines WL21and WL22, a plurality of (nine inFIG. 1) bit lines BL24to BL212, and a plurality of (nine inFIG. 1) PCM elements1124to11212. The word lines WL21and WL22, the PCM elements1124to11212, and the bit lines BL24to BL212are disposed at different levels in the z direction (the vertical direction inFIG. 1).

The word line WL21and the word line WL22extend in the lateral direction inFIG. 1(y direction), and separated from each other. The word line WL21and the word line WL22are disposed to be in electrical contact with the top faces of the word line WL11and the word line WL12of the semiconductor memory101, respectively. The lengths of the word line WL21and the word line WL22in the y direction are substantially the same as the lengths of the word line WL11and the word line WL12in the y direction, respectively. The description “A and B are in electrical contact with each other” herein means that A and B may be electrically in direct contact with each other or in indirect contact with each other with a conductive member being disposed therebetween. There is a space between the word line WL21and the word line WL22, like the word line WL11and the word line WL12. The bit lines BL24to BL212extend in the direction perpendicular to the plane ofFIG. 1(x direction). One end of each of the PCM elements1124to1126is electrically connected to the word line WL21. One end of each of the PCM elements1127to11212is electrically connected to the word line WL22. The other end of the PCM element112j(j=4, . . . , 12) is electrically connected to the bit line BL2j.

The semiconductor memory103includes a plurality of (nine inFIG. 1) bit lines BL34to BL312, a plurality of (nine inFIG. 1) PCM elements1134to11312, and a plurality of (two inFIG. 1) word lines WL31and WL32. The bit lines BL34to BL312, the PCM elements1134to11312, and the word line WL31, WL32are disposed at different levels in the z direction (the vertical direction inFIG. 1).

The bit lines BL34to BL312extend in the direction perpendicular to the plane ofFIG. 1(x direction). The bit line BL3j(j=4, . . . , 12) is arranged to be in electrical contact with the top face of the bit line BL23of the semiconductor memory102. The word line WL31and the word line WL32extend in the lateral direction inFIG. 1(y direction), and separated from each other. In other words, there is a space (region) between the word line WL31and the word line WL32. The word line WL31is arranged at substantially the same location as the word line WL11and the word line WL21in the y direction. However, the length of the word line WL31in the y direction is longer than the length of each of the word line WL11and the word line WL21in the y direction to have a portion where a contact (not shown) is connected. The word line WL32is arranged at substantially the same location as the word line WL12and the word line WL22in the y direction. However, the length of the word line WL32in the y direction is longer than the length of each of the word line WL12and the word line WL22in the y direction to have a portion where a contact (not shown) is connected. For example, inFIG. 1, a contact VW32is disposed at a left end (on the word line WL31side) of the word line WL32. The “end of a wiring” herein means a region of the wiring that is closer to an adjacent wiring in the wiring extending direction than any of resistive change elements connected to the wiring. Therefore, there are two ends for each wiring. The left end of the word line WL32means an end of the word line WL32on the side of the word line WL31that is arranged to the immediate left of the word line WL32in the y direction.

Therefore, the length in the y direction of the space between the word line WL31and the word line WL32is shorter than the length in the y direction of the space between the word line WL11and the word line WL12. One end of the PCM element113jis electrically connected to the bit line BL3j(j=4, . . . , 12). The other end of each of the PCM elements1134to1136is electrically connected to the word line WL31. The other end of each of the PCM elements1137to11312is electrically connected to the word line WL32.

The semiconductor memory104includes a plurality of (two inFIG. 1) word lines WL41and WL42, a plurality of (nine inFIG. 1) bit lines BL44to BL412, and a plurality of (nine inFIG. 1) PCM elements1144to11412. The word lines WL41and WL42, the PCM elements1144to11412, and the bit lines BL44to BL412are disposed at different levels in the z direction (the vertical direction inFIG. 1).

The word line WL41and the word line WL42extend in the lateral direction inFIG. 1(y direction), and separated from each other. The word line WL41and the word line WL42are disposed to be in electrical contact with the top faces of the word line WL31and the word line WL32of the semiconductor memory103, respectively. The lengths of the word line WL41and the word line WL42in the y direction are substantially the same as the lengths of the word line WL31and the word line WL32in the y direction, respectively. Thus, like the word line WL31and the word line WL32, there is a space between the word line WL41and the word line WL42. The bit lines BL44to BL412extend in the direction perpendicular to the plane ofFIG. 1(x direction). One end of each of the PCM elements1144to1146is electrically connected to the word line WL41. One end of each of the PCM elements1147to11412is electrically connected to the word line WL42. The other end of the PCM element114j(j=4, . . . , 12) is electrically connected to the bit line BL4j.

The semiconductor memory105includes a plurality of (nine inFIG. 1) bit lines BL54to BL512, a plurality of (nine inFIG. 1) PCM elements1154to11512, and a plurality of (two inFIG. 1) word lines WL51and WL52. The bit lines BL54to BL512, the PCM elements1154to11512, and the word lines WL51and WL52are disposed at different levels in the z direction (the vertical direction inFIG. 1).

The bit lines BL54to BL512extend in the direction perpendicular to the plane ofFIG. 1(x direction). The bit line BL5j(j=4, . . . , 12) is arranged to be in electrical contact with the top face of the bit line BL4jof the semiconductor memory104. The word line WL51and the word line WL52extend in the lateral direction inFIG. 1(y direction), and separated from each other. In other words, there is a space between the word line WL51and the word line WL52. The word line WL51is arranged at a location that is different from the location of each of the word line WL31and the word line WL41in the y direction. The word line WL52is arranged at a location that is different from the location of each of the word line WL32and the word line WL42in the y direction. For example, inFIG. 1, the central portion in the y direction of the word line WL51is located above the central portion of the space between word line WL11and the word line WL12(in the z direction). One end of the PCM element1153is electrically connected to the bit line BL5j(j=4, . . . , 12). The other end of each of the PCM elements1154to1156is connected to the word line WL51. The other end of each of the PCM elements1157to11512is electrically connected to the word line WL52.

The semiconductor memory106includes a plurality of (two inFIG. 1) word lines WL61and WL62, a plurality of (nine inFIG. 1) bit lines BL64to BL612, and a plurality of (nine inFIG. 1) PCM elements1164to11612. The word lines WL61and WL62, the PCM elements1164to11612, and the bit lines BL64to BL612are disposed at different levels in the z direction (the vertical direction inFIG. 1).

The word line WL61and the word line WL62extend in the lateral direction inFIG. 1(y direction), and separated from each other. The word line WL61and the word line WL62are disposed to be in electrical contact with the top faces of the word line WL51and the word line WL52of the semiconductor memory105, respectively. The lengths of the word line WL61and the word line WL62in the y direction are substantially the same as the lengths of the word line WL51and the word line WL52in the y direction, respectively. Thus, like the word line WL51and the word line WL52, there is a space between the word line WL61and the word line WL62. The bit lines BL64to BL612extend in the direction perpendicular to the plane ofFIG. 1(x direction). One end of each of the PCM elements1164to1166is electrically connected to the word line WL61. One end of each of the PCM elements1167to11612is electrically connected to the word line WL62. The other end of the PCM element116j(j=4, . . . , 12) is electrically connected to the bit line BL6j.

One end of each of three PCM elements that are not shown is electrically connected to each of the word lines WL21, WL31, and WL41, and the other ends of the PCM elements are electrically connected to bit lines that are not shown. One end of each of three PCM elements that are not shown is electrically connected to each of the word lines WL52and WL62, and the other ends of the PCM elements are electrically connected to bit lines that are not shown. Thus, in the semiconductor memory device shown inFIG. 1, one end of each of six PCM elements is electrically connected to each word line. The number of PCM elements electrically connected to each word line may be more than six.

The semiconductor memory device shown inFIG. 1also includes driving circuits (for example, driving circuits10012,10032,10051, and10052) for driving the respective word lines, and a control circuit200for controlling the driving circuits. For example, the driving circuit10012is connected to the word line WL12through a contact VW12, the driving circuit10032is connected to the word line WL32through a contact VW32, the driving circuit10051is connected to the word line WL51through a contact VW51, and the driving circuit10052is connected to the word line WL52through a contact VW52. Since the word line WL22is arranged to be in contact with the top face of the word line WL12, it is driven by the driving circuit10012. Since the word line WL42is arranged to be in contact with the top face of the word line WL32, it is driven by the driving circuit10032. Since the word line WL51is arranged to be in contact with the top face of the word line WL51, it is driven by the driving circuit10051. Since the word line WL62arranged to be in contact with the top face of the word line WL52, it is driven by the driving circuit10052. The word lines WL11and WL31are driven by driving circuits, which are not shown, through contacts, which are not shown, either. The contact (not shown) for the word line WL11connects to a portion (for example a central portion) of the word line WL11, like the contact for the word line WL12. The contact (not shown) for the word line WL31connects to the left end of the word line WL31, like the contact for the word line WL32. Since the word lines WL21and WL41are in contact with the top faces of the word lines WL11and WL31, respectively, they are also driven by the driving circuits that are not shown.

The contact VW12is formed to electrically connect to a portion (for example a central portion) of the word line WL12. The contact VW32is formed to electrically connect to the left end (on the side of the word line WL31) of the word line WL32and also to the driving circuit10032through the space between the word line WL11and the word line WL12. The bit line BL3jconnected to the PCM element113j(j=7, . . . , 12) that is further connected to the word line WL32is stacked on the bit line BL23. As a result, the wiring resistance of this portion becomes lower than that of a single wiring. Therefore, the existence of the contact VW32at the end of the word line WL32does not affect the voltage drop caused by a write current or a read current.

The contact VW51is formed to electrically connect to a portion (for example a central portion) of the word line WL51, and also to the driving circuit10051through the space between the word line WL31and the word line WL32and the space between the word line WL11and the word line WL12. The contact VW52is formed to electrically connect to a portion (for example a central portion) of the word line WL52, and also to the driving circuit10052through the space on the right side of the word lines WL42and WL32and the space on the right side of the word lines WL22and WL12. The control circuit200also controls bit lines connected to PCM elements to be accessed.

Each driving circuit includes a p-channel transistor and an n-channel transistor connected in series. The gate of each of the series-connected p-channel transistor and n-channel transistor is connected to the control circuit200. An intermediate node (connection node) of the series-connected transistors is electrically connected to the corresponding word line through the corresponding contact. Each of the driving circuits supplies a write current or a read current via the corresponding word line to the PCM element to be accessed.

Furthermore, in the semiconductor memory device according to the first embodiment, the bit line BL14is electrically connected to the bit line BL44through a contact VB44, and to the control circuit200through a contact VB14, as shown inFIG. 2. The bit line BL34is electrically connected to the bit line BL64through a contact VB64, and the bit line BL24is electrically connected to the control circuit200through a contact VB24.

The semiconductor memory device according to the first embodiment also includes stacked bit lines BL24′ and BL34′ located at a distance from the right end of the stacked bit lines BL24and BL34and extending in the x direction. The contact VB44is disposed to pass through the space between the bit lines BL24, BL34and the bit lines BL24′, BL34′. Furthermore, a bit line BL64′ extending in the x direction is disposed at a distance from the right end of the bit line BL64. The bit line BL64′ is electrically connected to the bit line BL34′ through the contact VB64′. The contact VB64′ passes through the space on the right side of the bit lines BL44, BL54and is electrically connected to the bit line BL34′. The contact VB64passes through the space on the left side of the bit lines BL44, BL54and electrically connected to the bit line BL34. The contact VB24passes through the space on the left side of the bit line BL14and is electrically connected to the control circuit200. The contact VB24′ passes through the space on the right side of the bit line BL14and is electrically connected to the control circuit200. The bit lines BL44, BL54are located directly above the bit line BL14, the bit line BL64is located directly above the bit lines BL24, BL34, and the bit line BL64′ is located directly above the bit lines BL24′, BL34′. Therefore, the location of the bit line BL14is shifted along the x direction from the locations of the bit lines BL24, BL34, and BL64, and also the locations of the bit lines BL24′, BL34′, and BL64′. The location of the bit line BL64is shifted along the x direction from the location of the bit lines BL44, BL54, and the location of the bit line BL64′ is shifted along the x direction from the location of the bit lines BL44, BL54.

As described above, in the first embodiment and second and third embodiments that will be described later, a bit line (for example, the bit line BL14) of the first semiconductor memory101on the bottom and a bit line (for example, the bit line BL44) of the fourth semiconductor memory104, the location of which along the x direction is the same as the location of the bit line of the first semiconductor memory101, are connected to each other through the contact VB44, and a bit line (for example, the bit line BL34) of the third semiconductor memory103and a bit line (for example, the bit line BL64) of the sixth semiconductor memory106, the location of which along the x direction is the same as the location of the bit line of the third semiconductor memory103, are connected to each other through the contact VB64. In other words, a bit line of the ith(i=1, 2, 3, 4) semiconductor memory and a bit line of the (i+3)thsemiconductor memory, the location of which along the x direction is the same as the bit line of the ithsemiconductor memory, are electrically connected to each other through a contact.

Furthermore, in the semiconductor memory device according to the first embodiment, a plurality of (three inFIG. 2) sets of stacked word lines WL11, WL21are disposed between the left region relative to the contact VB44of the bit line BL14and the right region relative to the contact VB24of the bit line BL24. The PCM element1114is disposed between the bit line BL14and each word line WL11, and the PCM element1124is disposed between the bit line BL24and each word line WL21.

A plurality of (three inFIG. 2) sets of stacked word lines WL11′, WL21′ are disposed between the right region relative to the contact VB44of the bit line BL14and the left region relative to the contact VB24′ of the bit line BL24′. The PCM element1114′ is disposed between the bit line BL14and each word line and the PCM element1124′ is disposed between the bit line BL24′ and each word line WL21′.

A plurality of (three inFIG. 2) sets of stacked word lines WL31, WL41are disposed between the left region relative to the contact VB44of the bit line BL44and the right region relative to the contact VB64of the bit line BL34. The PCM element1134is disposed between the bit line BL34and each word line WL31, and the PCM element1144is disposed between the bit line BL44and each word line WL41.

A plurality of (three inFIG. 2) sets of stacked word lines WL31′, WL41′ are disposed between the right region relative to the contact VB44of the bit line BL44and the left region relative to the contact VB64′ of the bit line BL34′. The PCM element1134′ is disposed between the bit line BL34and each word line WL31′ and the PCM element1144′ is disposed between the bit line BL44′ and each word line WL41′.

A plurality of (three inFIG. 2) sets of word lines WL51, WL61are disposed between the right region relative to the contact VB64of the bit line BL64and the left region of the bit line BL54. The PCM element1154is disposed between the bit line BL54and each word line WL51, and the PCM element1164is disposed between the bit line BL64and each word line WL61.

A plurality of (three inFIG. 2) sets of stacked word lines WL51′, WL61′ are disposed between the left region relative to the contact VB64′ of the bit line BL64′ and the right region of the bit line BL54. The PCM element1154′ is disposed between the bit line BL54and each word line WL51′, and the PCM element1164′ is disposed between the bit line BL64′ and each word line WL61′.

A plurality of sets of word lines and PCM elements connected to those word line sets, which are not shown, are disposed on the left region relative to the contact VB24of the bit line BL24. A plurality of sets of word lines and PCM elements connected to those word line sets, which are not shown, are disposed on the left region relative to the contact VB64of the bit line BL34. A plurality of sets of word lines and PCM elements connected to those word line sets, which are not shown, are disposed on the right region relative to the contact VB24′ of the bit line BL24′. A plurality of sets of word lines and PCM elements connected to those word line sets, which are not shown, are disposed on the right region relative to the contact VB64′ of the bit line BL34′. A plurality of sets of word lines and PCM elements connected to those word line sets, which are not shown, are disposed on the left region relative to the contact VB64of the bit line BL64. A plurality of sets of word lines and PCM elements connected to those word line sets, which are not shown, are disposed on the right region relative to the contact VB64′ of the bit line BL64′.

In the first embodiment having the above-described structure and the second and third embodiments that will be described later, the PCM elements includes a phase-change material, the phase of which changes between crystal phase and amorphous phase. An example of the phase-change material is a chalcogenide alloy (for example, a GeSbTe alloy). The chalcogenide alloy contains a chalcogenide (GeSbTe). Other examples include a AsSbTe alloy, a TaSbTe alloy, a NbSbTe alloy, a VSbTe alloy, a NbSbSe alloy, a VSbSe alloy, a WSbTe alloy, a MoSbTe alloy, a CrSbTe alloy, a WSbSe alloy, a MoSbSe alloy, a CrSbSe alloy, and a SnSbTe alloy.

A phase-change material changes to the crystal phase having a low resistance value if it is heated, melted, and cooled slowly, and to the amorphous phase having a high resistance value if it is cooled rapidly. Therefore, if a PCM element is heated by applying a voltage between the corresponding word line and the corresponding bit line, and then the voltage is rapidly dropped, the phase-change material of the PCM element is cooled rapidly and changes to the amorphous phase that is in a high-resistance state. If the voltage is dropped slowly, the phase-change material of the PCM element is cooled slowly and changes to the crystal phase that is in a low-resistance state. Data (information) may be written to the PCM element in this manner. The data (information) may be read from the PCM element by applying a voltage between the corresponding word line and the corresponding bit line, and measuring a current caused to flow by the voltage application, thereby measuring the resistance of the PCM element, for example.

As described above, according to the first embodiment, the contact VW51is electrically connected to a driving circuit for the fifth semiconductor memory105, for example the driving circuit10051, and the contact VW32is electrically connected to a driving circuit for the third semiconductor memory103, for example the driving circuit10032, through the space between the word line WL31and the word line WL32of the third semiconductor memory103, the space between the word line WL21and the word line WL22of the second semiconductor memory102, and the space between the word line WL11and the word line WL12of the first semiconductor memory101.

Thus, a contact electrically connected to a word line (for example, the word line WL61) included in the uppermost semiconductor memory106passes through the spaces between the word lines included in the semiconductor memories104,103, and102that are located at two or more levels below the uppermost semiconductor memory106, and is electrically connected to the corresponding driving circuit. A contact electrically connected to one of the word lines included in any of the semiconductor memories103,104,105, and106located at the third or higher level passes through the space between the word lines included in the semiconductor memory101disposed at the first level, or the space on the right or left side of either of the word lines included in the semiconductor memory101that is located substantially the same position as the word line electrically connected to the contact, and is electrically connected to the corresponding driving circuit. For example, the contact electrically connected to the word line WL31passes through the space at the left end of the word line WL11of the semiconductor memory101and electrically connected to the corresponding driving circuit.

As a result, a contact for the fifth semiconductor memory105, for example the contact VW51electrically connecting a word line, for example the word line WL51, and the driving circuit10051that is located on the bottom does not contact the word lines of the first to fourth semiconductor memories101to104. Therefore, it is not necessary to divide the word lines of the semiconductor memories located below the fifth semiconductor memory105. As a result, an increase in chip size may be prevented.

Second Embodiment

FIG. 3shows a semiconductor memory device according to a second embodiment. Like the semiconductor memory device according to the first embodiment, the semiconductor memory device according to the second embodiment has a structure in which a contact electrically connecting to a word line included in the uppermost semiconductor memory passes through the space between word lines included in semiconductor memories located two or more levels below the uppermost semiconductor memory to be electrically connected to a corresponding driving circuit. Furthermore, a contact electrically connecting to a word line of each of the semiconductor memories disposed at the third or higher levels passes through the space between the word lines of the semiconductor memory disposed at the first level, or the space on the right or left side of any of the word lines included in the semiconductor memory that is located at substantially the same position as the word line to which the contact is electrically connected, to be electrically connected to a corresponding driving circuit. The structure of the semiconductor memory device according to the second embodiment will be described below with reference toFIG. 3.

The semiconductor memory device according to the second embodiment has a structure obtained by sequentially stacking a cross-point semiconductor memory101, a cross-point semiconductor memory102, a cross-point semiconductor memory103, a cross-point semiconductor memory104, a cross-point semiconductor memory105, a cross-point semiconductor memory106, a cross-point semiconductor memory107, and a cross-point semiconductor memory108. In the following descriptions, each memory cell of the respective semiconductor memories has a resistive change element serving as a storage element. The resistive change element is a PCM element in the following descriptions, but not limited thereto.

The semiconductor memory101includes a plurality of (nine inFIG. 3) bit lines BL14to BL112, a plurality of (nine inFIG. 3) PCM elements1114to11112, and a plurality of (two inFIG. 3) word lines WL11and WL12. The bit lines BL14to BL112, the PCM elements1114to11112, and the word lines WL11and WL12are disposed at different levels in a z direction (the vertical direction inFIG. 3).

The bit lines BL14to BL112extend in a direction perpendicular to the plane ofFIG. 3(x direction). The word line WL11and the word line WL12extend in a lateral direction inFIG. 3(y direction), and separated from each other. In other words, there is a space between the word line WL11and the word line WL12. One end of the PCM element111jis electrically connected to the bit line BL1j(j=4, . . . , 12). The other end of each of the PCM elements1114to1116is electrically connected to the word line WL11. The other end of each of the PCM elements1117to11112is electrically connected to the word line WL12.

The semiconductor memory102includes a plurality of (two inFIG. 3) word lines WL21and WL22, a plurality of (nine inFIG. 3) bit lines BL24to BL212, and a plurality of (nine inFIG. 3) PCM elements1124to11212. The word lines WL21and WL22, the PCM elements1124to11212, and the bit lines BL24to BL212are disposed at different levels in the z direction (the vertical direction inFIG. 3).

The word line WL21and the word line WL22extend in the lateral direction inFIG. 3(y direction), and separated from each other. The word line WL21and the word line WL22are disposed to be in electrical contact with the top faces of the word line WL11and the word line WL12of the semiconductor memory101, respectively. The lengths of the word line WL21and the word line WL22in the y direction are substantially the same as the lengths of the word line WL11and the word line WL12in the y direction, respectively. Thus, like the word line WL11and the word line WL12, there is a space between the word line WL21and the word line WL22. The bit lines BL24to BL212extend in the direction perpendicular to the plane ofFIG. 3(x direction). One end of each of the PCM elements1124to1126is electrically connected to the word line WL21. One end of each of the PCM elements1127to11212is electrically connected to the word line WL22. The other end of the PCM element112j(j=4, . . . , 12) is electrically connected to the bit line BL2j.

The semiconductor memory103includes a plurality of (nine inFIG. 3) bit lines BL34to BL312, a plurality of (nine inFIG. 3) PCM elements1134to11312, and a plurality of (two inFIG. 3) word lines WL31and WL32. The bit lines BL34to BL312, the PCM elements1134to11312, and the word lines WL31and WL32are disposed at different levels in the z direction (the vertical direction inFIG. 3).

The bit lines BL34to BL312extend in the direction perpendicular to the plane ofFIG. 3(x direction). The bit line BL3j(j=4, . . . , 12) is arranged to be in electrical contact with the top face of the bit line BL2jof the semiconductor memory102. The word line WL31and the word line WL32extend in the lateral direction inFIG. 3(y direction), and separated from each other. In other words, there is a space between the word line WL31and the word line WL32. The word line WL31is arranged at substantially the same location as the word line WL11and the word line WL21in the y direction. However, the length of the word line WL31in the y direction is longer than the length of each of the word line WL11and the word line WL21in the y direction to have a region where a contact (not shown) is disposed. The word line WL32is arranged at substantially the same location as the word line WL12and the word line WL22in the y direction. However, the length of the word line WL32in the y direction is longer than the length of each of the word line WL12and the word line WL22in the y direction to have a region where a contact VW32is disposed. For example, inFIG. 3, the contact VW32is disposed on a left and (on the word line WL31side) of the word line WL32. Therefore, the length in the y direction of the space between the word line WL31and the word line WL32is shorter than the length in the y direction of the space between the word line WL11and the word line WL12. One end of the PCM element113jis electrically connected to the bit line BL3j(j=4, . . . , 12). The other end of each of the PCM elements1134to1136is electrically connected to the word line WL31. The other end of each of the PCM elements1137to11312is electrically connected to the word line WL32.

The semiconductor memory104includes a plurality of (two inFIG. 3) word lines WL41and WL42, a plurality of (nine inFIG. 1) bit lines BL44to BL412, and a plurality of (nine inFIG. 3) PCM elements1144to11412. The word lines WL41and WL42, the PCM elements1144to11412, and the bit lines BL44to BL412are disposed at different levels in the z direction (the vertical direction inFIG. 3).

The word line WL41and the word line WL42extend in the lateral direction inFIG. 3(y direction), and separated from each other. The word line WL41and the word line WL42are disposed to be in electrical contact with the top faces of the word line WL31and the word line WL32of the semiconductor memory103, respectively. The lengths of the word line WL41and the word line WL42in the y direction are substantially the same as the lengths of the word line WL31and the word line WL32in the y direction, respectively. Thus, like the word line WL31and the word line WL32, there is a space between the word line WL41and the word line WL42. The bit lines BL44to BL412extend in the direction perpendicular to the plane ofFIG. 3(x direction). One end of each of the PCM elements1144to1146is electrically connected to the word line WL41. One end of each of the PCM elements1147to11412is electrically connected to the word line WL42. The other end of the PCM element114j(j=4, . . . , 12) is electrically connected to the bit line BL4j.

The semiconductor memory105includes a plurality of (nine inFIG. 3) bit lines BL54to BL512, a plurality of (nine inFIG. 1) PCM elements1154to11512, and a plurality of (two inFIG. 3) word lines WL51and WL52. The bit lines BL54to BL512, the PCM elements1154to11512, and the word lines WL51and WL52are disposed at different levels in the z direction (the vertical direction inFIG. 3).

The bit lines BL54to BL512extend in the direction perpendicular to the plane ofFIG. 3(x direction). The bit line BL5j(j=4, . . . , 12) is arranged to be in electrical contact with the top face of the bit line BL4jof the semiconductor memory104. The word line WL51and the word line WL52extend in the lateral direction inFIG. 3(y direction), and separated from each other. In other words, there is a space between the word line WL51and the word line WL52. The word line WL51is arranged at substantially the same location as the word line WL11and the word line WL21in the y direction. However, the length of the word line WL51in the y direction is longer than the length of each of the word line WL11and the word line WL21in the y direction to have a region where a contact VW51is disposed. The contact VW51is electrically connected to the word line WL51and also to the driving circuit10051. The word line WL52is arranged at substantially the same location as the word line WL12and the word line WL22in the y direction. However, the length of the word line WL52in the y direction is longer than the length of each of the word line WL12and the word line WL22in the y direction to have a region where a contact (not shown) is disposed. For example, inFIG. 3, the contact VW51connecting to the word line WL51is disposed at an end on the word line WL52side. Therefore, the length in the y direction of the space between the word line WL51and the word line WL52is shorter than the length in the y direction of the space between the word line WL11and the word line WL12. InFIG. 3, the contact VW52connecting to the word line WL52is disposed at a right end of the word line WL52.

One end of the PCM element1151is electrically connected to the bit line BL5j(j=4, . . . , 12). The other end of each of the PCM elements1154to1156is electrically connected to the word line WL51. The other end of each of the PCM elements1157to11512is electrically connected to the word line WL52.

The semiconductor memory106includes a plurality of (two inFIG. 3) word lines WL61and WL62, a plurality of (nine inFIG. 1) bit lines BL64to BL612, and a plurality of (nine inFIG. 1) PCM elements1164to11612. The word lines WL61and WL62, the PCM elements1164to11612, and the bit lines BL64to BL612are disposed at different levels in the z direction (the vertical direction inFIG. 3).

The word line WL61and the word line WL62extend in the lateral direction inFIG. 3(y direction), and separated from each other. The word line WL61and the word line WL62are disposed to be in electrical contact with the top faces of the word line WL51and the word line WL52of the semiconductor memory105, respectively. The lengths of the word line WL61and the word line WL62in the y direction are substantially the same as the lengths of the word line WL51and the word line WL52in the y direction, respectively. Thus, like the word line WL51and the word line WL52, there is a space between the word line WL61and the word line WL62. The bit lines BL64to BL612extend in the direction perpendicular to the plane ofFIG. 3(x direction). One end of each of the PCM elements1164to1166is electrically connected to the word line WL61. One end of each of the PCM elements1167to11612is electrically connected to the word line WL62. The other end of the PCM element116j(j=4, . . . , 12) is electrically connected to the bit line BL6j.

The semiconductor memory107includes a plurality of (nine inFIG. 3) bit lines BL74to BL712, a plurality of (nine inFIG. 1) PCM elements1174to11712, a plurality of (two inFIG. 3) word lines WL71and WL72. The bit lines BL74to BL712, the PCM elements1174to11712, and the word lines WL71and WL72are disposed at different levels in the z direction (the vertical direction inFIG. 3).

The bit lines BL74to BL712extend in the direction perpendicular to the plane ofFIG. 3(x direction). The bit line BL7j(j=4, . . . , 12) is arranged to be in electrical contact with the top face of the bit line BL6jof the semiconductor memory106. The word line WL71and the word line WL72extend in the lateral direction inFIG. 3(y direction), and separated from each other. In other words, there is a space between the word line WL71and the word line WL72. The word line WL71is arranged at a location that is different from the locations of the word line WL51and the word line WL61in the y direction. The word line WL72is arranged at a location that is different from the locations of the word line WL52and the word line WL62in the y direction. For example, inFIG. 3, the central portion in the y direction of the word line WL71is located above the central portion of the space between the word line WL11and the word line WL12(in the z direction). One end of the PCM element117jis electrically connected to the bit line BL7j(j=4, . . . , 12). The other end of each of the PCM elements1174to1176is electrically connected to the word line WL71. The other end of each of the PCM elements1177to11712is electrically connected to the word line WL72.

The semiconductor memory108includes a plurality of (two inFIG. 3) word lines WL81and WL82, a plurality of (nine inFIG. 3) bit lines BL84to BL812, and a plurality of (nine inFIG. 3) PCM elements1184to11812. The word lines WL81and WL82, the PCM elements1184to11812, and the bit lines BL84to BL812disposed at different levels in the z direction (the vertical direction inFIG. 3).

The word line WL81and the word line WL82extend in a lateral direction inFIG. 3(y direction), and separated from each other. The word line WL81and the word line WL82are disposed to be in electrical contact with the top faces of the word line WL71and the word line WL72of the semiconductor memory107, respectively. The lengths of the word line WL81and the word line WL82in the y direction are substantially the same as the lengths of the word line WL71and the word line WL72in the y direction, respectively. Thus, like the word line WL71and the word line WL72, there is a space between the word line WL81and the word line WL82. The bit lines BL84to BL812extend in the direction perpendicular to the plane ofFIG. 3(x direction). One end of each of the PCM elements1184to1186is electrically connected to the word line WL81. One end of each of the PCM elements1187to11812is electrically connected to the word line WL82. The other end of the PCM element118j(j=4, . . . , 12) is electrically connected to the bit line BL8j.

One end of each of three PCM elements that are not shown is electrically connected to each of the word line WL21, WL31, WL41, WL51, and WL61, and the other ends of the PCM elements are electrically connected to bit lines that are not shown. One end of each of three PCM elements that are not shown is electrically connected to each of the word lines WL72and WL82, and the other ends of the PCM elements are electrically connected to bit lines that are not shown. Thus, in the semiconductor memory device shown inFIG. 3, one end of each of six PCM elements is electrically connected to each word line. The number of PCM elements electrically connected to each word line may be more than six.

The semiconductor memory device shown inFIG. 3also includes driving circuits (for example, driving circuits10012,10032,10051,10052,10071, and10072) for driving the respective word lines, and a control circuit200for controlling the driving circuits. For example, the driving circuit10012is connected to the word line WL12through a contact VW12, the driving circuit10032is connected to the word line WL32through a contact VW32, the driving circuit10051is connected to the word line WL51through a contact VW51, and the driving circuit10052is connected to the word line WL52through a contact VW52. Since the word line WL22is arranged to be in contact with the top face of the word line WL12, it is driven by the driving circuit10012. Since the word line WL42is arranged to be in contact with the top face of the word line WL32, it is driven by the driving circuit10032. Since the word line WL61is arranged to be in contact with the top face of the word line WL51, it is driven by the driving circuit10051. Since the word line WL62is arranged to be in contact with the top face of the word line WL52, it is driven by the driving circuit10052. Since the word line WL31is arranged to be in contact with the top face of the word line WL71, it is driven by the driving circuit10071. Since the word line WL32is arranged to be in contact with the top face of the word line WL72, it is driven by the driving circuit10072.

The word lines WL11and WL31are driven by driving circuits, which are not shown, through contacts, which are not shown, either. As in the case of the contact of the word line WL12, the contact for the word line WL11is formed to electrically connect to a portion (for example a central portion) of the word line WL11. As in the case of the contact of the word line WL32, the contact for the word line WL31is formed to electrically connect to a portion (for example a left end) of the word line WL31. Since the word lines WL21and WL41are in contact with the top faces of the word lines WL11and WL31, respectively, they are driven by the aforementioned driving circuits that are not shown.

The contact VW12is formed to electrically connect to a portion (for example a central portion) of the word line WL12. The contact VW32is formed to electrically connect to an end of the word line WL32on the word line WL31side, and also to the driving circuit10032via a space between the word line WL11and the word line WL12. The bit line BL3jfor the PCM element113j(j=7 . . . , 12) connecting to the word line WL32is stacked on the bit line BL2j. As a result, the wiring resistance of this portion is lower than that of a single wiring. Therefore, the existence of the contact VW32at the end of the word line WL32does not affect the voltage drop caused by a write current or a read current.

The contact VW51is formed to electrically connect to an end (right end) of the word line WL51on the word line WL52side and also to the driving circuit10051through the space between the word line WL31and the word line WL32and the space between the word line WL11and the word line WL12. The contact VW52is formed to electrically connect to a right end of the word line WL52and also to the driving circuit10052through the space on the right side of the word lines WL42and WL32and the space on the right side of the word lines WL22and WL12. The contact VW71is formed to electrically connect to a portion (for example a central portion) of the word line WL71, and also to the driving circuit10071through the space between the word line WL51and the word line WL52, the space between the word line WL31and the word line WL32, and the space between the word line WL11and the word line WL12. The contact VW72is formed to electrically connect to a portion (for example a central portion) of the word line WL71and also to the driving circuit10072through the space on the right side of the word line WL52, the space on the right side of the word line WL32, and the space on the right side of the word line WL12. The control circuit200also controls bit lines connected to PCM elements to be accessed.

As in the first embodiment, each driving circuit includes a p-channel transistor and an n-channel transistor connected in series. The gate of each of the series-connected p-channel transistor and n-channel transistor is connected to the control circuit200. An intermediate node (connection node) of the series-connected transistors is electrically connected to a central portion of the corresponding word line. Each of the driving circuits supplies a write current or a read current via the corresponding word line to the PCM element to be accessed. Each of the PCM elements has the same structure as that of the first embodiment.

As described above, the semiconductor memory device according to the second embodiment has a structure in which the contact VW71electrically connected to the word line included in the uppermost semiconductor memory108is also electrically connected to the corresponding driving circuit10071through the space between adjacent word lines of each of the semiconductor memories106,105,104,103,102, and101, which are arranged two or more levels below the uppermost semiconductor memory. Each of the contacts electrically connected to one of the word lines included in any of the semiconductor memories106,105,104, and103arranged at the third or higher level is electrically connected to the corresponding driving circuit through the space between the word lines included in the semiconductor memory101disposed at the first level, or the space on the right or left side of the corresponding word line included in the semiconductor memory101arranged on the first layer, which is disposed at substantially the same position as the word line to which the contact is electrically connected.

Thus, the contact VW71, for example, for connecting one of the word lines included in the eighth semiconductor memory108, for example the word line WL81, and the driving circuit10071located at the lowermost level, does not contact the word lines included in the first to sixth semiconductor memories101to106. Therefore, it is not necessary to divide the word lines of the semiconductor memories located below the eighth semiconductor memory108. As a result, an increase in chip size may be prevented.

Third Embodiment

FIG. 4shows a semiconductor memory device according to a third embodiment. The semiconductor memory device according to the third embodiment has a structure obtained by sequentially stacking a cross-point semiconductor memory101, a cross-point semiconductor memory102, a cross-point semiconductor memory103, and a cross-point semiconductor memory104. In the following descriptions, each memory cell of the respective semiconductor memories has a resistive change element serving as a storage element. The resistive change element is a PCM element in the following descriptions, but not limited thereto.

The semiconductor memory101includes a plurality of (nine inFIG. 4) bit lines BL14to BL112, a plurality of (nine inFIG. 4) PCM elements1114to11112, a plurality of (two inFIG. 4) word lines WL11and WL12. The bit lines BL14to BL112, the PCM elements1114to11112, and the word lines WL11and WL12are disposed at different levels in a z direction (the vertical direction inFIG. 4).

The bit lines BL14to BL112extend in a direction perpendicular to the plane ofFIG. 4(x direction). The word line WL11and the word line WL12extend in a lateral direction inFIG. 4(y direction), and separated from each other. In other words, there is a space between the word line WL11and the word line WL12. One end of the PCM element111jis electrically connected to the bit line BL1j(j=4, . . . , 12). The other end of each of the PCM elements1114to1116is electrically connected to the word line WL11. The other end of each of the PCM elements1117to11112is electrically connected to the word line WL12.

The semiconductor memory102includes a plurality of (two inFIG. 4) word lines WL21and WL22, a plurality of (nine inFIG. 4) bit lines BL24to BL212, and a plurality of (nine inFIG. 4) PCM elements1124to11212. The word lines WL21and WL22, the PCM elements1124to11212, and the bit lines BL24to BL212are disposed at different levels in the z direction (the vertical direction inFIG. 4).

The word line WL21and the word line WL22extend in the lateral direction inFIG. 4(y direction), and separated from each other. The word line WL21and the word line WL22are disposed to be in electrical contact with the top faces of the word line WL11and the word line WL12of the semiconductor memory101, respectively. The lengths of the word line WL21and the word line WL22in the y direction are substantially the same as the lengths of the word line WL11and the word line WL12in the y direction, respectively. Thus, like the word line WL11and the word line WL12, there is a space between the word line WL21and the word line WL22. The bit lines BL24to BL212extend in the direction perpendicular to the plane ofFIG. 4(x direction). One end of each of the PCM elements1124to1126is electrically connected to the word line WL21. One end of each of the PCM elements1127to11212is electrically connected to the word line WL22. The other end of the PCM element112j(j=4, . . . , 12) is electrically connected to the bit line BL2j.

The semiconductor memory103includes a plurality of (nine inFIG. 4) bit lines BL34to BL312, a plurality of (nine inFIG. 4) PCM elements1134to11312, and a plurality of (two inFIG. 4) word lines WL31and WL32. The bit lines BL34to BL312, the PCM elements1134to11312, and the word lines WL31and WL32are disposed at different levels in the z direction (the vertical direction inFIG. 4).

The bit lines BL34to BL312extend in the direction perpendicular to the plane ofFIG. 4(x direction). The bit line BL3j(j=4, . . . , 12) is arranged to be in electrical contact with the top face of the bit line BL2jof the semiconductor memory102. The word line WL31and the word line WL32extend in the lateral direction inFIG. 4(y direction), and separated from each other. In other words, there is a space between the word line WL31and the word line WL32.

The word line WL31is arranged at a different location from the word line WL11and the word line WL21in the y direction, and the word line WL32is arranged at a different location from the word line WL12and the word line WL22. For example, inFIG. 4, a central portion in the y direction of the word line WL31is located above (z direction) a central portion of the space between the word line WL11and the word line WL12. One end of the PCM element113jis electrically connected to the bit line BL3j(j=4, . . . , 12). The other end of each of the PCM elements1134to1136is electrically connected to the word line WL31. The other end of each of the PCM elements1137to11312is electrically connected to the word line WL32.

The semiconductor memory104includes a plurality of (two inFIG. 4) word lines WL41and WL42, a plurality of (nine inFIG. 4) bit lines BL44to BL412, and a plurality of (nine inFIG. 4) PCM elements1144to11412. The word lines WL41and WL42, the PCM elements1144to11412, and the bit lines BL44to BL412are disposed at different levels in the z direction (the vertical direction inFIG. 4).

The word line WL41and the word line WL42extend in the lateral direction inFIG. 4(y direction), and separated from each other. The word line WL41and the word line WL42are disposed to be in electrical contact with the top faces of the word line WL31and the word line WL32of the semiconductor memory103, respectively. The lengths of the word line WL41and the word line WL42in the y direction are substantially the same as the lengths of the word line WL31and the word line WL32in the y direction, respectively. Thus, like the word line WL31and the word line WL32, there is a space between the word line WL41and the word line WL42. The bit lines BL44to BL412extend in the direction perpendicular to the plane ofFIG. 4(x direction). One end of each of the PCM elements1144to1146is electrically connected to the word line WL41. One end of each of the PCM elements1147to11412is electrically connected to the word line WL42. The other end of the PCM element114j(j=4, . . . , 12) is electrically connected to the bit line BL4j.

One end of each of three PCM elements that are not shown is electrically connected to each of the word lines WL11and WL21, and the other ends of the PCM elements are electrically connected to bit lines that are not shown. One end of each of three PCM elements that are not shown is electrically connected to each of the word lines WL32and WL42, and the other ends of the PCM elements are electrically connected to bit lines that are not shown. Thus, in the semiconductor memory device shown inFIG. 4, one end of each of six PCM elements is electrically connected to each word line. The number of PCM elements electrically connected to each word line may be more than six.

The semiconductor memory device according to the third embodiment shown inFIG. 4also includes driving circuits (for example, driving circuits10012,10031,10032) for driving the respective word lines, and a control circuit200for controlling the driving circuits. For example, the driving circuit10012is connected to the word line WL12through a contact VW12, the driving circuit10031is connected to the word line WL31through a contact VW31, and the driving circuit10032is connected to the word line WL32through a contact VW32. Since the word line WL22is arranged to be in contact with the top face of the word line WL12, it is driven by the driving circuit10012. Since the word line WL41is arranged to be in contact with the top face of the word line WL31, it is driven by the driving circuit10031. Since the word line WL42is arranged to be in contact with the top face of the word line WL32, it is driven by the driving circuit10032. The word line WL11is driven by a driving circuit, which is not shown, through a contact that is not shown, either. As in the case of the contact of the word line WL12, the contact for the word line WL11is formed to electrically connect to a portion (for example a central portion) of the word line WL11. Since the word line WL21is arranged to be in contact with the top face of the word line WL11, the word line WL21is driven by the driving circuit that is not shown.

The contact VW12is formed to electrically connect to a portion (for example a central portion) of the word line WL12. The contact VW31is formed to electrically connect to a portion (for example a central portion) of the word line WL31, and also to the driving circuit10031through the space between the word line WL11and the word line WL12. The contact VW32is formed to electrically connect to a portion (for example a central portion) of the word line WL32, and also to the driving circuit10032through a space on the right side of the word line WL22. The control circuit200also controls bit lines connected to PCM elements to be accessed.

Each driving circuit includes a p-channel transistor and an n-channel transistor connected in series. The gate of each of the series-connected p-channel transistor and n-channel transistor is connected to the control circuit200. An intermediate node (connection node) of the series-connected transistors is electrically connected to a central portion of the corresponding word line. Each of the driving circuits supplies a write current or a read current via the corresponding word line to the PCM element to be accessed.

According to the third embodiment, the contact VW31for example, is electrically connected to the driving circuit for the fourth semiconductor memory104, for example the driving circuit10031, through a space between the word line WL21and the word line WL22of the second semiconductor memory102, and a space between the word line WL11and the word line WL12of the first semiconductor memory101. Furthermore, the contact VW32is electrically connected to the driving circuit10032through a space on the right side of the word line WL22of the second semiconductor memory102and a space on the right side of the word line WL12of the first semiconductor memory101.

Thus, the contact VW31electrically connected to the word line included in the uppermost semiconductor memory104(for example, the word line WL41) is also electrically connected to the corresponding driving circuit10031through the space between adjacent word lines of each of the semiconductor memories102and101arranged two or more levels below the uppermost semiconductor memory. The contact VW32electrically connected to the word line WL42is electrically connected to the driving circuit10032through a space on the right side of the word line WL22included in the second semiconductor memory102and the word line WL12included in the first semiconductor memory101.

Thus, the contact VW31, for example, for connecting one of the word lines included in the fourth semiconductor memory104, for example the word line WL41, and the driving circuit10031located at the lowermost level, does not contact the word lines included in the first and the second semiconductor memories101and102. Therefore, it is not necessary to divide the word lines of the semiconductor memories located below the fourth semiconductor memory104. As a result, an increase in chip size may be prevented.