Phase comparison circuit arrangement

A phase comparison circuit for producing an output signal which is a measure of the phase difference between first (A) and second (B) pulse trains applied to respective first and second inputs thereof. The circuit is immune to the omission of a pulse from one of the trains and to pulse length inequality in the two trains. It comprises a logic circuit, two switchable current sources connected to a capacitor (17), a switchable constant voltage source, i.e. a controllable switch (18) connected to the capacitor, and a sampling circuit connected to the capacitor. The logic circuit generates four output signals that control the first current source, the second current source, the constant voltage source, and the sampling circuit respectively so that the charge on the capacitor is changed in a positive sense by the first current source when a pulse of the first train is present while a pulse of the second train is absent and in the other sense by the second current source when a pulse of the second train is present while a pulse of the first train is absent. The capacitor charge is restored to a reference value (zero) by the constant voltage source when pulses of both trains are absent simultaneously. The sampling circuit samples the capacitor voltage when pulses of both trains are present simultaneously.

The invention relates to a phase comparison circuit arrangement constructed 
to generate at an output thereof a signal which is a measure of the phase 
difference between first and second pulse trains applied to first and 
second inputs thereof, respectively. 
In a known phase comparison circuit arrangement of this kind, a ramp 
generator is started by each pulse of the second pulse train. A pulse of 
the first pulse train which appears during the generation of a ramp in 
response to the occurrence of a pulse of the second pulse train causes a 
sampling circuit to sample the output signal of the generator and the 
value of the sample obtained is a measure of the time difference between 
the two pulses and hence of the instantaneous phase difference between the 
two pulse trains. In order to enable the phase difference to be determined 
also when the pulses of the first pulse train lead those of the second 
pulse train (negative phase), the pulses of the first pulse train are 
applied to the sampling circuit after having been delayed by a period of 
time which corresponds to half the nominal period of the second pulse 
train. When the phase difference equals zero, the value of the sample 
taken by the sampling circuit corresponds to the value of the generated 
sawtooth halfway through a period of the sawtooth. 
This known phase comparison circuit has the drawback that the accuracy with 
which phase differences around zero can be determined is determined by the 
accuracy with which the aforesaid delay is equal to a half-period of the 
sawtooth. Moreover, if this delay is fixed, the phase comparison circuit 
only operates satisfactorily when the pulse trains have a particular 
frequency, because deviations from this frequency give rise to changes in 
the values of the samples obtained when the phase difference is equal to 
zero. 
The invention has for an object to provide a phase comparison circuit 
arrangement of the kind set forth in the opening paragraph which need not 
have these drawbacks. 
The invention provides a phase comparison circuit arrangement constructed 
to generate at an output thereof a signal which is a measure of the phase 
difference between first and second pulse trains applied to first and 
second inputs thereof, respectively. The arrangement comprises first and 
second activatable current sources having their outputs connected to said 
capacitor, an activatable constant voltage source connected to said 
capacitor, a sampling circuit having an input to which said capacitor is 
connected, and a control circuit having inputs to which said first and 
second inputs are coupled and outputs which are coupled to activation 
signal inputs of said current sources, said constant voltage source and 
said sampling circuit. The constant voltage source is constructed to 
produce, when activated, an output voltage which lies between the 
open-circuit output voltages of said first and second current sources and 
said control circuit is constructed to respond to the application of first 
and second pulse trains to said first and second inputs respectively by 
(a) activating said first current source for periods when a pulse of the 
first pulse train is present while a pulse of the second pulse train is 
absent, (b) activating said second current source for periods when a pulse 
of the second pulse train is present while a pulse of the first series is 
absent, (c) activating said constant voltage source each time a pulse of 
the first pulse train is absent while a pulse of the second pulse train is 
absent, and (d) activating said sampling circuit each time a pulse of the 
first pulse train is present while a pulse of the second pulse train is 
present. 
Statements concerning the presence or absence of a pulse in a given pulse 
series are used herein merely to distinguish between times when the 
relevant signal has one of its two possible levels and times when it has 
the other of these levels. Thus the relevant signal may have either a 
higher or a lower actual level when a pulse is "present" therein than it 
has when such a pulse is absent. 
The output voltage of one of the three said sources may be zero. 
Such an arrangement need not incorporate either a delay device or a ramp 
generator, so that the aforesaid drawbacks need not occur. Moreover, such 
an arrangement is not susceptible to variations in the frequency of the 
two pulse trains. Furthermore, its correct operation need not be disturbed 
by the occasional omission of pulses from one or both of the pulse trains.

FIG. 1 shows a known phase comparison circuit which has a first input 1 and 
a second input 2 for receiving first (A) and second (B) pulse trains, 
respectively. In a motor control system, for example, the pulse series B 
may be a reference pulse series and the pulse series A may be a pulse 
series originating from a tachogenerator. The input 2 is connected to a 
ramp generator 3 which is reset each time a pulse appears at the input 2. 
The input 1 is connected via a delay network 6, which produces a delay 
equal to half the nominal period of the sawtooth V.sub.S appearing at the 
output of ramp generator 3 when the pulse series B is applied to the input 
2, to the control input of a (preferably electronic) switch 4 which 
briefly connects a sampling capacitor 5 to the output of the ramp 
generator 3 each time a pulse appears. The voltage on the capacitor 5 is 
fed to an output 7. 
The operation of the circuit shown in FIG. 1 is as follows. A pulse of the 
pulse series B applied to the input 2 starts the generation of a voltage 
ramp. When the switch 4 is briefly closed at a given instant due to the 
appearance at its control input of a pulse of the pulse series A which 
occurred at input 1 a period of time equal to the delay produced by the 
network 6 before this instant, the voltage across the capacitor 5 and 
hence at the output 7 becomes equal to the value of the ramp at this 
instant. This value is linearly proportional to the time difference 
between the instant at which the ramp started and the instant at which its 
value is sampled. This time difference minus the delay produced by the 
network 6 is proportional to the phase difference between the pulse series 
A and B, the value of the sawtooth being sampled halfway through each 
period thereof if this phase difference is equal to zero, provided that 
the delay produced by the network 6 corresponds to exactly half this 
period. 
In the embodiment of the invention shown in FIG. 2, a phase comparison 
circuit comprises a logic gate circuit 12 having inputs 1 and 2 to which 
the pulse series A and B, respectively, are applied. The gate circuit 12 
has outputs 8, 9, 10 and 11 at which signals C, D, E and F, respectively, 
occur in operation, where these signals are given in terms of the signals 
A and B by the following logic relations: 
C=A.B. 
D=A.B. 
E=A.B. 
F=A.B. 
The circuit furthermore comprises a capacitor 17 across which a signal G 
occurs in operation. This capacitor 17 is connected, via a switch 13 which 
is controlled by the signal C, and a resistor 15, to a terminal carrying a 
positive voltage +V.sub.B, and via a switch 14, controlled by the signal 
E, and a resistor 16, to a terminal carrying a negative voltage -V.sub.B. 
The combinations 13, 15, +V.sub.B and 14, 16, -V.sub.B thus constitute 
first and second activatable (switchable) current sources, respectively. A 
switch 18 which is controlled by the signal D is connected in parallel 
with the capacitor 17. Switch 18 effectively constitutes an activatable 
(switchable) constant voltage source the output voltage of which is zero. 
The voltage G across the capacitor 17 can be sampled in that the capacitor 
17 is connected, via a switch 4 which is controlled by the signal F, to an 
output 7 to which a sampling capacitor 5 is connected. A voltage H occurs 
across the latter capacitor in operation. All the switches 4, 13, 14 and 
18 are closed when their respective control signals are logic " 1" and are 
open otherwise. 
FIG. 3 shows the time relation between the signals A to H for two different 
situations, i.e. a situation where the pulse series A leads the pulse 
series B, and the situation where the pulse series B leads the pulse 
series A. 
If the leading edge of the pulse of the pulse series A occurs at the 
instant t.sub.1, the signal C becomes high (logic "1") until the leading 
edge of a pulse of the pulse series B occurs at the instant t.sub.2, at 
which instant the signal C becomes low again. During the period between 
t.sub.1 and t.sub.2, therefore, the capacitor 17 is connected, via the 
switch 13 and the resistor 15, to the positive voltage +V.sub.B, and the 
voltage G across the capacitor 17 increases (from zero) to a value 
determined by the time difference t.sub.2 -t.sub.1 and hence by the phase 
difference between the pulse series A and B. Between the instant t.sub.2 
and the instant t.sub.3 at which the trailing edge of the pulse of the 
series A occurs, the signal F is high and the switch 4 is therefore closed 
so that the capacitor 5 is charged to the level of the voltage G across 
the capacitor 17, provided that its capacitance is negligibly small with 
respect to the capacitance of the capacitor 17. Between the instant 
t.sub.3 and the instant t.sub.4 at which the trailing edge of the pulse 
series B occurs, the signal E is high and the capacitor 17 is therefore 
connected, via the switch 14 and the resistor 16, to the negative voltage 
-V.sub.B, so that the capacitor 17 discharges. If the widths of the pulses 
of the series A and B are equal, the values of the resistors 15 and 16 are 
equal, and the voltages +V.sub.B and -V.sub.B are equal, the capacitor 17 
discharges to substantially the original level (zero). Between the 
instants t.sub.4 and t.sub.5, the signal D is high due to the absence of 
pulses on the inputs 1 and 2 so that the capacitor 17 is short-circuited 
via the switch 18, with the result that any remaining charge on the 
capacitor 17 is removed and the voltage thereacross becomes exactly equal 
to zero. 
Similar operations occur at the instants t.sub.6 to t.sub.10 as occur at 
the instants t.sub.1 to t.sub.5. However, because the signal B now leads 
the signal A, the capacitor 17 is charged in a negative sense between the 
instants t.sub.6 and t.sub.7 rather than in a positive sense, so that a 
negative value of the signal G is sampled between the instants t.sub.7 and 
t.sub.8. The capacitor 17 is subsequently discharged between the instants 
t.sub.8 and t.sub.9. 
The sampling under the control of the signal F offers the advantage that, 
if a pulse of the pulse series A or B is omitted, no sample is taken 
preventing an incorrect value from being sampled. 
The resetting of the charge on the capacitor 17 to zero by means of the 
switch 18 offers the advantage that any inequality between the widths of 
the pulses of the pulse series A and B, between the values of the 
resistors 15 and 16, and between the values of the voltages +V.sub.B and 
-V.sub.B will not result in a residual voltage occurring across the 
capacitor 17 at the end of each cycle of operation, which voltage would 
influence the value of the sample taken during the next cycle. This 
resetting also prevents such a residual voltage from occurring if a pulse 
of the signal A or B should be missing. 
The circuit shown in FIG. 2 can be improved in many respects, if desired, 
although at the expense of simplicity. For example, in order to improve 
the linearity of the relationship between the voltage produced across the 
capacitor 17 and the time during which the switch 13 or 14 is closed, the 
resistors 15 and 16 together with the switches 13 and 14 can be replaced 
by switched constant current sources. Moreover, in order to prevent the 
sampling capacitor 5 from loading the capacitor 17 during the sampling 
operations, a buffer amplifier may be included between the capacitor 17 
and the capacitor 5. 
FIG. 4 shows how the circuit shown in FIG. 2 can be realized using an 
integrated circuit available under the Philips type number HEF 4052B, 
which integrated circuit is described in Philips Datahandbook, 
Semiconductors and Integrated Circuits, Part 6, October 1977. Pins 1 to 5 
of the integrated circuit are not used, pins 6, 8 and 12 are connected to 
ground, pin 7 is connected to the negative supply voltage -V.sub.B, pin 16 
is connected to the positive supply voltage +V.sub.B, pin 15 is connected, 
via the resistor 16, to the negative supply voltage -V.sub.B, pin 14 is 
connected, via the resistor 15, to the positive supply voltage +V.sub.B, 
pin 13 is connected to ground via the capacitor 17, pin 11 is connected to 
the output 7 and, via the capacitor 5, to ground, pin 10 is connected to 
the input 2, and pin 9 is connected to the input 1. If desired, the phase 
comparison circuit shown in FIG. 4 can be deactivated by switching the pin 
6 from ground to +V.sub.B by means of a switch (not shown).