Image sensor with contact dummy pixels

An image sensor array includes a substrate layer, a metal layer, an epitaxial layer, a plurality of imaging pixels, and a contact dummy pixel. The metal layer is disposed above the substrate layer. The epitaxial layer is disposed between the substrate layer and the metal layer. The imaging pixels are disposed within the epitaxial layer and each include a photosensitive element for collecting an image signal. The contact dummy pixel is dispose within the epitaxial layer and includes an electrical conducting path through the epitaxial layer. The electrical conducting path couples to the metal layer above the epitaxial layer.

TECHNICAL FIELD

This disclosure relates generally to image sensors, and in particular but not exclusively, relates to back-side illuminated image sensors.

BACKGROUND INFORMATION

In standard CMOS image sensors (CIS), such as front-side illuminated devices, the CIS and controlling circuitry are formed on the surface of a p-type doped epitaxial (“epi”) silicon layer formed on a p-type doped silicon substrate, which is typically highly p-type doped and has relatively low resistance. Back-side illuminated (BSI) CMOS image sensors however have the majority of the underlying silicon removed, which increases the substrate resistance across the array. Performance problems associated with increased substrate resistance are therefore more problematic in BSI devices. Other thin substrate devices such as those fabricated on Silicon On Insulator (SOI) substrates or those incorporating buried collector layers may also have similar problems. One method of solving this problem is to create a substrate contact in each imaging pixel. Such a solution involves additional well and contact doping implants, as well as additional metal contacts and metal routing in each pixel. For very large pixel structures (i.e. larger than 4 μm) the additional layers and metal routing may not be a concern. However for smaller, more advance device structures, this solution reduces the photodiode fill factor, which degrades many of its performance parameters such as sensitivity and full well capacity. A technique that provides adequate pixel grounding across the pixel array in larger arrays with smaller pixels is desirable to prevent performance problems in BSI devices.

DETAILED DESCRIPTION

FIG. 1illustrates two neighboring CMOS image sensors (CIS) pixels100formed within a p-type doped epi layer140disposed over a p-type doped silicon substrate105. When a photo-generated charge carrier is formed shallow within pixel100(e.g., charge carrier150), it experiences a strong upward attractive force (shown by the arrows145) towards a photo-sensor or photodiode (“PD”) region115, due to a depletion region or P-N junction between PD region115and the underlying p-type doped epi layer140. In the illustrated embodiment, a p-type doped pinning layer135overlays PD regions115to passivate their surfaces. CIS pixels100are separated by Shallow Trench Isolation (STI) regions160which are disposed within p-type doped wells130. CIS pixels100includes pixel circuitry (not shown) disposed adjacent to PD region115within a P doped well (not shown). Such pixel circuitry provides a variety of functionality for regular operation of CIS pixel100. For example, such pixel circuitry may include circuitry to commence acquisition of an image charge within PD region115, to reset the image charge accumulated within PD region115, to ready CIS pixel100for the next image, or to transfer out the image data acquired by CIS pixel100. When substrate105is made very thin such as in the case of a Back Side Illuminated (BSI) CIS, and when the number of pixels is made very large, the lateral electrical resistance within substrate105may become relatively large and reduce performance of the pixel array.

FIG. 2is a cross sectional view of a portion of a BSI CIS including two neighboring pixels: an imaging pixel200and a contact dummy pixel270, in accordance with an embodiment of the invention. The illustrated embodiment of pixels200and270include a thinned substrate205, a p-type doped epi layer240, and PD region215. Pixels200and270are formed into an array with other pixels200and270that are not shown. The photo-sensitive or PD regions215of each imaging pixel200are isolated from each other and from contact dummy pixels270with shallow trench isolations (“STI”)260and dopant wells230(e.g., P-wells). In the illustrated embodiment, a p-type doped pinning layer235overlays PD regions215to passivate their surfaces.

Contact dummy pixel270is different from imaging pixel200in that it contains a doped connecting well280for making electrical contact to substrate205. Contact dummy pixels270will in general not have a PD region215and will not be available for image collection. Instead doped connecting well280is located in the area normally reserved for PD regions215and extends down to substrate205. Doped connecting well280is doped to have the same conductivity type as substrate205(e.g., p-type). Additionally, a p-type doped contact285(e.g., same as logic P source/drain) may be included within doped connecting well280to form an electrical contact to metal layer M-1. In one embodiment, metal layer M-1is coupled to circuit ground and provides frontside grounding contact to substrate205via doped connecting well280. Additional metal contacts and routing are not shown since these layers are layout dependent. In one embodiment, metal layer M-1may be coupled to a plurality of contact dummy pixels280dispersed throughout a pixel array to provide multiple grounding points to substrate205thereby reducing its lateral resistance. Thus, doped connecting wells280acts as an electrical conducting path connecting metal layer M-1to substrate205through epitaxial layer240. WhileFIG. 2illustrates doped connecting well280being coupled to metal layer M-1, in other embodiments, it may be coupled to any of the metal layers disposed over the frontside of the image sensor.

One advantage of this approach is that the individual PD region fill factor (the ratio of the PD region area to the entire pixel area) of imaging pixels200remains unchanged, so the performance of each pixel is unchanged. All of the layers in contact dummy pixel270(p-well implant, p-contact, metal1contact, etc) are already present in a standard CIS fabrication process. The number of such contact dummy pixels270is small in comparison to the total number of pixels in a pixel array, for example, there may be one per every 1000 imaging pixels200. Placement as well as number of contact dummy pixels270depends on parameters such as the final substrate resistance (final silicon thickness), the physical size of the array, and the number of pixels. The total array sensing area is not significantly reduced by the total number of these “dummy” pixels. They will not significantly impact the total active pixel count. In addition, already established and applied methods of averaging out white or dead pixels in any CIS device will also remove the impact of the contact-dummy pixels from the final image. Therefore the final image will not significantly be altered by contact dummy pixels270.

FIG. 2also shows an embodiment in which an electron collector290is incorporated into contact dummy pixel270. Photo-electron hole pairs may form in contact dummy pixels270and may interfere with image collection in adjacent imaging pixels200. The holes can drain out of the p-type wells, which are typically grounded, but the photo-electrons may not be drained out of the dummy pixels. The embodiment ofFIG. 2illustrates contact dummy pixels270with an additional n-type contact295. This contact is formed with a n-type implant and a contact to metal layer M-2(or any other metal layer). The n-type implant can be the standard CMOS logic N+ source/drain implant, and may also include the n-type photo-diode implants to increase the depth of this electron collection region (not shown). This n-type electron collector can be biased with a bias voltage VBIAS>0 (such as VDD) coupled via metal layer M-2.

In one embodiment, dopant wells230are p-type doped wells for isolating adjacent PD regions215and for preventing direct interface between STI260and PD regions215. However, it should be appreciated that the conductivity types of all the elements can be swapped such that substrate205is n-type doped, epi layer240is n-type doped, PD regions215are p-type doped, and dopant wells230and280are n-type doped.

FIG. 3illustrates how a contact dummy pixel can be applied to a vertical overflow drain (VOD) structure of a BSI CIS pixel architecture, in accordance with an embodiment of the invention. In the illustrated embodiment, the upper layers (epitaxial layer340, PD region315, P wells330, etc.) are isolated from a bulk p-type substrate305by a buried VOD, which includes doped connecting well380and collector layer310. Contact dummy pixel370provides an electrical conducting path from the frontside region, through epitaxial layer240, down to collector layer310. The illustrated embodiment of imaging pixel300includes a substrate305, an epitaxial (“epi”) layer307, a collector layer310, a barrier layer312, an epi layer340, and a PD region315. The PD regions315of each imaging pixel300are isolated from each other with shallow trench isolations (“STI”)360and P wells330. In the illustrated embodiment, a p-type doped pinning layer335overlays PD regions315to passivate their surfaces. Contact dummy pixel370includes an doped connecting well380(e.g., deep N-well) for making electrical connection between collector layer310and above metal interconnect layers (e.g., metal layer M-2) used to conduct charge out of collector layer310. An n-type doped contact385may be present to form a low resistance connection between a metal interconnect layer and doped connecting well380. Contact dummy pixels370may also contain a laterally extended version of dopant well330(e.g., wider than corresponding dopant wells separating adjacent imaging pixels) with a p-type doped contact395for making electrical contact to a metal interconnect layer (e.g., metal layer M-1). The number and placement of contact dummy pixels370may be similar to those for an image sensor array including contact dummy pixels270ofFIG. 2.

In one embodiment, substrate305, epitaxial layer307, barrier layer312, epitaxial layer340, doped wells330, and pinning layer335are all p-typed doped (though not necessarily to the same concentration), while collector layer310, doped connecting well380, and PD region315are n-type doped (though not necessarily to the same concentration. Of course, in other embodiments, the conductivity types may be swapped.

FIG. 4is a block diagram illustrating an imaging system400, in accordance with an embodiment of the invention. The illustrated embodiment of imaging system400includes an image sensor array405, readout circuitry410, function logic415, and control circuitry420. Image sensor array405is a two-dimensional (“2D”) array of imaging pixels (e.g., pixels P1, P2. . . , Pn) having improved performance characteristics and contact dummy pixels470. Contact dummy pixels470may be implemented with either contact dummy pixels270or370. In one embodiment, image sensor array405is a color filter array including a color pattern (e.g., Bayer pattern or mosaic) of red, green, and blue filters. As illustrated, each pixel is arranged into a row (e.g., rows R1to Ry) and a column (e.g., column Cl to Cx) to acquire image data of a person, place, or object, which can then be used to render a 2D image of the person, place, or object. When contact dummy pixels470are implemented as contact dummy pixels270, substrate grounding is improved and lateral resistance across image sensor array405is reduced thereby improving image sensor performance characteristics. When contact dummy pixels470are implemented as contact dummy pixels370, the VOD operates as an anti-blooming structure that reduces overflow induced cross-talk.

During operation, after each imaging pixel has acquired its image data or image charge, the image data is readout by readout circuitry410and transferred to function logic415. Readout circuitry410may include amplification circuitry, analog-to-digital (“ADC”) conversion circuitry, or otherwise. Function logic415may simply store the image data or even manipulate the image data by applying post image effects (e.g., crop, rotate, remove red eye, adjust brightness, adjust contrast, or otherwise). In one embodiment, readout circuitry410may readout a row of image data at a time along readout column lines (illustrated) or may readout the image data using a variety of other techniques (not illustrated), such as a column/row readout, a serial readout, or a full parallel readout of all pixels simultaneously. Control circuitry420is coupled to image sensor array405to control operational characteristic of image sensor array405. For example, control circuitry420may generate a shutter signal for controlling image acquisition. In one embodiment, the shutter signal is a global shutter signal for simultaneously enabling all pixels within image sensor array405to simultaneously capture their respective image data during a single acquisition window. In an alternative embodiment, the shutter signal is a rolling shutter signal whereby each row, column, or group of pixels is sequentially enabled during consecutive acquisition windows.

The above description of illustrated embodiments of the invention is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.