Method and system for fabricating semiconductor components with lens structures and lens support structures

A method for fabricating semiconductor components with lens structures and lens support structures includes the steps of providing semiconductor substrates on a substrate, attaching a carrier to the substrate configured to support the substrate during various processes, thinning the carrier to form lens support structures having desired geometrical characteristics, singulating the substrate and the carrier such that each semiconductor substrate includes a lens support structure, and then attaching the lens structures to the support structures. Each semiconductor component includes a thinned semiconductor substrate, a support structure attached to the semiconductor substrate, and a lens structure attached to the support structure. A system for fabricating the semiconductor components includes the substrate containing the semiconductor substrates, and the carrier configured to support the wafer, to protect the semiconductor substrates and to provide the lens support structures.

BACKGROUND

Some types of semiconductor components require a lens structure, and an associated lens support structure. For example, image sensor semiconductor components utilize a lens structure to cover and protect radiation sensitive integrated circuits, and to focus light radiation onto these integrated circuits. Typically, the lens structure comprises an optically transmissive glass or plastic material configured to focus light radiation onto the radiation sensitive integrated circuits. In addition, the lens structure can include multiple lenses, or may be combined with another optically transmissive element, such as a package lid.

One consideration in the manufacture of image sensor semiconductor components is the process by which the lens structures are attached to the semiconductor dice containing the radiation sensitive integrated circuits. Wafer level packaging (WLP) is a preferred method of packaging semiconductor components because it produces smaller form factors, higher output and lower cost devices. However, applying wafer level packaging to image sensor semiconductor components has proven to be difficult. Currently, the lens structures and the lens support structures are separate components that are often bulky, and must be attached at the die level following singulation of the wafer.

It would be advantageous to have a wafer level packaging method for fabricating the lens structures and the lens support structures of image sensor semiconductor components. Accordingly, the microelectronics and imaging industries are currently seeking methods to fabricate image sensor semiconductor components at the wafer level in order to reduce processing steps, lower costs, and reduce package dimensions.

US Patent Application Publication 2006/0035415A1 to Wood et al. discloses an exemplary wafer level fabrication process for image sensor semiconductor components. In the Wood et al. process, a frame structure includes an array of frames for mounting lenses or other elements of the image sensor components. The frame structure can be attached to a wafer, and aligned using skirts on the frame structure that mate with kerfs in the wafer. The frame structure and the wafer can then be singulated into individual image sensor components.

One consideration in the fabrication of image sensor semiconductor components is the fragility of the radiation sensitive integrated circuits contained on the semiconductor dice. During wafer processing these integrated circuits, as well as other elements contained on the dice, must be protected from damage. In addition, the semiconductor industry is moving towards chip scale packages that utilize thinned semiconductor dice. It would be advantageous for a fabrication method for image sensor semiconductor components to be capable of handling thinned semiconductor dice.

Another consideration in the fabrication of image sensor semiconductor components is the construction of the lens structures, and associated lens support structures. It is necessary for the lens structure and the lens support structures to protect the integrated circuits, and to provide desired optical characteristics as well. It is also advantageous for the lens structures and the lens support structures to be capable of providing electrical paths for various electrical elements of the components, such as MEMS (microelectricalmechanical system) devices used for autofocusing, and lens manipulation.

The method to be hereinafter described is directed to a wafer level fabrication method for image sensor semiconductor components, which addresses the above noted considerations. In addition, improved image sensor semiconductor components, and improved systems for fabricating image sensor semiconductor components will be hereinafter described.

DETAILED DESCRIPTION

As used herein, “semiconductor component” means an electronic element that includes a semiconductor substrate or makes contact with a semiconductor substrate. “Semiconductor substrate” means an electronic element, such as a semiconductor die, or a semiconductor package that includes integrated circuits and semiconductor devices. A “semiconductor wafer” means a substrate or portion thereof containing a plurality of semiconductor substrates or packages. “Wafer-level” means a process conducted on an element, such as a semiconductor wafer, containing multiple semiconductor components or substrates. “Die level” means a process conducted on a singulated element, such as a singulated semiconductor die or package. “Chip scale” means having an outline about the same as that of a semiconductor substrate. “Wafer size” means having an outline about the same as that of a semiconductor wafer. “Interconnect” means an electrical element which electrically connects different electrical elements and transmits signals between these elements.

Referring toFIGS. 1A-1G,FIGS. 2A-2BandFIGS. 3A-3B, a method for fabricating image sensor semiconductor components10(FIG. 1G) with lens structures12(FIG. 1G), and lens support structures26S (FIG. 1G) is illustrated. Initially, as shown inFIG. 1A, a semiconductor substrate14can be provided. By way of example, the semiconductor substrate14can comprise an image sensor die (or an image sensor package) having an imager pixel array16, and a plurality of integrated circuits18in the imager pixel array16and on other portions of the semiconductor substrate14as well. The integrated circuits18can include radiation sensitive integrated circuits in the pixel array, such as complimentary metal oxide semiconductor (CMOS) devices. The integrated circuits18can also include other types of integrated circuits outside of the imager pixel array16for processing image data. Rather than being an image sensor die (or image sensor package), the semiconductor substrate14can comprise another type of semiconductor die or package which requires a lens structure and a lens support structure (e.g., solar sensor).

As shown inFIG. 2A, the semiconductor substrate14is initially contained on a semiconductor wafer20, which includes a plurality of substantially identical semiconductor substrates14. Although a semiconductor wafer20is illustrated, it is to be understood that the method can be performed on any substrate which contains multiple semiconductor substrates14. For example, rather than the semiconductor wafer20(FIG. 2A), a substrate can comprise a portion of a semiconductor wafer, a panel, a leadframe or a circuit board containing multiple semiconductor substrates. In the claims to follow, the term “substrate” is used to encompass all of these elements.

As shown inFIG. 1A, the semiconductor substrate14, and the semiconductor wafer20as well, include a circuit side22wherein the imager pixel array16is located, and a back side24. As shown inFIG. 2A, each semiconductor substrate14has a generally square, die sized, peripheral outline. However, the semiconductor substrates14can have any polygonal peripheral outline used in the art. For illustrative purposes inFIGS. 1A-1E, a complete semiconductor substrate14is shown on the left, and a partial semiconductor substrate14is shown on the right to an arbitrary vertical break line30. The streets36(FIG. 2A) between adjacent semiconductor substrates14are denoted by spaces on the wafer20inFIG. 2A, and by vertical lines inFIG. 1A.

Next, as shown inFIG. 1B, a wafer scale carrier26can be provided. The carrier26can comprise a separate member configured for attachment to the semiconductor wafer20. In addition, the carrier26can comprise a relatively rigid material configured as a wafer sized support structure for the semiconductor wafer20during processing. Further, the carrier26is configured to protect the integrated circuits18during processing. Still further, following further processing to be hereinafter described, the carrier26is configured to provide die sized lens support structures26S (FIG. 1G) for the lens structures12(FIG. 1G) in the completed semiconductor components10(FIG. 1G). By way of example, the carrier26can comprise a glass material, a semiconductor material (e.g., silicon), or a ceramic material, which can be patterned in a desired configuration. For example, a sheet of material having a selected thickness, and a selected peripheral outline, can be etched through a mask containing a selected pattern with desired geometrical features. A representative initial thickness T1(FIG. 1B) for the carrier26can be from 300 μm to 600 μm.

In the illustrative embodiment of the method, a peripheral outline of the carrier26initially matches the peripheral outline of the semiconductor wafer20(FIG. 2A). As such, the carrier26can have a diameter of from about 24.5 mm (1 inch) to 300 mm (12 inch), which is a representative range for standard semiconductor wafers. Alternately, rather than having the same peripheral outline as the semiconductor wafer20(FIG. 2A), the carrier26can initially have any selected peripheral outline (e.g., square, rectangular, round), which covers multiple semiconductor substrates14(FIG. 2A) on the semiconductor wafer20(FIG. 2A). Following a singulation process to be hereinafter described, the die sized support structures26S (FIG. 1G) formed from the carrier26(FIG. 1B) may have a peripheral outline which matches the peripheral outline of a thinned semiconductor substrate14T (FIG. 1G) of the component10(FIG. 1G). Alternately depending on the singulation process the peripheral outlines of the support structures26S and the semiconductor substrate14T may be different.

For making the carrier26out of a glass material, glass plates are commercially available from Corning of Corning, N.Y., under the designation Corning 7059 glass. Another suitable glass material comprises borosilicate glass. In addition, glass can be wet etched through a mask using a solution of HF and H2O, or alternately using a solution of NH4F and H2O. Glass can also be dry etched using plasmas of CF4, CF4+O2, C2F6, CF3H, and C3F8. Photosensitive glasses which can be patterned using ultraviolet radiation are also available from Corning of Corning, N.Y. Plan Optik AG of Germany provides wafer level glass with cavities of a selected geometry, and also wafer level glass with electrical paths therethrough. Anteryon of The Netherlands also provides glass wafers with structured cavities, and also integrated lens stacks. Berliner Glas of Berlin, Germany also provides wafer level glass with cavities and metal via interconnects.

For making the carrier26out of a semiconductor material, a blank semiconductor wafer or portion thereof, can be anisotropically etched through a mask using a solution of KOH and H2O. A blank semiconductor wafer or portion thereof, can also be isotropically etched through a mask using a solution of HF, HNO3and H2O. A blank semiconductor wafer or portion thereof, can also be etched using a dry etch process such as reactive ion etching (RIE), (also known as “BOSCH” etching). Reactive ion etching (RIE) can be performed in a reactor with a suitable etch gas, such as CF4, SF6, Cl2or CCl2F2. For making the carrier26out of a ceramic material, glass ceramics are also available from Corning of Corning, N.Y. and can be etched using thermochemical etching techniques.

As shown inFIG. 1B, the carrier26initially includes a plurality of recesses28having a depth of D1. Mask openings in the mask (not shown) that is used to etch the carrier26determine the peripheral shape of the recesses. The depth D1of the recesses28is determined by the end point of the etch process. The peripheral shape of each recess28is selected to have a desired geometry which surrounds the imager pixel array16(FIG. 1A) on an associated semiconductor substrate14. In addition, each semiconductor substrate14on the wafer20(FIG. 2A) has an associated recess28(FIG. 1B) on the carrier26(FIG. 1B). As shown inFIG. 2B, each recess28can have a peripheral outline that substantially matches, but is slightly less than, the peripheral outline of the semiconductor substrates14on the wafer20(FIG. 2A). In addition, each recess28(FIG. 2B) can be slightly larger than the peripheral outline of the imager pixel arrays16. As also shown inFIG. 1B, the carrier26also includes full thickness pillars32that align with the streets36(FIG. 2A) between adjacent semiconductor substrates14on the semiconductor wafer20(FIG. 2A).

For attaching the carrier26to the wafer20(FIG. 2A), the pillars32(FIG. 1B) on the carrier26(FIG. 1B) are aligned with the streets36(FIG. 2A) on the wafer20, and the recesses28(FIG. 1B) on the carrier26(FIG. 1B) are aligned with the imager pixel arrays16(FIG. 1A) on the semiconductor substrates14. The aligning step can be performed using a suitable apparatus such as an aligner bonder configured for wafer level processes. Following the aligning step, an adhesive material34(FIG. 1B) is placed on the wafer20(FIG. 2A), such as in the streets36(FIG. 2A), and the pillars32(FIG. 1B) on the carrier26(FIG. 1B) are placed in contact with the adhesive material34(FIG. 1B). Alternately, the adhesive material34(FIG. 1B) can be placed on the pillars32(FIG. 1B), or on both the pillars32(FIG. 1B) and the wafer20(FIG. 2A).

The adhesive material34(FIG. 1B) can comprise a curable polymer deposited in a required pattern in a viscous or b-stage condition, and then cured under compression between the carrier26(FIG. 1B) and the wafer20(FIG. 2A). The adhesive material34(FIG. 1B) can be deposited on the wafer20(FIG. 2A) using a suitable deposition process such as deposition through a nozzle, screen printing, stenciling or stereographic lithography. One suitable nozzle deposition apparatus, also known as a material dispensing system, is manufactured by Asymtek of Carlsbad, Calif. Suitable curable polymers for the adhesive material34(FIG. 1B) include silicones, polyimides, epoxies and underfill materials. In addition, these polymer materials can include fillers, such as silicates, configured to reduce the coefficient of thermal expansion (CTE) and adjust the viscosity of the polymer material. Suitable curable polymer are manufactured by Dexter Electronic Materials of Rocky Hill, Conn. under the trademark “HYSOL”. As shown inFIG. 1C, following curing under compression, the adhesive material34(FIG. 1B) forms an adhesive layer34L (FIG. 1C) which adhesively attaches the carrier26(FIG. 1B) to the wafer14(FIG. 1B).

As also shown inFIG. 1B, a protective layer38can be placed on the exposed surface of the carrier26for protection during subsequent processes. For example, the protective layer38(FIG. 1B) can comprise a tape material that can be removed following a carrier etch step to be hereinafter described. Suitable tape materials are available from 3M of Minneapolis Minn. Rather than a tape material, the protective layer38(FIG. 1B) can comprise a deposited and cured polymer material, such as a resist deposited by a spin on process, which can be stripped following a carrier thinning step to be hereinafter described. Suitable resists are available from a variety of manufacturers including Shipley Company of Marlborough, Mass.

Next, as shown inFIG. 1C, a substrate thinning step can be performed on the back side24of the wafer20(FIG. 2A) to thin the semiconductor substrates14into thinned substrates14T (FIG. 1C). During the substrate thinning step, the carrier26(FIG. 1C) supports the wafer20(FIG. 2A) and prevents cracking, particularly near the peripheral edges of the wafer20(FIG. 2A), which are prone to cracking. The substrate thinning step can be performed by mechanically planarizing the wafer20(FIG. 2A), or by etching the wafer20(FIG. 2A). For example, the substrate thinning step can be performed using a mechanical planarization apparatus (e.g., a grinder). One suitable mechanical planarization apparatus is manufactured by Okamoto, and is designated a model no. VG502. The substrate thinning step can also be performed using a chemical mechanical planarization (CMP) apparatus. A suitable CMP apparatus is commercially available from a manufacturer such as Westech, SEZ, Plasma Polishing Systems, or TRUSI. The substrate thinning step can also be performed using an etch back process, such as a wet etch process, a dry etch process or a plasma etching process. The thinned semiconductor substrates14T (FIG. 1C) can have a selected thickness T2(FIG. 1C). A representative range for the selected thickness T2can be from about 50 μm to 700 μm.

As also shown inFIG. 1C, following the substrate thinning step, terminal contacts40can be formed on the back sides24of the thinned semiconductor substrates14T. In addition, as shown inFIG. 3A, back side redistribution conductors42can be formed on the back sides24of the thinned semiconductor substrates14T in electrical communication with the terminal contacts40. As also shown inFIG. 3A, the back side redistribution conductors42can be in electrical communication with conductive vias44through the thinned semiconductor substrates14T. The conductive vias44can be in electrical communication with the integrated circuits18on the circuit sides22of the thinned semiconductor substrates14T.

With the carrier26(FIG. 1C) comprising a semiconductor material, prior to forming the terminal contacts40(FIG. 3A) and the back side redistribution conductors42(FIG. 3A), insulation layers46(FIG. 3A) can be formed on the back sides24(FIG. 1C) of the thinned semiconductor substrates14T (FIG. 3A). The insulation layers46(FIG. 3A) can comprise a polymer, such as polyimide or parylene, deposited using a suitable process, such as vapor deposition, spin-on, capillary injection or screen-printing. Alternately, the insulation layers46(FIG. 3A) can comprise a deposited oxide layer, such as a low temperature deposited oxide. As another alternative, the insulation layers46(FIG. 3A) can comprise a grown oxide layer, such as silicon dioxide formed by oxidation of silicon.

The back side redistribution conductors42(FIG. 3A) can also include terminal contact pads (not shown) for the terminal contacts40(FIG. 3A). The redistribution conductors42(FIG. 3A), and associated terminal contact pads (not shown), can comprise a same patterned layer of material, such as a highly conductive metal layer (e.g., Cu, Al, Au). The terminal contacts40(FIG. 3A) can comprise metal, or solder, balls, bumps or pins, formed on the terminal contact pads using a metallization process, a stud bumping process or a ball bonding process. A representative range for the diameter of the terminal contacts40(FIG. 3A) can be from 60-500 μm. In addition, the terminal contact pads (not shown) and the terminal contacts40(FIG. 3A), can be formed in an area array, such as a ball grid array, a pin grid array, an edge array or a center array.

The conductive vias44(FIG. 3A) can be formed either prior to, or after the substrate thinning step, using a suitable process. For example, the conductive vias44can be formed using a wet or dry etching process substantially as previously described for patterning the carrier26to form the recesses28(FIG. 1B). Another method for forming the conductive vias44(FIG. 3A) uses laser machining to machine openings, which are then insulated and filled with a conductive material. By way of example, the diameters of the conductive vias44(FIG. 3A) can be from 10 μm to 2 mils or greater. A suitable laser system for performing the laser machining step is manufactured by Electro Scientific, Inc., of Portland, Oreg. and is designated a Model No. 2700. Another laser system is manufactured by XSIL Corporation of Dublin, Ireland and is designated a Model No. “XCISE-200”.

With the carrier26(FIG. 1C) comprising a semiconductor material, the conductive vias44(FIG. 3A) can be insulated using a polymer, such as polyimide or parylene, deposited using a suitable process, such as vapor deposition, capillary injection or screen-printing. Alternately, the insulation layers can comprise a deposited oxide layer, such as a low temperature deposited oxide. With the carrier26(FIG. 1C) comprising glass or ceramic, the conductive vias44do not require insulation. The conductive material for the conductive vias44(FIG. 3A) can comprise a highly conductive metal, such as aluminum, titanium, nickel, iridium, copper, gold, tungsten, silver, platinum, palladium, tantalum, molybdenum, tin, zinc and alloys of these metals including solder alloys. The above metals can be deposited within insulated openings using a deposition process, such as electroless deposition, CVD, or electrolytic deposition. Rather than being a metal, the conductive material can comprise a conductive polymer, such as a metal filled silicone, an isotropic epoxy, or a nano-particle conductive polymer.

During the fabrication of the conductive vias44(FIG. 3A), and during the fabrication of the back side redistribution conductors42(FIG. 3A), and the terminal contacts40(FIG. 3A) as well, the carrier26functions to support and rigidify the thinned semiconductor substrates14T, and the thinned semiconductor wafer20(FIG. 2A). In addition, as shown inFIG. 1C, the recesses28on the carrier26cover and protect the imager pixel arrays16(FIG. 1A), and the integrated circuits18on the circuit sides22of the thinned semiconductor substrates14T.

Next, as shown inFIG. 1D, the protective layer38can be removed from the carrier26using a suitable process such as peeling, chemical stripping or grinding. In addition, the carrier26can be thinned to remove material to the recesses28(FIG. 1C) to form individual support structures26S on the thinned semiconductor substrates14T. The carrier thinning step can be performed using an etching process substantially as previously described for patterning the carrier26to form the recesses28(FIG. 1B). However, in this case the etch mask includes openings which align with the recesses28(FIG. 1B) and remove all of the material covering the recesses28such that only the pillars32remain. Stated differently, the recesses28are transformed from enclosed structures to open ended structures. InFIG. 1D, the removed material is denoted by the dotted lines. Alternately, rather than performing the carrier thinning step by etching, a mechanical process can be utilized, such as a grinding process or a chemical mechanical planarization (CMP) process, substantially as previously described for the substrate thinning step for thinning the semiconductor substrates14(FIG. 1B) into thinned semiconductor substrates14T (FIG. 1C).

In addition, the carrier thinning step can be performed to form the support structures26S with a selected geometry, a planar surface and a selected height H on the thinned semiconductor substrates14T. Further, the height H can be selected to accommodate a desired focal length between the lens structures12(FIG. 1G) and the imager pixel arrays16. In addition by changing the height H, the focal length can be tailored for a particular application. As shown inFIG. 3B, the support structures26S have a picture frame shape, which surrounds the imager pixel arrays16on the thinned semiconductor substrates14T. The middle portion of each support structure26S (FIG. 3B) has an outline which matches the outline of a recess28(FIG. 1B). The outer of each support structure26S (FIG. 3B) has an outline which matches the outline of a thinned semiconductor substrate14T (FIG. 1D). In addition, an outer surface33of each support structure26S comprises a planar surface suitable for precisely mounting the lens structure12(FIG. 1G).

Following the carrier thinning step, and as shown inFIG. 1E, a protective layer48can be applied to the planar outer surfaces33of the support structures26S, to protect the imager pixel arrays16, the integrated circuits18, and the circuit sides22of the thinned substrates14T. The protective layer48can comprise a tape material or a polymer structure attached to the carrier26, substantially as previously described for the protective layer38(FIG. 1B). As with the protective layer38, the protective layer48will be subsequently removed following a singulation step to be further described.

Next, as shown inFIG. 1F, a singulating step can be performed to form cut lines50in the semiconductor wafer20(FIG. 2A), and to singulate the thinned semiconductor substrates14T from the semiconductor wafer20(FIG. 2A). The singulating step can be performed using a dicing saw configured to dice semiconductor wafers into individual dice. Alternately, rather than by sawing, the singulating step can be performed using another singulation method, such as cutting with a laser or a water jet, or by etching with a suitable wet or dry etchant. Following the singulating step, the protective layer48can be removed from the support structures26S using a suitable process such as peeling, chemical stripping or grinding. As shown inFIG. 3B, each support structure26S has a chip scale outline which matches the outline of a singulated thinned semiconductor substrate14T. In addition, each support structure26S has a picture frame shape which encloses an associated imager pixel array16on the thinned semiconductor substrate14T.

Next, as shown inFIG. 1G, the lens structures12can be provided, and a lens attachment (or forming) step can be performed. Each lens structure12can include any number of lenses combined in an integrated structure. Suitable lens structures12are commercially available from manufacturers such as Anteryon of the Netherlands with any desired number of integrated lenses. In the illustrative embodiment, each lens structure12includes a first lens52and a second lens54mounted to a lens support56. The lens structures12can comprise separate members as shown inFIG. 1G, or as will be further explained, can be assembled in place. The lens attachment step can be performed using an adhesive material (not shown), substantially as previously described for attaching the carrier26(FIG. 1B) using the adhesive material34(FIG. 1B). However, in this case attachment is performed at the die level on the singulated thinned semiconductor substrates14T, rather than at the wafer level as with the previously described carrier attachment step. Placement of the lens structures12on the support structures26S can be performed using a suitable automated apparatus such as a pick and place system. In addition, since the outer surfaces33of the support structures26S have been planarized by the carrier thinning step, a precise alignment between the lens structure12and the pixel array16can be achieved.

As shown inFIG. 1G, the semiconductor component10includes the thinned semiconductor substrate14T, the support structure26S attached to the thinned semiconductor substrate14T, and the lens structure12attached to the support structure26S. The semiconductor component10also includes terminal contacts40on its back side24, and the imager pixel array16and integrated circuits18on its circuit side22. In addition, the semiconductor component10has a chip scale outline that matches the outline of the thinned semiconductor substrate14T. Further, the height H of the support structure26S can be selected to provide a desired focal length for the lens structure12relative to the imager pixel array16. With the height H being fixed the lens structure12comprises a fixed focus system. However, as will be further explained a lens structure can include a fixed lens and a variable focus lens in combination.

Referring toFIGS. 4A-4B, a method for fabricating semiconductor components10A (FIG. 4B) with lens structures12A (FIG. 4B) is illustrated. The lens structure12A (FIG. 4B) include a lens support (FIG. 4B), a first lens52A (FIG. 4B) and a second lens54A (FIG. 4B), substantially as previously described for lens structure12(FIG. 1G). However, the lens structure12A (FIG. 4B) also includes a focusing device58A (FIG. 4B). The focusing device58A (FIG. 4B) can comprise a MEMS (microelectricalmechanical system), or similar electro mechanical device, configured to manipulate the first lens52A (FIG. 4B), the second lens54A (FIG. 4B) or both, for focusing and other operations.

Rather than being a MEMS (microelectricalmechanical system), the focusing device58A (FIG. 4B) can comprise a tunable/variable lens supplied by a manufacturer such as Varioptics of Lyon, France. One type of tunable/variable lens is based on the principle of electrowetting where an electrical voltage is applied to a combination of liquids in order to change the contact angle and form a surface into a desired shape. Another type of tunable/variable lens is described by Hongwen Ren, Yi-Hsin Lin, and Shin-Tson Wu in an article entitled “Flat Polymeric Microlens Array” published in Optics Communications 261, 2006 pages 269-299. This article describes “a polymer-based microlens which can focus light due to its central-symmetric inhomogeneous gradient index distribution, rather than surface-relief structure.” A voltage is applied to the material and the focus length changes as the index of refraction within the polymer is changed in a central-symmetrical inhomogeneous orientation. In addition, UV light can be used to cure the polymer and fix the focus length once it has been tuned.

The method illustrated inFIGS. 4A-4Bis substantially similar to the method ofFIGS. 1A-1G. As such, a wafer sized carrier26A (FIG. 4A) is provided for attachment to a semiconductor wafer20(“substrate” in the claims) containing a plurality of semiconductor substrates14(FIG. 4A). The carrier26A (FIG. 4A) also includes recesses28A (FIG. 4A) that align with the imager pixel arrays16(FIG. 4A) and protect the integrated circuits18(FIG. 4A) on the semiconductor substrates14(FIG. 4A). The carrier26A also includes conductive vias60A (FIG. 4A) having contacts62A (FIG. 4A) thereon. The conductive vias60A (FIG. 4A) are substantially similar to the conductive vias44(FIG. 3A) previously described in the thinned semiconductor substrate14T.

As shown inFIG. 4A, a conductive adhesive material34A is placed between the carrier26A and the semiconductor substrates14. The conductive adhesive material34A (FIG. 4A) aligns with the contacts62A (FIG. 4A) on the conductive vias60A (FIG. 4A). The conductive adhesive material34A (FIG. 4A) also aligns with conductive vias44A (FIG. 4A) in the semiconductor substrates14. The conductive vias44A (FIG. 4A) can be formed either before thinning of the semiconductor substrates14or after thinning, substantially as previously described for conductive vias44(FIG. 3A). In addition, the conductive vias44A (FIG. 4B) are in electrical communication with terminal contacts40A (FIG. 4B) on the component10A (FIG. 4B) substantially as previously described for conductive vias44(FIG. 3A). Rather than fabricating the conductive vias44prefabricated conductive vias in glass plates can be provided by a manufacturer such as Plan Optik AG of Germany. This type of glass plate could then be etched to form the recesses28A (FIG. 4A).

The conductive adhesive material34A (FIG. 4A) can comprise a bondable metal such as solder or gold. As another alternative, the conductive adhesive material34A (FIG. 4A) can comprise a conductive polymer, such as a metal filled silicone, or a z-axis epoxy. Suitable conductive polymers are available from A.I. Technology, Trenton, N.J.; Sheldahl, Northfield, Minn.; and 3M, St. Paul, Minn. Another suitable conductive polymer is a nano-particle paste or ink, having metal nano-particles made of a highly conductive metal, such as gold or silver. Nano-particle conductive polymers are commercially available from Superior Micropowders, of Albuquerque, N. Mex. As shown inFIG. 4B, following hardening or curing, the adhesive material34A forms an electrically conductive adhesive layer34AL.

As shown inFIG. 4B, the lens supports56A include contacts64A in electrical communication with the focusing devices58A. During attachment of the lens structures12A to the support structures26AS (FIG. 4B), the contacts64A (FIG. 4B) can be bonded, or otherwise electrically connected to the conductive vias60A (FIG. 4B) on the support structures26AS (FIG. 4B). For example, the contacts64A (FIG. 4B) can comprise a metal or a conductive polymer that bonds to the conductive vias60A (FIG. 4B) on the support structures26AS (FIG. 4B).

In the component10A (FIG. 4B), the conductive adhesive layer34AL (FIG. 4B) provides electrical paths from the terminal contacts40A (FIG. 4B) and the conductive vias44A (FIG. 4B) on the thinned semiconductor substrate14T, to the conductive vias60A (FIG. 4B) on the support structure26AS (FIG. 4B). The conductive vias60A (FIG. 4B) on the support structure26AS (FIG. 4B) provide electrical paths to the contacts64A (FIG. 4B) and to the focusing devices58A (FIG. 4B) on the lens structure12A (FIG. 4B).

Initially as shown inFIG. 5A, a carrier26B is attached to a wafer20(“substrate” in the claims) containing semiconductor substrates14(FIG. 2A) as previously described. In addition, the carrier26B supports the wafer20(FIG. 2A) during substrate thinning to form the thinned semiconductor substrates14T (FIG. 5A) as previously described. In this case, the carrier26B (FIG. 5A) comprises an optically transparent material, such as glass. In addition, the carrier26B (FIG. 5A) includes recesses28B (FIG. 5A) that align with the imager pixel arrays16(FIG. 5A), and pillars32B (FIG. 5A) that adhesively attach to the semiconductor substrates14T as previously described. The recesses28B (FIG. 5A) can be formed as previously described by etching. Alternately, a wafer level glass plate can be provided with prefabricated recesses from a manufacturer such as Plan Optik AG of Germany, Anteryon of The Netherlands, or Berliner Glas of Berlin, Germany. Further, using the carrier26B (FIG. 5A) for support and protection, terminal contacts40B (FIG. 5A) are formed on the thinned semiconductor substrates14T, as previously described.

As shown inFIG. 5A, dots or globs of a lens polymer66B can be applied to selected areas on the outer surface of the carrier26B for forming the first lens52B (FIG. 5B). The lens polymer66B can comprise a curable polymer, such as a resist. The lens polymer66B can be applied in viscous form using a suitable process such as inkjet deposition, deposition through a nozzle, screen printing, stenciling or stereographic lithography. In addition, the lens polymer66B can be applied on areas on the carrier26B that align with the imager pixel arrays16. Further, the dots or globs of lens polymer can have a shape and a volume selected to cover areas with a desired geometry (e.g., circular, oval, square, rectangular), and with a desired thickness of material. Also, prior to applying the lens polymer66B, these areas on the carrier26B can be one to one selectively etched (or otherwise processed such as by grinding), to form a smooth lens surface.

The shape of the first lens52B (FIG. 5B) can also be formed by a standard photoresist reflow technique for making lenses. For example, the lens polymer66B can comprise a photoresist, such as Shipley “AZ4562” manufactured by Shipley of Company of Marlborough, Mass., or an amorphous fluorocarbon polymer such as “CYTOP” manufactured by Bellex International Corporation of Delaware. The photoresist can be patterned into a desired shape (e.g., cylindrical) and then heated until it reflows into a spherical lens shape. The lens shape can then be transferred onto the carrier26B (FIG. 5B) through a reactive ion etch (RIE) process that provides a near one-to-one selectivity. The reactive gases will vary depending upon the polymer and substrate used. Examples of gases used to etch polymer and glass are O2in combination with CF4, C2F6, CF3H, or C3F8. In addition, the transferred lens shape can be varied by changing the gas flows and pressure so that aspherical lens shapes can be made in the carrier26B (FIG. 5B).

As shown inFIG. 5B, curing of the lens polymer66B forms the first lenses52B integrally on the surface of the carrier26B. In addition, the first lenses52B align with the recesses in the carrier28B, and align with the imager pixel arrays16on the thinned semiconductor substrates14T. In this case, the depth D1of the recesses28B, and the thickness T3(FIG. 5A) of the carrier28B over the recesses28B, can be selected to provide a desired focal length between the first lenses52B and the imager pixel arrays16. In addition, the recesses28B (FIG. 5B) can be etched with a generally convex or alternately concave shape to vary the focal length across the imager pixel array16. As with the previous embodiment, the first lenses52B have a fixed focus, but the second lenses54B (FIG. 5F) can be configured to provide a variable focus.

Next, as shown inFIG. 5C, the lens supports56B can be fabricated on the carrier26B proximate to the first lenses52B. The lens supports56B can comprise a polymer material, such as a resist, that can be patterned to form the lens supports56B with a desired geometry, and in desired locations on the surface of the carrier26B. For example, the lens supports56B can have a circular, oval, square or rectangular shape that matches the shape of the first lenses52B. In addition, the lens supports56B can have a thickness T4selected to space the second lenses54B from the first lenses52B by a desired distance. One suitable material for the lens supports56B is a thick film resist such as “EPON RESIN SU-8” available from Shell Chemical of Houston, Tex. Alternately, the lens supports56B can comprise glass or silicon spacer adhesively or otherwise attached to the carrier26B (FIG. 5C).

Next, as shown inFIG. 5C, a protective layer48B can be applied to the carrier26B to protect the first lenses52B. The protective layer48B can comprise a tape material or a polymer structure attached to the carrier26B, substantially as previously described for the protective layer48(FIG. 1E).

Next, as shown inFIG. 5D, a singulating step can be performed to form cut lines50B in the semiconductor wafer20(FIG. 2A), and to singulate the thinned semiconductor substrates14T from the semiconductor wafer20(FIG. 2A). The singulating step can be performed using a dicing saw configured to dice semiconductor wafers into individual dice. Alternately, rather than by sawing, the singulating step can be performed using another singulation method, such as cutting with a laser or a water jet, or by etching with a suitable wet or dry etchant. Following the singulating step, the protective layer48B can be removed from the support structures26S using a suitable process such as peeling, chemical stripping or grinding. As shown inFIG. 5E, each support structure26BS has a chip scale outline which matches the outline of a singulated thinned semiconductor substrate14T. In addition, each support structure26BS has a picture frame shape which encloses an associated imager pixel array16on the thinned semiconductor substrate14T.

Next, as shown inFIG. 5F, the second lens54B can be provided, and a lens attachment step can be performed. The lens attachment step can be performed using an adhesive material (not shown) which attaches the second lens54B to the lens support56B, substantially as previously described for attaching the lens structure12(FIG. 1C). Placement of the second lens54B on the lens support56B can be performed using a suitable automated apparatus such as a pick and place system.

As shown inFIG. 5F, the semiconductor component10B includes the thinned semiconductor substrate14T, the support structure26BS attached to the thinned semiconductor substrate14T, and the lens structure12B attached to the support structure26S. The lens structure12B (FIG. 5F) includes the first lens52B (FIG. 5F) formed integrally with the support structure26BS (FIG. 5F), and the second lens54B (FIG. 5F) on the lens support56B (FIG. 5F). The semiconductor component10B (FIG. 5F) also includes terminal contacts40B (FIG. 5F) on its back side24, and the imager pixel array16and integrated circuits18on its circuit side22. In addition, the semiconductor component10B has a chip scale outline that matches the outline of the thinned semiconductor substrate14T. The semiconductor component10B can also include a focusing device58A (FIG. 4B), and conductive vias60A (FIG. 4A) through the lens support structure26BS (FIG. 5F) for providing electrical paths to the focusing device58A (FIG. 4B).

An alternate embodiment semiconductor component10BB, is shown inFIG. 5G. The semiconductor component10BB (FIG. 5G) is substantially similar to the semiconductor component10B (FIG. 5F), and is fabricated using essentially the same process. As such, the semiconductor component10BB (FIG. 5G) includes a lens support structure26BB (FIG. 5G) having an integral first lens52BB (FIG. 5G), substantially as previously described for lens support structure26BS (FIG. 5F) with first lens52B (FIG. 5F). As previously explained, the first lens52BB is formed at a fixed focal distance from the imager pixel array16(FIG. 5F). In addition, the semiconductor component10BB (FIG. 5G) includes a lens support56BB (FIG. 5G), which is substantially similar to the lens support56B (FIG. 5F). However, both the lens support structure26BB (FIG. 5G) and the lens support56BB (FIG. 5G), include conductive vias60BB (FIG. 5G), which are substantially similar to the previously described conductive vias60A (FIG. 4B). In addition, a second lens structure54BB (FIG. 5G) includes two lenses54B-1,54B-2coupled to a focusing device58BB (FIG. 5G), which is substantially similar to the focusing device58A (FIG. 4B). The second lens structure54BB (FIG. 5G) can comprise a commercial system such as one manufactured by Varioptic of Lyons France. Additionally, the second lens structure54BB (FIG. 5G) can comprise one or any number of separate lenses. Further, the focusing device58BB (FIG. 5G) is in electrical communication with the conductive vias60BB (FIG. 5G), such that control signals can be used as previously described to manipulate the lenses54B-1,54B-2(FIG. 5G) to provide variable focus for the semiconductor component10BB (FIG. 5G).

Referring toFIG. 6A, a system68for fabricating image sensor semiconductor components10(FIG. 1G) with lens structures12(FIG. 1G) is illustrated. The system68includes the semiconductor wafer20(“substrate” in the claims) containing the semiconductor substrates14having the imager pixel arrays16(FIG. 1A) and integrated circuits18(FIG. 1A). The system68also includes the carrier26configured for attachment to the circuit side22of the wafer20. The carrier26is configured to support the wafer20for various processes including thinning. In addition, the carrier26includes recesses28that align with the semiconductor substrates14, which are configured to protect the imager pixel arrays16(FIG. 1A) and the integrated circuits18(FIG. 1A), during these processes. Further, the carrier26is configured for thinning and singulation to form a plurality of lens support structures26S for lens structures12having planar surfaces33(FIG. 1D), a selected geometry (e.g., picture frame) and a selected height H (FIG. 1D).

The system68(FIG. 6A) can also include a substrate thinning system70(FIG. 6A) configured to thin the back side24of the semiconductor wafer20and the semiconductor substrates14with support from the carrier26(FIG. 6A). The substrate thinning system70(FIG. 6A) can comprise a mechanical system, such as a grinder or a chemical mechanical planarization (CMP) apparatus, or an etching system, such as a wet or dry etcher. The system68(FIG. 6A) can also include a carrier thinning system74(FIG. 6A), such as an etching system or a mechanical system, such as a grinder or a chemical mechanical planarization (CMP) apparatus, configured to thin the carrier26(FIG. 6A) to shape the support structures26S (FIG. 6A). The system68(FIG. 6A) can also include a dicing system72(FIG. 6A), such as a dicing saw, a laser, a water jet or an etching system, configured to singulate the carrier26(FIG. 6A) into the support structures26S (FIG. 6A), and the semiconductor substrates14T into the components10(FIG. 1G).

Referring toFIG. 6B, a system68A for fabricating image sensor semiconductor components10A (FIG. 4B) with lens structures12A (FIG. 4B) with focusing devices58A is illustrated. The system68A includes the semiconductor wafer20(“substrate” in the claims) containing the semiconductor substrates14having the imager pixel arrays16(FIG. 1A) and integrated circuits18(FIG. 1A). The system68A (FIG. 6B) also includes the carrier26A (FIG. 6B) configured for attachment to the circuit side22of the wafer20. The carrier26A (FIG. 6B) is configured to support the wafer20for various processes including thinning. In addition, the carrier26A includes recesses28A that align with the semiconductor substrates14, which are configured to protect the imager pixel arrays16(FIG. 1A) and the integrated circuits18(FIG. 1A), during these processes. Further, the carrier26A (FIG. 6B) is configured for thinning and singulation to form a plurality of support structures26AS (FIG. 6B) for lens structures12A (FIG. 6B) having planar surfaces33(FIG. 1D), a selected geometry (e.g., picture frame) and a selected height H (FIG. 1D). Still further, the carrier26A (FIG. 6B) includes conductive vias60A (FIG. 6B), which along with the conductive adhesive layer34AL (FIG. 6B), provide separate electrical paths to the focusing devices58A.

The system68A (FIG. 6B) can also include a substrate thinning system70(FIG. 6B) configured to thin the back side24of the semiconductor wafer20and the semiconductor substrates14with support from the carrier26A (FIG. 6B). The thinning system70(FIG. 6B) can comprise a mechanical system, such as a grinder or a chemical mechanical planarization (CMP) apparatus, or an etching system, such as a wet or dry etcher. The system68A (FIG. 6B) can also include a carrier thinning system74(FIG. 6B), such as an etching system or a mechanical system, such as a grinder or a chemical mechanical planarization (CMP) apparatus, configured to thin the carrier26(FIG. 6B) to shape the support structures26AS (FIG. 6A). The system68A (FIG. 6B) can also include a singulation system72(FIG. 6B), such as a dicing saw, a laser, a water jet or an etching system, configured to singulate the carrier26A (FIG. 6B) into the support structures26AS (FIG. 6B), and the semiconductor substrates14T into the components10A (FIG. 4B).

Referring toFIG. 6C, a system68B for fabricating image sensor semiconductor components10B (FIG. 5F) with lens structures12B (FIG. 5F) with integral first lenses52B (FIG. 5F) is illustrated. The system68B includes the semiconductor wafer20(“substrate” in the claims) containing the semiconductor substrates14having the imager pixel arrays16(FIG. 1A) and integrated circuits18(FIG. 1A). The system68B (FIG. 6C) also includes the carrier26B (FIG. 6C) configured for attachment to the circuit side22of the wafer20. The carrier26B (FIG. 6C) is configured to support the wafer20for various processes including thinning. In addition, the carrier26B includes recesses28B that align with the semiconductor substrates14, which are configured to protect the imager pixel arrays16(FIG. 1A) and the integrated circuits18(FIG. 1A), during these processes. Further, the carrier26B (FIG. 6B) is configured for patterning and singulation to form a plurality of support structures26BS (FIG. 6C) for lens structures12B (FIG. 6C). Still further, the carrier26B (FIG. 6C) is configured to provide the first lenses52B (FIG. 5F) and the lens supports56B (FIG. 5F) for the second lenses54B (FIG. 5F).

The system68B (FIG. 6C) can also include a thinning system70(FIG. 6C) configured to thin the back side24of the semiconductor wafer20and the semiconductor substrates14with support from the carrier26B (FIG. 6C). The thinning system70(FIG. 6C) can comprise a mechanical system, such as a grinder or a chemical mechanical planarization (CMP) apparatus, or an etching system, such as a wet or dry etcher. The system68B (FIG. 6C) can also include a singulation system72(FIG. 6C), such as a dicing saw, a laser, a water jet or an etching system, configured to singulate the carrier26B (FIG. 6C) into the support structures26BS (FIG. 6C), and the semiconductor substrates14T into the components10B (FIG. 5F). The system68B (FIG. 6C) can also include a lens deposition system76(FIG. 6C) configured to deposit a lens polymer for forming the first lenses52B (FIG. 5F). The lens deposition system76(FIG. 6C) can comprise a nozzle deposition system, a screen printing system, a stenciling system or a stereographic lithography system.