Ultrathin spacer formation for carbon-based FET

A method for formation of a carbon-based field effect transistor (FET) includes depositing a first dielectric layer on a carbon layer located on a substrate; forming a gate electrode on the first dielectric layer; etching an exposed portion of the first dielectric layer to expose a portion of the carbon layer; depositing a second dielectric layer over the gate electrode to form a spacer, wherein the second dielectric layer is deposited by atomic layer deposition (ALD), and wherein the second dielectric layer does not form on the exposed portion of the carbon layer; forming source and drain contacts on the carbon layer and forming a gate contact on the gate electrode to form the carbon-based FET.

FIELD

This disclosure relates generally to the field of semiconductor device fabrication, and more specifically to formation of an ultrathin spacer for a carbon-based field effect transistor (FET) device.

DESCRIPTION OF RELATED ART

In modern microelectronic integrated circuit (IC) technology, a silicon wafer is lithographically patterned to accommodate a large number of interconnected electronic components (such as FETs, resistors, or capacitors, etc.). The technology relies on the semiconducting properties of silicon and on lithographic patterning methods. Increasing the density of electronic components and reducing the power consumption per component are two major objectives in the microelectronics industry, which have driven the steady reduction in the size of components in past decades. However, miniaturization of silicon-based electronics may reach a limit in the near future, primarily because of limitations imposed by the material properties of silicon and doped silicon at the nanoscale level.

To sustain the miniaturization trend in microelectronics beyond the limits imposed by silicon-based microelectronics technologies, alternative technologies and materials need to be developed. Requirements for such alternative technologies include smaller feature sizes than are feasible with silicon-based microelectronics, more energy-efficient electronic strategies, and production processes that allow large-scale integration, preferably using lithographic patterning methods related to those used in silicon-based microelectronic fabrication. A material that is being explored as an alternative to silicon in microelectronics fabrication is carbon. The carbon used for such applications may take various forms, including graphene. Graphene refers to a two-dimensional planar sheet of carbon atoms arranged in a hexagonal benzene-ring structure. A free-standing graphene structure is theoretically stable only in a two-dimensional space, which implies that a truly planar graphene structure does not exist in a three-dimensional space, being unstable with respect to formation of curved structures such as soot, fullerenes, nanotubes or buckled two dimensional structures. However, a two-dimensional graphene structure may be stable when supported on a substrate, for example, on the surface of a silicon carbide (SiC) crystal. Free standing graphene films have also been produced, but they may not have the idealized flat geometry.

Structurally, graphene has hybrid orbitals formed by sp2hybridization. In the sp2hybridization, the 2s orbital and two of the three 2p orbitals mix to form three sp2orbitals. The one remaining p-orbital forms a pi (π)-bond between the carbon atoms. Similar to the structure of benzene, the structure of graphene has a conjugated ring of the p-orbitals, i.e., the graphene structure is aromatic. Unlike other allotropes of carbon such as diamond, amorphous carbon, carbon nanofoam, or fullerenes, graphene is only one atomic layer thin.

Graphene has an unusual band structure in which conical electron and hole pockets meet only at the K-points of the Brillouin zone in momentum space. The energy of the charge carriers, i.e., electrons or holes, has a linear dependence on the momentum of the carriers. As a consequence, the carriers behave as relativistic Dirac-Fermions with a zero effective mass and are governed by Dirac's equation. Graphene sheets may have a large carrier mobility of greater than 200,000 cm2/V-sec at 4K. Even at 300K, the carrier mobility can be as high as 15,000 cm2/V-sec.

Graphene layers may be grown by solid-state graphitization, i.e., by sublimating silicon atoms from a surface of a silicon carbide crystal, such as the (0001) surface. At about 1,150° C., a complex pattern of surface reconstruction begins to appear at an initial stage of graphitization. Typically, a higher temperature is needed to form a graphene layer. Graphene layers on another material are also known in the art. For example, single or several layers of graphene may be formed on a metal surface, such as copper and nickel, by chemical deposition of carbon atoms from a carbon-rich precursor.

Graphene displays many other advantageous electrical properties such as electronic coherence at near room temperature and quantum interference effects. Ballistic transport properties in small scale structures are also expected in graphene layers. Graphene may form a one-atom thick planar sheet of carbon, referred to as a graphene sheet; graphite, which comprises stacks of graphene sheets; or a carbon nanotube.

A carbon-based FET may comprise a form of graphene in the channel and source/drain regions. However, one issue in forming carbon-based FET devices is that spacer formation may be difficult. FET spacers may be formed by depositing the spacer material, and then performing reactive ion etching (RIE) to shape the spacers. However, in a carbon-based FET, the RIE may damage the graphene in the source/drain and channel regions, making this method of spacer formation impractical for carbon-based FETs.

SUMMARY

In one aspect, a method for formation of a carbon-based field effect transistor (FET) includes depositing a first dielectric layer on a carbon layer located on a substrate; forming a gate electrode on the first dielectric layer; etching an exposed portion of the first dielectric layer to expose a portion of the carbon layer; depositing a second dielectric layer over the gate electrode to form a spacer, wherein the second dielectric layer is deposited by atomic layer deposition (ALD), and wherein the second dielectric layer does not form on the exposed portion of the carbon layer; forming source and drain contacts on the carbon layer and forming a gate contact on the gate electrode to form the carbon-based FET.

In one aspect, a carbon-based field effect transistor (FET) includes a substrate; a carbon layer located on the substrate, the carbon layer comprising a channel region, and source and drain regions located on either side of the channel region; a gate electrode located on the channel region, the gate electrode comprising a dielectric layer, a gate metal layer located on the dielectric layer, and a nitride layer located on the gate metal layer; and a spacer located adjacent to the gate electrode, the spacer comprising a material deposited by atomic layer deposition (ALD).

Additional features are realized through the techniques of the present exemplary embodiment. Other embodiments are described in detail herein and are considered a part of what is claimed. For a better understanding of the features of the exemplary embodiment, refer to the description and to the drawings.

DETAILED DESCRIPTION

Embodiments of an ultrathin spacer for a carbon-based FET, and a method of forming an ultrathin spacer for a carbon-based FET, are provided, with exemplary embodiments being discussed below in detail. Selective deposition using atomic layer deposition (ALD) may be used to deposit spacer material for a carbon-based FET, allowing precise spacer thickness control, anywhere in the range from about 10 angstroms to about 100 nanometers or greater. Reduction in spacer thickness may significantly improve FET parasitic resistance by reducing the underlap region between the gate and source/drain regions. A carbon FET may comprise one or more graphene sheets or carbon nanotubes in the channel and source/drain regions.

FIG. 1illustrates an embodiment of a method100of forming an ultrathin spacer for a carbon FET.FIG. 1is discussed with reference toFIGS. 2-8. In block101, a first dielectric203is deposited using ALD over substrate201and carbon layer202, as shown in the cross section200ofFIG. 2. Substrate201may comprise oxide in some embodiments. Carbon layer202may comprise one or more graphene sheets or carbon nanotubes in various embodiments. First dielectric203comprises a high k material, and may be formed by first depositing a seed layer, and the depositing the high k material over the seed layer using ALD. The seed layer is selected to promote adhesion of the first dielectric203to carbon layer202, and may comprise aluminum or a polymer such as a nanofibrillar composite (NFC) in some embodiments. Alternately, the top surface of carbon layer202maybe treated with ozone (O3) before ALD of high k first dielectric203. The high k material comprising first dielectric203may comprise any appropriate high k material, including but not limited so hafnium oxide (HfO2) or aluminum oxide (Al2O3).

In block102, gate electrodes comprising gate metal301under nitride layers302are formed on first dielectric203, as shown inFIG. 3.FIG. 3illustrates an embodiment of a cross section300A and a top view300B of the device ofFIG. 2after gate electrode formation. The gate metal301and nitride layers302may be formed by lift-off patterning in some embodiments, or by deposition and etching in other embodiments. Gate metal301may comprise palladium in embodiments in which a p-type carbon FET is being formed, or may comprise aluminum in embodiments in which an n-type carbon FET is being formed. The thickness of gate metal301may be adjusted as needed to obtain an optimal gate-to-source/drain capacitance and source/drain underlap resistance in the finished carbon-based FET.

In block103, a high k etch is used to remove the exposed portion of first dielectric layer203(the portion not located underneath gate metal301and nitride layers302), thereby exposing substrate201and a portion of carbon layer202, as shown inFIG. 4.FIG. 4illustrates an embodiment of a cross section400A and a top view400B of the device ofFIG. 3after high k etching. The nitride layers302act as a hard mask during the high k etch. In embodiments in which carbon layer202comprises carbon nanotubes, the high k etch of block103may overetch into the substrate201underneath carbon layer202, as shown in cross section400A. In other embodiments, in which carbon layer202comprises one or more sheets of graphene, the high k etch of block103may stop at carbon layer202, and not overetch into substrate201. The high k etch may comprise a wet etch, which may be selected so as not to damage carbon layer202.

In block104, a second dielectric501is deposited using ALD over the device ofFIG. 4, as shown inFIG. 5.FIG. 5illustrates an embodiment of a cross section500A and a top view500B of the device ofFIG. 4after deposition of the second dielectric501. The second dielectric501is formed using ALD with no seed layer; therefore, second dielectric501does not form on carbon layer202, but will form good coverage on nitride layers302, gate metal301, first dielectric203, and substrate201. Second dielectric501may also form on the overetched portion of substrate201located under carbon layer202in embodiments in which carbon layer202comprises carbon nanotubes. The second dielectric501comprises the spacer for the finished FET (discussed below with respect toFIG. 8and block107). Use of ALD to form the second dielectric501allows for precise control of the thickness of second dielectric501, anywhere in the range of about 10 angstroms to about 100 nanometers. The second dielectric501may comprise a low k material in some embodiments.

In block105, metal layer601is formed over the device ofFIG. 5, and chemical mechanical polishing (CMP) is performed to expose the top portion of second dielectric501located on top of the gate electrodes on nitride layers302.FIG. 6illustrates an embodiment of a cross section600A and a top view600B of the device ofFIG. 5after deposition of metal601and CMP. Metal layer601may comprise palladium in embodiments in which a p-type carbon FET is being formed, or may comprise aluminum in embodiments in which an n-type carbon FET is being formed.

In block106, the metal layer601of the device ofFIG. 6is patterned to form source and drain bars over carbon layer202, removing the portion of metal601that is located on the surface of the substrate201, as shown inFIG. 7.FIG. 7illustrates an embodiment of a cross section and a top view of the device ofFIG. 6after patterning of source and drain bars, which comprise the remaining portion of metal601located on carbon layer202after patterning. Patterning of metal layer601may be performed using a hard mask, such as oxide, or a soft mask in some embodiments. The metal601that comprises the source and drain bars provides an electrical connection to the source and drain regions of the finished FET, which are located in carbon layer202.

In block107, a passivation layer801is formed over device700, and metal contacts for the gate, source, and drain of the finished FET are formed, as shown in FIG.8.FIG. 8illustrates an embodiment of a cross section800A and a top view800B of a carbon FET after formation of gate, source, and drain contacts802and803, and a passivation layer801. The top gate, source, and drain contacts formed in block107may comprise the same metal as metal layer601in some embodiments. Gate contact802is located on top of the gate electrode comprising second dielectric501, nitride302, and gate metal301, which is located on top of the first dielectric203and the channel region804of carbon layer202. Source and drain contacts803are located over source and drain bars comprising metal601, and the source/drain regions805of the FET, which are located in carbon layer202. Passivation layer801may comprise a relatively thick layer of oxide or nitride in some embodiments. Second dielectric501comprises the spacer of the carbon-based FET shown inFIG. 8, and is located adjacent to and on top of the gate electrode. Because second dielectric501is deposited using ALD in block104, the thickness of the spacer is adjustable, and may be made as thin a necessary to minimize underlap between the gate metal301and the source/drain regions in carbon layer202, thereby reducing the parasitic resistance and power consumption of the carbon-based FET.

The technical effects and benefits of exemplary embodiments include formation of a spacer for a carbon-based FET with precise thickness control, anywhere in the range from about 10 angstroms to about 100 nanometers or greater.