Field effect transistor devices with low source resistance

A semiconductor device includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region. The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region. A source ohmic contact overlaps at least one of the source contact regions and the body contact region. A minimum dimension of a source contact area of the semiconductor device is defined by an area of overlap between the source ohmic contact and the at least one source contact region.

FIELD OF THE INVENTION

The present invention relates to electronic devices and fabrication methods. More particularly, the present invention relates to high power insulated gate transistors and fabrication methods.

BACKGROUND

Power devices made with silicon carbide (SiC) are expected to show great advantages as compared to those on silicon for high speed, high power and/or high temperature applications due to the high critical field and wide band gap of SiC. For devices capable of blocking high voltages, such as voltages in excess of about 5 kV, it may be desirable to have bipolar operation to reduce the drift layer resistance via conductivity modulation resulting from injected minority carriers. However, one technical challenge for bipolar devices in silicon carbide is forward voltage degradation over time, possibly due to the presence of Basal Plane Dislocations (BPD) in single crystals of silicon carbide. Thus, unipolar devices such as SiC Schottky diodes and MOSFETs are typically used for high power applications, e.g., up to 10 kV or more.

SiC DMOSFET devices with a 10 kV blocking capability have been fabricated with a specific on-resistance of about 100 mΩ×cm2. DMOSFET devices may exhibit very fast switching speeds of, for example, less than 100 ns, due to their majority carrier nature. However, as the desired blocking voltage of devices increases, for example up to 15 kV or more, the on-resistance of a MOSFET device may increase substantially, due to the corresponding increase in the drift layer thickness. This problem may be exacerbated at high temperatures due to bulk mobility reduction, which may result in excessive power dissipation.

With the progress of SiC crystal material growth, several approaches have been developed to mitigate BPD related problems. See, e.g., B. Hull, M. Das, J. Sumakeris, J. Richmond, and S. Krishinaswami, “Drift-Free 10-kV, 20-A 4H—SiC PiN Diodes”, Journal of Electrical Materials, Vol. 34, No. 4, 2005. These developments may enhance the development and/or potential applications of SiC bipolar devices such as thyristors, GTOs, etc. Even though thyristors and/or GTOs may offer low forward voltage drops, they may require bulky commutating circuits for the gate drive and protections. Accordingly, it may be desirable for a SiC bipolar device to have gate turn-off capability. Due to their superior on-state characteristics, reasonable switching speed, and/or excellent safe-operation-area (SOA), 4H—SiC insulated gate bipolar transistors (IGBTs) are becoming more suitable for power switching applications.

SUMMARY

A semiconductor device according to some embodiments includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region. The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region, and a source ohmic contact is in contact with the source contact regions and the body contact region.

The body contact region may include a plurality of body contact regions that are interspersed between the source contact regions. The plurality of body contact regions may be spaced apart from the channel region by the lateral source region.

The source ohmic contact may be in contact with the source region in a source contact area and the source ohmic contact may be in contact with the body contact region in a body contact region area.

In some embodiments, a ratio of a minimum dimension p1of the contact region area to a minimum dimension w1of the well region may be greater than 0.2. In further embodiments, the ratio of the minimum dimension p1of the contact region area to the minimum dimension w1of the well region may be greater than about 0.3.

The drift region may include a wide bandgap semiconductor material, such as silicon carbide.

The source region has a sheet resistance and the source ohmic contact has a sheet resistance that is greater than 75% of the contact resistance of the source region, and in some embodiments is greater than the contact resistance of the source region.

The device may have a reverse blocking voltage in excess of 1000 volts and a current density greater than 200 amps per square centimeter.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

Some embodiments of the invention are described with reference to semiconductor layers and/or regions which are characterized as having a conductivity type such as n-type or p-type, which refers to the majority carrier concentration in the layer and/or region. Thus, n-type material has a majority equilibrium concentration of negatively charged electrons, while p-type material has a majority equilibrium concentration of positively charged holes. Some material may be designated with a “+” or “−” (as in n+, n−, p+, p−, n++, n−−, p++, p−−, or the like), to indicate a relatively larger (“+”) or smaller (“−”) concentration of majority carriers compared to another layer or region. However, such notation does not imply the existence of a particular concentration of majority or minority carriers in a layer or region.

Some embodiments of the invention provide silicon carbide (SiC) insulated gate devices that are suitable for high power and/or high temperature applications.

FIG. 1is a circuit diagram of a metal oxide semiconductor field effect transistor (MOSFET) device10. As shown therein, a MOSFET device generally includes three terminals, namely, a drain terminal (D), a source terminal (S) and a gate terminal (G). The gate-to-source voltage of the device is denoted VGS, while the drain-to-source voltage of the device is denoted VDS. The device has a built in source resistance RSand a built-in drain resistance RDbased on the physical characteristics of the device. The voltage over the built-in source resistance RSis denoted VRs.

In a MOSFET device, current passing through a channel of the device from the drain to the source is regulated by applying a voltage to the gate. The gate is insulated from the channel by a gate insulator, such as silicon dioxide. As the voltage on the gate terminal is increased, current passing through the device may increase.

FIG. 2is a graph illustrating hypothetical (curve102) and actual (104) on-state current-voltage characteristics for a MOSFET device for a given gate-to-source voltage (VGS). As shown inFIG. 2, for a given gate voltage, the current through the device (ID) increases as the voltage between the drain and source (VDS) increases, up to a saturation point. In actual devices, the actual saturation current of a transistor is typically less than the ideal saturation current. Part of the reason for this relates to the source resistance of the device.

In particular, as the drain current IDpassing through the device increases, the amount of voltage dropped over the source resistance RSincreases in direct proportion.FIG. 3is a graph illustrating the effect of source resistance on gate voltage. InFIG. 3, the voltage from the gate terminal to the source terminal is denoted VGS. A portion of the gate voltage VGSapplied to the device across the gate and source terminals is dropped over the internal source resistance RSof the device. That portion of the gate voltage is denoted VRsinFIG. 3. The remainder of the gate-to-source voltage appears as a voltage across the gate insulator, denoted VGS,intinFIG. 3. Thus, VGSis equal to the sum of VRsand VGS,int.

As shown inFIG. 3, the gate-to-source voltage may remain constant as the drain current increases. However, the portion of the gate voltage VGSthat is dropped over the internal source resistance of the device, VRs, increases as the drain current IDincreases, while the portion of the gate-to-source voltage that appears as a voltage across the gate insulator, VGS,int, decreases as the drain current IDincreases.

Thus, as the drain current increases the portion of the gate voltage that is being used to maintain the channel decreases, which may cause the device to go into saturation at a lower level of drain-to-source voltage. Accordingly, a high source resistance can adversely affect the operation of a MOSFET or other insulated gate controlled device.

A unit cell10of a MOSFET structure according to some embodiments is shown inFIG. 4. The device10ofFIG. 1includes an n− drift epitaxial layer14on an n-type, 8° off-axis 4H—SiC substrate12. The n− drift layer14may have a thickness of about 100 μm to about 120 μm, and may be doped with n-type dopants at a doping concentration of about 2×1014cm−3to about 6×1014cm−3for a blocking capability of about 10 kV. Other doping concentrations/voltage blocking ranges are also possible.

The structure further includes a p+ well region18and an n+ source region20that may be formed by selective implantation of, for example, aluminum and nitrogen, respectively. The junction depth of the p+ well region18may be about 0.5 μm, although other depths are possible. The structure10further includes a p+ contact region22that extends from a surface of the drift layer14into the p+ well region18. A junction termination (not shown) may be provided around the device periphery.

All of the implanted dopants may be activated by annealing the structure at a temperature of about 1600° C. with a silicon over pressure and/or covered by an encapsulation layer such as a graphite film. A high temperature anneal may damage the surface of the silicon carbide epitaxy. In order to reduce such damage, a graphite coating may be formed on the surface of the device. Prior to annealing the device to activate the implanted ions, a graphite coating may be applied to the top/front side of the structure in order to protect the surface of the structure during the anneal. The graphite coating may be applied by a conventional resist coating method and may have a thickness of about 1 μm. The graphite coating may be heated to form a crystalline coating on the drift layer14. The implanted ions may be activated by a thermal anneal that may be performed, for example, in an inert gas at a temperature of about 1600° C. or greater. In particular the thermal anneal may be performed at a temperature of about 1600° C. in argon for 5 minutes. The graphite coating may help to protect the surface of the drift layer14during the high temperature anneal.

The graphite coating may then be removed, for example, by ashing and thermal oxidation.

After implant annealing, a field oxide of silicon dioxide (not shown) having a thickness of about 1 μm may be deposited and patterned to expose the active region of the device.

A gate oxide layer36may be formed by a gate oxidation process, with a final gate oxide thickness of 400-600 Å.

In particular, the gate oxide may be grown by a dry-wet oxidation process that includes a growth of bulk oxide in dry O2followed by an anneal of the bulk oxide in wet O2as described, for example, in U.S. Pat. No. 5,972,801, the disclosure of which is incorporated herein by reference in its entirety. As used herein, anneal of oxide in wet O2refers to anneal of an oxide in an ambient containing both O2and vaporized H2O. An anneal may be performed in between the dry oxide growth and the wet oxide growth. The dry O2oxide growth may be performed, for example, in a quartz tube at a temperature of up to about 1200° C. in dry O2for a time of at least about 2.5 hours. Dry oxide growth is performed to grow the bulk oxide layer to a desired thickness. The temperature of the dry oxide growth may affect the oxide growth rate. For example, higher process temperatures may produce higher oxide growth rates. The maximum growth temperature may be dependent on the system used.

In some embodiments, the dry O2oxide growth may be performed at a temperature of about 1175° C. in dry O2for about 3.5 hours. The resulting oxide layer may be annealed at a temperature of up to about 1200° C. in an inert atmosphere. In particular, the resulting oxide layer may be annealed at a temperature of about 1175° C. in Ar for about 1 hour. The wet O2oxide anneal may be performed at a temperature of about 950° C. or less for a time of at least about 1 hour. The temperature of the wet O2anneal may be limited to discourage further thermal oxide growth at the SiC/SiO2interface, which may introduce additional interface states. In particular, the wet O2anneal may be performed in wet O2at a temperature of about 950° C. for about 3 hours. The resulting gate oxide layer may have a thickness of about 500 Å.

In some embodiments, the dry O2oxide growth may be performed at a temperature of about 1175° C. in dry O2for about 4 hours. The resulting oxide layer may be annealed at a temperature of up to about 1175° C. in an inert atmosphere. In particular, the resulting oxide layer may be annealed at a temperature of about 1175° C. in Ar for about a time duration ranging from 30 min to 2 hours. Then the oxide layer receives an anneal in NO ambient at a temperature ranging from 1175 C to 1300 C, for a duration ranging from 30 minutes to 3 hours. The resulting gate oxide layer may have a thickness of about 500 Å.

After formation of the gate oxide36, a polysilicon gate32may be deposited and doped, for example, with boron followed by a metallization process to reduce the gate resistance. Al/Ni contacts may be deposited as the p-type ohmic source contact metal28, and Ni as the n-type drain contact metal26. All contacts may be sintered in a Rapid Thermal Annealer (RTA), and thick Ti/Au layers may be used for pad metals.

Referring toFIG. 4, the source resistance of a MOSFET device has two primary components, namely, the contact resistance RCbetween the source ohmic contact34and the source region20, and the sheet resistance Rsheetin the source region20between the source ohmic contact34and the channel. Thus, RS=RC+Rsheet. In a conventional silicon-based MOSFET device, the sheet resistance Rsheetis the dominant factor in determining the source resistance, because it is possible to form very low resistivity ohmic contacts to silicon and other narrow-bandgap semiconductors. However, in wide bandgap semiconductors (i.e., semiconductors having a bandgap greater than about 2.0 V), including compound semiconductor materials, such as silicon carbide and gallium nitride, diamond, and ZnO, the contact resistance RCmay be the dominant contributor to the source resistance. In particular, it is difficult to form very low resistivity ohmic contacts to silicon carbide and other wide bandgap materials because of the high energy barrier associated with such materials.

FIGS. 5 and 6are plan views illustrating layouts of conventional power MOSFET devices. In a conventional power MOSFET device, the layout is designed to reduce or minimize sheet resistance under the assumption that contact resistance is less important than sheet resistance. Thus, referring toFIG. 5, a conventional power MOSFET device typically includes a p-well18formed in a drift layer14, an n+ source region20in the p-well18, and a p+ contact region22in the n+ source region20. Referring toFIG. 6, a source contact34is formed on the n+ source region20and the p+ contact region22. A gate32is formed over the p-well18and overlaps the periphery of the n+ source region20and adjacent portions of the drift layer14. Current flow from the drain to the source is indicated by the arrows42inFIG. 5.

As noted above, in a wide bandgap semiconductor material system, the source resistance may be more affected by the contact resistance of the source ohmic contact than by the sheet resistance of the source layer. Accordingly, to decrease the source resistance of a wide bandgap power semiconductor device, it may be desirable to decrease the contact resistance of the source ohmic contact. In general, contact resistance can be decreased by increasing the minimum dimension of the contact, which is the smallest dimension of the contact in any direction. However, simply increasing the minimum dimension of the source ohmic contact of an electronic device can undesirably increase the cell to cell spacing, or pitch, of the device. The pitch of a MOSFET device may be proportional to the width of the p-well region of the device. Increasing the pitch of the device reduces the density of the devices that can be formed on a single substrate, reducing the devices yielded and increasing manufacturing costs.

According to some embodiments, an insulated gate device layout is provided that increases the minimum dimension of the source ohmic contact without increasing the pitch of the device and/or the width of the p-well region of the device. A device layout according to some embodiments may increase the sheet resistance of the device. Such an effect may be highly undesirable in a device based on a narrow bandgap semiconductor material. However, since sheet resistance is not the dominant factor in determining source resistance of a wide bandgap device, such a tradeoff may be acceptable for wide bandgap devices. In devices according to some embodiments, a ratio of the source sheet resistance to the source contact resistance may be greater than 0.75 (i.e. Rsheet/RC>0.75). In some embodiments, the device may have a source contact resistance that is less than the source sheet resistance. That is, in some embodiments, the ratio of the source sheet resistance to the source contact resistance may be greater than 1 (i.e. Rsheet/RC>1), and in further embodiments, the ratio of the source sheet resistance to the source contact resistance may be greater than 5.

FIGS. 7 and 8are plan views illustrating layouts of MOSFET device cells100according to some embodiments, andFIGS. 9 and 10are partial cross sectional illustrations of a cell of a MOSFET device according to some embodiments. In particular,FIG. 9is a cross section taken along line A-A′ ofFIG. 8, whileFIG. 10is a cross section taken along line B-B′ ofFIG. 8.

The device100shown inFIGS. 7-10includes an n− drift epitaxial layer114on an n-type, 8° off-axis 4H—SiC substrate112. The n− drift layer114may have a thickness of about 100 μm to about 120 μm, and may be doped with n-type dopants at a doping concentration of about 2×1014cm−3to about 6×1014cm−3for a blocking capability of about 10 kV.

The structure further includes a p+ well region118and an n+ source region120that may be formed by selective implantation of, for example, aluminum and nitrogen, respectively. The junction depth of the p+ well region118may be about 0.5 μm. The structure100further includes a plurality of p+ contact regions122that extend from a surface of the drift layer114into the p+ well region118. A junction termination (not shown) may be provided around the device periphery.

Referring toFIG. 7, the n+ source region120includes a pair of lateral source regions120A that are parallel to opposing channel regions125in the p-well118. A plurality of source contact regions120B extend between the lateral source regions120A, and the plurality of p+ contact regions122are provided between the source contact regions120B.

Referring toFIG. 8, gate contacts132are formed over the channel regions125and overlap the lateral source regions120A. A source ohmic contact134is formed across the source contact regions120B and the p+ contact regions122. The source ohmic contact134overlaps the source contact regions120B in a source contact region136. The source ohmic contact134overlaps the p+ contact regions122in a body contact region138.

The portion of the source contact regions120B contacted by the source ohmic contact134may have a minimum dimension that is larger than the minimum dimension that can be obtained for a conventional layout such as the layout shown inFIGS. 5 and 6for a similar pitch/p-well size. Accordingly, the source contact resistance may be reduced without substantially increasing the device pitch/p-well size. The “minimum dimension” of a feature refers to the smallest width of the feature in any cross section of the feature. For example, the minimum dimension p1of the body contact region138, the minimum dimension n1of the n-type contact region136and the minimum dimension w1of the p-well region118are shown inFIG. 8.

In a device having a layout as shown inFIGS. 7 and 8, current flow to the source contact flows through the source contact regions120B, as indicated by the arrows142inFIG. 7. The source contact regions120B may have an increased sheet resistance compared to the source region of a device having a conventional layout as shown inFIGS. 5 and 6. However, the increase in sheet resistance may be more than compensated by the decrease in contact resistance, thus providing an overall decrease in the source resistance of the device.

FIG. 11is a graph of on-state current-voltage characteristics for a 7 mm×8 mm 1200 V silicon carbide MOSFET device according to some embodiments. In the device characteristics illustrated inFIG. 11, a drain current (ID) of 377 A was measured at a forward voltage drain-to-source voltage (VDS) of 3.8 V. The current density, normalized to the active area, was over 750 A/cm2.

The on-resistance of a MOSFET device is affected by the drain resistance, the channel resistance and the source resistance of the device. Accordingly, reducing the source resistance of the device also reduces the on-resistance of the device.

A wide bandgap MOSFET device having a layout according to some embodiments may be capable of substantially increased saturation current due to the lower on-resistance of the device and the fact that increased current levels have less of a de-biasing effect on the gate. That is, because of the lower source resistance, less voltage will be developed over the source resistance as the drain current increases. Thus, more of the gate-to-source voltage is applied to the channel of the device.

FIG. 12is an idealized cross section of a device having a layout in accordance with some embodiments. In particular,FIG. 12illustrates some dimensions of a device having a layout in accordance with some embodiments. For example, as shown inFIG. 12, the minimum dimension of the implanted cell area (i.e. the p-well118) is denoted as width w1inFIG. 12. It will be appreciated, however, that the minimum dimension of the p-well118may occur in a dimension that is different from the plane of the device illustrated inFIG. 12. For example, the minimum dimension of the p-well118may occur in a dimension that is perpendicular to the plane of the device illustrated inFIG. 12.

The minimum dimension of the n-type contact area is denoted as width n1inFIG. 12, while the minimum dimension of the p-type contact area is denoted as width p1inFIG. 12. The n-type contact area may be defined as the area of overlap between the source ohmic contact134and the n+ source region120, while the p-type contact area may be defined as the area of overlap between the source ohmic contact134and the p+ contact regions122.

An insulated gate bipolar transistor (IGBT) device200according to some embodiments is illustrated inFIG. 13. As shown therein, the IGBT device includes an n− drift epitaxial layer214on a p-type epitaxial layer212. The p-type epitaxial layer212is formed on a p-type, 8° off-axis 4H—SiC substrate210. The n− drift layer214may have a thickness of about 100 μm to about 120 μm, and may be doped with p-type dopants at a doping concentration of about 2×1014cm−3to about 6×1014cm−3for a blocking capability of about 10 kV.

The IGBT structure200further includes a p+ well region218and an n+ source/emitter region220that may be formed by selective implantation of, for example, aluminum and nitrogen, respectively. The junction depth of the p+ well region218may be about 0.5 μm. The structure200further includes a plurality of p+ body contact regions222that extend from a surface of the drift layer214into the p+ well region218. The conductivity types may be reversed in some embodiments.

A gate contact232is on a gate insulator236, a source/emitter contact234is on the source contact regions220and the body contact regions222. A collector contact226contacts the substrate210.

According to some embodiments, a transistor device may have a ratio of n1to w1that is greater than 0.2. In further embodiments, a transistor device may have a ratio of n1to w1that is greater than about 0.3. In further embodiments, a transistor device may have a ratio of n1to w1that is in the range of about 0.2 to 1. In further embodiments, a transistor device may have a ratio of n1to w1that is in the range of about 0.3 to 1. In further embodiments, transistor device may have a ratio of n1to w1that is greater than 0.5. For example, the minimum dimension n1of the n-type contact area of a device having a layout according to some embodiments may be about 2 μm for a device having a minimum dimension of the implanted cell area of 6 μm.

According to some embodiments, a transistor device may have a ratio of p1to w1that is greater than 0.2. In further embodiments, a transistor device may have a ratio of p1to w1that is greater than about 0.3. In further embodiments, a transistor device may have a ratio of p1to w1that is greater than about 0.5. In further embodiments, a transistor device may have a ratio of p1to w1that is in the range of about 0.2 to 0.5. In further embodiments, a transistor device may have a ratio of p1to w1that is in the range of about 0.2 to 1.

Some embodiments provide transistor devices having increased current densities. Current density is defined as the total current divided by the cross sectional area of the chip. For example, a wide bandgap transistor device according to some embodiments may be capable of current densities in excess of 200 A/cm2and a blocking voltage of 1000 V or more. A wide bandgap transistor device according to further embodiments may be capable of a current of 100 A or greater at current densities in excess of 200 A/cm2, a forward voltage drop of less than 5 V and a blocking voltage of 1000 V or more. A wide bandgap transistor device according to still further embodiments may be capable of a current of 100 A or greater at current densities in excess of 300 A/cm2, a forward voltage drop of less than 5 V and a blocking voltage of 1000 V or more.

A semiconductor device according to some embodiments has a reverse blocking voltage in excess of 1000 volts and a current density greater than 200 amps per square centimeter at a current greater than 100 A.

A semiconductor device according to further embodiments has a reverse blocking voltage of 1000 volts or more and a forward current capability greater than 100 A at a forward voltage of 5 volts or less.

A metal-oxide semiconductor field effect transistor device according to some embodiments has a reverse blocking voltage of 1200 volts or more and a forward current capability greater than 100 A.

A metal-oxide semiconductor field effect transistor device according to some embodiments has a reverse blocking voltage of 1000 volts or more and a differential on-resistance less than 8 mOhms-cm2.

A semiconductor device having a blocking voltage less than 1000 V and configured to pass forward current at a current density greater than 200 amps per square centimeter at a forward voltage drop of 5 V or less.

Some embodiments may enable wide bandgap transistor devices to achieve drain currents of 100 Amps or higher at a drain to source voltage that is less than 4 Volts in a device having a cell pitch of less than 20 μm. Some embodiments may enable wide bandgap transistor devices to achieve drain currents of 100 Amps or higher at a drain to source voltage that is less than 4 Volts in a device having a cell pitch of less than 10 μm. Some embodiments may enable wide bandgap transistor devices to achieve drain currents of 80 Amps or higher at a drain to source voltage that is less than 5 Volts in a device having a cell pitch of less than 10 μm.

An IGBT device according to some embodiments with a voltage blocking capability of 10 kV or greater may have a specific on-resistance of less than 14 mOhm-cm2with a forward voltage drop of 5.2 V or less at a current density of 100 A/cm2.

It will be appreciated that although some embodiments of the invention have been described in connection with silicon carbide IGBT and MOSFET devices having n-type drift layers, the present invention is not limited thereto, and may be embodied in devices having p-type substrates and/or drift layers. Furthermore, the invention may be used in many different types of devices, including but not limited to insulated gate bipolar transistors (IGBTs), MOS controlled thyristors (MCTs), insulated gate commutated thyristors (IGCTs), junction field effect transistors (JFETs), high electron mobility transistors (HEMTs), etc.