RF passive mixer with DC offset tracking and local oscillator DC bias level-shifting network for reducing even-order distortion

An apparatus and method for tracking a DC offset in a mixer circuit used in wireless communication systems and for providing local oscillator DC bias level-shifting to reduce even order distortion resulting from the DC offset is described. The apparatus has an input coupled to a mixer circuit output for receiving a DC voltage present on the mixer circuit output. The DC voltage includes an offset component. A level shifting circuit is coupled to the input for level shifting the received DC voltage a predetermined amount. An output of the level shifting circuit is coupled to a local oscillator input for outputting the level shifted DC voltage to the local oscillator input. The shift in the DC bias level at the local oscillator input of the mixer circuit provided by the apparatus and method reduces even order distortion in the mixer circuit, including second order intermodulation (IM2) distortion.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Embodiments of the present invention relate to mixer circuits for use in communication systems, and in preferred embodiments, to an apparatus and method for tracking a DC offset in a direct conversion passive mixer circuit used in wireless communication systems and for providing local oscillator DC bias level-shifting to reduce even order distortion, including second order intermodulation (IM2) distortion, resulting from the DC offset, and to wireless communication systems that employ such an apparatus and method.

2. Description of Related Art

Mixers are used in transceivers in many commercial wireless applications, including wireless Local Area Networks (LANs), wireless personal communication devices including radios, cellular telephones, mobile cordless telephones, Personal Digital Assistants (PDAs), Personal Computer Memory Card International Association (PCMCIA) computer interface applications, telemetry systems, global positioning systems (GPS) and other radio frequency (RF) devices.

In such applications, the transmitted and received signal is an RF signal. The RF signal consists of a baseband signal modulated on a carrier frequency signal. Because the baseband signal is a relatively low frequency signal, the baseband signal is modulated onto the higher frequency carrier signal before transmission. Conversely, because the carrier frequency is a relatively high frequency signal, the RF signal is down-converted to a lower frequency upon reception and before further processing.

Conventional heterodyne receivers down convert a RF signal to a baseband signal using one or more intermediate stages in which the RF signal is converted to one or more intermediate-frequency signals, lower than the RF signal, until the base-band frequency is reached. A heterodyne transmitter generates a higher frequency RF signal from a baseband signal using one or more intermediate stages to up-convert the frequency.

A homodyne or “direct conversion” receiver directly down-converts RF signals to baseband frequency without intermediate stages. Analogously, a direct conversion transmitter up-converts from base-band to RF without intermediate stages. A direct conversion receiver may be defined more generally as a receiver that directly converts any frequency to DC. Direct conversion transceivers are particularly useful in multi-band transceivers, because of the elimination of the intermediate frequency passband filtering components and the resulting space savings. In addition, in direct conversion transceivers there is a corresponding reduction in the complexity of the transceivers.

Mixers are used in transceivers to convert a signal from a low frequency to a high frequency or a high frequency to a low frequency by mixing the signal with a local oscillator signal. The local oscillator frequency can be above or below the frequency of the desired signal to produce a sum and a difference frequency, one of which is the frequency of interest. There are many types of mixers including unbalanced, single and double balanced mixers. Mixers may be further categorized as passive or active.

Conventional mixers are implemented in various semiconductor technologies such as silicon and gallium arsenide with diodes, bipolar junction transistors (BJT), field effect transistors (FET), or other variations of these types. Increasingly, integrated circuits (ICs) having complementary metal-oxide semiconductor (CMOS) technology are being used in RF circuits, including RF circuits for wireless (LAN) networks.

Thus, increasingly, direct conversion transceivers implemented with CMOS technology are being used in such wireless communication applications. Mixers used in direct conversion transceivers generally require low flicker (1/f) noise. The 1/f noise is an intrinsic noise phenomenon found in semiconductor devices. Active mixer circuits implemented in CMOS generally suffer from 1/f problems. Passive mixer circuits implemented in CMOS, on the other hand, generally exhibit a low noise figure. Thus, it is advantageous to use passive mixer circuits in direct conversion transceivers implemented with CMOS technology due to the improved noise figure.

A conventional CMOS implemented passive mixer circuit used in a receiver is shown inFIG. 1. InFIG. 1, the RF input signal to be down converted is fed into input terminals101and103and through capacitors112and114to the source terminals of the NMOS FET differential pairs102(M1),104(M2) and106(M3),108(M4) of passive mixer circuit100. The local oscillator signal (LO) to be mixed with the RF signal is fed into input terminal105and through capacitor116to the gate terminals of FETs102and108. The 180-degree phase shifted or “complementary” local oscillator signal (LOC) to be mixed with the RF signal is fed into input terminal107and through capacitor118to the gate terminals of FETs104and106. A transformer or other phase shifting device (not shown) can provide this phase shift input.

A baseband (BB) signal is output at output terminals113and115. DC power and biasing are provided via VBIASterminal109through resistors120and122to the drain terminals of differential pairs102,104and106,108of passive mixer circuit100. Capacitors128and130short higher frequencies appearing on output terminals113and115to VBIASterminal109. DC power and biasing are also provided via VLO BIASterminal111through resistors124and126to the gate terminals of differential pairs102,104and106,108.

Because the differential pairs102,104and106,108are driven by local oscillator signals that are 180 degrees out of phase, only one of FET pair102,108or FET pair104,106is on at a given time. Passive mixer circuit100multiplies the incoming signal RF-in with the local oscillator signal, producing sum and difference frequencies.

High linearity performance is required in mixer circuits used in wireless communication applications. Passive mixer circuits such as the one shown inFIG. 1generally have poor linearity performance. One parameter by which the linearity performance of a mixer may be defined is the even order distortion of the mixer. The most significant form of even order distortion in a mixer is second order intermodulation (IM2) distortion. IM2 occurs when two interfering signals mix with each other through a second order nonlinearity to produce an intermodulation product at the sum and difference frequencies of the two interferers. IM2 may be produced, for example, by device mismatches, parametric imbalance, imperfect layout, and other device characteristic inequalities that cause imbalances in a differential pair.

A particular cause of IM2 in a passive mixer circuit like that shown inFIG. 1are DC offsets caused by LO leakage. There are several mechanisms through which LO leakage may occur. For example, there may be conductive paths between components. This occurs because there is limited isolation from the LO input terminals of the mixer to the RF input terminals of the mixer. There may also be limited reverse isolation through the low-noise amplifying stages preceding the mixer. A parasitic signal path for signals through the substrate, as well as a lateral signal path through the substrate, can also occur. In addition to the conductive paths, there may also be radiated paths via the bond wires used to interconnect the circuit blocks to the outside world. The bond wires act as antennas and couple RF energy, such as that of the LO, to adjacent pins. The lack of LO isolation causes self mixing in the direct down converter that manifests as a DC offset at the baseband terminals of the mixer. This DC offset then negatively affects the bias voltages of the passive mixer100.

Referring again toFIG. 1, differential pair102,104will be used to describe a typical biasing method for the passive mixer100. Differential pair106,108is biased in a similar manner. A DC bias voltage of 1.2 Volts (V) is provided at VLO BIASterminal111. Thus, the DC voltage present at the gate terminals of NMOS FETs102or104, respectively, is 1.2 V. A typical value of DC bias voltage provided at VBIASterminal109is 0.6 V. Because mixer100is a passive mixer, there is no current flow through NMOS FETs102or104. Because there is no current flow through NMOS FETs102or104, the DC voltage present at output terminals113and115, and also at the respective drain terminals of NMOS FETs102or104, should ideally be 0.6 V, i.e. the DC voltage present at VBIASterminal109.

As stated above, because in operation FETs102and104are driven by local oscillator signals that are 180 degrees out of phase, only one of them is on at a given time. When either of the FETs102and104are turned on by the LO or LOC signals, respectively, the DC voltage present at their source terminals will be that present at their respective drain terminals, that is, ideally 0.6 V.

However, because of the DC offset manifested at the output terminals113and115by the LO self-mixing, the actual DC voltage present on output terminal113may vary from the DC voltage present on output115. As an example, instead of the ideal DC voltage of 0.6 V that should be present at both output terminals113and115, a DC voltage of 0.7 V may be present at output terminal113, while a DC voltage of 0.5 V may be present at output terminal115. Thus, in the present example there is a DC offset between output terminals113and115of 0.2 V. Therefore, when FET102is turned on, the DC voltage at its source terminal will be pulled up to 0.7 VDC. When FET104is turned on, the DC voltage at its source terminal will be pulled down to 0.5 VDC.

Referring now toFIGS. 2A through 2D, the negative effects on the linear performance of passive mixer100of LO self-mixing and the resulting DC offsets are illustrated.FIGS. 2A through 2Dshow waveforms present at the terminals of FETs102and104during operation of the passive mixer100.

FIG. 2Arepresents the LO and LOC signals superimposed on one another on a horizontal axis representing time t. During operation of passive mixer100, the LO and LOC signals are input to the gate terminals of FETs102and104, respectively, as shown inFIG. 1. The LO and LOC signals switch their respective FETs on and off. As discussed above, the LO and LOC signals are 180 degrees out of phase and thus when FET102is switched on, FET104is switched off, and vice versa.

FIG. 2Brepresents output signals seen at the drain terminals of FETs102and104. The slow-varying solid lines represent the baseband signal waveforms present at the terminals of FETs102and104during operation of the passive mixer100.FIG. 2Bshows that due to the DC offset of 0.2 V introduced by the LO self-mixing, the DC voltages at the drain terminals of FETs102and104deviate from each other by 0.2 V. Thus, the output signals present on the drain terminals of FETs102and104ride on DC levels that are offset by 0.2 V.

FIG. 2Crepresents the signal input seen at the source terminals of FETs102and104. When either FET102or FET104turns on, the DC voltage at its drain terminal will be extended to its source terminal. Thus, as shown inFIG. 2C, when FET102turns on, the RF input signal at its source terminal will ride on a DC level that is shifted up from the original DC level of 0.6 V to 0.7 V. Similarly, when FET104turns on, the RF signal input at its source terminal will ride on a DC level that is shifted down from the original DC level of 0.6 V to 0.5 V.

FIG. 2Dshows the gate-to-source voltage (Vgs) of FETs102and104. As shown inFIG. 2D, the gate-to-source voltage of FET102(Vgs1) is not symmetrical to the gate-to-source voltage of FET104(Vgs2). This asymmetry results from the different DC voltages present on the source terminals of FETs102and104when they are turned on. When FET102is turned on, 0.7 V is present on its source terminal. The DC voltage from gate terminal to source terminal of FET102is determined by subtracting the DC voltage at its source terminal from the DC voltage at its gate terminal. The DC voltage from gate to source of FET102is 1.2 V−0.7 V=0.5 V. Thus, the DC level of signal Vgs1will be shifted down from 0.6 V to 0.5 V. This results in reduced turn-on time for FET102, as shown inFIG. 2D.

Similarly, when FET104is turned on, 0.5 V is present on its source terminal. The DC voltage from gate terminal to source terminal of FET104may be determined in the same manner as above to be 1.2 V−0.5 V=0.7 V. Thus, the DC level of signal Vgs2will be shifted up from 0.6 V to 0.7 V This results in increased turn-on time for FET104, as shown inFIG. 2D. The imbalance between Vgs1and Vgs2of passive mixer100shown inFIG. 2Dresults in increased IM2 distortion. Thus, the linearity performance of passive mixer100is degraded by the DC offset.

Efforts have been made to reduce LO self-mixing in order to reduce IM2 distortion. For example, attempts have been made to provide better isolation between the LO input terminals and RF input terminals of the mixer. However, these efforts have not been completely successful because parasitic and lateral signal paths through the substrate, as well as conductive paths between components, are difficult to overcome.

Thus, there remains a need for a passive mixer circuit for use in a direct conversion transceiver employed in wireless communication applications which IM2 distortion due to LO leakage induced DC offsets.

SUMMARY OF THE DISCLOSURE

Therefore, it is an advantage of embodiments of the present invention to overcome the problems in the existing art described above by providing a DC offset tracking and LO DC bias level-shifting network for use with a mixer circuit that reduces or substantially eliminates even order distortion, including IM2 distortion, due to LO leakage induced DC offsets.

According to embodiments of the invention, a DC offset tracking and LO DC bias level-shifting network for use with a mixer circuit having a local oscillator input and an output is described. The network includes an input coupled to the mixer circuit output for receiving a DC voltage present on the mixer circuit output. The DC voltage present on the mixer circuit output includes a DC offset component.

The network further includes a level shifting circuit coupled to the input for level shifting the received DC voltage a predetermined amount. An output of the level shifting circuit is coupled to the local oscillator input for outputting the level shifted DC voltage to the local oscillator input.

According to a preferred embodiment of the invention, the level shifting circuit includes a first P-Channel MOSFET (PFET) configured as a source follower. The gate terminal of the first PFET may be coupled to the mixer circuit output for receiving a DC voltage present on the mixer circuit output. The first PFET is biased such that when it is turned on, a value of a DC voltage on its source terminal varies from the received DC voltage present on its gate terminal by a predetermined amount. The predetermined amount may be selected by adjusting a first current source coupled to the source terminal of the first PFET.

The level shifting circuit further includes a second PFET having its source terminal coupled to the source terminal of the first PFET. The second PFET may be a long channel device having a large “on” resistance to DC current flow. The drain terminal of the second PFET may be coupled to the local oscillator input. When the second PFET is turned on, a value of a DC voltage present on its drain terminal is substantially the same as the value of the DC voltage present on its source terminal and is provided to the to the local oscillator input.

The level shifting circuit further includes an N-Channel MOSFET (NFET) for turning on the second PFET. The NFET has a gate terminal coupled to the source terminals of the first and second PFETs. A current source is coupled to the source terminal of the NFET and is adjustable for biasing the NFET and the second PFET.

These and other features and advantages of embodiments of the invention will be apparent to those skilled in the art from the following detailed description of embodiments of the invention, when read with the drawings and appended claims.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Embodiments of the present invention relate, generally, to communication systems and processes which have RF transceivers employing mixers for converting a signal from a low frequency to a high frequency or a high frequency to a low frequency by mixing the signal with another signal.

RF transceivers employing mixers according to embodiments of the present invention may be employed in a variety of communications electronics, including wireless transmission systems as well as wired systems. Thus, embodiments of the invention described herein may involve various forms of communications systems. However, for purposes of simplifying the present disclosure, preferred embodiments of the present invention are described herein, in relation to wireless applications, including, but not limited to wireless Local Area Networks (LANs), wireless personal communication devices including radios, cellular telephones, mobile cordless telephones, Personal Digital Assistants (PDAs), Personal Computer Memory Card International Association (PCMCIA) computer interface applications, telemetry systems, global positioning systems (GPS) and other RF devices. In these applications, it is typically desirable to improve the linearity performance of the RF transceiver.

Communications system nodes such as, but not limited to, notebook computers, workstations, personal computers, PDAs or other electronic processing devices may be interconnected via a wireless LAN. Each Communications system node generally includes a communications controller and a wireless transceiver. The communications controller controls data exchange between the computer system and the wireless transceiver. Example functions of the communications controller include channel selection, organization of data packets for transmission and reception across the LAN, and error correction on received data packets.

FIG. 3is a simplified block diagram of a communications system node300such as a notebook computer, cordless telephone, PDA or other RF device in which embodiments of the present invention may be employed. Communications system node300is preferably part of a wireless LAN, wide area network (WAN), cellular network or other RF application such as, but not limited to, a cordless or wireless telephone system.

Communications system node300includes, but is not limited to, a radio transceiver302, a communications controller304, and antenna306. In one embodiment, the antenna may be incorporated directly into transceiver302. Transceiver302includes transceiver circuits308, a mixer310and a local oscillator312. An RF input and output of mixer310are coupled to antenna306. The LO input of mixer310is coupled to the LO312. Received data and transmitted data are communicated between communications controller304, transceiver circuits308and mixer310.

In operation, the communications controller304controls the flow of data. The receiver portion of transceiver302performs RF demodulation signal processing for communications system node300. In the receive mode, antenna306receives a modulated carrier wave or RF signal and provides it to mixer310. The LO provides a mixing signal corresponding to a selected channel in the appropriate frequency range. Mixer310provides essentially the multiplicative product of the signals from its two inputs to transceiver circuits308. Transceiver circuits308further process the product of the signals and provide a filtered baseband signal to communications controller304.

A circuit schematic of mixer310according to a preferred embodiment of the present invention is shown inFIG. 4. The CMOS implemented passive mixer circuit shown inFIG. 4differs from the conventional passive mixer circuit100shown inFIG. 1by incorporating a DC offset tracking and LO DC bias level-shifting network400in place of the DC power and biasing circuit (including VLO BIASterminal111and resistors124and126) that is shown inFIG. 1.

InFIG. 4, the RF input signal to be down converted is fed into input terminals401and403and through capacitors412and414to the source terminals of the NMOS field effect transistor (FET) differential pairs402(M1),404(M2) and406(M3),408(M4) of passive mixer circuit310. The local oscillator signal (LO) to be mixed with the RF signal is fed into input terminal405and through capacitor416to the gate terminals of FETs402and408. The 180-degree phase shifted or “complementary” local oscillator signal (LOC) to be mixed with the RF signal is fed into input terminal407and through capacitor418to the gate terminals of FETs404and406. A transformer or other phase shifting device (not shown) can provide this phase shift input.

A baseband (BB) signal is output at output terminals413and415. DC power and biasing are provided via VBIASterminal409through resistors420and422to the drain terminals of differential pairs402,404and406,408of passive mixer circuit310. Capacitors428and430short higher frequencies appearing on output terminals413and415to VBIASterminal409.

DC power and biasing are also provided by network400. Network400receives power from power rails VDD and GND. Network400comprises two identical branches, one for operation with each of the two differential pairs of the passive mixer310. For simplicity, only the operation of the branch operating with FETs402and406will be described in detail. Those skilled in the art will recognize that the remaining branch operates in a similar manner in relation to FETs404and408.

The branch of network400operating with FETs402and406comprises FETs432(M5),434(M6) and436(M7), as well as current sources438and440, capacitor442and resistors444,446and448. The drain terminals of FETs402and406are connected to one side of resistor444. The other side of resistor444is connected to the gate terminal of PFET432. Current source438is connected between the VDD power rail and the source terminal of PFET432. The source terminal of PFET432is also connected to the gate terminal of NFET434and the source terminal of PFET436. The drain terminal of PFET432is connected to the GND power rail. The drain terminal of NFET434is connected to the VDD power rail. Current source440is connected between the source terminal of NFET434and the GND power rail. The source terminal of NFET434is also connected to the gate terminal of PFET436. The drain terminal of PFET436is connected to the gate terminals of FETs402and406through resistors446and448, respectively. One side of capacitor442is connected to the VDD power rail. The other side of capacitor442is connected to the source terminals of PFET432and PFET436, as well as to the gate terminal of NFET434.

During operation of passive mixer310, the DC voltage present at the drain terminals of FETs402and406is picked up by resistor444and is present on the gate terminal of PFET432. Resistor444may have a value of, for example, 50 kilohm. Resistor444is not critical to the operation of network400and may, in some embodiments, be left out, depending on the application. Thus, in some embodiments, the drain terminals of FETs402and406may be connected directly to the gate terminal of PFET432.

PFET432is configured as a source follower. The value of current source438may be designed to bias PFET432such that it has a predetermined gate-to-source DC voltage that is matched to the gate-to-source DC voltage of FETs402and406. For example, if the gate-to-source DC voltage of FETs402and406is 0.6 V, the value of current source438may be designed such that the gate-to-source DC voltage of PFET432is also 0.6 V. The DC voltage present at the source terminal of PFET432will be equal to the DC voltage at its gate terminal minus its gate-to-source DC voltage.

The DC voltage present at the source terminal of PFET432will also be present at the gate terminal of NFET434, as well as at the source terminal of PFET436. Capacitor442will short higher frequencies appearing at the source terminal of PFET432to the VDD power rail.

The value of current source440may be designed to properly bias NFET434and PFET436. For example, the value of current source440may be designed such that the DC voltage at the source terminal of NFET434and the gate terminal of PFET436is 0.6 V. The current source440biases NFET434to be active and to turn on PFET436.

PFET436is a long channel device. During operation of the passive mixer310, PFET436provides a large resistance to DC current flow between its source terminal and drain terminal. In one embodiment, PFET436may provide an “on” resistance greater than one gigohm. When PFET436is turned on by NFET434, the value of the DC voltage present at the source terminal of PFET436will also be the value of the DC voltage present at the drain terminal of PFET436. In turn, the value of the DC voltage present at the drain terminal of PFET436will be the value of the DC voltage present at the gate terminals of NFETs402and406, through resistors446and448, respectively.

An example of the beneficial operation of network400will now be described. It will be assumed that, during operation of passive mixer310, LO self-mixing has manifested a DC offset of 0.2 V at the output terminals413and415. Thus, for example, a DC voltage of 0.7 V is present on output terminal413and a DC voltage of 0.5 V is present on output terminal415. The DC voltage of 0.7 V present on output terminal413is picked up by resistor444and appears on the gate terminal of PFET432. In the present example, current source438is designed such that the gate-to-source DC voltage of PFET432is equal to the gate-to-source DC voltage of NFET402, which is 0.6 V.

The DC voltage present at the source terminal of PFET432is thus equal to 0.7 V−(−0.6 V)=1.3 V. Thus, 1.3 V is present at both the gate terminal of NFET434and the source terminal of PFET436. In the present example, current source440is designed to provide a DC bias voltage of 0.6 V on both the source terminal of NFET434and the gate terminal of PFET436. The 1.3 V present on the gate terminal of NFET434, along with the 0.6 V present on the source terminal of NFET434, turns NFET434on. In turn, PFET436is turned on, passing the 1.3 V on its source terminal to its drain terminal. The DC voltage of 1.3 V is also present at the gate terminals of NFETs402and406, through resistors446and448, respectively.

In a similar manner, the branch of network400operating with FETs404and408and comprising FETs452(M5),454(M9) and456(M10), as well as current sources458and460, capacitor462and resistors464,466and468, picks up the DC voltage of 0.5 V present on output terminal415and provides a DC voltage of 1.1 V on the gate terminals of NFETs404and408, as shown inFIG. 4.

Thus, network400tracks the DC offset component of the DC voltage manifested at the outputs of passive mixer310by LO self-mixing and provides a compensating shift in the DC levels of the LO signal present at the gate terminals of NFETs402and408and the LOC signal present at the gate terminals of NFETs404and406.

Referring now toFIGS. 5A through 5D, the beneficial effect on the linear performance of passive mixer310of the compensating shift in the DC levels of the LO and LOC signals provided by the above-described embodiment of the present invention are illustrated.FIGS. 5A through 5Dshow waveforms present at the terminals of FETs402and404during operation of the passive mixer310.

FIG. 5Arepresents the LO and LOC signals superimposed on one another on a horizontal axis representing time t. During operation of passive mixer310, the LO and LOC signals are input to the gate terminals of FETs402and404, respectively, as shown inFIG. 4. The LO and LOC signals are used to switch their respective FETs on and off. As discussed above, the LO and LOC signals are 180 degrees out of phase and thus when FET402is switched on, FET404is switched off, and vice versa. As can be seen fromFIG. 5A, the embodiment of the present invention shown inFIG. 4has shifted the DC voltage bias level of the LO signal present at the gate terminal of NFET402from 1.2 V to 1.3 V. In addition, the DC voltage bias level of the LOC signal present at the gate terminal of NFET404has been level shifted from 1.2 V to 1.1 V by the embodiment of the present invention shown inFIG. 4.

FIG. 5Brepresents output signals seen at the drain terminals of FETs402and404. The slow-varying solid lines represent the baseband signal waveforms present at the terminals of FETs402and404during operation of the passive mixer310.FIG. 5Bshows that due to the DC offset of 0.2 V introduced by the LO self-mixing, the DC voltages at the drain terminals of FETs402and404deviate from each other by 0.2 V. Thus, the output signals present on the drain terminals of FETs402and404rides on DC levels that are offset by 0.2 V.

FIG. 5Crepresents the signal input seen at the source terminals of FETs402and404. When either FET402or FET404turns on, the DC voltage at its drain terminal will be extended to its source terminal. Thus, as shown inFIG. 5C, when FET402turns on, the RF input signal at its source terminal will ride on a DC level that is shifted up from the original DC level of 0.6 V to 0.7 V. Similarly, when FET404turns on, the RF signal input at its source terminal will ride on a DC level that is shifted down from the original DC level of 0.6 V to 0.5 V.

However, as shown inFIG. 5Dwhich shows the Vgs of FETs402and404, due to the beneficial DC offset tracking and LO DC voltage bias level shifting effect of the embodiment of the present invention shown inFIG. 4, the gate-to-source voltage of FET402(Vgs1) is now symmetrical to the gate-to-source voltage of FET404(Vgs2). This symmetry results from the shift in the DC voltage bias level of the LO and LOC signals provided by network400. When FET402is turned on, 0.7 V is present on its source terminal. The DC voltage from gate terminal to source terminal of FET402is determined by subtracting the DC voltage at its source terminal from the DC voltage at its gate terminal. The DC voltage from gate to source of FET402is 1.3 V−0.7 V=0.6 V. Thus, the DC level of signal Vgs1is 0.6 V. When FET404is turned on, 0.5 V is present on its source terminal. The DC voltage from gate terminal to source terminal of FET404may be determined in the same manner as above to be 1.1 V−0.5 V=0.6 V. Thus, the DC level of signal Vgs2is 0.6 V. As can be seen fromFIG. 5D, the turn on times of FET402and FET404are now substantially equal. This balance between Vgs1and Vgs2of passive mixer310shown inFIG. 5Dadvantageously results in decreased even order distortion, including IM2 distortion. Thus, the linearity performance of passive mixer310is improved by the embodiment of the present invention shown inFIG. 4.

Computer simulations of the conventional passive mixer circuit100shown inFIG. 1and the embodiment of the present invention shown inFIG. 4were performed. The linearity performance of each was determined by plotting the IM2 and IM3 for both circuits. Examples of simulation results are shown inFIGS. 6 and 7.

FIG. 6shows a plot600of a two tone test performed on a computer simulation of passive mixer100. The horizontal axis of plot600represents frequency measured in hertz (Hz) and the vertical axis represents distortion measured in decibels (dB). At a frequency of 20 MHz, the IM2 distortion of the conventional passive mixer100is approximately −65 dB.

FIG. 7shows a plot700of a two tone test performed on a computer simulation of passive mixer310. The horizontal axis of plot700represents frequency measured in Hz and the vertical axis represents distortion measured in dB. At a frequency of 20 MHz, the IM2 distortion of the passive mixer310incorporating the embodiment of the present invention shown inFIG. 4is approximately −87 dB. This represents a reduction in IM2 distortion of approximately 20 dB.

Thus, some embodiments described above employ a CMOS implementation of a passive mixer circuit coupled to a DC offset tracking and LO DC bias level-shifting network for improving linearity performance in wireless communication systems. Preferred embodiments of the present invention relate to a DC offset tracking and LO DC bias level-shifting network including an input coupled to a mixer circuit output for receiving a DC voltage present on the mixer circuit output. The DC voltage includes an offset component. A level shifting circuit is coupled to the input for level shifting the received DC voltage a predetermined amount. An output of the level shifting circuit is coupled to a local oscillator input for outputting the level shifted DC voltage to the local oscillator input. The level shifted DC voltage outputted to the local oscillator input of the mixer circuit reduces or substantially eliminates distortion in the mixer circuit caused by the DC offset component, including IM2 distortion.

It is to be understood that even though numerous characteristics and advantages of various embodiments of the present invention have been set forth in the foregoing description, together with details of the structure and function of various embodiments of the invention, this disclosure is illustrative only. Changes may be made in detail, especially matters of structure and management of parts within the principles of the present invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed. For example, although embodiments of the present invention are described in which a DC offset tracking and LO DC bias level-shifting network comprises PMOS and NMOS FETs to perform the functions of the network, any suitable switching device may be used. For example, where an NMOS FET is used in the network, a PMOS FET could be substituted and the DC biasing of the FET adjusted accordingly. Similarly, where a PMOS FET is used in the network, an NMOS FET could be substituted.

In addition, although the preferred embodiment described herein is directed to a mixer circuit for use in a communication system node in a wireless LAN, it will be appreciated by those skilled in the art that the teaching of the present invention may be applied to other RF wireless communication systems. In fact, any RF communication system is within the teachings of the present invention, without departing from the scope and spirit of the present invention.

Having disclosed exemplary embodiments and the best mode, modifications and variations may be made to the disclosed embodiments while remaining within the scope of the invention as defined by the following claims.