Unified bandgap voltage curvature correction circuit

A unified bandgap voltage waveform compensation amplifier is arranged having shared input transistor pairs, a shared load resistor, and shared current sources. For example, a first amplifier structure is arranged to produce a negative-going bias correction signal when a bandgap voltage reference increases as operating temperatures rise and a second amplifier structure is arranged to produce a positive-going bias correction signal when the bandgap voltage reference increases as operating temperatures rise. The unified amplifier is arranged to combine the positive-and negative-going signals to generate a combined compensation current that is used to compensate for temperature instability of the bandage voltage reference.

BACKGROUND

Electronic circuits are designed using increasingly smaller design features to attain increased integration and reduced power consumption. An example of such increasingly integrated circuits, includes SoC (System on Chip) designs implemented using VLSI (very large scale integration). Power management (including controlling power consumption and heat dissipation) are significant design concerns in such VLSI circuits. For example, the rate and amounts of power consumption affects the operating temperatures, lifetimes, battery longevity for mobile devices, and the like, of the devices incorporating the VLSI circuits. However, as the design features of integrated circuits are increasingly made smaller, variability of the electrical characteristics of the components of the integrated circuits increasingly jeopardizes proper operation of the integrated circuits.

SUMMARY

The problems noted above can be solved in large part by a PWL (piecewise linear) curvature compensation circuit that is arranged to compensate, for example, temperature-dependent deviations of a voltage reference signal produced by a bandgap voltage generator. The PWL curvature compensation circuit includes a unified amplifier that is arranged to provide a negative-going bias correction when the bandgap voltage reference increases over a first range of temperatures and to provide a positive-going bias correction signal when the bandgap voltage reference decreases over a second range of temperatures.

The unified amplifier includes a stacked input transistor pair (for receiving reference signals), a shared load resistor, and common tail and load current sources that are arranged in an area- and power-efficient configuration. When the unified amplifier is arranged in a substrate using a similar layout to a bandgap voltage generator (also arranged in the substrate), temperature compensation is improved because thermal effects on the structures of the bandgap voltage generator are similar to the thermal effects on the structures of the unified amplifier.

The unified amplifier is arranged without having separate input transistor pairs, a separate load resistor, and separate current sources that would otherwise be used by separate amplifiers. For example, a first amplifier structure is arranged to produce a negative-going bias correction signal when the bandgap voltage reference increases as operating temperatures rise and a second amplifier structure is arranged to produce a positive-going bias correction when the bandgap voltage reference increases as operating temperatures rise. Accordingly, the unified amplifier shares input transistor pairs, the load resistor, and current sources used to generate the PWL compensation current.

This Summary is submitted with the understanding that it is not be used to interpret or limit the scope or meaning of the claims. Further, the Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

DETAILED DESCRIPTION

Certain terms are used throughout the following description—and claims—to refer to particular system components. As one skilled in the art will appreciate, various names may be used to refer to a component or system. Accordingly, distinctions are not necessarily made herein between components that differ in name but not function. Further, a system can be a sub-system of yet another system. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus are to be interpreted to mean “including, but not limited to . . . . ” Also, the terms “coupled to” or “couples with” (and the like) are intended to describe either an indirect or direct electrical connection. Thus, if a first device couples to a second device, that connection can be made through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

FIG. 1is a block diagram illustrating a computing device100in accordance with example embodiments of the disclosure. For example, the computing device100is, or is incorporated into, a mobile communication device129, such as a mobile phone, a personal digital assistant, a personal computer, automotive electronics, projection (and/or media-playback) unit, or any other type of electronic system.

In some example embodiments, the computing device100comprises a megacell or a system-on-chip (SOC) which includes control logic such as a CPU112(Central Processing Unit), a storage114(e.g., random access memory (RAM) and/or disk storage) and a tester110. The CPU112can be, for example, a CISC-type (Complex Instruction Set Computer) CPU, RISC-type CPU (Reduced Instruction Set Computer), or a digital signal processor (DSP). As further discussed below, CPU112can be a multicore processor, for example a heterogeneous multicore processor including a combination of one or more cores.

The storage114(which can be memory such as RAM, flash memory, or disk storage) stores one or more software applications130(e.g., embedded applications) that, when executed by the CPU112, perform any suitable function associated with the computing device100. For example, power supply related functions (such as power data logging over temperature) can be implemented using program and/or data information stored in storage114.

The tester110comprises logic that supports testing and debugging of the computing device100executing the software application130. For example, the tester110can be used to emulate a defective or unavailable component(s) of the computing device100to allow verification of how the component(s), were it actually present on the computing device100, would perform in various situations (e.g., how the component(s) would interact with the software application130). In this way, the software application130can be debugged in an environment which resembles post-production operation.

The CPU112comprises memory and logic that processes and/or (at least temporarily) stores information under control of programs accessed from the storage114. The computing device100is often controlled by a user using a UI (user interface)120, which provides output to and receives input from the user during the execution the software application130. The output is provided using the display118, indicator lights, a speaker, vibrations, and the like. The input is received using audio and/or video inputs (using, for example, voice or image recognition), and electro-mechanical devices such as keypads, switches, proximity detectors, and the like. CPU112may execute operating system tasks and/or application specific tasks that manipulate text, numbers, graphics, audio, video or a combination of these elements (e.g., in audio and/or video steaming applications).

The CPU112and tester110are coupled to I/O (Input-Output) port128, which provides an interface that is configured to receive input from (and/or provide output to) peripherals and/or computing devices131, including tangible (e.g., “non-transitory”) media (such as flash memory) and/or cabled or wireless media (such as a Joint Test Action Group (JTAG) interface). These and other input and output devices are selectively coupled to the computing device100by external devices using wireless or cabled connections. The CPU112, storage114, and tester110are also coupled to a programmable power supply (not shown), which is configured to receive power from a power source136(such as a battery, solar cell, “live” power cord, inductive field, fuel cell, and the like).

The CPU112(and/or the substrate upon which the CPU112is formed) includes a PWL bandgap voltage corrector116. The PWL bandgap voltage corrector116is arranged to provide PWL curvature to improve the curvature of the bandgap voltage over a range of operating temperatures. The PWL bandgap voltage corrector116provides an area and power efficient PWL current generation circuit that can be used to reduce temperature fluctuation-caused bandgap voltage curvature. Although the PWL bandgap voltage corrector is illustrated a being a part of (and/or on the same substrate as) CPU112, the PWL bandgap voltage corrector can be implemented in a variety of system components, including analog domains, analog-to-digital converters, microcontrollers, SoCs, and the like.

FIG. 2is a waveform diagram illustrating unified PWL bandgap voltage compensation generation in accordance with example embodiments of the disclosure. Graph200includes signal VBG_HI (voltage bandgap high)210and signal VBG_LO (voltage bandgap low)212that are illustrated as remaining substantially constant.

Signal VPTAT (voltage proportional to absolute temperature)214is illustrated in graph200as increasing as a function of temperature (e.g., where temperature increases from left to right). Signal VPTAT can be supplied by a thermal voltage generator of a bandgap voltage generator and is used to bias transistors of the PWL bandgap voltage corrector116(e.g., as discussed with reference toFIG. 4, below).

The intersection of signal VPTAT214with VBG_HI210represents first point at which temperature compensation is no longer applied to a bandgap voltage generator. For example, as temperature increases, the magnitude of the (e.g., instantaneous) slope of bandgap voltage gradually decreases until the bandgap voltage (e.g., bandgap voltage712ofFIG. 7) reaches a maximum value (at which point the slope is zero). The intersection of signal VPTAT214with VBG_HI210can be a point, for example, where the magnitude of the slope is around unity (e.g., the rise is equal to the run).

The intersection of signal VPTAT214with VBG_LO212represents second point at which temperature compensation is to be reapplied to a bandgap voltage generator. For example, as temperature increases, the magnitude of the (instantaneous) slope of bandgap voltage parabolically increases. The intersection of signal VPTAT214with VBG_LO212can be a point, for example, where the magnitude of the slope is around unity.

Curve220is a PWL correction curve that is used to correct a voltage produced by the bandgap voltage generator while the bandgap voltage increases as a function of temperature. Segment222illustrates a negative-going correction signal that is used to compensate for temperature effects on the voltage generated by the bandgap voltage generator until, for example, the bandgap voltage is substantially stable. The bandgap voltage is substantially stable, for example, when the magnitude of the slope of the bandgap voltage is less than unity. Segment224illustrates a level (e.g., non-correcting) correction signal that maintains a bandgap voltage level that is not (e.g., further) corrected as a function of temperature.

Curve230is a PWL correction curve that is used to correct a voltage produced by the bandgap voltage generator while the bandgap voltage decreases as a function of temperature. Segment232illustrates a level (e.g., non-correcting) correction signal that maintains a bandgap voltage level that is not (e.g., further) corrected as a function of temperature, whereas segment234illustrates a positive-going correction signal that is used to compensate for temperature effects on the voltage generated by the bandgap voltage generator after, for example, the bandgap voltage substantially increases as a function of temperature. The bandgap voltage substantially increases, for example, when the magnitude of the slope of the bandgap voltage is greater than unity.

Curve240is a unified (e.g., formed by combining curves220and230) PWL correction curve that is used to correct a voltage produced by the bandgap voltage generator while the bandgap voltage increases and decreases as a function of temperature. Segment242illustrates a negative-going correction signal that is used to compensate for temperature effects on the voltage generated by the bandgap voltage generator until, for example, the bandgap voltage is substantially stable. Segment244illustrates a level (e.g., non-correcting) correction signal that maintains a bandgap voltage level that is not (e.g., further) corrected as a function of temperature. Segment246illustrates a positive-going correction signal that is used to compensate for temperature effects on the voltage generated by the bandgap voltage generator after, for example, the bandgap voltage substantially increases as a function of temperature.

FIG. 3is a waveform diagram illustrating unified PWL bandgap voltage waveform compensation in accordance with example embodiments of the disclosure. Graph300includes signal bandgap voltage310that is illustrated as having a ΔV (change in voltage) over temperature. For example, the signal bandgap voltage310increases over a ΔT (change in temperature) period312and decreases over a ΔT (change in temperature) period314.

Unified PWL correction voltage320is similar to the (unified) curve240discussed above. The unified PWL correction voltage is arranged, for example, with each segment being approximately one-third of the length of time being defined by periods312and314. For example, period322(which encompasses the negative-going segment of the PWL correction voltage320), period324(which encompasses the substantially flat segment of the PWL correction voltage320), and period326(which encompasses the negative-going segment of the PWL correction voltage320) are substantially the same length.

In various example embodiments, other arrangements of the lengths of periods322,324, and326are possible. For example, the length of period324can be shorter, with the lengths of periods322and326made longer (although the tolerances of VBG_HI and VBG_LO with respect to the maximum value of the bandgap voltage are lessened).

Waveform330illustrates a compensated bandgap voltage that has been compensated using the unified PWL correction voltage230signal. Waveform330includes a segment332that decreases in amplitude in response to (for example) the negative-going PWL correction voltage, a segment344that increases in response to (for example) increasing temperature, a segment346that decreases in response to (for example) increasing temperature, and a segment338that increases in amplitude in response to (for example) the positive-going PWL correction voltage. In various embodiments, complementary signals and circuitry can be used, such that the illustrated signals are inverted.

The example compensated ΔV (change in voltage) over temperature for waveform330(as discussed below with reference toFIG. 7, for example) is around four times less than the uncompensated bandgap voltage ΔV over temperature, thus indicating an improvement in temperature stability over the uncompensated bandgap voltage.

FIG. 4is a schematic diagram illustrating a unified PWL bandgap voltage waveform compensation amplifier in accordance with example embodiments of the disclosure. Unified PWL bandgap voltage waveform compensation amplifier400includes a first and a second amplifier that are electrically coupled together via coupler R1. Coupler R1is, for example, a resistor that is arranged to permit current flow from one amplifier to the other amplifier and to linearize the compensated output of the unified PWL bandgap voltage waveform compensation amplifier400. Further, the sharing of the coupler R1between the amplifiers, for example, eliminates resistive mismatch that would otherwise occur using separate resistors in separate amplifiers (and would also decrease overall bandgap voltage accuracy).

PMOS (positive-type metal oxide semiconductor) input transistors414and416are used by the first amplifier to control a current in response to the signals VPTAT and VBG_LO, respectively. The (“head”) current (which is supplied by current source412having a nominal value of “2I”) is coupled such that half of the supplied current (having a nominal value of “I”) flows through transistors414and416(via current source418) and the other half of the supplied current (also having a nominal value of “I”) flows through the NMOS (negative-type metal oxide semiconductor) load transistor440. Transistor440is biased by the voltage at the input of the current source418, thus providing a feedback loop (discussed below) and causing transistor440to mirror the current of the current source418. (The term current “source” also includes the meaning of current “sink” as, for example, determined by placement within a schematic and the direction of flow of current.)

PMOS (positive-type metal oxide semiconductor) input transistors424and426are used by the first amplifier to control a current in response to the signals VPTAT and VBG_HI, respectively. The (“head”) current (which is supplied by current source422having a nominal value of “2I”) is coupled such that around half of the supplied current (having a nominal value of “I”) flows through transistors424and426(via current source428) and the other half of the supplied current (also having a nominal value of “I”) flows through the NMOS (negative-type metal oxide semiconductor) load transistor442. Transistor442is biased by the voltage at the input of the current source428, thus causing transistor440to mirror the current of the current source428.

Input transistors414and416of the first amplifier are coupled in series (e.g., a transistor “stack”) between current sources412and418, whereas input transistors424and426of the second amplifier are coupled in parallel between current sources412and418. Accordingly, input transistors414and416each have a size ratio of twice the size of each of input transistors424and426.

In operation, the signal VPTAT provides a voltage that varies with temperature. As described above with reference toFIG. 3, the signal bandgap voltage310increases with temperature over period312and then decreases with temperature over period314. Accordingly, the current “ΔI” through load transistor440is a temperature dependent current. For example, ΔI is equal to twice the value of ΔV divided by the value in Ohms of the coupler R1(when the transconductance times the value of the coupler R1is much greater than one). The drain of transistor416is modulated by load transistor440, which provides a feedback mechanism (from the drain of transistor416to the source of transistor414). The feedback mechanism substantially prevents the transconductance of the transistors414and416from changing, which maintains linearity over a larger input range of VPTAT voltages.

Likewise, the current “−ΔI” through load transistor442is a temperature dependent current. The drain of transistor424is modulated by load transistor444, which provides a feedback mechanism (from the drain to the source of transistor424). The feedback mechanism substantially maintains the transconductance of the transistors424and426to help preserve linearity over temperature.

As illustrated, output signal IPWL is generated in response to current mirroring of current “ΔI” through transistor440. For example, NMOS transistor452is biased similarly to transistor440so that current ΔI also flows through transistor452. PMOS transistors450and460have sources tied to the high side power rail and are arranged as a current mirror such that current ΔI (which flows through transistors450and452) also flows through transistor460. However, NMOS transistor462is biased similarly to transistor442so that current −ΔI also flows through transistor462. Signal IPWL is difference of current ΔI and current −ΔI and is carried through self-biased (e.g., where the source is coupled to the gate) NMOS transistor470.

When VPTAT is less than VBG_LO, the ΔI varies in accordance with a positive temperature coefficient, and signal IPWL has a negative-going slope as illustrated by segment242(illustrated inFIG. 2). When VPTAT is greater than VBG_LO and less than VBG_HI, the ΔI varies in accordance with a negative temperature coefficient, and signal IPWL has a horizontal (e.g., zero) slope as illustrated by segment244. When VPTAT is greater than VBG_HI, the ΔI varies in accordance with a positive temperature coefficient, and signal IPWL has a positive-going slope as illustrated by segment246.

FIG. 5is a schematic diagram illustrating a reduced-size unified PWL bandgap voltage waveform compensation amplifier in accordance with example embodiments of the disclosure. The unified PWL bandgap voltage waveform compensation amplifier500does not include a current mirror (e.g., provided by the PMOS mirror transistors450and460), which consumes less power and requires less layout area.

Unified PWL bandgap voltage waveform compensation amplifier500includes a first and a second amplifier that are electrically coupled together via coupler R1. Coupler R1is, for example, a resistor that is arranged to permit current flow from one amplifier to the other amplifier and to linearize the compensated output of the unified PWL bandgap voltage waveform compensation amplifier500.

PMOS (positive-type metal oxide semiconductor) input transistors514and516are used by the first amplifier to control a current in response to the signals VPTAT and VBG_LO, respectively. The (“head”) current (which is supplied by current source512having a nominal value of “2I”) is coupled such that half of the supplied current (having a nominal value of “I”) flows through transistors514and516(as controlled by current source518) and the other half of the supplied current (also having a nominal value of “I”) flows through the NMOS (negative-type metal oxide semiconductor) load transistor540. Transistor540is biased by the voltage at the input of the current source518, thus providing a feedback loop and causing transistor540to mirror the current of the current source518.

PMOS (positive-type metal oxide semiconductor) input transistors524and526are used by the first amplifier to control a current in response to the signals VPTAT and VBG_HI, respectively. The (“head”) current (which is supplied by current source522having a nominal value of “2I”) is coupled such that around half of the supplied current (having a nominal value of “I”) flows through transistors524and526(via current source528) and the other half of the supplied current (also having a nominal value of “I”) flows through the NMOS (negative-type metal oxide semiconductor) load transistor542.

The drain of transistor516is modulated by load transistor540, which provides a feedback mechanism (from the drain of transistor516to the source of transistor514). The feedback mechanism substantially prevents the transconductance of the transistors514and516from changing, which maintains linearity over a larger input range of VPTAT voltages. Likewise, the drains of transistor524and526are modulated by load transistor544, which provides a feedback mechanism (e.g., from the drain to the source of transistor524).

Input transistors514and516of the first amplifier are coupled in series (e.g., a transistor “stack”) between current sources512and518, whereas input transistors524and526of the second amplifier are coupled in parallel between current sources512and518. Accordingly, input transistors514and516each have a size ratio of twice the size of each (e.g., active area) of input transistors524and526.

In operation, the signal VPTAT provides a voltage that varies with temperature. As described above with reference toFIG. 3, the signal bandgap voltage310increases with temperature over period312and then decreases with temperature over period314. Accordingly, the current ΔI through load transistor540is a temperature dependent current. The drain of transistor516is modulated by load transistor540, which provides a feedback mechanism (from the drain of transistor516to the source of transistor514). The feedback mechanism substantially prevents the transconductance of the transistors514and516from changing, which maintains linearity over a larger input range of VPTAT voltages.

Likewise, the current −ΔI through load transistor542is a temperature dependent current. The drain of transistor524is modulated by load transistor544, which provides a feedback mechanism (from the drain to the source of transistor524). The drain of transistor524is further coupled to the source of NMOS transistor552. Transistor552is biased by the voltage at the gate of transistor540, thus causing transistor552to (in proportion to the bias voltage of gate552) subtract current (e.g., supplied from current source522and coupler R1) that would otherwise flow through transistor542. Because the subtraction of currents from the source of transistor542is fed-back to the source of transistor524, the bias voltage applied to the gate of542reflects any ΔI of transistor540. The bias voltage applied to the gate of542is also applied to transistor562, such that transistor562is arranged to sink a current in response to the subtraction of currents.

The output NMOS transistor562is the current signal IPWL. The IPWL is coupled to the bandgap voltage generator580and is arranged to compensate the output voltage or the bandgap voltage generator580to produce the voltage bandgap compensated (VBG_COMP). For example the IPWL can be injected into a bandgap generator output resistive ladder to compensate for temperature-dependent curvature of the output voltage. The curvature of the output voltage can be adjusted (e.g., in a post-fabrication environment) using laser trimming (e.g., at little or no additional cost). The unified PWL bandgap voltage waveform compensation amplifier500can be used as a stable voltage reference as a low-cost on-chip resource for analog-to-digital converters.

FIG. 6is a waveform diagram illustrating unified PWL bandgap voltage compensation control parameters over temperature in accordance with example embodiments of the disclosure. Graph600includes signal VBG_HI (voltage bandgap high)610and signal VBG_LO (voltage bandgap low)212that are illustrated as remaining substantially constant. Signal VPTAT (voltage proportional to absolute temperature)614is illustrated in graph600as increasing as a function of temperature (e.g., where temperature increases from left to right).

Signal616illustrates a current ΔI, such as the current carried through load transistor540. Signal616is quantized in units of nano-Amperes (nA), as graphed using the right-hand vertical scale. Signal616is symmetrical with respect to a middle (e.g., minimum) point that occurs at a temperature of around 25 degrees Celsius. At this point, the current ΔI is zero nA, and the current ΔI increases parabolically with either increasing or decreasing temperature.

The intersection of signal VPTAT614with VBG_HI610represents first point that occurs at a temperature of around 5 degrees Celsius, where the VPTAT signal614has a voltage of around 672.75 mV. The intersection of signal VPTAT614with VBG_HI610can be a second point that occurs at a temperature of around 45 degrees Celsius, where the VPTAT signal614has a voltage of around 756.6 mV. (Actual values can vary in accordance with process parameters and design rules used to implement the unified PWL bandgap voltage waveform compensation amplifier500, for example.) Thus, the first and second points are centered about the middle point of signal616, which represents the inflection point of the bandgap voltage curve712discussed below with respect toFIG. 7.

FIG. 7is a waveform diagram illustrating unified PWL bandgap voltage compensation over temperature in accordance with example embodiments of the disclosure. Graph700includes a compensated bandgap voltage signal710and that is illustrated in graph700as increasing as a function of temperature (e.g., where temperature increases from left to right) over a horizontal axis that represents increasing temperatures and a vertical axis that represents a value measured in Volts.

Graph700also includes an uncompensated bandgap voltage signal720and that is illustrated in graph700as having a point of inflection (e.g., maximum voltage) at a point that occurs at a temperature of around 25 degrees Celsius and a voltage around 1.23457 Volts. The uncompensated bandgap voltage signal720parabolically increases as temperature increases or decreases. The compensated bandgap voltage signal710curve and the uncompensated bandgap voltage signal720curve intersect at the point of inflection (e.g., where the current ΔI has a value of zero nA).

The compensated bandgap voltage signal710has a curvature of around 0.58 parts-per-million (PPM) per degree Celsius and a non-linear error of 1.3 ppm/C that is introduced by the curvature compensation. In contrast, the uncompensated bandgap voltage signal720has a raw (e.g., uncompensated) bandgap curvature of 6 ppm/C.