Trenched and implanted bipolar junction transistor

The present invention concerns a monolithically merged trenched-and-implanted Bipolar Junction Transistor (TI-BJT) with antiparallel diode and a method of manufacturing the same. Trenches are made in a collector, base, emitter stack downto the collector. The base electrode is formed on an implanted base contact region at the bottom surface of the trench. The present invention also provides for products produced by the methods of the present invention and for apparatuses used to perform the methods of the present invention.

FIELD OF THE INVENTION

The disclosed invention is in the field of high-current and high-voltage semiconductor devices, such as, for example, a trenched and implanted bipolar junction transistor (TI-BJT) and methods of making the same.

BACKGROUND OF THE INVENTION

The high voltage BJT is of great interest for power conversion applications, as it is a normally-off device with very low conduction losses. One disadvantage of high voltage BJTs is a low common emitter current gain, which may include complications in building necessary gate drivers to supply the high continuous base current needed to support the BJT in its on-state. Additionally, the base layer of a BJT may have to be thicker than the maximum depletion region extension into the base in the blocking mode, to avoid a “punch-through” breakdown. This may impose limitations in the minimum thickness of the base layer and doping, and may limit the common emitter current gain.

Thus, there is a need for a BJT with improved performance characteristics, where a high common emitter current gain may be achieved without compromising blocking capability. The invention is directed to these and other important needs.

SUMMARY OF THE INVENTION

In accordance with the various embodiments disclosed herein, a trenched-and-implanted bipolar junction transistor (TI-BJT) is disclosed. The TI-BJT may include a drift layer of a second conductivity type; a channel layer of the second conductivity type formed on top of the drift layer; a base layer of a first conductivity type formed on top of the channel layer, wherein the base layer has a thickness which extends along a first direction, wherein the thickness is in the range of 0.02 to 2 microns; and an emitter layer of the second conductivity type formed on top of the base layer, the emitter layer having a bottom surface located adjacent to the base layer and a top surface opposite the first bottom surface along the first direction. The TI-BJT may also include at least one U-shaped trench formed in at least the emitter layer, base layer, and channel layer. The at least one U-shaped trench may include: a first side surface, a second side surface, and a bottom surface, the first side surface, second side surface, and the bottom surface being substantially planar; the first and the second side surfaces spaced apart along a second direction, the second direction being perpendicular to the first direction, the first and second side surfaces extending (1) along the first direction, (2) from the top surface of the emitter layer to the bottom surface of the at least one U-shaped trench, and (3) through the emitter layer, through the base layer, and at least partially into the channel layer; and the bottom surface of the at least one U-shaped trench extending (1) along the second direction and (2) between the first and the second wall of the at least one U-shaped trench. The TI-BJT may further include at least one implanted U-shaped conductivity region of the first conductivity type, the U-shaped region of the first conductivity type comprising: a first portion extending along the bottom surface of the at least one U-shaped trench; a second portion and a third portion extending (1) along the first and the second side surfaces of the at least one U-shaped trench, respectively, and (2) between the bottom surface of the emitter layer and the bottom surface of the at least one U-shaped trench; and a base electrode disposed between the first and the second side surfaces of the at least one U-shaped trench.

In another embodiment, the TI-BJT may also include a second U-shaped trench formed in the emitter layer, base layer, and channel layer, the second U-shaped trench including: a first side surface, a second side surface, and a bottom surface, the first side surface, second side surface, and the bottom surface being substantially planar; the first and the second side surfaces of the second U-shaped trench spaced apart along a second direction, the second direction being perpendicular to the first direction, the first and second side surfaces extending (1) along the first direction, (2) from the top surface of the emitter layer to the bottom surface of the second U-shaped trench, and (3) through the emitter layer, through the base layer, and at least partially into the channel layer; and the bottom surface of the second U-shaped trench extending (1) along the second direction and (2) between the first and the second wall of the second U-shaped trench; a second implanted U-shaped conductivity region of the first conductivity type, the U-shaped region of the first conductivity type comprising: a first portion extending along the bottom surface of the second U-shaped trench; a second portion and a third portion extending (1) along the first and the second side surfaces of the second U-shaped trench, respectively, and (2) between the bottom surface of the emitter layer and the bottom surface of the second U-shaped trench; and a base electrode disposed between the first and the second side surfaces of the second U-shaped trench. The TI-BJT may also include at least one mesa, the at least one mesa comprising: a first side wall defined by the first side wall of the at least one U-shaped trench and a second side wall defined by the second side wall of the second U-shaped trench; and an unetched region of the emitter layer, base layer, and channel layer extending between the first and the second side walls of the at least one mesa.

In yet another embodiment, the TI-BJT may include an antiparallel diode, monolithically integrated with the TI-BJT, the antiparallel diode comprising an anode electrode and a cathode electrode; a first electric connection between the emitter electrode of the TI-BJT and the anode electrode of the antiparallel diode; wherein the collector electrode of the TI-BJT is the cathode electrode of the antiparallel diode; an electrically inactive isolation region, the electrically inactive isolation region providing an electric isolation between the anode electrode of the antiparallel diode and the base electrode of the BJT, wherein the electrically inactive isolation region increases voltage blocking capability between the BJT base and JBS anode; and a shared edge termination region for the TI-BJT and the antiparallel diode.

In another further embodiment of an integrated TI-BJT and antiparallel diode, the TI-BJT may include at least one of the first side and the second side of the at least one U-shaped trench of the TI-BJT extend a first distance along the first direction, and the emitter layer and the base layer of the TI-BJT formed by ion implantation of the channel layer. The antiparallel diode may include a trenched-and-implanted Junction Barrier Schottky diode (TI-JBS diode), the TI-JBS diode comprising: the drift layer; the channel layer; two adjacent trenches, the two adjacent trenches spaced a second distance from one another along the second direction; and at least one of the two adjacent trenches having a depth that extends the first distance along the first direction; and a mesa, the mesa comprising: a first side wall and a second side wall of the mesa defined by the depth of the at least two adjacent trenches; an unetched and implanted region of the channel layer extending between the first and the second side walls of the mesa, the unetched and implanted region of the mesas including a top surface of the channel layer that is coplanar with the top surface of the emitter layer of the TI-BJT along the second direction; and a second and a third implanted conductivity region of the first conductivity type extending along the first and second side walls of the mesa, respectively; and an electrical contact formed on the top surface of the mesa.

In another embodiment of an integrated TI-BJT and antiparallel diode, the TI-BJT may include the emitter, base, and channel layers of the TI-BJT formed by ion implantation of the drift layer. The antiparallel diode may include an unetched Junction Barrier Schottky diode (JBS diode) comprising: the drift layer, the drift layer including a top surface that is coplanar with the top surface of the emitter layer of the TI-BJT along the second direction; a second and a third implanted conductivity region of the first conductivity type extending from the top surface of the drift layer into the drift layer, the second and third implanted conductivity regions being separated by an implanted region of the second conductivity type along the second direction; and a vertical etched step extending along the first direction, the vertical etched step disposed between the isolation region and the second and third implanted regions along the second direction.

In yet another embodiment of an integrated TI-BJT and antiparallel diode, the TI-BJT may include the emitter, base, and channel layers of the TI-BJT formed by ion implantation of the drift layer. The antiparallel diode may include a planar, unetched Junction Barrier Schottky diode (JBS diode) comprising: the drift layer, the drift layer including a top surface that is coplanar with the top surface of the emitter layer of the TI-BJT along the second direction; a second and a third implanted conductivity region of the first conductivity type extending from the top surface of the drift layer into the drift layer, the second and third implanted conductivity regions being separated by an implanted region of the second conductivity type along the second direction; and a sloped side wall extending along the first and the second directions, the sloped side wall disposed between the isolation region and the second and third implanted regions along the second direction.

In yet another embodiment of an integrated TI-BJT and antiparallel diode, the TI-BJT may include at least one of the first side and the second side of the at least one U-shaped trench of the TI-BJT extend a first distance along the first direction, and the emitter, base, and channel layers of the TI-BJT are formed epitaxially. The antiparallel diode may include a trenched-and-implanted Junction Barrier Schottky diode (TI-JBS diode), the TI-JBS diode comprising: the drift layer; the channel layer; two adjacent trenches, the two adjacent trenches spaced a second distance from one another along the second direction; and at least one of the two adjacent trenches having a depth that extends a third distance along the first direction, the third distance being less than the first distance; and a mesa, the mesa comprising: a first side wall and a second side wall of the mesa defined by the depth of the at least two adjacent trenches; an etched and implanted region of the channel layer extending between the first and the second side walls of the mesa, the etched and implanted region of the mesa including a top surface of the channel layer that is below with the top surface of the emitter layer of the TI-BJT along the first direction extending from the emitter layer towards the base layer; and a second and a third implanted conductivity region of the first conductivity type extending along the first and second side walls of the mesa, respectively; and an electrical contact formed on the top surface of the mesa.

In an embodiment of an integrated TI-BJT and antiparallel diode, the TI-BJT may include the emitter, base, and channel layers of the TI-BJT are formed epitaxially or by ion implantation. The antiparallel diode may include a planar, etched Junction Barrier Schottky diode (JBS diode) comprising: the drift layer, the drift layer being implanted and including an etched top surface that is disposed below the channel layer of the TI-BJT along the first direction extending from the emitter layer towards the channel layer; a second and a third implanted conductivity region of the first conductivity type extending from the top surface of the drift layer into the drift layer, the second and third implanted conductivity regions being separated by an implanted region of the second conductivity type along the second direction.

Methods of forming the above embodiments are also disclosed herein.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

It is to be appreciated that certain features of the invention which are, for clarity, described herein in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of the invention that are, for brevity, described in the context of a single embodiment, may also be provided separately or in any sub combination. Further, reference to values stated in ranges include each and every value within that range.

In an exemplary embodiment of the invention, the first conductivity type and the second conductivity type may refer to p-type and n-type, respectively, or n-type and p-type respectively. It should be understood that the exemplary systems described herein may contain layers and regions of a first conductivity type and a second conductivity type. Layer may also be understood to be region. It should be understood that a BJT may also be referred to as a high-voltage switch, a switch or a transistor.

FIG. 1Aillustrates an exemplary view of a schematic cross-sectional view of a high-voltage BJT transistor.FIG. 1Aillustrates a power unit cell of the BJT. As illustrated inFIG. 1A, the BJT may be comprised of one or more layers of substrate109of second conductivity type, collector ohmic contact112, drift layer103of second conductivity type, base layer100of first conductivity type, base layer100of thickness106, base ohmic contacts118, emitter layer121of second conductivity type, and emitter ohmic contacts115. It should be understood that the base layer100may also be referred to as an intrinsic base region or an intrinsic base. As further depicted inFIG. 1A, when a BJT supports high voltage, for example, its drift layer103may fully or partially be depleted, and depletion region124may be formed. For example, if the thickness of the depletion region124reaches through the thickness106of the base layer100, for example, a “punch-through” breakdown may occur. It should be understood that the emitter layer121may, as a result, become effectively shorted with the collector layer109and result in potentially catastrophic consequences. As further depicted inFIG. 1A, the thickness106of the base layer100may, for example, need to support the maximum depletion124width in the blocking mode. The base layer100may need to be thick enough and its doping may need to be high enough to support the maximum depletion124width into the base layer100in the blocking mode. In one example, increasing the thickness106of the base layer100and the doping level may lead to reduction in the BJT's common emitter current gain. To achieve the same level of collector forward current, for example, may require a higher base current drive capability.

In one example, high voltage BJTs, a normally-off device, may have a low common emitter current gain and complications may arise in building necessary gate drivers to supply a high continuous base current to support the BJT in its on-state or turn-off the BJT rapidly. For example, the base layer100of a BJT may have to be thicker than the maximum depletion region124in a blocking mode to avoid a “punch-through” breakdown. This may impose limitations on the minimum thickness106of the base layer100and doping, and hence limit the common emitter current gain.

In accordance with the exemplary embodiments described herein, various trenched and implanted BJTs (TI-BJTs) are been described which possess an epitaxial structure with only n-type layers that requires no epitaxial regrowth or deep ion implantations. Exemplary embodiments of the invention may also include monolithic integration of, for example, a BJT device with various antiparallel diode structures (such as JBS diodes), and various layouts in a device cell and its integration with the edge termination region at the device periphery. JBS diodes may be replaced with PiN diodes or pure SBD (Schottky Barrier Diodes). A JBS diode may also be understood to be a Schottky or a Schottky diode. An anti-parallel diode may also be understood to be a diode. It should be understood that an anti-parallel diode may also be referred to as a diode, a JBS diode or a Schottky or a Schottky diode. It should also be understood that a JBS diode may also be referred to as a diode.

FIG. 1Billustrates a full bridge circuit application of the TI-BJT. As shown inFIG. 1B, an exemplary circuit application of the TI-BJT may comprise a diode32and a TI-BJT33in each of the four switch locations, where31refers to power output of the circuit. It should be understood that the integrated TI-BJT33and diode32circuit may be also be configured in half-bridge circuits, three phase bridge circuits and multi-level converter circuits, or the like, or any appropriate combination thereof. In hard switched applications, for example, using a JBS diode may eliminate diode recovery related switching losses, which may allow for higher frequency operation, smaller passives and lower cooling requirements.

FIG. 1Cillustrates an exemplary comparison of hybrid and monolithic device integration.FIG. 1Cillustrates the difference between using two separate chips for a high-voltage switch such as a, TI-BJT1, and diode2with individual edge termination regions10and using a single chip with a combined termination9around the TI-BJT1region and monolithically integrated diode2. As further illustrated,FIG. 1Ccomprises base layer5, emitter layer6and anode contact7. Anode contacts7may also be understood to comprise anode bonding pads or the like. The emitter layer6may be shared with the anode bonding pads7. For example, the periphery of a discrete high voltage device, for example, may include a wide edge termination9,10region to improve device blocking voltage. In an example embodiment, the width of the edge termination9,10, for example, may be 3 to 5 times the thickness of the drift layer, and may constitute a large portion of the overall device die area. For example, in a hybrid integration that uses separate chips for the TI-BJT245and diode248, the TI-BJT245and diode248may have to include a large edge termination9area to support high voltage in the blocking mode. The TI-BJT245and diode248may have similar requirements for the drift layer thickness and doping. In an example embodiment, monolithic integration of a TI-BJT245with diode248, for example, may enable the sharing of the common edge termination9. In an example embodiment, this may save the overall chip area and may be useful for devices with higher voltage rating. In an exemplary embodiment of the hybrid integration, for example, additional wire-bonding interconnects may be needed between the TI-BJT245and diode248, which may introduce parasitic inductance. This may further limit the operating frequency of a power module and may cause excessive voltage spiking during device switching.FIG. 1Cfurther illustrates that a TI-BJT245region and diode248region arrangement within a monolithically integrated die may vary. In an example embodiment, two separate regions may be formed, one for TI-BJT245and one for the diode248. In another example embodiment, interdigitated TI-BJT245regions and diode248regions may be formed throughout the entire die active area. In an example embodiment, such an arrangement may help to reduce the impact of the substrate layer and drift layer resistance.

FIGS. 2A-2Jillustrate an exemplary method of manufacturing a discrete TI-BJT245.

FIG. 2Aillustrates a cross sectional side view an exemplary embodiment of the initial wafer structure for the TI-BJT245with an implanted emitter layer218and base layer215. In an example embodiment, the emitter layer218and base layer215may be also be formed by ion co-implantation over the entire surface using dopants of the first conductivity type for the base layer215, and second conductivity type for the emitter layer218.FIG. 2Aillustrates a typical original wafer structure, which may comprise substrate236of second conductivity type, drift layer233of second conductivity type, an epitaxially grown channel layer227of second conductivity type, a base layer215of first conductivity type and an emitter layer218of second conductivity type.

FIG. 2Billustrates an exemplary trench270and mesa278formation with plasma etching205for the TI-BJT245. In an example embodiment, the plasma etching205may penetrate through the emitter layer218, base layer215, and most or all of the channel layer227, and stop within or just short of the drift layer233. For example, the etching mask204may be of a thickness to withstand plasma etching205, block the subsequent ion implantations and prevent dopant compensation in emitter layer218. It should be understood that the etching mask204may also be referred to as hardmask material or an implantation mask. A mesa278may be defined by and disposed between two adjacent trenches and include a portion of one or more of the emitter layer218, base layer215, channel layer227, and drift layer233. It should be understood that a mesa278may also be referred to as an emitter mesa.

FIG. 2Cillustrates an exemplary embodiment of tilted ion implantation200into the first side-wall of the TI-BJT. It should be understood that a tilted ion implantation may also be referred to as a side-wall ion implantation or a tilted ion implantations. As illustrated inFIG. 2C, the tilted ion implantation200of the first conductivity type may be performed under non-vertical conditions into one trench270, in the side-wall251A for the TI-BJT245region, forming a region of the first conductivity type251B in the side-wall251A of each trench270. It should be understood that a region of the first conductivity type251B may also be referred to as side-wall251A implanted regions. In an example embodiment, the doping of the emitter layer218may, for example, be high enough to prevent the thick, heavily doped emitter layer218of second conductivity type from being converted to a region of first conductivity type251B by the tilted ion implantation.

FIG. 2Dillustrates an exemplary embodiment of tilted ion implants201into second side-wall of the TI-BJT245with implanted emitter layer218and base layer215.FIG. 2Dillustrates an exemplary ion implantation201of the first conductivity type, performed under non-vertical conditions into another sidewall251A of the trench270for the TI-BJT245. In an example embodiment, tilted ion implantation may form a region of first conductivity type251B in each side-wall251A. In another example embodiment, depending upon the implant angles used, tilted ion implantation may also create a region224B of the first conductivity type at the bottom surface224A of the trench270which may or may not fully cover the bottom surface224A of the trench270at this stage.

FIG. 2Eillustrates an exemplary embodiment of the vertical ion implantation of first conductivity type211, performed under a vertical angle, to form the region of first conductivity type224B at the bottom surface224A of the trench270for the TI-BJT245. The region of the first conductivity type224B may be formed in layer(s) adjacent to the bottom surface224A of the trench270. In an example embodiment, the depth of the region of first conductivity type224B at the bottom surface224A of the trench270may be in the range of 20-1000 nm. As illustrated inFIG. 2E, the layer adjacent to the bottom surface224A of the trench270, is the channel layer227. The bottom surface224A of the trench270may be located adjacent to the drift layer233. In an exemplary embodiment, region224B may extend into a second layer, such as the drift layer233. In an example embodiment, region224B may also define the blocking junction underneath.

Vertical ion implantation may be used in addition to tilted ion implantation to form a region224B of the second conductivity type which fully covers the bottom surface224A of the trench270. Vertical ion implantation may also be used to in addition to tilted ion implantation to increase the depth of the region251B of the first conductivity type in the layer(s) adjacent to the bottom surface224A of the trench270. It may be understood that region224B may be the result of at least one of tilted ion implantation and vertical ion implantation. In an example embodiment, this vertical ion implantation211may cover the bottom surface224A of the trench270. For example, the vertical ion implantation211may also penetrate, for example, a certain depth into the layers of second conductivity type underneath bottom surface224A of the trench270, where it converts the original conductivity of the second type into the first type. The implant may also have a high surface concentration for basic ohmic contact formation. In an example embodiment, the implant may also be deep enough to form a blocking junction that does not deplete completely when the device is in its blocking mode. The blocking p-n junction may be formed, for example, at the interface between (1) bottom surface224A of the trench270, which is converted into first conductivity type and (2) the original layer of second conductivity type below, which may be either the channel layer227or drift layer233. Additionally, the ion implants may be further activated, for example, through a high-temperature annealing process. This may consist of a thermal anneal process in a furnace, or a laser-annealing process, or the like, or an appropriate combination thereof. In an example embodiment, the etching mask204may then be removed. It should be understood that ion implantation may result in implanted ions, which may be referred to as implants.

FIG. 2Fillustrates an exemplary embodiment of surface passivation for the TI-BJT245with implanted emitter layer218and base layer215. In an exemplary embodiment, surface passivation layer212may be a dielectric. Formation of surface passivation layer212may employ techniques such as, for example, stacks of thermally grown oxides, deposited plasma enhanced, low pressure chemical vapor deposition (CVD) oxides and nitrides, high density plasma oxides, atomic layer deposited dielectrics, high temperature doped, undoped CVD oxides, or the like, or an appropriate combination thereof. In an example embodiment, surface passivation may reduce surface leakage and improve blocking and bipolar injection capabilities of the base-emitter pn-junction, as well as eliminate surface breakdown paths at the device edge termination region.

FIG. 2Gillustrates the spacer formation on the side-walls by reactive ion etching to expose the regions for subsequent emitter contact and base contact formation. It should be understood that emitter contact may also be referred to as an emitter ohmic contact. It should also be understood that base contact may also be referred to as a base ohmic contact.

FIG. 2Hillustrates an exemplary embodiment of the formation of the emitter ohmic contacts203, base ohmic contacts221and collector ohmic contact239. In an example embodiment, a high temperature annealing step may be performed separately for each contact (i.e. emitter ohmic contact203, base ohmic contact221, collector ohmic contact239), or simultaneously for all three.

FIG. 2Iillustrates the formation of the base contact overlay metal285and the interlayer dielectric206.

FIG. 2Jillustrates an embodiment of the present invention directed to a fabricated TI-BJT245.FIG. 2Jillustrates an exemplary schematic cross-sectional view of a completed device after base contact overlay285, interlayer dielectric206and collector overlay242are formed. The TI-BJT245may comprise, for example, a base layer215of a first conductivity type in direct interface with emitter layer218, where electrostatic shielding may be provided for the thin base layer215by implanted regions of first conductivity type251along the side-walls251A of the trench270. In an example embodiment, a thinner base layer215with a higher value of common emitter current gain may be implemented without compromising device blocking capability. In an example embodiment, there may be no MOS interface incorporated into any active device structure, which may eliminate operational reliability as evidenced in structures such as SiC MOSFETs. In an example embodiment, a benefit of the TI-BJT245structure illustrated inFIG. 2Jmay be high value of base-emitter breakdown voltage, which may be utilized to increase the speed of device turn-off. The higher breakdown may result from the fact that the thin base layer215and sidewall regions are lightly doped, separating the heavily doped emitter layer218region from the heavily doped base layer215at the bottom surface224A of the trench270. It should be understood that emitter layer218may also be referred to as an emitter surface.

In an example embodiment, the trench geometry may provide versatility in the device design. A thin implanted layer of first conductivity type may be formed on the side-walls251A of the mesa278with low-energy ion implanters. For example, this may result in a low-cost manufacturing process. In an example embodiment, region224B in bottom surface224A of the trench270region may provide a blocking junction and high-voltage capability. The side-wall251A implanted regions251B, such as the implanted regions of first conductivity type251B may provide electrical connection to the base layer215and an electrostatic shielding effect of the base layer215in a blocking mode. In an example embodiment, the thickness of the base layer215and emitter layer218, for example, may be 0.2 um and 0.25 um respectively. In another example embodiment, the base layer215and the emitter layer218may also be implanted with ion implanters with required energies, such as, for example under 360 keV for the base layer215and 60 KeV for the emitter layer218. This may provide a method of uniform doping control of the base layer215through ion implantation instead of epitaxial growth, which may result in a uniform and reproducible common emitter current gain of the TI-BJT245.

FIG. 2Jillustrates an example embodiment that comprises a base layer215of a TI-BJT245region, which is confined between two side-walls251A of the etched emitter mesa278. In an example embodiment, the side-walls251A may be subsequently implanted with the dopant of the same conductivity type as the base layer215(e.g., regions251B). In an example embodiment, this may form an electrical connection to the base ohmic contact221. In an example embodiment, the trench geometry may provide great versatility for optimizing the common emitter current gain, forward current, and device blocking voltage. In an example embodiment, the width of the base layer215may be made thin enough to provide a higher value of common emitter current gain because it may not need to support high voltage in a blocking mode. The base layer215, for example, may be electrostatically shielded through depletion of the channel layer227when a reverse bias is applied between the collector ohmic contact239and the base layer215.

For example, the blocking pn-junction in the BJT seen inFIG. 1Amay have to support high voltage and may be formed of the base layer100and underlying drift layer103. In an example embodiment, a thicker depletion region may be formed within a base layer100in blocking mode, as the depletion charge in the base layer100may be equal to the total charge in depleted drift layer103, buffer layer and/or substrate layer109.

The minimum required charge per unit area in the base layer100of the BJT, as depicted inFIG. 1A, may be calculated by the following formula:
QB=∈SEC,  (1)

where ∈Sis semiconductor permittivity and ECis the critical electric field.

ECmay depend upon semiconductor material and breakdown voltage. In an example embodiment, if the base charge is smaller than this value, it may result in the total depletion of base layer100, and a premature “punch-through” breakdown may occur.

The base charge may be calculated by the following formula:
QB=qNBWB,  (2)

where NBis the doping in the base layer100, and WBis the thickness of the base layer100. In an example embodiment, the amount of base current needed to drive the BJT in forward mode may be proportional to β−1, where β is the common emitter current gain of a BJT. A smaller base current may be useful in power conversion applications.

The common emitter current gain may have the following dependency upon the doping in the base layer100and the thickness of the base layer100:

It should be understood that there may be a clear trade-off between the minimum required charge per unit area in the base layer100to block high voltage, and the common emitter current gain in a power BJT. In an example embodiment, the concept of electrostatic shielding of the base layer215, such as for a structure shown inFIG. 2J, may imply that the minimum charge in the base layer215, qNBWB, may not have to be determined by equation (1). In an example embodiment, this may be accomplished by forming blocking junction not with the base layer215, but with the implanted regions in the bottom surface224A of the trench270(i.e. region224B) and on the side-walls251A of the trench270(i.e. region251B). The base layer215may be electrostatically shielded from high-field region by a pinched-off JFET like structure, formed by adjacent side-wall implants, such as, a region of the first conductivity type251B and the channel layer227. In an example embodiment, the total charge in the base layer215may be substantially reduced, providing a much higher value of common emitter current gain according to equation (3) without compromising on device blocking capability.

In an example embodiment, epitaxial re-growth may not be required to fabricate such a device, because electrostatic shielding of the base layer215, without a “punch-through” breakdown, may be achieved by utilizing ion implanters with energies, for example, below 360 keV and without using, for example, deep MeV ion implantations. In an example embodiment, there may be no MOS interface incorporated into any active device structure, which may eliminate operational reliability in structures such as SiC MOSFET structures. In an example embodiment, a plurality of stacked layers of conductivity of second type may be formed to optimize the emitter-base capacitance instead of a single emitter layer218. In an example embodiment, the edge termination may be a single or multi-zone junction termination extension (JTE or MJTE), multiple floating guard-rings (MFGR), a bevel, field-plate or deep mesa278isolation formed with an additional manufacturing step, or the like, or an appropriate combination thereof.

In an example embodiment, the structure of a TI-BJT245may be applied to a thyristor, where the emitter layer218becomes the cathode layer, the base layer215becomes the gate, and the substrate layer236has the conductivity type opposite of the cathode layer and the drift layer233. The collector layer becomes the anode282layer. The opposite polarity device may be implemented by reversing all the layer doping polarities. It should be understood that a collector layer may also be referred to as a collector electrode.

FIGS. 2K-2Tillustrate an exemplary method of manufacturing the TI-BJT245which is monolithically integrated with a Junction Barrier Schottky (JBS)248diode structure.

FIG. 2Killustrates an exemplary embodiment of the initial wafer structure for the TI-BJT245with an implanted emitter and base, monolithically integrated with TI-JBS diode248.FIG. 2Kfurther illustrates a typical original wafer structure, which may comprise the substrate236of second conductivity type, drift layer233of second conductivity type, and an epitaxially grown channel layer227of the second conductivity type. Channel layer227may also, for example, serve to form a Schottky contact within a JBS diode248region.

FIG. 2Lillustrates an exemplary embodiment of an ion implantation of an emitter layer218and a base layer215for the TI-BJT245with implanted emitter and base, monolithically integrated with JBS diode248.FIG. 2Lillustrates an exemplary ion implantation201of first conductivity type for the base layer215and second conductivity type for emitter layer218into channel layer227. In an example embodiment, this implantation may be masked using a masking material202over the JBS diode248region. It should be understood that the masking material202may also be referred to as an implantation mask. The masking material202may consist of, but is not limited to, photoresist, metal or CVD dielectric materials, and may be thick enough to block the implantation tail from penetrating into semiconductor surface. In an example embodiment, the ion implantation201may be performed at a temperature compatible with masking material202, such as, for example, from room temperature to 1100 degrees Celsius.

FIG. 2Millustrates an exemplary trench270formation with plasma etching205for the TI-BJT245and JBS diode248regions. The plasma etching205may penetrate through the emitter layer218, the base layer215, and the channel layer227, and stop within the drift layer233. Alternatively, the trench270may stop within the channel layer227in some embodiments. The etching mask204may be of a thickness, for example, to withstand plasma etching205, to block the subsequent ion implantations and to prevent dopant compensation in emitter layer218.

FIG. 2Nillustrates an exemplary embodiment of a tilted ion implantation200into a side-wall251A of a trench270of the TI-BJT245with implanted emitter layer218and base layer215, monolithically integrated with the JBS diode248. It should be understood that side-walls251A may refer to side-walls of the mesa278as well as side walls of the trench270. As illustrated inFIG. 2N, the tilted ion implantation200of first conductivity type may be performed under non-vertical conditions into one side-wall251A of a trench270and mesa278side-wall for both the TI-BJT245and JBS diode248regions, forming a region of first conductivity type251B. In an example embodiment, the doping of emitter layer218may, for example, be high enough to prevent the thick, heavily doped emitter layer218of second conductivity type from being converted to a region of first conductivity type251B by tilted ion implantation200.

FIG. 2Oillustrates an exemplary embodiment of tilted ion implantation201into second side-wall of the TI-BJT245with implanted emitter layer218and base layer215, monolithically integrated with the JBS diode248.FIG. 2Ofurther illustrates an exemplary ion implantation201of first conductivity type, performed under non-vertical condition into another trench side-wall251A for TI-BJT245and JBS diode248regions. In an example embodiment, this may form a region of first conductivity type251B. These implants may not necessarily cover the bottom surface224A of the trench270.

FIG. 2Pillustrates an exemplary embodiment of the vertical ion implantation211of first conductivity type, performed under vertical angle, to form the region of first conductivity type224B at the bottom surface224A of the trench270for the TI-BJT245and JBS diode248regions. In an example embodiment, the vertical ion implantation211may have a high surface concentration for basic ohmic contact formation, and may be deep enough to form a blocking junction that does not deplete completely when the device is in its blocking mode. Additionally, the vertical ion implantation211may be further activated, for example, through a high-temperature annealing process. In an example embodiment, this may consist of a thermal anneal process in a furnace, or a laser-annealing process, or the like, or an appropriate combination thereof.

FIG. 2Qillustrates an exemplary embodiment of surface passivation for the TI-BJT245with implanted emitter layer218and base layer215, monolithically integrated with a JBS diode248. As illustrated inFIG. 2Q, a surface passivation layer212may be formed. In an example embodiment, surface passivation may eliminate surface leakage paths between the base layer215and emitter layer218, as well as between base layer215and anode282of the diode, and may also protect device edge termination.

FIG. 2Rillustrates an exemplary embodiment of the formation of the emitter ohmic contacts203, base ohmic contacts221and collector ohmic contacts242in the TI-BJT245region. A masked etch of the surface passivation layer212, for example, may form gaps in the TI-BJT245region, while protecting the top surface of the JBS diode248region. In an example embodiment, a metal, for example, Nickel, may then be deposited in these gaps and annealed to form the contact regions such as emitter ohmic contacts203and base ohmic contacts221. The excess metal may then be chemically removed. In this manner, self-aligned contact regions, such as, for example, the emitter ohmic contacts203and base ohmic contacts221may be formed, with no metal remaining in the JBS diode248region.

FIG. 2Sillustrates the formation of the anode contact282of the JBS diode248. A mask may be used to protect the TI-BJT245region, allowing removal of the surface passivation212selectively from the JBS diode248. This removed portions may then be contacted by the Schottky metal282using processes, such as, for example, lift-off. It should be understood that Schottky metal may also be referred to as a Schottky contact or an anode contact.

FIG. 2Tillustrates a unit cell of the TI-BJT245. TI-BJT245, as well as other embodiments of the present invention, may contain layers and regions of a first conductivity type and a second conductivity type.FIG. 2Tillustrates an exemplary schematic cross-sectional view of a device after the base contact overlay285, interlayer dielectric206and collector overlay242are formed. In an embodiment illustrated inFIG. 2T, JBS diode248may be understood to be a trenched and implanted diode. The device structure may comprise TI-BJT245and a JBS diode248. As illustrated inFIG. 2T, the top overlay209may connect emitter ohmic contacts203of a TI-BJT with anode contact282of JBS diode248. In an example embodiment, emitter metallization may also connect the collector and cathode on the wafer backside242. As further illustrated inFIG. 2T, the electrically inactive region254may provide electrical isolation between the base ohmic contacts221of TI-BJT245and the emitter ohmic contacts203or between the base ohmic contacts221of TI-BJT245and the anode contact282of JBS diode248. The isolation region254may, for example, consist of multiple trenches and unimplanted regions to increase voltage blocking capability between the base layer215of the TI-BJT245and anode contact282of JBS diode248. In an example embodiment, the electrically inactive region254may comprise two back-to-back pn junctions. The width of the region may be of a narrow thickness to prevent field crowding in blocking mode and to support potential differences between the base ohmic contact221of the TI-BJT245and the emitter layer218. The trench270of the TI-BJT245may comprise, for example, an base layer215of first conductivity type in direct interface with emitter layer218, where electrostatic shielding provided by implanted regions251of second conductivity type.

In an example embodiment, the trench geometry may provide versatility in the device design. A thin implanted layer of first conductivity type251B may be formed on the side-walls251A of mesa278with low-energy ion implanters. For example, this may result in a low-cost manufacturing process. In an example embodiment, the blocking junction may be provided by implanted regions of first conductivity type, such as the bottom surface224A of the trench270. The doping and geometry of the channel layer227of second conductivity type may then be separately optimized depending on the widths of the mesa278. Bottom surface224A of the trench270may provide a blocking junction and high-voltage capability. In an example embodiment, the side-wall251A implanted regions, such as a region of the first conductivity type251B may provide electrical connection to the base layer215and an electrostatic shielding effect of the base layer215in the blocking mode. In an example embodiment, the thickness of the base layer215and the emitter layer218, for example, may be 0.2 um and 0.25 um respectively. The base layer215and the emitter layer218may also be implanted with ion implanters with required energies, such as, for example under 360 keV for the base215and 60 KeV for the emitter218. This may provide a method of uniform doping control of the base layer215through ion implantation instead of epitaxial growth, which in turn results in a uniform and reproducible common emitter current gain of the TI-BJT245. In an example embodiment, the JBS diode248may provide a built-in antiparallel diode for switching applications, for example, in the H-bridge configuration. The width of the JBS diode248trenches270may be optimized to block the same voltage as the BJT and to provide forward current handling capability. In an example embodiment, the anode contact282may be formed on, for example, an un-etched and un-implanted virgin semiconductor surface, which may lead to lower device leakage levels. In another example embodiment, the shielding of the JBS diode248surface by the implanted regions, such as layer of first conductivity type, may also allow design of a lower forward voltage drop for a given level of blocking mode leakage current. In an example embodiment, monolithic integration may provide savings in the amount of device active area used. In an example embodiment, savings in chip size may become considerable at higher device voltage ratings, where a very wide edge termination may be needed for both transistor and diode.

FIG. 2Tillustrates an example embodiment that comprises a base layer215of a TI-BJT245region confined between two side-walls of the etched emitter mesa278, where the side-walls251A are implanted with layers of first conductivity type251B as the base, which form an electrical connection to the base ohmic contact221. In an example embodiment, the trench geometry may provide great versatility for optimizing the common emitter current gain, forward current, and device blocking voltage. Additionally, the width of the base215may be thin to provide a higher value of common emitter current gain so it does not have to support high voltage in blocking mode. The base layer215, for example, may be electrostatically shielded with a pinched-off JFET like structure described in, for example,FIGS. 2J and 2T, when a reverse bias is applied between the base layer215and collector of the TI-BJT245. In an example embodiment, epitaxial re-growth may not be required to fabricate such a device. For example, efficient electrostatic shielding of the base layer215, without a “punch-through” breakdown, may be achieved by utilizing tilted ion implants into side-walls251A of the trench270with energies, for example, below 360 keV and without needing, for example, deep MeV ion implantations were they to be done vertically as in the prior art.

FIGS. 3-5illustrate exemplary embodiments of manufacturing the TI-BJT245in accordance with the present invention.

In an example embodiment, monolithic integration of the TI-BJT and JBS diode248may be manufactured with implanted emitter layer218, base layer215, and channel layer227of the trench TI-BJT245, and a JBS diode248formed on unetched virgin epitaxial surface of the drift layer.FIG. 3Aillustrates an example embodiment of an initial wafer structure for the TI-BJT245with implanted emitter layer218, base layer215, and channel layer227, monolithically integrated with a planar non-etched JBS diode248. AsFIG. 3Aillustrates, the initial wafer structure may comprise the substrate236of second conductivity type and drift layer233of second conductivity type.

FIG. 3Billustrates an exemplary embodiment of the TI-BJT245with implanted emitter layer218, base layer215, and channel layer227, monolithically integrated with planar non-etched JBS diode248.FIG. 3Billustrates the combined ion implantation213for emitter layer218, base layer215and the channel layer227for the TI-BJT245.FIG. 3Cillustrates the trench270formation within the TI-BJT245with implanted emitter layer218, base layer215, and channel layer227, monolithically integrated with planar non-etched JBS diode248, where the JBS diode248region, for example, may be unetched.

FIG. 3Dillustrates an example embodiment of the vertical ion implantation of the first conductivity type201of the TI-BJT245.FIG. 3Dfurther illustrates vertical ion implantation201into the active area of the planar non-etched JBS diode248. In an example embodiment, in addition to the etching and etching mask204for the TI-BJT245active area, an additional masking material202may be formed to protect, for example, the Schottky regions of the JBS diode248from ion implantation, such as, for example, ion implantation201.

FIG. 3Eillustrates a cross-sectional view of a fabricated TI-BJT245with implanted emitter layer218, base layer215, and channel layer227, monolithically integrated with a planar non-etched JBS diode248. The challenge to this approach, for example, might be that deep ion implantation may be required for the channel layer227of the trench TI-BJT245. In an example embodiment, this approach may provide, for example, uniform doping control in emitter layer218, base layer215, and channel layer227across the entire wafer. In order to minimize field crowding at the lower right corner of the trench270formed between the JBS diode248and TI-BJT245, a bevel255, for example, may be implemented. As illustrated inFIGS. 3F and 3G, the bevel255is an implanted sidewall with a sloped transition from the plane of the bottom surface224A of the trench270to the semiconductor top surface. In an example embodiment, the bevel255region may be formed with techniques, such as, using an intentionally sloped side-wall of an etching mask204, and utilizing the difference in plasma etching205rates of semiconductor material and the etching mask204. In an exemplary embodiment, bevel255may be an angle in the range of 3 to 89 degrees with the bottom surface224A. Stated differently, bevel255may extend in the longitudinal direction L and the transverse direction T from the bottom surface224A towards the top surface of the region248

As illustrated inFIG. 3G, in an example embodiment, monolithic integration of a TI-BJT245with a fast unipolar antiparallel diode, such as diode248, may be accomplished by fabrication process of both a TI-BJT245and a diode248on the same chip, where the anode282of the antiparallel diode248shares the same overlay209metallization with the emitter ohmic contacts203of a TI-BJT245. Additionally, the wafer backside contact239may naturally serve as a cathode of a diode shared with a collector of the TI-BJT245. For example, the edge termination may be formed together with regions of first conductivity type, such as, region224B in the bottom surface224A of the trench270or region of the first conductivity type251B in the side wall(s)251A either in a form of multiple floating guard-rings, or JTE. In an example embodiment, the diode may be a Schottky, PiN, JBS JBS diode, or MPS (merged PiN and Schottky), or the like, or any appropriate combination thereof.

In an example embodiment, the entire structure may be manufactured based on a drift233layer of second conductivity type, without epitaxially grown base layer215and emitter layer218. In the example embodiment, the life-time enhancement may be implemented for very thick drift layers233in Silicon Carbide through high-temperature oxidation and subsequent annealing processes. The structure, for example, may also be manufactured on a zero degree off-cut wafer to fully eliminate basal-plane defects in case of Silicon Carbide. For example, the resulting step bunching and surface roughness may be polished off, and N++ emitter layer218of the second conductivity type and a base layer215of the first conductivity type may then be co-implanted. For example, this process may be useful for Silicon Carbide transistors with over 15 kiloVolt ratings, where the life time may not be long enough to provide efficient conductivity modulation in the drift layer233. For example, consumption of the surface layer through life-time enhancement and polishing may be negligible compared to the thickness of the drift layer233. In an example embodiment, the thickness of the drift layer233, may be, for example, over 120 μm in silicon carbide for >15 kV blocking voltage.

In an example embodiment, a TI-BJT245may be epitaxially grown.FIG. 4Aillustrates an initial wafer structure for all-epitaxial monolithically integrated TI-BJT245and JBS diode248. As illustrated byFIG. 4A, the original wafer structure may comprise the substrate236of second conductivity type, drift layer233of second conductivity type, and an epitaxially grown channel layer227of the second conductivity type. In one example embodiment, the base layer215and emitter layer218may also be epitaxially grown and instead of being implanted.

FIG. 4Billustrates trench formation for all-epitaxial monolithically integrated TI-BJT245and JBS diode248diode. As illustrated inFIG. 4B, the plasma etching205may penetrate through emitter layer218, base layer215, and partly or fully through channel layer227, and may stop within drift layer233. In contrast to the process illustrated inFIG. 2, the mesa278tops in JBS diode248region may have a heavier doped region218of second conductivity type and layer215of first conductivity type. In an example embodiment, these layers may have to be subsequently removed from the mesa278tops of JBS diode248. The etching mask204may be of a thickness to withstand plasma etching205and to block the subsequent ion implantations. This may prevent undesirable dopant compensation in the emitter layer218.

FIG. 4Cillustrates an example embodiment of selective etching of top epitaxial layers in the diode248region for the all-epitaxial TI-BJT245, monolithically integrated with trenched-and-implanted JBS diode248. As illustrated inFIG. 4C, the TI-BJT245may comprise selective plasma etching205of top epitaxial layers, such as the base layer215and emitter layer218in diode region248, stopping within the channel layer227. To accomplish this,FIG. 4Cshows the implementation of a dual masking step, wherein layer208is first deposited and then removed from the diode area248. Thereafter, a second layer210is deposited and etched back to expose the mesa278tops in the diode area248. The mask layers may be selected to provide good selectivity over the semiconductor during etching, e.g., Nickel. In an example embodiment, the mesa278region in the TI-JBS diode area248may then be etched to remove the emitter layer218and base epi layers215and exposing the channel layer227surface for Schottky formation in a subsequent step. In another example embodiment, the rest of the steps to manufacture the fabrication of the TI-BJT245may be similar to the steps to manufacture the fabrication of the TI-BJT245described inFIG. 2.

FIG. 4Dillustrates an example embodiment of a cross-sectional view of a fabricated all-epitaxial TI-BJT245, monolithically integrated with JBS diode248. It should be understood that a JBS diode248may also be referred to as a TI-JBS diode. As illustrated inFIG. 4Dand in contrast to the process described inFIG. 2T, the anode contact282of the JBS diode248may be formed on the surface, where the base layer215and the emitter layer218were etched.

FIG. 5Aillustrates an example embodiment of a trench270formation for an all-epitaxial monolithically integrated TI-BJT245and planar-etched JBS diode248. Another example embodiment of a monolithic integration of TI-BJT245and JBS diode248may be accomplished with the same wafer structure as illustrated inFIG. 4A. For example, JBS diode248may be formed on a single plane without trenches270by planar etching of the entire JBS diode248region by, for example, plasma etching. As illustrated inFIG. 5A, the TI-BJT245may include, selective plasma etching205of the top epitaxial layers, such as the base layer215, emitter layer218and the channel layer227, and stopping within drift layer233.

FIG. 5Billustrates the ion implantation205of first conductivity type205into the blocking pn-junction bottom surface224A of the trench270of TI-BJT245and the active area of the planar-etched JBS diode248. In addition to etching and etching mask204for the TI-BJT245active area, for example, an additional masking material202may be formed to protect Schottky regions of the JBS diode248from ion implantation201.

FIG. 5Cillustrates a schematic cross-sectional view of a fabricated all-epitaxial monolithically integrated TI-BJT245and planar-etched JBS diode248. In an example embodiment, this approach may enable the JBS diode248active structure to be independently defined without forming, for example, high-aspect ratio trenches270.

FIG. 6A-Dshow an example embodiment of exemplary schematic arrangements of BJT and diode unit cells within a monolithically integrated device structure from above the device structure along the transverse direction T.FIG. 6Aillustrates an example embodiment of a basic stripe layout, where the interdigitated TI-BJT245mesa601of the emitter601and base ohmic contacts602are separated with an isolation region603from linear Schottky604and implanted605patterns of an integrated diode. In an example embodiment, the ratio N1:N2 of emitter mesa278to Schottky regions may be determined based on required ratio of TI-BJT245and diode248forward currents.

FIG. 6Billustrates an example embodiment of a staggered closed cell arrangement of TI-BJT245and diode248unit cells within the monolithically integrated device structure. In an example embodiment, the ratio of diode248area to TI-BJT245region may be 1:1 or 1:N and may be determined based on required ratio of the forward currents of the TI-BJT245and diode248.

FIG. 6Cillustrates an example embodiment of schematic hexagonal cell arrangement of TI-BJT245and diode248unit cells within monolithically integrated device structure. In an example embodiment, the ratio of hexagon side lengths L1:L2 may be determined based on required ratio of the forward currents of the TI-BJT245and diode248.

FIG. 6Dillustrates an example embodiment of a cell arrangement of circular TI-BJT245and circular diode248unit cells within the monolithically integrated device structure.

In an example embodiment, the JBS diode248may inject minority carriers into the drift layer233. If JBS diode248, for example, operates in bipolar mode, i.e. injects minority carriers into the drift layer233, it may be referred to an MPS (merged PiN-Schottky). For example, instead of JBS diode248, a pure Schottky diode may be manufactured by eliminating ion implantation of first conductivity type into JBS diode248active area. In another example embodiment, a Schottky contact may be formed over the wide area. A PiN diode, for example, may be defined by implanting the entire diode248active area with the dopants of first conductivity type, and forming the anode ohmic contact instead of Schottky.

FIG. 7Aillustrates an example embodiment of a schematic cross-sectional view of a fabricated TI-BJT245monolithically integrated with planar-etched PiN diode249. As further illustrated inFIG. 7A, the monolithic integration of the TI-BJT245may also consist of an anode ohmic contact214of the diode.

FIG. 7Billustrates a schematic cross-sectional view of a fabricated TI-BJT245monolithically integrated with planar-unetched Schottky diode252. As further illustrated inFIG. 7B, the monolithic integration of the TI-BJT245may also consist of an anode contact282of the diode252. It should be understood that anode contact may also be referred to as an anode Schottky contact.

As depicted and disclosed in the above figures, it should be understood that the various embodiments of the BJT and antiparallel diodes may be understood with reference to a first, second, and third direction such as, for example, lateral direction ‘A’, a longitudinal direction ‘L’ which is perpendicular to lateral direction ‘A’, and a transverse direction ‘T’ which is perpendicular to longitudinal direction ‘L.’ As illustrated in the above figures, the longitudinal direction L and the lateral direction A extend horizontally as illustrated, and the transverse direction T extends vertically, though it should be appreciated that these directions may change depending, for instance, on the orientation of TI-BJT.

For example, inFIGS. 2A-2J, the transverse direction T and the longitudinal direction L are shown while the lateral direction A extends into and out of the page. Side-walls251A of the respective trenches270may be substantially planar walls251A which extend in the transverse direction T and the lateral direction A. Similarly, implanted regions251B in side walls251A may also extend in the transverse direction T and the lateral direction A. The side walls251A of each trench270and mesa278may be spaced apart from one another along the longitudinal direction L. Side walls251A may extend fully or partially through one or more of substrate layer236, drift layer233, channel layer227, base layer215, and emitter layer218along the transverse direction T.

Side-walls251A may be understood to be side-walls251A of mesas278as well as trenches270. The height of consecutive side-walls278may further define the depth of an exemplary trench270as well as the height of an exemplary mesa278. For example, consecutive side-walls may each have a height defined by the distance each side-wall extends (1) in the transverse direction T, (2) between the top of the mesa and the bottom surface224A of the mesa, and (3) through one or more of substrate layer236, drift layer233, channel layer227, base layer215, and emitter layer218. In an exemplary embodiment, the height of consecutive side walls may exclude contacts203,221formed in the trench or on top of the mesa. Exemplary mesas278may have a width defined by the distance consecutive side walls251A are spaced apart from one another along the longitudinal direction L. Similarly, exemplary trenches270may have a width defined by the distance consecutive side walls251A which are spaced apart from one another along the longitudinal direction L.

Further, bottom surfaces224A of trenches270may also be substantially planar and extend in the longitudinal direction L and the lateral direction A. Respective layers, such as substrate layer236, drift layer233, channel layer227, base layer215, and emitter layer218, may each have a substantially planar upper and lower surface (when moving along the transverse direction T from the emitter layer218towards the channel layer227) which extend along the longitudinal direction L and the lateral direction A. These layers may also have a thickness, which extends along the transverse direction, and be stacked one on top of another along the transverse direction T. Similarly, implanted regions224B of the first conductivity type may also extend along the bottom surface224A of the trench.

For example, in accordance with the various embodiments disclosed herein, a trenched-and-implanted bipolar junction transistor (TI-BJT) is disclosed. The TI-BJT may include a drift layer of a second conductivity type; a channel layer of the second conductivity type formed on top of the drift layer; a base layer of a first conductivity type formed on top of the channel layer, wherein the base layer has a thickness which extends along a first direction, wherein the thickness is in the range of 0.02 to 2 microns; and an emitter layer of the second conductivity type formed on top of the base layer, the emitter layer having a bottom surface located adjacent to the base layer and a top surface opposite the first bottom surface along the first direction. The TI-BJT may also include at least one U-shaped trench formed in at least the emitter layer, base layer, and channel layer. The at least one U-shaped trench may include: a first side surface, a second side surface, and a bottom surface, the first side surface, second side surface, and the bottom surface being substantially planar; the first and the second side surfaces spaced apart along a second direction, the second direction being perpendicular to the first direction, the first and second side surfaces extending (1) along the first direction, (2) from the top surface of the emitter layer to the bottom surface of the at least one U-shaped trench, and (3) through the emitter layer, through the base layer, and at least partially into the channel layer; and the bottom surface of the at least one U-shaped trench extending (1) along the second direction and (2) between the first and the second wall of the at least one U-shaped trench. The TI-BJT may further include at least one implanted U-shaped conductivity region of the first conductivity type, the U-shaped region of the first conductivity type comprising: a first portion extending along the bottom surface of the at least one U-shaped trench; a second portion and a third portion extending (1) along the first and the second side surfaces of the at least one U-shaped trench, respectively, and (2) between the bottom surface of the emitter layer and the bottom surface of the at least one U-shaped trench; and a base electrode disposed between the first and the second side surfaces of the at least one U-shaped trench.

In another embodiment, the TI-BJT may also include a second U-shaped trench formed in the emitter layer, base layer, and channel layer, the second U-shaped trench including: a first side surface, a second side surface, and a bottom surface, the first side surface, second side surface, and the bottom surface being substantially planar; the first and the second side surfaces of the second U-shaped trench spaced apart along a second direction, the second direction being perpendicular to the first direction, the first and second side surfaces extending (1) along the first direction, (2) from the top surface of the emitter layer to the bottom surface of the second U-shaped trench, and (3) through the emitter layer, through the base layer, and at least partially into the channel layer; and the bottom surface of the second U-shaped trench extending (1) along the second direction and (2) between the first and the second wall of the second U-shaped trench; a second implanted U-shaped conductivity region of the first conductivity type, the U-shaped region of the first conductivity type comprising: a first portion extending along the bottom surface of the second U-shaped trench; a second portion and a third portion extending (1) along the first and the second side surfaces of the second U-shaped trench, respectively, and (2) between the bottom surface of the emitter layer and the bottom surface of the second U-shaped trench; and a base electrode disposed between the first and the second side surfaces of the second U-shaped trench. The TI-BJT may also include at least one mesa, the at least one mesa comprising: a first side wall defined by the first side wall of the at least one U-shaped trench and a second side wall defined by the second side wall of the second U-shaped trench; and an unetched region of the emitter layer, base layer, and channel layer extending between the first and the second side walls of the at least one mesa.

In yet another embodiment, the TI-BJT may include an antiparallel diode, monolithically integrated with the TI-BJT, the antiparallel diode comprising an anode electrode and a cathode electrode; a first electric connection between the emitter electrode of the TI-BJT and the anode electrode of the antiparallel diode; wherein the collector electrode of the TI-BJT is the cathode electrode of the antiparallel diode; an electrically inactive isolation region, the electrically inactive isolation region providing an electric isolation between the anode electrode of the antiparallel diode and the base electrode of the BJT, wherein the electrically inactive isolation region increases voltage blocking capability between the BJT base and JBS anode; and a shared edge termination region for the TI-BJT and the antiparallel diode.

In another further embodiment of an integrated TI-BJT and antiparallel diode, the TI-BJT may include at least one of the first side and the second side of the at least one U-shaped trench of the TI-BJT extend a first distance along the first direction, and the emitter layer and the base layer of the TI-BJT formed by ion implantation of the channel layer. The antiparallel diode may include a trenched-and-implanted Junction Barrier Schottky diode (TI-JBS diode), the TI-JBS diode comprising: the drift layer; the channel layer; two adjacent trenches, the two adjacent trenches spaced a second distance from one another along the second direction; and at least one of the two adjacent trenches having a depth that extends the first distance along the first direction; and a mesa, the mesa comprising: a first side wall and a second side wall of the mesa defined by the depth of the at least two adjacent trenches; an unetched and implanted region of the channel layer extending between the first and the second side walls of the mesa, the unetched and implanted region of the mesas including a top surface of the channel layer that is coplanar with the top surface of the emitter layer of the TI-BJT along the second direction; a second and a third implanted conductivity region of the first conductivity type extending along the first and second side walls of the mesa, respectively; and an electrical contact formed on the top surface of the mesa.

In another embodiment of an integrated TI-BJT and antiparallel diode, the TI-BJT may include the emitter, base, and channel layers of the TI-BJT formed by ion implantation of the drift layer. The antiparallel diode may include an unetched Junction Barrier Schottky diode (JBS diode) comprising: the drift layer, the drift layer including a top surface that is coplanar with the top surface of the emitter layer of the TI-BJT along the second direction; a second and a third implanted conductivity region of the first conductivity type extending from the top surface of the drift layer into the drift layer, the second and third implanted conductivity regions being separated by an implanted region of the second conductivity type along the second direction; and a vertical etched step extending along the first direction, the vertical etched step disposed between the isolation region and the second and third implanted regions along the second direction.

In yet another embodiment of an integrated TI-BJT and antiparallel diode, the TI-BJT may include the emitter, base, and channel layers of the TI-BJT formed by ion implantation of the drift layer. The antiparallel diode may include a planar, unetched Junction Barrier Schottky diode (JBS diode) comprising: the drift layer, the drift layer including a top surface that is coplanar with the top surface of the emitter layer of the TI-BJT along the second direction; a second and a third implanted conductivity region of the first conductivity type extending from the top surface of the drift layer into the drift layer, the second and third implanted conductivity regions being separated by an implanted region of the second conductivity type along the second direction; and a sloped side wall extending along the first and the second directions, the sloped side wall disposed between the isolation region and the second and third implanted regions along the second direction.

In yet another embodiment of an integrated TI-BJT and antiparallel diode, the TI-BJT may include at least one of the first side and the second side of the at least one U-shaped trench of the TI-BJT which extend a first distance along the first direction, and the emitter, base, and channel layers of the TI-BJT are formed epitaxially. The antiparallel diode may include a trenched-and-implanted Junction Barrier Schottky diode (TI-JBS diode), the TI-JBS diode comprising: the drift layer; the channel layer; two adjacent trenches, the two adjacent trenches spaced a second distance from one another along the second direction; at least one of the two adjacent trenches having a depth that extends a third distance along the first direction, the third distance being less than the first distance; a mesa, the mesa comprising: a first side wall and a second side wall of the mesa defined by the depth of the at least two adjacent trenches; an etched and implanted region of the channel layer extending between the first and the second side walls of the mesa, the etched and implanted region of the mesa including a top surface of the channel layer that is below with the top surface of the emitter layer of the TI-BJT along the first direction extending from the emitter layer towards the base layer; a second and a third implanted conductivity region of the first conductivity type extending along the first and second side walls of the mesa, respectively; and an electrical contact formed on the top surface of the mesa.

In an embodiment of an integrated TI-BJT and antiparallel diode, the TI-BJT may include the emitter, base, and channel layers of the TI-BJT are formed epitaxially or by ion implantation. The antiparallel diode may include a planar, etched Junction Barrier Schottky diode (JBS diode) comprising: the drift layer, the drift layer being implanted and including an etched top surface that is disposed below the channel layer of the TI-BJT along the first direction extending from the emitter layer towards the channel layer; a second and a third implanted conductivity region of the first conductivity type extending from the top surface of the drift layer into the drift layer, the second and third implanted conductivity regions being separated by an implanted region of the second conductivity type along the second direction.

Methods of forming the above embodiments are also disclosed.

In the exemplary embodiments described above in connection withFIGS. 2A-7B, the thickness of base layer215may be in the range of 20 nm to 1000 nm. In another embodiment, the thickness of the drift layer233may be in the range of 0.1 microns to 1000 microns. In an example embodiment, the depths of regions251B and224B may be in the range of 20 nm to 1000 nm or in the range 0.02 to 2 microns. In an example embodiment, the ratio of the width of an exemplary mesa278in the BJT region245(i.e., a BJT mesa278) to its height (i.e., the trench depth) may be in the range of 1:6 to 2:1. In another exemplary embodiment, the ratio of the width of a BJT mesa278to its height (i.e., the trench depth) may be in the range of 1:6 to 6:1. In an embodiment, the base layer215may have a thickness is in the range of 0.02 to 2 microns. In another embodiment, the emitter electrode203may have a thickness of 0.1 to 2 microns.

It should be understood that, the semiconductor devices, described herein, may be manufactured from semiconductor materials, such as Si, SiC, GaAs, diamond, InP, AlN, GaN. BJTs made in silicon carbide (SiC), including its polytypes such as 4H-, 6H-, or 3C-SiC may be of interest for power conversion applications due to their high voltage blocking capability and very low conduction losses. In an example embodiment, the same blocking voltage may be achieved in SiC with, for example, ˜10× thinner drift layers than in silicon, that may result in smaller stored minority carrier charge and faster device turn-off time. The on-resistance of a SiC BJT may increase with temperature, while the common emitter current gain may decrease, which may make device paralleling easy and eliminates thermal run-away.

In accordance with the exemplary embodiments of the invention described above JBS diodes may be replaced with PiN diodes or pure SBD (Schottky Barrier Diode).

When ranges are used herein for physical properties, such as molecular weight, or chemical properties, such as chemical formulae, all combinations, and sub combinations of ranges for specific embodiments therein are intended to be included.

The disclosures of each patent, patent application, and publication cited or described in this document are hereby incorporated herein by reference, in its entirety.

In describing preferred embodiments of the subject matter of the present disclosure, as illustrated in the figures, specific terminology is employed for the sake of clarity. The claimed subject matter, however, is not intended to be limited to the specific terminology so selected, and it is to be understood that each specific element includes all technical equivalents that operate in a similar manner to accomplish a similar purpose.