Magnetic memory cells and manufacturing methods

An improved magnetoresistive memory device has a reduced distance between the magnetic memory element and a conductive memory line used for writing to the magnetic memory element. The reduced distance is facilitated by forming the improved magnetoresistive memory device according to a method that includes forming a mask over the magnetoresistive memory element and forming an insulating layer over the mask layer, then removing portions of the insulating layer using a planarization process. A conductive via can then be formed in the mask layer, for example using a damascene process. The conductive memory line can then be formed over the mask layer and conductive via.

TECHNICAL FIELD

This invention relates to semiconductor memory devices, particularly those utilizing a magnetoresistive structure for data storage.

BACKGROUND

Magnetic random access memory (MRAM) is non-volatile memory that uses magnetism rather than electrical power to store data.FIG. 1shows a schematic diagram of a portion10of an MRAM array, which includes a plurality of memory cells12–19and a series of conductive lines40–48. Each memory cell12–19includes a magnetoresistive (MR) memory element20–27and a transistor30–37. For this reason, the architecture shown inFIG. 1is referred to as1T1MTJ (one transistor, one MTJ) architecture.

As shown inFIG. 1, the transistors30–33are coupled to each other via a word line (WL1)40, and transistors34–37are coupled to each other via a word line (WL2)41, where the word lines40,41form the gate electrode for the transistors30–37. The transistors30–33are also coupled to each other via a program line (PL1)42, and transistors34–37are coupled via a program line (PL2)43, where the program lines42,43serve as virtual ground lines. Similarly, the MR memory elements20and24are coupled to each other by bit line (BL1)45, MR memory elements21and25are coupled to each other by bit line (BL2)46, MR memory elements22and26are coupled to each other by bit line (BL3)47, and MR memory elements23and27are coupled to each other by bit line (BL4)48. The bit lines45–48are typically somewhat perpendicular to the word lines40,41and the program lines42,43.

The terminology used in the art for the various conductive lines (e.g., bit lines, program lines, and word lines) can vary. For example, the “bit lines” inFIG. 1are sometime referred to as “word lines” or “upper write lines,” and the “program lines” inFIG. 1are sometimes referred to as “digit lines” or “bottom write lines.” For the sake of clarity, the terminology used in connection withFIG. 1will be used throughout the present document.

Each of the MR memory elements20–27can be a multi-layer magnetoresistive structure, such as a magnetic tunneling junction (MTJ) or a giant magnetoresistive (GMR) structure.FIG. 2shows an example of a typical MTJ structure50. The MTJ structure50includes four basic layers: a free layer52, a spacer54which serves as a tunneling barrier, a pinned layer56, and a pinning layer58. The free layer52and the pinned layer56are constructed of ferromagnetic material, for example cobalt-iron or nickel-cobalt-iron. The pinning layer58is constructed of antiferromagnetic material, for example platinum manganese. Magnetostatic coupling between the pinned layer56and the pinning layer58causes the pinned layer56to have a fixed magnetic moment. The free layer52, on the other hand, has a magnetic moment that, by application of a magnetic field, can be switched between a first orientation, which is parallel to the magnetic moment of the pinned layer56, and a second orientation, which is antiparallel to the magnetic moment of the pinned layer56.

The spacer54interposes the pinned layer56and the free layer52. The spacer54is composed of insulating material, for example aluminum oxide, magnesium oxide, or tantalum oxide. The spacer54is formed thin enough to allow the transfer (tunneling) of spin-aligned electrons when the magnetic moments of the free layer52and the pinned layer56are parallel. On the other hand, when the magnetic moments of the free layer52and the pinned layer56are antiparallel, the probability of electrons tunneling through the spacer54is reduced. This phenomenon is commonly referred to as spin-dependent tunneling (SDT).

As shown inFIG. 3, the electrical resistance through the MTJ50(e.g., from layer52to layer58or vice-versa) increases as the moments of the pinned and free layers become more antiparallel and decreases as they become more parallel. In an MRAM memory cell, the electrical resistance of the MTJ50can therefore be switched between first and second resistance values representing first and second logic states. For example, a high resistance value can represent a logic state “1” and a low resistance value can represent a logic state “0.” The logic states thus stored in a memory cell can be read by passing a sense current through the MR memory element and sensing the resistance. For example, referring back toFIG. 1, the logic state of memory cell12can be read by passing a sense current through bit line (BL1)45, activating transistor30via word line (WL1)40, and sensing the current passing from (BL1)45through the MTJ20and on to program line (PL1)42.

During a write operation, electrical current flows through a program line42,43and a bit line45–48that intersect at the target memory cell12–19. For example, in order to write to memory cell13, a current is passed through program line (PL1)42and a current is passed through bit line (BL2)46. The magnitude of these currents is selected such that, ideally, the resulting magnetic fields are not strong enough on their own to affect the memory state of the MR memory elements20–23and25, but the combination of the two magnetic fields (at MR memory element21) is sufficient for switching the memory state (e.g., switching the magnetic moment of the free layer52) of the MR memory element21.

A method of fabricating a magnetic memory device is disclosed in U.S. Pat. No. 6,713,802 to Lee. Specifically, this patent discloses the use of a damascene process to create a via connection between a top write line (corresponding to a “bit line” inFIG. 1) and the MTJ. A film (mask128) is used as an insulating layer in which vias can be formed, and it is also used as a stop layer for a dielectric CMP process. Since this film (mask128) is used as a stop layer for dielectric CMP, it has a minimum thickness of about 4000 angstroms in order to protect against being etched through itself. But because the top write line is used for generating a magnetic field for writing to the MTJ, it is desirable to have the write line as close to the MTJ as possible. Thus the thickness requirement of the interconnect film (mask128) competes with the desire to place the write line closer to the MTJ.

SUMMARY

Disclosed herein is an improved magnetoresistive memory device having a reduced distance between the magnetic memory element and a conductive memory line used for writing to the magnetic memory element. By reducing the distance between the memory element and the write line, the write current can be reduced in the write line for write operations, which in turn reduces the risk of cross-talk between neighboring memory cells.

According to the present disclosure, a magnetic memory device, for example an MRAM memory device, can be produced that has a distance between the magnetic memory element and the write line that is less than 1500 angstroms, for example in a range of 300 angstroms to 1500 angstroms. Such a device can be fabricated according to disclosed methods, which include forming a mask layer over the magnetoresistive memory element and an insulating layer over the mask layer, then removing portions of the insulating layer using a planarization process, for example CMP. Vias can then be formed in the mask layer, for example using a damascene process, and then conductive memory lines can be formed over the mask layer and into the vias in order to effect an electrical connection between the conductive memory lines and the MTJs.

DETAILED DESCRIPTION

FIG. 4shows a schematic cross-sectional view of an early stage in the fabrication process. At the stage shown inFIG. 4, the device includes a substrate110having a dielectric layer112formed thereon, a series of conductive elements114–117, an insulating layer (spacer)122, an electrode layer124, and a magnetoresistive layer126.

The substrate110can be a semiconductor substrate, such as a p-type silicon wafer with <100> crystal surface. The substrate110can also include any other suitable semiconductor material, for example GaAs, InP, SiC, or Si/Ge. The substrate110can also include active components or circuits formed in the front end of the line (FEOL), not shown.

In one embodiment the substrate110is provided as a base for forming the MRAM circuits and the wafer substrate is initially planarized, for example using wet chemical mechanical polishing (CMP). The substrate110may be formed then processed to comprise planar circuit elements (not shown) such as MOSFETS or other transistors or circuits using implanted or deposited circuit elements. A dielectric layer112is then formed over the substrate110including any circuit elements formed in or on the substrate110. The dielectric layer112can be referred to as an inter-level dielectric (ILD) layer, which may be the wafer's first layer that substantially establishes a new planarized surface. In some embodiments, the dielectric layer112can include multiple sub-layers (not shown). For example, the dielectric layer112can include a first sub-layer formed with silicon oxynitride (SiON), a second sub-layer formed over the first sub-layer with plasma-enhanced oxide (PEOX), and a third sub-layer formed over the second sub-layer with SiON, where the first sub-layer can have a thickness in a range of 1050 Å to 1350 Å, for example 1200 Å, the second sub-layer can have a thickness in a range of 2100 Å to 2900 Å, for example 2500 Å, and the third sub-layer can have a thickness in a range of 1050 Å to 1350 Å, for example 1200 Å. The dielectric layer112can also be planarized using a reflow process or spin-on glass deposition.

The dielectric layer112is patterned, etched, and filled with a conductive material to form the conductive elements114–117, e.g., using a damascene process. The pattern and fill process may comprise a single damascene or dual-damascene process, with vias connecting to substrate circuit elements (not shown) being filled at the same time as the conductive elements114–117. The dielectric layer112can be lithographically patterned, for example using photolithography, and reactive ion etched (RIE) to form trenches where the conductive elements114–117will be formed. In embodiments where photolithography is used, the dielectric layer112can include an upper sub-layer of SiON for use as an antireflective coating (ARC) in order to improve control of the photolithography process.

The conductive elements114–117comprise a conductive material, for example Cu, Al, TiN, Ti, W, combinations thereof, or other conductive materials. Depending on the conductive material used, the conductive elements114–117can include an optional liner (not shown). For example, if copper is used for the conductive elements114–117, the optional liner can first be deposited to form a diffusion barrier for confining the copper. In this case, the optional liner can be formed of Ta or TaN or any other material that is a good diffusion barrier for confining copper. Conductive material is deposited over the dielectric layer112and within the trenches using any deposition technique suitable for the conductive material selected. For example, in the case of copper, electrodeposition (e.g., electroplating) can be used for deposition. As an alternative, any of a number of known deposition processes can be used, for example chemical vapor deposition (CVD) or physical vapor deposition (PVD). A CMP or other etching process is then used for removing the excessive conductive material from above the top surface of the dielectric layer112.

After the exposed surfaces of the dielectric layer112and the conductive elements114–117have been planarized, the insulating layer122is deposited over the planarized surface. The insulating layer122can be formed to have any thickness suitable for allowing the insulating layer122to provide electrical isolation, for example between the conductive elements115,117and an electrode layer124discussed below, for example 600 Å. The insulating layer122is formed of a dielectric material, for example SiN. As an alternative, the insulating layer122can be formed of SiON, SiCN, or SiC. The insulating material can be deposited by any deposition process appropriate for the selected dielectric material. For example, SiN can be deposited using a plasma enhanced chemical vapor deposition (PECVD) process.

The insulating layer122is patterned and etched to expose the upper surfaces of the conductive elements114and116. The insulating layer122can be lithographically patterned, for example using photolithography, and reactive ion etched (RIE) to form trenches over the upper surfaces of the conductive elements114and116.

The electrode layer124is formed over the insulating layer122and the exposed surfaces of the conductive elements114and116. The electrode layer124is a conductive layer serving as a lower electrode of the magnetoresistive elements formed in steps described below. The electrode layer124can be formed of any conductive material, for example the electrode layer124can be a layer of tantalum (Ta) formed by CVD to have a thickness greater than 200 Å.

The magnetoresistive layer126is formed over the electrode layer124. In some embodiments, the magnetoresistive layer126includes layers for forming a magnetic tunnel junction. In such embodiments, the magnetoresistive layer126includes an antiferromagnetic layer formed over the electrode layer124, a first ferromagnetic layer (“pinned” layer) formed over the antiferromagnetic layer, a tunnel barrier formed over the first ferromagnetic layer, a second ferromagnetic layer (“free” layer) formed over the tunnel barrier, and a capping layer/upper electrode layer formed over the second ferromagnetic layer.

When the MR layer126includes layers for forming a magnetic tunnel junction, the ferromagnetic layers can be formed of ferromagnetic materials comprising cobalt (Co), iron (Fe), nickel (Ni), or alloys containing these elements. For example, materials that can be used for the ferromagnetic layers can be a Co90Fe10(at %) alloy, a CoFeNi alloy, or a Ni80Fe20alloy (permalloy). The tunnel barrier can be formed of an insulating material, for example an aluminum oxide (e.g., AlOx) such as Al2O3or a nitride such as AlN. The antiferromagnetic layer can be formed of an antiferromagnetic material comprising a manganese (Mn)-based alloy containing, for example, iron (Fe), platinum (Pt), iridium (Ir), rhodium (Rh), ruthenium (Ru), or palladium (Pd). For example, materials that can be used for forming an AFM layer can be an FeMn alloy, a PtMn alloy, a PtPdMn alloy, or an IrMn alloy. The ferromagnetic pinned layer can be a multi-layered structure. The ferromagnetic pinned layer can comprise a synthetic antiferromagnetic (SAF) structure that includes a pair of ferromagnetic layers separated by a layer of Ruthenium (Ru).

Examples of suitable thicknesses for the magnetic tunnel junction layers of the magnetoresistive layer126are summarized in Table 1 below. In Table 1, “FM FREE” refers to the ferromagnetic free layer, “FM PINNED” refers to the ferromagnetic pinned layer, “AFM” refers to the antiferromagnetic pinning layer, and “TB” refers to the tunnel barrier. It should be noted that these thicknesses are not intended to be limiting in any way, but instead are provided merely as examples.

In the magnetoresistive layer126described above comprising a magnetic tunnel junction, the magnetoresistive layer126can include as a free/spacer/pinned/pinning series of layers. In such a structure, the magnetization direction of the free layer is free to change under the influence of an applied magnetic field. The magnetization direction of the pinned layer is fixed to a particular direction due to exchange coupling with an antiferromagnetic pinning layer. The antiferromagnetic pinning layer can be initialized during manufacturing to have a particular exchange bias that determines the pinning direction, or the direction in which the magnetization direction of the ferromagnetic pinned layer will be set.

The exchange bias of the antiferromagnetic pinning layer can be set using an initialization process. In order to initialize the exchange bias of the antiferromagnetic pinning layer and pin the ferromagnetic pinned layer, these layers are heated to a blocking temperature (e.g., at or above the Néel temperature of the antiferromagnetic material) and then subsequently cooled to an ambient temperature in the presence of a magnetic field.

During the initialization process, a strong magnetic field, for example a field of 2000 oersteds, is applied in a direction parallel to the desired magnetization direction. The layers are heated in the presence of the applied magnetic field to a blocking temperature, for example to a temperature greater than 200° C. (e.g., 200° C.–300° C.), for any amount of time necessary, for example in a range of 15 minutes to several hours, depending upon the material. The layers are then cooled in the presence of the applied magnetic field to fix the pinned layer magnetization and exchange bias at the desired direction. Magnetic exchange coupling between the antiferromagnetic pinning layer and the ferromagnetic pinned layer will keep the magnetization direction of the ferromagnetic pinned layer fixed.

The magnetoresistive layer126includes a capping layer, for example deposited over the magnetic tunnel junction layers. The capping layer comprises approximately 10 nm of a material such as WN, TiN, Ta, or TaN.

As shown inFIG. 5, the magnetoresistive layer126is patterned and etched to expose the upper surface of the electrode layer124, except in regions over the conductive elements115and117, to form magnetoresistive elements126A and126B. The magnetoresistive layer126can be lithographically patterned, for example using photolithography, and reactive ion etched (RIE) to stop on the Ta material of the electrode layer124.

Referring next toFIG. 6, a hard mask layer128is next formed over the exposed surfaces of the electrode layer124and the magnetoresistive elements126A and126B. The hard mask layer128will serve as a stop layer for an oxide CMP process described below. The thickness of the hard mask layer128will ultimately define the distance between the magnetoresistive elements126A,126B and the upper write line138(discussed below, seeFIG. 10). For this reason, it is desirable to use a minimal thickness for the hard mask layer128, for instance a thickness equal to or less than approximately 1500 Å. For example, the hard mask layer128can be formed to have a thickness in a range of 300 Å to 1500 Å, or in a range of 550 Å to 850 Å, for example 600 Å. The hard mask128can be formed of any material suitable for use as an oxide CMP stop. For example, the hard mask128can be formed of SiN since oxide CMP processes can be used that have high selectivity “Oxide to SiN”. The SiN can be deposited using a low-temperature deposition process, for example PECVD in a range of approximately 300° C. to 350° C. A low-temperature deposition process for forming the mask layer128will prevent damage to the magnetoresistive structure, which is sensitive to higher temperatures, for example above 400° C.

The mask layer128and electrode layer124are then patterned and etched to expose portions of the upper surface of the insulating layer122as shown inFIG. 6. The mask layer128and electrode layer124can be lithographically patterned, for example using photolithography, and reactive ion etched (RIE). This step allows for isolation of portions of the electrode layer124.

Referring next toFIG. 7, a insulating layer130is next formed over the exposed surfaces of the mask layer128, the insulating layer122, and the electrode layer124. The insulating layer130can be formed of a dielectric material. For example, the insulating layer130can be formed of an oxide such as SiO2. The SiO2can be deposited using a low-temperature deposition process, for example PECVD in a range of approximately 300° C. to 350° C. As described above with respect to formation of the mask layer128, a low temperature deposition process for forming the insulating layer130will prevent damage to the magnetoresistive structure, which is sensitive to higher temperatures.

Referring next toFIG. 8, the insulating layer130is planarized using a CMP process having a high degree of selectivity between the material of the insulating layer130and the material of the hard mask layer128so that the hard mask layer128can serve as a CMP stop. For example, in some embodiments, the hard mask layer128is formed of SiN, the insulating layer is formed of SiO2, and an oxide CMP process having a high degree of selectivity between SiO2and SiN is used to planarize the insulating layer130, stopping flush with the upper surface of the hard mask layer128as shown inFIG. 8.

Next, the mask layer128(and in some cases remnants of the insulating layer130) is patterned, etched, and filled with a conductive material to form conductive vias132–134, e.g., using a damascene process. The mask layer128can be lithographically patterned, for example using photolithography, and reactive ion etched (RIE) to form the openings where the conductive vias132–134will be formed.

The conductive vias132–134comprise a conductive material, for example Cu, Ta, TaN, Al, TiN, Ti, W, combinations thereof, or other conductive materials. Conductive material is deposited over the exposed surfaces of the hard mask layer128and the insulating layer130and within the trenches using any deposition technique suitable for the conductive material selected. For example, in the case of copper, electrodeposition (e.g., electroplating) can be used for deposition. Any of a number of known deposition processes can be used, for example chemical vapor deposition (CVD) or physical vapor deposition (PVD) can be used for Ta or TaN. A metal CMP process may then be used for removing the excessive conductive material from above the top surface of the hard mask layer128and the insulating layer130.

Referring next toFIG. 9, an insulating layer136is next formed over the exposed surfaces of the mask layer128, the insulating layer130, and the vias132–134. The insulating layer136will serve as an electrical insulator between upper conductive lines (e.g., bit lines, etc.). Thus, the insulating layer136can be formed of a dielectric material. For example, the insulating layer136can be formed of an oxide such as SiO2. The SiO2can be deposited using a low-temperature deposition process, for example PECVD in a range of approximately 300° C. to 350° C. A low-temperature deposition process for forming the insulating layer136will prevent damage to the magnetoresistive structure, which is sensitive to higher temperatures, for example above 400° C.

Referring next toFIG. 10, a conductive line138is formed in the insulating layer136. The conductive line138can be formed of any conductive material. Depending on the conductive material used, the conductive line138can include an optional liner (not shown). For example, if copper is used for the conductive line138, the optional liner can first be deposited to form a diffusion barrier for confining the copper. In this case, the optional liner can be formed of Ta or TaN or any other material that is a good diffusion barrier for confining copper. The conductive line138can be formed by etching a suitable pattern in the insulating layer136, for example using photolithography, and depositing or plating a selected conductive material. The upper surface of the structure can then be planarized using CMP to remove excess conductive material from the upper surface of the insulating layer136. From this point, subsequent processing can be performed to complete the manufacturing of the memory device.

It should be noted that the use of the term “layer” should not be construed to impose limitations, particularly with respect to how a “layer” is formed, for example a “layer” as referred to herein can be formed by one or multiple layer-forming steps, such as using one or more steps of deposition for forming what is termed herein as a “layer”.