Device structure and methods of making high density MOSFETs for load switch and DC-DC applications

Aspects of the present disclosure describe a high density trench-based power MOSFETs with self-aligned source contacts and methods for making such devices. The source contacts are self-aligned with spacers that are formed along the sidewall of the gate caps. Additionally, the active devices may have a two-step gate oxide. A lower portion may have a thickness that is larger than the thickness of an upper portion of the gate oxide. The two-step gate oxide combined with the self-aligned source contacts allow for the production of devices with a pitch in the deep sub-micron level. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is related to commonly-assigned, co-pending application Ser. No. 13/724,228, filed the same day as the present application and entitled “HIGH DENSITY TRENCH-BASED POWER MOSFETS WITH SELF-ALIGNED ACTIVE CONTACTS AND METHOD OF MAKING SUCH DEVICES” to Lee, Chang, Kim, Lui, Yilmaz, Bobde, Calafut, and Chen, the entire disclosures of which are incorporated herein by reference.

This application is related to commonly-assigned, co-pending application Ser. No. 13/724,093, filed the same day as the present application and entitled “HIGH FREQUENCY SWITCHING MOSFETS WITH A LOW OUTPUT CAPACITANCE USING A DEPLETABLE P-SHIELD” to Bobde, Yilmaz, Lui, and Ng, the entire disclosures of which are incorporated herein by reference.

FIELD OF THE INVENTION

This invention generally relates to metal oxide silicon field effect transistors (MOSFETs) and more particularly to high density trench based power MOSFETS.

BACKGROUND OF THE INVENTION

Low voltage power MOSFETs are often used in load switching applications. In load switching applications it is desirable to reduce the on-resistance (Rds) of the device. Specifically, the RdsAof the device needs to be minimized, where RdsAis the on-resistance of the device multiplied by the active area of the device. Additionally, low voltage power MOSFETs are commonly used in high frequency DC-DC applications. In such applications it is often desirable to maximize the device's switching speed. Three of the most important parameters for optimizing the switching speed are: 1) Rds×Qg; 2) Rds×QOSS; and 3) the ratio of Qgd/Qgs. First, the product of the Rdsand the gate charge (Qg) is a measure of the device conduction and switching losses together. Qgis the sum of the gate to drain charge (Qgd) and the gate to source charge (Qgs). In the second parameter, QOSSis a measure of the capacitances that need to be charged and discharged whenever the device is switched on or off. Finally, minimizing the ratio of Qgd/Qgsreduces the possibility of the device turning on due to a large dV/dt when the device is being switched off.

Trench based MOSFETs, as shown inFIG. 1A, were designed in part in order to reduce RdsAof the device. The design of trench based MOSFETs allowed for the removal of the JFET structure that was present in planar MOSFETs. By eliminating the JFET, the cell pitch could be reduced. However, the basic trench based MOSFET does not have any charge balancing in the drift regions, and therefore causes an increase in the RdsA. Also, the relatively thin gate oxide generates a high electric field under the trench, which leads to a lower breakdown voltage. Low doping concentrations are needed in the drift region in order to support the voltage, and this increases the RdsAfor structures with thinner gate oxides. Further, as cell pitch continues to decrease, the trench based MOSFET may become a less desirable choice because of the difficulty in reducing the thickness of the gate oxide further.

Previous attempts have been made to solve these problems through various designs. A first example is a shielded gate MOSFET as shown inFIG. 1Band described in U.S. Pat. No. 5,998,833 to Baliga. The use of a trench-based shield electrode connected to source potential instead of a larger gate electrode reduces the gate-to-drain capacitance (Cgd) of the MOSFET and improves switching speed by reducing the amount of gate charging and discharging needed during high frequency operation. However, the MOSFET device described by Baliga exhibits a high output capacitance because the source potential is capacitively coupled to the drain via the shield electrode. Also, in order to sustain the blocking voltage a thick oxide is required. Finally, complex processing is required in order to produce two electrically separated polysilicon electrodes within the same trench. The complexity of the fabrication is further accentuated when the pitch of the device is scaled downwards to the deep sub-micron level.

Finally, the MOSFET design shown inFIG. 1Cand described in U.S. Pat. No. 4,941,026 to Temple, has certain characteristics that may be utilized to optimize the switching characteristics of a device. The device in Temple utilizes a two-step gate oxide with a thin layer of oxide near the top of the gate and a thicker layer of oxide in the bottom portion of the gate in order to create a device that has a low channel resistance and a low drift resistance. The thin upper portion of the gate oxide provides good coupling between the gate and body region which generates a strong inversion and low on-resistance in a channel next to the thin upper portion. The thicker gate oxide on the bottom creates a charge balancing effect and allows for the drift region to have an increased doping concentration. A higher doping concentration in the drift region decreases its resistance.

However, the device shown inFIG. 1Cis not easily downwards scalable because it is highly susceptible to body contact misalignment errors. For example, if the pitch of the devices was scaled to the deep sub-micron level e.g., 0.5-0.6 μm, then the contact mask misalignment, relative to the gate, may greatly alter the characteristics of the device. In order to provide a good ohmic contact to the body region, an ohmic contact that is highly doped with dopants of the same conductivity type as the body region may be implanted after the contact mask has been used. If the contact mask is aligned too close to the gate, namely not landing exactly at the center of the silicon mesa, then highly doped implants used to generate an ohmic contact with the body may end up in the channel. If the highly doped ohmic region is in the channel, then the threshold voltage and the on-resistance of the device will be impacted. Also, if the contact mask is aligned too far away from the gate, then the turn on of the bipolar junction transistor (BJT) becomes an issue. Since the contact is further from the trench, the length of the body region is increased and therefore so is its resistance. As the resistance of the body region increases, it increases the voltage drop across the body region. The larger voltage drop across the body region will make it easier for the parasitic BJT to turn on and ruin the device.

Therefore, in order to fabricate deep sub-micron devices that are optimized for use as load switches and high frequency DC-DC applications there is a need for a device and method capable of self-aligning the contacts to the gate in order to prevent the aforementioned side effects.

It is within this context that embodiments of the present invention arise.

DESCRIPTION OF THE SPECIFIC EMBODIMENTS

Although the following detailed description contains many specific details for the purposes of illustration, anyone of ordinary skill in the art will appreciate that many variations and alterations to the following details are within the scope of the invention. Accordingly, the exemplary embodiments of the invention described below are set forth without any loss of generality to, and without imposing limitations upon, the claimed invention. In the following discussion, an N-type device is described for purposes of illustration. P-type devices may be fabricated using a similar process but with opposite conductivity types.

Aspects of the present disclosure describe a high density trench-based power MOSFET with self-aligned source and body contacts. The source/body contacts may be self-aligned with conductive or semiconductor (e.g., doped polysilicon) spacers. The spacers may be formed along the sidewall of the gate caps. Additionally, the active devices may have a two-step gate oxide, wherein a lower portion of the gate oxide has a thickness T2that is larger than the thickness T1of an upper portion of the gate oxide. The two-step gate oxide combined with the self-aligned source/body contacts allow for a highly scalable device that is capable of being produced with an active device pitch in the deep sub-micron level, e.g., 0.5-0.6 microns.

Additional aspects of the present disclosure describe a similar device that does not have a source region formed in the silicon epi part of the device. According to this aspect of the present disclosure, the semiconductor spacers, e.g., N+-doped polysilicon spacers, may also serve as the source region, and therefore the addition of a source region within the substrate may be omitted. Additional aspects of the present disclosure describe a similar device where the source region formed in the silicon epi part of the device is formed by diffusing dopants from the doped polysilicon spacers into the silicon epi part of the device.

Additional aspects of the present disclosure describe a high density trench-based power MOSFET with self-aligned source contacts that is adapted for high switching speeds. In addition to the self-aligned source contacts and two-step gate oxide, the fast switching MOSFET further comprises a lightly doped P-region below the body region. The lightly doped P-region reduces the coupling between the gate and the drain of the device.

The two step gate oxide allows for a significant portion of the voltage to be supported by a lower portion of the gate oxide374. This reduces the amount of voltage that the epitaxial layer307must support.FIG. 2Ais a cross sectional view of an active device that displays the strength of the electric field, where darker shading indicates a higher electric field strength. As shown by the heavy shading along the bottom portion of the trench, the lower portion of the gate oxide374supports a large portion of the electric field.FIG. 2Bis a graph depicting voltage that has been blocked by device300versus the depth into the substrate. Device300begins blocking voltage at a depth of approximately 0.5 microns. This depth is consistent with the depth at which the lower portion of the gate oxide374with a thickness T2begins. Near the bottom of the trench and the oxide374(about 1.0 microns) the device has blocked a total of approximately 18 volts. This greatly reduces the voltage blocking burden of the epitaxial layer307. Therefore, the doping concentration of epitaxial drift layer307may be increased in order to reduce the RdsAof device. The increase in the doping concentration of the epitaxial layer307along with lower channel resistance due to smaller cell pitch allows for an approximately 90% or more decrease in the RdsAwhen compared to the prior art trench based MOSFET designed to support the same voltage described inFIG. 1A, or an approximately 37% or more decrease in the RdsAwhen compared to the prior art split gate MOSFET designed to support the same voltage described inFIG. 1B.

The RdsAof the device is further decreased because of the location of the accumulation region391. As shown inFIG. 2C, when the gate is turned on a narrow accumulation region391is formed in the upper portion of the epitaxial layer307adjacent to the trench sidewall. By way of example, the accumulation region391may be approximately 300-400 Å wide. This concentration of charge carriers along the accumulation region reduces the resistance over the upper portion of the epitaxial layer307. Further, since the accumulation region391is thin, reducing the cell pitch does not affect the resistance as long as the pitch is greater than the width of the accumulation region391. This feature is not present in a split gate MOSFET device of the type described above with respect toFIG. 1B. In that type of device, the lower portion of the trench is kept at the source potential, which prevents an accumulation region391from forming along a narrow path proximate to the sidewall. Therefore, it is not practical to shrink the pitch of the split gate MOSFET to the deep sub-micron level.

FIG. 3Ais a cross sectional view of a device structure300according to aspects of the present disclosure. The device structure300may be built on a semiconductor substrate301. The substrate301may be suitably doped to be an N-type or a P-type substrate. As used herein, the substrate301will be described as an N-type substrate. The semiconductor substrate301may comprise a heavily doped N+drain region302and an epitaxial layer307. By way of example, the drain region302may have a doping concentration of approximately 1019cm−3or greater. The epitaxial layer307may be grown above the drain region302and may be lightly doped with N-type dopants. By way of example, the epitaxial layer107may have a doping concentration that is approximately between 1015cm−3and 1017cm−3. A suitably doped P-body layer303may be formed in a top portion of the epitaxial layer307. An N+-doped source region304may be formed in a top portion of the body layer303.

According to aspects of the present disclosure, the active area of the device structure300may comprise a plurality of trench based power MOSFETs. The trench based power MOSFETs are formed by creating a trench370that extends through the P-body region303and into the epitaxial layer307. Each trench may have an upper portion371and a lower portion372. The upper portion of the trench371may be lined with an upper insulative layer373that has a thickness T1, and the lower portion of the trench372may be lined with a lower insulative layer374that has a thickness T2. According to aspects of the present disclosure, it is desirable that the thickness T1be smaller than the thickness T2. By way of example, the upper and lower insulative layers may be an oxide. The remainder of the trench may be filled with a suitable material to form a gate electrode309. By way of example, the gate electrode309may be formed with polysilicon. Though not shown inFIG. 3A, gate electrodes309are connected to a gate pad and are maintained at a gate potential. Each gate electrodes309is electrically isolated from a source material317by an insulative gate cap308which is disposed above the trench. An insulative layer355may also be formed above the source region304. The possibility of short circuiting the gate electrode309to the source material317may be reduced by forming an insulative spacer341along the vertical edges of the gate caps308. By way of example, the insulative spacer341may be an oxide.

The source regions304are electrically connected to the source material317through self-aligned contact openings389in the substrate that extend through the insulating layer355and the source region304. The openings389are self-aligned by the N+-doped polysilicon spacers342formed along the exposed sidewall of the insulative spacers341. These spacers function as a mask layer for an etching process used to form the contact openings389. The N+-doped polysilicon spacers342reduce the contact resistance by increasing the area of contact to the source and allow for the formation of an ohmic contact. By way of example and not by way of limitation, the electrical connections may be made with conductive plugs357. By way of example and not by way of limitation, the conductive plugs357may be made from a conductive material such as tungsten. An ohmic contact between the conductive plugs357and the P-body layer303may be improved by the addition of an ohmic contact region343. The ohmic contact region343is a highly doped P-region that is formed on the exposed surface of the self-aligned contact openings389. By way of example, the ohmic contact region343may by formed by implanting P-type dopants such as boron with a doping concentration of approximately 1×1019cm−3.

The self-aligned contact openings389may be formed sufficiently close to each other such that the active devices in the MOSFET device have a pitch P of less than 1.0 microns. More specifically, aspects of the present disclosure allow for the devices to have a pitch P of less than 0.6 microns. This pitch is made possible in because the self-alignment of the contact openings389eliminates alignment errors even when the devices are scaled to have a pitch below 1.0 micron. This ensures that threshold voltage of the device is maintained, because the dopants from the ohmic contact region343remain outside of the channel. Additionally, the self-alignment of the contact openings389allows for precise control of the parasitic BJT turn on because the distance between the trench sidewall and the conductive plug will be substantially constant across the device. Consistent spacing makes the resistance of the body region and the voltage drop across the body region substantially constant across the device as well. Therefore, there will be little variation in the conditions that will cause the parasitic BJT to turn on for each active device.

According to another additional aspect of the present disclosure, a device structure300′ may also be configured for fast switching applications such as DC-DC applications.FIG. 3Bdepicts a structure300′ that is substantially similar to device300inFIG. 3A, but with the addition of a sub-body layer388. The sub-body layer388is a lightly doped P-layer formed below the P-body layer303and electrically connected to the source metal. The dopant concentration of the sub-body layer388should be low enough to allow for an inversion channel to be formed proximate to the lower insulative layer374. The doping range for the lightly doped sub-body layer388may be from about 1×1014cm−3to about 1×1016cm−3Adding the sub-body layer388to device300′ reduces the coupling between the gate electrode and the drain electrode, and therefore provides significant decreases in the values of Qg, Qgd, and QOSS. Further the Rds-onof the device is only slightly increased. As described above these variables are included in the key figures of merit for determining the switching speed of a device. By maximizing Qg, Qgd, and QOSSwith only a slight increase in Rds-on, the switching speed of device300′ may be greatly improved. The sub-body layer388may extend to a depth below the top portion of the trench371. As the depth of the sub-body layer388increases the improvements in the switching speed increase as well. However, the increase in depth also increases the Rds-on.

FIG. 3Cdepicts a device300″ according to an additional aspect of the present disclosure that omits the source region304from the top portion of the semiconductor substrate301. Other than the removal of source region304, device300″ is substantially similar to that of device300described inFIG. 3A. The source region304may be omitted because the N+-doped polysilicon spacer342may also serve as the source region due to its high concentration of N-type dopants. The utilization of the N+-doped polysilicon spacers342as the source region allows for the reduction of a source implantation step during processing, and significantly suppress the parasitic bipolar action.

Device300may optionally include an electrostatic discharge (ESD) protection structure395as shown inFIG. 3D. The ESD protection structure395may be a conductive material396formed over a first layer356of a two layer hardmask. The conductive material396may be selectively doped to include N-type and P-type regions. An insulative layer397may be formed over a top surface of the conductive material396.

Device300may also optionally include one or more gate pickup trenches370′ as shown inFIG. 3D. The gate pickup trench370′ is substantially similar to the active device trenches370. However, instead of an electrically insulated gate electrode309, the gate pickup electrode322is electrically connected to a gate metal324with an electrical connection320that extends through the gate cap308. By way of example, and not by way of limitation, the electrical connection320may be tungsten. The gate pickup trench may be formed in a deep doped region361that is doped with opposite-type dopants to the substrate301. By way of example, and not by way of limitation, if the substrate301is N-type, the deep doped region361would be doped P-type, in which case it is sometimes referred to as a “P-Tub”. Alternatively, if the substrate301us P-type, the deep doped region361would be doped N-type, in which case it is sometimes referred to as an “N-Tub”.FIG. 3Edepicts a device300that may also optionally include one or more Schottky contacts configured to terminate the electric field. The Schottky contacts in combination with the P-tub361may also function as a body clamp (BCL) configured to prevent the active devices from operating above their breakdown voltages. As shown inFIG. 3E, a metal contact321may electrically connect a Schottky metal325to the semiconductor substrate301. By way of example, the contact321may extend through a hardmask having a first layer356and a second layer355. By way of example, and not by way of limitation, the first layer may be a nitride layer and the second layer may be an oxide layer. By way of example, and not by way of limitation, the metal contacts321may be tungsten. The Schottky metal325may be deposited over the metal contacts321and the first layer of the hardmask356and is isolated from the gate metal324. Additionally, the gate pickup metal324and the Schottky contact325are electrically isolated from each other.

FIG. 4is a diagram of the layout for a device structure300. The layout shows the gate electrodes309alternating with source contacts357in a device region. The source contacts357extend perpendicular to the plane of the drawing to make electrical contact with the source metal317. Gate runners319electrically connect to the gate electrodes309to gate pickups322. The gate electrodes, gate runners and gate pickups may be made from the same material, e.g., polysilicon, which may be formed in corresponding trenches in a common step. Gate contacts320extend perpendicular to the plane of the drawing to make electrical contact with the gate metal324(not shown). The gate metal324may be initially formed as part of the same metal layer as the source metal317. The gate metal324may be electrically isolated from the source metal317and/or Schottky metal325, e.g., by forming a common metal layer followed by subsequent masking, etching and dielectric fill processes, as are commonly done for this purpose.

The BCL regions may be placed outside the active device region, which can be seen from the locations of Schottky contacts325inFIG. 4. Additionally, ESD structures395may be formed outside of the active device region. The ESD structures395may be formed over an insulator layer356. Although the ESD structures395are shown as being formed outside the active region, they may also be located outside the gate pickup area.

Aspects of the present disclosure describe methods for fabricating the devices descried inFIG. 3A-3E. Methods of fabrication are described in conjunction withFIGS. 5A-5Jwhich depict cross sectional views of a device structure500at different stages of fabrication.

FIG. 5Adepicts a semiconductor region501. The region501may be suitably doped to be an N-type or a P-type substrate. For purposes of illustration, the semiconductor region501used herein will be an N-type substrate. The semiconductor region501may comprise a heavily doped drain contact502with a lightly doped epitaxial region507grown above the drain contact region502. A heavily doped P-tub561may be formed in the epitaxial layer507. The P-tub may be formed by ion implantation or any other suitable method. By way of example, and not by way of limitation, a P-tub mask may be used with a masked implantation of P-type dopants.

A hard mask having a first insulating layer556and a second insulating layer555may be formed on a top surface of the semiconductor substrate501. The second insulating layer555may be resistant to a first etching process that etches the first insulating layer556, and the first insulating layer556may be resistant to a second etching process that etches the second insulating layer555. By way of example, and not by way of limitation, the first insulating layer556may be a nitride layer and the second insulating layer may be an oxide. By way of example, the first insulating layer556may be between 0.2 microns (μm) and 0.5 μm thick, and the second insulating layer555may be between 50 angstroms (Å) and 250 Å thick.

InFIG. 5Ba trench mask may be utilized to define the locations of the trenches570by etching through the first and second insulative layers of the hardmask556,555. Additionally, the gate pickup trenches570′ may also be defined in the same processing step. Next, inFIG. 5Ca partial trench etch is utilized to form the upper portion571of the trenches570and570′. The upper portion of the trench571may be approximately half of the total depth of the trench570. By way of example, and not by way of limitation, the depth of the upper portion of the trench D1may be approximately 0.5 μm deep. Each trench570may be spaced apart from other trenches by a mesa with a width WM. By way of example the width WMmay be between 0.2 μm and 0.5 μm. By way of example, the width of each trench WTmay be between 0.2 μm and 0.5 μm.

InFIG. 5Dthe upper portion of the trenches571are lined with a thin pad oxide575and an insulative spacer546. The pad oxide575and the insulative spacer546prevent the upper portion of the trench571from growing an oxide during the processing of the lower portion of the trench572. The insulative spacer546also functions as an additional mask layer in order to reduce the width of the lower portion of the trench572. By way of example, the insulative spacer546may be a nitride. After the insulative spacer546has been formed, the lower portion of the trench572may be formed by an etching process. By way of example, and not by way of limitation, the depth of the second portion of the trench D2may be an additional 0.5 μm, resulting in a total depth DTof the trenches570,570′ being approximately 1.0 μm.

Next, inFIG. 5Ea lower insulative layer574may be formed. By way of example, but not by way of limitation, the lower insulative layer574may be an oxide grown through thermal oxidation. Typically, the thickness T2may range from 400 Å-1500 Å. InFIG. 5Fthe pad oxide575and the insulative spacers546are removed first. Then, the upper insulative layer573, which is a gate oxide, may be grown. The thickness T1may range from 50 Å-500 Å. While the ranges for the thicknesses for T1and T2slightly overlap, it is desirable for the thickness T2of the lower insulative portion574to be larger than the thickness T1of the upper insulative layer573. After the upper insulative layer573is grown, the trenches570and570′ may be filled with a conductive material in order to form the gate electrode509in the active devices and the gate pickup electrode522in the gate pickup trench570′. In order to minimize the possibility of forming voids within the electrodes509and522the trenches should have an aspect ratio of width to depth no greater than approximately 1:6. By way of example, and not by way of limitation, the conductive material used to form the electrodes509and522may be a polysilicon doped with N-type dopants. Once the trenches570and570′ are filled, the conductive material may be etched down in order to be substantially planar with the top surface of the semiconductor substrate501.

InFIG. 5G, the insulative gate caps508are formed. The insulative gate caps may be formed with a deposited oxide, such as but not limited, to borophosphosilicate glass (BPSG) or tetraethylorthosilicate (TEOS). After the insulative gate caps508have been deposited, they may be planarized with the top surface of the first layer of the hardmask556. By way of example, the planarization may be done with chemical mechanical planarization (CMP). By way of example, and not by way of limitation, the thickness of the gate caps508may be approximately 300 Å. Gate caps508are self-aligned due to the presence of the first and second layers of the hardmask556and555that were originally etched to form the trench masks. Without the need for an additional mask aligning step, the alignment of the gate caps508may be improved. Further, the self-alignment of gate caps508provides the foundation for the self-aligning source contacts. Therefore, it is critical that the gate caps508be properly aligned.

After the caps508have been formed, device500may have the first layer of the hardmask556removed in the active area with a masking and a first etching process. The first etching process may selectively remove the first layer of the hardmask556with little effect on the second layer of the hardmask555. By way of example, if the first hardmask layer556is a nitride and the second hardmask layer555is an oxide, then a hot-phosphoric acid wet dip may preferentially remove the nitride while leaving the oxide. Once the first hardmask layer556has been removed, the P-body503may be implanted into a top portion of the semiconductor substrate501. The N+-source region504may also be implanted after the first layer of the hardmask556has been removed. Next, an insulative spacer541may be formed along the sidewalls of the gate caps508in order to prevent a short circuit between the gate electrodes509and the source metal517. The insulative spacers541may be formed by depositing an insulation layer on the exposed surfaces of the device and then etching the insulation layer away with an anisotropic etch. The anisotropic etch will leave a portion of the insulative layer along the sidewalls of the gate caps508that will function as the insulative spacer541After the oxidization, a polysilicon layer may be disposed along the top surface of the second layer of the hardmask555, over the exposed surfaces of the insulative spacer541, and over the top surface of the gate caps508. The polysilicon layer may be doped with a high concentration of N-type dopants. An anisotropic etch may then be used to remove the polysilicon layer, leaving behind only polysilicon spacers542spaced away from the sidewalls of the gate caps508by the insulative spacer541. By way of example and not by way of limitation, the anisotropic etch process may be a reactive ion etching (RIE). The anisotropic etch process may also etch through the second layer of the hardmask555. Additionally, the polysilicon spacers542may be used to form the source regions504with a diffusion process instead of the implantation step as described above. The source regions504may be formed by diffusing N-type dopants from the polysilicon spacer542into the top portion of the epitaxial layer507below the spacers542.

With the top surface of the epitaxial layer507exposed, another anisotropic etching process may be used to etch through the epitaxial layer in order to expose the P-body region503with the self-aligned contact openings547. The polysilicon spacers542protect the source region504underneath and therefore provide source regions504with a consistent size across the device500. In order to provide better ohmic contact with the source metal517, a high concentration of P-type dopants may be implanted into the surface of the self-aligned contact openings547in order to form ohmic contacts543. By way of example, a boron surface implant may be used to form the ohmic contacts543.

According to additional aspects of the present disclosure, the device500may also have an ESD structured595. FIG.5H′ shows that the structure595may be formed before the first hardmask layer556is removed from the active region. By way of example, the ESD structure may be formed by first depositing an un-doped polysilicon layer over the top surface of the device500. A first ESD mask may then be used to selectively dope, with N-type dopants, the regions of the polysilicon that will become the ESD diode596. The P-type portions of the ESD diode596may be implanted during the P-body implant. A second ESD mask may then be used to selectively remove the polysilicon layer in order to form the ESD diode596. An insulative layer597may be grown over the ESD diode596to protect it from subsequent processing. Thereafter, device500may be processed according to the process described byFIG. 5H.

FIG. 6Adescribes the processing of a device600′ that is configured for fast switching speeds. The processing of device600′ is substantially similar to that of device500but with an additional step for forming a sub-body layer688. The sub-body layer688may be formed by implanting a lightly doped P-region below the bottom surface of the body layer603. This implantation may occur before or after the P-body layer603and/or the source regions604are implanted. Thereafter, the processing may continue according to the same processing as device500.

FIG. 6Bdescribes the processing of a device600″. Device600″ is processed substantially the same as device500, with the exception that there is no source region implanted into the semiconductor substrate601. The device may still function because the polysilicon spacer642is doped with N-type dopants and may serve as the source region. Thereafter, the processing may continue according to the same processing as device500.

Returning to device500, the processing continues with standard contact formation procedures. InFIG. 5Ia photoresist layer516is deposited over the top surface of the device. A gate contact mask may be used to provide an opening through the gate cap over the gate pickup electrode522. Additionally, the gate contact mask may provide an opening that allows for the first and second hardmask layers556,555to be etched through in a non-active area of the device to form a Schottky contact520. InFIG. 5Jthe photoresist layer is removed and the device500is prepared for metallization. Source contacts507may be formed in the self-aligned contact openings547. By way of example, and not by way of limitation, the source contacts may be tungsten. Contacts520may also be made to connect the gate pickup electrode to a gate metal524and to connect the Schottky metal525to the substrate501. By way of example, the contacts520may be made of tungsten. Finally a metal layer may be deposited over the top surface of the device. The metal layer may then be etched to form a source metal517, a gate pickup metal524and a Schottky metal525connected to the source metal517with the use of a metal mask.

Aspects of the present disclosure also describe an additional process for forming a two-step trench oxide layer. First inFIG. 7Aan etching process is used to form trenches770,770′ in the substrate701through a hard mask having a first insulating layer756and a second insulating layer755formed on a top surface of the semiconductor substrate701. Substrate701may comprise a heavily doped N+drain region702and an epitaxial layer707. Trenches770and trenches770′ are substantially similar. Trenches770may be used for active MOSFET structures, and be located in an active region of the device700. Trenches770′ may be used for gate pickup structures and may be located in non-active regions of the device. As shown, trench770′ is formed in a P-tub761. The trenches770,770′ are formed to a depth DTand width WT. By way of example, the depth DTmay be approximately 1.0 micron and the width of the trench WTmay be between approximately 0.2 μm and 0.5 μm. The trenches may be spaced apart from each other by a mesa that has a width WMranging from approximately 0.2 μm-0.5 μm.

After the trenches770,770′ have been made, an insulation layer774may be formed along the walls and the bottom surface of the trench, as shown inFIG. 7B. The insulation layer774may have a thickness T2. By way of example, and not by way of limitation, the thickness T2may be between 400 Å and 1500 Å. Next the trenches770,770′ may be filled with a first portion of the conductive material7091. The conductive material7091may be etched back down such that it only fills the lower portion of the trench772.

InFIG. 7Cthe insulation layer774in the upper portion of the trench771may be etched away. The insulation layer774in the lower portion of the trench772will be protected from the etching process by the first portion of the conductive material7091. Then the upper insulation layer773may be grown on the walls of the upper portion of the trench771. The upper insulation layer773may have a thickness T1. By way of example, and not by way of limitation, the thickness T1may be between approximately 50 Å and 500 Å. Further, it should be noted that even though the approximate ranges of the thicknesses T1and T2overlap, it is desirable that T2should remain larger than T1. During the growth of the upper insulation layer773, an insulation layer773′ may also form over the top surface of the first portion of the conductive material7091. A layer of insulation between portions of the conductive material709would cause the gate electrode to have a bottom portion that was not at the gate potential. However, simply etching away the unwanted insulation layer773′ may damage the upper insulation layer773.

Therefore, inFIG. 7Da second portion of conductive material7092may be used to fill the trench770. An anisotropic etching process may then be used to partially remove the second portion of the conductive material7092leaving only sidewall spacers that protect the upper insulation layer773from subsequent etching processes. Next, the unwanted insulation layer773′ may be removed with a suitable etching process. Once removed, the remainder of the trench770may be filled with a third portion of the conductive material7093. Thereafter, the processing may continue according to the same processing as device500.