Hearing assistance system and method

A system for providing hearing assistance having: an audio signal source; a transmission unit transmitting audio signals as data packets in a frame structure; a receiver unit for receiving audio signals from the transmission unit and associated with an ear-worn device having a power source and a hearing stimulator, and having a digital transceiver powered by the power source of the ear-worn device with a value between lower and upper limits. The transceiver listens, and optionally transmits, during part of each frame and otherwise sleeps. The receiver unit has a capacitor connected in parallel to the transceiver for supplying the transceiver with current during listening or transmission. A controlled current for controlling current flowing from the power source to the transceiver and the capacitor. The controlled current source has a DC/DC converter with an input connected to the power source and an output voltage connected to the capacitor.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a system and a method for providing hearing assistance to at least one user, wherein audio signals from an audio signal source, such as a microphone for capturing a speaker's voice, are transmitted via a wireless link to a receiver unit acting as an audio receiver for an ear-worn device, such as a hearing aid.

2. Description of Related Art

Presently, in such systems, the wireless audio link usually is an FM (frequency modulation) radio link. According to a typical application of such wireless audio systems, the receiver unit is connected to or integrated into a hearing instrument, such as a hearing aid, with the transmitted audio signals being mixed with audio signals captured by the microphone of the hearing instrument prior to being reproduced by the output transducer of the hearing instrument. The benefit of such systems is that the microphone of the hearing instrument can be supplemented or replaced by a remote microphone which produces audio signals which are transmitted wirelessly to the FM receiver, and thus, to the hearing instrument. In particular, FM systems have been standard equipment for children with hearing loss in educational settings for many years. Their merit lies in the fact that a microphone placed a few centimeters from the mouth of a person speaking receives speech at a much higher level than one placed several feet away. This increase in speech level corresponds to an increase in signal-to-noise ratio (SNR) due to the direct wireless connection to the listener's amplification system. The resulting improvements of signal level and SNR in the listener's ear are recognized as the primary benefits of FM radio systems, as hearing-impaired individuals are at a significant disadvantage when processing signals with a poor acoustical SNR.

A typical application of such wireless audio systems is at school, wherein the teacher uses a wireless microphone for transmitting the captured audio signals via the transmission unit to receiver units worn by the students. Since the receiver units and the respective hearing aids are usually owned by the students, the receiver units may be of different types within a class.

Another typical application of wireless audio systems is the case in which the transmission unit is designed as an assistive listening device. In this case, the transmission unit may include a wireless microphone for capturing ambient sound, in particular from a speaker close to the user, and/or a gateway to an external audio device, such as a mobile phone; here the transmission unit usually only serves to supply wireless audio signals to the receiver unit(s) worn by the user.

Examples of analog wireless FM systems particularly suited for school applications are described, for example, in European Patent Application EP 1 863 320 A1 and International Patent Application Publication WO 2008/138365 A1. According to these systems, the wireless link not only serves to transmit audio signals captured by the wireless microphone, but in addition, also serves to transmit control data obtained from analyzing the audio signals in the transmission unit to the receiver unit(s), with such control data being used in the receiver unit to adjust, for example, the gain applied to the received audio signals according to the prevailing ambient noise and the issue of whether the speaker is presently speaking or not.

In applications where the receiver unit is part of or connected to a hearing aid, transmission is usually carried out by using analog FM technology in the 200 MHz frequency band. In recent systems the analog FM transmission technology is replaced by employing digital modulation techniques for audio signal transmission. An example of such a digital system is available from the company Comfort Audio AB, 30105 Halmstad, Sweden under the trademark COMFORT DIGISYSTEM®.

A specific example of an analog wireless FM system particularly suited for school applications is described in International Patent Application Publication WO 2008/074350 A1, wherein the system consists of a plurality of transmission units comprising a microphone and a plurality of analog FM receiver units and wherein only one of the transmission units has an analog audio signal transmitter, while each of the transmission units is provided with a digital transceiver in order to realize an assistive digital link for enabling communication between the transmission units. The assistive digital link also serves to transmit audio signals captured by a transmission unit not having the analog transmitter to the transmission unit having the analog transmitter from where the audio signals are transmitted via the analog FM link to the receiver units.

U.S. Pat. No. 7,778,432 B2 relates to a wireless network for communication of binaural hearing aids with other devices, such as a mobile phone, using slow frequency hopping, wherein each data packet is transmitted in a separate slot of a TDMA frame, with each slot being associated to a different transmission frequency, wherein the hopping sequence is calculated using the ID of the master device, the slot number and the frame number. A link management package (LMP) is sent from the master device to the slave devices in the first slot of each frame. The system may be operated in a broadcast mode. Each receiver is turned on only during the transmission during time slots associated to the respective receiver. The system has two acquisition modes for synchronization, with two different handshake protocols. Eight LMP messages are transmitted in every frame during initial acquisition, and one LMP message is transmitted in every frame once a network is established. Handshake, i.e., bi-directional message exchange, is needed both for initial acquisition and acquisition into the established network. During acquisition, only a reduced number of acquisition channels is used, with the frequency hopping scheme being applied to these acquisition channels. The system operates in the 2.4 GHz ISM band. A similar system is known from U.S. Pat. No. 8,229,146 B2.

International Patent Application Publication WO 2008/135975 A2 relates to a communication network, wherein the receiver wakes up for listening to the preamble of a data packet and goes to sleep again, if no valid preamble is received.

U.S. Patent Application Publication 2007/0086601 A1 relates to a system comprising a transmission unit with a microphone for transmitting a speaker's voice to a plurality of hearing aids via a wireless digital link, which may be unidirectional or bi-directional and which may be used for transmitting both audio data and control data to the hearing aids.

U.S. Pat. No. 7,529,565 B2 relates to a hearing aid comprising a transceiver for communication with an external device, wherein a wireless communication protocol including a transmission protocol, link protocol, extended protocol, data protocol and audio protocol is used. The transmission protocol is adapted to control transceiver operations to provide half duplex communications over a single channel, and the link protocol is adapted to implement a packet transmission process to account for frame collisions on the channel.

European Patent Application EP 1 560 383 A2 relates to a Bluetooth system, wherein the slave device, in a park mode or in a sniff mode, periodically wakes up to listen to transmission from the master and to re-synchronize its clock offset.

U.S. Patent Application Publication 2007/0259629 A1 relates to the transmission of audio signals from a main device, such as a mobile phone, to a peripheral device, such as a headset, in order to establish a wireless personal area network by using an ultra-wide band link, wherein very short pulses of 1 ns or less duration, corresponding to transmission band width of about 500 MHz, are transmitted. In order to reduce power consumption, the transceivers are operated in an interpulse duty cycling mode. In order to better match the peak current consumption from the battery during powered-on times of the interpulse duty cycling to the average current drawn from the battery, a capacitive element is charged when pulses are not being transmitted or received and is then discharged to power the transceiver when pulses are being transmitted or received. It is also mentioned that such system may be used with devices like a microphone and a hearing aid.

In U.S. Pat. No. 5,083,095, which relates to a hearing aid having a microphone preamplifier using a junction field effect transistors (JFET), in order to enhance power supply rejection, it is mentioned that, due to the internal impedance of the power source, in connection with the relatively low power supply voltage, the power output stage may contribute a signal which, due to the high current drawn through the power supply impedance, is equal to or greater than the wanted signal. It is also mentioned that such ripple signals may be reduced by placing a capacitor across the power leads or by placing a large resistor between the power lead and the stage to be isolated, with a capacitor across the normal leads of that stage. It is also mentioned that the drawback of such solutions employing a RC-filter is the relatively large capacitor required therefore.

U.S. Patent Application Publication 2008/0232623 A1 relates to a hearing aid which is recharged via the direct audio input by a battery included in a wireless communication device attached to the hearing aid via the direct audio input, with the transceiver of the communication device likewise being powered by that battery.

U.S. Pat. No. 6,737,838 B2 relates to a DC/DC up/down converter, wherein first a supply voltage is converted to a lower voltage through a step-down DC/DC converter (buck converter) and then, during specific phases of work also the higher voltage is generated from the lower voltage using the same coil in a step-up converter (boost converter) architecture.

Conventional radio receiver units (“boots”) for hearing aids typically use FM-modulation in the VHF frequency band (169 to 220 MHz) and are connected to the hearing aid through a 3-pin plug-in interface having an audio signal pin, a power pin and a common ground pin, wherein the radio receiver boot is powered by the hearing aid battery. The hearing aid typically is provided with a so-called audio shoe, provided by the hearing aid manufacturer, for connection to the standard 3-pin interface. Typically, the batteries of the hearing aid provide for a supply voltage between 1 and 1.5 V, wherein a typical current consumption of, for example, a BTE hearing aid is between 1 and 2 mA. A digital transceiver operating in the 2.4 GHz band typically needs a supply voltage of 1.5 to 3 V and requires a typical current of 25 mA.

SUMMARY OF THE INVENTION

It is an object of the invention to provide for a hearing assistance system employing a digital audio link, wherein the receiver unit is powered by the battery of an ear-worn device comprising the stimulation means and wherein noise signals due to current ripples should be avoided. It is also an object of the invention to provide for a corresponding hearing assistance method.

According to the invention, these objects are achieved by a hearing assistance system and a hearing assistance method as described herein.

The invention is beneficial in that, by providing the receiver unit with a capacitor connected in parallel to the transceiver for supplying the transceiver during listening or transmission operation with current and for being recharged by the power supply of the ear-worn device, when the transceiver is sleeping and with a controlled current source for controlling the current flowing from the power source to the transceiver and the capacitor in a manner so as to prevent changes in that current which are expected to add an audible noise signal to the audio signals supplied to the stimulation means, the transceiver can be operated in a duty cycling mode for reducing power consumption, while nevertheless noise signals, which otherwise would be caused by the fast changes in the current consumed by the transceiver when switching between the sleeping state and the active listening/transmission state and vice-versa, can be prevented. By using a capacitor to provide for the necessary current peaks in the current consumed by the transceiver, the controlled current source is able to keep the current supplied by the power source close to the average current consumed by the transceiver.

Preferably, the controlled current source is adapted to adjust the current flowing from the power source to the transceiver and the capacitor to a constant target current value selected according to the estimated quality of the audio link (or according to the estimated average current consumption of the transceiver). The current flowing from the power source to the transceiver may be kept within −0% to +20% at the target value. In case of a change of the estimated quality of the audio link, the current may be adjusted to a new target current value corresponding to the changed quality of the audio link with a time constant of at least 0.05 sec. The target current value preferably is selected as the estimated average current to be consumed by the transceiver plus a safety overhead to account for transient changes in link quality. The link quality may be estimated from an output signal of the transceiver indicative of the packet level error rate and/or the bit level error rate of the received audio signals.

Preferably, the controlled current source is adapted to monitor the voltage across the transceiver in a manner so as to keep it below a given threshold. To this end, dummy discharge of the capacitor may be caused. According to one example, the receiver unit may comprise a shunt circuit connected in parallel to the capacitor. The shunt circuit may comprise a load resistance, which is periodically switched on by the controlled current source. It can also be a circuit operating in an independent manner, as to prevent the voltage across the transceiver to go over a maximum value and/or to prevent the voltage across the current source to fall below a minimum value. Alternatively or addition, the transceiver may be forced to carry out dummy listening operation.

These and further objects, features and advantages of the present invention will become apparent from the following description when taken in connection with the accompanying drawings which, for purposes of illustration only, show several embodiments in accordance with the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to a system for providing hearing assistance to at least one user, wherein audio signals are transmitted, using a transmission unit comprising a digital transmitter, which transmits from an audio signal source via a wireless digital audio link to at least one receiver unit, from which the audio signals are supplied to means for stimulating the hearing of the user, typically a loudspeaker.

As shown inFIG. 1, the device used on the transmission side may be a wireless microphone used by a speaker in a room for an audience; an audio transmitter having an integrated or a cable-connected microphone as are used by teachers in a classroom for hearing-impaired pupils/students; an acoustic alarm system, like a door bell, a fire alarm or a baby monitor; an audio or video player; a television device; a telephone device; a gateway to audio sources like a mobile phone, music player; etc. The transmission devices include body-worn devices as well as fixed devices. The devices on the receiver side include ear-worn devices, such as all kinds of hearing aids and ear pieces. The receiver devices may be for hearing-impaired persons or for normal-hearing persons.

The system may include a plurality of devices on the transmission side and a plurality of devices on the receiver side, for implementing a network architecture, usually in a master-slave topology.

The transmission unit typically comprises or is connected to a microphone for capturing audio signals, which is typically worn by a user, with the voice of the user being transmitted via the wireless audio link to the receiver unit.

The receiver unit is connected to or integrated within an ear-worn device. Typically, receiver unit is connected to a hearing aid via an audio shoe or is integrated within a hearing aid.

Usually, in addition to the audio signals, control data is transmitted bi-directionally between the transmission unit and the receiver unit. Such control data may include, for example, volume control or a query regarding the status of the receiver unit or of the device connected to the receiver unit (for example, battery state and parameter settings).

InFIG. 2, a typical use case is shown schematically, wherein a body-worn transmission unit10comprising a microphone17is used by a teacher11in a classroom for transmitting audio signals corresponding to the teacher's voice via a digital link12to a plurality of receiver units14, which are integrated within or connected to hearing aids16worn by hearing-impaired pupils/students13. The digital link12is also used to exchange control data between the transmission unit10and the receiver units14. Typically, the transmission unit10is used in a broadcast mode, i.e., the same signals are sent to all receiver units14.

Another typical use case is shown inFIG. 3, wherein a transmission unit10having an integrated microphone is used by a hearing-impaired person13wearing receiver units14connected to or integrated within a hearing aid16for capturing the voice of a person11speaking to the person13. The captured audio signals are transmitted via the digital link12to the receiver units14.

A modification of the use case ofFIG. 3is shown inFIG. 4, wherein the transmission unit10is used as a relay for relaying audio signals received from a remote transmission unit110to the receiver units14of the hearing-impaired person13. The remote transmission unit110is worn by a speaker11and comprises a microphone for capturing the voice of the speaker11, thereby acting as a companion microphone.

The transmission units10,110may comprise an audio input for a connection to an audio device, such as a mobile phone, a FM radio, a music player, a telephone or a TV device, as an external audio signal source.

In each of such use cases, the transmission unit10usually comprises an audio signal processing unit (not shown inFIGS. 2 to 5) for processing the audio signals captured by the microphone prior to being transmitted.

A schematic block diagram of an example of a hearing assistance system according to the invention is shown inFIG. 5. The system comprises a transmission unit10and at least one digital receiver unit14.

The transmission unit10comprises a microphone arrangement17for capturing a speaker's voice, which may be integrated within the housing of the transmission unit10or which may be connected to it via a cable. The transmission unit10also may include an audio signal input19which serves to connect an external audio signal source20, such as a mobile phone, an FM radio, a music player, a telephone or a TV device, to the transmission unit10.

The audio signals captured by the microphone arrangement17and/or the audio signals optionally received from the external audio signal source20are supplied to a digital signal processor (DSP)22which is controlled by a microcontroller24and which acts as an audio signal processing unit which applies, for example, a gain model to the captured audio signals.

In addition, the DSP22may serve to analyze the captured audio signals and to generate control data (control commands) according to the result of the analysis of the captured audio signals. The processed audio signals and the control data/commands are supplied to a digital transmitter28, which is likewise controlled by the microcontroller24.

The digital transmitter28transmits the modulated signals via an antenna36to an antenna38of the digital receiver unit14, thereby establishing a digital link12.

Both the digital transmitter28and the digital receiver unit14are designed as transceivers, so that the digital transceiver28can also receive control data and commands sent from the digital receiver unit14.

The transceiver28also may be used for receiving audio signals from an external audio source25, such as a remote microphone used as a companion microphone, via a wireless digital audio link27, with the received audio signals being supplied to the DSP22for retransmission by the transceiver28. Hence, in this case, the transmission unit10serves to relay audio signals from the external audio source to the receiver unit14(see examples ofFIGS. 4 and 11). Alternatively, the transmission unit10may include a separate receiver (not shown in theFIGS. 6 and 7) for receiving the audio signals from the external audio source; in this case the link27would be independent from the link12and thus also could be analog.

The microcontroller24is responsible for management of all transmitter components and may implement the wireless communication protocol, in particular for the digital link12.

The digital receiver unit14comprises or is connected to a loudspeaker42or another means for stimulating a user's hearing. Typically, the receiver unit14is an ear-worn device which is integrated into or connected to a hearing aid comprising the speaker42. The control data transmitted in parallel to the audio signals may serve to control operation of the receiver unit14according to the presently prevailing auditory scene as detected by the DSP22from the audio signal captured by the microphone arrangement17.

InFIG. 6, an example of the audio signal path in the transmission unit10is shown in more detail.

The microphone arrangement17of the transmission unit10comprises two spaced apart microphones17A and17B for capturing audio signals which are supplied to an acoustic beam-former unit44which generates an output signal supplied to a gain model unit46. The output of the beam-former unit44is also supplied to a voice activity detector (VAD) unit48which serves to detect whether the speaker is presently speaking or not and which generates a corresponding status output signal. The output of at least one of the microphones17A,17B is also supplied to an ambient noise estimation unit50which serves to estimate the ambient noise level and which generates a corresponding output signal. The output signals of the units48and50and the processed audio signals from the gain model46are supplied to a unit56which serves to generate a corresponding digital signal comprising the audio signals and the control data which is supplied to the digital transceiver28. The external audio signals optionally received via the audio input19and/or the transceiver28may be supplied to the gain model46.

The units44,46,48,50and56may be functionally realized by the DSP22(see dashed line surrounding these units inFIG. 6).

A more detailed example of the digital receiver unit14is shown inFIG. 7, according to which the antenna38is connected to a digital receiver61including a demodulator58and a buffer59(actually, the element61is designed as a transceiver).

The signals transmitted via the digital link12are received by the antenna38and are demodulated in the digital radio receiver61. The demodulated signals are supplied via the buffer59to a DSP74acting as processing unit which separates the signals into the audio signals and the control data and which is provided for advanced processing, e.g., equalization, of the audio signals according to the information provided by the control data. The processed audio signals, after digital-to-analog conversion, are supplied to a variable gain amplifier62which serves to amplify the audio signals by applying a gain controlled by the control data received via the digital link12. The amplified audio signals are supplied to a hearing aid64. Alternatively, the variable gain amplifier may be realized in the digital domain by using a PWM modulator taking over the role of the D/A-converter and the power amplifier. The receiver unit14also includes a memory76for the DSP74.

Rather than supplying the audio signals amplified by the variable gain amplifier62to the audio input of a hearing aid64, the receiver unit14may include a power amplifier78which may be controlled by a manual volume control80and which supplies power amplified audio signals to a loudspeaker82which may be an ear-worn element integrated within or connected to the receiver unit14. Volume control also could be obtained remotely from the transmission unit10by transmitting corresponding control commands to the receiver unit14.

In general, the role of the microcontroller24could also be taken over by the DSP22. Also, signal transmission could be limited to a pure audio signal, without adding control and command data.

Details of the protocol of the digital link12will be described by reference toFIGS. 8, 9 and 10. Typical carrier frequencies for the digital link12are 865 MHz, 915 MHz and 2.45 GHz, wherein the latter band is preferred. Examples of the digital modulation scheme are Phase-shift keying (PSK)/Frequency-shift keying (FSK), Amplitude-Shift Keying (ASK) or combined amplitude and phase modulations such as Quadrature Phase Shift Keying (QPSK), and variations thereof (for example, Gaussian Frequency-Shift Keying (GFSK)).

Preferably, data transmission occurs in the form of TDMA (Time Division Multiple Access) frames comprising a plurality (for example, 10) of time slots, wherein one data packet may be transmitted in each slot. InFIG. 8, an example is shown wherein the TDMA frame has a length of 4 ms and is divided into 10 time slots of 400 μs, with each data packet having a length of 160 μs.

A slow frequency hopping scheme is used, wherein each slot is transmitted at a different frequency according to a frequency hopping sequence calculated by a given algorithm in the same manner by the transmitter unit10and the receiver units14, wherein the frequency sequence is a pseudo-random sequence depending on the number of the present TDMA frame (sequence number), the ID of the network master device (usually one of the transmission units10) and the frequency of the last slot of the previous frame.

The first slot of each TDMA frame (beacon=slot0inFIG. 8) is allocated to the periodic transmission of a beacon packet which contains the sequence number numbering, the TDMA frame and other data necessary for synchronizing the network, such as information relevant for the audio stream, such as description of the encoding format, description of the audio content, gain parameter, surrounding noise level, etc., information relevant for multi-talker network operation, and optionally, control data for all or a specific one of the receiver units.

The second slot (slot1inFIG. 8) may be allocated to the reception of response data from slave devices (usually the receiver units) of the network, whereby the slave devices can respond to requests from the master device through the beacon packet. At least some of the other slots are allocated to the transmission of audio data packets, wherein each audio data packet is repeated at least once, typically in subsequent slots. In the example shown inFIG. 9slots3,4and5are used for three-fold transmission of a single audio data packet. The master device does not expect any acknowledgement from the slaves devices (receiver units), i.e., repetition of the audio data packets is done in any case, irrespective of whether the receiver unit has correctly received the first audio data packet (which, in the example ofFIG. 9, is transmitted in slot3) or not. Also, the receiver units are not individually addressed by sending a device ID, i.e., the same signals are sent to all receiver units (broadcast mode).

Rather than allocating separate slots to the beacon packet and the response of the slaves, the beacon packet and the response data may be multiplexed on the same slot, for example, slot0.

The audio data maybe compressed in the transmission unit10prior to being transmitted.

Each audio data packet comprises a start frame delimiter (SFD), audio data and a frame check sequence, such as CRC (Cyclic Redundancy Check) bits (seeFIG. 10).

In order to save power, the receiver61in the receiver unit14is operated in a duty cycling mode, wherein each receiver wakes up shortly before the expected arrival of an audio packet. If the receiver is able to verify (by using the CRC at the end of the data packet) that the data packet has been received correctly, then the receiver goes to sleep until shortly before the expected arrival of a new audio data packet (the receiver sleeps during the repetitions of the same audio data packet), which, in the example ofFIG. 9, would be the first audio data packet in the next frame. If the receiver determines, by using the CRC, that the audio data packet has not been correctly received, the receiver switches to the next frequency in the hopping sequence and waits for the repetition of the same audio data packet (in the example ofFIG. 9, the receiver then would listen to slot4as shown inFIG. 9, wherein in the third frame transmission of the packet in slot3fails).

In order to further reduce power consumption of the receiver, the receiver goes to sleep already shortly after the expected end of the SFD, if the receiver determines, from the missing SFD, that the packet is missing or has been lost; seeFIG. 10. The receiver then will wake up again shortly before the expected arrival of the next audio data packet (i.e., the copy/repetition of the missing packet).

FIG. 9shows a typical behavior of a receiver unit14. In the first frame, the transceiver61correctly receives the first transmission, so that only one current pulse is taken from the power supply during the 1stframe. At the beginning of the second frame, the transceiver61switches ON for receiving also the beacon (as already mentioned above, the beacon is a service data packet that is transmitted in the first slot of each frame for synchronisation of different receivers). The receiver unit does not need to receive each beacon, it needs only to receive it from time to time (typically 1 beacon every 25thframe). The reception of a beacon adds one current pulse every xth(here: every 25th) frame. In the example ofFIG. 9, the first transmission is received correctly. In total, 2 current pulses are consumed during this 2ndframe. In the 3rdframe, the transceiver61switches ON for receiving the first packet but it receives it with errors (first current pulse). Then, it switches ON again for receiving the second transmission and receives it correctly (2ndcurrent pulse in the same frame, i.e., total 2 current pulses in the 3rdframe). In the 4thframe, transceiver61switches ON for receiving the first packet; the packet is correctly received (i.e., only one current pulse is consumed during the 4thframe). If the transmission path is good, the normal working regime is to receive one packet per frame, i.e., only one current pulse is taken during each frame.

An example of duty cycling operation of the receiver is shown inFIG. 10, wherein the duration of each data packet is 160 μs and wherein the guard time (i.e., the time period by which the receiver wakes up earlier than the expected arrival time of the audio packet) is 20 μs and the timeout period (i.e., the time period for which the receiver waits after the expected end of transmission of the SFD and CRC, respectively) likewise is 20 μs. It can be seen fromFIG. 10that, by sending the receiver to sleep already after timeout of SFD-transmission (when no SFD has been received), the power consumption can be reduced to about half of the value when the receiver is sent to sleep after timeout of CRC transmission.

Typically, a radio receiver boot is connected to the hearing instrument by a 3-pin interface comprising a pin assigned to the analog audio input of the hearing instrument for external audio signals, a pin assigned to the positive contact of the hearing instrument battery and a pin assigned to the negative contact of the hearing instrument battery, wherein the negative contact of the hearing instrument battery also serves as the ground return path for the audio signal, so that in fact the power line and the audio signal line share a common ground line.

Serial parasitic resistances between the two devices occur due to the contacts between the hearing instrument and its audio shoe on one side and through contacts between the audio shoe and the radio receiver unit on the other side. The contact resistance in serial with the ground connection causes a problem, since this line is the ground line for the analog audio signal, and at the same time, also carries the supply current pulses. If, for example, the ground contact resistance is assumed to be 100 mΩ, a current pulse of 25 mA produces a voltage pulse in serial with the ground line which amounts to 2.5 mV. This level is close to that of the audio signals delivered by the receiver unit to the hearing instrument, which is typically from 1 to 10 mV. Assuming that the transceiver is switched on and off at least once in each 4 milliseconds TDMA frame for listening to one audio data packet, a 250 Hz signal of 2.5 mV amplitude would be produced by the switching of the transceiver.

A similar, although less severe, problem occurs also if the receiver unit is integrated within the hearing instrument rather being connected to it by a 3-pin connector. The reason is that in this case a noise signal might be generated in the earphone of the hearing aid by the transceiver current changes due to the internal resistance of the hearing instrument battery.

InFIGS. 11 to 19, examples are shown of how such noise signals due to transceiver current ripples can be avoided.

InFIG. 11, a schematic block diagram of a receiver unit14connected to hearing aid16is shown, wherein a controlled current source88is connected in series between the battery90of the hearing aid16and the digital transceiver61of the receiver unit14, with a capacitor91being connected in parallel to the transceiver61. The capacitor91is provided for supplying the transceiver61during listening or transmission operation with current and for being recharged by the hearing aid battery90when the transceiver61is sleeping (typically, the transceiver61listens only during less than 10% of each frame).FIG. 12shows an embodiment of system ofFIG. 11, where the current source88is placed after a voltage multiplier93in the receiver unit14. The controlled current source88includes a control unit92for controlling the current I2flowing from the battery90to the transceiver61and the capacitor91in a manner so as to prevent changes in the current I2caused by the transceiver61switching between sleeping and listening/transmission operation and vice versa, respectively, which are expected to add an audible nose signal to the audio signals supplied to the hearing aid16for being reproduced by the stimulation means/loudspeaker42of the hearing aid16.

The controlled current source88preferably adjusts the current I2to a constant target current value selected according to the estimated quality of the digital audio link12(usually, the quality of the digital audio link12is a measure for the expected average current consumption of the transceiver61, since a low link quality requires the transceiver to listen more frequently to repetitions of packets). The target current value corresponds to the estimated average current to be consumed by the transceiver61plus a safety factor of −0% . . . +20% to account for transient, i.e., short-term, changes in link quality. The excess current is derived to GND by the shunt circuit70, which prevents the radio supply voltage VRADIOfrom exceeding a maximum value. Preferably, the controlled current source88and the capacitor91are designed to keep the current (I2) flowing from the power source90to the transceiver61within ±0.1% at the target value.

As illustrated in the top and bottom diagrams ofFIG. 13, degrading link quality causes a higher average current I1consumed by the transceiver61, since, when the link quality is reduced, the likelihood that the transceiver61has to listen to the first or second repetition of a certain audio data packet is higher. If the link quality degrades during a short time period (for example, caused by interference from other systems on specific frequencies), the current I2can be kept constant, as the current overhead is sufficient to inflate again the voltage VRADIOover the capacitor once the interference has ceased. However, if the link quality degrades so much that the transceiver61has to listen almost in every frame to the second transmission of each audio data packet, the average current will double with regard to a good link quality which does not require reception of repetitions of the audio data packet. Correspondingly, also the current drawn from the hearing aid battery90has to be doubled. However, if such current increase would occur very fast, such current increase may cause voltage ripples in the audible frequency range, which might be perceived by the user of the hearing aid16. Therefore, the control unit92adjusts the current I2to be supplied by the current source88with a time constant of at least 0.05 seconds. This example is illustrated inFIG. 13, wherein the current I2is increased relatively slowly from the lower value corresponding to good link quality to the second value corresponding to bad link quality. Then, if the link quality improves again, the system has to listen to less packets and the radio supply voltage VRADIOrises again. The loading current can be reduced again by the controller, but this time a relatively long time constant of typically 0.5 to 1 second can be used. Due to such relatively long time constant, some current may be “wasted” for a while if the link quality remains constant, but, on the other hand, the current must not be increased again if the link degrades again soon.

However, if there is a sudden and severe degradation of link quality that forces reception of 2-3 transmission at each frame for a long time, the system may enter an emergency procedure, raising the current faster, i.e., with a shorter time constant than 0.05 s, although this may cause audible ripples. In such case, the audio output of the receiver unit may be interrupted during the time of current increase, and it may be connected again once the current is stable again. Such emergency situations may be avoided, to some extent, by using the above-mentioned relatively long current release time constants of 0.5-1 seconds. Preferably, the control unit92estimates the link quality from an output signal of the transceiver61, which is indicative of the packet level error rate, i.e., how frequently the transceiver61has to listen to packet repetitions, and/or the bit level error rate of the received audio signals.

Since the current I2includes a certain safety overhead and since the control unit92is informed by the transceiver61regarding the link quality in real time, the control unit92will be able to adjust the target value of the current I2early enough and with a sufficiently long time constant in a manner that the charging state of the capacitor91is always sufficient for supplying the transceiver61with the required current, while avoiding the need for fast changes of the current I2.

The control unit92monitors the supply voltage VRADIOof the transceiver61in a manner so as to keep VRADIOin a safe range. In order to generate a sufficiently high supply voltage for the radio, the voltage of the hearing aid battery90is increased sufficiently by a voltage multiplier93provided in the receiver unit14. The voltage multiplier93provides for an output voltage VM. The maximum allowable value of VRADIOis given by the output voltage VMof the voltage multiplier93minus the minimum voltage VSATacross the current source88required for proper operation (if the current source88is realized, for example, by a MOS transistor operating in moderate inversion, the minimum value VSATwould be between about 100 and 200 mV). The lower limit of the allowable range of VRADIOis given by the minimum voltage at the transceiver61necessary for operating correctly.

In order to prevent VRADIOfrom exceeding the allowed maximum value, the shunt regulator70may cause dummy discharge of the capacitor91. This may be realized by the shunt regulator70alone that monitors the voltage VRADIOand automatically derivates the excess of current delivered by the current source88to GND, thus maintaining VRADIObelow a maximum value. This may also be realized, for example, by a load resistor connected in parallel to the capacitor91, which is periodically switched on by the control unit92to provide for the necessary discharge of the capacitor91. Alternatively or in addition the control unit92may force the transceiver61to periodically carry out dummy listening operation in order to provide for a necessary (additional) discharge of the capacitor91.

The middle diagram ofFIG. 13illustrates an example of the control of the transceiver supply voltage

If there are small disturbances during a short time, more than one reception of packets in a frame is needed and the transceiver supply voltage VRADIOdecreases a bit but it stays above a safety margin. Once the disturbance has ceased, the voltage can rise again up to its maximum value using the current overhead, and it is not necessary to change the value of the current source I2. If the disturbance is more severe, the system will first wait until VRADIOfalls below a first security threshold and/or count for the number of receptions required by the transceiver. If the degradation is confirmed, the system will start raising the value of I2with a slow time constant in the order of 0.05-0.1 s, as already mentioned above. During this reaction time, VRADIOcan still decrease.

If the supply voltage falls below a saftey threshold value (VRADIO≦VRADIO_MIN) then the system, as already mentioned above, will react fast in an emergency procedure, which may cause the current ripple to become audible (the system may at this time temporarily break the audio path, and connect it again once the current I2is stable again). The release time of current typically is longer than the attack time, in the order of 0.5-1 s. If the link becomes good again, the excess current will be derived to GND by the shunt regulator during this time.

In the example ofFIG. 12, the receiver unit14is connected to the hearing aid16via an audio interface89, usually an audio shoe, comprising a pin89C connected to the positive electrode of the hearing aid battery90, a pin89A connected to the negative electrode of the hearing aid battery90, and a pin89B connected to the external audio input of the hearing aid16, wherein the pin89A also serves as a ground pin for the audio signal input. The hearing aid16includes, as shown inFIG. 12, a speaker (earphone)42, a microphone arrangement94and a signal processor72for processing the audio signals captured by the microphone arrangement94and the audio signals supplied by the receiver unit14via the audio input.

In the example ofFIG. 12, the voltage multiplier93and the current source88are separate blocks. A drawback is the voltage drop that is needed for proper operation of the current source VM−VRADIO≧VSAT=100 . . . 200 mV

According to an example of the invention, this drawback can be overcome by combining both voltage multiplier93and current source88into a single block, for example by realizing the voltage multiplier in a special form of a boost DC/DC converter using a coil and working in discontinuous mode.

In this regard, a step-up DC/DC converter is needed that delivers an output voltage having a value set between a lower and an upper limit. The DC/DC converter should have the characteristic of a current source at its input, so that a change in output voltage over the capacitor91will not produce a change in the current consumed by the DC/DC converter from the battery90.

The DC/DC converter may be realized as a “bridged boost converter” using 4 switches. The sequence of operation of the switches, as illustrated inFIG. 15, insures a constant current flowing out of the battery90. According toFIG. 14the bridged boost converter95is connected in serial with the battery90and the digital transceiver61, with a capacitor91being connected in parallel to the transceiver61. The capacitor91is provided for supplying the transceiver61during listening or transmission operation with current and for being recharged by the battery90when the transceiver61is sleeping, as discussed already in connection withFIG. 12. Usually, the capacitor91is connected in parallel to the transceiver61through specific contact pads91A and91B.

The control block97provides appropriate voltage levels for switching ON or OFF the MOS M1, M2, M3and M4at the right time; for achieving this task, the control block97monitors the battery voltage VBATthe output voltage VRADIOand the voltage level at contact96B (Voltage at node B).

The converter95operates over a defined number of working cycles per second. The current I2that is delivered to the radio61and the capacitor91as well as the current IBATtaken from the battery are proportional to the number of cycles. The number of working cycles per second that is needed for proper operation is defined by the control block97as a function of the output voltage VRADIOand of the battery voltage VBAT.

InFIG. 15, the different phases of a working cycle are illustrated. Before the cycle starts, all switches M1, M2, M3and M4are open and the current through the coil96equals zero.Phase 1: At start (time t=0) switches M2and M3are closed and M1and M4remain open. In this way, the current flowing through the coil96(L) increases linearly with time.Phase 2: At time t=T1, switches M2and M3open. This will not stop the current flowing through the coil96, as a coil opposes naturally to current variations; the coil will drive the voltage at node A below that of GND node and will also drive the voltage at node B over the voltage of output node (Node VH=VRADIO). Diodes D1and D4become then conductive and the current flows now through the coil96, the diodes D1and D4, the reference node GND and the output node91A through the capacitor91; this current charges the output capacitor91.Phase 3: At time T2, switches M1and M4close, providing a short circuit of diodes D1and D4. This improves the transfer of the energy that was stored into the coil96during the phase 1 to the capacitor91, as there exists no longer the voltage drop over the diodes D1and D4. The time duration of precedent phase 2, T2−T1=ΔTOVLis called “non overlap time”. It is needed for insuring that switch M2opens before switch M1closes and also that switch M3opens before switch M4closes; this prevents the direct conduction path through M1-M2or M3-M4, respectively. For saving energy, the “non overlap time” T2-T1has to be kept as low as possible. During time interval T3-T2, the current flowing through the coil96decreases, charging the output capacitor91.Phase 4: At time T3, the control block97opens again the switch M4. Time T3is chosen by the control block97as a point in time before the current through the coil96reverses sense. The control block monitors the voltages at nodes96B (Node B) and91A (Node VH) for deciding the right moment to switch M4OFF. During phase 4, the residual current through the coil96continues flowing through the reference node GND, the switch M1and the diode D4to the output node91A, delivering its residual energy to the output capacitor91. At time T4, the current through the coil reaches zero. The diode D4ceases conduction and the voltage at node B goes back to GND level.Phase 5: At time T4′>T4the control block97opens the switch M1again. Until end of this phase (guard time), all switches are open and the current through the coil is zero. At time T5, the converter is ready for starting a new working phase.

The converter95operates in discontinuous mode, wherein at the beginning and at the end of each cycle the current through the coil96is zero.

The time duration until T1is the “charging time”, during which the coil96stores energy. This time period is made independent of the value of output voltage at node91A (VRADIO) by the control block97. In this way, the average current ĪBATthat is consumed by the converter95on the battery is made independent of the value of output voltage VRADIO.

The control block97will adjust the number of working cycles per second for maintaining the output voltage VRADIObetween the two voltage thresholds VRADIO_MIN≦VRADIO≦VRADIO_MAXwith slow time constants. In this way, the average current consumed from the battery will also vary with a slow time constant, preventing the current changes through the battery from being audible.

In a practical example, a working period of the converter95uses 5 periods of a clock generated by a quartz oscillator at a 26 MHz frequency. The duration of the charging time T1(phase 1) is 3 periods of the quartz frequency (115 ns), the non-overlap time T2-T1(phase 2) is preferably less than 2 ns, the time duration of phase 3 is typically one period of the quartz frequency (38.5 ns), and duration of phases 4 and 5 together is also one period of the quartz frequency or less. The coil has value L=4.7 μH, the battery voltage is between VBAT=1.0V . . . 1.5V and the output voltage is between 1.8V≦VRADIO≦2.4V. The average current taken by the radio is Ī1=0.9 mA . . . 2 mA

FIG. 19shows an example of current profile through the coil96during one working cycle for various combinations of the battery voltage and the output voltage. It can be seen that during the phase 1 of the cycle the current does not depend on the output voltage. As already mentioned, the control block97will adjust the number of working periods per second (duty-cycle of operation) as to maintain the output voltage between two defined limits VRADIO_MIN≦VRADIO≦VRADIO_MAX. This duty-cycle (DC) is to be changed in small step increments. For example, the maximum size of increment in battery current for making the change inaudible should be ΔI1=≦5 μA. Also, the fundamental frequency of duty-cycle should be above the audio frequency range, the upper limit of which is about 16 kHz. These are contradictory requirements.

For achieving small current increments without adding noise at audible frequencies the control of duty-cycle may be implemented through a fractional N-divider realized with a multi-modulus divider driven by a Δ/Σ modulator (such method is used in PLL frequency synthesizers for producing arbitrary small frequency step increments in short settling times).

A block diagram of such an implementation of the control block97is shown inFIG. 18. The control block97comprises a gate driver98, a multi-modulus divider99, a Δ/Σ modulator100, a control unit101and a frequency divider102.

The gate driver98generates the control voltages for MOS transistors M1, M2, M3, M4and M51-M52at proper levels; it has as inputs the clock signals CK1. . . CKN, a command signal “WP-Start” and the voltages at nodes96B (internal node B of converter95) and91A (VRADIO). The input signal “WP-Start” initiates the start for a working cycle of the gate driver98. The frequency divider102generates clocks (CK2. . . CKN) at various frequencies, lower than the clock signal CK1of XTAL oscillator103; these clocks are used by all other units98,99,100and101of the control block97.

The multi-modulus divider99delivers the start signal for the gate driver98. The start signal “WP-Start” is generated from clock signals CK1. . . CKN, by frequency division by an integer number K: fWP_START=fCK1/K. The number K is variable in time. It is limited between the values KMIN≦K≦KMAXthat are the minimum and maximum division factor of the multi-modulus divider99.

The Δ/Σ modulator100determines the division factor K of the multi-modulus divider99, and it varies the division number in order to get the average value of K over time equal to the fractional number N:K=N. The fractional number N is delivered to the Δ/Σ modulator100by the control unit101that adjusts N in order to get the voltage at node91A in the allowable range: VRADIO_MIN≦VRADIO≦VRADIO_MAX. The duty-cycle of the converter95is proportional to the frequency of the signal “WP-Start” (fWP_START), which is inversely proportional to the fractional division number N. Thus, the input and the output currents of converter are both inversely proportional to N.

The control block97needs a clock frequency that is independent of the battery voltage and the output voltages. In the present example, this clock frequency (CK1) is delivered by a quartz oscillator103connected to a quartz XTAL104. The output frequency fCK1=fXTALof XTAL oscillator103drives the gate driver98, the frequency divider102, the multi-modulus divider99and the Δ/Σ modulator100.

In a typical application, assuming a coil inductance L=4.7 μH, a battery voltage VBAT=1.25V, an output voltage is VRADIO=2.0V, an average current taken by the radio of Ī1=1.0 mA, an efficiency of the boost converter95of η=85% and a gate driver operating over 5 cycles of the XTAL clock frequency fCK1=fXTAL=26 MHz (with the duration of phase 1 being 3 periods of clock CK1, the duration of phase 3 being one period of CK1and the duration of phases 4 and 5 together being 1 period of CK1), the working duty-cycle of the converter95needs to be only DC=21.1%. The average division number is then

According to an alternative embodiment of the invention, the supply of digital circuits and of analog/RF circuits of the receiver unit14is combined within a single block.

The receiver unit14has digital and analog/RF circuits. The analog/RF circuits need a higher supply voltage than the battery (VRADIO>VBAT) but the digital circuits may be supplied at a lower voltage for saving power. With state of the art technologies, the digital circuits may operate at VDIG=0.7 . . . 1.2V. Another reason for reducing the digital supply voltage would be the fact that the dynamic power consumption of digital circuits is proportional to the square of its supply voltage.

For simplification, one could supply the digital circuits directly from the battery voltage. However, an issue would be again the current ripple produced on the battery at audio frequencies by the duty-cycled current consumption of the digital block, because the digital block works in synchronisms with the radio.

This problem may be overcome by supplying the digital circuits at a lower voltage VDIGproduced from the filtered voltage VRADIOthrough a step-down DC/DC converter (buck converter) using a coil. As described above, the step-up DC/DC converter95ofFIG. 14used to generate the supply voltage VRADIOof the transceiver61works in a burst mode with a duty-cycle lower than 1. The coil96of the boost converter may be used by the buck converter for generating VDIGduring the periods when the coil96is not used by the boost converter.

InFIG. 16a schematic of an example of such a supply system for the receiver unit14is shown, wherein a digital block106is supplied from the voltage converter195(acting as a boost/buck DC/DC converter), with a capacitor105being connected in parallel to the digital block106. The capacitor105is provided for filtering the current ripple produced by the operation of the digital block106. Usually, the capacitor105is connected in parallel to the digital block106through specific contact pads91B and91C.

The control block97provides appropriate voltage levels for switching ON or OFF the MOS transistors M1, M2, M3, M4, M51and M52at the right time; for achieving this task, the control block97monitors the battery voltage VBAT, the output voltage VRADIO, the voltage level at contact96B (Node B) and the output voltage VDIG.

Operation of the boost converter already has been described with regard toFIG. 15. Operation of the buck converter which supplies the digital block106will be described with regard toFIGS. 16 and 17. The current I3that is delivered to the digital block106and the capacitor105is proportional to the number of cycles. The number of working cycles per second that is needed for proper operation is defined by the control block97in function of the output voltage VDIGover capacitor105. InFIG. 17, the different phases of a working cycle of the buck converter are shown. The buck converter uses the coil96and the switches M3, M4, M51and M52during the time when these elements are not used for the operation of the boost converter.

Before start of a buck converter cycle, all switches M1, M2, M3, M4, M51and M52are open and the current through the coil96is zero.Phase 1: At start (time t=0) the switches M4, M51and M52(M51and M52are shown as a single element “5” inFIG. 17) are closed and M3remains open. In this way, the current flowing through the coil96increases linearly with time, flowing from the higher voltage VRADIO(=VH) through the switch M4, the coil96, the switches M51and M52, the capacitor105and the capacitor91. This current charges also the output capacitor105.Phase 2: At time t=T1, the switch M4opens. This will not stop the current flowing through the coil96, as a coil naturally opposes to current variations; the coil will drive the voltage at node B below that of GND node. Diode D3becomes conductive and the current continues flowing through the switches M51and M52, the coil96, the diode D3, the reference node GND and the capacitor105; this current charges also the output capacitor105.Phase 3: At time T2, the switch M3closes, providing a short circuit of diode D3. This improves the transfer of the energy that was stored into the coil96during the phase 1 to the capacitor105as there is no more voltage drop over the diode D3. The time duration of precedent phase 2, T2−T1=ΔTOVLis called “non overlap time”. This time is needed for insuring that switch M4opens before switch M3closes; this prevents a direct conduction path through M3-M4. For saving energy, the “non overlap time” T2-T1has to be kept as low as possible. During the time interval T3-T2, the current flowing through the coil96decreases, while charging the output capacitor105.Phase 4: At time T3, the control block97opens again the switch M3. Time T3is chosen by the control block97as a point in time before the current through the coil96reverses sense. The control block97monitors the voltages at node96B for deciding the right moment to switch M3OFF. The residual current through the coil96continues flowing through the reference node GND, the diode D3, the switches M51and M52and the capacitor105, delivering its residual energy to the output capacitor105. At time T4, the current through the coil reaches 0 value. The diode D3ceases conduction and the voltage at node B goes to the VDIGvoltage level.Phase 5: At time T4′>T4the control block97opens the switches M51and M52again. Until end of this phase (guard time), all switches are open and the current through the coil is zero. At time T5, the converter is ready for starting a new working phase, either in boost converter or in buck converter operation.

The control block97will adjust the number of working cycles per second for maintaining the output voltage VDIGof node91C at a fixed value. In contrary to the boost converter, it can do that with a short time constant. Smooth time constants are not needed as the buck converter takes its energy from the boost converter node91A that is already filtered.

It is noted that, although not shown inFIGS. 14 and 16for the sake of clarity, the shunt regulator96ofFIG. 12preferably is maintained for safety reasons

A modification of the embodiment ofFIGS. 16 & 18is shown inFIGS. 20 & 21. According to a first aspect, a (transistor) switch M6and a resistor RDAMPhave been added for connecting node B to ground. The switch M6is driven by a reset signal output by the gate driver98of the control block97. The purpose of this circuit is to damp remaining high frequency ringing current through the coil96(and high frequency ringing voltage on node B) before connecting the coil96in parallel to the battery for the next step-up operation.

In practice, parasitic capacitances on nodes A and B build a resonant circuit with the coil96at a much higher frequency than the operating frequency of DC/DC-converter195. At end of either the boost or the buck pulses (phases 4 and 5 inFIGS. 15 & 17), the current through the coil96reaches zero, but the voltage across the coil96is not zero; this initiates a new current through the coil96, and then, oscillation occurs through the serial resonant circuit formed by the parasitic capacitance on node B and the coil96. Connecting resistor RDAMPin parallel between node B and GND allows absorbing the remaining oscillating energy (oscillation damping) before the start of next “boost” pulse.

According to a second aspect, a programmable current source111is added, which delivers a constant DC current to the digital block106and the respective capacitor105(i.e., to the pad91C). This current source is supplied directly from the power source voltage VBAT. The purpose of this additional current source111is to reduce the current consumed on the power source90, as can be seen from the following considerations.

The DC/DC converter195generates two different supply voltages using a single coil96: VRADIO(typically≈2V) which is generated from VBAT(typically 1.0V to 1.4V) in the “boost” (step-up) mode and VDIG(typically 1.0V) which is generated from VRADIOin the “buck” (step-down) mode. Both voltage conversions have limited energy efficiency: that of the step-up process has been measured as η(boost)=(VRADIO*I2)/(VBAT*IBAT)=0.76, and that of step-down process as η(buck)=0.85. But seen from the power source90(all energy comes from the power source90), the efficiency of the step-up-down converter is:
η(boost−buck)=(VDIG*I3)/(VBAT*IBAT)=0.76*0.85≈0.65
only. This means that every microwatt delivered to the digital block106through VDIGconsumes 1/0.65=1.55 μW on the power source. Thus, while, with this solution, the pulsed currents taken by the digital block106do not influence the power source90, the efficiency of this supply scheme is low.

If, however, the current taken by the digital block106is delivered by the additional current source111, the energy efficiency is better. As an example, with VBAT=1.2V and VDIG=1.0V, the efficiency is:
η(current−source 111)=(VDIG*I3)/(VBAT*IBAT)=VDIG/VBAT≈0.83
(because in this case I3=I4=IBAT). However, it has to be taken into account that the current source111operates correctly (i.e., prevents the voltage ripple present on VDIGfrom reaching VBAT) only if the voltage difference is sufficient, i.e., VBAT>=VDIG+0.1V. Accordingly, the power source voltage is monitored by the system: as long the power source voltage is sufficient, the current source111stays ON; if VBATdrops below VDIG+0.1V, the current source is switched OFF, and all the current to the digital block106is delivered by the DC/DC converter195.

Supplying the whole current to the digital block106from the constant current source111is not feasible, because the average current I(VDIG) is variable over time, and VDIGhas to be fixed at, e.g., 1.0V. For this reason, only a part of the current to the digital block106out of VDIGis delivered by the current source111(e.g., 85%). The remaining current (e.g., 15%) is delivered by the DC/DC converter195that provides regulation of the VDIGvoltage at proper level.

A modification of the example ofFIG. 20is shown inFIG. 22, which is particularly suitable for more advanced technologies wherein the radio transceiver61consumes less current and can be supplied at lower voltage. Also, the digital block106would consume less current and use a lower voltage supply. The power source90may remain a zinc-air battery typically used in hearing aids and having an operating voltage VBAT=1.25V nominal (end-of-lifetime at 1.0V). With new technologies, the supply voltage of the radio transceiver61could be as low as VRADIO=1.2-1.4V, and that of digital VDIG=0.7-0.9V.

The basic idea is the same as before: providing regulated voltages to pulsed loads, while pulling a quasi-constant current from the battery (or a current that varies slowly over time). However, the working principle of the example ofFIG. 22is slightly different: Both output voltages VRADIOand VDIGare generated directly from VBAT(unlike in the example ofFIG. 20, VDIGis not generated from VRADIO). An example of a working sequence of the DC/DC-converter295with two consecutive working cycles of DC/DC converter is illustrated inFIGS. 24 to 26, wherein the current is directed to VRADIO, i.e., to the capacitor C2, in the first cycle and to VDIG, i.e., to the capacitor C1, in the second cycle, with each working cycle having a duration of 1 μs.FIGS. 24A & 24Bshows a sequence of the phases of the current flow during the first cycle, i.e., when the capacitor C2of VRADIOis charged;FIGS. 25A & 25Bshows a sequence of the phases of the current flow during the second cycle, when the capacitor C1of VDIGis charged;FIG. 26shows the respective plots of current profiles through the coil L during a working period for two different battery voltages (top) and the respective positions of the switches S1to S6bduring the entire working sequence including the first and second cycle (bottom)):In a first phase, the coil96is connected in parallel to the battery90during a charging time interval T1(the switches S2and S3close)In a second phase, the current accumulated in the coil96is sent either to VRADIOor to VDIG(the switch S1closes and also one of switches S4and S6closes) during a discharging time interval T2(T2uor T2d, respectively). During this time interval, the current flowing through the coil96decreases, charging one of the output capacitors C2and C1.The third phase is a reset phase, wherein switch S1remains closed, the switches S4and S6are opened and switch S5is closed, connecting the resistor RDAMPin parallel to the parasitic capacitance of node B(CB). This provides damping of parasitic oscillation of the resonant circuit (coil96in serial with CB). At end of the reset phase, both the current into the coil96and the voltage on node B are nulled.

The first cycle starts with a reset phase; the reset duration in this example is 6 clock ticks (the clock tick duration, for example, may be Tck=38.5 ns=1/26 MHz). Then, during the first phase the coil is pre-charged with current during time T1=8*Tck; and then during the second phase the coil current is send to VRADIOduring time T2u=4*Tck in this example. The duration of T1may adapted by software in order to maintain the peak current in the coil L (at end of time T1) constant (the current slope is proportional to VBAT; if VBATdecreases, one has to increase T1).

The second cycle starts like the first cycle: with a reset phase followed by the pre-charge of the coil L with current for the same time period T1. Then, during the second phase, the coil current is send to VDIGinstead of VRADIO. In this example, the duration of T2dis T2d=9*Tck; it is longer than that of T2u, because the decay of coil current is proportional to VRADIOand VDIG, respectively during the first and second cycle.

During the discharging time T2, the current into the coil96decays with a slope that is proportional to either VRADIOor VDIG. If T2is set too long, the current in the coil96would reverse and energy would be lost. Switch S4, respectively switch S6, have to be switched OFF before the current into the coil96reverses sense. The discharging times T2u(VRADIO) and T2d(VDIG) will be different and automatically adapted for switching switch S4, respectively S6, before the current in the coil96reaches zero.

A control circuit297provides regulation of the two output voltages VRADIOand VDIG. It operates as follows:VDIGis monitored first. If VDIGis lower than a given lower threshold value, then during the second phase of the DC/DC converter cycle (T2) the current is sent to VDIG(through switch S6). This defines a priority scheme between VRADIOand VDIG.If VDIGis higher than the lower threshold value, then during the second phase the coil current is sent to VRADIO(through switch S4).The control block297adjusts the number of working periods of the DC/DC converter per second (i.e., the duty-cycle) so as to maintain the output voltage VRADIObetween two defined limits VRADIO_min<VRADIO<VRADIO_max. This duty cycle is changed in small step increments. As in the case of the examples ofFIGS. 18 and 21, the control of duty cycle is implemented through a fractional-N divider realized with a multi-modulus divider99driven by a Delta-Sigma modulator100. The duty cycle is changed slowly with time using long time constants for making the changes inaudible.

Switches S1, S3and S5may be realized by N-MOST transistors, while switches S2, S4and S6may be realized by P-MOST transistors. As VRADIOis higher than VDIG, the bulk of S6(represented by the connection point of serial diodes D6A and D6B) needs to be connected correctly.

Switch S6bswitches the bulk of switch S6between VRADIOand VDIG: if the coil current is sent to VRADIO, then during the second phase V(B)=VRADIO>VDIG, and the bulk of switch S6(b) must be connected to VRADIO(if it would be connected to VDIG, then the diode D6A could turn into conduction, making the coil current flowing to VDIGinstead of VRADIO); if the coil current is sent to VDIG, then switch S6bmust connect the bulk of S6to VDIG, for best efficiency (lowest ON-resistance of switch S6).

A clamp circuit270(or voltage limiter) is connected in parallel to the transceiver61. The purpose of this circuit is to limit the value of VRADIObelow a safety limit VRADIO_SAFE(which is in general much higher than VRADIO_MAX). If the radio link is weak or disturbed, the transceiver61will remain switched ON during longer time for listening for more data packets transmitted; this will increase the average current consumption on VRADIO. If suddenly the radio link becomes good, the transceiver61will listen again on only for one data packet per frame, reducing strongly the average current taken from VRADIO. At this time, VRADIOwill raise rapidly, because the control unit297adapts the current with a low time constant, and then VRADIOmay reach a too high and unsafe value for the transceiver61. In this case, the clamp circuit270will pull down the excess current delivered by the DC/DC converter to GND, preventing VRADIOto exceed VRADIO_SAFE.

Newest IC technologies may allow using even lower supply voltages. However, three different supply voltages may be needed, for example, VCC≈1.0 V for the memories, VDD2≈0.9V for the transceiver, and VDD1≈0.7 V for the digital circuitry (DSP, microcontroller).

An example of a DC/DC converter395having three outputs in shown inFIG. 23, wherein VCC>VDD2>VDD1.

The general working principle is the same as in the example ofFIG. 22(DC/DC converter with two outputs):In a first phase, the coil96is connected in parallel to the power source90during a charging time interval T1(wherein the switches S2and S3are closed).In a second phase, the current accumulated in the coil96is sent either to VCC, VDD2 or to VDD1 (switch S1closes and either switch S4, S7or S6also closes) during a discharging time interval T2. During this time interval, the current flowing through the coil96decreases, charging one of the output capacitors C3, C2or C1.The third phase is the reset phase, wherein switch S1remains closed, switches S4, S6and S7are opened and switch S5closes, connecting the resistor RDAMPin parallel to the parasitic capacitance of node B(CB). This provides damping of parasitic oscillation of resonant circuit (coil96in serial with CB). At end of the reset phase, both the current into the coil96and the voltage on node B are nulled.

The loads Load1, Load2and Load3are different digital blocks or the transceiver, with the transceiver not necessarily being supplied at the highest voltage VCC.

As in the case of the example ofFIG. 22, there is a priority mechanism during the second phase:The current stored in the coil96is directed with priority to the lowest voltage VDD1, if VDD1 is lower than a threshold voltage VDD1.If VDD1 is equal to or larger than VDD1, and VDD2 is lower than a threshold value VDD2, the current is directed to VDD2If VDD1 is equal to or larger than VDD1, and VDD2 is equal to or larger than VDD2, the current is directed to VCCA protection circuit270(“voltage clamp”) prevents VCC to exceed a safety limit

As in the case of the example ofFIG. 22, the switches may be N-MOST and P-MOST transistors. The bulks of P-MOST S6and S7have to be connected according to the direction of current during the second phase:If the current flows to VCC, then the bulks of S6and S7(b6and b7) must be connected to VCC through switches S6band S7b, respectively.If the current flows to VDD2, then the bulk of S7must be connected to VDD2 and that of S6either to VCC or to VDD2.If the current flows to VDD1, then the bulk of S6must be connected to VDD1; that of S7can be connected either to VCC or to VDD2.

While various embodiments in accordance with the present invention have been shown and described, it is understood that the invention is not limited thereto, and is susceptible to numerous changes and modifications as known to those skilled in the art. Therefore, this invention is not limited to the details shown and described herein, and includes all such changes and modifications as encompassed by the scope of the appended claims