Schottky diode integrated into LDMOS

In an LDMOS device leakage and forward conduction parameters are adjusted by integrating an Schottky diode into the LDMOS by substituting one or more n+ source regions with Schottky diodes.

FIELD OF THE INVENTION

The invention relates to LDMOS (laterally diffused metal oxide semiconductor) devices. The invention is applicable to LDMOS which is used as a power switch (able to switch amperes of current). The requirements of a POWER MOSFET (like the LDMOS) are to minimize switching losses. In particular it relates to LDMOS devices implemented in a (Bipolar CMOS DMOS) BCD process.

BACKGROUND OF THE INVENTION

LDMOS (laterally diffused metal oxide semiconductor) transistors are commonly used in RF/microwave power amplifiers, e.g., in base-stations where the requirement is for high output power with a corresponding drain to source breakdown voltage usually above 60 volts. These transistors are fabricated by growing an epitaxial silicon layer on a more highly doped silicon substrate.

A typical LDMOS is shown inFIG. 1, which shows a n-epitaxial layer100grown on a p-epitaxial layer102, which, in turn is grown on a p-substrate104. In this depiction, an n-buried layer106is formed in the n-epi100on top of the p-epi102. The LDMOS includes an n+ drain110formed in an n-well112with an n-drift region114extending underneath the poly gate120. As shown inFIG. 1, the n+ source region122is formed in a p-body124. A p+ implant126provides a contact to the p-body. The gate120is formed on a gate oxide130.

One of the drawbacks of an LDMOS device is the conduction loss in the inherent body diode of the device. Also, due to minority carrier accumulation the reverse recovery time is slow. Hence the LDMOS suffers from high dynamic losses due to the slow reverse recovery times.

One prior art solution is to include an external Schottky diode. However due to the high inductance of the package and printed circuit board the benefits are diminished. This is illustrated in the circuit diagram ofFIG. 2, which shows a buck converter circuit comprising a high side LDMOS device200and a low side LDMOS202, with external Schottky diode210. The inductance of the package and the inductance of the PCB are depicted as parasitic stray inductances Lp220. As shown inFIG. 2, the LDMOS devices200,202both define an internal body diode240,242, respectively. The inductance of the external Schottky diode can be reduced by placing the Schottky diode in the same package as the MOSFET, however this requires two devices in the same package, which requires a large amount of space.

SUMMARY OF THE INVENTION

In accordance with an embodiment of the present invention, an apparatus is provided.

The apparatus has at least one Schottky diode integrated into an LDMOS which comprises a substrate; a first layer of lightly doped n-type epitaxial material formed over the substrate; a p-well formed in the first layer, wherein the well has a rectangular surface topology which includes a rectangular aperture in the p-well exposing the under-lying lightly doped n-type material; wherein the long side of the rectangular aperture is aligned with the long side of the p-well and further wherein the sides of the rectangular aperture are inside and spaced apart from the rectangular sides of the p-well; an n+ drain formed in the lightly doped n-type epitaxial region spaced apart from the p-well; at least one Schottky diode formed by providing a metal or metalized region that forms a diode within the surface of the aperture exposing the lightly doped n-type region in the p-well, wherein the metal over the diode forms the anode of the diode; wherein the metalized region comprises a silicide region over surface of the aperture exposing the lightly doped n-type region in the p-well; a source divided into multiple n+ source regions by intermediate p+ body contact regions, wherein the p+ body contact regions between the multiple n+ source regions are configured to increase the safe operating area of the apparatus; a p+ ring coupled to the p-body region and surrounding each at least one Schottky diode, wherein the p+ ring provides edge termination of the at least one Schottky diode to reduce leakage; and a metal layer coupling the n+ source region, the p+ body contact regions and the anodes of the at least one Schottky diode.

In accordance with an embodiment of the present invention, a method of reducing forward conduction loss in an LDMOS device, which comprises integrating a Schottky diode into the LDMOS device by converting part of the LDMOS device into a Schottky diode; wherein the LDMOS device includes a lightly doped n-type region and the Schottky diode is formed by forming a metal or metalized region on the lightly doped n-type region; and wherein the LDMOS includes multiple n+ source regions, wherein the multiple n+ source regions are separated by p-type regions, wherein the p− type regions between the multiple n+ source regions are configured to increase the safe operating area of the LDMOS device.

Further, in accordance with an embodiment of the present invention, a method of reducing reverse recovery time in an LDMOS device, which comprises integrating a Schottky diode into the LDMOS device by converting part of the LDMOS device into a Schottky diode by forming a p− well in a first layer, wherein the p− well has a rectangular surface topology which includes a rectangular aperture in the p-well exposing an under-lying lightly doped n-type material; forming the Schottky diode by forming a metal or metalized region over the lightly doped n-type region; and forming a source divided into multiple n+ source regions by intermediate p+ well contact regions, wherein the p+ well contact regions between the multiple n+ source regions are configured to increase the safe operating area of the LDMOS.

DETAILED DESCRIPTION OF THE INVENTION

The present invention provides an LDMOS device with integrated Schottky diode.

Schottky diodes are formed when a metal plate is brought into contact with lightly doped n-type silicon. As depicted inFIGS. 3 and 4, this creates a high concentration of electrons300at the surface402of the metal plate where it contacts the n-type silicon404, and a depletion region310,410between the metal plate and the n-type silicon, which shows the electron concentration across the Schottky diode. This provides the Schottky diode with a forward breakdown voltage Vf of about 0.3V compared to about 0.7V for a p-n diode formed between p-type silicon and n type silicon. The benefits of a lower Vf are realized when the LDMOS is implemented in a circuit such as the buck converter ofFIG. 2.

FIG. 5shows the typical waveforms for a synchronous buck converter. As can be seen by comparing the voltage waveform on the gate of the high side LDMOS100(curve500) with the voltage waveform on the gate of the low side LDMOS102(curve502) there is a certain dead time (tdeadtime)510when the gate voltage on the LDMOS102changes but the gate voltage on LDMOS102has not yet changed. If Vf is the diode forward voltage, IL is the diode current, and f is the frequency, diode conduction loss is given by Vf×IL×tdeadtime×f. It will therefore be appreciated that the forward conduction loss is dependent on the forward breakdown voltage Vf. Therefore losses will be lower for a Schottky diode with a Vf of only 0.3V compared to the 0.7V for a p-n diode.

The Schottky diode also reduces the reverse recovery loss. Since the Schottky diode is a majority carrier device at low level injection, the minority carrier storage time is eliminated, thereby providing for a faster reverse recover time Trr. Trr is depicted by reference numeral520on curve530.

Consider again the external Schottky diode circuit ofFIG. 2. When the high side LDMOS turns on, the low side diode (body diode or external Schottky) has to recover the stored charge, also known as the diode reverse recovery charge Qrr. The diode recovery loss, which is a function of the input voltage Yin and the frequency, is given by Vin×Qrr×f. Since a Schottky diode has a lower Qrr than a regular p-n diode or an internal MOSFET body diode, it provides a lower diode recovery loss.

The present invention therefore provides substantial loss reduction, both regarding forward conduction losses as well as reverse recovery losses. One implementation of the LDMOS with integrated Schottky is shown inFIG. 6, which shows a buck converter circuit making use of LDMOS devices for the high side and low side devices600,602, respectively.

In order to integrate the Schottky diode without adding process steps and thus additional cost, the present invention implements the Schottky diode using the same process steps as those used for the LDMOS. In an LDMOS formed using a BCD process, the Schottky is also implemented in the BCD process flow.

FIG. 7shows a top view of the source side of a typical prior art LDMOS device. The source comprises multiple n+ source regions700, each separated laterally from the next by a p+ body regions702, wherein the p+ body contact regions between the multiple n+ source regions are configured to increase the safe operating area of the apparatus. The present invention integrates Schottky diodes into the LDMOS device by eliminating a portion of the p-body underlying of the one or more n+ source regions from the LDMOS. This is shown inFIG. 8, which shows a top view of one embodiment of an LDMOS device of the invention. A section of the p-body and the corresponding source has been eliminated by blocking the deposition of p− and n+ impurities during the formation of the p-body and the source, as depicted by the region804, which was masked to avoid the formation of a portion of the p-body and the n+ source. In this embodiment, the region804covers an area that is separated into three regions by p+ body contacts806forming a guard ring as is shown more clearly in the sectional view ofFIG. 9, thereby allowing three Schottky diodes to be formed. As can be seen inFIG. 8, the source regions800separated by the p+ body regions802are shown above and below the blocked region804with p+ body regions terminating the source segments at the top and bottoms of the segmented source800and p+ body802regions, wherein the p+ body contact regions and the multiple n+ source regions are configured to increase the safe operating area of the apparatus. A silicide layer910is formed to span the blocked region804to define and the anode of the three Schottky diodes. The cathode contact to the Schottky diodes is defined by the drain contact (not shown), which extends to the n-epi912via an n-well as best understood from the depiction of an LDMOS inFIG. 1. By determining how many of the n+ source regions are to be blocked it is possible to provide a trade-off between leakage and forward conduction. More or fewer such regions can be blocked to form a greater or smaller Schottky diode area.

By eliminating the p-body and highly doped n+ source from the region804a lightly doped region is provided in the form of an underlying epitaxial layer. This is best shown inFIG. 9, which shows a sectional side view of another embodiment of the source side of an LDMOS device of the invention. For ease of reference the embodiment ofFIG. 9uses the same reference numerals to depict similar structural elements as those in theFIG. 8embodiment. The epitaxial layer900defines the cathodes of the integrated Schottky diodes of the invention. In order to provide an anode, a metalized region is formed over the epitaxial layer900. In one embodiment of the invention a cobalt silicide layer910is formed over the epitaxial layer900. Each Schottky diode includes at least one contact to define anode and cathode contacts. In the embodiment ofFIG. 9each Schottky diode is provided with three contacts908to the silicide layer910. The contacts provide the anode contact to the Schottky diode. The electrical contact to the epitaxial region900in this embodiment is made by means of the drain contact, which contacts the n+ drain region formed in an n-well as best appreciated with respect to the prior art LDMOS device ofFIG. 1and also forms the cathode contact to the Schottky diodes.FIG. 1shows the n+ drain110formed in the n-well112.

The cobalt silicide forming the anode of the Schottky diodes will, if a typical LDMOS process is used, be formed on top of the lightly doped n-epitaxial region and will provide a Schottky diode with the underlying lightly doped n-epitaxial region.

In the embodiment ofFIG. 10each Schottky diode is surrounded by a p+ ring for edge termination, to reduce leakage. This also clearly shown inFIGS. 8 and 9.

The present invention thus provides an elegant way of reducing forward conduction loss and reverse recovery time in an LDMOS while maintaining the same process steps. Therefore if a Bipolar CMOS DMOS (BCD) process is used in forming the LDMOS, the present invention allows the BCD process to be used in forming an integrated Schottky diode, in accordance with the invention.

In the above embodiments the Schottky diodes were formed in of the lightly doped n-epitaxial region surrounded by the source/body active region. Schottkys are leakier than regular diodes, hence, only a selected few n+ regions were removed in the source/body active region. The number of n+ source regions eliminated to support Schottky diodes depends on the degree to which high power current has to be supported by the device and the amount of leakage that is acceptable. It will also be noted that each Schottky diode region is surrounded by a p+ ring for edge termination, to reduce leakage.

In the above embodiments leakage reduction is achieved by shorting out the p+ body contact region802, p-body and n+ source regions800by means of a layer of cobalt silicide.

While the implementation was described with respect to particular embodiments, it will be appreciated that the integrated Schottky can be implemented in different ways to achieve integrated Schottky diodes in the source/body active region. Also as discussed above, the number of Schottky diodes created will vary depending on the application.