Apparatus and method for transferring multi-byte words in a fly-by DMA operation

An apparatus and method for transferring multi-byte words having arbitrary start and end byte addresses are described. Data transfers between a memory and a PCI-bus pass through a PCI-side aligner unit, PCI FIFO, Endian swap logic, and PCI-bus interface unit under the control of a PCI FIFO controller. The PCI-side aligner unit properly aligns the data while communicating data with the memory's bus on a word-at-a-time basis, and communicating data with the PCI FIFO managed on a byte-at-a-time basis synchronous with a clock signal provided by the memory's bus. The Endian swap logic properly orients the data in big or little Endian orientation. The PCI-bus interface unit communicates data with the PCI-bus on a word-at-a-time basis, and communicates data with the PCI FIFO managed on a byte-at-a-time basis synchronous with a clock signal provided by the PCI-bus. To keep track of unread stored data in the PCI FIFO, the PCI FIFO controller includes a #Bytes logic unit that automatically accounts for wrap-around of write and read pointers for the PCI FIFO.

FIELD OF THE INVENTION

The present invention generally relates to data transfer and in particular, to an apparatus and method for transferring multi-byte words in a fly-by DMA operation.

BACKGROUND OF THE INVENTION

Fly-by direct memory access (“DMA”) read and write operations are employed to free up valuable system resources such as a central processing unit (“CPU”) and DMA controller from having to extensively manage data transfers between a memory and PCI-bus. An example of such fly-by DMA operation is described in U.S. patent application Ser. No. 09/888,321 entitled “Transaction Aligner Microarchitecture” filed Jun. 21, 2001, assigned to the same Assignee as the present invention, and incorporated herein in its entirety by this reference.

Management of data transfers between a memory and a PCI-bus can be complicated, however, for a number of reasons. Although it may be desirable to manage certain functions on a byte-at-a-time basis, data transfers on the memory's bus and the PCI-bus typically use word addresses so that data are transferred on a word-at-a-time basis. Each word typically comprises multiple bytes to form multi-byte words. Valid data for multi-byte words may start and end at arbitrary byte locations in the multi-byte words. Data aligners are commonly employed since the starting and ending byte locations may be different for data communicated from and to the memory and data communicated from and to the PCI-bus. Data communicated to and from the PCI-bus may also require swapping between big and little Endian orientations. To simplify implementation, a fixed byte enable vector may be required to be provided during each burst transfer of data to the PCI-bus. Also, data transfer rates from and to the memory may not be related to data transfer rates from and to the PCI-bus.

OBJECTS AND SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to provide an apparatus and method for transferring multi-byte words having arbitrary start and end byte addresses.

Another object is to provide an apparatus and method for transferring multi-byte words that employs a hybrid byte-at-a-time and word-at-a-time data transfer management scheme for enhanced efficiency and simplicity of implementation.

Another object is to provide an apparatus and method for transferring multi-byte words that accommodates different data transfer rates from and to the memory than from and to the PCI-bus.

These and additional objects are accomplished by the various aspects of the present invention, wherein briefly stated, one aspect is an apparatus for transferring multi-byte words in a fly-by DMA operation. The apparatus comprises a FIFO, first and second registers, and control logic. The FIFO is coupled to a memory and a PCI-bus such that the FIFO buffers multi-byte words that are transferred between the memory and the PCI-bus. The first register stores a write pointer to a next available byte location to be written to the FIFO when the multi-byte words are being transferred from the memory to the PCI-bus, and a read pointer to a next byte location to be read from the FIFO when the multi-byte words are being transferred from the PCI-bus to the memory. Conversely, the second register stores a read pointer to a next byte location to be read from the FIFO when the multi-byte words are being transferred from the memory to the PCI-bus, and a write pointer to a next byte location to be read firm the FIFO when the multi-byte words are being transfer from the PCI-bus to the memory. The control logic is configured to manage the transfer of the multi-byte words through the FIFO and shift the read and write pointers to match a starting byte address of a first multi-byte word at the beginning of a fly-by DMA operation.

Another aspect is a method for transferring multi-byte words, comprising: receiving one or more multi-byte words and a first clock signal from a first bus configured to communicate on a word-at-a-time basis; writing the one or more multi-byte words into a FIFO managed on a byte-at-a-time basis synchronous with the first clock signal; reading the one or more multi-byte words from the FIFO managed on a byte-at-a-time basis synchronous with a second clock signal received from a second bus; and transmitting the one or more multi-byte words to the second bus on a word-at-a-time basis.

Additional objects, features and advantages of the various aspects of the present invention will become apparent from the following description of its preferred embodiment, which description should be taken in conjunction with the accompanying drawings.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 1illustrates, as an example, a block diagram of a computer system including a CPU101, memory102and DMA controller103coupled through a bus104. A memory controller105controls the reading and writing of multi-byte word data on a word-at-a-time basis from and to the memory102. The multi-byte word data (also referred to herein simply as “data”) in this case may have arbitrary starting and ending byte addresses as they are read from or written to the memory102. By convention, data provided to or retrieved from the bus104, however, should be fully left aligned. Therefore, a memory-side aligner unit106is included in the computer system to align the multi-byte word data read from the memory102so that they are fully left-aligned before providing the data to the bus104and conversely, to retrieve fully left-aligned data from the bus104and properly shift them so that they reflect correct starting and ending byte addresses before writing them into the memory102.

Similarly, a PCI-side aligner unit107is included in the computer system to align multi-byte word data received from the PCI-bus108so that they are fully left-aligned before providing the data to the bus104and conversely, to retrieve fully left-aligned data from the bus104and properly shift them so that they reflect correct starting and ending byte addresses before they are transferred to the PCI-bus108. Information of the starting and ending byte addresses are provided by a PCI FIFO controller109as least significant address bits A1, A0of their respective PCI-bus addresses. The starting PCI-bus address is provided to the PCI FIFO controller109by, for example, the DMA controller103, and subsequent PCI-bus addresses, are then determined, for example, by the PCI FIFO controller109as it manages the transfer of data between the bus104and the PCI-bus108. Although the CPU101, DMA controller103, memory-side aligner unit106, PCI-side aligner unit107, and PCI FIFO controller logic109are all shown being connected to the bus104to simplify the present description, in a preferred embodiment of the invention, the bus104comprises a system bus to which the CPU101and memory-side aligner unit106are coupled, a local bus to which the DMA controller103and PCI-side aligner unit107are coupled, and a bridge circuit coupling the system bus to the local bus.

A PCI FIFO110buffers multi-byte words being transferred from or to the PCI-bus108. When communicating data with the PCI-side aligner unit107, the PCI FIFO110and PCI-side aligner unit107preferably perform such communication synchronous with a local bus clock signal provided by the bus104. On the other hand, when communicating data with a PCI-bus interface unit112through Endian swap logic111, the PCI FIFO110and the PCI-bus interface unit112preferably perform such communication synchronous with a PCI-bus clock signal provided by the PCI-bus108. The Endian swap logic111responds to a swap bit provided by the PCI FIFO controller logic109to orient the data into either little or big Endian orientation before passing it on.

The PCI FIFO110operates as a circular FIFO so that writing to the PCI FIFO110wraps around back to the starting address after a last address in the PCI FIFO110has been written to. In the present example, the PCI FIFO110stores up to 64 4-byte words that are written in and read out on a byte-at-a-time basis under management of the PCI FIFO controller logic109. The transfer out or reading of stored data is not initiated by the PCI FIFO controller logic109until at least a specified number of bytes have been stored in the PCI FIFO110during, for examples, a fly-by DMA read or write operation. Once such a transfer is initiated towards the PCI-bus108, the transfer is performed in one or more burst transfers during each of which a fixed byte enable vector is provided to the PCI-bus108. Communication of data between the PCI FIFO110and the PCI-side aligner107is managed on a byte-at-a-time basis, while communication of data between the PCI-side aligner107and the bus104is performed on a word-at-a-time basis. Similarly, communication of data between the PCI FIFO110and the PCI-bus interface unit112is managed on a byte-at-a-time basis, while communication of data between the PCI-bus interface unit112and the PCI-bus108is performed on a word-at-a-time basis.

The PCI-bus interface unit112communicates with the PCI-bus108. When receiving data from the PCI-bus108, the PCI-bus interface unit112passes data to the Endian swap logic111in response to command/byte enable, address and control information provided by the PCI FIFO controller logic109. The PCI FIFO controller logic109manages the transfer of the data in this case from the PCI-bus interface unit112through the Endian swap logic111and into the PCI FIFO110. On the other hand, when transferring data to the PCI-bus108, the PCI-bus interface unit112receives command/byte enable, address and control information from the PCI FIFO controller logic109, and data from the Endian swap logic111. The PCI FIFO controller logic109manages the transfer of the data in this case to the PCI-bus interface unit112from the PCI FIFO110.

FIG. 2illustrates, as an example, a block diagram of the PCI FIFO controller logic109coupled to the PCI FIFO110. There are several important registers included in the PCI FIFO controller logic109along with control logic201and #Bytes logic202.

Two pointer registers,203and204, store byte address pointers for writing to and reading from the PCI FIFO110. When data is being transferred to the PCI-bus108from the memory102, for example, in a fly-by DMA write operation, the first pointer register203stores a write pointer to the next byte location in the PCI FIFO110that is available to be written to, and the second pointer register204stores a read pointer to the next byte location in the PCI FIFO110that is to be read from. On the other hand, when data is being written to the memory102from the PCI-bus108, for example, in a fly-by DMA read operation, the first pointer register203stores a read pointer to the next byte location in the PCI FIFO110that is to be read from, and the second pointer register204stores a write pointer to the next byte location in the PCI FIFO110that is available to be written to.

Upon initiation of a fly-by DMA read or write operation through the PCI FIFO110, the control logic201initially resets then shifts the contents of the pointer registers203and204to indicate the starting byte address of a first multi-byte word to be transferred from (i.e., fly-by DMA read operation) or to (i.e., fly-by DMA write operation) the PCI-bus108. Thereafter, for each byte of data written into the PCI FIFO110, the write pointer is incremented by one (e.g., contents of register203during fly-by DMA read or contents of register204during a fly-by DMA write operation), and for each byte of data read from the PCI FIFO110, the read pointer is incremented by one (e.g., contents of register204during fly-by DMA read or contents of register203during a fly-by DMA write operation). In this way, the starting and ending byte addresses of the write and read pointers correspond to (or match) the starting and ending byte addresses on the PCI-bus108for the fly-by DMA operation.

The #Bytes logic202keeps track of the number of unread stored bytes in the PCI FIFO110. Since the PCI FIFO110is a circular FIFO, it is important to keep track of this number so overwriting of stored data can be avoided be fore the data is read out of the PCI FIFO110.

In addition to initializing and incrementing the pointer registers203and204, the control logic201also provides the first two bits A1, A0of the PCI-bus address to the PCI-side aligner unit107so that the PCI-side aligner unit107knows how many bytes to shift the first byte of the first multi-byte word when passing data to the PCI FIFO110(e.g., during a fly-by DMA write operation), or knows the byte location of the first valid byte in the first multi-byte word when passing data to the bus104(e.g., during a fly-by DMA read operation).

Another function of the control logic201is to initiate data transfers each time after prespecified numbers of bytes have been written to the PCI FIFO110. In order to make efficient use of the local bus104when transferring data to the memory102(e.g., during a fly-by DMA read operation) and the PCI-bus108when transferring data to a peripheral113(e.g., during a fly-by DMA write operation), data is not transferred out of the PCI FIFO110until these prespecified numbers of bytes have been written to the PCI FIFO110.

After initializing the pointer registers203and204, the control logic201does not start a transfer of data until the number of bytes written into the PCI FIFO11Q, as indicated by the output of the #Bytes logic202, reaches at least a first specified number, such as 64 bytes. Upon reaching that number, the control logic201stores the number of unread stored bytes in the PCI FIFO110at that time in a count register205, initiates a data transfer request for a corresponding number of multi-byte words, and starts keeping track of additional bytes written into the PCI FIFO110in a counter register206. Subsequently, when a sum of the contents of the count register205and the counter register206is at least a second specified number, such as 128 bytes, the control logic201initiates another data transfer request for a corresponding number of multi-byte words to the number indicated by the counter register206at that time, and appropriately updates the count register205and resets the counter register206so that after at least another prespecified number of bytes, such as 64 bytes, have been written into the PCI FIFO110, another data transfer and updating of the registers205and206occurs. In this way, the control logic201initiates a data transfer from the PCI FIFO110either each time approximately 64 bytes (or 16 or 17 4-byte words, depending upon the valid data byte locations of the words) have been written into the PCI FIFO110, or when the remaining number of bytes in the data transfer transaction in progress (e.g., a fly-by DMA read or write operation) have been written into the PCI FIFO110.

When data is being transferred to the PCI-bus108, such as in a fly-by write operation, the control logic201initiates transfer of the multi-byte words from the PCI FIFO110to the PCI-bus108in one or more burst transfers individually conducted while a constant byte enable vector is being communicated to the PCI-bus108by the control logic201through the PCI-bus interface unit112. In this case, if the first multi-byte word contains less than a full multi-byte word, the control logic201initiates transfer of the first multi-byte word in a single word burst from the PCI FIFO110while a byte enable vector indicating that less than a full multi-byte word is being communicated, is being provided to the PCI-bus108. Likewise, if the last multi-byte word to be transferred contains less than the full multi-byte word, the control logic201initiates transfer of the last multi-byte word in a single word burst from the PCI FIFO110while a byte enable vector indicating that less than the full multi-byte word is being communicated, is being provided to the PCI-bus108. Otherwise, the control logic201initiates transfer of up to the number of words to be transferred, in one or more burst transfers from the PCI FIFO110while a constant byte enable vector indicating that full multi-byte words are being communicated, is provided to the PCI-bus108. In all cases, initiation of the burst transfers involve providing the appropriate signals to the PCI-bus interface unit112so that the PCI-bus interface unit112provides the burst transfers of data to the PCI-bus108.

Communications between the PCI-side aligner unit107and the PCI FIFO110are preferably performed according to a first clock signal CLK1that is generated by the control logic201to be synchronous with the local bus clock signal that it receives directly from the local bus104. As previously described, such communications of data between the PCI-side aligner unit107and the PCI FIFO110are managed on a byte-at-a-time basis. Communications between the PCI FIFO110and the PCI-bus interface unit112, on the other hand, are preferably performed according to a second clock signal CLK2that is generated by the control logic201to be synchronous with the PCI-bus clock signal that it receives indirectly through the PCI-bus interface unit112from the PCI-bus108. Such communications of data between the PCI-bus interface unit112and the PCT FIFO110are also managed on a byte-at-a-time basis.

Although the PCI FIFO110is represented as a single block in the figures, in the preferred embodiment of the invention, the PCI FIFO110comprises an output FIFO for data being transferred to the PCI-bus108from the memory102and an input FIFO for data being transferred from the PCI-bus108to the memory102. In this case, for each of the directional FIFO's, a corresponding set of registers is also included for FIFO management purposes.

FIG. 3illustrates, as an example, a block diagram of the #Bytes logic202along with the pointer registers203and204, configured for performing a fly-by DMA write operation. Both pointer registers203and204generate a rollover indication when their contents (e.g., the write pointer in this case for register203and the read pointer for register204) rollover from their maximum count values back to zero. The maximum count values in this case also indicate the size of the PCI FIFO110. In particular, the maximum number of bytes that can be stored in the PCI FIFO110in this example equals 256 (or64 4-byte words), therefore, the maximum count value for each of the registers203and204is equal to 255, as indicated by the 8-bit address “11111111”, and a minimum count value for each of the registers203and204is equal to 0, as indicated by the 8-bit address “00000000”, so as to provide a range of 256 count values.

An S-R flip-flop301in the #Bytes logic201has a set input “S” coupled to the rollover indication generated by the register203containing the write pointer, and a reset input “R” coupled to the rollover indication generated by the register204containing the read pointer. Consequently, each time the S-R flip-flop301is set by the register203containing the write pointer rolling over, its output provides a “1”, and each time the S-R flip-flop301is reset by the register204containing the read pointer rolling over, its output provides a “0”. In contrast, a storage cell302has an output that provides a fixed “0” value.

An “A” register303has its least significant bit inputs (i.e., bits0˜8) coupled to the outputs of the register203indicating in this case the byte address of the PCI FIFO110that the write pointer is currently pointing to, and in its next most significant bit input (i.e., bit9) coupled to the output of the S-R flip-flop301. These inputs are then latched to the outputs of the “A” register303, in response to, for example, the clock signal CLK1generated by the control logic201. Similarly, a “B” register304has its least significant bit inputs (i.e., bits0˜8) coupled to the outputs of the register204indicating in this case the byte address of the PCI FIFO110that the read pointer is currently pointing to, and in its next most significant bit input (i.e., bit9) coupled to the output of the storage cell302. These inputs are then latched to the outputs of the “B” register304, in response to, for example, the clock signal CLK2generated by the control logic201.

A subtractor unit305has a first set of inputs coupled to the outputs of the “A” register303, a second set of inputs coupled to the outputs of the “B” register304, and outputs306providing a difference between the two values represented by the two sets of inputs.

Consequently, the outputs306indicate the number of unread stored bytes in the PCI FIFO110taking into account write pointer rollover and possible write pointer/read pointer wrap-around.

To accommodate a fly-by DMA read operation, the block diagram ofFIG. 3is modified so that the pointer registers203and204effectively reverse positions. Such reversal is necessary, because the pointer register204in that case contains the write pointer and the register203contains the read pointer. One structure to implement such configurations for fly-by DMA write and read operations includes in addition to the elements shown inFIG. 3, four additional mulitplexers. Each of the added multiplexers include inputs that are selected by the type of fly-by DMA operation being performed at the time. A first multiplexer provides the set input to the S-R flip-flop301. It has the rollover indications from the pointer registers203and204as inputs, and a select input that selects the rollover indication from pointer register203if a fly-by DMA write operation is being performed or the rollover indication from pointer register204if a fly-by DMA read operation is being performed. A second multiplexer provides the reset input to the S-R flip-flop301. It also has the rollover indications from the pointer registers203and204as inputs, but its select input selects the rollover indication from pointer register204if a fly-by DMA write operation is being performed or the rollover indication from pointer register203if a fly-by DMA read operation is being performed.

A third multiplexer provides the least significant bits (i.e., 8:0) to the “A” register303. It has the outputs of the pointer registers203and204as inputs, and a select input that selects the outputs of the pointer register203if a fly-by DMA write operation is being performed or the outputs of the pointer register204if a fly-by DMA read operation is being performed. A fourth multiplexer provides the least significant bits (i.e., 8:0) to the “B” register304. It also has the outputs of the pointer registers203and204as inputs, but its select input selects the outputs of the pointer register204if a fly-by DMA write operation is being performed or the outputs of the pointer register203if a fly-by DMA read operation is being performed.

Alternatively, to accommodate a fly-by DMA read operation, the block diagram ofFIG. 3is modified to include another identically structure circuit except with the pointer registers203and204in reverse positions. Such an alternative implementation is preferable for performance and simplicity in construction and control purposes.

The output of the #Bytes logic202is also used to request the bus104for fly-by DMA read or write operations. As a particular example, the bus104is assumed to operate much faster than the PCI-bus108. For a fly-by DMA read operation in this case, the output of the #Bytes logic202initiates data transfer from the PCI FIFO110to the bus104after 64 bytes have been written into the PCI FIFO110from the PCI-bus108. On the other hand, for a fly-by DMA write operation, the output of the #Bytes logic202initiates data transfer from the bus104to the PCI FIFO110whenever there is space of 64 bytes left available in the PCI FIFO110for writing to (e.g., output of the #Bytes logic202indicates a count value less than 192 for the 256 byte PCI FIFO110). For data transfers between the PCI FIFO110and the PCI-bus108, however, the output of the #Bytes logic202initiates data transfer from the PCI FIFO110to the PCI-bus108whenever there is unread data in the PCI FIFO110, and from the PCI-bus108to the PCI FIFO110whenever there is available space in the PCI FIFO110.

Although the various aspects of the present invention have been described with respect to a preferred embodiment, it will be understood that the invention is entitled to full protection within the full scope of the appended claims.