Imaging device

An imaging device comprising: a pixel array that includes pixels arranged in rows and columns, each of the pixels outputting a pixel signal; vertical signal lines each of which is provided for each of the columns; a reference-signal generator that generates a reset signal corresponding to a reset voltage of the pixels; a signal processor that outputs a differential signal corresponding to a difference between the pixel signal and the reset signal; a first switch that is connected between one of the vertical signal lines and the signal processor, the first switch switching between input and interruption of the pixel signal from each of the pixels to the signal processor; and a second switch that is connected between the reference-signal generator and the signal processor, the second switch switching between input and interruption of the reset signal from the reference-signal generator to the signal processor.

BACKGROUND

1. Technical Field

The present disclosure relates to an imaging device.

2. Description of the Related Art

In imaging devices having pixel array sections where pixel cells are arranged in rows and columns, signal processing called correlated double sampling (CDS) is performed. Specifically, a CDS pixel signal is generated as an output signal. The CDS pixel signal corresponds to a potential difference between two arbitrary different timings in a vertical signal line disposed corresponding to a pixel column. The potential difference is the difference between a reset potential at the time of a reset operation and a potential at the time of pixel signal output.

Japanese Patent No. 4116710 discloses an imaging device including a two-dimensional pixel array, a retaining unit that is disposed for each pixel column and retains an output of a noise suppression circuit, and an integration unit that integrates signals resulting from reading a signal from the retaining unit two or more time during a horizontal blanking period.

SUMMARY

In one general aspect, the techniques disclosed here feature an imaging device comprising: a pixel array that includes pixels arranged in rows and columns, each of the pixels outputting a pixel signal; vertical signal lines each of which is provided for each of the columns; a reference-signal generator that generates a reset signal corresponding to a reset voltage of the pixels; a signal processor that outputs a differential signal corresponding to a difference between the pixel signal and the reset signal; a first switch that is connected between one of the vertical signal lines and the signal processor, the first switch switching between input and interruption of the pixel signal from each of the pixels to the signal processor; and a second switch that is connected between the reference-signal generator and the signal processor, the second switch switching between input and interruption of the reset signal from the reference-signal generator to the signal processor.

It should be noted that general or specific embodiments may be implemented as an element, a device, a system, an integrated circuit, and a method, or any selective combination thereof.

DETAILED DESCRIPTION

In the imaging device disclosed in Japanese Patent No. 4116710, an integration circuit section resets a vertical signal line. This vertical signal line has a large capacity and therefore, charge and discharge at the time of reset takes a long time. Further, the integration circuit section is configured using an integrator having a switched capacitor, and even if an input voltage from a vertical signal line represents no (a dark) signal, an offset voltage that is the difference between the input voltage and a reference (ground) voltage is generated by a switching operation of the switched capacitor. Because of this switching operation with the offset voltage, a reading operation takes a long time.

In view of the above-described situation, a non-limiting and exemplary embodiment of the present disclosure provides an imaging device capable of high-speed reading.

An imaging device according to each of embodiments of the present disclosure will be described in detail below with reference to drawings. The embodiments to be described below each represent a specific example of the present disclosure. Therefore, numerical values, shapes, materials, components, arrangements as well as connection configurations of the components, and the like described in the following embodiments are each taken as an example, and not intended to limit the present disclosure. Accordingly, among the components in the following embodiments, any component not described in each independent claim representing a broadest concept of the present disclosure will be described as an arbitrary component.

In addition, each of the drawings is schematic, and is not necessarily an exact illustration. Moreover, in each of the drawings, the same components are provided with the same reference characters.

First Embodiment

First, an overall configuration of an imaging device according to a first embodiment will be described.

FIG. 1is a block diagram showing an overall configuration of the imaging device according to the first embodiment. An imaging device1shown inFIG. 1includes a pixel array section10, a driving control section20, a vertical scanning section30, a horizontal scanning section40, a signal retention section50, a current source60, a reference-signal generation section70, a first switch section80A, and a second switch section80B. Further, in the pixel array section10and a peripheral region thereof, a vertical signal line210is disposed for each pixel column, and a scanning line220is disposed for each pixel row.

The pixel array section10is an imaging section in which pixels100are arranged in rows and columns.

The vertical scanning section30has a function of controlling a reset operation, an electric-charge accumulation operation, and a reading operation for the pixels100, row by row.

The current source60is connected to the vertical signal line210, and disposed corresponding to the vertical signal line210. The current source60forms a source follower circuit, together with an amplification transistor of the pixel100, and has a function of amplifying a voltage corresponding to electric charge stored in the pixel100.

The signal retention section50retains a differential signal between a pixel signal outputted from the pixel100and a reset signal corresponding to this pixel100, and outputs the differential signal in response to an instruction of the horizontal scanning section40to be described later.

The reference-signal generation section70generates a reset signal corresponding to the pixel100.

The first switch section80A is connected to the vertical signal line210, and disposed corresponding to the vertical signal line210. The first switch section80A switches between input and interruption of a pixel signal from the pixel100to the signal retention section50.

The second switch section80B is connected to the reference-signal generation section70, and disposed corresponding to the vertical signal line210. The second switch section80B switches between input and interruption of a reset signal from the reference-signal generation section70to the signal retention section50.

The horizontal scanning section40has a function of sequentially selecting the above-described differential signal for one row retained in the signal retention section50, and reading the selected differential signal to an output circuit (not shown) disposed on the output side of the signal retention section50.

The driving control section20controls the vertical scanning section30, the horizontal scanning section40, the signal retention section50, the reference-signal generation section70, the first switch section80A, and the second switch section80B, by supplying various control signals to these sections. Specifically, for example, at first, the driving control section20brings the second switch section80B to a conduction state, thereby allowing the signal retention section50to retain the above-described reset signal. Next, in the state where the above-described reset signal is retained by the signal retention section50, the driving control section20brings the first switch section80A to a conduction state, thereby allowing the signal retention section50to input a pixel signal via the vertical signal line210. The signal retention section50thus retains a differential signal between a pixel signal outputted from the pixel100and a reset signal corresponding to this pixel100.

[2. Configuration of Each Section]

FIG. 2is a diagram showing an example of a circuit configuration of each of the pixel and the reference-signal generation section according to the first embodiment.FIG. 2shows a specific circuit configuration example of each of the pixel100, the reference-signal generation section70, the current source60, and each switch section.

The pixel100includes a photoelectric conversion element101, a reset transistor102, an amplification transistor103, a select transistor104, and a charge storage section105.

The photoelectric conversion element101is a photoelectric converter that performs a photoelectric conversion for converting incident light into signal charge. Specifically, the photoelectric conversion element101includes an upper electrode, a lower electrode, and a photoelectric conversion film interposed between these electrodes. The photoelectric conversion film contains, for example, organic molecules having a high light-absorbing ability. Further, the photoelectric conversion film has a thickness of, for example, about 500 nm. Furthermore, the photoelectric conversion film is formed using, for example, vacuum deposition. The light-absorbing ability of the above-described organic molecules is high over the entire range of visible light from a wavelength of about 400 nm to a wavelength of about 700 nm.

The photoelectric conversion element of the pixel100according to the present embodiment is not limited to the above-described configuration using the organic photoelectric conversion film, and may be, for example, a photodiode configured using an inorganic material.

The charge storage section105is connected to the photoelectric conversion element101, and stores signal charge.

The amplification transistor103has a gate connected to the charge storage section105, and a drain supplied with a power supply voltage VDD, and outputs a pixel signal according to an amount of signal charge stored in the charge storage section105.

The reset transistor102has a drain supplied with a reset voltage VRST, and a sauce connected to the charge storage section105, and resets the potential of the charge storage section105.

The select transistor104has a drain connected to a sauce of the amplification transistor103, and a sauce connected to the vertical signal line210, and selectively outputs a pixel signal from the amplification transistor103.

The transistor73is a first transistor having a drain supplied with a power supply voltage VDD.

The transistor74is a second transistor having a drain connected to a sauce of the transistor73, and a sauce connected to a switch transistor82of the second switch section80B.

The transistor72is a third transistor having a drain supplied with a reset voltage VRST, and a sauce connected to a gate of the transistor73.

The transistor75is a current source transistor having a drain connected to the sauce of the transistor74, and a source being grounded.

The above-described circuit configuration of the reference-signal generation section70is similar to a circuit configuration formed by combining the pixel100excluding the photoelectric conversion element101, with a current source transistor61.

The current source transistor61has a drain connected to the vertical signal line210, and a source being grounded, and forms the current source60shown inFIG. 1.

A switch transistor81is the first switch section80A having a drain connected to the vertical signal line210, and a sauce connected to the signal retention section50.

The switch transistor82is the second switch section80B having a drain connected to a reference signal line271, and a sauce connected to the signal retention section50.

The above-described configuration of the reference-signal generation section70allows signal processing at the time of a reset operation in correlated double sampling (CDS) processing. Specifically, a reset signal is outputted from the reference-signal generation section70to the signal retention section50via the reference signal line271, instead of being outputted from the pixel100to the signal retention section50via the vertical signal line210.

Therefore, it is possible to allow the signal retention section50to retain a reset signal corresponding to the reset signal of the pixel100, without requiring the time to charge and discharge the vertical signal line210extending in a pixel-column direction and having a large capacity, by using the reset voltage VRST.

Here, an electric characteristic of the transistor73may be substantially identical with an electric characteristic of the amplification transistor103. For example, the difference between a threshold of the transistor73and a threshold of the amplification transistor103may be 200 mV or less.

Further, an electric characteristic of the transistor74may be substantially identical with an electric characteristic of the select transistor104. For example, the difference between a threshold of the transistor74and a threshold of the select transistor104may be 200 mV or less.

Furthermore, an electric characteristic of the transistor72may be substantially identical with an electric characteristic of the reset transistor102. For example, the difference between a threshold of the transistor72and a threshold of the reset transistor102may be 200 mV or less.

In addition, an electric characteristic of the transistor75may be substantially identical with an electric characteristic of the current source transistor61. For example, the difference between a threshold of the transistor75and a threshold of the current source transistor61may be 200 mV or less.

Moreover, to drive the reference signal line271, the reference-signal generation section70may be configured in two or more arrays, by providing a parallel connection of transistors, for example. This can reduce an output impedance of the reference-signal generation section70, and therefore, driving capability can be increased, and a noise level can be lowered.

Therefore, the circuit configuration of the reference-signal generation section70and the circuit configuration of the pixel100excluding the photoelectric conversion element101can be substantially identical. In other words, the circuit configuration of the reference-signal generation section70is a replica of the source follower circuit in the pixel100. Accordingly, a reset signal voltage outputted from the reference-signal generation section70can be substantially identical with a reset signal voltage outputted from the pixel100by turning on the reset transistor102. Hence, it is possible to execute the CDS processing at the signal retention section50, without resetting the potential of the charge storage section105of the pixel100, and therefore, high-speed and high-accuracy nondestructive reading is achievable.

The reset operation performed by the reference-signal generation section70will be described in detail later, by usingFIGS. 5 and 6.

FIG. 3is a diagram showing an example of a circuit configuration of each of a pixel and a reference-signal generation section according to a modification of the first embodiment. Only the circuit configuration of the reference-signal generation section is different, as compared with the circuit configuration of each of the pixel and the reference-signal generation section shown inFIG. 2. Therefore, the point different from the circuit configuration shown inFIG. 2will be mainly described below.

A reference-signal generation section71includes the transistors73to75, but not the transistor72supplying the reset voltage VRSTto the gate of the transistor73. A bias voltage VBIASis supplied to the gate of the transistor73from a bias-voltage supply line.

According to the configuration of the reference-signal generation section71in the present modification, the circuit configuration of the reference-signal generation section71and the circuit configuration of the pixel100excluding the photoelectric conversion element101can be substantially identical. Therefore, a reset signal voltage outputted from the reference-signal generation section71can be substantially identical with a reset signal voltage outputted from the pixel100. Accordingly, it is possible to execute the CDS processing at the signal retention section50without resetting the potential of the charge storage section105of the pixel100, and therefore, high-speed and high-accuracy nondestructive reading is achievable.

As compared with the reference-signal generation section70, the reference-signal generation section71can supply a more stable reset signal, because a constant voltage is applied to the gate of the transistor73. In contrast, in the reference-signal generation section70, the transistor72corresponding to the reset transistor102is provided and therefore, when the reset transistor102is in an OFF state, the gate of the transistor73is in a floating state and susceptible to noise. However, when the reset transistor102is in the OFF state, a reset signal reflecting an offset by capacitive coupling can be reproduced, and in this respect, higher-accuracy CDS processing can be realized.

FIG. 4is a diagram showing an example of a circuit configuration of the signal retention section and a peripheral part thereof according to the first embodiment. A signal retention circuit50A shown inFIG. 4is disposed corresponding to the vertical signal line210, and connected to the vertical signal line210via the switch transistor81as well as being connected to the reference signal line271via the switch transistor82. The signal retention circuit50A is provided as each of signal retention circuits50A disposed corresponding to the respective vertical signal lines210, and the signal retention circuits50A form the signal retention section50.

The signal retention circuit50A includes an input capacitor51, transistors52to54, and a signal retention capacitor55. The signal retention circuit50A thus configured can cause the signal retention capacitor55to retain a pixel signal voltage outputted from the pixel100via the vertical signal line210, and a reset signal voltage outputted from the reference-signal generation section70via the reference signal line271. When the transistor54is brought to an ON state by the control of the horizontal scanning section40, a CDS pixel signal, which is a differential voltage between the above-described pixel signal voltage and the above-described reset signal voltage, is sequentially transferred to a horizontal signal line254in a horizontal direction, and then outputted to the output circuit (not shown).

Details of a CDS operation by the signal retention circuit50A will be described later, usingFIG. 5.

FIG. 5is an operation timing chart for describing the CDS processing for a pixel signal in each of the imaging device according to the first embodiment and a conventional imaging device.FIG. 5shows a voltage level of each of a control signal SEL for controlling a conduction state of the select transistor104, a control signal S1for controlling a conduction state of the switch transistor81, a control signal N1for controlling a conduction state of the switch transistor82, an input terminal OUT1of the signal retention circuit50A, a control signal HSEL for controlling a conduction state of the transistor54, a control signal NCSH for controlling a conduction state of the transistor53, a control signal NCCL for controlling a conduction state of the transistor52, a connection terminal OUT2of the transistors53and54as well as the signal retention capacitor55, a control signal SEL in a conventional method, a control signal RST in the conventional method, and an input terminal OUT1in the conventional method, in this order from the top.

First, a reading operation (a destructive reading operation) in the conventional method will be described.

At a time T1, a vertical scanning section changes the control signal SEL to a high level, thereby bringing a select transistor104to an ON state. At the same time, control signals NCSH and NCCL are each changed to a high level, so that transistors53and52are each brought to an ON state. As a result, the potential of the input terminal OUT1converges to a pixel signal voltage, and the potential of a connection terminal OUT2is clamped (converges) to a reference voltage VREF.

Next, at a time T2, the control signal NCCL is changed to a low level, so that the transistor52is brought to an OFF state. As a result, an input capacitor51retains the pixel signal voltage.

Next, at a time T3, the vertical scanning section changes the control signal RST to a high level, thereby bringing a reset transistor102to an ON state. As a result, the potential of a charge storage section105is reset by a reset voltage VRST.

Next, at a time T5, the vertical scanning section changes the control signal RST to a low level, thereby bringing the reset transistor102to an OFF state. As a result, the reset voltage VRSTof the charge storage section105is transmitted to the input terminal OUT1via a vertical signal line210, and the potential of the connection terminal OUT2converges to a differential voltage that is a difference between a pixel signal voltage and a reset signal voltage. Here, in the reading operation in the conventional method, a period from the time when the charge storage section105is changed to have the reset voltage VRSTuntil the potential of the input terminal OUT1converges to the reset voltage VRSTis a period P2. The period P2depends on a time constant of the vertical signal line210transmitting the reset voltage VRST.

Next, at a time T6, the control signal NCSH is changed to a low level, to bring the transistor53to an OFF state. As a result, a CDS pixel signal that is the above-described differential voltage is retained in the signal retention capacitor55.

Next, at a time T8, a horizontal scanning section40changes a control signal HSEL to a high level, thereby bringing a transistor54to an ON state. As a result, the CDS pixel signal that is the above-described differential voltage is read out to a horizontal signal line254.

Here, the reading operation (the nondestructive reading operation) according to the present embodiment will be described.

At a time T1, the vertical scanning section30changes the control signal SEL to a high level, thereby bringing the select transistor104to an ON state. At the same time, the control signals S1, NCSH, and NCCL are each changed to a high level, so that the switch transistor81, the transistor53, and the transistor52are each brought to an ON state. As a result, the potential of the input terminal OUT1converges to a pixel signal voltage, and at the same time, the potential of the connection terminal OUT2is clamped (converges) to a reference voltage VREF.

Next, at a time T2, the control signal NCCL is changed to a low level, to bring the transistor52to an OFF state. As a result, the potential of the connection terminal OUT2converges from the reference voltage VREFto the pixel signal voltage.

Next, at a time T3, the control signal S1is changed to a low level, to bring the switch transistor81to an OFF state.

Next, at a time T4, the control signal N1is changed to a high level, to bring the switch transistor82to an ON state. As a result, the reset voltage VRSToutputted from the reference-signal generation section70is transmitted to the input terminal OUT1via the reference signal line271. Here, in the reading operation according to the present embodiment, a period from the time when the switch transistor82is brought to the ON state until the potential of the input terminal OUT1converges to the reset voltage VRSTis a period P1. The period P1depends on a time constant of the reference signal line271transmitting the reset voltage VRST.

Next, at a time T6, the control signal NCSH is changed to a low level, to bring the transistor53to an OFF state. As a result, the potential of the connection terminal OUT2converges to a differential voltage that is a difference between a pixel signal voltage and a reset signal voltage.

Next, at a time T8, the horizontal scanning section40changes the control signal HSEL to a high level, thereby bringing the transistor54to an ON state. As a result, a CDS pixel signal that is the above-described differential voltage is read to the horizontal signal line254.

In the CDS reading operation described above, a period until the potential of the input terminal OUT1converges to the level of the reset signal voltage determines a CDS reading speed. In the conventional CDS reading operation, the period P2depends on the time constant of the vertical signal line210. In contrast, in the reading operation according to the present embodiment, the period P1depends on the time constant of the reference signal line271. The vertical signal lines210each extend along a pixel column within a pixel region, and are arranged corresponding to the number of pixel columns, and thus each have limited wiring thickness and width. In contrast, only at least one or more of the reference signal line271may be provided, and besides, an arrangement layout of the reference-signal generation section70has flexibility. For example, to drive the reference signal line271, the reference-signal generation section70may be configured in two or more arrays, by providing a parallel connection of transistors, for example. This can reduce an output impedance of the reference-signal generation section70, and therefore, driving capability can be increased, and a noise level can be lowered. Accordingly, the time constant of the reference signal line271can be set to be sufficiently smaller than the time constant of the vertical signal line210.

In the reading operation according to the present embodiment, the pixel100may be reset.

FIG. 6is an operation timing chart for describing CDS processing for a pixel signal in each of an imaging device according to a modification of the first embodiment and a conventional imaging device. The operation timing chart shown inFIG. 6is different from the operation timing chart shown inFIG. 5, in that operation timing of a control signal RST for controlling a conduction state of the reset transistor102, and a voltage of the charge storage section105are shown. Therefore, only the point different form the operation timing chart shown inFIG. 5will be described below.

When it is desired to reset the pixel100after the above-described nondestructive reading operation, the control signal RST for the reset transistor102may be changed to a high level to bring the reset transistor102to an ON state, after the control signal NCSH is changed to the low level. Desirably, timing for changing the above-described control signal RST to the high level comes immediately after the control signal SEL is changed to the low level (inFIG. 6, timing between a time T7and the time T8). The pixel100and the vertical signal line210are electrically disconnected by changing the control signal SEL to the low level. As a result, as shown inFIG. 6, the charge storage section105of the pixel100can be rapidly reset, without being affected by a load of the vertical signal line210.

The reading operation according to the present modification is not executed when the nondestructive reading is to be continued.

As described above, according to the imaging device1of the present embodiment, the above-described period P1can be shorter than the above-described period P2, and therefore, high-speed nondestructive CDS reading can be realized.

Further, in order for the signal retention section50to retain either one of a pixel signal voltage and a reset signal voltage by switching these signals, the imaging device1according to the present embodiment employs a simplified configuration. Specifically, the imaging device1employs a switch transistor switching between the vertical signal line210and the reference signal line271, without employing a configuration such as an integrator having a switched capacitor. In addition, the circuit configuration of the pixel100and the circuit configuration of the reference-signal generation section70are substantially identical. Therefore, for example, an offset voltage is not generated in an operation of switching between a pixel signal and a reset signal. Accordingly, it is possible to realize high-speed high-precision CDS nondestructive reading without limiting the dynamic range of a pixel signal. In the present embodiment, the signal retention section50exemplifies the signal processor. It is the same in the following embodiments.

Second Embodiment

In a second embodiment, a reference-signal generation section has an arrangement layout to improve the speed and the reading accuracy of reading operation.

FIG. 7is a block diagram showing an overall configuration of an imaging device according to the second embodiment. An imaging device2shown inFIG. 7includes a pixel array section10, a driving control section20, a vertical scanning section30, a horizontal scanning section40, a signal retention section50, a current source60, a reference-signal generation section170, a first switch section80A, and a second switch section80B. Further, in the pixel array section10and a peripheral region thereof, a vertical signal line210is disposed for each pixel column, and a scanning line220is disposed for each pixel row.

In the imaging device2, the reference-signal generation section170has an arrangement and a configuration different from those of the reference-signal generation section70in the imaging device1according to the first embodiment. Description of points similar to those of the imaging device1according to the first embodiment will be omitted, and the difference will be mainly described below.

The reference-signal generation section170generates a reset signal corresponding to a pixel100.

The reference-signal generation section170is disposed in a so-called vertical optical black (OB) region. In the present embodiment, the current source60is not disposed in the vertical OB region. However, the current source60may be disposed in the vertical OB region. The vertical OB region is a first peripheral region located next to an effective pixel region, on either an upper side or a lower side (or both of these sides) of the effective pixel region in a column direction. The effective pixel region is a region formed of the pixels100that each output a pixel signal corresponding to each point of a two-dimensional image formed by image formation of light incident from a subject.

The vertical OB region is a region formed of light-shielding pixels each having a structure and a circuit configuration similar to those of the pixel100, except blocking light. In the vertical OB region, the light-shielding pixels are arranged to be flush with the pixels100, and each output a black level signal for determining the brightness level of a pixel signal, by performing control and reading similar to those for the pixel100.

The reference-signal generation section170is disposed in the vertical OB region where the light-shielding pixels are disposed.

FIG. 8is a diagram showing an example of a circuit configuration of the imaging device according to the second embodiment.FIG. 8shows a specific circuit configuration corresponding to the overall configuration of the imaging device2shown inFIG. 7.

In the vertical OB region, reference-signal generation circuits170A are arranged corresponding to each pixel column, and the reference-signal generation circuits170A form the reference-signal generation section170. The reference-signal generation circuit170A is connected to a switch transistor82disposed for each pixel column. The reference-signal generation circuit170A has a circuit configuration similar to the circuit configuration of the reference-signal generation section70according to the first embodiment, and a source terminal of a transistor74is connected to a drain terminal of the switch transistor82. The circuit configuration of the reference-signal generation circuit170A may be similar to the circuit configuration of the reference-signal generation section71according to the modification of the first embodiment.

Further, the signal retention section50includes signal retention circuits50A disposed for each pixel column. The signal retention circuit50A is connected to a connection point between the switch transistor81and a switch transistor82that are disposed for each pixel column.

In the above-described configuration, the reference-signal generation section170is disposed in the vertical OB region provided next to the effective pixel region. Therefore, the reference-signal generation circuit170A and the pixel100can be closely similar to each other in terms of structure. Accordingly, a reset signal outputted from the reference-signal generation circuit170A and a reset signal outputted from the pixel100can be matched with each other with high accuracy, so that higher-accuracy nondestructive CDS operation is realized.

In addition, since the reference-signal generation circuit170A is disposed for each pixel column, a transistor75and a current source transistor61can be disposed in proximity to each other. Therefore, the reset signal is accurately supplied for each column. Moreover, a fluctuation in a ground voltage generated by a flow of an electric current from a current source transistor is independent of the position of a pixel column (e.g., a pixel center and a pixel edge, in a row (horizontal) direction), and therefore, the reset signal is accurately supplied for each column. Accordingly, a fluctuation of the reset signal outputted from the reference-signal generation section170, the fluctuation being due to a factor independent of the pixel100, can be suppressed. Therefore, a high-precision reset signal can be supplied to the signal retention section50.

It is be noted that, since the reference-signal generation circuit170A is disposed for each pixel column, power is expected to increase due to a flow of an electric current from a current source transistor of the reference-signal generation circuit170A for each pixel column. To address this situation, for example, it is desirable to add a circuit configuration for causing a flow of an electric current from the current source transistor only when necessary such as when outputting a reset signal.

Further, to reduce power consumption, a shared current source may be provided for a current source necessary for output of a pixel signal and a current source necessary for output of a reset signal. In other words, inFIG. 8, the current source transistor61and the transistor75disposed for the same pixel column may be replaced with a shared current source transistor. Specifically, in place of the current source transistor61and the transistor75, the shared current source transistor is provided, and a drain of the shared current source transistor is connected to a wiring that connects the connection point between the switch transistors81and82to an input terminal of the signal retention circuit50A. This causes an electric current to flow exclusively from the current source transistor at the time of pixel signal output or at the time of reset signal output, thereby allowing a reduction in power consumption. Further, since the current source is common to the reference-signal generation circuit170A and the pixel100being effective, it is possible to supply the same electric current, and a reset signal of the reference-signal generation circuit170A can be matched with a reset signal of the pixel100with high accuracy. Furthermore, since the transistor75serving as a current source transistor is unnecessary, it is possible to reduce the area and the electric current of the reference-signal generation circuit170A.

When the circuit configuration of the reference-signal generation circuit170A and the circuit configuration of the reference-signal generation section70are similar, it is desirable to shield the reference-signal generation circuit170A from light. This is to avoid a change in the conduction state of the transistor72serving as a reset transistor due to incident light.

In addition, the reset signal output from the reference-signal generation circuit170A via the switch transistor82may be shared between the pixel columns. In this case, to output a reset signal from a single reference-signal generation circuit170A to the pixel columns, the transistors of the reference-signal generation circuit170A may be connected in parallel to each other. An array configuration achieved by such parallel connection can lower output impedance, and therefore, it is possible to increase the driving capability and to decrease the noise level. Moreover, since the transistor75and the current source transistor61are disposed in proximity to each other, it is possible to suppress (perform averaging of) an influence with respect to a fluctuation of a ground voltage due to a flow of an electric current from a current source transistor.

Third Embodiment

In a third embodiment, a reference-signal generation section has an arrangement layout to achieve a reduction of power consumption, in addition to improvements in the speed and the reading accuracy of reading operation.

FIG. 9is a block diagram showing an overall configuration of an imaging device according to the third embodiment. An imaging device3shown inFIG. 9includes a pixel array section10, a driving control section20, a vertical scanning section30, a horizontal scanning section40, a signal retention section50, a current source60, a reference-signal generation section270, a first switch section80A, and a second switch section80B. Further, in the pixel array section10and a peripheral region thereof, a vertical signal line210is disposed for each pixel column, and a scanning line220is disposed for each pixel row.

In the imaging device3, the reference-signal generation section270has an arrangement different from that of the reference-signal generation section270in the imaging device1according to the first embodiment. Description of points similar to those of the imaging device1according to the first embodiment will be omitted, and the difference will be mainly described below.

The reference-signal generation section270generates a reset signal corresponding to a pixel100.

The reference-signal generation section270is disposed in a third peripheral region next to both of a vertical OB region and a horizontal OB region. The vertical OB region is a first peripheral region located next to an effective pixel region, on either an upper side or a lower side (or both of these sides) of the effective pixel region in a column direction. The horizontal OB region is a second peripheral region located next to the effective pixel region, on either a left side or a right side (or both of these sides) of the effective pixel region in a row direction. The effective pixel region is a region formed of the pixels100that each output a pixel signal corresponding to each point of a two-dimensional image formed by image formation of light incident from a subject.

The vertical OB region and the horizontal OB region each include light-shielding pixels that each have a structure and a circuit configuration similar to those of the pixel100, except blocking light. In the vertical OB region and the horizontal OB region, the light-shielding pixels are arranged to be flush with the pixels100, and each output a black level signal for determining the brightness level of a pixel signal, by performing control and reading similar to those for the pixel100.

The current source60is disposed corresponding to a pixel column, and connected to the vertical signal line210.

FIG. 10is a diagram showing an example of a circuit configuration of the imaging device according to the third embodiment.FIG. 10shows a specific circuit configuration corresponding to the overall configuration of the imaging device3shown inFIG. 9.

The reference-signal generation section270is disposed in the third peripheral region next to both of the vertical OB region and the horizontal OB region. The reference-signal generation section270includes transistors72to75. A source terminal of the transistor74is connected to a switch transistor82disposed for each pixel column, via a reference signal line271. The reference-signal generation section270is similar to the reference-signal generation section70according to the first embodiment.

A current source transistor62has a drain terminal connected to the vertical signal line210. The current source transistor62serves as a current source in outputting a pixel signal of the pixel100.

In the reference-signal generation section270shown inFIG. 10, one set of the transistors72to75is disposed. However, two or more reference-signal generation circuits each including the transistors72to75may be disposed according to the size of the third peripheral region, as well as according to the number of pixel columns. This makes it possible to reduce a load of the reference-signal generation section270with respect to a reset signal supplied to each pixel column, so that a stable reset signal can be outputted.

The reference-signal generation section270may have a circuit configuration similar to the circuit configuration of the reference-signal generation section71according to the modification of the first embodiment.

In the above-described configuration, the reference-signal generation section270is disposed in the third peripheral region next to the horizontal OB region and the vertical OB region. Therefore, the reference-signal generation section270and the pixel100can be closely similar to each other in terms of structure. Accordingly, a reset signal outputted from the reference-signal generation section270and a reset signal outputted from the pixel100can be matched with each other with high accuracy, so that higher-accuracy nondestructive CDS operation is realized. Further, the size of the vertical OB region can be reduced, because a reference-signal generation circuit for each pixel column is not provided. Furthermore, since the reference-signal generation section270is disposed in the third peripheral region close to the effective pixel region, the reference-signal generation section270and the pixel100can be closely similar to each other in terms of structure. Therefore, a reset signal outputted from the reference-signal generation section270and a reset signal outputted from the pixel100can be matched with each other with high accuracy, so that higher-accuracy nondestructive CDS operation is realized. Moreover, since a reference-signal generation circuit for each pixel column is not provided, an electric current can be controlled and adjusted at the reference-signal generation section270, so that power can be reduced. For example, two or more reference-signal generation circuits each including the transistors72to75may be disposed, and an electric current may be adjusted based on the number of the disposed reference-signal generation circuits.

The number of reference-signal generation circuits to be disposed is limited by a limitation to the size of the third peripheral region. Therefore, a load fluctuation of the reference-signal generation section as well as a potential fluctuation of the reference signal line271are expected to become greater, as the size as well as the number of pixels become larger. An imaging device according to a modification to be described below is configured by adding a configuration of suppressing the potential fluctuation of the reference signal line271to the imaging device3according to the third embodiment.

FIG. 11is a diagram showing an example of a circuit configuration of the imaging device according to the modification of the third embodiment. An imaging device3A shown inFIG. 11includes a reference-signal generation section having a configuration different from that in the imaging device3according to the third embodiment. Description of points similar to those of the imaging device3according to the third embodiment will be omitted, and the difference will be mainly described below.

A reference-signal generation section270A includes the transistors72to75and a buffer amplifier91. A connection configuration of these transistors72to75is similar to a connection configuration of the transistors72to75in the reference-signal generation section70. The buffer amplifier91forms a voltage-follower-type buffer circuit in which a negative input terminal and an output terminal are short-circuited.

A current source transistor61is disposed for each pixel column, and connected to the vertical signal line210.

Therefore, a reset signal voltage on the input side of the buffer amplifier91is stably transmitted to the reference signal line271on the output side, even if there is a load fluctuation. Accordingly, the capability of driving a reset signal increases, even if the number of reference-signal generation circuits included in the reference-signal generation section270A is small. Therefore, the signal retention section50can be supplied with a high-accuracy reset signal unaffected by a load fluctuation.

In the present modification, the voltage-follower-type buffer circuit in which the negative input terminal and the output terminal are short-circuited is taken as a circuit configuration that increases the capability of driving the reset signal. However, the circuit configuration that increases the capability of driving the reset signal is not limited to this type. Any type of circuit configuration may be adopted if an output impedance of a circuit is reduced and an output voltage follows an input voltage of this circuit.

Fourth Embodiment

In each of the first to third embodiments, the nondestructive CDS reading is implemented by outputting a reset signal generated in the reference-signal generation section to the signal retention section50, in place of a reset signal outputted from the pixel100to the signal retention section50via the vertical signal line210. In contrast, in a fourth embodiment, a vertical signal line is reset with a reference voltage, and a pixel signal is outputted to a signal retention section50via this vertical signal line. Nondestructive CDS reading is thereby implemented.

FIG. 12is a diagram showing an example of a circuit configuration of each of a pixel and a reference-signal generation section according to the fourth embodiment.FIG. 12shows a pixel110, a current source transistor61, a reference-signal generation section370, switch transistors81and82, a vertical scanning section30, and the signal retention section50. The imaging device according to the present embodiment includes a driving control section20and a horizontal scanning section40similar to those of the first to third embodiments, in addition to the components shown inFIG. 12.

The circuit configuration of the pixel110is different from that of the pixel100, only in that a drain of a reset transistor102is not connected to a reset power supply, while being connected to the reference-signal generation section370.

The reference-signal generation section370includes an inverting amplifier95, in addition to each component of the reference-signal generation section70according to the first embodiment. The inverting amplifier95is a buffer amplifier. In the inverting amplifier95, a positive input terminal that is a second input terminal is connected to a reference signal line295supplying a reset voltage V1, a negative input terminal that is a first input terminal is connected to a vertical signal line210, and an output terminal is connected to a drain terminal of the reset transistor102.

The switch transistor81has a drain connected to the vertical signal line210, a sauce connected to the signal retention section50, and a gate serving as a first switch section connected to a control line for supplying a control signal S1.

The switch transistor82has a drain connected to the reference signal line295, a sauce connected to the signal retention section50, and a gate serving as a second switch section connected to a control line for supplying a control signal N1.

Here, CDS nondestructive reading operation in the above-described configuration will be described.

FIG. 13is an operation timing chart for describing CDS processing for a pixel signal in each of the imaging device according to the fourth embodiment and a conventional imaging device. The CDS nondestructive reading operation according to the present embodiment will be described below with reference toFIG. 13.

First, at a time T1, the vertical scanning section30changes a control signal SEL to a high level, thereby bringing a select transistor104to an ON state. At the same time, the control signal S1as well as control signals NCSH and NCCL (shown inFIG. 4) supplied to the signal retention section50are each changed to a high level, so that the switch transistor81as well as transistors53and52(shown inFIG. 4) of the signal retention section50are each brought to an ON state. As a result, the potential of an input terminal OUT1converges to a pixel signal voltage, and at the same time, the potential of a connection terminal OUT2(shown inFIG. 4) is clamped (converges) to a reference voltage VREF(shown inFIG. 4).

Next, at a time T2, the control signal NCCL is changed to a low level, to bring the transistor52to an OFF state. As a result, the potential of the connection terminal OUT2converges from the reference voltage VREFto the pixel signal voltage.

Next, at a time T3, the control signal S1is changed to a low level, to bring the switch transistor81to an OFF state.

Next, at a time T4, the control signal N1is changed to a high level, to bring the switch transistor82to an ON state. As a result, the reset voltage V1outputted from the reference-signal generation section370is transmitted to the input terminal OUT1via the reference signal line295. Here, in the reading operation according to the present embodiment, a period from the time when the switch transistor82is brought to the ON state until the potential of the input terminal OUT1converges to the reset voltage V1is a period P1. The period P1depends on a time constant of the reference signal line295that transmits the reset voltage V1.

Accordingly, it is possible to execute the CDS processing at the signal retention section50without resetting the potential of a charge storage section105of the pixel110, and therefore, high-speed and high-accuracy nondestructive reading is achievable.

Next, at a time T6, the control signal NCSH is changed to a low level, to bring the transistor53to an OFF state. As a result, the potential of the connection terminal OUT2converges to a differential voltage that is a difference between a pixel signal voltage and a reset signal voltage.

Next, at a time T8, the horizontal scanning section40changes a control signal HSEL to a high level, thereby bringing a transistor54to an ON state. As a result, a CDS pixel signal that is the above-described differential voltage is read out to a horizontal signal line254.

Here, there will be described operation of setting the vertical signal line210at the reset signal V1of the reference-signal generation section370, in resetting the pixel110. At a time T7′ following a time T7, a control signal RST is changed to a high level, to bring the reset transistor102to an ON state. At this moment, the voltage of the negative input terminal connected to the vertical signal line210converges to the reset voltage V1of the positive input terminal connected to the reference signal line295, due to action of the inverting amplifier95.

As a result, it is possible to set the vertical signal line210at the reset signal V1of the reference-signal generation section370, in resetting the pixel110. In the present embodiment, due to the action of the inverting amplifier95, the voltage of the negative input terminal connected to the vertical signal line210can accurately converge to a voltage equivalent to the reset voltage V1of the positive input terminal connected to the reference signal line295, without depending on variations in the transistors of the pixel section and variations in the current sources. In other words, when an input voltage from the vertical signal line represents no (a dark) signal, there is no difference from a reference voltage V1, and therefore, it is possible to provide an imaging device capable of performing high-speed nondestructive reading, without impairing a dynamic range.

Moreover, in resetting the pixel110, although a period P2is necessary for resetting a pixel, it is possible to perform driving without losing a high speed (a frame rate), by, for example, causing operation in the same period as a horizontal transfer period.

Fifth Embodiment

In each of the first to third embodiments, the nondestructive CDS reading is implemented by outputting a reset signal generated in the reference-signal generation section to the signal retention section50, in place of a reset signal outputted from the pixel100to the signal retention section50via the vertical signal line210. In contrast, in a fifth embodiment, a vertical signal line is reset with a reference voltage, and a pixel signal is outputted to a signal retention section50via this vertical signal line. Nondestructive CDS reading is thereby implemented.

FIG. 14is a diagram showing an example of a circuit configuration of each of a pixel and a reference-signal generation section according to the fifth embodiment.FIG. 14shows a pixel110, a current source transistor61, a reference-signal generation section470, switch transistors81and82, a vertical scanning section30, and the signal retention section50. The imaging device according to the present embodiment includes a driving control section20and a horizontal scanning section40similar to those of the first to third embodiments, in addition to the components shown inFIG. 14.

The circuit configuration of the pixel110is different from that of the pixel100, only in that a drain of a reset transistor102is not connected to a reset power supply, while being connected to the reference-signal generation section470via the switch transistor81.

The reference-signal generation section470includes an inverting amplifier96, in addition to each component of the reference-signal generation section70according to the first embodiment. The inverting amplifier96is a buffer amplifier. In the inverting amplifier96, a positive input terminal serving as a second input terminal is connected to a reference signal line296that supplies a reset voltage V1, a negative input terminal serving as a first input terminal is connected to a vertical signal line210via the switch transistor82, and an output terminal is connected to a drain of the reset transistor102via the switch transistor81. Further, the negative input terminal and the output terminal of the inverting amplifier96are connected to each other via a switch transistor83.

The switch transistor81is a first switch transistor having a drain connected to the drain of the reset transistor102, a sauce connected to the output terminal of the inverting amplifier96, and a gate connected to a control line that supplies a control signal S1.

The switch transistor82is a second switch transistor having a drain connected to the vertical signal line210, a sauce connected the negative input terminal of the inverting amplifier96and one end of the switch transistor83, and a gate connected to a control line that supplies a control signal S1.

The switch transistors81and82form a first switch section.

The switch transistor83is a second switch section in which one of a source and a drain is connected to the negative input terminal of the inverting amplifier96and the sauce of the switch transistor82, and the other of the source and the drain is connected to the output terminal of the inverting amplifier96and the source of the switch transistor81.

Here, CDS nondestructive reading operation in the above-described configuration will be described.

FIG. 15is an operation timing chart for describing CDS processing for a pixel signal in each of the imaging device according to the fifth embodiment and a conventional imaging device. The CDS nondestructive reading operation according to the present embodiment will be described below with reference to FIG.15.

First, at a time T1, the vertical scanning section30changes a control signal SEL to a high level, thereby bringing a select transistor104to an ON state. At the same time, the control signal S1as well as control signals NCSH and NCCL (shown inFIG. 4) supplied to the signal retention section50are each changed to a high level, so that the switch transistors81and82as well as transistors53and52(shown inFIG. 4) are each brought to an ON state. As a result, the potential of an input terminal OUT1converges to a pixel signal voltage, and at the same time, the potential of a connection terminal OUT2(shown inFIG. 4) is clamped (converges) to a reference voltage VREF(shown inFIG. 4).

Next, at a time T2, the control signal NCCL is changed to a low level, to bring the transistor52to an OFF state. As a result, the potential of the connection terminal OUT2converges from the reference voltage VREFto the pixel signal voltage.

Next, at a time T3, the control signal S1is changed to a low level, to bring each of the switch transistors81and82to an OFF state.

Next, at a time T4, the control signal N1is changed to a high level, to bring the switch transistor83to an ON state. As a result, the negative input terminal and the output terminal of the inverting amplifier96are connected, so that the inverting amplifier96can operate as a voltage follower circuit. Therefore, the reset voltage V1outputted from the reference-signal generation section470is transmitted to the positive input terminal of the inverting amplifier96via the reference signal line296, so that the reset voltage V1is transmitted to the input terminal OUT1via the inverting amplifier96. Here, in the reading operation according to the present embodiment, a period from the time when the switch transistor82is brought to the ON state until the potential of the input terminal OUT1converges to the reset voltage V1is a period P1. The period P1depends on a time constant of the reference signal line296that transmits the reset voltage V1.

Therefore, it is possible to execute the CDS processing at the signal retention section50without resetting the potential of a charge storage section105of the pixel110, and therefore, high-speed and high-accuracy nondestructive reading is achievable.

Next, at a time T6, the control signal NCSH is changed to a low level, to bring the transistor53to an OFF state. As a result, the potential of the connection terminal OUT2converges to a differential voltage that is a difference between a pixel signal voltage and a reset signal voltage.

Next, at a time T8, the horizontal scanning section40changes a control signal HSEL to a high level, thereby bringing a transistor54to an ON state. As a result, a CDS pixel signal that is the above-described differential voltage is read out to a horizontal signal line254.

Here, there will be described operation of setting the vertical signal line210at a reset signal V1of the reference-signal generation section370, in resetting the pixel110. At a time T7′ following a time T7, a control signal RST is changed to a high level, to bring the reset transistor102to an ON state. Further, the control signal S1is changed to the high level to bring each of the switch transistors81and82to the ON state, and the control signal N1is changed to a low level to bring the switch transistor83to an OFF state. The voltage of the negative input terminal connected to the vertical signal line210converges to the reset voltage V1of the positive input terminal connected to the reference signal line296, due to action of the inverting amplifier95.

As a result, it is possible to set the vertical signal line210at the reset signal V1of the reference-signal generation section470, in resetting the pixel110. In the present embodiment, due to the action of the inverting amplifier96, the voltage of the negative input terminal connected to the vertical signal line210can accurately converge to a voltage equivalent to the reset voltage V1of the positive input terminal connected to the reference signal line296, without depending on variations in the transistors of the pixel section and variations in the current sources. In the present embodiment, it is possible to set the reset signal V1at the negative input terminal of the inverting amplifier96, both at the time of setting the reset signal V1in resetting between the time T5and the time T6, and at the time of setting the reset signal V1in resetting the pixel section at the time T7′. Therefore, it is possible to eliminate an offset difference in the reset signal V1. In other words, when an input voltage from the vertical signal line represents no (a dark) signal, there is no difference from a reference voltage V1, and therefore, it is possible to provide an imaging device capable of performing high-speed nondestructive reading, without impairing a dynamic range.

Moreover, in resetting the pixel110, although a period P2is necessary for resetting a pixel, it is possible to perform driving without losing a high speed (a frame rate), by, for example, causing operation in the same period as a horizontal transfer period.

Sixth Embodiment

The imaging device according to each of the first to fifth embodiments can be applied to a digital-output-type image sensor.

FIG. 16is a block diagram showing an overall configuration of an imaging device according to a sixth embodiment. An imaging device4shown inFIG. 16is a digital-output-type image sensor, and includes a pixel array section510, a vertical scanning section530, a timing control circuit520, an analog/digital (AD) converter circuit540, a current source560, a reference-signal generation section570, a first switch section581, a second switch section582, an AD-reference-signal generation section590, and an output interface (I/F)546.

The pixel array section510has a configuration similar to that of the pixel array section10according to the first embodiment. Each pixel is connected to a scanning line controlled by the vertical scanning section530, and to a vertical signal line610transmitting a pixel signal to the A/D converter circuit540.

The timing control circuit520generates various internal clocks by receiving a master clock CLKO and data DATA via an external terminal, thereby controlling the vertical scanning section530, the reference-signal generation section570, the AD-reference-signal generation section590, the first switch section581, and the second switch section582.

The AD-reference-signal generation section590supplies a reference voltage RAMP for AD conversion, to a column AD circuit541of the A/D converter circuit540.

The A/D converter circuit540includes the column AD circuit541as each of column AD circuits541provided for the respective pixel columns. The column AD circuit541converts an analog voltage signal into a digital signal, by using the reference voltage RAMP generated in the AD-reference-signal generation section590. This analog voltage signal is each of a pixel signal outputted from a pixel100and a reset signal outputted from the reference-signal generation section570.

The column AD circuit541includes a voltage comparison section542, a counter section543, a switch544, and a memory545. The voltage comparison section542compares the analog pixel signal obtained from the pixel100via the vertical signal line610, with the reference voltage RAMP. In addition, the voltage comparison section542compares the analog reset signal obtained from the reference-signal generation section570via a reference signal line571, with the reference voltage RAMP. The memory545holds the time consumed up to completion of comparison processing by the voltage comparison section542and a result of counting performed using the counter section543.

The reference voltage RAMP, which is a stepwise voltage generated in the AD-reference-signal generation section590, is inputted to one of input terminals of the voltage comparison section542, as a voltage common to input terminals of other voltage comparison sections542. The pixel signal from the pixel100or the reset signal from the reference-signal generation section570is inputted to the other one of the input terminals of the voltage comparison section542. An output signal of the voltage comparison section542is supplied to the counter section543.

Simultaneously with the supply of the reference voltage RAMP to the voltage comparison section542, the column AD circuit541starts counting with a clock signal, and continues the counting until obtaining a pulse signal by comparing the inputted analog voltage signal with the reference voltage RAMP, thereby performing the AD conversion.

The column AD circuit541also performs processing of determining a difference between a reset signal level (a noise level) and a pixel signal level, in addition to the AD conversion. A noise signal component can be thereby removed from a voltage signal.

The column AD circuit541is configured to extract only a true signal level by counting down the reset signal level, and counting up the pixel signal level. The signal digitized in the column AD circuit541is inputted to the output UF546via a horizontal signal line547.

In the imaging device4having the above-described configuration, a pixel signal is outputted to the A/D converter circuit540by a change of the first switch section581to a conduction state, and then a reset signal from the reference-signal generation section570is outputted to the A/D converter circuit540by a change of the second switch section582to a conduction state.

Therefore, it is possible to allow the signal retention section50to retain a reset signal corresponding to the reset signal of a pixel, without requiring the time to charge and discharge the vertical signal line610extending in a pixel-column direction and having a large capacity, by using a reset voltage VRST.

In addition, a circuit configuration of the reference-signal generation section570and a circuit configuration of the pixel excluding a photoelectric conversion element are substantially identical. Therefore, a reset signal voltage outputted from the reference-signal generation section570can be substantially identical to a reset signal voltage outputted from the pixel by bringing a reset transistor102to an ON state. Accordingly, it is possible to execute CDS processing at the A/D converter circuit540without resetting the pixel, so that high-speed and high-accuracy nondestructive reading of a digital output signal can be performed.

Seventh Embodiment

In the imaging device according to each of the first to sixth embodiments, the configuration for executing the nondestructive CDS processing, including the reference-signal generation section, the current source, the switch section, and the signal retention section, is disposed around the effective pixel region where the pixels are disposed. Adding this configuration increases a chip size of the imaging device, and limits a finer pixel pitch that accompanies an increase in the number of pixels.

An imaging device according to a seventh embodiment downsizes the above-described configuration for executing the nondestructive CDS processing.

FIG. 17is a block diagram showing an overall configuration of the imaging device according to the seventh embodiment. An imaging device5shown inFIG. 17includes a pixel array section10, a driving control section20, a vertical scanning section30, a horizontal scanning section40, a signal retention section50, a current source60, a reference-signal generation section70, a first switch section80A, a second switch section80B, and a multiplexer150. Further, in the pixel array section10and a peripheral region thereof, a vertical signal line210is disposed for each pixel column, and a scanning line220is disposed for each pixel row.

A configuration of the imaging device5according to the present embodiment is different from that of the imaging device1according to the first embodiment, in that the multiplexer150is provided. Description of points similar to those of the imaging device1according to the first embodiment will be omitted, and the difference will be mainly described below.

The multiplexer150has two input terminals and one output terminal, and is disposed for every two adjacent pixel columns. The two input terminals are connected to two adjacent vertical signal lines210, respectively, and the output terminal is connected to the current source60and the first switch section80A that are disposed for the every two adjacent pixel columns.

The reference-signal generation section70is connected to the second switch section80B disposed for the above-described every two adjacent pixel columns.

The signal retention section50includes a signal retention circuit50A disposed for the above-described every two adjacent pixel columns. An input terminal of the signal retention circuit50A is connected to a connection point between the first switch section80A and the second switch section80B.

In the above-described configuration, the imaging device5performs, for example, the following operation.

First, the multiplexer150is caused to select connection with the vertical signal line210in every odd-numbered column.

Next, the first switch section80A is caused to conduct, so that a pixel signal is outputted from a pixel100in an odd-numbered column to the signal retention circuit50A.

Next, the second switch section80B is caused to conduct, so that a reset signal is outputted from the reference-signal generation section70to the signal retention circuit50A.

Next, the signal retention circuit50A generates a CDS pixel signal of the odd-numbered pixel column from the pixel signal and the reset signal described above, and retains the generated CDS pixel signal.

Next, the multiplexer150is caused to select connection with the vertical signal line210in an even-numbered column.

Next, the first switch section80A is caused to conduct, so that a pixel signal is outputted from the pixel100in the even-numbered column to the signal retention circuit50A.

Next, the second switch section80B is caused to conduct, so that a reset signal is outputted from the reference-signal generation section70to the signal retention circuit50A.

Next, the signal retention circuit50A generates a CDS pixel signal of the even-numbered pixel column from the pixel signal and the reset signal described above, and retains the generated CDS pixel signal.

The horizontal scanning section40reads the CDS pixel signal of the odd-numbered pixel column and the CDS pixel signal of the even-numbered pixel column, from the signal retention section50.

According to the above-described configuration, to execute nondestructive CDS reading operation, the current source60, the first switch section80A, the second switch section80B, and the signal retention circuit50A may be disposed for every two pixel columns, not for each pixel column. Therefore, it is possible to reduce a circuit area provided around the pixel array section10, so that the imaging device can be downsized.

The multiplexer150according to the present embodiment may be disposed on the vertical signal line210, in the configuration in which the reference-signal generation circuit170A is disposed for each pixel column as in the imaging device2according to the second embodiment. This can halve the number of the reference-signal generation circuits170A to be disposed. In this case, likewise, it is possible to reduce a circuit area provided around the pixel array section10, so that the imaging device can be downsized.

Moreover, the number of pixel columns selectable by the multiplexer150is not limited to two, and tree or more pixel columns may be connected depending on the signal retention capability of the signal retention circuit50A.

According to the above-described embodiments of the present disclosure, the imaging device includes the pixel array section10that includes the pixels100arranged in rows and columns, the vertical signal line210that is provided for each pixel column, the signal retention section50that outputs a differential signal corresponding to a difference between a pixel signal outputted from each of the pixels100and a reset signal corresponding to a reset voltage of the pixels100, the first switch section80A that is connected between the vertical signal line210and the signal retention section50and switches between input and interruption of the pixel signal from each of the pixels100to the signal retention section50, the reference-signal generation section70that generates the reset signal, and the second switch section80B that is connected between the reference-signal generation section70and the signal retention section50and switches between input and interruption of the reset signal from the reference-signal generation section70to the signal retention section50.

Therefore, it is possible to allow the signal retention section50to retain a reset signal corresponding to the reset signal of the pixel100, without requiring the time to charge and discharge the vertical signal line210extending in a pixel-column direction and having a large capacity by using the reset voltage. Accordingly, high-speed nondestructive reading is allowed.

The imaging device may further include the driving control section20that causes the signal retention section50to retain the pixel signal by bringing the first switch section80A to a conduction state and the second switch section80B to a non-conduction state, and may allow input of the reset signal to the signal retention section50by bringing the first switch section80A to a non-conduction state and the second switch section80B to a conduction state in a state where the pixel signal is retained by the signal retention section50, thereby allowing the signal retention section50to retain the differential signal.

Therefore, it is possible to execute the CDS processing at the signal retention section50without resetting the potential of the charge storage section105of the pixel110, and therefore, high-speed and high-accuracy nondestructive reading is achievable.

Further, the pixels100may each include the photoelectric conversion element101that performs photoelectric conversion of incident light into signal charge, the charge storage section105that is connected to the photoelectric conversion element101and stores the signal charge, the amplification transistor103that includes the gate being connected to the charge storage section105and the drain being supplied with a power supply voltage and outputs a pixel signal corresponding to an amount of the signal charge, the reset transistor102that includes the drain being supplied with a reset voltage and the source being connected to the charge storage section105and resets the potential of the charge storage section105, and the select transistor104that includes the drain being connected to the source of the amplification transistor103and the source being connected to the vertical signal line210and selectively outputs the pixel signal from the amplification transistor103, and the reference-signal generation section70includes the transistor73that includes the drain being supplied with the power supply voltage, and the transistor74that includes the drain being connected to the source of the transistor73and the source being connected to the second switch section80B.

Furthermore, the transistor73may have an electric characteristic substantially identical to an electric characteristic of the amplification transistor103, and the transistor74may have an electric characteristic substantially identical to an electric characteristic of the select transistor104.

The reference-signal generation section70may further include the transistor72that includes the drain being supplied with the reset voltage, and the source being connected to the gate of the transistor73.

Further, the transistor72may have an electric characteristic substantially identical to an electric characteristic of the reset transistor102.

Therefore, the circuit configuration of the reference-signal generation section70and the circuit configuration of the pixel100excluding the photoelectric conversion element101can be substantially identical. In other words, the circuit configuration of the reference-signal generation section70is a replica of the source follower circuit in the pixel100. Accordingly, a reset signal voltage outputted from the reference-signal generation section70can be substantially identical with a reset signal voltage outputted from the pixel100upon turning on of the reset transistor102. Hence, it is possible to execute the CDS processing at the signal retention section50without resetting the potential of the charge storage section105of the pixel100, and therefore, high-speed and high-accuracy nondestructive reading is achievable.

One terminal of the first switch section80A may be connected to the vertical signal line210, and one terminal of the second switch section80B may be connected to the source of the transistor74, and the imaging device may further include the current source transistor62that includes the drain being connected to the other terminal of the first switch section80A and the other terminal of the second switch section80B, and the source being grounded.

Therefore, the current source transistor62serves as a current source in outputting a pixel signal of the pixel100when the first switch section80A is in the conduction state, and serves as a current source in outputting a reset signal of the reference-signal generation section when the second switch section80B is in the conduction state. Accordingly, it is possible to reduce the current source transistors in the reference-signal generation section and therefore, it is easy to reduce the area of the reference-signal generation section.

Further, the pixels100may form the effective pixel region where the pixels100each generate a pixel signal by receiving incident light, in the pixel array section10, and the reference-signal generation section170may be disposed in the first peripheral region next to the effective pixel region in the column direction.

When the reference-signal generation section170is thus disposed in the first peripheral region provided next to the effective pixel region, the reference-signal generation circuit170A and the pixel100can be closely similar to each other in terms of structure. Therefore, a reset signal outputted from the reference-signal generation circuit170A and a reset signal outputted from the pixel100can be matched with each other with high accuracy, so that higher-accuracy nondestructive CDS operation is realized.

In addition, since the reference-signal generation circuit170A can be disposed for each pixel column, it is possible to reduce the distance between the reference-signal generation section170and the second switch section80B, and it is also possible to distribute a power load of the reference-signal generation section170among the reference-signal generation circuits170A. Accordingly, it is possible to suppress a fluctuation of a reset signal outputted from the reference-signal generation section170due to a factor independent of the pixel100, so that a high-precision reset signal can be supplied to the signal retention section50.

Furthermore, the pixels100may form the effective pixel region where the pixels100each generate a pixel signal by receiving incident light, in the pixel array10, and the reference-signal generation section270may be disposed in the third peripheral region next to both of the first peripheral region next to the effective pixel region in the column direction, and the second peripheral region next to the effective pixel region in the row direction.

Therefore, the reference-signal generation section270and the pixel100can be closely similar to each other in terms of structure. Accordingly, a reset signal outputted from the reference-signal generation section270and a reset signal outputted from the pixel100can be matched with each other with high accuracy, so that higher-accuracy nondestructive CDS operation is realized.

Furthermore, in the reference-signal generation section270A, the buffer amplifier91may be inserted between an output terminal for the reset signal and the second switch section80B.

Therefore, a reset signal voltage on the input side of the buffer amplifier91is stably transmitted to the reference signal line271on the output side, even if there is a load fluctuation. Accordingly, the capability of driving a reset signal increases even if the number of reference-signal generation circuits included in the reference-signal generation section270A is small, and therefore, the signal retention section50can be supplied with a high-accuracy reset signal unaffected by a load fluctuation.

Further, the pixels110each include the photoelectric conversion element101that performs photoelectric conversion of incident light into signal charge, the charge storage section105that is connected to the photoelectric conversion element101and stores the signal charge, the amplification transistor103that includes the gate being connected to the charge storage section105and the drain being supplied with a power supply voltage and outputs a pixel signal corresponding to an amount of the signal charge, the reset transistor102that includes the source being connected to the charge storage section105and resets the potential of the charge storage section105, and the select transistor104that includes the drain being connected to the source of the amplification transistor103and the source being connected to the vertical signal line210and selectively outputs the pixel signal from the amplification transistor103, the reference-signal generation section370includes the transistor73that includes the drain being supplied with the power supply voltage, the transistor74that includes the drain being connected to the source of the transistor73and the source being connected to the second switch section80B, and the inverting amplifier95that includes the first input terminal, the second input terminal, and the output terminal, the first input terminal is connected to the vertical signal line210and the first switch section80A, the second input terminal is connected to the second switch section80B and receives the reset voltage V1that is the reset signal, and the output terminal is connected to the drain of the reset transistor102.

Therefore, it is possible to execute the CDS processing at the signal retention section50without resetting the potential of the charge storage section105of the pixel110, and thus, high-speed and high-accuracy nondestructive reading is achievable. In addition, it is possible to set the vertical signal line210at the reset signal V1of the reference-signal generation section370, in resetting the pixel110. Due to the action of the inverting amplifier95, the voltage of the negative input terminal connected to the vertical signal line210can accurately converge to a voltage equivalent to the reset voltage V1of the positive input terminal connected to the reference signal line295, without depending on variations in the transistors of the pixel110and variations in the current sources. In other words, when an input voltage from the vertical signal line210represents no (a dark) signal, there is no difference from the reference voltage V1, and therefore, it is possible to provide an imaging device capable of performing high-speed nondestructive reading, without impairing a dynamic range.

Furthermore, the pixels110each include the photoelectric conversion element101that performs photoelectric conversion of incident light into signal charge, the charge storage section105that is connected to the photoelectric conversion element101and stores the signal charge, the amplification transistor103that includes the gate being connected to the charge storage section105and the drain being supplied with a power supply voltage and outputs a pixel signal corresponding to an amount of the signal charge, the reset transistor102that includes the source being connected to the charge storage section105and resets the potential of the charge storage section105, and the select transistor104that includes the drain being connected to the source of the amplification transistor103and the source being connected to the vertical signal line210and selectively outputs the pixel signal from the amplification transistor103, the first switch section80A includes the switch transistor81and the switch transistor82, the reference-signal generation section470includes the transistor73that includes the drain being supplied with the power supply voltage, the transistor74that includes the drain being connected to the source of the transistor73, and the inverting amplifier96that includes the first input terminal, the second input terminal, and the output terminal, the switch transistor81includes the drain being connected to the drain of the reset transistor102, the switch transistor82includes the drain being connected to the vertical signal line210, the first input terminal is connected to the source of the switch transistor82and one end of the second switch section80B, the second input terminal receives a reset voltage that is the reset signal, and the output terminal is connected to the source of the switch transistor81as well as the other end of the second switch section80B.

Therefore, it is possible to execute the CDS processing at the signal retention section50without resetting the potential of the charge storage section105of the pixel101, and thus, high-speed and high-accuracy nondestructive reading is achievable. In addition, it is possible to set the vertical signal line210at the reset signal V1of the reference-signal generation section470, in resetting the pixel110. Due to the action of the inverting amplifier96, the voltage of the negative input terminal connected to the vertical signal line210can accurately converge to a voltage equivalent to the reset voltage V1of the positive input terminal connected to the reference signal line296, without depending on variations in the transistors of the pixel110and variations in the current sources. Moreover, it is possible to eliminate an offset difference in the reset signals V1. In other words, when an input voltage from the vertical signal line210represents no (a dark) signal, there is no difference from the reference voltage V1, and therefore, it is possible to provide an imaging device capable of performing high-speed nondestructive reading, without impairing a dynamic range.

The imaging device may further include the multiplexer150that is disposed between the vertical signal lines210and the first switch section80A, and selectively switches connection between one of the vertical signal lines210to the first switch section80A, and the first switch section80A and the second switch section80B may be each disposed corresponding to the multiplexer150.

Therefore, to execute the nondestructive CDS reading operation, the current source60, the first switch section80A, the second switch section80B, and the signal retention circuit50A may not be disposed for each pixel column, and may be disposed for every two or more pixel columns. Accordingly, it is possible to reduce the circuit area provided around the pixel array section10, so that the imaging device can be downsized.

Other Embodiments

The imaging devices according to the first to seventh embodiments of the present disclosure have been described, but the present disclosure is not limited to the first to seventh embodiments. Various modifications conceived by a person skilled in the art without departing from the gist of the present disclosure are also included in the scope of the present disclosure. Further, any components in two or more of the embodiments may be freely combined without departing from the gist of the present disclosure.

The imaging device according to each of the embodiments described above is typically implemented as a large scale integration (LSI) that is an integrated circuit. These imaging devices may be each integrated into one chip, and may be each integrated partially or entirely into one chip.

The integrated circuit is not limited to LSI, and may be implemented by an exclusive circuit or a general-purpose processor. A field programmable gate array (FPGA) capable of being programmed after LSI manufacturing, or a reconfigurable processor capable of reconfiguring connection and setting for circuit cells in an LSI may be used.

Further, at least some of the functions of the imaging devices according to the embodiments described above may be combined.

The numbers used above are each taken as an example for specifically describing the present disclosure, and the present disclosure is not limited to these numbers.

In each of the embodiments described above, having the select transistor104and the transistor74is taken as an example. However, a pixel configuration without having the select transistor104and the transistor74may be used, for example, by performing pulse driving of the power supply of the amplification transistor103and the transistor73.

In each of the embodiments described above, using an Nch-type metal oxide semiconductor (MOS) transistor is taken as an example. However, a Pch-type transistor may be used.

Further, in the above description, using the MOS transistor is taken as an example, but other type of transistor may be used.

In each of the embodiments described above, performing the operation of resetting the signal retention section50after retaining a pixel signal is taken as an example. However, the pixel signal may be retained after the signal retention section50is reset. Including such a modification, various modifications conceived by a person skilled in the art without departing from the gist of the present disclosure are also included in the scope of the present disclosure.

Furthermore, various modifications conceived by a person skilled in the art based on the present embodiments are also included in the scope of the present disclosure, as long as these modifications do not depart from the gist of the present disclosure.

The imaging devices of the present disclosure is capable of performing high-speed nondestructive reading, and applicable to a digital still camera, a video camera, a vehicle-mounted camera, a surveillance camera, a medical camera, and the like.