Organic light emitting diode display device and method for driving the same

The present invention an organic light emitting diode display device includes a display panel having a plurality of pixel regions, a gate driving unit for driving gate lines and light emitting control lines of the display panel, a data driving unit for driving data lines of the display panel, a power supply unit for supplying first and second power signals to power lines of the display panel as well as a compensating voltage to a compensating power line, and a timing controller for controlling the gate and data driving units for displaying an image with a data voltage compensated with the compensating voltage and controlling the power supply unit to supply the compensating voltage after converting a level of the compensating voltage just before display of a first image on the display panel at an initial driving.

CROSS REFERENCE TO RELATED APPLICATION

This application claims the benefit of the Patent Korean Application No. 10-2010-0114939, filed on Nov. 18, 2010, which is hereby incorporated by reference as if fully set forth herein.

BACKGROUND OF THE DISCLOSURE

1. Field of the Disclosure

The present invention relates to an organic light emitting diode display device and a method for driving the same which can prevent drive error that is liable to take place at initial turning on of the organic light emitting diode display device for improving reliability of the same, and in which an image voltage charged to each of unit pixels is compensated to improve a display picture quality, further.

2. Discussion of the Related Art

As flat display devices on the rise currently, there are liquid crystal display devices, field emission display devices, plasma display panels, organic light emitting display devices, and so on. Of the flat display devices, the organic light emitting diode display device is a spontaneous emission device which makes an organic light emitting layer to emit a light as an electron and a hole re-couple and is expected to be the next generation display device owing to high brightness, a low driving voltage and possibility of fabrication of an extra-thin device.

Each of a plurality of pixels of the OLED display device is provided with an organic light emitting diode having the organic light emitting layer between an anode and a cathode, and a pixel circuit for driving the organic light emitting diode, independently.

The pixel circuit is provided with switching transistors, capacitors, and driving transistors, principally. The switching transistor charges a data signal to the capacitor in response to a scan pulse, and the driving transistor controls current intensity being supplied to the organic light emitting diode according to a data voltage charged to the capacitor for producing gradients.

However, the organic light emitting diode display device has had defects in that the drive error takes place, in which a power source current is applied to the pixels, particularly, to the pixel circuits at the time of initial driving of the organic light emitting diode display device, making the organic light emitting diodes in the pixel to emit a light. In other words, in a normal of operation of the organic light emitting diode display device, at the time of initial driving of the organic light emitting diode display device, the power source current is supplied for driving the organic light emitting diode display device at first, and then, different control signals are generated for displaying an image on a display panel. However, a related art organic light emitting diode display device causes the drive error in which the power source current applied to the display panel at the time of initial driving is applied to the pixels, making the organic light emitting diode to emit the light. Consequently, the related art organic light emitting diode display device causes the drive error, such as blinking, at the time of the initial turning on, impairing reliability thereof.

SUMMARY OF THE DISCLOSURE

An object of the present invention is to provide an organic light emitting diode display device and a method for driving the same.

To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, an organic light emitting diode display device includes a display panel having a plurality of pixel regions, a gate driving unit for driving gate lines and light emitting control lines of the display panel, a data driving unit for driving data lines of the display panel, a power supply unit for supplying first and second power-signals to power lines of the display panel as well as a compensating voltage to a compensating power line, and a timing controller for controlling the gate and data driving units for displaying an image with a data voltage compensated with the compensating voltage, and controlling the power supply unit to supply the compensating voltage after converting a level of the compensating voltage just before display of a first image on the display panel at an initial driving.

The timing controller, at the time of initial driving of the display panel, generates and supplies a level converting control signal to the power supply unit such that the level of the compensating voltage is converted from the ground voltage level which is a level of the second power signal to a level of a preset straight polarity compensating voltage just before the image is displayed on a first horizontal line of the display panel, and the power supply unit converts the level of the compensating voltage to be supplied to the compensating power line to the ground level or the preset straight polarity level in response to the level converting control signal.

The display panel or the power supply unit further includes a compensating voltage supply unit for supplying the compensating voltage to the compensating voltage supply line after converting a compensating voltage level to the ground voltage level or the preset straight polarity compensating voltage level.

The compensating voltage supply unit is provided with NMOS and PMOS switching devices connected in series between the ground voltage application terminal and a preset straight polarity compensating voltage application terminal for supplying the compensating voltage of the preset straight polarity compensating voltage level or the ground voltage level to the compensating voltage supply line according to the level converting control signal.

The gate driving unit supplies at least one of the gate voltage and the light emitting voltage to the gate lines or the light emitting control lines after reducing application periods of the gate voltage and the light emitting voltage as much as a-preset time period for at least an initial one frame period.

In another aspect of the present invention, a method for driving an organic light emitting diode display device includes the steps of driving gate lines and light emitting control line of a display panel having a plurality of pixel regions, driving data lines of the display panel, supplying first and second power signals to power lines of the display panel as well as a compensating voltage to a compensating power line, and controlling to display an image with a data voltage compensated with the compensating voltage and controlling to supply the compensating voltage after converting a level of the compensating voltage just before display of a first image on the display panel at an initial driving.

The step of supplying the compensating voltage after converting a level of the compensating voltage includes the steps of, at the time of initial driving of the display panel, generating and supplying a level converting control signal to the power supply unit such that the level of the compensating voltage is converted from the ground voltage level which is a level of the second power signal to a level of a preset straight polarity compensating voltage just before the image is displayed on a first horizontal line of the display panel, and converting the level of the compensating voltage to be supplied to the compensating power line to the ground level or the preset straight polarity level in response to the level converting control signal.

The step of supplying the compensating voltage after converting a level of the compensating voltage includes the step of supplying the compensating voltage to the compensating voltage supply line after converting a compensating voltage level to the ground voltage level or the preset straight polarity compensating voltage level by using a compensating voltage supply unit provided to the display panel or a separate power supply unit.

The step of supplying the compensating voltage includes the step of supplying the compensating voltage of the preset straight polarity compensating voltage level or the ground voltage level to the compensating voltage supply line according to the level converting control signal by using NMOS and PMOS switching devices connected in series between the ground voltage application terminal and a preset straight polarity compensating voltage application terminal.

The method further includes the step of supplying at least one of the gate voltage and the light emitting voltage to the gate lines or the light emitting control lines after reducing application periods of the gate voltage and the light emitting voltage as much as a preset time period for at least an initial one frame period.

DESCRIPTION OF SPECIFIC EMBODIMENTS

FIG. 1illustrates a block diagram of an organic light emitting diode display device, in accordance with a preferred embodiment of the present invention. And,FIG. 2illustrates an equivalent circuit of a sub-pixel of the display panel inFIG. 1.

Referring toFIG. 1, the organic light emitting diode display device includes a display panel1having a plurality of pixel regions, a gate driving unit2for driving gate lines GL1˜GLn and light emitting control lines EL1˜ELn of the display panel1, a data driving unit3for driving data lines DL1˜DLm of the display panel1, a power supply unit4for supplying first and second'power signals VDD, and GND to power lines PL1˜PLm as well as a compensating voltage Vref to a compensating power line CPL, and a timing controller5for controlling the gate and data driving units2, and3for displaying an image with a data voltage compensated with the compensating voltage Vref and controlling the power supply unit4to supply the compensating voltage Vref after converting a level of the compensating voltage Vref just before display of a first image on the display panel1at an initial driving.

The display panel1has a matrix of pixel regions each having a plurality of sub-pixels P for displaying the image. Each of the sub-pixels P includes a light emitting cell OLD, and a cell driving unit DVD for driving the light emitting cell OLD, independently. In detail, as shown inFIG. 2, each of the sub-pixels P includes a gate line GL, a data line DL, a compensating power line CPL, a light emitting control line EL, a cell driving unit DVD, expressed as a diode in equivalency, connected to the power line PL, and a light emitting cell OLD connected between the cell driving unit DVD and the second power signal GND.

The cell driving unit DVD includes first to fifth switching devices T1˜T5, a drive switching device DT, and a storage capacitor Cst. In this instance, the first to fifth switching devices T1˜T5, and the drive switching device DT may be NMOS transistors or PMOS transistors. Hereinafter, an example will be described, in which the first to fifth switching devices T˜T5, and the drive switching device DT are the PMOS transistors.

The first switching device T1supplies a data signal Vdata from the data line DL to a first node N1in response to a low logic gate voltage from the gate line GL for charging the storage capacitor Cst.

The second switching device T2connects the gate electrode to the drain electrode of the drive switching device DT in response to a low logic gate voltage from the gate line GL for connecting the drive switching device DT in a form of a diode.

The third switching device T3connects the drain electrode of the drive switching device DT to an anode electrode of the light emitting cell OLD in response to a low logic light emitting control voltage from the light emitting control line EL. That is, the third switching device T3supplies a data current from the drive switching device DT to the light emitting cell OLD according to the low logic light emitting control voltage.

The fourth switching device T4supplies the compensating voltage Vref supplied through the compensating power line CPL to the first node N1.

The fifth switching device T5supplies the compensating voltage Vref supplied through the compensating power line CPL to a third node N3connected to the light emitting cell OLD in response to the low logic gate voltage from the gate line GL. In this instance, the fifth switching device T5, being a cell driving unit DVD stabilizing device, does not influence to a driving process even if the fifth switching device T5is not provided.

The drive switching device DT controls an intensity of a current to the light emitting cell OLD in response to a voltage at the second node N2.

The storage capacitor Cst is formed between the first and second nodes N1and N2for storage of a difference of voltages between the first and second nodes N1and N2therein, and sustains a turned on state of the drive switching device DT for a preset time period, for an example, one frame period, by using a voltage stored therein if the first switching device T1is turned off.

The light emitting cell OLD includes the anode electrode connected to the cell driving unit DVD, a cathode electrode connected to the second power source signal GND which is a low potential voltage, and an organic layer formed between the anode electrode and the cathode electrode. The light emitting cell OLD emits the light with the current from the drive switching device DT through the third switching device T3of the cell driving unit DVD.

The gate driving unit2generates gate on signals (For an example, a low logic gate voltage) in succession in response to gate control signals GVS, for an example, a gate start pulse GSP and a gate shift clock GSC, from the timing controller5, and controls a pulse width of each of the gate on signals according to a gate output enable signal GOE. Then, the gate on signals are supplied to the gate lines GL1˜GLn in succession. In this instance, in each of periods in which the gate on signals are supplied to the gate lines GL1˜GLn, a gate off voltage (For an example, a high logic gate voltage) is supplied. According to this, the gate driving unit2drives the first and second switching devices T1and T2connected to each of the gate lines GL1˜GLn. In this instance, the gate driving unit2also supplies the high logic gate voltage during a data input period in one horizontal period, and the low logic gate voltage during a scan period in the one horizontal period. In this case, in the data input period, the data voltage is supplied to the light emitting cells OLD, not during the data input period, but during the scan period.

And, the gate driving unit2generates high or low logic light emitting control voltages in succession and supplies the same to the light emitting control lines EL1˜ELn. In this instance, the light emitting control voltages forwarded in succession controls a period in which a current flows to the light emitting cell OLD, i.e., a period the image is displayed, and a period the compensating voltage Vref is supplied to the fourth switching device T4. In other words, the gate driving unit2controls an image display period and a blanking period in which a black image is displayed.

The data driving unit3converts a digital image data received from the timing controller5to an analog voltage, i.e., an analog data voltage by using a source start pulse SSP and a source shift clock SSC of the data control signals from the timing controller5. In this instance, the data driving unit3converts the digital image data to the analog data voltage by using a gamma voltage set having gamma voltages finely divided to match to gradients of the digital image data. And, the data driving unit3supplies the data voltage to the data lines DL1˜DLm in response to the source output enable SOE signal. In detail, the data driving unit3latches the digital image data received according to the SSC, and supplies one horizontal line portion of the data voltage to the data lines DL1˜DLn in every horizontal period in which the gate on signal is supplied to the gate lines GL1˜GLn in response to the SOE signal.

The power supply unit4supplies the first and second power signals VDD and GND to the power lines PL1˜PLm of the display panel1, and the compensating voltage Vref to the compensating power line CPL. The power supply unit4converts a level of the compensating voltage Vref being supplied to the compensating power line CPL in response to a level converting control signal CS from the timing controller5to a preset straight polarity level or a ground level and supplies the same.

The timing controller5aligns RGB data received from an outside with a size and resolution of the display panel1, and supplies the digital image data aligned thus to the data driving unit3. And, the timing controller5generates the gate and data control signals by using synchronizing signals received from an outside, such a dot clock DCLK, a data enable signal DE, a horizontal synchronizing signal Hsync, a vertical synchronizing signal Vsync, and supplies the gate and data control signals to the gate driving unit2and the data driving unit3, respectively.

Moreover, at the time of initial driving of the display panel1, the timing controller5generates and supplies the level converting control signal CS to the power supply unit4such that the level of the compensating voltage Vref is converted from the ground voltage level to the preset straight polarity compensating voltage Vref level just before the image is displayed on a first horizontal line of the display panel1. According to this, the power supply unit4converts the compensating voltage Vref level to the ground level or the preset straight polarity level in response to the level converting control signal CS from the timing controller5.

FIG. 3illustrates waveforms for describing a method for driving an organic light emitting diode display device in accordance with a preferred embodiment of the present invention.

A time period from a time the user turns on the organic light emitting diode display device to a time the image is displayed on the display panel1is divided into a power signal turn on period, an initial driving period t_initial, and a frame period t1˜t3.

The power signal turn on period is a most initial time period in which the user supplies the power signal for using the organic light emitting diode display device, when the power signal is supplied to, starting from the power supply unit4, the gate and data driving units2and3, and the timing controller5for the first time. In the turn on period, no signal is supplied to the display panel1.

Then, in the initial driving period t_initial, an initial driving signal Disp is supplied from the timing controller5to the data driving units2and3or the power supply unit4. In response to the initial driving signal Disp, all the data driving unit2and3and the power supply unit4are enabled. In this instance, since the display panel1has the first and second power signals VDD and GND supplied thereto, a current is liable to be supplied to the pixels to cause the drive error. As a counter measure to this, the timing controller5supplies a black data to the data driving unit3so that the black is displayed on the display panel even if the drive error takes place. And, the data driving unit3supplies a data voltage corresponding to the black data to the data lines DL1˜DLm. The gate driving unit2supplies the gate voltage and the light emitting control voltage to the gate lines GL1˜GLn and the light emitting control line EL1˜ELn so that the black data supplied to the data lines DL1˜DLm is displayed.

In the meantime, in the initial driving period t_initial, the timing controller5generates and supplies the level converting control signal CS to the power supply unit4for maintaining the compensating voltage Vref at the ground voltage level. And, the power supply unit4also maintains the compensating voltage Vref at the ground voltage level and supplies the same to the compensating power line CPL. This is for passing the first power signal VDD supplied to the cell driving unit DVD to the compensating power line CPL even if the drive error takes place at the sub-pixels of the display panel1, i.e., at the cell driving units DVD in the initial driving period t_initial. In this case, even if the drive error takes place at the cell driving unit DVD, since the first power signal VDD passes to the compensating power line CPL, without giving any influence to the light emitting cell OLD, no light is emitted.

The frame period t1˜t3, i.e., a frame period of each pixel, after the initializing process is performed is divided into an initializing period t1, a data charging period t2, and a light emitting period t3.

In the initializing period t1, the low logic gate voltage is supplied to a relevant gate line GL in succession. And, the high logic light emitting control voltage is supplied to a relevant light emitting control line EL. According to this, the first, second and fifth switching devices T1, T2and T5of each sub-pixel P are turned on, and the third and fourth switching devices T3and T4are turned off.

In the initializing period t1, the timing controller5generates and supplies the level converting control signal CS to the power supply unit4such that the compensating voltage Vref level is supplied after converted from the ground voltage level to a preset straight polarity compensating voltage Vref level. According to this, the power supply unit4supplies the compensating voltage Vref after converting the compensating voltage Vref level to the preset straight polarity compensating voltage level D_level in response to the level converting control signal CS.

Then, in the data charging period t2, the data voltage is supplied from the data line DL to the first node N1through the first switching device T1turned on thus, and the gate electrode and the drain electrode of the drive switching device DT are connected to each other through the second switching device T2turned on thus. Since the drive switching device DT becomes a forward direction diode according to this, supplying a threshold voltage Vth of the drive switching device DT to the gate electrode of the drive switching device DT, i.e., the second node N2, the threshold voltage Vth of the drive switching device DT is sampled from the second node N2. In this instance, as the first power signal VDD which is a high potential voltage is supplied to the source electrode of the drive switching device DT, a difference VDD-Vth of voltages of the first power signal VDD and the threshold voltage of the drive switching device DT is supplied to the second node N2.

In the light emitting period t3, the high logic gate voltage is supplied to a relevant gate line GL, and the low level light emitting control signal is supplied to the light emitting control line EL. According to this, the first, second and fifth switching devices T1, T2and T5are turned off and the third and fourth T3and T4switching devices are turned on. In this instance, the compensating voltage Vref is supplied to the first node N1through the fourth switching device T4turned on thus.

In this instance, voltages at both terminals of the storage capacitor Cst are maintained constant as no current pass is formed at the cell driving unit DVD. According to this, the voltage at the second node N2which is the other terminal of the storage capacitor Cst changes as much as a voltage change Vref-Vdata on the first node N1which is one terminal of the storage capacitor Cst. That is, the second node N2has a VDD−Vth+Vref−Vdata supplied thereto.

Then, the drive switching device DT is turned on by a voltage between the gate-source electrodes. According to this, a current supplied to the light emitting cell OLD from the drive switching device DT through the third switching device T3, i.e., a third node N3current N3I can be expressed as an equation 3 below. In the equation 3, β is a constant, and Vth_R is an actual threshold voltage of the drive switching device DT.

In the equation 1, if the threshold voltage Vth of the drive switching device DT sampled thus and an actual threshold voltage Vth_R of the drive switching device DT are the same, a current to the drive switching device DT is fixed by the compensating voltage Vref and the data voltage Vdata without being influenced by a voltage drop of the high potential voltage VDD and the threshold voltage of the drive switching device DT. According to this, a picture quality drop caused by hysteresis of the drive switching device DT can be minimized.

FIG. 4illustrates an equivalent circuit showing a structure for supplying a compensating voltage to any one of the sub-pixels inFIG. 2.

Referring toFIG. 4, the display panel1or the power supply unit4of the present invention may further include a compensating voltage supply unit RVD for supplying the compensating voltage Vref to the sub-pixels P of the display panel1, particularly the compensating voltage supply line CPL of the cell driving unit DVD after converting a compensating voltage Vref level to the ground voltage GND level or the preset straight polarity compensating voltage Vref level.

In detail, the compensating voltage supply unit RVD provided to the display panel1or the power supply unit4is provided with NMOS and PMOS switching devices connected in series between the ground voltage GND application terminal and a preset straight polarity compensating voltage Vref application terminal for supplying the compensating voltage of the preset straight polarity compensating voltage Vref level or the ground voltage GND level to the compensating voltage supply line CPL according to the level converting control signal CS.

FIG. 5illustrates other waveforms for describing a method for driving an organic light emitting diode display device in accordance with a preferred embodiment of the present invention.

As described in detail with reference toFIG. 3, a time period from a time the user turns on the organic light emitting diode display device to a time the image is displayed on the display panel1is divided into a power signal turn on period, an initial driving period t_initial, and a frame period t1˜t3.

A method for driving the display panel1in the power signal turn on period, the initial driving period t_initial, and the frame period t1˜t3is identical to the driving method described with reference toFIG. 3.

However, referring toFIG. 5, the gate driving unit2of the present invention may supply the gate voltage to the gate lines GL1˜GLn in succession after reducing an application period of the gate voltage as much as a preset time period dt for at least an initial one frame period. In the meantime, though not shown, separate from the gate voltage, the gate driving unit2may supply the light emitting voltage to the light emitting control lines EL1˜ELn in succession after reducing an application period of the light emitting voltage as much as the preset time period dt for at least the initial one frame period.

In this case, even if the drive error takes place at least one cell driving unit DVD for at least initial one frame period, a time period of the cell driving unit DVD can be reduced, reducing the influence thereof.

As has been described, the organic light emitting diode display device and the method for driving the same of the present invention can improve a display quality of the image by compensating an image voltage being charged to the pixels P and improve reliability of the display device by preventing drive error liable to take place at an initial turn on of the organic light emitting diode display device.