Semiconductor devices and methods of fabricating the same

Semiconductor devices, and methods of fabricating a semiconductor device, include forming a via hole through a first surface of a substrate, the via hole being spaced apart from a second surface facing the first surface, forming a first conductive pattern in the via hole, forming an insulating pad layer on the first surface of the substrate, the insulating pad having an opening exposing the first conductive pattern, performing a thermal treatment on the first conductive pattern to form a protrusion protruding from a top surface of the first conductive pattern toward the opening, and then, forming a second conductive pattern in the opening.

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. non-provisional patent application claims the benefit of priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2012-0140996, filed on Dec. 6, 2012, in the Korean Intellectual Property Office, the entire contents of which are herein incorporated by reference.

BACKGROUND

Example embodiments of the inventive concepts relate to semiconductor devices and/or methods of fabricating the same, and in particular, to semiconductor devices with through-silicon vias and/or methods of fabricating the same.

2. Description of Related Art

There is a growing trend to fabricate lightweight, small-sized, high speed, multifunctional, high performance, and low-cost electronic systems. In response to such a trend, multi-chip stacked package techniques and/or system in package techniques have been proposed. In the multi-chip stacked package or the system in package, one or more semiconductor devices may perform one or more functions in a single semiconductor package. The multi-chip stacked package or the system in package may have a thicker thickness as compared to a single chip package but have a similar size to the single chip package in terms of a planar surface area or ‘footprint’. Thus, the multi-chip stacked package or the system in package may be used in small electronic devices such as mobile devices with high performance requirements, for example, mobile phones, notebook computers, memory cards, and/or portable camcorders.

The multi-chip stacked package or the system in package may be realized using a through-silicon via (TSV) technology. A through-silicon via may affect performance of the semiconductor device.

SUMMARY

Example embodiments of the inventive concepts provide a semiconductor device with improved electric characteristics.

Other example embodiments of the inventive concepts provide a method of fabricating a semiconductor device with improved electric characteristics.

According to example embodiments of the inventive concepts, a semiconductor device may include a substrate having a first surface and a second surface facing each other, a through-silicon via provided in a via hole penetrating the substrate, an integrated circuit spaced apart from the through-silicon via, the integrated circuit being on the first surface of the substrate, a first pad connected to the through-silicon via, the first pad being on the first surface of the substrate, and a second pad connected to the through-silicon via, the second pad being on the second surface of the substrate. The through-silicon via may include a first conductive pattern filling the via hole and a protrusion extending from the first conductive pattern into the first pad.

In example embodiments, the first pad may be in contact with the protrusion.

In example embodiments, the first pad may include a recess region extending from a bottom surface of the first pad toward a top surface of the first pad, and the protrusion may be in contact with the recess region of the first pad.

In example embodiments, a width of the recess region decreases with increasing distance from the bottom surface of the first pad.

In example embodiments, the device may further include an interlayered dielectric layer on the first surface of the substrate to cover the integrated circuit. The via hole penetrates the interlayered dielectric layer, and the first pad may be on the interlayered dielectric layer.

In example embodiments, the recess region may extend to the top surface of the first pad, and the protrusion penetrates the first pad.

In example embodiments, the protrusion has a top surface coplanar with the top surface of the first pad.

In example embodiments, the protrusion has a top surface lower than the top surface of the first pad, and the protrusion may be in contact with the recess region.

According to example embodiments of the inventive concepts, a method of fabricating a semiconductor device includes forming a via hole through a first surface of a substrate, the via hole being spaced apart from a second surface facing the first surface, forming a first conductive pattern in the via hole, forming an insulating pad layer on the first surface of the substrate, the insulating pad layer having an opening exposing the first conductive pattern, performing a thermal treatment on the first conductive pattern to form a protrusion protruding from a top surface of the first conductive pattern toward the opening, and forming a second conductive pattern in the opening.

In example embodiments, the thermal treatment may be performed at a temperature of about 300° C.-500° C., or at a temperature of about 400° C. or more.

In example embodiments, the forming of a second conductive pattern may include forming a second conductive layer in the opening, and planarizing the second conductive layer to expose the insulating pad layer. The second conductive pattern may have a top surface coplanar with a top surface of the insulating pad layer.

In example embodiments, the thermal treatment may be performed in such a way that the protrusion has a top surface higher than the top surface of the insulating pad layer.

In example embodiments, the planarizing the second conductive layer may be performed in such a way that the protrusion has a top surface coplanar with the top surface of the insulating pad layer.

In example embodiments, the method may further include forming an integrated circuit on the first surface of the substrate, the integrated circuit being spaced apart from the via hole, before the forming a via hole, and then, forming an interlayered dielectric layer to cover the integrated circuit. The via hole may be formed to penetrate the interlayered dielectric layer, and the insulating pad layer may be formed on the interlayered dielectric layer.

In example embodiments, the method may further include etching the second surface of the substrate to expose a bottom surface of the first conductive pattern, and forming a pad on the second surface of the substrate, the pad being connected to the bottom surface of the first conductive pattern.

According to example embodiments, a method of fabricating a semiconductor device, includes forming a first conductive pattern in a via hole, the via hole penetrating a substrate, forming an insulating pad layer over the substrate, the insulating pad layer exposing the first conductive pattern, exerting a compressive stress on the first conductive pattern exposed by the insulating pad layer to form a protrusion protruding from the first conductive pattern, and forming a second conductive pattern contacting the protrusion.

The method may further include forming at least one interlayered dielectric layer on the substrate, prior to the forming a first conductive pattern, wherein the via hole penetrates the at least one interlayered dielectric layer, and the exerting a compressive stress may include performing a thermal treatment process so as to cause metallic elements in the first conductive pattern to extrude above the at least one interlayered dielectric layer.

The method may further include performing a preliminary thermal treatment process on the first conductive pattern so as to induce growth of metal grains in the first conductive pattern, prior to the forming an insulating pad layer. The thermal treatment process may be performed at a higher temperature than the preliminary thermal treatment process.

The forming a second conductive pattern may include forming a second conductive layer over the insulating pad layer and the protrusion, a bottom surface of the second conductive layer having a recess with a profile corresponding to a profile of the protrusion, and planarizing the second conductive layer to form the second conductive pattern exposing an upper surface of the insulating pad layer.

The thermal treatment process may cause the metallic elements in the first conductive pattern to extrude above the insulating pad layer, and the planarizing the second conductive layer to form the second conductive pattern may include forming the second conductive pattern so as to expose an upper surface of the protrusion.

DETAILED DESCRIPTION

Various example embodiments will now be described more fully with reference to the accompanying drawings in which some example embodiments are shown. However, specific structural and functional details disclosed herein are merely representative for purposes of describing example embodiments, and thus may be embodied in many alternate forms and should not be construed as limited to only example embodiments set forth herein. Therefore, it should be understood that there is no intent to limit example embodiments to the particular forms disclosed, but on the contrary, example embodiments are to cover all modifications, equivalents, and alternatives falling within the scope of the disclosure.

It will be understood that, if an element is referred to as being ibe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For eIn contrast, if an element is referred to as being ed to as being ibe various elements, these elements shouldent, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” etc.).

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms be the relati “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms e of describing particng,r embodiments only and is not intended to be limiting of example embodiments. A features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.

Spatially relative terms (e.g., at the terms tures, integers, steps, operations, elements, components and/or groups thereof.fy the presence of stated features, integers, steps, operations, elements and/or componen mor feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, for example, the term “below” can encompass both an orientation that is above, as well as, below. The device may be otherwise oriented (rotated 90 degrees or viewed or referenced at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

A method of fabricating a semiconductor device according to an example embodiment of the inventive concepts will be described with reference to sectional views ofFIGS. 1 through 9.

Referring toFIG. 1, provided is a substrate10having a first surface11and a second surface12facing each other. In example embodiments, the substrate10may be, for example, a p-type silicon wafer.

An integrated circuit15may be formed on the first surface11of the substrate10. The integrated circuit15may include a switching element, a capacitor, a resistor, or a vertical memory cell. The switching element may be, for example, a diode, an NMOS transistor, a PMOS transistor, or a bipolar transistor. The vertical memory cell may include a vertical pillar vertically extending from the substrate10and a memory element coupled to the vertical pillar.

A first interlayered dielectric layer20may be formed on the first surface11of the substrate10to cover the integrated circuit15. The first interlayered dielectric layer20may include a silicon oxide layer. A first contact22may be formed through the first interlayered dielectric layer20. The first contact22may be formed of, for example, aluminum or tungsten. The first contact22may be connected to a doped region of the integrated circuit15(e.g., source/drain regions of MOS transistor). An etch stop layer24may be formed on the first interlayered dielectric layer20. The etch stop layer24may include a silicon nitride layer.

A mask pattern (not shown) may be formed on the etch stop layer24. The mask pattern (not shown) may be used to etch the etch stop layer24, the first interlayered dielectric layer20, and the substrate10and to form a via hole21. The via hole21may be formed by a drilling process, a Bosch etching process, or a steady-state etching process. The via hole21may be formed to penetrate the etch stop layer24and the first interlayered dielectric layer20and extend from the first surface11of the substrate10toward the second surface12. The via hole21may be too shallow to penetrate the substrate10. The via hole21may be formed to have a depth of about 50 μm or more. However, the depth of the via hole21may be changed depending on a design rule or a specific device requirement.

Referring toFIG. 2, a via-hole insulating layer32may be formed in the via hole21. The via-hole insulating layer32may be formed by depositing an insulating material, such as, a silicon oxide layer or a silicon nitride layer. The via-hole insulating layer32may be conformally deposited on an inner surface of the via hole21. The via-hole insulating layer32may extend over the first interlayered dielectric layer20. The via-hole insulating layer32may be formed using, for example, an atomic layer deposition or a chemical vapor deposition.

A first barrier layer34may be formed on the via-hole insulating layer32. The first barrier layer34may be formed to cover the inner surface of the via hole21and extend over the first surface11. The first barrier layer34may include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, cobalt, manganese, tungsten nitride, nickel, nickel boride, or a double layer of titanium/titanium nitride. The first barrier layer34may be formed by a sputtering process. The first barrier layer34may be formed at a temperature of about 375° C. The first barrier layer34may be configured to prevent metallic elements in a first conductive layer36, which will be formed in a subsequent process, from diffusing into the substrate10.

The first conductive layer36may be formed on the first barrier layer34to fill the via hole21. The first conductive layer36may extend over the first surface11. The first conductive layer36may be formed using an electroplating process, an electroless plating process, or a selective deposition process. The electroplating process may include forming a seed layer (not shown) on the inner surface of the via hole21provided with the first barrier layer34, and then, plating the seed layer with a conductive layer. In example embodiments, the first conductive layer36may be formed at room temperature (or, alternatively, about 21° C.). The seed layer may be a copper layer, which may be formed by a sputtering process. The conductive layer34may be a metal layer. For example, the metal layer may include silver, gold, copper, tungsten, or indium. In example embodiments, the electroplating process may be performed by dipping the substrate into electrolytic solution containing CuSO4, H2SO4, and Cl.

After the formation of the first barrier layer34and the first conductive layer36, a first thermal treatment process may be performed. The first thermal treatment process may be performed at a temperature of about 100-500° C. The first thermal treatment process may be performed to induce growth of metal grains in the first conductive layer36.

Referring toFIG. 3, the first conductive layer36may be planarized to expose the etch stop layer24. Here, the first barrier layer34and the via-hole insulating layer32may be removed from a top surface of the etch stop layer24. As the result of the planarization, a through-silicon via (TSV) with a first barrier pattern33and a first conductive pattern35may be formed in the via hole21. Thereafter, the etch stop layer24may be removed. In example embodiments, a thermal treatment process may be additionally performed. Thermal treatment process may be performed at a temperature of about 100-500° C.

Referring toFIG. 4, an insulating pad layer26may be formed on the first interlayered dielectric layer20. The insulating pad layer26may be formed to have first and second openings27and28exposing the through-silicon via (TSV) and the first contact22, respectively. Widths of the first and second openings27and28may be greater than widths of the through-silicon via (TSV) and the first contact22, respectively. In example embodiments, the insulating pad layer26may include a silicon oxide layer. In other example embodiments, the insulating pad layer26may include SiCN, SiCOH, and SiON layers that are sequentially stacked on the first interlayered dielectric layer20.

Referring toFIG. 5, a second thermal treatment process may be performed at a temperature that is higher than that of the first thermal treatment process. For example, the second thermal treatment process may be performed at a temperature of about 300-500° C. In the case where the first conductive pattern35is formed of a different material (e.g., copper) from the substrate (e.g., made of silicon), a difference in thermal expansion coefficient therebetween may produce a compressive stress to be exerted to the first conductive pattern35. Accordingly, metallic elements of the first conductive layer36may expand and extrude. For example, as the result of the extrusion of the first conductive pattern35, a protrusion37may be formed in the first opening27. The protrusion37may be protruded from a top of the first conductive pattern35into the first opening27, and thus, the protrusion37may have a top surface that is higher than that of the insulating pad layer26.

Referring toFIG. 6, a second conductive layer40may be formed on the insulating pad layer26to fill the first and second openings27and28. The second conductive layer40may be formed using a process similar to that for the first conductive layer36. Before the formation of the second conductive layer40, a second barrier layer (not shown) and a seed layer (not shown) may be additionally formed. In the first opening27, the second conductive layer40may have a recess region41that is a concave portion formed from a bottom surface thereof toward a top surface thereof. The recess region41may be formed to have a profile corresponding to that of the protrusion37. The protrusion37may be in contact with the recess region41of the second conductive layer40.

Referring toFIG. 7, the second conductive layer40may be planarized to form a second conductive pattern exposing the insulating pad layer26. The second barrier layer (not shown) may be planarized to form a second barrier pattern. As the result of the planarization, a first pad43may be formed in the first opening27and a second pad45may be formed in the second opening28. The first pad43may be in contact with the through-silicon via (TSV), and the second pad45may be in contact with the first contact22. Each of the first and second pads43and45may include the second conductive pattern and the second barrier pattern (not shown). The first and second pads43and45may have top surfaces that are coplanar with that of the insulating pad layer26.

In example embodiments, the protrusion37may be planarized during the planarization process. Accordingly, the protrusion37may have the top surface that is coplanar with that of the first pad43. Further, the recess region41and the protrusion37may be exposed through a top surface of the first pad43.

Referring toFIG. 8, a second interlayered dielectric layer50may be formed on the insulating pad layer26. The second interlayered dielectric layer50may include a silicon oxide layer. The second interlayered dielectric layer50may be formed by a CVD process. For example, the second interlayered dielectric layer50may be a TEOS oxide layer. The second interlayered dielectric layer50may be formed at a temperature of about 400° C.

A second contact52may be formed in the second interlayered dielectric layer50. The formation of the second contact52may include patterning the second interlayered dielectric layer50to form openings exposing the first and second pads43and45, and then, filling the opening with aluminum or tungsten.

A third pad63may be formed on the second interlayered dielectric layer50. The third pad63may be connected to the second contact52. Thereafter, a first passivation layer61may be formed to cover the second interlayered dielectric layer50and expose a portion of the third pad63. The first passivation layer61may be formed of a material capable of protecting the integrated circuit15against external pollution and environmental stress. For example, the first passivation layer61may include at least one of silicon oxide or silicon nitride. The third pad63may be formed of aluminum or copper.

Referring toFIG. 9, the second surface12of the substrate10may be polished or ground. Accordingly, the through-silicon via (TSV) may be exposed through the ground second surface12. The grinding process will be described in more detail below.

Firstly, a carrier (not shown) may be attached on the first passivation layer61of the substrate10using an adhesive layer (not shown). The carrier may be configured to relieve a mechanical stress, which may be exerted to the substrate10in the grinding process, and to prevent a thinned substrate10from being deformed after the grinding process. In example embodiments, the carrier may include a glass substrate or a resin substrate. The adhesive layer may include an ultraviolet adhesive or a thermoplastic adhesive. Next, the second surface12of the substrate10may be polished to expose the via-hole insulating layer32. The polishing of the substrate10may be performed by, for example, a grinding process, in which each or at least one of a CMP process, an etch-back process, and a spin-etch process is used.

Thereafter, the substrate10may be selectively etched in such a way that a bottom portion of the through-silicon via (TSV) is protruded from the second surface12of the substrate10. The selective etching of the substrate10may be performed by a wet etching process or a dry etching process, in which the substrate10is etched with a higher etch rate than the via-hole insulating layer32. For example, if the via-hole insulating layer32is a silicon oxide layer, SF6etching gas may be used to etch selectively the substrate10.

A second passivation layer62may be formed on the polished surface of the second surface12. An etching process may be performed to remove partially the second passivation layer62and the via-hole insulating layer32and expose the through-silicon via (TSV). A fourth pad65may be formed on the second passivation layer62and be connected to the through-silicon via (TSV). The second passivation layer62may include at least one of silicon oxide or silicon nitride. The fourth pad65may be formed of, for example, copper.

Hereinafter, the semiconductor device according to an example embodiment of the inventive concepts will be described with reference toFIG. 9.

Referring toFIG. 9, a semiconductor device101may include the through-silicon via (TSV) penetrating the substrate10.

The substrate10may have the first surface11and the second surface12facing each other. The substrate10may be, for example, a p-type silicon wafer. The integrated circuit15may be formed or integrated on the first surface11of the substrate10. The integrated circuit15may include a switching element, a capacitor, a resistor, or a vertical memory cell. The switching element may be, for example, a diode, an NMOS transistor, a PMOS transistor, or a bipolar transistor. The vertical memory cell may include a vertical pillar vertically extending from the substrate10and a memory element coupled to the vertical pillar.

The first interlayered dielectric layer20may be formed on the first surface11of the substrate10to cover the integrated circuit15. The first interlayered dielectric layer20may include a silicon oxide layer. The first contact22may penetrate the first interlayered dielectric layer20. The first contact22may be formed of, for example, aluminum or tungsten. The first contact22may be connected to a doped region of the integrated circuit15(e.g., source/drain regions of MOS transistor).

The through-silicon via (TSV) may be formed in the via hole21that is formed to penetrate the substrate10and the first interlayered dielectric layer20. The via-hole insulating layer32may be provided between sidewalls of the through-silicon via (TSV) and the via hole21. The via-hole insulating layer32may include or be formed of a silicon oxide layer or a silicon nitride layer. In example embodiments, the through-silicon via (TSV) may be exposed through both of the first and second surfaces11and12of the substrate10. The through-silicon via (TSV) may include the first barrier pattern33and the first conductive pattern35. The through-silicon via (TSV) may further include the protrusion37upward protruding from the top surface of the first conductive pattern35. The first conductive pattern35may include or be formed of a metal layer. The metal layer may include silver, gold, copper, tungsten, or indium. The first barrier pattern33may be provided between the via-hole insulating layer32and the first conductive pattern35. The first barrier pattern33may include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, cobalt, manganese, tungsten nitride, nickel, nickel boride, or a double layer of titanium/titanium nitride.

The insulating pad layer26may be provided on the first interlayered dielectric layer20. The insulating pad layer26may be formed to expose the through-silicon via (TSV) and the first contact22.

The first pad43and the second pad45may be provided on the first interlayered dielectric layer20and be electrically connected to the through-silicon via (TSV) and the first contact22, respectively. Each or all of the first pad43and the second pad45may include the second conductive pattern and the second barrier pattern. The second conductive pattern may be a metal layer. The metal layer may include silver, gold, copper, tungsten, or indium. The second barrier pattern may include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, cobalt, manganese, tungsten nitride, nickel, nickel boride, or a double layer of titanium/titanium nitride. In example embodiments, the first pad43may have the recess region41extending from a bottom surface thereof to a top surface thereof. The recess region41may have a shape corresponding to that of the protrusion37. A width of the recess region41may decrease with increasing distance from the bottom surface of the first pad43. The protrusion37may extend from the first conductive pattern35into the first pad43. The protrusion37may be in contact with the recess region41of the first pad43. For example, the protrusion37may have a top surface that is coplanar with that of the first pad43. The protrusion37may penetrate the first pad43and be exposed through the top surface of the first pad43.

The second interlayered dielectric layer50may be provided on the insulating pad layer26. The second interlayered dielectric layer50may include a silicon oxide layer. The second contacts52may be formed in the second interlayered dielectric layer50. The second contacts52may be connected to the first and second pads43and45, respectively.

The third pad63may be formed on the second interlayered dielectric layer50. The third pad63may be connected to the second contact52. The first passivation layer61may be formed to cover the second interlayered dielectric layer50and expose a portion of the third pad63. The first passivation layer61may be formed of a material capable of protecting the integrated circuit15against external pollution and environmental stress. For example, the first passivation layer61may include at least one of silicon oxide or silicon nitride. The third pad63may be formed of aluminum or copper.

The second passivation layer62may be formed on the second surface12of the substrate10. The second passivation layer62may be formed to expose the through-silicon via TSV. The fourth pad65may be formed on the second passivation layer62and be connected to the through-silicon via (TSV). The second passivation layer62may include or be formed of at least one of silicon oxide or silicon nitride. The fourth pad65may be formed of, for example, copper.

A semiconductor device according to an example embodiment of the inventive concepts will be described with reference to a sectional view ofFIG. 10. For the sake of brevity, the elements and features of this example that are similar to those previously shown and described will not be described in much further detail.

Referring toFIG. 10, the protrusion37may have a top surface that is lower than that of the first pad43and is in contact with the recess region41. The protrusion37may be formed not to penetrate the first pad43.

A semiconductor device according to another example embodiment of the inventive concepts will be described with reference to a sectional view ofFIG. 11. For the sake of brevity, the elements and features of this example that are similar to those previously shown and described will not be described in much further detail.

Referring toFIG. 11, the first interlayered dielectric layer20may be formed on the first surface11of the substrate10to cover the integrated circuit15. The first interlayered dielectric layer20may include a silicon oxide layer.

The first contact22may be electrically connected to the integrated circuit15through the first interlayered dielectric layer20. A first pad42may be formed on the first interlayered dielectric layer20. The first pad42may be connected to the first contact22. The second interlayered dielectric layer50may be formed to cover the first interlayered dielectric layer20. The second interlayered dielectric layer50may include a silicon oxide layer. The second contact52may be electrically connected to the first pad42through the second interlayered dielectric layer50.

The via hole21of the semiconductor device103may be formed to penetrate the first and third interlayered dielectric layers20and50. The via hole21may extend from a top surface of the second interlayered dielectric layer50toward the substrate10.

The through-silicon via (TSV) may be formed to fill the via hole21. The through-silicon via (TSV) may be exposed through the top surface of the second interlayered dielectric layer50. The through-silicon via (TSV) may extend to the top surface of the second interlayered dielectric layer50that is located opposite the first interlayered dielectric layer20. The via-hole insulating layer32may be interposed between the through-silicon via (TSV) and the via hole21.

The second and third pads43and45may be formed on the second interlayered dielectric layer50. The second pad43may be connected to the through-silicon via (TSV). The third pad45may be connected to the second contact52. The second and third pads43and45may have structures similar to those in the previous example embodiments. The first passivation layer61may be formed to cover the second interlayered dielectric layer50and expose at least a portion of the second and third pads43and45.

The second passivation layer62may be formed on the second surface12of the substrate10. The fourth pad65may be formed on the second passivation layer62and be connected to the through-silicon via (TSV). The second passivation layer62may include at least one of silicon oxide or silicon nitride. The fourth pad65may be formed of, for example, copper.

The semiconductor device shown in ofFIG. 11may be fabricated using a process similar to that for the semiconductor device formed in the method shown inFIGS. 1-9. In the following description, for concise description, technical features in a fabricating method that are different from that for the semiconductor device shown inFIGS. 1-9will be mainly described below.

As shown inFIG. 11, the formation of the via hole21of a semiconductor device103may be performed after forming the second interlayered dielectric layer50on the first interlayered dielectric layer20, unlike the method of the previous example embodiments.

Thereafter, the second and third pads43and45may be formed on the second interlayered dielectric layer50. The first passivation layer61may be formed to cover the second interlayered dielectric layer50and expose at least a portion of the second and third pads43and45. The first passivation layer61may include or be formed of at least one of silicon oxide or silicon nitride.

The second passivation layer62may be formed on the second surface12of the substrate10. The fourth pad65may be formed on the second passivation layer62and be connected to the through-silicon via (TSV). The second passivation layer62may include or be formed of at least one of silicon oxide or silicon nitride. The fourth pad65may be formed of, for example, copper.

In general, after the formation of the through-silicon via and the interlayered dielectric layer thereon, a metal expansion in the through-silicon via (TSV) may occur as the result of a thermal budget. The metal expansion may lead to various technical problems, related to connectivity between the through-silicon via and an interconnection line thereon. For example, reliability issue, such as an increase in contact resistance, may occur. By contrast, according to example embodiments of the inventive concepts, the protrusion may be formed and then removed, after the through-silicon via (TSV), and thus, it is possible to reduce technical problems related to the protrusion of the through-silicon via.

According to example embodiments of the inventive concepts, the second thermal treatment process may be performed after the formation of the insulating pad layer26, and thus, it is possible to suppress characteristics of the integrated circuit from being changed. In other words, the insulating pad layer26makes it possible to reduce a change in threshold voltage, Vth, of transistors constituting the integrated circuit, which may be caused by a thermal budget in the second thermal treatment process. By contrast, if the second thermal treatment process is performed before the formation of the insulating pad layer26, the transistors may suffer from a large change in threshold voltage thereof.

FIGS. 12 through 14are sectional views illustrating semiconductor packages, according to example embodiments of the inventive concepts.

Referring toFIG. 12, a semiconductor package401, according to an example embodiment of the inventive concepts, may include a package substrate200and a semiconductor device100mounted thereon. The package substrate200may be a printed circuit board. The package substrate200may include an insulating substrate201, a redistributed line215provided in the insulating substrate201, conductive patterns211and213provided on top and bottom surfaces, respectively, of the insulating substrate201, and package-substrate insulating layers205and203partially covering the conductive patterns211and213. In example embodiments, the semiconductor device100may be configured to have substantially the same features as those of one of the semiconductor devices described with reference toFIGS. 1 through 11.

The semiconductor device100may be mounted on the package substrate200in such a way that the second surface12of the substrate10faces the package substrate200. The semiconductor device100may be electrically connected to the package substrate200via a first bump71. A second bump73may be attached on a bottom surface of the package substrate200. The bumps71and73may be a solder ball, a conductive bump, a conductive spacer, a pin grid array, or any combination thereof. The semiconductor package401may further include a mold layer310covering the semiconductor device100. The mold layer310may include or be formed of an epoxy molding compound.

Referring toFIG. 13, a semiconductor package402, according to another example embodiment of the inventive concepts, may include a first semiconductor device100and a second semiconductor device300that are mounted on the package substrate200. The package substrate200may be a printed circuit board. The first semiconductor device100may be configured to have substantially the same features as those of one of the semiconductor devices described with reference toFIGS. 1 through 11. The second semiconductor device300may be a semiconductor device, e.g., a memory or logic chip, that is different from the first semiconductor device100. In example embodiments, the second semiconductor device300may be configured not to include a through-silicon via.

The first semiconductor device100may be electrically connected to the package substrate200via the first bump71. The second semiconductor device300may be mounted on the first semiconductor device100in a flip-chip bonding manner. The second semiconductor device300may be electrically connected to the first semiconductor device100via a third bump75. The first semiconductor device100may be configured to serve as an interposer. In certain embodiments, a space between the third bumps75may be different from that between the through-silicon vias (TSVs).

The second bump73may be attached on a bottom surface of the package substrate200. The bumps71,73, and75may be a solder ball, a conductive bump, a conductive spacer, a pin grid array, or any combination thereof. The semiconductor package402may further include the mold layer310, which may be formed to cover the first and second semiconductor devices100and300. The mold layer310may include or be formed of an epoxy molding compound.

Referring toFIG. 14, a semiconductor package403, according to still another example embodiment of the inventive concepts, may include a first semiconductor device100aand a second semiconductor device100bthat are mounted on the package substrate200. The semiconductor package403may be configured to have the multi-chip package structure. The first semiconductor device100aand the second semiconductor device100bmay be configured to be of the same kind and have the same structure.

The package substrate200may be a printed circuit board. Each of the first and second semiconductor devices100aand100bmay be configured to have substantially the same features as those of one of the semiconductor devices described with reference toFIGS. 1 through 11.

The first and second semiconductor devices100aand100bmay include a first through-silicon via TSVa and a second through-silicon via TSVb, respectively. The first through-silicon via TSVa and the second through-silicon via TSVb may be overlapped with each other in plan view. The first through-silicon via TSVa may be connected to the second through-silicon via TSVb through the third bump75.

The first semiconductor device100may be electrically connected to the package substrate200via the first bump71. The first semiconductor device100may be configured to serve as an interposer. The second bump73may be attached on a bottom surface of the package substrate200. The bumps71,73, and75may be a solder ball, a conductive bump, a conductive spacer, a pin grid array, or any combination thereof. The semiconductor package403may further include the mold layer310, which may be formed to cover the first and second semiconductor devices100aand100b. The mold layer310may include or be formed of an epoxy molding compound.

According to example embodiments of the inventive concepts described above, the packages may be electrically connected to the package substrate via the through-silicon via, but example embodiments of the inventive concepts may not be limited thereto. For example, some of the pads may be electrically connected to the package substrate by bonding wires.

FIG. 15is a plan view illustrating a package module according an example embodiment of the inventive concepts.

Referring toFIG. 15, a package module500may include a module substrate502, which may be provided with at least one external connection terminal508. The package module500may further include at least one semiconductor chip504and at least one semiconductor package506, for example, a quad-flat-package (QFP) structure, mounted on the module substrate502. The semiconductor chip504and/or the semiconductor package506may include one or more semiconductor devices according to embodiments of the inventive concepts. The package module500may be electrically connected to an external electronic device via the external connection terminal508.

FIG. 16is a schematic block diagram illustrating a memory card in accordance with an example embodiment of the inventive concepts.

Referring toFIG. 16, a memory card600may include a controller620and a memory630in a housing610. The controller620and the memory630may exchange an electric signal with each other. For example, the memory630and the controller620may exchange data with each other according to a command provided by the controller620. Thus, the memory card600may store data in the memory630or may output data from the memory630.

The controller620and/or the memory630may include at least one of the semiconductor devices or the semiconductor packages in accordance with embodiments of the inventive concepts, for example, described herein. The memory card600may be used as a data storage medium for various portable devices. For example, the memory card600may include a multi media card (MMC) or a secure digital (SD) card.

FIG. 17is a block diagram illustrating an electronic system in accordance with an example embodiment of the inventive concepts.

Referring toFIG. 17, an electronic system700may include at least one of the semiconductor devices or the semiconductor packages in accordance with an example embodiment of the inventive concepts, for example, described herein. The electronic system700may include a mobile device or a computer. For example, the electronic system700may include a memory system712, a processor714, a random access memory (RAM)716, and a user interface718that can exchange data with one another using a bus720. The processor714may execute a program and/or control the electronic system700. The RAM716may be used as an operation memory of the processor714. For example, the processor714and the RAM716may include a semiconductor device or the semiconductor packages in accordance with example embodiments of the inventive concepts. The processor714and the RAM716may be included in one package. The user interface718may be used to input data in the electronic system700or to output data from the electronic system700. The memory system712may store program code for performing an operation of the processor714, data processed by the processor714, and/or data input from an external source. The memory system712may include a controller and a memory, and may be the same as or similar to the memory card600ofFIG. 16.

The electronic system700may be applied to various electronic devices. For example, as shown inFIG. 18, the electronic system700can be applied to a mobile phone800. According to other example embodiments, the electronic system700may be applied to a portable notebook, a MP3 player, a navigation system, a solid state disk (SSD), a vehicle, or home appliances.

According to example embodiments of the inventive concepts, it is possible to suppress characteristics of the integrated circuit from being changed by a thermal treatment process. In addition, the through-silicon via can be prevented from being extruded in a subsequent process, and thus, it is possible to prevent an interlayered dielectric layer on the through-silicon via from being cracked and to prevent the through-silicon via from being detached from an interconnection line thereon. This makes it possible to reduce a contact resistance of the device.