Semiconductor wafer, field-effect transistor, method of producing semiconductor wafer, and method of producing field-effect transistor

Provided is a semiconductor wafer including a base wafer, a first insulating layer, and a semiconductor layer. Here, the base wafer, the first insulating layer and the semiconductor layer are arranged in an order of the base wafer, the first insulating layer and the semiconductor layer, the first insulating layer is made of an amorphous metal oxide or an amorphous metal nitride, the semiconductor layer includes a first crystal layer and a second crystal layer, the first crystal layer and the second crystal layer are arranged in an order of the first crystal layer and the second crystal layer in such a manner that the first crystal layer is positioned closer to the base wafer, and the electron affinity Ea1 of the first crystal layer is larger than the electron affinity Ea2 of the second crystal layer.

The contents of the following Japanese patent applications are incorporated herein by reference:No. 2011-045510 filed in JP on Mar. 2, 2011, andPCT/JP2012/001477 filed on Mar. 2, 2012.

BACKGROUND

1. Technical Field

The present invention relates to a semiconductor wafer, a field-effect transistor, a method of producing a semiconductor wafer, and a method of producing a field-effect transistor. The present patent application is related to a research sponsored by 2009, NEDO “Nanoelectronics Semiconductor New Material/New Structure Nanoelectronic Device Technological Development, Research and Development of Group III-V Semiconductor Channel Transistor Technology on Silicon Platform” and filed under the Industrial Technology Enhancement Act, Article 19.

2. Related Art

A Group III-V MISFET (metal-insulator-semiconductor field-effect transistor) utilizing a Group III-V compound semiconductor layer as a channel material exhibits a high electron mobility and is expected to serve as a switching device suitable for high-frequency and high-power operation. A Group III-V MISFET is considered to be a promising alternative of a Si CMOSFET (complementary metal-oxide-semiconductor field-effect transistor) utilizing silicon for a channel material. When Group III-V MISFETs are used to constitute complementary elements to produce an LSI (Large Scale Integration), it is preferable to form the Group III-V MISFETs on a silicon wafer so as to use the existing production equipment and the existing production process.

Non-Patent Documents 1 and 2 disclose a MISFET utilizing a Group III-V compound semiconductor material for the channel layer. Non-Patent Document 3 discloses that the energy level existing at the interface between the semiconductor and the insulator (herein, referred to as “the interface state”) may be effectively reduced by, for example, treating the compound semiconductor surface with an ammonia sulfide solution.

To produce a Group III-V MISFET on a silicon wafer, a Group III-V compound semiconductor layer needs to be formed on the silicon wafer. However, there is a large difference in lattice constant between the Group III-V compound semiconductor layer and the silicon wafer. Therefore, it is difficult to form a high-quality Group III-V compound semiconductor layer by epitaxial growth.

In response, a Group III-V compound semiconductor layer may be formed on a silicon wafer using a direct wafer bonding (DWB) method, which is known as an optical device integration technology, in other words, by directly bonding wafers to each other. When the DWB method is employed, however, the Group III-V compound semiconductor layer may experience damages, for example, generation of crystal defects after the bonding process. When the damage is too serious, the Group III-V compound semiconductor layer can be difficult to be used as a channel material of the MISFET. In particular, a Group III-V compound semiconductor layer is more obviously damaged in the case of an ultra-thin-body MISFET having an extremely thin Group III-V compound semiconductor layer.

There is also a strong demand for further improvement of the performance of Group III-V MISFETs. In particular, it is highly requested to achieve high carrier mobility. An interface state exists at the interface between a channel layer and a gate insulator layer. If carriers are trapped in the interface state, the carrier mobility is degraded due to coulomb scattering and other reasons. Accordingly, it is desirable to further lower the interface state. Furthermore, irrespective of a certain high interface state density at a MIS interface, it is desirable to further enhance the performance of FETs by taking measures to minimize the influence of the interface state existing at the MIS interface.

An objective of the present invention is to provide a Group III-V MISFET having a high carrier mobility by reducing the damage to be experienced by a Group III-V compound semiconductor layer when the DWB method is employed and the Group III-V compound semiconductor layer is bonded to a wafer and mitigating the influences of the experienced damage and the interface state.

SUMMARY

For a solution to the above-mentioned problems, according to the first aspect related to the present invention, provided is one exemplary semiconductor wafer including a base wafer, a first insulating layer, and a semiconductor layer. Here, the base wafer, the first insulating layer and the semiconductor layer are arranged in an order of the base wafer, the first insulating layer and the semiconductor layer, the first insulating layer is made of an amorphous metal oxide or an amorphous metal nitride, the semiconductor layer includes a first crystal layer and a second crystal layer, the first crystal layer and the second crystal layer are arranged in an order of the first crystal layer and the second crystal layer in such a manner that the first crystal layer is positioned closer to the base wafer, and the electron affinity Ea1of the first crystal layer is larger than the electron affinity Ea2of the second crystal layer.

The semiconductor layer may further include a third crystal layer. In this case, the first crystal layer, the second crystal layer and the third crystal layer are arranged in an order of the third crystal layer, the first crystal layer and the second crystal layer in such a manner that the third crystal layer is positioned closest to the base wafer, and the electron affinity Ea3of the third crystal layer is smaller than the electron affinity Ea1of the first crystal layer. The first crystal layer can be, for example, made of Inx1Ga1-x1As (0<x1≦1), the second crystal layer can be, for example, made of Inx2Ga1-x2As (0≦x2<1), the third crystal layer can be, for example, made of Inx3Ga1-x3As (0≦x3<1), and the relation of x1>x2 and the relation of x1>x3 are preferably satisfied. The semiconductor layer preferably has the thickness of 20 nm or less.

For a solution to the above-mentioned problems, according to the second aspect related to the present invention, provided is one exemplary field-effect transistor including the semiconductor layer of the above-described semiconductor wafer and a source electrode and a drain electrode that are electrically connected to the semiconductor layer of the semiconductor wafer.

The semiconductor layer includes a source region in contact with the source electrode or a drain region in contact with the drain electrode. In this case, the source region or the drain region may contain an alloy of (i) at least one type of atom selected from the group consisting of a Group III atom and a Group V atom that make the semiconductor layer and (ii) a metal atom. The metal atom is preferably a nickel atom. The field-effect transistor preferably includes a gate electrode on a side of the semiconductor layer that faces away from the base wafer, and an interface of the source region that is positioned closer to the drain region and an interface of the drain region that is positioned closer to the source region are formed in an under-gate electrode region that is a region of the semiconductor layer that is sandwiched between the gate electrode and the base wafer. In this manner, a planar MOSFET having a channel length of 100 nm or less can be produced. When the field-effect transistor is an n-channel field-effect transistor, the source region or the drain region may further contain a donor impurity atom. When the field-effect transistor is a p-channel field-effect transistor, the source region or the drain region may further contain an acceptor impurity atom.

For a solution to the above-mentioned problems, according to the third aspect related to the present invention, provided is one exemplary method for producing a semiconductor wafer. The method includes forming a semiconductor layer on a semiconductor layer-forming wafer by an epitaxial crystal growth method, forming a first insulating layer on the semiconductor layer by an atomic layer deposition method, bonding a base wafer onto the first insulating layer, and removing the semiconductor layer-forming wafer from the semiconductor layer. Here, said forming a semiconductor layer includes forming a second crystal layer on the semiconductor layer-forming wafer by an epitaxial crystal growth method, and after said forming a second crystal layer, forming a first crystal layer on the second crystal layer by an epitaxial crystal growth method, and the electron affinity Ea1of the first crystal layer is larger than the electron affinity Ea2of the second crystal layer.

Said forming a semiconductor layer may further include, after said forming a first crystal layer, forming a third crystal layer on the first crystal layer by an epitaxial crystal growth method, and the electron affinity Ea3of the third crystal layer is smaller than the electron affinity Ea1of the first crystal layer.

For a solution to the above-mentioned problems, according to the fourth aspect related to the present invention, provided is one exemplary method for producing a field-effect transistor. The method includes forming a second insulating layer by an atomic layer deposition method on the semiconductor layer of the semiconductor wafer produced by a method for producing a semiconductor wafer comprising: forming a semiconductor layer on a semiconductor layer-forming wafer by an epitaxial crystal growth method; forming a first insulating layer on the semiconductor layer by an atomic layer deposition method; bonding a base wafer onto the first insulating layer; and removing the semiconductor layer-forming wafer, wherein the forming a semiconductor layer includes: forming a second crystal layer on the semiconductor layer-forming wafer by an epitaxial crystal growth method; and after the forming a second crystal layer, forming a first crystal layer on the second crystal layer by an epitaxial crystal growth method, and the electron affinity Ea1of the first crystal layer is larger than the electron affinity Ea2of the second crystal layer, forming a gate electrode on the second insulating layer, etching a portion of the second insulating layer that is other than a region in which the gate electrode is formed, thereby forming an opening reaching the semiconductor layer, forming a metal film in contact with a portion of the semiconductor layer that is exposed through the opening, and thermally treating the metal film, thereby forming at least one of a source region and a drain region in the portion of the semiconductor layer that is in contact with the metal film.

In said forming at least one of the source region and the drain region, one or more conditions selected from the temperature of the thermal treatment and the duration of the thermal treatment can be controlled in such a manner that one or more interfaces selected from an interface of the source region that is positioned closer to the drain region and an interface of the drain region that is positioned closer to the source region can be positioned in an under-gate electrode region that is a region of the semiconductor layer that is sandwiched between the gate electrode and the base wafer.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

FIG. 1illustrates the cross-section of a semiconductor wafer100. The semiconductor wafer100includes a base wafer102, a first insulator layer104, and a semiconductor layer106. The base wafer102, the first insulator layer104, and the semiconductor layer106are arranged in the order of the base wafer102, the first insulator layer104, and the semiconductor layer106.

The base wafer102is, for example, a wafer whose surface is made of silicon crystal. The wafer whose surface is made of silicon crystal is, for example, a silicon wafer or a silicon-on-insulator (SOI) wafer and the silicon wafer is a preferable choice due to its low cost from the perspective of production. When the base wafer102is a wafer whose surface is made of silicon crystal, the existing production apparatuses and the existing production processes can be employed, which can streamline the research and development and the production. The base wafer102is not limited to a wafer whose surface is made of silicon crystal, and may be an insulator wafer such as a glass wafer and a ceramics wafer, an electrically conductive wafer such as a metal wafer, or a semiconductor wafer such as a silicon carbide wafer.

The first insulator layer104is made of an amorphous metal oxide or an amorphous metal nitride. The first insulator layer104is, for example, a layer made of at least one material selected from among Al2O3, SiO2, AlN, AlON, HfO2, HfSiON, ZrO2, SiNx(for example, Si3N4), and Ta2O5, or a laminate constituted by two layers made of at least two different materials selected from the above-described materials.

As described later, the semiconductor layer106is formed on the base wafer102with the first insulator layer104interposed therebetween by means of a bonding method. Accordingly, the first insulator layer104desirably has a flat surface. The first insulator layer104is preferably made of a metal oxide or a metal nitride obtained by atomic layer deposition (ALD) or of SiO2obtained by thermal oxidation. Surface flatness can be evaluated by a root mean square (RMS) value of surface roughness observed using an atomic force microscope (AFM). Here, the RMS value of the surface of the first insulator layer104is preferably 1 nm or less. When the first insulator layer104is formed using atomic layer deposition (ALD), the first insulator layer104can have a flat surface, be amorphous and be constituted by one or more layers made of one or more materials selected from among Al2O3, SiO2, AlN, AlON, HfO2, HfSiON, ZrO2, SiNx(for example, Si3N4), and Ta2O5. When the first insulator layer104is formed by thermal oxidation, the first insulator layer104can be formed as an amorphous SiO2layer having a flat surface. Since SiO2and Al2O3exhibit high thermal stability, the thermal stability of the first insulator layer104can be enhanced when the first insulator layer104is formed by one or more insulator layers made of one or more materials selected from among SiO2and Al2O3. Thus, SiO2and Al2O3are more preferable choices. Here, the thermal stability indicates that a subsequent step in the production process can be performed at a high wafer temperature and is an advantageous property from the perspective of the production process.

If the base wafer102and the semiconductor layer106are directly bonded together, stress may be generated due to the difference in lattice constant between the base wafer102and the semiconductor layer106and the stress may generate crystal defects in the semiconductor layer106. To address this issue, the semiconductor wafer100relating to the present exemplary embodiment has the first insulator layer104made of an amorphous metal oxide or an amorphous metal nitride between the base wafer102and the semiconductor layer106. Since the first insulator layer104does not have a crystal structure, the stress due to the difference in lattice constant between the base wafer102and the semiconductor layer106is mitigated in the semiconductor wafer100relating to the present exemplary embodiment. Thus, crystal defects are prevented from being generated in the semiconductor layer106. As discussed above, when the amorphous first insulator layer104is interposed between the base wafer102and the semiconductor layer106, the semiconductor layer106is less damaged during the production process.

The semiconductor layer106is made of a Group III-V compound semiconductor. When the semiconductor wafer100has the semiconductor layer106made of a Group III-V compound semiconductor, a MISFET with a high mobility and high performance can be formed on the base wafer102.

The thickness of the semiconductor layer106preferably falls within the range of 20 nm or less. When the semiconductor layer106has the thickness of 20 nm or less, an ultrathin-body MISFET can be obtained. An ultrathin-body MISFET can reduce the short channel effects and leakage currents. The thickness of the semiconductor layer106is more preferably 10 nm or less.

When the first insulator layer104is in contact with the semiconductor layer106, the semiconductor layer106may be sulfur-terminated at the plane in contact with the first insulator layer104. This can lower the interface state density at the interface between the first insulator layer104and the semiconductor layer106.

The semiconductor layer106includes a first crystal layer108and a second crystal layer110. The first crystal layer108and the second crystal layer110are arranged in such a manner that the first crystal layer108is positioned closer to the base wafer102than the second crystal layer110is. The first crystal layer108lattice matches or pseudo-lattice matches the second crystal layer110. The first crystal layer108and the second crystal layer110are formed in such a manner that the electron affinity Ea1of the first crystal layer108is larger than the electron affinity Ea2of the second crystal layer110. When the electron affinity Ea1of the first crystal layer108is larger than the electron affinity Ea2of the second crystal layer110, more carrier electrons are distributed in the first crystal layer108. In other words, even when an insulator layer is formed on the second crystal layer110and an interface state is created at the interface between the insulator layer and the second crystal layer110, the carrier electrons are prevented from being scattered due to the interface state. Therefore, when fabricating a semiconductor device using the semiconductor layer106as a channel layer, the electron mobility in the channel layer can be high.

The first crystal layer108is, for example, made of InGaAs or InAs, in which case the second crystal layer110is, for example, made of InGaAsP. The first crystal layer108is, for example, made of Inx1Ga1-x1As (0<x1≦1), in which case the second crystal layer110is, for example, made of Inx2Ga1-x2As (0≦x2<1, x1>x2). The first crystal layer108is, for example, made of Inx1Ga1-x1As (0.53≦x1≦1), in which case the second crystal layer110is, for example, made of Inx2Ga1-x2As (0≦x2<0.53). The first crystal layer108is, for example, made of In0.7Ga0.3As, in which case the second crystal layer110is, for example, made of In0.3Ga0.7As. The first crystal layer108is, for example, made of InAs, in which case the second crystal layer110is, for example, made of In0.3Ga0.7As.

The thickness of the first crystal layer108can be within the range of 10 nm or less, in particular, preferably within the range of 5 nm or less. The thickness of the second crystal layer110can be within the range of 10 nm or less, in particular, preferably within the range of 2 nm to 5 nm. The second crystal layer110may be at least partially doped with impurities.

FIGS. 2 to 4show the cross-section observed during the production process of the semiconductor wafer100. As shown inFIG. 2, a semiconductor layer-forming wafer120is provided, and the semiconductor layer106is formed by epitaxial growth on the semiconductor layer-forming wafer120. After this, the first insulator layer104is formed by atomic layer deposition on the semiconductor layer106.

The semiconductor layer-forming wafer120is, for example, an InP wafer. When the semiconductor layer-forming wafer120is an InP wafer, the Group III-V compound semiconductor layer106can achieve high quality.

The semiconductor layer106is formed in such a manner that the second crystal layer110is first formed by epitaxial growth and the first crystal layer108is then formed by epitaxial growth. Here, the first crystal layer108and the second crystal layer110are formed in such a manner that the electron affinity Ea1of the first crystal layer108is larger than the electron affinity Ea2of the second crystal layer110.

The epitaxial growth of the semiconductor layer106can be performed using metal organic chemical vapor deposition (MOCVD). When MOCVD is used, the In source is, for example, trimethylindium (TMIn), the Ga source is, for example, trimethylgallium (TMGa), the As source is, for example, AsH3(arsine), and the P source is, for example, PH3(phosphine). The carrier gas can be hydrogen. The temperature at which the reaction takes place can range from 300° C. to 900° C., preferably from 450° C. to 750° C. The duration of the reaction can be appropriately selected to control the thickness of the epitaxial growth layers.

When the first insulator layer104is formed by atomic layer deposition (ALD), the first insulator layer104can be formed flat. Therefore, high adhesion can be achieved between the first insulator layer104and the semiconductor layer106, and the semiconductor layer106can be less damaged during the step of bonding the first insulator layer104and the base wafer102to each other. The bonding step is described in detail later.

As shown inFIG. 3, the base wafer102is separately provided, the surface of the first insulator layer104and the surface of the base wafer102are activated using an argon beam122. Following this, as shown inFIG. 4, the surface of the first insulator layer104that has been activated by the argon beam122is bonded and attached to the surface of the base wafer102that has also been activated by the argon beam122. The bonding can be performed at a room temperature. The activation does not have to be performed using the argon beam122and may alternatively be performed using a beam of a different rare gas. After this, etching is performed using a HCl solution or the like to remove the semiconductor layer-forming wafer120. In this manner, the semiconductor wafer100shown inFIG. 1can be produced.

Before the bonding, an insulator layer may be formed by ALD on the surface of the base wafer102, and the insulator layer on the surface of the base wafer102may be bonded to the first insulator layer104. In place of the activation using the argon beam122or the like, the surface of the insulator layer on the base wafer102and the surface of the first insulator layer104may be subjected to hydrophilic treatment before they are bonded together. When the hydrophilic treatment is employed, it is preferable to heat the base wafer102and the first insulator layer104after bonding them together. Between the formation of the semiconductor layer106and the formation of the first insulator layer104, the surface of the semiconductor layer106may be subjected to sulfur-termination treatment.

FIG. 5shows the cross-section of a field-effect transistor200. The field-effect transistor200is formed using the semiconductor wafer100shown in FIG.1. The field-effect transistor200includes a source electrode202and a drain electrode204on the semiconductor wafer100. The source electrode202and the drain electrode204are electrically connected to the semiconductor layer106of the semiconductor wafer100. The semiconductor layer106includes a source region206and a drain region208. The source region206is in contact with the source electrode202, and the drain region208is in contact with the drain electrode204. The field-effect transistor200includes a second insulator layer210on a plane of the semiconductor layer106that faces away from the plane of the semiconductor layer106that is in contact with the first insulator layer104. The second insulator layer210may be provided on a region of the semiconductor layer106that is sandwiched between the source region206and the drain region208. The field-effect transistor200also includes a gate electrode212on the second insulator layer210. A portion of the second insulator layer210serves as a gate insulator. At least one of the boundary of the source region206that faces the drain region208and the boundary of the drain region208that faces the source region206is positioned in an under-gate-electrode region, which is a region of the semiconductor layer106that is sandwiched between the gate electrode212and the base wafer102. Here, the region that is sandwiched between the gate electrode212and the base wafer102indicates the region that is positioned between the gate electrode212and the base wafer102and overlaps both of the gate electrode212and the base wafer102. The boundary of the source region206that faces the drain region208may indicate the boundary of the source region206that is the nearest to the drain region208. The boundary of the drain region208that faces the source region206may indicate the boundary of the drain region208that is the nearest to the source region206.

The source region206or the drain region208contains an alloy of a metal atom and at least one atom selected from the group consisting of the Group III atoms and the Group V atoms forming the semiconductor layer106. In other words, at least one of the source region206and the drain region208(preferably, both of the source region206and the drain region208) is a region formed by metallizing the semiconductor layer106with the above-mentioned metal atom. The metal atom is, for example, a nickel atom, a cobalt atom, in particular, a nickel atom. The alloy may be an alloy of at least one atom selected from the group consisting of a nickel atom and a cobalt atom, and Group III and Group V atoms. The alloy is preferably an alloy of three elements including a Group III atom, a Group V atom, and a nickel atom.

Since the source region206or the drain region208contains the above-described alloy, an ohmic contact is established between the source electrode202and the source region206and between the drain electrode204and the drain region208. This can allow the field-effect transistor200to have a high on-current. Since the source-drain resistance is low, the channel resistance does not need to be low and the concentration of the doping impurity atoms is allowed to be low. Consequently, high carrier mobility can be achieved.

When the field-effect transistor200is an n-channel field-effect transistor, the source region206or the drain region208may further contain donor impurity atoms. The donor impurity atoms are, for example, Si, S, Se or Ge atoms. When the field-effect transistor200is a p-channel field-effect transistor, the source region206or the drain region208may further contain acceptor impurity atoms. The acceptor impurity atoms are, for example, Zn, C or Mg atoms.

The relative permittivities, the thicknesses and the electron affinities of the second insulator layer210and of the second crystal layer110are preferably selected to satisfy the relation represented by Expression 1.
(ε1·d0)/(ε0·d1)>(V−δ)/δ  (Expression 1)

In Expression 1, d0and ε0respectively denote the thickness and the relative permittivity of the second insulator layer210in the under-gate region sandwiched between the gate electrode212and the first crystal layer108, and d1and ε1respectively denote the thickness and the relative permittivity of the second crystal layer110in the under-gate region. Also, δ denotes the difference in electron affinity between the second crystal layer110and the first crystal layer108and δ=Ea1−Ea2. Furthermore, V denotes the voltage defined by the expression V=Vg−Vt, Vg denotes the voltage applied to the gate electrode212of the field-effect transistor200, and Vt denotes the threshold voltage. The voltage V can be approximated by the voltage applied to the laminate structure of the second crystal layer110and the second insulator layer210in the under-gate region when the field-effect transistor200is operated by a voltage equal to or higher than the threshold voltage applied to the gate electrode212.

If the relation represented by Expression 1 is satisfied while the carriers migrate between the source electrode202and the drain electrode204of the field-effect transistor200, many channel electrons can be induced at the interface between the first crystal layer108and the second crystal layer110. Therefore, the influence of the interface state existing between the second insulator layer210and the second crystal layer110on the channel electrons can be reduced. Accordingly, the mobility of the channel electrons can be increased. When the field-effect transistor200is used for a CMOS circuit, the power source voltage is preferably no less than 0.4 V and no more than 1.0 V.

The relation represented by Expression 1 can be derived as follows. When the voltage V is applied to the laminate structure of the second crystal layer110and the second insulator layer210in the under-gate region, the voltage drop ΔV in the second crystal layer110can be represented by Expression 2.
ΔV=V×(d1/ε1)/((d1/ε1)+d0/ε0)  (Expression 2)

If ΔV<δ, many channel electrons can be induced between the second insulator layer210and the second crystal layer110. Thus, Expression 3 is obtained.
V×(d1/ε1)/((d1/ε1)+d0/ε0)<δ  (Expression 3)

Expression 3 can be converted into Expression 1. Thus, when the relation represented by Expression 1 is satisfied, high-mobility channel electrons can be induced at the interface between the first crystal layer108and the second crystal layer110.

FIGS. 6 to 8illustrate the cross-section observed during the production process of the field-effect transistor200. As shown inFIG. 6, the second insulator layer210is formed by atomic layer deposition on the semiconductor wafer100, and a metal layer211to be formed into the gate electrode212is subsequently formed. As shown inFIG. 7, the metal layer211is patterned to form the gate electrode212, and the gate electrode212is used as a mask to pattern the second insulator layer210. Stated differently, a portion of the second insulator layer210that excludes the region in which the gate electrode212is formed is etched away, thereby forming an opening that reaches the semiconductor layer106.

Furthermore, a metal film220is formed. Specifically speaking, the metal film220is formed so as to be in contact with the semiconductor layer106exposed through the opening. The metal film220can be formed by, for example, sputtering or evaporation. The metal film220is, for example, a nickel film or a cobalt film, preferably a nickel film. As shown inFIG. 8, the metal film220is subjected to thermal treatment, thereby forming the source region206or the drain region208in a portion of the semiconductor layer106that is in contact with the metal film220. After the unreacted portion of the metal film220is removed, the source electrode202and the drain electrode204are formed on the source region206and the drain region208, respectively. Thus, the field-effect transistor200shown inFIG. 5can be fabricated.

When the field-effect transistor200is an N-channel field-effect transistor, the metal film220may contain a nickel atom and a donor impurity atom (Si or the like). When the field-effect transistor200is a P-channel field-effect transistor, the metal film220may contain a nickel atom and an acceptor impurity atom (Zn or the like). The thermal treatment of the metal film220is preferably performed using rapid thermal annealing (RTA). When RTA is employed, the annealing temperature can be preferably set at 250° C. In the above-described manner, the source region206and the drain region208can be self-aligned. By controlling one or both of the temperature and the duration of the annealing using RTA, the reaction that proceeds in the lateral direction between the metal atoms constituting the metal film220and the semiconductor atoms constituting the semiconductor layer106is controlled so as to control the positions of the boundaries of the source region206and the drain region208that face each other. Stated differently, it can be controlled how much the source region206and the drain region208go into the under-gate-electrode region. In this way, a planar MOSFET having a channel length of approximately several dozen nanometers (100 nm or less) can be easily produced.

In the case of the above-described semiconductor wafer100and the field-effect transistor200using the semiconductor wafer100, the semiconductor layer106is formed by epitaxial growth on the semiconductor layer-forming wafer120made of InP. Thus, the semiconductor layer106can achieve high quality. Since the semiconductor layer106is bonded to the base wafer102with the amorphous first insulator layer104interposed therebetween, the semiconductor layer106can maintain the high quality. Thus, the field-effect transistor200utilizing the semiconductor layer106as the channel layer can achieve high performance. Since the semiconductor layer106has an ultrathin body, the leakage currents can be reduced. Furthermore, since the electron affinity Ea1of the first crystal layer108, which is distant from the gate insulator, is larger than the electron affinity Ea2of the second crystal layer110, which is closer to the gate insulator, the carrier electrons in the channel layer are prevented from the scattering at the MIS interface and the carrier mobility in the channel can be thus improved. Additionally, since the source region206and the drain region208of the field-effect transistor200are metallized, the source-drain resistance can be reduced. Since the source-drain resistance is reduced, the doping level of the channel layer can be lowered, which can result in improved carrier mobility.

As shown inFIG. 9, the semiconductor layer106may further include a third crystal layer302.FIG. 9shows the cross-section of a semiconductor wafer300. The semiconductor wafer300may have the same configuration as the semiconductor wafer100except that the semiconductor layer106additionally includes the third crystal layer302. Referring to the semiconductor wafer300, the first crystal layer108, the second crystal layer110and the third crystal layer302are arranged in the order of the third crystal layer302, the first crystal layer108and the second crystal layer110, where the third crystal layer302is positioned the closest to the base wafer102. The third crystal layer302is formed in such a manner that the electron affinity Ea3of the third crystal layer302is smaller than the electron affinity Ea1of the first crystal layer108.FIG. 10shows the cross-section of a field-effect transistor400utilizing the semiconductor wafer300. The field-effect transistor400may have the same configuration as the field-effect transistor200except that the semiconductor layer106additionally includes the third crystal layer302.

Referring to the semiconductor wafer300and the field-effect transistor400, the existence of the third crystal layer302separates the carrier electrons within the semiconductor layer106away from the interface between the semiconductor layer106and the first insulator layer104. This can prevent the scattering of the carrier electrons caused by the interface state at the interface between the first insulator layer104and the third crystal layer302. Consequently, the carrier mobility improves. Since the first crystal layer is sandwiched between the second crystal layer110and the third crystal layer302that respectively satisfy the relations of Ea<Ea1, and Ea3<Ea1, the channel electrons within the semiconductor layer106are quantized. Therefore, the position within the semiconductor layer106at which the number of channel electrons takes a maximum value can be further away from the interface between the semiconductor layer106and the first insulator layer104and from the interface between the semiconductor layer106and the second insulator layer210. Thus, the carrier mobility is enhanced.

The third crystal layer302lattice matches or pseudo-lattice matches the first crystal layer108. When the first crystal layer108is made of InGaAs and the second crystal layer110is made of InGaAsP, the third crystal layer302can be, for example, made of InGaAsP. When the first crystal layer108is made of Inx1Ga1-x1As (0<x1≦1) and the second crystal layer110is made of Inx2Ga1-x2As (0≦x2≦1, x1>x2), the third crystal layer302can be, for example, made of Inx3Ga1-x3As (0≦x3<1, x1>x3). The first crystal layer108is, for example, made of Inx1Ga1-x1As (0.53≦x1≦1). In this case, the second crystal layer110is, for example, made of Inx2Ga1-x2As (0≦x2<0.53) and the third crystal layer302is, for example, made of Inx3Ga1-x3As (0≦x3<0.53). Here, x2 may be equal to x3. When the first crystal layer108is made of In0.7Ga0.3As and the second crystal layer110is made of In0.3Ga0.7As, the third crystal layer302can be, for example, made of In0.3Ga0.7As. When the first crystal layer108is made of InAs and the second crystal layer110is In0.3Ga0.7As, the third crystal layer302can be, for example, made of In0.3Ga0.7As.

The thickness of the third crystal layer302may preferably fall within the range of 20 nm or less, in particular, within the range of 2 nm to 5 nm. During the production process of the semiconductor layer106, the third crystal layer302can be formed by epitaxial growth after the first crystal layer108is formed.

In the above, a front-gate field-effect transistor, which has the gate electrode212on the side of the front surface of the semiconductor wafer, is described as an example. A field-effect transistor may alternatively have a back gate electrode502as shown inFIG. 11. Specifically speaking, a field-effect transistor500shown inFIG. 11is different from the field-effect transistor200shown inFIG. 5or the field-effect transistor400shown inFIG. 10in terms that the second insulator layer210and the gate electrode212are not provided and that the back gate electrode502is provided on the plane of the base wafer102that faces away from the first insulator layer104. The field-effect transistor500may include the source electrode202, the drain electrode204, the source region206, the drain region208, the semiconductor layer106, the first insulator layer104, and the base wafer102, in the same manner as the field-effect transistor200shown inFIG. 5or the field-effect transistor400shown inFIG. 10. In the field-effect transistor500, the first insulator layer104partially serves as a gate insulator.

As shown inFIG. 12, a double-gate field-effect transistor may be provided that is a combination of a front gate structure and a back gate structure. Specifically speaking, a field-effect transistor600shown inFIG. 12includes the back gate electrode502arranged on the base wafer102, and the gate electrode212that is provided on the plane of the semiconductor layer106that faces away from its plane in contact with the first insulator layer104with the second insulator layer210being interposed therebetween. The first insulator layer104and the second insulator layer210partially serve as a gate insulator. The field-effect transistor600may include the source electrode202, the drain electrode204, the source region206, the drain region208, the semiconductor layer106, the first insulator layer104, and the base wafer102, in the same manner as the field-effect transistor200shown inFIG. 5or the field-effect transistor400shown inFIG. 10.

First Working Example

An InGaAs layer was epitaxially grown by metal organic vapor phase epitaxy (MOVPE) on an InP wafer of the plane orientation (001), and an Al2O3layer was formed by ALD on the InGaAs layer. Another Al2O3layer was formed by ALD on a separate silicon wafer. The Al2O3layers formed on the InP wafer and the silicon wafer were subjected to hydrophilic treatment, the InP wafer was bonded to the silicon wafer, and InP was selectively removed using a HCl solution. In this way, a semiconductor wafer constituted by the InGaAs layer, the Al2O3layer (BOX layer) and the silicon wafer was produced.

The surface of the InGaAs layer of the thus-produced semiconductor wafer was cleaned using acetone, NH4OH, (NH4)2S and subjected to sulfur-termination treatment. After this, an Al2O3layer having the thickness of 10 nm was formed using ALD on the InGaAs layer. The sulfur-termination treatment may not use acetone and NH4OH and may only use (NH4)2S. A gate electrode made of tantalum was formed by sputtering and subjected to post-metallization annealing, after which a nickel film having the thickness of 20 nm was formed. The nickel film was subjected to RTA at the temperature of 250° C., to form a source and a drain (S/D) made of Ni—InGaAs alloy. In this way, a field-effect transistor was produced.

Five sample field-effect transistors (1) to (5) were produced that differ from each other in terms of the InGaAs layer as follows.

(3) A laminate constituted by In0.3Ga0.7As/In0.7Ga0.3As/In0.3Ga0.7As having the thicknesses of 2/1/3 nm

(4) A laminate constituted by In0.3Ga0.7As/In0.7Ga0.3As/In0.3Ga0.7As having the thicknesses of 2/3/3 nm

(5) A laminate constituted by In0.3Ga0.7As/In0.7Ga0.3As/In0.3Ga0.7As having the thicknesses of 2/5/3 nm

In the following description made with reference toFIGS. 13 to 20, the samples (1) and (2) may be referred to using the terms such as “without buffer” or “single channel,” and the samples (3) to (5) may be referred to using the term “with buffer.” The thickness of the InGaAs layer may be referred to as “the thickness of the body” and the thickness of the In0.7Ga0.3As layer may be referred to as “the thickness of the channel” in relation to the samples (3) to (5).

FIG. 13is a TEM photograph showing the cross-section of the sample (5).FIG. 13shows that the respective layers were formed appropriately. It was confirmed that the Ni—InGaAs alloy under the gate overlapped the gate to an appropriate extent and that the source and the drain of Ni—InGaAs alloy were formed in self-alignment.

FIG. 14shows the Id-Vg characteristics of the sample (1).FIG. 15shows the Id-Vd characteristics of the sample (1).FIG. 16shows the relation between the mobility and the charge density Ns for the sample (1).FIG. 16also shows, for the comparison purpose, the data of a sample that has a heavily doped InGaAs channel (having the thickness of 9 nm) instead of using a Ni—InGaAs alloy for the source and the drain. With reference toFIGS. 14 to 16, the sample (1) exhibited a high on-current irrespective of a low channel doping concentration of 1×1016atoms/cm3. This is the result of the fact that the source and the drain were made of the Ni—InGaAs alloy. As seen fromFIG. 15, the sample (1) exhibited excellent Id-Vd characteristics. As seen fromFIG. 16, the mobility of the sample (1) was approximately 1.9 times as high as the mobility of the comparative example that did not constitute the source and the drain with a Ni—InGaAs alloy. It was therefore confirmed that the source and the drain achieved an improved mobility when made of a Ni—InGaAs alloy.

FIG. 17shows the Id-Vg characteristics of the sample (5). The sample (5) exhibited a three-digit on/off ratio and a low subthreshold swing value of 183 mV/dec.FIG. 18shows the Id-Vg characteristics of the sample (3). The sample (3) exhibited a seven-digit on/off ratio and an extremely excellent subthreshold swing value of 103 mV/dec.FIG. 19shows the relation between the mobility and the charge density Ns for the sample (5).FIG. 19also shows, for the comparison purpose, the same parameters for the sample (1) (WITHOUT BUFFER) and a Si MOSFET. The mobility of the sample (5) was 4.2 times and 1.6 times higher than the mobility of the Si MOSFET and the mobility of the sample (1). Thus, it has been confirmed that utilizing the laminated channel of In0.3Ga0.7As/In0.7Ga0.3As/In0.3Ga0.7As effectively enhanced the mobility.

FIG. 20shows how the mobility is dependent on the thickness of the channel material for the samples (1) to (5). As is seen fromFIG. 20, while the mobility rapidly decreases when the thickness of the channel material (TOTAL THICKNESS OF BODY) falls below approximately 10 nm, it was confirmed that the laminated channel structure of In0.3Ga0.7As/In0.7Ga0.3As/In0.3Ga0.7As (WITH BUFFER) maintained high mobility even if the channel layer was thinner, as compared with the single-layer structure (WITHOUT BUFFER).FIG. 20also shows that the laminated channel structure achieved higher mobility than a bulk structure.

Second Working Example

Similarly to the first working example, an InGaAs layer was epitaxially grown by MOVPE on an InP wafer of the plane orientation (001), and an Al2O3layer was formed by ALD on the InGaAs layer. Another Al2O3layer was formed by ALD on a separate silicon wafer. The Al2O3layers formed on the InP wafer and the silicon wafer were subjected to hydrophilic treatment, the InP wafer was bonded to the silicon wafer, and InP was then selectively removed using a HCl solution. In this way, a semiconductor wafer constituted by the InGaAs layer, the Al2O3layer (BOX layer) and the silicon wafer was produced.

The surface of the InGaAs layer of the thus-produced semiconductor wafer was cleaned using acetone, NH4OH, (NH4)2S and subjected to sulfur-termination treatment. After this, an Al2O3layer having the thickness of 10 nm was formed using ALD on the InGaAs layer. A gate electrode made of tantalum was formed by sputtering and subjected to post-metallization annealing, after which a nickel film having the thickness of 20 nm was formed. The nickel film was subjected to RTA at the temperature of 250° C., to form a source and a drain (S/D) using a Ni—InGaAs alloy. In this way, a field-effect transistor was produced. The gate length L of the field-effect transistor was 5 μm and the gate width W was 100 μm.

Four sample field-effect transistors (6) to (9) were produced that differ from each other in terms of the InGaAs layer as follows.

(6) A laminate constituted by In0.3Ga0.7As/InAs/In0.3Ga0.7As having the thicknesses of 3/3/3 nm

(7) A laminate constituted by In0.3Ga0.7As/In0.7Ga0.3As/In0.3Ga0.7As having the thicknesses of 3/5/3 nm

In the following description made with reference toFIGS. 21 to 23, the samples (8) and (9) may be referred to using the terms such as “without buffer” or “single channel,” and the samples (6) and (7) may be referred to using the term “with buffer.” The thickness of the InGaAs layer may be referred to as “the thickness of the body,” and the thickness of the In0.7Ga0.3As layer or the In0.53Ga0.47As layer may be referred to as “the thickness of the channel” in relation to the samples (8) and (9).

FIG. 21is a TEM photograph showing the cross-section of the sample (6). Even when the channel layer was made of InAs, the respective layers were appropriately formed as in the first working example, and the Ni—InGaAs alloy under the gate overlapped the gate to an appropriate extent. The source and the drain made of the Ni—InGaAs alloy were self-aligned.FIG. 22shows the Id-Vg characteristics of the sample (6). Even when the channel layer was made of InAs, the sample (6) operated appropriately as a transistor as in the first working example.

FIG. 23shows the relation between the mobility and the charge density Ns at a room temperature for the samples (6) to (9). The mobility of the samples (6) and (7) having a laminated channel was higher than the mobility of the samples (8) and (9) having a single-layer channel. The mobility of the sample (6), in which a layer equivalent to the first crystal layer108has an indium proportion of 1, was higher than the mobility of the sample (7), in which a layer equivalent to the first crystal layer108has an indium proportion of 0.7. Thus, as the indium proportion increases, the mobility can accordingly increase. The maximum mobility of the sample (6) reaches 3180 cm2/Vs. This was the first time that an ultrathin-body (UTB) InAs-composite OI channel having the thickness of 10 nm or less achieved a mobility of 3180 cm2/Vs.

Third Working Example

Similarly to the first working example, an InGaAs layer was epitaxially grown by MOVPE on an InP wafer of the plane orientation (001), and an Al2O3layer was formed by ALD on the InGaAs layer. Another Al2O3layer was formed by ALD on a separate silicon wafer. The Al2O3layers formed on the InP wafer and the silicon wafer were subjected to hydrophilic treatment, the InP wafer was bonded to the silicon wafer, and InP was then selectively removed using a HCl solution. In this way, a semiconductor wafer constituted by the InGaAs layer, the Al2O3layer (BOX layer) and the silicon wafer was produced.

The surface of the InGaAs layer of the thus-produced semiconductor wafer was cleaned using acetone, NH4OH, (NH4)2S and subjected to sulfur-termination treatment. After this, an Al2O3layer having the thickness of 10 nm was formed using ALD on the InGaAs layer. A gate electrode made of tantalum was formed by sputtering and electron beam lithography. The width of the gate electrode was set to approximately 200 nm, and microfabrication was implemented. After post-metallization annealing was performed, a20nm thick nickel film was formed. The nickel film was subjected to RTA at the temperature of 250° C., to form a source and a drain (S/D) made of Ni—InGaAs alloy. The source and the drain were laterally (horizontally) extended through thermal reaction between the InGaAs layer and the nickel film, so that the boundaries of the source and the drain regions that oppose each other were formed under the gate electrode. In this way, a field-effect transistor was produced. The gate length L of the field-effect transistor was approximately 55 nm.

Two sample field-effect transistors (10) and (11) were produced that differ from each other in terms of the InGaAs layer as follows.

(10) A laminate constituted by In0.3Ga0.7As/InAs/In0.3Ga0.7As having the thicknesses of 3/3/3 nm

In the following description made with reference toFIGS. 24 to 37, the sample (11) may be referred to using the terms such as “without buffer” or “single channel,” and the sample (10) may be referred to using the term “with buffer.” The thickness of the InGaAs layer may be referred to as “the thickness of the body” and the thickness of the In0.53Ga0.47As layer may be referred to as “the thickness of the channel” in relation to the sample (11).

FIGS. 24 and 25are each a TEM photograph showing the cross-section of the sample (10). As in the first working example, the respective layers were appropriately formed.FIG. 25shows that the overlapping portion of the Ni—InGaAs alloy was positioned in the InGaAs layer under the gate. The length of the overlapping portion from the edge of the gate was approximately several dozen nanometers. If the width of the gate electrode is several hundred nanometers and the length of the overlapping portion is controlled by the temperature or duration of the thermal treatment, the gate length of the transistor (the distance between the source and the drain) can be controlled precisely and easily. In addition, it was confirmed that the source and the drain made of the Ni—InGaAs alloy were formed in self-alignment. In the above-described manner, a planar MOSFET having a channel length of 100 nm or less can be easily produced.

FIG. 26shows the Id-Vg characteristics of the sample (10).FIG. 27shows the Id-Vg characteristics of the sample (10). It was proved that a MOSFET having an InAs laminated channel on an insulator layer and a fine gate length of 55 nm had excellent transistor characteristics.

FIG. 28shows how the S.S. value (the subthreshold swing value) of the sample (11) is dependent on the channel length, andFIG. 29shows how the DIBL (drain induced barrier lowering) value of the sample (11) is dependent on the channel length. InFIGS. 28 and 29, the dependency observed when the thickness of the Al2O3layer serving as a gate insulator was set at 6 nm and 12 nm were shown for the comparison purpose. The S.S. value is smaller when the Al2O3layer has the thickness of 6 nm than when the Al2O3layer has the thickness of 12 nm. This is probably because the channel is advantageously positioned closer to the gate electrode. The DIBL value is smaller when the Al2O3layer has the thickness of 6 nm than when the Al2O3layer has the thickness of 12 nm. This proves that the transistor performance may be improved by reducing (scaling) the effective oxide thickness (EOT).

FIGS. 30 to 35respectively show, for the samples (10) and (11), how the threshold voltage (Vth) is dependent on the channel length (FIG. 30), how the S.S. value is dependent on the channel length (FIG. 31), how the DIBL value is dependent on the channel length (FIG. 32), the on-current/off-current characteristics (FIG. 33), how the on-current is dependent on the DIBL value (FIG. 34), and how the total resistance value between the source and the drain is dependent on the channel length (FIG. 35). Here, the threshold was defined as the gate voltage when the drain current was 10−6μA/μm, and the DIBL value was evaluated by how the threshold varies depending on the drain voltage.

FIG. 31shows that neither a rapid change in the threshold value (roll-off) nor a shift of the threshold value into a minus bias is seen for both of the samples (10) and (11). Since the phenomena such as the roll-off are caused by the short channel effects, it was confirmed that the short channel effects were restrained. The short channel effects were restrained probably because an OI structure was obtained by forming a transistor on an insulator layer (BOX layer), which proved that the OI structure was advantageous.

FIGS. 32 and 33show that excellent S.S. and DIBL values are obtained for a short-channel MOSFET having a channel length of approximately several hundred nanometers. When the channel length is 100 nm or less, the sample (10) has a lower DIBL value and considered to be a better choice. It was confirmed that an InAs laminated channel structure (the sample (10)) was advantageous when the channel is short.

FIG. 34shows that the on-current of the sample (10) was approximately four times as high as the on-current of the sample (11) (when the off-current is 1 nA/μm).

FIG. 35shows that the on-current of the sample (10) was approximately four times as high as the on-current of the sample (11) (when they have the same DIBL value).

FIG. 35shows that the parasitic resistance between the source and the drain for the sample (10) was 1.16 kg·μm and that the parasitic resistance between the source and the drain for the sample (11) was 5.54 kg·μm. Here, the parasitic resistance between the source and the drain is defined as the total resistance value Rtotbetween the source and the drain observed when the channel length Lchis zero. Thus, the parasitic resistance of the sample (10) is approximately five times less than the parasitic resistance of the sample (11).

FIG. 36shows how the S.S. value of the field-effect transistor is dependent on the channel length for the samples (10) and (11) and first, second and fourth referential examples.FIG. 37shows how the DIBL value of the field-effect transistor is dependent on the channel length for the sample (10) and the first to fourth referential examples. Table 1 compares the main constituents and characteristics of the sample (10), which is the third working example and the first to fourth referential examples.

Here, the first to fourth referential examples are the transistors disclosed in the following documents and respectively have a three-dimensional gate structure such as a tri-gate structure, a fin structure, or a gate-all-around structure.

FIGS. 36 and 37and Table 1 indicate that the sample (10) is a MOSFET having a planar gate structure but achieves as high performance as or higher performance than a transistor with a3D gate structure.

As used herein, the sentence “a first element such as a layer, a region or a wafer is on a second element” means that the first element is directly on the second element and also means that the first element is indirectly on the second element with another element being provided between the first element and the second element. Furthermore, the expression “the portion of the semiconductor layer106exposed though the opening” means a portion of the semiconductor layer106that forms the bottom of the opening. When the field-effect transistor is an n-channel field-effect transistor, the relation between the electron affinities of the layers described herein may be reversed.

DESCRIPTION OF REFERENCE NUMERALS