Semiconductor device, semiconductor package, interposer, semiconductor device manufacturing method and interposer manufacturing method

A semiconductor device includes an interposer having a base member including a first surface and a second surface opposite to the first surface, a first interconnect formed on the first surface of the base member, a first insulating film formed on the first surface of the base member, a first external terminal and a second external terminal neighboring the first external terminal formed on the second surface of the base member, a second interconnect formed on the second surface of the base member and passing between the first external terminal and the second external terminal, and a second insulating film formed on the second surface of the base member, a semiconductor chip mounted on the first insulating film, a sealing resin formed on the first insulating film and sealing the semiconductor chip. The second insulating film has an opening so that the second interconnect is exposed in an area.

BACKGROUND

1. Field of the Invention

The present invention relates to a semiconductor device in which a semiconductor package with an interposer is mounted over an interconnection substrate, a semiconductor package, an interposer, a semiconductor device manufacturing method, and an interposer manufacturing method.

2. Description of Related Art

For example, BGA packages and LGA packages are semiconductor packages. Semiconductor packages are anticipated to provide high reliability, particularly long-term reliability such as temperature cyclicity. If the temperature of a semiconductor device in which a semiconductor package is mounted over a printed wiring board changes, thermal stress generated due to the difference in thermal expansion coefficient between the printed wiring board and semiconductor package may affect a solder ball and cause a crack in the joint of the solder ball and an external coupling terminal of the package substrate or printed wiring board, resulting in a disconnection. Among techniques of preventing such disconnection are the techniques disclosed in Japanese Unexamined Patent Publication No. Hei 10(1998)-313167 and Japanese Unexamined Patent Publication No. 2003-023243.

These techniques use an NSMD structure in order to prevent solder balls from running on a solder resist layer. The techniques eliminate a notch which may cause cracking and also reduce the possibility that a molten solder ball spreads over a wire from an external coupling terminal and runs on the solder resist layer.

The technique described in Japanese Unexamined Patent Publication No. Hei 10(1998)-313167 uses an NSMD structure to decrease the width of the exposed portion of an interconnect wire. The technique described in Japanese Unexamined Patent Publication No. 2003-023243 uses an NSMD structure in which the exposed portion of an interconnect wire is covered by a solder resist layer. These techniques are described as further reducing the possibility that thermal stress of a solder ball is directly applied to the interconnect wire and disconnection of the interconnect wire occurs.

SUMMARY

However, the present inventors have found that a difference in thermal expansion coefficient as mentioned above may cause cracking in a solder resist layer covering the surface of an interposer between external coupling terminals and such cracking may lead to a wire disconnection. The inventors have also found it difficult for the above two conventional techniques to prevent disconnection of an interconnect wire passing between external coupling terminals.

According to a first aspect of the present invention, there is provided a semiconductor device which includes an interposer having a base member including a first surface and a second surface opposite to the first surface, a first interconnect formed on the first surface of the base member, a first insulating film formed on the first surface of the base member, a first external terminal and a second external terminal neighboring the first external terminal formed on the second surface of the base member, a second interconnect formed on the second surface of the base member and passing between the first external terminal and the second external terminal, and a second insulating film formed on the second surface of the base member, a semiconductor chip mounted on the first insulating film, a sealing resin formed on the first insulating film and sealing the semiconductor chip, wherein the second insulating film has an opening so that the second interconnect is exposed in an area where the second interconnect intersects with a line connecting centers of the first external terminal and the second external terminal.

According to the present invention, the possibility of disconnection of an interconnect wire passing between external coupling terminals in an interposer is reduced.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Next, the preferred embodiments of the present invention will be described in detail referring to the accompanying drawings. In all the drawings, the same elements are designated by the same reference numerals and repeated descriptions of such elements are omitted.

FIG. 1is a sectional view showing the structure of a semiconductor device1according to a first embodiment of the invention. The semiconductor device1includes an interconnection substrate10, a semiconductor package200, and an underfill resin layer100. The semiconductor package200includes a semiconductor chip250and an interposer210. The interposer210has the semiconductor chip250mounted over one surface thereof and a plurality of external coupling terminals240and an interconnect wire230formed over the other surface and is covered by a solder resist layer220. The semiconductor package200is mounted over the interconnection substrate10, for example, through solder balls110. The underfill resin layer100seals the space between the semiconductor package200and interconnection substrate10. In an area where the interconnect wire230passing between two neighboring external coupling terminals240intersects with a line connecting the centers of the neighboring external coupling terminals240, the interconnect wire230is not covered by the solder resist layer220.

The semiconductor package200further includes a mount member251and a mold resin252. The semiconductor chip250is mounted over the interposer210through the mount member251in a way that its active side is opposite to the interposer210. Electrode pads (not shown) are formed on the active side of the semiconductor chip250. These electrode pads are coupled to bonding pads271of the semiconductor package200by bonding wires270. The mold resin252seals the semiconductor chip250, the bonding wires270and the interposer210's surface bearing the semiconductor chip250.

The interposer210includes a base member211, a solder resist layer215and interconnect wire236which are formed on its surface to bear the semiconductor chip250, and a solder resist layer220and interconnect wires230which are formed on its surface to be joined to the interconnection substrate10. For example, the base member211is a glass epoxy board. The bonding pads271are provided on the interposer210's surface to bear the semiconductor chip250and the external coupling terminals240and through holes310as shown inFIG. 2are formed on its surface to be joined to the interconnection substrate10. A conductor for coupling an interconnect wire230to the interconnect wire236is provided on the sidewall of each through hole310. The through holes310are filled with the solder resist layer220. For example, the underfill resin layer100is an epoxy resin layer. For example, the semiconductor package200is a BGA package like the one shown inFIG. 1.

FIG. 2is a plan view of the interposer210's surface to be joined to the interconnection substrate10before attachment of the solder balls110to the surface.FIG. 1is a sectional view taken along the line A-A′ ofFIG. 2. The external coupling terminals240to which the solder balls110are attached are circular and two-dimensionally arranged, for example, in a grid pattern. A particular external coupling terminal242is coupled to a through hole312by an interconnect wire232. A particular external coupling terminal244is coupled to a through hole314by an interconnect wire234. The other external coupling terminals240are also coupled to through holes in the same way (not shown). The solder resist layer220has the shape of a ring and lies in the peripheral area of each external coupling terminal240and its vicinity. The solder resist layer220and external coupling terminal240are concentric with each other. The diameter of a solder resist opening222is smaller than that of an external coupling terminal240. No solder resist layer220is formed over an interconnect wire230passing between external coupling terminals240.

FIGS. 3A to 3Dare sectional views showing the processes of manufacturing the interposer210shown inFIGS. 1 and 2. First, as shown inFIG. 3A, an interconnect wire236and interconnect wires230are formed on the front and back surfaces of the base member211respectively by patterning. Next, solder resist layers215and220are formed on the front and back surfaces respectively (FIG. 3B), then the solder resist layers215and220are selectively removed by photographic exposure and development processes to form a pattern as shown inFIG. 2(FIG. 3C). Electrolytic Ni/Au coatings330and336are made over the exposed interconnect wires230and wire236using an electrolytic Ni/Au coating method (FIG. 3D). The interposer210is thus completed.

After that, the semiconductor chip250is mounted over the interposer210through the mount member251. Then, the interposer210and semiconductor chip250are coupled to each other by the bonding wires270. Then, the interposer210, semiconductor chip250, and bonding wires270are sealed with mold resin252. The semiconductor package200is thus completed.

After that, a solder ball110is attached to the semiconductor package200as shown inFIG. 6. The semiconductor package200and interconnection substrate10are joined through the solder balls110. Then, the semiconductor package200is mounted over the interconnection substrate10and an underfill resin layer100is filled in the space between the semiconductor package200and interconnection substrate10to form the semiconductor device1as shown inFIG. 1.

Next, the effect of this embodiment will be explained referring toFIGS. 1 and 7. In the semiconductor package200mounted over the interconnection substrate10, a solder resist crack221may occur in the solder resist layer220's area in contact with the underfill resin layer100. It is thought that this occurs because thermal stress generated due to the difference in thermal expansion coefficient between the interconnection substrate10and semiconductor package200causes them to warp. As shown inFIG. 7, a solder resist crack221tends to occur in a narrow space between external coupling terminals240in the solder resist layer220. Also, a solder resist crack221tends to occur in an area which overlaps the vicinity of an edge of the semiconductor chip250because expansion and contraction of the interposer210are restricted by the semiconductor chip250.

In this embodiment, an interconnect wire230passing between external coupling terminals240is not covered by the solder resist layer220. This means that a solder resist crack221never occurs on the interconnect wire230. Therefore, disconnection of the interconnect wire230passing between the external coupling terminals240is prevented, thereby reducing the possibility of deterioration in the reliability of the semiconductor package200.

Cracking hardly propagates inside the interposer210made of glass cloth impregnated with resin, so propagation of cracking into the interposer210is suppressed. Furthermore, the underfill resin layer100filled in the space between the semiconductor package200and interconnection substrate10prevents short-circuiting which can be caused by exposure of the interconnect wire230.

FIG. 4is a sectional view showing the structure of a semiconductor device2according to a second embodiment of the invention, as a counterpart ofFIG. 1which shows the first embodiment.FIG. 5is a plan view of the interposer210's surface to be joined to the interconnection substrate10before attachment of the solder balls110to the surface in the semiconductor package201according to the second embodiment, as a counterpart ofFIG. 2which shows the first embodiment.FIG. 4is a sectional view taken along the line A-A′ ofFIG. 5. The semiconductor device2and semiconductor package201according to the second embodiment are structurally the same as the semiconductor device1and semiconductor package200according to the first embodiment, except the pattern of the solder resist layer220. The manufacturing method for the interposer210according to the second embodiment is the same as that for the interposer210according to the first embodiment.

As shown inFIG. 5, in the interposer210according to the second embodiment, a solder resist layer220is formed on the interposer210's surface opposite to the interconnection substrate10except the areas of solder resist openings223over external coupling terminals240and solder resist openings222. Each solder resist opening223lies over an external coupling terminal240. Each solder resist opening222is formed over an interconnect wire234between external coupling terminals240. Each interconnect wire234is passed between external coupling terminals240arranged along an edge of the semiconductor chip250.

Since the semiconductor chip250restricts expansion and contraction of the interposer210, a solder resist crack due to the difference in thermal expansion coefficient tends to occur in an area which overlaps the vicinity of an edge of the semiconductor chip250. According to the second embodiment, a solder resist opening222is provided over an interconnect wire230passing between external coupling terminals240of the interposer210, arranged along an edge of the semiconductor chip250, and the solder resist layer220does not lie over the interconnect wire230. Therefore, the same effect as in the first embodiment can be achieved in an area over each interconnect wire230passing between external coupling terminals240arranged along an edge of the semiconductor chip250.

Furthermore, since the areas except the openings222and openings223are covered by the solder resist layer220, the total area of electrolytic Ni/Au coatings330as shown inFIG. 3is smaller than in the first embodiment. Consequently the semiconductor package manufacturing cost is lower. In addition, adhesion of foreign matter to interconnect wires is reduced during the semiconductor package manufacturing process.

FIG. 8is a sectional view showing the structure of a semiconductor device3according to a third embodiment of the invention, as a counterpart ofFIG. 1which shows the first embodiment. The semiconductor device3according to the third embodiment is structurally the same as the semiconductor device1according to the first embodiment, except that the semiconductor package202is an LGA package.

In the second embodiment as well, the solder resist layer220does not lie over an interconnect wire230passing between external coupling terminals240of the interposer210, so the same effect as in the first embodiment can be achieved.

FIG. 9is a sectional view showing the structure of a semiconductor device4according to a fourth embodiment of the invention, as a counterpart ofFIG. 1which shows the first embodiment. The semiconductor device4according to the fourth embodiment is structurally the same as the semiconductor device1according to the first embodiment, except that the semiconductor chip250is flip-chip coupled to the interposer210in the semiconductor package203.

More specifically, the semiconductor chip250is mounted over the interposer210through bumps120with its active side facing the interposer210. In the fourth embodiment as well, the solder resist layer220does not lie over an interconnect wire230passing between external coupling terminals240of the interposer210, so the same effect as in the first embodiment can be achieved.

The preferred embodiments of the present invention have been so far described referring to the accompanying drawings. These embodiments are just illustrative of the invention. The invention can be embodied in other various forms.